From 2731b2eadeaa141e6f305fa8086106608112bbaa Mon Sep 17 00:00:00 2001 From: Roshni Shah Date: Mon, 14 Mar 2011 06:49:42 -0400 Subject: Add support for the i.MX53 QSB This patch seems to have originated from the 11.01.00 release from Freescale, which is no longer available except through the gitweb interface from Freescale. http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=commit;h=27fdf7bae11978d21e8aba09bb635f49b07edd4a --- Documentation/arm/Booting | 1 + Documentation/imx_nfc.txt | 369 + arch/arm/Kconfig | 39 +- arch/arm/Makefile | 3 + arch/arm/boot/compressed/Makefile | 1 + arch/arm/boot/compressed/head.S | 53 + arch/arm/configs/imx23evk_defconfig | 2053 + arch/arm/configs/imx23evk_updater_defconfig | 1474 + arch/arm/configs/imx25_3stack_defconfig | 2109 + arch/arm/configs/imx25_updater_defconfig | 1337 + arch/arm/configs/imx28evk_defconfig | 2133 + arch/arm/configs/imx28evk_updater_defconfig | 1473 + arch/arm/configs/imx5_defconfig | 2486 + arch/arm/configs/imx5_updater_defconfig | 1871 + arch/arm/configs/mx3_defconfig | 1426 +- arch/arm/configs/mx3_updater_defconfig | 1321 + arch/arm/include/asm/hardware/cache-l2x0.h | 2 + arch/arm/include/asm/mach/flash.h | 1 + arch/arm/include/asm/mach/keypad.h | 29 + arch/arm/include/asm/memory.h | 5 + arch/arm/include/asm/pgtable.h | 2 + arch/arm/kernel/head.S | 31 +- arch/arm/kernel/setup.c | 10 +- arch/arm/mach-mx23/Kconfig | 25 + arch/arm/mach-mx23/Makefile | 15 + arch/arm/mach-mx23/Makefile.boot | 3 + arch/arm/mach-mx23/bus_freq.c | 170 + arch/arm/mach-mx23/clock.c | 1596 + arch/arm/mach-mx23/device.c | 1066 + arch/arm/mach-mx23/device.h | 34 + arch/arm/mach-mx23/emi.S | 254 + arch/arm/mach-mx23/emi.inc | 667 + arch/arm/mach-mx23/gpio.c | 190 + arch/arm/mach-mx23/include/mach/dma.h | 59 + arch/arm/mach-mx23/include/mach/irqs.h | 102 + arch/arm/mach-mx23/include/mach/lcdif.h | 441 + arch/arm/mach-mx23/include/mach/mx23.h | 98 + arch/arm/mach-mx23/include/mach/regs-apbh.h | 358 + arch/arm/mach-mx23/include/mach/regs-audioin.h | 287 + arch/arm/mach-mx23/include/mach/regs-audioout.h | 518 + arch/arm/mach-mx23/include/mach/regs-emi.h | 234 + arch/arm/mach-mx23/include/mach/regs-i2c.h | 383 + arch/arm/mach-mx23/include/mach/regs-lcdif.h | 650 + arch/arm/mach-mx23/include/mach/regs-lradc.h | 669 + arch/arm/mach-mx23/include/mach/regs-ocotp.h | 311 + arch/arm/mach-mx23/include/mach/regs-power.h | 564 + arch/arm/mach-mx23/include/mach/regs-pwm.h | 135 + arch/arm/mach-mx23/include/mach/regs-pxp.h | 517 + arch/arm/mach-mx23/include/mach/regs-rtc.h | 219 + arch/arm/mach-mx23/include/mach/regs-ssp.h | 392 + arch/arm/mach-mx23/include/mach/regs-timrot.h | 257 + arch/arm/mach-mx23/include/mach/regulator.h | 30 + arch/arm/mach-mx23/mx23_pins.h | 156 + arch/arm/mach-mx23/mx23evk.c | 154 + arch/arm/mach-mx23/mx23evk.h | 32 + arch/arm/mach-mx23/mx23evk_pins.c | 939 + arch/arm/mach-mx23/otp.c | 437 + arch/arm/mach-mx23/pinctrl.c | 161 + arch/arm/mach-mx23/pm.c | 652 + arch/arm/mach-mx23/power.c | 525 + arch/arm/mach-mx23/regs-clkctrl.h | 442 + arch/arm/mach-mx23/regs-digctl.h | 724 + arch/arm/mach-mx23/regs-dram.h | 890 + arch/arm/mach-mx23/regs-pinctrl.h | 1879 + arch/arm/mach-mx23/serial.c | 161 + arch/arm/mach-mx23/sleep.S | 553 + arch/arm/mach-mx23/sleep.h | 125 + arch/arm/mach-mx23/usb.h | 109 + arch/arm/mach-mx23/usb_dr.c | 193 + arch/arm/mach-mx25/Kconfig | 75 + arch/arm/mach-mx25/Makefile | 16 +- arch/arm/mach-mx25/board-mx25_3stack.h | 175 + arch/arm/mach-mx25/bus_freq.c | 102 + arch/arm/mach-mx25/clock.c | 1674 +- arch/arm/mach-mx25/cpu.c | 63 + arch/arm/mach-mx25/crm_regs.h | 249 + arch/arm/mach-mx25/devices.c | 305 +- arch/arm/mach-mx25/dma.c | 663 + arch/arm/mach-mx25/iomux.c | 199 + arch/arm/mach-mx25/iomux.h | 233 + arch/arm/mach-mx25/mm.c | 2 +- arch/arm/mach-mx25/mx25_3stack.c | 848 + arch/arm/mach-mx25/mx25_3stack_cpld.c | 247 + arch/arm/mach-mx25/mx25_3stack_gpio.c | 1367 + arch/arm/mach-mx25/mx25_3stack_pmic_mc34704.c | 147 + arch/arm/mach-mx25/mx25_pins.h | 250 + arch/arm/mach-mx25/pm.c | 103 + arch/arm/mach-mx25/sdma_script_code.h | 158 + arch/arm/mach-mx25/serial.c | 332 + arch/arm/mach-mx25/serial.h | 148 + arch/arm/mach-mx25/system.c | 159 + arch/arm/mach-mx25/usb.h | 103 + arch/arm/mach-mx25/usb_dr.c | 138 + arch/arm/mach-mx25/usb_h2.c | 88 + arch/arm/mach-mx28/Kconfig | 25 + arch/arm/mach-mx28/Makefile | 15 + arch/arm/mach-mx28/Makefile.boot | 3 + arch/arm/mach-mx28/bus_freq.c | 190 + arch/arm/mach-mx28/clock.c | 1818 + arch/arm/mach-mx28/device.c | 1704 + arch/arm/mach-mx28/device.h | 34 + arch/arm/mach-mx28/emi.S | 220 + arch/arm/mach-mx28/emi_settings.c | 1263 + arch/arm/mach-mx28/emi_settings.h | 40 + arch/arm/mach-mx28/gpio.c | 196 + arch/arm/mach-mx28/include/mach/dma.h | 59 + arch/arm/mach-mx28/include/mach/lcdif.h | 276 + arch/arm/mach-mx28/include/mach/mx28.h | 245 + arch/arm/mach-mx28/include/mach/regs-apbh.h | 535 + arch/arm/mach-mx28/include/mach/regs-i2c.h | 498 + arch/arm/mach-mx28/include/mach/regs-icoll.h | 293 + arch/arm/mach-mx28/include/mach/regs-lcdif.h | 680 + arch/arm/mach-mx28/include/mach/regs-lradc.h | 772 + arch/arm/mach-mx28/include/mach/regs-ocotp.h | 239 + arch/arm/mach-mx28/include/mach/regs-power.h | 683 + arch/arm/mach-mx28/include/mach/regs-pwm.h | 147 + arch/arm/mach-mx28/include/mach/regs-pxp.h | 518 + arch/arm/mach-mx28/include/mach/regs-rtc.h | 226 + arch/arm/mach-mx28/include/mach/regs-ssp.h | 474 + arch/arm/mach-mx28/include/mach/regs-timrot.h | 293 + arch/arm/mach-mx28/include/mach/regulator.h | 30 + arch/arm/mach-mx28/mx28_pins.h | 164 + arch/arm/mach-mx28/mx28evk.c | 163 + arch/arm/mach-mx28/mx28evk.h | 28 + arch/arm/mach-mx28/mx28evk_pins.c | 1231 + arch/arm/mach-mx28/pinctrl.c | 175 + arch/arm/mach-mx28/pm.c | 367 + arch/arm/mach-mx28/power.c | 582 + arch/arm/mach-mx28/regs-clkctrl.h | 634 + arch/arm/mach-mx28/regs-digctl.h | 1022 + arch/arm/mach-mx28/regs-dram.h | 2505 + arch/arm/mach-mx28/regs-pinctrl.h | 2673 + arch/arm/mach-mx28/serial.c | 309 + arch/arm/mach-mx28/sleep.S | 698 + arch/arm/mach-mx28/sleep.h | 125 + arch/arm/mach-mx28/usb.h | 109 + arch/arm/mach-mx28/usb_dr.c | 570 + arch/arm/mach-mx28/usb_h1.c | 280 + arch/arm/mach-mx3/Kconfig | 60 + arch/arm/mach-mx3/Makefile | 24 +- arch/arm/mach-mx3/clock-imx31.c | 255 +- arch/arm/mach-mx3/clock-imx35.c | 26 +- arch/arm/mach-mx3/cpu.c | 37 + arch/arm/mach-mx3/crm_regs.h | 162 +- arch/arm/mach-mx3/devices-imx31.h | 37 + arch/arm/mach-mx3/devices-imx35.h | 43 + arch/arm/mach-mx3/devices.c | 186 +- arch/arm/mach-mx3/devices.h | 4 + arch/arm/mach-mx3/dma.c | 1270 + arch/arm/mach-mx3/dptc.c | 103 + arch/arm/mach-mx3/dummy_gpio.c | 119 + arch/arm/mach-mx3/dvfs-imx35.c | 609 + arch/arm/mach-mx3/entry-pm.S | 315 + arch/arm/mach-mx3/iomux.h | 186 + arch/arm/mach-mx3/mach-mx31_3ds.c | 270 +- arch/arm/mach-mx3/mach-mx31ads.c | 11 +- arch/arm/mach-mx3/mach-mx35_3ds.c | 433 + arch/arm/mach-mx3/mach-mx35pdk.c | 116 - arch/arm/mach-mx3/mx31_sdma_script_code_v1.h | 581 + arch/arm/mach-mx3/mx31_sdma_script_code_v2.h | 371 + arch/arm/mach-mx3/mx35_3ds-irq.c | 381 + arch/arm/mach-mx3/mx35_3ds_pesudo_irq.c | 372 + arch/arm/mach-mx3/mx35_3ds_pmic_mc13892.c | 392 + arch/arm/mach-mx3/mx35_3ds_pmic_mc9s08dz60.c | 105 + arch/arm/mach-mx3/mx35_sdma_script_code_v1.h | 254 + arch/arm/mach-mx3/mx35_sdma_script_code_v2.h | 234 + arch/arm/mach-mx3/mx3_3ds_pmic_mc13783.c | 273 + arch/arm/mach-mx3/mx3x-dma.c | 195 + arch/arm/mach-mx3/pm.c | 179 + arch/arm/mach-mx3/system.c | 93 + arch/arm/mach-mx5/Kconfig | 109 +- arch/arm/mach-mx5/Makefile | 16 +- arch/arm/mach-mx5/Makefile.boot | 12 +- arch/arm/mach-mx5/board-mx51_babbage.c | 10 +- arch/arm/mach-mx5/bus_freq.c | 1108 + arch/arm/mach-mx5/clock-mx51.c | 871 - arch/arm/mach-mx5/clock.c | 5140 ++ arch/arm/mach-mx5/clock_mx50.c | 3523 + arch/arm/mach-mx5/cpu.c | 205 +- arch/arm/mach-mx5/crm_regs.h | 669 +- arch/arm/mach-mx5/devices-imx51.h | 26 + arch/arm/mach-mx5/devices.c | 1882 +- arch/arm/mach-mx5/devices.h | 97 +- arch/arm/mach-mx5/dma-apbh.c | 225 + arch/arm/mach-mx5/dma-apbh.h | 35 + arch/arm/mach-mx5/dma.c | 1724 + arch/arm/mach-mx5/dmaengine.c | 682 + arch/arm/mach-mx5/dummy_gpio.c | 119 + arch/arm/mach-mx5/early_setup.c | 29 + arch/arm/mach-mx5/iomux.c | 268 + arch/arm/mach-mx5/iomux.h | 202 + arch/arm/mach-mx5/lpmodes.c | 308 + arch/arm/mach-mx5/mm.c | 85 +- arch/arm/mach-mx5/mx50_arm2.c | 1260 + arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c | 434 + arch/arm/mach-mx5/mx50_ddr_freq.S | 832 + arch/arm/mach-mx5/mx50_rdp.c | 1595 + arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c | 435 + arch/arm/mach-mx5/mx50_suspend.S | 234 + arch/arm/mach-mx5/mx50_wfi.S | 124 + arch/arm/mach-mx5/mx51_3stack.c | 1078 + arch/arm/mach-mx5/mx51_3stack_gpio.c | 852 + arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c | 370 + arch/arm/mach-mx5/mx51_babbage.c | 1325 + arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c | 436 + arch/arm/mach-mx5/mx51_pins.h | 409 + arch/arm/mach-mx5/mx53_ard.c | 1322 + arch/arm/mach-mx5/mx53_ard_pmic_ltc3589.c | 228 + arch/arm/mach-mx5/mx53_evk.c | 1562 + arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c | 351 + arch/arm/mach-mx5/mx53_loco.c | 839 + arch/arm/mach-mx5/mx53_loco_pmic_da9053.c | 270 + arch/arm/mach-mx5/mx53_smd.c | 1122 + arch/arm/mach-mx5/mx53_smd_pmic_da9053.c | 298 + arch/arm/mach-mx5/mx53_smd_rfkill.c | 136 + arch/arm/mach-mx5/mx53_wp.c | 159 + arch/arm/mach-mx5/mx53_wp.h | 43 + arch/arm/mach-mx5/pm.c | 300 + arch/arm/mach-mx5/pm_da9053.c | 385 + arch/arm/mach-mx5/regs-apbh.h | 512 + arch/arm/mach-mx5/sdma_script_code_mx50.h | 129 + arch/arm/mach-mx5/sdma_script_code_mx51.h | 256 + arch/arm/mach-mx5/sdma_script_code_mx53.h | 206 + arch/arm/mach-mx5/sdram_autogating.c | 201 + arch/arm/mach-mx5/serial.c | 282 + arch/arm/mach-mx5/serial.h | 71 + arch/arm/mach-mx5/suspend.S | 153 + arch/arm/mach-mx5/system.c | 316 + arch/arm/mach-mx5/usb.h | 48 + arch/arm/mach-mx5/usb_dr.c | 314 + arch/arm/mach-mx5/usb_h1.c | 252 + arch/arm/mach-mx5/usb_h2.c | 198 + arch/arm/mach-mx5/wfi.S | 426 + arch/arm/mm/cache-l2x0.c | 34 + arch/arm/mm/proc-v6.S | 16 + arch/arm/plat-mxc/3ds_debugboard.c | 205 + arch/arm/plat-mxc/Kconfig | 116 +- arch/arm/plat-mxc/Makefile | 35 +- arch/arm/plat-mxc/ahci_sata.c | 589 + arch/arm/plat-mxc/clock.c | 401 +- arch/arm/plat-mxc/cpu_common.c | 98 + arch/arm/plat-mxc/cpufreq.c | 330 + arch/arm/plat-mxc/devices.c | 33 + arch/arm/plat-mxc/devices/Kconfig | 18 + arch/arm/plat-mxc/devices/Makefile | 9 + arch/arm/plat-mxc/devices/platform-flexcan.c | 31 + arch/arm/plat-mxc/devices/platform-imx-i2c.c | 30 + arch/arm/plat-mxc/devices/platform-imx-mmc.c | 44 + arch/arm/plat-mxc/devices/platform-imx-uart.c | 154 + arch/arm/plat-mxc/devices/platform-mxc_nand.c | 45 + arch/arm/plat-mxc/devices/platform-spi_imx.c | 31 + arch/arm/plat-mxc/dptc.c | 640 + arch/arm/plat-mxc/dvfs_core.c | 994 + arch/arm/plat-mxc/dvfs_per.c | 936 + arch/arm/plat-mxc/gpio.c | 157 +- arch/arm/plat-mxc/include/mach/3ds_debugboard.h | 18 + arch/arm/plat-mxc/include/mach/arc_otg.h | 373 + arch/arm/plat-mxc/include/mach/audio_controls.h | 220 + arch/arm/plat-mxc/include/mach/board-mx35_3ds.h | 55 + arch/arm/plat-mxc/include/mach/board-mx35pdk.h | 22 - arch/arm/plat-mxc/include/mach/clock.h | 22 +- arch/arm/plat-mxc/include/mach/common.h | 15 +- arch/arm/plat-mxc/include/mach/debug-macro.S | 2 +- arch/arm/plat-mxc/include/mach/devices-common.h | 78 + arch/arm/plat-mxc/include/mach/dma.h | 305 + arch/arm/plat-mxc/include/mach/dmaengine.h | 515 + arch/arm/plat-mxc/include/mach/dptc.h | 186 + arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h | 169 + arch/arm/plat-mxc/include/mach/fsl_usb.h | 100 + arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h | 40 + arch/arm/plat-mxc/include/mach/gpio.h | 5 +- arch/arm/plat-mxc/include/mach/hardware.h | 61 +- arch/arm/plat-mxc/include/mach/hw_events.h | 65 + arch/arm/plat-mxc/include/mach/io.h | 42 +- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 6 +- arch/arm/plat-mxc/include/mach/iomux-mx35.h | 6 + arch/arm/plat-mxc/include/mach/iomux-mx50.h | 596 + arch/arm/plat-mxc/include/mach/iomux-mx51.h | 468 +- arch/arm/plat-mxc/include/mach/iomux-mx53.h | 763 + arch/arm/plat-mxc/include/mach/iomux-v3.h | 17 +- arch/arm/plat-mxc/include/mach/irqs.h | 21 +- arch/arm/plat-mxc/include/mach/memory.h | 47 +- arch/arm/plat-mxc/include/mach/mmc.h | 20 + arch/arm/plat-mxc/include/mach/mx25.h | 262 +- arch/arm/plat-mxc/include/mach/mx31.h | 19 + arch/arm/plat-mxc/include/mach/mx35.h | 66 +- arch/arm/plat-mxc/include/mach/mx3x.h | 54 +- arch/arm/plat-mxc/include/mach/mx51.h | 6 +- arch/arm/plat-mxc/include/mach/mx5x.h | 683 + arch/arm/plat-mxc/include/mach/mxc.h | 164 +- arch/arm/plat-mxc/include/mach/mxc_dptc.h | 111 + arch/arm/plat-mxc/include/mach/mxc_dvfs.h | 276 + arch/arm/plat-mxc/include/mach/mxc_edid.h | 40 + arch/arm/plat-mxc/include/mach/mxc_gpc.h | 74 + arch/arm/plat-mxc/include/mach/mxc_iim.h | 86 + arch/arm/plat-mxc/include/mach/mxc_pm.h | 252 + arch/arm/plat-mxc/include/mach/mxc_rfkill.h | 28 + arch/arm/plat-mxc/include/mach/mxc_scc.h | 45 + arch/arm/plat-mxc/include/mach/mxc_timer.h | 158 + arch/arm/plat-mxc/include/mach/mxc_uart.h | 275 + arch/arm/plat-mxc/include/mach/mxc_vpu.h | 94 + arch/arm/plat-mxc/include/mach/pcmcia.h | 218 + arch/arm/plat-mxc/include/mach/pmic_audio.h | 2315 + arch/arm/plat-mxc/include/mach/pmic_convity.h | 873 + arch/arm/plat-mxc/include/mach/pmic_power.h | 1358 + arch/arm/plat-mxc/include/mach/sdma.h | 572 + arch/arm/plat-mxc/include/mach/sdram_autogating.h | 56 + arch/arm/plat-mxc/include/mach/system.h | 15 +- arch/arm/plat-mxc/include/mach/timex.h | 6 +- arch/arm/plat-mxc/include/mach/uncompress.h | 11 + arch/arm/plat-mxc/io.c | 42 + arch/arm/plat-mxc/iomux-v3.c | 67 +- arch/arm/plat-mxc/iram.c | 67 + arch/arm/plat-mxc/irq.c | 144 +- arch/arm/plat-mxc/isp1301xc.c | 290 + arch/arm/plat-mxc/isp1504xc.c | 279 + arch/arm/plat-mxc/mc13783_xc.c | 299 + arch/arm/plat-mxc/pwm.c | 41 +- arch/arm/plat-mxc/sdma/Makefile | 18 + arch/arm/plat-mxc/sdma/dma_sdma.c | 697 + arch/arm/plat-mxc/sdma/iapi/Makefile | 5 + arch/arm/plat-mxc/sdma/iapi/include/epm.h | 191 + arch/arm/plat-mxc/sdma/iapi/include/iapi.h | 47 + arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h | 126 + arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h | 132 + arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h | 76 + arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h | 60 + arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h | 52 + .../arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h | 41 + arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h | 92 + arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h | 509 + arch/arm/plat-mxc/sdma/iapi/src/Makefile | 18 + arch/arm/plat-mxc/sdma/iapi/src/iapiDefaults.c | 110 + arch/arm/plat-mxc/sdma/iapi/src/iapiHigh.c | 2750 + arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c | 151 + arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c | 503 + arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c | 644 + arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c | 52 + arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c | 64 + arch/arm/plat-mxc/sdma/sdma.c | 1548 + arch/arm/plat-mxc/sdma/sdma_malloc.c | 233 + arch/arm/plat-mxc/serialxc.c | 64 + arch/arm/plat-mxc/snoop.c | 133 + arch/arm/plat-mxc/system.c | 19 +- arch/arm/plat-mxc/time.c | 12 +- arch/arm/plat-mxc/tzic.c | 125 +- arch/arm/plat-mxc/usb_common.c | 922 + arch/arm/plat-mxc/usb_wakeup.c | 220 + arch/arm/plat-mxc/utmixc.c | 108 + arch/arm/plat-mxc/zq_calib.c | 436 + arch/arm/plat-mxs/Kconfig | 179 + arch/arm/plat-mxs/Makefile | 24 + arch/arm/plat-mxs/clock.c | 325 + arch/arm/plat-mxs/core.c | 137 + arch/arm/plat-mxs/cpufreq.c | 527 + arch/arm/plat-mxs/device.c | 831 + arch/arm/plat-mxs/dma-apbh.c | 243 + arch/arm/plat-mxs/dma-apbx.c | 205 + arch/arm/plat-mxs/dmaengine.c | 656 + arch/arm/plat-mxs/gpio.c | 225 + arch/arm/plat-mxs/icoll.c | 141 + arch/arm/plat-mxs/include/mach/arc_otg.h | 174 + arch/arm/plat-mxs/include/mach/bus_freq.h | 46 + arch/arm/plat-mxs/include/mach/clkdev.h | 25 + arch/arm/plat-mxs/include/mach/clock.h | 127 + arch/arm/plat-mxs/include/mach/ddi_bc.h | 715 + arch/arm/plat-mxs/include/mach/debug-macro.S | 42 + arch/arm/plat-mxs/include/mach/device.h | 195 + arch/arm/plat-mxs/include/mach/dmaengine.h | 518 + arch/arm/plat-mxs/include/mach/entry-macro.S | 36 + arch/arm/plat-mxs/include/mach/fsl_usb.h | 74 + arch/arm/plat-mxs/include/mach/fsl_usb_gadget.h | 46 + arch/arm/plat-mxs/include/mach/gpio.h | 63 + arch/arm/plat-mxs/include/mach/hardware.h | 53 + arch/arm/plat-mxs/include/mach/io.h | 38 + arch/arm/plat-mxs/include/mach/irqs.h | 44 + arch/arm/plat-mxs/include/mach/lradc.h | 61 + arch/arm/plat-mxs/include/mach/memory.h | 59 + arch/arm/plat-mxs/include/mach/pinctrl.h | 152 + arch/arm/plat-mxs/include/mach/power.h | 64 + arch/arm/plat-mxs/include/mach/system.h | 30 + arch/arm/plat-mxs/include/mach/timex.h | 23 + arch/arm/plat-mxs/include/mach/uncompress.h | 56 + arch/arm/plat-mxs/include/mach/unique-id.h | 30 + arch/arm/plat-mxs/include/mach/vmalloc.h | 19 + arch/arm/plat-mxs/iram.c | 67 + arch/arm/plat-mxs/lradc.c | 385 + arch/arm/plat-mxs/pinctrl.c | 215 + arch/arm/plat-mxs/regs-apbx.h | 433 + arch/arm/plat-mxs/regs-icoll.h | 293 + arch/arm/plat-mxs/regs-usbphy.h | 323 + arch/arm/plat-mxs/timer-match.c | 164 + arch/arm/plat-mxs/timer-nomatch.c | 195 + arch/arm/plat-mxs/unique-id.c | 199 + arch/arm/plat-mxs/usb_common.c | 426 + arch/arm/plat-mxs/usb_wakeup.c | 222 + arch/arm/plat-mxs/utmixc.c | 89 + arch/arm/tools/mach-types | 347 +- block/genhd.c | 17 + crypto/Kconfig | 8 + crypto/Makefile | 2 + crypto/cryptodev.c | 558 + drivers/Kconfig | 2 + drivers/Makefile | 3 + drivers/ata/Kconfig | 8 + drivers/ata/Makefile | 1 + drivers/ata/pata_fsl.c | 1041 + drivers/base/power/main.c | 40 +- drivers/base/power/power.h | 4 + drivers/block/brd.c | 7 +- drivers/bluetooth/Kconfig | 11 + drivers/bluetooth/Makefile | 2 + drivers/bluetooth/hci_ath.c | 386 + drivers/bluetooth/hci_ldisc.c | 8 +- drivers/bluetooth/hci_uart.h | 9 +- drivers/char/Kconfig | 39 + drivers/char/Makefile | 6 + drivers/char/fsl_otp.c | 240 + drivers/char/fsl_otp.h | 234 + drivers/char/hw_random/Kconfig | 24 + drivers/char/hw_random/Makefile | 2 + drivers/char/hw_random/fsl-rnga.c | 238 + drivers/char/hw_random/fsl-rngc.c | 414 + drivers/char/imx_sim.c | 1498 + drivers/char/mxc_iim.c | 644 + drivers/char/mxc_si4702.c | 1223 + drivers/char/mxs_viim.c | 175 + drivers/char/random.c | 2 + drivers/char/regs-ocotp-v2.h | 239 + drivers/crypto/Kconfig | 12 + drivers/crypto/Makefile | 1 + drivers/crypto/dcp.c | 1775 + drivers/crypto/dcp.h | 717 + drivers/crypto/dcp_bootstream_ioctl.h | 32 + drivers/dma/Kconfig | 9 + drivers/dma/Makefile | 1 + drivers/dma/pxp/Makefile | 2 + drivers/dma/pxp/pxp_device.c | 512 + drivers/dma/pxp/pxp_dma.c | 1520 + drivers/dma/pxp/regs-pxp.h | 949 + drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/da9052-gpio.c | 731 + drivers/hwmon/Kconfig | 39 + drivers/hwmon/Makefile | 6 + drivers/hwmon/da9052-adc.c | 644 + drivers/hwmon/isl29003.c | 439 + drivers/hwmon/max17135-hwmon.c | 173 + drivers/hwmon/mxc_mma7450.c | 788 + drivers/hwmon/mxc_mma8450.c | 390 + drivers/hwmon/mxc_mma8451.c | 371 + drivers/i2c-slave/Kconfig | 39 + drivers/i2c-slave/Makefile | 8 + drivers/i2c-slave/i2c_slave_client.c | 81 + drivers/i2c-slave/i2c_slave_core.c | 359 + drivers/i2c-slave/i2c_slave_device.c | 271 + drivers/i2c-slave/i2c_slave_device.h | 79 + drivers/i2c-slave/i2c_slave_ring_buffer.c | 185 + drivers/i2c-slave/i2c_slave_ring_buffer.h | 39 + drivers/i2c-slave/mxc_i2c_slave.c | 335 + drivers/i2c-slave/mxc_i2c_slave.h | 44 + drivers/i2c-slave/mxc_i2c_slave_reg.h | 41 + drivers/i2c/busses/Kconfig | 58 + drivers/i2c/busses/Makefile | 4 + drivers/i2c/busses/i2c-mxs.c | 611 + drivers/i2c/busses/i2c-mxs.h | 42 + drivers/i2c/busses/mxc_i2c.c | 808 + drivers/i2c/busses/mxc_i2c_hs.c | 553 + drivers/i2c/busses/mxc_i2c_hs_reg.h | 97 + drivers/i2c/busses/mxc_i2c_reg.h | 40 + drivers/input/evdev.c | 6 +- drivers/input/keyboard/Kconfig | 37 + drivers/input/keyboard/Makefile | 6 + drivers/input/keyboard/mc9s08dz60_keyb.c | 248 + drivers/input/keyboard/mpr084.c | 500 + drivers/input/keyboard/mpr121.c | 305 + drivers/input/keyboard/mxc_keyb.c | 1203 + drivers/input/keyboard/mxc_pwrkey.c | 156 + drivers/input/keyboard/mxs-kbd.c | 365 + drivers/input/misc/Kconfig | 10 + drivers/input/misc/Makefile | 2 +- drivers/input/misc/da9052_onkey.c | 148 + drivers/input/touchscreen/Kconfig | 59 + drivers/input/touchscreen/Makefile | 6 + drivers/input/touchscreen/da9052_tsi.c | 1449 + drivers/input/touchscreen/da9052_tsi_calibrate.c | 107 + drivers/input/touchscreen/da9052_tsi_filter.c | 489 + drivers/input/touchscreen/imx_adc_ts.c | 114 + drivers/input/touchscreen/max11801_ts.c | 351 + drivers/input/touchscreen/mxc_ts.c | 189 + drivers/input/touchscreen/mxs-ts.c | 464 + drivers/input/touchscreen/tsc2007.c | 9 + drivers/leds/Kconfig | 21 + drivers/leds/Makefile | 3 + drivers/leds/leds-da9052.c | 307 + drivers/leds/leds-mc13892.c | 153 + drivers/leds/leds-mxs-pwm.c | 217 + drivers/media/video/Kconfig | 50 + drivers/media/video/Makefile | 9 + drivers/media/video/mxc/capture/Kconfig | 125 + drivers/media/video/mxc/capture/Makefile | 44 + drivers/media/video/mxc/capture/adv7180.c | 1024 + drivers/media/video/mxc/capture/csi_v4l2_capture.c | 1466 + drivers/media/video/mxc/capture/fsl_csi.c | 287 + drivers/media/video/mxc/capture/fsl_csi.h | 198 + drivers/media/video/mxc/capture/ipu_csi_enc.c | 357 + drivers/media/video/mxc/capture/ipu_prp_enc.c | 530 + drivers/media/video/mxc/capture/ipu_prp_sw.h | 36 + drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c | 482 + .../media/video/mxc/capture/ipu_prp_vf_sdc_bg.c | 443 + drivers/media/video/mxc/capture/ipu_still.c | 268 + drivers/media/video/mxc/capture/mt9v111.c | 1076 + drivers/media/video/mxc/capture/mt9v111.h | 431 + drivers/media/video/mxc/capture/mxc_v4l2_capture.c | 2812 + drivers/media/video/mxc/capture/mxc_v4l2_capture.h | 207 + drivers/media/video/mxc/capture/ov2640.c | 1081 + drivers/media/video/mxc/capture/ov3640.c | 1499 + drivers/media/video/mxc/capture/ov5640.c | 1527 + drivers/media/video/mxc/capture/ov5642.c | 2105 + drivers/media/video/mxc/capture/sensor_clock.c | 97 + drivers/media/video/mxc/opl/Makefile | 5 + .../media/video/mxc/opl/hmirror_rotate180_u16.c | 259 + drivers/media/video/mxc/opl/opl.h | 162 + drivers/media/video/mxc/opl/opl_mod.c | 30 + drivers/media/video/mxc/opl/rotate270_u16.c | 285 + drivers/media/video/mxc/opl/rotate270_u16_qcif.S | 70 + drivers/media/video/mxc/opl/rotate90_u16.c | 220 + drivers/media/video/mxc/opl/rotate90_u16_qcif.S | 71 + drivers/media/video/mxc/opl/vmirror_u16.c | 46 + drivers/media/video/mxc/output/Kconfig | 28 + drivers/media/video/mxc/output/Makefile | 14 + .../media/video/mxc/output/mx31_v4l2_wvga_output.c | 1928 + drivers/media/video/mxc/output/mxc_pxp_v4l2.c | 1237 + drivers/media/video/mxc/output/mxc_pxp_v4l2.h | 82 + drivers/media/video/mxc/output/mxc_v4l2_output.c | 2793 + drivers/media/video/mxc/output/mxc_v4l2_output.h | 157 + drivers/media/video/mxs_pxp.c | 1414 + drivers/media/video/mxs_pxp.h | 158 + drivers/media/video/pxp.c | 1409 + drivers/media/video/pxp.h | 130 + drivers/media/video/videobuf-dma-contig.c | 4 +- drivers/mfd/Kconfig | 27 + drivers/mfd/Makefile | 9 + drivers/mfd/da9052-core.c | 521 + drivers/mfd/da9052-i2c.c | 377 + drivers/mfd/da9052-spi.c | 399 + drivers/mfd/ltc3589-i2c.c | 121 + drivers/mfd/max17135-core.c | 232 + drivers/mfd/wm8350-core.c | 3 +- drivers/misc/Kconfig | 18 + drivers/misc/Makefile | 4 + drivers/misc/mxs-perfmon.c | 395 + drivers/misc/mxs-persistent.c | 271 + drivers/misc/pmem.c | 1340 + drivers/misc/regs-perfmon.h | 189 + drivers/misc/uid_stat.c | 153 + drivers/mmc/card/Kconfig | 12 + drivers/mmc/card/Makefile | 1 + drivers/mmc/card/unifi_fs/Makefile | 2 + drivers/mmc/card/unifi_fs/fs_lx.c | 683 + drivers/mmc/card/unifi_fs/fs_sdio_api.h | 68 + drivers/mmc/core/mmc.c | 416 +- drivers/mmc/host/Kconfig | 54 + drivers/mmc/host/Makefile | 4 +- drivers/mmc/host/mx_sdhci.c | 2289 + drivers/mmc/host/mx_sdhci.h | 302 + drivers/mmc/host/mxc_mmc.c | 1534 + drivers/mmc/host/mxc_mmc.h | 124 + drivers/mmc/host/mxs-mmc.c | 1327 + drivers/mtd/Kconfig | 8 + drivers/mtd/Makefile | 1 + drivers/mtd/devices/Kconfig | 8 + drivers/mtd/devices/Makefile | 1 + drivers/mtd/devices/mxc_dataflash.c | 1037 + drivers/mtd/maps/Kconfig | 10 + drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/mxc_nor.c | 181 + drivers/mtd/mtd_blkdevs.c | 5 +- drivers/mtd/mtdchar.c | 1 + drivers/mtd/nand/Kconfig | 62 + drivers/mtd/nand/Makefile | 4 + drivers/mtd/nand/gpmi-nfc/Makefile | 10 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h | 550 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h | 557 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h | 567 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h | 416 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h | 421 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h | 511 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c | 898 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c | 664 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c | 625 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c | 918 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c | 1889 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c | 1929 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c | 59 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c | 330 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c | 80 + drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h | 588 + drivers/mtd/nand/imx_nfc.c | 8286 ++ drivers/mtd/nand/mxc_nand.c | 3 +- drivers/mtd/nand/mxc_nd.c | 1413 + drivers/mtd/nand/mxc_nd.h | 112 + drivers/mtd/nand/mxc_nd2.c | 1756 + drivers/mtd/nand/mxc_nd2.h | 718 + drivers/mtd/nand/nand_base.c | 19 +- drivers/mtd/nand/nand_device_info.c | 2413 + drivers/mtd/nand/nand_device_info.h | 152 + drivers/mtd/nand/nand_ids.c | 7 + drivers/mtd/ubiblock.c | 626 + drivers/mxc/Kconfig | 40 + drivers/mxc/Makefile | 18 + drivers/mxc/adc/Kconfig | 14 + drivers/mxc/adc/Makefile | 4 + drivers/mxc/adc/imx_adc.c | 1134 + drivers/mxc/adc/imx_adc_reg.h | 242 + drivers/mxc/amd-gpu/Kconfig | 13 + drivers/mxc/amd-gpu/Makefile | 31 + drivers/mxc/amd-gpu/common/gsl_cmdstream.c | 267 + drivers/mxc/amd-gpu/common/gsl_cmdwindow.c | 161 + drivers/mxc/amd-gpu/common/gsl_context.c | 74 + drivers/mxc/amd-gpu/common/gsl_debug_pm4.c | 1015 + drivers/mxc/amd-gpu/common/gsl_device.c | 694 + drivers/mxc/amd-gpu/common/gsl_drawctxt.c | 1828 + drivers/mxc/amd-gpu/common/gsl_driver.c | 329 + drivers/mxc/amd-gpu/common/gsl_g12.c | 1025 + drivers/mxc/amd-gpu/common/gsl_intrmgr.c | 305 + drivers/mxc/amd-gpu/common/gsl_log.c | 591 + drivers/mxc/amd-gpu/common/gsl_memmgr.c | 949 + drivers/mxc/amd-gpu/common/gsl_mmu.c | 1084 + drivers/mxc/amd-gpu/common/gsl_ringbuffer.c | 1169 + drivers/mxc/amd-gpu/common/gsl_sharedmem.c | 937 + drivers/mxc/amd-gpu/common/gsl_tbdump.c | 228 + drivers/mxc/amd-gpu/common/gsl_yamato.c | 924 + drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl | 327 + drivers/mxc/amd-gpu/common/pm4_microcode.inl | 815 + drivers/mxc/amd-gpu/include/api/gsl_displayapi.h | 86 + drivers/mxc/amd-gpu/include/api/gsl_klibapi.h | 136 + drivers/mxc/amd-gpu/include/api/gsl_libapi.h | 143 + drivers/mxc/amd-gpu/include/api/gsl_pm4types.h | 157 + drivers/mxc/amd-gpu/include/api/gsl_properties.h | 94 + drivers/mxc/amd-gpu/include/api/gsl_types.h | 479 + drivers/mxc/amd-gpu/include/api/gsl_utils.h | 43 + drivers/mxc/amd-gpu/include/gsl.h | 79 + drivers/mxc/amd-gpu/include/gsl_buildconfig.h | 55 + drivers/mxc/amd-gpu/include/gsl_cmdstream.h | 62 + drivers/mxc/amd-gpu/include/gsl_cmdwindow.h | 51 + drivers/mxc/amd-gpu/include/gsl_config.h | 221 + drivers/mxc/amd-gpu/include/gsl_context.h | 45 + drivers/mxc/amd-gpu/include/gsl_debug.h | 126 + drivers/mxc/amd-gpu/include/gsl_device.h | 152 + drivers/mxc/amd-gpu/include/gsl_display.h | 62 + drivers/mxc/amd-gpu/include/gsl_drawctxt.h | 118 + drivers/mxc/amd-gpu/include/gsl_driver.h | 106 + drivers/mxc/amd-gpu/include/gsl_hal.h | 151 + drivers/mxc/amd-gpu/include/gsl_halconfig.h | 49 + drivers/mxc/amd-gpu/include/gsl_intrmgr.h | 104 + drivers/mxc/amd-gpu/include/gsl_ioctl.h | 243 + drivers/mxc/amd-gpu/include/gsl_log.h | 74 + drivers/mxc/amd-gpu/include/gsl_memmgr.h | 122 + drivers/mxc/amd-gpu/include/gsl_mmu.h | 186 + drivers/mxc/amd-gpu/include/gsl_ringbuffer.h | 250 + drivers/mxc/amd-gpu/include/gsl_sharedmem.h | 110 + drivers/mxc/amd-gpu/include/gsl_tbdump.h | 38 + drivers/mxc/amd-gpu/include/reg/g12_reg.h | 41 + drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h | 291 + drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h | 3775 + drivers/mxc/amd-gpu/include/reg/yamato.h | 66 + .../amd-gpu/include/reg/yamato/10/yamato_enum.h | 1895 + .../amd-gpu/include/reg/yamato/10/yamato_genenum.h | 1703 + .../amd-gpu/include/reg/yamato/10/yamato_genreg.h | 3404 + .../amd-gpu/include/reg/yamato/10/yamato_mask.h | 5906 ++ .../amd-gpu/include/reg/yamato/10/yamato_offset.h | 590 + .../amd-gpu/include/reg/yamato/10/yamato_random.h | 223 + .../include/reg/yamato/10/yamato_registers.h | 14278 ++++ .../amd-gpu/include/reg/yamato/10/yamato_shift.h | 4183 + .../amd-gpu/include/reg/yamato/10/yamato_struct.h | 52421 +++++++++++++ .../amd-gpu/include/reg/yamato/10/yamato_typedef.h | 550 + .../mxc/amd-gpu/include/reg/yamato/10/yamatoix.h | 169 + .../amd-gpu/include/reg/yamato/14/yamato_enum.h | 1867 + .../amd-gpu/include/reg/yamato/14/yamato_genenum.h | 1674 + .../amd-gpu/include/reg/yamato/14/yamato_genreg.h | 3310 + .../mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h | 95 + .../amd-gpu/include/reg/yamato/14/yamato_mask.h | 5739 ++ .../amd-gpu/include/reg/yamato/14/yamato_offset.h | 581 + .../amd-gpu/include/reg/yamato/14/yamato_random.h | 221 + .../include/reg/yamato/14/yamato_registers.h | 13962 ++++ .../amd-gpu/include/reg/yamato/14/yamato_shift.h | 4078 + .../amd-gpu/include/reg/yamato/14/yamato_struct.h | 51151 ++++++++++++ .../amd-gpu/include/reg/yamato/14/yamato_typedef.h | 540 + .../amd-gpu/include/reg/yamato/22/yamato_enum.h | 1897 + .../amd-gpu/include/reg/yamato/22/yamato_genenum.h | 1703 + .../amd-gpu/include/reg/yamato/22/yamato_genreg.h | 3405 + .../mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h | 95 + .../amd-gpu/include/reg/yamato/22/yamato_mask.h | 5908 ++ .../amd-gpu/include/reg/yamato/22/yamato_offset.h | 591 + .../amd-gpu/include/reg/yamato/22/yamato_random.h | 223 + .../include/reg/yamato/22/yamato_registers.h | 14280 ++++ .../amd-gpu/include/reg/yamato/22/yamato_shift.h | 4184 + .../amd-gpu/include/reg/yamato/22/yamato_struct.h | 52433 +++++++++++++ .../amd-gpu/include/reg/yamato/22/yamato_typedef.h | 550 + drivers/mxc/amd-gpu/os/include/os_types.h | 138 + drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h | 813 + drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c | 661 + drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c | 579 + .../mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h | 142 + drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c | 976 + .../amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c | 269 + .../amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h | 90 + .../mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c | 221 + .../mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h | 46 + drivers/mxc/amd-gpu/platform/hal/linux/misc.c | 167 + drivers/mxc/asrc/Kconfig | 13 + drivers/mxc/asrc/Makefile | 4 + drivers/mxc/asrc/mxc_asrc.c | 1728 + drivers/mxc/bt/Kconfig | 13 + drivers/mxc/bt/Makefile | 4 + drivers/mxc/bt/mxc_bt.c | 128 + drivers/mxc/dam/Kconfig | 13 + drivers/mxc/dam/Makefile | 9 + drivers/mxc/dam/dam.c | 427 + drivers/mxc/dam/dam.h | 258 + drivers/mxc/dam/dam_v1.c | 617 + drivers/mxc/gps_ioctrl/Kconfig | 13 + drivers/mxc/gps_ioctrl/Makefile | 5 + drivers/mxc/gps_ioctrl/agpsgpiodev.c | 332 + drivers/mxc/gps_ioctrl/agpsgpiodev.h | 46 + drivers/mxc/hmp4e/Kconfig | 24 + drivers/mxc/hmp4e/Makefile | 9 + drivers/mxc/hmp4e/mxc_hmp4e.c | 812 + drivers/mxc/hmp4e/mxc_hmp4e.h | 70 + drivers/mxc/hw_event/Kconfig | 11 + drivers/mxc/hw_event/Makefile | 1 + drivers/mxc/hw_event/mxc_hw_event.c | 266 + drivers/mxc/ipu/Kconfig | 4 + drivers/mxc/ipu/Makefile | 5 + drivers/mxc/ipu/ipu_adc.c | 689 + drivers/mxc/ipu/ipu_calc_stripes_sizes.c | 374 + drivers/mxc/ipu/ipu_common.c | 1970 + drivers/mxc/ipu/ipu_csi.c | 238 + drivers/mxc/ipu/ipu_device.c | 696 + drivers/mxc/ipu/ipu_ic.c | 590 + drivers/mxc/ipu/ipu_param_mem.h | 176 + drivers/mxc/ipu/ipu_prv.h | 59 + drivers/mxc/ipu/ipu_regs.h | 396 + drivers/mxc/ipu/ipu_sdc.c | 357 + drivers/mxc/ipu/pf/Kconfig | 7 + drivers/mxc/ipu/pf/Makefile | 1 + drivers/mxc/ipu/pf/mxc_pf.c | 991 + drivers/mxc/ipu3/Kconfig | 5 + drivers/mxc/ipu3/Makefile | 4 + drivers/mxc/ipu3/ipu_calc_stripes_sizes.c | 374 + drivers/mxc/ipu3/ipu_capture.c | 851 + drivers/mxc/ipu3/ipu_common.c | 2644 + drivers/mxc/ipu3/ipu_device.c | 510 + drivers/mxc/ipu3/ipu_disp.c | 1884 + drivers/mxc/ipu3/ipu_ic.c | 833 + drivers/mxc/ipu3/ipu_param_mem.h | 570 + drivers/mxc/ipu3/ipu_prv.h | 102 + drivers/mxc/ipu3/ipu_regs.h | 669 + drivers/mxc/mcu_pmic/Kconfig | 17 + drivers/mxc/mcu_pmic/Makefile | 6 + drivers/mxc/mcu_pmic/max8660.c | 154 + drivers/mxc/mcu_pmic/max8660.h | 49 + drivers/mxc/mcu_pmic/mc9s08dz60.c | 197 + drivers/mxc/mcu_pmic/mc9s08dz60.h | 73 + drivers/mxc/mcu_pmic/mcu_pmic_core.c | 226 + drivers/mxc/mcu_pmic/mcu_pmic_core.h | 43 + drivers/mxc/mcu_pmic/mcu_pmic_gpio.c | 131 + drivers/mxc/mlb/Kconfig | 13 + drivers/mxc/mlb/Makefile | 5 + drivers/mxc/mlb/mxc_mlb.c | 1060 + drivers/mxc/pmic/Kconfig | 64 + drivers/mxc/pmic/Makefile | 7 + drivers/mxc/pmic/core/Makefile | 21 + drivers/mxc/pmic/core/mc13783.c | 380 + drivers/mxc/pmic/core/mc13892.c | 335 + drivers/mxc/pmic/core/mc34704.c | 329 + drivers/mxc/pmic/core/pmic-dev.c | 316 + drivers/mxc/pmic/core/pmic.h | 138 + drivers/mxc/pmic/core/pmic_common.c | 131 + drivers/mxc/pmic/core/pmic_core_i2c.c | 348 + drivers/mxc/pmic/core/pmic_core_spi.c | 303 + drivers/mxc/pmic/core/pmic_event.c | 236 + drivers/mxc/pmic/core/pmic_external.c | 100 + drivers/mxc/pmic/mc13783/Kconfig | 55 + drivers/mxc/pmic/mc13783/Makefile | 18 + drivers/mxc/pmic/mc13783/pmic_adc.c | 1541 + drivers/mxc/pmic/mc13783/pmic_adc_defs.h | 321 + drivers/mxc/pmic/mc13783/pmic_audio.c | 5873 ++ drivers/mxc/pmic/mc13783/pmic_battery.c | 1220 + drivers/mxc/pmic/mc13783/pmic_battery_defs.h | 81 + drivers/mxc/pmic/mc13783/pmic_convity.c | 2468 + drivers/mxc/pmic/mc13783/pmic_light.c | 2764 + drivers/mxc/pmic/mc13783/pmic_light_defs.h | 144 + drivers/mxc/pmic/mc13783/pmic_power.c | 3146 + drivers/mxc/pmic/mc13783/pmic_power_defs.h | 509 + drivers/mxc/pmic/mc13783/pmic_rtc.c | 544 + drivers/mxc/pmic/mc13783/pmic_rtc_defs.h | 47 + drivers/mxc/pmic/mc13892/Kconfig | 48 + drivers/mxc/pmic/mc13892/Makefile | 10 + drivers/mxc/pmic/mc13892/pmic_adc.c | 1073 + drivers/mxc/pmic/mc13892/pmic_battery.c | 797 + drivers/mxc/pmic/mc13892/pmic_light.c | 685 + drivers/mxc/security/Kconfig | 64 + drivers/mxc/security/Makefile | 11 + drivers/mxc/security/dryice-regs.h | 207 + drivers/mxc/security/dryice.c | 1123 + drivers/mxc/security/dryice.h | 287 + drivers/mxc/security/mxc_scc.c | 2386 + drivers/mxc/security/mxc_scc_internals.h | 498 + drivers/mxc/security/rng/Makefile | 35 + drivers/mxc/security/rng/des_key.c | 385 + drivers/mxc/security/rng/fsl_shw_hash.c | 84 + drivers/mxc/security/rng/fsl_shw_hmac.c | 83 + drivers/mxc/security/rng/fsl_shw_rand.c | 122 + drivers/mxc/security/rng/fsl_shw_sym.c | 317 + drivers/mxc/security/rng/fsl_shw_wrap.c | 1301 + drivers/mxc/security/rng/include/rng_driver.h | 134 + drivers/mxc/security/rng/include/rng_internals.h | 680 + drivers/mxc/security/rng/include/rng_rnga.h | 181 + drivers/mxc/security/rng/include/rng_rngc.h | 235 + drivers/mxc/security/rng/include/shw_driver.h | 2971 + drivers/mxc/security/rng/include/shw_hash.h | 96 + drivers/mxc/security/rng/include/shw_hmac.h | 82 + drivers/mxc/security/rng/include/shw_internals.h | 162 + drivers/mxc/security/rng/rng_driver.c | 1150 + drivers/mxc/security/rng/shw_driver.c | 2335 + drivers/mxc/security/rng/shw_dryice.c | 204 + drivers/mxc/security/rng/shw_hash.c | 328 + drivers/mxc/security/rng/shw_hmac.c | 145 + drivers/mxc/security/rng/shw_memory_mapper.c | 213 + drivers/mxc/security/sahara2/Kconfig | 35 + drivers/mxc/security/sahara2/Makefile | 47 + drivers/mxc/security/sahara2/fsl_shw_auth.c | 706 + drivers/mxc/security/sahara2/fsl_shw_hash.c | 186 + drivers/mxc/security/sahara2/fsl_shw_hmac.c | 266 + drivers/mxc/security/sahara2/fsl_shw_keystore.c | 837 + drivers/mxc/security/sahara2/fsl_shw_rand.c | 96 + drivers/mxc/security/sahara2/fsl_shw_sym.c | 281 + drivers/mxc/security/sahara2/fsl_shw_user.c | 137 + drivers/mxc/security/sahara2/fsl_shw_wrap.c | 967 + drivers/mxc/security/sahara2/include/adaptor.h | 113 + drivers/mxc/security/sahara2/include/diagnostic.h | 116 + .../mxc/security/sahara2/include/fsl_platform.h | 161 + drivers/mxc/security/sahara2/include/fsl_shw.h | 2515 + .../security/sahara2/include/fsl_shw_keystore.h | 475 + drivers/mxc/security/sahara2/include/linux_port.h | 1806 + .../sahara2/include/platform_abstractions.h | 15 + drivers/mxc/security/sahara2/include/portable_os.h | 1453 + .../security/sahara2/include/sah_driver_common.h | 102 + .../sahara2/include/sah_hardware_interface.h | 99 + .../sahara2/include/sah_interrupt_handler.h | 42 + drivers/mxc/security/sahara2/include/sah_kernel.h | 113 + .../security/sahara2/include/sah_memory_mapper.h | 79 + .../security/sahara2/include/sah_queue_manager.h | 63 + .../security/sahara2/include/sah_status_manager.h | 228 + drivers/mxc/security/sahara2/include/sahara.h | 2265 + .../mxc/security/sahara2/include/sahara2_kernel.h | 49 + drivers/mxc/security/sahara2/include/sf_util.h | 466 + drivers/mxc/security/sahara2/km_adaptor.c | 849 + .../mxc/security/sahara2/sah_driver_interface.c | 2185 + .../mxc/security/sahara2/sah_hardware_interface.c | 808 + .../mxc/security/sahara2/sah_interrupt_handler.c | 216 + drivers/mxc/security/sahara2/sah_memory_mapper.c | 2356 + drivers/mxc/security/sahara2/sah_queue.c | 249 + drivers/mxc/security/sahara2/sah_queue_manager.c | 1076 + drivers/mxc/security/sahara2/sah_status_manager.c | 714 + drivers/mxc/security/sahara2/sf_util.c | 1390 + drivers/mxc/security/scc2_driver.c | 2401 + drivers/mxc/security/scc2_internals.h | 519 + drivers/mxc/ssi/Kconfig | 12 + drivers/mxc/ssi/Makefile | 7 + drivers/mxc/ssi/registers.h | 208 + drivers/mxc/ssi/ssi.c | 1221 + drivers/mxc/ssi/ssi.h | 574 + drivers/mxc/ssi/ssi_types.h | 367 + drivers/mxc/vpu/Kconfig | 30 + drivers/mxc/vpu/Makefile | 10 + drivers/mxc/vpu/mxc_vl2cc.c | 124 + drivers/mxc/vpu/mxc_vpu.c | 881 + drivers/net/Kconfig | 33 +- drivers/net/Makefile | 7 + drivers/net/arm/ixp4xx_eth.c | 3 +- drivers/net/au1000_eth.c | 2 +- drivers/net/bcm63xx_enet.c | 2 +- drivers/net/can/Kconfig | 9 + drivers/net/can/Makefile | 1 + drivers/net/can/flexcan/Makefile | 3 + drivers/net/can/flexcan/dev.c | 743 + drivers/net/can/flexcan/drv.c | 628 + drivers/net/can/flexcan/flexcan.h | 222 + drivers/net/can/flexcan/mbm.c | 361 + drivers/net/cpmac.c | 5 +- drivers/net/dnet.c | 2 +- drivers/net/enc28j60.c | 164 +- drivers/net/ethoc.c | 2 +- drivers/net/fec.c | 409 +- drivers/net/fec.h | 29 +- drivers/net/fec_1588.c | 796 + drivers/net/fec_1588.h | 217 + drivers/net/fec_mpc52xx.c | 2 +- drivers/net/fec_switch.c | 4313 ++ drivers/net/fec_switch.h | 1126 + drivers/net/fs_enet/fs_enet-main.c | 3 +- drivers/net/gianfar.c | 2 +- drivers/net/imx_ptp.c | 1748 + drivers/net/imx_ptp.h | 356 + drivers/net/irda/Kconfig | 4 + drivers/net/irda/Makefile | 1 + drivers/net/irda/mxc_ir.c | 1781 + drivers/net/irda/mxc_ir.h | 131 + drivers/net/macb.c | 2 +- drivers/net/mv643xx_eth.c | 2 +- drivers/net/octeon/octeon_mgmt.c | 2 +- drivers/net/phy/phy.c | 3 +- drivers/net/sb1250-mac.c | 2 +- drivers/net/sh_eth.c | 2 +- drivers/net/smsc911x.c | 8 +- drivers/net/smsc9420.c | 2 +- drivers/net/stmmac/stmmac_main.c | 22 +- drivers/net/tc35815.c | 2 +- drivers/net/tg3.c | 2 +- drivers/net/ucc_geth.c | 13 + drivers/net/wireless/Kconfig | 1 + drivers/net/wireless/Makefile | 2 + drivers/net/wireless/ath6kl/Kconfig | 152 + drivers/net/wireless/ath6kl/Makefile | 138 + .../net/wireless/ath6kl/bmi/include/bmi_internal.h | 51 + drivers/net/wireless/ath6kl/bmi/src/bmi.c | 984 + drivers/net/wireless/ath6kl/bmi/src/makefile | 22 + .../wireless/ath6kl/hif/common/hif_sdio_common.h | 88 + drivers/net/wireless/ath6kl/hif/sdio/Makefile | 86 + .../hif/sdio/linux_sdio/include/hif_internal.h | 134 + .../hif/sdio/linux_sdio/nativemmcstack_readme.txt | 35 + .../wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c | 1010 + .../ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c | 390 + drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c | 1399 + drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h | 383 + .../net/wireless/ath6kl/htc2/AR6000/ar6k_events.c | 762 + .../net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c | 752 + .../ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c | 1255 + drivers/net/wireless/ath6kl/htc2/AR6000/makefile | 22 + drivers/net/wireless/ath6kl/htc2/htc.c | 558 + drivers/net/wireless/ath6kl/htc2/htc_debug.h | 34 + drivers/net/wireless/ath6kl/htc2/htc_internal.h | 213 + drivers/net/wireless/ath6kl/htc2/htc_recv.c | 1545 + drivers/net/wireless/ath6kl/htc2/htc_send.c | 1019 + drivers/net/wireless/ath6kl/htc2/htc_services.c | 444 + .../ath6kl/include/AR6002/AR6002_regdump.h | 57 + .../wireless/ath6kl/include/AR6002/AR6K_version.h | 47 + drivers/net/wireless/ath6kl/include/AR6002/addrs.h | 86 + .../ath6kl/include/AR6002/hw/analog_intf_reg.h | 83 + .../wireless/ath6kl/include/AR6002/hw/analog_reg.h | 1951 + .../wireless/ath6kl/include/AR6002/hw/apb_map.h | 32 + .../wireless/ath6kl/include/AR6002/hw/gpio_reg.h | 996 + .../ath6kl/include/AR6002/hw/mbox_host_reg.h | 405 + .../wireless/ath6kl/include/AR6002/hw/mbox_reg.h | 500 + .../wireless/ath6kl/include/AR6002/hw/rtc_reg.h | 1182 + .../net/wireless/ath6kl/include/AR6002/hw/si_reg.h | 205 + .../wireless/ath6kl/include/AR6002/hw/uart_reg.h | 346 + .../wireless/ath6kl/include/AR6002/hw/vmc_reg.h | 95 + .../include/AR6002/hw2.0/hw/analog_intf_reg.h | 83 + .../ath6kl/include/AR6002/hw2.0/hw/analog_reg.h | 1951 + .../ath6kl/include/AR6002/hw2.0/hw/apb_map.h | 32 + .../ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h | 996 + .../ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h | 405 + .../ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h | 500 + .../ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h | 1182 + .../ath6kl/include/AR6002/hw2.0/hw/si_reg.h | 205 + .../ath6kl/include/AR6002/hw2.0/hw/uart_reg.h | 346 + .../ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h | 95 + .../include/AR6002/hw4.0/hw/analog_intf_ares_reg.h | 3287 + .../AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h | 3670 + .../include/AR6002/hw4.0/hw/analog_intf_reg.h | 33 + .../include/AR6002/hw4.0/hw/apb_athr_wlan_map.h | 36 + .../ath6kl/include/AR6002/hw4.0/hw/apb_map.h | 44 + .../ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h | 7072 ++ .../ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h | 104 + .../include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h | 1249 + .../ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h | 1090 + .../ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h | 587 + .../ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h | 3061 + .../ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h | 33 + .../ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h | 556 + .../include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h | 518 + .../ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h | 634 + .../ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h | 560 + .../ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h | 971 + .../ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h | 2061 + .../ath6kl/include/AR6002/hw4.0/hw/si_reg.h | 205 + .../ath6kl/include/AR6002/hw4.0/hw/uart_reg.h | 256 + .../ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h | 33 + .../include/AR6002/hw4.0/hw/umbox_wlan_reg.h | 318 + .../ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h | 163 + .../ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h | 191 + drivers/net/wireless/ath6kl/include/a_config.h | 45 + drivers/net/wireless/ath6kl/include/a_debug.h | 215 + drivers/net/wireless/ath6kl/include/a_drv.h | 46 + drivers/net/wireless/ath6kl/include/a_drv_api.h | 228 + drivers/net/wireless/ath6kl/include/a_hci.h | 668 + drivers/net/wireless/ath6kl/include/a_osapi.h | 53 + drivers/net/wireless/ath6kl/include/a_types.h | 50 + .../net/wireless/ath6kl/include/aggr_recv_api.h | 136 + drivers/net/wireless/ath6kl/include/ar3kconfig.h | 58 + drivers/net/wireless/ath6kl/include/ar6000_api.h | 50 + drivers/net/wireless/ath6kl/include/ar6000_diag.h | 44 + .../net/wireless/ath6kl/include/ar6kap_common.h | 40 + drivers/net/wireless/ath6kl/include/athbtfilter.h | 129 + drivers/net/wireless/ath6kl/include/athdefs.h | 80 + drivers/net/wireless/ath6kl/include/athendpack.h | 48 + drivers/net/wireless/ath6kl/include/athstartpack.h | 47 + drivers/net/wireless/ath6kl/include/bmi.h | 128 + drivers/net/wireless/ath6kl/include/bmi_msg.h | 231 + drivers/net/wireless/ath6kl/include/btcoexGpio.h | 68 + drivers/net/wireless/ath6kl/include/cnxmgmt.h | 32 + drivers/net/wireless/ath6kl/include/common_drv.h | 90 + drivers/net/wireless/ath6kl/include/dbglog.h | 122 + drivers/net/wireless/ath6kl/include/dbglog_api.h | 48 + drivers/net/wireless/ath6kl/include/dbglog_id.h | 530 + drivers/net/wireless/ath6kl/include/discovery.h | 71 + drivers/net/wireless/ath6kl/include/dl_list.h | 149 + drivers/net/wireless/ath6kl/include/dset_api.h | 61 + .../net/wireless/ath6kl/include/dset_internal.h | 51 + drivers/net/wireless/ath6kl/include/dsetid.h | 122 + drivers/net/wireless/ath6kl/include/epping_test.h | 115 + drivers/net/wireless/ath6kl/include/gmboxif.h | 73 + drivers/net/wireless/ath6kl/include/gpio.h | 43 + drivers/net/wireless/ath6kl/include/gpio_api.h | 55 + .../wireless/ath6kl/include/hci_transport_api.h | 243 + drivers/net/wireless/ath6kl/include/hif.h | 421 + drivers/net/wireless/ath6kl/include/host_version.h | 48 + drivers/net/wireless/ath6kl/include/htc.h | 232 + drivers/net/wireless/ath6kl/include/htc_api.h | 568 + drivers/net/wireless/ath6kl/include/htc_packet.h | 223 + drivers/net/wireless/ath6kl/include/htc_services.h | 48 + drivers/net/wireless/ath6kl/include/ini_dset.h | 80 + drivers/net/wireless/ath6kl/include/pkt_log.h | 41 + drivers/net/wireless/ath6kl/include/regdump.h | 45 + drivers/net/wireless/ath6kl/include/roaming.h | 37 + drivers/net/wireless/ath6kl/include/targaddrs.h | 232 + .../net/wireless/ath6kl/include/target_reg_table.h | 236 + drivers/net/wireless/ath6kl/include/testcmd.h | 179 + drivers/net/wireless/ath6kl/include/wlan_api.h | 122 + drivers/net/wireless/ath6kl/include/wlan_defs.h | 75 + drivers/net/wireless/ath6kl/include/wlan_dset.h | 30 + drivers/net/wireless/ath6kl/include/wmi.h | 3053 + drivers/net/wireless/ath6kl/include/wmi_api.h | 435 + drivers/net/wireless/ath6kl/include/wmi_thin.h | 343 + drivers/net/wireless/ath6kl/include/wmix.h | 275 + drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c | 432 + .../wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c | 506 + .../wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h | 74 + .../wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c | 972 + .../wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h | 156 + drivers/net/wireless/ath6kl/miscdrv/common_drv.c | 973 + drivers/net/wireless/ath6kl/miscdrv/credit_dist.c | 375 + drivers/net/wireless/ath6kl/miscdrv/makefile | 22 + drivers/net/wireless/ath6kl/miscdrv/miscdrv.h | 40 + .../net/wireless/ath6kl/os/linux/ar6000_android.c | 621 + drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c | 6311 ++ .../net/wireless/ath6kl/os/linux/ar6000_raw_if.c | 455 + drivers/net/wireless/ath6kl/os/linux/cfg80211.c | 1467 + drivers/net/wireless/ath6kl/os/linux/eeprom.c | 581 + .../ath6kl/os/linux/export_hci_transport.c | 119 + drivers/net/wireless/ath6kl/os/linux/hci_bridge.c | 1126 + .../wireless/ath6kl/os/linux/include/ar6000_drv.h | 694 + .../ath6kl/os/linux/include/ar6xapi_linux.h | 175 + .../ath6kl/os/linux/include/athdrv_linux.h | 1202 + .../ath6kl/os/linux/include/athtypes_linux.h | 47 + .../wireless/ath6kl/os/linux/include/cfg80211.h | 46 + .../ath6kl/os/linux/include/config_linux.h | 54 + .../wireless/ath6kl/os/linux/include/debug_linux.h | 45 + .../ath6kl/os/linux/include/export_hci_transport.h | 70 + .../ath6kl/os/linux/include/ieee80211_ioctl.h | 174 + .../wireless/ath6kl/os/linux/include/osapi_linux.h | 361 + .../wireless/ath6kl/os/linux/include/wlan_config.h | 50 + .../ath6kl/os/linux/include/wmi_filter_linux.h | 281 + drivers/net/wireless/ath6kl/os/linux/ioctl.c | 4559 ++ drivers/net/wireless/ath6kl/os/linux/netbuf.c | 233 + .../net/wireless/ath6kl/os/linux/wireless_ext.c | 2703 + .../net/wireless/ath6kl/reorder/aggr_rx_internal.h | 112 + drivers/net/wireless/ath6kl/reorder/makefile | 22 + drivers/net/wireless/ath6kl/reorder/rcv_aggr.c | 662 + .../net/wireless/ath6kl/wlan/include/ieee80211.h | 397 + .../wireless/ath6kl/wlan/include/ieee80211_node.h | 81 + drivers/net/wireless/ath6kl/wlan/src/makefile | 22 + drivers/net/wireless/ath6kl/wlan/src/wlan_node.c | 569 + .../wireless/ath6kl/wlan/src/wlan_recv_beacon.c | 196 + drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c | 57 + drivers/net/wireless/ath6kl/wmi/makefile | 22 + drivers/net/wireless/ath6kl/wmi/wmi.c | 6536 ++ drivers/net/wireless/ath6kl/wmi/wmi_host.h | 78 + drivers/pcmcia/Kconfig | 8 + drivers/pcmcia/Makefile | 1 + drivers/pcmcia/mx31ads-pcmcia.c | 1293 + drivers/pcmcia/mx31ads-pcmcia.h | 155 + drivers/power/Kconfig | 36 + drivers/power/Makefile | 3 + drivers/power/da9052-battery.c | 1579 + drivers/power/ds2438_battery.c | 567 + drivers/power/mxs/Makefile | 9 + drivers/power/mxs/ddi_bc_api.c | 559 + drivers/power/mxs/ddi_bc_hw.c | 397 + drivers/power/mxs/ddi_bc_hw.h | 77 + drivers/power/mxs/ddi_bc_init.c | 188 + drivers/power/mxs/ddi_bc_internal.h | 53 + drivers/power/mxs/ddi_bc_ramp.c | 724 + drivers/power/mxs/ddi_bc_ramp.h | 50 + drivers/power/mxs/ddi_bc_sm.c | 918 + drivers/power/mxs/ddi_bc_sm.h | 46 + drivers/power/mxs/ddi_power_battery.c | 1908 + drivers/power/mxs/ddi_power_battery.h | 95 + drivers/power/mxs/fiq.S | 125 + drivers/power/mxs/linux.c | 1213 + drivers/regulator/Kconfig | 37 + drivers/regulator/Makefile | 13 +- drivers/regulator/core.c | 5 + drivers/regulator/da9052-regulator.c | 547 + drivers/regulator/ltc3589-regulator.c | 1052 + drivers/regulator/max17135-regulator.c | 640 + drivers/regulator/mxs-regulator.c | 302 + drivers/regulator/reg-mc13783.c | 2662 + drivers/regulator/reg-mc13892.c | 1956 + drivers/regulator/reg-mc34704.c | 289 + drivers/regulator/reg-mc9s08dz60.c | 236 + drivers/rtc/Kconfig | 54 + drivers/rtc/Makefile | 7 + drivers/rtc/rtc-da9052.c | 694 + drivers/rtc/rtc-imxdi.c | 581 + drivers/rtc/rtc-mc13892.c | 257 + drivers/rtc/rtc-mxc.c | 4 +- drivers/rtc/rtc-mxc_v2.c | 754 + drivers/rtc/rtc-mxs.c | 322 + drivers/serial/Kconfig | 104 + drivers/serial/Makefile | 4 + drivers/serial/mxc_uart.c | 1957 + drivers/serial/mxc_uart_early.c | 184 + drivers/serial/mxc_uart_reg.h | 128 + drivers/serial/mxs-auart.c | 1108 + drivers/serial/mxs-duart.c | 803 + drivers/serial/regs-duart.h | 301 + drivers/serial/regs-uartapp.h | 307 + drivers/serial/serial_core.c | 2 +- drivers/spi/Kconfig | 12 + drivers/spi/Makefile | 2 + drivers/spi/mxc_spi.c | 1316 + drivers/spi/spi_mxs.c | 750 + drivers/spi/spi_mxs.h | 54 + drivers/spi/spi_sam.c | 1161 + drivers/staging/Kconfig | 2 + drivers/staging/Makefile | 1 + drivers/staging/android/Kconfig | 27 + drivers/staging/android/Makefile | 3 + drivers/staging/android/TODO | 10 + drivers/staging/android/binder.c | 3600 + drivers/staging/android/binder.h | 330 + drivers/staging/android/logger.c | 616 + drivers/staging/android/logger.h | 49 + drivers/staging/android/lowmemorykiller.c | 220 + drivers/staging/octeon/ethernet-mdio.c | 2 +- drivers/uio/uio_pdrv_genirq.c | 6 + drivers/usb/class/cdc-acm.c | 1 + drivers/usb/core/driver.c | 2 +- drivers/usb/core/hub.c | 52 + drivers/usb/gadget/Kconfig | 62 +- drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/arcotg_udc.c | 3307 + drivers/usb/gadget/arcotg_udc.h | 712 + drivers/usb/gadget/file_storage.c | 74 +- drivers/usb/gadget/fsl_udc_core.c | 9 +- drivers/usb/gadget/fsl_updater.c | 586 + drivers/usb/gadget/fsl_updater.h | 148 + drivers/usb/gadget/gadget_chips.h | 8 + drivers/usb/gadget/inode.c | 105 + drivers/usb/gadget/stmp_updater.c | 504 + drivers/usb/gadget/stmp_updater.h | 140 + drivers/usb/host/Kconfig | 92 + drivers/usb/host/ehci-arc.c | 737 + drivers/usb/host/ehci-fsl.h | 7 + drivers/usb/host/ehci-hcd.c | 10 + drivers/usb/host/ehci-mem-iram.c | 514 + drivers/usb/host/ehci-q-iram.c | 1345 + drivers/usb/host/ehci.h | 20 + drivers/usb/otg/Kconfig | 8 + drivers/usb/otg/Makefile | 2 + drivers/usb/otg/fsl_otg.c | 1376 + drivers/usb/otg/fsl_otg.h | 412 + drivers/usb/otg/otg_fsm.c | 371 + drivers/usb/otg/otg_fsm.h | 151 + drivers/usb/storage/usb.c | 7 +- drivers/video/Kconfig | 8 + drivers/video/Makefile | 2 + drivers/video/backlight/Kconfig | 41 + drivers/video/backlight/Makefile | 7 + drivers/video/backlight/da9052_bl.c | 439 + drivers/video/backlight/mxc_ipu_bl.c | 158 + drivers/video/backlight/mxc_lcdc_bl.c | 164 + drivers/video/backlight/mxc_mc13892_bl.c | 180 + drivers/video/backlight/mxc_pmic_bl.c | 200 + drivers/video/backlight/mxs_bl.c | 387 + drivers/video/backlight/pwm_bl.c | 10 + drivers/video/backlight/wm8350_bl.c | 299 + drivers/video/mxc/Kconfig | 111 + drivers/video/mxc/Makefile | 26 + drivers/video/mxc/ch7024.c | 866 + drivers/video/mxc/elcdif_regs.h | 678 + drivers/video/mxc/epdc_regs.h | 301 + drivers/video/mxc/ldb.c | 1458 + drivers/video/mxc/mx2fb.c | 1349 + drivers/video/mxc/mx2fb.h | 141 + drivers/video/mxc/mxc_edid.c | 319 + drivers/video/mxc/mxc_elcdif_fb.c | 1466 + drivers/video/mxc/mxc_epdc_fb.c | 3786 + drivers/video/mxc/mxc_ipuv3_fb.c | 2074 + drivers/video/mxc/mxcfb.c | 1372 + drivers/video/mxc/mxcfb_ch7026.c | 370 + drivers/video/mxc/mxcfb_claa_wvga.c | 240 + drivers/video/mxc/mxcfb_epson.c | 1153 + drivers/video/mxc/mxcfb_epson_vga.c | 362 + drivers/video/mxc/mxcfb_modedb.c | 69 + drivers/video/mxc/mxcfb_seiko_wvga.c | 241 + drivers/video/mxc/tve.c | 1289 + drivers/video/mxs/Kconfig | 28 + drivers/video/mxs/Makefile | 6 + drivers/video/mxs/lcd_43wvf1g.c | 289 + drivers/video/mxs/lcd_lms430.c | 300 + drivers/video/mxs/lcdif.c | 136 + drivers/video/mxs/mxsfb.c | 950 + drivers/video/mxs/regs-tvenc.h | 583 + drivers/video/mxs/tvenc.c | 279 + drivers/w1/masters/mxc_w1.c | 177 +- drivers/w1/slaves/Kconfig | 23 + drivers/w1/slaves/Makefile | 2 + drivers/w1/slaves/w1_ds2438.c | 204 + drivers/w1/slaves/w1_ds2438.h | 125 + drivers/w1/slaves/w1_ds2751.c | 320 + drivers/w1/w1_family.h | 2 + drivers/watchdog/Kconfig | 29 + drivers/watchdog/Makefile | 3 + drivers/watchdog/da9052_wdt.c | 542 + drivers/watchdog/mxc_wdt.c | 376 + drivers/watchdog/mxc_wdt.h | 37 + drivers/watchdog/mxs-wdt.c | 303 + firmware/Makefile | 3 + firmware/imx/epdc_E60_V110.fw.ihex | 45914 +++++++++++ firmware/imx/epdc_E60_V220.fw.ihex | 77569 +++++++++++++++++++ firmware/imx/epdc_E97_V110.fw.ihex | 54512 +++++++++++++ fs/fat/dir.c | 9 + fs/fat/fat.h | 1 + fs/fat/inode.c | 9 + fs/jffs2/fs.c | 6 +- fs/jffs2/os-linux.h | 2 +- fs/jffs2/scan.c | 24 +- fs/partitions/check.c | 8 + include/linux/Kbuild | 24 + include/linux/android_pmem.h | 91 + include/linux/ashmem.h | 48 + include/linux/cryptodev.h | 82 + include/linux/fec.h | 24 + include/linux/fsl_devices.h | 542 +- include/linux/gpmi-nfc.h | 123 + include/linux/i2c/mpr.h | 79 + include/linux/imx_adc.h | 275 + include/linux/ipu.h | 1292 + include/linux/iram_alloc.h | 35 + include/linux/ldb.h | 88 + include/linux/major.h | 2 + include/linux/mfd/da9052/adc.h | 66 + include/linux/mfd/da9052/bat.h | 341 + include/linux/mfd/da9052/bl.h | 289 + include/linux/mfd/da9052/da9052.h | 228 + include/linux/mfd/da9052/eh.h | 74 + include/linux/mfd/da9052/gpio.h | 253 + include/linux/mfd/da9052/led.h | 39 + include/linux/mfd/da9052/pm.h | 75 + include/linux/mfd/da9052/reg.h | 922 + include/linux/mfd/da9052/rtc.h | 322 + include/linux/mfd/da9052/tsi.h | 427 + include/linux/mfd/da9052/tsi_calibrate.h | 47 + include/linux/mfd/da9052/tsi_cfg.h | 132 + include/linux/mfd/da9052/tsi_filter.h | 57 + include/linux/mfd/da9052/wdt.h | 83 + include/linux/mfd/ltc3589/core.h | 68 + include/linux/mfd/max17135.h | 217 + include/linux/mfd/mc13783/core.h | 72 + include/linux/mfd/mc13892/core.h | 77 + include/linux/mfd/mc34704/core.h | 84 + include/linux/mfd/mc9s08dz60/core.h | 59 + include/linux/mfd/mc9s08dz60/pmic.h | 82 + include/linux/mfd/wm8350/audio.h | 2 + include/linux/mfd/wm8350/bl.h | 33 + include/linux/mmc/card.h | 6 + include/linux/mmc/host.h | 2 + include/linux/mmc/mmc.h | 29 + include/linux/msdos_fs.h | 12 + include/linux/mtd/nand.h | 24 +- include/linux/mxc_asrc.h | 210 + include/linux/mxc_mlb.h | 51 + include/linux/mxc_pf.h | 125 + include/linux/mxc_scc2_driver.h | 975 + include/linux/mxc_scc_driver.h | 1031 + include/linux/mxc_si4702.h | 39 + include/linux/mxc_sim_interface.h | 108 + include/linux/mxc_srtc.h | 25 + include/linux/mxc_v4l2.h | 48 + include/linux/mxcfb.h | 171 + include/linux/mxcfb_epdc_kernel.h | 34 + include/linux/phy.h | 2 +- include/linux/pmic_adc.h | 455 + include/linux/pmic_battery.h | 419 + include/linux/pmic_external.h | 435 + include/linux/pmic_light.h | 1082 + include/linux/pmic_rtc.h | 153 + include/linux/pmic_status.h | 82 + include/linux/powerkey.h | 30 + include/linux/pxp_dma.h | 223 + include/linux/regulator/da9052-regulator.h | 15 + include/linux/regulator/ltc3589.h | 224 + include/linux/sched.h | 3 + include/linux/sockios.h | 1 + include/linux/soundcard.h | 7 + include/linux/uid_stat.h | 29 + include/linux/usb/fsl_xcvr.h | 58 + include/mtd/mtd-abi.h | 3 +- include/net/tcp.h | 2 + init/Kconfig | 9 + kernel/fork.c | 18 + kernel/power/Kconfig | 14 + kernel/power/main.c | 36 + localversion | 1 + mm/Makefile | 1 + mm/ashmem.c | 745 + mm/shmem.c | 14 +- net/core/dev.c | 6 + net/dsa/slave.c | 3 +- net/ipv4/af_inet.c | 1 + net/ipv4/devinet.c | 9 +- net/ipv4/tcp.c | 13 +- net/ipv4/tcp_ipv4.c | 43 + sound/arm/Kconfig | 49 + sound/arm/Makefile | 11 + sound/arm/mxc-alsa-common.h | 68 + sound/arm/mxc-alsa-mixer.c | 411 + sound/arm/mxc-alsa-pmic.c | 3793 + sound/arm/mxc-alsa-pmic.h | 110 + sound/arm/mxc-alsa-spdif.c | 2293 + sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/codecs/Kconfig | 25 + sound/soc/codecs/Makefile | 14 + sound/soc/codecs/ak4647.c | 800 + sound/soc/codecs/ak4647.h | 92 + sound/soc/codecs/ak5702.c | 595 + sound/soc/codecs/ak5702.h | 130 + sound/soc/codecs/bluetooth.c | 162 + sound/soc/codecs/cs42888.c | 1193 + sound/soc/codecs/cs42888.h | 31 + sound/soc/codecs/mxs-adc-codec.c | 1214 + sound/soc/codecs/mxs-adc-codec.h | 87 + sound/soc/codecs/mxs_spdif.c | 447 + sound/soc/codecs/mxs_spdif.h | 172 + sound/soc/codecs/sgtl5000.c | 1394 + sound/soc/codecs/sgtl5000.h | 410 + sound/soc/codecs/wm8350.c | 10 +- sound/soc/codecs/wm8580.c | 135 +- sound/soc/codecs/wm8580.h | 9 + sound/soc/imx/Kconfig | 85 +- sound/soc/imx/Makefile | 28 +- sound/soc/imx/imx-3stack-ak4647.c | 445 + sound/soc/imx/imx-3stack-ak5702.c | 226 + sound/soc/imx/imx-3stack-bt.c | 256 + sound/soc/imx/imx-3stack-bt.h | 21 + sound/soc/imx/imx-3stack-cs42888.c | 428 + sound/soc/imx/imx-3stack-sgtl5000.c | 706 + sound/soc/imx/imx-3stack-wm8350.c | 696 + sound/soc/imx/imx-3stack-wm8580.c | 437 + sound/soc/imx/imx-ac97.c | 564 + sound/soc/imx/imx-esai.c | 711 + sound/soc/imx/imx-esai.h | 314 + sound/soc/imx/imx-pcm.c | 719 + sound/soc/imx/imx-pcm.h | 83 + sound/soc/imx/imx-ssi.c | 1102 +- sound/soc/imx/imx-ssi.h | 443 +- sound/soc/mxs/Kconfig | 51 + sound/soc/mxs/Makefile | 16 + sound/soc/mxs/mxs-adc.c | 477 + sound/soc/mxs/mxs-adc.h | 21 + sound/soc/mxs/mxs-dai.c | 689 + sound/soc/mxs/mxs-dai.h | 42 + sound/soc/mxs/mxs-devb-spdif.c | 90 + sound/soc/mxs/mxs-devb.c | 282 + sound/soc/mxs/mxs-evk-adc.c | 198 + sound/soc/mxs/mxs-pcm.c | 504 + sound/soc/mxs/mxs-pcm.h | 40 + sound/soc/mxs/mxs-spdif-dai.c | 203 + sound/soc/mxs/mxs-spdif-dai.h | 21 + 1396 files changed, 1002844 insertions(+), 2980 deletions(-) create mode 100644 Documentation/imx_nfc.txt create mode 100644 arch/arm/configs/imx23evk_defconfig create mode 100644 arch/arm/configs/imx23evk_updater_defconfig create mode 100644 arch/arm/configs/imx25_3stack_defconfig create mode 100644 arch/arm/configs/imx25_updater_defconfig create mode 100644 arch/arm/configs/imx28evk_defconfig create mode 100644 arch/arm/configs/imx28evk_updater_defconfig create mode 100644 arch/arm/configs/imx5_defconfig create mode 100644 arch/arm/configs/imx5_updater_defconfig create mode 100644 arch/arm/configs/mx3_updater_defconfig create mode 100644 arch/arm/include/asm/mach/keypad.h create mode 100644 arch/arm/mach-mx23/Kconfig create mode 100644 arch/arm/mach-mx23/Makefile create mode 100644 arch/arm/mach-mx23/Makefile.boot create mode 100644 arch/arm/mach-mx23/bus_freq.c create mode 100644 arch/arm/mach-mx23/clock.c create mode 100644 arch/arm/mach-mx23/device.c create mode 100644 arch/arm/mach-mx23/device.h create mode 100644 arch/arm/mach-mx23/emi.S create mode 100644 arch/arm/mach-mx23/emi.inc create mode 100644 arch/arm/mach-mx23/gpio.c create mode 100644 arch/arm/mach-mx23/include/mach/dma.h create mode 100644 arch/arm/mach-mx23/include/mach/irqs.h create mode 100644 arch/arm/mach-mx23/include/mach/lcdif.h create mode 100644 arch/arm/mach-mx23/include/mach/mx23.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-apbh.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-audioin.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-audioout.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-emi.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-i2c.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-lcdif.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-lradc.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-ocotp.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-power.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-pwm.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-pxp.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-rtc.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-ssp.h create mode 100644 arch/arm/mach-mx23/include/mach/regs-timrot.h create mode 100644 arch/arm/mach-mx23/include/mach/regulator.h create mode 100644 arch/arm/mach-mx23/mx23_pins.h create mode 100644 arch/arm/mach-mx23/mx23evk.c create mode 100644 arch/arm/mach-mx23/mx23evk.h create mode 100644 arch/arm/mach-mx23/mx23evk_pins.c create mode 100644 arch/arm/mach-mx23/otp.c create mode 100644 arch/arm/mach-mx23/pinctrl.c create mode 100644 arch/arm/mach-mx23/pm.c create mode 100644 arch/arm/mach-mx23/power.c create mode 100644 arch/arm/mach-mx23/regs-clkctrl.h create mode 100644 arch/arm/mach-mx23/regs-digctl.h create mode 100644 arch/arm/mach-mx23/regs-dram.h create mode 100644 arch/arm/mach-mx23/regs-pinctrl.h create mode 100644 arch/arm/mach-mx23/serial.c create mode 100644 arch/arm/mach-mx23/sleep.S create mode 100644 arch/arm/mach-mx23/sleep.h create mode 100644 arch/arm/mach-mx23/usb.h create mode 100644 arch/arm/mach-mx23/usb_dr.c create mode 100644 arch/arm/mach-mx25/board-mx25_3stack.h create mode 100644 arch/arm/mach-mx25/bus_freq.c create mode 100644 arch/arm/mach-mx25/cpu.c create mode 100644 arch/arm/mach-mx25/crm_regs.h create mode 100644 arch/arm/mach-mx25/dma.c create mode 100644 arch/arm/mach-mx25/iomux.c create mode 100644 arch/arm/mach-mx25/iomux.h create mode 100644 arch/arm/mach-mx25/mx25_3stack.c create mode 100644 arch/arm/mach-mx25/mx25_3stack_cpld.c create mode 100644 arch/arm/mach-mx25/mx25_3stack_gpio.c create mode 100644 arch/arm/mach-mx25/mx25_3stack_pmic_mc34704.c create mode 100644 arch/arm/mach-mx25/mx25_pins.h create mode 100644 arch/arm/mach-mx25/pm.c create mode 100644 arch/arm/mach-mx25/sdma_script_code.h create mode 100644 arch/arm/mach-mx25/serial.c create mode 100644 arch/arm/mach-mx25/serial.h create mode 100644 arch/arm/mach-mx25/system.c create mode 100644 arch/arm/mach-mx25/usb.h create mode 100644 arch/arm/mach-mx25/usb_dr.c create mode 100644 arch/arm/mach-mx25/usb_h2.c create mode 100644 arch/arm/mach-mx28/Kconfig create mode 100644 arch/arm/mach-mx28/Makefile create mode 100644 arch/arm/mach-mx28/Makefile.boot create mode 100644 arch/arm/mach-mx28/bus_freq.c create mode 100644 arch/arm/mach-mx28/clock.c create mode 100644 arch/arm/mach-mx28/device.c create mode 100644 arch/arm/mach-mx28/device.h create mode 100644 arch/arm/mach-mx28/emi.S create mode 100644 arch/arm/mach-mx28/emi_settings.c create mode 100644 arch/arm/mach-mx28/emi_settings.h create mode 100644 arch/arm/mach-mx28/gpio.c create mode 100644 arch/arm/mach-mx28/include/mach/dma.h create mode 100644 arch/arm/mach-mx28/include/mach/lcdif.h create mode 100644 arch/arm/mach-mx28/include/mach/mx28.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-apbh.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-i2c.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-icoll.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-lcdif.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-lradc.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-ocotp.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-power.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-pwm.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-pxp.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-rtc.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-ssp.h create mode 100644 arch/arm/mach-mx28/include/mach/regs-timrot.h create mode 100644 arch/arm/mach-mx28/include/mach/regulator.h create mode 100644 arch/arm/mach-mx28/mx28_pins.h create mode 100644 arch/arm/mach-mx28/mx28evk.c create mode 100644 arch/arm/mach-mx28/mx28evk.h create mode 100644 arch/arm/mach-mx28/mx28evk_pins.c create mode 100644 arch/arm/mach-mx28/pinctrl.c create mode 100644 arch/arm/mach-mx28/pm.c create mode 100644 arch/arm/mach-mx28/power.c create mode 100644 arch/arm/mach-mx28/regs-clkctrl.h create mode 100644 arch/arm/mach-mx28/regs-digctl.h create mode 100644 arch/arm/mach-mx28/regs-dram.h create mode 100644 arch/arm/mach-mx28/regs-pinctrl.h create mode 100644 arch/arm/mach-mx28/serial.c create mode 100644 arch/arm/mach-mx28/sleep.S create mode 100644 arch/arm/mach-mx28/sleep.h create mode 100644 arch/arm/mach-mx28/usb.h create mode 100644 arch/arm/mach-mx28/usb_dr.c create mode 100644 arch/arm/mach-mx28/usb_h1.c create mode 100644 arch/arm/mach-mx3/devices-imx31.h create mode 100644 arch/arm/mach-mx3/devices-imx35.h create mode 100644 arch/arm/mach-mx3/dma.c create mode 100644 arch/arm/mach-mx3/dptc.c create mode 100644 arch/arm/mach-mx3/dummy_gpio.c create mode 100644 arch/arm/mach-mx3/dvfs-imx35.c create mode 100644 arch/arm/mach-mx3/entry-pm.S create mode 100644 arch/arm/mach-mx3/iomux.h create mode 100644 arch/arm/mach-mx3/mach-mx35_3ds.c delete mode 100644 arch/arm/mach-mx3/mach-mx35pdk.c create mode 100644 arch/arm/mach-mx3/mx31_sdma_script_code_v1.h create mode 100644 arch/arm/mach-mx3/mx31_sdma_script_code_v2.h create mode 100644 arch/arm/mach-mx3/mx35_3ds-irq.c create mode 100644 arch/arm/mach-mx3/mx35_3ds_pesudo_irq.c create mode 100644 arch/arm/mach-mx3/mx35_3ds_pmic_mc13892.c create mode 100644 arch/arm/mach-mx3/mx35_3ds_pmic_mc9s08dz60.c create mode 100644 arch/arm/mach-mx3/mx35_sdma_script_code_v1.h create mode 100644 arch/arm/mach-mx3/mx35_sdma_script_code_v2.h create mode 100644 arch/arm/mach-mx3/mx3_3ds_pmic_mc13783.c create mode 100644 arch/arm/mach-mx3/mx3x-dma.c create mode 100644 arch/arm/mach-mx3/pm.c create mode 100644 arch/arm/mach-mx3/system.c create mode 100644 arch/arm/mach-mx5/bus_freq.c delete mode 100644 arch/arm/mach-mx5/clock-mx51.c create mode 100644 arch/arm/mach-mx5/clock.c create mode 100644 arch/arm/mach-mx5/clock_mx50.c create mode 100644 arch/arm/mach-mx5/devices-imx51.h create mode 100644 arch/arm/mach-mx5/dma-apbh.c create mode 100644 arch/arm/mach-mx5/dma-apbh.h create mode 100644 arch/arm/mach-mx5/dma.c create mode 100644 arch/arm/mach-mx5/dmaengine.c create mode 100644 arch/arm/mach-mx5/dummy_gpio.c create mode 100644 arch/arm/mach-mx5/early_setup.c create mode 100644 arch/arm/mach-mx5/iomux.c create mode 100644 arch/arm/mach-mx5/iomux.h create mode 100644 arch/arm/mach-mx5/lpmodes.c create mode 100644 arch/arm/mach-mx5/mx50_arm2.c create mode 100644 arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c create mode 100644 arch/arm/mach-mx5/mx50_ddr_freq.S create mode 100644 arch/arm/mach-mx5/mx50_rdp.c create mode 100644 arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c create mode 100644 arch/arm/mach-mx5/mx50_suspend.S create mode 100644 arch/arm/mach-mx5/mx50_wfi.S create mode 100644 arch/arm/mach-mx5/mx51_3stack.c create mode 100644 arch/arm/mach-mx5/mx51_3stack_gpio.c create mode 100644 arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c create mode 100644 arch/arm/mach-mx5/mx51_babbage.c create mode 100644 arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c create mode 100644 arch/arm/mach-mx5/mx51_pins.h create mode 100644 arch/arm/mach-mx5/mx53_ard.c create mode 100644 arch/arm/mach-mx5/mx53_ard_pmic_ltc3589.c create mode 100644 arch/arm/mach-mx5/mx53_evk.c create mode 100644 arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c create mode 100644 arch/arm/mach-mx5/mx53_loco.c create mode 100644 arch/arm/mach-mx5/mx53_loco_pmic_da9053.c create mode 100644 arch/arm/mach-mx5/mx53_smd.c create mode 100644 arch/arm/mach-mx5/mx53_smd_pmic_da9053.c create mode 100644 arch/arm/mach-mx5/mx53_smd_rfkill.c create mode 100644 arch/arm/mach-mx5/mx53_wp.c create mode 100644 arch/arm/mach-mx5/mx53_wp.h create mode 100644 arch/arm/mach-mx5/pm.c create mode 100644 arch/arm/mach-mx5/pm_da9053.c create mode 100644 arch/arm/mach-mx5/regs-apbh.h create mode 100644 arch/arm/mach-mx5/sdma_script_code_mx50.h create mode 100644 arch/arm/mach-mx5/sdma_script_code_mx51.h create mode 100644 arch/arm/mach-mx5/sdma_script_code_mx53.h create mode 100644 arch/arm/mach-mx5/sdram_autogating.c create mode 100644 arch/arm/mach-mx5/serial.c create mode 100644 arch/arm/mach-mx5/serial.h create mode 100644 arch/arm/mach-mx5/suspend.S create mode 100644 arch/arm/mach-mx5/system.c create mode 100644 arch/arm/mach-mx5/usb.h create mode 100644 arch/arm/mach-mx5/usb_dr.c create mode 100644 arch/arm/mach-mx5/usb_h1.c create mode 100644 arch/arm/mach-mx5/usb_h2.c create mode 100644 arch/arm/mach-mx5/wfi.S create mode 100644 arch/arm/plat-mxc/3ds_debugboard.c create mode 100644 arch/arm/plat-mxc/ahci_sata.c create mode 100644 arch/arm/plat-mxc/cpu_common.c create mode 100644 arch/arm/plat-mxc/cpufreq.c create mode 100644 arch/arm/plat-mxc/devices/Kconfig create mode 100644 arch/arm/plat-mxc/devices/Makefile create mode 100644 arch/arm/plat-mxc/devices/platform-flexcan.c create mode 100644 arch/arm/plat-mxc/devices/platform-imx-i2c.c create mode 100644 arch/arm/plat-mxc/devices/platform-imx-mmc.c create mode 100644 arch/arm/plat-mxc/devices/platform-imx-uart.c create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_nand.c create mode 100644 arch/arm/plat-mxc/devices/platform-spi_imx.c create mode 100644 arch/arm/plat-mxc/dptc.c create mode 100644 arch/arm/plat-mxc/dvfs_core.c create mode 100644 arch/arm/plat-mxc/dvfs_per.c create mode 100644 arch/arm/plat-mxc/include/mach/3ds_debugboard.h create mode 100644 arch/arm/plat-mxc/include/mach/arc_otg.h create mode 100644 arch/arm/plat-mxc/include/mach/audio_controls.h create mode 100644 arch/arm/plat-mxc/include/mach/board-mx35_3ds.h delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx35pdk.h create mode 100644 arch/arm/plat-mxc/include/mach/devices-common.h create mode 100644 arch/arm/plat-mxc/include/mach/dma.h create mode 100644 arch/arm/plat-mxc/include/mach/dmaengine.h create mode 100644 arch/arm/plat-mxc/include/mach/dptc.h create mode 100644 arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h create mode 100644 arch/arm/plat-mxc/include/mach/fsl_usb.h create mode 100644 arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h create mode 100644 arch/arm/plat-mxc/include/mach/hw_events.h create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx50.h create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx53.h create mode 100644 arch/arm/plat-mxc/include/mach/mx5x.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_dptc.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_dvfs.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_edid.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_gpc.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_iim.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_pm.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_rfkill.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_scc.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_timer.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_uart.h create mode 100644 arch/arm/plat-mxc/include/mach/mxc_vpu.h create mode 100644 arch/arm/plat-mxc/include/mach/pcmcia.h create mode 100644 arch/arm/plat-mxc/include/mach/pmic_audio.h create mode 100644 arch/arm/plat-mxc/include/mach/pmic_convity.h create mode 100644 arch/arm/plat-mxc/include/mach/pmic_power.h create mode 100644 arch/arm/plat-mxc/include/mach/sdma.h create mode 100644 arch/arm/plat-mxc/include/mach/sdram_autogating.h create mode 100644 arch/arm/plat-mxc/io.c create mode 100644 arch/arm/plat-mxc/iram.c create mode 100644 arch/arm/plat-mxc/isp1301xc.c create mode 100644 arch/arm/plat-mxc/isp1504xc.c create mode 100644 arch/arm/plat-mxc/mc13783_xc.c create mode 100644 arch/arm/plat-mxc/sdma/Makefile create mode 100644 arch/arm/plat-mxc/sdma/dma_sdma.c create mode 100644 arch/arm/plat-mxc/sdma/iapi/Makefile create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/epm.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/iapi.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h create mode 100644 arch/arm/plat-mxc/sdma/iapi/src/Makefile create mode 100644 arch/arm/plat-mxc/sdma/iapi/src/iapiDefaults.c create mode 100644 arch/arm/plat-mxc/sdma/iapi/src/iapiHigh.c create mode 100644 arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c create mode 100644 arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c create mode 100644 arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c create mode 100644 arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c create mode 100644 arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c create mode 100644 arch/arm/plat-mxc/sdma/sdma.c create mode 100644 arch/arm/plat-mxc/sdma/sdma_malloc.c create mode 100644 arch/arm/plat-mxc/serialxc.c create mode 100644 arch/arm/plat-mxc/snoop.c create mode 100644 arch/arm/plat-mxc/usb_common.c create mode 100644 arch/arm/plat-mxc/usb_wakeup.c create mode 100644 arch/arm/plat-mxc/utmixc.c create mode 100644 arch/arm/plat-mxc/zq_calib.c create mode 100644 arch/arm/plat-mxs/Kconfig create mode 100644 arch/arm/plat-mxs/Makefile create mode 100644 arch/arm/plat-mxs/clock.c create mode 100644 arch/arm/plat-mxs/core.c create mode 100644 arch/arm/plat-mxs/cpufreq.c create mode 100644 arch/arm/plat-mxs/device.c create mode 100644 arch/arm/plat-mxs/dma-apbh.c create mode 100644 arch/arm/plat-mxs/dma-apbx.c create mode 100644 arch/arm/plat-mxs/dmaengine.c create mode 100644 arch/arm/plat-mxs/gpio.c create mode 100644 arch/arm/plat-mxs/icoll.c create mode 100644 arch/arm/plat-mxs/include/mach/arc_otg.h create mode 100644 arch/arm/plat-mxs/include/mach/bus_freq.h create mode 100644 arch/arm/plat-mxs/include/mach/clkdev.h create mode 100644 arch/arm/plat-mxs/include/mach/clock.h create mode 100644 arch/arm/plat-mxs/include/mach/ddi_bc.h create mode 100644 arch/arm/plat-mxs/include/mach/debug-macro.S create mode 100644 arch/arm/plat-mxs/include/mach/device.h create mode 100644 arch/arm/plat-mxs/include/mach/dmaengine.h create mode 100644 arch/arm/plat-mxs/include/mach/entry-macro.S create mode 100644 arch/arm/plat-mxs/include/mach/fsl_usb.h create mode 100644 arch/arm/plat-mxs/include/mach/fsl_usb_gadget.h create mode 100644 arch/arm/plat-mxs/include/mach/gpio.h create mode 100644 arch/arm/plat-mxs/include/mach/hardware.h create mode 100644 arch/arm/plat-mxs/include/mach/io.h create mode 100644 arch/arm/plat-mxs/include/mach/irqs.h create mode 100644 arch/arm/plat-mxs/include/mach/lradc.h create mode 100644 arch/arm/plat-mxs/include/mach/memory.h create mode 100644 arch/arm/plat-mxs/include/mach/pinctrl.h create mode 100644 arch/arm/plat-mxs/include/mach/power.h create mode 100644 arch/arm/plat-mxs/include/mach/system.h create mode 100644 arch/arm/plat-mxs/include/mach/timex.h create mode 100644 arch/arm/plat-mxs/include/mach/uncompress.h create mode 100644 arch/arm/plat-mxs/include/mach/unique-id.h create mode 100644 arch/arm/plat-mxs/include/mach/vmalloc.h create mode 100644 arch/arm/plat-mxs/iram.c create mode 100644 arch/arm/plat-mxs/lradc.c create mode 100644 arch/arm/plat-mxs/pinctrl.c create mode 100644 arch/arm/plat-mxs/regs-apbx.h create mode 100644 arch/arm/plat-mxs/regs-icoll.h create mode 100644 arch/arm/plat-mxs/regs-usbphy.h create mode 100644 arch/arm/plat-mxs/timer-match.c create mode 100644 arch/arm/plat-mxs/timer-nomatch.c create mode 100644 arch/arm/plat-mxs/unique-id.c create mode 100644 arch/arm/plat-mxs/usb_common.c create mode 100644 arch/arm/plat-mxs/usb_wakeup.c create mode 100644 arch/arm/plat-mxs/utmixc.c create mode 100644 crypto/cryptodev.c create mode 100644 drivers/ata/pata_fsl.c create mode 100644 drivers/bluetooth/hci_ath.c create mode 100644 drivers/char/fsl_otp.c create mode 100644 drivers/char/fsl_otp.h create mode 100644 drivers/char/hw_random/fsl-rnga.c create mode 100644 drivers/char/hw_random/fsl-rngc.c create mode 100644 drivers/char/imx_sim.c create mode 100644 drivers/char/mxc_iim.c create mode 100644 drivers/char/mxc_si4702.c create mode 100644 drivers/char/mxs_viim.c create mode 100644 drivers/char/regs-ocotp-v2.h create mode 100644 drivers/crypto/dcp.c create mode 100644 drivers/crypto/dcp.h create mode 100644 drivers/crypto/dcp_bootstream_ioctl.h create mode 100644 drivers/dma/pxp/Makefile create mode 100644 drivers/dma/pxp/pxp_device.c create mode 100644 drivers/dma/pxp/pxp_dma.c create mode 100644 drivers/dma/pxp/regs-pxp.h create mode 100644 drivers/gpio/da9052-gpio.c create mode 100644 drivers/hwmon/da9052-adc.c create mode 100644 drivers/hwmon/isl29003.c create mode 100644 drivers/hwmon/max17135-hwmon.c create mode 100644 drivers/hwmon/mxc_mma7450.c create mode 100644 drivers/hwmon/mxc_mma8450.c create mode 100644 drivers/hwmon/mxc_mma8451.c create mode 100644 drivers/i2c-slave/Kconfig create mode 100644 drivers/i2c-slave/Makefile create mode 100644 drivers/i2c-slave/i2c_slave_client.c create mode 100644 drivers/i2c-slave/i2c_slave_core.c create mode 100644 drivers/i2c-slave/i2c_slave_device.c create mode 100644 drivers/i2c-slave/i2c_slave_device.h create mode 100644 drivers/i2c-slave/i2c_slave_ring_buffer.c create mode 100644 drivers/i2c-slave/i2c_slave_ring_buffer.h create mode 100644 drivers/i2c-slave/mxc_i2c_slave.c create mode 100644 drivers/i2c-slave/mxc_i2c_slave.h create mode 100644 drivers/i2c-slave/mxc_i2c_slave_reg.h create mode 100644 drivers/i2c/busses/i2c-mxs.c create mode 100644 drivers/i2c/busses/i2c-mxs.h create mode 100644 drivers/i2c/busses/mxc_i2c.c create mode 100644 drivers/i2c/busses/mxc_i2c_hs.c create mode 100644 drivers/i2c/busses/mxc_i2c_hs_reg.h create mode 100644 drivers/i2c/busses/mxc_i2c_reg.h create mode 100644 drivers/input/keyboard/mc9s08dz60_keyb.c create mode 100644 drivers/input/keyboard/mpr084.c create mode 100644 drivers/input/keyboard/mpr121.c create mode 100644 drivers/input/keyboard/mxc_keyb.c create mode 100644 drivers/input/keyboard/mxc_pwrkey.c create mode 100644 drivers/input/keyboard/mxs-kbd.c create mode 100644 drivers/input/misc/da9052_onkey.c create mode 100644 drivers/input/touchscreen/da9052_tsi.c create mode 100644 drivers/input/touchscreen/da9052_tsi_calibrate.c create mode 100644 drivers/input/touchscreen/da9052_tsi_filter.c create mode 100644 drivers/input/touchscreen/imx_adc_ts.c create mode 100644 drivers/input/touchscreen/max11801_ts.c create mode 100644 drivers/input/touchscreen/mxc_ts.c create mode 100644 drivers/input/touchscreen/mxs-ts.c create mode 100644 drivers/leds/leds-da9052.c create mode 100644 drivers/leds/leds-mc13892.c create mode 100644 drivers/leds/leds-mxs-pwm.c create mode 100644 drivers/media/video/mxc/capture/Kconfig create mode 100644 drivers/media/video/mxc/capture/Makefile create mode 100644 drivers/media/video/mxc/capture/adv7180.c create mode 100644 drivers/media/video/mxc/capture/csi_v4l2_capture.c create mode 100644 drivers/media/video/mxc/capture/fsl_csi.c create mode 100644 drivers/media/video/mxc/capture/fsl_csi.h create mode 100644 drivers/media/video/mxc/capture/ipu_csi_enc.c create mode 100644 drivers/media/video/mxc/capture/ipu_prp_enc.c create mode 100644 drivers/media/video/mxc/capture/ipu_prp_sw.h create mode 100644 drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c create mode 100644 drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c create mode 100644 drivers/media/video/mxc/capture/ipu_still.c create mode 100644 drivers/media/video/mxc/capture/mt9v111.c create mode 100644 drivers/media/video/mxc/capture/mt9v111.h create mode 100644 drivers/media/video/mxc/capture/mxc_v4l2_capture.c create mode 100644 drivers/media/video/mxc/capture/mxc_v4l2_capture.h create mode 100644 drivers/media/video/mxc/capture/ov2640.c create mode 100644 drivers/media/video/mxc/capture/ov3640.c create mode 100644 drivers/media/video/mxc/capture/ov5640.c create mode 100644 drivers/media/video/mxc/capture/ov5642.c create mode 100644 drivers/media/video/mxc/capture/sensor_clock.c create mode 100644 drivers/media/video/mxc/opl/Makefile create mode 100644 drivers/media/video/mxc/opl/hmirror_rotate180_u16.c create mode 100644 drivers/media/video/mxc/opl/opl.h create mode 100644 drivers/media/video/mxc/opl/opl_mod.c create mode 100644 drivers/media/video/mxc/opl/rotate270_u16.c create mode 100644 drivers/media/video/mxc/opl/rotate270_u16_qcif.S create mode 100644 drivers/media/video/mxc/opl/rotate90_u16.c create mode 100644 drivers/media/video/mxc/opl/rotate90_u16_qcif.S create mode 100644 drivers/media/video/mxc/opl/vmirror_u16.c create mode 100644 drivers/media/video/mxc/output/Kconfig create mode 100644 drivers/media/video/mxc/output/Makefile create mode 100644 drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c create mode 100644 drivers/media/video/mxc/output/mxc_pxp_v4l2.c create mode 100644 drivers/media/video/mxc/output/mxc_pxp_v4l2.h create mode 100644 drivers/media/video/mxc/output/mxc_v4l2_output.c create mode 100644 drivers/media/video/mxc/output/mxc_v4l2_output.h create mode 100644 drivers/media/video/mxs_pxp.c create mode 100644 drivers/media/video/mxs_pxp.h create mode 100644 drivers/media/video/pxp.c create mode 100644 drivers/media/video/pxp.h create mode 100644 drivers/mfd/da9052-core.c create mode 100644 drivers/mfd/da9052-i2c.c create mode 100644 drivers/mfd/da9052-spi.c create mode 100644 drivers/mfd/ltc3589-i2c.c create mode 100644 drivers/mfd/max17135-core.c create mode 100644 drivers/misc/mxs-perfmon.c create mode 100644 drivers/misc/mxs-persistent.c create mode 100644 drivers/misc/pmem.c create mode 100644 drivers/misc/regs-perfmon.h create mode 100644 drivers/misc/uid_stat.c create mode 100644 drivers/mmc/card/unifi_fs/Makefile create mode 100644 drivers/mmc/card/unifi_fs/fs_lx.c create mode 100644 drivers/mmc/card/unifi_fs/fs_sdio_api.h create mode 100644 drivers/mmc/host/mx_sdhci.c create mode 100644 drivers/mmc/host/mx_sdhci.h create mode 100644 drivers/mmc/host/mxc_mmc.c create mode 100644 drivers/mmc/host/mxc_mmc.h create mode 100644 drivers/mmc/host/mxs-mmc.c create mode 100644 drivers/mtd/devices/mxc_dataflash.c create mode 100644 drivers/mtd/maps/mxc_nor.c create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h create mode 100644 drivers/mtd/nand/imx_nfc.c create mode 100644 drivers/mtd/nand/mxc_nd.c create mode 100644 drivers/mtd/nand/mxc_nd.h create mode 100644 drivers/mtd/nand/mxc_nd2.c create mode 100644 drivers/mtd/nand/mxc_nd2.h create mode 100644 drivers/mtd/nand/nand_device_info.c create mode 100644 drivers/mtd/nand/nand_device_info.h create mode 100644 drivers/mtd/ubiblock.c create mode 100644 drivers/mxc/Kconfig create mode 100644 drivers/mxc/Makefile create mode 100644 drivers/mxc/adc/Kconfig create mode 100644 drivers/mxc/adc/Makefile create mode 100644 drivers/mxc/adc/imx_adc.c create mode 100644 drivers/mxc/adc/imx_adc_reg.h create mode 100644 drivers/mxc/amd-gpu/Kconfig create mode 100644 drivers/mxc/amd-gpu/Makefile create mode 100644 drivers/mxc/amd-gpu/common/gsl_cmdstream.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_cmdwindow.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_context.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_debug_pm4.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_device.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_drawctxt.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_driver.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_g12.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_intrmgr.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_log.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_memmgr.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_mmu.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_ringbuffer.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_sharedmem.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_tbdump.c create mode 100644 drivers/mxc/amd-gpu/common/gsl_yamato.c create mode 100644 drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl create mode 100644 drivers/mxc/amd-gpu/common/pm4_microcode.inl create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_displayapi.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_klibapi.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_libapi.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_pm4types.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_properties.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_types.h create mode 100644 drivers/mxc/amd-gpu/include/api/gsl_utils.h create mode 100644 drivers/mxc/amd-gpu/include/gsl.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_buildconfig.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_cmdstream.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_cmdwindow.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_config.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_context.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_debug.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_device.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_display.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_drawctxt.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_driver.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_hal.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_halconfig.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_intrmgr.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_ioctl.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_log.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_memmgr.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_mmu.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_ringbuffer.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_sharedmem.h create mode 100644 drivers/mxc/amd-gpu/include/gsl_tbdump.h create mode 100644 drivers/mxc/amd-gpu/include/reg/g12_reg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h create mode 100644 drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h create mode 100644 drivers/mxc/amd-gpu/os/include/os_types.h create mode 100644 drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h create mode 100644 drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h create mode 100644 drivers/mxc/amd-gpu/platform/hal/linux/misc.c create mode 100644 drivers/mxc/asrc/Kconfig create mode 100644 drivers/mxc/asrc/Makefile create mode 100644 drivers/mxc/asrc/mxc_asrc.c create mode 100644 drivers/mxc/bt/Kconfig create mode 100644 drivers/mxc/bt/Makefile create mode 100644 drivers/mxc/bt/mxc_bt.c create mode 100644 drivers/mxc/dam/Kconfig create mode 100644 drivers/mxc/dam/Makefile create mode 100644 drivers/mxc/dam/dam.c create mode 100644 drivers/mxc/dam/dam.h create mode 100644 drivers/mxc/dam/dam_v1.c create mode 100644 drivers/mxc/gps_ioctrl/Kconfig create mode 100644 drivers/mxc/gps_ioctrl/Makefile create mode 100644 drivers/mxc/gps_ioctrl/agpsgpiodev.c create mode 100644 drivers/mxc/gps_ioctrl/agpsgpiodev.h create mode 100644 drivers/mxc/hmp4e/Kconfig create mode 100644 drivers/mxc/hmp4e/Makefile create mode 100644 drivers/mxc/hmp4e/mxc_hmp4e.c create mode 100644 drivers/mxc/hmp4e/mxc_hmp4e.h create mode 100644 drivers/mxc/hw_event/Kconfig create mode 100644 drivers/mxc/hw_event/Makefile create mode 100644 drivers/mxc/hw_event/mxc_hw_event.c create mode 100644 drivers/mxc/ipu/Kconfig create mode 100644 drivers/mxc/ipu/Makefile create mode 100644 drivers/mxc/ipu/ipu_adc.c create mode 100644 drivers/mxc/ipu/ipu_calc_stripes_sizes.c create mode 100644 drivers/mxc/ipu/ipu_common.c create mode 100644 drivers/mxc/ipu/ipu_csi.c create mode 100644 drivers/mxc/ipu/ipu_device.c create mode 100644 drivers/mxc/ipu/ipu_ic.c create mode 100644 drivers/mxc/ipu/ipu_param_mem.h create mode 100644 drivers/mxc/ipu/ipu_prv.h create mode 100644 drivers/mxc/ipu/ipu_regs.h create mode 100644 drivers/mxc/ipu/ipu_sdc.c create mode 100644 drivers/mxc/ipu/pf/Kconfig create mode 100644 drivers/mxc/ipu/pf/Makefile create mode 100644 drivers/mxc/ipu/pf/mxc_pf.c create mode 100644 drivers/mxc/ipu3/Kconfig create mode 100644 drivers/mxc/ipu3/Makefile create mode 100644 drivers/mxc/ipu3/ipu_calc_stripes_sizes.c create mode 100644 drivers/mxc/ipu3/ipu_capture.c create mode 100644 drivers/mxc/ipu3/ipu_common.c create mode 100644 drivers/mxc/ipu3/ipu_device.c create mode 100644 drivers/mxc/ipu3/ipu_disp.c create mode 100644 drivers/mxc/ipu3/ipu_ic.c create mode 100644 drivers/mxc/ipu3/ipu_param_mem.h create mode 100644 drivers/mxc/ipu3/ipu_prv.h create mode 100644 drivers/mxc/ipu3/ipu_regs.h create mode 100644 drivers/mxc/mcu_pmic/Kconfig create mode 100644 drivers/mxc/mcu_pmic/Makefile create mode 100644 drivers/mxc/mcu_pmic/max8660.c create mode 100644 drivers/mxc/mcu_pmic/max8660.h create mode 100644 drivers/mxc/mcu_pmic/mc9s08dz60.c create mode 100644 drivers/mxc/mcu_pmic/mc9s08dz60.h create mode 100644 drivers/mxc/mcu_pmic/mcu_pmic_core.c create mode 100644 drivers/mxc/mcu_pmic/mcu_pmic_core.h create mode 100644 drivers/mxc/mcu_pmic/mcu_pmic_gpio.c create mode 100644 drivers/mxc/mlb/Kconfig create mode 100644 drivers/mxc/mlb/Makefile create mode 100644 drivers/mxc/mlb/mxc_mlb.c create mode 100644 drivers/mxc/pmic/Kconfig create mode 100644 drivers/mxc/pmic/Makefile create mode 100644 drivers/mxc/pmic/core/Makefile create mode 100644 drivers/mxc/pmic/core/mc13783.c create mode 100644 drivers/mxc/pmic/core/mc13892.c create mode 100644 drivers/mxc/pmic/core/mc34704.c create mode 100644 drivers/mxc/pmic/core/pmic-dev.c create mode 100644 drivers/mxc/pmic/core/pmic.h create mode 100644 drivers/mxc/pmic/core/pmic_common.c create mode 100644 drivers/mxc/pmic/core/pmic_core_i2c.c create mode 100644 drivers/mxc/pmic/core/pmic_core_spi.c create mode 100644 drivers/mxc/pmic/core/pmic_event.c create mode 100644 drivers/mxc/pmic/core/pmic_external.c create mode 100644 drivers/mxc/pmic/mc13783/Kconfig create mode 100644 drivers/mxc/pmic/mc13783/Makefile create mode 100644 drivers/mxc/pmic/mc13783/pmic_adc.c create mode 100644 drivers/mxc/pmic/mc13783/pmic_adc_defs.h create mode 100644 drivers/mxc/pmic/mc13783/pmic_audio.c create mode 100644 drivers/mxc/pmic/mc13783/pmic_battery.c create mode 100644 drivers/mxc/pmic/mc13783/pmic_battery_defs.h create mode 100644 drivers/mxc/pmic/mc13783/pmic_convity.c create mode 100644 drivers/mxc/pmic/mc13783/pmic_light.c create mode 100644 drivers/mxc/pmic/mc13783/pmic_light_defs.h create mode 100644 drivers/mxc/pmic/mc13783/pmic_power.c create mode 100644 drivers/mxc/pmic/mc13783/pmic_power_defs.h create mode 100644 drivers/mxc/pmic/mc13783/pmic_rtc.c create mode 100644 drivers/mxc/pmic/mc13783/pmic_rtc_defs.h create mode 100644 drivers/mxc/pmic/mc13892/Kconfig create mode 100644 drivers/mxc/pmic/mc13892/Makefile create mode 100644 drivers/mxc/pmic/mc13892/pmic_adc.c create mode 100644 drivers/mxc/pmic/mc13892/pmic_battery.c create mode 100644 drivers/mxc/pmic/mc13892/pmic_light.c create mode 100644 drivers/mxc/security/Kconfig create mode 100644 drivers/mxc/security/Makefile create mode 100644 drivers/mxc/security/dryice-regs.h create mode 100644 drivers/mxc/security/dryice.c create mode 100644 drivers/mxc/security/dryice.h create mode 100644 drivers/mxc/security/mxc_scc.c create mode 100644 drivers/mxc/security/mxc_scc_internals.h create mode 100644 drivers/mxc/security/rng/Makefile create mode 100644 drivers/mxc/security/rng/des_key.c create mode 100644 drivers/mxc/security/rng/fsl_shw_hash.c create mode 100644 drivers/mxc/security/rng/fsl_shw_hmac.c create mode 100644 drivers/mxc/security/rng/fsl_shw_rand.c create mode 100644 drivers/mxc/security/rng/fsl_shw_sym.c create mode 100644 drivers/mxc/security/rng/fsl_shw_wrap.c create mode 100644 drivers/mxc/security/rng/include/rng_driver.h create mode 100644 drivers/mxc/security/rng/include/rng_internals.h create mode 100644 drivers/mxc/security/rng/include/rng_rnga.h create mode 100644 drivers/mxc/security/rng/include/rng_rngc.h create mode 100644 drivers/mxc/security/rng/include/shw_driver.h create mode 100644 drivers/mxc/security/rng/include/shw_hash.h create mode 100644 drivers/mxc/security/rng/include/shw_hmac.h create mode 100644 drivers/mxc/security/rng/include/shw_internals.h create mode 100644 drivers/mxc/security/rng/rng_driver.c create mode 100644 drivers/mxc/security/rng/shw_driver.c create mode 100644 drivers/mxc/security/rng/shw_dryice.c create mode 100644 drivers/mxc/security/rng/shw_hash.c create mode 100644 drivers/mxc/security/rng/shw_hmac.c create mode 100644 drivers/mxc/security/rng/shw_memory_mapper.c create mode 100644 drivers/mxc/security/sahara2/Kconfig create mode 100644 drivers/mxc/security/sahara2/Makefile create mode 100644 drivers/mxc/security/sahara2/fsl_shw_auth.c create mode 100644 drivers/mxc/security/sahara2/fsl_shw_hash.c create mode 100644 drivers/mxc/security/sahara2/fsl_shw_hmac.c create mode 100644 drivers/mxc/security/sahara2/fsl_shw_keystore.c create mode 100644 drivers/mxc/security/sahara2/fsl_shw_rand.c create mode 100644 drivers/mxc/security/sahara2/fsl_shw_sym.c create mode 100644 drivers/mxc/security/sahara2/fsl_shw_user.c create mode 100644 drivers/mxc/security/sahara2/fsl_shw_wrap.c create mode 100644 drivers/mxc/security/sahara2/include/adaptor.h create mode 100644 drivers/mxc/security/sahara2/include/diagnostic.h create mode 100644 drivers/mxc/security/sahara2/include/fsl_platform.h create mode 100644 drivers/mxc/security/sahara2/include/fsl_shw.h create mode 100644 drivers/mxc/security/sahara2/include/fsl_shw_keystore.h create mode 100644 drivers/mxc/security/sahara2/include/linux_port.h create mode 100644 drivers/mxc/security/sahara2/include/platform_abstractions.h create mode 100644 drivers/mxc/security/sahara2/include/portable_os.h create mode 100644 drivers/mxc/security/sahara2/include/sah_driver_common.h create mode 100644 drivers/mxc/security/sahara2/include/sah_hardware_interface.h create mode 100644 drivers/mxc/security/sahara2/include/sah_interrupt_handler.h create mode 100644 drivers/mxc/security/sahara2/include/sah_kernel.h create mode 100644 drivers/mxc/security/sahara2/include/sah_memory_mapper.h create mode 100644 drivers/mxc/security/sahara2/include/sah_queue_manager.h create mode 100644 drivers/mxc/security/sahara2/include/sah_status_manager.h create mode 100644 drivers/mxc/security/sahara2/include/sahara.h create mode 100644 drivers/mxc/security/sahara2/include/sahara2_kernel.h create mode 100644 drivers/mxc/security/sahara2/include/sf_util.h create mode 100644 drivers/mxc/security/sahara2/km_adaptor.c create mode 100644 drivers/mxc/security/sahara2/sah_driver_interface.c create mode 100644 drivers/mxc/security/sahara2/sah_hardware_interface.c create mode 100644 drivers/mxc/security/sahara2/sah_interrupt_handler.c create mode 100644 drivers/mxc/security/sahara2/sah_memory_mapper.c create mode 100644 drivers/mxc/security/sahara2/sah_queue.c create mode 100644 drivers/mxc/security/sahara2/sah_queue_manager.c create mode 100644 drivers/mxc/security/sahara2/sah_status_manager.c create mode 100644 drivers/mxc/security/sahara2/sf_util.c create mode 100644 drivers/mxc/security/scc2_driver.c create mode 100644 drivers/mxc/security/scc2_internals.h create mode 100644 drivers/mxc/ssi/Kconfig create mode 100644 drivers/mxc/ssi/Makefile create mode 100644 drivers/mxc/ssi/registers.h create mode 100644 drivers/mxc/ssi/ssi.c create mode 100644 drivers/mxc/ssi/ssi.h create mode 100644 drivers/mxc/ssi/ssi_types.h create mode 100644 drivers/mxc/vpu/Kconfig create mode 100644 drivers/mxc/vpu/Makefile create mode 100644 drivers/mxc/vpu/mxc_vl2cc.c create mode 100644 drivers/mxc/vpu/mxc_vpu.c create mode 100644 drivers/net/can/flexcan/Makefile create mode 100644 drivers/net/can/flexcan/dev.c create mode 100644 drivers/net/can/flexcan/drv.c create mode 100644 drivers/net/can/flexcan/flexcan.h create mode 100644 drivers/net/can/flexcan/mbm.c create mode 100644 drivers/net/fec_1588.c create mode 100644 drivers/net/fec_1588.h create mode 100644 drivers/net/fec_switch.c create mode 100644 drivers/net/fec_switch.h create mode 100644 drivers/net/imx_ptp.c create mode 100644 drivers/net/imx_ptp.h create mode 100644 drivers/net/irda/mxc_ir.c create mode 100644 drivers/net/irda/mxc_ir.h create mode 100644 drivers/net/wireless/ath6kl/Kconfig create mode 100644 drivers/net/wireless/ath6kl/Makefile create mode 100644 drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h create mode 100644 drivers/net/wireless/ath6kl/bmi/src/bmi.c create mode 100644 drivers/net/wireless/ath6kl/bmi/src/makefile create mode 100644 drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h create mode 100644 drivers/net/wireless/ath6kl/hif/sdio/Makefile create mode 100644 drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h create mode 100644 drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt create mode 100644 drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c create mode 100644 drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c create mode 100644 drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c create mode 100644 drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h create mode 100644 drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c create mode 100644 drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c create mode 100644 drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c create mode 100644 drivers/net/wireless/ath6kl/htc2/AR6000/makefile create mode 100644 drivers/net/wireless/ath6kl/htc2/htc.c create mode 100644 drivers/net/wireless/ath6kl/htc2/htc_debug.h create mode 100644 drivers/net/wireless/ath6kl/htc2/htc_internal.h create mode 100644 drivers/net/wireless/ath6kl/htc2/htc_recv.c create mode 100644 drivers/net/wireless/ath6kl/htc2/htc_send.c create mode 100644 drivers/net/wireless/ath6kl/htc2/htc_services.c create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/addrs.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h create mode 100644 drivers/net/wireless/ath6kl/include/a_config.h create mode 100644 drivers/net/wireless/ath6kl/include/a_debug.h create mode 100644 drivers/net/wireless/ath6kl/include/a_drv.h create mode 100644 drivers/net/wireless/ath6kl/include/a_drv_api.h create mode 100644 drivers/net/wireless/ath6kl/include/a_hci.h create mode 100644 drivers/net/wireless/ath6kl/include/a_osapi.h create mode 100644 drivers/net/wireless/ath6kl/include/a_types.h create mode 100644 drivers/net/wireless/ath6kl/include/aggr_recv_api.h create mode 100644 drivers/net/wireless/ath6kl/include/ar3kconfig.h create mode 100644 drivers/net/wireless/ath6kl/include/ar6000_api.h create mode 100644 drivers/net/wireless/ath6kl/include/ar6000_diag.h create mode 100644 drivers/net/wireless/ath6kl/include/ar6kap_common.h create mode 100644 drivers/net/wireless/ath6kl/include/athbtfilter.h create mode 100644 drivers/net/wireless/ath6kl/include/athdefs.h create mode 100644 drivers/net/wireless/ath6kl/include/athendpack.h create mode 100644 drivers/net/wireless/ath6kl/include/athstartpack.h create mode 100644 drivers/net/wireless/ath6kl/include/bmi.h create mode 100644 drivers/net/wireless/ath6kl/include/bmi_msg.h create mode 100644 drivers/net/wireless/ath6kl/include/btcoexGpio.h create mode 100644 drivers/net/wireless/ath6kl/include/cnxmgmt.h create mode 100644 drivers/net/wireless/ath6kl/include/common_drv.h create mode 100644 drivers/net/wireless/ath6kl/include/dbglog.h create mode 100644 drivers/net/wireless/ath6kl/include/dbglog_api.h create mode 100644 drivers/net/wireless/ath6kl/include/dbglog_id.h create mode 100644 drivers/net/wireless/ath6kl/include/discovery.h create mode 100644 drivers/net/wireless/ath6kl/include/dl_list.h create mode 100644 drivers/net/wireless/ath6kl/include/dset_api.h create mode 100644 drivers/net/wireless/ath6kl/include/dset_internal.h create mode 100644 drivers/net/wireless/ath6kl/include/dsetid.h create mode 100644 drivers/net/wireless/ath6kl/include/epping_test.h create mode 100644 drivers/net/wireless/ath6kl/include/gmboxif.h create mode 100644 drivers/net/wireless/ath6kl/include/gpio.h create mode 100644 drivers/net/wireless/ath6kl/include/gpio_api.h create mode 100644 drivers/net/wireless/ath6kl/include/hci_transport_api.h create mode 100644 drivers/net/wireless/ath6kl/include/hif.h create mode 100644 drivers/net/wireless/ath6kl/include/host_version.h create mode 100644 drivers/net/wireless/ath6kl/include/htc.h create mode 100644 drivers/net/wireless/ath6kl/include/htc_api.h create mode 100644 drivers/net/wireless/ath6kl/include/htc_packet.h create mode 100644 drivers/net/wireless/ath6kl/include/htc_services.h create mode 100644 drivers/net/wireless/ath6kl/include/ini_dset.h create mode 100644 drivers/net/wireless/ath6kl/include/pkt_log.h create mode 100644 drivers/net/wireless/ath6kl/include/regdump.h create mode 100644 drivers/net/wireless/ath6kl/include/roaming.h create mode 100644 drivers/net/wireless/ath6kl/include/targaddrs.h create mode 100644 drivers/net/wireless/ath6kl/include/target_reg_table.h create mode 100644 drivers/net/wireless/ath6kl/include/testcmd.h create mode 100644 drivers/net/wireless/ath6kl/include/wlan_api.h create mode 100644 drivers/net/wireless/ath6kl/include/wlan_defs.h create mode 100644 drivers/net/wireless/ath6kl/include/wlan_dset.h create mode 100644 drivers/net/wireless/ath6kl/include/wmi.h create mode 100644 drivers/net/wireless/ath6kl/include/wmi_api.h create mode 100644 drivers/net/wireless/ath6kl/include/wmi_thin.h create mode 100644 drivers/net/wireless/ath6kl/include/wmix.h create mode 100644 drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c create mode 100644 drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c create mode 100644 drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h create mode 100644 drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c create mode 100644 drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.h create mode 100644 drivers/net/wireless/ath6kl/miscdrv/common_drv.c create mode 100644 drivers/net/wireless/ath6kl/miscdrv/credit_dist.c create mode 100644 drivers/net/wireless/ath6kl/miscdrv/makefile create mode 100644 drivers/net/wireless/ath6kl/miscdrv/miscdrv.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/ar6000_android.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/cfg80211.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/eeprom.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/hci_bridge.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/config_linux.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h create mode 100644 drivers/net/wireless/ath6kl/os/linux/ioctl.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/netbuf.c create mode 100644 drivers/net/wireless/ath6kl/os/linux/wireless_ext.c create mode 100644 drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h create mode 100644 drivers/net/wireless/ath6kl/reorder/makefile create mode 100644 drivers/net/wireless/ath6kl/reorder/rcv_aggr.c create mode 100644 drivers/net/wireless/ath6kl/wlan/include/ieee80211.h create mode 100644 drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h create mode 100644 drivers/net/wireless/ath6kl/wlan/src/makefile create mode 100644 drivers/net/wireless/ath6kl/wlan/src/wlan_node.c create mode 100644 drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c create mode 100644 drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c create mode 100644 drivers/net/wireless/ath6kl/wmi/makefile create mode 100644 drivers/net/wireless/ath6kl/wmi/wmi.c create mode 100644 drivers/net/wireless/ath6kl/wmi/wmi_host.h create mode 100644 drivers/pcmcia/mx31ads-pcmcia.c create mode 100644 drivers/pcmcia/mx31ads-pcmcia.h create mode 100644 drivers/power/da9052-battery.c create mode 100644 drivers/power/ds2438_battery.c create mode 100644 drivers/power/mxs/Makefile create mode 100644 drivers/power/mxs/ddi_bc_api.c create mode 100644 drivers/power/mxs/ddi_bc_hw.c create mode 100644 drivers/power/mxs/ddi_bc_hw.h create mode 100644 drivers/power/mxs/ddi_bc_init.c create mode 100644 drivers/power/mxs/ddi_bc_internal.h create mode 100644 drivers/power/mxs/ddi_bc_ramp.c create mode 100644 drivers/power/mxs/ddi_bc_ramp.h create mode 100644 drivers/power/mxs/ddi_bc_sm.c create mode 100644 drivers/power/mxs/ddi_bc_sm.h create mode 100644 drivers/power/mxs/ddi_power_battery.c create mode 100644 drivers/power/mxs/ddi_power_battery.h create mode 100644 drivers/power/mxs/fiq.S create mode 100644 drivers/power/mxs/linux.c create mode 100644 drivers/regulator/da9052-regulator.c create mode 100644 drivers/regulator/ltc3589-regulator.c create mode 100644 drivers/regulator/max17135-regulator.c create mode 100644 drivers/regulator/mxs-regulator.c create mode 100644 drivers/regulator/reg-mc13783.c create mode 100644 drivers/regulator/reg-mc13892.c create mode 100644 drivers/regulator/reg-mc34704.c create mode 100644 drivers/regulator/reg-mc9s08dz60.c create mode 100644 drivers/rtc/rtc-da9052.c create mode 100644 drivers/rtc/rtc-imxdi.c create mode 100644 drivers/rtc/rtc-mc13892.c create mode 100644 drivers/rtc/rtc-mxc_v2.c create mode 100644 drivers/rtc/rtc-mxs.c create mode 100644 drivers/serial/mxc_uart.c create mode 100644 drivers/serial/mxc_uart_early.c create mode 100644 drivers/serial/mxc_uart_reg.h create mode 100644 drivers/serial/mxs-auart.c create mode 100644 drivers/serial/mxs-duart.c create mode 100644 drivers/serial/regs-duart.h create mode 100644 drivers/serial/regs-uartapp.h create mode 100644 drivers/spi/mxc_spi.c create mode 100644 drivers/spi/spi_mxs.c create mode 100644 drivers/spi/spi_mxs.h create mode 100644 drivers/spi/spi_sam.c create mode 100644 drivers/staging/android/Kconfig create mode 100644 drivers/staging/android/Makefile create mode 100644 drivers/staging/android/TODO create mode 100644 drivers/staging/android/binder.c create mode 100644 drivers/staging/android/binder.h create mode 100644 drivers/staging/android/logger.c create mode 100644 drivers/staging/android/logger.h create mode 100644 drivers/staging/android/lowmemorykiller.c create mode 100644 drivers/usb/gadget/arcotg_udc.c create mode 100644 drivers/usb/gadget/arcotg_udc.h create mode 100644 drivers/usb/gadget/fsl_updater.c create mode 100644 drivers/usb/gadget/fsl_updater.h create mode 100644 drivers/usb/gadget/stmp_updater.c create mode 100644 drivers/usb/gadget/stmp_updater.h create mode 100644 drivers/usb/host/ehci-arc.c create mode 100644 drivers/usb/host/ehci-mem-iram.c create mode 100644 drivers/usb/host/ehci-q-iram.c create mode 100644 drivers/usb/otg/fsl_otg.c create mode 100644 drivers/usb/otg/fsl_otg.h create mode 100644 drivers/usb/otg/otg_fsm.c create mode 100644 drivers/usb/otg/otg_fsm.h create mode 100644 drivers/video/backlight/da9052_bl.c create mode 100644 drivers/video/backlight/mxc_ipu_bl.c create mode 100644 drivers/video/backlight/mxc_lcdc_bl.c create mode 100644 drivers/video/backlight/mxc_mc13892_bl.c create mode 100644 drivers/video/backlight/mxc_pmic_bl.c create mode 100644 drivers/video/backlight/mxs_bl.c create mode 100644 drivers/video/backlight/wm8350_bl.c create mode 100644 drivers/video/mxc/Kconfig create mode 100644 drivers/video/mxc/Makefile create mode 100644 drivers/video/mxc/ch7024.c create mode 100644 drivers/video/mxc/elcdif_regs.h create mode 100644 drivers/video/mxc/epdc_regs.h create mode 100644 drivers/video/mxc/ldb.c create mode 100644 drivers/video/mxc/mx2fb.c create mode 100644 drivers/video/mxc/mx2fb.h create mode 100644 drivers/video/mxc/mxc_edid.c create mode 100644 drivers/video/mxc/mxc_elcdif_fb.c create mode 100644 drivers/video/mxc/mxc_epdc_fb.c create mode 100644 drivers/video/mxc/mxc_ipuv3_fb.c create mode 100644 drivers/video/mxc/mxcfb.c create mode 100644 drivers/video/mxc/mxcfb_ch7026.c create mode 100644 drivers/video/mxc/mxcfb_claa_wvga.c create mode 100644 drivers/video/mxc/mxcfb_epson.c create mode 100644 drivers/video/mxc/mxcfb_epson_vga.c create mode 100644 drivers/video/mxc/mxcfb_modedb.c create mode 100644 drivers/video/mxc/mxcfb_seiko_wvga.c create mode 100644 drivers/video/mxc/tve.c create mode 100644 drivers/video/mxs/Kconfig create mode 100644 drivers/video/mxs/Makefile create mode 100644 drivers/video/mxs/lcd_43wvf1g.c create mode 100644 drivers/video/mxs/lcd_lms430.c create mode 100644 drivers/video/mxs/lcdif.c create mode 100644 drivers/video/mxs/mxsfb.c create mode 100644 drivers/video/mxs/regs-tvenc.h create mode 100644 drivers/video/mxs/tvenc.c create mode 100644 drivers/w1/slaves/w1_ds2438.c create mode 100644 drivers/w1/slaves/w1_ds2438.h create mode 100644 drivers/w1/slaves/w1_ds2751.c create mode 100644 drivers/watchdog/da9052_wdt.c create mode 100644 drivers/watchdog/mxc_wdt.c create mode 100644 drivers/watchdog/mxc_wdt.h create mode 100644 drivers/watchdog/mxs-wdt.c create mode 100644 firmware/imx/epdc_E60_V110.fw.ihex create mode 100644 firmware/imx/epdc_E60_V220.fw.ihex create mode 100644 firmware/imx/epdc_E97_V110.fw.ihex create mode 100644 include/linux/android_pmem.h create mode 100644 include/linux/ashmem.h create mode 100644 include/linux/cryptodev.h create mode 100644 include/linux/gpmi-nfc.h create mode 100644 include/linux/i2c/mpr.h create mode 100644 include/linux/imx_adc.h create mode 100644 include/linux/ipu.h create mode 100644 include/linux/iram_alloc.h create mode 100644 include/linux/ldb.h create mode 100644 include/linux/mfd/da9052/adc.h create mode 100644 include/linux/mfd/da9052/bat.h create mode 100644 include/linux/mfd/da9052/bl.h create mode 100644 include/linux/mfd/da9052/da9052.h create mode 100644 include/linux/mfd/da9052/eh.h create mode 100644 include/linux/mfd/da9052/gpio.h create mode 100644 include/linux/mfd/da9052/led.h create mode 100644 include/linux/mfd/da9052/pm.h create mode 100644 include/linux/mfd/da9052/reg.h create mode 100644 include/linux/mfd/da9052/rtc.h create mode 100644 include/linux/mfd/da9052/tsi.h create mode 100644 include/linux/mfd/da9052/tsi_calibrate.h create mode 100644 include/linux/mfd/da9052/tsi_cfg.h create mode 100644 include/linux/mfd/da9052/tsi_filter.h create mode 100644 include/linux/mfd/da9052/wdt.h create mode 100644 include/linux/mfd/ltc3589/core.h create mode 100644 include/linux/mfd/max17135.h create mode 100644 include/linux/mfd/mc13783/core.h create mode 100644 include/linux/mfd/mc13892/core.h create mode 100644 include/linux/mfd/mc34704/core.h create mode 100644 include/linux/mfd/mc9s08dz60/core.h create mode 100644 include/linux/mfd/mc9s08dz60/pmic.h create mode 100644 include/linux/mfd/wm8350/bl.h create mode 100644 include/linux/mxc_asrc.h create mode 100644 include/linux/mxc_mlb.h create mode 100644 include/linux/mxc_pf.h create mode 100644 include/linux/mxc_scc2_driver.h create mode 100644 include/linux/mxc_scc_driver.h create mode 100644 include/linux/mxc_si4702.h create mode 100644 include/linux/mxc_sim_interface.h create mode 100644 include/linux/mxc_srtc.h create mode 100644 include/linux/mxc_v4l2.h create mode 100644 include/linux/mxcfb.h create mode 100644 include/linux/mxcfb_epdc_kernel.h create mode 100644 include/linux/pmic_adc.h create mode 100644 include/linux/pmic_battery.h create mode 100644 include/linux/pmic_external.h create mode 100644 include/linux/pmic_light.h create mode 100644 include/linux/pmic_rtc.h create mode 100644 include/linux/pmic_status.h create mode 100644 include/linux/powerkey.h create mode 100644 include/linux/pxp_dma.h create mode 100644 include/linux/regulator/da9052-regulator.h create mode 100644 include/linux/regulator/ltc3589.h create mode 100644 include/linux/uid_stat.h create mode 100644 include/linux/usb/fsl_xcvr.h create mode 100644 localversion create mode 100644 mm/ashmem.c create mode 100644 sound/arm/mxc-alsa-common.h create mode 100644 sound/arm/mxc-alsa-mixer.c create mode 100644 sound/arm/mxc-alsa-pmic.c create mode 100644 sound/arm/mxc-alsa-pmic.h create mode 100644 sound/arm/mxc-alsa-spdif.c create mode 100644 sound/soc/codecs/ak4647.c create mode 100644 sound/soc/codecs/ak4647.h create mode 100644 sound/soc/codecs/ak5702.c create mode 100644 sound/soc/codecs/ak5702.h create mode 100644 sound/soc/codecs/bluetooth.c create mode 100644 sound/soc/codecs/cs42888.c create mode 100644 sound/soc/codecs/cs42888.h create mode 100644 sound/soc/codecs/mxs-adc-codec.c create mode 100644 sound/soc/codecs/mxs-adc-codec.h create mode 100644 sound/soc/codecs/mxs_spdif.c create mode 100644 sound/soc/codecs/mxs_spdif.h create mode 100644 sound/soc/codecs/sgtl5000.c create mode 100644 sound/soc/codecs/sgtl5000.h create mode 100644 sound/soc/imx/imx-3stack-ak4647.c create mode 100644 sound/soc/imx/imx-3stack-ak5702.c create mode 100644 sound/soc/imx/imx-3stack-bt.c create mode 100644 sound/soc/imx/imx-3stack-bt.h create mode 100644 sound/soc/imx/imx-3stack-cs42888.c create mode 100644 sound/soc/imx/imx-3stack-sgtl5000.c create mode 100644 sound/soc/imx/imx-3stack-wm8350.c create mode 100644 sound/soc/imx/imx-3stack-wm8580.c create mode 100644 sound/soc/imx/imx-ac97.c create mode 100644 sound/soc/imx/imx-esai.c create mode 100644 sound/soc/imx/imx-esai.h create mode 100644 sound/soc/imx/imx-pcm.c create mode 100644 sound/soc/imx/imx-pcm.h create mode 100644 sound/soc/mxs/Kconfig create mode 100644 sound/soc/mxs/Makefile create mode 100644 sound/soc/mxs/mxs-adc.c create mode 100644 sound/soc/mxs/mxs-adc.h create mode 100644 sound/soc/mxs/mxs-dai.c create mode 100644 sound/soc/mxs/mxs-dai.h create mode 100644 sound/soc/mxs/mxs-devb-spdif.c create mode 100644 sound/soc/mxs/mxs-devb.c create mode 100644 sound/soc/mxs/mxs-evk-adc.c create mode 100644 sound/soc/mxs/mxs-pcm.c create mode 100644 sound/soc/mxs/mxs-pcm.h create mode 100644 sound/soc/mxs/mxs-spdif-dai.c create mode 100644 sound/soc/mxs/mxs-spdif-dai.h diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting index 76850295af8f..ec228a472bec 100644 --- a/Documentation/arm/Booting +++ b/Documentation/arm/Booting @@ -126,6 +126,7 @@ In either case, the following conditions must be met: r0 = 0, r1 = machine type number discovered in (3) above. r2 = physical address of tagged list in system RAM. + r3 = PHYS_OFFSET - CPU mode All forms of interrupts must be disabled (IRQs and FIQs) diff --git a/Documentation/imx_nfc.txt b/Documentation/imx_nfc.txt new file mode 100644 index 000000000000..7fec999c2884 --- /dev/null +++ b/Documentation/imx_nfc.txt @@ -0,0 +1,369 @@ +i.MX NAND Flash Controller Driver Documentation +=============================================== + + +Definitions of Terms +==================== + +To avoid confusion, let's carefully define some of the terms we'll be using: + + "NAND Flash Chip" or "Chip" + A NAND Flash storage array and controller (including a chip select + signal, ready/busy signal, data register, etc.). + + "NAND Flash Package" or "Package" + A hardware package containing one or more NAND Flash chips that share + data lines and most control signals, but with separate chip select + and ready/busy signals. Package "boundaries" are unimportant to MTD. + + "NAND Flash Medium" or "Medium" + A collection of one or more NAND Flash chips that the system views as + logically contiguous. + + "Memory Technology Device" or "MTD" + An abstraction of underlying memory hardware, represented by a single + struct mtd_info. + + "NAND Flash MTD" + An abstraction of a NAND Flash medium that is represented by a single + struct nand_chip (the name of this structure is misleading because it + has evolved to represent an entire medium, not just a single chip). + All the physical chips in a NAND Flash MTD medium have answered the + "Read ID" command with the same manufacturer code and device code and + are presumed to have identical characteristics. + + "NAND Flash MTD Hardware-independent Layer" or "HIL" + The code that implements an MTD interface and drives all NAND Flash + MTDs. + + "NAND Flash MTD Hardware Abstraction Layer" or "HAL" + Code that implements the internal NAND Flash hardware model and + matches it to specific hardware. + + "NAND Flash MTD Reference Implementation" + A reference implementation of a HAL "stack." + + "Out-of-Band" or "OOB" + An adjective describing information that is not part of the "data" in + a NAND Flash page. NAND Flash pages are generally described in terms + of the amount of data they can hold (e.g., "2K pages" or "4K pages"). + The physical page size is actually larger than this and the + additional bytes are called "out-of-band." + + + +The Structure of the MTD NAND Flash System +========================================== + +The following figure illustrates how control flows down from the system's +MTD interface into the NAND Flash MTD system and down to the hardware- +specific implementation (this driver): + + + + / +---------------------------------------+ + | | MTD | + | +---------------------------------------+ + MTD | | + | | +----------+ + | | | | + | v v | + \ ======================================== | + - struct mtd_info | + / ======================================== | + | | | + | v | + | +---------------------------------------+ | + | | NAND Flash MTD | | + NAND Flash | | Interface Functions | | + Hardware- | +---------------------------------------+ | + Independent | | | | + Layer | | v | + (HIL) | +-------------+ | +-------------+ +-------------+ + | | Init | | | Support | | Reference | + | | Functions | | | Functions | |BBT Functions| + | +-------------+ | +-------------+ +-------------+ + | | | | ^ + | v v v | + \ ======================================== | + - struct nand_chip | + / ======================================== | + | | ^ | ^ | | + NAND Flash | | | | | | | + Hardware | v | v | | | + Abstraction | +--------------+ +---------------+ | | + Layer | | Hardware- | | Reference | +-----------+ + (HAL) | | Specific | | | + | |Implementation| |Implementations| + \ +--------------+ +---------------+ + + + +The function pointers and attributes in struct mtd_info embody an abstract +model of memory technology devices. + +The struct nand_chip is an aggregation of two categories of function pointers +and attributes: + + - Function pointers and attributes used by the HIL. These members embody + an abstract model of NAND Flash media, or a hardware abstraction + layer (HAL). + + - Function pointers and attributes used by the reference implementations. + +The single most confusing thing about the MTD NAND Flash system is that +struct nand_chip contains all the main HAL members mixed up with all the +members used only by the reference implementation, without any clear +distinction. Recognizing the distinction is critical for understanding the +relationship between the HIL and HAL, and can greatly simplify driver +implementation. + +The fundamental operations represented by the function pointers in +struct nand_chip fall into the following categories (from conceptually +"low-level" to "high-level"): + + - Signal Control + - Chip Control + - Low-level I/O + - ECC Control + - ECC-aware I/O + - Error Recovery + - High-level I/O + - Bad Block Management + +The HIL uses only the following "Replaceable" function pointers in +struct nand_chip: + + - Signal Control + - None + - Chip Control + - dev_ready + - select_chip + - cmdfunc + - waitfunc + - Low-level I/O + - read_byte + - ECC Control + - None + - ECC-aware I/O + - ecc.read_page + - ecc.read_page_raw + - Error Recovery + - None + - High-level I/O + - write_page + - ecc.read_oob + - ecc.write_oob + - Bad Block Management + - block_bad + - block_markbad + - scan_bbt + +Note that the HIL calls erase_cmd, but this member is marked "Internal." + +The HIL uses only the following commands with cmdfunc: + + * NAND_CMD_STATUS + - nand_check_wp() - Checks if the current chip is + write-protected. + * NAND_CMD_READID + - nand_get_flash_type() - Gets information about the first chip. + - nand_scan_ident() - Scans for additional chips. + * NAND_CMD_RESET + - nand_do_write_oob() - Clears a bug observed on the + Toshiba TC5832DC and DiskOnChip 2000. + * NAND_CMD_READ0 + - nand_do_read_ops() - Used to begin a full page read (both with + and without ECC). + * NAND_CMD_ERASE1 + - single_erase_cmd() - Starts a block erase operation. + - multi_erase_cmd() - Starts a block erase operation. + * NAND_CMD_ERASE2 + - single_erase_cmd() - Finishes a block erase operation. + - multi_erase_cmd() - Finishes a block erase operation. + + +Since this is all the HIL uses, this is all a driver needs to implement. + + + +The Structure of the imx_nfc Driver +=================================== + +This driver supports many different versions of underlying controller, and +also supports higher-level abstractions like interleaving. To facilitate this +versatility, the code is layered as shown in the following diagram: + + + +--------------------------------------+ + | MTD | + +--------------------------------------+ + | NAND Flash MTD | + ======================================== <-- struct nand_chip + / | MTD Interface Layer (mil_*) | + | | +----------------------------------+ + | | | Medium Abstraction Layer (mal_*) | + imx_nfc | | | | + driver | | | +------------------------+ + | | | | NFC Utils (nfc_util_*) | + | ======================================== <-- struct nfc_hal + \ | NFC HAL (nfc_x_y_*) | + ======================================== <-- Hardware Interface + | NFC Hardware | + +--------------------------------------+ + + +MTD Interface Layer +------------------- +This layer includes functions that the NAND Flash MTD system calls directly. +In a manner of speaking, this layer "parses" the function calls made by MTD +and translates them into fundamental operations understood by the Medium +Abstraction Layer. Some simple operations don't need any abstraction, so code +in this layer can sometimes use the NFC HAL directly. + + +Medium Abstraction Layer +------------------------ +This layer implements the abstract model of the NAND Flash medium and hides +details that shouldn't concern higher layers (e.g., interleaving). + + +NFC Utilities +------------- +These functions make it easier to use the NFC HAL. Even though this layer +is shown above the NFC HAL in the diagram, it's actually possible for the +NFC HAL to call some of these functions. + + +NFC HAL +------- +This layer implements the abstract model of an i.MX NAND Flash controller. + + +Other Collections of Functions +------------------------------ + +- System Interface + - imx_nfc_* + +- sysfs Interface + - get_module_* + - set_module_* + - show_device_* + - store_device_* + + + + +i.MX NAND Flash Controller Versions +=================================== + +The i.MX NAND Flash controller (NFC) has evolved over time. Both its memory +layout and behaviors have changed. In this driver, we use major and minor +version numbers to label these stages in the NFC's evolution. These version +numbers are very useful, but they are entirely a figment of this driver's +imagination -- you will never find them in Freescale hardware reference +manuals. + +When the platform code instantiates an i.MX NFC device, it provides a struct +imx_nfc_platform_data that contains platform-specific information. This +includes the major and minor version numbers for the NFC. This driver uses +the version numbers to select an appopriate NFC HAL structure. + + + +i.MX NFC Memory Map +=================== + +While many things have changed during the evolution of the NFC, much has +remained the same. All i.MX NFCs have two or three essential memory-mapped +regions: a set of buffers, and one or two sets of registers (one on the AXI +bus and perhaps a second on the IP bus). + +The buffer area contains the captive memory to which the NFC writes data +received from the NAND Flash medium. This area is subdivided into several +contiguous "main" buffers that hold 512-byte chunks of data, and several +"spare" buffers that hold varying-size chunks of out-of-band bytes. The +number of main buffers is always the same as the number of spare buffers, but +the exact count and the size of the spare buffers varies across NFC versions. + +The register areas contain the NFC's control interface. Some versions have +only one set of registers, and some have two. + +The platform-specific resources passed to this driver include the starting +and ending physical addresses of the buffer and register areas. This driver +maps those physical addresses to virtual addresses, and then uses version- +specific offsets and bit masks to operate the NFC. + + + +Matching the NAND Flash MTD Page Model with the i.MX NFC +======================================================== + +The NAND Flash MTD HAL model views a page as containing two essentially +independent groups of bytes: "data" bytes and "out-of-band" bytes. If the +underlying physical format has data and out-of-band bytes distributed across +the page, they must be reassembled before being delivered to the caller +(e.g., see the function nand_read_page_syndrome(), which is part of the +reference implementation). + +The i.MX NFC hardware imposes both a physical page layout and a layout in its +memory buffer that differ from the HAL model. The following figure shows how +all these layouts relate to each other: + + + i.MX NFC i.MX NFC + Physical Memory NAND Flash + Page Buffers MTD Model + + +--------+ +--------+ +--------+ + |OOB[N-1]| |OOB[N-1]| |OOB[N-1]| + +--------+ +--------+ +--------+ + | | |OOB[ 1 ]| + | Data | +--------+ +--------+ + | [N-1] | |OOB[ 1 ]| |OOB[ 0 ]| + | | +--------+ +--------+ + +--------+ + ... +--------+ +--------+ + +--------+ |OOB[ 0 ]| | | + |OOB[ 1 ]| +--------+ | Data | + +--------+ | | | [N-1] | + | | | Data | | | + | Data | | [N-1] | +--------+ + | [ 1 ] | | | | | + | | +--------+ | Data | + +--------+ ... | [ 1 ] | + |OOB[ 0 ]| +--------+ | | + +--------+ | | +--------+ + | | | Data | | | + | Data | | [ 1 ] | | Data | + | [ 0 ] | | | | [ 0 ] | + | | +--------+ | | + +--------+ | | +--------+ + | Data | + | [ 0 ] | + | | + +--------+ + + +The NFC memory is *almost* what we want, but not quite. The problems are: + + 1) There are gaps between the out-of-band fragments. + + 2) The NFC memory responds only to 16-byte or 32-byte reads and writes. + +To resolve these problems, we've encapsulated the NFC memory behind these +functions: + + nfc_util_copy_from_the_nfc() - Copies data to main memory from the the NFC. + nfc_util_copy_to_the_nfc() - Copies data from main memory to the NFC. + +These functions don't take pointers to locations within the NFC memory - they +take a "column address." These functions know how to skip over the gaps and +handle the NFC memory such that it looks like all the data and out-of-band +bytes are completely contiguous. They also handle copying arbitrary bytes +from/to a memory that only responds to 16- or 32-byte reads/writes. If you're +accessing the NFC memory without these functions, you're *probably* doing +something wrong. + + diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4824fb4f4019..22febb022d24 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -350,6 +350,8 @@ config ARCH_MXC select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select COMMON_CLKDEV + select ZONE_DMA + select ARCH_HAS_CPUFREQ help Support for Freescale MXC/iMX-based family of processors @@ -363,6 +365,17 @@ config ARCH_STMP3XXX help Support for systems based on the Freescale 3xxx CPUs. +config ARCH_MXS + bool "Freescale i.MXS family soc" + select HAVE_CLK + select ARCH_REQUIRE_GPIOLIB + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select GENERIC_GPIO + select COMMON_CLKDEV + help + Support for Freescale i.MXS family of processors. + config ARCH_NETX bool "Hilscher NetX based" select CPU_ARM926T @@ -851,6 +864,8 @@ source "arch/arm/mach-mv78xx0/Kconfig" source "arch/arm/plat-mxc/Kconfig" +source "arch/arm/plat-mxs/Kconfig" + source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" @@ -973,6 +988,19 @@ config ARM_ERRATA_411920 It does not affect the MPCore. This option enables the ARM Ltd. recommended workaround. +config ARM_ERRATA_364296 + bool "Enable partial low interrupt latency mode for ARM1136" + depends on CPU_V6 && !SMP + default n + help + This options enables the workaround for the 364296 ARM1136 + r0pX errata (possible cache data corruption with + hit-under-miss enabled). It sets the undocumented bit 31 in + the auxiliary control register and the FI bit in the control + register, thus disabling hit-under-miss without putting the + processor into full low interrupt latency mode. ARM11MPCore + is not affected. + config ARM_ERRATA_430973 bool "ARM errata: Stale prediction on replaced interworking branch" depends on CPU_V7 @@ -1312,7 +1340,7 @@ config LEDS ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ ARCH_AT91 || ARCH_DAVINCI || \ - ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW + ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW || ARCH_MXC help If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. @@ -1387,6 +1415,9 @@ config UACCESS_WITH_MEMCPY However, if the CPU data cache is using a write-allocate mode, this option is unlikely to provide any performance gain. +config RUNTIME_PHYS_OFFSET + bool + endmenu menu "Boot options" @@ -1511,6 +1542,12 @@ config CPU_FREQ_SA1100 config CPU_FREQ_SA1110 bool +config CPU_FREQ_IMX + tristate "CPUfreq driver for i.MX CPUs" + depends on ARCH_MXC && CPU_FREQ && REGULATOR + help + This enables the CPUfreq driver for i.MX CPUs. + config CPU_FREQ_INTEGRATOR tristate "CPUfreq driver for ARM Integrator CPUs" depends on ARCH_INTEGRATOR && CPU_FREQ diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 64ba313724d2..767874de1063 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -150,6 +150,8 @@ machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX5) := mx5 +machine-$(CONFIG_ARCH_MX28) := mx28 +machine-$(CONFIG_ARCH_MX23) := mx23 machine-$(CONFIG_ARCH_MXC91231) := mxc91231 machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik @@ -190,6 +192,7 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. plat-$(CONFIG_ARCH_MXC) := mxc +plat-$(CONFIG_ARCH_MXS) := mxs plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_S3C64XX) := samsung plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 864a002137fe..5393d04bfc36 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -4,6 +4,7 @@ # create a compressed vmlinuz image from the original vmlinux # +AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) HEAD = head.o OBJS = misc.o decompress.o FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index c5191b1532e8..437943d6b55e 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -120,6 +120,16 @@ wait: mrc p14, 0, pc, c0, c1, 0 #endif .endm + .macro debug_passed_physoffset +#ifdef DEBUG + bleq 1f + kputc #'!' + kphex r9, 8 + kputc #'\n' +1: +#endif + .endm + .section ".start", #alloc, #execinstr /* * sort out different calling conventions @@ -137,6 +147,7 @@ start: .word _edata @ zImage end address 1: mov r7, r1 @ save architecture ID mov r8, r2 @ save atags pointer + mov r9, r3 @ save phys_offset #ifndef __ARM_ARCH_2__ /* @@ -234,6 +245,47 @@ not_relocated: mov r0, #0 cmp r2, r3 blo 1b +#ifdef CONFIG_RUNTIME_PHYS_OFFSET + /* + * assert physoffset passed by bootloader is properly + * 2MiB-aligned, ... + */ + ldr r10, =0x001fffff + + tst r9, r10 + debug_passed_physoffset + tst r9, r10 + + /* + * ... if not guess it based on sp. + * sp & 0xf8000000 should work for most machines. The needed + * preconditions are: + * - physoffset is aligned to a 128MiB boundary + * (As of Jan 2010 all but s3c2400, u300 and at91 have it. + * For the latter it depends on configuration.) + * - sp < physoffset + 128MiB (which is definitely true if you + * only have 128MiB of RAM or less) + */ +#ifdef CONFIG_ARCH_MX5 + and r9, sp, #0xf8000000 +#else + andne r9, sp, #0xf8000000 +#endif +#ifdef DEBUG + kputc #'P' + kphex r9, 8 + kputc #'\n' +#endif + + add r4, r9, #TEXT_OFFSET +#else /* ifdef CONFIG_RUNTIME_PHYS_OFFSET */ + /* warn on r4(ZRELADDR) != r9 + TEXT_OFFSET */ + add r10, r9, #TEXT_OFFSET + cmp r10, r4 + debug_passed_physoffset + +#endif /* ifdef CONFIG_RUNTIME_PHYS_OFFSET / else */ + /* * The C runtime environment should now be setup * sufficiently. Turn the cache on, set up some @@ -568,6 +620,7 @@ call_kernel: bl cache_clean_flush mov r0, #0 @ must be zero mov r1, r7 @ restore architecture number mov r2, r8 @ restore atags pointer + sub r3, r4, #TEXT_OFFSET @ physoffset mov pc, r4 @ call kernel /* diff --git a/arch/arm/configs/imx23evk_defconfig b/arch/arm/configs/imx23evk_defconfig new file mode 100644 index 000000000000..054cfb342fed --- /dev/null +++ b/arch/arm/configs/imx23evk_defconfig @@ -0,0 +1,2053 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Fri Nov 5 09:51:09 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_FIQ=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +CONFIG_ARCH_MXS=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=12 + +# +# Freescale i.MXS implementations +# +# CONFIG_ARCH_MX28 is not set +CONFIG_ARCH_MX23=y +CONFIG_VECTORS_PHY_ADDR=0 +CONFIG_MACH_MX23EVK=y +CONFIG_MXS_UNIQUE_ID=y +CONFIG_MXS_UNIQUE_ID_OTP=y +CONFIG_MXS_ICOLL=y +CONFIG_MXS_EARLY_CONSOLE=y +CONFIG_MXS_DMA_ENGINE=y +CONFIG_MXS_LRADC=y +CONFIG_MXS_PWM_CHANNELS=8 + +# +# Freescale Application UART: +# +CONFIG_MXS_AUART_DMA_SUPPORT=y +CONFIG_MXS_AUART_PORTS=5 +# CONFIG_MXS_AUART0_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART0_DMA_ENABLE is not set +CONFIG_MXS_AUART1_DEVICE_ENABLE=y +# CONFIG_MXS_AUART1_DMA_ENABLE is not set +# CONFIG_MXS_AUART2_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART2_DMA_ENABLE is not set +# CONFIG_MXS_AUART3_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART3_DMA_ENABLE is not set +# CONFIG_MXS_AUART4_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART4_DMA_ENABLE is not set +CONFIG_MXS_RAM_FREQ_SCALING=y +# CONFIG_MXS_RAM_MDDR is not set +CONFIG_MXS_RAM_DDR=y + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/mmcblk0p2 rootwait lcd_panel=lms350" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +CONFIG_ARPD=y +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +CONFIG_MXS_PERSISTENT=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +CONFIG_ENC28J60=y +# CONFIG_ENC28J60_WRITEVERIFY is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set +# CONFIG_ATH6K_LEGACY is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXS=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXS=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +CONFIG_MXS_VIIM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXS_DUART=y +CONFIG_SERIAL_MXS_AUART=y +# CONFIG_SERIAL_MXS_AUART_CONSOLE is not set +CONFIG_SERIAL_MXS_DUART_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_FSL_OTP is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MXS=y +CONFIG_I2C_MXS_SELECT0=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXS=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_BATTERY_MXS=y +# CONFIG_MXS_VBUS_CURRENT_DRAW is not set +# CONFIG_BATTERY_DS2438 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX17135 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +CONFIG_MXC_MMA7450=m +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_MXS_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_LTC3589_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB8500_CORE is not set +# CONFIG_MFD_MAX17135 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MXS=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_IR_CORE=y +CONFIG_VIDEO_IR=y +CONFIG_RC_MAP=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +# CONFIG_IR_IMON is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_CONTIG=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_IR_I2C=y +CONFIG_VIDEO_MXS_PXP=y +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_USB_DRIVERS=y +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXS=y +# CONFIG_FB_MXS_LCD_43WVF1G is not set +CONFIG_FB_MXS_LCD_LMS430=y +# CONFIG_FB_MXS_TVENC is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +CONFIG_BACKLIGHT_MXS=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_SPI=y +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_MXS_SOC=y +CONFIG_SND_MXS_SOC_EVK_ADC=y +CONFIG_SND_MXS_SOC_ADC=y +# CONFIG_SND_MXS_SOC_EVK_DEVB_SPDIF is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_MXS_ADC_CODEC=y +# CONFIG_SOUND_PRIME is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_STATIC_IRAM is not set +# CONFIG_USB_EHCI_FSL_MC13783 is not set +# CONFIG_USB_EHCI_FSL_1301 is not set +# CONFIG_USB_EHCI_FSL_1504 is not set +CONFIG_USB_EHCI_FSL_UTMI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_FSL_UTP is not set +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_CDC_COMPOSITE=m +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_MXC_OTG is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +CONFIG_MMC_MXS=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_MXS=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set +# CONFIG_SECURITY_PATH is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_IMA is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CRYPTODEV=y + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_DCP=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/imx23evk_updater_defconfig b/arch/arm/configs/imx23evk_updater_defconfig new file mode 100644 index 000000000000..0c591ac5b8e8 --- /dev/null +++ b/arch/arm/configs/imx23evk_updater_defconfig @@ -0,0 +1,1474 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Sun Sep 26 11:18:10 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_FIQ=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +CONFIG_ARCH_MXS=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=12 + +# +# Freescale i.MXS implementations +# +# CONFIG_ARCH_MX28 is not set +CONFIG_ARCH_MX23=y +CONFIG_VECTORS_PHY_ADDR=0 +CONFIG_MACH_MX23EVK=y +CONFIG_MXS_UNIQUE_ID=y +CONFIG_MXS_UNIQUE_ID_OTP=y +CONFIG_MXS_ICOLL=y +CONFIG_MXS_EARLY_CONSOLE=y +CONFIG_MXS_DMA_ENGINE=y +CONFIG_MXS_LRADC=y +CONFIG_MXS_PWM_CHANNELS=8 + +# +# Freescale Application UART: +# +CONFIG_MXS_AUART_DMA_SUPPORT=y +CONFIG_MXS_AUART_PORTS=5 +# CONFIG_MXS_AUART0_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART0_DMA_ENABLE is not set +CONFIG_MXS_AUART1_DEVICE_ENABLE=y +# CONFIG_MXS_AUART1_DMA_ENABLE is not set +# CONFIG_MXS_AUART2_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART2_DMA_ENABLE is not set +# CONFIG_MXS_AUART3_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART3_DMA_ENABLE is not set +# CONFIG_MXS_AUART4_DEVICE_ENABLE is not set +# CONFIG_MXS_AUART4_DMA_ENABLE is not set +CONFIG_MXS_RAM_FREQ_SCALING=y +# CONFIG_MXS_RAM_MDDR is not set +CONFIG_MXS_RAM_DDR=y + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/mmcblk0p2 rootwait lcd_panel=lms350" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +CONFIG_MTD_UBI_GLUEBI=y + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +CONFIG_MXS_PERSISTENT=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXS=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXS=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_MXS_VIIM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXS_DUART=y +CONFIG_SERIAL_MXS_AUART=y +# CONFIG_SERIAL_MXS_AUART_CONSOLE is not set +CONFIG_SERIAL_MXS_DUART_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_FSL_OTP=y +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MXS=y +CONFIG_I2C_MXS_SELECT0=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXS=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_BATTERY_MXS=y +# CONFIG_MXS_VBUS_CURRENT_DRAW is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +CONFIG_MXC_MMA7450=y +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MXS=y +# CONFIG_REGULATOR_MAX17135 is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXS=y +# CONFIG_FB_MXS_LCD_43WVF1G is not set +CONFIG_FB_MXS_LCD_LMS430=y +# CONFIG_FB_MXS_TVENC is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +CONFIG_BACKLIGHT_MXS=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +CONFIG_MMC_MXS=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_MXS=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_CRYPTODEV=y + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_DCP=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/imx25_3stack_defconfig b/arch/arm/configs/imx25_3stack_defconfig new file mode 100644 index 000000000000..3b24316735e6 --- /dev/null +++ b/arch/arm/configs/imx25_3stack_defconfig @@ -0,0 +1,2109 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Thu Sep 30 10:01:12 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +CONFIG_ARCH_MX25=y +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX37 is not set +# CONFIG_ARCH_MXC91231 is not set +# CONFIG_ARCH_MX5 is not set +CONFIG_MXC_SDMA_API=y +CONFIG_SDMA_IRAM=y +CONFIG_ARCH_MXC_HAS_NFC_V2=y +CONFIG_ARCH_MXC_HAS_NFC_V2_1=y + +# +# MX25 platforms: +# +CONFIG_MACH_MX25_3DS=y + +# +# MX25 Options +# +CONFIG_MX25_OPTIONS=y +# CONFIG_MX25_DOZE_DURING_IDLE is not set + +# +# Device options +# +CONFIG_I2C_MXC_SELECT1=y +# CONFIG_I2C_MXC_SELECT2 is not set +# CONFIG_I2C_MXC_SELECT3 is not set +# CONFIG_FLEXCAN_MXC_SELECT1 is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=24 +CONFIG_ISP1504_MXC=y +CONFIG_UTMI_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +# CONFIG_MXC_PWM is not set +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_ARCH_MXC_IOMUX_V3=y + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +# CONFIG_CAN_BCM is not set + +# +# CAN Device Drivers +# +# CONFIG_CAN_VCAN is not set +# CONFIG_CAN_DEV is not set +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_FLEXCAN=y +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m + +# +# Dongle support +# +# CONFIG_DONGLE is not set +# CONFIG_KINGSUN_DONGLE is not set +# CONFIG_KSDAZZLE_DONGLE is not set +# CONFIG_KS959_DONGLE is not set + +# +# FIR device drivers +# +# CONFIG_USB_IRDA is not set +# CONFIG_SIGMATEL_FIR is not set +# CONFIG_MCS_FIR is not set +# CONFIG_MXC_FIR is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +# CONFIG_MTD_CFI_I2 is not set +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_MXC is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_MXC is not set +CONFIG_MTD_NAND_MXC_V2=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_FEC is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXC=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_IMX_ADC=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +CONFIG_MXC_IIM=y +CONFIG_IMX_SIM=m + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXC=y +CONFIG_SERIAL_MXC_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_IMX is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IMX is not set +CONFIG_I2C_MXC=y +# CONFIG_I2C_MXC_HS is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_IMX is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_MXC_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_IMX2_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB8500_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MC34704=y +# CONFIG_REGULATOR_MAX17135 is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_IR_CORE=y +CONFIG_VIDEO_IR=y +CONFIG_RC_MAP=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +# CONFIG_IR_IMON is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +CONFIG_VIDEO_IR_I2C=y + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +CONFIG_VIDEO_MXC_CAMERA=m + +# +# MXC Camera/V4L2 PRP Features support +# +CONFIG_VIDEO_MXC_CSI_CAMERA=m +# CONFIG_MXC_CAMERA_MC521DA is not set +# CONFIG_MXC_EMMA_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640_EMMA is not set +# CONFIG_MXC_CAMERA_MICRON111 is not set +CONFIG_MXC_CAMERA_OV2640=m +# CONFIG_MXC_CAMERA_OV3640 is not set +# CONFIG_MXC_TVIN_ADV7180 is not set +# CONFIG_VIDEO_MXC_OUTPUT is not set +# CONFIG_VIDEO_MXC_OPL is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_V4L_USB_DRIVERS is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +CONFIG_HAVE_FB_IMX=y +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SII9022 is not set +# CONFIG_FB_MXC_CH7026 is not set +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +# CONFIG_FB_MXC_ASYNC_PANEL is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_ADP8860 is not set +CONFIG_BACKLIGHT_MXC_LCDC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +# CONFIG_SND_MXC_SPDIF is not set +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_MXC_SOC=y +CONFIG_SND_MXC_SOC_SSI=y +CONFIG_SND_MXC_SOC_ESAI=m +CONFIG_SND_MXC_SOC_IRAM=y +CONFIG_SND_SOC_IMX_3STACK_SGTL5000=y +# CONFIG_SND_SOC_IMX_3STACK_AK4647 is not set +CONFIG_SND_SOC_IMX_3STACK_WM8580=m +CONFIG_SND_SOC_IMX_3STACK_AK5702=m +# CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH is not set +# CONFIG_SND_SOC_IMX_3STACK_CS42888 is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AK5702=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_SGTL5000=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +# CONFIG_HID_CANDO is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_PRODIKEYS is not set +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_KYE is not set +CONFIG_HID_GYRATION=y +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MOSART is not set +CONFIG_HID_MONTEREY=y +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +# CONFIG_HID_STANTUM is not set +CONFIG_HID_SUNPLUS=y +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_H2=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_STATIC_IRAM is not set +# CONFIG_USB_EHCI_FSL_MC13783 is not set +# CONFIG_USB_EHCI_FSL_1301 is not set +# CONFIG_USB_EHCI_FSL_1504 is not set +CONFIG_USB_EHCI_FSL_UTMI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_MXC is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_STATIC_IRAM_PPH=y +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_FSL_UTP is not set +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_MXC_OTG is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_SELECT2 is not set +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_MXC_V2 is not set +CONFIG_RTC_DRV_IMXDI=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# MXC support drivers +# + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +# CONFIG_MXC_PMIC_MC13892 is not set +CONFIG_MXC_PMIC_MC34704=y +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +CONFIG_MXC_PMIC_CHARDEV=y + +# +# MXC PMIC Client Drivers +# +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_RNG is not set +# CONFIG_MXC_DRYICE is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# + +# +# MXC Asynchronous Sample Rate Converter support +# + +# +# MXC Bluetooth support +# + +# +# Broadcom GPS ioctrl support +# + +# +# MXC Media Local Bus Driver +# + +# +# i.MX ADC support +# +CONFIG_IMX_ADC=y + +# +# MXC GPU support +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LKDTM is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/imx25_updater_defconfig b/arch/arm/configs/imx25_updater_defconfig new file mode 100644 index 000000000000..32110031bad3 --- /dev/null +++ b/arch/arm/configs/imx25_updater_defconfig @@ -0,0 +1,1337 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Sun Sep 26 11:36:51 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +CONFIG_ARCH_MX25=y +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX37 is not set +# CONFIG_ARCH_MXC91231 is not set +# CONFIG_ARCH_MX5 is not set +CONFIG_MXC_SDMA_API=y +CONFIG_SDMA_IRAM=y +CONFIG_ARCH_MXC_HAS_NFC_V2=y +CONFIG_ARCH_MXC_HAS_NFC_V2_1=y + +# +# MX25 platforms: +# +CONFIG_MACH_MX25_3DS=y + +# +# MX25 Options +# +CONFIG_MX25_OPTIONS=y +# CONFIG_MX25_DOZE_DURING_IDLE is not set + +# +# Device options +# +CONFIG_I2C_MXC_SELECT1=y +# CONFIG_I2C_MXC_SELECT2 is not set +# CONFIG_I2C_MXC_SELECT3 is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=24 +CONFIG_ISP1504_MXC=y +CONFIG_UTMI_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +# CONFIG_MXC_PWM is not set +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_ARCH_MXC_IOMUX_V3=y + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +# CONFIG_MTD_CFI_I2 is not set +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_RAM=y +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_MXC is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_MXC is not set +CONFIG_MTD_NAND_MXC_V2=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXC=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_IMX_ADC=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_MXC_IIM=y +CONFIG_IMX_SIM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXC=y +CONFIG_SERIAL_MXC_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_IMX is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IMX is not set +CONFIG_I2C_MXC=y +# CONFIG_I2C_MXC_HS is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_IMX is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MC34704=y +# CONFIG_REGULATOR_MAX17135 is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_HAVE_FB_IMX=y +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SII9022 is not set +# CONFIG_FB_MXC_CH7026 is not set +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +# CONFIG_FB_MXC_ASYNC_PANEL is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_ADP8860 is not set +CONFIG_BACKLIGHT_MXC_LCDC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_STATIC_IRAM_PPH=y +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_SELECT2 is not set +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_MXC_V2 is not set +CONFIG_RTC_DRV_IMXDI=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# MXC support drivers +# + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +# CONFIG_MXC_PMIC_MC13892 is not set +CONFIG_MXC_PMIC_MC34704=y +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +CONFIG_MXC_PMIC_CHARDEV=y + +# +# MXC PMIC Client Drivers +# +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_RNG is not set +# CONFIG_MXC_DRYICE is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# + +# +# MXC Asynchronous Sample Rate Converter support +# + +# +# MXC Bluetooth support +# + +# +# Broadcom GPS ioctrl support +# + +# +# MXC Media Local Bus Driver +# + +# +# i.MX ADC support +# +CONFIG_IMX_ADC=y + +# +# MXC GPU support +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/imx28evk_defconfig b/arch/arm/configs/imx28evk_defconfig new file mode 100644 index 000000000000..8454a851caea --- /dev/null +++ b/arch/arm/configs/imx28evk_defconfig @@ -0,0 +1,2133 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Mon Dec 6 17:17:47 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_FIQ=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +# CONFIG_ASHMEM is not set +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +CONFIG_ARCH_MXS=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=16 + +# +# Freescale i.MXS implementations +# +CONFIG_ARCH_MX28=y +# CONFIG_ARCH_MX23 is not set +CONFIG_MACH_MX28EVK=y +CONFIG_VECTORS_PHY_ADDR=0 +CONFIG_MXS_TIMER_WITH_MACH=y +# CONFIG_MEM_mDDR is not set +CONFIG_MXS_ICOLL=y +CONFIG_MXS_EARLY_CONSOLE=y +CONFIG_MXS_DMA_ENGINE=y +CONFIG_MXS_LRADC=y +CONFIG_MXS_PWM_CHANNELS=8 + +# +# Freescale Application UART: +# +CONFIG_MXS_AUART_DMA_SUPPORT=y +CONFIG_MXS_AUART_PORTS=5 +CONFIG_MXS_AUART0_DEVICE_ENABLE=y +# CONFIG_MXS_AUART0_DMA_ENABLE is not set +CONFIG_MXS_AUART1_DEVICE_ENABLE=y +# CONFIG_MXS_AUART1_DMA_ENABLE is not set +CONFIG_MXS_AUART2_DEVICE_ENABLE=y +# CONFIG_MXS_AUART2_DMA_ENABLE is not set +CONFIG_MXS_AUART3_DEVICE_ENABLE=y +# CONFIG_MXS_AUART3_DMA_ENABLE is not set +CONFIG_MXS_AUART4_DEVICE_ENABLE=y +# CONFIG_MXS_AUART4_DMA_ENABLE is not set +CONFIG_MXS_RAM_FREQ_SCALING=y +# CONFIG_MXS_RAM_MDDR is not set +# CONFIG_MXS_RAM_DDR is not set + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +# CONFIG_CAN_BCM is not set + +# +# CAN Device Drivers +# +# CONFIG_CAN_VCAN is not set +# CONFIG_CAN_DEV is not set +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_FLEXCAN=m +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +CONFIG_MTD_M25P80=m +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +CONFIG_MXS_PERSISTENT=y +# CONFIG_ANDROID_PMEM is not set +# CONFIG_UID_STAT is not set +# CONFIG_C2PORT is not set +CONFIG_MXS_PERFMON=y + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_FEC=y +# CONFIG_FEC_1588 is not set +# CONFIG_FEC2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set +CONFIG_ATH6K_LEGACY=m +CONFIG_AR600x_SD31_XXX=y +# CONFIG_AR600x_WB31_XXX is not set +# CONFIG_AR600x_SD32_XXX is not set +# CONFIG_AR600x_CUSTOM_XXX is not set +# CONFIG_ATH6KL_ENABLE_COEXISTENCE is not set +# CONFIG_ATH6KL_HCI_BRIDGE is not set +# CONFIG_ATH6KL_CFG80211 is not set +# CONFIG_ATH6KL_HTC_RAW_INTERFACE is not set +# CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER is not set +# CONFIG_ATH6KL_DEBUG is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXS=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_JOYSTICK_XPAD is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GUNZE=m +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXS=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=m +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +CONFIG_STALDRV=y +CONFIG_MXS_VIIM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXS_DUART=y +CONFIG_SERIAL_MXS_AUART=y +# CONFIG_SERIAL_MXS_AUART_CONSOLE is not set +CONFIG_SERIAL_MXS_DUART_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_FSL_OTP is not set +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MXS=y +CONFIG_I2C_MXS_SELECT0=y +# CONFIG_I2C_MXS_SELECT0_PIOQUEUE_MODE is not set +# CONFIG_I2C_MXS_SELECT1 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXS=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_BATTERY_MXS=y +# CONFIG_MXS_VBUS_CURRENT_DRAW is not set +# CONFIG_BATTERY_DS2438 is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_MXS_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_SDIOHOST_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_LTC3589_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB8500_CORE is not set +# CONFIG_MFD_MAX17135 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MXS=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_VIDEO_ALLOW_V4L1 is not set +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_IR_CORE=y +CONFIG_VIDEO_IR=y +CONFIG_RC_MAP=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +# CONFIG_IR_IMON is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_CONTIG=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +CONFIG_VIDEO_IR_I2C=y + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +CONFIG_VIDEO_MXS_PXP=y +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_V4L_USB_DRIVERS is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXS=y +CONFIG_FB_MXS_LCD_43WVF1G=y +# CONFIG_FB_MXS_LCD_LMS430 is not set +# CONFIG_FB_MXS_TVENC is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +CONFIG_BACKLIGHT_MXS=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_SPI=y +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_MXS_SOC=y +CONFIG_SND_MXS_SOC_SPDIF_DAI=y +CONFIG_SND_MXS_SOC_EVK_DEVB=y +CONFIG_SND_MXS_SOC_DAI=y +CONFIG_SND_MXS_SOC_EVK_DEVB_SPDIF=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_SGTL5000=y +CONFIG_SND_SOC_MXS_SPDIF=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +# CONFIG_HID_CANDO is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_PRODIKEYS is not set +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_HID_EGALAX is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +CONFIG_HID_GYRATION=y +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +CONFIG_HID_MICROSOFT=y +# CONFIG_HID_MOSART is not set +CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y +# CONFIG_HID_ORTEK is not set +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +# CONFIG_HID_STANTUM is not set +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_SMARTJOYPLUS=y +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_HID_ZEROPLUS=y +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_H1=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_STATIC_IRAM is not set +# CONFIG_USB_EHCI_FSL_MC13783 is not set +# CONFIG_USB_EHCI_FSL_1301 is not set +# CONFIG_USB_EHCI_FSL_1504 is not set +CONFIG_USB_EHCI_FSL_UTMI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_ARC=y +CONFIG_WORKAROUND_ARCUSB_REG_RW=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_FSL_UTP is not set +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MXC_OTG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +CONFIG_MMC_MXS=y +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_MXS=y +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TRIGGERS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_MXS=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +# CONFIG_MXC_PXP is not set +# CONFIG_TIMB_DMA is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +CONFIG_VXFS_FS=m +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LKDTM is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_IMA is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CRYPTODEV=y + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_DCP=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/imx28evk_updater_defconfig b/arch/arm/configs/imx28evk_updater_defconfig new file mode 100644 index 000000000000..8a1cd362d7c5 --- /dev/null +++ b/arch/arm/configs/imx28evk_updater_defconfig @@ -0,0 +1,1473 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Sun Sep 26 10:08:14 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_FIQ=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +CONFIG_ARCH_MXS=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=16 + +# +# Freescale i.MXS implementations +# +CONFIG_ARCH_MX28=y +# CONFIG_ARCH_MX23 is not set +CONFIG_MACH_MX28EVK=y +CONFIG_VECTORS_PHY_ADDR=0 +CONFIG_MXS_TIMER_WITH_MACH=y +CONFIG_MXS_ICOLL=y +CONFIG_MXS_EARLY_CONSOLE=y +CONFIG_MXS_DMA_ENGINE=y +CONFIG_MXS_LRADC=y +CONFIG_MXS_PWM_CHANNELS=8 + +# +# Freescale Application UART: +# +CONFIG_MXS_AUART_DMA_SUPPORT=y +CONFIG_MXS_AUART_PORTS=5 +CONFIG_MXS_AUART0_DEVICE_ENABLE=y +# CONFIG_MXS_AUART0_DMA_ENABLE is not set +CONFIG_MXS_AUART1_DEVICE_ENABLE=y +# CONFIG_MXS_AUART1_DMA_ENABLE is not set +CONFIG_MXS_AUART2_DEVICE_ENABLE=y +# CONFIG_MXS_AUART2_DMA_ENABLE is not set +CONFIG_MXS_AUART3_DEVICE_ENABLE=y +# CONFIG_MXS_AUART3_DMA_ENABLE is not set +CONFIG_MXS_AUART4_DEVICE_ENABLE=y +# CONFIG_MXS_AUART4_DMA_ENABLE is not set +CONFIG_MXS_RAM_FREQ_SCALING=y +# CONFIG_MXS_RAM_MDDR is not set +# CONFIG_MXS_RAM_DDR is not set + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_UNIX is not set +# CONFIG_NET_KEY is not set +# CONFIG_INET is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +CONFIG_MXS_PERSISTENT=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_SCSI_FC_ATTRS=y +CONFIG_SCSI_ISCSI_ATTRS=y +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXS=y +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +CONFIG_MOUSE_VSXXXAA=y +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_JOYSTICK_XPAD is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GUNZE=y +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXS=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +CONFIG_STALDRV=y +CONFIG_MXS_VIIM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXS_DUART=y +CONFIG_SERIAL_MXS_AUART=y +# CONFIG_SERIAL_MXS_AUART_CONSOLE is not set +CONFIG_SERIAL_MXS_DUART_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_FSL_OTP=y +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MXS=y +CONFIG_I2C_MXS_SELECT0=y +# CONFIG_I2C_MXS_SELECT0_PIOQUEUE_MODE is not set +# CONFIG_I2C_MXS_SELECT1 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_BATTERY_MXS=y +# CONFIG_MXS_VBUS_CURRENT_DRAW is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +# CONFIG_SSB_DEBUG is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MXS=y +# CONFIG_REGULATOR_MAX17135 is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXS=y +CONFIG_FB_MXS_LCD_43WVF1G=y +# CONFIG_FB_MXS_LCD_LMS430 is not set +# CONFIG_FB_MXS_TVENC is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +CONFIG_BACKLIGHT_MXS=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_ARC=y +CONFIG_WORKAROUND_ARCUSB_REG_RW=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +CONFIG_MMC_MXS=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_MXS=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +# CONFIG_MXC_PXP is not set +# CONFIG_TIMB_DMA is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +CONFIG_VXFS_FS=y +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/imx5_defconfig b/arch/arm/configs/imx5_defconfig new file mode 100644 index 000000000000..49079688432a --- /dev/null +++ b/arch/arm/configs/imx5_defconfig @@ -0,0 +1,2486 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Wed Jan 19 20:30:04 2011 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +# CONFIG_ASHMEM is not set +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX37 is not set +# CONFIG_ARCH_MXC91231 is not set +CONFIG_ARCH_MX5=y +CONFIG_MXC_SDMA_API=y +CONFIG_SDMA_IRAM=y +CONFIG_ARCH_MX51=y +CONFIG_ARCH_MX53=y +CONFIG_ARCH_MX50=y +CONFIG_FORCE_MAX_ZONEORDER=13 +CONFIG_MX5_MULTI_ARCH=y +CONFIG_MACH_MX51_3DS=y +CONFIG_MACH_MX51_BABBAGE=y +CONFIG_MACH_MX53_EVK=y +CONFIG_MACH_MX53_ARD=y +CONFIG_MACH_MX53_SMD=y +CONFIG_MACH_MX53_LOCO=y +CONFIG_MACH_MX50_ARM2=y +CONFIG_MACH_MX50_RDP=y + +# +# MX5x Options: +# +CONFIG_ARCH_MXC_HAS_NFC_V3=y +CONFIG_ARCH_MXC_HAS_NFC_V3_2=y +CONFIG_MXC_BLUETOOTH_RFKILL=y +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=96 +CONFIG_ISP1504_MXC=y +CONFIG_UTMI_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_TZIC=y +CONFIG_MXC_PWM=y +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_ARCH_HAS_RNGC=y +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_MXC_DVFS_PER=y +CONFIG_MXC_ZQ_CALIBRATION=y + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_RUNTIME_PHYS_OFFSET=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_VERBOSE is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_PM_RUNTIME=y +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=y +# CONFIG_CAN_DEV is not set +CONFIG_CAN_DEBUG_DEVICES=y +CONFIG_CAN_FLEXCAN=y +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +# CONFIG_BT_L2CAP_EXT_FEATURES is not set +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=y +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +# CONFIG_BT_HCIUART_H4 is not set +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +CONFIG_BT_HCIVHCI=y +# CONFIG_BT_MRVL is not set +# CONFIG_BT_ATH3K is not set +CONFIG_BT_HCIUART_ATH=y +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_MXC is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MXC_DATAFLASH=y +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_IMX_NFC is not set +CONFIG_MTD_NAND_MXC_V3=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +CONFIG_MXS_PERFMON=y +# CONFIG_ANDROID_PMEM is not set +# CONFIG_UID_STAT is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +# CONFIG_SATA_PMP is not set + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_SATA_MV is not set + +# +# PATA SFF controllers with BMDMA +# +CONFIG_PATA_FSL=m + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_PLATFORM is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_FEC=y +# CONFIG_FEC_1588 is not set +# CONFIG_FEC2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set +CONFIG_ATH6K_LEGACY=m +CONFIG_AR600x_SD31_XXX=y +# CONFIG_AR600x_WB31_XXX is not set +# CONFIG_AR600x_SD32_XXX is not set +# CONFIG_AR600x_CUSTOM_XXX is not set +# CONFIG_ATH6KL_ENABLE_COEXISTENCE is not set +# CONFIG_ATH6KL_HCI_BRIDGE is not set +# CONFIG_ATH6KL_CFG80211 is not set +# CONFIG_ATH6KL_HTC_RAW_INTERFACE is not set +# CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER is not set +# CONFIG_ATH6KL_DEBUG is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXC=y +CONFIG_KEYBOARD_MPR121=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXC=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_TOUCHSCREEN_DA9052=y +CONFIG_TOUCHSCREEN_MAX11801=y +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +CONFIG_INPUT_DA9052_ONKEY=y + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +CONFIG_FM_SI4702=m +CONFIG_MXC_IIM=y +CONFIG_MXS_VIIM=y +CONFIG_IMX_SIM=m + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXC=y +CONFIG_SERIAL_MXC_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_IMX is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_FSL_OTP is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_FSL_RNGC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IMX=y +# CONFIG_I2C_MXC is not set +CONFIG_I2C_MXC_HS=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_IMX is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_DA9052_GPIO_ENABLE is not set +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +CONFIG_W1_MASTER_MXC=m +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_GPIO is not set + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2751 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +CONFIG_W1_SLAVE_DS2438=m +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +CONFIG_APM_POWER=y +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_DA9052 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_BATTERY_DS2438=m +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +CONFIG_SENSORS_DA9052=y +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +CONFIG_SENSORS_MAX17135=y +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +CONFIG_SENSORS_ISL29003=y +CONFIG_MXC_MMA8450=y +CONFIG_MXC_MMA8451=y +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_DA9052_WATCHDOG is not set +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_MXC_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_IMX2_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_MFD_LTC3589=y +CONFIG_MFD_LTC3589_I2C=y +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +CONFIG_PMIC_DA9052=y +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB8500_CORE is not set +CONFIG_MFD_MAX17135=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_LTC3589=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_REGULATOR_DA9052=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_IR_CORE=y +CONFIG_VIDEO_IR=y +CONFIG_RC_MAP=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +# CONFIG_IR_IMON is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_CUSTOMISE=y +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +CONFIG_VIDEO_IR_I2C=y + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_VIVI is not set +CONFIG_VIDEO_MXC_CAMERA=m + +# +# MXC Camera/V4L2 PRP Features support +# +CONFIG_VIDEO_MXC_IPU_CAMERA=y +# CONFIG_VIDEO_MXC_CSI_CAMERA is not set +# CONFIG_MXC_CAMERA_MC521DA is not set +# CONFIG_MXC_EMMA_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640_EMMA is not set +# CONFIG_MXC_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640 is not set +CONFIG_MXC_CAMERA_OV3640=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_PRP_VF_SDC=m +CONFIG_MXC_IPU_PRP_ENC=m +CONFIG_MXC_IPU_CSI_ENC=m +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +# CONFIG_VIDEO_MXC_OPL is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL=y +CONFIG_FB_MXC_TVOUT_TVE=y +CONFIG_FB_MXC_LDB=y +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set +CONFIG_FB_MXC_SII902X=y +CONFIG_FB_MXC_CH7026=y +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +# CONFIG_FB_MXC_ASYNC_PANEL is not set +CONFIG_FB_MXC_EINK_PANEL=y +# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_DA9052 is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set +CONFIG_BACKLIGHT_MXC_MC13892=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_MXC_SPDIF=m +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_MXC_SOC=y +CONFIG_SND_MXC_SOC_SSI=y +CONFIG_SND_MXC_SOC_ESAI=y +CONFIG_SND_MXC_SOC_IRAM=y +CONFIG_SND_SOC_IMX_3STACK_SGTL5000=y +# CONFIG_SND_SOC_IMX_3STACK_AK4647 is not set +# CONFIG_SND_SOC_IMX_3STACK_WM8580 is not set +# CONFIG_SND_SOC_IMX_3STACK_AK5702 is not set +# CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH is not set +CONFIG_SND_SOC_IMX_3STACK_CS42888=y +# CONFIG_MXC_SSI_DUAL_FIFO is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_CS42888=y +CONFIG_SND_SOC_SGTL5000=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +CONFIG_HID_A4TECH=m +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +# CONFIG_HID_CANDO is not set +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +# CONFIG_HID_PRODIKEYS is not set +CONFIG_HID_CYPRESS=m +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EGALAX is not set +CONFIG_HID_EZKEY=m +# CONFIG_HID_KYE is not set +CONFIG_HID_GYRATION=m +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +CONFIG_HID_LOGITECH=m +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=m +# CONFIG_HID_MOSART is not set +CONFIG_HID_MONTEREY=m +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +CONFIG_HID_PANTHERLORD=m +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=m +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_KONE is not set +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +# CONFIG_HID_STANTUM is not set +CONFIG_HID_SUNPLUS=m +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_STATIC_IRAM is not set +# CONFIG_USB_EHCI_FSL_MC13783 is not set +# CONFIG_USB_EHCI_FSL_1301 is not set +# CONFIG_USB_EHCI_FSL_1504 is not set +CONFIG_USB_EHCI_FSL_UTMI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_MXC is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +# CONFIG_USB_STATIC_IRAM_PPH is not set +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_FSL_UTP is not set +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MXC_OTG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set +CONFIG_SDIO_UNIFI_FS=m + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_MC13892=y +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DA9052 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TRIGGERS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DA9052 is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_MXC_V2=y +# CONFIG_RTC_DRV_IMXDI is not set +CONFIG_RTC_MC13892=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_MXC_PXP=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +# CONFIG_TIMB_DMA is not set +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3=y + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +CONFIG_MXC_PMIC_I2C=y +CONFIG_MXC_PMIC_SPI=y +# CONFIG_MXC_PMIC_MC34704 is not set +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +CONFIG_MXC_MC13892_ADC=y +CONFIG_MXC_MC13892_RTC=y +CONFIG_MXC_MC13892_LIGHT=y +CONFIG_MXC_MC13892_BATTERY=m +CONFIG_MXC_MC13892_CONNECTIVITY=y +CONFIG_MXC_MC13892_POWER=y +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_SCC2 is not set +# CONFIG_MXC_SECURITY_RNG is not set + +# +# SAHARA2 Security Hardware Support +# +# CONFIG_MXC_SAHARA is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +# CONFIG_MXC_VPU_IRAM is not set +# CONFIG_MXC_VPU_DEBUG is not set + +# +# MXC Asynchronous Sample Rate Converter support +# +CONFIG_MXC_ASRC=y + +# +# MXC Bluetooth support +# +CONFIG_MXC_BLUETOOTH=m + +# +# Broadcom GPS ioctrl support +# +CONFIG_GPS_IOCTRL=m + +# +# MXC Media Local Bus Driver +# +CONFIG_MXC_MLB=m + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC GPU support +# +CONFIG_MXC_AMD_GPU=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CRYPTODEV=y + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_DCP is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/imx5_updater_defconfig b/arch/arm/configs/imx5_updater_defconfig new file mode 100644 index 000000000000..58d48889def8 --- /dev/null +++ b/arch/arm/configs/imx5_updater_defconfig @@ -0,0 +1,1871 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Tue Jan 11 21:48:16 2011 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +# CONFIG_ASHMEM is not set +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX37 is not set +# CONFIG_ARCH_MXC91231 is not set +CONFIG_ARCH_MX5=y +CONFIG_MXC_SDMA_API=y +CONFIG_SDMA_IRAM=y +CONFIG_ARCH_MX51=y +CONFIG_ARCH_MX53=y +CONFIG_ARCH_MX50=y +CONFIG_FORCE_MAX_ZONEORDER=13 +CONFIG_MX5_MULTI_ARCH=y +CONFIG_MACH_MX51_3DS=y +CONFIG_MACH_MX51_BABBAGE=y +CONFIG_MACH_MX53_EVK=y +CONFIG_MACH_MX53_ARD=y +CONFIG_MACH_MX53_SMD=y +CONFIG_MACH_MX53_LOCO=y +CONFIG_MACH_MX50_ARM2=y +CONFIG_MACH_MX50_RDP=y + +# +# MX5x Options: +# +CONFIG_ARCH_MXC_HAS_NFC_V3=y +CONFIG_ARCH_MXC_HAS_NFC_V3_2=y +CONFIG_IRAM_ALLOC=y +CONFIG_DMA_ZONE_SIZE=96 +CONFIG_ISP1504_MXC=y +CONFIG_UTMI_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_TZIC=y +CONFIG_MXC_PWM=y +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_ARCH_HAS_RNGC=y +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_MXC_DVFS_PER=y +# CONFIG_MXC_ZQ_CALIBRATION is not set + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_RUNTIME_PHYS_OFFSET=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_MXC is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MXC_DATAFLASH=y +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_IMX_NFC is not set +CONFIG_MTD_NAND_MXC_V3=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +# CONFIG_SATA_PMP is not set + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_SATA_MV is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_FSL is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_PLATFORM is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_MXC=y +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_MXC=y +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_DA9052 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_FM_SI4702 is not set +CONFIG_MXC_IIM=y +CONFIG_MXS_VIIM=y +# CONFIG_IMX_SIM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_MXC=y +CONFIG_SERIAL_MXC_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_IMX is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_FSL_OTP=y +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_FSL_RNGC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IMX=y +# CONFIG_I2C_MXC is not set +CONFIG_I2C_MXC_HS=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_IMX is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_DA9052_GPIO_ENABLE is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +CONFIG_APM_POWER=y +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_DA9052 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_DS2438 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DA9052 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX17135 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_SENSORS_ISL29003 is not set +# CONFIG_MXC_MMA8450 is not set +# CONFIG_MXC_MMA8451 is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_DA9052_WATCHDOG is not set +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_MXC_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_IMX2_WDT is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_MFD_LTC3589=y +CONFIG_MFD_LTC3589_I2C=y +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +CONFIG_PMIC_DA9052=y +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB8500_CORE is not set +CONFIG_MFD_MAX17135=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_LTC3589=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_REGULATOR_DA9052=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_IR_CORE=y +CONFIG_VIDEO_IR=y +CONFIG_RC_MAP=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +# CONFIG_IR_IMON is not set +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_CUSTOMISE=y +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +CONFIG_MEDIA_TUNER_MAX2165=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +CONFIG_VIDEO_IR_I2C=y + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_VIVI is not set +CONFIG_VIDEO_MXC_CAMERA=y + +# +# MXC Camera/V4L2 PRP Features support +# +CONFIG_VIDEO_MXC_IPU_CAMERA=y +# CONFIG_VIDEO_MXC_CSI_CAMERA is not set +# CONFIG_MXC_CAMERA_MC521DA is not set +# CONFIG_MXC_EMMA_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640_EMMA is not set +# CONFIG_MXC_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640 is not set +CONFIG_MXC_CAMERA_OV3640=y +# CONFIG_MXC_CAMERA_OV5640 is not set +# CONFIG_MXC_CAMERA_OV5642 is not set +# CONFIG_MXC_TVIN_ADV7180 is not set +CONFIG_MXC_IPU_PRP_VF_SDC=y +CONFIG_MXC_IPU_PRP_ENC=y +CONFIG_MXC_IPU_CSI_ENC=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +# CONFIG_VIDEO_MXC_OPL is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_TVOUT_TVE is not set +# CONFIG_FB_MXC_LDB is not set +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SII9022 is not set +# CONFIG_FB_MXC_CH7026 is not set +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +# CONFIG_FB_MXC_ASYNC_PANEL is not set +# CONFIG_FB_MXC_EINK_PANEL is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_DA9052 is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set +CONFIG_BACKLIGHT_MXC_MC13892=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +# CONFIG_USB_STATIC_IRAM_PPH is not set +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set +CONFIG_SDIO_UNIFI_FS=y + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DA9052 is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_MXC_V2 is not set +# CONFIG_RTC_DRV_IMXDI is not set +CONFIG_RTC_MC13892=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_MXC_PXP=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +# CONFIG_TIMB_DMA is not set +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3=y + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +CONFIG_MXC_PMIC_I2C=y +CONFIG_MXC_PMIC_SPI=y +# CONFIG_MXC_PMIC_MC34704 is not set +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +CONFIG_MXC_MC13892_ADC=y +CONFIG_MXC_MC13892_RTC=y +CONFIG_MXC_MC13892_LIGHT=y +# CONFIG_MXC_MC13892_BATTERY is not set +CONFIG_MXC_MC13892_CONNECTIVITY=y +CONFIG_MXC_MC13892_POWER=y +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_SCC2 is not set +# CONFIG_MXC_SECURITY_RNG is not set + +# +# SAHARA2 Security Hardware Support +# +# CONFIG_MXC_SAHARA is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +# CONFIG_MXC_VPU is not set +# CONFIG_MXC_VPU_IRAM is not set + +# +# MXC Asynchronous Sample Rate Converter support +# +# CONFIG_MXC_ASRC is not set + +# +# MXC Bluetooth support +# +CONFIG_MXC_BLUETOOTH=y + +# +# Broadcom GPS ioctrl support +# +CONFIG_GPS_IOCTRL=y + +# +# MXC Media Local Bus Driver +# +# CONFIG_MXC_MLB is not set + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC GPU support +# +# CONFIG_MXC_AMD_GPU is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_MANAGER_TESTS is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index 161f907b611f..ca26bc46080e 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig @@ -1,22 +1,264 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Tue Sep 7 14:59:08 2010 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y +CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y +CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y +CONFIG_IMX_HAVE_PLATFORM_IMX_MMC=y + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +CONFIG_ARCH_MX3=y +# CONFIG_ARCH_MX37 is not set +# CONFIG_ARCH_MXC91231 is not set +# CONFIG_ARCH_MX5 is not set +CONFIG_ARCH_MX31=y +CONFIG_ARCH_MX35=y + +# +# MX3 platforms: +# +CONFIG_MACH_MX31ADS=y CONFIG_MACH_MX31ADS_WM1133_EV1=y CONFIG_MACH_PCM037=y CONFIG_MACH_PCM037_EET=y CONFIG_MACH_MX31LITE=y CONFIG_MACH_MX31_3DS=y +# CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT is not set CONFIG_MACH_MX31MOBOARD=y CONFIG_MACH_MX31LILLY=y CONFIG_MACH_QONG=y @@ -24,100 +266,1282 @@ CONFIG_MACH_PCM043=y CONFIG_MACH_ARMADILLO5X0=y CONFIG_MACH_MX35_3DS=y CONFIG_MACH_KZM_ARM11_01=y +CONFIG_MXC_SDMA_API=y +# CONFIG_SDMA_IRAM is not set +CONFIG_ARCH_MXC_HAS_NFC_V1=y +CONFIG_ARCH_MXC_HAS_NFC_V2=y +CONFIG_ARCH_MXC_HAS_NFC_V2_1=y +CONFIG_IRAM_ALLOC=y +CONFIG_ARCH_HAS_EVTMON=y +CONFIG_DMA_ZONE_SIZE=24 +CONFIG_ISP1504_MXC=y +CONFIG_UTMI_MXC=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y +CONFIG_MXC_DEBUG_BOARD=y +CONFIG_ARCH_HAS_RNGA=y +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_ARCH_MXC_AUDMUX_V2=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_CACHE_L2X0=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +CONFIG_ARM_ERRATA_411920=y +CONFIG_ARM_ERRATA_364296=y +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y +CONFIG_HZ=100 CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# CONFIG_PM=y CONFIG_PM_DEBUG=y +CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_VERBOSE is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y + +# +# Networking options +# CONFIG_PACKET=y CONFIG_UNIX=y +# CONFIG_NET_KEY is not set CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set +CONFIG_MTD_MXC=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_IMX_NFC is not set CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_NAND_MXC_V2=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_PARPORT is not set # CONFIG_BLK_DEV is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set CONFIG_SMSC_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set CONFIG_SMSC911X=y CONFIG_DNET=y +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_CS89x0 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set CONFIG_FEC=y +# CONFIG_FEC2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# # CONFIG_INPUT is not set + +# +# Hardware I/O ports +# # CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# # CONFIG_VT is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_FM_SI4702 is not set +# CONFIG_MXC_IIM is not set + +# +# Serial drivers +# CONFIG_SERIAL_8250=m +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MXC is not set +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set CONFIG_I2C_IMX=y +# CONFIG_I2C_MXC is not set +# CONFIG_I2C_MXC_HS is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_IMX is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_WM8350 is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# CONFIG_W1=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2482 is not set CONFIG_W1_MASTER_MXC=y +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_GPIO is not set + +# +# 1-wire Slaves +# CONFIG_W1_SLAVE_THERM=y +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2751 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2438 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TC35892 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +CONFIG_MFD_WM8350=y +CONFIG_MFD_WM8350_CONFIG_MODE_0=y +CONFIG_MFD_WM8352_CONFIG_MODE_0=y CONFIG_MFD_WM8350_I2C=y +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_AB8500_CORE is not set CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set CONFIG_REGULATOR_WM8350=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_MC9S08DZ60=y +# CONFIG_REGULATOR_MAX17135 is not set CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y # CONFIG_VIDEO_ALLOW_V4L1 is not set +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_CONTIG=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_MXC_CAMERA=y + +# +# MXC Camera/V4L2 PRP Features support +# +# CONFIG_VIDEO_MXC_CSI_CAMERA is not set +# CONFIG_MXC_CAMERA_MC521DA is not set +# CONFIG_MXC_EMMA_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640_EMMA is not set +# CONFIG_MXC_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640 is not set +# CONFIG_MXC_CAMERA_OV3640 is not set +# CONFIG_MXC_TVIN_ADV7180 is not set +CONFIG_VIDEO_MXC_OUTPUT=y +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set CONFIG_SOC_CAMERA=y CONFIG_SOC_CAMERA_MT9M001=y CONFIG_SOC_CAMERA_MT9M111=y CONFIG_SOC_CAMERA_MT9T031=y +# CONFIG_SOC_CAMERA_MT9T112 is not set CONFIG_SOC_CAMERA_MT9V022=y +# CONFIG_SOC_CAMERA_RJ54N1 is not set CONFIG_SOC_CAMERA_TW9910=y +# CONFIG_SOC_CAMERA_PLATFORM is not set CONFIG_SOC_CAMERA_OV772X=y +# CONFIG_SOC_CAMERA_OV9640 is not set +CONFIG_MX3_VIDEO=y CONFIG_VIDEO_MX3=y +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +CONFIG_FB_MX3=y +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set +CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_MMC=y -CONFIG_MMC_MXC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set +# CONFIG_SDIO_UNIFI_FS is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_MX3_IPU=y +CONFIG_MX3_IPU_IRQS=4 +# CONFIG_MXC_PXP is not set +# CONFIG_TIMB_DMA is not set +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# MXC support drivers +# +# CONFIG_MXC_IPU is not set + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +CONFIG_MXC_PMIC_I2C=y +# CONFIG_MXC_PMIC_SPI is not set +# CONFIG_MXC_PMIC_MC34704 is not set +CONFIG_MXC_PMIC_MC9SDZ60=y +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +CONFIG_MXC_MC13892_ADC=y +CONFIG_MXC_MC13892_RTC=y +CONFIG_MXC_MC13892_LIGHT=y +# CONFIG_MXC_MC13892_BATTERY is not set +# CONFIG_MXC_MC13892_CONNECTIVITY is not set +CONFIG_MXC_MC13892_POWER=y +CONFIG_MXC_PMIC_MC9S08DZ60=y +# CONFIG_MXC_MC9SDZ60_RTC is not set + +# +# MXC Security Drivers +# + +# +# MXC MPEG4 Encoder Kernel module support +# +CONFIG_MXC_HMP4E=y +# CONFIG_MXC_HMP4E_DEBUG is not set + +# +# MXC HARDWARE EVENT +# +CONFIG_MXC_HWEVENT=y + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +# CONFIG_MXC_VPU_DEBUG is not set + +# +# MXC Asynchronous Sample Rate Converter support +# +# CONFIG_MXC_ASRC is not set + +# +# MXC Bluetooth support +# +# CONFIG_MXC_BLUETOOTH is not set + +# +# Broadcom GPS ioctrl support +# +# CONFIG_GPS_IOCTRL is not set + +# +# MXC Media Local Bus Driver +# +# CONFIG_MXC_MLB is not set + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/configs/mx3_updater_defconfig b/arch/arm/configs/mx3_updater_defconfig new file mode 100644 index 000000000000..f589634532d7 --- /dev/null +++ b/arch/arm/configs/mx3_updater_defconfig @@ -0,0 +1,1321 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35.3 +# Sun Sep 26 12:30:14 2010 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y +CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y +CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y +CONFIG_IMX_HAVE_PLATFORM_IMX_MMC=y + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +CONFIG_ARCH_MX3=y +# CONFIG_ARCH_MX37 is not set +# CONFIG_ARCH_MXC91231 is not set +# CONFIG_ARCH_MX5 is not set +CONFIG_ARCH_MX31=y +CONFIG_ARCH_MX35=y + +# +# MX3 platforms: +# +CONFIG_MACH_MX31ADS=y +CONFIG_MACH_PCM037=y +CONFIG_MACH_PCM037_EET=y +CONFIG_MACH_MX31LITE=y +CONFIG_MACH_MX31_3DS=y +# CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT is not set +CONFIG_MACH_MX31MOBOARD=y +CONFIG_MACH_MX31LILLY=y +CONFIG_MACH_QONG=y +CONFIG_MACH_PCM043=y +CONFIG_MACH_ARMADILLO5X0=y +CONFIG_MACH_MX35_3DS=y +CONFIG_MACH_KZM_ARM11_01=y +CONFIG_MXC_SDMA_API=y +# CONFIG_SDMA_IRAM is not set +CONFIG_ARCH_MXC_HAS_NFC_V1=y +CONFIG_ARCH_MXC_HAS_NFC_V2=y +CONFIG_ARCH_MXC_HAS_NFC_V2_1=y +CONFIG_IRAM_ALLOC=y +CONFIG_ARCH_HAS_EVTMON=y +CONFIG_DMA_ZONE_SIZE=24 +CONFIG_ISP1504_MXC=y +CONFIG_UTMI_MXC=y +CONFIG_MXC_IRQ_PRIOR=y +CONFIG_MXC_PWM=y +CONFIG_MXC_DEBUG_BOARD=y +CONFIG_ARCH_HAS_RNGA=y +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_ARCH_MXC_AUDMUX_V2=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_CACHE_L2X0=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +CONFIG_ARM_ERRATA_411920=y +CONFIG_ARM_ERRATA_364296=y +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off" +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_VERBOSE is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_NVS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_PM_OPS=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set +CONFIG_MTD_MXC=y + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_IMX_NFC is not set +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_NAND_MXC_V2=y +# CONFIG_MTD_NAND_MXC_SWECC is not set +# CONFIG_MTD_NAND_MXC_FORCE_CE is not set +# CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 is not set +# CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_FM_SI4702 is not set +# CONFIG_MXC_IIM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MXC is not set +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IMX=y +# CONFIG_I2C_MXC is not set +# CONFIG_I2C_MXC_HS is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_IMX is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI_MXC=y +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +CONFIG_W1=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2482 is not set +CONFIG_W1_MASTER_MXC=y +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_GPIO is not set + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=y +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2751 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2438 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_MC9S08DZ60=y +# CONFIG_REGULATOR_MAX17135 is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +CONFIG_USB_GADGET_ARC=y +# CONFIG_USB_STATIC_IRAM_PPH is not set +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=y +CONFIG_FSL_UTP=y +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set +# CONFIG_SDIO_UNIFI_FS is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_IMX_ESDHCI=y +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +# CONFIG_MX3_IPU is not set +# CONFIG_MXC_PXP is not set +# CONFIG_TIMB_DMA is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# MXC support drivers +# +# CONFIG_MXC_IPU is not set + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +CONFIG_MXC_PMIC=y +# CONFIG_MXC_PMIC_MC13783 is not set +CONFIG_MXC_PMIC_MC13892=y +CONFIG_MXC_PMIC_I2C=y +# CONFIG_MXC_PMIC_SPI is not set +# CONFIG_MXC_PMIC_MC34704 is not set +CONFIG_MXC_PMIC_MC9SDZ60=y +# CONFIG_MXC_PMIC_CHARDEV is not set + +# +# MXC PMIC Client Drivers +# +CONFIG_MXC_MC13892_ADC=y +CONFIG_MXC_MC13892_RTC=y +CONFIG_MXC_MC13892_LIGHT=y +# CONFIG_MXC_MC13892_BATTERY is not set +# CONFIG_MXC_MC13892_CONNECTIVITY is not set +CONFIG_MXC_MC13892_POWER=y +CONFIG_MXC_PMIC_MC9S08DZ60=y +# CONFIG_MXC_MC9SDZ60_RTC is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_RNG is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +CONFIG_MXC_HMP4E=y +# CONFIG_MXC_HMP4E_DEBUG is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +# CONFIG_MXC_VPU_DEBUG is not set + +# +# MXC Asynchronous Sample Rate Converter support +# +# CONFIG_MXC_ASRC is not set + +# +# MXC Bluetooth support +# +# CONFIG_MXC_BLUETOOTH is not set + +# +# Broadcom GPS ioctrl support +# +# CONFIG_GPS_IOCTRL is not set + +# +# MXC Media Local Bus Driver +# +# CONFIG_MXC_MLB is not set + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC GPU support +# +CONFIG_MXC_AMD_GPU=y + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_MANAGER_TESTS is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 6bcba48800fe..11ed7d901654 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -56,6 +56,8 @@ #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); +extern void l2x0_enable(void); +extern void l2x0_disable(void); #endif #endif diff --git a/arch/arm/include/asm/mach/flash.h b/arch/arm/include/asm/mach/flash.h index 4ca69fe2c850..8b57c2ed6d7e 100644 --- a/arch/arm/include/asm/mach/flash.h +++ b/arch/arm/include/asm/mach/flash.h @@ -34,6 +34,7 @@ struct flash_platform_data { void (*mmcontrol)(struct mtd_info *mtd, int sync_read); struct mtd_partition *parts; unsigned int nr_parts; + char *type; }; #endif diff --git a/arch/arm/include/asm/mach/keypad.h b/arch/arm/include/asm/mach/keypad.h new file mode 100644 index 000000000000..6f950d29b4a6 --- /dev/null +++ b/arch/arm/include/asm/mach/keypad.h @@ -0,0 +1,29 @@ +/* + * include/asm-arm/mach/keypad.h + * + * Generic Keypad struct + * + * Author: Armin Kuster + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * Copyright (C) 2010 Freescale Semiconductor, + */ + +#ifndef __ASM_MACH_KEYPAD_H_ +#define __ASM_MACH_KEYPAD_H_ + +#include + +struct keypad_data { + u16 rowmax; + u16 colmax; + u32 irq; + u16 delay; + u16 learning; + u16 *matrix; +}; + +#endif /* __ARM_MACH_KEYPAD_H_ */ diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 4312ee5e3d0b..05a7a3f22f26 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -24,6 +24,11 @@ */ #define UL(x) _AC(x, UL) +#if defined(CONFIG_RUNTIME_PHYS_OFFSET) && !defined(__ASSEMBLY__) +extern unsigned long phys_offset; +#define PHYS_OFFSET phys_offset +#endif + #ifdef CONFIG_MMU /* diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index ab68cf1ef80f..7c4b3e714a9b 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -314,6 +314,8 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; } __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) #define pgprot_writecombine(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) +#define pgprot_writethru(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_WRITETHROUGH) #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE #define pgprot_dmacoherent(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index eb62bf947212..b173bb645222 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -22,12 +22,14 @@ #include #include +#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) #if (PHYS_OFFSET & 0x001fffff) #error "PHYS_OFFSET must be at an even 2MiB boundary!" #endif +#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) +#endif #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) -#define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) /* @@ -44,8 +46,8 @@ .globl swapper_pg_dir .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 - .macro pgtbl, rd - ldr \rd, =(KERNEL_RAM_PADDR - 0x4000) + .macro pgtbl, rd, phys_offset + add \rd, \phys_offset, #(TEXT_OFFSET - 0x4000) .endm #ifdef CONFIG_XIP_KERNEL @@ -215,9 +217,25 @@ ENDPROC(__turn_mmu_on) * Returns: * r0, r3, r6, r7 corrupted * r4 = physical page table address + * r5 = physical start address of (the first bank of) RAM (PHYS_OFFSET) */ __create_page_tables: - pgtbl r4 @ page table address +#if defined(CONFIG_RUNTIME_PHYS_OFFSET) + @ stext is at PHYS_OFFSET + TEXT_OFFSET. As PHYS_OFFSET has to be + @ 2MiB-aligned and assuming that TEXT_OFFSET < 2MiB + @ stext & 0xffe00000 yields PHYS_OFFSET + adr r5, stext + ldr r4, =0xffe00000 + and r5, r5, r4 + + @ save phys_offset + ldr r4, =(phys_offset - PAGE_OFFSET) + str r5, [r4, r5] +#else + ldr r5, =PHYS_OFFSET +#endif + + pgtbl r4, r5 @ r4 = page table address /* * Clear the 16K level 1 swapper page table @@ -282,10 +300,7 @@ __create_page_tables: * Then map first 1MB of ram in case it contains our boot params. */ add r0, r4, #PAGE_OFFSET >> 18 - orr r6, r7, #(PHYS_OFFSET & 0xff000000) - .if (PHYS_OFFSET & 0x00f00000) - orr r6, r6, #(PHYS_OFFSET & 0x00f00000) - .endif + orr r6, r7, r5 str r6, [r0] #ifdef CONFIG_DEBUG_LL diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 122d999bdc7c..8833d95c7009 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -67,6 +67,12 @@ __setup("fpe=", fpe_setup); extern void paging_init(struct machine_desc *desc); extern void reboot_setup(char *str); +#if defined(CONFIG_RUNTIME_PHYS_OFFSET) +/* assign a value to prevent phys_offset from ending in up bss */ +unsigned long phys_offset = 0xdeadbeef; +EXPORT_SYMBOL(phys_offset); +#endif + unsigned int processor_id; EXPORT_SYMBOL(processor_id); unsigned int __machine_arch_type; @@ -648,7 +654,7 @@ static struct init_tags { { tag_size(tag_core), ATAG_CORE }, { 1, PAGE_SIZE, 0xff }, { tag_size(tag_mem32), ATAG_MEM }, - { MEM_SIZE, PHYS_OFFSET }, + { MEM_SIZE, }, { 0, ATAG_NONE } }; @@ -682,6 +688,8 @@ void __init setup_arch(char **cmdline_p) tags = phys_to_virt(__atags_pointer); else if (mdesc->boot_params) tags = phys_to_virt(mdesc->boot_params); + else + init_tags.mem.start = PHYS_OFFSET; /* * If we have the old style parameters, convert them to diff --git a/arch/arm/mach-mx23/Kconfig b/arch/arm/mach-mx23/Kconfig new file mode 100644 index 000000000000..28009b0d62cb --- /dev/null +++ b/arch/arm/mach-mx23/Kconfig @@ -0,0 +1,25 @@ +choice + prompt "Select i.MXS board type" + +config MACH_MX23EVK + bool "Freescale MX23 EVK board" + depends on ARCH_MX23 + select USB_ARCH_HAS_EHCI + +endchoice + + +config MXS_UNIQUE_ID + bool "Support for UniqueID on boot media" + default y + +config MXS_UNIQUE_ID_OTP + bool "UniqueID on OTP" + depends on MXS_UNIQUE_ID + default y + +config VECTORS_PHY_ADDR + int "vectors address" + default 0 + help + This config set vectors table is located which physical address diff --git a/arch/arm/mach-mx23/Makefile b/arch/arm/mach-mx23/Makefile new file mode 100644 index 000000000000..a5e278190326 --- /dev/null +++ b/arch/arm/mach-mx23/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the linux kernel. +# +obj-y += pinctrl.o clock.o device.o serial.o power.o pm.o sleep.o bus_freq.o + +# Board select +obj-$(CONFIG_MACH_MX23EVK) += mx23evk.o mx23evk_pins.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_MXS_RAM_FREQ_SCALING) +=emi.o +obj-$(CONFIG_MXS_UNIQUE_ID_OTP) += otp.o + +# USB support +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif diff --git a/arch/arm/mach-mx23/Makefile.boot b/arch/arm/mach-mx23/Makefile.boot new file mode 100644 index 000000000000..1568ad404d59 --- /dev/null +++ b/arch/arm/mach-mx23/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-mx23/bus_freq.c b/arch/arm/mach-mx23/bus_freq.c new file mode 100644 index 000000000000..9133e6b1080a --- /dev/null +++ b/arch/arm/mach-mx23/bus_freq.c @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file bus_freq.c + * + * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "regs-clkctrl.h" +#include "regs-digctl.h" + +#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +struct profile profiles[] = { + { 454736, 151580, 130910, 0, 1550000, + 1450000, 355000, 3300000, 1750000, 24000, 0 }, + { 392727, 130910, 130910, 0, 1450000, + 1375000, 225000, 3300000, 1750000, 24000, 0x1CF3 }, + { 360000, 120000, 130910, 0, 1375000, + 1275000, 200000, 3300000, 1750000, 24000, 0x1CF3 }, + { 261818, 130910, 130910, 0, 1275000, + 1175000, 173000, 3300000, 1750000, 24000, 0x1CF3 }, +#ifdef CONFIG_MXS_RAM_MDDR + { 64000, 64000, 48000, 3, 1050000, + 975000, 150000, 3300000, 1750000, 24000, 0x1CF3 }, + { 24000, 24000, 24000, 3, 1050000, + 975000, 150000, 3075000, 1725000, 6000, 0x1C93 }, +#else + { 64000, 64000, 96000, 3, 1050000, + 975000, 150000, 3300000, 1750000, 24000, 0x1CF3 }, + { 24000, 24000, 96000, 3, 1050000, + 975000, 150000, 3300000, 1725000, 6000, 0x1C93 }, +#endif +}; + +static struct clk *usb_clk; +static struct clk *lcdif_clk; + +int low_freq_used(void) +{ + if ((clk_get_usecount(usb_clk) == 0) + && (clk_get_usecount(lcdif_clk) == 0)) + return 1; + else + return 0; +} + +int is_hclk_autoslow_ok(void) +{ + if (clk_get_usecount(usb_clk) == 0) + return 1; + else + return 0; +} + +int timing_ctrl_rams(int ss) +{ + __raw_writel(BF(ss, DIGCTL_ARMCACHE_VALID_SS) | + BF(ss, DIGCTL_ARMCACHE_DRTY_SS) | + BF(ss, DIGCTL_ARMCACHE_CACHE_SS) | + BF(ss, DIGCTL_ARMCACHE_DTAG_SS) | + BF(ss, DIGCTL_ARMCACHE_ITAG_SS), + DIGCTRL_BASE_ADDR + HW_DIGCTL_ARMCACHE); + return 0; +} + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit busfreq_probe(struct platform_device *pdev) +{ + int ret = 0; + + usb_clk = clk_get(NULL, "usb_clk0"); + if (IS_ERR(usb_clk)) { + ret = PTR_ERR(usb_clk); + goto out_usb; + } + + lcdif_clk = clk_get(NULL, "lcdif"); + if (IS_ERR(lcdif_clk)) { + ret = PTR_ERR(lcdif_clk); + goto out_lcd; + } + return 0; + +out_lcd: + clk_put(usb_clk); +out_usb: + return ret; +} + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "busfreq", + }, + .probe = busfreq_probe, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ + if (platform_driver_register(&busfreq_driver) != 0) { + printk(KERN_ERR "busfreq_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "Bus freq driver module loaded\n"); + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx23/clock.c b/arch/arm/mach-mx23/clock.c new file mode 100644 index 000000000000..9e18dbc74337 --- /dev/null +++ b/arch/arm/mach-mx23/clock.c @@ -0,0 +1,1596 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "regs-clkctrl.h" +#include "regs-digctl.h" + +#include +#include + +#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) +#define RTC_BASE_ADDR IO_ADDRESS(RTC_PHYS_ADDR) + +/* these are the maximum clock speeds that have been + * validated to run at the minumum VddD target voltage level for cpu operation + * (presently 1.05V target, .975V Brownout). Higher clock speeds for GPMI and + * SSP have not been validated. + */ +#define PLL_ENABLED_MAX_CLK_SSP 96000000 +#define PLL_ENABLED_MAX_CLK_GPMI 96000000 + + +/* external clock input */ +static struct clk pll_clk; +static struct clk ref_xtal_clk; + +#ifdef DEBUG +static void print_ref_counts(void); +#endif + +static unsigned long enet_mii_phy_rate; + +static inline int clk_is_busy(struct clk *clk) +{ + if ((clk->parent == &ref_xtal_clk) && (clk->xtal_busy_bits)) + return __raw_readl(clk->busy_reg) & (1 << clk->xtal_busy_bits); + else if (clk->busy_bits && clk->busy_reg) + return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits); + else { + printk(KERN_ERR "WARNING: clock has no assigned busy \ + register or bits\n"); + udelay(10); + return 0; + } +} + +static inline int clk_busy_wait(struct clk *clk) +{ + int i; + + for (i = 10000000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) + return -ETIMEDOUT; + else + return 0; +} + +static bool mx23_enable_h_autoslow(bool enable) +{ + bool currently_enabled; + + if (__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS) & + BM_CLKCTRL_HBUS_AUTO_SLOW_MODE) + currently_enabled = true; + else + currently_enabled = false; + + if (enable) + __raw_writel(BM_CLKCTRL_HBUS_AUTO_SLOW_MODE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); + else + __raw_writel(BM_CLKCTRL_HBUS_AUTO_SLOW_MODE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); + return currently_enabled; +} + + +static void mx23_set_hbus_autoslow_flags(u16 mask) +{ + u32 reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= 0xFFFF; + reg |= mask << 16; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); +} + +static void local_clk_disable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk) || !clk->ref) + return; + + if ((--clk->ref) & CLK_EN_MASK) + return; + + if (clk->disable) + clk->disable(clk); + local_clk_disable(clk->secondary); + local_clk_disable(clk->parent); +} + +static int local_clk_enable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if ((clk->ref++) & CLK_EN_MASK) + return 0; + if (clk->parent) + local_clk_enable(clk->parent); + if (clk->secondary) + local_clk_enable(clk->secondary); + if (clk->enable) + clk->enable(clk); + return 0; +} + + +static bool mx23_is_clk_enabled(struct clk *clk) +{ + if (clk->enable_reg) + return (__raw_readl(clk->enable_reg) & + clk->enable_bits) ? 0 : 1; + else + return (clk->ref & CLK_EN_MASK) ? 1 : 0; +} + + +static int mx23_raw_enable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg &= ~clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } + if (clk->busy_reg) + clk_busy_wait(clk); + + return 0; +} + +static void mx23_raw_disable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg |= clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } +} + +static unsigned long ref_xtal_get_rate(struct clk *clk) +{ + return 24000000; +} + +static struct clk ref_xtal_clk = { + .flags = RATE_FIXED, + .get_rate = ref_xtal_get_rate, +}; + +static unsigned long pll_get_rate(struct clk *clk); +static int pll_enable(struct clk *clk); +static void pll_disable(struct clk *clk); + +static struct clk pll_clk = { + + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .enable = pll_enable, + .disable = pll_disable, + +}; + +static unsigned long pll_get_rate(struct clk *clk) +{ + return 480000000; +} + +static int pll_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0); + + if ((reg & BM_CLKCTRL_PLLCTRL0_POWER) && + (reg & BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS)) + return 0; + + __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | + BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET); + /* only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer + * and is incorrect (excessive). Per definition of the PLLCTRL0 + * POWER field, waiting at least 10us. + */ + udelay(10); + + return 0; +} + +static void pll_disable(struct clk *clk) +{ + __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | + BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR); + return; +} + +static inline unsigned long +ref_clk_get_rate(unsigned long base, unsigned int div) +{ + unsigned long rate = base / 1000; + return 1000 * ((rate * 18) / div); +} + +static unsigned long ref_clk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long base = clk->parent->get_rate(clk->parent); + unsigned long div = (base * 18) / rate; + return (base / div) * 18; +} + +static int ref_clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long base = clk->parent->get_rate(clk->parent); + unsigned long div = ((base/1000) * 18) / (rate/1000); + if (rate != ((base / div) * 18)) + return -EINVAL; + if (clk->scale_reg == 0) + return -EINVAL; + base = __raw_readl(clk->scale_reg); + base &= ~(0x3F << clk->scale_bits); + base |= (div << clk->scale_bits); + __raw_writel(base, clk->scale_reg); + return 0; +} + +static unsigned long ref_cpu_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_CPUFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_cpu_clk = { + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .get_rate = ref_cpu_get_rate, + .round_rate = ref_clk_round_rate, + .set_rate = ref_clk_set_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATECPU, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .scale_bits = BP_CLKCTRL_FRAC_CPUFRAC, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU, + .busy_bits = 28, +}; + +static unsigned long ref_emi_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_EMIFRAC; + reg >>= BP_CLKCTRL_FRAC_EMIFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_emi_clk = { + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .get_rate = ref_emi_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATEEMI, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .scale_bits = BP_CLKCTRL_FRAC_EMIFRAC, +}; + +static unsigned long ref_io_get_rate(struct clk *clk); +static struct clk ref_io_clk = { + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .get_rate = ref_io_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATEIO, +}; + +static unsigned long ref_io_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_IOFRAC; + reg >>= BP_CLKCTRL_FRAC_IOFRAC; + + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static unsigned long ref_pix_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_PIXFRAC; + reg >>= BP_CLKCTRL_FRAC_PIXFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_pix_clk = { + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .get_rate = ref_pix_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATEPIX, +}; + +static struct clk cpu_clk, h_clk; +static int clkseq_set_parent(struct clk *clk, struct clk *parent) +{ + int shift; + + if (clk->parent == parent) + return 0; /* clock parent already at target. nothing to do */ + /* bypass? */ + if (parent == &ref_xtal_clk) + shift = 4; + else + shift = 8; + + if (clk->bypass_reg) + __raw_writel(1 << clk->bypass_bits, clk->bypass_reg + shift); + + return 0; +} + +static unsigned long lcdif_get_rate(struct clk *clk) +{ + long rate = clk->parent->get_rate(clk->parent); + long div; + const int mask = 0xff; + + div = (__raw_readl(clk->scale_reg) >> clk->scale_bits) & mask; + if (div) { + rate /= div; + div = (__raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) & + BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC; + rate /= div; + } + + return rate; +} + +static int lcdif_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = 0; + /* + * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz, + * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns. + * + * ns_cycle >= 2*18e3/(18*480) = 25/6 + * ns_cycle <= 2*35e3/(18*480) = 875/108 + * + * Multiply the ns_cycle by 'div' to lengthen it until it fits the + * bounds. This is the divider we'll use after ref_pix. + * + * 6 * ns_cycle >= 25 * div + * 108 * ns_cycle <= 875 * div + */ + u32 ns_cycle = 1000000000 / rate; + u32 div, reg_val; + u32 lowest_result = (u32) -1; + u32 lowest_div = 0, lowest_fracdiv = 0; + + ns_cycle *= 2; /* Fix calculate double frequency */ + + + + for (div = 1; div < 256; ++div) { + u32 fracdiv; + u32 ps_result; + int lower_bound = 6 * ns_cycle >= 25 * div; + int upper_bound = 108 * ns_cycle <= 875 * div; + if (!lower_bound) + break; + if (!upper_bound) + continue; + /* + * Found a matching div. Calculate fractional divider needed, + * rounded up. + */ + fracdiv = ((clk->parent->get_rate(clk->parent) / 1000000 * 18 / 2) * + ns_cycle + 1000 * div - 1) / + (1000 * div); + if (fracdiv < 18 || fracdiv > 35) { + ret = -EINVAL; + goto out; + } + /* Calculate the actual cycle time this results in */ + ps_result = 6250 * div * fracdiv / 27; + + /* Use the fastest result that doesn't break ns_cycle */ + if (ps_result <= lowest_result) { + lowest_result = ps_result; + lowest_div = div; + lowest_fracdiv = fracdiv; + } + } + + if (div >= 256 || lowest_result == (u32) -1) { + ret = -EINVAL; + goto out; + } + pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz " + "PIXCLK=%uMHz cycle=%u.%03uns\n", + lowest_fracdiv, lowest_div, + 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div, + lowest_result / 1000, lowest_result % 1000); + + /* Program ref_pix phase fractional divider */ + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC; + reg_val |= BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv); + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + + /* Ungate PFD */ + __raw_writel(BM_CLKCTRL_FRAC_CLKGATEPIX, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC_CLR); + + /* Program pix divider */ + reg_val = __raw_readl(clk->scale_reg); + reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); + reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div); + __raw_writel(reg_val, clk->scale_reg); + + /* Wait for divider update */ + ret = clk_busy_wait(clk); + if (ret) + goto out; + + /* Switch to ref_pix source */ + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX; + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + +out: + return ret; +} + +/* + * We set lcdif_clk's parent as &pll_clk deliberately, although + * in IC spec lcdif_clk(CLK_PIX) is derived from ref_pix which in turn + * is derived from PLL. By doing so, users just need to set/get clock rate + * for lcdif_clk, without need to take care of ref_pix, because the clock + * driver will automatically calculate the fracdivider for HW_CLKCTRL_FRAC + * and the divider for HW_CLKCTRL_PIX conjointly. + */ +static struct clk lcdif_clk = { + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX, + .busy_bits = 29, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX, + .enable_bits = 31, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 1, + .get_rate = lcdif_get_rate, + .set_rate = lcdif_set_rate, + .set_parent = clkseq_set_parent, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long cpu_get_rate(struct clk *clk) +{ + unsigned long rate, div; + rate = (clk->parent->get_rate(clk->parent)); + div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU) & + BM_CLKCTRL_CPU_DIV_CPU; + rate = rate/div; + return rate; +} + +static unsigned long cpu_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long frac_rate, root_rate = clk->parent->get_rate(clk->parent); + unsigned int div = root_rate / rate; + if (div == 0) + return root_rate; + if (clk->parent == &ref_cpu_clk) { + if (div > 0x3F) + div = 0x3F; + return root_rate / div; + } + + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return root_rate; + if (frac_rate == 0) + return rate; + return rate; +} + +static int cpu_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate = pll_clk.get_rate(&pll_clk); + int ret = -EINVAL; + u32 clkctrl_cpu = 1; + u32 c = clkctrl_cpu; + u32 clkctrl_frac = 1; + u32 val; + u32 reg_val, hclk_reg; + bool h_autoslow; + + /* make sure the cpu div_xtal is 1 */ + reg_val = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_CPU); + reg_val &= ~(BM_CLKCTRL_CPU_DIV_XTAL); + reg_val |= (1 << BP_CLKCTRL_CPU_DIV_XTAL); + __raw_writel(reg_val, CLKCTRL_BASE_ADDR+HW_CLKCTRL_CPU); + + if (rate < ref_xtal_get_rate(&ref_xtal_clk)) + return -EINVAL; + + if (rate == clk_get_rate(clk)) + return 0; + /* temporaily disable h autoslow to avoid + * hclk getting too slow while temporarily + * changing clocks + */ + h_autoslow = mx23_enable_h_autoslow(false); + + if (rate == ref_xtal_get_rate(&ref_xtal_clk)) { + + /* switch to the 24M source */ + clk_set_parent(clk, &ref_xtal_clk); + + /* to avoid bus starvation issues, we'll go ahead + * and change hbus clock divider to 1 now. Cpufreq + * or other clock management can lower it later if + * desired for power savings or other reasons, but + * there should be no need to with hbus autoslow + * functionality enabled. + */ + + ret = clk_busy_wait(&cpu_clk); + if (ret) { + printk(KERN_ERR "* couldn't set\ + up CPU divisor\n"); + return ret; + } + + ret = clk_busy_wait(&h_clk); + if (ret) { + printk(KERN_ERR "* H_CLK busy timeout\n"); + return ret; + } + + hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS); + hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV); + hclk_reg |= (1 << BP_CLKCTRL_HBUS_DIV); + + __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); + + ret = clk_busy_wait(&cpu_clk); + if (ret) { + printk(KERN_ERR "** couldn't set\ + up CPU divisor\n"); + return ret; + } + + ret = clk_busy_wait(&h_clk); + if (ret) { + printk(KERN_ERR "** CLK busy timeout\n"); + return ret; + } + + } else { + for ( ; c < 0x40; c++) { + u32 f = ((root_rate/1000)*18/c + (rate/1000)/2) / + (rate/1000); + int s1, s2; + + if (f < 18 || f > 35) + continue; + s1 = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu - + (rate/1000); + s2 = (root_rate/1000)*18/c/f - (rate/1000); + if (abs(s1) > abs(s2)) { + clkctrl_cpu = c; + clkctrl_frac = f; + } + if (s2 == 0) + break; + }; + if (c == 0x40) { + int d = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu - + (rate/1000); + if ((abs(d) > 100) || (clkctrl_frac < 18) || + (clkctrl_frac > 35)) + return -EINVAL; + } + + /* prepare Frac div */ + val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + val &= ~(BM_CLKCTRL_FRAC_CPUFRAC); + val |= (clkctrl_frac << BP_CLKCTRL_FRAC_CPUFRAC); + + /* prepare clkctrl_cpu div*/ + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + reg_val &= ~0x3F; + reg_val |= clkctrl_cpu; + + /* set safe hbus clock divider. A divider of 3 ensure that + * the Vddd voltage required for the cpuclk is sufficiently + * high for the hbus clock and under 24MHz cpuclk conditions, + * a divider of at least 3 ensures hbusclk doesn't remain + * uneccesarily low which hurts performance + */ + hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS); + hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV); + hclk_reg |= (3 << BP_CLKCTRL_HBUS_DIV); + + /* if the pll was OFF, we need to turn it ON. + * Even if it was ON, we want to temporarily + * increment it by 1 to avoid turning off + * in the upcoming parent clock change to xtal. This + * avoids waiting an extra 10us for every cpu clock + * change between ref_cpu sourced frequencies. + */ + pll_enable(&pll_clk); + pll_clk.ref++; + + /* switch to XTAL CLK source temparily while + * we manipulate ref_cpu frequency */ + clk_set_parent(clk, &ref_xtal_clk); + + ret = clk_busy_wait(&h_clk); + + if (ret) { + printk(KERN_ERR "-* HCLK busy wait timeout\n"); + return ret; + } + + ret = clk_busy_wait(clk); + + if (ret) { + printk(KERN_ERR "-* couldn't set\ + up CPU divisor\n"); + return ret; + } + + __raw_writel(val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + + /* clear the gate */ + __raw_writel(BM_CLKCTRL_FRAC_CLKGATECPU, CLKCTRL_BASE_ADDR + + HW_CLKCTRL_FRAC_CLR); + + /* set the ref_cpu integer divider */ + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + + /* wait for the ref_cpu path to become stable before + * switching over to it + */ + + ret = clk_busy_wait(&ref_cpu_clk); + + if (ret) { + printk(KERN_ERR "-** couldn't set\ + up CPU divisor\n"); + return ret; + } + + /* change hclk divider to safe value for any ref_cpu + * value. + */ + __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + + ret = clk_busy_wait(&h_clk); + + if (ret) { + printk(KERN_ERR "-** HCLK busy wait timeout\n"); + return ret; + } + + clk_set_parent(clk, &ref_cpu_clk); + + /* decrement the pll_clk ref count because + * we temporarily enabled/incremented the count + * above. + */ + pll_clk.ref--; + + ret = clk_busy_wait(&cpu_clk); + + if (ret) { + printk(KERN_ERR "-*** Couldn't set\ + up CPU divisor\n"); + return ret; + } + + ret = clk_busy_wait(&h_clk); + + if (ret) { + printk(KERN_ERR "-*** HCLK busy wait timeout\n"); + return ret; + } + + } + mx23_enable_h_autoslow(h_autoslow); + return ret; +} + +static struct clk cpu_clk = { + .parent = &ref_cpu_clk, + .get_rate = cpu_get_rate, + .round_rate = cpu_round_rate, + .set_rate = cpu_set_rate, + .set_parent = clkseq_set_parent, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 7, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU, + .busy_bits = 28, + .xtal_busy_bits = 29, +}; + +static unsigned long uart_get_rate(struct clk *clk) +{ + unsigned int div; + div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL) & + BM_CLKCTRL_XTAL_DIV_UART; + return clk->parent->get_rate(clk->parent) / div; +} + +static struct clk uart_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_UART_CLK_GATE, + .get_rate = uart_get_rate, +}; + +static struct clk pwm_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_PWM_CLK24M_GATE, +}; + +static unsigned long clk_32k_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 750; +} + +static struct clk clk_32k = { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE, + .get_rate = clk_32k_get_rate, +}; + +static unsigned long lradc_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 16; +} + +static struct clk lradc_clk = { + .parent = &clk_32k, + .flags = RATE_FIXED, + .get_rate = lradc_get_rate, +}; + +static unsigned long x_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS) & + BM_CLKCTRL_XBUS_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static unsigned long x_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + /* while the reference manual specifies that divider + * values up to 1023 are aloud, other critial SoC compents + * require higher x clock values at all times. Through + * limited testing, the lradc functionality to measure + * the battery voltage and copy this value to the + * power supply requires at least a 64kHz xclk. + * so the divider will be limited to 375. + */ + if ((div == 0) || (div > 375)) + return root_rate; + if (frac_rate == 0) + return rate; + else + return root_rate / (div + 1); +} + +static int x_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned long round_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + + if ((!clk->round_rate) || !(clk->scale_reg)) + return -EINVAL; + + round_rate = clk->round_rate(clk, rate); + div = root_rate / round_rate; + + if (root_rate % round_rate) + return -EINVAL; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + reg &= ~(BM_CLKCTRL_XBUS_DIV_FRAC_EN | BM_CLKCTRL_XBUS_DIV); + reg |= BF_CLKCTRL_XBUS_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + + return clk_busy_wait(clk); + +} + +static struct clk x_clk = { + .parent = &ref_xtal_clk, + .get_rate = x_get_rate, + .set_rate = x_set_rate, + .round_rate = x_round_rate, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS, + .busy_bits = 31, +}; + + + +static struct clk ana_clk = { + .parent = &ref_xtal_clk, +}; + + + +static unsigned long xtal_clock32k_get_rate(struct clk *clk) +{ + if (__raw_readl(RTC_BASE_ADDR + HW_RTC_PERSISTENT0) & + BM_RTC_PERSISTENT0_XTAL32_FREQ) + return 32000; + else + return 32768; +} + +static struct clk xtal_clock32k_clk = { + .get_rate = xtal_clock32k_get_rate, +}; + +static unsigned long rtc32k_get_rate(struct clk *clk) +{ + if (clk->parent == &ref_xtal_clk) + /* mx23 reference manual had error. + * fixed divider is 750 not 768 + */ + return clk->parent->get_rate(clk->parent) / 750; + else + return xtal_clock32k_get_rate(clk); +} + +static struct clk rtc32k_clk = { + .parent = &xtal_clock32k_clk, + .get_rate = rtc32k_get_rate, +}; + +static unsigned long h_get_rate(struct clk *clk) +{ + unsigned long reg, div; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + div = reg & BM_CLKCTRL_HBUS_DIV; + return clk->parent->get_rate(clk->parent) / div; +} + +static unsigned long h_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x20)) + return root_rate; + if (frac_rate == 0) + return rate; + else + return root_rate / (div + 1); +} + +static int h_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned long round_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + round_rate = h_round_rate(clk, rate); + div = root_rate / round_rate; + if ((div == 0) || (div >= 0x20)) + return -EINVAL; + + if (root_rate % round_rate) + return -EINVAL; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | BM_CLKCTRL_HBUS_DIV); + reg |= BF_CLKCTRL_HBUS_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + + if (clk_busy_wait(clk)) { + printk(KERN_ERR "couldn't set up AHB divisor\n"); + return -EINVAL; + } + + return 0; +} + +static struct clk h_clk = { + .parent = &cpu_clk, + .get_rate = h_get_rate, + .set_rate = h_set_rate, + .round_rate = h_round_rate, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS, + .busy_bits = 31, +}; + +static struct clk ocrom_clk = { + .parent = &h_clk, +}; + +static unsigned long emi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI); + if (clk->parent == &ref_emi_clk) + reg = (reg & BM_CLKCTRL_EMI_DIV_EMI); + else + reg = (reg & BM_CLKCTRL_EMI_DIV_XTAL) >> + BP_CLKCTRL_EMI_DIV_XTAL; + return clk->parent->get_rate(clk->parent) / reg; +} + +static unsigned long emi_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate = clk->parent->get_rate(clk->parent); + unsigned int div = root_rate / rate; + if (div == 0) + return root_rate; + if (clk->parent == &ref_emi_clk) { + if (div > 0x3F) + div = 0x3F; + return root_rate / div; + } + if (div > 0xF) + div = 0xF; + return root_rate / div; +} + +/* when changing the emi clock, dram access must be + * disabled. Special handling is needed to perform + * the emi clock change without touching sdram. + */ +static int emi_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = 0; + + struct mxs_emi_scaling_data sc_data; + + unsigned long clkctrl_emi; + unsigned long clkctrl_frac; + int div = 1; + unsigned long root_rate, cur_emi_div, cur_emi_frac; + struct clk *target_parent_p = &ref_xtal_clk; + + if (rate < ref_xtal_get_rate(&ref_xtal_clk)) + return -EINVAL; + + if (!mxs_ram_funcs_sz) + goto out; + + sc_data.cur_freq = (clk->get_rate(clk)) / 1000 / 1000; + sc_data.new_freq = rate / 1000 / 1000; + + if (sc_data.cur_freq == sc_data.new_freq) + goto out; + + if (rate != ref_xtal_get_rate(&ref_xtal_clk)) { + target_parent_p = &ref_emi_clk; + pll_enable(&pll_clk); + + root_rate = pll_clk.get_rate(&pll_clk); + + for (clkctrl_emi = div; clkctrl_emi < 0x3f; + clkctrl_emi += div) { + clkctrl_frac = ((root_rate / 1000) * 18 + + (rate / 1000) * clkctrl_emi / 2) / + ((rate / 1000) * clkctrl_emi); + if (clkctrl_frac >= 18 && clkctrl_frac <= 35) { + pr_debug("%s: clkctrl_frac found %ld for %ld\n", + __func__, clkctrl_frac, clkctrl_emi); + if (((root_rate / 1000) * 18 / + clkctrl_frac / clkctrl_emi) / 1000 == + rate / 1000 / 1000) + break; + } + } + + if (clkctrl_emi >= 0x3f) + return -EINVAL; + pr_debug("%s: clkctrl_emi %ld, clkctrl_frac %ld\n", + __func__, clkctrl_emi, clkctrl_frac); + + sc_data.emi_div = clkctrl_emi; + sc_data.frac_div = clkctrl_frac; + } + + + cur_emi_div = ((__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_EMI) & + BM_CLKCTRL_EMI_DIV_EMI) >> BP_CLKCTRL_EMI_DIV_EMI); + cur_emi_frac = ((__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_FRAC) & + BM_CLKCTRL_EMI_DIV_EMI) >> BP_CLKCTRL_FRAC_EMIFRAC); + + if ((cur_emi_div == sc_data.emi_div) && + (cur_emi_frac == sc_data.frac_div)) + goto out; + { + unsigned long iram_phy; + bool h_autoslow; + int (*scale)(struct mxs_emi_scaling_data *) = + iram_alloc(mxs_ram_funcs_sz, &iram_phy); + + if (NULL == scale) { + pr_err("%s Not enough iram\n", __func__); + return -ENOMEM; + } + + /* temporaily disable h autoslow to maximize + * performance/minimize time spent with no + * sdram access + */ + h_autoslow = mx23_enable_h_autoslow(false); + + memcpy(scale, mxs_ram_freq_scale, mxs_ram_funcs_sz); + + local_irq_disable(); + local_fiq_disable(); + + scale(&sc_data); + + iram_free(iram_phy, mxs_ram_funcs_sz); + + local_fiq_enable(); + local_irq_enable(); + + /* temporaily disable h autoslow to avoid + * hclk getting too slow while temporarily + * changing clocks + */ + mx23_enable_h_autoslow(h_autoslow); + } + + /* this code is for keeping track of ref counts. + * and disabling previous parent if necessary + * actual clkseq changes have already + * been made. + */ + clk_set_parent(clk, target_parent_p); + +out: + return ret; +} + +static struct clk emi_clk = { + .parent = &ref_emi_clk, + .get_rate = emi_get_rate, + .set_rate = emi_set_rate, + .round_rate = emi_round_rate, + .set_parent = clkseq_set_parent, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, + .enable_bits = BM_CLKCTRL_EMI_CLKGATE, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, + .busy_bits = 28, + .xtal_busy_bits = 29, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 6, +}; + +static unsigned long ssp_get_rate(struct clk *clk); + +static int ssp_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + u32 reg, div; + bool is_clk_enable; + + is_clk_enable = mx23_is_clk_enabled(clk); + if (!is_clk_enable) + local_clk_enable(clk); + + /* if the desired clock can be sourced from ref_xtal, + * use ref_xtal to save power + */ + if ((rate <= ref_xtal_get_rate(&ref_xtal_clk)) && + ((ref_xtal_get_rate(&ref_xtal_clk) % rate) == 0)) + clk_set_parent(clk, &ref_xtal_clk); + else + clk_set_parent(clk, &ref_io_clk); + + if (rate > PLL_ENABLED_MAX_CLK_SSP) + rate = PLL_ENABLED_MAX_CLK_SSP; + + div = (clk_get_rate(clk->parent) + rate - 1) / rate; + + if (div == 0 || div > BM_CLKCTRL_SSP_DIV) + goto out; + + reg = __raw_readl(clk->scale_reg); + reg &= ~(BM_CLKCTRL_SSP_DIV | BM_CLKCTRL_SSP_DIV_FRAC_EN); + reg |= div << clk->scale_bits; + __raw_writel(reg, clk->scale_reg); + + ret = clk_busy_wait(clk); +out: + if (!is_clk_enable) + local_clk_disable(clk); + + if (ret != 0) + printk(KERN_ERR "%s: error %d\n", __func__, ret); + return ret; +} + +static int ssp_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + + if (clk->bypass_reg) { + if (clk->parent == parent) + return 0; + if (parent == &ref_io_clk) + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + else + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + clk->parent = parent; + ret = 0; + } + + return ret; +} + +/* handle peripheral clocks whose optimal parent dependent on + * system parameters such as cpu_clk rate. For now, this optimization + * only occurs to the peripheral clock when it's not in use to avoid + * handling more complex system clock coordination issues. + */ +static int ssp_set_sys_dependent_parent(struct clk *clk) +{ + if ((clk->ref & CLK_EN_MASK) == 0) { + if (clk_get_rate(&cpu_clk) > ref_xtal_get_rate(&ref_xtal_clk)) { + clk_set_parent(clk, &ref_io_clk); + clk_set_rate(clk, PLL_ENABLED_MAX_CLK_SSP); + } else { + clk_set_parent(clk, &ref_xtal_clk); + clk_set_rate(clk, ref_xtal_get_rate(&ref_xtal_clk)); + } + } + + return 0; +} + +static struct clk ssp_clk = { + .parent = &ref_io_clk, + .get_rate = ssp_get_rate, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP, + .enable_bits = BM_CLKCTRL_SSP_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 5, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + .set_sys_dependent_parent = ssp_set_sys_dependent_parent, +}; + +static unsigned long ssp_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP) & + BM_CLKCTRL_SSP_DIV; + + return clk->parent->get_rate(clk->parent) / reg; +} + +static unsigned long gpmi_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) & + BM_CLKCTRL_GPMI_DIV; + + return clk->parent->get_rate(clk->parent) / reg; +} + +static int gpmi_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + u32 reg, div; + + /* Make absolutely certain the clock is enabled. */ + local_clk_enable(clk); + + /* if the desired clock can be sourced from ref_xtal, + * use ref_xtal to save power + */ + if ((rate <= ref_xtal_get_rate(&ref_xtal_clk)) && + ((ref_xtal_get_rate(&ref_xtal_clk) % rate) == 0)) + clk_set_parent(clk, &ref_xtal_clk); + else + clk_set_parent(clk, &ref_io_clk); + + if (rate > PLL_ENABLED_MAX_CLK_SSP) + rate = PLL_ENABLED_MAX_CLK_GPMI; + + div = (clk_get_rate(clk->parent) + rate - 1) / rate; + + if (div == 0 || div > BM_CLKCTRL_GPMI_DIV) + goto out; + + reg = __raw_readl(clk->scale_reg); + reg &= ~(BM_CLKCTRL_GPMI_DIV | BM_CLKCTRL_GPMI_DIV_FRAC_EN); + reg |= div << clk->scale_bits; + __raw_writel(reg, clk->scale_reg); + + ret = clk_busy_wait(clk); + +out: + + /* Undo the enable above. */ + local_clk_disable(clk); + + if (ret != 0) + printk(KERN_ERR "%s: error %d\n", __func__, ret); + return ret; +} + +static int gpmi_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + + if (clk->bypass_reg) { + if (clk->parent == parent) + return 0; + if (parent == &ref_io_clk) + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + else + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + clk->parent = parent; + ret = 0; + } + + return ret; +} + +/* handle peripheral clocks whose optimal parent dependent on + * system parameters such as cpu_clk rate. For now, this optimization + * only occurs to the peripheral clock when it's not in use to avoid + * handling more complex system clock coordination issues. + */ +static int gpmi_set_sys_dependent_parent(struct clk *clk) +{ + + if ((clk->ref & CLK_EN_MASK) == 0) { + if (clk_get_rate(&cpu_clk) > ref_xtal_get_rate(&ref_xtal_clk)) { + clk_set_parent(clk, &ref_io_clk); + clk_set_rate(clk, PLL_ENABLED_MAX_CLK_GPMI); + } else { + clk_set_parent(clk, &ref_xtal_clk); + clk_set_rate(clk, ref_xtal_get_rate(&ref_xtal_clk)); + } + } + + return 0; +} + +static struct clk gpmi_clk = { + .parent = &ref_io_clk, + .secondary = 0, + .flags = 0, + .set_parent = gpmi_set_parent, + .set_sys_dependent_parent = gpmi_set_sys_dependent_parent, + + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .enable_bits = BM_CLKCTRL_GPMI_CLKGATE, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .scale_bits = 0, + .round_rate = 0, + .set_rate = gpmi_set_rate, + .get_rate = gpmi_get_rate, + + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 4, + + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .busy_bits = 29, +}; + +static unsigned long pcmspdif_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 4; +} + +static struct clk pcmspdif_clk = { + .parent = &pll_clk, + .get_rate = pcmspdif_get_rate, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SPDIF, + .enable_bits = BM_CLKCTRL_SPDIF_CLKGATE, +}; + +/* usb_clk for usb0 */ +static struct clk usb_clk = { + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL, + .enable_bits = BM_DIGCTL_CTRL_USB_CLKGATE, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk audio_clk = { + .parent = &ref_xtal_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_FILT_CLK24M_GATE, +}; + +static struct clk vid_clk = { + .parent = &ref_xtal_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEVID, +}; + +static struct clk tv108M_ng_clk = { + .parent = &vid_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_TV, + .enable_bits = BM_CLKCTRL_TV_CLK_TV108M_GATE, + .flags = RATE_FIXED, +}; + +static struct clk tv27M_clk = { + .parent = &vid_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_TV, + .enable_bits = BM_CLKCTRL_TV_CLK_TV_GATE, + .flags = RATE_FIXED, +}; + +static struct clk_lookup onchip_clocks[] = { + { + .con_id = "pll.0", + .clk = &pll_clk, + }, + { + .con_id = "ref_xtal", + .clk = &ref_xtal_clk, + }, + { + .con_id = "ref_cpu", + .clk = &ref_cpu_clk, + }, + { + .con_id = "ref_emi", + .clk = &ref_emi_clk, + }, + { + .con_id = "ref_io.0", + .clk = &ref_io_clk, + }, + { + .con_id = "ref_pix", + .clk = &ref_pix_clk, + }, + { + .con_id = "lcdif", + .clk = &lcdif_clk, + }, + { + .con_id = "xtal_clock32k", + .clk = &xtal_clock32k_clk, + }, + { + .con_id = "rtc", + .clk = &rtc32k_clk, + }, + { + .con_id = "cpu", + .clk = &cpu_clk, + }, + { + .con_id = "h", + .clk = &h_clk, + }, + { + .con_id = "x", + .clk = &x_clk, + }, + { + .con_id = "ocrom", + .clk = &ocrom_clk, + }, + { + .con_id = "clk_32k", + .clk = &clk_32k, + }, + { + .con_id = "uart", + .clk = &uart_clk, + }, + { + .con_id = "pwm", + .clk = &pwm_clk, + }, + { + .con_id = "lradc", + .clk = &lradc_clk, + }, + { + .con_id = "ssp.0", + .clk = &ssp_clk, + }, + { + .con_id = "emi", + .clk = &emi_clk, + }, + { + .con_id = "usb_clk0", + .clk = &usb_clk, + }, + { + .con_id = "audio", + .clk = &audio_clk, + }, + { + .con_id = "spdif", + .clk = &pcmspdif_clk, + }, + { + .con_id = "ref_vid", + .clk = &vid_clk, + }, + { + .con_id = "tv108M_ng", + .clk = &tv108M_ng_clk, + }, + { + .con_id = "tv27M", + .clk = &tv27M_clk, + }, + { + .con_id = "gpmi", + .clk = &gpmi_clk, + }, +}; + +/* for debugging */ +#ifdef DEBUG +static void print_ref_counts(void) +{ + + printk(KERN_INFO "pll_clk ref count: %i\n", + pll_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "ref_cpu_clk ref count: %i\n", + ref_cpu_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "ref_emi_clk ref count: %i\n", + ref_emi_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "lcdif_clk ref count: %i\n", + lcdif_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "ref_io_clk ref count: %i\n", + ref_io_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "ssp_clk ref count: %i\n", + ssp_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "gpmi_clk ref count: %i\n", + gpmi_clk.ref & CLK_EN_MASK); + +} +#endif + +static void mx23_clock_scan(void) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) + cpu_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) + emi_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) + ssp_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) + gpmi_clk.parent = &ref_xtal_clk; + + reg = __raw_readl(RTC_BASE_ADDR + HW_RTC_PERSISTENT0); + if (!(reg & BM_RTC_PERSISTENT0_CLOCKSOURCE)) + rtc32k_clk.parent = &ref_xtal_clk; +}; + +void __init mx23_set_input_clk(unsigned long xtal0, + unsigned long xtal1, + unsigned long xtal2, unsigned long enet) +{ + +} + +void __init mx23_clock_init(void) +{ + int i; + mx23_clock_scan(); + for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) + clk_register(&onchip_clocks[i]); + + clk_enable(&cpu_clk); + clk_enable(&emi_clk); + + clk_en_public_h_asm_ctrl(mx23_enable_h_autoslow, + mx23_set_hbus_autoslow_flags); +} diff --git a/arch/arm/mach-mx23/device.c b/arch/arm/mach-mx23/device.c new file mode 100644 index 000000000000..835254017f46 --- /dev/null +++ b/arch/arm/mach-mx23/device.c @@ -0,0 +1,1066 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "device.h" +#include "mx23_pins.h" +#include "mx23evk.h" +#include "mach/mx23.h" + +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) +static struct resource duart_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = DUART_PHYS_ADDR, + .end = DUART_PHYS_ADDR + 0x1000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_DEBUG_UART , + .end = IRQ_DEBUG_UART , + }, +}; + +static void __init mx23_init_duart(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-duart", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = duart_resource; + pdev->num_resources = ARRAY_SIZE(duart_resource); + mxs_add_device(pdev, 3); +} +#else +static void mx23_init_duart(void) +{ +} +#endif + +#if defined(CONFIG_MXS_DMA_ENGINE) +static struct resource mxs_ahb_apbh_res = { + .flags = IORESOURCE_MEM, + .start = APBH_DMA_PHYS_ADDR, + .end = APBH_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbh_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBH, + .chan_num = 8, +}; + +static struct resource mxs_ahb_apbx_res = { + .flags = IORESOURCE_MEM, + .start = APBX_DMA_PHYS_ADDR, + .end = APBX_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbx_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBX, + .chan_num = 16, +}; + +static void __init mx23_init_dma(void) +{ + int i; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev; + lookup = mxs_get_devices("mxs-dma"); + if (lookup == NULL || IS_ERR(lookup)) + return; + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + if (!strcmp(pdev->name, "mxs-dma-apbh")) { + pdev->resource = &mxs_ahb_apbh_res; + pdev->dev.platform_data = &mxs_ahb_apbh_data; + } else if (!strcmp(pdev->name, "mxs-dma-apbx")) { + pdev->resource = &mxs_ahb_apbx_res; + pdev->dev.platform_data = &mxs_ahb_apbx_data; + } else + continue; + pdev->num_resources = 1; + mxs_add_device(pdev, 0); + } +} +#else +static void mx23_init_dma(void) +{ + ; +} +#endif + +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) +static struct resource framebuffer_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = LCDIF_PHYS_ADDR, + .end = LCDIF_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LCDIF_ERROR, + .end = IRQ_LCDIF_ERROR, + }, +}; + +static struct mxs_platform_fb_data mxs_framebuffer_pdata = { + .list = LIST_HEAD_INIT(mxs_framebuffer_pdata.list), +}; + +static void __init mx23_init_lcdif(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-fb", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = framebuffer_resource; + pdev->num_resources = ARRAY_SIZE(framebuffer_resource); + pdev->dev.platform_data = &mxs_framebuffer_pdata; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_lcdif(void) +{ + ; +} +#endif + +#if defined(CONFIG_VIDEO_MXS_PXP) || \ + defined(CONFIG_VIDEO_MXS_PXP_MODULE) +static struct resource pxp_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = (unsigned int)IO_ADDRESS(PXP_PHYS_ADDR), + .end = (unsigned int)IO_ADDRESS(PXP_PHYS_ADDR) + 0x2000 - 1, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_PXP, + .end = IRQ_PXP, + }, +}; +static void __init mx23_init_pxp(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-pxp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = pxp_resource; + pdev->num_resources = ARRAY_SIZE(pxp_resource); + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_pxp(void) +{ + ; +} +#endif + +#if defined(CONFIG_MXS_VIIM) || defined(CONFIG_MXS_VIIM_MODULE) +struct resource viim_resources[] = { + [0] = { + .start = DIGCTL_PHYS_ADDR, + .end = DIGCTL_PHYS_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OCOTP_PHYS_ADDR, + .end = OCOTP_PHYS_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +static void __init mx23_init_viim(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs_viim", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->resource = viim_resources; + pdev->num_resources = ARRAY_SIZE(viim_resources); + + mxs_add_device(pdev, 2); +} +#else +static void __init mx23_init_viim(void) +{ +} +#endif + +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) +static struct resource i2c_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = I2C0_PHYS_ADDR, + .end = I2C0_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_I2C, + .end = MXS_DMA_CHANNEL_AHB_APBX_I2C, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C_ERROR, + .end = IRQ_I2C_ERROR, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C_DMA, + .end = IRQ_I2C_DMA, + }, +}; + +static struct mxs_i2c_plat_data i2c_platdata = { +#ifdef CONFIG_I2C_MXS_SELECT0_PIOQUEUE_MODE + .pioqueue_mode = 0, +#endif +}; + +static void __init mx23_init_i2c(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-i2c", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->resource = i2c_resource; + pdev->num_resources = ARRAY_SIZE(i2c_resource); + pdev->dev.platform_data = &i2c_platdata; + + mxs_add_device(pdev, 2); +} +#else +static void __init mx23_init_i2c(void) +{ +} +#endif + +#if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE) +static struct resource mx23_wdt_res = { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, +}; + +static void __init mx23_init_wdt(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-wdt", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = &mx23_wdt_res; + pdev->num_resources = 1; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_wdt(void) +{ + ; +} +#endif + +#if defined(CONFIG_RTC_DRV_MXS) || defined(CONFIG_RTC_DRV_MXS_MODULE) +static struct resource mx23_rtc_res[] = { + { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_1MSEC, + .end = IRQ_RTC_1MSEC, + }, +}; + +static void __init mx23_init_rtc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-rtc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_rtc_res; + pdev->num_resources = ARRAY_SIZE(mx23_rtc_res); + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_rtc(void) +{ + ; +} +#endif + +#ifdef CONFIG_MXS_LRADC +struct mxs_lradc_plat_data mx23_lradc_data = { + .vddio_voltage = BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6, + .battery_voltage = BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7, +}; + +static struct resource mx23_lradc_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, +}; + +static void __init mx23_init_lradc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-lradc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_lradc_res; + pdev->num_resources = ARRAY_SIZE(mx23_lradc_res); + pdev->dev.platform_data = &mx23_lradc_data; + mxs_add_device(pdev, 0); +} +#else +static void __init mx23_init_lradc(void) +{ + ; +} +#endif + +#if defined(CONFIG_KEYBOARD_MXS) || defined(CONFIG_KEYBOARD_MXS_MODULE) +static struct mxskbd_keypair keyboard_data[] = { + { 100, KEY_F1 }, + { 306, KEY_RIGHT}, + { 626, KEY_F2}, + { 932, KEY_LEFT }, + { 1584, KEY_UP }, + { 2207, KEY_DOWN }, + { 1907, KEY_F3 }, + { 2831, KEY_SELECT }, + { -1, 0 }, +}; + +static struct mxs_kbd_plat_data mxs_kbd_data = { + .keypair = keyboard_data, + .channel = LRADC_CH0, +}; + +static struct resource mx23_kbd_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH0, + .end = IRQ_LRADC_CH0, + }, +}; + +static void __init mx23_init_kbd(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-kbd", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_kbd_res; + pdev->num_resources = ARRAY_SIZE(mx23_kbd_res); + pdev->dev.platform_data = &mxs_kbd_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_kbd(void) +{ + ; +} +#endif + +#if defined(CONFIG_TOUCHSCREEN_MXS) || defined(CONFIG_TOUCHSCREEN_MXS_MODULE) +static struct mxs_touchscreen_plat_data mx23_ts_data = { + .x_plus_chan = LRADC_TOUCH_X_PLUS, + .x_minus_chan = LRADC_TOUCH_X_MINUS, + .y_plus_chan = LRADC_TOUCH_Y_PLUS, + .y_minus_chan = LRADC_TOUCH_Y_MINUS, + .x_plus_val = BM_LRADC_CTRL0_XPLUS_ENABLE, + .x_minus_val = BM_LRADC_CTRL0_XMINUS_ENABLE, + .y_plus_val = BM_LRADC_CTRL0_YPLUS_ENABLE, + .y_minus_val = BM_LRADC_CTRL0_YMINUS_ENABLE, + .x_plus_mask = BM_LRADC_CTRL0_XPLUS_ENABLE, + .x_minus_mask = BM_LRADC_CTRL0_XMINUS_ENABLE, + .y_plus_mask = BM_LRADC_CTRL0_YPLUS_ENABLE, + .y_minus_mask = BM_LRADC_CTRL0_YMINUS_ENABLE, +}; + +static struct resource mx23_ts_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_TOUCH_DETECT, + .end = IRQ_TOUCH_DETECT, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH5, + .end = IRQ_LRADC_CH5, + }, +}; + +static void __init mx23_init_ts(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-ts", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_ts_res; + pdev->num_resources = ARRAY_SIZE(mx23_ts_res); + pdev->dev.platform_data = &mx23_ts_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_ts(void) +{ + ; +} +#endif + +#if defined(CONFIG_CRYPTO_DEV_DCP) + +static struct resource dcp_resources[] = { + + { + .flags = IORESOURCE_MEM, + .start = DCP_PHYS_ADDR, + .end = DCP_PHYS_ADDR + 0x2000 - 1, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_DCP_VMI, + .end = IRQ_DCP_VMI, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_DCP, + .end = IRQ_DCP, + }, +}; + +static void __init mx23_init_dcp(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("dcp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = dcp_resources; + pdev->num_resources = ARRAY_SIZE(dcp_resources); + mxs_add_device(pdev, 3); +} +#else +static void __init mx23_init_dcp(void) +{ + ; +} +#endif + +#if defined(CONFIG_MTD_NAND_GPMI_NFC) + +static int gpmi_nfc_platform_init(unsigned int max_chip_count) +{ + return 0; +} + +static void gpmi_nfc_platform_exit(unsigned int max_chip_count) +{ +} + +static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; + +static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { + .nfc_version = 0, + .boot_rom_version = 0, + .clock_name = "gpmi", + .platform_init = gpmi_nfc_platform_init, + .platform_exit = gpmi_nfc_platform_exit, + .min_prop_delay_in_ns = 5, + .max_prop_delay_in_ns = 9, + .max_chip_count = 2, + .boot_area_size_in_bytes = 20 * SZ_1M, + .partition_source_types = gpmi_nfc_partition_source_types, + .partitions = 0, + .partition_count = 0, +}; + +static struct resource gpmi_nfc_resources[] = { + { + .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = GPMI_PHYS_ADDR, + .end = GPMI_PHYS_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI_ATTENTION, + .end = IRQ_GPMI_ATTENTION, + }, + { + .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = BCH_PHYS_ADDR, + .end = BCH_PHYS_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_BCH, + .end = IRQ_BCH, + }, + { + .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + }, + { + .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI_DMA, + .end = IRQ_GPMI_DMA, + }, +}; + +static void __init mx23_init_gpmi_nfc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device(GPMI_NFC_DRIVER_NAME, 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &gpmi_nfc_platform_data; + pdev->resource = gpmi_nfc_resources; + pdev->num_resources = ARRAY_SIZE(gpmi_nfc_resources); + mxs_add_device(pdev, 1); +} +#else +static void mx23_init_gpmi_nfc(void) +{ +} +#endif + +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) +static unsigned long mxs_mmc_setclock_mmc0(unsigned long hz) +{ + struct clk *ssp = clk_get(NULL, "ssp.0"); + + clk_set_rate(ssp, 2 * hz); + clk_put(ssp); + + return hz; +} + +static struct mxs_mmc_platform_data mx23_mmc0_data = { + .hw_init = mxs_mmc_hw_init_mmc0, + .hw_release = mxs_mmc_hw_release_mmc0, + .get_wp = mxs_mmc_get_wp_mmc0, + .cmd_pullup = mxs_mmc_cmd_pullup_mmc0, + /* + Don't change ssp clock because ssp1 and ssp2 share one ssp clock source + ssp module have own divider. + .setclock = mxs_mmc_setclock_mmc0, + */ + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 48000000, + .read_uA = 50000, + .write_uA = 70000, + .clock_mmc = "ssp.0", + .power_mmc = NULL, +}; + +static struct resource mx23_mmc0_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = SSP1_PHYS_ADDR, + .end = SSP1_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP1_DMA, + .end = IRQ_SSP1_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP_ERROR, + .end = IRQ_SSP_ERROR, + }, +}; + +static void __init mx23_init_mmc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-mmc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx23_mmc0_resource; + pdev->num_resources = ARRAY_SIZE(mx23_mmc0_resource); + pdev->dev.platform_data = &mx23_mmc0_data; + + mxs_add_device(pdev, 2); +} +#else +static void mx23_init_mmc(void) +{ + ; +} +#endif + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct mxs_spi_platform_data ssp1_data = { + .hw_pin_init = mxs_spi_enc_pin_init, + .hw_pin_release = mxs_spi_enc_pin_release, + .clk = "ssp.0", +}; + +static struct resource ssp1_resources[] = { + { + .start = SSP1_PHYS_ADDR, + .end = SSP1_PHYS_ADDR + 0x1FFF, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_SSP1_DMA, + .end = IRQ_SSP1_DMA, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_SSP_ERROR, + .end = IRQ_SSP_ERROR, + .flags = IORESOURCE_IRQ, + }, { + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + .flags = IORESOURCE_DMA, + }, +}; + +static void __init mx23_init_spi1(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-spi", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = ssp1_resources; + pdev->num_resources = ARRAY_SIZE(ssp1_resources); + pdev->dev.platform_data = &ssp1_data; + + mxs_add_device(pdev, 3); +} +#else +static void mx23_init_spi1(void) +{ + ; +} +#endif + +#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \ + static char *cmdline_device_##name; \ + static int cmdline_device_##name##_setup(char *dev) \ + { \ + cmdline_device_##name = dev + 1; \ + return 0; \ + } \ + __setup(#name, cmdline_device_##name##_setup); \ + void mx23_init_##name(void) \ + { \ + if (!cmdline_device_##name || \ + !strcmp(cmdline_device_##name, #dev1)) \ + mx23_init_##dev1(); \ + else if (!strcmp(cmdline_device_##name, #dev2)) \ + mx23_init_##dev2(); \ + else \ + pr_err("Unknown %s assignment '%s'.\n", \ + #name, cmdline_device_##name); \ + } + +CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1) + +#if defined(CONFIG_BATTERY_MXS) +/* battery info data */ +static ddi_bc_Cfg_t battery_data = { + .u32StateMachinePeriod = 100, /* ms */ + .u16CurrentRampSlope = 75, /* mA/s */ + .u16ConditioningThresholdVoltage = 2900, /* mV */ + .u16ConditioningMaxVoltage = 3000, /* mV */ + .u16ConditioningCurrent = 60, /* mA */ + .u32ConditioningTimeout = 4*60*60*1000, /* ms (4 hours) */ + .u16ChargingVoltage = 4200, /* mV */ + /* FIXME: the current comparator could have h/w bugs in current + * detection through POWER_STS.CHRGSTS bit */ + .u16ChargingCurrent = 600, /* mA 600 */ + .u16ChargingThresholdCurrent = 60, /* mA 60 */ + .u32ChargingTimeout = 4*60*60*1000,/* ms (4 hours) */ + .u32TopOffPeriod = 30*60*1000, /* ms (30 minutes) */ + .monitorDieTemp = 1, /* Monitor the die */ + .u8DieTempHigh = 75, /* deg centigrade */ + .u8DieTempLow = 65, /* deg centigrade */ + .u16DieTempSafeCurrent = 0, /* mA */ + .monitorBatteryTemp = 0, /* Monitor the battery*/ + .u8BatteryTempChannel = 1, /* LRADC 1 */ + .u16BatteryTempHigh = 642, /* Unknown units */ + .u16BatteryTempLow = 497, /* Unknown units */ + .u16BatteryTempSafeCurrent = 0, /* mA */ +}; + +static struct resource battery_resource[] = { + {/* 0 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDD5V, + .end = IRQ_VDD5V, + }, + {/* 1 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_DCDC4P2_BO, + .end = IRQ_DCDC4P2_BO, + }, + {/* 2 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_BATT_BRNOUT, + .end = IRQ_BATT_BRNOUT, + }, + {/* 3 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDDD_BRNOUT, + .end = IRQ_VDDD_BRNOUT, + }, + {/* 4 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDD18_BRNOUT, + .end = IRQ_VDD18_BRNOUT, + }, + {/* 5 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDDIO_BRNOUT, + .end = IRQ_VDDIO_BRNOUT, + }, + {/* 6 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDD5V_DROOP, + .end = IRQ_VDD5V_DROOP, + }, +}; + +static void mx23_init_battery(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-battery", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = battery_resource, + pdev->num_resources = ARRAY_SIZE(battery_resource), + pdev->dev.platform_data = &battery_data; + mxs_add_device(pdev, 3); + +} +#else +static void mx23_init_battery(void) +{ +} +#endif + +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) +void __init mx23_init_spdif(void) +{ struct platform_device *pdev; + pdev = mxs_get_device("mxs-spdif", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + mxs_add_device(pdev, 3); +} +#else +static inline void mx23_init_spdif(void) +{ +} +#endif + +#if defined(CONFIG_MXS_PERSISTENT) +static const struct mxs_persistent_bit_config +mx23_persistent_bit_config[] = { + { .reg = 0, .start = 0, .width = 1, + .name = "CLOCKSOURCE" }, + { .reg = 0, .start = 1, .width = 1, + .name = "ALARM_WAKE_EN" }, + { .reg = 0, .start = 2, .width = 1, + .name = "ALARM_EN" }, + { .reg = 0, .start = 3, .width = 1, + .name = "CLK_SECS" }, + { .reg = 0, .start = 4, .width = 1, + .name = "XTAL24MHZ_PWRUP" }, + { .reg = 0, .start = 5, .width = 1, + .name = "XTAL32MHZ_PWRUP" }, + { .reg = 0, .start = 6, .width = 1, + .name = "XTAL32_FREQ" }, + { .reg = 0, .start = 7, .width = 1, + .name = "ALARM_WAKE" }, + { .reg = 0, .start = 8, .width = 5, + .name = "MSEC_RES" }, + { .reg = 0, .start = 13, .width = 1, + .name = "DISABLE_XTALOK" }, + { .reg = 0, .start = 14, .width = 2, + .name = "LOWERBIAS" }, + { .reg = 0, .start = 16, .width = 1, + .name = "DISABLE_PSWITCH" }, + { .reg = 0, .start = 17, .width = 1, + .name = "AUTO_RESTART" }, + { .reg = 0, .start = 18, .width = 14, + .name = "SPARE_ANALOG" }, + + { .reg = 1, .start = 0, .width = 1, + .name = "FORCE_RECOVERY" }, + { .reg = 1, .start = 1, .width = 1, + .name = "NAND_SECONDARY_BOOT" }, + { .reg = 1, .start = 2, .width = 1, + .name = "NAND_SDK_BLOCK_REWRITE" }, + { .reg = 1, .start = 3, .width = 1, + .name = "SD_SPEED_ENABLE" }, + { .reg = 1, .start = 4, .width = 1, + .name = "SD_INIT_SEQ_1_DISABLE" }, + { .reg = 1, .start = 5, .width = 1, + .name = "SD_CMD0_DISABLE" }, + { .reg = 1, .start = 6, .width = 1, + .name = "SD_INIT_SEQ_2_ENABLE" }, + { .reg = 1, .start = 7, .width = 1, + .name = "OTG_ATL_ROLE_BIT" }, + { .reg = 1, .start = 8, .width = 1, + .name = "OTG_HNP_BIT" }, + { .reg = 1, .start = 9, .width = 1, + .name = "USB_LOW_POWER_MODE" }, + { .reg = 1, .start = 10, .width = 1, + .name = "SKIP_CHECKDISK" }, + { .reg = 1, .start = 11, .width = 1, + .name = "USB_BOOT_PLAYER_MODE" }, + { .reg = 1, .start = 12, .width = 1, + .name = "ENUMERATE_500MA_TWICE" }, + { .reg = 1, .start = 13, .width = 19, + .name = "SPARE_GENERAL" }, + + { .reg = 2, .start = 0, .width = 32, + .name = "SPARE_2" }, + { .reg = 3, .start = 0, .width = 32, + .name = "SPARE_3" }, + { .reg = 4, .start = 0, .width = 32, + .name = "SPARE_4" }, + { .reg = 5, .start = 0, .width = 32, + .name = "SPARE_5" }, +}; + +static struct mxs_platform_persistent_data mx23_persistent_data = { + .bit_config_tab = mx23_persistent_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx23_persistent_bit_config), +}; + +static struct resource mx23_persistent_res[] = { + { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, + }, +}; + +static void mx23_init_persistent(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-persistent", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &mx23_persistent_data; + pdev->resource = mx23_persistent_res, + pdev->num_resources = ARRAY_SIZE(mx23_persistent_res), + mxs_add_device(pdev, 3); +} +#else +static void mx23_init_persistent() +{ +} +#endif + +#if defined(CONFIG_FSL_OTP) +/* Building up eight registers's names of a bank */ +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (4) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(CUST0, CUST1, CUST2, CUST3, CRYPTO0, CRYPTO1, CRYPTO2, CRYPTO3), + BANK(HWCAP0, HWCAP1, HWCAP2, HWCAP3, HWCAP4, HWCAP5, SWCAP, CUSTCAP), + BANK(LOCK, OPS0, OPS1, OPS2, OPS3, UN0, UN1, UN2), + BANK(ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7), +}; + +static struct fsl_otp_data otp_data = { + .fuse_name = (char **)bank_reg_desc, + .regulator_name = "vddio", + .fuse_num = BANKS * BANK_ITEMS, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS + +static void mx23_init_otp(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("ocotp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &otp_data; + pdev->resource = NULL; + pdev->num_resources = 0; + mxs_add_device(pdev, 3); +} +#else +static void mx23_init_otp(void) +{ +} +#endif + +int __init mx23_device_init(void) +{ + mx23_init_dma(); + mx23_init_viim(); + mx23_init_duart(); + mx23_init_auart(); + mx23_init_lradc(); + mx23_init_i2c(); + mx23_init_kbd(); + mx23_init_wdt(); + mx23_init_ts(); + mx23_init_rtc(); + mx23_init_dcp(); + mx23_init_ssp1(); + mx23_init_gpmi_nfc(); + mx23_init_spdif(); + mx23_init_lcdif(); + mx23_init_pxp(); + mx23_init_battery(); + mx23_init_persistent(); + mx23_init_otp(); + + return 0; +} + +static struct __initdata map_desc mx23_io_desc[] = { + { + .virtual = MX23_SOC_IO_VIRT_BASE, + .pfn = __phys_to_pfn(MX23_SOC_IO_PHYS_BASE), + .length = MX23_SOC_IO_AREA_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = MX23_OCRAM_BASE, + .pfn = __phys_to_pfn(MX23_OCRAM_PHBASE), + .length = MX23_OCRAM_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init mx23_map_io(void) +{ + iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); +} + +void __init mx23_irq_init(void) +{ + avic_init_irq(IO_ADDRESS(ICOLL_PHYS_ADDR), ARCH_NR_IRQS); +} + +static void mx23_timer_init(void) +{ + int i, reg; + mx23_clock_init(); + + mx23_timer.clk = clk_get(NULL, "clk_32k"); + if (mx23_timer.clk == NULL || IS_ERR(mx23_timer.clk)) + return; + __raw_writel(BM_TIMROT_ROTCTRL_SFTRST, + mx23_timer.base + HW_TIMROT_ROTCTRL_CLR); + for (i = 0; i < 10000; i++) { + reg = __raw_readl(mx23_timer.base + HW_TIMROT_ROTCTRL); + if (!(reg & BM_TIMROT_ROTCTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return; + __raw_writel(BM_TIMROT_ROTCTRL_CLKGATE, + mx23_timer.base + HW_TIMROT_ROTCTRL_CLR); + + reg = __raw_readl(mx23_timer.base + HW_TIMROT_ROTCTRL); + + mxs_nomatch_timer_init(&mx23_timer); +} + +struct mxs_sys_timer mx23_timer = { + .timer = { + .init = mx23_timer_init, + }, + .clk_sel = BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL, + .base = IO_ADDRESS(TIMROT_PHYS_ADDR), +}; diff --git a/arch/arm/mach-mx23/device.h b/arch/arm/mach-mx23/device.h new file mode 100644 index 000000000000..ec411552bd10 --- /dev/null +++ b/arch/arm/mach-mx23/device.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DEVICE_H__ +#define __ASM_ARCH_MACH_DEVICE_H__ + +extern struct mxs_sys_timer mx23_timer; + +extern void __init mx23_map_io(void); +extern void __init mx23_clock_init(void); +extern void __init mx23_irq_init(void); +extern int __init mx23_pinctrl_init(void); +extern int __init mx23_gpio_init(void); +extern int __init mx23_device_init(void); +extern void __init mx23_init_auart(void); +extern void __init +mx23_set_input_clk(unsigned long, unsigned long, unsigned long, unsigned long); + +#endif diff --git a/arch/arm/mach-mx23/emi.S b/arch/arm/mach-mx23/emi.S new file mode 100644 index 000000000000..41e1ea6abe71 --- /dev/null +++ b/arch/arm/mach-mx23/emi.S @@ -0,0 +1,254 @@ +/* + * Freescale MX23 low level RAM frequency manipulation + * + * Author: Vitaly Wool + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include "regs-clkctrl.h" +#include "regs-dram.h" +#include "regs-digctl.h" + +/* TODO should be move to clock.h */ +#define SCALING_DATA_EMI_DIV_OFFSET 0 +#define SCALING_DATA_FRAC_DIV_OFFSET 4 +#define SCALING_DATA_CUR_FREQ_OFFSET 8 +#define SCALING_DATA_NEW_FREQ_OFFSET 12 +#define REGS_CLKCTRL_BASE MX23_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) +#define HW_CLKCTRL_FRAC_SET_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_SET) +#define HW_CLKCTRL_FRAC_CLR_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_CLR) +#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) +#define HW_EMI_CTRL_ADDR MX23_SOC_IO_ADDRESS(REGS_EMI_PHYS + HW_EMI_CTRL) +#define HW_DRAM_CTL04_ADDR MX23_SOC_IO_ADDRESS(REGS_DRAM_PHYS + HW_DRAM_CTL04) +#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ) +.global cpu_arm926_switch_mm + +.align 8 +ENTRY(mxs_ram_freq_scale) + stmfd sp!, {r1 - r9, lr} + + ldr r5, [r0, #SCALING_DATA_NEW_FREQ_OFFSET] + ldr r6, [r0, #SCALING_DATA_CUR_FREQ_OFFSET] + ldr r7, [r0, #SCALING_DATA_EMI_DIV_OFFSET] + ldr r8, [r0, #SCALING_DATA_FRAC_DIV_OFFSET] + + adr r9, __mxs_temp_stack + + @ clean cache + ldr r1, __mxs_flush_cache_addr + mov lr, pc + mov pc, r1 + + @ put DRAM into self refresh + ldr r0, __mx23_dram_ctl00 + ldr r1, [r0, #0x20] + orr r1, r1, #(1 << 8) + str r1, [r0, #0x20] + @ wait for it to actually happen + ldr r0, __mx23_dram_emi00 +1: ldr r1, [r0, #0x10] + tst r1, #(1 << 1) + beq 1b + nop + + + @ RAM to clk from xtal + mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000) + mov r1, #(1<<6) + str r1, [r0, #4] + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) +101: ldr r1, [r0] + tst r1, #BM_CLKCTRL_EMI_BUSY_REF_XTAL + bne 101b + + @ Gate ref_emi + mov r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0xFF000000) + + mov r1, #(BM_CLKCTRL_FRAC_CLKGATEEMI) + str r1, [r0] + + + @ prepare for change + cmp r5, #24 + bgt 2f + bl mx23_ram_24M_set_timings + b 44f +2: cmp r5, #48 + bgt 3f + bl mx23_ram_48M_set_timings + b 55f +3: cmp r5, #60 + bgt 4f + bl mx23_ram_60M_set_timings + b 55f +4: cmp r5, #80 + bgt 5f + bl mx23_ram_80M_set_timings + b 55f +5: cmp r5, #96 + bgt 6f + bl mx23_ram_96M_set_timings + b 55f +6: cmp r5, #120 + bgt 7f + bl mx23_ram_120M_set_timings + b 55f +7: cmp r5, #133 + bgt 8f + bl mx23_ram_133M_set_timings + b 55f +8: bl mx23_ram_150M_set_timings + + +44: + + bl __mx23_emi_set_values_xtal + + @ resttore normal DRAM mode + ldr r0, __mx23_dram_ctl00 + ldr r1, [r0, #0x20] + bic r1, r1, #(1 << 8) + str r1, [r0, #0x20] + + @ wait for it to actually happen + ldr r0, __mx23_dram_emi00 +99: ldr r1, [r0, #0x10] + tst r1, #(1 << 1) + bne 99b + b 110f + +55: + @When are using the DLL, reset the DRAM controller and DLL + @start point logic (via DLL_SHIFT_RESET and DLL_RESET). + @After changing clock dividers and loading + @the new HW_DRAM_CTL* parameters, we will wait for a new DLL_LOCK + + @todo - for DRAM's that will use DLL bypass (non DDR1) + @ we should not use DLL_RESET and DLL_SHIFT_RESET. + + mov r0, #(HW_EMI_CTRL_ADDR & 0x000000FF) + orr r0, r0, #(HW_EMI_CTRL_ADDR & 0x0000FF00) + orr r0, r0, #(HW_EMI_CTRL_ADDR & 0x00FF0000) + orr r0, r0, #(HW_EMI_CTRL_ADDR & 0xFF000000) + ldr r1, [r0] @read values of HW_EMI_CTRL into R1 + orr r1, r1, #BM_EMI_CTRL_DLL_SHIFT_RESET @Set these 2 fields. + orr r1, r1, #BM_EMI_CTRL_DLL_RESET + str r1, [r0] @write back values to HW_EMI_CTRL register. + + bl __mx23_emi_set_values2 + + @ EMI back to PLL + mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000) + mov r1, #(BM_CLKCTRL_CLKSEQ_BYPASS_EMI) + @clear bypass bit + str r1, [r0, #8] + + @ Wait for BUSY_REF_EMI, to assure new clock dividers + @ are done transferring + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) +1: ldr r1, [r0] + tst r1, #BM_CLKCTRL_EMI_BUSY_REF_EMI + bne 1b + str r1, [r0] + +@todo - for DRAM's that will use DLL bypass (non DDR1) +@we should not use DLL_RESET and DLL_SHIFT_RESET. +@ if(HW_DRAM_CTL04.B.DLL_BYPASS_MODE==0) +@ { +@ +@ Clear the DLL_RESET and DLL_SHIFT_RESET bitfields +@ (\todo - is that necessary? +@ they were already set previously to reset +@ the controller/DLL start point, +@ so clearing should have no effect..) +@ +@ BF_CS2(EMI_CTRL, DLL_RESET, 0, DLL_SHIFT_RESET, 0); + + mov r0, #(HW_EMI_CTRL_ADDR & 0x000000FF) + orr r0, r0, #(HW_EMI_CTRL_ADDR & 0x0000FF00) + orr r0, r0, #(HW_EMI_CTRL_ADDR & 0x00FF0000) + orr r0, r0, #(HW_EMI_CTRL_ADDR & 0xFF000000) + ldr r1, [r0] + bic r1, #BM_EMI_CTRL_DLL_SHIFT_RESET + bic r1, #BM_EMI_CTRL_DLL_RESET + str r1, [r0] + +@ Wait for DLL locking. +@ while(HW_DRAM_CTL04.B.DLLLOCKREG==0); + + mov r0, #(HW_DRAM_CTL04_ADDR & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL04_ADDR & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL04_ADDR & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL04_ADDR & 0xFF000000) +77: ldr r1, [r0] + tst r1, #BM_DRAM_CTL04_DLLLOCKREG + beq 77b + +88: + @ resttore normal DRAM mode + ldr r0, __mx23_dram_ctl00 + ldr r1, [r0, #0x20] + bic r1, r1, #(1 << 8) + str r1, [r0, #0x20] + + @ wait for it to actually happen + ldr r0, __mx23_dram_emi00 +102: ldr r1, [r0, #0x10] + tst r1, #(1 << 1) + bne 102b + +110: +@ restore regs and return + ldmfd sp!, {r1 - r9, lr} + mov pc, lr + + .space 0x100 +__mxs_temp_stack: + .word 0 + +#include "emi.inc" + +__mxs_flush_cache_addr: + .word arm926_flush_kern_cache_all + +ENTRY(mxs_ram_funcs_sz) + .word . - mxs_ram_freq_scale + diff --git a/arch/arm/mach-mx23/emi.inc b/arch/arm/mach-mx23/emi.inc new file mode 100644 index 000000000000..290d35ed2729 --- /dev/null +++ b/arch/arm/mach-mx23/emi.inc @@ -0,0 +1,667 @@ +/* + * Freescale MX23 low level RAM timings tables for Micron mDDR + * + * Author: Vitaly Wool + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +__mx23_emi_set_values_xtal: + stmfd r9!, {r0 - r4, lr} + + mov r1, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + +32: ldr r4, [r1] + tst r4, #BM_CLKCTRL_EMI_BUSY_REF_XTAL + bne 32b + b 4f + +__mx23_emi_set_values2: + + stmfd r9!, {r0 - r4, lr} + + mov r1, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + + mov r0, #(HW_CLKCTRL_FRAC_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0xFF000000) + ldr r2, [r0] + + @clear EMIFRAC bits and store result in r4 + bic r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC + + orr r4, r4, r8, lsl #BP_CLKCTRL_FRAC_EMIFRAC + str r4, [r0] + + @ ungate ref_emi + mov r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0xFF000000) + + mov r2, #(BM_CLKCTRL_FRAC_CLKGATEEMI) + str r2, [r0] + + + @ set the integer divider + ldr r2, [r1] + bic r2, r2, #BM_CLKCTRL_EMI_DIV_EMI + orr r2, r2, r7, lsl #BP_CLKCTRL_EMI_DIV_EMI + + str r2, [r1] + + @ wait for clock to stabilize +50: ldr r2, [r1] + tst r2, #BM_CLKCTRL_EMI_BUSY_REF_EMI + bne 50b + b 4f + +@ Change integer/fractional dividers. + +@ The fractional divider and integer divider must be written in such +@ an order to guarantee that when going from a lower frequency to a +@ higher frequency that any intermediate frequencies do not exceed +@ the final frequency. For this reason, we must make sure to check +@ the current divider values with the new divider values and write +@ them in the correct order. + +1: ldr r4, [r1] + and r4, r4, #BM_CLKCTRL_EMI_DIV_EMI + /* new emi div > cur emi div? */ + cmp r4, r7 + bgt 2f + mov r4, r7 + orr r4, r4, #0x100 + +@ This was for DCC_RESYNC_ENABLE, which is deprecated in mx23 +@ orr r4, r4, r3 + + str r4, [r1] +11: ldr r4, [r1] + tst r4, #BM_CLKCTRL_EMI_BUSY_REF_EMI + bne 11b + tst r4, #BM_CLKCTRL_EMI_BUSY_REF_XTAL + bne 11b + +2: ldr r2, [r0] + + and r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC + lsr r4, r4, #8 + /* new pll div != cur pll div? */ + cmp r4, r8 + beq 3f + bic r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC + orr r4, r4, r8, lsl #8 + str r4, [r0] + nop + nop + nop + +3: ldr r4, [r1] + and r4, r4, #BM_CLKCTRL_EMI_DIV_EMI + /* new emi div != cur emi div? */ + cmp r4, r7 + beq 4f + mov r4, r7 + orr r4, r4, #0x100 + +@ This was for DCC_RESYNC_ENABLE, which is deprecated in mx23 +@ orr r4, r4, r3 + str r4, [r1] +31: ldr r4, [r1] + tst r4, #BM_CLKCTRL_EMI_BUSY_REF_EMI + bne 31b + +4: ldmfd r9!, {r0 - r4, lr} + mov pc, lr + +mx23_ram_24M_set_timings: + ldr r0, __mx23_dram_ctl00 +#ifdef CONFIG_MXS_RAM_MDDR + adr r1, __mx23_dram_24M_values +#else +// 96MHz is the lowest frequency supported for DDR1. + adr r1, __mx23_dram_96M_values +#endif +1: ldr r2, [r1] + ldr r3, [r1, #4] + mov r4, r2, lsl #2 + str r3, [r0, r4] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +mx23_ram_48M_set_timings: + ldr r0, __mx23_dram_ctl00 +#ifdef CONFIG_MXS_RAM_MDDR + adr r1, __mx23_dram_48M_values +#else +// 96MHz is the lowest frequency supported for DDR1. + adr r1, __mx23_dram_96M_values +#endif +1: ldr r2, [r1] + ldr r3, [r1, #4] + mov r4, r2, lsl #2 + str r3, [r0, r4] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +mx23_ram_60M_set_timings: + ldr r0, __mx23_dram_ctl00 +#ifdef CONFIG_MXS_RAM_MDDR + adr r1, __mx23_dram_60M_values +#else +// 96MHz is the lowest frequency supported for DDR1. + adr r1, __mx23_dram_96M_values +#endif +1: ldr r2, [r1] + ldr r3, [r1, #4] + mov r4, r2, lsl #2 + str r3, [r0, r4] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +mx23_ram_80M_set_timings: + ldr r0, __mx23_dram_ctl00 +#ifdef CONFIG_MXS_RAM_MDDR + adr r1, __mx23_dram_80M_values +#else +// 96MHz is the lowest frequency supported for DDR1. + adr r1, __mx23_dram_96M_values +#endif +1: ldr r2, [r1] + ldr r3, [r1, #4] + mov r4, r2, lsl #2 + str r3, [r0, r4] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +mx23_ram_96M_set_timings: + ldr r0, __mx23_dram_ctl00 + adr r1, __mx23_dram_96M_values +1: ldr r2, [r1] + ldr r3, [r1, #4] + mov r4, r2, lsl #2 + str r3, [r0, r4] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +mx23_ram_120M_set_timings: + ldr r0, __mx23_dram_ctl00 + adr r1, __mx23_dram_120M_values +1: ldr r2, [r1] + ldr r3, [r1, #4] + mov r4, r2, lsl #2 + str r3, [r0, r4] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +mx23_ram_133M_set_timings: + ldr r0, __mx23_dram_ctl00 + adr r1, __mx23_dram_133M_values +1: ldr r2, [r1] + ldr r3, [r1, #4] + str r3, [r0, r2, lsl #2] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +mx23_ram_150M_set_timings: + ldr r0, __mx23_dram_ctl00 + adr r1, __mx23_dram_150M_values +1: ldr r2, [r1] + ldr r3, [r1, #4] + str r3, [r0, r2, lsl #2] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +__mx23_dram_ctl00: + .word MX23_SOC_IO_ADDRESS(REGS_DRAM_PHYS) +__mx23_dram_emi00: + .word MX23_SOC_IO_ADDRESS(REGS_EMI_PHYS) +__mx23_power_vdddctrl: + .word MX23_SOC_IO_ADDRESS(REGS_POWER_PHYS + HW_POWER_VDDDCTRL) + +mx23_ram_save_timings: + ldr r0, __mx23_dram_ctl00 + adr r1, __mx23_dram_saved_values +1: ldr r2, [r1] + mov r4, r2, lsl #2 + ldr r3, [r0, r4] + str r3, [r1, #4] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +#ifdef CONFIG_MXS_RAM_MDDR +__mx23_dram_24M_values: + .word 4 + .word 0x01000101 + .word 7 + .word 0x01000101 + .word 12 + .word 0x02010002 + .word 13 + .word 0x06060a02 + .word 15 + .word 0x01030000 + .word 17 + .word 0x2d000102 + .word 18 + .word 0x20200000 + .word 19 + .word 0x027f1414 + .word 20 + .word 0x01021608 + .word 21 + .word 0x00000002 + .word 26 + .word 0x000000b3 + .word 32 + .word 0x00030687 + .word 33 + .word 0x00000003 + .word 34 + .word 0x000012c1 + .word 40 + .word 0x00010000 + +__mx23_dram_48M_values: + .word 4 + .word 0x01000101 + .word 7 + .word 0x01000101 + .word 13 + .word 0x06060a02 + .word 12 + .word 0x02010002 + .word 15 + .word 0x02040000 + .word 17 + .word 0x2d000104 + .word 18 + .word 0x1f1f0000 + .word 19 + .word 0x027f0a0a + .word 20 + .word 0x02030a10 + .word 21 + .word 0x00000004 + .word 26 + .word 0x0000016f + .word 32 + .word 0x00060d17 + .word 33 + .word 0x00000006 + .word 34 + .word 0x00002582 + .word 40 + .word 0x00020000 + +__mx23_dram_60M_values: +__mx23_dram_80M_values: + .word 4 + .word 0x01000101 + .word 7 + .word 0x01000101 + .word 12 + .word 0x02020002 + .word 13 + .word 0x06060a02 + .word 15 + .word 0x02040000 + .word 17 + .word 0x2d000005 + .word 18 + .word 0x1f1f0000 + .word 19 + .word 0x027f0a0a + .word 20 + .word 0x02040a10 + .word 21 + .word 0x00000006 + .word 26 + .word 0x000001cc + .word 32 + .word 0x00081060 + .word 33 + .word 0x00000008 + .word 34 + .word 0x00002ee5 + .word 40 + .word 0x00020000 + +__mx23_dram_96M_values: + .word 4 + .word 0x00000101 + .word 7 + .word 0x01000001 + .word 12 + .word 0x02020002 + .word 13 + .word 0x06070a02 + .word 15 + .word 0x03050000 + .word 17 + .word 0x2d000808 + .word 18 + .word 0x1f1f0000 + .word 19 + .word 0x020c1010 + .word 20 + .word 0x0305101c + .word 21 + .word 0x00000007 + .word 26 + .word 0x000002e6 + .word 32 + .word 0x000c1a3b + .word 33 + .word 0x0000000c + .word 34 + .word 0x00004b0d + .word 40 + .word 0x00030000 + +__mx23_dram_120M_values: + .word 4 + .word 0x00000101 + .word 7 + .word 0x01000001 + .word 12 + .word 0x02020002 + .word 13 + .word 0x06070a02 + .word 15 + .word 0x03050000 + .word 17 + .word 0x2300080a + .word 18 + .word 0x1f1f0000 + .word 19 + .word 0x020c1010 + .word 20 + .word 0x0306101c + .word 21 + .word 0x00000009 + .word 26 + .word 0x000003a1 + .word 32 + .word 0x000f20ca + .word 33 + .word 0x0000000f + .word 34 + .word 0x00005dca + .word 40 + .word 0x00040000 + +__mx23_dram_133M_values: +__mx23_dram_150M_values: + .word 4 + .word 0x00000101 + .word 7 + .word 0x01000001 + .word 12 + .word 0x02020002 + .word 13 + .word 0x06070a02 + .word 15 + .word 0x03050000 + .word 17 + .word 0x2000080a + .word 18 + .word 0x1f1f0000 + .word 19 + .word 0x020c1010 + .word 20 + .word 0x0306101c + .word 21 + .word 0x0000000a + .word 26 + .word 0x00000408 + .word 32 + .word 0x0010245f + .word 33 + .word 0x00000010 + .word 34 + .word 0x00006808 + .word 40 + .word 0x00040000 + +#elif CONFIG_MXS_RAM_DDR + +__mx23_dram_96M_values: + .word 4 + .word 0x00000101 + .word 7 + .word 0x01000001 + .word 11 + .word 0x00070202 + .word 12 + .word 0x02020000 @ t_wr 2, t_rrd 2, t_cke 0 + .word 13 + .word 0x04040a01 @ t_wtr 1 + .word 15 + .word 0x02040000 @ t_rp 2, t_dal 4 + .word 17 + .word 0x2f001706 @ dll_start_point 0x2f, dll_increment 0x17, t_rc 6 + .word 19 + .word 0x027f1a1a + .word 20 + .word 0x02051c21 @ t_rcd 2, t_rasmin 5, wr_dqs_shift 0x22 + .word 21 + .word 0x00000007 @ t_rfc 7 + .word 26 + .word 0x000002e6 /* 0x347b */ @ t_ref + .word 32 + .word 0x00081a3e @ t_xsnr 8, t_rasmax 0x1a3e + .word 33 + .word 0x000000c8 @ t_xsr 0xc8 + .word 34 + .word 0x00004b0d @ t_init + .word 40 + .word 0x00010000 + +__mx23_dram_120M_values: + .word 4 + .word 0x00000101 + .word 7 + .word 0x01000001 + .word 11 + .word 0x00070202 + .word 12 + .word 0x02020000 @ t_wr 2, t_rrd 2, t_cke 0 + .word 13 + .word 0x04040a01 @ t_wtr 1 + .word 15 + .word 0x02040000 @ t_rp 2, t_dal 4 + .word 17 + .word 0x26001308 @ dll_start_point 0x26, dll_increment 0x13, t_rc 8 + .word 19 + .word 0x027f1a1a + .word 20 + .word 0x02061c23 @ t_rcd 2, t_rasmin 6 + .word 21 + .word 0x00000009 @ t_rfc 9 + .word 26 + .word 0x000003a1 /* 0x41a6 */ @ t_ref + .word 32 + .word 0x000a20ca @ t_xsnr 9, t_rasmax 0x20ca + .word 33 + .word 0x000000c8 @ t_xsr 0xc8 + .word 34 + .word 0x00005dca @ t_init + .word 40 + .word 0x00010000 + +__mx23_dram_133M_values: + .word 4 + .word 0x00000101 + .word 7 + .word 0x01000001 + .word 11 + .word 0x00070202 + .word 12 + .word 0x02020000 + .word 13 + .word 0x04040a01 + .word 15 + .word 0x02040000 + .word 17 + .word 0x19000f08 @ t_rc 0xa + .word 19 + .word 0x02021313 + .word 20 + .word 0x02061521 + .word 21 + .word 0x0000000a + .word 26 + .word 0x000003f7 /* 0x48b9 */ + .word 32 + .word 0x000a23cd + .word 33 + .word 0x000000c8 @ t_xsr 0xc8 + .word 34 + .word 0x00006665 + .word 40 + .word 0x00010000 + +__mx23_dram_150M_values: + .word 4 + .word 0x00000101 + .word 7 + .word 0x01000001 +/* +Note that CASLAT of 0x06 means 2.5 cycles. This is needed to operate at this +frequency. HOWEVER, we would need to implement the setting of WRITEMODEREG +after setting CAS latency to assure that the new CAS latency is actually +being used in the EMI controller. Otherwise, the controller will still be +using whatever was set the first time the EMI controller was initialized. +Also, a CASLAT of 2.5 needs caslat_lin and caslat_lin_gate of 0x05 +(also 2.5 cycles). +*/ + .word 11 + .word 0x00070206 + .word 12 + .word 0x02020000 @ t_wr 2, t_rrd 2, t_cke 0 +/* + caslat_lin and caslat_lin_gate of 0x05 since CASLAT is 0x06 (2.5 cycles). See above note. +*/ + .word 13 + .word 0x05050a02 @ t_wtr 2 + .word 15 + .word 0x03060000 @ t_rp 3, t_dal 6 + .word 17 + .word 0x18000d0c @ dll_start_point 0x18, dll_increment 0xd, t_rc 0xc + .word 19 + .word 0x027f0f0f + .word 20 + .word 0x03071121 @ t_rcd 3, t_rasmin 7 + .word 21 + .word 0x0000000c @ t_rfc 0xc + .word 26 + .word 0x000001cc /* 0x20cd */ @ t_ref + .word 32 + .word 0x000c2860 @ t_xsnr 0xc, t_rasmax 0x2860 + .word 33 + .word 0x000000c8 @ t_xsr 0xc8 + .word 34 + .word 0x00007554 @ t_init + .word 40 + .word 0x00010000 + +#else +#error RAM chip not defined +#endif + +mx23_ram_restore_timings: + ldr r0, __mx23_dram_ctl00 + adr r1, __mx23_dram_saved_values +1: ldr r2, [r1] + ldr r3, [r1, #4] + mov r4, r2, lsl #2 + str r3, [r0, r4] + add r1, r1, #8 + cmp r2, #40 + bne 1b + mov pc, lr + +__mx23_dram_saved_values: + .word 4 + .word 0 + .word 7 + .word 0 + .word 12 + .word 0 + .word 13 + .word 0 + .word 15 + .word 0 + .word 17 + .word 0 + .word 18 + .word 0 + .word 19 + .word 0 + .word 20 + .word 0 + .word 21 + .word 0 + .word 26 + .word 0 + .word 32 + .word 0 + .word 33 + .word 0 + .word 34 + .word 0 + .word 40 + .word 0 + diff --git a/arch/arm/mach-mx23/gpio.c b/arch/arm/mach-mx23/gpio.c new file mode 100644 index 000000000000..fca4534cbb2b --- /dev/null +++ b/arch/arm/mach-mx23/gpio.c @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx23_gpio_direction(struct mxs_gpio_port *port, int pin, unsigned int input) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (input) + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_CLR); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_SET); + + return 0; +} + +static int mx23_gpio_get(struct mxs_gpio_port *port, int pin) +{ + unsigned int data; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + data = __raw_readl(base + HW_PINCTRL_DIN0); + return data & (1 << pin); +} + +static void mx23_gpio_set(struct mxs_gpio_port *port, int pin, int data) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (data) + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_CLR); +} + +static unsigned int mx23_gpio_irq_stat(struct mxs_gpio_port *port) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = __raw_readl(base + HW_PINCTRL_IRQSTAT0); + mask &= __raw_readl(base + HW_PINCTRL_IRQEN0); + return mask; +} + +static int +mx23_gpio_set_irq_type(struct mxs_gpio_port *port, int pin, unsigned int type) +{ + unsigned int level, pol; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + switch (type) { + case IRQ_TYPE_EDGE_RISING: + level = 0; + pol = 1; + break; + case IRQ_TYPE_EDGE_FALLING: + level = 0; + pol = 0; + break; + case IRQ_TYPE_LEVEL_HIGH: + level = 1; + pol = 1; + break; + case IRQ_TYPE_LEVEL_LOW: + level = 1; + pol = 0; + break; + default: + pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", + __func__, type); + return -ENXIO; + } + + if (level) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_CLR); + + if (pol) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_CLR); + + return 0; +} + +static void mx23_gpio_unmask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_SET); +} + +static void mx23_gpio_mask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_CLR); +} + +static void mx23_gpio_ack_irq(struct mxs_gpio_port *port, int pin) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = 1 << pin; + if (mask) + __raw_writel(mask, base + HW_PINCTRL_IRQSTAT0_CLR); +} + +static struct mxs_gpio_port mx23_gpios[] = { + { + .irq = IRQ_GPIO0, + }, + { + .irq = IRQ_GPIO1, + }, + { + .irq = IRQ_GPIO2, + }, +}; + +static struct mxs_gpio_chip mx23_gpio_chip = { + .set_dir = mx23_gpio_direction, + .get = mx23_gpio_get, + .set = mx23_gpio_set, + .get_irq_stat = mx23_gpio_irq_stat, + .set_irq_type = mx23_gpio_set_irq_type, + .unmask_irq = mx23_gpio_unmask_irq, + .mask_irq = mx23_gpio_mask_irq, + .ack_irq = mx23_gpio_ack_irq, +}; + +int __init mx23_gpio_init(void) +{ + int i; + unsigned int reg; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + reg = __raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL); + for (i = 0; i < ARRAY_SIZE(mx23_gpios); i++) { + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * i; + if (!(reg & (BM_PINCTRL_CTRL_PRESENT0 << i))) + continue; + mxs_set_gpio_chip(&mx23_gpios[i], &mx23_gpio_chip); + mx23_gpios[i].id = i; + __raw_writel(0, base + HW_PINCTRL_IRQEN0); + __raw_writel(0xFFFFFFFF, base + HW_PINCTRL_PIN2IRQ0); + mx23_gpios[i].child_irq = MXS_GPIO_IRQ_START + + (i * PINS_PER_BANK); + mxs_add_gpio_port(&mx23_gpios[i]); + } + return 0; +} diff --git a/arch/arm/mach-mx23/include/mach/dma.h b/arch/arm/mach-mx23/include/mach/dma.h new file mode 100644 index 000000000000..ae4b7782892b --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/dma.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DMA_H__ +#define __ASM_ARCH_MACH_DMA_H__ + +enum { + MXS_DMA_CHANNEL_AHB_APBH = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_HSADC, + MXS_DMA_CHANNEL_AHB_APBH_LCDIF, + MXS_DMA_CHANNEL_AHB_APBH_14, + MXS_DMA_CHANNEL_AHB_APBH_15, + MXS_DMA_CHANNEL_AHB_APBX = 16, + MXS_DMA_CHANNEL_AHB_APBX_AUDIOADC = MXS_DMA_CHANNEL_AHB_APBX, + MXS_DMA_CHANNEL_AHB_APBX_AUDIODAC, + MXS_DMA_CHANNEL_AHB_APBX_SPDIF, + MXS_DMA_CHANNEL_AHB_APBX_I2C, + MXS_DMA_CHANNEL_AHB_APBX_SAIF1, + MXS_DMA_CHANNEL_AHB_APBX_DRI, + MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + MXS_DMA_CHANNEL_AHB_APBX_SAIF2, + MXS_DMA_CHANNEL_AHB_APBX_RESERVED1, + MXS_DMA_CHANNEL_AHB_APBX_RESERVED2, + MXS_DMA_CHANNEL_AHB_APBX_RESERVED3, + MXS_DMA_CHANNEL_AHB_APBX_RESERVED4, + MXS_DMA_CHANNEL_AHB_APBX_RESERVED5, + MAX_DMA_CHANNELS, +}; +#endif /* __ASM_ARCH_MACH_MX23_H__ */ diff --git a/arch/arm/mach-mx23/include/mach/irqs.h b/arch/arm/mach-mx23/include/mach/irqs.h new file mode 100644 index 000000000000..5d5211b6e889 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/irqs.h @@ -0,0 +1,102 @@ +/* + * Freescale STMP378X interrupts + * + * Copyright (C) 2005 Sigmatel Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#define IRQ_DEBUG_UART 0 +#define IRQ_COMMS_RX 1 +#define IRQ_COMMS_TX 1 +#define IRQ_SSP2_ERROR 2 +#define IRQ_VDD5V 3 +#define IRQ_HEADPHONE_SHORT 4 +#define IRQ_DAC_DMA 5 +#define IRQ_DAC_ERROR 6 +#define IRQ_ADC_DMA 7 +#define IRQ_ADC_ERROR 8 +#define IRQ_SPDIF_DMA 9 +#define IRQ_SAIF2_DMA 9 +#define IRQ_SPDIF_ERROR 10 +#define IRQ_SAIF1_IRQ 10 +#define IRQ_SAIF2_IRQ 10 +#define IRQ_USB_CTRL 11 +#define IRQ_USB_WAKEUP 12 +#define IRQ_GPMI_DMA 13 +#define IRQ_SSP1_DMA 14 +#define IRQ_SSP_ERROR 15 +#define IRQ_GPIO0 16 +#define IRQ_GPIO1 17 +#define IRQ_GPIO2 18 +#define IRQ_SAIF1_DMA 19 +#define IRQ_SSP2_DMA 20 +#define IRQ_ECC8_IRQ 21 +#define IRQ_RTC_ALARM 22 +#define IRQ_UARTAPP_TX_DMA 23 +#define IRQ_UARTAPP_INTERNAL 24 +#define IRQ_UARTAPP_RX_DMA 25 +#define IRQ_I2C_DMA 26 +#define IRQ_I2C_ERROR 27 +#define IRQ_TIMER0 28 +#define IRQ_TIMER1 29 +#define IRQ_TIMER2 30 +#define IRQ_TIMER3 31 +#define IRQ_BATT_BRNOUT 32 +#define IRQ_VDDD_BRNOUT 33 +#define IRQ_VDDIO_BRNOUT 34 +#define IRQ_VDD18_BRNOUT 35 +#define IRQ_TOUCH_DETECT 36 +#define IRQ_LRADC_CH0 37 +#define IRQ_LRADC_CH1 38 +#define IRQ_LRADC_CH2 39 +#define IRQ_LRADC_CH3 40 +#define IRQ_LRADC_CH4 41 +#define IRQ_LRADC_CH5 42 +#define IRQ_LRADC_CH6 43 +#define IRQ_LRADC_CH7 44 +#define IRQ_LCDIF_DMA 45 +#define IRQ_LCDIF_ERROR 46 +#define IRQ_DIGCTL_DEBUG_TRAP 47 +#define IRQ_RTC_1MSEC 48 +#define IRQ_DRI_DMA 49 +#define IRQ_DRI_ATTENTION 50 +#define IRQ_GPMI_ATTENTION 51 +#define IRQ_IR 52 +#define IRQ_DCP_VMI 53 +#define IRQ_DCP 54 +#define IRQ_BCH 56 +#define IRQ_PXP 57 +#define IRQ_UARTAPP2_TX_DMA 58 +#define IRQ_UARTAPP2_INTERNAL 59 +#define IRQ_UARTAPP2_RX_DMA 60 +#define IRQ_VDAC_DETECT 61 +#define IRQ_VDD5V_DROOP 64 +#define IRQ_DCDC4P2_BO 65 + + +#define NR_REAL_IRQS 128 +#define NR_IRQS (NR_REAL_IRQS + 32 * 3) +#define ARCH_NR_IRQS NR_REAL_IRQS + +/* All interrupts are FIQ capable */ +#define FIQ_START IRQ_DEBUG_UART + +/* Hard disk IRQ is a GPMI attention IRQ */ +#define IRQ_HARDDISK IRQ_GPMI_ATTENTION + +#ifndef __ASSEMBLY__ +void mxs_set_irq_fiq(unsigned int irq, unsigned int type); +void mxs_enable_fiq_functionality(int enable); +#endif + diff --git a/arch/arm/mach-mx23/include/mach/lcdif.h b/arch/arm/mach-mx23/include/mach/lcdif.h new file mode 100644 index 000000000000..f12802087320 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/lcdif.h @@ -0,0 +1,441 @@ +/* + * Freescale MXS LCDIF interfaces + * + * Author: Vitaly Wool + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _ARCH_ARM_LCDIF_H +#define _ARCH_ARM_LCDIF_H + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "regs-lcdif.h" + +#define REGS_LCDIF_BASE IO_ADDRESS(LCDIF_PHYS_ADDR) + +enum { + SPI_MOSI = 0, + SPI_SCLK, + SPI_CS, +}; + +struct mxs_lcd_dma_chain_info { + dma_addr_t *dma_addr_p; + unsigned offset; +}; + +enum { + MXS_LCD_PANEL_SYSTEM = 0, + MXS_LCD_PANEL_VSYNC, + MXS_LCD_PANEL_DOTCLK, + MXS_LCD_PANEL_DVI, +}; + +struct mxs_platform_bl_data; +struct mxs_platform_fb_entry { + char name[16]; + u16 x_res; + u16 y_res; + u16 bpp; + u32 cycle_time_ns; + int lcd_type; + int (*init_panel) (struct device *, dma_addr_t, int, + struct mxs_platform_fb_entry *); + void (*release_panel) (struct device *, struct mxs_platform_fb_entry *); + int (*blank_panel) (int); + void (*run_panel) (void); + void (*stop_panel) (void); + int (*pan_display) (dma_addr_t); + int (*update_panel) (void *, struct mxs_platform_fb_entry *); + struct list_head link; + struct mxs_platform_bl_data *bl_data; +}; + +struct mxs_platform_fb_data { + struct list_head list; + struct mxs_platform_fb_entry *cur; + struct mxs_platform_fb_entry *next; +}; + +#define MXS_LCDIF_PANEL_INIT 1 +#define MXS_LCDIF_PANEL_RELEASE 2 + +struct mxs_platform_bl_data { + struct list_head list; + struct regulator *regulator; + int bl_gpio; + int bl_max_intensity; + int bl_cons_intensity; + int bl_default_intensity; + int (*init_bl) (struct mxs_platform_bl_data *); + int (*set_bl_intensity) (struct mxs_platform_bl_data *, + struct backlight_device *, int); + void (*free_bl) (struct mxs_platform_bl_data *); +}; + +static inline void mxs_lcd_register_entry(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_add_tail(&pentry->link, &pdata->list); + if (!pdata->cur) + pdata->cur = pentry; +} + +static inline void mxs_lcd_move_pentry_up(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_move(&pentry->link, &pdata->list); +} + +static inline int mxs_lcd_iterate_pdata(struct mxs_platform_fb_data + *pdata, + int (*func) (struct + mxs_platform_fb_entry + * pentry, void *data, + int ret_prev), void *data) +{ + struct mxs_platform_fb_entry *pentry; + int ret = 0; + list_for_each_entry(pentry, &pdata->list, link) { + ret = func(pentry, data, ret); + } + return ret; +} + +static inline void mxs_lcd_set_bl_pdata(struct mxs_platform_bl_data + *pdata) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-bl", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->dev.platform_data = pdata; +} + +void mxs_init_lcdif(void); +int mxs_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize); +void mxs_lcdif_dma_release(void); +void mxs_lcdif_run(void); +void mxs_lcdif_stop(void); +int mxs_lcdif_pan_display(dma_addr_t addr); + +int mxs_lcdif_register_client(struct notifier_block *nb); +void mxs_lcdif_unregister_client(struct notifier_block *nb); +void mxs_lcdif_notify_clients(unsigned long event, + struct mxs_platform_fb_entry *pentry); + +#ifndef FBIO_WAITFORVSYNC +#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t) +#endif + +static inline void setup_dotclk_panel(u16 v_pulse_width, + u16 v_period, + u16 v_wait_cnt, + u16 v_active, + u16 h_pulse_width, + u16 h_period, + u16 h_wait_cnt, + u16 h_active, int enable_present) +{ + u32 val; + + __raw_writel(BM_LCDIF_CTRL_DATA_SHIFT_DIR, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL_SHIFT_NUM_BITS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(7) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) |/* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT |/* data mode */ + BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |/* no swap */ + BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(3),/* 24 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_POL | + BM_LCDIF_VDCTRL0_HSYNC_POL | + BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL); + val |= BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_OEB); + /* vsync is output */ + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + /* + * need enable sig for true RGB i/f. Or, if not true RGB, leave it + * zero. + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val |= BM_LCDIF_VDCTRL0_ENABLE_PRESENT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + /* + * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT); + val |= BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + __raw_writel(BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_CLR); + __raw_writel(v_pulse_width, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET); + + __raw_writel(BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + + __raw_writel(BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) | + BF_LCDIF_VDCTRL2_HSYNC_PERIOD(h_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val &= ~BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT; + val |= BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + val &= ~(BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT | + BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT); + val |= BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) | + BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val |= BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); +} + +static inline void release_dotclk_panel(void) +{ + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); +} + +static inline void setup_dvi_panel(u16 h_active, u16 v_active, + u16 h_blanking, u16 v_lines, + u16 v1_blank_start, u16 v1_blank_end, + u16 v2_blank_start, u16 v2_blank_end, + u16 f1_start, u16 f1_end, + u16 f2_start, u16 f2_end) +{ + u32 val; + /* 32bit packed format (RGB) */ + __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + /* set lcdif to DVI mode */ + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + /* convert input RGB -> YCbCr */ + __raw_writel(BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + /* interlace odd and even fields */ + __raw_writel(BM_LCDIF_CTRL1_INTERLACE_FIELDS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ + BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ + BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /* 8 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + /* LCDIF_DVI */ + /* set frame size */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0); + val &= ~(BM_LCDIF_DVICTRL0_H_ACTIVE_CNT | + BM_LCDIF_DVICTRL0_H_BLANKING_CNT | + BM_LCDIF_DVICTRL0_V_LINES_CNT); + val |= BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(1440) | + BF_LCDIF_DVICTRL0_H_BLANKING_CNT(h_blanking) | + BF_LCDIF_DVICTRL0_V_LINES_CNT(v_lines); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0); + + /* set start/end of field-1 and start of field-2 */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1); + val &= ~(BM_LCDIF_DVICTRL1_F1_START_LINE | + BM_LCDIF_DVICTRL1_F1_END_LINE | + BM_LCDIF_DVICTRL1_F2_START_LINE); + val |= BF_LCDIF_DVICTRL1_F1_START_LINE(f1_start) | + BF_LCDIF_DVICTRL1_F1_END_LINE(f1_end) | + BF_LCDIF_DVICTRL1_F2_START_LINE(f2_start); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1); + + /* set first vertical blanking interval and end of filed-2 */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2); + val &= ~(BM_LCDIF_DVICTRL2_F2_END_LINE | + BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE | + BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE); + val |= BF_LCDIF_DVICTRL2_F2_END_LINE(f2_end) | + BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v1_blank_start) | + BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v1_blank_end); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2); + + /* set second vertical blanking interval */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3); + val &= ~(BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE | + BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE); + val |= BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v2_blank_start) | + BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v2_blank_end); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3); + + /* fill the rest area black color if the input frame + * is not 720 pixels/line + */ + if (h_active != 720) { + /* the input frame can't be less then (720-256) pixels/line */ + if (720 - h_active > 0xff) + h_active = 720 - 0xff; + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4); + val &= ~(BM_LCDIF_DVICTRL4_H_FILL_CNT | + BM_LCDIF_DVICTRL4_Y_FILL_VALUE | + BM_LCDIF_DVICTRL4_CB_FILL_VALUE | + BM_LCDIF_DVICTRL4_CR_FILL_VALUE); + val |= BF_LCDIF_DVICTRL4_H_FILL_CNT(720 - h_active) | + BF_LCDIF_DVICTRL4_Y_FILL_VALUE(16) | + BF_LCDIF_DVICTRL4_CB_FILL_VALUE(128) | + BF_LCDIF_DVICTRL4_CR_FILL_VALUE(128); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4); + } + + /* Color Space Conversion RGB->YCbCr */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0); + val &= ~(BM_LCDIF_CSC_COEFF0_C0 | + BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER); + val |= BF_LCDIF_CSC_COEFF0_C0(0x41) | + BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(3); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1); + val &= ~(BM_LCDIF_CSC_COEFF1_C1 | BM_LCDIF_CSC_COEFF1_C2); + val |= BF_LCDIF_CSC_COEFF1_C1(0x81) | + BF_LCDIF_CSC_COEFF1_C2(0x19); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2); + val &= ~(BM_LCDIF_CSC_COEFF2_C3 | BM_LCDIF_CSC_COEFF2_C4); + val |= BF_LCDIF_CSC_COEFF2_C3(0x3DB) | + BF_LCDIF_CSC_COEFF2_C4(0x3B6); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3); + val &= ~(BM_LCDIF_CSC_COEFF3_C5 | BM_LCDIF_CSC_COEFF3_C6); + val |= BF_LCDIF_CSC_COEFF3_C5(0x70) | + BF_LCDIF_CSC_COEFF3_C6(0x70); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4); + val &= ~(BM_LCDIF_CSC_COEFF4_C7 | BM_LCDIF_CSC_COEFF4_C8); + val |= BF_LCDIF_CSC_COEFF4_C7(0x3A2) | BF_LCDIF_CSC_COEFF4_C8(0x3EE); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET); + val &= ~(BM_LCDIF_CSC_OFFSET_CBCR_OFFSET + | BM_LCDIF_CSC_OFFSET_Y_OFFSET); + val |= BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(0x80) | + BF_LCDIF_CSC_OFFSET_Y_OFFSET(0x10); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT); + val &= ~(BM_LCDIF_CSC_LIMIT_CBCR_MIN | + BM_LCDIF_CSC_LIMIT_CBCR_MAX | + BM_LCDIF_CSC_LIMIT_Y_MIN | + BM_LCDIF_CSC_LIMIT_Y_MAX); + val |= BF_LCDIF_CSC_LIMIT_CBCR_MIN(16) | + BF_LCDIF_CSC_LIMIT_CBCR_MAX(240) | + BF_LCDIF_CSC_LIMIT_Y_MIN(16) | + BF_LCDIF_CSC_LIMIT_Y_MAX(235); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT); +} + +static inline void release_dvi_panel(void) +{ + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); +} +#endif /* _ARCH_ARM_LCDIF_H */ diff --git a/arch/arm/mach-mx23/include/mach/mx23.h b/arch/arm/mach-mx23/include/mach/mx23.h new file mode 100644 index 000000000000..c22ce1223e68 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/mx23.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_MX23_H___ +#define __ASM_ARCH_MACH_MX23_H___ + +#include +#include + +#define MX23_SOC_IO_PHYS_BASE 0x80000000 +#define MX23_SOC_IO_VIRT_BASE 0xF0000000 +#define MX23_SOC_IO_AREA_SIZE SZ_1M + +/* Virtual address where OCRAM is mapped */ +#define MX23_OCRAM_PHBASE 0x00000000 +#ifdef __ASSEMBLER__ +#define MX23_OCRAM_BASE 0xf1000000 +#else +#define MX23_OCRAM_BASE (void __iomem *)0xf1000000 +#endif +#define MX23_OCRAM_SIZE (32 * SZ_1K) + +#define ICOLL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x000000) +#define APBH_DMA_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x004000) +#define BCH_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x00A000) +#define GPMI_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x00C000) +#define SSP1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x010000) +#define SSP2_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x034000) +#define PINCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x018000) +#define DIGCTL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x01C000) +#define ETM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x020000) +#define APBX_DMA_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x024000) +#define DCP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x028000) +#define PXP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02A000) +#define OCOTP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02C000) +#define AXI_AHB0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02E000) +#define LCDIF_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x030000) +#define TVENC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x038000) +#define CLKCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x040000) +#define SAIF0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x042000) +#define POWER_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x044000) +#define SAIF1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x046000) +#define AUDIOOUT_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x048000) +#define AUDIOIN_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x04c000) +#define LRADC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x050000) +#define SPDIF_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x054000) +#define RTC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x05c000) +#define I2C0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x058000) +#define PWM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x064000) +#define TIMROT_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x068000) +#define AUART1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x06C000) +#define AUART2_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x06E000) +#define DUART_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x070000) +#define USBPHY_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x07C000) +#define USBCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x080000) +#define DRAM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x0E0000) + +#define MX23_SOC_IO_ADDRESS(x) \ + ((x) - MX23_SOC_IO_PHYS_BASE + MX23_SOC_IO_VIRT_BASE) + +#ifdef __ASSEMBLER__ +#define IO_ADDRESS(x) \ + MX23_SOC_IO_ADDRESS(x) +#else +#define IO_ADDRESS(x) \ + (void __force __iomem *) \ + (((x) >= (unsigned long)MX23_SOC_IO_PHYS_BASE) && \ + ((x) < (unsigned long)MX23_SOC_IO_PHYS_BASE + \ + MX23_SOC_IO_AREA_SIZE) ? \ + MX23_SOC_IO_ADDRESS(x) : 0xDEADBEEF) +#endif + +#ifdef CONFIG_MXS_EARLY_CONSOLE +#define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR +#define MXS_DEBUG_CONSOLE_VIRT IO_ADDRESS(DUART_PHYS_ADDR) +#endif + +#ifdef CONFIG_DEBUG_LL +#define MXS_LL_UART_PADDR DUART_PHYS_ADDR +#define MXS_LL_UART_VADDR MX23_SOC_IO_ADDRESS(DUART_PHYS_ADDR) +#endif + +#endif /* __ASM_ARCH_MACH_MX23_H__ */ diff --git a/arch/arm/mach-mx23/include/mach/regs-apbh.h b/arch/arm/mach-mx23/include/mach/regs-apbh.h new file mode 100644 index 000000000000..e3ee9bef3f19 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-apbh.h @@ -0,0 +1,358 @@ +/* + * Freescale APBH Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H + + +#define HW_APBH_CTRL0 (0x00000000) +#define HW_APBH_CTRL0_SET (0x00000004) +#define HW_APBH_CTRL0_CLR (0x00000008) +#define HW_APBH_CTRL0_TOG (0x0000000c) + +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000 +#define BP_APBH_CTRL0_RSVD0 24 +#define BM_APBH_CTRL0_RSVD0 0x0F000000 +#define BF_APBH_CTRL0_RSVD0(v) \ + (((v) << 24) & BM_APBH_CTRL0_RSVD0) +#define BP_APBH_CTRL0_RESET_CHANNEL 16 +#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 +#define BF_APBH_CTRL0_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CTRL0_RESET_CHANNEL) +#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1 0x02 +#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2 0x04 +#define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x80 +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FF00 +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ + (((v) << 8) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x02 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x04 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x80 +#define BP_APBH_CTRL0_FREEZE_CHANNEL 0 +#define BM_APBH_CTRL0_FREEZE_CHANNEL 0x000000FF +#define BF_APBH_CTRL0_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CTRL0_FREEZE_CHANNEL) +#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1 0x02 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2 0x04 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x80 + +#define HW_APBH_CTRL1 (0x00000010) +#define HW_APBH_CTRL1_SET (0x00000014) +#define HW_APBH_CTRL1_CLR (0x00000018) +#define HW_APBH_CTRL1_TOG (0x0000001c) + +#define BP_APBH_CTRL1_RSVD1 24 +#define BM_APBH_CTRL1_RSVD1 0xFF000000 +#define BF_APBH_CTRL1_RSVD1(v) \ + (((v) << 24) & BM_APBH_CTRL1_RSVD1) +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BP_APBH_CTRL1_RSVD0 8 +#define BM_APBH_CTRL1_RSVD0 0x0000FF00 +#define BF_APBH_CTRL1_RSVD0(v) \ + (((v) << 8) & BM_APBH_CTRL1_RSVD0) +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBH_CTRL2 (0x00000020) +#define HW_APBH_CTRL2_SET (0x00000024) +#define HW_APBH_CTRL2_CLR (0x00000028) +#define HW_APBH_CTRL2_TOG (0x0000002c) + +#define BP_APBH_CTRL2_RSVD1 24 +#define BM_APBH_CTRL2_RSVD1 0xFF000000 +#define BF_APBH_CTRL2_RSVD1(v) \ + (((v) << 24) & BM_APBH_CTRL2_RSVD1) +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BP_APBH_CTRL2_RSVD0 8 +#define BM_APBH_CTRL2_RSVD0 0x0000FF00 +#define BF_APBH_CTRL2_RSVD0(v) \ + (((v) << 8) & BM_APBH_CTRL2_RSVD0) +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBH_DEVSEL (0x00000030) + +#define BP_APBH_DEVSEL_CH7 28 +#define BM_APBH_DEVSEL_CH7 0xF0000000 +#define BF_APBH_DEVSEL_CH7(v) \ + (((v) << 28) & BM_APBH_DEVSEL_CH7) +#define BP_APBH_DEVSEL_CH6 24 +#define BM_APBH_DEVSEL_CH6 0x0F000000 +#define BF_APBH_DEVSEL_CH6(v) \ + (((v) << 24) & BM_APBH_DEVSEL_CH6) +#define BP_APBH_DEVSEL_CH5 20 +#define BM_APBH_DEVSEL_CH5 0x00F00000 +#define BF_APBH_DEVSEL_CH5(v) \ + (((v) << 20) & BM_APBH_DEVSEL_CH5) +#define BP_APBH_DEVSEL_CH4 16 +#define BM_APBH_DEVSEL_CH4 0x000F0000 +#define BF_APBH_DEVSEL_CH4(v) \ + (((v) << 16) & BM_APBH_DEVSEL_CH4) +#define BP_APBH_DEVSEL_CH3 12 +#define BM_APBH_DEVSEL_CH3 0x0000F000 +#define BF_APBH_DEVSEL_CH3(v) \ + (((v) << 12) & BM_APBH_DEVSEL_CH3) +#define BP_APBH_DEVSEL_CH2 8 +#define BM_APBH_DEVSEL_CH2 0x00000F00 +#define BF_APBH_DEVSEL_CH2(v) \ + (((v) << 8) & BM_APBH_DEVSEL_CH2) +#define BP_APBH_DEVSEL_CH1 4 +#define BM_APBH_DEVSEL_CH1 0x000000F0 +#define BF_APBH_DEVSEL_CH1(v) \ + (((v) << 4) & BM_APBH_DEVSEL_CH1) +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x0000000F +#define BF_APBH_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBH_DEVSEL_CH0) + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000040 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_CURCMDAR(n) (0x00000040 + (n) * 0x70) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000050 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_NXTCMDAR(n) (0x00000050 + (n) * 0x70) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000060 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_CMD(n) (0x00000060 + (n) * 0x70) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBH_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 + +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000070 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_BAR(n) (0x00000070 + (n) * 0x70) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000080 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_SEMA(n) (0x00000080 + (n) * 0x70) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBH_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000090 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG1(n) (0x00000090 + (n) * 0x70) +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x000000A0 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG2(n) (0x000000a0 + (n) * 0x70) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBH_VERSION (0x000003f0) + +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 +#define BF_APBH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBH_VERSION_MAJOR) +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 +#define BF_APBH_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBH_VERSION_MINOR) +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF +#define BF_APBH_VERSION_STEP(v) \ + (((v) << 0) & BM_APBH_VERSION_STEP) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-audioin.h b/arch/arm/mach-mx23/include/mach/regs-audioin.h new file mode 100644 index 000000000000..1a881ce0407e --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-audioin.h @@ -0,0 +1,287 @@ +/* + * Freescale AUDIOIN Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.52 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___AUDIOIN_H +#define __ARCH_ARM___AUDIOIN_H + +#define REGS_AUDIOIN_BASE (IO_ADDRESS(AUDIOIN_PHYS_ADDR)) + +#define HW_AUDIOIN_CTRL (0x00000000) +#define HW_AUDIOIN_CTRL_SET (0x00000004) +#define HW_AUDIOIN_CTRL_CLR (0x00000008) +#define HW_AUDIOIN_CTRL_TOG (0x0000000c) + +#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 +#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 +#define BP_AUDIOIN_CTRL_RSRVD3 21 +#define BM_AUDIOIN_CTRL_RSRVD3 0x3FE00000 +#define BF_AUDIOIN_CTRL_RSRVD3(v) \ + (((v) << 21) & BM_AUDIOIN_CTRL_RSRVD3) +#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 +#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_AUDIOIN_CTRL_DMAWAIT_COUNT) +#define BP_AUDIOIN_CTRL_RSRVD1 11 +#define BM_AUDIOIN_CTRL_RSRVD1 0x0000F800 +#define BF_AUDIOIN_CTRL_RSRVD1(v) \ + (((v) << 11) & BM_AUDIOIN_CTRL_RSRVD1) +#define BM_AUDIOIN_CTRL_LR_SWAP 0x00000400 +#define BM_AUDIOIN_CTRL_EDGE_SYNC 0x00000200 +#define BM_AUDIOIN_CTRL_INVERT_1BIT 0x00000100 +#define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x00000080 +#define BM_AUDIOIN_CTRL_HPF_ENABLE 0x00000040 +#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 +#define BM_AUDIOIN_CTRL_LOOPBACK 0x00000010 +#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_AUDIOIN_CTRL_RUN 0x00000001 + +#define HW_AUDIOIN_STAT (0x00000010) +#define HW_AUDIOIN_STAT_SET (0x00000014) +#define HW_AUDIOIN_STAT_CLR (0x00000018) +#define HW_AUDIOIN_STAT_TOG (0x0000001c) + +#define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 +#define BP_AUDIOIN_STAT_RSRVD3 0 +#define BM_AUDIOIN_STAT_RSRVD3 0x7FFFFFFF +#define BF_AUDIOIN_STAT_RSRVD3(v) \ + (((v) << 0) & BM_AUDIOIN_STAT_RSRVD3) + +#define HW_AUDIOIN_ADCSRR (0x00000020) +#define HW_AUDIOIN_ADCSRR_SET (0x00000024) +#define HW_AUDIOIN_ADCSRR_CLR (0x00000028) +#define HW_AUDIOIN_ADCSRR_TOG (0x0000002c) + +#define BM_AUDIOIN_ADCSRR_OSR 0x80000000 +#define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 +#define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 +#define BP_AUDIOIN_ADCSRR_BASEMULT 28 +#define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 +#define BF_AUDIOIN_ADCSRR_BASEMULT(v) \ + (((v) << 28) & BM_AUDIOIN_ADCSRR_BASEMULT) +#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 +#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 +#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 +#define BM_AUDIOIN_ADCSRR_RSRVD2 0x08000000 +#define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 +#define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x07000000 +#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) \ + (((v) << 24) & BM_AUDIOIN_ADCSRR_SRC_HOLD) +#define BP_AUDIOIN_ADCSRR_RSRVD1 21 +#define BM_AUDIOIN_ADCSRR_RSRVD1 0x00E00000 +#define BF_AUDIOIN_ADCSRR_RSRVD1(v) \ + (((v) << 21) & BM_AUDIOIN_ADCSRR_RSRVD1) +#define BP_AUDIOIN_ADCSRR_SRC_INT 16 +#define BM_AUDIOIN_ADCSRR_SRC_INT 0x001F0000 +#define BF_AUDIOIN_ADCSRR_SRC_INT(v) \ + (((v) << 16) & BM_AUDIOIN_ADCSRR_SRC_INT) +#define BP_AUDIOIN_ADCSRR_RSRVD0 13 +#define BM_AUDIOIN_ADCSRR_RSRVD0 0x0000E000 +#define BF_AUDIOIN_ADCSRR_RSRVD0(v) \ + (((v) << 13) & BM_AUDIOIN_ADCSRR_RSRVD0) +#define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 +#define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x00001FFF +#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) \ + (((v) << 0) & BM_AUDIOIN_ADCSRR_SRC_FRAC) + +#define HW_AUDIOIN_ADCVOLUME (0x00000030) +#define HW_AUDIOIN_ADCVOLUME_SET (0x00000034) +#define HW_AUDIOIN_ADCVOLUME_CLR (0x00000038) +#define HW_AUDIOIN_ADCVOLUME_TOG (0x0000003c) + +#define BP_AUDIOIN_ADCVOLUME_RSRVD5 29 +#define BM_AUDIOIN_ADCVOLUME_RSRVD5 0xE0000000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v) \ + (((v) << 29) & BM_AUDIOIN_ADCVOLUME_RSRVD5) +#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 +#define BP_AUDIOIN_ADCVOLUME_RSRVD4 26 +#define BM_AUDIOIN_ADCVOLUME_RSRVD4 0x0C000000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v) \ + (((v) << 26) & BM_AUDIOIN_ADCVOLUME_RSRVD4) +#define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x02000000 +#define BM_AUDIOIN_ADCVOLUME_RSRVD3 0x01000000 +#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 +#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) \ + (((v) << 16) & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT) +#define BP_AUDIOIN_ADCVOLUME_RSRVD2 13 +#define BM_AUDIOIN_ADCVOLUME_RSRVD2 0x0000E000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v) \ + (((v) << 13) & BM_AUDIOIN_ADCVOLUME_RSRVD2) +#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x00001000 +#define BP_AUDIOIN_ADCVOLUME_RSRVD1 8 +#define BM_AUDIOIN_ADCVOLUME_RSRVD1 0x00000F00 +#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v) \ + (((v) << 8) & BM_AUDIOIN_ADCVOLUME_RSRVD1) +#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF +#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) \ + (((v) << 0) & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT) + +#define HW_AUDIOIN_ADCDEBUG (0x00000040) +#define HW_AUDIOIN_ADCDEBUG_SET (0x00000044) +#define HW_AUDIOIN_ADCDEBUG_CLR (0x00000048) +#define HW_AUDIOIN_ADCDEBUG_TOG (0x0000004c) + +#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 +#define BP_AUDIOIN_ADCDEBUG_RSRVD1 4 +#define BM_AUDIOIN_ADCDEBUG_RSRVD1 0x7FFFFFF0 +#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v) \ + (((v) << 4) & BM_AUDIOIN_ADCDEBUG_RSRVD1) +#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x00000008 +#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x00000004 +#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x00000002 +#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x00000001 + +#define HW_AUDIOIN_ADCVOL (0x00000050) +#define HW_AUDIOIN_ADCVOL_SET (0x00000054) +#define HW_AUDIOIN_ADCVOL_CLR (0x00000058) +#define HW_AUDIOIN_ADCVOL_TOG (0x0000005c) + +#define BP_AUDIOIN_ADCVOL_RSRVD4 29 +#define BM_AUDIOIN_ADCVOL_RSRVD4 0xE0000000 +#define BF_AUDIOIN_ADCVOL_RSRVD4(v) \ + (((v) << 29) & BM_AUDIOIN_ADCVOL_RSRVD4) +#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000 +#define BP_AUDIOIN_ADCVOL_RSRVD3 26 +#define BM_AUDIOIN_ADCVOL_RSRVD3 0x0C000000 +#define BF_AUDIOIN_ADCVOL_RSRVD3(v) \ + (((v) << 26) & BM_AUDIOIN_ADCVOL_RSRVD3) +#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x02000000 +#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 +#define BP_AUDIOIN_ADCVOL_RSRVD2 14 +#define BM_AUDIOIN_ADCVOL_RSRVD2 0x00FFC000 +#define BF_AUDIOIN_ADCVOL_RSRVD2(v) \ + (((v) << 14) & BM_AUDIOIN_ADCVOL_RSRVD2) +#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 +#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 +#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) \ + (((v) << 12) & BM_AUDIOIN_ADCVOL_SELECT_LEFT) +#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 +#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 +#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) \ + (((v) << 8) & BM_AUDIOIN_ADCVOL_GAIN_LEFT) +#define BP_AUDIOIN_ADCVOL_RSRVD1 6 +#define BM_AUDIOIN_ADCVOL_RSRVD1 0x000000C0 +#define BF_AUDIOIN_ADCVOL_RSRVD1(v) \ + (((v) << 6) & BM_AUDIOIN_ADCVOL_RSRVD1) +#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 +#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 +#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) \ + (((v) << 4) & BM_AUDIOIN_ADCVOL_SELECT_RIGHT) +#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 +#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F +#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) \ + (((v) << 0) & BM_AUDIOIN_ADCVOL_GAIN_RIGHT) + +#define HW_AUDIOIN_MICLINE (0x00000060) +#define HW_AUDIOIN_MICLINE_SET (0x00000064) +#define HW_AUDIOIN_MICLINE_CLR (0x00000068) +#define HW_AUDIOIN_MICLINE_TOG (0x0000006c) + +#define BP_AUDIOIN_MICLINE_RSRVD6 30 +#define BM_AUDIOIN_MICLINE_RSRVD6 0xC0000000 +#define BF_AUDIOIN_MICLINE_RSRVD6(v) \ + (((v) << 30) & BM_AUDIOIN_MICLINE_RSRVD6) +#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 +#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 +#define BP_AUDIOIN_MICLINE_RSRVD5 25 +#define BM_AUDIOIN_MICLINE_RSRVD5 0x0E000000 +#define BF_AUDIOIN_MICLINE_RSRVD5(v) \ + (((v) << 25) & BM_AUDIOIN_MICLINE_RSRVD5) +#define BM_AUDIOIN_MICLINE_MIC_SELECT 0x01000000 +#define BP_AUDIOIN_MICLINE_RSRVD4 22 +#define BM_AUDIOIN_MICLINE_RSRVD4 0x00C00000 +#define BF_AUDIOIN_MICLINE_RSRVD4(v) \ + (((v) << 22) & BM_AUDIOIN_MICLINE_RSRVD4) +#define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 +#define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x00300000 +#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) \ + (((v) << 20) & BM_AUDIOIN_MICLINE_MIC_RESISTOR) +#define BM_AUDIOIN_MICLINE_RSRVD3 0x00080000 +#define BP_AUDIOIN_MICLINE_MIC_BIAS 16 +#define BM_AUDIOIN_MICLINE_MIC_BIAS 0x00070000 +#define BF_AUDIOIN_MICLINE_MIC_BIAS(v) \ + (((v) << 16) & BM_AUDIOIN_MICLINE_MIC_BIAS) +#define BP_AUDIOIN_MICLINE_RSRVD2 6 +#define BM_AUDIOIN_MICLINE_RSRVD2 0x0000FFC0 +#define BF_AUDIOIN_MICLINE_RSRVD2(v) \ + (((v) << 6) & BM_AUDIOIN_MICLINE_RSRVD2) +#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4 +#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x00000030 +#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) \ + (((v) << 4) & BM_AUDIOIN_MICLINE_MIC_CHOPCLK) +#define BP_AUDIOIN_MICLINE_RSRVD1 2 +#define BM_AUDIOIN_MICLINE_RSRVD1 0x0000000C +#define BF_AUDIOIN_MICLINE_RSRVD1(v) \ + (((v) << 2) & BM_AUDIOIN_MICLINE_RSRVD1) +#define BP_AUDIOIN_MICLINE_MIC_GAIN 0 +#define BM_AUDIOIN_MICLINE_MIC_GAIN 0x00000003 +#define BF_AUDIOIN_MICLINE_MIC_GAIN(v) \ + (((v) << 0) & BM_AUDIOIN_MICLINE_MIC_GAIN) + +#define HW_AUDIOIN_ANACLKCTRL (0x00000070) +#define HW_AUDIOIN_ANACLKCTRL_SET (0x00000074) +#define HW_AUDIOIN_ANACLKCTRL_CLR (0x00000078) +#define HW_AUDIOIN_ANACLKCTRL_TOG (0x0000007c) + +#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 +#define BP_AUDIOIN_ANACLKCTRL_RSRVD4 11 +#define BM_AUDIOIN_ANACLKCTRL_RSRVD4 0x7FFFF800 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v) \ + (((v) << 11) & BM_AUDIOIN_ANACLKCTRL_RSRVD4) +#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x00000400 +#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x00000200 +#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x00000100 +#define BP_AUDIOIN_ANACLKCTRL_RSRVD3 6 +#define BM_AUDIOIN_ANACLKCTRL_RSRVD3 0x000000C0 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v) \ + (((v) << 6) & BM_AUDIOIN_ANACLKCTRL_RSRVD3) +#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 4 +#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 0x00000030 +#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) \ + (((v) << 4) & BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT) +#define BM_AUDIOIN_ANACLKCTRL_RSRVD2 0x00000008 +#define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 +#define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x00000007 +#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) \ + (((v) << 0) & BM_AUDIOIN_ANACLKCTRL_ADCDIV) + +#define HW_AUDIOIN_DATA (0x00000080) +#define HW_AUDIOIN_DATA_SET (0x00000084) +#define HW_AUDIOIN_DATA_CLR (0x00000088) +#define HW_AUDIOIN_DATA_TOG (0x0000008c) + +#define BP_AUDIOIN_DATA_HIGH 16 +#define BM_AUDIOIN_DATA_HIGH 0xFFFF0000 +#define BF_AUDIOIN_DATA_HIGH(v) \ + (((v) << 16) & BM_AUDIOIN_DATA_HIGH) +#define BP_AUDIOIN_DATA_LOW 0 +#define BM_AUDIOIN_DATA_LOW 0x0000FFFF +#define BF_AUDIOIN_DATA_LOW(v) \ + (((v) << 0) & BM_AUDIOIN_DATA_LOW) +#endif /* __ARCH_ARM___AUDIOIN_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-audioout.h b/arch/arm/mach-mx23/include/mach/regs-audioout.h new file mode 100644 index 000000000000..d751858a1327 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-audioout.h @@ -0,0 +1,518 @@ +/* + * Freescale AUDIOOUT Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.65 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___AUDIOOUT_H +#define __ARCH_ARM___AUDIOOUT_H + +#define REGS_AUDIOOUT_BASE (IO_ADDRESS(AUDIOOUT_PHYS_ADDR)) + +#define HW_AUDIOOUT_CTRL (0x00000000) +#define HW_AUDIOOUT_CTRL_SET (0x00000004) +#define HW_AUDIOOUT_CTRL_CLR (0x00000008) +#define HW_AUDIOOUT_CTRL_TOG (0x0000000c) + +#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 +#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 +#define BP_AUDIOOUT_CTRL_RSRVD4 21 +#define BM_AUDIOOUT_CTRL_RSRVD4 0x3FE00000 +#define BF_AUDIOOUT_CTRL_RSRVD4(v) \ + (((v) << 21) & BM_AUDIOOUT_CTRL_RSRVD4) +#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 +#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_AUDIOOUT_CTRL_DMAWAIT_COUNT) +#define BM_AUDIOOUT_CTRL_RSRVD3 0x00008000 +#define BM_AUDIOOUT_CTRL_LR_SWAP 0x00004000 +#define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x00002000 +#define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x00001000 +#define BP_AUDIOOUT_CTRL_RSRVD2 10 +#define BM_AUDIOOUT_CTRL_RSRVD2 0x00000C00 +#define BF_AUDIOOUT_CTRL_RSRVD2(v) \ + (((v) << 10) & BM_AUDIOOUT_CTRL_RSRVD2) +#define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 +#define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x00000300 +#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) \ + (((v) << 8) & BM_AUDIOOUT_CTRL_SS3D_EFFECT) +#define BM_AUDIOOUT_CTRL_RSRVD1 0x00000080 +#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 +#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x00000020 +#define BM_AUDIOOUT_CTRL_LOOPBACK 0x00000010 +#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_AUDIOOUT_CTRL_RUN 0x00000001 + +#define HW_AUDIOOUT_STAT (0x00000010) +#define HW_AUDIOOUT_STAT_SET (0x00000014) +#define HW_AUDIOOUT_STAT_CLR (0x00000018) +#define HW_AUDIOOUT_STAT_TOG (0x0000001c) + +#define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 +#define BP_AUDIOOUT_STAT_RSRVD1 0 +#define BM_AUDIOOUT_STAT_RSRVD1 0x7FFFFFFF +#define BF_AUDIOOUT_STAT_RSRVD1(v) \ + (((v) << 0) & BM_AUDIOOUT_STAT_RSRVD1) + +#define HW_AUDIOOUT_DACSRR (0x00000020) +#define HW_AUDIOOUT_DACSRR_SET (0x00000024) +#define HW_AUDIOOUT_DACSRR_CLR (0x00000028) +#define HW_AUDIOOUT_DACSRR_TOG (0x0000002c) + +#define BM_AUDIOOUT_DACSRR_OSR 0x80000000 +#define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 +#define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 +#define BP_AUDIOOUT_DACSRR_BASEMULT 28 +#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 +#define BF_AUDIOOUT_DACSRR_BASEMULT(v) \ + (((v) << 28) & BM_AUDIOOUT_DACSRR_BASEMULT) +#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 +#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 +#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 +#define BM_AUDIOOUT_DACSRR_RSRVD2 0x08000000 +#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 +#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 +#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) \ + (((v) << 24) & BM_AUDIOOUT_DACSRR_SRC_HOLD) +#define BP_AUDIOOUT_DACSRR_RSRVD1 21 +#define BM_AUDIOOUT_DACSRR_RSRVD1 0x00E00000 +#define BF_AUDIOOUT_DACSRR_RSRVD1(v) \ + (((v) << 21) & BM_AUDIOOUT_DACSRR_RSRVD1) +#define BP_AUDIOOUT_DACSRR_SRC_INT 16 +#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 +#define BF_AUDIOOUT_DACSRR_SRC_INT(v) \ + (((v) << 16) & BM_AUDIOOUT_DACSRR_SRC_INT) +#define BP_AUDIOOUT_DACSRR_RSRVD0 13 +#define BM_AUDIOOUT_DACSRR_RSRVD0 0x0000E000 +#define BF_AUDIOOUT_DACSRR_RSRVD0(v) \ + (((v) << 13) & BM_AUDIOOUT_DACSRR_RSRVD0) +#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 +#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF +#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) \ + (((v) << 0) & BM_AUDIOOUT_DACSRR_SRC_FRAC) + +#define HW_AUDIOOUT_DACVOLUME (0x00000030) +#define HW_AUDIOOUT_DACVOLUME_SET (0x00000034) +#define HW_AUDIOOUT_DACVOLUME_CLR (0x00000038) +#define HW_AUDIOOUT_DACVOLUME_TOG (0x0000003c) + +#define BP_AUDIOOUT_DACVOLUME_RSRVD4 29 +#define BM_AUDIOOUT_DACVOLUME_RSRVD4 0xE0000000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v) \ + (((v) << 29) & BM_AUDIOOUT_DACVOLUME_RSRVD4) +#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 +#define BP_AUDIOOUT_DACVOLUME_RSRVD3 26 +#define BM_AUDIOOUT_DACVOLUME_RSRVD3 0x0C000000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v) \ + (((v) << 26) & BM_AUDIOOUT_DACVOLUME_RSRVD3) +#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 +#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 +#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 +#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0x00FF0000 +#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) \ + (((v) << 16) & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) +#define BP_AUDIOOUT_DACVOLUME_RSRVD2 13 +#define BM_AUDIOOUT_DACVOLUME_RSRVD2 0x0000E000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v) \ + (((v) << 13) & BM_AUDIOOUT_DACVOLUME_RSRVD2) +#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x00001000 +#define BP_AUDIOOUT_DACVOLUME_RSRVD1 9 +#define BM_AUDIOOUT_DACVOLUME_RSRVD1 0x00000E00 +#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v) \ + (((v) << 9) & BM_AUDIOOUT_DACVOLUME_RSRVD1) +#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 +#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 +#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0x000000FF +#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) \ + (((v) << 0) & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) + +#define HW_AUDIOOUT_DACDEBUG (0x00000040) +#define HW_AUDIOOUT_DACDEBUG_SET (0x00000044) +#define HW_AUDIOOUT_DACDEBUG_CLR (0x00000048) +#define HW_AUDIOOUT_DACDEBUG_TOG (0x0000004c) + +#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 +#define BP_AUDIOOUT_DACDEBUG_RSRVD2 12 +#define BM_AUDIOOUT_DACDEBUG_RSRVD2 0x7FFFF000 +#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v) \ + (((v) << 12) & BM_AUDIOOUT_DACDEBUG_RSRVD2) +#define BP_AUDIOOUT_DACDEBUG_RAM_SS 8 +#define BM_AUDIOOUT_DACDEBUG_RAM_SS 0x00000F00 +#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) \ + (((v) << 8) & BM_AUDIOOUT_DACDEBUG_RAM_SS) +#define BP_AUDIOOUT_DACDEBUG_RSRVD1 6 +#define BM_AUDIOOUT_DACDEBUG_RSRVD1 0x000000C0 +#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v) \ + (((v) << 6) & BM_AUDIOOUT_DACDEBUG_RSRVD1) +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x00000020 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x00000010 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x00000008 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x00000004 +#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x00000002 +#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x00000001 + +#define HW_AUDIOOUT_HPVOL (0x00000050) +#define HW_AUDIOOUT_HPVOL_SET (0x00000054) +#define HW_AUDIOOUT_HPVOL_CLR (0x00000058) +#define HW_AUDIOOUT_HPVOL_TOG (0x0000005c) + +#define BP_AUDIOOUT_HPVOL_RSRVD5 29 +#define BM_AUDIOOUT_HPVOL_RSRVD5 0xE0000000 +#define BF_AUDIOOUT_HPVOL_RSRVD5(v) \ + (((v) << 29) & BM_AUDIOOUT_HPVOL_RSRVD5) +#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000 +#define BP_AUDIOOUT_HPVOL_RSRVD4 26 +#define BM_AUDIOOUT_HPVOL_RSRVD4 0x0C000000 +#define BF_AUDIOOUT_HPVOL_RSRVD4(v) \ + (((v) << 26) & BM_AUDIOOUT_HPVOL_RSRVD4) +#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 +#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 +#define BP_AUDIOOUT_HPVOL_RSRVD3 17 +#define BM_AUDIOOUT_HPVOL_RSRVD3 0x00FE0000 +#define BF_AUDIOOUT_HPVOL_RSRVD3(v) \ + (((v) << 17) & BM_AUDIOOUT_HPVOL_RSRVD3) +#define BM_AUDIOOUT_HPVOL_SELECT 0x00010000 +#define BM_AUDIOOUT_HPVOL_RSRVD2 0x00008000 +#define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 +#define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x00007F00 +#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) \ + (((v) << 8) & BM_AUDIOOUT_HPVOL_VOL_LEFT) +#define BM_AUDIOOUT_HPVOL_RSRVD1 0x00000080 +#define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 +#define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x0000007F +#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) \ + (((v) << 0) & BM_AUDIOOUT_HPVOL_VOL_RIGHT) + +#define HW_AUDIOOUT_RESERVED (0x00000060) +#define HW_AUDIOOUT_RESERVED_SET (0x00000064) +#define HW_AUDIOOUT_RESERVED_CLR (0x00000068) +#define HW_AUDIOOUT_RESERVED_TOG (0x0000006c) + +#define BP_AUDIOOUT_RESERVED_RSRVD1 0 +#define BM_AUDIOOUT_RESERVED_RSRVD1 0xFFFFFFFF +#define BF_AUDIOOUT_RESERVED_RSRVD1(v) (v) + +#define HW_AUDIOOUT_PWRDN (0x00000070) +#define HW_AUDIOOUT_PWRDN_SET (0x00000074) +#define HW_AUDIOOUT_PWRDN_CLR (0x00000078) +#define HW_AUDIOOUT_PWRDN_TOG (0x0000007c) + +#define BP_AUDIOOUT_PWRDN_RSRVD7 25 +#define BM_AUDIOOUT_PWRDN_RSRVD7 0xFE000000 +#define BF_AUDIOOUT_PWRDN_RSRVD7(v) \ + (((v) << 25) & BM_AUDIOOUT_PWRDN_RSRVD7) +#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000 +#define BP_AUDIOOUT_PWRDN_RSRVD6 21 +#define BM_AUDIOOUT_PWRDN_RSRVD6 0x00E00000 +#define BF_AUDIOOUT_PWRDN_RSRVD6(v) \ + (((v) << 21) & BM_AUDIOOUT_PWRDN_RSRVD6) +#define BM_AUDIOOUT_PWRDN_SELFBIAS 0x00100000 +#define BP_AUDIOOUT_PWRDN_RSRVD5 17 +#define BM_AUDIOOUT_PWRDN_RSRVD5 0x000E0000 +#define BF_AUDIOOUT_PWRDN_RSRVD5(v) \ + (((v) << 17) & BM_AUDIOOUT_PWRDN_RSRVD5) +#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 +#define BP_AUDIOOUT_PWRDN_RSRVD4 13 +#define BM_AUDIOOUT_PWRDN_RSRVD4 0x0000E000 +#define BF_AUDIOOUT_PWRDN_RSRVD4(v) \ + (((v) << 13) & BM_AUDIOOUT_PWRDN_RSRVD4) +#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 +#define BP_AUDIOOUT_PWRDN_RSRVD3 9 +#define BM_AUDIOOUT_PWRDN_RSRVD3 0x00000E00 +#define BF_AUDIOOUT_PWRDN_RSRVD3(v) \ + (((v) << 9) & BM_AUDIOOUT_PWRDN_RSRVD3) +#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 +#define BP_AUDIOOUT_PWRDN_RSRVD2 5 +#define BM_AUDIOOUT_PWRDN_RSRVD2 0x000000E0 +#define BF_AUDIOOUT_PWRDN_RSRVD2(v) \ + (((v) << 5) & BM_AUDIOOUT_PWRDN_RSRVD2) +#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 +#define BP_AUDIOOUT_PWRDN_RSRVD1 1 +#define BM_AUDIOOUT_PWRDN_RSRVD1 0x0000000E +#define BF_AUDIOOUT_PWRDN_RSRVD1(v) \ + (((v) << 1) & BM_AUDIOOUT_PWRDN_RSRVD1) +#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 + +#define HW_AUDIOOUT_REFCTRL (0x00000080) +#define HW_AUDIOOUT_REFCTRL_SET (0x00000084) +#define HW_AUDIOOUT_REFCTRL_CLR (0x00000088) +#define HW_AUDIOOUT_REFCTRL_TOG (0x0000008c) + +#define BP_AUDIOOUT_REFCTRL_RSRVD4 27 +#define BM_AUDIOOUT_REFCTRL_RSRVD4 0xF8000000 +#define BF_AUDIOOUT_REFCTRL_RSRVD4(v) \ + (((v) << 27) & BM_AUDIOOUT_REFCTRL_RSRVD4) +#define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x04000000 +#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 +#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 +#define BM_AUDIOOUT_REFCTRL_RSRVD3 0x00800000 +#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 +#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 +#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) \ + (((v) << 20) & BM_AUDIOOUT_REFCTRL_VBG_ADJ) +#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 +#define BM_AUDIOOUT_REFCTRL_LW_REF 0x00040000 +#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 +#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 +#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) \ + (((v) << 16) & BM_AUDIOOUT_REFCTRL_BIAS_CTRL) +#define BM_AUDIOOUT_REFCTRL_RSRVD2 0x00008000 +#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x00004000 +#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 +#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 +#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 +#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 +#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) \ + (((v) << 8) & BM_AUDIOOUT_REFCTRL_ADC_REFVAL) +#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 +#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 +#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) \ + (((v) << 4) & BM_AUDIOOUT_REFCTRL_VAG_VAL) +#define BM_AUDIOOUT_REFCTRL_RSRVD1 0x00000008 +#define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 +#define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x00000007 +#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) \ + (((v) << 0) & BM_AUDIOOUT_REFCTRL_DAC_ADJ) + +#define HW_AUDIOOUT_ANACTRL (0x00000090) +#define HW_AUDIOOUT_ANACTRL_SET (0x00000094) +#define HW_AUDIOOUT_ANACTRL_CLR (0x00000098) +#define HW_AUDIOOUT_ANACTRL_TOG (0x0000009c) + +#define BP_AUDIOOUT_ANACTRL_RSRVD8 29 +#define BM_AUDIOOUT_ANACTRL_RSRVD8 0xE0000000 +#define BF_AUDIOOUT_ANACTRL_RSRVD8(v) \ + (((v) << 29) & BM_AUDIOOUT_ANACTRL_RSRVD8) +#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 +#define BP_AUDIOOUT_ANACTRL_RSRVD7 25 +#define BM_AUDIOOUT_ANACTRL_RSRVD7 0x0E000000 +#define BF_AUDIOOUT_ANACTRL_RSRVD7(v) \ + (((v) << 25) & BM_AUDIOOUT_ANACTRL_RSRVD7) +#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x01000000 +#define BP_AUDIOOUT_ANACTRL_RSRVD6 22 +#define BM_AUDIOOUT_ANACTRL_RSRVD6 0x00C00000 +#define BF_AUDIOOUT_ANACTRL_RSRVD6(v) \ + (((v) << 22) & BM_AUDIOOUT_ANACTRL_RSRVD6) +#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 +#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x00300000 +#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) \ + (((v) << 20) & BM_AUDIOOUT_ANACTRL_SHORTMODE_CM) +#define BM_AUDIOOUT_ANACTRL_RSRVD5 0x00080000 +#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 +#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x00060000 +#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) \ + (((v) << 17) & BM_AUDIOOUT_ANACTRL_SHORTMODE_LR) +#define BP_AUDIOOUT_ANACTRL_RSRVD4 15 +#define BM_AUDIOOUT_ANACTRL_RSRVD4 0x00018000 +#define BF_AUDIOOUT_ANACTRL_RSRVD4(v) \ + (((v) << 15) & BM_AUDIOOUT_ANACTRL_RSRVD4) +#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 +#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x00007000 +#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) \ + (((v) << 12) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL) +#define BM_AUDIOOUT_ANACTRL_RSRVD3 0x00000800 +#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 +#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x00000700 +#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) \ + (((v) << 8) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR) +#define BP_AUDIOOUT_ANACTRL_RSRVD2 6 +#define BM_AUDIOOUT_ANACTRL_RSRVD2 0x000000C0 +#define BF_AUDIOOUT_ANACTRL_RSRVD2(v) \ + (((v) << 6) & BM_AUDIOOUT_ANACTRL_RSRVD2) +#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 +#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 +#define BP_AUDIOOUT_ANACTRL_RSRVD1 0 +#define BM_AUDIOOUT_ANACTRL_RSRVD1 0x0000000F +#define BF_AUDIOOUT_ANACTRL_RSRVD1(v) \ + (((v) << 0) & BM_AUDIOOUT_ANACTRL_RSRVD1) + +#define HW_AUDIOOUT_TEST (0x000000a0) +#define HW_AUDIOOUT_TEST_SET (0x000000a4) +#define HW_AUDIOOUT_TEST_CLR (0x000000a8) +#define HW_AUDIOOUT_TEST_TOG (0x000000ac) + +#define BM_AUDIOOUT_TEST_RSRVD4 0x80000000 +#define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 +#define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 +#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) \ + (((v) << 28) & BM_AUDIOOUT_TEST_HP_ANTIPOP) +#define BM_AUDIOOUT_TEST_RSRVD3 0x08000000 +#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x04000000 +#define BM_AUDIOOUT_TEST_TM_LOOP 0x02000000 +#define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x01000000 +#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 +#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 +#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) \ + (((v) << 22) & BM_AUDIOOUT_TEST_HP_I1_ADJ) +#define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 +#define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x00300000 +#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) \ + (((v) << 20) & BM_AUDIOOUT_TEST_HP_IALL_ADJ) +#define BP_AUDIOOUT_TEST_RSRVD2 14 +#define BM_AUDIOOUT_TEST_RSRVD2 0x000FC000 +#define BF_AUDIOOUT_TEST_RSRVD2(v) \ + (((v) << 14) & BM_AUDIOOUT_TEST_RSRVD2) +#define BM_AUDIOOUT_TEST_VAG_CLASSA 0x00002000 +#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x00001000 +#define BP_AUDIOOUT_TEST_RSRVD1 4 +#define BM_AUDIOOUT_TEST_RSRVD1 0x00000FF0 +#define BF_AUDIOOUT_TEST_RSRVD1(v) \ + (((v) << 4) & BM_AUDIOOUT_TEST_RSRVD1) +#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP 0x00000008 +#define BM_AUDIOOUT_TEST_DAC_CLASSA 0x00000004 +#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x00000002 +#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x00000001 + +#define HW_AUDIOOUT_BISTCTRL (0x000000b0) +#define HW_AUDIOOUT_BISTCTRL_SET (0x000000b4) +#define HW_AUDIOOUT_BISTCTRL_CLR (0x000000b8) +#define HW_AUDIOOUT_BISTCTRL_TOG (0x000000bc) + +#define BP_AUDIOOUT_BISTCTRL_RSVD0 4 +#define BM_AUDIOOUT_BISTCTRL_RSVD0 0xFFFFFFF0 +#define BF_AUDIOOUT_BISTCTRL_RSVD0(v) \ + (((v) << 4) & BM_AUDIOOUT_BISTCTRL_RSVD0) +#define BM_AUDIOOUT_BISTCTRL_FAIL 0x00000008 +#define BM_AUDIOOUT_BISTCTRL_PASS 0x00000004 +#define BM_AUDIOOUT_BISTCTRL_DONE 0x00000002 +#define BM_AUDIOOUT_BISTCTRL_START 0x00000001 + +#define HW_AUDIOOUT_BISTSTAT0 (0x000000c0) +#define HW_AUDIOOUT_BISTSTAT0_SET (0x000000c4) +#define HW_AUDIOOUT_BISTSTAT0_CLR (0x000000c8) +#define HW_AUDIOOUT_BISTSTAT0_TOG (0x000000cc) + +#define BP_AUDIOOUT_BISTSTAT0_RSVD0 24 +#define BM_AUDIOOUT_BISTSTAT0_RSVD0 0xFF000000 +#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v) \ + (((v) << 24) & BM_AUDIOOUT_BISTSTAT0_RSVD0) +#define BP_AUDIOOUT_BISTSTAT0_DATA 0 +#define BM_AUDIOOUT_BISTSTAT0_DATA 0x00FFFFFF +#define BF_AUDIOOUT_BISTSTAT0_DATA(v) \ + (((v) << 0) & BM_AUDIOOUT_BISTSTAT0_DATA) + +#define HW_AUDIOOUT_BISTSTAT1 (0x000000d0) +#define HW_AUDIOOUT_BISTSTAT1_SET (0x000000d4) +#define HW_AUDIOOUT_BISTSTAT1_CLR (0x000000d8) +#define HW_AUDIOOUT_BISTSTAT1_TOG (0x000000dc) + +#define BP_AUDIOOUT_BISTSTAT1_RSVD1 29 +#define BM_AUDIOOUT_BISTSTAT1_RSVD1 0xE0000000 +#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v) \ + (((v) << 29) & BM_AUDIOOUT_BISTSTAT1_RSVD1) +#define BP_AUDIOOUT_BISTSTAT1_STATE 24 +#define BM_AUDIOOUT_BISTSTAT1_STATE 0x1F000000 +#define BF_AUDIOOUT_BISTSTAT1_STATE(v) \ + (((v) << 24) & BM_AUDIOOUT_BISTSTAT1_STATE) +#define BP_AUDIOOUT_BISTSTAT1_RSVD0 8 +#define BM_AUDIOOUT_BISTSTAT1_RSVD0 0x00FFFF00 +#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v) \ + (((v) << 8) & BM_AUDIOOUT_BISTSTAT1_RSVD0) +#define BP_AUDIOOUT_BISTSTAT1_ADDR 0 +#define BM_AUDIOOUT_BISTSTAT1_ADDR 0x000000FF +#define BF_AUDIOOUT_BISTSTAT1_ADDR(v) \ + (((v) << 0) & BM_AUDIOOUT_BISTSTAT1_ADDR) + +#define HW_AUDIOOUT_ANACLKCTRL (0x000000e0) +#define HW_AUDIOOUT_ANACLKCTRL_SET (0x000000e4) +#define HW_AUDIOOUT_ANACLKCTRL_CLR (0x000000e8) +#define HW_AUDIOOUT_ANACLKCTRL_TOG (0x000000ec) + +#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 +#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3 5 +#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3 0x7FFFFFE0 +#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v) \ + (((v) << 5) & BM_AUDIOOUT_ANACLKCTRL_RSRVD3) +#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x00000010 +#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2 0x00000008 +#define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 +#define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x00000007 +#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) \ + (((v) << 0) & BM_AUDIOOUT_ANACLKCTRL_DACDIV) + +#define HW_AUDIOOUT_DATA (0x000000f0) +#define HW_AUDIOOUT_DATA_SET (0x000000f4) +#define HW_AUDIOOUT_DATA_CLR (0x000000f8) +#define HW_AUDIOOUT_DATA_TOG (0x000000fc) + +#define BP_AUDIOOUT_DATA_HIGH 16 +#define BM_AUDIOOUT_DATA_HIGH 0xFFFF0000 +#define BF_AUDIOOUT_DATA_HIGH(v) \ + (((v) << 16) & BM_AUDIOOUT_DATA_HIGH) +#define BP_AUDIOOUT_DATA_LOW 0 +#define BM_AUDIOOUT_DATA_LOW 0x0000FFFF +#define BF_AUDIOOUT_DATA_LOW(v) \ + (((v) << 0) & BM_AUDIOOUT_DATA_LOW) + +#define HW_AUDIOOUT_SPEAKERCTRL (0x00000100) +#define HW_AUDIOOUT_SPEAKERCTRL_SET (0x00000104) +#define HW_AUDIOOUT_SPEAKERCTRL_CLR (0x00000108) +#define HW_AUDIOOUT_SPEAKERCTRL_TOG (0x0000010c) + +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2 25 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 0xFE000000 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) \ + (((v) << 25) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD2) +#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000 +#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ 22 +#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ 0x00C00000 +#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) \ + (((v) << 22) & BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ) +#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 20 +#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 0x00300000 +#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) \ + (((v) << 20) & BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ) +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1 16 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 0x000F0000 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) \ + (((v) << 16) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD1) +#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER 14 +#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER 0x0000C000 +#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) \ + (((v) << 14) & BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER) +#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 12 +#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 0x00003000 +#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) \ + (((v) << 12) & BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER) +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0 0 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 0x00000FFF +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) \ + (((v) << 0) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD0) + +#define HW_AUDIOOUT_VERSION (0x00000200) + +#define BP_AUDIOOUT_VERSION_MAJOR 24 +#define BM_AUDIOOUT_VERSION_MAJOR 0xFF000000 +#define BF_AUDIOOUT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_AUDIOOUT_VERSION_MAJOR) +#define BP_AUDIOOUT_VERSION_MINOR 16 +#define BM_AUDIOOUT_VERSION_MINOR 0x00FF0000 +#define BF_AUDIOOUT_VERSION_MINOR(v) \ + (((v) << 16) & BM_AUDIOOUT_VERSION_MINOR) +#define BP_AUDIOOUT_VERSION_STEP 0 +#define BM_AUDIOOUT_VERSION_STEP 0x0000FFFF +#define BF_AUDIOOUT_VERSION_STEP(v) \ + (((v) << 0) & BM_AUDIOOUT_VERSION_STEP) +#endif /* __ARCH_ARM___AUDIOOUT_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-emi.h b/arch/arm/mach-mx23/include/mach/regs-emi.h new file mode 100644 index 000000000000..bf3adff446e6 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-emi.h @@ -0,0 +1,234 @@ +/* + * Freescale EMI Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + */ + +#ifndef __ARCH_ARM___EMI_H +#define __ARCH_ARM___EMI_H 1 + +#define REGS_EMI_PHYS (0x80020000) +#define REGS_EMI_SIZE 0x00002000 + +#define HW_EMI_CTRL (0x00000000) +#define HW_EMI_CTRL_SET (0x00000004) +#define HW_EMI_CTRL_CLR (0x00000008) +#define HW_EMI_CTRL_TOG (0x0000000c) + +#define BM_EMI_CTRL_SFTRST 0x80000000 +#define BM_EMI_CTRL_CLKGATE 0x40000000 +#define BM_EMI_CTRL_TRAP_SR 0x20000000 +#define BM_EMI_CTRL_TRAP_INIT 0x10000000 +#define BP_EMI_CTRL_AXI_DEPTH 26 +#define BM_EMI_CTRL_AXI_DEPTH 0x0C000000 +#define BF_EMI_CTRL_AXI_DEPTH(v) \ + (((v) << 26) & BM_EMI_CTRL_AXI_DEPTH) +#define BV_EMI_CTRL_AXI_DEPTH__ONE 0x0 +#define BV_EMI_CTRL_AXI_DEPTH__TWO 0x1 +#define BV_EMI_CTRL_AXI_DEPTH__THREE 0x2 +#define BV_EMI_CTRL_AXI_DEPTH__FOUR 0x3 +#define BM_EMI_CTRL_DLL_SHIFT_RESET 0x02000000 +#define BM_EMI_CTRL_DLL_RESET 0x01000000 +#define BP_EMI_CTRL_ARB_MODE 22 +#define BM_EMI_CTRL_ARB_MODE 0x00C00000 +#define BF_EMI_CTRL_ARB_MODE(v) \ + (((v) << 22) & BM_EMI_CTRL_ARB_MODE) +#define BV_EMI_CTRL_ARB_MODE__TIMESTAMP 0x0 +#define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID 0x1 +#define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY 0x2 +#define BM_EMI_CTRL_RSVD3 0x00200000 +#define BP_EMI_CTRL_PORT_PRIORITY_ORDER 16 +#define BM_EMI_CTRL_PORT_PRIORITY_ORDER 0x001F0000 +#define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v) \ + (((v) << 16) & BM_EMI_CTRL_PORT_PRIORITY_ORDER) +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123 0x00 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312 0x01 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231 0x02 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321 0x03 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213 0x04 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132 0x05 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023 0x06 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302 0x07 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230 0x08 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320 0x09 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203 0x0A +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032 0x0B +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013 0x0C +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301 0x0D +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130 0x0E +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310 0x0F +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103 0x10 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031 0x11 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012 0x12 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201 0x13 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120 0x14 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210 0x15 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102 0x16 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021 0x17 +#define BM_EMI_CTRL_RSVD2 0x00008000 +#define BP_EMI_CTRL_PRIORITY_WRITE_ITER 12 +#define BM_EMI_CTRL_PRIORITY_WRITE_ITER 0x00007000 +#define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v) \ + (((v) << 12) & BM_EMI_CTRL_PRIORITY_WRITE_ITER) +#define BM_EMI_CTRL_RSVD1 0x00000800 +#define BP_EMI_CTRL_HIGH_PRIORITY_WRITE 8 +#define BM_EMI_CTRL_HIGH_PRIORITY_WRITE 0x00000700 +#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v) \ + (((v) << 8) & BM_EMI_CTRL_HIGH_PRIORITY_WRITE) +#define BM_EMI_CTRL_RSVD0 0x00000080 +#define BM_EMI_CTRL_MEM_WIDTH 0x00000040 +#define BM_EMI_CTRL_WRITE_PROTECT 0x00000020 +#define BM_EMI_CTRL_RESET_OUT 0x00000010 +#define BP_EMI_CTRL_CE_SELECT 0 +#define BM_EMI_CTRL_CE_SELECT 0x0000000F +#define BF_EMI_CTRL_CE_SELECT(v) \ + (((v) << 0) & BM_EMI_CTRL_CE_SELECT) +#define BV_EMI_CTRL_CE_SELECT__NONE 0x0 +#define BV_EMI_CTRL_CE_SELECT__CE0 0x1 +#define BV_EMI_CTRL_CE_SELECT__CE1 0x2 +#define BV_EMI_CTRL_CE_SELECT__CE2 0x4 +#define BV_EMI_CTRL_CE_SELECT__CE3 0x8 + +#define HW_EMI_STAT (0x00000010) + +#define BM_EMI_STAT_DRAM_PRESENT 0x80000000 +#define BM_EMI_STAT_NOR_PRESENT 0x40000000 +#define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000 +#define BP_EMI_STAT_RSVD0 2 +#define BM_EMI_STAT_RSVD0 0x1FFFFFFC +#define BF_EMI_STAT_RSVD0(v) \ + (((v) << 2) & BM_EMI_STAT_RSVD0) +#define BM_EMI_STAT_DRAM_HALTED 0x00000002 +#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0 +#define BV_EMI_STAT_DRAM_HALTED__HALTED 0x1 +#define BM_EMI_STAT_NOR_BUSY 0x00000001 +#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0 +#define BV_EMI_STAT_NOR_BUSY__BUSY 0x1 + +#define HW_EMI_TIME (0x00000020) +#define HW_EMI_TIME_SET (0x00000024) +#define HW_EMI_TIME_CLR (0x00000028) +#define HW_EMI_TIME_TOG (0x0000002c) + +#define BP_EMI_TIME_RSVD4 28 +#define BM_EMI_TIME_RSVD4 0xF0000000 +#define BF_EMI_TIME_RSVD4(v) \ + (((v) << 28) & BM_EMI_TIME_RSVD4) +#define BP_EMI_TIME_THZ 24 +#define BM_EMI_TIME_THZ 0x0F000000 +#define BF_EMI_TIME_THZ(v) \ + (((v) << 24) & BM_EMI_TIME_THZ) +#define BP_EMI_TIME_RSVD2 20 +#define BM_EMI_TIME_RSVD2 0x00F00000 +#define BF_EMI_TIME_RSVD2(v) \ + (((v) << 20) & BM_EMI_TIME_RSVD2) +#define BP_EMI_TIME_TDH 16 +#define BM_EMI_TIME_TDH 0x000F0000 +#define BF_EMI_TIME_TDH(v) \ + (((v) << 16) & BM_EMI_TIME_TDH) +#define BP_EMI_TIME_RSVD1 13 +#define BM_EMI_TIME_RSVD1 0x0000E000 +#define BF_EMI_TIME_RSVD1(v) \ + (((v) << 13) & BM_EMI_TIME_RSVD1) +#define BP_EMI_TIME_TDS 8 +#define BM_EMI_TIME_TDS 0x00001F00 +#define BF_EMI_TIME_TDS(v) \ + (((v) << 8) & BM_EMI_TIME_TDS) +#define BP_EMI_TIME_RSVD0 4 +#define BM_EMI_TIME_RSVD0 0x000000F0 +#define BF_EMI_TIME_RSVD0(v) \ + (((v) << 4) & BM_EMI_TIME_RSVD0) +#define BP_EMI_TIME_TAS 0 +#define BM_EMI_TIME_TAS 0x0000000F +#define BF_EMI_TIME_TAS(v) \ + (((v) << 0) & BM_EMI_TIME_TAS) + +#define HW_EMI_DDR_TEST_MODE_CSR (0x00000030) +#define HW_EMI_DDR_TEST_MODE_CSR_SET (0x00000034) +#define HW_EMI_DDR_TEST_MODE_CSR_CLR (0x00000038) +#define HW_EMI_DDR_TEST_MODE_CSR_TOG (0x0000003c) + +#define BP_EMI_DDR_TEST_MODE_CSR_RSVD1 2 +#define BM_EMI_DDR_TEST_MODE_CSR_RSVD1 0xFFFFFFFC +#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v) \ + (((v) << 2) & BM_EMI_DDR_TEST_MODE_CSR_RSVD1) +#define BM_EMI_DDR_TEST_MODE_CSR_DONE 0x00000002 +#define BM_EMI_DDR_TEST_MODE_CSR_START 0x00000001 + +#define HW_EMI_DEBUG (0x00000080) + +#define BP_EMI_DEBUG_RSVD1 4 +#define BM_EMI_DEBUG_RSVD1 0xFFFFFFF0 +#define BF_EMI_DEBUG_RSVD1(v) \ + (((v) << 4) & BM_EMI_DEBUG_RSVD1) +#define BP_EMI_DEBUG_NOR_STATE 0 +#define BM_EMI_DEBUG_NOR_STATE 0x0000000F +#define BF_EMI_DEBUG_NOR_STATE(v) \ + (((v) << 0) & BM_EMI_DEBUG_NOR_STATE) + +#define HW_EMI_DDR_TEST_MODE_STATUS0 (0x00000090) + +#define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1 13 +#define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1 0xFFFFE000 +#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v) \ + (((v) << 13) & BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1) +#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0 +#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0x00001FFF +#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) \ + (((v) << 0) & BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0) + +#define HW_EMI_DDR_TEST_MODE_STATUS1 (0x000000a0) + +#define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1 13 +#define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1 0xFFFFE000 +#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v) \ + (((v) << 13) & BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1) +#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0 +#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0x00001FFF +#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) \ + (((v) << 0) & BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1) + +#define HW_EMI_DDR_TEST_MODE_STATUS2 (0x000000b0) + +#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0 0 +#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0 0xFFFFFFFF +#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) (v) + +#define HW_EMI_DDR_TEST_MODE_STATUS3 (0x000000c0) + +#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1 0 +#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1 0xFFFFFFFF +#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) (v) + +#define HW_EMI_VERSION (0x000000f0) + +#define BP_EMI_VERSION_MAJOR 24 +#define BM_EMI_VERSION_MAJOR 0xFF000000 +#define BF_EMI_VERSION_MAJOR(v) \ + (((v) << 24) & BM_EMI_VERSION_MAJOR) +#define BP_EMI_VERSION_MINOR 16 +#define BM_EMI_VERSION_MINOR 0x00FF0000 +#define BF_EMI_VERSION_MINOR(v) \ + (((v) << 16) & BM_EMI_VERSION_MINOR) +#define BP_EMI_VERSION_STEP 0 +#define BM_EMI_VERSION_STEP 0x0000FFFF +#define BF_EMI_VERSION_STEP(v) \ + (((v) << 0) & BM_EMI_VERSION_STEP) +#endif /* __ARCH_ARM___EMI_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-i2c.h b/arch/arm/mach-mx23/include/mach/regs-i2c.h new file mode 100644 index 000000000000..a255d3fa78c5 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-i2c.h @@ -0,0 +1,383 @@ +/* + * Freescale I2C Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.54 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___I2C_H +#define __ARCH_ARM___I2C_H + + +#define HW_I2C_CTRL0 (0x00000000) +#define HW_I2C_CTRL0_SET (0x00000004) +#define HW_I2C_CTRL0_CLR (0x00000008) +#define HW_I2C_CTRL0_TOG (0x0000000c) + +#define BM_I2C_CTRL0_SFTRST 0x80000000 +#define BV_I2C_CTRL0_SFTRST__RUN 0x0 +#define BV_I2C_CTRL0_SFTRST__RESET 0x1 +#define BM_I2C_CTRL0_CLKGATE 0x40000000 +#define BV_I2C_CTRL0_CLKGATE__RUN 0x0 +#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_I2C_CTRL0_RUN 0x20000000 +#define BV_I2C_CTRL0_RUN__HALT 0x0 +#define BV_I2C_CTRL0_RUN__RUN 0x1 +#define BM_I2C_CTRL0_RSVD1 0x10000000 +#define BM_I2C_CTRL0_PRE_ACK 0x08000000 +#define BM_I2C_CTRL0_ACKNOWLEDGE 0x04000000 +#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_CTRL0_PIO_MODE 0x01000000 +#define BM_I2C_CTRL0_MULTI_MASTER 0x00800000 +#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_CTRL0_CLOCK_HELD 0x00400000 +#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 +#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 +#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 +#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 +#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 +#define BM_I2C_CTRL0_DIRECTION 0x00010000 +#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 +#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_CTRL0_XFER_COUNT 0 +#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_I2C_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_CTRL0_XFER_COUNT) + +#define HW_I2C_TIMING0 (0x00000010) +#define HW_I2C_TIMING0_SET (0x00000014) +#define HW_I2C_TIMING0_CLR (0x00000018) +#define HW_I2C_TIMING0_TOG (0x0000001c) + +#define BP_I2C_TIMING0_RSVD2 26 +#define BM_I2C_TIMING0_RSVD2 0xFC000000 +#define BF_I2C_TIMING0_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING0_RSVD2) +#define BP_I2C_TIMING0_HIGH_COUNT 16 +#define BM_I2C_TIMING0_HIGH_COUNT 0x03FF0000 +#define BF_I2C_TIMING0_HIGH_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING0_HIGH_COUNT) +#define BP_I2C_TIMING0_RSVD1 10 +#define BM_I2C_TIMING0_RSVD1 0x0000FC00 +#define BF_I2C_TIMING0_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING0_RSVD1) +#define BP_I2C_TIMING0_RCV_COUNT 0 +#define BM_I2C_TIMING0_RCV_COUNT 0x000003FF +#define BF_I2C_TIMING0_RCV_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING0_RCV_COUNT) + +#define HW_I2C_TIMING1 (0x00000020) +#define HW_I2C_TIMING1_SET (0x00000024) +#define HW_I2C_TIMING1_CLR (0x00000028) +#define HW_I2C_TIMING1_TOG (0x0000002c) + +#define BP_I2C_TIMING1_RSVD2 26 +#define BM_I2C_TIMING1_RSVD2 0xFC000000 +#define BF_I2C_TIMING1_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING1_RSVD2) +#define BP_I2C_TIMING1_LOW_COUNT 16 +#define BM_I2C_TIMING1_LOW_COUNT 0x03FF0000 +#define BF_I2C_TIMING1_LOW_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING1_LOW_COUNT) +#define BP_I2C_TIMING1_RSVD1 10 +#define BM_I2C_TIMING1_RSVD1 0x0000FC00 +#define BF_I2C_TIMING1_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING1_RSVD1) +#define BP_I2C_TIMING1_XMIT_COUNT 0 +#define BM_I2C_TIMING1_XMIT_COUNT 0x000003FF +#define BF_I2C_TIMING1_XMIT_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING1_XMIT_COUNT) + +#define HW_I2C_TIMING2 (0x00000030) +#define HW_I2C_TIMING2_SET (0x00000034) +#define HW_I2C_TIMING2_CLR (0x00000038) +#define HW_I2C_TIMING2_TOG (0x0000003c) + +#define BP_I2C_TIMING2_RSVD2 26 +#define BM_I2C_TIMING2_RSVD2 0xFC000000 +#define BF_I2C_TIMING2_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING2_RSVD2) +#define BP_I2C_TIMING2_BUS_FREE 16 +#define BM_I2C_TIMING2_BUS_FREE 0x03FF0000 +#define BF_I2C_TIMING2_BUS_FREE(v) \ + (((v) << 16) & BM_I2C_TIMING2_BUS_FREE) +#define BP_I2C_TIMING2_RSVD1 10 +#define BM_I2C_TIMING2_RSVD1 0x0000FC00 +#define BF_I2C_TIMING2_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING2_RSVD1) +#define BP_I2C_TIMING2_LEADIN_COUNT 0 +#define BM_I2C_TIMING2_LEADIN_COUNT 0x000003FF +#define BF_I2C_TIMING2_LEADIN_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING2_LEADIN_COUNT) + +#define HW_I2C_CTRL1 (0x00000040) +#define HW_I2C_CTRL1_SET (0x00000044) +#define HW_I2C_CTRL1_CLR (0x00000048) +#define HW_I2C_CTRL1_TOG (0x0000004c) + +#define BP_I2C_CTRL1_RSVD1 29 +#define BM_I2C_CTRL1_RSVD1 0xE0000000 +#define BF_I2C_CTRL1_RSVD1(v) \ + (((v) << 29) & BM_I2C_CTRL1_RSVD1) +#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING 0x0 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR 0x1 +#define BM_I2C_CTRL1_ACK_MODE 0x08000000 +#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW 0x0 +#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW 0x1 +#define BM_I2C_CTRL1_FORCE_DATA_IDLE 0x04000000 +#define BM_I2C_CTRL1_FORCE_CLK_IDLE 0x02000000 +#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x01000000 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 +#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 +#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0x00FF0000 +#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) \ + (((v) << 16) & BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE) +#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x00008000 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x00004000 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x00002000 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x00001000 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x00000800 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x00000400 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x00000200 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x00000100 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 +#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 + +#define HW_I2C_STAT (0x00000050) + +#define BM_I2C_STAT_MASTER_PRESENT 0x80000000 +#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 +#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 +#define BM_I2C_STAT_GOT_A_NAK 0x10000000 +#define BV_I2C_STAT_GOT_A_NAK__NO_NAK 0x0 +#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK 0x1 +#define BP_I2C_STAT_RSVD1 24 +#define BM_I2C_STAT_RSVD1 0x0F000000 +#define BF_I2C_STAT_RSVD1(v) \ + (((v) << 24) & BM_I2C_STAT_RSVD1) +#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 +#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0x00FF0000 +#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) \ + (((v) << 16) & BM_I2C_STAT_RCVD_SLAVE_ADDR) +#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x00008000 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 +#define BM_I2C_STAT_SLAVE_FOUND 0x00004000 +#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 +#define BM_I2C_STAT_SLAVE_SEARCHING 0x00002000 +#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 +#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x00001000 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 +#define BM_I2C_STAT_BUS_BUSY 0x00000800 +#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 +#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 +#define BM_I2C_STAT_CLK_GEN_BUSY 0x00000400 +#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 +#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 +#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x00000200 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_SLAVE_BUSY 0x00000100 +#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x00000080 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x00000040 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x00000020 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x00000010 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x00000008 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x00000004 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x00000002 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x00000001 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 + +#define HW_I2C_DATA (0x00000060) + +#define BP_I2C_DATA_DATA 0 +#define BM_I2C_DATA_DATA 0xFFFFFFFF +#define BF_I2C_DATA_DATA(v) (v) + +#define HW_I2C_DEBUG0 (0x00000070) +#define HW_I2C_DEBUG0_SET (0x00000074) +#define HW_I2C_DEBUG0_CLR (0x00000078) +#define HW_I2C_DEBUG0_TOG (0x0000007c) + +#define BM_I2C_DEBUG0_DMAREQ 0x80000000 +#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 +#define BM_I2C_DEBUG0_DMAKICK 0x20000000 +#define BM_I2C_DEBUG0_DMATERMINATE 0x10000000 +#define BP_I2C_DEBUG0_TBD 26 +#define BM_I2C_DEBUG0_TBD 0x0C000000 +#define BF_I2C_DEBUG0_TBD(v) \ + (((v) << 26) & BM_I2C_DEBUG0_TBD) +#define BP_I2C_DEBUG0_DMA_STATE 16 +#define BM_I2C_DEBUG0_DMA_STATE 0x03FF0000 +#define BF_I2C_DEBUG0_DMA_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG0_DMA_STATE) +#define BM_I2C_DEBUG0_START_TOGGLE 0x00008000 +#define BM_I2C_DEBUG0_STOP_TOGGLE 0x00004000 +#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x00002000 +#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x00001000 +#define BM_I2C_DEBUG0_TESTMODE 0x00000800 +#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x00000400 +#define BP_I2C_DEBUG0_SLAVE_STATE 0 +#define BM_I2C_DEBUG0_SLAVE_STATE 0x000003FF +#define BF_I2C_DEBUG0_SLAVE_STATE(v) \ + (((v) << 0) & BM_I2C_DEBUG0_SLAVE_STATE) + +#define HW_I2C_DEBUG1 (0x00000080) +#define HW_I2C_DEBUG1_SET (0x00000084) +#define HW_I2C_DEBUG1_CLR (0x00000088) +#define HW_I2C_DEBUG1_TOG (0x0000008c) + +#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 +#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 +#define BP_I2C_DEBUG1_RSVD4 28 +#define BM_I2C_DEBUG1_RSVD4 0x30000000 +#define BF_I2C_DEBUG1_RSVD4(v) \ + (((v) << 28) & BM_I2C_DEBUG1_RSVD4) +#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 +#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0x0F000000 +#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) \ + (((v) << 24) & BM_I2C_DEBUG1_DMA_BYTE_ENABLES) +#define BP_I2C_DEBUG1_CLK_GEN_STATE 16 +#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x00FF0000 +#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG1_CLK_GEN_STATE) +#define BP_I2C_DEBUG1_RSVD2 11 +#define BM_I2C_DEBUG1_RSVD2 0x0000F800 +#define BF_I2C_DEBUG1_RSVD2(v) \ + (((v) << 11) & BM_I2C_DEBUG1_RSVD2) +#define BP_I2C_DEBUG1_LST_MODE 9 +#define BM_I2C_DEBUG1_LST_MODE 0x00000600 +#define BF_I2C_DEBUG1_LST_MODE(v) \ + (((v) << 9) & BM_I2C_DEBUG1_LST_MODE) +#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 +#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 +#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 +#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 +#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x00000100 +#define BP_I2C_DEBUG1_RSVD1 5 +#define BM_I2C_DEBUG1_RSVD1 0x000000E0 +#define BF_I2C_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_I2C_DEBUG1_RSVD1) +#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x00000010 +#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x00000008 +#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x00000004 +#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x00000002 +#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x00000001 + +#define HW_I2C_VERSION (0x00000090) + +#define BP_I2C_VERSION_MAJOR 24 +#define BM_I2C_VERSION_MAJOR 0xFF000000 +#define BF_I2C_VERSION_MAJOR(v) \ + (((v) << 24) & BM_I2C_VERSION_MAJOR) +#define BP_I2C_VERSION_MINOR 16 +#define BM_I2C_VERSION_MINOR 0x00FF0000 +#define BF_I2C_VERSION_MINOR(v) \ + (((v) << 16) & BM_I2C_VERSION_MINOR) +#define BP_I2C_VERSION_STEP 0 +#define BM_I2C_VERSION_STEP 0x0000FFFF +#define BF_I2C_VERSION_STEP(v) \ + (((v) << 0) & BM_I2C_VERSION_STEP) +#endif /* __ARCH_ARM___I2C_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-lcdif.h b/arch/arm/mach-mx23/include/mach/regs-lcdif.h new file mode 100644 index 000000000000..b8eae0f47e57 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-lcdif.h @@ -0,0 +1,650 @@ +/* + * Freescale LCDIF Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.32 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LCDIF_H +#define __ARCH_ARM___LCDIF_H + + +#define HW_LCDIF_CTRL (0x00000000) +#define HW_LCDIF_CTRL_SET (0x00000004) +#define HW_LCDIF_CTRL_CLR (0x00000008) +#define HW_LCDIF_CTRL_TOG (0x0000000c) + +#define BM_LCDIF_CTRL_SFTRST 0x80000000 +#define BM_LCDIF_CTRL_CLKGATE 0x40000000 +#define BM_LCDIF_CTRL_YCBCR422_INPUT 0x20000000 +#define BM_LCDIF_CTRL_RSRVD0 0x10000000 +#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 +#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 +#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 +#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 +#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) \ + (((v) << 21) & BM_LCDIF_CTRL_SHIFT_NUM_BITS) +#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 +#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 +#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 +#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 +#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 +#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 +#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 +#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 +#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 +#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \ + (((v) << 14) & BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE 12 +#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000 +#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v) \ + (((v) << 12) & BM_LCDIF_CTRL_CSC_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 +#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 +#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v) \ + (((v) << 10) & BM_LCDIF_CTRL_LCD_DATABUS_WIDTH) +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3 +#define BP_LCDIF_CTRL_WORD_LENGTH 8 +#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 +#define BF_LCDIF_CTRL_WORD_LENGTH(v) \ + (((v) << 8) & BM_LCDIF_CTRL_WORD_LENGTH) +#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT 0x3 +#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 +#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040 +#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 +#define BM_LCDIF_CTRL_DMA_BURST_LENGTH 0x00000010 +#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008 +#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1 +#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1 +#define BM_LCDIF_CTRL_RUN 0x00000001 + +#define HW_LCDIF_CTRL1 (0x00000010) +#define HW_LCDIF_CTRL1_SET (0x00000014) +#define HW_LCDIF_CTRL1_CLR (0x00000018) +#define HW_LCDIF_CTRL1_TOG (0x0000001c) + +#define BP_LCDIF_CTRL1_RSRVD1 27 +#define BM_LCDIF_CTRL1_RSRVD1 0xF8000000 +#define BF_LCDIF_CTRL1_RSRVD1(v) \ + (((v) << 27) & BM_LCDIF_CTRL1_RSRVD1) +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ 0x02000000 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 +#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 +#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000 +#define BM_LCDIF_CTRL1_FIFO_CLEAR 0x00200000 +#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000 +#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 +#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 +#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \ + (((v) << 16) & BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT) +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_RSRVD0 0x00000080 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER 0x00000040 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN 0x00000020 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ 0x00000010 +#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_LCD_CS_CTRL 0x00000008 +#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 +#define BM_LCDIF_CTRL1_MODE86 0x00000002 +#define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 +#define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 +#define BM_LCDIF_CTRL1_RESET 0x00000001 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 + +#define HW_LCDIF_TRANSFER_COUNT (0x00000020) + +#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 +#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 +#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v) \ + (((v) << 16) & BM_LCDIF_TRANSFER_COUNT_V_COUNT) +#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 +#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF +#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v) \ + (((v) << 0) & BM_LCDIF_TRANSFER_COUNT_H_COUNT) + +#define HW_LCDIF_CUR_BUF (0x00000030) + +#define BP_LCDIF_CUR_BUF_ADDR 0 +#define BM_LCDIF_CUR_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_CUR_BUF_ADDR(v) (v) + +#define HW_LCDIF_NEXT_BUF (0x00000040) + +#define BP_LCDIF_NEXT_BUF_ADDR 0 +#define BM_LCDIF_NEXT_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_NEXT_BUF_ADDR(v) (v) + +#define HW_LCDIF_PAGETABLE (0x00000050) + +#define BP_LCDIF_PAGETABLE_BASE 14 +#define BM_LCDIF_PAGETABLE_BASE 0xFFFFC000 +#define BF_LCDIF_PAGETABLE_BASE(v) \ + (((v) << 14) & BM_LCDIF_PAGETABLE_BASE) +#define BP_LCDIF_PAGETABLE_RSVD1 2 +#define BM_LCDIF_PAGETABLE_RSVD1 0x00003FFC +#define BF_LCDIF_PAGETABLE_RSVD1(v) \ + (((v) << 2) & BM_LCDIF_PAGETABLE_RSVD1) +#define BM_LCDIF_PAGETABLE_FLUSH 0x00000002 +#define BM_LCDIF_PAGETABLE_ENABLE 0x00000001 + +#define HW_LCDIF_TIMING (0x00000060) + +#define BP_LCDIF_TIMING_CMD_HOLD 24 +#define BM_LCDIF_TIMING_CMD_HOLD 0xFF000000 +#define BF_LCDIF_TIMING_CMD_HOLD(v) \ + (((v) << 24) & BM_LCDIF_TIMING_CMD_HOLD) +#define BP_LCDIF_TIMING_CMD_SETUP 16 +#define BM_LCDIF_TIMING_CMD_SETUP 0x00FF0000 +#define BF_LCDIF_TIMING_CMD_SETUP(v) \ + (((v) << 16) & BM_LCDIF_TIMING_CMD_SETUP) +#define BP_LCDIF_TIMING_DATA_HOLD 8 +#define BM_LCDIF_TIMING_DATA_HOLD 0x0000FF00 +#define BF_LCDIF_TIMING_DATA_HOLD(v) \ + (((v) << 8) & BM_LCDIF_TIMING_DATA_HOLD) +#define BP_LCDIF_TIMING_DATA_SETUP 0 +#define BM_LCDIF_TIMING_DATA_SETUP 0x000000FF +#define BF_LCDIF_TIMING_DATA_SETUP(v) \ + (((v) << 0) & BM_LCDIF_TIMING_DATA_SETUP) + +#define HW_LCDIF_VDCTRL0 (0x00000070) +#define HW_LCDIF_VDCTRL0_SET (0x00000074) +#define HW_LCDIF_VDCTRL0_CLR (0x00000078) +#define HW_LCDIF_VDCTRL0_TOG (0x0000007c) + +#define BP_LCDIF_VDCTRL0_RSRVD2 30 +#define BM_LCDIF_VDCTRL0_RSRVD2 0xC0000000 +#define BF_LCDIF_VDCTRL0_RSRVD2(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL0_RSRVD2) +#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 +#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 +#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 +#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 +#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 +#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 +#define BP_LCDIF_VDCTRL0_RSRVD1 22 +#define BM_LCDIF_VDCTRL0_RSRVD1 0x00C00000 +#define BF_LCDIF_VDCTRL0_RSRVD1(v) \ + (((v) << 22) & BM_LCDIF_VDCTRL0_RSRVD1) +#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 +#define BM_LCDIF_VDCTRL0_HALF_LINE 0x00080000 +#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000 +#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF +#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH) + +#define HW_LCDIF_VDCTRL1 (0x00000080) + +#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF +#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (v) + +#define HW_LCDIF_VDCTRL2 (0x00000090) + +#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 +#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 +#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \ + (((v) << 24) & BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH) +#define BP_LCDIF_VDCTRL2_RSRVD0 18 +#define BM_LCDIF_VDCTRL2_RSRVD0 0x00FC0000 +#define BF_LCDIF_VDCTRL2_RSRVD0(v) \ + (((v) << 18) & BM_LCDIF_VDCTRL2_RSRVD0) +#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF +#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL2_HSYNC_PERIOD) + +#define HW_LCDIF_VDCTRL3 (0x000000a0) + +#define BP_LCDIF_VDCTRL3_RSRVD0 30 +#define BM_LCDIF_VDCTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_VDCTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL3_RSRVD0) +#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000 +#define BM_LCDIF_VDCTRL3_VSYNC_ONLY 0x10000000 +#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 +#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 +#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \ + (((v) << 16) & BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT) +#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 +#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF +#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT) + +#define HW_LCDIF_VDCTRL4 (0x000000b0) + +#define BP_LCDIF_VDCTRL4_RSRVD0 19 +#define BM_LCDIF_VDCTRL4_RSRVD0 0xFFF80000 +#define BF_LCDIF_VDCTRL4_RSRVD0(v) \ + (((v) << 19) & BM_LCDIF_VDCTRL4_RSRVD0) +#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 +#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 +#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF +#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT) + +#define HW_LCDIF_DVICTRL0 (0x000000c0) + +#define BM_LCDIF_DVICTRL0_START_TRS 0x80000000 +#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 +#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 +#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL0_H_ACTIVE_CNT) +#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 +#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 +#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL0_H_BLANKING_CNT) +#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 +#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF +#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL0_V_LINES_CNT) + +#define HW_LCDIF_DVICTRL1 (0x000000d0) + +#define BP_LCDIF_DVICTRL1_RSRVD0 30 +#define BM_LCDIF_DVICTRL1_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL1_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL1_RSRVD0) +#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 +#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL1_F1_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL1_F1_START_LINE) +#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 +#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL1_F1_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL1_F1_END_LINE) +#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 +#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF +#define BF_LCDIF_DVICTRL1_F2_START_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL1_F2_START_LINE) + +#define HW_LCDIF_DVICTRL2 (0x000000e0) + +#define BP_LCDIF_DVICTRL2_RSRVD0 30 +#define BM_LCDIF_DVICTRL2_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL2_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL2_RSRVD0) +#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 +#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL2_F2_END_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL2_F2_END_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 +#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE) + +#define HW_LCDIF_DVICTRL3 (0x000000f0) + +#define BP_LCDIF_DVICTRL3_RSRVD1 26 +#define BM_LCDIF_DVICTRL3_RSRVD1 0xFC000000 +#define BF_LCDIF_DVICTRL3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_DVICTRL3_RSRVD1) +#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 +#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 +#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL3_RSRVD0 10 +#define BM_LCDIF_DVICTRL3_RSRVD0 0x0000FC00 +#define BF_LCDIF_DVICTRL3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL3_RSRVD0) +#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE) + +#define HW_LCDIF_DVICTRL4 (0x00000100) + +#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 +#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 +#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v) \ + (((v) << 24) & BM_LCDIF_DVICTRL4_Y_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 +#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 +#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL4_CB_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 +#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 +#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v) \ + (((v) << 8) & BM_LCDIF_DVICTRL4_CR_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 +#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF +#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL4_H_FILL_CNT) + +#define HW_LCDIF_CSC_COEFF0 (0x00000110) + +#define BP_LCDIF_CSC_COEFF0_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF0_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF0_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF0_RSRVD1) +#define BP_LCDIF_CSC_COEFF0_C0 16 +#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 +#define BF_LCDIF_CSC_COEFF0_C0(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF0_C0) +#define BP_LCDIF_CSC_COEFF0_RSRVD0 2 +#define BM_LCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC +#define BF_LCDIF_CSC_COEFF0_RSRVD0(v) \ + (((v) << 2) & BM_LCDIF_CSC_COEFF0_RSRVD0) +#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 +#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 +#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER) +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3 + +#define HW_LCDIF_CSC_COEFF1 (0x00000120) + +#define BP_LCDIF_CSC_COEFF1_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF1_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF1_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF1_RSRVD1) +#define BP_LCDIF_CSC_COEFF1_C2 16 +#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 +#define BF_LCDIF_CSC_COEFF1_C2(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF1_C2) +#define BP_LCDIF_CSC_COEFF1_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF1_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF1_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF1_RSRVD0) +#define BP_LCDIF_CSC_COEFF1_C1 0 +#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF +#define BF_LCDIF_CSC_COEFF1_C1(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF1_C1) + +#define HW_LCDIF_CSC_COEFF2 (0x00000130) + +#define BP_LCDIF_CSC_COEFF2_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF2_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF2_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF2_RSRVD1) +#define BP_LCDIF_CSC_COEFF2_C4 16 +#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 +#define BF_LCDIF_CSC_COEFF2_C4(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF2_C4) +#define BP_LCDIF_CSC_COEFF2_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF2_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF2_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF2_RSRVD0) +#define BP_LCDIF_CSC_COEFF2_C3 0 +#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF +#define BF_LCDIF_CSC_COEFF2_C3(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF2_C3) + +#define HW_LCDIF_CSC_COEFF3 (0x00000140) + +#define BP_LCDIF_CSC_COEFF3_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF3_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF3_RSRVD1) +#define BP_LCDIF_CSC_COEFF3_C6 16 +#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 +#define BF_LCDIF_CSC_COEFF3_C6(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF3_C6) +#define BP_LCDIF_CSC_COEFF3_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF3_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF3_RSRVD0) +#define BP_LCDIF_CSC_COEFF3_C5 0 +#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF +#define BF_LCDIF_CSC_COEFF3_C5(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF3_C5) + +#define HW_LCDIF_CSC_COEFF4 (0x00000150) + +#define BP_LCDIF_CSC_COEFF4_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF4_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF4_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF4_RSRVD1) +#define BP_LCDIF_CSC_COEFF4_C8 16 +#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 +#define BF_LCDIF_CSC_COEFF4_C8(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF4_C8) +#define BP_LCDIF_CSC_COEFF4_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF4_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF4_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF4_RSRVD0) +#define BP_LCDIF_CSC_COEFF4_C7 0 +#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF +#define BF_LCDIF_CSC_COEFF4_C7(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF4_C7) + +#define HW_LCDIF_CSC_OFFSET (0x00000160) + +#define BP_LCDIF_CSC_OFFSET_RSRVD1 25 +#define BM_LCDIF_CSC_OFFSET_RSRVD1 0xFE000000 +#define BF_LCDIF_CSC_OFFSET_RSRVD1(v) \ + (((v) << 25) & BM_LCDIF_CSC_OFFSET_RSRVD1) +#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 +#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 +#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v) \ + (((v) << 16) & BM_LCDIF_CSC_OFFSET_CBCR_OFFSET) +#define BP_LCDIF_CSC_OFFSET_RSRVD0 9 +#define BM_LCDIF_CSC_OFFSET_RSRVD0 0x0000FE00 +#define BF_LCDIF_CSC_OFFSET_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_CSC_OFFSET_RSRVD0) +#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 +#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF +#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v) \ + (((v) << 0) & BM_LCDIF_CSC_OFFSET_Y_OFFSET) + +#define HW_LCDIF_CSC_LIMIT (0x00000170) + +#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 +#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v) \ + (((v) << 24) & BM_LCDIF_CSC_LIMIT_CBCR_MIN) +#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 +#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v) \ + (((v) << 16) & BM_LCDIF_CSC_LIMIT_CBCR_MAX) +#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 +#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 +#define BF_LCDIF_CSC_LIMIT_Y_MIN(v) \ + (((v) << 8) & BM_LCDIF_CSC_LIMIT_Y_MIN) +#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 +#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF +#define BF_LCDIF_CSC_LIMIT_Y_MAX(v) \ + (((v) << 0) & BM_LCDIF_CSC_LIMIT_Y_MAX) + +#define HW_LCDIF_PIN_SHARING_CTRL0 (0x00000180) +#define HW_LCDIF_PIN_SHARING_CTRL0_SET (0x00000184) +#define HW_LCDIF_PIN_SHARING_CTRL0_CLR (0x00000188) +#define HW_LCDIF_PIN_SHARING_CTRL0_TOG (0x0000018c) + +#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1 6 +#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1 0xFFFFFFC0 +#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v) \ + (((v) << 6) & BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1) +#define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 4 +#define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 0x00000030 +#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v) \ + (((v) << 4) & BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE) +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE 0x0 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD 0x1 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL 0x2 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL 0x3 +#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0 0x00000008 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN 0x00000004 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ 0x00000002 +#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST 0x1 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE 0x00000001 + +#define HW_LCDIF_PIN_SHARING_CTRL1 (0x00000190) + +#define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0 +#define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0xFFFFFFFF +#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v) (v) + +#define HW_LCDIF_PIN_SHARING_CTRL2 (0x000001a0) + +#define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0 +#define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0xFFFFFFFF +#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v) (v) + +#define HW_LCDIF_DATA (0x000001b0) + +#define BP_LCDIF_DATA_DATA_THREE 24 +#define BM_LCDIF_DATA_DATA_THREE 0xFF000000 +#define BF_LCDIF_DATA_DATA_THREE(v) \ + (((v) << 24) & BM_LCDIF_DATA_DATA_THREE) +#define BP_LCDIF_DATA_DATA_TWO 16 +#define BM_LCDIF_DATA_DATA_TWO 0x00FF0000 +#define BF_LCDIF_DATA_DATA_TWO(v) \ + (((v) << 16) & BM_LCDIF_DATA_DATA_TWO) +#define BP_LCDIF_DATA_DATA_ONE 8 +#define BM_LCDIF_DATA_DATA_ONE 0x0000FF00 +#define BF_LCDIF_DATA_DATA_ONE(v) \ + (((v) << 8) & BM_LCDIF_DATA_DATA_ONE) +#define BP_LCDIF_DATA_DATA_ZERO 0 +#define BM_LCDIF_DATA_DATA_ZERO 0x000000FF +#define BF_LCDIF_DATA_DATA_ZERO(v) \ + (((v) << 0) & BM_LCDIF_DATA_DATA_ZERO) + +#define HW_LCDIF_BM_ERROR_STAT (0x000001c0) + +#define BP_LCDIF_BM_ERROR_STAT_ADDR 0 +#define BM_LCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF +#define BF_LCDIF_BM_ERROR_STAT_ADDR(v) (v) + +#define HW_LCDIF_STAT (0x000001d0) + +#define BM_LCDIF_STAT_PRESENT 0x80000000 +#define BM_LCDIF_STAT_DMA_REQ 0x40000000 +#define BM_LCDIF_STAT_LFIFO_FULL 0x20000000 +#define BM_LCDIF_STAT_LFIFO_EMPTY 0x10000000 +#define BM_LCDIF_STAT_TXFIFO_FULL 0x08000000 +#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 +#define BM_LCDIF_STAT_BUSY 0x02000000 +#define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x01000000 +#define BP_LCDIF_STAT_RSRVD0 0 +#define BM_LCDIF_STAT_RSRVD0 0x00FFFFFF +#define BF_LCDIF_STAT_RSRVD0(v) \ + (((v) << 0) & BM_LCDIF_STAT_RSRVD0) + +#define HW_LCDIF_VERSION (0x000001e0) + +#define BP_LCDIF_VERSION_MAJOR 24 +#define BM_LCDIF_VERSION_MAJOR 0xFF000000 +#define BF_LCDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LCDIF_VERSION_MAJOR) +#define BP_LCDIF_VERSION_MINOR 16 +#define BM_LCDIF_VERSION_MINOR 0x00FF0000 +#define BF_LCDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_LCDIF_VERSION_MINOR) +#define BP_LCDIF_VERSION_STEP 0 +#define BM_LCDIF_VERSION_STEP 0x0000FFFF +#define BF_LCDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_LCDIF_VERSION_STEP) + +#define HW_LCDIF_DEBUG0 (0x000001f0) + +#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 +#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 +#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 +#define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 +#define BM_LCDIF_DEBUG0_ENABLE 0x08000000 +#define BM_LCDIF_DEBUG0_HSYNC 0x04000000 +#define BM_LCDIF_DEBUG0_VSYNC 0x02000000 +#define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x01000000 +#define BM_LCDIF_DEBUG0_EMPTY_WORD 0x00800000 +#define BP_LCDIF_DEBUG0_CUR_STATE 16 +#define BM_LCDIF_DEBUG0_CUR_STATE 0x007F0000 +#define BF_LCDIF_DEBUG0_CUR_STATE(v) \ + (((v) << 16) & BM_LCDIF_DEBUG0_CUR_STATE) +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 0x00008000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 0x00004000 +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 0x00002000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 0x00001000 +#define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ 0x00000800 +#define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT 0x00000400 +#define BP_LCDIF_DEBUG0_RSRVD0 0 +#define BM_LCDIF_DEBUG0_RSRVD0 0x000003FF +#define BF_LCDIF_DEBUG0_RSRVD0(v) \ + (((v) << 0) & BM_LCDIF_DEBUG0_RSRVD0) + +#define HW_LCDIF_DEBUG1 (0x00000200) + +#define BP_LCDIF_DEBUG1_H_DATA_COUNT 16 +#define BM_LCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000 +#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) \ + (((v) << 16) & BM_LCDIF_DEBUG1_H_DATA_COUNT) +#define BP_LCDIF_DEBUG1_V_DATA_COUNT 0 +#define BM_LCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF +#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) \ + (((v) << 0) & BM_LCDIF_DEBUG1_V_DATA_COUNT) +#endif /* __ARCH_ARM___LCDIF_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-lradc.h b/arch/arm/mach-mx23/include/mach/regs-lradc.h new file mode 100644 index 000000000000..77af4be1d33b --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-lradc.h @@ -0,0 +1,669 @@ +/* + * Freescale LRADC Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LRADC_H +#define __ARCH_ARM___LRADC_H + + +#define HW_LRADC_CTRL0 (0x00000000) +#define HW_LRADC_CTRL0_SET (0x00000004) +#define HW_LRADC_CTRL0_CLR (0x00000008) +#define HW_LRADC_CTRL0_TOG (0x0000000c) + +#define BM_LRADC_CTRL0_SFTRST 0x80000000 +#define BM_LRADC_CTRL0_CLKGATE 0x40000000 +#define BP_LRADC_CTRL0_RSRVD2 22 +#define BM_LRADC_CTRL0_RSRVD2 0x3FC00000 +#define BF_LRADC_CTRL0_RSRVD2(v) \ + (((v) << 22) & BM_LRADC_CTRL0_RSRVD2) +#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 +#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 +#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 +#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 +#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 +#define BP_LRADC_CTRL0_RSRVD1 8 +#define BM_LRADC_CTRL0_RSRVD1 0x0000FF00 +#define BF_LRADC_CTRL0_RSRVD1(v) \ + (((v) << 8) & BM_LRADC_CTRL0_RSRVD1) +#define BP_LRADC_CTRL0_SCHEDULE 0 +#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF +#define BF_LRADC_CTRL0_SCHEDULE(v) \ + (((v) << 0) & BM_LRADC_CTRL0_SCHEDULE) + +#define HW_LRADC_CTRL1 (0x00000010) +#define HW_LRADC_CTRL1_SET (0x00000014) +#define HW_LRADC_CTRL1_CLR (0x00000018) +#define HW_LRADC_CTRL1_TOG (0x0000001c) + +#define BP_LRADC_CTRL1_RSRVD2 25 +#define BM_LRADC_CTRL1_RSRVD2 0xFE000000 +#define BF_LRADC_CTRL1_RSRVD2(v) \ + (((v) << 25) & BM_LRADC_CTRL1_RSRVD2) +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x00800000 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x00400000 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x00100000 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x00080000 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x00040000 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x00020000 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 +#define BP_LRADC_CTRL1_RSRVD1 9 +#define BM_LRADC_CTRL1_RSRVD1 0x0000FE00 +#define BF_LRADC_CTRL1_RSRVD1(v) \ + (((v) << 9) & BM_LRADC_CTRL1_RSRVD1) +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ 0x00000080 +#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 +#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 +#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ 0x00000010 +#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ 0x00000008 +#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ 0x00000004 +#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ 0x00000002 +#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 +#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 + +#define HW_LRADC_CTRL2 (0x00000020) +#define HW_LRADC_CTRL2_SET (0x00000024) +#define HW_LRADC_CTRL2_CLR (0x00000028) +#define HW_LRADC_CTRL2_TOG (0x0000002c) + +#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 +#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 +#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) \ + (((v) << 24) & BM_LRADC_CTRL2_DIVIDE_BY_TWO) +#define BM_LRADC_CTRL2_BL_AMP_BYPASS 0x00800000 +#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE 0x0 +#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE 0x1 +#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 +#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 +#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 +#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 +#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v) \ + (((v) << 16) & BM_LRADC_CTRL2_BL_BRIGHTNESS) +#define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x00008000 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x0 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x1 +#define BM_LRADC_CTRL2_RSRVD1 0x00004000 +#define BM_LRADC_CTRL2_EXT_EN1 0x00002000 +#define BV_LRADC_CTRL2_EXT_EN1__DISABLE 0x0 +#define BV_LRADC_CTRL2_EXT_EN1__ENABLE 0x1 +#define BM_LRADC_CTRL2_EXT_EN0 0x00001000 +#define BP_LRADC_CTRL2_RSRVD2 10 +#define BM_LRADC_CTRL2_RSRVD2 0x00000C00 +#define BF_LRADC_CTRL2_RSRVD2(v) \ + (((v) << 10) & BM_LRADC_CTRL2_RSRVD2) +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x00000200 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x00000100 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 +#define BP_LRADC_CTRL2_TEMP_ISRC1 4 +#define BM_LRADC_CTRL2_TEMP_ISRC1 0x000000F0 +#define BF_LRADC_CTRL2_TEMP_ISRC1(v) \ + (((v) << 4) & BM_LRADC_CTRL2_TEMP_ISRC1) +#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 +#define BP_LRADC_CTRL2_TEMP_ISRC0 0 +#define BM_LRADC_CTRL2_TEMP_ISRC0 0x0000000F +#define BF_LRADC_CTRL2_TEMP_ISRC0(v) \ + (((v) << 0) & BM_LRADC_CTRL2_TEMP_ISRC0) +#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 + +#define HW_LRADC_CTRL3 (0x00000030) +#define HW_LRADC_CTRL3_SET (0x00000034) +#define HW_LRADC_CTRL3_CLR (0x00000038) +#define HW_LRADC_CTRL3_TOG (0x0000003c) + +#define BP_LRADC_CTRL3_RSRVD5 26 +#define BM_LRADC_CTRL3_RSRVD5 0xFC000000 +#define BF_LRADC_CTRL3_RSRVD5(v) \ + (((v) << 26) & BM_LRADC_CTRL3_RSRVD5) +#define BP_LRADC_CTRL3_DISCARD 24 +#define BM_LRADC_CTRL3_DISCARD 0x03000000 +#define BF_LRADC_CTRL3_DISCARD(v) \ + (((v) << 24) & BM_LRADC_CTRL3_DISCARD) +#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 +#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 +#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x00800000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x00400000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 +#define BP_LRADC_CTRL3_RSRVD4 14 +#define BM_LRADC_CTRL3_RSRVD4 0x003FC000 +#define BF_LRADC_CTRL3_RSRVD4(v) \ + (((v) << 14) & BM_LRADC_CTRL3_RSRVD4) +#define BP_LRADC_CTRL3_RSRVD3 10 +#define BM_LRADC_CTRL3_RSRVD3 0x00003C00 +#define BF_LRADC_CTRL3_RSRVD3(v) \ + (((v) << 10) & BM_LRADC_CTRL3_RSRVD3) +#define BP_LRADC_CTRL3_CYCLE_TIME 8 +#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 +#define BF_LRADC_CTRL3_CYCLE_TIME(v) \ + (((v) << 8) & BM_LRADC_CTRL3_CYCLE_TIME) +#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 +#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 +#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 +#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 +#define BP_LRADC_CTRL3_RSRVD2 6 +#define BM_LRADC_CTRL3_RSRVD2 0x000000C0 +#define BF_LRADC_CTRL3_RSRVD2(v) \ + (((v) << 6) & BM_LRADC_CTRL3_RSRVD2) +#define BP_LRADC_CTRL3_HIGH_TIME 4 +#define BM_LRADC_CTRL3_HIGH_TIME 0x00000030 +#define BF_LRADC_CTRL3_HIGH_TIME(v) \ + (((v) << 4) & BM_LRADC_CTRL3_HIGH_TIME) +#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 +#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 +#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 +#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 +#define BP_LRADC_CTRL3_RSRVD1 2 +#define BM_LRADC_CTRL3_RSRVD1 0x0000000C +#define BF_LRADC_CTRL3_RSRVD1(v) \ + (((v) << 2) & BM_LRADC_CTRL3_RSRVD1) +#define BM_LRADC_CTRL3_DELAY_CLOCK 0x00000002 +#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 +#define BM_LRADC_CTRL3_INVERT_CLOCK 0x00000001 +#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 + +#define HW_LRADC_STATUS (0x00000040) +#define HW_LRADC_STATUS_SET (0x00000044) +#define HW_LRADC_STATUS_CLR (0x00000048) +#define HW_LRADC_STATUS_TOG (0x0000004c) + +#define BP_LRADC_STATUS_RSRVD3 27 +#define BM_LRADC_STATUS_RSRVD3 0xF8000000 +#define BF_LRADC_STATUS_RSRVD3(v) \ + (((v) << 27) & BM_LRADC_STATUS_RSRVD3) +#define BM_LRADC_STATUS_TEMP1_PRESENT 0x04000000 +#define BM_LRADC_STATUS_TEMP0_PRESENT 0x02000000 +#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x01000000 +#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x00800000 +#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x00400000 +#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x00200000 +#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x00100000 +#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x00080000 +#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x00040000 +#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x00020000 +#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x00010000 +#define BP_LRADC_STATUS_RSRVD2 1 +#define BM_LRADC_STATUS_RSRVD2 0x0000FFFE +#define BF_LRADC_STATUS_RSRVD2(v) \ + (((v) << 1) & BM_LRADC_STATUS_RSRVD2) +#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 + +/* + * multi-register-define name HW_LRADC_CHn + * base 0x00000050 + * count 6 + * offset 0x10 + */ +#define HW_LRADC_CHn(n) (0x00000050 + (n) * 0x10) +#define HW_LRADC_CHn_SET(n) (0x00000054 + (n) * 0x10) +#define HW_LRADC_CHn_CLR(n) (0x00000058 + (n) * 0x10) +#define HW_LRADC_CHn_TOG(n) (0x0000005c + (n) * 0x10) +#define BM_LRADC_CHn_TOGGLE 0x80000000 +#define BM_LRADC_CHn_RSRVD2 0x40000000 +#define BM_LRADC_CHn_ACCUMULATE 0x20000000 +#define BP_LRADC_CHn_NUM_SAMPLES 24 +#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CHn_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CHn_NUM_SAMPLES) +#define BP_LRADC_CHn_RSRVD1 18 +#define BM_LRADC_CHn_RSRVD1 0x00FC0000 +#define BF_LRADC_CHn_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CHn_RSRVD1) +#define BP_LRADC_CHn_VALUE 0 +#define BM_LRADC_CHn_VALUE 0x0003FFFF +#define BF_LRADC_CHn_VALUE(v) \ + (((v) << 0) & BM_LRADC_CHn_VALUE) + +#define HW_LRADC_CH6 (0x000000b0) +#define HW_LRADC_CH6_SET (0x000000b4) +#define HW_LRADC_CH6_CLR (0x000000b8) +#define HW_LRADC_CH6_TOG (0x000000bc) + +#define BM_LRADC_CH6_TOGGLE 0x80000000 +#define BM_LRADC_CH6_RSRVD2 0x40000000 +#define BM_LRADC_CH6_ACCUMULATE 0x20000000 +#define BP_LRADC_CH6_NUM_SAMPLES 24 +#define BM_LRADC_CH6_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH6_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH6_NUM_SAMPLES) +#define BP_LRADC_CH6_RSRVD1 18 +#define BM_LRADC_CH6_RSRVD1 0x00FC0000 +#define BF_LRADC_CH6_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH6_RSRVD1) +#define BP_LRADC_CH6_VALUE 0 +#define BM_LRADC_CH6_VALUE 0x0003FFFF +#define BF_LRADC_CH6_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH6_VALUE) + +#define HW_LRADC_CH7 (0x000000c0) +#define HW_LRADC_CH7_SET (0x000000c4) +#define HW_LRADC_CH7_CLR (0x000000c8) +#define HW_LRADC_CH7_TOG (0x000000cc) + +#define BM_LRADC_CH7_TOGGLE 0x80000000 +#define BM_LRADC_CH7_TESTMODE_TOGGLE 0x40000000 +#define BM_LRADC_CH7_ACCUMULATE 0x20000000 +#define BP_LRADC_CH7_NUM_SAMPLES 24 +#define BM_LRADC_CH7_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH7_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH7_NUM_SAMPLES) +#define BP_LRADC_CH7_RSRVD1 18 +#define BM_LRADC_CH7_RSRVD1 0x00FC0000 +#define BF_LRADC_CH7_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH7_RSRVD1) +#define BP_LRADC_CH7_VALUE 0 +#define BM_LRADC_CH7_VALUE 0x0003FFFF +#define BF_LRADC_CH7_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH7_VALUE) + +/* + * multi-register-define name HW_LRADC_DELAYn + * base 0x000000D0 + * count 4 + * offset 0x10 + */ +#define HW_LRADC_DELAYn(n) (0x000000d0 + (n) * 0x10) +#define HW_LRADC_DELAYn_SET(n) (0x000000d4 + (n) * 0x10) +#define HW_LRADC_DELAYn_CLR(n) (0x000000d8 + (n) * 0x10) +#define HW_LRADC_DELAYn_TOG(n) (0x000000dc + (n) * 0x10) +#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 +#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 +#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) \ + (((v) << 24) & BM_LRADC_DELAYn_TRIGGER_LRADCS) +#define BP_LRADC_DELAYn_RSRVD2 21 +#define BM_LRADC_DELAYn_RSRVD2 0x00E00000 +#define BF_LRADC_DELAYn_RSRVD2(v) \ + (((v) << 21) & BM_LRADC_DELAYn_RSRVD2) +#define BM_LRADC_DELAYn_KICK 0x00100000 +#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 +#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 +#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) \ + (((v) << 16) & BM_LRADC_DELAYn_TRIGGER_DELAYS) +#define BP_LRADC_DELAYn_LOOP_COUNT 11 +#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 +#define BF_LRADC_DELAYn_LOOP_COUNT(v) \ + (((v) << 11) & BM_LRADC_DELAYn_LOOP_COUNT) +#define BP_LRADC_DELAYn_DELAY 0 +#define BM_LRADC_DELAYn_DELAY 0x000007FF +#define BF_LRADC_DELAYn_DELAY(v) \ + (((v) << 0) & BM_LRADC_DELAYn_DELAY) + +#define HW_LRADC_DEBUG0 (0x00000110) +#define HW_LRADC_DEBUG0_SET (0x00000114) +#define HW_LRADC_DEBUG0_CLR (0x00000118) +#define HW_LRADC_DEBUG0_TOG (0x0000011c) + +#define BP_LRADC_DEBUG0_READONLY 16 +#define BM_LRADC_DEBUG0_READONLY 0xFFFF0000 +#define BF_LRADC_DEBUG0_READONLY(v) \ + (((v) << 16) & BM_LRADC_DEBUG0_READONLY) +#define BP_LRADC_DEBUG0_RSRVD1 12 +#define BM_LRADC_DEBUG0_RSRVD1 0x0000F000 +#define BF_LRADC_DEBUG0_RSRVD1(v) \ + (((v) << 12) & BM_LRADC_DEBUG0_RSRVD1) +#define BP_LRADC_DEBUG0_STATE 0 +#define BM_LRADC_DEBUG0_STATE 0x00000FFF +#define BF_LRADC_DEBUG0_STATE(v) \ + (((v) << 0) & BM_LRADC_DEBUG0_STATE) + +#define HW_LRADC_DEBUG1 (0x00000120) +#define HW_LRADC_DEBUG1_SET (0x00000124) +#define HW_LRADC_DEBUG1_CLR (0x00000128) +#define HW_LRADC_DEBUG1_TOG (0x0000012c) + +#define BP_LRADC_DEBUG1_RSRVD3 24 +#define BM_LRADC_DEBUG1_RSRVD3 0xFF000000 +#define BF_LRADC_DEBUG1_RSRVD3(v) \ + (((v) << 24) & BM_LRADC_DEBUG1_RSRVD3) +#define BP_LRADC_DEBUG1_REQUEST 16 +#define BM_LRADC_DEBUG1_REQUEST 0x00FF0000 +#define BF_LRADC_DEBUG1_REQUEST(v) \ + (((v) << 16) & BM_LRADC_DEBUG1_REQUEST) +#define BP_LRADC_DEBUG1_RSRVD2 13 +#define BM_LRADC_DEBUG1_RSRVD2 0x0000E000 +#define BF_LRADC_DEBUG1_RSRVD2(v) \ + (((v) << 13) & BM_LRADC_DEBUG1_RSRVD2) +#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 +#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x00001F00 +#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) \ + (((v) << 8) & BM_LRADC_DEBUG1_TESTMODE_COUNT) +#define BP_LRADC_DEBUG1_RSRVD1 3 +#define BM_LRADC_DEBUG1_RSRVD1 0x000000F8 +#define BF_LRADC_DEBUG1_RSRVD1(v) \ + (((v) << 3) & BM_LRADC_DEBUG1_RSRVD1) +#define BM_LRADC_DEBUG1_TESTMODE6 0x00000004 +#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE5 0x00000002 +#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE 0x00000001 +#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 + +#define HW_LRADC_CONVERSION (0x00000130) +#define HW_LRADC_CONVERSION_SET (0x00000134) +#define HW_LRADC_CONVERSION_CLR (0x00000138) +#define HW_LRADC_CONVERSION_TOG (0x0000013c) + +#define BP_LRADC_CONVERSION_RSRVD3 21 +#define BM_LRADC_CONVERSION_RSRVD3 0xFFE00000 +#define BF_LRADC_CONVERSION_RSRVD3(v) \ + (((v) << 21) & BM_LRADC_CONVERSION_RSRVD3) +#define BM_LRADC_CONVERSION_AUTOMATIC 0x00100000 +#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 +#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 +#define BP_LRADC_CONVERSION_RSRVD2 18 +#define BM_LRADC_CONVERSION_RSRVD2 0x000C0000 +#define BF_LRADC_CONVERSION_RSRVD2(v) \ + (((v) << 18) & BM_LRADC_CONVERSION_RSRVD2) +#define BP_LRADC_CONVERSION_SCALE_FACTOR 16 +#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x00030000 +#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) \ + (((v) << 16) & BM_LRADC_CONVERSION_SCALE_FACTOR) +#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 +#define BP_LRADC_CONVERSION_RSRVD1 10 +#define BM_LRADC_CONVERSION_RSRVD1 0x0000FC00 +#define BF_LRADC_CONVERSION_RSRVD1(v) \ + (((v) << 10) & BM_LRADC_CONVERSION_RSRVD1) +#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 +#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x000003FF +#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) \ + (((v) << 0) & BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE) + +#define HW_LRADC_CTRL4 (0x00000140) +#define HW_LRADC_CTRL4_SET (0x00000144) +#define HW_LRADC_CTRL4_CLR (0x00000148) +#define HW_LRADC_CTRL4_TOG (0x0000014c) + +#define BP_LRADC_CTRL4_LRADC7SELECT 28 +#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 +#define BF_LRADC_CTRL4_LRADC7SELECT(v) \ + (((v) << 28) & BM_LRADC_CTRL4_LRADC7SELECT) +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC6SELECT 24 +#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 +#define BF_LRADC_CTRL4_LRADC6SELECT(v) \ + (((v) << 24) & BM_LRADC_CTRL4_LRADC6SELECT) +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC5SELECT 20 +#define BM_LRADC_CTRL4_LRADC5SELECT 0x00F00000 +#define BF_LRADC_CTRL4_LRADC5SELECT(v) \ + (((v) << 20) & BM_LRADC_CTRL4_LRADC5SELECT) +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC4SELECT 16 +#define BM_LRADC_CTRL4_LRADC4SELECT 0x000F0000 +#define BF_LRADC_CTRL4_LRADC4SELECT(v) \ + (((v) << 16) & BM_LRADC_CTRL4_LRADC4SELECT) +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC3SELECT 12 +#define BM_LRADC_CTRL4_LRADC3SELECT 0x0000F000 +#define BF_LRADC_CTRL4_LRADC3SELECT(v) \ + (((v) << 12) & BM_LRADC_CTRL4_LRADC3SELECT) +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC2SELECT 8 +#define BM_LRADC_CTRL4_LRADC2SELECT 0x00000F00 +#define BF_LRADC_CTRL4_LRADC2SELECT(v) \ + (((v) << 8) & BM_LRADC_CTRL4_LRADC2SELECT) +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC1SELECT 4 +#define BM_LRADC_CTRL4_LRADC1SELECT 0x000000F0 +#define BF_LRADC_CTRL4_LRADC1SELECT(v) \ + (((v) << 4) & BM_LRADC_CTRL4_LRADC1SELECT) +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC0SELECT 0 +#define BM_LRADC_CTRL4_LRADC0SELECT 0x0000000F +#define BF_LRADC_CTRL4_LRADC0SELECT(v) \ + (((v) << 0) & BM_LRADC_CTRL4_LRADC0SELECT) +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xF + +#define HW_LRADC_VERSION (0x00000150) + +#define BP_LRADC_VERSION_MAJOR 24 +#define BM_LRADC_VERSION_MAJOR 0xFF000000 +#define BF_LRADC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LRADC_VERSION_MAJOR) +#define BP_LRADC_VERSION_MINOR 16 +#define BM_LRADC_VERSION_MINOR 0x00FF0000 +#define BF_LRADC_VERSION_MINOR(v) \ + (((v) << 16) & BM_LRADC_VERSION_MINOR) +#define BP_LRADC_VERSION_STEP 0 +#define BM_LRADC_VERSION_STEP 0x0000FFFF +#define BF_LRADC_VERSION_STEP(v) \ + (((v) << 0) & BM_LRADC_VERSION_STEP) +#endif /* __ARCH_ARM___LRADC_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-ocotp.h b/arch/arm/mach-mx23/include/mach/regs-ocotp.h new file mode 100644 index 000000000000..b0313dd67f93 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-ocotp.h @@ -0,0 +1,311 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 5 +#define BM_OCOTP_CTRL_RSRVD0 0x000000E0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 5) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000001F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_DATA (0x00000010) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +/* + * multi-register-define name HW_OCOTP_CUSTn + * base 0x00000020 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10) +#define BP_OCOTP_CUSTn_BITS 0 +#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF +#define BF_OCOTP_CUSTn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_CRYPTOn + * base 0x00000060 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10) +#define BP_OCOTP_CRYPTOn_BITS 0 +#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF +#define BF_OCOTP_CRYPTOn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x000000A0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x00000100) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_CUSTCAP (0x00000110) + +#define BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9 0x80000000 +#define BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10 0x40000000 +#define BP_OCOTP_CUSTCAP_RSRVD1 5 +#define BM_OCOTP_CUSTCAP_RSRVD1 0x3FFFFFE0 +#define BF_OCOTP_CUSTCAP_RSRVD1(v) \ + (((v) << 5) & BM_OCOTP_CUSTCAP_RSRVD1) +#define BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE 0x00000010 +#define BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG 0x00000008 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002 +#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001 + +#define HW_OCOTP_LOCK (0x00000120) + +#define BM_OCOTP_LOCK_ROM7 0x80000000 +#define BM_OCOTP_LOCK_ROM6 0x40000000 +#define BM_OCOTP_LOCK_ROM5 0x20000000 +#define BM_OCOTP_LOCK_ROM4 0x10000000 +#define BM_OCOTP_LOCK_ROM3 0x08000000 +#define BM_OCOTP_LOCK_ROM2 0x04000000 +#define BM_OCOTP_LOCK_ROM1 0x02000000 +#define BM_OCOTP_LOCK_ROM0 0x01000000 +#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000 +#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000 +#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000 +#define BM_OCOTP_LOCK_PIN 0x00100000 +#define BM_OCOTP_LOCK_OPS 0x00080000 +#define BM_OCOTP_LOCK_UN2 0x00040000 +#define BM_OCOTP_LOCK_UN1 0x00020000 +#define BM_OCOTP_LOCK_UN0 0x00010000 +#define BP_OCOTP_LOCK_UNALLOCATED 11 +#define BM_OCOTP_LOCK_UNALLOCATED 0x0000F800 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 11) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400 +#define BM_OCOTP_LOCK_CUSTCAP 0x00000200 +#define BM_OCOTP_LOCK_HWSW 0x00000100 +#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020 +#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010 +#define BM_OCOTP_LOCK_CUST3 0x00000008 +#define BM_OCOTP_LOCK_CUST2 0x00000004 +#define BM_OCOTP_LOCK_CUST1 0x00000002 +#define BM_OCOTP_LOCK_CUST0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_OPSn + * base 0x00000130 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_OPSn_BITS 0 +#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF +#define BF_OCOTP_OPSn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_UNn + * base 0x00000170 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10) +#define BP_OCOTP_UNn_BITS 0 +#define BM_OCOTP_UNn_BITS 0xFFFFFFFF +#define BF_OCOTP_UNn_BITS(v) (v) + +#define HW_OCOTP_ROM0 (0x000001a0) + +#define BP_OCOTP_ROM0_BOOT_MODE 24 +#define BM_OCOTP_ROM0_BOOT_MODE 0xFF000000 +#define BF_OCOTP_ROM0_BOOT_MODE(v) \ + (((v) << 24) & BM_OCOTP_ROM0_BOOT_MODE) +#define BM_OCOTP_ROM0_ENABLE_PJTAG_12MA_DRIVE 0x00800000 +#define BM_OCOTP_ROM0_USE_PARALLEL_JTAG 0x00400000 +#define BP_OCOTP_ROM0_SD_POWER_GATE_GPIO 20 +#define BM_OCOTP_ROM0_SD_POWER_GATE_GPIO 0x00300000 +#define BF_OCOTP_ROM0_SD_POWER_GATE_GPIO(v) \ + (((v) << 20) & BM_OCOTP_ROM0_SD_POWER_GATE_GPIO) +#define BP_OCOTP_ROM0_SD_POWER_UP_DELAY 14 +#define BM_OCOTP_ROM0_SD_POWER_UP_DELAY 0x000FC000 +#define BF_OCOTP_ROM0_SD_POWER_UP_DELAY(v) \ + (((v) << 14) & BM_OCOTP_ROM0_SD_POWER_UP_DELAY) +#define BP_OCOTP_ROM0_SD_BUS_WIDTH 12 +#define BM_OCOTP_ROM0_SD_BUS_WIDTH 0x00003000 +#define BF_OCOTP_ROM0_SD_BUS_WIDTH(v) \ + (((v) << 12) & BM_OCOTP_ROM0_SD_BUS_WIDTH) +#define BP_OCOTP_ROM0_SSP_SCK_INDEX 8 +#define BM_OCOTP_ROM0_SSP_SCK_INDEX 0x00000F00 +#define BF_OCOTP_ROM0_SSP_SCK_INDEX(v) \ + (((v) << 8) & BM_OCOTP_ROM0_SSP_SCK_INDEX) +#define BM_OCOTP_ROM0_RSRVD3 0x00000080 +#define BM_OCOTP_ROM0_DISABLE_SPI_NOR_FAST_ READ 0x00000040 +#define BM_OCOTP_ROM0_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020 +#define BM_OCOTP_ROM0_ENABLE_UNENCRYPTED_ BOOT 0x00000010 +#define BM_OCOTP_ROM0_SD_MBR_BOOT 0x00000008 +#define BM_OCOTP_ROM0_RSRVD2 0x00000004 +#define BM_OCOTP_ROM0_RSRVD1 0x00000002 +#define BM_OCOTP_ROM0_RSRVD0 0x00000001 + +#define HW_OCOTP_ROM1 (0x000001b0) + +#define BP_OCOTP_ROM1_RSRVD1 30 +#define BM_OCOTP_ROM1_RSRVD1 0xC0000000 +#define BF_OCOTP_ROM1_RSRVD1(v) \ + (((v) << 30) & BM_OCOTP_ROM1_RSRVD1) +#define BP_OCOTP_ROM1_USE_ALT_GPMI_RDY3 28 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_RDY3 0x30000000 +#define BF_OCOTP_ROM1_USE_ALT_GPMI_RDY3(v) \ + (((v) << 28) & BM_OCOTP_ROM1_USE_ALT_GPMI_RDY3) +#define BP_OCOTP_ROM1_USE_ALT_GPMI_CE3 26 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_CE3 0x0C000000 +#define BF_OCOTP_ROM1_USE_ALT_GPMI_CE3(v) \ + (((v) << 26) & BM_OCOTP_ROM1_USE_ALT_GPMI_CE3) +#define BM_OCOTP_ROM1_USE_ALT_GPMI_RDY2 0x02000000 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_CE2 0x01000000 +#define BM_OCOTP_ROM1_ENABLE_NAND3_CE_RDY_PULLUP 0x00800000 +#define BM_OCOTP_ROM1_ENABLE_NAND2_CE_RDY_PULLUP 0x00400000 +#define BM_OCOTP_ROM1_ENABLE_NAND1_CE_RDY_PULLUP 0x00200000 +#define BM_OCOTP_ROM1_ENABLE_NAND0_CE_RDY_PULLUP 0x00100000 +#define BM_OCOTP_ROM1_UNTOUCH_INTERNAL_SSP_PULLUP 0x00080000 +#define BM_OCOTP_ROM1_SSP2_EXT_PULLUP 0x00040000 +#define BM_OCOTP_ROM1_SSP1_EXT_PULLUP 0x00020000 +#define BM_OCOTP_ROM1_SD_INCREASE_INIT_SEQ_TIME 0x00010000 +#define BM_OCOTP_ROM1_SD_INIT_SEQ_2_ENABLE 0x00008000 +#define BM_OCOTP_ROM1_SD_CMD0_DISABLE 0x00004000 +#define BM_OCOTP_ROM1_SD_INIT_SEQ_1_DISABLE 0x00002000 +#define BM_OCOTP_ROM1_USE_ALT_SSP1_DATA4_7 0x00001000 +#define BP_OCOTP_ROM1_BOOT_SEARCH_COUNT 8 +#define BM_OCOTP_ROM1_BOOT_SEARCH_COUNT 0x00000F00 +#define BF_OCOTP_ROM1_BOOT_SEARCH_COUNT(v) \ + (((v) << 8) & BM_OCOTP_ROM1_BOOT_SEARCH_COUNT) +#define BP_OCOTP_ROM1_RSRVD0 3 +#define BM_OCOTP_ROM1_RSRVD0 0x000000F8 +#define BF_OCOTP_ROM1_RSRVD0(v) \ + (((v) << 3) & BM_OCOTP_ROM1_RSRVD0) +#define BP_OCOTP_ROM1_NUMBER_OF_NANDS 0 +#define BM_OCOTP_ROM1_NUMBER_OF_NANDS 0x00000007 +#define BF_OCOTP_ROM1_NUMBER_OF_NANDS(v) \ + (((v) << 0) & BM_OCOTP_ROM1_NUMBER_OF_NANDS) + +#define HW_OCOTP_ROM2 (0x000001c0) + +#define BP_OCOTP_ROM2_USB_VID 16 +#define BM_OCOTP_ROM2_USB_VID 0xFFFF0000 +#define BF_OCOTP_ROM2_USB_VID(v) \ + (((v) << 16) & BM_OCOTP_ROM2_USB_VID) +#define BP_OCOTP_ROM2_USB_PID 0 +#define BM_OCOTP_ROM2_USB_PID 0x0000FFFF +#define BF_OCOTP_ROM2_USB_PID(v) \ + (((v) << 0) & BM_OCOTP_ROM2_USB_PID) + +#define HW_OCOTP_ROM3 (0x000001d0) + +#define BP_OCOTP_ROM3_RSRVD1 10 +#define BM_OCOTP_ROM3_RSRVD1 0xFFFFFC00 +#define BF_OCOTP_ROM3_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_ROM3_RSRVD1) +#define BP_OCOTP_ROM3_RSRVD0 0 +#define BM_OCOTP_ROM3_RSRVD0 0x000003FF +#define BF_OCOTP_ROM3_RSRVD0(v) \ + (((v) << 0) & BM_OCOTP_ROM3_RSRVD0) + +#define HW_OCOTP_ROM4 (0x000001e0) + +#define BP_OCOTP_ROM4_BITS 0 +#define BM_OCOTP_ROM4_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM4_BITS(v) (v) + +#define HW_OCOTP_ROM5 (0x000001f0) + +#define BP_OCOTP_ROM5_BITS 0 +#define BM_OCOTP_ROM5_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM5_BITS(v) (v) + +#define HW_OCOTP_ROM6 (0x00000200) + +#define BP_OCOTP_ROM6_BITS 0 +#define BM_OCOTP_ROM6_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM6_BITS(v) (v) + +#define HW_OCOTP_ROM7 (0x00000210) + +#define BP_OCOTP_ROM7_BITS 0 +#define BM_OCOTP_ROM7_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM7_BITS(v) (v) + +#define HW_OCOTP_VERSION (0x00000220) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-power.h b/arch/arm/mach-mx23/include/mach/regs-power.h new file mode 100644 index 000000000000..5b74943254bb --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-power.h @@ -0,0 +1,564 @@ +/* + * Freescale POWER Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___POWER_H +#define __ARCH_ARM___POWER_H + +#include + +#define REGS_POWER_BASE IO_ADDRESS(POWER_PHYS_ADDR) +#define REGS_POWER_PHYS (0x80044000) +#define REGS_POWER_SIZE 0x00002000 + +#define HW_POWER_CTRL (0x00000000) +#define HW_POWER_CTRL_SET (0x00000004) +#define HW_POWER_CTRL_CLR (0x00000008) +#define HW_POWER_CTRL_TOG (0x0000000c) + +#define BM_POWER_CTRL_RSRVD3 0x80000000 +#define BM_POWER_CTRL_CLKGATE 0x40000000 +#define BP_POWER_CTRL_RSRVD2 28 +#define BM_POWER_CTRL_RSRVD2 0x30000000 +#define BF_POWER_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_POWER_CTRL_RSRVD2) +#define BM_POWER_CTRL_PSWITCH_MID_TRAN 0x08000000 +#define BP_POWER_CTRL_RSRVD1 25 +#define BM_POWER_CTRL_RSRVD1 0x06000000 +#define BF_POWER_CTRL_RSRVD1(v) \ + (((v) << 25) & BM_POWER_CTRL_RSRVD1) +#define BM_POWER_CTRL_DCDC4P2_BO_IRQ 0x01000000 +#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO 0x00800000 +#define BM_POWER_CTRL_VDD5V_DROOP_IRQ 0x00400000 +#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP 0x00200000 +#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 +#define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x00080000 +#define BM_POWER_CTRL_POLARITY_PSWITCH 0x00040000 +#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 +#define BM_POWER_CTRL_POLARITY_DC_OK 0x00010000 +#define BM_POWER_CTRL_DC_OK_IRQ 0x00008000 +#define BM_POWER_CTRL_ENIRQ_DC_OK 0x00004000 +#define BM_POWER_CTRL_BATT_BO_IRQ 0x00002000 +#define BM_POWER_CTRL_ENIRQBATT_BO 0x00001000 +#define BM_POWER_CTRL_VDDIO_BO_IRQ 0x00000800 +#define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x00000400 +#define BM_POWER_CTRL_VDDA_BO_IRQ 0x00000200 +#define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x00000100 +#define BM_POWER_CTRL_VDDD_BO_IRQ 0x00000080 +#define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x00000040 +#define BM_POWER_CTRL_POLARITY_VBUSVALID 0x00000020 +#define BM_POWER_CTRL_VBUSVALID_IRQ 0x00000010 +#define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x00000008 +#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x00000004 +#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x00000002 +#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 + +#define HW_POWER_5VCTRL (0x00000010) +#define HW_POWER_5VCTRL_SET (0x00000014) +#define HW_POWER_5VCTRL_CLR (0x00000018) +#define HW_POWER_5VCTRL_TOG (0x0000001c) + +#define BP_POWER_5VCTRL_RSRVD6 30 +#define BM_POWER_5VCTRL_RSRVD6 0xC0000000 +#define BF_POWER_5VCTRL_RSRVD6(v) \ + (((v) << 30) & BM_POWER_5VCTRL_RSRVD6) +#define BP_POWER_5VCTRL_VBUSDROOP_TRSH 28 +#define BM_POWER_5VCTRL_VBUSDROOP_TRSH 0x30000000 +#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v) \ + (((v) << 28) & BM_POWER_5VCTRL_VBUSDROOP_TRSH) +#define BM_POWER_5VCTRL_RSRVD5 0x08000000 +#define BP_POWER_5VCTRL_HEADROOM_ADJ 24 +#define BM_POWER_5VCTRL_HEADROOM_ADJ 0x07000000 +#define BF_POWER_5VCTRL_HEADROOM_ADJ(v) \ + (((v) << 24) & BM_POWER_5VCTRL_HEADROOM_ADJ) +#define BP_POWER_5VCTRL_RSRVD4 21 +#define BM_POWER_5VCTRL_RSRVD4 0x00E00000 +#define BF_POWER_5VCTRL_RSRVD4(v) \ + (((v) << 21) & BM_POWER_5VCTRL_RSRVD4) +#define BM_POWER_5VCTRL_PWD_CHARGE_4P2 0x00100000 +#define BP_POWER_5VCTRL_RSRVD3 18 +#define BM_POWER_5VCTRL_RSRVD3 0x000C0000 +#define BF_POWER_5VCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_5VCTRL_RSRVD3) +#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT 12 +#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT 0x0003F000 +#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v) \ + (((v) << 12) & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) +#define BM_POWER_5VCTRL_RSRVD2 0x00000800 +#define BP_POWER_5VCTRL_VBUSVALID_TRSH 8 +#define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x00000700 +#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) \ + (((v) << 8) & BM_POWER_5VCTRL_VBUSVALID_TRSH) +#define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x00000080 +#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 +#define BM_POWER_5VCTRL_DCDC_XFER 0x00000020 +#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x00000010 +#define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x00000008 +#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x00000004 +#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS 0x00000002 +#define BM_POWER_5VCTRL_ENABLE_DCDC 0x00000001 + +#define HW_POWER_MINPWR (0x00000020) +#define HW_POWER_MINPWR_SET (0x00000024) +#define HW_POWER_MINPWR_CLR (0x00000028) +#define HW_POWER_MINPWR_TOG (0x0000002c) + +#define BP_POWER_MINPWR_RSRVD1 15 +#define BM_POWER_MINPWR_RSRVD1 0xFFFF8000 +#define BF_POWER_MINPWR_RSRVD1(v) \ + (((v) << 15) & BM_POWER_MINPWR_RSRVD1) +#define BM_POWER_MINPWR_LOWPWR_4P2 0x00004000 +#define BM_POWER_MINPWR_VDAC_DUMP_CTRL 0x00002000 +#define BM_POWER_MINPWR_PWD_BO 0x00001000 +#define BM_POWER_MINPWR_USE_VDDXTAL_VBG 0x00000800 +#define BM_POWER_MINPWR_PWD_ANA_CMPS 0x00000400 +#define BM_POWER_MINPWR_ENABLE_OSC 0x00000200 +#define BM_POWER_MINPWR_SELECT_OSC 0x00000100 +#define BM_POWER_MINPWR_VBG_OFF 0x00000080 +#define BM_POWER_MINPWR_DOUBLE_FETS 0x00000040 +#define BM_POWER_MINPWR_HALF_FETS 0x00000020 +#define BM_POWER_MINPWR_LESSANA_I 0x00000010 +#define BM_POWER_MINPWR_PWD_XTAL24 0x00000008 +#define BM_POWER_MINPWR_DC_STOPCLK 0x00000004 +#define BM_POWER_MINPWR_EN_DC_PFM 0x00000002 +#define BM_POWER_MINPWR_DC_HALFCLK 0x00000001 + +#define HW_POWER_CHARGE (0x00000030) +#define HW_POWER_CHARGE_SET (0x00000034) +#define HW_POWER_CHARGE_CLR (0x00000038) +#define HW_POWER_CHARGE_TOG (0x0000003c) + +#define BP_POWER_CHARGE_RSRVD4 27 +#define BM_POWER_CHARGE_RSRVD4 0xF8000000 +#define BF_POWER_CHARGE_RSRVD4(v) \ + (((v) << 27) & BM_POWER_CHARGE_RSRVD4) +#define BP_POWER_CHARGE_ADJ_VOLT 24 +#define BM_POWER_CHARGE_ADJ_VOLT 0x07000000 +#define BF_POWER_CHARGE_ADJ_VOLT(v) \ + (((v) << 24) & BM_POWER_CHARGE_ADJ_VOLT) +#define BM_POWER_CHARGE_RSRVD3 0x00800000 +#define BM_POWER_CHARGE_ENABLE_LOAD 0x00400000 +#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS 0x00200000 +#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x00100000 +#define BM_POWER_CHARGE_CHRG_STS_OFF 0x00080000 +#define BM_POWER_CHARGE_LIION_4P1 0x00040000 +#define BM_POWER_CHARGE_USE_EXTERN_R 0x00020000 +#define BM_POWER_CHARGE_PWD_BATTCHRG 0x00010000 +#define BP_POWER_CHARGE_RSRVD2 12 +#define BM_POWER_CHARGE_RSRVD2 0x0000F000 +#define BF_POWER_CHARGE_RSRVD2(v) \ + (((v) << 12) & BM_POWER_CHARGE_RSRVD2) +#define BP_POWER_CHARGE_STOP_ILIMIT 8 +#define BM_POWER_CHARGE_STOP_ILIMIT 0x00000F00 +#define BF_POWER_CHARGE_STOP_ILIMIT(v) \ + (((v) << 8) & BM_POWER_CHARGE_STOP_ILIMIT) +#define BP_POWER_CHARGE_RSRVD1 6 +#define BM_POWER_CHARGE_RSRVD1 0x000000C0 +#define BF_POWER_CHARGE_RSRVD1(v) \ + (((v) << 6) & BM_POWER_CHARGE_RSRVD1) +#define BP_POWER_CHARGE_BATTCHRG_I 0 +#define BM_POWER_CHARGE_BATTCHRG_I 0x0000003F +#define BF_POWER_CHARGE_BATTCHRG_I(v) \ + (((v) << 0) & BM_POWER_CHARGE_BATTCHRG_I) + +#define HW_POWER_VDDDCTRL (0x00000040) + +#define BP_POWER_VDDDCTRL_ADJTN 28 +#define BM_POWER_VDDDCTRL_ADJTN 0xF0000000 +#define BF_POWER_VDDDCTRL_ADJTN(v) \ + (((v) << 28) & BM_POWER_VDDDCTRL_ADJTN) +#define BP_POWER_VDDDCTRL_RSRVD4 24 +#define BM_POWER_VDDDCTRL_RSRVD4 0x0F000000 +#define BF_POWER_VDDDCTRL_RSRVD4(v) \ + (((v) << 24) & BM_POWER_VDDDCTRL_RSRVD4) +#define BM_POWER_VDDDCTRL_PWDN_BRNOUT 0x00800000 +#define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x00400000 +#define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x00200000 +#define BM_POWER_VDDDCTRL_DISABLE_FET 0x00100000 +#define BP_POWER_VDDDCTRL_RSRVD3 18 +#define BM_POWER_VDDDCTRL_RSRVD3 0x000C0000 +#define BF_POWER_VDDDCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_VDDDCTRL_RSRVD3) +#define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 +#define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x00030000 +#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) \ + (((v) << 16) & BM_POWER_VDDDCTRL_LINREG_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD2 11 +#define BM_POWER_VDDDCTRL_RSRVD2 0x0000F800 +#define BF_POWER_VDDDCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDDCTRL_RSRVD2) +#define BP_POWER_VDDDCTRL_BO_OFFSET 8 +#define BM_POWER_VDDDCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDDCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDDCTRL_BO_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD1 5 +#define BM_POWER_VDDDCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDDCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDDCTRL_RSRVD1) +#define BP_POWER_VDDDCTRL_TRG 0 +#define BM_POWER_VDDDCTRL_TRG 0x0000001F +#define BF_POWER_VDDDCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDDCTRL_TRG) + +#define HW_POWER_VDDACTRL (0x00000050) + +#define BP_POWER_VDDACTRL_RSRVD4 20 +#define BM_POWER_VDDACTRL_RSRVD4 0xFFF00000 +#define BF_POWER_VDDACTRL_RSRVD4(v) \ + (((v) << 20) & BM_POWER_VDDACTRL_RSRVD4) +#define BM_POWER_VDDACTRL_PWDN_BRNOUT 0x00080000 +#define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x00040000 +#define BM_POWER_VDDACTRL_ENABLE_LINREG 0x00020000 +#define BM_POWER_VDDACTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDACTRL_RSRVD3 14 +#define BM_POWER_VDDACTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDACTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDACTRL_RSRVD3) +#define BP_POWER_VDDACTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDACTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDACTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDACTRL_LINREG_OFFSET) +#define BM_POWER_VDDACTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDACTRL_BO_OFFSET 8 +#define BM_POWER_VDDACTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDACTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDACTRL_BO_OFFSET) +#define BP_POWER_VDDACTRL_RSRVD1 5 +#define BM_POWER_VDDACTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDACTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDACTRL_RSRVD1) +#define BP_POWER_VDDACTRL_TRG 0 +#define BM_POWER_VDDACTRL_TRG 0x0000001F +#define BF_POWER_VDDACTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDACTRL_TRG) + +#define HW_POWER_VDDIOCTRL (0x00000060) + +#define BP_POWER_VDDIOCTRL_RSRVD5 24 +#define BM_POWER_VDDIOCTRL_RSRVD5 0xFF000000 +#define BF_POWER_VDDIOCTRL_RSRVD5(v) \ + (((v) << 24) & BM_POWER_VDDIOCTRL_RSRVD5) +#define BP_POWER_VDDIOCTRL_ADJTN 20 +#define BM_POWER_VDDIOCTRL_ADJTN 0x00F00000 +#define BF_POWER_VDDIOCTRL_ADJTN(v) \ + (((v) << 20) & BM_POWER_VDDIOCTRL_ADJTN) +#define BM_POWER_VDDIOCTRL_RSRVD4 0x00080000 +#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT 0x00040000 +#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x00020000 +#define BM_POWER_VDDIOCTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDIOCTRL_RSRVD3 14 +#define BM_POWER_VDDIOCTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDIOCTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDIOCTRL_RSRVD3) +#define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDIOCTRL_LINREG_OFFSET) +#define BM_POWER_VDDIOCTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDIOCTRL_BO_OFFSET 8 +#define BM_POWER_VDDIOCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDIOCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDIOCTRL_BO_OFFSET) +#define BP_POWER_VDDIOCTRL_RSRVD1 5 +#define BM_POWER_VDDIOCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDIOCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDIOCTRL_RSRVD1) +#define BP_POWER_VDDIOCTRL_TRG 0 +#define BM_POWER_VDDIOCTRL_TRG 0x0000001F +#define BF_POWER_VDDIOCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDIOCTRL_TRG) + +#define HW_POWER_VDDMEMCTRL (0x00000070) + +#define BP_POWER_VDDMEMCTRL_RSRVD2 11 +#define BM_POWER_VDDMEMCTRL_RSRVD2 0xFFFFF800 +#define BF_POWER_VDDMEMCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDMEMCTRL_RSRVD2) +#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 0x00000400 +#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT 0x00000200 +#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG 0x00000100 +#define BP_POWER_VDDMEMCTRL_RSRVD1 5 +#define BM_POWER_VDDMEMCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDMEMCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDMEMCTRL_RSRVD1) +#define BP_POWER_VDDMEMCTRL_TRG 0 +#define BM_POWER_VDDMEMCTRL_TRG 0x0000001F +#define BF_POWER_VDDMEMCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDMEMCTRL_TRG) + +#define HW_POWER_DCDC4P2 (0x00000080) + +#define BP_POWER_DCDC4P2_DROPOUT_CTRL 28 +#define BM_POWER_DCDC4P2_DROPOUT_CTRL 0xF0000000 +#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v) \ + (((v) << 28) & BM_POWER_DCDC4P2_DROPOUT_CTRL) +#define BP_POWER_DCDC4P2_RSRVD5 26 +#define BM_POWER_DCDC4P2_RSRVD5 0x0C000000 +#define BF_POWER_DCDC4P2_RSRVD5(v) \ + (((v) << 26) & BM_POWER_DCDC4P2_RSRVD5) +#define BP_POWER_DCDC4P2_ISTEAL_THRESH 24 +#define BM_POWER_DCDC4P2_ISTEAL_THRESH 0x03000000 +#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v) \ + (((v) << 24) & BM_POWER_DCDC4P2_ISTEAL_THRESH) +#define BM_POWER_DCDC4P2_ENABLE_4P2 0x00800000 +#define BM_POWER_DCDC4P2_ENABLE_DCDC 0x00400000 +#define BM_POWER_DCDC4P2_HYST_DIR 0x00200000 +#define BM_POWER_DCDC4P2_HYST_THRESH 0x00100000 +#define BM_POWER_DCDC4P2_RSRVD3 0x00080000 +#define BP_POWER_DCDC4P2_TRG 16 +#define BM_POWER_DCDC4P2_TRG 0x00070000 +#define BF_POWER_DCDC4P2_TRG(v) \ + (((v) << 16) & BM_POWER_DCDC4P2_TRG) +#define BP_POWER_DCDC4P2_RSRVD2 13 +#define BM_POWER_DCDC4P2_RSRVD2 0x0000E000 +#define BF_POWER_DCDC4P2_RSRVD2(v) \ + (((v) << 13) & BM_POWER_DCDC4P2_RSRVD2) +#define BP_POWER_DCDC4P2_BO 8 +#define BM_POWER_DCDC4P2_BO 0x00001F00 +#define BF_POWER_DCDC4P2_BO(v) \ + (((v) << 8) & BM_POWER_DCDC4P2_BO) +#define BP_POWER_DCDC4P2_RSRVD1 5 +#define BM_POWER_DCDC4P2_RSRVD1 0x000000E0 +#define BF_POWER_DCDC4P2_RSRVD1(v) \ + (((v) << 5) & BM_POWER_DCDC4P2_RSRVD1) +#define BP_POWER_DCDC4P2_CMPTRIP 0 +#define BM_POWER_DCDC4P2_CMPTRIP 0x0000001F +#define BF_POWER_DCDC4P2_CMPTRIP(v) \ + (((v) << 0) & BM_POWER_DCDC4P2_CMPTRIP) + +#define HW_POWER_MISC (0x00000090) + +#define BP_POWER_MISC_RSRVD2 7 +#define BM_POWER_MISC_RSRVD2 0xFFFFFF80 +#define BF_POWER_MISC_RSRVD2(v) \ + (((v) << 7) & BM_POWER_MISC_RSRVD2) +#define BP_POWER_MISC_FREQSEL 4 +#define BM_POWER_MISC_FREQSEL 0x00000070 +#define BF_POWER_MISC_FREQSEL(v) \ + (((v) << 4) & BM_POWER_MISC_FREQSEL) +#define BM_POWER_MISC_RSRVD1 0x00000008 +#define BM_POWER_MISC_DELAY_TIMING 0x00000004 +#define BM_POWER_MISC_TEST 0x00000002 +#define BM_POWER_MISC_SEL_PLLCLK 0x00000001 + +#define HW_POWER_DCLIMITS (0x000000a0) + +#define BP_POWER_DCLIMITS_RSRVD3 16 +#define BM_POWER_DCLIMITS_RSRVD3 0xFFFF0000 +#define BF_POWER_DCLIMITS_RSRVD3(v) \ + (((v) << 16) & BM_POWER_DCLIMITS_RSRVD3) +#define BM_POWER_DCLIMITS_RSRVD2 0x00008000 +#define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 +#define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x00007F00 +#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) \ + (((v) << 8) & BM_POWER_DCLIMITS_POSLIMIT_BUCK) +#define BM_POWER_DCLIMITS_RSRVD1 0x00000080 +#define BP_POWER_DCLIMITS_NEGLIMIT 0 +#define BM_POWER_DCLIMITS_NEGLIMIT 0x0000007F +#define BF_POWER_DCLIMITS_NEGLIMIT(v) \ + (((v) << 0) & BM_POWER_DCLIMITS_NEGLIMIT) + +#define HW_POWER_LOOPCTRL (0x000000b0) +#define HW_POWER_LOOPCTRL_SET (0x000000b4) +#define HW_POWER_LOOPCTRL_CLR (0x000000b8) +#define HW_POWER_LOOPCTRL_TOG (0x000000bc) + +#define BP_POWER_LOOPCTRL_RSRVD3 21 +#define BM_POWER_LOOPCTRL_RSRVD3 0xFFE00000 +#define BF_POWER_LOOPCTRL_RSRVD3(v) \ + (((v) << 21) & BM_POWER_LOOPCTRL_RSRVD3) +#define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x00100000 +#define BM_POWER_LOOPCTRL_HYST_SIGN 0x00080000 +#define BM_POWER_LOOPCTRL_EN_CM_HYST 0x00040000 +#define BM_POWER_LOOPCTRL_EN_DF_HYST 0x00020000 +#define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x00010000 +#define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x00008000 +#define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x00004000 +#define BP_POWER_LOOPCTRL_EN_RCSCALE 12 +#define BM_POWER_LOOPCTRL_EN_RCSCALE 0x00003000 +#define BF_POWER_LOOPCTRL_EN_RCSCALE(v) \ + (((v) << 12) & BM_POWER_LOOPCTRL_EN_RCSCALE) +#define BM_POWER_LOOPCTRL_RSRVD2 0x00000800 +#define BP_POWER_LOOPCTRL_DC_FF 8 +#define BM_POWER_LOOPCTRL_DC_FF 0x00000700 +#define BF_POWER_LOOPCTRL_DC_FF(v) \ + (((v) << 8) & BM_POWER_LOOPCTRL_DC_FF) +#define BP_POWER_LOOPCTRL_DC_R 4 +#define BM_POWER_LOOPCTRL_DC_R 0x000000F0 +#define BF_POWER_LOOPCTRL_DC_R(v) \ + (((v) << 4) & BM_POWER_LOOPCTRL_DC_R) +#define BP_POWER_LOOPCTRL_RSRVD1 2 +#define BM_POWER_LOOPCTRL_RSRVD1 0x0000000C +#define BF_POWER_LOOPCTRL_RSRVD1(v) \ + (((v) << 2) & BM_POWER_LOOPCTRL_RSRVD1) +#define BP_POWER_LOOPCTRL_DC_C 0 +#define BM_POWER_LOOPCTRL_DC_C 0x00000003 +#define BF_POWER_LOOPCTRL_DC_C(v) \ + (((v) << 0) & BM_POWER_LOOPCTRL_DC_C) + +#define HW_POWER_STS (0x000000c0) + +#define BP_POWER_STS_RSRVD3 30 +#define BM_POWER_STS_RSRVD3 0xC0000000 +#define BF_POWER_STS_RSRVD3(v) \ + (((v) << 30) & BM_POWER_STS_RSRVD3) +#define BP_POWER_STS_PWRUP_SOURCE 24 +#define BM_POWER_STS_PWRUP_SOURCE 0x3F000000 +#define BF_POWER_STS_PWRUP_SOURCE(v) \ + (((v) << 24) & BM_POWER_STS_PWRUP_SOURCE) +#define BP_POWER_STS_RSRVD2 22 +#define BM_POWER_STS_RSRVD2 0x00C00000 +#define BF_POWER_STS_RSRVD2(v) \ + (((v) << 22) & BM_POWER_STS_RSRVD2) +#define BP_POWER_STS_PSWITCH 20 +#define BM_POWER_STS_PSWITCH 0x00300000 +#define BF_POWER_STS_PSWITCH(v) \ + (((v) << 20) & BM_POWER_STS_PSWITCH) +#define BP_POWER_STS_RSRVD1 18 +#define BM_POWER_STS_RSRVD1 0x000C0000 +#define BF_POWER_STS_RSRVD1(v) \ + (((v) << 18) & BM_POWER_STS_RSRVD1) +#define BM_POWER_STS_AVALID_STATUS 0x00020000 +#define BM_POWER_STS_BVALID_STATUS 0x00010000 +#define BM_POWER_STS_VBUSVALID_STATUS 0x00008000 +#define BM_POWER_STS_SESSEND_STATUS 0x00004000 +#define BM_POWER_STS_BATT_BO 0x00002000 +#define BM_POWER_STS_VDD5V_FAULT 0x00001000 +#define BM_POWER_STS_CHRGSTS 0x00000800 +#define BM_POWER_STS_DCDC_4P2_BO 0x00000400 +#define BM_POWER_STS_DC_OK 0x00000200 +#define BM_POWER_STS_VDDIO_BO 0x00000100 +#define BM_POWER_STS_VDDA_BO 0x00000080 +#define BM_POWER_STS_VDDD_BO 0x00000040 +#define BM_POWER_STS_VDD5V_GT_VDDIO 0x00000020 +#define BM_POWER_STS_VDD5V_DROOP 0x00000010 +#define BM_POWER_STS_AVALID 0x00000008 +#define BM_POWER_STS_BVALID 0x00000004 +#define BM_POWER_STS_VBUSVALID 0x00000002 +#define BM_POWER_STS_SESSEND 0x00000001 + +#define HW_POWER_SPEED (0x000000d0) +#define HW_POWER_SPEED_SET (0x000000d4) +#define HW_POWER_SPEED_CLR (0x000000d8) +#define HW_POWER_SPEED_TOG (0x000000dc) + +#define BP_POWER_SPEED_RSRVD1 24 +#define BM_POWER_SPEED_RSRVD1 0xFF000000 +#define BF_POWER_SPEED_RSRVD1(v) \ + (((v) << 24) & BM_POWER_SPEED_RSRVD1) +#define BP_POWER_SPEED_STATUS 16 +#define BM_POWER_SPEED_STATUS 0x00FF0000 +#define BF_POWER_SPEED_STATUS(v) \ + (((v) << 16) & BM_POWER_SPEED_STATUS) +#define BP_POWER_SPEED_RSRVD0 2 +#define BM_POWER_SPEED_RSRVD0 0x0000FFFC +#define BF_POWER_SPEED_RSRVD0(v) \ + (((v) << 2) & BM_POWER_SPEED_RSRVD0) +#define BP_POWER_SPEED_CTRL 0 +#define BM_POWER_SPEED_CTRL 0x00000003 +#define BF_POWER_SPEED_CTRL(v) \ + (((v) << 0) & BM_POWER_SPEED_CTRL) + +#define HW_POWER_BATTMONITOR (0x000000e0) + +#define BP_POWER_BATTMONITOR_RSRVD3 26 +#define BM_POWER_BATTMONITOR_RSRVD3 0xFC000000 +#define BF_POWER_BATTMONITOR_RSRVD3(v) \ + (((v) << 26) & BM_POWER_BATTMONITOR_RSRVD3) +#define BP_POWER_BATTMONITOR_BATT_VAL 16 +#define BM_POWER_BATTMONITOR_BATT_VAL 0x03FF0000 +#define BF_POWER_BATTMONITOR_BATT_VAL(v) \ + (((v) << 16) & BM_POWER_BATTMONITOR_BATT_VAL) +#define BP_POWER_BATTMONITOR_RSRVD2 11 +#define BM_POWER_BATTMONITOR_RSRVD2 0x0000F800 +#define BF_POWER_BATTMONITOR_RSRVD2(v) \ + (((v) << 11) & BM_POWER_BATTMONITOR_RSRVD2) +#define BM_POWER_BATTMONITOR_EN_BATADJ 0x00000400 +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x00000200 +#define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x00000100 +#define BP_POWER_BATTMONITOR_RSRVD1 5 +#define BM_POWER_BATTMONITOR_RSRVD1 0x000000E0 +#define BF_POWER_BATTMONITOR_RSRVD1(v) \ + (((v) << 5) & BM_POWER_BATTMONITOR_RSRVD1) +#define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 +#define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0x0000001F +#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) \ + (((v) << 0) & BM_POWER_BATTMONITOR_BRWNOUT_LVL) + +#define HW_POWER_RESET (0x00000100) +#define HW_POWER_RESET_SET (0x00000104) +#define HW_POWER_RESET_CLR (0x00000108) +#define HW_POWER_RESET_TOG (0x0000010c) + +#define BP_POWER_RESET_UNLOCK 16 +#define BM_POWER_RESET_UNLOCK 0xFFFF0000 +#define BF_POWER_RESET_UNLOCK(v) \ + (((v) << 16) & BM_POWER_RESET_UNLOCK) +#define BV_POWER_RESET_UNLOCK__KEY 0x3E77 +#define BP_POWER_RESET_RSRVD1 2 +#define BM_POWER_RESET_RSRVD1 0x0000FFFC +#define BF_POWER_RESET_RSRVD1(v) \ + (((v) << 2) & BM_POWER_RESET_RSRVD1) +#define BM_POWER_RESET_PWD_OFF 0x00000002 +#define BM_POWER_RESET_PWD 0x00000001 + +#define HW_POWER_DEBUG (0x00000110) +#define HW_POWER_DEBUG_SET (0x00000114) +#define HW_POWER_DEBUG_CLR (0x00000118) +#define HW_POWER_DEBUG_TOG (0x0000011c) + +#define BP_POWER_DEBUG_RSRVD0 4 +#define BM_POWER_DEBUG_RSRVD0 0xFFFFFFF0 +#define BF_POWER_DEBUG_RSRVD0(v) \ + (((v) << 4) & BM_POWER_DEBUG_RSRVD0) +#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 +#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +#define BM_POWER_DEBUG_SESSENDPIOLOCK 0x00000001 + +#define HW_POWER_SPECIAL (0x00000120) +#define HW_POWER_SPECIAL_SET (0x00000124) +#define HW_POWER_SPECIAL_CLR (0x00000128) +#define HW_POWER_SPECIAL_TOG (0x0000012c) + +#define BP_POWER_SPECIAL_TEST 0 +#define BM_POWER_SPECIAL_TEST 0xFFFFFFFF +#define BF_POWER_SPECIAL_TEST(v) (v) + +#define HW_POWER_VERSION (0x00000130) + +#define BP_POWER_VERSION_MAJOR 24 +#define BM_POWER_VERSION_MAJOR 0xFF000000 +#define BF_POWER_VERSION_MAJOR(v) \ + (((v) << 24) & BM_POWER_VERSION_MAJOR) +#define BP_POWER_VERSION_MINOR 16 +#define BM_POWER_VERSION_MINOR 0x00FF0000 +#define BF_POWER_VERSION_MINOR(v) \ + (((v) << 16) & BM_POWER_VERSION_MINOR) +#define BP_POWER_VERSION_STEP 0 +#define BM_POWER_VERSION_STEP 0x0000FFFF +#define BF_POWER_VERSION_STEP(v) \ + (((v) << 0) & BM_POWER_VERSION_STEP) +#endif /* __ARCH_ARM___POWER_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-pwm.h b/arch/arm/mach-mx23/include/mach/regs-pwm.h new file mode 100644 index 000000000000..30380d71e2e4 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-pwm.h @@ -0,0 +1,135 @@ +/* + * Freescale PWM Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.23 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PWM_H +#define __ARCH_ARM___PWM_H + + +#define HW_PWM_CTRL (0x00000000) +#define HW_PWM_CTRL_SET (0x00000004) +#define HW_PWM_CTRL_CLR (0x00000008) +#define HW_PWM_CTRL_TOG (0x0000000c) + +#define BM_PWM_CTRL_SFTRST 0x80000000 +#define BM_PWM_CTRL_CLKGATE 0x40000000 +#define BM_PWM_CTRL_PWM4_PRESENT 0x20000000 +#define BM_PWM_CTRL_PWM3_PRESENT 0x10000000 +#define BM_PWM_CTRL_PWM2_PRESENT 0x08000000 +#define BM_PWM_CTRL_PWM1_PRESENT 0x04000000 +#define BM_PWM_CTRL_PWM0_PRESENT 0x02000000 +#define BP_PWM_CTRL_RSRVD1 7 +#define BM_PWM_CTRL_RSRVD1 0x01FFFF80 +#define BF_PWM_CTRL_RSRVD1(v) \ + (((v) << 7) & BM_PWM_CTRL_RSRVD1) +#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN 0x00000040 +#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 +#define BM_PWM_CTRL_PWM4_ENABLE 0x00000010 +#define BM_PWM_CTRL_PWM3_ENABLE 0x00000008 +#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 +#define BM_PWM_CTRL_PWM1_ENABLE 0x00000002 +#define BM_PWM_CTRL_PWM0_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PWM_ACTIVEn + * base 0x00000010 + * count 5 + * offset 0x20 + */ +#define HW_PWM_ACTIVEn(n) (0x00000010 + (n) * 0x20) +#define HW_PWM_ACTIVEn_SET(n) (0x00000014 + (n) * 0x20) +#define HW_PWM_ACTIVEn_CLR(n) (0x00000018 + (n) * 0x20) +#define HW_PWM_ACTIVEn_TOG(n) (0x0000001c + (n) * 0x20) +#define BP_PWM_ACTIVEn_INACTIVE 16 +#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 +#define BF_PWM_ACTIVEn_INACTIVE(v) \ + (((v) << 16) & BM_PWM_ACTIVEn_INACTIVE) +#define BP_PWM_ACTIVEn_ACTIVE 0 +#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF +#define BF_PWM_ACTIVEn_ACTIVE(v) \ + (((v) << 0) & BM_PWM_ACTIVEn_ACTIVE) + +/* + * multi-register-define name HW_PWM_PERIODn + * base 0x00000020 + * count 5 + * offset 0x20 + */ +#define HW_PWM_PERIODn(n) (0x00000020 + (n) * 0x20) +#define HW_PWM_PERIODn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_PWM_PERIODn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_PWM_PERIODn_TOG(n) (0x0000002c + (n) * 0x20) +#define BP_PWM_PERIODn_RSRVD2 25 +#define BM_PWM_PERIODn_RSRVD2 0xFE000000 +#define BF_PWM_PERIODn_RSRVD2(v) \ + (((v) << 25) & BM_PWM_PERIODn_RSRVD2) +#define BM_PWM_PERIODn_MATT_SEL 0x01000000 +#define BM_PWM_PERIODn_MATT 0x00800000 +#define BP_PWM_PERIODn_CDIV 20 +#define BM_PWM_PERIODn_CDIV 0x00700000 +#define BF_PWM_PERIODn_CDIV(v) \ + (((v) << 20) & BM_PWM_PERIODn_CDIV) +#define BV_PWM_PERIODn_CDIV__DIV_1 0x0 +#define BV_PWM_PERIODn_CDIV__DIV_2 0x1 +#define BV_PWM_PERIODn_CDIV__DIV_4 0x2 +#define BV_PWM_PERIODn_CDIV__DIV_8 0x3 +#define BV_PWM_PERIODn_CDIV__DIV_16 0x4 +#define BV_PWM_PERIODn_CDIV__DIV_64 0x5 +#define BV_PWM_PERIODn_CDIV__DIV_256 0x6 +#define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 +#define BP_PWM_PERIODn_INACTIVE_STATE 18 +#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 +#define BF_PWM_PERIODn_INACTIVE_STATE(v) \ + (((v) << 18) & BM_PWM_PERIODn_INACTIVE_STATE) +#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_ACTIVE_STATE 16 +#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 +#define BF_PWM_PERIODn_ACTIVE_STATE(v) \ + (((v) << 16) & BM_PWM_PERIODn_ACTIVE_STATE) +#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_PERIOD 0 +#define BM_PWM_PERIODn_PERIOD 0x0000FFFF +#define BF_PWM_PERIODn_PERIOD(v) \ + (((v) << 0) & BM_PWM_PERIODn_PERIOD) + +#define HW_PWM_VERSION (0x000000b0) + +#define BP_PWM_VERSION_MAJOR 24 +#define BM_PWM_VERSION_MAJOR 0xFF000000 +#define BF_PWM_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PWM_VERSION_MAJOR) +#define BP_PWM_VERSION_MINOR 16 +#define BM_PWM_VERSION_MINOR 0x00FF0000 +#define BF_PWM_VERSION_MINOR(v) \ + (((v) << 16) & BM_PWM_VERSION_MINOR) +#define BP_PWM_VERSION_STEP 0 +#define BM_PWM_VERSION_STEP 0x0000FFFF +#define BF_PWM_VERSION_STEP(v) \ + (((v) << 0) & BM_PWM_VERSION_STEP) +#endif /* __ARCH_ARM___PWM_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-pxp.h b/arch/arm/mach-mx23/include/mach/regs-pxp.h new file mode 100644 index 000000000000..0a960614d9d7 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-pxp.h @@ -0,0 +1,517 @@ +/* + * Freescale PXP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BP_PXP_CTRL_RSVD2 28 +#define BM_PXP_CTRL_RSVD2 0x30000000 +#define BF_PXP_CTRL_RSVD2(v) \ + (((v) << 28) & BM_PXP_CTRL_RSVD2) +#define BP_PXP_CTRL_INTERLACED_OUTPUT 26 +#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000 +#define BF_PXP_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_RSVD1 0x00800000 +#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BM_PXP_CTRL_DELTA 0x00100000 +#define BM_PXP_CTRL_CROP 0x00080000 +#define BM_PXP_CTRL_SCALE 0x00040000 +#define BM_PXP_CTRL_UPSAMPLE 0x00020000 +#define BM_PXP_CTRL_SUBSAMPLE 0x00010000 +#define BP_PXP_CTRL_S0_FORMAT 12 +#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 +#define BF_PXP_CTRL_S0_FORMAT(v) \ + (((v) << 12) & BM_PXP_CTRL_S0_FORMAT) +#define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8 +#define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9 +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 +#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0 +#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v) \ + (((v) << 4) & BM_PXP_CTRL_OUTPUT_RGB_FORMAT) +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P 0x2 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555 0x3 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555 0x5 +#define BM_PXP_CTRL_RSVD0 0x00000008 +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 8 +#define BM_PXP_STAT_RSVD2 0x0000FF00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 8) & BM_PXP_STAT_RSVD2) +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_RSVD1 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_RGBBUF (0x00000020) + +#define BP_PXP_RGBBUF_ADDR 0 +#define BM_PXP_RGBBUF_ADDR 0xFFFFFFFF +#define BF_PXP_RGBBUF_ADDR(v) (v) + +#define HW_PXP_RGBBUF2 (0x00000030) + +#define BP_PXP_RGBBUF2_ADDR 0 +#define BM_PXP_RGBBUF2_ADDR 0xFFFFFFFF +#define BF_PXP_RGBBUF2_ADDR(v) (v) + +#define HW_PXP_RGBSIZE (0x00000040) + +#define BP_PXP_RGBSIZE_ALPHA 24 +#define BM_PXP_RGBSIZE_ALPHA 0xFF000000 +#define BF_PXP_RGBSIZE_ALPHA(v) \ + (((v) << 24) & BM_PXP_RGBSIZE_ALPHA) +#define BP_PXP_RGBSIZE_WIDTH 12 +#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000 +#define BF_PXP_RGBSIZE_WIDTH(v) \ + (((v) << 12) & BM_PXP_RGBSIZE_WIDTH) +#define BP_PXP_RGBSIZE_HEIGHT 0 +#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF +#define BF_PXP_RGBSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_RGBSIZE_HEIGHT) + +#define HW_PXP_S0BUF (0x00000050) + +#define BP_PXP_S0BUF_ADDR 0 +#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0BUF_ADDR(v) (v) + +#define HW_PXP_S0UBUF (0x00000060) + +#define BP_PXP_S0UBUF_ADDR 0 +#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0UBUF_ADDR(v) (v) + +#define HW_PXP_S0VBUF (0x00000070) + +#define BP_PXP_S0VBUF_ADDR 0 +#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0VBUF_ADDR(v) (v) + +#define HW_PXP_S0PARAM (0x00000080) + +#define BP_PXP_S0PARAM_XBASE 24 +#define BM_PXP_S0PARAM_XBASE 0xFF000000 +#define BF_PXP_S0PARAM_XBASE(v) \ + (((v) << 24) & BM_PXP_S0PARAM_XBASE) +#define BP_PXP_S0PARAM_YBASE 16 +#define BM_PXP_S0PARAM_YBASE 0x00FF0000 +#define BF_PXP_S0PARAM_YBASE(v) \ + (((v) << 16) & BM_PXP_S0PARAM_YBASE) +#define BP_PXP_S0PARAM_WIDTH 8 +#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 +#define BF_PXP_S0PARAM_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0PARAM_WIDTH) +#define BP_PXP_S0PARAM_HEIGHT 0 +#define BM_PXP_S0PARAM_HEIGHT 0x000000FF +#define BF_PXP_S0PARAM_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0PARAM_HEIGHT) + +#define HW_PXP_S0BACKGROUND (0x00000090) + +#define BP_PXP_S0BACKGROUND_COLOR 0 +#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_S0BACKGROUND_COLOR(v) (v) + +#define HW_PXP_S0CROP (0x000000a0) + +#define BP_PXP_S0CROP_XBASE 24 +#define BM_PXP_S0CROP_XBASE 0xFF000000 +#define BF_PXP_S0CROP_XBASE(v) \ + (((v) << 24) & BM_PXP_S0CROP_XBASE) +#define BP_PXP_S0CROP_YBASE 16 +#define BM_PXP_S0CROP_YBASE 0x00FF0000 +#define BF_PXP_S0CROP_YBASE(v) \ + (((v) << 16) & BM_PXP_S0CROP_YBASE) +#define BP_PXP_S0CROP_WIDTH 8 +#define BM_PXP_S0CROP_WIDTH 0x0000FF00 +#define BF_PXP_S0CROP_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0CROP_WIDTH) +#define BP_PXP_S0CROP_HEIGHT 0 +#define BM_PXP_S0CROP_HEIGHT 0x000000FF +#define BF_PXP_S0CROP_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0CROP_HEIGHT) + +#define HW_PXP_S0SCALE (0x000000b0) + +#define BP_PXP_S0SCALE_RSVD2 30 +#define BM_PXP_S0SCALE_RSVD2 0xC0000000 +#define BF_PXP_S0SCALE_RSVD2(v) \ + (((v) << 30) & BM_PXP_S0SCALE_RSVD2) +#define BP_PXP_S0SCALE_YSCALE 16 +#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000 +#define BF_PXP_S0SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_S0SCALE_YSCALE) +#define BP_PXP_S0SCALE_RSVD1 14 +#define BM_PXP_S0SCALE_RSVD1 0x0000C000 +#define BF_PXP_S0SCALE_RSVD1(v) \ + (((v) << 14) & BM_PXP_S0SCALE_RSVD1) +#define BP_PXP_S0SCALE_XSCALE 0 +#define BM_PXP_S0SCALE_XSCALE 0x00003FFF +#define BF_PXP_S0SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_S0SCALE_XSCALE) + +#define HW_PXP_S0OFFSET (0x000000c0) + +#define BP_PXP_S0OFFSET_RSVD2 28 +#define BM_PXP_S0OFFSET_RSVD2 0xF0000000 +#define BF_PXP_S0OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_S0OFFSET_RSVD2) +#define BP_PXP_S0OFFSET_YOFFSET 16 +#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_S0OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_S0OFFSET_YOFFSET) +#define BP_PXP_S0OFFSET_RSVD1 12 +#define BM_PXP_S0OFFSET_RSVD1 0x0000F000 +#define BF_PXP_S0OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_S0OFFSET_RSVD1) +#define BP_PXP_S0OFFSET_XOFFSET 0 +#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_S0OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_S0OFFSET_XOFFSET) + +#define HW_PXP_CSCCOEFF0 (0x000000d0) + +#define BM_PXP_CSCCOEFF0_YCBCR_MODE 0x80000000 +#define BP_PXP_CSCCOEFF0_RSVD1 29 +#define BM_PXP_CSCCOEFF0_RSVD1 0x60000000 +#define BF_PXP_CSCCOEFF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSCCOEFF0_RSVD1) +#define BP_PXP_CSCCOEFF0_C0 18 +#define BM_PXP_CSCCOEFF0_C0 0x1FFC0000 +#define BF_PXP_CSCCOEFF0_C0(v) \ + (((v) << 18) & BM_PXP_CSCCOEFF0_C0) +#define BP_PXP_CSCCOEFF0_UV_OFFSET 9 +#define BM_PXP_CSCCOEFF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSCCOEFF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSCCOEFF0_UV_OFFSET) +#define BP_PXP_CSCCOEFF0_Y_OFFSET 0 +#define BM_PXP_CSCCOEFF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSCCOEFF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF0_Y_OFFSET) + +#define HW_PXP_CSCCOEFF1 (0x000000e0) + +#define BP_PXP_CSCCOEFF1_RSVD1 27 +#define BM_PXP_CSCCOEFF1_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF1_RSVD1) +#define BP_PXP_CSCCOEFF1_C1 16 +#define BM_PXP_CSCCOEFF1_C1 0x07FF0000 +#define BF_PXP_CSCCOEFF1_C1(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF1_C1) +#define BP_PXP_CSCCOEFF1_RSVD0 11 +#define BM_PXP_CSCCOEFF1_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF1_RSVD0) +#define BP_PXP_CSCCOEFF1_C4 0 +#define BM_PXP_CSCCOEFF1_C4 0x000007FF +#define BF_PXP_CSCCOEFF1_C4(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF1_C4) + +#define HW_PXP_CSCCOEFF2 (0x000000f0) + +#define BP_PXP_CSCCOEFF2_RSVD1 27 +#define BM_PXP_CSCCOEFF2_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF2_RSVD1) +#define BP_PXP_CSCCOEFF2_C2 16 +#define BM_PXP_CSCCOEFF2_C2 0x07FF0000 +#define BF_PXP_CSCCOEFF2_C2(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF2_C2) +#define BP_PXP_CSCCOEFF2_RSVD0 11 +#define BM_PXP_CSCCOEFF2_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF2_RSVD0) +#define BP_PXP_CSCCOEFF2_C3 0 +#define BM_PXP_CSCCOEFF2_C3 0x000007FF +#define BF_PXP_CSCCOEFF2_C3(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF2_C3) + +#define HW_PXP_NEXT (0x00000100) +#define HW_PXP_NEXT_SET (0x00000104) +#define HW_PXP_NEXT_CLR (0x00000108) +#define HW_PXP_NEXT_TOG (0x0000010c) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_PAGETABLE (0x00000170) + +#define BP_PXP_PAGETABLE_BASE 14 +#define BM_PXP_PAGETABLE_BASE 0xFFFFC000 +#define BF_PXP_PAGETABLE_BASE(v) \ + (((v) << 14) & BM_PXP_PAGETABLE_BASE) +#define BP_PXP_PAGETABLE_RSVD1 2 +#define BM_PXP_PAGETABLE_RSVD1 0x00003FFC +#define BF_PXP_PAGETABLE_RSVD1(v) \ + (((v) << 2) & BM_PXP_PAGETABLE_RSVD1) +#define BM_PXP_PAGETABLE_FLUSH 0x00000002 +#define BM_PXP_PAGETABLE_ENABLE 0x00000001 + +#define HW_PXP_S0COLORKEYLOW (0x00000180) + +#define BP_PXP_S0COLORKEYLOW_RSVD1 24 +#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1) +#define BP_PXP_S0COLORKEYLOW_PIXEL 0 +#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL) + +#define HW_PXP_S0COLORKEYHIGH (0x00000190) + +#define BP_PXP_S0COLORKEYHIGH_RSVD1 24 +#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1) +#define BP_PXP_S0COLORKEYHIGH_PIXEL 0 +#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL) + +#define HW_PXP_OLCOLORKEYLOW (0x000001a0) + +#define BP_PXP_OLCOLORKEYLOW_RSVD1 24 +#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1) +#define BP_PXP_OLCOLORKEYLOW_PIXEL 0 +#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL) + +#define HW_PXP_OLCOLORKEYHIGH (0x000001b0) + +#define BP_PXP_OLCOLORKEYHIGH_RSVD1 24 +#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1) +#define BP_PXP_OLCOLORKEYHIGH_PIXEL 0 +#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL) + +#define HW_PXP_DEBUGCTRL (0x000001d0) + +#define BP_PXP_DEBUGCTRL_RSVD 9 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFE00 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 9) & BM_PXP_DEBUGCTRL_RSVD) +#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS 0x00000100 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8 + +#define HW_PXP_DEBUG (0x000001e0) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x000001f0) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +/* + * multi-register-define name HW_PXP_OLn + * base 0x00000200 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLn(n) (0x00000200 + (n) * 0x40) +#define BP_PXP_OLn_ADDR 0 +#define BM_PXP_OLn_ADDR 0xFFFFFFFF +#define BF_PXP_OLn_ADDR(v) (v) + +/* + * multi-register-define name HW_PXP_OLnSIZE + * base 0x00000210 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnSIZE(n) (0x00000210 + (n) * 0x40) +#define BP_PXP_OLnSIZE_XBASE 24 +#define BM_PXP_OLnSIZE_XBASE 0xFF000000 +#define BF_PXP_OLnSIZE_XBASE(v) \ + (((v) << 24) & BM_PXP_OLnSIZE_XBASE) +#define BP_PXP_OLnSIZE_YBASE 16 +#define BM_PXP_OLnSIZE_YBASE 0x00FF0000 +#define BF_PXP_OLnSIZE_YBASE(v) \ + (((v) << 16) & BM_PXP_OLnSIZE_YBASE) +#define BP_PXP_OLnSIZE_WIDTH 8 +#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 +#define BF_PXP_OLnSIZE_WIDTH(v) \ + (((v) << 8) & BM_PXP_OLnSIZE_WIDTH) +#define BP_PXP_OLnSIZE_HEIGHT 0 +#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF +#define BF_PXP_OLnSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OLnSIZE_HEIGHT) + +/* + * multi-register-define name HW_PXP_OLnPARAM + * base 0x00000220 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM(n) (0x00000220 + (n) * 0x40) +#define BP_PXP_OLnPARAM_RSVD1 20 +#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000 +#define BF_PXP_OLnPARAM_RSVD1(v) \ + (((v) << 20) & BM_PXP_OLnPARAM_RSVD1) +#define BP_PXP_OLnPARAM_ROP 16 +#define BM_PXP_OLnPARAM_ROP 0x000F0000 +#define BF_PXP_OLnPARAM_ROP(v) \ + (((v) << 16) & BM_PXP_OLnPARAM_ROP) +#define BV_PXP_OLnPARAM_ROP__MASKOL 0x0 +#define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1 +#define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2 +#define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3 +#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4 +#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5 +#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6 +#define BV_PXP_OLnPARAM_ROP__NOT 0x7 +#define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8 +#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9 +#define BV_PXP_OLnPARAM_ROP__XOROL 0xA +#define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xB +#define BP_PXP_OLnPARAM_ALPHA 8 +#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 +#define BF_PXP_OLnPARAM_ALPHA(v) \ + (((v) << 8) & BM_PXP_OLnPARAM_ALPHA) +#define BP_PXP_OLnPARAM_FORMAT 4 +#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 +#define BF_PXP_OLnPARAM_FORMAT(v) \ + (((v) << 4) & BM_PXP_OLnPARAM_FORMAT) +#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0 +#define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1 +#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3 +#define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4 +#define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5 +#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 +#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 +#define BF_PXP_OLnPARAM_ALPHA_CNTL(v) \ + (((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL) +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3 +#define BM_PXP_OLnPARAM_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PXP_OLnPARAM2 + * base 0x00000230 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM2(n) (0x00000230 + (n) * 0x40) +#define BP_PXP_OLnPARAM2_RSVD 0 +#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF +#define BF_PXP_OLnPARAM2_RSVD(v) (v) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-rtc.h b/arch/arm/mach-mx23/include/mach/regs-rtc.h new file mode 100644 index 000000000000..a953a1d361ca --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-rtc.h @@ -0,0 +1,219 @@ +/* + * Freescale RTC Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.75 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___RTC_H +#define __ARCH_ARM___RTC_H + + +#define HW_RTC_CTRL (0x00000000) +#define HW_RTC_CTRL_SET (0x00000004) +#define HW_RTC_CTRL_CLR (0x00000008) +#define HW_RTC_CTRL_TOG (0x0000000c) + +#define BM_RTC_CTRL_SFTRST 0x80000000 +#define BM_RTC_CTRL_CLKGATE 0x40000000 +#define BP_RTC_CTRL_RSVD0 7 +#define BM_RTC_CTRL_RSVD0 0x3FFFFF80 +#define BF_RTC_CTRL_RSVD0(v) \ + (((v) << 7) & BM_RTC_CTRL_RSVD0) +#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x00000040 +#define BM_RTC_CTRL_FORCE_UPDATE 0x00000020 +#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 +#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 +#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 +#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 +#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 + +#define HW_RTC_STAT (0x00000010) +#define HW_RTC_STAT_SET (0x00000014) +#define HW_RTC_STAT_CLR (0x00000018) +#define HW_RTC_STAT_TOG (0x0000001c) + +#define BM_RTC_STAT_RTC_PRESENT 0x80000000 +#define BM_RTC_STAT_ALARM_PRESENT 0x40000000 +#define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 +#define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 +#define BM_RTC_STAT_XTAL32768_PRESENT 0x08000000 +#define BP_RTC_STAT_RSVD1 24 +#define BM_RTC_STAT_RSVD1 0x07000000 +#define BF_RTC_STAT_RSVD1(v) \ + (((v) << 24) & BM_RTC_STAT_RSVD1) +#define BP_RTC_STAT_STALE_REGS 16 +#define BM_RTC_STAT_STALE_REGS 0x00FF0000 +#define BF_RTC_STAT_STALE_REGS(v) \ + (((v) << 16) & BM_RTC_STAT_STALE_REGS) +#define BP_RTC_STAT_NEW_REGS 8 +#define BM_RTC_STAT_NEW_REGS 0x0000FF00 +#define BF_RTC_STAT_NEW_REGS(v) \ + (((v) << 8) & BM_RTC_STAT_NEW_REGS) +#define BP_RTC_STAT_RSVD0 0 +#define BM_RTC_STAT_RSVD0 0x000000FF +#define BF_RTC_STAT_RSVD0(v) \ + (((v) << 0) & BM_RTC_STAT_RSVD0) + +#define HW_RTC_MILLISECONDS (0x00000020) +#define HW_RTC_MILLISECONDS_SET (0x00000024) +#define HW_RTC_MILLISECONDS_CLR (0x00000028) +#define HW_RTC_MILLISECONDS_TOG (0x0000002c) + +#define BP_RTC_MILLISECONDS_COUNT 0 +#define BM_RTC_MILLISECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_MILLISECONDS_COUNT(v) (v) + +#define HW_RTC_SECONDS (0x00000030) +#define HW_RTC_SECONDS_SET (0x00000034) +#define HW_RTC_SECONDS_CLR (0x00000038) +#define HW_RTC_SECONDS_TOG (0x0000003c) + +#define BP_RTC_SECONDS_COUNT 0 +#define BM_RTC_SECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_SECONDS_COUNT(v) (v) + +#define HW_RTC_ALARM (0x00000040) +#define HW_RTC_ALARM_SET (0x00000044) +#define HW_RTC_ALARM_CLR (0x00000048) +#define HW_RTC_ALARM_TOG (0x0000004c) + +#define BP_RTC_ALARM_VALUE 0 +#define BM_RTC_ALARM_VALUE 0xFFFFFFFF +#define BF_RTC_ALARM_VALUE(v) (v) + +#define HW_RTC_WATCHDOG (0x00000050) +#define HW_RTC_WATCHDOG_SET (0x00000054) +#define HW_RTC_WATCHDOG_CLR (0x00000058) +#define HW_RTC_WATCHDOG_TOG (0x0000005c) + +#define BP_RTC_WATCHDOG_COUNT 0 +#define BM_RTC_WATCHDOG_COUNT 0xFFFFFFFF +#define BF_RTC_WATCHDOG_COUNT(v) (v) + +#define HW_RTC_PERSISTENT0 (0x00000060) +#define HW_RTC_PERSISTENT0_SET (0x00000064) +#define HW_RTC_PERSISTENT0_CLR (0x00000068) +#define HW_RTC_PERSISTENT0_TOG (0x0000006c) + +#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 +#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 +#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) \ + (((v) << 18) & BM_RTC_PERSISTENT0_SPARE_ANALOG) +#define BM_RTC_PERSISTENT0_AUTO_RESTART 0x00020000 +#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x00010000 +#define BP_RTC_PERSISTENT0_LOWERBIAS 14 +#define BM_RTC_PERSISTENT0_LOWERBIAS 0x0000C000 +#define BF_RTC_PERSISTENT0_LOWERBIAS(v) \ + (((v) << 14) & BM_RTC_PERSISTENT0_LOWERBIAS) +#define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x00002000 +#define BP_RTC_PERSISTENT0_MSEC_RES 8 +#define BM_RTC_PERSISTENT0_MSEC_RES 0x00001F00 +#define BF_RTC_PERSISTENT0_MSEC_RES(v) \ + (((v) << 8) & BM_RTC_PERSISTENT0_MSEC_RES) +#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 +#define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x00000040 +#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 +#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 +#define BM_RTC_PERSISTENT0_LCK_SECS 0x00000008 +#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 +#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 +#define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x00000001 + +#define HW_RTC_PERSISTENT1 (0x00000070) +#define HW_RTC_PERSISTENT1_SET (0x00000074) +#define HW_RTC_PERSISTENT1_CLR (0x00000078) +#define HW_RTC_PERSISTENT1_TOG (0x0000007c) + +#define BP_RTC_PERSISTENT1_GENERAL 0 +#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT1_GENERAL(v) (v) +#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 +#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x0800 +#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x0400 +#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x0200 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x0100 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x0080 + +#define HW_RTC_PERSISTENT2 (0x00000080) +#define HW_RTC_PERSISTENT2_SET (0x00000084) +#define HW_RTC_PERSISTENT2_CLR (0x00000088) +#define HW_RTC_PERSISTENT2_TOG (0x0000008c) + +#define BP_RTC_PERSISTENT2_GENERAL 0 +#define BM_RTC_PERSISTENT2_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT2_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT3 (0x00000090) +#define HW_RTC_PERSISTENT3_SET (0x00000094) +#define HW_RTC_PERSISTENT3_CLR (0x00000098) +#define HW_RTC_PERSISTENT3_TOG (0x0000009c) + +#define BP_RTC_PERSISTENT3_GENERAL 0 +#define BM_RTC_PERSISTENT3_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT3_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT4 (0x000000a0) +#define HW_RTC_PERSISTENT4_SET (0x000000a4) +#define HW_RTC_PERSISTENT4_CLR (0x000000a8) +#define HW_RTC_PERSISTENT4_TOG (0x000000ac) + +#define BP_RTC_PERSISTENT4_GENERAL 0 +#define BM_RTC_PERSISTENT4_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT4_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT5 (0x000000b0) +#define HW_RTC_PERSISTENT5_SET (0x000000b4) +#define HW_RTC_PERSISTENT5_CLR (0x000000b8) +#define HW_RTC_PERSISTENT5_TOG (0x000000bc) + +#define BP_RTC_PERSISTENT5_GENERAL 0 +#define BM_RTC_PERSISTENT5_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT5_GENERAL(v) (v) + +#define HW_RTC_DEBUG (0x000000c0) +#define HW_RTC_DEBUG_SET (0x000000c4) +#define HW_RTC_DEBUG_CLR (0x000000c8) +#define HW_RTC_DEBUG_TOG (0x000000cc) + +#define BP_RTC_DEBUG_RSVD0 2 +#define BM_RTC_DEBUG_RSVD0 0xFFFFFFFC +#define BF_RTC_DEBUG_RSVD0(v) \ + (((v) << 2) & BM_RTC_DEBUG_RSVD0) +#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x00000002 +#define BM_RTC_DEBUG_WATCHDOG_RESET 0x00000001 + +#define HW_RTC_VERSION (0x000000d0) + +#define BP_RTC_VERSION_MAJOR 24 +#define BM_RTC_VERSION_MAJOR 0xFF000000 +#define BF_RTC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_RTC_VERSION_MAJOR) +#define BP_RTC_VERSION_MINOR 16 +#define BM_RTC_VERSION_MINOR 0x00FF0000 +#define BF_RTC_VERSION_MINOR(v) \ + (((v) << 16) & BM_RTC_VERSION_MINOR) +#define BP_RTC_VERSION_STEP 0 +#define BM_RTC_VERSION_STEP 0x0000FFFF +#define BF_RTC_VERSION_STEP(v) \ + (((v) << 0) & BM_RTC_VERSION_STEP) +#endif /* __ARCH_ARM___RTC_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-ssp.h b/arch/arm/mach-mx23/include/mach/regs-ssp.h new file mode 100644 index 000000000000..cdc07f8930dd --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-ssp.h @@ -0,0 +1,392 @@ +/* + * Freescale SSP Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 2.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___SSP_H +#define __ARCH_ARM___SSP_H + + +#define HW_SSP_CTRL0 (0x00000000) +#define HW_SSP_CTRL0_SET (0x00000004) +#define HW_SSP_CTRL0_CLR (0x00000008) +#define HW_SSP_CTRL0_TOG (0x0000000c) + +#define BM_SSP_CTRL0_SFTRST 0x80000000 +#define BM_SSP_CTRL0_CLKGATE 0x40000000 +#define BM_SSP_CTRL0_RUN 0x20000000 +#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 +#define BM_SSP_CTRL0_LOCK_CS 0x08000000 +#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 +#define BM_SSP_CTRL0_READ 0x02000000 +#define BM_SSP_CTRL0_DATA_XFER 0x01000000 +#define BP_SSP_CTRL0_BUS_WIDTH 22 +#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 +#define BF_SSP_CTRL0_BUS_WIDTH(v) \ + (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH) +#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 +#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 +#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 +#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 +#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 +#define BM_SSP_CTRL0_LONG_RESP 0x00080000 +#define BM_SSP_CTRL0_CHECK_RESP 0x00040000 +#define BM_SSP_CTRL0_GET_RESP 0x00020000 +#define BM_SSP_CTRL0_ENABLE 0x00010000 +#define BP_SSP_CTRL0_XFER_COUNT 0 +#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_SSP_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_SSP_CTRL0_XFER_COUNT) + +#define HW_SSP_CMD0 (0x00000010) +#define HW_SSP_CMD0_SET (0x00000014) +#define HW_SSP_CMD0_CLR (0x00000018) +#define HW_SSP_CMD0_TOG (0x0000001c) + +#define BP_SSP_CMD0_RSVD0 23 +#define BM_SSP_CMD0_RSVD0 0xFF800000 +#define BF_SSP_CMD0_RSVD0(v) \ + (((v) << 23) & BM_SSP_CMD0_RSVD0) +#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000 +#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000 +#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 +#define BP_SSP_CMD0_BLOCK_SIZE 16 +#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 +#define BF_SSP_CMD0_BLOCK_SIZE(v) \ + (((v) << 16) & BM_SSP_CMD0_BLOCK_SIZE) +#define BP_SSP_CMD0_BLOCK_COUNT 8 +#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 +#define BF_SSP_CMD0_BLOCK_COUNT(v) \ + (((v) << 8) & BM_SSP_CMD0_BLOCK_COUNT) +#define BP_SSP_CMD0_CMD 0 +#define BM_SSP_CMD0_CMD 0x000000FF +#define BF_SSP_CMD0_CMD(v) \ + (((v) << 0) & BM_SSP_CMD0_CMD) +#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01 +#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05 +#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06 +#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08 +#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B +#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E +#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 +#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 +#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 +#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 +#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 +#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 +#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05 +#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__SD_ERASE 0x26 +#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 +#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 +#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 + +#define HW_SSP_CMD1 (0x00000020) + +#define BP_SSP_CMD1_CMD_ARG 0 +#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF +#define BF_SSP_CMD1_CMD_ARG(v) (v) + +#define HW_SSP_COMPREF (0x00000030) + +#define BP_SSP_COMPREF_REFERENCE 0 +#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF +#define BF_SSP_COMPREF_REFERENCE(v) (v) + +#define HW_SSP_COMPMASK (0x00000040) + +#define BP_SSP_COMPMASK_MASK 0 +#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF +#define BF_SSP_COMPMASK_MASK(v) (v) + +#define HW_SSP_TIMING (0x00000050) + +#define BP_SSP_TIMING_TIMEOUT 16 +#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 +#define BF_SSP_TIMING_TIMEOUT(v) \ + (((v) << 16) & BM_SSP_TIMING_TIMEOUT) +#define BP_SSP_TIMING_CLOCK_DIVIDE 8 +#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) +#define BP_SSP_TIMING_CLOCK_RATE 0 +#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) + +#define HW_SSP_CTRL1 (0x00000060) +#define HW_SSP_CTRL1_SET (0x00000064) +#define HW_SSP_CTRL1_CLR (0x00000068) +#define HW_SSP_CTRL1_TOG (0x0000006c) + +#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 +#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000 +#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000 +#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800 +#define BM_SSP_CTRL1_PHASE 0x00000400 +#define BM_SSP_CTRL1_POLARITY 0x00000200 +#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100 +#define BP_SSP_CTRL1_WORD_LENGTH 4 +#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF +#define BP_SSP_CTRL1_SSP_MODE 0 +#define BM_SSP_CTRL1_SSP_MODE 0x0000000F +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 +#define BV_SSP_CTRL1_SSP_MODE__CE_ATA 0x7 + +#define HW_SSP_DATA (0x00000070) + +#define BP_SSP_DATA_DATA 0 +#define BM_SSP_DATA_DATA 0xFFFFFFFF +#define BF_SSP_DATA_DATA(v) (v) + +#define HW_SSP_SDRESP0 (0x00000080) + +#define BP_SSP_SDRESP0_RESP0 0 +#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF +#define BF_SSP_SDRESP0_RESP0(v) (v) + +#define HW_SSP_SDRESP1 (0x00000090) + +#define BP_SSP_SDRESP1_RESP1 0 +#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF +#define BF_SSP_SDRESP1_RESP1(v) (v) + +#define HW_SSP_SDRESP2 (0x000000a0) + +#define BP_SSP_SDRESP2_RESP2 0 +#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF +#define BF_SSP_SDRESP2_RESP2(v) (v) + +#define HW_SSP_SDRESP3 (0x000000b0) + +#define BP_SSP_SDRESP3_RESP3 0 +#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF +#define BF_SSP_SDRESP3_RESP3(v) (v) + +#define HW_SSP_STATUS (0x000000c0) + +#define BM_SSP_STATUS_PRESENT 0x80000000 +#define BM_SSP_STATUS_MS_PRESENT 0x40000000 +#define BM_SSP_STATUS_SD_PRESENT 0x20000000 +#define BM_SSP_STATUS_CARD_DETECT 0x10000000 +#define BP_SSP_STATUS_RSVD3 22 +#define BM_SSP_STATUS_RSVD3 0x0FC00000 +#define BF_SSP_STATUS_RSVD3(v) \ + (((v) << 22) & BM_SSP_STATUS_RSVD3) +#define BM_SSP_STATUS_DMASENSE 0x00200000 +#define BM_SSP_STATUS_DMATERM 0x00100000 +#define BM_SSP_STATUS_DMAREQ 0x00080000 +#define BM_SSP_STATUS_DMAEND 0x00040000 +#define BM_SSP_STATUS_SDIO_IRQ 0x00020000 +#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 +#define BM_SSP_STATUS_RESP_ERR 0x00008000 +#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 +#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000 +#define BM_SSP_STATUS_TIMEOUT 0x00001000 +#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800 +#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400 +#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200 +#define BM_SSP_STATUS_FIFO_FULL 0x00000100 +#define BP_SSP_STATUS_RSVD1 6 +#define BM_SSP_STATUS_RSVD1 0x000000C0 +#define BF_SSP_STATUS_RSVD1(v) \ + (((v) << 6) & BM_SSP_STATUS_RSVD1) +#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 +#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010 +#define BM_SSP_STATUS_CMD_BUSY 0x00000008 +#define BM_SSP_STATUS_DATA_BUSY 0x00000004 +#define BM_SSP_STATUS_RSVD0 0x00000002 +#define BM_SSP_STATUS_BUSY 0x00000001 + +#define HW_SSP_DEBUG (0x00000100) + +#define BP_SSP_DEBUG_DATACRC_ERR 28 +#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000 +#define BF_SSP_DEBUG_DATACRC_ERR(v) \ + (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR) +#define BM_SSP_DEBUG_DATA_STALL 0x08000000 +#define BP_SSP_DEBUG_DAT_SM 24 +#define BM_SSP_DEBUG_DAT_SM 0x07000000 +#define BF_SSP_DEBUG_DAT_SM(v) \ + (((v) << 24) & BM_SSP_DEBUG_DAT_SM) +#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 +#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 +#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 +#define BP_SSP_DEBUG_MSTK_SM 20 +#define BM_SSP_DEBUG_MSTK_SM 0x00F00000 +#define BF_SSP_DEBUG_MSTK_SM(v) \ + (((v) << 20) & BM_SSP_DEBUG_MSTK_SM) +#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD +#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE +#define BM_SSP_DEBUG_CMD_OE 0x00080000 +#define BP_SSP_DEBUG_DMA_SM 16 +#define BM_SSP_DEBUG_DMA_SM 0x00070000 +#define BF_SSP_DEBUG_DMA_SM(v) \ + (((v) << 16) & BM_SSP_DEBUG_DMA_SM) +#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 +#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 +#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 +#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 +#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 +#define BP_SSP_DEBUG_MMC_SM 12 +#define BM_SSP_DEBUG_MMC_SM 0x0000F000 +#define BF_SSP_DEBUG_MMC_SM(v) \ + (((v) << 12) & BM_SSP_DEBUG_MMC_SM) +#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 +#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 +#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 +#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 +#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 +#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 +#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 +#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 +#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 +#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 +#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA +#define BP_SSP_DEBUG_CMD_SM 10 +#define BM_SSP_DEBUG_CMD_SM 0x00000C00 +#define BF_SSP_DEBUG_CMD_SM(v) \ + (((v) << 10) & BM_SSP_DEBUG_CMD_SM) +#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 +#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 +#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 +#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 +#define BM_SSP_DEBUG_SSP_CMD 0x00000200 +#define BM_SSP_DEBUG_SSP_RESP 0x00000100 +#define BP_SSP_DEBUG_SSP_RXD 0 +#define BM_SSP_DEBUG_SSP_RXD 0x000000FF +#define BF_SSP_DEBUG_SSP_RXD(v) \ + (((v) << 0) & BM_SSP_DEBUG_SSP_RXD) + +#define HW_SSP_VERSION (0x00000110) + +#define BP_SSP_VERSION_MAJOR 24 +#define BM_SSP_VERSION_MAJOR 0xFF000000 +#define BF_SSP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SSP_VERSION_MAJOR) +#define BP_SSP_VERSION_MINOR 16 +#define BM_SSP_VERSION_MINOR 0x00FF0000 +#define BF_SSP_VERSION_MINOR(v) \ + (((v) << 16) & BM_SSP_VERSION_MINOR) +#define BP_SSP_VERSION_STEP 0 +#define BM_SSP_VERSION_STEP 0x0000FFFF +#define BF_SSP_VERSION_STEP(v) \ + (((v) << 0) & BM_SSP_VERSION_STEP) +#endif /* __ARCH_ARM___SSP_H */ diff --git a/arch/arm/mach-mx23/include/mach/regs-timrot.h b/arch/arm/mach-mx23/include/mach/regs-timrot.h new file mode 100644 index 000000000000..860709e92941 --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regs-timrot.h @@ -0,0 +1,257 @@ +/* + * Freescale TIMROT Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.38 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H + + +#define HW_TIMROT_ROTCTRL (0x00000000) +#define HW_TIMROT_ROTCTRL_SET (0x00000004) +#define HW_TIMROT_ROTCTRL_CLR (0x00000008) +#define HW_TIMROT_ROTCTRL_TOG (0x0000000c) + +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BP_TIMROT_ROTCTRL_RSRVD3 13 +#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000 +#define BF_TIMROT_ROTCTRL_RSRVD3(v) \ + (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BM_TIMROT_ROTCTRL_RSRVD2 0x00000080 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 +#define BM_TIMROT_ROTCTRL_RSRVD1 0x00000008 +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 + +#define HW_TIMROT_ROTCOUNT (0x00000010) + +#define BP_TIMROT_ROTCOUNT_RSRVD1 16 +#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000 +#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \ + (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) + +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x20 + */ +#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x20) +#define BP_TIMROT_TIMCTRLn_RSRVD2 16 +#define BM_TIMROT_TIMCTRLn_RSRVD2 0xFFFF0000 +#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD2) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRLn_RSRVD1 9 +#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00003E00 +#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \ + (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xC + +/* + * multi-register-define name HW_TIMROT_TIMCOUNTn + * base 0x00000030 + * count 3 + * offset 0x20 + */ +#define HW_TIMROT_TIMCOUNTn(n) (0x00000030 + (n) * 0x20) +#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 +#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xFFFF0000 +#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) \ + (((v) << 16) & BM_TIMROT_TIMCOUNTn_RUNNING_COUNT) +#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 +#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0x0000FFFF +#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) \ + (((v) << 0) & BM_TIMROT_TIMCOUNTn_FIXED_COUNT) + +#define HW_TIMROT_TIMCTRL3 (0x00000080) +#define HW_TIMROT_TIMCTRL3_SET (0x00000084) +#define HW_TIMROT_TIMCTRL3_CLR (0x00000088) +#define HW_TIMROT_TIMCTRL3_TOG (0x0000008c) + +#define BP_TIMROT_TIMCTRL3_RSRVD2 20 +#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000 +#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \ + (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xC +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRL3_RSRVD1 11 +#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003800 +#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \ + (((v) << 11) & BM_TIMROT_TIMCTRL3_RSRVD1) +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xC + +#define HW_TIMROT_TIMCOUNT3 (0x00000090) + +#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 +#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xFFFF0000 +#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) \ + (((v) << 16) & BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT) +#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0x0000FFFF +#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) \ + (((v) << 0) & BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT) + +#define HW_TIMROT_VERSION (0x000000a0) + +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/arch/arm/mach-mx23/include/mach/regulator.h b/arch/arm/mach-mx23/include/mach/regulator.h new file mode 100644 index 000000000000..1b073586268b --- /dev/null +++ b/arch/arm/mach-mx23/include/mach/regulator.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __PLAT_REGULATOR_H_ +#define __PLAT_REGULATOR_H_ + +#define MXS_REG5V_NOT_USB 0 +#define MXS_REG5V_IS_USB 1 +#define MXS_VDDD 0 +#define MXS_VDDA 1 +#define MXS_VDDIO 2 +#define MXS_VDDDBO 3 +#define MXS_OVERALL_CUR 4 + +#endif diff --git a/arch/arm/mach-mx23/mx23_pins.h b/arch/arm/mach-mx23/mx23_pins.h new file mode 100644 index 000000000000..9811bfdd0cad --- /dev/null +++ b/arch/arm/mach-mx23/mx23_pins.h @@ -0,0 +1,156 @@ +/* + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * Author: Vladislav Buzov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_PINS_H +#define __ASM_ARCH_PINS_H + +#include + +/* + * Define MX28 pins, the pin name corresponds to MX28 hardware + * interface this pin belongs to. + */ + +/* Bank 0 */ +#define PINID_GPMI_D00 MXS_PIN_ENCODE(0, 0) +#define PINID_GPMI_D01 MXS_PIN_ENCODE(0, 1) +#define PINID_GPMI_D02 MXS_PIN_ENCODE(0, 2) +#define PINID_GPMI_D03 MXS_PIN_ENCODE(0, 3) +#define PINID_GPMI_D04 MXS_PIN_ENCODE(0, 4) +#define PINID_GPMI_D05 MXS_PIN_ENCODE(0, 5) +#define PINID_GPMI_D06 MXS_PIN_ENCODE(0, 6) +#define PINID_GPMI_D07 MXS_PIN_ENCODE(0, 7) +#define PINID_GPMI_D08 MXS_PIN_ENCODE(0, 8) +#define PINID_GPMI_D09 MXS_PIN_ENCODE(0, 9) +#define PINID_GPMI_D10 MXS_PIN_ENCODE(0, 10) +#define PINID_GPMI_D11 MXS_PIN_ENCODE(0, 11) +#define PINID_GPMI_D12 MXS_PIN_ENCODE(0, 12) +#define PINID_GPMI_D13 MXS_PIN_ENCODE(0, 13) +#define PINID_GPMI_D14 MXS_PIN_ENCODE(0, 14) +#define PINID_GPMI_D15 MXS_PIN_ENCODE(0, 15) +#define PINID_GPMI_CLE MXS_PIN_ENCODE(0, 16) +#define PINID_GPMI_ALE MXS_PIN_ENCODE(0, 17) +#define PINID_GPMI_CE2N MXS_PIN_ENCODE(0, 18) +#define PINID_GPMI_RDY0 MXS_PIN_ENCODE(0, 19) +#define PINID_GPMI_RDY1 MXS_PIN_ENCODE(0, 20) +#define PINID_GPMI_RDY2 MXS_PIN_ENCODE(0, 21) +#define PINID_GPMI_RDY3 MXS_PIN_ENCODE(0, 22) +#define PINID_GPMI_WPN MXS_PIN_ENCODE(0, 23) +#define PINID_GPMI_WRN MXS_PIN_ENCODE(0, 24) +#define PINID_GPMI_RDN MXS_PIN_ENCODE(0, 25) +#define PINID_AUART1_CTS MXS_PIN_ENCODE(0, 26) +#define PINID_AUART1_RTS MXS_PIN_ENCODE(0, 27) +#define PINID_AUART1_RX MXS_PIN_ENCODE(0, 28) +#define PINID_AUART1_TX MXS_PIN_ENCODE(0, 29) +#define PINID_I2C_SCL MXS_PIN_ENCODE(0, 30) +#define PINID_I2C_SDA MXS_PIN_ENCODE(0, 31) + +/* Bank 1 */ +#define PINID_LCD_D00 MXS_PIN_ENCODE(1, 0) +#define PINID_LCD_D01 MXS_PIN_ENCODE(1, 1) +#define PINID_LCD_D02 MXS_PIN_ENCODE(1, 2) +#define PINID_LCD_D03 MXS_PIN_ENCODE(1, 3) +#define PINID_LCD_D04 MXS_PIN_ENCODE(1, 4) +#define PINID_LCD_D05 MXS_PIN_ENCODE(1, 5) +#define PINID_LCD_D06 MXS_PIN_ENCODE(1, 6) +#define PINID_LCD_D07 MXS_PIN_ENCODE(1, 7) +#define PINID_LCD_D08 MXS_PIN_ENCODE(1, 8) +#define PINID_LCD_D09 MXS_PIN_ENCODE(1, 9) +#define PINID_LCD_D10 MXS_PIN_ENCODE(1, 10) +#define PINID_LCD_D11 MXS_PIN_ENCODE(1, 11) +#define PINID_LCD_D12 MXS_PIN_ENCODE(1, 12) +#define PINID_LCD_D13 MXS_PIN_ENCODE(1, 13) +#define PINID_LCD_D14 MXS_PIN_ENCODE(1, 14) +#define PINID_LCD_D15 MXS_PIN_ENCODE(1, 15) +#define PINID_LCD_D16 MXS_PIN_ENCODE(1, 16) +#define PINID_LCD_D17 MXS_PIN_ENCODE(1, 17) +#define PINID_LCD_RESET MXS_PIN_ENCODE(1, 18) +#define PINID_LCD_RS MXS_PIN_ENCODE(1, 19) +#define PINID_LCD_WR MXS_PIN_ENCODE(1, 20) +#define PINID_LCD_CS MXS_PIN_ENCODE(1, 21) +#define PINID_LCD_DOTCK MXS_PIN_ENCODE(1, 22) +#define PINID_LCD_ENABLE MXS_PIN_ENCODE(1, 23) +#define PINID_LCD_HSYNC MXS_PIN_ENCODE(1, 24) +#define PINID_LCD_VSYNC MXS_PIN_ENCODE(1, 25) +#define PINID_PWM0 MXS_PIN_ENCODE(1, 26) +#define PINID_PWM1 MXS_PIN_ENCODE(1, 27) +#define PINID_PWM2 MXS_PIN_ENCODE(1, 28) +#define PINID_PWM3 MXS_PIN_ENCODE(1, 29) +#define PINID_PWM4 MXS_PIN_ENCODE(1, 30) + +/* Bank 2 */ +#define PINID_SSP1_CMD MXS_PIN_ENCODE(2, 0) +#define PINID_SSP1_DETECT MXS_PIN_ENCODE(2, 1) +#define PINID_SSP1_DATA0 MXS_PIN_ENCODE(2, 2) +#define PINID_SSP1_DATA1 MXS_PIN_ENCODE(2, 3) +#define PINID_SSP1_DATA2 MXS_PIN_ENCODE(2, 4) +#define PINID_SSP1_DATA3 MXS_PIN_ENCODE(2, 5) +#define PINID_SSP1_SCK MXS_PIN_ENCODE(2, 6) +#define PINID_ROTARYA MXS_PIN_ENCODE(2, 7) +#define PINID_ROTARYB MXS_PIN_ENCODE(2, 8) +#define PINID_EMI_A00 MXS_PIN_ENCODE(2, 9) +#define PINID_EMI_A01 MXS_PIN_ENCODE(2, 10) +#define PINID_EMI_A02 MXS_PIN_ENCODE(2, 11) +#define PINID_EMI_A03 MXS_PIN_ENCODE(2, 12) +#define PINID_EMI_A04 MXS_PIN_ENCODE(2, 13) +#define PINID_EMI_A05 MXS_PIN_ENCODE(2, 14) +#define PINID_EMI_A06 MXS_PIN_ENCODE(2, 15) +#define PINID_EMI_A07 MXS_PIN_ENCODE(2, 16) +#define PINID_EMI_A08 MXS_PIN_ENCODE(2, 17) +#define PINID_EMI_A09 MXS_PIN_ENCODE(2, 18) +#define PINID_EMI_A10 MXS_PIN_ENCODE(2, 19) +#define PINID_EMI_A11 MXS_PIN_ENCODE(2, 20) +#define PINID_EMI_A12 MXS_PIN_ENCODE(2, 21) +#define PINID_EMI_BA0 MXS_PIN_ENCODE(2, 22) +#define PINID_EMI_BA1 MXS_PIN_ENCODE(2, 23) +#define PINID_EMI_CASN MXS_PIN_ENCODE(2, 24) +#define PINID_EMI_CE0N MXS_PIN_ENCODE(2, 25) +#define PINID_EMI_CE1N MXS_PIN_ENCODE(2, 26) +#define PINID_GPMI_CE1N MXS_PIN_ENCODE(2, 27) +#define PINID_GPMI_CE0N MXS_PIN_ENCODE(2, 28) +#define PINID_EMI_CKE MXS_PIN_ENCODE(2, 29) +#define PINID_EMI_RASN MXS_PIN_ENCODE(2, 30) +#define PINID_EMI_WEN MXS_PIN_ENCODE(2, 31) + +/* Bank 3 */ +#define PINID_EMI_D00 MXS_PIN_ENCODE(3, 0) +#define PINID_EMI_D01 MXS_PIN_ENCODE(3, 1) +#define PINID_EMI_D02 MXS_PIN_ENCODE(3, 2) +#define PINID_EMI_D03 MXS_PIN_ENCODE(3, 3) +#define PINID_EMI_D04 MXS_PIN_ENCODE(3, 4) +#define PINID_EMI_D05 MXS_PIN_ENCODE(3, 5) +#define PINID_EMI_D06 MXS_PIN_ENCODE(3, 6) +#define PINID_EMI_D07 MXS_PIN_ENCODE(3, 7) +#define PINID_EMI_D08 MXS_PIN_ENCODE(3, 8) +#define PINID_EMI_D09 MXS_PIN_ENCODE(3, 9) +#define PINID_EMI_D10 MXS_PIN_ENCODE(3, 10) +#define PINID_EMI_D11 MXS_PIN_ENCODE(3, 11) +#define PINID_EMI_D12 MXS_PIN_ENCODE(3, 12) +#define PINID_EMI_D13 MXS_PIN_ENCODE(3, 13) +#define PINID_EMI_D14 MXS_PIN_ENCODE(3, 14) +#define PINID_EMI_D15 MXS_PIN_ENCODE(3, 15) +#define PINID_EMI_DQM0 MXS_PIN_ENCODE(3, 16) +#define PINID_EMI_DQM1 MXS_PIN_ENCODE(3, 17) +#define PINID_EMI_DQS0 MXS_PIN_ENCODE(3, 18) +#define PINID_EMI_DQS1 MXS_PIN_ENCODE(3, 19) +#define PINID_EMI_CLK MXS_PIN_ENCODE(3, 20) +#define PINID_EMI_CLKN MXS_PIN_ENCODE(3, 21) + +#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-mx23/mx23evk.c b/arch/arm/mach-mx23/mx23evk.c new file mode 100644 index 000000000000..823718ba4ec2 --- /dev/null +++ b/arch/arm/mach-mx23/mx23evk.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "device.h" +#include "mx23evk.h" +#include "mx23_pins.h" + +static struct mxs_mma7450_platform_data mma7450_platdata = { + .reg_dvdd_io = "vddio", + .reg_avdd = "vdda", + .gpio_pin_get = mx23evk_mma7450_pin_init, + .gpio_pin_put = mx23evk_mma7450_pin_release, + /* int1 and int2 will be initialized in + i2c_device_init */ + .int1 = 0, + .int2 = 0, +}; + +static struct i2c_board_info __initdata mma7450_i2c_device = { + I2C_BOARD_INFO("mma7450", 0x1d), + .platform_data = (void *)&mma7450_platdata, +}; + +static void i2c_device_init(void) +{ + mma7450_platdata.int1 = gpio_to_irq(MXS_PIN_TO_GPIO(PINID_GPMI_D14)); + mma7450_platdata.int2 = gpio_to_irq(MXS_PIN_TO_GPIO(PINID_GPMI_D15)); + i2c_register_board_info(0, &mma7450_i2c_device, 1); +} + +static struct spi_board_info spi_board_info[] __initdata = { +#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) + { + .modalias = "enc28j60", + .max_speed_hz = 6 * 1000 * 1000, + .bus_num = 1, + .chip_select = 0, + }, +#endif +}; + +static void spi_device_init(void) +{ + spi_board_info[0].irq = gpio_to_irq(MXS_PIN_TO_GPIO(PINID_SSP1_DATA1)); + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +} + +static void __init fixup_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mx23_set_input_clk(24000000, 24000000, 32000, 50000000); +} + +#if defined(CONFIG_SND_MXS_SOC_ADC) || defined(CONFIG_SND_MXS_SOC_ADC_MODULE) +static void __init mx23evk_init_adc(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-adc", 0); + if (pdev == NULL) + return; + mxs_add_device(pdev, 3); +} +#else +static void __init mx23evk_init_adc(void) +{ + +} +#endif + +#define REGS_OCOTP_BASE IO_ADDRESS(OCOTP_PHYS_ADDR) +int get_evk_board_version() +{ + int boardid; + boardid = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTCAP); + boardid &= 0x30000000; + boardid = boardid >> 28; + + return boardid; +} +EXPORT_SYMBOL_GPL(get_evk_board_version); + +static void __init mx23evk_device_init(void) +{ + /* Add mx23evk special code */ + i2c_device_init(); + spi_device_init(); + mx23evk_init_adc(); +} + + +static void __init mx23evk_init_machine(void) +{ + mx23_pinctrl_init(); + + /* Init iram allocate */ +#ifdef CONFIG_VECTORS_PHY_ADDR + /* reserve the first page for irq vectors table*/ + iram_init(MX23_OCRAM_PHBASE + PAGE_SIZE, MX23_OCRAM_SIZE - PAGE_SIZE); +#else + iram_init(MX23_OCRAM_PHBASE, MX23_OCRAM_SIZE); +#endif + + mx23_gpio_init(); + mx23evk_pins_init(); + mx23evk_mma7450_pin_init(); + mx23_device_init(); + mx23evk_device_init(); + + /* init the system revesion */ + system_rev = 0x23004; +} + +MACHINE_START(MX23EVK, "Freescale MX23EVK board") + .phys_io = 0x80000000, + .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, + .boot_params = 0x40000100, + .fixup = fixup_board, + .map_io = mx23_map_io, + .init_irq = mx23_irq_init, + .init_machine = mx23evk_init_machine, + .timer = &mx23_timer.timer, +MACHINE_END diff --git a/arch/arm/mach-mx23/mx23evk.h b/arch/arm/mach-mx23/mx23evk.h new file mode 100644 index 000000000000..ea2ab4def477 --- /dev/null +++ b/arch/arm/mach-mx23/mx23evk.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_MACH_MX23EVK_H +#define __ASM_ARM_MACH_MX23EVK_H + +extern void __init mx23evk_pins_init(void); +extern void mx23evk_mma7450_pin_init(void); +extern int mx23evk_mma7450_pin_release(void); +extern int mxs_spi_enc_pin_init(void); +extern int mxs_spi_enc_pin_release(void); +extern int mxs_mmc_get_wp_mmc0(void); +extern int mxs_mmc_hw_init_mmc0(void); +extern void mxs_mmc_hw_release_mmc0(void); +extern void mxs_mmc_cmd_pullup_mmc0(int enable); + +#endif /* __ASM_ARM_MACH_MX23EVK_H */ diff --git a/arch/arm/mach-mx23/mx23evk_pins.c b/arch/arm/mach-mx23/mx23evk_pins.c new file mode 100644 index 000000000000..cdf86cfbea63 --- /dev/null +++ b/arch/arm/mach-mx23/mx23evk_pins.c @@ -0,0 +1,939 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "mx23_pins.h" + +static struct pin_desc mx23evk_fixed_pins[] = { + { + .name = "DUART.RX", + .id = PINID_PWM0, + .fun = PIN_FUN3, + }, + { + .name = "DUART.TX", + .id = PINID_PWM1, + .fun = PIN_FUN3, + }, +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE + { + .name = "AUART1.RX", + .id = PINID_AUART1_RX, + .fun = PIN_FUN1, + }, + { + .name = "AUART1.TX", + .id = PINID_AUART1_TX, + .fun = PIN_FUN1, + }, + { + .name = "AUART1.CTS", + .id = PINID_AUART1_CTS, + .fun = PIN_FUN1, + }, + { + .name = "AUART1.RTS", + .id = PINID_AUART1_RTS, + .fun = PIN_FUN1, + }, +#endif + +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE + { + .name = "AUART2.RX", + .id = PINID_GPMI_D14, + .fun = PIN_FUN2, + }, + { + .name = "AUART2.TX", + .id = PINID_GPMI_D15, + .fun = PIN_FUN2, + }, + { + .name = "AUART2.CTS", + .id = PINID_ROTARYB, + .fun = PIN_FUN2, + }, + { + .name = "AUART2.RTS", + .id = PINID_ROTARYA, + .fun = PIN_FUN2, + }, +#endif +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) + { + .name = "I2C_SCL", + .id = PINID_I2C_SCL, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "I2C_SDA", + .id = PINID_I2C_SDA, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) + { + .name = "LCD_D00", + .id = PINID_LCD_D00, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D01", + .id = PINID_LCD_D01, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D02", + .id = PINID_LCD_D02, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D03", + .id = PINID_LCD_D03, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D04", + .id = PINID_LCD_D04, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D05", + .id = PINID_LCD_D05, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D06", + .id = PINID_LCD_D06, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D07", + .id = PINID_LCD_D07, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D08", + .id = PINID_LCD_D08, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D09", + .id = PINID_LCD_D09, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D10", + .id = PINID_LCD_D10, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D11", + .id = PINID_LCD_D11, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D12", + .id = PINID_LCD_D12, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D13", + .id = PINID_LCD_D13, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D14", + .id = PINID_LCD_D14, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D15", + .id = PINID_LCD_D15, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D16", + .id = PINID_LCD_D16, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D17", + .id = PINID_LCD_D17, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D18", + .id = PINID_GPMI_D08, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D19", + .id = PINID_GPMI_D09, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D20", + .id = PINID_GPMI_D10, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D21", + .id = PINID_GPMI_D11, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D22", + .id = PINID_GPMI_D12, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D23", + .id = PINID_GPMI_D13, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_RESET", + .id = PINID_LCD_RESET, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_VSYNC", + .id = PINID_LCD_VSYNC, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_HSYNC", + .id = PINID_LCD_HSYNC, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_ENABLE", + .id = PINID_LCD_ENABLE, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_DOTCLK", + .id = PINID_LCD_DOTCK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_BACKLIGHT", + .id = PINID_PWM2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) + { + .name = "ENET0_MDC", + .id = PINID_ENET0_MDC, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_MDIO", + .id = PINID_ENET0_MDIO, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RX_EN", + .id = PINID_ENET0_RX_EN, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RXD0", + .id = PINID_ENET0_RXD0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RXD1", + .id = PINID_ENET0_RXD1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TX_EN", + .id = PINID_ENET0_TX_EN, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TXD0", + .id = PINID_ENET0_TXD0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TXD1", + .id = PINID_ENET0_TXD1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET_CLK", + .id = PINID_ENET_CLK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +#if defined(CONFIG_USB_OTG) + { + .name = "USB_OTG_ID", + .id = PINID_ROTARYA, + .fun = PIN_GPIO, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + }, +#endif +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) + { + .name = "SPDIF", + .id = PINID_ROTARYA, + .fun = PIN_FUN3, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif + +#if defined(CONFIG_MTD_NAND_GPMI_NFC) || \ + defined(CONFIG_MTD_NAND_GPMI_NFC_MODULE) + { + .name = "GPMI D0", + .id = PINID_GPMI_D00, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D1", + .id = PINID_GPMI_D01, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D2", + .id = PINID_GPMI_D02, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D3", + .id = PINID_GPMI_D03, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D4", + .id = PINID_GPMI_D04, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D5", + .id = PINID_GPMI_D05, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D6", + .id = PINID_GPMI_D06, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D7", + .id = PINID_GPMI_D07, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CLE", + .id = PINID_GPMI_CLE, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI ALE", + .id = PINID_GPMI_ALE, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI WPN-", + .id = PINID_GPMI_WPN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI WR-", + .id = PINID_GPMI_WRN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RD-", + .id = PINID_GPMI_RDN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RDY0", + .id = PINID_GPMI_RDY0, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RDY1", + .id = PINID_GPMI_RDY1, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CE0-", + .id = PINID_GPMI_CE0N, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CE1-", + .id = PINID_GPMI_CE1N, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, +#endif + +}; + +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) +static struct pin_desc mx23evk_mmc_pins[] = { + /* Configurations of SSP0 SD/MMC port pins */ + { + .name = "SSP1_DATA0", + .id = PINID_SSP1_DATA0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA1", + .id = PINID_SSP1_DATA1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA2", + .id = PINID_SSP1_DATA2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA3", + .id = PINID_SSP1_DATA3, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_CMD", + .id = PINID_SSP1_CMD, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DETECT", + .id = PINID_SSP1_DETECT, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "SSP1_SCK", + .id = PINID_SSP1_SCK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, +}; +#endif + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct pin_desc mx23evk_spi_pins[] = { + { + .name = "SSP1_DATA0", + .id = PINID_SSP1_DATA0, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP1_DATA3", + .id = PINID_SSP1_DATA3, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP1_CMD", + .id = PINID_SSP1_CMD, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP1_SCK", + .id = PINID_SSP1_SCK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +}; +#endif + + +static void mxs_request_pins(struct pin_desc *pins, int nr) +{ + int i; + struct pin_desc *pin; + + /* configure the pins */ + for (i = 0; i < nr; i++) { + pin = &pins[i]; + if (pin->fun == PIN_GPIO) + gpio_request(MXS_PIN_TO_GPIO(pin->id), pin->name); + else + mxs_request_pin(pin->id, pin->fun, pin->name); + if (pin->drive) { + mxs_set_strength(pin->id, pin->strength, pin->name); + mxs_set_voltage(pin->id, pin->voltage, pin->name); + } + if (pin->pull) + mxs_set_pullup(pin->id, pin->pullup, pin->name); + if (pin->fun == PIN_GPIO) { + if (pin->output) + gpio_direction_output(MXS_PIN_TO_GPIO(pin->id), + pin->data); + else + gpio_direction_input(MXS_PIN_TO_GPIO(pin->id)); + } + } +} + +static void mxs_release_pins(struct pin_desc *pins, int nr) +{ + int i; + struct pin_desc *pin; + + /* release the pins */ + for (i = 0; i < nr; i++) { + pin = &pins[i]; + if (pin->fun == PIN_GPIO) + gpio_free(MXS_PIN_TO_GPIO(pin->id)); + else + mxs_release_pin(pin->id, pin->name); + } +} + +#if defined(CONFIG_MXC_MMA7450) || defined(CONFIG_MXC_MMA7450_MODULE) +int mx23evk_mma7450_pin_init(void) +{ + /* intr */ + gpio_request(MXS_PIN_TO_GPIO(PINID_GPMI_D14), "MMA7450_INTR1"); + gpio_direction_input(MXS_PIN_TO_GPIO(PINID_GPMI_D14)); + gpio_request(MXS_PIN_TO_GPIO(PINID_GPMI_D15), "MMA7450_INTR2"); + gpio_direction_input(MXS_PIN_TO_GPIO(PINID_GPMI_D15)); + return 0; +} +int mx23evk_mma7450_pin_release(void) +{ + return 0; +} +#else +int mx23evk_mma7450_pin_init(void) +{ + return 0; +} +int mx23evk_mma7450_pin_release(void) +{ + return 0; +} +#endif + +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) +#define MMC0_POWER MXS_PIN_TO_GPIO(PINID_PWM3) +#define MMC0_WP MXS_PIN_TO_GPIO(PINID_PWM4) + +int mxs_mmc_get_wp_mmc0(void) +{ + return gpio_get_value(MMC0_WP); +} + +int mxs_mmc_hw_init_mmc0(void) +{ + int ret = 0; + + mxs_request_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins)); + + /* Configure write protect GPIO pin */ + ret = gpio_request(MMC0_WP, "mmc0_wp"); + if (ret) { + pr_err("wp\n"); + goto out_wp; + } + gpio_set_value(MMC0_WP, 0); + gpio_direction_input(MMC0_WP); + + /* Configure POWER pin as gpio to drive power to MMC slot */ + ret = gpio_request(MMC0_POWER, "mmc0_power"); + if (ret) { + pr_err("power\n"); + goto out_power; + } + gpio_direction_output(MMC0_POWER, 0); + mdelay(100); + + return 0; + +out_power: + gpio_free(MMC0_WP); +out_wp: + mxs_release_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins)); + return ret; +} + +void mxs_mmc_hw_release_mmc0(void) +{ + gpio_free(MMC0_POWER); + gpio_free(MMC0_WP); + + mxs_release_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins)); +} + +void mxs_mmc_cmd_pullup_mmc0(int enable) +{ + mxs_set_pullup(PINID_SSP1_CMD, enable, "mmc0_cmd"); +} +#else +int mxs_mmc_get_wp_mmc0(void) +{ + return 0; +} +int mxs_mmc_hw_init_mmc0(void) +{ + return 0; +} + +void mxs_mmc_hw_release_mmc0(void) +{ +} + +void mxs_mmc_cmd_pullup_mmc0(int enable) +{ +} +#endif + +#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) +int mxs_spi_enc_pin_init(void) +{ + unsigned gpio = MXS_PIN_TO_GPIO(PINID_SSP1_DATA1); + + mxs_request_pins(mx23evk_spi_pins, ARRAY_SIZE(mx23evk_spi_pins)); + + gpio_request(gpio, "ENC28J60_INTR"); + gpio_direction_input(gpio); + set_irq_type(gpio_to_irq(gpio), IRQ_TYPE_EDGE_FALLING); + + return 0; +} +int mxs_spi_enc_pin_release(void) +{ + unsigned gpio = MXS_PIN_TO_GPIO(PINID_SSP1_DATA1); + + + gpio_free(gpio); + set_irq_type(gpio_to_irq(gpio), IRQ_TYPE_NONE); + + /* release the pins */ + mxs_release_pins(mx23evk_spi_pins, ARRAY_SIZE(mx23evk_spi_pins)); + + return 0; +} +#else +int mxs_spi_enc_pin_init(void) +{ + return 0; +} +int mxs_spi_enc_pin_release(void) +{ + return 0; +} +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +int mx23evk_enet_gpio_init(void) +{ + /* pwr */ + gpio_request(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), "ENET_PWR"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0); + + /* reset phy */ + gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), "PHY_RESET"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1); + + return 0; +} +#else +int mx23evk_enet_gpio_init(void) +{ + return 0; +} +#endif + +void __init mx23evk_pins_init(void) +{ + mxs_request_pins(mx23evk_fixed_pins, ARRAY_SIZE(mx23evk_fixed_pins)); +} diff --git a/arch/arm/mach-mx23/otp.c b/arch/arm/mach-mx23/otp.c new file mode 100644 index 000000000000..7bec45f3754c --- /dev/null +++ b/arch/arm/mach-mx23/otp.c @@ -0,0 +1,437 @@ +/* + * Unique ID manipulation: Freescale STMP378X OTP bits read/write procedures + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static DEFINE_MUTEX(otp_mutex); +static unsigned otp_mode; +static unsigned long otp_hclk_saved; +static u32 otp_voltage_saved; + +static int otp_full; /* = 0. By default, show/set only customer bits */ +#define OTP_USER_OFFSET 0 +#define OTP_USER_SIZE 4 + +#define REGS_OCOTP_BASE (IO_ADDRESS(OCOTP_PHYS_ADDR)) +#define BF(value, field) (((value) << BP_##field) & BM_##field) +/** + * otp_wait_busy - wait for completion of operation + * + * @flags: flags that should be clear in addition to _BUSY and _ERROR + * + * Returns 0 on success or -ETIMEDOUT on error + **/ +static int otp_wait_busy(u32 flags) +{ + int count; + u32 c; + + for (count = 10000; count >= 0; count--) { + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags))) + break; + cpu_relax(); + } + if (count < 0) + return -ETIMEDOUT; + return 0; +} + +/** + * otp_open - open OTP bits for read or write access + * + * @mode: either O_RDONLY or O_WRONLY + * + * Returns 0 on success, error code otherwise + **/ +static int otp_open(int mode) +{ + int r; + struct clk *hclk; + int err; + + if (!mutex_trylock(&otp_mutex)) { + printk(KERN_ERR"%s: already opened\n", __func__); + return -EAGAIN; + } + + if (mode == O_RDONLY) { + pr_debug("%s: read-only mode\n", __func__); + + r = otp_wait_busy(0); + if (r) { + err = -ETIMEDOUT; + goto out; + } + + /* 2. Set RD_BANK_OPEN */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + udelay(10); + + otp_wait_busy(0); + } + + else if (mode == O_WRONLY) { + pr_debug("%s: write-only mode\n", __func__); + hclk = clk_get(NULL, "hclk"); + if (IS_ERR(hclk)) { + err = PTR_ERR(hclk); + goto out; + } + + /* + WARNING ACHTUNG UWAGA + + the code below changes HCLK clock rate to 24M. This is + required to write OTP bits (7.2.2 in STMP378x Target + Specification), and might affect LCD operation, for example. + Moreover, this hacky code changes VDDIO to 2.8V; and resto- + res it only on otp_close(). This may affect... anything. + + You are warned now. + */ + otp_hclk_saved = clk_get_rate(hclk); + clk_set_rate(hclk, 24000); + /* Set the voltage to 2.8V */ + otp_voltage_saved = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + __raw_writel( + (otp_voltage_saved & ~BM_POWER_VDDIOCTRL_TRG) | 0x00, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + + r = otp_wait_busy(BM_OCOTP_CTRL_RD_BANK_OPEN); + if (r < 0) { + __raw_writel(otp_voltage_saved, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + clk_set_rate(hclk, otp_hclk_saved); + clk_put(hclk); + err = -ETIMEDOUT; + goto out; + } + + clk_put(hclk); + } + + else { + pr_debug("%s: unknown mode '%d'\n", __func__, mode); + err = -EINVAL; + goto out; + } + + otp_mode = mode; + return 0; +out: + mutex_unlock(&otp_mutex); + pr_debug("%s: status %d\n", __func__, err); + return err; +} + +/** + * otp_close - close the OTP bits after opening by otp_open + **/ +static void otp_close(void) +{ + struct clk *hclk; + + if (!mutex_is_locked(&otp_mutex)) { + printk(KERN_ERR"%s: wasn't opened\n", __func__); + return; + } + + if (otp_mode == O_RDONLY) { + /* 5. clear RD_BANK_OPEN */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, REGS_OCOTP_BASE + HW_OCOTP_CTRL_CLR); + } + + else if (otp_mode == O_WRONLY) { + hclk = clk_get(NULL, "hclk"); + clk_set_rate(hclk, otp_hclk_saved); + __raw_writel(otp_voltage_saved, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + otp_wait_busy(0); + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + } + + else { + return; /* -EINVAL. Who does really check close? */ + } + + otp_mode = 0; + mutex_unlock(&otp_mutex); +} + +/** + * otp_read_bits - read the content of OTP + * + * @start: offset from 0, in u32's + * @len: number of OTP u32's to read + * @bits: caller-allocated buffer to save bits + * @size: size of @bits + * + * Returns number of u32's saved to buffer + **/ +static size_t otp_read_bits(int start, int len, u32 *bits, size_t size) +{ + int ofs; + + BUG_ON(!mutex_is_locked(&otp_mutex)); + + /* read all stuff that caller needs */ + if (start + len > 4 * 8) /* 4 banks, 8 registers each */ + len = 4 * 8 - start; + + for (ofs = start; ofs < len; ofs++) { + if (size/sizeof(*bits) <= 0) /* we drained out the buffer */ + break; + *bits = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(ofs)); + bits++; + size -= sizeof(*bits); + } + + return ofs - start; /* number of u32's that we saved to buffer */ +} + +/** + * otp_write_bits - store OTP bits + * + * @offset: offset from 0, in u32's + * @data: the u32 to write + * @magic: the magic value to be stored in UNLOCK field + * + **/ +static int otp_write_bits(int offset, u32 data, u32 magic) +{ + u32 c; + int r; + + BUG_ON(!mutex_is_locked(&otp_mutex)); + + if (offset < 0 || offset > 0x1F) + return -EINVAL; + + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + c &= ~BM_OCOTP_CTRL_ADDR; + c |= BF(offset, OCOTP_CTRL_ADDR); + c |= BF(magic, OCOTP_CTRL_WR_UNLOCK); + __raw_writel(c, REGS_OCOTP_BASE + HW_OCOTP_CTRL); + + __raw_writel(data, REGS_OCOTP_BASE + HW_OCOTP_DATA); + + r = otp_wait_busy(0); + if (r < 0) + return r; + + udelay(2); + return 0; +} + +static ssize_t otp_id_show(void *context, char *page, int ascii) +{ + char s[60]; + int ret; + int n, i, j, r; + u32 otp_bits[4 * 8]; + + r = otp_open(O_RDONLY); + if (r < 0) + return 0; + n = otp_read_bits(0, 4 * 8, otp_bits, sizeof(otp_bits)); + otp_close(); + + ret = 0; + + + if (ascii) { + + strcpy(page, ""); + ret = 0; + + if (otp_full) { + for (i = 0; i < 4; i++) { + + ret += sprintf(s, "Bank %d: ", i); + strcat(page, s); + + for (j = 0; j < 8; j++) { + + if (i * 4 + j > n) + break; + ret += sprintf(s, "%08X ", + otp_bits[i * 4 + j]); + strcat(page, s); + } + + strcat(page, "\n"); + ret++; + } + } else { + for (i = 0; i < OTP_USER_SIZE; i++) { + ret += sprintf(s, "%08X ", + otp_bits[i + OTP_USER_OFFSET]); + strcat(page, s); + } + strcat(page, "\n"); + ret++; + } + } else { + + if (otp_full) { + memcpy(page, otp_bits, sizeof(otp_bits)); + ret = sizeof(otp_bits); + } else { + memcpy(page, otp_bits + OTP_USER_OFFSET, + OTP_USER_SIZE * sizeof(u32)); + ret = OTP_USER_SIZE * sizeof(u32); + } + } + + return ret; +} + +static int otp_check_dry_run(const char *page, size_t count) +{ + if (count >= 3 && memcmp(page, "+++", 3) == 0) + return 3; + return 0; +} + +static ssize_t otp_id_store(void *context, const char *page, + size_t count, int ascii) +{ + int r = 0; + const char *p, *cp, *d; + unsigned long index, value; + char tmps[20]; /* subject of strtoul */ + int dry_run; + + r = otp_open(O_WRONLY); + if (r < 0) { + printk(KERN_ERR"Cannot open OTP in WRITE mode\n"); + return r; + } + + if (ascii) { + + dry_run = otp_check_dry_run(page, count); + if (dry_run > 0) + page += dry_run; + + index = 0; + cp = page; + + memset(tmps, 0, sizeof(tmps)); + + for (index = 0, cp = page; cp != NULL; index++) { + p = strchr(cp, ','); + + d = strchr(cp, ':'); + if (d && (!p || d < p)) { + strncpy(tmps, cp, + min_t(int, d - cp, sizeof(tmps) - 1)); + r = strict_strtoul(tmps, 0, &index); + if (r < 0) { + pr_debug("Cannot parse '%s'\n", tmps); + break; + } + cp = d + 1; + } + + memset(tmps, 0, sizeof(tmps)); + + if (!p) + strncpy(tmps, cp, sizeof(tmps)); + else + strncpy(tmps, cp, + min_t(int, p - cp, sizeof(tmps) - 1)); + r = strict_strtoul(tmps, 0, &value); + if (r < 0) { + pr_debug("Cannot parse '%s'\n", tmps); + break; + } + + memset(tmps, 0, sizeof(tmps)); + + cp = p ? ++p : NULL; + + if (!otp_full) { + index += OTP_USER_OFFSET; + if (index > OTP_USER_SIZE) { + printk(KERN_ERR"Cannot write at " + "offset %ld\n", index); + continue; + } + } + + r = 0; + if (!dry_run) { + pr_debug("Index %ld, value 0x%08lx\n", + index, value); + r = otp_write_bits(index, value, 0x3e77); + } else + printk(KERN_NOTICE + "Dry-run: writing 0x%08lX => [%ld]\n", + value, index); + if (r < 0) + break; + } + } else { + printk(KERN_ERR"Binary write is not supported\n"); + r = -ENOSYS; + } + otp_close(); + return (r >= 0) ? count : r; +} + +static struct uid_ops otp_ops = { + .id_show = otp_id_show, + .id_store = otp_id_store, +}; + +static int __init_or_module otp_init(void) +{ + void *p; + + mutex_init(&otp_mutex); + p = uid_provider_init("otp", &otp_ops, NULL); + if (IS_ERR(p)) + return PTR_ERR(p); + return 0; +} + +static void __exit otp_remove(void) +{ + uid_provider_remove("otp"); +} + +module_param(otp_full, int, 0600); +module_init(otp_init); +module_exit(otp_remove); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("dmitry pervushin "); +MODULE_DESCRIPTION("Unique ID: OTP"); diff --git a/arch/arm/mach-mx23/pinctrl.c b/arch/arm/mach-mx23/pinctrl.c new file mode 100644 index 000000000000..0cb85e2674ef --- /dev/null +++ b/arch/arm/mach-mx23/pinctrl.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx23_pin2id(struct pinctrl_chip *chip, unsigned int pin, unsigned int *id) +{ + int bank; + bank = MXS_PIN_TO_BANK(pin & MXS_GPIO_MASK); + if (bank == MXS_PIN_BANK_MAX) + return -EINVAL; + *id = MXS_PIN_TO_PINID(pin & MXS_GPIO_MASK); + return bank; +} + +static unsigned int mx23_get_gpio(struct pin_bank *bank, unsigned int id) +{ + if (bank->gpio_port >= MXS_NON_GPIO) + return -EINVAL; + return bank->gpio_port * PINS_PER_BANK + id; +} + +static void mx23_set_strength(struct pin_bank *bank, + unsigned int id, enum pad_strength strength) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id *= 4; + __raw_writel(PAD_CLEAR << id, addr + CLR_REGISTER); + __raw_writel(strength << id, addr + SET_REGISTER); +} + +static void mx23_set_voltage(struct pin_bank *bank, + unsigned int id, enum pad_voltage volt) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id = id * 4 + 2; + if (volt == PAD_1_8V) + __raw_writel(1 << id, addr + CLR_REGISTER); + else + __raw_writel(1 << id, addr + SET_REGISTER); +} + +static void mx23_set_pullup(struct pin_bank *bank, unsigned int id, int pullup) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_PULL0; + addr += 0x10 * bank->id; + if (pullup) + __raw_writel(1 << id, addr + SET_REGISTER); + else + __raw_writel(1 << id, addr + CLR_REGISTER); +} + +static void mx23_set_type(struct pin_bank *bank, + unsigned int id, enum pin_fun cfg) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_MUXSEL0; + addr += 0x20 * bank->id + 0x10 * (id >> 4); + id &= 0xF; + id *= 2; + __raw_writel(0x3 << id, addr + CLR_REGISTER); + __raw_writel(cfg << id, addr + SET_REGISTER); +} + +static struct pin_bank mx23_pin_banks[6] = { + [0] = { + .id = 0, + .gpio_port = 0, + }, + [1] = { + .id = 1, + .gpio_port = 1, + }, + [2] = { + .id = 2, + .gpio_port = 2, + }, + [3] = { + .id = 3, + .gpio_port = 3, + }, + [4] = { + .id = 4, + .gpio_port = 4, + }, + [5] = { + .id = 5, + .gpio_port = MXS_NON_GPIO, + } +}; + +static struct pinctrl_chip mx23_pinctrl = { + .name = "pinctrl", + .banks = mx23_pin_banks, + .pin2id = mx23_pin2id, + .get_gpio = mx23_get_gpio, + .set_strength = mx23_set_strength, + .set_voltage = mx23_set_voltage, + .set_pullup = mx23_set_pullup, + .set_type = mx23_set_type, +}; + +int __init mx23_pinctrl_init(void) +{ + int i; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + mx23_pinctrl.bank_size = ARRAY_SIZE(mx23_pin_banks); + return mxs_set_pinctrl_chip(&mx23_pinctrl); +} diff --git a/arch/arm/mach-mx23/pm.c b/arch/arm/mach-mx23/pm.c new file mode 100644 index 000000000000..8512be14b367 --- /dev/null +++ b/arch/arm/mach-mx23/pm.c @@ -0,0 +1,652 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include "regs-clkctrl.h" +#include "regs-pinctrl.h" +#include +#include +#include +#include +#include "regs-dram.h" + +#include "sleep.h" + +#define PENDING_IRQ_RETRY 100 +static void *saved_sram; +static int saved_sleep_state; + +#define WAIT_DC_OK_CYCLES 24000 +#define WAIT_CYCLE(n) for (i = 0; i < n; i++); +#define LOWER_VDDIO 10 +#define LOWER_VDDA 9 +#define LOWER_VDDD 8 +#define MAX_POWEROFF_CODE_SIZE (6 * 1024) +#define REGS_CLKCTRL_BASE IO_ADDRESS(CLKCTRL_PHYS_ADDR) + +static void mx23_standby(void) +{ + int i; + u32 reg_vddd, reg_vdda, reg_vddio; + /* DDR EnterSelfrefreshMode */ + __raw_writel( + BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(0x2) | + __raw_readl(IO_ADDRESS(DRAM_PHYS_ADDR) + + HW_DRAM_CTL16), + IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL16); + + __raw_writel( + BF_DRAM_CTL16_LOWPOWER_CONTROL(0x2) | + __raw_readl(IO_ADDRESS(DRAM_PHYS_ADDR) + + HW_DRAM_CTL16), + IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL16); + /* Gating EMI CLock */ + __raw_writel(BM_CLKCTRL_EMI_CLKGATE | + __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI), + REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI); + + /* Disable PLL */ + __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER, + REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0_CLR); + + /* Reduce the VDDIO (3.050 volt) */ + reg_vddio = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + __raw_writel(reg_vddio | BM_POWER_VDDIOCTRL_BO_OFFSET, + REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) & + ~BM_POWER_VDDIOCTRL_TRG) | LOWER_VDDIO, + REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + WAIT_CYCLE(WAIT_DC_OK_CYCLES) + + while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BM_POWER_STS_DC_OK)) + ; + + /* Reduce VDDA 1.725volt */ + reg_vdda = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL); + __raw_writel(reg_vdda | BM_POWER_VDDACTRL_BO_OFFSET, + REGS_POWER_BASE + HW_POWER_VDDACTRL); + __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL) & + ~BM_POWER_VDDACTRL_TRG) | LOWER_VDDA, + REGS_POWER_BASE + HW_POWER_VDDACTRL); + WAIT_CYCLE(WAIT_DC_OK_CYCLES) + + /* wait for DC_OK */ + while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BM_POWER_STS_DC_OK)) + ; + + /* Reduce VDDD 1.000 volt */ + reg_vddd = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL); + __raw_writel(reg_vddd | BM_POWER_VDDDCTRL_BO_OFFSET, + REGS_POWER_BASE + HW_POWER_VDDDCTRL); + __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL) & + ~BM_POWER_VDDDCTRL_TRG) | LOWER_VDDD, + REGS_POWER_BASE + HW_POWER_VDDDCTRL); + WAIT_CYCLE(WAIT_DC_OK_CYCLES) + + while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BM_POWER_STS_DC_OK)) + ; + + /* optimize the DCDC loop gain */ + __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_LOOPCTRL) & + ~BM_POWER_LOOPCTRL_EN_RCSCALE), + REGS_POWER_BASE + HW_POWER_LOOPCTRL); + __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_LOOPCTRL) & + ~BM_POWER_LOOPCTRL_DC_R) | + (2< + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* #define DEBUG */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static int get_voltage(struct mxs_regulator *sreg) +{ + struct mxs_platform_regulator_data *rdata = sreg->rdata; + u32 val = __raw_readl(rdata->control_reg) & 0x1f; + int uv = rdata->min_voltage + val * + (rdata->max_voltage - rdata->min_voltage) / 0x1f; + return uv; +} + +static int get_bo_voltage(struct mxs_regulator *sreg) +{ + int uv; + int offs; + + if (!sreg->parent) + return -EINVAL; + + uv = get_voltage(sreg->parent); + offs = (__raw_readl(sreg->parent->rdata->control_reg) & ~0x700) >> 8; + return uv - 25000*offs; +} + +static int set_voltage(struct mxs_regulator *sreg, int uv) +{ + u32 val, reg, i; + + pr_debug("%s: uv %d, min %d, max %d\n", __func__, + uv, sreg->rdata->min_voltage, sreg->rdata->max_voltage); + + if (uv < sreg->rdata->min_voltage || uv > sreg->rdata->max_voltage) + return -EINVAL; + + val = (uv - sreg->rdata->min_voltage) * 0x1f / + (sreg->rdata->max_voltage - sreg->rdata->min_voltage); + reg = (__raw_readl(sreg->rdata->control_reg) & ~0x1f); + pr_debug("%s: calculated val %d\n", __func__, val); + __raw_writel(val | reg, sreg->rdata->control_reg); + for (i = 20; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + __raw_writel(val | reg, sreg->rdata->control_reg); + for (i = 40000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + for (i = 40000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + +out: + return !i; +} + +static int set_bo_voltage(struct mxs_regulator *sreg, int bo_uv) +{ + int uv; + int offs; + u32 reg; + int i; + + if (!sreg->parent) + return -EINVAL; + + uv = get_voltage(sreg->parent); + offs = (uv - bo_uv) / 25000; + if (offs < 0 || offs > 7) + return -EINVAL; + + reg = (__raw_readl(sreg->parent->rdata->control_reg) & ~0x700); + pr_debug("%s: calculated offs %d\n", __func__, offs); + __raw_writel((offs << 8) | reg, sreg->parent->rdata->control_reg); + + for (i = 10000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + for (i = 10000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + +out: + return !i; +} + +static int enable(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int disable(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int is_enabled(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 1; +} + +static int set_mode(struct mxs_regulator *sreg, int mode) +{ + int ret = 0; + u32 val; + + switch (mode) { + case REGULATOR_MODE_FAST: + val = __raw_readl(sreg->rdata->control_reg); + __raw_writel(val | (1 << 17), sreg->rdata->control_reg); + break; + + case REGULATOR_MODE_NORMAL: + val = __raw_readl(sreg->rdata->control_reg); + __raw_writel(val & ~(1<<17), sreg->rdata->control_reg); + break; + + default: + ret = -EINVAL; + break; + } + return ret; +} + +static int get_mode(struct mxs_regulator *sreg) +{ + u32 val = __raw_readl(sreg->rdata->control_reg) & (1 << 17); + + return val ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; +} + +static struct mxs_platform_regulator_data vddd_data = { + .name = "vddd", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDDCTRL), + .min_voltage = 800000, + .max_voltage = 1575000, +}; + +static struct mxs_platform_regulator_data vdddbo_data = { + .name = "vddd_bo", + .parent_name = "vddd", + .set_voltage = set_bo_voltage, + .get_voltage = get_bo_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .min_voltage = 800000, + .max_voltage = 1575000, +}; + +static struct mxs_platform_regulator_data vdda_data = { + .name = "vdda", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDACTRL), + .min_voltage = 1500000, + .max_voltage = 2275000, +}; + +static struct mxs_platform_regulator_data vddio_data = { + .name = "vddio", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDIOCTRL), + .min_voltage = 2800000, + .max_voltage = 3575000, +}; + +static struct regulator_init_data vddd_init = { + .constraints = { + .name = "vddd", + .min_uV = 800000, + .max_uV = 1575000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + +static struct regulator_init_data vdddbo_init = { + .constraints = { + .name = "vdddbo", + .min_uV = 800000, + .max_uV = 1575000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + + +static struct regulator_init_data vdda_init = { + .constraints = { + .name = "vdda", + .min_uV = 1500000, + .max_uV = 2275000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + + +static struct regulator_init_data vddio_init = { + .constraints = { + .name = "vddio", + .min_uV = 2800000, + .max_uV = 3575000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + +/* now the current regulators */ +/* Restriction: .... no set_current call on root regulator */ +static int main_add_current(struct mxs_regulator *sreg, + int uA) +{ + + pr_debug("%s: enter reg %s, uA=%d\n", + __func__, sreg->regulator.name, uA); + if (uA > 0 && (sreg->cur_current + uA > sreg->rdata->max_current)) + return -EINVAL; + else + sreg->cur_current += uA; + return 0; +} + +static int cur_reg_set_current(struct mxs_regulator *sreg, int uA) +{ + int ret = 0; + unsigned long flags; + + pr_debug("%s: enter reg %s, uA=%d\n", + __func__, sreg->regulator.name, uA); + + if (sreg->parent) { + spin_lock_irqsave(&sreg->parent->lock, flags); + ret = main_add_current(sreg->parent, uA - sreg->cur_current); + spin_unlock_irqrestore(&sreg->parent->lock, flags); + } + + + if ((!ret) || (!sreg->parent)) + goto out; + + if (sreg->mode == REGULATOR_MODE_FAST) + return ret; + + while (ret) { + wait_event(sreg->parent->wait_q , + (uA - sreg->cur_current < + sreg->parent->rdata->max_current - + sreg->parent->cur_current)); + spin_lock_irqsave(&sreg->parent->lock, flags); + ret = main_add_current(sreg->parent, uA - sreg->cur_current); + spin_unlock_irqrestore(&sreg->parent->lock, flags); + } +out: + if (sreg->parent && (uA - sreg->cur_current < 0)) + wake_up_all(&sreg->parent->wait_q); + sreg->cur_current = uA; + return 0; + +} + +static int cur_reg_get_current(struct mxs_regulator *sreg) +{ + return sreg->cur_current; +} + +static int enable_cur_reg(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int disable_cur_reg(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int cur_reg_is_enabled(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 1; +} + +static int cur_reg_set_mode(struct mxs_regulator *sreg, int mode) +{ + int ret = 0; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + case REGULATOR_MODE_FAST: + sreg->mode = mode; + break; + default: + ret = -EINVAL; + break; + } + return ret; +} + +static int cur_reg_get_mode(struct mxs_regulator *sreg) +{ + return sreg->mode; +} + +static struct mxs_platform_regulator_data overall_cur_data = { + .name = "overall_current", + .set_current = cur_reg_set_current, + .get_current = cur_reg_get_current, + .enable = enable_cur_reg, + .disable = disable_cur_reg, + .is_enabled = cur_reg_is_enabled, + .set_mode = cur_reg_set_mode, + .get_mode = cur_reg_get_mode, + .max_current = 0x7fffffff, +}; + +static struct regulator_init_data overall_cur_init = { + .constraints = { + .name = "overall_current", + .valid_modes_mask = REGULATOR_MODE_NORMAL | + REGULATOR_MODE_FAST, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT | + REGULATOR_CHANGE_MODE, + .max_uA = 0x7fffffff, + .min_uA = 0x0, + .always_on = 1, + } +}; + +static struct mxs_platform_regulator_data sibling_cur_data = { + .parent_name = "overall_current", + .set_current = cur_reg_set_current, + .get_current = cur_reg_get_current, + .enable = enable_cur_reg, + .disable = disable_cur_reg, + .is_enabled = cur_reg_is_enabled, + .set_mode = cur_reg_set_mode, + .get_mode = cur_reg_get_mode, +}; + + +static const char *device_names[] = { + "mxs-duart", "mxs-bl", "mxs-i2c" +}; + +static int sibling_current_devices_num; + +int mxs_platform_add_regulator(const char *name, int count) +{ + int i; + pr_debug("%s: name %s, count %d\n", __func__, name, count); + for (i = sibling_current_devices_num; + i < sibling_current_devices_num + count; + i++) { + struct regulator_init_data *sibling_init = + kzalloc(sizeof(struct regulator_init_data), + GFP_KERNEL); + struct mxs_regulator *curr_reg = + kzalloc(sizeof(struct mxs_regulator), + GFP_KERNEL); + struct mxs_platform_regulator_data *d = + kzalloc(sizeof(struct mxs_platform_regulator_data), + GFP_KERNEL); + if (!d || !curr_reg || !sibling_init) + return -ENOMEM; + + sibling_init->constraints.valid_modes_mask = + REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST; + sibling_init->constraints.valid_ops_mask = + REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_MODE; + sibling_init->constraints.max_uA = 0x7fffffff; + sibling_init->constraints.min_uA = 0x0; + + memcpy(d, &sibling_cur_data, sizeof(sibling_cur_data)); + d->parent_name = kstrdup(sibling_cur_data.parent_name, + GFP_KERNEL); + snprintf(d->name, 80, "%s-%d", + name, i - sibling_current_devices_num + 1); + sibling_init->constraints.name = kstrdup(d->name, GFP_KERNEL); + sibling_init->constraints.always_on = 1; + curr_reg->rdata = d; + mxs_register_regulator(curr_reg, 101 + i, sibling_init); + } + sibling_current_devices_num += count; + return 0; +} + +static struct mxs_regulator vddd_reg = { + .rdata = &vddd_data, +}; + +static struct mxs_regulator vdda_reg = { + .rdata = &vdda_data, +}; + +static struct mxs_regulator vddio_reg = { + .rdata = &vddio_data, +}; + +static struct mxs_regulator vdddbo_reg = { + .rdata = &vdddbo_data, +}; + +static struct mxs_regulator overall_cur_reg = { + .rdata = &overall_cur_data, +}; + + +static int __init regulators_init(void) +{ + int i; + int retval = 0; + u32 vddio = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) & ~0x1f; + pr_debug("regulators_init \n"); + __raw_writel(vddio | 0x14, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + vdddbo_reg.parent = &vddd_reg; + mxs_register_regulator(&vddd_reg, MXS_VDDD, &vddd_init); + mxs_register_regulator(&vdddbo_reg, MXS_VDDDBO, &vdddbo_init); + mxs_register_regulator(&vdda_reg, MXS_VDDA, &vdda_init); + mxs_register_regulator(&vddio_reg, MXS_VDDIO, &vddio_init); + mxs_register_regulator(&overall_cur_reg, + MXS_OVERALL_CUR, &overall_cur_init); + + for (i = 0; i < ARRAY_SIZE(device_names); i++) { + retval = mxs_platform_add_regulator(device_names[i], 1); + if (retval) + return retval; + } + mxs_platform_add_regulator("mmc_ssp", 2); + mxs_platform_add_regulator("charger", 1); + mxs_platform_add_regulator("power-test", 1); + mxs_platform_add_regulator("cpufreq", 1); + return 0; +} +postcore_initcall(regulators_init); diff --git a/arch/arm/mach-mx23/regs-clkctrl.h b/arch/arm/mach-mx23/regs-clkctrl.h new file mode 100644 index 000000000000..7b8e089f9707 --- /dev/null +++ b/arch/arm/mach-mx23/regs-clkctrl.h @@ -0,0 +1,442 @@ +/* + * Freescale CLKCTRL Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___CLKCTRL_H +#define __ARCH_ARM___CLKCTRL_H + + +#define HW_CLKCTRL_PLLCTRL0 (0x00000000) +#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) + +#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6) +#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL) +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5) +#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL) +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4) +#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL) +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000 +#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 +#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1) + +#define HW_CLKCTRL_PLLCTRL1 (0x00000010) + +#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1) +#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_CPU (0x00000020) +#define HW_CLKCTRL_CPU_SET (0x00000024) +#define HW_CLKCTRL_CPU_CLR (0x00000028) +#define HW_CLKCTRL_CPU_TOG (0x0000002c) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS (0x00000030) +#define HW_CLKCTRL_HBUS_SET (0x00000034) +#define HW_CLKCTRL_HBUS_CLR (0x00000038) +#define HW_CLKCTRL_HBUS_TOG (0x0000003c) + +#define BP_CLKCTRL_HBUS_RSRVD4 30 +#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000 +#define BF_CLKCTRL_HBUS_RSRVD4(v) \ + (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4) +#define BM_CLKCTRL_HBUS_BUSY 0x20000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000040) + +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 11 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) + +#define HW_CLKCTRL_XTAL (0x00000050) +#define HW_CLKCTRL_XTAL_SET (0x00000054) +#define HW_CLKCTRL_XTAL_CLR (0x00000058) +#define HW_CLKCTRL_XTAL_TOG (0x0000005c) + +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 +#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_PIX (0x00000060) + +#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 +#define BM_CLKCTRL_PIX_RSRVD2 0x40000000 +#define BM_CLKCTRL_PIX_BUSY 0x20000000 +#define BP_CLKCTRL_PIX_RSRVD1 13 +#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000 +#define BF_CLKCTRL_PIX_RSRVD1(v) \ + (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1) +#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 +#define BP_CLKCTRL_PIX_DIV 0 +#define BM_CLKCTRL_PIX_DIV 0x00000FFF +#define BF_CLKCTRL_PIX_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_PIX_DIV) + +#define HW_CLKCTRL_SSP (0x00000070) + +#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP_BUSY 0x20000000 +#define BP_CLKCTRL_SSP_RSRVD1 10 +#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1) +#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP_DIV 0 +#define BM_CLKCTRL_SSP_DIV 0x000001FF +#define BF_CLKCTRL_SSP_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP_DIV) + +#define HW_CLKCTRL_GPMI (0x00000080) + +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x00000090) + +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000a0) + +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) + +#define HW_CLKCTRL_IR (0x000000b0) + +#define BM_CLKCTRL_IR_CLKGATE 0x80000000 +#define BM_CLKCTRL_IR_RSRVD3 0x40000000 +#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 +#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 +#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 +#define BP_CLKCTRL_IR_RSRVD2 25 +#define BM_CLKCTRL_IR_RSRVD2 0x06000000 +#define BF_CLKCTRL_IR_RSRVD2(v) \ + (((v) << 25) & BM_CLKCTRL_IR_RSRVD2) +#define BP_CLKCTRL_IR_IROV_DIV 16 +#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 +#define BF_CLKCTRL_IR_IROV_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) +#define BP_CLKCTRL_IR_RSRVD1 10 +#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00 +#define BF_CLKCTRL_IR_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_IR_RSRVD1) +#define BP_CLKCTRL_IR_IR_DIV 0 +#define BM_CLKCTRL_IR_IR_DIV 0x000003FF +#define BF_CLKCTRL_IR_IR_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_IR_IR_DIV) + +#define HW_CLKCTRL_SAIF (0x000000c0) + +#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF_RSRVD1 17 +#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1) +#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF_DIV 0 +#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF_DIV) + +#define HW_CLKCTRL_TV (0x000000d0) + +#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 +#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 +#define BP_CLKCTRL_TV_RSRVD 0 +#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_TV_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_TV_RSRVD) + +#define HW_CLKCTRL_ETM (0x000000e0) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 7 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000003F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_FRAC (0x000000f0) +#define HW_CLKCTRL_FRAC_SET (0x000000f4) +#define HW_CLKCTRL_FRAC_CLR (0x000000f8) +#define HW_CLKCTRL_FRAC_TOG (0x000000fc) + +#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 +#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC_IOFRAC 24 +#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 +#define BF_CLKCTRL_FRAC_IOFRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 +#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC_PIXFRAC 16 +#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC_PIXFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC_EMIFRAC 8 +#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC) +#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC_CPUFRAC 0 +#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC) + +#define HW_CLKCTRL_FRAC1 (0x00000100) +#define HW_CLKCTRL_FRAC1_SET (0x00000104) +#define HW_CLKCTRL_FRAC1_CLR (0x00000108) +#define HW_CLKCTRL_FRAC1_TOG (0x0000010c) + +#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 +#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC1_RSRVD1 0 +#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF +#define BF_CLKCTRL_FRAC1_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1) + +#define HW_CLKCTRL_CLKSEQ (0x00000110) +#define HW_CLKCTRL_CLKSEQ_SET (0x00000114) +#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) +#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) + +#define BP_CLKCTRL_CLKSEQ_RSRVD1 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004 +#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 + +#define HW_CLKCTRL_RESET (0x00000120) + +#define BP_CLKCTRL_RESET_RSRVD 2 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 2) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 + +#define HW_CLKCTRL_STATUS (0x00000130) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000140) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) +#endif /* __ARCH_ARM___CLKCTRL_H */ diff --git a/arch/arm/mach-mx23/regs-digctl.h b/arch/arm/mach-mx23/regs-digctl.h new file mode 100644 index 000000000000..291ba927f63a --- /dev/null +++ b/arch/arm/mach-mx23/regs-digctl.h @@ -0,0 +1,724 @@ +/* + * Freescale DIGCTL Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___DIGCTL_H +#define __ARCH_ARM___DIGCTL_H + + +#define HW_DIGCTL_CTRL (0x00000000) +#define HW_DIGCTL_CTRL_SET (0x00000004) +#define HW_DIGCTL_CTRL_CLR (0x00000008) +#define HW_DIGCTL_CTRL_TOG (0x0000000c) + +#define BM_DIGCTL_CTRL_RSVD3 0x80000000 +#define BM_DIGCTL_CTRL_XTAL24M_GATE 0x40000000 +#define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 +#define BP_DIGCTL_CTRL_RSVD2 27 +#define BM_DIGCTL_CTRL_RSVD2 0x18000000 +#define BF_DIGCTL_CTRL_RSVD2(v) \ + (((v) << 27) & BM_DIGCTL_CTRL_RSVD2) +#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE 0x04000000 +#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN 0x02000000 +#define BM_DIGCTL_CTRL_LCD_BIST_START 0x01000000 +#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x00800000 +#define BM_DIGCTL_CTRL_DCP_BIST_START 0x00400000 +#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x00200000 +#define BM_DIGCTL_CTRL_USB_TESTMODE 0x00100000 +#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x00080000 +#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x00040000 +#define BM_DIGCTL_CTRL_ARM_BIST_START 0x00020000 +#define BM_DIGCTL_CTRL_UART_LOOPBACK 0x00010000 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x00008000 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 +#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 +#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x00006000 +#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) \ + (((v) << 13) & BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL) +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 +#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x00001000 +#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 +#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x00000800 +#define BM_DIGCTL_CTRL_RSVD1 0x00000400 +#define BM_DIGCTL_CTRL_SY_ENDIAN 0x00000200 +#define BM_DIGCTL_CTRL_SY_SFTRST 0x00000100 +#define BM_DIGCTL_CTRL_SY_CLKGATE 0x00000080 +#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x00000040 +#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 +#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 +#define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x00000020 +#define BM_DIGCTL_CTRL_TRAP_ENABLE 0x00000010 +#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x00000008 +#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 +#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 +#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x00000002 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 +#define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x00000001 + +#define HW_DIGCTL_STATUS (0x00000010) +#define HW_DIGCTL_STATUS_SET (0x00000014) +#define HW_DIGCTL_STATUS_CLR (0x00000018) +#define HW_DIGCTL_STATUS_TOG (0x0000001c) + +#define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 +#define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 +#define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 +#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 +#define BP_DIGCTL_STATUS_RSVD2 11 +#define BM_DIGCTL_STATUS_RSVD2 0x0FFFF800 +#define BF_DIGCTL_STATUS_RSVD2(v) \ + (((v) << 11) & BM_DIGCTL_STATUS_RSVD2) +#define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x00000400 +#define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x00000200 +#define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x00000100 +#define BM_DIGCTL_STATUS_LCD_BIST_FAIL 0x00000080 +#define BM_DIGCTL_STATUS_LCD_BIST_PASS 0x00000040 +#define BM_DIGCTL_STATUS_LCD_BIST_DONE 0x00000020 +#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x00000010 +#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 +#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x0000000E +#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) \ + (((v) << 1) & BM_DIGCTL_STATUS_PACKAGE_TYPE) +#define BM_DIGCTL_STATUS_WRITTEN 0x00000001 + +#define HW_DIGCTL_HCLKCOUNT (0x00000020) +#define HW_DIGCTL_HCLKCOUNT_SET (0x00000024) +#define HW_DIGCTL_HCLKCOUNT_CLR (0x00000028) +#define HW_DIGCTL_HCLKCOUNT_TOG (0x0000002c) + +#define BP_DIGCTL_HCLKCOUNT_COUNT 0 +#define BM_DIGCTL_HCLKCOUNT_COUNT 0xFFFFFFFF +#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (v) + +#define HW_DIGCTL_RAMCTRL (0x00000030) +#define HW_DIGCTL_RAMCTRL_SET (0x00000034) +#define HW_DIGCTL_RAMCTRL_CLR (0x00000038) +#define HW_DIGCTL_RAMCTRL_TOG (0x0000003c) + +#define BP_DIGCTL_RAMCTRL_RSVD1 12 +#define BM_DIGCTL_RAMCTRL_RSVD1 0xFFFFF000 +#define BF_DIGCTL_RAMCTRL_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_RAMCTRL_RSVD1) +#define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 +#define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0x00000F00 +#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) \ + (((v) << 8) & BM_DIGCTL_RAMCTRL_SPEED_SELECT) +#define BP_DIGCTL_RAMCTRL_RSVD0 1 +#define BM_DIGCTL_RAMCTRL_RSVD0 0x000000FE +#define BF_DIGCTL_RAMCTRL_RSVD0(v) \ + (((v) << 1) & BM_DIGCTL_RAMCTRL_RSVD0) +#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x00000001 + +#define HW_DIGCTL_RAMREPAIR (0x00000040) +#define HW_DIGCTL_RAMREPAIR_SET (0x00000044) +#define HW_DIGCTL_RAMREPAIR_CLR (0x00000048) +#define HW_DIGCTL_RAMREPAIR_TOG (0x0000004c) + +#define BP_DIGCTL_RAMREPAIR_RSVD1 16 +#define BM_DIGCTL_RAMREPAIR_RSVD1 0xFFFF0000 +#define BF_DIGCTL_RAMREPAIR_RSVD1(v) \ + (((v) << 16) & BM_DIGCTL_RAMREPAIR_RSVD1) +#define BP_DIGCTL_RAMREPAIR_ADDR 0 +#define BM_DIGCTL_RAMREPAIR_ADDR 0x0000FFFF +#define BF_DIGCTL_RAMREPAIR_ADDR(v) \ + (((v) << 0) & BM_DIGCTL_RAMREPAIR_ADDR) + +#define HW_DIGCTL_ROMCTRL (0x00000050) +#define HW_DIGCTL_ROMCTRL_SET (0x00000054) +#define HW_DIGCTL_ROMCTRL_CLR (0x00000058) +#define HW_DIGCTL_ROMCTRL_TOG (0x0000005c) + +#define BP_DIGCTL_ROMCTRL_RSVD0 4 +#define BM_DIGCTL_ROMCTRL_RSVD0 0xFFFFFFF0 +#define BF_DIGCTL_ROMCTRL_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_ROMCTRL_RSVD0) +#define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 +#define BM_DIGCTL_ROMCTRL_RD_MARGIN 0x0000000F +#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) \ + (((v) << 0) & BM_DIGCTL_ROMCTRL_RD_MARGIN) + +#define HW_DIGCTL_WRITEONCE (0x00000060) + +#define BP_DIGCTL_WRITEONCE_BITS 0 +#define BM_DIGCTL_WRITEONCE_BITS 0xFFFFFFFF +#define BF_DIGCTL_WRITEONCE_BITS(v) (v) + +#define HW_DIGCTL_ENTROPY (0x00000090) + +#define BP_DIGCTL_ENTROPY_VALUE 0 +#define BM_DIGCTL_ENTROPY_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_VALUE(v) (v) + +#define HW_DIGCTL_ENTROPY_LATCHED (0x000000a0) + +#define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 +#define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (v) + +#define HW_DIGCTL_SJTAGDBG (0x000000b0) +#define HW_DIGCTL_SJTAGDBG_SET (0x000000b4) +#define HW_DIGCTL_SJTAGDBG_CLR (0x000000b8) +#define HW_DIGCTL_SJTAGDBG_TOG (0x000000bc) + +#define BP_DIGCTL_SJTAGDBG_RSVD2 27 +#define BM_DIGCTL_SJTAGDBG_RSVD2 0xF8000000 +#define BF_DIGCTL_SJTAGDBG_RSVD2(v) \ + (((v) << 27) & BM_DIGCTL_SJTAGDBG_RSVD2) +#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 +#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x07FF0000 +#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) \ + (((v) << 16) & BM_DIGCTL_SJTAGDBG_SJTAG_STATE) +#define BP_DIGCTL_SJTAGDBG_RSVD1 11 +#define BM_DIGCTL_SJTAGDBG_RSVD1 0x0000F800 +#define BF_DIGCTL_SJTAGDBG_RSVD1(v) \ + (((v) << 11) & BM_DIGCTL_SJTAGDBG_RSVD1) +#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x00000400 +#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x00000200 +#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x00000100 +#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 +#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0x000000F0 +#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) \ + (((v) << 4) & BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE) +#define BM_DIGCTL_SJTAGDBG_ACTIVE 0x00000008 +#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x00000004 +#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x00000002 +#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x00000001 + +#define HW_DIGCTL_MICROSECONDS (0x000000c0) +#define HW_DIGCTL_MICROSECONDS_SET (0x000000c4) +#define HW_DIGCTL_MICROSECONDS_CLR (0x000000c8) +#define HW_DIGCTL_MICROSECONDS_TOG (0x000000cc) + +#define BP_DIGCTL_MICROSECONDS_VALUE 0 +#define BM_DIGCTL_MICROSECONDS_VALUE 0xFFFFFFFF +#define BF_DIGCTL_MICROSECONDS_VALUE(v) (v) + +#define HW_DIGCTL_DBGRD (0x000000d0) + +#define BP_DIGCTL_DBGRD_COMPLEMENT 0 +#define BM_DIGCTL_DBGRD_COMPLEMENT 0xFFFFFFFF +#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (v) + +#define HW_DIGCTL_DBG (0x000000e0) + +#define BP_DIGCTL_DBG_VALUE 0 +#define BM_DIGCTL_DBG_VALUE 0xFFFFFFFF +#define BF_DIGCTL_DBG_VALUE(v) (v) + +#define HW_DIGCTL_OCRAM_BIST_CSR (0x000000f0) +#define HW_DIGCTL_OCRAM_BIST_CSR_SET (0x000000f4) +#define HW_DIGCTL_OCRAM_BIST_CSR_CLR (0x000000f8) +#define HW_DIGCTL_OCRAM_BIST_CSR_TOG (0x000000fc) + +#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1 11 +#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1 0xFFFFF800 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v) \ + (((v) << 11) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD1) +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE 0x00000400 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x00000200 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x00000100 +#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0 4 +#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD0) +#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x00000008 +#define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x00000004 +#define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x00000002 +#define BM_DIGCTL_OCRAM_BIST_CSR_START 0x00000001 + +#define HW_DIGCTL_OCRAM_STATUS0 (0x00000110) +#define HW_DIGCTL_OCRAM_STATUS0_SET (0x00000114) +#define HW_DIGCTL_OCRAM_STATUS0_CLR (0x00000118) +#define HW_DIGCTL_OCRAM_STATUS0_TOG (0x0000011c) + +#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 +#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS1 (0x00000120) +#define HW_DIGCTL_OCRAM_STATUS1_SET (0x00000124) +#define HW_DIGCTL_OCRAM_STATUS1_CLR (0x00000128) +#define HW_DIGCTL_OCRAM_STATUS1_TOG (0x0000012c) + +#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 +#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS2 (0x00000130) +#define HW_DIGCTL_OCRAM_STATUS2_SET (0x00000134) +#define HW_DIGCTL_OCRAM_STATUS2_CLR (0x00000138) +#define HW_DIGCTL_OCRAM_STATUS2_TOG (0x0000013c) + +#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 +#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS3 (0x00000140) +#define HW_DIGCTL_OCRAM_STATUS3_SET (0x00000144) +#define HW_DIGCTL_OCRAM_STATUS3_CLR (0x00000148) +#define HW_DIGCTL_OCRAM_STATUS3_TOG (0x0000014c) + +#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 +#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS4 (0x00000150) +#define HW_DIGCTL_OCRAM_STATUS4_SET (0x00000154) +#define HW_DIGCTL_OCRAM_STATUS4_CLR (0x00000158) +#define HW_DIGCTL_OCRAM_STATUS4_TOG (0x0000015c) + +#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 +#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS5 (0x00000160) +#define HW_DIGCTL_OCRAM_STATUS5_SET (0x00000164) +#define HW_DIGCTL_OCRAM_STATUS5_CLR (0x00000168) +#define HW_DIGCTL_OCRAM_STATUS5_TOG (0x0000016c) + +#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 +#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS6 (0x00000170) +#define HW_DIGCTL_OCRAM_STATUS6_SET (0x00000174) +#define HW_DIGCTL_OCRAM_STATUS6_CLR (0x00000178) +#define HW_DIGCTL_OCRAM_STATUS6_TOG (0x0000017c) + +#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 +#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS7 (0x00000180) +#define HW_DIGCTL_OCRAM_STATUS7_SET (0x00000184) +#define HW_DIGCTL_OCRAM_STATUS7_CLR (0x00000188) +#define HW_DIGCTL_OCRAM_STATUS7_TOG (0x0000018c) + +#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 +#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS8 (0x00000190) +#define HW_DIGCTL_OCRAM_STATUS8_SET (0x00000194) +#define HW_DIGCTL_OCRAM_STATUS8_CLR (0x00000198) +#define HW_DIGCTL_OCRAM_STATUS8_TOG (0x0000019c) + +#define BP_DIGCTL_OCRAM_STATUS8_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS8_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS8_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR01) +#define BP_DIGCTL_OCRAM_STATUS8_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS8_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS8_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR00) + +#define HW_DIGCTL_OCRAM_STATUS9 (0x000001a0) +#define HW_DIGCTL_OCRAM_STATUS9_SET (0x000001a4) +#define HW_DIGCTL_OCRAM_STATUS9_CLR (0x000001a8) +#define HW_DIGCTL_OCRAM_STATUS9_TOG (0x000001ac) + +#define BP_DIGCTL_OCRAM_STATUS9_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS9_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS9_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR11) +#define BP_DIGCTL_OCRAM_STATUS9_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS9_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS9_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR10) + +#define HW_DIGCTL_OCRAM_STATUS10 (0x000001b0) +#define HW_DIGCTL_OCRAM_STATUS10_SET (0x000001b4) +#define HW_DIGCTL_OCRAM_STATUS10_CLR (0x000001b8) +#define HW_DIGCTL_OCRAM_STATUS10_TOG (0x000001bc) + +#define BP_DIGCTL_OCRAM_STATUS10_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS10_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS10_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR21) +#define BP_DIGCTL_OCRAM_STATUS10_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS10_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS10_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR20) + +#define HW_DIGCTL_OCRAM_STATUS11 (0x000001c0) +#define HW_DIGCTL_OCRAM_STATUS11_SET (0x000001c4) +#define HW_DIGCTL_OCRAM_STATUS11_CLR (0x000001c8) +#define HW_DIGCTL_OCRAM_STATUS11_TOG (0x000001cc) + +#define BP_DIGCTL_OCRAM_STATUS11_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS11_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS11_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR31) +#define BP_DIGCTL_OCRAM_STATUS11_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS11_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS11_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR30) + +#define HW_DIGCTL_OCRAM_STATUS12 (0x000001d0) +#define HW_DIGCTL_OCRAM_STATUS12_SET (0x000001d4) +#define HW_DIGCTL_OCRAM_STATUS12_CLR (0x000001d8) +#define HW_DIGCTL_OCRAM_STATUS12_TOG (0x000001dc) + +#define BP_DIGCTL_OCRAM_STATUS12_RSVD3 28 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD3 0xF0000000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_OCRAM_STATUS12_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x0F000000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD2 20 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD2 0x00F00000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_OCRAM_STATUS12_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x000F0000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD1 12 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD1 0x0000F000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_OCRAM_STATUS12_RSVD1) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x00000F00 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD0 4 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_STATUS12_RSVD0) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x0000000F +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00) + +#define HW_DIGCTL_OCRAM_STATUS13 (0x000001e0) +#define HW_DIGCTL_OCRAM_STATUS13_SET (0x000001e4) +#define HW_DIGCTL_OCRAM_STATUS13_CLR (0x000001e8) +#define HW_DIGCTL_OCRAM_STATUS13_TOG (0x000001ec) + +#define BP_DIGCTL_OCRAM_STATUS13_RSVD3 28 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD3 0xF0000000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_OCRAM_STATUS13_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x0F000000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD2 20 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD2 0x00F00000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_OCRAM_STATUS13_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x000F0000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD1 12 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD1 0x0000F000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_OCRAM_STATUS13_RSVD1) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x00000F00 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD0 4 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_STATUS13_RSVD0) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x0000000F +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20) + +#define HW_DIGCTL_SCRATCH0 (0x00000290) + +#define BP_DIGCTL_SCRATCH0_PTR 0 +#define BM_DIGCTL_SCRATCH0_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH0_PTR(v) (v) + +#define HW_DIGCTL_SCRATCH1 (0x000002a0) + +#define BP_DIGCTL_SCRATCH1_PTR 0 +#define BM_DIGCTL_SCRATCH1_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH1_PTR(v) (v) + +#define HW_DIGCTL_ARMCACHE (0x000002b0) + +#define BP_DIGCTL_ARMCACHE_RSVD4 18 +#define BM_DIGCTL_ARMCACHE_RSVD4 0xFFFC0000 +#define BF_DIGCTL_ARMCACHE_RSVD4(v) \ + (((v) << 18) & BM_DIGCTL_ARMCACHE_RSVD4) +#define BP_DIGCTL_ARMCACHE_VALID_SS 16 +#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 +#define BF_DIGCTL_ARMCACHE_VALID_SS(v) \ + (((v) << 16) & BM_DIGCTL_ARMCACHE_VALID_SS) +#define BP_DIGCTL_ARMCACHE_RSVD3 14 +#define BM_DIGCTL_ARMCACHE_RSVD3 0x0000C000 +#define BF_DIGCTL_ARMCACHE_RSVD3(v) \ + (((v) << 14) & BM_DIGCTL_ARMCACHE_RSVD3) +#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 +#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 +#define BF_DIGCTL_ARMCACHE_DRTY_SS(v) \ + (((v) << 12) & BM_DIGCTL_ARMCACHE_DRTY_SS) +#define BP_DIGCTL_ARMCACHE_RSVD2 10 +#define BM_DIGCTL_ARMCACHE_RSVD2 0x00000C00 +#define BF_DIGCTL_ARMCACHE_RSVD2(v) \ + (((v) << 10) & BM_DIGCTL_ARMCACHE_RSVD2) +#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 +#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 +#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) \ + (((v) << 8) & BM_DIGCTL_ARMCACHE_CACHE_SS) +#define BP_DIGCTL_ARMCACHE_RSVD1 6 +#define BM_DIGCTL_ARMCACHE_RSVD1 0x000000C0 +#define BF_DIGCTL_ARMCACHE_RSVD1(v) \ + (((v) << 6) & BM_DIGCTL_ARMCACHE_RSVD1) +#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 +#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 +#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) \ + (((v) << 4) & BM_DIGCTL_ARMCACHE_DTAG_SS) +#define BP_DIGCTL_ARMCACHE_RSVD0 2 +#define BM_DIGCTL_ARMCACHE_RSVD0 0x0000000C +#define BF_DIGCTL_ARMCACHE_RSVD0(v) \ + (((v) << 2) & BM_DIGCTL_ARMCACHE_RSVD0) +#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 +#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 +#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) \ + (((v) << 0) & BM_DIGCTL_ARMCACHE_ITAG_SS) + +#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW (0x000002c0) + +#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH (0x000002d0) + +#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (v) + +#define HW_DIGCTL_SGTL (0x00000300) + +#define BP_DIGCTL_SGTL_COPYRIGHT 0 +#define BM_DIGCTL_SGTL_COPYRIGHT 0xFFFFFFFF +#define BF_DIGCTL_SGTL_COPYRIGHT(v) (v) + +#define HW_DIGCTL_CHIPID (0x00000310) + +#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 +#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xFFFF0000 +#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) \ + (((v) << 16) & BM_DIGCTL_CHIPID_PRODUCT_CODE) +#define BP_DIGCTL_CHIPID_RSVD0 8 +#define BM_DIGCTL_CHIPID_RSVD0 0x0000FF00 +#define BF_DIGCTL_CHIPID_RSVD0(v) \ + (((v) << 8) & BM_DIGCTL_CHIPID_RSVD0) +#define BP_DIGCTL_CHIPID_REVISION 0 +#define BM_DIGCTL_CHIPID_REVISION 0x000000FF +#define BF_DIGCTL_CHIPID_REVISION(v) \ + (((v) << 0) & BM_DIGCTL_CHIPID_REVISION) + +#define HW_DIGCTL_AHB_STATS_SELECT (0x00000330) + +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3 28 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3 0xF0000000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_AHB_STATS_SELECT_RSVD3) +#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 +#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0x0F000000 +#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) \ + (((v) << 24) & BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2 20 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2 0x00F00000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_AHB_STATS_SELECT_RSVD2) +#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 +#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0x000F0000 +#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) \ + (((v) << 16) & BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1 12 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1 0x0000F000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_AHB_STATS_SELECT_RSVD1) +#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 +#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0x00000F00 +#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) \ + (((v) << 8) & BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0 4 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0 0x000000F0 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_AHB_STATS_SELECT_RSVD0) +#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 +#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0x0000000F +#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) \ + (((v) << 0) & BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 + +#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES (0x00000340) + +#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L0_AHB_DATA_STALLED (0x00000350) + +#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L0_AHB_DATA_CYCLES (0x00000360) + +#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (0x00000370) + +#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_STALLED (0x00000380) + +#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_CYCLES (0x00000390) + +#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (0x000003a0) + +#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_STALLED (0x000003b0) + +#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_CYCLES (0x000003c0) + +#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (0x000003d0) + +#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_STALLED (0x000003e0) + +#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_CYCLES (0x000003f0) + +#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (v) + +/* + * multi-register-define name HW_DIGCTL_MPTEn_LOC + * base 0x00000400 + * count 16 + * offset 0x10 + */ +#define HW_DIGCTL_MPTEn_LOC(n) (0x00000400 + (n) * 0x10) +#define BP_DIGCTL_MPTEn_LOC_RSVD0 12 +#define BM_DIGCTL_MPTEn_LOC_RSVD0 0xFFFFF000 +#define BF_DIGCTL_MPTEn_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTEn_LOC_RSVD0) +#define BP_DIGCTL_MPTEn_LOC_LOC 0 +#define BM_DIGCTL_MPTEn_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTEn_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTEn_LOC_LOC) + +#define HW_DIGCTL_EMICLK_DELAY (0x00000500) + +#define BP_DIGCTL_EMICLK_DELAY_RSVD0 5 +#define BM_DIGCTL_EMICLK_DELAY_RSVD0 0xFFFFFFE0 +#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v) \ + (((v) << 5) & BM_DIGCTL_EMICLK_DELAY_RSVD0) +#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 +#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x0000001F +#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) \ + (((v) << 0) & BM_DIGCTL_EMICLK_DELAY_NUM_TAPS) +#endif /* __ARCH_ARM___DIGCTL_H */ diff --git a/arch/arm/mach-mx23/regs-dram.h b/arch/arm/mach-mx23/regs-dram.h new file mode 100644 index 000000000000..be2fcfa83983 --- /dev/null +++ b/arch/arm/mach-mx23/regs-dram.h @@ -0,0 +1,890 @@ +/* + * Freescale DRAM Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + */ + +#ifndef __ARCH_ARM___DRAM_H +#define __ARCH_ARM___DRAM_H 1 + +#define REGS_DRAM_PHYS (0x800E0000) +#define REGS_DRAM_SIZE 0x00002000 + +#define HW_DRAM_CTL00 (0x00000000) + +#define BP_DRAM_CTL00_RSVD4 25 +#define BM_DRAM_CTL00_RSVD4 0xFE000000 +#define BF_DRAM_CTL00_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL00_RSVD4) +#define BM_DRAM_CTL00_AHB0_W_PRIORITY 0x01000000 +#define BP_DRAM_CTL00_RSVD3 17 +#define BM_DRAM_CTL00_RSVD3 0x00FE0000 +#define BF_DRAM_CTL00_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL00_RSVD3) +#define BM_DRAM_CTL00_AHB0_R_PRIORITY 0x00010000 +#define BP_DRAM_CTL00_RSVD2 9 +#define BM_DRAM_CTL00_RSVD2 0x0000FE00 +#define BF_DRAM_CTL00_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL00_RSVD2) +#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG 0x00000100 +#define BP_DRAM_CTL00_RSVD1 1 +#define BM_DRAM_CTL00_RSVD1 0x000000FE +#define BF_DRAM_CTL00_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL00_RSVD1) +#define BM_DRAM_CTL00_ADDR_CMP_EN 0x00000001 + +#define HW_DRAM_CTL01 (0x00000004) + +#define BP_DRAM_CTL01_RSVD4 25 +#define BM_DRAM_CTL01_RSVD4 0xFE000000 +#define BF_DRAM_CTL01_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL01_RSVD4) +#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG 0x01000000 +#define BP_DRAM_CTL01_RSVD3 17 +#define BM_DRAM_CTL01_RSVD3 0x00FE0000 +#define BF_DRAM_CTL01_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL01_RSVD3) +#define BM_DRAM_CTL01_AHB1_W_PRIORITY 0x00010000 +#define BP_DRAM_CTL01_RSVD2 9 +#define BM_DRAM_CTL01_RSVD2 0x0000FE00 +#define BF_DRAM_CTL01_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL01_RSVD2) +#define BM_DRAM_CTL01_AHB1_R_PRIORITY 0x00000100 +#define BP_DRAM_CTL01_RSVD1 1 +#define BM_DRAM_CTL01_RSVD1 0x000000FE +#define BF_DRAM_CTL01_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL01_RSVD1) +#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0x00000001 + +#define HW_DRAM_CTL02 (0x00000008) + +#define BP_DRAM_CTL02_RSVD4 25 +#define BM_DRAM_CTL02_RSVD4 0xFE000000 +#define BF_DRAM_CTL02_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL02_RSVD4) +#define BM_DRAM_CTL02_AHB3_R_PRIORITY 0x01000000 +#define BP_DRAM_CTL02_RSVD3 17 +#define BM_DRAM_CTL02_RSVD3 0x00FE0000 +#define BF_DRAM_CTL02_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL02_RSVD3) +#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG 0x00010000 +#define BP_DRAM_CTL02_RSVD2 9 +#define BM_DRAM_CTL02_RSVD2 0x0000FE00 +#define BF_DRAM_CTL02_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL02_RSVD2) +#define BM_DRAM_CTL02_AHB2_W_PRIORITY 0x00000100 +#define BP_DRAM_CTL02_RSVD1 1 +#define BM_DRAM_CTL02_RSVD1 0x000000FE +#define BF_DRAM_CTL02_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL02_RSVD1) +#define BM_DRAM_CTL02_AHB2_R_PRIORITY 0x00000001 + +#define HW_DRAM_CTL03 (0x0000000c) + +#define BP_DRAM_CTL03_RSVD4 25 +#define BM_DRAM_CTL03_RSVD4 0xFE000000 +#define BF_DRAM_CTL03_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL03_RSVD4) +#define BM_DRAM_CTL03_AUTO_REFRESH_MODE 0x01000000 +#define BP_DRAM_CTL03_RSVD3 17 +#define BM_DRAM_CTL03_RSVD3 0x00FE0000 +#define BF_DRAM_CTL03_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL03_RSVD3) +#define BM_DRAM_CTL03_AREFRESH 0x00010000 +#define BP_DRAM_CTL03_RSVD2 9 +#define BM_DRAM_CTL03_RSVD2 0x0000FE00 +#define BF_DRAM_CTL03_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL03_RSVD2) +#define BM_DRAM_CTL03_AP 0x00000100 +#define BP_DRAM_CTL03_RSVD1 1 +#define BM_DRAM_CTL03_RSVD1 0x000000FE +#define BF_DRAM_CTL03_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL03_RSVD1) +#define BM_DRAM_CTL03_AHB3_W_PRIORITY 0x00000001 + +#define HW_DRAM_CTL04 (0x00000010) + +#define BP_DRAM_CTL04_RSVD4 25 +#define BM_DRAM_CTL04_RSVD4 0xFE000000 +#define BF_DRAM_CTL04_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL04_RSVD4) +#define BM_DRAM_CTL04_DLL_BYPASS_MODE 0x01000000 +#define BP_DRAM_CTL04_RSVD3 17 +#define BM_DRAM_CTL04_RSVD3 0x00FE0000 +#define BF_DRAM_CTL04_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL04_RSVD3) +#define BM_DRAM_CTL04_DLLLOCKREG 0x00010000 +#define BP_DRAM_CTL04_RSVD2 9 +#define BM_DRAM_CTL04_RSVD2 0x0000FE00 +#define BF_DRAM_CTL04_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL04_RSVD2) +#define BM_DRAM_CTL04_CONCURRENTAP 0x00000100 +#define BP_DRAM_CTL04_RSVD1 1 +#define BM_DRAM_CTL04_RSVD1 0x000000FE +#define BF_DRAM_CTL04_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL04_RSVD1) +#define BM_DRAM_CTL04_BANK_SPLIT_EN 0x00000001 + +#define HW_DRAM_CTL05 (0x00000014) + +#define BP_DRAM_CTL05_RSVD4 25 +#define BM_DRAM_CTL05_RSVD4 0xFE000000 +#define BF_DRAM_CTL05_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL05_RSVD4) +#define BM_DRAM_CTL05_INTRPTREADA 0x01000000 +#define BP_DRAM_CTL05_RSVD3 17 +#define BM_DRAM_CTL05_RSVD3 0x00FE0000 +#define BF_DRAM_CTL05_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL05_RSVD3) +#define BM_DRAM_CTL05_INTRPTAPBURST 0x00010000 +#define BP_DRAM_CTL05_RSVD2 9 +#define BM_DRAM_CTL05_RSVD2 0x0000FE00 +#define BF_DRAM_CTL05_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL05_RSVD2) +#define BM_DRAM_CTL05_FAST_WRITE 0x00000100 +#define BP_DRAM_CTL05_RSVD1 1 +#define BM_DRAM_CTL05_RSVD1 0x000000FE +#define BF_DRAM_CTL05_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL05_RSVD1) +#define BM_DRAM_CTL05_EN_LOWPOWER_MODE 0x00000001 + +#define HW_DRAM_CTL06 (0x00000018) + +#define BP_DRAM_CTL06_RSVD4 25 +#define BM_DRAM_CTL06_RSVD4 0xFE000000 +#define BF_DRAM_CTL06_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL06_RSVD4) +#define BM_DRAM_CTL06_POWER_DOWN 0x01000000 +#define BP_DRAM_CTL06_RSVD3 17 +#define BM_DRAM_CTL06_RSVD3 0x00FE0000 +#define BF_DRAM_CTL06_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL06_RSVD3) +#define BM_DRAM_CTL06_PLACEMENT_EN 0x00010000 +#define BP_DRAM_CTL06_RSVD2 9 +#define BM_DRAM_CTL06_RSVD2 0x0000FE00 +#define BF_DRAM_CTL06_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL06_RSVD2) +#define BM_DRAM_CTL06_NO_CMD_INIT 0x00000100 +#define BP_DRAM_CTL06_RSVD1 1 +#define BM_DRAM_CTL06_RSVD1 0x000000FE +#define BF_DRAM_CTL06_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL06_RSVD1) +#define BM_DRAM_CTL06_INTRPTWRITEA 0x00000001 + +#define HW_DRAM_CTL07 (0x0000001c) + +#define BP_DRAM_CTL07_RSVD4 25 +#define BM_DRAM_CTL07_RSVD4 0xFE000000 +#define BF_DRAM_CTL07_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL07_RSVD4) +#define BM_DRAM_CTL07_RW_SAME_EN 0x01000000 +#define BP_DRAM_CTL07_RSVD3 17 +#define BM_DRAM_CTL07_RSVD3 0x00FE0000 +#define BF_DRAM_CTL07_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL07_RSVD3) +#define BM_DRAM_CTL07_REG_DIMM_ENABLE 0x00010000 +#define BP_DRAM_CTL07_RSVD2 9 +#define BM_DRAM_CTL07_RSVD2 0x0000FE00 +#define BF_DRAM_CTL07_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL07_RSVD2) +#define BM_DRAM_CTL07_RD2RD_TURN 0x00000100 +#define BP_DRAM_CTL07_RSVD1 1 +#define BM_DRAM_CTL07_RSVD1 0x000000FE +#define BF_DRAM_CTL07_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL07_RSVD1) +#define BM_DRAM_CTL07_PRIORITY_EN 0x00000001 + +#define HW_DRAM_CTL08 (0x00000020) + +#define BP_DRAM_CTL08_RSVD4 25 +#define BM_DRAM_CTL08_RSVD4 0xFE000000 +#define BF_DRAM_CTL08_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL08_RSVD4) +#define BM_DRAM_CTL08_TRAS_LOCKOUT 0x01000000 +#define BP_DRAM_CTL08_RSVD3 17 +#define BM_DRAM_CTL08_RSVD3 0x00FE0000 +#define BF_DRAM_CTL08_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL08_RSVD3) +#define BM_DRAM_CTL08_START 0x00010000 +#define BP_DRAM_CTL08_RSVD2 9 +#define BM_DRAM_CTL08_RSVD2 0x0000FE00 +#define BF_DRAM_CTL08_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL08_RSVD2) +#define BM_DRAM_CTL08_SREFRESH 0x00000100 +#define BP_DRAM_CTL08_RSVD1 1 +#define BM_DRAM_CTL08_RSVD1 0x000000FE +#define BF_DRAM_CTL08_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL08_RSVD1) +#define BM_DRAM_CTL08_SDR_MODE 0x00000001 + +#define HW_DRAM_CTL09 (0x00000024) + +#define BP_DRAM_CTL09_RSVD4 26 +#define BM_DRAM_CTL09_RSVD4 0xFC000000 +#define BF_DRAM_CTL09_RSVD4(v) \ + (((v) << 26) & BM_DRAM_CTL09_RSVD4) +#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE 24 +#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE 0x03000000 +#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) \ + (((v) << 24) & BM_DRAM_CTL09_OUT_OF_RANGE_TYPE) +#define BP_DRAM_CTL09_RSVD3 18 +#define BM_DRAM_CTL09_RSVD3 0x00FC0000 +#define BF_DRAM_CTL09_RSVD3(v) \ + (((v) << 18) & BM_DRAM_CTL09_RSVD3) +#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 16 +#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 0x00030000 +#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) \ + (((v) << 16) & BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID) +#define BP_DRAM_CTL09_RSVD2 9 +#define BM_DRAM_CTL09_RSVD2 0x0000FE00 +#define BF_DRAM_CTL09_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL09_RSVD2) +#define BM_DRAM_CTL09_WRITE_MODEREG 0x00000100 +#define BP_DRAM_CTL09_RSVD1 1 +#define BM_DRAM_CTL09_RSVD1 0x000000FE +#define BF_DRAM_CTL09_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL09_RSVD1) +#define BM_DRAM_CTL09_WRITEINTERP 0x00000001 + +#define HW_DRAM_CTL10 (0x00000028) + +#define BP_DRAM_CTL10_RSVD4 27 +#define BM_DRAM_CTL10_RSVD4 0xF8000000 +#define BF_DRAM_CTL10_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL10_RSVD4) +#define BP_DRAM_CTL10_AGE_COUNT 24 +#define BM_DRAM_CTL10_AGE_COUNT 0x07000000 +#define BF_DRAM_CTL10_AGE_COUNT(v) \ + (((v) << 24) & BM_DRAM_CTL10_AGE_COUNT) +#define BP_DRAM_CTL10_RSVD3 19 +#define BM_DRAM_CTL10_RSVD3 0x00F80000 +#define BF_DRAM_CTL10_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL10_RSVD3) +#define BP_DRAM_CTL10_ADDR_PINS 16 +#define BM_DRAM_CTL10_ADDR_PINS 0x00070000 +#define BF_DRAM_CTL10_ADDR_PINS(v) \ + (((v) << 16) & BM_DRAM_CTL10_ADDR_PINS) +#define BP_DRAM_CTL10_RSVD2 10 +#define BM_DRAM_CTL10_RSVD2 0x0000FC00 +#define BF_DRAM_CTL10_RSVD2(v) \ + (((v) << 10) & BM_DRAM_CTL10_RSVD2) +#define BP_DRAM_CTL10_TEMRS 8 +#define BM_DRAM_CTL10_TEMRS 0x00000300 +#define BF_DRAM_CTL10_TEMRS(v) \ + (((v) << 8) & BM_DRAM_CTL10_TEMRS) +#define BP_DRAM_CTL10_RSVD1 2 +#define BM_DRAM_CTL10_RSVD1 0x000000FC +#define BF_DRAM_CTL10_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL10_RSVD1) +#define BP_DRAM_CTL10_Q_FULLNESS 0 +#define BM_DRAM_CTL10_Q_FULLNESS 0x00000003 +#define BF_DRAM_CTL10_Q_FULLNESS(v) \ + (((v) << 0) & BM_DRAM_CTL10_Q_FULLNESS) + +#define HW_DRAM_CTL11 (0x0000002c) + +#define BP_DRAM_CTL11_RSVD4 27 +#define BM_DRAM_CTL11_RSVD4 0xF8000000 +#define BF_DRAM_CTL11_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL11_RSVD4) +#define BP_DRAM_CTL11_MAX_CS_REG 24 +#define BM_DRAM_CTL11_MAX_CS_REG 0x07000000 +#define BF_DRAM_CTL11_MAX_CS_REG(v) \ + (((v) << 24) & BM_DRAM_CTL11_MAX_CS_REG) +#define BP_DRAM_CTL11_RSVD3 19 +#define BM_DRAM_CTL11_RSVD3 0x00F80000 +#define BF_DRAM_CTL11_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL11_RSVD3) +#define BP_DRAM_CTL11_COMMAND_AGE_COUNT 16 +#define BM_DRAM_CTL11_COMMAND_AGE_COUNT 0x00070000 +#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v) \ + (((v) << 16) & BM_DRAM_CTL11_COMMAND_AGE_COUNT) +#define BP_DRAM_CTL11_RSVD2 11 +#define BM_DRAM_CTL11_RSVD2 0x0000F800 +#define BF_DRAM_CTL11_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL11_RSVD2) +#define BP_DRAM_CTL11_COLUMN_SIZE 8 +#define BM_DRAM_CTL11_COLUMN_SIZE 0x00000700 +#define BF_DRAM_CTL11_COLUMN_SIZE(v) \ + (((v) << 8) & BM_DRAM_CTL11_COLUMN_SIZE) +#define BP_DRAM_CTL11_RSVD1 3 +#define BM_DRAM_CTL11_RSVD1 0x000000F8 +#define BF_DRAM_CTL11_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL11_RSVD1) +#define BP_DRAM_CTL11_CASLAT 0 +#define BM_DRAM_CTL11_CASLAT 0x00000007 +#define BF_DRAM_CTL11_CASLAT(v) \ + (((v) << 0) & BM_DRAM_CTL11_CASLAT) + +#define HW_DRAM_CTL12 (0x00000030) + +#define BP_DRAM_CTL12_RSVD3 27 +#define BM_DRAM_CTL12_RSVD3 0xF8000000 +#define BF_DRAM_CTL12_RSVD3(v) \ + (((v) << 27) & BM_DRAM_CTL12_RSVD3) +#define BP_DRAM_CTL12_TWR_INT 24 +#define BM_DRAM_CTL12_TWR_INT 0x07000000 +#define BF_DRAM_CTL12_TWR_INT(v) \ + (((v) << 24) & BM_DRAM_CTL12_TWR_INT) +#define BP_DRAM_CTL12_RSVD2 19 +#define BM_DRAM_CTL12_RSVD2 0x00F80000 +#define BF_DRAM_CTL12_RSVD2(v) \ + (((v) << 19) & BM_DRAM_CTL12_RSVD2) +#define BP_DRAM_CTL12_TRRD 16 +#define BM_DRAM_CTL12_TRRD 0x00070000 +#define BF_DRAM_CTL12_TRRD(v) \ + (((v) << 16) & BM_DRAM_CTL12_TRRD) +#define BP_DRAM_CTL12_OBSOLETE 8 +#define BM_DRAM_CTL12_OBSOLETE 0x0000FF00 +#define BF_DRAM_CTL12_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL12_OBSOLETE) +#define BP_DRAM_CTL12_RSVD1 3 +#define BM_DRAM_CTL12_RSVD1 0x000000F8 +#define BF_DRAM_CTL12_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL12_RSVD1) +#define BP_DRAM_CTL12_TCKE 0 +#define BM_DRAM_CTL12_TCKE 0x00000007 +#define BF_DRAM_CTL12_TCKE(v) \ + (((v) << 0) & BM_DRAM_CTL12_TCKE) + +#define HW_DRAM_CTL13 (0x00000034) + +#define BP_DRAM_CTL13_RSVD4 28 +#define BM_DRAM_CTL13_RSVD4 0xF0000000 +#define BF_DRAM_CTL13_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL13_RSVD4) +#define BP_DRAM_CTL13_CASLAT_LIN_GATE 24 +#define BM_DRAM_CTL13_CASLAT_LIN_GATE 0x0F000000 +#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v) \ + (((v) << 24) & BM_DRAM_CTL13_CASLAT_LIN_GATE) +#define BP_DRAM_CTL13_RSVD3 20 +#define BM_DRAM_CTL13_RSVD3 0x00F00000 +#define BF_DRAM_CTL13_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL13_RSVD3) +#define BP_DRAM_CTL13_CASLAT_LIN 16 +#define BM_DRAM_CTL13_CASLAT_LIN 0x000F0000 +#define BF_DRAM_CTL13_CASLAT_LIN(v) \ + (((v) << 16) & BM_DRAM_CTL13_CASLAT_LIN) +#define BP_DRAM_CTL13_RSVD2 12 +#define BM_DRAM_CTL13_RSVD2 0x0000F000 +#define BF_DRAM_CTL13_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL13_RSVD2) +#define BP_DRAM_CTL13_APREBIT 8 +#define BM_DRAM_CTL13_APREBIT 0x00000F00 +#define BF_DRAM_CTL13_APREBIT(v) \ + (((v) << 8) & BM_DRAM_CTL13_APREBIT) +#define BP_DRAM_CTL13_RSVD1 3 +#define BM_DRAM_CTL13_RSVD1 0x000000F8 +#define BF_DRAM_CTL13_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL13_RSVD1) +#define BP_DRAM_CTL13_TWTR 0 +#define BM_DRAM_CTL13_TWTR 0x00000007 +#define BF_DRAM_CTL13_TWTR(v) \ + (((v) << 0) & BM_DRAM_CTL13_TWTR) + +#define HW_DRAM_CTL14 (0x00000038) + +#define BP_DRAM_CTL14_RSVD4 28 +#define BM_DRAM_CTL14_RSVD4 0xF0000000 +#define BF_DRAM_CTL14_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL14_RSVD4) +#define BP_DRAM_CTL14_MAX_COL_REG 24 +#define BM_DRAM_CTL14_MAX_COL_REG 0x0F000000 +#define BF_DRAM_CTL14_MAX_COL_REG(v) \ + (((v) << 24) & BM_DRAM_CTL14_MAX_COL_REG) +#define BP_DRAM_CTL14_RSVD3 20 +#define BM_DRAM_CTL14_RSVD3 0x00F00000 +#define BF_DRAM_CTL14_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL14_RSVD3) +#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 16 +#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 0x000F0000 +#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) \ + (((v) << 16) & BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE) +#define BP_DRAM_CTL14_RSVD2 12 +#define BM_DRAM_CTL14_RSVD2 0x0000F000 +#define BF_DRAM_CTL14_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL14_RSVD2) +#define BP_DRAM_CTL14_INITAREF 8 +#define BM_DRAM_CTL14_INITAREF 0x00000F00 +#define BF_DRAM_CTL14_INITAREF(v) \ + (((v) << 8) & BM_DRAM_CTL14_INITAREF) +#define BP_DRAM_CTL14_RSVD1 4 +#define BM_DRAM_CTL14_RSVD1 0x000000F0 +#define BF_DRAM_CTL14_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL14_RSVD1) +#define BP_DRAM_CTL14_CS_MAP 0 +#define BM_DRAM_CTL14_CS_MAP 0x0000000F +#define BF_DRAM_CTL14_CS_MAP(v) \ + (((v) << 0) & BM_DRAM_CTL14_CS_MAP) + +#define HW_DRAM_CTL15 (0x0000003c) + +#define BP_DRAM_CTL15_RSVD4 28 +#define BM_DRAM_CTL15_RSVD4 0xF0000000 +#define BF_DRAM_CTL15_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL15_RSVD4) +#define BP_DRAM_CTL15_TRP 24 +#define BM_DRAM_CTL15_TRP 0x0F000000 +#define BF_DRAM_CTL15_TRP(v) \ + (((v) << 24) & BM_DRAM_CTL15_TRP) +#define BP_DRAM_CTL15_RSVD3 20 +#define BM_DRAM_CTL15_RSVD3 0x00F00000 +#define BF_DRAM_CTL15_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL15_RSVD3) +#define BP_DRAM_CTL15_TDAL 16 +#define BM_DRAM_CTL15_TDAL 0x000F0000 +#define BF_DRAM_CTL15_TDAL(v) \ + (((v) << 16) & BM_DRAM_CTL15_TDAL) +#define BP_DRAM_CTL15_RSVD2 12 +#define BM_DRAM_CTL15_RSVD2 0x0000F000 +#define BF_DRAM_CTL15_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL15_RSVD2) +#define BP_DRAM_CTL15_PORT_BUSY 8 +#define BM_DRAM_CTL15_PORT_BUSY 0x00000F00 +#define BF_DRAM_CTL15_PORT_BUSY(v) \ + (((v) << 8) & BM_DRAM_CTL15_PORT_BUSY) +#define BP_DRAM_CTL15_RSVD1 4 +#define BM_DRAM_CTL15_RSVD1 0x000000F0 +#define BF_DRAM_CTL15_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL15_RSVD1) +#define BP_DRAM_CTL15_MAX_ROW_REG 0 +#define BM_DRAM_CTL15_MAX_ROW_REG 0x0000000F +#define BF_DRAM_CTL15_MAX_ROW_REG(v) \ + (((v) << 0) & BM_DRAM_CTL15_MAX_ROW_REG) + +#define HW_DRAM_CTL16 (0x00000040) + +#define BP_DRAM_CTL16_RSVD4 29 +#define BM_DRAM_CTL16_RSVD4 0xE0000000 +#define BF_DRAM_CTL16_RSVD4(v) \ + (((v) << 29) & BM_DRAM_CTL16_RSVD4) +#define BP_DRAM_CTL16_TMRD 24 +#define BM_DRAM_CTL16_TMRD 0x1F000000 +#define BF_DRAM_CTL16_TMRD(v) \ + (((v) << 24) & BM_DRAM_CTL16_TMRD) +#define BP_DRAM_CTL16_RSVD3 21 +#define BM_DRAM_CTL16_RSVD3 0x00E00000 +#define BF_DRAM_CTL16_RSVD3(v) \ + (((v) << 21) & BM_DRAM_CTL16_RSVD3) +#define BP_DRAM_CTL16_LOWPOWER_CONTROL 16 +#define BM_DRAM_CTL16_LOWPOWER_CONTROL 0x001F0000 +#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v) \ + (((v) << 16) & BM_DRAM_CTL16_LOWPOWER_CONTROL) +#define BP_DRAM_CTL16_RSVD2 13 +#define BM_DRAM_CTL16_RSVD2 0x0000E000 +#define BF_DRAM_CTL16_RSVD2(v) \ + (((v) << 13) & BM_DRAM_CTL16_RSVD2) +#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 8 +#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 0x00001F00 +#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) \ + (((v) << 8) & BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE) +#define BP_DRAM_CTL16_RSVD1 4 +#define BM_DRAM_CTL16_RSVD1 0x000000F0 +#define BF_DRAM_CTL16_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL16_RSVD1) +#define BP_DRAM_CTL16_INT_ACK 0 +#define BM_DRAM_CTL16_INT_ACK 0x0000000F +#define BF_DRAM_CTL16_INT_ACK(v) \ + (((v) << 0) & BM_DRAM_CTL16_INT_ACK) + +#define HW_DRAM_CTL17 (0x00000044) + +#define BP_DRAM_CTL17_DLL_START_POINT 24 +#define BM_DRAM_CTL17_DLL_START_POINT 0xFF000000 +#define BF_DRAM_CTL17_DLL_START_POINT(v) \ + (((v) << 24) & BM_DRAM_CTL17_DLL_START_POINT) +#define BP_DRAM_CTL17_DLL_LOCK 16 +#define BM_DRAM_CTL17_DLL_LOCK 0x00FF0000 +#define BF_DRAM_CTL17_DLL_LOCK(v) \ + (((v) << 16) & BM_DRAM_CTL17_DLL_LOCK) +#define BP_DRAM_CTL17_DLL_INCREMENT 8 +#define BM_DRAM_CTL17_DLL_INCREMENT 0x0000FF00 +#define BF_DRAM_CTL17_DLL_INCREMENT(v) \ + (((v) << 8) & BM_DRAM_CTL17_DLL_INCREMENT) +#define BP_DRAM_CTL17_RSVD1 5 +#define BM_DRAM_CTL17_RSVD1 0x000000E0 +#define BF_DRAM_CTL17_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL17_RSVD1) +#define BP_DRAM_CTL17_TRC 0 +#define BM_DRAM_CTL17_TRC 0x0000001F +#define BF_DRAM_CTL17_TRC(v) \ + (((v) << 0) & BM_DRAM_CTL17_TRC) + +#define HW_DRAM_CTL18 (0x00000048) + +#define BM_DRAM_CTL18_RSVD4 0x80000000 +#define BP_DRAM_CTL18_DLL_DQS_DELAY_1 24 +#define BM_DRAM_CTL18_DLL_DQS_DELAY_1 0x7F000000 +#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v) \ + (((v) << 24) & BM_DRAM_CTL18_DLL_DQS_DELAY_1) +#define BM_DRAM_CTL18_RSVD3 0x00800000 +#define BP_DRAM_CTL18_DLL_DQS_DELAY_0 16 +#define BM_DRAM_CTL18_DLL_DQS_DELAY_0 0x007F0000 +#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v) \ + (((v) << 16) & BM_DRAM_CTL18_DLL_DQS_DELAY_0) +#define BP_DRAM_CTL18_RSVD2 13 +#define BM_DRAM_CTL18_RSVD2 0x0000E000 +#define BF_DRAM_CTL18_RSVD2(v) \ + (((v) << 13) & BM_DRAM_CTL18_RSVD2) +#define BP_DRAM_CTL18_INT_STATUS 8 +#define BM_DRAM_CTL18_INT_STATUS 0x00001F00 +#define BF_DRAM_CTL18_INT_STATUS(v) \ + (((v) << 8) & BM_DRAM_CTL18_INT_STATUS) +#define BP_DRAM_CTL18_RSVD1 5 +#define BM_DRAM_CTL18_RSVD1 0x000000E0 +#define BF_DRAM_CTL18_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL18_RSVD1) +#define BP_DRAM_CTL18_INT_MASK 0 +#define BM_DRAM_CTL18_INT_MASK 0x0000001F +#define BF_DRAM_CTL18_INT_MASK(v) \ + (((v) << 0) & BM_DRAM_CTL18_INT_MASK) + +#define HW_DRAM_CTL19 (0x0000004c) + +#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 24 +#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 0xFF000000 +#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) \ + (((v) << 24) & BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS) +#define BM_DRAM_CTL19_RSVD1 0x00800000 +#define BP_DRAM_CTL19_DQS_OUT_SHIFT 16 +#define BM_DRAM_CTL19_DQS_OUT_SHIFT 0x007F0000 +#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v) \ + (((v) << 16) & BM_DRAM_CTL19_DQS_OUT_SHIFT) +#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 8 +#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 0x0000FF00 +#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) \ + (((v) << 8) & BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1) +#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0 +#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0x000000FF +#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) \ + (((v) << 0) & BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0) + +#define HW_DRAM_CTL20 (0x00000050) + +#define BP_DRAM_CTL20_TRCD_INT 24 +#define BM_DRAM_CTL20_TRCD_INT 0xFF000000 +#define BF_DRAM_CTL20_TRCD_INT(v) \ + (((v) << 24) & BM_DRAM_CTL20_TRCD_INT) +#define BP_DRAM_CTL20_TRAS_MIN 16 +#define BM_DRAM_CTL20_TRAS_MIN 0x00FF0000 +#define BF_DRAM_CTL20_TRAS_MIN(v) \ + (((v) << 16) & BM_DRAM_CTL20_TRAS_MIN) +#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 8 +#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 0x0000FF00 +#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) \ + (((v) << 8) & BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS) +#define BM_DRAM_CTL20_RSVD1 0x00000080 +#define BP_DRAM_CTL20_WR_DQS_SHIFT 0 +#define BM_DRAM_CTL20_WR_DQS_SHIFT 0x0000007F +#define BF_DRAM_CTL20_WR_DQS_SHIFT(v) \ + (((v) << 0) & BM_DRAM_CTL20_WR_DQS_SHIFT) + +#define HW_DRAM_CTL21 (0x00000054) + +#define BP_DRAM_CTL21_OBSOLETE 24 +#define BM_DRAM_CTL21_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL21_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL21_OBSOLETE) +#define BP_DRAM_CTL21_RSVD1 18 +#define BM_DRAM_CTL21_RSVD1 0x00FC0000 +#define BF_DRAM_CTL21_RSVD1(v) \ + (((v) << 18) & BM_DRAM_CTL21_RSVD1) +#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH 8 +#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH 0x0003FF00 +#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) \ + (((v) << 8) & BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH) +#define BP_DRAM_CTL21_TRFC 0 +#define BM_DRAM_CTL21_TRFC 0x000000FF +#define BF_DRAM_CTL21_TRFC(v) \ + (((v) << 0) & BM_DRAM_CTL21_TRFC) + +#define HW_DRAM_CTL22 (0x00000058) + +#define BP_DRAM_CTL22_RSVD2 27 +#define BM_DRAM_CTL22_RSVD2 0xF8000000 +#define BF_DRAM_CTL22_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL22_RSVD2) +#define BP_DRAM_CTL22_AHB0_WRCNT 16 +#define BM_DRAM_CTL22_AHB0_WRCNT 0x07FF0000 +#define BF_DRAM_CTL22_AHB0_WRCNT(v) \ + (((v) << 16) & BM_DRAM_CTL22_AHB0_WRCNT) +#define BP_DRAM_CTL22_RSVD1 11 +#define BM_DRAM_CTL22_RSVD1 0x0000F800 +#define BF_DRAM_CTL22_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL22_RSVD1) +#define BP_DRAM_CTL22_AHB0_RDCNT 0 +#define BM_DRAM_CTL22_AHB0_RDCNT 0x000007FF +#define BF_DRAM_CTL22_AHB0_RDCNT(v) \ + (((v) << 0) & BM_DRAM_CTL22_AHB0_RDCNT) + +#define HW_DRAM_CTL23 (0x0000005c) + +#define BP_DRAM_CTL23_RSVD2 27 +#define BM_DRAM_CTL23_RSVD2 0xF8000000 +#define BF_DRAM_CTL23_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL23_RSVD2) +#define BP_DRAM_CTL23_AHB1_WRCNT 16 +#define BM_DRAM_CTL23_AHB1_WRCNT 0x07FF0000 +#define BF_DRAM_CTL23_AHB1_WRCNT(v) \ + (((v) << 16) & BM_DRAM_CTL23_AHB1_WRCNT) +#define BP_DRAM_CTL23_RSVD1 11 +#define BM_DRAM_CTL23_RSVD1 0x0000F800 +#define BF_DRAM_CTL23_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL23_RSVD1) +#define BP_DRAM_CTL23_AHB1_RDCNT 0 +#define BM_DRAM_CTL23_AHB1_RDCNT 0x000007FF +#define BF_DRAM_CTL23_AHB1_RDCNT(v) \ + (((v) << 0) & BM_DRAM_CTL23_AHB1_RDCNT) + +#define HW_DRAM_CTL24 (0x00000060) + +#define BP_DRAM_CTL24_RSVD2 27 +#define BM_DRAM_CTL24_RSVD2 0xF8000000 +#define BF_DRAM_CTL24_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL24_RSVD2) +#define BP_DRAM_CTL24_AHB2_WRCNT 16 +#define BM_DRAM_CTL24_AHB2_WRCNT 0x07FF0000 +#define BF_DRAM_CTL24_AHB2_WRCNT(v) \ + (((v) << 16) & BM_DRAM_CTL24_AHB2_WRCNT) +#define BP_DRAM_CTL24_RSVD1 11 +#define BM_DRAM_CTL24_RSVD1 0x0000F800 +#define BF_DRAM_CTL24_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL24_RSVD1) +#define BP_DRAM_CTL24_AHB2_RDCNT 0 +#define BM_DRAM_CTL24_AHB2_RDCNT 0x000007FF +#define BF_DRAM_CTL24_AHB2_RDCNT(v) \ + (((v) << 0) & BM_DRAM_CTL24_AHB2_RDCNT) + +#define HW_DRAM_CTL25 (0x00000064) + +#define BP_DRAM_CTL25_RSVD2 27 +#define BM_DRAM_CTL25_RSVD2 0xF8000000 +#define BF_DRAM_CTL25_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL25_RSVD2) +#define BP_DRAM_CTL25_AHB3_WRCNT 16 +#define BM_DRAM_CTL25_AHB3_WRCNT 0x07FF0000 +#define BF_DRAM_CTL25_AHB3_WRCNT(v) \ + (((v) << 16) & BM_DRAM_CTL25_AHB3_WRCNT) +#define BP_DRAM_CTL25_RSVD1 11 +#define BM_DRAM_CTL25_RSVD1 0x0000F800 +#define BF_DRAM_CTL25_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL25_RSVD1) +#define BP_DRAM_CTL25_AHB3_RDCNT 0 +#define BM_DRAM_CTL25_AHB3_RDCNT 0x000007FF +#define BF_DRAM_CTL25_AHB3_RDCNT(v) \ + (((v) << 0) & BM_DRAM_CTL25_AHB3_RDCNT) + +#define HW_DRAM_CTL26 (0x00000068) + +#define BP_DRAM_CTL26_OBSOLETE 16 +#define BM_DRAM_CTL26_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL26_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL26_OBSOLETE) +#define BP_DRAM_CTL26_RSVD1 12 +#define BM_DRAM_CTL26_RSVD1 0x0000F000 +#define BF_DRAM_CTL26_RSVD1(v) \ + (((v) << 12) & BM_DRAM_CTL26_RSVD1) +#define BP_DRAM_CTL26_TREF 0 +#define BM_DRAM_CTL26_TREF 0x00000FFF +#define BF_DRAM_CTL26_TREF(v) \ + (((v) << 0) & BM_DRAM_CTL26_TREF) + +#define HW_DRAM_CTL27 (0x0000006c) + +#define BP_DRAM_CTL27_OBSOLETE 0 +#define BM_DRAM_CTL27_OBSOLETE 0xFFFFFFFF +#define BF_DRAM_CTL27_OBSOLETE(v) (v) + +#define HW_DRAM_CTL28 (0x00000070) + +#define BP_DRAM_CTL28_OBSOLETE 0 +#define BM_DRAM_CTL28_OBSOLETE 0xFFFFFFFF +#define BF_DRAM_CTL28_OBSOLETE(v) (v) + +#define HW_DRAM_CTL29 (0x00000074) + +#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 16 +#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 0xFFFF0000 +#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT) +#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0 +#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0x0000FFFF +#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT) + +#define HW_DRAM_CTL30 (0x00000078) + +#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 16 +#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 0xFFFF0000 +#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v) \ + (((v) << 16) & BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD) +#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0 +#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0x0000FFFF +#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT) + +#define HW_DRAM_CTL31 (0x0000007c) + +#define BP_DRAM_CTL31_TDLL 16 +#define BM_DRAM_CTL31_TDLL 0xFFFF0000 +#define BF_DRAM_CTL31_TDLL(v) \ + (((v) << 16) & BM_DRAM_CTL31_TDLL) +#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0 +#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0x0000FFFF +#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT) + +#define HW_DRAM_CTL32 (0x00000080) + +#define BP_DRAM_CTL32_TXSNR 16 +#define BM_DRAM_CTL32_TXSNR 0xFFFF0000 +#define BF_DRAM_CTL32_TXSNR(v) \ + (((v) << 16) & BM_DRAM_CTL32_TXSNR) +#define BP_DRAM_CTL32_TRAS_MAX 0 +#define BM_DRAM_CTL32_TRAS_MAX 0x0000FFFF +#define BF_DRAM_CTL32_TRAS_MAX(v) \ + (((v) << 0) & BM_DRAM_CTL32_TRAS_MAX) + +#define HW_DRAM_CTL33 (0x00000084) + +#define BP_DRAM_CTL33_VERSION 16 +#define BM_DRAM_CTL33_VERSION 0xFFFF0000 +#define BF_DRAM_CTL33_VERSION(v) \ + (((v) << 16) & BM_DRAM_CTL33_VERSION) +#define BP_DRAM_CTL33_TXSR 0 +#define BM_DRAM_CTL33_TXSR 0x0000FFFF +#define BF_DRAM_CTL33_TXSR(v) \ + (((v) << 0) & BM_DRAM_CTL33_TXSR) + +#define HW_DRAM_CTL34 (0x00000088) + +#define BP_DRAM_CTL34_RSVD1 24 +#define BM_DRAM_CTL34_RSVD1 0xFF000000 +#define BF_DRAM_CTL34_RSVD1(v) \ + (((v) << 24) & BM_DRAM_CTL34_RSVD1) +#define BP_DRAM_CTL34_TINIT 0 +#define BM_DRAM_CTL34_TINIT 0x00FFFFFF +#define BF_DRAM_CTL34_TINIT(v) \ + (((v) << 0) & BM_DRAM_CTL34_TINIT) + +#define HW_DRAM_CTL35 (0x0000008c) + +#define BM_DRAM_CTL35_RSVD1 0x80000000 +#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR 0 +#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR 0x7FFFFFFF +#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v) \ + (((v) << 0) & BM_DRAM_CTL35_OUT_OF_RANGE_ADDR) + +#define HW_DRAM_CTL36 (0x00000090) + +#define BP_DRAM_CTL36_RSVD4 25 +#define BM_DRAM_CTL36_RSVD4 0xFE000000 +#define BF_DRAM_CTL36_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL36_RSVD4) +#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT 0x01000000 +#define BP_DRAM_CTL36_RSVD3 17 +#define BM_DRAM_CTL36_RSVD3 0x00FE0000 +#define BF_DRAM_CTL36_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL36_RSVD3) +#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH 0x00010000 +#define BP_DRAM_CTL36_RSVD2 9 +#define BM_DRAM_CTL36_RSVD2 0x0000FE00 +#define BF_DRAM_CTL36_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL36_RSVD2) +#define BM_DRAM_CTL36_BUS_SHARE_ENABLE 0x00000100 +#define BP_DRAM_CTL36_RSVD1 1 +#define BM_DRAM_CTL36_RSVD1 0x000000FE +#define BF_DRAM_CTL36_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL36_RSVD1) +#define BM_DRAM_CTL36_ACTIVE_AGING 0x00000001 + +#define HW_DRAM_CTL37 (0x00000094) + +#define BP_DRAM_CTL37_OBSOLETE 24 +#define BM_DRAM_CTL37_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL37_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL37_OBSOLETE) +#define BP_DRAM_CTL37_RSVD2 18 +#define BM_DRAM_CTL37_RSVD2 0x00FC0000 +#define BF_DRAM_CTL37_RSVD2(v) \ + (((v) << 18) & BM_DRAM_CTL37_RSVD2) +#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT 8 +#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT 0x0003FF00 +#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v) \ + (((v) << 8) & BM_DRAM_CTL37_BUS_SHARE_TIMEOUT) +#define BP_DRAM_CTL37_RSVD1 1 +#define BM_DRAM_CTL37_RSVD1 0x000000FE +#define BF_DRAM_CTL37_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL37_RSVD1) +#define BM_DRAM_CTL37_TREF_ENABLE 0x00000001 + +#define HW_DRAM_CTL38 (0x00000098) + +#define BP_DRAM_CTL38_RSVD2 29 +#define BM_DRAM_CTL38_RSVD2 0xE0000000 +#define BF_DRAM_CTL38_RSVD2(v) \ + (((v) << 29) & BM_DRAM_CTL38_RSVD2) +#define BP_DRAM_CTL38_EMRS2_DATA_0 16 +#define BM_DRAM_CTL38_EMRS2_DATA_0 0x1FFF0000 +#define BF_DRAM_CTL38_EMRS2_DATA_0(v) \ + (((v) << 16) & BM_DRAM_CTL38_EMRS2_DATA_0) +#define BP_DRAM_CTL38_RSVD1 13 +#define BM_DRAM_CTL38_RSVD1 0x0000E000 +#define BF_DRAM_CTL38_RSVD1(v) \ + (((v) << 13) & BM_DRAM_CTL38_RSVD1) +#define BP_DRAM_CTL38_EMRS1_DATA 0 +#define BM_DRAM_CTL38_EMRS1_DATA 0x00001FFF +#define BF_DRAM_CTL38_EMRS1_DATA(v) \ + (((v) << 0) & BM_DRAM_CTL38_EMRS1_DATA) + +#define HW_DRAM_CTL39 (0x0000009c) + +#define BP_DRAM_CTL39_RSVD2 29 +#define BM_DRAM_CTL39_RSVD2 0xE0000000 +#define BF_DRAM_CTL39_RSVD2(v) \ + (((v) << 29) & BM_DRAM_CTL39_RSVD2) +#define BP_DRAM_CTL39_EMRS2_DATA_2 16 +#define BM_DRAM_CTL39_EMRS2_DATA_2 0x1FFF0000 +#define BF_DRAM_CTL39_EMRS2_DATA_2(v) \ + (((v) << 16) & BM_DRAM_CTL39_EMRS2_DATA_2) +#define BP_DRAM_CTL39_RSVD1 13 +#define BM_DRAM_CTL39_RSVD1 0x0000E000 +#define BF_DRAM_CTL39_RSVD1(v) \ + (((v) << 13) & BM_DRAM_CTL39_RSVD1) +#define BP_DRAM_CTL39_EMRS2_DATA_1 0 +#define BM_DRAM_CTL39_EMRS2_DATA_1 0x00001FFF +#define BF_DRAM_CTL39_EMRS2_DATA_1(v) \ + (((v) << 0) & BM_DRAM_CTL39_EMRS2_DATA_1) + +#define HW_DRAM_CTL40 (0x000000a0) + +#define BP_DRAM_CTL40_TPDEX 16 +#define BM_DRAM_CTL40_TPDEX 0xFFFF0000 +#define BF_DRAM_CTL40_TPDEX(v) \ + (((v) << 16) & BM_DRAM_CTL40_TPDEX) +#define BP_DRAM_CTL40_RSVD1 13 +#define BM_DRAM_CTL40_RSVD1 0x0000E000 +#define BF_DRAM_CTL40_RSVD1(v) \ + (((v) << 13) & BM_DRAM_CTL40_RSVD1) +#define BP_DRAM_CTL40_EMRS2_DATA_3 0 +#define BM_DRAM_CTL40_EMRS2_DATA_3 0x00001FFF +#define BF_DRAM_CTL40_EMRS2_DATA_3(v) \ + (((v) << 0) & BM_DRAM_CTL40_EMRS2_DATA_3) +#endif /* __ARCH_ARM___DRAM_H */ diff --git a/arch/arm/mach-mx23/regs-pinctrl.h b/arch/arm/mach-mx23/regs-pinctrl.h new file mode 100644 index 000000000000..d38f7bdca051 --- /dev/null +++ b/arch/arm/mach-mx23/regs-pinctrl.h @@ -0,0 +1,1879 @@ +/* + * Freescale PINCTRL Register Definitions + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.19 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H + + +#define HW_PINCTRL_CTRL (0x00000000) +#define HW_PINCTRL_CTRL_SET (0x00000004) +#define HW_PINCTRL_CTRL_CLR (0x00000008) +#define HW_PINCTRL_CTRL_TOG (0x0000000c) + +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BP_PINCTRL_CTRL_RSRVD2 28 +#define BM_PINCTRL_CTRL_RSRVD2 0x30000000 +#define BF_PINCTRL_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_PINCTRL_CTRL_RSRVD2) +#define BM_PINCTRL_CTRL_PRESENT3 0x08000000 +#define BM_PINCTRL_CTRL_PRESENT2 0x04000000 +#define BM_PINCTRL_CTRL_PRESENT1 0x02000000 +#define BM_PINCTRL_CTRL_PRESENT0 0x01000000 +#define BP_PINCTRL_CTRL_RSRVD1 3 +#define BM_PINCTRL_CTRL_RSRVD1 0x00FFFFF8 +#define BF_PINCTRL_CTRL_RSRVD1(v) \ + (((v) << 3) & BM_PINCTRL_CTRL_RSRVD1) +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 + +#define HW_PINCTRL_MUXSEL0 (0x00000100) +#define HW_PINCTRL_MUXSEL0_SET (0x00000104) +#define HW_PINCTRL_MUXSEL0_CLR (0x00000108) +#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c) + +#define BP_PINCTRL_MUXSEL0_BANK0_PIN15 30 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL0_BANK0_PIN15) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN14 28 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL0_BANK0_PIN14) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN13 26 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL0_BANK0_PIN13) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN12 24 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL0_BANK0_PIN12) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN11 22 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL0_BANK0_PIN11) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN10 20 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL0_BANK0_PIN10) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN09 18 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL0_BANK0_PIN09) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN08 16 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL0_BANK0_PIN08) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00) + +#define HW_PINCTRL_MUXSEL1 (0x00000110) +#define HW_PINCTRL_MUXSEL1_SET (0x00000114) +#define HW_PINCTRL_MUXSEL1_CLR (0x00000118) +#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c) + +#define BP_PINCTRL_MUXSEL1_BANK0_PIN31 30 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL1_BANK0_PIN31) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN30 28 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL1_BANK0_PIN30) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN29 26 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL1_BANK0_PIN29) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16) + +#define HW_PINCTRL_MUXSEL2 (0x00000120) +#define HW_PINCTRL_MUXSEL2_SET (0x00000124) +#define HW_PINCTRL_MUXSEL2_CLR (0x00000128) +#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c) + +#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00) + +#define HW_PINCTRL_MUXSEL3 (0x00000130) +#define HW_PINCTRL_MUXSEL3_SET (0x00000134) +#define HW_PINCTRL_MUXSEL3_CLR (0x00000138) +#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c) + +#define BP_PINCTRL_MUXSEL3_RSRVD0 30 +#define BM_PINCTRL_MUXSEL3_RSRVD0 0xC0000000 +#define BF_PINCTRL_MUXSEL3_RSRVD0(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL3_RSRVD0) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16) + +#define HW_PINCTRL_MUXSEL4 (0x00000140) +#define HW_PINCTRL_MUXSEL4_SET (0x00000144) +#define HW_PINCTRL_MUXSEL4_CLR (0x00000148) +#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c) + +#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN11 22 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL4_BANK2_PIN11) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00) + +#define HW_PINCTRL_MUXSEL5 (0x00000150) +#define HW_PINCTRL_MUXSEL5_SET (0x00000154) +#define HW_PINCTRL_MUXSEL5_CLR (0x00000158) +#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c) + +#define BP_PINCTRL_MUXSEL5_BANK2_PIN31 30 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL5_BANK2_PIN31) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN30 28 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL5_BANK2_PIN30) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN29 26 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL5_BANK2_PIN29) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN28 24 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL5_BANK2_PIN28) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN23 14 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL5_BANK2_PIN23) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN22 12 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL5_BANK2_PIN22) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16) + +#define HW_PINCTRL_MUXSEL6 (0x00000160) +#define HW_PINCTRL_MUXSEL6_SET (0x00000164) +#define HW_PINCTRL_MUXSEL6_CLR (0x00000168) +#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c) + +#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00) + +#define HW_PINCTRL_MUXSEL7 (0x00000170) +#define HW_PINCTRL_MUXSEL7_SET (0x00000174) +#define HW_PINCTRL_MUXSEL7_CLR (0x00000178) +#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c) + +#define BP_PINCTRL_MUXSEL7_RSRVD0 12 +#define BM_PINCTRL_MUXSEL7_RSRVD0 0xFFFFF000 +#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL7_RSRVD0) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN19 6 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL7_BANK3_PIN19) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16) + +#define HW_PINCTRL_DRIVE0 (0x00000200) +#define HW_PINCTRL_DRIVE0_SET (0x00000204) +#define HW_PINCTRL_DRIVE0_CLR (0x00000208) +#define HW_PINCTRL_DRIVE0_TOG (0x0000020c) + +#define BP_PINCTRL_DRIVE0_RSRVD7 30 +#define BM_PINCTRL_DRIVE0_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE0_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE0_RSRVD7) +#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA) +#define BP_PINCTRL_DRIVE0_RSRVD6 26 +#define BM_PINCTRL_DRIVE0_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE0_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE0_RSRVD6) +#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA) +#define BP_PINCTRL_DRIVE0_RSRVD5 22 +#define BM_PINCTRL_DRIVE0_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE0_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE0_RSRVD5) +#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA) +#define BP_PINCTRL_DRIVE0_RSRVD4 18 +#define BM_PINCTRL_DRIVE0_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE0_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE0_RSRVD4) +#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA) +#define BP_PINCTRL_DRIVE0_RSRVD3 14 +#define BM_PINCTRL_DRIVE0_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE0_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE0_RSRVD3) +#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA) +#define BP_PINCTRL_DRIVE0_RSRVD2 10 +#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE0_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE0_RSRVD2) +#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA) +#define BP_PINCTRL_DRIVE0_RSRVD1 6 +#define BM_PINCTRL_DRIVE0_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE0_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE0_RSRVD1) +#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA) +#define BP_PINCTRL_DRIVE0_RSRVD0 2 +#define BM_PINCTRL_DRIVE0_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE0_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE0_RSRVD0) +#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA) + +#define HW_PINCTRL_DRIVE1 (0x00000210) +#define HW_PINCTRL_DRIVE1_SET (0x00000214) +#define HW_PINCTRL_DRIVE1_CLR (0x00000218) +#define HW_PINCTRL_DRIVE1_TOG (0x0000021c) + +#define BP_PINCTRL_DRIVE1_RSRVD7 30 +#define BM_PINCTRL_DRIVE1_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE1_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE1_RSRVD7) +#define BP_PINCTRL_DRIVE1_BANK0_PIN15_MA 28 +#define BM_PINCTRL_DRIVE1_BANK0_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE1_BANK0_PIN15_MA) +#define BP_PINCTRL_DRIVE1_RSRVD6 26 +#define BM_PINCTRL_DRIVE1_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE1_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE1_RSRVD6) +#define BP_PINCTRL_DRIVE1_BANK0_PIN14_MA 24 +#define BM_PINCTRL_DRIVE1_BANK0_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE1_BANK0_PIN14_MA) +#define BP_PINCTRL_DRIVE1_RSRVD5 22 +#define BM_PINCTRL_DRIVE1_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE1_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE1_RSRVD5) +#define BP_PINCTRL_DRIVE1_BANK0_PIN13_MA 20 +#define BM_PINCTRL_DRIVE1_BANK0_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE1_BANK0_PIN13_MA) +#define BP_PINCTRL_DRIVE1_RSRVD4 18 +#define BM_PINCTRL_DRIVE1_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE1_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE1_RSRVD4) +#define BP_PINCTRL_DRIVE1_BANK0_PIN12_MA 16 +#define BM_PINCTRL_DRIVE1_BANK0_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE1_BANK0_PIN12_MA) +#define BP_PINCTRL_DRIVE1_RSRVD3 14 +#define BM_PINCTRL_DRIVE1_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE1_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE1_RSRVD3) +#define BP_PINCTRL_DRIVE1_BANK0_PIN11_MA 12 +#define BM_PINCTRL_DRIVE1_BANK0_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE1_BANK0_PIN11_MA) +#define BP_PINCTRL_DRIVE1_RSRVD2 10 +#define BM_PINCTRL_DRIVE1_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE1_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE1_RSRVD2) +#define BP_PINCTRL_DRIVE1_BANK0_PIN10_MA 8 +#define BM_PINCTRL_DRIVE1_BANK0_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE1_BANK0_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE1_BANK0_PIN10_MA) +#define BP_PINCTRL_DRIVE1_RSRVD1 6 +#define BM_PINCTRL_DRIVE1_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE1_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE1_RSRVD1) +#define BP_PINCTRL_DRIVE1_BANK0_PIN09_MA 4 +#define BM_PINCTRL_DRIVE1_BANK0_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE1_BANK0_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE1_BANK0_PIN09_MA) +#define BP_PINCTRL_DRIVE1_RSRVD0 2 +#define BM_PINCTRL_DRIVE1_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE1_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE1_RSRVD0) +#define BP_PINCTRL_DRIVE1_BANK0_PIN08_MA 0 +#define BM_PINCTRL_DRIVE1_BANK0_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE1_BANK0_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE1_BANK0_PIN08_MA) + +#define HW_PINCTRL_DRIVE2 (0x00000220) +#define HW_PINCTRL_DRIVE2_SET (0x00000224) +#define HW_PINCTRL_DRIVE2_CLR (0x00000228) +#define HW_PINCTRL_DRIVE2_TOG (0x0000022c) + +#define BP_PINCTRL_DRIVE2_RSRVD7 30 +#define BM_PINCTRL_DRIVE2_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE2_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE2_RSRVD7) +#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA) +#define BP_PINCTRL_DRIVE2_RSRVD6 26 +#define BM_PINCTRL_DRIVE2_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE2_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE2_RSRVD6) +#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA) +#define BP_PINCTRL_DRIVE2_RSRVD5 22 +#define BM_PINCTRL_DRIVE2_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE2_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE2_RSRVD5) +#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA) +#define BP_PINCTRL_DRIVE2_RSRVD4 18 +#define BM_PINCTRL_DRIVE2_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE2_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE2_RSRVD4) +#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA) +#define BP_PINCTRL_DRIVE2_RSRVD3 14 +#define BM_PINCTRL_DRIVE2_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE2_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE2_RSRVD3) +#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA) +#define BP_PINCTRL_DRIVE2_RSRVD2 10 +#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE2_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE2_RSRVD2) +#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA) +#define BP_PINCTRL_DRIVE2_RSRVD1 6 +#define BM_PINCTRL_DRIVE2_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE2_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE2_RSRVD1) +#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA) +#define BP_PINCTRL_DRIVE2_RSRVD0 2 +#define BM_PINCTRL_DRIVE2_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE2_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE2_RSRVD0) +#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA) + +#define HW_PINCTRL_DRIVE3 (0x00000230) +#define HW_PINCTRL_DRIVE3_SET (0x00000234) +#define HW_PINCTRL_DRIVE3_CLR (0x00000238) +#define HW_PINCTRL_DRIVE3_TOG (0x0000023c) + +#define BP_PINCTRL_DRIVE3_RSRVD7 30 +#define BM_PINCTRL_DRIVE3_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE3_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE3_RSRVD7) +#define BP_PINCTRL_DRIVE3_BANK0_PIN31_MA 28 +#define BM_PINCTRL_DRIVE3_BANK0_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE3_BANK0_PIN31_MA) +#define BP_PINCTRL_DRIVE3_RSRVD6 26 +#define BM_PINCTRL_DRIVE3_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE3_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE3_RSRVD6) +#define BP_PINCTRL_DRIVE3_BANK0_PIN30_MA 24 +#define BM_PINCTRL_DRIVE3_BANK0_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE3_BANK0_PIN30_MA) +#define BP_PINCTRL_DRIVE3_RSRVD5 22 +#define BM_PINCTRL_DRIVE3_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE3_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE3_RSRVD5) +#define BP_PINCTRL_DRIVE3_BANK0_PIN29_MA 20 +#define BM_PINCTRL_DRIVE3_BANK0_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE3_BANK0_PIN29_MA) +#define BP_PINCTRL_DRIVE3_RSRVD4 18 +#define BM_PINCTRL_DRIVE3_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE3_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE3_RSRVD4) +#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA) +#define BP_PINCTRL_DRIVE3_RSRVD3 14 +#define BM_PINCTRL_DRIVE3_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE3_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE3_RSRVD3) +#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA) +#define BP_PINCTRL_DRIVE3_RSRVD2 10 +#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE3_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE3_RSRVD2) +#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA) +#define BP_PINCTRL_DRIVE3_RSRVD1 6 +#define BM_PINCTRL_DRIVE3_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE3_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE3_RSRVD1) +#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA) +#define BP_PINCTRL_DRIVE3_RSRVD0 2 +#define BM_PINCTRL_DRIVE3_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE3_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE3_RSRVD0) +#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA) + +#define HW_PINCTRL_DRIVE4 (0x00000240) +#define HW_PINCTRL_DRIVE4_SET (0x00000244) +#define HW_PINCTRL_DRIVE4_CLR (0x00000248) +#define HW_PINCTRL_DRIVE4_TOG (0x0000024c) + +#define BP_PINCTRL_DRIVE4_RSRVD7 30 +#define BM_PINCTRL_DRIVE4_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE4_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE4_RSRVD7) +#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA) +#define BP_PINCTRL_DRIVE4_RSRVD6 26 +#define BM_PINCTRL_DRIVE4_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE4_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE4_RSRVD6) +#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA) +#define BP_PINCTRL_DRIVE4_RSRVD5 22 +#define BM_PINCTRL_DRIVE4_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE4_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE4_RSRVD5) +#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA) +#define BP_PINCTRL_DRIVE4_RSRVD4 18 +#define BM_PINCTRL_DRIVE4_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE4_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE4_RSRVD4) +#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA) +#define BP_PINCTRL_DRIVE4_RSRVD3 14 +#define BM_PINCTRL_DRIVE4_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE4_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE4_RSRVD3) +#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA) +#define BP_PINCTRL_DRIVE4_RSRVD2 10 +#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE4_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE4_RSRVD2) +#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA) +#define BP_PINCTRL_DRIVE4_RSRVD1 6 +#define BM_PINCTRL_DRIVE4_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE4_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE4_RSRVD1) +#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA) +#define BP_PINCTRL_DRIVE4_RSRVD0 2 +#define BM_PINCTRL_DRIVE4_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE4_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE4_RSRVD0) +#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA) + +#define HW_PINCTRL_DRIVE5 (0x00000250) +#define HW_PINCTRL_DRIVE5_SET (0x00000254) +#define HW_PINCTRL_DRIVE5_CLR (0x00000258) +#define HW_PINCTRL_DRIVE5_TOG (0x0000025c) + +#define BP_PINCTRL_DRIVE5_RSRVD7 30 +#define BM_PINCTRL_DRIVE5_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE5_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE5_RSRVD7) +#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA) +#define BP_PINCTRL_DRIVE5_RSRVD6 26 +#define BM_PINCTRL_DRIVE5_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE5_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE5_RSRVD6) +#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA) +#define BP_PINCTRL_DRIVE5_RSRVD5 22 +#define BM_PINCTRL_DRIVE5_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE5_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE5_RSRVD5) +#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA) +#define BP_PINCTRL_DRIVE5_RSRVD4 18 +#define BM_PINCTRL_DRIVE5_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE5_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE5_RSRVD4) +#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA) +#define BP_PINCTRL_DRIVE5_RSRVD3 14 +#define BM_PINCTRL_DRIVE5_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE5_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE5_RSRVD3) +#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA) +#define BP_PINCTRL_DRIVE5_RSRVD2 10 +#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE5_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE5_RSRVD2) +#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA) +#define BP_PINCTRL_DRIVE5_RSRVD1 6 +#define BM_PINCTRL_DRIVE5_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE5_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE5_RSRVD1) +#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA) +#define BP_PINCTRL_DRIVE5_RSRVD0 2 +#define BM_PINCTRL_DRIVE5_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE5_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE5_RSRVD0) +#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA) + +#define HW_PINCTRL_DRIVE6 (0x00000260) +#define HW_PINCTRL_DRIVE6_SET (0x00000264) +#define HW_PINCTRL_DRIVE6_CLR (0x00000268) +#define HW_PINCTRL_DRIVE6_TOG (0x0000026c) + +#define BP_PINCTRL_DRIVE6_RSRVD7 30 +#define BM_PINCTRL_DRIVE6_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE6_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE6_RSRVD7) +#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA) +#define BP_PINCTRL_DRIVE6_RSRVD6 26 +#define BM_PINCTRL_DRIVE6_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE6_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE6_RSRVD6) +#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA) +#define BP_PINCTRL_DRIVE6_RSRVD5 22 +#define BM_PINCTRL_DRIVE6_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE6_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE6_RSRVD5) +#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA) +#define BP_PINCTRL_DRIVE6_RSRVD4 18 +#define BM_PINCTRL_DRIVE6_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE6_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE6_RSRVD4) +#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA) +#define BP_PINCTRL_DRIVE6_RSRVD3 14 +#define BM_PINCTRL_DRIVE6_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE6_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE6_RSRVD3) +#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA) +#define BP_PINCTRL_DRIVE6_RSRVD2 10 +#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE6_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE6_RSRVD2) +#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA) +#define BP_PINCTRL_DRIVE6_RSRVD1 6 +#define BM_PINCTRL_DRIVE6_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE6_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE6_RSRVD1) +#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA) +#define BP_PINCTRL_DRIVE6_RSRVD0 2 +#define BM_PINCTRL_DRIVE6_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE6_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE6_RSRVD0) +#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA) + +#define HW_PINCTRL_DRIVE7 (0x00000270) +#define HW_PINCTRL_DRIVE7_SET (0x00000274) +#define HW_PINCTRL_DRIVE7_CLR (0x00000278) +#define HW_PINCTRL_DRIVE7_TOG (0x0000027c) + +#define BP_PINCTRL_DRIVE7_RSRVD7 28 +#define BM_PINCTRL_DRIVE7_RSRVD7 0xF0000000 +#define BF_PINCTRL_DRIVE7_RSRVD7(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE7_RSRVD7) +#define BP_PINCTRL_DRIVE7_RSRVD6 26 +#define BM_PINCTRL_DRIVE7_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE7_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE7_RSRVD6) +#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA) +#define BP_PINCTRL_DRIVE7_RSRVD5 22 +#define BM_PINCTRL_DRIVE7_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE7_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE7_RSRVD5) +#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA) +#define BP_PINCTRL_DRIVE7_RSRVD4 18 +#define BM_PINCTRL_DRIVE7_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE7_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE7_RSRVD4) +#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA) +#define BP_PINCTRL_DRIVE7_RSRVD3 14 +#define BM_PINCTRL_DRIVE7_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE7_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE7_RSRVD3) +#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA) +#define BP_PINCTRL_DRIVE7_RSRVD2 10 +#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE7_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE7_RSRVD2) +#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA) +#define BP_PINCTRL_DRIVE7_RSRVD1 6 +#define BM_PINCTRL_DRIVE7_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE7_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE7_RSRVD1) +#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA) +#define BP_PINCTRL_DRIVE7_RSRVD0 2 +#define BM_PINCTRL_DRIVE7_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE7_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE7_RSRVD0) +#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA) + +#define HW_PINCTRL_DRIVE8 (0x00000280) +#define HW_PINCTRL_DRIVE8_SET (0x00000284) +#define HW_PINCTRL_DRIVE8_CLR (0x00000288) +#define HW_PINCTRL_DRIVE8_TOG (0x0000028c) + +#define BP_PINCTRL_DRIVE8_RSRVD7 30 +#define BM_PINCTRL_DRIVE8_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE8_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE8_RSRVD7) +#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA) +#define BP_PINCTRL_DRIVE8_RSRVD6 26 +#define BM_PINCTRL_DRIVE8_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE8_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE8_RSRVD6) +#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA) +#define BP_PINCTRL_DRIVE8_RSRVD5 22 +#define BM_PINCTRL_DRIVE8_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE8_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE8_RSRVD5) +#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA) +#define BP_PINCTRL_DRIVE8_RSRVD4 18 +#define BM_PINCTRL_DRIVE8_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE8_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE8_RSRVD4) +#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA) +#define BP_PINCTRL_DRIVE8_RSRVD3 14 +#define BM_PINCTRL_DRIVE8_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE8_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE8_RSRVD3) +#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA) +#define BP_PINCTRL_DRIVE8_RSRVD2 10 +#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE8_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE8_RSRVD2) +#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA) +#define BP_PINCTRL_DRIVE8_RSRVD1 6 +#define BM_PINCTRL_DRIVE8_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE8_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE8_RSRVD1) +#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA) +#define BP_PINCTRL_DRIVE8_RSRVD0 2 +#define BM_PINCTRL_DRIVE8_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE8_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE8_RSRVD0) +#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA) + +#define HW_PINCTRL_DRIVE9 (0x00000290) +#define HW_PINCTRL_DRIVE9_SET (0x00000294) +#define HW_PINCTRL_DRIVE9_CLR (0x00000298) +#define HW_PINCTRL_DRIVE9_TOG (0x0000029c) + +#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA) +#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA) +#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA) +#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA) +#define BM_PINCTRL_DRIVE9_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN11_MA 12 +#define BM_PINCTRL_DRIVE9_BANK2_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE9_BANK2_PIN11_MA) +#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA) +#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA) +#define BP_PINCTRL_DRIVE9_RSRVD0 2 +#define BM_PINCTRL_DRIVE9_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE9_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE9_RSRVD0) +#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA) + +#define HW_PINCTRL_DRIVE10 (0x000002a0) +#define HW_PINCTRL_DRIVE10_SET (0x000002a4) +#define HW_PINCTRL_DRIVE10_CLR (0x000002a8) +#define HW_PINCTRL_DRIVE10_TOG (0x000002ac) + +#define BM_PINCTRL_DRIVE10_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN23_MA 28 +#define BM_PINCTRL_DRIVE10_BANK2_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE10_BANK2_PIN23_MA) +#define BM_PINCTRL_DRIVE10_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN22_MA 24 +#define BM_PINCTRL_DRIVE10_BANK2_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE10_BANK2_PIN22_MA) +#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA) +#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA) +#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA) +#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA) +#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA) +#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA) + +#define HW_PINCTRL_DRIVE11 (0x000002b0) +#define HW_PINCTRL_DRIVE11_SET (0x000002b4) +#define HW_PINCTRL_DRIVE11_CLR (0x000002b8) +#define HW_PINCTRL_DRIVE11_TOG (0x000002bc) + +#define BM_PINCTRL_DRIVE11_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN31_V 0x40000000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN31_MA 28 +#define BM_PINCTRL_DRIVE11_BANK2_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE11_BANK2_PIN31_MA) +#define BM_PINCTRL_DRIVE11_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN30_MA 24 +#define BM_PINCTRL_DRIVE11_BANK2_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE11_BANK2_PIN30_MA) +#define BM_PINCTRL_DRIVE11_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN29_MA 20 +#define BM_PINCTRL_DRIVE11_BANK2_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE11_BANK2_PIN29_MA) +#define BP_PINCTRL_DRIVE11_RSRVD4 18 +#define BM_PINCTRL_DRIVE11_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE11_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE11_RSRVD4) +#define BP_PINCTRL_DRIVE11_BANK2_PIN28_MA 16 +#define BM_PINCTRL_DRIVE11_BANK2_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE11_BANK2_PIN28_MA) +#define BP_PINCTRL_DRIVE11_RSRVD3 14 +#define BM_PINCTRL_DRIVE11_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE11_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE11_RSRVD3) +#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA) +#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA) +#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA) +#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA) + +#define HW_PINCTRL_DRIVE12 (0x000002c0) +#define HW_PINCTRL_DRIVE12_SET (0x000002c4) +#define HW_PINCTRL_DRIVE12_CLR (0x000002c8) +#define HW_PINCTRL_DRIVE12_TOG (0x000002cc) + +#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA) +#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA) +#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA) +#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA) +#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA) +#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA) +#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA) +#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA) + +#define HW_PINCTRL_DRIVE13 (0x000002d0) +#define HW_PINCTRL_DRIVE13_SET (0x000002d4) +#define HW_PINCTRL_DRIVE13_CLR (0x000002d8) +#define HW_PINCTRL_DRIVE13_TOG (0x000002dc) + +#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA) +#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA) +#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA) +#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA) +#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA) +#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA) +#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA) +#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA) + +#define HW_PINCTRL_DRIVE14 (0x000002e0) +#define HW_PINCTRL_DRIVE14_SET (0x000002e4) +#define HW_PINCTRL_DRIVE14_CLR (0x000002e8) +#define HW_PINCTRL_DRIVE14_TOG (0x000002ec) + +#define BP_PINCTRL_DRIVE14_RSRVD6 24 +#define BM_PINCTRL_DRIVE14_RSRVD6 0xFF000000 +#define BF_PINCTRL_DRIVE14_RSRVD6(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE14_RSRVD6) +#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA) +#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA) +#define BM_PINCTRL_DRIVE14_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN19_MA 12 +#define BM_PINCTRL_DRIVE14_BANK3_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE14_BANK3_PIN19_MA) +#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA) +#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA) +#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA) + +#define HW_PINCTRL_PULL0 (0x00000400) +#define HW_PINCTRL_PULL0_SET (0x00000404) +#define HW_PINCTRL_PULL0_CLR (0x00000408) +#define HW_PINCTRL_PULL0_TOG (0x0000040c) + +#define BM_PINCTRL_PULL0_BANK0_PIN31 0x80000000 +#define BM_PINCTRL_PULL0_BANK0_PIN30 0x40000000 +#define BM_PINCTRL_PULL0_BANK0_PIN29 0x20000000 +#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000 +#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000 +#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000 +#define BP_PINCTRL_PULL0_RSRVD2 23 +#define BM_PINCTRL_PULL0_RSRVD2 0x03800000 +#define BF_PINCTRL_PULL0_RSRVD2(v) \ + (((v) << 23) & BM_PINCTRL_PULL0_RSRVD2) +#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000 +#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000 +#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000 +#define BP_PINCTRL_PULL0_RSRVD1 16 +#define BM_PINCTRL_PULL0_RSRVD1 0x00030000 +#define BF_PINCTRL_PULL0_RSRVD1(v) \ + (((v) << 16) & BM_PINCTRL_PULL0_RSRVD1) +#define BM_PINCTRL_PULL0_BANK0_PIN15 0x00008000 +#define BP_PINCTRL_PULL0_RSRVD0 12 +#define BM_PINCTRL_PULL0_RSRVD0 0x00007000 +#define BF_PINCTRL_PULL0_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_PULL0_RSRVD0) +#define BM_PINCTRL_PULL0_BANK0_PIN11 0x00000800 +#define BM_PINCTRL_PULL0_BANK0_PIN10 0x00000400 +#define BM_PINCTRL_PULL0_BANK0_PIN09 0x00000200 +#define BM_PINCTRL_PULL0_BANK0_PIN08 0x00000100 +#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080 +#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040 +#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001 + +#define HW_PINCTRL_PULL1 (0x00000410) +#define HW_PINCTRL_PULL1_SET (0x00000414) +#define HW_PINCTRL_PULL1_CLR (0x00000418) +#define HW_PINCTRL_PULL1_TOG (0x0000041c) + +#define BP_PINCTRL_PULL1_RSRVD3 29 +#define BM_PINCTRL_PULL1_RSRVD3 0xE0000000 +#define BF_PINCTRL_PULL1_RSRVD3(v) \ + (((v) << 29) & BM_PINCTRL_PULL1_RSRVD3) +#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000 +#define BP_PINCTRL_PULL1_RSRVD2 23 +#define BM_PINCTRL_PULL1_RSRVD2 0x0F800000 +#define BF_PINCTRL_PULL1_RSRVD2(v) \ + (((v) << 23) & BM_PINCTRL_PULL1_RSRVD2) +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BP_PINCTRL_PULL1_RSRVD1 19 +#define BM_PINCTRL_PULL1_RSRVD1 0x00380000 +#define BF_PINCTRL_PULL1_RSRVD1(v) \ + (((v) << 19) & BM_PINCTRL_PULL1_RSRVD1) +#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000 +#define BP_PINCTRL_PULL1_RSRVD0 0 +#define BM_PINCTRL_PULL1_RSRVD0 0x0003FFFF +#define BF_PINCTRL_PULL1_RSRVD0(v) \ + (((v) << 0) & BM_PINCTRL_PULL1_RSRVD0) + +#define HW_PINCTRL_PULL2 (0x00000420) +#define HW_PINCTRL_PULL2_SET (0x00000424) +#define HW_PINCTRL_PULL2_CLR (0x00000428) +#define HW_PINCTRL_PULL2_TOG (0x0000042c) + +#define BP_PINCTRL_PULL2_RSRVD2 29 +#define BM_PINCTRL_PULL2_RSRVD2 0xE0000000 +#define BF_PINCTRL_PULL2_RSRVD2(v) \ + (((v) << 29) & BM_PINCTRL_PULL2_RSRVD2) +#define BM_PINCTRL_PULL2_BANK2_PIN28 0x10000000 +#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000 +#define BP_PINCTRL_PULL2_RSRVD1 9 +#define BM_PINCTRL_PULL2_RSRVD1 0x07FFFE00 +#define BF_PINCTRL_PULL2_RSRVD1(v) \ + (((v) << 9) & BM_PINCTRL_PULL2_RSRVD1) +#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100 +#define BP_PINCTRL_PULL2_RSRVD0 6 +#define BM_PINCTRL_PULL2_RSRVD0 0x000000C0 +#define BF_PINCTRL_PULL2_RSRVD0(v) \ + (((v) << 6) & BM_PINCTRL_PULL2_RSRVD0) +#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020 +#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010 +#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008 +#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004 +#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002 +#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001 + +#define HW_PINCTRL_PULL3 (0x00000430) +#define HW_PINCTRL_PULL3_SET (0x00000434) +#define HW_PINCTRL_PULL3_CLR (0x00000438) +#define HW_PINCTRL_PULL3_TOG (0x0000043c) + +#define BP_PINCTRL_PULL3_RSRVD0 18 +#define BM_PINCTRL_PULL3_RSRVD0 0xFFFC0000 +#define BF_PINCTRL_PULL3_RSRVD0(v) \ + (((v) << 18) & BM_PINCTRL_PULL3_RSRVD0) +#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000 +#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000 +#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000 +#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000 +#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000 +#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000 +#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800 +#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400 +#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200 +#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100 +#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080 +#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040 +#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020 +#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010 +#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008 +#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004 +#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002 +#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001 + +#define HW_PINCTRL_DOUT0 (0x00000500) +#define HW_PINCTRL_DOUT0_SET (0x00000504) +#define HW_PINCTRL_DOUT0_CLR (0x00000508) +#define HW_PINCTRL_DOUT0_TOG (0x0000050c) + +#define BP_PINCTRL_DOUT0_DOUT 0 +#define BM_PINCTRL_DOUT0_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT0_DOUT(v) (v) + +#define HW_PINCTRL_DOUT1 (0x00000510) +#define HW_PINCTRL_DOUT1_SET (0x00000514) +#define HW_PINCTRL_DOUT1_CLR (0x00000518) +#define HW_PINCTRL_DOUT1_TOG (0x0000051c) + +#define BM_PINCTRL_DOUT1_RSRVD1 0x80000000 +#define BP_PINCTRL_DOUT1_DOUT 0 +#define BM_PINCTRL_DOUT1_DOUT 0x7FFFFFFF +#define BF_PINCTRL_DOUT1_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT1_DOUT) + +#define HW_PINCTRL_DOUT2 (0x00000520) +#define HW_PINCTRL_DOUT2_SET (0x00000524) +#define HW_PINCTRL_DOUT2_CLR (0x00000528) +#define HW_PINCTRL_DOUT2_TOG (0x0000052c) + +#define BP_PINCTRL_DOUT2_DOUT 0 +#define BM_PINCTRL_DOUT2_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT2_DOUT(v) (v) + +#define HW_PINCTRL_DIN0 (0x00000600) +#define HW_PINCTRL_DIN0_SET (0x00000604) +#define HW_PINCTRL_DIN0_CLR (0x00000608) +#define HW_PINCTRL_DIN0_TOG (0x0000060c) + +#define BP_PINCTRL_DIN0_DIN 0 +#define BM_PINCTRL_DIN0_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN0_DIN(v) (v) + +#define HW_PINCTRL_DIN1 (0x00000610) +#define HW_PINCTRL_DIN1_SET (0x00000614) +#define HW_PINCTRL_DIN1_CLR (0x00000618) +#define HW_PINCTRL_DIN1_TOG (0x0000061c) + +#define BM_PINCTRL_DIN1_RSRVD1 0x80000000 +#define BP_PINCTRL_DIN1_DIN 0 +#define BM_PINCTRL_DIN1_DIN 0x7FFFFFFF +#define BF_PINCTRL_DIN1_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN1_DIN) + +#define HW_PINCTRL_DIN2 (0x00000620) +#define HW_PINCTRL_DIN2_SET (0x00000624) +#define HW_PINCTRL_DIN2_CLR (0x00000628) +#define HW_PINCTRL_DIN2_TOG (0x0000062c) + +#define BP_PINCTRL_DIN2_DIN 0 +#define BM_PINCTRL_DIN2_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN2_DIN(v) (v) + +#define HW_PINCTRL_DOE0 (0x00000700) +#define HW_PINCTRL_DOE0_SET (0x00000704) +#define HW_PINCTRL_DOE0_CLR (0x00000708) +#define HW_PINCTRL_DOE0_TOG (0x0000070c) + +#define BP_PINCTRL_DOE0_DOE 0 +#define BM_PINCTRL_DOE0_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE0_DOE(v) (v) + +#define HW_PINCTRL_DOE1 (0x00000710) +#define HW_PINCTRL_DOE1_SET (0x00000714) +#define HW_PINCTRL_DOE1_CLR (0x00000718) +#define HW_PINCTRL_DOE1_TOG (0x0000071c) + +#define BM_PINCTRL_DOE1_RSRVD1 0x80000000 +#define BP_PINCTRL_DOE1_DOE 0 +#define BM_PINCTRL_DOE1_DOE 0x7FFFFFFF +#define BF_PINCTRL_DOE1_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE1_DOE) + +#define HW_PINCTRL_DOE2 (0x00000720) +#define HW_PINCTRL_DOE2_SET (0x00000724) +#define HW_PINCTRL_DOE2_CLR (0x00000728) +#define HW_PINCTRL_DOE2_TOG (0x0000072c) + +#define BP_PINCTRL_DOE2_DOE 0 +#define BM_PINCTRL_DOE2_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE2_DOE(v) (v) + +#define HW_PINCTRL_PIN2IRQ0 (0x00000800) +#define HW_PINCTRL_PIN2IRQ0_SET (0x00000804) +#define HW_PINCTRL_PIN2IRQ0_CLR (0x00000808) +#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000080c) + +#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) (v) + +#define HW_PINCTRL_PIN2IRQ1 (0x00000810) +#define HW_PINCTRL_PIN2IRQ1_SET (0x00000814) +#define HW_PINCTRL_PIN2IRQ1_CLR (0x00000818) +#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000081c) + +#define BM_PINCTRL_PIN2IRQ1_RSRVD1 0x80000000 +#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0x7FFFFFFF +#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ1_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ2 (0x00000820) +#define HW_PINCTRL_PIN2IRQ2_SET (0x00000824) +#define HW_PINCTRL_PIN2IRQ2_CLR (0x00000828) +#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000082c) + +#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) (v) + +#define HW_PINCTRL_IRQEN0 (0x00000900) +#define HW_PINCTRL_IRQEN0_SET (0x00000904) +#define HW_PINCTRL_IRQEN0_CLR (0x00000908) +#define HW_PINCTRL_IRQEN0_TOG (0x0000090c) + +#define BP_PINCTRL_IRQEN0_IRQEN 0 +#define BM_PINCTRL_IRQEN0_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN0_IRQEN(v) (v) + +#define HW_PINCTRL_IRQEN1 (0x00000910) +#define HW_PINCTRL_IRQEN1_SET (0x00000914) +#define HW_PINCTRL_IRQEN1_CLR (0x00000918) +#define HW_PINCTRL_IRQEN1_TOG (0x0000091c) + +#define BM_PINCTRL_IRQEN1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQEN1_IRQEN 0 +#define BM_PINCTRL_IRQEN1_IRQEN 0x7FFFFFFF +#define BF_PINCTRL_IRQEN1_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN1_IRQEN) + +#define HW_PINCTRL_IRQEN2 (0x00000920) +#define HW_PINCTRL_IRQEN2_SET (0x00000924) +#define HW_PINCTRL_IRQEN2_CLR (0x00000928) +#define HW_PINCTRL_IRQEN2_TOG (0x0000092c) + +#define BP_PINCTRL_IRQEN2_IRQEN 0 +#define BM_PINCTRL_IRQEN2_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN2_IRQEN(v) (v) + +#define HW_PINCTRL_IRQLEVEL0 (0x00000a00) +#define HW_PINCTRL_IRQLEVEL0_SET (0x00000a04) +#define HW_PINCTRL_IRQLEVEL0_CLR (0x00000a08) +#define HW_PINCTRL_IRQLEVEL0_TOG (0x00000a0c) + +#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQLEVEL1 (0x00000a10) +#define HW_PINCTRL_IRQLEVEL1_SET (0x00000a14) +#define HW_PINCTRL_IRQLEVEL1_CLR (0x00000a18) +#define HW_PINCTRL_IRQLEVEL1_TOG (0x00000a1c) + +#define BM_PINCTRL_IRQLEVEL1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0x7FFFFFFF +#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL1_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL2 (0x00000a20) +#define HW_PINCTRL_IRQLEVEL2_SET (0x00000a24) +#define HW_PINCTRL_IRQLEVEL2_CLR (0x00000a28) +#define HW_PINCTRL_IRQLEVEL2_TOG (0x00000a2c) + +#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQPOL0 (0x00000b00) +#define HW_PINCTRL_IRQPOL0_SET (0x00000b04) +#define HW_PINCTRL_IRQPOL0_CLR (0x00000b08) +#define HW_PINCTRL_IRQPOL0_TOG (0x00000b0c) + +#define BP_PINCTRL_IRQPOL0_IRQPOL 0 +#define BM_PINCTRL_IRQPOL0_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL0_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQPOL1 (0x00000b10) +#define HW_PINCTRL_IRQPOL1_SET (0x00000b14) +#define HW_PINCTRL_IRQPOL1_CLR (0x00000b18) +#define HW_PINCTRL_IRQPOL1_TOG (0x00000b1c) + +#define BM_PINCTRL_IRQPOL1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQPOL1_IRQPOL 0 +#define BM_PINCTRL_IRQPOL1_IRQPOL 0x7FFFFFFF +#define BF_PINCTRL_IRQPOL1_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL1_IRQPOL) + +#define HW_PINCTRL_IRQPOL2 (0x00000b20) +#define HW_PINCTRL_IRQPOL2_SET (0x00000b24) +#define HW_PINCTRL_IRQPOL2_CLR (0x00000b28) +#define HW_PINCTRL_IRQPOL2_TOG (0x00000b2c) + +#define BP_PINCTRL_IRQPOL2_IRQPOL 0 +#define BM_PINCTRL_IRQPOL2_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL2_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQSTAT0 (0x00000c00) +#define HW_PINCTRL_IRQSTAT0_SET (0x00000c04) +#define HW_PINCTRL_IRQSTAT0_CLR (0x00000c08) +#define HW_PINCTRL_IRQSTAT0_TOG (0x00000c0c) + +#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) (v) + +#define HW_PINCTRL_IRQSTAT1 (0x00000c10) +#define HW_PINCTRL_IRQSTAT1_SET (0x00000c14) +#define HW_PINCTRL_IRQSTAT1_CLR (0x00000c18) +#define HW_PINCTRL_IRQSTAT1_TOG (0x00000c1c) + +#define BM_PINCTRL_IRQSTAT1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0x7FFFFFFF +#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT1_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT2 (0x00000c20) +#define HW_PINCTRL_IRQSTAT2_SET (0x00000c24) +#define HW_PINCTRL_IRQSTAT2_CLR (0x00000c28) +#define HW_PINCTRL_IRQSTAT2_TOG (0x00000c2c) + +#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) (v) +#endif /* __ARCH_ARM___PINCTRL_H */ diff --git a/arch/arm/mach-mx23/serial.c b/arch/arm/mach-mx23/serial.c new file mode 100644 index 000000000000..85a08cdc8c1b --- /dev/null +++ b/arch/arm/mach-mx23/serial.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is distributed in the hope that it will be useful, + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "device.h" + +#if defined(CONFIG_SERIAL_MXS_AUART) || \ + defined(CONFIG_SERIAL_MXS_AUART_MODULE) + +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE +static struct resource auart1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART1_PHYS_ADDR, + .end = AUART1_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_UARTAPP_INTERNAL, + .end = IRQ_UARTAPP_INTERNAL, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_UARTAPP_RX_DMA, + .end = IRQ_UARTAPP_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_UARTAPP_TX_DMA, + .end = IRQ_UARTAPP_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart1_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART1_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = 8, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE +static struct resource auart2_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART2_PHYS_ADDR, + .end = AUART2_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_UARTAPP2_INTERNAL, + .end = IRQ_UARTAPP2_INTERNAL, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_UARTAPP2_RX_DMA, + .end = IRQ_UARTAPP2_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_UARTAPP2_TX_DMA, + .end = IRQ_UARTAPP2_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart2_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART2_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = 8, + .timeout = HZ, +}; +#endif + +void __init mx23_init_auart(void) +{ + int i; + struct mxs_dev_lookup *plookup; + struct platform_device *pdev; + + plookup = mxs_get_devices("mxs-auart"); + if (plookup == NULL || IS_ERR(plookup)) + return; + for (i = 0; i < plookup->size; i++) { + pdev = plookup->pdev + i; + switch (pdev->id) { +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE + case 1: + pdev->resource = auart1_resource; + pdev->num_resources = ARRAY_SIZE(auart1_resource); + pdev->dev.platform_data = &mxs_auart1_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE + case 2: + pdev->resource = auart2_resource; + pdev->num_resources = ARRAY_SIZE(auart2_resource); + pdev->dev.platform_data = &mxs_auart2_platdata; + break; +#endif + default: + break; + } + mxs_add_device(pdev, 3); + } +} +#else +void __init mx23_init_auart(void) +{ +} +#endif diff --git a/arch/arm/mach-mx23/sleep.S b/arch/arm/mach-mx23/sleep.S new file mode 100644 index 000000000000..0e6b00f9095a --- /dev/null +++ b/arch/arm/mach-mx23/sleep.S @@ -0,0 +1,553 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "regs-clkctrl.h" +#include "sleep.h" + +#define HW_CLKCTRL_CPU_ADDR \ + (MX23_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_CPU) +#define HW_POWER_MINPWR_ADDR \ + (MX23_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_MINPWR) +#define HW_POWER_RESET_ADDR \ + (MX23_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_RESET) + +#define HW_DRAM_CTL06 MX23_SOC_IO_ADDRESS(0x800E0018) +#define HW_DRAM_CTL08 MX23_SOC_IO_ADDRESS(0x800E0020) +#define HW_EMI_STAT MX23_SOC_IO_ADDRESS(0x80020010) +#define HW_RTC_PERSISTENT0 \ + MX23_SOC_IO_ADDRESS(0x8005C060) + +#define PHYS_RAM_START 0x40000000 + +.global cpu_arm926_switch_mm + + .text + +.align 8 +ENTRY(mx23_cpu_standby) + @ save registers on stack + stmfd sp!, {r0 - r9, lr} + + adr r9, __mx23_temp_stack + + @ clean cache + ldr r1, __mx23_flush_cache_addr + mov lr, pc + mov pc, r1 + + @ put DRAM into self refresh + mov r0, #(HW_DRAM_CTL08 & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL08 & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL08 & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL08 & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(1 << 8) + str r1, [r0] + @ wait for it to actually happen + mov r0, #(HW_EMI_STAT & 0x000000FF) + orr r0, r0, #(HW_EMI_STAT & 0x0000FF00) + orr r0, r0, #(HW_EMI_STAT & 0x00FF0000) + orr r0, r0, #(HW_EMI_STAT & 0xFF000000) +1: ldr r1, [r0] + teq r1, #(1 << 1) + beq 1b + nop + nop + nop + nop + nop + +#ifdef CONFIG_STMP378X_RAM_FREQ_SCALING + @ RAM to clk from xtal + mov lr, pc + b mx23_ram_save_timings + mov lr, pc + b mx23_ram_24M_set_timings + + mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000) + ldr r4, [r0] + mov r1, #(1<<6) + str r1, [r0, #4] +1: ldr r1, [r0] + tst r1, #BM_CLKCTRL_EMI_BUSY_REF_XTAL + bne 1b + + @ save RAM divisors + mov r0, #(HW_CLKCTRL_FRAC_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0xFF000000) + ldr r8, [r0] + and r8, r8, #(0x3F << 8) + lsr r8, r8, #8 + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + ldr r7, [r0] + and r7, r7, #0x3F + + @ shut the PLL down + mov r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0xFF000000) + mov r1, #(1<<16) + str r1, [r0, #0x08] @ clear + + @ set vddd to minimum + mov r0, #(HW_POWER_VDDDCTRL_ADDR & 0x000000FF) + orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x0000FF00) + orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x00FF0000) + orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0xFF000000) + ldr r6, [r0] + bic r1, r6, #0xFF + bic r1, r1, #0x30 + orr r1, r1, #0xa + str r1, [r0] + /* now wait 1000 us = 24000 cycles */ + mov r0, #24 << 10 +3: sub r0, r0, #1 + cmp r0, #0 + bne 3b + nop +#endif + + @ do enter standby + mov r0, #(HW_CLKCTRL_CPU_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0xFF000000) + mov r1, #(1<<12) + str r1, [r0, #4] + mov r2, #0 + mcr p15, 0, r2, c7, c0, 4 + nop + + @ sleeping now... + + @ remove INTERRUPT_WAIT bit + str r1, [r0, #8] + nop + nop + nop + +#ifdef CONFIG_STMP378X_RAM_FREQ_SCALING + @ restore vddd + mov r0, #(HW_POWER_VDDDCTRL_ADDR & 0x000000FF) + orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x0000FF00) + orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x00FF0000) + orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0xFF000000) + ldr r1, [r0] + str r6, [r0] + /* now wait 1000 us = 24000 cycles */ + mov r0, #24 << 10 +12: sub r0, r0, #1 + cmp r0, #0 + bne 12b + nop + + @ put the PLL back up + mov r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0xFF000000) + mov r1, #(1<<16) + str r1, [r0, #0x04] @ set + /* now wait 10 us = 240 cycles */ + mov r0, #240 +11: sub r0, r0, #1 + cmp r0, #0 + bne 11b + nop + + @ set divisors and switch EMI back to PLL + mov lr, pc + b mx23_ram_restore_timings + mov lr, pc + b __mx23_emi_set_values + + mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000) + mov r1, #(1<<6) + str r1, [r0, #8] + + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + ldr r1, [r0] + bic r1, #BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE + str r1, [r0] +#endif + + @ restore normal DRAM mode + mov r0, #(HW_DRAM_CTL08 & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL08 & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL08 & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL08 & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(1 << 8) + str r1, [r0] + @ wait for it to actually happen + mov r0, #(HW_EMI_STAT & 0x000000FF) + orr r0, r0, #(HW_EMI_STAT & 0x0000FF00) + orr r0, r0, #(HW_EMI_STAT & 0x00FF0000) + orr r0, r0, #(HW_EMI_STAT & 0xFF000000) +102: ldr r1, [r0] + tst r1, #(1 << 1) + bne 102b + + nop + nop + nop + + @ restore regs and return + ldmfd sp!, {r0 - r9, pc} + + .space 0x100 +__mx23_temp_stack: + .word 0 + +#ifdef CONFIG_STMP378X_RAM_FREQ_SCALING +#include "emi.inc" +#endif + +__mx23_flush_cache_addr: + .word arm926_flush_kern_cache_all + +ENTRY(mx23_standby_alloc_sz) + .word . - mx23_cpu_standby + +ENTRY(mx23_cpu_suspend) + @ save registers on stack + stmfd sp!, {r1 - r12, lr} + + @ save context + mov r0, #0xd3 @ SVC, Interrupts disabled + msr cpsr, r0 + mov r1, #0xC0000000 + ldr r1, [r1] + mrc p15, 0, r0, c1, c0, 0 + str r0, [r1, #MMUCTL_OFFS] + mrc p15, 0, r0, c15, c1, 0 + str r0, [r1, #MMUCPACCESS_OFS] + mrc p15, 0, r0, c2, c0, 0 + str r0, [r1, #MMUTTB_OFFS] + mrc p15, 0, r0, c3, c0, 0 + str r0, [r1, #MMUDOMAIN_OFFS] + mrc p15, 0, r0, c13, c0, 0 + str r0, [r1, #MMUPID_OFFS] + + str sp, [r1, #SVC_SP_OFFS] + mrs r0, spsr + str r0, [r1, #SVC_SPSR_OFFS] + + add r2, r1, #FIQ_SPSR_OFFS + mov r0, #0xd1 @ FIQ, Interrupts disabled + msr cpsr, r0 + mrs r3, spsr + stmia r2!, {r3, r8-r12, sp, lr} + + add r2, r1, #ABT_SPSR_OFFS + mov r0, #0xd7 @ ABT, Interrupts disabled + msr cpsr, r0 + mrs r3, spsr + stmia r2!, {r3, sp, lr} + + add r2, r1, #IRQ_SPSR_OFFS + mov r0, #0xd2 @ IRQ, Interrupts disabled + msr cpsr, r0 + mrs r3, spsr + stmia r2!, {r3, sp, lr} + + add r2, r1, #UND_SPSR_OFFS + mov r0, #0xdb @ UND, Interrupts disabled + msr cpsr, r0 + mrs r3, spsr + stmia r2!, {r3, sp, lr} + + add r2, r1, #SYS_SP_OFFS + mov r0, #0xdf @ SYS, Interrupts disabled + msr cpsr, r0 + stmia r2!, {sp, lr} + + add r2, r1, #SVC_R8_OFFS + mov r0, #0xd3 @ Back to SVC, Interrupts disabled + msr cpsr, r0 + + @ save entry point + sub r1, r1, #(0xC0000000 - PHYS_RAM_START) + mov r0, #0xC0000000 + str r1, [r0] + ldr r1, __mx23_resume_point + sub r1, r1, #(0xC0000000 - PHYS_RAM_START) + str r1, [r0, #4] + mov r0, #0 + + @ clean cache + ldr r1, __mx23_flush_cache_addr2 + mov lr, pc + mov pc, r1 + + @ enable internal xtal + mov r2, #(HW_POWER_MINPWR_ADDR & 0x000000FF) + orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0x0000FF00) + orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0x00FF0000) + orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0xFF000000) + ldr r1, [r2] + orr r1, r1, #(1<<9) + str r1, [r2] + orr r1, r1, #(1<<8) + str r1, [r2] + + @ enable RTC/RAM clocks + mov r0, #(HW_RTC_PERSISTENT0 & 0x000000FF) + orr r0, r0, #(HW_RTC_PERSISTENT0 & 0x0000FF00) + orr r0, r0, #(HW_RTC_PERSISTENT0 & 0x00FF0000) + orr r0, r0, #(HW_RTC_PERSISTENT0 & 0xFF000000) + mov r1, #((1<<4)|(1<<5)|1) + str r1, [r0, #4] + + @ put DRAM into self refresh + mov r0, #(HW_DRAM_CTL08 & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL08 & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL08 & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL08 & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(1 << 8) + str r1, [r0] + @ wait for it to actually happen + mov r0, #(HW_EMI_STAT & 0x000000FF) + orr r0, r0, #(HW_EMI_STAT & 0x0000FF00) + orr r0, r0, #(HW_EMI_STAT & 0x00FF0000) + orr r0, r0, #(HW_EMI_STAT & 0xFF000000) +1: ldr r1, [r0] + teq r1, #(1 << 1) + beq 1b + nop + nop + nop + nop + nop + nop + + @ power off RAM + mov r0, #(HW_DRAM_CTL06 & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL06 & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL06 & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL06 & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(1<<24) + str r1, [r0] + nop + nop + nop + nop + + @ do enter sleep + mov r0, #(HW_POWER_RESET_ADDR & 0x000000FF) + orr r0, r0, #(HW_POWER_RESET_ADDR & 0x0000FF00) + orr r0, r0, #(HW_POWER_RESET_ADDR & 0x00FF0000) + orr r0, r0, #(HW_POWER_RESET_ADDR & 0xFF000000) + mov r1, #0xFF000000 + orr r1, r1, #0x00FF0000 + str r1, [r0, #8] + mov r1, #0x3E000000 + orr r1, r1, #0x00770000 + str r1, [r0, #4] + mov r1, #2 + str r1, [r0, #8] + mov r1, #1 + str r1, [r0, #4] + nop + nop + nop + nop + nop + nop + + @ sleeping now... + +__restore_context: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer + mcr p15, 0, r0, c8, c7, 0 @ Invalidate TLBs + mcr p15, 0, r0, c7, c7, 0 @ Invalidate I & D cache + nop + nop + + mov r0, #0xd3 + msr cpsr, r0 + + bl __create_temp_page_tables + mov r3, r4 + + mov r1, #PHYS_RAM_START + ldr r1, [r1] + ldr r2, [r1, #MMUDOMAIN_OFFS] + ldr r4, [r1, #MMUCPACCESS_OFS] + ldr r5, [r1, #MMUPID_OFFS] + ldr r6, =__resume_after_mmu + ldr r7, [r1, #MMUCTL_OFFS] + ldr r8, [r1, #MMUTTB_OFFS] + add r1, r1, #(0xC0000000 - PHYS_RAM_START) + mov r0, #0 +@ mcr p15, 0, r4, c15, c1, 0 @ cpaccess + mcr p15, 0, r5, c13, c0, 0 @ pid + mcr p15, 0, r2, c3, c0, 0 @ domain + mcr p15, 0, r3, c2, c0, 0 @ ttb + b 1f + .align 5 +1: mov r0, r0 + mcr p15, 0, r7, c1, c0, 0 @ mmuctl + nop + mrc p15, 0, r0, c3, c0, 0 @ read id + mov r0, r0 + mov r0, r0 + sub pc, r6, r5, lsr #32 + nop + nop + nop +__resume_after_mmu: + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ Invalidate TLBs + mcr p15, 0, r0, c7, c7, 0 @ Invalidate I & D cache + + mov r0, r8 + bl cpu_arm926_switch_mm + + mov r0, #0xd1 @FIQ, Interrupts disabled + ldr r2, [r1, #FIQ_SPSR_OFFS] + add r3, r1, #FIQ_R8_OFFS + msr cpsr, r0 + msr spsr, r2 + ldmia r3!, {r8-r12, sp, lr} + + mov r0, #0xd7 @ABT, Interrupts disabled + ldr r2, [r1, #ABT_SPSR_OFFS] + add r3, r1, #ABT_SP_OFFS + msr cpsr, r0 + msr spsr, r2 + ldmia r3!, {sp, lr} + + mov r0, #0xd2 @IRQ, Interrupts disabled + ldr r2, [r1, #IRQ_SPSR_OFFS] + add r3, r1, #IRQ_SP_OFFS + msr cpsr, r0 + msr spsr, r2 + ldmia r3!, {sp, lr} + + mov r0, #0xdb @UND, Interrupts disabled + ldr r2, [r1, #UND_SPSR_OFFS] + add r3, r1, #UND_SP_OFFS + msr cpsr, r0 + msr spsr, r2 + ldmia r3!, {sp, lr} + + mov r0, #0xdf @SYS, Interrupts disabled + add r3, r1, #SYS_SP_OFFS + msr cpsr, r0 + ldmia r3!, {sp, lr} + + mov r0, #0xd3 @SVC, interrupts disabled + ldr r2, [r1, #SVC_SPSR_OFFS] + ldr r3, [r1, #SVC_SP_OFFS] + msr cpsr, r0 + msr spsr, r2 + mov sp, r3 + +#if 0 + @ select CPU bypass, will be cleared afterwards + ldr r0, =HW_CLKCTRL_CLKSEQ_ADDR + ldr r2, =HW_CLKCTRL_HBUS_ADDR + ldr r4, =HW_CLKCTRL_CPU_ADDR + mov r1, #(1<<7) + ldr r3, [r2] + bic r3, r3, #BM_CLKCTRL_HBUS_DIV + orr r3, r3, #1 + ldr r5, [r4] + bic r5, r5, #BM_CLKCTRL_CPU_DIV_CPU + orr r5, r5, #1 + str r1, [r0, #4] + str r3, [r2] + str r5, [r4] +#endif + @ restore regs and return + ldmfd sp!, {r1 - r12, lr} + mov pc, lr + +__mx23_flush_cache_addr2: + .word arm926_flush_kern_cache_all +__mx23_resume_point: + .word __restore_context +ENTRY(mx23_s2ram_alloc_sz) + .word . - mx23_cpu_suspend + +__create_temp_page_tables: + ldr r4, =(__temp_ttb - 0xC0000000 + PHYS_RAM_START) + + /* + * Clear the 16K level 1 swapper page table + */ + mov r0, r4 + mov r3, #0 + add r6, r0, #0x4000 +1: str r3, [r0], #4 + str r3, [r0], #4 + str r3, [r0], #4 + str r3, [r0], #4 + teq r0, r6 + bne 1b + + /* + * Create identity mapping for the area close to where we are to + * cater for the MMU enable. + */ + mov r6, pc, lsr #20 @ kind of where we are + ldr r7, =\ + (PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE\ + | PMD_BIT4 | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ) + + orr r3, r7, r6, lsl #20 @ flags + kernel base + str r3, [r4, r6, lsl #2] @ identity mapping + + mov r6, r6, lsl #20 + add r6, r6, #(0xC0000000-PHYS_RAM_START) + str r3, [r4, r6, lsr #18] + + mov pc, lr + .ltorg + + .section ".sdata", "a" + .align 14 +__temp_ttb: + .space 0x8000 diff --git a/arch/arm/mach-mx23/sleep.h b/arch/arm/mach-mx23/sleep.h new file mode 100644 index 000000000000..54695bc89020 --- /dev/null +++ b/arch/arm/mach-mx23/sleep.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#ifndef __PM_H__ +#define __PM_H__ + +#include "regs-clkctrl.h" + +#define MMUTTB1_MASK 0x00003FE0 +#define MMUTTBC_MASK 0xFFFFFFFC + +#define LINK_OFFS 0x08 +#define MMUCTL_OFFS 0x0C +#define MMUAUXCTL_OFFS 0x10 +#define MMUCPACCESS_OFS 0x14 +#define MMUTTB_OFFS 0x18 +#define MMUPID_OFFS 0x1C +#define MMUDOMAIN_OFFS 0x20 +#define SVC_R8_OFFS 0x2C +#define SVC_SP_OFFS 0x40 +#define SVC_SPSR_OFFS 0x44 +#define FIQ_SPSR_OFFS 0x48 +#define FIQ_R8_OFFS 0x4C +#define FIQ_SP_OFFS 0x60 +#define ABT_R8_OFFS 0x68 +#define ABT_SPSR_OFFS 0x7C +#define ABT_SP_OFFS 0x80 +#define IRQ_R8_OFFS 0x88 +#define IRQ_SPSR_OFFS 0x9C +#define IRQ_SP_OFFS 0xA0 +#define UND_SPSR_OFFS 0xA8 +#define UND_SP_OFFS 0xAC +#define SYS_SPSR_OFFS 0xB4 +#define SYS_SP_OFFS 0xB8 + +#ifndef __ASSEMBLER__ +#define SLEEP_DATA_FINGERPRINT 0xdeadbeef +struct sleep_data { + u32 fingerprint; + u32 wake_addr; + u32 link_addr; + u32 mmuctl; + u32 mmuauxctl; + u32 mmucpaccess; + u32 mmuttb; + u32 mmupid; + u32 mmudomain; + u32 svc_r6; + u32 svc_r7; + u32 svc_r8; + u32 svc_r9; + u32 svc_r10; + u32 svc_r11; + u32 svc_r12; + u32 svc_sp; + u32 svc_spsr; + u32 fiq_spsr; + u32 fiq_r8; + u32 fiq_r9; + u32 fiq_r10; + u32 fiq_r11; + u32 fiq_r12; + u32 fiq_sp; + u32 fiq_lr; + u32 abt_r8; + u32 abt_r9; + u32 abt_r10; + u32 abt_r11; + u32 abt_r12; + u32 abt_spsr; + u32 abt_sp; + u32 abt_lr; + u32 irq_r8; + u32 irq_r9; + u32 irq_r10; + u32 irq_r11; + u32 irq_r12; + u32 irq_spsr; + u32 irq_sp; + u32 irq_lr; + u32 und_spsr; + u32 und_sp; + u32 und_lr; + u32 sys_spsr; + u32 sys_sp; + u32 sys_lr; + u32 pinmux[0x100]; + u32 icoll_ctrl; + union { + u32 prio[0x10]; + u32 intr[0x80]; + } icoll; + u32 clks[16]; + u32 old_c00; + u32 old_c04; +}; + +extern int mx23_s2ram_alloc_sz; +void mx23_cpu_suspend(void); +extern int mx23_standby_alloc_sz; +void mx23_cpu_standby(void); +void mxs_nomatch_suspend_timer(void); +void mxs_nomatch_resume_timer(void); + +void *iram_alloc(unsigned int size, unsigned long *dma_addr); +void iram_free(unsigned long addr, unsigned int size); +#endif /* __ASSEMBLER__ */ +#endif /* __PM_H__ */ diff --git a/arch/arm/mach-mx23/usb.h b/arch/arm/mach-mx23/usb.h new file mode 100644 index 000000000000..689603d4e7d6 --- /dev/null +++ b/arch/arm/mach-mx23/usb.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_utmi_active(void); +extern void gpio_usbotg_utmi_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, + struct fsl_usb2_platform_data + *config); +extern void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata, + bool enable); +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbh2_active(void); +extern void gpio_usbh2_inactive(void); + +/* + * Determine which platform_data struct to use for the DR controller, + * based on which transceiver is configured. + * PDATA is a pointer to it. + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config; +#define PDATA (&dr_utmi_config) + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff --git a/arch/arm/mach-mx23/usb_dr.c b/arch/arm/mach-mx23/usb_dr.c new file mode 100644 index 000000000000..4c702ffcd07c --- /dev/null +++ b/arch/arm/mach-mx23/usb_dr.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "usb.h" +#include "mx23_pins.h" + +#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_GPMI_CE2N) +#define USB_ID_PIN MXS_PIN_TO_GPIO(PINID_ROTARYA) + +static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat) +{ + fsl_platform_set_usb_phy_dis(plat, 0); +} + +static int usbotg_init_ext(struct platform_device *pdev) +{ + struct clk *usb_clk; + + usb_clk = clk_get(NULL, "usb_clk0"); + clk_enable(usb_clk); + clk_put(usb_clk); + + return usbotg_init(pdev); +} + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init_ext, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .platform_resume = usb_host_phy_resume, + .transceiver = "utmi", + .phy_regs = USBPHY_PHYS_ADDR, + .id_gpio = USB_ID_PIN, +}; + +/* + * OTG resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)USBCTRL_PHYS_ADDR, + .end = (u32)(USBCTRL_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB_CTRL, + .flags = IORESOURCE_IRQ, + }, + + [2] = { + .start = IRQ_USB_WAKEUP, + .flags = IORESOURCE_IRQ, + }, +}; + +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)USBCTRL_PHYS_ADDR, + .end = (u32)(USBCTRL_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB_CTRL, + .flags = IORESOURCE_IRQ, + }, + + [2] = { + .start = IRQ_USB_WAKEUP, + .flags = IORESOURCE_IRQ, + }, +}; + + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), +}; + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{} + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + + +static int __init usb_dr_init(void) +{ + pr_debug("%s: \n", __func__); + + dr_register_otg(); + dr_register_host(otg_resources, ARRAY_SIZE(otg_resources)); + dr_register_udc(); + + PDATA->change_ahb_burst = 1; + PDATA->ahb_burst_mode = 0; + return 0; +} + +/* utmi_init will be call by otg, host and perperial tree time*/ +void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this) +{ +} + +void fsl_phy_usb_utmi_uninit(struct fsl_xcvr_ops *this) +{ +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +void fsl_phy_set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + int ret; + ret = gpio_request(USB_POWER_ENABLE, "usb_power"); + if (ret) { + pr_err("fail request usb power control pin\n"); + return; + } + gpio_direction_output(USB_POWER_ENABLE, on); + gpio_set_value(USB_POWER_ENABLE, on); + gpio_free(USB_POWER_ENABLE); +} + +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + fs_initcall(usb_dr_init); +#else + subsys_initcall(usb_dr_init); +#endif diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig index 54d217314ee9..95f966a5fb1a 100644 --- a/arch/arm/mach-mx25/Kconfig +++ b/arch/arm/mach-mx25/Kconfig @@ -5,4 +5,79 @@ comment "MX25 platforms:" config MACH_MX25_3DS bool "Support MX25PDK (3DS) Platform" +menu "MX25 Options" + +config MX25_OPTIONS + bool + default y + select CPU_ARM926T + select USB_ARCH_HAS_EHCI + +config MX25_DOZE_DURING_IDLE + bool "Enter Doze mode during idle" + help + Turning on this option will put the CPU into Doze mode during idle. + The default is to enter Wait mode during idle. Doze mode during + idle will save additional power over Wait mode. + +config MXC_SDMA_API + bool "Use SDMA API" + default y + help + This selects the Freescale MXC SDMA API. + If unsure, say N. + +config SDMA_IRAM + bool "Use Internal RAM for SDMA transfer" + depends on MXC_SDMA_API + help + Support Internal RAM as SDMA buffer or control structures + +config ARCH_MXC_HAS_NFC_V2 + bool "MXC NFC Hardware Version 2" + depends on ARCH_MX25 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 2 + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V2_1 + bool "MXC NFC Hardware Version 2.1" + depends on ARCH_MXC_HAS_NFC_V2 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 2.1 + If unsure, say N. + +menu "Device options" + +config I2C_MXC_SELECT1 + bool "Enable I2C1 module" + default y + depends on I2C_MXC + help + Enable MX25 I2C1 module. + +config I2C_MXC_SELECT2 + bool "Enable I2C2 module" + default n + depends on I2C_MXC + help + Enable MX25 I2C2 module. + +config I2C_MXC_SELECT3 + bool "Enable I2C3 module" + default n + depends on I2C_MXC + help + Enable MX25 I2C3 module. + +config FLEXCAN_MXC_SELECT1 + bool "Enable FlexCAN1 module" + depends on CAN_FLEXCAN + help + Enable MX25 FlexCAN1 module. + +endmenu +endmenu endif diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile index 10cebc5ced8c..93e835c10107 100644 --- a/arch/arm/mach-mx25/Makefile +++ b/arch/arm/mach-mx25/Makefile @@ -1,3 +1,13 @@ -obj-y := mm.o devices.o -obj-$(CONFIG_ARCH_MX25) += clock.o -obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o +obj-y := system.o iomux.o cpu.o mm.o clock.o bus_freq.o devices.o serial.o + +obj-$(CONFIG_MXC_SDMA_API) += dma.o +obj-$(CONFIG_SPI_MXC) += mx25_3stack_cpld.o +obj-$(CONFIG_MACH_MX25_3DS) += mx25_3stack.o mx25_3stack_gpio.o mx25_3stack_pmic_mc34704.o + +obj-$(CONFIG_USB_EHCI_ARC_H2) += usb_h2.o + +obj-$(CONFIG_PM) += pm.o + +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif diff --git a/arch/arm/mach-mx25/board-mx25_3stack.h b/arch/arm/mach-mx25/board-mx25_3stack.h new file mode 100644 index 000000000000..ec2f9e95ab7b --- /dev/null +++ b/arch/arm/mach-mx25/board-mx25_3stack.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX25_3STACK_H__ +#define __ASM_ARCH_MXC_BOARD_MX25_3STACK_H__ + +#ifdef CONFIG_MACH_MX25_3DS + +/*! + * @defgroup BRDCFG_MX25 Board Configuration Options + * @ingroup MSL_MX25 + */ + +/*! + * @file mach-mx25/board-mx25_3stack.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX25 3STACK Platform. + * + * @ingroup BRDCFG_MX25 + */ + +/* + * Include Files + */ +#include +#include + +/*! + * @name MXC UART board-level configurations + */ +/*! @{ */ +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR NO_IRDA +#define UART2_ENABLED 1 + +/* UART 3 configuration */ +#define UART3_MODE MODE_DTE +#define UART3_IR NO_IRDA +#define UART3_ENABLED 0 + +/* UART 4 configuration */ +#define UART4_MODE MODE_DTE +#define UART4_IR NO_IRDA +#define UART4_ENABLED 0 + +/* UART 5 configuration */ +#define UART5_MODE MODE_DTE +#define UART5_IR NO_IRDA +#define UART5_ENABLED 0 + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +/*! + * @name debug board parameters + */ +/*! @{ */ +/*! + * Base address of debug board + */ +#define DEBUG_BASE_ADDRESS 0x78000000 /* Use a dummy base address */ + +/* External ethernet LAN9217 base address */ +#define LAN9217_BASE_ADDR DEBUG_BASE_ADDRESS + +/* External UART */ +#define UARTA_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x08000) +#define UARTB_BASE_ADDR (DEBUG_BASE_ADDRESS + 0x10000) + +#define BOARD_IO_ADDR 0x20000 + +/* LED switchs */ +#define LED_SWITCH_REG (BOARD_IO_ADDR + 0x00) +/* buttons */ +#define SWITCH_BUTTON_REG (BOARD_IO_ADDR + 0x08) +/* status, interrupt */ +#define INTR_STATUS_REG (BOARD_IO_ADDR + 0x10) +#define INTR_RESET_REG (BOARD_IO_ADDR + 0x20) +/*CPLD configuration*/ +#define CONFIG1_REG (BOARD_IO_ADDR + 0x28) +#define CONFIG2_REG (BOARD_IO_ADDR + 0x30) +/*interrupt mask */ +#define INTR_MASK_REG (BOARD_IO_ADDR + 0x38) + +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG (BOARD_IO_ADDR + 0x40) +#define MAGIC_NUMBER2_REG (BOARD_IO_ADDR + 0x48) +/* CPLD code version */ +#define CPLD_CODE_VER_REG (BOARD_IO_ADDR + 0x50) +/* magic word for debug CPLD */ +#define MAGIC3_NUMBER3_REG (BOARD_IO_ADDR + 0x58) +/* module reset register*/ +#define CONTROL_REG (BOARD_IO_ADDR + 0x60) +/* CPU ID and Personality ID*/ +#define IDENT_REG (BOARD_IO_ADDR + 0x68) + +/* For interrupts like xuart, enet etc */ +#define EXPIO_PARENT_INT MX25_PIN_GPIO1_1 + +#define EXPIO_INT_ENET_INT (MXC_BOARD_IRQ_START + 0) +#define EXPIO_INT_XUARTA_INT (MXC_BOARD_IRQ_START + 1) +#define EXPIO_INT_XUARTB_INT (MXC_BOARD_IRQ_START + 2) + +/*! This is System IRQ used by LAN9217 for interrupt generation taken + * from platform.h + */ +#define LAN9217_IRQ EXPIO_INT_ENET_INT + +/*! This is base virtual address of debug board*/ +extern unsigned int mx25_3stack_board_io; + +#define MXC_BD_LED1 (1 << 0) +#define MXC_BD_LED2 (1 << 1) +#define MXC_BD_LED3 (1 << 2) +#define MXC_BD_LED4 (1 << 3) +#define MXC_BD_LED5 (1 << 4) +#define MXC_BD_LED6 (1 << 5) +#define MXC_BD_LED7 (1 << 6) +#define MXC_BD_LED8 (1 << 7) +#define MXC_BD_LED_ON(led) +#define MXC_BD_LED_OFF(led) + +#define MXC_DEFAULT_INTENSITY 127 +#define MXC_INTENSITY_OFF 0 + +/*! @} */ + +extern void mx25_3stack_gpio_init(void) __init; +extern int headphone_det_status(void); +extern void sgtl5000_enable_amp(void); +extern unsigned int sdhc_get_card_det_status(struct device *dev); +extern int sdhc_write_protect(struct device *dev); +extern void gpio_can_active(int id); +extern void gpio_can_inactive(int id); +extern struct flexcan_platform_data flexcan_data[]; +extern void mx2fb_set_brightness(uint8_t); +extern int __init mx25_3stack_init_mc34704(void); +extern void imx_adc_set_hsync(int on); + +#endif /* CONFIG_MACH_MX25_3DS */ +#endif /* __ASM_ARCH_MXC_BOARD_MX25_3STACK_H__ */ diff --git a/arch/arm/mach-mx25/bus_freq.c b/arch/arm/mach-mx25/bus_freq.c new file mode 100644 index 000000000000..9c98e9f77582 --- /dev/null +++ b/arch/arm/mach-mx25/bus_freq.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file bus_freq.c + * + * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module + * and DVFS CORE module. + * + * The APIs are for setting bus frequency to low or high. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include + +int low_bus_freq_mode; +int high_bus_freq_mode; +char *gp_reg_id = "REG3_CORE"; + +int set_low_bus_freq(void) +{ + return 0; +} + +int set_high_bus_freq(int high_bus_freq) +{ + return 0; +} + +int low_freq_bus_used(void) +{ + return 0; +} + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit busfreq_probe(struct platform_device *pdev) +{ + low_bus_freq_mode = 0; + high_bus_freq_mode = 0; + + return 0; +} + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "busfreq", + }, + .probe = busfreq_probe, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ + if (platform_driver_register(&busfreq_driver) != 0) { + printk(KERN_ERR "busfreq_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "Bus freq driver module loaded\n"); + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 155014993b13..d9723cc7cf47 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2009 by Sascha Hauer, Pengutronix + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -16,6 +17,8 @@ * MA 02110-1301, USA. */ +#include +#include #include #include #include @@ -28,6 +31,7 @@ #include #include #include +#include "crm_regs.h" #define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR) @@ -52,6 +56,1515 @@ #define CCM_LTR2 0x48 #define CCM_LTR3 0x4c +#define OSC24M_CLK_FREQ 24000000 /* 24M reference clk */ +#define OSC32K_CLK_FREQ 32768 /* 32.768k oscillator in */ + +#if defined CONFIG_CPU_FREQ_IMX +#define AHB_CLK_DEFAULT 133000000 +#define ARM_SRC_DEFAULT 532000000 +#endif + +static struct clk mpll_clk; +static struct clk upll_clk; +static struct clk ahb_clk; +static struct clk upll_24610k_clk; +int cpu_wp_nr; + +static int clk_cgcr_enable(struct clk *clk); +static void clk_cgcr_disable(struct clk *clk); +static unsigned long get_rate_ipg(struct clk *clk); + +static int _clk_upll_enable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(MXC_CCM_CCTL); + reg &= ~MXC_CCM_CCTL_UPLL_DISABLE; + __raw_writel(reg, MXC_CCM_CCTL); + + while ((__raw_readl(MXC_CCM_UPCTL) & MXC_CCM_UPCTL_LF) == 0) + ; + + return 0; +} + +static void _clk_upll_disable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(MXC_CCM_CCTL); + reg |= MXC_CCM_CCTL_UPLL_DISABLE; + __raw_writel(reg, MXC_CCM_CCTL); +} + +static int _perclk_enable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(MXC_CCM_CGCR0); + reg |= 1 << clk->id; + __raw_writel(reg, MXC_CCM_CGCR0); + + return 0; +} + +static void _perclk_disable(struct clk *clk) +{ + unsigned long reg; + + reg = __raw_readl(MXC_CCM_CGCR0); + reg &= ~(1 << clk->id); + __raw_writel(reg, MXC_CCM_CGCR0); +} + +static unsigned long _clk_osc24m_get_rate(struct clk *clk) +{ + return OSC24M_CLK_FREQ; +} + +static unsigned long _clk_osc32k_get_rate(struct clk *clk) +{ + return OSC32K_CLK_FREQ; +} + +static unsigned long _clk_pll_get_rate(struct clk *clk) +{ + unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; + unsigned long ref_clk; + unsigned long reg; + unsigned long long temp; + + ref_clk = clk_get_rate(clk->parent); + + if (clk == &mpll_clk) { + reg = __raw_readl(MXC_CCM_MPCTL); + pdf = (reg & MXC_CCM_MPCTL_PD_MASK) >> MXC_CCM_MPCTL_PD_OFFSET; + mfd = + (reg & MXC_CCM_MPCTL_MFD_MASK) >> MXC_CCM_MPCTL_MFD_OFFSET; + mfi = + (reg & MXC_CCM_MPCTL_MFI_MASK) >> MXC_CCM_MPCTL_MFI_OFFSET; + mfn = + (reg & MXC_CCM_MPCTL_MFN_MASK) >> MXC_CCM_MPCTL_MFN_OFFSET; + } else if (clk == &upll_clk) { + reg = __raw_readl(MXC_CCM_UPCTL); + pdf = (reg & MXC_CCM_UPCTL_PD_MASK) >> MXC_CCM_UPCTL_PD_OFFSET; + mfd = + (reg & MXC_CCM_UPCTL_MFD_MASK) >> MXC_CCM_UPCTL_MFD_OFFSET; + mfi = + (reg & MXC_CCM_UPCTL_MFI_MASK) >> MXC_CCM_UPCTL_MFI_OFFSET; + mfn = + (reg & MXC_CCM_UPCTL_MFN_MASK) >> MXC_CCM_UPCTL_MFN_OFFSET; + } else { + BUG(); /* oops */ + } + + mfi = (mfi <= 5) ? 5 : mfi; + temp = 2LL * ref_clk * mfn; + do_div(temp, mfd + 1); + temp = 2LL * ref_clk * mfi + temp; + do_div(temp, pdf + 1); + + return temp; +} + +static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate) +{ + int div = clk_get_rate(clk->parent) / rate; + + if (clk_get_rate(clk->parent) % rate) + div++; + + if (div > 4) + div = 4; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long div = 0x0, reg = 0x0; + unsigned long cctl = __raw_readl(MXC_CCM_CCTL); + +#if defined CONFIG_CPU_FREQ_IMX + struct cpu_wp *cpu_wp; + unsigned long ahb_clk_div = 0; + unsigned long arm_src = 0; + int i; + + cpu_wp = get_cpu_wp(&cpu_wp_nr); + for (i = 0; i < cpu_wp_nr; i++) { + if (cpu_wp[i].cpu_rate == rate) { + div = cpu_wp[i].cpu_podf; + ahb_clk_div = cpu_wp[i].cpu_rate / AHB_CLK_DEFAULT - 1; + arm_src = + (cpu_wp[i].pll_rate == ARM_SRC_DEFAULT) ? 0 : 1; + break; + } + } + if (i == cpu_wp_nr) + return -EINVAL; + reg = (cctl & ~MXC_CCM_CCTL_ARM_MASK) | + (div << MXC_CCM_CCTL_ARM_OFFSET); + reg = (reg & ~MXC_CCM_CCTL_AHB_MASK) | + (ahb_clk_div << MXC_CCM_CCTL_AHB_OFFSET); + reg = (reg & ~MXC_CCM_CCTL_ARM_SRC) | + (arm_src << MXC_CCM_CCTL_ARM_SRC_OFFSET); + __raw_writel(reg, MXC_CCM_CCTL); +#else + div = clk_get_rate(clk->parent) / rate; + + if (div > 4 || div < 1 || ((clk_get_rate(clk->parent) / div) != rate)) + return -EINVAL; + div--; + + reg = + (cctl & ~MXC_CCM_CCTL_ARM_MASK) | (div << MXC_CCM_CCTL_ARM_OFFSET); + __raw_writel(reg, MXC_CCM_CCTL); +#endif + + return 0; +} + +static unsigned long _clk_cpu_get_rate(struct clk *clk) +{ + unsigned long div; + unsigned long cctl = __raw_readl(MXC_CCM_CCTL); + unsigned long rate; + + div = (cctl & MXC_CCM_CCTL_ARM_MASK) >> MXC_CCM_CCTL_ARM_OFFSET; + + rate = clk_get_rate(clk->parent) / (div + 1); + + if (cctl & MXC_CCM_CCTL_ARM_SRC) { + rate *= 3; + rate /= 4; + } + + return rate; +} + +static unsigned long _clk_ahb_get_rate(struct clk *clk) +{ + unsigned long div; + unsigned long cctl = __raw_readl(MXC_CCM_CCTL); + + div = (cctl & MXC_CCM_CCTL_AHB_MASK) >> MXC_CCM_CCTL_AHB_OFFSET; + + return clk_get_rate(clk->parent) / (div + 1); +} + +static void *pcdr_a[4] = { + MXC_CCM_PCDR0, MXC_CCM_PCDR1, MXC_CCM_PCDR2, MXC_CCM_PCDR3 +}; +static unsigned long _clk_perclkx_get_rate(struct clk *clk) +{ + unsigned long perclk_pdf; + unsigned long pcdr; + + pcdr = __raw_readl(pcdr_a[clk->id >> 2]); + + perclk_pdf = + (pcdr >> ((clk->id & 3) << 3)) & MXC_CCM_PCDR1_PERDIV1_MASK; + + return clk_get_rate(clk->parent) / (perclk_pdf + 1); +} + +static unsigned long _clk_perclkx_round_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > 64) + div = 64; + + return parent_rate / div; +} + +static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long reg; + unsigned long div; + unsigned long parent_rate; + + if (clk->id < 0 || clk->id > 15) + return -EINVAL; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + if (div > 64 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + div--; + + reg = + __raw_readl(pcdr_a[clk->id >> 2]) & ~(MXC_CCM_PCDR1_PERDIV1_MASK << + ((clk->id & 3) << 3)); + reg |= div << ((clk->id & 3) << 3); + __raw_writel(reg, pcdr_a[clk->id >> 2]); + + return 0; +} + +static int _clk_perclkx_set_parent(struct clk *clk, struct clk *parent) +{ + unsigned long mcr; + + if (parent != &upll_clk && parent != &ahb_clk) + return -EINVAL; + + clk->parent = parent; + mcr = __raw_readl(MXC_CCM_MCR); + if (parent == &upll_clk) + mcr |= (1 << clk->id); + else + mcr &= ~(1 << clk->id); + + __raw_writel(mcr, MXC_CCM_MCR); + + return 0; +} + +static int _clk_perclkx_set_parent3(struct clk *clk, struct clk *parent) +{ + unsigned long mcr = __raw_readl(MXC_CCM_MCR); + int bit; + + if (parent != &upll_clk && parent != &ahb_clk && + parent != &upll_24610k_clk) + return -EINVAL; + + switch (clk->id) { + case 2: + bit = MXC_CCM_MCR_ESAI_CLK_MUX_OFFSET; + break; + case 13: + bit = MXC_CCM_MCR_SSI1_CLK_MUX_OFFSET; + break; + case 14: + bit = MXC_CCM_MCR_SSI2_CLK_MUX_OFFSET; + break; + default: + return -EINVAL; + } + + if (parent == &upll_24610k_clk) { + mcr |= 1 << bit; + __raw_writel(mcr, MXC_CCM_MCR); + clk->parent = parent; + } else { + mcr &= ~(1 << bit); + __raw_writel(mcr, MXC_CCM_MCR); + return _clk_perclkx_set_parent(clk, parent); + } + + return 0; +} + +static unsigned long _clk_ipg_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 2; /* Always AHB / 2 */ +} + +static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) +{ + return clk->parent->round_rate(clk->parent, rate); +} + +static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) +{ + return clk->parent->set_rate(clk->parent, rate); +} + +/* Top-level clocks */ + +static struct clk osc24m_clk = { + .get_rate = _clk_osc24m_get_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk osc32k_clk = { + .get_rate = _clk_osc32k_get_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk mpll_clk = { + .parent = &osc24m_clk, + .get_rate = _clk_pll_get_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk upll_clk = { + .parent = &osc24m_clk, + .get_rate = _clk_pll_get_rate, + .enable = _clk_upll_enable, + .disable = _clk_upll_disable, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_24610k_get_rate(struct clk *clk) +{ + long long temp = clk_get_rate(clk->parent) * 2461LL; + + do_div(temp, 24000); + + return temp; /* Always (UPLL * 24.61 / 240) */ +} + +static struct clk upll_24610k_clk = { + .parent = &upll_clk, + .get_rate = _clk_24610k_get_rate, + .flags = RATE_PROPAGATES, +}; + +/* Mid-level clocks */ + +static struct clk cpu_clk = { /* ARM clock */ + .parent = &mpll_clk, + .set_rate = _clk_cpu_set_rate, + .get_rate = _clk_cpu_get_rate, + .round_rate = _clk_cpu_round_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk ahb_clk = { /* a.k.a. HCLK */ + .parent = &cpu_clk, + .get_rate = _clk_ahb_get_rate, + .flags = RATE_PROPAGATES, +}; + +static struct clk ipg_clk = { + .parent = &ahb_clk, + .get_rate = _clk_ipg_get_rate, + .flags = RATE_PROPAGATES, +}; + + +/* Bottom-level clocks */ + +struct clk usb_ahb_clk = { + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_USBOTG_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk rtic_clk = { + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_RTIC_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk emi_clk = { + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_EMI_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk brom_clk = { + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_BROM_OFFSET, + .disable = clk_cgcr_disable, +}; + +static struct clk per_clk[] = { + /* per_csi_clk */ + { + .id = 0, + .parent = &upll_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_epit_clk */ + { + .id = 1, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_esai_clk */ + { + .id = 2, + .parent = &ahb_clk, /* can be AHB or UPLL or 24.61MHz */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent3, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_esdhc1_clk */ + { + .id = 3, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_esdhc2_clk */ + { + .id = 4, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_gpt_clk */ + { + .id = 5, + .parent = &ahb_clk, /* Must be AHB */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_i2c_clk */ + { + .id = 6, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_lcdc_clk */ + { + .id = 7, + .parent = &upll_clk, /* Must be UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_nfc_clk */ + { + .id = 8, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_owire_clk */ + { + .id = 9, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_pwm_clk */ + { + .id = 10, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_sim1_clk */ + { + .id = 11, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_sim2_clk */ + { + .id = 12, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_ssi1_clk */ + { + .id = 13, + .parent = &ahb_clk, /* can be AHB or UPLL or 24.61MHz */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent3, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_ssi2_clk */ + { + .id = 14, + .parent = &ahb_clk, /* can be AHB or UPLL or 24.61MHz */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent3, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES, + }, + /* per_uart_clk */ + { + .id = 15, + .parent = &ahb_clk, /* can be AHB or UPLL */ + .round_rate = _clk_perclkx_round_rate, + .set_rate = _clk_perclkx_set_rate, + .set_parent = _clk_perclkx_set_parent, + .get_rate = _clk_perclkx_get_rate, + .enable = _perclk_enable, + .disable = _perclk_disable, + .flags = RATE_PROPAGATES,}, +}; + +struct clk nfc_clk = { + .id = 0, + .parent = &per_clk[8], +}; + +struct clk audmux_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_AUDMUX_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk ata_clk[] = { + { + /* ata_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_ATA_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &ata_clk[1],}, + { + /* ata_ahb_clk */ + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_ATA_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk can_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_CAN1_OFFSET, + .disable = clk_cgcr_disable,}, + { + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_CAN2_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk csi_clk[] = { + { + /* csi_clk */ + .id = 0, + .parent = &per_clk[0], + .secondary = &csi_clk[1],}, + { + /* csi_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_CSI_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &csi_clk[2],}, + { + /* csi_ahb_clk */ + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_CSI_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk cspi_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_CSPI1_OFFSET, + .get_rate = get_rate_ipg, + .disable = clk_cgcr_disable,}, + { + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_CSPI2_OFFSET, + .get_rate = get_rate_ipg, + .disable = clk_cgcr_disable,}, + { + .id = 2, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_CSPI3_OFFSET, + .get_rate = get_rate_ipg, + .disable = clk_cgcr_disable,}, +}; + +struct clk dryice_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_DRYICE_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk ect_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_ECT_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk epit1_clk[] = { + { + /* epit_clk */ + .id = 0, + .parent = &per_clk[1], + .secondary = &epit1_clk[1],}, + { + /* epit_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_EPIT1_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk epit2_clk[] = { + { + /* epit_clk */ + .id = 1, + .parent = &per_clk[1], + .secondary = &epit2_clk[1],}, + { + /* epit_ipg_clk */ + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_EPIT2_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk esai_clk[] = { + { + /* esai_clk */ + .id = 0, + .parent = &per_clk[2], + .secondary = &esai_clk[1],}, + { + /* esai_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_ESAI_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &esai_clk[2],}, + { + /* esai_ahb_clk */ + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_ESAI_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk esdhc1_clk[] = { + { + /* esdhc_clk */ + .id = 0, + .parent = &per_clk[3], + .secondary = &esdhc1_clk[1],}, + { + /* esdhc_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_ESDHC1_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &esdhc1_clk[2],}, + { + /* esdhc_ahb_clk */ + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_ESDHC1_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk esdhc2_clk[] = { + { + /* esdhc_clk */ + .id = 1, + .parent = &per_clk[4], + .secondary = &esdhc2_clk[1],}, + { + /* esdhc_ipg_clk */ + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_ESDHC2_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &esdhc2_clk[2],}, + { + /* esdhc_ahb_clk */ + .id = 1, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_ESDHC2_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk fec_clk[] = { + { + /* fec_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_FEC_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &fec_clk[1],}, + { + /* fec_ahb_clk */ + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_FEC_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk gpio_clk[] = { + { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_GPIO1_OFFSET, + .disable = clk_cgcr_disable,}, + { + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_GPIO2_OFFSET, + .disable = clk_cgcr_disable,}, + { + .id = 2, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_GPIO3_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +static struct clk gpt1_clk[] = { + { + /* gpt_clk */ + .id = 0, + .parent = &per_clk[5], + .secondary = &gpt1_clk[1],}, + { + /* gpt_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_GPT1_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +static struct clk gpt2_clk[] = { + { + /* gpt_clk */ + .id = 1, + .parent = &per_clk[5], + .secondary = &gpt1_clk[1],}, + { + /* gpt_ipg_clk */ + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_GPT2_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +static struct clk gpt3_clk[] = { + { + /* gpt_clk */ + .id = 2, + .parent = &per_clk[5], + .secondary = &gpt1_clk[1],}, + { + /* gpt_ipg_clk */ + .id = 2, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_GPT3_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +static struct clk gpt4_clk[] = { + { + /* gpt_clk */ + .id = 3, + .parent = &per_clk[5], + .secondary = &gpt1_clk[1],}, + { + /* gpt_ipg_clk */ + .id = 3, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_GPT4_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk i2c_clk[] = { + { + .id = 0, + .parent = &per_clk[6],}, + { + .id = 1, + .parent = &per_clk[6],}, + { + .id = 2, + .parent = &per_clk[6],}, +}; + +struct clk iim_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_IIM_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk iomuxc_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_IOMUXC_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk kpp_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_KPP_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk lcdc_clk[] = { + { + /* lcdc_clk */ + .id = 0, + .parent = &per_clk[7], + .secondary = &lcdc_clk[1], + .round_rate = _clk_parent_round_rate, + .set_rate = _clk_parent_set_rate,}, + { + /* lcdc_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_LCDC_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &lcdc_clk[2],}, + { + /* lcdc_ahb_clk */ + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_LCDC_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk owire_clk[] = { + { + /* owire_clk */ + .id = 0, + .parent = &per_clk[9], + .secondary = &owire_clk[1],}, + { + /* owire_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_OWIRE_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk pwm1_clk[] = { + { + /* pwm_clk */ + .id = 0, + .parent = &per_clk[10], + .secondary = &pwm1_clk[1],}, + { + /* pwm_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR1, + .enable_shift = MXC_CCM_CGCR1_PWM1_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk pwm2_clk[] = { + { + /* pwm_clk */ + .id = 1, + .parent = &per_clk[10], + .secondary = &pwm2_clk[1],}, + { + /* pwm_ipg_clk */ + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_PWM2_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk pwm3_clk[] = { + { + /* pwm_clk */ + .id = 2, + .parent = &per_clk[10], + .secondary = &pwm3_clk[1],}, + { + /* pwm_ipg_clk */ + .id = 2, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_PWM3_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk pwm4_clk[] = { + { + /* pwm_clk */ + .id = 3, + .parent = &per_clk[10], + .secondary = &pwm4_clk[1],}, + { + /* pwm_ipg_clk */ + .id = 3, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_PWM3_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk rng_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_RNGB_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk scc_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_SCC_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk sdma_clk[] = { + { + /* sdma_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_SDMA_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &sdma_clk[1],}, + { + /* sdma_ahb_clk */ + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_SDMA_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk sim1_clk[] = { + { + /* sim1_clk */ + .id = 0, + .parent = &per_clk[11], + .secondary = &sim1_clk[1],}, + { + /* sim_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_SIM1_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk sim2_clk[] = { + { + /* sim2_clk */ + .id = 1, + .parent = &per_clk[12], + .secondary = &sim2_clk[1],}, + { + /* sim_ipg_clk */ + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_SIM2_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk slcdc_clk[] = { + { + /* slcdc_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_SLCDC_OFFSET, + .disable = clk_cgcr_disable, + .secondary = &slcdc_clk[1],}, + { + /* slcdc_ahb_clk */ + .id = 0, + .parent = &ahb_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR0, + .enable_shift = MXC_CCM_CGCR0_HCLK_SLCDC_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk spba_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_SPBA_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk ssi1_clk[] = { + { + /* ssi_clk */ + .id = 0, + .parent = &per_clk[13], + .secondary = &ssi1_clk[1],}, + { + /* ssi_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_SSI1_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk ssi2_clk[] = { + { + /* ssi_clk */ + .id = 1, + .parent = &per_clk[14], + .secondary = &ssi2_clk[1],}, + { + /* ssi_ipg_clk */ + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_SSI2_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk tsc_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_TCHSCRN_OFFSET, + .disable = clk_cgcr_disable, +}; + +struct clk uart1_clk[] = { + { + /* uart_clk */ + .id = 0, + .parent = &per_clk[15], + .secondary = &uart1_clk[1],}, + { + /* uart_ipg_clk */ + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_UART1_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk uart2_clk[] = { + { + /* uart_clk */ + .id = 1, + .parent = &per_clk[15], + .secondary = &uart2_clk[1],}, + { + /* uart_ipg_clk */ + .id = 1, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_UART2_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk uart3_clk[] = { + { + /* uart_clk */ + .id = 2, + .parent = &per_clk[15], + .secondary = &uart3_clk[1],}, + { + /* uart_ipg_clk */ + .id = 2, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_UART3_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk uart4_clk[] = { + { + /* uart_clk */ + .id = 3, + .parent = &per_clk[15], + .secondary = &uart4_clk[1],}, + { + /* uart_ipg_clk */ + .id = 3, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_UART4_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk uart5_clk[] = { + { + /* uart_clk */ + .id = 4, + .parent = &per_clk[15], + .secondary = &uart5_clk[1],}, + { + /* uart_ipg_clk */ + .id = 4, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_UART5_OFFSET, + .disable = clk_cgcr_disable,}, +}; + +struct clk wdog_clk = { + .id = 0, + .parent = &ipg_clk, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_CGCR2, + .enable_shift = MXC_CCM_CGCR2_WDOG_OFFSET, + .disable = clk_cgcr_disable, +}; + +static unsigned long _clk_usb_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > 64) + return -EINVAL; + + return parent_rate / div; +} + +static int _clk_usb_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long reg; + unsigned long div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if (parent_rate / div != rate) + return -EINVAL; + if (div > 64) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCTL) & ~MXC_CCM_CCTL_USB_DIV_MASK; + reg |= (div - 1) << MXC_CCM_CCTL_USB_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CCTL); + + return 0; +} + +static unsigned long _clk_usb_get_rate(struct clk *clk) +{ + unsigned long div = + __raw_readl(MXC_CCM_CCTL) & MXC_CCM_CCTL_USB_DIV_MASK; + + div >>= MXC_CCM_CCTL_USB_DIV_OFFSET; + + return clk_get_rate(clk->parent) / (div + 1); +} + +static int _clk_usb_set_parent(struct clk *clk, struct clk *parent) +{ + unsigned long mcr; + + if (parent != &upll_clk && parent != &ahb_clk) + return -EINVAL; + + clk->parent = parent; + mcr = __raw_readl(MXC_CCM_MCR); + if (parent == &ahb_clk) + mcr |= (1 << MXC_CCM_MCR_USB_CLK_MUX_OFFSET); + else + mcr &= ~(1 << MXC_CCM_MCR_USB_CLK_MUX_OFFSET); + + __raw_writel(mcr, MXC_CCM_MCR); + + return 0; +} + +static struct clk usb_clk = { + .parent = &upll_clk, + .get_rate = _clk_usb_get_rate, + .set_rate = _clk_usb_set_rate, + .round_rate = _clk_usb_round_rate, + .set_parent = _clk_usb_set_parent, +}; + +/* CLKO */ + +static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div > 64) + return -EINVAL; + + return parent_rate / div; +} + +static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long reg; + unsigned long div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + if (div > 64) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_MCR) & ~MXC_CCM_MCR_CLKO_DIV_MASK; + reg |= (div - 1) << MXC_CCM_MCR_CLKO_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_MCR); + + return 0; +} + +static unsigned long _clk_clko_get_rate(struct clk *clk) +{ + unsigned long div = + __raw_readl(MXC_CCM_MCR) & MXC_CCM_MCR_CLKO_DIV_MASK; + + div >>= MXC_CCM_MCR_CLKO_DIV_OFFSET; + + return clk_get_rate(clk->parent) / (div + 1); +} + +static struct clk *clko_sources[] = { + &osc32k_clk, /* 0x0 */ + &osc24m_clk, /* 0x1 */ + &cpu_clk, /* 0x2 */ + &ahb_clk, /* 0x3 */ + &ipg_clk, /* 0x4 */ + NULL, /* 0x5 */ + NULL, /* 0x6 */ + NULL, /* 0x7 */ + NULL, /* 0x8 */ + NULL, /* 0x9 */ + &per_clk[0], /* 0xA */ + &per_clk[2], /* 0xB */ + &per_clk[13], /* 0xC */ + &per_clk[14], /* 0xD */ + &usb_clk, /* 0xE */ + NULL, /* 0xF */ +}; + +#define NR_CLKO_SOURCES (sizeof(clko_sources) / sizeof(struct clk *)) + +static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) +{ + unsigned long reg = + __raw_readl(MXC_CCM_MCR) & ~MXC_CCM_MCR_CLKO_SEL_MASK; + struct clk **src; + int i; + + for (i = 0, src = clko_sources; i < NR_CLKO_SOURCES; i++, src++) + if (*src == parent) + break; + + if (i == NR_CLKO_SOURCES) + return -EINVAL; + + clk->parent = parent; + + reg |= i << MXC_CCM_MCR_CLKO_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_MCR); + + return 0; +} + +static struct clk clko_clk = { + .get_rate = _clk_clko_get_rate, + .set_rate = _clk_clko_set_rate, + .round_rate = _clk_clko_round_rate, + .set_parent = _clk_clko_set_parent, + .enable = clk_cgcr_enable, + .enable_reg = MXC_CCM_MCR, + .enable_shift = MXC_CCM_MCR_CLKO_EN_OFFSET, + .disable = clk_cgcr_disable, +}; + static unsigned long get_rate_mpll(void) { ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL); @@ -59,12 +1572,14 @@ static unsigned long get_rate_mpll(void) return mxc_decode_pll(mpctl, 24000000); } +# if 0 static unsigned long get_rate_upll(void) { ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL); return mxc_decode_pll(mpctl, 24000000); } +#endif unsigned long get_rate_arm(struct clk *clk) { @@ -89,6 +1604,7 @@ static unsigned long get_rate_ipg(struct clk *clk) return get_rate_ahb(NULL) >> 1; } +#if 0 static unsigned long get_rate_per(int per) { unsigned long ofs = (per & 0x3) * 8; @@ -133,6 +1649,7 @@ static unsigned long get_rate_otg(struct clk *clk) { return 48000000; /* FIXME */ } +#endif static int clk_cgcr_enable(struct clk *clk) { @@ -154,6 +1671,7 @@ static void clk_cgcr_disable(struct clk *clk) __raw_writel(reg, clk->enable_reg); } +#if 0 #define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \ static struct clk name = { \ .id = i, \ @@ -191,6 +1709,7 @@ DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); +#endif #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -200,6 +1719,7 @@ DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); }, static struct clk_lookup lookups[] = { +#if 0 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) @@ -225,24 +1745,174 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) +#endif + _REGISTER_CLOCK(NULL, "osc24m_clk", osc24m_clk) + _REGISTER_CLOCK(NULL, "osc32k_clk", osc32k_clk) + _REGISTER_CLOCK(NULL, "mpll_clk", mpll_clk) + _REGISTER_CLOCK(NULL, "upll_clk", upll_clk) + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) + _REGISTER_CLOCK(NULL, "ahb_clk", ahb_clk) + _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk) + _REGISTER_CLOCK(NULL, "usb_ahb_clk", usb_ahb_clk) + _REGISTER_CLOCK("mxcintuart.0", NULL, uart1_clk[0]) + _REGISTER_CLOCK("mxcintuart.1", NULL, uart2_clk[0]) + _REGISTER_CLOCK("mxcintuart.2", NULL, uart3_clk[0]) + _REGISTER_CLOCK("mxcintuart.3", NULL, uart4_clk[0]) + _REGISTER_CLOCK("mxcintuart.4", NULL, uart5_clk[0]) + _REGISTER_CLOCK(NULL, "usb_ahb_clk", usb_ahb_clk) + _REGISTER_CLOCK(NULL, "usb_clk", usb_clk) + _REGISTER_CLOCK("mxc_nandv2_flash.0", NULL, nfc_clk) + _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0]) + _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1]) + _REGISTER_CLOCK("spi_imx.2", NULL, cspi_clk[2]) + _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk[0]) + _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk[0]) + _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk[0]) + _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk[0]) + _REGISTER_CLOCK("mxc_keypad.0", NULL, kpp_clk) + _REGISTER_CLOCK("imx_adc.0", NULL, tsc_clk) + _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk[0]) + _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]) + _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]) + _REGISTER_CLOCK("fec.0", NULL, fec_clk[0]) + _REGISTER_CLOCK(NULL, "dryice_clk", dryice_clk) + _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0]) + _REGISTER_CLOCK("mxc_sdma.0", "sdma_ipg_clk", sdma_clk[0]) + _REGISTER_CLOCK("mxc_sdma.0", "sdma_ahb_clk", sdma_clk[1]) + _REGISTER_CLOCK("mxsdhci.0", NULL, esdhc1_clk[0]) + _REGISTER_CLOCK("mxsdhci.1", NULL, esdhc2_clk[0]) + _REGISTER_CLOCK(NULL, "gpt", gpt1_clk[0]) + _REGISTER_CLOCK(NULL, "gpt", gpt2_clk[0]) + _REGISTER_CLOCK(NULL, "gpt", gpt3_clk[0]) + _REGISTER_CLOCK(NULL, "gpt", gpt4_clk[0]) + _REGISTER_CLOCK(NULL, "clko_clk", clko_clk) + _REGISTER_CLOCK("pata_fsl", NULL, ata_clk[0]) + _REGISTER_CLOCK("FlexCAN.0", NULL, can_clk[0]) + _REGISTER_CLOCK("mxc_esai.0", NULL, esai_clk[0]) + _REGISTER_CLOCK("mxc_iim.0", NULL, iim_clk) + _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk[0]) + _REGISTER_CLOCK(NULL, "scc_clk", scc_clk) + _REGISTER_CLOCK("mxc_sim.0", NULL, sim1_clk[0]) + _REGISTER_CLOCK("mxc_sim.0", NULL, sim2_clk[0]) + _REGISTER_CLOCK("mxc_ssi.0", NULL, ssi1_clk[0]) + _REGISTER_CLOCK("mxc_ssi.0", NULL, ssi2_clk[0]) + _REGISTER_CLOCK("mxc_ipu", "csi_clk", csi_clk[0]) + _REGISTER_CLOCK(NULL, "lcdc_clk", lcdc_clk[0]) + _REGISTER_CLOCK(NULL, "slcdc_clk", lcdc_clk[0]) + _REGISTER_CLOCK(NULL, "rng_clk", rng_clk) + _REGISTER_CLOCK(NULL, "audmux_clk", audmux_clk) + _REGISTER_CLOCK(NULL, "ect_clk", ect_clk) + _REGISTER_CLOCK(NULL, "epit1_clk", epit1_clk[0]) + _REGISTER_CLOCK(NULL, "epit2_clk", epit2_clk[0]) + _REGISTER_CLOCK(NULL, "gpio_clk", gpio_clk[0]) + _REGISTER_CLOCK(NULL, "iomuxc_clk", iomuxc_clk) + _REGISTER_CLOCK(NULL, "spba_clk", spba_clk) + _REGISTER_CLOCK(NULL, "wdog_clk", wdog_clk) + _REGISTER_CLOCK(NULL, "per_csi_clk", per_clk[0]) + _REGISTER_CLOCK(NULL, "per_epit_clk", per_clk[1]) + _REGISTER_CLOCK(NULL, "per_esai_clk", per_clk[2]) + _REGISTER_CLOCK(NULL, "per_esdhc1_clk", per_clk[3]) + _REGISTER_CLOCK(NULL, "per_esdhc2_clk", per_clk[4]) + _REGISTER_CLOCK(NULL, "per_gpt_clk", per_clk[5]) + _REGISTER_CLOCK(NULL, "per_i2c_clk", per_clk[6]) + _REGISTER_CLOCK(NULL, "per_lcdc_clk", per_clk[7]) + _REGISTER_CLOCK(NULL, "per_nfc_clk", per_clk[8]) + _REGISTER_CLOCK(NULL, "per_owire_clk", per_clk[9]) + _REGISTER_CLOCK(NULL, "per_pwm_clk", per_clk[10]) + _REGISTER_CLOCK(NULL, "per_sim1_clk", per_clk[11]) + _REGISTER_CLOCK(NULL, "per_sim2_clk", per_clk[12]) + _REGISTER_CLOCK(NULL, "per_ssi1_clk", per_clk[13]) + _REGISTER_CLOCK(NULL, "per_ssi2_clk", per_clk[14]) + _REGISTER_CLOCK(NULL, "per_uart_clk", per_clk[15]) }; +static struct mxc_clk mxc_clks[ARRAY_SIZE(lookups)]; + +/*! + * Function to get timer clock rate early in boot process before clock tree is + * initialized. + * + * @return Clock rate for timer + */ +unsigned long __init clk_early_get_timer_rate(void) +{ + upll_clk.get_rate(&upll_clk); + per_clk[5].get_rate(&per_clk[5]); + per_clk[5].enable(&per_clk[5]); + + return clk_get_rate(&per_clk[5]); +} + int __init mx25_clocks_init(void) { + int i; + unsigned long upll_rate; + unsigned long ahb_rate; + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + clkdev_add(&lookups[i]); + mxc_clks[i].reg_clk = lookups[i].clk; + if (lookups[i].con_id != NULL) + strcpy(mxc_clks[i].name, lookups[i].con_id); + else + strcpy(mxc_clks[i].name, lookups[i].dev_id); + clk_register(&mxc_clks[i]); + } + /* Turn off all clocks except the ones we need to survive, namely: * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM, * SCC */ __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0); - __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); + + __raw_writel((1 << MXC_CCM_CGCR1_GPT1_OFFSET) | + (1 << MXC_CCM_CGCR1_IIM_OFFSET), + CRM_BASE + CCM_CGCR1); + __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); /* Clock source for lcdc is upll */ __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); - mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); + /* Init all perclk sources to ahb clock*/ + for (i = 0; i < (sizeof(per_clk) / sizeof(struct clk)); i++) + per_clk[i].set_parent(&per_clk[i], &ahb_clk); + + /* GPT clock must be derived from AHB clock */ + ahb_rate = clk_get_rate(&ahb_clk); + clk_set_rate(&per_clk[5], ahb_rate / 10); + + /* LCDC clock must be derived from UPLL clock */ + upll_rate = clk_get_rate(&upll_clk); + clk_set_parent(&per_clk[7], &upll_clk); + clk_set_rate(&per_clk[7], upll_rate); + + /* the NFC clock must be derived from AHB clock */ + clk_set_parent(&per_clk[8], &ahb_clk); + clk_set_rate(&per_clk[8], ahb_rate / 6); + + /* sim clock */ + clk_set_rate(&per_clk[11], ahb_rate / 2); + + /* the csi clock must be derived from UPLL clock */ + clk_set_parent(&per_clk[0], &upll_clk); + clk_set_rate(&per_clk[0], upll_rate / 5); + + pr_info("Clock input source is %ld\n", clk_get_rate(&osc24m_clk)); + + clk_enable(&emi_clk); + clk_enable(&gpio_clk[0]); + clk_enable(&gpio_clk[1]); + clk_enable(&gpio_clk[2]); + clk_enable(&iim_clk); + clk_enable(&gpt1_clk[0]); + clk_enable(&iomuxc_clk); + clk_enable(&scc_clk); + + mxc_timer_init(&gpt1_clk[0], IO_ADDRESS(MX25_GPT1_BASE_ADDR), + MX25_INT_GPT1); return 0; } diff --git a/arch/arm/mach-mx25/cpu.c b/arch/arm/mach-mx25/cpu.c new file mode 100644 index 000000000000..f64dfbf6cf03 --- /dev/null +++ b/arch/arm/mach-mx25/cpu.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mach-mx25/cpu.c + * + * @brief This file contains the CPU initialization code. + * + * @ingroup MSL_MX25 + */ + +#include +#include +#include +#include +#include +#include + +/*! + * CPU initialization. It is called by fixup_mxc_board() + */ +void __init mxc_cpu_init(void) +{ + if (!system_rev) + mxc_set_system_rev(0x25, CHIP_REV_1_0); +} + +static int __init post_cpu_init(void) +{ + void __iomem *base; + unsigned int reg; + + iram_init(MX25_IRAM_BASE_ADDR, IRAM_SIZE); + + base = IO_ADDRESS(MX25_AIPS1_BASE_ADDR); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + base = IO_ADDRESS(MX25_AIPS2_BASE_ADDR); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + return 0; +} +postcore_initcall(post_cpu_init); diff --git a/arch/arm/mach-mx25/crm_regs.h b/arch/arm/mach-mx25/crm_regs.h new file mode 100644 index 000000000000..b9368dd227a9 --- /dev/null +++ b/arch/arm/mach-mx25/crm_regs.h @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX25_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX25_CRM_REGS_H__ + +#include + +#define MXC_CCM_BASE ((char *)IO_ADDRESS(MX25_CRM_BASE_ADDR)) + +/* Register offsets */ +#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x00) +#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CCTL (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CGCR0 (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_CGCR1 (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CGCR2 (MXC_CCM_BASE + 0x14) +#define MXC_CCM_PCDR0 (MXC_CCM_BASE + 0x18) +#define MXC_CCM_PCDR1 (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_PCDR2 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_PCDR3 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x28) +#define MXC_CCM_CRDR (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x30) +#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x34) +#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x3C) +#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x44) +#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x48) +#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x50) +#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x54) +#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x58) +#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_PMCR2 (MXC_CCM_BASE + 0x60) +#define MXC_CCM_MCR (MXC_CCM_BASE + 0x64) +#define MXC_CCM_LPIMR0 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_LPIMR1 (MXC_CCM_BASE + 0x6C) + +#define MXC_CCM_MPCTL_BRMO (1 << 31) +#define MXC_CCM_MPCTL_PD_OFFSET 26 +#define MXC_CCM_MPCTL_PD_MASK (0xf << 26) +#define MXC_CCM_MPCTL_MFD_OFFSET 16 +#define MXC_CCM_MPCTL_MFD_MASK (0x3ff << 16) +#define MXC_CCM_MPCTL_MFI_OFFSET 10 +#define MXC_CCM_MPCTL_MFI_MASK (0xf << 10) +#define MXC_CCM_MPCTL_MFN_OFFSET 0 +#define MXC_CCM_MPCTL_MFN_MASK 0x3ff +#define MXC_CCM_MPCTL_LF (1 << 15) + +#define MXC_CCM_UPCTL_BRMO (1 << 31) +#define MXC_CCM_UPCTL_PD_OFFSET 26 +#define MXC_CCM_UPCTL_PD_MASK (0xf << 26) +#define MXC_CCM_UPCTL_MFD_OFFSET 16 +#define MXC_CCM_UPCTL_MFD_MASK (0x3ff << 16) +#define MXC_CCM_UPCTL_MFI_OFFSET 10 +#define MXC_CCM_UPCTL_MFI_MASK (0xf << 10) +#define MXC_CCM_UPCTL_MFN_OFFSET 0 +#define MXC_CCM_UPCTL_MFN_MASK 0x3ff +#define MXC_CCM_UPCTL_LF (1 << 15) + +#define MXC_CCM_CCTL_ARM_OFFSET 30 +#define MXC_CCM_CCTL_ARM_MASK (0x3 << 30) +#define MXC_CCM_CCTL_AHB_OFFSET 28 +#define MXC_CCM_CCTL_AHB_MASK (0x3 << 28) +#define MXC_CCM_CCTL_MPLL_RST (1 << 27) +#define MXC_CCM_CCTL_UPLL_RST (1 << 26) +#define MXC_CCM_CCTL_LP_CTL_OFFSET 24 +#define MXC_CCM_CCTL_LP_CTL_MASK (0x3 << 24) +#define MXC_CCM_CCTL_LP_MODE_RUN (0x0 << 24) +#define MXC_CCM_CCTL_LP_MODE_WAIT (0x1 << 24) +#define MXC_CCM_CCTL_LP_MODE_DOZE (0x2 << 24) +#define MXC_CCM_CCTL_LP_MODE_STOP (0x3 << 24) +#define MXC_CCM_CCTL_UPLL_DISABLE (1 << 23) +#define MXC_CCM_CCTL_MPLL_BYPASS (1 << 22) +#define MXC_CCM_CCTL_USB_DIV_OFFSET 16 +#define MXC_CCM_CCTL_USB_DIV_MASK (0x3 << 16) +#define MXC_CCM_CCTL_CG_CTRL (1 << 15) +#define MXC_CCM_CCTL_ARM_SRC (1 << 14) +#define MXC_CCM_CCTL_ARM_SRC_OFFSET 14 + +#define MXC_CCM_CGCR0_HCLK_ATA_OFFSET 16 +#define MXC_CCM_CGCR0_HCLK_BROM_OFFSET 17 +#define MXC_CCM_CGCR0_HCLK_CSI_OFFSET 18 +#define MXC_CCM_CGCR0_HCLK_EMI_OFFSET 19 +#define MXC_CCM_CGCR0_HCLK_ESAI_OFFSET 20 +#define MXC_CCM_CGCR0_HCLK_ESDHC1_OFFSET 21 +#define MXC_CCM_CGCR0_HCLK_ESDHC2_OFFSET 22 +#define MXC_CCM_CGCR0_HCLK_FEC_OFFSET 23 +#define MXC_CCM_CGCR0_HCLK_LCDC_OFFSET 24 +#define MXC_CCM_CGCR0_HCLK_RTIC_OFFSET 25 +#define MXC_CCM_CGCR0_HCLK_SDMA_OFFSET 26 +#define MXC_CCM_CGCR0_HCLK_SLCDC_OFFSET 27 +#define MXC_CCM_CGCR0_HCLK_USBOTG_OFFSET 28 + +#define MXC_CCM_CGCR0_PER_CSI_OFFSET 0 +#define MXC_CCM_CGCR0_PER_EPIT_OFFSET 1 +#define MXC_CCM_CGCR0_PER_ESAI_OFFSET 2 +#define MXC_CCM_CGCR0_PER_ESDHC1_OFFSET 3 +#define MXC_CCM_CGCR0_PER_ESDHC2_OFFSET 4 +#define MXC_CCM_CGCR0_PER_GPT_OFFSET 5 +#define MXC_CCM_CGCR0_PER_I2C_OFFSET 6 +#define MXC_CCM_CGCR0_PER_LCDC_OFFSET 7 +#define MXC_CCM_CGCR0_PER_NFC_OFFSET 8 +#define MXC_CCM_CGCR0_PER_OWIRE_OFFSET 9 +#define MXC_CCM_CGCR0_PER_PWM_OFFSET 10 +#define MXC_CCM_CGCR0_PER_SIM1_OFFSET 11 +#define MXC_CCM_CGCR0_PER_SIM2_OFFSET 12 +#define MXC_CCM_CGCR0_PER_SSI1_OFFSET 13 +#define MXC_CCM_CGCR0_PER_SSI2_OFFSET 14 +#define MXC_CCM_CGCR0_PER_UART_OFFSET 15 + +#define MXC_CCM_CGCR1_AUDMUX_OFFSET 0 +#define MXC_CCM_CGCR1_ATA_OFFSET 1 +#define MXC_CCM_CGCR1_CAN1_OFFSET 2 +#define MXC_CCM_CGCR1_CAN2_OFFSET 3 +#define MXC_CCM_CGCR1_CSI_OFFSET 4 +#define MXC_CCM_CGCR1_CSPI1_OFFSET 5 +#define MXC_CCM_CGCR1_CSPI2_OFFSET 6 +#define MXC_CCM_CGCR1_CSPI3_OFFSET 7 +#define MXC_CCM_CGCR1_DRYICE_OFFSET 8 +#define MXC_CCM_CGCR1_ECT_OFFSET 9 +#define MXC_CCM_CGCR1_EPIT1_OFFSET 10 +#define MXC_CCM_CGCR1_EPIT2_OFFSET 11 +#define MXC_CCM_CGCR1_ESAI_OFFSET 12 +#define MXC_CCM_CGCR1_ESDHC1_OFFSET 13 +#define MXC_CCM_CGCR1_ESDHC2_OFFSET 14 +#define MXC_CCM_CGCR1_FEC_OFFSET 15 +#define MXC_CCM_CGCR1_GPIO1_OFFSET 16 +#define MXC_CCM_CGCR1_GPIO2_OFFSET 17 +#define MXC_CCM_CGCR1_GPIO3_OFFSET 18 +#define MXC_CCM_CGCR1_GPT1_OFFSET 19 +#define MXC_CCM_CGCR1_GPT2_OFFSET 20 +#define MXC_CCM_CGCR1_GPT3_OFFSET 21 +#define MXC_CCM_CGCR1_GPT4_OFFSET 22 +#define MXC_CCM_CGCR1_I2C1_OFFSET 23 +#define MXC_CCM_CGCR1_I2C2_OFFSET 24 +#define MXC_CCM_CGCR1_I2C3_OFFSET 25 +#define MXC_CCM_CGCR1_IIM_OFFSET 26 +#define MXC_CCM_CGCR1_IOMUXC_OFFSET 27 +#define MXC_CCM_CGCR1_KPP_OFFSET 28 +#define MXC_CCM_CGCR1_LCDC_OFFSET 29 +#define MXC_CCM_CGCR1_OWIRE_OFFSET 30 +#define MXC_CCM_CGCR1_PWM1_OFFSET 31 + +#define MXC_CCM_CGCR2_PWM2_OFFSET (32-32) +#define MXC_CCM_CGCR2_PWM3_OFFSET (33-32) +#define MXC_CCM_CGCR2_PWM4_OFFSET (34-32) +#define MXC_CCM_CGCR2_RNGB_OFFSET (35-32) +#define MXC_CCM_CGCR2_RTIC_OFFSET (36-32) +#define MXC_CCM_CGCR2_SCC_OFFSET (37-32) +#define MXC_CCM_CGCR2_SDMA_OFFSET (38-32) +#define MXC_CCM_CGCR2_SIM1_OFFSET (39-32) +#define MXC_CCM_CGCR2_SIM2_OFFSET (40-32) +#define MXC_CCM_CGCR2_SLCDC_OFFSET (41-32) +#define MXC_CCM_CGCR2_SPBA_OFFSET (42-32) +#define MXC_CCM_CGCR2_SSI1_OFFSET (43-32) +#define MXC_CCM_CGCR2_SSI2_OFFSET (44-32) +#define MXC_CCM_CGCR2_TCHSCRN_OFFSET (45-32) +#define MXC_CCM_CGCR2_UART1_OFFSET (46-32) +#define MXC_CCM_CGCR2_UART2_OFFSET (47-32) +#define MXC_CCM_CGCR2_UART3_OFFSET (48-32) +#define MXC_CCM_CGCR2_UART4_OFFSET (49-32) +#define MXC_CCM_CGCR2_UART5_OFFSET (50-32) +#define MXC_CCM_CGCR2_WDOG_OFFSET (51-32) + +#define MXC_CCM_CGCR0_STOP_MODE_MASK \ + ((1 << MXC_CCM_CGCR0_HCLK_SLCDC_OFFSET) | \ + (1 << MXC_CCM_CGCR0_HCLK_RTIC_OFFSET) | \ + (1 << MXC_CCM_CGCR0_HCLK_EMI_OFFSET) | \ + (1 << MXC_CCM_CGCR0_HCLK_BROM_OFFSET)) + +#define MXC_CCM_CGCR1_STOP_MODE_MASK ((1 << MXC_CCM_CGCR1_IIM_OFFSET) | \ + (1 << MXC_CCM_CGCR1_CAN2_OFFSET) | \ + (1 << MXC_CCM_CGCR1_CAN1_OFFSET)) + +#define MXC_CCM_CGCR2_STOP_MODE_MASK ((1 << MXC_CCM_CGCR2_SPBA_OFFSET) | \ + (1 << MXC_CCM_CGCR2_SDMA_OFFSET) | \ + (1 << MXC_CCM_CGCR2_RTIC_OFFSET)) + +#define MXC_CCM_PCDR1_PERDIV1_MASK 0x3f + +#define MXC_CCM_RCSR_NF16B (1 << 14) + +#define MXC_CCM_PMCR1_CPEN_EMI (1 << 29) +#define MXC_CCM_PMCR1_CSPAEM_P_OFFSET 26 +#define MXC_CCM_PMCR1_CSPAEM_N_OFFSET 24 +#define MXC_CCM_PMCR1_CSPAEM_MASK (0xf << 24) +#define MXC_CCM_PMCR1_WBCN_OFFSET 16 +#define MXC_CCM_PMCR1_CPEN (1 << 13) +#define MXC_CCM_PMCR1_CSPA_P_OFFSET 11 +#define MXC_CCM_PMCR1_CSPA_N_OFFSET 9 +#define MXC_CCM_PMCR1_CSPA_MASK (0xf << 9) + +#define MXC_CCM_PMCR1_WBCN_MASK (0xff << 16) +#define MXC_CCM_PMCR1_WBCN_DEFAULT 0xa0 +#define MXC_CCM_PMCR1_WBB_INCR 0 +#define MXC_CCM_PMCR1_WBB_MODE 1 +#define MXC_CCM_PMCR1_WBB_DECR 2 +#define MXC_CCM_PMCR1_WBB_MINI 3 + +#define MXC_CCM_PMCR2_VSTBY (1 << 17) +#define MXC_CCM_PMCR2_OSC24M_DOWN (1 << 16) + +#define MXC_CCM_PMCR1_AWB_EN (MXC_CCM_PMCR1_CPEN_EMI | \ + MXC_CCM_PMCR1_CPEN | \ + (MXC_CCM_PMCR1_WBCN_DEFAULT << \ + MXC_CCM_PMCR1_WBCN_OFFSET)) + +#define MXC_CCM_PMCR1_WBB_DEFAULT ((MXC_CCM_PMCR1_WBB_DECR << \ + MXC_CCM_PMCR1_CSPAEM_P_OFFSET) | \ + (MXC_CCM_PMCR1_WBB_DECR << \ + MXC_CCM_PMCR1_CSPAEM_N_OFFSET) | \ + (MXC_CCM_PMCR1_WBB_DECR << \ + MXC_CCM_PMCR1_CSPA_P_OFFSET) | \ + (MXC_CCM_PMCR1_WBB_DECR << \ + MXC_CCM_PMCR1_CSPA_N_OFFSET)) + +#define MXC_CCM_PMCR1_AWB_DEFAULT (MXC_CCM_PMCR1_AWB_EN | \ + MXC_CCM_PMCR1_WBB_DEFAULT) + +#define MXC_CCM_MCR_USB_XTAL_MUX_OFFSET 31 +#define MXC_CCM_MCR_CLKO_EN_OFFSET 30 +#define MXC_CCM_MCR_CLKO_DIV_OFFSET 24 +#define MXC_CCM_MCR_CLKO_DIV_MASK (0x3F << 24) +#define MXC_CCM_MCR_CLKO_SEL_OFFSET 20 +#define MXC_CCM_MCR_CLKO_SEL_MASK (0xF << 20) +#define MXC_CCM_MCR_ESAI_CLK_MUX_OFFSET 19 +#define MXC_CCM_MCR_SSI2_CLK_MUX_OFFSET 18 +#define MXC_CCM_MCR_SSI1_CLK_MUX_OFFSET 17 +#define MXC_CCM_MCR_USB_CLK_MUX_OFFSET 16 + +#define MXC_CCM_MCR_PER_CLK_MUX_MASK (0xFFFF << 0) + +#define MXC_CCM_LPIMR0_MASK 0xFFFFFFFF +#define MXC_CCM_LPIMR1_MASK 0xFFFFFFFF + +#endif /* __ARCH_ARM_MACH_MX25_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 3a405fa400eb..532ee52c64d5 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -1,5 +1,6 @@ /* * Copyright 2009 Sascha Hauer, + * Copyright (C) 2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -17,11 +18,103 @@ */ #include +#include +#include +#include +#include +#include +#include #include #include +#include #include #include +#include +#include +#include +#include +#include + +#include "iomux.h" +#include "sdma_script_code.h" + +void mxc_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR; + + sdma_script_addr->mxc_sdma_per_2_per_addr = -1; + + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_per_ADDR; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR; + + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR; + + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR; + + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = -1; + + sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = -1; + + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = ext_mem__ipu_ram_ADDR; + sdma_script_addr->mxc_sdma_descrambler_addr = -1; + + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; + sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR; +} + +static struct resource sdma_resources[] = { + { + .start = SDMA_BASE_ADDR, + .end = SDMA_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_SDMA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_dma_device = { + .name = "mxc_sdma", + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(sdma_resources), + .resource = sdma_resources, +}; + +static inline void mxc_init_dma(void) +{ + (void)platform_device_register(&mxc_dma_device); +} + static struct resource uart0[] = { { .start = 0x43f90000, @@ -295,25 +388,6 @@ struct platform_device mxc_pwm_device2 = { .resource = mxc_pwm_resources2, }; -static struct resource mxc_keypad_resources[] = { - { - .start = 0x43fa8000, - .end = 0x43fabfff, - .flags = IORESOURCE_MEM, - }, { - .start = 24, - .end = 24, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_keypad_device = { - .name = "mxc-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(mxc_keypad_resources), - .resource = mxc_keypad_resources, -}; - static struct resource mxc_pwm_resources3[] = { { .start = 0x53fc8000, @@ -515,3 +589,196 @@ struct platform_device mxc_wdt = { .num_resources = ARRAY_SIZE(mxc_wdt_resources), .resource = mxc_wdt_resources, }; + +/* imx adc driver */ +#if defined(CONFIG_IMX_ADC) || defined(CONFIG_IMX_ADC_MODULE) + +static struct resource imx_adc_resources[] = { + [0] = { + .start = MX25_INT_TSC, + .end = MX25_INT_TSC, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = MX25_TSC_BASE_ADDR, + .end = MX25_TSC_BASE_ADDR + PAGE_SIZE, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device imx_adc_device = { + .name = "imx_adc", + .id = 0, + .num_resources = ARRAY_SIZE(imx_adc_resources), + .resource = imx_adc_resources, + .dev = { + .release = NULL, + }, +}; +static void imx_init_adc(void) +{ + (void)platform_device_register(&imx_adc_device); +} +#else +static void imx_init_adc(void) +{ +} +#endif + +#if defined(CONFIG_SND_MXC_SOC_ESAI) || defined(CONFIG_SND_MXC_SOC_ESAI_MODULE) + +static struct mxc_esai_platform_data esai_data = { + .activate_esai_ports = gpio_activate_esai_ports, + .deactivate_esai_ports = gpio_deactivate_esai_ports, +}; + +static struct resource esai_resources[] = { + { + .start = MX25_ESAI_BASE_ADDR, + .end = MX25_ESAI_BASE_ADDR + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_ESAI, + .end = MX25_INT_ESAI, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_esai_device = { + .name = "mxc_esai", + .id = 0, + .num_resources = ARRAY_SIZE(esai_resources), + .resource = esai_resources, + .dev = { + .platform_data = &esai_data, + }, +}; + +static void mxc_init_esai(void) +{ + platform_device_register(&mxc_esai_device); +} +#else +static void mxc_init_esai(void) +{ + +} +#endif + +static struct mxc_audio_platform_data mxc_surround_audio_data = { + .ext_ram = 1, +}; + +static struct platform_device mxc_alsa_surround_device = { + .name = "imx-3stack-wm8580", + .id = 0, + .dev = { + .platform_data = &mxc_surround_audio_data, + }, +}; + +static void mxc_init_surround_audio(void) +{ + platform_device_register(&mxc_alsa_surround_device); +} + +#if defined(CONFIG_MXC_IIM) || defined(CONFIG_MXC_IIM_MODULE) +static struct resource mxc_iim_resources[] = { + { + .start = MX25_IIM_BASE_ADDR, + .end = MX25_IIM_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_iim_data iim_data = { + .bank_start = MXC_IIM_BANK_START_ADDR, + .bank_end = MXC_IIM_BANK_END_ADDR, +}; + +static struct platform_device mxc_iim_device = { + .name = "mxc_iim", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_iim_resources), + .resource = mxc_iim_resources, + .dev.platform_data = &iim_data, +}; + +static inline void mxc_init_iim(void) +{ + if (platform_device_register(&mxc_iim_device) < 0) + dev_err(&mxc_iim_device.dev, + "Unable to register mxc iim device\n"); +} +#else +static inline void mxc_init_iim(void) +{ +} +#endif + +#if defined(CONFIG_SND_MXC_SOC_SSI) || defined(CONFIG_SND_MXC_SOC_SSI_MODULE) + +static struct resource ssi1_resources[] = { + { + .start = MX25_SSI1_BASE_ADDR, + .end = MX25_SSI1_BASE_ADDR + 0x5C, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_SSI1, + .end = MX25_INT_SSI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_alsa_ssi1_device = { + .name = "mxc_ssi", + .id = 0, + .num_resources = ARRAY_SIZE(ssi1_resources), + .resource = ssi1_resources, +}; + +static struct resource ssi2_resources[] = { + { + .start = MX25_SSI2_BASE_ADDR, + .end = MX25_SSI2_BASE_ADDR + 0x5C, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_SSI2, + .end = MX25_INT_SSI2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_alsa_ssi2_device = { + .name = "mxc_ssi", + .id = 1, + .num_resources = ARRAY_SIZE(ssi2_resources), + .resource = ssi2_resources, +}; + +static inline void mxc_init_ssi(void) +{ + platform_device_register(&mxc_alsa_ssi1_device); + platform_device_register(&mxc_alsa_ssi2_device); +} +#else +static inline void mxc_init_ssi(void) +{ +} +#endif /* CONFIG_SND_MXC_SOC_SSI */ + +static int __init mxc_init_devices(void) +{ + mxc_init_dma(); + mxc_init_surround_audio(); + imx_init_adc(); + mxc_init_iim(); + mxc_init_ssi(); + mxc_init_esai(); + return 0; +} + +arch_initcall(mxc_init_devices); diff --git a/arch/arm/mach-mx25/dma.c b/arch/arm/mach-mx25/dma.c new file mode 100644 index 000000000000..85a92751a812 --- /dev/null +++ b/arch/arm/mach-mx25/dma.c @@ -0,0 +1,663 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +#include "serial.h" + +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define soc_trans_type int_2_per +#else +#define soc_trans_type emi_2_per +#endif + +#define MXC_SSI_TX0_REG 0x0 +#define MXC_SSI_TX1_REG 0x4 +#define MXC_SSI_RX0_REG 0x8 +#define MXC_SSI_RX1_REG 0xC +#define MXC_SSI_TXFIFO_WML 0x4 +#define MXC_SSI_RXFIFO_WML 0x6 + +#define MXC_ESAI_TX_REG 0x00 +#define MXC_ESAI_RX_REG 0x04 +#define MXC_ESAI_FIFO_WML 0x40 + +struct mxc_sdma_info_entry_s { + mxc_dma_device_t device; + mxc_sdma_channel_params_t *chnl_info; +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_RXTL, + .per_address = MX25_UART1_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART1_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_TXTL, + .per_address = MX25_UART1_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART1_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_RXTL, + .per_address = MX25_UART2_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART2_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_TXTL, + .per_address = MX25_UART2_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART2_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_RXTL, + .per_address = MX25_UART3_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART3_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_TXTL, + .per_address = MX25_UART3_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART3_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_rx_params = { + .chnl_params = { + .watermark_level = UART4_UFCR_RXTL, + .per_address = MX25_UART4_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART4_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART4_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_tx_params = { + .chnl_params = { + .watermark_level = UART4_UFCR_TXTL, + .per_address = MX25_UART4_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART4_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART4_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_rx_params = { + .chnl_params = { + .watermark_level = UART5_UFCR_RXTL, + .per_address = MX25_UART5_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART5_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART5_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_tx_params = { + .chnl_params = { + .watermark_level = UART5_UFCR_TXTL, + .per_address = MX25_UART5_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART5_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART5_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX0, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX0, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX0, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX0, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX0, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX0, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX0, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX0, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX0, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX0, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX0, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX0, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX25_SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_memory_params = { + .chnl_params = { + .peripheral_type = MEMORY, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MEMORY, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = MX25_ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = MX25_ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = MX25_ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = MX25_ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = soc_trans_type, + .event_id = DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static struct mxc_sdma_info_entry_s mxc_sdma_active_dma_info[] = { + {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params}, + {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params}, + {MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params}, + {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params}, + {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params}, + {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params}, + {MXC_DMA_UART4_RX, &mxc_sdma_uart4_rx_params}, + {MXC_DMA_UART4_TX, &mxc_sdma_uart4_tx_params}, + {MXC_DMA_UART5_RX, &mxc_sdma_uart5_rx_params}, + {MXC_DMA_UART5_TX, &mxc_sdma_uart5_tx_params}, + {MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params}, + {MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params}, + {MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params}, + {MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params}, + {MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params}, + {MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params}, + {MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params}, + {MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params}, + {MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params}, + {MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params}, + {MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params}, + {MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params}, + {MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params}, + {MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params}, + {MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params}, + {MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params}, + {MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params}, + {MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params}, + {MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params}, + {MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params}, + {MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params}, + {MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params}, + {MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params}, + {MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params}, + {MXC_DMA_ESAI_16BIT_RX, &mxc_sdma_esai_16bit_rx_params}, + {MXC_DMA_ESAI_16BIT_TX, &mxc_sdma_esai_16bit_tx_params}, + {MXC_DMA_ESAI_24BIT_RX, &mxc_sdma_esai_24bit_rx_params}, + {MXC_DMA_ESAI_24BIT_TX, &mxc_sdma_esai_24bit_tx_params}, + {MXC_DMA_MEMORY, &mxc_sdma_memory_params}, +}; + +static int mxc_sdma_info_entrys = + sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]); +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id) +{ + struct mxc_sdma_info_entry_s *p = mxc_sdma_active_dma_info; + int i; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + if (p->device == channel_id) + return p->chnl_info; + } + return NULL; +} +EXPORT_SYMBOL(mxc_sdma_get_channel_params); + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t *chnl) +{ +#ifdef CONFIG_SDMA_IRAM + int i; + for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++) + chnl[i].dynamic = 0; +#endif +} +EXPORT_SYMBOL(mxc_get_static_channels); diff --git a/arch/arm/mach-mx25/iomux.c b/arch/arm/mach-mx25/iomux.c new file mode 100644 index 000000000000..7c100f2406de --- /dev/null +++ b/arch/arm/mach-mx25/iomux.c @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX25 Board GPIO and Muxing Setup + * @ingroup MSL_MX25 + */ +/*! + * @file mach-mx25/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX25 + */ + +#include +#include +#include +#include +#include +#include +#include "iomux.h" + +/*! + * IOMUX register (base) addresses + */ +#define IOMUXGPR (IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)) +#define IOMUXSW_MUX_CTL (IO_ADDRESS(MX25_IOMUXC_BASE_ADDR) + 0x008) +#define IOMUXSW_MUX_END (IO_ADDRESS(MX25_IOMUXC_BASE_ADDR) + 0x228) +#define IOMUXSW_PAD_CTL (IO_ADDRESS(MX25_IOMUXC_BASE_ADDR) + 0x22C) +#define IOMUXSW_PAD_END (IO_ADDRESS(MX25_IOMUXC_BASE_ADDR) + 0x414) +#define IOMUXSW_INPUT_CTL (IO_ADDRESS(MX25_IOMUXC_BASE_ADDR) + 0x460) +#define IOMUXSW_INPUT_END (IO_ADDRESS(MX25_IOMUXC_BASE_ADDR) + 0x580) + +#define MUX_PIN_NUM_MAX \ + (((IOMUXSW_MUX_END - IOMUXSW_MUX_CTL) >> 2) + 1) +#define MUX_INPUT_NUM_MUX \ + (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) + +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +static DEFINE_SPINLOCK(gpio_mux_lock); +static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX]; +#define MUX_USED 0x80 + +/*! + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param cfg an output function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 ret = 0; + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + void *mux_reg = IOMUXGPR + PIN_TO_IOMUX_MUX(pin); + u8 *rp; + + BUG_ON(pin_index > MUX_PIN_NUM_MAX); + BUG_ON((mux_reg > IOMUXSW_MUX_END) || (mux_reg < IOMUXSW_MUX_CTL)); + spin_lock(&gpio_mux_lock); + __raw_writel(cfg, mux_reg); + /* + * Log a warning if a pin changes ownership + */ + rp = iomux_pin_res_table + pin_index; + if (*rp && *rp != (cfg | MUX_USED)) { + /*Console: how to do */ + printk(KERN_ERR "iomux_config_mux: Warning: iomux pin" + " config changed, index=%d register=%p, " + " prev=0x%x new=0x%x\n", pin_index, mux_reg, + *rp, cfg); + ret = -EINVAL; + } + *rp = cfg | MUX_USED; + spin_unlock(&gpio_mux_lock); + + return ret; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + int ret = iomux_config_mux(pin, cfg); + if (IOMUX_TO_GPIO(pin) < MXC_GPIO_IRQS) { + if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) || + (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) && + ((pin == MX25_PIN_GPIO_A) || (pin == MX25_PIN_GPIO_B) || + (pin == MX25_PIN_GPIO_C) || (pin == MX25_PIN_GPIO_D) || + (pin == MX25_PIN_GPIO_E) || (pin == MX25_PIN_GPIO_F)))) + ret |= gpio_request(IOMUX_TO_GPIO(pin), NULL); + } + return ret; +} +EXPORT_SYMBOL(mxc_request_iomux); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + u8 *rp = iomux_pin_res_table + pin_index; + + BUG_ON((pin_index > MUX_PIN_NUM_MAX)); + + *rp = 0; + if (IOMUX_TO_GPIO(pin) < MXC_GPIO_IRQS) { + if (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_GPIO) || + (((cfg & (~MUX_CONFIG_SION)) == MUX_CONFIG_FUNC) && + ((pin == MX25_PIN_GPIO_A) || (pin == MX25_PIN_GPIO_B) || + (pin == MX25_PIN_GPIO_C) || (pin == MX25_PIN_GPIO_D) || + (pin == MX25_PIN_GPIO_E) || (pin == MX25_PIN_GPIO_F)))) + gpio_free(IOMUX_TO_GPIO(pin)); + } +} +EXPORT_SYMBOL(mxc_free_iomux); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + void *pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); + + BUG_ON((pad_reg > IOMUXSW_PAD_END) || (pad_reg < IOMUXSW_PAD_CTL)); + + __raw_writel(config, pad_reg); +} +EXPORT_SYMBOL(mxc_iomux_set_pad); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en) +{ + u32 l; + + spin_lock(&gpio_mux_lock); + l = __raw_readl(IOMUXGPR); + + if (en) + l |= gp; + else + l &= ~gp; + + __raw_writel(l, IOMUXGPR); + spin_unlock(&gpio_mux_lock); +} +EXPORT_SYMBOL(mxc_iomux_set_gpr); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + void *reg = IOMUXSW_INPUT_CTL + (input << 2); + + BUG_ON(input >= MUX_INPUT_NUM_MUX); + + __raw_writel(config, reg); +} +EXPORT_SYMBOL(mxc_iomux_set_input); diff --git a/arch/arm/mach-mx25/iomux.h b/arch/arm/mach-mx25/iomux.h new file mode 100644 index 000000000000..d91f9764fa8e --- /dev/null +++ b/arch/arm/mach-mx25/iomux.h @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX25_IOMUX_H__ +#define __MACH_MX25_IOMUX_H__ + +#include +#include +#include "mx25_pins.h" + +/*! + * @file mach-mx25/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX25 + */ + +typedef unsigned int iomux_pin_name_t; + +/*! + * IOMUX functions + * SW_MUX_CTL + */ +typedef enum iomux_pin_config { + MUX_CONFIG_FUNC = 0, /*!< used as function */ + MUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + MUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + MUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + MUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + MUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + MUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + MUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */ +} iomux_pin_cfg_t; + +/*! + * IOMUX pad functions + * SW_PAD_CTL + */ +typedef enum iomux_pad_config { + PAD_CTL_DRV_3_3V = 0x0 << 13, + PAD_CTL_DRV_1_8V = 0x1 << 13, + PAD_CTL_HYS_CMOS = 0x0 << 8, + PAD_CTL_HYS_SCHMITZ = 0x1 << 8, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PULL = 0x1 << 6, + PAD_CTL_PUE_PUD = 0x1 << 6, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/*! + * IOMUX general purpose functions + * IOMUXC_GPR1 + */ +typedef enum iomux_gp_func { + MUX_SDCTL_CSD0_SEL = 0x1 << 0, + MUX_SDCTL_CSD1_SEL = 0x1 << 1, +} iomux_gp_func_t; + +/*! + * IOMUX SELECT_INPUT register index + * Base register is IOMUXSW_INPUT_CTL in iomux.c + */ +typedef enum iomux_input_select { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX, + MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX, + MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX, + MUX_IN_AUDMUX_P7_INPUT_DA_AMX, + MUX_IN_AUDMUX_P7_INPUT_TXFS_AMX, + MUX_IN_CAN1_IPP_IND_CANRX, + MUX_IN_CAN2_IPP_IND_CANRX, + MUX_IN_CSI_IPP_CSI_D_0, + MUX_IN_CSI_IPP_CSI_D_1, + MUX_IN_CSPI1_IPP_IND_SS3_B, + MUX_IN_CSPI2_IPP_CSPI_CLK_IN, + MUX_IN_CSPI2_IPP_IND_DATAREADY_B, + MUX_IN_CSPI2_IPP_IND_MISO, + MUX_IN_CSPI2_IPP_IND_MOSI, + MUX_IN_CSPI2_IPP_IND_SS0_B, + MUX_IN_CSPI2_IPP_IND_SS1_B, + MUX_IN_CSPI3_IPP_CSPI_CLK_IN, + MUX_IN_CSPI3_IPP_IND_DATAREADY_B, + MUX_IN_CSPI3_IPP_IND_MISO, + MUX_IN_CSPI3_IPP_IND_MOSI, + MUX_IN_CSPI3_IPP_IND_SS0_B, + MUX_IN_CSPI3_IPP_IND_SS1_B, + MUX_IN_CSPI3_IPP_IND_SS2_B, + MUX_IN_CSPI3_IPP_IND_SS3_B, + MUX_IN_ESDHC1_IPP_DAT4_IN, + MUX_IN_ESDHC1_IPP_DAT5_IN, + MUX_IN_ESDHC1_IPP_DAT6_IN, + MUX_IN_ESDHC1_IPP_DAT7_IN, + MUX_IN_ESDHC2_IPP_CARD_CLK_IN, + MUX_IN_ESDHC2_IPP_CMD_IN, + MUX_IN_ESDHC2_IPP_DAT0_IN, + MUX_IN_ESDHC2_IPP_DAT1_IN, + MUX_IN_ESDHC2_IPP_DAT2_IN, + MUX_IN_ESDHC2_IPP_DAT3_IN, + MUX_IN_ESDHC2_IPP_DAT4_IN, + MUX_IN_ESDHC2_IPP_DAT5_IN, + MUX_IN_ESDHC2_IPP_DAT6_IN, + MUX_IN_ESDHC2_IPP_DAT7_IN, + MUX_IN_FEC_FEC_COL, + MUX_IN_FEC_FEC_CRS, + MUX_IN_FEC_FEC_RDATA_2, + MUX_IN_FEC_FEC_RDATA_3, + MUX_IN_FEC_FEC_RX_CLK, + MUX_IN_FEC_FEC_RX_ER, + MUX_IN_I2C2_IPP_SCL_IN, + MUX_IN_I2C2_IPP_SDA_IN, + MUX_IN_I2C3_IPP_SCL_IN, + MUX_IN_I2C3_IPP_SDA_IN, + MUX_IN_KPP_IPP_IND_COL_4, + MUX_IN_KPP_IPP_IND_COL_5, + MUX_IN_KPP_IPP_IND_COL_6, + MUX_IN_KPP_IPP_IND_COL_7, + MUX_IN_KPP_IPP_IND_ROW_4, + MUX_IN_KPP_IPP_IND_ROW_5, + MUX_IN_KPP_IPP_IND_ROW_6, + MUX_IN_KPP_IPP_IND_ROW_7, + MUX_IN_SIM1_PIN_SIM_RCVD1_IN, + MUX_IN_SIM1_PIN_SIM_SIMPD1, + MUX_IN_SIM1_SIM_RCVD1_IO, + MUX_IN_SIM2_PIN_SIM_RCVD1_IN, + MUX_IN_SIM2_PIN_SIM_SIMPD1, + MUX_IN_SIM2_SIM_RCVD1_IO, + MUX_IN_UART3_IPP_UART_RTS_B, + MUX_IN_UART3_IPP_UART_RXD_MUX, + MUX_IN_UART4_IPP_UART_RTS_B, + MUX_IN_UART4_IPP_UART_RXD_MUX, + MUX_IN_UART5_IPP_UART_RTS_B, + MUX_IN_UART5_IPP_UART_RXD_MUX, + MUX_IN_USB_TOP_IPP_IND_OTG_USB_OC, + MUX_IN_USB_TOP_IPP_IND_UH2_USB_OC, +} iomux_input_select_t; + +/*! + * IOMUX input functions + * SW_SELECT_INPUT bits 2-0 + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_cfg_t; + +struct mxc_iomux_pin_cfg { + iomux_pin_name_t pin; + u8 mux_mode; + u16 pad_cfg; + u8 in_select; + u8 in_mode; +}; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b + * #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_cfg_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); +#endif diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c index a7e587ff3e9e..2b707da33596 100644 --- a/arch/arm/mach-mx25/mm.c +++ b/arch/arm/mach-mx25/mm.c @@ -2,7 +2,7 @@ * Copyright (C) 1999,2000 Arm Limited * Copyright (C) 2000 Deep Blue Solutions Ltd * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2005-2007, 2010 Freescale Semiconductor, Inc. * - add MX31 specific definitions * * This program is free software; you can redistribute it and/or modify diff --git a/arch/arm/mach-mx25/mx25_3stack.c b/arch/arm/mach-mx25/mx25_3stack.c new file mode 100644 index 000000000000..dc528dd5d130 --- /dev/null +++ b/arch/arm/mach-mx25/mx25_3stack.c @@ -0,0 +1,848 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board-mx25_3stack.h" +#include "crm_regs.h" +#include "iomux.h" +#include "devices.h" + +/*! + * @file mach-mx25/mx25_3stack.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX25 + */ + +unsigned int mx25_3stack_board_io; + +/* working point(wp): 0 - 399MHz; 1 - 266MHz; 2 - 133MHz; */ +/* 24MHz input clock table */ +static struct cpu_wp cpu_wp_mx25[] = { + { + .pll_rate = 399000000, + .cpu_rate = 399000000, + .cpu_podf = 0x0, + .cpu_voltage = 1450000}, + { + .pll_rate = 532000000, + .cpu_rate = 266000000, + .cpu_podf = 0x1, + .cpu_voltage = 1340000}, + { + .pll_rate = 532000000, + .cpu_rate = 133000000, + .cpu_podf = 0x3, + .cpu_voltage = 1340000}, +}; +struct cpu_wp *get_cpu_wp(int *wp) +{ + *wp = 3; + return cpu_wp_mx25; +} + +static void mxc_nop_release(struct device *dev) +{ + /* Nothing */ +} + +#if defined(CONFIG_KEYBOARD_MXC) || defined(CONFIG_KEYBOARD_MXC_MODULE) +static u16 keymapping[16] = { + KEY_UP, KEY_DOWN, KEY_VOLUMEDOWN, KEY_HOME, + KEY_RIGHT, KEY_LEFT, KEY_ENTER, KEY_VOLUMEUP, + KEY_F6, KEY_F8, KEY_F9, KEY_F10, + KEY_F1, KEY_F2, KEY_F3, KEY_POWER, +}; + +static struct resource mxc_kpp_resources[] = { + [0] = { + .start = MX25_INT_KPP, + .end = MX25_INT_KPP, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = MX25_KPP_BASE_ADDR, + .end = MX25_KPP_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct keypad_data keypad_plat_data = { + .rowmax = 4, + .colmax = 4, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + +/* mxc keypad driver */ +struct platform_device mxc_keypad_device = { + .name = "mxc_keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &keypad_plat_data, + }, +}; + +static void mxc_init_keypad(void) +{ + (void)platform_device_register(&mxc_keypad_device); +} +#else +static inline void mxc_init_keypad(void) +{ +} +#endif + +/* MTD NAND flash */ + +#if defined(CONFIG_MTD_NAND_MXC_V2) || defined(CONFIG_MTD_NAND_MXC_V2_MODULE) + +static struct mtd_partition mxc_nand_partitions[] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 3 * 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.configure", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024}, + { + .name = "nand.userfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +static struct resource mxc_nand_resources[] = { + { + .flags = IORESOURCE_MEM, + .name = "NFC_AXI_BASE", + .start = MX25_NFC_BASE_ADDR, + .end = MX25_NFC_BASE_ADDR + SZ_8K - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = MX25_INT_NANDFC, + .end = MX25_INT_NANDFC, + }, +}; + + +static struct flash_platform_data mxc_nand_data = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static struct platform_device mxc_nand_mtd_device = { + .name = "mxc_nandv2_flash", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mxc_nand_data, + }, + .resource = mxc_nand_resources, + .num_resources = ARRAY_SIZE(mxc_nand_resources), +}; + +static void mxc_init_nand_mtd(void) +{ + if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B) + mxc_nand_data.width = 2; + + platform_device_register(&mxc_nand_mtd_device); +} +#else +static inline void mxc_init_nand_mtd(void) +{ +} +#endif + +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) +static const char fb_default_mode[] = "CPT-VGA"; + +/* mxc lcd driver */ +static struct platform_device mxc_fb_device = { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &fb_default_mode, + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; + +/* + * Power on/off CPT VGA panel. + */ +void board_power_lcd(int on) +{ + if (on) { + /* Enable HSYNC bit of touch screen */ + imx_adc_set_hsync(1); + mx2fb_set_brightness(MXC_DEFAULT_INTENSITY); + } else { + /* disable HSYNC bit of touchscreen */ + imx_adc_set_hsync(0); + mx2fb_set_brightness(MXC_INTENSITY_OFF); + } +} +EXPORT_SYMBOL_GPL(board_power_lcd); + +static void mxc_init_fb(void) +{ + (void)platform_device_register(&mxc_fb_device); +} +#else +static inline void mxc_init_fb(void) +{ +} +#endif + +#if defined(CONFIG_BACKLIGHT_MXC) +static struct platform_device mxcbl_devices[] = { +#if defined(CONFIG_BACKLIGHT_MXC_LCDC) || \ + defined(CONFIG_BACKLIGHT_MXC_LCDC_MODULE) + { + .name = "mxc_lcdc_bl", + .id = 0, + }, +#endif +}; + +static inline void mxc_init_bl(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxcbl_devices); i++) + platform_device_register(&mxcbl_devices[i]); +} +#else +static inline void mxc_init_bl(void) +{ +} +#endif + +/*! + * Power Key interrupt handler. + */ +static irqreturn_t power_key_int(int irq, void *dev_id) +{ + pr_info("on-off key pressed\n"); + return 0; +} + +/*! + * Power Key initialization. + */ +static int __init mxc_init_power_key(void) +{ + /*Set power key as wakeup resource */ + int irq, ret; + + mxc_request_iomux(MX25_PIN_A25, MUX_CONFIG_ALT5); + mxc_iomux_set_pad(MX25_PIN_A25, PAD_CTL_DRV_NORMAL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A25), NULL); + gpio_direction_input(IOMUX_TO_GPIO(MX25_PIN_A25)); + + irq = IOMUX_TO_IRQ(MX25_PIN_A25); + set_irq_type(irq, IRQF_TRIGGER_RISING); + ret = request_irq(irq, power_key_int, 0, "power_key", 0); + if (ret) + pr_info("register on-off key interrupt failed\n"); + else + enable_irq_wake(irq); + + return ret; +} + +late_initcall(mxc_init_power_key); + +static struct spi_board_info mxc_spi_board_info[] __initdata = { + { + .modalias = "cpld_spi", + .max_speed_hz = 18000000, + .bus_num = 1, + .chip_select = 0, + .mode = SPI_MODE_0, + }, + { + .modalias = "wm8580_spi", + .max_speed_hz = 8000000, /* max spi SCK clock speed in HZ */ + .bus_num = 1, + .chip_select = 1, + }, +}; + +static struct mxc_camera_platform_data camera_data = { + .core_regulator = NULL, + .io_regulator = NULL, + .analog_regulator = NULL, + .gpo_regulator = NULL, + .mclk = 24000000, +}; + +static struct i2c_board_info mxc_i2c_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "ak5702-i2c", + .addr = 0x13, + }, + { + .type = "ov2640", + .addr = 0x30, + .platform_data = (void *)&camera_data, + }, +}; + +#if defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000) \ + || defined(CONFIG_SND_SOC_IMX_3STACK_SGTL5000_MODULE) +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 2, + .src_port = 1, + .ext_port = 4, + .hp_irq = IOMUX_TO_IRQ(MX25_PIN_A10), + .hp_status = headphone_det_status, + .sysclk = 8300000, +}; + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", + .dev = { + .release = mxc_nop_release, + .platform_data = &sgtl5000_data, + }, +}; + +static void mxc_init_sgtl5000(void) +{ + struct clk *cko1, *parent; + unsigned long rate; + + /* cko1 clock */ + mxc_request_iomux(MX25_PIN_CLKO, MUX_CONFIG_FUNC); + + cko1 = clk_get(NULL, "clko_clk"); + if (IS_ERR(cko1)) + return; + parent = clk_get(NULL, "ipg_clk"); + if (IS_ERR(parent)) + return; + clk_set_parent(cko1, parent); + rate = clk_round_rate(cko1, 13000000); + if (rate < 8000000 || rate > 27000000) { + pr_err("Error: SGTL5000 mclk freq %ld out of range!\n", rate); + clk_put(parent); + clk_put(cko1); + return; + } + clk_set_rate(cko1, rate); + clk_enable(cko1); + sgtl5000_data.sysclk = rate; + sgtl5000_enable_amp(); + platform_device_register(&mxc_sgtl5000_device); +} +#else +static inline void mxc_init_sgtl5000(void) +{ +} +#endif + +#if defined(CONFIG_SND_SOC_IMX_3STACK_AK5702) \ + || defined(CONFIG_SND_SOC_IMX_3STACK_AK5702_MODULE) +static struct platform_device mxc_ak5702_device = { + .name = "imx-3stack-ak5702", + .dev = { + .release = mxc_nop_release, + }, +}; + +static void mxc_init_ak5702(void) +{ + platform_device_register(&mxc_ak5702_device); +} +#else +static inline void mxc_init_ak5702(void) +{ +} +#endif + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +static struct resource smsc911x_resources[] = { + { + .start = LAN9217_BASE_ADDR, + .end = LAN9217_BASE_ADDR + 255, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_BOARD_IRQ_START, + .flags = IORESOURCE_IRQ, + } +}; + +struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .flags = 0x8000 | SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, +}; + +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &smsc911x_config, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static int __init mxc_init_enet(void) +{ + (void)platform_device_register(&smsc_lan9217_device); + return 0; +} +#else +static int __init mxc_init_enet(void) +{ + return 0; +} +#endif + +late_initcall(mxc_init_enet); + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +static struct resource mxc_fec_resources[] = { + { + .start = MX25_FEC_BASE_ADDR, + .end = MX25_FEC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM + }, { + .start = MX25_INT_FEC, + .end = MX25_INT_FEC, + .flags = IORESOURCE_IRQ + }, +}; + +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +struct platform_device mxc_fec_device = { + .name = "fec", + .id = 0, + .dev = { + .platform_data = &fec_data, + }, + .num_resources = ARRAY_SIZE(mxc_fec_resources), + .resource = mxc_fec_resources, +}; + +static __init int mxc_init_fec(void) +{ + return platform_device_register(&mxc_fec_device); +} +#else +static inline int mxc_init_fec(void) +{ + return 0; +} +#endif + +#if defined(CONFIG_IMX_SIM) || defined(CONFIG_IMX_SIM_MODULE) +/* Used to configure the SIM bus */ +static struct mxc_sim_platform_data sim1_data = { + .clk_rate = 5000000, + .clock_sim = "sim1_clk", + .power_sim = NULL, + .init = NULL, + .exit = NULL, + .detect = 1, +}; + +/*! + * Resource definition for the SIM + */ +static struct resource mxc_sim1_resources[] = { + [0] = { + .start = MX25_SIM1_BASE_ADDR, + .end = MX25_SIM1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MX25_INT_SIM1, + .end = MX25_INT_SIM1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = 0, + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for IMX SIM */ +static struct platform_device mxc_sim1_device = { + .name = "mxc_sim", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &sim1_data, + }, + .num_resources = ARRAY_SIZE(mxc_sim1_resources), + .resource = mxc_sim1_resources, +}; + +static inline void mxc_init_sim(void) +{ + (void)platform_device_register(&mxc_sim1_device); +} +#else +static inline void mxc_init_sim(void) +{ +} +#endif + +#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_29_30 | MMC_VDD_32_33, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 52000000, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +/*! + * Resource definition for the SDHC1 + */ +static struct resource mxcsdhc1_resources[] = { + [0] = { + .start = MX25_MMC_SDHC1_BASE_ADDR, + .end = MX25_MMC_SDHC1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MX25_INT_SDHC1, + .end = MX25_INT_SDHC1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IOMUX_TO_IRQ(MX25_PIN_A15), + .end = IOMUX_TO_IRQ(MX25_PIN_A15), + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC1 */ +static struct platform_device mxcsdhc1_device = { + .name = "mxsdhci", + .id = 0, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc1_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +#ifdef CONFIG_MMC_IMX_ESDHCI_SELECT2 +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_29_30 | MMC_VDD_32_33, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 52000000, + .card_fixed = 1, + .card_inserted_state = 1, + .status = sdhc_get_card_det_status, + .clock_mmc = "esdhc2_clk", +}; + +/*! + * Resource definition for the SDHC2 + */ +static struct resource mxcsdhc2_resources[] = { + [0] = { + .start = MX25_MMC_SDHC2_BASE_ADDR, + .end = MX25_MMC_SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MX25_INT_SDHC2, + .end = MX25_INT_SDHC2, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC SDHC2 */ +static struct platform_device mxcsdhc2_device = { + .name = "mxsdhci", + .id = 1, + .dev = { + .release = mxc_nop_release, + .platform_data = &mmc2_data, + }, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, +}; +#endif + +static inline void mxc_init_mmc(void) +{ + (void)platform_device_register(&mxcsdhc1_device); +#ifdef CONFIG_MMC_IMX_ESDHCI_SELECT2 + (void)platform_device_register(&mxcsdhc2_device); +#endif +} +#else +static inline void mxc_init_mmc(void) +{ +} +#endif + +static void __init mx25_3stack_timer_init(void) +{ + struct clk *uart_clk; + + mx25_clocks_init(); + uart_clk = clk_get_sys("imx-uart.0", NULL); + early_console_setup(MX25_UART1_BASE_ADDR, uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx25_3stack_timer_init, +}; + +#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE) +static void flexcan_xcvr_enable(int id, int en) +{ + static int pwdn; + + if (id != 1) /* MX25 3-stack uses only CAN2 */ + return; + + if (en) { + if (!pwdn++) + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D14), 0); + } else { + if (!--pwdn) + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D14), 1); + } +} + +struct flexcan_platform_data flexcan_data[] = { + { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .active = gpio_can_active, + .inactive = gpio_can_inactive, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 6, + .br_propseg = 4, + .br_pseg1 = 4, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .smp = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1,}, + { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .active = gpio_can_active, + .inactive = gpio_can_inactive, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 6, + .br_propseg = 4, + .br_pseg1 = 4, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .smp = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1,}, +}; + +static struct resource flexcan1_resources[] = { + { + .start = MX25_CAN1_BASE_ADDR, + .end = MX25_CAN1_BASE_ADDR + 0x97F, + .flags = IORESOURCE_MEM,}, + { + .start = MX25_INT_CAN1, + .end = MX25_INT_CAN1, + .flags = IORESOURCE_IRQ,} +}; +static struct resource flexcan2_resources[] = { + { + .start = MX25_CAN3_BASE_ADDR, + .end = MX25_CAN3_BASE_ADDR + 0x97F, + .flags = IORESOURCE_MEM,}, + { + .start = MX25_INT_CAN2, + .end = MX25_INT_CAN2, + .flags = IORESOURCE_IRQ,} +}; + +static struct platform_device flexcan_devices[] = { + { + .name = "FlexCAN", + .id = 0, + .num_resources = ARRAY_SIZE(flexcan1_resources), + .resource = flexcan1_resources,}, + { + .name = "FlexCAN", + .id = 1, + .num_resources = ARRAY_SIZE(flexcan2_resources), + .resource = flexcan2_resources,}, +}; + +static inline void mxc_init_flexcan(void) +{ +#ifdef CONFIG_FLEXCAN_MXC_SELECT1 + /* MX25 3stack doesn't use CAN1 */ + mxc_register_device(&flexcan_devices[0], &flexcan_data[0]); +#endif + mxc_register_device(&flexcan_devices[1], &flexcan_data[1]); +} +#else +static inline void mxc_init_flexcan(void) +{ +} +#endif + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_cpu_init(); + +#ifdef CONFIG_DISCONTIGMEM + do { + int nid; + mi->nr_banks = MXC_NUMNODES; + for (nid = 0; nid < mi->nr_banks; nid++) + SET_NODE(mi, nid); + } while (0); +#endif +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + pr_info("AIPS1 VA base: 0x%p\n", IO_ADDRESS(MX25_AIPS1_BASE_ADDR)); + mxc_cpu_common_init(); + mx25_3stack_gpio_init(); + mxc_init_keypad(); +#ifdef CONFIG_I2C + i2c_register_board_info(0, mxc_i2c_board_info, + ARRAY_SIZE(mxc_i2c_board_info)); +#endif + spi_register_board_info(mxc_spi_board_info, + ARRAY_SIZE(mxc_spi_board_info)); + mx25_3stack_init_mc34704(); + mxc_init_fb(); + mxc_init_bl(); + mxc_init_nand_mtd(); + mxc_init_sgtl5000(); + mxc_init_ak5702(); + mxc_init_mmc(); + mxc_init_sim(); + mxc_init_fec(); + mxc_init_flexcan(); + mxc_register_device(&mx25_rtc_device, NULL); +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX25_3DS data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX25_3DS, "Freescale MX25 3-Stack Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = MX25_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mx25_map_io, + .init_irq = mx25_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx25/mx25_3stack_cpld.c b/arch/arm/mach-mx25/mx25_3stack_cpld.c new file mode 100644 index 000000000000..32fb68ae68c0 --- /dev/null +++ b/arch/arm/mach-mx25/mx25_3stack_cpld.c @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "board-mx25_3stack.h" +#include "iomux.h" + +/*! + * @file mach-mx25/mx25_3stack_cpld.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX25 + */ + +extern int mxc_spi_poll_transfer(struct spi_device *spi, + struct spi_transfer *t); +static int __init mxc_expio_init(void); + +struct spi_device *cpld_spi; + +/*! + * This function is used to tranfer data to CPLD regs over CSPI + */ +static inline int mx25_3ds_cpld_rw(u8 *buf, size_t len) +{ + struct spi_transfer t = { + .tx_buf = (const void *)buf, + .rx_buf = buf, + .len = len, + .cs_change = 0, + .delay_usecs = 0, + }; + + if (!cpld_spi) + return -1; + + mxc_spi_poll_transfer(cpld_spi, &t); + return 0; +} + +/*! + * This function is called to read a CPLD register over CSPI. + * + * @param offset number of the cpld register to be read + * + * @return Returns 0 on success -1 on failure. + */ +unsigned int spi_cpld_read(unsigned int offset) +{ + unsigned int frame[2]; + unsigned int reg_num = offset >> 1; + unsigned int data = 0; + + frame[0] = (1 << 13) | ((reg_num & 0x0001FFFF) >> 5) | 0x00001000; + frame[1] = (((reg_num & 0x0000001F) << 27) | 0x0200001f); + mx25_3ds_cpld_rw((u8 *) frame, 2); + data = (frame[1] >> 6) & 0xFFFF; + + reg_num = (offset + 2) >> 1; + frame[0] = (1 << 13) | ((reg_num & 0x0001FFFF) >> 5) | 0x00001000; + frame[1] = (((reg_num & 0x0000001F) << 27) | 0x0200001f); + mx25_3ds_cpld_rw((u8 *) frame, 2); + + data |= (((frame[1] >> 6) & 0xFFFF) << 16); + return data; +} +EXPORT_SYMBOL(spi_cpld_read); + +/*! + * This function is called to write to a CPLD register over CSPI. + * + * @param offset number of the cpld register to be written + * @param reg_val value to be written + * + * @return Returns 0 on success -1 on failure. + */ +unsigned int spi_cpld_write(unsigned int offset, unsigned int reg_val) +{ + unsigned int frame[2] = { 0, 0 }; + unsigned int reg_num = offset >> 1; + unsigned int data = reg_val; + + frame[0] = ((reg_num & 0x0001FFFF) >> 5) | 0x00001000; + frame[1] = (((reg_num & 0x0000001F) << 27) | + ((data & 0x0000FFFF) << 6) | 0x03C00027); + mx25_3ds_cpld_rw((u8 *) frame, 2); + + reg_num = (offset + 2) >> 1; + data = reg_val >> 16; + frame[0] = 0; + frame[1] = 0; + frame[0] = ((reg_num & 0x0001FFFF) >> 5) | 0x00001000; + frame[1] = (((reg_num & 0x0000001F) << 27) | + ((data & 0x0000FFFF) << 6) | 0x03C00027); + + mx25_3ds_cpld_rw((u8 *) frame, 2); + + return 0; +} +EXPORT_SYMBOL(spi_cpld_write); + +static int __init mx25_3ds_cpld_probe(struct spi_device *spi) +{ + unsigned int i = 0; + + spi->bits_per_word = 46; + cpld_spi = spi; + + spi_setup(spi); + i = spi_cpld_read(CPLD_CODE_VER_REG); + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", i); + spi_cpld_write(LED_SWITCH_REG, 0xFF); + + /* disable the interrupt and clear the status */ + spi_cpld_write(INTR_MASK_REG, 0); + spi_cpld_write(INTR_RESET_REG, 0xFFFF); + spi_cpld_write(INTR_RESET_REG, 0); + spi_cpld_write(INTR_MASK_REG, 0x1E); + + mxc_expio_init(); + return 0; +} + +/*! + * This structure contains pointers to the CPLD callback functions. + */ +static struct spi_driver mx25_3ds_cpld_driver = { + .driver = { + .name = "cpld_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = mx25_3ds_cpld_probe, +}; + +static int __init mx25_3ds_cpld_init(void) +{ + pr_info("Registering the CPLD Driver\n"); + return spi_register_driver(&mx25_3ds_cpld_driver); +} +device_initcall(mx25_3ds_cpld_init); + +static int __initdata is_dbg_removed = { 0 }; +static int __init remove_dbg_setup(char *__unused) +{ + is_dbg_removed = 1; + return 0; +} +__setup("remove_dbg", remove_dbg_setup); + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 expio_irq; + struct irq_desc *d; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + expio_irq = MXC_BOARD_IRQ_START; + + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nEXPIO irq: %d unhandled\n", expio_irq); + BUG(); /* oops */ + } + d->handle_irq(expio_irq, d); + + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + /* clear the interrupt status */ + spi_cpld_write(INTR_RESET_REG, 1); + spi_cpld_write(INTR_RESET_REG, 0); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int __init mxc_expio_init(void) +{ + int i; + + if (is_dbg_removed) + return 0; + + /* + * Configure INT line as GPIO input + */ + mxc_request_iomux(MX25_PIN_PWM, MUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX25_PIN_PWM, PAD_CTL_PUE_PUD); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_PWM), NULL); + gpio_direction_input(IOMUX_TO_GPIO(MX25_PIN_PWM)); + + for (i = MXC_BOARD_IRQ_START; + i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(IOMUX_TO_IRQ(MX25_PIN_PWM), IRQF_TRIGGER_LOW); + set_irq_chained_handler(IOMUX_TO_IRQ(MX25_PIN_PWM), + mxc_expio_irq_handler); + + return 0; +} + diff --git a/arch/arm/mach-mx25/mx25_3stack_gpio.c b/arch/arm/mach-mx25/mx25_3stack_gpio.c new file mode 100644 index 000000000000..042aca30e9a7 --- /dev/null +++ b/arch/arm/mach-mx25/mx25_3stack_gpio.c @@ -0,0 +1,1367 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include "board-mx25_3stack.h" +#include "iomux.h" + +/*! + * @file mach-mx25/mx25_3stack_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO_MX25 + */ +static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { +}; + +static struct mxc_iomux_pin_cfg __initdata sim_iomux_pins[] = { + /* SIM1 */ + /* SIM1 CLK */ + { + MX25_PIN_CSI_D2, MUX_CONFIG_ALT4, + PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_CMOS | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE, + }, + /* SIM1 RST */ + { + MX25_PIN_CSI_D3, MUX_CONFIG_ALT4, + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_CMOS | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE, + }, + /* SIM1 VEN */ + { + MX25_PIN_CSI_D4, MUX_CONFIG_ALT4, + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_CMOS | PAD_CTL_100K_PU | + PAD_CTL_PUE_PULL | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE, + }, + /* SIM1 TX */ + { + MX25_PIN_CSI_D5, MUX_CONFIG_ALT4, + PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_CMOS | PAD_CTL_22K_PU | + PAD_CTL_PUE_PULL | PAD_CTL_ODE_OpenDrain | PAD_CTL_PKE_ENABLE, + }, + /* SIM1 PD */ + { + MX25_PIN_CSI_D6, MUX_CONFIG_ALT4, + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_CMOS | PAD_CTL_22K_PU | + PAD_CTL_PUE_PULL | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE, + }, + /* SIM2 */ + /* SIM2 CLK */ + { + MX25_PIN_CSI_D8, MUX_CONFIG_ALT4, + PAD_CTL_DRV_NORMAL | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE, + }, + /* SIM2 RST */ + { + MX25_PIN_CSI_D9, MUX_CONFIG_ALT4, + PAD_CTL_DRV_NORMAL | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE, + }, + /* SIM2 VEN */ + { + MX25_PIN_CSI_MCLK, MUX_CONFIG_ALT4, + PAD_CTL_DRV_NORMAL | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_100K_PU | + PAD_CTL_PUE_PULL | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_NONE, + }, + /* SIM2 TX */ + { + MX25_PIN_CSI_VSYNC, MUX_CONFIG_ALT4, + PAD_CTL_DRV_NORMAL | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE, + }, + /* SIM2 PD */ + { + MX25_PIN_CSI_HSYNC, MUX_CONFIG_ALT4, + PAD_CTL_DRV_NORMAL | PAD_CTL_DRV_3_3V | + PAD_CTL_HYS_SCHMITZ | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_ODE_CMOS | PAD_CTL_PKE_ENABLE, + }, +}; + +static int __initdata enable_sim = { 0 }; +static int __init sim_setup(char *__unused) +{ + enable_sim = 1; + return 1; +} + +__setup("sim", sim_setup); + +/*! + * This system-wide GPIO function initializes the pins during system startup. + * All the statically linked device drivers should put the proper GPIO + * initialization code inside this function. It is called by + * \b fixup_mx25_3stack() during system startup. This function is board + * specific. + */ +void __init mx25_3stack_gpio_init(void) +{ + int i, num = 0; + struct mxc_iomux_pin_cfg *pin_ptr; + + for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) { + mxc_request_iomux(mxc_iomux_pins[i].pin, + mxc_iomux_pins[i].mux_mode); + if (mxc_iomux_pins[i].pad_cfg) + mxc_iomux_set_pad(mxc_iomux_pins[i].pin, + mxc_iomux_pins[i].pad_cfg); + if (mxc_iomux_pins[i].in_select) + mxc_iomux_set_input(mxc_iomux_pins[i].in_select, + mxc_iomux_pins[i].in_mode); + } + + if (enable_sim) { + pin_ptr = sim_iomux_pins; + num = ARRAY_SIZE(sim_iomux_pins); + } + + for (i = 0; i < num; i++) { + mxc_request_iomux(pin_ptr[i].pin, pin_ptr[i].mux_mode); + if (pin_ptr[i].pad_cfg) + mxc_iomux_set_pad(pin_ptr[i].pin, pin_ptr[i].pad_cfg); + if (pin_ptr[i].in_select) + mxc_iomux_set_input(pin_ptr[i].in_select, + pin_ptr[i].in_mode); + } +} + +/*! + * Activate a UART port + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_active(int port, int no_irda) +{ + /* + * Configure the IOMUX control registers for the UART signals + */ + switch (port) { + case 0: + /* UART 1 IOMUX Configs */ + mxc_request_iomux(MX25_PIN_UART1_RXD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART1_TXD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART1_CTS, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX25_PIN_UART1_RXD, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX25_PIN_UART1_TXD, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX25_PIN_UART1_RTS, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX25_PIN_UART1_CTS, + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + + break; + case 1: + /* UART 2 IOMUX Configs */ + mxc_request_iomux(MX25_PIN_UART2_RXD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART2_TXD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART2_RTS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_UART2_CTS, MUX_CONFIG_FUNC); + mxc_iomux_set_pad(MX25_PIN_UART2_RXD, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX25_PIN_UART2_TXD, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + mxc_iomux_set_pad(MX25_PIN_UART2_RTS, + PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX25_PIN_UART2_CTS, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PD); + break; + case 2: + /* UART 3 IOMUX Configs */ + mxc_request_iomux(MX25_PIN_KPP_ROW0, MUX_CONFIG_ALT1); /*RXD*/ + mxc_request_iomux(MX25_PIN_KPP_ROW1, MUX_CONFIG_ALT1); /*TXD*/ + mxc_request_iomux(MX25_PIN_KPP_ROW2, MUX_CONFIG_ALT1); /*RTS*/ + mxc_request_iomux(MX25_PIN_KPP_ROW3, MUX_CONFIG_ALT1); /*CTS*/ + + mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RTS_B, + INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RXD_MUX, + INPUT_CTL_PATH1); + break; + case 3: + /* UART 4 IOMUX Configs */ + mxc_request_iomux(MX25_PIN_LD8, MUX_CONFIG_ALT2); /*RXD*/ + mxc_request_iomux(MX25_PIN_LD9, MUX_CONFIG_ALT2); /*TXD*/ + mxc_request_iomux(MX25_PIN_LD10, MUX_CONFIG_ALT2); /*RTS*/ + mxc_request_iomux(MX25_PIN_LD11, MUX_CONFIG_ALT2); /*CTS*/ + + mxc_iomux_set_input(MUX_IN_UART4_IPP_UART_RTS_B, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_UART4_IPP_UART_RXD_MUX, + INPUT_CTL_PATH0); + case 4: + /* UART 5 IOMUX Configs */ + mxc_request_iomux(MX25_PIN_CSI_D2, MUX_CONFIG_ALT1); /*RXD*/ + mxc_request_iomux(MX25_PIN_CSI_D3, MUX_CONFIG_ALT1); /*TXD*/ + mxc_request_iomux(MX25_PIN_CSI_D4, MUX_CONFIG_ALT1); /*RTS*/ + mxc_request_iomux(MX25_PIN_CSI_D5, MUX_CONFIG_ALT1); /*CTS*/ + + mxc_iomux_set_input(MUX_IN_UART5_IPP_UART_RTS_B, + INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_UART5_IPP_UART_RXD_MUX, + INPUT_CTL_PATH1); + default: + break; + } +} +EXPORT_SYMBOL(gpio_uart_active); + +/*! + * Inactivate a UART port + * + * @param port a UART port + * @param no_irda indicates if the port is used for SIR + */ +void gpio_uart_inactive(int port, int no_irda) +{ + switch (port) { + case 0: + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART1_RXD), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART1_TXD), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART1_RTS), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART1_CTS), NULL); + + mxc_free_iomux(MX25_PIN_UART1_RXD, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_UART1_TXD, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_UART1_CTS, MUX_CONFIG_GPIO); + break; + case 1: + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART2_RXD), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART2_TXD), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART2_RTS), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART2_CTS), NULL); + + mxc_free_iomux(MX25_PIN_UART2_RXD, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_UART2_TXD, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_UART2_RTS, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_UART2_CTS, MUX_CONFIG_GPIO); + break; + case 2: + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_ROW0), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_ROW1), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_ROW2), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_ROW3), NULL); + + mxc_free_iomux(MX25_PIN_KPP_ROW0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_ROW1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_ROW2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_ROW3, MUX_CONFIG_GPIO); + break; + case 3: + mxc_free_iomux(MX25_PIN_LD8, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD9, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD10, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD11, MUX_CONFIG_FUNC); + break; + case 4: + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D2), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D3), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D4), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D5), NULL); + + mxc_free_iomux(MX25_PIN_CSI_D2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D3, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D4, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D5, MUX_CONFIG_GPIO); + break; + default: + break; + } +} +EXPORT_SYMBOL(gpio_uart_inactive); + +/*! + * Configure the IOMUX GPR register to receive shared SDMA UART events + * + * @param port a UART port + */ +void config_uartdma_event(int port) +{ +} +EXPORT_SYMBOL(config_uartdma_event); + +/*! + * Activate Keypad + */ +void gpio_keypad_active(void) +{ + mxc_request_iomux(MX25_PIN_KPP_ROW0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_KPP_ROW1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_KPP_ROW2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_KPP_ROW3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_KPP_COL0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_KPP_COL1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_KPP_COL2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_KPP_COL3, MUX_CONFIG_FUNC); + +#define KPP_PAD_CTL_ROW (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | \ + PAD_CTL_100K_PU) +#define KPP_PAD_CTL_COL (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | \ + PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain) + + mxc_iomux_set_pad(MX25_PIN_KPP_ROW0, KPP_PAD_CTL_ROW); + mxc_iomux_set_pad(MX25_PIN_KPP_ROW1, KPP_PAD_CTL_ROW); + mxc_iomux_set_pad(MX25_PIN_KPP_ROW2, KPP_PAD_CTL_ROW); + mxc_iomux_set_pad(MX25_PIN_KPP_ROW3, KPP_PAD_CTL_ROW); + mxc_iomux_set_pad(MX25_PIN_KPP_COL0, KPP_PAD_CTL_COL); + mxc_iomux_set_pad(MX25_PIN_KPP_COL1, KPP_PAD_CTL_COL); + mxc_iomux_set_pad(MX25_PIN_KPP_COL2, KPP_PAD_CTL_COL); + mxc_iomux_set_pad(MX25_PIN_KPP_COL3, KPP_PAD_CTL_COL); + +#undef KPP_PAD_CTL_ROW +#undef KPP_PAD_CTL_COL +} +EXPORT_SYMBOL(gpio_keypad_active); + +/*! + * Inactivate Keypad + */ +void gpio_keypad_inactive(void) +{ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_ROW0), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_ROW1), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_ROW2), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_ROW3), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_COL0), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_COL1), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_COL2), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_KPP_COL3), NULL); + + mxc_free_iomux(MX25_PIN_KPP_ROW0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_ROW1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_ROW2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_ROW3, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_COL0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_COL1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_COL2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_KPP_COL3, MUX_CONFIG_GPIO); +} +EXPORT_SYMBOL(gpio_keypad_inactive); + +/*! + * Activate FEC + */ +void gpio_fec_active(void) +{ + mxc_request_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_POWER_FAIL, MUX_CONFIG_FUNC); /* PHY INT */ + +#define FEC_PAD_CTL1 (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PUE_PUD | \ + PAD_CTL_PKE_ENABLE) +#define FEC_PAD_CTL2 (PAD_CTL_PUE_PUD) + + mxc_iomux_set_pad(MX25_PIN_FEC_TX_CLK, FEC_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_FEC_RX_DV, FEC_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_FEC_RDATA0, FEC_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_FEC_TDATA0, FEC_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_FEC_TX_EN, FEC_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_FEC_MDC, FEC_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_FEC_MDIO, FEC_PAD_CTL1 | PAD_CTL_22K_PU); + mxc_iomux_set_pad(MX25_PIN_FEC_RDATA1, FEC_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_FEC_TDATA1, FEC_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_POWER_FAIL, FEC_PAD_CTL1); + + /* + * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. + * Assert FEC_RESET_B, then power up the PHY by asserting + * FEC_ENABLE, at the same time lifting FEC_RESET_B. + * + * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin D12 + * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin A17 + */ + mxc_request_iomux(MX25_PIN_A17, MUX_CONFIG_ALT5); /* FEC_EN */ + mxc_request_iomux(MX25_PIN_D12, MUX_CONFIG_ALT5); /* FEC_RESET_B */ + + mxc_iomux_set_pad(MX25_PIN_A17, PAD_CTL_ODE_OpenDrain); + mxc_iomux_set_pad(MX25_PIN_D12, 0); + + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A17), "a17"); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_D12), "d12"); + + gpio_direction_output(IOMUX_TO_GPIO(MX25_PIN_A17), 0); /* FEC_EN */ + gpio_direction_output(IOMUX_TO_GPIO(MX25_PIN_D12), 0); /* FEC_RESET_B */ + + /* drop PHY power */ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_A17), 0); /* FEC_EN */ + + /* assert reset */ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D12), 0); /* FEC_RESET_B */ + udelay(2); /* spec says 1us min */ + + /* turn on PHY power and lift reset */ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_A17), 1); /* FEC_EN */ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D12), 1); /* FEC_RESET_B */ + +#undef FEC_PAD_CTL_COMMON +#undef FEC_PAD_CTL1 +#undef FEC_PAD_CTL2 +} +EXPORT_SYMBOL(gpio_fec_active); + +/*! + * Inactivate FEC + */ +void gpio_fec_inactive(void) +{ + /* + * Turn off the PHY. + */ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_A17), 0); + + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_TX_CLK), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_RX_DV), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_RDATA0), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_TDATA0), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_TX_EN), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_MDC), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_MDIO), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_RDATA1), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_TDATA1), NULL); + + mxc_free_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_RDATA0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_TDATA0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_TX_EN, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_MDC, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_MDIO, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_TDATA1, MUX_CONFIG_GPIO); + mxc_request_iomux(MX25_PIN_POWER_FAIL, MUX_CONFIG_FUNC); /* PHY INT */ + + mxc_free_iomux(MX25_PIN_A17, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_D12, MUX_CONFIG_GPIO); /* FEC_RESET_B */ + + /* We keep pin A17, so FEC_ENABLE doesn't float */ +} +EXPORT_SYMBOL(gpio_fec_inactive); + +/*! + * Activate an I2C device + * + * @param i2c_num an I2C device + */ +void gpio_i2c_active(int i2c_num) +{ +#define I2C_PAD_CTL (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \ + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain) + + switch (i2c_num) { + case 0: + /*I2C1*/ + mxc_request_iomux(MX25_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX25_PIN_I2C1_DAT, MUX_CONFIG_SION); + mxc_iomux_set_pad(MX25_PIN_I2C1_CLK, I2C_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_I2C1_DAT, I2C_PAD_CTL); + break; + case 1: + /*I2C2*/ + mxc_request_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_ALT2); /*SCL*/ + mxc_request_iomux(MX25_PIN_GPIO_D, MUX_CONFIG_ALT2); /*SDA*/ + mxc_iomux_set_pad(MX25_PIN_GPIO_C, I2C_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_GPIO_D, I2C_PAD_CTL); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN, INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN, INPUT_CTL_PATH1); + +#if 0 + /* Or use FEC pins if it is not used */ + mxc_request_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_ALT1); /*SCL*/ + mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_ALT1); /*SDA*/ + mxc_iomux_set_pad(MX25_PIN_FEC_RDATA1, I2C_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_FEC_RX_DV, I2C_PAD_CTL); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN, INPUT_CTL_PATH0); +#endif + + break; + case 2: + /*I2C3*/ + mxc_request_iomux(MX25_PIN_HSYNC, MUX_CONFIG_ALT2); /*SCL*/ + mxc_request_iomux(MX25_PIN_VSYNC, MUX_CONFIG_ALT2); /*SDA*/ + mxc_iomux_set_pad(MX25_PIN_HSYNC, I2C_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_VSYNC, I2C_PAD_CTL); + mxc_iomux_set_input(MUX_IN_I2C3_IPP_SCL_IN, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_I2C3_IPP_SDA_IN, INPUT_CTL_PATH0); + break; + default: + break; + } +#undef I2C_PAD_CTL +} +EXPORT_SYMBOL(gpio_i2c_active); + +/*! + * Inactivate an I2C device + * + * @param i2c_num an I2C device + */ +void gpio_i2c_inactive(int i2c_num) +{ + switch (i2c_num) { + case 0: + /*I2C1*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_I2C1_CLK), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_I2C1_DAT), NULL); + mxc_free_iomux(MX25_PIN_I2C1_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_I2C1_DAT, MUX_CONFIG_GPIO); + break; + case 1: + /*I2C2*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_C), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_D), NULL); + mxc_free_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_GPIO_D, MUX_CONFIG_GPIO); + +#if 0 + /* Or use FEC pins if not in use */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_RDATA1, NULL); /*SCL*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_FEC_RX_DV, NULL); /*SDA*/ + mxc_free_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_GPIO); +#endif + + break; + case 2: + /*I2C3*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_HSYNC), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_VSYNC), NULL); + mxc_free_iomux(MX25_PIN_HSYNC, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_VSYNC, MUX_CONFIG_GPIO); + break; + default: + break; + } +} +EXPORT_SYMBOL(gpio_i2c_inactive); + +/*! + * Activate a CSPI device + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_active(int cspi_mod) +{ +#define SPI_PAD_CTL1 (PAD_CTL_HYS_SCHMITZ|PAD_CTL_PKE_ENABLE| \ + PAD_CTL_100K_PU) +#define SPI_PAD_CTL2 (PAD_CTL_HYS_SCHMITZ|PAD_CTL_PKE_ENABLE| \ + PAD_CTL_PUE_PUD|PAD_CTL_100K_PU) + + switch (cspi_mod) { + case 0: + /* SPI1 */ + mxc_request_iomux(MX25_PIN_CSPI1_MOSI, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSPI1_MISO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSPI1_SS0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSPI1_SS1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSPI1_SCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSPI1_RDY, MUX_CONFIG_FUNC); +#ifndef CONFIG_CAN_FLEXCAN /* MX25 3-stack uses this pin for CAN2 */ + mxc_request_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_ALT5); /*SS2*/ +#endif + mxc_request_iomux(MX25_PIN_VSTBY_ACK, MUX_CONFIG_ALT2); /*SS3*/ + + /* Or if VSTBY_ACK is being used */ + /*mxc_request_iomux(MX25_PIN_NF_CE0, MUX_CONFIG_ALT1);*/ /*SS3*/ + + mxc_iomux_set_pad(MX25_PIN_CSPI1_MOSI, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSPI1_MISO, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSPI1_SS0, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSPI1_SS1, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSPI1_SCLK, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSPI1_RDY, SPI_PAD_CTL1); +#ifndef CONFIG_CAN_FLEXCAN /* MX25 3-stack uses this pin for CAN2 */ + mxc_iomux_set_pad(MX25_PIN_GPIO_C, SPI_PAD_CTL2); +#endif + mxc_iomux_set_pad(MX25_PIN_VSTBY_ACK, SPI_PAD_CTL1); + + mxc_iomux_set_input(MUX_IN_CSPI1_IPP_IND_SS3_B, + INPUT_CTL_PATH1); + break; + case 1: + /* SPI2 */ + mxc_request_iomux(MX25_PIN_LD12, MUX_CONFIG_ALT2); /*MOSI*/ + mxc_request_iomux(MX25_PIN_LD13, MUX_CONFIG_ALT2); /*MISO*/ + mxc_request_iomux(MX25_PIN_LD14, MUX_CONFIG_ALT2); /*SCLK*/ + mxc_request_iomux(MX25_PIN_LD15, MUX_CONFIG_ALT2); /*RDY*/ + mxc_request_iomux(MX25_PIN_OE_ACD, MUX_CONFIG_ALT2); /*SS0*/ + mxc_request_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_ALT2); /*SS1*/ + mxc_request_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_ALT7); /*SS2*/ + mxc_request_iomux(MX25_PIN_UART2_RTS, MUX_CONFIG_ALT6); /*SS3*/ + + mxc_iomux_set_pad(MX25_PIN_LD12, SPI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_LD13, SPI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_LD14, SPI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_LD15, SPI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_OE_ACD, SPI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_CONTRAST, SPI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_GPIO_C, SPI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_UART2_RTS, SPI_PAD_CTL2); + + mxc_iomux_set_input(MUX_IN_CSPI2_IPP_CSPI_CLK_IN, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI2_IPP_IND_DATAREADY_B, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI2_IPP_IND_MISO, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI2_IPP_IND_MOSI, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI2_IPP_IND_SS0_B, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI2_IPP_IND_SS1_B, + INPUT_CTL_PATH0); + break; + case 2: + /* SPI3 */ + mxc_request_iomux(MX25_PIN_EB0, MUX_CONFIG_ALT6); /*SS0*/ + mxc_request_iomux(MX25_PIN_EB1, MUX_CONFIG_ALT6); /*SS1*/ + mxc_request_iomux(MX25_PIN_CS4, MUX_CONFIG_ALT6); /*MOSI*/ + mxc_request_iomux(MX25_PIN_CS5, MUX_CONFIG_ALT6); /*MISO*/ + mxc_request_iomux(MX25_PIN_ECB, MUX_CONFIG_ALT6); /*SCLK*/ + mxc_request_iomux(MX25_PIN_LBA, MUX_CONFIG_ALT6); /*RDY*/ + mxc_request_iomux(MX25_PIN_GPIO_D, MUX_CONFIG_ALT7); /*SS2*/ + mxc_request_iomux(MX25_PIN_CSI_D9, MUX_CONFIG_ALT7); /*SS3*/ + + mxc_iomux_set_pad(MX25_PIN_EB0, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_EB1, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CS4, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CS5, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_ECB, SPI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_LBA, SPI_PAD_CTL1); + + mxc_iomux_set_input(MUX_IN_CSPI3_IPP_CSPI_CLK_IN, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI3_IPP_IND_DATAREADY_B, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI3_IPP_IND_MISO, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI3_IPP_IND_MOSI, INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI3_IPP_IND_SS0_B, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI3_IPP_IND_SS1_B, + INPUT_CTL_PATH0); + mxc_iomux_set_input(MUX_IN_CSPI3_IPP_IND_SS2_B, + INPUT_CTL_PATH1); + mxc_iomux_set_input(MUX_IN_CSPI3_IPP_IND_SS3_B, + INPUT_CTL_PATH0); + break; + default: + break; + } +#undef SPI_PAD_CTL1 +#undef SPI_PAD_CTL2 +} +EXPORT_SYMBOL(gpio_spi_active); + +/*! + * Inactivate a CSPI device + * + * @param cspi_mod a CSPI device + */ +void gpio_spi_inactive(int cspi_mod) +{ + switch (cspi_mod) { + case 0: + /* SPI1 */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSPI1_MOSI), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSPI1_MISO), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSPI1_SS0), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSPI1_SS1), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSPI1_SCLK), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSPI1_RDY), NULL); +#ifndef CONFIG_CAN_FLEXCAN /* MX25 3-stack uses this pin for CAN2 */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_C), NULL); /*SS2*/ +#endif + gpio_request(IOMUX_TO_GPIO(MX25_PIN_VSTBY_ACK), NULL); /*SS3*/ + + mxc_free_iomux(MX25_PIN_CSPI1_MOSI, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSPI1_MISO, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSPI1_SS0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSPI1_SS1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSPI1_SCLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSPI1_RDY, MUX_CONFIG_GPIO); +#ifndef CONFIG_CAN_FLEXCAN /* MX25 3-stack uses this pin for CAN2 */ + mxc_free_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_GPIO); +#endif + mxc_free_iomux(MX25_PIN_VSTBY_ACK, MUX_CONFIG_GPIO); + break; + case 1: + /* SPI2 */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD12), NULL); /*MOSI*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD13), NULL); /*MISO*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD14), NULL); /*SCLK*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD15), NULL); /*RDY*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_OE_ACD), NULL); /*SS0*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CONTRAST), NULL); /*SS1*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_C), NULL); /*SS2*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_UART2_RTS), NULL); /*SS3*/ + + mxc_free_iomux(MX25_PIN_LD12, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD13, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD14, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD15, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_OE_ACD, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_UART2_RTS, MUX_CONFIG_GPIO); + break; + case 2: + /* SPI3 */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_EB0), NULL); /*SS0*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_EB1), NULL); /*SS1*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CS4), NULL); /*MOSI*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CS5), NULL); /*MISO*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_ECB), NULL); /*SCLK*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LBA), NULL); /*RDY*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_D), NULL); /*SS2*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D9), NULL); /*SS3*/ + + mxc_free_iomux(MX25_PIN_EB0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_EB1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CS4, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CS5, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_ECB, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LBA, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_GPIO_D, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D9, MUX_CONFIG_GPIO); + break; + default: + break; + } +} +EXPORT_SYMBOL(gpio_spi_inactive); + +/*! + * Activate LCD + */ +void gpio_lcdc_active(void) +{ + mxc_request_iomux(MX25_PIN_LD0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD5, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD6, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD7, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD8, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD9, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD10, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD11, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD12, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD13, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD14, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LD15, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_GPIO_E, MUX_CONFIG_ALT2); /*D16*/ + mxc_request_iomux(MX25_PIN_GPIO_F, MUX_CONFIG_ALT2); /*D17*/ + mxc_request_iomux(MX25_PIN_HSYNC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_VSYNC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_LSCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_OE_ACD, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_FUNC); + +#define LCD_PAD_CTL (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU) + mxc_iomux_set_pad(MX25_PIN_LD0, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD1, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD2, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD3, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD4, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD5, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD6, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD7, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD8, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD9, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD10, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD11, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD12, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD13, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD14, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD15, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_GPIO_E, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_GPIO_F, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_HSYNC, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_VSYNC, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LSCLK, LCD_PAD_CTL | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX25_PIN_OE_ACD, LCD_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CONTRAST, LCD_PAD_CTL); +} +EXPORT_SYMBOL(gpio_lcdc_active); + +/*! + * Inactivate LCD + */ +void gpio_lcdc_inactive(void) +{ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD0), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD1), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD2), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD3), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD4), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD5), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD6), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD7), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_E), NULL); /*D16*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_F), NULL); /*D17*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_HSYNC), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_VSYNC), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LSCLK), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_OE_ACD), NULL); + + mxc_free_iomux(MX25_PIN_LD0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD3, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD4, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD5, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD6, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD7, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD8, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD9, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD10, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD11, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD12, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD13, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD14, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_LD15, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_GPIO_E, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_GPIO_F, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_HSYNC, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_VSYNC, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LSCLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_OE_ACD, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CONTRAST, MUX_CONFIG_FUNC); +} +EXPORT_SYMBOL(gpio_lcdc_inactive); + +/*! + * Activate SDHC + * + * @param module SDHC module number + */ +void gpio_sdhc_active(int module) +{ +#define SDHC_PAD_CTL (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | \ + PAD_CTL_47K_PU | PAD_CTL_SRE_FAST) + + switch (module) { + case 0: + /* SDHC1 */ + mxc_request_iomux(MX25_PIN_SD1_CMD, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX25_PIN_SD1_CLK, + MUX_CONFIG_FUNC | MUX_CONFIG_SION); + mxc_request_iomux(MX25_PIN_SD1_DATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_SD1_DATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_SD1_DATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_SD1_DATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_A14, MUX_CONFIG_ALT5); /*SD1_WP*/ + mxc_request_iomux(MX25_PIN_A15, MUX_CONFIG_ALT5); /*SD1_DET*/ + + mxc_iomux_set_pad(MX25_PIN_SD1_CMD, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_SD1_CLK, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_SD1_DATA0, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_SD1_DATA1, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_SD1_DATA2, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_SD1_DATA3, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_A14, PAD_CTL_DRV_NORMAL); + mxc_iomux_set_pad(MX25_PIN_A15, PAD_CTL_DRV_NORMAL); + + /* Set write protect and card detect gpio as inputs */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A14), "a14"); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A15), "a15"); + gpio_direction_input(IOMUX_TO_GPIO(MX25_PIN_A14)); /*SD1_WP*/ + gpio_direction_input(IOMUX_TO_GPIO(MX25_PIN_A15)); /*SD1_DET*/ + + break; + case 1: + /* SDHC2 */ + mxc_request_iomux(MX25_PIN_LD8, + MUX_CONFIG_ALT6 | MUX_CONFIG_SION); /*CMD*/ + mxc_request_iomux(MX25_PIN_LD9, + MUX_CONFIG_ALT6 | MUX_CONFIG_SION); /*CLK*/ + mxc_request_iomux(MX25_PIN_LD10, MUX_CONFIG_ALT6); /*DAT0*/ + mxc_request_iomux(MX25_PIN_LD11, MUX_CONFIG_ALT6); /*DAT1*/ + mxc_request_iomux(MX25_PIN_LD12, MUX_CONFIG_ALT6); /*DAT2*/ + mxc_request_iomux(MX25_PIN_LD13, MUX_CONFIG_ALT6); /*DAT3*/ + + mxc_iomux_set_pad(MX25_PIN_LD8, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD9, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD10, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD11, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD12, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_LD13, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D2, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D3, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D4, SDHC_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D5, SDHC_PAD_CTL); + break; + default: + break; + } +} +EXPORT_SYMBOL(gpio_sdhc_active); + +/*! + * Inactivate SDHC + * + * @param module SDHC module number + */ +void gpio_sdhc_inactive(int module) +{ + switch (module) { + case 0: + /* SDHC1 */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_SD1_CMD), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_SD1_CLK), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_SD1_DATA0), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_SD1_DATA1), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_SD1_DATA2), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_SD1_DATA3), NULL); + + mxc_free_iomux(MX25_PIN_SD1_CMD, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_SD1_CLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_SD1_DATA0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_SD1_DATA1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_SD1_DATA2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_SD1_DATA3, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_A14, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_A15, MUX_CONFIG_GPIO); + break; + case 1: + /* SDHC2 */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD8), NULL); /*CMD*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD9), NULL); /*CLK*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD10), NULL); /*DAT0*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD11), NULL); /*DAT1*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD12), NULL); /*DAT2*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_LD13), NULL); /*DAT3*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D2), NULL); /*DAT4*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D3), NULL); /*DAT5*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D4), NULL); /*DAT6*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D5), NULL); /*DAT7*/ + + mxc_free_iomux(MX25_PIN_LD8, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD9, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD10, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD11, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD12, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_LD13, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D3, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D4, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D5, MUX_CONFIG_GPIO); + break; + default: + break; + } +} +EXPORT_SYMBOL(gpio_sdhc_inactive); + +/* + * Probe for the card. If present the GPIO data would be set. + */ +unsigned int sdhc_get_card_det_status(struct device *dev) +{ + unsigned int ret = 0; + + ret = gpio_get_value(IOMUX_TO_GPIO(MX25_PIN_A15)); + return ret; +} +EXPORT_SYMBOL(sdhc_get_card_det_status); + +/*! + * Get pin value to detect write protection + */ +int sdhc_write_protect(struct device *dev) +{ + unsigned int rc = 0; + + rc = gpio_get_value(IOMUX_TO_GPIO(MX25_PIN_A14)); + return rc; +} +EXPORT_SYMBOL(sdhc_write_protect); + +/* + * USB Host2 + * + * This configuration uses the on-chip FS/LS serial transceiver. + * USBPHY2_{DP,DM} pins are not muxed. + * We just need to grab USBH2_PWR, USBH2_OC and the Bluetooth/USB + * mux control signal. + */ +int gpio_usbh2_active(void) +{ + if (mxc_request_iomux(MX25_PIN_D9, MUX_CONFIG_ALT6) || /* PWR */ + mxc_request_iomux(MX25_PIN_D8, MUX_CONFIG_ALT6) || /* OC */ + mxc_request_iomux(MX25_PIN_A21, MUX_CONFIG_ALT5)) { /* BT_USB_CS */ + return -EINVAL; + } + + /* + * This pin controls the mux that switches between + * the J18 connector and the on-board bluetooth module. + * dir: 0 = out + * pin: 0 = J18, 1 = BT + */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A21), "a21"); + gpio_direction_output(IOMUX_TO_GPIO(MX25_PIN_A21), 0); + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_A21), 0); + + return 0; +} +EXPORT_SYMBOL(gpio_usbh2_active); + +void gpio_usbh2_inactive(void) +{ + mxc_free_iomux(MX25_PIN_D9, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_D8, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_A21, MUX_CONFIG_GPIO); +} + +/* + * USB OTG UTMI + * + * This configuration uses the on-chip UTMI transceiver. + * USBPHY1_{VBUS,DP,DM,UID,RREF} pins are not muxed. + * We just need to grab the USBOTG_PWR and USBOTG_OC pins. + */ +int gpio_usbotg_utmi_active(void) +{ + if (mxc_request_iomux(MX25_PIN_GPIO_A, MUX_CONFIG_ALT2) || /* PWR */ + mxc_request_iomux(MX25_PIN_GPIO_B, MUX_CONFIG_ALT2)) { /* OC */ + return -EINVAL; + } + return 0; +} +EXPORT_SYMBOL(gpio_usbotg_utmi_active); + +void gpio_usbotg_utmi_inactive(void) +{ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_A), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_B), NULL); + + mxc_free_iomux(MX25_PIN_GPIO_A, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_GPIO_B, MUX_CONFIG_GPIO); +} +EXPORT_SYMBOL(gpio_usbotg_utmi_inactive); + +/*! + * Activate camera sensor + */ +void gpio_sensor_active(void) +{ + mxc_request_iomux(MX25_PIN_CSI_D2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_D3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_D4, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_D5, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_D6, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_D7, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_D8, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_D9, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_HSYNC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_MCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_PIXCLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_CSI_VSYNC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX25_PIN_A19, MUX_CONFIG_ALT5); /*CSI_PWDN*/ + mxc_request_iomux(MX25_PIN_A20, MUX_CONFIG_ALT5); /*CMOS_RST*/ + + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A19), "a19"); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A20), "a20"); + gpio_direction_output(IOMUX_TO_GPIO(MX25_PIN_A19), 0); /*CSI_PWDN*/ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_A19), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX25_PIN_A20), 0); /*CMOS_RST*/ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_A20), 0); + mdelay(20); + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_A20), 1); + +#define CSI_PAD_CTL1 (PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU) +#define CSI_PAD_CTL2 (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \ + PAD_CTL_100K_PU) + + mxc_iomux_set_pad(MX25_PIN_CSI_D2, CSI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSI_D3, CSI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSI_D4, CSI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_CSI_D5, CSI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSI_D6, CSI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSI_D7, CSI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_CSI_D8, CSI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSI_D9, CSI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSI_HSYNC, CSI_PAD_CTL1); + mxc_iomux_set_pad(MX25_PIN_CSI_MCLK, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX25_PIN_CSI_PIXCLK, CSI_PAD_CTL2); + mxc_iomux_set_pad(MX25_PIN_CSI_VSYNC, CSI_PAD_CTL1); +} +EXPORT_SYMBOL(gpio_sensor_active); + +/*! + * Inactivate camera sensor + */ +void gpio_sensor_inactive(void) +{ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D2), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D3), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D4), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D5), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D6), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D7), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D8), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_D9), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_HSYNC), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_MCLK), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_PIXCLK), NULL); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_CSI_VSYNC), NULL); + + mxc_free_iomux(MX25_PIN_A19, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_A20, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D2, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D3, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D4, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D5, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D6, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D7, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D8, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_D9, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_HSYNC, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_MCLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_PIXCLK, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_CSI_VSYNC, MUX_CONFIG_GPIO); +} +EXPORT_SYMBOL(gpio_sensor_inactive); + +/*! + * Activate ESAI ports to enable surround sound I/O + */ +void gpio_activate_esai_ports(void) +{ + mxc_request_iomux(MX25_PIN_CSI_D2, MUX_CONFIG_ALT3); /*SCKR*/ + mxc_request_iomux(MX25_PIN_CSI_D3, MUX_CONFIG_ALT3); /*FSR*/ + mxc_request_iomux(MX25_PIN_CSI_D4, MUX_CONFIG_ALT3); /*HCKR*/ + mxc_request_iomux(MX25_PIN_CSI_D5, MUX_CONFIG_ALT3); /*SCKT*/ + mxc_request_iomux(MX25_PIN_CSI_D6, MUX_CONFIG_ALT3); /*FST*/ + mxc_request_iomux(MX25_PIN_CSI_D7, MUX_CONFIG_ALT3); /*HCKT*/ + mxc_request_iomux(MX25_PIN_CSI_D8, MUX_CONFIG_ALT3); /*TX5_RX0*/ + mxc_request_iomux(MX25_PIN_CSI_D9, MUX_CONFIG_ALT3); /*TX4_RX1*/ + mxc_request_iomux(MX25_PIN_CSI_MCLK, MUX_CONFIG_ALT3); /*TX3_RX2*/ + mxc_request_iomux(MX25_PIN_CSI_VSYNC, MUX_CONFIG_ALT3); /*TX2_RX3*/ + mxc_request_iomux(MX25_PIN_CSI_HSYNC, MUX_CONFIG_ALT3); /*TX1*/ + mxc_request_iomux(MX25_PIN_CSI_PIXCLK, MUX_CONFIG_ALT3); /*TX0*/ + +#define ESAI_PAD_CTL (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \ + PAD_CTL_100K_PU | PAD_CTL_PUE_PUD) + mxc_iomux_set_pad(MX25_PIN_CSI_D2, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D3, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D4, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D5, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D6, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D7, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D8, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_D9, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_MCLK, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_VSYNC, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_HSYNC, ESAI_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_CSI_PIXCLK, ESAI_PAD_CTL); + +#undef ESAI_PAD_CTL +} +EXPORT_SYMBOL(gpio_activate_esai_ports); + +/*! + * Inactivate ESAI ports to disable surround sound I/O + */ +void gpio_deactivate_esai_ports(void) +{ + mxc_free_iomux(MX25_PIN_CSI_D2, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_D3, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_D4, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_D5, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_D6, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_D7, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_D8, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_D9, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_MCLK, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_VSYNC, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_HSYNC, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_CSI_PIXCLK, MUX_CONFIG_FUNC); +} +EXPORT_SYMBOL(gpio_deactivate_esai_ports); + + +/*! + * Activate CAN + */ +void gpio_can_active(int id) +{ +#define CAN_PAD_CTL (PAD_CTL_DRV_3_3V | PAD_CTL_PKE_NONE | PAD_CTL_ODE_CMOS | \ + PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW) +#define CAN_PAD_IN_CTL (PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE) + + switch (id) { + case 0: + /* CAN1 */ + mxc_request_iomux(MX25_PIN_GPIO_A, MUX_CONFIG_ALT6); /*TXCAN*/ + mxc_request_iomux(MX25_PIN_GPIO_B, MUX_CONFIG_ALT6); /*RXCAN*/ + + mxc_iomux_set_pad(MX25_PIN_GPIO_A, CAN_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_GPIO_B, CAN_PAD_IN_CTL); + + mxc_iomux_set_input(MUX_IN_CAN1_IPP_IND_CANRX, INPUT_CTL_PATH1); + break; + case 1: + /* CAN2 */ + mxc_request_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_ALT6); /*TXCAN*/ + mxc_request_iomux(MX25_PIN_GPIO_D, MUX_CONFIG_ALT6); /*RXCAN*/ + mxc_request_iomux(MX25_PIN_D14, MUX_CONFIG_ALT5); /*PWDN*/ + + mxc_iomux_set_pad(MX25_PIN_GPIO_C, CAN_PAD_CTL); + mxc_iomux_set_pad(MX25_PIN_GPIO_D, CAN_PAD_IN_CTL); + mxc_iomux_set_pad(MX25_PIN_D14, CAN_PAD_CTL); + + mxc_iomux_set_input(MUX_IN_CAN2_IPP_IND_CANRX, INPUT_CTL_PATH1); + + /* Configure CAN_PWDN as output */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_D14), "d14"); + gpio_direction_output(IOMUX_TO_GPIO(MX25_PIN_D14), 0); + + /* Enable input by setting PWDN/TLE6250.INH low (gpio4 bit6) */ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D14), 0); + break; + default: + break; + } +} +EXPORT_SYMBOL(gpio_can_active); + +/*! + * Inactivate CAN + */ +void gpio_can_inactive(int id) +{ + switch (id) { + case 0: + /* CAN1 */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_A), NULL); /*TXCAN*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_B), NULL); /*RXCAN*/ + + mxc_free_iomux(MX25_PIN_GPIO_A, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_GPIO_B, MUX_CONFIG_FUNC); + + break; + case 1: + /* CAN2 */ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_C), NULL); /*TXCAN*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_GPIO_D), NULL); /*RXCAN*/ + + mxc_free_iomux(MX25_PIN_GPIO_C, MUX_CONFIG_FUNC); + mxc_free_iomux(MX25_PIN_GPIO_D, MUX_CONFIG_FUNC); + + /* Disable input by setting PWDN/TLE6250.INH high */ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D14), 1); + mxc_free_iomux(MX25_PIN_D14, MUX_CONFIG_ALT5); + break; + default: + break; + } +} +EXPORT_SYMBOL(gpio_can_inactive); + +/*! + * This function activates DAM port 4 to enable + * audio I/O. + */ +void gpio_activate_audio_ports(void) +{ + mxc_request_iomux(MX25_PIN_EB0, MUX_CONFIG_ALT4); /*SSI4_STXD*/ + mxc_request_iomux(MX25_PIN_EB1, MUX_CONFIG_ALT4); /*SSI4_SRXD*/ + mxc_request_iomux(MX25_PIN_RW, MUX_CONFIG_ALT4); /*SSI4_STXFS*/ + mxc_request_iomux(MX25_PIN_OE, MUX_CONFIG_ALT4); /*SSI4_SCK*/ + mxc_request_iomux(MX25_PIN_A10, MUX_CONFIG_ALT5); /*HP_DEC*/ + mxc_request_iomux(MX25_PIN_D13, MUX_CONFIG_ALT5); /*AMP_SHUTDOWN*/ + + mxc_iomux_set_pad(MX25_PIN_EB0, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX25_PIN_EB1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX25_PIN_RW, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX25_PIN_OE, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX25_PIN_D13, PAD_CTL_DRV_3_3V); + + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A10), "a10"); + gpio_direction_input(IOMUX_TO_GPIO(MX25_PIN_A10)); + gpio_request(IOMUX_TO_GPIO(MX25_PIN_D13), "d13"); + gpio_direction_output(IOMUX_TO_GPIO(MX25_PIN_D13), 0); +} +EXPORT_SYMBOL(gpio_activate_audio_ports); + +/*! + * This function deactivates DAM port 4 for + * audio I/O + */ +void gpio_deactive_audio_ports(void) +{ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_EB0), NULL); /*SSI4_STXD*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_EB1), NULL); /*SSI4_SRXD*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_RW), NULL); /*SSI4_STXFS*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_OE), NULL); /*SSI4_SCK*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_A10), NULL); /*HP_DEC*/ + gpio_request(IOMUX_TO_GPIO(MX25_PIN_D13), NULL); /*AMP_SHUTDOWN*/ + + mxc_free_iomux(MX25_PIN_EB0, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_EB1, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_RW, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_OE, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_A10, MUX_CONFIG_GPIO); + mxc_free_iomux(MX25_PIN_D13, MUX_CONFIG_GPIO); +} +EXPORT_SYMBOL(gpio_deactive_audio_ports); + +int headphone_det_status(void) +{ + return gpio_get_value(IOMUX_TO_GPIO(MX25_PIN_A10)); +} +EXPORT_SYMBOL(headphone_det_status); + +void sgtl5000_enable_amp(void) +{ + gpio_set_value(IOMUX_TO_GPIO(MX25_PIN_D13), 1); +} +EXPORT_SYMBOL(sgtl5000_enable_amp); diff --git a/arch/arm/mach-mx25/mx25_3stack_pmic_mc34704.c b/arch/arm/mach-mx25/mx25_3stack_pmic_mc34704.c new file mode 100644 index 000000000000..6c857d00f2e5 --- /dev/null +++ b/arch/arm/mach-mx25/mx25_3stack_pmic_mc34704.c @@ -0,0 +1,147 @@ +/* + * mx25-3stack-pmic-mc34704.c -- i.MX25 3STACK Driver for MC34704 PMIC + */ + /* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "iomux.h" + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +struct mc34704; + +static struct regulator_consumer_supply rcpu_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDA", + .dev_name = "0-000a", + }, +}; + +static struct regulator_consumer_supply rddr_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDIO", + .dev_name = "0-000a", + }, +}; + +static struct regulator_init_data rbklt_init = { + .constraints = { + .name = "REG1_BKLT", + .min_uV = + mV_to_uV(REG1_V_MV * (1000 + REG1_DVS_MIN_PCT * 10) / + 1000), + .max_uV = + mV_to_uV(REG1_V_MV * (1000 + REG1_DVS_MAX_PCT * 10) / + 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data rcpu_init = { + .constraints = { + .name = "REG2_CPU", + .min_uV = + mV_to_uV(REG2_V_MV * (1000 + REG2_DVS_MIN_PCT * 10) / + 1000), + .max_uV = + mV_to_uV(REG2_V_MV * (1000 + REG2_DVS_MAX_PCT * 10) / + 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(rcpu_consumers), + .consumer_supplies = rcpu_consumers, +}; + +static struct regulator_init_data rcore_init = { + .constraints = { + .name = "REG3_CORE", + .min_uV = + mV_to_uV(REG3_V_MV * (1000 + REG3_DVS_MIN_PCT * 10) / + 1000), + .max_uV = + mV_to_uV(REG3_V_MV * (1000 + REG3_DVS_MAX_PCT * 10) / + 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data rddr_init = { + .constraints = { + .name = "REG4_DDR", + .min_uV = + mV_to_uV(REG4_V_MV * (1000 + REG4_DVS_MIN_PCT * 10) / + 1000), + .max_uV = + mV_to_uV(REG4_V_MV * (1000 + REG4_DVS_MAX_PCT * 10) / + 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + }, + .num_consumer_supplies = ARRAY_SIZE(rddr_consumers), + .consumer_supplies = rddr_consumers, +}; + +static struct regulator_init_data rpers_init = { + .constraints = { + .name = "REG5_PERS", + .min_uV = + mV_to_uV(REG5_V_MV * (1000 + REG5_DVS_MIN_PCT * 10) / + 1000), + .max_uV = + mV_to_uV(REG5_V_MV * (1000 + REG5_DVS_MAX_PCT * 10) / + 1000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static int mc34704_regulator_init(struct mc34704 *mc34704) +{ + mc34704_register_regulator(mc34704, MC34704_BKLT, &rbklt_init); + mc34704_register_regulator(mc34704, MC34704_CPU, &rcpu_init); + mc34704_register_regulator(mc34704, MC34704_CORE, &rcore_init); + mc34704_register_regulator(mc34704, MC34704_DDR, &rddr_init); + mc34704_register_regulator(mc34704, MC34704_PERS, &rpers_init); + + return 0; +} + +static struct mc34704_platform_data mc34704_plat = { + .init = mc34704_regulator_init, +}; + +static struct i2c_board_info __initdata mc34704_i2c_device = { + .type = "mc34704", + .addr = 0x54, + .platform_data = &mc34704_plat, +}; + +int __init mx25_3stack_init_mc34704(void) +{ + return i2c_register_board_info(0, &mc34704_i2c_device, 1); +} diff --git a/arch/arm/mach-mx25/mx25_pins.h b/arch/arm/mach-mx25/mx25_pins.h new file mode 100644 index 000000000000..ce11f8252ea6 --- /dev/null +++ b/arch/arm/mach-mx25/mx25_pins.h @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX25_PINS_H__ +#define __ASM_ARCH_MXC_MX25_PINS_H__ + +/*! + * @file arch-mxc/mx25_pins.h + * + * @brief MX25 I/O Pin List + * + * @ingroup GPIO_MX25 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (base is IOMUX_module_base ) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. Similar field + * definitions are used for the pad control register. For example, + * MX25_PIN_A14 is defined in the enumeration: + * ( 0x10 << MUX_I) | ( 0x230 << PAD_I) + * So the absolute address is: IOMUX_module_base + 0x10. + * The pad control register offset is: 0x230. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * reserved filed + */ +#define RSVD_I 21 + +#define NON_GPIO_I 0x7 +#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) +#define NON_MUX_I PIN_TO_MUX_MASK + +#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | ((pi) << PAD_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) + +/*! @} End IOMUX/PAD Bit field definitions */ + +enum iomux_pins { + MX25_PIN_A10 = _MXC_BUILD_GPIO_PIN(3, 0, 0x8, 0x0), + MX25_PIN_A13 = _MXC_BUILD_GPIO_PIN(3, 1, 0x0c, 0x22C), + MX25_PIN_A14 = _MXC_BUILD_GPIO_PIN(1, 0, 0x10, 0x230), + MX25_PIN_A15 = _MXC_BUILD_GPIO_PIN(1, 1, 0x14, 0x234), + MX25_PIN_A16 = _MXC_BUILD_GPIO_PIN(1, 2, 0x18, 0x0), + MX25_PIN_A17 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1c, 0x238), + MX25_PIN_A18 = _MXC_BUILD_GPIO_PIN(1, 4, 0x20, 0x23c), + MX25_PIN_A19 = _MXC_BUILD_GPIO_PIN(1, 5, 0x24, 0x240), + MX25_PIN_A20 = _MXC_BUILD_GPIO_PIN(1, 6, 0x28, 0x244), + MX25_PIN_A21 = _MXC_BUILD_GPIO_PIN(1, 7, 0x2c, 0x248), + MX25_PIN_A22 = _MXC_BUILD_GPIO_PIN(1, 8, 0x30, 0x0), + MX25_PIN_A23 = _MXC_BUILD_GPIO_PIN(1, 9, 0x34, 0x24c), + MX25_PIN_A24 = _MXC_BUILD_GPIO_PIN(1, 10, 0x38, 0x250), + MX25_PIN_A25 = _MXC_BUILD_GPIO_PIN(1, 11, 0x3c, 0x254), + MX25_PIN_EB0 = _MXC_BUILD_GPIO_PIN(1, 12, 0x40, 0x258), + MX25_PIN_EB1 = _MXC_BUILD_GPIO_PIN(1, 13, 0x44, 0x25c), + MX25_PIN_OE = _MXC_BUILD_GPIO_PIN(1, 14, 0x48, 0x260), + MX25_PIN_CS0 = _MXC_BUILD_GPIO_PIN(3, 2, 0x4c, 0x0), + MX25_PIN_CS1 = _MXC_BUILD_GPIO_PIN(3, 3, 0x50, 0x0), + MX25_PIN_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 0x54, 0x264), + MX25_PIN_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 0x58, 0x268), + MX25_PIN_NF_CE0 = _MXC_BUILD_GPIO_PIN(2, 22, 0x5c, 0x26c), + MX25_PIN_ECB = _MXC_BUILD_GPIO_PIN(2, 23, 0x60, 0x270), + MX25_PIN_LBA = _MXC_BUILD_GPIO_PIN(2, 24, 0x64, 0x274), + MX25_PIN_BCLK = _MXC_BUILD_GPIO_PIN(3, 4, 0x68, 0x0), + MX25_PIN_RW = _MXC_BUILD_GPIO_PIN(2, 25, 0x6c, 0x278), + MX25_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(2, 26, 0x70, 0x0), + MX25_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(2, 27, 0x74, 0x0), + MX25_PIN_NFALE = _MXC_BUILD_GPIO_PIN(2, 28, 0x78, 0x0), + MX25_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(2, 29, 0x7c, 0x0), + MX25_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(2, 30, 0x80, 0x0), + MX25_PIN_NFRB = _MXC_BUILD_GPIO_PIN(2, 31, 0x84, 0x27c), + MX25_PIN_D15 = _MXC_BUILD_GPIO_PIN(3, 5, 0x88, 0x280), + MX25_PIN_D14 = _MXC_BUILD_GPIO_PIN(3, 6, 0x8c, 0x284), + MX25_PIN_D13 = _MXC_BUILD_GPIO_PIN(3, 7, 0x90, 0x288), + MX25_PIN_D12 = _MXC_BUILD_GPIO_PIN(3, 8, 0x94, 0x28c), + MX25_PIN_D11 = _MXC_BUILD_GPIO_PIN(3, 9, 0x98, 0x290), + MX25_PIN_D10 = _MXC_BUILD_GPIO_PIN(3, 10, 0x9c, 0x294), + MX25_PIN_D9 = _MXC_BUILD_GPIO_PIN(3, 11, 0xa0, 0x298), + MX25_PIN_D8 = _MXC_BUILD_GPIO_PIN(3, 12, 0xa4, 0x29c), + MX25_PIN_D7 = _MXC_BUILD_GPIO_PIN(3, 13, 0xa8, 0x2a0), + MX25_PIN_D6 = _MXC_BUILD_GPIO_PIN(3, 14, 0xac, 0x2a4), + MX25_PIN_D5 = _MXC_BUILD_GPIO_PIN(3, 15, 0xb0, 0x2a8), + MX25_PIN_D4 = _MXC_BUILD_GPIO_PIN(3, 16, 0xb4, 0x2ac), + MX25_PIN_D3 = _MXC_BUILD_GPIO_PIN(3, 17, 0xb8, 0x2b0), + MX25_PIN_D2 = _MXC_BUILD_GPIO_PIN(3, 18, 0xbc, 0x2b4), + MX25_PIN_D1 = _MXC_BUILD_GPIO_PIN(3, 19, 0xc0, 0x2b8), + MX25_PIN_D0 = _MXC_BUILD_GPIO_PIN(3, 20, 0xc4, 0x2bc), + MX25_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 15, 0xc8, 0x2c0), + MX25_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 16, 0xcc, 0x2c4), + MX25_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 17, 0xd0, 0x2c8), + MX25_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 18, 0xd4, 0x2cc), + MX25_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 19, 0xd8, 0x2d0), + MX25_PIN_LD5 = _MXC_BUILD_GPIO_PIN(0, 19, 0xdc, 0x2d4), + MX25_PIN_LD6 = _MXC_BUILD_GPIO_PIN(0, 20, 0xe0, 0x2d8), + MX25_PIN_LD7 = _MXC_BUILD_GPIO_PIN(0, 21, 0xe4, 0x2dc), + MX25_PIN_LD8 = _MXC_BUILD_NON_GPIO_PIN(0xe8, 0x2e0), + MX25_PIN_LD9 = _MXC_BUILD_NON_GPIO_PIN(0xec, 0x2e4), + MX25_PIN_LD10 = _MXC_BUILD_NON_GPIO_PIN(0xf0, 0x2e8), + MX25_PIN_LD11 = _MXC_BUILD_NON_GPIO_PIN(0xf4, 0x2ec), + MX25_PIN_LD12 = _MXC_BUILD_NON_GPIO_PIN(0xf8, 0x2f0), + MX25_PIN_LD13 = _MXC_BUILD_NON_GPIO_PIN(0xfc, 0x2f4), + MX25_PIN_LD14 = _MXC_BUILD_NON_GPIO_PIN(0x100, 0x2f8), + MX25_PIN_LD15 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x2fc), + MX25_PIN_HSYNC = _MXC_BUILD_GPIO_PIN(0, 22, 0x108, 0x300), + MX25_PIN_VSYNC = _MXC_BUILD_GPIO_PIN(0, 23, 0x10c, 0x304), + MX25_PIN_LSCLK = _MXC_BUILD_GPIO_PIN(0, 24, 0x110, 0x308), + MX25_PIN_OE_ACD = _MXC_BUILD_GPIO_PIN(0, 25, 0x114, 0x30c), + MX25_PIN_CONTRAST = _MXC_BUILD_NON_GPIO_PIN(0x118, 0x310), + MX25_PIN_PWM = _MXC_BUILD_GPIO_PIN(0, 26, 0x11c, 0x314), + MX25_PIN_CSI_D2 = _MXC_BUILD_GPIO_PIN(0, 27, 0x120, 0x318), + MX25_PIN_CSI_D3 = _MXC_BUILD_GPIO_PIN(0, 28, 0x124, 0x31c), + MX25_PIN_CSI_D4 = _MXC_BUILD_GPIO_PIN(0, 29, 0x128, 0x320), + MX25_PIN_CSI_D5 = _MXC_BUILD_GPIO_PIN(0, 30, 0x12c, 0x324), + MX25_PIN_CSI_D6 = _MXC_BUILD_GPIO_PIN(0, 31, 0x130, 0x328), + MX25_PIN_CSI_D7 = _MXC_BUILD_GPIO_PIN(0, 6, 0x134, 0x32c), + MX25_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 7, 0x138, 0x330), + MX25_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(3, 21, 0x13c, 0x334), + MX25_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 8, 0x140, 0x338), + MX25_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 9, 0x144, 0x33c), + MX25_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 10, 0x148, 0x340), + MX25_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 11, 0x14c, 0x344), + MX25_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(0, 12, 0x150, 0x348), + MX25_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(0, 13, 0x154, 0x34c), + MX25_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 14, 0x158, 0x350), + MX25_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 15, 0x15c, 0x354), + MX25_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 16, 0x160, 0x358), + MX25_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 17, 0x164, 0x35c), + MX25_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(0, 18, 0x168, 0x360), + MX25_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(1, 22, 0x16c, 0x364), + MX25_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 22, 0x170, 0x368), + MX25_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 23, 0x174, 0x36c), + MX25_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 24, 0x178, 0x370), + MX25_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 25, 0x17c, 0x374), + MX25_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(3, 26, 0x180, 0x378), + MX25_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(3, 27, 0x184, 0x37c), + MX25_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN(3, 28, 0x188, 0x380), + MX25_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN(3, 29, 0x18c, 0x384), + MX25_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(1, 23, 0x190, 0x388), + MX25_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x194, 0x38c), + MX25_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(1, 25, 0x198, 0x390), + MX25_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(1, 26, 0x19c, 0x394), + MX25_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(1, 27, 0x1a0, 0x398), + MX25_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(1, 28, 0x1a4, 0x39c), + MX25_PIN_KPP_ROW0 = _MXC_BUILD_GPIO_PIN(1, 29, 0x1a8, 0x3a0), + MX25_PIN_KPP_ROW1 = _MXC_BUILD_GPIO_PIN(1, 30, 0x1ac, 0x3a4), + MX25_PIN_KPP_ROW2 = _MXC_BUILD_GPIO_PIN(1, 31, 0x1b0, 0x3a8), + MX25_PIN_KPP_ROW3 = _MXC_BUILD_GPIO_PIN(2, 0, 0x1b4, 0x3ac), + MX25_PIN_KPP_COL0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1b8, 0x3b0), + MX25_PIN_KPP_COL1 = _MXC_BUILD_GPIO_PIN(2, 2, 0x1bc, 0x3b4), + MX25_PIN_KPP_COL2 = _MXC_BUILD_GPIO_PIN(2, 3, 0x1c0, 0x3b8), + MX25_PIN_KPP_COL3 = _MXC_BUILD_GPIO_PIN(2, 4, 0x1c4, 0x3bc), + MX25_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 5, 0x1c8, 0x3c0), + MX25_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 6, 0x1cc, 0x3c4), + MX25_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 7, 0x1d0, 0x3c8), + MX25_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x1d4, 0x3cc), + MX25_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 9, 0x1d8, 0x3d0), + MX25_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x1dc, 0x3d4), + MX25_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 11, 0x1e0, 0x3d8), + MX25_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 12, 0x1e4, 0x3dc), + MX25_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 13, 0x1e8, 0x3e0), + MX25_PIN_RTCK = _MXC_BUILD_GPIO_PIN(2, 14, 0x1ec, 0x3e4), + MX25_PIN_DE_B = _MXC_BUILD_GPIO_PIN(1, 20, 0x1f0, 0x3ec), + MX25_PIN_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x3e8), + MX25_PIN_GPIO_A = _MXC_BUILD_GPIO_PIN(0, 0, 0x1f4, 0x3f0), + MX25_PIN_GPIO_B = _MXC_BUILD_GPIO_PIN(0, 1, 0x1f8, 0x3f4), + MX25_PIN_GPIO_C = _MXC_BUILD_GPIO_PIN(0, 2, 0x1fc, 0x3f8), + MX25_PIN_GPIO_D = _MXC_BUILD_GPIO_PIN(0, 3, 0x200, 0x3fc), + MX25_PIN_GPIO_E = _MXC_BUILD_GPIO_PIN(0, 4, 0x204, 0x400), + MX25_PIN_GPIO_F = _MXC_BUILD_GPIO_PIN(0, 5, 0x208, 0x404), + MX25_PIN_EXT_ARMCLK = _MXC_BUILD_GPIO_PIN(2, 15, 0x20c, 0x0), + MX25_PIN_UPLL_BYPCLK = _MXC_BUILD_GPIO_PIN(2, 16, 0x210, 0x0), + MX25_PIN_VSTBY_REQ = _MXC_BUILD_GPIO_PIN(2, 17, 0x214, 0x408), + MX25_PIN_VSTBY_ACK = _MXC_BUILD_GPIO_PIN(2, 18, 0x218, 0x40c), + MX25_PIN_POWER_FAIL = _MXC_BUILD_GPIO_PIN(2, 19, 0x21c, 0x410), + MX25_PIN_CLKO = _MXC_BUILD_GPIO_PIN(1, 21, 0x220, 0x414), + MX25_PIN_BOOT_MODE0 = _MXC_BUILD_GPIO_PIN(3, 30, 0x224, 0x0), + MX25_PIN_BOOT_MODE1 = _MXC_BUILD_GPIO_PIN(3, 31, 0x228, 0x0), + + MX25_PIN_CTL_GRP_DVS_MISC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x418), + MX25_PIN_CTL_GRP_DSE_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x41c), + MX25_PIN_CTL_GRP_DVS_JTAG = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x420), + MX25_PIN_CTL_GRP_DSE_NFC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x424), + MX25_PIN_CTL_GRP_DSE_CSI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x428), + MX25_PIN_CTL_GRP_DSE_WEIM = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x42c), + MX25_PIN_CTL_GRP_DSE_DDR = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x430), + MX25_PIN_CTL_GRP_DVS_CRM = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x434), + MX25_PIN_CTL_GRP_DSE_KPP = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x438), + MX25_PIN_CTL_GRP_DSE_SDHC1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43c), + MX25_PIN_CTL_GRP_DSE_LCD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440), + MX25_PIN_CTL_GRP_DSE_UART = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444), + MX25_PIN_CTL_GRP_DVS_NFC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448), + MX25_PIN_CTL_GRP_DVS_CSI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44c), + MX25_PIN_CTL_GRP_DSE_CSPI1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450), + MX25_PIN_CTL_GRP_DDRTYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454), + MX25_PIN_CTL_GRP_DVS_SDHC1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x458), + MX25_PIN_CTL_GRP_DVS_LCD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x45c) +}; + +#endif +#endif diff --git a/arch/arm/mach-mx25/pm.c b/arch/arm/mach-mx25/pm.c new file mode 100644 index 000000000000..690bce795389 --- /dev/null +++ b/arch/arm/mach-mx25/pm.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include "crm_regs.h" + +/*! + * @defgroup MSL_MX25 i.MX25 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx25/pm.c + * @brief This file contains suspend operations + * + * @ingroup MSL_MX25 + */ +static unsigned int cgcr0, cgcr1, cgcr2; + +static int mx25_suspend_enter(suspend_state_t state) +{ + unsigned int reg; + + switch (state) { + case PM_SUSPEND_MEM: + mxc_cpu_lp_set(STOP_POWER_OFF); + break; + case PM_SUSPEND_STANDBY: + mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + break; + default: + return -EINVAL; + } + /* Executing CP15 (Wait-for-Interrupt) Instruction */ + cpu_do_idle(); + + reg = (__raw_readl(MXC_CCM_CGCR0) & ~MXC_CCM_CGCR0_STOP_MODE_MASK) | + cgcr0; + __raw_writel(reg, MXC_CCM_CGCR0); + + reg = (__raw_readl(MXC_CCM_CGCR1) & ~MXC_CCM_CGCR1_STOP_MODE_MASK) | + cgcr1; + __raw_writel(reg, MXC_CCM_CGCR1); + + reg = (__raw_readl(MXC_CCM_CGCR2) & ~MXC_CCM_CGCR2_STOP_MODE_MASK) | + cgcr2; + __raw_writel(reg, MXC_CCM_CGCR2); + + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx25_suspend_prepare(void) +{ + cgcr0 = __raw_readl(MXC_CCM_CGCR0) & MXC_CCM_CGCR0_STOP_MODE_MASK; + cgcr1 = __raw_readl(MXC_CCM_CGCR1) & MXC_CCM_CGCR1_STOP_MODE_MASK; + cgcr2 = __raw_readl(MXC_CCM_CGCR2) & MXC_CCM_CGCR2_STOP_MODE_MASK; + + return 0; +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx25_suspend_finish(void) +{ +} + +static int mx25_pm_valid(suspend_state_t state) +{ + return state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX; +} + +struct platform_suspend_ops mx25_suspend_ops = { + .valid = mx25_pm_valid, + .prepare = mx25_suspend_prepare, + .enter = mx25_suspend_enter, + .finish = mx25_suspend_finish, +}; + +static int __init mx25_pm_init(void) +{ + pr_info("Static Power Management for Freescale i.MX25\n"); + suspend_set_ops(&mx25_suspend_ops); + + return 0; +} + +late_initcall(mx25_pm_init); diff --git a/arch/arm/mach-mx25/sdma_script_code.h b/arch/arm/mach-mx25/sdma_script_code.h new file mode 100644 index 000000000000..6adacb03c0d7 --- /dev/null +++ b/arch/arm/mach-mx25/sdma_script_code.h @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/************************************************************************ + + SDMA RELEASE LABEL: "SS15_SENNA" + +************************************************************************/ + +#ifndef SDMA_SCRIPT_CODE_H +#define SDMA_SCRIPT_CODE_H + +/*! + * SDMA ROM scripts start addresses and sizes + */ +#define start_ADDR 0 +#define start_SIZE 22 + +#define core_ADDR 80 +#define core_SIZE 233 + +#define common_ADDR 313 +#define common_SIZE 416 + +#define ap_2_ap_ADDR 729 +#define ap_2_ap_SIZE 41 + +#define app_2_mcu_ADDR 770 +#define app_2_mcu_SIZE 64 + +#define mcu_2_app_ADDR 834 +#define mcu_2_app_SIZE 70 + +#define uart_2_mcu_ADDR 904 +#define uart_2_mcu_SIZE 75 + +#define shp_2_mcu_ADDR 979 +#define shp_2_mcu_SIZE 69 + +#define mcu_2_shp_ADDR 1048 +#define mcu_2_shp_SIZE 72 + +#define uartsh_2_mcu_ADDR 1120 +#define uartsh_2_mcu_SIZE 69 + +#define app_2_per_ADDR 1189 +#define app_2_per_SIZE 66 + +#define per_2_app_ADDR 1255 +#define per_2_app_SIZE 74 + +#define per_2_shp_ADDR 1329 +#define per_2_shp_SIZE 78 + +#define shp_2_per_ADDR 1407 +#define shp_2_per_SIZE 72 + +#define mcu_2_ata_ADDR 1479 +#define mcu_2_ata_SIZE 81 + +#define ata_2_mcu_ADDR 1560 +#define ata_2_mcu_SIZE 96 + +#define loop_DMAs_routines_ADDR 1656 +#define loop_DMAs_routines_SIZE 227 + +#define test_ADDR 1883 +#define test_SIZE 63 + +#define signature_ADDR 1022 +#define signature_SIZE 1 + +/*! + * SDMA RAM scripts start addresses and sizes + */ +#define ext_mem__ipu_ram_ADDR 6144 +#define ext_mem__ipu_ram_SIZE 123 + +#define uart_2_per_ADDR 6267 +#define uart_2_per_SIZE 73 + +#define uartsh_2_per_ADDR 6340 +#define uartsh_2_per_SIZE 67 + +/*! + * SDMA RAM image start address and size + */ +#define RAM_CODE_START_ADDR 6144 +#define RAM_CODE_SIZE 263 + +/*! + * Buffer that holds the SDMA RAM image + */ +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short sdma_code[] = { + 0x0e70, 0x0611, 0x5616, 0xc18a, 0x7d2a, 0x5ade, 0x008e, 0xc19c, + 0x7c26, 0x5be0, 0x5ef0, 0x5ce8, 0x0688, 0x08ff, 0x0011, 0x28ff, + 0x00bc, 0x53f6, 0x05df, 0x7d0b, 0x6dc5, 0x03df, 0x7d03, 0x6bd5, + 0xd84f, 0x982b, 0x6b05, 0xc6d8, 0x7e27, 0x7f29, 0x982b, 0x6d01, + 0x03df, 0x7d05, 0x6bd5, 0xc702, 0x7e18, 0x7f1a, 0x982b, 0x6b05, + 0xc678, 0x7e07, 0x7f06, 0x52de, 0x53e6, 0xc1a8, 0x7dd7, 0x0200, + 0x9803, 0x0007, 0x6004, 0x680c, 0x53f6, 0x028e, 0x00a3, 0xc2ad, + 0x048b, 0x0498, 0x0454, 0x068a, 0x982b, 0x0207, 0x680c, 0x6ddf, + 0x0107, 0x68ff, 0x60d0, 0x9834, 0x0207, 0x68ff, 0x6d28, 0x0107, + 0x6004, 0x680c, 0x9834, 0x0007, 0x68ff, 0x60d0, 0x9834, 0x0288, + 0x03a5, 0x3b03, 0x3d03, 0x4d00, 0x7d0a, 0x0804, 0x00a5, 0x00da, + 0x7d1a, 0x02a0, 0x7b01, 0x65d8, 0x7eee, 0x65ff, 0x7eec, 0x0804, + 0x02d0, 0x7d11, 0x4b00, 0x7c0f, 0x008a, 0x3003, 0x6dcf, 0x6bdf, + 0x0015, 0x0015, 0x7b02, 0x65d8, 0x0000, 0x7edd, 0x63ff, 0x7edb, + 0x3a03, 0x6dcd, 0x6bdd, 0x008a, 0x7b02, 0x65d8, 0x0000, 0x7ed3, + 0x65ff, 0x7ed1, 0x0006, 0xc23a, 0x57db, 0x52f3, 0x6ad5, 0x56fb, + 0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1e, 0x1e94, 0x6ee3, + 0x62d0, 0x5aeb, 0x62c8, 0x0248, 0x6ed3, 0x6ac8, 0x2694, 0x52eb, + 0x6ad5, 0x6ee3, 0x62c8, 0x026e, 0x7d27, 0x6ac8, 0x7f23, 0x2501, + 0x4d00, 0x7d26, 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3, 0x0260, + 0x7df1, 0x62d0, 0xc2d1, 0x98c0, 0x6ee3, 0x008f, 0x2001, 0x00d5, + 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, + 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d09, 0xc251, + 0x57db, 0x987f, 0x0007, 0x6aff, 0x62d0, 0xc2d1, 0x0458, 0x0454, + 0x6add, 0x7ff8, 0xc261, 0x987c, 0xc230, 0xc23a, 0x57db, 0x52f3, + 0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d17, 0x1e94, + 0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d26, 0x6ac8, + 0x7f22, 0x2501, 0x4d00, 0x7d27, 0x028e, 0x1a98, 0x5202, 0x0260, + 0x7df3, 0x6add, 0x7f18, 0x62d0, 0xc2d1, 0x9903, 0x008f, 0x2001, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d0e, 0x6ac8, + 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d0b, + 0xc251, 0x57db, 0x98c9, 0x0007, 0x6aff, 0x6add, 0x7ffc, 0x62d0, + 0xc2d1, 0x0458, 0x0454, 0x6add, 0x7ff6, 0xc261, 0x98c6 +}; +#endif diff --git a/arch/arm/mach-mx25/serial.c b/arch/arm/mach-mx25/serial.c new file mode 100644 index 000000000000..c2310d77c6b0 --- /dev/null +++ b/arch/arm/mach-mx25/serial.c @@ -0,0 +1,332 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file mach-mx25/serial.c + * + * @brief This file contains the UART initiliazation. + * + * @ingroup MSL_MX25 + */ +#include +#include +#include +#include +#include +#include "serial.h" +#include "board-mx25_3stack.h" + +#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) + +/*! + * This is an array where each element holds information about a UART port, + * like base address of the UART, interrupt numbers etc. This structure is + * passed to the serial_core.c file. Based on which UART is used, the core file + * passes back the appropriate port structure as an argument to the control + * functions. + */ +static uart_mxc_port mxc_ports[] = { + [0] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + .ints_muxed = UART1_MUX_INTS, + .mode = UART1_MODE, + .ir_mode = UART1_IR, + .enabled = UART1_ENABLED, + .hardware_flow = UART1_HW_FLOW, + .cts_threshold = UART1_UCR4_CTSTL, + .dma_enabled = UART1_DMA_ENABLE, + .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, + .rx_threshold = UART1_UFCR_RXTL, + .tx_threshold = UART1_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART1_TX, + .dma_rx_id = MXC_DMA_UART1_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [1] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + .ints_muxed = UART2_MUX_INTS, + .mode = UART2_MODE, + .ir_mode = UART2_IR, + .enabled = UART2_ENABLED, + .hardware_flow = UART2_HW_FLOW, + .cts_threshold = UART2_UCR4_CTSTL, + .dma_enabled = UART2_DMA_ENABLE, + .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, + .rx_threshold = UART2_UFCR_RXTL, + .tx_threshold = UART2_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART2_TX, + .dma_rx_id = MXC_DMA_UART2_RX, + .rxd_mux = MXC_UART_IR_RXDMUX, + }, +#if UART3_ENABLED == 1 + [2] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 2, + }, + .ints_muxed = UART3_MUX_INTS, + .mode = UART3_MODE, + .ir_mode = UART3_IR, + .enabled = UART3_ENABLED, + .hardware_flow = UART3_HW_FLOW, + .cts_threshold = UART3_UCR4_CTSTL, + .dma_enabled = UART3_DMA_ENABLE, + .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, + .rx_threshold = UART3_UFCR_RXTL, + .tx_threshold = UART3_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART3_TX, + .dma_rx_id = MXC_DMA_UART3_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, +#endif +#if UART4_ENABLED == 1 + [3] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 3, + }, + .ints_muxed = UART4_MUX_INTS, + .mode = UART4_MODE, + .ir_mode = UART4_IR, + .enabled = UART4_ENABLED, + .hardware_flow = UART4_HW_FLOW, + .cts_threshold = UART4_UCR4_CTSTL, + .dma_enabled = UART4_DMA_ENABLE, + .dma_rxbuf_size = UART4_DMA_RXBUFSIZE, + .rx_threshold = UART4_UFCR_RXTL, + .tx_threshold = UART4_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART4_TX, + .dma_rx_id = MXC_DMA_UART4_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, +#endif +#if UART5_ENABLED == 1 + [4] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 4, + }, + .ints_muxed = UART5_MUX_INTS, + .mode = UART5_MODE, + .ir_mode = UART5_IR, + .enabled = UART5_ENABLED, + .hardware_flow = UART5_HW_FLOW, + .cts_threshold = UART5_UCR4_CTSTL, + .dma_enabled = UART5_DMA_ENABLE, + .dma_rxbuf_size = UART5_DMA_RXBUFSIZE, + .rx_threshold = UART5_UFCR_RXTL, + .tx_threshold = UART5_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART5_TX, + .dma_rx_id = MXC_DMA_UART5_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, +#endif +}; + +static struct resource mxc_uart_resources1[] = { + { + .start = MX25_UART1_BASE_ADDR, + .end = MX25_UART1_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = UART1_INT1, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART1_INT2, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART1_INT3, + .flags = IORESOURCE_IRQ, + }, + +}; + +static struct platform_device mxc_uart_device1 = { + .name = "mxcintuart", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_uart_resources1), + .resource = mxc_uart_resources1, + .dev = { + .platform_data = &mxc_ports[0], + }, +}; + +static struct resource mxc_uart_resources2[] = { + { + .start = MX25_UART2_BASE_ADDR, + .end = MX25_UART2_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = UART2_INT1, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART2_INT2, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART2_INT3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device2 = { + .name = "mxcintuart", + .id = 1, + .num_resources = ARRAY_SIZE(mxc_uart_resources2), + .resource = mxc_uart_resources2, + .dev = { + .platform_data = &mxc_ports[1], + }, +}; + +#if UART3_ENABLED == 1 +static struct resource mxc_uart_resources3[] = { + { + .start = MX25_UART3_BASE_ADDR, + .end = MX25_UART3_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = UART3_INT1, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART3_INT2, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART3_INT3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device3 = { + .name = "mxcintuart", + .id = 2, + .num_resources = ARRAY_SIZE(mxc_uart_resources3), + .resource = mxc_uart_resources3, + .dev = { + .platform_data = &mxc_ports[2], + }, +}; +#endif +#if UART4_ENABLED == 1 +static struct resource mxc_uart_resources4[] = { + { + .start = MX25_UART4_BASE_ADDR, + .end = MX25_UART4_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = UART4_INT1, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART4_INT2, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART4_INT3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device4 = { + .name = "mxcintuart", + .id = 3, + .num_resources = ARRAY_SIZE(mxc_uart_resources4), + .resource = mxc_uart_resources4, + .dev = { + .platform_data = &mxc_ports[3], + }, +}; +#endif +#if UART5_ENABLED == 1 +static struct resource mxc_uart_resources5[] = { + { + .start = MX25_UART5_BASE_ADDR, + .end = MX25_UART5_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = UART5_INT1, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART5_INT2, + .flags = IORESOURCE_IRQ, + }, + { + .start = UART5_INT3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device5 = { + .name = "mxcintuart", + .id = 4, + .num_resources = ARRAY_SIZE(mxc_uart_resources5), + .resource = mxc_uart_resources5, + .dev = { + .platform_data = &mxc_ports[4], + }, +}; +#endif + +static int __init mxc_init_uart(void) +{ + /* Register all the MXC UART platform device structures */ + platform_device_register(&mxc_uart_device1); + platform_device_register(&mxc_uart_device2); + +#if UART3_ENABLED == 1 + platform_device_register(&mxc_uart_device3); +#endif /* UART3_ENABLED */ +#if UART4_ENABLED == 1 + platform_device_register(&mxc_uart_device4); +#endif /* UART4_ENABLED */ +#if UART5_ENABLED == 1 + platform_device_register(&mxc_uart_device5); +#endif /* UART5_ENABLED */ + + return 0; +} + +#else +static int __init mxc_init_uart(void) +{ + return 0; +} +#endif + +arch_initcall(mxc_init_uart); diff --git a/arch/arm/mach-mx25/serial.h b/arch/arm/mach-mx25/serial.h new file mode 100644 index 000000000000..c6e77f9159c2 --- /dev/null +++ b/arch/arm/mach-mx25/serial.h @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX25_SERIAL_H__ +#define __ARCH_ARM_MACH_MX25_SERIAL_H__ + +/*! + * @file mach-mx25/serial.h + * + * @ingroup MSL_MX25 + */ +#include + +/* UART 1 configuration */ +/*! + * This option allows to choose either an interrupt-driven software controlled + * hardware flow control (set this option to 0) or hardware-driven hardware + * flow control (set this option to 1). + */ +#define UART1_HW_FLOW 1 +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * This is option to enable (set this option to 1) or disable DMA data transfer + */ +#define UART1_DMA_ENABLE 0 +/*! + * Specify the size of the DMA receive buffer. The minimum buffer size is 512 + * bytes. The buffer size should be a multiple of 256. + */ +#define UART1_DMA_RXBUFSIZE 1024 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +/* UART 2 configuration */ +#define UART2_HW_FLOW 0 +#define UART2_UCR4_CTSTL (-1) +#define UART2_DMA_ENABLE 0 +#define UART2_DMA_RXBUFSIZE 512 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_HW_FLOW 1 +#define UART3_UCR4_CTSTL 16 +#define UART3_DMA_ENABLE 1 +#define UART3_DMA_RXBUFSIZE 1024 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 +/* UART 4 configuration */ +#define UART4_HW_FLOW 1 +#define UART4_UCR4_CTSTL 16 +#define UART4_DMA_ENABLE 1 +#define UART4_DMA_RXBUFSIZE 1024 +#define UART4_UFCR_RXTL 16 +#define UART4_UFCR_TXTL 16 +/* UART 5 configuration */ +#define UART5_HW_FLOW 1 +#define UART5_UCR4_CTSTL 16 +#define UART5_DMA_ENABLE 1 +#define UART5_DMA_RXBUFSIZE 1024 +#define UART5_UFCR_RXTL 16 +#define UART5_UFCR_TXTL 16 + +/* + * UART Chip level Configuration that a user may not have to edit. These + * configuration vary depending on how the UART module is integrated with + * the ARM core + */ +/* + * Is the MUXED interrupt output sent to the ARM core + */ +#define INTS_NOTMUXED 0 +#define INTS_MUXED 1 +/* UART 1 configuration */ +/*! + * This define specifies whether the muxed ANDed interrupt line or the + * individual interrupts from the UART port is integrated with the ARM core. + * There exists a define like this for each UART port. Valid values that can + * be used are \b INTS_NOTMUXED or \b INTS_MUXED. + */ +#define UART1_MUX_INTS INTS_MUXED +/*! + * This define specifies the transmitter interrupt number or the interrupt + * number of the ANDed interrupt in case the interrupts are muxed. There exists + * a define like this for each UART port. + */ +#define UART1_INT1 MX25_INT_UART1 +/*! + * This define specifies the receiver interrupt number. If the interrupts of + * the UART are muxed, then we specify here a dummy value -1. There exists a + * define like this for each UART port. + */ +#define UART1_INT2 (-1) +/*! + * This specifies the master interrupt number. If the interrupts of the UART + * are muxed, then we specify here a dummy value of -1. There exists a define + * like this for each UART port. + */ +#define UART1_INT3 (-1) +/* UART 2 configuration */ +#define UART2_MUX_INTS INTS_MUXED +#define UART2_INT1 MX25_INT_UART2 +#define UART2_INT2 (-1) +#define UART2_INT3 (-1) +/* UART 3 configuration */ +#define UART3_MUX_INTS INTS_MUXED +#define UART3_INT1 MX25_INT_UART3 +#define UART3_INT2 (-1) +#define UART3_INT3 (-1) +/* UART 4 configuration */ +#define UART4_MUX_INTS INTS_MUXED +#define UART4_INT1 MX25_INT_UART4 +#define UART4_INT2 (-1) +#define UART4_INT3 (-1) +/* UART 5 configuration */ +#define UART5_MUX_INTS INTS_MUXED +#define UART5_INT1 MX25_INT_UART5 +#define UART5_INT2 (-1) +#define UART5_INT3 (-1) + +#endif /* __ARCH_ARM_MACH_MX25_SERIAL_H__ */ diff --git a/arch/arm/mach-mx25/system.c b/arch/arm/mach-mx25/system.c new file mode 100644 index 000000000000..f70b6017e61a --- /dev/null +++ b/arch/arm/mach-mx25/system.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/*! + * @defgroup MSL_MX25 i.MX25 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx25/system.c + * @brief This file contains idle and reset functions. + * + * @ingroup MSL_MX25 + */ + +/*! + * MX25 low-power mode + */ +enum mx25_low_pwr_mode { + MX25_RUN_MODE, + MX25_WAIT_MODE, + MX25_DOZE_MODE, + MX25_STOP_MODE +}; + +extern int mxc_jtag_enabled; + +/*! + * This function is used to set cpu low power mode before WFI instruction + * + * @param mode indicates different kinds of power modes + */ +void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) +{ + unsigned int lpm; + unsigned long reg; + unsigned int pmcr1, pmcr2, lpimr; + unsigned int cgcr0, cgcr1, cgcr2; + struct irq_desc *desc; + int i; + + /*read CCTL value */ + reg = __raw_readl(MXC_CCM_CCTL); + + switch (mode) { + case WAIT_UNCLOCKED_POWER_OFF: + lpm = MX25_DOZE_MODE; + break; + + case STOP_POWER_ON: + case STOP_POWER_OFF: + lpm = MX25_STOP_MODE; + /* The clock of LCDC/SLCDC, SDMA, RTIC, RNGC, MAX, CAN + and EMI needs to be gated on when entering Stop mode. + */ + cgcr0 = __raw_readl(MXC_CCM_CGCR0); + cgcr1 = __raw_readl(MXC_CCM_CGCR1); + cgcr2 = __raw_readl(MXC_CCM_CGCR2); + __raw_writel(cgcr0 | MXC_CCM_CGCR0_STOP_MODE_MASK, + MXC_CCM_CGCR0); + __raw_writel(cgcr1 | MXC_CCM_CGCR1_STOP_MODE_MASK, + MXC_CCM_CGCR1); + __raw_writel(cgcr2 | MXC_CCM_CGCR2_STOP_MODE_MASK, + MXC_CCM_CGCR2); + /* The interrupts which are not wake-up sources need + be mask when entering Stop mode. + */ + lpimr = MXC_CCM_LPIMR0_MASK; + for (i = 0; i < 32; i++) { + desc = irq_desc + i; + if ((desc->status & IRQ_WAKEUP) != 0) + lpimr &= ~(1 << i); + } + __raw_writel(lpimr, MXC_CCM_LPIMR0); + lpimr = MXC_CCM_LPIMR1_MASK; + for (i = 32; i < 64; i++) { + desc = irq_desc + i; + if ((desc->status & IRQ_WAKEUP) != 0) + lpimr &= ~(1 << (i - 32)); + } + __raw_writel(lpimr, MXC_CCM_LPIMR1); + + if (mode == STOP_POWER_OFF) { + pmcr2 = __raw_readl(MXC_CCM_PMCR2); + pmcr2 |= (MXC_CCM_PMCR2_OSC24M_DOWN | + MXC_CCM_PMCR2_VSTBY); + __raw_writel(pmcr2, MXC_CCM_PMCR2); + pmcr1 = __raw_readl(MXC_CCM_PMCR1); + pmcr1 &= ~(MXC_CCM_PMCR1_WBCN_MASK | + MXC_CCM_PMCR1_CSPAEM_MASK | + MXC_CCM_PMCR1_CSPA_MASK); + pmcr1 |= MXC_CCM_PMCR1_AWB_DEFAULT; + __raw_writel(pmcr1, MXC_CCM_PMCR1); + } + break; + + case WAIT_CLOCKED: + case WAIT_UNCLOCKED: + default: + /* Wait is the default mode used when idle. */ + lpm = MX25_WAIT_MODE; + break; + } + + /* program LP CTL bit */ + reg = ((reg & (~MXC_CCM_CCTL_LP_CTL_MASK)) | + lpm << MXC_CCM_CCTL_LP_CTL_OFFSET); + + __raw_writel(reg, MXC_CCM_CCTL); +} + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks. + */ + if (!mxc_jtag_enabled) { + /* set as Wait mode */ + mxc_cpu_lp_set(WAIT_UNCLOCKED); + cpu_do_idle(); + } +} + +#if 0 +/* + * This function resets the system. It is called by machine_restart(). + * + * @param mode indicates different kinds of resets + */ +void arch_reset(char mode) +{ + /* Assert SRS signal */ + mxc_wd_reset(); +} +#endif diff --git a/arch/arm/mach-mx25/usb.h b/arch/arm/mach-mx25/usb.h new file mode 100644 index 000000000000..b1c21a7ffaa8 --- /dev/null +++ b/arch/arm/mach-mx25/usb.h @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_utmi_active(void); +extern void gpio_usbotg_utmi_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, + struct fsl_usb2_platform_data + *config); + +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbh2_active(void); +extern void gpio_usbh2_inactive(void); + +/* + * Determine which platform_data struct to use for the DR controller, + * based on which transceiver is configured. + * PDATA is a pointer to it. + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config; +#define PDATA (&dr_utmi_config) + +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff --git a/arch/arm/mach-mx25/usb_dr.c b/arch/arm/mach-mx25/usb_dr.c new file mode 100644 index 000000000000..9dd6c8f54911 --- /dev/null +++ b/arch/arm/mach-mx25/usb_dr.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include "usb.h" + +static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable); + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init, + .platform_uninit = usbotg_uninit, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* via RT9706 */ + .gpio_usb_active = gpio_usbotg_utmi_active, + .gpio_usb_inactive = gpio_usbotg_utmi_inactive, + .transceiver = "utmi", + .wake_up_enable = _wake_up_enable, +}; + +/* + * OTG resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MX25_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device __maybe_unused dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), +}; + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + if (get_usb_mode(pdata) == FSL_USB_DR_DEVICE) { + if (enable) + USBCTRL |= (UCTRL_OWIE | UCTRL_VBUS_WKUP_EN); + else { + USBCTRL &= ~UCTRL_OWIE; + USBCTRL &= ~UCTRL_VBUS_WKUP_EN; + } + } else { + if (enable) + USBCTRL |= UCTRL_OWIE; + else + USBCTRL &= ~UCTRL_OWIE; + } +} + +static int __init usb_dr_init(void) +{ + pr_debug("%s: \n", __func__); + + dr_register_otg(); + dr_register_host(otg_resources, ARRAY_SIZE(otg_resources)); + dr_register_udc(); + + return 0; +} + +module_init(usb_dr_init); diff --git a/arch/arm/mach-mx25/usb_h2.c b/arch/arm/mach-mx25/usb_h2.c new file mode 100644 index 000000000000..ba29172df3a8 --- /dev/null +++ b/arch/arm/mach-mx25/usb_h2.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "usb.h" + +static struct fsl_usb2_platform_data usbh2_config = { + .name = "Host 2", + .platform_init = fsl_usb_host_init, + .platform_uninit = fsl_usb_host_uninit, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_SERIAL, + .power_budget = 500, /* via RT9702 */ + .gpio_usb_active = gpio_usbh2_active, + .gpio_usb_inactive = gpio_usbh2_inactive, + .transceiver = "serial", /* on-chip */ +}; + +static struct resource usbh2_resources[] = { + [0] = { + .start = (u32) (USB_H2REGS_BASE), + .end = (u32) (USB_H2REGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MX25_INT_USB_HTG, + .flags = IORESOURCE_IRQ, + }, +}; + +void usbh2_get_xcvr_power(struct device *dev) +{ + struct regulator *usbh2_regux; + + usbh2_regux = regulator_get(dev, "GPO1"); + regulator_enable(usbh2_regux); + ((struct fsl_usb2_platform_data *)dev->platform_data)-> + xcvr_pwr->regu1 = usbh2_regux; + + usbh2_regux = regulator_get(dev, "GPO3"); + regulator_enable(usbh2_regux); + ((struct fsl_usb2_platform_data *)dev->platform_data)-> + xcvr_pwr->regu2 = usbh2_regux; +} +EXPORT_SYMBOL(usbh2_get_xcvr_power); + +void usbh2_put_xcvr_power(struct device *dev) +{ + struct regulator *usbh2_regux; + + usbh2_regux = ((struct fsl_usb2_platform_data *)dev-> + platform_data)->xcvr_pwr->regu2; + regulator_disable(usbh2_regux); + regulator_put(usbh2_regux); + + usbh2_regux = ((struct fsl_usb2_platform_data *)dev-> + platform_data)->xcvr_pwr->regu1; + regulator_disable(usbh2_regux); + regulator_put(usbh2_regux); +} +EXPORT_SYMBOL(usbh2_put_xcvr_power); + +static int __init usbh2_init(void) +{ + pr_debug("%s: \n", __func__); + + host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources), + &usbh2_config); + return 0; +} +module_init(usbh2_init); diff --git a/arch/arm/mach-mx28/Kconfig b/arch/arm/mach-mx28/Kconfig new file mode 100644 index 000000000000..dc1d8b115869 --- /dev/null +++ b/arch/arm/mach-mx28/Kconfig @@ -0,0 +1,25 @@ +choice + prompt "Select i.MXS board type" + +config MACH_MX28EVK + bool "Freescale MX28 EVK board" + depends on ARCH_MX28 + select USB_ARCH_HAS_EHCI + +endchoice + +config VECTORS_PHY_ADDR + int "vectors address" + default 0 + help + This config set vectors table is located which physical address + +config MXS_TIMER_WITH_MACH + bool "System Timer support Compare Match interrupt" + default y + +config MEM_mDDR + bool "Memory type is mDDR" + depends on ARCH_MX28 + help + Say Y to select mDDR memory diff --git a/arch/arm/mach-mx28/Makefile b/arch/arm/mach-mx28/Makefile new file mode 100644 index 000000000000..23869ad9cbbc --- /dev/null +++ b/arch/arm/mach-mx28/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the linux kernel. +# +obj-y += pinctrl.o clock.o device.o serial.o power.o bus_freq.o pm.o sleep.o + +# Board select +obj-$(CONFIG_MACH_MX28EVK) += mx28evk.o mx28evk_pins.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_MXS_RAM_FREQ_SCALING) +=emi.o emi_settings.o + +# USB support +ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) + obj-y += usb_dr.o +endif +obj-$(CONFIG_USB_EHCI_ARC_H1) += usb_h1.o diff --git a/arch/arm/mach-mx28/Makefile.boot b/arch/arm/mach-mx28/Makefile.boot new file mode 100644 index 000000000000..1568ad404d59 --- /dev/null +++ b/arch/arm/mach-mx28/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x40008000 +params_phys-y := 0x40000100 +initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-mx28/bus_freq.c b/arch/arm/mach-mx28/bus_freq.c new file mode 100644 index 000000000000..920c6309e886 --- /dev/null +++ b/arch/arm/mach-mx28/bus_freq.c @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file bus_freq.c + * + * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "regs-clkctrl.h" +#include "regs-digctl.h" + +#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +#ifdef CONFIG_MEM_mDDR +struct profile profiles[] = { + { 454736, 151570, 205710, 0, 1550000, + 1450000, 355000, 3300000, 1750000, 24000, 0 }, + { 360000, 120000, 130910, 0, 1350000, + 1250000, 200000, 3300000, 1750000, 24000, 0 }, + { 261818, 130910, 130910, 0, 1350000, + 1250000, 173000, 3300000, 1750000, 24000, 0 }, + { 64000, 64000, 240000, 3, 1350000, + 1250000, 150000, 3300000, 1750000, 24000, 0 }, + { 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 }, +}; +#else +struct profile profiles[] = { + { 454736, 151570, 205710, 0, 1550000, + 1450000, 355000, 3300000, 1750000, 24000, 0 }, + { 360000, 120000, 130910, 0, 1350000, + 1250000, 200000, 3300000, 1750000, 24000, 0 }, + { 261818, 130910, 130910, 0, 1350000, + 1250000, 173000, 3300000, 1750000, 24000, 0 }, + { 64000, 64000, 130910, 3, 1350000, + 1250000, 150000, 3300000, 1750000, 24000, 0 }, + { 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 }, +}; +#endif +static struct device *busfreq_dev; +static struct clk *usb_clk0; +static struct clk *usb_clk1; +static struct clk *lcdif_clk; +u32 clkseq_setting; + +int low_freq_used(void) +{ + if ((clk_get_usecount(usb_clk0) == 0) + && (clk_get_usecount(usb_clk1) == 0) + && (clk_get_usecount(lcdif_clk) == 0)) + return 1; + else + return 0; +} + +int is_hclk_autoslow_ok(void) +{ + if ((clk_get_usecount(usb_clk0) == 0) + && (clk_get_usecount(usb_clk1) == 0)) + return 1; + else + return 0; +} + +int timing_ctrl_rams(int ss) +{ + __raw_writel(BF(ss, DIGCTL_ARMCACHE_VALID_SS) | + BF(ss, DIGCTL_ARMCACHE_DRTY_SS) | + BF(ss, DIGCTL_ARMCACHE_CACHE_SS) | + BF(ss, DIGCTL_ARMCACHE_DTAG_SS) | + BF(ss, DIGCTL_ARMCACHE_ITAG_SS), + DIGCTRL_BASE_ADDR + HW_DIGCTL_ARMCACHE); + return 0; +} + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit busfreq_probe(struct platform_device *pdev) +{ + int ret = 0; + + busfreq_dev = &pdev->dev; + + usb_clk0 = clk_get(NULL, "usb_clk0"); + if (IS_ERR(usb_clk0)) { + ret = PTR_ERR(usb_clk0); + goto out_usb0; + } + + usb_clk1 = clk_get(NULL, "usb_clk1"); + if (IS_ERR(usb_clk1)) { + ret = PTR_ERR(usb_clk1); + goto out_usb1; + } + + lcdif_clk = clk_get(NULL, "dis_lcdif"); + if (IS_ERR(lcdif_clk)) { + ret = PTR_ERR(lcdif_clk); + goto out_lcd; + } + return 0; + +out_lcd: + clk_put(usb_clk1); +out_usb1: + clk_put(usb_clk0); +out_usb0: + return ret; +} + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "busfreq", + }, + .probe = busfreq_probe, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ + if (platform_driver_register(&busfreq_driver) != 0) { + printk(KERN_ERR "busfreq_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "Bus freq driver module loaded\n"); + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx28/clock.c b/arch/arm/mach-mx28/clock.c new file mode 100644 index 000000000000..9797d1f650d9 --- /dev/null +++ b/arch/arm/mach-mx28/clock.c @@ -0,0 +1,1818 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "regs-clkctrl.h" +#include "regs-digctl.h" +#include "emi_settings.h" + +#define HW_SAIF_CTRL (0x00000000) +#define HW_SAIF_STAT (0x00000010) +#define SAIF0_CTRL (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_CTRL) +#define SAIF0_STAT (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_STAT) +#define SAIF1_CTRL (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_CTRL) +#define SAIF1_STAT (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_STAT) +#define BM_SAIF_CTRL_RUN 0x00000001 +#define BM_SAIF_STAT_BUSY 0x00000001 +#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) + +/* external clock input */ +static struct clk xtal_clk[]; +static unsigned long xtal_clk_rate[3] = { 24000000, 24000000, 32000 }; + +static unsigned long enet_mii_phy_rate; + +static inline int clk_is_busy(struct clk *clk) +{ + return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits); +} + +static bool mx28_enable_h_autoslow(bool enable) +{ + bool currently_enabled; + + if (__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS) & + BM_CLKCTRL_HBUS_ASM_ENABLE) + currently_enabled = true; + else + currently_enabled = false; + + if (enable) + __raw_writel(BM_CLKCTRL_HBUS_ASM_ENABLE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); + else + __raw_writel(BM_CLKCTRL_HBUS_ASM_ENABLE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); + return currently_enabled; +} + + +static void mx28_set_hbus_autoslow_flags(u16 mask) +{ + u32 reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= 0xFFFF; + reg |= mask << 16; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); +} + +static int mx28_raw_enable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg &= ~clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } + return 0; +} + +static void mx28_raw_disable(struct clk *clk) +{ + unsigned int reg; + if (clk->enable_reg) { + reg = __raw_readl(clk->enable_reg); + reg |= clk->enable_bits; + __raw_writel(reg, clk->enable_reg); + } +} + +static unsigned int +mx28_get_frac_div(unsigned long root_rate, unsigned long rate, unsigned mask) +{ + unsigned long mult_rate; + unsigned int div; + mult_rate = rate * (mask + 1); + div = mult_rate / root_rate; + if ((mult_rate % root_rate) && (div < mask)) + div--; + return div; +} + +static unsigned long xtal_get_rate(struct clk *clk) +{ + int id = clk - xtal_clk; + return xtal_clk_rate[id]; +} + +static struct clk xtal_clk[] = { + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, + { + .flags = RATE_FIXED, + .get_rate = xtal_get_rate, + }, +}; + +static struct clk ref_xtal_clk = { + .parent = &xtal_clk[0], +}; + +static unsigned long pll_get_rate(struct clk *clk); +static int pll_enable(struct clk *clk); +static void pll_disable(struct clk *clk); +static int pll_set_rate(struct clk *clk, unsigned long rate); +static struct clk pll_clk[] = { + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .set_rate = pll_set_rate, + .enable = pll_enable, + .disable = pll_disable, + }, + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .set_rate = pll_set_rate, + .enable = pll_enable, + .disable = pll_disable, + }, + { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .get_rate = pll_get_rate, + .set_rate = pll_set_rate, + .enable = pll_enable, + .disable = pll_disable, + } +}; + +static unsigned long pll_get_rate(struct clk *clk) +{ + unsigned int reg; + if (clk == (pll_clk + 2)) + return 50000000; + if (clk == pll_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL1); + reg = (reg & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) >> + BP_CLKCTRL_PLL0CTRL0_DIV_SEL; + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL1); + reg = (reg & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) >> + BP_CLKCTRL_PLL1CTRL0_DIV_SEL; + } + switch (reg) { + case 0: + return 480000000; + case 1: + return 384000000; + case 2: + return 288000000; + default: + return -EINVAL; + } +} + +static int pll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div, reg; + + if (clk == pll_clk + 2) + return -EINVAL; + + switch (rate) { + case 480000000: + div = 0; + break; + case 384000000: + div = 1; + break; + case 288000000: + div = 2; + break; + default: + return -EINVAL; + } + if (clk == pll_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL1); + reg &= ~BM_CLKCTRL_PLL0CTRL0_DIV_SEL; + reg |= BF_CLKCTRL_PLL0CTRL0_DIV_SEL(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL1); + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL1); + reg &= ~BM_CLKCTRL_PLL1CTRL0_DIV_SEL; + reg |= BF_CLKCTRL_PLL1CTRL0_DIV_SEL(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL1); + } + return 0; +} + +static int pll_enable(struct clk *clk) +{ + int timeout = 100; + unsigned long reg; + switch (clk - pll_clk) { + case 0: + __raw_writel(BM_CLKCTRL_PLL0CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL0_SET); + do { + udelay(10); + reg = __raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_PLL0CTRL1); + timeout--; + } while ((timeout > 0) && !(reg & BM_CLKCTRL_PLL0CTRL1_LOCK)); + if (timeout <= 0) + return -EFAULT; + return 0; + case 1: + __raw_writel(BM_CLKCTRL_PLL1CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL0_SET); + do { + udelay(10); + reg = __raw_readl(CLKCTRL_BASE_ADDR + + HW_CLKCTRL_PLL1CTRL1); + timeout--; + } while ((timeout > 0) && !(reg & BM_CLKCTRL_PLL1CTRL1_LOCK)); + if (timeout <= 0) + return -EFAULT; + return 0; + case 2: + __raw_writel(BM_CLKCTRL_PLL2CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_SET); + udelay(10); + __raw_writel(BM_CLKCTRL_PLL2CTRL0_CLKGATE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_CLR); + break; + } + return -ENODEV; +} + +static void pll_disable(struct clk *clk) +{ + switch (clk - pll_clk) { + case 0: + __raw_writel(BM_CLKCTRL_PLL0CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL0_CLR); + return; + case 1: + __raw_writel(BM_CLKCTRL_PLL1CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL0_CLR); + return; + case 2: + __raw_writel(BM_CLKCTRL_PLL2CTRL0_CLKGATE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_SET); + __raw_writel(BM_CLKCTRL_PLL2CTRL0_POWER, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL2CTRL0_CLR); + break; + } + return; +} + +static inline unsigned long +ref_clk_get_rate(unsigned long base, unsigned int div) +{ + unsigned long rate = base / 1000; + return 1000 * ((rate * 18) / div); +} + +static unsigned long ref_clk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long base = clk->parent->get_rate(clk->parent); + unsigned long div = (base * 18) / rate; + return (base / div) * 18; +} + +static int ref_clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long base = clk->parent->get_rate(clk->parent); + unsigned long div = ((base/1000) * 18) / (rate/1000); + if (rate != ((base / div) * 18)) + return -EINVAL; + if (clk->scale_reg == 0) + return -EINVAL; + base = __raw_readl(clk->scale_reg); + base &= ~(0x3F << clk->scale_bits); + base |= (div << clk->scale_bits); + __raw_writel(base, clk->scale_reg); + return 0; +} + +static unsigned long ref_cpu_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_CPUFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + + +static struct clk ref_cpu_clk = { + .parent = &pll_clk[0], + .get_rate = ref_cpu_get_rate, + .round_rate = ref_clk_round_rate, + .set_rate = ref_clk_set_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATECPU, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .scale_bits = BP_CLKCTRL_FRAC0_CPUFRAC, +}; + +static unsigned long ref_emi_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_EMIFRAC; + reg >>= BP_CLKCTRL_FRAC0_EMIFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_emi_clk = { + .parent = &pll_clk[0], + .get_rate = ref_emi_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEEMI, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .scale_bits = BP_CLKCTRL_FRAC0_EMIFRAC, +}; + +static unsigned long ref_io_get_rate(struct clk *clk); +static struct clk ref_io_clk[] = { + { + .parent = &pll_clk[0], + .get_rate = ref_io_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEIO0, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .scale_bits = BP_CLKCTRL_FRAC0_IO0FRAC, + }, + { + .parent = &pll_clk[0], + .get_rate = ref_io_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .enable_bits = BM_CLKCTRL_FRAC0_CLKGATEIO1, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .scale_bits = BP_CLKCTRL_FRAC0_IO1FRAC, + }, +}; + +static unsigned long ref_io_get_rate(struct clk *clk) +{ + unsigned int reg; + if (clk == ref_io_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_IO0FRAC; + reg >>= BP_CLKCTRL_FRAC0_IO0FRAC; + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0) & + BM_CLKCTRL_FRAC0_IO1FRAC; + reg >>= BP_CLKCTRL_FRAC0_IO1FRAC; + } + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static unsigned long ref_pix_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_PIXFRAC; + reg >>= BP_CLKCTRL_FRAC1_PIXFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_pix_clk = { + .parent = &pll_clk[0], + .get_rate = ref_pix_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEPIX, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .scale_bits = BP_CLKCTRL_FRAC1_PIXFRAC, +}; + +static unsigned long ref_hsadc_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_HSADCFRAC; + reg >>= BP_CLKCTRL_FRAC1_HSADCFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_hsadc_clk = { + .parent = &pll_clk[0], + .get_rate = ref_hsadc_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEHSADC, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .scale_bits = BP_CLKCTRL_FRAC1_HSADCFRAC, +}; + +static unsigned long ref_gpmi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1) & + BM_CLKCTRL_FRAC1_GPMIFRAC; + reg >>= BP_CLKCTRL_FRAC1_GPMIFRAC; + return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg); +} + +static struct clk ref_gpmi_clk = { + .parent = &pll_clk[0], + .get_rate = ref_gpmi_get_rate, + .set_rate = ref_clk_set_rate, + .round_rate = ref_clk_round_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEGPMI, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .scale_bits = BP_CLKCTRL_FRAC1_GPMIFRAC, +}; + +static unsigned long cpu_get_rate(struct clk *clk) +{ + unsigned long rate, div; + rate = (clk->parent->get_rate(clk->parent)); + div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU) & + BM_CLKCTRL_CPU_DIV_CPU; + rate = rate/div; + return rate; + } + +static unsigned long cpu_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long frac_rate, root_rate = clk->parent->get_rate(clk->parent); + unsigned int div = root_rate / rate; + if (div == 0) + return root_rate; + if (clk->parent == &ref_cpu_clk) { + if (div > 0x3F) + div = 0x3F; + return root_rate / div; + } + + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return root_rate; + if (frac_rate == 0) + return rate; + return rate; +} + +static struct clk h_clk; +static int cpu_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate = + clk->parent->parent->get_rate(clk->parent->parent); + int i; + u32 clkctrl_cpu = 1; + u32 c = clkctrl_cpu; + u32 clkctrl_frac = 1; + u32 val; + u32 reg_val, hclk_reg; + + if (rate < 24000) + return -EINVAL; + else if (rate == 24000) { + /* switch to the 24M source */ + clk_set_parent(clk, &ref_xtal_clk); + } else { + for ( ; c < 0x40; c++) { + u32 f = ((root_rate/1000)*18/c + (rate/1000)/2) / + (rate/1000); + int s1, s2; + + if (f < 18 || f > 35) + continue; + s1 = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu - + (rate/1000); + s2 = (root_rate/1000)*18/c/f - (rate/1000); + if (abs(s1) > abs(s2)) { + clkctrl_cpu = c; + clkctrl_frac = f; + } + if (s2 == 0) + break; + }; + if (c == 0x40) { + int d = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu - + (rate/1000); + if ((abs(d) > 100) || (clkctrl_frac < 18) || + (clkctrl_frac > 35)) + return -EINVAL; + } + + /* Set safe hbus clock divider. A divider of 3 ensure that + * the Vddd voltage required for the cpuclk is sufficiently + * high for the hbus clock. + */ + hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + if ((hclk_reg & BP_CLKCTRL_HBUS_DIV) != 3) { + hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV); + hclk_reg |= BF_CLKCTRL_HBUS_DIV(3); + + /* change hclk divider to safe value for any ref_cpu + * value. + */ + __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + + HW_CLKCTRL_HBUS); + } + + for (i = 10000; i; i--) + if (!clk_is_busy(&h_clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up HCLK divisor\n"); + return -ETIMEDOUT; + } + + /* Set Frac div */ + val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); + val &= ~(BM_CLKCTRL_FRAC0_CPUFRAC << BP_CLKCTRL_FRAC0_CPUFRAC); + val |= clkctrl_frac; + __raw_writel(val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); + /* Do not gate */ + __raw_writel(BM_CLKCTRL_FRAC0_CLKGATECPU, CLKCTRL_BASE_ADDR + + HW_CLKCTRL_FRAC0_CLR); + + /* write clkctrl_cpu */ + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + reg_val &= ~0x3F; + reg_val |= clkctrl_cpu; + + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); + + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up CPU divisor\n"); + return -ETIMEDOUT; + } + } + return 0; +} + +static int cpu_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + + if (clk->bypass_reg) { + if (parent == clk->parent) + return 0; + if (parent == &ref_xtal_clk) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + ret = 0; + } + if (ret && (parent == &ref_cpu_clk)) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + ret = 0; + } + if (!ret) + clk->parent = parent; + } + return ret; +} + +static struct clk cpu_clk = { + .parent = &ref_cpu_clk, + .get_rate = cpu_get_rate, + .round_rate = cpu_round_rate, + .set_rate = cpu_set_rate, + .set_parent = cpu_set_parent, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 18, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .busy_bits = 28, +}; + +static unsigned long uart_get_rate(struct clk *clk) +{ + unsigned int div; + div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL) & + BM_CLKCTRL_XTAL_DIV_UART; + return clk->parent->get_rate(clk->parent) / div; +} + +static struct clk uart_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_UART_CLK_GATE, + .get_rate = uart_get_rate, +}; + +static struct clk pwm_clk = { + .parent = &ref_xtal_clk, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_PWM_CLK24M_GATE, +}; + +static unsigned long clk_32k_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 750; +} + +static struct clk clk_32k = { + .parent = &ref_xtal_clk, + .flags = RATE_FIXED, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL, + .enable_bits = BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE, + .get_rate = clk_32k_get_rate, +}; + +static unsigned long lradc_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 16; +} + +static struct clk lradc_clk = { + .parent = &clk_32k, + .flags = RATE_FIXED, + .get_rate = lradc_get_rate, +}; + +static unsigned long x_get_rate(struct clk *clk) +{ + unsigned long reg, div; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + div = reg & BM_CLKCTRL_XBUS_DIV; + if (!(reg & BM_CLKCTRL_XBUS_DIV_FRAC_EN)) + return clk->parent->get_rate(clk->parent) / div; + return (clk->parent->get_rate(clk->parent) / 0x400) * div; +} + +static unsigned long x_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return root_rate; + if (frac_rate == 0) + return rate; + return rate; +} + +static int x_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return -EINVAL; + + if (root_rate % rate) { + div = mx28_get_frac_div(root_rate / 1000, rate / 1000, 0x3FF); + if (((root_rate / 0x400) * div) > rate) + return -EINVAL; + } + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + reg &= ~(BM_CLKCTRL_XBUS_DIV | BM_CLKCTRL_XBUS_DIV_FRAC_EN); + if (root_rate % rate) + reg |= BM_CLKCTRL_XBUS_DIV_FRAC_EN; + reg |= BF_CLKCTRL_XBUS_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + return 0; +} + +static struct clk x_clk = { + .parent = &ref_xtal_clk, + .get_rate = x_get_rate, + .set_rate = x_set_rate, + .round_rate = x_round_rate, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS, + .scale_bits = BM_CLKCTRL_XBUS_BUSY, +}; + +static struct clk ana_clk = { + .parent = &ref_xtal_clk, +}; + +static unsigned long rtc_get_rate(struct clk *clk) +{ + if (clk->parent == &xtal_clk[2]) + return clk->parent->get_rate(clk->parent); + return clk->parent->get_rate(clk->parent) / 768; +} + +static struct clk rtc_clk = { + .parent = &ref_xtal_clk, + .get_rate = rtc_get_rate, +}; + +static struct clk flexcan_clk[] = { + { + .parent = &ref_xtal_clk, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FLEXCAN, + .enable_bits = BM_CLKCTRL_FLEXCAN_STOP_CAN0, + }, + { + .parent = &ref_xtal_clk, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FLEXCAN, + .enable_bits = BM_CLKCTRL_FLEXCAN_STOP_CAN1, + }, +}; + +static unsigned long h_get_rate(struct clk *clk) +{ + unsigned long reg, div; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + div = reg & BM_CLKCTRL_HBUS_DIV; + return clk->parent->get_rate(clk->parent) / div; +} + +static unsigned long h_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x20)) + return root_rate; + if (frac_rate < (rate / 2)) + return rate; + else + return root_rate / (div + 1); +} + +static int h_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned long round_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + round_rate = h_round_rate(clk, rate); + div = root_rate / round_rate; + if ((div == 0) || (div >= 0x20)) + return -EINVAL; + + if (root_rate % round_rate) + return -EINVAL; + + if ((root_rate < rate) && (root_rate == 64000000)) + div = 3; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | BM_CLKCTRL_HBUS_DIV); + reg |= BF_CLKCTRL_HBUS_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up AHB divisor\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + +static struct clk h_clk = { + .parent = &cpu_clk, + .get_rate = h_get_rate, + .set_rate = h_set_rate, + .round_rate = h_round_rate, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS, + .busy_bits = 31, +}; + +static struct clk ocrom_clk = { + .parent = &h_clk, +}; + +static unsigned long emi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI); + if (clk->parent == &ref_emi_clk) + reg = (reg & BM_CLKCTRL_EMI_DIV_EMI); + else + reg = (reg & BM_CLKCTRL_EMI_DIV_XTAL) >> + BP_CLKCTRL_EMI_DIV_XTAL; + return clk->parent->get_rate(clk->parent) / reg; +} + +static int emi_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + if (clk->bypass_reg) { + if (parent == clk->parent) + return 0; + if (parent == &ref_xtal_clk) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + ret = 0; + } + if (ret && (parent == &ref_emi_clk)) { + __raw_writel(0 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + ret = 0; + } + if (!ret) + clk->parent = parent; + } + return ret; +} + +static unsigned long emi_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate = clk->parent->get_rate(clk->parent); + unsigned int div = root_rate / rate; + if (div == 0) + return root_rate; + if (clk->parent == &ref_emi_clk) { + if (div > 0x3F) + div = 0x3F; + return root_rate / div; + } + if (div > 0xF) + div = 0xF; + return root_rate / div; +} + +static int emi_set_rate(struct clk *clk, unsigned long rate) +{ + int i; + struct mxs_emi_scaling_data emi; + unsigned long iram_phy; + void (*f) (struct mxs_emi_scaling_data *, unsigned int *); + f = iram_alloc((unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale, &iram_phy); + if (NULL == f) { + pr_err("%s Not enough iram\n", __func__); + return -ENOMEM; + } + memcpy(f, mxs_ram_freq_scale, + (unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale); +#ifdef CONFIG_MEM_mDDR + if (rate <= 24000000) { + emi.emi_div = 20; + emi.frac_div = 18; + emi.new_freq = 24; + mDDREmiController_24MHz(); + } else if (rate <= 133000000) { + emi.emi_div = 3; + emi.frac_div = 22; + emi.new_freq = 133; + mDDREmiController_133MHz(); + } else { + emi.emi_div = 2; + emi.frac_div = 22; + emi.new_freq = 200; + mDDREmiController_200MHz(); + } +#else + if (rate <= 133000000) { + emi.emi_div = 3; + emi.frac_div = 22; + emi.new_freq = 133; + DDR2EmiController_EDE1116_133MHz(); + } else if (rate <= 166000000) { + emi.emi_div = 2; + emi.frac_div = 27; + emi.new_freq = 166; + DDR2EmiController_EDE1116_166MHz(); + } else { + emi.emi_div = 2; + emi.frac_div = 22; + emi.new_freq = 200; + DDR2EmiController_EDE1116_200MHz(); + } +#endif + + local_irq_disable(); + local_fiq_disable(); + f(&emi, get_current_emidata()); + local_fiq_enable(); + local_irq_enable(); + iram_free(iram_phy, + (unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale); + + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + + if (!i) { + printk(KERN_ERR "couldn't set up EMI divisor\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static struct clk emi_clk = { + .parent = &ref_emi_clk, + .get_rate = emi_get_rate, + .set_rate = emi_set_rate, + .round_rate = emi_round_rate, + .set_parent = emi_set_parent, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, + .enable_bits = BM_CLKCTRL_EMI_CLKGATE, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, + .busy_bits = 28, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 7, +}; + +static unsigned long ssp_get_rate(struct clk *clk); + +static int ssp_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + int div = (clk_get_rate(clk->parent) + rate - 1) / rate; + u32 reg_frac; + const int mask = 0x1FF; + int try = 10; + int i = -1; + + if (div == 0 || div > mask) + goto out; + + reg_frac = __raw_readl(clk->scale_reg); + reg_frac &= ~(mask << clk->scale_bits); + + while (try--) { + __raw_writel(reg_frac | (div << clk->scale_bits), + clk->scale_reg); + + if (clk->busy_reg) { + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + } + if (i) + break; + } + + if (!i) + ret = -ETIMEDOUT; + else + ret = 0; + +out: + if (ret != 0) + pr_err("%s: error %d\n", __func__, ret); + return ret; +} + +static int ssp_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + + if (clk->bypass_reg) { + if (clk->parent == parent) + return 0; + if (parent == &ref_io_clk[0] || parent == &ref_io_clk[1]) + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + else + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + clk->parent = parent; + ret = 0; + } + + return ret; +} + +static struct clk ssp_clk[] = { + { + .parent = &ref_io_clk[0], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0, + .enable_bits = BM_CLKCTRL_SSP0_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 3, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, + { + .parent = &ref_io_clk[0], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1, + .enable_bits = BM_CLKCTRL_SSP1_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 4, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, + { + .parent = &ref_io_clk[1], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .enable_bits = BM_CLKCTRL_SSP2_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 5, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, + { + .parent = &ref_io_clk[1], + .get_rate = ssp_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .enable_bits = BM_CLKCTRL_SSP3_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 6, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, + }, +}; + +static unsigned long ssp_get_rate(struct clk *clk) +{ + unsigned int reg, div; + switch (clk - ssp_clk) { + case 0: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0); + div = reg & BM_CLKCTRL_SSP0_DIV; + reg &= BM_CLKCTRL_SSP0_DIV_FRAC_EN; + break; + case 1: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1); + div = reg & BM_CLKCTRL_SSP1_DIV; + reg &= BM_CLKCTRL_SSP1_DIV_FRAC_EN; + break; + case 2: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2); + div = reg & BM_CLKCTRL_SSP2_DIV; + reg &= BM_CLKCTRL_SSP2_DIV_FRAC_EN; + break; + case 3: + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3); + div = reg & BM_CLKCTRL_SSP3_DIV; + reg &= BM_CLKCTRL_SSP3_DIV_FRAC_EN; + break; + default: + return 0; + } + if (!reg) + return clk->parent->get_rate(clk->parent) / div; + return (clk->parent->get_rate(clk->parent) / 0x200) / div; +} + +static unsigned long lcdif_get_rate(struct clk *clk) +{ + long rate = clk->parent->get_rate(clk->parent); + long div; + + div = __raw_readl(clk->scale_reg); + if (!(div & BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN)) { + div = (div >> clk->scale_bits) & BM_CLKCTRL_DIS_LCDIF_DIV; + return rate / (div ? div : 1); + } + + div = (div >> clk->scale_bits) & BM_CLKCTRL_DIS_LCDIF_DIV; + rate /= (BM_CLKCTRL_DIS_LCDIF_DIV >> clk->scale_bits) + 1; + rate *= div; + return rate; +} + +static int lcdif_set_rate(struct clk *clk, unsigned long rate) +{ + int reg_val; + + reg_val = __raw_readl(clk->scale_reg); + reg_val &= ~(BM_CLKCTRL_DIS_LCDIF_DIV | BM_CLKCTRL_DIS_LCDIF_CLKGATE); + reg_val |= (1 << BP_CLKCTRL_DIS_LCDIF_DIV) & BM_CLKCTRL_DIS_LCDIF_DIV; + __raw_writel(reg_val, clk->scale_reg); + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) + return -ETIMEDOUT; + } + + reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + reg_val |= BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF; + __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + + return 0; +} + +static int lcdif_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + if (clk->bypass_reg) { + if (parent == clk->parent) + return 0; + if (parent == &ref_xtal_clk) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + ret = 0; + } + if (ret && (parent == &ref_pix_clk)) { + __raw_writel(0 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + ret = 0; + } + if (!ret) + clk->parent = parent; + } + return ret; +} + +static struct clk dis_lcdif_clk = { + .parent = &pll_clk[0], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .scale_bits = 0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .busy_bits = 29, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF, + .enable_bits = 31, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 14, + .get_rate = lcdif_get_rate, + .set_rate = lcdif_set_rate, + .set_parent = lcdif_set_parent, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long hsadc_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HSADC); + reg = (reg & BM_CLKCTRL_HSADC_FREQDIV) >> BP_CLKCTRL_HSADC_FREQDIV; + return clk->parent->get_rate(clk->parent) / ((1 << reg) * 9); +} + +static int hsadc_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg = clk->parent->get_rate(clk->parent); + if ((reg / rate) % 9) + return -EINVAL; + reg = reg / 9; + switch (reg) { + case 1: + reg = BM_CLKCTRL_HSADC_RESETB; + break; + case 2: + reg = 1 | BM_CLKCTRL_HSADC_RESETB; + break; + case 4: + reg = 2 | BM_CLKCTRL_HSADC_RESETB; + break; + case 8: + reg = 3 | BM_CLKCTRL_HSADC_RESETB; + break; + default: + return -EINVAL; + } + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HSADC); + return 0; +} + +static unsigned long hsadc_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int div; + unsigned int reg = clk->parent->get_rate(clk->parent); + div = ((reg / rate) + 8) / 9; + if (div <= 1) + return reg; + if (div > 4) + return reg >> 3; + if (div > 2) + return reg >> 2; + return reg >> 1; +} + +static struct clk hsadc_clk = { + .parent = &ref_hsadc_clk, + .get_rate = hsadc_get_rate, + .set_rate = hsadc_set_rate, + .round_rate = hsadc_round_rate, +}; + +static unsigned long gpmi_get_rate(struct clk *clk) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) & + BM_CLKCTRL_GPMI_DIV; + return clk->parent->get_rate(clk->parent) / reg; +} + +static int gpmi_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + if (clk->bypass_reg) { + if (parent == clk->parent) + return 0; + if (parent == &ref_xtal_clk) { + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + ret = 0; + } + if (ret && (parent == &ref_gpmi_clk)) { + __raw_writel(0 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + ret = 0; + } + if (!ret) + clk->parent = parent; + } + return ret; +} + +static unsigned long gpmi_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return root_rate; + if (frac_rate == 0) + return rate; + return rate; +} + +static int gpmi_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + div = root_rate / rate; + if ((div == 0) || (div >= 0x400)) + return -EINVAL; + + if (root_rate % rate) { + div = mx28_get_frac_div(root_rate / 1000, rate / 1000, 0x3FF); + if (((root_rate / 0x400) * div) > rate) + return -EINVAL; + } + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + reg &= ~(BM_CLKCTRL_GPMI_DIV | BM_CLKCTRL_GPMI_DIV_FRAC_EN); + if (root_rate % rate) + reg |= BM_CLKCTRL_GPMI_DIV_FRAC_EN; + reg |= BF_CLKCTRL_GPMI_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + + do { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); + } while (reg & BM_CLKCTRL_GPMI_BUSY); + return 0; +} + +static struct clk gpmi_clk = { + .parent = &ref_gpmi_clk, + .set_parent = gpmi_set_parent, + .get_rate = gpmi_get_rate, + .set_rate = gpmi_set_rate, + .round_rate = gpmi_round_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .enable_bits = BM_CLKCTRL_GPMI_CLKGATE, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 2, +}; + +static unsigned long saif_get_rate(struct clk *clk); +static unsigned long saif_set_rate(struct clk *clk, unsigned int rate); +static unsigned long saif_set_parent(struct clk *clk, struct clk *parent); + +static struct clk saif_clk[] = { + { + .parent = &pll_clk[0], + .get_rate = saif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0, + .enable_bits = BM_CLKCTRL_SAIF0_CLKGATE, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0, + .scale_bits = 0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0, + .busy_bits = 29, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 0, + .set_rate = saif_set_rate, + .set_parent = saif_set_parent, + }, + { + .parent = &pll_clk[0], + .get_rate = saif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1, + .enable_bits = BM_CLKCTRL_SAIF1_CLKGATE, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1, + .scale_bits = 0, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1, + .busy_bits = 29, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 1, + .set_rate = saif_set_rate, + .set_parent = saif_set_parent, + }, +}; + +static unsigned long saif_get_rate(struct clk *clk) +{ + unsigned long reg, div; + if (clk == saif_clk) { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); + div = reg & BM_CLKCTRL_SAIF0_DIV; + reg &= BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + } else { + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); + div = reg & BM_CLKCTRL_SAIF1_DIV; + reg &= BM_CLKCTRL_SAIF1_DIV_FRAC_EN; + } + if (!reg) + return clk->parent->get_rate(clk->parent) / div; + return (clk->parent->get_rate(clk->parent) / 0x10000) * div; +} + +static unsigned long saif_set_rate(struct clk *clk, unsigned int rate) +{ + u16 div = 0; + u32 clkctrl_saif; + u64 rates; + struct clk *parent = clk->parent; + + pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, + clk_get_rate(parent)); + + if (rate > clk_get_rate(parent)) + return -EINVAL; + /*saif clock always use frac div*/ + rates = 65536 * (u64)rate; + rates = rates + (u64)(clk_get_rate(parent) / 2); + do_div(rates, clk_get_rate(parent)); + div = rates; + + pr_debug("%s: div calculated is %d\n", __func__, div); + if (!div) + return -EINVAL; + + clkctrl_saif = __raw_readl(clk->scale_reg); + clkctrl_saif &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + clkctrl_saif &= ~BM_CLKCTRL_SAIF0_DIV; + clkctrl_saif |= div; + clkctrl_saif |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + clkctrl_saif &= ~BM_CLKCTRL_SAIF0_CLKGATE; + __raw_writel(clkctrl_saif, clk->scale_reg); + if (clk->busy_reg) { + int i; + for (i = 10000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) { + pr_err("couldn't set up SAIF clk divisor\n"); + return -ETIMEDOUT; + } + } + return 0; +} + +static unsigned long saif_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + int shift = 4; + /*bypass*/ + if (parent == &pll_clk[0]) + shift = 8; + if (clk->bypass_reg) { + __raw_writel(1 << clk->bypass_bits, clk->bypass_reg + shift); + ret = 0; + } + return ret; +} + +static int saif_mclk_enable(struct clk *clk) +{ + /*Check if enabled already*/ + if (__raw_readl(clk->busy_reg) & clk->busy_bits) + return 0; + /*Enable saif to enable mclk*/ + __raw_writel(0x1, clk->enable_reg); + mdelay(1); + __raw_writel(0x1, clk->enable_reg); + mdelay(1); + return 0; +} + +static int saif_mclk_disable(struct clk *clk) +{ + /*Check if disabled already*/ + if (!(__raw_readl(clk->busy_reg) & clk->busy_bits)) + return 0; + /*Disable saif to disable mclk*/ + __raw_writel(0x0, clk->enable_reg); + mdelay(1); + __raw_writel(0x0, clk->enable_reg); + mdelay(1); + return 0; +} + +static struct clk saif_mclk[] = { + { + .parent = &saif_clk[0], + .enable = saif_mclk_enable, + .disable = saif_mclk_disable, + .enable_reg = SAIF0_CTRL, + .enable_bits = BM_SAIF_CTRL_RUN, + .busy_reg = SAIF0_STAT, + .busy_bits = BM_SAIF_STAT_BUSY, + }, + { + .parent = &saif_clk[1], + .enable = saif_mclk_enable, + .disable = saif_mclk_disable, + .enable_reg = SAIF1_CTRL, + .enable_bits = BM_SAIF_CTRL_RUN, + .busy_reg = SAIF1_STAT, + .busy_bits = BM_SAIF_STAT_BUSY, + }, +}; + +static unsigned long pcmspdif_get_rate(struct clk *clk) +{ + return clk->parent->get_rate(clk->parent) / 4; +} + +static struct clk pcmspdif_clk = { + .parent = &pll_clk[0], + .get_rate = pcmspdif_get_rate, + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SPDIF, + .enable_bits = BM_CLKCTRL_SPDIF_CLKGATE, +}; + +/* usb_clk for usb0 */ +static struct clk usb_clk0 = { + .parent = &pll_clk[0], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL, + .enable_bits = BM_DIGCTL_CTRL_USB0_CLKGATE, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +/* usb_clk for usb1 */ +static struct clk usb_clk1 = { + .parent = &pll_clk[1], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL, + .enable_bits = BM_DIGCTL_CTRL_USB1_CLKGATE, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +/* usb phy clock for usb0 */ +static struct clk usb_phy_clk0 = { + .parent = &pll_clk[0], + .enable = mx28_raw_disable, /* EN_USB_CLKS = 1 means ON */ + .disable = mx28_raw_enable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL0CTRL0_SET, + .enable_bits = BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +/* usb phy clock for usb1 */ +static struct clk usb_phy_clk1 = { + .parent = &pll_clk[1], + .enable = mx28_raw_disable, + .disable = mx28_raw_enable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLL1CTRL0_SET, + .enable_bits = BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS, + .flags = CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk enet_out_clk = { + .parent = &pll_clk[2], + .enable = mx28_raw_enable, + .disable = mx28_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET, + .enable_bits = BM_CLKCTRL_ENET_DISABLE, +}; + +static struct clk_lookup onchip_clocks[] = { + { + .con_id = "xtal.0", + .clk = &xtal_clk[0], + }, + { + .con_id = "xtal.1", + .clk = &xtal_clk[1], + }, + { + .con_id = "xtal.2", + .clk = &xtal_clk[2], + }, + { + .con_id = "pll.0", + .clk = &pll_clk[0], + }, + { + .con_id = "pll.1", + .clk = &pll_clk[1], + }, + { + .con_id = "pll.2", + .clk = &pll_clk[2], + }, + { + .con_id = "ref_xtal", + .clk = &ref_xtal_clk, + }, + { + .con_id = "ref_cpu", + .clk = &ref_cpu_clk, + }, + { + .con_id = "ref_emi", + .clk = &ref_emi_clk, + }, + { + .con_id = "ref_io.0", + .clk = &ref_io_clk[0], + }, + { + .con_id = "ref_io.1", + .clk = &ref_io_clk[1], + }, + { + .con_id = "ref_pix", + .clk = &ref_pix_clk, + }, + { + .con_id = "ref_hsadc", + .clk = &ref_hsadc_clk, + }, + { + .con_id = "ref_gpmi", + .clk = &ref_gpmi_clk, + }, + { + .con_id = "ana", + .clk = &ana_clk, + }, + { + .con_id = "rtc", + .clk = &rtc_clk, + }, + { + .con_id = "cpu", + .clk = &cpu_clk, + }, + { + .con_id = "h", + .clk = &h_clk, + }, + { + .con_id = "x", + .clk = &x_clk, + }, + { + .con_id = "ocrom", + .clk = &ocrom_clk, + }, + { + .con_id = "clk_32k", + .clk = &clk_32k, + }, + { + .con_id = "uart", + .clk = &uart_clk, + }, + { + .con_id = "pwm", + .clk = &pwm_clk, + }, + { + .con_id = "lradc", + .clk = &lradc_clk, + }, + { + .con_id = "ssp.0", + .clk = &ssp_clk[0], + }, + { + .con_id = "ssp.1", + .clk = &ssp_clk[1], + }, + { + .con_id = "ssp.2", + .clk = &ssp_clk[2], + }, + { + .con_id = "ssp.3", + .clk = &ssp_clk[3], + }, + { + .con_id = "gpmi", + .clk = &gpmi_clk, + }, + { + .con_id = "spdif", + .clk = &pcmspdif_clk, + }, + { + .con_id = "saif.0", + .clk = &saif_clk[0], + }, + { + .con_id = "saif.1", + .clk = &saif_clk[1], + }, + { + .con_id = "emi", + .clk = &emi_clk, + }, + { + .con_id = "dis_lcdif", + .clk = &dis_lcdif_clk, + }, + { + .con_id = "hsadc", + .clk = &hsadc_clk, + }, + { + .con_id = "can_clk", + .dev_id = "FlexCAN.0", + .clk = &flexcan_clk[0], + }, + { + .con_id = "can_clk", + .dev_id = "FlexCAN.1", + .clk = &flexcan_clk[1], + }, + { + .con_id = "usb_clk0", + .clk = &usb_clk0, + }, + { + .con_id = "usb_clk1", + .clk = &usb_clk1, + }, + { + .con_id = "usb_phy_clk0", + .clk = &usb_phy_clk0, + }, + { + .con_id = "usb_phy_clk1", + .clk = &usb_phy_clk1, + }, + { + .con_id = "fec_clk", + .clk = &enet_out_clk, + }, + { + .con_id = "saif_mclk.0", + .clk = &saif_mclk[0], + }, + { + .con_id = "saif_mclk.1", + .clk = &saif_mclk[1], + } +}; + +static void mx28_clock_scan(void) +{ + unsigned long reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) + cpu_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) + dis_lcdif_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) + emi_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) + ssp_clk[3].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) + ssp_clk[2].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) + ssp_clk[1].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) + ssp_clk[0].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) + gpmi_clk.parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) + saif_clk[1].parent = &ref_xtal_clk; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) + saif_clk[0].parent = &ref_xtal_clk; +}; + +void __init mx28_set_input_clk(unsigned long xtal0, + unsigned long xtal1, + unsigned long xtal2, unsigned long enet) +{ + xtal_clk_rate[0] = xtal0; + xtal_clk_rate[1] = xtal1; + xtal_clk_rate[2] = xtal2; + enet_mii_phy_rate = enet; +} + +void mx28_enet_clk_hook(void) +{ + unsigned long reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); + + reg &= ~BM_CLKCTRL_ENET_SLEEP; + reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; + /* select clock for 1588 module */ + reg &= ~(BM_CLKCTRL_ENET_DIV_TIME | BM_CLKCTRL_ENET_TIME_SEL); + reg |= BF_CLKCTRL_ENET_TIME_SEL(BV_CLKCTRL_ENET_TIME_SEL__PLL) + | BF_CLKCTRL_ENET_DIV_TIME(12); + + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); +} + +void __init mx28_clock_init(void) +{ + int i; + mx28_clock_scan(); + mx28_enet_clk_hook(); + for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) + clk_register(&onchip_clocks[i]); + + clk_enable(&cpu_clk); + clk_enable(&emi_clk); + + clk_en_public_h_asm_ctrl(mx28_enable_h_autoslow, + mx28_set_hbus_autoslow_flags); +} diff --git a/arch/arm/mach-mx28/device.c b/arch/arm/mach-mx28/device.c new file mode 100644 index 000000000000..410928fc7d32 --- /dev/null +++ b/arch/arm/mach-mx28/device.c @@ -0,0 +1,1704 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-digctl.h" +#include "device.h" +#include "mx28evk.h" +#include "mx28_pins.h" + +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) +static struct resource duart_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = DUART_PHYS_ADDR, + .end = DUART_PHYS_ADDR + 0x1000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_DUART, + .end = IRQ_DUART, + }, +}; + +static void __init mx28_init_duart(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-duart", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = duart_resource; + pdev->num_resources = ARRAY_SIZE(duart_resource); + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_duart(void) +{ +} +#endif + +#if defined(CONFIG_MXS_DMA_ENGINE) +static struct resource mxs_ahb_apbh_res = { + .flags = IORESOURCE_MEM, + .start = APBH_DMA_PHYS_ADDR, + .end = APBH_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbh_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBH, + .chan_num = 16, +}; + +static struct resource mxs_ahb_apbx_res = { + .flags = IORESOURCE_MEM, + .start = APBX_DMA_PHYS_ADDR, + .end = APBX_DMA_PHYS_ADDR + 0x2000 - 1, +}; + +static struct mxs_dma_plat_data mxs_ahb_apbx_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBX, + .chan_num = 16, +}; + +static void __init mx28_init_dma(void) +{ + int i; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev; + lookup = mxs_get_devices("mxs-dma"); + if (lookup == NULL || IS_ERR(lookup)) + return; + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + if (!strcmp(pdev->name, "mxs-dma-apbh")) { + pdev->resource = &mxs_ahb_apbh_res; + pdev->dev.platform_data = &mxs_ahb_apbh_data; + } else if (!strcmp(pdev->name, "mxs-dma-apbx")) { + pdev->resource = &mxs_ahb_apbx_res; + pdev->dev.platform_data = &mxs_ahb_apbx_data; + } else + continue; + pdev->num_resources = 1; + mxs_add_device(pdev, 0); + } +} +#else +static void mx28_init_dma(void) +{ + ; +} +#endif + +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) +static struct resource framebuffer_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = LCDIF_PHYS_ADDR, + .end = LCDIF_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LCDIF, + .end = IRQ_LCDIF, + }, +}; + +static struct mxs_platform_fb_data mxs_framebuffer_pdata = { + .list = LIST_HEAD_INIT(mxs_framebuffer_pdata.list), +}; + +static void __init mx28_init_lcdif(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-fb", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = framebuffer_resource; + pdev->num_resources = ARRAY_SIZE(framebuffer_resource); + pdev->dev.platform_data = &mxs_framebuffer_pdata; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_lcdif(void) +{ + ; +} +#endif + +#if defined(CONFIG_VIDEO_MXS_PXP) || \ + defined(CONFIG_VIDEO_MXS_PXP_MODULE) +static struct resource pxp_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = (unsigned int)IO_ADDRESS(PXP_PHYS_ADDR), + .end = (unsigned int)IO_ADDRESS(PXP_PHYS_ADDR) + 0x2000 - 1, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_PXP, + .end = IRQ_PXP, + }, +}; +static void __init mx28_init_pxp(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-pxp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = pxp_resource; + pdev->num_resources = ARRAY_SIZE(pxp_resource); + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_pxp(void) +{ + ; +} +#endif + +#if defined(CONFIG_MXS_VIIM) || defined(CONFIG_MXS_VIIM_MODULE) +struct resource viim_resources[] = { + [0] = { + .start = DIGCTL_PHYS_ADDR, + .end = DIGCTL_PHYS_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OCOTP_PHYS_ADDR, + .end = OCOTP_PHYS_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +static void __init mx28_init_viim(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs_viim", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->resource = viim_resources; + pdev->num_resources = ARRAY_SIZE(viim_resources); + + mxs_add_device(pdev, 2); +} +#else +static void __init mx28_init_viim(void) +{ +} +#endif + +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) +#ifdef CONFIG_I2C_MXS_SELECT0 +static struct resource i2c0_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = I2C0_PHYS_ADDR, + .end = I2C0_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_I2C0, + .end = MXS_DMA_CHANNEL_AHB_APBX_I2C0, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C0_ERROR, + .end = IRQ_I2C0_ERROR, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C0_DMA, + .end = IRQ_I2C0_DMA, + }, +}; + +static struct mxs_i2c_plat_data i2c0_platdata = { +#ifdef CONFIG_I2C_MXS_SELECT0_PIOQUEUE_MODE + .pioqueue_mode = 1, +#endif +}; +#endif + +#ifdef CONFIG_I2C_MXS_SELECT1 +static struct resource i2c1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = I2C1_PHYS_ADDR, + .end = I2C1_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_I2C1, + .end = MXS_DMA_CHANNEL_AHB_APBX_I2C1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C1_ERROR, + .end = IRQ_I2C1_ERROR, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_I2C1_DMA, + .end = IRQ_I2C1_DMA, + }, +}; + +static struct mxs_i2c_plat_data i2c1_platdata = { +#ifdef CONFIG_I2C_MXS_SELECT1_PIOQUEUE_MODE + .pioqueue_mode = 1, +#endif +}; +#endif + +static void __init mx28_init_i2c(void) +{ + int i; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev; + + lookup = mxs_get_devices("mxs-i2c"); + if (lookup == NULL || IS_ERR(lookup)) + return; + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + switch (pdev->id) { +#ifdef CONFIG_I2C_MXS_SELECT0 + case 0: + pdev->resource = i2c0_resource; + pdev->num_resources = ARRAY_SIZE(i2c0_resource); + pdev->dev.platform_data = &i2c0_platdata; + break; +#endif +#ifdef CONFIG_I2C_MXS_SELECT1 + case 1: + pdev->resource = i2c1_resource; + pdev->num_resources = ARRAY_SIZE(i2c1_resource); + pdev->dev.platform_data = &i2c1_platdata; + break; +#endif + default: + return; + } + mxs_add_device(pdev, 2); + } +} +#else +static void __init mx28_init_i2c(void) +{ +} +#endif + +#if defined(CONFIG_MTD_NAND_GPMI_NFC) + +extern int enable_gpmi; + +static int gpmi_nfc_platform_init(unsigned int max_chip_count) +{ + return !enable_gpmi; +} + +static void gpmi_nfc_platform_exit(unsigned int max_chip_count) +{ +} + +static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; + +static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { + .nfc_version = 1, + .boot_rom_version = 1, + .clock_name = "gpmi", + .platform_init = gpmi_nfc_platform_init, + .platform_exit = gpmi_nfc_platform_exit, + .min_prop_delay_in_ns = 5, + .max_prop_delay_in_ns = 9, + .max_chip_count = 2, + .boot_area_size_in_bytes = 20 * SZ_1M, + .partition_source_types = gpmi_nfc_partition_source_types, + .partitions = 0, + .partition_count = 0, +}; + +static struct resource gpmi_nfc_resources[] = { + { + .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = GPMI_PHYS_ADDR, + .end = GPMI_PHYS_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI, + .end = IRQ_GPMI, + }, + { + .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = BCH_PHYS_ADDR, + .end = BCH_PHYS_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_BCH, + .end = IRQ_BCH, + }, + { + .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + }, + { + .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI_DMA, + .end = IRQ_GPMI_DMA, + }, +}; + +static void __init mx28_init_gpmi_nfc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device(GPMI_NFC_DRIVER_NAME, 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &gpmi_nfc_platform_data; + pdev->resource = gpmi_nfc_resources; + pdev->num_resources = ARRAY_SIZE(gpmi_nfc_resources); + mxs_add_device(pdev, 1); +} +#else +static void mx28_init_gpmi_nfc(void) +{ +} +#endif + +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) +#if defined(CONFIG_MACH_MX28EVK) +#define MMC0_POWER MXS_PIN_TO_GPIO(PINID_PWM3) +#define MMC1_POWER MXS_PIN_TO_GPIO(PINID_PWM4) +#define MMC0_WP MXS_PIN_TO_GPIO(PINID_SSP1_SCK) +#define MMC1_WP MXS_PIN_TO_GPIO(PINID_GPMI_RESETN) +#endif + +static int mxs_mmc_get_wp_ssp0(void) +{ + return gpio_get_value(MMC0_WP); +} + +static int mxs_mmc_hw_init_ssp0(void) +{ + int ret = 0; + + /* Configure write protect GPIO pin */ + ret = gpio_request(MMC0_WP, "mmc0_wp"); + if (ret) + goto out_wp; + + gpio_set_value(MMC0_WP, 0); + gpio_direction_input(MMC0_WP); + + /* Configure POWER pin as gpio to drive power to MMC slot */ + ret = gpio_request(MMC0_POWER, "mmc0_power"); + if (ret) + goto out_power; + + gpio_direction_output(MMC0_POWER, 0); + mdelay(100); + + return 0; + +out_power: + gpio_free(MMC0_WP); +out_wp: + return ret; +} + +static void mxs_mmc_hw_release_ssp0(void) +{ + gpio_free(MMC0_POWER); + gpio_free(MMC0_WP); + +} + +static void mxs_mmc_cmd_pullup_ssp0(int enable) +{ + mxs_set_pullup(PINID_SSP0_CMD, enable, "mmc0_cmd"); +} + +static unsigned long mxs_mmc_setclock_ssp0(unsigned long hz) +{ + struct clk *ssp = clk_get(NULL, "ssp.0"), *parent; + + if (hz > 1000000) + parent = clk_get(NULL, "ref_io.0"); + else + parent = clk_get(NULL, "xtal.0"); + + clk_set_parent(ssp, parent); + clk_set_rate(ssp, 2 * hz); + clk_put(parent); + clk_put(ssp); + + return hz; +} + +static int mxs_mmc_get_wp_ssp1(void) +{ + return gpio_get_value(MMC1_WP); +} + +static int mxs_mmc_hw_init_ssp1(void) +{ + int ret = 0; + + /* Configure write protect GPIO pin */ + ret = gpio_request(MMC1_WP, "mmc1_wp"); + if (ret) + goto out_wp; + + gpio_set_value(MMC1_WP, 0); + gpio_direction_input(MMC1_WP); + + /* Configure POWER pin as gpio to drive power to MMC slot */ + ret = gpio_request(MMC1_POWER, "mmc1_power"); + if (ret) + goto out_power; + + gpio_direction_output(MMC1_POWER, 0); + mdelay(100); + + return 0; + +out_power: + gpio_free(MMC1_WP); +out_wp: + return ret; +} + +static void mxs_mmc_hw_release_ssp1(void) +{ + gpio_free(MMC1_POWER); + gpio_free(MMC1_WP); +} + +static void mxs_mmc_cmd_pullup_ssp1(int enable) +{ + mxs_set_pullup(PINID_GPMI_RDY1, enable, "mmc1_cmd"); +} + +static unsigned long mxs_mmc_setclock_ssp1(unsigned long hz) +{ + struct clk *ssp = clk_get(NULL, "ssp.1"), *parent; + + if (hz > 1000000) + parent = clk_get(NULL, "ref_io.0"); + else + parent = clk_get(NULL, "xtal.0"); + + clk_set_parent(ssp, parent); + clk_set_rate(ssp, 2 * hz); + clk_put(parent); + clk_put(ssp); + + return hz; +} + +static struct mxs_mmc_platform_data mmc0_data = { + .hw_init = mxs_mmc_hw_init_ssp0, + .hw_release = mxs_mmc_hw_release_ssp0, + .get_wp = mxs_mmc_get_wp_ssp0, + .cmd_pullup = mxs_mmc_cmd_pullup_ssp0, + .setclock = mxs_mmc_setclock_ssp0, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 48000000, + .read_uA = 50000, + .write_uA = 70000, + .clock_mmc = "ssp.0", + .power_mmc = NULL, +}; + +static struct resource mmc0_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = SSP0_PHYS_ADDR, + .end = SSP0_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP0, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP0, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP0_DMA, + .end = IRQ_SSP0_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP0, + .end = IRQ_SSP0, + }, +}; + +static struct mxs_mmc_platform_data mmc1_data = { + .hw_init = mxs_mmc_hw_init_ssp1, + .hw_release = mxs_mmc_hw_release_ssp1, + .get_wp = mxs_mmc_get_wp_ssp1, + .cmd_pullup = mxs_mmc_cmd_pullup_ssp1, + .setclock = mxs_mmc_setclock_ssp1, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 48000000, + .read_uA = 50000, + .write_uA = 70000, + .clock_mmc = "ssp.1", + .power_mmc = NULL, +}; + +static struct resource mmc1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = SSP1_PHYS_ADDR, + .end = SSP1_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP1_DMA, + .end = IRQ_SSP1_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_SSP1, + .end = IRQ_SSP1, + }, +}; + +static void __init mx28_init_mmc(void) +{ + struct platform_device *pdev; + + if (mxs_get_type(PINID_SSP0_CMD) == PIN_FUN1) { + pdev = mxs_get_device("mxs-mmc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mmc0_resource; + pdev->num_resources = ARRAY_SIZE(mmc0_resource); + pdev->dev.platform_data = &mmc0_data; + mxs_add_device(pdev, 2); + } + + if (mxs_get_type(PINID_GPMI_RDY1) == PIN_FUN2) { + pdev = mxs_get_device("mxs-mmc", 1); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mmc1_resource; + pdev->num_resources = ARRAY_SIZE(mmc1_resource); + pdev->dev.platform_data = &mmc1_data; + mxs_add_device(pdev, 2); + } +} +#else +static void mx28_init_mmc(void) +{ +} +#endif + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct mxs_spi_platform_data spi_data = { + .clk = "ssp.2", +}; +static struct resource ssp2_resources[] = { + { + .start = SSP2_PHYS_ADDR, + .end = SSP2_PHYS_ADDR + 0x2000 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP2, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP2, + .flags = IORESOURCE_DMA, + }, { + .start = IRQ_SSP2_DMA, + .end = IRQ_SSP2_DMA, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_SSP2, + .end = IRQ_SSP2, + .flags = IORESOURCE_IRQ, + }, +}; + +static void __init mx28_init_spi(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-spi", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = ssp2_resources; + pdev->num_resources = ARRAY_SIZE(ssp2_resources); + pdev->dev.platform_data = &spi_data; + + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_spi(void) +{ +} +#endif + +#if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE) +static struct resource mx28_wdt_res = { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, +}; + +static void __init mx28_init_wdt(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-wdt", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = &mx28_wdt_res; + pdev->num_resources = 1; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_wdt(void) +{ + ; +} +#endif + +#if defined(CONFIG_RTC_DRV_MXS) || defined(CONFIG_RTC_DRV_MXS_MODULE) +static struct resource mx28_rtc_res[] = { + { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_RTC_1MSEC, + .end = IRQ_RTC_1MSEC, + }, +}; + +static void __init mx28_init_rtc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-rtc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx28_rtc_res; + pdev->num_resources = ARRAY_SIZE(mx28_rtc_res); + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_rtc(void) +{ + ; +} +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +static struct resource fec0_resource[] = { + { + .start = ENET_PHYS_ADDR, + .end = ENET_PHYS_ADDR + 0x3fff, + .flags = IORESOURCE_MEM + }, + { + .start = IRQ_ENET_MAC0, + .end = IRQ_ENET_MAC0, + .flags = IORESOURCE_IRQ + }, +}; + +static struct resource fec1_resource[] = { + { + .start = ENET_PHYS_ADDR + 0x4000, + .end = ENET_PHYS_ADDR + 0x7fff, + .flags = IORESOURCE_MEM + }, + { + .start = IRQ_ENET_MAC1, + .end = IRQ_ENET_MAC1, + .flags = IORESOURCE_IRQ + }, +}; + +extern int mx28evk_enet_gpio_init(void); +static struct fec_platform_data fec_pdata0 = { + .phy = PHY_INTERFACE_MODE_RMII, + .init = mx28evk_enet_gpio_init, +}; + +static struct fec_platform_data fec_pdata1 = { + .phy = PHY_INTERFACE_MODE_RMII, + .init = mx28evk_enet_gpio_init, +}; + +static void __init mx28_init_fec(void) +{ + struct platform_device *pdev; + struct mxs_dev_lookup *lookup; + struct fec_platform_data *pfec; + int i; + u32 val; + + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET); + + while (BM_OCOTP_CTRL_BUSY & + __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL)) + udelay(10); + + lookup = mxs_get_devices("mxs-fec"); + if (lookup == NULL || IS_ERR(lookup)) + return; + + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + val = __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + + HW_OCOTP_CUSTn(pdev->id)); + switch (pdev->id) { + case 0: + pdev->resource = fec0_resource; + pdev->num_resources = ARRAY_SIZE(fec0_resource); + pdev->dev.platform_data = &fec_pdata0; + break; + case 1: + pdev->resource = fec1_resource; + pdev->num_resources = ARRAY_SIZE(fec1_resource); + pdev->dev.platform_data = &fec_pdata1; + break; + default: + return; + } + + pfec = (struct fec_platform_data *)pdev->dev.platform_data; + pfec->mac[0] = 0x00; + pfec->mac[1] = 0x04; + pfec->mac[2] = (val >> 24) & 0xFF; + pfec->mac[3] = (val >> 16) & 0xFF; + pfec->mac[4] = (val >> 8) & 0xFF; + pfec->mac[5] = (val >> 0) & 0xFF; + + mxs_add_device(pdev, 2); + } +} +#else +static void __init mx28_init_fec(void) +{ + ; +} +#endif + +#if defined(CONFIG_FEC_L2SWITCH) +static struct resource l2switch_resources[] = { + { + .start = ENET_PHYS_ADDR, + .end = ENET_PHYS_ADDR + 0x17FFC, + .flags = IORESOURCE_MEM + }, + { + .start = IRQ_ENET_SWI, + .end = IRQ_ENET_SWI, + .flags = IORESOURCE_IRQ + }, + { + .start = IRQ_ENET_MAC0, + .end = IRQ_ENET_MAC0, + .flags = IORESOURCE_IRQ + }, + { + .start = IRQ_ENET_MAC1, + .end = IRQ_ENET_MAC1, + .flags = IORESOURCE_IRQ + }, +}; + +/* Define the fixed address of the L2 Switch hardware. */ +static unsigned int switch_platform_hw[2] = { + (0x800F8000), + (0x800FC000), +}; + +static struct fec_platform_data fec_enet = { + .phy = PHY_INTERFACE_MODE_RMII, + .init = mx28evk_enet_gpio_init, +}; + +static struct switch_platform_data l2switch_data = { + .id = 0, + .fec_enet = &fec_enet, + .hash_table = 0, + .switch_hw = switch_platform_hw, +}; + +static void __init mx28_init_l2switch(void) +{ + struct platform_device *pdev; + struct switch_platform_data *pswitch; + struct fec_platform_data *pfec; + u32 val; + + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET); + + while (BM_OCOTP_CTRL_BUSY & + __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL)) + udelay(10); + + pdev = mxs_get_device("mxs-l2switch", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + val = __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + + HW_OCOTP_CUSTn(pdev->id)); + pdev->resource = l2switch_resources; + pdev->num_resources = ARRAY_SIZE(l2switch_resources); + pdev->dev.platform_data = &l2switch_data; + + pswitch = (struct switch_platform_data *)pdev->dev.platform_data; + pfec = pswitch->fec_enet; + pfec->mac[0] = 0x00; + pfec->mac[1] = 0x04; + pfec->mac[2] = (val >> 24) & 0xFF; + pfec->mac[3] = (val >> 16) & 0xFF; + pfec->mac[4] = (val >> 8) & 0xFF; + pfec->mac[5] = (val >> 0) & 0xFF; + + mxs_add_device(pdev, 2); +} +#else +static void __init mx28_init_l2switch(void) +{ + ; +} +#endif + +#ifdef CONFIG_MXS_LRADC +struct mxs_lradc_plat_data mx28_lradc_data = { + .vddio_voltage = BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10, + .battery_voltage = BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7, +}; + +static struct resource mx28_lradc_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, +}; + +static void __init mx28_init_lradc(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-lradc", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx28_lradc_res; + pdev->num_resources = ARRAY_SIZE(mx28_lradc_res); + pdev->dev.platform_data = &mx28_lradc_data; + mxs_add_device(pdev, 0); +} +#else +static void __init mx28_init_lradc(void) +{ + ; +} +#endif + +#if defined(CONFIG_KEYBOARD_MXS) || defined(CONFIG_KEYBOARD_MXS_MODULE) +static struct mxskbd_keypair keyboard_data[] = { + { 100, KEY_F4 }, + { 306, KEY_F5 }, + { 626, KEY_F6 }, + { 932, KEY_F7 }, + { 1260, KEY_F8 }, + { 1584, KEY_F9 }, + { 1907, KEY_F10 }, + { 2207, KEY_F11 }, + { 2525, KEY_F12 }, + { 2831, KEY_F13}, + { 3134, KEY_F14 }, + { -1, 0 }, +}; + +static struct mxs_kbd_plat_data mxs_kbd_data = { + .keypair = keyboard_data, + .channel = LRADC_CH1, + .btn_enable = BM_LRADC_CTRL0_BUTTON1_DETECT_ENABLE, + .btn_irq_stat = BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ, + .btn_irq_ctrl = BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN, +}; + +static struct resource mx28_kbd_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH1, + .end = IRQ_LRADC_CH1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_BUTTON1, + .end = IRQ_LRADC_BUTTON1, + } +}; + +static void __init mx28_init_kbd(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-kbd", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx28_kbd_res; + pdev->num_resources = ARRAY_SIZE(mx28_kbd_res); + pdev->dev.platform_data = &mxs_kbd_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_kbd(void) +{ + ; +} +#endif + +#if defined(CONFIG_TOUCHSCREEN_MXS) || defined(CONFIG_TOUCHSCREEN_MXS_MODULE) +static struct mxs_touchscreen_plat_data mx28_ts_data = { + .x_plus_chan = LRADC_TOUCH_X_PLUS, + .x_minus_chan = LRADC_TOUCH_X_MINUS, + .y_plus_chan = LRADC_TOUCH_Y_PLUS, + .y_minus_chan = LRADC_TOUCH_Y_MINUS, + .x_plus_val = BM_LRADC_CTRL0_XPULSW, + .x_minus_val = BF_LRADC_CTRL0_XNURSW(2), + .y_plus_val = BF_LRADC_CTRL0_YPLLSW(1), + .y_minus_val = BM_LRADC_CTRL0_YNLRSW, + .x_plus_mask = BM_LRADC_CTRL0_XPULSW, + .x_minus_mask = BM_LRADC_CTRL0_XNURSW, + .y_plus_mask = BM_LRADC_CTRL0_YPLLSW, + .y_minus_mask = BM_LRADC_CTRL0_YNLRSW, +}; + +static struct resource mx28_ts_res[] = { + { + .flags = IORESOURCE_MEM, + .start = LRADC_PHYS_ADDR, + .end = LRADC_PHYS_ADDR + 0x2000 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_TOUCH, + .end = IRQ_LRADC_TOUCH, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_LRADC_CH5, + .end = IRQ_LRADC_CH5, + }, +}; + +static void __init mx28_init_ts(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-ts", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = mx28_ts_res; + pdev->num_resources = ARRAY_SIZE(mx28_ts_res); + pdev->dev.platform_data = &mx28_ts_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_ts(void) +{ + ; +} +#endif + +#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE) +static void flexcan_xcvr_enable(int id, int en) +{ + static int pwdn; + if (en) { + if (!pwdn++) + gpio_set_value(MXS_PIN_TO_GPIO(PINID_SSP1_CMD), 1); + } else { + if (!--pwdn) + gpio_set_value(MXS_PIN_TO_GPIO(PINID_SSP1_CMD), 0); + } +} + +struct flexcan_platform_data flexcan_data[] = { + { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 2, + .br_propseg = 2, + .br_pseg1 = 3, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .smp = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, + }, + { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 2, + .br_propseg = 2, + .br_pseg1 = 3, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, + }, +}; + +static struct resource flexcan0_resources[] = { + { + .start = CAN0_PHYS_ADDR, + .end = CAN0_PHYS_ADDR + 0x1FFF, + .flags = IORESOURCE_MEM,}, + { + .start = IRQ_CAN0, + .end = IRQ_CAN0, + .flags = IORESOURCE_IRQ,}, +}; +static struct resource flexcan1_resources[] = { + { + .start = CAN1_PHYS_ADDR, + .end = CAN1_PHYS_ADDR + 0x1FFF, + .flags = IORESOURCE_MEM,}, + { + .start = IRQ_CAN1, + .end = IRQ_CAN1, + .flags = IORESOURCE_IRQ,}, +}; + +static inline void mx28_init_flexcan(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("FlexCAN", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = flexcan0_resources; + pdev->num_resources = ARRAY_SIZE(flexcan0_resources); + pdev->dev.platform_data = &flexcan_data[0]; + mxs_add_device(pdev, 2); + + pdev = mxs_get_device("FlexCAN", 1); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = flexcan1_resources; + pdev->num_resources = ARRAY_SIZE(flexcan1_resources); + pdev->dev.platform_data = &flexcan_data[1]; + mxs_add_device(pdev, 2); +} +#else +static inline void mx28_init_flexcan(void) +{ +} +#endif +#if defined(CONFIG_BATTERY_MXS) +/* battery info data */ +static ddi_bc_Cfg_t battery_data = { + .u32StateMachinePeriod = 100, /* ms */ + .u16CurrentRampSlope = 75, /* mA/s */ + .u16ConditioningThresholdVoltage = 2900, /* mV */ + .u16ConditioningMaxVoltage = 3000, /* mV */ + .u16ConditioningCurrent = 160, /* mA */ + .u32ConditioningTimeout = 4*60*60*1000, /* ms (4 hours) */ + .u16ChargingVoltage = 4200, /* mV */ + /* FIXME: the current comparator could have h/w bugs in current + * detection through POWER_STS.CHRGSTS bit */ + .u16ChargingCurrent = 600, /* mA 600 */ + .u16ChargingThresholdCurrent = 60, /* mA 60 */ + .u32ChargingTimeout = 4*60*60*1000,/* ms (4 hours) */ + .u32TopOffPeriod = 30*60*1000, /* ms (30 minutes) */ + .monitorDieTemp = 1, /* Monitor the die */ + .u8DieTempHigh = 75, /* deg centigrade */ + .u8DieTempLow = 65, /* deg centigrade */ + .u16DieTempSafeCurrent = 0, /* mA */ + .monitorBatteryTemp = 0, /* Monitor the battery*/ + .u8BatteryTempChannel = 0, /* LRADC 0 */ + .u16BatteryTempHigh = 642, /* Unknown units */ + .u16BatteryTempLow = 497, /* Unknown units */ + .u16BatteryTempSafeCurrent = 0, /* mA */ +}; + +static struct resource battery_resource[] = { + {/* 0 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDD5V, + .end = IRQ_VDD5V, + }, + {/* 1 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_DCDC4P2_BRNOUT, + .end = IRQ_DCDC4P2_BRNOUT, + }, + {/* 2 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_BATT_BRNOUT, + .end = IRQ_BATT_BRNOUT, + }, + {/* 3 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDDD_BRNOUT, + .end = IRQ_VDDD_BRNOUT, + }, + {/* 4 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDDA_BRNOUT, + .end = IRQ_VDDA_BRNOUT, + }, + {/* 5 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDDIO_BRNOUT, + .end = IRQ_VDDIO_BRNOUT, + }, + {/* 6 */ + .flags = IORESOURCE_IRQ, + .start = IRQ_VDD5V_DROOP, + .end = IRQ_VDD5V_DROOP, + }, +}; + +static void mx28_init_battery(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-battery", 0); + if (pdev) { + pdev->resource = battery_resource, + pdev->num_resources = ARRAY_SIZE(battery_resource), + pdev->dev.platform_data = &battery_data; + mxs_add_device(pdev, 3); + } +} +#else +static void mx28_init_battery(void) +{ +} +#endif + +#if defined(CONFIG_CRYPTO_DEV_DCP) + +static struct resource dcp_resources[] = { + + { + .flags = IORESOURCE_MEM, + .start = DCP_PHYS_ADDR, + .end = DCP_PHYS_ADDR + 0x2000 - 1, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_DCP_VMI, + .end = IRQ_DCP_VMI, + }, { + .flags = IORESOURCE_IRQ, + .start = IRQ_DCP, + .end = IRQ_DCP, + }, +}; + +static void __init mx28_init_dcp(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("dcp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = dcp_resources; + pdev->num_resources = ARRAY_SIZE(dcp_resources); + mxs_add_device(pdev, 3); +} +#else +static void __init mx28_init_dcp(void) +{ + ; +} +#endif + +#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE) +static int audio_clk_init(struct clk *clk) +{ + struct clk *pll_clk; + struct clk *saif_mclk0; + struct clk *saif_mclk1; + int ret = -EINVAL; + if (IS_ERR(clk)) { + pr_err("%s:failed to get clk\n", __func__); + goto err_clk_init; + } + pll_clk = clk_get(NULL, "pll.0"); + if (IS_ERR(pll_clk)) { + pr_err("%s:failed to get pll_clk\n", __func__); + goto err_clk_init; + } + saif_mclk0 = clk_get(NULL, "saif_mclk.0"); + if (IS_ERR(saif_mclk0)) { + pr_err("%s:failed to get saif_mclk\n", __func__); + goto err_clk_init; + } + saif_mclk1 = clk_get(NULL, "saif_mclk.1"); + if (IS_ERR(saif_mclk1)) { + pr_err("%s:failed to get saif_mclk\n", __func__); + goto err_clk_init; + } + ret = clk_set_parent(clk, pll_clk); + if (ret) { + pr_err("%s:failed to set parent clk\n", __func__); + goto err_clk_init; + } + ret = 0; + /*set a default freq of 12M to sgtl5000*/ + clk_set_rate(clk, 12000000); + clk_enable(clk); + /*set the saif clk mux, saif0/saif1 both use saif0 clk*/ + __raw_writel(BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(0x2), \ + IO_ADDRESS(DIGCTL_PHYS_ADDR) + HW_DIGCTL_CTRL); + + /*enable saif0/saif1 clk output*/ + clk_enable(saif_mclk0); + clk_enable(saif_mclk1); +err_clk_init: + return ret; +} + +static int audio_clk_finit(void) +{ + struct clk *saif_clk; + struct clk *saif_mclk0; + struct clk *saif_mclk1; + int ret = 0; + saif_clk = clk_get(NULL, "saif.0"); + if (IS_ERR(saif_clk)) { + pr_err("%s:failed to get saif_clk\n", __func__); + ret = -EINVAL; + goto err_clk_finit; + } + clk_disable(saif_clk); + + saif_mclk0 = clk_get(NULL, "saif_mclk.0"); + if (IS_ERR(saif_mclk0)) { + pr_err("%s:failed to get saif_mclk\n", __func__); + goto err_clk_finit; + } + clk_disable(saif_mclk0); + + saif_mclk1 = clk_get(NULL, "saif_mclk.1"); + if (IS_ERR(saif_mclk1)) { + pr_err("%s:failed to get saif_mclk\n", __func__); + goto err_clk_finit; + } + clk_disable(saif_mclk1); +err_clk_finit: + return ret; +} + +static struct mxs_audio_platform_data audio_plat_data; +#endif + +#if defined(CONFIG_SND_SOC_SGTL5000) || defined(CONFIG_SND_SOC_SGTL5000_MODULE) +void __init mx28_init_audio(void) +{ struct platform_device *pdev; + pdev = mxs_get_device("mxs-sgtl5000", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + mxs_add_device(pdev, 3); + audio_plat_data.saif_mclock = clk_get(NULL, "saif.0"); + audio_clk_init(audio_plat_data.saif_mclock); + pdev->dev.platform_data = &audio_plat_data; +} +#else +void __init mx28_init_audio(void) +{ +} +#endif + +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) +void __init mx28_init_spdif(void) +{ struct platform_device *pdev; + pdev = mxs_get_device("mxs-spdif", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + mxs_add_device(pdev, 3); +} +#else +static inline mx28_init_spdif(void) +{ +} +#endif + +#if defined(CONFIG_MXS_PERSISTENT) +static const struct mxs_persistent_bit_config +mx28_persistent_bit_config[] = { + { .reg = 0, .start = 0, .width = 1, + .name = "CLOCKSOURCE" }, + { .reg = 0, .start = 1, .width = 1, + .name = "ALARM_WAKE_EN" }, + { .reg = 0, .start = 2, .width = 1, + .name = "ALARM_EN" }, + { .reg = 0, .start = 3, .width = 1, + .name = "CLK_SECS" }, + { .reg = 0, .start = 4, .width = 1, + .name = "XTAL24MHZ_PWRUP" }, + { .reg = 0, .start = 5, .width = 1, + .name = "XTAL32MHZ_PWRUP" }, + { .reg = 0, .start = 6, .width = 1, + .name = "XTAL32_FREQ" }, + { .reg = 0, .start = 7, .width = 1, + .name = "ALARM_WAKE" }, + { .reg = 0, .start = 8, .width = 5, + .name = "MSEC_RES" }, + { .reg = 0, .start = 13, .width = 1, + .name = "DISABLE_XTALOK" }, + { .reg = 0, .start = 14, .width = 2, + .name = "LOWERBIAS" }, + { .reg = 0, .start = 16, .width = 1, + .name = "DISABLE_PSWITCH" }, + { .reg = 0, .start = 17, .width = 1, + .name = "AUTO_RESTART" }, + { .reg = 0, .start = 18, .width = 1, + .name = "ENABLE_LRADC_PWRUP" }, + { .reg = 0, .start = 20, .width = 1, + .name = "THERMAL_RESET" }, + { .reg = 0, .start = 21, .width = 1, + .name = "EXTERNAL_RESET" }, + { .reg = 0, .start = 28, .width = 4, + .name = "ADJ_POSLIMITBUCK" }, + { .reg = 1, .start = 0, .width = 1, + .name = "FORCE_RECOVERY" }, + { .reg = 1, .start = 1, .width = 1, + .name = "ROM_REDUNDANT_BOOT" }, + { .reg = 1, .start = 2, .width = 1, + .name = "NAND_SDK_BLOCK_REWRITE" }, + { .reg = 1, .start = 3, .width = 1, + .name = "SD_SPEED_ENABLE" }, + { .reg = 1, .start = 4, .width = 1, + .name = "SD_INIT_SEQ_1_DISABLE" }, + { .reg = 1, .start = 5, .width = 1, + .name = "SD_CMD0_DISABLE" }, + { .reg = 1, .start = 6, .width = 1, + .name = "SD_INIT_SEQ_2_ENABLE" }, + { .reg = 1, .start = 7, .width = 1, + .name = "OTG_ATL_ROLE_BIT" }, + { .reg = 1, .start = 8, .width = 1, + .name = "OTG_HNP_BIT" }, + { .reg = 1, .start = 9, .width = 1, + .name = "USB_LOW_POWER_MODE" }, + { .reg = 1, .start = 10, .width = 1, + .name = "SKIP_CHECKDISK" }, + { .reg = 1, .start = 11, .width = 1, + .name = "USB_BOOT_PLAYER_MODE" }, + { .reg = 1, .start = 12, .width = 1, + .name = "ENUMERATE_500MA_TWICE" }, + { .reg = 1, .start = 13, .width = 19, + .name = "SPARE_GENERAL" }, + + { .reg = 2, .start = 0, .width = 32, + .name = "SPARE_2" }, + { .reg = 3, .start = 0, .width = 32, + .name = "SPARE_3" }, + { .reg = 4, .start = 0, .width = 32, + .name = "SPARE_4" }, + { .reg = 5, .start = 0, .width = 32, + .name = "SPARE_5" }, +}; + +static struct mxs_platform_persistent_data mx28_persistent_data = { + .bit_config_tab = mx28_persistent_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx28_persistent_bit_config), +}; + +static struct resource mx28_persistent_res[] = { + { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, + }, +}; + +static void mx28_init_persistent(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-persistent", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &mx28_persistent_data; + pdev->resource = mx28_persistent_res, + pdev->num_resources = ARRAY_SIZE(mx28_persistent_res), + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_persistent() +{ +} +#endif + +#if defined(CONFIG_MXS_PERFMON) + +static struct mxs_perfmon_bit_config +mx28_perfmon_bit_config[] = { + {.field = (1 << 0), .name = "MID0-PXP" }, + {.field = (1 << 1), .name = "MID1-LCDIF" }, + {.field = (1 << 2), .name = "MID2-BCH" }, + {.field = (1 << 3), .name = "MID3-DCP" } +}; + +static struct mxs_platform_perfmon_data mx28_perfmon_data = { + .bit_config_tab = mx28_perfmon_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx28_perfmon_bit_config), +}; + +static struct resource mx28_perfmon_res[] = { + { + .flags = IORESOURCE_MEM, + .start = PERFMON_PHYS_ADDR, + .end = PERFMON_PHYS_ADDR + 0x1000 - 1, + }, +}; + +static void mx28_init_perfmon(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-perfmon", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &mx28_perfmon_data; + pdev->resource = mx28_perfmon_res, + pdev->num_resources = ARRAY_SIZE(mx28_perfmon_res), + mxs_add_device(pdev, 3); +} + +#else + +static void mx28_init_perfmon() +{ +} + +#endif + + +#if defined(CONFIG_FSL_OTP) +/* Building up eight registers's names of a bank */ +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (5) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(CUST0, CUST1, CUST2, CUST3, CRYPTO0, CRYPTO1, CRYPTO2, CRYPTO3), + BANK(HWCAP0, HWCAP1, HWCAP2, HWCAP3, HWCAP4, HWCAP5, SWCAP, CUSTCAP), + BANK(LOCK, OPS0, OPS1, OPS2, OPS3, UN0, UN1, UN2), + BANK(ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7), + BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), +}; + +static struct fsl_otp_data otp_data = { + .fuse_name = (char **)bank_reg_desc, + .regulator_name = "vddio", + .fuse_num = BANKS * BANK_ITEMS, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS + +static void __init mx28_init_otp(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("ocotp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &otp_data; + pdev->resource = NULL; + pdev->num_resources = 0; + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_otp(void) +{ +} +#endif + +int __init mx28_device_init(void) +{ + mx28_init_dma(); + mx28_init_viim(); + mx28_init_duart(); + mx28_init_i2c(); + mx28_init_lradc(); + mx28_init_auart(); + mx28_init_mmc(); + mx28_init_spi(); + mx28_init_gpmi_nfc(); + mx28_init_wdt(); + mx28_init_rtc(); + mx28_init_fec(); + mx28_init_l2switch(); + mx28_init_flexcan(); + mx28_init_kbd(); + mx28_init_ts(); + mx28_init_audio(); + mx28_init_spdif(); + mx28_init_lcdif(); + mx28_init_pxp(); + mx28_init_dcp(); + mx28_init_battery(); + mx28_init_persistent(); + mx28_init_perfmon(); + mx28_init_otp(); + return 0; +} + +static struct __initdata map_desc mx28_io_desc[] = { + { + .virtual = MX28_SOC_IO_VIRT_BASE, + .pfn = __phys_to_pfn(MX28_SOC_IO_PHYS_BASE), + .length = MX28_SOC_IO_AREA_SIZE, + .type = MT_DEVICE, + }, + { + .virtual = MX28_OCRAM_BASE, + .pfn = __phys_to_pfn(MX28_OCRAM_PHBASE), + .length = MX28_OCRAM_SIZE, + .type = MT_DEVICE, + } +}; + +void __init mx28_map_io(void) +{ + iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); +} + +void __init mx28_irq_init(void) +{ + avic_init_irq(IO_ADDRESS(ICOLL_PHYS_ADDR), ARCH_NR_IRQS); +} + +static void mx28_timer_init(void) +{ + int i, reg; + mx28_clock_init(); + + mx28_timer.clk = clk_get(NULL, "clk_32k"); + if (mx28_timer.clk == NULL || IS_ERR(mx28_timer.clk)) + return; + __raw_writel(BM_TIMROT_ROTCTRL_SFTRST, + mx28_timer.base + HW_TIMROT_ROTCTRL_CLR); + for (i = 0; i < 10000; i++) { + reg = __raw_readl(mx28_timer.base + HW_TIMROT_ROTCTRL); + if (!(reg & BM_TIMROT_ROTCTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return; + __raw_writel(BM_TIMROT_ROTCTRL_CLKGATE, + mx28_timer.base + HW_TIMROT_ROTCTRL_CLR); + + reg = __raw_readl(mx28_timer.base + HW_TIMROT_ROTCTRL); + for (i = 0; i < 4; i++) { + if (!(reg & (BM_TIMROT_ROTCTRL_TIM0_PRESENT << i))) + continue; + mx28_timer.id = i; + mx28_timer.irq = IRQ_TIMER0 + i; + mxs_timer_init(&mx28_timer); + return; + } +} + +struct mxs_sys_timer mx28_timer = { + .timer = { + .init = mx28_timer_init, + }, + .clk_sel = BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL, + .base = IO_ADDRESS(TIMROT_PHYS_ADDR), +}; + diff --git a/arch/arm/mach-mx28/device.h b/arch/arm/mach-mx28/device.h new file mode 100644 index 000000000000..6fac8f670c58 --- /dev/null +++ b/arch/arm/mach-mx28/device.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DEVICE_H__ +#define __ASM_ARCH_MACH_DEVICE_H__ + +extern struct mxs_sys_timer mx28_timer; + +extern void __init mx28_map_io(void); +extern void __init mx28_clock_init(void); +extern void __init mx28_irq_init(void); +extern int __init mx28_pinctrl_init(void); +extern int __init mx28_gpio_init(void); +extern int __init mx28_device_init(void); +extern void __init mx28_init_auart(void); +extern void __init +mx28_set_input_clk(unsigned long, unsigned long, unsigned long, unsigned long); + +#endif diff --git a/arch/arm/mach-mx28/emi.S b/arch/arm/mach-mx28/emi.S new file mode 100644 index 000000000000..ec25b4e942e5 --- /dev/null +++ b/arch/arm/mach-mx28/emi.S @@ -0,0 +1,220 @@ +/* + * Freescale MX28 low level RAM frequency manipulation + * + * Author: Vitaly Wool + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include + +#include +#include +#include "regs-clkctrl.h" +#include "regs-dram.h" +#include "regs-digctl.h" + +#include "emi_settings.h" + +.global cpu_arm926_switch_mm + +.align 8 +ENTRY(mxs_ram_freq_scale) + stmfd sp!, {r1 - r10, lr} + ldr r5, [r0, #SCALING_DATA_NEW_FREQ_OFFSET] + ldr r6, [r0, #SCALING_DATA_CUR_FREQ_OFFSET] + ldr r7, [r0, #SCALING_DATA_EMI_DIV_OFFSET] + mov r7, r7, LSL #BP_CLKCTRL_EMI_DIV_EMI + ldr r8, [r0, #SCALING_DATA_FRAC_DIV_OFFSET] + mov r8, r8, LSL #BP_CLKCTRL_FRAC0_EMIFRAC + + @copy memory setting to iram + mov r2, #MX28_DRAMCTRLREGNUM + adr r0, __mx28_emisetting +1: ldr r3, [r1] + str r3, [r0] + add r0, r0, #4 + add r1, r1, #4 + subs r2, r2, #1 + bne 1b + + @set temp static to iram. + adr r9, __mxs_temp_stack + + @ clean cache + ldr r1, __mxs_flush_cache_addr + mov lr, pc + mov pc, r1 + + mov r2, #MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)&0xFF + orr r2, r2, #MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)&0xFF00 + orr r2, r2, #MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)&0xFF0000 + orr r2, r2, #MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)&0xFF000000 + + mov r0, r2 + bl lock_vector_tlb + + mov r0, #MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR)&0xFF + orr r0, r0, #MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR)&0xFF00 + orr r0, r0, #MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR)&0xFF0000 + orr r0, r0, #MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR)&0xFF000000 + + @ Make sure emi not busy +2: + ldr r1, [r0, #HW_DRAM_CTL08] + tst r1, #BM_DRAM_CTL08_CONTROLLER_BUSY + bne 2b + + @ put DRAM into self refresh + ldr r1, [r0, #HW_DRAM_CTL17] + orr r1, r1, #BM_DRAM_CTL17_SREFRESH + str r1, [r0, #HW_DRAM_CTL17] +3: + ldr r1, [r0, #HW_DRAM_CTL172] + tst r1, #BM_DRAM_CTL172_CKE_STATUS + beq 3b + + ldr r1, [r0, #HW_DRAM_CTL58] + orr r1, #BF_DRAM_CTL58_INT_MASK(0x100) + str r1, [r0, #HW_DRAM_CTL58] + + @stop emi controller + ldr r1, [r0, #HW_DRAM_CTL16] + bic r1, r1, #BM_DRAM_CTL16_START + str r1, [r0, #HW_DRAM_CTL16] + + @clear lock status HW_DRAM_CTL164_CLR(BF_DRAM_CTL164_INT_ACK(0x3ff)); + ldr r1, [r0, #HW_DRAM_CTL164] + bic r1, r1, #BF_DRAM_CTL164_INT_ACK(0xff) + bic r1, r1, #BF_DRAM_CTL164_INT_ACK(0x300) + str r1, [r0, #HW_DRAM_CTL164] + + ldr r1, [r2, #HW_CLKCTRL_FRAC0] + and r1, #BM_CLKCTRL_FRAC0_EMIFRAC + ldr r3, [r2, #HW_CLKCTRL_EMI] + and r3, #BM_CLKCTRL_EMI_DIV_EMI + +/* + * The fractional divider and integer divider must be written in such + * an order to guarantee that when going from a lower frequency to a + * higher frequency that any intermediate frequencies do not exceed + * the final frequency. For this reason, we must make sure to check + * the current divider values with the new divider values and write + * them in the correct order. + */ + + ldr r9, [r2, #HW_CLKCTRL_FRAC0] + bic r9, #BM_CLKCTRL_FRAC0_EMIFRAC + orr r9, r8 + + ldr r10, [r2, #HW_CLKCTRL_EMI] + bic r10, #BM_CLKCTRL_EMI_DIV_EMI + orr r10, r7 + + cmp r8, r1 + strgt r9, [r2, #HW_CLKCTRL_FRAC0] + cmp r7, r3 + strgt r10, [r2, #HW_CLKCTRL_EMI] + + cmp r8, r1 + strlt r9, [r2, #HW_CLKCTRL_FRAC0] + cmp r7, r3 + strlt r10, [r2, #HW_CLKCTRL_EMI] + + @copy memory setting to iram + mov r3, r0 + adr r4, __mx28_emisetting + mov r6, #MX28_DRAMCTRLREGNUM +8: ldr r5, [r4] + str r5, [r3] + add r3, r3, #4 + add r4, r4, #4 + subs r6, r6, #1 + bne 8b + +7: ldr r1, [r2, #HW_CLKCTRL_EMI] + tst r1, #BM_CLKCTRL_EMI_BUSY_REF_EMI + bne 7b + + @Restart memory controller + ldr r1, [r0, #HW_DRAM_CTL16] + orr r1, #BM_DRAM_CTL16_START + str r1, [r0, #HW_DRAM_CTL16] + + /*Wait DLL is locked*/ +9: + ldr r1, [r0, #HW_DRAM_CTL21] + tst r1, #BM_DRAM_CTL21_DLLLOCKREG + beq 9b + + + @11. Exit Memory self-refresh + ldr r1, [r0, #HW_DRAM_CTL17] + bic r1, r1, #BM_DRAM_CTL17_SREFRESH + str r1, [r0, #HW_DRAM_CTL17] + + @Wait Memory device exit into self-refresh +10: + ldr r1, [r0, #HW_DRAM_CTL172] + tst r1, #BM_DRAM_CTL172_CKE_STATUS + bne 10b + + mov r2, #MX28_SOC_IO_ADDRESS(DIGCTL_PHYS_ADDR)&0xFF + orr r2, r2, #MX28_SOC_IO_ADDRESS(DIGCTL_PHYS_ADDR)&0xFF00 + orr r2, r2, #MX28_SOC_IO_ADDRESS(DIGCTL_PHYS_ADDR)&0xFF0000 + orr r2, r2, #MX28_SOC_IO_ADDRESS(DIGCTL_PHYS_ADDR)&0xFF000000 + + ldr r0, [r2, #HW_DIGCTL_MICROSECONDS]; + add r0, #100 +11: ldr r1, [r2, #HW_DIGCTL_MICROSECONDS]; + cmp r1, r0 + blt 11b + +@ restore regs and return + ldmfd sp!, {r1 - r10, lr} + mov pc, lr + + .space 0x100 +__mxs_temp_stack: + .word 0 +__mx28_emisetting: + .space MX28_DRAMCTRLREGNUM*4 + +lock_vector_tlb: + mov r1, r0 @ set r1 to the value of the address to be locked down + mcr p15,0,r1,c8,c7,1 @ invalidate TLB single entry to ensure that + @ LockAddr is not already in the TLB + mrc p15,0,r0,c10,c0,0 @ read the lockdown register + orr r0,r0,#1 @ set the preserve bit + mcr p15,0,r0,c10,c0,0 @ write to the lockdown register + ldr r1,[r1] @ TLB will miss, and entry will be loaded + mrc p15,0,r0,c10,c0,0 @ read the lockdown register (victim will have + @ incremented) + bic r0,r0,#1 @ clear preserve bit + mcr p15,0,r0,c10,c0,0 @ write to the lockdown registerADR r1,LockAddr + mov pc,lr + +__mxs_flush_cache_addr: + .word arm926_flush_kern_cache_all + +ENTRY(mxs_ram_funcs_sz) + .word . - mxs_ram_freq_scale +ENTRY(mxs_ram_freq_scale_end) diff --git a/arch/arm/mach-mx28/emi_settings.c b/arch/arm/mach-mx28/emi_settings.c new file mode 100644 index 000000000000..918e39deb439 --- /dev/null +++ b/arch/arm/mach-mx28/emi_settings.c @@ -0,0 +1,1263 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include "emi_settings.h" + +static unsigned int DRAM_REG[MX28_DRAMCTRLREGNUM]; +unsigned int *get_current_emidata() +{ + return DRAM_REG; +} + +void test_emi_change() +{ + struct mxs_emi_scaling_data emi; + void (*f) (struct mxs_emi_scaling_data *, unsigned int *); + f = (void *)MX28_OCRAM_BASE; + memcpy(f, mxs_ram_freq_scale, + (unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale); + + pr_debug("start change emi frequency test\n"); + pr_debug("begin change 133\n"); + emi.emi_div = 3; /* 130Mhz */ + emi.frac_div = 22; /* 392Mhz */ + emi.new_freq = 133; + DDR2EmiController_EDE1116_133MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 133\n"); + + pr_debug("begin change 166\n"); + emi.emi_div = 2; /* 160Mhz */ + emi.frac_div = 27; /* 320Mhz */ + emi.new_freq = 166; + DDR2EmiController_EDE1116_166MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 166\n"); + + pr_debug("begin change 200\n"); + emi.emi_div = 2; /* 192Mhz */ + emi.frac_div = 22; /* 392Mhz */ + emi.new_freq = 200; + DDR2EmiController_EDE1116_200MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 200\n"); + + pr_debug("begin change 166\n"); + emi.emi_div = 2; /* 166Mhz */ + emi.frac_div = 26; /* 332Mhz */ + emi.new_freq = 166; + DDR2EmiController_EDE1116_166MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 166\n"); + + pr_debug("begin change 133\n"); + emi.emi_div = 3; /* 130Mhz */ + emi.frac_div = 22; /* 392Mhz */ + emi.new_freq = 133; + DDR2EmiController_EDE1116_133MHz(); + f(&emi, get_current_emidata()); + pr_debug("end change 133\n"); + pr_debug("finish change emi frequency test\n"); +} + +void DDR2EmiController_EDE1116_133MHz(void) +{ + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02020a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00010101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x00000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x07080403; + DRAM_REG[38] = 0x04003603; + DRAM_REG[39] = 0x070000c8; + DRAM_REG[40] = 0x0200682b; + DRAM_REG[41] = 0x00020208; + DRAM_REG[42] = 0x00246c06; + DRAM_REG[43] = 0x02110409; + DRAM_REG[44] = 0x01020202; + DRAM_REG[45] = 0x00c80013; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000409; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x04090409; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020006; + DRAM_REG[71] = 0xf4004a27; + DRAM_REG[72] = 0xf4004a27; + DRAM_REG[73] = 0xf4004a27; + DRAM_REG[74] = 0xf4004a27; + DRAM_REG[75] = 0x07000300; + DRAM_REG[76] = 0x07000300; + DRAM_REG[77] = 0x07400300; + DRAM_REG[78] = 0x07400300; + DRAM_REG[79] = 0x00000005; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00001f04; + DRAM_REG[88] = 0x00001f04; + DRAM_REG[89] = 0x00001f04; + DRAM_REG[90] = 0x00001f04; + DRAM_REG[91] = 0x00001f04; + DRAM_REG[92] = 0x00001f04; + DRAM_REG[93] = 0x00001f04; + DRAM_REG[94] = 0x00001f04; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00010000; + DRAM_REG[163] = 0x00030404; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000000; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00010303; + DRAM_REG[175] = 0x01020202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x02030303; + DRAM_REG[178] = 0x21002103; + DRAM_REG[179] = 0x00040900; + DRAM_REG[180] = 0x04090409; + DRAM_REG[181] = 0x02420242; + DRAM_REG[182] = 0x02420242; + DRAM_REG[183] = 0x00040004; + DRAM_REG[184] = 0x00040004; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; + +} + +void DDR2EmiController_EDE1116_166MHz(void) +{ + + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02020a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00010101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x00000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x07080403; + DRAM_REG[38] = 0x06004303; + DRAM_REG[39] = 0x090000c8; + DRAM_REG[40] = 0x02008236; + DRAM_REG[41] = 0x0002030a; + DRAM_REG[42] = 0x002d8908; + DRAM_REG[43] = 0x0316050e; + DRAM_REG[44] = 0x02030202; + DRAM_REG[45] = 0x00c80017; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xff000303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x0000050e; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x050e050e; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020007; + DRAM_REG[71] = 0xf5004a27; + DRAM_REG[72] = 0xf5004a27; + DRAM_REG[73] = 0xf5004a27; + DRAM_REG[74] = 0xf5004a27; + DRAM_REG[75] = 0x07000300; + DRAM_REG[76] = 0x07000300; + DRAM_REG[77] = 0x07400300; + DRAM_REG[78] = 0x07400300; + DRAM_REG[79] = 0x00000006; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00001f04; + DRAM_REG[88] = 0x00001f04; + DRAM_REG[89] = 0x00001f04; + DRAM_REG[90] = 0x00001f04; + DRAM_REG[91] = 0x00001f04; + DRAM_REG[92] = 0x00001f04; + DRAM_REG[93] = 0x00001f04; + DRAM_REG[94] = 0x00001f04; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00010000; + DRAM_REG[163] = 0x00030404; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000000; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00010303; + DRAM_REG[175] = 0x01020202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x02040303; + DRAM_REG[178] = 0x21002103; + DRAM_REG[179] = 0x00050e00; + DRAM_REG[180] = 0x050e050e; + DRAM_REG[181] = 0x04420442; + DRAM_REG[182] = 0x04420442; + DRAM_REG[183] = 0x00040004; + DRAM_REG[184] = 0x00040004; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; + +} + +void DDR2EmiController_EDE1116_200MHz(void) +{ + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02020a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00010101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x00000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x07080403; + DRAM_REG[38] = 0x06005003; + DRAM_REG[39] = 0x0a0000c8; + DRAM_REG[40] = 0x02009c40; + DRAM_REG[41] = 0x0002030c; + DRAM_REG[42] = 0x0036a609; + DRAM_REG[43] = 0x031a0612; + DRAM_REG[44] = 0x02030202; + DRAM_REG[45] = 0x00c8001c; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000612; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x06120612; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020007; + DRAM_REG[71] = 0xf4004a27; + DRAM_REG[72] = 0xf4004a27; + DRAM_REG[73] = 0xf4004a27; + DRAM_REG[74] = 0xf4004a27; + DRAM_REG[75] = 0x07000300; + DRAM_REG[76] = 0x07000300; + DRAM_REG[77] = 0x07400300; + DRAM_REG[78] = 0x07400300; + DRAM_REG[79] = 0x00000005; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00001f04; + DRAM_REG[88] = 0x00001f04; + DRAM_REG[89] = 0x00001f04; + DRAM_REG[90] = 0x00001f04; + DRAM_REG[91] = 0x00001f04; + DRAM_REG[92] = 0x00001f04; + DRAM_REG[93] = 0x00001f04; + DRAM_REG[94] = 0x00001f04; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00010000; + DRAM_REG[163] = 0x00030404; + DRAM_REG[164] = 0x00000003; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000000; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00010303; + DRAM_REG[175] = 0x01020202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x02040303; + DRAM_REG[178] = 0x21002103; + DRAM_REG[179] = 0x00061200; + DRAM_REG[180] = 0x06120612; + DRAM_REG[181] = 0x04420442; + DRAM_REG[182] = 0x04420442; + DRAM_REG[183] = 0x00040004; + DRAM_REG[184] = 0x00040004; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; + +} +void mDDREmiController_24MHz(void) +{ + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000001; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02010a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00000101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x01000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x05060301; + DRAM_REG[38] = 0x02000001; + DRAM_REG[39] = 0x06000000; + DRAM_REG[40] = 0x020012c0; + DRAM_REG[41] = 0x00020102; + DRAM_REG[42] = 0x00068601; + DRAM_REG[43] = 0x01030055; + DRAM_REG[44] = 0x03010001; + DRAM_REG[45] = 0x00040004; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000055; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x00550055; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020006; + DRAM_REG[71] = 0xf3004925; + DRAM_REG[72] = 0xf3004925; + DRAM_REG[73] = 0xf3004925; + DRAM_REG[74] = 0xf3004925; + DRAM_REG[75] = 0x07400300; + DRAM_REG[76] = 0x07400300; + DRAM_REG[77] = 0x07400300; + DRAM_REG[78] = 0x07400300; + DRAM_REG[79] = 0x00800004; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x1034a138; + DRAM_REG[88] = 0x1034a138; + DRAM_REG[89] = 0x1034a138; + DRAM_REG[90] = 0x1034a138; + DRAM_REG[91] = 0x00329f53; + DRAM_REG[92] = 0x00329f53; + DRAM_REG[93] = 0x00329f53; + DRAM_REG[94] = 0x00329f53; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00000000; + DRAM_REG[163] = 0x00010301; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000100; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00020303; + DRAM_REG[175] = 0x01010202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x01010101; + DRAM_REG[178] = 0x21002101; + DRAM_REG[179] = 0x00005500; + DRAM_REG[180] = 0x00550055; + DRAM_REG[181] = 0x00320032; + DRAM_REG[182] = 0x00320032; + DRAM_REG[183] = 0x00000000; + DRAM_REG[184] = 0x00000000; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; +} + +void mDDREmiController_133MHz(void) +{ + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02010a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00000101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x01000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x07060301; + DRAM_REG[38] = 0x04000001; + DRAM_REG[39] = 0x0a000000; + DRAM_REG[40] = 0x02000020; + DRAM_REG[41] = 0x00020208; + DRAM_REG[42] = 0x00246c06; + DRAM_REG[43] = 0x020f0200; + DRAM_REG[44] = 0x03020002; + DRAM_REG[45] = 0x00150013; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000200; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x02000200; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020006; + DRAM_REG[71] = 0xf3004b27; + DRAM_REG[72] = 0xf3004b27; + DRAM_REG[73] = 0xf3004b27; + DRAM_REG[74] = 0xf3004b27; + DRAM_REG[75] = 0x07400310; + DRAM_REG[76] = 0x07400310; + DRAM_REG[77] = 0x07400310; + DRAM_REG[78] = 0x07400310; + DRAM_REG[79] = 0x00800004; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00099f36; + DRAM_REG[88] = 0x00099f36; + DRAM_REG[89] = 0x00099f36; + DRAM_REG[90] = 0x00099f36; + DRAM_REG[91] = 0x00091f0f; + DRAM_REG[92] = 0x00091f0f; + DRAM_REG[93] = 0x00091f0f; + DRAM_REG[94] = 0x00091f0f; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00000000; + DRAM_REG[163] = 0x00010301; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000100; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00010303; + DRAM_REG[175] = 0x01010202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x01020101; + DRAM_REG[178] = 0x21002101; + DRAM_REG[179] = 0x00020000; + DRAM_REG[180] = 0x02000200; + DRAM_REG[181] = 0x00320032; + DRAM_REG[182] = 0x00320032; + DRAM_REG[183] = 0x00000000; + DRAM_REG[184] = 0x00000000; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; +} + +void mDDREmiController_200MHz(void) +{ + + DRAM_REG[0] = 0x00000000; + DRAM_REG[1] = 0x00000000; + DRAM_REG[2] = 0x00000000; + DRAM_REG[3] = 0x00000000; + DRAM_REG[4] = 0x00000000; + DRAM_REG[5] = 0x00000000; + DRAM_REG[6] = 0x00000000; + DRAM_REG[7] = 0x00000000; + DRAM_REG[8] = 0x00000000; + DRAM_REG[9] = 0x00000000; + DRAM_REG[10] = 0x00000000; + DRAM_REG[11] = 0x00000000; + DRAM_REG[12] = 0x00000000; + DRAM_REG[13] = 0x00000000; + DRAM_REG[14] = 0x00000000; + DRAM_REG[15] = 0x00000000; + DRAM_REG[16] = 0x00000000; + DRAM_REG[17] = 0x00000100; + DRAM_REG[18] = 0x00000000; + DRAM_REG[19] = 0x00000000; + DRAM_REG[20] = 0x00000000; + DRAM_REG[21] = 0x00000000; + DRAM_REG[22] = 0x00000000; + DRAM_REG[23] = 0x00000000; + DRAM_REG[24] = 0x00000000; + DRAM_REG[25] = 0x00000000; + DRAM_REG[26] = 0x00010101; + DRAM_REG[27] = 0x01010101; + DRAM_REG[28] = 0x000f0f01; + DRAM_REG[29] = 0x0f02010a; + DRAM_REG[30] = 0x00000000; + DRAM_REG[31] = 0x00000101; + DRAM_REG[32] = 0x00000100; + DRAM_REG[33] = 0x00000100; + DRAM_REG[34] = 0x01000000; + DRAM_REG[35] = 0x00000002; + DRAM_REG[36] = 0x01010000; + DRAM_REG[37] = 0x08060301; + DRAM_REG[38] = 0x06000001; + DRAM_REG[39] = 0x0a000000; + DRAM_REG[40] = 0x02000020; + DRAM_REG[41] = 0x0002030b; + DRAM_REG[42] = 0x0036a608; + DRAM_REG[43] = 0x03160305; + DRAM_REG[44] = 0x03030002; + DRAM_REG[45] = 0x001f001c; + DRAM_REG[46] = 0x00000000; + DRAM_REG[47] = 0x00000000; + DRAM_REG[48] = 0x00012100; + DRAM_REG[49] = 0xffff0303; + DRAM_REG[50] = 0x00012100; + DRAM_REG[51] = 0xffff0303; + DRAM_REG[52] = 0x00012100; + DRAM_REG[53] = 0xffff0303; + DRAM_REG[54] = 0x00012100; + DRAM_REG[55] = 0xffff0303; + DRAM_REG[56] = 0x00000003; + DRAM_REG[57] = 0x00000000; + DRAM_REG[58] = 0x00000000; + DRAM_REG[59] = 0x00000000; + DRAM_REG[60] = 0x00000000; + DRAM_REG[61] = 0x00000000; + DRAM_REG[62] = 0x00000000; + DRAM_REG[63] = 0x00000000; + DRAM_REG[64] = 0x00000000; + DRAM_REG[65] = 0x00000000; + DRAM_REG[66] = 0x00000305; + DRAM_REG[67] = 0x01000f02; + DRAM_REG[68] = 0x03050305; + DRAM_REG[69] = 0x00000200; + DRAM_REG[70] = 0x00020007; + DRAM_REG[71] = 0xf4004b27; + DRAM_REG[72] = 0xf4004b27; + DRAM_REG[73] = 0xf4004b27; + DRAM_REG[74] = 0xf4004b27; + DRAM_REG[75] = 0x07000310; + DRAM_REG[76] = 0x07000310; + DRAM_REG[77] = 0x07000310; + DRAM_REG[78] = 0x07000310; + DRAM_REG[79] = 0x00800005; + DRAM_REG[80] = 0x00000000; + DRAM_REG[81] = 0x00000000; + DRAM_REG[82] = 0x01000000; + DRAM_REG[83] = 0x01020408; + DRAM_REG[84] = 0x08040201; + DRAM_REG[85] = 0x000f1133; + DRAM_REG[86] = 0x00000000; + DRAM_REG[87] = 0x00069f24; + DRAM_REG[88] = 0x00069f24; + DRAM_REG[89] = 0x00069f24; + DRAM_REG[90] = 0x00069f24; + DRAM_REG[91] = 0x00061f0a; + DRAM_REG[92] = 0x00061f0a; + DRAM_REG[93] = 0x00061f0a; + DRAM_REG[94] = 0x00061f0a; + DRAM_REG[95] = 0x00000000; + DRAM_REG[96] = 0x00000000; + DRAM_REG[97] = 0x00000000; + DRAM_REG[98] = 0x00000000; + DRAM_REG[99] = 0x00000000; + DRAM_REG[100] = 0x00000000; + DRAM_REG[101] = 0x00000000; + DRAM_REG[102] = 0x00000000; + DRAM_REG[103] = 0x00000000; + DRAM_REG[104] = 0x00000000; + DRAM_REG[105] = 0x00000000; + DRAM_REG[106] = 0x00000000; + DRAM_REG[107] = 0x00000000; + DRAM_REG[108] = 0x00000000; + DRAM_REG[109] = 0x00000000; + DRAM_REG[110] = 0x00000000; + DRAM_REG[111] = 0x00000000; + DRAM_REG[112] = 0x00000000; + DRAM_REG[113] = 0x00000000; + DRAM_REG[114] = 0x00000000; + DRAM_REG[115] = 0x00000000; + DRAM_REG[116] = 0x00000000; + DRAM_REG[117] = 0x00000000; + DRAM_REG[118] = 0x00000000; + DRAM_REG[119] = 0x00000000; + DRAM_REG[120] = 0x00000000; + DRAM_REG[121] = 0x00000000; + DRAM_REG[122] = 0x00000000; + DRAM_REG[123] = 0x00000000; + DRAM_REG[124] = 0x00000000; + DRAM_REG[125] = 0x00000000; + DRAM_REG[126] = 0x00000000; + DRAM_REG[127] = 0x00000000; + DRAM_REG[128] = 0x00000000; + DRAM_REG[129] = 0x00000000; + DRAM_REG[130] = 0x00000000; + DRAM_REG[131] = 0x00000000; + DRAM_REG[132] = 0x00000000; + DRAM_REG[133] = 0x00000000; + DRAM_REG[134] = 0x00000000; + DRAM_REG[135] = 0x00000000; + DRAM_REG[136] = 0x00000000; + DRAM_REG[137] = 0x00000000; + DRAM_REG[138] = 0x00000000; + DRAM_REG[139] = 0x00000000; + DRAM_REG[140] = 0x00000000; + DRAM_REG[141] = 0x00000000; + DRAM_REG[142] = 0x00000000; + DRAM_REG[143] = 0x00000000; + DRAM_REG[144] = 0x00000000; + DRAM_REG[145] = 0x00000000; + DRAM_REG[146] = 0x00000000; + DRAM_REG[147] = 0x00000000; + DRAM_REG[148] = 0x00000000; + DRAM_REG[149] = 0x00000000; + DRAM_REG[150] = 0x00000000; + DRAM_REG[151] = 0x00000000; + DRAM_REG[152] = 0x00000000; + DRAM_REG[153] = 0x00000000; + DRAM_REG[154] = 0x00000000; + DRAM_REG[155] = 0x00000000; + DRAM_REG[156] = 0x00000000; + DRAM_REG[157] = 0x00000000; + DRAM_REG[158] = 0x00000000; + DRAM_REG[159] = 0x00000000; + DRAM_REG[160] = 0x00000000; + DRAM_REG[161] = 0x00000000; + DRAM_REG[162] = 0x00000000; + DRAM_REG[163] = 0x00010301; + DRAM_REG[164] = 0x00000002; + DRAM_REG[165] = 0x00000000; + DRAM_REG[166] = 0x00000000; + DRAM_REG[167] = 0x00000000; + DRAM_REG[168] = 0x00000000; + DRAM_REG[169] = 0x00000000; + DRAM_REG[170] = 0x00000000; + DRAM_REG[171] = 0x01010000; + DRAM_REG[172] = 0x01000100; + DRAM_REG[173] = 0x03030000; + DRAM_REG[174] = 0x00020303; + DRAM_REG[175] = 0x01010202; + DRAM_REG[176] = 0x00000000; + DRAM_REG[177] = 0x01030101; + DRAM_REG[178] = 0x21002101; + DRAM_REG[179] = 0x00030500; + DRAM_REG[180] = 0x03050305; + DRAM_REG[181] = 0x00320032; + DRAM_REG[182] = 0x00320032; + DRAM_REG[183] = 0x00000000; + DRAM_REG[184] = 0x00000000; + DRAM_REG[185] = 0x00000000; + DRAM_REG[186] = 0x00000000; + DRAM_REG[187] = 0x00000000; + DRAM_REG[188] = 0x00000000; + DRAM_REG[189] = 0xffffffff; +} + + diff --git a/arch/arm/mach-mx28/emi_settings.h b/arch/arm/mach-mx28/emi_settings.h new file mode 100644 index 000000000000..d22261fc3522 --- /dev/null +++ b/arch/arm/mach-mx28/emi_settings.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _EMI_SETTINGS_H_ +#define _EMI_SETTINGS_H_ + +#define MX28_DRAMCTRLREGNUM 190 + +#define SCALING_DATA_EMI_DIV_OFFSET 0 +#define SCALING_DATA_FRAC_DIV_OFFSET 4 +#define SCALING_DATA_CUR_FREQ_OFFSET 8 +#define SCALING_DATA_NEW_FREQ_OFFSET 12 + +#ifndef __ASSEMBLER__ +void mxs_ram_freq_scale_end(); +void DDR2EmiController_EDE1116_133MHz(void); +void DDR2EmiController_EDE1116_166MHz(void); +void DDR2EmiController_EDE1116_200MHz(void); +void mDDREmiController_24MHz(void); +void mDDREmiController_133MHz(void); +void mDDREmiController_200MHz(void); +unsigned int *get_current_emidata(); +#endif + +#endif diff --git a/arch/arm/mach-mx28/gpio.c b/arch/arm/mach-mx28/gpio.c new file mode 100644 index 000000000000..4f7d42422c78 --- /dev/null +++ b/arch/arm/mach-mx28/gpio.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx28_gpio_direction(struct mxs_gpio_port *port, int pin, unsigned int input) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (input) + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_CLR); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_SET); + + return 0; +} + +static int mx28_gpio_get(struct mxs_gpio_port *port, int pin) +{ + unsigned int data; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + data = __raw_readl(base + HW_PINCTRL_DIN0); + return data & (1 << pin); +} + +static void mx28_gpio_set(struct mxs_gpio_port *port, int pin, int data) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + if (data) + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_CLR); +} + +static unsigned int mx28_gpio_irq_stat(struct mxs_gpio_port *port) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = __raw_readl(base + HW_PINCTRL_IRQSTAT0); + mask &= __raw_readl(base + HW_PINCTRL_IRQEN0); + return mask; +} + +static int +mx28_gpio_set_irq_type(struct mxs_gpio_port *port, int pin, unsigned int type) +{ + unsigned int level, pol; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + switch (type) { + case IRQ_TYPE_EDGE_RISING: + level = 0; + pol = 1; + break; + case IRQ_TYPE_EDGE_FALLING: + level = 0; + pol = 0; + break; + case IRQ_TYPE_LEVEL_HIGH: + level = 1; + pol = 1; + break; + case IRQ_TYPE_LEVEL_LOW: + level = 1; + pol = 0; + break; + default: + pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", + __func__, type); + return -ENXIO; + } + + if (level) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_CLR); + + if (pol) + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_SET); + else + __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_CLR); + + return 0; +} + +static void mx28_gpio_unmask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_SET); +} + +static void mx28_gpio_mask_irq(struct mxs_gpio_port *port, int pin) +{ + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_CLR); +} + +static void mx28_gpio_ack_irq(struct mxs_gpio_port *port, int pin) +{ + unsigned int mask; + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id; + mask = 1 << pin; + if (mask) + __raw_writel(mask, base + HW_PINCTRL_IRQSTAT0_CLR); +} + +static struct mxs_gpio_port mx28_gpios[] = { + { + .irq = IRQ_GPIO0, + }, + { + .irq = IRQ_GPIO1, + }, + { + .irq = IRQ_GPIO2, + }, + { + .irq = IRQ_GPIO3, + }, + { + .irq = IRQ_GPIO4, + }, +}; + +static struct mxs_gpio_chip mx28_gpio_chip = { + .set_dir = mx28_gpio_direction, + .get = mx28_gpio_get, + .set = mx28_gpio_set, + .get_irq_stat = mx28_gpio_irq_stat, + .set_irq_type = mx28_gpio_set_irq_type, + .unmask_irq = mx28_gpio_unmask_irq, + .mask_irq = mx28_gpio_mask_irq, + .ack_irq = mx28_gpio_ack_irq, +}; + +int __init mx28_gpio_init(void) +{ + int i; + unsigned int reg; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + reg = __raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL); + for (i = 0; i < ARRAY_SIZE(mx28_gpios); i++) { + void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * i; + if (!(reg & (BM_PINCTRL_CTRL_PRESENT0 << i))) + continue; + mxs_set_gpio_chip(&mx28_gpios[i], &mx28_gpio_chip); + mx28_gpios[i].id = i; + __raw_writel(0, base + HW_PINCTRL_IRQEN0); + __raw_writel(0xFFFFFFFF, base + HW_PINCTRL_PIN2IRQ0); + mx28_gpios[i].child_irq = MXS_GPIO_IRQ_START + + (i * PINS_PER_BANK); + mxs_add_gpio_port(&mx28_gpios[i]); + } + return 0; +} diff --git a/arch/arm/mach-mx28/include/mach/dma.h b/arch/arm/mach-mx28/include/mach/dma.h new file mode 100644 index 000000000000..ad8076c5d8f3 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/dma.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DMA_H__ +#define __ASM_ARCH_MACH_DMA_H__ + +enum { + MXS_DMA_CHANNEL_AHB_APBH = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_HSADC, + MXS_DMA_CHANNEL_AHB_APBH_LCDIF, + MXS_DMA_CHANNEL_AHB_APBH_14, + MXS_DMA_CHANNEL_AHB_APBH_15, + MXS_DMA_CHANNEL_AHB_APBX = 16, + MXS_DMA_CHANNEL_AHB_APBX_UART4_RX = MXS_DMA_CHANNEL_AHB_APBX, + MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + MXS_DMA_CHANNEL_AHB_APBX_SPDIF, + MXS_DMA_CHANNEL_AHB_APBX_03, + MXS_DMA_CHANNEL_AHB_APBX_SAIF0, + MXS_DMA_CHANNEL_AHB_APBX_SAIF1, + MXS_DMA_CHANNEL_AHB_APBX_I2C0, + MXS_DMA_CHANNEL_AHB_APBX_I2C1, + MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + MAX_DMA_CHANNELS, +}; +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx28/include/mach/lcdif.h b/arch/arm/mach-mx28/include/mach/lcdif.h new file mode 100644 index 000000000000..23fff95968ba --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/lcdif.h @@ -0,0 +1,276 @@ +/* + * Freescale MXS LCDIF interfaces + * + * Author: Vitaly Wool + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _ARCH_ARM_LCDIF_H +#define _ARCH_ARM_LCDIF_H + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "regs-lcdif.h" + +#define REGS_LCDIF_BASE IO_ADDRESS(LCDIF_PHYS_ADDR) + +enum { + SPI_MOSI = 0, + SPI_SCLK, + SPI_CS, +}; + +struct mxs_lcd_dma_chain_info { + dma_addr_t *dma_addr_p; + unsigned offset; +}; + +enum { + MXS_LCD_PANEL_SYSTEM = 0, + MXS_LCD_PANEL_VSYNC, + MXS_LCD_PANEL_DOTCLK, + MXS_LCD_PANEL_DVI, +}; + +struct mxs_platform_bl_data; +struct mxs_platform_fb_entry { + char name[16]; + u16 x_res; + u16 y_res; + u16 bpp; + u32 cycle_time_ns; + int lcd_type; + int (*init_panel) (struct device *, dma_addr_t, int, + struct mxs_platform_fb_entry *); + void (*release_panel) (struct device *, struct mxs_platform_fb_entry *); + int (*blank_panel) (int); + void (*run_panel) (void); + void (*stop_panel) (void); + int (*pan_display) (dma_addr_t); + int (*update_panel) (void *, struct mxs_platform_fb_entry *); + struct list_head link; + struct mxs_platform_bl_data *bl_data; +}; + +struct mxs_platform_fb_data { + struct list_head list; + struct mxs_platform_fb_entry *cur; + struct mxs_platform_fb_entry *next; +}; + +#define MXS_LCDIF_PANEL_INIT 1 +#define MXS_LCDIF_PANEL_RELEASE 2 + +struct mxs_platform_bl_data { + struct list_head list; + struct regulator *regulator; + int bl_gpio; + int bl_max_intensity; + int bl_cons_intensity; + int bl_default_intensity; + int (*init_bl) (struct mxs_platform_bl_data *); + int (*set_bl_intensity) (struct mxs_platform_bl_data *, + struct backlight_device *, int); + void (*free_bl) (struct mxs_platform_bl_data *); +}; + +static inline void mxs_lcd_register_entry(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_add_tail(&pentry->link, &pdata->list); + if (!pdata->cur) + pdata->cur = pentry; +} + +static inline void mxs_lcd_move_pentry_up(struct mxs_platform_fb_entry + *pentry, struct mxs_platform_fb_data + *pdata) +{ + list_move(&pentry->link, &pdata->list); +} + +static inline int mxs_lcd_iterate_pdata(struct mxs_platform_fb_data + *pdata, + int (*func) (struct + mxs_platform_fb_entry + * pentry, void *data, + int ret_prev), void *data) +{ + struct mxs_platform_fb_entry *pentry; + int ret = 0; + list_for_each_entry(pentry, &pdata->list, link) { + ret = func(pentry, data, ret); + } + return ret; +} + +static inline void mxs_lcd_set_bl_pdata(struct mxs_platform_bl_data + *pdata) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-bl", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->dev.platform_data = pdata; +} + +void mxs_init_lcdif(void); +int mxs_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize); +void mxs_lcdif_dma_release(void); +void mxs_lcdif_run(void); +void mxs_lcdif_stop(void); +int mxs_lcdif_pan_display(dma_addr_t addr); + +int mxs_lcdif_register_client(struct notifier_block *nb); +void mxs_lcdif_unregister_client(struct notifier_block *nb); +void mxs_lcdif_notify_clients(unsigned long event, + struct mxs_platform_fb_entry *pentry); + +#ifndef FBIO_WAITFORVSYNC +#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t) +#endif + +static inline void setup_dotclk_panel(u16 v_pulse_width, + u16 v_period, + u16 v_wait_cnt, + u16 v_active, + u16 h_pulse_width, + u16 h_period, + u16 h_wait_cnt, + u16 h_active, int enable_present) +{ + u32 val; + + __raw_writel(BM_LCDIF_CTRL_DATA_SHIFT_DIR, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL_SHIFT_NUM_BITS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(7) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ + BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ + BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /* 24 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_POL | + BM_LCDIF_VDCTRL0_HSYNC_POL | + BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL); + val |= BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_OEB); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); /* vsync is output */ + + /* + * need enable sig for true RGB i/f. Or, if not true RGB, leave it + * zero. + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val |= BM_LCDIF_VDCTRL0_ENABLE_PRESENT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + /* + * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT); + val |= BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + __raw_writel(BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_CLR); + __raw_writel(v_pulse_width, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET); + + __raw_writel(BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + + __raw_writel(BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) | + BF_LCDIF_VDCTRL2_HSYNC_PERIOD(h_period), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val &= ~BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT; + val |= BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + val &= ~(BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT | + BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT); + val |= BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) | + BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val |= BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); +} + +static inline void release_dotclk_panel(void) +{ + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); +} + +#endif /* _ARCH_ARM_LCDIF_H */ diff --git a/arch/arm/mach-mx28/include/mach/mx28.h b/arch/arm/mach-mx28/include/mach/mx28.h new file mode 100644 index 000000000000..097253266709 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/mx28.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_MX28_H__ +#define __ASM_ARCH_MACH_MX28_H__ + +#include + +#define MX28_SOC_IO_PHYS_BASE 0x80000000 +#define MX28_SOC_IO_VIRT_BASE 0xF0000000 +#define MX28_SOC_IO_AREA_SIZE SZ_1M + +/* Virtual address where OCRAM is mapped */ +#define MX28_OCRAM_PHBASE 0x00000000 +#ifdef __ASSEMBLER__ +#define MX28_OCRAM_BASE 0xf1000000 +#else +#define MX28_OCRAM_BASE (void __iomem *)0xf1000000 +#endif +#define MX28_OCRAM_SIZE (128 * SZ_1K) + + +#define ICOLL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x000000) +#define HSADC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x002000) +#define APBH_DMA_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x004000) +#define PERFMON_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x006000) +#define BCH_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x00A000) +#define GPMI_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x00C000) +#define SSP0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x010000) +#define SSP1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x012000) +#define SSP2_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x014000) +#define SSP3_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x016000) +#define PINCTRL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x018000) +#define DIGCTL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x01C000) +#define ETM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x022000) +#define APBX_DMA_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x024000) +#define DCP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x028000) +#define PXP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02A000) +#define OCOTP_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02C000) +#define AXI_AHB0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x02E000) +#define LCDIF_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x030000) +#define CAN0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x032000) +#define CAN1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x034000) +#define SIMDBG_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C000) +#define SIMGPMISEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C200) +#define SIMSSPSEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C300) +#define SIMMEMSEL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C400) +#define GPIOMON_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C500) +#define SIMENET_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C700) +#define ARMJTAG_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x03C800) +#define CLKCTRL_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x040000) +#define SAIF0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x042000) +#define POWER_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x044000) +#define SAIF1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x046000) +#define LRADC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x050000) +#define SPDIF_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x054000) +#define RTC_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x056000) +#define I2C0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x058000) +#define I2C1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x05A000) +#define PWM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x064000) +#define TIMROT_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x068000) +#define AUART0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06A000) +#define AUART1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06C000) +#define AUART2_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x06E000) +#define AUART3_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x070000) +#define AUART4_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x072000) +#define DUART_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x074000) +#define USBPHY0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x07C000) +#define USBPHY1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x07E000) +#define USBCTRL0_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x080000) +#define USBCTRL1_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x090000) +#define DFLPT_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0C0000) +#define DRAM_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0E0000) +#define ENET_PHYS_ADDR (MX28_SOC_IO_PHYS_BASE + 0x0F0000) + +/* IRQ Definitions */ +#define IRQ_BATT_BRNOUT 0 +#define IRQ_VDDD_BRNOUT 1 +#define IRQ_VDDIO_BRNOUT 2 +#define IRQ_VDDA_BRNOUT 3 +#define IRQ_VDD5V_DROOP 4 +#define IRQ_DCDC4P2_BRNOUT 5 +#define IRQ_VDD5V 6 +#define IRQ_RESV7 7 +#define IRQ_CAN0 8 +#define IRQ_CAN1 9 +#define IRQ_LRADC_TOUCH 10 +#define IRQ_RESV11 11 +#define IRQ_RESV12 12 +#define IRQ_HSADC 13 +#define IRQ_IRADC_THRESH0 14 +#define IRQ_IRADC_THRESH1 15 +#define IRQ_LRADC_CH0 16 +#define IRQ_LRADC_CH1 17 +#define IRQ_LRADC_CH2 18 +#define IRQ_LRADC_CH3 19 +#define IRQ_LRADC_CH4 20 +#define IRQ_LRADC_CH5 21 +#define IRQ_LRADC_CH6 22 +#define IRQ_LRADC_CH7 23 +#define IRQ_LRADC_BUTTON0 24 +#define IRQ_LRADC_BUTTON1 25 +#define IRQ_RESV26 26 +#define IRQ_PERFMON 27 +#define IRQ_RTC_1MSEC 28 +#define IRQ_RTC_ALARM 29 +#define IRQ_RESV30 30 +#define IRQ_COMMS 31 +#define IRQ_EMI_ERR 32 +#define IRQ_RESV33 33 +#define IRQ_RESV34 34 +#define IRQ_RESV35 35 +#define IRQ_RESV36 36 +#define IRQ_RESV37 37 +#define IRQ_LCDIF 38 +#define IRQ_PXP 39 +#define IRQ_RESV40 40 +#define IRQ_BCH 41 +#define IRQ_GPMI 42 +#define IRQ_RESV43 43 +#define IRQ_RESV44 44 +#define IRQ_SPDIF_ERROR 45 +#define IRQ_RESV46 46 +#define IRQ_DUART 47 +#define IRQ_TIMER0 48 +#define IRQ_TIMER1 49 +#define IRQ_TIMER2 50 +#define IRQ_TIMER3 51 +#define IRQ_DCP_VMI 52 +#define IRQ_DCP 53 +#define IRQ_DCP_SECURE 54 +#define IRQ_RESV55 55 +#define IRQ_RESV56 56 +#define IRQ_RESV57 57 +#define IRQ_SAIF1 58 +#define IRQ_SAIF0 59 +#define IRQ_RESV60 60 +#define IRQ_RESV61 61 +#define IRQ_RESV62 62 +#define IRQ_RESV63 63 +#define IRQ_RESV64 64 +#define IRQ_RESV65 65 +#define IRQ_SPDIF_DMA 66 +#define IRQ_RESV67 67 +#define IRQ_I2C0_DMA 68 +#define IRQ_I2C1_DMA 69 +#define IRQ_AUART0_RX_DMA 70 +#define IRQ_AUART0_TX_DMA 71 +#define IRQ_AUART1_RX_DMA 72 +#define IRQ_AUART1_TX_DMA 73 +#define IRQ_AUART2_RX_DMA 74 +#define IRQ_AUART2_TX_DMA 75 +#define IRQ_AUART3_RX_DMA 76 +#define IRQ_AUART3_TX_DMA 77 +#define IRQ_AUART4_RX_DMA 78 +#define IRQ_AUART4_TX_DMA 79 +#define IRQ_SAIF0_DMA 80 +#define IRQ_SAIF1_DMA 81 +#define IRQ_SSP0_DMA 82 +#define IRQ_SSP1_DMA 83 +#define IRQ_SSP2_DMA 84 +#define IRQ_SSP3_DMA 85 +#define IRQ_LCDIF_DMA 86 +#define IRQ_HSADC_DMA 87 +#define IRQ_GPMI_DMA 88 +#define IRQ_DIGCTL_DEBUG_TRAP 89 +#define IRQ_RESV90 90 +#define IRQ_RESV91 91 +#define IRQ_USB1 92 +#define IRQ_USB0 93 +#define IRQ_USB1_WAKEUP 94 +#define IRQ_USB0_WAKEUP 95 +#define IRQ_SSP0 96 +#define IRQ_SSP1 97 +#define IRQ_SSP2 98 +#define IRQ_SSP3 99 +#define IRQ_ENET_SWI 100 +#define IRQ_ENET_MAC0 101 +#define IRQ_ENET_MAC1 102 +#define IRQ_ENET_MAC0_1588 103 +#define IRQ_ENET_MAC1_1588 104 +#define IRQ_RESV105 105 +#define IRQ_RESV106 106 +#define IRQ_RESV107 107 +#define IRQ_RESV108 108 +#define IRQ_RESV109 109 +#define IRQ_I2C1_ERROR 110 +#define IRQ_I2C0_ERROR 111 +#define IRQ_AUART0 112 +#define IRQ_AUART1 113 +#define IRQ_AUART2 114 +#define IRQ_AUART3 115 +#define IRQ_AUART4 116 +#define IRQ_RESV117 117 +#define IRQ_RESV118 118 +#define IRQ_RESV119 119 +#define IRQ_RESV120 120 +#define IRQ_RESV121 121 +#define IRQ_RESV122 122 +#define IRQ_GPIO4 123 +#define IRQ_GPIO3 124 +#define IRQ_GPIO2 125 +#define IRQ_GPIO1 126 +#define IRQ_GPIO0 127 + +#define ARCH_NR_IRQS 128 + +/* On i.MX28, all interrupt sources can be configured as FIQ */ +#define FIQ_START IRQ_BATT_BRNOUT + +#define MX28_SOC_IO_ADDRESS(x) \ + ((x) - MX28_SOC_IO_PHYS_BASE + MX28_SOC_IO_VIRT_BASE) + +#ifdef __ASSEMBLER__ +#define IO_ADDRESS(x) \ + MX28_SOC_IO_ADDRESS(x) +#else +#define IO_ADDRESS(x) \ + (void __force __iomem *) \ + (((x) >= (unsigned long)MX28_SOC_IO_PHYS_BASE) && \ + ((x) < (unsigned long)MX28_SOC_IO_PHYS_BASE + \ + MX28_SOC_IO_AREA_SIZE) ? \ + MX28_SOC_IO_ADDRESS(x) : 0xDEADBEEF) +#endif + +#ifdef CONFIG_MXS_EARLY_CONSOLE +#define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR +#define MXS_DEBUG_CONSOLE_VIRT IO_ADDRESS(DUART_PHYS_ADDR) +#endif +#endif /* __ASM_ARCH_MACH_MX28_H__ */ diff --git a/arch/arm/mach-mx28/include/mach/regs-apbh.h b/arch/arm/mach-mx28/include/mach/regs-apbh.h new file mode 100644 index 000000000000..23f26ca10e9e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-apbh.h @@ -0,0 +1,535 @@ +/* + * Freescale APBH Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H + +#define HW_APBH_CTRL0 (0x00000000) +#define HW_APBH_CTRL0_SET (0x00000004) +#define HW_APBH_CTRL0_CLR (0x00000008) +#define HW_APBH_CTRL0_TOG (0x0000000c) + +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST_EN 0x10000000 +#define BP_APBH_CTRL0_RSVD0 16 +#define BM_APBH_CTRL0_RSVD0 0x0FFF0000 +#define BF_APBH_CTRL0_RSVD0(v) \ + (((v) << 16) & BM_APBH_CTRL0_RSVD0) +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 0 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FFFF +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF 0x2000 + +#define HW_APBH_CTRL1 (0x00000010) +#define HW_APBH_CTRL1_SET (0x00000014) +#define HW_APBH_CTRL1_CLR (0x00000018) +#define HW_APBH_CTRL1_TOG (0x0000001c) + +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBH_CTRL2 (0x00000020) +#define HW_APBH_CTRL2_SET (0x00000024) +#define HW_APBH_CTRL2_CLR (0x00000028) +#define HW_APBH_CTRL2_TOG (0x0000002c) + +#define BM_APBH_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBH_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBH_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBH_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBH_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBH_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBH_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBH_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBH_CHANNEL_CTRL (0x00000030) +#define HW_APBH_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBH_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBH_CHANNEL_CTRL_TOG (0x0000003c) + +#define BP_APBH_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__LCDIF 0x2000 +#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__LCDIF 0x2000 + +#define HW_APBH_DEVSEL (0x00000040) + +#define BP_APBH_DEVSEL_CH15 30 +#define BM_APBH_DEVSEL_CH15 0xC0000000 +#define BF_APBH_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBH_DEVSEL_CH15) +#define BP_APBH_DEVSEL_CH14 28 +#define BM_APBH_DEVSEL_CH14 0x30000000 +#define BF_APBH_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBH_DEVSEL_CH14) +#define BP_APBH_DEVSEL_CH13 26 +#define BM_APBH_DEVSEL_CH13 0x0C000000 +#define BF_APBH_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBH_DEVSEL_CH13) +#define BP_APBH_DEVSEL_CH12 24 +#define BM_APBH_DEVSEL_CH12 0x03000000 +#define BF_APBH_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBH_DEVSEL_CH12) +#define BP_APBH_DEVSEL_CH11 22 +#define BM_APBH_DEVSEL_CH11 0x00C00000 +#define BF_APBH_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBH_DEVSEL_CH11) +#define BP_APBH_DEVSEL_CH10 20 +#define BM_APBH_DEVSEL_CH10 0x00300000 +#define BF_APBH_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBH_DEVSEL_CH10) +#define BP_APBH_DEVSEL_CH9 18 +#define BM_APBH_DEVSEL_CH9 0x000C0000 +#define BF_APBH_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBH_DEVSEL_CH9) +#define BP_APBH_DEVSEL_CH8 16 +#define BM_APBH_DEVSEL_CH8 0x00030000 +#define BF_APBH_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBH_DEVSEL_CH8) +#define BP_APBH_DEVSEL_CH7 14 +#define BM_APBH_DEVSEL_CH7 0x0000C000 +#define BF_APBH_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBH_DEVSEL_CH7) +#define BP_APBH_DEVSEL_CH6 12 +#define BM_APBH_DEVSEL_CH6 0x00003000 +#define BF_APBH_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBH_DEVSEL_CH6) +#define BP_APBH_DEVSEL_CH5 10 +#define BM_APBH_DEVSEL_CH5 0x00000C00 +#define BF_APBH_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBH_DEVSEL_CH5) +#define BP_APBH_DEVSEL_CH4 8 +#define BM_APBH_DEVSEL_CH4 0x00000300 +#define BF_APBH_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBH_DEVSEL_CH4) +#define BP_APBH_DEVSEL_CH3 6 +#define BM_APBH_DEVSEL_CH3 0x000000C0 +#define BF_APBH_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBH_DEVSEL_CH3) +#define BP_APBH_DEVSEL_CH2 4 +#define BM_APBH_DEVSEL_CH2 0x00000030 +#define BF_APBH_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBH_DEVSEL_CH2) +#define BP_APBH_DEVSEL_CH1 2 +#define BM_APBH_DEVSEL_CH1 0x0000000C +#define BF_APBH_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBH_DEVSEL_CH1) +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x00000003 +#define BF_APBH_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBH_DEVSEL_CH0) + +#define HW_APBH_DMA_BURST_SIZE (0x00000050) + +#define BP_APBH_DMA_BURST_SIZE_CH15 30 +#define BM_APBH_DMA_BURST_SIZE_CH15 0xC0000000 +#define BF_APBH_DMA_BURST_SIZE_CH15(v) \ + (((v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15) +#define BP_APBH_DMA_BURST_SIZE_CH14 28 +#define BM_APBH_DMA_BURST_SIZE_CH14 0x30000000 +#define BF_APBH_DMA_BURST_SIZE_CH14(v) \ + (((v) << 28) & BM_APBH_DMA_BURST_SIZE_CH14) +#define BP_APBH_DMA_BURST_SIZE_CH13 26 +#define BM_APBH_DMA_BURST_SIZE_CH13 0x0C000000 +#define BF_APBH_DMA_BURST_SIZE_CH13(v) \ + (((v) << 26) & BM_APBH_DMA_BURST_SIZE_CH13) +#define BP_APBH_DMA_BURST_SIZE_CH12 24 +#define BM_APBH_DMA_BURST_SIZE_CH12 0x03000000 +#define BF_APBH_DMA_BURST_SIZE_CH12(v) \ + (((v) << 24) & BM_APBH_DMA_BURST_SIZE_CH12) +#define BP_APBH_DMA_BURST_SIZE_CH11 22 +#define BM_APBH_DMA_BURST_SIZE_CH11 0x00C00000 +#define BF_APBH_DMA_BURST_SIZE_CH11(v) \ + (((v) << 22) & BM_APBH_DMA_BURST_SIZE_CH11) +#define BP_APBH_DMA_BURST_SIZE_CH10 20 +#define BM_APBH_DMA_BURST_SIZE_CH10 0x00300000 +#define BF_APBH_DMA_BURST_SIZE_CH10(v) \ + (((v) << 20) & BM_APBH_DMA_BURST_SIZE_CH10) +#define BP_APBH_DMA_BURST_SIZE_CH9 18 +#define BM_APBH_DMA_BURST_SIZE_CH9 0x000C0000 +#define BF_APBH_DMA_BURST_SIZE_CH9(v) \ + (((v) << 18) & BM_APBH_DMA_BURST_SIZE_CH9) +#define BP_APBH_DMA_BURST_SIZE_CH8 16 +#define BM_APBH_DMA_BURST_SIZE_CH8 0x00030000 +#define BF_APBH_DMA_BURST_SIZE_CH8(v) \ + (((v) << 16) & BM_APBH_DMA_BURST_SIZE_CH8) +#define BP_APBH_DMA_BURST_SIZE_CH7 14 +#define BM_APBH_DMA_BURST_SIZE_CH7 0x0000C000 +#define BF_APBH_DMA_BURST_SIZE_CH7(v) \ + (((v) << 14) & BM_APBH_DMA_BURST_SIZE_CH7) +#define BP_APBH_DMA_BURST_SIZE_CH6 12 +#define BM_APBH_DMA_BURST_SIZE_CH6 0x00003000 +#define BF_APBH_DMA_BURST_SIZE_CH6(v) \ + (((v) << 12) & BM_APBH_DMA_BURST_SIZE_CH6) +#define BP_APBH_DMA_BURST_SIZE_CH5 10 +#define BM_APBH_DMA_BURST_SIZE_CH5 0x00000C00 +#define BF_APBH_DMA_BURST_SIZE_CH5(v) \ + (((v) << 10) & BM_APBH_DMA_BURST_SIZE_CH5) +#define BP_APBH_DMA_BURST_SIZE_CH4 8 +#define BM_APBH_DMA_BURST_SIZE_CH4 0x00000300 +#define BF_APBH_DMA_BURST_SIZE_CH4(v) \ + (((v) << 8) & BM_APBH_DMA_BURST_SIZE_CH4) +#define BP_APBH_DMA_BURST_SIZE_CH3 6 +#define BM_APBH_DMA_BURST_SIZE_CH3 0x000000C0 +#define BF_APBH_DMA_BURST_SIZE_CH3(v) \ + (((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3) +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH2 4 +#define BM_APBH_DMA_BURST_SIZE_CH2 0x00000030 +#define BF_APBH_DMA_BURST_SIZE_CH2(v) \ + (((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2) +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH1 2 +#define BM_APBH_DMA_BURST_SIZE_CH1 0x0000000C +#define BF_APBH_DMA_BURST_SIZE_CH1(v) \ + (((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1) +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH0 0 +#define BM_APBH_DMA_BURST_SIZE_CH0 0x00000003 +#define BF_APBH_DMA_BURST_SIZE_CH0(v) \ + (((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0) +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST8 0x2 + +#define HW_APBH_DEBUG (0x00000060) + +#define BP_APBH_DEBUG_RSVD 1 +#define BM_APBH_DEBUG_RSVD 0xFFFFFFFE +#define BF_APBH_DEBUG_RSVD(v) \ + (((v) << 1) & BM_APBH_DEBUG_RSVD) +#define BM_APBH_DEBUG_GPMI_ONE_FIFO 0x00000001 + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBH_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 + +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBH_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_READY 0x1F + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBH_VERSION (0x00000800) + +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 +#define BF_APBH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBH_VERSION_MAJOR) +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 +#define BF_APBH_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBH_VERSION_MINOR) +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF +#define BF_APBH_VERSION_STEP(v) \ + (((v) << 0) & BM_APBH_VERSION_STEP) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-i2c.h b/arch/arm/mach-mx28/include/mach/regs-i2c.h new file mode 100644 index 000000000000..71997445f44e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-i2c.h @@ -0,0 +1,498 @@ +/* + * Freescale I2C Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.54 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___I2C_H +#define __ARCH_ARM___I2C_H + + +#define HW_I2C_CTRL0 (0x00000000) +#define HW_I2C_CTRL0_SET (0x00000004) +#define HW_I2C_CTRL0_CLR (0x00000008) +#define HW_I2C_CTRL0_TOG (0x0000000c) + +#define BM_I2C_CTRL0_SFTRST 0x80000000 +#define BV_I2C_CTRL0_SFTRST__RUN 0x0 +#define BV_I2C_CTRL0_SFTRST__RESET 0x1 +#define BM_I2C_CTRL0_CLKGATE 0x40000000 +#define BV_I2C_CTRL0_CLKGATE__RUN 0x0 +#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_I2C_CTRL0_RUN 0x20000000 +#define BV_I2C_CTRL0_RUN__HALT 0x0 +#define BV_I2C_CTRL0_RUN__RUN 0x1 +#define BM_I2C_CTRL0_RSVD2 0x10000000 +#define BM_I2C_CTRL0_PRE_ACK 0x08000000 +#define BM_I2C_CTRL0_ACKNOWLEDGE 0x04000000 +#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_CTRL0_RSVD1 0x01000000 +#define BM_I2C_CTRL0_MULTI_MASTER 0x00800000 +#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_CTRL0_CLOCK_HELD 0x00400000 +#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 +#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 +#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 +#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 +#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 +#define BM_I2C_CTRL0_DIRECTION 0x00010000 +#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 +#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_CTRL0_XFER_COUNT 0 +#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_I2C_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_CTRL0_XFER_COUNT) + +#define HW_I2C_TIMING0 (0x00000010) +#define HW_I2C_TIMING0_SET (0x00000014) +#define HW_I2C_TIMING0_CLR (0x00000018) +#define HW_I2C_TIMING0_TOG (0x0000001c) + +#define BP_I2C_TIMING0_RSVD2 26 +#define BM_I2C_TIMING0_RSVD2 0xFC000000 +#define BF_I2C_TIMING0_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING0_RSVD2) +#define BP_I2C_TIMING0_HIGH_COUNT 16 +#define BM_I2C_TIMING0_HIGH_COUNT 0x03FF0000 +#define BF_I2C_TIMING0_HIGH_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING0_HIGH_COUNT) +#define BP_I2C_TIMING0_RSVD1 10 +#define BM_I2C_TIMING0_RSVD1 0x0000FC00 +#define BF_I2C_TIMING0_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING0_RSVD1) +#define BP_I2C_TIMING0_RCV_COUNT 0 +#define BM_I2C_TIMING0_RCV_COUNT 0x000003FF +#define BF_I2C_TIMING0_RCV_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING0_RCV_COUNT) + +#define HW_I2C_TIMING1 (0x00000020) +#define HW_I2C_TIMING1_SET (0x00000024) +#define HW_I2C_TIMING1_CLR (0x00000028) +#define HW_I2C_TIMING1_TOG (0x0000002c) + +#define BP_I2C_TIMING1_RSVD2 26 +#define BM_I2C_TIMING1_RSVD2 0xFC000000 +#define BF_I2C_TIMING1_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING1_RSVD2) +#define BP_I2C_TIMING1_LOW_COUNT 16 +#define BM_I2C_TIMING1_LOW_COUNT 0x03FF0000 +#define BF_I2C_TIMING1_LOW_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING1_LOW_COUNT) +#define BP_I2C_TIMING1_RSVD1 10 +#define BM_I2C_TIMING1_RSVD1 0x0000FC00 +#define BF_I2C_TIMING1_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING1_RSVD1) +#define BP_I2C_TIMING1_XMIT_COUNT 0 +#define BM_I2C_TIMING1_XMIT_COUNT 0x000003FF +#define BF_I2C_TIMING1_XMIT_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING1_XMIT_COUNT) + +#define HW_I2C_TIMING2 (0x00000030) +#define HW_I2C_TIMING2_SET (0x00000034) +#define HW_I2C_TIMING2_CLR (0x00000038) +#define HW_I2C_TIMING2_TOG (0x0000003c) + +#define BP_I2C_TIMING2_RSVD2 26 +#define BM_I2C_TIMING2_RSVD2 0xFC000000 +#define BF_I2C_TIMING2_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING2_RSVD2) +#define BP_I2C_TIMING2_BUS_FREE 16 +#define BM_I2C_TIMING2_BUS_FREE 0x03FF0000 +#define BF_I2C_TIMING2_BUS_FREE(v) \ + (((v) << 16) & BM_I2C_TIMING2_BUS_FREE) +#define BP_I2C_TIMING2_RSVD1 10 +#define BM_I2C_TIMING2_RSVD1 0x0000FC00 +#define BF_I2C_TIMING2_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING2_RSVD1) +#define BP_I2C_TIMING2_LEADIN_COUNT 0 +#define BM_I2C_TIMING2_LEADIN_COUNT 0x000003FF +#define BF_I2C_TIMING2_LEADIN_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING2_LEADIN_COUNT) + +#define HW_I2C_CTRL1 (0x00000040) +#define HW_I2C_CTRL1_SET (0x00000044) +#define HW_I2C_CTRL1_CLR (0x00000048) +#define HW_I2C_CTRL1_TOG (0x0000004c) + +#define BM_I2C_CTRL1_RSVD1 0x80000000 +#define BM_I2C_CTRL1_RD_QUEUE_IRQ 0x40000000 +#define BV_I2C_CTRL1_RD_QUEUE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_RD_QUEUE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_WR_QUEUE_IRQ 0x20000000 +#define BV_I2C_CTRL1_WR_QUEUE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_WR_QUEUE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING 0x0 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR 0x1 +#define BM_I2C_CTRL1_ACK_MODE 0x08000000 +#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW 0x0 +#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW 0x1 +#define BM_I2C_CTRL1_FORCE_DATA_IDLE 0x04000000 +#define BM_I2C_CTRL1_FORCE_CLK_IDLE 0x02000000 +#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x01000000 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 +#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 +#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0x00FF0000 +#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) \ + (((v) << 16) & BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE) +#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x00008000 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x00004000 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x00002000 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x00001000 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x00000800 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x00000400 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x00000200 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x00000100 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 +#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 + +#define HW_I2C_STAT (0x00000050) + +#define BM_I2C_STAT_MASTER_PRESENT 0x80000000 +#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 +#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 +#define BM_I2C_STAT_GOT_A_NAK 0x10000000 +#define BV_I2C_STAT_GOT_A_NAK__NO_NAK 0x0 +#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK 0x1 +#define BP_I2C_STAT_RSVD1 24 +#define BM_I2C_STAT_RSVD1 0x0F000000 +#define BF_I2C_STAT_RSVD1(v) \ + (((v) << 24) & BM_I2C_STAT_RSVD1) +#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 +#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0x00FF0000 +#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) \ + (((v) << 16) & BM_I2C_STAT_RCVD_SLAVE_ADDR) +#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x00008000 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 +#define BM_I2C_STAT_SLAVE_FOUND 0x00004000 +#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 +#define BM_I2C_STAT_SLAVE_SEARCHING 0x00002000 +#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 +#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x00001000 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 +#define BM_I2C_STAT_BUS_BUSY 0x00000800 +#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 +#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 +#define BM_I2C_STAT_CLK_GEN_BUSY 0x00000400 +#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 +#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 +#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x00000200 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_SLAVE_BUSY 0x00000100 +#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x00000080 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x00000040 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x00000020 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x00000010 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x00000008 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x00000004 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x00000002 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x00000001 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 + +#define HW_I2C_QUEUECTRL (0x00000060) +#define HW_I2C_QUEUECTRL_SET (0x00000064) +#define HW_I2C_QUEUECTRL_CLR (0x00000068) +#define HW_I2C_QUEUECTRL_TOG (0x0000006c) + +#define BP_I2C_QUEUECTRL_RSVD3 21 +#define BM_I2C_QUEUECTRL_RSVD3 0xFFE00000 +#define BF_I2C_QUEUECTRL_RSVD3(v) \ + (((v) << 21) & BM_I2C_QUEUECTRL_RSVD3) +#define BP_I2C_QUEUECTRL_RD_THRESH 16 +#define BM_I2C_QUEUECTRL_RD_THRESH 0x001F0000 +#define BF_I2C_QUEUECTRL_RD_THRESH(v) \ + (((v) << 16) & BM_I2C_QUEUECTRL_RD_THRESH) +#define BP_I2C_QUEUECTRL_RSVD2 13 +#define BM_I2C_QUEUECTRL_RSVD2 0x0000E000 +#define BF_I2C_QUEUECTRL_RSVD2(v) \ + (((v) << 13) & BM_I2C_QUEUECTRL_RSVD2) +#define BP_I2C_QUEUECTRL_WR_THRESH 8 +#define BM_I2C_QUEUECTRL_WR_THRESH 0x00001F00 +#define BF_I2C_QUEUECTRL_WR_THRESH(v) \ + (((v) << 8) & BM_I2C_QUEUECTRL_WR_THRESH) +#define BP_I2C_QUEUECTRL_RSVD1 6 +#define BM_I2C_QUEUECTRL_RSVD1 0x000000C0 +#define BF_I2C_QUEUECTRL_RSVD1(v) \ + (((v) << 6) & BM_I2C_QUEUECTRL_RSVD1) +#define BM_I2C_QUEUECTRL_QUEUE_RUN 0x00000020 +#define BV_I2C_QUEUECTRL_QUEUE_RUN__STOP 0x0 +#define BV_I2C_QUEUECTRL_QUEUE_RUN__START 0x1 +#define BM_I2C_QUEUECTRL_RD_CLEAR 0x00000010 +#define BM_I2C_QUEUECTRL_WR_CLEAR 0x00000008 +#define BM_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x00000004 +#define BM_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN 0x00000002 +#define BV_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_QUEUECTRL_RD_QUEUE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN 0x00000001 +#define BV_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_QUEUECTRL_WR_QUEUE_IRQ_EN__ENABLED 0x1 + +#define HW_I2C_QUEUESTAT (0x00000070) +#define HW_I2C_QUEUESTAT_SET (0x00000074) +#define HW_I2C_QUEUESTAT_CLR (0x00000078) +#define HW_I2C_QUEUESTAT_TOG (0x0000007c) + +#define BP_I2C_QUEUESTAT_RSVD2 15 +#define BM_I2C_QUEUESTAT_RSVD2 0xFFFF8000 +#define BF_I2C_QUEUESTAT_RSVD2(v) \ + (((v) << 15) & BM_I2C_QUEUESTAT_RSVD2) +#define BM_I2C_QUEUESTAT_RD_QUEUE_FULL 0x00004000 +#define BM_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 +#define BP_I2C_QUEUESTAT_RD_QUEUE_CNT 8 +#define BM_I2C_QUEUESTAT_RD_QUEUE_CNT 0x00001F00 +#define BF_I2C_QUEUESTAT_RD_QUEUE_CNT(v) \ + (((v) << 8) & BM_I2C_QUEUESTAT_RD_QUEUE_CNT) +#define BM_I2C_QUEUESTAT_RSVD1 0x00000080 +#define BM_I2C_QUEUESTAT_WR_QUEUE_FULL 0x00000040 +#define BM_I2C_QUEUESTAT_WR_QUEUE_EMPTY 0x00000020 +#define BP_I2C_QUEUESTAT_WR_QUEUE_CNT 0 +#define BM_I2C_QUEUESTAT_WR_QUEUE_CNT 0x0000001F +#define BF_I2C_QUEUESTAT_WR_QUEUE_CNT(v) \ + (((v) << 0) & BM_I2C_QUEUESTAT_WR_QUEUE_CNT) + +#define HW_I2C_QUEUECMD (0x00000080) +#define HW_I2C_QUEUECMD_SET (0x00000084) +#define HW_I2C_QUEUECMD_CLR (0x00000088) +#define HW_I2C_QUEUECMD_TOG (0x0000008c) + +#define BP_I2C_QUEUECMD_RSVD2 28 +#define BM_I2C_QUEUECMD_RSVD2 0xF0000000 +#define BF_I2C_QUEUECMD_RSVD2(v) \ + (((v) << 28) & BM_I2C_QUEUECMD_RSVD2) +#define BM_I2C_QUEUECMD_PRE_ACK 0x08000000 +#define BM_I2C_QUEUECMD_ACKNOWLEDGE 0x04000000 +#define BV_I2C_QUEUECMD_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_QUEUECMD_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_QUEUECMD_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_QUEUECMD_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_QUEUECMD_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_QUEUECMD_RSVD1 0x01000000 +#define BM_I2C_QUEUECMD_MULTI_MASTER 0x00800000 +#define BV_I2C_QUEUECMD_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_QUEUECMD_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_QUEUECMD_CLOCK_HELD 0x00400000 +#define BV_I2C_QUEUECMD_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_QUEUECMD_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_QUEUECMD_RETAIN_CLOCK 0x00200000 +#define BV_I2C_QUEUECMD_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_QUEUECMD_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_QUEUECMD_POST_SEND_STOP 0x00100000 +#define BV_I2C_QUEUECMD_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_QUEUECMD_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_QUEUECMD_PRE_SEND_START 0x00080000 +#define BV_I2C_QUEUECMD_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_QUEUECMD_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_QUEUECMD_MASTER_MODE 0x00020000 +#define BV_I2C_QUEUECMD_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_QUEUECMD_MASTER_MODE__MASTER 0x1 +#define BM_I2C_QUEUECMD_DIRECTION 0x00010000 +#define BV_I2C_QUEUECMD_DIRECTION__RECEIVE 0x0 +#define BV_I2C_QUEUECMD_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_QUEUECMD_XFER_COUNT 0 +#define BM_I2C_QUEUECMD_XFER_COUNT 0x0000FFFF +#define BF_I2C_QUEUECMD_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_QUEUECMD_XFER_COUNT) + +#define HW_I2C_QUEUEDATA (0x00000090) + +#define BP_I2C_QUEUEDATA_DATA 0 +#define BM_I2C_QUEUEDATA_DATA 0xFFFFFFFF +#define BF_I2C_QUEUEDATA_DATA(v) (v) + +#define HW_I2C_DATA (0x000000a0) + +#define BP_I2C_DATA_DATA 0 +#define BM_I2C_DATA_DATA 0xFFFFFFFF +#define BF_I2C_DATA_DATA(v) (v) + +#define HW_I2C_DEBUG0 (0x000000b0) +#define HW_I2C_DEBUG0_SET (0x000000b4) +#define HW_I2C_DEBUG0_CLR (0x000000b8) +#define HW_I2C_DEBUG0_TOG (0x000000bc) + +#define BM_I2C_DEBUG0_DMAREQ 0x80000000 +#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 +#define BM_I2C_DEBUG0_DMAKICK 0x20000000 +#define BM_I2C_DEBUG0_DMATERMINATE 0x10000000 +#define BP_I2C_DEBUG0_STATE_VALUE 26 +#define BM_I2C_DEBUG0_STATE_VALUE 0x0C000000 +#define BF_I2C_DEBUG0_STATE_VALUE(v) \ + (((v) << 26) & BM_I2C_DEBUG0_STATE_VALUE) +#define BP_I2C_DEBUG0_DMA_STATE 16 +#define BM_I2C_DEBUG0_DMA_STATE 0x03FF0000 +#define BF_I2C_DEBUG0_DMA_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG0_DMA_STATE) +#define BM_I2C_DEBUG0_START_TOGGLE 0x00008000 +#define BM_I2C_DEBUG0_STOP_TOGGLE 0x00004000 +#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x00002000 +#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x00001000 +#define BM_I2C_DEBUG0_STATE_LATCH 0x00000800 +#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x00000400 +#define BP_I2C_DEBUG0_SLAVE_STATE 0 +#define BM_I2C_DEBUG0_SLAVE_STATE 0x000003FF +#define BF_I2C_DEBUG0_SLAVE_STATE(v) \ + (((v) << 0) & BM_I2C_DEBUG0_SLAVE_STATE) + +#define HW_I2C_DEBUG1 (0x000000c0) +#define HW_I2C_DEBUG1_SET (0x000000c4) +#define HW_I2C_DEBUG1_CLR (0x000000c8) +#define HW_I2C_DEBUG1_TOG (0x000000cc) + +#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 +#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 +#define BP_I2C_DEBUG1_RSVD4 28 +#define BM_I2C_DEBUG1_RSVD4 0x30000000 +#define BF_I2C_DEBUG1_RSVD4(v) \ + (((v) << 28) & BM_I2C_DEBUG1_RSVD4) +#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 +#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0x0F000000 +#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) \ + (((v) << 24) & BM_I2C_DEBUG1_DMA_BYTE_ENABLES) +#define BP_I2C_DEBUG1_CLK_GEN_STATE 16 +#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x00FF0000 +#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG1_CLK_GEN_STATE) +#define BP_I2C_DEBUG1_RSVD2 11 +#define BM_I2C_DEBUG1_RSVD2 0x0000F800 +#define BF_I2C_DEBUG1_RSVD2(v) \ + (((v) << 11) & BM_I2C_DEBUG1_RSVD2) +#define BP_I2C_DEBUG1_LST_MODE 9 +#define BM_I2C_DEBUG1_LST_MODE 0x00000600 +#define BF_I2C_DEBUG1_LST_MODE(v) \ + (((v) << 9) & BM_I2C_DEBUG1_LST_MODE) +#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 +#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 +#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 +#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 +#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x00000100 +#define BP_I2C_DEBUG1_RSVD1 5 +#define BM_I2C_DEBUG1_RSVD1 0x000000E0 +#define BF_I2C_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_I2C_DEBUG1_RSVD1) +#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x00000010 +#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x00000008 +#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x00000004 +#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x00000002 +#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x00000001 + +#define HW_I2C_VERSION (0x000000d0) + +#define BP_I2C_VERSION_MAJOR 24 +#define BM_I2C_VERSION_MAJOR 0xFF000000 +#define BF_I2C_VERSION_MAJOR(v) \ + (((v) << 24) & BM_I2C_VERSION_MAJOR) +#define BP_I2C_VERSION_MINOR 16 +#define BM_I2C_VERSION_MINOR 0x00FF0000 +#define BF_I2C_VERSION_MINOR(v) \ + (((v) << 16) & BM_I2C_VERSION_MINOR) +#define BP_I2C_VERSION_STEP 0 +#define BM_I2C_VERSION_STEP 0x0000FFFF +#define BF_I2C_VERSION_STEP(v) \ + (((v) << 0) & BM_I2C_VERSION_STEP) +#endif /* __ARCH_ARM___I2C_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-icoll.h b/arch/arm/mach-mx28/include/mach/regs-icoll.h new file mode 100644 index 000000000000..f06ac0d4720b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-icoll.h @@ -0,0 +1,293 @@ +/* + * Freescale ICOLL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___ICOLL_H +#define __ARCH_ARM___ICOLL_H + +#define HW_ICOLL_VECTOR (0x00000000) +#define HW_ICOLL_VECTOR_SET (0x00000004) +#define HW_ICOLL_VECTOR_CLR (0x00000008) +#define HW_ICOLL_VECTOR_TOG (0x0000000c) + +#define BP_ICOLL_VECTOR_IRQVECTOR 2 +#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC +#define BF_ICOLL_VECTOR_IRQVECTOR(v) \ + (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR) +#define BP_ICOLL_VECTOR_RSRVD1 0 +#define BM_ICOLL_VECTOR_RSRVD1 0x00000003 +#define BF_ICOLL_VECTOR_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VECTOR_RSRVD1) + +#define HW_ICOLL_LEVELACK (0x00000010) + +#define BP_ICOLL_LEVELACK_RSRVD1 4 +#define BM_ICOLL_LEVELACK_RSRVD1 0xFFFFFFF0 +#define BF_ICOLL_LEVELACK_RSRVD1(v) \ + (((v) << 4) & BM_ICOLL_LEVELACK_RSRVD1) +#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 +#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F +#define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \ + (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK) +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 + +#define HW_ICOLL_CTRL (0x00000020) +#define HW_ICOLL_CTRL_SET (0x00000024) +#define HW_ICOLL_CTRL_CLR (0x00000028) +#define HW_ICOLL_CTRL_TOG (0x0000002c) + +#define BM_ICOLL_CTRL_SFTRST 0x80000000 +#define BV_ICOLL_CTRL_SFTRST__RUN 0x0 +#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 +#define BM_ICOLL_CTRL_CLKGATE 0x40000000 +#define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 +#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 +#define BP_ICOLL_CTRL_RSRVD3 24 +#define BM_ICOLL_CTRL_RSRVD3 0x3F000000 +#define BF_ICOLL_CTRL_RSRVD3(v) \ + (((v) << 24) & BM_ICOLL_CTRL_RSRVD3) +#define BP_ICOLL_CTRL_VECTOR_PITCH 21 +#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000 +#define BF_ICOLL_CTRL_VECTOR_PITCH(v) \ + (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH) +#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 +#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000 +#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 +#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 +#define BM_ICOLL_CTRL_NO_NESTING 0x00080000 +#define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 +#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 +#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000 +#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 +#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 +#define BP_ICOLL_CTRL_RSRVD1 0 +#define BM_ICOLL_CTRL_RSRVD1 0x0000FFFF +#define BF_ICOLL_CTRL_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_CTRL_RSRVD1) + +#define HW_ICOLL_VBASE (0x00000040) +#define HW_ICOLL_VBASE_SET (0x00000044) +#define HW_ICOLL_VBASE_CLR (0x00000048) +#define HW_ICOLL_VBASE_TOG (0x0000004c) + +#define BP_ICOLL_VBASE_TABLE_ADDRESS 2 +#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC +#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \ + (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS) +#define BP_ICOLL_VBASE_RSRVD1 0 +#define BM_ICOLL_VBASE_RSRVD1 0x00000003 +#define BF_ICOLL_VBASE_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VBASE_RSRVD1) + +#define HW_ICOLL_STAT (0x00000070) + +#define BP_ICOLL_STAT_RSRVD1 7 +#define BM_ICOLL_STAT_RSRVD1 0xFFFFFF80 +#define BF_ICOLL_STAT_RSRVD1(v) \ + (((v) << 7) & BM_ICOLL_STAT_RSRVD1) +#define BP_ICOLL_STAT_VECTOR_NUMBER 0 +#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F +#define BF_ICOLL_STAT_VECTOR_NUMBER(v) \ + (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER) + +/* + * multi-register-define name HW_ICOLL_RAWn + * base 0x000000A0 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_RAWn(n) (0x000000a0 + (n) * 0x10) +#define HW_ICOLL_RAWn_SET(n) (0x000000a4 + (n) * 0x10) +#define HW_ICOLL_RAWn_CLR(n) (0x000000a8 + (n) * 0x10) +#define HW_ICOLL_RAWn_TOG(n) (0x000000ac + (n) * 0x10) +#define BP_ICOLL_RAWn_RAW_IRQS 0 +#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF +#define BF_ICOLL_RAWn_RAW_IRQS(v) (v) + +/* + * multi-register-define name HW_ICOLL_INTERRUPTn + * base 0x00000120 + * count 128 + * offset 0x10 + */ +#define HW_ICOLL_INTERRUPTn(n) (0x00000120 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_SET(n) (0x00000124 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_CLR(n) (0x00000128 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_TOG(n) (0x0000012c + (n) * 0x10) +#define BP_ICOLL_INTERRUPTn_RSRVD1 5 +#define BM_ICOLL_INTERRUPTn_RSRVD1 0xFFFFFFE0 +#define BF_ICOLL_INTERRUPTn_RSRVD1(v) \ + (((v) << 5) & BM_ICOLL_INTERRUPTn_RSRVD1) +#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010 +#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 +#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 +#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 +#define BP_ICOLL_INTERRUPTn_PRIORITY 0 +#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003 +#define BF_ICOLL_INTERRUPTn_PRIORITY(v) \ + (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY) +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 + +#define HW_ICOLL_DEBUG (0x00001120) +#define HW_ICOLL_DEBUG_SET (0x00001124) +#define HW_ICOLL_DEBUG_CLR (0x00001128) +#define HW_ICOLL_DEBUG_TOG (0x0000112c) + +#define BP_ICOLL_DEBUG_INSERVICE 28 +#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000 +#define BF_ICOLL_DEBUG_INSERVICE(v) \ + (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE) +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 +#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000 +#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \ + (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS) +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 +#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000 +#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \ + (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL) +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_RSRVD2 18 +#define BM_ICOLL_DEBUG_RSRVD2 0x000C0000 +#define BF_ICOLL_DEBUG_RSRVD2(v) \ + (((v) << 18) & BM_ICOLL_DEBUG_RSRVD2) +#define BM_ICOLL_DEBUG_FIQ 0x00020000 +#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 +#define BM_ICOLL_DEBUG_IRQ 0x00010000 +#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 +#define BP_ICOLL_DEBUG_RSRVD1 10 +#define BM_ICOLL_DEBUG_RSRVD1 0x0000FC00 +#define BF_ICOLL_DEBUG_RSRVD1(v) \ + (((v) << 10) & BM_ICOLL_DEBUG_RSRVD1) +#define BP_ICOLL_DEBUG_VECTOR_FSM 0 +#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF +#define BF_ICOLL_DEBUG_VECTOR_FSM(v) \ + (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM) +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 + +#define HW_ICOLL_DBGREAD0 (0x00001130) +#define HW_ICOLL_DBGREAD0_SET (0x00001134) +#define HW_ICOLL_DBGREAD0_CLR (0x00001138) +#define HW_ICOLL_DBGREAD0_TOG (0x0000113c) + +#define BP_ICOLL_DBGREAD0_VALUE 0 +#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD0_VALUE(v) (v) + +#define HW_ICOLL_DBGREAD1 (0x00001140) +#define HW_ICOLL_DBGREAD1_SET (0x00001144) +#define HW_ICOLL_DBGREAD1_CLR (0x00001148) +#define HW_ICOLL_DBGREAD1_TOG (0x0000114c) + +#define BP_ICOLL_DBGREAD1_VALUE 0 +#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD1_VALUE(v) (v) + +#define HW_ICOLL_DBGFLAG (0x00001150) +#define HW_ICOLL_DBGFLAG_SET (0x00001154) +#define HW_ICOLL_DBGFLAG_CLR (0x00001158) +#define HW_ICOLL_DBGFLAG_TOG (0x0000115c) + +#define BP_ICOLL_DBGFLAG_RSRVD1 16 +#define BM_ICOLL_DBGFLAG_RSRVD1 0xFFFF0000 +#define BF_ICOLL_DBGFLAG_RSRVD1(v) \ + (((v) << 16) & BM_ICOLL_DBGFLAG_RSRVD1) +#define BP_ICOLL_DBGFLAG_FLAG 0 +#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF +#define BF_ICOLL_DBGFLAG_FLAG(v) \ + (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG) + +/* + * multi-register-define name HW_ICOLL_DBGREQUESTn + * base 0x00001160 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_DBGREQUESTn(n) (0x00001160 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_SET(n) (0x00001164 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_CLR(n) (0x00001168 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_TOG(n) (0x0000116c + (n) * 0x10) +#define BP_ICOLL_DBGREQUESTn_BITS 0 +#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF +#define BF_ICOLL_DBGREQUESTn_BITS(v) (v) + +#define HW_ICOLL_VERSION (0x000011e0) + +#define BP_ICOLL_VERSION_MAJOR 24 +#define BM_ICOLL_VERSION_MAJOR 0xFF000000 +#define BF_ICOLL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ICOLL_VERSION_MAJOR) +#define BP_ICOLL_VERSION_MINOR 16 +#define BM_ICOLL_VERSION_MINOR 0x00FF0000 +#define BF_ICOLL_VERSION_MINOR(v) \ + (((v) << 16) & BM_ICOLL_VERSION_MINOR) +#define BP_ICOLL_VERSION_STEP 0 +#define BM_ICOLL_VERSION_STEP 0x0000FFFF +#define BF_ICOLL_VERSION_STEP(v) \ + (((v) << 0) & BM_ICOLL_VERSION_STEP) +#endif /* __ARCH_ARM___ICOLL_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-lcdif.h b/arch/arm/mach-mx28/include/mach/regs-lcdif.h new file mode 100644 index 000000000000..6a0e008be308 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-lcdif.h @@ -0,0 +1,680 @@ +/* + * Freescale LCDIF Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.32 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LCDIF_H +#define __ARCH_ARM___LCDIF_H + + +#define HW_LCDIF_CTRL (0x00000000) +#define HW_LCDIF_CTRL_SET (0x00000004) +#define HW_LCDIF_CTRL_CLR (0x00000008) +#define HW_LCDIF_CTRL_TOG (0x0000000c) + +#define BM_LCDIF_CTRL_SFTRST 0x80000000 +#define BM_LCDIF_CTRL_CLKGATE 0x40000000 +#define BM_LCDIF_CTRL_YCBCR422_INPUT 0x20000000 +#define BM_LCDIF_CTRL_READ_WRITEB 0x10000000 +#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 +#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 +#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 +#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 +#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) \ + (((v) << 21) & BM_LCDIF_CTRL_SHIFT_NUM_BITS) +#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 +#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 +#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 +#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 +#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 +#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 +#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 +#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 +#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 +#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \ + (((v) << 14) & BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE 12 +#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000 +#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v) \ + (((v) << 12) & BM_LCDIF_CTRL_CSC_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 +#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 +#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v) \ + (((v) << 10) & BM_LCDIF_CTRL_LCD_DATABUS_WIDTH) +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3 +#define BP_LCDIF_CTRL_WORD_LENGTH 8 +#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 +#define BF_LCDIF_CTRL_WORD_LENGTH(v) \ + (((v) << 8) & BM_LCDIF_CTRL_WORD_LENGTH) +#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT 0x3 +#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 +#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040 +#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 +#define BM_LCDIF_CTRL_RSRVD0 0x00000010 +#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008 +#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1 +#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1 +#define BM_LCDIF_CTRL_RUN 0x00000001 + +#define HW_LCDIF_CTRL1 (0x00000010) +#define HW_LCDIF_CTRL1_SET (0x00000014) +#define HW_LCDIF_CTRL1_CLR (0x00000018) +#define HW_LCDIF_CTRL1_TOG (0x0000001c) + +#define BP_LCDIF_CTRL1_RSRVD1 28 +#define BM_LCDIF_CTRL1_RSRVD1 0xF0000000 +#define BF_LCDIF_CTRL1_RSRVD1(v) \ + (((v) << 28) & BM_LCDIF_CTRL1_RSRVD1) +#define BM_LCDIF_CTRL1_COMBINE_MPU_WR_STRB 0x08000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ 0x02000000 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 +#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 +#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000 +#define BM_LCDIF_CTRL1_FIFO_CLEAR 0x00200000 +#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000 +#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 +#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 +#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \ + (((v) << 16) & BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT) +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 +#define BP_LCDIF_CTRL1_RSRVD0 3 +#define BM_LCDIF_CTRL1_RSRVD0 0x000000F8 +#define BF_LCDIF_CTRL1_RSRVD0(v) \ + (((v) << 3) & BM_LCDIF_CTRL1_RSRVD0) +#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 +#define BM_LCDIF_CTRL1_MODE86 0x00000002 +#define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 +#define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 +#define BM_LCDIF_CTRL1_RESET 0x00000001 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 + +#define HW_LCDIF_CTRL2 (0x00000020) +#define HW_LCDIF_CTRL2_SET (0x00000024) +#define HW_LCDIF_CTRL2_CLR (0x00000028) +#define HW_LCDIF_CTRL2_TOG (0x0000002c) + +#define BP_LCDIF_CTRL2_RSRVD5 24 +#define BM_LCDIF_CTRL2_RSRVD5 0xFF000000 +#define BF_LCDIF_CTRL2_RSRVD5(v) \ + (((v) << 24) & BM_LCDIF_CTRL2_RSRVD5) +#define BP_LCDIF_CTRL2_OUTSTANDING_REQS 21 +#define BM_LCDIF_CTRL2_OUTSTANDING_REQS 0x00E00000 +#define BF_LCDIF_CTRL2_OUTSTANDING_REQS(v) \ + (((v) << 21) & BM_LCDIF_CTRL2_OUTSTANDING_REQS) +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_1 0x0 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_2 0x1 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_4 0x2 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_8 0x3 +#define BV_LCDIF_CTRL2_OUTSTANDING_REQS__REQ_16 0x4 +#define BM_LCDIF_CTRL2_BURST_LEN_8 0x00100000 +#define BM_LCDIF_CTRL2_RSRVD4 0x00080000 +#define BP_LCDIF_CTRL2_ODD_LINE_PATTERN 16 +#define BM_LCDIF_CTRL2_ODD_LINE_PATTERN 0x00070000 +#define BF_LCDIF_CTRL2_ODD_LINE_PATTERN(v) \ + (((v) << 16) & BM_LCDIF_CTRL2_ODD_LINE_PATTERN) +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__RGB 0x0 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__RBG 0x1 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__GBR 0x2 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__GRB 0x3 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__BRG 0x4 +#define BV_LCDIF_CTRL2_ODD_LINE_PATTERN__BGR 0x5 +#define BM_LCDIF_CTRL2_RSRVD3 0x00008000 +#define BP_LCDIF_CTRL2_EVEN_LINE_PATTERN 12 +#define BM_LCDIF_CTRL2_EVEN_LINE_PATTERN 0x00007000 +#define BF_LCDIF_CTRL2_EVEN_LINE_PATTERN(v) \ + (((v) << 12) & BM_LCDIF_CTRL2_EVEN_LINE_PATTERN) +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__RGB 0x0 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__RBG 0x1 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__GBR 0x2 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__GRB 0x3 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__BRG 0x4 +#define BV_LCDIF_CTRL2_EVEN_LINE_PATTERN__BGR 0x5 +#define BM_LCDIF_CTRL2_RSRVD2 0x00000800 +#define BM_LCDIF_CTRL2_READ_PACK_DIR 0x00000400 +#define BM_LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT 0x00000200 +#define BM_LCDIF_CTRL2_READ_MODE_6_BIT_INPUT 0x00000100 +#define BM_LCDIF_CTRL2_RSRVD1 0x00000080 +#define BP_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 4 +#define BM_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 0x00000070 +#define BF_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(v) \ + (((v) << 4) & BM_LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS) +#define BP_LCDIF_CTRL2_INITIAL_DUMMY_READ 1 +#define BM_LCDIF_CTRL2_INITIAL_DUMMY_READ 0x0000000E +#define BF_LCDIF_CTRL2_INITIAL_DUMMY_READ(v) \ + (((v) << 1) & BM_LCDIF_CTRL2_INITIAL_DUMMY_READ) +#define BM_LCDIF_CTRL2_RSRVD0 0x00000001 + +#define HW_LCDIF_TRANSFER_COUNT (0x00000030) + +#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 +#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 +#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v) \ + (((v) << 16) & BM_LCDIF_TRANSFER_COUNT_V_COUNT) +#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 +#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF +#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v) \ + (((v) << 0) & BM_LCDIF_TRANSFER_COUNT_H_COUNT) + +#define HW_LCDIF_CUR_BUF (0x00000040) + +#define BP_LCDIF_CUR_BUF_ADDR 0 +#define BM_LCDIF_CUR_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_CUR_BUF_ADDR(v) (v) + +#define HW_LCDIF_NEXT_BUF (0x00000050) + +#define BP_LCDIF_NEXT_BUF_ADDR 0 +#define BM_LCDIF_NEXT_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_NEXT_BUF_ADDR(v) (v) + +#define HW_LCDIF_TIMING (0x00000060) + +#define BP_LCDIF_TIMING_CMD_HOLD 24 +#define BM_LCDIF_TIMING_CMD_HOLD 0xFF000000 +#define BF_LCDIF_TIMING_CMD_HOLD(v) \ + (((v) << 24) & BM_LCDIF_TIMING_CMD_HOLD) +#define BP_LCDIF_TIMING_CMD_SETUP 16 +#define BM_LCDIF_TIMING_CMD_SETUP 0x00FF0000 +#define BF_LCDIF_TIMING_CMD_SETUP(v) \ + (((v) << 16) & BM_LCDIF_TIMING_CMD_SETUP) +#define BP_LCDIF_TIMING_DATA_HOLD 8 +#define BM_LCDIF_TIMING_DATA_HOLD 0x0000FF00 +#define BF_LCDIF_TIMING_DATA_HOLD(v) \ + (((v) << 8) & BM_LCDIF_TIMING_DATA_HOLD) +#define BP_LCDIF_TIMING_DATA_SETUP 0 +#define BM_LCDIF_TIMING_DATA_SETUP 0x000000FF +#define BF_LCDIF_TIMING_DATA_SETUP(v) \ + (((v) << 0) & BM_LCDIF_TIMING_DATA_SETUP) + +#define HW_LCDIF_VDCTRL0 (0x00000070) +#define HW_LCDIF_VDCTRL0_SET (0x00000074) +#define HW_LCDIF_VDCTRL0_CLR (0x00000078) +#define HW_LCDIF_VDCTRL0_TOG (0x0000007c) + +#define BP_LCDIF_VDCTRL0_RSRVD2 30 +#define BM_LCDIF_VDCTRL0_RSRVD2 0xC0000000 +#define BF_LCDIF_VDCTRL0_RSRVD2(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL0_RSRVD2) +#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 +#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 +#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 +#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 +#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 +#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 +#define BP_LCDIF_VDCTRL0_RSRVD1 22 +#define BM_LCDIF_VDCTRL0_RSRVD1 0x00C00000 +#define BF_LCDIF_VDCTRL0_RSRVD1(v) \ + (((v) << 22) & BM_LCDIF_VDCTRL0_RSRVD1) +#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 +#define BM_LCDIF_VDCTRL0_HALF_LINE 0x00080000 +#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000 +#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF +#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH) + +#define HW_LCDIF_VDCTRL1 (0x00000080) + +#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF +#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (v) + +#define HW_LCDIF_VDCTRL2 (0x00000090) + +#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 18 +#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFFFC0000 +#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \ + (((v) << 18) & BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH) +#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF +#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL2_HSYNC_PERIOD) + +#define HW_LCDIF_VDCTRL3 (0x000000a0) + +#define BP_LCDIF_VDCTRL3_RSRVD0 30 +#define BM_LCDIF_VDCTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_VDCTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL3_RSRVD0) +#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000 +#define BM_LCDIF_VDCTRL3_VSYNC_ONLY 0x10000000 +#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 +#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 +#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \ + (((v) << 16) & BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT) +#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 +#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF +#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT) + +#define HW_LCDIF_VDCTRL4 (0x000000b0) + +#define BP_LCDIF_VDCTRL4_DOTCLK_DLY_SEL 29 +#define BM_LCDIF_VDCTRL4_DOTCLK_DLY_SEL 0xE0000000 +#define BF_LCDIF_VDCTRL4_DOTCLK_DLY_SEL(v) \ + (((v) << 29) & BM_LCDIF_VDCTRL4_DOTCLK_DLY_SEL) +#define BP_LCDIF_VDCTRL4_RSRVD0 19 +#define BM_LCDIF_VDCTRL4_RSRVD0 0x1FF80000 +#define BF_LCDIF_VDCTRL4_RSRVD0(v) \ + (((v) << 19) & BM_LCDIF_VDCTRL4_RSRVD0) +#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 +#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 +#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF +#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT) + +#define HW_LCDIF_DVICTRL0 (0x000000c0) + +#define BP_LCDIF_DVICTRL0_RSRVD1 28 +#define BM_LCDIF_DVICTRL0_RSRVD1 0xF0000000 +#define BF_LCDIF_DVICTRL0_RSRVD1(v) \ + (((v) << 28) & BM_LCDIF_DVICTRL0_RSRVD1) +#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 16 +#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x0FFF0000 +#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL0_H_ACTIVE_CNT) +#define BP_LCDIF_DVICTRL0_RSRVD0 12 +#define BM_LCDIF_DVICTRL0_RSRVD0 0x0000F000 +#define BF_LCDIF_DVICTRL0_RSRVD0(v) \ + (((v) << 12) & BM_LCDIF_DVICTRL0_RSRVD0) +#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 0 +#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x00000FFF +#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL0_H_BLANKING_CNT) + +#define HW_LCDIF_DVICTRL1 (0x000000d0) + +#define BP_LCDIF_DVICTRL1_RSRVD0 30 +#define BM_LCDIF_DVICTRL1_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL1_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL1_RSRVD0) +#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 +#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL1_F1_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL1_F1_START_LINE) +#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 +#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL1_F1_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL1_F1_END_LINE) +#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 +#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF +#define BF_LCDIF_DVICTRL1_F2_START_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL1_F2_START_LINE) + +#define HW_LCDIF_DVICTRL2 (0x000000e0) + +#define BP_LCDIF_DVICTRL2_RSRVD0 30 +#define BM_LCDIF_DVICTRL2_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL2_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL2_RSRVD0) +#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 +#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL2_F2_END_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL2_F2_END_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 +#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE) + +#define HW_LCDIF_DVICTRL3 (0x000000f0) + +#define BP_LCDIF_DVICTRL3_RSRVD0 30 +#define BM_LCDIF_DVICTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL3_RSRVD0) +#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 20 +#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 10 +#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE) +#define BP_LCDIF_DVICTRL3_V_LINES_CNT 0 +#define BM_LCDIF_DVICTRL3_V_LINES_CNT 0x000003FF +#define BF_LCDIF_DVICTRL3_V_LINES_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL3_V_LINES_CNT) + +#define HW_LCDIF_DVICTRL4 (0x00000100) + +#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 +#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 +#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v) \ + (((v) << 24) & BM_LCDIF_DVICTRL4_Y_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 +#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 +#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL4_CB_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 +#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 +#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v) \ + (((v) << 8) & BM_LCDIF_DVICTRL4_CR_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 +#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF +#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL4_H_FILL_CNT) + +#define HW_LCDIF_CSC_COEFF0 (0x00000110) + +#define BP_LCDIF_CSC_COEFF0_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF0_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF0_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF0_RSRVD1) +#define BP_LCDIF_CSC_COEFF0_C0 16 +#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 +#define BF_LCDIF_CSC_COEFF0_C0(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF0_C0) +#define BP_LCDIF_CSC_COEFF0_RSRVD0 2 +#define BM_LCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC +#define BF_LCDIF_CSC_COEFF0_RSRVD0(v) \ + (((v) << 2) & BM_LCDIF_CSC_COEFF0_RSRVD0) +#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 +#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 +#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER) +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3 + +#define HW_LCDIF_CSC_COEFF1 (0x00000120) + +#define BP_LCDIF_CSC_COEFF1_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF1_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF1_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF1_RSRVD1) +#define BP_LCDIF_CSC_COEFF1_C2 16 +#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 +#define BF_LCDIF_CSC_COEFF1_C2(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF1_C2) +#define BP_LCDIF_CSC_COEFF1_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF1_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF1_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF1_RSRVD0) +#define BP_LCDIF_CSC_COEFF1_C1 0 +#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF +#define BF_LCDIF_CSC_COEFF1_C1(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF1_C1) + +#define HW_LCDIF_CSC_COEFF2 (0x00000130) + +#define BP_LCDIF_CSC_COEFF2_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF2_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF2_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF2_RSRVD1) +#define BP_LCDIF_CSC_COEFF2_C4 16 +#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 +#define BF_LCDIF_CSC_COEFF2_C4(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF2_C4) +#define BP_LCDIF_CSC_COEFF2_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF2_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF2_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF2_RSRVD0) +#define BP_LCDIF_CSC_COEFF2_C3 0 +#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF +#define BF_LCDIF_CSC_COEFF2_C3(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF2_C3) + +#define HW_LCDIF_CSC_COEFF3 (0x00000140) + +#define BP_LCDIF_CSC_COEFF3_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF3_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF3_RSRVD1) +#define BP_LCDIF_CSC_COEFF3_C6 16 +#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 +#define BF_LCDIF_CSC_COEFF3_C6(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF3_C6) +#define BP_LCDIF_CSC_COEFF3_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF3_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF3_RSRVD0) +#define BP_LCDIF_CSC_COEFF3_C5 0 +#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF +#define BF_LCDIF_CSC_COEFF3_C5(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF3_C5) + +#define HW_LCDIF_CSC_COEFF4 (0x00000150) + +#define BP_LCDIF_CSC_COEFF4_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF4_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF4_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF4_RSRVD1) +#define BP_LCDIF_CSC_COEFF4_C8 16 +#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 +#define BF_LCDIF_CSC_COEFF4_C8(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF4_C8) +#define BP_LCDIF_CSC_COEFF4_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF4_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF4_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF4_RSRVD0) +#define BP_LCDIF_CSC_COEFF4_C7 0 +#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF +#define BF_LCDIF_CSC_COEFF4_C7(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF4_C7) + +#define HW_LCDIF_CSC_OFFSET (0x00000160) + +#define BP_LCDIF_CSC_OFFSET_RSRVD1 25 +#define BM_LCDIF_CSC_OFFSET_RSRVD1 0xFE000000 +#define BF_LCDIF_CSC_OFFSET_RSRVD1(v) \ + (((v) << 25) & BM_LCDIF_CSC_OFFSET_RSRVD1) +#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 +#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 +#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v) \ + (((v) << 16) & BM_LCDIF_CSC_OFFSET_CBCR_OFFSET) +#define BP_LCDIF_CSC_OFFSET_RSRVD0 9 +#define BM_LCDIF_CSC_OFFSET_RSRVD0 0x0000FE00 +#define BF_LCDIF_CSC_OFFSET_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_CSC_OFFSET_RSRVD0) +#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 +#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF +#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v) \ + (((v) << 0) & BM_LCDIF_CSC_OFFSET_Y_OFFSET) + +#define HW_LCDIF_CSC_LIMIT (0x00000170) + +#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 +#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v) \ + (((v) << 24) & BM_LCDIF_CSC_LIMIT_CBCR_MIN) +#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 +#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v) \ + (((v) << 16) & BM_LCDIF_CSC_LIMIT_CBCR_MAX) +#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 +#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 +#define BF_LCDIF_CSC_LIMIT_Y_MIN(v) \ + (((v) << 8) & BM_LCDIF_CSC_LIMIT_Y_MIN) +#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 +#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF +#define BF_LCDIF_CSC_LIMIT_Y_MAX(v) \ + (((v) << 0) & BM_LCDIF_CSC_LIMIT_Y_MAX) + +#define HW_LCDIF_DATA (0x00000180) + +#define BP_LCDIF_DATA_DATA_THREE 24 +#define BM_LCDIF_DATA_DATA_THREE 0xFF000000 +#define BF_LCDIF_DATA_DATA_THREE(v) \ + (((v) << 24) & BM_LCDIF_DATA_DATA_THREE) +#define BP_LCDIF_DATA_DATA_TWO 16 +#define BM_LCDIF_DATA_DATA_TWO 0x00FF0000 +#define BF_LCDIF_DATA_DATA_TWO(v) \ + (((v) << 16) & BM_LCDIF_DATA_DATA_TWO) +#define BP_LCDIF_DATA_DATA_ONE 8 +#define BM_LCDIF_DATA_DATA_ONE 0x0000FF00 +#define BF_LCDIF_DATA_DATA_ONE(v) \ + (((v) << 8) & BM_LCDIF_DATA_DATA_ONE) +#define BP_LCDIF_DATA_DATA_ZERO 0 +#define BM_LCDIF_DATA_DATA_ZERO 0x000000FF +#define BF_LCDIF_DATA_DATA_ZERO(v) \ + (((v) << 0) & BM_LCDIF_DATA_DATA_ZERO) + +#define HW_LCDIF_BM_ERROR_STAT (0x00000190) + +#define BP_LCDIF_BM_ERROR_STAT_ADDR 0 +#define BM_LCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF +#define BF_LCDIF_BM_ERROR_STAT_ADDR(v) (v) + +#define HW_LCDIF_CRC_STAT (0x000001a0) + +#define BP_LCDIF_CRC_STAT_CRC_VALUE 0 +#define BM_LCDIF_CRC_STAT_CRC_VALUE 0xFFFFFFFF +#define BF_LCDIF_CRC_STAT_CRC_VALUE(v) (v) + +#define HW_LCDIF_STAT (0x000001b0) + +#define BM_LCDIF_STAT_PRESENT 0x80000000 +#define BM_LCDIF_STAT_DMA_REQ 0x40000000 +#define BM_LCDIF_STAT_LFIFO_FULL 0x20000000 +#define BM_LCDIF_STAT_LFIFO_EMPTY 0x10000000 +#define BM_LCDIF_STAT_TXFIFO_FULL 0x08000000 +#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 +#define BM_LCDIF_STAT_BUSY 0x02000000 +#define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x01000000 +#define BP_LCDIF_STAT_RSRVD0 9 +#define BM_LCDIF_STAT_RSRVD0 0x00FFFE00 +#define BF_LCDIF_STAT_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_STAT_RSRVD0) +#define BP_LCDIF_STAT_LFIFO_COUNT 0 +#define BM_LCDIF_STAT_LFIFO_COUNT 0x000001FF +#define BF_LCDIF_STAT_LFIFO_COUNT(v) \ + (((v) << 0) & BM_LCDIF_STAT_LFIFO_COUNT) + +#define HW_LCDIF_VERSION (0x000001c0) + +#define BP_LCDIF_VERSION_MAJOR 24 +#define BM_LCDIF_VERSION_MAJOR 0xFF000000 +#define BF_LCDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LCDIF_VERSION_MAJOR) +#define BP_LCDIF_VERSION_MINOR 16 +#define BM_LCDIF_VERSION_MINOR 0x00FF0000 +#define BF_LCDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_LCDIF_VERSION_MINOR) +#define BP_LCDIF_VERSION_STEP 0 +#define BM_LCDIF_VERSION_STEP 0x0000FFFF +#define BF_LCDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_LCDIF_VERSION_STEP) + +#define HW_LCDIF_DEBUG0 (0x000001d0) + +#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 +#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 +#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 +#define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 +#define BM_LCDIF_DEBUG0_ENABLE 0x08000000 +#define BM_LCDIF_DEBUG0_HSYNC 0x04000000 +#define BM_LCDIF_DEBUG0_VSYNC 0x02000000 +#define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x01000000 +#define BM_LCDIF_DEBUG0_EMPTY_WORD 0x00800000 +#define BP_LCDIF_DEBUG0_CUR_STATE 16 +#define BM_LCDIF_DEBUG0_CUR_STATE 0x007F0000 +#define BF_LCDIF_DEBUG0_CUR_STATE(v) \ + (((v) << 16) & BM_LCDIF_DEBUG0_CUR_STATE) +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 0x00008000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 0x00004000 +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 0x00002000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 0x00001000 +#define BP_LCDIF_DEBUG0_CUR_REQ_STATE 10 +#define BM_LCDIF_DEBUG0_CUR_REQ_STATE 0x00000C00 +#define BF_LCDIF_DEBUG0_CUR_REQ_STATE(v) \ + (((v) << 10) & BM_LCDIF_DEBUG0_CUR_REQ_STATE) +#define BM_LCDIF_DEBUG0_MST_AVALID 0x00000200 +#define BP_LCDIF_DEBUG0_MST_OUTSTANDING_REQS 4 +#define BM_LCDIF_DEBUG0_MST_OUTSTANDING_REQS 0x000001F0 +#define BF_LCDIF_DEBUG0_MST_OUTSTANDING_REQS(v) \ + (((v) << 4) & BM_LCDIF_DEBUG0_MST_OUTSTANDING_REQS) +#define BP_LCDIF_DEBUG0_MST_WORDS 0 +#define BM_LCDIF_DEBUG0_MST_WORDS 0x0000000F +#define BF_LCDIF_DEBUG0_MST_WORDS(v) \ + (((v) << 0) & BM_LCDIF_DEBUG0_MST_WORDS) + +#define HW_LCDIF_DEBUG1 (0x000001e0) + +#define BP_LCDIF_DEBUG1_H_DATA_COUNT 16 +#define BM_LCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000 +#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) \ + (((v) << 16) & BM_LCDIF_DEBUG1_H_DATA_COUNT) +#define BP_LCDIF_DEBUG1_V_DATA_COUNT 0 +#define BM_LCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF +#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) \ + (((v) << 0) & BM_LCDIF_DEBUG1_V_DATA_COUNT) + +#define HW_LCDIF_DEBUG2 (0x000001f0) + +#define BP_LCDIF_DEBUG2_MST_ADDRESS 0 +#define BM_LCDIF_DEBUG2_MST_ADDRESS 0xFFFFFFFF +#define BF_LCDIF_DEBUG2_MST_ADDRESS(v) (v) +#endif /* __ARCH_ARM___LCDIF_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-lradc.h b/arch/arm/mach-mx28/include/mach/regs-lradc.h new file mode 100644 index 000000000000..d7906b91c72e --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-lradc.h @@ -0,0 +1,772 @@ +/* + * Freescale LRADC Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___LRADC_H +#define __ARCH_ARM___LRADC_H + + +#define HW_LRADC_CTRL0 (0x00000000) +#define HW_LRADC_CTRL0_SET (0x00000004) +#define HW_LRADC_CTRL0_CLR (0x00000008) +#define HW_LRADC_CTRL0_TOG (0x0000000c) + +#define BM_LRADC_CTRL0_SFTRST 0x80000000 +#define BM_LRADC_CTRL0_CLKGATE 0x40000000 +#define BP_LRADC_CTRL0_RSRVD2 27 +#define BM_LRADC_CTRL0_RSRVD2 0x38000000 +#define BF_LRADC_CTRL0_RSRVD2(v) \ + (((v) << 27) & BM_LRADC_CTRL0_RSRVD2) +#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x04000000 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 +#define BM_LRADC_CTRL0_BUTTON1_DETECT_ENABLE 0x02000000 +#define BV_LRADC_CTRL0_BUTTON1_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_BUTTON1_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_BUTTON0_DETECT_ENABLE 0x01000000 +#define BV_LRADC_CTRL0_BUTTON0_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_BUTTON0_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00800000 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_SCREEN_TYPE 0x00400000 +#define BM_LRADC_CTRL0_YNLRSW 0x00200000 +#define BP_LRADC_CTRL0_YPLLSW 19 +#define BM_LRADC_CTRL0_YPLLSW 0x00180000 +#define BF_LRADC_CTRL0_YPLLSW(v) \ + (((v) << 19) & BM_LRADC_CTRL0_YPLLSW) +#define BP_LRADC_CTRL0_XNURSW 17 +#define BM_LRADC_CTRL0_XNURSW 0x00060000 +#define BF_LRADC_CTRL0_XNURSW(v) \ + (((v) << 17) & BM_LRADC_CTRL0_XNURSW) +#define BM_LRADC_CTRL0_XPULSW 0x00010000 +#define BP_LRADC_CTRL0_RSRVD1 8 +#define BM_LRADC_CTRL0_RSRVD1 0x0000FF00 +#define BF_LRADC_CTRL0_RSRVD1(v) \ + (((v) << 8) & BM_LRADC_CTRL0_RSRVD1) +#define BP_LRADC_CTRL0_SCHEDULE 0 +#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF +#define BF_LRADC_CTRL0_SCHEDULE(v) \ + (((v) << 0) & BM_LRADC_CTRL0_SCHEDULE) + +#define HW_LRADC_CTRL1 (0x00000010) +#define HW_LRADC_CTRL1_SET (0x00000014) +#define HW_LRADC_CTRL1_CLR (0x00000018) +#define HW_LRADC_CTRL1_TOG (0x0000001c) + +#define BP_LRADC_CTRL1_RSRVD2 29 +#define BM_LRADC_CTRL1_RSRVD2 0xE0000000 +#define BF_LRADC_CTRL1_RSRVD2(v) \ + (((v) << 29) & BM_LRADC_CTRL1_RSRVD2) +#define BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN 0x10000000 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN 0x08000000 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN 0x04000000 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN 0x02000000 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x00800000 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x00400000 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x00100000 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x00080000 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x00040000 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x00020000 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 +#define BP_LRADC_CTRL1_RSRVD1 13 +#define BM_LRADC_CTRL1_RSRVD1 0x0000E000 +#define BF_LRADC_CTRL1_RSRVD1(v) \ + (((v) << 13) & BM_LRADC_CTRL1_RSRVD1) +#define BM_LRADC_CTRL1_BUTTON1_DETECT_IRQ 0x00001000 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_BUTTON1_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_BUTTON0_DETECT_IRQ 0x00000800 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_BUTTON0_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ 0x00000400 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_THRESHOLD1_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ 0x00000200 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_THRESHOLD0_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ 0x00000080 +#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 +#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 +#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ 0x00000010 +#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ 0x00000008 +#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ 0x00000004 +#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ 0x00000002 +#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 +#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 + +#define HW_LRADC_CTRL2 (0x00000020) +#define HW_LRADC_CTRL2_SET (0x00000024) +#define HW_LRADC_CTRL2_CLR (0x00000028) +#define HW_LRADC_CTRL2_TOG (0x0000002c) + +#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 +#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 +#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) \ + (((v) << 24) & BM_LRADC_CTRL2_DIVIDE_BY_TWO) +#define BP_LRADC_CTRL2_RSRVD3 16 +#define BM_LRADC_CTRL2_RSRVD3 0x00FF0000 +#define BF_LRADC_CTRL2_RSRVD3(v) \ + (((v) << 16) & BM_LRADC_CTRL2_RSRVD3) +#define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x00008000 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x0 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x1 +#define BP_LRADC_CTRL2_VTHSENSE 13 +#define BM_LRADC_CTRL2_VTHSENSE 0x00006000 +#define BF_LRADC_CTRL2_VTHSENSE(v) \ + (((v) << 13) & BM_LRADC_CTRL2_VTHSENSE) +#define BM_LRADC_CTRL2_DISABLE_MUXAMP_BYPASS 0x00001000 +#define BP_LRADC_CTRL2_RSRVD2 10 +#define BM_LRADC_CTRL2_RSRVD2 0x00000C00 +#define BF_LRADC_CTRL2_RSRVD2(v) \ + (((v) << 10) & BM_LRADC_CTRL2_RSRVD2) +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x00000200 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x00000100 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 +#define BP_LRADC_CTRL2_TEMP_ISRC1 4 +#define BM_LRADC_CTRL2_TEMP_ISRC1 0x000000F0 +#define BF_LRADC_CTRL2_TEMP_ISRC1(v) \ + (((v) << 4) & BM_LRADC_CTRL2_TEMP_ISRC1) +#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 +#define BP_LRADC_CTRL2_TEMP_ISRC0 0 +#define BM_LRADC_CTRL2_TEMP_ISRC0 0x0000000F +#define BF_LRADC_CTRL2_TEMP_ISRC0(v) \ + (((v) << 0) & BM_LRADC_CTRL2_TEMP_ISRC0) +#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 + +#define HW_LRADC_CTRL3 (0x00000030) +#define HW_LRADC_CTRL3_SET (0x00000034) +#define HW_LRADC_CTRL3_CLR (0x00000038) +#define HW_LRADC_CTRL3_TOG (0x0000003c) + +#define BP_LRADC_CTRL3_RSRVD5 26 +#define BM_LRADC_CTRL3_RSRVD5 0xFC000000 +#define BF_LRADC_CTRL3_RSRVD5(v) \ + (((v) << 26) & BM_LRADC_CTRL3_RSRVD5) +#define BP_LRADC_CTRL3_DISCARD 24 +#define BM_LRADC_CTRL3_DISCARD 0x03000000 +#define BF_LRADC_CTRL3_DISCARD(v) \ + (((v) << 24) & BM_LRADC_CTRL3_DISCARD) +#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 +#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 +#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x00800000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x00400000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 +#define BP_LRADC_CTRL3_RSRVD4 14 +#define BM_LRADC_CTRL3_RSRVD4 0x003FC000 +#define BF_LRADC_CTRL3_RSRVD4(v) \ + (((v) << 14) & BM_LRADC_CTRL3_RSRVD4) +#define BP_LRADC_CTRL3_RSRVD3 10 +#define BM_LRADC_CTRL3_RSRVD3 0x00003C00 +#define BF_LRADC_CTRL3_RSRVD3(v) \ + (((v) << 10) & BM_LRADC_CTRL3_RSRVD3) +#define BP_LRADC_CTRL3_CYCLE_TIME 8 +#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 +#define BF_LRADC_CTRL3_CYCLE_TIME(v) \ + (((v) << 8) & BM_LRADC_CTRL3_CYCLE_TIME) +#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 +#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 +#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 +#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 +#define BP_LRADC_CTRL3_RSRVD2 6 +#define BM_LRADC_CTRL3_RSRVD2 0x000000C0 +#define BF_LRADC_CTRL3_RSRVD2(v) \ + (((v) << 6) & BM_LRADC_CTRL3_RSRVD2) +#define BP_LRADC_CTRL3_HIGH_TIME 4 +#define BM_LRADC_CTRL3_HIGH_TIME 0x00000030 +#define BF_LRADC_CTRL3_HIGH_TIME(v) \ + (((v) << 4) & BM_LRADC_CTRL3_HIGH_TIME) +#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 +#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 +#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 +#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 +#define BP_LRADC_CTRL3_RSRVD1 2 +#define BM_LRADC_CTRL3_RSRVD1 0x0000000C +#define BF_LRADC_CTRL3_RSRVD1(v) \ + (((v) << 2) & BM_LRADC_CTRL3_RSRVD1) +#define BM_LRADC_CTRL3_DELAY_CLOCK 0x00000002 +#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 +#define BM_LRADC_CTRL3_INVERT_CLOCK 0x00000001 +#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 + +#define HW_LRADC_STATUS (0x00000040) +#define HW_LRADC_STATUS_SET (0x00000044) +#define HW_LRADC_STATUS_CLR (0x00000048) +#define HW_LRADC_STATUS_TOG (0x0000004c) + +#define BP_LRADC_STATUS_RSRVD3 29 +#define BM_LRADC_STATUS_RSRVD3 0xE0000000 +#define BF_LRADC_STATUS_RSRVD3(v) \ + (((v) << 29) & BM_LRADC_STATUS_RSRVD3) +#define BM_LRADC_STATUS_BUTTON1_PRESENT 0x10000000 +#define BM_LRADC_STATUS_BUTTON0_PRESENT 0x08000000 +#define BM_LRADC_STATUS_TEMP1_PRESENT 0x04000000 +#define BM_LRADC_STATUS_TEMP0_PRESENT 0x02000000 +#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x01000000 +#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x00800000 +#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x00400000 +#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x00200000 +#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x00100000 +#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x00080000 +#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x00040000 +#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x00020000 +#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x00010000 +#define BP_LRADC_STATUS_RSRVD2 3 +#define BM_LRADC_STATUS_RSRVD2 0x0000FFF8 +#define BF_LRADC_STATUS_RSRVD2(v) \ + (((v) << 3) & BM_LRADC_STATUS_RSRVD2) +#define BM_LRADC_STATUS_BUTTON1_DETECT_RAW 0x00000004 +#define BV_LRADC_STATUS_BUTTON1_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_BUTTON1_DETECT_RAW__HIT 0x1 +#define BM_LRADC_STATUS_BUTTON0_DETECT_RAW 0x00000002 +#define BV_LRADC_STATUS_BUTTON0_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_BUTTON0_DETECT_RAW__HIT 0x1 +#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 + +/* + * multi-register-define name HW_LRADC_CHn + * base 0x00000050 + * count 6 + * offset 0x10 + */ +#define HW_LRADC_CHn(n) (0x00000050 + (n) * 0x10) +#define HW_LRADC_CHn_SET(n) (0x00000054 + (n) * 0x10) +#define HW_LRADC_CHn_CLR(n) (0x00000058 + (n) * 0x10) +#define HW_LRADC_CHn_TOG(n) (0x0000005c + (n) * 0x10) +#define BM_LRADC_CHn_TOGGLE 0x80000000 +#define BM_LRADC_CHn_RSRVD2 0x40000000 +#define BM_LRADC_CHn_ACCUMULATE 0x20000000 +#define BP_LRADC_CHn_NUM_SAMPLES 24 +#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CHn_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CHn_NUM_SAMPLES) +#define BP_LRADC_CHn_RSRVD1 18 +#define BM_LRADC_CHn_RSRVD1 0x00FC0000 +#define BF_LRADC_CHn_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CHn_RSRVD1) +#define BP_LRADC_CHn_VALUE 0 +#define BM_LRADC_CHn_VALUE 0x0003FFFF +#define BF_LRADC_CHn_VALUE(v) \ + (((v) << 0) & BM_LRADC_CHn_VALUE) + +#define HW_LRADC_CH6 (0x000000b0) +#define HW_LRADC_CH6_SET (0x000000b4) +#define HW_LRADC_CH6_CLR (0x000000b8) +#define HW_LRADC_CH6_TOG (0x000000bc) + +#define BM_LRADC_CH6_TOGGLE 0x80000000 +#define BM_LRADC_CH6_RSRVD2 0x40000000 +#define BM_LRADC_CH6_ACCUMULATE 0x20000000 +#define BP_LRADC_CH6_NUM_SAMPLES 24 +#define BM_LRADC_CH6_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH6_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH6_NUM_SAMPLES) +#define BP_LRADC_CH6_RSRVD1 18 +#define BM_LRADC_CH6_RSRVD1 0x00FC0000 +#define BF_LRADC_CH6_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH6_RSRVD1) +#define BP_LRADC_CH6_VALUE 0 +#define BM_LRADC_CH6_VALUE 0x0003FFFF +#define BF_LRADC_CH6_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH6_VALUE) + +#define HW_LRADC_CH7 (0x000000c0) +#define HW_LRADC_CH7_SET (0x000000c4) +#define HW_LRADC_CH7_CLR (0x000000c8) +#define HW_LRADC_CH7_TOG (0x000000cc) + +#define BM_LRADC_CH7_TOGGLE 0x80000000 +#define BM_LRADC_CH7_TESTMODE_TOGGLE 0x40000000 +#define BM_LRADC_CH7_ACCUMULATE 0x20000000 +#define BP_LRADC_CH7_NUM_SAMPLES 24 +#define BM_LRADC_CH7_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH7_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH7_NUM_SAMPLES) +#define BP_LRADC_CH7_RSRVD1 18 +#define BM_LRADC_CH7_RSRVD1 0x00FC0000 +#define BF_LRADC_CH7_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH7_RSRVD1) +#define BP_LRADC_CH7_VALUE 0 +#define BM_LRADC_CH7_VALUE 0x0003FFFF +#define BF_LRADC_CH7_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH7_VALUE) + +/* + * multi-register-define name HW_LRADC_DELAYn + * base 0x000000D0 + * count 4 + * offset 0x10 + */ +#define HW_LRADC_DELAYn(n) (0x000000d0 + (n) * 0x10) +#define HW_LRADC_DELAYn_SET(n) (0x000000d4 + (n) * 0x10) +#define HW_LRADC_DELAYn_CLR(n) (0x000000d8 + (n) * 0x10) +#define HW_LRADC_DELAYn_TOG(n) (0x000000dc + (n) * 0x10) +#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 +#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 +#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) \ + (((v) << 24) & BM_LRADC_DELAYn_TRIGGER_LRADCS) +#define BP_LRADC_DELAYn_RSRVD2 21 +#define BM_LRADC_DELAYn_RSRVD2 0x00E00000 +#define BF_LRADC_DELAYn_RSRVD2(v) \ + (((v) << 21) & BM_LRADC_DELAYn_RSRVD2) +#define BM_LRADC_DELAYn_KICK 0x00100000 +#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 +#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 +#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) \ + (((v) << 16) & BM_LRADC_DELAYn_TRIGGER_DELAYS) +#define BP_LRADC_DELAYn_LOOP_COUNT 11 +#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 +#define BF_LRADC_DELAYn_LOOP_COUNT(v) \ + (((v) << 11) & BM_LRADC_DELAYn_LOOP_COUNT) +#define BP_LRADC_DELAYn_DELAY 0 +#define BM_LRADC_DELAYn_DELAY 0x000007FF +#define BF_LRADC_DELAYn_DELAY(v) \ + (((v) << 0) & BM_LRADC_DELAYn_DELAY) + +#define HW_LRADC_DEBUG0 (0x00000110) +#define HW_LRADC_DEBUG0_SET (0x00000114) +#define HW_LRADC_DEBUG0_CLR (0x00000118) +#define HW_LRADC_DEBUG0_TOG (0x0000011c) + +#define BP_LRADC_DEBUG0_READONLY 16 +#define BM_LRADC_DEBUG0_READONLY 0xFFFF0000 +#define BF_LRADC_DEBUG0_READONLY(v) \ + (((v) << 16) & BM_LRADC_DEBUG0_READONLY) +#define BP_LRADC_DEBUG0_RSRVD1 12 +#define BM_LRADC_DEBUG0_RSRVD1 0x0000F000 +#define BF_LRADC_DEBUG0_RSRVD1(v) \ + (((v) << 12) & BM_LRADC_DEBUG0_RSRVD1) +#define BP_LRADC_DEBUG0_STATE 0 +#define BM_LRADC_DEBUG0_STATE 0x00000FFF +#define BF_LRADC_DEBUG0_STATE(v) \ + (((v) << 0) & BM_LRADC_DEBUG0_STATE) + +#define HW_LRADC_DEBUG1 (0x00000120) +#define HW_LRADC_DEBUG1_SET (0x00000124) +#define HW_LRADC_DEBUG1_CLR (0x00000128) +#define HW_LRADC_DEBUG1_TOG (0x0000012c) + +#define BP_LRADC_DEBUG1_RSRVD3 24 +#define BM_LRADC_DEBUG1_RSRVD3 0xFF000000 +#define BF_LRADC_DEBUG1_RSRVD3(v) \ + (((v) << 24) & BM_LRADC_DEBUG1_RSRVD3) +#define BP_LRADC_DEBUG1_REQUEST 16 +#define BM_LRADC_DEBUG1_REQUEST 0x00FF0000 +#define BF_LRADC_DEBUG1_REQUEST(v) \ + (((v) << 16) & BM_LRADC_DEBUG1_REQUEST) +#define BP_LRADC_DEBUG1_RSRVD2 13 +#define BM_LRADC_DEBUG1_RSRVD2 0x0000E000 +#define BF_LRADC_DEBUG1_RSRVD2(v) \ + (((v) << 13) & BM_LRADC_DEBUG1_RSRVD2) +#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 +#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x00001F00 +#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) \ + (((v) << 8) & BM_LRADC_DEBUG1_TESTMODE_COUNT) +#define BP_LRADC_DEBUG1_RSRVD1 3 +#define BM_LRADC_DEBUG1_RSRVD1 0x000000F8 +#define BF_LRADC_DEBUG1_RSRVD1(v) \ + (((v) << 3) & BM_LRADC_DEBUG1_RSRVD1) +#define BM_LRADC_DEBUG1_TESTMODE6 0x00000004 +#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE5 0x00000002 +#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE 0x00000001 +#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 + +#define HW_LRADC_CONVERSION (0x00000130) +#define HW_LRADC_CONVERSION_SET (0x00000134) +#define HW_LRADC_CONVERSION_CLR (0x00000138) +#define HW_LRADC_CONVERSION_TOG (0x0000013c) + +#define BP_LRADC_CONVERSION_RSRVD3 21 +#define BM_LRADC_CONVERSION_RSRVD3 0xFFE00000 +#define BF_LRADC_CONVERSION_RSRVD3(v) \ + (((v) << 21) & BM_LRADC_CONVERSION_RSRVD3) +#define BM_LRADC_CONVERSION_AUTOMATIC 0x00100000 +#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 +#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 +#define BP_LRADC_CONVERSION_RSRVD2 18 +#define BM_LRADC_CONVERSION_RSRVD2 0x000C0000 +#define BF_LRADC_CONVERSION_RSRVD2(v) \ + (((v) << 18) & BM_LRADC_CONVERSION_RSRVD2) +#define BP_LRADC_CONVERSION_SCALE_FACTOR 16 +#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x00030000 +#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) \ + (((v) << 16) & BM_LRADC_CONVERSION_SCALE_FACTOR) +#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 +#define BP_LRADC_CONVERSION_RSRVD1 10 +#define BM_LRADC_CONVERSION_RSRVD1 0x0000FC00 +#define BF_LRADC_CONVERSION_RSRVD1(v) \ + (((v) << 10) & BM_LRADC_CONVERSION_RSRVD1) +#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 +#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x000003FF +#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) \ + (((v) << 0) & BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE) + +#define HW_LRADC_CTRL4 (0x00000140) +#define HW_LRADC_CTRL4_SET (0x00000144) +#define HW_LRADC_CTRL4_CLR (0x00000148) +#define HW_LRADC_CTRL4_TOG (0x0000014c) + +#define BP_LRADC_CTRL4_LRADC7SELECT 28 +#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 +#define BF_LRADC_CTRL4_LRADC7SELECT(v) \ + (((v) << 28) & BM_LRADC_CTRL4_LRADC7SELECT) +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC6SELECT 24 +#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 +#define BF_LRADC_CTRL4_LRADC6SELECT(v) \ + (((v) << 24) & BM_LRADC_CTRL4_LRADC6SELECT) +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC5SELECT 20 +#define BM_LRADC_CTRL4_LRADC5SELECT 0x00F00000 +#define BF_LRADC_CTRL4_LRADC5SELECT(v) \ + (((v) << 20) & BM_LRADC_CTRL4_LRADC5SELECT) +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC4SELECT 16 +#define BM_LRADC_CTRL4_LRADC4SELECT 0x000F0000 +#define BF_LRADC_CTRL4_LRADC4SELECT(v) \ + (((v) << 16) & BM_LRADC_CTRL4_LRADC4SELECT) +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC3SELECT 12 +#define BM_LRADC_CTRL4_LRADC3SELECT 0x0000F000 +#define BF_LRADC_CTRL4_LRADC3SELECT(v) \ + (((v) << 12) & BM_LRADC_CTRL4_LRADC3SELECT) +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC2SELECT 8 +#define BM_LRADC_CTRL4_LRADC2SELECT 0x00000F00 +#define BF_LRADC_CTRL4_LRADC2SELECT(v) \ + (((v) << 8) & BM_LRADC_CTRL4_LRADC2SELECT) +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC1SELECT 4 +#define BM_LRADC_CTRL4_LRADC1SELECT 0x000000F0 +#define BF_LRADC_CTRL4_LRADC1SELECT(v) \ + (((v) << 4) & BM_LRADC_CTRL4_LRADC1SELECT) +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC0SELECT 0 +#define BM_LRADC_CTRL4_LRADC0SELECT 0x0000000F +#define BF_LRADC_CTRL4_LRADC0SELECT(v) \ + (((v) << 0) & BM_LRADC_CTRL4_LRADC0SELECT) +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xF + +#define HW_LRADC_THRESHOLD0 (0x00000150) +#define HW_LRADC_THRESHOLD0_SET (0x00000154) +#define HW_LRADC_THRESHOLD0_CLR (0x00000158) +#define HW_LRADC_THRESHOLD0_TOG (0x0000015c) + +#define BP_LRADC_THRESHOLD0_RSRVD1 25 +#define BM_LRADC_THRESHOLD0_RSRVD1 0xFE000000 +#define BF_LRADC_THRESHOLD0_RSRVD1(v) \ + (((v) << 25) & BM_LRADC_THRESHOLD0_RSRVD1) +#define BM_LRADC_THRESHOLD0_ENABLE 0x01000000 +#define BM_LRADC_THRESHOLD0_BATTCHRG_DISABLE 0x00800000 +#define BP_LRADC_THRESHOLD0_CHANNEL_SEL 20 +#define BM_LRADC_THRESHOLD0_CHANNEL_SEL 0x00700000 +#define BF_LRADC_THRESHOLD0_CHANNEL_SEL(v) \ + (((v) << 20) & BM_LRADC_THRESHOLD0_CHANNEL_SEL) +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL0 0x0 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL1 0x1 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL2 0x2 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL3 0x3 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL4 0x4 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL5 0x5 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL6 0x6 +#define BV_LRADC_THRESHOLD0_CHANNEL_SEL__CHANNEL7 0x7 +#define BP_LRADC_THRESHOLD0_SETTING 18 +#define BM_LRADC_THRESHOLD0_SETTING 0x000C0000 +#define BF_LRADC_THRESHOLD0_SETTING(v) \ + (((v) << 18) & BM_LRADC_THRESHOLD0_SETTING) +#define BV_LRADC_THRESHOLD0_SETTING__NO_COMPARE 0x0 +#define BV_LRADC_THRESHOLD0_SETTING__DETECT_LOW 0x1 +#define BV_LRADC_THRESHOLD0_SETTING__DETECT_HIGH 0x2 +#define BV_LRADC_THRESHOLD0_SETTING__RESERVED 0x3 +#define BP_LRADC_THRESHOLD0_VALUE 0 +#define BM_LRADC_THRESHOLD0_VALUE 0x0003FFFF +#define BF_LRADC_THRESHOLD0_VALUE(v) \ + (((v) << 0) & BM_LRADC_THRESHOLD0_VALUE) + +#define HW_LRADC_THRESHOLD1 (0x00000160) +#define HW_LRADC_THRESHOLD1_SET (0x00000164) +#define HW_LRADC_THRESHOLD1_CLR (0x00000168) +#define HW_LRADC_THRESHOLD1_TOG (0x0000016c) + +#define BP_LRADC_THRESHOLD1_RSRVD1 25 +#define BM_LRADC_THRESHOLD1_RSRVD1 0xFE000000 +#define BF_LRADC_THRESHOLD1_RSRVD1(v) \ + (((v) << 25) & BM_LRADC_THRESHOLD1_RSRVD1) +#define BM_LRADC_THRESHOLD1_ENABLE 0x01000000 +#define BM_LRADC_THRESHOLD1_BATTCHRG_DISABLE 0x00800000 +#define BP_LRADC_THRESHOLD1_CHANNEL_SEL 20 +#define BM_LRADC_THRESHOLD1_CHANNEL_SEL 0x00700000 +#define BF_LRADC_THRESHOLD1_CHANNEL_SEL(v) \ + (((v) << 20) & BM_LRADC_THRESHOLD1_CHANNEL_SEL) +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL0 0x0 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL1 0x1 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL2 0x2 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL3 0x3 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL4 0x4 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL5 0x5 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL6 0x6 +#define BV_LRADC_THRESHOLD1_CHANNEL_SEL__CHANNEL7 0x7 +#define BP_LRADC_THRESHOLD1_SETTING 18 +#define BM_LRADC_THRESHOLD1_SETTING 0x000C0000 +#define BF_LRADC_THRESHOLD1_SETTING(v) \ + (((v) << 18) & BM_LRADC_THRESHOLD1_SETTING) +#define BV_LRADC_THRESHOLD1_SETTING__NO_COMPARE 0x0 +#define BV_LRADC_THRESHOLD1_SETTING__DETECT_LOW 0x1 +#define BV_LRADC_THRESHOLD1_SETTING__DETECT_HIGH 0x2 +#define BV_LRADC_THRESHOLD1_SETTING__RESERVED 0x3 +#define BP_LRADC_THRESHOLD1_VALUE 0 +#define BM_LRADC_THRESHOLD1_VALUE 0x0003FFFF +#define BF_LRADC_THRESHOLD1_VALUE(v) \ + (((v) << 0) & BM_LRADC_THRESHOLD1_VALUE) + +#define HW_LRADC_VERSION (0x00000170) + +#define BP_LRADC_VERSION_MAJOR 24 +#define BM_LRADC_VERSION_MAJOR 0xFF000000 +#define BF_LRADC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LRADC_VERSION_MAJOR) +#define BP_LRADC_VERSION_MINOR 16 +#define BM_LRADC_VERSION_MINOR 0x00FF0000 +#define BF_LRADC_VERSION_MINOR(v) \ + (((v) << 16) & BM_LRADC_VERSION_MINOR) +#define BP_LRADC_VERSION_STEP 0 +#define BM_LRADC_VERSION_STEP 0x0000FFFF +#define BF_LRADC_VERSION_STEP(v) \ + (((v) << 0) & BM_LRADC_VERSION_STEP) +#endif /* __ARCH_ARM___LRADC_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-ocotp.h b/arch/arm/mach-mx28/include/mach/regs-ocotp.h new file mode 100644 index 000000000000..7907250116ec --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-ocotp.h @@ -0,0 +1,239 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 6 +#define BM_OCOTP_CTRL_RSRVD0 0x000000C0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000003F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_DATA (0x00000010) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +/* + * multi-register-define name HW_OCOTP_CUSTn + * base 0x00000020 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10) +#define BP_OCOTP_CUSTn_BITS 0 +#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF +#define BF_OCOTP_CUSTn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_CRYPTOn + * base 0x00000060 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10) +#define BP_OCOTP_CRYPTOn_BITS 0 +#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF +#define BF_OCOTP_CRYPTOn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x000000A0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x00000100) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_CUSTCAP (0x00000110) + +#define BP_OCOTP_CUSTCAP_RSRVD1 3 +#define BM_OCOTP_CUSTCAP_RSRVD1 0xFFFFFFF8 +#define BF_OCOTP_CUSTCAP_RSRVD1(v) \ + (((v) << 3) & BM_OCOTP_CUSTCAP_RSRVD1) +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002 +#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001 + +#define HW_OCOTP_LOCK (0x00000120) + +#define BM_OCOTP_LOCK_ROM7 0x80000000 +#define BM_OCOTP_LOCK_ROM6 0x40000000 +#define BM_OCOTP_LOCK_ROM5 0x20000000 +#define BM_OCOTP_LOCK_ROM4 0x10000000 +#define BM_OCOTP_LOCK_ROM3 0x08000000 +#define BM_OCOTP_LOCK_ROM2 0x04000000 +#define BM_OCOTP_LOCK_ROM1 0x02000000 +#define BM_OCOTP_LOCK_ROM0 0x01000000 +#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000 +#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000 +#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000 +#define BM_OCOTP_LOCK_PIN 0x00100000 +#define BM_OCOTP_LOCK_OPS 0x00080000 +#define BM_OCOTP_LOCK_UN2 0x00040000 +#define BM_OCOTP_LOCK_UN1 0x00020000 +#define BM_OCOTP_LOCK_UN0 0x00010000 +#define BM_OCOTP_LOCK_SRK 0x00008000 +#define BP_OCOTP_LOCK_UNALLOCATED 12 +#define BM_OCOTP_LOCK_UNALLOCATED 0x00007000 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 12) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_SRK_SHADOW 0x00000800 +#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400 +#define BM_OCOTP_LOCK_CUSTCAP 0x00000200 +#define BM_OCOTP_LOCK_HWSW 0x00000100 +#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020 +#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010 +#define BM_OCOTP_LOCK_CUST3 0x00000008 +#define BM_OCOTP_LOCK_CUST2 0x00000004 +#define BM_OCOTP_LOCK_CUST1 0x00000002 +#define BM_OCOTP_LOCK_CUST0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_OPSn + * base 0x00000130 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_OPSn_BITS 0 +#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF +#define BF_OCOTP_OPSn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_UNn + * base 0x00000170 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10) +#define BP_OCOTP_UNn_BITS 0 +#define BM_OCOTP_UNn_BITS 0xFFFFFFFF +#define BF_OCOTP_UNn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_ROMn + * base 0x000001A0 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_ROMn(n) (0x000001a0 + (n) * 0x10) +#define BP_OCOTP_ROMn_BOOT_MODE 24 +#define BM_OCOTP_ROMn_BOOT_MODE 0xFF000000 +#define BF_OCOTP_ROMn_BOOT_MODE(v) \ + (((v) << 24) & BM_OCOTP_ROMn_BOOT_MODE) +#define BP_OCOTP_ROMn_SD_MMC_MODE 22 +#define BM_OCOTP_ROMn_SD_MMC_MODE 0x00C00000 +#define BF_OCOTP_ROMn_SD_MMC_MODE(v) \ + (((v) << 22) & BM_OCOTP_ROMn_SD_MMC_MODE) +#define BP_OCOTP_ROMn_SD_POWER_GATE_GPIO 20 +#define BM_OCOTP_ROMn_SD_POWER_GATE_GPIO 0x00300000 +#define BF_OCOTP_ROMn_SD_POWER_GATE_GPIO(v) \ + (((v) << 20) & BM_OCOTP_ROMn_SD_POWER_GATE_GPIO) +#define BP_OCOTP_ROMn_SD_POWER_UP_DELAY 14 +#define BM_OCOTP_ROMn_SD_POWER_UP_DELAY 0x000FC000 +#define BF_OCOTP_ROMn_SD_POWER_UP_DELAY(v) \ + (((v) << 14) & BM_OCOTP_ROMn_SD_POWER_UP_DELAY) +#define BP_OCOTP_ROMn_SD_BUS_WIDTH 12 +#define BM_OCOTP_ROMn_SD_BUS_WIDTH 0x00003000 +#define BF_OCOTP_ROMn_SD_BUS_WIDTH(v) \ + (((v) << 12) & BM_OCOTP_ROMn_SD_BUS_WIDTH) +#define BP_OCOTP_ROMn_SSP_SCK_INDEX 8 +#define BM_OCOTP_ROMn_SSP_SCK_INDEX 0x00000F00 +#define BF_OCOTP_ROMn_SSP_SCK_INDEX(v) \ + (((v) << 8) & BM_OCOTP_ROMn_SSP_SCK_INDEX) +#define BM_OCOTP_ROMn_EMMC_USE_DDR 0x00000080 +#define BM_OCOTP_ROMn_DISABLE_SPI_NOR_FAST_READ 0x00000040 +#define BM_OCOTP_ROMn_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020 +#define BM_OCOTP_ROMn_ENABLE_UNENCRYPTED_BOOT 0x00000010 +#define BM_OCOTP_ROMn_SD_MBR_BOOT 0x00000008 +#define BM_OCOTP_ROMn_RSRVD2 0x00000004 +#define BM_OCOTP_ROMn_RSRVD1 0x00000002 +#define BM_OCOTP_ROMn_RSRVD0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_SRKn + * base 0x00000220 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SRKn(n) (0x00000220 + (n) * 0x10) +#define BP_OCOTP_SRKn_BITS 0 +#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF +#define BF_OCOTP_SRKn_BITS(v) (v) + +#define HW_OCOTP_VERSION (0x000002a0) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-power.h b/arch/arm/mach-mx28/include/mach/regs-power.h new file mode 100644 index 000000000000..8f6a8eeefa4b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-power.h @@ -0,0 +1,683 @@ +/* + * Freescale POWER Register Definitions + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___POWER_H +#define __ARCH_ARM___POWER_H + + +#include + +#define REGS_POWER_BASE IO_ADDRESS(POWER_PHYS_ADDR) +#define REGS_POWER_PHYS (0x80044000) +#define REGS_POWER_SIZE 0x00002000 + +#define HW_POWER_CTRL (0x00000000) +#define HW_POWER_CTRL_SET (0x00000004) +#define HW_POWER_CTRL_CLR (0x00000008) +#define HW_POWER_CTRL_TOG (0x0000000c) + +#define BP_POWER_CTRL_RSRVD2 28 +#define BM_POWER_CTRL_RSRVD2 0xF0000000 +#define BF_POWER_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_POWER_CTRL_RSRVD2) +#define BM_POWER_CTRL_PSWITCH_MID_TRAN 0x08000000 +#define BP_POWER_CTRL_RSRVD1 25 +#define BM_POWER_CTRL_RSRVD1 0x06000000 +#define BF_POWER_CTRL_RSRVD1(v) \ + (((v) << 25) & BM_POWER_CTRL_RSRVD1) +#define BM_POWER_CTRL_DCDC4P2_BO_IRQ 0x01000000 +#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO 0x00800000 +#define BM_POWER_CTRL_VDD5V_DROOP_IRQ 0x00400000 +#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP 0x00200000 +#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 +#define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x00080000 +#define BM_POWER_CTRL_POLARITY_PSWITCH 0x00040000 +#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 +#define BM_POWER_CTRL_POLARITY_DC_OK 0x00010000 +#define BM_POWER_CTRL_DC_OK_IRQ 0x00008000 +#define BM_POWER_CTRL_ENIRQ_DC_OK 0x00004000 +#define BM_POWER_CTRL_BATT_BO_IRQ 0x00002000 +#define BM_POWER_CTRL_ENIRQBATT_BO 0x00001000 +#define BM_POWER_CTRL_VDDIO_BO_IRQ 0x00000800 +#define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x00000400 +#define BM_POWER_CTRL_VDDA_BO_IRQ 0x00000200 +#define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x00000100 +#define BM_POWER_CTRL_VDDD_BO_IRQ 0x00000080 +#define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x00000040 +#define BM_POWER_CTRL_POLARITY_VBUSVALID 0x00000020 +#define BM_POWER_CTRL_VBUSVALID_IRQ 0x00000010 +#define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x00000008 +#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x00000004 +#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x00000002 +#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 + +#define HW_POWER_5VCTRL (0x00000010) +#define HW_POWER_5VCTRL_SET (0x00000014) +#define HW_POWER_5VCTRL_CLR (0x00000018) +#define HW_POWER_5VCTRL_TOG (0x0000001c) + +#define BP_POWER_5VCTRL_RSRVD6 30 +#define BM_POWER_5VCTRL_RSRVD6 0xC0000000 +#define BF_POWER_5VCTRL_RSRVD6(v) \ + (((v) << 30) & BM_POWER_5VCTRL_RSRVD6) +#define BP_POWER_5VCTRL_VBUSDROOP_TRSH 28 +#define BM_POWER_5VCTRL_VBUSDROOP_TRSH 0x30000000 +#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v) \ + (((v) << 28) & BM_POWER_5VCTRL_VBUSDROOP_TRSH) +#define BM_POWER_5VCTRL_RSRVD5 0x08000000 +#define BP_POWER_5VCTRL_HEADROOM_ADJ 24 +#define BM_POWER_5VCTRL_HEADROOM_ADJ 0x07000000 +#define BF_POWER_5VCTRL_HEADROOM_ADJ(v) \ + (((v) << 24) & BM_POWER_5VCTRL_HEADROOM_ADJ) +#define BP_POWER_5VCTRL_RSRVD4 22 +#define BM_POWER_5VCTRL_RSRVD4 0x00C00000 +#define BF_POWER_5VCTRL_RSRVD4(v) \ + (((v) << 22) & BM_POWER_5VCTRL_RSRVD4) +#define BP_POWER_5VCTRL_PWD_CHARGE_4P2 20 +#define BM_POWER_5VCTRL_PWD_CHARGE_4P2 0x00300000 +#define BF_POWER_5VCTRL_PWD_CHARGE_4P2(v) \ + (((v) << 20) & BM_POWER_5VCTRL_PWD_CHARGE_4P2) +#define BP_POWER_5VCTRL_RSRVD3 18 +#define BM_POWER_5VCTRL_RSRVD3 0x000C0000 +#define BF_POWER_5VCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_5VCTRL_RSRVD3) +#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT 12 +#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT 0x0003F000 +#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v) \ + (((v) << 12) & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) +#define BM_POWER_5VCTRL_RSRVD2 0x00000800 +#define BP_POWER_5VCTRL_VBUSVALID_TRSH 8 +#define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x00000700 +#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) \ + (((v) << 8) & BM_POWER_5VCTRL_VBUSVALID_TRSH) +#define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x00000080 +#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 +#define BM_POWER_5VCTRL_DCDC_XFER 0x00000020 +#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x00000010 +#define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x00000008 +#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x00000004 +#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS 0x00000002 +#define BM_POWER_5VCTRL_ENABLE_DCDC 0x00000001 + +#define HW_POWER_MINPWR (0x00000020) +#define HW_POWER_MINPWR_SET (0x00000024) +#define HW_POWER_MINPWR_CLR (0x00000028) +#define HW_POWER_MINPWR_TOG (0x0000002c) + +#define BP_POWER_MINPWR_RSRVD1 15 +#define BM_POWER_MINPWR_RSRVD1 0xFFFF8000 +#define BF_POWER_MINPWR_RSRVD1(v) \ + (((v) << 15) & BM_POWER_MINPWR_RSRVD1) +#define BM_POWER_MINPWR_LOWPWR_4P2 0x00004000 +#define BM_POWER_MINPWR_VDAC_DUMP_CTRL 0x00002000 +#define BM_POWER_MINPWR_PWD_BO 0x00001000 +#define BM_POWER_MINPWR_USE_VDDXTAL_VBG 0x00000800 +#define BM_POWER_MINPWR_PWD_ANA_CMPS 0x00000400 +#define BM_POWER_MINPWR_ENABLE_OSC 0x00000200 +#define BM_POWER_MINPWR_SELECT_OSC 0x00000100 +#define BM_POWER_MINPWR_VBG_OFF 0x00000080 +#define BM_POWER_MINPWR_DOUBLE_FETS 0x00000040 +#define BM_POWER_MINPWR_HALF_FETS 0x00000020 +#define BM_POWER_MINPWR_LESSANA_I 0x00000010 +#define BM_POWER_MINPWR_PWD_XTAL24 0x00000008 +#define BM_POWER_MINPWR_DC_STOPCLK 0x00000004 +#define BM_POWER_MINPWR_EN_DC_PFM 0x00000002 +#define BM_POWER_MINPWR_DC_HALFCLK 0x00000001 + +#define HW_POWER_CHARGE (0x00000030) +#define HW_POWER_CHARGE_SET (0x00000034) +#define HW_POWER_CHARGE_CLR (0x00000038) +#define HW_POWER_CHARGE_TOG (0x0000003c) + +#define BP_POWER_CHARGE_RSRVD6 27 +#define BM_POWER_CHARGE_RSRVD6 0xF8000000 +#define BF_POWER_CHARGE_RSRVD6(v) \ + (((v) << 27) & BM_POWER_CHARGE_RSRVD6) +#define BP_POWER_CHARGE_ADJ_VOLT 24 +#define BM_POWER_CHARGE_ADJ_VOLT 0x07000000 +#define BF_POWER_CHARGE_ADJ_VOLT(v) \ + (((v) << 24) & BM_POWER_CHARGE_ADJ_VOLT) +#define BM_POWER_CHARGE_RSRVD5 0x00800000 +#define BM_POWER_CHARGE_ENABLE_LOAD 0x00400000 +#define BM_POWER_CHARGE_RSRVD4 0x00200000 +#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x00100000 +#define BM_POWER_CHARGE_CHRG_STS_OFF 0x00080000 +#define BM_POWER_CHARGE_LIION_4P1 0x00040000 +#define BM_POWER_CHARGE_RSRVD3 0x00020000 +#define BM_POWER_CHARGE_PWD_BATTCHRG 0x00010000 +#define BP_POWER_CHARGE_RSRVD2 14 +#define BM_POWER_CHARGE_RSRVD2 0x0000C000 +#define BF_POWER_CHARGE_RSRVD2(v) \ + (((v) << 14) & BM_POWER_CHARGE_RSRVD2) +#define BM_POWER_CHARGE_ENABLE_CHARGER_USB1 0x00002000 +#define BM_POWER_CHARGE_ENABLE_CHARGER_USB0 0x00001000 +#define BP_POWER_CHARGE_STOP_ILIMIT 8 +#define BM_POWER_CHARGE_STOP_ILIMIT 0x00000F00 +#define BF_POWER_CHARGE_STOP_ILIMIT(v) \ + (((v) << 8) & BM_POWER_CHARGE_STOP_ILIMIT) +#define BP_POWER_CHARGE_RSRVD1 6 +#define BM_POWER_CHARGE_RSRVD1 0x000000C0 +#define BF_POWER_CHARGE_RSRVD1(v) \ + (((v) << 6) & BM_POWER_CHARGE_RSRVD1) +#define BP_POWER_CHARGE_BATTCHRG_I 0 +#define BM_POWER_CHARGE_BATTCHRG_I 0x0000003F +#define BF_POWER_CHARGE_BATTCHRG_I(v) \ + (((v) << 0) & BM_POWER_CHARGE_BATTCHRG_I) + +#define HW_POWER_VDDDCTRL (0x00000040) + +#define BP_POWER_VDDDCTRL_ADJTN 28 +#define BM_POWER_VDDDCTRL_ADJTN 0xF0000000 +#define BF_POWER_VDDDCTRL_ADJTN(v) \ + (((v) << 28) & BM_POWER_VDDDCTRL_ADJTN) +#define BP_POWER_VDDDCTRL_RSRVD4 24 +#define BM_POWER_VDDDCTRL_RSRVD4 0x0F000000 +#define BF_POWER_VDDDCTRL_RSRVD4(v) \ + (((v) << 24) & BM_POWER_VDDDCTRL_RSRVD4) +#define BM_POWER_VDDDCTRL_PWDN_BRNOUT 0x00800000 +#define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x00400000 +#define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x00200000 +#define BM_POWER_VDDDCTRL_DISABLE_FET 0x00100000 +#define BP_POWER_VDDDCTRL_RSRVD3 18 +#define BM_POWER_VDDDCTRL_RSRVD3 0x000C0000 +#define BF_POWER_VDDDCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_VDDDCTRL_RSRVD3) +#define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 +#define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x00030000 +#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) \ + (((v) << 16) & BM_POWER_VDDDCTRL_LINREG_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD2 11 +#define BM_POWER_VDDDCTRL_RSRVD2 0x0000F800 +#define BF_POWER_VDDDCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDDCTRL_RSRVD2) +#define BP_POWER_VDDDCTRL_BO_OFFSET 8 +#define BM_POWER_VDDDCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDDCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDDCTRL_BO_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD1 5 +#define BM_POWER_VDDDCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDDCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDDCTRL_RSRVD1) +#define BP_POWER_VDDDCTRL_TRG 0 +#define BM_POWER_VDDDCTRL_TRG 0x0000001F +#define BF_POWER_VDDDCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDDCTRL_TRG) + +#define HW_POWER_VDDACTRL (0x00000050) + +#define BP_POWER_VDDACTRL_RSRVD4 20 +#define BM_POWER_VDDACTRL_RSRVD4 0xFFF00000 +#define BF_POWER_VDDACTRL_RSRVD4(v) \ + (((v) << 20) & BM_POWER_VDDACTRL_RSRVD4) +#define BM_POWER_VDDACTRL_PWDN_BRNOUT 0x00080000 +#define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x00040000 +#define BM_POWER_VDDACTRL_ENABLE_LINREG 0x00020000 +#define BM_POWER_VDDACTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDACTRL_RSRVD3 14 +#define BM_POWER_VDDACTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDACTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDACTRL_RSRVD3) +#define BP_POWER_VDDACTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDACTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDACTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDACTRL_LINREG_OFFSET) +#define BM_POWER_VDDACTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDACTRL_BO_OFFSET 8 +#define BM_POWER_VDDACTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDACTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDACTRL_BO_OFFSET) +#define BP_POWER_VDDACTRL_RSRVD1 5 +#define BM_POWER_VDDACTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDACTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDACTRL_RSRVD1) +#define BP_POWER_VDDACTRL_TRG 0 +#define BM_POWER_VDDACTRL_TRG 0x0000001F +#define BF_POWER_VDDACTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDACTRL_TRG) + +#define HW_POWER_VDDIOCTRL (0x00000060) + +#define BP_POWER_VDDIOCTRL_RSRVD5 24 +#define BM_POWER_VDDIOCTRL_RSRVD5 0xFF000000 +#define BF_POWER_VDDIOCTRL_RSRVD5(v) \ + (((v) << 24) & BM_POWER_VDDIOCTRL_RSRVD5) +#define BP_POWER_VDDIOCTRL_ADJTN 20 +#define BM_POWER_VDDIOCTRL_ADJTN 0x00F00000 +#define BF_POWER_VDDIOCTRL_ADJTN(v) \ + (((v) << 20) & BM_POWER_VDDIOCTRL_ADJTN) +#define BM_POWER_VDDIOCTRL_RSRVD4 0x00080000 +#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT 0x00040000 +#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x00020000 +#define BM_POWER_VDDIOCTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDIOCTRL_RSRVD3 14 +#define BM_POWER_VDDIOCTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDIOCTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDIOCTRL_RSRVD3) +#define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDIOCTRL_LINREG_OFFSET) +#define BM_POWER_VDDIOCTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDIOCTRL_BO_OFFSET 8 +#define BM_POWER_VDDIOCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDIOCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDIOCTRL_BO_OFFSET) +#define BP_POWER_VDDIOCTRL_RSRVD1 5 +#define BM_POWER_VDDIOCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDIOCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDIOCTRL_RSRVD1) +#define BP_POWER_VDDIOCTRL_TRG 0 +#define BM_POWER_VDDIOCTRL_TRG 0x0000001F +#define BF_POWER_VDDIOCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDIOCTRL_TRG) + +#define HW_POWER_VDDMEMCTRL (0x00000070) + +#define BP_POWER_VDDMEMCTRL_RSRVD2 11 +#define BM_POWER_VDDMEMCTRL_RSRVD2 0xFFFFF800 +#define BF_POWER_VDDMEMCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDMEMCTRL_RSRVD2) +#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 0x00000400 +#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT 0x00000200 +#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG 0x00000100 +#define BP_POWER_VDDMEMCTRL_BO_OFFSET 5 +#define BM_POWER_VDDMEMCTRL_BO_OFFSET 0x000000E0 +#define BF_POWER_VDDMEMCTRL_BO_OFFSET(v) \ + (((v) << 5) & BM_POWER_VDDMEMCTRL_BO_OFFSET) +#define BP_POWER_VDDMEMCTRL_TRG 0 +#define BM_POWER_VDDMEMCTRL_TRG 0x0000001F +#define BF_POWER_VDDMEMCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDMEMCTRL_TRG) + +#define HW_POWER_DCDC4P2 (0x00000080) + +#define BP_POWER_DCDC4P2_DROPOUT_CTRL 28 +#define BM_POWER_DCDC4P2_DROPOUT_CTRL 0xF0000000 +#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v) \ + (((v) << 28) & BM_POWER_DCDC4P2_DROPOUT_CTRL) +#define BP_POWER_DCDC4P2_RSRVD5 26 +#define BM_POWER_DCDC4P2_RSRVD5 0x0C000000 +#define BF_POWER_DCDC4P2_RSRVD5(v) \ + (((v) << 26) & BM_POWER_DCDC4P2_RSRVD5) +#define BP_POWER_DCDC4P2_ISTEAL_THRESH 24 +#define BM_POWER_DCDC4P2_ISTEAL_THRESH 0x03000000 +#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v) \ + (((v) << 24) & BM_POWER_DCDC4P2_ISTEAL_THRESH) +#define BM_POWER_DCDC4P2_ENABLE_4P2 0x00800000 +#define BM_POWER_DCDC4P2_ENABLE_DCDC 0x00400000 +#define BM_POWER_DCDC4P2_HYST_DIR 0x00200000 +#define BM_POWER_DCDC4P2_HYST_THRESH 0x00100000 +#define BM_POWER_DCDC4P2_RSRVD3 0x00080000 +#define BP_POWER_DCDC4P2_TRG 16 +#define BM_POWER_DCDC4P2_TRG 0x00070000 +#define BF_POWER_DCDC4P2_TRG(v) \ + (((v) << 16) & BM_POWER_DCDC4P2_TRG) +#define BP_POWER_DCDC4P2_RSRVD2 13 +#define BM_POWER_DCDC4P2_RSRVD2 0x0000E000 +#define BF_POWER_DCDC4P2_RSRVD2(v) \ + (((v) << 13) & BM_POWER_DCDC4P2_RSRVD2) +#define BP_POWER_DCDC4P2_BO 8 +#define BM_POWER_DCDC4P2_BO 0x00001F00 +#define BF_POWER_DCDC4P2_BO(v) \ + (((v) << 8) & BM_POWER_DCDC4P2_BO) +#define BP_POWER_DCDC4P2_RSRVD1 5 +#define BM_POWER_DCDC4P2_RSRVD1 0x000000E0 +#define BF_POWER_DCDC4P2_RSRVD1(v) \ + (((v) << 5) & BM_POWER_DCDC4P2_RSRVD1) +#define BP_POWER_DCDC4P2_CMPTRIP 0 +#define BM_POWER_DCDC4P2_CMPTRIP 0x0000001F +#define BF_POWER_DCDC4P2_CMPTRIP(v) \ + (((v) << 0) & BM_POWER_DCDC4P2_CMPTRIP) + +#define HW_POWER_MISC (0x00000090) + +#define BP_POWER_MISC_RSRVD2 7 +#define BM_POWER_MISC_RSRVD2 0xFFFFFF80 +#define BF_POWER_MISC_RSRVD2(v) \ + (((v) << 7) & BM_POWER_MISC_RSRVD2) +#define BP_POWER_MISC_FREQSEL 4 +#define BM_POWER_MISC_FREQSEL 0x00000070 +#define BF_POWER_MISC_FREQSEL(v) \ + (((v) << 4) & BM_POWER_MISC_FREQSEL) +#define BM_POWER_MISC_DISABLEFET_BO_LOGIC 0x00000008 +#define BM_POWER_MISC_DELAY_TIMING 0x00000004 +#define BM_POWER_MISC_TEST 0x00000002 +#define BM_POWER_MISC_SEL_PLLCLK 0x00000001 + +#define HW_POWER_DCLIMITS (0x000000a0) + +#define BP_POWER_DCLIMITS_RSRVD3 16 +#define BM_POWER_DCLIMITS_RSRVD3 0xFFFF0000 +#define BF_POWER_DCLIMITS_RSRVD3(v) \ + (((v) << 16) & BM_POWER_DCLIMITS_RSRVD3) +#define BM_POWER_DCLIMITS_RSRVD2 0x00008000 +#define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 +#define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x00007F00 +#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) \ + (((v) << 8) & BM_POWER_DCLIMITS_POSLIMIT_BUCK) +#define BM_POWER_DCLIMITS_RSRVD1 0x00000080 +#define BP_POWER_DCLIMITS_NEGLIMIT 0 +#define BM_POWER_DCLIMITS_NEGLIMIT 0x0000007F +#define BF_POWER_DCLIMITS_NEGLIMIT(v) \ + (((v) << 0) & BM_POWER_DCLIMITS_NEGLIMIT) + +#define HW_POWER_LOOPCTRL (0x000000b0) +#define HW_POWER_LOOPCTRL_SET (0x000000b4) +#define HW_POWER_LOOPCTRL_CLR (0x000000b8) +#define HW_POWER_LOOPCTRL_TOG (0x000000bc) + +#define BP_POWER_LOOPCTRL_RSRVD3 21 +#define BM_POWER_LOOPCTRL_RSRVD3 0xFFE00000 +#define BF_POWER_LOOPCTRL_RSRVD3(v) \ + (((v) << 21) & BM_POWER_LOOPCTRL_RSRVD3) +#define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x00100000 +#define BM_POWER_LOOPCTRL_HYST_SIGN 0x00080000 +#define BM_POWER_LOOPCTRL_EN_CM_HYST 0x00040000 +#define BM_POWER_LOOPCTRL_EN_DF_HYST 0x00020000 +#define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x00010000 +#define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x00008000 +#define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x00004000 +#define BP_POWER_LOOPCTRL_EN_RCSCALE 12 +#define BM_POWER_LOOPCTRL_EN_RCSCALE 0x00003000 +#define BF_POWER_LOOPCTRL_EN_RCSCALE(v) \ + (((v) << 12) & BM_POWER_LOOPCTRL_EN_RCSCALE) +#define BM_POWER_LOOPCTRL_RSRVD2 0x00000800 +#define BP_POWER_LOOPCTRL_DC_FF 8 +#define BM_POWER_LOOPCTRL_DC_FF 0x00000700 +#define BF_POWER_LOOPCTRL_DC_FF(v) \ + (((v) << 8) & BM_POWER_LOOPCTRL_DC_FF) +#define BP_POWER_LOOPCTRL_DC_R 4 +#define BM_POWER_LOOPCTRL_DC_R 0x000000F0 +#define BF_POWER_LOOPCTRL_DC_R(v) \ + (((v) << 4) & BM_POWER_LOOPCTRL_DC_R) +#define BP_POWER_LOOPCTRL_RSRVD1 2 +#define BM_POWER_LOOPCTRL_RSRVD1 0x0000000C +#define BF_POWER_LOOPCTRL_RSRVD1(v) \ + (((v) << 2) & BM_POWER_LOOPCTRL_RSRVD1) +#define BP_POWER_LOOPCTRL_DC_C 0 +#define BM_POWER_LOOPCTRL_DC_C 0x00000003 +#define BF_POWER_LOOPCTRL_DC_C(v) \ + (((v) << 0) & BM_POWER_LOOPCTRL_DC_C) + +#define HW_POWER_STS (0x000000c0) + +#define BP_POWER_STS_RSRVD3 30 +#define BM_POWER_STS_RSRVD3 0xC0000000 +#define BF_POWER_STS_RSRVD3(v) \ + (((v) << 30) & BM_POWER_STS_RSRVD3) +#define BP_POWER_STS_PWRUP_SOURCE 24 +#define BM_POWER_STS_PWRUP_SOURCE 0x3F000000 +#define BF_POWER_STS_PWRUP_SOURCE(v) \ + (((v) << 24) & BM_POWER_STS_PWRUP_SOURCE) +#define BP_POWER_STS_RSRVD2 22 +#define BM_POWER_STS_RSRVD2 0x00C00000 +#define BF_POWER_STS_RSRVD2(v) \ + (((v) << 22) & BM_POWER_STS_RSRVD2) +#define BP_POWER_STS_PSWITCH 20 +#define BM_POWER_STS_PSWITCH 0x00300000 +#define BF_POWER_STS_PSWITCH(v) \ + (((v) << 20) & BM_POWER_STS_PSWITCH) +#define BM_POWER_STS_THERMAL_WARNING 0x00080000 +#define BM_POWER_STS_VDDMEM_BO 0x00040000 +#define BM_POWER_STS_AVALID0_STATUS 0x00020000 +#define BM_POWER_STS_BVALID0_STATUS 0x00010000 +#define BM_POWER_STS_VBUSVALID0_STATUS 0x00008000 +#define BM_POWER_STS_SESSEND0_STATUS 0x00004000 +#define BM_POWER_STS_BATT_BO 0x00002000 +#define BM_POWER_STS_VDD5V_FAULT 0x00001000 +#define BM_POWER_STS_CHRGSTS 0x00000800 +#define BM_POWER_STS_DCDC_4P2_BO 0x00000400 +#define BM_POWER_STS_DC_OK 0x00000200 +#define BM_POWER_STS_VDDIO_BO 0x00000100 +#define BM_POWER_STS_VDDA_BO 0x00000080 +#define BM_POWER_STS_VDDD_BO 0x00000040 +#define BM_POWER_STS_VDD5V_GT_VDDIO 0x00000020 +#define BM_POWER_STS_VDD5V_DROOP 0x00000010 +#define BM_POWER_STS_AVALID0 0x00000008 +#define BM_POWER_STS_BVALID0 0x00000004 +#define BM_POWER_STS_VBUSVALID0 0x00000002 +#define BM_POWER_STS_SESSEND0 0x00000001 + +#define HW_POWER_SPEED (0x000000d0) +#define HW_POWER_SPEED_SET (0x000000d4) +#define HW_POWER_SPEED_CLR (0x000000d8) +#define HW_POWER_SPEED_TOG (0x000000dc) + +#define BP_POWER_SPEED_RSRVD1 24 +#define BM_POWER_SPEED_RSRVD1 0xFF000000 +#define BF_POWER_SPEED_RSRVD1(v) \ + (((v) << 24) & BM_POWER_SPEED_RSRVD1) +#define BP_POWER_SPEED_STATUS 8 +#define BM_POWER_SPEED_STATUS 0x00FFFF00 +#define BF_POWER_SPEED_STATUS(v) \ + (((v) << 8) & BM_POWER_SPEED_STATUS) +#define BP_POWER_SPEED_STATUS_SEL 6 +#define BM_POWER_SPEED_STATUS_SEL 0x000000C0 +#define BF_POWER_SPEED_STATUS_SEL(v) \ + (((v) << 6) & BM_POWER_SPEED_STATUS_SEL) +#define BV_POWER_SPEED_STATUS_SEL__DCDC_STAT 0x0 +#define BV_POWER_SPEED_STATUS_SEL__CORE_STAT 0x1 +#define BV_POWER_SPEED_STATUS_SEL__ARM_STAT 0x2 +#define BP_POWER_SPEED_RSRVD0 2 +#define BM_POWER_SPEED_RSRVD0 0x0000003C +#define BF_POWER_SPEED_RSRVD0(v) \ + (((v) << 2) & BM_POWER_SPEED_RSRVD0) +#define BP_POWER_SPEED_CTRL 0 +#define BM_POWER_SPEED_CTRL 0x00000003 +#define BF_POWER_SPEED_CTRL(v) \ + (((v) << 0) & BM_POWER_SPEED_CTRL) + +#define HW_POWER_BATTMONITOR (0x000000e0) + +#define BP_POWER_BATTMONITOR_RSRVD3 26 +#define BM_POWER_BATTMONITOR_RSRVD3 0xFC000000 +#define BF_POWER_BATTMONITOR_RSRVD3(v) \ + (((v) << 26) & BM_POWER_BATTMONITOR_RSRVD3) +#define BP_POWER_BATTMONITOR_BATT_VAL 16 +#define BM_POWER_BATTMONITOR_BATT_VAL 0x03FF0000 +#define BF_POWER_BATTMONITOR_BATT_VAL(v) \ + (((v) << 16) & BM_POWER_BATTMONITOR_BATT_VAL) +#define BP_POWER_BATTMONITOR_RSRVD2 12 +#define BM_POWER_BATTMONITOR_RSRVD2 0x0000F000 +#define BF_POWER_BATTMONITOR_RSRVD2(v) \ + (((v) << 12) & BM_POWER_BATTMONITOR_RSRVD2) +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_ENABLE 0x00000800 +#define BM_POWER_BATTMONITOR_EN_BATADJ 0x00000400 +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x00000200 +#define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x00000100 +#define BP_POWER_BATTMONITOR_RSRVD1 5 +#define BM_POWER_BATTMONITOR_RSRVD1 0x000000E0 +#define BF_POWER_BATTMONITOR_RSRVD1(v) \ + (((v) << 5) & BM_POWER_BATTMONITOR_RSRVD1) +#define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 +#define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0x0000001F +#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) \ + (((v) << 0) & BM_POWER_BATTMONITOR_BRWNOUT_LVL) + +#define HW_POWER_RESET (0x00000100) +#define HW_POWER_RESET_SET (0x00000104) +#define HW_POWER_RESET_CLR (0x00000108) +#define HW_POWER_RESET_TOG (0x0000010c) + +#define BP_POWER_RESET_UNLOCK 16 +#define BM_POWER_RESET_UNLOCK 0xFFFF0000 +#define BF_POWER_RESET_UNLOCK(v) \ + (((v) << 16) & BM_POWER_RESET_UNLOCK) +#define BV_POWER_RESET_UNLOCK__KEY 0x3E77 +#define BP_POWER_RESET_RSRVD1 3 +#define BM_POWER_RESET_RSRVD1 0x0000FFF8 +#define BF_POWER_RESET_RSRVD1(v) \ + (((v) << 3) & BM_POWER_RESET_RSRVD1) +#define BM_POWER_RESET_FASTFALLPSWITCH_OFF 0x00000004 +#define BM_POWER_RESET_PWD_OFF 0x00000002 +#define BM_POWER_RESET_PWD 0x00000001 + +#define HW_POWER_DEBUG (0x00000110) +#define HW_POWER_DEBUG_SET (0x00000114) +#define HW_POWER_DEBUG_CLR (0x00000118) +#define HW_POWER_DEBUG_TOG (0x0000011c) + +#define BP_POWER_DEBUG_RSRVD0 4 +#define BM_POWER_DEBUG_RSRVD0 0xFFFFFFF0 +#define BF_POWER_DEBUG_RSRVD0(v) \ + (((v) << 4) & BM_POWER_DEBUG_RSRVD0) +#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 +#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +#define BM_POWER_DEBUG_SESSENDPIOLOCK 0x00000001 + +#define HW_POWER_THERMAL (0x00000120) +#define HW_POWER_THERMAL_SET (0x00000124) +#define HW_POWER_THERMAL_CLR (0x00000128) +#define HW_POWER_THERMAL_TOG (0x0000012c) + +#define BP_POWER_THERMAL_RSRVD0 9 +#define BM_POWER_THERMAL_RSRVD0 0xFFFFFE00 +#define BF_POWER_THERMAL_RSRVD0(v) \ + (((v) << 9) & BM_POWER_THERMAL_RSRVD0) +#define BM_POWER_THERMAL_TEST 0x00000100 +#define BM_POWER_THERMAL_PWD 0x00000080 +#define BM_POWER_THERMAL_LOW_POWER 0x00000040 +#define BP_POWER_THERMAL_OFFSET_ADJ 4 +#define BM_POWER_THERMAL_OFFSET_ADJ 0x00000030 +#define BF_POWER_THERMAL_OFFSET_ADJ(v) \ + (((v) << 4) & BM_POWER_THERMAL_OFFSET_ADJ) +#define BM_POWER_THERMAL_OFFSET_ADJ_ENABLE 0x00000008 +#define BP_POWER_THERMAL_TEMP_THRESHOLD 0 +#define BM_POWER_THERMAL_TEMP_THRESHOLD 0x00000007 +#define BF_POWER_THERMAL_TEMP_THRESHOLD(v) \ + (((v) << 0) & BM_POWER_THERMAL_TEMP_THRESHOLD) + +#define HW_POWER_USB1CTRL (0x00000130) +#define HW_POWER_USB1CTRL_SET (0x00000134) +#define HW_POWER_USB1CTRL_CLR (0x00000138) +#define HW_POWER_USB1CTRL_TOG (0x0000013c) + +#define BP_POWER_USB1CTRL_RSRVD0 4 +#define BM_POWER_USB1CTRL_RSRVD0 0xFFFFFFF0 +#define BF_POWER_USB1CTRL_RSRVD0(v) \ + (((v) << 4) & BM_POWER_USB1CTRL_RSRVD0) +#define BM_POWER_USB1CTRL_AVALID1 0x00000008 +#define BM_POWER_USB1CTRL_BVALID1 0x00000004 +#define BM_POWER_USB1CTRL_VBUSVALID1 0x00000002 +#define BM_POWER_USB1CTRL_SESSEND1 0x00000001 + +#define HW_POWER_SPECIAL (0x00000140) +#define HW_POWER_SPECIAL_SET (0x00000144) +#define HW_POWER_SPECIAL_CLR (0x00000148) +#define HW_POWER_SPECIAL_TOG (0x0000014c) + +#define BP_POWER_SPECIAL_TEST 0 +#define BM_POWER_SPECIAL_TEST 0xFFFFFFFF +#define BF_POWER_SPECIAL_TEST(v) (v) + +#define HW_POWER_VERSION (0x00000150) + +#define BP_POWER_VERSION_MAJOR 24 +#define BM_POWER_VERSION_MAJOR 0xFF000000 +#define BF_POWER_VERSION_MAJOR(v) \ + (((v) << 24) & BM_POWER_VERSION_MAJOR) +#define BP_POWER_VERSION_MINOR 16 +#define BM_POWER_VERSION_MINOR 0x00FF0000 +#define BF_POWER_VERSION_MINOR(v) \ + (((v) << 16) & BM_POWER_VERSION_MINOR) +#define BP_POWER_VERSION_STEP 0 +#define BM_POWER_VERSION_STEP 0x0000FFFF +#define BF_POWER_VERSION_STEP(v) \ + (((v) << 0) & BM_POWER_VERSION_STEP) + +#define HW_POWER_ANACLKCTRL (0x00000160) +#define HW_POWER_ANACLKCTRL_SET (0x00000164) +#define HW_POWER_ANACLKCTRL_CLR (0x00000168) +#define HW_POWER_ANACLKCTRL_TOG (0x0000016c) + +#define BM_POWER_ANACLKCTRL_CKGATE_O 0x80000000 +#define BP_POWER_ANACLKCTRL_OUTDIV 28 +#define BM_POWER_ANACLKCTRL_OUTDIV 0x70000000 +#define BF_POWER_ANACLKCTRL_OUTDIV(v) \ + (((v) << 28) & BM_POWER_ANACLKCTRL_OUTDIV) +#define BM_POWER_ANACLKCTRL_INVERT_OUTCLK 0x08000000 +#define BM_POWER_ANACLKCTRL_CKGATE_I 0x04000000 +#define BP_POWER_ANACLKCTRL_RSRVD4 11 +#define BM_POWER_ANACLKCTRL_RSRVD4 0x03FFF800 +#define BF_POWER_ANACLKCTRL_RSRVD4(v) \ + (((v) << 11) & BM_POWER_ANACLKCTRL_RSRVD4) +#define BM_POWER_ANACLKCTRL_DITHER_OFF 0x00000400 +#define BM_POWER_ANACLKCTRL_SLOW_DITHER 0x00000200 +#define BM_POWER_ANACLKCTRL_INVERT_INCLK 0x00000100 +#define BP_POWER_ANACLKCTRL_RSRVD3 6 +#define BM_POWER_ANACLKCTRL_RSRVD3 0x000000C0 +#define BF_POWER_ANACLKCTRL_RSRVD3(v) \ + (((v) << 6) & BM_POWER_ANACLKCTRL_RSRVD3) +#define BP_POWER_ANACLKCTRL_INCLK_SHIFT 4 +#define BM_POWER_ANACLKCTRL_INCLK_SHIFT 0x00000030 +#define BF_POWER_ANACLKCTRL_INCLK_SHIFT(v) \ + (((v) << 4) & BM_POWER_ANACLKCTRL_INCLK_SHIFT) +#define BM_POWER_ANACLKCTRL_RSRVD2 0x00000008 +#define BP_POWER_ANACLKCTRL_INDIV 0 +#define BM_POWER_ANACLKCTRL_INDIV 0x00000007 +#define BF_POWER_ANACLKCTRL_INDIV(v) \ + (((v) << 0) & BM_POWER_ANACLKCTRL_INDIV) + +#define HW_POWER_REFCTRL (0x00000170) +#define HW_POWER_REFCTRL_SET (0x00000174) +#define HW_POWER_REFCTRL_CLR (0x00000178) +#define HW_POWER_REFCTRL_TOG (0x0000017c) + +#define BP_POWER_REFCTRL_RSRVD5 27 +#define BM_POWER_REFCTRL_RSRVD5 0xF8000000 +#define BF_POWER_REFCTRL_RSRVD5(v) \ + (((v) << 27) & BM_POWER_REFCTRL_RSRVD5) +#define BM_POWER_REFCTRL_FASTSETTLING 0x04000000 +#define BM_POWER_REFCTRL_RAISE_REF 0x02000000 +#define BM_POWER_REFCTRL_XTAL_BGR_BIAS 0x01000000 +#define BM_POWER_REFCTRL_RSRVD4 0x00800000 +#define BP_POWER_REFCTRL_VBG_ADJ 20 +#define BM_POWER_REFCTRL_VBG_ADJ 0x00700000 +#define BF_POWER_REFCTRL_VBG_ADJ(v) \ + (((v) << 20) & BM_POWER_REFCTRL_VBG_ADJ) +#define BM_POWER_REFCTRL_LOW_PWR 0x00080000 +#define BM_POWER_REFCTRL_RSRVD3 0x00040000 +#define BP_POWER_REFCTRL_BIAS_CTRL 16 +#define BM_POWER_REFCTRL_BIAS_CTRL 0x00030000 +#define BF_POWER_REFCTRL_BIAS_CTRL(v) \ + (((v) << 16) & BM_POWER_REFCTRL_BIAS_CTRL) +#define BM_POWER_REFCTRL_RSRVD2 0x00008000 +#define BM_POWER_REFCTRL_VDDXTAL_TO_VDDD 0x00004000 +#define BM_POWER_REFCTRL_ADJ_ANA 0x00002000 +#define BM_POWER_REFCTRL_ADJ_VAG 0x00001000 +#define BP_POWER_REFCTRL_ANA_REFVAL 8 +#define BM_POWER_REFCTRL_ANA_REFVAL 0x00000F00 +#define BF_POWER_REFCTRL_ANA_REFVAL(v) \ + (((v) << 8) & BM_POWER_REFCTRL_ANA_REFVAL) +#define BP_POWER_REFCTRL_VAG_VAL 4 +#define BM_POWER_REFCTRL_VAG_VAL 0x000000F0 +#define BF_POWER_REFCTRL_VAG_VAL(v) \ + (((v) << 4) & BM_POWER_REFCTRL_VAG_VAL) +#define BP_POWER_REFCTRL_RSRVD1 0 +#define BM_POWER_REFCTRL_RSRVD1 0x0000000F +#define BF_POWER_REFCTRL_RSRVD1(v) \ + (((v) << 0) & BM_POWER_REFCTRL_RSRVD1) +#endif /* __ARCH_ARM___POWER_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-pwm.h b/arch/arm/mach-mx28/include/mach/regs-pwm.h new file mode 100644 index 000000000000..ac0ebfbb7cca --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-pwm.h @@ -0,0 +1,147 @@ +/* + * Freescale PWM Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.30 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PWM_H +#define __ARCH_ARM___PWM_H + +#include + +#define REGS_PWM_BASE IO_ADDRESS(PWM_PHYS_ADDR) +#define REGS_PWM_PHYS (0x80064000) +#define REGS_PWM_SIZE 0x00002000 + +#define HW_PWM_CTRL (0x00000000) +#define HW_PWM_CTRL_SET (0x00000004) +#define HW_PWM_CTRL_CLR (0x00000008) +#define HW_PWM_CTRL_TOG (0x0000000c) + +#define BM_PWM_CTRL_SFTRST 0x80000000 +#define BM_PWM_CTRL_CLKGATE 0x40000000 +#define BM_PWM_CTRL_PWM7_PRESENT 0x20000000 +#define BM_PWM_CTRL_PWM6_PRESENT 0x10000000 +#define BM_PWM_CTRL_PWM5_PRESENT 0x08000000 +#define BM_PWM_CTRL_PWM4_PRESENT 0x04000000 +#define BM_PWM_CTRL_PWM3_PRESENT 0x02000000 +#define BM_PWM_CTRL_PWM2_PRESENT 0x01000000 +#define BM_PWM_CTRL_PWM1_PRESENT 0x00800000 +#define BM_PWM_CTRL_PWM0_PRESENT 0x00400000 +#define BP_PWM_CTRL_RSRVD1 10 +#define BM_PWM_CTRL_RSRVD1 0x003FFC00 +#define BF_PWM_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_PWM_CTRL_RSRVD1) +#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN 0x00000200 +#define BM_PWM_CTRL_RSRVD2 0x00000100 +#define BM_PWM_CTRL_PWM7_ENABLE 0x00000080 +#define BM_PWM_CTRL_PWM6_ENABLE 0x00000040 +#define BM_PWM_CTRL_PWM5_ENABLE 0x00000020 +#define BM_PWM_CTRL_PWM4_ENABLE 0x00000010 +#define BM_PWM_CTRL_PWM3_ENABLE 0x00000008 +#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 +#define BM_PWM_CTRL_PWM1_ENABLE 0x00000002 +#define BM_PWM_CTRL_PWM0_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PWM_ACTIVEn + * base 0x00000010 + * count 8 + * offset 0x20 + */ +#define HW_PWM_ACTIVEn(n) (0x00000010 + (n) * 0x20) +#define HW_PWM_ACTIVEn_SET(n) (0x00000014 + (n) * 0x20) +#define HW_PWM_ACTIVEn_CLR(n) (0x00000018 + (n) * 0x20) +#define HW_PWM_ACTIVEn_TOG(n) (0x0000001c + (n) * 0x20) +#define BP_PWM_ACTIVEn_INACTIVE 16 +#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 +#define BF_PWM_ACTIVEn_INACTIVE(v) \ + (((v) << 16) & BM_PWM_ACTIVEn_INACTIVE) +#define BP_PWM_ACTIVEn_ACTIVE 0 +#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF +#define BF_PWM_ACTIVEn_ACTIVE(v) \ + (((v) << 0) & BM_PWM_ACTIVEn_ACTIVE) + +/* + * multi-register-define name HW_PWM_PERIODn + * base 0x00000020 + * count 8 + * offset 0x20 + */ +#define HW_PWM_PERIODn(n) (0x00000020 + (n) * 0x20) +#define HW_PWM_PERIODn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_PWM_PERIODn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_PWM_PERIODn_TOG(n) (0x0000002c + (n) * 0x20) +#define BP_PWM_PERIODn_RSRVD2 27 +#define BM_PWM_PERIODn_RSRVD2 0xF8000000 +#define BF_PWM_PERIODn_RSRVD2(v) \ + (((v) << 27) & BM_PWM_PERIODn_RSRVD2) +#define BM_PWM_PERIODn_HSADC_OUT 0x04000000 +#define BM_PWM_PERIODn_HSADC_CLK_SEL 0x02000000 +#define BM_PWM_PERIODn_MATT_SEL 0x01000000 +#define BM_PWM_PERIODn_MATT 0x00800000 +#define BP_PWM_PERIODn_CDIV 20 +#define BM_PWM_PERIODn_CDIV 0x00700000 +#define BF_PWM_PERIODn_CDIV(v) \ + (((v) << 20) & BM_PWM_PERIODn_CDIV) +#define BV_PWM_PERIODn_CDIV__DIV_1 0x0 +#define BV_PWM_PERIODn_CDIV__DIV_2 0x1 +#define BV_PWM_PERIODn_CDIV__DIV_4 0x2 +#define BV_PWM_PERIODn_CDIV__DIV_8 0x3 +#define BV_PWM_PERIODn_CDIV__DIV_16 0x4 +#define BV_PWM_PERIODn_CDIV__DIV_64 0x5 +#define BV_PWM_PERIODn_CDIV__DIV_256 0x6 +#define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 +#define BP_PWM_PERIODn_INACTIVE_STATE 18 +#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 +#define BF_PWM_PERIODn_INACTIVE_STATE(v) \ + (((v) << 18) & BM_PWM_PERIODn_INACTIVE_STATE) +#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_ACTIVE_STATE 16 +#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 +#define BF_PWM_PERIODn_ACTIVE_STATE(v) \ + (((v) << 16) & BM_PWM_PERIODn_ACTIVE_STATE) +#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_PERIOD 0 +#define BM_PWM_PERIODn_PERIOD 0x0000FFFF +#define BF_PWM_PERIODn_PERIOD(v) \ + (((v) << 0) & BM_PWM_PERIODn_PERIOD) + +#define HW_PWM_VERSION (0x00000110) + +#define BP_PWM_VERSION_MAJOR 24 +#define BM_PWM_VERSION_MAJOR 0xFF000000 +#define BF_PWM_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PWM_VERSION_MAJOR) +#define BP_PWM_VERSION_MINOR 16 +#define BM_PWM_VERSION_MINOR 0x00FF0000 +#define BF_PWM_VERSION_MINOR(v) \ + (((v) << 16) & BM_PWM_VERSION_MINOR) +#define BP_PWM_VERSION_STEP 0 +#define BM_PWM_VERSION_STEP 0x0000FFFF +#define BF_PWM_VERSION_STEP(v) \ + (((v) << 0) & BM_PWM_VERSION_STEP) +#endif /* __ARCH_ARM___PWM_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-pxp.h b/arch/arm/mach-mx28/include/mach/regs-pxp.h new file mode 100644 index 000000000000..2feb8f8db649 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-pxp.h @@ -0,0 +1,518 @@ +/* + * Freescale PXP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.57 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BP_PXP_CTRL_RSVD2 28 +#define BM_PXP_CTRL_RSVD2 0x30000000 +#define BF_PXP_CTRL_RSVD2(v) \ + (((v) << 28) & BM_PXP_CTRL_RSVD2) +#define BP_PXP_CTRL_INTERLACED_OUTPUT 26 +#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000 +#define BF_PXP_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BM_PXP_CTRL_DELTA 0x00100000 +#define BM_PXP_CTRL_CROP 0x00080000 +#define BM_PXP_CTRL_SCALE 0x00040000 +#define BM_PXP_CTRL_UPSAMPLE 0x00020000 +#define BM_PXP_CTRL_SUBSAMPLE 0x00010000 +#define BP_PXP_CTRL_S0_FORMAT 12 +#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 +#define BF_PXP_CTRL_S0_FORMAT(v) \ + (((v) << 12) & BM_PXP_CTRL_S0_FORMAT) +#define BV_PXP_CTRL_S0_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8 +#define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9 +#define BV_PXP_CTRL_S0_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_S0_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_S0_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_S0_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_S0_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_S0_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_OUTBUF_FORMAT 4 +#define BM_PXP_CTRL_OUTBUF_FORMAT 0x000000F0 +#define BF_PXP_CTRL_OUTBUF_FORMAT(v) \ + (((v) << 4) & BM_PXP_CTRL_OUTBUF_FORMAT) +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P 0x2 +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555 0x3 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV444 0x7 +#define BV_PXP_CTRL_OUTBUF_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_OUTBUF_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 8 +#define BM_PXP_STAT_RSVD2 0x0000FF00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 8) & BM_PXP_STAT_RSVD2) +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUTBUF (0x00000020) + +#define BP_PXP_OUTBUF_ADDR 0 +#define BM_PXP_OUTBUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF_ADDR(v) (v) + +#define HW_PXP_OUTBUF2 (0x00000030) + +#define BP_PXP_OUTBUF2_ADDR 0 +#define BM_PXP_OUTBUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF2_ADDR(v) (v) + +#define HW_PXP_OUTSIZE (0x00000040) + +#define BP_PXP_OUTSIZE_ALPHA 24 +#define BM_PXP_OUTSIZE_ALPHA 0xFF000000 +#define BF_PXP_OUTSIZE_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUTSIZE_ALPHA) +#define BP_PXP_OUTSIZE_WIDTH 12 +#define BM_PXP_OUTSIZE_WIDTH 0x00FFF000 +#define BF_PXP_OUTSIZE_WIDTH(v) \ + (((v) << 12) & BM_PXP_OUTSIZE_WIDTH) +#define BP_PXP_OUTSIZE_HEIGHT 0 +#define BM_PXP_OUTSIZE_HEIGHT 0x00000FFF +#define BF_PXP_OUTSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OUTSIZE_HEIGHT) + +#define HW_PXP_S0BUF (0x00000050) + +#define BP_PXP_S0BUF_ADDR 0 +#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0BUF_ADDR(v) (v) + +#define HW_PXP_S0UBUF (0x00000060) + +#define BP_PXP_S0UBUF_ADDR 0 +#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0UBUF_ADDR(v) (v) + +#define HW_PXP_S0VBUF (0x00000070) + +#define BP_PXP_S0VBUF_ADDR 0 +#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0VBUF_ADDR(v) (v) + +#define HW_PXP_S0PARAM (0x00000080) + +#define BP_PXP_S0PARAM_XBASE 24 +#define BM_PXP_S0PARAM_XBASE 0xFF000000 +#define BF_PXP_S0PARAM_XBASE(v) \ + (((v) << 24) & BM_PXP_S0PARAM_XBASE) +#define BP_PXP_S0PARAM_YBASE 16 +#define BM_PXP_S0PARAM_YBASE 0x00FF0000 +#define BF_PXP_S0PARAM_YBASE(v) \ + (((v) << 16) & BM_PXP_S0PARAM_YBASE) +#define BP_PXP_S0PARAM_WIDTH 8 +#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 +#define BF_PXP_S0PARAM_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0PARAM_WIDTH) +#define BP_PXP_S0PARAM_HEIGHT 0 +#define BM_PXP_S0PARAM_HEIGHT 0x000000FF +#define BF_PXP_S0PARAM_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0PARAM_HEIGHT) + +#define HW_PXP_S0BACKGROUND (0x00000090) + +#define BP_PXP_S0BACKGROUND_COLOR 0 +#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_S0BACKGROUND_COLOR(v) (v) + +#define HW_PXP_S0CROP (0x000000a0) + +#define BP_PXP_S0CROP_XBASE 24 +#define BM_PXP_S0CROP_XBASE 0xFF000000 +#define BF_PXP_S0CROP_XBASE(v) \ + (((v) << 24) & BM_PXP_S0CROP_XBASE) +#define BP_PXP_S0CROP_YBASE 16 +#define BM_PXP_S0CROP_YBASE 0x00FF0000 +#define BF_PXP_S0CROP_YBASE(v) \ + (((v) << 16) & BM_PXP_S0CROP_YBASE) +#define BP_PXP_S0CROP_WIDTH 8 +#define BM_PXP_S0CROP_WIDTH 0x0000FF00 +#define BF_PXP_S0CROP_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0CROP_WIDTH) +#define BP_PXP_S0CROP_HEIGHT 0 +#define BM_PXP_S0CROP_HEIGHT 0x000000FF +#define BF_PXP_S0CROP_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0CROP_HEIGHT) + +#define HW_PXP_S0SCALE (0x000000b0) + +#define BM_PXP_S0SCALE_RSVD2 0x80000000 +#define BP_PXP_S0SCALE_YSCALE 16 +#define BM_PXP_S0SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_S0SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_S0SCALE_YSCALE) +#define BM_PXP_S0SCALE_RSVD1 0x00008000 +#define BP_PXP_S0SCALE_XSCALE 0 +#define BM_PXP_S0SCALE_XSCALE 0x00007FFF +#define BF_PXP_S0SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_S0SCALE_XSCALE) + +#define HW_PXP_S0OFFSET (0x000000c0) + +#define BP_PXP_S0OFFSET_RSVD2 28 +#define BM_PXP_S0OFFSET_RSVD2 0xF0000000 +#define BF_PXP_S0OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_S0OFFSET_RSVD2) +#define BP_PXP_S0OFFSET_YOFFSET 16 +#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_S0OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_S0OFFSET_YOFFSET) +#define BP_PXP_S0OFFSET_RSVD1 12 +#define BM_PXP_S0OFFSET_RSVD1 0x0000F000 +#define BF_PXP_S0OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_S0OFFSET_RSVD1) +#define BP_PXP_S0OFFSET_XOFFSET 0 +#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_S0OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_S0OFFSET_XOFFSET) + +#define HW_PXP_CSCCOEFF0 (0x000000d0) + +#define BM_PXP_CSCCOEFF0_YCBCR_MODE 0x80000000 +#define BP_PXP_CSCCOEFF0_RSVD1 29 +#define BM_PXP_CSCCOEFF0_RSVD1 0x60000000 +#define BF_PXP_CSCCOEFF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSCCOEFF0_RSVD1) +#define BP_PXP_CSCCOEFF0_C0 18 +#define BM_PXP_CSCCOEFF0_C0 0x1FFC0000 +#define BF_PXP_CSCCOEFF0_C0(v) \ + (((v) << 18) & BM_PXP_CSCCOEFF0_C0) +#define BP_PXP_CSCCOEFF0_UV_OFFSET 9 +#define BM_PXP_CSCCOEFF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSCCOEFF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSCCOEFF0_UV_OFFSET) +#define BP_PXP_CSCCOEFF0_Y_OFFSET 0 +#define BM_PXP_CSCCOEFF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSCCOEFF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF0_Y_OFFSET) + +#define HW_PXP_CSCCOEFF1 (0x000000e0) + +#define BP_PXP_CSCCOEFF1_RSVD1 27 +#define BM_PXP_CSCCOEFF1_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF1_RSVD1) +#define BP_PXP_CSCCOEFF1_C1 16 +#define BM_PXP_CSCCOEFF1_C1 0x07FF0000 +#define BF_PXP_CSCCOEFF1_C1(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF1_C1) +#define BP_PXP_CSCCOEFF1_RSVD0 11 +#define BM_PXP_CSCCOEFF1_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF1_RSVD0) +#define BP_PXP_CSCCOEFF1_C4 0 +#define BM_PXP_CSCCOEFF1_C4 0x000007FF +#define BF_PXP_CSCCOEFF1_C4(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF1_C4) + +#define HW_PXP_CSCCOEFF2 (0x000000f0) + +#define BP_PXP_CSCCOEFF2_RSVD1 27 +#define BM_PXP_CSCCOEFF2_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF2_RSVD1) +#define BP_PXP_CSCCOEFF2_C2 16 +#define BM_PXP_CSCCOEFF2_C2 0x07FF0000 +#define BF_PXP_CSCCOEFF2_C2(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF2_C2) +#define BP_PXP_CSCCOEFF2_RSVD0 11 +#define BM_PXP_CSCCOEFF2_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF2_RSVD0) +#define BP_PXP_CSCCOEFF2_C3 0 +#define BM_PXP_CSCCOEFF2_C3 0x000007FF +#define BF_PXP_CSCCOEFF2_C3(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF2_C3) + +#define HW_PXP_NEXT (0x00000100) +#define HW_PXP_NEXT_SET (0x00000104) +#define HW_PXP_NEXT_CLR (0x00000108) +#define HW_PXP_NEXT_TOG (0x0000010c) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_S0COLORKEYLOW (0x00000180) + +#define BP_PXP_S0COLORKEYLOW_RSVD1 24 +#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1) +#define BP_PXP_S0COLORKEYLOW_PIXEL 0 +#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL) + +#define HW_PXP_S0COLORKEYHIGH (0x00000190) + +#define BP_PXP_S0COLORKEYHIGH_RSVD1 24 +#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1) +#define BP_PXP_S0COLORKEYHIGH_PIXEL 0 +#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL) + +#define HW_PXP_OLCOLORKEYLOW (0x000001a0) + +#define BP_PXP_OLCOLORKEYLOW_RSVD1 24 +#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1) +#define BP_PXP_OLCOLORKEYLOW_PIXEL 0 +#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL) + +#define HW_PXP_OLCOLORKEYHIGH (0x000001b0) + +#define BP_PXP_OLCOLORKEYHIGH_RSVD1 24 +#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1) +#define BP_PXP_OLCOLORKEYHIGH_PIXEL 0 +#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL) + +#define HW_PXP_DEBUGCTRL (0x000001d0) + +#define BP_PXP_DEBUGCTRL_RSVD 9 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFE00 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 9) & BM_PXP_DEBUGCTRL_RSVD) +#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS 0x00000100 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8 +#define BV_PXP_DEBUGCTRL_SELECT__TLBCOUNT 0xF0 +#define BV_PXP_DEBUGCTRL_SELECT__TLBHIT 0xF1 +#define BV_PXP_DEBUGCTRL_SELECT__TLBMISS 0xF2 +#define BV_PXP_DEBUGCTRL_SELECT__TLBLAT 0xF3 +#define BV_PXP_DEBUGCTRL_SELECT__TLBSTATE 0xF8 + +#define HW_PXP_DEBUG (0x000001e0) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x000001f0) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +/* + * multi-register-define name HW_PXP_OLn + * base 0x00000200 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLn(n) (0x00000200 + (n) * 0x40) +#define BP_PXP_OLn_ADDR 0 +#define BM_PXP_OLn_ADDR 0xFFFFFFFF +#define BF_PXP_OLn_ADDR(v) (v) + +/* + * multi-register-define name HW_PXP_OLnSIZE + * base 0x00000210 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnSIZE(n) (0x00000210 + (n) * 0x40) +#define BP_PXP_OLnSIZE_XBASE 24 +#define BM_PXP_OLnSIZE_XBASE 0xFF000000 +#define BF_PXP_OLnSIZE_XBASE(v) \ + (((v) << 24) & BM_PXP_OLnSIZE_XBASE) +#define BP_PXP_OLnSIZE_YBASE 16 +#define BM_PXP_OLnSIZE_YBASE 0x00FF0000 +#define BF_PXP_OLnSIZE_YBASE(v) \ + (((v) << 16) & BM_PXP_OLnSIZE_YBASE) +#define BP_PXP_OLnSIZE_WIDTH 8 +#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 +#define BF_PXP_OLnSIZE_WIDTH(v) \ + (((v) << 8) & BM_PXP_OLnSIZE_WIDTH) +#define BP_PXP_OLnSIZE_HEIGHT 0 +#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF +#define BF_PXP_OLnSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OLnSIZE_HEIGHT) + +/* + * multi-register-define name HW_PXP_OLnPARAM + * base 0x00000220 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM(n) (0x00000220 + (n) * 0x40) +#define BP_PXP_OLnPARAM_RSVD1 20 +#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000 +#define BF_PXP_OLnPARAM_RSVD1(v) \ + (((v) << 20) & BM_PXP_OLnPARAM_RSVD1) +#define BP_PXP_OLnPARAM_ROP 16 +#define BM_PXP_OLnPARAM_ROP 0x000F0000 +#define BF_PXP_OLnPARAM_ROP(v) \ + (((v) << 16) & BM_PXP_OLnPARAM_ROP) +#define BV_PXP_OLnPARAM_ROP__MASKOL 0x0 +#define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1 +#define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2 +#define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3 +#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4 +#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5 +#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6 +#define BV_PXP_OLnPARAM_ROP__NOT 0x7 +#define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8 +#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9 +#define BV_PXP_OLnPARAM_ROP__XOROL 0xA +#define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xB +#define BP_PXP_OLnPARAM_ALPHA 8 +#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 +#define BF_PXP_OLnPARAM_ALPHA(v) \ + (((v) << 8) & BM_PXP_OLnPARAM_ALPHA) +#define BP_PXP_OLnPARAM_FORMAT 4 +#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 +#define BF_PXP_OLnPARAM_FORMAT(v) \ + (((v) << 4) & BM_PXP_OLnPARAM_FORMAT) +#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0 +#define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1 +#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3 +#define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4 +#define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5 +#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 +#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 +#define BF_PXP_OLnPARAM_ALPHA_CNTL(v) \ + (((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL) +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3 +#define BM_PXP_OLnPARAM_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PXP_OLnPARAM2 + * base 0x00000230 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM2(n) (0x00000230 + (n) * 0x40) +#define BP_PXP_OLnPARAM2_RSVD 0 +#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF +#define BF_PXP_OLnPARAM2_RSVD(v) (v) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-rtc.h b/arch/arm/mach-mx28/include/mach/regs-rtc.h new file mode 100644 index 000000000000..bdb3ac23a2a0 --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-rtc.h @@ -0,0 +1,226 @@ +/* + * Freescale RTC Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.75 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___RTC_H +#define __ARCH_ARM___RTC_H + + +#define HW_RTC_CTRL (0x00000000) +#define HW_RTC_CTRL_SET (0x00000004) +#define HW_RTC_CTRL_CLR (0x00000008) +#define HW_RTC_CTRL_TOG (0x0000000c) + +#define BM_RTC_CTRL_SFTRST 0x80000000 +#define BM_RTC_CTRL_CLKGATE 0x40000000 +#define BP_RTC_CTRL_RSVD0 7 +#define BM_RTC_CTRL_RSVD0 0x3FFFFF80 +#define BF_RTC_CTRL_RSVD0(v) \ + (((v) << 7) & BM_RTC_CTRL_RSVD0) +#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x00000040 +#define BM_RTC_CTRL_FORCE_UPDATE 0x00000020 +#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 +#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 +#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 +#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 +#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 + +#define HW_RTC_STAT (0x00000010) +#define HW_RTC_STAT_SET (0x00000014) +#define HW_RTC_STAT_CLR (0x00000018) +#define HW_RTC_STAT_TOG (0x0000001c) + +#define BM_RTC_STAT_RTC_PRESENT 0x80000000 +#define BM_RTC_STAT_ALARM_PRESENT 0x40000000 +#define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 +#define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 +#define BM_RTC_STAT_XTAL32768_PRESENT 0x08000000 +#define BP_RTC_STAT_RSVD1 24 +#define BM_RTC_STAT_RSVD1 0x07000000 +#define BF_RTC_STAT_RSVD1(v) \ + (((v) << 24) & BM_RTC_STAT_RSVD1) +#define BP_RTC_STAT_STALE_REGS 16 +#define BM_RTC_STAT_STALE_REGS 0x00FF0000 +#define BF_RTC_STAT_STALE_REGS(v) \ + (((v) << 16) & BM_RTC_STAT_STALE_REGS) +#define BP_RTC_STAT_NEW_REGS 8 +#define BM_RTC_STAT_NEW_REGS 0x0000FF00 +#define BF_RTC_STAT_NEW_REGS(v) \ + (((v) << 8) & BM_RTC_STAT_NEW_REGS) +#define BP_RTC_STAT_RSVD0 0 +#define BM_RTC_STAT_RSVD0 0x000000FF +#define BF_RTC_STAT_RSVD0(v) \ + (((v) << 0) & BM_RTC_STAT_RSVD0) + +#define HW_RTC_MILLISECONDS (0x00000020) +#define HW_RTC_MILLISECONDS_SET (0x00000024) +#define HW_RTC_MILLISECONDS_CLR (0x00000028) +#define HW_RTC_MILLISECONDS_TOG (0x0000002c) + +#define BP_RTC_MILLISECONDS_COUNT 0 +#define BM_RTC_MILLISECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_MILLISECONDS_COUNT(v) (v) + +#define HW_RTC_SECONDS (0x00000030) +#define HW_RTC_SECONDS_SET (0x00000034) +#define HW_RTC_SECONDS_CLR (0x00000038) +#define HW_RTC_SECONDS_TOG (0x0000003c) + +#define BP_RTC_SECONDS_COUNT 0 +#define BM_RTC_SECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_SECONDS_COUNT(v) (v) + +#define HW_RTC_ALARM (0x00000040) +#define HW_RTC_ALARM_SET (0x00000044) +#define HW_RTC_ALARM_CLR (0x00000048) +#define HW_RTC_ALARM_TOG (0x0000004c) + +#define BP_RTC_ALARM_VALUE 0 +#define BM_RTC_ALARM_VALUE 0xFFFFFFFF +#define BF_RTC_ALARM_VALUE(v) (v) + +#define HW_RTC_WATCHDOG (0x00000050) +#define HW_RTC_WATCHDOG_SET (0x00000054) +#define HW_RTC_WATCHDOG_CLR (0x00000058) +#define HW_RTC_WATCHDOG_TOG (0x0000005c) + +#define BP_RTC_WATCHDOG_COUNT 0 +#define BM_RTC_WATCHDOG_COUNT 0xFFFFFFFF +#define BF_RTC_WATCHDOG_COUNT(v) (v) + +#define HW_RTC_PERSISTENT0 (0x00000060) +#define HW_RTC_PERSISTENT0_SET (0x00000064) +#define HW_RTC_PERSISTENT0_CLR (0x00000068) +#define HW_RTC_PERSISTENT0_TOG (0x0000006c) + +#define BP_RTC_PERSISTENT0_ADJ_POSLIMITBUCK 28 +#define BM_RTC_PERSISTENT0_ADJ_POSLIMITBUCK 0xF0000000 +#define BF_RTC_PERSISTENT0_ADJ_POSLIMITBUCK(v) \ + (((v) << 28) & BM_RTC_PERSISTENT0_ADJ_POSLIMITBUCK) +#define BP_RTC_PERSISTENT0_SPARE_ANALOG 22 +#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0x0FC00000 +#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) \ + (((v) << 22) & BM_RTC_PERSISTENT0_SPARE_ANALOG) +#define BM_RTC_PERSISTENT0_EXTERNAL_RESET 0x00200000 +#define BM_RTC_PERSISTENT0_THERMAL_RESET 0x00100000 +#define BM_RTC_PERSISTENT0_RELEASE_GND 0x00080000 +#define BM_RTC_PERSISTENT0_ENABLE_LRADC_PWRUP 0x00040000 +#define BM_RTC_PERSISTENT0_AUTO_RESTART 0x00020000 +#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x00010000 +#define BP_RTC_PERSISTENT0_LOWERBIAS 14 +#define BM_RTC_PERSISTENT0_LOWERBIAS 0x0000C000 +#define BF_RTC_PERSISTENT0_LOWERBIAS(v) \ + (((v) << 14) & BM_RTC_PERSISTENT0_LOWERBIAS) +#define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x00002000 +#define BP_RTC_PERSISTENT0_MSEC_RES 8 +#define BM_RTC_PERSISTENT0_MSEC_RES 0x00001F00 +#define BF_RTC_PERSISTENT0_MSEC_RES(v) \ + (((v) << 8) & BM_RTC_PERSISTENT0_MSEC_RES) +#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 +#define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x00000040 +#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 +#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 +#define BM_RTC_PERSISTENT0_LCK_SECS 0x00000008 +#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 +#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 +#define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x00000001 + +#define HW_RTC_PERSISTENT1 (0x00000070) +#define HW_RTC_PERSISTENT1_SET (0x00000074) +#define HW_RTC_PERSISTENT1_CLR (0x00000078) +#define HW_RTC_PERSISTENT1_TOG (0x0000007c) + +#define BP_RTC_PERSISTENT1_GENERAL 0 +#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT1_GENERAL(v) (v) +#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 +#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x0800 +#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x0400 +#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x0200 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x0100 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x0080 + +#define HW_RTC_PERSISTENT2 (0x00000080) +#define HW_RTC_PERSISTENT2_SET (0x00000084) +#define HW_RTC_PERSISTENT2_CLR (0x00000088) +#define HW_RTC_PERSISTENT2_TOG (0x0000008c) + +#define BP_RTC_PERSISTENT2_GENERAL 0 +#define BM_RTC_PERSISTENT2_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT2_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT3 (0x00000090) +#define HW_RTC_PERSISTENT3_SET (0x00000094) +#define HW_RTC_PERSISTENT3_CLR (0x00000098) +#define HW_RTC_PERSISTENT3_TOG (0x0000009c) + +#define BP_RTC_PERSISTENT3_GENERAL 0 +#define BM_RTC_PERSISTENT3_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT3_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT4 (0x000000a0) +#define HW_RTC_PERSISTENT4_SET (0x000000a4) +#define HW_RTC_PERSISTENT4_CLR (0x000000a8) +#define HW_RTC_PERSISTENT4_TOG (0x000000ac) + +#define BP_RTC_PERSISTENT4_GENERAL 0 +#define BM_RTC_PERSISTENT4_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT4_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT5 (0x000000b0) +#define HW_RTC_PERSISTENT5_SET (0x000000b4) +#define HW_RTC_PERSISTENT5_CLR (0x000000b8) +#define HW_RTC_PERSISTENT5_TOG (0x000000bc) + +#define BP_RTC_PERSISTENT5_GENERAL 0 +#define BM_RTC_PERSISTENT5_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT5_GENERAL(v) (v) + +#define HW_RTC_DEBUG (0x000000c0) +#define HW_RTC_DEBUG_SET (0x000000c4) +#define HW_RTC_DEBUG_CLR (0x000000c8) +#define HW_RTC_DEBUG_TOG (0x000000cc) + +#define BP_RTC_DEBUG_RSVD0 2 +#define BM_RTC_DEBUG_RSVD0 0xFFFFFFFC +#define BF_RTC_DEBUG_RSVD0(v) \ + (((v) << 2) & BM_RTC_DEBUG_RSVD0) +#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x00000002 +#define BM_RTC_DEBUG_WATCHDOG_RESET 0x00000001 + +#define HW_RTC_VERSION (0x000000d0) + +#define BP_RTC_VERSION_MAJOR 24 +#define BM_RTC_VERSION_MAJOR 0xFF000000 +#define BF_RTC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_RTC_VERSION_MAJOR) +#define BP_RTC_VERSION_MINOR 16 +#define BM_RTC_VERSION_MINOR 0x00FF0000 +#define BF_RTC_VERSION_MINOR(v) \ + (((v) << 16) & BM_RTC_VERSION_MINOR) +#define BP_RTC_VERSION_STEP 0 +#define BM_RTC_VERSION_STEP 0x0000FFFF +#define BF_RTC_VERSION_STEP(v) \ + (((v) << 0) & BM_RTC_VERSION_STEP) +#endif /* __ARCH_ARM___RTC_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-ssp.h b/arch/arm/mach-mx28/include/mach/regs-ssp.h new file mode 100644 index 000000000000..1d4793b25a3b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-ssp.h @@ -0,0 +1,474 @@ +/* + * Freescale SSP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 4.0 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___SSP_H +#define __ARCH_ARM___SSP_H + +#ifndef BF +#define BF(value, field) (((value) << BP_##field) & BM_##field) +#endif + +#define HW_SSP_CTRL0 (0x00000000) +#define HW_SSP_CTRL0_SET (0x00000004) +#define HW_SSP_CTRL0_CLR (0x00000008) +#define HW_SSP_CTRL0_TOG (0x0000000c) + +#define BM_SSP_CTRL0_SFTRST 0x80000000 +#define BM_SSP_CTRL0_CLKGATE 0x40000000 +#define BM_SSP_CTRL0_RUN 0x20000000 +#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 +#define BM_SSP_CTRL0_LOCK_CS 0x08000000 +#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 +#define BM_SSP_CTRL0_READ 0x02000000 +#define BM_SSP_CTRL0_DATA_XFER 0x01000000 +#define BP_SSP_CTRL0_BUS_WIDTH 22 +#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 +#define BF_SSP_CTRL0_BUS_WIDTH(v) \ + (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH) +#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 +#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 +#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 +#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 +#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 +#define BM_SSP_CTRL0_LONG_RESP 0x00080000 +#define BM_SSP_CTRL0_CHECK_RESP 0x00040000 +#define BM_SSP_CTRL0_GET_RESP 0x00020000 +#define BM_SSP_CTRL0_ENABLE 0x00010000 +#define BP_SSP_CTRL0_RSVD0 0 +#define BM_SSP_CTRL0_RSVD0 0x0000FFFF +#define BF_SSP_CTRL0_RSVD0(v) \ + (((v) << 0) & BM_SSP_CTRL0_RSVD0) + +#define HW_SSP_CMD0 (0x00000010) +#define HW_SSP_CMD0_SET (0x00000014) +#define HW_SSP_CMD0_CLR (0x00000018) +#define HW_SSP_CMD0_TOG (0x0000001c) + +#define BP_SSP_CMD0_RSVD0 27 +#define BM_SSP_CMD0_RSVD0 0xF8000000 +#define BF_SSP_CMD0_RSVD0(v) \ + (((v) << 27) & BM_SSP_CMD0_RSVD0) +#define BM_SSP_CMD0_SOFT_TERMINATE 0x04000000 +#define BM_SSP_CMD0_DBL_DATA_RATE_EN 0x02000000 +#define BM_SSP_CMD0_PRIM_BOOT_OP_EN 0x01000000 +#define BM_SSP_CMD0_BOOT_ACK_EN 0x00800000 +#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000 +#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000 +#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 +#define BP_SSP_CMD0_RSVD1 8 +#define BM_SSP_CMD0_RSVD1 0x000FFF00 +#define BF_SSP_CMD0_RSVD1(v) \ + (((v) << 8) & BM_SSP_CMD0_RSVD1) +#define BP_SSP_CMD0_CMD 0 +#define BM_SSP_CMD0_CMD 0x000000FF +#define BF_SSP_CMD0_CMD(v) \ + (((v) << 0) & BM_SSP_CMD0_CMD) +#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01 +#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05 +#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06 +#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08 +#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B +#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E +#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 +#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 +#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 +#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 +#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 +#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 +#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05 +#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__SD_ERASE 0x26 +#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 +#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 +#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 + +#define HW_SSP_CMD1 (0x00000020) + +#define BP_SSP_CMD1_CMD_ARG 0 +#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF +#define BF_SSP_CMD1_CMD_ARG(v) (v) + +#define HW_SSP_XFER_SIZE (0x00000030) + +#define BP_SSP_XFER_SIZE_XFER_COUNT 0 +#define BM_SSP_XFER_SIZE_XFER_COUNT 0xFFFFFFFF +#define BF_SSP_XFER_SIZE_XFER_COUNT(v) (v) + +#define HW_SSP_BLOCK_SIZE (0x00000040) + +#define BP_SSP_BLOCK_SIZE_RSVD0 28 +#define BM_SSP_BLOCK_SIZE_RSVD0 0xF0000000 +#define BF_SSP_BLOCK_SIZE_RSVD0(v) \ + (((v) << 28) & BM_SSP_BLOCK_SIZE_RSVD0) +#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4 +#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT 0x0FFFFFF0 +#define BF_SSP_BLOCK_SIZE_BLOCK_COUNT(v) \ + (((v) << 4) & BM_SSP_BLOCK_SIZE_BLOCK_COUNT) +#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0 +#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0x0000000F +#define BF_SSP_BLOCK_SIZE_BLOCK_SIZE(v) \ + (((v) << 0) & BM_SSP_BLOCK_SIZE_BLOCK_SIZE) + +#define HW_SSP_COMPREF (0x00000050) + +#define BP_SSP_COMPREF_REFERENCE 0 +#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF +#define BF_SSP_COMPREF_REFERENCE(v) (v) + +#define HW_SSP_COMPMASK (0x00000060) + +#define BP_SSP_COMPMASK_MASK 0 +#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF +#define BF_SSP_COMPMASK_MASK(v) (v) + +#define HW_SSP_TIMING (0x00000070) + +#define BP_SSP_TIMING_TIMEOUT 16 +#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 +#define BF_SSP_TIMING_TIMEOUT(v) \ + (((v) << 16) & BM_SSP_TIMING_TIMEOUT) +#define BP_SSP_TIMING_CLOCK_DIVIDE 8 +#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) +#define BP_SSP_TIMING_CLOCK_RATE 0 +#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) + +#define HW_SSP_CTRL1 (0x00000080) +#define HW_SSP_CTRL1_SET (0x00000084) +#define HW_SSP_CTRL1_CLR (0x00000088) +#define HW_SSP_CTRL1_TOG (0x0000008c) + +#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 +#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000 +#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000 +#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800 +#define BM_SSP_CTRL1_PHASE 0x00000400 +#define BM_SSP_CTRL1_POLARITY 0x00000200 +#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100 +#define BP_SSP_CTRL1_WORD_LENGTH 4 +#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF +#define BP_SSP_CTRL1_SSP_MODE 0 +#define BM_SSP_CTRL1_SSP_MODE 0x0000000F +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 + +#define HW_SSP_DATA (0x00000090) + +#define BP_SSP_DATA_DATA 0 +#define BM_SSP_DATA_DATA 0xFFFFFFFF +#define BF_SSP_DATA_DATA(v) (v) + +#define HW_SSP_SDRESP0 (0x000000a0) + +#define BP_SSP_SDRESP0_RESP0 0 +#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF +#define BF_SSP_SDRESP0_RESP0(v) (v) + +#define HW_SSP_SDRESP1 (0x000000b0) + +#define BP_SSP_SDRESP1_RESP1 0 +#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF +#define BF_SSP_SDRESP1_RESP1(v) (v) + +#define HW_SSP_SDRESP2 (0x000000c0) + +#define BP_SSP_SDRESP2_RESP2 0 +#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF +#define BF_SSP_SDRESP2_RESP2(v) (v) + +#define HW_SSP_SDRESP3 (0x000000d0) + +#define BP_SSP_SDRESP3_RESP3 0 +#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF +#define BF_SSP_SDRESP3_RESP3(v) (v) + +#define HW_SSP_DDR_CTRL (0x000000e0) + +#define BP_SSP_DDR_CTRL_DMA_BURST_TYPE 30 +#define BM_SSP_DDR_CTRL_DMA_BURST_TYPE 0xC0000000 +#define BF_SSP_DDR_CTRL_DMA_BURST_TYPE(v) \ + (((v) << 30) & BM_SSP_DDR_CTRL_DMA_BURST_TYPE) +#define BP_SSP_DDR_CTRL_RSVD0 2 +#define BM_SSP_DDR_CTRL_RSVD0 0x3FFFFFFC +#define BF_SSP_DDR_CTRL_RSVD0(v) \ + (((v) << 2) & BM_SSP_DDR_CTRL_RSVD0) +#define BM_SSP_DDR_CTRL_NIBBLE_POS 0x00000002 +#define BM_SSP_DDR_CTRL_TXCLK_DELAY_TYPE 0x00000001 + +#define HW_SSP_DLL_CTRL (0x000000f0) + +#define BP_SSP_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_SSP_DLL_CTRL_REF_UPDATE_INT 0xF0000000 +#define BF_SSP_DLL_CTRL_REF_UPDATE_INT(v) \ + (((v) << 28) & BM_SSP_DLL_CTRL_REF_UPDATE_INT) +#define BP_SSP_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_SSP_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 +#define BF_SSP_DLL_CTRL_SLV_UPDATE_INT(v) \ + (((v) << 20) & BM_SSP_DLL_CTRL_SLV_UPDATE_INT) +#define BP_SSP_DLL_CTRL_RSVD1 16 +#define BM_SSP_DLL_CTRL_RSVD1 0x000F0000 +#define BF_SSP_DLL_CTRL_RSVD1(v) \ + (((v) << 16) & BM_SSP_DLL_CTRL_RSVD1) +#define BP_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL 0x0000FC00 +#define BF_SSP_DLL_CTRL_SLV_OVERRIDE_VAL(v) \ + (((v) << 10) & BM_SSP_DLL_CTRL_SLV_OVERRIDE_VAL) +#define BM_SSP_DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define BM_SSP_DLL_CTRL_RSVD0 0x00000100 +#define BM_SSP_DLL_CTRL_GATE_UPDATE 0x00000080 +#define BP_SSP_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_SSP_DLL_CTRL_SLV_DLY_TARGET 0x00000078 +#define BF_SSP_DLL_CTRL_SLV_DLY_TARGET(v) \ + (((v) << 3) & BM_SSP_DLL_CTRL_SLV_DLY_TARGET) +#define BM_SSP_DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define BM_SSP_DLL_CTRL_RESET 0x00000002 +#define BM_SSP_DLL_CTRL_ENABLE 0x00000001 + +#define HW_SSP_STATUS (0x00000100) + +#define BM_SSP_STATUS_PRESENT 0x80000000 +#define BM_SSP_STATUS_MS_PRESENT 0x40000000 +#define BM_SSP_STATUS_SD_PRESENT 0x20000000 +#define BM_SSP_STATUS_CARD_DETECT 0x10000000 +#define BP_SSP_STATUS_RSVD3 23 +#define BM_SSP_STATUS_RSVD3 0x0F800000 +#define BF_SSP_STATUS_RSVD3(v) \ + (((v) << 23) & BM_SSP_STATUS_RSVD3) +#define BM_SSP_STATUS_DMABURST 0x00400000 +#define BM_SSP_STATUS_DMASENSE 0x00200000 +#define BM_SSP_STATUS_DMATERM 0x00100000 +#define BM_SSP_STATUS_DMAREQ 0x00080000 +#define BM_SSP_STATUS_DMAEND 0x00040000 +#define BM_SSP_STATUS_SDIO_IRQ 0x00020000 +#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 +#define BM_SSP_STATUS_RESP_ERR 0x00008000 +#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 +#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000 +#define BM_SSP_STATUS_TIMEOUT 0x00001000 +#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800 +#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400 +#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200 +#define BM_SSP_STATUS_FIFO_FULL 0x00000100 +#define BP_SSP_STATUS_RSVD1 6 +#define BM_SSP_STATUS_RSVD1 0x000000C0 +#define BF_SSP_STATUS_RSVD1(v) \ + (((v) << 6) & BM_SSP_STATUS_RSVD1) +#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 +#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010 +#define BM_SSP_STATUS_CMD_BUSY 0x00000008 +#define BM_SSP_STATUS_DATA_BUSY 0x00000004 +#define BM_SSP_STATUS_RSVD0 0x00000002 +#define BM_SSP_STATUS_BUSY 0x00000001 + +#define HW_SSP_DLL_STS (0x00000110) + +#define BP_SSP_DLL_STS_RSVD0 14 +#define BM_SSP_DLL_STS_RSVD0 0xFFFFC000 +#define BF_SSP_DLL_STS_RSVD0(v) \ + (((v) << 14) & BM_SSP_DLL_STS_RSVD0) +#define BP_SSP_DLL_STS_REF_SEL 8 +#define BM_SSP_DLL_STS_REF_SEL 0x00003F00 +#define BF_SSP_DLL_STS_REF_SEL(v) \ + (((v) << 8) & BM_SSP_DLL_STS_REF_SEL) +#define BP_SSP_DLL_STS_SLV_SEL 2 +#define BM_SSP_DLL_STS_SLV_SEL 0x000000FC +#define BF_SSP_DLL_STS_SLV_SEL(v) \ + (((v) << 2) & BM_SSP_DLL_STS_SLV_SEL) +#define BM_SSP_DLL_STS_REF_LOCK 0x00000002 +#define BM_SSP_DLL_STS_SLV_LOCK 0x00000001 + +#define HW_SSP_DEBUG (0x00000120) + +#define BP_SSP_DEBUG_DATACRC_ERR 28 +#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000 +#define BF_SSP_DEBUG_DATACRC_ERR(v) \ + (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR) +#define BM_SSP_DEBUG_DATA_STALL 0x08000000 +#define BP_SSP_DEBUG_DAT_SM 24 +#define BM_SSP_DEBUG_DAT_SM 0x07000000 +#define BF_SSP_DEBUG_DAT_SM(v) \ + (((v) << 24) & BM_SSP_DEBUG_DAT_SM) +#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 +#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 +#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 +#define BP_SSP_DEBUG_MSTK_SM 20 +#define BM_SSP_DEBUG_MSTK_SM 0x00F00000 +#define BF_SSP_DEBUG_MSTK_SM(v) \ + (((v) << 20) & BM_SSP_DEBUG_MSTK_SM) +#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD +#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE +#define BM_SSP_DEBUG_CMD_OE 0x00080000 +#define BP_SSP_DEBUG_DMA_SM 16 +#define BM_SSP_DEBUG_DMA_SM 0x00070000 +#define BF_SSP_DEBUG_DMA_SM(v) \ + (((v) << 16) & BM_SSP_DEBUG_DMA_SM) +#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 +#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 +#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 +#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 +#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 +#define BP_SSP_DEBUG_MMC_SM 12 +#define BM_SSP_DEBUG_MMC_SM 0x0000F000 +#define BF_SSP_DEBUG_MMC_SM(v) \ + (((v) << 12) & BM_SSP_DEBUG_MMC_SM) +#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 +#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 +#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 +#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 +#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 +#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 +#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 +#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 +#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 +#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 +#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA +#define BP_SSP_DEBUG_CMD_SM 10 +#define BM_SSP_DEBUG_CMD_SM 0x00000C00 +#define BF_SSP_DEBUG_CMD_SM(v) \ + (((v) << 10) & BM_SSP_DEBUG_CMD_SM) +#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 +#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 +#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 +#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 +#define BM_SSP_DEBUG_SSP_CMD 0x00000200 +#define BM_SSP_DEBUG_SSP_RESP 0x00000100 +#define BP_SSP_DEBUG_SSP_RXD 0 +#define BM_SSP_DEBUG_SSP_RXD 0x000000FF +#define BF_SSP_DEBUG_SSP_RXD(v) \ + (((v) << 0) & BM_SSP_DEBUG_SSP_RXD) + +#define HW_SSP_VERSION (0x00000130) + +#define BP_SSP_VERSION_MAJOR 24 +#define BM_SSP_VERSION_MAJOR 0xFF000000 +#define BF_SSP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SSP_VERSION_MAJOR) +#define BP_SSP_VERSION_MINOR 16 +#define BM_SSP_VERSION_MINOR 0x00FF0000 +#define BF_SSP_VERSION_MINOR(v) \ + (((v) << 16) & BM_SSP_VERSION_MINOR) +#define BP_SSP_VERSION_STEP 0 +#define BM_SSP_VERSION_STEP 0x0000FFFF +#define BF_SSP_VERSION_STEP(v) \ + (((v) << 0) & BM_SSP_VERSION_STEP) +#endif /* __ARCH_ARM___SSP_H */ diff --git a/arch/arm/mach-mx28/include/mach/regs-timrot.h b/arch/arm/mach-mx28/include/mach/regs-timrot.h new file mode 100644 index 000000000000..125b835e19ec --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regs-timrot.h @@ -0,0 +1,293 @@ +/* + * Freescale TIMROT Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.40 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H + + +#define HW_TIMROT_ROTCTRL (0x00000000) +#define HW_TIMROT_ROTCTRL_SET (0x00000004) +#define HW_TIMROT_ROTCTRL_CLR (0x00000008) +#define HW_TIMROT_ROTCTRL_TOG (0x0000000c) + +#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BP_TIMROT_ROTCTRL_RSRVD3 13 +#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000 +#define BF_TIMROT_ROTCTRL_RSRVD3(v) \ + (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x000000F0 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0xA +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x0000000F +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM5 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM6 0x7 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM7 0x8 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x9 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0xA + +#define HW_TIMROT_ROTCOUNT (0x00000010) + +#define BP_TIMROT_ROTCOUNT_RSRVD1 16 +#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000 +#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \ + (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) + +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x40) +#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x40) +#define BP_TIMROT_TIMCTRLn_RSRVD3 16 +#define BM_TIMROT_TIMCTRLn_RSRVD3 0xFFFF0000 +#define BF_TIMROT_TIMCTRLn_RSRVD3(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD3) +#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRLn_RSRVD2 12 +#define BM_TIMROT_TIMCTRLn_RSRVD2 0x00003000 +#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRLn_RSRVD2) +#define BM_TIMROT_TIMCTRLn_MATCH_MODE 0x00000800 +#define BP_TIMROT_TIMCTRLn_RSRVD1 9 +#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00000600 +#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \ + (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xF + +/* + * multi-register-define name HW_TIMROT_RUNNING_COUNTn + * base 0x00000030 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_RUNNING_COUNTn(n) (0x00000030 + (n) * 0x40) +#define BP_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNTn_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNTn_RUNNING_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_FIXED_COUNTn + * base 0x00000040 + * count 3 + * offset 0x40 + */ +#define HW_TIMROT_FIXED_COUNTn(n) (0x00000040 + (n) * 0x40) +#define BP_TIMROT_FIXED_COUNTn_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNTn_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNTn_FIXED_COUNT(v) (v) + +/* + * multi-register-define name HW_TIMROT_MATCH_COUNTn + * base 0x00000050 + * count 4 + * offset 0x40 + */ +#define HW_TIMROT_MATCH_COUNTn(n) (0x00000050 + (n) * 0x40) +#define BP_TIMROT_MATCH_COUNTn_MATCH_COUNT 0 +#define BM_TIMROT_MATCH_COUNTn_MATCH_COUNT 0xFFFFFFFF +#define BF_TIMROT_MATCH_COUNTn_MATCH_COUNT(v) (v) + +#define HW_TIMROT_TIMCTRL3 (0x000000e0) +#define HW_TIMROT_TIMCTRL3_SET (0x000000e4) +#define HW_TIMROT_TIMCTRL3_CLR (0x000000e8) +#define HW_TIMROT_TIMCTRL3_TOG (0x000000ec) + +#define BP_TIMROT_TIMCTRL3_RSRVD2 20 +#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000 +#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \ + (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xF +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRL3_RSRVD1 12 +#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003000 +#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \ + (((v) << 12) & BM_TIMROT_TIMCTRL3_RSRVD1) +#define BM_TIMROT_TIMCTRL3_MATCH_MODE 0x00000800 +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM5 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM6 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM7 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0xC +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xD +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xE +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xF + +#define HW_TIMROT_RUNNING_COUNT3 (0x000000f0) + +#define BP_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0 +#define BM_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT 0xFFFFFFFF +#define BF_TIMROT_RUNNING_COUNT3_LOW_RUNNING_COUNT(v) (v) + +#define HW_TIMROT_FIXED_COUNT3 (0x00000100) + +#define BP_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT 0xFFFFFFFF +#define BF_TIMROT_FIXED_COUNT3_HIGH_FIXED_COUNT(v) (v) + +#define HW_TIMROT_VERSION (0x00000120) + +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/arch/arm/mach-mx28/include/mach/regulator.h b/arch/arm/mach-mx28/include/mach/regulator.h new file mode 100644 index 000000000000..1b073586268b --- /dev/null +++ b/arch/arm/mach-mx28/include/mach/regulator.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __PLAT_REGULATOR_H_ +#define __PLAT_REGULATOR_H_ + +#define MXS_REG5V_NOT_USB 0 +#define MXS_REG5V_IS_USB 1 +#define MXS_VDDD 0 +#define MXS_VDDA 1 +#define MXS_VDDIO 2 +#define MXS_VDDDBO 3 +#define MXS_OVERALL_CUR 4 + +#endif diff --git a/arch/arm/mach-mx28/mx28_pins.h b/arch/arm/mach-mx28/mx28_pins.h new file mode 100644 index 000000000000..a87ab9d6fc81 --- /dev/null +++ b/arch/arm/mach-mx28/mx28_pins.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_PINS_H +#define __ASM_ARCH_PINS_H + +#include + +/* + * Define MX28 pins, the pin name corresponds to MX28 hardware + * interface this pin belongs to. + */ + +/* Bank 0 */ +#define PINID_GPMI_D00 MXS_PIN_ENCODE(0, 0) +#define PINID_GPMI_D01 MXS_PIN_ENCODE(0, 1) +#define PINID_GPMI_D02 MXS_PIN_ENCODE(0, 2) +#define PINID_GPMI_D03 MXS_PIN_ENCODE(0, 3) +#define PINID_GPMI_D04 MXS_PIN_ENCODE(0, 4) +#define PINID_GPMI_D05 MXS_PIN_ENCODE(0, 5) +#define PINID_GPMI_D06 MXS_PIN_ENCODE(0, 6) +#define PINID_GPMI_D07 MXS_PIN_ENCODE(0, 7) +#define PINID_GPMI_CE0N MXS_PIN_ENCODE(0, 16) +#define PINID_GPMI_CE1N MXS_PIN_ENCODE(0, 17) +#define PINID_GPMI_CE2N MXS_PIN_ENCODE(0, 18) +#define PINID_GPMI_CE3N MXS_PIN_ENCODE(0, 19) +#define PINID_GPMI_RDY0 MXS_PIN_ENCODE(0, 20) +#define PINID_GPMI_RDY1 MXS_PIN_ENCODE(0, 21) +#define PINID_GPMI_RDY2 MXS_PIN_ENCODE(0, 22) +#define PINID_GPMI_RDY3 MXS_PIN_ENCODE(0, 23) +#define PINID_GPMI_RDN MXS_PIN_ENCODE(0, 24) +#define PINID_GPMI_WRN MXS_PIN_ENCODE(0, 25) +#define PINID_GPMI_ALE MXS_PIN_ENCODE(0, 26) +#define PINID_GPMI_CLE MXS_PIN_ENCODE(0, 27) +#define PINID_GPMI_RESETN MXS_PIN_ENCODE(0, 28) + +/* Bank 1 */ +#define PINID_LCD_D00 MXS_PIN_ENCODE(1, 0) +#define PINID_LCD_D01 MXS_PIN_ENCODE(1, 1) +#define PINID_LCD_D02 MXS_PIN_ENCODE(1, 2) +#define PINID_LCD_D03 MXS_PIN_ENCODE(1, 3) +#define PINID_LCD_D04 MXS_PIN_ENCODE(1, 4) +#define PINID_LCD_D05 MXS_PIN_ENCODE(1, 5) +#define PINID_LCD_D06 MXS_PIN_ENCODE(1, 6) +#define PINID_LCD_D07 MXS_PIN_ENCODE(1, 7) +#define PINID_LCD_D08 MXS_PIN_ENCODE(1, 8) +#define PINID_LCD_D09 MXS_PIN_ENCODE(1, 9) +#define PINID_LCD_D10 MXS_PIN_ENCODE(1, 10) +#define PINID_LCD_D11 MXS_PIN_ENCODE(1, 11) +#define PINID_LCD_D12 MXS_PIN_ENCODE(1, 12) +#define PINID_LCD_D13 MXS_PIN_ENCODE(1, 13) +#define PINID_LCD_D14 MXS_PIN_ENCODE(1, 14) +#define PINID_LCD_D15 MXS_PIN_ENCODE(1, 15) +#define PINID_LCD_D16 MXS_PIN_ENCODE(1, 16) +#define PINID_LCD_D17 MXS_PIN_ENCODE(1, 17) +#define PINID_LCD_D18 MXS_PIN_ENCODE(1, 18) +#define PINID_LCD_D19 MXS_PIN_ENCODE(1, 19) +#define PINID_LCD_D20 MXS_PIN_ENCODE(1, 20) +#define PINID_LCD_D21 MXS_PIN_ENCODE(1, 21) +#define PINID_LCD_D22 MXS_PIN_ENCODE(1, 22) +#define PINID_LCD_D23 MXS_PIN_ENCODE(1, 23) +#define PINID_LCD_RD_E MXS_PIN_ENCODE(1, 24) +#define PINID_LCD_WR_RWN MXS_PIN_ENCODE(1, 25) +#define PINID_LCD_RS MXS_PIN_ENCODE(1, 26) +#define PINID_LCD_CS MXS_PIN_ENCODE(1, 27) +#define PINID_LCD_VSYNC MXS_PIN_ENCODE(1, 28) +#define PINID_LCD_HSYNC MXS_PIN_ENCODE(1, 29) +#define PINID_LCD_DOTCK MXS_PIN_ENCODE(1, 30) +#define PINID_LCD_ENABLE MXS_PIN_ENCODE(1, 31) + +/* Bank 2 */ +#define PINID_SSP0_DATA0 MXS_PIN_ENCODE(2, 0) +#define PINID_SSP0_DATA1 MXS_PIN_ENCODE(2, 1) +#define PINID_SSP0_DATA2 MXS_PIN_ENCODE(2, 2) +#define PINID_SSP0_DATA3 MXS_PIN_ENCODE(2, 3) +#define PINID_SSP0_DATA4 MXS_PIN_ENCODE(2, 4) +#define PINID_SSP0_DATA5 MXS_PIN_ENCODE(2, 5) +#define PINID_SSP0_DATA6 MXS_PIN_ENCODE(2, 6) +#define PINID_SSP0_DATA7 MXS_PIN_ENCODE(2, 7) +#define PINID_SSP0_CMD MXS_PIN_ENCODE(2, 8) +#define PINID_SSP0_DETECT MXS_PIN_ENCODE(2, 9) +#define PINID_SSP0_SCK MXS_PIN_ENCODE(2, 10) +#define PINID_SSP1_SCK MXS_PIN_ENCODE(2, 12) +#define PINID_SSP1_CMD MXS_PIN_ENCODE(2, 13) +#define PINID_SSP1_DATA0 MXS_PIN_ENCODE(2, 14) +#define PINID_SSP1_DATA3 MXS_PIN_ENCODE(2, 15) +#define PINID_SSP2_SCK MXS_PIN_ENCODE(2, 16) +#define PINID_SSP2_MOSI MXS_PIN_ENCODE(2, 17) +#define PINID_SSP2_MISO MXS_PIN_ENCODE(2, 18) +#define PINID_SSP2_SS0 MXS_PIN_ENCODE(2, 19) +#define PINID_SSP2_SS1 MXS_PIN_ENCODE(2, 20) +#define PINID_SSP2_SS2 MXS_PIN_ENCODE(2, 21) +#define PINID_SSP3_SCK MXS_PIN_ENCODE(2, 24) +#define PINID_SSP3_MOSI MXS_PIN_ENCODE(2, 25) +#define PINID_SSP3_MISO MXS_PIN_ENCODE(2, 26) +#define PINID_SSP3_SS0 MXS_PIN_ENCODE(2, 27) + +/* Bank 3 */ +#define PINID_AUART0_RX MXS_PIN_ENCODE(3, 0) +#define PINID_AUART0_TX MXS_PIN_ENCODE(3, 1) +#define PINID_AUART0_CTS MXS_PIN_ENCODE(3, 2) +#define PINID_AUART0_RTS MXS_PIN_ENCODE(3, 3) +#define PINID_AUART1_RX MXS_PIN_ENCODE(3, 4) +#define PINID_AUART1_TX MXS_PIN_ENCODE(3, 5) +#define PINID_AUART1_CTS MXS_PIN_ENCODE(3, 6) +#define PINID_AUART1_RTS MXS_PIN_ENCODE(3, 7) +#define PINID_AUART2_RX MXS_PIN_ENCODE(3, 8) +#define PINID_AUART2_TX MXS_PIN_ENCODE(3, 9) +#define PINID_AUART2_CTS MXS_PIN_ENCODE(3, 10) +#define PINID_AUART2_RTS MXS_PIN_ENCODE(3, 11) +#define PINID_AUART3_RX MXS_PIN_ENCODE(3, 12) +#define PINID_AUART3_TX MXS_PIN_ENCODE(3, 13) +#define PINID_AUART3_CTS MXS_PIN_ENCODE(3, 14) +#define PINID_AUART3_RTS MXS_PIN_ENCODE(3, 15) +#define PINID_PWM0 MXS_PIN_ENCODE(3, 16) +#define PINID_PWM1 MXS_PIN_ENCODE(3, 17) +#define PINID_PWM2 MXS_PIN_ENCODE(3, 18) +#define PINID_SAIF0_MCLK MXS_PIN_ENCODE(3, 20) +#define PINID_SAIF0_LRCLK MXS_PIN_ENCODE(3, 21) +#define PINID_SAIF0_BITCLK MXS_PIN_ENCODE(3, 22) +#define PINID_SAIF0_SDATA0 MXS_PIN_ENCODE(3, 23) +#define PINID_I2C0_SCL MXS_PIN_ENCODE(3, 24) +#define PINID_I2C0_SDA MXS_PIN_ENCODE(3, 25) +#define PINID_SAIF1_SDATA0 MXS_PIN_ENCODE(3, 26) +#define PINID_SPDIF MXS_PIN_ENCODE(3, 27) +#define PINID_PWM3 MXS_PIN_ENCODE(3, 28) +#define PINID_PWM4 MXS_PIN_ENCODE(3, 29) +#define PINID_LCD_RESET MXS_PIN_ENCODE(3, 30) + +/* Bank 4 */ +#define PINID_ENET0_MDC MXS_PIN_ENCODE(4, 0) +#define PINID_ENET0_MDIO MXS_PIN_ENCODE(4, 1) +#define PINID_ENET0_RX_EN MXS_PIN_ENCODE(4, 2) +#define PINID_ENET0_RXD0 MXS_PIN_ENCODE(4, 3) +#define PINID_ENET0_RXD1 MXS_PIN_ENCODE(4, 4) +#define PINID_ENET0_TX_CLK MXS_PIN_ENCODE(4, 5) +#define PINID_ENET0_TX_EN MXS_PIN_ENCODE(4, 6) +#define PINID_ENET0_TXD0 MXS_PIN_ENCODE(4, 7) +#define PINID_ENET0_TXD1 MXS_PIN_ENCODE(4, 8) +#define PINID_ENET0_RXD2 MXS_PIN_ENCODE(4, 9) +#define PINID_ENET0_RXD3 MXS_PIN_ENCODE(4, 10) +#define PINID_ENET0_TXD2 MXS_PIN_ENCODE(4, 11) +#define PINID_ENET0_TXD3 MXS_PIN_ENCODE(4, 12) +#define PINID_ENET0_RX_CLK MXS_PIN_ENCODE(4, 13) +#define PINID_ENET0_COL MXS_PIN_ENCODE(4, 14) +#define PINID_ENET0_CRS MXS_PIN_ENCODE(4, 15) +#define PINID_ENET_CLK MXS_PIN_ENCODE(4, 16) +#define PINID_JTAG_RTCK MXS_PIN_ENCODE(4, 20) +#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-mx28/mx28evk.c b/arch/arm/mach-mx28/mx28evk.c new file mode 100644 index 000000000000..97ce49c20d9d --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "device.h" +#include "mx28evk.h" + +static struct i2c_board_info __initdata mxs_i2c_device[] = { + { I2C_BOARD_INFO("sgtl5000-i2c", 0xa), .flags = I2C_M_TEN } +}; + +static void __init i2c_device_init(void) +{ + i2c_register_board_info(0, mxs_i2c_device, ARRAY_SIZE(mxs_i2c_device)); +} +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +static struct flash_platform_data mx28_spi_flash_data = { + .name = "m25p80", + .type = "w25x80", +}; +#endif + +static struct spi_board_info spi_board_info[] __initdata = { +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) + { + /* the modalias must be the same as spi device driver name */ + .modalias = "m25p80", /* Name of spi_driver for this device */ + .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, /* Framework bus number */ + .chip_select = 0, /* Framework chip select. */ + .platform_data = &mx28_spi_flash_data, + }, +#endif +}; + +static void spi_device_init(void) +{ + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +} + +static void __init fixup_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mx28_set_input_clk(24000000, 24000000, 32000, 50000000); +} + +#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE) +static struct mxs_pwm_led mx28evk_led_pwm[2] = { + [0] = { + .name = "led-pwm0", + .pwm = 0, + }, + [1] = { + .name = "led-pwm1", + .pwm = 1, + }, +}; + +struct mxs_pwm_leds_plat_data mx28evk_led_data = { + .num = ARRAY_SIZE(mx28evk_led_pwm), + .leds = mx28evk_led_pwm, +}; + +static struct resource mx28evk_led_res = { + .flags = IORESOURCE_MEM, + .start = PWM_PHYS_ADDR, + .end = PWM_PHYS_ADDR + 0x3FFF, +}; + +static void __init mx28evk_init_leds(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-leds", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + + pdev->resource = &mx28evk_led_res; + pdev->num_resources = 1; + pdev->dev.platform_data = &mx28evk_led_data; + mxs_add_device(pdev, 3); +} +#else +static void __init mx28evk_init_leds(void) +{ + ; +} +#endif + +static void __init mx28evk_device_init(void) +{ + /* Add mx28evk special code */ + i2c_device_init(); + spi_device_init(); + mx28evk_init_leds(); +} + +static void __init mx28evk_init_machine(void) +{ + mx28_pinctrl_init(); + /* Init iram allocate */ +#ifdef CONFIG_VECTORS_PHY_ADDR + /* reserve the first page for irq vector table*/ + iram_init(MX28_OCRAM_PHBASE + PAGE_SIZE, MX28_OCRAM_SIZE - PAGE_SIZE); +#else + iram_init(MX28_OCRAM_PHBASE, MX28_OCRAM_SIZE); +#endif + + mx28_gpio_init(); + mx28evk_pins_init(); + mx28_device_init(); + mx28evk_device_init(); + + /* init the system revesion */ + system_rev = 0x28011; +} + +MACHINE_START(MX28EVK, "Freescale MX28EVK board") + .phys_io = 0x80000000, + .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, + .boot_params = 0x40000100, + .fixup = fixup_board, + .map_io = mx28_map_io, + .init_irq = mx28_irq_init, + .init_machine = mx28evk_init_machine, + .timer = &mx28_timer.timer, +MACHINE_END diff --git a/arch/arm/mach-mx28/mx28evk.h b/arch/arm/mach-mx28/mx28evk.h new file mode 100644 index 000000000000..d973c0f7ef19 --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_MACH_MX28EVK_H +#define __ASM_ARM_MACH_MX28EVK_H + +extern void __init mx28evk_pins_init(void); +extern int mx28evk_enet_gpio_init(void); +void mx28evk_enet_io_lowerpower_enter(void); +void mx28evk_enet_io_lowerpower_exit(void); + + +#endif /* __ASM_ARM_MACH_MX28EVK_H */ diff --git a/arch/arm/mach-mx28/mx28evk_pins.c b/arch/arm/mach-mx28/mx28evk_pins.c new file mode 100644 index 000000000000..1990b925f681 --- /dev/null +++ b/arch/arm/mach-mx28/mx28evk_pins.c @@ -0,0 +1,1231 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "mx28_pins.h" + +static struct pin_desc mx28evk_fixed_pins[] = { + { + .name = "DUART.RX", + .id = PINID_PWM0, + .fun = PIN_FUN3, + }, + { + .name = "DUART.TX", + .id = PINID_PWM1, + .fun = PIN_FUN3, + }, +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE + { + .name = "AUART0.RX", + .id = PINID_AUART0_RX, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.TX", + .id = PINID_AUART0_TX, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.CTS", + .id = PINID_AUART0_CTS, + .fun = PIN_FUN1, + }, + { + .name = "AUART0.RTS", + .id = PINID_AUART0_RTS, + .fun = PIN_FUN1, + }, +#endif +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE + { + .name = "AUART3.RX", + .id = PINID_AUART3_RX, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.TX", + .id = PINID_AUART3_TX, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.CTS", + .id = PINID_AUART3_CTS, + .fun = PIN_FUN1, + }, + { + .name = "AUART3.RTS", + .id = PINID_AUART3_RTS, + .fun = PIN_FUN1, + }, +#endif + { + .name = "usb0", + .id = PINID_AUART2_TX, /* Power enable pin*/ + .fun = PIN_GPIO, + .data = 0, + .output = 1, + }, + { + .name = "usb1", + .id = PINID_AUART2_RX, + .fun = PIN_GPIO, + .data = 1, + .output = 1, + }, + +#if defined(CONFIG_USB_OTG) + { + .name = "usb0_id", + .id = PINID_AUART1_RTS, + .fun = PIN_FUN2, + .data = 1, + .pull = 1, + .pullup = 1, + }, +#endif + +#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE) + { + .name = "CAN1_TX", + .id = PINID_GPMI_CE2N, + .fun = PIN_FUN2, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "CAN1_RX", + .id = PINID_GPMI_CE3N, + .fun = PIN_FUN2, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "CAN0_TX", + .id = PINID_GPMI_RDY2, + .fun = PIN_FUN2, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "CAN0_RX", + .id = PINID_GPMI_RDY3, + .fun = PIN_FUN2, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "CAN_PWDN", + .id = PINID_SSP1_CMD, + .fun = PIN_GPIO, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + .data = 0, + .output = 1, + }, + +#endif + +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) + { + .name = "I2C0_SCL", + .id = PINID_I2C0_SCL, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "I2C0_SDA", + .id = PINID_I2C0_SDA, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) + { + .name = "LCD_D00", + .id = PINID_LCD_D00, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D01", + .id = PINID_LCD_D01, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D02", + .id = PINID_LCD_D02, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D03", + .id = PINID_LCD_D03, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D04", + .id = PINID_LCD_D04, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D05", + .id = PINID_LCD_D05, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D06", + .id = PINID_LCD_D06, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D07", + .id = PINID_LCD_D07, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D08", + .id = PINID_LCD_D08, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D09", + .id = PINID_LCD_D09, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D10", + .id = PINID_LCD_D10, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D11", + .id = PINID_LCD_D11, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D12", + .id = PINID_LCD_D12, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D13", + .id = PINID_LCD_D13, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D14", + .id = PINID_LCD_D14, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D15", + .id = PINID_LCD_D15, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D16", + .id = PINID_LCD_D16, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D17", + .id = PINID_LCD_D17, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D18", + .id = PINID_LCD_D18, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D19", + .id = PINID_LCD_D19, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D20", + .id = PINID_LCD_D20, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D21", + .id = PINID_LCD_D21, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D22", + .id = PINID_LCD_D22, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_D23", + .id = PINID_LCD_D23, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_RESET", + .id = PINID_LCD_RESET, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_VSYNC", + .id = PINID_LCD_RD_E, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_HSYNC", + .id = PINID_LCD_WR_RWN, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_ENABLE", + .id = PINID_LCD_CS, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_DOTCLK", + .id = PINID_LCD_RS, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "LCD_BACKLIGHT", + .id = PINID_PWM2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +#endif +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) + /* Configurations of SSP0 SD/MMC port pins */ + { + .name = "SSP0_DATA0", + .id = PINID_SSP0_DATA0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA1", + .id = PINID_SSP0_DATA1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA2", + .id = PINID_SSP0_DATA2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA3", + .id = PINID_SSP0_DATA3, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA4", + .id = PINID_SSP0_DATA4, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA5", + .id = PINID_SSP0_DATA5, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA6", + .id = PINID_SSP0_DATA6, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DATA7", + .id = PINID_SSP0_DATA7, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_CMD", + .id = PINID_SSP0_CMD, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP0_DETECT", + .id = PINID_SSP0_DETECT, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "SSP0_SCK", + .id = PINID_SSP0_SCK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 2, + .pull = 0, + }, +#endif +#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE) + { + .name = "LEDS_PWM0", + .id = PINID_AUART1_RX, + .fun = PIN_FUN3, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "LEDS_PWM1", + .id = PINID_AUART1_TX, + .fun = PIN_FUN3, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE) + /* Configurations of SAIF0 port pins */ + { + .name = "SAIF0_MCLK", + .id = PINID_SAIF0_MCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_LRCLK", + .id = PINID_SAIF0_LRCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_BITCLK", + .id = PINID_SAIF0_BITCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_SDATA0", + .id = PINID_SAIF0_SDATA0, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF1_SDATA0", + .id = PINID_SAIF1_SDATA0, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) + { + .name = "SPDIF", + .id = PINID_SPDIF, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +}; + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) +static struct pin_desc mx28evk_eth_pins[] = { + { + .name = "ENET0_MDC", + .id = PINID_ENET0_MDC, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_MDIO", + .id = PINID_ENET0_MDIO, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RX_EN", + .id = PINID_ENET0_RX_EN, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RXD0", + .id = PINID_ENET0_RXD0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_RXD1", + .id = PINID_ENET0_RXD1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TX_EN", + .id = PINID_ENET0_TX_EN, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TXD0", + .id = PINID_ENET0_TXD0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET0_TXD1", + .id = PINID_ENET0_TXD1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_RX_EN", + .id = PINID_ENET0_CRS, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_RXD0", + .id = PINID_ENET0_RXD2, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_RXD1", + .id = PINID_ENET0_RXD3, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_TX_EN", + .id = PINID_ENET0_COL, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_TXD0", + .id = PINID_ENET0_TXD2, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET1_TXD1", + .id = PINID_ENET0_TXD3, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "ENET_CLK", + .id = PINID_ENET_CLK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, + }, +}; +#endif + +static int __initdata enable_ssp1 = { 0 }; +static int __init ssp1_setup(char *__unused) +{ + enable_ssp1 = 1; + return 1; +} + +__setup("ssp1", ssp1_setup); + +static struct pin_desc mx28evk_ssp1_pins[] = { + { + .name = "SSP1_DATA0", + .id = PINID_GPMI_D00, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA1", + .id = PINID_GPMI_D01, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA2", + .id = PINID_GPMI_D02, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA3", + .id = PINID_GPMI_D03, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA4", + .id = PINID_GPMI_D04, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA5", + .id = PINID_GPMI_D05, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA6", + .id = PINID_GPMI_D06, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA7", + .id = PINID_GPMI_D07, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_CMD", + .id = PINID_GPMI_RDY1, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DETECT", + .id = PINID_GPMI_RDY0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "SSP1_SCK", + .id = PINID_GPMI_WRN, + .fun = PIN_FUN2, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 2, + .pull = 0, + }, +}; + + +int enable_gpmi = { 0 }; +static int __init gpmi_setup(char *__unused) +{ + enable_gpmi = 1; + return 1; +} + +__setup("gpmi", gpmi_setup); + +static struct pin_desc mx28evk_gpmi_pins[] = { + { + .name = "GPMI D0", + .id = PINID_GPMI_D00, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D1", + .id = PINID_GPMI_D01, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D2", + .id = PINID_GPMI_D02, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D3", + .id = PINID_GPMI_D03, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D4", + .id = PINID_GPMI_D04, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D5", + .id = PINID_GPMI_D05, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D6", + .id = PINID_GPMI_D06, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D7", + .id = PINID_GPMI_D07, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CE0-", + .id = PINID_GPMI_CE0N, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CE1-", + .id = PINID_GPMI_CE1N, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RDY0", + .id = PINID_GPMI_RDY0, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RDY1", + .id = PINID_GPMI_RDY1, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RD-", + .id = PINID_GPMI_RDN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI WR-", + .id = PINID_GPMI_WRN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI ALE", + .id = PINID_GPMI_ALE, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CLE", + .id = PINID_GPMI_CLE, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RST-", + .id = PINID_GPMI_RESETN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, +}; + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct pin_desc mx28evk_spi_pins[] = { + { + .name = "SSP2 MOSI", + .id = PINID_SSP2_MOSI, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP2 MISO", + .id = PINID_SSP2_MISO, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP2 SCK", + .id = PINID_SSP2_SCK, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP2 SS0", + .id = PINID_SSP2_SS0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +}; +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) +int mx28evk_enet_gpio_init(void) +{ + /* pwr */ + gpio_request(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), "ENET_PWR"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0); + + /* reset phy */ + gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), "PHY_RESET"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0); + + /* + * Before timer bug fix(set wrong match value of timer), + * mdelay(10) delay 50ms actually. + * So change delay to 50ms after timer issue fix. + */ + mdelay(50); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1); + + return 0; +} + +void mx28evk_enet_io_lowerpower_enter(void) +{ + int i; + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 1); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0); + gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK), "ETH_INT"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK), 0); + + for (i = 0; i < ARRAY_SIZE(mx28evk_eth_pins); i++) { + mxs_release_pin(mx28evk_eth_pins[i].id, + mx28evk_eth_pins[i].name); + gpio_request(MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id), + mx28evk_eth_pins[i].name); + gpio_direction_output( + MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id), 0); + } + +} + +void mx28evk_enet_io_lowerpower_exit(void) +{ + int i; + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1); + gpio_free(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK)); + for (i = 0; i < ARRAY_SIZE(mx28evk_eth_pins); i++) { + gpio_free(MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id)); + mxs_request_pin(mx28evk_eth_pins[i].id, + mx28evk_eth_pins[i].fun, + mx28evk_eth_pins[i].name); + } +} + +#else +int mx28evk_enet_gpio_init(void) +{ + return 0; +} +void mx28evk_enet_io_lowerpower_enter(void) +{} +void mx28evk_enet_io_lowerpower_exit(void) +{} +#endif + +void __init mx28evk_init_pin_group(struct pin_desc *pins, unsigned count) +{ + int i; + struct pin_desc *pin; + for (i = 0; i < count; i++) { + pin = pins + i; + if (pin->fun == PIN_GPIO) + gpio_request(MXS_PIN_TO_GPIO(pin->id), pin->name); + else + mxs_request_pin(pin->id, pin->fun, pin->name); + if (pin->drive) { + mxs_set_strength(pin->id, pin->strength, pin->name); + mxs_set_voltage(pin->id, pin->voltage, pin->name); + } + if (pin->pull) + mxs_set_pullup(pin->id, pin->pullup, pin->name); + if (pin->fun == PIN_GPIO) { + if (pin->output) + gpio_direction_output(MXS_PIN_TO_GPIO(pin->id), + pin->data); + else + gpio_direction_input(MXS_PIN_TO_GPIO(pin->id)); + } + } +} + +void __init mx28evk_pins_init(void) +{ + + mx28evk_init_pin_group(mx28evk_fixed_pins, + ARRAY_SIZE(mx28evk_fixed_pins)); + + if (enable_ssp1) { + pr_info("Initializing SSP1 pins\n"); + mx28evk_init_pin_group(mx28evk_ssp1_pins, + ARRAY_SIZE(mx28evk_ssp1_pins)); + } else if (enable_gpmi) { + pr_info("Initializing GPMI pins\n"); + mx28evk_init_pin_group(mx28evk_gpmi_pins, + ARRAY_SIZE(mx28evk_gpmi_pins)); + } + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) + mx28evk_init_pin_group(mx28evk_spi_pins, + ARRAY_SIZE(mx28evk_spi_pins)); +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) + mx28evk_init_pin_group(mx28evk_eth_pins, + ARRAY_SIZE(mx28evk_eth_pins)); +#endif +} diff --git a/arch/arm/mach-mx28/pinctrl.c b/arch/arm/mach-mx28/pinctrl.c new file mode 100644 index 000000000000..296f4036395d --- /dev/null +++ b/arch/arm/mach-mx28/pinctrl.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "regs-pinctrl.h" + +#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR) + +static int +mx28_pin2id(struct pinctrl_chip *chip, unsigned int pin, unsigned int *id) +{ + int bank; + bank = MXS_PIN_TO_BANK(pin & MXS_GPIO_MASK); + if (bank == MXS_PIN_BANK_MAX) + return -EINVAL; + *id = MXS_PIN_TO_PINID(pin & MXS_GPIO_MASK); + return bank; +} + +static unsigned int mx28_get_gpio(struct pin_bank *bank, unsigned int id) +{ + if (bank->gpio_port >= MXS_NON_GPIO) + return -EINVAL; + return bank->gpio_port * PINS_PER_BANK + id; +} + +static void mx28_set_strength(struct pin_bank *bank, + unsigned int id, enum pad_strength strength) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id *= 4; + __raw_writel(PAD_CLEAR << id, addr + CLR_REGISTER); + __raw_writel(strength << id, addr + SET_REGISTER); +} + +static void mx28_set_voltage(struct pin_bank *bank, + unsigned int id, enum pad_voltage volt) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0; + addr += 0x40 * bank->id + 0x10 * (id >> 3); + id &= 0x7; + id = id * 4 + 2; + if (volt == PAD_1_8V) + __raw_writel(1 << id, addr + CLR_REGISTER); + else + __raw_writel(1 << id, addr + SET_REGISTER); +} + +static void mx28_set_pullup(struct pin_bank *bank, unsigned int id, int pullup) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_PULL0; + addr += 0x10 * bank->id; + if (pullup) + __raw_writel(1 << id, addr + SET_REGISTER); + else + __raw_writel(1 << id, addr + CLR_REGISTER); +} + +static void mx28_set_type(struct pin_bank *bank, + unsigned int id, enum pin_fun cfg) +{ + void __iomem *addr; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_MUXSEL0; + addr += 0x20 * bank->id + 0x10 * (id >> 4); + id &= 0xF; + id *= 2; + __raw_writel(0x3 << id, addr + CLR_REGISTER); + __raw_writel(cfg << id, addr + SET_REGISTER); +} + +static int mx28_get_type(struct pin_bank *bank, + unsigned int id) +{ + void __iomem *addr; + int ret; + addr = PINCTRL_BASE_ADDR + HW_PINCTRL_MUXSEL0; + addr += 0x20 * bank->id + 0x10 * (id >> 4); + id &= 0xF; + id *= 2; + ret = (__raw_readl(addr) >> id) & 0x3; + return ret; +} + +static struct pin_bank mx28_pin_banks[6] = { + [0] = { + .id = 0, + .gpio_port = 0, + }, + [1] = { + .id = 1, + .gpio_port = 1, + }, + [2] = { + .id = 2, + .gpio_port = 2, + }, + [3] = { + .id = 3, + .gpio_port = 3, + }, + [4] = { + .id = 4, + .gpio_port = 4, + }, + [5] = { + .id = 5, + .gpio_port = MXS_NON_GPIO, + } +}; + +static struct pinctrl_chip mx28_pinctrl = { + .name = "pinctrl", + .banks = mx28_pin_banks, + .pin2id = mx28_pin2id, + .get_gpio = mx28_get_gpio, + .set_strength = mx28_set_strength, + .set_voltage = mx28_set_voltage, + .set_pullup = mx28_set_pullup, + .set_type = mx28_set_type, + .get_type = mx28_get_type, +}; + +int __init mx28_pinctrl_init(void) +{ + int i; + if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) & + BM_PINCTRL_CTRL_SFTRST) { + __raw_writel(BM_PINCTRL_CTRL_SFTRST, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) & + BM_PINCTRL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -EFAULT; + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + } + + __raw_writel(BM_PINCTRL_CTRL_CLKGATE, + PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR); + mx28_pinctrl.bank_size = ARRAY_SIZE(mx28_pin_banks); + return mxs_set_pinctrl_chip(&mx28_pinctrl); +} diff --git a/arch/arm/mach-mx28/pm.c b/arch/arm/mach-mx28/pm.c new file mode 100644 index 000000000000..affb0de9f312 --- /dev/null +++ b/arch/arm/mach-mx28/pm.c @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include "regs-clkctrl.h" +#include +#include +#include +#include +#include "regs-dram.h" +#include "mx28_pins.h" +#include "mx28evk.h" + +#include "sleep.h" + +#define PENDING_IRQ_RETRY 100 +static void *saved_sram; +static int saved_sleep_state; + +#define WAIT_DC_OK_CYCLES 24000 +#define WAIT_CYCLE(n) for (i = 0; i < n; i++); +#define LOWER_VDDIO 10 +#define LOWER_VDDA 9 +#define LOWER_VDDD 0xa +#define MAX_POWEROFF_CODE_SIZE (6 * 1024) +#define REGS_CLKCTRL_BASE IO_ADDRESS(CLKCTRL_PHYS_ADDR) +#define dbgc(ch) __raw_writel(ch, IO_ADDRESS(0x80074000)); +inline void dbgnum(u32 num) +{ + dbgc((num / 1000) + '0'); + dbgc(((num%1000) / 100) + '0'); + dbgc(((num%100) / 10) + '0'); + dbgc((num%10) + '0'); + dbgc('\n'); +} + +static inline void do_standby(void) +{ + void (*mx28_cpu_standby_ptr) (void); + struct clk *cpu_clk; + struct clk *osc_clk; + struct clk *pll_clk; + struct clk *hbus_clk; + struct clk *cpu_parent = NULL; + int cpu_rate = 0; + int hbus_rate = 0; + u32 reg_clkctrl_clkseq, reg_clkctrl_xtal; + unsigned long iram_phy_addr; + void *iram_virtual_addr; + int wakeupirq; + mx28evk_enet_io_lowerpower_enter(); + /* + * 1) switch clock domains from PLL to 24MHz + * 2) lower voltage (TODO) + * 3) switch EMI to 24MHz and turn PLL off (done in sleep.S) + */ + + + /* make sure SRAM copy gets physically written into SDRAM. + * SDRAM will be placed into self-refresh during power down + */ + flush_cache_all(); + iram_virtual_addr = iram_alloc(MAX_POWEROFF_CODE_SIZE, &iram_phy_addr); + if (iram_virtual_addr == NULL) { + pr_info("can not get iram for suspend\n"); + return; + } + /* copy suspend function into SRAM */ + memcpy(iram_virtual_addr, mx28_cpu_standby, mx28_standby_alloc_sz); + + /* now switch the CPU to ref_xtal */ + cpu_clk = clk_get(NULL, "cpu"); + osc_clk = clk_get(NULL, "ref_xtal"); + pll_clk = clk_get(NULL, "pll.0"); + hbus_clk = clk_get(NULL, "h"); + + if (!IS_ERR(cpu_clk) && !IS_ERR(osc_clk)) { + cpu_rate = clk_get_rate(cpu_clk); + cpu_parent = clk_get_parent(cpu_clk); + hbus_rate = clk_get_rate(hbus_clk); + clk_set_parent(cpu_clk, osc_clk); + } else + pr_err("fail to get cpu clk\n"); + if (cpu_rate == 261818000) + clk_set_rate(hbus_clk, 8727267); + local_fiq_disable(); + + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + + reg_clkctrl_clkseq = __raw_readl(REGS_CLKCTRL_BASE + + HW_CLKCTRL_CLKSEQ); + + reg_clkctrl_xtal = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL); + + + /* do suspend */ + mx28_cpu_standby_ptr = iram_virtual_addr; + + mx28_cpu_standby_ptr(); + + wakeupirq = __raw_readl(IO_ADDRESS(ICOLL_PHYS_ADDR) + HW_ICOLL_STAT); + + pr_info("wakeup irq = %d\n", wakeupirq); + + __raw_writel(reg_clkctrl_clkseq, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); + __raw_writel(reg_clkctrl_xtal, REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL); + saved_sleep_state = 0; /* waking from standby */ + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + + local_fiq_enable(); + + if (cpu_parent) { + clk_set_parent(cpu_clk, cpu_parent); + clk_set_rate(cpu_clk, cpu_rate); + clk_set_rate(hbus_clk, hbus_rate); + } + + clk_put(hbus_clk); + clk_put(pll_clk); + clk_put(osc_clk); + clk_put(cpu_clk); + + iram_free(iram_phy_addr, MAX_POWEROFF_CODE_SIZE); + mx28evk_enet_io_lowerpower_exit(); +} + +static noinline void do_mem(void) +{ + /* TODO */ +} + +static int mx28_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + do_standby(); + break; + case PM_SUSPEND_MEM: + do_mem(); + break; + } + return 0; +} + +static int mx28_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY) || + (state == PM_SUSPEND_MEM); +} + +static suspend_state_t saved_state; + +static int mx28_pm_begin(suspend_state_t state) +{ + saved_state = state; + return 0; +} + +static void mx28_pm_recover(void) +{ + /* + * The PSWITCH interrupt is enabled at do_standby, if the deivce + * suspend failed, the enable operation will not be executed, in that + * case, the POWER key will not be active again. + */ + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); +} + +static void mx28_pm_end(void) +{ + /*XXX: Nothing to do */ +} + +suspend_state_t mx28_pm_get_target(void) +{ + return saved_state; +} +EXPORT_SYMBOL(mx28_pm_get_target); + +/** + * mx28_pm_get_sleep_state - get sleep state we waking from + * + * returns boolean: 0 if waking up from standby, 1 otherwise + */ +int mx28_pm_sleep_was_deep(void) +{ + return saved_sleep_state; +} +EXPORT_SYMBOL(mx28_pm_sleep_was_deep); + +static struct platform_suspend_ops mx28_suspend_ops = { + .enter = mx28_pm_enter, + .valid = mx28_pm_valid, + .begin = mx28_pm_begin, + .end = mx28_pm_end, + .recover = mx28_pm_recover, +}; + +void mx28_pm_idle(void) +{ + local_irq_disable(); + local_fiq_disable(); + if (need_resched()) { + local_fiq_enable(); + local_irq_enable(); + return; + } + + __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, + REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU_SET); + __asm__ __volatile__ ("mcr p15, 0, r0, c7, c0, 4"); + + local_fiq_enable(); + local_irq_enable(); +} + +static void mx28_pm_power_off(void) +{ + __raw_writel(BF_POWER_RESET_UNLOCK(0x3e77) | BM_POWER_RESET_PWD, + REGS_POWER_BASE + HW_POWER_RESET); +} + +struct mx28_pswitch_state { + int dev_running; +}; + +static DECLARE_COMPLETION(suspend_request); + +static int suspend_thread_fn(void *data) +{ + while (1) { + wait_for_completion_interruptible(&suspend_request); + pm_suspend(PM_SUSPEND_STANDBY); + } + return 0; +} + +static struct mx28_pswitch_state pswitch_state = { + .dev_running = 0, +}; + +#define PSWITCH_POWER_DOWN_DELAY 30 +static struct delayed_work pswitch_work; +static void pswitch_check_work(struct work_struct *work) +{ + int pin_value, i; + for (i = 0; i < PSWITCH_POWER_DOWN_DELAY; i++) { + pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BF_POWER_STS_PSWITCH(0x1); + if (pin_value == 0) + break; + msleep(100); + } + if (i < PSWITCH_POWER_DOWN_DELAY) { + pr_info("pswitch goto suspend\n"); + complete(&suspend_request); + } else { + pr_info("release pswitch to power down\n"); + for (i = 0; i < 500; i++) { + pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS) + & BF_POWER_STS_PSWITCH(0x1); + if (pin_value == 0) + break; + msleep(10); + } + pr_info("pswitch power down\n"); + mx28_pm_power_off(); + } + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); +} + + +static irqreturn_t pswitch_interrupt(int irq, void *dev) +{ + + /* check if irq by pswitch */ + if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_PSWITCH_IRQ)) + return IRQ_HANDLED; + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + schedule_delayed_work(&pswitch_work, 1); + return IRQ_HANDLED; +} + +static struct irqaction pswitch_irq = { + .name = "pswitch", + .flags = IRQF_DISABLED | IRQF_SHARED, + .handler = pswitch_interrupt, + .dev_id = &pswitch_state, +}; + +static void init_pswitch(void) +{ + INIT_DELAYED_WORK(&pswitch_work, pswitch_check_work); + kthread_run(suspend_thread_fn, NULL, "pswitch"); + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_POLARITY_PSWITCH | + BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + setup_irq(IRQ_VDD5V, &pswitch_irq); +} + +static int __init mx28_pm_init(void) +{ + saved_sram = kmalloc(0x4000, GFP_ATOMIC); + if (!saved_sram) { + printk(KERN_ERR + "PM Suspend: can't allocate memory to save portion of SRAM\n"); + return -ENOMEM; + } + + pm_power_off = mx28_pm_power_off; + pm_idle = mx28_pm_idle; + suspend_set_ops(&mx28_suspend_ops); + init_pswitch(); + return 0; +} + +late_initcall(mx28_pm_init); diff --git a/arch/arm/mach-mx28/power.c b/arch/arm/mach-mx28/power.c new file mode 100644 index 000000000000..3ea9161ea95d --- /dev/null +++ b/arch/arm/mach-mx28/power.c @@ -0,0 +1,582 @@ +/* + * Freescale STMP378X voltage regulator low-level driver + * + * Embedded Alley Solutions, Inc + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* #define DEBUG */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mx28_pins.h" +#include +#include +#include + +#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_AUART2_TX) +#define MX28EVK_VBUS5v 5 + +static int get_voltage(struct mxs_regulator *sreg) +{ + int uv; + struct mxs_platform_regulator_data *rdata = sreg->rdata; + u32 val = __raw_readl(rdata->control_reg) & 0x1f; + if (sreg->rdata->control_reg == + (u32)(REGS_POWER_BASE + HW_POWER_VDDIOCTRL)) { + if (val > 0x10) + val = 0x10; + uv = rdata->min_voltage + val * 50000; + pr_info("vddio = %d, val=%u\n", uv, val); + } else + uv = rdata->min_voltage + val * + (rdata->max_voltage - rdata->min_voltage) / 0x1f; + return uv; +} + +static int get_bo_voltage(struct mxs_regulator *sreg) +{ + int uv; + int offs; + + if (!sreg->parent) + return -EINVAL; + + uv = get_voltage(sreg->parent); + offs = (__raw_readl(sreg->parent->rdata->control_reg) & ~0x700) >> 8; + return uv - 25000*offs; +} + +static int set_voltage(struct mxs_regulator *sreg, int uv) +{ + u32 val, reg, i; + + pr_debug("%s: uv %d, min %d, max %d\n", __func__, + uv, sreg->rdata->min_voltage, sreg->rdata->max_voltage); + + if (uv < sreg->rdata->min_voltage || uv > sreg->rdata->max_voltage) + return -EINVAL; + + if (sreg->rdata->control_reg == + (u32)(REGS_POWER_BASE + HW_POWER_VDDIOCTRL)) + val = (uv - sreg->rdata->min_voltage) / 50000; + else + val = (uv - sreg->rdata->min_voltage) * 0x1f / + (sreg->rdata->max_voltage - sreg->rdata->min_voltage); + reg = (__raw_readl(sreg->rdata->control_reg) & ~0x1f); + pr_debug("%s: calculated val %d\n", __func__, val); + __raw_writel(val | reg, sreg->rdata->control_reg); + for (i = 20; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + __raw_writel(val | reg, sreg->rdata->control_reg); + for (i = 40000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + for (i = 40000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + +out: + return !i; +} + +static int set_bo_voltage(struct mxs_regulator *sreg, int bo_uv) +{ + int uv; + int offs; + u32 reg; + int i; + + if (!sreg->parent) + return -EINVAL; + + uv = get_voltage(sreg->parent); + offs = (uv - bo_uv) / 25000; + if (offs < 0 || offs > 7) + return -EINVAL; + + reg = (__raw_readl(sreg->parent->rdata->control_reg) & ~0x700); + pr_debug("%s: calculated offs %d\n", __func__, offs); + __raw_writel((offs << 8) | reg, sreg->parent->rdata->control_reg); + + for (i = 10000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + + if (i) + goto out; + + for (i = 10000; i; i--) { + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK) + break; + udelay(1); + } + +out: + return !i; +} + +static int enable(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int disable(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int is_enabled(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 1; +} + +static int set_mode(struct mxs_regulator *sreg, int mode) +{ + int ret = 0; + u32 val; + + switch (mode) { + case REGULATOR_MODE_FAST: + val = __raw_readl(sreg->rdata->control_reg); + __raw_writel(val | (1 << 17), sreg->rdata->control_reg); + break; + + case REGULATOR_MODE_NORMAL: + val = __raw_readl(sreg->rdata->control_reg); + __raw_writel(val & ~(1<<17), sreg->rdata->control_reg); + break; + + default: + ret = -EINVAL; + break; + } + return ret; +} + +static int get_mode(struct mxs_regulator *sreg) +{ + u32 val = __raw_readl(sreg->rdata->control_reg) & (1 << 17); + + return val ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; +} + +static struct mxs_platform_regulator_data vddd_data = { + .name = "vddd", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDDCTRL), + .min_voltage = 800000, + .max_voltage = 1575000, +}; + +static struct mxs_platform_regulator_data vdddbo_data = { + .name = "vddd_bo", + .parent_name = "vddd", + .set_voltage = set_bo_voltage, + .get_voltage = get_bo_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .min_voltage = 800000, + .max_voltage = 1575000, +}; + +static struct mxs_platform_regulator_data vdda_data = { + .name = "vdda", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDACTRL), + .min_voltage = 1500000, + .max_voltage = 2275000, +}; + +#define MX28EVK_VDDIO_OFFSET 80000 +static struct mxs_platform_regulator_data vddio_data = { + .name = "vddio", + .set_voltage = set_voltage, + .get_voltage = get_voltage, + .enable = enable, + .disable = disable, + .is_enabled = is_enabled, + .set_mode = set_mode, + .get_mode = get_mode, + .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDIOCTRL), + .min_voltage = 2800000 + MX28EVK_VDDIO_OFFSET, + .max_voltage = 3600000 + MX28EVK_VDDIO_OFFSET, +}; + +static struct regulator_init_data vddd_init = { + .constraints = { + .name = "vddd", + .min_uV = 800000, + .max_uV = 1575000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + +static struct regulator_init_data vdddbo_init = { + .constraints = { + .name = "vdddbo", + .min_uV = 800000, + .max_uV = 1575000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + + +static struct regulator_init_data vdda_init = { + .constraints = { + .name = "vdda", + .min_uV = 1500000, + .max_uV = 2275000, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + + +static struct regulator_init_data vddio_init = { + .constraints = { + .name = "vddio", + .min_uV = 2800000 + MX28EVK_VDDIO_OFFSET, + .max_uV = 3600000 + MX28EVK_VDDIO_OFFSET, + .valid_modes_mask = REGULATOR_MODE_FAST | + REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + .input_uV = 5000000, + .always_on = 1, + } +}; + +static int vbus5v_enable(struct mxs_regulator *sreg) +{ + gpio_set_value(USB_POWER_ENABLE, 1); + return 0; +} + +static int vbus5v_disable(struct mxs_regulator *sreg) +{ + gpio_set_value(USB_POWER_ENABLE, 0); + return 0; +} + +static int vbus5v_is_enabled(struct mxs_regulator *sreg) +{ + return gpio_get_value(USB_POWER_ENABLE); +} + + +static struct mxs_platform_regulator_data vbus5v_data = { + .name = "vbus5v", + .enable = vbus5v_enable, + .disable = vbus5v_disable, + .is_enabled = vbus5v_is_enabled, +}; + +static struct regulator_init_data vbus5v_init = { + .constraints = { + .name = "vbus5v", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + + +/* now the current regulators */ +/* Restriction: .... no set_current call on root regulator */ +static int main_add_current(struct mxs_regulator *sreg, + int uA) +{ + + pr_debug("%s: enter reg %s, uA=%d\n", + __func__, sreg->regulator.name, uA); + if (uA > 0 && (sreg->cur_current + uA > sreg->rdata->max_current)) + return -EINVAL; + else + sreg->cur_current += uA; + return 0; +} + +static int cur_reg_set_current(struct mxs_regulator *sreg, int uA) +{ + int ret = 0; + unsigned long flags; + + pr_debug("%s: enter reg %s, uA=%d\n", + __func__, sreg->regulator.name, uA); + + if (sreg->parent) { + spin_lock_irqsave(&sreg->parent->lock, flags); + ret = main_add_current(sreg->parent, uA - sreg->cur_current); + spin_unlock_irqrestore(&sreg->parent->lock, flags); + } + + + if ((!ret) || (!sreg->parent)) + goto out; + + if (sreg->mode == REGULATOR_MODE_FAST) + return ret; + + while (ret) { + wait_event(sreg->parent->wait_q , + (uA - sreg->cur_current < + sreg->parent->rdata->max_current - + sreg->parent->cur_current)); + spin_lock_irqsave(&sreg->parent->lock, flags); + ret = main_add_current(sreg->parent, uA - sreg->cur_current); + spin_unlock_irqrestore(&sreg->parent->lock, flags); + } +out: + if (sreg->parent && (uA - sreg->cur_current < 0)) + wake_up_all(&sreg->parent->wait_q); + sreg->cur_current = uA; + return 0; + +} + +static int cur_reg_get_current(struct mxs_regulator *sreg) +{ + return sreg->cur_current; +} + +static int enable_cur_reg(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int disable_cur_reg(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 0; +} + +static int cur_reg_is_enabled(struct mxs_regulator *sreg) +{ + /* XXX: TODO */ + return 1; +} + +static int cur_reg_set_mode(struct mxs_regulator *sreg, int mode) +{ + int ret = 0; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + case REGULATOR_MODE_FAST: + sreg->mode = mode; + break; + default: + ret = -EINVAL; + break; + } + return ret; +} + +static int cur_reg_get_mode(struct mxs_regulator *sreg) +{ + return sreg->mode; +} + +static struct mxs_platform_regulator_data overall_cur_data = { + .name = "overall_current", + .set_current = cur_reg_set_current, + .get_current = cur_reg_get_current, + .enable = enable_cur_reg, + .disable = disable_cur_reg, + .is_enabled = cur_reg_is_enabled, + .set_mode = cur_reg_set_mode, + .get_mode = cur_reg_get_mode, + .max_current = 0x7fffffff, +}; + +static struct regulator_init_data overall_cur_init = { + .constraints = { + .name = "overall_current", + .valid_modes_mask = REGULATOR_MODE_NORMAL | + REGULATOR_MODE_FAST, + .valid_ops_mask = REGULATOR_CHANGE_CURRENT | + REGULATOR_CHANGE_MODE, + .max_uA = 0x7fffffff, + .min_uA = 0x0, + .always_on = 1, + } +}; + +static struct mxs_platform_regulator_data sibling_cur_data = { + .parent_name = "overall_current", + .set_current = cur_reg_set_current, + .get_current = cur_reg_get_current, + .enable = enable_cur_reg, + .disable = disable_cur_reg, + .is_enabled = cur_reg_is_enabled, + .set_mode = cur_reg_set_mode, + .get_mode = cur_reg_get_mode, +}; + + +static const char *device_names[] = { + "mxs-duart", "mxs-bl", "mxs-i2c" +}; + +static int sibling_current_devices_num; + +int mxs_platform_add_regulator(const char *name, int count) +{ + int i; + pr_debug("%s: name %s, count %d\n", __func__, name, count); + for (i = sibling_current_devices_num; + i < sibling_current_devices_num + count; + i++) { + struct regulator_init_data *sibling_init = + kzalloc(sizeof(struct regulator_init_data), + GFP_KERNEL); + struct mxs_regulator *curr_reg = + kzalloc(sizeof(struct mxs_regulator), + GFP_KERNEL); + struct mxs_platform_regulator_data *d = + kzalloc(sizeof(struct mxs_platform_regulator_data), + GFP_KERNEL); + if (!d || !curr_reg || !sibling_init) + return -ENOMEM; + + sibling_init->constraints.valid_modes_mask = + REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST; + sibling_init->constraints.valid_ops_mask = + REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_MODE; + sibling_init->constraints.max_uA = 0x7fffffff; + sibling_init->constraints.min_uA = 0x0; + + memcpy(d, &sibling_cur_data, sizeof(sibling_cur_data)); + d->parent_name = kstrdup(sibling_cur_data.parent_name, + GFP_KERNEL); + snprintf(d->name, 80, "%s-%d", + name, i - sibling_current_devices_num + 1); + sibling_init->constraints.name = kstrdup(d->name, GFP_KERNEL); + sibling_init->constraints.always_on = 1; + curr_reg->rdata = d; + mxs_register_regulator(curr_reg, 101 + i, sibling_init); + } + sibling_current_devices_num += count; + return 0; +} + +static struct mxs_regulator vddd_reg = { + .rdata = &vddd_data, +}; + +static struct mxs_regulator vdda_reg = { + .rdata = &vdda_data, +}; + +static struct mxs_regulator vddio_reg = { + .rdata = &vddio_data, +}; + +static struct mxs_regulator vdddbo_reg = { + .rdata = &vdddbo_data, +}; + +static struct mxs_regulator overall_cur_reg = { + .rdata = &overall_cur_data, +}; + +static struct mxs_regulator vbus5v_reg = { + .rdata = &vbus5v_data, +}; + +static int __init regulators_init(void) +{ + int i; + int retval = 0; + u32 vddio = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) & ~0x1f; + pr_debug("regulators_init \n"); + __raw_writel(vddio | 0xA, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + vdddbo_reg.parent = &vddd_reg; + mxs_register_regulator(&vddd_reg, MXS_VDDD, &vddd_init); + mxs_register_regulator(&vdddbo_reg, MXS_VDDDBO, &vdddbo_init); + mxs_register_regulator(&vdda_reg, MXS_VDDA, &vdda_init); + mxs_register_regulator(&vddio_reg, MXS_VDDIO, &vddio_init); + mxs_register_regulator(&overall_cur_reg, + MXS_OVERALL_CUR, &overall_cur_init); + + mxs_register_regulator(&vbus5v_reg, MX28EVK_VBUS5v, &vbus5v_init); + + for (i = 0; i < ARRAY_SIZE(device_names); i++) { + retval = mxs_platform_add_regulator(device_names[i], 1); + if (retval) + return retval; + } + mxs_platform_add_regulator("mmc_ssp", 2); + mxs_platform_add_regulator("charger", 1); + mxs_platform_add_regulator("power-test", 1); + mxs_platform_add_regulator("cpufreq", 1); + gpio_direction_output(USB_POWER_ENABLE, 0); + return 0; +} +postcore_initcall(regulators_init); diff --git a/arch/arm/mach-mx28/regs-clkctrl.h b/arch/arm/mach-mx28/regs-clkctrl.h new file mode 100644 index 000000000000..161860c2fcf0 --- /dev/null +++ b/arch/arm/mach-mx28/regs-clkctrl.h @@ -0,0 +1,634 @@ +/* + * Freescale CLKCTRL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.48 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___CLKCTRL_H +#define __ARCH_ARM___CLKCTRL_H + +#define HW_CLKCTRL_PLL0CTRL0 (0x00000000) +#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) + +#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6) +#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL0CTRL1 (0x00000010) + +#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL1CTRL0 (0x00000020) +#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024) +#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028) +#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) + +#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000 +#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL) +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5) +#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL) +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4) +#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000 +#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 +#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF +#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1) + +#define HW_CLKCTRL_PLL1CTRL1 (0x00000030) + +#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1) +#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_PLL2CTRL0 (0x00000040) +#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044) +#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048) +#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) + +#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000 +#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) +#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000 +#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 +#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) +#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 +#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF +#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1) + +#define HW_CLKCTRL_CPU (0x00000050) +#define HW_CLKCTRL_CPU_SET (0x00000054) +#define HW_CLKCTRL_CPU_CLR (0x00000058) +#define HW_CLKCTRL_CPU_TOG (0x0000005c) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) + +#define HW_CLKCTRL_HBUS (0x00000060) +#define HW_CLKCTRL_HBUS_SET (0x00000064) +#define HW_CLKCTRL_HBUS_CLR (0x00000068) +#define HW_CLKCTRL_HBUS_TOG (0x0000006c) + +#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000 +#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000 +#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000070) + +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 12 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) + +#define HW_CLKCTRL_XTAL (0x00000080) +#define HW_CLKCTRL_XTAL_SET (0x00000084) +#define HW_CLKCTRL_XTAL_CLR (0x00000088) +#define HW_CLKCTRL_XTAL_TOG (0x0000008c) + +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BP_CLKCTRL_XTAL_RSRVD2 27 +#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000 +#define BF_CLKCTRL_XTAL_RSRVD2(v) \ + (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2) +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_SSP0 (0x00000090) + +#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP0_BUSY 0x20000000 +#define BP_CLKCTRL_SSP0_RSRVD1 10 +#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP0_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1) +#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP0_DIV 0 +#define BM_CLKCTRL_SSP0_DIV 0x000001FF +#define BF_CLKCTRL_SSP0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP0_DIV) + +#define HW_CLKCTRL_SSP1 (0x000000a0) + +#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP1_BUSY 0x20000000 +#define BP_CLKCTRL_SSP1_RSRVD1 10 +#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP1_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1) +#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP1_DIV 0 +#define BM_CLKCTRL_SSP1_DIV 0x000001FF +#define BF_CLKCTRL_SSP1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP1_DIV) + +#define HW_CLKCTRL_SSP2 (0x000000b0) + +#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP2_BUSY 0x20000000 +#define BP_CLKCTRL_SSP2_RSRVD1 10 +#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP2_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1) +#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP2_DIV 0 +#define BM_CLKCTRL_SSP2_DIV 0x000001FF +#define BF_CLKCTRL_SSP2_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP2_DIV) + +#define HW_CLKCTRL_SSP3 (0x000000c0) + +#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP3_BUSY 0x20000000 +#define BP_CLKCTRL_SSP3_RSRVD1 10 +#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP3_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1) +#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP3_DIV 0 +#define BM_CLKCTRL_SSP3_DIV 0x000001FF +#define BF_CLKCTRL_SSP3_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP3_DIV) + +#define HW_CLKCTRL_GPMI (0x000000d0) + +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x000000e0) + +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000f0) + +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) + +#define HW_CLKCTRL_SAIF0 (0x00000100) + +#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF0_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF0_RSRVD1 17 +#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF0_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1) +#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF0_DIV 0 +#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF0_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) + +#define HW_CLKCTRL_SAIF1 (0x00000110) + +#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF1_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF1_RSRVD1 17 +#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF1_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1) +#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF1_DIV 0 +#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF1_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF1_DIV) + +#define HW_CLKCTRL_DIS_LCDIF (0x00000120) + +#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 +#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14 +#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000 +#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \ + (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1) +#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 +#define BP_CLKCTRL_DIS_LCDIF_DIV 0 +#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF +#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV) + +#define HW_CLKCTRL_ETM (0x00000130) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 8 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000007F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_ENET (0x00000140) + +#define BM_CLKCTRL_ENET_SLEEP 0x80000000 +#define BM_CLKCTRL_ENET_DISABLE 0x40000000 +#define BM_CLKCTRL_ENET_STATUS 0x20000000 +#define BM_CLKCTRL_ENET_RSRVD1 0x10000000 +#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 +#define BP_CLKCTRL_ENET_DIV_TIME 21 +#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 +#define BF_CLKCTRL_ENET_DIV_TIME(v) \ + (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME) +#define BP_CLKCTRL_ENET_TIME_SEL 19 +#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000 +#define BF_CLKCTRL_ENET_TIME_SEL(v) \ + (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL) +#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0 +#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1 +#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2 +#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 +#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 +#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 +#define BP_CLKCTRL_ENET_RSRVD0 0 +#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF +#define BF_CLKCTRL_ENET_RSRVD0(v) \ + (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) + +#define HW_CLKCTRL_HSADC (0x00000150) + +#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000 +#define BM_CLKCTRL_HSADC_RESETB 0x40000000 +#define BP_CLKCTRL_HSADC_FREQDIV 28 +#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 +#define BF_CLKCTRL_HSADC_FREQDIV(v) \ + (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) +#define BP_CLKCTRL_HSADC_RSRVD1 0 +#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF +#define BF_CLKCTRL_HSADC_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1) + +#define HW_CLKCTRL_FLEXCAN (0x00000160) + +#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 +#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 +#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 +#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 +#define BP_CLKCTRL_FLEXCAN_RSRVD1 0 +#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF +#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1) + +#define HW_CLKCTRL_FRAC0 (0x000001b0) +#define HW_CLKCTRL_FRAC0_SET (0x000001b4) +#define HW_CLKCTRL_FRAC0_CLR (0x000001b8) +#define HW_CLKCTRL_FRAC0_TOG (0x000001bc) + +#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000 +#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC0_IO0FRAC 24 +#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000 +#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC) +#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000 +#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC0_IO1FRAC 16 +#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000 +#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC) +#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC0_EMIFRAC 8 +#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC) +#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC0_CPUFRAC 0 +#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC) + +#define HW_CLKCTRL_FRAC1 (0x000001c0) +#define HW_CLKCTRL_FRAC1_SET (0x000001c4) +#define HW_CLKCTRL_FRAC1_CLR (0x000001c8) +#define HW_CLKCTRL_FRAC1_TOG (0x000001cc) + +#define BP_CLKCTRL_FRAC1_RSRVD2 24 +#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000 +#define BF_CLKCTRL_FRAC1_RSRVD2(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2) +#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 +#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC1_GPMIFRAC 16 +#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC) +#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000 +#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC1_HSADCFRAC 8 +#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC) +#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080 +#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC1_PIXFRAC 0 +#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F +#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC) + +#define HW_CLKCTRL_CLKSEQ (0x000001d0) +#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4) +#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) +#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) + +#define BP_CLKCTRL_CLKSEQ_RSRVD0 19 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000 +#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \ + (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0) +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 +#define BP_CLKCTRL_CLKSEQ_RSRVD1 15 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 +#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 +#define BP_CLKCTRL_CLKSEQ_RSRVD2 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00 +#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001 + +#define HW_CLKCTRL_RESET (0x000001e0) + +#define BP_CLKCTRL_RESET_RSRVD 6 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0 +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 6) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 +#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 +#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 +#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004 +#define BM_CLKCTRL_RESET_CHIP 0x00000002 +#define BM_CLKCTRL_RESET_DIG 0x00000001 + +#define HW_CLKCTRL_STATUS (0x000001f0) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000200) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) +#endif /* __ARCH_ARM___CLKCTRL_H */ diff --git a/arch/arm/mach-mx28/regs-digctl.h b/arch/arm/mach-mx28/regs-digctl.h new file mode 100644 index 000000000000..6ebda07581c2 --- /dev/null +++ b/arch/arm/mach-mx28/regs-digctl.h @@ -0,0 +1,1022 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ARCH_ARM___DIGCTL_H +#define __ARCH_ARM___DIGCTL_H + + +#define HW_DIGCTL_CTRL (0x00000000) +#define HW_DIGCTL_CTRL_SET (0x00000004) +#define HW_DIGCTL_CTRL_CLR (0x00000008) +#define HW_DIGCTL_CTRL_TOG (0x0000000c) + +#define BM_DIGCTL_CTRL_RSVD3 0x80000000 +#define BM_DIGCTL_CTRL_XTAL24M_GATE 0x40000000 +#define BP_DIGCTL_CTRL_RSVD2 25 +#define BM_DIGCTL_CTRL_RSVD2 0x3E000000 +#define BF_DIGCTL_CTRL_RSVD2(v) \ + (((v) << 25) & BM_DIGCTL_CTRL_RSVD2) +#define BM_DIGCTL_CTRL_USB1_OVERCURRENT_ENABLE 0x01000000 +#define BM_DIGCTL_CTRL_USB0_OVERCURRENT_ENABLE 0x00800000 +#define BM_DIGCTL_CTRL_USB1_OVERCURRENT_POL 0x00400000 +#define BM_DIGCTL_CTRL_USB0_OVERCURRENT_POL 0x00200000 +#define BM_DIGCTL_CTRL_USB1_TESTMODE 0x00100000 +#define BM_DIGCTL_CTRL_USB0_TESTMODE 0x00080000 +#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x00040000 +#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x00020000 +#define BM_DIGCTL_CTRL_USB1_CLKGATE 0x00010000 +#define BV_DIGCTL_CTRL_USB1_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB1_CLKGATE__NO_CLKS 0x1 +#define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x00008000 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_DUART_LOOPBACK 0x00004000 +#define BV_DIGCTL_CTRL_DUART_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_DUART_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_AUART01_LOOPBACK 0x00002000 +#define BV_DIGCTL_CTRL_AUART01_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_AUART01_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_RSVD1 0x00001000 +#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 10 +#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x00000C00 +#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) \ + (((v) << 10) & BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL) +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__DIRECT 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__CROSSINPUT 0x1 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__CLKSRCSAIF0PIN 0x2 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__CLKSRCSAIF1PIN 0x3 +#define BP_DIGCTL_CTRL_RSVD0 4 +#define BM_DIGCTL_CTRL_RSVD0 0x000003F0 +#define BF_DIGCTL_CTRL_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_CTRL_RSVD0) +#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x00000008 +#define BM_DIGCTL_CTRL_USB0_CLKGATE 0x00000004 +#define BV_DIGCTL_CTRL_USB0_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB0_CLKGATE__NO_CLKS 0x1 +#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x00000002 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 +#define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x00000001 + +#define HW_DIGCTL_STATUS (0x00000010) +#define HW_DIGCTL_STATUS_SET (0x00000014) +#define HW_DIGCTL_STATUS_CLR (0x00000018) +#define HW_DIGCTL_STATUS_TOG (0x0000001c) + +#define BM_DIGCTL_STATUS_USB0_HS_PRESENT 0x80000000 +#define BM_DIGCTL_STATUS_USB0_OTG_PRESENT 0x40000000 +#define BM_DIGCTL_STATUS_USB0_HOST_PRESENT 0x20000000 +#define BM_DIGCTL_STATUS_USB0_DEVICE_PRESENT 0x10000000 +#define BM_DIGCTL_STATUS_USB1_HS_PRESENT 0x08000000 +#define BM_DIGCTL_STATUS_USB1_OTG_PRESENT 0x04000000 +#define BM_DIGCTL_STATUS_USB1_HOST_PRESENT 0x02000000 +#define BM_DIGCTL_STATUS_USB1_DEVICE_PRESENT 0x01000000 +#define BP_DIGCTL_STATUS_RSVD0 5 +#define BM_DIGCTL_STATUS_RSVD0 0x00FFFFE0 +#define BF_DIGCTL_STATUS_RSVD0(v) \ + (((v) << 5) & BM_DIGCTL_STATUS_RSVD0) +#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x00000010 +#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 +#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x0000000E +#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) \ + (((v) << 1) & BM_DIGCTL_STATUS_PACKAGE_TYPE) +#define BM_DIGCTL_STATUS_WRITTEN 0x00000001 + +#define HW_DIGCTL_HCLKCOUNT (0x00000020) +#define HW_DIGCTL_HCLKCOUNT_SET (0x00000024) +#define HW_DIGCTL_HCLKCOUNT_CLR (0x00000028) +#define HW_DIGCTL_HCLKCOUNT_TOG (0x0000002c) + +#define BP_DIGCTL_HCLKCOUNT_COUNT 0 +#define BM_DIGCTL_HCLKCOUNT_COUNT 0xFFFFFFFF +#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (v) + +#define HW_DIGCTL_RAMCTRL (0x00000030) +#define HW_DIGCTL_RAMCTRL_SET (0x00000034) +#define HW_DIGCTL_RAMCTRL_CLR (0x00000038) +#define HW_DIGCTL_RAMCTRL_TOG (0x0000003c) + +#define BP_DIGCTL_RAMCTRL_RSVD1 15 +#define BM_DIGCTL_RAMCTRL_RSVD1 0xFFFF8000 +#define BF_DIGCTL_RAMCTRL_RSVD1(v) \ + (((v) << 15) & BM_DIGCTL_RAMCTRL_RSVD1) +#define BM_DIGCTL_RAMCTRL_TBYPASS 0x00004000 +#define BM_DIGCTL_RAMCTRL_DEBUG_ENABLE 0x00002000 +#define BP_DIGCTL_RAMCTRL_DEBUG_CODE 8 +#define BM_DIGCTL_RAMCTRL_DEBUG_CODE 0x00001F00 +#define BF_DIGCTL_RAMCTRL_DEBUG_CODE(v) \ + (((v) << 8) & BM_DIGCTL_RAMCTRL_DEBUG_CODE) +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__NORMAL 0x0 +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__DELAY1 0x4 +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__DELAY2 0x5 +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__DELAY3 0x6 +#define BV_DIGCTL_RAMCTRL_DEBUG_CODE__DELAY4 0x7 +#define BP_DIGCTL_RAMCTRL_RSVD0 0 +#define BM_DIGCTL_RAMCTRL_RSVD0 0x000000FF +#define BF_DIGCTL_RAMCTRL_RSVD0(v) \ + (((v) << 0) & BM_DIGCTL_RAMCTRL_RSVD0) + +#define HW_DIGCTL_EMI_STATUS (0x00000040) +#define HW_DIGCTL_EMI_STATUS_SET (0x00000044) +#define HW_DIGCTL_EMI_STATUS_CLR (0x00000048) +#define HW_DIGCTL_EMI_STATUS_TOG (0x0000004c) + +#define BP_DIGCTL_EMI_STATUS_RSVD0 5 +#define BM_DIGCTL_EMI_STATUS_RSVD0 0xFFFFFFE0 +#define BF_DIGCTL_EMI_STATUS_RSVD0(v) \ + (((v) << 5) & BM_DIGCTL_EMI_STATUS_RSVD0) +#define BP_DIGCTL_EMI_STATUS_POWER_MODE 0 +#define BM_DIGCTL_EMI_STATUS_POWER_MODE 0x0000001F +#define BF_DIGCTL_EMI_STATUS_POWER_MODE(v) \ + (((v) << 0) & BM_DIGCTL_EMI_STATUS_POWER_MODE) +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM5 0x1 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM4 0x2 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM3 0x4 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM2 0x8 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__PM1 0x10 +#define BV_DIGCTL_EMI_STATUS_POWER_MODE__NORMAL 0x0 + +#define HW_DIGCTL_READ_MARGIN (0x00000050) +#define HW_DIGCTL_READ_MARGIN_SET (0x00000054) +#define HW_DIGCTL_READ_MARGIN_CLR (0x00000058) +#define HW_DIGCTL_READ_MARGIN_TOG (0x0000005c) + +#define BP_DIGCTL_READ_MARGIN_RSVD0 4 +#define BM_DIGCTL_READ_MARGIN_RSVD0 0xFFFFFFF0 +#define BF_DIGCTL_READ_MARGIN_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_READ_MARGIN_RSVD0) +#define BP_DIGCTL_READ_MARGIN_ROM 0 +#define BM_DIGCTL_READ_MARGIN_ROM 0x0000000F +#define BF_DIGCTL_READ_MARGIN_ROM(v) \ + (((v) << 0) & BM_DIGCTL_READ_MARGIN_ROM) + +#define HW_DIGCTL_WRITEONCE (0x00000060) + +#define BP_DIGCTL_WRITEONCE_BITS 0 +#define BM_DIGCTL_WRITEONCE_BITS 0xFFFFFFFF +#define BF_DIGCTL_WRITEONCE_BITS(v) (v) + +#define HW_DIGCTL_BIST_CTL (0x00000070) +#define HW_DIGCTL_BIST_CTL_SET (0x00000074) +#define HW_DIGCTL_BIST_CTL_CLR (0x00000078) +#define HW_DIGCTL_BIST_CTL_TOG (0x0000007c) + +#define BM_DIGCTL_BIST_CTL_BIST_TESTMODE 0x80000000 +#define BM_DIGCTL_BIST_CTL_BIST_RESETN 0x40000000 +#define BM_DIGCTL_BIST_CTL_BIST_DEBUGZ 0x20000000 +#define BM_DIGCTL_BIST_CTL_BIST_CHECKB 0x10000000 +#define BM_DIGCTL_BIST_CTL_BIST_RESUME 0x08000000 +#define BP_DIGCTL_BIST_CTL_RSVD0 15 +#define BM_DIGCTL_BIST_CTL_RSVD0 0x07FF8000 +#define BF_DIGCTL_BIST_CTL_RSVD0(v) \ + (((v) << 15) & BM_DIGCTL_BIST_CTL_RSVD0) +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_RETENTION 0x00004000 +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_PASS 0x00002000 +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_FAIL 0x00001000 +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_DONE 0x00000800 +#define BM_DIGCTL_BIST_CTL_OCRAM_BIST_START 0x00000400 +#define BM_DIGCTL_BIST_CTL_PXP_BIST_START 0x00000200 +#define BM_DIGCTL_BIST_CTL_LCDIF_BIST_START 0x00000100 +#define BM_DIGCTL_BIST_CTL_DCP_BIST_START 0x00000080 +#define BM_DIGCTL_BIST_CTL_ENET_BIST_START 0x00000040 +#define BM_DIGCTL_BIST_CTL_USB1_BIST_START 0x00000020 +#define BM_DIGCTL_BIST_CTL_USB0_BIST_START 0x00000010 +#define BM_DIGCTL_BIST_CTL_DMA1_BIST_START 0x00000008 +#define BM_DIGCTL_BIST_CTL_DMA0_BIST_START 0x00000004 +#define BM_DIGCTL_BIST_CTL_CACHE_BIST_START 0x00000002 +#define BM_DIGCTL_BIST_CTL_CAN_BIST_START 0x00000001 + +#define HW_DIGCTL_BIST_STATUS (0x00000080) +#define HW_DIGCTL_BIST_STATUS_SET (0x00000084) +#define HW_DIGCTL_BIST_STATUS_CLR (0x00000088) +#define HW_DIGCTL_BIST_STATUS_TOG (0x0000008c) + +#define BP_DIGCTL_BIST_STATUS_RSVD0 30 +#define BM_DIGCTL_BIST_STATUS_RSVD0 0xC0000000 +#define BF_DIGCTL_BIST_STATUS_RSVD0(v) \ + (((v) << 30) & BM_DIGCTL_BIST_STATUS_RSVD0) +#define BM_DIGCTL_BIST_STATUS_PXP_BIST_RETENTION 0x20000000 +#define BM_DIGCTL_BIST_STATUS_LCDIF_BIST_RETENTION 0x10000000 +#define BM_DIGCTL_BIST_STATUS_DCP_BIST_RETENTION 0x08000000 +#define BM_DIGCTL_BIST_STATUS_ENET_BIST_RETENTION 0x04000000 +#define BM_DIGCTL_BIST_STATUS_USB1_BIST_RETENTION 0x02000000 +#define BM_DIGCTL_BIST_STATUS_USB0_BIST_RETENTION 0x01000000 +#define BM_DIGCTL_BIST_STATUS_DMA1_BIST_RETENTION 0x00800000 +#define BM_DIGCTL_BIST_STATUS_DMA0_BIST_RETENTION 0x00400000 +#define BM_DIGCTL_BIST_STATUS_CACHE_BIST_RETENTION 0x00200000 +#define BM_DIGCTL_BIST_STATUS_CAN_BIST_RETENTION 0x00100000 +#define BM_DIGCTL_BIST_STATUS_PXP_BIST_FAIL 0x00080000 +#define BM_DIGCTL_BIST_STATUS_LCDIF_BIST_FAIL 0x00040000 +#define BM_DIGCTL_BIST_STATUS_DCP_BIST_FAIL 0x00020000 +#define BM_DIGCTL_BIST_STATUS_ENET_BIST_FAIL 0x00010000 +#define BM_DIGCTL_BIST_STATUS_USB1_BIST_FAIL 0x00008000 +#define BM_DIGCTL_BIST_STATUS_USB0_BIST_FAIL 0x00004000 +#define BM_DIGCTL_BIST_STATUS_DMA1_BIST_FAIL 0x00002000 +#define BM_DIGCTL_BIST_STATUS_DMA0_BIST_FAIL 0x00001000 +#define BM_DIGCTL_BIST_STATUS_CACHE_BIST_FAIL 0x00000800 +#define BM_DIGCTL_BIST_STATUS_CAN_BIST_FAIL 0x00000400 +#define BM_DIGCTL_BIST_STATUS_PXP_BIST_DONE 0x00000200 +#define BM_DIGCTL_BIST_STATUS_LCDIF_BIST_DONE 0x00000100 +#define BM_DIGCTL_BIST_STATUS_DCP_BIST_DONE 0x00000080 +#define BM_DIGCTL_BIST_STATUS_ENET_BIST_DONE 0x00000040 +#define BM_DIGCTL_BIST_STATUS_USB1_BIST_DONE 0x00000020 +#define BM_DIGCTL_BIST_STATUS_USB0_BIST_DONE 0x00000010 +#define BM_DIGCTL_BIST_STATUS_DMA1_BIST_DONE 0x00000008 +#define BM_DIGCTL_BIST_STATUS_DMA0_BIST_DONE 0x00000004 +#define BM_DIGCTL_BIST_STATUS_CACHE_BIST_DONE 0x00000002 +#define BM_DIGCTL_BIST_STATUS_CAN_BIST_DONE 0x00000001 + +#define HW_DIGCTL_ENTROPY (0x00000090) + +#define BP_DIGCTL_ENTROPY_VALUE 0 +#define BM_DIGCTL_ENTROPY_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_VALUE(v) (v) + +#define HW_DIGCTL_ENTROPY_LATCHED (0x000000a0) + +#define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 +#define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (v) + +#define HW_DIGCTL_MICROSECONDS (0x000000c0) +#define HW_DIGCTL_MICROSECONDS_SET (0x000000c4) +#define HW_DIGCTL_MICROSECONDS_CLR (0x000000c8) +#define HW_DIGCTL_MICROSECONDS_TOG (0x000000cc) + +#define BP_DIGCTL_MICROSECONDS_VALUE 0 +#define BM_DIGCTL_MICROSECONDS_VALUE 0xFFFFFFFF +#define BF_DIGCTL_MICROSECONDS_VALUE(v) (v) + +#define HW_DIGCTL_DBGRD (0x000000d0) + +#define BP_DIGCTL_DBGRD_COMPLEMENT 0 +#define BM_DIGCTL_DBGRD_COMPLEMENT 0xFFFFFFFF +#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (v) + +#define HW_DIGCTL_DBG (0x000000e0) + +#define BP_DIGCTL_DBG_VALUE 0 +#define BM_DIGCTL_DBG_VALUE 0xFFFFFFFF +#define BF_DIGCTL_DBG_VALUE(v) (v) + +#define HW_DIGCTL_USB_LOOPBACK (0x00000100) +#define HW_DIGCTL_USB_LOOPBACK_SET (0x00000104) +#define HW_DIGCTL_USB_LOOPBACK_CLR (0x00000108) +#define HW_DIGCTL_USB_LOOPBACK_TOG (0x0000010c) + +#define BP_DIGCTL_USB_LOOPBACK_RSVD0 18 +#define BM_DIGCTL_USB_LOOPBACK_RSVD0 0xFFFC0000 +#define BF_DIGCTL_USB_LOOPBACK_RSVD0(v) \ + (((v) << 18) & BM_DIGCTL_USB_LOOPBACK_RSVD0) +#define BM_DIGCTL_USB_LOOPBACK_USB1_TST_START 0x00020000 +#define BM_DIGCTL_USB_LOOPBACK_TSTI1_TX_LS 0x00010000 +#define BM_DIGCTL_USB_LOOPBACK_TSTI1_TX_HS 0x00008000 +#define BM_DIGCTL_USB_LOOPBACK_TSTI1_TX_EN 0x00004000 +#define BM_DIGCTL_USB_LOOPBACK_TSTI1_TX_HIZ 0x00002000 +#define BM_DIGCTL_USB_LOOPBACK_UTMI1_DIG_TST1 0x00001000 +#define BM_DIGCTL_USB_LOOPBACK_UTMI1_DIG_TST0 0x00000800 +#define BM_DIGCTL_USB_LOOPBACK_USB0_TST_START 0x00000400 +#define BM_DIGCTL_USB_LOOPBACK_TSTI0_TX_LS 0x00000200 +#define BM_DIGCTL_USB_LOOPBACK_TSTI0_TX_HS 0x00000100 +#define BM_DIGCTL_USB_LOOPBACK_TSTI0_TX_EN 0x00000080 +#define BM_DIGCTL_USB_LOOPBACK_TSTI0_TX_HIZ 0x00000040 +#define BM_DIGCTL_USB_LOOPBACK_UTMI0_DIG_TST1 0x00000020 +#define BM_DIGCTL_USB_LOOPBACK_UTMI0_DIG_TST0 0x00000010 +#define BM_DIGCTL_USB_LOOPBACK_UTMO1_DIG_TST1 0x00000008 +#define BM_DIGCTL_USB_LOOPBACK_UTMO1_DIG_TST0 0x00000004 +#define BM_DIGCTL_USB_LOOPBACK_UTMO0_DIG_TST1 0x00000002 +#define BM_DIGCTL_USB_LOOPBACK_UTMO0_DIG_TST0 0x00000001 + +#define HW_DIGCTL_OCRAM_STATUS0 (0x00000110) +#define HW_DIGCTL_OCRAM_STATUS0_SET (0x00000114) +#define HW_DIGCTL_OCRAM_STATUS0_CLR (0x00000118) +#define HW_DIGCTL_OCRAM_STATUS0_TOG (0x0000011c) + +#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 +#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS1 (0x00000120) +#define HW_DIGCTL_OCRAM_STATUS1_SET (0x00000124) +#define HW_DIGCTL_OCRAM_STATUS1_CLR (0x00000128) +#define HW_DIGCTL_OCRAM_STATUS1_TOG (0x0000012c) + +#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 +#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS2 (0x00000130) +#define HW_DIGCTL_OCRAM_STATUS2_SET (0x00000134) +#define HW_DIGCTL_OCRAM_STATUS2_CLR (0x00000138) +#define HW_DIGCTL_OCRAM_STATUS2_TOG (0x0000013c) + +#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 +#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS3 (0x00000140) +#define HW_DIGCTL_OCRAM_STATUS3_SET (0x00000144) +#define HW_DIGCTL_OCRAM_STATUS3_CLR (0x00000148) +#define HW_DIGCTL_OCRAM_STATUS3_TOG (0x0000014c) + +#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 +#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS4 (0x00000150) +#define HW_DIGCTL_OCRAM_STATUS4_SET (0x00000154) +#define HW_DIGCTL_OCRAM_STATUS4_CLR (0x00000158) +#define HW_DIGCTL_OCRAM_STATUS4_TOG (0x0000015c) + +#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 +#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS5 (0x00000160) +#define HW_DIGCTL_OCRAM_STATUS5_SET (0x00000164) +#define HW_DIGCTL_OCRAM_STATUS5_CLR (0x00000168) +#define HW_DIGCTL_OCRAM_STATUS5_TOG (0x0000016c) + +#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 +#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS6 (0x00000170) +#define HW_DIGCTL_OCRAM_STATUS6_SET (0x00000174) +#define HW_DIGCTL_OCRAM_STATUS6_CLR (0x00000178) +#define HW_DIGCTL_OCRAM_STATUS6_TOG (0x0000017c) + +#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 +#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS7 (0x00000180) +#define HW_DIGCTL_OCRAM_STATUS7_SET (0x00000184) +#define HW_DIGCTL_OCRAM_STATUS7_CLR (0x00000188) +#define HW_DIGCTL_OCRAM_STATUS7_TOG (0x0000018c) + +#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 +#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS8 (0x00000190) +#define HW_DIGCTL_OCRAM_STATUS8_SET (0x00000194) +#define HW_DIGCTL_OCRAM_STATUS8_CLR (0x00000198) +#define HW_DIGCTL_OCRAM_STATUS8_TOG (0x0000019c) + +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0xFFFF0000 +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR01) +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0x0000FFFF +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR00) + +#define HW_DIGCTL_OCRAM_STATUS9 (0x000001a0) +#define HW_DIGCTL_OCRAM_STATUS9_SET (0x000001a4) +#define HW_DIGCTL_OCRAM_STATUS9_CLR (0x000001a8) +#define HW_DIGCTL_OCRAM_STATUS9_TOG (0x000001ac) + +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0xFFFF0000 +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR11) +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0x0000FFFF +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR10) + +#define HW_DIGCTL_OCRAM_STATUS10 (0x000001b0) +#define HW_DIGCTL_OCRAM_STATUS10_SET (0x000001b4) +#define HW_DIGCTL_OCRAM_STATUS10_CLR (0x000001b8) +#define HW_DIGCTL_OCRAM_STATUS10_TOG (0x000001bc) + +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0xFFFF0000 +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR21) +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0x0000FFFF +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR20) + +#define HW_DIGCTL_OCRAM_STATUS11 (0x000001c0) +#define HW_DIGCTL_OCRAM_STATUS11_SET (0x000001c4) +#define HW_DIGCTL_OCRAM_STATUS11_CLR (0x000001c8) +#define HW_DIGCTL_OCRAM_STATUS11_TOG (0x000001cc) + +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0xFFFF0000 +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR31) +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0x0000FFFF +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR30) + +#define HW_DIGCTL_OCRAM_STATUS12 (0x000001d0) +#define HW_DIGCTL_OCRAM_STATUS12_SET (0x000001d4) +#define HW_DIGCTL_OCRAM_STATUS12_CLR (0x000001d8) +#define HW_DIGCTL_OCRAM_STATUS12_TOG (0x000001dc) + +#define BM_DIGCTL_OCRAM_STATUS12_RSVD3 0x80000000 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x7F000000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11) +#define BM_DIGCTL_OCRAM_STATUS12_RSVD2 0x00800000 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x007F0000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10) +#define BM_DIGCTL_OCRAM_STATUS12_RSVD1 0x00008000 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x00007F00 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01) +#define BM_DIGCTL_OCRAM_STATUS12_RSVD0 0x00000080 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x0000007F +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00) + +#define HW_DIGCTL_OCRAM_STATUS13 (0x000001e0) +#define HW_DIGCTL_OCRAM_STATUS13_SET (0x000001e4) +#define HW_DIGCTL_OCRAM_STATUS13_CLR (0x000001e8) +#define HW_DIGCTL_OCRAM_STATUS13_TOG (0x000001ec) + +#define BM_DIGCTL_OCRAM_STATUS13_RSVD3 0x80000000 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x7F000000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31) +#define BM_DIGCTL_OCRAM_STATUS13_RSVD2 0x00800000 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x007F0000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30) +#define BM_DIGCTL_OCRAM_STATUS13_RSVD1 0x00008000 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x00007F00 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21) +#define BM_DIGCTL_OCRAM_STATUS13_RSVD0 0x00000080 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x0000007F +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20) + +#define HW_DIGCTL_SCRATCH0 (0x00000280) + +#define BP_DIGCTL_SCRATCH0_PTR 0 +#define BM_DIGCTL_SCRATCH0_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH0_PTR(v) (v) + +#define HW_DIGCTL_SCRATCH1 (0x00000290) + +#define BP_DIGCTL_SCRATCH1_PTR 0 +#define BM_DIGCTL_SCRATCH1_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH1_PTR(v) (v) + +#define HW_DIGCTL_ARMCACHE (0x000002a0) + +#define BP_DIGCTL_ARMCACHE_RSVD4 18 +#define BM_DIGCTL_ARMCACHE_RSVD4 0xFFFC0000 +#define BF_DIGCTL_ARMCACHE_RSVD4(v) \ + (((v) << 18) & BM_DIGCTL_ARMCACHE_RSVD4) +#define BP_DIGCTL_ARMCACHE_VALID_SS 16 +#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 +#define BF_DIGCTL_ARMCACHE_VALID_SS(v) \ + (((v) << 16) & BM_DIGCTL_ARMCACHE_VALID_SS) +#define BP_DIGCTL_ARMCACHE_RSVD3 14 +#define BM_DIGCTL_ARMCACHE_RSVD3 0x0000C000 +#define BF_DIGCTL_ARMCACHE_RSVD3(v) \ + (((v) << 14) & BM_DIGCTL_ARMCACHE_RSVD3) +#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 +#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 +#define BF_DIGCTL_ARMCACHE_DRTY_SS(v) \ + (((v) << 12) & BM_DIGCTL_ARMCACHE_DRTY_SS) +#define BP_DIGCTL_ARMCACHE_RSVD2 10 +#define BM_DIGCTL_ARMCACHE_RSVD2 0x00000C00 +#define BF_DIGCTL_ARMCACHE_RSVD2(v) \ + (((v) << 10) & BM_DIGCTL_ARMCACHE_RSVD2) +#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 +#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 +#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) \ + (((v) << 8) & BM_DIGCTL_ARMCACHE_CACHE_SS) +#define BP_DIGCTL_ARMCACHE_RSVD1 6 +#define BM_DIGCTL_ARMCACHE_RSVD1 0x000000C0 +#define BF_DIGCTL_ARMCACHE_RSVD1(v) \ + (((v) << 6) & BM_DIGCTL_ARMCACHE_RSVD1) +#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 +#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 +#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) \ + (((v) << 4) & BM_DIGCTL_ARMCACHE_DTAG_SS) +#define BP_DIGCTL_ARMCACHE_RSVD0 2 +#define BM_DIGCTL_ARMCACHE_RSVD0 0x0000000C +#define BF_DIGCTL_ARMCACHE_RSVD0(v) \ + (((v) << 2) & BM_DIGCTL_ARMCACHE_RSVD0) +#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 +#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 +#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) \ + (((v) << 0) & BM_DIGCTL_ARMCACHE_ITAG_SS) + +#define HW_DIGCTL_DEBUG_TRAP (0x000002b0) +#define HW_DIGCTL_DEBUG_TRAP_SET (0x000002b4) +#define HW_DIGCTL_DEBUG_TRAP_CLR (0x000002b8) +#define HW_DIGCTL_DEBUG_TRAP_TOG (0x000002bc) + +#define BP_DIGCTL_DEBUG_TRAP_RSVD2 12 +#define BM_DIGCTL_DEBUG_TRAP_RSVD2 0xFFFFF000 +#define BF_DIGCTL_DEBUG_TRAP_RSVD2(v) \ + (((v) << 12) & BM_DIGCTL_DEBUG_TRAP_RSVD2) +#define BP_DIGCTL_DEBUG_TRAP_RSVD1 10 +#define BM_DIGCTL_DEBUG_TRAP_RSVD1 0x00000C00 +#define BF_DIGCTL_DEBUG_TRAP_RSVD1(v) \ + (((v) << 10) & BM_DIGCTL_DEBUG_TRAP_RSVD1) +#define BP_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID 8 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID 0x00000300 +#define BF_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID(v) \ + (((v) << 8) & BM_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID) +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID__PXP 0x0 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID__LCDIF 0x1 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID__BCH 0x2 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L0_MASTER_ID__DCP 0x3 +#define BM_DIGCTL_DEBUG_TRAP_RSVD0 0x00000080 +#define BP_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID 4 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID 0x00000070 +#define BF_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID(v) \ + (((v) << 4) & BM_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID) +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__APBH_BRIDE_DMA 0x0 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__APBX_BRIDE_DMA 0x1 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__USB0 0x2 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__USB1 0x3 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__ENET_M0 0x4 +#define BV_DIGCTL_DEBUG_TRAP_TRAP_L3_MASTER_ID__ENET_M1 0x5 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_L3_IRQ 0x00000008 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_L0_IRQ 0x00000004 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_IN_RANGE 0x00000002 +#define BM_DIGCTL_DEBUG_TRAP_TRAP_ENABLE 0x00000001 + +#define HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW (0x000002c0) + +#define BP_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH (0x000002d0) + +#define BP_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW (0x000002e0) + +#define BP_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH (0x000002f0) + +#define BP_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH_ADDR(v) (v) + +#define HW_DIGCTL_FSL (0x00000300) + +#define BP_DIGCTL_FSL_COPYRIGHT 0 +#define BM_DIGCTL_FSL_COPYRIGHT 0xFFFFFFFF +#define BF_DIGCTL_FSL_COPYRIGHT(v) (v) + +#define HW_DIGCTL_CHIPID (0x00000310) + +#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 +#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xFFFF0000 +#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) \ + (((v) << 16) & BM_DIGCTL_CHIPID_PRODUCT_CODE) +#define BP_DIGCTL_CHIPID_RSVD0 8 +#define BM_DIGCTL_CHIPID_RSVD0 0x0000FF00 +#define BF_DIGCTL_CHIPID_RSVD0(v) \ + (((v) << 8) & BM_DIGCTL_CHIPID_RSVD0) +#define BP_DIGCTL_CHIPID_REVISION 0 +#define BM_DIGCTL_CHIPID_REVISION 0x000000FF +#define BF_DIGCTL_CHIPID_REVISION(v) \ + (((v) << 0) & BM_DIGCTL_CHIPID_REVISION) + +#define HW_DIGCTL_AHB_STATS_SELECT (0x00000330) + +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0 24 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0 0xFF000000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v) \ + (((v) << 24) & BM_DIGCTL_AHB_STATS_SELECT_RSVD0) +#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 16 +#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0x00FF0000 +#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) \ + (((v) << 16) & BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBHDMA 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBXDMA 0x2 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB0 0x4 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB1 0x8 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__UDMA0 0x10 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__UDMA1 0x20 +#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 8 +#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0x0000FF00 +#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) \ + (((v) << 8) & BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARMD 0x1 +#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0 +#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0x000000FF +#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) \ + (((v) << 0) & BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARMI 0x1 + +#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (0x00000370) + +#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_STALLED (0x00000380) + +#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_CYCLES (0x00000390) + +#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (0x000003a0) + +#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_STALLED (0x000003b0) + +#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_CYCLES (0x000003c0) + +#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (0x000003d0) + +#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_STALLED (0x000003e0) + +#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_CYCLES (0x000003f0) + +#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_MPTE0_LOC (0x00000500) + +#define BM_DIGCTL_MPTE0_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE0_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE0_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE0_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE0_LOC_RSVD1) +#define BP_DIGCTL_MPTE0_LOC_SPAN 24 +#define BM_DIGCTL_MPTE0_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE0_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE0_LOC_SPAN) +#define BP_DIGCTL_MPTE0_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE0_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE0_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE0_LOC_RSVD0) +#define BP_DIGCTL_MPTE0_LOC_LOC 0 +#define BM_DIGCTL_MPTE0_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE0_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE0_LOC_LOC) + +#define HW_DIGCTL_MPTE1_LOC (0x00000510) + +#define BM_DIGCTL_MPTE1_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE1_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE1_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE1_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE1_LOC_RSVD1) +#define BP_DIGCTL_MPTE1_LOC_SPAN 24 +#define BM_DIGCTL_MPTE1_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE1_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE1_LOC_SPAN) +#define BP_DIGCTL_MPTE1_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE1_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE1_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE1_LOC_RSVD0) +#define BP_DIGCTL_MPTE1_LOC_LOC 0 +#define BM_DIGCTL_MPTE1_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE1_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE1_LOC_LOC) + +#define HW_DIGCTL_MPTE2_LOC (0x00000520) + +#define BM_DIGCTL_MPTE2_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE2_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE2_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE2_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE2_LOC_RSVD1) +#define BP_DIGCTL_MPTE2_LOC_SPAN 24 +#define BM_DIGCTL_MPTE2_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE2_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE2_LOC_SPAN) +#define BP_DIGCTL_MPTE2_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE2_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE2_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE2_LOC_RSVD0) +#define BP_DIGCTL_MPTE2_LOC_LOC 0 +#define BM_DIGCTL_MPTE2_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE2_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE2_LOC_LOC) + +#define HW_DIGCTL_MPTE3_LOC (0x00000530) + +#define BM_DIGCTL_MPTE3_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE3_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE3_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE3_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE3_LOC_RSVD1) +#define BP_DIGCTL_MPTE3_LOC_SPAN 24 +#define BM_DIGCTL_MPTE3_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE3_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE3_LOC_SPAN) +#define BP_DIGCTL_MPTE3_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE3_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE3_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE3_LOC_RSVD0) +#define BP_DIGCTL_MPTE3_LOC_LOC 0 +#define BM_DIGCTL_MPTE3_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE3_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE3_LOC_LOC) + +#define HW_DIGCTL_MPTE4_LOC (0x00000540) + +#define BM_DIGCTL_MPTE4_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE4_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE4_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE4_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE4_LOC_RSVD1) +#define BP_DIGCTL_MPTE4_LOC_SPAN 24 +#define BM_DIGCTL_MPTE4_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE4_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE4_LOC_SPAN) +#define BP_DIGCTL_MPTE4_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE4_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE4_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE4_LOC_RSVD0) +#define BP_DIGCTL_MPTE4_LOC_LOC 0 +#define BM_DIGCTL_MPTE4_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE4_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE4_LOC_LOC) + +#define HW_DIGCTL_MPTE5_LOC (0x00000550) + +#define BM_DIGCTL_MPTE5_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE5_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE5_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE5_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE5_LOC_RSVD1) +#define BP_DIGCTL_MPTE5_LOC_SPAN 24 +#define BM_DIGCTL_MPTE5_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE5_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE5_LOC_SPAN) +#define BP_DIGCTL_MPTE5_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE5_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE5_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE5_LOC_RSVD0) +#define BP_DIGCTL_MPTE5_LOC_LOC 0 +#define BM_DIGCTL_MPTE5_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE5_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE5_LOC_LOC) + +#define HW_DIGCTL_MPTE6_LOC (0x00000560) + +#define BM_DIGCTL_MPTE6_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE6_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE6_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE6_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE6_LOC_RSVD1) +#define BP_DIGCTL_MPTE6_LOC_SPAN 24 +#define BM_DIGCTL_MPTE6_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE6_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE6_LOC_SPAN) +#define BP_DIGCTL_MPTE6_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE6_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE6_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE6_LOC_RSVD0) +#define BP_DIGCTL_MPTE6_LOC_LOC 0 +#define BM_DIGCTL_MPTE6_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE6_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE6_LOC_LOC) + +#define HW_DIGCTL_MPTE7_LOC (0x00000570) + +#define BM_DIGCTL_MPTE7_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE7_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE7_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE7_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE7_LOC_RSVD1) +#define BP_DIGCTL_MPTE7_LOC_SPAN 24 +#define BM_DIGCTL_MPTE7_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE7_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE7_LOC_SPAN) +#define BP_DIGCTL_MPTE7_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE7_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE7_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE7_LOC_RSVD0) +#define BP_DIGCTL_MPTE7_LOC_LOC 0 +#define BM_DIGCTL_MPTE7_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE7_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE7_LOC_LOC) + +#define HW_DIGCTL_MPTE8_LOC (0x00000580) + +#define BM_DIGCTL_MPTE8_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE8_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE8_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE8_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE8_LOC_RSVD1) +#define BP_DIGCTL_MPTE8_LOC_SPAN 24 +#define BM_DIGCTL_MPTE8_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE8_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE8_LOC_SPAN) +#define BP_DIGCTL_MPTE8_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE8_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE8_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE8_LOC_RSVD0) +#define BP_DIGCTL_MPTE8_LOC_LOC 0 +#define BM_DIGCTL_MPTE8_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE8_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE8_LOC_LOC) + +#define HW_DIGCTL_MPTE9_LOC (0x00000590) + +#define BM_DIGCTL_MPTE9_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE9_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE9_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE9_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE9_LOC_RSVD1) +#define BP_DIGCTL_MPTE9_LOC_SPAN 24 +#define BM_DIGCTL_MPTE9_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE9_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE9_LOC_SPAN) +#define BP_DIGCTL_MPTE9_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE9_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE9_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE9_LOC_RSVD0) +#define BP_DIGCTL_MPTE9_LOC_LOC 0 +#define BM_DIGCTL_MPTE9_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE9_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE9_LOC_LOC) + +#define HW_DIGCTL_MPTE10_LOC (0x000005a0) + +#define BM_DIGCTL_MPTE10_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE10_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE10_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE10_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE10_LOC_RSVD1) +#define BP_DIGCTL_MPTE10_LOC_SPAN 24 +#define BM_DIGCTL_MPTE10_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE10_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE10_LOC_SPAN) +#define BP_DIGCTL_MPTE10_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE10_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE10_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE10_LOC_RSVD0) +#define BP_DIGCTL_MPTE10_LOC_LOC 0 +#define BM_DIGCTL_MPTE10_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE10_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE10_LOC_LOC) + +#define HW_DIGCTL_MPTE11_LOC (0x000005b0) + +#define BM_DIGCTL_MPTE11_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE11_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE11_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE11_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE11_LOC_RSVD1) +#define BP_DIGCTL_MPTE11_LOC_SPAN 24 +#define BM_DIGCTL_MPTE11_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE11_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE11_LOC_SPAN) +#define BP_DIGCTL_MPTE11_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE11_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE11_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE11_LOC_RSVD0) +#define BP_DIGCTL_MPTE11_LOC_LOC 0 +#define BM_DIGCTL_MPTE11_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE11_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE11_LOC_LOC) + +#define HW_DIGCTL_MPTE12_LOC (0x000005c0) + +#define BM_DIGCTL_MPTE12_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE12_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE12_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE12_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE12_LOC_RSVD1) +#define BP_DIGCTL_MPTE12_LOC_SPAN 24 +#define BM_DIGCTL_MPTE12_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE12_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE12_LOC_SPAN) +#define BP_DIGCTL_MPTE12_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE12_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE12_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE12_LOC_RSVD0) +#define BP_DIGCTL_MPTE12_LOC_LOC 0 +#define BM_DIGCTL_MPTE12_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE12_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE12_LOC_LOC) + +#define HW_DIGCTL_MPTE13_LOC (0x000005d0) + +#define BM_DIGCTL_MPTE13_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE13_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE13_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE13_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE13_LOC_RSVD1) +#define BP_DIGCTL_MPTE13_LOC_SPAN 24 +#define BM_DIGCTL_MPTE13_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE13_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE13_LOC_SPAN) +#define BP_DIGCTL_MPTE13_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE13_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE13_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE13_LOC_RSVD0) +#define BP_DIGCTL_MPTE13_LOC_LOC 0 +#define BM_DIGCTL_MPTE13_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE13_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE13_LOC_LOC) + +#define HW_DIGCTL_MPTE14_LOC (0x000005e0) + +#define BM_DIGCTL_MPTE14_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE14_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE14_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE14_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE14_LOC_RSVD1) +#define BP_DIGCTL_MPTE14_LOC_SPAN 24 +#define BM_DIGCTL_MPTE14_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE14_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE14_LOC_SPAN) +#define BP_DIGCTL_MPTE14_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE14_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE14_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE14_LOC_RSVD0) +#define BP_DIGCTL_MPTE14_LOC_LOC 0 +#define BM_DIGCTL_MPTE14_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE14_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE14_LOC_LOC) + +#define HW_DIGCTL_MPTE15_LOC (0x000005f0) + +#define BM_DIGCTL_MPTE15_LOC_DIS 0x80000000 +#define BP_DIGCTL_MPTE15_LOC_RSVD1 27 +#define BM_DIGCTL_MPTE15_LOC_RSVD1 0x78000000 +#define BF_DIGCTL_MPTE15_LOC_RSVD1(v) \ + (((v) << 27) & BM_DIGCTL_MPTE15_LOC_RSVD1) +#define BP_DIGCTL_MPTE15_LOC_SPAN 24 +#define BM_DIGCTL_MPTE15_LOC_SPAN 0x07000000 +#define BF_DIGCTL_MPTE15_LOC_SPAN(v) \ + (((v) << 24) & BM_DIGCTL_MPTE15_LOC_SPAN) +#define BP_DIGCTL_MPTE15_LOC_RSVD0 12 +#define BM_DIGCTL_MPTE15_LOC_RSVD0 0x00FFF000 +#define BF_DIGCTL_MPTE15_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTE15_LOC_RSVD0) +#define BP_DIGCTL_MPTE15_LOC_LOC 0 +#define BM_DIGCTL_MPTE15_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTE15_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTE15_LOC_LOC) +#endif /* __ARCH_ARM___DIGCTL_H */ diff --git a/arch/arm/mach-mx28/regs-dram.h b/arch/arm/mach-mx28/regs-dram.h new file mode 100644 index 000000000000..ed962a6d5324 --- /dev/null +++ b/arch/arm/mach-mx28/regs-dram.h @@ -0,0 +1,2505 @@ +/* + * Freescale DRAM Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___DRAM_H +#define __ARCH_ARM___DRAM_H + + +#define HW_DRAM_CTL00 (0x00000000) + +#define BP_DRAM_CTL00_USER_DEF_REG_0_1 3 +#define BM_DRAM_CTL00_USER_DEF_REG_0_1 0xFFFFFFF8 +#define BF_DRAM_CTL00_USER_DEF_REG_0_1(v) \ + (((v) << 3) & BM_DRAM_CTL00_USER_DEF_REG_0_1) +#define BM_DRAM_CTL00_CKE_SELECT 0x00000004 +#define BV_DRAM_CTL00_CKE_SELECT__DDR2 0x0 +#define BV_DRAM_CTL00_CKE_SELECT__LPDDR 0x1 +#define BM_DRAM_CTL00_SREFRESH_ENTER 0x00000002 +#define BM_DRAM_CTL00_BRESP_TIMING 0x00000001 +#define BV_DRAM_CTL00_BRESP_TIMING__BUFFERABLE 0x0 +#define BV_DRAM_CTL00_BRESP_TIMING__SEMI_BUFFERABLE 0x1 + +#define HW_DRAM_CTL01 (0x00000004) + +#define BP_DRAM_CTL01_USER_DEF_REG_1 9 +#define BM_DRAM_CTL01_USER_DEF_REG_1 0xFFFFFE00 +#define BF_DRAM_CTL01_USER_DEF_REG_1(v) \ + (((v) << 9) & BM_DRAM_CTL01_USER_DEF_REG_1) +#define BM_DRAM_CTL01_MON_DBG_STB 0x00000100 +#define BP_DRAM_CTL01_SLVERR 4 +#define BM_DRAM_CTL01_SLVERR 0x000000F0 +#define BF_DRAM_CTL01_SLVERR(v) \ + (((v) << 4) & BM_DRAM_CTL01_SLVERR) +#define BP_DRAM_CTL01_MON_DISABLE 0 +#define BM_DRAM_CTL01_MON_DISABLE 0x0000000F +#define BF_DRAM_CTL01_MON_DISABLE(v) \ + (((v) << 0) & BM_DRAM_CTL01_MON_DISABLE) + +#define HW_DRAM_CTL02 (0x00000008) + +#define BP_DRAM_CTL02_USER_DEF_REG_2 0 +#define BM_DRAM_CTL02_USER_DEF_REG_2 0xFFFFFFFF +#define BF_DRAM_CTL02_USER_DEF_REG_2(v) (v) + +#define HW_DRAM_CTL03 (0x0000000c) + +#define BP_DRAM_CTL03_USER_DEF_REG_3 0 +#define BM_DRAM_CTL03_USER_DEF_REG_3 0xFFFFFFFF +#define BF_DRAM_CTL03_USER_DEF_REG_3(v) (v) + +#define HW_DRAM_CTL04 (0x00000010) + +#define BP_DRAM_CTL04_USER_DEF_REG_4 0 +#define BM_DRAM_CTL04_USER_DEF_REG_4 0xFFFFFFFF +#define BF_DRAM_CTL04_USER_DEF_REG_4(v) (v) + +#define HW_DRAM_CTL05 (0x00000014) + +#define BP_DRAM_CTL05_USER_DEF_REG_5 0 +#define BM_DRAM_CTL05_USER_DEF_REG_5 0xFFFFFFFF +#define BF_DRAM_CTL05_USER_DEF_REG_5(v) (v) + +#define HW_DRAM_CTL06 (0x00000018) + +#define BP_DRAM_CTL06_USER_DEF_REG_6 0 +#define BM_DRAM_CTL06_USER_DEF_REG_6 0xFFFFFFFF +#define BF_DRAM_CTL06_USER_DEF_REG_6(v) (v) + +#define HW_DRAM_CTL07 (0x0000001c) + +#define BP_DRAM_CTL07_USER_DEF_REG_7 0 +#define BM_DRAM_CTL07_USER_DEF_REG_7 0xFFFFFFFF +#define BF_DRAM_CTL07_USER_DEF_REG_7(v) (v) + +#define HW_DRAM_CTL08 (0x00000020) + +#define BP_DRAM_CTL08_USER_DEF_REG_RO_0 9 +#define BM_DRAM_CTL08_USER_DEF_REG_RO_0 0xFFFFFE00 +#define BF_DRAM_CTL08_USER_DEF_REG_RO_0(v) \ + (((v) << 9) & BM_DRAM_CTL08_USER_DEF_REG_RO_0) +#define BM_DRAM_CTL08_CONTROLLER_BUSY 0x00000100 +#define BM_DRAM_CTL08_REFRESH_IN_PROCESS 0x00000080 +#define BM_DRAM_CTL08_Q_ALMOST_FULL 0x00000040 +#define BM_DRAM_CTL08_SREFRESH_ACK 0x00000020 +#define BM_DRAM_CTL08_CKE_STATUS 0x00000010 +#define BP_DRAM_CTL08_COMMAND_ACCEPTED 0 +#define BM_DRAM_CTL08_COMMAND_ACCEPTED 0x0000000F +#define BF_DRAM_CTL08_COMMAND_ACCEPTED(v) \ + (((v) << 0) & BM_DRAM_CTL08_COMMAND_ACCEPTED) + +#define HW_DRAM_CTL09 (0x00000024) + +#define BP_DRAM_CTL09_USER_DEF_REG_RO_1 0 +#define BM_DRAM_CTL09_USER_DEF_REG_RO_1 0xFFFFFFFF +#define BF_DRAM_CTL09_USER_DEF_REG_RO_1(v) (v) + +#define HW_DRAM_CTL10 (0x00000028) + +#define BP_DRAM_CTL10_RSVD 24 +#define BM_DRAM_CTL10_RSVD 0xFF000000 +#define BF_DRAM_CTL10_RSVD(v) \ + (((v) << 24) & BM_DRAM_CTL10_RSVD) +#define BP_DRAM_CTL10_READ_CNT 16 +#define BM_DRAM_CTL10_READ_CNT 0x00FF0000 +#define BF_DRAM_CTL10_READ_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL10_READ_CNT) +#define BP_DRAM_CTL10_WRESP_CNT 8 +#define BM_DRAM_CTL10_WRESP_CNT 0x0000FF00 +#define BF_DRAM_CTL10_WRESP_CNT(v) \ + (((v) << 8) & BM_DRAM_CTL10_WRESP_CNT) +#define BP_DRAM_CTL10_WDATA_CNT 0 +#define BM_DRAM_CTL10_WDATA_CNT 0x000000FF +#define BF_DRAM_CTL10_WDATA_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL10_WDATA_CNT) + +#define HW_DRAM_CTL11 (0x0000002c) + +#define BP_DRAM_CTL11_WSTATE 24 +#define BM_DRAM_CTL11_WSTATE 0xFF000000 +#define BF_DRAM_CTL11_WSTATE(v) \ + (((v) << 24) & BM_DRAM_CTL11_WSTATE) +#define BP_DRAM_CTL11_RSTATE 16 +#define BM_DRAM_CTL11_RSTATE 0x00FF0000 +#define BF_DRAM_CTL11_RSTATE(v) \ + (((v) << 16) & BM_DRAM_CTL11_RSTATE) +#define BP_DRAM_CTL11_RLEN 8 +#define BM_DRAM_CTL11_RLEN 0x0000FF00 +#define BF_DRAM_CTL11_RLEN(v) \ + (((v) << 8) & BM_DRAM_CTL11_RLEN) +#define BP_DRAM_CTL11_WLEN 0 +#define BM_DRAM_CTL11_WLEN 0x000000FF +#define BF_DRAM_CTL11_WLEN(v) \ + (((v) << 0) & BM_DRAM_CTL11_WLEN) + +#define HW_DRAM_CTL12 (0x00000030) + +#define BP_DRAM_CTL12_RSVD 24 +#define BM_DRAM_CTL12_RSVD 0xFF000000 +#define BF_DRAM_CTL12_RSVD(v) \ + (((v) << 24) & BM_DRAM_CTL12_RSVD) +#define BP_DRAM_CTL12_READ_CNT 16 +#define BM_DRAM_CTL12_READ_CNT 0x00FF0000 +#define BF_DRAM_CTL12_READ_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL12_READ_CNT) +#define BP_DRAM_CTL12_WRESP_CNT 8 +#define BM_DRAM_CTL12_WRESP_CNT 0x0000FF00 +#define BF_DRAM_CTL12_WRESP_CNT(v) \ + (((v) << 8) & BM_DRAM_CTL12_WRESP_CNT) +#define BP_DRAM_CTL12_WDATA_CNT 0 +#define BM_DRAM_CTL12_WDATA_CNT 0x000000FF +#define BF_DRAM_CTL12_WDATA_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL12_WDATA_CNT) + +#define HW_DRAM_CTL13 (0x00000034) + +#define BP_DRAM_CTL13_WSTATE 24 +#define BM_DRAM_CTL13_WSTATE 0xFF000000 +#define BF_DRAM_CTL13_WSTATE(v) \ + (((v) << 24) & BM_DRAM_CTL13_WSTATE) +#define BP_DRAM_CTL13_RSTATE 16 +#define BM_DRAM_CTL13_RSTATE 0x00FF0000 +#define BF_DRAM_CTL13_RSTATE(v) \ + (((v) << 16) & BM_DRAM_CTL13_RSTATE) +#define BP_DRAM_CTL13_RLEN 8 +#define BM_DRAM_CTL13_RLEN 0x0000FF00 +#define BF_DRAM_CTL13_RLEN(v) \ + (((v) << 8) & BM_DRAM_CTL13_RLEN) +#define BP_DRAM_CTL13_WLEN 0 +#define BM_DRAM_CTL13_WLEN 0x000000FF +#define BF_DRAM_CTL13_WLEN(v) \ + (((v) << 0) & BM_DRAM_CTL13_WLEN) + +#define HW_DRAM_CTL14 (0x00000038) + +#define BP_DRAM_CTL14_RSVD 24 +#define BM_DRAM_CTL14_RSVD 0xFF000000 +#define BF_DRAM_CTL14_RSVD(v) \ + (((v) << 24) & BM_DRAM_CTL14_RSVD) +#define BP_DRAM_CTL14_READ_CNT 16 +#define BM_DRAM_CTL14_READ_CNT 0x00FF0000 +#define BF_DRAM_CTL14_READ_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL14_READ_CNT) +#define BP_DRAM_CTL14_WRESP_CNT 8 +#define BM_DRAM_CTL14_WRESP_CNT 0x0000FF00 +#define BF_DRAM_CTL14_WRESP_CNT(v) \ + (((v) << 8) & BM_DRAM_CTL14_WRESP_CNT) +#define BP_DRAM_CTL14_WDATA_CNT 0 +#define BM_DRAM_CTL14_WDATA_CNT 0x000000FF +#define BF_DRAM_CTL14_WDATA_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL14_WDATA_CNT) + +#define HW_DRAM_CTL15 (0x0000003c) + +#define BP_DRAM_CTL15_WSTATE 24 +#define BM_DRAM_CTL15_WSTATE 0xFF000000 +#define BF_DRAM_CTL15_WSTATE(v) \ + (((v) << 24) & BM_DRAM_CTL15_WSTATE) +#define BP_DRAM_CTL15_RSTATE 16 +#define BM_DRAM_CTL15_RSTATE 0x00FF0000 +#define BF_DRAM_CTL15_RSTATE(v) \ + (((v) << 16) & BM_DRAM_CTL15_RSTATE) +#define BP_DRAM_CTL15_RLEN 8 +#define BM_DRAM_CTL15_RLEN 0x0000FF00 +#define BF_DRAM_CTL15_RLEN(v) \ + (((v) << 8) & BM_DRAM_CTL15_RLEN) +#define BP_DRAM_CTL15_WLEN 0 +#define BM_DRAM_CTL15_WLEN 0x000000FF +#define BF_DRAM_CTL15_WLEN(v) \ + (((v) << 0) & BM_DRAM_CTL15_WLEN) + +#define HW_DRAM_CTL16 (0x00000040) + +#define BP_DRAM_CTL16_RSVD3 25 +#define BM_DRAM_CTL16_RSVD3 0xFE000000 +#define BF_DRAM_CTL16_RSVD3(v) \ + (((v) << 25) & BM_DRAM_CTL16_RSVD3) +#define BM_DRAM_CTL16_WRITE_MODEREG 0x01000000 +#define BP_DRAM_CTL16_RSVD2 17 +#define BM_DRAM_CTL16_RSVD2 0x00FE0000 +#define BF_DRAM_CTL16_RSVD2(v) \ + (((v) << 17) & BM_DRAM_CTL16_RSVD2) +#define BM_DRAM_CTL16_POWER_DOWN 0x00010000 +#define BP_DRAM_CTL16_OBSOLETE 8 +#define BM_DRAM_CTL16_OBSOLETE 0x0000FF00 +#define BF_DRAM_CTL16_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL16_OBSOLETE) +#define BP_DRAM_CTL16_RSVD1 1 +#define BM_DRAM_CTL16_RSVD1 0x000000FE +#define BF_DRAM_CTL16_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL16_RSVD1) +#define BM_DRAM_CTL16_START 0x00000001 + +#define HW_DRAM_CTL17 (0x00000044) + +#define BP_DRAM_CTL17_RSVD4 25 +#define BM_DRAM_CTL17_RSVD4 0xFE000000 +#define BF_DRAM_CTL17_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL17_RSVD4) +#define BM_DRAM_CTL17_AUTO_REFRESH_MODE 0x01000000 +#define BP_DRAM_CTL17_RSVD3 17 +#define BM_DRAM_CTL17_RSVD3 0x00FE0000 +#define BF_DRAM_CTL17_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL17_RSVD3) +#define BM_DRAM_CTL17_AREFRESH 0x00010000 +#define BP_DRAM_CTL17_RSVD2 9 +#define BM_DRAM_CTL17_RSVD2 0x0000FE00 +#define BF_DRAM_CTL17_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL17_RSVD2) +#define BM_DRAM_CTL17_ENABLE_QUICK_SREFRESH 0x00000100 +#define BP_DRAM_CTL17_RSVD1 1 +#define BM_DRAM_CTL17_RSVD1 0x000000FE +#define BF_DRAM_CTL17_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL17_RSVD1) +#define BM_DRAM_CTL17_SREFRESH 0x00000001 + +#define HW_DRAM_CTL21 (0x00000054) + +#define BP_DRAM_CTL21_RSVD3 27 +#define BM_DRAM_CTL21_RSVD3 0xF8000000 +#define BF_DRAM_CTL21_RSVD3(v) \ + (((v) << 27) & BM_DRAM_CTL21_RSVD3) +#define BP_DRAM_CTL21_CKE_DELAY 24 +#define BM_DRAM_CTL21_CKE_DELAY 0x07000000 +#define BF_DRAM_CTL21_CKE_DELAY(v) \ + (((v) << 24) & BM_DRAM_CTL21_CKE_DELAY) +#define BP_DRAM_CTL21_DLL_LOCK 16 +#define BM_DRAM_CTL21_DLL_LOCK 0x00FF0000 +#define BF_DRAM_CTL21_DLL_LOCK(v) \ + (((v) << 16) & BM_DRAM_CTL21_DLL_LOCK) +#define BP_DRAM_CTL21_RSVD2 9 +#define BM_DRAM_CTL21_RSVD2 0x0000FE00 +#define BF_DRAM_CTL21_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL21_RSVD2) +#define BM_DRAM_CTL21_DLLLOCKREG 0x00000100 +#define BP_DRAM_CTL21_RSVD1 1 +#define BM_DRAM_CTL21_RSVD1 0x000000FE +#define BF_DRAM_CTL21_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL21_RSVD1) +#define BM_DRAM_CTL21_DLL_BYPASS_MODE 0x00000001 + +#define HW_DRAM_CTL22 (0x00000058) + +#define BP_DRAM_CTL22_OBSOLETE 24 +#define BM_DRAM_CTL22_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL22_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL22_OBSOLETE) +#define BP_DRAM_CTL22_RSVD3 20 +#define BM_DRAM_CTL22_RSVD3 0x00F00000 +#define BF_DRAM_CTL22_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL22_RSVD3) +#define BP_DRAM_CTL22_LOWPOWER_REFRESH_ENABLE 16 +#define BM_DRAM_CTL22_LOWPOWER_REFRESH_ENABLE 0x000F0000 +#define BF_DRAM_CTL22_LOWPOWER_REFRESH_ENABLE(v) \ + (((v) << 16) & BM_DRAM_CTL22_LOWPOWER_REFRESH_ENABLE) +#define BP_DRAM_CTL22_RSVD2 13 +#define BM_DRAM_CTL22_RSVD2 0x0000E000 +#define BF_DRAM_CTL22_RSVD2(v) \ + (((v) << 13) & BM_DRAM_CTL22_RSVD2) +#define BP_DRAM_CTL22_LOWPOWER_CONTROL 8 +#define BM_DRAM_CTL22_LOWPOWER_CONTROL 0x00001F00 +#define BF_DRAM_CTL22_LOWPOWER_CONTROL(v) \ + (((v) << 8) & BM_DRAM_CTL22_LOWPOWER_CONTROL) +#define BP_DRAM_CTL22_RSVD1 5 +#define BM_DRAM_CTL22_RSVD1 0x000000E0 +#define BF_DRAM_CTL22_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL22_RSVD1) +#define BP_DRAM_CTL22_LOWPOWER_AUTO_ENABLE 0 +#define BM_DRAM_CTL22_LOWPOWER_AUTO_ENABLE 0x0000001F +#define BF_DRAM_CTL22_LOWPOWER_AUTO_ENABLE(v) \ + (((v) << 0) & BM_DRAM_CTL22_LOWPOWER_AUTO_ENABLE) + +#define HW_DRAM_CTL23 (0x0000005c) + +#define BP_DRAM_CTL23_LOWPOWER_INTERNAL_CNT 16 +#define BM_DRAM_CTL23_LOWPOWER_INTERNAL_CNT 0xFFFF0000 +#define BF_DRAM_CTL23_LOWPOWER_INTERNAL_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL23_LOWPOWER_INTERNAL_CNT) +#define BP_DRAM_CTL23_LOWPOWER_EXTERNAL_CNT 0 +#define BM_DRAM_CTL23_LOWPOWER_EXTERNAL_CNT 0x0000FFFF +#define BF_DRAM_CTL23_LOWPOWER_EXTERNAL_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL23_LOWPOWER_EXTERNAL_CNT) + +#define HW_DRAM_CTL24 (0x00000060) + +#define BP_DRAM_CTL24_LOWPOWER_SELF_REFRESH_CNT 16 +#define BM_DRAM_CTL24_LOWPOWER_SELF_REFRESH_CNT 0xFFFF0000 +#define BF_DRAM_CTL24_LOWPOWER_SELF_REFRESH_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL24_LOWPOWER_SELF_REFRESH_CNT) +#define BP_DRAM_CTL24_LOWPOWER_REFRESH_HOLD 0 +#define BM_DRAM_CTL24_LOWPOWER_REFRESH_HOLD 0x0000FFFF +#define BF_DRAM_CTL24_LOWPOWER_REFRESH_HOLD(v) \ + (((v) << 0) & BM_DRAM_CTL24_LOWPOWER_REFRESH_HOLD) + +#define HW_DRAM_CTL25 (0x00000064) + +#define BP_DRAM_CTL25_OBSOLETE 16 +#define BM_DRAM_CTL25_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL25_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL25_OBSOLETE) +#define BP_DRAM_CTL25_LOWPOWER_POWER_DOWN_CNT 0 +#define BM_DRAM_CTL25_LOWPOWER_POWER_DOWN_CNT 0x0000FFFF +#define BF_DRAM_CTL25_LOWPOWER_POWER_DOWN_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL25_LOWPOWER_POWER_DOWN_CNT) + +#define HW_DRAM_CTL26 (0x00000068) + +#define BP_DRAM_CTL26_OBSOLETE 24 +#define BM_DRAM_CTL26_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL26_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL26_OBSOLETE) +#define BP_DRAM_CTL26_RSVD3 17 +#define BM_DRAM_CTL26_RSVD3 0x00FE0000 +#define BF_DRAM_CTL26_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL26_RSVD3) +#define BM_DRAM_CTL26_PRIORITY_EN 0x00010000 +#define BP_DRAM_CTL26_RSVD2 9 +#define BM_DRAM_CTL26_RSVD2 0x0000FE00 +#define BF_DRAM_CTL26_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL26_RSVD2) +#define BM_DRAM_CTL26_ADDR_CMP_EN 0x00000100 +#define BP_DRAM_CTL26_RSVD1 1 +#define BM_DRAM_CTL26_RSVD1 0x000000FE +#define BF_DRAM_CTL26_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL26_RSVD1) +#define BM_DRAM_CTL26_PLACEMENT_EN 0x00000001 + +#define HW_DRAM_CTL27 (0x0000006c) + +#define BP_DRAM_CTL27_RSVD4 25 +#define BM_DRAM_CTL27_RSVD4 0xFE000000 +#define BF_DRAM_CTL27_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL27_RSVD4) +#define BM_DRAM_CTL27_SWAP_PORT_RW_SAME_EN 0x01000000 +#define BP_DRAM_CTL27_RSVD3 17 +#define BM_DRAM_CTL27_RSVD3 0x00FE0000 +#define BF_DRAM_CTL27_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL27_RSVD3) +#define BM_DRAM_CTL27_SWAP_EN 0x00010000 +#define BP_DRAM_CTL27_RSVD2 9 +#define BM_DRAM_CTL27_RSVD2 0x0000FE00 +#define BF_DRAM_CTL27_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL27_RSVD2) +#define BM_DRAM_CTL27_BANK_SPLIT_EN 0x00000100 +#define BP_DRAM_CTL27_RSVD1 1 +#define BM_DRAM_CTL27_RSVD1 0x000000FE +#define BF_DRAM_CTL27_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL27_RSVD1) +#define BM_DRAM_CTL27_RW_SAME_EN 0x00000001 + +#define HW_DRAM_CTL28 (0x00000070) + +#define BP_DRAM_CTL28_RSVD4 27 +#define BM_DRAM_CTL28_RSVD4 0xF8000000 +#define BF_DRAM_CTL28_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL28_RSVD4) +#define BP_DRAM_CTL28_Q_FULLNESS 24 +#define BM_DRAM_CTL28_Q_FULLNESS 0x07000000 +#define BF_DRAM_CTL28_Q_FULLNESS(v) \ + (((v) << 24) & BM_DRAM_CTL28_Q_FULLNESS) +#define BP_DRAM_CTL28_RSVD3 20 +#define BM_DRAM_CTL28_RSVD3 0x00F00000 +#define BF_DRAM_CTL28_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL28_RSVD3) +#define BP_DRAM_CTL28_AGE_COUNT 16 +#define BM_DRAM_CTL28_AGE_COUNT 0x000F0000 +#define BF_DRAM_CTL28_AGE_COUNT(v) \ + (((v) << 16) & BM_DRAM_CTL28_AGE_COUNT) +#define BP_DRAM_CTL28_RSVD2 12 +#define BM_DRAM_CTL28_RSVD2 0x0000F000 +#define BF_DRAM_CTL28_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL28_RSVD2) +#define BP_DRAM_CTL28_COMMAND_AGE_COUNT 8 +#define BM_DRAM_CTL28_COMMAND_AGE_COUNT 0x00000F00 +#define BF_DRAM_CTL28_COMMAND_AGE_COUNT(v) \ + (((v) << 8) & BM_DRAM_CTL28_COMMAND_AGE_COUNT) +#define BP_DRAM_CTL28_RSVD1 1 +#define BM_DRAM_CTL28_RSVD1 0x000000FE +#define BF_DRAM_CTL28_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL28_RSVD1) +#define BM_DRAM_CTL28_ACTIVE_AGING 0x00000001 + +#define HW_DRAM_CTL29 (0x00000074) + +#define BP_DRAM_CTL29_RSVD4 28 +#define BM_DRAM_CTL29_RSVD4 0xF0000000 +#define BF_DRAM_CTL29_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL29_RSVD4) +#define BP_DRAM_CTL29_CS_MAP 24 +#define BM_DRAM_CTL29_CS_MAP 0x0F000000 +#define BF_DRAM_CTL29_CS_MAP(v) \ + (((v) << 24) & BM_DRAM_CTL29_CS_MAP) +#define BP_DRAM_CTL29_RSVD3 19 +#define BM_DRAM_CTL29_RSVD3 0x00F80000 +#define BF_DRAM_CTL29_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL29_RSVD3) +#define BP_DRAM_CTL29_COLUMN_SIZE 16 +#define BM_DRAM_CTL29_COLUMN_SIZE 0x00070000 +#define BF_DRAM_CTL29_COLUMN_SIZE(v) \ + (((v) << 16) & BM_DRAM_CTL29_COLUMN_SIZE) +#define BP_DRAM_CTL29_RSVD2 11 +#define BM_DRAM_CTL29_RSVD2 0x0000F800 +#define BF_DRAM_CTL29_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL29_RSVD2) +#define BP_DRAM_CTL29_ADDR_PINS 8 +#define BM_DRAM_CTL29_ADDR_PINS 0x00000700 +#define BF_DRAM_CTL29_ADDR_PINS(v) \ + (((v) << 8) & BM_DRAM_CTL29_ADDR_PINS) +#define BP_DRAM_CTL29_RSVD1 4 +#define BM_DRAM_CTL29_RSVD1 0x000000F0 +#define BF_DRAM_CTL29_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL29_RSVD1) +#define BP_DRAM_CTL29_APREBIT 0 +#define BM_DRAM_CTL29_APREBIT 0x0000000F +#define BF_DRAM_CTL29_APREBIT(v) \ + (((v) << 0) & BM_DRAM_CTL29_APREBIT) + +#define HW_DRAM_CTL30 (0x00000078) + +#define BP_DRAM_CTL30_OBSOLETE 24 +#define BM_DRAM_CTL30_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL30_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL30_OBSOLETE) +#define BP_DRAM_CTL30_RSVD3 19 +#define BM_DRAM_CTL30_RSVD3 0x00F80000 +#define BF_DRAM_CTL30_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL30_RSVD3) +#define BP_DRAM_CTL30_MAX_CS_REG 16 +#define BM_DRAM_CTL30_MAX_CS_REG 0x00070000 +#define BF_DRAM_CTL30_MAX_CS_REG(v) \ + (((v) << 16) & BM_DRAM_CTL30_MAX_CS_REG) +#define BP_DRAM_CTL30_RSVD2 12 +#define BM_DRAM_CTL30_RSVD2 0x0000F000 +#define BF_DRAM_CTL30_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL30_RSVD2) +#define BP_DRAM_CTL30_MAX_ROW_REG 8 +#define BM_DRAM_CTL30_MAX_ROW_REG 0x00000F00 +#define BF_DRAM_CTL30_MAX_ROW_REG(v) \ + (((v) << 8) & BM_DRAM_CTL30_MAX_ROW_REG) +#define BP_DRAM_CTL30_RSVD1 4 +#define BM_DRAM_CTL30_RSVD1 0x000000F0 +#define BF_DRAM_CTL30_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL30_RSVD1) +#define BP_DRAM_CTL30_MAX_COL_REG 0 +#define BM_DRAM_CTL30_MAX_COL_REG 0x0000000F +#define BF_DRAM_CTL30_MAX_COL_REG(v) \ + (((v) << 0) & BM_DRAM_CTL30_MAX_COL_REG) + +#define HW_DRAM_CTL31 (0x0000007c) + +#define BP_DRAM_CTL31_OBSOLETE 24 +#define BM_DRAM_CTL31_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL31_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL31_OBSOLETE) +#define BP_DRAM_CTL31_RSVD3 17 +#define BM_DRAM_CTL31_RSVD3 0x00FE0000 +#define BF_DRAM_CTL31_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL31_RSVD3) +#define BM_DRAM_CTL31_EIGHT_BANK_MODE 0x00010000 +#define BP_DRAM_CTL31_RSVD2 9 +#define BM_DRAM_CTL31_RSVD2 0x0000FE00 +#define BF_DRAM_CTL31_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL31_RSVD2) +#define BM_DRAM_CTL31_DRIVE_DQ_DQS 0x00000100 +#define BP_DRAM_CTL31_RSVD1 1 +#define BM_DRAM_CTL31_RSVD1 0x000000FE +#define BF_DRAM_CTL31_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL31_RSVD1) +#define BM_DRAM_CTL31_DQS_N_EN 0x00000001 + +#define HW_DRAM_CTL32 (0x00000080) + +#define BP_DRAM_CTL32_OBSOLETE 16 +#define BM_DRAM_CTL32_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL32_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL32_OBSOLETE) +#define BP_DRAM_CTL32_RSVD2 9 +#define BM_DRAM_CTL32_RSVD2 0x0000FE00 +#define BF_DRAM_CTL32_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL32_RSVD2) +#define BM_DRAM_CTL32_REDUC 0x00000100 +#define BP_DRAM_CTL32_RSVD1 1 +#define BM_DRAM_CTL32_RSVD1 0x000000FE +#define BF_DRAM_CTL32_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL32_RSVD1) +#define BM_DRAM_CTL32_REG_DIMM_ENABLE 0x00000001 + +#define HW_DRAM_CTL33 (0x00000084) + +#define BP_DRAM_CTL33_OBSOLETE 16 +#define BM_DRAM_CTL33_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL33_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL33_OBSOLETE) +#define BP_DRAM_CTL33_RSVD2 9 +#define BM_DRAM_CTL33_RSVD2 0x0000FE00 +#define BF_DRAM_CTL33_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL33_RSVD2) +#define BM_DRAM_CTL33_CONCURRENTAP 0x00000100 +#define BP_DRAM_CTL33_RSVD1 1 +#define BM_DRAM_CTL33_RSVD1 0x000000FE +#define BF_DRAM_CTL33_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL33_RSVD1) +#define BM_DRAM_CTL33_AP 0x00000001 + +#define HW_DRAM_CTL34 (0x00000088) + +#define BP_DRAM_CTL34_RSVD4 25 +#define BM_DRAM_CTL34_RSVD4 0xFE000000 +#define BF_DRAM_CTL34_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL34_RSVD4) +#define BM_DRAM_CTL34_WRITEINTERP 0x01000000 +#define BP_DRAM_CTL34_RSVD3 17 +#define BM_DRAM_CTL34_RSVD3 0x00FE0000 +#define BF_DRAM_CTL34_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL34_RSVD3) +#define BM_DRAM_CTL34_INTRPTWRITEA 0x00010000 +#define BP_DRAM_CTL34_RSVD2 9 +#define BM_DRAM_CTL34_RSVD2 0x0000FE00 +#define BF_DRAM_CTL34_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL34_RSVD2) +#define BM_DRAM_CTL34_INTRPTREADA 0x00000100 +#define BP_DRAM_CTL34_RSVD1 1 +#define BM_DRAM_CTL34_RSVD1 0x000000FE +#define BF_DRAM_CTL34_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL34_RSVD1) +#define BM_DRAM_CTL34_INTRPTAPBURST 0x00000001 + +#define HW_DRAM_CTL35 (0x0000008c) + +#define BP_DRAM_CTL35_OBSOLETE 24 +#define BM_DRAM_CTL35_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL35_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL35_OBSOLETE) +#define BP_DRAM_CTL35_RSVD3 17 +#define BM_DRAM_CTL35_RSVD3 0x00FE0000 +#define BF_DRAM_CTL35_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL35_RSVD3) +#define BM_DRAM_CTL35_PWRUP_SREFRESH_EXIT 0x00010000 +#define BP_DRAM_CTL35_RSVD2 9 +#define BM_DRAM_CTL35_RSVD2 0x0000FE00 +#define BF_DRAM_CTL35_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL35_RSVD2) +#define BM_DRAM_CTL35_NO_CMD_INIT 0x00000100 +#define BP_DRAM_CTL35_RSVD1 4 +#define BM_DRAM_CTL35_RSVD1 0x000000F0 +#define BF_DRAM_CTL35_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL35_RSVD1) +#define BP_DRAM_CTL35_INITAREF 0 +#define BM_DRAM_CTL35_INITAREF 0x0000000F +#define BF_DRAM_CTL35_INITAREF(v) \ + (((v) << 0) & BM_DRAM_CTL35_INITAREF) + +#define HW_DRAM_CTL36 (0x00000090) + +#define BP_DRAM_CTL36_RSVD3 25 +#define BM_DRAM_CTL36_RSVD3 0xFE000000 +#define BF_DRAM_CTL36_RSVD3(v) \ + (((v) << 25) & BM_DRAM_CTL36_RSVD3) +#define BM_DRAM_CTL36_TREF_ENABLE 0x01000000 +#define BP_DRAM_CTL36_RSVD2 17 +#define BM_DRAM_CTL36_RSVD2 0x00FE0000 +#define BF_DRAM_CTL36_RSVD2(v) \ + (((v) << 17) & BM_DRAM_CTL36_RSVD2) +#define BM_DRAM_CTL36_TRAS_LOCKOUT 0x00010000 +#define BP_DRAM_CTL36_OBSOLETE 8 +#define BM_DRAM_CTL36_OBSOLETE 0x0000FF00 +#define BF_DRAM_CTL36_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL36_OBSOLETE) +#define BP_DRAM_CTL36_RSVD1 1 +#define BM_DRAM_CTL36_RSVD1 0x000000FE +#define BF_DRAM_CTL36_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL36_RSVD1) +#define BM_DRAM_CTL36_FAST_WRITE 0x00000001 + +#define HW_DRAM_CTL37 (0x00000094) + +#define BP_DRAM_CTL37_RSVD4 28 +#define BM_DRAM_CTL37_RSVD4 0xF0000000 +#define BF_DRAM_CTL37_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL37_RSVD4) +#define BP_DRAM_CTL37_CASLAT_LIN_GATE 24 +#define BM_DRAM_CTL37_CASLAT_LIN_GATE 0x0F000000 +#define BF_DRAM_CTL37_CASLAT_LIN_GATE(v) \ + (((v) << 24) & BM_DRAM_CTL37_CASLAT_LIN_GATE) +#define BP_DRAM_CTL37_RSVD3 20 +#define BM_DRAM_CTL37_RSVD3 0x00F00000 +#define BF_DRAM_CTL37_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL37_RSVD3) +#define BP_DRAM_CTL37_CASLAT_LIN 16 +#define BM_DRAM_CTL37_CASLAT_LIN 0x000F0000 +#define BF_DRAM_CTL37_CASLAT_LIN(v) \ + (((v) << 16) & BM_DRAM_CTL37_CASLAT_LIN) +#define BP_DRAM_CTL37_RSVD2 11 +#define BM_DRAM_CTL37_RSVD2 0x0000F800 +#define BF_DRAM_CTL37_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL37_RSVD2) +#define BP_DRAM_CTL37_CASLAT 8 +#define BM_DRAM_CTL37_CASLAT 0x00000700 +#define BF_DRAM_CTL37_CASLAT(v) \ + (((v) << 8) & BM_DRAM_CTL37_CASLAT) +#define BP_DRAM_CTL37_RSVD1 4 +#define BM_DRAM_CTL37_RSVD1 0x000000F0 +#define BF_DRAM_CTL37_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL37_RSVD1) +#define BP_DRAM_CTL37_WRLAT 0 +#define BM_DRAM_CTL37_WRLAT 0x0000000F +#define BF_DRAM_CTL37_WRLAT(v) \ + (((v) << 0) & BM_DRAM_CTL37_WRLAT) + +#define HW_DRAM_CTL38 (0x00000098) + +#define BP_DRAM_CTL38_RSVD2 29 +#define BM_DRAM_CTL38_RSVD2 0xE0000000 +#define BF_DRAM_CTL38_RSVD2(v) \ + (((v) << 29) & BM_DRAM_CTL38_RSVD2) +#define BP_DRAM_CTL38_TDAL 24 +#define BM_DRAM_CTL38_TDAL 0x1F000000 +#define BF_DRAM_CTL38_TDAL(v) \ + (((v) << 24) & BM_DRAM_CTL38_TDAL) +#define BP_DRAM_CTL38_TCPD 8 +#define BM_DRAM_CTL38_TCPD 0x00FFFF00 +#define BF_DRAM_CTL38_TCPD(v) \ + (((v) << 8) & BM_DRAM_CTL38_TCPD) +#define BP_DRAM_CTL38_RSVD1 3 +#define BM_DRAM_CTL38_RSVD1 0x000000F8 +#define BF_DRAM_CTL38_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL38_RSVD1) +#define BP_DRAM_CTL38_TCKE 0 +#define BM_DRAM_CTL38_TCKE 0x00000007 +#define BF_DRAM_CTL38_TCKE(v) \ + (((v) << 0) & BM_DRAM_CTL38_TCKE) + +#define HW_DRAM_CTL39 (0x0000009c) + +#define BP_DRAM_CTL39_RSVD1 30 +#define BM_DRAM_CTL39_RSVD1 0xC0000000 +#define BF_DRAM_CTL39_RSVD1(v) \ + (((v) << 30) & BM_DRAM_CTL39_RSVD1) +#define BP_DRAM_CTL39_TFAW 24 +#define BM_DRAM_CTL39_TFAW 0x3F000000 +#define BF_DRAM_CTL39_TFAW(v) \ + (((v) << 24) & BM_DRAM_CTL39_TFAW) +#define BP_DRAM_CTL39_OBSOLETE 16 +#define BM_DRAM_CTL39_OBSOLETE 0x00FF0000 +#define BF_DRAM_CTL39_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL39_OBSOLETE) +#define BP_DRAM_CTL39_TDLL 0 +#define BM_DRAM_CTL39_TDLL 0x0000FFFF +#define BF_DRAM_CTL39_TDLL(v) \ + (((v) << 0) & BM_DRAM_CTL39_TDLL) + +#define HW_DRAM_CTL40 (0x000000a0) + +#define BP_DRAM_CTL40_RSVD1 29 +#define BM_DRAM_CTL40_RSVD1 0xE0000000 +#define BF_DRAM_CTL40_RSVD1(v) \ + (((v) << 29) & BM_DRAM_CTL40_RSVD1) +#define BP_DRAM_CTL40_TMRD 24 +#define BM_DRAM_CTL40_TMRD 0x1F000000 +#define BF_DRAM_CTL40_TMRD(v) \ + (((v) << 24) & BM_DRAM_CTL40_TMRD) +#define BP_DRAM_CTL40_TINIT 0 +#define BM_DRAM_CTL40_TINIT 0x00FFFFFF +#define BF_DRAM_CTL40_TINIT(v) \ + (((v) << 0) & BM_DRAM_CTL40_TINIT) + +#define HW_DRAM_CTL41 (0x000000a4) + +#define BP_DRAM_CTL41_TPDEX 16 +#define BM_DRAM_CTL41_TPDEX 0xFFFF0000 +#define BF_DRAM_CTL41_TPDEX(v) \ + (((v) << 16) & BM_DRAM_CTL41_TPDEX) +#define BP_DRAM_CTL41_TRCD_INT 8 +#define BM_DRAM_CTL41_TRCD_INT 0x0000FF00 +#define BF_DRAM_CTL41_TRCD_INT(v) \ + (((v) << 8) & BM_DRAM_CTL41_TRCD_INT) +#define BP_DRAM_CTL41_RSVD1 6 +#define BM_DRAM_CTL41_RSVD1 0x000000C0 +#define BF_DRAM_CTL41_RSVD1(v) \ + (((v) << 6) & BM_DRAM_CTL41_RSVD1) +#define BP_DRAM_CTL41_TRC 0 +#define BM_DRAM_CTL41_TRC 0x0000003F +#define BF_DRAM_CTL41_TRC(v) \ + (((v) << 0) & BM_DRAM_CTL41_TRC) + +#define HW_DRAM_CTL42 (0x000000a8) + +#define BP_DRAM_CTL42_OBSOLETE 24 +#define BM_DRAM_CTL42_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL42_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL42_OBSOLETE) +#define BP_DRAM_CTL42_TRAS_MAX 8 +#define BM_DRAM_CTL42_TRAS_MAX 0x00FFFF00 +#define BF_DRAM_CTL42_TRAS_MAX(v) \ + (((v) << 8) & BM_DRAM_CTL42_TRAS_MAX) +#define BP_DRAM_CTL42_TRAS_MIN 0 +#define BM_DRAM_CTL42_TRAS_MIN 0x000000FF +#define BF_DRAM_CTL42_TRAS_MIN(v) \ + (((v) << 0) & BM_DRAM_CTL42_TRAS_MIN) + +#define HW_DRAM_CTL43 (0x000000ac) + +#define BP_DRAM_CTL43_RSVD2 28 +#define BM_DRAM_CTL43_RSVD2 0xF0000000 +#define BF_DRAM_CTL43_RSVD2(v) \ + (((v) << 28) & BM_DRAM_CTL43_RSVD2) +#define BP_DRAM_CTL43_TRP 24 +#define BM_DRAM_CTL43_TRP 0x0F000000 +#define BF_DRAM_CTL43_TRP(v) \ + (((v) << 24) & BM_DRAM_CTL43_TRP) +#define BP_DRAM_CTL43_TRFC 16 +#define BM_DRAM_CTL43_TRFC 0x00FF0000 +#define BF_DRAM_CTL43_TRFC(v) \ + (((v) << 16) & BM_DRAM_CTL43_TRFC) +#define BP_DRAM_CTL43_RSVD1 14 +#define BM_DRAM_CTL43_RSVD1 0x0000C000 +#define BF_DRAM_CTL43_RSVD1(v) \ + (((v) << 14) & BM_DRAM_CTL43_RSVD1) +#define BP_DRAM_CTL43_TREF 0 +#define BM_DRAM_CTL43_TREF 0x00003FFF +#define BF_DRAM_CTL43_TREF(v) \ + (((v) << 0) & BM_DRAM_CTL43_TREF) + +#define HW_DRAM_CTL44 (0x000000b0) + +#define BP_DRAM_CTL44_RSVD4 28 +#define BM_DRAM_CTL44_RSVD4 0xF0000000 +#define BF_DRAM_CTL44_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL44_RSVD4) +#define BP_DRAM_CTL44_TWTR 24 +#define BM_DRAM_CTL44_TWTR 0x0F000000 +#define BF_DRAM_CTL44_TWTR(v) \ + (((v) << 24) & BM_DRAM_CTL44_TWTR) +#define BP_DRAM_CTL44_RSVD3 21 +#define BM_DRAM_CTL44_RSVD3 0x00E00000 +#define BF_DRAM_CTL44_RSVD3(v) \ + (((v) << 21) & BM_DRAM_CTL44_RSVD3) +#define BP_DRAM_CTL44_TWR_INT 16 +#define BM_DRAM_CTL44_TWR_INT 0x001F0000 +#define BF_DRAM_CTL44_TWR_INT(v) \ + (((v) << 16) & BM_DRAM_CTL44_TWR_INT) +#define BP_DRAM_CTL44_RSVD2 11 +#define BM_DRAM_CTL44_RSVD2 0x0000F800 +#define BF_DRAM_CTL44_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL44_RSVD2) +#define BP_DRAM_CTL44_TRTP 8 +#define BM_DRAM_CTL44_TRTP 0x00000700 +#define BF_DRAM_CTL44_TRTP(v) \ + (((v) << 8) & BM_DRAM_CTL44_TRTP) +#define BP_DRAM_CTL44_RSVD1 3 +#define BM_DRAM_CTL44_RSVD1 0x000000F8 +#define BF_DRAM_CTL44_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL44_RSVD1) +#define BP_DRAM_CTL44_TRRD 0 +#define BM_DRAM_CTL44_TRRD 0x00000007 +#define BF_DRAM_CTL44_TRRD(v) \ + (((v) << 0) & BM_DRAM_CTL44_TRRD) + +#define HW_DRAM_CTL45 (0x000000b4) + +#define BP_DRAM_CTL45_TXSR 16 +#define BM_DRAM_CTL45_TXSR 0xFFFF0000 +#define BF_DRAM_CTL45_TXSR(v) \ + (((v) << 16) & BM_DRAM_CTL45_TXSR) +#define BP_DRAM_CTL45_TXSNR 0 +#define BM_DRAM_CTL45_TXSNR 0x0000FFFF +#define BF_DRAM_CTL45_TXSNR(v) \ + (((v) << 0) & BM_DRAM_CTL45_TXSNR) + +#define HW_DRAM_CTL48 (0x000000c0) + +#define BM_DRAM_CTL48_RSVD4 0x80000000 +#define BP_DRAM_CTL48_AXI0_CURRENT_BDW 24 +#define BM_DRAM_CTL48_AXI0_CURRENT_BDW 0x7F000000 +#define BF_DRAM_CTL48_AXI0_CURRENT_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL48_AXI0_CURRENT_BDW) +#define BP_DRAM_CTL48_RSVD3 17 +#define BM_DRAM_CTL48_RSVD3 0x00FE0000 +#define BF_DRAM_CTL48_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL48_RSVD3) +#define BM_DRAM_CTL48_AXI0_BDW_OVFLOW 0x00010000 +#define BM_DRAM_CTL48_RSVD2 0x00008000 +#define BP_DRAM_CTL48_AXI0_BDW 8 +#define BM_DRAM_CTL48_AXI0_BDW 0x00007F00 +#define BF_DRAM_CTL48_AXI0_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL48_AXI0_BDW) +#define BP_DRAM_CTL48_RSVD1 2 +#define BM_DRAM_CTL48_RSVD1 0x000000FC +#define BF_DRAM_CTL48_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL48_RSVD1) +#define BP_DRAM_CTL48_AXI0_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL48_AXI0_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL48_AXI0_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL48_AXI0_FIFO_TYPE_REG) + +#define HW_DRAM_CTL49 (0x000000c4) + +#define BP_DRAM_CTL49_AXI0_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL49_AXI0_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL49_AXI0_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL49_AXI0_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL49_RSVD2 11 +#define BM_DRAM_CTL49_RSVD2 0x0000F800 +#define BF_DRAM_CTL49_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL49_RSVD2) +#define BP_DRAM_CTL49_AXI0_W_PRIORITY 8 +#define BM_DRAM_CTL49_AXI0_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL49_AXI0_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL49_AXI0_W_PRIORITY) +#define BP_DRAM_CTL49_RSVD1 3 +#define BM_DRAM_CTL49_RSVD1 0x000000F8 +#define BF_DRAM_CTL49_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL49_RSVD1) +#define BP_DRAM_CTL49_AXI0_R_PRIORITY 0 +#define BM_DRAM_CTL49_AXI0_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL49_AXI0_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL49_AXI0_R_PRIORITY) + +#define HW_DRAM_CTL50 (0x000000c8) + +#define BM_DRAM_CTL50_RSVD4 0x80000000 +#define BP_DRAM_CTL50_AXI1_CURRENT_BDW 24 +#define BM_DRAM_CTL50_AXI1_CURRENT_BDW 0x7F000000 +#define BF_DRAM_CTL50_AXI1_CURRENT_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL50_AXI1_CURRENT_BDW) +#define BP_DRAM_CTL50_RSVD3 17 +#define BM_DRAM_CTL50_RSVD3 0x00FE0000 +#define BF_DRAM_CTL50_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL50_RSVD3) +#define BM_DRAM_CTL50_AXI1_BDW_OVFLOW 0x00010000 +#define BM_DRAM_CTL50_RSVD2 0x00008000 +#define BP_DRAM_CTL50_AXI1_BDW 8 +#define BM_DRAM_CTL50_AXI1_BDW 0x00007F00 +#define BF_DRAM_CTL50_AXI1_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL50_AXI1_BDW) +#define BP_DRAM_CTL50_RSVD1 2 +#define BM_DRAM_CTL50_RSVD1 0x000000FC +#define BF_DRAM_CTL50_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL50_RSVD1) +#define BP_DRAM_CTL50_AXI1_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL50_AXI1_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL50_AXI1_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL50_AXI1_FIFO_TYPE_REG) + +#define HW_DRAM_CTL51 (0x000000cc) + +#define BP_DRAM_CTL51_AXI1_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL51_AXI1_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL51_AXI1_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL51_AXI1_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL51_RSVD2 11 +#define BM_DRAM_CTL51_RSVD2 0x0000F800 +#define BF_DRAM_CTL51_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL51_RSVD2) +#define BP_DRAM_CTL51_AXI1_W_PRIORITY 8 +#define BM_DRAM_CTL51_AXI1_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL51_AXI1_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL51_AXI1_W_PRIORITY) +#define BP_DRAM_CTL51_RSVD1 3 +#define BM_DRAM_CTL51_RSVD1 0x000000F8 +#define BF_DRAM_CTL51_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL51_RSVD1) +#define BP_DRAM_CTL51_AXI1_R_PRIORITY 0 +#define BM_DRAM_CTL51_AXI1_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL51_AXI1_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL51_AXI1_R_PRIORITY) + +#define HW_DRAM_CTL52 (0x000000d0) + +#define BM_DRAM_CTL52_RSVD4 0x80000000 +#define BP_DRAM_CTL52_AXI2_CURRENT_BDW 24 +#define BM_DRAM_CTL52_AXI2_CURRENT_BDW 0x7F000000 +#define BF_DRAM_CTL52_AXI2_CURRENT_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL52_AXI2_CURRENT_BDW) +#define BP_DRAM_CTL52_RSVD3 17 +#define BM_DRAM_CTL52_RSVD3 0x00FE0000 +#define BF_DRAM_CTL52_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL52_RSVD3) +#define BM_DRAM_CTL52_AXI2_BDW_OVFLOW 0x00010000 +#define BM_DRAM_CTL52_RSVD2 0x00008000 +#define BP_DRAM_CTL52_AXI2_BDW 8 +#define BM_DRAM_CTL52_AXI2_BDW 0x00007F00 +#define BF_DRAM_CTL52_AXI2_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL52_AXI2_BDW) +#define BP_DRAM_CTL52_RSVD1 2 +#define BM_DRAM_CTL52_RSVD1 0x000000FC +#define BF_DRAM_CTL52_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL52_RSVD1) +#define BP_DRAM_CTL52_AXI2_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL52_AXI2_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL52_AXI2_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL52_AXI2_FIFO_TYPE_REG) + +#define HW_DRAM_CTL53 (0x000000d4) + +#define BP_DRAM_CTL53_AXI2_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL53_AXI2_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL53_AXI2_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL53_AXI2_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL53_RSVD2 11 +#define BM_DRAM_CTL53_RSVD2 0x0000F800 +#define BF_DRAM_CTL53_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL53_RSVD2) +#define BP_DRAM_CTL53_AXI2_W_PRIORITY 8 +#define BM_DRAM_CTL53_AXI2_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL53_AXI2_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL53_AXI2_W_PRIORITY) +#define BP_DRAM_CTL53_RSVD1 3 +#define BM_DRAM_CTL53_RSVD1 0x000000F8 +#define BF_DRAM_CTL53_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL53_RSVD1) +#define BP_DRAM_CTL53_AXI2_R_PRIORITY 0 +#define BM_DRAM_CTL53_AXI2_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL53_AXI2_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL53_AXI2_R_PRIORITY) + +#define HW_DRAM_CTL54 (0x000000d8) + +#define BM_DRAM_CTL54_RSVD4 0x80000000 +#define BP_DRAM_CTL54_AXI3_CURRENT_BDW 24 +#define BM_DRAM_CTL54_AXI3_CURRENT_BDW 0x7F000000 +#define BF_DRAM_CTL54_AXI3_CURRENT_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL54_AXI3_CURRENT_BDW) +#define BP_DRAM_CTL54_RSVD3 17 +#define BM_DRAM_CTL54_RSVD3 0x00FE0000 +#define BF_DRAM_CTL54_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL54_RSVD3) +#define BM_DRAM_CTL54_AXI3_BDW_OVFLOW 0x00010000 +#define BM_DRAM_CTL54_RSVD2 0x00008000 +#define BP_DRAM_CTL54_AXI3_BDW 8 +#define BM_DRAM_CTL54_AXI3_BDW 0x00007F00 +#define BF_DRAM_CTL54_AXI3_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL54_AXI3_BDW) +#define BP_DRAM_CTL54_RSVD1 2 +#define BM_DRAM_CTL54_RSVD1 0x000000FC +#define BF_DRAM_CTL54_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL54_RSVD1) +#define BP_DRAM_CTL54_AXI3_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL54_AXI3_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL54_AXI3_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL54_AXI3_FIFO_TYPE_REG) + +#define HW_DRAM_CTL55 (0x000000dc) + +#define BP_DRAM_CTL55_AXI3_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL55_AXI3_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL55_AXI3_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL55_AXI3_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL55_RSVD2 11 +#define BM_DRAM_CTL55_RSVD2 0x0000F800 +#define BF_DRAM_CTL55_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL55_RSVD2) +#define BP_DRAM_CTL55_AXI3_W_PRIORITY 8 +#define BM_DRAM_CTL55_AXI3_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL55_AXI3_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL55_AXI3_W_PRIORITY) +#define BP_DRAM_CTL55_RSVD1 3 +#define BM_DRAM_CTL55_RSVD1 0x000000F8 +#define BF_DRAM_CTL55_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL55_RSVD1) +#define BP_DRAM_CTL55_AXI3_R_PRIORITY 0 +#define BM_DRAM_CTL55_AXI3_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL55_AXI3_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL55_AXI3_R_PRIORITY) + +#define HW_DRAM_CTL56 (0x000000e0) + +#define BP_DRAM_CTL56_OBSOLETE 8 +#define BM_DRAM_CTL56_OBSOLETE 0xFFFFFF00 +#define BF_DRAM_CTL56_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL56_OBSOLETE) +#define BP_DRAM_CTL56_RSVD1 3 +#define BM_DRAM_CTL56_RSVD1 0x000000F8 +#define BF_DRAM_CTL56_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL56_RSVD1) +#define BP_DRAM_CTL56_ARB_CMD_Q_THRESHOLD 0 +#define BM_DRAM_CTL56_ARB_CMD_Q_THRESHOLD 0x00000007 +#define BF_DRAM_CTL56_ARB_CMD_Q_THRESHOLD(v) \ + (((v) << 0) & BM_DRAM_CTL56_ARB_CMD_Q_THRESHOLD) + +#define HW_DRAM_CTL58 (0x000000e8) + +#define BP_DRAM_CTL58_RSVD2 27 +#define BM_DRAM_CTL58_RSVD2 0xF8000000 +#define BF_DRAM_CTL58_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL58_RSVD2) +#define BP_DRAM_CTL58_INT_STATUS 16 +#define BM_DRAM_CTL58_INT_STATUS 0x07FF0000 +#define BF_DRAM_CTL58_INT_STATUS(v) \ + (((v) << 16) & BM_DRAM_CTL58_INT_STATUS) +#define BP_DRAM_CTL58_RSVD1 11 +#define BM_DRAM_CTL58_RSVD1 0x0000F800 +#define BF_DRAM_CTL58_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL58_RSVD1) +#define BP_DRAM_CTL58_INT_MASK 0 +#define BM_DRAM_CTL58_INT_MASK 0x000007FF +#define BF_DRAM_CTL58_INT_MASK(v) \ + (((v) << 0) & BM_DRAM_CTL58_INT_MASK) + +#define HW_DRAM_CTL59 (0x000000ec) + +#define BP_DRAM_CTL59_OUT_OF_RANGE_ADDR 0 +#define BM_DRAM_CTL59_OUT_OF_RANGE_ADDR 0xFFFFFFFF +#define BF_DRAM_CTL59_OUT_OF_RANGE_ADDR(v) (v) + +#define HW_DRAM_CTL60 (0x000000f0) + +#define BP_DRAM_CTL60_OBSOLETE 8 +#define BM_DRAM_CTL60_OBSOLETE 0xFFFFFF00 +#define BF_DRAM_CTL60_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL60_OBSOLETE) +#define BP_DRAM_CTL60_RSVD1 2 +#define BM_DRAM_CTL60_RSVD1 0x000000FC +#define BF_DRAM_CTL60_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL60_RSVD1) +#define BP_DRAM_CTL60_OUT_OF_RANGE_ADDR 0 +#define BM_DRAM_CTL60_OUT_OF_RANGE_ADDR 0x00000003 +#define BF_DRAM_CTL60_OUT_OF_RANGE_ADDR(v) \ + (((v) << 0) & BM_DRAM_CTL60_OUT_OF_RANGE_ADDR) + +#define HW_DRAM_CTL61 (0x000000f4) + +#define BP_DRAM_CTL61_RSVD3 30 +#define BM_DRAM_CTL61_RSVD3 0xC0000000 +#define BF_DRAM_CTL61_RSVD3(v) \ + (((v) << 30) & BM_DRAM_CTL61_RSVD3) +#define BP_DRAM_CTL61_OUT_OF_RANGE_TYPE 24 +#define BM_DRAM_CTL61_OUT_OF_RANGE_TYPE 0x3F000000 +#define BF_DRAM_CTL61_OUT_OF_RANGE_TYPE(v) \ + (((v) << 24) & BM_DRAM_CTL61_OUT_OF_RANGE_TYPE) +#define BM_DRAM_CTL61_RSVD2 0x00800000 +#define BP_DRAM_CTL61_OUT_OF_RANGE_LENGTH 16 +#define BM_DRAM_CTL61_OUT_OF_RANGE_LENGTH 0x007F0000 +#define BF_DRAM_CTL61_OUT_OF_RANGE_LENGTH(v) \ + (((v) << 16) & BM_DRAM_CTL61_OUT_OF_RANGE_LENGTH) +#define BP_DRAM_CTL61_RSVD1 13 +#define BM_DRAM_CTL61_RSVD1 0x0000E000 +#define BF_DRAM_CTL61_RSVD1(v) \ + (((v) << 13) & BM_DRAM_CTL61_RSVD1) +#define BP_DRAM_CTL61_OUT_OF_RANGE_SOURCE_ID 0 +#define BM_DRAM_CTL61_OUT_OF_RANGE_SOURCE_ID 0x00001FFF +#define BF_DRAM_CTL61_OUT_OF_RANGE_SOURCE_ID(v) \ + (((v) << 0) & BM_DRAM_CTL61_OUT_OF_RANGE_SOURCE_ID) + +#define HW_DRAM_CTL62 (0x000000f8) + +#define BP_DRAM_CTL62_PORT_CMD_ERROR_ADDR 0 +#define BM_DRAM_CTL62_PORT_CMD_ERROR_ADDR 0xFFFFFFFF +#define BF_DRAM_CTL62_PORT_CMD_ERROR_ADDR(v) (v) + +#define HW_DRAM_CTL63 (0x000000fc) + +#define BP_DRAM_CTL63_OBSOLETE 8 +#define BM_DRAM_CTL63_OBSOLETE 0xFFFFFF00 +#define BF_DRAM_CTL63_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL63_OBSOLETE) +#define BP_DRAM_CTL63_RSVD1 2 +#define BM_DRAM_CTL63_RSVD1 0x000000FC +#define BF_DRAM_CTL63_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL63_RSVD1) +#define BP_DRAM_CTL63_PORT_CMD_ERROR_ADDR 0 +#define BM_DRAM_CTL63_PORT_CMD_ERROR_ADDR 0x00000003 +#define BF_DRAM_CTL63_PORT_CMD_ERROR_ADDR(v) \ + (((v) << 0) & BM_DRAM_CTL63_PORT_CMD_ERROR_ADDR) + +#define HW_DRAM_CTL64 (0x00000100) + +#define BP_DRAM_CTL64_OBSOLETE 24 +#define BM_DRAM_CTL64_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL64_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL64_OBSOLETE) +#define BP_DRAM_CTL64_RSVD2 21 +#define BM_DRAM_CTL64_RSVD2 0x00E00000 +#define BF_DRAM_CTL64_RSVD2(v) \ + (((v) << 21) & BM_DRAM_CTL64_RSVD2) +#define BP_DRAM_CTL64_PORT_CMD_ERROR_ID 8 +#define BM_DRAM_CTL64_PORT_CMD_ERROR_ID 0x001FFF00 +#define BF_DRAM_CTL64_PORT_CMD_ERROR_ID(v) \ + (((v) << 8) & BM_DRAM_CTL64_PORT_CMD_ERROR_ID) +#define BP_DRAM_CTL64_RSVD1 4 +#define BM_DRAM_CTL64_RSVD1 0x000000F0 +#define BF_DRAM_CTL64_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL64_RSVD1) +#define BP_DRAM_CTL64_PORT_CMD_ERROR_TYPE 0 +#define BM_DRAM_CTL64_PORT_CMD_ERROR_TYPE 0x0000000F +#define BF_DRAM_CTL64_PORT_CMD_ERROR_TYPE(v) \ + (((v) << 0) & BM_DRAM_CTL64_PORT_CMD_ERROR_TYPE) + +#define HW_DRAM_CTL65 (0x00000104) + +#define BP_DRAM_CTL65_OBSOLETE 24 +#define BM_DRAM_CTL65_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL65_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL65_OBSOLETE) +#define BP_DRAM_CTL65_RSVD2 21 +#define BM_DRAM_CTL65_RSVD2 0x00E00000 +#define BF_DRAM_CTL65_RSVD2(v) \ + (((v) << 21) & BM_DRAM_CTL65_RSVD2) +#define BP_DRAM_CTL65_PORT_DATA_ERROR_ID 8 +#define BM_DRAM_CTL65_PORT_DATA_ERROR_ID 0x001FFF00 +#define BF_DRAM_CTL65_PORT_DATA_ERROR_ID(v) \ + (((v) << 8) & BM_DRAM_CTL65_PORT_DATA_ERROR_ID) +#define BP_DRAM_CTL65_RSVD1 3 +#define BM_DRAM_CTL65_RSVD1 0x000000F8 +#define BF_DRAM_CTL65_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL65_RSVD1) +#define BP_DRAM_CTL65_PORT_DATA_ERROR_TYPE 0 +#define BM_DRAM_CTL65_PORT_DATA_ERROR_TYPE 0x00000007 +#define BF_DRAM_CTL65_PORT_DATA_ERROR_TYPE(v) \ + (((v) << 0) & BM_DRAM_CTL65_PORT_DATA_ERROR_TYPE) + +#define HW_DRAM_CTL66 (0x00000108) + +#define BP_DRAM_CTL66_OBSOLETE 24 +#define BM_DRAM_CTL66_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL66_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL66_OBSOLETE) +#define BP_DRAM_CTL66_RSVD2 20 +#define BM_DRAM_CTL66_RSVD2 0x00F00000 +#define BF_DRAM_CTL66_RSVD2(v) \ + (((v) << 20) & BM_DRAM_CTL66_RSVD2) +#define BP_DRAM_CTL66_TDFI_CTRLUPD_MIN 16 +#define BM_DRAM_CTL66_TDFI_CTRLUPD_MIN 0x000F0000 +#define BF_DRAM_CTL66_TDFI_CTRLUPD_MIN(v) \ + (((v) << 16) & BM_DRAM_CTL66_TDFI_CTRLUPD_MIN) +#define BP_DRAM_CTL66_RSVD1 14 +#define BM_DRAM_CTL66_RSVD1 0x0000C000 +#define BF_DRAM_CTL66_RSVD1(v) \ + (((v) << 14) & BM_DRAM_CTL66_RSVD1) +#define BP_DRAM_CTL66_TDFI_CTRLUPD_MAX 0 +#define BM_DRAM_CTL66_TDFI_CTRLUPD_MAX 0x00003FFF +#define BF_DRAM_CTL66_TDFI_CTRLUPD_MAX(v) \ + (((v) << 0) & BM_DRAM_CTL66_TDFI_CTRLUPD_MAX) + +#define HW_DRAM_CTL67 (0x0000010c) + +#define BP_DRAM_CTL67_RSVD4 28 +#define BM_DRAM_CTL67_RSVD4 0xF0000000 +#define BF_DRAM_CTL67_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL67_RSVD4) +#define BP_DRAM_CTL67_TDFI_DRAM_CLK_ENABLE 24 +#define BM_DRAM_CTL67_TDFI_DRAM_CLK_ENABLE 0x0F000000 +#define BF_DRAM_CTL67_TDFI_DRAM_CLK_ENABLE(v) \ + (((v) << 24) & BM_DRAM_CTL67_TDFI_DRAM_CLK_ENABLE) +#define BP_DRAM_CTL67_RSVD3 19 +#define BM_DRAM_CTL67_RSVD3 0x00F80000 +#define BF_DRAM_CTL67_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL67_RSVD3) +#define BP_DRAM_CTL67_TDFI_DRAM_CLK_DISABLE 16 +#define BM_DRAM_CTL67_TDFI_DRAM_CLK_DISABLE 0x00070000 +#define BF_DRAM_CTL67_TDFI_DRAM_CLK_DISABLE(v) \ + (((v) << 16) & BM_DRAM_CTL67_TDFI_DRAM_CLK_DISABLE) +#define BP_DRAM_CTL67_RSVD2 12 +#define BM_DRAM_CTL67_RSVD2 0x0000F000 +#define BF_DRAM_CTL67_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL67_RSVD2) +#define BP_DRAM_CTL67_DRAM_CLK_ENABLE 8 +#define BM_DRAM_CTL67_DRAM_CLK_ENABLE 0x00000F00 +#define BF_DRAM_CTL67_DRAM_CLK_ENABLE(v) \ + (((v) << 8) & BM_DRAM_CTL67_DRAM_CLK_ENABLE) +#define BP_DRAM_CTL67_RSVD1 4 +#define BM_DRAM_CTL67_RSVD1 0x000000F0 +#define BF_DRAM_CTL67_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL67_RSVD1) +#define BP_DRAM_CTL67_TDFI_CTRL_DELAY 0 +#define BM_DRAM_CTL67_TDFI_CTRL_DELAY 0x0000000F +#define BF_DRAM_CTL67_TDFI_CTRL_DELAY(v) \ + (((v) << 0) & BM_DRAM_CTL67_TDFI_CTRL_DELAY) + +#define HW_DRAM_CTL68 (0x00000110) + +#define BP_DRAM_CTL68_RSVD2 30 +#define BM_DRAM_CTL68_RSVD2 0xC0000000 +#define BF_DRAM_CTL68_RSVD2(v) \ + (((v) << 30) & BM_DRAM_CTL68_RSVD2) +#define BP_DRAM_CTL68_TDFI_PHYUPD_TYPE0 16 +#define BM_DRAM_CTL68_TDFI_PHYUPD_TYPE0 0x3FFF0000 +#define BF_DRAM_CTL68_TDFI_PHYUPD_TYPE0(v) \ + (((v) << 16) & BM_DRAM_CTL68_TDFI_PHYUPD_TYPE0) +#define BP_DRAM_CTL68_RSVD1 14 +#define BM_DRAM_CTL68_RSVD1 0x0000C000 +#define BF_DRAM_CTL68_RSVD1(v) \ + (((v) << 14) & BM_DRAM_CTL68_RSVD1) +#define BP_DRAM_CTL68_TDFI_PHYUPD_RESP 0 +#define BM_DRAM_CTL68_TDFI_PHYUPD_RESP 0x00003FFF +#define BF_DRAM_CTL68_TDFI_PHYUPD_RESP(v) \ + (((v) << 0) & BM_DRAM_CTL68_TDFI_PHYUPD_RESP) + +#define HW_DRAM_CTL69 (0x00000114) + +#define BP_DRAM_CTL69_OBSOLETE 16 +#define BM_DRAM_CTL69_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL69_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL69_OBSOLETE) +#define BP_DRAM_CTL69_RSVD2 12 +#define BM_DRAM_CTL69_RSVD2 0x0000F000 +#define BF_DRAM_CTL69_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL69_RSVD2) +#define BP_DRAM_CTL69_TDFI_PHY_WRLAT_BASE 8 +#define BM_DRAM_CTL69_TDFI_PHY_WRLAT_BASE 0x00000F00 +#define BF_DRAM_CTL69_TDFI_PHY_WRLAT_BASE(v) \ + (((v) << 8) & BM_DRAM_CTL69_TDFI_PHY_WRLAT_BASE) +#define BP_DRAM_CTL69_RSVD1 4 +#define BM_DRAM_CTL69_RSVD1 0x000000F0 +#define BF_DRAM_CTL69_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL69_RSVD1) +#define BP_DRAM_CTL69_TDFI_PHY_WRLAT 0 +#define BM_DRAM_CTL69_TDFI_PHY_WRLAT 0x0000000F +#define BF_DRAM_CTL69_TDFI_PHY_WRLAT(v) \ + (((v) << 0) & BM_DRAM_CTL69_TDFI_PHY_WRLAT) + +#define HW_DRAM_CTL70 (0x00000118) + +#define BP_DRAM_CTL70_OBSOLETE 24 +#define BM_DRAM_CTL70_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL70_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL70_OBSOLETE) +#define BP_DRAM_CTL70_RSVD3 20 +#define BM_DRAM_CTL70_RSVD3 0x00F00000 +#define BF_DRAM_CTL70_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL70_RSVD3) +#define BP_DRAM_CTL70_TDFI_RDDATA_EN_BASE 16 +#define BM_DRAM_CTL70_TDFI_RDDATA_EN_BASE 0x000F0000 +#define BF_DRAM_CTL70_TDFI_RDDATA_EN_BASE(v) \ + (((v) << 16) & BM_DRAM_CTL70_TDFI_RDDATA_EN_BASE) +#define BP_DRAM_CTL70_RSVD2 12 +#define BM_DRAM_CTL70_RSVD2 0x0000F000 +#define BF_DRAM_CTL70_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL70_RSVD2) +#define BP_DRAM_CTL70_TDFI_RDDATA_EN 8 +#define BM_DRAM_CTL70_TDFI_RDDATA_EN 0x00000F00 +#define BF_DRAM_CTL70_TDFI_RDDATA_EN(v) \ + (((v) << 8) & BM_DRAM_CTL70_TDFI_RDDATA_EN) +#define BP_DRAM_CTL70_RSVD1 4 +#define BM_DRAM_CTL70_RSVD1 0x000000F0 +#define BF_DRAM_CTL70_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL70_RSVD1) +#define BP_DRAM_CTL70_TDFI_PHY_RDLAT 0 +#define BM_DRAM_CTL70_TDFI_PHY_RDLAT 0x0000000F +#define BF_DRAM_CTL70_TDFI_PHY_RDLAT(v) \ + (((v) << 0) & BM_DRAM_CTL70_TDFI_PHY_RDLAT) + +#define HW_DRAM_CTL71 (0x0000011c) + +#define BP_DRAM_CTL71_PHY_CTRL_REG_0_0 0 +#define BM_DRAM_CTL71_PHY_CTRL_REG_0_0 0xFFFFFFFF +#define BF_DRAM_CTL71_PHY_CTRL_REG_0_0(v) (v) + +#define HW_DRAM_CTL72 (0x00000120) + +#define BP_DRAM_CTL72_PHY_CTRL_REG_0_1 0 +#define BM_DRAM_CTL72_PHY_CTRL_REG_0_1 0xFFFFFFFF +#define BF_DRAM_CTL72_PHY_CTRL_REG_0_1(v) (v) + +#define HW_DRAM_CTL73 (0x00000124) + +#define BP_DRAM_CTL73_PHY_CTRL_REG_0_2 0 +#define BM_DRAM_CTL73_PHY_CTRL_REG_0_2 0xFFFFFFFF +#define BF_DRAM_CTL73_PHY_CTRL_REG_0_2(v) (v) + +#define HW_DRAM_CTL74 (0x00000128) + +#define BP_DRAM_CTL74_PHY_CTRL_REG_0_3 0 +#define BM_DRAM_CTL74_PHY_CTRL_REG_0_3 0xFFFFFFFF +#define BF_DRAM_CTL74_PHY_CTRL_REG_0_3(v) (v) + +#define HW_DRAM_CTL75 (0x0000012c) + +#define BP_DRAM_CTL75_PHY_CTRL_REG_1_0 0 +#define BM_DRAM_CTL75_PHY_CTRL_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL75_PHY_CTRL_REG_1_0(v) (v) + +#define HW_DRAM_CTL76 (0x00000130) + +#define BP_DRAM_CTL76_PHY_CTRL_REG_1_1 0 +#define BM_DRAM_CTL76_PHY_CTRL_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL76_PHY_CTRL_REG_1_1(v) (v) + +#define HW_DRAM_CTL77 (0x00000134) + +#define BP_DRAM_CTL77_PHY_CTRL_REG_1_2 0 +#define BM_DRAM_CTL77_PHY_CTRL_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL77_PHY_CTRL_REG_1_2(v) (v) + +#define HW_DRAM_CTL78 (0x00000138) + +#define BP_DRAM_CTL78_PHY_CTRL_REG_1_3 0 +#define BM_DRAM_CTL78_PHY_CTRL_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL78_PHY_CTRL_REG_1_3(v) (v) + +#define HW_DRAM_CTL79 (0x0000013c) + +#define BP_DRAM_CTL79_PHY_CTRL_REG_2 0 +#define BM_DRAM_CTL79_PHY_CTRL_REG_2 0xFFFFFFFF +#define BF_DRAM_CTL79_PHY_CTRL_REG_2(v) (v) + +#define HW_DRAM_CTL80 (0x00000140) + +#define BP_DRAM_CTL80_DFT_CTRL_REG 0 +#define BM_DRAM_CTL80_DFT_CTRL_REG 0xFFFFFFFF +#define BF_DRAM_CTL80_DFT_CTRL_REG(v) (v) + +#define HW_DRAM_CTL81 (0x00000144) + +#define BP_DRAM_CTL81_OBSOLETE 16 +#define BM_DRAM_CTL81_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL81_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL81_OBSOLETE) +#define BP_DRAM_CTL81_RSVD2 13 +#define BM_DRAM_CTL81_RSVD2 0x0000E000 +#define BF_DRAM_CTL81_RSVD2(v) \ + (((v) << 13) & BM_DRAM_CTL81_RSVD2) +#define BP_DRAM_CTL81_OCD_ADJUST_PUP_CS_0 8 +#define BM_DRAM_CTL81_OCD_ADJUST_PUP_CS_0 0x00001F00 +#define BF_DRAM_CTL81_OCD_ADJUST_PUP_CS_0(v) \ + (((v) << 8) & BM_DRAM_CTL81_OCD_ADJUST_PUP_CS_0) +#define BP_DRAM_CTL81_RSVD1 5 +#define BM_DRAM_CTL81_RSVD1 0x000000E0 +#define BF_DRAM_CTL81_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL81_RSVD1) +#define BP_DRAM_CTL81_OCD_ADJUST_PDN_CS_0 0 +#define BM_DRAM_CTL81_OCD_ADJUST_PDN_CS_0 0x0000001F +#define BF_DRAM_CTL81_OCD_ADJUST_PDN_CS_0(v) \ + (((v) << 0) & BM_DRAM_CTL81_OCD_ADJUST_PDN_CS_0) + +#define HW_DRAM_CTL82 (0x00000148) + +#define BP_DRAM_CTL82_RSVD1 25 +#define BM_DRAM_CTL82_RSVD1 0xFE000000 +#define BF_DRAM_CTL82_RSVD1(v) \ + (((v) << 25) & BM_DRAM_CTL82_RSVD1) +#define BM_DRAM_CTL82_ODT_ALT_EN 0x01000000 +#define BP_DRAM_CTL82_OBSOLETE 0 +#define BM_DRAM_CTL82_OBSOLETE 0x00FFFFFF +#define BF_DRAM_CTL82_OBSOLETE(v) \ + (((v) << 0) & BM_DRAM_CTL82_OBSOLETE) + +#define HW_DRAM_CTL83 (0x0000014c) + +#define BP_DRAM_CTL83_RSVD4 28 +#define BM_DRAM_CTL83_RSVD4 0xF0000000 +#define BF_DRAM_CTL83_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL83_RSVD4) +#define BP_DRAM_CTL83_ODT_RD_MAP_CS3 24 +#define BM_DRAM_CTL83_ODT_RD_MAP_CS3 0x0F000000 +#define BF_DRAM_CTL83_ODT_RD_MAP_CS3(v) \ + (((v) << 24) & BM_DRAM_CTL83_ODT_RD_MAP_CS3) +#define BP_DRAM_CTL83_RSVD3 20 +#define BM_DRAM_CTL83_RSVD3 0x00F00000 +#define BF_DRAM_CTL83_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL83_RSVD3) +#define BP_DRAM_CTL83_ODT_RD_MAP_CS2 16 +#define BM_DRAM_CTL83_ODT_RD_MAP_CS2 0x000F0000 +#define BF_DRAM_CTL83_ODT_RD_MAP_CS2(v) \ + (((v) << 16) & BM_DRAM_CTL83_ODT_RD_MAP_CS2) +#define BP_DRAM_CTL83_RSVD2 12 +#define BM_DRAM_CTL83_RSVD2 0x0000F000 +#define BF_DRAM_CTL83_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL83_RSVD2) +#define BP_DRAM_CTL83_ODT_RD_MAP_CS1 8 +#define BM_DRAM_CTL83_ODT_RD_MAP_CS1 0x00000F00 +#define BF_DRAM_CTL83_ODT_RD_MAP_CS1(v) \ + (((v) << 8) & BM_DRAM_CTL83_ODT_RD_MAP_CS1) +#define BP_DRAM_CTL83_RSVD1 4 +#define BM_DRAM_CTL83_RSVD1 0x000000F0 +#define BF_DRAM_CTL83_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL83_RSVD1) +#define BP_DRAM_CTL83_ODT_RD_MAP_CS0 0 +#define BM_DRAM_CTL83_ODT_RD_MAP_CS0 0x0000000F +#define BF_DRAM_CTL83_ODT_RD_MAP_CS0(v) \ + (((v) << 0) & BM_DRAM_CTL83_ODT_RD_MAP_CS0) + +#define HW_DRAM_CTL84 (0x00000150) + +#define BP_DRAM_CTL84_RSVD4 28 +#define BM_DRAM_CTL84_RSVD4 0xF0000000 +#define BF_DRAM_CTL84_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL84_RSVD4) +#define BP_DRAM_CTL84_ODT_WR_MAP_CS3 24 +#define BM_DRAM_CTL84_ODT_WR_MAP_CS3 0x0F000000 +#define BF_DRAM_CTL84_ODT_WR_MAP_CS3(v) \ + (((v) << 24) & BM_DRAM_CTL84_ODT_WR_MAP_CS3) +#define BP_DRAM_CTL84_RSVD3 20 +#define BM_DRAM_CTL84_RSVD3 0x00F00000 +#define BF_DRAM_CTL84_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL84_RSVD3) +#define BP_DRAM_CTL84_ODT_WR_MAP_CS2 16 +#define BM_DRAM_CTL84_ODT_WR_MAP_CS2 0x000F0000 +#define BF_DRAM_CTL84_ODT_WR_MAP_CS2(v) \ + (((v) << 16) & BM_DRAM_CTL84_ODT_WR_MAP_CS2) +#define BP_DRAM_CTL84_RSVD2 12 +#define BM_DRAM_CTL84_RSVD2 0x0000F000 +#define BF_DRAM_CTL84_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL84_RSVD2) +#define BP_DRAM_CTL84_ODT_WR_MAP_CS1 8 +#define BM_DRAM_CTL84_ODT_WR_MAP_CS1 0x00000F00 +#define BF_DRAM_CTL84_ODT_WR_MAP_CS1(v) \ + (((v) << 8) & BM_DRAM_CTL84_ODT_WR_MAP_CS1) +#define BP_DRAM_CTL84_RSVD1 4 +#define BM_DRAM_CTL84_RSVD1 0x000000F0 +#define BF_DRAM_CTL84_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL84_RSVD1) +#define BP_DRAM_CTL84_ODT_WR_MAP_CS0 0 +#define BM_DRAM_CTL84_ODT_WR_MAP_CS0 0x0000000F +#define BF_DRAM_CTL84_ODT_WR_MAP_CS0(v) \ + (((v) << 0) & BM_DRAM_CTL84_ODT_WR_MAP_CS0) + +#define HW_DRAM_CTL85 (0x00000154) + +#define BP_DRAM_CTL85_PAD_CTRL_REG_0 0 +#define BM_DRAM_CTL85_PAD_CTRL_REG_0 0xFFFFFFFF +#define BF_DRAM_CTL85_PAD_CTRL_REG_0(v) (v) + +#define HW_DRAM_CTL86 (0x00000158) + +#define BP_DRAM_CTL86_OBSOLETE 16 +#define BM_DRAM_CTL86_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL86_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL86_OBSOLETE) +#define BP_DRAM_CTL86_VERSION 0 +#define BM_DRAM_CTL86_VERSION 0x0000FFFF +#define BF_DRAM_CTL86_VERSION(v) \ + (((v) << 0) & BM_DRAM_CTL86_VERSION) + +#define HW_DRAM_CTL87 (0x0000015c) + +#define BP_DRAM_CTL87_DLL_CTRL_REG_0_0 0 +#define BM_DRAM_CTL87_DLL_CTRL_REG_0_0 0xFFFFFFFF +#define BF_DRAM_CTL87_DLL_CTRL_REG_0_0(v) (v) + +#define HW_DRAM_CTL88 (0x00000160) + +#define BP_DRAM_CTL88_DLL_CTRL_REG_0_1 0 +#define BM_DRAM_CTL88_DLL_CTRL_REG_0_1 0xFFFFFFFF +#define BF_DRAM_CTL88_DLL_CTRL_REG_0_1(v) (v) + +#define HW_DRAM_CTL89 (0x00000164) + +#define BP_DRAM_CTL89_DLL_CTRL_REG_0_2 0 +#define BM_DRAM_CTL89_DLL_CTRL_REG_0_2 0xFFFFFFFF +#define BF_DRAM_CTL89_DLL_CTRL_REG_0_2(v) (v) + +#define HW_DRAM_CTL90 (0x00000168) + +#define BP_DRAM_CTL90_DLL_CTRL_REG_0_3 0 +#define BM_DRAM_CTL90_DLL_CTRL_REG_0_3 0xFFFFFFFF +#define BF_DRAM_CTL90_DLL_CTRL_REG_0_3(v) (v) + +#define HW_DRAM_CTL91 (0x0000016c) + +#define BP_DRAM_CTL91_DLL_CTRL_REG_1_0 0 +#define BM_DRAM_CTL91_DLL_CTRL_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL91_DLL_CTRL_REG_1_0(v) (v) + +#define HW_DRAM_CTL92 (0x00000170) + +#define BP_DRAM_CTL92_DLL_CTRL_REG_1_1 0 +#define BM_DRAM_CTL92_DLL_CTRL_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL92_DLL_CTRL_REG_1_1(v) (v) + +#define HW_DRAM_CTL93 (0x00000174) + +#define BP_DRAM_CTL93_DLL_CTRL_REG_1_2 0 +#define BM_DRAM_CTL93_DLL_CTRL_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL93_DLL_CTRL_REG_1_2(v) (v) + +#define HW_DRAM_CTL94 (0x00000178) + +#define BP_DRAM_CTL94_DLL_CTRL_REG_1_3 0 +#define BM_DRAM_CTL94_DLL_CTRL_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL94_DLL_CTRL_REG_1_3(v) (v) + +#define HW_DRAM_CTL95 (0x0000017c) + +#define BP_DRAM_CTL95_DLL_OBS_REG_0_0 0 +#define BM_DRAM_CTL95_DLL_OBS_REG_0_0 0xFFFFFFFF +#define BF_DRAM_CTL95_DLL_OBS_REG_0_0(v) (v) + +#define HW_DRAM_CTL96 (0x00000180) + +#define BP_DRAM_CTL96_DLL_OBS_REG_0_1 0 +#define BM_DRAM_CTL96_DLL_OBS_REG_0_1 0xFFFFFFFF +#define BF_DRAM_CTL96_DLL_OBS_REG_0_1(v) (v) + +#define HW_DRAM_CTL97 (0x00000184) + +#define BP_DRAM_CTL97_DLL_OBS_REG_0_2 0 +#define BM_DRAM_CTL97_DLL_OBS_REG_0_2 0xFFFFFFFF +#define BF_DRAM_CTL97_DLL_OBS_REG_0_2(v) (v) + +#define HW_DRAM_CTL98 (0x00000188) + +#define BP_DRAM_CTL98_DLL_OBS_REG_0_3 0 +#define BM_DRAM_CTL98_DLL_OBS_REG_0_3 0xFFFFFFFF +#define BF_DRAM_CTL98_DLL_OBS_REG_0_3(v) (v) + +#define HW_DRAM_CTL99 (0x0000018c) + +#define BP_DRAM_CTL99_PHY_OBS_REG_0_0 0 +#define BM_DRAM_CTL99_PHY_OBS_REG_0_0 0xFFFFFFFF +#define BF_DRAM_CTL99_PHY_OBS_REG_0_0(v) (v) + +#define HW_DRAM_CTL100 (0x00000190) + +#define BP_DRAM_CTL100_PHY_OBS_REG_0_1 0 +#define BM_DRAM_CTL100_PHY_OBS_REG_0_1 0xFFFFFFFF +#define BF_DRAM_CTL100_PHY_OBS_REG_0_1(v) (v) + +#define HW_DRAM_CTL101 (0x00000194) + +#define BP_DRAM_CTL101_PHY_OBS_REG_0_2 0 +#define BM_DRAM_CTL101_PHY_OBS_REG_0_2 0xFFFFFFFF +#define BF_DRAM_CTL101_PHY_OBS_REG_0_2(v) (v) + +#define HW_DRAM_CTL102 (0x00000198) + +#define BP_DRAM_CTL102_PHY_OBS_REG_0_3 0 +#define BM_DRAM_CTL102_PHY_OBS_REG_0_3 0xFFFFFFFF +#define BF_DRAM_CTL102_PHY_OBS_REG_0_3(v) (v) + +#define HW_DRAM_CTL103 (0x0000019c) + +#define BP_DRAM_CTL103_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL103_DLL_OBS_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL103_DLL_OBS_REG_1_0(v) (v) + +#define HW_DRAM_CTL104 (0x000001a0) + +#define BP_DRAM_CTL104_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL104_DLL_OBS_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL104_DLL_OBS_REG_1_0(v) (v) + +#define HW_DRAM_CTL105 (0x000001a4) + +#define BP_DRAM_CTL105_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL105_DLL_OBS_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL105_DLL_OBS_REG_1_0(v) (v) + +#define HW_DRAM_CTL106 (0x000001a8) + +#define BP_DRAM_CTL106_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL106_DLL_OBS_REG_1_0 0xFFFFFFFF +#define BF_DRAM_CTL106_DLL_OBS_REG_1_0(v) (v) + +#define HW_DRAM_CTL107 (0x000001ac) + +#define BP_DRAM_CTL107_OBSOLETE 16 +#define BM_DRAM_CTL107_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL107_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL107_OBSOLETE) +#define BP_DRAM_CTL107_RSVD1 9 +#define BM_DRAM_CTL107_RSVD1 0x0000FE00 +#define BF_DRAM_CTL107_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL107_RSVD1) +#define BP_DRAM_CTL107_DLL_OBS_REG_1_0 0 +#define BM_DRAM_CTL107_DLL_OBS_REG_1_0 0x000001FF +#define BF_DRAM_CTL107_DLL_OBS_REG_1_0(v) \ + (((v) << 0) & BM_DRAM_CTL107_DLL_OBS_REG_1_0) + +#define HW_DRAM_CTL108 (0x000001b0) + +#define BP_DRAM_CTL108_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL108_DLL_OBS_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL108_DLL_OBS_REG_1_1(v) (v) + +#define HW_DRAM_CTL109 (0x000001b4) + +#define BP_DRAM_CTL109_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL109_DLL_OBS_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL109_DLL_OBS_REG_1_1(v) (v) + +#define HW_DRAM_CTL110 (0x000001b8) + +#define BP_DRAM_CTL110_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL110_DLL_OBS_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL110_DLL_OBS_REG_1_1(v) (v) + +#define HW_DRAM_CTL111 (0x000001bc) + +#define BP_DRAM_CTL111_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL111_DLL_OBS_REG_1_1 0xFFFFFFFF +#define BF_DRAM_CTL111_DLL_OBS_REG_1_1(v) (v) + +#define HW_DRAM_CTL112 (0x000001c0) + +#define BP_DRAM_CTL112_OBSOLETE 16 +#define BM_DRAM_CTL112_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL112_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL112_OBSOLETE) +#define BP_DRAM_CTL112_RSVD1 9 +#define BM_DRAM_CTL112_RSVD1 0x0000FE00 +#define BF_DRAM_CTL112_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL112_RSVD1) +#define BP_DRAM_CTL112_DLL_OBS_REG_1_1 0 +#define BM_DRAM_CTL112_DLL_OBS_REG_1_1 0x000001FF +#define BF_DRAM_CTL112_DLL_OBS_REG_1_1(v) \ + (((v) << 0) & BM_DRAM_CTL112_DLL_OBS_REG_1_1) + +#define HW_DRAM_CTL113 (0x000001c4) + +#define BP_DRAM_CTL113_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL113_DLL_OBS_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL113_DLL_OBS_REG_1_2(v) (v) + +#define HW_DRAM_CTL114 (0x000001c8) + +#define BP_DRAM_CTL114_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL114_DLL_OBS_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL114_DLL_OBS_REG_1_2(v) (v) + +#define HW_DRAM_CTL115 (0x000001cc) + +#define BP_DRAM_CTL115_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL115_DLL_OBS_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL115_DLL_OBS_REG_1_2(v) (v) + +#define HW_DRAM_CTL116 (0x000001d0) + +#define BP_DRAM_CTL116_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL116_DLL_OBS_REG_1_2 0xFFFFFFFF +#define BF_DRAM_CTL116_DLL_OBS_REG_1_2(v) (v) + +#define HW_DRAM_CTL117 (0x000001d4) + +#define BP_DRAM_CTL117_OBSOLETE 16 +#define BM_DRAM_CTL117_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL117_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL117_OBSOLETE) +#define BP_DRAM_CTL117_RSVD1 9 +#define BM_DRAM_CTL117_RSVD1 0x0000FE00 +#define BF_DRAM_CTL117_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL117_RSVD1) +#define BP_DRAM_CTL117_DLL_OBS_REG_1_2 0 +#define BM_DRAM_CTL117_DLL_OBS_REG_1_2 0x000001FF +#define BF_DRAM_CTL117_DLL_OBS_REG_1_2(v) \ + (((v) << 0) & BM_DRAM_CTL117_DLL_OBS_REG_1_2) + +#define HW_DRAM_CTL118 (0x000001d8) + +#define BP_DRAM_CTL118_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL118_DLL_OBS_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL118_DLL_OBS_REG_1_3(v) (v) + +#define HW_DRAM_CTL119 (0x000001dc) + +#define BP_DRAM_CTL119_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL119_DLL_OBS_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL119_DLL_OBS_REG_1_3(v) (v) + +#define HW_DRAM_CTL120 (0x000001e0) + +#define BP_DRAM_CTL120_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL120_DLL_OBS_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL120_DLL_OBS_REG_1_3(v) (v) + +#define HW_DRAM_CTL121 (0x000001e4) + +#define BP_DRAM_CTL121_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL121_DLL_OBS_REG_1_3 0xFFFFFFFF +#define BF_DRAM_CTL121_DLL_OBS_REG_1_3(v) (v) + +#define HW_DRAM_CTL122 (0x000001e8) + +#define BP_DRAM_CTL122_OBSOLETE 16 +#define BM_DRAM_CTL122_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL122_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL122_OBSOLETE) +#define BP_DRAM_CTL122_RSVD1 9 +#define BM_DRAM_CTL122_RSVD1 0x0000FE00 +#define BF_DRAM_CTL122_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL122_RSVD1) +#define BP_DRAM_CTL122_DLL_OBS_REG_1_3 0 +#define BM_DRAM_CTL122_DLL_OBS_REG_1_3 0x000001FF +#define BF_DRAM_CTL122_DLL_OBS_REG_1_3(v) \ + (((v) << 0) & BM_DRAM_CTL122_DLL_OBS_REG_1_3) + +#define HW_DRAM_CTL123 (0x000001ec) + +#define BP_DRAM_CTL123_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL123_DLL_OBS_REG_2_0 0xFFFFFFFF +#define BF_DRAM_CTL123_DLL_OBS_REG_2_0(v) (v) + +#define HW_DRAM_CTL124 (0x000001f0) + +#define BP_DRAM_CTL124_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL124_DLL_OBS_REG_2_0 0xFFFFFFFF +#define BF_DRAM_CTL124_DLL_OBS_REG_2_0(v) (v) + +#define HW_DRAM_CTL125 (0x000001f4) + +#define BP_DRAM_CTL125_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL125_DLL_OBS_REG_2_0 0xFFFFFFFF +#define BF_DRAM_CTL125_DLL_OBS_REG_2_0(v) (v) + +#define HW_DRAM_CTL126 (0x000001f8) + +#define BP_DRAM_CTL126_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL126_DLL_OBS_REG_2_0 0xFFFFFFFF +#define BF_DRAM_CTL126_DLL_OBS_REG_2_0(v) (v) + +#define HW_DRAM_CTL127 (0x000001fc) + +#define BP_DRAM_CTL127_OBSOLETE 16 +#define BM_DRAM_CTL127_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL127_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL127_OBSOLETE) +#define BP_DRAM_CTL127_RSVD1 9 +#define BM_DRAM_CTL127_RSVD1 0x0000FE00 +#define BF_DRAM_CTL127_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL127_RSVD1) +#define BP_DRAM_CTL127_DLL_OBS_REG_2_0 0 +#define BM_DRAM_CTL127_DLL_OBS_REG_2_0 0x000001FF +#define BF_DRAM_CTL127_DLL_OBS_REG_2_0(v) \ + (((v) << 0) & BM_DRAM_CTL127_DLL_OBS_REG_2_0) + +#define HW_DRAM_CTL128 (0x00000200) + +#define BP_DRAM_CTL128_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL128_DLL_OBS_REG_2_1 0xFFFFFFFF +#define BF_DRAM_CTL128_DLL_OBS_REG_2_1(v) (v) + +#define HW_DRAM_CTL129 (0x00000204) + +#define BP_DRAM_CTL129_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL129_DLL_OBS_REG_2_1 0xFFFFFFFF +#define BF_DRAM_CTL129_DLL_OBS_REG_2_1(v) (v) + +#define HW_DRAM_CTL130 (0x00000208) + +#define BP_DRAM_CTL130_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL130_DLL_OBS_REG_2_1 0xFFFFFFFF +#define BF_DRAM_CTL130_DLL_OBS_REG_2_1(v) (v) + +#define HW_DRAM_CTL131 (0x0000020c) + +#define BP_DRAM_CTL131_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL131_DLL_OBS_REG_2_1 0xFFFFFFFF +#define BF_DRAM_CTL131_DLL_OBS_REG_2_1(v) (v) + +#define HW_DRAM_CTL132 (0x00000210) + +#define BP_DRAM_CTL132_OBSOLETE 16 +#define BM_DRAM_CTL132_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL132_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL132_OBSOLETE) +#define BP_DRAM_CTL132_RSVD1 9 +#define BM_DRAM_CTL132_RSVD1 0x0000FE00 +#define BF_DRAM_CTL132_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL132_RSVD1) +#define BP_DRAM_CTL132_DLL_OBS_REG_2_1 0 +#define BM_DRAM_CTL132_DLL_OBS_REG_2_1 0x000001FF +#define BF_DRAM_CTL132_DLL_OBS_REG_2_1(v) \ + (((v) << 0) & BM_DRAM_CTL132_DLL_OBS_REG_2_1) + +#define HW_DRAM_CTL133 (0x00000214) + +#define BP_DRAM_CTL133_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL133_DLL_OBS_REG_2_2 0xFFFFFFFF +#define BF_DRAM_CTL133_DLL_OBS_REG_2_2(v) (v) + +#define HW_DRAM_CTL134 (0x00000218) + +#define BP_DRAM_CTL134_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL134_DLL_OBS_REG_2_2 0xFFFFFFFF +#define BF_DRAM_CTL134_DLL_OBS_REG_2_2(v) (v) + +#define HW_DRAM_CTL135 (0x0000021c) + +#define BP_DRAM_CTL135_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL135_DLL_OBS_REG_2_2 0xFFFFFFFF +#define BF_DRAM_CTL135_DLL_OBS_REG_2_2(v) (v) + +#define HW_DRAM_CTL136 (0x00000220) + +#define BP_DRAM_CTL136_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL136_DLL_OBS_REG_2_2 0xFFFFFFFF +#define BF_DRAM_CTL136_DLL_OBS_REG_2_2(v) (v) + +#define HW_DRAM_CTL137 (0x00000224) + +#define BP_DRAM_CTL137_OBSOLETE 16 +#define BM_DRAM_CTL137_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL137_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL137_OBSOLETE) +#define BP_DRAM_CTL137_RSVD1 9 +#define BM_DRAM_CTL137_RSVD1 0x0000FE00 +#define BF_DRAM_CTL137_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL137_RSVD1) +#define BP_DRAM_CTL137_DLL_OBS_REG_2_2 0 +#define BM_DRAM_CTL137_DLL_OBS_REG_2_2 0x000001FF +#define BF_DRAM_CTL137_DLL_OBS_REG_2_2(v) \ + (((v) << 0) & BM_DRAM_CTL137_DLL_OBS_REG_2_2) + +#define HW_DRAM_CTL138 (0x00000228) + +#define BP_DRAM_CTL138_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL138_DLL_OBS_REG_2_3 0xFFFFFFFF +#define BF_DRAM_CTL138_DLL_OBS_REG_2_3(v) (v) + +#define HW_DRAM_CTL139 (0x0000022c) + +#define BP_DRAM_CTL139_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL139_DLL_OBS_REG_2_3 0xFFFFFFFF +#define BF_DRAM_CTL139_DLL_OBS_REG_2_3(v) (v) + +#define HW_DRAM_CTL140 (0x00000230) + +#define BP_DRAM_CTL140_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL140_DLL_OBS_REG_2_3 0xFFFFFFFF +#define BF_DRAM_CTL140_DLL_OBS_REG_2_3(v) (v) + +#define HW_DRAM_CTL141 (0x00000234) + +#define BP_DRAM_CTL141_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL141_DLL_OBS_REG_2_3 0xFFFFFFFF +#define BF_DRAM_CTL141_DLL_OBS_REG_2_3(v) (v) + +#define HW_DRAM_CTL142 (0x00000238) + +#define BP_DRAM_CTL142_OBSOLETE 16 +#define BM_DRAM_CTL142_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL142_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL142_OBSOLETE) +#define BP_DRAM_CTL142_RSVD1 9 +#define BM_DRAM_CTL142_RSVD1 0x0000FE00 +#define BF_DRAM_CTL142_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL142_RSVD1) +#define BP_DRAM_CTL142_DLL_OBS_REG_2_3 0 +#define BM_DRAM_CTL142_DLL_OBS_REG_2_3 0x000001FF +#define BF_DRAM_CTL142_DLL_OBS_REG_2_3(v) \ + (((v) << 0) & BM_DRAM_CTL142_DLL_OBS_REG_2_3) + +#define HW_DRAM_CTL143 (0x0000023c) + +#define BP_DRAM_CTL143_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL143_DLL_OBS_REG_3_0 0xFFFFFFFF +#define BF_DRAM_CTL143_DLL_OBS_REG_3_0(v) (v) + +#define HW_DRAM_CTL144 (0x00000240) + +#define BP_DRAM_CTL144_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL144_DLL_OBS_REG_3_0 0xFFFFFFFF +#define BF_DRAM_CTL144_DLL_OBS_REG_3_0(v) (v) + +#define HW_DRAM_CTL145 (0x00000244) + +#define BP_DRAM_CTL145_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL145_DLL_OBS_REG_3_0 0xFFFFFFFF +#define BF_DRAM_CTL145_DLL_OBS_REG_3_0(v) (v) + +#define HW_DRAM_CTL146 (0x00000248) + +#define BP_DRAM_CTL146_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL146_DLL_OBS_REG_3_0 0xFFFFFFFF +#define BF_DRAM_CTL146_DLL_OBS_REG_3_0(v) (v) + +#define HW_DRAM_CTL147 (0x0000024c) + +#define BP_DRAM_CTL147_OBSOLETE 16 +#define BM_DRAM_CTL147_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL147_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL147_OBSOLETE) +#define BP_DRAM_CTL147_RSVD1 9 +#define BM_DRAM_CTL147_RSVD1 0x0000FE00 +#define BF_DRAM_CTL147_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL147_RSVD1) +#define BP_DRAM_CTL147_DLL_OBS_REG_3_0 0 +#define BM_DRAM_CTL147_DLL_OBS_REG_3_0 0x000001FF +#define BF_DRAM_CTL147_DLL_OBS_REG_3_0(v) \ + (((v) << 0) & BM_DRAM_CTL147_DLL_OBS_REG_3_0) + +#define HW_DRAM_CTL148 (0x00000250) + +#define BP_DRAM_CTL148_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL148_DLL_OBS_REG_3_1 0xFFFFFFFF +#define BF_DRAM_CTL148_DLL_OBS_REG_3_1(v) (v) + +#define HW_DRAM_CTL149 (0x00000254) + +#define BP_DRAM_CTL149_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL149_DLL_OBS_REG_3_1 0xFFFFFFFF +#define BF_DRAM_CTL149_DLL_OBS_REG_3_1(v) (v) + +#define HW_DRAM_CTL150 (0x00000258) + +#define BP_DRAM_CTL150_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL150_DLL_OBS_REG_3_1 0xFFFFFFFF +#define BF_DRAM_CTL150_DLL_OBS_REG_3_1(v) (v) + +#define HW_DRAM_CTL151 (0x0000025c) + +#define BP_DRAM_CTL151_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL151_DLL_OBS_REG_3_1 0xFFFFFFFF +#define BF_DRAM_CTL151_DLL_OBS_REG_3_1(v) (v) + +#define HW_DRAM_CTL152 (0x00000260) + +#define BP_DRAM_CTL152_OBSOLETE 16 +#define BM_DRAM_CTL152_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL152_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL152_OBSOLETE) +#define BP_DRAM_CTL152_RSVD1 9 +#define BM_DRAM_CTL152_RSVD1 0x0000FE00 +#define BF_DRAM_CTL152_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL152_RSVD1) +#define BP_DRAM_CTL152_DLL_OBS_REG_3_1 0 +#define BM_DRAM_CTL152_DLL_OBS_REG_3_1 0x000001FF +#define BF_DRAM_CTL152_DLL_OBS_REG_3_1(v) \ + (((v) << 0) & BM_DRAM_CTL152_DLL_OBS_REG_3_1) + +#define HW_DRAM_CTL153 (0x00000264) + +#define BP_DRAM_CTL153_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL153_DLL_OBS_REG_3_2 0xFFFFFFFF +#define BF_DRAM_CTL153_DLL_OBS_REG_3_2(v) (v) + +#define HW_DRAM_CTL154 (0x00000268) + +#define BP_DRAM_CTL154_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL154_DLL_OBS_REG_3_2 0xFFFFFFFF +#define BF_DRAM_CTL154_DLL_OBS_REG_3_2(v) (v) + +#define HW_DRAM_CTL155 (0x0000026c) + +#define BP_DRAM_CTL155_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL155_DLL_OBS_REG_3_2 0xFFFFFFFF +#define BF_DRAM_CTL155_DLL_OBS_REG_3_2(v) (v) + +#define HW_DRAM_CTL156 (0x00000270) + +#define BP_DRAM_CTL156_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL156_DLL_OBS_REG_3_2 0xFFFFFFFF +#define BF_DRAM_CTL156_DLL_OBS_REG_3_2(v) (v) + +#define HW_DRAM_CTL157 (0x00000274) + +#define BP_DRAM_CTL157_OBSOLETE 16 +#define BM_DRAM_CTL157_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL157_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL157_OBSOLETE) +#define BP_DRAM_CTL157_RSVD1 9 +#define BM_DRAM_CTL157_RSVD1 0x0000FE00 +#define BF_DRAM_CTL157_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL157_RSVD1) +#define BP_DRAM_CTL157_DLL_OBS_REG_3_2 0 +#define BM_DRAM_CTL157_DLL_OBS_REG_3_2 0x000001FF +#define BF_DRAM_CTL157_DLL_OBS_REG_3_2(v) \ + (((v) << 0) & BM_DRAM_CTL157_DLL_OBS_REG_3_2) + +#define HW_DRAM_CTL158 (0x00000278) + +#define BP_DRAM_CTL158_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL158_DLL_OBS_REG_3_3 0xFFFFFFFF +#define BF_DRAM_CTL158_DLL_OBS_REG_3_3(v) (v) + +#define HW_DRAM_CTL159 (0x0000027c) + +#define BP_DRAM_CTL159_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL159_DLL_OBS_REG_3_3 0xFFFFFFFF +#define BF_DRAM_CTL159_DLL_OBS_REG_3_3(v) (v) + +#define HW_DRAM_CTL160 (0x00000280) + +#define BP_DRAM_CTL160_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL160_DLL_OBS_REG_3_3 0xFFFFFFFF +#define BF_DRAM_CTL160_DLL_OBS_REG_3_3(v) (v) + +#define HW_DRAM_CTL161 (0x00000284) + +#define BP_DRAM_CTL161_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL161_DLL_OBS_REG_3_3 0xFFFFFFFF +#define BF_DRAM_CTL161_DLL_OBS_REG_3_3(v) (v) + +#define HW_DRAM_CTL162 (0x00000288) + +#define BP_DRAM_CTL162_RSVD3 27 +#define BM_DRAM_CTL162_RSVD3 0xF8000000 +#define BF_DRAM_CTL162_RSVD3(v) \ + (((v) << 27) & BM_DRAM_CTL162_RSVD3) +#define BP_DRAM_CTL162_W2R_SAMECS_DLY 24 +#define BM_DRAM_CTL162_W2R_SAMECS_DLY 0x07000000 +#define BF_DRAM_CTL162_W2R_SAMECS_DLY(v) \ + (((v) << 24) & BM_DRAM_CTL162_W2R_SAMECS_DLY) +#define BP_DRAM_CTL162_RSVD2 19 +#define BM_DRAM_CTL162_RSVD2 0x00F80000 +#define BF_DRAM_CTL162_RSVD2(v) \ + (((v) << 19) & BM_DRAM_CTL162_RSVD2) +#define BP_DRAM_CTL162_W2R_DIFFCS_DLY 16 +#define BM_DRAM_CTL162_W2R_DIFFCS_DLY 0x00070000 +#define BF_DRAM_CTL162_W2R_DIFFCS_DLY(v) \ + (((v) << 16) & BM_DRAM_CTL162_W2R_DIFFCS_DLY) +#define BP_DRAM_CTL162_RSVD1 9 +#define BM_DRAM_CTL162_RSVD1 0x0000FE00 +#define BF_DRAM_CTL162_RSVD1(v) \ + (((v) << 9) & BM_DRAM_CTL162_RSVD1) +#define BP_DRAM_CTL162_DLL_OBS_REG_3_3 0 +#define BM_DRAM_CTL162_DLL_OBS_REG_3_3 0x000001FF +#define BF_DRAM_CTL162_DLL_OBS_REG_3_3(v) \ + (((v) << 0) & BM_DRAM_CTL162_DLL_OBS_REG_3_3) + +#define HW_DRAM_CTL163 (0x0000028c) + +#define BP_DRAM_CTL163_DLL_RST_ADJ_DLY 24 +#define BM_DRAM_CTL163_DLL_RST_ADJ_DLY 0xFF000000 +#define BF_DRAM_CTL163_DLL_RST_ADJ_DLY(v) \ + (((v) << 24) & BM_DRAM_CTL163_DLL_RST_ADJ_DLY) +#define BP_DRAM_CTL163_RSVD3 20 +#define BM_DRAM_CTL163_RSVD3 0x00F00000 +#define BF_DRAM_CTL163_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL163_RSVD3) +#define BP_DRAM_CTL163_WRLAT_ADJ 16 +#define BM_DRAM_CTL163_WRLAT_ADJ 0x000F0000 +#define BF_DRAM_CTL163_WRLAT_ADJ(v) \ + (((v) << 16) & BM_DRAM_CTL163_WRLAT_ADJ) +#define BP_DRAM_CTL163_RSVD2 12 +#define BM_DRAM_CTL163_RSVD2 0x0000F000 +#define BF_DRAM_CTL163_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL163_RSVD2) +#define BP_DRAM_CTL163_RDLAT_ADJ 8 +#define BM_DRAM_CTL163_RDLAT_ADJ 0x00000F00 +#define BF_DRAM_CTL163_RDLAT_ADJ(v) \ + (((v) << 8) & BM_DRAM_CTL163_RDLAT_ADJ) +#define BP_DRAM_CTL163_RSVD1 4 +#define BM_DRAM_CTL163_RSVD1 0x000000F0 +#define BF_DRAM_CTL163_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL163_RSVD1) +#define BP_DRAM_CTL163_DRAM_CLASS 0 +#define BM_DRAM_CTL163_DRAM_CLASS 0x0000000F +#define BF_DRAM_CTL163_DRAM_CLASS(v) \ + (((v) << 0) & BM_DRAM_CTL163_DRAM_CLASS) + +#define HW_DRAM_CTL164 (0x00000290) + +#define BP_DRAM_CTL164_OBSOLETE 24 +#define BM_DRAM_CTL164_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL164_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL164_OBSOLETE) +#define BP_DRAM_CTL164_RSVD1 18 +#define BM_DRAM_CTL164_RSVD1 0x00FC0000 +#define BF_DRAM_CTL164_RSVD1(v) \ + (((v) << 18) & BM_DRAM_CTL164_RSVD1) +#define BP_DRAM_CTL164_INT_ACK 8 +#define BM_DRAM_CTL164_INT_ACK 0x0003FF00 +#define BF_DRAM_CTL164_INT_ACK(v) \ + (((v) << 8) & BM_DRAM_CTL164_INT_ACK) +#define BP_DRAM_CTL164_TMOD 0 +#define BM_DRAM_CTL164_TMOD 0x000000FF +#define BF_DRAM_CTL164_TMOD(v) \ + (((v) << 0) & BM_DRAM_CTL164_TMOD) + +#define HW_DRAM_CTL171 (0x000002ac) + +#define BP_DRAM_CTL171_RSVD2 25 +#define BM_DRAM_CTL171_RSVD2 0xFE000000 +#define BF_DRAM_CTL171_RSVD2(v) \ + (((v) << 25) & BM_DRAM_CTL171_RSVD2) +#define BM_DRAM_CTL171_AXI5_BDW_OVFLOW 0x01000000 +#define BP_DRAM_CTL171_RSVD1 17 +#define BM_DRAM_CTL171_RSVD1 0x00FE0000 +#define BF_DRAM_CTL171_RSVD1(v) \ + (((v) << 17) & BM_DRAM_CTL171_RSVD1) +#define BM_DRAM_CTL171_AXI4_BDW_OVFLOW 0x00010000 +#define BP_DRAM_CTL171_DLL_RST_DELAY 0 +#define BM_DRAM_CTL171_DLL_RST_DELAY 0x0000FFFF +#define BF_DRAM_CTL171_DLL_RST_DELAY(v) \ + (((v) << 0) & BM_DRAM_CTL171_DLL_RST_DELAY) + +#define HW_DRAM_CTL172 (0x000002b0) + +#define BP_DRAM_CTL172_RSVD4 25 +#define BM_DRAM_CTL172_RSVD4 0xFE000000 +#define BF_DRAM_CTL172_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL172_RSVD4) +#define BM_DRAM_CTL172_RESYNC_DLL_PER_AREF_EN 0x01000000 +#define BP_DRAM_CTL172_RSVD3 17 +#define BM_DRAM_CTL172_RSVD3 0x00FE0000 +#define BF_DRAM_CTL172_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL172_RSVD3) +#define BM_DRAM_CTL172_RESYNC_DLL 0x00010000 +#define BP_DRAM_CTL172_RSVD2 9 +#define BM_DRAM_CTL172_RSVD2 0x0000FE00 +#define BF_DRAM_CTL172_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL172_RSVD2) +#define BM_DRAM_CTL172_CONCURRENTAP_WR_ONLY 0x00000100 +#define BP_DRAM_CTL172_RSVD1 1 +#define BM_DRAM_CTL172_RSVD1 0x000000FE +#define BF_DRAM_CTL172_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL172_RSVD1) +#define BM_DRAM_CTL172_CKE_STATUS 0x00000001 + +#define HW_DRAM_CTL173 (0x000002b4) + +#define BP_DRAM_CTL173_RSVD4 27 +#define BM_DRAM_CTL173_RSVD4 0xF8000000 +#define BF_DRAM_CTL173_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL173_RSVD4) +#define BP_DRAM_CTL173_AXI4_W_PRIORITY 24 +#define BM_DRAM_CTL173_AXI4_W_PRIORITY 0x07000000 +#define BF_DRAM_CTL173_AXI4_W_PRIORITY(v) \ + (((v) << 24) & BM_DRAM_CTL173_AXI4_W_PRIORITY) +#define BP_DRAM_CTL173_RSVD3 19 +#define BM_DRAM_CTL173_RSVD3 0x00F80000 +#define BF_DRAM_CTL173_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL173_RSVD3) +#define BP_DRAM_CTL173_AXI4_R_PRIORITY 16 +#define BM_DRAM_CTL173_AXI4_R_PRIORITY 0x00070000 +#define BF_DRAM_CTL173_AXI4_R_PRIORITY(v) \ + (((v) << 16) & BM_DRAM_CTL173_AXI4_R_PRIORITY) +#define BP_DRAM_CTL173_RSVD2 10 +#define BM_DRAM_CTL173_RSVD2 0x0000FC00 +#define BF_DRAM_CTL173_RSVD2(v) \ + (((v) << 10) & BM_DRAM_CTL173_RSVD2) +#define BP_DRAM_CTL173_AXI5_FIFO_TYPE_REG 8 +#define BM_DRAM_CTL173_AXI5_FIFO_TYPE_REG 0x00000300 +#define BF_DRAM_CTL173_AXI5_FIFO_TYPE_REG(v) \ + (((v) << 8) & BM_DRAM_CTL173_AXI5_FIFO_TYPE_REG) +#define BP_DRAM_CTL173_RSVD1 2 +#define BM_DRAM_CTL173_RSVD1 0x000000FC +#define BF_DRAM_CTL173_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL173_RSVD1) +#define BP_DRAM_CTL173_AXI4_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL173_AXI4_FIFO_TYPE_REG 0x00000003 +#define BF_DRAM_CTL173_AXI4_FIFO_TYPE_REG(v) \ + (((v) << 0) & BM_DRAM_CTL173_AXI4_FIFO_TYPE_REG) + +#define HW_DRAM_CTL174 (0x000002b8) + +#define BP_DRAM_CTL174_RSVD4 27 +#define BM_DRAM_CTL174_RSVD4 0xF8000000 +#define BF_DRAM_CTL174_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL174_RSVD4) +#define BP_DRAM_CTL174_R2R_SAMECS_DLY 24 +#define BM_DRAM_CTL174_R2R_SAMECS_DLY 0x07000000 +#define BF_DRAM_CTL174_R2R_SAMECS_DLY(v) \ + (((v) << 24) & BM_DRAM_CTL174_R2R_SAMECS_DLY) +#define BP_DRAM_CTL174_RSVD3 19 +#define BM_DRAM_CTL174_RSVD3 0x00F80000 +#define BF_DRAM_CTL174_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL174_RSVD3) +#define BP_DRAM_CTL174_R2R_DIFFCS_DLY 16 +#define BM_DRAM_CTL174_R2R_DIFFCS_DLY 0x00070000 +#define BF_DRAM_CTL174_R2R_DIFFCS_DLY(v) \ + (((v) << 16) & BM_DRAM_CTL174_R2R_DIFFCS_DLY) +#define BP_DRAM_CTL174_RSVD2 11 +#define BM_DRAM_CTL174_RSVD2 0x0000F800 +#define BF_DRAM_CTL174_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL174_RSVD2) +#define BP_DRAM_CTL174_AXI5_W_PRIORITY 8 +#define BM_DRAM_CTL174_AXI5_W_PRIORITY 0x00000700 +#define BF_DRAM_CTL174_AXI5_W_PRIORITY(v) \ + (((v) << 8) & BM_DRAM_CTL174_AXI5_W_PRIORITY) +#define BP_DRAM_CTL174_RSVD1 3 +#define BM_DRAM_CTL174_RSVD1 0x000000F8 +#define BF_DRAM_CTL174_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL174_RSVD1) +#define BP_DRAM_CTL174_AXI5_R_PRIORITY 0 +#define BM_DRAM_CTL174_AXI5_R_PRIORITY 0x00000007 +#define BF_DRAM_CTL174_AXI5_R_PRIORITY(v) \ + (((v) << 0) & BM_DRAM_CTL174_AXI5_R_PRIORITY) + +#define HW_DRAM_CTL175 (0x000002bc) + +#define BP_DRAM_CTL175_RSVD4 27 +#define BM_DRAM_CTL175_RSVD4 0xF8000000 +#define BF_DRAM_CTL175_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL175_RSVD4) +#define BP_DRAM_CTL175_W2W_DIFFCS_DLY 24 +#define BM_DRAM_CTL175_W2W_DIFFCS_DLY 0x07000000 +#define BF_DRAM_CTL175_W2W_DIFFCS_DLY(v) \ + (((v) << 24) & BM_DRAM_CTL175_W2W_DIFFCS_DLY) +#define BP_DRAM_CTL175_RSVD3 19 +#define BM_DRAM_CTL175_RSVD3 0x00F80000 +#define BF_DRAM_CTL175_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL175_RSVD3) +#define BP_DRAM_CTL175_TBST_INT_INTERVAL 16 +#define BM_DRAM_CTL175_TBST_INT_INTERVAL 0x00070000 +#define BF_DRAM_CTL175_TBST_INT_INTERVAL(v) \ + (((v) << 16) & BM_DRAM_CTL175_TBST_INT_INTERVAL) +#define BP_DRAM_CTL175_RSVD2 11 +#define BM_DRAM_CTL175_RSVD2 0x0000F800 +#define BF_DRAM_CTL175_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL175_RSVD2) +#define BP_DRAM_CTL175_R2W_SAMECS_DLY 8 +#define BM_DRAM_CTL175_R2W_SAMECS_DLY 0x00000700 +#define BF_DRAM_CTL175_R2W_SAMECS_DLY(v) \ + (((v) << 8) & BM_DRAM_CTL175_R2W_SAMECS_DLY) +#define BP_DRAM_CTL175_RSVD1 3 +#define BM_DRAM_CTL175_RSVD1 0x000000F8 +#define BF_DRAM_CTL175_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL175_RSVD1) +#define BP_DRAM_CTL175_R2W_DIFFCS_DLY 0 +#define BM_DRAM_CTL175_R2W_DIFFCS_DLY 0x00000007 +#define BF_DRAM_CTL175_R2W_DIFFCS_DLY(v) \ + (((v) << 0) & BM_DRAM_CTL175_R2W_DIFFCS_DLY) + +#define HW_DRAM_CTL176 (0x000002c0) + +#define BP_DRAM_CTL176_RSVD4 28 +#define BM_DRAM_CTL176_RSVD4 0xF0000000 +#define BF_DRAM_CTL176_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL176_RSVD4) +#define BP_DRAM_CTL176_ADD_ODT_CLK_SAMETYPE_DIFFCS 24 +#define BM_DRAM_CTL176_ADD_ODT_CLK_SAMETYPE_DIFFCS 0x0F000000 +#define BF_DRAM_CTL176_ADD_ODT_CLK_SAMETYPE_DIFFCS(v) \ + (((v) << 24) & BM_DRAM_CTL176_ADD_ODT_CLK_SAMETYPE_DIFFCS) +#define BP_DRAM_CTL176_RSVD3 20 +#define BM_DRAM_CTL176_RSVD3 0x00F00000 +#define BF_DRAM_CTL176_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL176_RSVD3) +#define BP_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_SAMECS 16 +#define BM_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_SAMECS 0x000F0000 +#define BF_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_SAMECS(v) \ + (((v) << 16) & BM_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_SAMECS) +#define BP_DRAM_CTL176_RSVD2 12 +#define BM_DRAM_CTL176_RSVD2 0x0000F000 +#define BF_DRAM_CTL176_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL176_RSVD2) +#define BP_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_DIFFCS 8 +#define BM_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_DIFFCS 0x00000F00 +#define BF_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_DIFFCS(v) \ + (((v) << 8) & BM_DRAM_CTL176_ADD_ODT_CLK_DIFFTYPE_DIFFCS) +#define BP_DRAM_CTL176_RSVD1 3 +#define BM_DRAM_CTL176_RSVD1 0x000000F8 +#define BF_DRAM_CTL176_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL176_RSVD1) +#define BP_DRAM_CTL176_W2W_SAMECS_DLY 0 +#define BM_DRAM_CTL176_W2W_SAMECS_DLY 0x00000007 +#define BF_DRAM_CTL176_W2W_SAMECS_DLY(v) \ + (((v) << 0) & BM_DRAM_CTL176_W2W_SAMECS_DLY) + +#define HW_DRAM_CTL177 (0x000002c4) + +#define BP_DRAM_CTL177_RSVD4 29 +#define BM_DRAM_CTL177_RSVD4 0xE0000000 +#define BF_DRAM_CTL177_RSVD4(v) \ + (((v) << 29) & BM_DRAM_CTL177_RSVD4) +#define BP_DRAM_CTL177_TCCD 24 +#define BM_DRAM_CTL177_TCCD 0x1F000000 +#define BF_DRAM_CTL177_TCCD(v) \ + (((v) << 24) & BM_DRAM_CTL177_TCCD) +#define BP_DRAM_CTL177_RSVD3 20 +#define BM_DRAM_CTL177_RSVD3 0x00F00000 +#define BF_DRAM_CTL177_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL177_RSVD3) +#define BP_DRAM_CTL177_TRP_AB 16 +#define BM_DRAM_CTL177_TRP_AB 0x000F0000 +#define BF_DRAM_CTL177_TRP_AB(v) \ + (((v) << 16) & BM_DRAM_CTL177_TRP_AB) +#define BP_DRAM_CTL177_RSVD2 12 +#define BM_DRAM_CTL177_RSVD2 0x0000F000 +#define BF_DRAM_CTL177_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL177_RSVD2) +#define BP_DRAM_CTL177_CKSRX 8 +#define BM_DRAM_CTL177_CKSRX 0x00000F00 +#define BF_DRAM_CTL177_CKSRX(v) \ + (((v) << 8) & BM_DRAM_CTL177_CKSRX) +#define BP_DRAM_CTL177_RSVD1 4 +#define BM_DRAM_CTL177_RSVD1 0x000000F0 +#define BF_DRAM_CTL177_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL177_RSVD1) +#define BP_DRAM_CTL177_CKSRE 0 +#define BM_DRAM_CTL177_CKSRE 0x0000000F +#define BF_DRAM_CTL177_CKSRE(v) \ + (((v) << 0) & BM_DRAM_CTL177_CKSRE) + +#define HW_DRAM_CTL178 (0x000002c8) + +#define BM_DRAM_CTL178_RSVD4 0x80000000 +#define BP_DRAM_CTL178_AXI5_BDW 24 +#define BM_DRAM_CTL178_AXI5_BDW 0x7F000000 +#define BF_DRAM_CTL178_AXI5_BDW(v) \ + (((v) << 24) & BM_DRAM_CTL178_AXI5_BDW) +#define BM_DRAM_CTL178_RSVD3 0x00800000 +#define BP_DRAM_CTL178_AXI4_CURRENT_BDW 16 +#define BM_DRAM_CTL178_AXI4_CURRENT_BDW 0x007F0000 +#define BF_DRAM_CTL178_AXI4_CURRENT_BDW(v) \ + (((v) << 16) & BM_DRAM_CTL178_AXI4_CURRENT_BDW) +#define BM_DRAM_CTL178_RSVD2 0x00008000 +#define BP_DRAM_CTL178_AXI4_BDW 8 +#define BM_DRAM_CTL178_AXI4_BDW 0x00007F00 +#define BF_DRAM_CTL178_AXI4_BDW(v) \ + (((v) << 8) & BM_DRAM_CTL178_AXI4_BDW) +#define BP_DRAM_CTL178_RSVD1 5 +#define BM_DRAM_CTL178_RSVD1 0x000000E0 +#define BF_DRAM_CTL178_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL178_RSVD1) +#define BP_DRAM_CTL178_TCKESR 0 +#define BM_DRAM_CTL178_TCKESR 0x0000001F +#define BF_DRAM_CTL178_TCKESR(v) \ + (((v) << 0) & BM_DRAM_CTL178_TCKESR) + +#define HW_DRAM_CTL179 (0x000002cc) + +#define BP_DRAM_CTL179_RSVD3 24 +#define BM_DRAM_CTL179_RSVD3 0xFF000000 +#define BF_DRAM_CTL179_RSVD3(v) \ + (((v) << 24) & BM_DRAM_CTL179_RSVD3) +#define BP_DRAM_CTL179_RSVD2 22 +#define BM_DRAM_CTL179_RSVD2 0x00C00000 +#define BF_DRAM_CTL179_RSVD2(v) \ + (((v) << 22) & BM_DRAM_CTL179_RSVD2) +#define BP_DRAM_CTL179_TDFI_PHYUPD_TYPE1 8 +#define BM_DRAM_CTL179_TDFI_PHYUPD_TYPE1 0x003FFF00 +#define BF_DRAM_CTL179_TDFI_PHYUPD_TYPE1(v) \ + (((v) << 8) & BM_DRAM_CTL179_TDFI_PHYUPD_TYPE1) +#define BM_DRAM_CTL179_RSVD1 0x00000080 +#define BP_DRAM_CTL179_AXI5_CURRENT_BDW 0 +#define BM_DRAM_CTL179_AXI5_CURRENT_BDW 0x0000007F +#define BF_DRAM_CTL179_AXI5_CURRENT_BDW(v) \ + (((v) << 0) & BM_DRAM_CTL179_AXI5_CURRENT_BDW) + +#define HW_DRAM_CTL180 (0x000002d0) + +#define BP_DRAM_CTL180_RSVD2 30 +#define BM_DRAM_CTL180_RSVD2 0xC0000000 +#define BF_DRAM_CTL180_RSVD2(v) \ + (((v) << 30) & BM_DRAM_CTL180_RSVD2) +#define BP_DRAM_CTL180_TDFI_PHYUPD_TYPE3 16 +#define BM_DRAM_CTL180_TDFI_PHYUPD_TYPE3 0x3FFF0000 +#define BF_DRAM_CTL180_TDFI_PHYUPD_TYPE3(v) \ + (((v) << 16) & BM_DRAM_CTL180_TDFI_PHYUPD_TYPE3) +#define BP_DRAM_CTL180_RSVD1 14 +#define BM_DRAM_CTL180_RSVD1 0x0000C000 +#define BF_DRAM_CTL180_RSVD1(v) \ + (((v) << 14) & BM_DRAM_CTL180_RSVD1) +#define BP_DRAM_CTL180_TDFI_PHYUPD_TYPE2 0 +#define BM_DRAM_CTL180_TDFI_PHYUPD_TYPE2 0x00003FFF +#define BF_DRAM_CTL180_TDFI_PHYUPD_TYPE2(v) \ + (((v) << 0) & BM_DRAM_CTL180_TDFI_PHYUPD_TYPE2) + +#define HW_DRAM_CTL181 (0x000002d4) + +#define BM_DRAM_CTL181_RSVD2 0x80000000 +#define BP_DRAM_CTL181_MR0_DATA_1 16 +#define BM_DRAM_CTL181_MR0_DATA_1 0x7FFF0000 +#define BF_DRAM_CTL181_MR0_DATA_1(v) \ + (((v) << 16) & BM_DRAM_CTL181_MR0_DATA_1) +#define BM_DRAM_CTL181_RSVD1 0x00008000 +#define BP_DRAM_CTL181_MR0_DATA_0 0 +#define BM_DRAM_CTL181_MR0_DATA_0 0x00007FFF +#define BF_DRAM_CTL181_MR0_DATA_0(v) \ + (((v) << 0) & BM_DRAM_CTL181_MR0_DATA_0) + +#define HW_DRAM_CTL182 (0x000002d8) + +#define BM_DRAM_CTL182_RSVD2 0x80000000 +#define BP_DRAM_CTL182_MR0_DATA_3 16 +#define BM_DRAM_CTL182_MR0_DATA_3 0x7FFF0000 +#define BF_DRAM_CTL182_MR0_DATA_3(v) \ + (((v) << 16) & BM_DRAM_CTL182_MR0_DATA_3) +#define BM_DRAM_CTL182_RSVD1 0x00008000 +#define BP_DRAM_CTL182_MR0_DATA_2 0 +#define BM_DRAM_CTL182_MR0_DATA_2 0x00007FFF +#define BF_DRAM_CTL182_MR0_DATA_2(v) \ + (((v) << 0) & BM_DRAM_CTL182_MR0_DATA_2) + +#define HW_DRAM_CTL183 (0x000002dc) + +#define BM_DRAM_CTL183_RSVD2 0x80000000 +#define BP_DRAM_CTL183_MR1_DATA_1 16 +#define BM_DRAM_CTL183_MR1_DATA_1 0x7FFF0000 +#define BF_DRAM_CTL183_MR1_DATA_1(v) \ + (((v) << 16) & BM_DRAM_CTL183_MR1_DATA_1) +#define BM_DRAM_CTL183_RSVD1 0x00008000 +#define BP_DRAM_CTL183_MR1_DATA_0 0 +#define BM_DRAM_CTL183_MR1_DATA_0 0x00007FFF +#define BF_DRAM_CTL183_MR1_DATA_0(v) \ + (((v) << 0) & BM_DRAM_CTL183_MR1_DATA_0) + +#define HW_DRAM_CTL184 (0x000002e0) + +#define BM_DRAM_CTL184_RSVD2 0x80000000 +#define BP_DRAM_CTL184_MR1_DATA_3 16 +#define BM_DRAM_CTL184_MR1_DATA_3 0x7FFF0000 +#define BF_DRAM_CTL184_MR1_DATA_3(v) \ + (((v) << 16) & BM_DRAM_CTL184_MR1_DATA_3) +#define BM_DRAM_CTL184_RSVD1 0x00008000 +#define BP_DRAM_CTL184_MR1_DATA_2 0 +#define BM_DRAM_CTL184_MR1_DATA_2 0x00007FFF +#define BF_DRAM_CTL184_MR1_DATA_2(v) \ + (((v) << 0) & BM_DRAM_CTL184_MR1_DATA_2) + +#define HW_DRAM_CTL185 (0x000002e4) + +#define BM_DRAM_CTL185_RSVD2 0x80000000 +#define BP_DRAM_CTL185_MR2_DATA_1 16 +#define BM_DRAM_CTL185_MR2_DATA_1 0x7FFF0000 +#define BF_DRAM_CTL185_MR2_DATA_1(v) \ + (((v) << 16) & BM_DRAM_CTL185_MR2_DATA_1) +#define BM_DRAM_CTL185_RSVD1 0x00008000 +#define BP_DRAM_CTL185_MR2_DATA_0 0 +#define BM_DRAM_CTL185_MR2_DATA_0 0x00007FFF +#define BF_DRAM_CTL185_MR2_DATA_0(v) \ + (((v) << 0) & BM_DRAM_CTL185_MR2_DATA_0) + +#define HW_DRAM_CTL186 (0x000002e8) + +#define BM_DRAM_CTL186_RSVD2 0x80000000 +#define BP_DRAM_CTL186_MR2_DATA_3 16 +#define BM_DRAM_CTL186_MR2_DATA_3 0x7FFF0000 +#define BF_DRAM_CTL186_MR2_DATA_3(v) \ + (((v) << 16) & BM_DRAM_CTL186_MR2_DATA_3) +#define BM_DRAM_CTL186_RSVD1 0x00008000 +#define BP_DRAM_CTL186_MR2_DATA_2 0 +#define BM_DRAM_CTL186_MR2_DATA_2 0x00007FFF +#define BF_DRAM_CTL186_MR2_DATA_2(v) \ + (((v) << 0) & BM_DRAM_CTL186_MR2_DATA_2) + +#define HW_DRAM_CTL187 (0x000002ec) + +#define BM_DRAM_CTL187_RSVD2 0x80000000 +#define BP_DRAM_CTL187_MR3_DATA_1 16 +#define BM_DRAM_CTL187_MR3_DATA_1 0x7FFF0000 +#define BF_DRAM_CTL187_MR3_DATA_1(v) \ + (((v) << 16) & BM_DRAM_CTL187_MR3_DATA_1) +#define BM_DRAM_CTL187_RSVD1 0x00008000 +#define BP_DRAM_CTL187_MR3_DATA_0 0 +#define BM_DRAM_CTL187_MR3_DATA_0 0x00007FFF +#define BF_DRAM_CTL187_MR3_DATA_0(v) \ + (((v) << 0) & BM_DRAM_CTL187_MR3_DATA_0) + +#define HW_DRAM_CTL188 (0x000002f0) + +#define BM_DRAM_CTL188_RSVD2 0x80000000 +#define BP_DRAM_CTL188_MR3_DATA_3 16 +#define BM_DRAM_CTL188_MR3_DATA_3 0x7FFF0000 +#define BF_DRAM_CTL188_MR3_DATA_3(v) \ + (((v) << 16) & BM_DRAM_CTL188_MR3_DATA_3) +#define BM_DRAM_CTL188_RSVD1 0x00008000 +#define BP_DRAM_CTL188_MR3_DATA_2 0 +#define BM_DRAM_CTL188_MR3_DATA_2 0x00007FFF +#define BF_DRAM_CTL188_MR3_DATA_2(v) \ + (((v) << 0) & BM_DRAM_CTL188_MR3_DATA_2) + +#define HW_DRAM_CTL189 (0x000002f4) + +#define BP_DRAM_CTL189_AXI5_EN_SIZE_LT_WIDTH_INSTR 16 +#define BM_DRAM_CTL189_AXI5_EN_SIZE_LT_WIDTH_INSTR 0xFFFF0000 +#define BF_DRAM_CTL189_AXI5_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 16) & BM_DRAM_CTL189_AXI5_EN_SIZE_LT_WIDTH_INSTR) +#define BP_DRAM_CTL189_AXI4_EN_SIZE_LT_WIDTH_INSTR 0 +#define BM_DRAM_CTL189_AXI4_EN_SIZE_LT_WIDTH_INSTR 0x0000FFFF +#define BF_DRAM_CTL189_AXI4_EN_SIZE_LT_WIDTH_INSTR(v) \ + (((v) << 0) & BM_DRAM_CTL189_AXI4_EN_SIZE_LT_WIDTH_INSTR) +#endif /* __ARCH_ARM___DRAM_H */ diff --git a/arch/arm/mach-mx28/regs-pinctrl.h b/arch/arm/mach-mx28/regs-pinctrl.h new file mode 100644 index 000000000000..03c7f15da080 --- /dev/null +++ b/arch/arm/mach-mx28/regs-pinctrl.h @@ -0,0 +1,2673 @@ +/* + * Freescale PINCTRL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.19 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H + +#define HW_PINCTRL_CTRL (0x00000000) +#define HW_PINCTRL_CTRL_SET (0x00000004) +#define HW_PINCTRL_CTRL_CLR (0x00000008) +#define HW_PINCTRL_CTRL_TOG (0x0000000c) + +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BP_PINCTRL_CTRL_RSRVD2 25 +#define BM_PINCTRL_CTRL_RSRVD2 0x3E000000 +#define BF_PINCTRL_CTRL_RSRVD2(v) \ + (((v) << 25) & BM_PINCTRL_CTRL_RSRVD2) +#define BM_PINCTRL_CTRL_PRESENT4 0x01000000 +#define BM_PINCTRL_CTRL_PRESENT3 0x00800000 +#define BM_PINCTRL_CTRL_PRESENT2 0x00400000 +#define BM_PINCTRL_CTRL_PRESENT1 0x00200000 +#define BM_PINCTRL_CTRL_PRESENT0 0x00100000 +#define BP_PINCTRL_CTRL_RSRVD1 5 +#define BM_PINCTRL_CTRL_RSRVD1 0x000FFFE0 +#define BF_PINCTRL_CTRL_RSRVD1(v) \ + (((v) << 5) & BM_PINCTRL_CTRL_RSRVD1) +#define BM_PINCTRL_CTRL_IRQOUT4 0x00000010 +#define BM_PINCTRL_CTRL_IRQOUT3 0x00000008 +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 + +#define HW_PINCTRL_MUXSEL0 (0x00000100) +#define HW_PINCTRL_MUXSEL0_SET (0x00000104) +#define HW_PINCTRL_MUXSEL0_CLR (0x00000108) +#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c) + +#define BP_PINCTRL_MUXSEL0_RSRVD0 16 +#define BM_PINCTRL_MUXSEL0_RSRVD0 0xFFFF0000 +#define BF_PINCTRL_MUXSEL0_RSRVD0(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL0_RSRVD0) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00) + +#define HW_PINCTRL_MUXSEL1 (0x00000110) +#define HW_PINCTRL_MUXSEL1_SET (0x00000114) +#define HW_PINCTRL_MUXSEL1_CLR (0x00000118) +#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c) + +#define BP_PINCTRL_MUXSEL1_RSRVD0 26 +#define BM_PINCTRL_MUXSEL1_RSRVD0 0xFC000000 +#define BF_PINCTRL_MUXSEL1_RSRVD0(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL1_RSRVD0) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16) + +#define HW_PINCTRL_MUXSEL2 (0x00000120) +#define HW_PINCTRL_MUXSEL2_SET (0x00000124) +#define HW_PINCTRL_MUXSEL2_CLR (0x00000128) +#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c) + +#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00) + +#define HW_PINCTRL_MUXSEL3 (0x00000130) +#define HW_PINCTRL_MUXSEL3_SET (0x00000134) +#define HW_PINCTRL_MUXSEL3_CLR (0x00000138) +#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c) + +#define BP_PINCTRL_MUXSEL3_BANK1_PIN31 30 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL3_BANK1_PIN31) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16) + +#define HW_PINCTRL_MUXSEL4 (0x00000140) +#define HW_PINCTRL_MUXSEL4_SET (0x00000144) +#define HW_PINCTRL_MUXSEL4_CLR (0x00000148) +#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c) + +#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12) +#define BP_PINCTRL_MUXSEL4_RSRVD0 22 +#define BM_PINCTRL_MUXSEL4_RSRVD0 0x00C00000 +#define BF_PINCTRL_MUXSEL4_RSRVD0(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL4_RSRVD0) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00) + +#define HW_PINCTRL_MUXSEL5 (0x00000150) +#define HW_PINCTRL_MUXSEL5_SET (0x00000154) +#define HW_PINCTRL_MUXSEL5_CLR (0x00000158) +#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c) + +#define BP_PINCTRL_MUXSEL5_RSRVD1 24 +#define BM_PINCTRL_MUXSEL5_RSRVD1 0xFF000000 +#define BF_PINCTRL_MUXSEL5_RSRVD1(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL5_RSRVD1) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24) +#define BP_PINCTRL_MUXSEL5_RSRVD0 12 +#define BM_PINCTRL_MUXSEL5_RSRVD0 0x0000F000 +#define BF_PINCTRL_MUXSEL5_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL5_RSRVD0) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16) + +#define HW_PINCTRL_MUXSEL6 (0x00000160) +#define HW_PINCTRL_MUXSEL6_SET (0x00000164) +#define HW_PINCTRL_MUXSEL6_CLR (0x00000168) +#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c) + +#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00) + +#define HW_PINCTRL_MUXSEL7 (0x00000170) +#define HW_PINCTRL_MUXSEL7_SET (0x00000174) +#define HW_PINCTRL_MUXSEL7_CLR (0x00000178) +#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c) + +#define BP_PINCTRL_MUXSEL7_RSRVD1 30 +#define BM_PINCTRL_MUXSEL7_RSRVD1 0xC0000000 +#define BF_PINCTRL_MUXSEL7_RSRVD1(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL7_RSRVD1) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN30 28 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL7_BANK3_PIN30) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN29 26 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL7_BANK3_PIN29) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN28 24 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL7_BANK3_PIN28) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN27 22 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL7_BANK3_PIN27) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN26 20 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL7_BANK3_PIN26) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN25 18 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL7_BANK3_PIN25) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN24 16 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL7_BANK3_PIN24) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN23 14 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL7_BANK3_PIN23) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN22 12 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL7_BANK3_PIN22) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20) +#define BP_PINCTRL_MUXSEL7_RSRVD0 6 +#define BM_PINCTRL_MUXSEL7_RSRVD0 0x000000C0 +#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL7_RSRVD0) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16) + +#define HW_PINCTRL_MUXSEL8 (0x00000180) +#define HW_PINCTRL_MUXSEL8_SET (0x00000184) +#define HW_PINCTRL_MUXSEL8_CLR (0x00000188) +#define HW_PINCTRL_MUXSEL8_TOG (0x0000018c) + +#define BP_PINCTRL_MUXSEL8_BANK4_PIN15 30 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL8_BANK4_PIN15) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN14 28 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL8_BANK4_PIN14) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN13 26 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL8_BANK4_PIN13) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN12 24 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL8_BANK4_PIN12) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN11 22 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL8_BANK4_PIN11) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN10 20 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL8_BANK4_PIN10) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN09 18 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL8_BANK4_PIN09) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN08 16 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL8_BANK4_PIN08) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN07 14 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL8_BANK4_PIN07) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN06 12 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL8_BANK4_PIN06) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN05 10 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL8_BANK4_PIN05) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN04 8 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL8_BANK4_PIN04) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN03 6 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL8_BANK4_PIN03) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN02 4 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL8_BANK4_PIN02) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN01 2 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL8_BANK4_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL8_BANK4_PIN01) +#define BP_PINCTRL_MUXSEL8_BANK4_PIN00 0 +#define BM_PINCTRL_MUXSEL8_BANK4_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL8_BANK4_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL8_BANK4_PIN00) + +#define HW_PINCTRL_MUXSEL9 (0x00000190) +#define HW_PINCTRL_MUXSEL9_SET (0x00000194) +#define HW_PINCTRL_MUXSEL9_CLR (0x00000198) +#define HW_PINCTRL_MUXSEL9_TOG (0x0000019c) + +#define BP_PINCTRL_MUXSEL9_RSRVD1 10 +#define BM_PINCTRL_MUXSEL9_RSRVD1 0xFFFFFC00 +#define BF_PINCTRL_MUXSEL9_RSRVD1(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL9_RSRVD1) +#define BP_PINCTRL_MUXSEL9_BANK4_PIN20 8 +#define BM_PINCTRL_MUXSEL9_BANK4_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL9_BANK4_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL9_BANK4_PIN20) +#define BP_PINCTRL_MUXSEL9_RSRVD0 2 +#define BM_PINCTRL_MUXSEL9_RSRVD0 0x000000FC +#define BF_PINCTRL_MUXSEL9_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL9_RSRVD0) +#define BP_PINCTRL_MUXSEL9_BANK4_PIN16 0 +#define BM_PINCTRL_MUXSEL9_BANK4_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL9_BANK4_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL9_BANK4_PIN16) + +#define HW_PINCTRL_MUXSEL10 (0x000001a0) +#define HW_PINCTRL_MUXSEL10_SET (0x000001a4) +#define HW_PINCTRL_MUXSEL10_CLR (0x000001a8) +#define HW_PINCTRL_MUXSEL10_TOG (0x000001ac) + +#define BP_PINCTRL_MUXSEL10_BANK5_PIN15 30 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL10_BANK5_PIN15) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN14 28 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL10_BANK5_PIN14) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN13 26 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL10_BANK5_PIN13) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN12 24 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL10_BANK5_PIN12) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN11 22 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL10_BANK5_PIN11) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN10 20 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL10_BANK5_PIN10) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN09 18 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL10_BANK5_PIN09) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN08 16 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL10_BANK5_PIN08) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN07 14 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL10_BANK5_PIN07) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN06 12 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL10_BANK5_PIN06) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN05 10 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL10_BANK5_PIN05) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN04 8 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL10_BANK5_PIN04) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN03 6 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL10_BANK5_PIN03) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN02 4 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL10_BANK5_PIN02) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN01 2 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL10_BANK5_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL10_BANK5_PIN01) +#define BP_PINCTRL_MUXSEL10_BANK5_PIN00 0 +#define BM_PINCTRL_MUXSEL10_BANK5_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL10_BANK5_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL10_BANK5_PIN00) + +#define HW_PINCTRL_MUXSEL11 (0x000001b0) +#define HW_PINCTRL_MUXSEL11_SET (0x000001b4) +#define HW_PINCTRL_MUXSEL11_CLR (0x000001b8) +#define HW_PINCTRL_MUXSEL11_TOG (0x000001bc) + +#define BP_PINCTRL_MUXSEL11_RSRVD1 22 +#define BM_PINCTRL_MUXSEL11_RSRVD1 0xFFC00000 +#define BF_PINCTRL_MUXSEL11_RSRVD1(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL11_RSRVD1) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN26 20 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL11_BANK5_PIN26) +#define BP_PINCTRL_MUXSEL11_RSRVD0 16 +#define BM_PINCTRL_MUXSEL11_RSRVD0 0x000F0000 +#define BF_PINCTRL_MUXSEL11_RSRVD0(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL11_RSRVD0) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN23 14 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL11_BANK5_PIN23) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN22 12 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL11_BANK5_PIN22) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN21 10 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL11_BANK5_PIN21) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN20 8 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL11_BANK5_PIN20) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN19 6 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL11_BANK5_PIN19) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN18 4 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL11_BANK5_PIN18) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN17 2 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL11_BANK5_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL11_BANK5_PIN17) +#define BP_PINCTRL_MUXSEL11_BANK5_PIN16 0 +#define BM_PINCTRL_MUXSEL11_BANK5_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL11_BANK5_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL11_BANK5_PIN16) + +#define HW_PINCTRL_MUXSEL12 (0x000001c0) +#define HW_PINCTRL_MUXSEL12_SET (0x000001c4) +#define HW_PINCTRL_MUXSEL12_CLR (0x000001c8) +#define HW_PINCTRL_MUXSEL12_TOG (0x000001cc) + +#define BP_PINCTRL_MUXSEL12_RSRVD0 30 +#define BM_PINCTRL_MUXSEL12_RSRVD0 0xC0000000 +#define BF_PINCTRL_MUXSEL12_RSRVD0(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL12_RSRVD0) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN14 28 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL12_BANK6_PIN14) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN13 26 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL12_BANK6_PIN13) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN12 24 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL12_BANK6_PIN12) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN11 22 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL12_BANK6_PIN11) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN10 20 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL12_BANK6_PIN10) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN09 18 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL12_BANK6_PIN09) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN08 16 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL12_BANK6_PIN08) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN07 14 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL12_BANK6_PIN07) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN06 12 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL12_BANK6_PIN06) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN05 10 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL12_BANK6_PIN05) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN04 8 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL12_BANK6_PIN04) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN03 6 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL12_BANK6_PIN03) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN02 4 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL12_BANK6_PIN02) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN01 2 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL12_BANK6_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL12_BANK6_PIN01) +#define BP_PINCTRL_MUXSEL12_BANK6_PIN00 0 +#define BM_PINCTRL_MUXSEL12_BANK6_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL12_BANK6_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL12_BANK6_PIN00) + +#define HW_PINCTRL_MUXSEL13 (0x000001d0) +#define HW_PINCTRL_MUXSEL13_SET (0x000001d4) +#define HW_PINCTRL_MUXSEL13_CLR (0x000001d8) +#define HW_PINCTRL_MUXSEL13_TOG (0x000001dc) + +#define BP_PINCTRL_MUXSEL13_RSRVD0 18 +#define BM_PINCTRL_MUXSEL13_RSRVD0 0xFFFC0000 +#define BF_PINCTRL_MUXSEL13_RSRVD0(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL13_RSRVD0) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN24 16 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL13_BANK6_PIN24) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN23 14 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL13_BANK6_PIN23) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN22 12 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL13_BANK6_PIN22) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN21 10 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL13_BANK6_PIN21) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN20 8 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL13_BANK6_PIN20) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN19 6 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL13_BANK6_PIN19) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN18 4 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL13_BANK6_PIN18) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN17 2 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL13_BANK6_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL13_BANK6_PIN17) +#define BP_PINCTRL_MUXSEL13_BANK6_PIN16 0 +#define BM_PINCTRL_MUXSEL13_BANK6_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL13_BANK6_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL13_BANK6_PIN16) + +#define HW_PINCTRL_DRIVE0 (0x00000300) +#define HW_PINCTRL_DRIVE0_SET (0x00000304) +#define HW_PINCTRL_DRIVE0_CLR (0x00000308) +#define HW_PINCTRL_DRIVE0_TOG (0x0000030c) + +#define BM_PINCTRL_DRIVE0_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA) +#define BM_PINCTRL_DRIVE0_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA) +#define BM_PINCTRL_DRIVE0_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA) +#define BM_PINCTRL_DRIVE0_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA) +#define BM_PINCTRL_DRIVE0_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA) +#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA) +#define BM_PINCTRL_DRIVE0_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA) +#define BM_PINCTRL_DRIVE0_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA) + +#define HW_PINCTRL_DRIVE1 (0x00000310) +#define HW_PINCTRL_DRIVE1_SET (0x00000314) +#define HW_PINCTRL_DRIVE1_CLR (0x00000318) +#define HW_PINCTRL_DRIVE1_TOG (0x0000031c) + +#define BP_PINCTRL_DRIVE1_RSRVD0 0 +#define BM_PINCTRL_DRIVE1_RSRVD0 0xFFFFFFFF +#define BF_PINCTRL_DRIVE1_RSRVD0(v) (v) + +#define HW_PINCTRL_DRIVE2 (0x00000320) +#define HW_PINCTRL_DRIVE2_SET (0x00000324) +#define HW_PINCTRL_DRIVE2_CLR (0x00000328) +#define HW_PINCTRL_DRIVE2_TOG (0x0000032c) + +#define BM_PINCTRL_DRIVE2_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA) +#define BM_PINCTRL_DRIVE2_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA) +#define BM_PINCTRL_DRIVE2_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA) +#define BM_PINCTRL_DRIVE2_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA) +#define BM_PINCTRL_DRIVE2_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA) +#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA) +#define BM_PINCTRL_DRIVE2_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA) +#define BM_PINCTRL_DRIVE2_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA) + +#define HW_PINCTRL_DRIVE3 (0x00000330) +#define HW_PINCTRL_DRIVE3_SET (0x00000334) +#define HW_PINCTRL_DRIVE3_CLR (0x00000338) +#define HW_PINCTRL_DRIVE3_TOG (0x0000033c) + +#define BP_PINCTRL_DRIVE3_RSRVD5 20 +#define BM_PINCTRL_DRIVE3_RSRVD5 0xFFF00000 +#define BF_PINCTRL_DRIVE3_RSRVD5(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE3_RSRVD5) +#define BM_PINCTRL_DRIVE3_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA) +#define BM_PINCTRL_DRIVE3_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA) +#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA) +#define BM_PINCTRL_DRIVE3_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA) +#define BM_PINCTRL_DRIVE3_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA) + +#define HW_PINCTRL_DRIVE4 (0x00000340) +#define HW_PINCTRL_DRIVE4_SET (0x00000344) +#define HW_PINCTRL_DRIVE4_CLR (0x00000348) +#define HW_PINCTRL_DRIVE4_TOG (0x0000034c) + +#define BM_PINCTRL_DRIVE4_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA) +#define BM_PINCTRL_DRIVE4_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA) +#define BM_PINCTRL_DRIVE4_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA) +#define BM_PINCTRL_DRIVE4_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA) +#define BM_PINCTRL_DRIVE4_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA) +#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA) +#define BM_PINCTRL_DRIVE4_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA) +#define BM_PINCTRL_DRIVE4_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA) + +#define HW_PINCTRL_DRIVE5 (0x00000350) +#define HW_PINCTRL_DRIVE5_SET (0x00000354) +#define HW_PINCTRL_DRIVE5_CLR (0x00000358) +#define HW_PINCTRL_DRIVE5_TOG (0x0000035c) + +#define BM_PINCTRL_DRIVE5_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA) +#define BM_PINCTRL_DRIVE5_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA) +#define BM_PINCTRL_DRIVE5_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA) +#define BM_PINCTRL_DRIVE5_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA) +#define BM_PINCTRL_DRIVE5_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA) +#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA) +#define BM_PINCTRL_DRIVE5_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA) +#define BM_PINCTRL_DRIVE5_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA) + +#define HW_PINCTRL_DRIVE6 (0x00000360) +#define HW_PINCTRL_DRIVE6_SET (0x00000364) +#define HW_PINCTRL_DRIVE6_CLR (0x00000368) +#define HW_PINCTRL_DRIVE6_TOG (0x0000036c) + +#define BM_PINCTRL_DRIVE6_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA) +#define BM_PINCTRL_DRIVE6_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA) +#define BM_PINCTRL_DRIVE6_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA) +#define BM_PINCTRL_DRIVE6_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA) +#define BM_PINCTRL_DRIVE6_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA) +#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA) +#define BM_PINCTRL_DRIVE6_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA) +#define BM_PINCTRL_DRIVE6_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA) + +#define HW_PINCTRL_DRIVE7 (0x00000370) +#define HW_PINCTRL_DRIVE7_SET (0x00000374) +#define HW_PINCTRL_DRIVE7_CLR (0x00000378) +#define HW_PINCTRL_DRIVE7_TOG (0x0000037c) + +#define BM_PINCTRL_DRIVE7_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN31_V 0x40000000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN31_MA 28 +#define BM_PINCTRL_DRIVE7_BANK1_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE7_BANK1_PIN31_MA) +#define BM_PINCTRL_DRIVE7_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA) +#define BM_PINCTRL_DRIVE7_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA) +#define BM_PINCTRL_DRIVE7_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA) +#define BM_PINCTRL_DRIVE7_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA) +#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA) +#define BM_PINCTRL_DRIVE7_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA) +#define BM_PINCTRL_DRIVE7_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA) + +#define HW_PINCTRL_DRIVE8 (0x00000380) +#define HW_PINCTRL_DRIVE8_SET (0x00000384) +#define HW_PINCTRL_DRIVE8_CLR (0x00000388) +#define HW_PINCTRL_DRIVE8_TOG (0x0000038c) + +#define BM_PINCTRL_DRIVE8_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA) +#define BM_PINCTRL_DRIVE8_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA) +#define BM_PINCTRL_DRIVE8_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA) +#define BM_PINCTRL_DRIVE8_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA) +#define BM_PINCTRL_DRIVE8_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA) +#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA) +#define BM_PINCTRL_DRIVE8_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA) +#define BM_PINCTRL_DRIVE8_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA) + +#define HW_PINCTRL_DRIVE9 (0x00000390) +#define HW_PINCTRL_DRIVE9_SET (0x00000394) +#define HW_PINCTRL_DRIVE9_CLR (0x00000398) +#define HW_PINCTRL_DRIVE9_TOG (0x0000039c) + +#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA) +#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA) +#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA) +#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA) +#define BP_PINCTRL_DRIVE9_RSRVD3 12 +#define BM_PINCTRL_DRIVE9_RSRVD3 0x0000F000 +#define BF_PINCTRL_DRIVE9_RSRVD3(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE9_RSRVD3) +#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA) +#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA) +#define BM_PINCTRL_DRIVE9_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA) + +#define HW_PINCTRL_DRIVE10 (0x000003a0) +#define HW_PINCTRL_DRIVE10_SET (0x000003a4) +#define HW_PINCTRL_DRIVE10_CLR (0x000003a8) +#define HW_PINCTRL_DRIVE10_TOG (0x000003ac) + +#define BP_PINCTRL_DRIVE10_RSRVD6 24 +#define BM_PINCTRL_DRIVE10_RSRVD6 0xFF000000 +#define BF_PINCTRL_DRIVE10_RSRVD6(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE10_RSRVD6) +#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA) +#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA) +#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA) +#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA) +#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA) +#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA) + +#define HW_PINCTRL_DRIVE11 (0x000003b0) +#define HW_PINCTRL_DRIVE11_SET (0x000003b4) +#define HW_PINCTRL_DRIVE11_CLR (0x000003b8) +#define HW_PINCTRL_DRIVE11_TOG (0x000003bc) + +#define BP_PINCTRL_DRIVE11_RSRVD4 16 +#define BM_PINCTRL_DRIVE11_RSRVD4 0xFFFF0000 +#define BF_PINCTRL_DRIVE11_RSRVD4(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE11_RSRVD4) +#define BM_PINCTRL_DRIVE11_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA) +#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA) +#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA) +#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA) + +#define HW_PINCTRL_DRIVE12 (0x000003c0) +#define HW_PINCTRL_DRIVE12_SET (0x000003c4) +#define HW_PINCTRL_DRIVE12_CLR (0x000003c8) +#define HW_PINCTRL_DRIVE12_TOG (0x000003cc) + +#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA) +#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA) +#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA) +#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA) +#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA) +#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA) +#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA) +#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA) + +#define HW_PINCTRL_DRIVE13 (0x000003d0) +#define HW_PINCTRL_DRIVE13_SET (0x000003d4) +#define HW_PINCTRL_DRIVE13_CLR (0x000003d8) +#define HW_PINCTRL_DRIVE13_TOG (0x000003dc) + +#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA) +#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA) +#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA) +#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA) +#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA) +#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA) +#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA) +#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA) + +#define HW_PINCTRL_DRIVE14 (0x000003e0) +#define HW_PINCTRL_DRIVE14_SET (0x000003e4) +#define HW_PINCTRL_DRIVE14_CLR (0x000003e8) +#define HW_PINCTRL_DRIVE14_TOG (0x000003ec) + +#define BM_PINCTRL_DRIVE14_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN23_MA 28 +#define BM_PINCTRL_DRIVE14_BANK3_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE14_BANK3_PIN23_MA) +#define BM_PINCTRL_DRIVE14_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN22_MA 24 +#define BM_PINCTRL_DRIVE14_BANK3_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE14_BANK3_PIN22_MA) +#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA) +#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA) +#define BP_PINCTRL_DRIVE14_RSRVD3 12 +#define BM_PINCTRL_DRIVE14_RSRVD3 0x0000F000 +#define BF_PINCTRL_DRIVE14_RSRVD3(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE14_RSRVD3) +#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA) +#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA) +#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA) + +#define HW_PINCTRL_DRIVE15 (0x000003f0) +#define HW_PINCTRL_DRIVE15_SET (0x000003f4) +#define HW_PINCTRL_DRIVE15_CLR (0x000003f8) +#define HW_PINCTRL_DRIVE15_TOG (0x000003fc) + +#define BP_PINCTRL_DRIVE15_RSRVD7 28 +#define BM_PINCTRL_DRIVE15_RSRVD7 0xF0000000 +#define BF_PINCTRL_DRIVE15_RSRVD7(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE15_RSRVD7) +#define BM_PINCTRL_DRIVE15_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN30_MA 24 +#define BM_PINCTRL_DRIVE15_BANK3_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE15_BANK3_PIN30_MA) +#define BM_PINCTRL_DRIVE15_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN29_MA 20 +#define BM_PINCTRL_DRIVE15_BANK3_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE15_BANK3_PIN29_MA) +#define BM_PINCTRL_DRIVE15_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN28_V 0x00040000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN28_MA 16 +#define BM_PINCTRL_DRIVE15_BANK3_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE15_BANK3_PIN28_MA) +#define BM_PINCTRL_DRIVE15_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE15_BANK3_PIN27_V 0x00004000 +#define BP_PINCTRL_DRIVE15_BANK3_PIN27_MA 12 +#define BM_PINCTRL_DRIVE15_BANK3_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE15_BANK3_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE15_BANK3_PIN27_MA) +#define BM_PINCTRL_DRIVE15_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE15_BANK3_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE15_BANK3_PIN26_MA 8 +#define BM_PINCTRL_DRIVE15_BANK3_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE15_BANK3_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE15_BANK3_PIN26_MA) +#define BM_PINCTRL_DRIVE15_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE15_BANK3_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE15_BANK3_PIN25_MA 4 +#define BM_PINCTRL_DRIVE15_BANK3_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE15_BANK3_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE15_BANK3_PIN25_MA) +#define BM_PINCTRL_DRIVE15_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE15_BANK3_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE15_BANK3_PIN24_MA 0 +#define BM_PINCTRL_DRIVE15_BANK3_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE15_BANK3_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE15_BANK3_PIN24_MA) + +#define HW_PINCTRL_DRIVE16 (0x00000400) +#define HW_PINCTRL_DRIVE16_SET (0x00000404) +#define HW_PINCTRL_DRIVE16_CLR (0x00000408) +#define HW_PINCTRL_DRIVE16_TOG (0x0000040c) + +#define BM_PINCTRL_DRIVE16_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN07_MA 28 +#define BM_PINCTRL_DRIVE16_BANK4_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE16_BANK4_PIN07_MA) +#define BM_PINCTRL_DRIVE16_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN06_MA 24 +#define BM_PINCTRL_DRIVE16_BANK4_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE16_BANK4_PIN06_MA) +#define BM_PINCTRL_DRIVE16_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN05_MA 20 +#define BM_PINCTRL_DRIVE16_BANK4_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE16_BANK4_PIN05_MA) +#define BM_PINCTRL_DRIVE16_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN04_MA 16 +#define BM_PINCTRL_DRIVE16_BANK4_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE16_BANK4_PIN04_MA) +#define BM_PINCTRL_DRIVE16_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE16_BANK4_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE16_BANK4_PIN03_MA 12 +#define BM_PINCTRL_DRIVE16_BANK4_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE16_BANK4_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE16_BANK4_PIN03_MA) +#define BM_PINCTRL_DRIVE16_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE16_BANK4_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE16_BANK4_PIN02_MA 8 +#define BM_PINCTRL_DRIVE16_BANK4_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE16_BANK4_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE16_BANK4_PIN02_MA) +#define BM_PINCTRL_DRIVE16_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE16_BANK4_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE16_BANK4_PIN01_MA 4 +#define BM_PINCTRL_DRIVE16_BANK4_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE16_BANK4_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE16_BANK4_PIN01_MA) +#define BM_PINCTRL_DRIVE16_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE16_BANK4_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE16_BANK4_PIN00_MA 0 +#define BM_PINCTRL_DRIVE16_BANK4_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE16_BANK4_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE16_BANK4_PIN00_MA) + +#define HW_PINCTRL_DRIVE17 (0x00000410) +#define HW_PINCTRL_DRIVE17_SET (0x00000414) +#define HW_PINCTRL_DRIVE17_CLR (0x00000418) +#define HW_PINCTRL_DRIVE17_TOG (0x0000041c) + +#define BM_PINCTRL_DRIVE17_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN15_MA 28 +#define BM_PINCTRL_DRIVE17_BANK4_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE17_BANK4_PIN15_MA) +#define BM_PINCTRL_DRIVE17_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN14_MA 24 +#define BM_PINCTRL_DRIVE17_BANK4_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE17_BANK4_PIN14_MA) +#define BM_PINCTRL_DRIVE17_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN13_MA 20 +#define BM_PINCTRL_DRIVE17_BANK4_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE17_BANK4_PIN13_MA) +#define BM_PINCTRL_DRIVE17_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN12_MA 16 +#define BM_PINCTRL_DRIVE17_BANK4_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE17_BANK4_PIN12_MA) +#define BM_PINCTRL_DRIVE17_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE17_BANK4_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE17_BANK4_PIN11_MA 12 +#define BM_PINCTRL_DRIVE17_BANK4_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE17_BANK4_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE17_BANK4_PIN11_MA) +#define BM_PINCTRL_DRIVE17_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE17_BANK4_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE17_BANK4_PIN10_MA 8 +#define BM_PINCTRL_DRIVE17_BANK4_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE17_BANK4_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE17_BANK4_PIN10_MA) +#define BM_PINCTRL_DRIVE17_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE17_BANK4_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE17_BANK4_PIN09_MA 4 +#define BM_PINCTRL_DRIVE17_BANK4_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE17_BANK4_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE17_BANK4_PIN09_MA) +#define BM_PINCTRL_DRIVE17_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE17_BANK4_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE17_BANK4_PIN08_MA 0 +#define BM_PINCTRL_DRIVE17_BANK4_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE17_BANK4_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE17_BANK4_PIN08_MA) + +#define HW_PINCTRL_DRIVE18 (0x00000420) +#define HW_PINCTRL_DRIVE18_SET (0x00000424) +#define HW_PINCTRL_DRIVE18_CLR (0x00000428) +#define HW_PINCTRL_DRIVE18_TOG (0x0000042c) + +#define BP_PINCTRL_DRIVE18_RSRVD3 20 +#define BM_PINCTRL_DRIVE18_RSRVD3 0xFFF00000 +#define BF_PINCTRL_DRIVE18_RSRVD3(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE18_RSRVD3) +#define BM_PINCTRL_DRIVE18_RSRVD2 0x00080000 +#define BM_PINCTRL_DRIVE18_BANK4_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE18_BANK4_PIN20_MA 16 +#define BM_PINCTRL_DRIVE18_BANK4_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE18_BANK4_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE18_BANK4_PIN20_MA) +#define BP_PINCTRL_DRIVE18_RSRVD1 4 +#define BM_PINCTRL_DRIVE18_RSRVD1 0x0000FFF0 +#define BF_PINCTRL_DRIVE18_RSRVD1(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE18_RSRVD1) +#define BM_PINCTRL_DRIVE18_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE18_BANK4_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE18_BANK4_PIN16_MA 0 +#define BM_PINCTRL_DRIVE18_BANK4_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE18_BANK4_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE18_BANK4_PIN16_MA) + +#define HW_PINCTRL_DRIVE19 (0x00000430) +#define HW_PINCTRL_DRIVE19_SET (0x00000434) +#define HW_PINCTRL_DRIVE19_CLR (0x00000438) +#define HW_PINCTRL_DRIVE19_TOG (0x0000043c) + +#define BP_PINCTRL_DRIVE19_RSRVD0 0 +#define BM_PINCTRL_DRIVE19_RSRVD0 0xFFFFFFFF +#define BF_PINCTRL_DRIVE19_RSRVD0(v) (v) + +#define HW_PINCTRL_PULL0 (0x00000600) +#define HW_PINCTRL_PULL0_SET (0x00000604) +#define HW_PINCTRL_PULL0_CLR (0x00000608) +#define HW_PINCTRL_PULL0_TOG (0x0000060c) + +#define BP_PINCTRL_PULL0_RSRVD1 29 +#define BM_PINCTRL_PULL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_PULL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_PULL0_RSRVD1) +#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000 +#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000 +#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000 +#define BM_PINCTRL_PULL0_BANK0_PIN25 0x02000000 +#define BM_PINCTRL_PULL0_BANK0_PIN24 0x01000000 +#define BM_PINCTRL_PULL0_BANK0_PIN23 0x00800000 +#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000 +#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000 +#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000 +#define BM_PINCTRL_PULL0_BANK0_PIN17 0x00020000 +#define BM_PINCTRL_PULL0_BANK0_PIN16 0x00010000 +#define BP_PINCTRL_PULL0_RSRVD0 8 +#define BM_PINCTRL_PULL0_RSRVD0 0x0000FF00 +#define BF_PINCTRL_PULL0_RSRVD0(v) \ + (((v) << 8) & BM_PINCTRL_PULL0_RSRVD0) +#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080 +#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040 +#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001 + +#define HW_PINCTRL_PULL1 (0x00000610) +#define HW_PINCTRL_PULL1_SET (0x00000614) +#define HW_PINCTRL_PULL1_CLR (0x00000618) +#define HW_PINCTRL_PULL1_TOG (0x0000061c) + +#define BM_PINCTRL_PULL1_BANK1_PIN31 0x80000000 +#define BM_PINCTRL_PULL1_BANK1_PIN30 0x40000000 +#define BM_PINCTRL_PULL1_BANK1_PIN29 0x20000000 +#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000 +#define BM_PINCTRL_PULL1_BANK1_PIN27 0x08000000 +#define BM_PINCTRL_PULL1_BANK1_PIN26 0x04000000 +#define BM_PINCTRL_PULL1_BANK1_PIN25 0x02000000 +#define BM_PINCTRL_PULL1_BANK1_PIN24 0x01000000 +#define BM_PINCTRL_PULL1_BANK1_PIN23 0x00800000 +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BM_PINCTRL_PULL1_BANK1_PIN21 0x00200000 +#define BM_PINCTRL_PULL1_BANK1_PIN20 0x00100000 +#define BM_PINCTRL_PULL1_BANK1_PIN19 0x00080000 +#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000 +#define BM_PINCTRL_PULL1_BANK1_PIN17 0x00020000 +#define BM_PINCTRL_PULL1_BANK1_PIN16 0x00010000 +#define BM_PINCTRL_PULL1_BANK1_PIN15 0x00008000 +#define BM_PINCTRL_PULL1_BANK1_PIN14 0x00004000 +#define BM_PINCTRL_PULL1_BANK1_PIN13 0x00002000 +#define BM_PINCTRL_PULL1_BANK1_PIN12 0x00001000 +#define BM_PINCTRL_PULL1_BANK1_PIN11 0x00000800 +#define BM_PINCTRL_PULL1_BANK1_PIN10 0x00000400 +#define BM_PINCTRL_PULL1_BANK1_PIN09 0x00000200 +#define BM_PINCTRL_PULL1_BANK1_PIN08 0x00000100 +#define BM_PINCTRL_PULL1_BANK1_PIN07 0x00000080 +#define BM_PINCTRL_PULL1_BANK1_PIN06 0x00000040 +#define BM_PINCTRL_PULL1_BANK1_PIN05 0x00000020 +#define BM_PINCTRL_PULL1_BANK1_PIN04 0x00000010 +#define BM_PINCTRL_PULL1_BANK1_PIN03 0x00000008 +#define BM_PINCTRL_PULL1_BANK1_PIN02 0x00000004 +#define BM_PINCTRL_PULL1_BANK1_PIN01 0x00000002 +#define BM_PINCTRL_PULL1_BANK1_PIN00 0x00000001 + +#define HW_PINCTRL_PULL2 (0x00000620) +#define HW_PINCTRL_PULL2_SET (0x00000624) +#define HW_PINCTRL_PULL2_CLR (0x00000628) +#define HW_PINCTRL_PULL2_TOG (0x0000062c) + +#define BP_PINCTRL_PULL2_RSRVD2 28 +#define BM_PINCTRL_PULL2_RSRVD2 0xF0000000 +#define BF_PINCTRL_PULL2_RSRVD2(v) \ + (((v) << 28) & BM_PINCTRL_PULL2_RSRVD2) +#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000 +#define BM_PINCTRL_PULL2_BANK2_PIN26 0x04000000 +#define BM_PINCTRL_PULL2_BANK2_PIN25 0x02000000 +#define BM_PINCTRL_PULL2_BANK2_PIN24 0x01000000 +#define BP_PINCTRL_PULL2_RSRVD1 22 +#define BM_PINCTRL_PULL2_RSRVD1 0x00C00000 +#define BF_PINCTRL_PULL2_RSRVD1(v) \ + (((v) << 22) & BM_PINCTRL_PULL2_RSRVD1) +#define BM_PINCTRL_PULL2_BANK2_PIN21 0x00200000 +#define BM_PINCTRL_PULL2_BANK2_PIN20 0x00100000 +#define BM_PINCTRL_PULL2_BANK2_PIN19 0x00080000 +#define BM_PINCTRL_PULL2_BANK2_PIN18 0x00040000 +#define BM_PINCTRL_PULL2_BANK2_PIN17 0x00020000 +#define BM_PINCTRL_PULL2_BANK2_PIN16 0x00010000 +#define BM_PINCTRL_PULL2_BANK2_PIN15 0x00008000 +#define BM_PINCTRL_PULL2_BANK2_PIN14 0x00004000 +#define BM_PINCTRL_PULL2_BANK2_PIN13 0x00002000 +#define BM_PINCTRL_PULL2_BANK2_PIN12 0x00001000 +#define BM_PINCTRL_PULL2_RSRVD0 0x00000800 +#define BM_PINCTRL_PULL2_BANK2_PIN10 0x00000400 +#define BM_PINCTRL_PULL2_BANK2_PIN09 0x00000200 +#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100 +#define BM_PINCTRL_PULL2_BANK2_PIN07 0x00000080 +#define BM_PINCTRL_PULL2_BANK2_PIN06 0x00000040 +#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020 +#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010 +#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008 +#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004 +#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002 +#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001 + +#define HW_PINCTRL_PULL3 (0x00000630) +#define HW_PINCTRL_PULL3_SET (0x00000634) +#define HW_PINCTRL_PULL3_CLR (0x00000638) +#define HW_PINCTRL_PULL3_TOG (0x0000063c) + +#define BM_PINCTRL_PULL3_RSRVD1 0x80000000 +#define BM_PINCTRL_PULL3_BANK3_PIN30 0x40000000 +#define BM_PINCTRL_PULL3_BANK3_PIN29 0x20000000 +#define BM_PINCTRL_PULL3_BANK3_PIN28 0x10000000 +#define BM_PINCTRL_PULL3_BANK3_PIN27 0x08000000 +#define BM_PINCTRL_PULL3_BANK3_PIN26 0x04000000 +#define BM_PINCTRL_PULL3_BANK3_PIN25 0x02000000 +#define BM_PINCTRL_PULL3_BANK3_PIN24 0x01000000 +#define BM_PINCTRL_PULL3_BANK3_PIN23 0x00800000 +#define BM_PINCTRL_PULL3_BANK3_PIN22 0x00400000 +#define BM_PINCTRL_PULL3_BANK3_PIN21 0x00200000 +#define BM_PINCTRL_PULL3_BANK3_PIN20 0x00100000 +#define BM_PINCTRL_PULL3_RSRVD0 0x00080000 +#define BM_PINCTRL_PULL3_BANK3_PIN18 0x00040000 +#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000 +#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000 +#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000 +#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000 +#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000 +#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000 +#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800 +#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400 +#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200 +#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100 +#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080 +#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040 +#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020 +#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010 +#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008 +#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004 +#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002 +#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001 + +#define HW_PINCTRL_PULL4 (0x00000640) +#define HW_PINCTRL_PULL4_SET (0x00000644) +#define HW_PINCTRL_PULL4_CLR (0x00000648) +#define HW_PINCTRL_PULL4_TOG (0x0000064c) + +#define BP_PINCTRL_PULL4_RSRVD1 21 +#define BM_PINCTRL_PULL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_PULL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_PULL4_RSRVD1) +#define BM_PINCTRL_PULL4_BANK4_PIN20 0x00100000 +#define BP_PINCTRL_PULL4_RSRVD0 17 +#define BM_PINCTRL_PULL4_RSRVD0 0x000E0000 +#define BF_PINCTRL_PULL4_RSRVD0(v) \ + (((v) << 17) & BM_PINCTRL_PULL4_RSRVD0) +#define BM_PINCTRL_PULL4_BANK4_PIN16 0x00010000 +#define BM_PINCTRL_PULL4_BANK4_PIN15 0x00008000 +#define BM_PINCTRL_PULL4_BANK4_PIN14 0x00004000 +#define BM_PINCTRL_PULL4_BANK4_PIN13 0x00002000 +#define BM_PINCTRL_PULL4_BANK4_PIN12 0x00001000 +#define BM_PINCTRL_PULL4_BANK4_PIN11 0x00000800 +#define BM_PINCTRL_PULL4_BANK4_PIN10 0x00000400 +#define BM_PINCTRL_PULL4_BANK4_PIN09 0x00000200 +#define BM_PINCTRL_PULL4_BANK4_PIN08 0x00000100 +#define BM_PINCTRL_PULL4_BANK4_PIN07 0x00000080 +#define BM_PINCTRL_PULL4_BANK4_PIN06 0x00000040 +#define BM_PINCTRL_PULL4_BANK4_PIN05 0x00000020 +#define BM_PINCTRL_PULL4_BANK4_PIN04 0x00000010 +#define BM_PINCTRL_PULL4_BANK4_PIN03 0x00000008 +#define BM_PINCTRL_PULL4_BANK4_PIN02 0x00000004 +#define BM_PINCTRL_PULL4_BANK4_PIN01 0x00000002 +#define BM_PINCTRL_PULL4_BANK4_PIN00 0x00000001 + +#define HW_PINCTRL_PULL5 (0x00000650) +#define HW_PINCTRL_PULL5_SET (0x00000654) +#define HW_PINCTRL_PULL5_CLR (0x00000658) +#define HW_PINCTRL_PULL5_TOG (0x0000065c) + +#define BP_PINCTRL_PULL5_RSRVD1 27 +#define BM_PINCTRL_PULL5_RSRVD1 0xF8000000 +#define BF_PINCTRL_PULL5_RSRVD1(v) \ + (((v) << 27) & BM_PINCTRL_PULL5_RSRVD1) +#define BM_PINCTRL_PULL5_BANK5_PIN26 0x04000000 +#define BP_PINCTRL_PULL5_RSRVD0 24 +#define BM_PINCTRL_PULL5_RSRVD0 0x03000000 +#define BF_PINCTRL_PULL5_RSRVD0(v) \ + (((v) << 24) & BM_PINCTRL_PULL5_RSRVD0) +#define BM_PINCTRL_PULL5_BANK5_PIN23 0x00800000 +#define BM_PINCTRL_PULL5_BANK5_PIN22 0x00400000 +#define BM_PINCTRL_PULL5_BANK5_PIN21 0x00200000 +#define BM_PINCTRL_PULL5_BANK5_PIN20 0x00100000 +#define BM_PINCTRL_PULL5_BANK5_PIN19 0x00080000 +#define BM_PINCTRL_PULL5_BANK5_PIN18 0x00040000 +#define BM_PINCTRL_PULL5_BANK5_PIN17 0x00020000 +#define BM_PINCTRL_PULL5_BANK5_PIN16 0x00010000 +#define BM_PINCTRL_PULL5_BANK5_PIN15 0x00008000 +#define BM_PINCTRL_PULL5_BANK5_PIN14 0x00004000 +#define BM_PINCTRL_PULL5_BANK5_PIN13 0x00002000 +#define BM_PINCTRL_PULL5_BANK5_PIN12 0x00001000 +#define BM_PINCTRL_PULL5_BANK5_PIN11 0x00000800 +#define BM_PINCTRL_PULL5_BANK5_PIN10 0x00000400 +#define BM_PINCTRL_PULL5_BANK5_PIN09 0x00000200 +#define BM_PINCTRL_PULL5_BANK5_PIN08 0x00000100 +#define BM_PINCTRL_PULL5_BANK5_PIN07 0x00000080 +#define BM_PINCTRL_PULL5_BANK5_PIN06 0x00000040 +#define BM_PINCTRL_PULL5_BANK5_PIN05 0x00000020 +#define BM_PINCTRL_PULL5_BANK5_PIN04 0x00000010 +#define BM_PINCTRL_PULL5_BANK5_PIN03 0x00000008 +#define BM_PINCTRL_PULL5_BANK5_PIN02 0x00000004 +#define BM_PINCTRL_PULL5_BANK5_PIN01 0x00000002 +#define BM_PINCTRL_PULL5_BANK5_PIN00 0x00000001 + +#define HW_PINCTRL_PULL6 (0x00000660) +#define HW_PINCTRL_PULL6_SET (0x00000664) +#define HW_PINCTRL_PULL6_CLR (0x00000668) +#define HW_PINCTRL_PULL6_TOG (0x0000066c) + +#define BP_PINCTRL_PULL6_RSRVD1 25 +#define BM_PINCTRL_PULL6_RSRVD1 0xFE000000 +#define BF_PINCTRL_PULL6_RSRVD1(v) \ + (((v) << 25) & BM_PINCTRL_PULL6_RSRVD1) +#define BM_PINCTRL_PULL6_BANK6_PIN24 0x01000000 +#define BM_PINCTRL_PULL6_BANK6_PIN23 0x00800000 +#define BM_PINCTRL_PULL6_BANK6_PIN22 0x00400000 +#define BM_PINCTRL_PULL6_BANK6_PIN21 0x00200000 +#define BM_PINCTRL_PULL6_BANK6_PIN20 0x00100000 +#define BM_PINCTRL_PULL6_BANK6_PIN19 0x00080000 +#define BM_PINCTRL_PULL6_BANK6_PIN18 0x00040000 +#define BM_PINCTRL_PULL6_BANK6_PIN17 0x00020000 +#define BM_PINCTRL_PULL6_BANK6_PIN16 0x00010000 +#define BM_PINCTRL_PULL6_RSRVD0 0x00008000 +#define BM_PINCTRL_PULL6_BANK6_PIN14 0x00004000 +#define BM_PINCTRL_PULL6_BANK6_PIN13 0x00002000 +#define BM_PINCTRL_PULL6_BANK6_PIN12 0x00001000 +#define BM_PINCTRL_PULL6_BANK6_PIN11 0x00000800 +#define BM_PINCTRL_PULL6_BANK6_PIN10 0x00000400 +#define BM_PINCTRL_PULL6_BANK6_PIN09 0x00000200 +#define BM_PINCTRL_PULL6_BANK6_PIN08 0x00000100 +#define BM_PINCTRL_PULL6_BANK6_PIN07 0x00000080 +#define BM_PINCTRL_PULL6_BANK6_PIN06 0x00000040 +#define BM_PINCTRL_PULL6_BANK6_PIN05 0x00000020 +#define BM_PINCTRL_PULL6_BANK6_PIN04 0x00000010 +#define BM_PINCTRL_PULL6_BANK6_PIN03 0x00000008 +#define BM_PINCTRL_PULL6_BANK6_PIN02 0x00000004 +#define BM_PINCTRL_PULL6_BANK6_PIN01 0x00000002 +#define BM_PINCTRL_PULL6_BANK6_PIN00 0x00000001 + +#define HW_PINCTRL_DOUT0 (0x00000700) +#define HW_PINCTRL_DOUT0_SET (0x00000704) +#define HW_PINCTRL_DOUT0_CLR (0x00000708) +#define HW_PINCTRL_DOUT0_TOG (0x0000070c) + +#define BP_PINCTRL_DOUT0_RSRVD1 29 +#define BM_PINCTRL_DOUT0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DOUT0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DOUT0_RSRVD1) +#define BP_PINCTRL_DOUT0_DOUT 0 +#define BM_PINCTRL_DOUT0_DOUT 0x1FFFFFFF +#define BF_PINCTRL_DOUT0_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT0_DOUT) + +#define HW_PINCTRL_DOUT1 (0x00000710) +#define HW_PINCTRL_DOUT1_SET (0x00000714) +#define HW_PINCTRL_DOUT1_CLR (0x00000718) +#define HW_PINCTRL_DOUT1_TOG (0x0000071c) + +#define BP_PINCTRL_DOUT1_DOUT 0 +#define BM_PINCTRL_DOUT1_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT1_DOUT(v) (v) + +#define HW_PINCTRL_DOUT2 (0x00000720) +#define HW_PINCTRL_DOUT2_SET (0x00000724) +#define HW_PINCTRL_DOUT2_CLR (0x00000728) +#define HW_PINCTRL_DOUT2_TOG (0x0000072c) + +#define BP_PINCTRL_DOUT2_RSRVD1 28 +#define BM_PINCTRL_DOUT2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DOUT2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DOUT2_RSRVD1) +#define BP_PINCTRL_DOUT2_DOUT 0 +#define BM_PINCTRL_DOUT2_DOUT 0x0FFFFFFF +#define BF_PINCTRL_DOUT2_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT2_DOUT) + +#define HW_PINCTRL_DOUT3 (0x00000730) +#define HW_PINCTRL_DOUT3_SET (0x00000734) +#define HW_PINCTRL_DOUT3_CLR (0x00000738) +#define HW_PINCTRL_DOUT3_TOG (0x0000073c) + +#define BM_PINCTRL_DOUT3_RSRVD1 0x80000000 +#define BP_PINCTRL_DOUT3_DOUT 0 +#define BM_PINCTRL_DOUT3_DOUT 0x7FFFFFFF +#define BF_PINCTRL_DOUT3_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT3_DOUT) + +#define HW_PINCTRL_DOUT4 (0x00000740) +#define HW_PINCTRL_DOUT4_SET (0x00000744) +#define HW_PINCTRL_DOUT4_CLR (0x00000748) +#define HW_PINCTRL_DOUT4_TOG (0x0000074c) + +#define BP_PINCTRL_DOUT4_RSRVD1 21 +#define BM_PINCTRL_DOUT4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DOUT4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DOUT4_RSRVD1) +#define BP_PINCTRL_DOUT4_DOUT 0 +#define BM_PINCTRL_DOUT4_DOUT 0x001FFFFF +#define BF_PINCTRL_DOUT4_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT4_DOUT) + +#define HW_PINCTRL_DIN0 (0x00000900) +#define HW_PINCTRL_DIN0_SET (0x00000904) +#define HW_PINCTRL_DIN0_CLR (0x00000908) +#define HW_PINCTRL_DIN0_TOG (0x0000090c) + +#define BP_PINCTRL_DIN0_RSRVD1 29 +#define BM_PINCTRL_DIN0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DIN0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DIN0_RSRVD1) +#define BP_PINCTRL_DIN0_DIN 0 +#define BM_PINCTRL_DIN0_DIN 0x1FFFFFFF +#define BF_PINCTRL_DIN0_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN0_DIN) + +#define HW_PINCTRL_DIN1 (0x00000910) +#define HW_PINCTRL_DIN1_SET (0x00000914) +#define HW_PINCTRL_DIN1_CLR (0x00000918) +#define HW_PINCTRL_DIN1_TOG (0x0000091c) + +#define BP_PINCTRL_DIN1_DIN 0 +#define BM_PINCTRL_DIN1_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN1_DIN(v) (v) + +#define HW_PINCTRL_DIN2 (0x00000920) +#define HW_PINCTRL_DIN2_SET (0x00000924) +#define HW_PINCTRL_DIN2_CLR (0x00000928) +#define HW_PINCTRL_DIN2_TOG (0x0000092c) + +#define BP_PINCTRL_DIN2_RSRVD1 28 +#define BM_PINCTRL_DIN2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DIN2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DIN2_RSRVD1) +#define BP_PINCTRL_DIN2_DIN 0 +#define BM_PINCTRL_DIN2_DIN 0x0FFFFFFF +#define BF_PINCTRL_DIN2_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN2_DIN) + +#define HW_PINCTRL_DIN3 (0x00000930) +#define HW_PINCTRL_DIN3_SET (0x00000934) +#define HW_PINCTRL_DIN3_CLR (0x00000938) +#define HW_PINCTRL_DIN3_TOG (0x0000093c) + +#define BM_PINCTRL_DIN3_RSRVD1 0x80000000 +#define BP_PINCTRL_DIN3_DIN 0 +#define BM_PINCTRL_DIN3_DIN 0x7FFFFFFF +#define BF_PINCTRL_DIN3_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN3_DIN) + +#define HW_PINCTRL_DIN4 (0x00000940) +#define HW_PINCTRL_DIN4_SET (0x00000944) +#define HW_PINCTRL_DIN4_CLR (0x00000948) +#define HW_PINCTRL_DIN4_TOG (0x0000094c) + +#define BP_PINCTRL_DIN4_RSRVD1 21 +#define BM_PINCTRL_DIN4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DIN4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DIN4_RSRVD1) +#define BP_PINCTRL_DIN4_DIN 0 +#define BM_PINCTRL_DIN4_DIN 0x001FFFFF +#define BF_PINCTRL_DIN4_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN4_DIN) + +#define HW_PINCTRL_DOE0 (0x00000b00) +#define HW_PINCTRL_DOE0_SET (0x00000b04) +#define HW_PINCTRL_DOE0_CLR (0x00000b08) +#define HW_PINCTRL_DOE0_TOG (0x00000b0c) + +#define BP_PINCTRL_DOE0_RSRVD1 29 +#define BM_PINCTRL_DOE0_RSRVD1 0xE0000000 +#define BF_PINCTRL_DOE0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_DOE0_RSRVD1) +#define BP_PINCTRL_DOE0_DOE 0 +#define BM_PINCTRL_DOE0_DOE 0x1FFFFFFF +#define BF_PINCTRL_DOE0_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE0_DOE) + +#define HW_PINCTRL_DOE1 (0x00000b10) +#define HW_PINCTRL_DOE1_SET (0x00000b14) +#define HW_PINCTRL_DOE1_CLR (0x00000b18) +#define HW_PINCTRL_DOE1_TOG (0x00000b1c) + +#define BP_PINCTRL_DOE1_DOE 0 +#define BM_PINCTRL_DOE1_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE1_DOE(v) (v) + +#define HW_PINCTRL_DOE2 (0x00000b20) +#define HW_PINCTRL_DOE2_SET (0x00000b24) +#define HW_PINCTRL_DOE2_CLR (0x00000b28) +#define HW_PINCTRL_DOE2_TOG (0x00000b2c) + +#define BP_PINCTRL_DOE2_RSRVD1 28 +#define BM_PINCTRL_DOE2_RSRVD1 0xF0000000 +#define BF_PINCTRL_DOE2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_DOE2_RSRVD1) +#define BP_PINCTRL_DOE2_DOE 0 +#define BM_PINCTRL_DOE2_DOE 0x0FFFFFFF +#define BF_PINCTRL_DOE2_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE2_DOE) + +#define HW_PINCTRL_DOE3 (0x00000b30) +#define HW_PINCTRL_DOE3_SET (0x00000b34) +#define HW_PINCTRL_DOE3_CLR (0x00000b38) +#define HW_PINCTRL_DOE3_TOG (0x00000b3c) + +#define BM_PINCTRL_DOE3_RSRVD1 0x80000000 +#define BP_PINCTRL_DOE3_DOE 0 +#define BM_PINCTRL_DOE3_DOE 0x7FFFFFFF +#define BF_PINCTRL_DOE3_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE3_DOE) + +#define HW_PINCTRL_DOE4 (0x00000b40) +#define HW_PINCTRL_DOE4_SET (0x00000b44) +#define HW_PINCTRL_DOE4_CLR (0x00000b48) +#define HW_PINCTRL_DOE4_TOG (0x00000b4c) + +#define BP_PINCTRL_DOE4_RSRVD1 21 +#define BM_PINCTRL_DOE4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_DOE4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_DOE4_RSRVD1) +#define BP_PINCTRL_DOE4_DOE 0 +#define BM_PINCTRL_DOE4_DOE 0x001FFFFF +#define BF_PINCTRL_DOE4_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE4_DOE) + +#define HW_PINCTRL_PIN2IRQ0 (0x00001000) +#define HW_PINCTRL_PIN2IRQ0_SET (0x00001004) +#define HW_PINCTRL_PIN2IRQ0_CLR (0x00001008) +#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000100c) + +#define BP_PINCTRL_PIN2IRQ0_RSRVD1 29 +#define BM_PINCTRL_PIN2IRQ0_RSRVD1 0xE0000000 +#define BF_PINCTRL_PIN2IRQ0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_PIN2IRQ0_RSRVD1) +#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0x1FFFFFFF +#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ0_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ1 (0x00001010) +#define HW_PINCTRL_PIN2IRQ1_SET (0x00001014) +#define HW_PINCTRL_PIN2IRQ1_CLR (0x00001018) +#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000101c) + +#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) (v) + +#define HW_PINCTRL_PIN2IRQ2 (0x00001020) +#define HW_PINCTRL_PIN2IRQ2_SET (0x00001024) +#define HW_PINCTRL_PIN2IRQ2_CLR (0x00001028) +#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000102c) + +#define BP_PINCTRL_PIN2IRQ2_RSRVD1 28 +#define BM_PINCTRL_PIN2IRQ2_RSRVD1 0xF0000000 +#define BF_PINCTRL_PIN2IRQ2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_PIN2IRQ2_RSRVD1) +#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0x0FFFFFFF +#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ2_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ3 (0x00001030) +#define HW_PINCTRL_PIN2IRQ3_SET (0x00001034) +#define HW_PINCTRL_PIN2IRQ3_CLR (0x00001038) +#define HW_PINCTRL_PIN2IRQ3_TOG (0x0000103c) + +#define BM_PINCTRL_PIN2IRQ3_RSRVD1 0x80000000 +#define BP_PINCTRL_PIN2IRQ3_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ3_PIN2IRQ 0x7FFFFFFF +#define BF_PINCTRL_PIN2IRQ3_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ3_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ4 (0x00001040) +#define HW_PINCTRL_PIN2IRQ4_SET (0x00001044) +#define HW_PINCTRL_PIN2IRQ4_CLR (0x00001048) +#define HW_PINCTRL_PIN2IRQ4_TOG (0x0000104c) + +#define BP_PINCTRL_PIN2IRQ4_RSRVD1 21 +#define BM_PINCTRL_PIN2IRQ4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_PIN2IRQ4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_PIN2IRQ4_RSRVD1) +#define BP_PINCTRL_PIN2IRQ4_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ4_PIN2IRQ 0x001FFFFF +#define BF_PINCTRL_PIN2IRQ4_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ4_PIN2IRQ) + +#define HW_PINCTRL_IRQEN0 (0x00001100) +#define HW_PINCTRL_IRQEN0_SET (0x00001104) +#define HW_PINCTRL_IRQEN0_CLR (0x00001108) +#define HW_PINCTRL_IRQEN0_TOG (0x0000110c) + +#define BP_PINCTRL_IRQEN0_RSRVD1 29 +#define BM_PINCTRL_IRQEN0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQEN0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQEN0_RSRVD1) +#define BP_PINCTRL_IRQEN0_IRQEN 0 +#define BM_PINCTRL_IRQEN0_IRQEN 0x1FFFFFFF +#define BF_PINCTRL_IRQEN0_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN0_IRQEN) + +#define HW_PINCTRL_IRQEN1 (0x00001110) +#define HW_PINCTRL_IRQEN1_SET (0x00001114) +#define HW_PINCTRL_IRQEN1_CLR (0x00001118) +#define HW_PINCTRL_IRQEN1_TOG (0x0000111c) + +#define BP_PINCTRL_IRQEN1_IRQEN 0 +#define BM_PINCTRL_IRQEN1_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN1_IRQEN(v) (v) + +#define HW_PINCTRL_IRQEN2 (0x00001120) +#define HW_PINCTRL_IRQEN2_SET (0x00001124) +#define HW_PINCTRL_IRQEN2_CLR (0x00001128) +#define HW_PINCTRL_IRQEN2_TOG (0x0000112c) + +#define BP_PINCTRL_IRQEN2_RSRVD1 28 +#define BM_PINCTRL_IRQEN2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQEN2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQEN2_RSRVD1) +#define BP_PINCTRL_IRQEN2_IRQEN 0 +#define BM_PINCTRL_IRQEN2_IRQEN 0x0FFFFFFF +#define BF_PINCTRL_IRQEN2_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN2_IRQEN) + +#define HW_PINCTRL_IRQEN3 (0x00001130) +#define HW_PINCTRL_IRQEN3_SET (0x00001134) +#define HW_PINCTRL_IRQEN3_CLR (0x00001138) +#define HW_PINCTRL_IRQEN3_TOG (0x0000113c) + +#define BM_PINCTRL_IRQEN3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQEN3_IRQEN 0 +#define BM_PINCTRL_IRQEN3_IRQEN 0x7FFFFFFF +#define BF_PINCTRL_IRQEN3_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN3_IRQEN) + +#define HW_PINCTRL_IRQEN4 (0x00001140) +#define HW_PINCTRL_IRQEN4_SET (0x00001144) +#define HW_PINCTRL_IRQEN4_CLR (0x00001148) +#define HW_PINCTRL_IRQEN4_TOG (0x0000114c) + +#define BP_PINCTRL_IRQEN4_RSRVD1 21 +#define BM_PINCTRL_IRQEN4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQEN4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQEN4_RSRVD1) +#define BP_PINCTRL_IRQEN4_IRQEN 0 +#define BM_PINCTRL_IRQEN4_IRQEN 0x001FFFFF +#define BF_PINCTRL_IRQEN4_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN4_IRQEN) + +#define HW_PINCTRL_IRQLEVEL0 (0x00001200) +#define HW_PINCTRL_IRQLEVEL0_SET (0x00001204) +#define HW_PINCTRL_IRQLEVEL0_CLR (0x00001208) +#define HW_PINCTRL_IRQLEVEL0_TOG (0x0000120c) + +#define BP_PINCTRL_IRQLEVEL0_RSRVD1 29 +#define BM_PINCTRL_IRQLEVEL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQLEVEL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQLEVEL0_RSRVD1) +#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0x1FFFFFFF +#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL0_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL1 (0x00001210) +#define HW_PINCTRL_IRQLEVEL1_SET (0x00001214) +#define HW_PINCTRL_IRQLEVEL1_CLR (0x00001218) +#define HW_PINCTRL_IRQLEVEL1_TOG (0x0000121c) + +#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQLEVEL2 (0x00001220) +#define HW_PINCTRL_IRQLEVEL2_SET (0x00001224) +#define HW_PINCTRL_IRQLEVEL2_CLR (0x00001228) +#define HW_PINCTRL_IRQLEVEL2_TOG (0x0000122c) + +#define BP_PINCTRL_IRQLEVEL2_RSRVD1 28 +#define BM_PINCTRL_IRQLEVEL2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQLEVEL2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQLEVEL2_RSRVD1) +#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0x0FFFFFFF +#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL2_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL3 (0x00001230) +#define HW_PINCTRL_IRQLEVEL3_SET (0x00001234) +#define HW_PINCTRL_IRQLEVEL3_CLR (0x00001238) +#define HW_PINCTRL_IRQLEVEL3_TOG (0x0000123c) + +#define BM_PINCTRL_IRQLEVEL3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQLEVEL3_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL3_IRQLEVEL 0x7FFFFFFF +#define BF_PINCTRL_IRQLEVEL3_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL3_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL4 (0x00001240) +#define HW_PINCTRL_IRQLEVEL4_SET (0x00001244) +#define HW_PINCTRL_IRQLEVEL4_CLR (0x00001248) +#define HW_PINCTRL_IRQLEVEL4_TOG (0x0000124c) + +#define BP_PINCTRL_IRQLEVEL4_RSRVD1 21 +#define BM_PINCTRL_IRQLEVEL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQLEVEL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQLEVEL4_RSRVD1) +#define BP_PINCTRL_IRQLEVEL4_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL4_IRQLEVEL 0x001FFFFF +#define BF_PINCTRL_IRQLEVEL4_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL4_IRQLEVEL) + +#define HW_PINCTRL_IRQPOL0 (0x00001300) +#define HW_PINCTRL_IRQPOL0_SET (0x00001304) +#define HW_PINCTRL_IRQPOL0_CLR (0x00001308) +#define HW_PINCTRL_IRQPOL0_TOG (0x0000130c) + +#define BP_PINCTRL_IRQPOL0_RSRVD1 29 +#define BM_PINCTRL_IRQPOL0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQPOL0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQPOL0_RSRVD1) +#define BP_PINCTRL_IRQPOL0_IRQPOL 0 +#define BM_PINCTRL_IRQPOL0_IRQPOL 0x1FFFFFFF +#define BF_PINCTRL_IRQPOL0_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL0_IRQPOL) + +#define HW_PINCTRL_IRQPOL1 (0x00001310) +#define HW_PINCTRL_IRQPOL1_SET (0x00001314) +#define HW_PINCTRL_IRQPOL1_CLR (0x00001318) +#define HW_PINCTRL_IRQPOL1_TOG (0x0000131c) + +#define BP_PINCTRL_IRQPOL1_IRQPOL 0 +#define BM_PINCTRL_IRQPOL1_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL1_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQPOL2 (0x00001320) +#define HW_PINCTRL_IRQPOL2_SET (0x00001324) +#define HW_PINCTRL_IRQPOL2_CLR (0x00001328) +#define HW_PINCTRL_IRQPOL2_TOG (0x0000132c) + +#define BP_PINCTRL_IRQPOL2_RSRVD1 28 +#define BM_PINCTRL_IRQPOL2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQPOL2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQPOL2_RSRVD1) +#define BP_PINCTRL_IRQPOL2_IRQPOL 0 +#define BM_PINCTRL_IRQPOL2_IRQPOL 0x0FFFFFFF +#define BF_PINCTRL_IRQPOL2_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL2_IRQPOL) + +#define HW_PINCTRL_IRQPOL3 (0x00001330) +#define HW_PINCTRL_IRQPOL3_SET (0x00001334) +#define HW_PINCTRL_IRQPOL3_CLR (0x00001338) +#define HW_PINCTRL_IRQPOL3_TOG (0x0000133c) + +#define BM_PINCTRL_IRQPOL3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQPOL3_IRQPOL 0 +#define BM_PINCTRL_IRQPOL3_IRQPOL 0x7FFFFFFF +#define BF_PINCTRL_IRQPOL3_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL3_IRQPOL) + +#define HW_PINCTRL_IRQPOL4 (0x00001340) +#define HW_PINCTRL_IRQPOL4_SET (0x00001344) +#define HW_PINCTRL_IRQPOL4_CLR (0x00001348) +#define HW_PINCTRL_IRQPOL4_TOG (0x0000134c) + +#define BP_PINCTRL_IRQPOL4_RSRVD1 21 +#define BM_PINCTRL_IRQPOL4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQPOL4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQPOL4_RSRVD1) +#define BP_PINCTRL_IRQPOL4_IRQPOL 0 +#define BM_PINCTRL_IRQPOL4_IRQPOL 0x001FFFFF +#define BF_PINCTRL_IRQPOL4_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL4_IRQPOL) + +#define HW_PINCTRL_IRQSTAT0 (0x00001400) +#define HW_PINCTRL_IRQSTAT0_SET (0x00001404) +#define HW_PINCTRL_IRQSTAT0_CLR (0x00001408) +#define HW_PINCTRL_IRQSTAT0_TOG (0x0000140c) + +#define BP_PINCTRL_IRQSTAT0_RSRVD1 29 +#define BM_PINCTRL_IRQSTAT0_RSRVD1 0xE0000000 +#define BF_PINCTRL_IRQSTAT0_RSRVD1(v) \ + (((v) << 29) & BM_PINCTRL_IRQSTAT0_RSRVD1) +#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0x1FFFFFFF +#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT0_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT1 (0x00001410) +#define HW_PINCTRL_IRQSTAT1_SET (0x00001414) +#define HW_PINCTRL_IRQSTAT1_CLR (0x00001418) +#define HW_PINCTRL_IRQSTAT1_TOG (0x0000141c) + +#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) (v) + +#define HW_PINCTRL_IRQSTAT2 (0x00001420) +#define HW_PINCTRL_IRQSTAT2_SET (0x00001424) +#define HW_PINCTRL_IRQSTAT2_CLR (0x00001428) +#define HW_PINCTRL_IRQSTAT2_TOG (0x0000142c) + +#define BP_PINCTRL_IRQSTAT2_RSRVD1 28 +#define BM_PINCTRL_IRQSTAT2_RSRVD1 0xF0000000 +#define BF_PINCTRL_IRQSTAT2_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_IRQSTAT2_RSRVD1) +#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0x0FFFFFFF +#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT2_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT3 (0x00001430) +#define HW_PINCTRL_IRQSTAT3_SET (0x00001434) +#define HW_PINCTRL_IRQSTAT3_CLR (0x00001438) +#define HW_PINCTRL_IRQSTAT3_TOG (0x0000143c) + +#define BM_PINCTRL_IRQSTAT3_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQSTAT3_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT3_IRQSTAT 0x7FFFFFFF +#define BF_PINCTRL_IRQSTAT3_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT3_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT4 (0x00001440) +#define HW_PINCTRL_IRQSTAT4_SET (0x00001444) +#define HW_PINCTRL_IRQSTAT4_CLR (0x00001448) +#define HW_PINCTRL_IRQSTAT4_TOG (0x0000144c) + +#define BP_PINCTRL_IRQSTAT4_RSRVD1 21 +#define BM_PINCTRL_IRQSTAT4_RSRVD1 0xFFE00000 +#define BF_PINCTRL_IRQSTAT4_RSRVD1(v) \ + (((v) << 21) & BM_PINCTRL_IRQSTAT4_RSRVD1) +#define BP_PINCTRL_IRQSTAT4_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT4_IRQSTAT 0x001FFFFF +#define BF_PINCTRL_IRQSTAT4_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT4_IRQSTAT) + +#define HW_PINCTRL_EMI_ODT_CTRL (0x00001a40) +#define HW_PINCTRL_EMI_ODT_CTRL_SET (0x00001a44) +#define HW_PINCTRL_EMI_ODT_CTRL_CLR (0x00001a48) +#define HW_PINCTRL_EMI_ODT_CTRL_TOG (0x00001a4c) + +#define BP_PINCTRL_EMI_ODT_CTRL_RSRVD1 28 +#define BM_PINCTRL_EMI_ODT_CTRL_RSRVD1 0xF0000000 +#define BF_PINCTRL_EMI_ODT_CTRL_RSRVD1(v) \ + (((v) << 28) & BM_PINCTRL_EMI_ODT_CTRL_RSRVD1) +#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 26 +#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB 0x0C000000 +#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB(v) \ + (((v) << 26) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 24 +#define BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD 0x03000000 +#define BF_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD(v) \ + (((v) << 24) & BM_PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 22 +#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB 0x00C00000 +#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB(v) \ + (((v) << 22) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 20 +#define BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD 0x00300000 +#define BF_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD(v) \ + (((v) << 20) & BM_PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 18 +#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB 0x000C0000 +#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB(v) \ + (((v) << 18) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 16 +#define BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD 0x00030000 +#define BF_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD(v) \ + (((v) << 16) & BM_PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 14 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB 0x0000C000 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB(v) \ + (((v) << 14) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 12 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD 0x00003000 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD(v) \ + (((v) << 12) & BM_PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 10 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB 0x00000C00 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB(v) \ + (((v) << 10) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 8 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD 0x00000300 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD(v) \ + (((v) << 8) & BM_PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 6 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB 0x000000C0 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB(v) \ + (((v) << 6) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 4 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD 0x00000030 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD(v) \ + (((v) << 4) & BM_PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 2 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB 0x0000000C +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB(v) \ + (((v) << 2) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB) +#define BP_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0 +#define BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD 0x00000003 +#define BF_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD(v) \ + (((v) << 0) & BM_PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD) + +#define HW_PINCTRL_EMI_DS_CTRL (0x00001b80) +#define HW_PINCTRL_EMI_DS_CTRL_SET (0x00001b84) +#define HW_PINCTRL_EMI_DS_CTRL_CLR (0x00001b88) +#define HW_PINCTRL_EMI_DS_CTRL_TOG (0x00001b8c) + +#define BP_PINCTRL_EMI_DS_CTRL_RSRVD1 18 +#define BM_PINCTRL_EMI_DS_CTRL_RSRVD1 0xFFFC0000 +#define BF_PINCTRL_EMI_DS_CTRL_RSRVD1(v) \ + (((v) << 18) & BM_PINCTRL_EMI_DS_CTRL_RSRVD1) +#define BP_PINCTRL_EMI_DS_CTRL_DDR_MODE 16 +#define BM_PINCTRL_EMI_DS_CTRL_DDR_MODE 0x00030000 +#define BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(v) \ + (((v) << 16) & BM_PINCTRL_EMI_DS_CTRL_DDR_MODE) +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__mDDR 00 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__GPIO 01 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__LVDDR2 10 +#define BV_PINCTRL_EMI_DS_CTRL_DDR_MODE__DDR2 11 +#define BP_PINCTRL_EMI_DS_CTRL_RSRVD0 14 +#define BM_PINCTRL_EMI_DS_CTRL_RSRVD0 0x0000C000 +#define BF_PINCTRL_EMI_DS_CTRL_RSRVD0(v) \ + (((v) << 14) & BM_PINCTRL_EMI_DS_CTRL_RSRVD0) +#define BP_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 12 +#define BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA 0x00003000 +#define BF_PINCTRL_EMI_DS_CTRL_ADDRESS_MA(v) \ + (((v) << 12) & BM_PINCTRL_EMI_DS_CTRL_ADDRESS_MA) +#define BP_PINCTRL_EMI_DS_CTRL_CONTROL_MA 10 +#define BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA 0x00000C00 +#define BF_PINCTRL_EMI_DS_CTRL_CONTROL_MA(v) \ + (((v) << 10) & BM_PINCTRL_EMI_DS_CTRL_CONTROL_MA) +#define BP_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 8 +#define BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA 0x00000300 +#define BF_PINCTRL_EMI_DS_CTRL_DUALPAD_MA(v) \ + (((v) << 8) & BM_PINCTRL_EMI_DS_CTRL_DUALPAD_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE3_MA 6 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA 0x000000C0 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE3_MA(v) \ + (((v) << 6) & BM_PINCTRL_EMI_DS_CTRL_SLICE3_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE2_MA 4 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA 0x00000030 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE2_MA(v) \ + (((v) << 4) & BM_PINCTRL_EMI_DS_CTRL_SLICE2_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE1_MA 2 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA 0x0000000C +#define BF_PINCTRL_EMI_DS_CTRL_SLICE1_MA(v) \ + (((v) << 2) & BM_PINCTRL_EMI_DS_CTRL_SLICE1_MA) +#define BP_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0 +#define BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA 0x00000003 +#define BF_PINCTRL_EMI_DS_CTRL_SLICE0_MA(v) \ + (((v) << 0) & BM_PINCTRL_EMI_DS_CTRL_SLICE0_MA) +#endif /* __ARCH_ARM___PINCTRL_H */ diff --git a/arch/arm/mach-mx28/serial.c b/arch/arm/mach-mx28/serial.c new file mode 100644 index 000000000000..a7297d1f62f6 --- /dev/null +++ b/arch/arm/mach-mx28/serial.c @@ -0,0 +1,309 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is distributed in the hope that it will be useful, + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "device.h" + +#if defined(CONFIG_SERIAL_MXS_AUART) || \ + defined(CONFIG_SERIAL_MXS_AUART_MODULE) + +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE +static struct resource auart0_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART0_PHYS_ADDR, + .end = AUART0_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART0_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART0_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0, + .end = IRQ_AUART0, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0_RX_DMA, + .end = IRQ_AUART0_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART0_TX_DMA, + .end = IRQ_AUART0_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart0_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART0_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE +static struct resource auart1_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART1_PHYS_ADDR, + .end = AUART1_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1, + .end = IRQ_AUART1, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1_RX_DMA, + .end = IRQ_AUART1_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART1_TX_DMA, + .end = IRQ_AUART1_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart1_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART1_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE +static struct resource auart2_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART2_PHYS_ADDR, + .end = AUART2_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2, + .end = IRQ_AUART2, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2_RX_DMA, + .end = IRQ_AUART2_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART2_TX_DMA, + .end = IRQ_AUART2_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart2_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART2_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE +static struct resource auart3_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART3_PHYS_ADDR, + .end = AUART3_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART3_RX, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART3_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3, + .end = IRQ_AUART3, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3_RX_DMA, + .end = IRQ_AUART3_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART3_TX_DMA, + .end = IRQ_AUART3_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart3_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART3_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +#ifdef CONFIG_MXS_AUART4_DEVICE_ENABLE +static struct resource auart4_resource[] = { + { + .flags = IORESOURCE_MEM, + .start = AUART4_PHYS_ADDR, + .end = AUART4_PHYS_ADDR + 0xFFF, + }, + { + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + .end = MXS_DMA_CHANNEL_AHB_APBX_UART4_TX, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4, + .end = IRQ_AUART4, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4_RX_DMA, + .end = IRQ_AUART4_RX_DMA, + }, + { + .flags = IORESOURCE_IRQ, + .start = IRQ_AUART4_TX_DMA, + .end = IRQ_AUART4_TX_DMA, + }, +}; + +static struct mxs_auart_plat_data mxs_auart4_platdata = { + .fifo_size = 16, +#ifdef CONFIG_MXS_AUART4_DMA_ENABLE + .dma_mode = 1, +#endif + .dma_rx_buffer_size = PAGE_SIZE, + .timeout = HZ, +}; +#endif + +void __init mx28_init_auart(void) +{ + int i; + struct mxs_dev_lookup *plookup; + struct platform_device *pdev; + + plookup = mxs_get_devices("mxs-auart"); + if (plookup == NULL || IS_ERR(plookup)) + return; + for (i = 0; i < plookup->size; i++) { + pdev = plookup->pdev + i; + switch (pdev->id) { +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE + case 0: + pdev->resource = auart0_resource; + pdev->num_resources = ARRAY_SIZE(auart0_resource); + pdev->dev.platform_data = &mxs_auart0_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE + case 1: + pdev->resource = auart1_resource; + pdev->num_resources = ARRAY_SIZE(auart1_resource); + pdev->dev.platform_data = &mxs_auart1_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE + case 2: + pdev->resource = auart2_resource; + pdev->num_resources = ARRAY_SIZE(auart2_resource); + pdev->dev.platform_data = &mxs_auart2_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE + case 3: + pdev->resource = auart3_resource; + pdev->num_resources = ARRAY_SIZE(auart3_resource); + pdev->dev.platform_data = &mxs_auart3_platdata; + break; +#endif +#ifdef CONFIG_MXS_AUART4_DEVICE_ENABLE + case 4: + pdev->resource = auart4_resource; + pdev->num_resources = ARRAY_SIZE(auart4_resource); + pdev->dev.platform_data = &mxs_auart4_platdata; + break; +#endif + default: + break; + } + mxs_add_device(pdev, 3); + } +} +#else +void __init mx28_init_auart(void) +{ +} +#endif diff --git a/arch/arm/mach-mx28/sleep.S b/arch/arm/mach-mx28/sleep.S new file mode 100644 index 000000000000..6c62bae310eb --- /dev/null +++ b/arch/arm/mach-mx28/sleep.S @@ -0,0 +1,698 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "regs-pinctrl.h" +#include "regs-clkctrl.h" +#include "regs-dram.h" +#include "sleep.h" + +#define BM_DRAM_CTL17_SREFRESH 0x00000001 +#define HW_CLKCTRL_CPU_ADDR \ + (MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_CPU) +#define HW_POWER_MINPWR_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_MINPWR) +#define HW_POWER_RESET_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_RESET) + +#define HW_DRAM_CTL17_ADDR \ + (MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL17) +#define HW_DRAM_CTL22_ADDR \ + (MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL22) + +#define HW_RTC_PERSISTENT0_ADDR \ + (MX28_SOC_IO_ADDRESS(RTC_PHYS_ADDR) + HW_RTC_PERSISTENT0) +#define HW_CLKCTRL_EMI_ADDR \ + (MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_EMI) +#define HW_CLKCTRL_PLL0CTRL0_ADDR \ + (MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_PLL0CTRL0) +#define HW_POWER_VDDIOCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDIOCTRL) +#define HW_POWER_VDDDCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDDCTRL) +#define HW_POWER_VDDACTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDACTRL) +#define HW_PINCTRL_EMI_DS_CTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(PINCTRL_PHYS_ADDR) + HW_PINCTRL_EMI_DS_CTRL) + +#define HW_POWER_5VCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_5VCTRL) +#define HW_POWER_LOOPCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_LOOPCTRL) +#define HW_POWER_STS_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_STS) +#define HW_POWER_MINPWR_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_MINPWR) + +#define PHYS_RAM_START 0x40000000 + +#define LOWER_VDDIO 5 +#define LOWER_VDDA 9 +#define LOWER_VDDD 12 + +#define VDDIOCTRL_BACKUP 0 +#define VDDACTRL_BACKUP 1 +#define VDDDCTRL_BACKUP 2 +#define POWER_LOOPCTRL_BACKUP 3 +#define POWER_MINPWR_BACKUP 4 + +.macro PM_BITS_SET, addr, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_BITS_CLR, addr, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_BACKUP_REG, addr, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + str r1, __mx28_temp_stack + \num * 4 +.endm + +.macro PM_WRITE_REG_MASK, addr, bitmask, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(\bitmask) + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_SET_AND_BACKUP_REG, addr, bitmask, val, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + str r1, __mx28_temp_stack + \num * 4 + bic r1, r1, #(\bitmask) + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_SET_RESTORE_REG, addr, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, __mx28_temp_stack + \num * 4 + str r1, [r0] +.endm + + +.global cpu_arm926_switch_mm + + .text + +.align 8 +ENTRY(mx28_cpu_standby) + @ save registers on stack + stmfd sp!, {r0 - r9, lr} + + adr r9, __mx28_temp_stack + + @ clean cache + ldr r1, __mx28_flush_cache_addr + mov lr, pc + mov pc, r1 + @ put DRAM into self refresh + mov r0, #(HW_DRAM_CTL22_ADDR & 0x000000FF) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0x0000FF00) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0x00FF0000) + orr r0, r0, #(HW_DRAM_CTL22_ADDR & 0xFF000000) + ldr r1,[r0] + and r1, r1, #(~BM_DRAM_CTL22_LOWPOWER_CONTROL) + orr r1, r1, #(BF_DRAM_CTL22_LOWPOWER_CONTROL(2)) + str r1, [r0] + + @ wait for it to actually happen + mov r0, #24 << 12 +11: sub r0, r0, #1 + cmp r0, #0 + bne 11b + + @ gate clk + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(BM_CLKCTRL_EMI_CLKGATE) + str r1, [r0] + +// PM_SET_AND_BACKUP_REG HW_PINCTRL_EMI_DS_CTRL_ADDR,\ +// BM_PINCTRL_EMI_DS_CTRL_DDR_MODE,\ +// BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(0x1), 4 + + mov r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x000000FF) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x0000FF00) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0x00FF0000) + orr r0, r0, #(HW_PINCTRL_EMI_DS_CTRL_ADDR & 0xFF000000) + ldr r1, [r0] + and r1, r1, #(~BM_PINCTRL_EMI_DS_CTRL_DDR_MODE) + orr r1, r1, #(BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(0x1)) + str r1, [r0] + + mov r2, #(HW_POWER_STS_ADDR & 0x000000FF) + orr r2, r2, #(HW_POWER_STS_ADDR & 0x0000FF00) + orr r2, r2, #(HW_POWER_STS_ADDR & 0x00FF0000) + orr r2, r2, #(HW_POWER_STS_ADDR & 0xFF000000) + // vddio + PM_SET_AND_BACKUP_REG HW_POWER_VDDIOCTRL_ADDR,\ + BM_POWER_VDDIOCTRL_TRG, LOWER_VDDIO, VDDIOCTRL_BACKUP + +7: + mov r0, #24 << 10 +1: sub r0, r0, #1 + cmp r0, #0 + bne 1b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 7b + + PM_SET_AND_BACKUP_REG HW_POWER_VDDACTRL_ADDR,\ + BM_POWER_VDDACTRL_TRG, LOWER_VDDA, VDDACTRL_BACKUP +8: + mov r0, #24 << 10 +2: sub r0, r0, #1 + cmp r0, #0 + bne 2b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 8b + + PM_SET_AND_BACKUP_REG HW_POWER_VDDDCTRL_ADDR,\ + BM_POWER_VDDDCTRL_TRG, LOWER_VDDD, VDDDCTRL_BACKUP +9: + mov r0, #24 << 10 +3: sub r0, r0, #1 + cmp r0, #0 + bne 3b + + ldr r0,[r2] + and r0,r0,#(BM_POWER_STS_DC_OK) + cmp r0,#(BM_POWER_STS_DC_OK) + bne 9b + + @ wait for DC OK + mov r0, #(HW_POWER_STS_ADDR & 0x000000FF) + orr r0, r0, #(HW_POWER_STS_ADDR & 0x0000FF00) + orr r0, r0, #(HW_POWER_STS_ADDR & 0x00FF0000) + orr r0, r0, #(HW_POWER_STS_ADDR & 0xFF000000) +4: ldr r1,[r0] + and r1,r1,#(BM_POWER_STS_DC_OK) + cmp r1,#(BM_POWER_STS_DC_OK) + bne 4b + + PM_BACKUP_REG HW_POWER_LOOPCTRL_ADDR, POWER_LOOPCTRL_BACKUP + PM_BACKUP_REG HW_POWER_MINPWR_ADDR, POWER_MINPWR_BACKUP + + PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_RCSCALE + PM_WRITE_REG_MASK HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_DC_R,\ + (2<operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static inline void dr_register_host(struct resource *r, int rs) +{ + PDATA->operating_mode = DR_HOST_MODE; + host_pdev_register(r, rs, PDATA); +} +#else +static inline void dr_register_host(struct resource *r, int rs) +{ +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static struct platform_device dr_udc_device; + +static inline void dr_register_udc(void) +{ + PDATA->operating_mode = DR_UDC_MODE; + dr_udc_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb: can't register DR gadget\n"); + else + printk(KERN_INFO "usb: DR gadget (%s) registered\n", + PDATA->transceiver); +} +#else +static inline void dr_register_udc(void) +{ +} +#endif + +#ifdef CONFIG_USB_OTG +static struct platform_device dr_otg_device; + +/* + * set the proper operating_mode and + * platform_data pointer, then register the + * device. + */ +static inline void dr_register_otg(void) +{ + PDATA->operating_mode = FSL_USB2_DR_OTG; + dr_otg_device.dev.platform_data = PDATA; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb: can't register otg device\n"); + else + printk(KERN_INFO "usb: DR OTG registered\n"); +} +#else +static inline void dr_register_otg(void) +{ +} +#endif diff --git a/arch/arm/mach-mx28/usb_dr.c b/arch/arm/mach-mx28/usb_dr.c new file mode 100644 index 000000000000..dff6b35840f2 --- /dev/null +++ b/arch/arm/mach-mx28/usb_dr.c @@ -0,0 +1,570 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "usb.h" +#include "mx28_pins.h" +#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_AUART2_TX) + +extern int clk_get_usecount(struct clk *clk); +static struct clk *usb_clk; +static struct clk *usb_phy_clk; +static struct platform_device *otg_host_pdev; + +/* Beginning of Common operation for DR port */ +void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this) +{ +} + +void fsl_phy_usb_utmi_uninit(struct fsl_xcvr_ops *this) +{ +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +void fsl_phy_set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + /* USB_POWER_ENABLE_PIN have request at pin init*/ + if (pdata->phy_regs != USBPHY1_PHYS_ADDR) { + pr_debug("%s: on is %d\n", __func__, on); + gpio_direction_output(USB_POWER_ENABLE, on); + gpio_set_value(USB_POWER_ENABLE, on); + } +} + +static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat) +{ + fsl_platform_set_usb_phy_dis(plat, 0); +} + +static int internal_phy_clk_already_on; +static void usbotg_internal_phy_clock_gate(bool on) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(USBPHY0_PHYS_ADDR); + if (on) { + internal_phy_clk_already_on += 1; + if (internal_phy_clk_already_on == 1) { + pr_debug ("%s, Clock on UTMI \n", __func__); + tmp = BM_USBPHY_CTRL_SFTRST | BM_USBPHY_CTRL_CLKGATE; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + } + } else { + internal_phy_clk_already_on -= 1; + if (internal_phy_clk_already_on == 0) { + pr_debug ("%s, Clock off UTMI \n", __func__); + tmp = BM_USBPHY_CTRL_CLKGATE; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } + } + if (internal_phy_clk_already_on < 0) + printk(KERN_ERR "please check internal phy clock ON/OFF sequence \n"); +} + +static int usbotg_init_ext(struct platform_device *pdev) +{ + usb_clk = clk_get(NULL, "usb_clk0"); + clk_enable(usb_clk); + clk_put(usb_clk); + + usb_phy_clk = clk_get(NULL, "usb_phy_clk0"); + clk_enable(usb_phy_clk); + clk_put(usb_phy_clk); + + usbotg_internal_phy_clock_gate(true); + return usbotg_init(pdev); +} + +static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + usbotg_uninit(pdata); + + usbotg_internal_phy_clock_gate(false); + clk_disable(usb_phy_clk); + clk_disable(usb_clk); +} + +static void usbotg_clock_gate(bool on) +{ + pr_debug("%s: on is %d\n", __func__, on); + if (on) { + clk_enable(usb_clk); + clk_enable(usb_phy_clk); + usbotg_internal_phy_clock_gate(on); + } else { + usbotg_internal_phy_clock_gate(on); + clk_disable(usb_phy_clk); + clk_disable(usb_clk); + } + + pr_debug("usb_clk0_ref_count:%d, usb_phy_clk0_ref_count:%d\n", clk_get_usecount(usb_clk), clk_get_usecount(usb_phy_clk)); +} + +/* Below two macros are used at otg mode to indicate usb mode*/ +#define ENABLED_BY_HOST (0x1 << 0) +#define ENABLED_BY_DEVICE (0x1 << 1) +static u32 low_power_enable_src; /* only useful at otg mode */ +static void enter_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + u32 tmp; + pr_debug("DR: %s, enable is %d\n", __func__, enable); + + if (enable) { + tmp = __raw_readl(usb_reg + UOG_PORTSC1); + tmp |= PORTSC_PHCD; + __raw_writel(tmp, usb_reg + UOG_PORTSC1); + + pr_debug("%s, Poweroff UTMI \n", __func__); + + tmp = (BM_USBPHY_PWD_TXPWDFS + | BM_USBPHY_PWD_TXPWDIBIAS + | BM_USBPHY_PWD_TXPWDV2I + | BM_USBPHY_PWD_RXPWDENV + | BM_USBPHY_PWD_RXPWD1PT1 + | BM_USBPHY_PWD_RXPWDDIFF + | BM_USBPHY_PWD_RXPWDRX); + __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET); + + pr_debug ("%s, Polling UTMI enter suspend \n", __func__); + while (tmp & BM_USBPHY_CTRL_UTMI_SUSPENDM) + tmp = __raw_readl(phy_reg + HW_USBPHY_CTRL); + } else { + tmp = (BM_USBPHY_PWD_TXPWDFS + | BM_USBPHY_PWD_TXPWDIBIAS + | BM_USBPHY_PWD_TXPWDV2I + | BM_USBPHY_PWD_RXPWDENV + | BM_USBPHY_PWD_RXPWD1PT1 + | BM_USBPHY_PWD_RXPWDDIFF + | BM_USBPHY_PWD_RXPWDRX); + __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR); + + tmp = __raw_readl(usb_reg + UOG_PORTSC1); + tmp &= ~PORTSC_PHCD; + __raw_writel(tmp, usb_reg + UOG_PORTSC1); + } +} + +static void __phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable, int source) +{ + if (enable) { + low_power_enable_src |= source; +#ifdef CONFIG_USB_OTG + if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { + pr_debug("phy lowpower enabled\n"); + enter_phy_lowpower_suspend(pdata, enable); + } +#else + enter_phy_lowpower_suspend(pdata, enable); +#endif + } else { + pr_debug("phy lowpower disable\n"); + enter_phy_lowpower_suspend(pdata, enable); + low_power_enable_src &= ~source; + } +} + +static void otg_wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + + pr_debug("%s, enable is %d\n", __func__, enable); + if (enable) { + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + + __raw_writel(BM_USBPHY_CTRL_ENIRQWAKEUP, phy_reg + HW_USBPHY_CTRL_SET); + } else { + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + + __raw_writel(BM_USBPHY_CTRL_ENIRQWAKEUP, phy_reg + HW_USBPHY_CTRL_CLR); + /* The interrupt must be disabled for at least 3 + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static u32 wakeup_irq_enable_src; /* only useful at otg mode */ +static void __wakeup_irq_enable(struct fsl_usb2_platform_data *pdata, bool on, int source) + { + /* otg host and device share the OWIE bit, only when host and device + * all enable the wakeup irq, we can enable the OWIE bit + */ + if (on) { +#ifdef CONFIG_USB_OTG + wakeup_irq_enable_src |= source; + if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { + otg_wake_up_enable(pdata, on); + } +#else + otg_wake_up_enable(pdata, on); +#endif + } else { + otg_wake_up_enable(pdata, on); + wakeup_irq_enable_src &= ~source; + /* The interrupt must be disabled for at least 3 clock + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +/* The wakeup operation for DR port, it will clear the wakeup irq status + * and re-enable the wakeup + */ +static void usbotg_wakeup_event_clear(void) +{ + void __iomem *phy_reg = IO_ADDRESS(USBPHY0_PHYS_ADDR); + u32 wakeup_irq_bits; + + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) { + /* clear the wakeup interrupt status */ + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + } +} + +/* End of Common operation for DR port */ + + +#ifdef CONFIG_USB_EHCI_ARC_OTG +extern void fsl_usb_recover_hcd(struct platform_device *pdev); +/* Beginning of host related operation for DR port */ +static void _host_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __phy_lowpower_suspend(pdata, enable, ENABLED_BY_HOST); +} + +static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + u32 tmp; + + __wakeup_irq_enable(pdata, enable, ENABLED_BY_HOST); + tmp = BM_USBPHY_CTRL_ENIDCHG_WKUP | BM_USBPHY_CTRL_ENDPDMCHG_WKUP; + /* host only care the ID change wakeup event */ + if (enable) { + pr_debug("DR: host wakeup enable\n"); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } else { + pr_debug("DR: host wakeup disable\n"); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + /* The interrupt must be disabled for at least 3 clock + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static enum usb_wakeup_event _is_host_wakeup(struct fsl_usb2_platform_data *pdata) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + u32 wakeup_irq_bits, wakeup_req, otgsc; + + pr_debug("%s\n", __func__); + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + otgsc = __raw_readl(usb_reg + UOG_OTGSC); + + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) + wakeup_req = 1; + + /* if ID change sts, it is a host wakeup event */ + if (wakeup_req && (otgsc & OTGSC_IS_USB_ID)) { + pr_debug("otg host ID wakeup\n"); + /* if host ID wakeup, we must clear the b session change sts */ + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + __raw_writel(otgsc & (~OTGSC_IS_USB_ID), usb_reg + UOG_OTGSC); + return WAKEUP_EVENT_ID; + } + if (wakeup_req && (!(otgsc & OTGSC_STS_USB_ID))) { + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + pr_debug("otg host Remote wakeup\n"); + return WAKEUP_EVENT_DPDM; + } + return WAKEUP_EVENT_INVALID; +} + +static void host_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _host_wakeup_enable(pdata, false); + _host_phy_lowpower_suspend(pdata, false); + fsl_usb_recover_hcd(otg_host_pdev); +} +/* End of host related operation for DR port */ +#endif /* CONFIG_USB_EHCI_ARC_OTG */ + + +#ifdef CONFIG_USB_GADGET_ARC +/* Beginning of device related operation for DR port */ +static void _device_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __phy_lowpower_suspend(pdata, enable, ENABLED_BY_DEVICE); +} + +static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + u32 tmp; + + tmp = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | BM_USBPHY_CTRL_ENDPDMCHG_WKUP; + __wakeup_irq_enable(pdata, enable, ENABLED_BY_DEVICE); + /* if udc is not used by any gadget, we can not enable the vbus wakeup */ + if (!pdata->port_enables) { + __raw_writel(BM_USBPHY_CTRL_ENVBUSCHG_WKUP, phy_reg + HW_USBPHY_CTRL_CLR); + return; + } + if (enable) { + pr_debug("device wakeup enable\n"); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } else { + pr_debug("device wakeup disable\n"); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + } +} + +static enum usb_wakeup_event _is_device_wakeup(struct fsl_usb2_platform_data *pdata) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + u32 wakeup_irq_bits, wakeup_req, otgsc; + + pr_debug("%s\n", __func__); + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + otgsc = __raw_readl(usb_reg + UOG_OTGSC); + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) { + wakeup_req = 1; + } + + /* if ID change sts, it is a host wakeup event */ + if (wakeup_req && (otgsc & OTGSC_STS_USB_ID) && (otgsc & OTGSC_IS_B_SESSION_VALID)) { + pr_debug("otg device wakeup\n"); + /* if host ID wakeup, we must clear the b session change sts */ + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + return WAKEUP_EVENT_VBUS; + } + + return WAKEUP_EVENT_INVALID; +} + +static void device_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _device_wakeup_enable(pdata, false); + _device_phy_lowpower_suspend(pdata, false); +} + +/* end of device related operation for DR port */ +#endif /* CONFIG_USB_GADGET_ARC */ + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init_ext, + .platform_uninit = usbotg_uninit_ext, + .usb_clock_for_pm = usbotg_clock_gate, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .platform_resume = usb_host_phy_resume, + .transceiver = "utmi", + .phy_regs = USBPHY0_PHYS_ADDR, +}; + +/* + * OTG resources + */ +static struct resource otg_resources[] = { + [0] = { + .start = (u32)USBCTRL0_PHYS_ADDR, + .end = (u32)(USBCTRL0_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB0, + .flags = IORESOURCE_IRQ, + }, +}; + +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)USBCTRL0_PHYS_ADDR, + .end = (u32)(USBCTRL0_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB0, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 dr_udc_dmamask = ~(u32) 0; +static void dr_udc_release(struct device *dev) +{ +} + +/* + * platform device structs + * dev.platform_data field plugged at run time + */ +static struct platform_device dr_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .release = dr_udc_release, + .dma_mask = &dr_udc_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + +static u64 dr_otg_dmamask = ~(u32) 0; +static void dr_otg_release(struct device *dev) +{} + +static struct platform_device __maybe_unused dr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, + .dev = { + .release = dr_otg_release, + .dma_mask = &dr_otg_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), +}; + +static struct resource usbotg_wakeup_resources[] = { + { + .start = IRQ_USB0_WAKEUP, /*wakeup irq*/ + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_USB0, /* usb core irq */ + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxs_usbotg_wakeup_device = { + .name = "usb_wakeup", + .id = 1, + .num_resources = ARRAY_SIZE(usbotg_wakeup_resources), + .resource = usbotg_wakeup_resources, +}; + +static struct fsl_usb2_wakeup_platform_data usbdr_wakeup_config = { + .name = "DR wakeup", + .usb_clock_for_pm = usbotg_clock_gate, + .usb_wakeup_exhandle = usbotg_wakeup_event_clear, +}; + +static int __init usb_dr_init(void) +{ + struct platform_device *pdev; + + pr_debug("%s: \n", __func__); + dr_utmi_config.change_ahb_burst = 1; + dr_utmi_config.ahb_burst_mode = 0; + +#ifdef CONFIG_USB_OTG + dr_utmi_config.operating_mode = FSL_USB2_DR_OTG; + /* wake_up_enalbe is useless, just for usb_register_remote_wakeup execution*/ + dr_utmi_config.wake_up_enable = _device_wakeup_enable; + dr_utmi_config.irq_delay = 0; + dr_utmi_config.wakeup_pdata = &usbdr_wakeup_config; + + if (platform_device_register(&dr_otg_device)) + printk(KERN_ERR "usb DR: can't register otg device\n"); + else { + platform_device_add_data(&dr_otg_device, &dr_utmi_config, sizeof(dr_utmi_config)); + usbdr_wakeup_config.usb_pdata[0] = dr_otg_device.dev.platform_data; + } +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG + dr_utmi_config.operating_mode = DR_HOST_MODE; + dr_utmi_config.wake_up_enable = _host_wakeup_enable; + dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend; + dr_utmi_config.wakeup_handler = host_wakeup_handler; + dr_utmi_config.is_wakeup_event = _is_host_wakeup; + dr_utmi_config.irq_delay = 0; + dr_utmi_config.wakeup_pdata = &usbdr_wakeup_config; + pdev = host_pdev_register(otg_resources, + ARRAY_SIZE(otg_resources), &dr_utmi_config); + if (pdev) { + usbdr_wakeup_config.usb_pdata[1] = pdev->dev.platform_data; + otg_host_pdev = pdev; + } else + printk(KERN_ERR "usb DR: can't alloc platform device for host\n"); +#endif + +#ifdef CONFIG_USB_GADGET_ARC + dr_utmi_config.operating_mode = DR_UDC_MODE; + dr_utmi_config.wake_up_enable = _device_wakeup_enable; + dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend; + dr_utmi_config.is_wakeup_event = _is_device_wakeup; + dr_utmi_config.wakeup_handler = device_wakeup_handler; + dr_utmi_config.irq_delay = 0; + dr_utmi_config.wakeup_pdata = &usbdr_wakeup_config; + + if (platform_device_register(&dr_udc_device)) + printk(KERN_ERR "usb DR: can't register udc device\n"); + else { + platform_device_add_data(&dr_udc_device, &dr_utmi_config, sizeof(dr_utmi_config)); + usbdr_wakeup_config.usb_pdata[2] = dr_udc_device.dev.platform_data; + } +#endif + + mxs_usbotg_wakeup_device.dev.platform_data = &usbdr_wakeup_config; + + if (platform_device_register(&mxs_usbotg_wakeup_device)) + printk(KERN_ERR "usb DR wakeup device\n"); + else + printk(KERN_INFO "usb DR wakeup device is registered\n"); + + return 0; +} +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + fs_initcall(usb_dr_init); +#else + subsys_initcall(usb_dr_init); +#endif diff --git a/arch/arm/mach-mx28/usb_h1.c b/arch/arm/mach-mx28/usb_h1.c new file mode 100644 index 000000000000..0c36d8f04130 --- /dev/null +++ b/arch/arm/mach-mx28/usb_h1.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "usb.h" + +extern int clk_get_usecount(struct clk *clk); +extern void fsl_usb_recover_hcd(struct platform_device *pdev); +static struct clk *usb_clk; +static struct clk *usb_phy_clk; +static struct platform_device *h1_pdev; + +static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat) +{ + fsl_platform_set_usb_phy_dis(plat, 0); +} + +static int internal_phy_clk_already_on; +static void usbh1_internal_phy_clock_gate(bool on) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(USBPHY1_PHYS_ADDR); + if (on) { + internal_phy_clk_already_on += 1; + if (internal_phy_clk_already_on == 1) { + pr_debug ("%s, Clock on UTMI \n", __func__); + tmp = BM_USBPHY_CTRL_SFTRST | BM_USBPHY_CTRL_CLKGATE; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + } + } else { + internal_phy_clk_already_on -= 1; + if (internal_phy_clk_already_on == 0) { + pr_debug ("%s, Clock off UTMI \n", __func__); + tmp = BM_USBPHY_CTRL_CLKGATE; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } + } + if (internal_phy_clk_already_on < 0) + printk(KERN_ERR "please check internal phy clock ON/OFF sequence \n"); +} +static int fsl_usb_host_init_ext(struct platform_device *pdev) +{ + usb_clk = clk_get(NULL, "usb_clk1"); + clk_enable(usb_clk); + clk_put(usb_clk); + + usb_phy_clk = clk_get(NULL, "usb_phy_clk1"); + clk_enable(usb_phy_clk); + clk_put(usb_phy_clk); + + usbh1_internal_phy_clock_gate(true); + return fsl_usb_host_init(pdev); +} + +static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + fsl_usb_host_uninit(pdata); + usbh1_internal_phy_clock_gate(false); + clk_disable(usb_phy_clk); + clk_disable(usb_clk); +} + +static void usbh1_clock_gate(bool on) +{ + pr_debug("%s: on is %d\n", __func__, on); + if (on) { + clk_enable(usb_clk); + clk_enable(usb_phy_clk); + } else { + clk_disable(usb_phy_clk); + clk_disable(usb_clk); + } + pr_debug("usb_clk1_ref_count:%d, usb_phy_clk1_ref_count:%d\n", clk_get_usecount(usb_clk), clk_get_usecount(usb_phy_clk)); +} + +static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + + pr_debug("host1, %s, enable is %d\n", __func__, enable); + if (enable) { + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + + tmp = (BM_USBPHY_CTRL_ENIRQWAKEUP + | BM_USBPHY_CTRL_ENIDCHG_WKUP + | BM_USBPHY_CTRL_ENDPDMCHG_WKUP); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_SET); + } else { + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + + tmp = (BM_USBPHY_CTRL_ENIRQWAKEUP + | BM_USBPHY_CTRL_ENIDCHG_WKUP + | BM_USBPHY_CTRL_ENDPDMCHG_WKUP); + + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + /* The interrupt must be disabled for at least 3 + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + pr_debug("host1, %s, enable is %d\n", __func__, enable); + if (enable) { + tmp = __raw_readl(usb_reg + UOG_PORTSC1); + tmp |= PORTSC_PHCD; + __raw_writel(tmp, usb_reg + UOG_PORTSC1); + + pr_debug("%s, Poweroff UTMI \n", __func__); + + tmp = (BM_USBPHY_PWD_TXPWDFS + | BM_USBPHY_PWD_TXPWDIBIAS + | BM_USBPHY_PWD_TXPWDV2I + | BM_USBPHY_PWD_RXPWDENV + | BM_USBPHY_PWD_RXPWD1PT1 + | BM_USBPHY_PWD_RXPWDDIFF + | BM_USBPHY_PWD_RXPWDRX); + __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET); + + pr_debug ("%s, Polling UTMI enter suspend \n", __func__); + while (tmp & BM_USBPHY_CTRL_UTMI_SUSPENDM) + tmp = __raw_readl(phy_reg + HW_USBPHY_CTRL); + } else { + tmp = (BM_USBPHY_PWD_TXPWDFS + | BM_USBPHY_PWD_TXPWDIBIAS + | BM_USBPHY_PWD_TXPWDV2I + | BM_USBPHY_PWD_RXPWDENV + | BM_USBPHY_PWD_RXPWD1PT1 + | BM_USBPHY_PWD_RXPWDDIFF + | BM_USBPHY_PWD_RXPWDRX); + __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR); + + tmp = __raw_readl(usb_reg + UOG_PORTSC1); + tmp &= ~PORTSC_PHCD; + __raw_writel(tmp, usb_reg + UOG_PORTSC1); + } +} + +static enum usb_wakeup_event _is_usbh1_wakeup(struct fsl_usb2_platform_data *pdata) +{ + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + u32 tmp; + + pr_debug("host1, %s\n", __func__); + tmp = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && tmp) { + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL_CLR); + return !WAKEUP_EVENT_INVALID; + } else + return WAKEUP_EVENT_INVALID; +} + +static void h1_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _wake_up_enable(pdata, false); + _phy_lowpower_suspend(pdata, false); + fsl_usb_recover_hcd(h1_pdev); +} + +static void usbh1_wakeup_event_clear(void) +{ + void __iomem *phy_reg = IO_ADDRESS(USBPHY1_PHYS_ADDR); + u32 wakeup_irq_bits; + + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + if (__raw_readl(phy_reg + HW_USBPHY_CTRL) && wakeup_irq_bits) { + /* clear the wakeup interrupt status */ + __raw_writel(wakeup_irq_bits, phy_reg + HW_USBPHY_CTRL_CLR); + } +} +static struct fsl_usb2_platform_data usbh1_config = { + .name = "Host 1", + .platform_init = fsl_usb_host_init_ext, + .platform_uninit = fsl_usb_host_uninit_ext, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .platform_resume = usb_host_phy_resume, + .transceiver = "utmi", + .usb_clock_for_pm = usbh1_clock_gate, + .wake_up_enable = _wake_up_enable, + .phy_lowpower_suspend = _phy_lowpower_suspend, + .is_wakeup_event = _is_usbh1_wakeup, + .wakeup_handler = h1_wakeup_handler, + .phy_regs = USBPHY1_PHYS_ADDR, +}; + +static struct fsl_usb2_wakeup_platform_data usbh1_wakeup_config = { + .name = "USBH1 wakeup", + .usb_clock_for_pm = usbh1_clock_gate, + .usb_pdata = {&usbh1_config, NULL, NULL}, + .usb_wakeup_exhandle = usbh1_wakeup_event_clear, +}; + +/* The resources for kinds of usb devices */ +static struct resource usbh1_resources[] = { + [0] = { + .start = (u32) (USBCTRL1_PHYS_ADDR), + .end = (u32) (USBCTRL1_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USB1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource usbh1_wakeup_resources[] = { + { + .start = IRQ_USB1_WAKEUP, /*wakeup irq*/ + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_USB1, + .flags = IORESOURCE_IRQ,/* usb core irq */ + }, +}; + +struct platform_device mxs_usbh1_wakeup_device = { + .name = "usb_wakeup", + .id = 2, + .num_resources = ARRAY_SIZE(usbh1_wakeup_resources), + .resource = usbh1_wakeup_resources, +}; + +static int __init usbh1_init(void) +{ + struct platform_device *pdev; + + usbh1_config.wakeup_pdata = &usbh1_wakeup_config; + pdev = host_pdev_register(usbh1_resources, + ARRAY_SIZE(usbh1_resources), &usbh1_config); + + h1_pdev = pdev; + pr_debug("%s: \n", __func__); + + /* the platform device(usb h1)'s pdata address has changed */ + usbh1_wakeup_config.usb_pdata[0] = pdev->dev.platform_data; + mxs_usbh1_wakeup_device.dev.platform_data = &usbh1_wakeup_config; + + if (platform_device_register(&mxs_usbh1_wakeup_device)) + printk(KERN_ERR "usb h1 wakeup device\n"); + else + printk(KERN_INFO "usb h1 wakeup device is registered\n"); + + return 0; +} +module_init(usbh1_init); diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 344753fdf25e..6286ceab5502 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -3,12 +3,28 @@ if ARCH_MX3 config ARCH_MX31 select ARCH_HAS_RNGA select ARCH_MXC_AUDMUX_V2 + select ARM_ERRATA_364296 + select ARM_ERRATA_411920 + select CACHE_L2X0 + select OUTER_CACHE + select USB_ARCH_HAS_EHCI + select ARCH_HAS_EVTMON + select ARCH_HAS_RNGA + select ISP1504_MXC bool config ARCH_MX35 bool select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 + select ARM_ERRATA_364296 + select ARM_ERRATA_411920 + select CACHE_L2X0 + select OUTER_CACHE + select USB_ARCH_HAS_EHCI + select ARCH_HAS_EVTMON + select ARCH_HAS_RNGA + select ISP1504_MXC comment "MX3 platforms:" @@ -58,6 +74,7 @@ config MACH_MX31LITE config MACH_MX31_3DS bool "Support MX31PDK (3DS)" select ARCH_MX31 + select MXC_DEBUG_BOARD help Include support for MX31PDK (3DS) platform. This includes specific configurations for the board and its peripherals. @@ -113,6 +130,11 @@ config MACH_ARMADILLO5X0 config MACH_MX35_3DS bool "Support MX35PDK platform" select ARCH_MX35 + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_SPI_IMX + select IMX_HAVE_PLATFORM_IMX_MMC + select MXC_ULPI if USB_ULPI default n help Include support for MX35PDK platform. This includes specific @@ -125,4 +147,42 @@ config MACH_KZM_ARM11_01 Include support for KZM-ARM11-01. This includes specific configurations for the board and its peripherals. + +config MXC_SDMA_API + bool "Use SDMA API" + default y + help + This selects the Freescale MXC SDMA API. + If unsure, say N. + +config SDMA_IRAM + bool "Use Internal RAM for SDMA transfer" + depends on MXC_SDMA_API + help + Support Internal RAM as SDMA buffer or control structures + + +config ARCH_MXC_HAS_NFC_V1 + bool "MXC NFC Hardware Version 1" + depends on !(MACH_MX31ADS && XIP_KERNEL) + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 1 + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V2 + bool "MXC NFC Hardware Version 2" + depends on !(MACH_MX31ADS && XIP_KERNEL) + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 2 + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V2_1 + bool "MXC NFC Hardware Version 2.1" + depends on ARCH_MXC_HAS_NFC_V2 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 2.1 + If unsure, say N. endif diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 5d650fda5d5d..3f7807be21f5 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -4,11 +4,10 @@ # Object file lists. -obj-y := mm.o devices.o cpu.o -CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS -obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o +obj-y := mm.o devices.o cpu.o system.o +obj-y += dma.o dummy_gpio.o mx3x-dma.o + +obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o entry-pm.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o @@ -16,11 +15,22 @@ obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o -CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ mx31moboard-marxbot.o mx31moboard-smartbot.o obj-$(CONFIG_MACH_QONG) += mach-qong.o obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o -obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o +obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o mx35_3ds_pmic_mc13892.o \ + mx35_3ds_pmic_mc9s08dz60.o mx35_3ds_pesudo_irq.o obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o + + +CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_mach-mx35_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS + +# power management +obj-$(CONFIG_PM) += pm.o + diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c index 9a9eb6de6127..cfe4a746937f 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@ -1,5 +1,5 @@ /* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. * Copyright (C) 2008 by Sascha Hauer * * This program is free software; you can redistribute it and/or @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include #include @@ -36,6 +38,11 @@ #define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */ +static int cpu_curr_wp; +static struct cpu_wp *cpu_wp_tbl; +static int cpu_wp_nr; +static int cpu_clk_set_wp(int wp); + static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) { u32 min_pre, temp_pre, old_err, err; @@ -70,6 +77,8 @@ static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) static struct clk mcu_pll_clk; static struct clk serial_pll_clk; +static struct clk usb_pll_clk; +static struct clk ahb_clk; static struct clk ipg_clk; static struct clk ckih_clk; @@ -117,6 +126,73 @@ static unsigned long pll_ref_get_rate(void) return clk_get_rate(&ckih_clk); } +static int pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + signed long pd = 1; /* Pre-divider */ + signed long mfi; /* Multiplication Factor (Integer part) */ + signed long mfn; /* Multiplication Factor (Integer part) */ + signed long mfd; /* Multiplication Factor (Denominator Part) */ + signed long tmp; + u32 ref_freq = clk_get_rate(clk->parent); + + while (((ref_freq / pd) * 10) > rate) + pd++; + + if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) + return -EINVAL; + + /* the ref_freq/2 in the following is to round up */ + mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq; + if (mfi < 5 || mfi > 15) + return -EINVAL; + + /* pick a mfd value that will work + * then solve for mfn */ + mfd = ref_freq / 50000; + + /* + * pll_freq * pd * mfd + * mfn = -------------------- - (mfi * mfd) + * 2 * ref_freq + */ + /* the tmp/2 is for rounding */ + tmp = ref_freq / 10000; + mfn = + ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) - + (mfi * mfd); + + mfn = mfn & 0x3ff; + pd--; + mfd--; + + /* Change the Pll value */ + reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) | + (mfn << MXC_CCM_PCTL_MFN_OFFSET) | + (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET); + + if (clk == &mcu_pll_clk) + __raw_writel(reg, MXC_CCM_MPCTL); + else if (clk == &usb_pll_clk) + __raw_writel(reg, MXC_CCM_UPCTL); + else if (clk == &serial_pll_clk) + __raw_writel(reg, MXC_CCM_SRPCTL); + + return 0; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + u32 ahb_rate = clk_get_rate(&ahb_clk); + if ((rate < ahb_rate) || (rate % ahb_rate != 0)) { + printk(KERN_ERR "Wrong rate %lu in _clk_cpu_set_rate\n", rate); + return -EINVAL; + } + + cpu_clk_set_wp(rate / ahb_rate - 1); + + return 0; +} static unsigned long usb_pll_get_rate(struct clk *clk) { unsigned long reg; @@ -209,6 +285,15 @@ static unsigned long mcu_main_get_rate(struct clk *clk) return clk_get_rate(&mcu_pll_clk); } +static unsigned long _clk_cpu_get_rate(struct clk *clk) +{ + unsigned long mcu_pdf; + + mcu_pdf = PDR0(MXC_CCM_PDR0_MCU_PODF_MASK, + MXC_CCM_PDR0_MCU_PODF_OFFSET); + return clk_get_rate(clk->parent) / (mcu_pdf + 1); +} + static unsigned long ahb_get_rate(struct clk *clk) { unsigned long max_pdf; @@ -414,6 +499,7 @@ static struct clk ckih_clk = { static struct clk mcu_pll_clk = { .parent = &ckih_clk, + .set_rate = pll_set_rate, .get_rate = mcu_pll_get_rate, }; @@ -424,6 +510,7 @@ static struct clk mcu_main_clk = { static struct clk serial_pll_clk = { .parent = &ckih_clk, + .set_rate = pll_set_rate, .get_rate = serial_pll_get_rate, .enable = serial_pll_enable, .disable = serial_pll_disable, @@ -431,11 +518,18 @@ static struct clk serial_pll_clk = { static struct clk usb_pll_clk = { .parent = &ckih_clk, + .set_rate = pll_set_rate, .get_rate = usb_pll_get_rate, .enable = usb_pll_enable, .disable = usb_pll_disable, }; +static struct clk cpu_clk = { + .parent = &mcu_main_clk, + .get_rate = _clk_cpu_get_rate, + .set_rate = _clk_cpu_set_rate, +}; + static struct clk ahb_clk = { .parent = &mcu_main_clk, .get_rate = ahb_get_rate, @@ -524,6 +618,7 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); }, static struct clk_lookup lookups[] = { + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) _REGISTER_CLOCK(NULL, "emi", emi_clk) _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) @@ -574,37 +669,33 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "mbx", mbx_clk) }; +static struct mxc_clk mxc_clks[ARRAY_SIZE(lookups)]; + int __init mx31_clocks_init(unsigned long fref) { u32 reg; + int i; ckih_rate = fref; clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + clkdev_add(&lookups[i]); + mxc_clks[i].reg_clk = lookups[i].clk; + if (lookups[i].con_id != NULL) + strcpy(mxc_clks[i].name, lookups[i].con_id); + else + strcpy(mxc_clks[i].name, lookups[i].dev_id); + clk_register(&mxc_clks[i]); + } + /* change the csi_clk parent if necessary */ reg = __raw_readl(MXC_CCM_CCMR); if (!(reg & MXC_CCM_CCMR_CSCS)) if (clk_set_parent(&csi_clk, &usb_pll_clk)) pr_err("%s: error changing csi_clk parent\n", __func__); - - /* Turn off all possible clocks */ - __raw_writel((3 << 4), MXC_CCM_CGR0); - __raw_writel(0, MXC_CCM_CGR1); - __raw_writel((3 << 8) | (3 << 14) | (3 << 16)| - 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for - MX32, but still required to be set */ - MXC_CCM_CGR2); - - /* - * Before turning off usb_pll make sure ipg_per_clk is generated - * by ipg_clk and not usb_pll. - */ - __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR); - - usb_pll_disable(&usb_pll_clk); - pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); clk_enable(&gpt_clk); @@ -622,9 +713,137 @@ int __init mx31_clocks_init(unsigned long fref) __raw_writel(reg, MXC_CCM_PMCR1); } + cpu_curr_wp = clk_get_rate(&cpu_clk) / clk_get_rate(&ahb_clk) - 1; + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + + /* Init serial PLL according */ + clk_set_rate(&serial_pll_clk, (cpu_wp_tbl[2].pll_rate)); + mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); return 0; } +#define MXC_PMCR0_DVFS_MASK (MXC_CCM_PMCR0_DVSUP_MASK | \ + MXC_CCM_PMCR0_UDSC_MASK | \ + MXC_CCM_PMCR0_VSCNT_MASK | \ + MXC_CCM_PMCR0_DPVCR) + +#define MXC_PDR0_MAX_MCU_MASK (MXC_CCM_PDR0_MAX_PODF_MASK | \ + MXC_CCM_PDR0_MCU_PODF_MASK | \ + MXC_CCM_PDR0_HSP_PODF_MASK | \ + MXC_CCM_PDR0_IPG_PODF_MASK | \ + MXC_CCM_PDR0_NFC_PODF_MASK) + +/*! + * Setup cpu clock based on working point. + * @param wp cpu freq working point (0 is the slowest) + * @return 0 on success or error code on failure. + */ +static int cpu_clk_set_wp(int wp) +{ + struct cpu_wp *p; + u32 dvsup; + u32 pmcr0, pmcr1; + u32 pdr0; + u32 cgr2 = 0x80000000; + u32 vscnt = MXC_CCM_PMCR0_VSCNT_2; + u32 udsc = MXC_CCM_PMCR0_UDSC_DOWN; + void __iomem *ipu_base = MX31_IO_ADDRESS(MX31_IPU_CTRL_BASE_ADDR); + u32 ipu_conf; + + if (wp >= cpu_wp_nr || wp < 0) { + printk(KERN_ERR "Wrong wp: %d for cpu_clk_set_wp\n", wp); + return -EINVAL; + } + if (wp == cpu_curr_wp) + return 0; + + pmcr0 = __raw_readl(MXC_CCM_PMCR0); + pmcr1 = __raw_readl(MXC_CCM_PMCR1); + pdr0 = __raw_readl(MXC_CCM_PDR0); + + if (!(pmcr0 & MXC_CCM_PMCR0_UPDTEN)) + return -EBUSY; + + if (wp > cpu_curr_wp) { + /* going faster */ + if (wp == (cpu_wp_nr - 1)) { + /* Only update vscnt going into Turbo */ + vscnt = MXC_CCM_PMCR0_VSCNT_8; + } + udsc = MXC_CCM_PMCR0_UDSC_UP; + } + + p = &cpu_wp_tbl[wp]; + + dvsup = (cpu_wp_nr - 1 - wp) << MXC_CCM_PMCR0_DVSUP_OFFSET; + + if ((clk_get_rate(&mcu_main_clk) == 399000000) && + (p->cpu_rate == 532000000)) { + cgr2 = __raw_readl(MXC_CCM_CGR2); + cgr2 &= 0x7fffffff; + vscnt = 0; + pmcr0 = (pmcr0 & ~MXC_PMCR0_DVFS_MASK) | dvsup | vscnt; + pr_debug("manul dvfs, dvsup = %x\n", dvsup); + __raw_writel(cgr2, MXC_CCM_CGR2); + __raw_writel(pmcr0, MXC_CCM_PMCR0); + udelay(100); + } + + if (clk_get_rate(&mcu_main_clk) == p->pll_rate) { + /* No pll switching and relocking needed */ + pmcr0 |= MXC_CCM_PMCR0_DFSUP0_PDR; + } else { + /* pll switching and relocking needed */ + pmcr0 ^= MXC_CCM_PMCR0_DFSUP1; /* flip MSB bit */ + pmcr0 &= ~(MXC_CCM_PMCR0_DFSUP0); + } + + pmcr0 = (pmcr0 & ~MXC_PMCR0_DVFS_MASK) | dvsup | vscnt | udsc; + /* also enable DVFS hardware */ + pmcr0 |= MXC_CCM_PMCR0_DVFEN; + + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + /* IPU and DI submodule must be on for PDR0 update to take effect */ + if (!clk_get_usecount(&ipu_clk)) + ipu_clk.enable(&ipu_clk); + ipu_conf = __raw_readl(ipu_base); + if (!(ipu_conf & 0x40)) + __raw_writel(ipu_conf | 0x40, ipu_base); + + __raw_writel((pdr0 & ~MXC_PDR0_MAX_MCU_MASK) | p->pdr0_reg, + MXC_CCM_PDR0); + + if ((pmcr0 & MXC_CCM_PMCR0_DFSUP0) == MXC_CCM_PMCR0_DFSUP0_PLL) { + /* prevent pll restart */ + pmcr1 |= 0x80; + __raw_writel(pmcr1, MXC_CCM_PMCR1); + /* PLL and post divider update */ + if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == + MXC_CCM_PMCR0_DFSUP1_SPLL) { + __raw_writel(p->pll_reg, MXC_CCM_SRPCTL); + mcu_main_clk.parent = &serial_pll_clk; + } else { + __raw_writel(p->pll_reg, MXC_CCM_MPCTL); + mcu_main_clk.parent = &mcu_pll_clk; + } + } + + if ((cgr2 & 0x80000000) == 0x0) { + pr_debug("start auto dvfs\n"); + cgr2 |= 0x80000000; + __raw_writel(cgr2, MXC_CCM_CGR2); + } + + cpu_curr_wp = wp; + + /* Restore IPU_CONF setting */ + __raw_writel(ipu_conf, ipu_base); + if (!clk_get_usecount(&ipu_clk)) + ipu_clk.disable(&ipu_clk); + + return 0; +} diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 9f3e943e2232..afd9fe7ea524 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -21,6 +21,7 @@ #include #include #include +#include #include @@ -370,7 +371,8 @@ DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL); DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL); DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL); DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL); -DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL); +DEFINE_CLOCK(sdma_a_clk, 0, CCM_CGR2, 6, get_rate_ahb, NULL); +DEFINE_CLOCK(sdma_p_clk, 0, CCM_CGR2, 6, get_rate_ipg, NULL); DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL); DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL); DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL); @@ -438,9 +440,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "epit", epit1_clk) _REGISTER_CLOCK(NULL, "epit", epit2_clk) _REGISTER_CLOCK(NULL, "esai", esai_clk) - _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk) - _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk) - _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk) + _REGISTER_CLOCK("mxsdhci.0", NULL, esdhc1_clk) + _REGISTER_CLOCK("mxsdhci.1", NULL, esdhc2_clk) + _REGISTER_CLOCK("mxsdhci.2", NULL, esdhc3_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK(NULL, "gpio", gpio1_clk) _REGISTER_CLOCK(NULL, "gpio", gpio2_clk) @@ -461,7 +463,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "rtc", rtc_clk) _REGISTER_CLOCK(NULL, "rtic", rtic_clk) _REGISTER_CLOCK(NULL, "scc", scc_clk) - _REGISTER_CLOCK(NULL, "sdma", sdma_clk) + _REGISTER_CLOCK(NULL, "sdma_ahb_clk", sdma_a_clk) + _REGISTER_CLOCK(NULL, "sdma_ipg_clk", sdma_p_clk) _REGISTER_CLOCK(NULL, "spba", spba_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) @@ -483,9 +486,12 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) }; +static struct mxc_clk mxc_clks[ARRAY_SIZE(lookups)]; + int __init mx35_clocks_init() { unsigned int ll = 0; + int i; #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) ll = (3 << 16); @@ -493,6 +499,16 @@ int __init mx35_clocks_init() clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + mxc_clks[i].reg_clk = lookups[i].clk; + if (lookups[i].con_id != NULL) + strcpy(mxc_clks[i].name, lookups[i].con_id); + else + strcpy(mxc_clks[i].name, lookups[i].dev_id); + clk_register(&mxc_clks[i]); + } + + /* Turn off all clocks except the ones we need to survive, namely: * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart */ diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c index 861afe0fe3ad..78d485471542 100644 --- a/arch/arm/mach-mx3/cpu.c +++ b/arch/arm/mach-mx3/cpu.c @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -55,3 +56,39 @@ void __init mx31_read_cpu_rev(void) printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); } + +/*! + * Post CPU init code + * + * @return 0 always + */ +static int __init post_cpu_init(void) +{ + volatile unsigned long aips_reg; + + iram_init(MX31_IRAM_BASE_ADDR, MX31_IRAM_SIZE); + + /* + * S/W workaround: Clear the off platform peripheral modules + * Supervisor Protect bit for SDMA to access them. + */ + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48)); + __raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C)); + aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50)); + aips_reg &= 0x00FFFFFF; + __raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50)); + + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48)); + __raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C)); + aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50)); + aips_reg &= 0x00FFFFFF; + __raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50)); + + return 0; +} + +postcore_initcall(post_cpu_init); diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h index 37a8a07beda3..58d17a1d0a91 100644 --- a/arch/arm/mach-mx3/crm_regs.h +++ b/arch/arm/mach-mx3/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. * Copyright (C) 2008 by Sascha Hauer * * This program is free software; you can redistribute it and/or @@ -55,6 +55,9 @@ #define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64) /* Register bit definitions */ +#define MX35_CCM_CCMR_WFI (1 << 30) +#define MX35_CCM_CCMR_STBY_EXIT_SRC (1 << 29) +#define MXC_CCM_CCMR_VSTBY (1 << 28) #define MXC_CCM_CCMR_WBEN (1 << 27) #define MXC_CCM_CCMR_CSCS (1 << 25) #define MXC_CCM_CCMR_PERCS (1 << 24) @@ -66,6 +69,7 @@ #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) #define MXC_CCM_CCMR_FIRS_OFFSET 11 #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) +#define MXC_CCM_CCMR_WAMO (1 << 10) #define MXC_CCM_CCMR_UPE (1 << 9) #define MXC_CCM_CCMR_SPE (1 << 8) #define MXC_CCM_CCMR_MDS (1 << 7) @@ -91,6 +95,47 @@ #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 +#define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11) +#define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11) +#define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11) +#define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11) +#define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11) +#define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11) +#define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11) +#define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11) + +#define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6) +#define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6) +#define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6) +#define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6) + +#define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3) +#define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3) +#define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3) +#define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3) +#define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3) +#define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3) +#define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3) +#define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3) + +#define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8) +#define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8) +#define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8) +#define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8) +#define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8) +#define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8) +#define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8) +#define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8) + +#define MXC_CCM_PDR0_MCU_DIV_1 0x0 +#define MXC_CCM_PDR0_MCU_DIV_2 0x1 +#define MXC_CCM_PDR0_MCU_DIV_3 0x2 +#define MXC_CCM_PDR0_MCU_DIV_4 0x3 +#define MXC_CCM_PDR0_MCU_DIV_5 0x4 +#define MXC_CCM_PDR0_MCU_DIV_6 0x5 +#define MXC_CCM_PDR0_MCU_DIV_7 0x6 +#define MXC_CCM_PDR0_MCU_DIV_8 0x7 + #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 @@ -109,7 +154,120 @@ #define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F /* Bit definitions for RCSR */ -#define MXC_CCM_RCSR_NF16B 0x80000000 +#define MXC_CCM_RCSR_NF16B (0x1 << 31) +#define MXC_CCM_RCSR_NFMS (0x1 << 30) + +/* Bit definitions for both MCU, USB and SR PLL control registers */ +#define MXC_CCM_PCTL_BRM 0x80000000 +#define MXC_CCM_PCTL_PD_OFFSET 26 +#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +#define MXC_CCM_PCTL_MFD_OFFSET 16 +#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +#define MXC_CCM_PCTL_MFI_OFFSET 10 +#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +#define MXC_CCM_PCTL_MFN_OFFSET 0 +#define MXC_CCM_PCTL_MFN_MASK 0x3FF + +#define MXC_CCM_CGR0_SD_MMC1_OFFSET 0 +#define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0) +#define MXC_CCM_CGR0_SD_MMC2_OFFSET 2 +#define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2) +#define MXC_CCM_CGR0_GPT_OFFSET 4 +#define MXC_CCM_CGR0_GPT_MASK (0x3 << 4) +#define MXC_CCM_CGR0_EPIT1_OFFSET 6 +#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6) +#define MXC_CCM_CGR0_EPIT2_OFFSET 8 +#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8) +#define MXC_CCM_CGR0_IIM_OFFSET 10 +#define MXC_CCM_CGR0_IIM_MASK (0x3 << 10) +#define MXC_CCM_CGR0_ATA_OFFSET 12 +#define MXC_CCM_CGR0_ATA_MASK (0x3 << 12) +#define MXC_CCM_CGR0_SDMA_OFFSET 14 +#define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14) +#define MXC_CCM_CGR0_CSPI3_OFFSET 16 +#define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16) +#define MXC_CCM_CGR0_RNG_OFFSET 18 +#define MXC_CCM_CGR0_RNG_MASK (0x3 << 18) +#define MXC_CCM_CGR0_UART1_OFFSET 20 +#define MXC_CCM_CGR0_UART1_MASK (0x3 << 20) +#define MXC_CCM_CGR0_UART2_OFFSET 22 +#define MXC_CCM_CGR0_UART2_MASK (0x3 << 22) +#define MXC_CCM_CGR0_SSI1_OFFSET 24 +#define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24) +#define MXC_CCM_CGR0_I2C1_OFFSET 26 +#define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26) +#define MXC_CCM_CGR0_I2C2_OFFSET 28 +#define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28) +#define MXC_CCM_CGR0_I2C3_OFFSET 30 +#define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30) + +#define MXC_CCM_CGR1_HANTRO_OFFSET 0 +#define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0) +#define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2 +#define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2) +#define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4 +#define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4) +#define MXC_CCM_CGR1_CSI_OFFSET 6 +#define MXC_CCM_CGR1_CSI_MASK (0x3 << 6) +#define MXC_CCM_CGR1_RTC_OFFSET 8 +#define MXC_CCM_CGR1_RTC_MASK (0x3 << 8) +#define MXC_CCM_CGR1_WDOG_OFFSET 10 +#define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10) +#define MXC_CCM_CGR1_PWM_OFFSET 12 +#define MXC_CCM_CGR1_PWM_MASK (0x3 << 12) +#define MXC_CCM_CGR1_SIM_OFFSET 14 +#define MXC_CCM_CGR1_SIM_MASK (0x3 << 14) +#define MXC_CCM_CGR1_ECT_OFFSET 16 +#define MXC_CCM_CGR1_ECT_MASK (0x3 << 16) +#define MXC_CCM_CGR1_USBOTG_OFFSET 18 +#define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18) +#define MXC_CCM_CGR1_KPP_OFFSET 20 +#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +#define MXC_CCM_CGR1_IPU_OFFSET 22 +#define MXC_CCM_CGR1_IPU_MASK (0x3 << 22) +#define MXC_CCM_CGR1_UART3_OFFSET 24 +#define MXC_CCM_CGR1_UART3_MASK (0x3 << 24) +#define MXC_CCM_CGR1_UART4_OFFSET 26 +#define MXC_CCM_CGR1_UART4_MASK (0x3 << 26) +#define MXC_CCM_CGR1_UART5_OFFSET 28 +#define MXC_CCM_CGR1_UART5_MASK (0x3 << 28) +#define MXC_CCM_CGR1_OWIRE_OFFSET 30 +#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30) + +#define MXC_CCM_CGR2_SSI2_OFFSET 0 +#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0) +#define MXC_CCM_CGR2_CSPI1_OFFSET 2 +#define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2) +#define MXC_CCM_CGR2_CSPI2_OFFSET 4 +#define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4) +#define MXC_CCM_CGR2_GACC_OFFSET 6 +#define MXC_CCM_CGR2_GACC_MASK (0x3 << 6) +#define MXC_CCM_CGR2_EMI_OFFSET 8 +#define MXC_CCM_CGR2_EMI_MASK (0x3 << 8) +#define MXC_CCM_CGR2_RTIC_OFFSET 10 +#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10) +#define MXC_CCM_CGR2_FIRI_OFFSET 12 +#define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12) +#define MXC_CCM_CGR2_IPMUX1_OFFSET 14 +#define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14) +#define MXC_CCM_CGR2_IPMUX2_OFFSET 16 +#define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16) + +/* These new CGR2 bits are added in MX32 */ +#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18 +#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18) +#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20 +#define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20) +#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22 +#define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22) +#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24 +#define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24) +#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25 +#define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25) +#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26 +#define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26) +#define MXC_CCM_CGR2_APMENA_OFFSET 30 +#define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30) /* * LTR0 register offsets diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h new file mode 100644 index 000000000000..e4ed1c964cdf --- /dev/null +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx31_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata) +#define imx31_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata) +#define imx31_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata) + +extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; +#define imx31_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) +#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata) +#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata) +#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata) +#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) +#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) + +#define imx31_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata) + +#define imx31_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata) +#define imx31_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata) +#define imx31_add_spi_imx2(pdata) \ + imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h new file mode 100644 index 000000000000..d0e4415943e4 --- /dev/null +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx35_add_flexcan0(pdata) \ + imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) +#define imx35_add_flexcan1(pdata) \ + imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) + +#define imx35_add_imx_i2c0(pdata) \ + imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata) +#define imx35_add_imx_i2c1(pdata) \ + imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata) +#define imx35_add_imx_i2c2(pdata) \ + imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata) + +extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; +#define imx35_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) +#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata) +#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) +#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) + +#define imx35_add_mxc_nand(pdata) \ + imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata) + +#define imx35_add_spi_imx0(pdata) \ + imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata) +#define imx35_add_spi_imx1(pdata) \ + imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata) + +#define imx35_add_imx_mmc0(pdata) \ + imx_add_imx_mmc(0, MX35_MMC_SDHC1_BASE_ADDR, SZ_4K, MX35_INT_MMC_SDHC1, MXC_PSEUDO_IRQ_SD1_CD, pdata) +#define imx35_add_imx_mmc1(pdata) \ + imx_add_imx_mmc(1, MX35_MMC_SDHC2_BASE_ADDR, SZ_4K, MX35_INT_MMC_SDHC2, 0, pdata) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index db7acd6e9101..73f97546216a 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -1,5 +1,5 @@ /* - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2006-2010 Freescale Semiconductor, Inc. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -27,6 +27,9 @@ #include #include #include +#include +#include +#include #include "devices.h" @@ -186,6 +189,41 @@ struct platform_device mxc_nand_device = { .resource = mxc_nand_resources, }; +static struct resource mxc_nor_flash_resource = { + .start = 0xa0000000, + .end = 0xa0000000 + 0x04000000 - 1, + .flags = IORESOURCE_MEM, + +}; + +struct platform_device mxc_nor_mtd_device = { + .name = "mxc_nor_flash", + .id = 0, + .num_resources = 1, + .resource = &mxc_nor_flash_resource, +}; + +static struct resource mxc_nandv2_resources[] = { + { + .flags = IORESOURCE_MEM, + .name = "NFC_AXI_BASE", + .start = 0, /* runtime dependent */ + .end = 0, + }, + { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_NANDFC, + .end = MXC_INT_NANDFC, + }, +}; + +struct platform_device mxc_nandv2_device = { + .name = "mxc_nandv2_flash", + .id = 0, + .resource = mxc_nandv2_resources, + .num_resources = ARRAY_SIZE(mxc_nandv2_resources), +}; + static struct resource mxc_i2c0_resources[] = { { .start = I2C_BASE_ADDR, @@ -626,6 +664,146 @@ struct platform_device imx_kpp_device = { .resource = imx_kpp_resources, }; + +static struct resource sdma_resources[] = { + { + .start = SDMA_BASE_ADDR, + .end = SDMA_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SDMA, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_dma_device = { + .name = "mxc_sdma", + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(sdma_resources), + .resource = sdma_resources, +}; + +static struct resource ipu_resources[] = { + { + .start = IPU_CTRL_BASE_ADDR, + .end = IPU_CTRL_BASE_ADDR + SZ_4K, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_IPU_SYN, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_IPU_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_ipu_device = { + .name = "mxc_ipu", + .id = -1, + .num_resources = ARRAY_SIZE(ipu_resources), + .resource = ipu_resources, +}; + +static struct platform_device mxc_alsa_device = { + .name = "mxc_alsa", + .id = 0, +}; + +static struct platform_device mxc_scc_device = { + .name = "mxc_scc", + .id = 0, +}; + +static struct platform_device hmp4e_device = { + .name = "mxc_hmp4e", + .id = 0, +}; + +/*! + * Resource definition for the DPTC LP + */ +static struct resource dptc_resources[] = { + [0] = { + .start = CCM_BASE_ADDR, + .end = CCM_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_CCM, + .end = MXC_INT_CCM, + .flags = IORESOURCE_IRQ, + }, +}; + +/*! Device Definition for MXC DPTC */ +static struct platform_device mxc_dptc_device = { + .name = "mxc_dptc", + .id = 0, + .num_resources = ARRAY_SIZE(dptc_resources), + .resource = dptc_resources, +}; + +static struct resource mxc_iim_resources[] = { + { + .start = MX31_IIM_BASE_ADDR, + .end = MX31_IIM_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_iim_data iim_data = { + .bank_start = MXC_IIM_BANK_START_ADDR, + .bank_end = MXC_IIM_BANK_END_ADDR, +}; + +static struct platform_device mxc_iim_device = { + .name = "mxc_iim", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_iim_resources), + .resource = mxc_iim_resources, + .dev.platform_data = &iim_data, +}; + +static inline void mxc_init_iim(void) +{ + if (platform_device_register(&mxc_iim_device) < 0) + dev_err(&mxc_iim_device.dev, + "Unable to register mxc iim device\n"); +} + +static struct resource pata_fsl_resources[] = { + { + .start = MX31_ATA_BASE_ADDR, + .end = MX31_ATA_BASE_ADDR + 0xD8, + .flags = IORESOURCE_MEM, + }, + { + .start = MX31_INT_ATA, + .end = MX31_INT_ATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pata_fsl_device = { + .name = "pata_fsl", + .id = -1, + .num_resources = ARRAY_SIZE(pata_fsl_resources), + .resource = pata_fsl_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device mxc_pseudo_irq_device = { + .name = "mxc_pseudo_irq", + .id = 0, +}; +volatile u32 *mx3_usb_otg_addr; static int __init mx3_devices_init(void) { if (cpu_is_mx31()) { @@ -634,10 +812,11 @@ static int __init mx3_devices_init(void) imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; mxc_register_device(&mxc_rnga_device, NULL); + mx3_usb_otg_addr = MX31_OTG_BASE_ADDR; } if (cpu_is_mx35()) { - mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; - mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff; + mxc_nandv2_resources[0].start = MX35_NFC_BASE_ADDR; + mxc_nandv2_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff; otg_resources[0].start = MX35_OTG_BASE_ADDR; otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; otg_resources[1].start = MXC_INT_USBOTG; @@ -652,6 +831,7 @@ static int __init mx3_devices_init(void) imx_ssi_resources1[1].end = MX35_INT_SSI2; imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; + mx3_usb_otg_addr = MX35_OTG_BASE_ADDR; } return 0; diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 2c3c8646a29e..479f6efbf62b 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -6,6 +6,8 @@ extern struct platform_device mxc_uart_device3; extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_w1_master_device; extern struct platform_device mxc_nand_device; +extern struct platform_device mxc_nandv2_device; +extern struct platform_device mxc_nor_mtd_device; extern struct platform_device mxc_i2c_device0; extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device2; @@ -15,6 +17,7 @@ extern struct platform_device mx3_camera; extern struct platform_device mxc_fec_device; extern struct platform_device mxcsdhc_device0; extern struct platform_device mxcsdhc_device1; +extern struct platform_device mxc_pseudo_irq_device; extern struct platform_device mxc_otg_udc_device; extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; @@ -23,6 +26,7 @@ extern struct platform_device mxc_rnga_device; extern struct platform_device mxc_spi_device0; extern struct platform_device mxc_spi_device1; extern struct platform_device mxc_spi_device2; +extern struct platform_device mxc_dma_device; extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; extern struct platform_device imx_ssi_device1; diff --git a/arch/arm/mach-mx3/dma.c b/arch/arm/mach-mx3/dma.c new file mode 100644 index 000000000000..115832d8fc72 --- /dev/null +++ b/arch/arm/mach-mx3/dma.c @@ -0,0 +1,1270 @@ +/* + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include +#include +#include +#include +#include + +#define MXC_MMC_BUFFER_ACCESS 0x38 +#define MXC_SSI_TX0_REG 0x0 +#define MXC_SSI_TX1_REG 0x4 +#define MXC_SSI_RX0_REG 0x8 +#define MXC_SSI_RX1_REG 0xC +#define MXC_FIRI_TXFIFO 0x14 +#define MXC_SDHC_MMC_WML 16 +#define MXC_SDHC_SD_WML 64 +#define MXC_SSI_TXFIFO_WML 0x4 +#define MXC_SSI_RXFIFO_WML 0x6 +#define MXC_FIRI_WML 16 +#define MXC_SPDIF_TXFIFO_WML 8 +#define MXC_SPDIF_RXFIFO_WML 8 +#define MXC_SPDIF_TX_REG 0x2C +#define MXC_SPDIF_RX_REG 0x14 +#define MXC_ASRC_FIFO_WML 0x40 +#define MXC_ASRCA_RX_REG 0x60 +#define MXC_ASRCA_TX_REG 0x64 +#define MXC_ASRCB_RX_REG 0x68 +#define MXC_ASRCB_TX_REG 0x6C +#define MXC_ASRCC_RX_REG 0x70 +#define MXC_ASRCC_TX_REG 0x74 +#define MXC_ESAI_TX_REG 0x00 +#define MXC_ESAI_RX_REG 0x04 +#define MXC_ESAI_FIFO_WML 0x40 +#define MXC_UARTUTXD 0x40 +#define UART_UFCR_RXTL 16 +#define UART_UFCR_TXTL 16 + +#ifdef CONFIG_SDMA_IRAM +#define trans_type int_2_per +#define MXC_DMA_CHANNEL_IRAM 30 +#define MXC_DMA_CHANNEL_SSI1_TX (MXC_DMA_CHANNEL_IRAM + 1) +#define MXC_DMA_CHANNEL_SSI2_TX (MXC_DMA_CHANNEL_IRAM + 1) +#else +#define trans_type emi_2_per +#define MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL +#endif + +struct mxc_sdma_info_entry_s { + mxc_dma_device_t device; + void *chnl_info; +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_RXTL, + .per_address = MX3x_UART1_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_UART1_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_TXTL, + .per_address = MX3x_UART1_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_UART1_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_RXTL, + .per_address = MX3x_UART2_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_UART2_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_TXTL, + .per_address = MX3x_UART2_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_UART2_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_RXTL, + .per_address = MX3x_UART3_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = MX31_DMA_REQ_UART3_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_TXTL, + .per_address = MX3x_UART3_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = MX31_DMA_REQ_UART3_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_rx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_RXTL, + .per_address = MX31_UART4_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = MX31_DMA_REQ_UART4_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_tx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_TXTL, + .per_address = MX31_UART4_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = MX31_DMA_REQ_UART4_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_rx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_RXTL, + .per_address = MX31_UART5_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = MX31_DMA_REQ_UART5_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_tx_params = { + .chnl_params = { + .watermark_level = UART_UFCR_TXTL, + .per_address = MX31_UART5_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = MX31_DMA_REQ_UART5_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MX31_MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = MX31_DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MX31_MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = MX31_DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MX31_MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = MX31_DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MX31_MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = MX31_DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = MX3x_DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = MX3x_DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = MX3x_DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = MX3x_DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = trans_type, + .event_id = MX3x_DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = MX3x_SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_fir_rx_params = { + .chnl_params = { + .watermark_level = MXC_FIRI_WML, + .per_address = MX31_FIRI_BASE_ADDR, + .peripheral_type = FIRI, + .transfer_type = per_2_emi, + .event_id = MX31_DMA_REQ_FIRI_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_fir_tx_params = { + .chnl_params = { + .watermark_level = MXC_FIRI_WML, + .per_address = MX31_FIRI_BASE_ADDR + MXC_FIRI_TXFIFO, + .peripheral_type = FIRI, + .transfer_type = emi_2_per, + .event_id = MX31_DMA_REQ_FIRI_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = MX35_SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = MX35_DMA_REQ_SPDIF_TX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = MX35_SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = MX35_DMA_REQ_SPDIF_TX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_RXFIFO_WML, + .per_address = MX35_SPDIF_BASE_ADDR + MXC_SPDIF_RX_REG, + .peripheral_type = SPDIF, + .transfer_type = per_2_emi, + .event_id = MX35_DMA_REQ_SPDIF_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_memory_params = { + .chnl_params = { + .peripheral_type = MEMORY, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrca_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = MX35_ASRC_BASE_ADDR + MXC_ASRCA_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = MX35_DMA_REQ_ASRC_DMA1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrca_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = MX35_ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = MX35_DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcb_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = MX35_ASRC_BASE_ADDR + MXC_ASRCB_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = MX35_DMA_REQ_ASRC_DMA2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcb_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = MX35_ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = MX35_DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcc_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML * 3, + .per_address = MX35_ASRC_BASE_ADDR + MXC_ASRCC_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = MX35_DMA_REQ_ASRC_DMA3, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcc_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML * 3, + .per_address = MX35_ASRC_BASE_ADDR + MXC_ASRCC_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = MX35_DMA_REQ_ASRC_DMA6, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX3x_SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX1, + .event_id2 = MX35_DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX3x_SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX2, + .event_id2 = MX35_DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX3x_SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX3x_DMA_REQ_SSI2_TX1, + .event_id2 = MX35_DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX3x_SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX3x_DMA_REQ_SSI2_TX2, + .event_id2 = MX35_DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX3x_SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX1, + .event_id2 = MX35_DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX3x_SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX3x_DMA_REQ_SSI1_TX2, + .event_id2 = MX35_DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX3x_SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX3x_DMA_REQ_SSI2_TX1, + .event_id2 = MX35_DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX3x_SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX3x_DMA_REQ_SSI2_TX2, + .event_id2 = MX35_DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX35_ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX35_DMA_REQ_ESAI_TX, + .event_id2 = MX35_DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ESAI_FIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX35_ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX35_DMA_REQ_ESAI_TX, + .event_id2 = MX35_DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ESAI_FIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcc_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + MX35_ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = MX35_DMA_REQ_ESAI_TX, + .event_id2 = MX35_DMA_REQ_ASRC_DMA6, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ASRC_FIFO_WML, + .per_address2 = + MX35_ASRC_BASE_ADDR + MXC_ASRCC_TX_REG, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = MX35_ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = MX35_DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = MX35_ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = trans_type, + .event_id = MX35_DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = MX35_ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = MX35_DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = MX35_ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = trans_type, + .event_id = MX35_DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_fifo_memory_params = { + .chnl_params = { + .peripheral_type = FIFO_MEMORY, + .per_address = MXC_FIFO_MEM_DEST_FIXED, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .event_id = 0, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_rx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = MX3x_ATA_DMA_BASE_ADDR, + .peripheral_type = ATA, + .transfer_type = per_2_emi, + .event_id = MX3x_DMA_REQ_ATA_TX_END, + .event_id2 = MX3x_DMA_REQ_ATA_RX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_tx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = MX3x_ATA_DMA_BASE_ADDR + 0x18, + .peripheral_type = ATA, + .transfer_type = emi_2_per, + .event_id = MX3x_DMA_REQ_ATA_TX_END, + .event_id2 = MX3x_DMA_REQ_ATA_TX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_DYNAMIC_CHANNEL, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static struct mxc_sdma_info_entry_s mxc_sdma_active_dma_info[] = { + {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params}, + {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params}, + {MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params}, + {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params}, + {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params}, + {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params}, + {MXC_DMA_UART4_RX, &mxc_sdma_uart4_rx_params}, + {MXC_DMA_UART4_TX, &mxc_sdma_uart4_tx_params}, + {MXC_DMA_UART5_RX, &mxc_sdma_uart5_rx_params}, + {MXC_DMA_UART5_TX, &mxc_sdma_uart5_tx_params}, + {MXC_DMA_MMC1_WIDTH_1, &mxc_sdma_mmc1_width1_params}, + {MXC_DMA_MMC1_WIDTH_4, &mxc_sdma_mmc1_width4_params}, + {MXC_DMA_MMC2_WIDTH_1, &mxc_sdma_mmc2_width1_params}, + {MXC_DMA_MMC2_WIDTH_4, &mxc_sdma_mmc2_width4_params}, + {MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params}, + {MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params}, + {MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params}, + {MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params}, + {MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params}, + {MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params}, + {MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params}, + {MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params}, + {MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params}, + {MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params}, + {MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params}, + {MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params}, + {MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params}, + {MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params}, + {MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params}, + {MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params}, + {MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params}, + {MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params}, + {MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params}, + {MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params}, + {MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params}, + {MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params}, + {MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params}, + {MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params}, + {MXC_DMA_FIR_RX, &mxc_sdma_fir_rx_params}, + {MXC_DMA_FIR_TX, &mxc_sdma_fir_tx_params}, + {MXC_DMA_MEMORY, &mxc_sdma_memory_params}, + {MXC_DMA_FIFO_MEMORY, &mxc_sdma_fifo_memory_params}, + {MXC_DMA_ATA_RX, &mxc_sdma_ata_rx_params}, + {MXC_DMA_ATA_TX, &mxc_sdma_ata_tx_params}, + {MXC_DMA_SPDIF_16BIT_TX, &mxc_sdma_spdif_16bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_TX, &mxc_sdma_spdif_32bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_RX, &mxc_sdma_spdif_32bit_rx_params}, + {MXC_DMA_ASRC_A_RX, &mxc_sdma_asrca_rx_params}, + {MXC_DMA_ASRC_A_TX, &mxc_sdma_asrca_tx_params}, + {MXC_DMA_ASRC_B_RX, &mxc_sdma_asrcb_rx_params}, + {MXC_DMA_ASRC_B_TX, &mxc_sdma_asrcb_tx_params}, + {MXC_DMA_ASRC_C_RX, &mxc_sdma_asrcc_rx_params}, + {MXC_DMA_ASRC_C_TX, &mxc_sdma_asrcc_tx_params}, + {MXC_DMA_ASRCA_SSI1_TX0, &mxc_sdma_asrca_ssi1_tx0_params}, + {MXC_DMA_ASRCA_SSI1_TX1, &mxc_sdma_asrca_ssi1_tx1_params}, + {MXC_DMA_ASRCA_SSI2_TX0, &mxc_sdma_asrca_ssi2_tx0_params}, + {MXC_DMA_ASRCA_SSI2_TX1, &mxc_sdma_asrca_ssi2_tx1_params}, + {MXC_DMA_ASRCB_SSI1_TX0, &mxc_sdma_asrcb_ssi1_tx0_params}, + {MXC_DMA_ASRCB_SSI1_TX1, &mxc_sdma_asrcb_ssi1_tx1_params}, + {MXC_DMA_ASRCB_SSI2_TX0, &mxc_sdma_asrcb_ssi2_tx0_params}, + {MXC_DMA_ASRCB_SSI2_TX1, &mxc_sdma_asrcb_ssi2_tx1_params}, + {MXC_DMA_ASRCA_ESAI, &mxc_sdma_asrca_esai_params}, + {MXC_DMA_ASRCB_ESAI, &mxc_sdma_asrcb_esai_params}, + {MXC_DMA_ASRCC_ESAI, &mxc_sdma_asrcc_esai_params}, + {MXC_DMA_ESAI_16BIT_RX, &mxc_sdma_esai_16bit_rx_params}, + {MXC_DMA_ESAI_16BIT_TX, &mxc_sdma_esai_16bit_tx_params}, + {MXC_DMA_ESAI_24BIT_RX, &mxc_sdma_esai_24bit_rx_params}, + {MXC_DMA_ESAI_24BIT_TX, &mxc_sdma_esai_24bit_tx_params}, +}; + +static int mxc_sdma_info_entrys = + sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]); + +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id) +{ + struct mxc_sdma_info_entry_s *p = mxc_sdma_active_dma_info; + int i; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + if (p->device == channel_id) + return p->chnl_info; + + } + return NULL; +} +EXPORT_SYMBOL(mxc_sdma_get_channel_params); + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t *chnl) +{ +#ifdef CONFIG_SDMA_IRAM + int i; + for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++) + chnl[i].dynamic = 0; +#endif /*CONFIG_SDMA_IRAM */ +} +EXPORT_SYMBOL(mxc_get_static_channels); diff --git a/arch/arm/mach-mx3/dptc.c b/arch/arm/mach-mx3/dptc.c new file mode 100644 index 000000000000..14efcbda550f --- /dev/null +++ b/arch/arm/mach-mx3/dptc.c @@ -0,0 +1,103 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dptc.c + * + * @brief DPTC table for the Freescale Semiconductor MXC DPTC module. + * + * @ingroup PM + */ + +#include +#include + +struct dptc_wp dptc_wp_allfreq_26ckih[DPTC_WP_SUPPORTED] = { + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 dcvr3 voltage */ + /* wp0 */ + {0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000, 1625}, + {0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0, 1600}, + {0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0, 1575}, + {0xffc00000, 0x95e3e8e8, 0xffc00000, 0xe5f70da4, 1550}, + {0xffc00000, 0x9623f8e8, 0xffc00000, 0xe6371da8, 1525}, + /* wp5 */ + {0xffc00000, 0x966408f0, 0xffc00000, 0xe6b73db0, 1500}, + {0xffc00000, 0x96e428f4, 0xffc00000, 0xe7776dbc, 1475}, + {0xffc00000, 0x976448fc, 0xffc00000, 0xe8379dc8, 1450}, + {0xffc00000, 0x97e46904, 0xffc00000, 0xe977ddd8, 1425}, + {0xffc00000, 0x98a48910, 0xffc00000, 0xeab81de8, 1400}, + /* wp10 */ + {0xffc00000, 0x9964b918, 0xffc00000, 0xebf86df8, 1375}, + {0xffc00000, 0xffe4e924, 0xffc00000, 0xfff8ae08, 1350}, + {0xffc00000, 0xffe5192c, 0xffc00000, 0xfff8fe1c, 1350}, + {0xffc00000, 0xffe54938, 0xffc00000, 0xfff95e2c, 1350}, + {0xffc00000, 0xffe57944, 0xffc00000, 0xfff9ae44, 1350}, + /* wp15 */ + {0xffc00000, 0xffe5b954, 0xffc00000, 0xfffa0e58, 1350}, + {0xffc00000, 0xffe5e960, 0xffc00000, 0xfffa6e70, 1350}, +}; + +struct dptc_wp dptc_wp_allfreq_26ckih_TO_2_0[DPTC_WP_SUPPORTED] = { + /* Mx31 TO 2.0 Offset table */ + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 dcvr3 voltage */ + /* wp0 */ + {0xffc00000, 0x9E265978, 0xffc00000, 0xE4371D9C, 1625}, + {0xffc00000, 0x9E665978, 0xffc00000, 0xE4772D9C, 1600}, + {0xffc00000, 0x9EA65978, 0xffc00000, 0xE4772DA0, 1575}, + {0xffc00000, 0x9EE66978, 0xffc00000, 0xE4B73DA0, 1550}, + {0xffc00000, 0x9F26697C, 0xffc00000, 0xE4F73DA0, 1525}, + /* wp5 */ + {0xffc00000, 0x9F66797C, 0xffc00000, 0xE5774DA4, 1500}, + {0xffc00000, 0x9FE6797C, 0xffc00000, 0xE5F75DA4, 1475}, + {0xffc00000, 0xA026897C, 0xffc00000, 0xE6776DA4, 1450}, + {0xffc00000, 0xA0A6897C, 0xffc00000, 0xE6F77DA8, 1425}, + {0xffc00000, 0xA0E69980, 0xffc00000, 0xE7B78DAC, 1400}, + /* wp10 */ + {0xffc00000, 0xA1669980, 0xffc00000, 0xE8379DAC, 1375}, + {0xffc00000, 0xA1A6A980, 0xffc00000, 0xE8F7ADB0, 1350}, + {0xffc00000, 0xA226B984, 0xffc00000, 0xE9F7CDB0, 1325}, + {0xffc00000, 0xA2A6C984, 0xffc00000, 0xEAB7DDB4, 1300}, + {0xffc00000, 0xA326C988, 0xffc00000, 0xEBB7FDB8, 1275}, + /* wp15 */ + {0xffc00000, 0xA3A6D988, 0xffc00000, 0xECB80DBC, 1250}, + {0xffc00000, 0xA426E988, 0xffc00000, 0xEDB82DC0, 1225}, +}; + +struct dptc_wp dptc_wp_allfreq_27ckih_TO_2_0[DPTC_WP_SUPPORTED] = { + /* Mx31 TO 2.0 Offset table */ + /* 532MHz */ + /* dcvr0 dcvr1 dcvr2 dcvr3 voltage */ + /* wp0 */ + {0xffc00000, 0x9864E920, 0xffc00000, 0xDBB50D1C, 1625}, + {0xffc00000, 0x98A4E920, 0xffc00000, 0xDBF51D1C, 1600}, + {0xffc00000, 0x98E4E920, 0xffc00000, 0xDBF51D20, 1575}, + {0xffc00000, 0x9924F920, 0xffc00000, 0xDC352D20, 1550}, + {0xffc00000, 0x9924F924, 0xffc00000, 0xDC752D20, 1525}, + /* wp5 */ + {0xffc00000, 0x99650924, 0xffc00000, 0xDCF53D24, 1500}, + {0xffc00000, 0x99E50924, 0xffc00000, 0xDD754D24, 1475}, + {0xffc00000, 0x9A251924, 0xffc00000, 0xDDF55D24, 1450}, + {0xffc00000, 0x9AA51924, 0xffc00000, 0xDE756D28, 1425}, + {0xffc00000, 0x9AE52928, 0xffc00000, 0xDF357D2C, 1400}, + /* wp10 */ + {0xffc00000, 0x9B652928, 0xffc00000, 0xDFB58D2C, 1375}, + {0xffc00000, 0x9BA53928, 0xffc00000, 0xE0759D30, 1350}, + {0xffc00000, 0x9C254928, 0xffc00000, 0xE135BD30, 1325}, + {0xffc00000, 0x9CA55928, 0xffc00000, 0xE1F5CD34, 1300}, + {0xffc00000, 0x9D25592C, 0xffc00000, 0xE2F5ED38, 1275}, + /* wp15 */ + {0xffc00000, 0x9DA5692C, 0xffc00000, 0xE3F5FD38, 1250}, + {0xffc00000, 0x9E25792C, 0xffc00000, 0xE4F61D3C, 1225}, +}; diff --git a/arch/arm/mach-mx3/dummy_gpio.c b/arch/arm/mach-mx3/dummy_gpio.c new file mode 100644 index 000000000000..6766cdf43911 --- /dev/null +++ b/arch/arm/mach-mx3/dummy_gpio.c @@ -0,0 +1,119 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +void gpio_uart_active(int port, int no_irda) {} +EXPORT_SYMBOL(gpio_uart_active); + +void gpio_uart_inactive(int port, int no_irda) {} +EXPORT_SYMBOL(gpio_uart_inactive); + +void gpio_gps_active(void) {} +EXPORT_SYMBOL(gpio_gps_active); + +void gpio_gps_inactive(void) {} +EXPORT_SYMBOL(gpio_gps_inactive); + +void config_uartdma_event(int port) {} +EXPORT_SYMBOL(config_uartdma_event); + +void gpio_spi_active(int cspi_mod) {} +EXPORT_SYMBOL(gpio_spi_active); + +void gpio_spi_inactive(int cspi_mod) {} +EXPORT_SYMBOL(gpio_spi_inactive); + +void gpio_owire_active(void) {} +EXPORT_SYMBOL(gpio_owire_active); + +void gpio_owire_inactive(void) {} +EXPORT_SYMBOL(gpio_owire_inactive); + +void gpio_i2c_active(int i2c_num) {} +EXPORT_SYMBOL(gpio_i2c_active); + +void gpio_i2c_inactive(int i2c_num) {} +EXPORT_SYMBOL(gpio_i2c_inactive); + +void gpio_i2c_hs_active(void) {} +EXPORT_SYMBOL(gpio_i2c_hs_active); + +void gpio_i2c_hs_inactive(void) {} +EXPORT_SYMBOL(gpio_i2c_hs_inactive); + +void gpio_pmic_active(void) {} +EXPORT_SYMBOL(gpio_pmic_active); + +void gpio_activate_audio_ports(void) {} +EXPORT_SYMBOL(gpio_activate_audio_ports); + +void gpio_sdhc_active(int module) {} +EXPORT_SYMBOL(gpio_sdhc_active); + +void gpio_sdhc_inactive(int module) {} +EXPORT_SYMBOL(gpio_sdhc_inactive); + +void gpio_sensor_select(int sensor) {} + +void gpio_sensor_active(unsigned int csi) {} +EXPORT_SYMBOL(gpio_sensor_active); + +void gpio_sensor_inactive(unsigned int csi) {} +EXPORT_SYMBOL(gpio_sensor_inactive); + +void gpio_ata_active(void) {} +EXPORT_SYMBOL(gpio_ata_active); + +void gpio_ata_inactive(void) {} +EXPORT_SYMBOL(gpio_ata_inactive); + +void gpio_nand_active(void) {} +EXPORT_SYMBOL(gpio_nand_active); + +void gpio_nand_inactive(void) {} +EXPORT_SYMBOL(gpio_nand_inactive); + +void gpio_keypad_active(void) {} +EXPORT_SYMBOL(gpio_keypad_active); + +void gpio_keypad_inactive(void) {} +EXPORT_SYMBOL(gpio_keypad_inactive); + +int gpio_usbotg_hs_active(void) +{ + return 0; +} +EXPORT_SYMBOL(gpio_usbotg_hs_active); + +void gpio_usbotg_hs_inactive(void) {} +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); + +void gpio_fec_active(void) {} +EXPORT_SYMBOL(gpio_fec_active); + +void gpio_fec_inactive(void) {} +EXPORT_SYMBOL(gpio_fec_inactive); + +void gpio_spdif_active(void) {} +EXPORT_SYMBOL(gpio_spdif_active); + +void gpio_spdif_inactive(void) {} +EXPORT_SYMBOL(gpio_spdif_inactive); + +void gpio_mlb_active(void) {} +EXPORT_SYMBOL(gpio_mlb_active); + +void gpio_mlb_inactive(void) {} +EXPORT_SYMBOL(gpio_mlb_inactive); diff --git a/arch/arm/mach-mx3/dvfs-imx35.c b/arch/arm/mach-mx3/dvfs-imx35.c new file mode 100644 index 000000000000..6ab210b3ff61 --- /dev/null +++ b/arch/arm/mach-mx3/dvfs-imx35.c @@ -0,0 +1,609 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file dvfs.c + * + * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module. + * + * Upon initialization, the DVFS driver initializes the DVFS hardware + * sets up driver nodes attaches to the DVFS interrupt and initializes internal + * data structures. When the DVFS interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and + * changes the CPU voltage according to translation table that is loaded into + * the driver. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/* + * The frequency of div_3_clk will affect the dvfs sample rate.. + */ +#define DVFS_DIV3CK (3 << MXC_CCM_LTR0_DIV3CK_OFFSET) + +/* + * Panic threshold. Panic frequency change request + * will be sent if DVFS counter value will be more than this value. + */ +#define DVFS_PNCTHR (63 << MXC_CCM_LTR1_PNCTHR_OFFSET) + +/* + * Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add + */ +#define DVFS_LTBRSR (1 << MXC_CCM_LTR1_LTBRSR_OFFSET) + +/* EMAC defines how many samples are included in EMA calculation */ +#define DVFS_EMAC (0x20 << MXC_CCM_LTR2_EMAC_OFFSET) + +/* + * Frequency increase threshold. Increase frequency change request + * will be sent if DVFS counter value will be more than this value. + */ +#define DVFS_UPTHR(val) (val << MXC_CCM_LTR0_UPTHR_OFFSET) + +/* + * Frequency decrease threshold. Decrease frequency change request + * will be sent if DVFS counter value will be less than this value. + */ +#define DVFS_DNTHR(val) (val << MXC_CCM_LTR0_DNTHR_OFFSET) + +/* + * DNCNT defines the amount of times the down threshold should be exceeded + * before DVFS will trigger frequency decrease request. + */ +#define DVFS_DNCNT(val) (val << MXC_CCM_LTR1_DNCNT_OFFSET) + +/* + * UPCNT defines the amount of times the up threshold should be exceeded + * before DVFS will trigger frequency increase request. + */ +#define DVFS_UPCNT(val) (val << MXC_CCM_LTR1_UPCNT_OFFSET) + +#define DVFS_DVSUP(val) (val << MXC_CCM_PMCR0_DVSUP_OFFSET) + +#define MXC_DVFS_MAX_WP_NUM 2 + +enum { + FSVAI_FREQ_NOCHANGE = 0x0, + FSVAI_FREQ_INCREASE, + FSVAI_FREQ_DECREASE, + FSVAI_FREQ_EMERG, +}; + +struct dvfs_wp { + unsigned long cpu_rate; + u32 core_voltage; + u32 dvsup; + u32 dnthr; + u32 upthr; + u32 dncnt; + u32 upcnt; +}; + +/* the default working points for MX35 TO2 DVFS. */ +static struct dvfs_wp dvfs_wp_tbl[MXC_DVFS_MAX_WP_NUM] = { + {399000000, 1200000, DVFS_DVSUP(DVSUP_LOW), DVFS_DNTHR(18), + DVFS_UPTHR(31), DVFS_DNCNT(0x33), + DVFS_UPCNT(0x33)}, +/* TBD: Need to set default voltage according to published data sheet */ + {532000000, 1350000, DVFS_DVSUP(DVSUP_TURBO), DVFS_DNTHR(18), + DVFS_UPTHR(30), DVFS_DNCNT(0x33), + DVFS_UPCNT(0x33)} +}; + +static u8 dvfs_wp_num = MXC_DVFS_MAX_WP_NUM; + + /* Used for tracking the number of interrupts */ +static u32 dvfs_nr_up[MXC_DVFS_MAX_WP_NUM]; +static u32 dvfs_nr_dn[MXC_DVFS_MAX_WP_NUM]; +static unsigned long stored_cpu_rate; /* cpu rate before DVFS starts */ +static u32 stored_pmcr0; +static int dvfs_is_active; /* indicate DVFS is active or not */ + +static struct delayed_work dvfs_work; + +/* + * Clock structures + */ +static struct clk *cpu_clk; +static struct regulator *core_reg; + +const static u8 ltr_gp_weight[] = { + 0, /* 0 */ + 0, + 0, + 0, + 0, + 0, /* 5 */ + 0, + 0, + 0, + 0, + 0, /* 10 */ + 0, + 0, + 0, + 0, + 0, /* 15 */ +}; + +DEFINE_SPINLOCK(mxc_dvfs_lock); + +/*! + * This function sets the weight of general purpose signals + * @param gp_id number of general purpose bit + * @param weight the weight of the general purpose bit + */ +static void set_gp_weight(int gp_id, u8 weight) +{ + u32 reg; + + if (gp_id < 9) { + reg = __raw_readl(MXC_CCM_LTR3); + reg = (reg & ~(MXC_CCM_LTR3_WSW_MASK(gp_id))) | + (weight << MXC_CCM_LTR3_WSW_OFFSET(gp_id)); + __raw_writel(reg, MXC_CCM_LTR3); + } else if (gp_id < 16) { + reg = __raw_readl(MXC_CCM_LTR2); + reg = (reg & ~(MXC_CCM_LTR2_WSW_MASK(gp_id))) | + (weight << MXC_CCM_LTR2_WSW_OFFSET(gp_id)); + __raw_writel(reg, MXC_CCM_LTR2); + } +} + +/*! + * This function sets upper threshold, lower threshold, + * up-counter, down-counter for load tracking. + * @param upthr upper threshold + * @param dnthr lower threshold + * @param upcnt up counter + * @param dncnt down counter + */ +static void set_ltr_thres_counter(u32 upthr, u32 dnthr, u32 upcnt, u32 dncnt) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_LTR0); + reg = + (reg & + ~(MXC_CCM_LTR0_UPTHR_MASK | + MXC_CCM_LTR0_DNTHR_MASK)) | upthr | dnthr; + __raw_writel(reg, MXC_CCM_LTR0); + + reg = __raw_readl(MXC_CCM_LTR1); + reg = + (reg & + ~(MXC_CCM_LTR1_UPCNT_MASK | + MXC_CCM_LTR1_DNCNT_MASK)) | upcnt | dncnt; + __raw_writel(reg, MXC_CCM_LTR1); +} + +/*! + * This function is called for module initialization. + * It sets up the DVFS hardware. + * It sets default values for DVFS thresholds and counters. The default + * values was chosen from a set of different reasonable values. They was tested + * and the default values in the driver gave the best results. + * More work should be done to find optimal values. + * + * @return 0 if successful; non-zero otherwise. + * + */ +static int init_dvfs_controller(void) +{ + u32 i, reg; + + /* setup LTR0 */ + reg = __raw_readl(MXC_CCM_LTR0); + reg = (reg & ~(MXC_CCM_LTR0_DIV3CK_MASK)) | DVFS_DIV3CK; + __raw_writel(reg, MXC_CCM_LTR0); + + /* set up LTR1 */ + reg = __raw_readl(MXC_CCM_LTR1); + reg = (reg & ~(MXC_CCM_LTR1_PNCTHR_MASK | MXC_CCM_LTR1_LTBRSR_MASK)); + reg = reg | DVFS_PNCTHR | DVFS_LTBRSR; + __raw_writel(reg, MXC_CCM_LTR1); + + /* setup LTR2 */ + reg = __raw_readl(MXC_CCM_LTR2); + reg = (reg & ~(MXC_CCM_LTR2_EMAC_MASK)) | DVFS_EMAC; + __raw_writel(reg, MXC_CCM_LTR2); + + /* Set general purpose weights to 0 */ + for (i = 0; i < 16; i++) + set_gp_weight(i, ltr_gp_weight[i]); + + /* ARM interrupt, mask load buf full interrupt */ + reg = __raw_readl(MXC_CCM_PMCR0); + reg |= MXC_CCM_PMCR0_DVFIS | MXC_CCM_PMCR0_LBMI; + __raw_writel(reg, MXC_CCM_PMCR0); + + return 0; +} + +static void dvfs_workqueue_handler(struct work_struct *work) +{ + u32 pmcr0 = stored_pmcr0; + u32 fsvai = (pmcr0 & MXC_CCM_PMCR0_FSVAI_MASK) >> + MXC_CCM_PMCR0_FSVAI_OFFSET; + u32 dvsup = (pmcr0 & MXC_CCM_PMCR0_DVSUP_MASK) >> + MXC_CCM_PMCR0_DVSUP_OFFSET; + u32 curr_cpu; + u8 curr_dvfs; + + if (!dvfs_is_active) + return; + + if (fsvai == FSVAI_FREQ_NOCHANGE) { + /* Do nothing. Freq change is not required */ + printk(KERN_WARNING "fsvai should not be 0\n"); + goto exit; + } + + if (((dvsup == DVSUP_LOW) && (fsvai == FSVAI_FREQ_DECREASE)) || + ((dvsup == DVSUP_TURBO) && ((fsvai == FSVAI_FREQ_INCREASE) || + (fsvai == FSVAI_FREQ_EMERG)))) { + /* Interrupt should be disabled in these cases according to + * the spec since DVFS is already at lowest (highest) state */ + printk(KERN_WARNING "Something is wrong?\n"); + goto exit; + } + + /*Disable DPTC voltage update */ + pmcr0 = pmcr0 & ~MXC_CCM_PMCR0_DPVCR; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + curr_cpu = clk_get_rate(cpu_clk); + for (curr_dvfs = 0; curr_dvfs < dvfs_wp_num; curr_dvfs++) { + if (dvfs_wp_tbl[curr_dvfs].cpu_rate == curr_cpu) { + if (fsvai == FSVAI_FREQ_DECREASE) { + curr_dvfs--; + dvfs_nr_dn[dvsup]++; + /*reduce frequency and then voltage */ + clk_set_rate(cpu_clk, + dvfs_wp_tbl[curr_dvfs].cpu_rate); + regulator_set_voltage(core_reg, + dvfs_wp_tbl[curr_dvfs]. + core_voltage, + dvfs_wp_tbl[curr_dvfs]. + core_voltage); + pr_info("Decrease frequency to: %ld \n", + dvfs_wp_tbl[curr_dvfs].cpu_rate); + } else { + /*increase freq to the highest one */ + curr_dvfs = dvfs_wp_num - 1; + dvfs_nr_up[dvsup]++; + /*Increase voltage and then frequency */ + regulator_set_voltage(core_reg, + dvfs_wp_tbl[curr_dvfs]. + core_voltage, + dvfs_wp_tbl[curr_dvfs]. + core_voltage); + clk_set_rate(cpu_clk, + dvfs_wp_tbl[curr_dvfs].cpu_rate); + pr_info("Increase frequency to: %ld \n", + dvfs_wp_tbl[curr_dvfs].cpu_rate); + } + pmcr0 = (pmcr0 & ~MXC_CCM_PMCR0_DVSUP_MASK) + | (dvfs_wp_tbl[curr_dvfs].dvsup); + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + set_ltr_thres_counter(dvfs_wp_tbl[curr_dvfs].upthr, + dvfs_wp_tbl[curr_dvfs].dnthr, + dvfs_wp_tbl[curr_dvfs].upcnt, + dvfs_wp_tbl[curr_dvfs].dncnt); + break; + } + } + + exit: + /* unmask interrupt */ + pmcr0 = pmcr0 & ~MXC_CCM_PMCR0_FSVAIM; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + /*DVFS update finish */ + pmcr0 = (pmcr0 | MXC_CCM_PMCR0_DVFS_UPDATE_FINISH); + __raw_writel(pmcr0, MXC_CCM_PMCR0); +} + +static irqreturn_t dvfs_irq(int irq, void *dev_id) +{ + + u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); + + /* Config dvfs_start bit */ + pmcr0 = pmcr0 | MXC_CCM_PMCR0_DVFS_START; + /*Mask interrupt */ + pmcr0 = pmcr0 | MXC_CCM_PMCR0_FSVAIM; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + stored_pmcr0 = pmcr0; + schedule_delayed_work(&dvfs_work, 0); + + return IRQ_RETVAL(1); +} + +/*! + * This function enables the DVFS module. + */ +static int start_dvfs(void) +{ + u32 reg = 0; + unsigned long flags; + u8 i; + + if (dvfs_is_active) { + pr_info("DVFS is already started\n"); + return 0; + } + + spin_lock_irqsave(&mxc_dvfs_lock, flags); + + stored_cpu_rate = clk_get_rate(cpu_clk); + for (i = 0; i < dvfs_wp_num; i++) { + if (dvfs_wp_tbl[i].cpu_rate == stored_cpu_rate) { + /*Set LTR0 and LTR1 */ + set_ltr_thres_counter(dvfs_wp_tbl[i].upthr, + dvfs_wp_tbl[i].dnthr, + dvfs_wp_tbl[i].upcnt, + dvfs_wp_tbl[i].dncnt); + + reg = __raw_readl(MXC_CCM_PMCR0); + reg = + (reg & ~MXC_CCM_PMCR0_DVSUP_MASK) | (dvfs_wp_tbl[i]. + dvsup); + /* enable dvfs and interrupt */ + reg = + (reg & ~MXC_CCM_PMCR0_FSVAIM) | MXC_CCM_PMCR0_DVFEN; + + __raw_writel(reg, MXC_CCM_PMCR0); + + dvfs_is_active = 1; + pr_info("DVFS Starts\n"); + break; + } + } + + spin_unlock_irqrestore(&mxc_dvfs_lock, flags); + if (dvfs_is_active) + return 0; + else + return 1; +} + +/*! + * This function disables the DVFS module. + */ +static void stop_dvfs(void) +{ + u32 pmcr0; + unsigned long curr_cpu = clk_get_rate(cpu_clk); + u8 index; + + if (dvfs_is_active) { + + pmcr0 = __raw_readl(MXC_CCM_PMCR0); + /* disable dvfs and its interrupt */ + pmcr0 = (pmcr0 & ~MXC_CCM_PMCR0_DVFEN) | MXC_CCM_PMCR0_FSVAIM; + __raw_writel(pmcr0, MXC_CCM_PMCR0); + + if (stored_cpu_rate < curr_cpu) { + for (index = 0; index < dvfs_wp_num; index++) { + if (dvfs_wp_tbl[index].cpu_rate == + stored_cpu_rate) + break; + } + clk_set_rate(cpu_clk, stored_cpu_rate); + regulator_set_voltage(core_reg, + dvfs_wp_tbl[index].core_voltage, + dvfs_wp_tbl[index].core_voltage); + } else if (stored_cpu_rate > curr_cpu) { + for (index = 0; index < dvfs_wp_num; index++) { + if (dvfs_wp_tbl[index].cpu_rate == + stored_cpu_rate) + break; + } + regulator_set_voltage(core_reg, + dvfs_wp_tbl[index].core_voltage, + dvfs_wp_tbl[index].core_voltage); + clk_set_rate(cpu_clk, stored_cpu_rate); + } + + dvfs_is_active = 0; + } + + pr_info("DVFS is stopped\n"); +} + +static ssize_t dvfs_enable_store(struct sys_device *dev, + struct sysdev_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) { + if (start_dvfs() != 0) + printk(KERN_ERR "Failed to start DVFS\n"); + } else if (strstr(buf, "0") != NULL) { + stop_dvfs(); + } + + return size; +} + +static ssize_t dvfs_status_show(struct sys_device *dev, + struct sysdev_attribute *attr, + char *buf) +{ + int size = 0, i; + + if (dvfs_is_active) + size = sprintf(buf, "DVFS is enabled\n"); + else + size = sprintf(buf, "DVFS is disabled\n"); + + size += sprintf((buf + size), "UP:\t"); + for (i = 0; i < MXC_DVFS_MAX_WP_NUM; i++) + size += sprintf((buf + size), "%d\t", dvfs_nr_up[i]); + size += sprintf((buf + size), "\n"); + + size += sprintf((buf + size), "DOWN:\t"); + for (i = 0; i < MXC_DVFS_MAX_WP_NUM; i++) + size += sprintf((buf + size), "%d\t", dvfs_nr_dn[i]); + size += sprintf((buf + size), "\n"); + + return size; +} + +static ssize_t dvfs_status_store(struct sys_device *dev, + struct sysdev_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "reset") != NULL) { + int i; + for (i = 0; i < MXC_DVFS_MAX_WP_NUM; i++) { + dvfs_nr_up[i] = 0; + dvfs_nr_dn[i] = 0; + } + } + + return size; +} + +static SYSDEV_ATTR(enable, 0200, NULL, dvfs_enable_store); +static SYSDEV_ATTR(status, 0644, dvfs_status_show, dvfs_status_store); + +static struct sysdev_class dvfs_sysclass = { + .name = "dvfs", +}; + +static struct sys_device dvfs_device = { + .id = 0, + .cls = &dvfs_sysclass, +}; + +static int dvfs_sysdev_ctrl_init(void) +{ + int err; + + err = sysdev_class_register(&dvfs_sysclass); + if (!err) + err = sysdev_register(&dvfs_device); + if (!err) { + err = sysdev_create_file(&dvfs_device, &attr_enable); + err = sysdev_create_file(&dvfs_device, &attr_status); + } + + return err; +} + +static void dvfs_sysdev_ctrl_exit(void) +{ + sysdev_remove_file(&dvfs_device, &attr_enable); + sysdev_remove_file(&dvfs_device, &attr_status); + sysdev_unregister(&dvfs_device); + sysdev_class_unregister(&dvfs_sysclass); +} + +static int __init dvfs_init(void) +{ + int err = 0; + u8 index; + unsigned long curr_cpu; + + if (cpu_is_mx35_rev(CHIP_REV_1_0) == 1) { + /* + * Don't support DVFS for auto path in TO1 because + * the voltages under 399M are all 1.2v + */ + if (!(__raw_readl(MXC_CCM_PDR0) & MXC_CCM_PDR0_AUTO_CON)) { + pr_info("MX35 TO1 auto path, no need to use DVFS \n"); + return -1; + } + } + + cpu_clk = clk_get(NULL, "cpu_clk"); + curr_cpu = clk_get_rate(cpu_clk); + + if (board_is_rev(BOARD_REV_2)) + core_reg = regulator_get(NULL, "SW2"); + else + core_reg = regulator_get(NULL, "SW3"); + + dvfs_is_active = 0; + + /*Set voltage */ + for (index = 0; index < dvfs_wp_num; index++) { + if (dvfs_wp_tbl[index].cpu_rate == curr_cpu + && !IS_ERR(core_reg)) { + regulator_set_voltage(core_reg, + dvfs_wp_tbl[index].core_voltage, + dvfs_wp_tbl[index].core_voltage); + break; + } + } + + err = init_dvfs_controller(); + if (err) { + printk(KERN_ERR "DVFS: Unable to initialize DVFS"); + return err; + } + + INIT_DELAYED_WORK(&dvfs_work, dvfs_workqueue_handler); + + /* request the DVFS interrupt */ + err = request_irq(MXC_INT_DVFS, dvfs_irq, IRQF_DISABLED, "dvfs", NULL); + if (err) { + printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt"); + return err; + } + + err = dvfs_sysdev_ctrl_init(); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for dvfs"); + return err; + } + + return err; +} + +static void __exit dvfs_cleanup(void) +{ + stop_dvfs(); + + /* release the DVFS interrupt */ + free_irq(MXC_INT_DVFS, NULL); + + dvfs_sysdev_ctrl_exit(); + + clk_put(cpu_clk); + regulator_put(core_reg); +} + +module_init(dvfs_init); +module_exit(dvfs_cleanup); + +MODULE_AUTHOR("Freescale Seminconductor, Inc."); +MODULE_DESCRIPTION("DVFS driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx3/entry-pm.S b/arch/arm/mach-mx3/entry-pm.S new file mode 100644 index 000000000000..17ce8da9af70 --- /dev/null +++ b/arch/arm/mach-mx3/entry-pm.S @@ -0,0 +1,315 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/entry-pm.S + * + * @brief This file contains common pm entry . + * + * @ingroup MXC_PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WAIT_MODE 111 +#define DOZE_MODE 112 +#define STOP_MODE 113 +#define DSM_MODE 114 + +#define PM_XLOAD_SIZE 0x04 +#define PM_XLOAD_ENTRY 0x08 +#define PM_XLOAD_SUSPEND_MODE 0x0C +#define PM_XLOAD_CORE_SP 0x10 + +#define PROCINFO_PROC_FNS 36 +#define PROC_FIN_FN 12 +#define PROC_IDLE_FN 20 + +#ifdef CONFIG_FIQ +#define ARM_CONTEXT_SIZE 12 +#else +#define ARM_CONTEXT_SIZE 8 +#endif + +#ifdef CONFIG_PM_VERBOSE +resume_str: + .string "Resume from DSM..." + .size resume_str, . - resume_str + +.macro show_resume_str + ldr r0, =resume_str + bl printk +.endm + +#else +.macro show_resume_str +.endm +#endif + + .data + .align 3 +arm_core_context: + .rept ARM_CONTEXT_SIZE + .long 0 + .endr + +#ifdef CONFIG_VFP + .text + .align 5 +arm_vfp_save: + mov ip, sp + stmdb sp!, {r0-r8, fp, ip, lr, pc} + sub fp, ip, #4 + mov r1, #THREAD_SIZE + sub r1, r1, #1 + bic r0, sp, r1 + ldr r8, [r0, #TI_CPU] + add r4, r0, #TI_VFPSTATE + + ldr r3, =last_VFP_context + VFPFMRX r2, FPEXC + tst r2, #FPEXC_EN + bne 1f + + ldr r4, [r3, r8, lsl #2] + cmp r4, #0 + beq dead_vfp +1: + bic r1, r2, #FPEXC_EN + VFPFMXR FPEXC, r1 + /*TODO: SMP */ + VFPFSTMIA r4, r1 + VFPFMRX r5, FPSCR + tst r2, #FPEXC_EX + VFPFMRX r6, FPINST, NE + tstne r2, #FPEXC_FP2V + VFPFMRX r7, FPINST2, NE + stmia r4, {r2, r5, r6, r7} + + mov r1, #0 + str r1, [r3, r8, lsl #2] +dead_vfp: + ldmia sp, {r0-r8, fp, sp, pc} +#endif +/* + * The function just be called in this file + * Current r0 ~r4 are not saved. + * Otherwise, the working registers should be saved + */ + .text + .align 5 +arm_core_save: + mov ip, sp + stmdb sp!, {r8, r9, sl, fp, ip, lr, pc} + sub fp, ip, #4 + ldr r0, =arm_core_context + mov r3, r0 + /* SVC mode */ + mrs r1, spsr @Save spsr + mrs r2, cpsr @Save cpsr + stmia r0!, {r1, r2} + /* Abort mode */ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | ABT_MODE + stmia r0!, {sp} @Save stack pointer for abort mode + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | UND_MODE + stmia r0!, {sp} @Save stack pointer for undefine mode + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | IRQ_MODE + stmia r0!, {sp} @Save stack pointer for irq mode +#ifdef CONFIG_FIQ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | FIQ_MODE + /*Save general register and sp for fiq mode*/ + stmia r0!, {r8-r9, sl, fp, ip, sp} +#endif + ldr r0, [r3, #4] + msr cpsr_c, r0 + ldmia sp, {r8-r9, sl, fp, sp, pc} + +/* + * The function just be called in this file + * Current r0 ~r4 are not saved. + * Otherwise, the working registers should be saved + */ +arm_core_restore: + mov ip, sp + stmdb sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r0, =arm_core_context + mov r3, r0 + /* SVC mode */ + add r0, r0, #8 @skip svc mode + /* Abort mode */ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | ABT_MODE + ldmia r0!, {sp} @restore stack pointer for abort mode + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | UND_MODE + ldmia r0!, {sp} @restore stack pointer for undefine mode + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | IRQ_MODE + ldmia r0!, {sp} @restore stack pointer for irq mode +#ifdef CONFIG_FIQ + msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | FIQ_MODE + /*Save general register and sp for fiq mode*/ + ldmia r0!, {r8-r9, sl, fp, ip, sp} +#endif + ldmia r3!, {r1, r2} + msr cpsr, r2 @restore cpsr + msr spsr, r1 @restore spsr + ldmia sp, {fp, sp, pc} + +mxc_cp15_context: + .rept 16 + .long 0 + .endr + + .align 5 +mxc_cp15_restore: + /* Physical address */ + adr r0, mxc_cp15_context + ldmia r0, {r1-r9} +#ifndef CONFIG_PM_DEBUG + @Add dynamic check to skip this block when debug + sub lr, lr, #PHYS_OFFSET + add lr, lr, #PAGE_OFFSET +#endif + mcr p15, 0, r3, c1, c0, 2 @CP Access Register + mcr p15, 0, r2, c1, c0, 1 @Aux Control register + +#ifndef CONFIG_PM_DEBUG + mcr p15, 0, r0, c7, c5, 6 @flush BTAC/BTB + mcr p15, 0, r0, c7, c7, 0 @invalidate both caches + mcr p15, 0, r0, c8, c7, 0 @Inval TLBs +#endif + + mcr p15, 0, r4, c13, c0, 0 @PID + mcr p15, 0, r5, c13, c0, 1 @Context ID + + mcr p15, 0, r6, c3, c0, 0 @Domain Access Register + mcr p15, 0, r7, c2, c0, 0 @TTB0 + mcr p15, 0, r8, c2, c0, 1 @TTB1 + mcr p15, 0, r9, c2, c0, 2 @TTBC + + mcr p15, 0, r1, c1, c0, 0 @Control Register + /* mcu enabled */ + mrc p15, 0, r0, c2, c0, 0 + + mov pc, lr + nop + nop + nop + nop + nop + nop + nop + nop + +mxc_cp15_save: + mov ip, sp + stmdb sp!, {r8-r9, fp, ip, lr, pc} + sub fp, ip, #4 + ldr r0, =mxc_cp15_context +/* System Control Registers */ + mrc p15, 0, r1, c1, c0, 0 @Control Register + mrc p15, 0, r2, c1, c0, 1 @Aux Control Register + mrc p15, 0, r3, c1, c0, 2 @CP access Register + +/* Memory management Registers */ + mrc p15, 0, r4, c13, c0, 0 @PID + mrc p15, 0, r5, c13, c0, 1 @Context ID + + mrc p15, 0, r6, c3, c0, 0 @Domain Access Register + + mrc p15, 0, r7, c2, c0, 0 @TTB0 + mrc p15, 0, r8, c2, c0, 1 @TTB1 + mrc p15, 0, r9, c2, c0, 2 @TTBC + stmia r0, {r1-r9} + ldmia sp, {r8, r9, fp, sp, pc} + +/* + * int __mxc_pm_arch_entry(u32 entry, u32 size) + */ + .align 5 + .globl mxc_pm_arch_entry +mxc_pm_arch_entry: + mov ip, sp + stmdb sp!, {r4-r9, sl, fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + mov r8, r0 @save entry + mov r9, r1 @save entry size +#ifdef CONFIG_VFP + bl arm_vfp_save +#endif + /* r0 ~r3, ip is dirty*/ + bl arm_core_save @save arm context + bl mxc_cp15_save + mov r0, sp + mov r1, r8 @restore entry + mov r2, r9 @restore entry size + bl __mxc_pm_xload_setup +1: bl cpu_v6_proc_fin + bl cpu_v6_do_idle + nop + nop + nop + nop +__mxc_pm_arch_leave: + adr r0, __mxc_pm_xload_info + ldr sp, [r0, #PM_XLOAD_CORE_SP] + +#ifndef CONFIG_PM_DEBUG + sub sp, sp, #PAGE_OFFSET + add sp, sp, #PHYS_OFFSET +#endif + bl mxc_cp15_restore +#ifndef CONFIG_PM_DEBUG + sub sp, sp, #PHYS_OFFSET + add sp, sp, #PAGE_OFFSET +#endif + show_resume_str + bl arm_core_restore + ldmib sp, {r4-r9, sl, fp, sp, pc} + +__mxc_pm_xload_info: + adr pc, __mxc_pm_xload_entry @Jump instruction + .long __mxc_pm_xload_end - __mxc_pm_xload_info @loader size + .long (__mxc_pm_arch_leave - PAGE_OFFSET + PHYS_OFFSET) @resume entry + .long 0 @suspend state + .long 0 @Core Stack pointer +__mxc_pm_xload_entry: + adr r0, __mxc_pm_xload_info + ldr pc, [r0, #PM_XLOAD_ENTRY] +__mxc_pm_xload_end: + +/* + * __mxc_pm_xload_setup(u32 sp, u32 entry, u32 size) + * r0~r6 is dirty + */ +__mxc_pm_xload_setup: + ldr r3, =__mxc_pm_xload_info + str r0, [r3, #PM_XLOAD_CORE_SP] + ldr r4, [r3, #PM_XLOAD_SIZE] + cmp r2, r4 + blo 2f +1: ldr r5, [r3], #4 + str r5, [r1], #4 + subs r4, r4, #4 + bhi 1b + b 3f +2: str r3, [r1] +3: mov pc, lr diff --git a/arch/arm/mach-mx3/iomux.h b/arch/arm/mach-mx3/iomux.h new file mode 100644 index 000000000000..de2651edc29f --- /dev/null +++ b/arch/arm/mach-mx3/iomux.h @@ -0,0 +1,186 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX31_IOMUX_H__ +#define __MACH_MX31_IOMUX_H__ + +#include +#include +#include "mx31_pins.h" + +typedef unsigned int iomux_pin_name_t; +/*! + * @file mach-mx3/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX31 + */ + +/*! + * various IOMUX output functions + */ +typedef enum iomux_output_config { + OUTPUTCONFIG_GPIO = 0, /*!< used as GPIO */ + OUTPUTCONFIG_FUNC, /*!< used as function */ + OUTPUTCONFIG_ALT1, /*!< used as alternate function 1 */ + OUTPUTCONFIG_ALT2, /*!< used as alternate function 2 */ + OUTPUTCONFIG_ALT3, /*!< used as alternate function 3 */ + OUTPUTCONFIG_ALT4, /*!< used as alternate function 4 */ + OUTPUTCONFIG_ALT5, /*!< used as alternate function 5 */ + OUTPUTCONFIG_ALT6 /*!< used as alternate function 6 */ +} iomux_pin_ocfg_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUTCONFIG_NONE = 0, /*!< not configured for input */ + INPUTCONFIG_GPIO = 1 << 0, /*!< used as GPIO */ + INPUTCONFIG_FUNC = 1 << 1, /*!< used as function */ + INPUTCONFIG_ALT1 = 1 << 2, /*!< used as alternate function 1 */ + INPUTCONFIG_ALT2 = 1 << 3 /*!< used as alternate function 2 */ +} iomux_pin_icfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_NOLOOPBACK = 0x0 << 9, + PAD_CTL_LOOPBACK = 0x1 << 9, + PAD_CTL_PKE_NONE = 0x0 << 8, + PAD_CTL_PKE_ENABLE = 0x1 << 8, + PAD_CTL_PUE_KEEPER = 0x0 << 7, + PAD_CTL_PUE_PUD = 0x1 << 7, + PAD_CTL_100K_PD = 0x0 << 5, + PAD_CTL_100K_PU = 0x1 << 5, + PAD_CTL_47K_PU = 0x2 << 5, + PAD_CTL_22K_PU = 0x3 << 5, + PAD_CTL_HYS_CMOS = 0x0 << 4, + PAD_CTL_HYS_SCHMITZ = 0x1 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/*! + * various IOMUX general purpose functions + */ +typedef enum iomux_gp_func { + MUX_PGP_FIRI = 0x1 << 0, + MUX_DDR_MODE = 0x1 << 1, + MUX_PGP_CSPI_BB = 0x1 << 2, + MUX_PGP_ATA_1 = 0x1 << 3, + MUX_PGP_ATA_2 = 0x1 << 4, + MUX_PGP_ATA_3 = 0x1 << 5, + MUX_PGP_ATA_4 = 0x1 << 6, + MUX_PGP_ATA_5 = 0x1 << 7, + MUX_PGP_ATA_6 = 0x1 << 8, + MUX_PGP_ATA_7 = 0x1 << 9, + MUX_PGP_ATA_8 = 0x1 << 10, + MUX_PGP_UH2 = 0x1 << 11, + MUX_SDCTL_CSD0_SEL = 0x1 << 12, + MUX_SDCTL_CSD1_SEL = 0x1 << 13, + MUX_CSPI1_UART3 = 0x1 << 14, + MUX_EXTDMAREQ2_MBX_SEL = 0x1 << 15, + MUX_TAMPER_DETECT_EN = 0x1 << 16, + MUX_PGP_USB_4WIRE = 0x1 << 17, + MUX_PGB_USB_COMMON = 0x1 << 18, + MUX_SDHC_MEMSTICK1 = 0x1 << 19, + MUX_SDHC_MEMSTICK2 = 0x1 << 20, + MUX_PGP_SPLL_BYP = 0x1 << 21, + MUX_PGP_UPLL_BYP = 0x1 << 22, + MUX_PGP_MSHC1_CLK_SEL = 0x1 << 23, + MUX_PGP_MSHC2_CLK_SEL = 0x1 << 24, + MUX_CSPI3_UART5_SEL = 0x1 << 25, + MUX_PGP_ATA_9 = 0x1 << 26, + MUX_PGP_USB_SUSPEND = 0x1 << 27, + MUX_PGP_USB_OTG_LOOPBACK = 0x1 << 28, + MUX_PGP_USB_HS1_LOOPBACK = 0x1 << 29, + MUX_PGP_USB_HS2_LOOPBACK = 0x1 << 30, + MUX_CLKO_DDR_MODE = 0x1 << 31, +} iomux_gp_func_t; + +/*! + * This function is used to configure a pin through the IOMUX module. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + * @return 0 if successful; Non-zero otherwise + */ +int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pins + * @param config ORed value of elements defined in \b #iomux_pad_config_t + */ +void iomux_config_pad(iomux_pin_name_t pin, __u32 config); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void iomux_config_gpr(iomux_gp_func_t gp, bool en); + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param out an output function as defined in \b #iomux_pin_ocfg_t + * @param in an input function as defined in \b #iomux_pin_icfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_ocfg_t out, + iomux_pin_icfg_t in); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, bool en); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +#endif diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 58e57291b79d..d72022b5e455 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,13 +22,15 @@ #include #include #include -#include #include #include #include #include #include #include +#include +#include +#include #include #include @@ -40,9 +42,12 @@ #include #include #include +#include +#include #include #include #include "devices.h" +#include "crm_regs.h" /*! * @file mx31_3ds.c @@ -68,6 +73,26 @@ static int mx31_3ds_pins[] = { MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ /* MC13783 IRQ */ IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), + /* SDHC1 */ + MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD, + MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, + /* SDHC2 */ + MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, + MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, + MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, + MX31_PIN_GPIO1_2__GPIO1_2, + /* AUDMUX (4 & 5) */ + MX31_PIN_SCK4__SCK4, MX31_PIN_SRXD4__SRXD4, + MX31_PIN_STXD4__STXD4, MX31_PIN_SFS4__SFS4, + MX31_PIN_STXD5__STXD5, MX31_PIN_SRXD5__SRXD5, + MX31_PIN_SCK5__SCK5, MX31_PIN_SFS5__SFS5, + + MX31_PIN_LCS0__GPI03_23, + MX31_PIN_SRST0__GPIO3_2, + MX31_PIN_SIMPD0__GPIO2_3, + MX31_PIN_BATT_LINE__GPIO2_17, /* USB OTG reset */ IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), /* USB OTG */ @@ -114,6 +139,10 @@ static struct matrix_keymap_data mx31_3ds_keymap_data = { .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), }; +static struct mxc_audio_platform_data mxc_audio_data = { + .ssi_num = 1, +}; + /* Regulators */ static struct regulator_init_data pwgtx_init = { .constraints = { @@ -212,174 +241,56 @@ static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -/* - * Support for the SMSC9217 on the Debug board. - */ - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct resource smsc911x_resources[] = { - { - .start = LAN9217_BASE_ADDR, - .end = LAN9217_BASE_ADDR + 0xff, - .flags = IORESOURCE_MEM, - }, { - .start = EXPIO_INT_ENET, - .end = EXPIO_INT_ENET, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; - -/* - * Routines for the CPLD on the debug board. It contains a CPLD handling - * LEDs, switches, interrupts for Ethernet. - */ +#define PLL_PCTL_REG(pd, mfd, mfi, mfn) \ + ((((pd) - 1) << 26) + (((mfd) - 1) << 16) + ((mfi) << 10) + mfn) -static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc) -{ - uint32_t imr_val; - uint32_t int_valid; - uint32_t expio_irq; - - imr_val = __raw_readw(CPLD_INT_MASK_REG); - int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val; - - expio_irq = MXC_EXP_IO_BASE; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - generic_handle_irq(expio_irq); - } -} +/* For 26MHz input clock */ +#define PLL_532MHZ PLL_PCTL_REG(1, 13, 10, 3) +#define PLL_399MHZ PLL_PCTL_REG(1, 52, 7, 35) +#define PLL_133MHZ PLL_PCTL_REG(2, 26, 5, 3) -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * @param irq an expio virtual irq number - */ -static void expio_mask_irq(uint32_t irq) -{ - uint16_t reg; - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* mask the interrupt */ - reg = __raw_readw(CPLD_INT_MASK_REG); - reg |= 1 << expio; - __raw_writew(reg, CPLD_INT_MASK_REG); -} - -/* - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. - * @param irq an expanded io virtual irq number - */ -static void expio_ack_irq(uint32_t irq) -{ - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); +#define PDR0_REG(mcu, max, hsp, ipg, nfc) \ + (MXC_CCM_PDR0_MCU_DIV_##mcu | MXC_CCM_PDR0_MAX_DIV_##max | \ + MXC_CCM_PDR0_HSP_DIV_##hsp | MXC_CCM_PDR0_IPG_DIV_##ipg | \ + MXC_CCM_PDR0_NFC_DIV_##nfc) - /* clear the interrupt status */ - __raw_writew(1 << expio, CPLD_INT_RESET_REG); - __raw_writew(0, CPLD_INT_RESET_REG); - /* mask the interrupt */ - expio_mask_irq(irq); -} - -/* - * Enable a expio pin's interrupt by clearing the bit in the imr. - * @param irq a expio virtual irq number - */ -static void expio_unmask_irq(uint32_t irq) -{ - uint16_t reg; - uint32_t expio = MXC_IRQ_TO_EXPIO(irq); - - /* unmask the interrupt */ - reg = __raw_readw(CPLD_INT_MASK_REG); - reg &= ~(1 << expio); - __raw_writew(reg, CPLD_INT_MASK_REG); -} - -static struct irq_chip expio_irq_chip = { - .ack = expio_ack_irq, - .mask = expio_mask_irq, - .unmask = expio_unmask_irq, +/* working point(wp): 0 - 133MHz; 1 - 266MHz; 2 - 399MHz; 3 - 532MHz */ +/* 26MHz input clock table */ +static struct cpu_wp cpu_wp_26[] = { + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 133000000, + .pdr0_reg = PDR0_REG(4, 4, 4, 2, 6),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 266000000, + .pdr0_reg = PDR0_REG(2, 4, 4, 2, 6),}, + { + .pll_reg = PLL_399MHZ, + .pll_rate = 399000000, + .cpu_rate = 399000000, + .pdr0_reg = PDR0_REG(1, 3, 3, 2, 6),}, + { + .pll_reg = PLL_532MHZ, + .pll_rate = 532000000, + .cpu_rate = 532000000, + .pdr0_reg = PDR0_REG(1, 4, 4, 2, 6),}, }; -static int __init mx31_3ds_init_expio(void) +struct cpu_wp *get_cpu_wp(int *wp) { - int i; - int ret; - - /* Check if there's a debug board connected */ - if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) || - (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) || - (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) { - /* No Debug board found */ - return -ENODEV; - } - - pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n", - __raw_readw(CPLD_CODE_VER_REG)); - - /* - * Configure INT line as GPIO input - */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - /* Disable the interrupts and clear the status */ - __raw_writew(0, CPLD_INT_MASK_REG); - __raw_writew(0xFFFF, CPLD_INT_RESET_REG); - __raw_writew(0, CPLD_INT_RESET_REG); - __raw_writew(0x1F, CPLD_INT_MASK_REG); - for (i = MXC_EXP_IO_BASE; - i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); - i++) { - set_irq_chip(i, &expio_irq_chip); - set_irq_handler(i, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW); - set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler); - - return 0; + *wp = 4; + return cpu_wp_26; } -/* - * This structure defines the MX31 memory map. - */ -static struct map_desc mx31_3ds_io_desc[] __initdata = { - { - .virtual = MX31_CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), - .length = MX31_CS5_SIZE, - .type = MT_DEVICE, - }, -}; - /* * Set up static virtual mappings. */ static void __init mx31_3ds_map_io(void) { mx31_map_io(); - iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc)); } /*! @@ -387,6 +298,47 @@ static void __init mx31_3ds_map_io(void) */ static void __init mxc_board_init(void) { + struct clk *pll_clk; + struct clk *ckih_clk; + struct clk *cko_clk; + void __iomem *iim_reg = MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR); + + /* request gpio for phone jack detect */ + mxc_iomux_set_pad(MX31_PIN_BATT_LINE, PAD_CTL_PKE_NONE); + gpio_request(IOMUX_TO_GPIO(MX31_PIN_BATT_LINE), "batt_line"); + gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_BATT_LINE)); + + pll_clk = clk_get(NULL, "usb_pll"); + mxc_audio_data.ssi_clk[0] = clk_get(NULL, "ssi_clk.0"); + if (IS_ERR(pll_clk) || IS_ERR(mxc_audio_data.ssi_clk[0])) { + pr_err("cannot get usb pll or ssi clks\n"); + } else { + clk_set_parent(mxc_audio_data.ssi_clk[0], pll_clk); + clk_put(mxc_audio_data.ssi_clk[0]); + clk_put(pll_clk); + } + + /* override fuse for Hantro HW clock */ + if (__raw_readl(iim_reg + 0x808) == 0x4) { + if (!(__raw_readl(iim_reg + 0x800) & (1 << 5))) { + writel(__raw_readl(iim_reg + 0x808) & 0xfffffffb, + iim_reg + 0x808); + } + } + + /* Enable 26 mhz clock on CKO1 for PMIC audio */ + ckih_clk = clk_get(NULL, "ckih"); + cko_clk = clk_get(NULL, "cko1_clk"); + if (IS_ERR(ckih_clk) || IS_ERR(cko_clk)) { + printk(KERN_ERR "Unable to set CKO1 output to CKIH\n"); + } else { + clk_set_parent(cko_clk, ckih_clk); + clk_set_rate(cko_clk, clk_get_rate(ckih_clk)); + clk_enable(cko_clk); + } + clk_put(ckih_clk); + clk_put(cko_clk); + mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds"); @@ -402,8 +354,10 @@ static void __init mxc_board_init(void) mx31_3ds_usbotg_init(); mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); - if (!mx31_3ds_init_expio()) - platform_device_register(&smsc911x_device); + if (mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT)) + printk(KERN_WARNING "Init of the debugboard failed, all " + "devices on the board are unusable.\n"); + } static void __init mx31_3ds_timer_init(void) diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index b3d1a1895c20..4ebaa2628f3e 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2000 Deep Blue Solutions Ltd * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,6 +44,7 @@ #endif #include "devices.h" +#include "devices-imx31.h" /*! * @file mx31ads.c @@ -98,7 +99,7 @@ static inline int mxc_init_extuart(void) #endif #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -112,7 +113,7 @@ static unsigned int uart_pins[] = { static inline void mxc_init_imx_uart(void) { mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx31_add_imx_uart0(&uart_pdata); } #else /* !SERIAL_IMX */ static inline void mxc_init_imx_uart(void) @@ -467,7 +468,7 @@ static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { #endif }; -static void mxc_init_i2c(void) +static void __init mxc_init_i2c(void) { i2c_register_board_info(1, mx31ads_i2c1_devices, ARRAY_SIZE(mx31ads_i2c1_devices)); @@ -475,7 +476,7 @@ static void mxc_init_i2c(void) mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); - mxc_register_device(&mxc_i2c_device1, NULL); + imx31_add_imx_i2c1(NULL); } #else static void mxc_init_i2c(void) diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c new file mode 100644 index 000000000000..7bd140f86314 --- /dev/null +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -0,0 +1,433 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices-imx35.h" +#include "devices.h" +#include "crm_regs.h" + +/* + * Board specific pad setting. + */ +#define MX35_ESDHC1_CMD__PAD_CFG \ +( \ + PAD_CTL_PUE | \ + PAD_CTL_PKE | \ + PAD_CTL_HYS | \ + PAD_CTL_DSE_MAX | \ + PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SRE_FAST \ +) + +#define MX35_ESDHC1_CLK__PAD_CFG \ +( \ + PAD_CTL_PUE | \ + PAD_CTL_PKE | \ + PAD_CTL_DSE_MAX | \ + PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SRE_FAST \ +) + +#define MX35_ESDHC1_DATA__PAD_CFG \ + MX35_ESDHC1_CMD__PAD_CFG + +static const struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static int spi_internal_chipselect[] = { + MXC_SPI_CS(0), + MXC_SPI_CS(1), + MXC_SPI_CS(2), + MXC_SPI_CS(3), +}; + +static const struct spi_imx_master spi_pdata = { + .chipselect = spi_internal_chipselect, + .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), +}; + +static const struct imxi2c_platform_data i2c_data = { + .bitrate = 100000, +}; + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + unsigned int ret; + + if (board_is_rev(BOARD_REV_2)) + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 7, 1); + + if (to_platform_device(dev)->id == 0) { + if (0 != pmic_gpio_get_designation_bit_val(2, &ret)) + printk(KERN_ERR "Get cd status error."); + return ret; + } + + return 0; +} + +static int sdhc_write_protect(struct device *dev) +{ + unsigned int rc = 0; + + if (0 != pmic_gpio_get_designation_bit_val(3, &rc)) + printk(KERN_ERR "Get wp status error."); + + return rc; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_32_33, +#if defined(CONFIG_SDIO_UNIFI_FS) || defined(CONFIG_SDIO_UNIFI_FS_MODULE) + .caps = MMC_CAP_4_BIT_DATA, +#else + .caps = MMC_CAP_8_BIT_DATA, +#endif + .min_clk = 150000, + .max_clk = 52000000, + /* Do not disable the eSDHC clk on MX35 3DS board, + * since SYSTEM can't boot up after the reset key + * is pressed when the SD/MMC boot mode is used. + * The root cause is that the ROM code don't ensure + * the SD/MMC clk is running when boot system. + * */ + .clk_always_on = 1, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "sdhc_clk", +}; + +/* MTD NOR flash */ +static struct mtd_partition mxc_nor_partitions[] = { + { + .name = "Bootloader", + .size = 512 * 1024, + .offset = 0x00000000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "nor.Kernel", + .size = 4 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0, + }, { + .name = "nor.userfs", + .size = 30 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = 0, + }, { + .name = "nor.rootfs", + .size = 28 * 1024 * 1024, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "FIS directory", + .size = 12 * 1024, + .offset = 0x01FE0000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Redboot config", + .size = MTDPART_SIZ_FULL, + .offset = 0x01FFF000, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct flash_platform_data mxc_nor_flash_pdata = { + .map_name = "cfi_probe", + .width = 2, + .parts = mxc_nor_partitions, + .nr_parts = ARRAY_SIZE(mxc_nor_partitions), +}; + +/* MTD NAND flash */ +static struct mtd_partition mxc_nand_partitions[] = { + { + .name = "nand.bootloader", + .offset = 0, + .size = 3 * 1024 * 1024, + }, { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024, + }, { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024, + }, { + .name = "nand.configure", + .offset = MTDPART_OFS_APPEND, + .size = 8 * 1024 * 1024, + }, { + .name = "nand.userfs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data mxc_nandv2_pdata = { + .parts = mxc_nand_partitions, + .nr_parts = ARRAY_SIZE(mxc_nand_partitions), + .width = 1, +}; + +static void __init mxc_register_nandv2_devices(void) +{ + if (__raw_readl(MXC_CCM_RCSR) & MXC_CCM_RCSR_NF16B) + mxc_nandv2_pdata.width = 2; + + mxc_register_device(&mxc_nandv2_device, &mxc_nandv2_pdata); +} + +static void si4702_reset(void) +{ + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 4, 0); + msleep(100); + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 4, 1); + msleep(100); +} + +static void si4702_clock_ctl(int flag) +{ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 7, flag); +} + +static struct mxc_fm_platform_data si4702_data = { + .reg_vio = "VSD", + .reg_vdd = NULL, + .reset = si4702_reset, + .clock_ctl = si4702_clock_ctl, + .sksnr = 0, + .skcnt = 0, + .band = 0, + .space = 100, + .seekth = 0xa, +}; + +static int tsc2007_get_pendown_state(void) +{ + return !gpio_get_value(MX35_GPIO1_4); +} + +struct tsc2007_platform_data tsc2007_data = { + .model = 2007, + .x_plate_ohms = 400, + .get_pendown_state = tsc2007_get_pendown_state, +}; + +static struct mxc_camera_platform_data camera_data = { + .core_regulator = "SW1", + .io_regulator = "VAUDIO", + .analog_regulator = NULL, + .gpo_regulator = "PWGT1", + .mclk = 27000000, +}; + +static void adv7180_pwdn(int pwdn) +{ + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 1, ~pwdn); +} + +static void adv7180_reset(void) +{ + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 6, 0); + msleep(5); + pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_1, 6, 1); + msleep(5); +} + +static struct mxc_tvin_platform_data adv7180_data = { + .dvddio_reg = NULL, + .dvdd_reg = "SW3", + .avdd_reg = "PWGT2", + .pvdd_reg = NULL, + .pwdn = adv7180_pwdn, + .reset = adv7180_reset, +}; + +static struct i2c_board_info mxc_i2c_board_info[] __initdata = { + { + I2C_BOARD_INFO("max8660", 0x34), + }, { I2C_BOARD_INFO("tsc2007", 0x48), + .platform_data = &tsc2007_data, + .irq = IOMUX_TO_IRQ(MX35_GPIO1_4), + }, { + I2C_BOARD_INFO("ov2640", 0x30), + .platform_data = (void *)&camera_data, + }, { + I2C_BOARD_INFO("sgtl5000-i2c", 0x0a), + }, { + I2C_BOARD_INFO("ak4647-i2c", 0x12), + }, { +#if defined(CONFIG_I2C_SLAVE_CLIENT) + I2C_BOARD_INFO("i2c-slave-client", 0x55), +#endif + }, { + I2C_BOARD_INFO("si4702", 0x10), + .platform_data = (void *)&si4702_data, + }, { + I2C_BOARD_INFO("adv7180", 0x21), + .platform_data = (void *)&adv7180_data, + }, +}; + +static struct platform_device *devices[] __initdata = { + &mxc_fec_device, + &mxc_dma_device, +}; + +static struct pad_cfg mx35pdk_pads[] = { + /* UART1 */ + {MX35_PAD_CTS1__UART1_CTS, }, + {MX35_PAD_RTS1__UART1_RTS, }, + {MX35_PAD_TXD1__UART1_TXD_MUX, }, + {MX35_PAD_RXD1__UART1_RXD_MUX, }, + /* FEC */ + {MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, }, + {MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, }, + {MX35_PAD_FEC_RX_DV__FEC_RX_DV, }, + {MX35_PAD_FEC_COL__FEC_COL,}, + {MX35_PAD_FEC_RDATA0__FEC_RDATA_0, }, + {MX35_PAD_FEC_TDATA0__FEC_TDATA_0, }, + {MX35_PAD_FEC_TX_EN__FEC_TX_EN, }, + {MX35_PAD_FEC_MDC__FEC_MDC, }, + {MX35_PAD_FEC_MDIO__FEC_MDIO, }, + {MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, }, + {MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, }, + {MX35_PAD_FEC_CRS__FEC_CRS, }, + {MX35_PAD_FEC_RDATA1__FEC_RDATA_1, }, + {MX35_PAD_FEC_TDATA1__FEC_TDATA_1, }, + {MX35_PAD_FEC_RDATA2__FEC_RDATA_2, }, + {MX35_PAD_FEC_TDATA2__FEC_TDATA_2, }, + {MX35_PAD_FEC_RDATA3__FEC_RDATA_3, }, + {MX35_PAD_FEC_TDATA3__FEC_TDATA_3, }, + /* USBOTG */ + {MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,}, + {MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, }, + + /* SD/MMC-SDHC1 */ + {MX35_PAD_SD1_CMD__ESDHC1_CMD, MX35_ESDHC1_CMD__PAD_CFG}, + {MX35_PAD_SD1_CLK__ESDHC1_CLK, MX35_ESDHC1_CLK__PAD_CFG}, + {MX35_PAD_SD1_DATA0__ESDHC1_DAT0, MX35_ESDHC1_DATA__PAD_CFG}, + {MX35_PAD_SD1_DATA1__ESDHC1_DAT1, MX35_ESDHC1_DATA__PAD_CFG}, + {MX35_PAD_SD1_DATA2__ESDHC1_DAT2, MX35_ESDHC1_DATA__PAD_CFG}, + {MX35_PAD_SD1_DATA3__ESDHC1_DAT3, MX35_ESDHC1_DATA__PAD_CFG}, +#if !defined(CONFIG_SDIO_UNIFI_FS) && !defined(CONFIG_SDIO_UNIFI_FS_MODULE) + {MX35_PAD_SD2_CMD__ESDHC1_DAT4, MX35_ESDHC1_DATA__PAD_CFG}, + {MX35_PAD_SD2_CLK__ESDHC1_DAT5, MX35_ESDHC1_DATA__PAD_CFG}, + {MX35_PAD_SD2_DATA0__ESDHC1_DAT6, MX35_ESDHC1_DATA__PAD_CFG}, + {MX35_PAD_SD2_DATA1__ESDHC1_DAT7, MX35_ESDHC1_DATA__PAD_CFG}, +#endif + /* Capature */ + {MX35_PAD_CAPTURE__GPIO1_4,}, +}; + +/* OTG config */ +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, +}; + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads_ext(mx35pdk_pads, + ARRAY_SIZE(mx35pdk_pads)); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + imx35_add_imx_uart0(&uart_pdata); + imx35_add_imx_uart1(&uart_pdata); + imx35_add_imx_uart2(&uart_pdata); + + imx35_add_spi_imx0(&spi_pdata); + imx35_add_spi_imx1(&spi_pdata); + + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + + mxc_register_device(&mxc_nor_mtd_device, &mxc_nor_flash_pdata); + + mxc_register_nandv2_devices(); + + i2c_register_board_info(0, mxc_i2c_board_info, + ARRAY_SIZE(mxc_i2c_board_info)); + imx35_add_imx_i2c0(&i2c_data); + + mx35_3stack_init_mc13892(); + mx35_3stack_init_mc9s08dz60(); + + imx35_add_imx_mmc0(&mmc1_data); + + if (mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT)) + printk(KERN_WARNING "Init of the debugboard failed, all " + "devices on the board are unusable.\n"); +} + +static void __init mx35pdk_timer_init(void) +{ + mx35_clocks_init(); +} + +struct sys_timer mx35pdk_timer = { + .init = mx35pdk_timer_init, +}; + +MACHINE_START(MX35_3DS, "Freescale MX35PDK") + /* Maintainer: Freescale Semiconductor, Inc */ + .phys_io = MX35_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, + .map_io = mx35_map_io, + .init_irq = mx35_init_irq, + .init_machine = mxc_board_init, + .timer = &mx35pdk_timer, +MACHINE_END diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c deleted file mode 100644 index bcac84d4dca4..000000000000 --- a/arch/arm/mach-mx3/mach-mx35pdk.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "devices.h" - -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *devices[] __initdata = { - &mxc_fec_device, -}; - -static struct pad_desc mx35pdk_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* USBOTG */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, -}; - -/* OTG config */ -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, -}; - -/* - * Board specific initialization. - */ -static void __init mxc_board_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - mxc_register_device(&mxc_uart_device0, &uart_pdata); - - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); -} - -static void __init mx35pdk_timer_init(void) -{ - mx35_clocks_init(); -} - -struct sys_timer mx35pdk_timer = { - .init = mx35pdk_timer_init, -}; - -MACHINE_START(MX35_3DS, "Freescale MX35PDK") - /* Maintainer: Freescale Semiconductor, Inc */ - .phys_io = MX35_AIPS1_BASE_ADDR, - .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = MX3x_PHYS_OFFSET + 0x100, - .map_io = mx35_map_io, - .init_irq = mx35_init_irq, - .init_machine = mxc_board_init, - .timer = &mx35pdk_timer, -MACHINE_END diff --git a/arch/arm/mach-mx3/mx31_sdma_script_code_v1.h b/arch/arm/mach-mx3/mx31_sdma_script_code_v1.h new file mode 100644 index 000000000000..fd9967fa8b7a --- /dev/null +++ b/arch/arm/mach-mx3/mx31_sdma_script_code_v1.h @@ -0,0 +1,581 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MX31_SDMA_SCRIPT_CODE_V1_H__ +#define __MX31_SDMA_SCRIPT_CODE_V1_H__ + +/*! +* Following define start address of start script +*/ +#define mx31_start_ADDR 0 +/*! +* Following define size of start script +*/ +#define mx31_start_SIZE 21 + +/*! +* Following define start address of core script +*/ +#define mx31_core_ADDR 80 +/*! +* Following define size of core script +*/ +#define mx31_core_SIZE 152 + +/*! +* Following define start address of common script +*/ +#define mx31_common_ADDR 232 +/*! +* Following define size of common script +*/ +#define mx31_common_SIZE 191 + +/*! +* Following define start address of burst_copy script +*/ +#define mx31_burst_copy_ADDR 423 +/*! +* Following define size of burst_copy script +*/ +#define mx31_burst_copy_SIZE 87 + +/*! +* Following define start address of dsp_2_burst script +*/ +#define mx31_dsp_2_burst_ADDR 510 +/*! +* Following define size of dsp_2_burst script +*/ +#define mx31_dsp_2_burst_SIZE 24 + +/*! +* Following define start address of burst_2_dsp script +*/ +#define mx31_burst_2_dsp_ADDR 534 +/*! +* Following define size of burst_2_dsp script +*/ +#define mx31_burst_2_dsp_SIZE 24 + +/*! +* Following define start address of dsp_copy script +*/ +#define mx31_dsp_copy_ADDR 558 +/*! +* Following define size of dsp_copy script +*/ +#define mx31_dsp_copy_SIZE 86 + +/*! +* Following define start address of mcu_2_mcu script +*/ +#define mx31_mcu_2_mcu_ADDR 644 +/*! +* Following define size of mcu_2_mcu script +*/ +#define mx31_mcu_2_mcu_SIZE 79 + +/*! +* Following define start address of mcu_2_per script +*/ +#define mx31_mcu_2_per_ADDR 723 +/*! +* Following define size of mcu_2_per script +*/ +#define mx31_mcu_2_per_SIZE 88 + +/*! +* Following define start address of test script +*/ +#define mx31_test_ADDR 811 +/*! +* Following define size of test script +*/ +#define mx31_test_SIZE 63 + +/*! +* Following define start address of mcu_2_dsp script +*/ +#define mx31_mcu_2_dsp_ADDR 874 +/*! +* Following define size of mcu_2_dsp script +*/ +#define mx31_mcu_2_dsp_SIZE 30 + +/*! +* Following define start address of mcu_2_dsp_2buf script +*/ +#define mx31_mcu_2_dsp_2buf_ADDR 904 +/*! +* Following define size of mcu_2_dsp_2buf script +*/ +#define mx31_mcu_2_dsp_2buf_SIZE 113 + +/*! +* Following define start address of dsp_2_mcu script +*/ +#define mx31_dsp_2_mcu_ADDR 1017 +/*! +* Following define size of dsp_2_mcu script +*/ +#define mx31_dsp_2_mcu_SIZE 30 + +/*! +* Following define start address of dsp_2_mcu_2buf script +*/ +#define mx31_dsp_2_mcu_2buf_ADDR 1047 +/*! +* Following define size of dsp_2_mcu_2buf script +*/ +#define mx31_dsp_2_mcu_2buf_SIZE 113 + +/*! +* Following define start address of dsp_2_dsp script +*/ +#define mx31_dsp_2_dsp_ADDR 1160 +/*! +* Following define size of dsp_2_dsp script +*/ +#define mx31_dsp_2_dsp_SIZE 64 + +/*! +* Following define start address of per_2_mcu script +*/ +#define mx31_per_2_mcu_ADDR 1224 +/*! +* Following define size of per_2_mcu script +*/ +#define mx31_per_2_mcu_SIZE 121 + +/*! +* Following define start address of dsp_2_per_2buf script +*/ +#define mx31_dsp_2_per_2buf_ADDR 1345 +/*! +* Following define size of dsp_2_per_2buf script +*/ +#define mx31_dsp_2_per_2buf_SIZE 164 + +/*! +* Following define start address of per_2_dsp_2buf script +*/ +#define mx31_per_2_dsp_2buf_ADDR 1509 +/*! +* Following define size of per_2_dsp_2buf script +*/ +#define mx31_per_2_dsp_2buf_SIZE 168 + +/*! +* Following define start address of per_2_per script +*/ +#define mx31_per_2_per_ADDR 1677 +/*! +* Following define size of per_2_per script +*/ +#define mx31_per_2_per_SIZE 67 + +/*! +* Following define start address of error_dsp script +*/ +#define mx31_error_dsp_ADDR 1744 +/*! +* Following define size of error_dsp script +*/ +#define mx31_error_dsp_SIZE 34 + +/*! +* Following define start address of ap_2_ap script +*/ +#define mx31_ap_2_ap_ADDR 6144 +/*! +* Following define size of ap_2_ap script +*/ +#define mx31_ap_2_ap_SIZE 294 + +/*! +* Following define start address of app_2_mcu script +*/ +#define mx31_app_2_mcu_ADDR 6438 +/*! +* Following define size of app_2_mcu script +*/ +#define mx31_app_2_mcu_SIZE 101 + +/*! +* Following define start address of ata_2_mcu script +*/ +#define mx31_ata_2_mcu_ADDR 6539 +/*! +* Following define size of ata_2_mcu script +*/ +#define mx31_ata_2_mcu_SIZE 110 + +/*! +* Following define start address of dptc_dvfs script +*/ +#define mx31_dptc_dvfs_ADDR 6649 +/*! +* Following define size of dptc_dvfs script +*/ +#define mx31_dptc_dvfs_SIZE 274 + +/*! +* Following define start address of error script +*/ +#define mx31_error_ADDR 6923 +/*! +* Following define size of error script +*/ +#define mx31_error_SIZE 73 + +/*! +* Following define start address of firi_2_mcu script +*/ +#define mx31_firi_2_mcu_ADDR 6996 +/*! +* Following define size of firi_2_mcu script +*/ +#define mx31_firi_2_mcu_SIZE 114 + +/*! +* Following define start address of mcu_2_app script +*/ +#define mx31_mcu_2_app_ADDR 7110 +/*! +* Following define size of mcu_2_app script +*/ +#define mx31_mcu_2_app_SIZE 127 + +/*! +* Following define start address of mcu_2_ata script +*/ +#define mx31_mcu_2_ata_ADDR 7237 +/*! +* Following define size of mcu_2_ata script +*/ +#define mx31_mcu_2_ata_SIZE 87 + +/*! +* Following define start address of mcu_2_firi script +*/ +#define mx31_mcu_2_firi_ADDR 7324 +/*! +* Following define size of mcu_2_firi script +*/ +#define mx31_mcu_2_firi_SIZE 77 + +/*! +* Following define start address of mcu_2_mshc script +*/ +#define mx31_mcu_2_mshc_ADDR 7401 +/*! +* Following define size of mcu_2_mshc script +*/ +#define mx31_mcu_2_mshc_SIZE 48 + +/*! +* Following define start address of mcu_2_shp script +*/ +#define mx31_mcu_2_shp_ADDR 7449 +/*! +* Following define size of mcu_2_shp script +*/ +#define mx31_mcu_2_shp_SIZE 123 + +/*! +* Following define start address of mshc_2_mcu script +*/ +#define mx31_mshc_2_mcu_ADDR 7572 +/*! +* Following define size of mshc_2_mcu script +*/ +#define mx31_mshc_2_mcu_SIZE 60 + +/*! +* Following define start address of shp_2_mcu script +*/ +#define mx31_shp_2_mcu_ADDR 7632 +/*! +* Following define size of shp_2_mcu script +*/ +#define mx31_shp_2_mcu_SIZE 101 + +/*! +* Following define start address of uart_2_mcu script +*/ +#define mx31_uart_2_mcu_ADDR 7733 +/*! +* Following define size of uart_2_mcu script +*/ +#define mx31_uart_2_mcu_SIZE 105 + +/*! +* Following define start address of uartsh_2_mcu script +*/ +#define mx31_uartsh_2_mcu_ADDR 7838 +/*! +* Following define size of uartsh_2_mcu script +*/ +#define mx31_uartsh_2_mcu_SIZE 98 + +/*! +* Following define the start address of sdma ram +*/ + +#define MX31_RAM_CODE_START_ADDR 6144 +/*! +* Following define the size of sdma ram +*/ +#define MX31_RAM_CODE_SIZE 1792 + +/*! +* This function returns buffer that holds the image of SDMA RAM. +* This is required to start on a 4-byte aligned boundary on some platforms +* for SDMA to work properly. +* +* @return pointer to buffer that holds the image of SDMA RAM +*/ + +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static short mx31_sdma_code[] = { + 0xc0ec, 0x7d59, 0x0970, 0x0111, 0x5111, 0x5ad1, 0x5bd9, 0xc0fe, + 0x5ce1, 0x7d02, 0x0200, 0x9806, 0x08ff, 0x0011, 0x28ff, 0x00bc, + 0x05df, 0x7d4b, 0x06df, 0x7d2f, 0x6dc5, 0x6ed5, 0x5ef1, 0x0288, + 0xd81a, 0x9854, 0x0b04, 0x00d3, 0x7d20, 0x06a5, 0x3e03, 0x3d03, + 0x03a5, 0x3b03, 0x008b, 0x058b, 0x7802, 0x63d8, 0x0000, 0x7e72, + 0x63ff, 0x7e70, 0x02a5, 0x008a, 0x4e00, 0x7d01, 0x983d, 0x6dcf, + 0x6edf, 0x0015, 0x0015, 0x7802, 0x63d8, 0x0000, 0x7e63, 0x63ff, + 0x7e61, 0x3a03, 0x008a, 0x6dcd, 0x6edd, 0x7801, 0x63d8, 0x7e5a, + 0x63ff, 0x7e58, 0x0006, 0x6dc5, 0x6e07, 0x5ef1, 0x0288, 0xd8f7, + 0x7e02, 0x7f04, 0x9854, 0x0007, 0x68cc, 0x6b28, 0x54e1, 0x0089, + 0xdb13, 0x0188, 0x5ce1, 0x9854, 0x52d1, 0x53d9, 0x54e1, 0xc10d, + 0x7dad, 0x0200, 0x9800, 0x0200, 0x9800, 0x06df, 0x7d06, 0x6d23, + 0x6ed5, 0x5ef1, 0x0288, 0xd8cd, 0x9854, 0x5ef1, 0x6e07, 0x6d03, + 0x0b04, 0x00d3, 0x7d59, 0x06a5, 0x3e03, 0x3d03, 0x4d00, 0x7d09, + 0x03a5, 0x00a3, 0x0588, 0x008b, 0xd8c9, 0x7ed8, 0x620c, 0x7ed6, + 0x008d, 0x4e00, 0x7c25, 0x0a20, 0x00da, 0x7c22, 0x6503, 0x3d1f, + 0x02a5, 0x00a2, 0x0215, 0x0215, 0x6a18, 0x6a28, 0x7fc7, 0x0a20, + 0x0b08, 0x00da, 0x7c06, 0x6b18, 0x6b28, 0x7fc0, 0x0000, 0x2020, + 0x9889, 0x0688, 0x0015, 0x0015, 0x6818, 0x6828, 0x7fb7, 0x98c2, + 0x0007, 0x6a0c, 0x54e1, 0x0089, 0xdb0f, 0x0188, 0x5ce1, 0x9854, + 0x0b04, 0x00d3, 0x7d21, 0x0389, 0x1b12, 0x048b, 0x0688, 0x0015, + 0x0015, 0x0588, 0x038c, 0x0a08, 0x05da, 0x008d, 0x7c01, 0x008a, + 0x05a0, 0x7803, 0x620b, 0x5a03, 0x1b01, 0x7e98, 0x008b, 0x00a4, + 0x038c, 0x7803, 0x5203, 0x6a0b, 0x1b01, 0x6a28, 0x7f8f, 0x0000, + 0x4d00, 0x7ce8, 0x008e, 0x3803, 0xd8c9, 0x7e88, 0x620c, 0x7e86, + 0x9854, 0x7802, 0x6209, 0x6a29, 0x0006, 0x3e03, 0x4e00, 0x7d11, + 0x0b04, 0x03a6, 0x02db, 0x7d01, 0x038a, 0x02a3, 0x048a, 0x008b, + 0x7802, 0x6329, 0x6bc8, 0x7ebc, 0x63c8, 0x7ebc, 0x008c, 0x4800, + 0x7d15, 0x0488, 0x0015, 0x0015, 0x6edf, 0x7803, 0x632b, 0x6bc8, + 0x0000, 0x7eae, 0x63c8, 0x7eae, 0x008c, 0x3803, 0x6edd, 0x7803, + 0x6329, 0x6bc8, 0x0000, 0x7ea4, 0x63c8, 0x7ea4, 0x0006, 0x3d03, + 0x4d00, 0x7d0e, 0x0b04, 0x03a5, 0x02db, 0x7d01, 0x038a, 0x02a3, + 0x048a, 0x008b, 0x7802, 0x63c8, 0x6b09, 0x7e1e, 0x7f1e, 0x008c, + 0x0488, 0x0015, 0x0015, 0x6dcf, 0x0288, 0x008a, 0x0d08, 0x02dd, + 0x7c01, 0x008d, 0x7802, 0x63c8, 0x6b0b, 0x7e0e, 0x6b28, 0x7f0d, + 0x0000, 0x02dd, 0x7c02, 0x2208, 0x990d, 0x008c, 0x3803, 0x65c0, + 0x6dc5, 0x7802, 0x63c8, 0x6b09, 0x6b28, 0x0006, 0x0870, 0x0011, + 0x5010, 0xc0ec, 0x7d5e, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, + 0x7d02, 0x0200, 0x992c, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, 0x0511, + 0x1dff, 0x05bc, 0x4d00, 0x7d44, 0x0b70, 0x0311, 0x522b, 0x5313, + 0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f3a, 0x0400, 0x993c, 0x008f, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210, + 0x4a00, 0x7d1c, 0x4a02, 0x7d20, 0x4a01, 0x7d23, 0x0b70, 0x0311, + 0x53eb, 0x62c8, 0x7e24, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6a09, + 0x7f1e, 0x0212, 0x6a09, 0x7f1b, 0x0212, 0x6a09, 0x7f18, 0x2003, + 0x4800, 0x7cef, 0x0b70, 0x0311, 0x5313, 0x997d, 0x0015, 0x0015, + 0x7802, 0x62c8, 0x6a0b, 0x997c, 0x0015, 0x7802, 0x62c8, 0x6a0a, + 0x997c, 0x7802, 0x62c8, 0x6a09, 0x7c02, 0x0000, 0x993a, 0xdb13, + 0x6a28, 0x7ffd, 0x008b, 0x52c3, 0x53cb, 0xc10d, 0x7da5, 0x0200, + 0x992c, 0x0200, 0x9929, 0xc19d, 0xc0ec, 0x7d69, 0x0c70, 0x0411, + 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe, 0x56fa, 0x7d02, + 0x0200, 0x9994, 0x6d07, 0x5bca, 0x5cd2, 0x0bff, 0x0311, 0x1bff, + 0x04bb, 0x0415, 0x53da, 0x4c00, 0x7d47, 0x0a70, 0x0211, 0x552a, + 0x5212, 0x008d, 0x00bb, 0x4800, 0x7c07, 0x05b9, 0x4d00, 0x7c13, + 0x6928, 0x7f2d, 0x0400, 0x99a5, 0x008f, 0x0015, 0x04d8, 0x7d01, + 0x008c, 0x04a0, 0x0015, 0x7802, 0x55c6, 0x6d0b, 0x7e29, 0x6d28, + 0x7f1e, 0x0000, 0x99a3, 0x1e20, 0x5506, 0x2620, 0x008d, 0x0560, + 0x7c08, 0x065f, 0x55c6, 0x063f, 0x7e1b, 0x6d0a, 0x7f10, 0x4c00, + 0x7d1b, 0x04d8, 0x7d02, 0x008c, 0x0020, 0x04a0, 0x0015, 0x7802, + 0x55c6, 0x6d0b, 0x7e0d, 0x6d28, 0x7f02, 0x0000, 0x99ec, 0x0007, + 0x680c, 0x6d0c, 0x6507, 0x6d07, 0x6d2b, 0x6d28, 0x0007, 0x680c, + 0x0007, 0x54d2, 0x0454, 0x99ef, 0x6928, 0x7ff1, 0x54d2, 0x008a, + 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7d9f, 0x0200, 0x9994, 0x0200, + 0x998c, 0xc0ec, 0x7d72, 0x0800, 0x0970, 0x0111, 0x5111, 0x5ac1, + 0x5bc9, 0x028e, 0xc0fe, 0x068a, 0x7c6a, 0x5dd9, 0x5ce1, 0x0bff, + 0x0311, 0x1bff, 0x03bc, 0x5bd1, 0x1a5c, 0x6ac3, 0x63c8, 0x0363, + 0x7c05, 0x036f, 0x7d27, 0x0374, 0x7c7a, 0x9a71, 0xdb04, 0x3c06, + 0x4c00, 0x7df7, 0x028f, 0x1a04, 0x6a23, 0x620b, 0x6f23, 0x301f, + 0x00aa, 0x0462, 0x7c04, 0x4a00, 0x7d0b, 0x2001, 0x9a30, 0x048a, + 0x620b, 0x2201, 0x1c01, 0x1801, 0x02dc, 0x7d02, 0x301f, 0x00aa, + 0x048f, 0x1c04, 0x6c07, 0x0488, 0x3c1f, 0x6c2b, 0x0045, 0x028e, + 0x1a5c, 0x9a11, 0x058f, 0x1d0c, 0x6d23, 0x650b, 0x007d, 0x7c01, + 0x1d08, 0x007c, 0x7c01, 0x1d04, 0x6d23, 0x650b, 0x0488, 0x3c1f, + 0x0417, 0x0417, 0x0417, 0x0417, 0x059c, 0x6d23, 0x028e, 0x1a34, + 0x6ad7, 0x0488, 0x0804, 0x7802, 0x650b, 0x6dc8, 0x008c, 0x1a28, + 0x6ad7, 0x63c8, 0x034c, 0x6bc8, 0x54d1, 0x4c00, 0x7d06, 0x0065, + 0x7c02, 0x0101, 0x0025, 0x0400, 0x9a0d, 0x52c1, 0x53c9, 0x54e1, + 0x0453, 0xc10d, 0x7d95, 0x0200, 0x9a00, 0x0200, 0x99f9, 0x0200, + 0x9a00, 0x55d9, 0x6d07, 0x54d1, 0x058a, 0x2508, 0x6dc7, 0x0373, + 0x7c03, 0x65c8, 0x6d0b, 0x2408, 0x0372, 0x7c04, 0x65c8, 0x6d0b, + 0x2408, 0x9a86, 0x6cce, 0x65c8, 0x6d0a, 0x2404, 0x6d28, 0x6507, + 0x5dd9, 0x5cd1, 0x6ad7, 0x6ae3, 0x63c8, 0x0334, 0x6bc8, 0x0370, + 0x7ca9, 0x0c60, 0x0411, 0x04bb, 0x4c00, 0x7da4, 0x0410, 0x1c30, + 0x0410, 0x04bb, 0x046d, 0x7d0a, 0x047d, 0x7c03, 0x047c, 0x7c01, + 0x9a3a, 0x003b, 0x003a, 0x0039, 0x0058, 0x9ab5, 0x047d, 0x7d03, + 0x047c, 0x7d01, 0x9a3a, 0x005b, 0xdaf9, 0x1d18, 0x6d23, 0x650b, + 0x0510, 0x003a, 0x0039, 0x0038, 0x00ad, 0xdb04, 0x0c30, 0x0410, + 0x04bb, 0x003c, 0x003d, 0x00ac, 0xdaf9, 0x007b, 0x7c04, 0x003d, + 0x003c, 0x1d0c, 0x9ad6, 0x048f, 0x1c14, 0x6c23, 0x640b, 0x4401, + 0x7d04, 0x005d, 0x005c, 0x1d0c, 0x9ad6, 0x0310, 0x3b30, 0x4b30, + 0x7d01, 0x1b10, 0x0310, 0x003d, 0x003c, 0x00ab, 0x6ad7, 0x63c8, + 0x6d23, 0x650b, 0x0560, 0x7d03, 0x005e, 0xdaed, 0x9a3a, 0x003e, + 0x0c80, 0x0410, 0x0394, 0xdaed, 0x640b, 0x037f, 0x7d02, 0x1a14, + 0x9aea, 0x1a0c, 0x6ad7, 0x6cc8, 0x9a3a, 0x0c7f, 0x0410, 0x03b4, + 0x04b8, 0x03ac, 0x640b, 0x6bc8, 0x028e, 0x1a04, 0x6ad7, 0x6cc8, + 0x0006, 0x058f, 0x1d08, 0x6d23, 0x650b, 0x007d, 0x7c01, 0x1d38, + 0x007c, 0x7c01, 0x1d1c, 0x0006, 0x048b, 0x042c, 0x0454, 0x042b, + 0x6ad7, 0x6cc8, 0x0006, 0x0007, 0x684c, 0x6144, 0x9b1c, 0x0007, + 0x68cc, 0x61d0, 0x9b1c, 0x0007, 0x680c, 0x680c, 0x6107, 0x6907, + 0x692b, 0x6928, 0x0007, 0x680c, 0x0d70, 0x0511, 0x5515, 0x55f5, + 0x01a5, 0x0dff, 0x0512, 0x1dff, 0x0512, 0x04bd, 0x0499, 0x0454, + 0x0006, 0x08ff, 0x0011, 0x28ff, 0x0006, 0x038c, 0x0eff, 0x0611, + 0x2eff, 0x03b6, 0x0006, 0x53d6, 0x0398, 0x5bd6, 0x53ee, 0x0398, + 0x5bee, 0x0006, 0x52de, 0x53e6, 0x54ee, 0x0498, 0x0454, 0x0006, + 0x50f6, 0x52c6, 0x53ce, 0x54d6, 0x0498, 0x0454, 0x0006, 0x6207, + 0x0b70, 0x0311, 0x5013, 0x55f0, 0x02a5, 0x0bff, 0x0312, 0x1bff, + 0x0312, 0x04bb, 0x049a, 0x0006, 0x1e10, 0x0870, 0x0011, 0x5010, + 0xc0ec, 0x7d39, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, + 0x0200, 0x9b5b, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d17, 0x6ec3, 0x62c8, 0x7e28, 0x0264, 0x7d08, 0x0b70, + 0x0311, 0x522b, 0x02b9, 0x4a00, 0x7c18, 0x0400, 0x9b6a, 0x0212, + 0x3aff, 0x008a, 0x05d8, 0x7d01, 0x008d, 0x0a10, 0x6ed3, 0x6ac8, + 0xdba5, 0x6a28, 0x7f17, 0x0b70, 0x0311, 0x5013, 0xdbbd, 0x52c0, + 0x53c8, 0xc10d, 0x7dd0, 0x0200, 0x9b5b, 0x008f, 0x00d5, 0x7d01, + 0x008d, 0xdba5, 0x9b68, 0x0200, 0x9b58, 0x0007, 0x68cc, 0x6a28, + 0x7f01, 0x9ba3, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07, 0x6a2b, + 0x6a28, 0x0007, 0x680c, 0x0454, 0x9b81, 0x05a0, 0x1e08, 0x6ec3, + 0x0388, 0x3b03, 0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b, 0x7ee5, + 0x6a28, 0x7fe8, 0x0000, 0x6ec1, 0x008b, 0x7802, 0x62c8, 0x6a09, + 0x7edc, 0x6a28, 0x7fdf, 0x2608, 0x0006, 0x55f0, 0x6207, 0x02a5, + 0x0dff, 0x0511, 0x1dff, 0x04b5, 0x049a, 0x0006, 0x0870, 0x0011, + 0x5010, 0xc0ec, 0x7d78, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, + 0x7d02, 0x0200, 0x9bcc, 0x6d03, 0x6ed3, 0x0dff, 0x0511, 0x1dff, + 0x05bc, 0x5df8, 0x4d00, 0x7d5e, 0x0b70, 0x0311, 0x522b, 0x5313, + 0x02b9, 0x4a00, 0x7c04, 0x62ff, 0x7e3f, 0x0400, 0x9bdc, 0x008f, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5ddb, 0x0d03, 0x0512, 0x05bc, + 0x0510, 0x5dd3, 0x4d00, 0x7d27, 0x4d02, 0x7d20, 0x4d01, 0x7d1a, + 0x0b70, 0x0311, 0x53eb, 0x0360, 0x7d05, 0x6509, 0x7e25, 0x620a, + 0x7e23, 0x9c06, 0x620a, 0x7e20, 0x6509, 0x7e1e, 0x0512, 0x0512, + 0x02ad, 0x6ac8, 0x7f19, 0x2003, 0x4800, 0x7ced, 0x0b70, 0x0311, + 0x5313, 0x9c21, 0x7802, 0x6209, 0x6ac8, 0x9c20, 0x0015, 0x7802, + 0x620a, 0x6ac8, 0x9c20, 0x0015, 0x0015, 0x7802, 0x620b, 0x6ac8, + 0x7c03, 0x0000, 0x55db, 0x9bda, 0x0007, 0x68cc, 0x680c, 0x55d3, + 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9c2f, 0x0017, 0x0017, 0x55db, + 0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8, + 0x04ad, 0x0454, 0x62ff, 0x7ee8, 0x008b, 0x52c0, 0x53c8, 0xc10d, + 0x7d8b, 0x0200, 0x9bcc, 0x0200, 0x9bc9, 0xc19d, 0xc0ec, 0x7d52, + 0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe, + 0x56fa, 0x7d02, 0x0200, 0x9c4e, 0x6d03, 0x5bca, 0x5cd2, 0x0bff, + 0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da, 0x0a70, 0x0211, 0x4c00, + 0x7d28, 0x552a, 0x05bb, 0x4d00, 0x7c02, 0x0400, 0x9c61, 0x4c01, + 0x7d0f, 0x008f, 0x0015, 0x04d8, 0x7d01, 0x008c, 0x0020, 0x04a0, + 0x0015, 0x7802, 0x650b, 0x5d06, 0x0000, 0x7e0c, 0x7f0d, 0x9c5f, + 0x650a, 0x7e08, 0x008d, 0x0011, 0x0010, 0x05a8, 0x065f, 0x5d06, + 0x063f, 0x7f02, 0x0007, 0x680c, 0x0007, 0x5012, 0x54d0, 0x0454, + 0x9c8b, 0x5012, 0x54d0, 0x0473, 0x7c06, 0x552a, 0x05b9, 0x4d00, + 0x7c02, 0x0400, 0x9c8d, 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7db6, + 0x0200, 0x9c4e, 0x0200, 0x9c46, 0x0870, 0x0011, 0x5010, 0xc0ec, + 0x7d46, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9ca2, 0x0b70, 0x0311, 0x6ed3, 0x6d03, 0x0dff, 0x0511, 0x1dff, + 0x05bc, 0x4d00, 0x7d2b, 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x62c8, + 0x7e1f, 0x0400, 0x9cb3, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x0060, 0x7c05, 0x6edd, 0x6209, 0x7e16, 0x6ac8, 0x7f11, 0x0015, + 0x0060, 0x7c05, 0x6ede, 0x620a, 0x7e0e, 0x6ac8, 0x7f09, 0x6edf, + 0x0015, 0x7802, 0x620b, 0x6ac8, 0x0000, 0x7e05, 0x7f01, 0x9cb1, + 0x0007, 0x68cc, 0x9cdd, 0x0007, 0x6a0c, 0x0454, 0x62c8, 0x7ef8, + 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7dbd, 0x0200, 0x9ca2, 0x0200, + 0x9c9f, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d29, 0x5010, 0x5ac0, + 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9cf0, 0x0870, 0x0011, + 0x6d03, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d12, 0x5228, + 0x02b9, 0x4a00, 0x7c02, 0x0400, 0x9cff, 0x620b, 0x7e06, 0x5a06, + 0x7f06, 0x0000, 0x2504, 0x7d05, 0x9cff, 0x0007, 0x680c, 0x0007, + 0x0454, 0x5010, 0x52c0, 0xc10d, 0x7ddb, 0x0200, 0x9cf0, 0x0200, + 0x9cec, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d74, 0x5010, 0x5ac0, + 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9d20, 0x6d03, + 0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd0, 0x0dff, 0x0511, 0x1dff, + 0x05bc, 0x5df8, 0x4d00, 0x7d57, 0x0a70, 0x0211, 0x532a, 0x5212, + 0x03b9, 0x4b00, 0x7c02, 0x0400, 0x9d34, 0x008f, 0x05d8, 0x7d01, + 0x008d, 0x05a0, 0x5dda, 0x55d2, 0x4d00, 0x7d27, 0x4d02, 0x7d20, + 0x4d01, 0x7d1a, 0x0a70, 0x0211, 0x52ea, 0x0260, 0x7d05, 0x6509, + 0x7e25, 0x630a, 0x7e23, 0x9d58, 0x630a, 0x7e20, 0x6509, 0x7e1e, + 0x0512, 0x0512, 0x03ad, 0x5b06, 0x7f19, 0x2003, 0x4800, 0x7ced, + 0x0a70, 0x0211, 0x5212, 0x9d73, 0x7802, 0x6309, 0x5b06, 0x9d72, + 0x0015, 0x7802, 0x630a, 0x5b06, 0x9d72, 0x0015, 0x0015, 0x7802, + 0x630b, 0x5b06, 0x7c03, 0x55da, 0x0000, 0x9d32, 0x0007, 0x680c, + 0x55d2, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9d80, 0x0017, 0x0017, + 0x55da, 0x009d, 0x55fa, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, + 0x04b8, 0x04ad, 0x0454, 0x008a, 0x52c0, 0x53c8, 0xc10d, 0x7d90, + 0x0200, 0x9d20, 0x0200, 0x9d1c, 0xc19d, 0x0870, 0x0011, 0xc0ec, + 0x7d35, 0x5010, 0x5ac0, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9d9b, 0x0870, 0x0011, 0x6d07, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d1c, 0x5228, 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f0b, + 0x0400, 0x9daa, 0x5206, 0x7e10, 0x6a0b, 0x6928, 0x7f04, 0x0000, + 0x2504, 0x7d0c, 0x9daa, 0x0007, 0x680c, 0x680c, 0x6207, 0x6a07, + 0x6a2b, 0x6a28, 0x0007, 0x680c, 0x0007, 0x0454, 0x6928, 0x7ff3, + 0x5010, 0x52c0, 0xc10d, 0x7dcf, 0x0200, 0x9d9b, 0x0200, 0x9d97, + 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d5e, 0x5010, 0x5ac0, 0x5bc8, + 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9dd7, 0x6d07, 0x5df0, + 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d44, 0x0a70, 0x0211, + 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c04, 0x6a28, 0x7f3a, 0x0400, + 0x9de6, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x0b03, 0x0312, + 0x03bc, 0x0310, 0x4b00, 0x7d1c, 0x4b02, 0x7d20, 0x4b01, 0x7d23, + 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e24, 0x0260, 0x7d02, 0x0310, + 0x0312, 0x6b09, 0x7f1e, 0x0312, 0x6b09, 0x7f1b, 0x0312, 0x6b09, + 0x7f18, 0x2003, 0x4800, 0x7cef, 0x0a70, 0x0211, 0x5212, 0x9e27, + 0x0015, 0x0015, 0x7802, 0x5306, 0x6b0b, 0x9e26, 0x0015, 0x7802, + 0x5306, 0x6b0a, 0x9e26, 0x7802, 0x5306, 0x6b09, 0x7c02, 0x0000, + 0x9de4, 0xdb13, 0x6928, 0x7ffd, 0x008a, 0x52c0, 0x53c8, 0xc10d, + 0x7da6, 0x0200, 0x9dd7, 0x0200, 0x9dd3, 0x0870, 0x0011, 0x5010, + 0xc0ec, 0x7d5b, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, + 0x0200, 0x9e3b, 0x0b70, 0x0311, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, + 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d3d, 0x522b, 0x02b9, 0x4a00, + 0x7c04, 0x6a28, 0x7f33, 0x0400, 0x9e4d, 0x028e, 0x1a94, 0x6ac3, + 0x62c8, 0x0269, 0x7d1b, 0x1e94, 0x6ec3, 0x6ed3, 0x62c8, 0x0248, + 0x6ac8, 0x2694, 0x6ec3, 0x62c8, 0x026e, 0x7d31, 0x6a09, 0x7f1e, + 0x2501, 0x4d00, 0x7d1f, 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3, + 0x0260, 0x7df1, 0x6a28, 0x7f12, 0xdb47, 0x9e8c, 0x6ee3, 0x008f, + 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d17, + 0x6a09, 0x7f04, 0x2001, 0x7cf9, 0x0000, 0x9e4b, 0x0289, 0xdb13, + 0x018a, 0x9e9b, 0x6a28, 0x7ffa, 0x0b70, 0x0311, 0x5013, 0x52c0, + 0x53c8, 0xc10d, 0x7da8, 0x0200, 0x9e3b, 0x0200, 0x9e38, 0x6a28, + 0x7fed, 0xdb47, 0x9e9b, 0x0458, 0x0454, 0x9e8c, 0xc19d, 0x0870, + 0x0011, 0xc0ec, 0x7d54, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, + 0x56f8, 0x7d02, 0x0200, 0x9ea5, 0x0b70, 0x0311, 0x6d07, 0x5df0, + 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d36, 0x522b, 0x02b9, + 0x4a00, 0x7c04, 0x6928, 0x7f2c, 0x0400, 0x9eb6, 0x028e, 0x1a94, + 0x5202, 0x0269, 0x7d16, 0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694, + 0x5206, 0x026e, 0x7d2e, 0x6a09, 0x7f1b, 0x2501, 0x4d00, 0x7d1c, + 0x028e, 0x1a98, 0x5202, 0x0260, 0x7df3, 0x6a28, 0x7f11, 0xdb47, + 0x9eee, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, + 0x026e, 0x7d17, 0x6a09, 0x7f04, 0x2001, 0x7cf9, 0x0000, 0x9eb4, + 0x0289, 0xdb13, 0x018a, 0x9efd, 0x6928, 0x7ffa, 0x0b70, 0x0311, + 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7db0, 0x0200, 0x9ea5, 0x0200, + 0x9ea1, 0x6a28, 0x7fed, 0xdb47, 0x9efd, 0x0458, 0x0454, 0x9eee, + 0x9eee +}; +#endif diff --git a/arch/arm/mach-mx3/mx31_sdma_script_code_v2.h b/arch/arm/mach-mx3/mx31_sdma_script_code_v2.h new file mode 100644 index 000000000000..a003b9416767 --- /dev/null +++ b/arch/arm/mach-mx3/mx31_sdma_script_code_v2.h @@ -0,0 +1,371 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SS15_MX31" + +*******************************************************************************/ + +#ifndef __MX31_SDMA_SCRIPT_CODE_V2_H__ +#define __MX31_SDMA_SCRIPT_CODE_V2_H__ + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define mx31_start_ADDR_2 0 +#define mx31_start_SIZE_2 20 + +#define mx31_core_ADDR_2 80 +#define mx31_core_SIZE_2 152 + +#define mx31_common_ADDR_2 232 +#define mx31_common_SIZE_2 191 + +#define mx31_ap_2_ap_ADDR_2 423 +#define mx31_ap_2_ap_SIZE_2 294 + +#define mx31_bp_2_bp_ADDR_2 717 +#define mx31_bp_2_bp_SIZE_2 112 + +#define mx31_ap_2_bp_ADDR_2 829 +#define mx31_ap_2_bp_SIZE_2 200 + +#define mx31_bp_2_ap_ADDR_2 1029 +#define mx31_bp_2_ap_SIZE_2 223 + +#define mx31_app_2_mcu_ADDR_2 6212 +#define mx31_app_2_mcu_SIZE_2 104 + +#define mx31_mcu_2_app_ADDR_2 6735 +#define mx31_mcu_2_app_SIZE_2 129 + +#define mx31_uart_2_mcu_ADDR_2 7736 +#define mx31_uart_2_mcu_SIZE_2 106 + +#define mx31_uartsh_2_mcu_ADDR_2 7842 +#define mx31_uartsh_2_mcu_SIZE_2 99 + +#define mx31_mcu_2_shp_ADDR_2 7076 +#define mx31_mcu_2_shp_SIZE_2 125 + +#define mx31_shp_2_mcu_ADDR_2 7523 +#define mx31_shp_2_mcu_SIZE_2 104 + +#define mx31_error_ADDR_2 1907 +#define mx31_error_SIZE_2 73 + +#define mx31_test_ADDR_2 1980 +#define mx31_test_SIZE_2 63 + +#define mx31_signature_ADDR_2 1023 +#define mx31_signature_SIZE_2 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define mx31_ap_2_ap_fixed_addr_ADDR_2 6144 +#define mx31_ap_2_ap_fixed_addr_SIZE_2 68 + +#define mx31_app_2_per_ADDR_2 6316 +#define mx31_app_2_per_SIZE_2 105 + +#define mx31_ata_2_mcu_ADDR_2 6421 +#define mx31_ata_2_mcu_SIZE_2 110 + +#define mx31_firi_2_mcu_ADDR_2 6531 +#define mx31_firi_2_mcu_SIZE_2 114 + +#define mx31_loop_DMAs_fixed_addr_ADDR_2 6645 +#define mx31_loop_DMAs_fixed_addr_SIZE_2 90 + +#define mx31_mcu_2_ata_ADDR_2 6864 +#define mx31_mcu_2_ata_SIZE_2 87 + +#define mx31_mcu_2_firi_ADDR_2 6951 +#define mx31_mcu_2_firi_SIZE_2 77 + +#define mx31_mcu_2_mshc_ADDR_2 7028 +#define mx31_mcu_2_mshc_SIZE_2 48 + +#define mx31_mshc_2_mcu_ADDR_2 7201 +#define mx31_mshc_2_mcu_SIZE_2 60 + +#define mx31_per_2_app_ADDR_2 7261 +#define mx31_per_2_app_SIZE_2 131 + +#define mx31_per_2_shp_ADDR_2 7392 +#define mx31_per_2_shp_SIZE_2 131 + +#define mx31_shp_2_per_ADDR_2 7627 +#define mx31_shp_2_per_SIZE_2 109 + +/*! +* SDMA RAM image start address and size +*/ + +#define MX31_RAM_CODE_START_ADDR_2 6144 +#define MX31_RAM_CODE_SIZE_2 1797 + +/*! +* Buffer that holds the SDMA RAM image +*/ + +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short mx31_sdma_code_2[] = { + 0x0970, 0x0111, 0x5111, 0x5ef9, 0xc0ec, 0x7d23, 0x5ad1, 0x5bd9, + 0xc0fe, 0x7c1f, 0x5ce1, 0x5de9, 0x5ef1, 0x08ff, 0x0011, 0x28ff, + 0x00bc, 0x048e, 0x56f9, 0x0660, 0x7d05, 0x0661, 0x7c2b, 0x6c07, + 0x6d13, 0x9821, 0x0661, 0x7d26, 0x6c17, 0x6d03, 0x028d, 0x058c, + 0x048a, 0xd9f5, 0x7e08, 0x7f07, 0x54e1, 0x52d1, 0x53d9, 0xc10d, + 0x7dde, 0x0200, 0x9804, 0x0660, 0x7d03, 0x6007, 0x52f1, 0x9832, + 0x6003, 0x52e9, 0x00a2, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07, + 0x6a2b, 0x6a28, 0x0007, 0x6a0c, 0x54e1, 0xc795, 0x048b, 0x0498, + 0x0454, 0x9825, 0x0800, 0x983c, 0x0870, 0x0011, 0x5010, 0xc0ec, + 0x7d61, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x984a, 0x6ec3, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d45, 0x0b70, 0x0311, 0x522b, 0x5313, 0x02b9, 0x4a00, + 0x7c04, 0x6a28, 0x7f3b, 0x0400, 0x985a, 0x008f, 0x00d5, 0x7d01, + 0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210, 0x4a00, 0x7d1c, + 0x4a02, 0x7d20, 0x4a01, 0x7d23, 0x0b70, 0x0311, 0x53eb, 0x62c8, + 0x7e25, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6a09, 0x7f1f, 0x0212, + 0x6a09, 0x7f1c, 0x0212, 0x6a09, 0x7f19, 0x2003, 0x4800, 0x7cef, + 0x0b70, 0x0311, 0x5313, 0x989b, 0x0015, 0x0015, 0x7802, 0x62c8, + 0x6a0b, 0x989a, 0x0015, 0x7802, 0x62c8, 0x6a0a, 0x989a, 0x7802, + 0x62c8, 0x6a09, 0x7c03, 0x6a28, 0x0000, 0x9858, 0xc77b, 0x6a28, + 0x7ffd, 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da2, + 0x0200, 0x984a, 0x0200, 0x9847, 0x0870, 0x0011, 0x5010, 0xc0ec, + 0x7d62, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x98b2, 0x6ec3, 0x6dd7, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d46, 0x0b70, 0x0311, 0x522b, 0x5313, 0x02b9, 0x4a00, + 0x7c04, 0x62ff, 0x7e3c, 0x0400, 0x98c2, 0x008f, 0x00d5, 0x7d01, + 0x008d, 0x05a0, 0x0a03, 0x0212, 0x02bc, 0x0210, 0x4a00, 0x7d28, + 0x4a02, 0x7d20, 0x4a01, 0x7d19, 0x6ddd, 0x0b70, 0x0311, 0x53eb, + 0x62c8, 0x7e25, 0x0360, 0x7d02, 0x0210, 0x0212, 0x6ac8, 0x7f1f, + 0x0212, 0x6ac8, 0x7f1c, 0x0212, 0x6ac8, 0x7f19, 0x2003, 0x4800, + 0x7cef, 0x0b70, 0x0311, 0x5313, 0x9905, 0x6ddd, 0x7802, 0x62c8, + 0x6ac8, 0x9904, 0x6dde, 0x0015, 0x7802, 0x62c8, 0x6ac8, 0x9904, + 0x0015, 0x0015, 0x7801, 0x62d8, 0x7c02, 0x0000, 0x98c0, 0xc777, + 0x62ff, 0x7efd, 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, + 0x7da1, 0x0200, 0x98b2, 0x0200, 0x98af, 0xc19d, 0xc0ec, 0x7d69, + 0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c, 0x58da, 0x5efa, 0xc0fe, + 0x56fa, 0x7d02, 0x0200, 0x991e, 0x6d07, 0x5bca, 0x5cd2, 0x0bff, + 0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da, 0x4c00, 0x7d47, 0x0a70, + 0x0211, 0x552a, 0x5212, 0x008d, 0x00bb, 0x4800, 0x7c07, 0x05b9, + 0x4d00, 0x7c13, 0x6928, 0x7f2d, 0x0400, 0x992f, 0x008f, 0x0015, + 0x04d8, 0x7d01, 0x008c, 0x04a0, 0x0015, 0x7802, 0x55c6, 0x6d0b, + 0x7e29, 0x6d28, 0x7f1e, 0x0000, 0x992d, 0x1e20, 0x5506, 0x2620, + 0x008d, 0x0560, 0x7c08, 0x065f, 0x55c6, 0x063f, 0x7e1b, 0x6d0a, + 0x7f10, 0x4c00, 0x7d1b, 0x04d8, 0x7d02, 0x008c, 0x0020, 0x04a0, + 0x0015, 0x7802, 0x55c6, 0x6d0b, 0x7e0d, 0x6d28, 0x7f02, 0x0000, + 0x9976, 0x0007, 0x680c, 0x6d0c, 0x6507, 0x6d07, 0x6d2b, 0x6d28, + 0x0007, 0x680c, 0x0007, 0x54d2, 0x0454, 0x9979, 0x6928, 0x7ff1, + 0x54d2, 0x008a, 0x52c0, 0x53c8, 0xc10d, 0x0288, 0x7d9f, 0x0200, + 0x991e, 0x0200, 0x9916, 0x1e10, 0x0870, 0x0011, 0x5010, 0xc0ec, + 0x7d39, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x998a, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, + 0x7d17, 0x6ec3, 0x62c8, 0x7e28, 0x0264, 0x7d08, 0x0b70, 0x0311, + 0x522b, 0x02b9, 0x4a00, 0x7c18, 0x0400, 0x9999, 0x0212, 0x3aff, + 0x008a, 0x05d8, 0x7d01, 0x008d, 0x0a10, 0x6ed3, 0x6ac8, 0xd9d4, + 0x6a28, 0x7f17, 0x0b70, 0x0311, 0x5013, 0xd9ec, 0x52c0, 0x53c8, + 0xc10d, 0x7dd0, 0x0200, 0x998a, 0x008f, 0x00d5, 0x7d01, 0x008d, + 0xd9d4, 0x9997, 0x0200, 0x9987, 0x0007, 0x68cc, 0x6a28, 0x7f01, + 0x99d2, 0x0007, 0x6a0c, 0x6a0c, 0x6207, 0x6a07, 0x6a2b, 0x6a28, + 0x0007, 0x680c, 0x0454, 0x99b0, 0x05a0, 0x1e08, 0x6ec3, 0x0388, + 0x3b03, 0x0015, 0x0015, 0x7802, 0x62c8, 0x6a0b, 0x7ee5, 0x6a28, + 0x7fe8, 0x0000, 0x6ec1, 0x008b, 0x7802, 0x62c8, 0x6a09, 0x7edc, + 0x6a28, 0x7fdf, 0x2608, 0x0006, 0x55f0, 0x6207, 0x02a5, 0x0dff, + 0x0511, 0x1dff, 0x04b5, 0x049a, 0x0006, 0x0388, 0x028d, 0x3a03, + 0x4a00, 0x7c33, 0x028c, 0x3a03, 0x4a00, 0x7d0c, 0x0804, 0x00a2, + 0x00db, 0x7d24, 0x03a0, 0x0498, 0x7802, 0x6209, 0x6a29, 0x7e24, + 0x620c, 0x7e22, 0x0804, 0x03d0, 0x7d19, 0x0820, 0x028c, 0x3a1f, + 0x00a2, 0x03d0, 0x7c02, 0x008b, 0x3003, 0x03a0, 0x0015, 0x0015, + 0x6818, 0x7e12, 0x6828, 0x7f10, 0x0000, 0x0820, 0x03d8, 0x7df5, + 0x0804, 0x03d0, 0x7d03, 0x008b, 0x3003, 0x9a15, 0x008b, 0x7802, + 0x6209, 0x6a29, 0x7e01, 0x620c, 0x0006, 0x0804, 0x03d0, 0x7df6, + 0x048b, 0x3403, 0x03a4, 0x0415, 0x0415, 0x0d0f, 0x0511, 0x1df0, + 0x0808, 0x04d0, 0x7c01, 0x008c, 0x58c1, 0x04a0, 0x7803, 0x620b, + 0x5a05, 0x1d01, 0x7ee9, 0x50c1, 0x05a0, 0x7803, 0x5205, 0x6a0b, + 0x1d01, 0x6a28, 0x7fe1, 0x0000, 0x4c00, 0x7ce7, 0x9a26, 0x0870, + 0x0011, 0x5010, 0xc0ec, 0x7d7a, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, + 0x56f8, 0x7d02, 0x0200, 0x9a55, 0x6d03, 0x6ed3, 0x0dff, 0x0511, + 0x1dff, 0x05bc, 0x5df8, 0x4d00, 0x7d5e, 0x0b70, 0x0311, 0x522b, + 0x5313, 0x02b9, 0x4a00, 0x7c04, 0x62ff, 0x7e3f, 0x0400, 0x9a65, + 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5ddb, 0x0d03, 0x0512, + 0x05bc, 0x0510, 0x5dd3, 0x4d00, 0x7d27, 0x4d02, 0x7d20, 0x4d01, + 0x7d1a, 0x0b70, 0x0311, 0x53eb, 0x0360, 0x7d05, 0x6509, 0x7e25, + 0x620a, 0x7e23, 0x9a8f, 0x620a, 0x7e20, 0x6509, 0x7e1e, 0x0512, + 0x0512, 0x02ad, 0x6ac8, 0x7f19, 0x2003, 0x4800, 0x7ced, 0x0b70, + 0x0311, 0x5313, 0x9aaa, 0x7802, 0x6209, 0x6ac8, 0x9aa9, 0x0015, + 0x7802, 0x620a, 0x6ac8, 0x9aa9, 0x0015, 0x0015, 0x7802, 0x620b, + 0x6ac8, 0x7c03, 0x0000, 0x55db, 0x9a63, 0x0007, 0x68cc, 0x680c, + 0x55d3, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9ab8, 0x0017, 0x0017, + 0x55db, 0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, + 0x04b8, 0x04ad, 0x0454, 0x62ff, 0x7ee8, 0x0870, 0x0011, 0x5010, + 0x52c0, 0x53c8, 0xc10d, 0x7d89, 0x0200, 0x9a55, 0x0200, 0x9a52, + 0xc19d, 0xc0ec, 0x7d52, 0x0c70, 0x0411, 0x5414, 0x5ac4, 0x028c, + 0x58da, 0x5efa, 0xc0fe, 0x56fa, 0x7d02, 0x0200, 0x9ad9, 0x6d03, + 0x5bca, 0x5cd2, 0x0bff, 0x0311, 0x1bff, 0x04bb, 0x0415, 0x53da, + 0x0a70, 0x0211, 0x4c00, 0x7d28, 0x552a, 0x05bb, 0x4d00, 0x7c02, + 0x0400, 0x9aec, 0x4c01, 0x7d0f, 0x008f, 0x0015, 0x04d8, 0x7d01, + 0x008c, 0x0020, 0x04a0, 0x0015, 0x7802, 0x650b, 0x5d06, 0x0000, + 0x7e0c, 0x7f0d, 0x9aea, 0x650a, 0x7e08, 0x008d, 0x0011, 0x0010, + 0x05a8, 0x065f, 0x5d06, 0x063f, 0x7f02, 0x0007, 0x680c, 0x0007, + 0x5012, 0x54d0, 0x0454, 0x9b16, 0x5012, 0x54d0, 0x0473, 0x7c06, + 0x552a, 0x05b9, 0x4d00, 0x7c02, 0x0400, 0x9b18, 0x52c0, 0x53c8, + 0xc10d, 0x0288, 0x7db6, 0x0200, 0x9ad9, 0x0200, 0x9ad1, 0x0870, + 0x0011, 0x5010, 0xc0ec, 0x7d46, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, + 0x56f8, 0x7d02, 0x0200, 0x9b2d, 0x0b70, 0x0311, 0x6ed3, 0x6d03, + 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d2b, 0x522b, 0x02b9, + 0x4a00, 0x7c04, 0x62c8, 0x7e1f, 0x0400, 0x9b3e, 0x008f, 0x00d5, + 0x7d01, 0x008d, 0x05a0, 0x0060, 0x7c05, 0x6edd, 0x6209, 0x7e16, + 0x6ac8, 0x7f11, 0x0015, 0x0060, 0x7c05, 0x6ede, 0x620a, 0x7e0e, + 0x6ac8, 0x7f09, 0x6edf, 0x0015, 0x7802, 0x620b, 0x6ac8, 0x0000, + 0x7e05, 0x7f01, 0x9b3c, 0x0007, 0x68cc, 0x9b68, 0x0007, 0x6a0c, + 0x0454, 0x62c8, 0x7ef8, 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7dbd, + 0x0200, 0x9b2d, 0x0200, 0x9b2a, 0xc19d, 0x0870, 0x0011, 0xc0ec, + 0x7d29, 0x5010, 0x5ac0, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9b7b, 0x0870, 0x0011, 0x6d03, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d12, 0x5228, 0x02b9, 0x4a00, 0x7c02, 0x0400, 0x9b8a, + 0x620b, 0x7e06, 0x5a06, 0x7f06, 0x0000, 0x2504, 0x7d05, 0x9b8a, + 0x0007, 0x680c, 0x0007, 0x0454, 0x5010, 0x52c0, 0xc10d, 0x7ddb, + 0x0200, 0x9b7b, 0x0200, 0x9b77, 0xc19d, 0x0870, 0x0011, 0xc0ec, + 0x7d76, 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, + 0x0200, 0x9bab, 0x6d03, 0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd0, + 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x5df8, 0x4d00, 0x7d57, 0x0a70, + 0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c02, 0x0400, 0x9bbf, + 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x5dda, 0x55d2, 0x4d00, + 0x7d27, 0x4d02, 0x7d20, 0x4d01, 0x7d1a, 0x0a70, 0x0211, 0x52ea, + 0x0260, 0x7d05, 0x6509, 0x7e25, 0x630a, 0x7e23, 0x9be3, 0x630a, + 0x7e20, 0x6509, 0x7e1e, 0x0512, 0x0512, 0x03ad, 0x5b06, 0x7f19, + 0x2003, 0x4800, 0x7ced, 0x0a70, 0x0211, 0x5212, 0x9bfe, 0x7802, + 0x6309, 0x5b06, 0x9bfd, 0x0015, 0x7802, 0x630a, 0x5b06, 0x9bfd, + 0x0015, 0x0015, 0x7802, 0x630b, 0x5b06, 0x7c03, 0x55da, 0x0000, + 0x9bbd, 0x0007, 0x680c, 0x55d2, 0x4d00, 0x7d03, 0x4d02, 0x7d02, + 0x9c0b, 0x0017, 0x0017, 0x55da, 0x009d, 0x55fa, 0x05a0, 0x08ff, + 0x0011, 0x18ff, 0x0010, 0x04b8, 0x04ad, 0x0454, 0x0870, 0x0011, + 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7d8e, 0x0200, 0x9bab, 0x0200, + 0x9ba7, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d35, 0x5010, 0x5ac0, + 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9c28, 0x0870, 0x0011, + 0x6d07, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d1c, 0x5228, + 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f0b, 0x0400, 0x9c37, 0x5206, + 0x7e10, 0x6a0b, 0x6928, 0x7f04, 0x0000, 0x2504, 0x7d0c, 0x9c37, + 0x0007, 0x680c, 0x680c, 0x6207, 0x6a07, 0x6a2b, 0x6a28, 0x0007, + 0x680c, 0x0007, 0x0454, 0x6928, 0x7ff3, 0x5010, 0x52c0, 0xc10d, + 0x7dcf, 0x0200, 0x9c28, 0x0200, 0x9c24, 0x0870, 0x0011, 0x5010, + 0xc0ec, 0x7d7c, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, + 0x0200, 0x9c63, 0x6ed3, 0x6dc5, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x5df8, 0x4d00, 0x7d60, 0x0b70, 0x0311, 0x522b, 0x5313, 0x02b9, + 0x4a00, 0x7c02, 0x0400, 0x9c73, 0x008f, 0x00d5, 0x7d01, 0x008d, + 0x05a0, 0x5ddb, 0x0d03, 0x0512, 0x05bc, 0x0510, 0x5dd3, 0x4d00, + 0x7d2c, 0x4d02, 0x7d24, 0x4d01, 0x7d1e, 0x59e3, 0x0b70, 0x0311, + 0x53eb, 0x61c8, 0x7e2b, 0x62c8, 0x7e29, 0x65c8, 0x7e27, 0x0360, + 0x7d03, 0x0112, 0x0112, 0x9c9e, 0x0512, 0x0512, 0x0211, 0x02a9, + 0x02ad, 0x6ac8, 0x7f1b, 0x2003, 0x4800, 0x7ceb, 0x0b70, 0x0311, + 0x5313, 0x51e3, 0x9cbb, 0x7802, 0x62c8, 0x6ac8, 0x9cba, 0x6dce, + 0x0015, 0x7802, 0x62c8, 0x6ac8, 0x9cba, 0x6dcf, 0x0015, 0x0015, + 0x7801, 0x62d8, 0x7c03, 0x0000, 0x55db, 0x9c71, 0x0007, 0x68ff, + 0x55d3, 0x4d00, 0x7d03, 0x4d02, 0x7d02, 0x9cc8, 0x0017, 0x0017, + 0x55db, 0x009d, 0x55fb, 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, + 0x04b8, 0x04ad, 0x0454, 0x62c8, 0x7ee9, 0x0870, 0x0011, 0x5010, + 0x52c0, 0x53c8, 0xc10d, 0x7d87, 0x0200, 0x9c63, 0x0200, 0x9c60, + 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d7c, 0x5010, 0x5ac0, 0x5bc8, + 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9ce7, 0x6dc5, 0x0d03, + 0x0512, 0x05bc, 0x0510, 0x5dd0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x5df8, 0x4d00, 0x7d5d, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9, + 0x4b00, 0x7c02, 0x0400, 0x9cfb, 0x008f, 0x05d8, 0x7d01, 0x008d, + 0x05a0, 0x5dda, 0x55d2, 0x4d00, 0x7d2c, 0x4d02, 0x7d24, 0x4d01, + 0x7d1e, 0x59e2, 0x0a70, 0x0211, 0x52ea, 0x61c8, 0x7e2c, 0x63c8, + 0x7e2a, 0x65c8, 0x7e28, 0x0260, 0x7d03, 0x0112, 0x0112, 0x9d22, + 0x0512, 0x0512, 0x0311, 0x03a9, 0x03ad, 0x5b06, 0x7f1c, 0x2003, + 0x4800, 0x7ceb, 0x0a70, 0x0211, 0x5212, 0x51e2, 0x9d40, 0x7802, + 0x63c8, 0x5b06, 0x9d3f, 0x6dce, 0x0015, 0x7802, 0x63c8, 0x5b06, + 0x9d3f, 0x6dcf, 0x0015, 0x0015, 0x7802, 0x63c8, 0x5b06, 0x7c03, + 0x55da, 0x0000, 0x9cf9, 0x0007, 0x68ff, 0x55d2, 0x4d00, 0x7d03, + 0x4d02, 0x7d02, 0x9d4d, 0x0017, 0x0017, 0x55da, 0x009d, 0x55fa, + 0x05a0, 0x08ff, 0x0011, 0x18ff, 0x0010, 0x04b8, 0x04ad, 0x0454, + 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7d88, 0x0200, + 0x9ce7, 0x0200, 0x9ce3, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d61, + 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9d6a, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, + 0x7d45, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c04, + 0x6a28, 0x7f3b, 0x0400, 0x9d79, 0x008f, 0x05d8, 0x7d01, 0x008d, + 0x05a0, 0x0b03, 0x0312, 0x03bc, 0x0310, 0x4b00, 0x7d1c, 0x4b02, + 0x7d20, 0x4b01, 0x7d23, 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e25, + 0x0260, 0x7d02, 0x0310, 0x0312, 0x6b09, 0x7f1f, 0x0312, 0x6b09, + 0x7f1c, 0x0312, 0x6b09, 0x7f19, 0x2003, 0x4800, 0x7cef, 0x0a70, + 0x0211, 0x5212, 0x9dba, 0x0015, 0x0015, 0x7802, 0x5306, 0x6b0b, + 0x9db9, 0x0015, 0x7802, 0x5306, 0x6b0a, 0x9db9, 0x7802, 0x5306, + 0x6b09, 0x7c03, 0x6b28, 0x0000, 0x9d77, 0xc77b, 0x6928, 0x7ffd, + 0x0870, 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da3, 0x0200, + 0x9d6a, 0x0200, 0x9d66, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d60, + 0x5010, 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, + 0x9dd2, 0x6dd7, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, + 0x7d46, 0x0a70, 0x0211, 0x532a, 0x5212, 0x03b9, 0x4b00, 0x7c02, + 0x0400, 0x9de1, 0x008f, 0x05d8, 0x7d01, 0x008d, 0x05a0, 0x0b03, + 0x0312, 0x03bc, 0x0310, 0x4b00, 0x7d28, 0x4b02, 0x7d20, 0x4b01, + 0x7d19, 0x6ddd, 0x0a70, 0x0211, 0x52ea, 0x5306, 0x7e27, 0x0260, + 0x7d02, 0x0310, 0x0312, 0x6bc8, 0x7f21, 0x0312, 0x6bc8, 0x7f1e, + 0x0312, 0x6bc8, 0x7f1b, 0x2003, 0x4800, 0x7cef, 0x0a70, 0x0211, + 0x5212, 0x9e23, 0x6ddd, 0x7802, 0x5306, 0x6bc8, 0x9e22, 0x6dde, + 0x0015, 0x7802, 0x5306, 0x6bc8, 0x9e22, 0x0015, 0x0015, 0x7802, + 0x5306, 0x6bc8, 0x7c03, 0x0000, 0xde32, 0x9ddf, 0xc777, 0x0870, + 0x0011, 0x5010, 0x52c0, 0x53c8, 0xc10d, 0x7da4, 0x0200, 0x9dd2, + 0x0200, 0x9dce, 0x63ff, 0x0368, 0x7d02, 0x0369, 0x7def, 0x0006, + 0x0870, 0x0011, 0x5010, 0xc0ec, 0x7d5c, 0x5ac0, 0x5bc8, 0x5ef8, + 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9e3e, 0x0b70, 0x0311, 0x6ec3, + 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x4d00, 0x7d3e, + 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x6a28, 0x7f34, 0x0400, 0x9e50, + 0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1b, 0x1e94, 0x6ec3, + 0x6ed3, 0x62c8, 0x0248, 0x6ac8, 0x2694, 0x6ec3, 0x62c8, 0x026e, + 0x7d32, 0x6a09, 0x7f1f, 0x2501, 0x4d00, 0x7d20, 0x028e, 0x1a98, + 0x6ac3, 0x62c8, 0x6ec3, 0x0260, 0x7df1, 0x6a28, 0x7f13, 0xc7af, + 0x9e90, 0x6ee3, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x62c8, 0x026e, 0x7d18, 0x6a09, 0x7f05, 0x2001, 0x7cf9, 0x6a28, + 0x0000, 0x9e4e, 0x0289, 0xc77b, 0x018a, 0x9e9f, 0x6a28, 0x7ffa, + 0x0b70, 0x0311, 0x5013, 0x52c0, 0x53c8, 0xc10d, 0x7da7, 0x0200, + 0x9e3e, 0x0200, 0x9e3b, 0x6a28, 0x7fed, 0xc7af, 0x9e9f, 0x0458, + 0x0454, 0x9e90, 0xc19d, 0x0870, 0x0011, 0xc0ec, 0x7d55, 0x5010, + 0x5ac0, 0x5bc8, 0x5ef8, 0xc0fe, 0x56f8, 0x7d02, 0x0200, 0x9ea9, + 0x0b70, 0x0311, 0x6d07, 0x5df0, 0x0dff, 0x0511, 0x1dff, 0x05bc, + 0x4d00, 0x7d37, 0x522b, 0x02b9, 0x4a00, 0x7c04, 0x6928, 0x7f2d, + 0x0400, 0x9eba, 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d16, 0x1e94, + 0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d2f, 0x6a09, + 0x7f1c, 0x2501, 0x4d00, 0x7d1d, 0x028e, 0x1a98, 0x5202, 0x0260, + 0x7df3, 0x6a28, 0x7f12, 0xc7af, 0x9ef3, 0x008f, 0x2001, 0x00d5, + 0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d18, 0x6a09, 0x7f05, + 0x2001, 0x7cf9, 0x6a28, 0x0000, 0x9eb8, 0x0289, 0xc77b, 0x018a, + 0x9f02, 0x6928, 0x7ffa, 0x0b70, 0x0311, 0x5013, 0x52c0, 0x53c8, + 0xc10d, 0x7daf, 0x0200, 0x9ea9, 0x0200, 0x9ea5, 0x6a28, 0x7fed, + 0xc7af, 0x9f02, 0x0458, 0x0454, 0x9ef3 +}; +#endif diff --git a/arch/arm/mach-mx3/mx35_3ds-irq.c b/arch/arm/mach-mx3/mx35_3ds-irq.c new file mode 100644 index 000000000000..f9f7e6f001ef --- /dev/null +++ b/arch/arm/mach-mx3/mx35_3ds-irq.c @@ -0,0 +1,381 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "mach/board-mx35pdk.h" + +/*! + * @file mach-mx35/mx35_3stack_irq.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX35 + */ + +/* + * The interrupt status and mask variables. + */ +static unsigned long pseudo_irq_pending; +static unsigned long pseudo_irq_enable; +static unsigned long pseudo_irq_wakeup; +static unsigned long pseudo_suspend; +static atomic_t pseudo_irq_state = ATOMIC_INIT(0); + +/* + * The declaration of handler of two work queue. + * The one is the work queue to indentify the events from MCU. + * The another is the work queue to change the events mask. + */ +static void mcu_event_handler(struct work_struct *work); +static void mcu_state_handler(struct work_struct *work); +static void mcu_event_delay(unsigned long data); + +/*! + * The work structure for mcu events. + */ +static DECLARE_WORK(mcu_event_ws, mcu_event_handler); +static DECLARE_WORK(mcu_state_ws, mcu_state_handler); +static DEFINE_TIMER(mcu_delay_timer, mcu_event_delay, HZ, 0); + +static inline void mxc_pseudo_irq_ack(void) +{ + disable_irq(MXC_PSEUDO_PARENT); + atomic_set(&pseudo_irq_state, 0); +} + +static inline void mxc_pseudo_irq_trigger(void) +{ + if (!atomic_xchg(&pseudo_irq_state, 1)) + enable_irq(MXC_PSEUDO_PARENT); +} + +/* + * mask a pseudo interrupt by setting the bit in the mask variable. + * @param irq a pseudo virtual irq number + */ +static void pseudo_mask_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + clear_bit(index, &pseudo_irq_enable); +} + +/* + * disable a pseudo interrupt by triggerring a work queue + * @param irq a pseudo virtual irq number + */ +static void pseudo_disable_irq(u32 irq) +{ + struct irq_desc *desc = irq_desc + irq; + desc->chip->mask(irq); + desc->status |= IRQ_MASKED; + schedule_work(&mcu_state_ws); +} + +/* + * Acknowledge a pseudo interrupt by clearing the bit in the isr variable. + * @param irq a pseudo virtual irq number + */ +static void pseudo_ack_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + /* clear the interrupt status */ + clear_bit(index, &pseudo_irq_pending); +} + +/* + * unmask a pseudo interrupt by clearing the bit in the imr. + * @param irq a pseudo virtual irq number + */ +static void pseudo_unmask_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + + set_bit(index, &pseudo_irq_enable); + + if (test_bit(index, &pseudo_irq_pending)) + mxc_pseudo_irq_trigger(); +} + +/* + * Enable a pseudo interrupt by triggerring a work queue + * @param irq a pseudo virtual irq number + */ +static void pseudo_enable_irq(u32 irq) +{ + struct irq_desc *desc = irq_desc + irq; + desc->chip->unmask(irq); + desc->status &= ~IRQ_MASKED; + schedule_work(&mcu_state_ws); +} + +/* + * set pseudo irq as a wake-up source. + * @param irq a pseudo virtual irq number + * @param enable enable as wake-up if equal to non-ero + * @return This function return 0 on success + */ +static int pseudo_set_wake_irq(u32 irq, u32 enable) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + + if (index >= 16) + return -ENODEV; + + if (enable) { + if (!pseudo_irq_wakeup) + enable_irq_wake(gpio_to_irq(0)); + pseudo_irq_wakeup |= (1 << index); + } else { + pseudo_irq_wakeup &= ~(1 << index); + if (!pseudo_irq_wakeup) + disable_irq_wake(gpio_to_irq(0)); + } + return 0; +} + +static struct irq_chip pseudo_irq_chip = { + .ack = pseudo_ack_irq, + .mask = pseudo_mask_irq, + .disable = pseudo_disable_irq, + .unmask = pseudo_unmask_irq, + .enable = pseudo_enable_irq, + .set_wake = pseudo_set_wake_irq, +}; + +static void mxc_pseudo_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 pseudo_irq; + u32 index, mask; + + desc->chip->mask(irq); + mxc_pseudo_irq_ack(); + + mask = pseudo_irq_enable; + index = pseudo_irq_pending; + + if (unlikely(!(index & mask))) { + printk(KERN_ERR "\nPseudo IRQ: Spurious interrupt:0x%0x\n\n", + index); + pr_info("IEN=0x%x, PENDING=0x%x\n", mask, index); + return; + } + + index = index & mask; + pseudo_irq = MXC_PSEUDO_IO_BASE; + for (; index != 0; index >>= 1, pseudo_irq++) { + struct irq_desc *d; + if ((index & 1) == 0) + continue; + d = irq_desc + pseudo_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nPseudo irq: %d unhandeled\n", + pseudo_irq); + BUG(); /* oops */ + } + d->handle_irq(pseudo_irq, d); + d->chip->ack(pseudo_irq); + } +} + +static void mcu_event_delay(unsigned long data) +{ + schedule_work(&mcu_event_ws); +} + +/*! + * This function is called when mcu interrupt occurs on the processor. + * It is the interrupt handler for the mcu. + * + * @param irq the irq number + * @param dev_id the pointer on the device + * + * @return The function returns IRQ_HANDLED when handled. + */ +static irqreturn_t mcu_irq_handler(int irq, void *dev_id) +{ + disable_irq_nosync(gpio_to_irq(0)); + if (pseudo_suspend) + mod_timer(&mcu_delay_timer, jiffies + HZ); + else + schedule_work(&mcu_event_ws); + + return IRQ_HANDLED; +} + +/*! + * This function is the work handler of mcu interrupt. + * It reads the events status and trigger the pseudo irq. + */ +static void mcu_event_handler(struct work_struct *work) +{ + int i, err; + unsigned int flag1, flag2; + + /* read int flags and ack int */ + for (i = 0; i < 3; i++) { +#if FIXME + err = mcu_pmic_read_reg(REG_MCU_INT_FLAG_1, &flag1, 0xFFFFFFFF); + err |= mcu_pmic_read_reg(REG_MCU_INT_FLAG_2, + &flag2, 0xFFFFFFFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_FLAG_1, 0, 0xFFFFFFFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_FLAG_2, 0, 0xFFFFFFFF); +#endif + if (err == 0) + break; + } + + if (i >= 3) { + printk(KERN_ERR "Reads MCU event fail\n"); + goto no_new_events; + } + + for (i = 0; flag1 && (i < MCU_INT_RTC); i++, flag1 >>= 1) + if (flag1 & 1) + set_bit(i, &pseudo_irq_pending); + + for (i = MCU_INT_RTC; flag2 && (i <= MCU_INT_KEYPAD); i++, flag2 >>= 1) + if (flag2 & 1) + set_bit(i, &pseudo_irq_pending); + no_new_events: + if (pseudo_irq_pending & pseudo_irq_enable) + mxc_pseudo_irq_trigger(); + enable_irq(gpio_to_irq(0)); +} + +static void mcu_state_handler(struct work_struct *work) +{ + int err, i; + unsigned int event1, event2; + event1 = pseudo_irq_enable & ((1 << MCU_INT_RTC) - 1); + event2 = pseudo_irq_enable >> MCU_INT_RTC; + +#if FIXME + if (is_suspend_ops_started()) + return; +#endif + + for (i = 0; i < 3; i++) { +#if FIXME + err = mcu_pmic_write_reg(REG_MCU_INT_ENABLE_1, event1, 0xFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_ENABLE_2, event2, 0xFF); +#endif + if (err == 0) + break; + } + if (i >= 3) + printk(KERN_ERR "Change MCU event mask fail\n"); +} + +static int __init mxc_pseudo_init(void) +{ + int i; + + /* disable the interrupt and clear the status */ + pseudo_irq_pending = 0; + pseudo_irq_enable = 0; + + pr_info("3-Stack Pseudo interrupt rev=0.1v\n"); + + for (i = MXC_PSEUDO_IO_BASE; + i < (MXC_PSEUDO_IO_BASE + 16); i++) { + set_irq_chip(i, &pseudo_irq_chip); + set_irq_handler(i, handle_simple_irq); + set_irq_flags(i, IRQF_VALID); + } + + set_irq_flags(MXC_PSEUDO_PARENT, IRQF_NOAUTOEN); + set_irq_handler(MXC_PSEUDO_PARENT, mxc_pseudo_irq_handler); + + /* Set and install PMIC IRQ handler */ + gpio_request(0, NULL); + gpio_direction_input(0); + + set_irq_type(gpio_to_irq(0), IRQF_TRIGGER_RISING); + if (request_irq(gpio_to_irq(0), mcu_irq_handler, + 0, "MCU_IRQ", 0)) { + printk(KERN_ERR "mcu request irq failed\n"); + return -1; + } + return 0; +} + +fs_initcall_sync(mxc_pseudo_init); + +static int mxc_pseudo_irq_suspend(struct platform_device *dev, + pm_message_t mesg) +{ + int err, i; + unsigned int event1, event2; + + if (!pseudo_irq_wakeup) + return 0; + + event1 = pseudo_irq_wakeup & ((1 << MCU_INT_RTC) - 1); + event2 = pseudo_irq_wakeup >> MCU_INT_RTC; + + for (i = 0; i < 3; i++) { +#if FIXME + err = mcu_pmic_write_reg(REG_MCU_INT_ENABLE_1, event1, 0xFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_ENABLE_2, event2, 0xFF); +#endif + if (err == 0) + break; + } + pseudo_suspend = 1; + return err; +} + +static int mxc_pseudo_irq_resume(struct platform_device *dev) +{ + if (!pseudo_irq_wakeup) + return 0; + + schedule_work(&mcu_state_ws); + pseudo_suspend = 0; + return 0; +} + +static struct platform_driver mxc_pseudo_irq_driver = { + .driver = { + .name = "mxc_pseudo_irq", + }, + .suspend = mxc_pseudo_irq_suspend, + .resume = mxc_pseudo_irq_resume, +}; + +static int __init mxc_pseudo_sysinit(void) +{ + return platform_driver_register(&mxc_pseudo_irq_driver); +} + +late_initcall(mxc_pseudo_sysinit); diff --git a/arch/arm/mach-mx3/mx35_3ds_pesudo_irq.c b/arch/arm/mach-mx3/mx35_3ds_pesudo_irq.c new file mode 100644 index 000000000000..cc9e330edf17 --- /dev/null +++ b/arch/arm/mach-mx3/mx35_3ds_pesudo_irq.c @@ -0,0 +1,372 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "mach/board-mx35_3ds.h" + +/*! + * @file mach-mx35/mx35_3stack_irq.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX35 + */ + +/* + * The interrupt status and mask variables. + */ +static unsigned long pseudo_irq_pending; +static unsigned long pseudo_irq_enable; +static unsigned long pseudo_irq_wakeup; +static unsigned long pseudo_suspend; +static atomic_t pseudo_irq_state = ATOMIC_INIT(0); + +/* + * The declaration of handler of two work queue. + * The one is the work queue to indentify the events from MCU. + * The another is the work queue to change the events mask. + */ +static void mcu_event_handler(struct work_struct *work); +static void mcu_state_handler(struct work_struct *work); +static void mcu_event_delay(unsigned long data); + +/*! + * The work structure for mcu events. + */ +static DECLARE_WORK(mcu_event_ws, mcu_event_handler); +static DECLARE_WORK(mcu_state_ws, mcu_state_handler); +static DEFINE_TIMER(mcu_delay_timer, mcu_event_delay, HZ, 0); + +static inline void mxc_pseudo_irq_ack(void) +{ + disable_irq(MXC_PSEUDO_PARENT); + atomic_set(&pseudo_irq_state, 0); +} + +static inline void mxc_pseudo_irq_trigger(void) +{ + if (!atomic_xchg(&pseudo_irq_state, 1)) + enable_irq(MXC_PSEUDO_PARENT); +} + +/* + * mask a pseudo interrupt by setting the bit in the mask variable. + * @param irq a pseudo virtual irq number + */ +static void pseudo_mask_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + clear_bit(index, &pseudo_irq_enable); +} + +/* + * disable a pseudo interrupt by triggerring a work queue + * @param irq a pseudo virtual irq number + */ +static void pseudo_disable_irq(u32 irq) +{ + struct irq_desc *desc = irq_desc + irq; + desc->chip->mask(irq); + desc->status |= IRQ_MASKED; + schedule_work(&mcu_state_ws); +} + +/* + * Acknowledge a pseudo interrupt by clearing the bit in the isr variable. + * @param irq a pseudo virtual irq number + */ +static void pseudo_ack_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + /* clear the interrupt status */ + clear_bit(index, &pseudo_irq_pending); +} + +/* + * unmask a pseudo interrupt by clearing the bit in the imr. + * @param irq a pseudo virtual irq number + */ +static void pseudo_unmask_irq(u32 irq) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + + set_bit(index, &pseudo_irq_enable); + + if (test_bit(index, &pseudo_irq_pending)) + mxc_pseudo_irq_trigger(); +} + +/* + * Enable a pseudo interrupt by triggerring a work queue + * @param irq a pseudo virtual irq number + */ +static void pseudo_enable_irq(u32 irq) +{ + struct irq_desc *desc = irq_desc + irq; + desc->chip->unmask(irq); + desc->status &= ~IRQ_MASKED; + schedule_work(&mcu_state_ws); +} + +/* + * set pseudo irq as a wake-up source. + * @param irq a pseudo virtual irq number + * @param enable enable as wake-up if equal to non-ero + * @return This function return 0 on success + */ +static int pseudo_set_wake_irq(u32 irq, u32 enable) +{ + int index = irq - MXC_PSEUDO_IO_BASE; + + if (index >= 16) + return -ENODEV; + + if (enable) { + if (!pseudo_irq_wakeup) + enable_irq_wake(gpio_to_irq(0)); + pseudo_irq_wakeup |= (1 << index); + } else { + pseudo_irq_wakeup &= ~(1 << index); + if (!pseudo_irq_wakeup) + disable_irq_wake(gpio_to_irq(0)); + } + return 0; +} + +static struct irq_chip pseudo_irq_chip = { + .ack = pseudo_ack_irq, + .mask = pseudo_mask_irq, + .disable = pseudo_disable_irq, + .unmask = pseudo_unmask_irq, + .enable = pseudo_enable_irq, + .set_wake = pseudo_set_wake_irq, +}; + +static void mxc_pseudo_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 pseudo_irq; + u32 index, mask; + + desc->chip->mask(irq); + mxc_pseudo_irq_ack(); + + mask = pseudo_irq_enable; + index = pseudo_irq_pending; + + if (unlikely(!(index & mask))) { + printk(KERN_ERR "\nPseudo IRQ: Spurious interrupt:0x%0x\n\n", + index); + pr_info("IEN=0x%x, PENDING=0x%x\n", mask, index); + return; + } + + index = index & mask; + pseudo_irq = MXC_PSEUDO_IO_BASE; + for (; index != 0; index >>= 1, pseudo_irq++) { + struct irq_desc *d; + if ((index & 1) == 0) + continue; + d = irq_desc + pseudo_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nPseudo irq: %d unhandeled\n", + pseudo_irq); + BUG(); /* oops */ + } + d->handle_irq(pseudo_irq, d); + d->chip->ack(pseudo_irq); + } +} + +static void mcu_event_delay(unsigned long data) +{ + schedule_work(&mcu_event_ws); +} + +/*! + * This function is called when mcu interrupt occurs on the processor. + * It is the interrupt handler for the mcu. + * + * @param irq the irq number + * @param dev_id the pointer on the device + * + * @return The function returns IRQ_HANDLED when handled. + */ +static irqreturn_t mcu_irq_handler(int irq, void *dev_id) +{ + disable_irq_nosync(gpio_to_irq(0)); + if (pseudo_suspend) + mod_timer(&mcu_delay_timer, jiffies + HZ); + else + schedule_work(&mcu_event_ws); + + return IRQ_HANDLED; +} + +/*! + * This function is the work handler of mcu interrupt. + * It reads the events status and trigger the pseudo irq. + */ +static void mcu_event_handler(struct work_struct *work) +{ + int i, err; + unsigned int flag1, flag2; + + /* read int flags and ack int */ + for (i = 0; i < 3; i++) { + err = mcu_pmic_read_reg(REG_MCU_INT_FLAG_1, &flag1, 0xFFFFFFFF); + err |= mcu_pmic_read_reg(REG_MCU_INT_FLAG_2, + &flag2, 0xFFFFFFFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_FLAG_1, 0, 0xFFFFFFFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_FLAG_2, 0, 0xFFFFFFFF); + if (err == 0) + break; + } + + if (i >= 3) { + printk(KERN_ERR "Reads MCU event fail\n"); + goto no_new_events; + } + + for (i = 0; flag1 && (i < MCU_INT_RTC); i++, flag1 >>= 1) + if (flag1 & 1) + set_bit(i, &pseudo_irq_pending); + + for (i = MCU_INT_RTC; flag2 && (i <= MCU_INT_KEYPAD); i++, flag2 >>= 1) + if (flag2 & 1) + set_bit(i, &pseudo_irq_pending); +no_new_events: + if (pseudo_irq_pending & pseudo_irq_enable) + mxc_pseudo_irq_trigger(); + enable_irq(gpio_to_irq(0)); +} + +static void mcu_state_handler(struct work_struct *work) +{ + int err, i; + unsigned int event1, event2; + event1 = pseudo_irq_enable & ((1 << MCU_INT_RTC) - 1); + event2 = pseudo_irq_enable >> MCU_INT_RTC; + + if (is_suspend_ops_started()) + return; + + for (i = 0; i < 3; i++) { + err = mcu_pmic_write_reg(REG_MCU_INT_ENABLE_1, event1, 0xFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_ENABLE_2, event2, 0xFF); + if (err == 0) + break; + } + if (i >= 3) + printk(KERN_ERR "Change MCU event mask fail\n"); +} + +static int __init mxc_pseudo_init(void) +{ + int i; + + /* disable the interrupt and clear the status */ + pseudo_irq_pending = 0; + pseudo_irq_enable = 0; + + pr_info("3-Stack Pseudo interrupt rev=0.1v\n"); + + for (i = MXC_PSEUDO_IO_BASE; + i < (MXC_PSEUDO_IO_BASE + 16); i++) { + set_irq_chip(i, &pseudo_irq_chip); + set_irq_handler(i, handle_simple_irq); + set_irq_flags(i, IRQF_VALID); + } + + set_irq_flags(MXC_PSEUDO_PARENT, IRQF_NOAUTOEN); + set_irq_handler(MXC_PSEUDO_PARENT, mxc_pseudo_irq_handler); + + /* Set and install PMIC IRQ handler */ + gpio_request(0, NULL); + gpio_direction_input(0); + + set_irq_type(gpio_to_irq(0), IRQF_TRIGGER_RISING); + if (request_irq(gpio_to_irq(0), mcu_irq_handler, + 0, "MCU_IRQ", 0)) { + printk(KERN_ERR "mcu request irq failed\n"); + return -1; + } + return 0; +} + +fs_initcall_sync(mxc_pseudo_init); + +static int mxc_pseudo_irq_suspend(struct platform_device *dev, + pm_message_t mesg) +{ + int err, i; + unsigned int event1, event2; + + if (!pseudo_irq_wakeup) + return 0; + + event1 = pseudo_irq_wakeup & ((1 << MCU_INT_RTC) - 1); + event2 = pseudo_irq_wakeup >> MCU_INT_RTC; + + for (i = 0; i < 3; i++) { + err = mcu_pmic_write_reg(REG_MCU_INT_ENABLE_1, event1, 0xFF); + err |= mcu_pmic_write_reg(REG_MCU_INT_ENABLE_2, event2, 0xFF); + if (err == 0) + break; + } + pseudo_suspend = 1; + return err; +} + +static int mxc_pseudo_irq_resume(struct platform_device *dev) +{ + if (!pseudo_irq_wakeup) + return 0; + + schedule_work(&mcu_state_ws); + pseudo_suspend = 0; + return 0; +} + +static struct platform_driver mxc_pseudo_irq_driver = { + .driver = { + .name = "mxc_pseudo_irq", + }, + .suspend = mxc_pseudo_irq_suspend, + .resume = mxc_pseudo_irq_resume, +}; + +static int __init mxc_pseudo_sysinit(void) +{ + return platform_driver_register(&mxc_pseudo_irq_driver); +} + +late_initcall(mxc_pseudo_sysinit); diff --git a/arch/arm/mach-mx3/mx35_3ds_pmic_mc13892.c b/arch/arm/mach-mx3/mx35_3ds_pmic_mc13892.c new file mode 100644 index 000000000000..2199e85733c5 --- /dev/null +++ b/arch/arm/mach-mx3/mx35_3ds_pmic_mc13892.c @@ -0,0 +1,392 @@ +/* + * mx35-3stack-pmic-mc13892.c -- i.MX35 3STACK Driver for Atlas MC13892 PMIC + */ + /* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +#define STANDBYSECINV_LSH 11 +#define STANDBYSECINV_WID 1 + +/* regulator standby mask */ +#define GEN1_STBY_MASK (1 << 1) +#define IOHI_STBY_MASK (1 << 4) +#define DIG_STBY_MASK (1 << 10) +#define GEN2_STBY_MASK (1 << 13) +#define PLL_STBY_MASK (1 << 16) +#define USB2_STBY_MASK (1 << 19) + +#define GEN3_STBY_MASK (1 << 1) +#define CAM_STBY_MASK (1 << 7) +#define VIDEO_STBY_MASK (1 << 13) +#define AUDIO_STBY_MASK (1 << 16) +#define SD_STBY_MASK (1 << 19) + +/* 0x92412 */ +#define REG_MODE_0_ALL_MASK (GEN1_STBY_MASK | \ + IOHI_STBY_MASK | DIG_STBY_MASK | \ + GEN2_STBY_MASK | PLL_STBY_MASK | \ + USB2_STBY_MASK) +/* 0x92082 */ +#define REG_MODE_1_ALL_MASK (GEN3_STBY_MASK | \ + CAM_STBY_MASK | VIDEO_STBY_MASK | \ + AUDIO_STBY_MASK | SD_STBY_MASK) + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +static struct regulator_consumer_supply vcam_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDA", + .dev_name = "0-000a", + }, +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 700000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 1200000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + .state_standby = { + .uV = 1000000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .boot_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + }, + .num_consumer_supplies = ARRAY_SIZE(vcam_consumers), + .consumer_supplies = vcam_consumers, +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + } +}; + +static struct regulator_init_data pwg1_init = { + .constraints = { + .name = "PWG1", + } +}; + +static struct regulator_init_data pwg2_init = { + .constraints = { + .name = "PWG2", + } +}; + +/*! + * the event handler for power on event + */ +static void power_on_evt_handler(void) +{ + pr_info("pwr on event1 is received \n"); +} + +/*! + * pmic board initialization code + */ +static int init_mc13892(void) +{ + unsigned int value; + pmic_event_callback_t power_key_event; + + if (!board_is_rev(BOARD_REV_2)) + return -1; + + /* subscribe PWRON1 event. */ + power_key_event.param = NULL; + power_key_event.func = (void *)power_on_evt_handler; + pmic_event_subscribe(EVENT_PWRONI, power_key_event); + + pmic_read_reg(REG_POWER_CTL2, &value, 0xffffff); + /* Bit 11 (STANDBYSECINV): Active Low */ + value |= 0x00800; + /* Bit 12 (WDIRESET): enable */ + value |= 0x01000; + pmic_write_reg(REG_POWER_CTL2, value, 0xffffff); + + /* Battery charger default settings */ + /* current limit = 1200mA, PLIM = 1000mw, disable auto charge */ + value = 0x210068; + pmic_write_reg(REG_CHARGE, value, 0x018078); + + /* enable standby controll for regulators */ + pmic_read_reg(REG_MODE_0, &value, 0xffffff); + value &= ~REG_MODE_0_ALL_MASK; + value |= (DIG_STBY_MASK | PLL_STBY_MASK | \ + USB2_STBY_MASK); + pmic_write_reg(REG_MODE_0, value, 0xffffff); + + pmic_read_reg(REG_MODE_1, &value, 0xffffff); + value |= REG_MODE_1_ALL_MASK; + pmic_write_reg(REG_MODE_1, value, 0xffffff); + + return 0; +} + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + mc13892_register_regulator(mc13892, MC13892_PWGT1, &pwg1_init); + mc13892_register_regulator(mc13892, MC13892_PWGT2, &pwg2_init); + + init_mc13892(); + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct i2c_board_info __initdata mc13892_i2c_device = { + I2C_BOARD_INFO("mc13892", 0x08), + .irq = IOMUX_TO_IRQ(MX35_GPIO2_0), + .platform_data = &mc13892_plat, +}; + +int __init mx35_3stack_init_mc13892(void) +{ + return i2c_register_board_info(0, &mc13892_i2c_device, 1); +} diff --git a/arch/arm/mach-mx3/mx35_3ds_pmic_mc9s08dz60.c b/arch/arm/mach-mx3/mx35_3ds_pmic_mc9s08dz60.c new file mode 100644 index 000000000000..8428befdf0b3 --- /dev/null +++ b/arch/arm/mach-mx3/mx35_3ds_pmic_mc9s08dz60.c @@ -0,0 +1,105 @@ +/* + * mx35-3stack-pmic-mc9s08dz60.c -- i.MX35 3STACK Driver for MCU PMIC + */ + /* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static struct regulator_init_data lcd_init = { + .constraints = { + .name = "LCD", + } +}; + +static struct regulator_init_data wifi_init = { + .constraints = { + .name = "WIFI", + } +}; + +static struct regulator_init_data hdd_init = { + .constraints = { + .name = "HDD", + } +}; + +static struct regulator_init_data gps_init = { + .constraints = { + .name = "GPS", + } +}; + +static struct regulator_init_data spkr_init = { + .constraints = { + .name = "SPKR", + } +}; + +static int mc9s08dz60_regulator_init(struct mc9s08dz60 *mc9s08dz60) +{ + if (!board_is_rev(BOARD_REV_2)) + return 0; + + mc9s08dz60_register_regulator( + mc9s08dz60, MC9S08DZ60_LCD, &lcd_init); + mc9s08dz60_register_regulator(mc9s08dz60, + MC9S08DZ60_WIFI, &wifi_init); + mc9s08dz60_register_regulator( + mc9s08dz60, MC9S08DZ60_HDD, &hdd_init); + mc9s08dz60_register_regulator( + mc9s08dz60, MC9S08DZ60_GPS, &gps_init); + mc9s08dz60_register_regulator(mc9s08dz60, + MC9S08DZ60_SPKR, &spkr_init); + return 0; +} + +static struct mc9s08dz60_platform_data mc9s08dz60_plat = { + .init = mc9s08dz60_regulator_init, +}; + +static struct i2c_board_info __initdata mc9s08dz60_i2c_device = { + I2C_BOARD_INFO("mc9s08dz60", 0x69), + .platform_data = &mc9s08dz60_plat, +}; + +static struct resource mc9s08dz60_keypad_resource = { + .start = MXC_PSEUDO_IRQ_KEYPAD, + .end = MXC_PSEUDO_IRQ_KEYPAD, + .flags = IORESOURCE_IRQ, +}; + +static struct platform_device mc9s08dz60_keypad_dev = { + .name = "mc9s08dz60keypad", + .num_resources = 1, + .resource = &mc9s08dz60_keypad_resource, +}; + +int __init mx35_3stack_init_mc9s08dz60(void) +{ + int retval = 0; + retval = i2c_register_board_info(0, &mc9s08dz60_i2c_device, 1); + if (retval == 0) + platform_device_register(&mc9s08dz60_keypad_dev); + return retval; +} diff --git a/arch/arm/mach-mx3/mx35_sdma_script_code_v1.h b/arch/arm/mach-mx3/mx35_sdma_script_code_v1.h new file mode 100644 index 000000000000..908921158534 --- /dev/null +++ b/arch/arm/mach-mx3/mx35_sdma_script_code_v1.h @@ -0,0 +1,254 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SS15_RINGO" + +*******************************************************************************/ + +#ifndef __MX35_SDMA_SCRIPT_CODE_V1_H__ +#define __MX35_SDMA_SCRIPT_CODE_V1_H__ + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define mx35_start_ADDR 0 +#define mx35_start_SIZE 22 + +#define mx35_core_ADDR 80 +#define mx35_core_SIZE 232 + +#define mx35_common_ADDR 312 +#define mx35_common_SIZE 330 + +#define mx35_ap_2_ap_ADDR 642 +#define mx35_ap_2_ap_SIZE 41 + +#define mx35_app_2_mcu_ADDR 683 +#define mx35_app_2_mcu_SIZE 64 + +#define mx35_mcu_2_app_ADDR 747 +#define mx35_mcu_2_app_SIZE 70 + +#define mx35_uart_2_mcu_ADDR 817 +#define mx35_uart_2_mcu_SIZE 75 + +#define mx35_shp_2_mcu_ADDR 892 +#define mx35_shp_2_mcu_SIZE 69 + +#define mx35_mcu_2_shp_ADDR 961 +#define mx35_mcu_2_shp_SIZE 72 + +#define mx35_per_2_shp_ADDR 1033 +#define mx35_per_2_shp_SIZE 78 + +#define mx35_shp_2_per_ADDR 1111 +#define mx35_shp_2_per_SIZE 72 + +#define mx35_uartsh_2_mcu_ADDR 1183 +#define mx35_uartsh_2_mcu_SIZE 69 + +#define mx35_mcu_2_ata_ADDR 1252 +#define mx35_mcu_2_ata_SIZE 81 + +#define mx35_ata_2_mcu_ADDR 1333 +#define mx35_ata_2_mcu_SIZE 96 + +#define mx35_loop_DMAs_routines_ADDR 1429 +#define mx35_loop_DMAs_routines_SIZE 227 + +#define mx35_test_ADDR 1656 +#define mx35_test_SIZE 63 + +#define mx35_signature_ADDR 1023 +#define mx35_signature_SIZE 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define mx35_app_2_per_ADDR 6144 +#define mx35_app_2_per_SIZE 66 + +#define mx35_asrc__mcu_ADDR 6210 +#define mx35_asrc__mcu_SIZE 114 + +#define mx35_ext_mem__ipu_ram_ADDR 6324 +#define mx35_ext_mem__ipu_ram_SIZE 123 + +#define mx35_mcu_2_spdif_ADDR 6447 +#define mx35_mcu_2_spdif_SIZE 103 + +#define mx35_p_2_p_ADDR 6550 +#define mx35_p_2_p_SIZE 254 + +#define mx35_per_2_app_ADDR 6804 +#define mx35_per_2_app_SIZE 74 + +#define mx35_spdif_2_mcu_ADDR 6878 +#define mx35_spdif_2_mcu_SIZE 47 + +#define mx35_uart_2_per_ADDR 6925 +#define mx35_uart_2_per_SIZE 73 + +#define mx35_uartsh_2_per_ADDR 6998 +#define mx35_uartsh_2_per_SIZE 67 + +/*! +* SDMA RAM image start address and size +*/ + +#define MX35_RAM_CODE_START_ADDR 6144 +#define MX35_RAM_CODE_SIZE 921 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short mx35_sdma_code[] = { + 0xc1e3, 0x57db, 0x52fb, 0x6ac3, 0x52f3, 0x6ad7, 0x008f, 0x00d5, + 0x7d01, 0x008d, 0x05a0, 0x0478, 0x7d03, 0x0479, 0x7d1c, 0x7c21, + 0x0479, 0x7c14, 0x6ddd, 0x56ee, 0x62c8, 0x7e28, 0x0660, 0x7d02, + 0x0210, 0x0212, 0x6ac8, 0x7f22, 0x0212, 0x6ac8, 0x7f1f, 0x0212, + 0x6ac8, 0x7f1c, 0x2003, 0x4800, 0x7cef, 0x9836, 0x6ddd, 0x7802, + 0x62c8, 0x6ac8, 0x9835, 0x6dde, 0x0015, 0x7802, 0x62c8, 0x6ac8, + 0x9835, 0x0015, 0x0015, 0x7801, 0x62d8, 0x7c08, 0x6ddf, 0x7f06, + 0x0000, 0x4d00, 0x7d05, 0xc1fa, 0x57db, 0x9806, 0xc273, 0x0454, + 0xc20a, 0x9801, 0xc1d9, 0xc1e3, 0x56f3, 0x57db, 0x047a, 0x7d07, + 0x072f, 0x076e, 0x7d02, 0x6ec7, 0x9855, 0x6ed7, 0x9855, 0x074f, + 0x076e, 0x7d02, 0x6e01, 0x9855, 0x6e05, 0x5ce3, 0x048f, 0x0410, + 0x3c0f, 0x5c93, 0x0eff, 0x06bf, 0x06d5, 0x7d01, 0x068d, 0x05a6, + 0x5deb, 0x55fb, 0x008e, 0x0768, 0x7d02, 0x0769, 0x7c04, 0x06d4, + 0x7d01, 0x008c, 0x04a0, 0x06a0, 0x076f, 0x7d0c, 0x076e, 0x7d05, + 0x7802, 0x62c8, 0x5a05, 0x7c2b, 0x9887, 0x7802, 0x5205, 0x6ac8, + 0x7c26, 0x9887, 0x076e, 0x7d05, 0x7802, 0x620b, 0x5a05, 0x7c21, + 0x9887, 0x7802, 0x5205, 0x6a0b, 0x7c1c, 0x6a28, 0x7f1a, 0x0768, + 0x7d02, 0x0769, 0x7c0a, 0x4c00, 0x7c08, 0x0768, 0x7d03, 0x5a05, + 0x7f11, 0x9894, 0x5205, 0x7e0e, 0x5493, 0x4e00, 0x7ccb, 0x0000, + 0x54e3, 0x55eb, 0x4d00, 0x7d0a, 0xc1fa, 0x57db, 0x9856, 0x68cc, + 0x98a2, 0x680c, 0x009e, 0x0007, 0x54e3, 0xd8a8, 0xc20a, 0x9844, + 0x55eb, 0x009d, 0x058c, 0x0aff, 0x0211, 0x1aff, 0x05ba, 0x05a0, + 0x04b2, 0x04ad, 0x0454, 0x0006, 0x0e70, 0x0611, 0x5616, 0xc13c, + 0x7d2a, 0x5ade, 0x008e, 0xc14e, 0x7c26, 0x5be0, 0x5ef0, 0x5ce8, + 0x0688, 0x08ff, 0x0011, 0x28ff, 0x00bc, 0x53f6, 0x05df, 0x7d0b, + 0x6dc5, 0x03df, 0x7d03, 0x6bd5, 0xd903, 0x98df, 0x6b05, 0xc5f5, + 0x7e27, 0x7f29, 0x98df, 0x6d01, 0x03df, 0x7d05, 0x6bd5, 0xc61f, + 0x7e18, 0x7f1a, 0x98df, 0x6b05, 0xc595, 0x7e07, 0x7f06, 0x52de, + 0x53e6, 0xc159, 0x7dd7, 0x0200, 0x98b7, 0x0007, 0x6004, 0x680c, + 0x53f6, 0x028e, 0x00a3, 0xc256, 0x048b, 0x0498, 0x0454, 0x068a, + 0x98df, 0x0207, 0x680c, 0x6ddf, 0x0107, 0x68ff, 0x60d0, 0x98e8, + 0x0207, 0x68ff, 0x6d28, 0x0107, 0x6004, 0x680c, 0x98e8, 0x0007, + 0x68ff, 0x60d0, 0x98e8, 0x0288, 0x03a5, 0x3b03, 0x3d03, 0x4d00, + 0x7d0a, 0x0804, 0x00a5, 0x00da, 0x7d1a, 0x02a0, 0x7b01, 0x65d8, + 0x7eee, 0x65ff, 0x7eec, 0x0804, 0x02d0, 0x7d11, 0x4b00, 0x7c0f, + 0x008a, 0x3003, 0x6dcf, 0x6bdf, 0x0015, 0x0015, 0x7b02, 0x65d8, + 0x0000, 0x7edd, 0x63ff, 0x7edb, 0x3a03, 0x6dcd, 0x6bdd, 0x008a, + 0x7b02, 0x65d8, 0x0000, 0x7ed3, 0x65ff, 0x7ed1, 0x0006, 0xc1d9, + 0xc1e3, 0x57db, 0x52f3, 0x047a, 0x7d06, 0x0479, 0x7c02, 0x6ac6, + 0x993c, 0x6ac7, 0x993c, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d, + 0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d4e, 0x0479, 0x7c1f, 0x0015, + 0x0388, 0x047a, 0x7d03, 0x62c8, 0x7e39, 0x9950, 0x620a, 0x7e38, + 0x0808, 0x7801, 0x0217, 0x5a06, 0x7f34, 0x2301, 0x047a, 0x7d03, + 0x62c8, 0x7e2c, 0x995d, 0x620a, 0x7e2b, 0x0808, 0x7801, 0x0217, + 0x5a26, 0x7f27, 0x2301, 0x4b00, 0x7ce4, 0x997c, 0x0015, 0x0015, + 0x0015, 0x047a, 0x7d09, 0x7806, 0x0b00, 0x62c8, 0x5a06, 0x0b01, + 0x62c8, 0x5a26, 0x7c13, 0x997c, 0x7806, 0x0b00, 0x620b, 0x5a06, + 0x0b01, 0x620b, 0x5a26, 0x7c0c, 0x0b70, 0x0311, 0x5313, 0x0000, + 0x55eb, 0x4d00, 0x7d11, 0xc1fa, 0x57db, 0x993c, 0x68cc, 0x9989, + 0x680c, 0x0007, 0x0479, 0x7c02, 0x008b, 0x9990, 0x0017, 0x00a3, + 0x0b70, 0x0311, 0x5313, 0xc213, 0xc20a, 0x9931, 0x0b70, 0x0311, + 0x5313, 0x076c, 0x7c01, 0xc1d9, 0x5efb, 0x068a, 0x076b, 0x7c01, + 0xc1d9, 0x5ef3, 0x59db, 0x58d3, 0x018f, 0x0110, 0x390f, 0x008b, + 0xc13c, 0x7d2b, 0x5ac0, 0x5bc8, 0xc14e, 0x7c27, 0x0388, 0x0689, + 0x5ce3, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x073e, 0x4d00, 0x7d18, + 0x0870, 0x0011, 0x077e, 0x7d09, 0x077d, 0x7d02, 0x5228, 0x99c1, + 0x52f8, 0x54db, 0x02bc, 0x02cc, 0x7c09, 0x077c, 0x7d02, 0x5228, + 0x99ca, 0x52f8, 0x54d3, 0x02bc, 0x02cc, 0x7d09, 0x0400, 0x99b8, + 0x008b, 0x52c0, 0x53c8, 0xc159, 0x7dd6, 0x0200, 0x99a8, 0x08ff, + 0x00bf, 0x077f, 0x7d15, 0x0488, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x5deb, 0x028f, 0x0212, 0x0212, 0x3aff, 0x05da, 0x7c02, 0x073e, + 0x99f3, 0x02a4, 0x02dd, 0x7d02, 0x073e, 0x99f3, 0x075e, 0x99f3, + 0x55eb, 0x0598, 0x5deb, 0x52f3, 0x54fb, 0x076a, 0x7d26, 0x076c, + 0x7d01, 0x9a30, 0x076b, 0x7c57, 0x0769, 0x7d04, 0x0768, 0x7d02, + 0x0e01, 0x9a0a, 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, + 0x5d93, 0x06a0, 0x7802, 0x5502, 0x5d04, 0x7c1d, 0x4e00, 0x7c08, + 0x0769, 0x7d03, 0x5502, 0x7e17, 0x9a17, 0x5d04, 0x7f14, 0x0689, + 0x5093, 0x4800, 0x7d01, 0x9a02, 0x9a7b, 0x0015, 0x7806, 0x5502, + 0x5d04, 0x074f, 0x5502, 0x5d24, 0x072f, 0x7c01, 0x9a7b, 0x0017, + 0x076f, 0x7c01, 0x2001, 0x5593, 0x009d, 0x0007, 0xda82, 0x99d0, + 0x6cd3, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a3f, 0x5893, + 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, + 0x5502, 0x6dc8, 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, + 0x7e09, 0x9a4c, 0x6dc8, 0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, + 0x9a37, 0x9a7b, 0x9a75, 0x6ac3, 0x0769, 0x7d04, 0x0768, 0x7d02, + 0x0e01, 0x9a62, 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, + 0x5d93, 0x06a0, 0x7802, 0x65c8, 0x5d04, 0x7c0f, 0x4e00, 0x7c08, + 0x0769, 0x7d03, 0x65c8, 0x7e09, 0x9a6f, 0x5d04, 0x7f06, 0x0689, + 0x5093, 0x4800, 0x7d01, 0x9a5a, 0x9a7b, 0x5593, 0x009d, 0x0007, + 0x6cff, 0xda82, 0x99d0, 0x0000, 0x54e3, 0x55eb, 0x4d00, 0x7c01, + 0x99d0, 0x99b8, 0x54e3, 0x55eb, 0x0aff, 0x0211, 0x1aff, 0x077f, + 0x7c02, 0x05a0, 0x9a8f, 0x009d, 0x058c, 0x05ba, 0x05a0, 0x0210, + 0x04ba, 0x04ad, 0x0454, 0x0006, 0xc1e3, 0x57db, 0x52f3, 0x6ac5, + 0x52fb, 0x6ad3, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, + 0x0478, 0x7d03, 0x0479, 0x7d20, 0x7c25, 0x0479, 0x7c19, 0x59e3, + 0x56ee, 0x61c8, 0x7e2e, 0x62c8, 0x7e2c, 0x65c8, 0x7e2a, 0x0660, + 0x7d03, 0x0112, 0x0112, 0x9ab6, 0x0512, 0x0512, 0x0211, 0x02a9, + 0x02ad, 0x6ac8, 0x7f1e, 0x2003, 0x4800, 0x7ceb, 0x51e3, 0x9ad0, + 0x7802, 0x62c8, 0x6ac8, 0x9acf, 0x6dce, 0x0015, 0x7802, 0x62c8, + 0x6ac8, 0x9acf, 0x6dcf, 0x0015, 0x0015, 0x7801, 0x62d8, 0x7c09, + 0x6ddf, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d06, 0xc1fa, 0x57db, + 0x9a9a, 0x0007, 0x68ff, 0xc213, 0xc20a, 0x9a95, 0xc1d9, 0xc1e3, + 0x57db, 0x52f3, 0x047a, 0x7d02, 0x6ad7, 0x9ae7, 0x6a05, 0x008f, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x56fb, 0x0015, 0x0015, 0x0015, + 0x047a, 0x7d07, 0x7804, 0x5206, 0x6ac8, 0x5226, 0x6ac8, 0x7c0f, + 0x9b01, 0x7804, 0x5206, 0x6a0b, 0x5226, 0x6a0b, 0x7c0a, 0x6a28, + 0x7f08, 0x0000, 0x4d00, 0x7d07, 0xc1fa, 0x57db, 0x9ae7, 0xc273, + 0x9b0a, 0xc277, 0x0454, 0xc20a, 0x9ae0, 0xc1e3, 0x57db, 0x52f3, + 0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1e, + 0x1e94, 0x6ee3, 0x62d0, 0x5aeb, 0x62c8, 0x0248, 0x6ed3, 0x6ac8, + 0x2694, 0x52eb, 0x6ad5, 0x6ee3, 0x62c8, 0x026e, 0x7d27, 0x6ac8, + 0x7f23, 0x2501, 0x4d00, 0x7d26, 0x028e, 0x1a98, 0x6ac3, 0x62c8, + 0x6ec3, 0x0260, 0x7df1, 0x62d0, 0xc27a, 0x9b52, 0x6ee3, 0x008f, + 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d0e, + 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, + 0x7d09, 0xc1fa, 0x57db, 0x9b11, 0x0007, 0x6aff, 0x62d0, 0xc27a, + 0x0458, 0x0454, 0x6add, 0x7ff8, 0xc20a, 0x9b0e, 0xc1d9, 0xc1e3, + 0x57db, 0x52f3, 0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x5202, 0x0269, + 0x7d17, 0x1e94, 0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, + 0x7d26, 0x6ac8, 0x7f22, 0x2501, 0x4d00, 0x7d27, 0x028e, 0x1a98, + 0x5202, 0x0260, 0x7df3, 0x6add, 0x7f18, 0x62d0, 0xc27a, 0x9b95, + 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e, + 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, + 0x4d00, 0x7d0b, 0xc1fa, 0x57db, 0x9b5b, 0x0007, 0x6aff, 0x6add, + 0x7ffc, 0x62d0, 0xc27a, 0x0458, 0x0454, 0x6add, 0x7ff6, 0xc20a, + 0x9b58 +}; +#endif diff --git a/arch/arm/mach-mx3/mx35_sdma_script_code_v2.h b/arch/arm/mach-mx3/mx35_sdma_script_code_v2.h new file mode 100644 index 000000000000..323eb4137bb3 --- /dev/null +++ b/arch/arm/mach-mx3/mx35_sdma_script_code_v2.h @@ -0,0 +1,234 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SDMA_RINGO.03.00.00" + +*******************************************************************************/ + +#ifndef __MX35_SDMA_SCRIPT_CODE_V2_H +#define __MX35_SDMA_SCRIPT_CODE_V2_H + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define mx35_start_ADDR_V2 0 +#define mx35_start_SIZE_V2 24 + +#define mx35_core_ADDR_V2 80 +#define mx35_core_SIZE_V2 233 + +#define mx35_common_ADDR_V2 313 +#define mx35_common_SIZE_V2 416 + +#define mx35_ap_2_ap_ADDR_V2 729 +#define mx35_ap_2_ap_SIZE_V2 41 + +#define mx35_app_2_mcu_ADDR_V2 770 +#define mx35_app_2_mcu_SIZE_V2 64 + +#define mx35_mcu_2_app_ADDR_V2 834 +#define mx35_mcu_2_app_SIZE_V2 70 + +#define mx35_uart_2_mcu_ADDR_V2 904 +#define mx35_uart_2_mcu_SIZE_V2 75 + +#define mx35_shp_2_mcu_ADDR_V2 979 +#define mx35_shp_2_mcu_SIZE_V2 69 + +#define mx35_mcu_2_shp_ADDR_V2 1048 +#define mx35_mcu_2_shp_SIZE_V2 72 + +#define mx35_per_2_shp_ADDR_V2 1120 +#define mx35_per_2_shp_SIZE_V2 78 + +#define mx35_shp_2_per_ADDR_V2 1198 +#define mx35_shp_2_per_SIZE_V2 72 + +#define mx35_uartsh_2_mcu_ADDR_V2 1270 +#define mx35_uartsh_2_mcu_SIZE_V2 69 + +#define mx35_mcu_2_ata_ADDR_V2 1339 +#define mx35_mcu_2_ata_SIZE_V2 90 + +#define mx35_ata_2_mcu_ADDR_V2 1429 +#define mx35_ata_2_mcu_SIZE_V2 102 + +#define mx35_app_2_per_ADDR_V2 1531 +#define mx35_app_2_per_SIZE_V2 66 + +#define mx35_per_2_app_ADDR_V2 1597 +#define mx35_per_2_app_SIZE_V2 74 + +#define mx35_loop_DMAs_routines_ADDR_V2 1671 +#define mx35_loop_DMAs_routines_SIZE_V2 240 + +#define mx35_test_ADDR_V2 1911 +#define mx35_test_SIZE_V2 63 + +#define mx35_signature_ADDR_V2 1022 +#define mx35_signature_SIZE_V2 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define mx35_asrc__mcu_ADDR_V2 6144 +#define mx35_asrc__mcu_SIZE_V2 116 + +#define mx35_ext_mem__ipu_ram_ADDR_V2 6260 +#define mx35_ext_mem__ipu_ram_SIZE_V2 123 + +#define mx35_mcu_2_spdif_ADDR_V2 6383 +#define mx35_mcu_2_spdif_SIZE_V2 103 + +#define mx35_p_2_p_ADDR_V2 6486 +#define mx35_p_2_p_SIZE_V2 260 + +#define mx35_spdif_2_mcu_ADDR_V2 6746 +#define mx35_spdif_2_mcu_SIZE_V2 47 + +#define mx35_uart_2_per_ADDR_V2 6793 +#define mx35_uart_2_per_SIZE_V2 73 + +#define mx35_uartsh_2_per_ADDR_V2 6866 +#define mx35_uartsh_2_per_SIZE_V2 67 + +/*! +* SDMA RAM image start address and size +*/ + +#define MX35_RAM_CODE_START_ADDR_V2 6144 +#define MX35_RAM_CODE_SIZE_V2 789 + +/*! +* Buffer that holds the SDMA RAM image +*/ + +static const short mx35_sdma_code_v2[] = { + 0xc230, 0xc23a, 0x56f3, 0x57db, 0x047a, 0x7d07, 0x072f, 0x076e, + 0x7d02, 0x6ec7, 0x9813, 0x6ed7, 0x9813, 0x074f, 0x076e, 0x7d02, + 0x6e01, 0x9813, 0x6e05, 0x5ce3, 0x048f, 0x0410, 0x3c0f, 0x5c93, + 0x0e03, 0x0611, 0x1eff, 0x06bf, 0x06d5, 0x7d01, 0x068d, 0x05a6, + 0x5deb, 0x55fb, 0x008e, 0x076a, 0x7d02, 0x076b, 0x7c04, 0x06d4, + 0x7d01, 0x008c, 0x04a0, 0x06a0, 0x076f, 0x7d0c, 0x076e, 0x7d05, + 0x7802, 0x62c8, 0x5a05, 0x7c2b, 0x9847, 0x7802, 0x5205, 0x6ac8, + 0x7c26, 0x9847, 0x076e, 0x7d05, 0x7802, 0x620b, 0x5a05, 0x7c21, + 0x9847, 0x7802, 0x5205, 0x6a0b, 0x7c1c, 0x6a28, 0x7f1a, 0x076a, + 0x7d02, 0x076b, 0x7c0a, 0x4c00, 0x7c08, 0x076a, 0x7d03, 0x5a05, + 0x7f11, 0x9854, 0x5205, 0x7e0e, 0x5493, 0x4e00, 0x7ccb, 0x0000, + 0x54e3, 0x55eb, 0x4d00, 0x7d0a, 0xc251, 0x57db, 0x9814, 0x68cc, + 0x9862, 0x680c, 0x009e, 0x0007, 0x54e3, 0xd868, 0xc261, 0x9802, + 0x55eb, 0x009d, 0x058c, 0x0aff, 0x0211, 0x1aff, 0x05ba, 0x05a0, + 0x04b2, 0x04ad, 0x0454, 0x0006, 0x0e70, 0x0611, 0x5616, 0xc18a, + 0x7d2a, 0x5ade, 0x008e, 0xc19c, 0x7c26, 0x5be0, 0x5ef0, 0x5ce8, + 0x0688, 0x08ff, 0x0011, 0x28ff, 0x00bc, 0x53f6, 0x05df, 0x7d0b, + 0x6dc5, 0x03df, 0x7d03, 0x6bd5, 0xd8c3, 0x989f, 0x6b05, 0xc6e7, + 0x7e27, 0x7f29, 0x989f, 0x6d01, 0x03df, 0x7d05, 0x6bd5, 0xc711, + 0x7e18, 0x7f1a, 0x989f, 0x6b05, 0xc687, 0x7e07, 0x7f06, 0x52de, + 0x53e6, 0xc1a8, 0x7dd7, 0x0200, 0x9877, 0x0007, 0x6004, 0x680c, + 0x53f6, 0x028e, 0x00a3, 0xc2ad, 0x048b, 0x0498, 0x0454, 0x068a, + 0x989f, 0x0207, 0x680c, 0x6ddf, 0x0107, 0x68ff, 0x60d0, 0x98a8, + 0x0207, 0x68ff, 0x6d28, 0x0107, 0x6004, 0x680c, 0x98a8, 0x0007, + 0x68ff, 0x60d0, 0x98a8, 0x0288, 0x03a5, 0x3b03, 0x3d03, 0x4d00, + 0x7d0a, 0x0804, 0x00a5, 0x00da, 0x7d1a, 0x02a0, 0x7b01, 0x65d8, + 0x7eee, 0x65ff, 0x7eec, 0x0804, 0x02d0, 0x7d11, 0x4b00, 0x7c0f, + 0x008a, 0x3003, 0x6dcf, 0x6bdf, 0x0015, 0x0015, 0x7b02, 0x65d8, + 0x0000, 0x7edd, 0x63ff, 0x7edb, 0x3a03, 0x6dcd, 0x6bdd, 0x008a, + 0x7b02, 0x65d8, 0x0000, 0x7ed3, 0x65ff, 0x7ed1, 0x0006, 0xc230, + 0xc23a, 0x57db, 0x52f3, 0x047a, 0x7d06, 0x0479, 0x7c02, 0x6ac6, + 0x98fc, 0x6ac7, 0x98fc, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d, + 0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d4e, 0x0479, 0x7c1f, 0x0015, + 0x0388, 0x047a, 0x7d03, 0x62c8, 0x7e39, 0x9910, 0x620a, 0x7e38, + 0x0808, 0x7801, 0x0217, 0x5a06, 0x7f34, 0x2301, 0x047a, 0x7d03, + 0x62c8, 0x7e2c, 0x991d, 0x620a, 0x7e2b, 0x0808, 0x7801, 0x0217, + 0x5a26, 0x7f27, 0x2301, 0x4b00, 0x7ce4, 0x993c, 0x0015, 0x0015, + 0x0015, 0x047a, 0x7d09, 0x7806, 0x0b00, 0x62c8, 0x5a06, 0x0b01, + 0x62c8, 0x5a26, 0x7c13, 0x993c, 0x7806, 0x0b00, 0x620b, 0x5a06, + 0x0b01, 0x620b, 0x5a26, 0x7c0c, 0x0b70, 0x0311, 0x5313, 0x0000, + 0x55eb, 0x4d00, 0x7d11, 0xc251, 0x57db, 0x98fc, 0x68cc, 0x9949, + 0x680c, 0x0007, 0x0479, 0x7c02, 0x008b, 0x9950, 0x0017, 0x00a3, + 0x0b70, 0x0311, 0x5313, 0xc26a, 0xc261, 0x98f1, 0x0b70, 0x0311, + 0x5313, 0x076c, 0x7c01, 0xc230, 0x5efb, 0x068a, 0x076b, 0x7c01, + 0xc230, 0x5ef3, 0x59db, 0x58d3, 0x018f, 0x0110, 0x390f, 0x008b, + 0xc18a, 0x7d2b, 0x5ac0, 0x5bc8, 0xc19c, 0x7c27, 0x0388, 0x0689, + 0x5ce3, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x073e, 0x4d00, 0x7d18, + 0x0870, 0x0011, 0x077e, 0x7d09, 0x077d, 0x7d02, 0x5228, 0x9981, + 0x52f8, 0x54db, 0x02bc, 0x02cc, 0x7c09, 0x077c, 0x7d02, 0x5228, + 0x998a, 0x52f8, 0x54d3, 0x02bc, 0x02cc, 0x7d09, 0x0400, 0x9978, + 0x008b, 0x52c0, 0x53c8, 0xc1a8, 0x7dd6, 0x0200, 0x9968, 0x08ff, + 0x00bf, 0x077f, 0x7d1b, 0x0488, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x5deb, 0x028f, 0x32ff, 0x0210, 0x32ff, 0x0210, 0x0212, 0x0217, + 0x0217, 0x32ff, 0x0212, 0x05da, 0x7c02, 0x073e, 0x99b9, 0x02a4, + 0x02dd, 0x7d02, 0x073e, 0x99b9, 0x075e, 0x99b9, 0x55eb, 0x0598, + 0x5deb, 0x52f3, 0x54fb, 0x076a, 0x7d26, 0x076c, 0x7d01, 0x99f6, + 0x076b, 0x7c57, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x99d0, + 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, + 0x7802, 0x5502, 0x5d04, 0x7c1d, 0x4e00, 0x7c08, 0x0769, 0x7d03, + 0x5502, 0x7e17, 0x99dd, 0x5d04, 0x7f14, 0x0689, 0x5093, 0x4800, + 0x7d01, 0x99c8, 0x9a41, 0x0015, 0x7806, 0x5502, 0x5d04, 0x074d, + 0x5502, 0x5d24, 0x072d, 0x7c01, 0x9a41, 0x0017, 0x076d, 0x7c01, + 0x2001, 0x5593, 0x009d, 0x0007, 0xda48, 0x9990, 0x6cd3, 0x0769, + 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a05, 0x5893, 0x00d6, 0x7d01, + 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x5502, 0x6dc8, + 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, 0x7e09, 0x9a12, + 0x6dc8, 0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, 0x99fd, 0x9a41, + 0x9a3b, 0x6ac3, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9a28, + 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, + 0x7802, 0x65c8, 0x5d04, 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, + 0x65c8, 0x7e09, 0x9a35, 0x5d04, 0x7f06, 0x0689, 0x5093, 0x4800, + 0x7d01, 0x9a20, 0x9a41, 0x5593, 0x009d, 0x0007, 0x6cff, 0xda48, + 0x9990, 0x0000, 0x54e3, 0x55eb, 0x4d00, 0x7c01, 0x9990, 0x9978, + 0x54e3, 0x55eb, 0x0aff, 0x0211, 0x1aff, 0x077f, 0x7c02, 0x05a0, + 0x9a55, 0x009d, 0x058c, 0x05ba, 0x05a0, 0x0210, 0x04ba, 0x04ad, + 0x0454, 0x0006, 0xc230, 0xc23a, 0x57db, 0x52f3, 0x047a, 0x7d02, + 0x6ad7, 0x9a63, 0x6a05, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, + 0x56fb, 0x0015, 0x0015, 0x0015, 0x047a, 0x7d07, 0x7804, 0x5206, + 0x6ac8, 0x5226, 0x6ac8, 0x7c0f, 0x9a7d, 0x7804, 0x5206, 0x6a0b, + 0x5226, 0x6a0b, 0x7c0a, 0x6a28, 0x7f08, 0x0000, 0x4d00, 0x7d07, + 0xc251, 0x57db, 0x9a63, 0xc2ca, 0x9a86, 0xc2ce, 0x0454, 0xc261, + 0x9a5c, 0xc23a, 0x57db, 0x52f3, 0x6ad5, 0x56fb, 0x028e, 0x1a94, + 0x6ac3, 0x62c8, 0x0269, 0x7d1e, 0x1e94, 0x6ee3, 0x62d0, 0x5aeb, + 0x62c8, 0x0248, 0x6ed3, 0x6ac8, 0x2694, 0x52eb, 0x6ad5, 0x6ee3, + 0x62c8, 0x026e, 0x7d27, 0x6ac8, 0x7f23, 0x2501, 0x4d00, 0x7d26, + 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3, 0x0260, 0x7df1, 0x62d0, + 0xc2d1, 0x9ace, 0x6ee3, 0x008f, 0x2001, 0x00d5, 0x7d01, 0x008d, + 0x05a0, 0x62c8, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, 0x7cf9, + 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d09, 0xc251, 0x57db, 0x9a8d, + 0x0007, 0x6aff, 0x62d0, 0xc2d1, 0x0458, 0x0454, 0x6add, 0x7ff8, + 0xc261, 0x9a8a, 0xc230, 0xc23a, 0x57db, 0x52f3, 0x6ad5, 0x56fb, + 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d17, 0x1e94, 0x5206, 0x0248, + 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d26, 0x6ac8, 0x7f22, 0x2501, + 0x4d00, 0x7d27, 0x028e, 0x1a98, 0x5202, 0x0260, 0x7df3, 0x6add, + 0x7f18, 0x62d0, 0xc2d1, 0x9b11, 0x008f, 0x2001, 0x00d5, 0x7d01, + 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, 0x2001, + 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d0b, 0xc251, 0x57db, + 0x9ad7, 0x0007, 0x6aff, 0x6add, 0x7ffc, 0x62d0, 0xc2d1, 0x0458, + 0x0454, 0x6add, 0x7ff6, 0xc261, 0x9ad4 +}; +#endif diff --git a/arch/arm/mach-mx3/mx3_3ds_pmic_mc13783.c b/arch/arm/mach-mx3/mx3_3ds_pmic_mc13783.c new file mode 100644 index 000000000000..1ecd5531e339 --- /dev/null +++ b/arch/arm/mach-mx3/mx3_3ds_pmic_mc13783.c @@ -0,0 +1,273 @@ +/* + * mx3-3stack-pmic-mc13783.c -- i.MX3 3STACK Driver for Atlas MC13783 PMIC + */ + /* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) + +struct mc13783; + +static struct regulator_init_data violo_init = { + .constraints = { + .min_uV = mV_to_uV(1200), /* mc13783 allows min of 1200. */ + .max_uV = mV_to_uV(1800), /* mc13783 allows max of 1800. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .min_uV = mV_to_uV(1200), /* mc13783 allows min of 1200. */ + .max_uV = mV_to_uV(1800), /* mc13783 allows max of 1800. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vgen_init = { + .constraints = { + .min_uV = mV_to_uV(1100), /* mc13783 allows min of 1100. */ + .max_uV = mV_to_uV(2775), /* mc13783 allows max of 2775. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vrfdig_init = { + .constraints = { + .min_uV = mV_to_uV(1200), /* mc13783 allows min of 1200. */ + .max_uV = mV_to_uV(1875), /* mc13783 allows max of 1875. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vrfref_init = { + .constraints = { + .min_uV = mV_to_uV(2475), /* mc13783 allows min of 2475. */ + .max_uV = mV_to_uV(2775), /* mc13783 allows max of 2775. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vrfcp_init = { + .constraints = { + .min_uV = mV_to_uV(2700), /* mc13783 allows min of 2700. */ + .max_uV = mV_to_uV(2775), /* mc13783 allows max of 2775. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vsim_init = { + .constraints = { + .min_uV = mV_to_uV(1800), /* mc13783 allows min of 1800. */ + .max_uV = mV_to_uV(2900), /* mc13783 allows max of 2900. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vesim_init = { + .constraints = { + .min_uV = mV_to_uV(1800), /* mc13783 allows min of 1800. */ + .max_uV = mV_to_uV(2900), /* mc13783 allows max of 2900. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .min_uV = mV_to_uV(1500), /* mc13783 allows min of 1500. */ + .max_uV = mV_to_uV(3000), /* mc13783 allows max of 3000. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vvib_init = { + .constraints = { + .min_uV = mV_to_uV(1300), /* mc13783 allows min of 1300. */ + .max_uV = mV_to_uV(3000), /* mc13783 allows max of 3000. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vrf_init = { + .constraints = { + .min_uV = mV_to_uV(1500), /* mc13783 allows min of 1500. */ + .max_uV = mV_to_uV(2775), /* mc13783 allows max of 2775. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vmmc_init = { + .constraints = { + .min_uV = mV_to_uV(1600), /* mc13783 allows min of 1600. */ + .max_uV = mV_to_uV(3000), /* mc13783 allows max of 3000. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .min_uV = mV_to_uV(5000), /* mc13783 allows min of 5000. */ + .max_uV = mV_to_uV(5500), /* mc13783 allows max of 5500. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data sw1_init = { + .constraints = { + .min_uV = mV_to_uV(1200), /* mc13783 allows min of 900. */ + .max_uV = mV_to_uV(1600), /* mc13783 allows max of 2200. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_FAST + | REGULATOR_MODE_NORMAL + | REGULATOR_MODE_IDLE + | REGULATOR_MODE_STANDBY, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = mV_to_uV(1250), + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw_init = { + .constraints = { + .min_uV = mV_to_uV(1200), /* mc13783 allows min of 900. */ + .max_uV = mV_to_uV(2200), /* mc13783 allows max of 2200. */ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .boot_on = 1, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .boot_on = 1, + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + }, +}; + +static struct regulator_init_data gpo_init = { + .constraints = { + }, +}; + +static int mc13783_regulator_init(void *data) +{ + struct mc13783 *mc13783 = data; + unsigned int value; +#if 0 + /*most regulators are controled by standby signal*/ + /*except violo*/ + pmic_read_reg(REG_REGULATOR_MODE_0, &value, 0xffffff); + value |= 0x492412; + pmic_write_reg(REG_REGULATOR_MODE_0, value, 0xffffff); + pmic_read_reg(REG_REGULATOR_MODE_1, &value, 0xffffff); + value |= 0x492492; + pmic_write_reg(REG_REGULATOR_MODE_1, value, 0xffffff); + /*also sw3 is controled by standby signal*/ + pmic_read_reg(REG_SWITCHERS_5, &value, 0xffffff); + value |= 0x200000; + pmic_write_reg(REG_SWITCHERS_5, value, 0xffffff); +#endif + mc13783_register_regulator(mc13783, MC13783_SW1A, &sw1_init); + mc13783_register_regulator(mc13783, MC13783_SW1B, &sw_init); + mc13783_register_regulator(mc13783, MC13783_SW2A, &sw_init); + mc13783_register_regulator(mc13783, MC13783_SW2B, &sw_init); + mc13783_register_regulator(mc13783, MC13783_SW3, &sw3_init); + mc13783_register_regulator(mc13783, MC13783_VMMC1, &vmmc_init); + mc13783_register_regulator(mc13783, MC13783_VMMC2, &vmmc_init); + mc13783_register_regulator(mc13783, MC13783_VVIB, &vvib_init); + mc13783_register_regulator(mc13783, MC13783_VIOHI, &viohi_init); + mc13783_register_regulator(mc13783, MC13783_VIOLO, &violo_init); + mc13783_register_regulator(mc13783, MC13783_VDIG, &vdig_init); + mc13783_register_regulator(mc13783, MC13783_VRFDIG, &vrfdig_init); + mc13783_register_regulator(mc13783, MC13783_VRFREF, &vrfref_init); + mc13783_register_regulator(mc13783, MC13783_VRFCP, &vrfcp_init); + mc13783_register_regulator(mc13783, MC13783_VRF1, &vrf_init); + mc13783_register_regulator(mc13783, MC13783_VRF2, &vrf_init); + mc13783_register_regulator(mc13783, MC13783_VAUDIO, &vaudio_init); + mc13783_register_regulator(mc13783, MC13783_VCAM, &vcam_init); + mc13783_register_regulator(mc13783, MC13783_VGEN, &vgen_init); + mc13783_register_regulator(mc13783, MC13783_VSIM, &vsim_init); + mc13783_register_regulator(mc13783, MC13783_VESIM, &vesim_init); + mc13783_register_regulator(mc13783, MC13783_GPO1, &gpo1_init); + + gpo_init.supply_regulator_dev = + &(mc13783->pmic.pdev[MC13783_GPO1]->dev); + mc13783_register_regulator(mc13783, MC13783_GPO2, &gpo_init); + mc13783_register_regulator(mc13783, MC13783_GPO3, &gpo_init); + mc13783_register_regulator(mc13783, MC13783_GPO4, &gpo4_init); + + return 0; +} + +static struct pmic_platform_data mc13783_plat = { + .init = mc13783_regulator_init, + .power_key_irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2), +}; + +static struct spi_board_info __initdata mc13783_spi_device = { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), + .max_speed_hz = 4000000, + .bus_num = 2, + .platform_data = &mc13783_plat, + .chip_select = 2, +}; + +int __init mx3_3stack_init_mc13783(void) +{ + return spi_register_board_info(&mc13783_spi_device, 1); +} diff --git a/arch/arm/mach-mx3/mx3x-dma.c b/arch/arm/mach-mx3/mx3x-dma.c new file mode 100644 index 000000000000..cd2eb1c6a478 --- /dev/null +++ b/arch/arm/mach-mx3/mx3x-dma.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include + +#include "mx31_sdma_script_code_v1.h" +#include "mx31_sdma_script_code_v2.h" +#include "mx35_sdma_script_code_v1.h" +#include "mx35_sdma_script_code_v2.h" + +void mx31_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + sdma_script_start_addrs *d = sdma_script_addr; + + if (cpu_is_mx31_rev(CHIP_REV_1_0) == 1) { + d->mxc_sdma_app_2_mcu_addr = mx31_app_2_mcu_ADDR; + d->mxc_sdma_ap_2_ap_addr = mx31_ap_2_ap_ADDR; + d->mxc_sdma_ap_2_bp_addr = -1; + d->mxc_sdma_bp_2_ap_addr = -1; + d->mxc_sdma_loopback_on_dsp_side_addr = -1; + d->mxc_sdma_mcu_2_app_addr = mx31_mcu_2_app_ADDR; + d->mxc_sdma_mcu_2_shp_addr = mx31_mcu_2_shp_ADDR; + d->mxc_sdma_mcu_interrupt_only_addr = -1; + d->mxc_sdma_shp_2_mcu_addr = mx31_shp_2_mcu_ADDR; + d->mxc_sdma_start_addr = (unsigned short *)mx31_sdma_code; + d->mxc_sdma_uartsh_2_mcu_addr = mx31_uartsh_2_mcu_ADDR; + d->mxc_sdma_uart_2_mcu_addr = mx31_uart_2_mcu_ADDR; + d->mxc_sdma_ram_code_size = MX31_RAM_CODE_SIZE; + d->mxc_sdma_ram_code_start_addr = MX31_RAM_CODE_START_ADDR; + d->mxc_sdma_dptc_dvfs_addr = mx31_dptc_dvfs_ADDR; + d->mxc_sdma_firi_2_mcu_addr = mx31_firi_2_mcu_ADDR; + d->mxc_sdma_firi_2_per_addr = -1; + d->mxc_sdma_mshc_2_mcu_addr = mx31_mshc_2_mcu_ADDR; + d->mxc_sdma_per_2_app_addr = -1; + d->mxc_sdma_per_2_firi_addr = -1; + d->mxc_sdma_per_2_shp_addr = -1; + d->mxc_sdma_mcu_2_ata_addr = mx31_mcu_2_ata_ADDR; + d->mxc_sdma_mcu_2_firi_addr = mx31_mcu_2_firi_ADDR; + d->mxc_sdma_mcu_2_mshc_addr = mx31_mcu_2_mshc_ADDR; + d->mxc_sdma_ata_2_mcu_addr = mx31_ata_2_mcu_ADDR; + d->mxc_sdma_uartsh_2_per_addr = -1; + d->mxc_sdma_shp_2_per_addr = -1; + d->mxc_sdma_uart_2_per_addr = -1; + d->mxc_sdma_app_2_per_addr = -1; + } else { + d->mxc_sdma_app_2_mcu_addr = mx31_app_2_mcu_ADDR_2; + d->mxc_sdma_ap_2_ap_addr = mx31_ap_2_ap_ADDR_2; + d->mxc_sdma_ap_2_ap_fixed_addr = mx31_ap_2_ap_fixed_addr_ADDR_2; + d->mxc_sdma_ap_2_bp_addr = mx31_ap_2_bp_ADDR_2; + d->mxc_sdma_ap_2_ap_fixed_addr = mx31_ap_2_ap_fixed_addr_ADDR_2; + d->mxc_sdma_bp_2_ap_addr = mx31_bp_2_ap_ADDR_2; + d->mxc_sdma_loopback_on_dsp_side_addr = -1; + d->mxc_sdma_mcu_2_app_addr = mx31_mcu_2_app_ADDR_2; + d->mxc_sdma_mcu_2_shp_addr = mx31_mcu_2_shp_ADDR_2; + d->mxc_sdma_mcu_interrupt_only_addr = -1; + d->mxc_sdma_shp_2_mcu_addr = mx31_shp_2_mcu_ADDR_2; + d->mxc_sdma_start_addr = (unsigned short *)mx31_sdma_code_2; + d->mxc_sdma_uartsh_2_mcu_addr = mx31_uartsh_2_mcu_ADDR_2; + d->mxc_sdma_uart_2_mcu_addr = mx31_uart_2_mcu_ADDR_2; + d->mxc_sdma_ram_code_size = MX31_RAM_CODE_SIZE_2; + d->mxc_sdma_ram_code_start_addr = MX31_RAM_CODE_START_ADDR_2; + d->mxc_sdma_dptc_dvfs_addr = -1; + d->mxc_sdma_firi_2_mcu_addr = mx31_firi_2_mcu_ADDR_2; + d->mxc_sdma_firi_2_per_addr = -1; + d->mxc_sdma_mshc_2_mcu_addr = mx31_mshc_2_mcu_ADDR_2; + d->mxc_sdma_per_2_app_addr = mx31_per_2_app_ADDR_2; + d->mxc_sdma_per_2_firi_addr = -1; + d->mxc_sdma_per_2_shp_addr = mx31_per_2_shp_ADDR_2; + d->mxc_sdma_mcu_2_ata_addr = mx31_mcu_2_ata_ADDR_2; + d->mxc_sdma_mcu_2_firi_addr = mx31_mcu_2_firi_ADDR_2; + d->mxc_sdma_mcu_2_mshc_addr = mx31_mcu_2_mshc_ADDR_2; + d->mxc_sdma_ata_2_mcu_addr = mx31_ata_2_mcu_ADDR_2; + d->mxc_sdma_uartsh_2_per_addr = -1; + d->mxc_sdma_shp_2_per_addr = mx31_shp_2_per_ADDR_2; + d->mxc_sdma_uart_2_per_addr = -1; + d->mxc_sdma_app_2_per_addr = mx31_app_2_per_ADDR_2; + } +} + +void mx35_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + sdma_script_start_addrs *d = sdma_script_addr; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 1) { + d->mxc_sdma_ap_2_ap_addr = mx35_ap_2_ap_ADDR; + d->mxc_sdma_ap_2_bp_addr = -1; + d->mxc_sdma_bp_2_ap_addr = -1; + d->mxc_sdma_loopback_on_dsp_side_addr = -1; + d->mxc_sdma_mcu_interrupt_only_addr = -1; + + d->mxc_sdma_firi_2_per_addr = -1; + d->mxc_sdma_firi_2_mcu_addr = -1; + d->mxc_sdma_per_2_firi_addr = -1; + d->mxc_sdma_mcu_2_firi_addr = -1; + + d->mxc_sdma_uart_2_per_addr = mx35_uart_2_per_ADDR; + d->mxc_sdma_uart_2_mcu_addr = mx35_uart_2_mcu_ADDR; + d->mxc_sdma_per_2_app_addr = mx35_per_2_app_ADDR; + d->mxc_sdma_mcu_2_app_addr = mx35_mcu_2_app_ADDR; + d->mxc_sdma_per_2_per_addr = mx35_p_2_p_ADDR; + d->mxc_sdma_uartsh_2_per_addr = mx35_uartsh_2_per_ADDR; + d->mxc_sdma_uartsh_2_mcu_addr = mx35_uartsh_2_mcu_ADDR; + d->mxc_sdma_per_2_shp_addr = mx35_per_2_shp_ADDR; + d->mxc_sdma_mcu_2_shp_addr = mx35_mcu_2_shp_ADDR; + d->mxc_sdma_ata_2_mcu_addr = mx35_ata_2_mcu_ADDR; + d->mxc_sdma_mcu_2_ata_addr = mx35_mcu_2_ata_ADDR; + d->mxc_sdma_app_2_per_addr = mx35_app_2_per_ADDR; + d->mxc_sdma_app_2_mcu_addr = mx35_app_2_mcu_ADDR; + d->mxc_sdma_shp_2_per_addr = mx35_shp_2_per_ADDR; + d->mxc_sdma_shp_2_mcu_addr = mx35_shp_2_mcu_ADDR; + d->mxc_sdma_mshc_2_mcu_addr = -1; + d->mxc_sdma_mcu_2_mshc_addr = -1; + + d->mxc_sdma_spdif_2_mcu_addr = mx35_spdif_2_mcu_ADDR; + d->mxc_sdma_mcu_2_spdif_addr = mx35_mcu_2_spdif_ADDR; + d->mxc_sdma_asrc_2_mcu_addr = mx35_asrc__mcu_ADDR; + + d->mxc_sdma_dptc_dvfs_addr = -1; + d->mxc_sdma_ext_mem_2_ipu_addr = mx35_ext_mem__ipu_ram_ADDR; + d->mxc_sdma_descrambler_addr = -1; + + d->mxc_sdma_start_addr = (unsigned short *)mx35_sdma_code; + d->mxc_sdma_ram_code_size = MX35_RAM_CODE_SIZE; + d->mxc_sdma_ram_code_start_addr = MX35_RAM_CODE_START_ADDR; + } else { + d->mxc_sdma_ap_2_ap_addr = mx35_ap_2_ap_ADDR_V2; + d->mxc_sdma_ap_2_bp_addr = -1; + d->mxc_sdma_bp_2_ap_addr = -1; + d->mxc_sdma_loopback_on_dsp_side_addr = -1; + d->mxc_sdma_mcu_interrupt_only_addr = -1; + + d->mxc_sdma_firi_2_per_addr = -1; + d->mxc_sdma_firi_2_mcu_addr = -1; + d->mxc_sdma_per_2_firi_addr = -1; + d->mxc_sdma_mcu_2_firi_addr = -1; + + d->mxc_sdma_uart_2_per_addr = mx35_uart_2_per_ADDR_V2; + d->mxc_sdma_uart_2_mcu_addr = mx35_uart_2_mcu_ADDR_V2; + d->mxc_sdma_per_2_app_addr = mx35_per_2_app_ADDR_V2; + d->mxc_sdma_mcu_2_app_addr = mx35_mcu_2_app_ADDR_V2; + d->mxc_sdma_per_2_per_addr = mx35_p_2_p_ADDR_V2; + d->mxc_sdma_uartsh_2_per_addr = mx35_uartsh_2_per_ADDR_V2; + d->mxc_sdma_uartsh_2_mcu_addr = mx35_uartsh_2_mcu_ADDR_V2; + d->mxc_sdma_per_2_shp_addr = mx35_per_2_shp_ADDR_V2; + d->mxc_sdma_mcu_2_shp_addr = mx35_mcu_2_shp_ADDR_V2; + + d->mxc_sdma_ata_2_mcu_addr = mx35_ata_2_mcu_ADDR_V2; + d->mxc_sdma_mcu_2_ata_addr = mx35_mcu_2_ata_ADDR_V2; + + d->mxc_sdma_app_2_per_addr = mx35_app_2_per_ADDR_V2; + d->mxc_sdma_app_2_mcu_addr = mx35_app_2_mcu_ADDR_V2; + d->mxc_sdma_shp_2_per_addr = mx35_shp_2_per_ADDR_V2; + d->mxc_sdma_shp_2_mcu_addr = mx35_shp_2_mcu_ADDR_V2; + + d->mxc_sdma_mshc_2_mcu_addr = -1; + d->mxc_sdma_mcu_2_mshc_addr = -1; + + d->mxc_sdma_spdif_2_mcu_addr = mx35_spdif_2_mcu_ADDR_V2; + d->mxc_sdma_mcu_2_spdif_addr = mx35_mcu_2_spdif_ADDR_V2; + + d->mxc_sdma_asrc_2_mcu_addr = mx35_asrc__mcu_ADDR_V2; + + d->mxc_sdma_dptc_dvfs_addr = -1; + d->mxc_sdma_ext_mem_2_ipu_addr = mx35_ext_mem__ipu_ram_ADDR_V2; + d->mxc_sdma_descrambler_addr = -1; + + d->mxc_sdma_start_addr = (unsigned short *)mx35_sdma_code_v2; + d->mxc_sdma_ram_code_size = MX35_RAM_CODE_SIZE; + d->mxc_sdma_ram_code_start_addr = MX35_RAM_CODE_START_ADDR_V2; + } +} + +void mxc_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + sdma_script_start_addrs *d = sdma_script_addr; + + if (cpu_is_mx31()) + mx31_sdma_get_script_info(d); + else if (cpu_is_mx35()) + mx35_sdma_get_script_info(d); +} diff --git a/arch/arm/mach-mx3/pm.c b/arch/arm/mach-mx3/pm.c new file mode 100644 index 000000000000..7c611b95c746 --- /dev/null +++ b/arch/arm/mach-mx3/pm.c @@ -0,0 +1,179 @@ +/* + * linux/arch/arm/mach-mx3/pm.c + * + * MX3 Power Management Routines + * + * Original code for the SA11x0: + * Copyright (c) 2001 Cliff Brake + * + * Modified for the PXA250 by Nicolas Pitre: + * Copyright (c) 2002 Monta Vista Software, Inc. + * + * Modified for the OMAP1510 by David Singleton: + * Copyright (c) 2002 Monta Vista Software, Inc. + * + * Cleanup 2004 for OMAP1510/1610 by Dirk Behme + * + * Modified for the MX31 + * Copyright 2005-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +extern void mxc_pm_arch_entry(void *entry, u32 size); +extern void mxc_init_irq(void __iomem *irqbase); + +int suspend_ops_started; +int is_suspend_ops_started(void) +{ + return suspend_ops_started; +} + +static int mx31_suspend_enter(suspend_state_t state) +{ + unsigned long reg; + + /* Enable Well Bias and set VSTBY + * VSTBY pin will be asserted during SR mode. This asks the + * PM IC to set the core voltage to the standby voltage + * Must clear the MXC_CCM_CCMR_SBYCS bit as well?? */ + reg = __raw_readl(MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_LPM_MASK; + reg |= MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY | MXC_CCM_CCMR_SBYCS; + + switch (state) { + case PM_SUSPEND_MEM: + /* State Retention mode */ + reg |= 2 << MXC_CCM_CCMR_LPM_OFFSET; + __raw_writel(reg, MXC_CCM_CCMR); + + /* Executing CP15 (Wait-for-Interrupt) Instruction */ + cpu_do_idle(); + break; + case PM_SUSPEND_STANDBY: + /* Deep Sleep Mode */ + reg |= 3 << MXC_CCM_CCMR_LPM_OFFSET; + __raw_writel(reg, MXC_CCM_CCMR); + + /* wake up by keypad */ + reg = __raw_readl(MXC_CCM_WIMR); + reg &= ~(1 << 18); + __raw_writel(reg, MXC_CCM_WIMR); + + flush_cache_all(); + l2x0_disable(); + + mxc_pm_arch_entry(MX31_IO_ADDRESS(MX31_NFC_BASE_ADDR), 2048); + printk(KERN_INFO "Resume from DSM\n"); + + l2x0_enable(); + mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); + + break; + default: + return -EINVAL; + } + return 0; +} + +static int mx35_suspend_enter(suspend_state_t state) +{ + unsigned long reg; + + reg = __raw_readl(MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_LPM_MASK; + + switch (state) { + case PM_SUSPEND_MEM: + case PM_SUSPEND_STANDBY: + /* Enabled Well Bias */ + reg |= MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY; + /* program LPM bit */ + reg |= 3 << MXC_CCM_CCMR_LPM_OFFSET; + /* program Interrupt holdoff bit */ + reg |= MX35_CCM_CCMR_WFI; + /* TBD: PMIC has put the voltage back to + * Normal if the voltage ready + */ + /* counter finished */ + reg |= MX35_CCM_CCMR_STBY_EXIT_SRC; + break; + default: + return -EINVAL; + } + + __raw_writel(reg, MXC_CCM_CCMR); + + /* Executing CP15 (Wait-for-Interrupt) Instruction */ + cpu_do_idle(); + return 0; +} + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx3_suspend_prepare(void) +{ + suspend_ops_started = 1; + return 0; +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx3_suspend_finish(void) +{ + suspend_ops_started = 0; + return; +} + +static int mx3_pm_valid(suspend_state_t state) +{ + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +struct platform_suspend_ops mx3_suspend_ops = { + .valid = mx3_pm_valid, + .prepare = mx3_suspend_prepare, + .enter = mx31_suspend_enter, + .finish = mx3_suspend_finish, +}; + +static int __init mx3_pm_init(void) +{ + printk(KERN_INFO "Power Management for Freescale MX3x\n"); + if (cpu_is_mx35()) + mx3_suspend_ops.enter = mx35_suspend_enter; + suspend_set_ops(&mx3_suspend_ops); + + return 0; +} + +late_initcall(mx3_pm_init); diff --git a/arch/arm/mach-mx3/system.c b/arch/arm/mach-mx3/system.c new file mode 100644 index 000000000000..a2f5442e7da5 --- /dev/null +++ b/arch/arm/mach-mx3/system.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright 2004-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/*! + * @defgroup MSL_MX31 i.MX31 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx3/system.c + * @brief This file contains idle and reset functions. + * + * @ingroup MSL_MX31 + */ + +static int clks_initialized; +static struct clk *sdma_clk, *mbx_clk, *ipu_clk, *mpeg_clk, *vpu_clk, *usb_clk, + *rtic_clk, *nfc_clk, *emi_clk; + +extern int mxc_jtag_enabled; + +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + int emi_gated_off = 0; + + /* + * This should do all the clock switching + * and wait for interrupt tricks. + */ + if (!mxc_jtag_enabled) { + if (clks_initialized == 0) { + clks_initialized = 1; + sdma_clk = clk_get(NULL, "sdma_ahb_clk"); + ipu_clk = clk_get(NULL, "ipu_clk"); + if (cpu_is_mx31()) { + mpeg_clk = clk_get(NULL, "mpeg4_clk"); + mbx_clk = clk_get(NULL, "mbx_clk"); + } else { + vpu_clk = clk_get(NULL, "vpu_clk"); + } + usb_clk = clk_get(NULL, "usb_ahb_clk"); + rtic_clk = clk_get(NULL, "rtic_clk"); + nfc_clk = clk_get(NULL, "nfc_clk"); + emi_clk = clk_get(NULL, "emi_clk"); + } + + if ((clk_get_usecount(sdma_clk) == 0) + && (clk_get_usecount(ipu_clk) <= 1) + && (clk_get_usecount(usb_clk) == 0) + && (clk_get_usecount(rtic_clk) == 0) + && (clk_get_usecount(mpeg_clk) == 0) + && (clk_get_usecount(mbx_clk) == 0) + && (clk_get_usecount(nfc_clk) == 0) + && (clk_get_usecount(vpu_clk) == 0)) { + emi_gated_off = 1; + clk_disable(emi_clk); + } + + cpu_do_idle(); + if (emi_gated_off == 1) + clk_enable(emi_clk); + + } +} + diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 1576d51e676c..2dc41de79f15 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -2,17 +2,122 @@ if ARCH_MX5 config ARCH_MX51 bool - default y + select USB_ARCH_HAS_EHCI + select MXC_TZIC + select ARCH_MXC_IOMUX_V3 + +config ARCH_MX53 + bool + select USB_ARCH_HAS_EHCI select MXC_TZIC select ARCH_MXC_IOMUX_V3 -comment "MX5 platforms:" +config ARCH_MX50 + bool + select ARCH_HAS_RNGC + +config FORCE_MAX_ZONEORDER + int "MAX_ORDER" + default "13" + +config MX5_MULTI_ARCH + bool + default y + select RUNTIME_PHYS_OFFSET + depends on ARCH_MX51 + depends on ARCH_MX50 || ARCH_MX53 + +config MACH_MX51_3DS + bool "Support MX51 3-Stack platform" + select ARCH_MX51 + help + Include support for MX51 3-Stack platform. This includes specific + configurations for the board and its peripherals. config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" + select ARCH_MX51 help Include support for MX51 Babbage platform, also known as MX51EVK in u-boot. This includes specific configurations for the board and its peripherals. +config MACH_MX53_EVK + bool "Support MX53 EVK platform" + select ARCH_MX53 + help + Include support for MX53 EVK platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX53_ARD + bool "Support MX53 ARD platform" + select ARCH_MX53 + help + Include support for MX53 ARD platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX53_SMD + bool "Support MX53 SMD platform" + select ARCH_MX53 + help + Include support for MX53 SMD platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX53_LOCO + bool "Support MX53 LOCO platform" + select ARCH_MX53 + help + Include support for MX53 LOCO platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX50_ARM2 + bool "Support MX50 Armadillo2 platform" + select ARCH_MX50 + help + Include support for MX50 EVK platform. This includes specific + configurations for the board and its peripherals. + +config MACH_MX50_RDP + bool "Support MX50 Reference Design Platform" + select ARCH_MX50 + help + Include support for MX50 RDP platform. This includes specific + configurations for the board and its peripherals. + +comment "MX5x Options:" + +config MXC_SDMA_API + bool "Use SDMA API" + default y + help + This selects the Freescale MXC SDMA API. + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V3 + bool "MXC NFC Hardware Version 3" + depends on ARCH_MX5 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 3 + If unsure, say N. + +config ARCH_MXC_HAS_NFC_V3_2 + bool "MXC NFC Hardware Version 3.2" + depends on ARCH_MXC_HAS_NFC_V3 + default y + help + This selects the Freescale MXC Nand Flash Controller Hardware Version 3.1 + If unsure, say N. + +config SDMA_IRAM + bool "Use Internal RAM for SDMA transfer" + depends on MXC_SDMA_API + help + Support Internal RAM as SDMA buffer or control structures + +config MXC_BLUETOOTH_RFKILL + tristate "MXC Bluetooth rfkill interface support" + depends on RFKILL + ---help--- + Say Y to get the standard rfkill interface of Bluetooth endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index bf23f869ef51..2ef2ceb29859 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -3,7 +3,19 @@ # # Object file lists. -obj-y := cpu.o mm.o clock-mx51.o devices.o +obj-y := system.o iomux.o cpu.o mm.o devices.o serial.o dma.o lpmodes.o pm.o \ +sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o early_setup.o -obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o +obj-$(CONFIG_ARCH_MX51) += clock.o suspend.o +obj-$(CONFIG_ARCH_MX53) += clock.o suspend.o mx53_wp.o pm_da9053.o +obj-$(CONFIG_ARCH_MX50) += clock_mx50.o dmaengine.o dma-apbh.o mx50_suspend.o mx50_ddr_freq.o mx50_wfi.o +obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o +obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_pmic_mc13892.o +obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_pmic_mc13892.o +obj-$(CONFIG_MACH_MX53_ARD) += mx53_ard.o mx53_ard_pmic_ltc3589.o +obj-$(CONFIG_MACH_MX53_SMD) += mx53_smd.o mx53_smd_pmic_da9053.o +obj-$(CONFIG_MACH_MX53_LOCO) += mx53_loco.o mx53_loco_pmic_da9053.o +obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_pmic_mc13892.o +obj-$(CONFIG_MACH_MX50_RDP) += mx50_rdp.o mx50_rdp_pmic_mc13892.o +obj-$(CONFIG_MXC_BLUETOOTH_RFKILL) += mx53_smd_rfkill.o diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot index 9939a19d99a1..434ef85a32dc 100644 --- a/arch/arm/mach-mx5/Makefile.boot +++ b/arch/arm/mach-mx5/Makefile.boot @@ -1,3 +1,9 @@ - zreladdr-y := 0x90008000 -params_phys-y := 0x90000100 -initrd_phys-y := 0x90800000 + zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000 +params_phys-$(CONFIG_ARCH_MX51) := 0x90000100 +initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000 + zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000 +params_phys-$(CONFIG_ARCH_MX53) := 0x70000100 +initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000 + zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000 +params_phys-$(CONFIG_ARCH_MX50) := 0x70000100 +initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000 diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index ed885f9d7b73..9968164f5271 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -19,7 +19,6 @@ #include #include -#include #include #include @@ -29,6 +28,7 @@ #include #include +#include "devices-imx51.h" #include "devices.h" #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ @@ -83,15 +83,15 @@ static struct pad_desc mx51babbage_pads[] = { /* Serial ports */ #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static inline void mxc_init_imx_uart(void) { - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_pdata); + imx51_add_imx_uart(0, &uart_pdata); + imx51_add_imx_uart(1, &uart_pdata); + imx51_add_imx_uart(2, &uart_pdata); } #else /* !SERIAL_IMX */ static inline void mxc_init_imx_uart(void) diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c new file mode 100644 index 000000000000..d598a0663e68 --- /dev/null +++ b/arch/arm/mach-mx5/bus_freq.c @@ -0,0 +1,1108 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file bus_freq.c + * + * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module + * and DVFS CORE module. + * + * The APIs are for setting bus frequency to low or high. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +#define LP_LOW_VOLTAGE 1050000 +#define LP_NORMAL_VOLTAGE 1250000 +#define LP_APM_CLK 24000000 +#define NAND_LP_APM_CLK 12000000 +#define AXI_A_NORMAL_CLK 166250000 +#define AXI_A_CLK_NORMAL_DIV 4 +#define AXI_B_CLK_NORMAL_DIV 5 +#define AHB_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV +#define EMI_SLOW_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV +#define NFC_CLK_NORMAL_DIV 4 +#define SPIN_DELAY 1000000 /* in nanoseconds */ +#define HW_QOS_DISABLE 0x70 +#define HW_QOS_DISABLE_SET 0x74 +#define HW_QOS_DISABLE_CLR 0x78 +#define DDR_TYPE_DDR3 0x0 +#define DDR_TYPE_DDR2 0x1 + +DEFINE_SPINLOCK(ddr_freq_lock); + +static unsigned long lp_normal_rate; +static unsigned long lp_med_rate; +static unsigned long ddr_normal_rate; +static unsigned long ddr_med_rate; +static unsigned long ddr_low_rate; +static int cur_ddr_rate; +static unsigned char mx53_ddr_type; + +static struct clk *ddr_clk; +static struct clk *pll1_sw_clk; +static struct clk *pll1; +static struct clk *pll2; +static struct clk *pll3; +static struct clk *pll4; +static struct clk *main_bus_clk; +static struct clk *axi_a_clk; +static struct clk *axi_b_clk; +static struct clk *cpu_clk; +static struct clk *ddr_hf_clk; +static struct clk *ahb_clk; +static struct clk *ddr_clk; +static struct clk *periph_apm_clk; +static struct clk *lp_apm; +static struct clk *gpc_dvfs_clk; +static struct clk *emi_garb_clk; +static struct clk *epdc_clk; + +static void __iomem *pll1_base; +static void __iomem *pll4_base; + +static void __iomem *qosc_base; + +struct regulator *pll_regulator; + +struct regulator *lp_regulator; +int low_bus_freq_mode; +int high_bus_freq_mode; +int med_bus_freq_mode; + +int bus_freq_scaling_initialized; +char *gp_reg_id; +char *lp_reg_id; + +static struct cpu_wp *cpu_wp_tbl; +static struct device *busfreq_dev; +static int busfreq_suspended; +static int cpu_podf; +/* True if bus_frequency is scaled not using DVFS-PER */ +int bus_freq_scaling_is_active; + +int cpu_wp_nr; +int lp_high_freq; +int lp_med_freq; + +static int lp_voltage; +struct workqueue_struct *voltage_wq; +static struct work_struct voltage_change_handler; +struct completion voltage_change_cmpl; + +void enter_lpapm_mode_mx50(void); +void enter_lpapm_mode_mx51(void); +void enter_lpapm_mode_mx53(void); +void exit_lpapm_mode_mx50(int high_bus_freq); +void exit_lpapm_mode_mx51(void); +void exit_lpapm_mode_mx53(void); +int low_freq_bus_used(void); +void set_ddr_freq(int ddr_freq); +void *ddr_freq_change_iram_base; +void (*change_ddr_freq)(void *ccm_addr, void *databahn_addr, u32 freq) = NULL; + +extern void mx50_ddr_freq_change(u32 ccm_base, + u32 databahn_addr, u32 freq); +extern int dvfs_core_is_active; +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void __iomem *ccm_base; +extern void __iomem *databahn_base; + +struct dvfs_wp dvfs_core_setpoint[] = { + {33, 8, 33, 10, 10, 0x08}, + {26, 0, 33, 20, 10, 0x08}, + {28, 8, 33, 20, 30, 0x08}, + {29, 0, 33, 20, 10, 0x08},}; + +static DEFINE_SPINLOCK(voltage_lock); +struct mutex bus_freq_mutex; + +struct timeval start_time; +struct timeval end_time; + +static void voltage_work_handler(struct work_struct *work) +{ + if (lp_regulator != NULL) { + u32 ret = 0; + ret = regulator_set_voltage(lp_regulator, + lp_voltage, lp_voltage); + udelay(400); + if (ret < 0) { + printk(KERN_ERR "COULD NOT SET LP VOLTAGE!!!!!!\n"); + return; + } + } + complete_all(&voltage_change_cmpl); +} + +int set_low_bus_freq(void) +{ + if (busfreq_suspended) + return 0; + if (bus_freq_scaling_initialized) { + /* can not enter low bus freq, when cpu is in higher freq + * or only have one working point */ + if ((clk_get_rate(cpu_clk) > + cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + || (cpu_wp_nr == 1)) { + return 0; + } + + mutex_lock(&bus_freq_mutex); + + stop_dvfs_per(); + + stop_sdram_autogating(); + + if (cpu_is_mx50()) + enter_lpapm_mode_mx50(); + else if (cpu_is_mx51()) + enter_lpapm_mode_mx51(); + else + enter_lpapm_mode_mx53(); + mutex_unlock(&bus_freq_mutex); + } + return 0; +} + +void enter_lpapm_mode_mx50() +{ + u32 reg; + unsigned long flags; + spin_lock_irqsave(&ddr_freq_lock, flags); + + set_ddr_freq(LP_APM_CLK); + /* Set the parent of main_bus_clk to be PLL3 */ + clk_set_parent(main_bus_clk, pll3); + + /* Set the AHB dividers to be 2. + * Set the dividers so that clock rates + * are not greater than current clock rate. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F) + udelay(10); + + low_bus_freq_mode = 1; + high_bus_freq_mode = 0; + med_bus_freq_mode = 0; + + /* Set the source of main_bus_clk to be lp-apm. */ + clk_set_parent(main_bus_clk, lp_apm); + + /* Set the AHB dividers to be 1. */ + /* Set the dividers to be 1, so the clock rates + * are at 24Mhz + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F) + udelay(10); + + spin_unlock_irqrestore(&ddr_freq_lock, flags); + + spin_lock_irqsave(&voltage_lock, flags); + lp_voltage = LP_LOW_VOLTAGE; + INIT_COMPLETION(voltage_change_cmpl); + queue_work(voltage_wq, &voltage_change_handler); + spin_unlock_irqrestore(&voltage_lock, flags); + + if (clk_get_usecount(pll1_sw_clk) == 1) { + /* Relock PLL1 to 160MHz. */ + clk_set_parent(pll1_sw_clk, pll2); + /* Set the divider to ARM_PODF to 3. */ + __raw_writel(0x02, MXC_CCM_CACRR); + + clk_set_rate(pll1, 160000000); + clk_set_parent(pll1_sw_clk, pll1); + /* Set the divider to ARM_PODF to 1. */ + __raw_writel(0x0, MXC_CCM_CACRR); + } + + udelay(100); +} + +void enter_lpapm_mode_mx51() +{ + u32 reg; + /* Set PLL3 to 133Mhz if no-one is using it. */ + if (clk_get_usecount(pll3) == 0) { + u32 pll3_rate = clk_get_rate(pll3); + + clk_enable(pll3); + clk_set_rate(pll3, clk_round_rate(pll3, 133000000)); + + /*Change the DDR freq to 133Mhz. */ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, ddr_low_rate)); + + /* Set the parent of Periph_apm_clk to be PLL3 */ + clk_set_parent(periph_apm_clk, pll3); + clk_set_parent(main_bus_clk, periph_apm_clk); + + /* Set the dividers to be 1, so the clock rates + * are at 133MHz. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MXC_CCM_CBCDR_EMI_PODF_MASK + | MXC_CCM_CBCDR_NFC_PODF_OFFSET); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET + | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + clk_enable(emi_garb_clk); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) + udelay(10); + clk_disable(emi_garb_clk); + + low_bus_freq_mode = 1; + high_bus_freq_mode = 0; + med_bus_freq_mode = 0; + + /* Set the source of Periph_APM_Clock to be lp-apm. */ + clk_set_parent(periph_apm_clk, lp_apm); + + /* Set PLL3 back to original rate. */ + clk_set_rate(pll3, clk_round_rate(pll3, pll3_rate)); + clk_disable(pll3); + } +} + +void enter_lpapm_mode_mx53() +{ + u32 reg; + struct timespec nstimeofday; + struct timespec curtime; + + /* TBD: Reduce DDR frequency for DDR2 */ + /* if (mx53_ddr_type == DDR_TYPE_DDR2) { + } */ + + /* move cpu clk to pll2, 400 / 3 = 133Mhz for cpu */ + /* Change the source of pll1_sw_clk to be the step_clk */ + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + + cpu_podf = __raw_readl(MXC_CCM_CACRR); + reg = __raw_readl(MXC_CCM_CDHIPR); + if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0) + __raw_writel(0x2, MXC_CCM_CACRR); + else + printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n"); + clk_set_parent(pll1_sw_clk, pll2); + + /* ahb = pll2/8, axi_b = pll2/8, axi_a = pll2/1*/ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 7 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & + (MXC_CCM_CDHIPR_AXI_A_PODF_BUSY | + MXC_CCM_CDHIPR_AXI_B_PODF_BUSY | + MXC_CCM_CDHIPR_AHB_PODF_BUSY)) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec + > SPIN_DELAY) + panic("low bus freq set rate error\n"); + } + + /* keep this infront of propagating */ + low_bus_freq_mode = 1; + high_bus_freq_mode = 0; + med_bus_freq_mode = 0; + + if (clk_get_usecount(pll1) == 0) { + reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL); + reg &= ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); + } + if (clk_get_usecount(pll4) == 0) { + reg = __raw_readl(pll4_base + MXC_PLL_DP_CTL); + reg &= ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pll4_base + MXC_PLL_DP_CTL); + } +} + +int set_high_bus_freq(int high_bus_freq) +{ + u32 reg; + if (bus_freq_scaling_initialized) { + mutex_lock(&bus_freq_mutex); + /* + * If the CPU freq is 800MHz, set the bus to the high + * setpoint (133MHz) and DDR to 200MHz. + */ + if ((clk_get_rate(cpu_clk) > + cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + || lp_high_freq) + high_bus_freq = 1; + + stop_sdram_autogating(); + + if (low_bus_freq_mode) { + /* Relock PLL3 to 133MHz */ + if (cpu_is_mx50()) + exit_lpapm_mode_mx50(high_bus_freq); + else if (cpu_is_mx51()) + exit_lpapm_mode_mx51(); + else + exit_lpapm_mode_mx53(); + start_dvfs_per(); + } + if (bus_freq_scaling_is_active) { + if (!high_bus_freq_mode && high_bus_freq) { + if (cpu_is_mx50()) { + if (med_bus_freq_mode) { + /* Increase SYS_CLK */ + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK; + reg |= 4 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET; + __raw_writel(reg, MXC_CCM_CLK_SYS); + + /* Set the dividers to the default dividers */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + |1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + |2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + while (__raw_readl(MXC_CCM_CDHIPR) & 0xF) + udelay(10); + } + } else { + clk_set_rate(ahb_clk, + clk_round_rate(ahb_clk, + lp_normal_rate)); + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, + ddr_normal_rate)); + } + /* Set to the high setpoint. */ + high_bus_freq_mode = 1; + low_bus_freq_mode = 0; + med_bus_freq_mode = 0; + } else if (!med_bus_freq_mode && !high_bus_freq) { + if (cpu_is_mx50()) { + /* Set the dividers to the medium setpoint dividers */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + |3 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + |5 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + while (__raw_readl(MXC_CCM_CDHIPR) & 0xF) + udelay(10); + /* Reduce SYS_CLK */ + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK; + reg |= 8 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET; + __raw_writel(reg, MXC_CCM_CLK_SYS); + } else { + if (cpu_is_mx51()) + clk_set_rate(ddr_hf_clk, + clk_round_rate( + ddr_hf_clk, + ddr_low_rate)); + clk_set_rate(ahb_clk, + clk_round_rate( + ahb_clk, lp_med_rate)); + } + /* Set to the medium setpoint. */ + high_bus_freq_mode = 0; + low_bus_freq_mode = 0; + med_bus_freq_mode = 1; + } + if (cpu_is_mx50()) { + if (med_bus_freq_mode && + (cur_ddr_rate != ddr_med_rate)) + set_ddr_freq(ddr_med_rate); + if (high_bus_freq_mode && + (cur_ddr_rate != ddr_normal_rate)) + set_ddr_freq(ddr_normal_rate); + } + } + start_sdram_autogating(); + mutex_unlock(&bus_freq_mutex); + } + return 0; +} + +void exit_lpapm_mode_mx50(int high_bus_freq) +{ + u32 reg; + unsigned long flags; + + if (clk_get_usecount(pll1_sw_clk) == 1) { + /* Relock PLL1 to 800MHz. */ + clk_set_parent(pll1_sw_clk, pll2); + /* Set the divider to ARM_PODF to 3, cpu is at 160MHz. */ + __raw_writel(0x02, MXC_CCM_CACRR); + + clk_set_rate(pll1, 800000000); + clk_set_parent(pll1_sw_clk, pll1); + /* Set the divider to ARM_PODF to 5. */ + __raw_writel(0x4, MXC_CCM_CACRR); + } + + if (!completion_done(&voltage_change_cmpl)) + wait_for_completion_interruptible(&voltage_change_cmpl); + spin_lock_irqsave(&voltage_lock, flags); + if (lp_voltage != LP_NORMAL_VOLTAGE) { + INIT_COMPLETION(voltage_change_cmpl); + lp_voltage = LP_NORMAL_VOLTAGE; + if (!queue_work(voltage_wq, &voltage_change_handler)) + printk(KERN_ERR "WORK_NOT_ADDED\n"); + spin_unlock_irqrestore(&voltage_lock, flags); + wait_for_completion_interruptible(&voltage_change_cmpl); + } else { + spin_unlock_irqrestore(&voltage_lock, flags); + if (!completion_done(&voltage_change_cmpl)) + wait_for_completion_interruptible(&voltage_change_cmpl); + } + + spin_lock_irqsave(&ddr_freq_lock, flags); + if (!low_bus_freq_mode) { + spin_unlock_irqrestore(&ddr_freq_lock, flags); + return; + } + + /* Temporarily set the dividers when the source is PLL3. + * No clock rate is above 133MHz. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + |1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + |1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + while (__raw_readl(MXC_CCM_CDHIPR) & 0xF) + udelay(10); + + clk_set_parent(main_bus_clk, pll3); + + if (bus_freq_scaling_is_active && !high_bus_freq) { + /* Set the dividers to the medium setpoint dividers */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + |3 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + |5 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + while (__raw_readl(MXC_CCM_CDHIPR) & 0xF) + udelay(10); + + /*Set the main_bus_clk parent to be PLL2. */ + clk_set_parent(main_bus_clk, pll2); + + /* Set to the medium setpoint. */ + high_bus_freq_mode = 0; + low_bus_freq_mode = 0; + med_bus_freq_mode = 1; + set_ddr_freq(ddr_med_rate); + } else { + /* Set the dividers to the default dividers */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + |1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + |2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + while (__raw_readl(MXC_CCM_CDHIPR) & 0xF) + udelay(10); + + /*Set the main_bus_clk parent to be PLL2. */ + clk_set_parent(main_bus_clk, pll2); + + /* Set to the high setpoint. */ + high_bus_freq_mode = 1; + low_bus_freq_mode = 0; + med_bus_freq_mode = 0; + set_ddr_freq(ddr_normal_rate); + } + + spin_unlock_irqrestore(&ddr_freq_lock, flags); + + udelay(100); +} + +void exit_lpapm_mode_mx51() +{ + u32 reg; + + /* Temporarily Set the dividers is PLL3. + * No clock rate is above 133MHz. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MXC_CCM_CBCDR_EMI_PODF_MASK + | MXC_CCM_CBCDR_NFC_PODF_OFFSET); + reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 1 << MXC_CCM_CBCDR_EMI_PODF_OFFSET + | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + clk_enable(emi_garb_clk); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) + udelay(10); + clk_disable(emi_garb_clk); + + clk_set_parent(periph_apm_clk, pll3); + + /* Set the dividers to the default dividers */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MXC_CCM_CBCDR_EMI_PODF_MASK + | MXC_CCM_CBCDR_NFC_PODF_OFFSET); + reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET + | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + clk_enable(emi_garb_clk); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) + udelay(10); + + low_bus_freq_mode = 0; + high_bus_freq_mode = 1; + clk_disable(emi_garb_clk); + + /*Set the main_bus_clk parent to be PLL2. */ + clk_set_parent(main_bus_clk, pll2); + + /*Change the DDR freq to 200MHz*/ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, ddr_normal_rate)); +} + +void exit_lpapm_mode_mx53() +{ + u32 reg; + struct timespec nstimeofday; + struct timespec curtime; + + + /* move cpu clk to pll1 */ + reg = __raw_readl(MXC_CCM_CDHIPR); + if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) != 0) + __raw_writel(cpu_podf & 0x7, + MXC_CCM_CACRR); + else + printk(KERN_DEBUG + "ARM_PODF still in busy!!!!\n"); + + clk_set_parent(pll1_sw_clk, pll1); + + + /* ahb = 400/3, axi_b = 400/2, axi_a = 400*/ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & + (MXC_CCM_CDHIPR_AXI_A_PODF_BUSY | + MXC_CCM_CDHIPR_AXI_B_PODF_BUSY | + MXC_CCM_CDHIPR_AHB_PODF_BUSY)) { + getnstimeofday(&curtime); + if (curtime.tv_nsec + - nstimeofday.tv_nsec + > SPIN_DELAY) + panic("bus freq error\n"); + } + + /* keep this infront of propagating */ + low_bus_freq_mode = 0; + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + + /* TBD: Restore DDR frequency for DDR2 */ + /* if (mx53_ddr_type == DDR_TYPE_DDR2) { + } */ +} + +int can_change_ddr_freq(void) +{ + if (clk_get_usecount(epdc_clk) == 0) + return 1; + return 0; +} + +void set_ddr_freq(int ddr_rate) +{ + u32 reg; + unsigned long flags; + + if (!can_change_ddr_freq()) + return; + + spin_lock_irqsave(&ddr_freq_lock, flags); + local_flush_tlb_all(); + flush_cache_all(); + + /* Disable all masters from accessing the DDR. */ + reg = __raw_readl(qosc_base + HW_QOS_DISABLE); + reg |= 0xFFE; + __raw_writel(reg, qosc_base + HW_QOS_DISABLE_SET); + udelay(100); + + /* Set the DDR to default freq. + */ + change_ddr_freq(ccm_base, databahn_base, ddr_rate); + + /* Enable all masters to access the DDR. */ + __raw_writel(reg, qosc_base + HW_QOS_DISABLE_CLR); + + spin_unlock_irqrestore(&ddr_freq_lock, flags); + cur_ddr_rate = ddr_rate; + udelay(100); +} + +int low_freq_bus_used(void) +{ + if ((lp_high_freq == 0) + && (lp_med_freq == 0)) + return 1; + else + return 0; +} + +void setup_pll(void) +{ +} + +static ssize_t bus_freq_scaling_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (bus_freq_scaling_is_active) + return sprintf(buf, "Bus frequency scaling is enabled\n"); + else + return sprintf(buf, "Bus frequency scaling is disabled\n"); +} + +static ssize_t bus_freq_scaling_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + u32 reg; + + if (strncmp(buf, "1", 1) == 0) { + if (dvfs_per_active()) { + printk(KERN_INFO "bus frequency scaling cannot be\ + enabled when DVFS-PER is active\n"); + return size; + } + if (!cpu_is_mx50()) { + /* Initialize DVFS-PODF to 0. */ + reg = __raw_readl(MXC_CCM_CDCR); + reg &= ~MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK; + __raw_writel(reg, MXC_CCM_CDCR); + clk_set_parent(main_bus_clk, pll2); + } + bus_freq_scaling_is_active = 1; + set_high_bus_freq(0); + } else if (strncmp(buf, "0", 1) == 0) { + if (bus_freq_scaling_is_active) + set_high_bus_freq(1); + bus_freq_scaling_is_active = 0; + } + + return size; +} + +static int busfreq_suspend(struct platform_device *pdev, pm_message_t message) +{ + if (low_bus_freq_mode) + set_high_bus_freq(1); + busfreq_suspended = 1; + return 0; +} + +static int busfreq_resume(struct platform_device *pdev) +{ + busfreq_suspended = 0; + return 0; +} + +static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show, + bus_freq_scaling_enable_store); + +/*! + * This is the probe routine for the bus frequency driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit busfreq_probe(struct platform_device *pdev) +{ + int err = 0; + unsigned long pll2_rate, pll1_rate; + unsigned long iram_paddr; + struct mxc_bus_freq_platform_data *p_bus_freq_data; + + p_bus_freq_data = pdev->dev.platform_data; + gp_reg_id = p_bus_freq_data->gp_reg_id; + lp_reg_id = p_bus_freq_data->lp_reg_id; + + pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); + if (cpu_is_mx53()) + pll4_base = ioremap(MX53_BASE_ADDR(PLL4_BASE_ADDR), SZ_4K); + + busfreq_dev = &pdev->dev; + + main_bus_clk = clk_get(NULL, "main_bus_clk"); + if (IS_ERR(main_bus_clk)) { + printk(KERN_DEBUG "%s: failed to get main_bus_clk\n", + __func__); + return PTR_ERR(main_bus_clk); + } + + pll1_sw_clk = clk_get(NULL, "pll1_sw_clk"); + if (IS_ERR(pll1_sw_clk)) { + printk(KERN_DEBUG "%s: failed to get pll1_sw_clk\n", __func__); + return PTR_ERR(pll1_sw_clk); + } + + pll1 = clk_get(NULL, "pll1_main_clk"); + if (IS_ERR(pll1)) { + printk(KERN_DEBUG "%s: failed to get pll1\n", __func__); + return PTR_ERR(pll1); + } + + pll2 = clk_get(NULL, "pll2"); + if (IS_ERR(pll2)) { + printk(KERN_DEBUG "%s: failed to get pll2\n", __func__); + return PTR_ERR(pll2); + } + + pll3 = clk_get(NULL, "pll3"); + if (IS_ERR(pll3)) { + printk(KERN_DEBUG "%s: failed to get pll3\n", __func__); + return PTR_ERR(pll3); + } + + if (cpu_is_mx53()) { + pll4 = clk_get(NULL, "pll4"); + if (IS_ERR(pll4)) { + printk(KERN_DEBUG "%s: failed to get pll4\n", __func__); + return PTR_ERR(pll4); + } + } + + axi_a_clk = clk_get(NULL, "axi_a_clk"); + if (IS_ERR(axi_a_clk)) { + printk(KERN_DEBUG "%s: failed to get axi_a_clk\n", + __func__); + return PTR_ERR(axi_a_clk); + } + + axi_b_clk = clk_get(NULL, "axi_b_clk"); + if (IS_ERR(axi_b_clk)) { + printk(KERN_DEBUG "%s: failed to get axi_b_clk\n", + __func__); + return PTR_ERR(axi_b_clk); + } + + ddr_clk = clk_get(NULL, "ddr_clk"); + if (IS_ERR(ddr_clk)) { + printk(KERN_DEBUG "%s: failed to get ddr_clk\n", + __func__); + return PTR_ERR(ddr_clk); + } + + ddr_hf_clk = clk_get_parent(ddr_clk); + + if (IS_ERR(ddr_hf_clk)) { + printk(KERN_DEBUG "%s: failed to get ddr_hf_clk\n", + __func__); + return PTR_ERR(ddr_hf_clk); + } + + ahb_clk = clk_get(NULL, "ahb_clk"); + if (IS_ERR(ahb_clk)) { + printk(KERN_DEBUG "%s: failed to get ahb_clk\n", + __func__); + return PTR_ERR(ahb_clk); + } + + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_DEBUG "%s: failed to get cpu_clk\n", + __func__); + return PTR_ERR(cpu_clk); + } + + if (cpu_is_mx51()) + emi_garb_clk = clk_get(NULL, "emi_intr_clk.1"); + else if (cpu_is_mx53()) + emi_garb_clk = clk_get(NULL, "emi_intr_clk.1"); + else + emi_garb_clk = clk_get(NULL, "ocram_clk"); + if (IS_ERR(emi_garb_clk)) { + printk(KERN_DEBUG "%s: failed to get emi_garb_clk\n", + __func__); + return PTR_ERR(emi_garb_clk); + } + + if (cpu_is_mx51() || cpu_is_mx53()) { + periph_apm_clk = clk_get(NULL, "periph_apm_clk"); + if (IS_ERR(periph_apm_clk)) { + printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n", + __func__); + return PTR_ERR(periph_apm_clk); + } + } + + lp_apm = clk_get(NULL, "lp_apm"); + if (IS_ERR(lp_apm)) { + printk(KERN_DEBUG "%s: failed to get lp_apm\n", + __func__); + return PTR_ERR(lp_apm); + } + + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); + if (IS_ERR(gpc_dvfs_clk)) { + printk(KERN_DEBUG "%s: failed to get gpc_dvfs_clk\n", __func__); + return PTR_ERR(gpc_dvfs_clk); + } + + err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + if (err) { + printk(KERN_ERR + "Unable to register sysdev entry for BUSFREQ"); + return err; + } + + pll1_rate = clk_get_rate(pll1_sw_clk); + pll2_rate = clk_get_rate(pll2); + + if (pll2_rate == 665000000) { + /* for mx51 */ + lp_normal_rate = pll2_rate / 5; + lp_med_rate = pll2_rate / 8; + ddr_normal_rate = pll1_rate / 4; /* 200M */ + ddr_low_rate = pll1_rate / 6; /* 133M */ + } else if (pll2_rate == 600000000) { + /* for mx53 evk rev.A */ + lp_normal_rate = pll2_rate / 5; + lp_med_rate = pll2_rate / 8; + ddr_normal_rate = pll2_rate / 2; + ddr_low_rate = pll2_rate / 2; + } else if (pll2_rate == 400000000) { + if (cpu_is_mx50()) { + lp_normal_rate = pll2_rate / 3; + ddr_normal_rate = clk_get_rate(ddr_clk); + lp_med_rate = pll2_rate / 6; + ddr_low_rate = LP_APM_CLK; + ddr_med_rate = pll2_rate / 3; + } + } + + /* for mx53 */ + if (cpu_is_mx53()) { + /* set DDR type */ + if (machine_is_mx53_evk() || machine_is_mx53_ard()) + mx53_ddr_type = DDR_TYPE_DDR2; + else + mx53_ddr_type = DDR_TYPE_DDR3; + if (mx53_ddr_type == DDR_TYPE_DDR2) { + /* DDR2 */ + lp_normal_rate = pll2_rate / 3; + lp_med_rate = pll2_rate / 5; + ddr_normal_rate = pll2_rate / 1; + ddr_low_rate = pll2_rate / 3; + } else { + /* DDR3: DDR3 frequency can not be lower than 300MHZ */ + lp_normal_rate = pll2_rate / 3; + lp_med_rate = pll2_rate / 5; + ddr_normal_rate = pll2_rate / 1; + ddr_low_rate = pll2_rate / 1; + } + } + + if (cpu_is_mx50()) { + u32 reg; + + iram_alloc(SZ_8K, &iram_paddr); + /* Need to remap the area here since we want the memory region + to be executable. */ + ddr_freq_change_iram_base = __arm_ioremap(iram_paddr, + SZ_8K, MT_HIGH_VECTORS); + memcpy(ddr_freq_change_iram_base, mx50_ddr_freq_change, SZ_8K); + change_ddr_freq = (void *)ddr_freq_change_iram_base; + cur_ddr_rate = ddr_normal_rate; + + lp_regulator = regulator_get(NULL, lp_reg_id); + if (IS_ERR(lp_regulator)) { + printk(KERN_DEBUG + "%s: failed to get lp regulator\n", __func__); + return PTR_ERR(lp_regulator); + } + + qosc_base = ioremap(QOSC_BASE_ADDR, SZ_4K); + /* Enable the QoSC */ + reg = __raw_readl(qosc_base); + reg &= ~0xC0000000; + __raw_writel(reg, qosc_base); + + voltage_wq = create_rt_workqueue("voltage_change"); + INIT_WORK(&voltage_change_handler, voltage_work_handler); + + init_completion(&voltage_change_cmpl); + + epdc_clk = clk_get(NULL, "epdc_axi"); + if (IS_ERR(epdc_clk)) { + printk(KERN_DEBUG "%s: failed to get epdc_axi_clk\n", + __func__); + return PTR_ERR(epdc_clk); + } + } + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + low_bus_freq_mode = 0; + high_bus_freq_mode = 1; + med_bus_freq_mode = 0; + bus_freq_scaling_is_active = 0; + bus_freq_scaling_initialized = 1; + + mutex_init(&bus_freq_mutex); + return 0; +} + +static struct platform_driver busfreq_driver = { + .driver = { + .name = "busfreq", + }, + .probe = busfreq_probe, + .suspend = busfreq_suspend, + .resume = busfreq_resume, +}; + +/*! + * Initialise the busfreq_driver. + * + * @return The function always returns 0. + */ + +static int __init busfreq_init(void) +{ + if (platform_driver_register(&busfreq_driver) != 0) { + printk(KERN_ERR "busfreq_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "Bus freq driver module loaded\n"); + return 0; +} + +static void __exit busfreq_cleanup(void) +{ + sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&busfreq_driver); + bus_freq_scaling_initialized = 0; +} + +module_init(busfreq_init); +module_exit(busfreq_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("BusFreq driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c deleted file mode 100644 index d9f612d3370e..000000000000 --- a/arch/arm/mach-mx5/clock-mx51.c +++ /dev/null @@ -1,871 +0,0 @@ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009-2010 Amit Kucheria - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "crm_regs.h" - -/* External clock values passed-in by the board code */ -static unsigned long external_high_reference, external_low_reference; -static unsigned long oscillator_reference, ckih2_reference; - -static struct clk osc_clk; -static struct clk pll1_main_clk; -static struct clk pll1_sw_clk; -static struct clk pll2_sw_clk; -static struct clk pll3_sw_clk; -static struct clk lp_apm_clk; -static struct clk periph_apm_clk; -static struct clk ahb_clk; -static struct clk ipg_clk; -static struct clk usboh3_clk; - -#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ - -static int _clk_ccgr_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); - - return 0; -} - -static void _clk_ccgr_disable(struct clk *clk) -{ - u32 reg; - reg = __raw_readl(clk->enable_reg); - reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); - -} - -static void _clk_ccgr_disable_inwait(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); - reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); -} - -/* - * For the 4-to-1 muxed input clock - */ -static inline u32 _get_mux(struct clk *parent, struct clk *m0, - struct clk *m1, struct clk *m2, struct clk *m3) -{ - if (parent == m0) - return 0; - else if (parent == m1) - return 1; - else if (parent == m2) - return 2; - else if (parent == m3) - return 3; - else - BUG(); - - return -EINVAL; -} - -static inline void __iomem *_get_pll_base(struct clk *pll) -{ - if (pll == &pll1_main_clk) - return MX51_DPLL1_BASE; - else if (pll == &pll2_sw_clk) - return MX51_DPLL2_BASE; - else if (pll == &pll3_sw_clk) - return MX51_DPLL3_BASE; - else - BUG(); - - return NULL; -} - -static unsigned long clk_pll_get_rate(struct clk *clk) -{ - long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; - unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; - void __iomem *pllbase; - s64 temp; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - pllbase = _get_pll_base(clk); - - dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); - pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; - dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; - - if (pll_hfsm == 0) { - dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); - dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); - dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); - } else { - dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); - dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); - dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); - } - pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; - mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; - mfi = (mfi <= 5) ? 5 : mfi; - mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; - mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; - /* Sign extend to 32-bits */ - if (mfn >= 0x04000000) { - mfn |= 0xFC000000; - mfn_abs = -mfn; - } - - ref_clk = 2 * parent_rate; - if (dbl != 0) - ref_clk *= 2; - - ref_clk /= (pdf + 1); - temp = (u64) ref_clk * mfn_abs; - do_div(temp, mfd + 1); - if (mfn < 0) - temp = -temp; - temp = (ref_clk * mfi) + temp; - - return temp; -} - -static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg; - void __iomem *pllbase; - - long mfi, pdf, mfn, mfd = 999999; - s64 temp64; - unsigned long quad_parent_rate; - unsigned long pll_hfsm, dp_ctl; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - pllbase = _get_pll_base(clk); - - quad_parent_rate = 4 * parent_rate; - pdf = mfi = -1; - while (++pdf < 16 && mfi < 5) - mfi = rate * (pdf+1) / quad_parent_rate; - if (mfi > 15) - return -EINVAL; - pdf--; - - temp64 = rate * (pdf+1) - quad_parent_rate * mfi; - do_div(temp64, quad_parent_rate/1000000); - mfn = (long)temp64; - - dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); - /* use dpdck0_2 */ - __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); - pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; - if (pll_hfsm == 0) { - reg = mfi << 4 | pdf; - __raw_writel(reg, pllbase + MXC_PLL_DP_OP); - __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); - __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); - } else { - reg = mfi << 4 | pdf; - __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); - __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); - __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); - } - - return 0; -} - -static int _clk_pll_enable(struct clk *clk) -{ - u32 reg; - void __iomem *pllbase; - int i = 0; - - pllbase = _get_pll_base(clk); - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); - - /* Wait for lock */ - do { - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); - if (reg & MXC_PLL_DP_CTL_LRF) - break; - - udelay(1); - } while (++i < MAX_DPLL_WAIT_TRIES); - - if (i == MAX_DPLL_WAIT_TRIES) { - pr_err("MX5: pll locking failed\n"); - return -EINVAL; - } - - return 0; -} - -static void _clk_pll_disable(struct clk *clk) -{ - u32 reg; - void __iomem *pllbase; - - pllbase = _get_pll_base(clk); - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); -} - -static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg, step; - - reg = __raw_readl(MXC_CCM_CCSR); - - /* When switching from pll_main_clk to a bypass clock, first select a - * multiplexed clock in 'step_sel', then shift the glitchless mux - * 'pll1_sw_clk_sel'. - * - * When switching back, do it in reverse order - */ - if (parent == &pll1_main_clk) { - /* Switch to pll1_main_clk */ - reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; - __raw_writel(reg, MXC_CCM_CCSR); - /* step_clk mux switched to lp_apm, to save power. */ - reg = __raw_readl(MXC_CCM_CCSR); - reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; - reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM << - MXC_CCM_CCSR_STEP_SEL_OFFSET); - } else { - if (parent == &lp_apm_clk) { - step = MXC_CCM_CCSR_STEP_SEL_LP_APM; - } else if (parent == &pll2_sw_clk) { - step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED; - } else if (parent == &pll3_sw_clk) { - step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED; - } else - return -EINVAL; - - reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; - reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET); - - __raw_writel(reg, MXC_CCM_CCSR); - /* Switch to step_clk */ - reg = __raw_readl(MXC_CCM_CCSR); - reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; - } - __raw_writel(reg, MXC_CCM_CCSR); - return 0; -} - -static unsigned long clk_pll1_sw_get_rate(struct clk *clk) -{ - u32 reg, div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - reg = __raw_readl(MXC_CCM_CCSR); - - if (clk->parent == &pll2_sw_clk) { - div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> - MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; - } else if (clk->parent == &pll3_sw_clk) { - div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> - MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; - } else - div = 1; - return parent_rate / div; -} - -static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CCSR); - - if (parent == &pll2_sw_clk) - reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; - else - reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; - - __raw_writel(reg, MXC_CCM_CCSR); - return 0; -} - -static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - if (parent == &osc_clk) - reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; - else - return -EINVAL; - - __raw_writel(reg, MXC_CCM_CCSR); - - return 0; -} - -static unsigned long clk_arm_get_rate(struct clk *clk) -{ - u32 cacrr, div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - cacrr = __raw_readl(MXC_CCM_CACRR); - div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; - - return parent_rate / div; -} - -static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg, mux; - int i = 0; - - mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); - - reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; - __raw_writel(reg, MXC_CCM_CBCMR); - - /* Wait for lock */ - do { - reg = __raw_readl(MXC_CCM_CDHIPR); - if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)) - break; - - udelay(1); - } while (++i < MAX_DPLL_WAIT_TRIES); - - if (i == MAX_DPLL_WAIT_TRIES) { - pr_err("MX5: Set parent for periph_apm clock failed\n"); - return -EINVAL; - } - - return 0; -} - -static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CBCDR); - - if (parent == &pll2_sw_clk) - reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; - else if (parent == &periph_apm_clk) - reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; - else - return -EINVAL; - - __raw_writel(reg, MXC_CCM_CBCDR); - - return 0; -} - -static struct clk main_bus_clk = { - .parent = &pll2_sw_clk, - .set_parent = _clk_main_bus_set_parent, -}; - -static unsigned long clk_ahb_get_rate(struct clk *clk) -{ - u32 reg, div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> - MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; - return parent_rate / div; -} - - -static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, div; - unsigned long parent_rate; - int i = 0; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (div > 8 || div < 1 || ((parent_rate / div) != rate)) - return -EINVAL; - - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; - reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; - __raw_writel(reg, MXC_CCM_CBCDR); - - /* Wait for lock */ - do { - reg = __raw_readl(MXC_CCM_CDHIPR); - if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY)) - break; - - udelay(1); - } while (++i < MAX_DPLL_WAIT_TRIES); - - if (i == MAX_DPLL_WAIT_TRIES) { - pr_err("MX5: clk_ahb_set_rate failed\n"); - return -EINVAL; - } - - return 0; -} - -static unsigned long _clk_ahb_round_rate(struct clk *clk, - unsigned long rate) -{ - u32 div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - div = parent_rate / rate; - if (div > 8) - div = 8; - else if (div == 0) - div++; - return parent_rate / div; -} - - -static int _clk_max_enable(struct clk *clk) -{ - u32 reg; - - _clk_ccgr_enable(clk); - - /* Handshake with MAX when LPM is entered. */ - reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); - - return 0; -} - -static void _clk_max_disable(struct clk *clk) -{ - u32 reg; - - _clk_ccgr_disable_inwait(clk); - - /* No Handshake with MAX when LPM is entered as its disabled. */ - reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; - __raw_writel(reg, MXC_CCM_CLPCR); -} - -static unsigned long clk_ipg_get_rate(struct clk *clk) -{ - u32 reg, div; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> - MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; - - return parent_rate / div; -} - -static unsigned long clk_ipg_per_get_rate(struct clk *clk) -{ - u32 reg, prediv1, prediv2, podf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { - /* the main_bus_clk is the one before the DVFS engine */ - reg = __raw_readl(MXC_CCM_CBCDR); - prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> - MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; - prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> - MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; - podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> - MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; - return parent_rate / (prediv1 * prediv2 * podf); - } else if (clk->parent == &ipg_clk) - return parent_rate; - else - BUG(); -} - -static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CBCMR); - - reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; - reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; - - if (parent == &ipg_clk) - reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; - else if (parent == &lp_apm_clk) - reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; - else if (parent != &main_bus_clk) - return -EINVAL; - - __raw_writel(reg, MXC_CCM_CBCMR); - - return 0; -} - -static unsigned long clk_uart_get_rate(struct clk *clk) -{ - u32 reg, prediv, podf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - reg = __raw_readl(MXC_CCM_CSCDR1); - prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> - MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; - podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; - - return parent_rate / (prediv * podf); -} - -static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg, mux; - - mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, - &lp_apm_clk); - reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; - __raw_writel(reg, MXC_CCM_CSCMR1); - - return 0; -} - -static unsigned long clk_usboh3_get_rate(struct clk *clk) -{ - u32 reg, prediv, podf; - unsigned long parent_rate; - - parent_rate = clk_get_rate(clk->parent); - - reg = __raw_readl(MXC_CCM_CSCDR1); - prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> - MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; - podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; - - return parent_rate / (prediv * podf); -} - -static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg, mux; - - mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, - &lp_apm_clk); - reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; - __raw_writel(reg, MXC_CCM_CSCMR1); - - return 0; -} - -static unsigned long get_high_reference_clock_rate(struct clk *clk) -{ - return external_high_reference; -} - -static unsigned long get_low_reference_clock_rate(struct clk *clk) -{ - return external_low_reference; -} - -static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) -{ - return oscillator_reference; -} - -static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) -{ - return ckih2_reference; -} - -/* External high frequency clock */ -static struct clk ckih_clk = { - .get_rate = get_high_reference_clock_rate, -}; - -static struct clk ckih2_clk = { - .get_rate = get_ckih2_reference_clock_rate, -}; - -static struct clk osc_clk = { - .get_rate = get_oscillator_reference_clock_rate, -}; - -/* External low frequency (32kHz) clock */ -static struct clk ckil_clk = { - .get_rate = get_low_reference_clock_rate, -}; - -static struct clk pll1_main_clk = { - .parent = &osc_clk, - .get_rate = clk_pll_get_rate, - .enable = _clk_pll_enable, - .disable = _clk_pll_disable, -}; - -/* Clock tree block diagram (WIP): - * CCM: Clock Controller Module - * - * PLL output -> | - * | CCM Switcher -> CCM_CLK_ROOT_GEN -> - * PLL bypass -> | - * - */ - -/* PLL1 SW supplies to ARM core */ -static struct clk pll1_sw_clk = { - .parent = &pll1_main_clk, - .set_parent = _clk_pll1_sw_set_parent, - .get_rate = clk_pll1_sw_get_rate, -}; - -/* PLL2 SW supplies to AXI/AHB/IP buses */ -static struct clk pll2_sw_clk = { - .parent = &osc_clk, - .get_rate = clk_pll_get_rate, - .set_rate = _clk_pll_set_rate, - .set_parent = _clk_pll2_sw_set_parent, - .enable = _clk_pll_enable, - .disable = _clk_pll_disable, -}; - -/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ -static struct clk pll3_sw_clk = { - .parent = &osc_clk, - .set_rate = _clk_pll_set_rate, - .get_rate = clk_pll_get_rate, - .enable = _clk_pll_enable, - .disable = _clk_pll_disable, -}; - -/* Low-power Audio Playback Mode clock */ -static struct clk lp_apm_clk = { - .parent = &osc_clk, - .set_parent = _clk_lp_apm_set_parent, -}; - -static struct clk periph_apm_clk = { - .parent = &pll1_sw_clk, - .set_parent = _clk_periph_apm_set_parent, -}; - -static struct clk cpu_clk = { - .parent = &pll1_sw_clk, - .get_rate = clk_arm_get_rate, -}; - -static struct clk ahb_clk = { - .parent = &main_bus_clk, - .get_rate = clk_ahb_get_rate, - .set_rate = _clk_ahb_set_rate, - .round_rate = _clk_ahb_round_rate, -}; - -/* Main IP interface clock for access to registers */ -static struct clk ipg_clk = { - .parent = &ahb_clk, - .get_rate = clk_ipg_get_rate, -}; - -static struct clk ipg_perclk = { - .parent = &lp_apm_clk, - .get_rate = clk_ipg_per_get_rate, - .set_parent = _clk_ipg_per_set_parent, -}; - -static struct clk uart_root_clk = { - .parent = &pll2_sw_clk, - .get_rate = clk_uart_get_rate, - .set_parent = _clk_uart_set_parent, -}; - -static struct clk usboh3_clk = { - .parent = &pll2_sw_clk, - .get_rate = clk_usboh3_get_rate, - .set_parent = _clk_usboh3_set_parent, -}; - -static struct clk ahb_max_clk = { - .parent = &ahb_clk, - .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, - .enable = _clk_max_enable, - .disable = _clk_max_disable, -}; - -static struct clk aips_tz1_clk = { - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable_inwait, -}; - -static struct clk aips_tz2_clk = { - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, - .enable = _clk_ccgr_enable, - .disable = _clk_ccgr_disable_inwait, -}; - -static struct clk gpt_32k_clk = { - .id = 0, - .parent = &ckil_clk, -}; - -#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = gr, \ - .set_rate = sr, \ - .enable = _clk_ccgr_enable, \ - .disable = _clk_ccgr_disable, \ - .parent = p, \ - .secondary = s, \ - } - -/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, - get_rate, set_rate, parent, secondary); */ - -/* Shared peripheral bus arbiter */ -DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, - NULL, NULL, &ipg_clk, NULL); - -/* UART */ -DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, - NULL, NULL, &uart_root_clk, NULL); -DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, &uart_root_clk, NULL); -DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, - NULL, NULL, &uart_root_clk, NULL); -DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, - NULL, NULL, &ipg_clk, &aips_tz1_clk); -DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, - NULL, NULL, &ipg_clk, &aips_tz1_clk); -DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, - NULL, NULL, &ipg_clk, &spba_clk); - -/* GPT */ -DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &ipg_clk, NULL); -DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, - NULL, NULL, &ipg_clk, NULL); - -/* FEC */ -DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, - NULL, NULL, &ipg_clk, NULL); - -#define _REGISTER_CLOCK(d, n, c) \ - { \ - .dev_id = d, \ - .con_id = n, \ - .clk = &c, \ - }, - -static struct clk_lookup lookups[] = { - _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) - _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) - _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) - _REGISTER_CLOCK(NULL, "gpt", gpt_clk) - _REGISTER_CLOCK("fec.0", NULL, fec_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) - _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) - _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) -}; - -static void clk_tree_init(void) -{ - u32 reg; - - ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); - - /* - * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at - * 8MHz, its derived from lp_apm. - * - * FIXME: Verify if true for all boards - */ - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; - reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; - reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; - reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); - __raw_writel(reg, MXC_CCM_CBCDR); -} - -int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2) -{ - int i; - - external_low_reference = ckil; - external_high_reference = ckih1; - ckih2_reference = ckih2; - oscillator_reference = osc; - - for (i = 0; i < ARRAY_SIZE(lookups); i++) - clkdev_add(&lookups[i]); - - clk_tree_init(); - - clk_enable(&cpu_clk); - clk_enable(&main_bus_clk); - - /* set the usboh3_clk parent to pll2_sw_clk */ - clk_set_parent(&usboh3_clk, &pll2_sw_clk); - - /* System timer */ - mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), - MX51_MXC_INT_GPT); - return 0; -} diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c new file mode 100644 index 000000000000..8c91002f4149 --- /dev/null +++ b/arch/arm/mach-mx5/clock.c @@ -0,0 +1,5140 @@ +/* + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" +#include "serial.h" +#include "mx53_wp.h" + +/* External clock values passed-in by the board code */ +static unsigned long external_high_reference, external_low_reference; +static unsigned long oscillator_reference, ckih2_reference; + +static struct clk pll1_main_clk; +static struct clk pll1_sw_clk; +static struct clk pll2_sw_clk; +static struct clk pll3_sw_clk; +static struct clk pll4_sw_clk; +static struct clk lp_apm_clk; +static struct clk tve_clk; +static struct clk emi_fast_clk; +static struct clk emi_slow_clk; +static struct clk emi_intr_clk[]; +static struct clk ddr_clk; +static struct clk ipu_clk[]; +static struct clk ldb_di_clk[]; +static struct clk axi_a_clk; +static struct clk axi_b_clk; +static struct clk ddr_hf_clk; +static struct clk mipi_hsp_clk; +static struct clk gpu3d_clk; +static struct clk gpu2d_clk; +static struct clk vpu_clk[]; +static int cpu_curr_wp; +static struct cpu_wp *cpu_wp_tbl; + +static void __iomem *pll1_base; +static void __iomem *pll2_base; +static void __iomem *pll3_base; +static void __iomem *pll4_base; + +extern int cpu_wp_nr; +extern int lp_high_freq; +extern int lp_med_freq; +static int max_axi_a_clk; +static int max_axi_b_clk; +static int max_ahb_clk; +static int max_emi_slow_clk; +extern int dvfs_core_is_active; + +#define SPIN_DELAY 1000000 /* in nanoseconds */ +#define MAX_AXI_A_CLK_MX51 166250000 +#define MAX_AXI_A_CLK_MX53 400000000 +#define MAX_AXI_B_CLK_MX51 133000000 +#define MAX_AXI_B_CLK_MX53 200000000 +#define MAX_AHB_CLK_MX51 133000000 +#define MAX_EMI_SLOW_CLK_MX51 133000000 +#define MAX_AHB_CLK_MX53 133333333 +#define MAX_EMI_SLOW_CLK_MX53 133333333 +#define MAX_DDR_HF_RATE 200000000 +/* To keep compatible with some NAND flash, limit + * max NAND clk to 34MHZ. The user can modify it for + * dedicate NAND flash */ +#define MAX_NFC_CLK 34000000 + +extern int mxc_jtag_enabled; +extern int uart_at_24; +extern int cpufreq_trig_needed; +extern int low_bus_freq_mode; + +static int cpu_clk_set_wp(int wp); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); + +static struct clk esdhc3_clk[]; + +static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) +{ + u32 min_pre, temp_pre, old_err, err; + + if (div >= 512) { + *pre = 8; + *post = 64; + } else if (div >= 8) { + min_pre = (div - 1) / 64 + 1; + old_err = 8; + for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { + err = div % temp_pre; + if (err == 0) { + *pre = temp_pre; + break; + } + err = temp_pre - err; + if (err < old_err) { + old_err = err; + *pre = temp_pre; + } + } + *post = (div + *pre - 1) / *pre; + } else if (div < 8) { + *pre = div; + *post = 1; + } +} + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + + return 0; +} + +static int _clk_enable_inrun(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq--; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq--; +} + +static void _clk_disable_inwait(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else + BUG(); + + return 0; +} + +/* + * For the ddr muxed input clock + */ +static inline u32 _get_mux_ddr(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3, struct clk *m4) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else if (parent == m4) + return 4; + else + BUG(); + + return 0; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) + return pll1_base; + else if (pll == &pll2_sw_clk) + return pll2_base; + else if (pll == &pll3_sw_clk) + return pll3_base; + else if (pll == &pll4_sw_clk) + return pll4_base; + else + BUG(); + + return NULL; +} + +static unsigned long get_high_reference_clock_rate(struct clk *clk) +{ + return external_high_reference; +} + +static unsigned long get_low_reference_clock_rate(struct clk *clk) +{ + return external_low_reference; +} + +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) +{ + return oscillator_reference; +} + +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) +{ + return ckih2_reference; +} + +/* External high frequency clock */ +static struct clk ckih_clk = { + .get_rate = get_high_reference_clock_rate, +}; + +static struct clk ckih2_clk = { + .get_rate = get_ckih2_reference_clock_rate, +}; + +static struct clk osc_clk = { + .get_rate = get_oscillator_reference_clock_rate, +}; + +/* External low frequency (32kHz) clock */ +static struct clk ckil_clk = { + .get_rate = get_low_reference_clock_rate, +}; + +static unsigned long _fpm_get_rate(struct clk *clk) +{ + u32 rate = ckil_clk.get_rate(&ckil_clk) * 512; + if ((__raw_readl(MXC_CCM_CCR) & MXC_CCM_CCR_FPM_MULT_MASK) != 0) + rate *= 2; + return rate; +} + +static int _fpm_enable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg |= MXC_CCM_CCR_FPM_EN; + __raw_writel(reg, MXC_CCM_CCR); + return 0; +} + +static void _fpm_disable(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCR); + reg &= ~MXC_CCM_CCR_FPM_EN; + __raw_writel(reg, MXC_CCM_CCR); +} + +static struct clk fpm_clk = { + .parent = &ckil_clk, + .get_rate = _fpm_get_rate, + .enable = _fpm_enable, + .disable = _fpm_disable, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _fpm_div2_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 2; +} + +static struct clk fpm_div2_clk = { + .parent = &fpm_clk, + .get_rate = _fpm_div2_get_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_pll_get_rate(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + void __iomem *pllbase; + s64 temp; + + pllbase = _get_pll_base(clk); + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * clk_get_rate(clk->parent); + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + return temp; +} + +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, reg1; + void __iomem *pllbase; + struct timespec nstimeofday; + struct timespec curtime; + + long mfi, pdf, mfn, mfd = 999999; + s64 temp64; + unsigned long quad_parent_rate; + unsigned long pll_hfsm, dp_ctl; + + pllbase = _get_pll_base(clk); + + quad_parent_rate = 4 * clk_get_rate(clk->parent); + pdf = mfi = -1; + while (++pdf < 16 && mfi < 5) + mfi = rate * (pdf+1) / quad_parent_rate; + if (mfi > 15) + return -1; + pdf--; + + temp64 = rate*(pdf+1) - quad_parent_rate*mfi; + do_div(temp64, quad_parent_rate/1000000); + mfn = (long)temp64; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + /* use dpdck0_2 */ + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + if (pll_hfsm == 0) { + reg = mfi<<4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); + } else { + reg = mfi<<4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); + } + /* If auto restart is disabled, restart the PLL and + * wait for it to lock. + */ + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + if (reg & MXC_PLL_DP_CTL_UPEN) { + reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG); + if (!(reg & MXC_PLL_DP_CONFIG_AREN)) { + reg1 = __raw_readl(pllbase + MXC_PLL_DP_CTL); + reg1 |= MXC_PLL_DP_CTL_RST; + __raw_writel(reg1, pllbase + MXC_PLL_DP_CTL); + } + /* Wait for lock */ + getnstimeofday(&nstimeofday); + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) + & MXC_PLL_DP_CTL_LRF)) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("pll_set_rate: pll relock failed\n"); + } + } + return 0; +} + +static int _clk_pll_enable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + struct timespec nstimeofday; + struct timespec curtime; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + + if (reg & MXC_PLL_DP_CTL_UPEN) + return 0; + + reg |= MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + + /* Wait for lock */ + getnstimeofday(&nstimeofday); + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("pll relock failed\n"); + } + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +} + +static struct clk pll1_main_clk = { + .parent = &osc_clk, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll1_main_clk) { + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + /* Set the step_clk parent to be lp_apm, to save power. */ + mux = _get_mux(&lp_apm_clk, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = __raw_readl(MXC_CCM_CCSR); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + } else { + if (parent == &lp_apm_clk) { + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + reg = __raw_readl(MXC_CCM_CCSR); + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + } else { + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + + } + } + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static unsigned long _clk_pll1_sw_get_rate(struct clk *clk) +{ + u32 reg, div; + div = 1; + reg = __raw_readl(MXC_CCM_CCSR); + + if (clk->parent == &pll2_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; + } else if (clk->parent == &pll3_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; + } + return clk_get_rate(clk->parent) / div; +} + +/* pll1 switch clock */ +static struct clk pll1_sw_clk = { + .parent = &pll1_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .get_rate = _clk_pll1_sw_get_rate, + .flags = RATE_PROPAGATES, +}; + +static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll2_sw_clk) { + reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + } else { + reg = (reg & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL); + reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +/* same as pll2_main_clk. These two clocks should always be the same */ +static struct clk pll2_sw_clk = { + .parent = &osc_clk, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_pll_set_rate, + .set_parent = _clk_pll2_sw_set_parent, + .flags = RATE_PROPAGATES, +}; + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +/* same as pll4_main_clk. These two clocks should always be the same */ +static struct clk pll4_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (parent == &osc_clk) + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; + else if (parent == &fpm_clk) + reg = __raw_readl(MXC_CCM_CCSR) | MXC_CCM_CCSR_LP_APM_SEL; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk lp_apm_clk = { + .parent = &osc_clk, + .set_parent = _clk_lp_apm_set_parent, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_arm_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + u32 i; + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + if (i >= cpu_wp_nr) + return -EINVAL; + cpu_clk_set_wp(i); + + return 0; +} + +static unsigned long _clk_cpu_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 i; + u32 wp; + + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + + if (i > cpu_wp_nr) + wp = 0; + + return cpu_wp_tbl[wp].cpu_rate; +} + + +static struct clk cpu_clk = { + .parent = &pll1_sw_clk, + .get_rate = _clk_arm_get_rate, + .set_rate = _clk_cpu_set_rate, + .round_rate = _clk_cpu_round_rate, +}; + +static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + struct timespec nstimeofday; + struct timespec curtime; + + mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); + + reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CBCMR); + + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & + MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("pll _clk_periph_apm_set_parent failed\n"); + } + return 0; +} + +static struct clk periph_apm_clk = { + .parent = &pll1_sw_clk, + .set_parent = _clk_periph_apm_set_parent, + .flags = RATE_PROPAGATES, +}; + +/* TODO: Need to sync with GPC to determine if DVFS is in place so that + * the DVFS_PODF divider can be applied in CDCR register. + */ +static unsigned long _clk_main_bus_get_rate(struct clk *clk) +{ + u32 div = 0; + + if (dvfs_per_divider_active() || low_bus_freq_mode) + div = (__raw_readl(MXC_CCM_CDCR) & 0x3); + return clk_get_rate(clk->parent) / (div + 1); +} + +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + + if (parent == &pll2_sw_clk) { + reg = __raw_readl(MXC_CCM_CBCDR) & + ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + } else if (parent == &periph_apm_clk) { + reg = __raw_readl(MXC_CCM_CBCDR) | MXC_CCM_CBCDR_PERIPH_CLK_SEL; + } else { + return -EINVAL; + } + __raw_writel(reg, MXC_CCM_CBCDR); + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + + return 0; +} + +static struct clk main_bus_clk = { + .parent = &pll2_sw_clk, + .set_parent = _clk_main_bus_set_parent, + .get_rate = _clk_main_bus_get_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_axi_a_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AXI_A_PODF_MASK) >> + MXC_CCM_CBCDR_AXI_A_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("pll _clk_axi_a_set_rate failed\n"); + } + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + + return 0; +} + +static unsigned long _clk_axi_a_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (parent_rate / div > max_axi_a_clk) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + + +static struct clk axi_a_clk = { + .parent = &main_bus_clk, + .get_rate = _clk_axi_a_get_rate, + .set_rate = _clk_axi_a_set_rate, + .round_rate = _clk_axi_a_round_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_ddr_hf_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >> + MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static unsigned long _clk_ddr_hf_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (parent_rate / div > MAX_DDR_HF_RATE) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static int _clk_ddr_hf_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_DDR_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_DDR_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_DDR_PODF_BUSY) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("clk_ddr_hf_set_rate failed\n"); + } + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + + return 0; +} + +static struct clk ddr_hf_clk = { + .parent = &pll1_sw_clk, + .get_rate = _clk_ddr_hf_get_rate, + .round_rate = _clk_ddr_hf_round_rate, + .set_rate = _clk_ddr_hf_set_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_axi_b_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AXI_B_PODF_MASK) >> + MXC_CCM_CBCDR_AXI_B_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("_clk_axi_b_set_rate failed\n"); + } + + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + + return 0; +} + +static unsigned long _clk_axi_b_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (parent_rate / div > max_axi_b_clk) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + + +static struct clk axi_b_clk = { + .parent = &main_bus_clk, + .get_rate = _clk_axi_b_get_rate, + .set_rate = _clk_axi_b_set_rate, + .round_rate = _clk_axi_b_round_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_ahb_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + + +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("_clk_ahb_set_rate failed\n"); + } + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + + return 0; +} + +static unsigned long _clk_ahb_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (parent_rate / div > max_ahb_clk) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + + +static struct clk ahb_clk = { + .parent = &main_bus_clk, + .get_rate = _clk_ahb_get_rate, + .set_rate = _clk_ahb_set_rate, + .round_rate = _clk_ahb_round_rate, + .flags = RATE_PROPAGATES, +}; + +static int _clk_max_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Handshake with MAX when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + if (cpu_is_mx51()) + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51; + else + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + + +static void _clk_max_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable_inwait(clk); + + /* No Handshake with MAX when LPM is entered as its disabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + if (cpu_is_mx51()) + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51; + else + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + + +static struct clk ahb_max_clk = { + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, +}; + +static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + + reg = __raw_readl(MXC_CCM_CBCDR); + if (parent == &ahb_clk) { + reg |= MXC_CCM_CBCDR_EMI_CLK_SEL; + } else if (parent == &main_bus_clk) { + reg &= ~MXC_CCM_CBCDR_EMI_CLK_SEL; + } else { + BUG(); + } + __raw_writel(reg, MXC_CCM_CBCDR); + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + + return 0; +} + +static unsigned long _clk_emi_slow_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> + MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY) { + getnstimeofday(&curtime); + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) + panic("_clk_emi_slow_set_rate failed\n"); + } + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + + return 0; +} + +static unsigned long _clk_emi_slow_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (parent_rate / div > max_emi_slow_clk) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + + +static struct clk emi_slow_clk = { + .parent = &main_bus_clk, + .set_parent = _clk_emi_slow_set_parent, + .get_rate = _clk_emi_slow_get_rate, + .set_rate = _clk_emi_slow_set_rate, + .round_rate = _clk_emi_slow_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .disable = _clk_disable_inwait, + .flags = RATE_PROPAGATES, +}; + +static struct clk ahbmux1_clk = { + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .disable = _clk_disable_inwait, +}; + +static struct clk ahbmux2_clk = { + .id = 0, + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .disable = _clk_disable_inwait, +}; + + +static struct clk emi_fast_clk = { + .parent = &ddr_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .disable = _clk_disable_inwait, +}; + +static struct clk emi_intr_clk[] = { + { + .id = 0, + .parent = &ahb_clk, + .secondary = &ahbmux2_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, + }, + { + /* On MX51 - this clock is name emi_garb_clk, and controls the + * access of ARM to GARB. + */ + .id = 1, + .parent = &ahb_clk, + .secondary = &ahbmux2_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, + } +}; + +static unsigned long _clk_ipg_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static struct clk ipg_clk = { + .parent = &ahb_clk, + .get_rate = _clk_ipg_get_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_ipg_per_get_rate(struct clk *clk) +{ + u32 reg, prediv1, prediv2, podf; + + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { + /* the main_bus_clk is the one before the DVFS engine */ + reg = __raw_readl(MXC_CCM_CBCDR); + prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; + prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; + podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / (prediv1 * prediv2 * podf); + } else if (clk->parent == &ipg_clk) { + return clk_get_rate(&ipg_clk); + } + BUG(); + return 0; +} + +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL); + if (mux == 2) { + reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + } else { + reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + if (mux == 0) + reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + else + reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk ipg_perclk = { + .parent = &lp_apm_clk, + .get_rate = _clk_ipg_per_get_rate, + .set_parent = _clk_ipg_per_set_parent, + .flags = RATE_PROPAGATES, +}; + +static int _clk_ipmux_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_ipmux_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(0x1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static struct clk ipumux1_clk = { + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG6_1_OFFSET, + .enable = _clk_ipmux_enable, + .disable = _clk_ipmux_disable, +}; + +static struct clk ipumux2_clk = { + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG6_2_OFFSET, + .enable = _clk_ipmux_enable, + .disable = _clk_ipmux_disable, +}; + +static int _clk_ocram_enable(struct clk *clk) +{ + return 0; +} + +static void _clk_ocram_disable(struct clk *clk) +{ +} + +static struct clk ocram_clk = { + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_ocram_enable, + .disable = _clk_ocram_disable, +}; + + +static struct clk aips_tz1_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk aips_tz2_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk gpc_dvfs_clk = { + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_sdma_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Handshake with SDMA when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + if (cpu_is_mx51()) + reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51; + else + reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_sdma_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable(clk); + /* No handshake with SDMA as its not enabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + if (cpu_is_mx51()) + reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51; + else + reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + + +static struct clk sdma_clk[] = { + { + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_sdma_enable, + .disable = _clk_sdma_disable, + }, + { + .parent = &ipg_clk, +#ifdef CONFIG_SDMA_IRAM + .secondary = &emi_intr_clk[0], +#endif + }, +}; + +static int _clk_ipu_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(MXC_CCM_CCDR); + if (cpu_is_mx51()) + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + else + reg &= ~MXC_CCM_CCDR_IPU_HS_MX53_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* Handshake with IPU when LPM is entered as its enabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + start_sdram_autogating(); + + return 0; +} + +static void _clk_ipu_disable(struct clk *clk) +{ + u32 reg; + + if (sdram_autogating_active()) + stop_sdram_autogating(); + + _clk_disable(clk); + + /* No handshake with IPU whe dividers are changed + * as its not enabled. */ + reg = __raw_readl(MXC_CCM_CCDR); + if (cpu_is_mx51()) + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + else + reg |= MXC_CCM_CCDR_IPU_HS_MX53_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* No handshake with IPU when LPM is entered as its not enabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + +static int _clk_ipu_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &ahb_clk, + &emi_slow_clk); + reg = (reg & ~MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + + +static struct clk ipu_clk[] = { + { + .parent = &ahb_clk, + .secondary = &ipu_clk[1], + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_ipu_enable, + .disable = _clk_ipu_disable, + .set_parent = _clk_ipu_set_parent, + .flags = CPU_FREQ_TRIG_UPDATE | AHB_MED_SET_POINT | RATE_PROPAGATES, + }, + { + .parent = &emi_fast_clk, + .secondary = &ahbmux1_clk, + } +}; + +static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR2); + reg &= ~MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id); + if (parent == &pll3_sw_clk) + ; + else if (parent == &osc_clk) + reg |= 1 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + else if (parent == &ckih_clk) + reg |= 2 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + else if ((parent == &pll4_sw_clk) && (clk->id == 0)) { + if (cpu_is_mx51()) + return -EINVAL; + reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + } else if ((parent == &tve_clk) && (clk->id == 1)) + reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + else if ((parent == &ldb_di_clk[clk->id]) && cpu_is_mx53()) + reg |= 5 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + else /* Assume any other clock is external clock pin */ + reg |= 4 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static int priv_div; +static unsigned long _clk_ipu_di_get_rate(struct clk *clk) +{ + u32 reg, mux; + u32 div = 1; + + reg = __raw_readl(MXC_CCM_CSCMR2); + mux = (reg & MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id)) >> + MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + if (mux == 0) { + reg = __raw_readl(MXC_CCM_CDCDR) & + MXC_CCM_CDCDR_DI1_CLK_PRED_MASK; + div = (reg >> MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET) + 1; + } else if ((mux == 3) && (clk->id == 1)) { + if (priv_div) + div = priv_div; + } else if ((mux == 3) && (clk->id == 0)) { + reg = __raw_readl(MXC_CCM_CDCDR) & + MXC_CCM_CDCDR_DI_PLL4_PODF_MASK; + div = (reg >> MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET) + 1; + } + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + if ((clk->parent == &pll4_sw_clk) && (clk->id == 0)) { + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_DI_PLL4_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CDCDR); + } else if (clk->parent == &pll3_sw_clk) { + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_DI1_CLK_PRED_MASK; + reg |= (div - 1) << MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CDCDR); + } else if (((clk->parent == &tve_clk) && (clk->id == 1)) || + ((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())) { + priv_div = div; + return 0; + } else + return -EINVAL; + + return 0; +} + +static unsigned long _clk_ipu_di_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + if ((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53()) + return parent_rate; + else { + div = (parent_rate + rate/2) / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return parent_rate / div; + } +} + +static struct clk ipu_di_clk[] = { + { + .id = 0, + .parent = &pll3_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .get_rate = _clk_ipu_di_get_rate, + .set_parent = _clk_ipu_di_set_parent, + .round_rate = _clk_ipu_di_round_rate, + .set_rate = _clk_ipu_di_set_rate, + .enable = _clk_enable, + .disable = _clk_disable, + .flags = RATE_PROPAGATES, + }, + { + .id = 1, + .parent = &pll3_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .get_rate = _clk_ipu_di_get_rate, + .set_parent = _clk_ipu_di_set_parent, + .round_rate = _clk_ipu_di_round_rate, + .set_rate = _clk_ipu_di_set_rate, + .enable = _clk_enable, + .disable = _clk_disable, + .flags = RATE_PROPAGATES, + }, +}; + +static int _clk_ldb_di_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR2); + + if ((parent == &pll3_sw_clk)) { + if (clk->id == 0) + reg &= ~(MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL); + else + reg &= ~(MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL); + } else if ((parent == &pll4_sw_clk)) { + if (clk->id == 0) + reg |= MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL; + else + reg |= MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL; + } else { + BUG(); + } + + __raw_writel(reg, MXC_CCM_CSCMR2); + return 0; +} + +static unsigned long _clk_ldb_di_get_rate(struct clk *clk) +{ + u32 div; + + if (clk->id == 0) + div = __raw_readl(MXC_CCM_CSCMR2) & + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + else + div = __raw_readl(MXC_CCM_CSCMR2) & + MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + + if (div) + return clk_get_rate(clk->parent) / 7; + + return (2 * clk_get_rate(clk->parent)) / 7; +} + +static unsigned long _clk_ldb_di_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 parent_rate = clk_get_rate(clk->parent); + + if (rate * 7 <= parent_rate + parent_rate/20) + return parent_rate / 7; + else + return 2 * parent_rate / 7; +} + +static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div = 0; + u32 parent_rate = clk_get_rate(clk->parent); + + if (rate * 7 <= parent_rate + parent_rate/20) { + div = 7; + rate = parent_rate / 7; + } else + rate = 2 * parent_rate / 7; + + reg = __raw_readl(MXC_CCM_CSCMR2); + if (div == 7) + reg |= (clk->id ? MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV : + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + else + reg &= ~(clk->id ? MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV : + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static int _clk_ldb_di_enable(struct clk *clk) +{ + _clk_enable(clk); + ipu_di_clk[clk->id].set_parent(&ipu_di_clk[clk->id], clk); + ipu_di_clk[clk->id].parent = clk; + ipu_di_clk[clk->id].enable(&ipu_di_clk[clk->id]); + ipu_di_clk[clk->id].usecount++; + return 0; +} + +static void _clk_ldb_di_disable(struct clk *clk) +{ + _clk_disable(clk); + ipu_di_clk[clk->id].disable(&ipu_di_clk[clk->id]); + ipu_di_clk[clk->id].usecount--; +} + +static struct clk ldb_di_clk[] = { + { + .id = 0, + .parent = &pll4_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .get_rate = _clk_ldb_di_get_rate, + .set_parent = _clk_ldb_di_set_parent, + .round_rate = _clk_ldb_di_round_rate, + .set_rate = _clk_ldb_di_set_rate, + .enable = _clk_ldb_di_enable, + .disable = _clk_ldb_di_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT, + }, + { + .id = 1, + .parent = &pll4_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .get_rate = _clk_ldb_di_get_rate, + .set_parent = _clk_ldb_di_set_parent, + .round_rate = _clk_ldb_di_round_rate, + .set_rate = _clk_ldb_di_set_rate, + .enable = _clk_ldb_di_enable, + .disable = _clk_ldb_di_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT, + }, +}; + +static int _clk_csi0_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL); + reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static unsigned long _clk_csi0_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CSCDR4); + pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK) >> + MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK) >> + MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent)/(pred * podf); +} + +static unsigned long _clk_csi0_round_rate(struct clk *clk, unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return parent_rate / (pre * post); +} + +static int _clk_csi0_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set CSI clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR4) & + ~(MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK | + MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR4); + + return 0; +} + +static struct clk csi0_clk = { + .parent = &pll3_sw_clk, + .set_parent = _clk_csi0_set_parent, + .get_rate = _clk_csi0_get_rate, + .round_rate = _clk_csi0_round_rate, + .set_rate = _clk_csi0_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_csi1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL); + reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static unsigned long _clk_csi1_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CSCDR4); + pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent)/(pred * podf) ; +} + +static unsigned long _clk_csi1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return parent_rate / (pre * post); +} + +static int _clk_csi1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set CSI clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR4) & + ~(MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK | + MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR4); + + return 0; +} + +static struct clk csi1_clk = { + .parent = &pll3_sw_clk, + .set_parent = _clk_csi1_set_parent, + .get_rate = _clk_csi1_get_rate, + .round_rate = _clk_csi1_round_rate, + .set_rate = _clk_csi1_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .disable = _clk_disable, +}; + + +static int _clk_hsc_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg &= ~MXC_CCM_CCDR_HSC_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_hsc_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable(clk); + /* No handshake with HSC as its not enabled. */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_HSC_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + +static struct clk mipi_esc_clk = { + .parent = &pll2_sw_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, +}; + +static struct clk mipi_hsc2_clk = { + .parent = &pll2_sw_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .secondary = &mipi_esc_clk, +}; + +static struct clk mipi_hsc1_clk = { + .parent = &pll2_sw_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .secondary = &mipi_hsc2_clk, +}; + +static struct clk mipi_hsp_clk = { + .parent = &ipu_clk[0], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_hsc_enable, + .disable = _clk_hsc_disable, + .secondary = &mipi_hsc1_clk, +}; + +static int _clk_tve_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + + if ((parent == &pll3_sw_clk) && cpu_is_mx51()) { + reg &= ~(MXC_CCM_CSCMR1_TVE_CLK_SEL); + } else if ((parent == &pll4_sw_clk) && cpu_is_mx53()) { + reg &= ~(MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL); + } else if ((parent == &osc_clk) && cpu_is_mx51()) { + reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; + reg &= ~MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; + } else if (parent == &ckih_clk) { + reg |= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; + reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; /* Reserved on MX53 */ + } else { + BUG(); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static unsigned long _clk_tve_get_rate(struct clk *clk) +{ + u32 reg, div = 1; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & (MXC_CCM_CSCMR1_TVE_CLK_SEL | MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) == 0) { + reg = __raw_readl(MXC_CCM_CDCDR) & + MXC_CCM_CDCDR_TVE_CLK_PRED_MASK; + div = (reg >> MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET) + 1; + } + return clk_get_rate(clk->parent) / div; +} + +static unsigned long _clk_tve_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (cpu_is_mx51() && (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL)) + return -EINVAL; + if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) + return -EINVAL; + + div = (parent_rate + rate/2) / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return parent_rate / div; +} + +static int _clk_tve_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (cpu_is_mx51() && (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL)) + return -EINVAL; + if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) + return -EINVAL; + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + div--; + reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_TVE_CLK_PRED_MASK; + reg |= div << MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CDCDR); + return 0; +} + +static struct clk tve_clk = { + .parent = &pll3_sw_clk, + .set_parent = _clk_tve_set_parent, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .get_rate = _clk_tve_get_rate, + .round_rate = _clk_tve_round_rate, + .set_rate = _clk_tve_set_rate, + .enable = _clk_enable, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk spba_clk = { + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static unsigned long _clk_uart_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent)/(prediv * podf) ; +} + +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk uart_main_clk = { + .parent = &pll2_sw_clk, + .get_rate = _clk_uart_get_rate, + .set_parent = _clk_uart_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk uart1_clk[] = { + { + .id = 0, + .parent = &uart_main_clk, + .secondary = &uart1_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART1_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 0, + .parent = &ipg_clk, +#if UART1_DMA_ENABLE + .secondary = &aips_tz1_clk, +#endif + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart2_clk[] = { + { + .id = 1, + .parent = &uart_main_clk, + .secondary = &uart2_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART2_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 1, + .parent = &ipg_clk, +#if UART2_DMA_ENABLE + .secondary = &aips_tz1_clk, +#endif + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart3_clk[] = { + { + .id = 2, + .parent = &uart_main_clk, + .secondary = &uart3_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART3_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 2, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart4_clk[] = { + { + .id = 3, + .parent = &uart_main_clk, + .secondary = &uart4_clk[1], + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART4_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 3, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart5_clk[] = { + { + .id = 4, + .parent = &uart_main_clk, + .secondary = &uart5_clk[1], + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART5_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 4, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk gpt_clk[] = { + { + .parent = &ipg_perclk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &gpt_clk[1], + }, + { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk pwm1_clk[] = { + { + .parent = &ipg_perclk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &pwm1_clk[1], + }, + { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk pwm2_clk[] = { + { + .parent = &ipg_perclk, + .id = 1, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &pwm2_clk[1], + }, + { + .id = 1, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ckil_clk, + }, +}; + +static struct clk i2c_clk[] = { + { + .id = 0, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 2, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static unsigned long _clk_hsi2c_serial_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR3); + prediv = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK) >> + MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK) >> + MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static struct clk hsi2c_serial_clk = { + .id = 0, + .parent = &pll3_sw_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .get_rate = _clk_hsi2c_serial_get_rate, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk hsi2c_clk = { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long _clk_cspi_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk cspi_main_clk = { + .parent = &pll3_sw_clk, + .get_rate = _clk_cspi_get_rate, + .set_parent = _clk_cspi_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk cspi1_clk[] = { + { + .id = 0, + .parent = &cspi_main_clk, + .secondary = &cspi1_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, +}; + +static struct clk cspi2_clk[] = { + { + .id = 1, + .parent = &cspi_main_clk, + .secondary = &cspi2_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, +}; + +static struct clk cspi3_clk = { + .id = 2, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &aips_tz2_clk, +}; + +static unsigned long _clk_ieee_rtc_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + prediv = ((reg & MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_ieee_rtc_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || div > 512) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CSCDR2); + reg &= ~(MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK | + MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + +static unsigned long _clk_ieee_rtc_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return parent_rate / (pre * post); +} + +static int _clk_ieee_rtc_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll3_sw_clk, &pll4_sw_clk, + NULL, NULL); + reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static struct clk ieee_rtc_clk = { + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_ieee_rtc_set_parent, + .set_rate = _clk_ieee_rtc_set_rate, + .round_rate = _clk_ieee_rtc_round_rate, + .get_rate = _clk_ieee_rtc_get_rate, +}; + +static int _clk_ssi_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &ckih_clk, &lp_apm_clk, &ckih2_clk, NULL); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_lp_apm_clk = { + .parent = &ckih_clk, + .set_parent = _clk_ssi_lp_apm_set_parent, +}; + +static unsigned long _clk_ssi1_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} +static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi1_clk[] = { + { + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi1_set_parent, + .secondary = &ssi1_clk[1], + .get_rate = _clk_ssi1_get_rate, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ipg_clk, + .secondary = &ssi1_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &aips_tz2_clk, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &emi_intr_clk[0], +#else + .secondary = &emi_fast_clk, +#endif + }, +}; + +static unsigned long _clk_ssi2_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi2_clk[] = { + { + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi2_set_parent, + .secondary = &ssi2_clk[1], + .get_rate = _clk_ssi2_get_rate, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ipg_clk, + .secondary = &ssi2_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &spba_clk, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &emi_intr_clk[0], +#else + .secondary = &emi_fast_clk, +#endif + }, +}; + +static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL; + + if (parent == &ssi1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_SSI3_CLK_SEL; + else if (parent == &ssi2_clk[0]) + reg |= MXC_CCM_CSCMR1_SSI3_CLK_SEL; + else { + printk(KERN_ERR"Set ssi3 clock parent failed!\n"); + printk(KERN_ERR"ssi3 only support"); + printk(KERN_ERR"ssi1 and ssi2 as parent clock\n"); + return -1; + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static struct clk ssi3_clk[] = { + { + .id = 2, + .parent = &ssi1_clk[0], + .set_parent = _clk_ssi3_set_parent, + .secondary = &ssi3_clk[1], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 2, + .parent = &ipg_clk, + .secondary = &ssi3_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 2, + .parent = &aips_tz2_clk, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &emi_intr_clk, +#else + .secondary = &emi_fast_clk, +#endif + }, +}; + +static unsigned long _clk_ssi_ext1_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + u32 div = 1; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET) + 1; + div = prediv * podf; + } + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || div > 512) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~(MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK | + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + return 0; +} + +static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi1_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_ssi_ext1_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return parent_rate / (pre * post); +} + +static struct clk ssi_ext1_clk = { + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext1_set_parent, + .set_rate = _clk_ssi_ext1_set_rate, + .round_rate = _clk_ssi_ext1_round_rate, + .get_rate = _clk_ssi_ext1_get_rate, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static unsigned long _clk_ssi_ext2_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + u32 div = 1; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET) + 1; + div = prediv * podf; + } + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ssi_ext2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi2_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_ext2_clk = { + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext2_set_parent, + .get_rate = _clk_ssi_ext2_get_rate, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_esai_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + if (parent == &pll1_sw_clk || parent == &pll2_sw_clk || + parent == &pll3_sw_clk) { + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + NULL); + reg &= ~MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET; + reg &= ~MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK; + reg |= 0 << MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET; + /* divider setting */ + } else { + mux = _get_mux(parent, &ssi1_clk[0], &ssi2_clk[0], &ckih_clk, + &ckih2_clk); + reg &= ~MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK; + reg |= (mux + 1) << MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET; + /* divider setting */ + } + + __raw_writel(reg, MXC_CCM_CSCMR2); + + /* set podf = 0 */ + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK; + __raw_writel(reg, MXC_CCM_CS1CDR); + + return 0; +} + +static unsigned long _clk_esai_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + if (clk->parent == &pll1_sw_clk || clk->parent == &pll2_sw_clk || + clk->parent == &pll3_sw_clk) { + pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (pred * podf); + } else { + podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / podf; + } +} + +static struct clk esai_clk[] = { + { + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_esai_set_parent, + .get_rate = _clk_esai_get_rate, + .secondary = &esai_clk[1], + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk iim_clk = { + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .disable = _clk_disable, +}; + +static struct clk tmax1_clk = { + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_disable, + }; + +static struct clk tmax2_clk = { + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk tmax3_clk = { + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, +}; + +static unsigned long _clk_usboh3_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk usboh3_clk[] = { + { + .parent = &pll3_sw_clk, + .set_parent = _clk_usboh3_set_parent, + .get_rate = _clk_usboh3_get_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .disable = _clk_disable, + .secondary = &usboh3_clk[1], + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .parent = &tmax2_clk, +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) + .secondary = &emi_intr_clk[0], +#else + .secondary = &emi_fast_clk, +#endif + }, +}; + +static struct clk usb_ahb_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .disable = _clk_disable, +}; + +static unsigned long _clk_usb_phy_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + u32 div = 1; + + if (clk->parent == &pll3_sw_clk) { + reg = __raw_readl(MXC_CCM_CDCDR); + prediv = ((reg & MXC_CCM_CDCDR_USB_PHY_PRED_MASK) >> + MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_USB_PHY_PODF_MASK) >> + MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET) + 1; + + div = (prediv * podf); + } + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_usb_phy_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &osc_clk) + reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + else if (parent == &pll3_sw_clk) + reg |= MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; + else + BUG(); + + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static struct clk usb_phy_clk[] = { + { + .id = 0, + .parent = &pll3_sw_clk, + .secondary = &tmax3_clk, + .set_parent = _clk_usb_phy_set_parent, + .get_rate = _clk_usb_phy_get_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &pll3_sw_clk, + .secondary = &tmax3_clk, + .set_parent = _clk_usb_phy_set_parent, + .get_rate = _clk_usb_phy_get_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .disable = _clk_disable, + } +}; + +static struct clk esdhc_dep_clks = { + .parent = &spba_clk, + .secondary = &emi_fast_clk, +}; + +static unsigned long _clk_esdhc1_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + + +static int _clk_sdhc1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static struct clk esdhc1_clk[] = { + { + .id = 0, + .parent = &pll2_sw_clk, + .set_parent = _clk_esdhc1_set_parent, + .get_rate = _clk_esdhc1_get_rate, + .set_rate = _clk_sdhc1_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc1_clk[1], + }, + { + .id = 0, + .parent = &ipg_clk, + .secondary = &esdhc1_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &tmax3_clk, + .secondary = &esdhc_dep_clks, + }, + +}; + +static unsigned long _clk_esdhc2_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + if (cpu_is_mx51()) { + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); + } + return clk_get_rate(clk->parent); +} + +static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + if (cpu_is_mx51()) { + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET; + } else { /* MX53 */ + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; + else if (parent == &esdhc3_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; + else + BUG(); + } + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static int _clk_esdhc2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + if (cpu_is_mx51()) { + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + } + return 0; +} + +static struct clk esdhc2_clk[] = { + { + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_esdhc2_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc2_clk[1], + }, + { + .id = 1, + .parent = &ipg_clk, + .secondary = &esdhc2_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + if (cpu_is_mx51()) { + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51; + else if (parent == &esdhc2_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51; + else + BUG(); + } else { /* MX53 */ + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET; + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_esdhc3_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_sdhc3_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + if (cpu_is_mx53()) { + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + } + return 0; +} + + +static struct clk esdhc3_clk[] = { + { + .id = 2, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc3_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc3_clk[1], + }, + { + .id = 2, + .parent = &ipg_clk, + .secondary = &esdhc3_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ahb_max_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + if (cpu_is_mx51()) { + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc2_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + BUG(); + } else {/*MX53 */ + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc3_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + BUG(); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc4_clk[] = { + { + .id = 3, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc4_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc4_clk[1], + }, + { + .id = 3, + .parent = &ipg_clk, + .secondary = &esdhc4_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &tmax3_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static struct clk sata_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk ieee_1588_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .disable = _clk_disable, +}; + +static struct clk mlb_clk[] = { + { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, + .secondary = &mlb_clk[1], + }, + { + .parent = &emi_fast_clk, + .secondary = &emi_intr_clk[1], + }, +}; + +static int _can_root_clk_set(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &ipg_clk, &ckih_clk, &ckih2_clk, &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static struct clk can1_clk[] = { + { + .id = 0, + .parent = &lp_apm_clk, + .set_parent = _can_root_clk_set, + .enable = _clk_enable, + .secondary = &can1_clk[1], + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk can2_clk[] = { + { + .id = 1, + .parent = &lp_apm_clk, + .set_parent = _can_root_clk_set, + .enable = _clk_enable, + .secondary = &can2_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .disable = _clk_disable, + }, +}; + +static int _clk_sim_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL); + reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static unsigned long _clk_sim_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + pred = ((reg & MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / (pred * podf); +} + +static unsigned long _clk_sim_round_rate(struct clk *clk, unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return parent_rate / (pre * post); +} + +static int _clk_sim_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set SIM clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR2) & + ~(MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK | + MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; + +} + +static struct clk sim_clk[] = { + { + .parent = &pll3_sw_clk, + .set_parent = _clk_sim_set_parent, + .secondary = &sim_clk[1], + .get_rate = _clk_sim_get_rate, + .round_rate = _clk_sim_round_rate, + .set_rate = _clk_sim_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, + }, +}; + +static unsigned long _clk_nfc_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >> + MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static unsigned long _clk_nfc_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + /* + * Compute the divider we'd have to use to reach the target rate. + */ + + div = parent_rate / rate; + if (div == 0) + div++; + if (parent_rate / div > MAX_NFC_CLK) + div++; + + /* + * The divider for this clock is 3 bits wide, so we can't possibly + * divide the parent by more than eight. + */ + + if (div > 8) + return -EINVAL; + + return parent_rate / div; + +} + +static int _clk_nfc_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + if (emi_fast_clk.usecount == 0) + emi_fast_clk.enable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.enable(&emi_slow_clk); + + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & + MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){ + getnstimeofday(&curtime); + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) + panic("_clk_nfc_set_rate failed\n"); + } + if (emi_fast_clk.usecount == 0) + emi_fast_clk.disable(&emi_fast_clk); + if (emi_slow_clk.usecount == 0) + emi_slow_clk.disable(&emi_slow_clk); + + return 0; +} + +static struct clk emi_enfc_clk = { + .parent = &emi_slow_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .disable = _clk_disable_inwait, + .get_rate = _clk_nfc_get_rate, + .round_rate = _clk_nfc_round_rate, + .set_rate = _clk_nfc_set_rate, +}; + +static int _clk_spdif_xtal_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &osc_clk, &ckih_clk, &ckih2_clk, NULL); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk spdif_xtal_clk = { + .parent = &osc_clk, + .set_parent = _clk_spdif_xtal_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + reg |= MXC_CCM_CSCMR2_SPDIF0_COM; + if (parent != &ssi1_clk[0]) { + reg &= ~MXC_CCM_CSCMR2_SPDIF0_COM; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &spdif_xtal_clk); + reg = (reg & ~MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET); + } + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static unsigned long _clk_spdif0_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + u32 div = 1; + + if (clk->parent != &ssi1_clk[0]) { + reg = __raw_readl(MXC_CCM_CDCDR); + pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK) >> + MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK) >> + MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1; + div = (pred * podf); + } + return clk_get_rate(clk->parent) / div; +} + +static struct clk spdif0_clk[] = { + { + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_spdif0_set_parent, + .get_rate = _clk_spdif0_get_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .disable = _clk_disable, + }, +}; + +static int _clk_spdif1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + reg |= MXC_CCM_CSCMR2_SPDIF1_COM; + if (parent != &ssi2_clk[0]) { + reg &= ~MXC_CCM_CSCMR2_SPDIF1_COM; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &spdif_xtal_clk); + reg = (reg & ~MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET); + } + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static unsigned long _clk_spdif1_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + u32 div = 1; + + if (clk->parent != &ssi2_clk[0]) { + reg = __raw_readl(MXC_CCM_CDCDR); + pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK) >> + MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK) >> + MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1; + div = (pred * podf); + } + return clk_get_rate(clk->parent) / div; +} + +static struct clk spdif1_clk[] = { + { + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_spdif1_set_parent, + .get_rate = _clk_spdif1_get_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .disable = _clk_disable, + }, +}; + +static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, reg2, mux; + struct timespec nstimeofday; + struct timespec curtime; + + reg = __raw_readl(MXC_CCM_CBCMR); + reg2 = __raw_readl(MXC_CCM_CBCDR); + if (cpu_is_mx51()) { + clk->parent = &ddr_hf_clk; + mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, &ddr_hf_clk); + } else { + clk->parent = &axi_a_clk; + mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, NULL); + } + if (mux < 4) { + reg = (reg & ~MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + if (cpu_is_mx51()) + reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL); + } else { + reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL) | + (MXC_CCM_CBCDR_DDR_HF_SEL); + } + if (cpu_is_mx51()) { + __raw_writel(reg2, MXC_CCM_CBCDR); + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & + MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY){ + getnstimeofday(&curtime); + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) + panic("_clk_ddr_set_parent failed\n"); + } + } + return 0; +} + +static struct clk ddr_clk = { + .parent = &axi_b_clk, + .set_parent = _clk_ddr_set_parent, + .flags = RATE_PROPAGATES, +}; + +static int _clk_arm_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk arm_axi_clk = { + .parent = &axi_a_clk, + .set_parent = _clk_arm_axi_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_vpu_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static int _clk_vpu_enable(struct clk *clk) +{ + /* Set VPU's parent to be axi_a or ahb when its enabled. */ + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + clk_set_parent(&vpu_clk[0], &ahb_clk); + clk_set_parent(&vpu_clk[1], &ahb_clk); + } else if (cpu_is_mx51()) { + clk_set_parent(&vpu_clk[0], &axi_a_clk); + clk_set_parent(&vpu_clk[1], &axi_a_clk); + } + + return _clk_enable(clk); + +} + +static void _clk_vpu_disable(struct clk *clk) +{ + _clk_disable(clk); + + /* Set VPU's parent to be axi_b when its disabled. */ + if (cpu_is_mx51()) { + clk_set_parent(&vpu_clk[0], &axi_b_clk); + clk_set_parent(&vpu_clk[1], &axi_b_clk); + } +} + +static struct clk vpu_clk[] = { + { + .set_parent = _clk_vpu_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .disable = _clk_disable, + .secondary = &vpu_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .set_parent = _clk_vpu_set_parent, + .enable = _clk_vpu_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .disable = _clk_vpu_disable, + .secondary = &vpu_clk[2], + }, + { + .parent = &emi_fast_clk, +#ifdef CONFIG_MXC_VPU_IRAM + .secondary = &emi_intr_clk[0], +#endif + } +}; + +static int _clk_lpsr_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + reg = __raw_readl(MXC_CCM_CLPCR); + mux = _get_mux(parent, &ckil_clk, &osc_clk, NULL, NULL); + reg = (reg & ~MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK) | + (mux << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static struct clk lpsr_clk = { + .parent = &ckil_clk, + .set_parent = _clk_lpsr_set_parent, +}; + +static unsigned long _clk_pgc_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET; + div = 1 >> div; + return clk_get_rate(clk->parent) / div; +} + +static struct clk pgc_clk = { + .parent = &ipg_clk, + .get_rate = _clk_pgc_get_rate, +}; + +static unsigned long _clk_usb_get_rate(struct clk *clk) +{ + return 60000000; +} + +/*usb OTG clock */ +static struct clk usb_clk = { + .get_rate = _clk_usb_get_rate, +}; + +static struct clk usb_utmi_clk = { + .enable = _clk_enable, + .enable_reg = MXC_CCM_CSCMR1, + .enable_shift = MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET, + .disable = _clk_disable, +}; + +static struct clk rtc_clk = { + .parent = &ckil_clk, + .secondary = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .disable = _clk_disable, +}; + +static struct clk ata_clk = { + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk owire_clk = { + .parent = &ipg_perclk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .disable = _clk_disable, +}; + + +static struct clk fec_clk[] = { + { + .parent = &ipg_clk, + .secondary = &fec_clk[1], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .parent = &tmax2_clk, + .secondary = &fec_clk[2], + }, + { + .parent = &aips_tz2_clk, + .secondary = &emi_fast_clk, + }, +}; + +static struct clk sahara_clk[] = { + { + .parent = &ahb_clk, + .secondary = &sahara_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .parent = &tmax1_clk, + .secondary = &emi_fast_clk, + } +}; + +static struct clk scc_clk[] = { + { + .parent = &ahb_clk, + .secondary = &scc_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .parent = &tmax1_clk, + .secondary = &emi_fast_clk, + } +}; + + +static int _clk_gpu3d_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_GPU_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + + +static struct clk garb_clk = { + .parent = &axi_a_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, +}; + +static struct clk gpu3d_clk = { + .parent = &axi_a_clk, + .set_parent = _clk_gpu3d_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .secondary = &garb_clk, +}; + +static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk gpu2d_clk = { + .parent = &axi_a_clk, + .set_parent = _clk_gpu2d_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long cko1_get_rate(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= MXC_CCM_CCOSR_CKOL_DIV_MASK; + reg = reg >> MXC_CCM_CCOSR_CKOL_DIV_OFFSET; + return clk_get_rate(clk->parent) / (reg + 1); +} + +static int cko1_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg |= MXC_CCM_CCOSR_CKOL_EN; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static void cko1_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_EN; + __raw_writel(reg, MXC_CCM_CCOSR); +} + +static int cko1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = (parent_rate/rate - 1) & 0x7; + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK; + reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static unsigned long cko1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + div = div < 1 ? 1 : div; + div = div > 8 ? 8 : div; + return parent_rate / div; +} + +static int cko1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg; + + if (parent == &cpu_clk) + sel = 0; + else if (parent == &pll1_sw_clk) + sel = 1; + else if (parent == &pll2_sw_clk) + sel = 2; + else if (parent == &pll3_sw_clk) + sel = 3; + else if (parent == &emi_slow_clk) + sel = 4; + else if (parent == &pll4_sw_clk) + sel = 5; + else if (parent == &emi_enfc_clk) + sel = 6; + else if (parent == &ipu_di_clk[0]) + sel = 8; + else if (parent == &ahb_clk) + sel = 11; + else if (parent == &ipg_clk) + sel = 12; + else if (parent == &ipg_perclk) + sel = 13; + else if (parent == &ckil_clk) + sel = 14; + else + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK; + reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} +static struct clk cko1_clk = { + .get_rate = cko1_get_rate, + .enable = cko1_enable, + .disable = cko1_disable, + .set_rate = cko1_set_rate, + .round_rate = cko1_round_rate, + .set_parent = cko1_set_parent, +}; +static int _clk_asrc_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR2); + if (parent == &pll4_sw_clk) + reg |= MXC_CCM_CSCMR2_ASRC_CLK_SEL; + else + reg &= ~MXC_CCM_CSCMR2_ASRC_CLK_SEL; + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static unsigned long _clk_asrc_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + prediv = ((reg & MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_asrc_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CSCDR2) & + ~(MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK | + MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + +static unsigned long _clk_asrc_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return parent_rate / (pre * post); +} + +static struct clk asrc_clk[] = { + { + .id = 0, + .parent = &pll4_sw_clk, + .set_parent = _clk_asrc_set_parent, + .get_rate = _clk_asrc_get_rate, + .set_rate = _clk_asrc_set_rate, + .round_rate = _clk_asrc_round_rate, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + } + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK(NULL, "osc", osc_clk), + _REGISTER_CLOCK(NULL, "ckih", ckih_clk), + _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk), + _REGISTER_CLOCK(NULL, "ckil", ckil_clk), + _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_main_clk), + _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk), + _REGISTER_CLOCK(NULL, "pll2", pll2_sw_clk), + _REGISTER_CLOCK(NULL, "pll3", pll3_sw_clk), + _REGISTER_CLOCK(NULL, "gpc_dvfs_clk", gpc_dvfs_clk), + _REGISTER_CLOCK(NULL, "lp_apm", lp_apm_clk), + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk), + _REGISTER_CLOCK(NULL, "periph_apm_clk", periph_apm_clk), + _REGISTER_CLOCK(NULL, "main_bus_clk", main_bus_clk), + _REGISTER_CLOCK(NULL, "axi_a_clk", axi_a_clk), + _REGISTER_CLOCK(NULL, "axi_b_clk", axi_b_clk), + _REGISTER_CLOCK(NULL, "ahb_clk", ahb_clk), + _REGISTER_CLOCK(NULL, "ahb_max_clk", ahb_max_clk), + _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]), + _REGISTER_CLOCK(NULL, "vpu_core_clk", vpu_clk[1]), + _REGISTER_CLOCK(NULL, "nfc_clk", emi_enfc_clk), + _REGISTER_CLOCK("mxc_sdma", "sdma_ahb_clk", sdma_clk[0]), + _REGISTER_CLOCK("mxc_sdma", "sdma_ipg_clk", sdma_clk[1]), + _REGISTER_CLOCK(NULL, "ipu_clk", ipu_clk[0]), + _REGISTER_CLOCK(NULL, "ipu_di0_clk", ipu_di_clk[0]), + _REGISTER_CLOCK(NULL, "ipu_di1_clk", ipu_di_clk[1]), + _REGISTER_CLOCK(NULL, "csi_mclk1", csi0_clk), + _REGISTER_CLOCK(NULL, "csi_mclk2", csi1_clk), + _REGISTER_CLOCK(NULL, "tve_clk", tve_clk), + _REGISTER_CLOCK("mxcintuart.0", NULL, uart1_clk[0]), + _REGISTER_CLOCK("mxcintuart.1", NULL, uart2_clk[0]), + _REGISTER_CLOCK("mxcintuart.2", NULL, uart3_clk[0]), + _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]), + _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]), + _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk[0]), + _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk[0]), + _REGISTER_CLOCK("mxc_spi.0", NULL, cspi1_clk[0]), + _REGISTER_CLOCK("mxc_spi.1", NULL, cspi2_clk[0]), + _REGISTER_CLOCK("mxc_spi.2", NULL, cspi3_clk), + _REGISTER_CLOCK(NULL, "ssi_lp_apm_clk", ssi_lp_apm_clk), + _REGISTER_CLOCK("mxc_ssi.0", NULL, ssi1_clk[0]), + _REGISTER_CLOCK("mxc_ssi.1", NULL, ssi2_clk[0]), + _REGISTER_CLOCK("mxc_ssi.2", NULL, ssi3_clk[0]), + _REGISTER_CLOCK(NULL, "ssi_ext1_clk", ssi_ext1_clk), + _REGISTER_CLOCK(NULL, "ssi_ext2_clk", ssi_ext2_clk), + _REGISTER_CLOCK(NULL, "iim_clk", iim_clk), + _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]), + _REGISTER_CLOCK(NULL, "usb_ahb_clk", usb_ahb_clk), + _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy_clk[0]), + _REGISTER_CLOCK(NULL, "usb_utmi_clk", usb_utmi_clk), + _REGISTER_CLOCK(NULL, "usb_clk", usb_clk), + _REGISTER_CLOCK("mxsdhci.0", NULL, esdhc1_clk[0]), + _REGISTER_CLOCK("mxsdhci.1", NULL, esdhc2_clk[0]), + _REGISTER_CLOCK("mxsdhci.2", NULL, esdhc3_clk[0]), + _REGISTER_CLOCK("mxsdhci.3", NULL, esdhc4_clk[0]), + _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk), + _REGISTER_CLOCK(NULL, "ddr_clk", ddr_clk), + _REGISTER_CLOCK(NULL, "emi_enfc_clk", emi_enfc_clk), + _REGISTER_CLOCK(NULL, "emi_fast_clk", emi_fast_clk), + _REGISTER_CLOCK(NULL, "emi_intr_clk.0", emi_intr_clk[0]), + _REGISTER_CLOCK(NULL, "emi_intr_clk.1", emi_intr_clk[1]), + _REGISTER_CLOCK(NULL, "spdif_xtal_clk", spdif_xtal_clk), + _REGISTER_CLOCK("mxc_alsa_spdif.0", NULL, spdif0_clk[0]), + _REGISTER_CLOCK("mxc_vpu.0", NULL, vpu_clk[0]), + _REGISTER_CLOCK(NULL, "lpsr_clk", lpsr_clk), + _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk), + _REGISTER_CLOCK("pata_fsl", NULL, ata_clk), + _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), + _REGISTER_CLOCK(NULL, "sahara_clk", sahara_clk[0]), + _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk), + _REGISTER_CLOCK(NULL, "garb_clk", garb_clk), + _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_clk), + _REGISTER_CLOCK("mxc_scc.0", NULL, scc_clk[0]), + _REGISTER_CLOCK(NULL, "cko1", cko1_clk), + _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]), + _REGISTER_CLOCK("fec.0", NULL, fec_clk[0]), + _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), +}; + +static struct clk_lookup mx51_lookups[] = { + _REGISTER_CLOCK("mxc_i2c_hs.3", NULL, hsi2c_serial_clk), + _REGISTER_CLOCK("mxc_sim.0", NULL, sim_clk[0]), + _REGISTER_CLOCK("mxc_alsa_spdif.0", NULL, spdif1_clk[0]), + _REGISTER_CLOCK(NULL, "mipi_hsp_clk", mipi_hsp_clk), + _REGISTER_CLOCK(NULL, "ddr_hf_clk", ddr_hf_clk), +}; + +static struct clk_lookup mx53_lookups[] = { + _REGISTER_CLOCK(NULL, "pll4", pll4_sw_clk), + _REGISTER_CLOCK("mxcintuart.3", NULL, uart4_clk[0]), + _REGISTER_CLOCK("mxcintuart.4", NULL, uart5_clk[0]), + _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]), + _REGISTER_CLOCK(NULL, "usb_phy2_clk", usb_phy_clk[1]), + _REGISTER_CLOCK(NULL, "ocram_clk", ocram_clk), + _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk), + _REGISTER_CLOCK(NULL, "ieee_1588_clk", ieee_1588_clk), + _REGISTER_CLOCK(NULL, "ieee_rtc_clk", ieee_rtc_clk), + _REGISTER_CLOCK("mxc_mlb.0", NULL, mlb_clk[0]), + _REGISTER_CLOCK("FlexCAN.0", "can_clk", can1_clk[0]), + _REGISTER_CLOCK("FlexCAN.1", "can_clk", can2_clk[0]), + _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di_clk[0]), + _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di_clk[1]), + _REGISTER_CLOCK(NULL, "esai_clk", esai_clk[0]), + _REGISTER_CLOCK(NULL, "esai_ipg_clk", esai_clk[1]), + _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[1]), + _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[0]), +}; + +static struct mxc_clk mx51_clks[ARRAY_SIZE(lookups) + ARRAY_SIZE(mx51_lookups)]; +static struct mxc_clk mx53_clks[ARRAY_SIZE(lookups) + ARRAY_SIZE(mx53_lookups)]; + +static void clk_tree_init(void) +{ + u32 reg, dp_ctl; + + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); + + /* + *Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at + * 8MHz, its derived from lp_apm. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; + reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + /* set pll1_main_clk parent */ + pll1_main_clk.parent = &osc_clk; + + /* set pll2_sw_clk parent */ + pll2_sw_clk.parent = &osc_clk; + + /* set pll3_clk parent */ + pll3_sw_clk.parent = &osc_clk; + + if (cpu_is_mx51()) { + dp_ctl = __raw_readl(pll1_base + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll1_main_clk.parent = &fpm_clk; + + dp_ctl = __raw_readl(pll2_base + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll2_sw_clk.parent = &fpm_clk; + + dp_ctl = __raw_readl(pll3_base + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll3_sw_clk.parent = &fpm_clk; + } else { + /* set pll4_clk parent */ + pll4_sw_clk.parent = &osc_clk; + } + + /* set emi_slow_clk parent */ + emi_slow_clk.parent = &main_bus_clk; + reg = __raw_readl(MXC_CCM_CBCDR); + if ((reg & MXC_CCM_CBCDR_EMI_CLK_SEL) != 0) + emi_slow_clk.parent = &ahb_clk; + + /* set ipg_perclk parent */ + ipg_perclk.parent = &lp_apm_clk; + reg = __raw_readl(MXC_CCM_CBCMR); + if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) { + ipg_perclk.parent = &ipg_clk; + } else { + if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0) + ipg_perclk.parent = &main_bus_clk; + } +} + + +int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) +{ + __iomem void *base; + struct clk *tclk; + int i = 0, j = 0, reg; + int wp_cnt = 0; + u32 pll1_rate; + + pll1_base = ioremap(PLL1_BASE_ADDR, SZ_4K); + pll2_base = ioremap(PLL2_BASE_ADDR, SZ_4K); + pll3_base = ioremap(PLL3_BASE_ADDR, SZ_4K); + + /* Turn off all possible clocks */ + if (mxc_jtag_enabled) { + __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET | + 1 << MXC_CCM_CCGRx_CG1_OFFSET | + 1 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 1 << MXC_CCM_CCGRx_CG12_OFFSET | + 1 << MXC_CCM_CCGRx_CG13_OFFSET | + 1 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0); + } else { + __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET | + 1 << MXC_CCM_CCGRx_CG1_OFFSET | + 1 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 1 << MXC_CCM_CCGRx_CG12_OFFSET | + 1 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0); + } + __raw_writel(0, MXC_CCM_CCGR1); + __raw_writel(0, MXC_CCM_CCGR2); + __raw_writel(0, MXC_CCM_CCGR3); + __raw_writel(1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR4); + + __raw_writel(1 << MXC_CCM_CCGRx_CG2_OFFSET | + 1 << MXC_CCM_CCGR5_CG6_1_OFFSET | + 1 << MXC_CCM_CCGR5_CG6_2_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 1 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 1 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET, MXC_CCM_CCGR5); + + __raw_writel(1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR6); + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + /* Fix up clocks unique to MX51. */ + esdhc2_clk[0].get_rate = _clk_esdhc2_get_rate; + esdhc2_clk[0].set_rate = _clk_esdhc2_set_rate; + + clk_tree_init(); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + clkdev_add(&lookups[i]); + mx51_clks[i].reg_clk = lookups[i].clk; + if (lookups[i].con_id != NULL) + strcpy(mx51_clks[i].name, lookups[i].con_id); + else + strcpy(mx51_clks[i].name, lookups[i].dev_id); + clk_register(&mx51_clks[i]); + } + + j = ARRAY_SIZE(lookups); + for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) { + clkdev_add(&mx51_lookups[i]); + mx51_clks[i+j].reg_clk = mx51_lookups[i].clk; + if (mx51_lookups[i].con_id != NULL) + strcpy(mx51_clks[i+j].name, mx51_lookups[i].con_id); + else + strcpy(mx51_clks[i+j].name, mx51_lookups[i].dev_id); + clk_register(&mx51_clks[i+j]); + } + + max_axi_a_clk = MAX_AXI_A_CLK_MX51; + max_axi_b_clk = MAX_AXI_B_CLK_MX51; + max_ahb_clk = MAX_AHB_CLK_MX51; + max_emi_slow_clk = MAX_AHB_CLK_MX51; + + /* set DDR clock parent */ + reg = 0; + if (cpu_is_mx51_rev(CHIP_REV_2_0) >= 1) { + reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL; + reg >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET; + + if (reg) + tclk = &ddr_hf_clk; + } + if (reg == 0) { + reg = __raw_readl(MXC_CCM_CBCMR) & + MXC_CCM_CBCMR_DDR_CLK_SEL_MASK; + reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; + + if (reg == 0) { + tclk = &axi_a_clk; + } else if (reg == 1) { + tclk = &axi_b_clk; + } else if (reg == 2) { + tclk = &emi_slow_clk; + } else { + tclk = &ahb_clk; + } + } + clk_set_parent(&ddr_clk, tclk); + + /*Setup the LPM bypass bits */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS + | MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX51 + | MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51; + __raw_writel(reg, MXC_CCM_CLPCR); + + /* Disable the handshake with HSC block as its not + * initialised right now. + */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_HSC_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + clk_enable(&cpu_clk); + + /* Set SDHC parents to be PLL2 */ + clk_set_parent(&esdhc1_clk[0], &pll2_sw_clk); + clk_set_parent(&esdhc2_clk[0], &pll2_sw_clk); + + /* set SDHC root clock as 166.25MHZ*/ + clk_set_rate(&esdhc1_clk[0], 166250000); + clk_set_rate(&esdhc2_clk[0], 166250000); + + /* Initialise the parents to be axi_b, parents are set to + * axi_a when the clocks are enabled. + */ + clk_set_parent(&vpu_clk[0], &axi_b_clk); + clk_set_parent(&vpu_clk[1], &axi_b_clk); + clk_set_parent(&gpu3d_clk, &axi_a_clk); + clk_set_parent(&gpu2d_clk, &axi_a_clk); + + /* move cspi to 24MHz */ + clk_set_parent(&cspi_main_clk, &lp_apm_clk); + clk_set_rate(&cspi_main_clk, 12000000); + /*move the spdif0 to spdif_xtal_ckl */ + clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk); + /*set the SPDIF dividers to 1 */ + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK; + reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK; + __raw_writel(reg, MXC_CCM_CDCDR); + + /* move the spdif1 to 24MHz */ + clk_set_parent(&spdif1_clk[0], &spdif_xtal_clk); + /* set the spdif1 dividers to 1 */ + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK; + reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK; + __raw_writel(reg, MXC_CCM_CDCDR); + + /* Move SSI clocks to SSI_LP_APM clock */ + clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk); + + clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk); + /* set the SSI dividers to divide by 2 */ + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CS2CDR); + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS2CDR); + + /* + * SSI3 has no clock divide register, + * we always set SSI3 parent clock to SSI1 and freq same to SSI1 + */ + clk_set_parent(&ssi3_clk[0], &ssi1_clk[0]); + + /* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */ + clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]); + clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]); + + /* move usb_phy_clk to 24MHz */ + clk_set_parent(&usb_phy_clk[0], &osc_clk); + + /* set usboh3_clk to pll2 */ + clk_set_parent(&usboh3_clk[0], &pll2_sw_clk); + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + /* Update the cpu working point table based on the PLL1 freq + * at boot time + */ + pll1_rate = clk_get_rate(&pll1_main_clk); + if (pll1_rate <= cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + wp_cnt = 1; + else if (pll1_rate <= cpu_wp_tbl[1].cpu_rate && + pll1_rate > cpu_wp_tbl[2].cpu_rate) + wp_cnt = cpu_wp_nr - 1; + else + wp_cnt = cpu_wp_nr; + + cpu_wp_tbl[0].cpu_rate = pll1_rate; + + if (wp_cnt == 1) { + cpu_wp_tbl[0] = cpu_wp_tbl[cpu_wp_nr - 1]; + memset(&cpu_wp_tbl[cpu_wp_nr - 1], 0, sizeof(struct cpu_wp)); + memset(&cpu_wp_tbl[cpu_wp_nr - 2], 0, sizeof(struct cpu_wp)); + } else if (wp_cnt < cpu_wp_nr) { + for (i = 0; i < wp_cnt; i++) + cpu_wp_tbl[i] = cpu_wp_tbl[i+1]; + memset(&cpu_wp_tbl[i], 0, sizeof(struct cpu_wp)); + } + + if (wp_cnt < cpu_wp_nr) { + set_num_cpu_wp(wp_cnt); + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + } + + pll1_rate = clk_get_rate(&pll1_main_clk); + for (j = 0; j < cpu_wp_nr; j++) { + if ((ddr_clk.parent == &ddr_hf_clk)) { + /* Change the CPU podf divider based on the boot up + * pll1 rate. + */ + cpu_wp_tbl[j].cpu_podf = + (pll1_rate / cpu_wp_tbl[j].cpu_rate) + - 1; + if (pll1_rate / (cpu_wp_tbl[j].cpu_podf + 1) > + cpu_wp_tbl[j].cpu_rate) { + cpu_wp_tbl[j].cpu_podf++; + cpu_wp_tbl[j].cpu_rate = + pll1_rate / + (1000 * (cpu_wp_tbl[j].cpu_podf + 1)); + cpu_wp_tbl[j].cpu_rate *= 1000; + } + if (pll1_rate / (cpu_wp_tbl[j].cpu_podf + 1) < + cpu_wp_tbl[j].cpu_rate) { + cpu_wp_tbl[j].cpu_rate = pll1_rate; + } + } + cpu_wp_tbl[j].pll_rate = pll1_rate; + } + /* Set the current working point. */ + for (i = 0; i < cpu_wp_nr; i++) { + if (clk_get_rate(&cpu_clk) == cpu_wp_tbl[i].cpu_rate) { + cpu_curr_wp = i; + break; + } + } + if (i > cpu_wp_nr) + BUG(); + + clk_set_parent(&arm_axi_clk, &axi_a_clk); + clk_set_parent(&ipu_clk[0], &axi_b_clk); + + if (uart_at_24) { + /* Move UART to run from lp_apm */ + clk_set_parent(&uart_main_clk, &lp_apm_clk); + + /* Set the UART dividers to divide, so the UART_CLK is 24MHz. */ + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK; + reg |= (0 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) | + (0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CSCDR1); + } else { + clk_set_parent(&uart_main_clk, &pll2_sw_clk); + + /* Set the UART dividers to divide, so the UART_CLK is 66.5MHz. */ + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK; + reg |= (4 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) | + (1 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CSCDR1); + } + + clk_set_parent(&emi_slow_clk, &ahb_clk); + clk_set_rate(&emi_slow_clk, clk_round_rate(&emi_slow_clk, 130000000)); + + /* Change the NFC clock rate to be 1:4 ratio with emi clock. */ + clk_set_rate(&emi_enfc_clk, clk_round_rate(&emi_enfc_clk, + (clk_get_rate(&emi_slow_clk))/4)); + + base = ioremap(GPT1_BASE_ADDR, SZ_4K); + mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); + return 0; +} + +int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) +{ + __iomem void *base; + struct clk *tclk; + int i = 0, j = 0, reg; + u32 pll1_rate; + + pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); + pll2_base = ioremap(MX53_BASE_ADDR(PLL2_BASE_ADDR), SZ_4K); + pll3_base = ioremap(MX53_BASE_ADDR(PLL3_BASE_ADDR), SZ_4K); + pll4_base = ioremap(MX53_BASE_ADDR(PLL4_BASE_ADDR), SZ_4K); + + /* Turn off all possible clocks */ + if (mxc_jtag_enabled) { + __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET | + 1 << MXC_CCM_CCGRx_CG1_OFFSET | + 1 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 1 << MXC_CCM_CCGRx_CG12_OFFSET | + 1 << MXC_CCM_CCGRx_CG13_OFFSET | + 1 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0); + } else { + __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET | + 1 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 1 << MXC_CCM_CCGRx_CG12_OFFSET | + 1 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0); + } + + __raw_writel(0, MXC_CCM_CCGR1); + __raw_writel(0, MXC_CCM_CCGR2); + __raw_writel(0, MXC_CCM_CCGR3); + __raw_writel(1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR4); + + __raw_writel(1 << MXC_CCM_CCGRx_CG2_OFFSET | + 1 << MXC_CCM_CCGRx_CG6_OFFSET | + 3 << MXC_CCM_CCGRx_CG7_OFFSET | + 1 << MXC_CCM_CCGRx_CG8_OFFSET | + 1 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET, MXC_CCM_CCGR5); + + __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 1 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET , MXC_CCM_CCGR6); + + __raw_writel(0, MXC_CCM_CCGR7); + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + usb_phy_clk[0].enable_reg = MXC_CCM_CCGR4; + usb_phy_clk[0].enable_shift = MXC_CCM_CCGRx_CG5_OFFSET; + + ipumux1_clk.enable_reg = MXC_CCM_CCGR5; + ipumux1_clk.enable_shift = MXC_CCM_CCGRx_CG6_OFFSET; + ipumux2_clk.enable_reg = MXC_CCM_CCGR6; + ipumux2_clk.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET; + + esdhc3_clk[0].get_rate = _clk_esdhc3_get_rate; + esdhc3_clk[0].set_rate = _clk_sdhc3_set_rate; + +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) + usboh3_clk[1].secondary = &emi_intr_clk[1]; +#endif +#ifdef CONFIG_SND_MXC_SOC_IRAM + ssi2_clk[2].secondary = &emi_intr_clk[1]; + ssi1_clk[2].secondary = &emi_intr_clk[1]; +#endif +#ifdef CONFIG_SDMA_IRAM + sdma_clk[1].secondary = &emi_intr_clk[1]; +#endif + + clk_tree_init(); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + clkdev_add(&lookups[i]); + mx53_clks[i].reg_clk = lookups[i].clk; + if (lookups[i].con_id != NULL) + strcpy(mx53_clks[i].name, lookups[i].con_id); + else + strcpy(mx53_clks[i].name, lookups[i].dev_id); + clk_register(&mx53_clks[i]); + } + + j = ARRAY_SIZE(lookups); + for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) { + clkdev_add(&mx53_lookups[i]); + mx53_clks[i+j].reg_clk = mx53_lookups[i].clk; + if (mx53_lookups[i].con_id != NULL) + strcpy(mx53_clks[i+j].name, mx53_lookups[i].con_id); + else + strcpy(mx53_clks[i+j].name, mx53_lookups[i].dev_id); + clk_register(&mx53_clks[i+j]); + } + + clk_set_parent(&esai_clk[0], &ckih_clk); + + ldb_di_clk[0].parent = ldb_di_clk[1].parent = + tve_clk.parent = &pll4_sw_clk; + + max_axi_a_clk = MAX_AXI_A_CLK_MX53; + max_axi_b_clk = MAX_AXI_B_CLK_MX53; + max_ahb_clk = MAX_AHB_CLK_MX53; + max_emi_slow_clk = MAX_AHB_CLK_MX53; + + + /* set DDR clock parent */ + reg = __raw_readl(MXC_CCM_CBCMR) & + MXC_CCM_CBCMR_DDR_CLK_SEL_MASK; + reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; + if (reg == 0) { + tclk = &axi_a_clk; + } else if (reg == 1) { + tclk = &axi_b_clk; + } else if (reg == 2) { + tclk = &emi_slow_clk; + } else { + tclk = &ahb_clk; + } + clk_set_parent(&ddr_clk, tclk); + + clk_set_parent(&esdhc1_clk[2], &tmax2_clk); + clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]); + clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk); + + clk_set_parent(&ipu_di_clk[0], &pll4_sw_clk); + +#if 0 + /*Setup the LPM bypass bits */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS + | MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +#endif + + clk_enable(&cpu_clk); + + clk_enable(&main_bus_clk); + + /* Set AXI_B_CLK to be 200MHz */ + clk_set_rate(&axi_b_clk, 200000000); + + /* Initialise the parents to be axi_b, parents are set to + * axi_a when the clocks are enabled. + */ + + clk_set_parent(&vpu_clk[0], &axi_b_clk); + clk_set_parent(&vpu_clk[1], &axi_b_clk); + + /* move cspi to 24MHz */ + clk_set_parent(&cspi_main_clk, &lp_apm_clk); + clk_set_rate(&cspi_main_clk, 12000000); + /*move the spdif0 to spdif_xtal_ckl */ + clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk); + /*set the SPDIF dividers to 1 */ + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK; + reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK; + __raw_writel(reg, MXC_CCM_CDCDR); + + /* Move SSI clocks to SSI_LP_APM clock */ + clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk); + + clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk); + /* set the SSI dividers to divide by 2 */ + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CS2CDR); + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS2CDR); + + /* Change the SSI_EXT1_CLK to be sourced from PLL2 for camera */ + clk_disable(&ssi_ext1_clk); + clk_set_parent(&ssi_ext1_clk, &pll2_sw_clk); + clk_set_rate(&ssi_ext1_clk, 24000000); + clk_enable(&ssi_ext1_clk); + clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]); + + /* move usb_phy_clk to 24MHz */ + clk_set_parent(&usb_phy_clk[0], &osc_clk); + clk_set_parent(&usb_phy_clk[1], &osc_clk); + + /* set usboh3_clk to pll2 */ + clk_set_parent(&usboh3_clk[0], &pll2_sw_clk); + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + /* set SDHC root clock as 200MHZ*/ + clk_set_rate(&esdhc1_clk[0], 200000000); + clk_set_rate(&esdhc3_clk[0], 200000000); + + /* Set the 1588 RTC input clocks as 108MHZ */ + clk_set_parent(&ieee_rtc_clk, &pll3_sw_clk); + clk_set_rate(&ieee_rtc_clk, 108000000); + + /* The CPU working point should be set according to part number + * information. But part number information is not clear now. + * So update the cpu working point table based on the PLL1 freq + * at boot time + */ + pll1_rate = clk_get_rate(&pll1_main_clk); + + if (pll1_rate > 1000000000) + mx53_set_cpu_part_number(IMX53_CEC_1_2G); + else if (pll1_rate > 800000000) + mx53_set_cpu_part_number(IMX53_CEC); + else + mx53_set_cpu_part_number(IMX53_AEC); + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + for (i = 0; i < cpu_wp_nr; i++) { + if (clk_get_rate(&cpu_clk) == cpu_wp_tbl[i].cpu_rate) { + cpu_curr_wp = i; + break; + } + } + if (i > cpu_wp_nr) + BUG(); + + clk_set_parent(&arm_axi_clk, &axi_b_clk); + clk_set_parent(&ipu_clk[0], &axi_b_clk); + clk_set_parent(&uart_main_clk, &pll3_sw_clk); + clk_set_parent(&gpu3d_clk, &axi_b_clk); + clk_set_parent(&gpu2d_clk, &axi_b_clk); + + clk_set_parent(&emi_slow_clk, &ahb_clk); + clk_set_rate(&emi_slow_clk, clk_round_rate(&emi_slow_clk, 133333333)); + + clk_set_rate(&emi_enfc_clk, clk_round_rate(&emi_enfc_clk, + MAX_NFC_CLK)); + + /* set the freq of asrc_serial_clk */ + clk_set_rate(&asrc_clk[0], clk_round_rate(&asrc_clk[0], + 1190000)); + base = ioremap(MX53_BASE_ADDR(GPT1_BASE_ADDR), SZ_4K); + mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); + return 0; +} + +/*! + * Setup cpu clock based on working point. + * @param wp cpu freq working point + * @return 0 on success or error code on failure. + */ +static int cpu_clk_set_wp(int wp) +{ + struct cpu_wp *p; + u32 reg, pll_hfsm; + u32 stat; + + if (wp == cpu_curr_wp) + return 0; + + p = &cpu_wp_tbl[wp]; + + /* + * If DDR clock is sourced from PLL1, we cannot drop PLL1 freq. + * Use the ARM_PODF to change the freq of the core, leave the PLL1 + * freq unchanged. Meanwhile, if pll_rate is same, use the ARM_PODF + * to change the freq of core + */ + if ((ddr_clk.parent == &ddr_hf_clk) || + (p->pll_rate == cpu_wp_tbl[cpu_curr_wp].pll_rate)) { + reg = __raw_readl(MXC_CCM_CACRR); + reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK; + reg |= cpu_wp_tbl[wp].cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CACRR); + cpu_curr_wp = wp; + } else { + struct timespec nstimeofday; + struct timespec curtime; + + /* Change the ARM clock to requested frequency */ + /* First move the ARM clock to step clock which is running + * at 24MHz. + */ + + /* Change the source of pll1_sw_clk to be the step_clk */ + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + + /* Stop the PLL */ + reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL); + reg &= ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); + + reg = __raw_readl(MXC_CCM_CACRR); + reg = (reg & ~MXC_CCM_CACRR_ARM_PODF_MASK) + | p->cpu_podf; + __raw_writel(reg, MXC_CCM_CACRR); + + reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL); + pll_hfsm = reg & MXC_PLL_DP_CTL_HFSM; + /* PDF and MFI */ + reg = p->pdf | p->mfi << MXC_PLL_DP_OP_MFI_OFFSET; + if (pll_hfsm == 0) { + __raw_writel(reg, pll1_base + MXC_PLL_DP_OP); + __raw_writel(p->mfd, pll1_base + MXC_PLL_DP_MFD); + __raw_writel(p->mfn, pll1_base + MXC_PLL_DP_MFN); + } else { + __raw_writel(reg, pll1_base + MXC_PLL_DP_HFS_OP); + __raw_writel(p->mfd, pll1_base + MXC_PLL_DP_HFS_MFD); + __raw_writel(p->mfn, pll1_base + MXC_PLL_DP_HFS_MFN); + } + + reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL); + reg |= MXC_PLL_DP_CTL_UPEN; + /* Set the UPEN bits */ + __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); + /* Forcefully restart the PLL */ + reg |= MXC_PLL_DP_CTL_RST; + __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); + + /* Wait for the PLL to lock */ + getnstimeofday(&nstimeofday); + do { + getnstimeofday(&curtime); + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) + panic("pll1 relock failed\n"); + stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL) & + MXC_PLL_DP_CTL_LRF; + } while (!stat); + + reg = __raw_readl(MXC_CCM_CCSR); + /* Move the PLL1 back to the pll1_main_clk */ + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + + cpu_curr_wp = wp; + } + +#if defined(CONFIG_CPU_FREQ) + cpufreq_trig_needed = 1; +#endif + return 0; +} diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c new file mode 100644 index 000000000000..87eee08fdbb5 --- /dev/null +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -0,0 +1,3523 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" +#include "serial.h" + +/* External clock values passed-in by the board code */ +static unsigned long external_high_reference, external_low_reference; +static unsigned long oscillator_reference, ckih2_reference; + +static struct clk pll1_main_clk; +static struct clk pll1_sw_clk; +static struct clk pll2_sw_clk; +static struct clk pll3_sw_clk; +static struct clk apbh_dma_clk; +static struct clk apll_clk; +static struct clk pfd0_clk; +static struct clk pfd1_clk; +static struct clk pfd2_clk; +static struct clk pfd3_clk; +static struct clk pfd4_clk; +static struct clk pfd5_clk; +static struct clk pfd6_clk; +static struct clk pfd7_clk; +static struct clk lp_apm_clk; +static struct clk weim_clk[]; +static struct clk ddr_clk; +static struct clk axi_a_clk; +static struct clk axi_b_clk; +static struct clk gpu2d_clk; +static int cpu_curr_wp; +static struct cpu_wp *cpu_wp_tbl; + +static void __iomem *pll1_base; +static void __iomem *pll2_base; +static void __iomem *pll3_base; +void __iomem *apll_base; + +extern int cpu_wp_nr; +extern int lp_high_freq; +extern int lp_med_freq; + +void __iomem *databahn; + +#define DDR_SYNC_MODE 0x30000 +#define SPIN_DELAY 1000000 /* in nanoseconds */ +#define WAIT(exp, timeout) \ +({ \ + struct timespec nstimeofday; \ + struct timespec curtime; \ + int result = 1; \ + getnstimeofday(&nstimeofday); \ + while (!(exp)) { \ + getnstimeofday(&curtime); \ + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \ + result = 0; \ + break; \ + } \ + } \ + result; \ +}) + +#define MAX_AXI_A_CLK_MX50 400000000 +#define MAX_AXI_B_CLK_MX50 200000000 +#define MAX_AHB_CLK 133333333 +#define MAX_EMI_SLOW_CLK 133000000 + +extern int mxc_jtag_enabled; +extern int uart_at_24; +extern int cpufreq_trig_needed; +extern int low_bus_freq_mode; +extern int med_bus_freq_mode; + +static int cpu_clk_set_wp(int wp); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); + +static struct clk esdhc3_clk[]; + +static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) +{ + u32 min_pre, temp_pre, old_err, err; + + if (div >= 512) { + *pre = 8; + *post = 64; + } else if (div >= 8) { + min_pre = (div - 1) / 64 + 1; + old_err = 8; + for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { + err = div % temp_pre; + if (err == 0) { + *pre = temp_pre; + break; + } + err = temp_pre - err; + if (err < old_err) { + old_err = err; + *pre = temp_pre; + } + } + *post = (div + *pre - 1) / *pre; + } else if (div < 8) { + *pre = div; + *post = 1; + } +} + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + + return 0; +} + +static int _clk_enable_inrun(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq--; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq--; +} + +static void _clk_disable_inwait(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +static unsigned long _clk_round_rate_div(struct clk *clk, + unsigned long rate, + u32 max_div, + u32 *new_div) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = DIV_ROUND_UP(parent_rate, rate); + if (div > max_div) + div = max_div; + else if (div == 0) + div++; + if (new_div != NULL) + *new_div = div; + + return parent_rate / div; +} +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else + BUG(); + + return 0; +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux8(struct clk *parent, struct clk *m0, struct clk *m1, + struct clk *m2, struct clk *m3, struct clk *m4, + struct clk *m5, struct clk *m6, struct clk *m7) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else if (parent == m4) + return 4; + else if (parent == m5) + return 5; + else if (parent == m6) + return 6; + else if (parent == m7) + return 7; + else + BUG(); + + return 0; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) + return pll1_base; + else if (pll == &pll2_sw_clk) + return pll2_base; + else if (pll == &pll3_sw_clk) + return pll3_base; + else + BUG(); + + return NULL; +} + +static unsigned long get_high_reference_clock_rate(struct clk *clk) +{ + return external_high_reference; +} + +static unsigned long get_low_reference_clock_rate(struct clk *clk) +{ + return external_low_reference; +} + +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) +{ + return oscillator_reference; +} + +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) +{ + return ckih2_reference; +} + +/* External high frequency clock */ +static struct clk ckih_clk = { + .get_rate = get_high_reference_clock_rate, +}; + +static struct clk ckih2_clk = { + .get_rate = get_ckih2_reference_clock_rate, +}; + +static struct clk osc_clk = { + .get_rate = get_oscillator_reference_clock_rate, +}; + +/* External low frequency (32kHz) clock */ +static struct clk ckil_clk = { + .get_rate = get_low_reference_clock_rate, +}; + +static int apll_enable(struct clk *clk) +{ + __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET); + return 0; +} + +static void apll_disable(struct clk *clk) +{ + __raw_writel(1, apll_base + MXC_ANADIG_MISC_CLR); +} + +static unsigned long apll_get_rate(struct clk *clk) +{ + return 480000000; +} + +static struct clk apll_clk = { + .get_rate = apll_get_rate, + .enable = apll_enable, + .disable = apll_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + tmp = (u64)clk_get_rate(clk->parent) * 18; + do_div(tmp, rate); + frac = tmp; + frac = frac < 18 ? 18 : frac; + frac = frac > 35 ? 35 : frac; + do_div(tmp, frac); + return tmp; +} + +static int pfd_set_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + tmp = (u64)clk_get_rate(clk->parent) * 18; + + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.enable(&apbh_dma_clk); + + do_div(tmp, rate); + frac = tmp; + frac = frac < 18 ? 18 : frac; + frac = frac > 35 ? 35 : frac; + /* clear clk frac bits */ + __raw_writel(MXC_ANADIG_PFD_FRAC_MASK << clk->enable_shift, + apll_base + (int)clk->enable_reg + 8); + /* set clk frac bits */ + __raw_writel(frac << clk->enable_shift, + apll_base + (int)clk->enable_reg + 4); + + tmp = (u64)clk_get_rate(clk->parent) * 18; + do_div(tmp, frac); + + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.disable(&apbh_dma_clk); + return 0; +} + +static int pfd_enable(struct clk *clk) +{ + int index; + + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.enable(&apbh_dma_clk); + index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk, + &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk); + __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), + apll_base + MXC_ANADIG_PLLCTRL_CLR); + /* clear clk gate bit */ + __raw_writel((1 << (clk->enable_shift + 7)), + apll_base + (int)clk->enable_reg + 8); + + /* check lock bit */ + if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) + & MXC_ANADIG_APLL_LOCK, 50000)) { + __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, + apll_base + MXC_ANADIG_PLLCTRL_CLR); + __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, + apll_base + MXC_ANADIG_PLLCTRL_SET); + if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) + & MXC_ANADIG_APLL_LOCK, SPIN_DELAY)) + panic("pfd_enable failed!\n"); + } + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.disable(&apbh_dma_clk); + return 0; +} + +static void pfd_disable(struct clk *clk) +{ + int index; + + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.enable(&apbh_dma_clk); + index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk, + &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk); + /* set clk gate bit */ + __raw_writel((1 << (clk->enable_shift + 7)), + apll_base + (int)clk->enable_reg + 4); + __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), + apll_base + MXC_ANADIG_PLLCTRL_SET); + if (apbh_dma_clk.usecount == 0) + apbh_dma_clk.disable(&apbh_dma_clk); +} + +static struct clk pfd0_clk = { + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC0, + .enable_shift = MXC_ANADIG_PFD0_FRAC_OFFSET, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk pfd1_clk = { + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC0, + .enable_shift = MXC_ANADIG_PFD1_FRAC_OFFSET, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk pfd2_clk = { + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC0, + .enable_shift = MXC_ANADIG_PFD2_FRAC_OFFSET, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk pfd3_clk = { + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC0, + .enable_shift = MXC_ANADIG_PFD3_FRAC_OFFSET, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk pfd4_clk = { + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC1, + .enable_shift = MXC_ANADIG_PFD4_FRAC_OFFSET, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk pfd5_clk = { + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC1, + .enable_shift = MXC_ANADIG_PFD5_FRAC_OFFSET, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk pfd6_clk = { + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC1, + .enable_shift = MXC_ANADIG_PFD6_FRAC_OFFSET, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk pfd7_clk = { + .parent = &apll_clk, + .enable_reg = (void *)MXC_ANADIG_FRAC1, + .enable_shift = MXC_ANADIG_PFD7_FRAC_OFFSET, + .set_rate = pfd_set_rate, + .round_rate = pfd_round_rate, + .enable = pfd_enable, + .disable = pfd_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long _clk_pll_get_rate(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + void __iomem *pllbase; + s64 temp; + + pllbase = _get_pll_base(clk); + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * clk_get_rate(clk->parent); + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + return temp; +} + +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, reg1; + void __iomem *pllbase; + + long mfi, pdf, mfn, mfd = 999999; + s64 temp64; + unsigned long quad_parent_rate; + unsigned long pll_hfsm, dp_ctl; + + pllbase = _get_pll_base(clk); + + quad_parent_rate = 4 * clk_get_rate(clk->parent); + pdf = mfi = -1; + while (++pdf < 16 && mfi < 5) + mfi = rate * (pdf+1) / quad_parent_rate; + if (mfi > 15) + return -1; + pdf--; + + temp64 = rate*(pdf+1) - quad_parent_rate*mfi; + do_div(temp64, quad_parent_rate/1000000); + mfn = (long)temp64; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + /* use dpdck0_2 */ + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + if (pll_hfsm == 0) { + reg = mfi<<4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); + } else { + reg = mfi<<4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); + } + /* If auto restart is disabled, restart the PLL and + * wait for it to lock. + */ + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + if (reg & MXC_PLL_DP_CTL_UPEN) { + reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG); + if (!(reg & MXC_PLL_DP_CONFIG_AREN)) { + reg1 = __raw_readl(pllbase + MXC_PLL_DP_CTL); + reg1 |= MXC_PLL_DP_CTL_RST; + __raw_writel(reg1, pllbase + MXC_PLL_DP_CTL); + } + /* Wait for lock */ + if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) + & MXC_PLL_DP_CTL_LRF, SPIN_DELAY)) + panic("pll_set_rate: pll relock failed\n"); + } + return 0; +} + +static int _clk_pll_enable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + + if (reg & MXC_PLL_DP_CTL_UPEN) + return 0; + + reg |= MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + + /* Wait for lock */ + if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF, + SPIN_DELAY)) + panic("pll relock failed\n"); + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +} + +static struct clk pll1_main_clk = { + .parent = &osc_clk, + .get_rate = _clk_pll_get_rate, + .set_rate = _clk_pll_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll1_main_clk) { + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + /* Set the step_clk parent to be lp_apm, to save power. */ + mux = _get_mux(&lp_apm_clk, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = __raw_readl(MXC_CCM_CCSR); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + } else { + if (parent == &lp_apm_clk) { + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + } else { + mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk, + &pll3_sw_clk); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) | + (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCSR); + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + + } + } + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static unsigned long _clk_pll1_sw_get_rate(struct clk *clk) +{ + u32 reg, div; + div = 1; + reg = __raw_readl(MXC_CCM_CCSR); + + if (clk->parent == &pll2_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; + } else if (clk->parent == &pll3_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; + } + return clk_get_rate(clk->parent) / div; +} + +/* pll1 switch clock */ +static struct clk pll1_sw_clk = { + .parent = &pll1_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .get_rate = _clk_pll1_sw_get_rate, + .flags = RATE_PROPAGATES, +}; + +static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll2_sw_clk) { + reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + } else { + reg = (reg & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL); + reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +/* same as pll2_main_clk. These two clocks should always be the same */ +static struct clk pll2_sw_clk = { + .parent = &osc_clk, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_pll_set_rate, + .set_parent = _clk_pll2_sw_set_parent, + .flags = RATE_PROPAGATES, +}; + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .get_rate = _clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (parent == &osc_clk) + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; + else if (parent == &apll_clk) + reg = __raw_readl(MXC_CCM_CCSR) | MXC_CCM_CCSR_LP_APM_SEL; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static struct clk lp_apm_clk = { + .parent = &osc_clk, + .set_parent = _clk_lp_apm_set_parent, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_arm_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + u32 i; + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + if (i >= cpu_wp_nr) + return -EINVAL; + cpu_clk_set_wp(i); + + return 0; +} + +static unsigned long _clk_cpu_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 i; + u32 wp; + + for (i = 0; i < cpu_wp_nr; i++) { + if (rate == cpu_wp_tbl[i].cpu_rate) + break; + } + + if (i > cpu_wp_nr) + wp = 0; + + return cpu_wp_tbl[wp].cpu_rate; +} + + +static struct clk cpu_clk = { + .parent = &pll1_sw_clk, + .get_rate = _clk_arm_get_rate, + .set_rate = _clk_cpu_set_rate, + .round_rate = _clk_cpu_round_rate, +}; + +/* TODO: Need to sync with GPC to determine if DVFS is in place so that + * the DVFS_PODF divider can be applied in CDCR register. + */ +static unsigned long _clk_main_bus_get_rate(struct clk *clk) +{ + u32 div = 0; + + if (med_bus_freq_mode) + div = (__raw_readl(MXC_CCM_CDCR) & 0x3); + return clk_get_rate(clk->parent) / (div + 1); +} + +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CBCDR) & ~MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK; + reg |= (mux << MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + return 0; +} + +static struct clk main_bus_clk = { + .parent = &pll2_sw_clk, + .set_parent = _clk_main_bus_set_parent, + .get_rate = _clk_main_bus_get_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_axi_a_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AXI_A_PODF_MASK) >> + MXC_CCM_CBCDR_AXI_A_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) + & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY), SPIN_DELAY)) + panic("pll _clk_axi_a_set_rate failed\n"); + + return 0; +} + +static unsigned long _clk_axi_a_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + + if (div > 8) + div = 8; + else if (div == 0) + div++; + + return parent_rate / div; +} + + +static struct clk axi_a_clk = { + .parent = &main_bus_clk, + .get_rate = _clk_axi_a_get_rate, + .set_rate = _clk_axi_a_set_rate, + .round_rate = _clk_axi_a_round_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_axi_b_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AXI_B_PODF_MASK) >> + MXC_CCM_CBCDR_AXI_B_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) + & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY), SPIN_DELAY)) + panic("_clk_axi_b_set_rate failed\n"); + + return 0; +} + +static unsigned long _clk_axi_b_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + + if (div > 8) + div = 8; + else if (div == 0) + div++; + + return parent_rate / div; +} + + +static struct clk axi_b_clk = { + .parent = &main_bus_clk, + .get_rate = _clk_axi_b_get_rate, + .set_rate = _clk_axi_b_set_rate, + .round_rate = _clk_axi_b_round_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_ahb_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + + +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY), + SPIN_DELAY)) + panic("_clk_ahb_set_rate failed\n"); + + return 0; +} + +static unsigned long _clk_ahb_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (parent_rate / div > MAX_AHB_CLK) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + + +static struct clk ahb_clk = { + .parent = &main_bus_clk, + .get_rate = _clk_ahb_get_rate, + .set_rate = _clk_ahb_set_rate, + .round_rate = _clk_ahb_round_rate, + .flags = RATE_PROPAGATES, +}; + +static int _clk_max_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Handshake with MAX when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + + +static void _clk_max_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable_inwait(clk); + + /* No Handshake with MAX when LPM is entered as its disabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + + +static struct clk ahb_max_clk = { + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, +}; + +static struct clk ahbmux1_clk = { + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .disable = _clk_disable_inwait, +}; + +static unsigned long _clk_ipg_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static struct clk ipg_clk = { + .parent = &ahb_clk, + .get_rate = _clk_ipg_get_rate, + .flags = RATE_PROPAGATES, +}; + +static unsigned long _clk_ipg_per_get_rate(struct clk *clk) +{ + u32 reg, prediv1, prediv2, podf; + + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { + /* the main_bus_clk is the one before the DVFS engine */ + reg = __raw_readl(MXC_CCM_CBCDR); + prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; + prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; + podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / (prediv1 * prediv2 * podf); + } else if (clk->parent == &ipg_clk) { + return clk_get_rate(&ipg_clk); + } + BUG(); + return 0; +} + +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL); + if (mux == 2) { + reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + } else { + reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + if (mux == 0) + reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + else + reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk ipg_perclk = { + .parent = &lp_apm_clk, + .get_rate = _clk_ipg_per_get_rate, + .set_parent = _clk_ipg_per_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk ipmux1_clk = { + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk ipmux2_clk = { + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_sys_clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK | + MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK); + if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1) + reg |= MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK; + else + reg |= MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_CLK_SYS); + return 0; +} + +static void _clk_sys_clk_disable(struct clk *clk) +{ + u32 reg, reg1; + + reg1 = (__raw_readl(databahn + DATABAHN_CTL_REG55)) + & DDR_SYNC_MODE; + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK | + MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK); + if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1) + reg |= 1 << MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET; + else { + /* If DDR is sourced from SYS_CLK (in Sync mode), we cannot + * gate its clock when ARM is in wait if the DDR is not in + * self refresh. + */ + if (reg1 == DDR_SYNC_MODE) + reg |= 3 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET; + else + reg |= 1 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET; + } + __raw_writel(reg, MXC_CCM_CLK_SYS); +} + +static struct clk sys_clk = { + .enable = _clk_sys_clk_enable, + .disable = _clk_sys_clk_disable, +}; + + +static int _clk_weim_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCDR); + if (parent == &ahb_clk) + reg |= MX50_CCM_CBCDR_WEIM_CLK_SEL; + else if (parent == &main_bus_clk) + reg &= ~MX50_CCM_CBCDR_WEIM_CLK_SEL; + else + BUG(); + __raw_writel(reg, MXC_CCM_CBCDR); + + return 0; +} + +static int _clk_weim_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY), + SPIN_DELAY)) + panic("_clk_emi_slow_set_rate failed\n"); + + return 0; +} + +static unsigned long _clk_weim_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return parent_rate / div; +} + +static struct clk weim_clk[] = { + { + .parent = &main_bus_clk, + .set_parent = _clk_weim_set_parent, + .set_rate = _clk_weim_set_rate, + .round_rate = _clk_weim_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .disable = _clk_disable_inwait, + .flags = RATE_PROPAGATES, + .secondary = &weim_clk[1], + }, + { + .parent = &ipg_clk, + .secondary = &sys_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .disable = _clk_disable_inwait, + } +}; + +static int _clk_ocram_enable(struct clk *clk) +{ + return 0; +} + +static void _clk_ocram_disable(struct clk *clk) +{ +} + +static struct clk ocram_clk = { + .parent = &sys_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_ocram_enable, + .disable = _clk_ocram_disable, +}; + +static struct clk aips_tz1_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk aips_tz2_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk gpc_dvfs_clk = { + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static int _clk_sdma_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Handshake with SDMA when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_sdma_disable(struct clk *clk) +{ + u32 reg; + + _clk_disable(clk); + /* No handshake with SDMA as its not enabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + + +static struct clk sdma_clk[] = { + { + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_sdma_enable, + .disable = _clk_sdma_disable, + }, + { + .parent = &ipg_clk, + .secondary = &ddr_clk, + }, +}; + +static struct clk spba_clk = { + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static unsigned long _clk_uart_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent)/(prediv * podf) ; +} + +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk uart_main_clk = { + .parent = &pll2_sw_clk, + .get_rate = _clk_uart_get_rate, + .set_parent = _clk_uart_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk uart1_clk[] = { + { + .id = 0, + .parent = &uart_main_clk, + .secondary = &uart1_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART1_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 0, + .parent = &ipg_clk, +#if UART1_DMA_ENABLE + .secondary = &aips_tz1_clk, +#endif + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart2_clk[] = { + { + .id = 1, + .parent = &uart_main_clk, + .secondary = &uart2_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART2_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 1, + .parent = &ipg_clk, +#if UART2_DMA_ENABLE + .secondary = &aips_tz1_clk, +#endif + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart3_clk[] = { + { + .id = 2, + .parent = &uart_main_clk, + .secondary = &uart3_clk[1], + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART3_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 2, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart4_clk[] = { + { + .id = 3, + .parent = &uart_main_clk, + .secondary = &uart4_clk[1], + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART4_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 3, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart5_clk[] = { + { + .id = 4, + .parent = &uart_main_clk, + .secondary = &uart5_clk[1], + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#if UART5_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .id = 4, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk gpt_clk[] = { + { + .parent = &ipg_perclk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk pwm1_clk[] = { + { + .parent = &ipg_perclk, + .id = 0, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &pwm1_clk[1], + }, + { + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ckil_clk, + }, +}; + +static struct clk pwm2_clk[] = { + { + .parent = &ipg_perclk, + .id = 1, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &pwm2_clk[1], + }, + { + .id = 1, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ckil_clk, + }, +}; + +static struct clk i2c_clk[] = { + { + .id = 0, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 2, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static unsigned long _clk_cspi_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk cspi_main_clk = { + .parent = &pll3_sw_clk, + .get_rate = _clk_cspi_get_rate, + .set_parent = _clk_cspi_set_parent, + .flags = RATE_PROPAGATES, +}; + +static struct clk cspi1_clk[] = { + { + .id = 0, + .parent = &cspi_main_clk, + .secondary = &cspi1_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, +}; + +static struct clk cspi2_clk[] = { + { + .id = 1, + .parent = &cspi_main_clk, + .secondary = &cspi2_clk[1], + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ipg_clk, + .secondary = &aips_tz2_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable_inrun, /*Active only when ARM is running. */ + .disable = _clk_disable, + }, +}; + +static struct clk cspi3_clk = { + .id = 2, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &aips_tz2_clk, +}; + +static int _clk_ssi_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &ckih_clk, &lp_apm_clk, &ckih2_clk, NULL); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_lp_apm_clk = { + .parent = &ckih_clk, + .set_parent = _clk_ssi_lp_apm_set_parent, +}; + +static unsigned long _clk_ssi1_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} +static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi1_clk[] = { + { + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi1_set_parent, + .secondary = &ssi1_clk[1], + .get_rate = _clk_ssi1_get_rate, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ipg_clk, + .secondary = &ssi1_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &aips_tz2_clk, + }, +}; + +static unsigned long _clk_ssi2_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi2_clk[] = { + { + .id = 1, + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi2_set_parent, + .secondary = &ssi2_clk[1], + .get_rate = _clk_ssi2_get_rate, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &ipg_clk, + .secondary = &ssi2_clk[2], + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &spba_clk, + }, +}; + +static unsigned long _clk_ssi_ext1_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + u32 div = 1; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CS1CDR); + prediv = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET) + 1; + div = prediv * podf; + } + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || div > 512) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~(MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK | + MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + return 0; +} + +static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi1_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_ssi_ext1_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(div, &pre, &post); + + return parent_rate / (pre * post); +} + +static struct clk ssi_ext1_clk = { + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext1_set_parent, + .set_rate = _clk_ssi_ext1_set_rate, + .round_rate = _clk_ssi_ext1_round_rate, + .get_rate = _clk_ssi_ext1_get_rate, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static unsigned long _clk_ssi_ext2_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + u32 div = 1; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if ((reg & MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL) == 0) { + reg = __raw_readl(MXC_CCM_CS2CDR); + prediv = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK) >> + MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET) + 1; + if (prediv == 1) + BUG(); + podf = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK) >> + MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET) + 1; + div = prediv * podf; + } + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ssi_ext2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &ssi2_clk[0]) { + reg |= MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + } else { + reg &= ~MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL; + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &ssi_lp_apm_clk); + reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK) | + (mux << MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET); + } + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi_ext2_clk = { + .parent = &pll3_sw_clk, + .set_parent = _clk_ssi_ext2_set_parent, + .get_rate = _clk_ssi_ext2_get_rate, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk tmax2_clk = { + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk usb_ahb_clk = { + .parent = &ipg_clk, + .secondary = &ddr_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .disable = _clk_disable, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk usb_phy_clk[] = { + { + .id = 0, + .parent = &osc_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .disable = _clk_disable, + }, + { + .id = 1, + .parent = &osc_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .disable = _clk_disable, + } +}; + +static struct clk esdhc_dep_clks = { + .parent = &spba_clk, + .secondary = &ddr_clk, +}; + +static unsigned long _clk_esdhc1_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = reg & ~MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK; + reg |= mux << MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + + +static int _clk_esdhc1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static struct clk esdhc1_clk[] = { + { + .id = 0, + .parent = &pll2_sw_clk, + .set_parent = _clk_esdhc1_set_parent, + .get_rate = _clk_esdhc1_get_rate, + .set_rate = _clk_esdhc1_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc1_clk[1], + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .id = 0, + .parent = &ipg_clk, + .secondary = &esdhc1_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, + +}; + +static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MX50_CCM_CSCMR1_ESDHC2_CLK_SEL; + else if (parent == &esdhc3_clk[0]) + reg |= MX50_CCM_CSCMR1_ESDHC2_CLK_SEL; + else + BUG(); + __raw_writel(reg, MXC_CCM_CSCMR1); + return 0; +} + +static struct clk esdhc2_clk[] = { + { + .id = 1, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc2_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc2_clk[1], + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .id = 1, + .parent = &ipg_clk, + .secondary = &esdhc2_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1); + mux = _get_mux8(parent, &pll1_sw_clk, &pll2_sw_clk, + &pll3_sw_clk, &lp_apm_clk, &pfd0_clk, + &pfd1_clk, &pfd4_clk, &osc_clk); + reg = reg & ~MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK; + reg |= mux << MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_esdhc3_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_esdhc3_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if ((parent_rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + + +static struct clk esdhc3_clk[] = { + { + .id = 2, + .parent = &pll2_sw_clk, + .set_parent = _clk_esdhc3_set_parent, + .get_rate = _clk_esdhc3_get_rate, + .set_rate = _clk_esdhc3_set_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc3_clk[1], + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .id = 2, + .parent = &ipg_clk, + .secondary = &esdhc3_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &ahb_max_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MX50_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc3_clk[0]) + reg |= MX50_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + BUG(); + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk esdhc4_clk[] = { + { + .id = 3, + .parent = &esdhc1_clk[0], + .set_parent = _clk_esdhc4_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .disable = _clk_disable, + .secondary = &esdhc4_clk[1], + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .id = 3, + .parent = &ipg_clk, + .secondary = &esdhc4_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .disable = _clk_disable, + }, + { + .id = 0, + .parent = &tmax2_clk, + .secondary = &esdhc_dep_clks, + }, +}; + +static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CLK_DDR); + if (parent == &pfd0_clk) + reg |= MXC_CCM_CLK_DDR_DDR_PFD_SEL; + else if (parent == &pll1_sw_clk) + reg &= ~MXC_CCM_CLK_DDR_DDR_PFD_SEL; + else + return -EINVAL; + __raw_writel(reg, MXC_CCM_CLK_DDR); + return 0; +} + +static unsigned long _clk_ddr_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CLK_DDR); + div = (reg & MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK) >> + MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET; + if (div) + return clk_get_rate(clk->parent) / div; + + return 0; +} + +static int _clk_ddr_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + reg = (__raw_readl(databahn + DATABAHN_CTL_REG55)) & + DDR_SYNC_MODE; + if (reg != DDR_SYNC_MODE) { + reg = __raw_readl(MXC_CCM_CLK_DDR); + reg |= MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_CLK_DDR); + } + return 0; +} + +static void _clk_ddr_disable(struct clk *clk) +{ + _clk_disable_inwait(clk); +} + + +static struct clk ddr_clk = { + .parent = &pll1_sw_clk, + .secondary = &sys_clk, + .set_parent = _clk_ddr_set_parent, + .get_rate = _clk_ddr_get_rate, + .enable = _clk_ddr_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .disable = _clk_ddr_disable, +}; + +static unsigned long _clk_pgc_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET; + div = 1 >> div; + return clk_get_rate(clk->parent) / div; +} + +static struct clk pgc_clk = { + .parent = &ipg_clk, + .get_rate = _clk_pgc_get_rate, +}; + +static unsigned long _clk_usb_get_rate(struct clk *clk) +{ + return 60000000; +} + +/*usb OTG clock */ +static struct clk usb_clk = { + .get_rate = _clk_usb_get_rate, +}; + +static struct clk rtc_clk = { + .parent = &ckil_clk, + .secondary = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .disable = _clk_disable, +}; + +struct clk rng_clk = { + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk owire_clk = { + .parent = &ipg_perclk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .disable = _clk_disable, +}; + +static struct clk fec_clk[] = { + { + .parent = &ipg_clk, + .secondary = &fec_clk[1], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .parent = &aips_tz2_clk, + .secondary = &ddr_clk, + }, +}; + +static int gpmi_clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_GPMI); + reg |= MXC_CCM_GPMI_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_GPMI); + _clk_enable(clk); + return 0; +} + +static void gpmi_clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_GPMI); + reg &= ~MXC_CCM_GPMI_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_GPMI); + _clk_disable(clk); +} + +static int bch_clk_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_BCH); + reg |= MXC_CCM_BCH_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_BCH); + _clk_enable(clk); + return 0; +} + +static void bch_clk_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_BCH); + reg &= ~MXC_CCM_BCH_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_BCH); + _clk_disable(clk); +} + +static int gpmi_set_parent(struct clk *clk, struct clk *parent) +{ + /* Setting for ONFI nand which need PLL1(800MHZ) */ + if (parent == &pll1_main_clk) { + u32 reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_MASK) | + (0x2 << MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_OFFSET); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_MASK) | + (0x2 << MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + /* change to the new Parent */ + clk->parent = parent; + } else + printk(KERN_WARNING "You should not call the %s\n", __func__); + return 0; +} + +static int gpmi_set_rate(struct clk *clk, unsigned long rate) +{ + /* Setting for ONFI nand which in different mode */ + if (clk->parent == &pll1_main_clk) { + u32 value; + u32 reg; + + value = clk_get_rate(clk->parent); + value /= rate; + value /= 2; /* HW_GPMI_CTRL1's GPMI_CLK_DIV2_EN will be set */ + + /* set GPMI clock */ + reg = __raw_readl(MXC_CCM_GPMI); + reg = (reg & ~MXC_CCM_GPMI_CLK_DIV_MASK) | value; + __raw_writel(reg, MXC_CCM_GPMI); + + /* set BCH clock */ + reg = __raw_readl(MXC_CCM_BCH); + reg = (reg & ~MXC_CCM_BCH_CLK_DIV_MASK) | value; + __raw_writel(reg, MXC_CCM_BCH); + } else + printk(KERN_WARNING "You should not call the %s\n", __func__); + return 0; +} + +static struct clk gpmi_nfc_clk[] = { + { /* gpmi_io_clk */ + .parent = &osc_clk, + .secondary = &gpmi_nfc_clk[1], + .set_parent = gpmi_set_parent, + .set_rate = gpmi_set_rate, + .enable = gpmi_clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .disable = gpmi_clk_disable, + }, + { /* gpmi_apb_clk */ + .parent = &ahb_clk, + .secondary = &gpmi_nfc_clk[2], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .disable = _clk_disable, + }, + { /* bch_clk */ + .parent = &osc_clk, + .secondary = &gpmi_nfc_clk[3], + .enable = bch_clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = bch_clk_disable, + }, + { /* bch_apb_clk */ + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk ocotp_clk = { + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CBCMR); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &weim_clk[0], &ahb_clk); + reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) | + (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static struct clk gpu2d_clk = { + .parent = &axi_a_clk, + .secondary = &ddr_clk, + .set_parent = _clk_gpu2d_set_parent, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk apbh_dma_clk = { + .parent = &ahb_clk, + .secondary = &ddr_clk, + .enable = _clk_enable, + .disable = _clk_disable_inwait, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, +}; + +struct clk dcp_clk = { + .parent = &ahb_clk, + .secondary = &apbh_dma_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .disable = _clk_disable, +}; + +static int _clk_display_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + mux = _get_mux(parent, &osc_clk, &pfd2_clk, &pll1_sw_clk, NULL); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + return 0; +} + +static unsigned long _clk_display_axi_get_rate(struct clk *clk) +{ + u32 div; + + div = __raw_readl(MXC_CCM_DISPLAY_AXI); + div &= MXC_CCM_DISPLAY_AXI_DIV_MASK; + if (div == 0) { /* gated off */ + return clk_get_rate(clk->parent); + } else { + return clk_get_rate(clk->parent) / div; + } +} + +static unsigned long _clk_display_axi_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 max_div = (2 << 6) - 1; + return _clk_round_rate_div(clk, rate, max_div, NULL); +} + +static int _clk_display_axi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div, max_div; + u32 reg; + + max_div = (2 << 6) - 1; + _clk_round_rate_div(clk, rate, max_div, &new_div); + + reg = __raw_readl(MXC_CCM_DISPLAY_AXI); + reg &= ~MXC_CCM_DISPLAY_AXI_DIV_MASK; + reg |= new_div << MXC_CCM_DISPLAY_AXI_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_DISPLAY_AXI); + + while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_DISPLAY_AXI_BUSY) + ; + return 0; +} + +static struct clk display_axi_clk = { + .parent = &osc_clk, + .secondary = &apbh_dma_clk, + .set_parent = _clk_display_axi_set_parent, + .get_rate = _clk_display_axi_get_rate, + .set_rate = _clk_display_axi_set_rate, + .round_rate = _clk_display_axi_round_rate, + .enable = _clk_enable, + .disable = _clk_disable, + .enable_reg = MXC_CCM_DISPLAY_AXI, + .enable_shift = MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_pxp_axi_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + /* Set the auto-slow bits */ + reg = __raw_readl(MXC_CCM_DISPLAY_AXI); + reg |= (MXC_CCM_DISPLAY_AXI_PXP_ASM_EN); + reg |= (5 << MXC_CCM_DISPLAY_AXI_PXP_ASM_DIV_OFFSET); + __raw_writel(reg, MXC_CCM_DISPLAY_AXI); + + return 0; +} + +static void _clk_pxp_axi_disable(struct clk *clk) +{ + u32 reg; + + /* clear the auto-slow bits */ + reg = __raw_readl(MXC_CCM_DISPLAY_AXI); + reg &= ~MXC_CCM_DISPLAY_AXI_PXP_ASM_EN; + __raw_writel(reg, MXC_CCM_DISPLAY_AXI); + + _clk_disable(clk); +} + + +/* TODO: check Auto-Slow Mode */ +static struct clk pxp_axi_clk = { + .parent = &display_axi_clk, + .enable = _clk_pxp_axi_enable, + .disable = _clk_pxp_axi_disable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk elcdif_axi_clk = { + .parent = &display_axi_clk, + .enable = _clk_enable, + .disable = _clk_disable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_elcdif_pix_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + mux = _get_mux(parent, &osc_clk, &pfd6_clk, &pll1_sw_clk, &ckih_clk); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_MASK) | + (mux << MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + return 0; +} + +static unsigned long _clk_elcdif_pix_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + prediv = ((reg & MXC_CCM_ELCDIFPIX_CLK_PRED_MASK) >> + MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_ELCDIFPIX_CLK_PODF_MASK) >> + MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static unsigned long _clk_elcdif_pix_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 max_div = (2 << 12) - 1; + return _clk_round_rate_div(clk, rate, max_div, NULL); +} + +static int _clk_elcdif_pix_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div, max_div; + u32 reg; + + max_div = (2 << 12) - 1; + _clk_round_rate_div(clk, rate, max_div, &new_div); + + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + /* Pre-divider set to 1 - only use PODF for clk dividing */ + reg &= ~MXC_CCM_ELCDIFPIX_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET; + reg &= ~MXC_CCM_ELCDIFPIX_CLK_PODF_MASK; + reg |= new_div << MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_ELCDIFPIX); + + return 0; +} + +static int _clk_elcdif_pix_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + reg |= 0x3 << MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET; + __raw_writel(reg, MXC_CCM_ELCDIFPIX); + return 0; +} + +static void _clk_elcdif_pix_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + reg &= ~MXC_CCM_ELCDIFPIX_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_ELCDIFPIX); + _clk_disable(clk); +} + +static struct clk elcdif_pix_clk = { + .parent = &osc_clk, + .secondary = &ddr_clk, + .enable = _clk_elcdif_pix_enable, + .disable = _clk_elcdif_pix_disable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .set_parent = _clk_elcdif_pix_set_parent, + .get_rate = _clk_elcdif_pix_get_rate, + .round_rate = _clk_elcdif_pix_round_rate, + .set_rate = _clk_elcdif_pix_set_rate, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_epdc_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + mux = _get_mux(parent, &osc_clk, &pfd3_clk, &pll1_sw_clk, NULL); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_MASK) | + (mux << MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + return 0; +} + +static unsigned long _clk_epdc_axi_get_rate(struct clk *clk) +{ + u32 div; + + div = __raw_readl(MXC_CCM_EPDC_AXI); + div &= MXC_CCM_EPDC_AXI_DIV_MASK; + if (div == 0) { /* gated off */ + return clk_get_rate(clk->parent); + } else { + return clk_get_rate(clk->parent) / div; + } +} + +static unsigned long _clk_epdc_axi_round_rate_div(struct clk *clk, + unsigned long rate, + u32 *new_div) +{ + u32 div, max_div; + + max_div = (2 << 6) - 1; + div = DIV_ROUND_UP(clk_get_rate(clk->parent), rate); + if (div > max_div) + div = max_div; + else if (div == 0) + div++; + if (new_div != NULL) + *new_div = div; + return clk_get_rate(clk->parent) / div; +} + +static unsigned long _clk_epdc_axi_round_rate(struct clk *clk, + unsigned long rate) +{ + return _clk_epdc_axi_round_rate_div(clk, rate, NULL); +} + +static int _clk_epdc_axi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div; + u32 reg; + + _clk_epdc_axi_round_rate_div(clk, rate, &new_div); + + reg = __raw_readl(MXC_CCM_EPDC_AXI); + reg &= ~MXC_CCM_EPDC_AXI_DIV_MASK; + reg |= new_div << MXC_CCM_EPDC_AXI_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_EPDC_AXI); + + while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_EPDC_AXI_BUSY) + ; + + return 0; +} + +static int _clk_epdc_axi_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + + reg = __raw_readl(MXC_CCM_EPDC_AXI); + reg |= MXC_CCM_EPDC_AXI_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_EPDC_AXI); + + /* Set the auto-slow bits */ + reg = __raw_readl(MXC_CCM_EPDC_AXI); + reg |= (MXC_CCM_EPDC_AXI_ASM_EN); + reg |= (5 << MXC_CCM_EPDC_AXI_ASM_DIV_OFFSET); + __raw_writel(reg, MXC_CCM_EPDC_AXI); + + return 0; +} + +static void _clk_epdc_axi_disable(struct clk *clk) +{ + u32 reg; + + /* clear the auto-slow bits */ + reg = __raw_readl(MXC_CCM_EPDC_AXI); + reg &= ~MXC_CCM_EPDC_AXI_ASM_EN; + __raw_writel(reg, MXC_CCM_EPDC_AXI); + + reg = __raw_readl(MXC_CCM_EPDC_AXI); + reg &= ~MXC_CCM_EPDC_AXI_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_EPDC_AXI); + _clk_disable(clk); +} + +/* TODO: check Auto-Slow Mode */ +static struct clk epdc_axi_clk = { + .parent = &osc_clk, + .secondary = &apbh_dma_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .set_parent = _clk_epdc_axi_set_parent, + .get_rate = _clk_epdc_axi_get_rate, + .set_rate = _clk_epdc_axi_set_rate, + .round_rate = _clk_epdc_axi_round_rate, + .enable = _clk_epdc_axi_enable, + .disable = _clk_epdc_axi_disable, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + + +static int _clk_epdc_pix_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + mux = _get_mux(parent, &osc_clk, &pfd5_clk, &pll1_sw_clk, &ckih_clk); + reg = (reg & ~MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_MASK) | + (mux << MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + + return 0; +} + +static unsigned long _clk_epdc_pix_get_rate(struct clk *clk) +{ + u32 div; + + div = __raw_readl(MXC_CCM_EPDCPIX); + div &= MXC_CCM_EPDC_PIX_CLK_PODF_MASK; + if (div == 0) { /* gated off */ + return clk_get_rate(clk->parent); + } else { + return clk_get_rate(clk->parent) / div; + } +} + +static unsigned long _clk_epdc_pix_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 max_div = (2 << 12) - 1; + return _clk_round_rate_div(clk, rate, max_div, NULL); +} + +static int _clk_epdc_pix_set_rate(struct clk *clk, unsigned long rate) +{ + u32 new_div, max_div; + u32 reg; + + max_div = (2 << 12) - 1; + _clk_round_rate_div(clk, rate, max_div, &new_div); + + reg = __raw_readl(MXC_CCM_EPDCPIX); + /* Pre-divider set to 1 - only use PODF for clk dividing */ + reg &= ~MXC_CCM_EPDC_PIX_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_EPDC_PIX_CLK_PRED_OFFSET; + reg &= ~MXC_CCM_EPDC_PIX_CLK_PODF_MASK; + reg |= new_div << MXC_CCM_EPDC_PIX_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_EPDCPIX); + + while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_EPDC_PIX_BUSY) + ; + + return 0; +} + +static int _clk_epdc_pix_enable(struct clk *clk) +{ + u32 reg; + + _clk_enable(clk); + reg = __raw_readl(MXC_CCM_EPDCPIX); + reg |= MXC_CCM_EPDC_PIX_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_EPDCPIX); + + return 0; +} + +static void _clk_epdc_pix_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_EPDCPIX); + reg &= ~MXC_CCM_EPDC_PIX_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_EPDCPIX); + _clk_disable(clk); +} + +/* TODO: check Auto-Slow Mode */ +static struct clk epdc_pix_clk = { + .parent = &osc_clk, + .secondary = &apbh_dma_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .set_parent = _clk_epdc_pix_set_parent, + .get_rate = _clk_epdc_pix_get_rate, + .set_rate = _clk_epdc_pix_set_rate, + .round_rate = _clk_epdc_pix_round_rate, + .enable = _clk_epdc_pix_enable, + .disable = _clk_epdc_pix_disable, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long cko1_get_rate(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= MX50_CCM_CCOSR_CKO1_DIV_MASK; + reg = reg >> MX50_CCM_CCOSR_CKO1_DIV_OFFSET; + return clk_get_rate(clk->parent) / (reg + 1); +} + +static int cko1_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg |= MX50_CCM_CCOSR_CKO1_EN; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static void cko1_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MX50_CCM_CCOSR_CKO1_EN; + __raw_writel(reg, MXC_CCM_CCOSR); +} + +static int cko1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = (parent_rate/rate - 1) & 0x7; + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MX50_CCM_CCOSR_CKO1_DIV_MASK; + reg |= div << MX50_CCM_CCOSR_CKO1_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static unsigned long cko1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + div = div < 1 ? 1 : div; + div = div > 8 ? 8 : div; + return parent_rate / div; +} + +static int cko1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg, fast; + + if (parent == &cpu_clk) { + sel = 0; + fast = 1; + } else if (parent == &pll1_sw_clk) { + sel = 1; + fast = 1; + } else if (parent == &pll2_sw_clk) { + sel = 2; + fast = 1; + } else if (parent == &pll3_sw_clk) { + sel = 3; + fast = 1; + } else if (parent == &apll_clk) { + sel = 0; + fast = 0; + } else if (parent == &pfd0_clk) { + sel = 1; + fast = 0; + } else if (parent == &pfd1_clk) { + sel = 2; + fast = 0; + } else if (parent == &pfd2_clk) { + sel = 3; + fast = 0; + } else if (parent == &pfd3_clk) { + sel = 4; + fast = 0; + } else if (parent == &pfd4_clk) { + sel = 5; + fast = 0; + } else if (parent == &pfd5_clk) { + sel = 6; + fast = 0; + } else if (parent == &pfd6_clk) { + sel = 7; + fast = 0; + } else if (parent == &weim_clk[0]) { + sel = 10; + fast = 0; + } else if (parent == &ahb_clk) { + sel = 11; + fast = 0; + } else if (parent == &ipg_clk) { + sel = 12; + fast = 0; + } else if (parent == &ipg_perclk) { + sel = 13; + fast = 0; + } else if (parent == &pfd7_clk) { + sel = 15; + fast = 0; + } else + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MX50_CCM_CCOSR_CKO1_SEL_MASK; + reg |= sel << MX50_CCM_CCOSR_CKO1_SEL_OFFSET; + if (fast) + reg &= ~MX50_CCM_CCOSR_CKO1_SLOW_SEL; + else + reg |= MX50_CCM_CCOSR_CKO1_SLOW_SEL; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static struct clk cko1_clk = { + .parent = &pll1_sw_clk, + .get_rate = cko1_get_rate, + .enable = cko1_enable, + .disable = cko1_disable, + .set_rate = cko1_set_rate, + .round_rate = cko1_round_rate, + .set_parent = cko1_set_parent, +}; + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + } + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK(NULL, "osc", osc_clk), + _REGISTER_CLOCK(NULL, "ckih", ckih_clk), + _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk), + _REGISTER_CLOCK(NULL, "ckil", ckil_clk), + _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_main_clk), + _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk), + _REGISTER_CLOCK(NULL, "pll2", pll2_sw_clk), + _REGISTER_CLOCK(NULL, "pll3", pll3_sw_clk), + _REGISTER_CLOCK(NULL, "apll", apll_clk), + _REGISTER_CLOCK(NULL, "pfd0", pfd0_clk), + _REGISTER_CLOCK(NULL, "pfd1", pfd1_clk), + _REGISTER_CLOCK(NULL, "pfd2", pfd2_clk), + _REGISTER_CLOCK(NULL, "pfd3", pfd3_clk), + _REGISTER_CLOCK(NULL, "pfd4", pfd4_clk), + _REGISTER_CLOCK(NULL, "pfd5", pfd5_clk), + _REGISTER_CLOCK(NULL, "pfd6", pfd6_clk), + _REGISTER_CLOCK(NULL, "pfd7", pfd7_clk), + _REGISTER_CLOCK(NULL, "gpc_dvfs_clk", gpc_dvfs_clk), + _REGISTER_CLOCK(NULL, "lp_apm", lp_apm_clk), + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk), + _REGISTER_CLOCK(NULL, "main_bus_clk", main_bus_clk), + _REGISTER_CLOCK(NULL, "axi_a_clk", axi_a_clk), + _REGISTER_CLOCK(NULL, "axi_b_clk", axi_b_clk), + _REGISTER_CLOCK(NULL, "ahb_clk", ahb_clk), + _REGISTER_CLOCK(NULL, "ahb_max_clk", ahb_max_clk), + _REGISTER_CLOCK("mxc_sdma", "sdma_ahb_clk", sdma_clk[0]), + _REGISTER_CLOCK("mxc_sdma", "sdma_ipg_clk", sdma_clk[1]), + _REGISTER_CLOCK("mxcintuart.0", NULL, uart1_clk[0]), + _REGISTER_CLOCK("mxcintuart.1", NULL, uart2_clk[0]), + _REGISTER_CLOCK("mxcintuart.2", NULL, uart3_clk[0]), + _REGISTER_CLOCK("mxcintuart.3", NULL, uart4_clk[0]), + _REGISTER_CLOCK("mxcintuart.4", NULL, uart5_clk[0]), + _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk[0]), + _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]), + _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]), + _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk[0]), + _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk[0]), + _REGISTER_CLOCK("mxc_spi.0", NULL, cspi1_clk[0]), + _REGISTER_CLOCK("mxc_spi.1", NULL, cspi2_clk[0]), + _REGISTER_CLOCK("mxc_spi.2", NULL, cspi3_clk), + _REGISTER_CLOCK(NULL, "ssi_lp_apm_clk", ssi_lp_apm_clk), + _REGISTER_CLOCK("mxc_ssi.0", NULL, ssi1_clk[0]), + _REGISTER_CLOCK("mxc_ssi.1", NULL, ssi2_clk[0]), + _REGISTER_CLOCK(NULL, "ssi_ext1_clk", ssi_ext1_clk), + _REGISTER_CLOCK(NULL, "ssi_ext2_clk", ssi_ext2_clk), + _REGISTER_CLOCK(NULL, "usb_ahb_clk", usb_ahb_clk), + _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy_clk[0]), + _REGISTER_CLOCK(NULL, "usb_phy2_clk", usb_phy_clk[1]), + _REGISTER_CLOCK(NULL, "usb_clk", usb_clk), + _REGISTER_CLOCK("mxsdhci.0", NULL, esdhc1_clk[0]), + _REGISTER_CLOCK("mxsdhci.1", NULL, esdhc2_clk[0]), + _REGISTER_CLOCK("mxsdhci.2", NULL, esdhc3_clk[0]), + _REGISTER_CLOCK("mxsdhci.3", NULL, esdhc4_clk[0]), + _REGISTER_CLOCK(NULL, "ddr_clk", ddr_clk), + _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk), + _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), + _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_clk), + _REGISTER_CLOCK(NULL, "cko1", cko1_clk), + _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]), + _REGISTER_CLOCK("fec.0", NULL, fec_clk[0]), + _REGISTER_CLOCK(NULL, "fec_sec1_clk", fec_clk[1]), + _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), + _REGISTER_CLOCK(NULL, "gpmi-nfc", gpmi_nfc_clk[0]), + _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nfc_clk[1]), + _REGISTER_CLOCK(NULL, "bch", gpmi_nfc_clk[2]), + _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nfc_clk[3]), + _REGISTER_CLOCK(NULL, "rng_clk", rng_clk), + _REGISTER_CLOCK(NULL, "dcp_clk", dcp_clk), + _REGISTER_CLOCK(NULL, "ocotp_ctrl_apb", ocotp_clk), + _REGISTER_CLOCK(NULL, "ocram_clk", ocram_clk), + _REGISTER_CLOCK(NULL, "apbh_dma_clk", apbh_dma_clk), + _REGISTER_CLOCK(NULL, "sys_clk", sys_clk), + _REGISTER_CLOCK(NULL, "elcdif_pix", elcdif_pix_clk), + _REGISTER_CLOCK(NULL, "display_axi", display_axi_clk), + _REGISTER_CLOCK(NULL, "elcdif_axi", elcdif_axi_clk), + _REGISTER_CLOCK(NULL, "pxp_axi", pxp_axi_clk), + _REGISTER_CLOCK(NULL, "epdc_axi", epdc_axi_clk), + _REGISTER_CLOCK(NULL, "epdc_pix", epdc_pix_clk), +}; + +static struct mxc_clk mxc_clks[ARRAY_SIZE(lookups)]; + +static void clk_tree_init(void) +{ + u32 reg; + + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); + + /* + *Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at + * 8MHz, its derived from lp_apm. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; + reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + /* set pll1_main_clk parent */ + pll1_main_clk.parent = &osc_clk; + + /* set pll2_sw_clk parent */ + pll2_sw_clk.parent = &osc_clk; + + /* set pll3_clk parent */ + pll3_sw_clk.parent = &osc_clk; + + /* set weim_clk parent */ + weim_clk[0].parent = &main_bus_clk; + reg = __raw_readl(MXC_CCM_CBCDR); + if ((reg & MX50_CCM_CBCDR_WEIM_CLK_SEL) != 0) + weim_clk[0].parent = &ahb_clk; + + /* set ipg_perclk parent */ + ipg_perclk.parent = &lp_apm_clk; + reg = __raw_readl(MXC_CCM_CBCMR); + if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) { + ipg_perclk.parent = &ipg_clk; + } else { + if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0) + ipg_perclk.parent = &main_bus_clk; + } +} + +int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1) +{ + __iomem void *base; + int i = 0, j = 0, reg; + int wp_cnt = 0; + u32 pll1_rate; + + pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); + pll2_base = ioremap(MX53_BASE_ADDR(PLL2_BASE_ADDR), SZ_4K); + pll3_base = ioremap(MX53_BASE_ADDR(PLL3_BASE_ADDR), SZ_4K); + apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K); + + /* Turn off all possible clocks */ + if (mxc_jtag_enabled) { + __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG4_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 1 << MXC_CCM_CCGRx_CG12_OFFSET | + 1 << MXC_CCM_CCGRx_CG13_OFFSET | + 1 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0); + } else { + __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG3_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET | + 1 << MXC_CCM_CCGRx_CG12_OFFSET | + 1 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0); + } + + __raw_writel(0, MXC_CCM_CCGR1); + __raw_writel(0, MXC_CCM_CCGR2); + __raw_writel(0, MXC_CCM_CCGR3); + __raw_writel(0, MXC_CCM_CCGR4); + + __raw_writel(3 << MXC_CCM_CCGRx_CG6_OFFSET | + 1 << MXC_CCM_CCGRx_CG8_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET, MXC_CCM_CCGR5); + + __raw_writel(3 << MXC_CCM_CCGRx_CG0_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 2 << MXC_CCM_CCGRx_CG14_OFFSET | + 3 << MXC_CCM_CCGRx_CG15_OFFSET, MXC_CCM_CCGR6); + + __raw_writel(0, MXC_CCM_CCGR7); + + external_low_reference = ckil; + external_high_reference = ckih1; + oscillator_reference = osc; + + usb_phy_clk[0].enable_reg = MXC_CCM_CCGR4; + usb_phy_clk[0].enable_shift = MXC_CCM_CCGRx_CG5_OFFSET; + + clk_tree_init(); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + clkdev_add(&lookups[i]); + mxc_clks[i].reg_clk = lookups[i].clk; + if (lookups[i].con_id != NULL) + strcpy(mxc_clks[i].name, lookups[i].con_id); + else + strcpy(mxc_clks[i].name, lookups[i].dev_id); + clk_register(&mxc_clks[i]); + } + + /* set DDR clock parent */ + reg = __raw_readl(MXC_CCM_CLK_DDR) & + MXC_CCM_CLK_DDR_DDR_PFD_SEL; + if (reg) + clk_set_parent(&ddr_clk, &pfd0_clk); + else + clk_set_parent(&ddr_clk, &pll1_sw_clk); + + clk_set_parent(&esdhc1_clk[0], &pll2_sw_clk); + clk_set_parent(&esdhc1_clk[2], &tmax2_clk); + clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]); + clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk); + + clk_enable(&cpu_clk); + + clk_enable(&main_bus_clk); + + clk_enable(&ocotp_clk); + + databahn = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K); + + /* Initialise the parents to be axi_b, parents are set to + * axi_a when the clocks are enabled. + */ + + clk_set_parent(&gpu2d_clk, &axi_a_clk); + + /* move cspi to 24MHz */ + clk_set_parent(&cspi_main_clk, &lp_apm_clk); + clk_set_rate(&cspi_main_clk, 12000000); + + /* + * Set DISPLAY_AXI to 200Mhz + * For Display AXI, source clocks must be + * enabled before dividers can be changed + */ + clk_enable(&display_axi_clk); + clk_enable(&elcdif_axi_clk); + clk_enable(&pxp_axi_clk); + clk_set_parent(&display_axi_clk, &pfd2_clk); + clk_set_rate(&display_axi_clk, 200000000); + clk_disable(&display_axi_clk); + clk_disable(&pxp_axi_clk); + clk_disable(&elcdif_axi_clk); + + clk_enable(&elcdif_pix_clk); + clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk); + clk_disable(&elcdif_pix_clk); + + /* + * Enable and set EPDC AXI to 200MHz + * For EPDC AXI, source clocks must be + * enabled before dividers can be changed + */ + clk_enable(&epdc_axi_clk); + clk_set_parent(&epdc_axi_clk, &pfd3_clk); + clk_set_rate(&epdc_axi_clk, 200000000); + clk_disable(&epdc_axi_clk); + + clk_set_parent(&epdc_pix_clk, &pfd5_clk); + + /* Move SSI clocks to SSI_LP_APM clock */ + clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk); + + clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk); + /* set the SSI dividers to divide by 2 */ + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CS2CDR); + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS2CDR); + + /* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */ + clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]); + clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]); + + /* move usb_phy_clk to 24MHz */ + clk_set_parent(&usb_phy_clk[0], &osc_clk); + clk_set_parent(&usb_phy_clk[1], &osc_clk); + + /* move gpmi-nfc to 24MHz */ + clk_set_parent(&gpmi_nfc_clk[0], &osc_clk); + + /* set SDHC root clock as 200MHZ*/ + clk_set_rate(&esdhc1_clk[0], 200000000); + clk_set_rate(&esdhc3_clk[0], 200000000); + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + /* Update the cpu working point table based on the PLL1 freq + * at boot time + */ + pll1_rate = clk_get_rate(&pll1_main_clk); + if (pll1_rate <= cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + wp_cnt = 1; + else if (pll1_rate <= cpu_wp_tbl[1].cpu_rate && + pll1_rate > cpu_wp_tbl[2].cpu_rate) + wp_cnt = cpu_wp_nr - 1; + else + wp_cnt = cpu_wp_nr; + + cpu_wp_tbl[0].cpu_rate = pll1_rate; + + if (wp_cnt == 1) { + cpu_wp_tbl[0] = cpu_wp_tbl[cpu_wp_nr - 1]; + memset(&cpu_wp_tbl[cpu_wp_nr - 1], 0, sizeof(struct cpu_wp)); + memset(&cpu_wp_tbl[cpu_wp_nr - 2], 0, sizeof(struct cpu_wp)); + } else if (wp_cnt < cpu_wp_nr) { + for (i = 0; i < wp_cnt; i++) + cpu_wp_tbl[i] = cpu_wp_tbl[i+1]; + memset(&cpu_wp_tbl[i], 0, sizeof(struct cpu_wp)); + } + + if (wp_cnt < cpu_wp_nr) { + set_num_cpu_wp(wp_cnt); + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + } + + pll1_rate = clk_get_rate(&pll1_main_clk); + for (j = 0; j < cpu_wp_nr; j++) { + /* Change the CPU podf divider based on the boot up + * pll1 rate. + */ + cpu_wp_tbl[j].cpu_podf = max( + (int)((pll1_rate / cpu_wp_tbl[j].cpu_rate) + - 1), 0); + if (pll1_rate/(cpu_wp_tbl[j].cpu_podf + 1) > + cpu_wp_tbl[j].cpu_rate) { + cpu_wp_tbl[j].cpu_podf++; + cpu_wp_tbl[j].cpu_rate = + pll1_rate/ + (1000 * (cpu_wp_tbl[j].cpu_podf + 1)); + cpu_wp_tbl[j].cpu_rate *= 1000; + } + if (pll1_rate/(cpu_wp_tbl[j].cpu_podf + 1) < + cpu_wp_tbl[j].cpu_rate) { + cpu_wp_tbl[j].cpu_rate = pll1_rate; + } + cpu_wp_tbl[j].pll_rate = pll1_rate; + } + /* Set the current working point. */ + for (i = 0; i < cpu_wp_nr; i++) { + if (clk_get_rate(&cpu_clk) == cpu_wp_tbl[i].cpu_rate) { + cpu_curr_wp = i; + break; + } + } + if (i > cpu_wp_nr) + BUG(); + + clk_set_parent(&uart_main_clk, &lp_apm_clk); + clk_set_parent(&gpu2d_clk, &axi_b_clk); + + clk_set_parent(&weim_clk[0], &ahb_clk); + clk_set_rate(&weim_clk[0], clk_round_rate(&weim_clk[0], 130000000)); + + /* Do the following just to disable the PLL since its not used */ + clk_enable(&pll3_sw_clk); + clk_disable(&pll3_sw_clk); + + base = ioremap(MX53_BASE_ADDR(GPT1_BASE_ADDR), SZ_4K); + mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); + return 0; +} + +/*! + * Setup cpu clock based on working point. + * @param wp cpu freq working point + * @return 0 on success or error code on failure. + */ +static int cpu_clk_set_wp(int wp) +{ + struct cpu_wp *p; + u32 reg; + + if (wp == cpu_curr_wp) + return 0; + + p = &cpu_wp_tbl[wp]; + + /* + * leave the PLL1 freq unchanged. + */ + reg = __raw_readl(MXC_CCM_CACRR); + reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK; + reg |= cpu_wp_tbl[wp].cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CACRR); + cpu_curr_wp = wp; + +#if defined(CONFIG_CPU_FREQ) + cpufreq_trig_needed = 1; +#endif + return 0; +} diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 2d37785e3857..abb33781c4c1 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -11,12 +11,37 @@ * This file contains the CPU initialization code. */ +#include #include +#include #include -#include #include +#include +#include +#include +#include +#include #include -#include +#include + +#define CORTEXA8_PLAT_AMC 0x18 +#define SRPG_NEON_PUPSCR 0x284 +#define SRPG_NEON_PDNSCR 0x288 +#define SRPG_ARM_PUPSCR 0x2A4 +#define SRPG_ARM_PDNSCR 0x2A8 +#define SRPG_EMPGC0_PUPSCR 0x2E4 +#define SRPG_EMPGC0_PDNSCR 0x2E8 +#define SRPG_EMPGC1_PUPSCR 0x304 +#define SRPG_EMPGC1_PDNSCR 0x308 + +void __iomem *arm_plat_base; +void __iomem *gpc_base; +void __iomem *ccm_base; +void __iomem *databahn_base; +void *wait_in_iram_base; +void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); + +extern void mx50_wait(u32 ccm_base, u32 databahn_addr); static int cpu_silicon_rev = -1; @@ -24,7 +49,7 @@ static int cpu_silicon_rev = -1; static void query_silicon_parameter(void) { - void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); + void __iomem *rom = ioremap(IROM_BASE_ADDR, IROM_SIZE); u32 rev; if (!rom) { @@ -35,16 +60,16 @@ static void query_silicon_parameter(void) rev = readl(rom + SI_REV); switch (rev) { case 0x1: - cpu_silicon_rev = MX51_CHIP_REV_1_0; + cpu_silicon_rev = CHIP_REV_1_0; break; case 0x2: - cpu_silicon_rev = MX51_CHIP_REV_1_1; + cpu_silicon_rev = CHIP_REV_1_1; break; case 0x10: - cpu_silicon_rev = MX51_CHIP_REV_2_0; + cpu_silicon_rev = CHIP_REV_2_0; break; case 0x20: - cpu_silicon_rev = MX51_CHIP_REV_3_0; + cpu_silicon_rev = CHIP_REV_3_0; break; default: cpu_silicon_rev = 0; @@ -70,30 +95,186 @@ int mx51_revision(void) } EXPORT_SYMBOL(mx51_revision); +struct cpu_wp *(*get_cpu_wp)(int *wp); +void (*set_num_cpu_wp)(int num); + +static void __init mipi_hsc_disable(void) +{ + void __iomem *reg_hsc_mcd = ioremap(MIPI_HSC_BASE_ADDR, SZ_4K); + void __iomem *reg_hsc_mxt_conf = reg_hsc_mcd + 0x800; + struct clk *clk; + uint32_t temp; + + /* Temporarily setup MIPI module to legacy mode */ + clk = clk_get(NULL, "mipi_hsp_clk"); + if (!IS_ERR(clk)) { + clk_enable(clk); + + /* Temporarily setup MIPI module to legacy mode */ + __raw_writel(0xF00, reg_hsc_mcd); + + /* CSI mode reserved*/ + temp = __raw_readl(reg_hsc_mxt_conf); + __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { + temp = __raw_readl(reg_hsc_mxt_conf); + __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); + } + + clk_disable(clk); + clk_put(clk); + } + iounmap(reg_hsc_mcd); +} + +/*! + * This function resets IPU + */ +void mx5_ipu_reset(void) +{ + u32 *reg; + u32 value; + reg = ioremap(MX53_BASE_ADDR(SRC_BASE_ADDR), PAGE_SIZE); + value = __raw_readl(reg); + value = value | 0x8; + __raw_writel(value, reg); + iounmap(reg); +} + +void mx5_vpu_reset(void) +{ + u32 reg; + void __iomem *src_base; + + src_base = ioremap(MX53_BASE_ADDR(SRC_BASE_ADDR), PAGE_SIZE); + + /* mask interrupt due to vpu passed reset */ + reg = __raw_readl(src_base + 0x18); + reg |= 0x02; + __raw_writel(reg, src_base + 0x18); + + reg = __raw_readl(src_base); + reg |= 0x5; /* warm reset vpu */ + __raw_writel(reg, src_base); + while (__raw_readl(src_base) & 0x04) + ; + + iounmap(src_base); +} + static int __init post_cpu_init(void) { - unsigned int reg; void __iomem *base; + unsigned int reg; + struct clk *gpcclk = clk_get(NULL, "gpc_dvfs_clk"); + int iram_size = IRAM_SIZE; - if (!cpu_is_mx51()) + if (!cpu_is_mx5()) return 0; - base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); + if (cpu_is_mx51()) { + mipi_hsc_disable(); + +#if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE) + iram_size -= SCC_RAM_SIZE; +#endif + iram_init(MX51_IRAM_BASE_ADDR, iram_size); + } else { + iram_init(MX53_IRAM_BASE_ADDR, iram_size); + } + + gpc_base = ioremap(MX53_BASE_ADDR(GPC_BASE_ADDR), SZ_4K); + ccm_base = ioremap(MX53_BASE_ADDR(CCM_BASE_ADDR), SZ_4K); + + clk_enable(gpcclk); + + /* Setup the number of clock cycles to wait for SRPG + * power up and power down requests. + */ + __raw_writel(0x010F0201, gpc_base + SRPG_ARM_PUPSCR); + __raw_writel(0x010F0201, gpc_base + SRPG_NEON_PUPSCR); + __raw_writel(0x00000008, gpc_base + SRPG_EMPGC0_PUPSCR); + __raw_writel(0x00000008, gpc_base + SRPG_EMPGC1_PUPSCR); + + __raw_writel(0x01010101, gpc_base + SRPG_ARM_PDNSCR); + __raw_writel(0x01010101, gpc_base + SRPG_NEON_PDNSCR); + __raw_writel(0x00000018, gpc_base + SRPG_EMPGC0_PDNSCR); + __raw_writel(0x00000018, gpc_base + SRPG_EMPGC1_PDNSCR); + + clk_disable(gpcclk); + clk_put(gpcclk); + + /* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */ + arm_plat_base = ioremap(MX53_BASE_ADDR(ARM_BASE_ADDR), SZ_4K); + reg = 0x8; + __raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_AMC); + + base = ioremap(MX53_BASE_ADDR(AIPS1_BASE_ADDR), SZ_4K); __raw_writel(0x0, base + 0x40); __raw_writel(0x0, base + 0x44); __raw_writel(0x0, base + 0x48); __raw_writel(0x0, base + 0x4C); reg = __raw_readl(base + 0x50) & 0x00FFFFFF; __raw_writel(reg, base + 0x50); + iounmap(base); - base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); + base = ioremap(MX53_BASE_ADDR(AIPS2_BASE_ADDR), SZ_4K); __raw_writel(0x0, base + 0x40); __raw_writel(0x0, base + 0x44); __raw_writel(0x0, base + 0x48); __raw_writel(0x0, base + 0x4C); reg = __raw_readl(base + 0x50) & 0x00FFFFFF; __raw_writel(reg, base + 0x50); + iounmap(base); + + if (cpu_is_mx51() || cpu_is_mx53()) { + /*Allow for automatic gating of the EMI internal clock. + * If this is done, emi_intr CCGR bits should be set to 11. + */ + base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); + reg = __raw_readl(base + 0x8c); + reg &= ~0x1; + __raw_writel(reg, base + 0x8c); + iounmap(base); + } + + databahn_base = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K); + + if (cpu_is_mx50()) { + struct clk *ddr_clk = clk_get(NULL, "ddr_clk"); + unsigned long iram_paddr; + iram_alloc(SZ_4K, &iram_paddr); + /* Need to remap the area here since we want the memory region + to be executable. */ + wait_in_iram_base = __arm_ioremap(iram_paddr, + SZ_4K, MT_HIGH_VECTORS); + memcpy(wait_in_iram_base, mx50_wait, SZ_4K); + wait_in_iram = (void *)wait_in_iram_base; + + clk_enable(ddr_clk); + + /* Set the DDR to enter automatic self-refresh. */ + /* Set the DDR to automatically enter lower power mode 4. */ + reg = __raw_readl(databahn_base + DATABAHN_CTL_REG22); + reg &= ~LOWPOWER_AUTOENABLE_MASK; + reg |= 1 << 1; + __raw_writel(reg, databahn_base + DATABAHN_CTL_REG22); + + /* set the counter for entering mode 4. */ + reg = __raw_readl(databahn_base + DATABAHN_CTL_REG21); + reg &= ~LOWPOWER_EXTERNAL_CNT_MASK; + reg = 128 << LOWPOWER_EXTERNAL_CNT_OFFSET; + __raw_writel(reg, databahn_base + DATABAHN_CTL_REG21); + + /* Enable low power mode 4 */ + reg = __raw_readl(databahn_base + DATABAHN_CTL_REG20); + reg &= ~LOWPOWER_CONTROL_MASK; + reg |= 1 << 1; + __raw_writel(reg, databahn_base + DATABAHN_CTL_REG20); + clk_disable(ddr_clk); + } return 0; } diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index c776b9af0624..45db5f60d7b1 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -11,12 +11,7 @@ #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) -#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) -#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) -#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) -#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) -#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) +#define MXC_CCM_BASE (IO_ADDRESS(CCM_BASE_ADDR)) /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 @@ -73,41 +68,108 @@ #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF +/* Register addresses of apll and pfd*/ +#define MXC_ANADIG_FRAC0 0x10 +#define MXC_ANADIG_FRAC0_SET 0x14 +#define MXC_ANADIG_FRAC0_CLR 0x18 +#define MXC_ANADIG_FRAC1 0x20 +#define MXC_ANADIG_FRAC1_SET 0x24 +#define MXC_ANADIG_FRAC1_CLR 0x28 +#define MXC_ANADIG_MISC 0x60 +#define MXC_ANADIG_MISC_SET 0x64 +#define MXC_ANADIG_MISC_CLR 0x68 +#define MXC_ANADIG_PLLCTRL 0x70 +#define MXC_ANADIG_PLLCTRL_SET 0x74 +#define MXC_ANADIG_PLLCTRL_CLR 0x78 + +/* apll and pfd Register Bit definitions */ + +#define MXC_ANADIG_PFD3_CLKGATE (1 << 31) +#define MXC_ANADIG_PFD3_STABLE (1 << 30) +#define MXC_ANADIG_PFD3_FRAC_OFFSET 24 +#define MXC_ANADIG_PFD_FRAC_MASK 0x3F +#define MXC_ANADIG_PFD2_CLKGATE (1 << 23) +#define MXC_ANADIG_PFD2_STABLE (1 << 22) +#define MXC_ANADIG_PFD2_FRAC_OFFSET 16 +#define MXC_ANADIG_PFD1_CLKGATE (1 << 15) +#define MXC_ANADIG_PFD1_STABLE (1 << 14) +#define MXC_ANADIG_PFD1_FRAC_OFFSET 8 +#define MXC_ANADIG_PFD0_CLKGATE (1 << 7) +#define MXC_ANADIG_PFD0_STABLE (1 << 6) +#define MXC_ANADIG_PFD0_FRAC_OFFSET 0 + +#define MXC_ANADIG_PFD7_CLKGATE (1 << 31) +#define MXC_ANADIG_PFD7_STABLE (1 << 30) +#define MXC_ANADIG_PFD7_FRAC_OFFSET 24 +#define MXC_ANADIG_PFD6_CLKGATE (1 << 23) +#define MXC_ANADIG_PFD6_STABLE (1 << 22) +#define MXC_ANADIG_PFD6_FRAC_OFFSET 16 +#define MXC_ANADIG_PFD5_CLKGATE (1 << 15) +#define MXC_ANADIG_PFD5_STABLE (1 << 14) +#define MXC_ANADIG_PFD5_FRAC_OFFSET 8 +#define MXC_ANADIG_PFD4_CLKGATE (1 << 7) +#define MXC_ANADIG_PFD4_STABLE (1 << 6) +#define MXC_ANADIG_PFD4_FRAC_OFFSET 0 + +#define MXC_ANADIG_APLL_LOCK (1 << 31) +#define MXC_ANADIG_APLL_FORCE_LOCK (1 << 30) +#define MXC_ANADIG_PFD_DIS_OFFSET 16 +#define MXC_ANADIG_PFD_DIS_MASK 0xff +#define MXC_ANADIG_APLL_LOCK_CNT_OFFSET 0 +#define MXC_ANADIG_APLL_LOCK_CNT_MASK 0xffff + /* Register addresses of CCM*/ -#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) -#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) -#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) -#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) -#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) -#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) -#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) -#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) -#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) -#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) -#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) -#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) -#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) -#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) -#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) -#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) -#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) -#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) -#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) -#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) -#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) -#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) -#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) -#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) -#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) -#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) -#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) -#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) -#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) -#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) -#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) -#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) -#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) -#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30) +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C) +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40) +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44) +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64) +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) +#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x84) +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88) +#define MXC_CCM_CSR2 (MXC_CCM_BASE + 0x8C) +#define MXC_CCM_CLKSEQ_BYPASS (MXC_CCM_BASE + 0x90) +#define MXC_CCM_CLK_SYS (MXC_CCM_BASE + 0x94) +#define MXC_CCM_CLK_DDR (MXC_CCM_BASE + 0x98) +#define MXC_CCM_ELCDIFPIX (MXC_CCM_BASE + 0x9C) +#define MXC_CCM_EPDCPIX (MXC_CCM_BASE + 0xA0) +#define MXC_CCM_DISPLAY_AXI (MXC_CCM_BASE + 0xA4) +#define MXC_CCM_EPDC_AXI (MXC_CCM_BASE + 0xA8) +#define MXC_CCM_GPMI (MXC_CCM_BASE + 0xAC) +#define MXC_CCM_BCH (MXC_CCM_BASE + 0xB0) +#define MXC_CCM_MSHC_XMSCKI (MXC_CCM_BASE + 0xB4) + +/* CCM Register Offsets. */ +#define MXC_CCM_CDCR_OFFSET 0x4C +#define MXC_CCM_CACRR_OFFSET 0x10 +#define MXC_CCM_CDHIPR_OFFSET 0x48 /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (1 << 12) @@ -119,82 +181,103 @@ #define MXC_CCM_CCR_OSCNT_MASK (0xFF) /* Define the bits in register CCDR */ +/* MX51 */ #define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) #define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) +/* MX53 */ +#define MXC_CCM_CCDR_IPU_HS_MX53_MASK (0x1 << 21) +#define MXC_CCM_CCDR_EMI_HS_INT2_MASK (0x1 << 20) +#define MXC_CCM_CCDR_EMI_HS_INT1_MASK (0x1 << 19) +#define MXC_CCM_CCDR_EMI_HS_SLOW_MASK (0x1 << 18) +#define MXC_CCM_CCDR_EMI_HS_FAST_MASK (0x1 << 17) +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) /* Define the bits in register CSR */ #define MXC_CCM_CSR_COSR_READY (1 << 5) -#define MXC_CCM_CSR_LVS_VALUE (1 << 4) +#define MXC_CCM_CSR_LVS_VALUE (1 << 4) #define MXC_CCM_CSR_CAMP2_READY (1 << 3) #define MXC_CCM_CSR_CAMP1_READY (1 << 2) #define MXC_CCM_CSR_FPM_READY (1 << 1) -#define MXC_CCM_CSR_REF_EN_B (1 << 0) +#define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) /* Define the bits in register CCSR */ -#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) -#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) -#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_PLL3_PFD_EN (0x1 << 13) +#define MXC_CCM_CCSR_PLL2_PFD_EN (0x1 << 12) +#define MXC_CCM_CCSR_PLL1_PFD_EN (0x1 << 11) +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10) +#define MXC_CCM_CCSR_LP_APM_SE_MX51L (0x1 << 9) +#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (1 << 9) +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) #define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 #define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ #define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 #define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 #define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) -#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) #define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) -#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, 1: step_clk */ -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) /* Define the bits in register CACRR */ #define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) -#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) /* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MX50_CCM_CBCDR_WEIM_CLK_SEL (0x1 << 27) +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET (25) +#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x3 << 25) #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) -#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) #define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) #define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MX50_CCM_CBCDR_WEIM_PODF_OFFSET (22) +#define MX50_CCM_CBCDR_WEIM_PODF_MASK (0x7 << 22) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) -#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) #define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) -#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) #define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) #define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) #define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) /* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) +#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_OFFSET (2) +#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) /* Define the bits in register CSCMR1 */ #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) @@ -203,96 +286,128 @@ #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51 (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 19) #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) -#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (21) +#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21) +#define MX50_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20) +#define MX50_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19) +#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16) +#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK (0x7 << 16) +#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) /* Define the bits in register CSCMR2 */ #define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) #define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) -#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) -#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) -#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) +/* MX51 */ #define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) -#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) +/* MX53 */ +#define MXC_CCM_CSCMR2_ASRC_CLK_SEL (1<<21) +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19) +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) +#define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET (16) +#define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK (0x7 << 16) +#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) +/* MX51 */ #define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) -#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) #define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) -#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) +/* MX53 */ +#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (0x1 << 11) +#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (0x1 << 10) +#define MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL (0x1 << 9) +#define MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL (0x1 << 8) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 6) #define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) #define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) -#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) #define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) /* Define the bits in register CSCDR1 */ #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK (0x7 << 11) #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) /* Define the bits in register CS1CDR and CS2CDR */ -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25) +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x7 << 9) #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) @@ -300,50 +415,74 @@ /* Define the bits in register CDCDR */ #define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) -#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) +/* MX51 */ +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) +/* MX53 */ +#define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET (16) +#define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK (0x7 << 16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) -#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) -#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) #define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) -#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) /* Define the bits in register CHSCCDR */ +/* MX51 */ #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) -#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) +/* MX53 */ +#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET (6) +#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK (0x3 << 6) +#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET (4) +#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK (0x3 << 4) +#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET (2) +#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK (0x3 << 2) +#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET (0) +#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK (0x3) /* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET (28) +#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK (0x7 << 28) #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +/* MX51 */ #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) +/* MX53 */ +#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK (0x3F) /* Define the bits in register CSCDR3 */ -#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) #define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) #define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) @@ -352,13 +491,13 @@ /* Define the bits in register CSCDR4 */ #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) #define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) /* Define the bits in register CDHIPR */ #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) @@ -373,58 +512,92 @@ #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) /* Define the bits in register CDCR */ -#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) -#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) +#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ_STATUS (0x1 << 7) +#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ (0x1 << 6) +#define MX50_CCM_CDCR_SW_DVFS_EN (0x1 << 5) +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) /* Define the bits in register CLPCR */ +/* MX51 */ #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) -#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) -#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) -#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX51 (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51 (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51 (0x1 << 20) +/* MX53 */ +#define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS (0x1 << 27) +#define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS (0x1 << 27) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX53 (0x1 << 26) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24) +#define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS (0x1 << 23) +#define MX50_CCM_CLPCR_BYPASS_RNGB_LPM_HS (0x1 << 23) +#define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS (0x1 << 20) #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) -#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) -#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) -#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) -#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) -#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) -#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) -#define MXC_CCM_CLPCR_LPM_OFFSET (0) +#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (0x1 << 2) +#define MXC_CCM_CLPCR_LPM_OFFSET (0) #define MXC_CCM_CLPCR_LPM_MASK (0x3) /* Define the bits in register CISR */ -#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) -#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CISR_ARM_PODF_LOADED_MX51 (0x1 << 25) +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26) +#define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25) +#define MXC_CCM_CISR_EMI_CLK_SEL_LOADED (0x1 << 23) +#define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22) +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) #define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) -#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) #define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) #define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) -#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) #define MXC_CCM_CISR_COSC_READY (0x1 << 6) -#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) #define MXC_CCM_CISR_CKIH_READY (0x1 << 4) +#define MX50_CCM_CISR_CAMP1_READY (0x1 << 4) #define MXC_CCM_CISR_FPM_READY (0x1 << 3) -#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) -#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) -#define MXC_CCM_CISR_LRF_PLL1 (0x1) +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (0x1) /* Define the bits in register CIMR */ -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX51 (0x1 << 25) +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED_MX51 (0x1 << 20) +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED_MX51 (0x1 << 19) +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26) +#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25) +#define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED (0x1 << 23) +#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22) #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) -#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) -#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED_MX53 (0x1 << 20) +#define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED_MX53 (0x1 << 19) +#define MX50_CCM_CIMR_MASK_WEIM_PODF_LOADED (0x1 << 19) #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) -#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) +/* MX51 */ +#define MXC_CCM_CIMR_MASK_COSC_READY_MX51 (0x1 << 5) #define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) #define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) +/* MX53/MX50 */ +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6) +#define MXC_CCM_CIMR_MASK_CAMP2_READY (0x1 << 5) +#define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_LRF_PLL4 (0x1 << 3) #define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) #define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) #define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) @@ -442,11 +615,20 @@ #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) /* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL (0x1 << 24) +#define MXC_CCM_CGPR_ARM_ASYNC_REF_EN (0x1 << 23) #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) #define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) +#define MX50_CCM_CCOSR_CKO1_SLOW_SEL (0x1 << 8) +#define MX50_CCM_CCOSR_CKO1_EN (0x1 << 7) +#define MX50_CCM_CCOSR_CKO1_DIV_OFFSET (4) +#define MX50_CCM_CCOSR_CKO1_DIV_MASK (0x7 << 4) +#define MX50_CCM_CCOSR_CKO1_SEL_OFFSET (0) +#define MX50_CCM_CCOSR_CKO1_SEL_MASK (0xF) + /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGRx_CG_MASK 0x3 #define MXC_CCM_CCGRx_MOD_OFF 0x0 @@ -485,30 +667,120 @@ #define MXC_CCM_CCGRx_CG1_OFFSET 2 #define MXC_CCM_CCGRx_CG0_OFFSET 0 -#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) -#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) -#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) -#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) -#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) -#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) -#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) -#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) -#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) -#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) -#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) -#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) -#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) +#define MXC_CCM_CCGR5_CG6_1_OFFSET 12 +#define MXC_CCM_CCGR5_CG6_2_OFFSET 13 + +/* Define the bits in registers CSR2 */ +#define MXC_CCM_CSR2_ELCDIF_PIX_BUSY (0x1 << 9) +#define MXC_CCM_CSR2_EPDC_PIX_BUSY (0x1 << 8) +#define MXC_CCM_CSR2_EPDC_AXI_BUSY (0x1 << 4) +#define MXC_CCM_CSR2_DISPLAY_AXI_BUSY (0x1 << 3) + +/* Define the bits in registers CLKSEQ_BYPASS */ +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_OFFSET 14 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_OFFSET 12 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_OFFSET 6 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_OFFSET 8 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_OFFSET 4 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_OFFSET 2 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK (0x3 << 2) + +/* Define the bits in registers CLK_SYS */ +#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET (30) +#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET (28) +#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK (0x3 << 28) +#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET (6) +#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK (0xF << 6) +#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET (0) +#define MXC_CCM_CLK_SYS_DIV_PLL_MASK (0x3F) + +/* Define the bits in registers CLK_DDR */ +#define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET (30) +#define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_CLK_DDR_DDR_PFD_SEL (1 << 6) +#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET (0) +#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK (0x3F) + +/* Define the bits in register DISPLAY_AXI */ +#define MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET (30) +#define MXC_CCM_DISPLAY_AXI_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_DISPLAY_AXI_PXP_ASM_EN (1 << 13) +#define MXC_CCM_DISPLAY_AXI_PXP_ASM_DIV_MASK (0x7 << 10) +#define MXC_CCM_DISPLAY_AXI_PXP_ASM_DIV_OFFSET 10 +#define MXC_CCM_DISPLAY_AXI_DIV_OFFSET (0) +#define MXC_CCM_DISPLAY_AXI_DIV_MASK (0x3F) + +/* Define the bits in register EPDC_AXI */ +#define MXC_CCM_EPDC_AXI_CLKGATE_OFFSET (30) +#define MXC_CCM_EPDC_AXI_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_EPDC_AXI_ASM_EN (1 << 9) +#define MXC_CCM_EPDC_AXI_ASM_DIV_OFFSET (6) +#define MXC_CCM_EPDC_AXI_ASM_DIV_MASK (0x7 << 6) +#define MXC_CCM_EPDC_AXI_DIV_OFFSET (0) +#define MXC_CCM_EPDC_AXI_DIV_MASK (0x3F) + +/* Define the bits in register EPDCPIX */ +#define MXC_CCM_EPDC_PIX_CLKGATE_OFFSET (30) +#define MXC_CCM_EPDC_PIX_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_EPDC_PIX_CLK_PRED_OFFSET (12) +#define MXC_CCM_EPDC_PIX_CLK_PRED_MASK (0x3 << 12) +#define MXC_CCM_EPDC_PIX_CLK_PODF_OFFSET (0) +#define MXC_CCM_EPDC_PIX_CLK_PODF_MASK (0xFFF) + +/* Define the bits in register ELCDIFPIX */ +#define MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET (30) +#define MXC_CCM_ELCDIFPIX_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET (12) +#define MXC_CCM_ELCDIFPIX_CLK_PRED_MASK (0x3 << 12) +#define MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET (0) +#define MXC_CCM_ELCDIFPIX_CLK_PODF_MASK (0xFFF) + + +/* Define the bits in register GPMI */ +#define MXC_CCM_GPMI_CLKGATE_OFFSET (30) +#define MXC_CCM_GPMI_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_GPMI_CLK_DIV_OFFSET (0) +#define MXC_CCM_GPMI_CLK_DIV_MASK (0x3F) + +/* Define the bits in register BCH */ +#define MXC_CCM_BCH_CLKGATE_OFFSET (30) +#define MXC_CCM_BCH_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_BCH_CLK_DIV_OFFSET (0) +#define MXC_CCM_BCH_CLK_DIV_MASK (0x3F) + +#define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR)) +#define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80) +#define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100) +#define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180) +#define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4) +#define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220) +#define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240) +#define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260) +#define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280) +#define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0) +#define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300) /* CORTEXA8 platform */ -#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) -#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) -#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) -#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) -#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) -#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) -#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) -#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) -#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) +extern void __iomem *arm_plat_base; +#define MXC_CORTEXA8_BASE (arm_plat_base) +#define MXC_CORTEXA8_PLAT_PVID (arm_plat_base + 0x0) +#define MXC_CORTEXA8_PLAT_GPC (arm_plat_base + 0x4) +#define MXC_CORTEXA8_PLAT_PIC (arm_plat_base + 0x8) +#define MXC_CORTEXA8_PLAT_LPC (arm_plat_base + 0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (arm_plat_base + 0x10) +#define MXC_CORTEXA8_PLAT_ICGC (arm_plat_base + 0x14) +#define MXC_CORTEXA8_PLAT_AMC (arm_plat_base + 0x18) +#define MXC_CORTEXA8_PLAT_NMC (arm_plat_base + 0x20) +#define MXC_CORTEXA8_PLAT_NMS (arm_plat_base + 0x24) /* DVFS CORE */ #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) @@ -529,14 +801,23 @@ #define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) +/* DVFS PER */ +#define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE) +#define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04) +#define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08) +#define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C) +#define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10) +#define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14) +#define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18) +#define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C) + /* GPC */ -#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) -#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) -#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) -#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) -#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) -#define MXC_GPC_PGR_ARMPG_OFFSET 8 -#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) +#define MXC_GPC_CNTR_OFFSET 0x0 +#define MXC_GPC_PGR_OFFSET 0x4 +#define MXC_GPC_VCR_OFFSET 0x8 /* PGC */ #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h new file mode 100644 index 000000000000..8235b8c6729b --- /dev/null +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst; +#define imx51_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) + +extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst; +#define imx51_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) + +extern const struct imx_spi_imx_data imx51_cspi_data __initconst; +#define imx51_add_cspi(pdata) \ + imx_add_spi_imx(&imx51_cspi_data, pdata) + +extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; +#define imx51_add_ecspi(id, pdata) \ + imx_add_spi_imx(&imx51_ecspi_data[id], pdata) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 7130449aacdc..68c021c28064 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -1,7 +1,8 @@ /* - * Copyright 2009 Amit Kucheria - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * + * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: @@ -10,140 +11,1279 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dma-apbh.h" + +/* Flag used to indicate when IRAM has been initialized */ +int iram_ready; +/* Flag used to indicate if dvfs_core is active. */ +int dvfs_core_is_active; + +static struct resource sdma_resources[] = { + { + .start = SDMA_BASE_ADDR, + .end = SDMA_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SDMA, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_dma_device = { + .name = "mxc_sdma", + .id = -1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(sdma_resources), + .resource = sdma_resources, +}; + +static struct resource mxc_w1_master_resources[] = { + { + .start = OWIRE_BASE_ADDR, + .end = OWIRE_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_OWIRE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_w1_master_device = { + .name = "mxc_w1", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_w1_master_resources), + .resource = mxc_w1_master_resources, +}; + +static struct resource mxc_kpp_resources[] = { + { + .start = KPP_BASE_ADDR, + .end = KPP_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_KPP, + .end = MXC_INT_KPP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_keypad_device = { + .name = "mxc_keypad", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_kpp_resources), + .resource = mxc_kpp_resources, +}; + +struct platform_device mxc_powerkey_device = { + .name = "mxcpwrkey", + .id = 0, +}; +static struct resource rtc_resources[] = { + { + .start = SRTC_BASE_ADDR, + .end = SRTC_BASE_ADDR + 0x40, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SRTC_NTZ, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_rtc_device = { + .name = "mxc_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +static struct resource mxc_nand_resources[] = { + { + .flags = IORESOURCE_MEM, + .name = "NFC_AXI_BASE", + .start = MX51_NFC_BASE_ADDR_AXI, + .end = MX51_NFC_BASE_ADDR_AXI + SZ_8K - 1, + }, + { + .flags = IORESOURCE_MEM, + .name = "NFC_IP_BASE", + .start = NFC_BASE_ADDR + 0x00, + .end = NFC_BASE_ADDR + 0x34 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_NFC, + .end = MXC_INT_NFC, + }, +}; + +struct platform_device mxc_nandv2_mtd_device = { + .name = "mxc_nandv2_flash", + .id = 0, + .resource = mxc_nand_resources, + .num_resources = ARRAY_SIZE(mxc_nand_resources), +}; + +static struct resource gpmi_nfc_resources[] = { + { + .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = GPMI_BASE_ADDR, + .end = GPMI_BASE_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_RAWNAND_GPMI, + .end = MXC_INT_RAWNAND_GPMI, + }, + { + .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = BCH_BASE_ADDR, + .end = BCH_BASE_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_RAWNAND_BCH, + .end = MXC_INT_RAWNAND_BCH, + }, + { + .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + }, + { + .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_APBHDMA_CHAN0, + .end = MXC_INT_APBHDMA_CHAN7, + }, +}; + +struct platform_device gpmi_nfc_device = { + .name = GPMI_NFC_DRIVER_NAME, + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = gpmi_nfc_resources, + .num_resources = ARRAY_SIZE(gpmi_nfc_resources), +}; + +static struct resource imx_nfc_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = MX51_NFC_BASE_ADDR_AXI, + .end = MX51_NFC_BASE_ADDR_AXI + 0x1200 - 1, + .name = IMX_NFC_BUFFERS_ADDR_RES_NAME, + }, + { + .flags = IORESOURCE_MEM, + .start = MX51_NFC_BASE_ADDR_AXI + 0x1E00, + .end = MX51_NFC_BASE_ADDR_AXI + 0x1E44 - 1, + .name = IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME, + }, + { + .flags = IORESOURCE_MEM, + .start = NFC_BASE_ADDR + 0x00, + .end = NFC_BASE_ADDR + 0x34 - 1, + .name = IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME, + }, + { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_NFC, + .end = MXC_INT_NFC, + .name = IMX_NFC_INTERRUPT_RES_NAME, + }, +}; + +struct platform_device imx_nfc_device = { + .name = IMX_NFC_DRIVER_NAME, + .id = 0, + .resource = imx_nfc_resources, + .num_resources = ARRAY_SIZE(imx_nfc_resources), +}; + +static struct resource wdt_resources[] = { + { + .start = WDOG1_BASE_ADDR, + .end = WDOG1_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_wdt_device = { + .name = "mxc_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static struct resource pwm1_resources[] = { + { + .start = PWM1_BASE_ADDR, + .end = PWM1_BASE_ADDR + 0x14, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_PWM1, + .end = MXC_INT_PWM1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_pwm1_device = { + .name = "mxc_pwm", + .id = 0, + .num_resources = ARRAY_SIZE(pwm1_resources), + .resource = pwm1_resources, +}; + +static struct resource pwm2_resources[] = { + { + .start = PWM2_BASE_ADDR, + .end = PWM2_BASE_ADDR + 0x14, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_PWM2, + .end = MXC_INT_PWM2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_pwm2_device = { + .name = "mxc_pwm", + .id = 1, + .num_resources = ARRAY_SIZE(pwm2_resources), + .resource = pwm2_resources, +}; + +struct platform_device mxc_pwm1_backlight_device = { + .name = "pwm-backlight", + .id = 0, +}; + +struct platform_device mxc_pwm2_backlight_device = { + .name = "pwm-backlight", + .id = 1, +}; + +static struct resource flexcan0_resources[] = { + { + .start = CAN1_BASE_ADDR, + .end = CAN1_BASE_ADDR + 0x3FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_CAN1, + .end = MXC_INT_CAN1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_flexcan0_device = { + .name = "FlexCAN", + .id = 0, + .num_resources = ARRAY_SIZE(flexcan0_resources), + .resource = flexcan0_resources, +}; + +static struct resource flexcan1_resources[] = { + { + .start = CAN2_BASE_ADDR, + .end = CAN2_BASE_ADDR + 0x3FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_CAN2, + .end = MXC_INT_CAN2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_flexcan1_device = { + .name = "FlexCAN", + .id = 1, + .num_resources = ARRAY_SIZE(flexcan1_resources), + .resource = flexcan1_resources, +}; + +static struct resource ipu_resources[] = { + { + .start = MX51_IPU_CTRL_BASE_ADDR, + .end = MX51_IPU_CTRL_BASE_ADDR + SZ_512M, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_IPU_SYN, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_IPU_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_ipu_device = { + .name = "mxc_ipu", + .id = -1, + .num_resources = ARRAY_SIZE(ipu_resources), + .resource = ipu_resources, +}; + +static struct resource epdc_resources[] = { + { + .start = EPDC_BASE_ADDR, + .end = EPDC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_EPDC, + .end = MXC_INT_EPDC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device epdc_device = { + .name = "mxc_epdc_fb", + .id = -1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(epdc_resources), + .resource = epdc_resources, +}; + +static struct resource elcdif_resources[] = { + { + .start = ELCDIF_BASE_ADDR, + .end = ELCDIF_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ELCDIF, + .end = MXC_INT_ELCDIF, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device elcdif_device = { + .name = "mxc_elcdif_fb", + .id = -1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(elcdif_resources), + .resource = elcdif_resources, +}; + +struct platform_device mxc_fb_devices[] = { + { + .name = "mxc_sdc_fb", + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, + { + .name = "mxc_sdc_fb", + .id = 1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, + { + .name = "mxc_sdc_fb", + .id = 2, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, +}; + +static struct resource ldb_resources[] = { + { + .start = IOMUXC_BASE_ADDR, + .end = IOMUXC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_ldb_device = { + .name = "mxc_ldb", + .id = -1, + .num_resources = ARRAY_SIZE(ldb_resources), + .resource = ldb_resources, +}; + +static struct resource vpu_resources[] = { + { + .start = VPU_BASE_ADDR, + .end = VPU_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_VPU, + .end = MXC_INT_VPU, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxcvpu_device = { + .name = "mxc_vpu", + .id = 0, + .num_resources = ARRAY_SIZE(vpu_resources), + .resource = vpu_resources, +}; + +struct platform_device fixed_volt_reg_device = { + .name = "reg-fixed-voltage", + .id = -1, +}; + +static struct resource scc_resources[] = { + { + .start = SCC_BASE_ADDR, + .end = SCC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MX51_SCC_RAM_BASE_ADDR, + .end = MX51_SCC_RAM_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxcscc_device = { + .name = "mxc_scc", + .id = 0, + .num_resources = ARRAY_SIZE(scc_resources), + .resource = scc_resources, +}; + +static struct resource dcp_resources[] = { + + { + .flags = IORESOURCE_MEM, + .start = DCP_BASE_ADDR, + .end = DCP_BASE_ADDR + 0x2000 - 1, + }, { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_DCP_CHAN0, + .end = MXC_INT_DCP_CHAN0, + }, { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_DCP_CHAN1_3, + .end = MXC_INT_DCP_CHAN1_3, + }, +}; + +struct platform_device dcp_device = { + .name = "dcp", + .id = 0, + .num_resources = ARRAY_SIZE(dcp_resources), + .resource = dcp_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + + +static struct resource rngb_resources[] = { + { + .start = RNGB_BASE_ADDR, + .end = RNGB_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_RNGB_BLOCK, + .flags = IORESOURCE_IRQ, + }, +}; + +/* the RNGC driver applies for MX50's RNGB hw */ +struct platform_device mxc_rngb_device = { + .name = "fsl_rngc", + .id = 0, + .num_resources = ARRAY_SIZE(rngb_resources), + .resource = rngb_resources, +}; + +static struct resource mxc_fec_resources[] = { + { + .start = FEC_BASE_ADDR, + .end = FEC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM + }, + { + .start = MXC_INT_FEC, + .end = MXC_INT_FEC, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mxc_fec_device = { + .name = "fec", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_fec_resources), + .resource = mxc_fec_resources, +}; + +static struct resource mxc_ptp_resources[] = { + { + .start = PTP_BASE_ADDR, + .end = PTP_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM + }, + { + .start = RTC_BASE_ADDR, + .end = RTC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM + }, + { + .start = MXC_INT_PTP, + .end = MXC_INT_PTP, + .flags = IORESOURCE_IRQ + }, + { + .start = MXC_INT_RTC, + .end = MXC_INT_RTC, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mxc_ptp_device = { + .name = "ptp", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_ptp_resources), + .resource = mxc_ptp_resources, +}; + +static struct resource mxcspi1_resources[] = { + { + .start = CSPI1_BASE_ADDR, + .end = CSPI1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_CSPI1, + .end = MXC_INT_CSPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxcspi1_device = { + .name = "mxc_spi", + .id = 0, + .num_resources = ARRAY_SIZE(mxcspi1_resources), + .resource = mxcspi1_resources, +}; + +static struct resource mxcspi2_resources[] = { + { + .start = CSPI2_BASE_ADDR, + .end = CSPI2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_CSPI2, + .end = MXC_INT_CSPI2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxcspi2_device = { + .name = "mxc_spi", + .id = 1, + .num_resources = ARRAY_SIZE(mxcspi2_resources), + .resource = mxcspi2_resources, +}; + +static struct resource mxcspi3_resources[] = { + { + .start = CSPI3_BASE_ADDR, + .end = CSPI3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_CSPI, + .end = MXC_INT_CSPI, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxcspi3_device = { + .name = "mxc_spi", + .id = 2, + .num_resources = ARRAY_SIZE(mxcspi3_resources), + .resource = mxcspi3_resources, +}; + +static struct resource mxci2c1_resources[] = { + { + .start = I2C1_BASE_ADDR, + .end = I2C1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_I2C1, + .end = MXC_INT_I2C1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource mxci2c2_resources[] = { + { + .start = I2C2_BASE_ADDR, + .end = I2C2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_I2C2, + .end = MXC_INT_I2C2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource mxci2c3_resources[] = { + { + .start = I2C3_BASE_ADDR, + .end = I2C3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_I2C3, + .end = MXC_INT_I2C3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxci2c_devices[] = { + { + .name = "imx-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(mxci2c1_resources), + .resource = mxci2c1_resources, + }, + { + .name = "imx-i2c", + .id = 1, + .num_resources = ARRAY_SIZE(mxci2c2_resources), + .resource = mxci2c2_resources, + }, + { + .name = "imx-i2c", + .id = 2, + .num_resources = ARRAY_SIZE(mxci2c3_resources), + .resource = mxci2c3_resources, + }, +}; + +static struct resource mxci2c_hs_resources[] = { + { + .start = HSI2C_DMA_BASE_ADDR, + .end = HSI2C_DMA_BASE_ADDR + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_HS_I2C, + .end = MXC_INT_HS_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxci2c_hs_device = { + .name = "mxc_i2c_hs", + .id = 3, + .num_resources = ARRAY_SIZE(mxci2c_hs_resources), + .resource = mxci2c_hs_resources +}; + +static struct resource ssi1_resources[] = { + { + .start = SSI1_BASE_ADDR, + .end = SSI1_BASE_ADDR + 0x5C, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SSI1, + .end = MXC_INT_SSI1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_ssi1_device = { + .name = "mxc_ssi", + .id = 0, + .num_resources = ARRAY_SIZE(ssi1_resources), + .resource = ssi1_resources, +}; + +static struct resource ssi2_resources[] = { + { + .start = SSI2_BASE_ADDR, + .end = SSI2_BASE_ADDR + 0x5C, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SSI2, + .end = MXC_INT_SSI2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_ssi2_device = { + .name = "mxc_ssi", + .id = 1, + .num_resources = ARRAY_SIZE(ssi2_resources), + .resource = ssi2_resources, +}; + +static struct resource ssi3_resources[] = { + { + .start = SSI3_BASE_ADDR, + .end = SSI3_BASE_ADDR + 0x5C, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SSI3, + .end = MXC_INT_SSI3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_ssi3_device = { + .name = "mxc_ssi", + .id = 2, + .num_resources = ARRAY_SIZE(ssi3_resources), + .resource = ssi3_resources, +}; + +static struct resource esai_resources[] = { + { + .start = ESAI_BASE_ADDR, + .end = ESAI_BASE_ADDR + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ESAI, + .end = MXC_INT_ESAI, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_esai_device = { + .name = "mxc_esai", + .id = 0, + .num_resources = ARRAY_SIZE(esai_resources), + .resource = esai_resources, +}; + +static struct resource tve_resources[] = { + { + .start = TVE_BASE_ADDR, + .end = TVE_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_TVE, + .end = MXC_INT_TVE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_tve_device = { + .name = "tve", + .num_resources = ARRAY_SIZE(tve_resources), + .resource = tve_resources, +}; + +static struct resource dvfs_core_resources[] = { + { + .start = DVFSCORE_BASE_ADDR, + .end = DVFSCORE_BASE_ADDR + 4 * SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_GPC1, + .end = MXC_INT_GPC1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_dvfs_core_device = { + .name = "mxc_dvfs_core", + .id = 0, + .num_resources = ARRAY_SIZE(dvfs_core_resources), + .resource = dvfs_core_resources, +}; + +static struct resource dvfs_per_resources[] = { + { + .start = DVFSPER_BASE_ADDR, + .end = DVFSPER_BASE_ADDR + 2 * SZ_16 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_GPC1, + .end = MXC_INT_GPC1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_dvfs_per_device = { + .name = "mxc_dvfsper", + .id = 0, + .num_resources = ARRAY_SIZE(dvfs_per_resources), + .resource = dvfs_per_resources, +}; + +static struct resource asrc_resources[] = { + { + .start = ASRC_BASE_ADDR, + .end = ASRC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ASRC, + .end = MXC_INT_ASRC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_asrc_device = { + .name = "mxc_asrc", + .id = 0, + .num_resources = ARRAY_SIZE(asrc_resources), + .resource = asrc_resources, +}; + +struct mxc_gpio_port mxc_gpio_ports[] = { + { + .chip.label = "gpio-0", + .base = IO_ADDRESS(GPIO1_BASE_ADDR), + .irq = MXC_INT_GPIO1_LOW, + .irq_high = MXC_INT_GPIO1_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + }, + { + .chip.label = "gpio-1", + .base = IO_ADDRESS(GPIO2_BASE_ADDR), + .irq = MXC_INT_GPIO2_LOW, + .irq_high = MXC_INT_GPIO2_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 + }, + { + .chip.label = "gpio-2", + .base = IO_ADDRESS(GPIO3_BASE_ADDR), + .irq = MXC_INT_GPIO3_LOW, + .irq_high = MXC_INT_GPIO3_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 + }, + { + .chip.label = "gpio-3", + .base = IO_ADDRESS(GPIO4_BASE_ADDR), + .irq = MXC_INT_GPIO4_LOW, + .irq_high = MXC_INT_GPIO4_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 + }, + { + .chip.label = "gpio-4", + .base = IO_ADDRESS(GPIO5_BASE_ADDR), + .irq = MXC_INT_GPIO5_LOW, + .irq_high = MXC_INT_GPIO5_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 + }, + { + .chip.label = "gpio-5", + .base = IO_ADDRESS(GPIO6_BASE_ADDR), + .irq = MXC_INT_GPIO6_LOW, + .irq_high = MXC_INT_GPIO6_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5 + }, + { + .chip.label = "gpio-6", + .base = IO_ADDRESS(GPIO7_BASE_ADDR), + .irq = MXC_INT_GPIO7_LOW, + .irq_high = MXC_INT_GPIO7_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6 + }, +}; + +int __init mxc_register_gpios(void) +{ + if (cpu_is_mx51()) + return mxc_gpio_init(mxc_gpio_ports, 4); + else if (cpu_is_mx50()) + return mxc_gpio_init(mxc_gpio_ports, 6); + return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); +} + +static struct resource spdif_resources[] = { + { + .start = SPDIF_BASE_ADDR, + .end = SPDIF_BASE_ADDR + 0x50, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SPDIF_MX51, + .end = MXC_INT_SPDIF_MX51, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_alsa_spdif_device = { + .name = "mxc_alsa_spdif", + .id = 0, + .num_resources = ARRAY_SIZE(spdif_resources), + .resource = spdif_resources, +}; + +struct platform_device mx51_lpmode_device = { + .name = "mx51_lpmode", + .id = 0, +}; + +struct platform_device busfreq_device = { + .name = "busfreq", + .id = 0, +}; + +struct platform_device pm_device = { + .name = "mx5_pm", + .id = 0, +}; + +static struct resource mxc_m4if_resources[] = { + { + .start = M4IF_BASE_ADDR, + .end = M4IF_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device sdram_autogating_device = { + .name = "sdram_autogating", + .id = 0, + .resource = mxc_m4if_resources, + .num_resources = ARRAY_SIZE(mxc_m4if_resources), +}; -static struct resource uart0[] = { +static struct resource mxc_iim_resources[] = { { - .start = MX51_UART1_BASE_ADDR, - .end = MX51_UART1_BASE_ADDR + 0xfff, + .start = IIM_BASE_ADDR, + .end = IIM_BASE_ADDR + SZ_16K - 1, .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_UART1, - .end = MX51_MXC_INT_UART1, + }, + { + .start = MXC_INT_IIM, + .end = MXC_INT_IIM, .flags = IORESOURCE_IRQ, }, }; -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", +struct platform_device mxc_iim_device = { + .name = "mxc_iim", .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), + .num_resources = ARRAY_SIZE(mxc_iim_resources), + .resource = mxc_iim_resources }; -static struct resource uart1[] = { +static struct resource mxc_sim_resources[] = { { - .start = MX51_UART2_BASE_ADDR, - .end = MX51_UART2_BASE_ADDR + 0xfff, + .start = SIM_BASE_ADDR, + .end = SIM_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_UART2, - .end = MX51_MXC_INT_UART2, + }, + { + .start = MXC_INT_SIM_IPB, + .end = MXC_INT_SIM_IPB, + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_SIM_DAT, + .end = MXC_INT_SIM_DAT, .flags = IORESOURCE_IRQ, }, }; -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), +struct platform_device mxc_sim_device = { + .name = "mxc_sim", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_sim_resources), + .resource = mxc_sim_resources, }; -static struct resource uart2[] = { +static struct resource mxcsdhc1_resources[] = { { - .start = MX51_UART3_BASE_ADDR, - .end = MX51_UART3_BASE_ADDR + 0xfff, + .start = MMC_SDHC1_BASE_ADDR, + .end = MMC_SDHC1_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_UART3, - .end = MX51_MXC_INT_UART3, + }, + { + .start = MXC_INT_MMC_SDHC1, + .end = MXC_INT_MMC_SDHC1, + .flags = IORESOURCE_IRQ, + }, + { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource mxcsdhc2_resources[] = { + { + .start = MMC_SDHC2_BASE_ADDR, + .end = MMC_SDHC2_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_MMC_SDHC2, + .end = MXC_INT_MMC_SDHC2, .flags = IORESOURCE_IRQ, }, + { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource mxcsdhc3_resources[] = { + { + .start = MMC_SDHC3_BASE_ADDR, + .end = MMC_SDHC3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_MMC_SDHC3, + .end = MXC_INT_MMC_SDHC3, + .flags = IORESOURCE_IRQ, + }, + { + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxcsdhc1_device = { + .name = "mxsdhci", + .id = 0, + .num_resources = ARRAY_SIZE(mxcsdhc1_resources), + .resource = mxcsdhc1_resources, +}; + +struct platform_device mxcsdhc2_device = { + .name = "mxsdhci", + .id = 1, + .num_resources = ARRAY_SIZE(mxcsdhc2_resources), + .resource = mxcsdhc2_resources, }; -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", +struct platform_device mxcsdhc3_device = { + .name = "mxsdhci", .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), + .num_resources = ARRAY_SIZE(mxcsdhc3_resources), + .resource = mxcsdhc3_resources, }; -static struct resource mxc_fec_resources[] = { +static struct resource pata_fsl_resources[] = { { - .start = MX51_MXC_FEC_BASE_ADDR, - .end = MX51_MXC_FEC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_FEC, - .end = MX51_MXC_INT_FEC, - .flags = IORESOURCE_IRQ, + .start = ATA_BASE_ADDR, + .end = ATA_BASE_ADDR + 0x000000C8, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ, }, }; -struct platform_device mxc_fec_device = { - .name = "fec", +struct platform_device pata_fsl_device = { + .name = "pata_fsl", + .id = -1, + .num_resources = ARRAY_SIZE(pata_fsl_resources), + .resource = pata_fsl_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +/* On-Chip OTP device and resource */ +static struct resource otp_resource = { + .start = OCOTP_CTRL_BASE_ADDR, + .end = OCOTP_CTRL_BASE_ADDR + SZ_8K - 1, + .flags = IORESOURCE_MEM, +}; + +struct platform_device fsl_otp_device = { + .name = "ocotp", + .id = -1, + .resource = &otp_resource, + .num_resources = 1, +}; + +static struct resource ahci_fsl_resources[] = { + { + .start = MX53_SATA_BASE_ADDR, + .end = MX53_SATA_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SATA, + .end = MXC_INT_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ahci_fsl_device = { + .name = "ahci", .id = 0, - .num_resources = ARRAY_SIZE(mxc_fec_resources), - .resource = mxc_fec_resources, + .num_resources = ARRAY_SIZE(ahci_fsl_resources), + .resource = ahci_fsl_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, }; static u64 usb_dma_mask = DMA_BIT_MASK(32); -static struct resource usbotg_resources[] = { +static struct resource usbotg_host_resources[] = { + { + .start = OTG_BASE_ADDR, + .end = OTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource usbotg_udc_resources[] = { + { + .start = OTG_BASE_ADDR, + .end = OTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource usbotg_xcvr_resources[] = { { - .start = MX51_OTG_BASE_ADDR, - .end = MX51_OTG_BASE_ADDR + 0x1ff, + .start = OTG_BASE_ADDR, + .end = OTG_BASE_ADDR + 0x1ff, .flags = IORESOURCE_MEM, }, { - .start = MX51_MXC_INT_USB_OTG, + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource usbotg_wakeup_resources[] = { + { + .start = MXC_INT_USB_OTG,/* wakeup irq */ + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_USB_OTG,/* usb core irq , may be equel to wakeup irq for some imx chips */ .flags = IORESOURCE_IRQ, }, }; -/* OTG gadget device */ struct platform_device mxc_usbdr_udc_device = { .name = "fsl-usb2-udc", .id = -1, - .num_resources = ARRAY_SIZE(usbotg_resources), - .resource = usbotg_resources, + .dev = { + .dma_mask = &usb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = usbotg_udc_resources, + .num_resources = ARRAY_SIZE(usbotg_udc_resources), +}; + +struct platform_device mxc_usbdr_otg_device = { + .name = "fsl-usb2-otg", + .id = -1, .dev = { .dma_mask = &usb_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, + .resource = usbotg_xcvr_resources, + .num_resources = ARRAY_SIZE(usbotg_xcvr_resources), }; struct platform_device mxc_usbdr_host_device = { - .name = "mxc-ehci", + .name = "fsl-ehci", .id = 0, - .num_resources = ARRAY_SIZE(usbotg_resources), - .resource = usbotg_resources, + .num_resources = ARRAY_SIZE(usbotg_host_resources), + .resource = usbotg_host_resources, .dev = { .dma_mask = &usb_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; +struct platform_device mxc_usbdr_wakeup_device = { + .name = "usb_wakeup", + .id = 0, + .num_resources = ARRAY_SIZE(usbotg_wakeup_resources), + .resource = usbotg_wakeup_resources, +}; + static struct resource usbh1_resources[] = { { - .start = MX51_OTG_BASE_ADDR + 0x200, - .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff, + .start = OTG_BASE_ADDR + 0x200, + .end = OTG_BASE_ADDR + 0x200 + 0x1ff, .flags = IORESOURCE_MEM, }, { - .start = MX51_MXC_INT_USB_H1, + .start = MXC_INT_USB_H1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource usbh1_wakeup_resources[] = { + { + .start = MXC_INT_USB_H1, /*wakeup irq*/ .flags = IORESOURCE_IRQ, }, + { + .start = MXC_INT_USB_H1, + .flags = IORESOURCE_IRQ,/* usb core irq */ + }, }; struct platform_device mxc_usbh1_device = { - .name = "mxc-ehci", + .name = "fsl-ehci", .id = 1, .num_resources = ARRAY_SIZE(usbh1_resources), .resource = usbh1_resources, @@ -153,49 +1293,607 @@ struct platform_device mxc_usbh1_device = { }, }; -static struct resource mxc_wdt_resources[] = { +struct platform_device mxc_usbh1_wakeup_device = { + .name = "usb_wakeup", + .id = 1, + .num_resources = ARRAY_SIZE(usbh1_wakeup_resources), + .resource = usbh1_wakeup_resources, +}; + +static struct resource usbh2_resources[] = { + { + .start = OTG_BASE_ADDR + 0x400, + .end = OTG_BASE_ADDR + 0x400 + 0x1ff, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_USB_H2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource usbh2_wakeup_resources[] = { + { + .start = MXC_INT_USB_H2, + .flags = IORESOURCE_IRQ,/* wakeup irq */ + }, + { + .start = MXC_INT_USB_H2, + .flags = IORESOURCE_IRQ,/* usb core irq */ + }, +}; +struct platform_device mxc_usbh2_device = { + .name = "fsl-ehci", + .id = 2, + .num_resources = ARRAY_SIZE(usbh2_resources), + .resource = usbh2_resources, + .dev = { + .dma_mask = &usb_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device mxc_usbh2_wakeup_device = { + .name = "usb_wakeup", + .id = 2, + .num_resources = ARRAY_SIZE(usbh2_wakeup_resources), + .resource = usbh2_wakeup_resources, +}; + +static struct resource mxc_gpu_resources[] = { + { + .start = MXC_INT_GPU2_IRQ, + .end = MXC_INT_GPU2_IRQ, + .name = "gpu_2d_irq", + .flags = IORESOURCE_IRQ, + }, + { + .start = MXC_INT_GPU, + .end = MXC_INT_GPU, + .name = "gpu_3d_irq", + .flags = IORESOURCE_IRQ, + }, + { + .start = MX51_GPU2D_BASE_ADDR, + .end = MX51_GPU2D_BASE_ADDR + SZ_4K - 1, + .name = "gpu_2d_registers", + .flags = IORESOURCE_MEM, + }, + { + .start = GPU_BASE_ADDR, + .end = GPU_BASE_ADDR + SZ_128K - 1, + .name = "gpu_3d_registers", + .flags = IORESOURCE_MEM, + }, + { + .start = MX51_GPU_GMEM_BASE_ADDR, + .end = MX51_GPU_GMEM_BASE_ADDR + SZ_128K - 1, + .name = "gpu_graphics_mem", + .flags = IORESOURCE_MEM, + }, { - .start = MX51_WDOG_BASE_ADDR, - .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1, + .start = 0, + .end = 0, + .name = "gpu_reserved_mem", .flags = IORESOURCE_MEM, }, }; -struct platform_device mxc_wdt = { - .name = "imx2-wdt", +struct platform_device gpu_device = { + .name = "mxc_gpu", .id = 0, - .num_resources = ARRAY_SIZE(mxc_wdt_resources), - .resource = mxc_wdt_resources, + .num_resources = ARRAY_SIZE(mxc_gpu_resources), + .resource = mxc_gpu_resources, }; -static struct mxc_gpio_port mxc_gpio_ports[] = { +int z160_revision; + +static struct resource mxc_gpu2d_resources[] = { { - .chip.label = "gpio-0", - .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR), - .irq = MX51_MXC_INT_GPIO1_LOW, - .virtual_irq_start = MXC_GPIO_IRQ_START + .start = MX51_GPU2D_BASE_ADDR, + .end = MX51_GPU2D_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .chip.label = "gpio-1", - .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR), - .irq = MX51_MXC_INT_GPIO2_LOW, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 + .flags = IORESOURCE_MEM, }, { - .chip.label = "gpio-2", - .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR), - .irq = MX51_MXC_INT_GPIO3_LOW, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 + .flags = IORESOURCE_MEM, }, +}; + +static struct resource mlb_resources[] = { + [0] = { + .start = MLB_BASE_ADDR, + .end = MLB_BASE_ADDR + 0x300, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MLB, + .end = MXC_INT_MLB, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_mlb_device = { + .name = "mxc_mlb", + .id = 0, + .num_resources = ARRAY_SIZE(mlb_resources), + .resource = mlb_resources, +}; + +static struct resource pxp_resources[] = { { - .chip.label = "gpio-3", - .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR), - .irq = MX51_MXC_INT_GPIO4_LOW, - .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 + .start = EPXP_BASE_ADDR, + .end = EPXP_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_EPXP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_pxp_device = { + .name = "mxc-pxp", + .id = -1, + .num_resources = ARRAY_SIZE(pxp_resources), + .resource = pxp_resources, +}; + +struct platform_device mxc_pxp_client_device = { + .name = "pxp-device", + .id = -1, +}; + +static u64 pxp_dma_mask = DMA_BIT_MASK(32); +struct platform_device mxc_pxp_v4l2 = { + .name = "pxp-v4l2", + .id = -1, + .dev = { + .dma_mask = &pxp_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; -int __init mxc_register_gpios(void) +struct platform_device mxc_v4l2_device = { + .name = "mxc_v4l2_capture", + .id = 0, +}; + +struct platform_device mxc_v4l2out_device = { + .name = "mxc_v4l2_output", + .id = 0, +}; + +struct resource viim_resources[] = { + [0] = { + .start = (GPT1_BASE_ADDR - 0x20000000), + .end = (GPT1_BASE_ADDR - 0x20000000) + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OCOTP_CTRL_BASE_ADDR, + .end = OCOTP_CTRL_BASE_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +struct platform_device mxs_viim = { + .name = "mxs_viim", + .id = -1, + .num_resources = ARRAY_SIZE(viim_resources), + .resource = viim_resources, +}; + +static struct resource mx5_perfmon_res[] = { + { + .flags = IORESOURCE_MEM, + .start = PERFMON_BASE_ADDR, + .end = PERFMON_BASE_ADDR + 0x1000 - 1, + }, +}; + +struct platform_device mxc_perfmon = { + .name = "mxs-perfmon", + .resource = mx5_perfmon_res, + .num_resources = ARRAY_SIZE(mx5_perfmon_res), + .id = 0 +}; + +static struct mxs_perfmon_bit_config +mx50_perfmon_bit_config[] = { + {.field = (1 << 0), .name = "MID0-CORE" }, + {.field = (1 << 1), .name = "MID1-DCP" }, + {.field = (1 << 2), .name = "MID2-PXP" }, + {.field = (1 << 3), .name = "MID3-USB" }, + {.field = (1 << 4), .name = "MID4-GPU2D" }, + {.field = (1 << 5), .name = "MID5-BCH" }, + {.field = (1 << 6), .name = "MID6-AHB" }, + {.field = (1 << 7), .name = "MID7-EPDC" }, + {.field = (1 << 8), .name = "MID8-LCDIF" }, + {.field = (1 << 9), .name = "MID9-SDMA" }, + {.field = (1 << 10), .name = "MID10-FEC" }, + {.field = (1 << 11), .name = "MID11-MSHC" } +}; + +struct mxs_platform_perfmon_data mxc_perfmon_data = { + .bit_config_tab = mx50_perfmon_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx50_perfmon_bit_config), +}; + +static struct resource dma_apbh_resources[] = { + { + .start = APBHDMA_BASE_ADDR, + .end = APBHDMA_BASE_ADDR + 0x2000 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxs_dma_apbh_device = { + .name = "mxs-dma-apbh", + .num_resources = ARRAY_SIZE(dma_apbh_resources), + .resource = dma_apbh_resources, +}; + +struct platform_device mxc_zq_calib_device = { + .name = "mxc_zq_calib", + .id = -1, +}; + +void __init mx5_init_irq(void) { - return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); + unsigned long tzic_addr; + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) + tzic_addr = MX51_TZIC_BASE_ADDR_T01; + else if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) + tzic_addr = MX51_TZIC_BASE_ADDR; + else /* mx53 and mx50 */ + tzic_addr = MX53_TZIC_BASE_ADDR; + + mxc_tzic_init_irq(tzic_addr); +} + +#define SCM_RD_DELAY 1000000 /* in nanoseconds */ +#define SEC_TO_NANOSEC 1000000000 /*Second to nanoseconds */ +static __init void mxc_init_scc_iram(void) +{ + uint32_t reg_value; + uint32_t reg_mask = 0; + uint8_t *UMID_base; + uint32_t *MAP_base; + uint8_t i; + uint32_t partition_no; + uint32_t scc_partno; + void *scm_ram_base; + void *scc_base; + uint32_t ram_partitions, ram_partition_size, ram_size; + uint32_t scm_version_register; + struct timespec stime; + struct timespec curtime; + long scm_rd_timeout = 0; + long cur_ns = 0; + long start_ns = 0; + + scc_base = ioremap((uint32_t) scc_resources[0].start, 0x140); + if (scc_base == NULL) { + printk(KERN_ERR "FAILED TO MAP SCC REGS\n"); + return; + } + + scm_version_register = __raw_readl(scc_base + SCM_VERSION_REG); + ram_partitions = 1 + ((scm_version_register & SCM_VER_NP_MASK) + >> SCM_VER_NP_SHIFT); + ram_partition_size = (uint32_t) (1 << + ((scm_version_register & SCM_VER_BPP_MASK) + >> SCM_VER_BPP_SHIFT)); + + ram_size = (uint32_t)(ram_partitions * ram_partition_size); + + scm_ram_base = ioremap((uint32_t) scc_resources[1].start, ram_size); + + if (scm_ram_base == NULL) { + printk(KERN_ERR "FAILED TO MAP SCC RAM\n"); + return; + } + + /* Wait for any running SCC operations to finish or fail */ + getnstimeofday(&stime); + do { + reg_value = __raw_readl(scc_base + SCM_STATUS_REG); + getnstimeofday(&curtime); + if (curtime.tv_nsec > stime.tv_nsec) + scm_rd_timeout = curtime.tv_nsec - stime.tv_nsec; + else{ + /*Converted second to nanosecond and add to + nsec when current nanosec is less than + start time nanosec.*/ + cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) + + curtime.tv_nsec; + start_ns = (stime.tv_sec * SEC_TO_NANOSEC) + + stime.tv_nsec; + scm_rd_timeout = cur_ns - start_ns; + } + } while (((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) + && ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_FAIL)); + + /* Check for failures */ + if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) { + /* Special message for bad secret key fuses */ + if (reg_value & SCM_STATUS_KST_BAD_KEY) + printk(KERN_ERR "INVALID SCC KEY FUSE PATTERN\n"); + else + printk(KERN_ERR "SECURE RAM FAILURE\n"); + + iounmap(scm_ram_base); + iounmap(scc_base); + return; + } + + scm_rd_timeout = 0; + + /* Release all partitions for SCC2 driver on MX53*/ + if (cpu_is_mx53()) + scc_partno = 0; + /* Release final two partitions for SCC2 driver on MX51 */ + else + scc_partno = ram_partitions - + (SCC_RAM_SIZE / ram_partition_size); + + for (partition_no = scc_partno; partition_no < ram_partitions; + partition_no++) { + reg_value = (((partition_no << SCM_ZCMD_PART_SHIFT) & + SCM_ZCMD_PART_MASK) | ((0x03 << SCM_ZCMD_CCMD_SHIFT) & + SCM_ZCMD_CCMD_MASK)); + __raw_writel(reg_value, scc_base + SCM_ZCMD_REG); + udelay(1); + /* Wait for zeroization to complete */ + getnstimeofday(&stime); + do { + reg_value = __raw_readl(scc_base + SCM_STATUS_REG); + getnstimeofday(&curtime); + if (curtime.tv_nsec > stime.tv_nsec) + scm_rd_timeout = curtime.tv_nsec - + stime.tv_nsec; + else { + /*Converted second to nanosecond and add to + nsec when current nanosec is less than + start time nanosec.*/ + cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) + + curtime.tv_nsec; + start_ns = (stime.tv_sec * SEC_TO_NANOSEC) + + stime.tv_nsec; + scm_rd_timeout = cur_ns - start_ns; + } + } while (((reg_value & SCM_STATUS_SRS_MASK) != + SCM_STATUS_SRS_READY) && ((reg_value & SCM_STATUS_SRS_MASK) != + SCM_STATUS_SRS_FAIL) && (scm_rd_timeout <= SCM_RD_DELAY)); + + if (scm_rd_timeout > SCM_RD_DELAY) + printk(KERN_ERR "SCM Status Register Read timeout" + "for Partition No:%d", partition_no); + + if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) + break; + } + + /* 4 partitions on MX53 */ + if (cpu_is_mx53()) + reg_mask = 0xFF; + + /*Check all expected partitions released */ + reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG); + if ((reg_value & reg_mask) != 0) { + printk(KERN_ERR "FAILED TO RELEASE IRAM PARTITION\n"); + iounmap(scm_ram_base); + iounmap(scc_base); + return; + } + + /* we are done if this is MX53, since no sharing of IRAM and SCC_RAM */ + if (cpu_is_mx53()) + goto exit; + + reg_mask = 0; + scm_rd_timeout = 0; + /* Allocate remaining partitions for general use */ + for (partition_no = 0; partition_no < scc_partno; partition_no++) { + /* Supervisor mode claims a partition for it's own use + by writing zero to SMID register.*/ + __raw_writel(0, scc_base + (SCM_SMID0_REG + 8 * partition_no)); + + /* Wait for any zeroization to complete */ + getnstimeofday(&stime); + do { + reg_value = __raw_readl(scc_base + SCM_STATUS_REG); + getnstimeofday(&curtime); + if (curtime.tv_nsec > stime.tv_nsec) + scm_rd_timeout = curtime.tv_nsec - + stime.tv_nsec; + else{ + /*Converted second to nanosecond and add to + nsec when current nanosec is less than + start time nanosec.*/ + cur_ns = (curtime.tv_sec * SEC_TO_NANOSEC) + + curtime.tv_nsec; + start_ns = (stime.tv_sec * SEC_TO_NANOSEC) + + stime.tv_nsec; + scm_rd_timeout = cur_ns - start_ns; + } + } while (((reg_value & SCM_STATUS_SRS_MASK) != + SCM_STATUS_SRS_READY) && ((reg_value & SCM_STATUS_SRS_MASK) != + SCM_STATUS_SRS_FAIL) && (scm_rd_timeout <= SCM_RD_DELAY)); + + if (scm_rd_timeout > SCM_RD_DELAY) + printk(KERN_ERR "SCM Status Register Read timeout" + "for Partition No:%d", partition_no); + + if ((reg_value & SCM_STATUS_SRS_MASK) != SCM_STATUS_SRS_READY) + break; + /* Set UMID=0 and permissions for universal data + read/write access */ + MAP_base = scm_ram_base + + (uint32_t) (partition_no * ram_partition_size); + UMID_base = (uint8_t *) MAP_base + 0x10; + for (i = 0; i < 16; i++) + UMID_base[i] = 0; + + MAP_base[0] = (SCM_PERM_NO_ZEROIZE | SCM_PERM_HD_SUP_DISABLE | + SCM_PERM_HD_READ | SCM_PERM_HD_WRITE | + SCM_PERM_HD_EXECUTE | SCM_PERM_TH_READ | + SCM_PERM_TH_WRITE); + reg_mask |= (3 << (2 * (partition_no))); + } + + /* Check all expected partitions allocated */ + reg_value = __raw_readl(scc_base + SCM_PART_OWNERS_REG); + if ((reg_value & reg_mask) != reg_mask) { + printk(KERN_ERR "FAILED TO ACQUIRE IRAM PARTITION\n"); + iounmap(scm_ram_base); + iounmap(scc_base); + return; + } + +exit: + iounmap(scm_ram_base); + iounmap(scc_base); + printk(KERN_INFO "IRAM READY\n"); + iram_ready = 1; } + +#define MX53_OFFSET 0x20000000 + +int __init mxc_init_devices(void) +{ + if (cpu_is_mx53() || cpu_is_mx50()) { + sdma_resources[0].start -= MX53_OFFSET; + sdma_resources[0].end -= MX53_OFFSET; + mxc_w1_master_resources[0].start -= MX53_OFFSET; + mxc_w1_master_resources[0].end -= MX53_OFFSET; + mxc_kpp_resources[0].start -= MX53_OFFSET; + mxc_kpp_resources[0].end -= MX53_OFFSET; + rtc_resources[0].start -= MX53_OFFSET; + rtc_resources[0].end -= MX53_OFFSET; + + wdt_resources[0].start -= MX53_OFFSET; + wdt_resources[0].end -= MX53_OFFSET; + pwm1_resources[0].start -= MX53_OFFSET; + pwm1_resources[0].end -= MX53_OFFSET; + pwm2_resources[0].start -= MX53_OFFSET; + pwm2_resources[0].end -= MX53_OFFSET; + flexcan0_resources[0].start -= MX53_OFFSET; + flexcan0_resources[0].end -= MX53_OFFSET; + flexcan1_resources[0].start -= MX53_OFFSET; + flexcan1_resources[0].end -= MX53_OFFSET; + mxc_fec_resources[0].start -= MX53_OFFSET; + mxc_fec_resources[0].end -= MX53_OFFSET; + mxc_ptp_resources[0].start -= MX53_OFFSET; + mxc_ptp_resources[0].end -= MX53_OFFSET; + mxc_ptp_resources[1].start -= MX53_OFFSET; + mxc_ptp_resources[1].end -= MX53_OFFSET; + vpu_resources[0].start -= MX53_OFFSET; + vpu_resources[0].end -= MX53_OFFSET; + scc_resources[0].start -= MX53_OFFSET; + scc_resources[0].end -= MX53_OFFSET; + scc_resources[1].start = MX53_SCC_RAM_BASE_ADDR; + scc_resources[1].end = MX53_SCC_RAM_BASE_ADDR + SZ_16K - 1; + rngb_resources[0].start -= MX53_OFFSET; + rngb_resources[0].end -= MX53_OFFSET; + mxcspi1_resources[0].start -= MX53_OFFSET; + mxcspi1_resources[0].end -= MX53_OFFSET; + mxcspi2_resources[0].start -= MX53_OFFSET; + mxcspi2_resources[0].end -= MX53_OFFSET; + mxcspi3_resources[0].start -= MX53_OFFSET; + mxcspi3_resources[0].end -= MX53_OFFSET; + mxci2c1_resources[0].start -= MX53_OFFSET; + mxci2c1_resources[0].end -= MX53_OFFSET; + mxci2c2_resources[0].start -= MX53_OFFSET; + mxci2c2_resources[0].end -= MX53_OFFSET; + mxci2c3_resources[0].start -= MX53_OFFSET; + mxci2c3_resources[0].end -= MX53_OFFSET; + ssi1_resources[0].start -= MX53_OFFSET; + ssi1_resources[0].end -= MX53_OFFSET; + ssi2_resources[0].start -= MX53_OFFSET; + ssi2_resources[0].end -= MX53_OFFSET; + esai_resources[0].start -= MX53_OFFSET; + esai_resources[0].end -= MX53_OFFSET; + tve_resources[0].start -= MX53_OFFSET; + tve_resources[0].end -= MX53_OFFSET; + dvfs_core_resources[0].start -= MX53_OFFSET; + dvfs_core_resources[0].end -= MX53_OFFSET; + dvfs_per_resources[0].start -= MX53_OFFSET; + dvfs_per_resources[0].end -= MX53_OFFSET; + spdif_resources[0].start -= MX53_OFFSET; + spdif_resources[0].end -= MX53_OFFSET; + spdif_resources[1].start = MXC_INT_SPDIF_MX53; + spdif_resources[1].end = MXC_INT_SPDIF_MX53; + asrc_resources[0].start -= MX53_OFFSET; + asrc_resources[0].end -= MX53_OFFSET; + mxc_m4if_resources[0].start -= MX53_OFFSET; + mxc_m4if_resources[0].end -= MX53_OFFSET; + mxc_iim_resources[0].start -= MX53_OFFSET; + mxc_iim_resources[0].end -= MX53_OFFSET; + mxc_sim_resources[0].start -= MX53_OFFSET; + mxc_sim_resources[0].end -= MX53_OFFSET; + mxcsdhc1_resources[0].start -= MX53_OFFSET; + mxcsdhc1_resources[0].end -= MX53_OFFSET; + mxcsdhc2_resources[0].start -= MX53_OFFSET; + mxcsdhc2_resources[0].end -= MX53_OFFSET; + mxcsdhc3_resources[0].start -= MX53_OFFSET; + mxcsdhc3_resources[0].end -= MX53_OFFSET; + usbotg_host_resources[0].start -= MX53_OFFSET; + usbotg_host_resources[0].end -= MX53_OFFSET; + usbotg_udc_resources[0].start -= MX53_OFFSET; + usbotg_udc_resources[0].end -= MX53_OFFSET; + usbotg_xcvr_resources[0].start -= MX53_OFFSET; + usbotg_xcvr_resources[0].end -= MX53_OFFSET; + usbh1_resources[0].start -= MX53_OFFSET; + usbh1_resources[0].end -= MX53_OFFSET; + usbh2_resources[0].start -= MX53_OFFSET; + usbh2_resources[0].end -= MX53_OFFSET; + mxc_gpu_resources[2].start = MX53_GPU2D_BASE_ADDR; + mxc_gpu_resources[2].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1; + mxc_gpu2d_resources[0].start = MX53_GPU2D_BASE_ADDR; + mxc_gpu2d_resources[0].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1; + if (cpu_is_mx53()) { + mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR; + mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR + + SZ_256K - 1; + if (cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) { + z160_revision = 1; + } else { + z160_revision = 0; + } + } else { + mxc_gpu_resources[1].start = 0; + mxc_gpu_resources[1].end = 0; + mxc_gpu_resources[3].start = 0; + mxc_gpu_resources[3].end = 0; + mxc_gpu_resources[4].start = 0; + mxc_gpu_resources[4].end = 0; + z160_revision = 1; + } + ipu_resources[0].start = MX53_IPU_CTRL_BASE_ADDR; + ipu_resources[0].end = MX53_IPU_CTRL_BASE_ADDR + SZ_128M - 1; + mlb_resources[0].start -= MX53_OFFSET; + mlb_resources[0].end -= MX53_OFFSET; + mxc_nandv2_mtd_device.resource[0].start = + MX53_NFC_BASE_ADDR_AXI; + mxc_nandv2_mtd_device.resource[0].end = + MX53_NFC_BASE_ADDR_AXI + SZ_8K - 1; + mxc_nandv2_mtd_device.resource[1].start -= MX53_OFFSET; + mxc_nandv2_mtd_device.resource[1].end -= MX53_OFFSET; + ldb_resources[0].start -= MX53_OFFSET; + ldb_resources[0].end -= MX53_OFFSET; + } else if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + scc_resources[1].start += 0x8000; + scc_resources[1].end += 0x8000; + } + + + if (cpu_is_mx51() || cpu_is_mx53()) + mxc_init_scc_iram(); + return 0; +} +postcore_initcall(mxc_init_devices); + diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index c879ae71cd5b..2671b5dc6f83 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -1,8 +1,95 @@ -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ extern struct platform_device mxc_fec_device; +extern struct platform_device mxc_ptp_device; +extern struct platform_device mxc_dma_device; +extern struct platform_device mxc_w1_master_device; +extern struct platform_device mxc_keypad_device; +extern struct platform_device mxc_powerkey_device; +extern struct platform_device mxc_rtc_device; +extern struct platform_device mxc_nandv2_mtd_device; +extern struct platform_device imx_nfc_device; +extern struct platform_device mxc_wdt_device; +extern struct platform_device mxc_pwm1_device; +extern struct platform_device mxc_pwm2_device; +extern struct platform_device mxc_pwm1_backlight_device; +extern struct platform_device mxc_pwm2_backlight_device; +extern struct platform_device mxc_flexcan0_device; +extern struct platform_device mxc_flexcan1_device; +extern struct platform_device mxc_ipu_device; +extern struct platform_device mxc_fb_devices[]; +extern struct platform_device mxc_ldb_device; +extern struct platform_device mxcvpu_device; +extern struct platform_device mxcscc_device; +extern struct platform_device mxcspi1_device; +extern struct platform_device mxcspi2_device; +extern struct platform_device mxcspi3_device; +extern struct platform_device mxci2c_devices[]; +extern struct platform_device mxci2c_hs_device; +extern struct platform_device mxc_tve_device; +extern struct platform_device mxc_dvfs_core_device; +extern struct platform_device mxc_dvfs_per_device; +extern struct platform_device mxc_ssi1_device; +extern struct platform_device mxc_ssi2_device; +extern struct platform_device mxc_ssi3_device; +extern struct platform_device mxc_esai_device; +extern struct platform_device mxc_alsa_spdif_device; +extern struct platform_device mx51_lpmode_device; +extern struct platform_device mx53_lpmode_device; +extern struct platform_device busfreq_device; +extern struct platform_device sdram_autogating_device; +extern struct platform_device mxc_iim_device; +extern struct platform_device mxc_sim_device; +extern struct platform_device mxcsdhc1_device; +extern struct platform_device mxcsdhc2_device; +extern struct platform_device mxcsdhc3_device; +extern struct platform_device ahci_fsl_device; +extern struct ahci_platform_data sata_data; +extern struct platform_device pata_fsl_device; +extern struct platform_device fsl_otp_device; +extern struct platform_device gpu_device; +extern struct platform_device mxc_usbdr_udc_device; +extern struct platform_device mxc_usbdr_otg_device; extern struct platform_device mxc_usbdr_host_device; +extern struct platform_device mxc_usbdr_wakeup_device; extern struct platform_device mxc_usbh1_device; -extern struct platform_device mxc_usbdr_udc_device; -extern struct platform_device mxc_wdt; +extern struct platform_device mxc_usbh1_wakeup_device; +extern struct platform_device mxc_usbh2_device; +extern struct platform_device mxc_usbh2_wakeup_device; +extern struct platform_device mxc_mlb_device; +extern struct platform_device mxc_nandv2_mtd_device; +extern struct platform_device mxc_pxp_device; +extern struct platform_device mxc_pxp_client_device; +extern struct platform_device mxc_pxp_v4l2; +extern struct platform_device epdc_device; +extern struct platform_device elcdif_device; +extern struct platform_device mxc_v4l2_device; +extern struct platform_device mxc_v4l2out_device; +extern struct platform_device mxs_viim; +extern struct platform_device mxs_dma_apbh_device; +extern struct platform_device gpmi_nfc_device; +extern struct platform_device mxc_rngb_device; +extern struct platform_device dcp_device; +extern struct platform_device pm_device; +extern struct platform_device fixed_volt_reg_device; +extern struct platform_device mxc_zq_calib_device; +extern struct platform_device mxc_asrc_device; +extern struct platform_device mxc_perfmon; +extern struct mxs_platform_perfmon_data mxc_perfmon_data; +extern int z160_revision; diff --git a/arch/arm/mach-mx5/dma-apbh.c b/arch/arm/mach-mx5/dma-apbh.c new file mode 100644 index 000000000000..9e1b10d7c35c --- /dev/null +++ b/arch/arm/mach-mx5/dma-apbh.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "regs-apbh.h" + +#ifndef BM_APBH_CTRL0_APB_BURST_EN +#define BM_APBH_CTRL0_APB_BURST_EN BM_APBH_CTRL0_APB_BURST4_EN +#endif + +static int mxs_dma_apbh_enable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + unsigned int sem; + struct mxs_dma_device *pdev = pchan->dma; + struct mxs_dma_desc *pdesc; + + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); + if (pdesc == NULL) + return -EFAULT; + + sem = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan)); + sem = (sem & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) { + + if (pdesc->cmd.cmd.bits.chain == 0) + return 0; + if (sem < 2) { + if (!sem) + return 0; + pdesc = list_entry(pdesc->node.next, + struct mxs_dma_desc, node); + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBH_CHn_NXTCMDAR(chan)); + } + sem = pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(BF_APBH_CHn_SEMA_INCREMENT_SEMA(sem), + pdev->base + HW_APBH_CHn_SEMA(chan)); + pchan->active_num += sem; + return 0; + } + + pchan->active_num += pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBH_CHn_NXTCMDAR(chan)); + __raw_writel(pchan->active_num, pdev->base + HW_APBH_CHn_SEMA(chan)); + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL0_CLR); + return 0; +} + +static void mxs_dma_apbh_disable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + struct mxs_dma_device *pdev = pchan->dma; + __raw_writel(1 << (chan + BP_APBH_CTRL0_CLKGATE_CHANNEL), + pdev->base + HW_APBH_CTRL0_SET); +} + +static void mxs_dma_apbh_reset(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << (chan + BP_APBH_CHANNEL_CTRL_RESET_CHANNEL), + pdev->base + HW_APBH_CHANNEL_CTRL_SET); +} + +static void mxs_dma_apbh_freeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_SET); +} + +static void +mxs_dma_apbh_unfreeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_CLR); +} + +static void mxs_dma_apbh_info(struct mxs_dma_device *pdev, + unsigned int chan, struct mxs_dma_info *info) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CTRL2); + info->status = reg >> chan; + info->buf_addr = __raw_readl(pdev->base + HW_APBH_CHn_BAR(chan)); +} + +static int +mxs_dma_apbh_read_semaphore(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan)); + return (reg & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; +} + +static void +mxs_dma_apbh_enable_irq(struct mxs_dma_device *pdev, + unsigned int chan, int enable) +{ + if (enable) + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_SET); + else + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_CLR); + +} + +static int +mxs_dma_apbh_irq_is_pending(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CTRL1); + reg |= __raw_readl(pdev->base + HW_APBH_CTRL2); + return reg & (1 << chan); +} + +static void mxs_dma_apbh_ack_irq(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL1_CLR); + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL2_CLR); +} + +static struct mxs_dma_device mxs_dma_apbh = { + .name = "mxs-dma-apbh", + .enable = mxs_dma_apbh_enable, + .disable = mxs_dma_apbh_disable, + .reset = mxs_dma_apbh_reset, + .freeze = mxs_dma_apbh_freeze, + .unfreeze = mxs_dma_apbh_unfreeze, + .info = mxs_dma_apbh_info, + .read_semaphore = mxs_dma_apbh_read_semaphore, + .enable_irq = mxs_dma_apbh_enable_irq, + .irq_is_pending = mxs_dma_apbh_irq_is_pending, + .ack_irq = mxs_dma_apbh_ack_irq, +}; + +static int __devinit dma_apbh_probe(struct platform_device *pdev) +{ + int i; + struct resource *res; + struct mxs_dma_plat_data *plat; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + mxs_dma_apbh.base = ioremap(res->start, resource_size(res)); + __raw_writel(BM_APBH_CTRL0_SFTRST, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(mxs_dma_apbh.base + HW_APBH_CTRL0_CLR) & + BM_APBH_CTRL0_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -ETIME; + __raw_writel(BM_APBH_CTRL0_CLKGATE, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + plat = (struct mxs_dma_plat_data *)pdev->dev.platform_data; + if (!plat) + return -ENODEV; + if (plat->burst8) + __raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_SET); + else + __raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + if (plat->burst) + __raw_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_SET); + else + __raw_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + mxs_dma_apbh.pdev = pdev; + mxs_dma_apbh.chan_base = plat->chan_base; + mxs_dma_apbh.chan_num = plat->chan_num; + platform_set_drvdata(pdev, &mxs_dma_apbh); + return mxs_dma_device_register(&mxs_dma_apbh); +} + +static int __devexit dma_apbh_remove(struct platform_device *pdev) +{ + iounmap(mxs_dma_apbh.base); + return 0; +} + +static struct platform_driver dma_apbh_driver = { + .probe = dma_apbh_probe, + .remove = __devexit_p(dma_apbh_remove), + .driver = { + .name = "mxs-dma-apbh"}, +}; + +static int __init mxs_dma_apbh_init(void) +{ + return platform_driver_register(&dma_apbh_driver); +} + +fs_initcall(mxs_dma_apbh_init); diff --git a/arch/arm/mach-mx5/dma-apbh.h b/arch/arm/mach-mx5/dma-apbh.h new file mode 100644 index 000000000000..9d8d1de53ecf --- /dev/null +++ b/arch/arm/mach-mx5/dma-apbh.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_DMA_H__ +#define __ASM_ARCH_MACH_DMA_H__ + +enum { + MXS_DMA_CHANNEL_AHB_APBH = 0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_SSP, + MXS_MAX_DMA_CHANNELS, +}; +#endif diff --git a/arch/arm/mach-mx5/dma.c b/arch/arm/mach-mx5/dma.c new file mode 100644 index 000000000000..aec79d5a96bb --- /dev/null +++ b/arch/arm/mach-mx5/dma.c @@ -0,0 +1,1724 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include + +#include "serial.h" +#include "sdma_script_code_mx51.h" +#include "sdma_script_code_mx53.h" +#include "sdma_script_code_mx50.h" + +#define MXC_MMC_BUFFER_ACCESS 0x20 +#define MXC_SDHC_MMC_WML 64 +#define MXC_SDHC_SD_WML 256 +#define MXC_SSI_TX0_REG 0x0 +#define MXC_SSI_TX1_REG 0x4 +#define MXC_SSI_RX0_REG 0x8 +#define MXC_SSI_RX1_REG 0xC +#ifdef CONFIG_MXC_SSI_DUAL_FIFO +#define MXC_SSI_TXFIFO_WML 0x8 +#define MXC_SSI_RXFIFO_WML 0xC +#else +#define MXC_SSI_TXFIFO_WML 0x4 +#define MXC_SSI_RXFIFO_WML 0x6 +#endif +#define MXC_SPDIF_TXFIFO_WML 0x8 +#define MXC_SPDIF_RXFIFO_WML 0x8 +#define MXC_SPDIF_TX_REG 0x2C +#define MXC_SPDIF_RX_REG 0x14 +#define MXC_ASRC_FIFO_WML 0x40 +#define MXC_ASRCA_RX_REG 0x60 +#define MXC_ASRCA_TX_REG 0x64 +#define MXC_ASRCB_RX_REG 0x68 +#define MXC_ASRCB_TX_REG 0x6C +#define MXC_ASRCC_RX_REG 0x70 +#define MXC_ASRCC_TX_REG 0x74 +#define MXC_ESAI_TX_REG 0x00 +#define MXC_ESAI_RX_REG 0x04 +#define MXC_ESAI_FIFO_WML 0x40 + +typedef struct mxc_sdma_info_entry_s { + mxc_dma_device_t device; + void *chnl_info; +} mxc_sdma_info_entry_t; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_RXTL, + .per_address = UART1_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART1_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart1_tx_params = { + .chnl_params = { + .watermark_level = UART1_UFCR_TXTL, + .per_address = UART1_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART1_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART1_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_rx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_RXTL, + .per_address = UART2_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART2_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart2_tx_params = { + .chnl_params = { + .watermark_level = UART2_UFCR_TXTL, + .per_address = UART2_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART2_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART2_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_RXTL, + .per_address = UART3_BASE_ADDR, + .peripheral_type = UART_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART3_RX_MX51, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { + .chnl_params = { + .watermark_level = UART3_UFCR_TXTL, + .per_address = UART3_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART3_TX_MX51, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART3_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_rx_params = { + .chnl_params = { + .watermark_level = UART4_UFCR_RXTL, + .per_address = UART4_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ATA_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART4_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_tx_params = { + .chnl_params = { + .watermark_level = UART4_UFCR_TXTL, + .per_address = UART4_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ATA_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART4_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_rx_params = { + .chnl_params = { + .watermark_level = UART5_UFCR_RXTL, + .per_address = UART5_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART5_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART5_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_tx_params = { + .chnl_params = { + .watermark_level = UART5_UFCR_TXTL, + .per_address = UART5_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART5_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART5_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc1_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MMC_SDHC1_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width1_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_MMC_WML, + .per_address = + MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC2, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_mmc2_width4_params = { + .chnl_params = { + .watermark_level = MXC_SDHC_SD_WML, + .per_address = + MMC_SDHC2_BASE_ADDR + MXC_MMC_BUFFER_ACCESS, + .peripheral_type = MMC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SDHC2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MMC2, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u16)), + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u16)), + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u32)), + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u32)), + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u16)), + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u16)), + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u32)), + .per_address = SSI1_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI1_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi1_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u32)), + .per_address = SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI1_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u16)), + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u16)), + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u32)), + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u32)), + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u16)), + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u16)), + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u32)), + .per_address = SSI2_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI2_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi2_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u32)), + .per_address = SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI_SP, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI2_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_8bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI3_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI3_RX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_8bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI3_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI3_TX1, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_16bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u16)), + .per_address = SSI3_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI3_RX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_16bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u16)), + .per_address = SSI3_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI3_TX1, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_24bit_rx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u32)), + .per_address = SSI3_BASE_ADDR + MXC_SSI_RX0_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI3_RX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_24bit_tx0_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u32)), + .per_address = SSI3_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI3_TX1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_8bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML, + .per_address = SSI3_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI3_RX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_8bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML, + .per_address = SSI3_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI3_TX2, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_16bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u16)), + .per_address = SSI3_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI3_RX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_16bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u16)), + .per_address = SSI3_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI3_TX2, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_24bit_rx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_RXFIFO_WML * (sizeof(u32)), + .per_address = SSI3_BASE_ADDR + MXC_SSI_RX1_REG, + .peripheral_type = SSI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SSI3_RX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_RX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ssi3_24bit_tx1_params = { + .chnl_params = { + .watermark_level = MXC_SSI_TXFIFO_WML * (sizeof(u32)), + .per_address = SSI3_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = SSI, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SSI3_TX2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SSI3_TX, + .chnl_priority = 2, +}; + +static mxc_sdma_channel_params_t mxc_sdma_memory_params = { + .chnl_params = { + .peripheral_type = MEMORY, + .transfer_type = emi_2_emi, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_MEMORY, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_rx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = ATA_DMA_BASE_ADDR, + .peripheral_type = ATA, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ATA_TX_END, + .event_id2 = DMA_REQ_ATA_RX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ATA_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_ata_tx_params = { + .chnl_params = { + .watermark_level = MXC_IDE_DMA_WATERMARK, + .per_address = ATA_DMA_BASE_ADDR + 0x18, + .peripheral_type = ATA, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ATA_TX_END, + .event_id2 = DMA_REQ_ATA_TX, + .bd_number = MXC_IDE_DMA_BD_NR, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ATA_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SPDIF_MX51, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_TXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, + .peripheral_type = SPDIF, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_SPDIF_MX51, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_RXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_RX_REG, + .peripheral_type = SPDIF, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SPDIF_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrca_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCA_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrca_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcb_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCB_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcb_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcc_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML * 3, + .per_address = ASRC_BASE_ADDR + MXC_ASRCC_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA3, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcc_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML * 3, + .per_address = ASRC_BASE_ADDR + MXC_ASRCC_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA6, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI1_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI1_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI2_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI2_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI1_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI1_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI2_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI2_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ESAI_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ESAI_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcc_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA6, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ASRC_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCC_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = int_2_per, + .event_id = DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = int_2_per, + .event_id = DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = { + {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params}, + {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params}, + {MXC_DMA_UART2_RX, &mxc_sdma_uart2_rx_params}, + {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params}, + {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params}, + {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params}, + {MXC_DMA_UART4_RX, &mxc_sdma_uart4_rx_params}, + {MXC_DMA_UART4_TX, &mxc_sdma_uart4_tx_params}, + {MXC_DMA_UART5_RX, &mxc_sdma_uart5_rx_params}, + {MXC_DMA_UART5_TX, &mxc_sdma_uart5_tx_params}, + {MXC_DMA_MMC1_WIDTH_1, &mxc_sdma_mmc1_width1_params}, + {MXC_DMA_MMC1_WIDTH_4, &mxc_sdma_mmc1_width4_params}, + {MXC_DMA_MMC2_WIDTH_1, &mxc_sdma_mmc2_width1_params}, + {MXC_DMA_MMC2_WIDTH_4, &mxc_sdma_mmc2_width4_params}, + {MXC_DMA_SSI1_8BIT_RX0, &mxc_sdma_ssi1_8bit_rx0_params}, + {MXC_DMA_SSI1_8BIT_TX0, &mxc_sdma_ssi1_8bit_tx0_params}, + {MXC_DMA_SSI1_16BIT_RX0, &mxc_sdma_ssi1_16bit_rx0_params}, + {MXC_DMA_SSI1_16BIT_TX0, &mxc_sdma_ssi1_16bit_tx0_params}, + {MXC_DMA_SSI1_24BIT_RX0, &mxc_sdma_ssi1_24bit_rx0_params}, + {MXC_DMA_SSI1_24BIT_TX0, &mxc_sdma_ssi1_24bit_tx0_params}, + {MXC_DMA_SSI1_8BIT_RX1, &mxc_sdma_ssi1_8bit_rx1_params}, + {MXC_DMA_SSI1_8BIT_TX1, &mxc_sdma_ssi1_8bit_tx1_params}, + {MXC_DMA_SSI1_16BIT_RX1, &mxc_sdma_ssi1_16bit_rx1_params}, + {MXC_DMA_SSI1_16BIT_TX1, &mxc_sdma_ssi1_16bit_tx1_params}, + {MXC_DMA_SSI1_24BIT_RX1, &mxc_sdma_ssi1_24bit_rx1_params}, + {MXC_DMA_SSI1_24BIT_TX1, &mxc_sdma_ssi1_24bit_tx1_params}, + {MXC_DMA_SSI2_8BIT_RX0, &mxc_sdma_ssi2_8bit_rx0_params}, + {MXC_DMA_SSI2_8BIT_TX0, &mxc_sdma_ssi2_8bit_tx0_params}, + {MXC_DMA_SSI2_16BIT_RX0, &mxc_sdma_ssi2_16bit_rx0_params}, + {MXC_DMA_SSI2_16BIT_TX0, &mxc_sdma_ssi2_16bit_tx0_params}, + {MXC_DMA_SSI2_24BIT_RX0, &mxc_sdma_ssi2_24bit_rx0_params}, + {MXC_DMA_SSI2_24BIT_TX0, &mxc_sdma_ssi2_24bit_tx0_params}, + {MXC_DMA_SSI2_8BIT_RX1, &mxc_sdma_ssi2_8bit_rx1_params}, + {MXC_DMA_SSI2_8BIT_TX1, &mxc_sdma_ssi2_8bit_tx1_params}, + {MXC_DMA_SSI2_16BIT_RX1, &mxc_sdma_ssi2_16bit_rx1_params}, + {MXC_DMA_SSI2_16BIT_TX1, &mxc_sdma_ssi2_16bit_tx1_params}, + {MXC_DMA_SSI2_24BIT_RX1, &mxc_sdma_ssi2_24bit_rx1_params}, + {MXC_DMA_SSI2_24BIT_TX1, &mxc_sdma_ssi2_24bit_tx1_params}, + {MXC_DMA_SSI3_8BIT_RX0, &mxc_sdma_ssi3_8bit_rx0_params}, + {MXC_DMA_SSI3_8BIT_TX0, &mxc_sdma_ssi3_8bit_tx0_params}, + {MXC_DMA_SSI3_16BIT_RX0, &mxc_sdma_ssi3_16bit_rx0_params}, + {MXC_DMA_SSI3_16BIT_TX0, &mxc_sdma_ssi3_16bit_tx0_params}, + {MXC_DMA_SSI3_24BIT_RX0, &mxc_sdma_ssi3_24bit_rx0_params}, + {MXC_DMA_SSI3_24BIT_TX0, &mxc_sdma_ssi3_24bit_tx0_params}, + {MXC_DMA_SSI3_8BIT_RX1, &mxc_sdma_ssi3_8bit_rx1_params}, + {MXC_DMA_SSI3_8BIT_TX1, &mxc_sdma_ssi3_8bit_tx1_params}, + {MXC_DMA_SSI3_16BIT_RX1, &mxc_sdma_ssi3_16bit_rx1_params}, + {MXC_DMA_SSI3_16BIT_TX1, &mxc_sdma_ssi3_16bit_tx1_params}, + {MXC_DMA_SSI3_24BIT_RX1, &mxc_sdma_ssi3_24bit_rx1_params}, + {MXC_DMA_SSI3_24BIT_TX1, &mxc_sdma_ssi3_24bit_tx1_params}, + {MXC_DMA_MEMORY, &mxc_sdma_memory_params}, + {MXC_DMA_ATA_RX, &mxc_sdma_ata_rx_params}, + {MXC_DMA_ATA_TX, &mxc_sdma_ata_tx_params}, + {MXC_DMA_SPDIF_16BIT_TX, &mxc_sdma_spdif_16bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_TX, &mxc_sdma_spdif_32bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_RX, &mxc_sdma_spdif_32bit_rx_params}, + {MXC_DMA_ASRC_A_RX, &mxc_sdma_asrca_rx_params}, + {MXC_DMA_ASRC_A_TX, &mxc_sdma_asrca_tx_params}, + {MXC_DMA_ASRC_B_RX, &mxc_sdma_asrcb_rx_params}, + {MXC_DMA_ASRC_B_TX, &mxc_sdma_asrcb_tx_params}, + {MXC_DMA_ASRC_C_RX, &mxc_sdma_asrcc_rx_params}, + {MXC_DMA_ASRC_C_TX, &mxc_sdma_asrcc_tx_params}, + {MXC_DMA_ASRCA_SSI1_TX0, &mxc_sdma_asrca_ssi1_tx0_params}, + {MXC_DMA_ASRCA_SSI1_TX1, &mxc_sdma_asrca_ssi1_tx1_params}, + {MXC_DMA_ASRCA_SSI2_TX0, &mxc_sdma_asrca_ssi2_tx0_params}, + {MXC_DMA_ASRCA_SSI2_TX1, &mxc_sdma_asrca_ssi2_tx1_params}, + {MXC_DMA_ASRCB_SSI1_TX0, &mxc_sdma_asrcb_ssi1_tx0_params}, + {MXC_DMA_ASRCB_SSI1_TX1, &mxc_sdma_asrcb_ssi1_tx1_params}, + {MXC_DMA_ASRCB_SSI2_TX0, &mxc_sdma_asrcb_ssi2_tx0_params}, + {MXC_DMA_ASRCB_SSI2_TX1, &mxc_sdma_asrcb_ssi2_tx1_params}, + {MXC_DMA_ASRCA_ESAI, &mxc_sdma_asrca_esai_params}, + {MXC_DMA_ASRCB_ESAI, &mxc_sdma_asrcb_esai_params}, + {MXC_DMA_ASRCC_ESAI, &mxc_sdma_asrcc_esai_params}, + {MXC_DMA_ESAI_16BIT_RX, &mxc_sdma_esai_16bit_rx_params}, + {MXC_DMA_ESAI_16BIT_TX, &mxc_sdma_esai_16bit_tx_params}, + {MXC_DMA_ESAI_24BIT_RX, &mxc_sdma_esai_24bit_rx_params}, + {MXC_DMA_ESAI_24BIT_TX, &mxc_sdma_esai_24bit_tx_params}, +}; + +static int mxc_sdma_info_entrys = + sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]); + +static int __init dma_fixups(void) +{ + mxc_sdma_info_entry_t *p = mxc_sdma_active_dma_info; + int i; + dma_channel_ext_params *params; + + if (cpu_is_mx51()) + return 0; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + params = &(((mxc_sdma_channel_ext_params_t *)p->chnl_info)->chnl_ext_params); + params->common.per_address -= 0x20000000; + if (params->common.ext) + params->per_address2 -= 0x20000000; + } + + mxc_sdma_uart2_rx_params.chnl_params.event_id = DMA_REQ_FIRI_RX; + mxc_sdma_uart2_tx_params.chnl_params.event_id = DMA_REQ_FIRI_TX; + mxc_sdma_uart3_rx_params.chnl_params.event_id = DMA_REQ_UART3_RX_MX53; + mxc_sdma_uart3_tx_params.chnl_params.event_id = DMA_REQ_UART3_TX_MX53; + mxc_sdma_spdif_16bit_tx_params.chnl_params.event_id = DMA_REQ_SPDIF_TX; + mxc_sdma_spdif_32bit_tx_params.chnl_params.event_id = DMA_REQ_SPDIF_TX; + + if (cpu_is_mx53()) { + mxc_sdma_ssi3_8bit_tx1_params.chnl_params.event_id = + DMA_REQ_SSI3_TX2_MX53; + mxc_sdma_ssi3_16bit_tx1_params.chnl_params.event_id = + DMA_REQ_SSI3_TX2_MX53; + mxc_sdma_ssi3_24bit_tx1_params.chnl_params.event_id = + DMA_REQ_SSI3_TX2_MX53; + } else if (cpu_is_mx50()) { + /* mx50 not support double fifo */ +#ifdef CONFIG_MXC_SSI_DUAL_FIFO + u32 tx_wm = MXC_SSI_TXFIFO_WML/2; + u32 rx_wm = MXC_SSI_RXFIFO_WML/2; +#else + u32 tx_wm = MXC_SSI_TXFIFO_WML; + u32 rx_wm = MXC_SSI_RXFIFO_WML; +#endif + mxc_sdma_ssi1_8bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi1_8bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi1_16bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi1_16bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi1_24bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi1_24bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi1_8bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi1_8bit_rx1_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi1_16bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi1_16bit_rx1_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi1_24bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi1_24bit_rx1_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi2_8bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi2_8bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi2_16bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi2_16bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi2_24bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi2_24bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi2_8bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi2_8bit_rx1_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi2_16bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi2_16bit_rx1_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi2_24bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi2_24bit_rx1_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi3_8bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi3_8bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi3_16bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi3_16bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi3_24bit_tx0_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi3_24bit_rx0_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi3_8bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi3_8bit_rx1_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi3_16bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi3_16bit_rx1_params.chnl_params.watermark_level = + rx_wm; + mxc_sdma_ssi3_24bit_tx1_params.chnl_params.watermark_level = + tx_wm; + mxc_sdma_ssi3_24bit_rx1_params.chnl_params.watermark_level = + rx_wm; + } + return 0; +} +arch_initcall(dma_fixups); + +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id) +{ + mxc_sdma_info_entry_t *p = mxc_sdma_active_dma_info; + int i; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + if (p->device == channel_id) + return p->chnl_info; + + } + return NULL; +} +EXPORT_SYMBOL(mxc_sdma_get_channel_params); + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t *chnl) +{ +#ifdef CONFIG_SDMA_IRAM + int i; + for (i = MXC_DMA_CHANNEL_IRAM; i < MAX_DMA_CHANNELS; i++) + chnl[i].dynamic = 0; +#endif +} +EXPORT_SYMBOL(mxc_get_static_channels); + +static void __init mx51_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + /* AP<->BP */ + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_MX51; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1; + + /*misc */ + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + /* firi */ + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + + /* uart */ + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR_MX51; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_MX51; + + /* UART SH */ + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_per_ADDR_MX51; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR_MX51; + + /* SHP */ + sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR_MX51; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR_MX51; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_MX51; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_MX51; + + /* ATA */ + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR_MX51; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR_MX51; + + /* app */ + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR_MX51; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_MX51; + sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR_MX51; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_MX51; + + /* MSHC */ + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + /* spdif */ + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR_MX51; + + /* IPU */ + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = + ext_mem__ipu_ram_ADDR_MX51; + + /* DVFS */ + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + + /* SSI */ +#ifdef CONFIG_MXC_SSI_DUAL_FIFO + sdma_script_addr->mxc_sdma_mcu_2_ssiapp_addr = mcu_2_ssiapp_ADDR_MX51; + sdma_script_addr->mxc_sdma_ssiapp_2_mcu_addr = ssiapp_2_mcu_ADDR_MX51; + + sdma_script_addr->mxc_sdma_mcu_2_ssish_addr = mcu_2_ssish_ADDR_MX51; + sdma_script_addr->mxc_sdma_ssish_2_mcu_addr = ssish_2_mcu_ADDR_MX51; +#endif + + /* core */ + sdma_script_addr->mxc_sdma_start_addr = + (unsigned short *)sdma_code_mx51; + sdma_script_addr->mxc_sdma_ram_code_start_addr = + RAM_CODE_START_ADDR_MX51; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE_MX51; +} + +static void __init mx53_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + /* AP<->BP */ + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_MX53; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1; + + /*misc */ + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + /* firi */ + sdma_script_addr->mxc_sdma_firi_2_per_addr = firi_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = firi_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_per_2_firi_addr = mcu_2_firi_ADDR_MX53; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = mcu_2_firi_ADDR_MX53; + + /* uart */ + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_MX53; + + /* UART SH */ + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR_MX53; + + /* SHP */ + sdma_script_addr->mxc_sdma_per_2_shp_addr = mcu_2_shp_ADDR_MX53; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_MX53; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_MX53; + + /* ATA use it's own DMA */ + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = -1; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = -1; + + /* app */ + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_per_2_app_addr = mcu_2_app_ADDR_MX53; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_MX53; + + /* MSHC */ + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + /* spdif */ + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = spdif_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR_MX53; + + /* asrc script address change to use shp_2_mcu since v01.01 */ + sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = shp_2_mcu_ADDR_MX53; + + /* IPU */ + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = mcu_2_app_ADDR_MX53; + + /* DVFS */ + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + + /* SSI */ +#ifdef CONFIG_MXC_SSI_DUAL_FIFO + sdma_script_addr->mxc_sdma_mcu_2_ssiapp_addr = mcu_2_ssiapp_ADDR_MX53; + sdma_script_addr->mxc_sdma_ssiapp_2_mcu_addr = ssiapp_2_mcu_ADDR_MX53; + + sdma_script_addr->mxc_sdma_mcu_2_ssish_addr = mcu_2_ssish_ADDR_MX53; + sdma_script_addr->mxc_sdma_ssish_2_mcu_addr = ssish_2_mcu_ADDR_MX53; +#endif + + /* core */ + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code_mx53; + sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR_MX53; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE_MX53; +} + +static void __init mx50_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + /* AP<->BP */ + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_MX50; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1; + + /*misc */ + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + /* firi */ + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + + /* uart */ + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_MX50; + + /* UART SH */ + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR_MX50; + + /* SHP */ + sdma_script_addr->mxc_sdma_per_2_shp_addr = mcu_2_shp_ADDR_MX50; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_MX50; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_MX50; + + /* ATA use it's own DMA */ + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = -1; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = -1; + + /* app */ + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_per_2_app_addr = mcu_2_app_ADDR_MX50; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_MX50; + + /* MSHC */ + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + /* spdif */ + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = -1; + + sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = -1; + + /* IPU */ + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = -1; + + /* DVFS */ + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + + /* core */ + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code_mx50; + sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR_MX50; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE_MX50; +} + +void __init mxc_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + if (cpu_is_mx51()) + mx51_sdma_get_script_info(sdma_script_addr); + else if (cpu_is_mx53()) + mx53_sdma_get_script_info(sdma_script_addr); + else + mx50_sdma_get_script_info(sdma_script_addr); +} + diff --git a/arch/arm/mach-mx5/dmaengine.c b/arch/arm/mach-mx5/dmaengine.c new file mode 100644 index 000000000000..e92d9b9202e8 --- /dev/null +++ b/arch/arm/mach-mx5/dmaengine.c @@ -0,0 +1,682 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dma-apbh.h" + +static void *mxs_dma_pool; +static int mxs_dma_alignment = MXS_DMA_ALIGNMENT; + +/* + * The mutex that arbitrates access to the array of structures that represent + * all the DMA channels in the system (see mxs_dma_channels, below). + */ + +static DEFINE_MUTEX(mxs_dma_mutex); + +/* + * The list of DMA drivers that manage various DMA channels. A DMA device + * driver registers to manage DMA channels by calling mxs_dma_device_register(). + */ + +static LIST_HEAD(mxs_dma_devices); + +/* + * The array of struct mxs_dma_chan that represent every DMA channel in the + * system. The index of the structure in the array indicates the specific DMA + * hardware it represents (see mach-mx28/include/mach/dma.h). + */ + +static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS]; + +int mxs_dma_request(int channel, struct device *dev, const char *name) +{ + int ret = 0; + struct mxs_dma_chan *pchan; + + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + + if (!dev || !name) + return -EINVAL; + pchan = mxs_dma_channels + channel; + mutex_lock(&mxs_dma_mutex); + if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID) { + ret = -ENODEV; + goto out; + } + if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED) { + ret = -EBUSY; + goto out; + } + pchan->flags |= MXS_DMA_FLAGS_ALLOCATED; + pchan->name = name; + pchan->dev = (unsigned long)dev; + pchan->active_num = 0; + pchan->pending_num = 0; + spin_lock_init(&pchan->lock); + INIT_LIST_HEAD(&pchan->active); + INIT_LIST_HEAD(&pchan->done); +out: + mutex_unlock(&mxs_dma_mutex); + return ret; +} +EXPORT_SYMBOL(mxs_dma_request); + +void mxs_dma_release(int channel, struct device *dev) +{ + struct mxs_dma_chan *pchan; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + + if (pchan->flags & MXS_DMA_FLAGS_BUSY) + return; + + if (pchan->dev != (unsigned long)dev) + return; + + mutex_lock(&mxs_dma_mutex); + pchan->dev = 0; + pchan->active_num = 0; + pchan->pending_num = 0; + pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED; + mutex_unlock(&mxs_dma_mutex); +} +EXPORT_SYMBOL(mxs_dma_release); + +int mxs_dma_enable(int channel) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pchan->pending_num && pdma->enable) + ret = pdma->enable(pchan, channel - pdma->chan_base); + pchan->flags |= MXS_DMA_FLAGS_BUSY; + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_enable); + +void mxs_dma_disable(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + if (!(pchan->flags & MXS_DMA_FLAGS_BUSY)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->disable) + pdma->disable(pchan, channel - pdma->chan_base); + pchan->flags &= ~MXS_DMA_FLAGS_BUSY; + pchan->active_num = 0; + pchan->pending_num = 0; + list_splice_init(&pchan->active, &pchan->done); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_disable); + +int mxs_dma_get_info(int channel, struct mxs_dma_info *info) +{ + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; +#ifdef DUMPING_DMA_ALL + struct list_head *pos; + int value, i, offset; +#endif + + if (!info) + return -EINVAL; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EFAULT; + pdma = pchan->dma; + if (pdma->info) + pdma->info(pdma, channel - pdma->chan_base, info); + +#ifdef DUMPING_DMA_ALL + printk(KERN_INFO "\n[ %s ] channel : %d ,active : %d, pending : %d\n", + __func__, channel, pchan->active_num, pchan->pending_num); + + for (i = 0; i < 6; i++) { + offset = i * 0x10 + channel * 0x70; + value = __raw_readl(pdma->base + offset); + printk(KERN_INFO "[ %s ] offset : 0x%.3x -- 0x%.8x\n", + __func__, offset, value); + } + for (i = 0; i < 7; i++) { + offset = 0x100 + i * 0x10 + channel * 0x70; + value = __raw_readl(pdma->base + offset); + printk(KERN_INFO "[ %s ] offset : 0x%.3x -- 0x%.8x\n", + __func__, offset, value); + } + + offset = 0; + list_for_each(pos, &pchan->active) { + struct mxs_dma_desc *pdesc; + + pdesc = list_entry(pos, struct mxs_dma_desc, node); + printk(KERN_INFO "========================================\n"); + printk(KERN_INFO "The whole chain of CMD %d is :\n" + "\tNEXT_COMMAND_ADDRESS : 0x%.8lx\n" + "\tCMD : 0x%.8lx\n" + "\tDMA Buffer : 0x%.8x\n" + "\taddress : 0x%.8x\n", + offset++, + pdesc->cmd.next, + pdesc->cmd.cmd.data, + (int)pdesc->cmd.address, + (int)pdesc->address); + + for (i = 0; i < pdesc->cmd.cmd.bits.pio_words; i++) { + printk(KERN_INFO "PIO WORD [ %d ] --> 0x%.8lx\n", + i, pdesc->cmd.pio_words[i]); + } + printk(KERN_INFO "==================================\n"); + } +#endif + return 0; +} +EXPORT_SYMBOL(mxs_dma_get_info); + +int mxs_dma_cooked(int channel, struct list_head *head) +{ + int sem; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct list_head *p, *q; + struct mxs_dma_desc *pdesc; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + sem = mxs_dma_read_semaphore(channel); + if (sem < 0) + return sem; + if (sem == pchan->active_num) + return 0; + BUG_ON(sem > pchan->active_num); + spin_lock_irqsave(&pchan->lock, flags); + list_for_each_safe(p, q, &pchan->active) { + if ((pchan->active_num) <= sem) + break; + pdesc = list_entry(p, struct mxs_dma_desc, node); + pdesc->flags &= ~MXS_DMA_DESC_READY; + if (head) + list_move_tail(p, head); + else + list_move_tail(p, &pchan->done); + if (pdesc->flags & MXS_DMA_DESC_LAST) + pchan->active_num--; + } + if (sem == 0) + pchan->flags &= ~MXS_DMA_FLAGS_BUSY; + spin_unlock_irqrestore(&pchan->lock, flags); + + BUG_ON(sem != pchan->active_num); + return 0; +} +EXPORT_SYMBOL(mxs_dma_cooked); + +void mxs_dma_reset(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->reset) + pdma->reset(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_reset); + +void mxs_dma_freeze(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->freeze) + pdma->freeze(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_freeze); + +void mxs_dma_unfreeze(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->unfreeze) + pdma->unfreeze(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_unfreeze); + +int mxs_dma_read_semaphore(int channel) +{ + int ret = -EINVAL; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return ret; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return ret; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->read_semaphore) + ret = pdma->read_semaphore(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_read_semaphore); + +void mxs_dma_enable_irq(int channel, int en) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->enable_irq) + pdma->enable_irq(pdma, channel - pdma->chan_base, en); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_enable_irq); + +int mxs_dma_irq_is_pending(int channel) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return ret; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return ret; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->irq_is_pending) + ret = pdma->irq_is_pending(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_irq_is_pending); + +void mxs_dma_ack_irq(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->ack_irq) + pdma->ack_irq(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_ack_irq); + +void mxs_dma_set_target(int channel, int target) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->set_target) + pdma->set_target(pdma, channel - pdma->chan_base, target); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_set_target); + +/* mxs dma utility function */ +struct mxs_dma_desc *mxs_dma_alloc_desc(void) +{ + struct mxs_dma_desc *pdesc; + unsigned int address; + if (mxs_dma_pool == NULL) + return NULL; + + pdesc = dma_pool_alloc(mxs_dma_pool, GFP_KERNEL, &address); + if (pdesc == NULL) + return NULL; + memset(pdesc, 0, sizeof(*pdesc)); + pdesc->address = address; + return pdesc; +}; +EXPORT_SYMBOL(mxs_dma_alloc_desc); + +void mxs_dma_free_desc(struct mxs_dma_desc *pdesc) +{ + if (pdesc == NULL) + return; + + if (mxs_dma_pool == NULL) + return; + + dma_pool_free(mxs_dma_pool, pdesc, pdesc->address); +} +EXPORT_SYMBOL(mxs_dma_free_desc); + +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_desc *last; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + pdma = pchan->dma; + pdesc->cmd.next = mxs_dma_cmd_address(pdesc); + pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST; + spin_lock_irqsave(&pchan->lock, flags); + if (!list_empty(&pchan->active)) { + + last = list_entry(pchan->active.prev, + struct mxs_dma_desc, node); + + pdesc->flags &= ~MXS_DMA_DESC_FIRST; + last->flags &= ~MXS_DMA_DESC_LAST; + + last->cmd.next = mxs_dma_cmd_address(pdesc); + last->cmd.cmd.bits.chain = 1; + } + pdesc->flags |= MXS_DMA_DESC_READY; + if (pdesc->flags & MXS_DMA_DESC_FIRST) + pchan->pending_num++; + list_add_tail(&pdesc->node, &pchan->active); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_desc_append); + +int mxs_dma_desc_add_list(int channel, struct list_head *head) +{ + int ret = 0, size = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + struct list_head *p; + struct mxs_dma_desc *prev = NULL, *pcur; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + if (list_empty(head)) + return 0; + + pdma = pchan->dma; + list_for_each(p, head) { + pcur = list_entry(p, struct mxs_dma_desc, node); + if (!(pcur->cmd.cmd.bits.dec_sem || pcur->cmd.cmd.bits.chain)) + return -EINVAL; + if (prev) + prev->cmd.next = mxs_dma_cmd_address(pcur); + else + pcur->flags |= MXS_DMA_DESC_FIRST; + pcur->flags |= MXS_DMA_DESC_READY; + prev = pcur; + size++; + } + pcur = list_first_entry(head, struct mxs_dma_desc, node); + prev->cmd.next = mxs_dma_cmd_address(pcur); + prev->flags |= MXS_DMA_DESC_LAST; + + spin_lock_irqsave(&pchan->lock, flags); + if (!list_empty(&pchan->active)) { + pcur = list_entry(pchan->active.next, + struct mxs_dma_desc, node); + if (pcur->cmd.cmd.bits.dec_sem != prev->cmd.cmd.bits.dec_sem) { + ret = -EFAULT; + goto out; + } + prev->cmd.next = mxs_dma_cmd_address(pcur); + prev = list_entry(pchan->active.prev, + struct mxs_dma_desc, node); + pcur = list_first_entry(head, struct mxs_dma_desc, node); + pcur->flags &= ~MXS_DMA_DESC_FIRST; + prev->flags &= ~MXS_DMA_DESC_LAST; + prev->cmd.next = mxs_dma_cmd_address(pcur); + } + list_splice(head, &pchan->active); + pchan->pending_num += size; + if (!(pcur->cmd.cmd.bits.dec_sem) && (pcur->flags & MXS_DMA_DESC_FIRST)) + pchan->pending_num += 1; + else + pchan->pending_num += size; +out: + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_desc_add_list); + +int mxs_dma_get_cooked(int channel, struct list_head *head) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + if (head == NULL) + return 0; + + spin_lock_irqsave(&pchan->lock, flags); + list_splice(&pchan->done, head); + spin_unlock_irqrestore(&pchan->lock, flags); + return 0; +} +EXPORT_SYMBOL(mxs_dma_get_cooked); + +int mxs_dma_device_register(struct mxs_dma_device *pdev) +{ + int i; + struct mxs_dma_chan *pchan; + + if (pdev == NULL || !pdev->chan_num) + return -EINVAL; + + if ((pdev->chan_base >= MXS_MAX_DMA_CHANNELS) || + ((pdev->chan_base + pdev->chan_num) > MXS_MAX_DMA_CHANNELS)) + return -EINVAL; + + mutex_lock(&mxs_dma_mutex); + pchan = mxs_dma_channels + pdev->chan_base; + for (i = 0; i < pdev->chan_num; i++, pchan++) { + pchan->dma = pdev; + pchan->flags = MXS_DMA_FLAGS_VALID; + } + list_add(&pdev->node, &mxs_dma_devices); + mutex_unlock(&mxs_dma_mutex); + return 0; +} +EXPORT_SYMBOL(mxs_dma_device_register); + +static int __init mxs_dma_alignment_setup(char *line) +{ + get_option(&line, &mxs_dma_alignment); + mxs_dma_alignment = (mxs_dma_alignment + 3) & (~3); + mxs_dma_alignment = max(mxs_dma_alignment, MXS_DMA_ALIGNMENT); + return 1; +}; + +__setup("mxs-dma-alignment=", mxs_dma_alignment_setup); + +static int mxs_dmaengine_init(void) +{ + mxs_dma_pool = dma_pool_create("mxs_dma", NULL, + sizeof(struct mxs_dma_desc), + mxs_dma_alignment, PAGE_SIZE); + if (mxs_dma_pool == NULL) + return -ENOMEM; + return 0; +} + +subsys_initcall(mxs_dmaengine_init); + +#ifdef CONFIG_PROC_FS + +static void *mxs_dma_proc_seq_start(struct seq_file *file, loff_t * index) +{ + if (*index >= MXS_MAX_DMA_CHANNELS) + return NULL; + return mxs_dma_channels + *index; +} + +static void *mxs_dma_proc_seq_next(struct seq_file *file, void *data, + loff_t *index) +{ + if (data == NULL) + return NULL; + + if (*index >= MXS_MAX_DMA_CHANNELS) + return NULL; + + return mxs_dma_channels + (*index)++; +} + +static void mxs_dma_proc_seq_stop(struct seq_file *file, void *data) +{ +} + +static int mxs_dma_proc_seq_show(struct seq_file *file, void *data) +{ + int result; + struct mxs_dma_chan *pchan = (struct mxs_dma_chan *)data; + struct mxs_dma_device *pdev = pchan->dma; + result = seq_printf(file, "%s-channel%-d (%s)\n", + pdev->name, + pchan - mxs_dma_channels, + pchan->name ? pchan->name : "idle"); + return result; +} + +static const struct seq_operations mxc_dma_proc_seq_ops = { + .start = mxs_dma_proc_seq_start, + .next = mxs_dma_proc_seq_next, + .stop = mxs_dma_proc_seq_stop, + .show = mxs_dma_proc_seq_show +}; + +static int mxs_dma_proc_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &mxc_dma_proc_seq_ops); +} + +static const struct file_operations mxs_dma_proc_info_ops = { + .open = mxs_dma_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int __init mxs_dmaengine_info_init(void) +{ + struct proc_dir_entry *res; + res = create_proc_entry("dma-engine", 0, NULL); + if (!res) { + printk(KERN_ERR "Failed to create dma info file \n"); + return -ENOMEM; + } + res->proc_fops = &mxs_dma_proc_info_ops; + return 0; +} + +late_initcall(mxs_dmaengine_info_init); +#endif diff --git a/arch/arm/mach-mx5/dummy_gpio.c b/arch/arm/mach-mx5/dummy_gpio.c new file mode 100644 index 000000000000..6766cdf43911 --- /dev/null +++ b/arch/arm/mach-mx5/dummy_gpio.c @@ -0,0 +1,119 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +void gpio_uart_active(int port, int no_irda) {} +EXPORT_SYMBOL(gpio_uart_active); + +void gpio_uart_inactive(int port, int no_irda) {} +EXPORT_SYMBOL(gpio_uart_inactive); + +void gpio_gps_active(void) {} +EXPORT_SYMBOL(gpio_gps_active); + +void gpio_gps_inactive(void) {} +EXPORT_SYMBOL(gpio_gps_inactive); + +void config_uartdma_event(int port) {} +EXPORT_SYMBOL(config_uartdma_event); + +void gpio_spi_active(int cspi_mod) {} +EXPORT_SYMBOL(gpio_spi_active); + +void gpio_spi_inactive(int cspi_mod) {} +EXPORT_SYMBOL(gpio_spi_inactive); + +void gpio_owire_active(void) {} +EXPORT_SYMBOL(gpio_owire_active); + +void gpio_owire_inactive(void) {} +EXPORT_SYMBOL(gpio_owire_inactive); + +void gpio_i2c_active(int i2c_num) {} +EXPORT_SYMBOL(gpio_i2c_active); + +void gpio_i2c_inactive(int i2c_num) {} +EXPORT_SYMBOL(gpio_i2c_inactive); + +void gpio_i2c_hs_active(void) {} +EXPORT_SYMBOL(gpio_i2c_hs_active); + +void gpio_i2c_hs_inactive(void) {} +EXPORT_SYMBOL(gpio_i2c_hs_inactive); + +void gpio_pmic_active(void) {} +EXPORT_SYMBOL(gpio_pmic_active); + +void gpio_activate_audio_ports(void) {} +EXPORT_SYMBOL(gpio_activate_audio_ports); + +void gpio_sdhc_active(int module) {} +EXPORT_SYMBOL(gpio_sdhc_active); + +void gpio_sdhc_inactive(int module) {} +EXPORT_SYMBOL(gpio_sdhc_inactive); + +void gpio_sensor_select(int sensor) {} + +void gpio_sensor_active(unsigned int csi) {} +EXPORT_SYMBOL(gpio_sensor_active); + +void gpio_sensor_inactive(unsigned int csi) {} +EXPORT_SYMBOL(gpio_sensor_inactive); + +void gpio_ata_active(void) {} +EXPORT_SYMBOL(gpio_ata_active); + +void gpio_ata_inactive(void) {} +EXPORT_SYMBOL(gpio_ata_inactive); + +void gpio_nand_active(void) {} +EXPORT_SYMBOL(gpio_nand_active); + +void gpio_nand_inactive(void) {} +EXPORT_SYMBOL(gpio_nand_inactive); + +void gpio_keypad_active(void) {} +EXPORT_SYMBOL(gpio_keypad_active); + +void gpio_keypad_inactive(void) {} +EXPORT_SYMBOL(gpio_keypad_inactive); + +int gpio_usbotg_hs_active(void) +{ + return 0; +} +EXPORT_SYMBOL(gpio_usbotg_hs_active); + +void gpio_usbotg_hs_inactive(void) {} +EXPORT_SYMBOL(gpio_usbotg_hs_inactive); + +void gpio_fec_active(void) {} +EXPORT_SYMBOL(gpio_fec_active); + +void gpio_fec_inactive(void) {} +EXPORT_SYMBOL(gpio_fec_inactive); + +void gpio_spdif_active(void) {} +EXPORT_SYMBOL(gpio_spdif_active); + +void gpio_spdif_inactive(void) {} +EXPORT_SYMBOL(gpio_spdif_inactive); + +void gpio_mlb_active(void) {} +EXPORT_SYMBOL(gpio_mlb_active); + +void gpio_mlb_inactive(void) {} +EXPORT_SYMBOL(gpio_mlb_inactive); diff --git a/arch/arm/mach-mx5/early_setup.c b/arch/arm/mach-mx5/early_setup.c new file mode 100644 index 000000000000..dd731d7f822e --- /dev/null +++ b/arch/arm/mach-mx5/early_setup.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include + +int __initdata primary_di = { 0 }; +static int __init di_setup(char *__unused) +{ + primary_di = 1; + return 1; +} +__setup("di1_primary", di_setup); + diff --git a/arch/arm/mach-mx5/iomux.c b/arch/arm/mach-mx5/iomux.c new file mode 100644 index 000000000000..25b8514b7048 --- /dev/null +++ b/arch/arm/mach-mx5/iomux.c @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup GPIO_MX5 Board GPIO and Muxing Setup + * @ingroup MSL_MX5 + */ +/*! + * @file mach-mx5/iomux.c + * + * @brief I/O Muxing control functions + * + * @ingroup GPIO_MX5 + */ + +#include +#include +#include +#include +#include +#include +#include "iomux.h" +#include "mx51_pins.h" + +#define MUX_I_START_MX53 0x0020 +#define PAD_I_START_MX53 0x348 +#define INPUT_CTL_START_MX53 0x730 +#define MUX_I_END_MX53 (PAD_I_START_MX53 - 4) + +#define PAD_I_START_MX50 0x2CC +#define INPUT_CTL_START_MX50 0x6C4 + +/*! + * IOMUX register (base) addressesf + */ +#define IOMUXGPR0 (IO_ADDRESS(IOMUXC_BASE_ADDR)) +#define IOMUXGPR1 (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x004) +#define IOMUXSW_MUX_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR)) +#define IOMUXSW_INPUT_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR)) + +static u8 iomux_pin_res_table[(0x3F0 / 4) + 1]; +static DEFINE_SPINLOCK(gpio_mux_lock); + +static inline void *_get_sw_pad(void) +{ + if (cpu_is_mx51()) + return IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START_MX51; + else if (cpu_is_mx53()) + return IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START_MX53; + else + return IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START_MX50; +} + +static inline void *_get_mux_reg(iomux_pin_name_t pin) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (mux_reg >= 0x2FC) + mux_reg += 8; + else if (mux_reg >= 0x130) + mux_reg += 0xC; + } + return IOMUXSW_MUX_CTL + mux_reg; +} + +static inline void *_get_pad_reg(iomux_pin_name_t pin) +{ + u32 pad_reg = PIN_TO_IOMUX_PAD(pin); + void __iomem *sw_pad_reg = _get_sw_pad(); + + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (pad_reg == 0x4D0 - PAD_I_START_MX51) + pad_reg += 0x4C; + else if (pad_reg == 0x860 - PAD_I_START_MX51) + pad_reg += 0x9C; + else if (pad_reg >= 0x804 - PAD_I_START_MX51) + pad_reg += 0xB0; + else if (pad_reg >= 0x7FC - PAD_I_START_MX51) + pad_reg += 0xB4; + else if (pad_reg >= 0x4E4 - PAD_I_START_MX51) + pad_reg += 0xCC; + else + pad_reg += 8; + } + return sw_pad_reg + pad_reg; +} + +static inline void *_get_mux_end(void) +{ + if (cpu_is_mx50()) + return IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x2C8; + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) + return IO_ADDRESS(IOMUXC_BASE_ADDR) + (0x3F8 - 4); + else + return IO_ADDRESS(IOMUXC_BASE_ADDR) + (0x3F0 - 4); +} + +/*! + * This function is used to configure a pin through the IOMUX module. + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config a configuration as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + u32 ret = 0; + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + void __iomem *mux_reg = _get_mux_reg(pin); + u32 mux_data = 0; + u8 *rp; + + BUG_ON((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL)); + spin_lock(&gpio_mux_lock); + + if (config == IOMUX_CONFIG_GPIO) + mux_data = PIN_TO_ALT_GPIO(pin); + else + mux_data = config; + + __raw_writel(mux_data, mux_reg); + + /* + * Log a warning if a pin changes ownership + */ + rp = iomux_pin_res_table + pin_index; + if ((mux_data & *rp) && (*rp != mux_data)) { + /* + * Don't call printk if we're tweaking the console uart or + * we'll deadlock. + */ + printk(KERN_ERR "iomux_config_mux: Warning: iomux pin" + " config changed, reg=%p, " + " prev=0x%x new=0x%x\n", mux_reg, *rp, mux_data); + ret = -EINVAL; + } + *rp = mux_data; + spin_unlock(&gpio_mux_lock); + return ret; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config a configuration as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + int ret = iomux_config_mux(pin, config); + int gpio = IOMUX_TO_GPIO(pin); + + if (!ret && (gpio < MXC_GPIO_IRQS) && ((config == IOMUX_CONFIG_GPIO) + || (config == PIN_TO_ALT_GPIO(pin)))) + ret |= gpio_request(gpio, NULL); + + return ret; +} +EXPORT_SYMBOL(mxc_request_iomux); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config) +{ + u32 pin_index = PIN_TO_IOMUX_INDEX(pin); + u8 *rp = iomux_pin_res_table + pin_index; + int gpio = IOMUX_TO_GPIO(pin); + + *rp = 0; + if ((gpio < MXC_GPIO_IRQS) + && ((config == IOMUX_CONFIG_GPIO) + || (config == PIN_TO_ALT_GPIO(pin)))) + gpio_free(gpio); + +} +EXPORT_SYMBOL(mxc_free_iomux); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + void __iomem *pad_reg = _get_pad_reg(pin); + void __iomem *sw_pad_reg = _get_sw_pad(); + + BUG_ON(pad_reg < sw_pad_reg); + __raw_writel(config, pad_reg); +} +EXPORT_SYMBOL(mxc_iomux_set_pad); + +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) +{ + void __iomem *pad_reg = _get_pad_reg(pin); + + return __raw_readl(pad_reg); +} +EXPORT_SYMBOL(mxc_iomux_get_pad); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b #iomux_input_select_t + * @param config the binary value of elements defined in \b #iomux_input_config_t + * */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + void __iomem *reg; + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { + if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT) + input -= 4; + else if (input == MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT) + input -= 3; + else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT) + input -= 2; + else if (input >= MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT) + input -= 5; + else if (input >= MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT) + input -= 3; + else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT) + input -= 2; + else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT) + input -= 1; + + reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX51_TO1; + } else if (cpu_is_mx51()) { + reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX51; + } else if (cpu_is_mx53()) { + reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX53; + } else + reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX50; + + BUG_ON(input >= MUX_INPUT_NUM_MUX); + __raw_writel(config, reg); +} +EXPORT_SYMBOL(mxc_iomux_set_input); diff --git a/arch/arm/mach-mx5/iomux.h b/arch/arm/mach-mx5/iomux.h new file mode 100644 index 000000000000..0732f2169e0a --- /dev/null +++ b/arch/arm/mach-mx5/iomux.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX5_IOMUX_H__ +#define __MACH_MX5_IOMUX_H__ + +#include +#include + +/*! + * @file mach-mx5/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX5 + */ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: + * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x28. The pad control + * register offset is: 0x250 and also occupy the least significant bits + * within the register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_PAD_I PIN_TO_PAD_MASK + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/*! @} End IOMUX/PAD Bit field definitions */ + +typedef unsigned int iomux_pin_name_t; +typedef unsigned int iomux_input_select_t; + +/*! + * various IOMUX output functions + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0, + PAD_CTL_DRV_LOW = 0x0 << 1, + PAD_CTL_DRV_MEDIUM = 0x1 << 1, + PAD_CTL_DRV_HIGH = 0x2 << 1, + PAD_CTL_DRV_MAX = 0x3 << 1, + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_360K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_75k_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PULL = 0x1 << 6, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_HYS_NONE = 0x0 << 8, + PAD_CTL_HYS_ENABLE = 0x1 << 8, + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9, + PAD_CTL_DRV_VOT_LOW = 0x0 << 13, + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13, +} iomux_pad_config_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_config_t; + +struct mxc_iomux_pin_cfg { + iomux_pin_name_t pin; + u8 mux_mode; + u16 pad_cfg; + u8 in_select; + u8 in_mode; +}; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param config config as defined in \b #iomux_pin_ocfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in + * \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function gets the current pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @return current pad value + */ +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in + * \b #iomux_input_select_t + * @param config the binary value of elements defined in \b #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); + +#endif /* __MACH_MX5_IOMUX_H__ */ diff --git a/arch/arm/mach-mx5/lpmodes.c b/arch/arm/mach-mx5/lpmodes.c new file mode 100644 index 000000000000..fad2d814fdef --- /dev/null +++ b/arch/arm/mach-mx5/lpmodes.c @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx51_lpmodes.c + * + * @brief Driver for the Freescale Semiconductor MXC low power modes setup. + * + * MX51 is designed to play and video with minimal power consumption. + * This driver enables the platform to enter and exit audio and video low + * power modes. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ARM_LP_CLK 166250000 +#define GP_LPM_VOLTAGE 775000 +#define GP_NORMAL_VOLTAGE 1050000 + +static int org_cpu_rate; +int lp_video_mode; +int lp_audio_mode; +static struct device *lpmode_dev; +struct regulator *gp_core; + +void enter_lp_video_mode(void) +{ +} + +void exit_lp_video_mode(void) +{ +} + +void enter_lp_audio_mode(void) +{ + struct clk *tclk; + int ret; + + struct clk *p_clk; + struct clk *amode_parent_clk; + + + tclk = clk_get(NULL, "ipu_clk"); + if (clk_get_usecount(tclk) != 0) { + printk(KERN_INFO + "Cannot enter AUDIO LPM mode - display is still active\n"); + return; + } + + tclk = clk_get(NULL, "cpu_clk"); + org_cpu_rate = clk_get_rate(tclk); + +#ifdef CHANGE_DDR2_TO_PLL2 + tclk = clk_get(NULL, "ddr_clk"); + clk_set_parent(tclk, clk_get(NULL, "axi_a_clk")); + + /* Set CPU clock to be derived from PLL2 instead of PLL1 */ + tclk = clk_get(NULL, "pll1_sw_clk"); + clk_set_parent(tclk, clk_get(NULL, "pll2")); + clk_enable(tclk); + + tclk = clk_get(NULL, "ddr_clk"); + clk_set_parent(tclk, clk_get(NULL, "ddr_hf_clk")); +#endif + + /*Change the DDR freq to 133Mhz. */ + tclk = clk_get(NULL, "ddr_hf_clk"); + clk_set_rate(tclk, clk_round_rate(tclk, 133000000)); + + tclk = clk_get(NULL, "cpu_clk"); + ret = clk_set_rate(tclk, ARM_LP_CLK); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + clk_put(tclk); + /* Set the voltage to 0.775v for the GP domain. */ + ret = regulator_set_voltage(gp_core, GP_LPM_VOLTAGE, GP_LPM_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!\n"); + + tclk = clk_get(NULL, "periph_apm_clk"); + amode_parent_clk = clk_get(NULL, "lp_apm"); + p_clk = clk_get_parent(tclk); + /* Make sure osc_clk is the parent of lp_apm. */ + clk_set_parent(amode_parent_clk, clk_get(NULL, "osc")); + /* Set the parent of periph_apm_clk to be lp_apm */ + clk_set_parent(tclk, amode_parent_clk); + + amode_parent_clk = tclk; + + tclk = clk_get(NULL, "main_bus_clk"); + p_clk = clk_get_parent(tclk); + /* Set the parent of main_bus_clk to be periph_apm_clk */ + clk_set_parent(tclk, amode_parent_clk); + + clk_set_rate(clk_get(NULL, "axi_a_clk"), 24000000); + clk_set_rate(clk_get(NULL, "axi_b_clk"), 24000000); + clk_set_rate(clk_get(NULL, "ahb_clk"), 24000000); + clk_set_rate(clk_get(NULL, "emi_slow_clk"), 24000000); + clk_set_rate(clk_get(NULL, "nfc_clk"), 12000000); + + /* disable PLL3 */ + tclk = clk_get(NULL, "pll3"); + if (tclk->usecount == 1) + clk_disable(tclk); + + /* disable PLL2 */ + tclk = clk_get(NULL, "pll2"); + if (tclk->usecount == 1) + clk_disable(tclk); + + /* disable PLL1 */ + tclk = clk_get(NULL, "pll1_main_clk"); + if (tclk->usecount == 1) + clk_disable(tclk); + + lp_audio_mode = 1; +} + +void exit_lp_audio_mode(void) +{ + struct clk *tclk; + struct clk *p_clk; + struct clk *rmode_parent_clk; + int ret; + + /* Set the voltage to 1.05v for the GP domain. */ + ret = regulator_set_voltage(gp_core, + GP_NORMAL_VOLTAGE, GP_NORMAL_VOLTAGE); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!\n"); + + rmode_parent_clk = clk_get(NULL, "pll2"); + clk_enable(rmode_parent_clk); + + tclk = clk_get(NULL, "main_bus_clk"); + p_clk = clk_get_parent(tclk); + + /* Set the dividers before setting the parent clock. */ + clk_set_rate(clk_get(NULL, "axi_a_clk"), 6000000); + clk_set_rate(clk_get(NULL, "axi_b_clk"), 4800000); + clk_set_rate(clk_get(NULL, "ahb_clk"), 4800000); + clk_set_rate(clk_get(NULL, "emi_slow_clk"), 4800000); + clk_set_rate(clk_get(NULL, "nfc_clk"), 1200000); + /* Set the parent of main_bus_clk to be pll2 */ + clk_set_parent(tclk, rmode_parent_clk); + +#ifdef CHANGE_DDR2_TO_PLL2 + tclk = clk_get(NULL, "ddr_clk"); + clk_set_parent(tclk, clk_get(NULL, "axi_a_clk")); + + /* Set CPU clock to be derived from PLL1 instead of PLL2 */ + tclk = clk_get(NULL, "pll1_sw_clk"); + clk_set_parent(tclk, clk_get(NULL, "pll1_main_clk")); + clk_disable(tclk); + + tclk = clk_get(NULL, "ddr_clk"); + clk_set_parent(tclk, clk_get(NULL, "ddr_hf_clk")); +#endif + + tclk = clk_get(NULL, "cpu_clk"); + ret = clk_set_rate(tclk, org_cpu_rate); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + clk_put(tclk); + + tclk = clk_get(NULL, "cpu_clk"); + + ret = clk_set_rate(tclk, org_cpu_rate); + if (ret != 0) + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + + + /*Change the DDR freq to 200MHz*/ + tclk = clk_get(NULL, "ddr_hf_clk"); + clk_set_rate(tclk, clk_round_rate(tclk, 200000000)); + lp_audio_mode = 0; + +} + +static ssize_t lp_curr_mode(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (lp_video_mode) + return sprintf(buf, "in lp_video_mode\n"); + else if (lp_audio_mode) + return sprintf(buf, "in lp_audio_mode\n"); + else + return sprintf(buf, "in normal mode\n"); +} + +static ssize_t set_lp_mode(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + printk(KERN_DEBUG "In set_lp_mode() \n"); + + if (strstr(buf, "enable_lp_video") != NULL) { + if (!lp_video_mode) + enter_lp_video_mode(); + } else if (strstr(buf, "disable_lp_video") != NULL) { + if (lp_video_mode) + exit_lp_video_mode(); + } else if (strstr(buf, "enable_lp_audio") != NULL) { + if (!lp_audio_mode) + enter_lp_audio_mode(); + } else if (strstr(buf, "disable_lp_audio") != NULL) { + if (lp_audio_mode) + exit_lp_audio_mode(); + } + return size; +} + +static DEVICE_ATTR(lp_modes, 0644, lp_curr_mode, set_lp_mode); + +/*! + * This is the probe routine for the lp_mode driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit mx51_lpmode_probe(struct platform_device *pdev) +{ + u32 res = 0; + lpmode_dev = &pdev->dev; + + res = sysfs_create_file(&lpmode_dev->kobj, &dev_attr_lp_modes.attr); + if (res) { + printk(KERN_ERR + "lpmode_dev: Unable to register sysdev entry for lpmode_dev"); + return res; + } + + if (res != 0) { + printk(KERN_ERR "lpmode_dev: Unable to start"); + return res; + } + gp_core = regulator_get(NULL, "SW1"); + lp_video_mode = 0; + lp_audio_mode = 0; + + return 0; +} + +static struct platform_driver mx51_lpmode_driver = { + .driver = { + .name = "mx51_lpmode", + }, + .probe = mx51_lpmode_probe, +}; + +/*! + * Initialise the mx51_lpmode_driver. + * + * @return The function always returns 0. + */ + +static int __init lpmode_init(void) +{ + if (platform_driver_register(&mx51_lpmode_driver) != 0) { + printk(KERN_ERR "mx37_lpmode_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "LPMode driver module loaded\n"); + return 0; +} + +static void __exit lpmode_cleanup(void) +{ + sysfs_remove_file(&lpmode_dev->kobj, &dev_attr_lp_modes.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&mx51_lpmode_driver); +} + +module_init(lpmode_init); +module_exit(lpmode_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("LPMode driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index b7677ef80cc4..a17ae5a588c2 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -15,69 +15,50 @@ #include #include +#include #include #include #include -/* - * Define the MX51 memory map. +/*! + * This structure defines the MX5x memory map. */ -static struct map_desc mxc_io_desc[] __initdata = { +static struct map_desc mx5_io_desc[] __initdata = { + { + .virtual = AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), + .length = AIPS1_SIZE, + .type = MT_DEVICE}, { - .virtual = MX51_IRAM_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), - .length = MX51_IRAM_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_DEBUG_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), - .length = MX51_DEBUG_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_AIPS1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), - .length = MX51_AIPS1_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_SPBA0_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR), - .length = MX51_SPBA0_SIZE, - .type = MT_DEVICE - }, { - .virtual = MX51_AIPS2_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), - .length = MX51_AIPS2_SIZE, - .type = MT_DEVICE - }, + .virtual = SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), + .length = SPBA0_SIZE, + .type = MT_DEVICE}, + { + .virtual = AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), + .length = AIPS2_SIZE, + .type = MT_DEVICE}, }; -/* +/*! * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. + * system startup to create static physical to virtual memory map for + * the IO modules. */ -void __init mx51_map_io(void) +void __init mx5_map_io(void) { - mxc_set_cpu_type(MXC_CPU_MX51); - mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); - mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); -} - -void __init mx51_init_irq(void) -{ - unsigned long tzic_addr; - void __iomem *tzic_virt; + int i; - if (mx51_revision() < MX51_CHIP_REV_2_0) - tzic_addr = MX51_TZIC_BASE_ADDR_TO1; - else - tzic_addr = MX51_TZIC_BASE_ADDR; + mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); + /* Fixup the mappings for MX53 */ + if (cpu_is_mx53() || cpu_is_mx50()) { + for (i = 0; i < ARRAY_SIZE(mx5_io_desc); i++) + mx5_io_desc[i].pfn -= __phys_to_pfn(0x20000000); + } - tzic_virt = ioremap(tzic_addr, SZ_16K); - if (!tzic_virt) - panic("unable to map TZIC interrupt controller\n"); - - tzic_init_irq(tzic_virt); + iotable_init(mx5_io_desc, ARRAY_SIZE(mx5_io_desc)); + mxc_arch_reset_init(IO_ADDRESS(WDOG1_BASE_ADDR)); } + diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c new file mode 100644 index 000000000000..01d6d3db4533 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_arm2.c @@ -0,0 +1,1260 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "crm_regs.h" +#include "usb.h" +#include "dma-apbh.h" + +#define SD1_WP (3*32 + 19) /*GPIO_4_19 */ +#define SD1_CD (0*32 + 27) /*GPIO_1_27 */ +#define SD2_WP (4*32 + 16) /*GPIO_5_16 */ +#define SD2_CD (4*32 + 17) /*GPIO_5_17 */ +#define SD3_WP (4*32 + 28) /*GPIO_5_28 */ +#define SD3_CD (3*32 + 4) /*GPIO_4_4 */ +#define HP_DETECT (3*32 + 15) /*GPIO_4_15 */ +#define PWR_INT (3*32 + 18) /*GPIO_4_18 */ + +#define EPDC_D0 (2*32 + 0) /*GPIO_3_0 */ +#define EPDC_D1 (2*32 + 1) /*GPIO_3_1 */ +#define EPDC_D2 (2*32 + 2) /*GPIO_3_2 */ +#define EPDC_D3 (2*32 + 3) /*GPIO_3_3 */ +#define EPDC_D4 (2*32 + 4) /*GPIO_3_4 */ +#define EPDC_D5 (2*32 + 5) /*GPIO_3_5 */ +#define EPDC_D6 (2*32 + 6) /*GPIO_3_6 */ +#define EPDC_D7 (2*32 + 7) /*GPIO_3_7 */ +#define EPDC_GDCLK (2*32 + 16) /*GPIO_3_16 */ +#define EPDC_GDSP (2*32 + 17) /*GPIO_3_17 */ +#define EPDC_GDOE (2*32 + 18) /*GPIO_3_18 */ +#define EPDC_GDRL (2*32 + 19) /*GPIO_3_19 */ +#define EPDC_SDCLK (2*32 + 20) /*GPIO_3_20 */ +#define EPDC_SDOE (2*32 + 23) /*GPIO_3_23 */ +#define EPDC_SDLE (2*32 + 24) /*GPIO_3_24 */ +#define EPDC_SDSHR (2*32 + 26) /*GPIO_3_26 */ +#define EPDC_BDR0 (3*32 + 23) /*GPIO_4_23 */ +#define EPDC_SDCE0 (3*32 + 25) /*GPIO_4_25 */ +#define EPDC_SDCE1 (3*32 + 26) /*GPIO_4_26 */ +#define EPDC_SDCE2 (3*32 + 27) /*GPIO_4_27 */ + +#define EPDC_PMIC_WAKE (5*32 + 16) /*GPIO_6_16 */ +#define EPDC_PMIC_INT (5*32 + 17) /*GPIO_6_17 */ +#define EPDC_VCOM (3*32 + 21) /*GPIO_4_21 */ +#define EPDC_PWRSTAT (2*32 + 28) /*GPIO_3_28 */ +#define EPDC_ELCDIF_BACKLIGHT (1*32 + 18) /*GPIO_2_18 */ +#define CSPI_CS1 (3*32 + 13) /*GPIO_4_13 */ +#define CSPI_CS2 (3*32 + 11) /*GPIO_4_11*/ +#define USB_OTG_PWR (5*32 + 25) /*GPIO_6_25*/ + +extern int __init mx50_arm2_init_mc13892(void); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +static int max17135_regulator_init(struct max17135 *max17135); +static int num_cpu_wp = 2; + +static struct pad_desc mx50_armadillo2[] = { + /* SD1 */ + MX50_PAD_ECSPI2_SS0__GPIO_4_19, + MX50_PAD_EIM_CRE__GPIO_1_27, + MX50_PAD_SD1_CMD__SD1_CMD, + + MX50_PAD_SD1_CLK__SD1_CLK, + MX50_PAD_SD1_D0__SD1_D0, + MX50_PAD_SD1_D1__SD1_D1, + MX50_PAD_SD1_D2__SD1_D2, + MX50_PAD_SD1_D3__SD1_D3, + + /* SD2 */ + MX50_PAD_SD2_CD__GPIO_5_17, + MX50_PAD_SD2_WP__GPIO_5_16, + MX50_PAD_SD2_CMD__SD2_CMD, + MX50_PAD_SD2_CLK__SD2_CLK, + MX50_PAD_SD2_D0__SD2_D0, + MX50_PAD_SD2_D1__SD2_D1, + MX50_PAD_SD2_D2__SD2_D2, + MX50_PAD_SD2_D3__SD2_D3, + MX50_PAD_SD2_D4__SD2_D4, + MX50_PAD_SD2_D5__SD2_D5, + MX50_PAD_SD2_D6__SD2_D6, + MX50_PAD_SD2_D7__SD2_D7, + + /* SD3 */ + MX50_PAD_SD3_WP__GPIO_5_28, + MX50_PAD_KEY_COL2__GPIO_4_4, + MX50_PAD_SD3_CMD__SD3_CMD, + MX50_PAD_SD3_CLK__SD3_CLK, + MX50_PAD_SD3_D0__SD3_D0, + MX50_PAD_SD3_D1__SD3_D1, + MX50_PAD_SD3_D2__SD3_D2, + MX50_PAD_SD3_D3__SD3_D3, + MX50_PAD_SD3_D4__SD3_D4, + MX50_PAD_SD3_D5__SD3_D5, + MX50_PAD_SD3_D6__SD3_D6, + MX50_PAD_SD3_D7__SD3_D7, + + MX50_PAD_SSI_RXD__SSI_RXD, + MX50_PAD_SSI_TXD__SSI_TXD, + MX50_PAD_SSI_TXC__SSI_TXC, + MX50_PAD_SSI_TXFS__SSI_TXFS, + + /* LINE1_DETECT (headphone detect) */ + MX50_PAD_ECSPI1_SS0__GPIO_4_15, + + /* PWR_INT */ + MX50_PAD_ECSPI2_MISO__GPIO_4_18, + + /* UART pad setting */ + MX50_PAD_UART1_TXD__UART1_TXD, + MX50_PAD_UART1_RXD__UART1_RXD, + MX50_PAD_UART1_CTS__UART1_CTS, + MX50_PAD_UART1_RTS__UART1_RTS, + MX50_PAD_UART2_TXD__UART2_TXD, + MX50_PAD_UART2_RXD__UART2_RXD, + MX50_PAD_UART2_CTS__UART2_CTS, + MX50_PAD_UART2_RTS__UART2_RTS, + + MX50_PAD_I2C1_SCL__I2C1_SCL, + MX50_PAD_I2C1_SDA__I2C1_SDA, + MX50_PAD_I2C2_SCL__I2C2_SCL, + MX50_PAD_I2C2_SDA__I2C2_SDA, + MX50_PAD_I2C3_SCL__I2C3_SCL, + MX50_PAD_I2C3_SDA__I2C3_SDA, + + /* EPDC pins */ + MX50_PAD_EPDC_D0__EPDC_D0, + MX50_PAD_EPDC_D1__EPDC_D1, + MX50_PAD_EPDC_D2__EPDC_D2, + MX50_PAD_EPDC_D3__EPDC_D3, + MX50_PAD_EPDC_D4__EPDC_D4, + MX50_PAD_EPDC_D5__EPDC_D5, + MX50_PAD_EPDC_D6__EPDC_D6, + MX50_PAD_EPDC_D7__EPDC_D7, + MX50_PAD_EPDC_GDCLK__EPDC_GDCLK, + MX50_PAD_EPDC_GDSP__EPDC_GDSP, + MX50_PAD_EPDC_GDOE__EPDC_GDOE , + MX50_PAD_EPDC_GDRL__EPDC_GDRL, + MX50_PAD_EPDC_SDCLK__EPDC_SDCLK, + MX50_PAD_EPDC_SDOE__EPDC_SDOE, + MX50_PAD_EPDC_SDLE__EPDC_SDLE, + MX50_PAD_EPDC_SDSHR__EPDC_SDSHR, + MX50_PAD_EPDC_BDR0__EPDC_BDR0, + MX50_PAD_EPDC_SDCE0__EPDC_SDCE0, + MX50_PAD_EPDC_SDCE1__EPDC_SDCE1, + MX50_PAD_EPDC_SDCE2__EPDC_SDCE2, + + MX50_PAD_EPDC_PWRSTAT__GPIO_3_28, + MX50_PAD_EPDC_VCOM0__GPIO_4_21, + + MX50_PAD_DISP_D8__DISP_D8, + MX50_PAD_DISP_D9__DISP_D9, + MX50_PAD_DISP_D10__DISP_D10, + MX50_PAD_DISP_D11__DISP_D11, + MX50_PAD_DISP_D12__DISP_D12, + MX50_PAD_DISP_D13__DISP_D13, + MX50_PAD_DISP_D14__DISP_D14, + MX50_PAD_DISP_D15__DISP_D15, + MX50_PAD_DISP_RS__ELCDIF_VSYNC, + + /* ELCDIF contrast */ + MX50_PAD_DISP_BUSY__GPIO_2_18, + + MX50_PAD_DISP_CS__ELCDIF_HSYNC, + MX50_PAD_DISP_RD__ELCDIF_EN, + MX50_PAD_DISP_WR__ELCDIF_PIXCLK, + + /* EPD PMIC WAKEUP */ + MX50_PAD_UART4_TXD__GPIO_6_16, + + /* EPD PMIC intr */ + MX50_PAD_UART4_RXD__GPIO_6_17, + + MX50_PAD_EPITO__USBH1_PWR, + /* Need to comment below line if + * one needs to debug owire. + */ + MX50_PAD_OWIRE__USBH1_OC, + /* using gpio to control otg pwr */ + MX50_PAD_PWM2__GPIO_6_25, + MX50_PAD_PWM1__USBOTG_OC, + + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_DISP_D0__FEC_TXCLK, + MX50_PAD_DISP_D1__FEC_RX_ER, + MX50_PAD_DISP_D2__FEC_RX_DV, + MX50_PAD_DISP_D3__FEC_RXD1, + MX50_PAD_DISP_D4__FEC_RXD0, + MX50_PAD_DISP_D5__FEC_TX_EN, + MX50_PAD_DISP_D6__FEC_TXD1, + MX50_PAD_DISP_D7__FEC_TXD0, + MX50_PAD_SSI_RXFS__FEC_MDC, + + MX50_PAD_CSPI_SS0__CSPI_SS0, + MX50_PAD_ECSPI1_MOSI__CSPI_SS1, + MX50_PAD_CSPI_MOSI__CSPI_MOSI, + MX50_PAD_CSPI_MISO__CSPI_MISO, +}; + +static struct pad_desc mx50_gpmi_nand[] = { + MX50_PIN_EIM_DA8__NANDF_CLE, + MX50_PIN_EIM_DA9__NANDF_ALE, + MX50_PIN_EIM_DA10__NANDF_CE0, + MX50_PIN_EIM_DA11__NANDF_CE1, + MX50_PIN_EIM_DA12__NANDF_CE2, + MX50_PIN_EIM_DA13__NANDF_CE3, + MX50_PIN_EIM_DA14__NANDF_READY, + MX50_PIN_EIM_DA15__NANDF_DQS, + MX50_PIN_SD3_D4__NANDF_D0, + MX50_PIN_SD3_D5__NANDF_D1, + MX50_PIN_SD3_D6__NANDF_D2, + MX50_PIN_SD3_D7__NANDF_D3, + MX50_PIN_SD3_D0__NANDF_D4, + MX50_PIN_SD3_D1__NANDF_D5, + MX50_PIN_SD3_D2__NANDF_D6, + MX50_PIN_SD3_D3__NANDF_D7, + MX50_PIN_SD3_CLK__NANDF_RDN, + MX50_PIN_SD3_CMD__NANDF_WRN, + MX50_PIN_SD3_WP__NANDF_RESETN, +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, + .num_wp = 2, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "SW1", + .lp_reg_id = "SW2", +}; + +/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1050000,}, + { + .pll_rate = 800000000, + .cpu_rate = 160000000, + .pdf = 4, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 4, + .cpu_voltage = 850000,}, +}; + +static struct cpu_wp *mx50_arm2_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_auto; +} + +static void mx50_arm2_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +/* workaround for cspi chipselect pin may not keep correct level when idle */ +static void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + { + struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__CSPI_SS0; + struct pad_desc cspi_cs1 = MX50_PAD_ECSPI1_MOSI__GPIO_4_13; + + /* pull up/down deassert it */ + mxc_iomux_v3_setup_pad(&cspi_ss0); + mxc_iomux_v3_setup_pad(&cspi_cs1); + + gpio_request(CSPI_CS1, "cspi-cs1"); + gpio_direction_input(CSPI_CS1); + } + break; + case 0x2: + { + struct pad_desc cspi_ss1 = MX50_PAD_ECSPI1_MOSI__CSPI_SS1; + struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__GPIO_4_11; + + /*disable other ss */ + mxc_iomux_v3_setup_pad(&cspi_ss1); + mxc_iomux_v3_setup_pad(&cspi_ss0); + + /* pull up/down deassert it */ + gpio_request(CSPI_CS2, "cspi-cs2"); + gpio_direction_input(CSPI_CS2); + } + break; + default: + break; + } + break; + + default: + break; + } +} + +static void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + gpio_free(CSPI_CS1); + break; + case 0x2: + gpio_free(CSPI_CS2); + break; + default: + break; + } + break; + default: + break; + } + +} + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = mx50_arm2_gpio_spi_chipselect_active, + .chipselect_inactive = mx50_arm2_gpio_spi_chipselect_inactive, +}; + +static struct mxc_spi_master mxcspi3_data = { + .maxchipselect = 4, + .spi_version = 7, + .chipselect_active = mx50_arm2_gpio_spi_chipselect_active, + .chipselect_inactive = mx50_arm2_gpio_spi_chipselect_inactive, +}; + +static struct imxi2c_platform_data mxci2c_data = { + .bitrate = 100000, +}; + +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +static struct regulator_init_data max17135_init_data[] __initdata = { + { + .constraints = { + .name = "DISPLAY", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + }, { + .constraints = { + .name = "GVDD", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "GVEE", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINN", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINP", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "VCOM", + .min_uV = mV_to_uV(-4325), + .max_uV = mV_to_uV(-500), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + }, { + .constraints = { + .name = "VNEG", + .min_uV = V_to_uV(-15), + .max_uV = V_to_uV(-15), + }, + }, { + .constraints = { + .name = "VPOS", + .min_uV = V_to_uV(15), + .max_uV = V_to_uV(15), + }, + }, +}; + +static void epdc_get_pins(void) +{ + /* Claim GPIOs for EPDC pins - used during power up/down */ + gpio_request(EPDC_D0, "epdc_d0"); + gpio_request(EPDC_D1, "epdc_d1"); + gpio_request(EPDC_D2, "epdc_d2"); + gpio_request(EPDC_D3, "epdc_d3"); + gpio_request(EPDC_D4, "epdc_d4"); + gpio_request(EPDC_D5, "epdc_d5"); + gpio_request(EPDC_D6, "epdc_d6"); + gpio_request(EPDC_D7, "epdc_d7"); + gpio_request(EPDC_GDCLK, "epdc_gdclk"); + gpio_request(EPDC_GDSP, "epdc_gdsp"); + gpio_request(EPDC_GDOE, "epdc_gdoe"); + gpio_request(EPDC_GDRL, "epdc_gdrl"); + gpio_request(EPDC_SDCLK, "epdc_sdclk"); + gpio_request(EPDC_SDOE, "epdc_sdoe"); + gpio_request(EPDC_SDLE, "epdc_sdle"); + gpio_request(EPDC_SDSHR, "epdc_sdshr"); + gpio_request(EPDC_BDR0, "epdc_bdr0"); + gpio_request(EPDC_SDCE0, "epdc_sdce0"); + gpio_request(EPDC_SDCE1, "epdc_sdce1"); + gpio_request(EPDC_SDCE2, "epdc_sdce2"); +} + +static void epdc_put_pins(void) +{ + gpio_free(EPDC_D0); + gpio_free(EPDC_D1); + gpio_free(EPDC_D2); + gpio_free(EPDC_D3); + gpio_free(EPDC_D4); + gpio_free(EPDC_D5); + gpio_free(EPDC_D6); + gpio_free(EPDC_D7); + gpio_free(EPDC_GDCLK); + gpio_free(EPDC_GDSP); + gpio_free(EPDC_GDOE); + gpio_free(EPDC_GDRL); + gpio_free(EPDC_SDCLK); + gpio_free(EPDC_SDOE); + gpio_free(EPDC_SDLE); + gpio_free(EPDC_SDSHR); + gpio_free(EPDC_BDR0); + gpio_free(EPDC_SDCE0); + gpio_free(EPDC_SDCE1); + gpio_free(EPDC_SDCE2); +} + +static struct pad_desc mx50_epdc_pads_enabled[] = { + MX50_PAD_EPDC_D0__EPDC_D0, + MX50_PAD_EPDC_D1__EPDC_D1, + MX50_PAD_EPDC_D2__EPDC_D2, + MX50_PAD_EPDC_D3__EPDC_D3, + MX50_PAD_EPDC_D4__EPDC_D4, + MX50_PAD_EPDC_D5__EPDC_D5, + MX50_PAD_EPDC_D6__EPDC_D6, + MX50_PAD_EPDC_D7__EPDC_D7, + MX50_PAD_EPDC_GDCLK__EPDC_GDCLK, + MX50_PAD_EPDC_GDSP__EPDC_GDSP, + MX50_PAD_EPDC_GDOE__EPDC_GDOE, + MX50_PAD_EPDC_GDRL__EPDC_GDRL, + MX50_PAD_EPDC_SDCLK__EPDC_SDCLK, + MX50_PAD_EPDC_SDOE__EPDC_SDOE, + MX50_PAD_EPDC_SDLE__EPDC_SDLE, + MX50_PAD_EPDC_SDSHR__EPDC_SDSHR, + MX50_PAD_EPDC_BDR0__EPDC_BDR0, + MX50_PAD_EPDC_SDCE0__EPDC_SDCE0, + MX50_PAD_EPDC_SDCE1__EPDC_SDCE1, + MX50_PAD_EPDC_SDCE2__EPDC_SDCE2, +}; + +static struct pad_desc mx50_epdc_pads_disabled[] = { + MX50_PAD_EPDC_D0__GPIO_3_0, + MX50_PAD_EPDC_D1__GPIO_3_1, + MX50_PAD_EPDC_D2__GPIO_3_2, + MX50_PAD_EPDC_D3__GPIO_3_3, + MX50_PAD_EPDC_D4__GPIO_3_4, + MX50_PAD_EPDC_D5__GPIO_3_5, + MX50_PAD_EPDC_D6__GPIO_3_6, + MX50_PAD_EPDC_D7__GPIO_3_7, + MX50_PAD_EPDC_GDCLK__GPIO_3_16, + MX50_PAD_EPDC_GDSP__GPIO_3_17, + MX50_PAD_EPDC_GDOE__GPIO_3_18, + MX50_PAD_EPDC_GDRL__GPIO_3_19, + MX50_PAD_EPDC_SDCLK__GPIO_3_20, + MX50_PAD_EPDC_SDOE__GPIO_3_23, + MX50_PAD_EPDC_SDLE__GPIO_3_24, + MX50_PAD_EPDC_SDSHR__GPIO_3_26, + MX50_PAD_EPDC_BDR0__GPIO_4_23, + MX50_PAD_EPDC_SDCE0__GPIO_4_25, + MX50_PAD_EPDC_SDCE1__GPIO_4_26, + MX50_PAD_EPDC_SDCE2__GPIO_4_27, +}; + +static void epdc_enable_pins(void) +{ + /* Configure MUX settings to enable EPDC use */ + mxc_iomux_v3_setup_multiple_pads(mx50_epdc_pads_enabled, \ + ARRAY_SIZE(mx50_epdc_pads_enabled)); + + gpio_direction_input(EPDC_D0); + gpio_direction_input(EPDC_D1); + gpio_direction_input(EPDC_D2); + gpio_direction_input(EPDC_D3); + gpio_direction_input(EPDC_D4); + gpio_direction_input(EPDC_D5); + gpio_direction_input(EPDC_D6); + gpio_direction_input(EPDC_D7); + gpio_direction_input(EPDC_GDCLK); + gpio_direction_input(EPDC_GDSP); + gpio_direction_input(EPDC_GDOE); + gpio_direction_input(EPDC_GDRL); + gpio_direction_input(EPDC_SDCLK); + gpio_direction_input(EPDC_SDOE); + gpio_direction_input(EPDC_SDLE); + gpio_direction_input(EPDC_SDSHR); + gpio_direction_input(EPDC_BDR0); + gpio_direction_input(EPDC_SDCE0); + gpio_direction_input(EPDC_SDCE1); + gpio_direction_input(EPDC_SDCE2); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to + * GPIO and drive to 0. */ + mxc_iomux_v3_setup_multiple_pads(mx50_epdc_pads_disabled, \ + ARRAY_SIZE(mx50_epdc_pads_disabled)); + + gpio_direction_output(EPDC_D0, 0); + gpio_direction_output(EPDC_D1, 0); + gpio_direction_output(EPDC_D2, 0); + gpio_direction_output(EPDC_D3, 0); + gpio_direction_output(EPDC_D4, 0); + gpio_direction_output(EPDC_D5, 0); + gpio_direction_output(EPDC_D6, 0); + gpio_direction_output(EPDC_D7, 0); + gpio_direction_output(EPDC_GDCLK, 0); + gpio_direction_output(EPDC_GDSP, 0); + gpio_direction_output(EPDC_GDOE, 0); + gpio_direction_output(EPDC_GDRL, 0); + gpio_direction_output(EPDC_SDCLK, 0); + gpio_direction_output(EPDC_SDOE, 0); + gpio_direction_output(EPDC_SDLE, 0); + gpio_direction_output(EPDC_SDSHR, 0); + gpio_direction_output(EPDC_BDR0, 0); + gpio_direction_output(EPDC_SDCE0, 0); + gpio_direction_output(EPDC_SDCE1, 0); + gpio_direction_output(EPDC_SDCE2, 0); +} + +static struct fb_videomode e60_v110_mode = { + .name = "E60_V110", + .refresh = 50, + .xres = 800, + .yres = 600, + .pixclock = 18604700, + .left_margin = 8, + .right_margin = 178, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct fb_videomode e60_v220_mode = { + .name = "E60_V220", + .refresh = 85, + .xres = 800, + .yres = 600, + .pixclock = 32000000, + .left_margin = 8, + .right_margin = 166, + .upper_margin = 4, + .lower_margin = 26, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct fb_videomode e97_v110_mode = { + .name = "E97_V110", + .refresh = 50, + .xres = 1200, + .yres = 825, + .pixclock = 32000000, + .left_margin = 12, + .right_margin = 128, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct mxc_epdc_fb_mode panel_modes[] = { + { + &e60_v110_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 428, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e60_v220_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 428, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e97_v110_mode, + 8, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 632, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 3, /* num_ce */ + } +}; + +static struct mxc_epdc_fb_platform_data epdc_data = { + .epdc_mode = panel_modes, + .num_modes = ARRAY_SIZE(panel_modes), + .get_pins = epdc_get_pins, + .put_pins = epdc_put_pins, + .enable_pins = epdc_enable_pins, + .disable_pins = epdc_disable_pins, +}; + +static struct platform_device max17135_sensor_device = { + .name = "max17135_sensor", + .id = 0, +}; + +static struct max17135_platform_data max17135_pdata __initdata = { + .vneg_pwrup = 1, + .gvee_pwrup = 1, + .vpos_pwrup = 2, + .gvdd_pwrup = 1, + .gvdd_pwrdn = 1, + .vpos_pwrdn = 2, + .gvee_pwrdn = 1, + .vneg_pwrdn = 1, + .gpio_pmic_pwrgood = EPDC_PWRSTAT, + .gpio_pmic_vcom_ctrl = EPDC_VCOM, + .gpio_pmic_wakeup = EPDC_PMIC_WAKE, + .gpio_pmic_intr = EPDC_PMIC_INT, + .regulator_init = max17135_init_data, + .init = max17135_regulator_init, +}; + +static int max17135_regulator_init(struct max17135 *max17135) +{ + struct max17135_platform_data *pdata = &max17135_pdata; + int i, ret; + + max17135->gvee_pwrup = pdata->gvee_pwrup; + max17135->vneg_pwrup = pdata->vneg_pwrup; + max17135->vpos_pwrup = pdata->vpos_pwrup; + max17135->gvdd_pwrup = pdata->gvdd_pwrup; + max17135->gvdd_pwrdn = pdata->gvdd_pwrdn; + max17135->vpos_pwrdn = pdata->vpos_pwrdn; + max17135->vneg_pwrdn = pdata->vneg_pwrdn; + max17135->gvee_pwrdn = pdata->gvee_pwrdn; + + max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup + + pdata->gvdd_pwrup + pdata->gvee_pwrup; + + max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood; + max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl; + max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup; + max17135->gpio_pmic_intr = pdata->gpio_pmic_intr; + + max17135->vcom_setup = false; + max17135->init_done = false; + + for (i = 0; i <= MAX17135_VPOS; i++) { + ret = max17135_register_regulator(max17135, i, + &pdata->regulator_init[i]); + if (ret != 0) { + printk(KERN_ERR"max17135 regulator init failed: %d\n", + ret); + return ret; + } + } + + regulator_has_full_constraints(); + + return 0; +} + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "backlight-i2c", + .addr = 0x2c, + }, + { + .type = "eeprom", + .addr = 0x50, + }, +}; + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + I2C_BOARD_INFO("max17135", 0x48), + .platform_data = &max17135_pdata, + }, +}; + +static struct mtd_partition mxc_dataflash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x000100000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, +}; + +static struct flash_platform_data mxc_spi_flash_data[] = { + { + .name = "mxc_dataflash", + .parts = mxc_dataflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), + .type = "at45db321d",} +}; + + +static struct spi_board_info mxc_dataflash_device[] __initdata = { + { + .modalias = "mxc_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 3, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[0],}, +}; + +static void mx50_arm2_usb_set_vbus(bool enable) +{ + gpio_set_value(USB_OTG_PWR, enable); +} + + +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(SD1_WP); + else if (to_platform_device(dev)->id == 1) + rc = gpio_get_value(SD2_WP); + else if (to_platform_device(dev)->id == 2) + rc = gpio_get_value(SD3_WP); + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret = 0; + if (to_platform_device(dev)->id == 0) + ret = gpio_get_value(SD1_CD); + else if (to_platform_device(dev)->id == 1) + ret = gpio_get_value(SD2_CD); + else if (to_platform_device(dev)->id == 2) + ret = gpio_get_value(SD3_CD); + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static struct mxc_mmc_platform_data mmc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 40000000, + .dll_override_en = 1, + .dll_delay_cells = 0xc, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static int mxc_sgtl5000_amp_enable(int enable) +{ +/* TO DO */ + return 0; +} + +static int headphone_det_status(void) +{ + return (gpio_get_value(HP_DETECT) != 0); +} + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_irq = IOMUX_TO_IRQ_V3(HP_DETECT), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .sysclk = 12288000, +}; + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static struct pad_desc armadillo2_wvga_pads[] = { + MX50_PAD_DISP_D0__DISP_D0, + MX50_PAD_DISP_D1__DISP_D1, + MX50_PAD_DISP_D2__DISP_D2, + MX50_PAD_DISP_D3__DISP_D3, + MX50_PAD_DISP_D4__DISP_D4, + MX50_PAD_DISP_D5__DISP_D5, + MX50_PAD_DISP_D6__DISP_D6, + MX50_PAD_DISP_D7__DISP_D7, +}; + +static void wvga_reset(void) +{ + mxc_iomux_v3_setup_multiple_pads(armadillo2_wvga_pads, \ + ARRAY_SIZE(armadillo2_wvga_pads)); + return; +} + +static struct mxc_lcd_platform_data lcd_wvga_data = { + .reset = wvga_reset, +}; + +static struct platform_device lcd_wvga_device = { + .name = "lcd_claa", + .dev = { + .platform_data = &lcd_wvga_data, + }, +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = V4L2_PIX_FMT_RGB565, + .mode_str = "CLAA-WVGA", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx50(); +} + +__setup("w1", w1_setup); + +static struct mxs_dma_plat_data dma_apbh_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBH, + .chan_num = MXS_MAX_DMA_CHANNELS, +}; + +static int gpmi_nfc_platform_init(unsigned int max_chip_count) +{ + mxc_iomux_v3_setup_multiple_pads(mx50_gpmi_nand, + ARRAY_SIZE(mx50_gpmi_nand)); + return 0; +} + +static void gpmi_nfc_platform_exit(unsigned int max_chip_count) +{ +} + +static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; + +static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { + .nfc_version = 2, + .boot_rom_version = 1, + .clock_name = "gpmi-nfc", + .platform_init = gpmi_nfc_platform_init, + .platform_exit = gpmi_nfc_platform_exit, + .min_prop_delay_in_ns = 5, + .max_prop_delay_in_ns = 9, + .max_chip_count = 2, + .boot_area_size_in_bytes = 20 * SZ_1M, + .partition_source_types = gpmi_nfc_partition_source_types, + .partitions = 0, + .partition_count = 0, +}; + +/* OTP data */ +/* Building up eight registers's names of a bank */ +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (5) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), + BANK(MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, GP0, GP1), + BANK(SCC0, SCC1, SCC2, SCC3, SCC4, SCC5, SCC6, SCC7), + BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), + BANK(SJC0, SJC1, MAC0, MAC1, HWCAP0, HWCAP1, HWCAP2, SWCAP), +}; + +static struct fsl_otp_data otp_data = { + .fuse_name = (char **)bank_reg_desc, + .fuse_num = BANKS * BANK_ITEMS, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_set_cpu_type(MXC_CPU_MX50); + + get_cpu_wp = mx50_arm2_get_cpu_wp; + set_num_cpu_wp = mx50_arm2_set_num_cpu_wp; +} + +static void __init mx50_arm2_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx50_armadillo2, \ + ARRAY_SIZE(mx50_armadillo2)); + + gpio_request(SD1_WP, "sdhc1-wp"); + gpio_direction_input(SD1_WP); + + gpio_request(SD1_CD, "sdhc1-cd"); + gpio_direction_input(SD1_CD); + + gpio_request(SD2_WP, "sdhc2-wp"); + gpio_direction_input(SD2_WP); + + gpio_request(SD2_CD, "sdhc2-cd"); + gpio_direction_input(SD2_CD); + + gpio_request(SD3_WP, "sdhc3-wp"); + gpio_direction_input(SD3_WP); + + gpio_request(SD3_CD, "sdhc3-cd"); + gpio_direction_input(SD3_CD); + + gpio_request(HP_DETECT, "hp-det"); + gpio_direction_input(HP_DETECT); + + gpio_request(PWR_INT, "pwr-int"); + gpio_direction_input(PWR_INT); + + gpio_request(EPDC_PMIC_WAKE, "epdc-pmic-wake"); + gpio_direction_output(EPDC_PMIC_WAKE, 0); + + gpio_request(EPDC_VCOM, "epdc-vcom"); + gpio_direction_output(EPDC_VCOM, 0); + + gpio_request(EPDC_PMIC_INT, "epdc-pmic-int"); + gpio_direction_input(EPDC_PMIC_INT); + + gpio_request(EPDC_PWRSTAT, "epdc-pwrstat"); + gpio_direction_input(EPDC_PWRSTAT); + + /* ELCDIF backlight */ + gpio_request(EPDC_ELCDIF_BACKLIGHT, "elcdif-backlight"); + gpio_direction_output(EPDC_ELCDIF_BACKLIGHT, 1); + + if (enable_w1) { + struct pad_desc one_wire = MX50_PAD_OWIRE__OWIRE; + mxc_iomux_v3_setup_pad(&one_wire); + } + + /* USB OTG PWR */ + gpio_request(USB_OTG_PWR, "usb otg power"); + gpio_direction_output(USB_OTG_PWR, 1); + gpio_set_value(USB_OTG_PWR, 0); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + /* SD card detect irqs */ + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(SD1_CD); + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(SD2_CD); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(SD2_CD); + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(SD3_CD); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(SD3_CD); + + mxc_cpu_common_init(); + mx50_arm2_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxs_dma_apbh_device, &dma_apbh_data); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxcspi3_device, &mxcspi3_data); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_devices[2], &mxci2c_data); + + mxc_register_device(&mxc_rtc_device, NULL); + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&gpu_device, &z160_revision); + mxc_register_device(&mxc_pxp_device, NULL); + mxc_register_device(&mxc_pxp_client_device, NULL); + mxc_register_device(&mxc_pxp_v4l2, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&busfreq_device, &bus_freq_data); + + /* + mxc_register_device(&mx53_lpmode_device, NULL); + mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); + */ + +/* mxc_register_device(&mxc_keypad_device, &keypad_plat_data); */ + + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&mxc_fec_device, &fec_data); + spi_register_board_info(mxc_dataflash_device, + ARRAY_SIZE(mxc_dataflash_device)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + i2c_register_board_info(2, mxc_i2c2_board_info, + ARRAY_SIZE(mxc_i2c2_board_info)); + + mxc_register_device(&max17135_sensor_device, NULL); + mxc_register_device(&epdc_device, &epdc_data); + mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); + mxc_register_device(&elcdif_device, &fb_data[0]); + mxc_register_device(&mxs_viim, NULL); + + mx50_arm2_init_mc13892(); +/* + pm_power_off = mxc_power_off; + */ + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mxc_register_device(&gpmi_nfc_device, &gpmi_nfc_platform_data); + + mx5_set_otghost_vbus_func(mx50_arm2_usb_set_vbus); + mx5_usb_dr_init(); + mx5_usbh1_init(); + + mxc_register_device(&mxc_rngb_device, NULL); + mxc_register_device(&dcp_device, NULL); + mxc_register_device(&fsl_otp_device, &otp_data); + if (cpu_is_mx50_rev(CHIP_REV_1_1) >= 1) + mxc_register_device(&mxc_zq_calib_device, NULL); + mxc_register_device(&mxc_perfmon, &mxc_perfmon_data); +} + +static void __init mx50_arm2_timer_init(void) +{ + struct clk *uart_clk; + + mx50_clocks_init(32768, 24000000, 22579200); + + uart_clk = clk_get_sys("mxcintuart.0", NULL); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx50_arm2_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX50_ARM2 data structure. + */ +MACHINE_START(MX50_ARM2, "Freescale MX50 ARM2 Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c new file mode 100644 index 000000000000..014ec1a985d7 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c @@ -0,0 +1,434 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +/* Coin cell charger enable */ +#define COINCHEN_LSH 23 +#define COINCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* regulator standby mask */ +#define GEN1_STBY_MASK (1 << 1) +#define IOHI_STBY_MASK (1 << 4) +#define DIG_STBY_MASK (1 << 10) +#define GEN2_STBY_MASK (1 << 13) +#define PLL_STBY_MASK (1 << 16) +#define USB2_STBY_MASK (1 << 19) + +#define GEN3_STBY_MASK (1 << 1) +#define CAM_STBY_MASK (1 << 7) +#define VIDEO_STBY_MASK (1 << 13) +#define AUDIO_STBY_MASK (1 << 16) +#define SD_STBY_MASK (1 << 19) + +#define REG_MODE_0_ALL_MASK (DIG_STBY_MASK | GEN1_STBY_MASK) +#define REG_MODE_1_ALL_MASK (CAM_STBY_MASK | VIDEO_STBY_MASK |\ + AUDIO_STBY_MASK | SD_STBY_MASK) + +/* switch mode setting */ +#define SW1MODE_LSB 0 +#define SW2MODE_LSB 10 +#define SW3MODE_LSB 0 +#define SW4MODE_LSB 8 + +#define SWMODE_MASK 0xF +#define SWMODE_AUTO 0x8 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +static struct regulator_consumer_supply vgen1_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDA", + .dev_name = "1-000a", + }, + { + /* sgtl5000 */ + .supply = "VDDIO", + .dev_name = "1-000a", + }, +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1200), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2775), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(3000), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen1_consumers), + .consumer_supplies = vgen1_consumers, +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value, register_mask; + printk("Initializing regulators for mx50 arm2.\n"); + + /* enable standby controll for all regulators */ + pmic_read_reg(REG_MODE_0, &value, 0xffffff); + value |= REG_MODE_0_ALL_MASK; + pmic_write_reg(REG_MODE_0, value, 0xffffff); + + pmic_read_reg(REG_MODE_1, &value, 0xffffff); + value |= REG_MODE_1_ALL_MASK; + pmic_write_reg(REG_MODE_1, value, 0xffffff); + + /* enable switch audo mode */ + pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff); + /* only for mc13892 2.0A */ + if ((value & 0x0000FFFF) == 0x45d0) { + pmic_read_reg(REG_SW_4, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW1MODE_LSB) | + (SWMODE_MASK << SW2MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW1MODE_LSB) | + (SWMODE_AUTO << SW2MODE_LSB); + pmic_write_reg(REG_SW_4, value, 0xffffff); + + pmic_read_reg(REG_SW_5, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW3MODE_LSB) | + (SWMODE_MASK << SW4MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW3MODE_LSB) | + (SWMODE_AUTO << SW4MODE_LSB); + pmic_write_reg(REG_SW_5, value, 0xffffff); + } + /* Enable coin cell charger */ + value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); + register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + + regulator_has_full_constraints(); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct spi_board_info __initdata mc13892_spi_device = { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ_V3(114), + .max_speed_hz = 6000000, /* max spi SCK clock speed in HZ */ + .bus_num = 3, + .chip_select = 0, + .platform_data = &mc13892_plat, +}; + + +int __init mx50_arm2_init_mc13892(void) +{ + return spi_register_board_info(&mc13892_spi_device, 1); +} diff --git a/arch/arm/mach-mx5/mx50_ddr_freq.S b/arch/arm/mach-mx5/mx50_ddr_freq.S new file mode 100644 index 000000000000..38317675c52f --- /dev/null +++ b/arch/arm/mach-mx5/mx50_ddr_freq.S @@ -0,0 +1,832 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +/* + * mx50_ddr_freq_change + * + * Idle the processor (eg, wait for interrupt). + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(mx50_ddr_freq_change) + stmfd sp!, {r3,r4,r5,r6, r7} @ Save registers + + mov r6, r0 @save CCM address + mov r5, r1 @save DataBahn address + mov r4, r2 @save new freq requested + + /* Make sure no TLB miss will occur when the DDR is in self refresh. */ + /* Invalidate TLB single entry to ensure that the address is not + * already in the TLB. + */ + adr r3, LoopCKE2 @Address in this function. + mcr p15, 0, r3, c8, c7, 1 @ Make sure freq code address + @ is not already in TLB. + mcr p15, 0, r6, c8, c7, 1 @ Make sure CCM address + @ is not already in TLB. + mcr p15, 0, r5, c8, c7, 1 @ make sure Databahn address + @ is not already in TLB. + mrc p15, 0, r0, c10, c0, 0 @ Read the TLB lockdown register + orr r0, r0, #1 @ Set the Preserve bit. + mcr p15, 0, r0, c10, c0, 0 @ Write to the lockdown register + ldr r2, [r6] @ TLB will miss, + @CCM address will be loaded + ldr r2, [r5] @ TLB will miss, + @Databahn address will be loaded + ldr r2, [r3] @ TLB will miss + mrc p15, 0, r0, c10, c0, 0 @ Read the lockdown register + @ (victim will be incremented) + bic r0, r0, #1 @ Clear the preserve bit + mcr p15, 0, r0, c10, c0, 0 @ Write to the lockdown register. + + /* If Databahn is in LPM4, exit that mode first. */ + ldr r1,[r5, #0x50] @Store LPM mode in r1. + mov r0, r1 + bic r0, #0x1F + str r0,[r5, #0x50] + +LoopCKE2: + /*Wait for CKE = 1 */ + ldr r0,[r5, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + bne LoopCKE2 + +/* Wait for the databahn to idle + Meaning, no access to the databahn is + being made. +*/ +NotIdle: + ldr r0,[r5, #0x13c] + and r0, r0, #0x100 + ldr r2, =0x100 + cmp r0, r2 + beq NotIdle + + /* + * Make sure the DDR is self-refresh, before switching its frequency + * and clock source + */ + + /* Step 1: Enter self-refresh mode */ + ldr r0,[r5, #0x4c] + orr r0,r0,#0x1 + str r0,[r5, #0x4c] + + /* Step 2: Poll the CKE_STATUS bit. */ +LoopCKE0: + /* Wait for CKE = 0 */ + ldr r0,[r5, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + beq LoopCKE0 + + /* Step 3: Mask the DLL lock state change, set bit 8 in int_mask. */ + ldr r0, [r5, #0xac] + orr r0, r0, #0x100 + str r0, [r5, #0xac] + + /* Step 4: Stop the Controller. */ + ldr r0,[r5] + bic r0, r0, #0x1 + str r0,[r5] + + /* Step 5: Clear the DLL lock state change bit 8 in int_ack */ + ldr r0, [r5, #0xa8] + orr r0, r0, #0x1000000 + str r0, [r5, #0xa8] + + /* Step 6: Clear the interrupt mask for DLL lock state. + * Bit 8 in int_mask */ + ldr r0, [r5, #0xac] + bic r0, r0, #0x100 + str r0, [r5, #0xac] + + /* Change the freq now */ + /* If the freq req is below 24MHz, set DDR to synchronous mode. + * else set to async mode. */ + ldr r0, =24000000 + cmp r4, r0 + bgt Async_Mode + + /* Set the DDR to be Synchronous + mode. */ + /* Set the Databahn to sync mode. */ + ldr r0, [r5, #0xdc] + orr r0, r0, #0x30000 + str r0, [r5, #0xdc] + + /* Turn OFF the DDR_CKLGATE_MASK in MXC_CCM_DDR */ + ldr r0, [r6, #0x98] + bic r0, r0, #0xC0000000 + str r0, [r6, #0x98] + + /* Check if XTAL can source the DDR. */ + ldr r0, =24000000 + cmp r4, r0 + ble databahn_ddr_24 + + /*Source DDR from PLL1. Setup the dividers accordingly. */ + ldr r0, =800000000 + ldr r3, =1 +Loop1: + sub r0, r0, r4 + cmp r0, r4 + blt Div_Found + add r3, r3, #1 + bgt Loop1 + +Div_Found: + ldr r0, [r6, #0x94] + bic r0, r0, #0x3f + orr r0, r0, r3 + str r0, [r6, #0x94] + /* Set the DDR to sourced from PLL1 in sync path */ + ldr r0, [r6, #0x90] + orr r0, r0, #0x3 + str r0, [r6, #0x90] + + /* Turn OFF the DDR_CKLGATE_MASK in MXC_CCM_DDR */ + ldr r0, [r6, #0x98] + bic r0, r0, #0xC0000000 + str r0, [r6, #0x98] + + ldr r0, =24000000 + cmp r4, r0 + beq databahn_ddr_24 + + b Ddr_not_24 + +databahn_ddr_24: + + /* Check for mDDR v LPDDR2 memory type */ + ldr r0, [r5] + ldr r2, =0x100 + and r0, r0, #0xF00 + cmp r0, r2 + beq mddr_24 + + /* LPDDR2 settings */ + ldr r0, =0x00000003 + str r0, [r5, #0x08] + ldr r0, =0x000012c0 + str r0, [r5, #0x0c] + ldr r0, =0x00000018 + + str r0, [r5, #0x10] + ldr r0, =0x000000f0 + str r0, [r5, #0x14] + ldr r0, =0x02030b0c + str r0, [r5, #0x18] + ldr r0, =0x02020104 + str r0, [r5, #0x1c] + + ldr r0, =0x05010102 + str r0, [r5, #0x20] + ldr r0, =0x00068005 + str r0, [r5, #0x24] + ldr r0, =0x01000103 + str r0, [r5, #0x28] + ldr r0, =0x04030101 + str r0, [r5, #0x2c] + + ldr r0, =0x00000202 + str r0, [r5, #0x34] + ldr r0, =0x00000001 + str r0, [r5, #0x38] + ldr r0, =0x00000401 + str r0, [r5, #0x3c] + + /* Set TREF. */ + ldr r0, =0x00030050 + str r0, [r5, #0x40] + ldr r0, =0x00040004 + str r0, [r5, #0x48] + + ldr r0, =0x00040022 + str r0, [r5, #0x6c] + + ldr r0, =0x00040022 + str r0, [r5, #0x78] + + ldr r0, =0x00180000 + str r0, [r5, #0x80] + ldr r0, =0x00000009 + str r0, [r5, #0x84] + ldr r0, =0x02400003 + str r0, [r5, #0x88] + ldr r0, =0x01000200 + str r0, [r5, #0x8c] + + ldr r0, =0x00000000 + str r0, [r5, #0xcc] + + ldr r0, =0x01010301 + str r0, [r5, #0xd4] + ldr r0, =0x00000101 + str r0, [r5, #0xd8] + + ldr r0, =0x02000602 + str r0, [r5, #0x104] + ldr r0, =0x00560000 + str r0, [r5, #0x108] + ldr r0, =0x00560056 + str r0, [r5, #0x10c] + + ldr r0, =0x00560056 + str r0, [r5, #0x110] + ldr r0, =0x03060056 + str r0, [r5, #0x114] + + /* Set the Databahn DLL in bypass mode */ + /* PHY Register settings. */ + ldr r0, =0x0 + str r0, [r5, #0x200] + ldr r0, =0x0 + str r0, [r5, #0x204] + ldr r0, =0xf3003a27 + str r0, [r5, #0x208] + ldr r0, =0x074002c1 + str r0, [r5, #0x20c] + + ldr r0, =0xf3003a27 + str r0, [r5, #0x210] + ldr r0, =0x074002c1 + str r0, [r5, #0x214] + ldr r0, =0xf3003a27 + str r0, [r5, #0x218] + ldr r0, =0x074002c1 + str r0, [r5, #0x21c] + + ldr r0, =0xf3003a27 + str r0, [r5, #0x220] + ldr r0, =0x074002c1 + str r0, [r5, #0x224] + ldr r0, =0xf3003a27 + str r0, [r5, #0x228] + ldr r0, =0x074002c1 + str r0, [r5, #0x22c] + + ldr r0, =0x00810004 + str r0, [r5, #0x234] + ldr r0, =0x30219fd3 + str r0, [r5, #0x238] + ldr r0, =0x00219fc1 + str r0, [r5, #0x23c] + + ldr r0, =0x30219fd3 + str r0, [r5, #0x240] + ldr r0, =0x00219fc1 + str r0, [r5, #0x244] + ldr r0, =0x30219fd3 + str r0, [r5, #0x248] + ldr r0, =0x00219fc1 + str r0, [r5, #0x24c] + + ldr r0, =0x30219fd3 + str r0, [r5, #0x250] + ldr r0, =0x00219fc1 + str r0, [r5, #0x254] + ldr r0, =0x30219fd3 + str r0, [r5, #0x258] + ldr r0, =0x00219fc1 + str r0, [r5, #0x25c] + + b clocking + +/* mDDR settings */ +mddr_24: + ldr r0, =0x000012c0 + str r0, [r5, #0x08] + ldr r0, =0x02000000 + str r0, [r5, #0x14] + ldr r0, =0x01010506 + str r0, [r5, #0x18] + ldr r0, =0x01020101 + str r0, [r5, #0x1c] + + ldr r0, =0x02000103 + str r0, [r5, #0x20] + ldr r0, =0x01069002 + str r0, [r5, #0x24] + ldr r0, =0x01000101 + str r0, [r5, #0x28] + ldr r0, =0x02010101 + str r0, [r5, #0x2c] + + ldr r0, =0x00000602 + str r0, [r5, #0x34] + ldr r0, =0x00000001 + str r0, [r5, #0x38] + ldr r0, =0x00000301 + str r0, [r5, #0x3c] + + /* Set TREF. */ + ldr r0, =0x000500b0 + str r0, [r5, #0x40] + ldr r0, =0x00030003 + str r0, [r5, #0x48] + + ldr r0, =0x00000000 + str r0, [r5, #0x6c] + + ldr r0, =0x00000200 + str r0, [r5, #0xd4] + + ldr r0, =0x00b30000 + str r0, [r5, #0x108] + ldr r0, =0x00b300b3 + str r0, [r5, #0x10c] + + ldr r0, =0x00b300b3 + str r0, [r5, #0x110] + ldr r0, =0x010300b3 + str r0, [r5, #0x114] + + /* Set the Databahn DLL in bypass mode */ + /* PHY Register settings. */ + ldr r0, =0x00000100 + str r0, [r5, #0x200] + ldr r0, =0x0 + str r0, [r5, #0x204] + ldr r0, =0xf4003a27 + str r0, [r5, #0x208] + ldr r0, =0x074002c0 + str r0, [r5, #0x20c] + + ldr r0, =0xf4003a27 + str r0, [r5, #0x210] + ldr r0, =0x074002c0 + str r0, [r5, #0x214] + ldr r0, =0xf4003a27 + str r0, [r5, #0x218] + ldr r0, =0x074002c0 + str r0, [r5, #0x21c] + + ldr r0, =0xf4003a27 + str r0, [r5, #0x220] + ldr r0, =0x074002c0 + str r0, [r5, #0x224] + ldr r0, =0xf4003a27 + str r0, [r5, #0x228] + ldr r0, =0x074002c0 + str r0, [r5, #0x22c] + + ldr r0, =0x00800005 + str r0, [r5, #0x234] + ldr r0, =0x30319f14 + str r0, [r5, #0x238] + ldr r0, =0x00319f01 + str r0, [r5, #0x23c] + + ldr r0, =0x30319f14 + str r0, [r5, #0x240] + ldr r0, =0x00319f01 + str r0, [r5, #0x244] + ldr r0, =0x30319f14 + str r0, [r5, #0x248] + ldr r0, =0x00319f01 + str r0, [r5, #0x24c] + + ldr r0, =0x30319f14 + str r0, [r5, #0x250] + ldr r0, =0x00319f01 + str r0, [r5, #0x254] + ldr r0, =0x30319f14 + str r0, [r5, #0x258] + ldr r0, =0x00319f01 + str r0, [r5, #0x25c] + +clocking: + /* Set SYS_CLK to be sourced from 24MHz. */ + /* Set the SYS_XTAL_DIV */ + ldr r0, [r6, #0x94] + bic r0, r0, #0x3c0 + orr r0, r0, #0x40 + str r0, [r6, #0x94] + + /* Enable SYS_XTAL_CLKGATE. */ + ldr r0, [r6, #0x94] + orr r0, r0, #0xC0000000 + str r0, [r6, #0x94] + + /* set SYS_CLK to be sourced from XTAL. */ + ldr r0, [r6, #0x90] + bic r0, r0, #0x1 + str r0, [r6, #0x90] + + /* Disable SYS_PLL_CLKGATE.*/ + ldr r0, [r6, #0x94] + bic r0, r0, #0x30000000 + str r0, [r6, #0x94] + b Setup_Done + +Async_Mode: + /* If SYS_CLK is running at 24MHz, increase + * it to 200MHz. + */ + /* r7 indicates that we are moving from 133Mhz<-> 266MHz */ + ldr r7, =1 + ldr r0, [r6, #0x90] + and r0, r0, #0x1 + cmp r0, #0 + bne Sys_Clk_Not_24 + ldr r7, =0 + + /* Disable SYS_PLL_CLKGATE. */ + ldr r0, [r6, #0x94] + bic r0, r0, #0x30000000 + str r0, [r6, #0x94] + + /* Set the new divider. */ + ldr r0, [r6, #0x94] + bic r0, r0, #0x3f + orr r0, r0, #4 + str r0, [r6, #0x94] + + /* Enable SYS_PLL_CLKGATE. */ + ldr r0, [r6, #0x94] + orr r0, r0, #0x30000000 + str r0, [r6, #0x94] + + /* SYS_CLK to be sourced from PLL1. */ + ldr r0, [r6, #0x90] + orr r0, r0, #0x3 + str r0, [r6, #0x90] + + /* Disable SYS_XTAL_CLKGATE. */ + ldr r0, [r6, #0x94] + bic r0, r0, #0xC0000000 + str r0, [r6, #0x94] + +Sys_Clk_Not_24: + /* Set the Databahn to async mode. */ + ldr r0, [r5, #0xdc] + and r0, r0, #0xfffcffff + str r0, [r5, #0xdc] + + /*Source DDR from PLL1. Setup the dividers accordingly. */ + ldr r0, =800000000 + ldr r3, =1 +Loop2: + sub r0, r0, r4 + cmp r0, r4 + blt Div_Found1 + add r3, r3, #1 + bgt Loop2 + +Div_Found1: + /* Turn OFF the DDR_CKLGATE_MASK in MXC_CCM_DDR */ + ldr r0, [r6, #0x98] + bic r0, r0, #0xC0000000 + str r0, [r6, #0x98] + + ldr r0, [r6, #0x98] + bic r0, r0, #0x3f + orr r0, r0, r3 + str r0, [r6, #0x98] + + /* Set the DDR to sourced from PLL1 in async path */ + ldr r0, [r6, #0x98] + bic r0, r0, #0x40 + str r0, [r6, #0x98] + + /* Turn ON the DDR_CKLGATE_MASK in MXC_CCM_DDR */ + ldr r0, [r6, #0x98] + orr r0, r0, #0xC0000000 + str r0, [r6, #0x98] + + ldr r0, =24000000 + cmp r4, r0 + beq databahn_ddr_24 + +Ddr_not_24: + /* Check for mDDR v LPDDR2 memory type */ + ldr r0, [r5] + ldr r2, =0x100 + and r0, r0, #0xF00 + cmp r0, r2 + beq mddr_not_24 + + cmp r7, #1 + beq just_set_tref + + ldr r0, =0x0000001b + str r0, [r5, #0x8] + ldr r0, =0x0000d056 + str r0, [r5, #0xc] + + ldr r0, =0x0000010b + str r0, [r5, #0x10] + ldr r0, =0x00000a6b + str r0, [r5, #0x14] + ldr r0, =0x02030d0c + str r0, [r5, #0x18] + ldr r0, =0x0c110304 + str r0, [r5, #0x1c] + + ldr r0, =0x05020503 + str r0, [r5, #0x20] + ldr r0, =0x0048D005 + str r0, [r5, #0x24] + ldr r0, =0x01000403 + str r0, [r5, #0x28] + ldr r0, =0x09040501 + str r0, [r5, #0x2c] + + ldr r0, =0x00000e02 + str r0, [r5, #0x34] + ldr r0, =0x00000006 + str r0, [r5, #0x38] + ldr r0, =0x00002301 + str r0, [r5, #0x3c] + +just_set_tref: + ldr r0, =133333333 + cmp r4, r0 + bgt ddr_266 + ldr r0, =0x00050180 + b tref_done +ddr_266: + ldr r0, =0x00050300 +tref_done: + str r0, [r5, #0x40] + + cmp r7, #1 + beq Setup_Done + + ldr r0, =0x00260026 + str r0, [r5, #0x48] + + ldr r0, =0x00040042 + str r0, [r5, #0x6c] + + ldr r0, =0x00040042 + str r0, [r5, #0x78] + + ldr r0, =0x010b0000 + str r0, [r5, #0x80] + ldr r0, =0x00000060 + str r0, [r5, #0x84] + ldr r0, =0x02400018 + str r0, [r5, #0x88] + ldr r0, =0x01000e00 + str r0, [r5, #0x8c] + + ldr r0, =0x01000000 + str r0, [r5, #0xcc] + + ldr r0, =0x00000200 + str r0, [r5, #0xd4] + ldr r0, =0x00000102 + str r0, [r5, #0xd8] + + ldr r0, =0x02000802 + str r0, [r5, #0x104] + ldr r0, =0x04080000 + str r0, [r5, #0x108] + ldr r0, =0x04080408 + str r0, [r5, #0x10c] + + ldr r0, =0x04080408 + str r0, [r5, #0x110] + ldr r0, =0x03060408 + str r0, [r5, #0x114] + + /* PHY setting for 266MHz */ + ldr r0, =0x00000000 + str r0, [r5, #0x200] + ldr r0, =0x00000000 + str r0, [r5, #0x204] + ldr r0, =0xf5003a27 + str r0, [r5, #0x208] + + ldr r0, =0xf5003a27 + str r0, [r5, #0x210] + ldr r0, =0xf5003a27 + str r0, [r5, #0x218] + + ldr r0, =0xf5003a27 + str r0, [r5, #0x220] + ldr r0, =0xf5003a27 + str r0, [r5, #0x228] + + ldr r0, =0x074002e1 + str r0, [r5, #0x20c] + ldr r0, =0x074002e1 + str r0, [r5, #0x214] + ldr r0, =0x074002e1 + str r0, [r5, #0x21c] + ldr r0, =0x074002e1 + str r0, [r5, #0x224] + ldr r0, =0x074002e1 + str r0, [r5, #0x22c] + + ldr r0, =0x00810006 + str r0, [r5, #0x234] + ldr r0, =0x60099414 + str r0, [r5, #0x238] + ldr r0, =0x000a0b01 + str r0, [r5, #0x23c] + + ldr r0, =0x60099414 + str r0, [r5, #0x240] + ldr r0, =0x000a0b01 + str r0, [r5, #0x244] + ldr r0, =0x60099414 + str r0, [r5, #0x248] + ldr r0, =0x000a0b01 + str r0, [r5, #0x24c] + + ldr r0, =0x60099414 + str r0, [r5, #0x250] + ldr r0, =0x000a0b01 + str r0, [r5, #0x254] + ldr r0, =0x60099414 + str r0, [r5, #0x258] + ldr r0, =0x000a0b01 + str r0, [r5, #0x25c] + + b Setup_Done + +mddr_not_24: + /* mDDR settings */ + cmp r7, #1 + beq just_set_tref_mddr + + ldr r0, =0x00009c40 + str r0, [r5, #0x8] + + ldr r0, =0x02000000 + str r0, [r5, #0x14] + ldr r0, =0x01010706 + str r0, [r5, #0x18] + ldr r0, =0x080b0201 + str r0, [r5, #0x1c] + + ldr r0, =0x02000303 + str r0, [r5, #0x20] + ldr r0, =0x0136b002 + str r0, [r5, #0x24] + ldr r0, =0x01000101 + str r0, [r5, #0x28] + ldr r0, =0x06030301 + str r0, [r5, #0x2c] + + ldr r0, =0x00000a02 + str r0, [r5, #0x34] + ldr r0, =0x00000003 + str r0, [r5, #0x38] + ldr r0, =0x00001401 + str r0, [r5, #0x3c] + +just_set_tref_mddr: + ldr r0, =133333333 + cmp r4, r0 + bgt mddr_200 + ldr r0, =0x00050208 + b tref_done1 +mddr_200: + ldr r0, =0x0005030f +tref_done1: + str r0, [r5, #0x40] + + cmp r7, #1 + beq Setup_Done + + ldr r0, =0x00180018 + str r0, [r5, #0x48] + + ldr r0, =0x00800000 + str r0, [r5, #0x6c] + + ldr r0, =0x02030302 + str r0, [r5, #0xd4] + + ldr r0, =0x06120000 + str r0, [r5, #0x108] + ldr r0, =0x06120612 + str r0, [r5, #0x10c] + + ldr r0, =0x06120612 + str r0, [r5, #0x110] + ldr r0, =0x01030612 + str r0, [r5, #0x114] + + /* PHY setting for 200 MHz */ + ldr r0, =0x00000000 + str r0, [r5, #0x200] + ldr r0, =0x00000000 + str r0, [r5, #0x204] + ldr r0, =0xf5002725 + str r0, [r5, #0x208] + + ldr r0, =0xf5002725 + str r0, [r5, #0x210] + ldr r0, =0xf5002725 + str r0, [r5, #0x218] + + ldr r0, =0xf5002725 + str r0, [r5, #0x220] + ldr r0, =0xf5002725 + str r0, [r5, #0x228] + + ldr r0, =0x070002d0 + str r0, [r5, #0x20c] + ldr r0, =0x074002d0 + str r0, [r5, #0x214] + ldr r0, =0x074002d0 + str r0, [r5, #0x21c] + ldr r0, =0x074002d0 + str r0, [r5, #0x224] + ldr r0, =0x074002d0 + str r0, [r5, #0x22c] + + ldr r0, =0x00800006 + str r0, [r5, #0x234] + ldr r0, =0x200e1014 + str r0, [r5, #0x238] + ldr r0, =0x000d9f01 + str r0, [r5, #0x23c] + + ldr r0, =0x200e1014 + str r0, [r5, #0x240] + ldr r0, =0x000d9f01 + str r0, [r5, #0x244] + ldr r0, =0x200e1014 + str r0, [r5, #0x248] + ldr r0, =0x000d9f01 + str r0, [r5, #0x24c] + + ldr r0, =0x200e1014 + str r0, [r5, #0x250] + ldr r0, =0x000d9f01 + str r0, [r5, #0x254] + ldr r0, =0x200e1014 + str r0, [r5, #0x258] + ldr r0, =0x000d9f01 + str r0, [r5, #0x25c] + +Setup_Done: + /* Start controller */ + ldr r0,[r5] + orr r0, r0,#0x1 + str r0,[r5] + + /* Poll the DLL lock state change in int_status reg*/ + /* DLL is bypassed in the 24MHz mode, so no waiting for DLL to lock. */ + ldr r0, =24000000 + cmp r4, r0 + beq Exit_Self_Refresh + +DllLock: + ldr r0, [r5, #0xa8] + and r0, r0, #0x100 + ldr r2, =0x100 + cmp r0, r2 + bne DllLock + + /*Leave self-refresh mode */ +Exit_Self_Refresh: + ldr r0,[r5, #0x4c] + and r0,r0,#0xfffffffe + str r0,[r5, #0x4c] + +LoopCKE1: + /*Wait for CKE = 1 */ + ldr r0,[r5, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + bne LoopCKE1 + + /* Put the databahn back to into the LPM mode. */ + str r1,[r5, #0x50] + + /* Restore registers */ + ldmfd sp!, {r3,r4,r5,r6, r7} + mov pc, lr + + .type mx50_do_ddr_freq_change, #object +ENTRY(mx50_do_ddr_freq_change) + .word mx50_ddr_freq_change + .size mx50_ddr_freq_change, . - mx50_ddr_freq_change diff --git a/arch/arm/mach-mx5/mx50_rdp.c b/arch/arm/mach-mx5/mx50_rdp.c new file mode 100644 index 000000000000..f5b64400f4a5 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_rdp.c @@ -0,0 +1,1595 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "usb.h" +#include "crm_regs.h" +#include "dma-apbh.h" + +#define SD1_WP (3*32 + 19) /*GPIO_4_19 */ +#define SD1_CD (0*32 + 27) /*GPIO_1_27 */ +#define SD2_WP (4*32 + 16) /*GPIO_5_16 */ +#define SD2_CD (4*32 + 17) /*GPIO_5_17 */ +#define HP_DETECT (3*32 + 15) /*GPIO_4_15 */ +#define PWR_INT (3*32 + 18) /*GPIO_4_18 */ +#define EPDC_D0 (2*32 + 0) /*GPIO_3_0 */ +#define EPDC_D1 (2*32 + 1) /*GPIO_3_1 */ +#define EPDC_D2 (2*32 + 2) /*GPIO_3_2 */ +#define EPDC_D3 (2*32 + 3) /*GPIO_3_3 */ +#define EPDC_D4 (2*32 + 4) /*GPIO_3_4 */ +#define EPDC_D5 (2*32 + 5) /*GPIO_3_5 */ +#define EPDC_D6 (2*32 + 6) /*GPIO_3_6 */ +#define EPDC_D7 (2*32 + 7) /*GPIO_3_7 */ +#define EPDC_GDCLK (2*32 + 16) /*GPIO_3_16 */ +#define EPDC_GDSP (2*32 + 17) /*GPIO_3_17 */ +#define EPDC_GDOE (2*32 + 18) /*GPIO_3_18 */ +#define EPDC_GDRL (2*32 + 19) /*GPIO_3_19 */ +#define EPDC_SDCLK (2*32 + 20) /*GPIO_3_20 */ +#define EPDC_SDOE (2*32 + 23) /*GPIO_3_23 */ +#define EPDC_SDLE (2*32 + 24) /*GPIO_3_24 */ +#define EPDC_SDSHR (2*32 + 26) /*GPIO_3_26 */ +#define EPDC_BDR0 (3*32 + 23) /*GPIO_4_23 */ +#define EPDC_SDCE0 (3*32 + 25) /*GPIO_4_25 */ +#define EPDC_SDCE1 (3*32 + 26) /*GPIO_4_26 */ +#define EPDC_SDCE2 (3*32 + 27) /*GPIO_4_27 */ +#define EPDC_PMIC_WAKE (5*32 + 16) /*GPIO_6_16 */ +#define EPDC_PMIC_INT (5*32 + 17) /*GPIO_6_17 */ +#define EPDC_VCOM (3*32 + 21) /*GPIO_4_21 */ +#define EPDC_PWRSTAT (2*32 + 28) /*GPIO_3_28 */ +#define ELCDIF_PWR_ON (1*32 + 21) /*GPIO_2_21 */ +#define ELCDIF_DAT0_DUMMY (0*32 + 0) /*GPIO_1_0 */ +#define ELCDIF_DAT1_DUMMY (0*32 + 1) /*GPIO_1_1 */ +#define ELCDIF_DAT2_DUMMY (0*32 + 2) /*GPIO_1_2 */ +#define ELCDIF_DAT8_DUMMY (0*32 + 3) /*GPIO_1_3 */ +#define ELCDIF_DAT9_DUMMY (0*32 + 4) /*GPIO_1_4 */ +#define ELCDIF_DAT16_DUMMY (0*32 + 5) /*GPIO_1_5 */ +#define ELCDIF_DAT17_DUMMY (0*32 + 6) /*GPIO_1_6 */ +#define ELCDIF_DAT18_DUMMY (0*32 + 7) /*GPIO_1_7 */ +#define CSPI_CS1 (3*32 + 13) /*GPIO_4_13 */ +#define CSPI_CS2 (3*32 + 11) /*GPIO_4_11*/ +#define SGTL_OSCEN (5*32 + 8) /*GPIO_6_8*/ +#define SGTL_AMP_SHDN (5*32 + 15) /*GPIO_6_15*/ +#define FEC_EN (5*32 + 23) /*GPIO_6_23*/ +#define FEC_RESET_B (3*32 + 12) /*GPIO_4_12*/ +#define USB_OTG_PWR (5*32 + 25) /*GPIO_6_25*/ + +extern int __init mx50_rdp_init_mc13892(void); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +static int max17135_regulator_init(struct max17135 *max17135); +static int num_cpu_wp = 2; + +static struct pad_desc mx50_rdp[] = { + /* SD1 */ + MX50_PAD_ECSPI2_SS0__GPIO_4_19, + MX50_PAD_EIM_CRE__GPIO_1_27, + MX50_PAD_SD1_CMD__SD1_CMD, + + MX50_PAD_SD1_CLK__SD1_CLK, + MX50_PAD_SD1_D0__SD1_D0, + MX50_PAD_SD1_D1__SD1_D1, + MX50_PAD_SD1_D2__SD1_D2, + MX50_PAD_SD1_D3__SD1_D3, + + /* SD2 */ + MX50_PAD_SD2_CD__GPIO_5_17, + MX50_PAD_SD2_WP__GPIO_5_16, + MX50_PAD_SD2_CMD__SD2_CMD, + MX50_PAD_SD2_CLK__SD2_CLK, + MX50_PAD_SD2_D0__SD2_D0, + MX50_PAD_SD2_D1__SD2_D1, + MX50_PAD_SD2_D2__SD2_D2, + MX50_PAD_SD2_D3__SD2_D3, + MX50_PAD_SD2_D4__SD2_D4, + MX50_PAD_SD2_D5__SD2_D5, + MX50_PAD_SD2_D6__SD2_D6, + MX50_PAD_SD2_D7__SD2_D7, + + /* SD3 */ + MX50_PAD_SD3_CMD__SD3_CMD, + MX50_PAD_SD3_CLK__SD3_CLK, + MX50_PAD_SD3_D0__SD3_D0, + MX50_PAD_SD3_D1__SD3_D1, + MX50_PAD_SD3_D2__SD3_D2, + MX50_PAD_SD3_D3__SD3_D3, + MX50_PAD_SD3_D4__SD3_D4, + MX50_PAD_SD3_D5__SD3_D5, + MX50_PAD_SD3_D6__SD3_D6, + MX50_PAD_SD3_D7__SD3_D7, + + MX50_PAD_SSI_RXD__SSI_RXD, + MX50_PAD_SSI_TXD__SSI_TXD, + MX50_PAD_SSI_TXC__SSI_TXC, + MX50_PAD_SSI_TXFS__SSI_TXFS, + + /* HP_DET_B (headphone detect) */ + MX50_PAD_ECSPI1_SS0__GPIO_4_15, + + /* PWR_INT */ + MX50_PAD_ECSPI2_MISO__GPIO_4_18, + + /* UART pad setting */ + MX50_PAD_UART1_TXD__UART1_TXD, + MX50_PAD_UART1_RXD__UART1_RXD, + MX50_PAD_UART1_RTS__UART1_RTS, + MX50_PAD_UART2_TXD__UART2_TXD, + MX50_PAD_UART2_RXD__UART2_RXD, + MX50_PAD_UART2_CTS__UART2_CTS, + MX50_PAD_UART2_RTS__UART2_RTS, + + MX50_PAD_I2C1_SCL__I2C1_SCL, + MX50_PAD_I2C1_SDA__I2C1_SDA, + MX50_PAD_I2C2_SCL__I2C2_SCL, + MX50_PAD_I2C2_SDA__I2C2_SDA, + + /* EPDC pins */ + MX50_PAD_EPDC_D0__EPDC_D0, + MX50_PAD_EPDC_D1__EPDC_D1, + MX50_PAD_EPDC_D2__EPDC_D2, + MX50_PAD_EPDC_D3__EPDC_D3, + MX50_PAD_EPDC_D4__EPDC_D4, + MX50_PAD_EPDC_D5__EPDC_D5, + MX50_PAD_EPDC_D6__EPDC_D6, + MX50_PAD_EPDC_D7__EPDC_D7, + MX50_PAD_EPDC_GDCLK__EPDC_GDCLK, + MX50_PAD_EPDC_GDSP__EPDC_GDSP, + MX50_PAD_EPDC_GDOE__EPDC_GDOE , + MX50_PAD_EPDC_GDRL__EPDC_GDRL, + MX50_PAD_EPDC_SDCLK__EPDC_SDCLK, + MX50_PAD_EPDC_SDOE__EPDC_SDOE, + MX50_PAD_EPDC_SDLE__EPDC_SDLE, + MX50_PAD_EPDC_SDSHR__EPDC_SDSHR, + MX50_PAD_EPDC_BDR0__EPDC_BDR0, + MX50_PAD_EPDC_SDCE0__EPDC_SDCE0, + MX50_PAD_EPDC_SDCE1__EPDC_SDCE1, + MX50_PAD_EPDC_SDCE2__EPDC_SDCE2, + + MX50_PAD_EPDC_PWRSTAT__GPIO_3_28, + MX50_PAD_EPDC_VCOM0__GPIO_4_21, + + MX50_PAD_DISP_D8__DISP_D8, + MX50_PAD_DISP_D9__DISP_D9, + MX50_PAD_DISP_D10__DISP_D10, + MX50_PAD_DISP_D11__DISP_D11, + MX50_PAD_DISP_D12__DISP_D12, + MX50_PAD_DISP_D13__DISP_D13, + MX50_PAD_DISP_D14__DISP_D14, + MX50_PAD_DISP_D15__DISP_D15, + MX50_PAD_DISP_RS__ELCDIF_VSYNC, + + /* ELCDIF contrast */ + MX50_PAD_PWM1__PWMO, + + /* ELCDIF power on */ + MX50_PAD_DISP_CS__GPIO_2_21, + + MX50_PAD_DISP_BUSY__ELCDIF_HSYNC, + MX50_PAD_DISP_RD__ELCDIF_EN, + MX50_PAD_DISP_WR__ELCDIF_PIXCLK, + + /* EPD PMIC WAKEUP */ + MX50_PAD_UART4_TXD__GPIO_6_16, + + /* EPD PMIC intr */ + MX50_PAD_UART4_RXD__GPIO_6_17, + + MX50_PAD_EPITO__USBH1_PWR, + /* Need to comment below line if + * one needs to debug owire. + */ + MX50_PAD_OWIRE__USBH1_OC, + /* using gpio to control otg pwr */ + MX50_PAD_PWM2__GPIO_6_25, + MX50_PAD_I2C3_SCL__USBOTG_OC, + + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_SSI_RXC__FEC_MDIO, + MX50_PAD_DISP_D0__FEC_TXCLK, + MX50_PAD_DISP_D1__FEC_RX_ER, + MX50_PAD_DISP_D2__FEC_RX_DV, + MX50_PAD_DISP_D3__FEC_RXD1, + MX50_PAD_DISP_D4__FEC_RXD0, + MX50_PAD_DISP_D5__FEC_TX_EN, + MX50_PAD_DISP_D6__FEC_TXD1, + MX50_PAD_DISP_D7__FEC_TXD0, + MX50_PAD_SSI_RXFS__FEC_MDC, + MX50_PAD_I2C3_SDA__GPIO_6_23, + MX50_PAD_ECSPI1_SCLK__GPIO_4_12, + + MX50_PAD_CSPI_SS0__CSPI_SS0, + MX50_PAD_ECSPI1_MOSI__CSPI_SS1, + MX50_PAD_CSPI_MOSI__CSPI_MOSI, + MX50_PAD_CSPI_MISO__CSPI_MISO, + + /* SGTL500_OSC_EN */ + MX50_PAD_UART1_CTS__GPIO_6_8, + + /* SGTL_AMP_SHDN */ + MX50_PAD_UART3_RXD__GPIO_6_15, + + /* Keypad */ + MX50_PAD_KEY_COL0__KEY_COL0, + MX50_PAD_KEY_ROW0__KEY_ROW0, + MX50_PAD_KEY_COL1__KEY_COL1, + MX50_PAD_KEY_ROW1__KEY_ROW1, + MX50_PAD_KEY_COL2__KEY_COL2, + MX50_PAD_KEY_ROW2__KEY_ROW2, + MX50_PAD_KEY_COL3__KEY_COL3, + MX50_PAD_KEY_ROW3__KEY_ROW3, + MX50_PAD_EIM_DA0__KEY_COL4, + MX50_PAD_EIM_DA1__KEY_ROW4, + MX50_PAD_EIM_DA2__KEY_COL5, + MX50_PAD_EIM_DA3__KEY_ROW5, + MX50_PAD_EIM_DA4__KEY_COL6, + MX50_PAD_EIM_DA5__KEY_ROW6, + MX50_PAD_EIM_DA6__KEY_COL7, + MX50_PAD_EIM_DA7__KEY_ROW7, + /*EIM pads */ + MX50_PAD_EIM_DA8__GPIO_1_8, + MX50_PAD_EIM_DA9__GPIO_1_9, + MX50_PAD_EIM_DA10__GPIO_1_10, + MX50_PAD_EIM_DA11__GPIO_1_11, + MX50_PAD_EIM_DA12__GPIO_1_12, + MX50_PAD_EIM_DA13__GPIO_1_13, + MX50_PAD_EIM_DA14__GPIO_1_14, + MX50_PAD_EIM_DA15__GPIO_1_15, + MX50_PAD_EIM_CS2__GPIO_1_16, + MX50_PAD_EIM_CS1__GPIO_1_17, + MX50_PAD_EIM_CS0__GPIO_1_18, + MX50_PAD_EIM_EB0__GPIO_1_19, + MX50_PAD_EIM_EB1__GPIO_1_20, + MX50_PAD_EIM_WAIT__GPIO_1_21, + MX50_PAD_EIM_BCLK__GPIO_1_22, + MX50_PAD_EIM_RDY__GPIO_1_23, + MX50_PAD_EIM_OE__GPIO_1_24, + MX50_PAD_EIM_RW__GPIO_1_25, + MX50_PAD_EIM_LBA__GPIO_1_26, +}; + +static struct pad_desc mx50_gpmi_nand[] = { + MX50_PIN_EIM_DA8__NANDF_CLE, + MX50_PIN_EIM_DA9__NANDF_ALE, + MX50_PIN_EIM_DA10__NANDF_CE0, + MX50_PIN_EIM_DA11__NANDF_CE1, + MX50_PIN_EIM_DA12__NANDF_CE2, + MX50_PIN_EIM_DA13__NANDF_CE3, + MX50_PIN_EIM_DA14__NANDF_READY, + MX50_PIN_EIM_DA15__NANDF_DQS, + MX50_PIN_SD3_D4__NANDF_D0, + MX50_PIN_SD3_D5__NANDF_D1, + MX50_PIN_SD3_D6__NANDF_D2, + MX50_PIN_SD3_D7__NANDF_D3, + MX50_PIN_SD3_D0__NANDF_D4, + MX50_PIN_SD3_D1__NANDF_D5, + MX50_PIN_SD3_D2__NANDF_D6, + MX50_PIN_SD3_D3__NANDF_D7, + MX50_PIN_SD3_CLK__NANDF_RDN, + MX50_PIN_SD3_CMD__NANDF_WRN, + MX50_PIN_SD3_WP__NANDF_RESETN, +}; + +static struct pad_desc suspend_enter_pads[] = { + MX50_PAD_EIM_DA0__GPIO_1_0, + MX50_PAD_EIM_DA1__GPIO_1_1, + MX50_PAD_EIM_DA2__GPIO_1_2, + MX50_PAD_EIM_DA3__GPIO_1_3, + MX50_PAD_EIM_DA4__GPIO_1_4, + MX50_PAD_EIM_DA5__GPIO_1_5, + MX50_PAD_EIM_DA6__GPIO_1_6, + MX50_PAD_EIM_DA7__GPIO_1_7, + + MX50_PAD_EIM_DA8__GPIO_1_8, + MX50_PAD_EIM_DA9__GPIO_1_9, + MX50_PAD_EIM_DA10__GPIO_1_10, + MX50_PAD_EIM_DA11__GPIO_1_11, + MX50_PAD_EIM_DA12__GPIO_1_12, + MX50_PAD_EIM_DA13__GPIO_1_13, + MX50_PAD_EIM_DA14__GPIO_1_14, + MX50_PAD_EIM_DA15__GPIO_1_15, + MX50_PAD_EIM_CS2__GPIO_1_16, + MX50_PAD_EIM_CS1__GPIO_1_17, + MX50_PAD_EIM_CS0__GPIO_1_18, + MX50_PAD_EIM_EB0__GPIO_1_19, + MX50_PAD_EIM_EB1__GPIO_1_20, + MX50_PAD_EIM_WAIT__GPIO_1_21, + MX50_PAD_EIM_BCLK__GPIO_1_22, + MX50_PAD_EIM_RDY__GPIO_1_23, + MX50_PAD_EIM_OE__GPIO_1_24, + MX50_PAD_EIM_RW__GPIO_1_25, + MX50_PAD_EIM_LBA__GPIO_1_26, + MX50_PAD_EIM_CRE__GPIO_1_27, + + /* NVCC_NANDF pads */ + MX50_PAD_DISP_D8__GPIO_2_8, + MX50_PAD_DISP_D9__GPIO_2_9, + MX50_PAD_DISP_D10__GPIO_2_10, + MX50_PAD_DISP_D11__GPIO_2_11, + MX50_PAD_DISP_D12__GPIO_2_12, + MX50_PAD_DISP_D13__GPIO_2_13, + MX50_PAD_DISP_D14__GPIO_2_14, + MX50_PAD_DISP_D15__GPIO_2_15, + MX50_PAD_SD3_CMD__GPIO_5_18, + MX50_PAD_SD3_CLK__GPIO_5_19, + MX50_PAD_SD3_D0__GPIO_5_20, + MX50_PAD_SD3_D1__GPIO_5_21, + MX50_PAD_SD3_D2__GPIO_5_22, + MX50_PAD_SD3_D3__GPIO_5_23, + MX50_PAD_SD3_D4__GPIO_5_24, + MX50_PAD_SD3_D5__GPIO_5_25, + MX50_PAD_SD3_D6__GPIO_5_26, + MX50_PAD_SD3_D7__GPIO_5_27, + MX50_PAD_SD3_WP__GPIO_5_28, + + /* NVCC_LCD pads */ + MX50_PAD_DISP_D0__GPIO_2_0, + MX50_PAD_DISP_D1__GPIO_2_1, + MX50_PAD_DISP_D2__GPIO_2_2, + MX50_PAD_DISP_D3__GPIO_2_3, + MX50_PAD_DISP_D4__GPIO_2_4, + MX50_PAD_DISP_D5__GPIO_2_5, + MX50_PAD_DISP_D6__GPIO_2_6, + MX50_PAD_DISP_D7__GPIO_2_7, + MX50_PAD_DISP_WR__GPIO_2_16, + MX50_PAD_DISP_RS__GPIO_2_17, + MX50_PAD_DISP_BUSY__GPIO_2_18, + MX50_PAD_DISP_RD__GPIO_2_19, + MX50_PAD_DISP_RESET__GPIO_2_20, + MX50_PAD_DISP_CS__GPIO_2_21, + + /* CSPI pads */ + MX50_PAD_CSPI_SCLK__GPIO_4_8, + MX50_PAD_CSPI_MOSI__GPIO_4_9, + MX50_PAD_CSPI_MISO__GPIO_4_10, + MX50_PAD_CSPI_SS0__GPIO_4_11, + + /*NVCC_MISC pins as GPIO */ + MX50_PAD_I2C1_SCL__GPIO_6_18, + MX50_PAD_I2C1_SDA__GPIO_6_19, + MX50_PAD_I2C2_SCL__GPIO_6_20, + MX50_PAD_I2C2_SDA__GPIO_6_21, + MX50_PAD_I2C3_SCL__GPIO_6_22, + MX50_PAD_I2C3_SDA__GPIO_6_23, + + /* NVCC_MISC_PWM_USB_OTG pins */ + MX50_PAD_PWM1__GPIO_6_24, + MX50_PAD_PWM2__GPIO_6_25, + MX50_PAD_EPITO__GPIO_6_27, + MX50_PAD_WDOG__GPIO_6_28, + + /* FEC related. */ + MX50_PAD_EPDC_D10__GPIO_3_10, + MX50_PAD_SSI_RXC__GPIO_6_5, + MX50_PAD_SSI_RXFS__GPIO_6_4, +}; + +static struct pad_desc suspend_exit_pads[ARRAY_SIZE(suspend_enter_pads)]; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 80, + .num_wp = 2, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "SW1", + .lp_reg_id = "SW2", +}; + +/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1050000,}, + { + .pll_rate = 800000000, + .cpu_rate = 160000000, + .pdf = 4, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 4, + .cpu_voltage = 850000,}, +}; + +static struct cpu_wp *mx50_rdp_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_auto; +} + +static void mx50_rdp_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static u16 keymapping[] = { + KEY_9, KEY_0, KEY_O, KEY_P, KEY_L, KEY_DELETE, KEY_SLASH, KEY_ENTER, + KEY_F4, KEY_F1, KEY_F6, KEY_F9, KEY_F5, KEY_BACKSPACE, KEY_MENU, 0, + KEY_PREVIOUS, KEY_NEXT, KEY_HOME, KEY_NEXT, KEY_F2, KEY_F3, KEY_F8, KEY_F7, + KEY_F11, KEY_CAPSLOCK, KEY_SPACE, KEY_SPACE, KEY_LEFTALT, KEY_LEFTSHIFT, 0, 0, + KEY_COMMA, KEY_M, KEY_N, KEY_B, KEY_V, KEY_C, KEY_X, KEY_Z, + KEY_K, KEY_J, KEY_H, KEY_G, KEY_F, KEY_D, KEY_S, KEY_A, + KEY_I, KEY_U, KEY_Y, KEY_T, KEY_R, KEY_E, KEY_W, KEY_Q, + KEY_8, KEY_7, KEY_6, KEY_5, KEY_4, KEY_3, KEY_2, KEY_1 +}; + +static struct keypad_data keypad_plat_data = { + .rowmax = 8, + .colmax = 8, + .irq = MXC_INT_KPP, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + + +/* workaround for cspi chipselect pin may not keep correct level when idle */ +static void mx50_rdp_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + { + struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__CSPI_SS0; + struct pad_desc cspi_cs1 = + MX50_PAD_ECSPI1_MOSI__GPIO_4_13; + + /* pull up/down deassert it */ + mxc_iomux_v3_setup_pad(&cspi_ss0); + mxc_iomux_v3_setup_pad(&cspi_cs1); + + gpio_request(CSPI_CS1, "cspi-cs1"); + gpio_direction_input(CSPI_CS1); + } + break; + case 0x2: + { + struct pad_desc cspi_ss1 = + MX50_PAD_ECSPI1_MOSI__CSPI_SS1; + struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__GPIO_4_11; + + /*disable other ss */ + mxc_iomux_v3_setup_pad(&cspi_ss1); + mxc_iomux_v3_setup_pad(&cspi_ss0); + + /* pull up/down deassert it */ + gpio_request(CSPI_CS2, "cspi-cs2"); + gpio_direction_input(CSPI_CS2); + } + break; + default: + break; + } + break; + + default: + break; + } +} + +static void mx50_rdp_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + gpio_free(CSPI_CS1); + break; + case 0x2: + gpio_free(CSPI_CS2); + break; + default: + break; + } + break; + default: + break; + } + +} + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = mx50_rdp_gpio_spi_chipselect_active, + .chipselect_inactive = mx50_rdp_gpio_spi_chipselect_inactive, +}; + +static struct mxc_spi_master mxcspi3_data = { + .maxchipselect = 4, + .spi_version = 7, + .chipselect_active = mx50_rdp_gpio_spi_chipselect_active, + .chipselect_inactive = mx50_rdp_gpio_spi_chipselect_inactive, +}; + +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +static struct regulator_init_data max17135_init_data[] __initdata = { + { + .constraints = { + .name = "DISPLAY", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + }, { + .constraints = { + .name = "GVDD", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "GVEE", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINN", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINP", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "VCOM", + .min_uV = mV_to_uV(-4325), + .max_uV = mV_to_uV(-500), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + }, { + .constraints = { + .name = "VNEG", + .min_uV = V_to_uV(-15), + .max_uV = V_to_uV(-15), + }, + }, { + .constraints = { + .name = "VPOS", + .min_uV = V_to_uV(15), + .max_uV = V_to_uV(15), + }, + }, +}; + +/* Fixed voltage regulator DCDC_3V15 */ +static struct regulator_consumer_supply fixed_volt_reg_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDIO", + .dev_name = "1-000a", + }, +}; + +static struct regulator_init_data fixed_volt_reg_init_data = { + .constraints = { + .always_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(fixed_volt_reg_consumers), + .consumer_supplies = fixed_volt_reg_consumers, +}; + +static struct fixed_voltage_config fixed_volt_reg_pdata = { + .supply_name = "DCDC_3V15", + .microvolts = 3150000, + .init_data = &fixed_volt_reg_init_data, + .gpio = -EINVAL, +}; + +static void epdc_get_pins(void) +{ + /* Claim GPIOs for EPDC pins - used during power up/down */ + gpio_request(EPDC_D0, "epdc_d0"); + gpio_request(EPDC_D1, "epdc_d1"); + gpio_request(EPDC_D2, "epdc_d2"); + gpio_request(EPDC_D3, "epdc_d3"); + gpio_request(EPDC_D4, "epdc_d4"); + gpio_request(EPDC_D5, "epdc_d5"); + gpio_request(EPDC_D6, "epdc_d6"); + gpio_request(EPDC_D7, "epdc_d7"); + gpio_request(EPDC_GDCLK, "epdc_gdclk"); + gpio_request(EPDC_GDSP, "epdc_gdsp"); + gpio_request(EPDC_GDOE, "epdc_gdoe"); + gpio_request(EPDC_GDRL, "epdc_gdrl"); + gpio_request(EPDC_SDCLK, "epdc_sdclk"); + gpio_request(EPDC_SDOE, "epdc_sdoe"); + gpio_request(EPDC_SDLE, "epdc_sdle"); + gpio_request(EPDC_SDSHR, "epdc_sdshr"); + gpio_request(EPDC_BDR0, "epdc_bdr0"); + gpio_request(EPDC_SDCE0, "epdc_sdce0"); + gpio_request(EPDC_SDCE1, "epdc_sdce1"); + gpio_request(EPDC_SDCE2, "epdc_sdce2"); +} + +static void epdc_put_pins(void) +{ + gpio_free(EPDC_D0); + gpio_free(EPDC_D1); + gpio_free(EPDC_D2); + gpio_free(EPDC_D3); + gpio_free(EPDC_D4); + gpio_free(EPDC_D5); + gpio_free(EPDC_D6); + gpio_free(EPDC_D7); + gpio_free(EPDC_GDCLK); + gpio_free(EPDC_GDSP); + gpio_free(EPDC_GDOE); + gpio_free(EPDC_GDRL); + gpio_free(EPDC_SDCLK); + gpio_free(EPDC_SDOE); + gpio_free(EPDC_SDLE); + gpio_free(EPDC_SDSHR); + gpio_free(EPDC_BDR0); + gpio_free(EPDC_SDCE0); + gpio_free(EPDC_SDCE1); + gpio_free(EPDC_SDCE2); +} + +static struct pad_desc mx50_epdc_pads_enabled[] = { + MX50_PAD_EPDC_D0__EPDC_D0, + MX50_PAD_EPDC_D1__EPDC_D1, + MX50_PAD_EPDC_D2__EPDC_D2, + MX50_PAD_EPDC_D3__EPDC_D3, + MX50_PAD_EPDC_D4__EPDC_D4, + MX50_PAD_EPDC_D5__EPDC_D5, + MX50_PAD_EPDC_D6__EPDC_D6, + MX50_PAD_EPDC_D7__EPDC_D7, + MX50_PAD_EPDC_GDCLK__EPDC_GDCLK, + MX50_PAD_EPDC_GDSP__EPDC_GDSP, + MX50_PAD_EPDC_GDOE__EPDC_GDOE, + MX50_PAD_EPDC_GDRL__EPDC_GDRL, + MX50_PAD_EPDC_SDCLK__EPDC_SDCLK, + MX50_PAD_EPDC_SDOE__EPDC_SDOE, + MX50_PAD_EPDC_SDLE__EPDC_SDLE, + MX50_PAD_EPDC_SDSHR__EPDC_SDSHR, + MX50_PAD_EPDC_BDR0__EPDC_BDR0, + MX50_PAD_EPDC_SDCE0__EPDC_SDCE0, + MX50_PAD_EPDC_SDCE1__EPDC_SDCE1, + MX50_PAD_EPDC_SDCE2__EPDC_SDCE2, +}; + +static struct pad_desc mx50_epdc_pads_disabled[] = { + MX50_PAD_EPDC_D0__GPIO_3_0, + MX50_PAD_EPDC_D1__GPIO_3_1, + MX50_PAD_EPDC_D2__GPIO_3_2, + MX50_PAD_EPDC_D3__GPIO_3_3, + MX50_PAD_EPDC_D4__GPIO_3_4, + MX50_PAD_EPDC_D5__GPIO_3_5, + MX50_PAD_EPDC_D6__GPIO_3_6, + MX50_PAD_EPDC_D7__GPIO_3_7, + MX50_PAD_EPDC_GDCLK__GPIO_3_16, + MX50_PAD_EPDC_GDSP__GPIO_3_17, + MX50_PAD_EPDC_GDOE__GPIO_3_18, + MX50_PAD_EPDC_GDRL__GPIO_3_19, + MX50_PAD_EPDC_SDCLK__GPIO_3_20, + MX50_PAD_EPDC_SDOE__GPIO_3_23, + MX50_PAD_EPDC_SDLE__GPIO_3_24, + MX50_PAD_EPDC_SDSHR__GPIO_3_26, + MX50_PAD_EPDC_BDR0__GPIO_4_23, + MX50_PAD_EPDC_SDCE0__GPIO_4_25, + MX50_PAD_EPDC_SDCE1__GPIO_4_26, + MX50_PAD_EPDC_SDCE2__GPIO_4_27, +}; + +static void epdc_enable_pins(void) +{ + /* Configure MUX settings to enable EPDC use */ + mxc_iomux_v3_setup_multiple_pads(mx50_epdc_pads_enabled, \ + ARRAY_SIZE(mx50_epdc_pads_enabled)); + + gpio_direction_input(EPDC_D0); + gpio_direction_input(EPDC_D1); + gpio_direction_input(EPDC_D2); + gpio_direction_input(EPDC_D3); + gpio_direction_input(EPDC_D4); + gpio_direction_input(EPDC_D5); + gpio_direction_input(EPDC_D6); + gpio_direction_input(EPDC_D7); + gpio_direction_input(EPDC_GDCLK); + gpio_direction_input(EPDC_GDSP); + gpio_direction_input(EPDC_GDOE); + gpio_direction_input(EPDC_GDRL); + gpio_direction_input(EPDC_SDCLK); + gpio_direction_input(EPDC_SDOE); + gpio_direction_input(EPDC_SDLE); + gpio_direction_input(EPDC_SDSHR); + gpio_direction_input(EPDC_BDR0); + gpio_direction_input(EPDC_SDCE0); + gpio_direction_input(EPDC_SDCE1); + gpio_direction_input(EPDC_SDCE2); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to + * GPIO and drive to 0. */ + mxc_iomux_v3_setup_multiple_pads(mx50_epdc_pads_disabled, \ + ARRAY_SIZE(mx50_epdc_pads_disabled)); + + gpio_direction_output(EPDC_D0, 0); + gpio_direction_output(EPDC_D1, 0); + gpio_direction_output(EPDC_D2, 0); + gpio_direction_output(EPDC_D3, 0); + gpio_direction_output(EPDC_D4, 0); + gpio_direction_output(EPDC_D5, 0); + gpio_direction_output(EPDC_D6, 0); + gpio_direction_output(EPDC_D7, 0); + gpio_direction_output(EPDC_GDCLK, 0); + gpio_direction_output(EPDC_GDSP, 0); + gpio_direction_output(EPDC_GDOE, 0); + gpio_direction_output(EPDC_GDRL, 0); + gpio_direction_output(EPDC_SDCLK, 0); + gpio_direction_output(EPDC_SDOE, 0); + gpio_direction_output(EPDC_SDLE, 0); + gpio_direction_output(EPDC_SDSHR, 0); + gpio_direction_output(EPDC_BDR0, 0); + gpio_direction_output(EPDC_SDCE0, 0); + gpio_direction_output(EPDC_SDCE1, 0); + gpio_direction_output(EPDC_SDCE2, 0); +} + +static struct fb_videomode e60_v110_mode = { + .name = "E60_V110", + .refresh = 50, + .xres = 800, + .yres = 600, + .pixclock = 18604700, + .left_margin = 8, + .right_margin = 178, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct fb_videomode e60_v220_mode = { + .name = "E60_V220", + .refresh = 85, + .xres = 800, + .yres = 600, + .pixclock = 32000000, + .left_margin = 8, + .right_margin = 166, + .upper_margin = 4, + .lower_margin = 26, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct fb_videomode e97_v110_mode = { + .name = "E97_V110", + .refresh = 50, + .xres = 1200, + .yres = 825, + .pixclock = 32000000, + .left_margin = 12, + .right_margin = 128, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct mxc_epdc_fb_mode panel_modes[] = { + { + &e60_v110_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 428, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e60_v220_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 428, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e97_v110_mode, + 8, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 632, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 3, /* num_ce */ + } +}; + +static struct mxc_epdc_fb_platform_data epdc_data = { + .epdc_mode = panel_modes, + .num_modes = ARRAY_SIZE(panel_modes), + .get_pins = epdc_get_pins, + .put_pins = epdc_put_pins, + .enable_pins = epdc_enable_pins, + .disable_pins = epdc_disable_pins, +}; + +static struct platform_device max17135_sensor_device = { + .name = "max17135_sensor", + .id = 0, +}; + +static struct max17135_platform_data max17135_pdata __initdata = { + .vneg_pwrup = 1, + .gvee_pwrup = 1, + .vpos_pwrup = 2, + .gvdd_pwrup = 1, + .gvdd_pwrdn = 1, + .vpos_pwrdn = 2, + .gvee_pwrdn = 1, + .vneg_pwrdn = 1, + .gpio_pmic_pwrgood = EPDC_PWRSTAT, + .gpio_pmic_vcom_ctrl = EPDC_VCOM, + .gpio_pmic_wakeup = EPDC_PMIC_WAKE, + .gpio_pmic_intr = EPDC_PMIC_INT, + .regulator_init = max17135_init_data, + .init = max17135_regulator_init, +}; + +static int max17135_regulator_init(struct max17135 *max17135) +{ + struct max17135_platform_data *pdata = &max17135_pdata; + int i, ret; + + max17135->gvee_pwrup = pdata->gvee_pwrup; + max17135->vneg_pwrup = pdata->vneg_pwrup; + max17135->vpos_pwrup = pdata->vpos_pwrup; + max17135->gvdd_pwrup = pdata->gvdd_pwrup; + max17135->gvdd_pwrdn = pdata->gvdd_pwrdn; + max17135->vpos_pwrdn = pdata->vpos_pwrdn; + max17135->vneg_pwrdn = pdata->vneg_pwrdn; + max17135->gvee_pwrdn = pdata->gvee_pwrdn; + + max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup + + pdata->gvdd_pwrup + pdata->gvee_pwrup; + + max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood; + max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl; + max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup; + max17135->gpio_pmic_intr = pdata->gpio_pmic_intr; + + max17135->vcom_setup = false; + max17135->init_done = false; + + for (i = 0; i <= MAX17135_VPOS; i++) { + ret = max17135_register_regulator(max17135, i, + &pdata->regulator_init[i]); + if (ret != 0) { + printk(KERN_ERR"max17135 regulator init failed: %d\n", + ret); + return ret; + } + } + + regulator_has_full_constraints(); + + return 0; +} + +static struct imxi2c_platform_data mxci2c_data = { + .bitrate = 100000, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + I2C_BOARD_INFO("max17135", 0x48), + .platform_data = &max17135_pdata, + }, + { + .type = "mma8450", + .addr = 0x1c, + }, + { + .type = "eeprom", + .addr = 0x50, + }, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, +}; + +static struct mtd_partition mxc_dataflash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x000100000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, +}; + +static struct flash_platform_data mxc_spi_flash_data[] = { + { + .name = "mxc_dataflash", + .parts = mxc_dataflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), + .type = "at45db321d",} +}; + + +static struct spi_board_info mxc_dataflash_device[] __initdata = { + { + .modalias = "mxc_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 3, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[0],}, +}; + +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(SD1_WP); + else if (to_platform_device(dev)->id == 1) + rc = gpio_get_value(SD2_WP); + else if (to_platform_device(dev)->id == 2) + rc = 0; + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret = 0; + if (to_platform_device(dev)->id == 0) + ret = gpio_get_value(SD1_CD); + else if (to_platform_device(dev)->id == 1) + ret = gpio_get_value(SD2_CD); + else if (to_platform_device(dev)->id == 2) + ret = 1; + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = "VSD" +}; + +static struct mxc_mmc_platform_data mmc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static int mxc_sgtl5000_amp_enable(int enable) +{ + gpio_set_value(SGTL_AMP_SHDN, !enable); + return 0; +} + +static int mxc_sgtl5000_clock_enable(int enable) +{ + gpio_set_value(SGTL_OSCEN, enable); + return 0; +} + +static int headphone_det_status(void) +{ + return (gpio_get_value(HP_DETECT) == 0); +} + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_irq = IOMUX_TO_IRQ_V3(HP_DETECT), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .clock_enable = mxc_sgtl5000_clock_enable, + .sysclk = 12288000, +}; + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static struct pad_desc rdp_wvga_pads[] = { + MX50_PAD_DISP_D0__DISP_D0, + MX50_PAD_DISP_D1__DISP_D1, + MX50_PAD_DISP_D2__DISP_D2, + MX50_PAD_DISP_D3__DISP_D3, + MX50_PAD_DISP_D4__DISP_D4, + MX50_PAD_DISP_D5__DISP_D5, + MX50_PAD_DISP_D6__DISP_D6, + MX50_PAD_DISP_D7__DISP_D7, + MX50_PAD_EIM_DA0__GPIO_1_0, + MX50_PAD_EIM_DA1__GPIO_1_1, + MX50_PAD_EIM_DA2__GPIO_1_2, + MX50_PAD_EIM_DA3__GPIO_1_3, + MX50_PAD_EIM_DA4__GPIO_1_4, + MX50_PAD_EIM_DA5__GPIO_1_5, + MX50_PAD_EIM_DA6__GPIO_1_6, + MX50_PAD_EIM_DA7__GPIO_1_7, +}; + +static void wvga_reset(void) +{ + mxc_iomux_v3_setup_multiple_pads(rdp_wvga_pads, \ + ARRAY_SIZE(rdp_wvga_pads)); + + gpio_direction_output(FEC_EN, 1); + + gpio_request(ELCDIF_DAT0_DUMMY, "elcdif-data0"); + gpio_direction_output(ELCDIF_DAT0_DUMMY, 0); + gpio_request(ELCDIF_DAT1_DUMMY, "elcdif-data1"); + gpio_direction_output(ELCDIF_DAT1_DUMMY, 0); + gpio_request(ELCDIF_DAT2_DUMMY, "elcdif-data2"); + gpio_direction_output(ELCDIF_DAT2_DUMMY, 0); + gpio_request(ELCDIF_DAT8_DUMMY, "elcdif-data8"); + gpio_direction_output(ELCDIF_DAT8_DUMMY, 0); + gpio_request(ELCDIF_DAT9_DUMMY, "elcdif-data9"); + gpio_direction_output(ELCDIF_DAT9_DUMMY, 0); + gpio_request(ELCDIF_DAT16_DUMMY, "elcdif-data16"); + gpio_direction_output(ELCDIF_DAT16_DUMMY, 0); + gpio_request(ELCDIF_DAT17_DUMMY, "elcdif-data17"); + gpio_direction_output(ELCDIF_DAT17_DUMMY, 0); + + return; +} + +static struct mxc_lcd_platform_data lcd_wvga_data = { + .reset = wvga_reset, +}; + +static struct platform_device lcd_wvga_device = { + .name = "lcd_seiko", + .dev = { + .platform_data = &lcd_wvga_data, + }, +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 32MHz */ + "SEIKO-WVGA", 60, 800, 480, 29850, 99, 164, 33, 10, 10, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = V4L2_PIX_FMT_RGB565, + .mode_str = "SEIKO-WVGA", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 2000000, +}; + +static void mx50_arm2_usb_set_vbus(bool enable) +{ + gpio_set_value(USB_OTG_PWR, enable); +} + +static void mxc_register_powerkey(pwrkey_callback pk_cb) +{ + pmic_event_callback_t power_key_event; + + power_key_event.param = (void *)1; + power_key_event.func = (void *)pk_cb; + pmic_event_subscribe(EVENT_PWRONI, power_key_event); + power_key_event.param = (void *)3; + pmic_event_subscribe(EVENT_PWRON3I, power_key_event); +} + +static int mxc_pwrkey_getstatus(int id) +{ + int sense, off = 3; + + pmic_read_reg(REG_INT_SENSE1, &sense, 0xffffffff); + switch (id) { + case 2: + off = 4; + break; + case 3: + off = 2; + break; + } + + if (sense & (1 << off)) + return 0; + + return 1; +} + +static struct power_key_platform_data pwrkey_data = { + .key_value = KEY_F4, + .register_pwrkey = mxc_register_powerkey, + .get_key_status = mxc_pwrkey_getstatus, +}; + + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx50(); +} + +__setup("w1", w1_setup); + +static int __initdata enable_keypad = {0}; +static int __init keypad_setup(char *__unused) +{ + enable_keypad = 1; + return cpu_is_mx50(); +} + +__setup("keypad", keypad_setup); + +static struct mxs_dma_plat_data dma_apbh_data = { + .chan_base = MXS_DMA_CHANNEL_AHB_APBH, + .chan_num = MXS_MAX_DMA_CHANNELS, +}; + +static int gpmi_nfc_platform_init(unsigned int max_chip_count) +{ + mxc_iomux_v3_setup_multiple_pads(mx50_gpmi_nand, + ARRAY_SIZE(mx50_gpmi_nand)); + + return 0; +} + +static void gpmi_nfc_platform_exit(unsigned int max_chip_count) +{ +} + +static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; + +static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { + .nfc_version = 2, + .boot_rom_version = 1, + .clock_name = "gpmi-nfc", + .platform_init = gpmi_nfc_platform_init, + .platform_exit = gpmi_nfc_platform_exit, + .min_prop_delay_in_ns = 5, + .max_prop_delay_in_ns = 9, + .max_chip_count = 2, + .boot_area_size_in_bytes = 20 * SZ_1M, + .partition_source_types = gpmi_nfc_partition_source_types, + .partitions = 0, + .partition_count = 0, +}; + +static void fec_gpio_iomux_init() +{ + struct pad_desc iomux_setting = + MX50_PAD_I2C3_SDA__GPIO_6_23; + + /* Enable the Pull/keeper */ + iomux_setting.pad_ctrl = 0x84; + mxc_iomux_v3_setup_pad(&iomux_setting); + gpio_request(FEC_EN, "fec-en"); + gpio_direction_output(FEC_EN, 0); + gpio_request(FEC_RESET_B, "fec-reset_b"); + gpio_direction_output(FEC_RESET_B, 0); + udelay(500); + gpio_set_value(FEC_RESET_B, 1); +} + +static void fec_gpio_iomux_deinit() +{ + struct pad_desc iomux_setting = + MX50_PAD_I2C3_SDA__GPIO_6_23; + + /* Disable the Pull/keeper */ + iomux_setting.pad_ctrl = 0xE4; + mxc_iomux_v3_setup_pad(&iomux_setting); + gpio_request(FEC_EN, "fec-en"); + gpio_direction_input(FEC_EN); + gpio_request(FEC_RESET_B, "fec-reset_b"); + gpio_direction_input(FEC_RESET_B); +} + +static void mx50_suspend_enter() +{ + struct pad_desc *p = suspend_enter_pads; + int i; + /* Set PADCTRL to 0 for all IOMUX. */ + for (i = 0; i < ARRAY_SIZE(suspend_enter_pads); i++) { + suspend_exit_pads[i] = *p; + p->pad_ctrl = 0; + p++; + } + mxc_iomux_v3_get_multiple_pads(suspend_exit_pads, + ARRAY_SIZE(suspend_exit_pads)); + mxc_iomux_v3_setup_multiple_pads( + suspend_enter_pads, + ARRAY_SIZE(suspend_enter_pads)); + + fec_gpio_iomux_deinit(); +} + +static void mx50_suspend_exit() +{ + mxc_iomux_v3_setup_multiple_pads( + suspend_exit_pads, + ARRAY_SIZE(suspend_exit_pads)); + fec_gpio_iomux_init(); +} + +static struct mxc_pm_platform_data mx50_pm_data = { + .suspend_enter = mx50_suspend_enter, + .suspend_exit = mx50_suspend_exit, +}; + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_set_cpu_type(MXC_CPU_MX50); + + get_cpu_wp = mx50_rdp_get_cpu_wp; + set_num_cpu_wp = mx50_rdp_set_num_cpu_wp; +} + +static void __init mx50_rdp_io_init(void) +{ + struct pad_desc cspi_keeper = MX50_PAD_ECSPI1_SCLK__GPIO_4_12; + struct pad_desc *p = mx50_rdp; + int i; + + /* Set PADCTRL to 0 for all IOMUX. */ + for (i = 0; i < ARRAY_SIZE(mx50_rdp); i++) { + int pad_ctl = p->pad_ctrl; + p->pad_ctrl = 0; + mxc_iomux_v3_setup_pad(p); + p->pad_ctrl = pad_ctl; + p++; + } + + mxc_iomux_v3_setup_multiple_pads(mx50_rdp, \ + ARRAY_SIZE(mx50_rdp)); + + gpio_request(SD1_WP, "sdhc1-wp"); + gpio_direction_input(SD1_WP); + + gpio_request(SD1_CD, "sdhc1-cd"); + gpio_direction_input(SD1_CD); + + gpio_request(SD2_WP, "sdhc2-wp"); + gpio_direction_input(SD2_WP); + + gpio_request(SD2_CD, "sdhc2-cd"); + gpio_direction_input(SD2_CD); + + gpio_request(HP_DETECT, "hp-det"); + gpio_direction_input(HP_DETECT); + + gpio_request(PWR_INT, "pwr-int"); + gpio_direction_input(PWR_INT); + + gpio_request(EPDC_PMIC_WAKE, "epdc-pmic-wake"); + gpio_direction_output(EPDC_PMIC_WAKE, 0); + + gpio_request(EPDC_VCOM, "epdc-vcom"); + gpio_direction_output(EPDC_VCOM, 0); + + gpio_request(EPDC_PMIC_INT, "epdc-pmic-int"); + gpio_direction_input(EPDC_PMIC_INT); + + gpio_request(EPDC_PWRSTAT, "epdc-pwrstat"); + gpio_direction_input(EPDC_PWRSTAT); + + gpio_request(ELCDIF_PWR_ON, "elcdif-power-on"); + gpio_direction_output(ELCDIF_PWR_ON, 1); + + if (enable_w1) { + struct pad_desc one_wire = MX50_PAD_OWIRE__OWIRE; + mxc_iomux_v3_setup_pad(&one_wire); + } + + /* SGTL5000_OSC_EN */ + gpio_request(SGTL_OSCEN, "sgtl5000-osc-en"); + gpio_direction_output(SGTL_OSCEN, 1); + + gpio_request(SGTL_AMP_SHDN, "sgtl5000-amp-shdn"); + gpio_direction_output(SGTL_AMP_SHDN, 1); + + fec_gpio_iomux_init(); + + /* USB OTG PWR */ + gpio_request(USB_OTG_PWR, "usb otg power"); + gpio_direction_output(USB_OTG_PWR, 0); + + cspi_keeper.pad_ctrl = 0x0; /* Disable all keepers */ + mxc_iomux_v3_setup_pad(&cspi_keeper); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + /* SD card detect irqs */ + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(SD1_CD); + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(SD2_CD); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(SD2_CD); + + mxc_cpu_common_init(); + mx50_rdp_io_init(); + + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxcspi3_device, &mxcspi3_data); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxs_dma_apbh_device, &dma_apbh_data); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_devices[2], &mxci2c_data); + + mxc_register_device(&mxc_rtc_device, NULL); + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&gpu_device, &z160_revision); + mxc_register_device(&mxc_pxp_device, NULL); + mxc_register_device(&mxc_pxp_client_device, NULL); + mxc_register_device(&mxc_pxp_v4l2, NULL); + mxc_register_device(&busfreq_device, &bus_freq_data); + mxc_register_device(&pm_device, &mx50_pm_data); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + + if (enable_keypad) + mxc_register_device(&mxc_keypad_device, &keypad_plat_data); + + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&mxc_fec_device, &fec_data); + spi_register_board_info(mxc_dataflash_device, + ARRAY_SIZE(mxc_dataflash_device)); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + + mxc_register_device(&max17135_sensor_device, NULL); + mxc_register_device(&epdc_device, &epdc_data); + mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); + mxc_register_device(&elcdif_device, &fb_data[0]); + mxc_register_device(&mxc_pwm1_device, NULL); + mxc_register_device(&mxc_pwm1_backlight_device, + &mxc_pwm_backlight_data); + mxc_register_device(&mxs_viim, NULL); + mxc_register_device(&mxc_rngb_device, NULL); + mxc_register_device(&dcp_device, NULL); + mxc_register_device(&mxc_powerkey_device, &pwrkey_data); + mxc_register_device(&fixed_volt_reg_device, &fixed_volt_reg_pdata); + if (cpu_is_mx50_rev(CHIP_REV_1_1) >= 1) + mxc_register_device(&mxc_zq_calib_device, NULL); + mx50_rdp_init_mc13892(); +/* + pm_power_off = mxc_power_off; + */ + mx5_set_otghost_vbus_func(mx50_arm2_usb_set_vbus); + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mxc_register_device(&gpmi_nfc_device, &gpmi_nfc_platform_data); + mx5_usb_dr_init(); + mx5_usbh1_init(); + mxc_register_device(&mxc_perfmon, &mxc_perfmon_data); +} + +static void __init mx50_rdp_timer_init(void) +{ + struct clk *uart_clk; + + mx50_clocks_init(32768, 24000000, 22579200); + + uart_clk = clk_get_sys("mxcintuart.0", NULL); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx50_rdp_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX50_RDP data structure. + */ +MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c b/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c new file mode 100644 index 000000000000..883108a2b53a --- /dev/null +++ b/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c @@ -0,0 +1,435 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +/* Coin cell charger enable */ +#define COINCHEN_LSH 23 +#define COINCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* regulator standby mask */ +#define GEN1_STBY_MASK (1 << 1) +#define IOHI_STBY_MASK (1 << 4) +#define DIG_STBY_MASK (1 << 10) +#define GEN2_STBY_MASK (1 << 13) +#define PLL_STBY_MASK (1 << 16) +#define USB2_STBY_MASK (1 << 19) + +#define GEN3_STBY_MASK (1 << 1) +#define CAM_STBY_MASK (1 << 7) +#define VIDEO_STBY_MASK (1 << 13) +#define AUDIO_STBY_MASK (1 << 16) +#define SD_STBY_MASK (1 << 19) + +#define REG_MODE_0_ALL_MASK (DIG_STBY_MASK | GEN1_STBY_MASK\ + | PLL_STBY_MASK | IOHI_STBY_MASK) +#define REG_MODE_1_ALL_MASK (CAM_STBY_MASK | VIDEO_STBY_MASK |\ + AUDIO_STBY_MASK | SD_STBY_MASK | GEN3_STBY_MASK) + +/* switch mode setting */ +#define SW1MODE_LSB 0 +#define SW2MODE_LSB 10 +#define SW3MODE_LSB 0 +#define SW4MODE_LSB 8 + +#define SWMODE_MASK 0xF +#define SWMODE_AUTO 0x8 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +static struct regulator_consumer_supply sw4_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDA", + .dev_name = "1-000a", + }, +}; + +static struct regulator_consumer_supply vgen1_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDIO", + .dev_name = "1-000a", + }, +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(sw4_consumers), + .consumer_supplies = sw4_consumers, +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1200), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2775), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .apply_uV = 1, + }, +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(3000), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value, register_mask; + printk("Initializing regulators for mx50 rdp.\n"); + + /* enable standby controll for all regulators */ + pmic_read_reg(REG_MODE_0, &value, 0xffffff); + value |= REG_MODE_0_ALL_MASK; + pmic_write_reg(REG_MODE_0, value, 0xffffff); + + pmic_read_reg(REG_MODE_1, &value, 0xffffff); + value |= REG_MODE_1_ALL_MASK; + pmic_write_reg(REG_MODE_1, value, 0xffffff); + + /* enable switch audo mode */ + pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff); + /* only for mc13892 2.0A */ + if ((value & 0x0000FFFF) == 0x45d0) { + pmic_read_reg(REG_SW_4, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW1MODE_LSB) | + (SWMODE_MASK << SW2MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW1MODE_LSB) | + (SWMODE_AUTO << SW2MODE_LSB); + pmic_write_reg(REG_SW_4, value, 0xffffff); + + pmic_read_reg(REG_SW_5, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW3MODE_LSB) | + (SWMODE_MASK << SW4MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW3MODE_LSB) | + (SWMODE_AUTO << SW4MODE_LSB); + pmic_write_reg(REG_SW_5, value, 0xffffff); + } + /* Enable coin cell charger */ + value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); + register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + + regulator_has_full_constraints(); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct spi_board_info __initdata mc13892_spi_device = { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ_V3(114), + .max_speed_hz = 6000000, /* max spi SCK clock speed in HZ */ + .bus_num = 3, + .chip_select = 0, + .platform_data = &mc13892_plat, +}; + + +int __init mx50_rdp_init_mc13892(void) +{ + return spi_register_board_info(&mc13892_spi_device, 1); +} diff --git a/arch/arm/mach-mx5/mx50_suspend.S b/arch/arm/mach-mx5/mx50_suspend.S new file mode 100644 index 000000000000..4d9e1b49a23d --- /dev/null +++ b/arch/arm/mach-mx5/mx50_suspend.S @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +#define ARM_CTRL_DCACHE 1 << 2 +#define ARM_CTRL_ICACHE 1 << 12 +#define ARM_AUXCR_L2EN 1 << 1 + +/* + * mx50_suspend + * + * Suspend the processor (eg, wait for interrupt). + * Set the DDR into Self Refresh + * IRQs are already disabled. + */ +ENTRY(mx50_suspend) + stmfd sp!, {r4,r5,r6,r7,r8, r9,r10,r11} @ Save registers + + mov r6, r0 @save databahn address + +/* Before putting DDR into self-refresh, make sure + any LPM mode that the DDR might be in is exited. +*/ + /* If Databahn is in LPM4, exit that mode first. */ + ldr r8,[r6, #0x50] @Store LPM mode in r8 + mov r0, r8 + bic r0, r0, #0x1F + str r0,[r6, #0x50] + + + /* Disable L1 caches */ + mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg + bic r0, r0, #ARM_CTRL_ICACHE @ Disable ICache + bic r0, r0, #ARM_CTRL_DCACHE @ Disable DCache + mcr p15, 0, r0, c1, c0, 0 @ Update system control reg + + mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR + ands r3, r0, #0x7000000 @ Isolate level of coherency + mov r3, r3, lsr #23 @ Cache level value (naturally aligned) + beq FinishedClean + mov r10, #0 +Loop1Clean: + add r2, r10, r10, lsr #1 @ Work out cache level + mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache Type + @ for this level + and r1, r1, #7 @ Get those 3 bits alone + cmp r1, #2 + blt SkipClean @ No cache or only instruction cache + @ at this level + mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register + mov r1, #0 + .long 0xF57FF06F @ ISB + mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register + and r2, r1, #7 @ Extract the line length field + add r2, r2, #4 @ Add 4 for the line length offset + @ (log2 16 bytes) + ldr r4, =0x3FF + ands r4, r4, r1, lsr #3 @ R4 is the max number on the + @ way size (right aligned) + clz r5, r4 @ R5 is the bit position of the way + @ size increment + ldr r7, =0x00007FFF + ands r7, r7, r1, lsr #13 @ R7 is the max number of the index + @ size (right aligned) +Loop2Clean: + mov r9, r4 @ R9 working copy of the max way size + @ (right aligned) +Loop3Clean: + orr r11, r10, r9, lsl r5 @ Factor in the way number and cache + @ number into R11 + orr r11, r11, r7, lsl r2 @ Factor in the index number + mcr p15, 0, r11, c7, c14, 2 @ Clean and invalidate by set/way + subs r9, r9, #1 @ Decrement the way number + bge Loop3Clean + subs r7, r7, #1 @ Decrement the index + bge Loop2Clean +SkipClean: + add r10, r10, #2 @ Increment the cache number + cmp r3, r10 + bgt Loop1Clean + +FinishedClean: + + /* Disable L2 cache */ + mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg + bic r0, r0, #ARM_AUXCR_L2EN @ Disable L2 cache + mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg + +/* Wait for the databahn to idle + Meaning, no access to the databahn is + being made. +*/ +EnterWFI: + ldr r0,[r6, #0x13c] + and r0, r0, #0x100 + ldr r2, =0x100 + cmp r0, r2 + beq EnterWFI + + /* Enter self-refresh mode */ + ldr r0,[r6, #0x4c] + orr r0,r0,#0x1 + str r0,[r6, #0x4c] + +LoopCKE0: + /* Wait for CKE = 0 */ + ldr r0,[r6, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + beq LoopCKE0 + + /* Stop controller */ + ldr r0,[r6] + bic r0, r0, #0x1 + str r0,[r6] + + .long 0xe320f003 @ Opcode for WFI + + /* Start controller */ + ldr r0,[r6] + orr r0,r0,#0x1 + str r0,[r6] + +LoopPHY: + /* Wait for PHY ready */ + ldr r0,[r6, #0x264] + and r0, r0, #0xfffffffe + ldr r2, =0x0 + cmp r0, r2 + beq LoopPHY + + /*Leave self-refresh mode */ + ldr r0,[r6, #0x4c] + and r0,r0,#0xfffffffe + str r0,[r6, #0x4c] + +LoopCKE1: + /*Wait for CKE = 1 */ + ldr r0,[r6, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + bne LoopCKE1 + + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate inst cache + +/* Invalidate data caches */ + mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR + ands r3, r0, #0x7000000 @ Isolate level of coherency + mov r3, r3, lsr #23 @ Cache level value (naturally aligned) + beq FinishedInvalidate + mov r10, #0 +Loop1Invalidate: + add r2, r10, r10, lsr #1 @ Work out cache level + mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache + @ Type for this level + and r1, r1, #7 @ Get those 3 bits alone + cmp r1, #2 + blt SkipInvalidate @ No cache or only instruction cache + @at this level + mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register + mov r1, #0 + .long 0xF57FF06F @ ISB + mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register + and r2, r1, #7 @ Extract the line length field + add r2, r2, #4 @ Add 4 for the line length offset + @(log2 16 bytes) + ldr r4, =0x3FF + ands r4, r4, r1, lsr #3 @ R4 is the max number on the way + @size (right aligned) + clz r5, r4 @ R5 is the bit position of the way + @ size increment + ldr r7, =0x00007FFF + ands r7, r7, r1, lsr #13 @ R7 is the max number of the + @ index size (right aligned) +Loop2Invalidate: + mov r9, r4 @ R9 working copy of the max way + @ size (right aligned) +Loop3Invalidate: + orr r11, r10, r9, lsl r5 @ Factor in the way number and cache + @ number into R11 + orr r11, r11, r7, lsl r2 @ Factor in the index number + mcr p15, 0, r11, c7, c6, 2 @ Invalidate by set/way + subs r9, r9, #1 @ Decrement the way number + bge Loop3Invalidate + subs r7, r7, #1 @ Decrement the index + bge Loop2Invalidate +SkipInvalidate: + add r10, r10, #2 @ Increment the cache number + cmp r3, r10 + bgt Loop1Invalidate + +FinishedInvalidate: + + /* Enable L2 cache */ + mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg + orr r0, r0, #ARM_AUXCR_L2EN @ Enable L2 cache + mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg + + /* Enable L1 caches */ + mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg + orr r0, r0, #ARM_CTRL_ICACHE @ Enable ICache + orr r0, r0, #ARM_CTRL_DCACHE @ Enable DCache + mcr p15, 0, r0, c1, c0, 0 @ Update system control reg + + /* restore LPM mode. */ + str r8, [r6, #0x50] + + /* Restore registers */ + ldmfd sp!, {r4,r5,r6,r7,r8,r9,r10,r11} + mov pc, lr + + .type mx50_do_suspend, #object +ENTRY(mx50_do_suspend) + .word mx50_suspend + .size mx50_suspend, . - mx50_suspend diff --git a/arch/arm/mach-mx5/mx50_wfi.S b/arch/arm/mach-mx5/mx50_wfi.S new file mode 100644 index 000000000000..3335b0f320a4 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_wfi.S @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +/* + * mx50_wait + * + * Idle the processor (eg, wait for interrupt). + * Make sure DDR is in self-refresh. + * IRQs are already disabled. + */ +ENTRY(mx50_wait) + stmfd sp!, {r3,r4,r5,r6,r7,r8,r9,r10,r11} @ Save registers + + mov r6, r0 @save CCM address + mov r5, r1 @save DataBahn address + + /* + * Make sure the DDR is self-refresh, before setting the clock bits. + */ + + /* Step 2: Poll the CKE_STATUS bit. */ +LoopCKE0: + /* Wait for CKE = 0 */ + ldr r0,[r5, #0xfc] + and r0, r0, #0x10000 + ldr r2, =0x10000 + cmp r0, r2 + beq LoopCKE0 + + /* Check if Databahn is in SYNC or ASYNC mode. */ + ldr r4, [r5, #0xdc] + and r4, r4, #0x30000 + cmp r4, #0x30000 + beq Sync_mode + + /* Set the DDR_CLKGATE to 0x1. */ + ldr r0, [r6, #0x98] + bic r0, r0, #0x80000000 + str r0, [r6, #0x98] + + .long 0xe320f003 @ Opcode for WFI + + /* Set the DDR_CLKGATE to 0x3. */ + ldr r0, [r6, #0x98] + orr r0, r0, #0xC0000000 + str r0, [r6, #0x98] + b Wfi_Done + +Sync_mode: + /* Check if PLL1 is sourcing SYS_CLK. */ + ldr r5, [r6, #0x90] + and r5, r0, #0x1 + cmp r5, #0x1 + beq pll1_source + + /* Set the SYS_XTAL_CLKGATE to 0x1. */ + ldr r0, [r6, #0x94] + bic r0, r0, #0x80000000 + str r0, [r6, #0x94] + + /* Set the SYS_XTAL_DIV to 0xF (1.6MHz) to reduce power. + * since this clock is not gated when ARM is in WFI. + */ + + ldr r0, [r6, #0x94] + orr r0, r0, #0x3c0 + str r0, [r6, #0x94] + + b do_wfi +pll1_source: + /* Set the SYS_PLL_CLKGATE to 0x1. */ + ldr r0, [r6, #0x94] + bic r0, r0, #0x40000000 + str r0, [r6, #0x94] + +do_wfi: + .long 0xe320f003 @ Opcode for WFI + + cmp r5, #1 + beq pll1_source1 + /* Set the SYS_XTAL_DIV to 24MHz.*/ + ldr r0, [r6, #0x94] + bic r0, r0, #0x3c0 + orr r0, r0, #0x40 + str r0, [r6, #0x94] + + /* Set the SYS_XTAL_CLKGATE to 0x3. */ + ldr r0, [r6, #0x94] + orr r0, r0, #0xC0000000 + str r0, [r6, #0x94] + b Wfi_Done + +pll1_source1: + /* Set the SYS_PLL_CLKGATE to 0x3. */ + ldr r0, [r6, #0x94] + orr r0, r0, #0x30000000 + str r0, [r6, #0x94] + +Wfi_Done: + /* Restore registers */ + ldmfd sp!, {r3,r4,r5,r6,r7,r8,r9,r10,r11} + mov pc, lr + + .type mx50_do_wait, #object +ENTRY(mx50_do_wait) + .word mx50_wait + .size mx50_wait, . - mx50_wait diff --git a/arch/arm/mach-mx5/mx51_3stack.c b/arch/arm/mach-mx5/mx51_3stack.c new file mode 100644 index 000000000000..3188cc77bf45 --- /dev/null +++ b/arch/arm/mach-mx5/mx51_3stack.c @@ -0,0 +1,1078 @@ +/* + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) +#include +#include +#include + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "iomux.h" +#include "mx51_pins.h" +#include "crm_regs.h" +#include "usb.h" + +/*! + * @file mach-mx51/mx51_3stack.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX51 + */ +#define DEBUG_BOARD_BASE_ADDRESS(n) (n) +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR(n) (DEBUG_BOARD_BASE_ADDRESS(n)) + +#define BOARD_IO_ADDR(n) (DEBUG_BOARD_BASE_ADDRESS(n) + 0x20000) +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +/* interrupts like external uart , external ethernet etc*/ +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX51_PIN_GPIO1_6) + +#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0) +#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1) +#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2) +#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3) +#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4) + +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START) + +/*! This is System IRQ used by LAN9217 */ +#define LAN9217_IRQ EXPIO_INT_ENET + +extern int __init mx51_3stack_init_mc13892(void); +extern void __init mx51_3stack_io_init(void); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +static int num_cpu_wp = 3; +static bool debug_board_present; + +/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 1000000000, + .cpu_rate = 1000000000, + .pdf = 0, + .mfi = 10, + .mfd = 11, + .mfn = 5, + .cpu_podf = 0, + .cpu_voltage = 1175000,}, + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1100000,}, + { + .pll_rate = 800000000, + .cpu_rate = 166250000, + .pdf = 4, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 4, + .cpu_voltage = 850000,}, +}; + +struct cpu_wp *mx51_3stack_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_auto; +} + +void mx51_3stack_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static u16 keymapping[24] = { + KEY_1, KEY_2, KEY_3, KEY_F1, KEY_UP, KEY_F2, + KEY_4, KEY_5, KEY_6, KEY_LEFT, KEY_SELECT, KEY_RIGHT, + KEY_7, KEY_8, KEY_9, KEY_F3, KEY_DOWN, KEY_F4, + KEY_0, KEY_OK, KEY_ESC, KEY_ENTER, KEY_MENU, KEY_BACK, +}; + +static struct keypad_data keypad_plat_data = { + .rowmax = 4, + .colmax = 6, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + +static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 78770, +}; + +extern void mx5_ipu_reset(void); +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 2, + .reset = mx5_ipu_reset, +}; + +extern void mx5_vpu_reset(void); +static struct mxc_vpu_platform_data mxc_vpu_data = { + .reset = mx5_vpu_reset, +}; + +/* workaround for ecspi chipselect pin may not keep correct level when idle */ +static void mx51_3ds_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + u32 gpio; + + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + mxc_request_iomux(MX51_PIN_CSPI1_SS0, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, + PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + break; + case 0x2: + gpio = IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0); + mxc_request_iomux(MX51_PIN_CSPI1_SS0, + IOMUX_CONFIG_GPIO); + gpio_request(gpio, "cspi1_ss0"); + gpio_direction_output(gpio, 0); + gpio_set_value(gpio, 1 & (~status)); + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static void mx51_3ds_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_CSPI1_SS0, + IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + break; + case 0x2: + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = mx51_3ds_gpio_spi_chipselect_active, + .chipselect_inactive = mx51_3ds_gpio_spi_chipselect_inactive, +}; + +static struct imxi2c_platform_data mxci2c_data = { + .bitrate = 100000, +}; + +static struct mxc_i2c_platform_data mxci2c_hs_data = { + .i2c_clk = 400000, +}; + +static struct tve_platform_data tve_data = { + .dac_reg = "VVIDEO", + .dig_reg = "VDIG", +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, + .num_wp = 3, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "SW1", + .lp_reg_id = "SW2", +}; + +static struct mxc_dvfsper_data dvfs_per_data = { + .reg_id = "SW2", + .clk_id = "gpc_dvfs_clk", + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .gpc_adu = 0x0, + .vai_mask = MXC_DVFSPMCR0_FSVAI_MASK, + .vai_offset = MXC_DVFSPMCR0_FSVAI_OFFSET, + .dvfs_enable_bit = MXC_DVFSPMCR0_DVFEN, + .irq_mask = MXC_DVFSPMCR0_FSVAIM, + .div3_offset = 0, + .div3_mask = 0x7, + .div3_div = 2, + .lp_high = 1250000, + .lp_low = 1250000, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 0, + .spdif_clk_44100 = 0, /* spdif_ext_clk source for 44.1KHz */ + .spdif_clk_48000 = 7, /* audio osc source */ + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + + +/* NAND Flash Partitions */ +#ifdef CONFIG_MTD_PARTITIONS + +static struct mtd_partition nand_flash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 3 * 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs1", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; + +#endif + +extern void gpio_nand_active(void); +extern void gpio_nand_inactive(void); + +static int nand_init(void) +{ + /* Configure the pins */ + gpio_nand_active(); + return 0; +} + +static void nand_exit(void) +{ + /* Free the pins */ + gpio_nand_inactive(); +} + +static struct flash_platform_data mxc_nand_data = { + #ifdef CONFIG_MTD_PARTITIONS + .parts = nand_flash_partitions, + .nr_parts = ARRAY_SIZE(nand_flash_partitions), + #endif + .width = 1, + .init = nand_init, + .exit = nand_exit, +}; + +/* i.MX MTD NAND Flash Controller */ + +#if defined(CONFIG_MTD_NAND_IMX_NFC) || defined(CONFIG_MTD_NAND_IMX_NFC_MODULE) + +/* + * Platform-specific information about this device. Some of the details depend + * on the SoC. See imx_init_nfc() below for code that fills in the rest. + */ + +static struct imx_nfc_platform_data imx_nfc_platform_data = { + .nfc_major_version = 3, + .nfc_minor_version = 2, + .force_ce = false, + .target_cycle_in_ns = 30, + .clock_name = "nfc_clk", + .set_page_size = 0, + .interleave = false, + #ifdef CONFIG_MTD_PARTITIONS + .partitions = nand_flash_partitions, + .partition_count = ARRAY_SIZE(nand_flash_partitions), + #endif +}; + +#endif /* i.MX MTD NAND Flash Controller */ + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = IPU_PIX_FMT_RGB666, + }, + { + .interface_pix_fmt = IPU_PIX_FMT_YUV444, + }, +}; + +static void lcd_reset_to2(void) +{ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0); + ipu_reset_disp_panel(); + + return; +} + +static void lcd_reset(void) +{ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), 0); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), "ser_rs"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), 0); + /* do reset */ + msleep(10); /* tRES >= 100us */ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), 1); + msleep(60); +} + +static struct mxc_lcd_platform_data lcd_data = { + .core_reg = "VIOHI", + .io_reg = "SW4", + .reset = lcd_reset, +}; + +static struct platform_device mxc_lcd_device = { + .name = "lcd_spi", +}; + +static void wvga_reset(void) +{ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 1); +} + +static struct mxc_lcd_platform_data lcd_wvga_data = { + .reset = wvga_reset, +}; + +static struct platform_device lcd_wvga_device = { + .name = "lcd_claa", +}; + +static struct platform_device mxcbl_device = { + .name = "mxc_mc13892_bl", +}; + +static void si4702_reset(void) +{ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_DTACK), 0); + msleep(100); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_DTACK), 1); + msleep(100); +} + +static void si4702_clock_ctl(int flag) +{ +} + +static void si4702_gpio_get(void) +{ + /* reset pin */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_DTACK), "eim_dtack"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_DTACK), 0); +} + +static void si4702_gpio_put(void) +{ +} + +static struct mxc_fm_platform_data si4702_data = { + .reg_vio = "SW4", + .reg_vdd = "VIOHI", + .gpio_get = si4702_gpio_get, + .gpio_put = si4702_gpio_put, + .reset = si4702_reset, + .clock_ctl = si4702_clock_ctl, + .sksnr = 0, + .skcnt = 0, + .band = 0, + .space = 100, + .seekth = 0xa, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "wm8903-i2c", + .addr = 0x1a, + }, + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "tsc2007", + .addr = 0x48, + .irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_5), + }, + { + .type = "si4702", + .addr = 0x10, + .platform_data = (void *)&si4702_data, + }, +}; + +static struct mxc_camera_platform_data camera_data = { + .io_regulator = "SW4", + .analog_regulator = "VIOHI", + .mclk = 24000000, + .csi = 0, +}; +static struct mxc_lightsensor_platform_data ls_data = { + .vdd_reg = NULL, + .rext = 100, +}; + +static struct i2c_board_info mxc_i2c_hs_board_info[] __initdata = { + { + .type = "ov3640", + .addr = 0x3C, + .platform_data = (void *)&camera_data, + }, + { + .type = "isl29003", + .addr = 0x44, + .platform_data = &ls_data, + }, +}; + +static struct resource smsc911x_resources[] = { + { + .start = CS5_BASE_ADDR, + .end = CS5_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = LAN9217_IRQ, + .end = LAN9217_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, +}; + +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static struct mxc_sim_platform_data sim_data = { + .clk_rate = 4000000, + .clock_sim = "sim_clk", + .power_sim = NULL, + .init = NULL, + .exit = NULL, + .detect = 0, +}; + +/*! + * Get WP pin value to detect write protection + */ +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); + else + rc = 0; + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret; + + if (to_platform_device(dev)->id == 0) { + ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); + return ret; + } else { /* config the det pin for SDHC2 */ + return 0; + } +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_32_33, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 52000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static u32 brd_io; +static void expio_ack_irq(u32 irq); + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr_val; + u32 int_valid; + u32 expio_irq; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + imr_val = __raw_readw(brd_io + INTR_MASK_REG); + int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; + + if (unlikely(!int_valid)) + goto out; + + expio_irq = MXC_BOARD_IRQ_START; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + struct irq_desc *d; + if ((int_valid & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) { + printk(KERN_ERR "\nEXPIO irq: %d unhandled\n", + expio_irq); + BUG(); /* oops */ + } + d->handle_irq(expio_irq, d); + } + + out: + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* mask the interrupt */ + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg |= (1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* clear the interrupt status */ + __raw_writew(1 << expio, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + /* mask the interrupt */ + expio_mask_irq(irq); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + /* unmask the interrupt */ + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg &= ~(1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +static int __init mxc_expio_init(void) +{ + int i; + + brd_io = (u32) ioremap(BOARD_IO_ADDR(CS5_BASE_ADDR), SZ_4K); + if (brd_io == 0) + return -ENOMEM; + + if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { + pr_info("3-Stack Debug board not detected \n"); + return -ENODEV; + } else { + debug_board_present = true; + } + + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", + readw(brd_io + CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6), "gpio1_6"); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6)); + + /* disable the interrupt and clear the status */ + __raw_writew(0, brd_io + INTR_MASK_REG); + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + __raw_writew(0x1F, brd_io + INTR_MASK_REG); + for (i = MXC_BOARD_IRQ_START; i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(EXPIO_PARENT_INT, IRQF_TRIGGER_LOW); + set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler); + + return 0; +} + +extern void gpio_ata_active(void); +extern void gpio_ata_inactive(void); + +static int ata_init(struct platform_device *pdev) +{ + /* Configure the pins */ + gpio_ata_active(); + return 0; +} + +static void ata_exit(void) +{ + /* Free the pins */ + gpio_ata_inactive(); +} + +static struct fsl_ata_platform_data ata_data = { + .udma_mask = ATA_UDMA3, + .mwdma_mask = ATA_MWDMA2, + .pio_mask = ATA_PIO4, + .fifo_alarm = MXC_IDE_DMA_WATERMARK / 2, + .max_sg = MXC_IDE_DMA_BD_NR, + .init = ata_init, + .exit = ata_exit, + .core_reg = NULL, + .io_reg = NULL, +}; + +static struct platform_device mxc_wm8903_device = { + .name = "imx-3stack-wm8903", + .id = 0, +}; + +static struct mxc_audio_platform_data wm8903_data; + +static void __init mxc_init_wm8903(void) +{ + wm8903_data.ssi_clk[0] = clk_get(NULL, "ssi_clk.0"); + clk_put(wm8903_data.ssi_clk[0]); + + wm8903_data.ssi_clk[1] = clk_get(NULL, "ssi_clk.1"); + clk_put(wm8903_data.ssi_clk[1]); + + wm8903_data.ssi_num = 1; + wm8903_data.src_port = 2; + wm8903_data.ext_port = 3; + + (void)platform_device_register(&mxc_wm8903_device); +} + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +int headphone_det_status(void) +{ + return gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26)); +} + +static struct mxc_audio_platform_data sgtl5000_data; + +static int mxc_sgtl5000_plat_init(void) +{ + struct regulator *reg; + reg = regulator_get(&mxc_sgtl5000_device.dev, "GPO2"); + if (IS_ERR(reg)) + return -EINVAL; + sgtl5000_data.priv = reg; + return 0; +} + +static int mxc_sgtl5000_plat_finit(void) +{ + struct regulator *reg; + reg = sgtl5000_data.priv; + if (reg) { + regulator_put(reg); + sgtl5000_data.priv = NULL; + } + return 0; +} + +static int mxc_sgtl5000_amp_enable(int enable) +{ + struct regulator *reg; + reg = sgtl5000_data.priv; + + if (!reg) + return -EINVAL; + if (enable) + regulator_enable(reg); + else + regulator_disable(reg); + return 0; +} + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_irq = IOMUX_TO_IRQ(MX51_PIN_EIM_A26), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .sysclk = 12000000, + .init = mxc_sgtl5000_plat_init, + .finit = mxc_sgtl5000_plat_finit, +}; + +static void bt_reset(void) +{ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D19), 1); +} + +static struct mxc_bt_platform_data mxc_bt_data = { + .bt_vdd = NULL, + .bt_vdd_parent = NULL, + .bt_vusb = "SW4", + .bt_vusb_parent = NULL, + .bt_reset = bt_reset, +}; + +static struct platform_device mxc_bt_device = { + .name = "mxc_bt", + .id = 0, +}; + +static void mxc_unifi_hardreset(int pin_level) +{ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D19), pin_level & 0x01); +} + +static struct mxc_unifi_platform_data unifi_data = { + .hardreset = mxc_unifi_hardreset, + .reg_vdd_vpa = "VSD", + .reg_1v5_dd = "VGEN1", + .host_id = 1, +}; + +struct mxc_unifi_platform_data *get_unifi_plat_data(void) +{ + return &unifi_data; +} +EXPORT_SYMBOL(get_unifi_plat_data); + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + mxc_set_cpu_type(MXC_CPU_MX51); + + get_cpu_wp = mx51_3stack_get_cpu_wp; + set_num_cpu_wp = mx51_3stack_set_num_cpu_wp; +} + +static struct mxc_gps_platform_data gps_data = { + .core_reg = "VIOHI", + .analog_reg = "SW4", +}; + +static struct platform_device mxc_gps_device = { + .name = "gps_ioctrl", + .id = -1, +}; + +int gpio_gps_access(int para) +{ + iomux_pin_name_t pin; + pin = (para & 0x1) ? MX51_PIN_EIM_CS2 : MX51_PIN_EIM_CRE; + + if (para & 0x4) /* Read GPIO */ + return gpio_get_value(IOMUX_TO_GPIO(pin)); + else if (para & 0x2) /* Write GPIO */ + gpio_set_value(IOMUX_TO_GPIO(pin), 1); + else + gpio_set_value(IOMUX_TO_GPIO(pin), 0); + return 0; +} +EXPORT_SYMBOL(gpio_gps_access); + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + int err; + + mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1"); + mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2"); + + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); + + mxc_cpu_common_init(); + mx51_3stack_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_hs_device, &mxci2c_hs_data); + mxc_register_device(&mxc_rtc_device, NULL); + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); + mxc_register_device(&mxc_tve_device, &tve_data); + mxc_register_device(&mxcvpu_device, &mxc_vpu_data); + mxc_register_device(&gpu_device, NULL); + mxc_register_device(&mxcscc_device, NULL); + mxc_register_device(&mx51_lpmode_device, NULL); + mxc_register_device(&busfreq_device, &bus_freq_data); + mxc_register_device(&sdram_autogating_device, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); + mxc_register_device(&mxc_iim_device, NULL); + mxc_register_device(&mxc_pwm1_device, NULL); + mxc_register_device(&mxc_pwm1_backlight_device, + &mxc_pwm_backlight_data); + mxc_register_device(&mxc_keypad_device, &keypad_plat_data); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + mxc_register_device(&mxc_sim_device, &sim_data); + mxc_register_device(&pata_fsl_device, &ata_data); + mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); + + mxc_expio_init(); + if (debug_board_present) + mxc_register_device(&smsc_lan9217_device, &smsc911x_config); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) + lcd_data.reset = lcd_reset_to2; + + mxc_register_device(&mxc_lcd_device, &lcd_data); + mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + mxc_register_device(&mxc_fb_devices[2], NULL); + mxc_register_device(&mxcbl_device, NULL); + +#if defined(CONFIG_MTD_NAND_IMX_NFC) || defined(CONFIG_MTD_NAND_IMX_NFC_MODULE) + mxc_register_device(&imx_nfc_device, &imx_nfc_platform_data); +#else + mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data); +#endif + mx51_3stack_init_mc13892(); + + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + i2c_register_board_info(3, mxc_i2c_hs_board_info, + ARRAY_SIZE(mxc_i2c_hs_board_info)); + + mxc_init_wm8903(); + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mxc_register_device(&mxc_bt_device, &mxc_bt_data); + mxc_register_device(&mxc_gps_device, &gps_data); + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); + + mx5_usb_dr_init(); + mx5_usbh1_init(); + + /* Setup Touchscreen interrupt */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), "gpio1_5"); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5)); + + err = mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_GPIO); + if (err) + printk(KERN_ERR "Error: bt reset request gpio failed!\n"); + else { + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D19), "eim_d19"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D19), 0); + } +} + +static void __init mx51_3stack_timer_init(void) +{ + struct clk *uart_clk; + + /* Change the CPU voltages for TO2*/ + if (cpu_is_mx51_rev(CHIP_REV_2_0) <= 1) { + cpu_wp_auto[0].cpu_voltage = 1175000; + cpu_wp_auto[1].cpu_voltage = 1100000; + cpu_wp_auto[2].cpu_voltage = 1000000; + } + + mx51_clocks_init(32768, 24000000, 22579200, 24576000); + + uart_clk = clk_get(NULL, "uart_clk.0"); + early_console_setup(UART1_BASE_ADDR, uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx51_3stack_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX51_3STACK data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx51_3stack_gpio.c b/arch/arm/mach-mx5/mx51_3stack_gpio.c new file mode 100644 index 000000000000..b0fca773eaaa --- /dev/null +++ b/arch/arm/mach-mx5/mx51_3stack_gpio.c @@ -0,0 +1,852 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "iomux.h" +#include "mx51_pins.h" + +/*! + * @file mach-mx5/mx51_3stack_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO + */ +#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) + +static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { + /* CSI0 */ + { + MX51_PIN_CSI1_D8, IOMUX_CONFIG_ALT3, + PAD_CTL_PKE_ENABLE, + MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { + MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3, + PAD_CTL_PKE_ENABLE, + }, + { + MX51_PIN_CSI1_D10, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D11, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D12, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D13, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D14, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D15, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D16, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D17, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D18, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D19, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW), + }, + { + MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW), + }, + { + MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_SLOW | PAD_CTL_DRV_MEDIUM | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_VOT_HIGH), + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* SPI1 */ + MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_OWIRE_LINE, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP2_DAT15, IOMUX_CONFIG_ALT5, + }, + { + MX51_PIN_DI_GP2, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0, + }, + { /* AUD3_TXD */ + MX51_PIN_AUD3_BB_TXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_100K_PU | + PAD_CTL_HYS_NONE | PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW), + }, + { /* AUD3_RXD */ + MX51_PIN_AUD3_BB_RXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_100K_PU | + PAD_CTL_HYS_NONE | PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW), + }, + { /* AUD3_CLK */ + MX51_PIN_AUD3_BB_CK, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_100K_PU | + PAD_CTL_HYS_NONE | PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW), + }, + { /* AUD3_FS */ + MX51_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_100K_PU | + PAD_CTL_HYS_NONE | PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW), + }, + { + MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { + MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PD, + }, + { + MX51_PIN_EIM_DTACK, IOMUX_CONFIG_GPIO, + (PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU), + }, + { + MX51_PIN_EIM_CS2, IOMUX_CONFIG_GPIO, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_EIM_CRE, IOMUX_CONFIG_GPIO, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT2, + }, + { + MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_GPIO, + 0, + MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { + MX51_PIN_DISPB2_SER_RS, IOMUX_CONFIG_GPIO, + }, + { + MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_GPIO, + }, + { /* TO2 */ + MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4, + }, + { /* TO2 */ + MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT1, + }, + { /* TO2 */ + MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT1, + }, + { /* TO2 */ + MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT1, + }, + { /* TO2 */ + MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT1, + }, +#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL + { + MX51_PIN_DISP1_DAT0, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT1, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT2, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT3, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT4, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT5, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT6, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT7, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT8, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT9, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT10, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT11, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT12, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT13, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT14, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT15, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT16, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT17, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT19, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT20, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT21, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, +#endif + { + MX51_PIN_I2C1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + 0x1E4, + }, + { + MX51_PIN_I2C1_DAT, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + 0x1E4, + }, + { + MX51_PIN_GPIO1_6, IOMUX_CONFIG_GPIO, + }, + { + MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE), + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH3, + }, + { + MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE), + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, INPUT_CTL_PATH3, + }, + { + MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USBH1_CLK */ + MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS), + }, + { /* USBH1_DIR */ + MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS), + }, + { /* USBH1_NXT */ + MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS), + }, + { /* USBH1_DATA0 */ + MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USBH1_DATA1 */ + MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USBH1_DATA2 */ + MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USBH1_DATA3 */ + MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USBH1_DATA4 */ + MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USBH1_DATA5 */ + MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USBH1_DATA6 */ + MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USBH1_DATA7 */ + MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + }, + { /* USB1_OC */ + MX51_PIN_GPIO1_9, IOMUX_CONFIG_ALT1, + (PAD_CTL_SRE_SLOW | PAD_CTL_DRV_LOW | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE), + }, + { /* USB1_PWR */ + MX51_PIN_GPIO1_8, IOMUX_CONFIG_ALT1, + (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_NONE | PAD_CTL_HYS_ENABLE), + }, + { + MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_GPIO1_0, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION, + (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), + }, + { + MX51_PIN_GPIO1_1, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION, + (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), + }, + { + MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { + MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH), + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { + MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH), + }, + { + MX51_PIN_UART2_RXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH2, + }, + { + MX51_PIN_UART2_TXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT4, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH3, + }, + { + MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT4, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_UART3_RXD, IOMUX_CONFIG_ALT1, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH4, + }, + { + MX51_PIN_UART3_TXD, IOMUX_CONFIG_ALT1, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + }, + { + MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT3, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH3, + }, + { + MX51_PIN_EIM_D24, IOMUX_CONFIG_ALT3, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + }, +}; + +static struct mxc_iomux_pin_cfg __initdata ata_iomux_pins[] = { + { + MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + /* TO 2.0 */ + { + MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + /* TO 1.0 */ + { + MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, + { + MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1, + ATA_PAD_CONFIG, + }, +}; + +static struct mxc_iomux_pin_cfg __initdata nand_iomux_pins[] = { + { + MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0, + }, + { + MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0, + }, + /* TO2 */ + { + MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT0, + }, + /* TO1 */ + { + MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT0, + }, +}; + +static struct mxc_iomux_pin_cfg __initdata sim_iomux_pins[] = { + { + MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT6, + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE, + }, + { + MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT6, + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE, + }, + { + MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT6, + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE, + }, + { + MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT6, + PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_22K_PU | + PAD_CTL_PUE_PULL | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE, + }, +}; + +static int __initdata enable_ata = { 0 }; +static int __init ata_setup(char *__unused) +{ + enable_ata = 1; + return 1; +} + +__setup("ata", ata_setup); + +static int __initdata enable_sim = { 0 }; +static int __init sim_setup(char *__unused) +{ + enable_sim = 1; + return 1; +} + +__setup("sim", sim_setup); + +void __init mx51_3stack_io_init(void) +{ + int i, num; + struct mxc_iomux_pin_cfg *pin_ptr; + + for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) { + mxc_request_iomux(mxc_iomux_pins[i].pin, + mxc_iomux_pins[i].mux_mode); + if (mxc_iomux_pins[i].pad_cfg) + mxc_iomux_set_pad(mxc_iomux_pins[i].pin, + mxc_iomux_pins[i].pad_cfg); + if (mxc_iomux_pins[i].in_select) + mxc_iomux_set_input(mxc_iomux_pins[i].in_select, + mxc_iomux_pins[i].in_mode); + } + + if (enable_ata) { + pin_ptr = ata_iomux_pins; + num = ARRAY_SIZE(ata_iomux_pins); + } else if (enable_sim) { + pin_ptr = sim_iomux_pins; + num = ARRAY_SIZE(sim_iomux_pins); + } else { + pin_ptr = nand_iomux_pins; + num = ARRAY_SIZE(nand_iomux_pins); + } + + for (i = 0; i < num; i++) { + mxc_request_iomux(pin_ptr[i].pin, pin_ptr[i].mux_mode); + if (pin_ptr[i].pad_cfg) + mxc_iomux_set_pad(pin_ptr[i].pin, pin_ptr[i].pad_cfg); + if (pin_ptr[i].in_select) + mxc_iomux_set_input(pin_ptr[i].in_select, + pin_ptr[i].in_mode); + } + + /* TO3 doesn't need pad to drive CSI_DATA_EN[0] high */ + if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) + mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT0); + + /* Camera low power */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), "csi1_d8"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), 0); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), "eim_eb2"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), 0); /* TO1 */ + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), 0); /* TO1 */ + + /* Camera reset */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), "csi1_d9"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 1); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), "gpio1_0"); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); /* SD1 CD */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), "gpio1_1"); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); /* SD1 WP */ + + /* EIM_D16 */ + /* osc_en is shared by SPDIF */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), "eim_d16"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), 1); + + /* LCD related gpio */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs"); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0); + + /* GPS related gpio */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), "eim_cs2"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), 0); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), "eim_cre"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 1); +} diff --git a/arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c new file mode 100644 index 000000000000..7f2136d44152 --- /dev/null +++ b/arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c @@ -0,0 +1,370 @@ +/* + * mx51-3stack-pmic-mc13892.c -- i.MX51 3STACK Driver for Atlas MC13892 PMIC + */ + /* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "iomux.h" +#include "mx51_pins.h" + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +#define STANDBYSECINV_LSH 11 +#define STANDBYSECINV_WID 1 + +/* Coin cell charger enable */ +#define COINCHEN_LSH 23 +#define COINCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +/*! + * the event handler for power on event + */ +static void power_on_evt_handler(void) +{ + pr_info("pwr on event1 is received \n"); +} + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value; + pmic_event_callback_t power_key_event; + int register_mask; + + printk("Initializing regulators for 3-stack.\n"); + if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) + sw2_init.constraints.state_mem.uV = 1100000; + else if (mxc_cpu_is_rev(CHIP_REV_2_0) == 1) { + sw2_init.constraints.state_mem.uV = 1250000; + sw1_init.constraints.state_mem.uV = 1000000; + } + + /* subscribe PWRON1 event to enable ON_OFF key */ + power_key_event.param = NULL; + power_key_event.func = (void *)power_on_evt_handler; + pmic_event_subscribe(EVENT_PWRONI, power_key_event); + + /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + /* Set the STANDBYSECINV bit, so that STANDBY pin is + * interpreted as active low. + */ + value = BITFVAL(STANDBYSECINV, 1); + register_mask = BITFMASK(STANDBYSECINV); + pmic_write_reg(REG_POWER_CTL2, value, register_mask); + + /* Enable coin cell charger */ + value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); + register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct i2c_board_info __initdata mc13892_i2c_device = { + I2C_BOARD_INFO("mc13892", 0x08), + .irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_5), + .platform_data = &mc13892_plat, +}; + +int __init mx51_3stack_init_mc13892(void) +{ + return i2c_register_board_info(1, &mc13892_i2c_device, 1); +} diff --git a/arch/arm/mach-mx5/mx51_babbage.c b/arch/arm/mach-mx5/mx51_babbage.c new file mode 100644 index 000000000000..b6edc8078aab --- /dev/null +++ b/arch/arm/mach-mx5/mx51_babbage.c @@ -0,0 +1,1325 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" +#include "crm_regs.h" +#include "usb.h" + +/*! + * @file mach-mx51/mx51_babbage.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX51 + */ + +#define BABBAGE_SD1_CD (0*32 + 0) /* GPIO_1_0 */ +#define BABBAGE_SD1_WP (0*32 + 1) /* GPIO_1_1 */ +#define BABBAGE_SD2_CD_2_0 (0*32 + 4) /* GPIO_1_4 */ +#define BABBAGE_SD2_WP (0*32 + 5) /* GPIO_1_5 */ +#define BABBAGE_SD2_CD_2_5 (0*32 + 6) /* GPIO_1_6 */ +#define BABBAGE_USBH1_HUB_RST (0*32 + 7) /* GPIO_1_7 */ +#define BABBAGE_PMIC_INT (0*32 + 8) /* GPIO_1_8 */ + +#define BABBAGE_USB_CLK_EN_B (1*32 + 1) /* GPIO_2_1 */ +#define BABBAGE_OSC_EN_B (1*32 + 2) /* GPIO_2_2 */ +#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ +#define BABBAGE_CAM_RESET (1*32 + 7) /* GPIO_2_7 */ +#define BABBAGE_FM_PWR (1*32 + 12) /* GPIO_2_12 */ +#define BABBAGE_VGA_RESET (1*32 + 13) /* GPIO_2_13 */ +#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ +#define BABBAGE_FM_RESET (1*32 + 15) /* GPIO_2_15 */ +#define BABBAGE_AUDAMP_STBY (1*32 + 17) /* GPIO_2_17 */ +#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */ + +#define BABBAGE_26M_OSC_EN (2*32 + 1) /* GPIO_3_1 */ +#define BABBAGE_LVDS_POWER_DOWN (2*32 + 3) /* GPIO_3_3 */ +#define BABBAGE_DISP_BRIGHTNESS_CTL (2*32 + 4) /* GPIO_3_4 */ +#define BABBAGE_DVI_RESET (2*32 + 5) /* GPIO_3_5 */ +#define BABBAGE_DVI_POWER (2*32 + 6) /* GPIO_3_6 */ +#define BABBAGE_HEADPHONE_DET (2*32 + 26) /* GPIO_3_26 */ +#define BABBAGE_DVI_DET (2*32 + 28) /* GPIO_3_28 */ + +#define BABBAGE_LCD_3V3_ON (3*32 + 9) /* GPIO_4_9 */ +#define BABBAGE_LCD_5V_ON (3*32 + 10) /* GPIO_4_10 */ +#define BABBAGE_CAM_LOW_POWER (3*32 + 10) /* GPIO_4_12 */ +#define BABBAGE_DVI_I2C_EN (3*32 + 14) /* GPIO_4_14 */ +#define BABBAGE_CSP1_SS0_GPIO (3*32 + 24) /* GPIO_4_24 */ +#define BABBAGE_AUDIO_CLK_EN (3*32 + 26) /* GPIO_4_26 */ + +extern int __init mx51_babbage_init_mc13892(void); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +static int num_cpu_wp = 3; + +static struct pad_desc mx51babbage_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + + /* USB HOST1 */ + MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + + MX51_PAD_GPIO_1_0__GPIO_1_0, + MX51_PAD_GPIO_1_1__GPIO_1_1, + MX51_PAD_GPIO_1_4__GPIO_1_4, + MX51_PAD_GPIO_1_5__GPIO_1_5, + MX51_PAD_GPIO_1_6__GPIO_1_6, + MX51_PAD_GPIO_1_7__GPIO_1_7, + MX51_PAD_GPIO_1_8__GPIO_1_8, + MX51_PAD_UART3_RXD__GPIO_1_22, + + MX51_PAD_EIM_D17__GPIO_2_1, + MX51_PAD_EIM_D18__GPIO_2_2, + MX51_PAD_EIM_D21__GPIO_2_5, + MX51_PAD_EIM_D23__GPIO_2_7, + MX51_PAD_EIM_A16__GPIO_2_10, + MX51_PAD_EIM_A17__GPIO_2_11, + MX51_PAD_EIM_A18__GPIO_2_12, + MX51_PAD_EIM_A19__GPIO_2_13, + MX51_PAD_EIM_A20__GPIO_2_14, + MX51_PAD_EIM_A21__GPIO_2_15, + MX51_PAD_EIM_A22__GPIO_2_16, + MX51_PAD_EIM_A23__GPIO_2_17, + MX51_PAD_EIM_A27__GPIO_2_21, + MX51_PAD_EIM_DTACK__GPIO_2_31, + + MX51_PAD_EIM_LBA__GPIO_3_1, + MX51_PAD_DI1_D0_CS__GPIO_3_3, + MX51_PAD_DISPB2_SER_DIN__GPIO_3_5, + MX51_PAD_DISPB2_SER_DIO__GPIO_3_6, + MX51_PAD_NANDF_CS0__GPIO_3_16, + MX51_PAD_NANDF_CS1__GPIO_3_17, + MX51_PAD_NANDF_D14__GPIO_3_26, + MX51_PAD_NANDF_D12__GPIO_3_28, + + MX51_PAD_CSI2_D12__GPIO_4_9, + MX51_PAD_CSI2_D13__GPIO_4_10, + MX51_PAD_CSI2_D19__GPIO_4_12, + MX51_PAD_CSI2_HSYNC__GPIO_4_14, + MX51_PAD_CSPI1_RDY__GPIO_4_26, + + MX51_PAD_EIM_EB2__FEC_MDIO, + MX51_PAD_EIM_EB3__FEC_RDAT1, + MX51_PAD_EIM_CS2__FEC_RDAT2, + MX51_PAD_EIM_CS3__FEC_RDAT3, + MX51_PAD_EIM_CS4__FEC_RX_ER, + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_NANDF_RB2__FEC_COL, + MX51_PAD_NANDF_RB3__FEC_RXCLK, + MX51_PAD_NANDF_RB6__FEC_RDAT0, + MX51_PAD_NANDF_RB7__FEC_TDAT0, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_NANDF_CS3__FEC_MDC, + MX51_PAD_NANDF_CS4__FEC_TDAT1, + MX51_PAD_NANDF_CS5__FEC_TDAT2, + MX51_PAD_NANDF_CS6__FEC_TDAT3, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + + MX51_PAD_GPIO_NAND__PATA_INTRQ, + + MX51_PAD_DI_GP4__DI2_PIN15, +#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL + MX51_PAD_DISP1_DAT22__DISP2_DAT16, + MX51_PAD_DISP1_DAT23__DISP2_DAT17, + + MX51_PAD_DI1_D1_CS__GPIO_3_4, +#endif + MX51_PAD_I2C1_CLK__HSI2C_CLK, + MX51_PAD_I2C1_DAT__HSI2C_DAT, + MX51_PAD_EIM_D16__I2C1_SDA, + MX51_PAD_EIM_D19__I2C1_SCL, + + MX51_PAD_GPIO_1_2__PWM_PWMO, + + MX51_PAD_KEY_COL5__I2C2_SDA, + MX51_PAD_KEY_COL4__I2C2_SCL, + + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + + MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD, + MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD, + MX51_PAD_AUD3_BB_CK__AUD3_BB_CK, + MX51_PAD_AUD3_BB_FS__AUD3_BB_FS, + + MX51_PAD_CSPI1_SS1__CSPI1_SS1, + + MX51_PAD_DI_GP3__CSI1_DATA_EN, + MX51_PAD_CSI1_D10__CSI1_D10, + MX51_PAD_CSI1_D11__CSI1_D11, + MX51_PAD_CSI1_D12__CSI1_D12, + MX51_PAD_CSI1_D13__CSI1_D13, + MX51_PAD_CSI1_D14__CSI1_D14, + MX51_PAD_CSI1_D15__CSI1_D15, + MX51_PAD_CSI1_D16__CSI1_D16, + MX51_PAD_CSI1_D17__CSI1_D17, + MX51_PAD_CSI1_D18__CSI1_D18, + MX51_PAD_CSI1_D19__CSI1_D19, + MX51_PAD_CSI1_VSYNC__CSI1_VSYNC, + MX51_PAD_CSI1_HSYNC__CSI1_HSYNC, + + MX51_PAD_OWIRE_LINE__SPDIF_OUT1, +}; + +/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 1000000000, + .cpu_rate = 1000000000, + .pdf = 0, + .mfi = 10, + .mfd = 11, + .mfn = 5, + .cpu_podf = 0, + .cpu_voltage = 1175000,}, + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1100000,}, + { + .pll_rate = 800000000, + .cpu_rate = 166250000, + .pdf = 4, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 4, + .cpu_voltage = 850000,}, +}; + +static struct fb_videomode video_modes[] = { + { + /*MITSUBISHI LVDS panel */ + "XGA", 60, 1024, 768, 15385, + 220, 40, + 21, 7, + 60, 10, + 0, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +struct cpu_wp *mx51_babbage_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_auto; +} + +void mx51_babbage_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static u16 keymapping[16] = { + KEY_UP, KEY_DOWN, KEY_MENU, KEY_BACK, + KEY_RIGHT, KEY_LEFT, KEY_SELECT, KEY_ENTER, + KEY_F1, KEY_F3, KEY_1, KEY_3, + KEY_F2, KEY_F4, KEY_2, KEY_4, +}; + +static struct keypad_data keypad_plat_data = { + .rowmax = 4, + .colmax = 4, + .learning = 0, + .delay = 2, + .matrix = keymapping, +}; + +static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 78770, +}; + +extern void mx5_ipu_reset(void); +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 2, + .reset = mx5_ipu_reset, +}; + +extern void mx5_vpu_reset(void); +static struct mxc_vpu_platform_data mxc_vpu_data = { + .reset = mx5_vpu_reset, +}; + +/* workaround for ecspi chipselect pin may not keep correct level when idle */ +static void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + { + struct pad_desc cspi1_ss0 = MX51_PAD_CSPI1_SS0__CSPI1_SS0; + + mxc_iomux_v3_setup_pad(&cspi1_ss0); + break; + } + case 0x2: + { + struct pad_desc cspi1_ss0_gpio = MX51_PAD_CSPI1_SS0__GPIO_4_24; + + mxc_iomux_v3_setup_pad(&cspi1_ss0_gpio); + gpio_request(BABBAGE_CSP1_SS0_GPIO, "cspi1-gpio"); + gpio_direction_output(BABBAGE_CSP1_SS0_GPIO, 0); + gpio_set_value(BABBAGE_CSP1_SS0_GPIO, 1 & (~status)); + break; + } + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + break; + case 0x2: + gpio_free(BABBAGE_CSP1_SS0_GPIO); + break; + + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = mx51_babbage_gpio_spi_chipselect_active, + .chipselect_inactive = mx51_babbage_gpio_spi_chipselect_inactive, +}; + +static struct imxi2c_platform_data mxci2c_data = { + .bitrate = 100000, +}; + +static struct mxc_i2c_platform_data mxci2c_hs_data = { + .i2c_clk = 400000, +}; + +static struct tve_platform_data tve_data = { + .dac_reg = "VVIDEO", +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, + .num_wp = 3, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "SW1", + .lp_reg_id = "SW2", +}; + +static struct mxc_dvfsper_data dvfs_per_data = { + .reg_id = "SW2", + .clk_id = "gpc_dvfs_clk", + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .gpc_adu = 0x0, + .vai_mask = MXC_DVFSPMCR0_FSVAI_MASK, + .vai_offset = MXC_DVFSPMCR0_FSVAI_OFFSET, + .dvfs_enable_bit = MXC_DVFSPMCR0_DVFEN, + .irq_mask = MXC_DVFSPMCR0_FSVAIM, + .div3_offset = 0, + .div3_mask = 0x7, + .div3_div = 2, + .lp_high = 1250000, + .lp_low = 1250000, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 0, + .spdif_clk_44100 = 0, /* spdif_ext_clk source for 44.1KHz */ + .spdif_clk_48000 = 7, /* audio osc source */ + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static struct resource mxcfb_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = IPU_PIX_FMT_RGB24, + .mode_str = "1024x768M-16@60", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, + { + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "800x480M@55", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +static void mxc_iim_enable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + /* Enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg |= 0x10; + writel(reg, ccm_base + 0x64); +} + +static void mxc_iim_disable_fuse(void) +{ + u32 reg; + + /* Disable fuse blown */ + if (!ccm_base) + return; + + reg = readl(ccm_base + 0x64); + reg &= ~0x10; + writel(reg, ccm_base + 0x64); +} + +static struct mxc_iim_data iim_data = { + .bank_start = MXC_IIM_MX51_BANK_START_ADDR, + .bank_end = MXC_IIM_MX51_BANK_END_ADDR, + .enable_fuse = mxc_iim_enable_fuse, + .disable_fuse = mxc_iim_disable_fuse, +}; + +extern int primary_di; +static int __init mxc_init_fb(void) +{ + if (!machine_is_mx51_babbage()) + return 0; + + /* DI0-LVDS */ + gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 0); + msleep(1); + gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 1); + gpio_set_value(BABBAGE_LCD_3V3_ON, 1); + gpio_set_value(BABBAGE_LCD_5V_ON, 1); + + /* DVI Detect */ + gpio_request(BABBAGE_DVI_DET, "dvi-detect"); + gpio_direction_input(BABBAGE_DVI_DET); + /* DVI Reset - Assert for i2c disabled mode */ + gpio_request(BABBAGE_DVI_RESET, "dvi-reset"); + gpio_direction_output(BABBAGE_DVI_RESET, 0); + /* DVI Power-down */ + gpio_request(BABBAGE_DVI_POWER, "dvi-power"); + gpio_direction_output(BABBAGE_DVI_POWER, 1); + + /* WVGA Reset */ + gpio_set_value(BABBAGE_DISP_BRIGHTNESS_CTL, 1); + + if (primary_di) { + printk(KERN_INFO "DI1 is primary\n"); + + /* DI1 -> DP-BG channel: */ + mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[1].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + + /* DI0 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + } else { + printk(KERN_INFO "DI0 is primary\n"); + + /* DI0 -> DP-BG channel: */ + mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[0].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + + /* DI1 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + } + + /* + * DI0/1 DP-FG channel: + */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +device_initcall(mxc_init_fb); + +static int handle_edid(int *pixclk) +{ +#if 0 + int err = 0; + int dvi = 0; + int fb0 = 0; + int fb1 = 1; + struct fb_var_screeninfo screeninfo; + struct i2c_adapter *adp; + + memset(&screeninfo, 0, sizeof(screeninfo)); + + adp = i2c_get_adapter(1); + + if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) { + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), 1); + msleep(1); + } + err = read_edid(adp, &screeninfo, &dvi); + if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), 0); + + if (!err) { + printk(KERN_INFO " EDID read\n"); + if (!dvi) { + enable_vga = 1; + fb0 = 1; /* fb0 will be VGA */ + fb1 = 0; /* fb1 will be DVI or TV */ + } + + /* Handle TV modes */ + /* This logic is fairly complex yet still doesn't handle all + possibilities. Once a customer knows the platform + configuration, this should be simplified to what is desired. + */ + if (screeninfo.xres == 1920 && screeninfo.yres != 1200) { + /* MX51 can't handle clock speeds for anything larger.*/ + if (!enable_tv) + enable_tv = 1; + if (enable_vga || enable_wvga || enable_tv == 2) + enable_tv = 2; + fb_data[0].mode = &(video_modes[0]); + if (!enable_wvga) + fb_data[1].mode_str = "800x600M-16@60"; + } else if (screeninfo.xres > 1280 && screeninfo.yres > 1024) { + if (!enable_wvga) { + fb_data[fb0].mode_str = "1280x1024M-16@60"; + fb_data[fb1].mode_str = NULL; + } else { + /* WVGA is preset so the DVI can't be > this. */ + fb_data[0].mode_str = "1024x768M-16@60"; + } + } else if (screeninfo.xres > 0 && screeninfo.yres > 0) { + if (!enable_wvga) { + fb_data[fb0].mode = + kzalloc(sizeof(struct fb_videomode), + GFP_KERNEL); + fb_var_to_videomode(fb_data[fb0].mode, + &screeninfo); + fb_data[fb0].mode_str = NULL; + if (screeninfo.xres >= 1280 && + screeninfo.yres > 720) + fb_data[fb1].mode_str = NULL; + else if (screeninfo.xres > 1024 && + screeninfo.yres > 768) + fb_data[fb1].mode_str = + "800x600M-16@60"; + else if (screeninfo.xres > 800 && + screeninfo.yres > 600) + fb_data[fb1].mode_str = + "1024x768M-16@60"; + } else { + /* A WVGA panel was specified and an EDID was + read thus there is a DVI monitor attached. */ + if (screeninfo.xres >= 1024) + fb_data[0].mode_str = "1024x768M-16@60"; + else if (screeninfo.xres >= 800) + fb_data[0].mode_str = "800x600M-16@60"; + else + fb_data[0].mode_str = "640x480M-16@60"; + } + } + } +#endif + return 0; +} + +static void dvi_reset(void) +{ + gpio_direction_output(BABBAGE_DVI_RESET, 0); + gpio_set_value(BABBAGE_DVI_RESET, 0); + msleep(50); + + /* do reset */ + gpio_set_value(BABBAGE_DVI_RESET, 1); + msleep(20); /* tRES >= 50us */ + + gpio_set_value(BABBAGE_DVI_RESET, 0); +} + +static struct mxc_lcd_platform_data dvi_data = { + .core_reg = "VGEN1", + .io_reg = "VGEN3", + .reset = dvi_reset, +}; + +static void vga_reset(void) +{ + + gpio_set_value(BABBAGE_VGA_RESET, 0); + msleep(50); + /* do reset */ + gpio_set_value(BABBAGE_VGA_RESET, 1); + msleep(10); /* tRES >= 50us */ + gpio_set_value(BABBAGE_VGA_RESET, 0); +} + +static struct mxc_lcd_platform_data vga_data = { + .core_reg = "VCAM", + .io_reg = "VGEN3", + .analog_reg = "VAUDIO", + .reset = vga_reset, +}; + +static void si4702_reset(void) +{ + return; + + gpio_set_value(BABBAGE_FM_RESET, 0); + msleep(100); + gpio_set_value(BABBAGE_FM_RESET, 1); + msleep(100); +} + +static void si4702_clock_ctl(int flag) +{ + gpio_set_value(BABBAGE_FM_PWR, flag); + msleep(100); +} + +static void si4702_gpio_get(void) +{ + gpio_request(BABBAGE_FM_PWR, "fm-power"); + gpio_direction_output(BABBAGE_FM_PWR, 0); +} + +static void si4702_gpio_put(void) +{ +} + +static struct mxc_fm_platform_data si4702_data = { + .reg_vio = "SW4", + .reg_vdd = "VIOHI", + .gpio_get = si4702_gpio_get, + .gpio_put = si4702_gpio_put, + .reset = si4702_reset, + .clock_ctl = si4702_clock_ctl, +}; + +static struct mxc_camera_platform_data camera_data = { + .io_regulator = "SW4", + .analog_regulator = "VIOHI", + .mclk = 24000000, + .csi = 0, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + .type = "ov3640", + .addr = 0x3C, + .platform_data = (void *)&camera_data, + }, +}; + +static struct mxc_lightsensor_platform_data ls_data = { + .vdd_reg = "VIOHI", + .rext = 100, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "isl29003", + .addr = 0x44, + .platform_data = &ls_data, + }, +}; + +static struct i2c_board_info mxc_i2c_hs_board_info[] __initdata = { + { + .type = "sii9022", + .addr = 0x39, + .platform_data = &dvi_data, + }, + { + .type = "ch7026", + .addr = 0x75, + .platform_data = &vga_data, + }, + { + .type = "si4702", + .addr = 0x10, + .platform_data = (void *)&si4702_data, + }, +}; + +static struct mtd_partition mxc_spi_nor_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x00040000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, + +}; + +static struct mtd_partition mxc_dataflash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x000100000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, +}; + +static struct flash_platform_data mxc_spi_flash_data[] = { + { + .name = "mxc_spi_nor", + .parts = mxc_spi_nor_partitions, + .nr_parts = ARRAY_SIZE(mxc_spi_nor_partitions), + .type = "sst25vf016b",}, + { + .name = "mxc_dataflash", + .parts = mxc_dataflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), + .type = "at45db321d",} +}; + +static struct spi_board_info mxc_spi_nor_device[] __initdata = { + { + .modalias = "mxc_spi_nor", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[0], + }, +}; + +static struct spi_board_info mxc_dataflash_device[] __initdata = { + { + .modalias = "mxc_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[1],}, +}; + +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(BABBAGE_SD1_WP); + else + rc = gpio_get_value(BABBAGE_SD2_WP); + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret; + + if (to_platform_device(dev)->id == 0) { + ret = gpio_get_value(BABBAGE_SD1_CD); + return ret; + } else { /* config the det pin for SDHC2 */ + if (board_is_rev(BOARD_REV_2)) + /* BB2.5 */ + ret = gpio_get_value(BABBAGE_SD2_CD_2_5); + else + /* BB2.0 */ + ret = gpio_get_value(BABBAGE_SD2_CD_2_0); + return ret; + } +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 52000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 150000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static int mxc_sgtl5000_amp_enable(int enable) +{ + gpio_set_value(BABBAGE_AUDAMP_STBY, enable ? 1 : 0); + return 0; +} + +static int mxc_sgtl5000_clock_enable(int enable) +{ + gpio_set_value(BABBAGE_AUDIO_CLK_EN, !enable); + return 0; +} + +static int headphone_det_status(void) +{ + return (gpio_get_value(BABBAGE_HEADPHONE_DET) == 0); +} + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_irq = IOMUX_TO_IRQ_V3(BABBAGE_HEADPHONE_DET), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .clock_enable = mxc_sgtl5000_clock_enable, + .sysclk = 12288000, +}; + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx51(); +} + +__setup("w1", w1_setup); + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + char *str; + struct tag *t; + struct tag *mem_tag = 0; + int total_mem = SZ_512M; + int left_mem = 0; + int gpu_mem = SZ_64M; + int fb_mem = SZ_32M; + + mxc_set_cpu_type(MXC_CPU_MX51); + + get_cpu_wp = mx51_babbage_get_cpu_wp; + set_num_cpu_wp = mx51_babbage_set_num_cpu_wp; + + for_each_tag(mem_tag, tags) { + if (mem_tag->hdr.tag == ATAG_MEM) { + total_mem = mem_tag->u.mem.size; + left_mem = total_mem - gpu_mem - fb_mem; + break; + } + } + + for_each_tag(t, tags) { + if (t->hdr.tag == ATAG_CMDLINE) { + str = t->u.cmdline.cmdline; + str = strstr(str, "mem="); + if (str != NULL) { + str += 4; + left_mem = memparse(str, &str); + if (left_mem == 0 || left_mem > total_mem) + left_mem = total_mem - gpu_mem - fb_mem; + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_memory="); + if (str != NULL) { + str += 11; + gpu_mem = memparse(str, &str); + } + + break; + } + } + + if (mem_tag) { + fb_mem = total_mem - left_mem - gpu_mem; + if (fb_mem < 0) { + gpu_mem = total_mem - left_mem; + fb_mem = 0; + } + mem_tag->u.mem.size = left_mem; + + /*reserve memory for gpu*/ + gpu_device.resource[5].start = + mem_tag->u.mem.start + left_mem; + gpu_device.resource[5].end = + gpu_device.resource[5].start + gpu_mem - 1; +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) + if (fb_mem) { + mxcfb_resources[0].start = + gpu_device.resource[5].end + 1; + mxcfb_resources[0].end = + mxcfb_resources[0].start + fb_mem - 1; + } else { + mxcfb_resources[0].start = 0; + mxcfb_resources[0].end = 0; + } +#endif + } +} + +#define PWGT1SPIEN (1<<15) +#define PWGT2SPIEN (1<<16) +#define USEROFFSPI (1<<3) + +static void mxc_power_off(void) +{ + /* We can do power down one of two ways: + Set the power gating + Set USEROFFSPI */ + + /* Set the power gate bits to power down */ + pmic_write_reg(REG_POWER_MISC, (PWGT1SPIEN|PWGT2SPIEN), + (PWGT1SPIEN|PWGT2SPIEN)); +} + +/*! + * Power Key interrupt handler. + */ +static irqreturn_t power_key_int(int irq, void *dev_id) +{ + pwrkey_callback cb = (pwrkey_callback)dev_id; + + cb((void *)1); + + if (gpio_get_value(BABBAGE_POWER_KEY)) + set_irq_type(irq, IRQF_TRIGGER_FALLING); + else + set_irq_type(irq, IRQF_TRIGGER_RISING); + + return 0; +} + +static void mxc_register_powerkey(pwrkey_callback pk_cb) +{ + /* Set power key as wakeup resource */ + int irq, ret; + irq = IOMUX_TO_IRQ_V3(BABBAGE_POWER_KEY); + + if (gpio_get_value(BABBAGE_POWER_KEY)) + set_irq_type(irq, IRQF_TRIGGER_FALLING); + else + set_irq_type(irq, IRQF_TRIGGER_RISING); + + ret = request_irq(irq, power_key_int, 0, "power_key", pk_cb); + if (ret) + pr_info("register on-off key interrupt failed\n"); + else + enable_irq_wake(irq); +} + +static int mxc_pwrkey_getstatus(int id) +{ + return gpio_get_value(BABBAGE_POWER_KEY); +} + +static struct power_key_platform_data pwrkey_data = { + .key_value = KEY_F4, + .register_pwrkey = mxc_register_powerkey, + .get_key_status = mxc_pwrkey_getstatus, +}; + +static void __init mx51_babbage_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, + ARRAY_SIZE(mx51babbage_pads)); + + gpio_request(BABBAGE_PMIC_INT, "pmic-int"); + gpio_request(BABBAGE_SD1_CD, "sdhc1-detect"); + gpio_request(BABBAGE_SD1_WP, "sdhc1-wp"); + + gpio_direction_input(BABBAGE_PMIC_INT); + gpio_direction_input(BABBAGE_SD1_CD); + gpio_direction_input(BABBAGE_SD1_WP); + + if (board_is_rev(BOARD_REV_2)) { + /* SD2 CD for BB2.5 */ + gpio_request(BABBAGE_SD2_CD_2_5, "sdhc2-detect"); + gpio_direction_input(BABBAGE_SD2_CD_2_5); + } else { + /* SD2 CD for BB2.0 */ + gpio_request(BABBAGE_SD2_CD_2_0, "sdhc2-detect"); + gpio_direction_input(BABBAGE_SD2_CD_2_0); + } + gpio_request(BABBAGE_SD2_WP, "sdhc2-wp"); + gpio_direction_input(BABBAGE_SD2_WP); + + /* reset usbh1 hub */ + gpio_request(BABBAGE_USBH1_HUB_RST, "hub-rst"); + gpio_direction_output(BABBAGE_USBH1_HUB_RST, 0); + gpio_set_value(BABBAGE_USBH1_HUB_RST, 0); + msleep(1); + gpio_set_value(BABBAGE_USBH1_HUB_RST, 1); + + /* reset FEC PHY */ + gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); + gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); + msleep(10); + gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); + + /* reset FM */ + gpio_request(BABBAGE_FM_RESET, "fm-reset"); + gpio_direction_output(BABBAGE_FM_RESET, 0); + msleep(10); + gpio_set_value(BABBAGE_FM_RESET, 1); + + /* Drive 26M_OSC_EN line high */ + gpio_request(BABBAGE_26M_OSC_EN, "26m-osc-en"); + gpio_direction_output(BABBAGE_26M_OSC_EN, 1); + + /* Drive USB_CLK_EN_B line low */ + gpio_request(BABBAGE_USB_CLK_EN_B, "usb-clk_en_b"); + gpio_direction_output(BABBAGE_USB_CLK_EN_B, 0); + + /* De-assert USB PHY RESETB */ + gpio_request(BABBAGE_PHY_RESET, "usb-phy-reset"); + gpio_direction_output(BABBAGE_PHY_RESET, 1); + + /* hphone_det_b */ + gpio_request(BABBAGE_HEADPHONE_DET, "hphone-det"); + gpio_direction_input(BABBAGE_HEADPHONE_DET); + + /* audio_clk_en_b */ + gpio_request(BABBAGE_AUDIO_CLK_EN, "audio-clk-en"); + gpio_direction_output(BABBAGE_AUDIO_CLK_EN, 0); + + /* power key */ + gpio_request(BABBAGE_POWER_KEY, "power-key"); + gpio_direction_input(BABBAGE_POWER_KEY); + + if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) { + /* DVI_I2C_ENB = 0 tristates the DVI I2C level shifter */ + gpio_request(BABBAGE_DVI_I2C_EN, "dvi-i2c-en"); + gpio_direction_output(BABBAGE_DVI_I2C_EN, 0); + } + + /* Deassert VGA reset to free i2c bus */ + gpio_request(BABBAGE_VGA_RESET, "vga-reset"); + gpio_direction_output(BABBAGE_VGA_RESET, 1); + + /* LCD related gpio */ + gpio_request(BABBAGE_DISP_BRIGHTNESS_CTL, "disp-brightness-ctl"); + gpio_request(BABBAGE_LVDS_POWER_DOWN, "lvds-power-down"); + gpio_request(BABBAGE_LCD_3V3_ON, "lcd-3v3-on"); + gpio_request(BABBAGE_LCD_5V_ON, "lcd-5v-on"); + gpio_direction_output(BABBAGE_DISP_BRIGHTNESS_CTL, 0); + gpio_direction_output(BABBAGE_LVDS_POWER_DOWN, 0); + gpio_direction_output(BABBAGE_LCD_3V3_ON, 0); + gpio_direction_output(BABBAGE_LCD_5V_ON, 0); + + /* Camera reset */ + gpio_request(BABBAGE_CAM_RESET, "cam-reset"); + gpio_direction_output(BABBAGE_CAM_RESET, 1); + + /* Camera low power */ + gpio_request(BABBAGE_CAM_LOW_POWER, "cam-low-power"); + gpio_direction_output(BABBAGE_CAM_LOW_POWER, 0); + + /* OSC_EN */ + gpio_request(BABBAGE_OSC_EN_B, "osc-en"); + gpio_direction_output(BABBAGE_OSC_EN_B, 1); + + if (enable_w1) { + /* OneWire */ + struct pad_desc onewire = MX51_PAD_OWIRE_LINE__OWIRE_LINE; + mxc_iomux_v3_setup_pad(&onewire); + } +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1"); + mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2"); + + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); + /* SD card detect irqs */ + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(BABBAGE_SD2_CD_2_5); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(BABBAGE_SD2_CD_2_5); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(BABBAGE_SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(BABBAGE_SD1_CD); + + mxc_cpu_common_init(); + mx51_babbage_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_hs_device, &mxci2c_hs_data); + mxc_register_device(&mxc_rtc_device, NULL); + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); + mxc_register_device(&mxc_tve_device, &tve_data); + mxc_register_device(&mxcvpu_device, &mxc_vpu_data); + mxc_register_device(&gpu_device, NULL); + mxc_register_device(&mxcscc_device, NULL); + mxc_register_device(&mx51_lpmode_device, NULL); + mxc_register_device(&busfreq_device, &bus_freq_data); + mxc_register_device(&sdram_autogating_device, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); + mxc_register_device(&mxc_iim_device, &iim_data); + mxc_register_device(&mxc_pwm1_device, NULL); + mxc_register_device(&mxc_pwm1_backlight_device, + &mxc_pwm_backlight_data); + mxc_register_device(&mxc_keypad_device, &keypad_plat_data); + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&mxc_ssi3_device, NULL); + mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); + mxc_register_device(&mxc_fec_device, NULL); + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); + mxc_register_device(&mxc_powerkey_device, &pwrkey_data); + + mx51_babbage_init_mc13892(); + + if (board_is_rev(BOARD_REV_2)) + /* BB2.5 */ + spi_register_board_info(mxc_dataflash_device, + ARRAY_SIZE(mxc_dataflash_device)); + else + /* BB2.0 */ + spi_register_board_info(mxc_spi_nor_device, + ARRAY_SIZE(mxc_spi_nor_device)); + + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + + if (cpu_is_mx51_rev(CHIP_REV_2_0) >= 1) { + vga_data.core_reg = NULL; + vga_data.io_reg = NULL; + vga_data.analog_reg = NULL; + } + i2c_register_board_info(3, mxc_i2c_hs_board_info, + ARRAY_SIZE(mxc_i2c_hs_board_info)); + + pm_power_off = mxc_power_off; + + if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2) { + sgtl5000_data.sysclk = 26000000; + } + gpio_request(BABBAGE_AUDAMP_STBY, "audioamp-stdby"); + gpio_direction_output(BABBAGE_AUDAMP_STBY, 0); + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + + mx5_usb_dr_init(); + mx5_usbh1_init(); +} + +static void __init mx51_babbage_timer_init(void) +{ + struct clk *uart_clk; + + /* Change the CPU voltages for TO2*/ + if (cpu_is_mx51_rev(CHIP_REV_2_0) <= 1) { + cpu_wp_auto[0].cpu_voltage = 1175000; + cpu_wp_auto[1].cpu_voltage = 1100000; + cpu_wp_auto[2].cpu_voltage = 1000000; + } + + mx51_clocks_init(32768, 24000000, 22579200, 24576000); + + uart_clk = clk_get_sys("mxcintuart.0", NULL); + early_console_setup(UART1_BASE_ADDR, uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx51_babbage_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX51_BABBAGE data structure. + */ +/* *INDENT-OFF* */ +MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c new file mode 100644 index 000000000000..1d5a06bfb5f4 --- /dev/null +++ b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c @@ -0,0 +1,436 @@ +/* + * mx51-babbage-pmic-mc13892.c -- i.MX51 Babbage Driver for Atlas MC13892 PMIC + */ + /* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +/* Coin cell charger enable */ +#define COINCHEN_LSH 23 +#define COINCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* regulator standby mask */ +#define GEN1_STBY_MASK (1 << 1) +#define IOHI_STBY_MASK (1 << 4) +#define DIG_STBY_MASK (1 << 10) +#define GEN2_STBY_MASK (1 << 13) +#define PLL_STBY_MASK (1 << 16) +#define USB2_STBY_MASK (1 << 19) + +#define GEN3_STBY_MASK (1 << 1) +#define CAM_STBY_MASK (1 << 7) +#define VIDEO_STBY_MASK (1 << 13) +#define AUDIO_STBY_MASK (1 << 16) +#define SD_STBY_MASK (1 << 19) + +/* 0x92412 */ +#define REG_MODE_0_ALL_MASK (GEN1_STBY_MASK |\ + DIG_STBY_MASK | GEN2_STBY_MASK |\ + PLL_STBY_MASK) +/* 0x92082 */ +#define REG_MODE_1_ALL_MASK (CAM_STBY_MASK | VIDEO_STBY_MASK |\ + AUDIO_STBY_MASK | SD_STBY_MASK) + +/* switch mode setting */ +#define SW1MODE_LSB 0 +#define SW2MODE_LSB 10 +#define SW3MODE_LSB 0 +#define SW4MODE_LSB 8 + +#define SWMODE_MASK 0xF +#define SWMODE_AUTO 0x8 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +static struct regulator_consumer_supply vdig_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDA", + .dev_name = "1-000a", + }, +}; + +static struct regulator_consumer_supply vvideo_consumers[] = { + { + /* sgtl5000 */ + .supply = "VDDIO", + .dev_name = "1-000a", + }, +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1650), + .max_uV = mV_to_uV(1650), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vdig_consumers), + .consumer_supplies = vdig_consumers, +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + .always_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2775), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .apply_uV = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers), + .consumer_supplies = vvideo_consumers, +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(1200), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value, register_mask; + printk("Initializing regulators for Babbage.\n"); + if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) + sw2_init.constraints.state_mem.uV = 1100000; + else if (mxc_cpu_is_rev(CHIP_REV_2_0) == 1) { + sw2_init.constraints.state_mem.uV = 1250000; + sw1_init.constraints.state_mem.uV = 1000000; + } + + /* enable standby controll for all regulators */ + pmic_read_reg(REG_MODE_0, &value, 0xffffff); + value |= REG_MODE_0_ALL_MASK; + pmic_write_reg(REG_MODE_0, value, 0xffffff); + + pmic_read_reg(REG_MODE_1, &value, 0xffffff); + value |= REG_MODE_1_ALL_MASK; + pmic_write_reg(REG_MODE_1, value, 0xffffff); + + /* enable switch audo mode */ + pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff); + /* only for mc13892 2.0A */ + if ((value & 0x0000FFFF) == 0x45d0) { + pmic_read_reg(REG_SW_4, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW1MODE_LSB) | + (SWMODE_MASK << SW2MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW1MODE_LSB) | + (SWMODE_AUTO << SW2MODE_LSB); + pmic_write_reg(REG_SW_4, value, 0xffffff); + + pmic_read_reg(REG_SW_5, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW3MODE_LSB) | + (SWMODE_MASK << SW4MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW3MODE_LSB) | + (SWMODE_AUTO << SW4MODE_LSB); + pmic_write_reg(REG_SW_5, value, 0xffffff); + } + + /* Enable coin cell charger */ + value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); + register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + + regulator_has_full_constraints(); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct spi_board_info __initdata mc13892_spi_device = { + .modalias = "pmic_spi", + .irq = IOMUX_TO_IRQ_V3(8), + .max_speed_hz = 6000000, /* max spi SCK clock speed in HZ */ + .bus_num = 1, + .chip_select = 0, + .platform_data = &mc13892_plat, +}; + + +int __init mx51_babbage_init_mc13892(void) +{ + return spi_register_board_info(&mc13892_spi_device, 1); +} diff --git a/arch/arm/mach-mx5/mx51_pins.h b/arch/arm/mach-mx5/mx51_pins.h new file mode 100644 index 000000000000..351cdb29a32a --- /dev/null +++ b/arch/arm/mach-mx5/mx51_pins.h @@ -0,0 +1,409 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX51_PINS_H__ +#define __ASM_ARCH_MXC_MX51_PINS_H__ +#include "iomux.h" + +/*! + * @file arch-mxc/mx51_pins.h + * + * @brief MX51 I/O Pin List + * + * @ingroup GPIO_MX51 + */ + +#ifndef __ASSEMBLY__ + +#define PAD_I_START_MX51 0x3F0 +#define INPUT_CTL_START_MX51 0x8C4 +#define INPUT_CTL_START_MX51_TO1 0x928 + +#define MUX_I_END_MX51 (PAD_I_START_MX51 - 4) + +#define _MXC_BUILD_PIN_MX51(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START_MX51) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN_MX51(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN_MX51(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN_MX51(mi, pi) \ + _MXC_BUILD_PIN_MX51(NON_GPIO_PORT, 0, 0, mi, pi) +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins_mx51 { + MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1C, 0x7A8), + MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x20, 0x7A8), + MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x24, 0x7A8), + MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x28, 0x7A8), + MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2C, 0x7AC), + MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x30, 0x7AC), + MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x34, 0x7AC), + MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x38, 0x7AC), + MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3C, 0x7B0), + MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x40, 0x7B0), + MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x44, 0x7B0), + MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x48, 0x7B0), + MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x4C, 0x7BC), + MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x50, 0x7BC), + MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x54, 0x7BC), + MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x58, 0x7BC), + MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN_MX51(1, 0, 1, 0x5C, 0x3F0), + MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN_MX51(1, 1, 1, 0x60, 0x3F4), + MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN_MX51(1, 2, 1, 0x64, 0x3F8), + MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN_MX51(1, 3, 1, 0x68, 0x3FC), + MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN_MX51(1, 4, 1, 0x6C, 0x400), + MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN_MX51(1, 5, 1, 0x70, 0x404), + MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN_MX51(1, 6, 1, 0x74, 0x408), + MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN_MX51(1, 7, 1, 0x78, 0x40C), + MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN_MX51(1, 8, 1, 0x7C, 0x410), + MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x80, 0x414), + MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x84, 0x418), + MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN_MX51(1, 9, 1, 0x88, 0x41C), + MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x8C, 0x420), + MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x90, 0x424), + MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x94, 0x428), + MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x98, 0x42C), + MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN_MX51(1, 10, 1, 0x9C, 0x430), + MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN_MX51(1, 11, 1, 0xA0, 0x434), + MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN_MX51(1, 12, 1, 0xA4, 0x438), + MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN_MX51(1, 13, 1, 0xA8, 0x43C), + MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN_MX51(1, 14, 1, 0xAC, 0x440), + MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN_MX51(1, 15, 1, 0xB0, 0x444), + MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN_MX51(1, 16, 1, 0xB4, 0x448), + MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN_MX51(1, 17, 1, 0xB8, 0x44C), + MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN_MX51(1, 18, 1, 0xBC, 0x450), + MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN_MX51(1, 19, 1, 0xC0, 0x454), + MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN_MX51(1, 20, 1, 0xC4, 0x458), + MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN_MX51(1, 21, 1, 0xC8, 0x45C), + MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0xCC, 0x460), + MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0xD0, 0x464), + MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN_MX51(1, 22, 1, 0xD4, 0x468), + MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN_MX51(1, 23, 1, 0xD8, 0x46C), + MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN_MX51(1, 24, 1, 0xDC, 0x470), + MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN_MX51(1, 25, 1, 0xE0, 0x474), + MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN_MX51(1, 26, 1, 0xE4, 0x478), + MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN_MX51(1, 27, 1, 0xE8, 0x47C), + MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN_MX51(1, 28, 1, 0xEC, 0x480), + MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN_MX51(1, 29, 1, 0xF0, 0x484), + MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN_MX51(1, 30, 1, 0xF4, 0x488), + MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN_MX51(1, 31, 1, 0xF8, 0x48C), + MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN_MX51(2, 1, 1, 0xFC, 0x494), + MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN_MX51(2, 2, 1, 0x100, 0x4A0), + MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x104, 0x4D0), + MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN_MX51(2, 3, 3, 0x108, 0x4E4), + MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN_MX51(2, 4, 3, 0x10C, 0x4E8), + MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN_MX51(2, 5, 3, 0x110, 0x4EC), + MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN_MX51(2, 6, 3, 0x114, 0x4F0), + MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN_MX51(2, 7, 3, 0x118, 0x4F4), + MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN_MX51(2, 8, 3, 0x11C, 0x4F8), + MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN_MX51(2, 9, 3, 0x120, 0x4FC), + MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN_MX51(2, 10, 3, 0x124, 0x500), + MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN_MX51(2, 11, 3, 0x128, 0x504), + MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN_MX51(2, 12, 3, 0x12C, 0x514), + MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND, + MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN_MX51(2, 13, 3, 0x130, 0x5D8), + MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN_MX51(2, 14, 3, 0x134, 0x5DC), + MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN_MX51(2, 15, 3, 0x138, 0x5E0), + MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN_MX51(2, 16, 3, 0x130, 0x518), + MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN_MX51(2, 17, 3, 0x134, 0x51C), + MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN_MX51(2, 18, 3, 0x138, 0x520), + MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN_MX51(2, 19, 3, 0x13C, 0x524), + MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN_MX51(2, 20, 3, 0x140, 0x528), + MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN_MX51(2, 21, 3, 0x144, 0x52C), + MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN_MX51(2, 22, 3, 0x148, 0x530), + MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN_MX51(2, 23, 3, 0x14C, 0x534), + MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN_MX51(2, 24, 3, 0x150, 0x538), + MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN_MX51(2, 25, 3, 0x154, 0x53C), + MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN_MX51(2, 26, 3, 0x158, 0x540), + MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN_MX51(2, 27, 3, 0x15C, 0x544), + MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN_MX51(2, 28, 3, 0x160, 0x548), + MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN_MX51(2, 29, 3, 0x164, 0x54C), + MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN_MX51(2, 30, 3, 0x168, 0x550), + MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN_MX51(2, 31, 3, 0x16C, 0x554), + MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN_MX51(3, 0, 3, 0x170, 0x558), + MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN_MX51(3, 1, 3, 0x174, 0x55C), + MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN_MX51(3, 2, 3, 0x178, 0x560), + MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN_MX51(3, 3, 3, 0x17C, 0x564), + MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN_MX51(3, 4, 3, 0x180, 0x568), + MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN_MX51(3, 5, 3, 0x184, 0x56C), + MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN_MX51(3, 6, 3, 0x188, 0x570), + MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN_MX51(3, 7, 3, 0x18C, 0x574), + MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN_MX51(3, 8, 3, 0x190, 0x578), + MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN_MX51(2, 12, 3, 0x194, 0x57C), + MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN_MX51(2, 13, 3, 0x198, 0x580), + MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x19C, 0x584), + MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1A0, 0x588), + MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1A4, 0x58C), + MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1A8, 0x590), + MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1AC, 0x594), + MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1B0, 0x598), + MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1B4, 0x59C), + MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1B8, 0x5A0), + MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1BC, 0x5A4), + MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1C0, 0x5A8), + MX51_PIN_CSI1_VSYNC = _MXC_BUILD_GPIO_PIN_MX51(2, 14, 3, 0x1C4, 0x5AC), + MX51_PIN_CSI1_HSYNC = _MXC_BUILD_GPIO_PIN_MX51(2, 15, 3, 0x1C8, 0x5B0), + MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN_MX51(NON_MUX_I, 0x5B4), + MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN_MX51(NON_MUX_I, 0x5B8), + MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN_MX51(NON_MUX_I, 0x860), + MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN_MX51(3, 9, 3, 0x1CC, 0x5BC), + MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN_MX51(3, 10, 3, 0x1D0, 0x5C0), + MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN_MX51(3, 11, 3, 0x1D4, 0x5C4), + MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN_MX51(3, 12, 3, 0x1D8, 0x5C8), + MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN_MX51(3, 11, 3, 0x1DC, 0x5CC), + MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN_MX51(3, 12, 3, 0x1E0, 0x5D0), + MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN_MX51(3, 11, 3, 0x1E4, 0x5D4), + MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN_MX51(3, 12, 3, 0x1E8, 0x5D8), + MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN_MX51(3, 13, 3, 0x1EC, 0x5DC), + MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN_MX51(3, 14, 3, 0x1F0, 0x5E0), + MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN_MX51(3, 15, 3, 0x1F4, 0x5E4), + MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN_MX51(NON_MUX_I, 0x81C), + MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN_MX51(3, 16, 3, 0x1F8, 0x5E8), + MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN_MX51(3, 17, 3, 0x1FC, 0x5EC), + MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN_MX51(3, 18, 3, 0x200, 0x5F0), + MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN_MX51(3, 19, 3, 0x204, 0x5F4), + MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN_MX51(3, 20, 3, 0x208, 0x5F8), + MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN_MX51(3, 21, 3, 0x20C, 0x5FC), + MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN_MX51(3, 22, 3, 0x210, 0x600), + MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN_MX51(3, 23, 3, 0x214, 0x604), + MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN_MX51(3, 24, 3, 0x218, 0x608), + MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN_MX51(3, 25, 3, 0x21C, 0x60C), + MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN_MX51(3, 26, 3, 0x220, 0x610), + MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN_MX51(3, 27, 3, 0x224, 0x614), + MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN_MX51(3, 28, 3, 0x228, 0x618), + MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN_MX51(3, 29, 3, 0x22C, 0x61C), + MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN_MX51(3, 30, 3, 0x230, 0x620), + MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN_MX51(3, 31, 3, 0x234, 0x624), + MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN_MX51(0, 20, 3, 0x238, 0x628), + MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN_MX51(0, 21, 3, 0x23C, 0x62C), + MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN_MX51(0, 22, 3, 0x240, 0x630), + MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN_MX51(0, 23, 3, 0x244, 0x634), + MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN_MX51(0, 24, 3, 0x248, 0x638), + MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x24C, 0x63C), + MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x250, 0x640), + MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x254, 0x644), + MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x258, 0x648), + MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x25C, 0x64C), + MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x260, 0x650), + MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x264, 0x654), + MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x268, 0x658), + MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x26C, 0x65C), + MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x270, 0x660), + MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN_MX51(0, 25, 2, 0x278, 0x678), + MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN_MX51(0, 26, 2, 0x27C, 0x67C), + MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN_MX51(0, 27, 2, 0x280, 0x680), + MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN_MX51(0, 28, 2, 0x284, 0x684), + MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN_MX51(0, 11, 2, 0x288, 0x688), + MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN_MX51(0, 12, 2, 0x28C, 0x68C), + MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN_MX51(0, 13, 2, 0x290, 0x690), + MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN_MX51(0, 14, 2, 0x294, 0x694), + MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN_MX51(0, 15, 2, 0x298, 0x698), + MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN_MX51(0, 16, 2, 0x29C, 0x69C), + MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN_MX51(0, 17, 2, 0x2A0, 0x6A0), + MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN_MX51(0, 18, 2, 0x2A4, 0x6A4), + MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN_MX51(2, 0, 4, 0x2A8, 0x6A8), + MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN_MX51(2, 1, 4, 0x2AC, 0x6AC), + MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN_MX51(2, 2, 4, 0x2B0, 0x6B0), + MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN_MX51(2, 3, 4, 0x2B4, 0x6B4), + MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN_MX51(2, 4, 4, 0x2B8, 0x6B8), + MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN_MX51(2, 5, 4, 0x2BC, 0x6BC), + MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN_MX51(2, 6, 4, 0x2C0, 0x6C0), + MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN_MX51(2, 7, 4, 0x2C4, 0x6C4), + MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN_MX51(2, 8, 4, 0x2C8, 0x6C8), + MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2CC, 0x6CC), + MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2D0, 0x6D0), + MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2D4, 0x6D4), + MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2D8, 0x6D8), + MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2DC, 0x6DC), + MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2E0, 0x6E0), + MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2E4, 0x6E4), + MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2E8, 0x6E8), + MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2EC, 0x6EC), + MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2F0, 0x6F0), + MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2F4, 0x6F4), + MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2F8, 0x6F8), + MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2FC, 0x6FC), + MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x300, 0x700), + MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x304, 0x704), + MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x308, 0x708), + MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x30C, 0x70C), + MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x310, 0x710), + MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x314, 0x714), + MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x318, 0x718), + MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x31C, 0x71C), + MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x320, 0x720), + MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x324, 0x724), + MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x328, 0x728), + MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x32C, 0x72C), + MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x330, 0x734), + MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x334, 0x73C), + MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x338, 0x740), + MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x33C, 0x744), + MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x340, 0x748), + MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x344, 0x74C), + MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x348, 0x750), + MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN_MX51(0x34C, 0x754), + MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x350, 0x758), + MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x354, 0x75C), + MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x358, 0x760), + MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x35C, 0x764), + MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x360, 0x768), + MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x364, 0x76C), + MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x368, 0x770), + MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN_MX51(0, 19, 5, 0x36C, 0x774), + MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN_MX51(0, 29, 5, 0x370, 0x778), + MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN_MX51(0, 30, 5, 0x374, 0x77C), + MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN_MX51(0, 31, 5, 0x378, 0x780), + MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x37C, 0x784), + MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x380, 0x788), + MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x384, 0x78C), + MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x388, 0x790), + MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x38C, 0x794), + MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x390, 0x798), + MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN_MX51(0x394, 0x79C), + MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN_MX51(0x398, 0x7A0), + MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x39C, 0x7A4), + MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3A0, 0x7A8), + MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3A4, 0x7AC), + MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3A8, 0x7B0), + MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN_MX51(0, 0, 1, 0x3AC, 0x7B4), + MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN_MX51(0, 1, 1, 0x3B0, 0x7B8), + MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3B4, 0x7BC), + MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3B8, 0x7C0), + MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3BC, 0x7C4), + MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3C0, 0x7C8), + MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3C4, 0x7CC), + MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3C8, 0x7D0), + MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN_MX51(0, 2, 0, 0x3CC, 0x7D4), + MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN_MX51(0, 3, 0, 0x3D0, 0x7D8), + MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3D4, 0x7FC), + MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN_MX51(0, 4, 0, 0x3D8, 0x804), + MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN_MX51(0, 5, 0, 0x3DC, 0x808), + MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN_MX51(0, 6, 0, 0x3E0, 0x80C), + MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN_MX51(0, 7, 0, 0x3E4, 0x810), + MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN_MX51(0, 8, 0, 0x3E8, 0x814), + MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN_MX51(0, 9, 0, 0x3EC, 0x818), +}; + +/*! + * various IOMUX input select register index + */ +enum iomux_input_select_mx51 { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, + /* TO2 */ + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, + MUX_IN_FEC_FEC_CRS_SELECT_INPUT, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, + /* TO2 */ + MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, + MUX_INPUT_NUM_MUX, +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */ diff --git a/arch/arm/mach-mx5/mx53_ard.c b/arch/arm/mach-mx5/mx53_ard.c new file mode 100644 index 000000000000..dd59608dd338 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_ard.c @@ -0,0 +1,1322 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" +#include "devices.h" +#include "usb.h" + +#define ARD_SD1_CD (0*32 + 1) /* GPIO_1_1 */ +#define ARD_SD2_WP (0*32 + 2) /* GPIO_1_2 */ +#define ARD_SD2_CD (0*32 + 4) /* GPIO_1_4 */ +#define ARD_VIDEOIN_INT_B (0*32 + 7) /* GPIO_1_7 */ +#define ARD_SD1_WP (0*32 + 9) /* GPIO_1_9 */ +#define ARD_PMIC_RDY (0*32 + 24) /* GPIO_1_24 */ + + +#define ARD_CAN1_NERR_B (1*32 + 0) /* GPIO_2_0 */ +#define ARD_CAN2_NERR_B (1*32 + 1) /* GPIO_2_1 */ +#define ARD_VIDEOIN_PWR (1*32 + 2) /* GPIO_2_2 */ +#define ARD_I2CPORTEXP_B (1*32 + 3) /* GPIO_2_3 */ +#define ARD_ESAI_INT (1*32 + 4) /* GPIO_2_4 */ +#define ARD_GPS_PWREN (1*32 + 5) /* GPIO_2_5 */ +#define ARD_GPS_INT_B (1*32 + 6) /* GPIO_2_6 */ +#define ARD_MLB_INT (1*32 + 7) /* GPIO_2_7 */ +#define ARD_ETHERNET_INT_B (1*32 + 31) /* GPIO_2_31 */ + +#define ARD_SATE_REQ (3*32 + 0) /* GPIO_4_0 */ +#define ARD_USBH1_OC (3*32 + 1) /* GPIO_4_1 */ +#define ARD_USBH2_OC (3*32 + 2) /* GPIO_4_2 */ +#define ARD_USBH1_PWR (3*32 + 3) /* GPIO_4_3 */ +#define ARD_USER_LED (3*32 + 4) /* GPIO_4_4 */ +#define ARD_FPGA_INT_B (3*32 + 5) /* GPIO_4_5 */ +#define ARD_USBH2_PHYRST_B (3*32 + 14) /* GPIO_4_14 */ +#define ARD_CAN_STBY (3*32 + 15) /* GPIO_4_15 */ +#define ARD_PWM1_OFF (3*32 + 29) /* GPIO_4_29 */ +#define ARD_PWM2_OFF (3*32 + 30) /* GPIO_4_30 */ + +#define ARD_USBOTG_PWR (4*32 + 2) /* GPIO_5_2 */ +#define ARD_USBOTG_OC (4*32 + 4) /* GPIO_5_4 */ +#define ARD_PMIC_INT (4*32 + 7) /* GPIO_5_7 */ +#define ARD_PMIC_PBSTAT (4*32 + 8) /* GPIO_5_8 */ +#define ARD_MLB_PWRDN (4*32 + 9) /* GPIO_5_9 */ + +#define ARD_CAN_EN (6*32 + 6) /* GPIO_7_6 */ +#define ARD_TS_INT (6*32 + 12) /* GPIO_7_12 */ +#define ARD_SD1_LCTL (6*32 + 13) /* GPIO_7_13 */ + +/* Start directly after the CPU's GPIO*/ +#define MAX7310_BASE_ADDR 224 /* 7x32 */ +#define ARD_BACKLIGHT_ON MAX7310_BASE_ADDR +#define ARD_SPARE (MAX7310_BASE_ADDR + 1) +#define ARD_CPU_PER_RST_B (MAX7310_BASE_ADDR + 2) +#define ARD_MAIN_PER_RST_B (MAX7310_BASE_ADDR + 3) +#define ARD_IPOD_RST_B (MAX7310_BASE_ADDR + 4) +#define ARD_MLB_RST_B (MAX7310_BASE_ADDR + 5) +#define ARD_SSI_STEERING (MAX7310_BASE_ADDR + 6) +#define ARD_GPS_RST_B (MAX7310_BASE_ADDR + 7) + +/*! + * @file mach-mx53/mx53_ard.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX53 + */ + +static struct pad_desc mx53ard_pads[] = { + /* UART1 */ + MX53_PAD_ATA_DIOW__UART1_TXD, + MX53_PAD_ATA_DMACK__UART1_RXD, + + /* UART2 */ + MX53_PAD_ATA_BUFFER_EN__UART2_RXD, + MX53_PAD_ATA_DMARQ__UART2_TXD, + MX53_PAD_ATA_DIOR__UART2_RTS, + MX53_PAD_ATA_INTRQ__UART2_CTS, + + /* UART3 */ + MX53_PAD_ATA_CS_0__UART3_TXD, + MX53_PAD_ATA_CS_1__UART3_RXD, + MX53_PAD_ATA_DA_1__UART3_CTS, + MX53_PAD_ATA_DA_2__UART3_RTS, + + /* PMIC */ + MX53_PAD_DISP0_DAT13__GPIO_5_7, + MX53_PAD_FEC_RX_ER__GPIO_1_24, + MX53_PAD_DISP0_DAT14__GPIO_5_8, + + /* USBOTG_OC and USBOTG_PWR */ + MX53_PAD_EIM_A24__GPIO_5_4, + MX53_PAD_EIM_A25__GPIO_5_2, + + /* USBH */ + MX53_PAD_GPIO_11__GPIO_4_1, + MX53_PAD_GPIO_12__GPIO_4_2, + MX53_PAD_GPIO_13__GPIO_4_3, + MX53_PAD_KEY_COL4__GPIO_4_14, + + /* MAINBRD_SPDIF_IN */ + MX53_PAD_KEY_COL3__SPDIF_IN1, + + /* CAN */ + MX53_PAD_KEY_COL2__TXCAN1, + MX53_PAD_KEY_ROW2__RXCAN1, + MX53_PAD_ATA_RESET_B__TXCAN2, + MX53_PAD_ATA_IORDY__RXCAN2, + + /* CAN1, CAN2 -- EN */ + MX53_PAD_ATA_DA_0__GPIO_7_6, + /* CAN1, CAN2 -- STBY */ + MX53_PAD_KEY_ROW4__GPIO_4_15, + /* CAN1 -- NERR */ + MX53_PAD_ATA_DATA0__GPIO_2_0, + /* CAN2 -- NERR */ + MX53_PAD_ATA_DATA1__GPIO_2_1, + + MX53_PAD_DISP0_DAT0__USBH2_DAT0, + MX53_PAD_DISP0_DAT1__USBH2_DAT1, + MX53_PAD_DISP0_DAT2__USBH2_DAT2, + MX53_PAD_DISP0_DAT3__USBH2_DAT3, + MX53_PAD_DISP0_DAT4__USBH2_DAT4, + MX53_PAD_DISP0_DAT5__USBH2_DAT5, + MX53_PAD_DISP0_DAT6__USBH2_DAT6, + MX53_PAD_DISP0_DAT7__USBH2_DAT7, + MX53_PAD_DISP0_DAT8__PWM1, + MX53_PAD_DISP0_DAT9__PWM2, + MX53_PAD_DISP0_DAT10__USBH2_STP, + MX53_PAD_DISP0_DAT11__USBH2_NXT, + MX53_PAD_DISP0_DAT12__USBH2_CLK, + MX53_PAD_DI0_DISP_CLK__USBH2_DIR, + + MX53_PAD_LVDS0_TX3_P__LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LVDS0_TX0, + + MX53_PAD_LVDS1_TX3_P__LVDS1_TX3, + MX53_PAD_LVDS1_CLK_P__LVDS1_CLK, + MX53_PAD_LVDS1_TX2_P__LVDS1_TX2, + MX53_PAD_LVDS1_TX1_P__LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LVDS1_TX0, + + /* Bluetooth */ + MX53_PAD_DISP0_DAT23__AUD4_SSI_RXD, + MX53_PAD_DISP0_DAT21__AUD4_TXD, + MX53_PAD_DISP0_DAT20__AUD4_TXC, + MX53_PAD_DISP0_DAT22__AUD4_TXFS, + + /* Video in */ + MX53_PAD_CSI0_D4__CSI0_D4, + MX53_PAD_CSI0_D5__CSI0_D5, + MX53_PAD_CSI0_D6__CSI0_D6, + MX53_PAD_CSI0_D7__CSI0_D7, + MX53_PAD_CSI0_D8__CSI0_D8, + MX53_PAD_CSI0_D9__CSI0_D9, + MX53_PAD_CSI0_D10__CSI0_D10, + MX53_PAD_CSI0_D11__CSI0_D11, + MX53_PAD_CSI0_D12__CSI0_D12, + MX53_PAD_CSI0_D13__CSI0_D13, + MX53_PAD_CSI0_D14__CSI0_D14, + MX53_PAD_CSI0_D15__CSI0_D15, + MX53_PAD_CSI0_D16__CSI0_D16, + MX53_PAD_CSI0_D17__CSI0_D17, + MX53_PAD_CSI0_D18__CSI0_D18, + MX53_PAD_CSI0_D19__CSI0_D19, + + MX53_PAD_CSI0_VSYNC__CSI0_VSYNC, + MX53_PAD_CSI0_MCLK__CSI0_HSYNC, + MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK, + + /* VIDEO_ADC_PWRDN_B */ + MX53_PAD_GPIO_7__GPIO_1_7, + MX53_PAD_ATA_DATA2__GPIO_2_2, + + /* MLB */ + MX53_PAD_FEC_TXD1__MLBCLK, + MX53_PAD_FEC_MDC__MLBDAT, + MX53_PAD_GPIO_6__MLBSIG, + MX53_PAD_ATA_DATA7__GPIO_2_7, + MX53_PAD_DISP0_DAT15__GPIO_5_9, + + /* esdhc1 */ + MX53_PAD_SD1_CMD__SD1_CMD, + MX53_PAD_SD1_CLK__SD1_CLK, + MX53_PAD_SD1_DATA0__SD1_DATA0, + MX53_PAD_SD1_DATA1__SD1_DATA1, + MX53_PAD_SD1_DATA2__SD1_DATA2, + MX53_PAD_SD1_DATA3__SD1_DATA3, + MX53_PAD_ATA_DATA8__SD1_DATA4, + MX53_PAD_ATA_DATA9__SD1_DATA5, + MX53_PAD_ATA_DATA10__SD1_DATA6, + MX53_PAD_ATA_DATA11__SD1_DATA7, + MX53_PAD_GPIO_1__GPIO_1_1, + MX53_PAD_GPIO_9__GPIO_1_9, + + /* esdhc2 */ + MX53_PAD_SD2_DATA0__SD2_DAT0, + MX53_PAD_SD2_DATA1__SD2_DAT1, + MX53_PAD_SD2_DATA2__SD2_DAT2, + MX53_PAD_SD2_DATA3__SD2_DAT3, + MX53_PAD_ATA_DATA12__SD2_DAT4, + MX53_PAD_ATA_DATA13__SD2_DAT5, + MX53_PAD_ATA_DATA14__SD2_DAT6, + MX53_PAD_ATA_DATA15__SD2_DAT7, + MX53_PAD_SD2_CLK__SD2_CLK, + MX53_PAD_SD2_CMD__SD2_CMD, + MX53_PAD_GPIO_4__GPIO_1_4, + MX53_PAD_GPIO_2__GPIO_1_2, + + /* WEIM for CS1 */ + /* ETHERNET_INT_B */ + MX53_PAD_EIM_EB3__GPIO_2_31, + MX53_PAD_EIM_D16__EIM_D16, + MX53_PAD_EIM_D17__EIM_D17, + MX53_PAD_EIM_D18__EIM_D18, + MX53_PAD_EIM_D19__EIM_D19, + MX53_PAD_EIM_D20__EIM_D20, + MX53_PAD_EIM_D21__EIM_D21, + MX53_PAD_EIM_D22__EIM_D22, + MX53_PAD_EIM_D23__EIM_D23, + MX53_PAD_EIM_D24__EIM_D24, + MX53_PAD_EIM_D25__EIM_D25, + MX53_PAD_EIM_D26__EIM_D26, + MX53_PAD_EIM_D27__EIM_D27, + MX53_PAD_EIM_D28__EIM_D28, + MX53_PAD_EIM_D29__EIM_D29, + MX53_PAD_EIM_D30__EIM_D30, + MX53_PAD_EIM_D31__EIM_D31, + MX53_PAD_EIM_DA0__EIM_DA0, + MX53_PAD_EIM_DA1__EIM_DA1, + MX53_PAD_EIM_DA2__EIM_DA2, + MX53_PAD_EIM_DA3__EIM_DA3, + MX53_PAD_EIM_DA4__EIM_DA4, + MX53_PAD_EIM_DA5__EIM_DA5, + MX53_PAD_EIM_DA6__EIM_DA6, + MX53_PAD_EIM_OE__EIM_OE, + MX53_PAD_EIM_RW__EIM_RW, + MX53_PAD_EIM_CS1__EIM_CS1, + + /* I2C2 */ + MX53_PAD_EIM_EB2__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, + + /* I2C3 */ + MX53_PAD_GPIO_3__I2C3_SCL, + MX53_PAD_GPIO_16__I2C3_SDA, + + /* TOUCH_INT_B */ + MX53_PAD_GPIO_17__GPIO_7_12, + + /* Tuner */ + MX53_PAD_DI0_PIN15__AUD6_TXC, + MX53_PAD_DI0_PIN4__AUD6_RXD, + MX53_PAD_DI0_PIN3__AUD6_TXFS, + + /* FPGA */ + MX53_PAD_EIM_A23__EIM_A23, + MX53_PAD_GPIO_19__GPIO_4_5, + + /* eCSPI */ + MX53_PAD_DISP0_DAT16__ECSPI2_MOSI, + MX53_PAD_DISP0_DAT17__ECSPI2_MISO, + MX53_PAD_DISP0_DAT18__ECSPI2_SS0, + MX53_PAD_DISP0_DAT19__ECSPI2_SCLK, + + /* NAND */ + MX53_PAD_NANDF_CLE__NANDF_CLE, + MX53_PAD_NANDF_ALE__NANDF_ALE, + MX53_PAD_NANDF_WP_B__NANDF_WP_B, + MX53_PAD_NANDF_WE_B__NANDF_WE_B, + MX53_PAD_NANDF_RE_B__NANDF_RE_B, + MX53_PAD_NANDF_RB0__NANDF_RB0, + MX53_PAD_NANDF_CS0__NANDF_CS0, + MX53_PAD_NANDF_CS1__NANDF_CS1 , + MX53_PAD_EIM_DA0__EIM_DA0, + MX53_PAD_EIM_DA1__EIM_DA1, + MX53_PAD_EIM_DA2__EIM_DA2, + MX53_PAD_EIM_DA3__EIM_DA3, + MX53_PAD_EIM_DA4__EIM_DA4, + MX53_PAD_EIM_DA5__EIM_DA5, + MX53_PAD_EIM_DA6__EIM_DA6, + MX53_PAD_EIM_DA7__EIM_DA7, + + /* IO Port Expander */ + MX53_PAD_ATA_DATA3__GPIO_2_3, + + /* GPS */ + MX53_PAD_GPIO_0__CLKO, + MX53_PAD_ATA_DATA5__GPIO_2_5, + MX53_PAD_ATA_DATA6__GPIO_2_6, + + MX53_PAD_GPIO_10__GPIO_4_0, + MX53_PAD_GPIO_14__GPIO_4_4, + MX53_PAD_GPIO_18__GPIO_7_13, + MX53_PAD_GPIO_19__GPIO_4_5, + + /* EIM_WAIT, EIM_OE ... */ +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 1600x1200 @ 60 Hz 162M pixel clk*/ + "UXGA", 60, 1600, 1200, 6172, + 304, 64, + 1, 46, + 192, 3, + FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, + /* 2 LVDS modes, had better remove from here */ + { + "1080P60", 60, 1920, 1080, 7692, + 100, 40, + 30, 3, + 10, 2, + 0, + FB_VMODE_NONINTERLACED, + 0,}, + { + "XGA", 60, 1024, 768, 15385, + 220, 40, + 21, 7, + 60, 10, + 0, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct pad_desc mx53_ard_pwm_pads[] = { + MX53_PAD_DISP0_DAT8__PWM1, + MX53_PAD_DISP0_DAT9__PWM2, + MX53_PAD_DISP0_DAT8__GPIO_4_29, + MX53_PAD_DISP0_DAT9__GPIO_4_30, +}; + +static void enable_pwm1_pad(void) +{ + mxc_iomux_v3_setup_pad(&mx53_ard_pwm_pads[0]); +} + +static void disable_pwm1_pad(void) +{ + mxc_iomux_v3_setup_pad(&mx53_ard_pwm_pads[2]); + + gpio_request(ARD_PWM2_OFF, "pwm2-off"); + gpio_direction_output(ARD_PWM2_OFF, 1); + gpio_free(ARD_PWM2_OFF); +} + +static struct mxc_pwm_platform_data mxc_pwm1_platform_data = { + .pwmo_invert = 1, + .enable_pwm_pad = enable_pwm1_pad, + .disable_pwm_pad = disable_pwm1_pad, +}; + +static struct platform_pwm_backlight_data mxc_pwm1_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 5000000, +}; + +static void enable_pwm2_pad(void) +{ + mxc_iomux_v3_setup_pad(&mx53_ard_pwm_pads[1]); +} + +static void disable_pwm2_pad(void) +{ + mxc_iomux_v3_setup_pad(&mx53_ard_pwm_pads[3]); + + gpio_request(ARD_PWM2_OFF, "pwm2-off"); + gpio_direction_output(ARD_PWM2_OFF, 1); + gpio_free(ARD_PWM2_OFF); +} + +static struct mxc_pwm_platform_data mxc_pwm2_platform_data = { + .pwmo_invert = 1, + .enable_pwm_pad = enable_pwm2_pad, + .disable_pwm_pad = disable_pwm2_pad, +}; + +static struct platform_pwm_backlight_data mxc_pwm2_backlight_data = { + .pwm_id = 1, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 5000000, +}; + +static void flexcan_xcvr_enable(int id, int en) +{ + if (id < 0 || id > 1) + return; + + if (en) + gpio_set_value(ARD_CAN_EN, 1); + else + gpio_set_value(ARD_CAN_EN, 0); +} + +static struct flexcan_platform_data flexcan0_data = { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 5, + .br_propseg = 5, + .br_pseg1 = 4, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .smp = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, +}; +static struct flexcan_platform_data flexcan1_data = { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 5, + .br_propseg = 5, + .br_pseg1 = 4, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, +}; + + +extern void mx5_ipu_reset(void); +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 3, + .reset = mx5_ipu_reset, +}; + +extern void mx5_vpu_reset(void); +static struct mxc_vpu_platform_data mxc_vpu_data = { + .reset = mx5_vpu_reset, +}; + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, +}; + +static struct imxi2c_platform_data mxci2c1_data = { + .bitrate = 50000, +}; + +static struct imxi2c_platform_data mxci2c2_data = { + .bitrate = 400000, +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "SW1", + .lp_reg_id = "SW2", +}; + +static struct ldb_platform_data ldb_data = { + .ext_ref = 1, +}; + +static void mxc_iim_enable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg |= 0x10; + writel(reg, ccm_base + 0x64); +} + +static void mxc_iim_disable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg &= ~0x10; + writel(reg, ccm_base + 0x64); +} + +static struct mxc_iim_data iim_data = { + .bank_start = MXC_IIM_MX53_BANK_START_ADDR, + .bank_end = MXC_IIM_MX53_BANK_END_ADDR, + .enable_fuse = mxc_iim_enable_fuse, + .disable_fuse = mxc_iim_disable_fuse, +}; + +static struct pad_desc mx53_ard_esai_pads[] = { + MX53_PAD_FEC_MDIO__ESAI_SCKR, + MX53_PAD_FEC_REF_CLK__ESAI_FSR, + MX53_PAD_FEC_CRS_DV__ESAI_SCKT, + MX53_PAD_FEC_RXD1__ESAI_FST, + MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2, + MX53_PAD_GPIO_5__ESAI_TX2_RX3, + MX53_PAD_FEC_TXD0__ESAI_TX4_RX1, + MX53_PAD_GPIO_8__ESAI_TX5_RX0, + MX53_PAD_NANDF_CS2__ESAI_TX0, + MX53_PAD_NANDF_CS3__ESAI_TX1, + MX53_PAD_ATA_DATA4__GPIO_2_4, +}; + + +void ard_gpio_activate_esai_ports(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53_ard_esai_pads, + ARRAY_SIZE(mx53_ard_esai_pads)); + /* ESAI_INT */ + gpio_request(ARD_ESAI_INT, "esai-int"); + gpio_direction_input(ARD_ESAI_INT); + +} + +static struct mxc_esai_platform_data esai_data = { + .activate_esai_ports = ard_gpio_activate_esai_ports, +}; + +static void mx53_ard_usbotg_driver_vbus(bool on) +{ + if (on) + gpio_set_value(ARD_USBOTG_PWR, 1); + else + gpio_set_value(ARD_USBOTG_PWR, 0); +} + +static void mx53_ard_host1_driver_vbus(bool on) +{ + if (on) + gpio_set_value(ARD_USBH1_PWR, 1); + else + gpio_set_value(ARD_USBH1_PWR, 0); +} + +static void adv7180_pwdn(int pwdn) +{ + gpio_request(ARD_VIDEOIN_PWR, "tvin-pwr"); + if (pwdn) + gpio_set_value(ARD_VIDEOIN_PWR, 0); + else + gpio_set_value(ARD_VIDEOIN_PWR, 1); + gpio_free(ARD_VIDEOIN_PWR); +} + +static struct mxc_tvin_platform_data adv7180_data = { + .dvddio_reg = NULL, + .dvdd_reg = NULL, + .avdd_reg = NULL, + .pvdd_reg = NULL, + .pwdn = adv7180_pwdn, + .reset = NULL, + .cvbs = true, +}; + +static struct resource mxcfb_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "800x480M@55", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, + { + .interface_pix_fmt = IPU_PIX_FMT_GBR24, + .mode_str = "1024x768M-16@60", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +extern int primary_di; +static int __init mxc_init_fb(void) +{ + if (!machine_is_mx53_ard()) + return 0; + + if (primary_di) { + printk(KERN_INFO "DI1 is primary\n"); + /* DI1 -> DP-BG channel: */ + mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[1].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + + /* DI0 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + } else { + printk(KERN_INFO "DI0 is primary\n"); + + /* DI0 -> DP-BG channel: */ + mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[0].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + + /* DI1 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + } + + /* + * DI0/1 DP-FG channel: + */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +device_initcall(mxc_init_fb); + +static struct mxc_audio_codec_platform_data cs42888_data = { + .analog_regulator = NULL, +}; + +static int mx53_ard_max7310_setup(struct i2c_client *client, + unsigned gpio_base, unsigned ngpio, + void *context) +{ + static int max7310_gpio_value[] = { + 1, 1, 1, 1, 0, 0, 0, 0, + }; + int n; + + for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) { + gpio_request(gpio_base + n, "MAX7310 GPIO Expander"); + if (max7310_gpio_value[n] < 0) + gpio_direction_input(gpio_base + n); + else + gpio_direction_output(gpio_base + n, + max7310_gpio_value[n]); + /* Export, direction locked down */ + gpio_export(gpio_base + n, 0); + } + + return 0; +} + +static struct pca953x_platform_data mx53_i2c_max7310_platdata = { + .gpio_base = MAX7310_BASE_ADDR, + .invert = 0, /* Do not invert */ + .setup = mx53_ard_max7310_setup, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "cs42888", + .addr = 0x48, + .platform_data = &cs42888_data, + }, + { + .type = "ipod", + .addr = 0x10, + }, + { + .type = "tuner", + .addr = 0x62, + }, +}; + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + .type = "max11801", + .addr = 0x49, + .irq = IOMUX_TO_IRQ_V3(ARD_TS_INT), + }, + { + .type = "max7310", + .addr = 0x18, + .platform_data = &mx53_i2c_max7310_platdata, + }, + { + .type = "mlb", + .addr = 0x20, + }, + { + .type = "adv7180", + .addr = 0x21, + .platform_data = (void *)&adv7180_data, + }, +}; + +static struct mtd_partition mxc_dataflash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x000100000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, +}; + +static struct flash_platform_data mxc_spi_flash_data[] = { + { + .name = "mxc_dataflash", + .parts = mxc_dataflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), + .type = "at45db321d",} +}; + + +static struct spi_board_info mxc_dataflash_device[] __initdata = { + { + .modalias = "mxc_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[0],}, +}; + +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(ARD_SD1_WP); + else + rc = gpio_get_value(ARD_SD2_WP); + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret; + if (to_platform_device(dev)->id == 0) { + ret = gpio_get_value(ARD_SD1_CD); + } else{ /* config the det pin for SDHC2 */ + ret = gpio_get_value(ARD_SD2_CD); + } + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static struct resource ard_smsc911x_resources[] = { + { + .start = MX53_CS1_BASE_ADDR, + .end = MX53_CS1_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IOMUX_TO_IRQ_V3(ARD_ETHERNET_INT_B), + .end = IOMUX_TO_IRQ_V3(ARD_ETHERNET_INT_B), + .flags = IORESOURCE_IRQ, + }, +}; + +struct smsc911x_platform_config ard_smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device ard_smsc_lan9220_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(ard_smsc911x_resources), + .resource = ard_smsc911x_resources, +}; + +static struct mxc_mlb_platform_data mlb_data = { + .reg_nvcc = NULL, + .mlb_clk = "mlb_clk", +}; + +/* NAND Flash Partitions */ +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition nand_flash_partitions[] = { +/* MX53 ROM require the boot FCB/DBBT support which need + * more space to store such info on NAND boot partition. + * 16M should cover all kind of NAND boot support on MX53. + */ + { + .name = "bootloader", + .offset = 0, + .size = 16 * 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs1", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; +#endif + +static int nand_init(void) +{ + u32 i, reg; + void __iomem *base; + + #define M4IF_GENP_WEIM_MM_MASK 0x00000001 + #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 + + base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); + reg = __raw_readl(base + 0xc); + reg &= ~M4IF_GENP_WEIM_MM_MASK; + __raw_writel(reg, base + 0xc); + + iounmap(base); + + base = ioremap(MX53_BASE_ADDR(WEIM_BASE_ADDR), SZ_4K); + for (i = 0x4; i < 0x94; i += 0x18) { + reg = __raw_readl((u32)base + i); + reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; + __raw_writel(reg, (u32)base + i); + } + + iounmap(base); + + return 0; +} + +static struct flash_platform_data mxc_nand_data = { +#ifdef CONFIG_MTD_PARTITIONS + .parts = nand_flash_partitions, + .nr_parts = ARRAY_SIZE(nand_flash_partitions), +#endif + .width = 1, + .init = nand_init, +}; + +static struct mxc_asrc_platform_data mxc_asrc_data = { + .channel_bits = 4, + .clk_map_ver = 2. +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 0, + .spdif_rx = 1, + .spdif_clk_44100 = 0, /* Souce from CKIH1 for 44.1K */ + .spdif_clk_48000 = 7, /* Source from CKIH2 for 48k and 32k */ + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static struct mxc_audio_platform_data mxc_surround_audio_data = { + .ext_ram = 1, + .sysclk = 24576000, +}; + + +static struct platform_device mxc_alsa_surround_device = { + .name = "imx-3stack-cs42888", +}; + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + struct tag *t; + struct tag *mem_tag = 0; + int total_mem = SZ_1G; + int left_mem = 0; + int gpu_mem = SZ_128M; + int fb_mem = SZ_32M; + char *str; + + mxc_set_cpu_type(MXC_CPU_MX53); + + for_each_tag(mem_tag, tags) { + if (mem_tag->hdr.tag == ATAG_MEM) { + total_mem = mem_tag->u.mem.size; + left_mem = total_mem - gpu_mem - fb_mem; + break; + } + } + + for_each_tag(t, tags) { + if (t->hdr.tag == ATAG_CMDLINE) { + str = t->u.cmdline.cmdline; + str = strstr(str, "mem="); + if (str != NULL) { + str += 4; + left_mem = memparse(str, &str); + if (left_mem == 0 || left_mem > total_mem) + left_mem = total_mem - gpu_mem - fb_mem; + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_memory="); + if (str != NULL) { + str += 11; + gpu_mem = memparse(str, &str); + } + + break; + } + } + + if (mem_tag) { + fb_mem = total_mem - left_mem - gpu_mem; + if (fb_mem < 0) { + gpu_mem = total_mem - left_mem; + fb_mem = 0; + } + mem_tag->u.mem.size = left_mem; + + /*reserve memory for gpu*/ + gpu_device.resource[5].start = + mem_tag->u.mem.start + left_mem; + gpu_device.resource[5].end = + gpu_device.resource[5].start + gpu_mem - 1; +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) + if (fb_mem) { + mxcfb_resources[0].start = + gpu_device.resource[5].end + 1; + mxcfb_resources[0].end = + mxcfb_resources[0].start + fb_mem - 1; + } else { + mxcfb_resources[0].start = 0; + mxcfb_resources[0].end = 0; + } +#endif + } +} + +static void __init mx53_ard_io_init(void) +{ + /* MX53 ARD board */ + pr_info("MX53 ARD board \n"); + mxc_iomux_v3_setup_multiple_pads(mx53ard_pads, + ARRAY_SIZE(mx53ard_pads)); + + /* USBOTG_OC */ + gpio_request(ARD_USBOTG_OC, "otg-oc"); + gpio_direction_input(ARD_USBOTG_OC); + /* USBOTG_PWR */ + gpio_request(ARD_USBOTG_PWR, "otg-pwr"); + gpio_direction_output(ARD_USBOTG_PWR, 1); + + gpio_request(ARD_USBH1_OC, "usbh1-oc"); + gpio_direction_input(ARD_USBH1_OC); + + gpio_request(ARD_USBH2_OC, "usbh2-oc"); + gpio_direction_input(ARD_USBH2_OC); + + gpio_request(ARD_USBH1_PWR, "usbh1-pwr"); + gpio_direction_output(ARD_USBH1_PWR, 1); + + gpio_request(ARD_USBH2_PHYRST_B, "usbh2-phyrst"); + gpio_direction_output(ARD_USBH2_PHYRST_B, 1); + + gpio_request(ARD_SD1_CD, "sdhc1-cd"); + gpio_direction_input(ARD_SD1_CD); /* SD1 CD */ + gpio_request(ARD_SD1_WP, "sdhc1-wp"); + gpio_direction_input(ARD_SD1_WP); /* SD1 WP */ + + /* SD2 CD */ + gpio_request(ARD_SD2_CD, "sdhc2-cd"); + gpio_direction_input(ARD_SD2_CD); + + /* SD2 WP */ + gpio_request(ARD_SD2_WP, "sdhc2-wp"); + gpio_direction_input(ARD_SD2_WP); + + gpio_request(ARD_PMIC_INT, "pmic-int"); + gpio_direction_input(ARD_PMIC_INT); /*PMIC_INT*/ + gpio_request(ARD_PMIC_RDY, "pmic-rdy"); + gpio_direction_input(ARD_PMIC_RDY); /*PMIC_RDY*/ + gpio_request(ARD_PMIC_PBSTAT, "pmic-pbstat"); + gpio_direction_input(ARD_PMIC_PBSTAT); /*PMIC_PBSTAT*/ + + /* CAN1 enable GPIO*/ + gpio_request(ARD_CAN_EN, "can-en"); + gpio_direction_output(ARD_CAN_EN, 0); + + gpio_request(ARD_CAN_STBY, "can-stby"); + gpio_direction_output(ARD_CAN_STBY, 0); + + gpio_request(ARD_CAN1_NERR_B, "can1-nerr"); + gpio_direction_input(ARD_CAN1_NERR_B); + + gpio_request(ARD_CAN2_NERR_B, "can2-nerr"); + gpio_direction_input(ARD_CAN2_NERR_B); + + gpio_request(ARD_VIDEOIN_PWR, "videoin-pwr"); + gpio_direction_output(ARD_VIDEOIN_PWR, 0); + + gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst"); + gpio_direction_output(ARD_I2CPORTEXP_B, 1); + + gpio_request(ARD_GPS_PWREN, "gps-pwren"); + gpio_direction_output(ARD_GPS_PWREN, 1); + + gpio_request(ARD_GPS_INT_B, "gps-int"); + gpio_direction_input(ARD_GPS_INT_B); + + gpio_request(ARD_MLB_INT, "mlb-int"); + gpio_direction_input(ARD_MLB_INT); + + gpio_request(ARD_MLB_PWRDN, "mlb-pwrdn"); + gpio_direction_input(ARD_MLB_PWRDN); + + gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); + gpio_direction_input(ARD_ETHERNET_INT_B); + + gpio_request(ARD_FPGA_INT_B, "fpga-int"); + gpio_direction_input(ARD_FPGA_INT_B); + + gpio_request(ARD_TS_INT, "ts-int"); + gpio_direction_input(ARD_TS_INT); + gpio_free(ARD_TS_INT); +} + +/* Config CS1 settings for ethernet controller */ +static void weim_cs_config(void) +{ + u32 reg; + void __iomem *weim_base, *iomuxc_base; + + weim_base = ioremap(MX53_BASE_ADDR(WEIM_BASE_ADDR), SZ_4K); + iomuxc_base = ioremap(MX53_BASE_ADDR(IOMUXC_BASE_ADDR), SZ_4K); + + /* CS1 timings for LAN9220 */ + writel(0x20001, (weim_base + 0x18)); + writel(0x0, (weim_base + 0x1C)); + writel(0x16000202, (weim_base + 0x20)); + writel(0x00000002, (weim_base + 0x24)); + writel(0x16002082, (weim_base + 0x28)); + writel(0x00000000, (weim_base + 0x2C)); + writel(0x00000000, (weim_base + 0x90)); + + /* specify 64 MB on CS1 and CS0 on GPR1 */ + reg = readl(iomuxc_base + 0x4); + reg &= ~0x3F; + reg |= 0x1B; + writel(reg, (iomuxc_base + 0x4)); + + iounmap(iomuxc_base); + iounmap(weim_base); +} + +static int mxc_read_mac_iim(void) +{ + struct clk *iim_clk; + void __iomem *iim_base = IO_ADDRESS(IIM_BASE_ADDR); + void __iomem *iim_mac_base = iim_base + \ + MXC_IIM_MX53_BANK_AREA_1_OFFSET + \ + MXC_IIM_MX53_MAC_ADDR_OFFSET; + int i; + + iim_clk = clk_get(NULL, "iim_clk"); + + if (!iim_clk) { + printk(KERN_ERR "Could not get IIM clk to read MAC fuses!\n"); + return ~EINVAL; + } + + clk_enable(iim_clk); + + for (i = 0; i < 6; i++) + ard_smsc911x_config.mac[i] = readl(iim_mac_base + (i*4)); + + clk_disable(iim_clk); + return 0; +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "ssi_ext1_clk"); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); + + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(ARD_SD2_CD); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(ARD_SD2_CD); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(ARD_SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(ARD_SD1_CD); + + mxc_cpu_common_init(); + + mx53_ard_io_init(); + weim_cs_config(); + mxc_read_mac_iim(); + mxc_register_device(&ard_smsc_lan9220_device, &ard_smsc911x_config); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c1_data); + mxc_register_device(&mxci2c_devices[2], &mxci2c2_data); + + mxc_register_device(&mxc_rtc_device, NULL); + mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); + mxc_register_device(&mxc_ldb_device, &ldb_data); + mxc_register_device(&mxcvpu_device, &mxc_vpu_data); + mxc_register_device(&gpu_device, &z160_revision); + mxc_register_device(&mxcscc_device, NULL); + + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&busfreq_device, &bus_freq_data); + + mxc_register_device(&mxc_iim_device, &iim_data); + + mxc_register_device(&mxc_pwm1_device, &mxc_pwm1_platform_data); + mxc_register_device(&mxc_pwm1_backlight_device, + &mxc_pwm1_backlight_data); + + mxc_register_device(&mxc_pwm2_device, &mxc_pwm2_platform_data); + mxc_register_device(&mxc_pwm2_backlight_device, + &mxc_pwm2_backlight_data); + + mxc_register_device(&mxc_flexcan0_device, &flexcan0_data); + mxc_register_device(&mxc_flexcan1_device, &flexcan1_data); + + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + + mxc_register_device(&ahci_fsl_device, &sata_data); + + /* ASRC is only available for MX53 TO2.0 */ + if (cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) { + mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + clk_put(mxc_asrc_data.asrc_core_clk); + mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); + clk_put(mxc_asrc_data.asrc_audio_clk); + mxc_register_device(&mxc_asrc_device, &mxc_asrc_data); + } + + mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); + + spi_register_board_info(mxc_dataflash_device, + ARRAY_SIZE(mxc_dataflash_device)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + i2c_register_board_info(2, mxc_i2c2_board_info, + ARRAY_SIZE(mxc_i2c2_board_info)); + + mxc_register_device(&mxc_mlb_device, &mlb_data); + mx5_set_otghost_vbus_func(mx53_ard_usbotg_driver_vbus); + mx5_usb_dr_init(); + mx5_set_host1_vbus_func(mx53_ard_host1_driver_vbus); + mx5_usbh1_init(); + mx5_usbh2_init(); + mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data); + mxc_register_device(&mxc_esai_device, &esai_data); + mxc_register_device(&mxc_alsa_surround_device, + &mxc_surround_audio_data); + + mxc_register_device(&mxc_v4l2out_device, NULL); + mxc_register_device(&mxc_v4l2_device, NULL); +} + +static void __init mx53_ard_timer_init(void) +{ + struct clk *uart_clk; + + mx53_clocks_init(32768, 24000000, 22579200, 24576000); + + uart_clk = clk_get_sys("mxcintuart.0", NULL); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx53_ard_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX53_ARD data structure. + */ +MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx53_ard_pmic_ltc3589.c b/arch/arm/mach-mx5/mx53_ard_pmic_ltc3589.c new file mode 100644 index 000000000000..02538815d2a4 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_ard_pmic_ltc3589.c @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * mx53_ard_pmic_ltc3589.c -- i.MX53 ARD Driver for Linear LTC3589 + * PMIC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ARD_PMIC_INT (4*32 + 7) /* GPIO_5_7 */ + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +struct ltc3589; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = 564000, + .max_uV = 1167000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = 704000, + .max_uV = 1456000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = 1342000, + .max_uV = 2775000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .apply_uV = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data ldo1_init = { + .constraints = { + .name = "LDO1_STBY", + .apply_uV = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data ldo2_init = { + .constraints = { + .name = "LDO2", + .min_uV = 704000, + .max_uV = 1456000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data ldo3_init = { + .constraints = { + .name = "LDO3", + .apply_uV = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data ldo4_init = { + .constraints = { + .name = "LDO4", + .min_uV = 1800000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .always_on = 1, + .boot_on = 1, + }, +}; + +static void ltc3589_nop_release(struct device *dev) +{ + /* Nothing */ +} + +static struct platform_device ltc3589_regulator_device[] = { + { + .name = "ltc3589-dev", + .id = 0, + .dev = { + .release = ltc3589_nop_release, + }, + }, +}; + +static int mx53_ltc3589_init(struct ltc3589 *ltc3589) +{ + int i; + + printk(KERN_INFO "Initializing regulators for ARD\n"); + for (i = 0; i < ARRAY_SIZE(ltc3589_regulator_device); i++) { + if (platform_device_register(<c3589_regulator_device[i]) < 0) + dev_err(<c3589_regulator_device[i].dev, + "Unable to register LTC3589 device\n"); + } + + ltc3589_register_regulator(ltc3589, LTC3589_SW1, &sw1_init); + ltc3589_register_regulator(ltc3589, LTC3589_SW2, &sw2_init); + ltc3589_register_regulator(ltc3589, LTC3589_SW3, &sw3_init); + ltc3589_register_regulator(ltc3589, LTC3589_SW4, &sw4_init); + ltc3589_register_regulator(ltc3589, LTC3589_LDO1, &ldo1_init); + ltc3589_register_regulator(ltc3589, LTC3589_LDO2, &ldo2_init); + ltc3589_register_regulator(ltc3589, LTC3589_LDO3, &ldo3_init); + ltc3589_register_regulator(ltc3589, LTC3589_LDO4, &ldo4_init); + + return 0; +} + +static struct ltc3589_platform_data __initdata ltc3589_plat = { + .init = mx53_ltc3589_init, +}; + +static struct i2c_board_info __initdata ltc3589_i2c_device = { + I2C_BOARD_INFO("ltc3589", 0x34), + .irq = IOMUX_TO_IRQ_V3(ARD_PMIC_INT), + .platform_data = <c3589_plat, +}; + +static __init int mx53_init_i2c(void) +{ + return i2c_register_board_info(1, <c3589_i2c_device, 1); +} + +subsys_initcall(mx53_init_i2c); + +static __init int ltc3589_pmic_init(void) +{ + int i = 0; + int ret = 0; + struct regulator *regulator; + + char *ltc3589_global_regulator[] = { + "SW1", + "SW2", + "SW3", + "SW4", + "LDO1_STBY", + "LDO2", + "LDO3", + "LDO4", + }; + + while ((i < ARRAY_SIZE(ltc3589_global_regulator)) && + !IS_ERR_VALUE( + (unsigned long)(regulator = + regulator_get(NULL, + ltc3589_global_regulator + [i])))) { + regulator_enable(regulator); + i++; + } + + return ret; +} + +late_initcall(ltc3589_pmic_init); + diff --git a/arch/arm/mach-mx5/mx53_evk.c b/arch/arm/mach-mx5/mx53_evk.c new file mode 100644 index 000000000000..092aec5498d0 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_evk.c @@ -0,0 +1,1562 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" +#include "devices.h" +#include "usb.h" + +#define ARM2_SD1_CD (0*32 + 1) /* GPIO_1_1 */ + +#define MX53_HP_DETECT (1*32 + 5) /* GPIO_2_5 */ + +#define EVK_SD3_CD (2*32 + 11) /* GPIO_3_11 */ +#define EVK_SD3_WP (2*32 + 12) /* GPIO_3_12 */ +#define EVK_SD1_CD (2*32 + 13) /* GPIO_3_13 */ +#define EVK_SD1_WP (2*32 + 14) /* GPIO_3_14 */ +#define ARM2_OTG_VBUS (2*32 + 22) /* GPIO_3_22 */ +#define MX53_DVI_PD (2*32 + 24) /* GPIO_3_24 */ +#define EVK_TS_INT (2*32 + 26) /* GPIO_3_26 */ +#define MX53_DVI_I2C (2*32 + 28) /* GPIO_3_28 */ +#define MX53_DVI_DETECT (2*32 + 31) /* GPIO_3_31 */ + +#define MX53_CAM_RESET (3*32 + 0) /* GPIO_4_0 */ +#define MX53_ESAI_RESET (3*32 + 2) /* GPIO_4_2 */ +#define MX53_CAN2_EN2 (3*32 + 4) /* GPIO_4_4 */ +#define MX53_12V_EN (3*32 + 5) /* GPIO_4_5 */ +#define ARM2_LCD_CONTRAST (3*32 + 20) /* GPIO_4_20 */ + +#define MX53_DVI_RESET (4*32 + 0) /* GPIO_5_0 */ +#define EVK_USB_HUB_RESET (4*32 + 20) /* GPIO_5_20 */ +#define MX53_TVIN_PWR (4*32 + 23) /* GPIO_5_23 */ +#define MX53_CAN2_EN1 (4*32 + 24) /* GPIO_5_24 */ +#define MX53_TVIN_RESET (4*32 + 25) /* GPIO_5_25 */ + +#define EVK_OTG_VBUS (5*32 + 6) /* GPIO_6_6 */ + +#define EVK_FEC_PHY_RESET (6*32 + 6) /* GPIO_7_6 */ +#define EVK_USBH1_VBUS (6*32 + 8) /* GPIO_7_8 */ +#define MX53_PMIC_INT (6*32 + 11) /* GPIO_7_11 */ +#define MX53_CAN1_EN1 (6*32 + 12) /* GPIO_7_12 */ +#define MX53_CAN1_EN2 (6*32 + 13) /* GPIO_7_13 */ + +/*! + * @file mach-mx53/mx53_evk.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX53 + */ +extern int __init mx53_evk_init_mc13892(void); + +static struct pad_desc mx53common_pads[] = { + MX53_PAD_EIM_WAIT__GPIO_5_0, + + MX53_PAD_EIM_OE__DI1_PIN7, + MX53_PAD_EIM_RW__DI1_PIN8, + + MX53_PAD_EIM_A25__DI0_D1_CS, + + MX53_PAD_EIM_D16__CSPI1_SCLK, + MX53_PAD_EIM_D17__CSPI1_MISO, + MX53_PAD_EIM_D18__CSPI1_MOSI, + + MX53_PAD_EIM_D20__SER_DISP0_CS, + + MX53_PAD_EIM_D23__DI0_D0_CS, + + MX53_PAD_EIM_D24__GPIO_3_24, + MX53_PAD_EIM_D26__GPIO_3_26, + + MX53_PAD_EIM_D29__DISPB0_SER_RS, + + MX53_PAD_EIM_D30__DI0_PIN11, + MX53_PAD_EIM_D31__DI0_PIN12, + + MX53_PAD_ATA_DA_1__GPIO_7_7, + MX53_PAD_ATA_DATA4__GPIO_2_4, + MX53_PAD_ATA_DATA5__GPIO_2_5, + MX53_PAD_ATA_DATA6__GPIO_2_6, + + MX53_PAD_SD2_CLK__SD2_CLK, + MX53_PAD_SD2_CMD__SD2_CMD, + MX53_PAD_SD2_DATA0__SD2_DAT0, + MX53_PAD_SD2_DATA1__SD2_DAT1, + MX53_PAD_SD2_DATA2__SD2_DAT2, + MX53_PAD_SD2_DATA3__SD2_DAT3, + MX53_PAD_ATA_DATA12__SD2_DAT4, + MX53_PAD_ATA_DATA13__SD2_DAT5, + MX53_PAD_ATA_DATA14__SD2_DAT6, + MX53_PAD_ATA_DATA15__SD2_DAT7, + + MX53_PAD_CSI0_D10__UART1_TXD, + MX53_PAD_CSI0_D11__UART1_RXD, + + MX53_PAD_ATA_BUFFER_EN__UART2_RXD, + MX53_PAD_ATA_DMARQ__UART2_TXD, + MX53_PAD_ATA_DIOR__UART2_RTS, + MX53_PAD_ATA_INTRQ__UART2_CTS, + + MX53_PAD_ATA_CS_0__UART3_TXD, + MX53_PAD_ATA_CS_1__UART3_RXD, + + MX53_PAD_KEY_COL0__AUD5_TXC, + MX53_PAD_KEY_ROW0__AUD5_TXD, + MX53_PAD_KEY_COL1__AUD5_TXFS, + MX53_PAD_KEY_ROW1__AUD5_RXD, + + MX53_PAD_CSI0_D7__GPIO_5_25, + + MX53_PAD_GPIO_2__MLBDAT, + MX53_PAD_GPIO_3__MLBCLK, + + MX53_PAD_GPIO_6__MLBSIG, + + MX53_PAD_GPIO_4__GPIO_1_4, + MX53_PAD_GPIO_7__GPIO_1_7, + MX53_PAD_GPIO_8__GPIO_1_8, + + MX53_PAD_GPIO_10__GPIO_4_0, + + MX53_PAD_KEY_COL2__TXCAN1, + MX53_PAD_KEY_ROW2__RXCAN1, + + /* CAN1 -- EN */ + MX53_PAD_GPIO_18__GPIO_7_13, + /* CAN1 -- STBY */ + MX53_PAD_GPIO_17__GPIO_7_12, + /* CAN1 -- NERR */ + MX53_PAD_GPIO_5__GPIO_1_5, + + MX53_PAD_KEY_COL4__TXCAN2, + MX53_PAD_KEY_ROW4__RXCAN2, + + /* CAN2 -- EN */ + MX53_PAD_CSI0_D6__GPIO_5_24, + /* CAN2 -- STBY */ + MX53_PAD_GPIO_14__GPIO_4_4, + /* CAN2 -- NERR */ + MX53_PAD_CSI0_D4__GPIO_5_22, + + MX53_PAD_GPIO_11__GPIO_4_1, + MX53_PAD_GPIO_12__GPIO_4_2, + MX53_PAD_GPIO_13__GPIO_4_3, + MX53_PAD_GPIO_16__GPIO_7_11, + MX53_PAD_GPIO_19__GPIO_4_5, + + /* DI0 display clock */ + MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK, + + /* DI0 data enable */ + MX53_PAD_DI0_PIN15__DI0_PIN15, + /* DI0 HSYNC */ + MX53_PAD_DI0_PIN2__DI0_PIN2, + /* DI0 VSYNC */ + MX53_PAD_DI0_PIN3__DI0_PIN3, + + MX53_PAD_DISP0_DAT0__DISP0_DAT0, + MX53_PAD_DISP0_DAT1__DISP0_DAT1, + MX53_PAD_DISP0_DAT2__DISP0_DAT2, + MX53_PAD_DISP0_DAT3__DISP0_DAT3, + MX53_PAD_DISP0_DAT4__DISP0_DAT4, + MX53_PAD_DISP0_DAT5__DISP0_DAT5, + MX53_PAD_DISP0_DAT6__DISP0_DAT6, + MX53_PAD_DISP0_DAT7__DISP0_DAT7, + MX53_PAD_DISP0_DAT8__DISP0_DAT8, + MX53_PAD_DISP0_DAT9__DISP0_DAT9, + MX53_PAD_DISP0_DAT10__DISP0_DAT10, + MX53_PAD_DISP0_DAT11__DISP0_DAT11, + MX53_PAD_DISP0_DAT12__DISP0_DAT12, + MX53_PAD_DISP0_DAT13__DISP0_DAT13, + MX53_PAD_DISP0_DAT14__DISP0_DAT14, + MX53_PAD_DISP0_DAT15__DISP0_DAT15, + MX53_PAD_DISP0_DAT16__DISP0_DAT16, + MX53_PAD_DISP0_DAT17__DISP0_DAT17, + MX53_PAD_DISP0_DAT18__DISP0_DAT18, + MX53_PAD_DISP0_DAT19__DISP0_DAT19, + MX53_PAD_DISP0_DAT20__DISP0_DAT20, + MX53_PAD_DISP0_DAT21__DISP0_DAT21, + MX53_PAD_DISP0_DAT22__DISP0_DAT22, + MX53_PAD_DISP0_DAT23__DISP0_DAT23, + + MX53_PAD_LVDS0_TX3_P__LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LVDS0_TX0, + + MX53_PAD_LVDS1_TX3_P__LVDS1_TX3, + MX53_PAD_LVDS1_CLK_P__LVDS1_CLK, + MX53_PAD_LVDS1_TX2_P__LVDS1_TX2, + MX53_PAD_LVDS1_TX1_P__LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LVDS1_TX0, + + /* audio and CSI clock out */ + MX53_PAD_GPIO_0__SSI_EXT1_CLK, + + MX53_PAD_CSI0_D12__CSI0_D12, + MX53_PAD_CSI0_D13__CSI0_D13, + MX53_PAD_CSI0_D14__CSI0_D14, + MX53_PAD_CSI0_D15__CSI0_D15, + MX53_PAD_CSI0_D16__CSI0_D16, + MX53_PAD_CSI0_D17__CSI0_D17, + MX53_PAD_CSI0_D18__CSI0_D18, + MX53_PAD_CSI0_D19__CSI0_D19, + + MX53_PAD_CSI0_VSYNC__CSI0_VSYNC, + MX53_PAD_CSI0_MCLK__CSI0_HSYNC, + MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK, + /* Camera low power */ + MX53_PAD_CSI0_D5__GPIO_5_23, + + /* esdhc1 */ + MX53_PAD_SD1_CMD__SD1_CMD, + MX53_PAD_SD1_CLK__SD1_CLK, + MX53_PAD_SD1_DATA0__SD1_DATA0, + MX53_PAD_SD1_DATA1__SD1_DATA1, + MX53_PAD_SD1_DATA2__SD1_DATA2, + MX53_PAD_SD1_DATA3__SD1_DATA3, + + /* esdhc3 */ + MX53_PAD_ATA_DATA8__SD3_DAT0, + MX53_PAD_ATA_DATA9__SD3_DAT1, + MX53_PAD_ATA_DATA10__SD3_DAT2, + MX53_PAD_ATA_DATA11__SD3_DAT3, + MX53_PAD_ATA_DATA0__SD3_DAT4, + MX53_PAD_ATA_DATA1__SD3_DAT5, + MX53_PAD_ATA_DATA2__SD3_DAT6, + MX53_PAD_ATA_DATA3__SD3_DAT7, + MX53_PAD_ATA_RESET_B__SD3_CMD, + MX53_PAD_ATA_IORDY__SD3_CLK, + + /* FEC pins */ + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_REF_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_CRS_DV, + MX53_PAD_FEC_RXD1__FEC_RXD1, + MX53_PAD_FEC_RXD0__FEC_RXD0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TXD1, + MX53_PAD_FEC_TXD0__FEC_TXD0, + MX53_PAD_FEC_MDC__FEC_MDC, + + MX53_PAD_CSI0_D8__I2C1_SDA, + MX53_PAD_CSI0_D9__I2C1_SCL, + + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, +}; + +static struct pad_desc mx53evk_pads[] = { + /* USB OTG USB_OC */ + MX53_PAD_EIM_A24__GPIO_5_4, + + /* USB OTG USB_PWR */ + MX53_PAD_EIM_A23__GPIO_6_6, + + /* DISPB0_SER_CLK */ + MX53_PAD_EIM_D21__DISPB0_SER_CLK, + + /* DI0_PIN1 */ + MX53_PAD_EIM_D22__DISPB0_SER_DIN, + + /* DVI I2C ENABLE */ + MX53_PAD_EIM_D28__GPIO_3_28, + + /* DVI DET */ + MX53_PAD_EIM_D31__GPIO_3_31, + + /* SDHC1 SD_CD */ + MX53_PAD_EIM_DA13__GPIO_3_13, + + /* SDHC1 SD_WP */ + MX53_PAD_EIM_DA14__GPIO_3_14, + + /* SDHC3 SD_CD */ + MX53_PAD_EIM_DA11__GPIO_3_11, + + /* SDHC3 SD_WP */ + MX53_PAD_EIM_DA12__GPIO_3_12, + + /* PWM backlight */ + MX53_PAD_GPIO_1__PWMO, + + /* USB HOST USB_PWR */ + MX53_PAD_ATA_DA_2__GPIO_7_8, + + /* USB HOST USB_RST */ + MX53_PAD_CSI0_DATA_EN__GPIO_5_20, + + /* USB HOST CARD_ON */ + MX53_PAD_EIM_DA15__GPIO_3_15, + + /* USB HOST CARD_RST */ + MX53_PAD_ATA_DATA7__GPIO_2_7, + + /* USB HOST WAN_WAKE */ + MX53_PAD_EIM_D25__GPIO_3_25, + + /* FEC_RST */ + MX53_PAD_ATA_DA_0__GPIO_7_6, +}; + +static struct pad_desc mx53arm2_pads[] = { + /* USB OTG USB_OC */ + MX53_PAD_EIM_D21__GPIO_3_21, + + /* USB OTG USB_PWR */ + MX53_PAD_EIM_D22__GPIO_3_22, + + /* SDHC1 SD_CD */ + MX53_PAD_GPIO_1__GPIO_1_1, + + /* gpio backlight */ + MX53_PAD_DI0_PIN4__GPIO_4_20, +}; + +static struct pad_desc mx53_nand_pads[] = { + MX53_PAD_NANDF_CLE__NANDF_CLE, + MX53_PAD_NANDF_ALE__NANDF_ALE, + MX53_PAD_NANDF_WP_B__NANDF_WP_B, + MX53_PAD_NANDF_WE_B__NANDF_WE_B, + MX53_PAD_NANDF_RE_B__NANDF_RE_B, + MX53_PAD_NANDF_RB0__NANDF_RB0, + MX53_PAD_NANDF_CS0__NANDF_CS0, + MX53_PAD_NANDF_CS1__NANDF_CS1 , + MX53_PAD_NANDF_CS2__NANDF_CS2, + MX53_PAD_NANDF_CS3__NANDF_CS3 , + MX53_PAD_EIM_DA0__EIM_DA0, + MX53_PAD_EIM_DA1__EIM_DA1, + MX53_PAD_EIM_DA2__EIM_DA2, + MX53_PAD_EIM_DA3__EIM_DA3, + MX53_PAD_EIM_DA4__EIM_DA4, + MX53_PAD_EIM_DA5__EIM_DA5, + MX53_PAD_EIM_DA6__EIM_DA6, + MX53_PAD_EIM_DA7__EIM_DA7, +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 1600x1200 @ 60 Hz 162M pixel clk*/ + "UXGA", 60, 1600, 1200, 6172, + 304, 64, + 1, 46, + 192, 3, + FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, + /* 2 LVDS modes, had better remove from here */ + { + "1080P60", 60, 1920, 1080, 7692, + 100, 40, + 30, 3, + 10, 2, + 0, + FB_VMODE_NONINTERLACED, + 0,}, + { + "XGA", 60, 1024, 768, 15385, + 220, 40, + 21, 7, + 60, 10, + 0, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { + .pwm_id = 1, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 50000, +}; + +static void flexcan_xcvr_enable(int id, int en) +{ + static int pwdn; + if (id < 0 || id > 1) + return; + + if (en) { + if (!(pwdn++)) + gpio_set_value(MX53_12V_EN, 1); + + if (id == 0) { + gpio_set_value(MX53_CAN1_EN1, 1); + gpio_set_value(MX53_CAN1_EN2, 1); + } else { + gpio_set_value(MX53_CAN2_EN1, 1); + gpio_set_value(MX53_CAN2_EN2, 1); + } + + } else { + if (!(--pwdn)) + gpio_set_value(MX53_12V_EN, 0); + + if (id == 0) { + gpio_set_value(MX53_CAN1_EN1, 0); + gpio_set_value(MX53_CAN1_EN2, 0); + } else { + gpio_set_value(MX53_CAN2_EN1, 0); + gpio_set_value(MX53_CAN2_EN2, 0); + } + } +} + +static struct flexcan_platform_data flexcan0_data = { + .core_reg = NULL, + .io_reg = NULL, + .root_clk_id = "lp_apm", /*lp_apm is 24MHz */ + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 0, + .br_rjw = 2, + .br_presdiv = 3, + .br_propseg = 2, + .br_pseg1 = 3, + .br_pseg2 = 3, + .bcc = 1, + .srx_dis = 1, + .smp = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, +}; +static struct flexcan_platform_data flexcan1_data = { + .core_reg = NULL, + .io_reg = NULL, + .root_clk_id = "lp_apm", /*lp_apm is 24MHz */ + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 0, + .br_rjw = 2, + .br_presdiv = 3, + .br_propseg = 2, + .br_pseg1 = 3, + .br_pseg2 = 3, + .bcc = 1, + .srx_dis = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, +}; + + +extern void mx5_ipu_reset(void); +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 3, + .reset = mx5_ipu_reset, +}; + +extern void mx5_vpu_reset(void); +static struct mxc_vpu_platform_data mxc_vpu_data = { + .reset = mx5_vpu_reset, +}; + +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +/* workaround for ecspi chipselect pin may not keep correct level when idle */ +static void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + { + struct pad_desc eim_d19_gpio = MX53_PAD_EIM_D19__GPIO_3_19; + struct pad_desc cspi_ss0 = MX53_PAD_EIM_EB2__CSPI_SS0; + + /* de-select SS1 of instance: ecspi1. */ + mxc_iomux_v3_setup_pad(&eim_d19_gpio); + mxc_iomux_v3_setup_pad(&cspi_ss0); + } + break; + case 0x2: + { + struct pad_desc eim_eb2_gpio = MX53_PAD_EIM_EB2__GPIO_2_30; + struct pad_desc cspi_ss1 = MX53_PAD_EIM_D19__CSPI_SS1; + + /* de-select SS0 of instance: ecspi1. */ + mxc_iomux_v3_setup_pad(&eim_eb2_gpio); + mxc_iomux_v3_setup_pad(&cspi_ss1); + } + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + break; + case 0x2: + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = mx53_evk_gpio_spi_chipselect_active, + .chipselect_inactive = mx53_evk_gpio_spi_chipselect_inactive, +}; + +static struct imxi2c_platform_data mxci2c_data = { + .bitrate = 100000, +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "SW1", + .lp_reg_id = "SW2", +}; + +static struct tve_platform_data tve_data = { + .dac_reg = "VVIDEO", +}; + +static struct ldb_platform_data ldb_data = { + .lvds_bg_reg = "VAUDIO", + .ext_ref = 1, +}; + +static void mxc_iim_enable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg |= 0x10; + writel(reg, ccm_base + 0x64); +} + +static void mxc_iim_disable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg &= ~0x10; + writel(reg, ccm_base + 0x64); +} + +static struct mxc_iim_data iim_data = { + .bank_start = MXC_IIM_MX53_BANK_START_ADDR, + .bank_end = MXC_IIM_MX53_BANK_END_ADDR, + .enable_fuse = mxc_iim_enable_fuse, + .disable_fuse = mxc_iim_disable_fuse, +}; + +static struct pad_desc mx53esai_pads[] = { + MX53_PAD_FEC_MDIO__ESAI_SCKR, + MX53_PAD_FEC_REF_CLK__ESAI_FSR, + MX53_PAD_FEC_RX_ER__ESAI_HCKR, + MX53_PAD_FEC_CRS_DV__ESAI_SCKT, + MX53_PAD_FEC_RXD1__ESAI_FST, + MX53_PAD_FEC_RXD0__ESAI_HCKT, + MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2, + MX53_PAD_FEC_TXD1__ESAI_TX2_RX3, + MX53_PAD_FEC_TXD0__ESAI_TX4_RX1, + MX53_PAD_FEC_MDC__ESAI_TX5_RX0, + MX53_PAD_NANDF_CS2__ESAI_TX0, + MX53_PAD_NANDF_CS3__ESAI_TX1, +}; + +void gpio_activate_esai_ports(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53esai_pads, + ARRAY_SIZE(mx53esai_pads)); +} + +static struct mxc_esai_platform_data esai_data = { + .activate_esai_ports = gpio_activate_esai_ports, +}; + +void gpio_cs42888_pdwn(int pdwn) +{ + if (pdwn) + gpio_set_value(MX53_ESAI_RESET, 0); + else + gpio_set_value(MX53_ESAI_RESET, 1); +} + +static void gpio_usbotg_vbus_active(void) +{ + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + /* Enable OTG VBus with GPIO low */ + gpio_set_value(ARM2_OTG_VBUS, 0); + } else if (board_is_mx53_evk_a()) { + /* MX53 EVK board ver A*/ + /* Enable OTG VBus with GPIO low */ + gpio_set_value(EVK_OTG_VBUS, 0); + } else if (board_is_mx53_evk_b()) { + /* MX53 EVK board ver B*/ + /* Enable OTG VBus with GPIO high */ + gpio_set_value(EVK_OTG_VBUS, 1); + } +} + +static void gpio_usbotg_vbus_inactive(void) +{ + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + /* Disable OTG VBus with GPIO high */ + gpio_set_value(ARM2_OTG_VBUS, 1); + } else if (board_is_mx53_evk_a()) { + /* MX53 EVK board ver A*/ + /* Disable OTG VBus with GPIO high */ + gpio_set_value(EVK_OTG_VBUS, 1); + } else if (board_is_mx53_evk_b()) { + /* MX53 EVK board ver B*/ + /* Disable OTG VBus with GPIO low */ + gpio_set_value(EVK_OTG_VBUS, 0); + } +} + +static void mx53_gpio_usbotg_driver_vbus(bool on) +{ + if (on) + gpio_usbotg_vbus_active(); + else + gpio_usbotg_vbus_inactive(); +} + +static void mx53_gpio_host1_driver_vbus(bool on) +{ + if (on) + gpio_set_value(EVK_USBH1_VBUS, 1); + else + gpio_set_value(EVK_USBH1_VBUS, 0); +} + +static void adv7180_pwdn(int pwdn) +{ + gpio_request(MX53_TVIN_PWR, "tvin-pwr"); + if (pwdn) + gpio_set_value(MX53_TVIN_PWR, 0); + else + gpio_set_value(MX53_TVIN_PWR, 1); + gpio_free(MX53_TVIN_PWR); +} + +static struct mxc_tvin_platform_data adv7180_data = { + .dvddio_reg = NULL, + .dvdd_reg = NULL, + .avdd_reg = NULL, + .pvdd_reg = NULL, + .pwdn = adv7180_pwdn, + .reset = NULL, +}; + +static struct resource mxcfb_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "800x480M@55", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, + { + .interface_pix_fmt = IPU_PIX_FMT_GBR24, + .mode_str = "1024x768M-16@60", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +extern int primary_di; +static int __init mxc_init_fb(void) +{ + if (!machine_is_mx53_evk()) + return 0; + + if (primary_di) { + printk(KERN_INFO "DI1 is primary\n"); + /* DI1 -> DP-BG channel: */ + mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[1].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + + /* DI0 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + } else { + printk(KERN_INFO "DI0 is primary\n"); + + /* DI0 -> DP-BG channel: */ + mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[0].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + + /* DI1 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + } + + /* + * DI0/1 DP-FG channel: + */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +device_initcall(mxc_init_fb); + +static void camera_pwdn(int pwdn) +{ + gpio_request(MX53_TVIN_PWR, "tvin-pwr"); + gpio_set_value(MX53_TVIN_PWR, pwdn); + gpio_free(MX53_TVIN_PWR); +} + +static struct mxc_camera_platform_data camera_data = { + .analog_regulator = "VSD", + .gpo_regulator = "VVIDEO", + .mclk = 24000000, + .csi = 0, + .pwdn = camera_pwdn, +}; + +static struct mxc_audio_codec_platform_data cs42888_data = { + .analog_regulator = "VSD", + .pwdn = gpio_cs42888_pdwn, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + .type = "ov3640", + .addr = 0x3C, + .platform_data = (void *)&camera_data, + }, + { + .type = "adv7180", + .addr = 0x21, + .platform_data = (void *)&adv7180_data, + }, + { + .type = "cs42888", + .addr = 0x48, + .platform_data = &cs42888_data, + }, +}; + +static void sii902x_hdmi_reset(void) +{ + gpio_set_value(MX53_DVI_RESET, 0); + msleep(10); + gpio_set_value(MX53_DVI_RESET, 1); + msleep(10); +} + +static struct mxc_lcd_platform_data sii902x_hdmi_data = { + .reset = sii902x_hdmi_reset, +}; + +/* TO DO add platform data */ +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "tsc2007", + .addr = 0x48, + .irq = IOMUX_TO_IRQ_V3(EVK_TS_INT), + }, + { + .type = "backlight-i2c", + .addr = 0x2c, + }, + { + .type = "vga-ddc", + .addr = 0x1f, + }, + { + .type = "eeprom", + .addr = 0x50, + }, + { + .type = "sii902x", + .addr = 0x39, + .irq = IOMUX_TO_IRQ_V3(MX53_DVI_DETECT), + .platform_data = &sii902x_hdmi_data, + }, +}; + +static struct mtd_partition mxc_dataflash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x000100000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, +}; + +static struct flash_platform_data mxc_spi_flash_data[] = { + { + .name = "mxc_dataflash", + .parts = mxc_dataflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), + .type = "at45db321d",} +}; + + +static struct spi_board_info mxc_dataflash_device[] __initdata = { + { + .modalias = "mxc_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[0],}, +}; + +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (!board_is_mx53_arm2()) { + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(EVK_SD1_WP); + else + rc = gpio_get_value(EVK_SD3_WP); + } + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret; + if (board_is_mx53_arm2()) { + if (to_platform_device(dev)->id == 0) + ret = gpio_get_value(ARM2_SD1_CD); + else + ret = 1; + } else { + if (to_platform_device(dev)->id == 0) { + ret = gpio_get_value(EVK_SD1_CD); + } else{ /* config the det pin for SDHC3 */ + ret = gpio_get_value(EVK_SD3_CD); + } + } + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static int mxc_sgtl5000_amp_enable(int enable) +{ +/* TO DO */ +return 0; +} + +static int headphone_det_status(void) +{ + return (gpio_get_value(MX53_HP_DETECT) == 0); +} + +static int mxc_sgtl5000_init(void); + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 5, + .hp_irq = IOMUX_TO_IRQ(MX53_HP_DETECT), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .init = mxc_sgtl5000_init, +}; + +static int mxc_sgtl5000_init(void) +{ + struct clk *ssi_ext1; + int rate; + + if (board_is_mx53_arm2()) { + sgtl5000_data.sysclk = 12000000; + } else { + ssi_ext1 = clk_get(NULL, "ssi_ext1_clk"); + if (IS_ERR(ssi_ext1)) + return -1; + + rate = clk_round_rate(ssi_ext1, 24000000); + if (rate < 8000000 || rate > 27000000) { + printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n", + rate); + clk_put(ssi_ext1); + return -1; + } + + clk_set_rate(ssi_ext1, rate); + clk_enable(ssi_ext1); + sgtl5000_data.sysclk = rate; + } + + return 0; +} + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static struct mxc_mlb_platform_data mlb_data = { + .reg_nvcc = "VCAM", + .mlb_clk = "mlb_clk", +}; + +static void mxc_register_powerkey(pwrkey_callback pk_cb) +{ + pmic_event_callback_t power_key_event; + + power_key_event.param = (void *)1; + power_key_event.func = (void *)pk_cb; + pmic_event_subscribe(EVENT_PWRONI, power_key_event); +} + +static int mxc_pwrkey_getstatus(int id) +{ + int sense; + + pmic_read_reg(REG_INT_SENSE1, &sense, 0xffffffff); + if (sense & (1 << 3)) + return 0; + + return 1; +} + +static struct power_key_platform_data pwrkey_data = { + .key_value = KEY_F4, + .register_pwrkey = mxc_register_powerkey, + .get_key_status = mxc_pwrkey_getstatus, +}; + +/* NAND Flash Partitions */ +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition nand_flash_partitions[] = { +/* MX53 ROM require the boot FCB/DBBT support which need + * more space to store such info on NAND boot partition. + * 16M should cover all kind of NAND boot support on MX53. + */ + { + .name = "bootloader", + .offset = 0, + .size = 16 * 1024 * 1024}, + { + .name = "nand.kernel", + .offset = MTDPART_OFS_APPEND, + .size = 5 * 1024 * 1024}, + { + .name = "nand.rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs1", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; +#endif + +static int nand_init(void) +{ + u32 i, reg; + void __iomem *base; + + #define M4IF_GENP_WEIM_MM_MASK 0x00000001 + #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 + + base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); + reg = __raw_readl(base + 0xc); + reg &= ~M4IF_GENP_WEIM_MM_MASK; + __raw_writel(reg, base + 0xc); + + iounmap(base); + + base = ioremap(MX53_BASE_ADDR(WEIM_BASE_ADDR), SZ_4K); + for (i = 0x4; i < 0x94; i += 0x18) { + reg = __raw_readl((u32)base + i); + reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; + __raw_writel(reg, (u32)base + i); + } + + iounmap(base); + + return 0; +} + +static struct flash_platform_data mxc_nand_data = { +#ifdef CONFIG_MTD_PARTITIONS + .parts = nand_flash_partitions, + .nr_parts = ARRAY_SIZE(nand_flash_partitions), +#endif + .width = 1, + .init = nand_init, +}; + +static struct mxc_asrc_platform_data mxc_asrc_data = { + .channel_bits = 4, + .clk_map_ver = 2, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 0, + .spdif_clk_44100 = 0, /* Souce from CKIH1 for 44.1K */ + .spdif_clk_48000 = 7, /* Source from CKIH2 for 48k and 32k */ + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static struct mxc_audio_platform_data mxc_surround_audio_data = { + .ext_ram = 1, + .sysclk = 22579200, +}; + + +static struct platform_device mxc_alsa_surround_device = { + .name = "imx-3stack-cs42888", +}; + +static int __initdata mxc_apc_on = { 0 }; /* OFF: 0 (default), ON: 1 */ +static int __init apc_setup(char *__unused) +{ + mxc_apc_on = 1; + printk(KERN_INFO "Automotive Port Card is Plugged on\n"); + return 1; +} +__setup("apc", apc_setup); + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx53(); +} +__setup("w1", w1_setup); + + +static int __initdata enable_spdif = { 0 }; +static int __init spdif_setup(char *__unused) +{ + enable_spdif = 1; + return 1; +} +__setup("spdif", spdif_setup); + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + struct tag *t; + struct tag *mem_tag = 0; + int total_mem = SZ_1G; + int left_mem = 0; + int gpu_mem = SZ_128M; + int fb_mem = SZ_32M; + char *str; + + mxc_set_cpu_type(MXC_CPU_MX53); + + for_each_tag(mem_tag, tags) { + if (mem_tag->hdr.tag == ATAG_MEM) { + total_mem = mem_tag->u.mem.size; + left_mem = total_mem - gpu_mem - fb_mem; + break; + } + } + + for_each_tag(t, tags) { + if (t->hdr.tag == ATAG_CMDLINE) { + str = t->u.cmdline.cmdline; + str = strstr(str, "mem="); + if (str != NULL) { + str += 4; + left_mem = memparse(str, &str); + if (left_mem == 0 || left_mem > total_mem) + left_mem = total_mem - gpu_mem - fb_mem; + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_memory="); + if (str != NULL) { + str += 11; + gpu_mem = memparse(str, &str); + } + + break; + } + } + + if (mem_tag) { + fb_mem = total_mem - left_mem - gpu_mem; + if (fb_mem < 0) { + gpu_mem = total_mem - left_mem; + fb_mem = 0; + } + mem_tag->u.mem.size = left_mem; + + /*reserve memory for gpu*/ + gpu_device.resource[5].start = + mem_tag->u.mem.start + left_mem; + gpu_device.resource[5].end = + gpu_device.resource[5].start + gpu_mem - 1; +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) + if (fb_mem) { + mxcfb_resources[0].start = + gpu_device.resource[5].end + 1; + mxcfb_resources[0].end = + mxcfb_resources[0].start + fb_mem - 1; + } else { + mxcfb_resources[0].start = 0; + mxcfb_resources[0].end = 0; + } +#endif + } +} + +static void __init mx53_evk_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53common_pads, + ARRAY_SIZE(mx53common_pads)); + + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + pr_info("MX53 ARM2 board \n"); + mxc_iomux_v3_setup_multiple_pads(mx53arm2_pads, + ARRAY_SIZE(mx53arm2_pads)); + + /* Config GPIO for OTG VBus */ + gpio_request(ARM2_OTG_VBUS, "otg-vbus"); + gpio_direction_output(ARM2_OTG_VBUS, 1); + + gpio_request(ARM2_SD1_CD, "sdhc1-cd"); + gpio_direction_input(ARM2_SD1_CD); /* SD1 CD */ + + gpio_request(ARM2_LCD_CONTRAST, "lcd-contrast"); + gpio_direction_output(ARM2_LCD_CONTRAST, 1); + } else { + /* MX53 EVK board */ + pr_info("MX53 EVK board \n"); + mxc_iomux_v3_setup_multiple_pads(mx53evk_pads, + ARRAY_SIZE(mx53evk_pads)); + + /* Host1 Vbus with GPIO high */ + gpio_request(EVK_USBH1_VBUS, "usbh1-vbus"); + gpio_direction_output(EVK_USBH1_VBUS, 1); + /* shutdown the Host1 Vbus when system bring up, + * Vbus will be opened in Host1 driver's probe function */ + gpio_set_value(EVK_USBH1_VBUS, 0); + + /* USB HUB RESET - De-assert USB HUB RESET_N */ + gpio_request(EVK_USB_HUB_RESET, "usb-hub-reset"); + gpio_direction_output(EVK_USB_HUB_RESET, 0); + msleep(1); + gpio_set_value(EVK_USB_HUB_RESET, 1); + + /* Config GPIO for OTG VBus */ + gpio_request(EVK_OTG_VBUS, "otg-vbus"); + gpio_direction_output(EVK_OTG_VBUS, 0); + if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/ + gpio_set_value(EVK_OTG_VBUS, 1); + else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/ + gpio_set_value(EVK_OTG_VBUS, 0); + + gpio_request(EVK_SD1_CD, "sdhc1-cd"); + gpio_direction_input(EVK_SD1_CD); /* SD1 CD */ + gpio_request(EVK_SD1_WP, "sdhc1-wp"); + gpio_direction_input(EVK_SD1_WP); /* SD1 WP */ + + /* SD3 CD */ + gpio_request(EVK_SD3_CD, "sdhc3-cd"); + gpio_direction_input(EVK_SD3_CD); + + /* SD3 WP */ + gpio_request(EVK_SD3_WP, "sdhc3-wp"); + gpio_direction_input(EVK_SD3_WP); + + /* reset FEC PHY */ + gpio_request(EVK_FEC_PHY_RESET, "fec-phy-reset"); + gpio_direction_output(EVK_FEC_PHY_RESET, 0); + msleep(1); + gpio_set_value(EVK_FEC_PHY_RESET, 1); + + gpio_request(MX53_ESAI_RESET, "fesai-reset"); + gpio_direction_output(MX53_ESAI_RESET, 0); + } + + /* DVI Detect */ + gpio_request(MX53_DVI_DETECT, "dvi-detect"); + gpio_direction_input(MX53_DVI_DETECT); + /* DVI Reset - Assert for i2c disabled mode */ + gpio_request(MX53_DVI_RESET, "dvi-reset"); + gpio_direction_output(MX53_DVI_RESET, 0); + + /* DVI Power-down */ + gpio_request(MX53_DVI_PD, "dvi-pd"); + gpio_direction_output(MX53_DVI_PD, 1); + + /* DVI I2C enable */ + gpio_request(MX53_DVI_I2C, "dvi-i2c"); + gpio_direction_output(MX53_DVI_I2C, 0); + + mxc_iomux_v3_setup_multiple_pads(mx53_nand_pads, + ARRAY_SIZE(mx53_nand_pads)); + + gpio_request(MX53_PMIC_INT, "pmic-int"); + gpio_direction_input(MX53_PMIC_INT); /*PMIC_INT*/ + + /* headphone_det_b */ + gpio_request(MX53_HP_DETECT, "hp-detect"); + gpio_direction_input(MX53_HP_DETECT); + + /* power key */ + + /* LCD related gpio */ + + /* Camera reset */ + gpio_request(MX53_CAM_RESET, "cam-reset"); + gpio_direction_output(MX53_CAM_RESET, 1); + + /* TVIN reset */ + gpio_request(MX53_TVIN_RESET, "tvin-reset"); + gpio_direction_output(MX53_TVIN_RESET, 0); + msleep(5); + gpio_set_value(MX53_TVIN_RESET, 1); + + /* TVin power down */ + gpio_request(MX53_TVIN_PWR, "tvin-pwr"); + gpio_direction_output(MX53_TVIN_PWR, 0); + + /* CAN1 enable GPIO*/ + gpio_request(MX53_CAN1_EN1, "can1-en1"); + gpio_direction_output(MX53_CAN1_EN1, 0); + + gpio_request(MX53_CAN1_EN2, "can1-en2"); + gpio_direction_output(MX53_CAN1_EN2, 0); + + /* CAN2 enable GPIO*/ + gpio_request(MX53_CAN2_EN1, "can2-en1"); + gpio_direction_output(MX53_CAN2_EN1, 0); + + gpio_request(MX53_CAN2_EN2, "can2-en2"); + gpio_direction_output(MX53_CAN2_EN2, 0); + + if (enable_spdif) { + struct pad_desc spdif_pin = MX53_PAD_GPIO_19__SPDIF_TX1; + mxc_iomux_v3_setup_pad(&spdif_pin); + } else { + /* GPIO for 12V */ + gpio_request(MX53_12V_EN, "12v-en"); + gpio_direction_output(MX53_12V_EN, 0); + } +} + +extern void mx53_gpio_usbotg_driver_vbus(bool on); +extern void mx53_gpio_host1_driver_vbus(bool on); +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "ssi_ext1_clk"); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); + + /* SD card detect irqs */ + if (board_is_mx53_arm2()) { + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(ARM2_SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(ARM2_SD1_CD); + mmc3_data.card_inserted_state = 1; + mmc3_data.status = NULL; + mmc3_data.wp_status = NULL; + mmc1_data.wp_status = NULL; + } else { + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD3_CD); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD3_CD); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD1_CD); + } + + mxc_cpu_common_init(); + mx53_evk_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_devices[2], &mxci2c_data); + + mxc_register_device(&mxc_rtc_device, NULL); + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); + mxc_register_device(&mxc_ldb_device, &ldb_data); + mxc_register_device(&mxc_tve_device, &tve_data); + mxc_register_device(&mxcvpu_device, &mxc_vpu_data); + mxc_register_device(&gpu_device, &z160_revision); + mxc_register_device(&mxcscc_device, NULL); + /* + mxc_register_device(&mx53_lpmode_device, NULL); + mxc_register_device(&sdram_autogating_device, NULL); + */ + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&busfreq_device, &bus_freq_data); + + /* + mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); + */ + + mxc_register_device(&mxc_iim_device, &iim_data); + if (!board_is_mx53_arm2()) { + mxc_register_device(&mxc_pwm2_device, NULL); + mxc_register_device(&mxc_pwm1_backlight_device, + &mxc_pwm_backlight_data); + } + mxc_register_device(&mxc_flexcan0_device, &flexcan0_data); + mxc_register_device(&mxc_flexcan1_device, &flexcan1_data); + +/* mxc_register_device(&mxc_keypad_device, &keypad_plat_data); */ + + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&ahci_fsl_device, &sata_data); + + /* ASRC is only available for MX53 TO2.0 */ + if (cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) { + mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + clk_put(mxc_asrc_data.asrc_core_clk); + mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); + clk_put(mxc_asrc_data.asrc_audio_clk); + mxc_register_device(&mxc_asrc_device, &mxc_asrc_data); + } + + mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); + if (!mxc_apc_on) { + mxc_register_device(&mxc_fec_device, &fec_data); + mxc_register_device(&mxc_ptp_device, NULL); + } + spi_register_board_info(mxc_dataflash_device, + ARRAY_SIZE(mxc_dataflash_device)); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + + mx53_evk_init_mc13892(); +/* + pm_power_off = mxc_power_off; + */ + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mxc_register_device(&mxc_mlb_device, &mlb_data); + mxc_register_device(&mxc_powerkey_device, &pwrkey_data); + mx5_set_otghost_vbus_func(mx53_gpio_usbotg_driver_vbus); + mx5_usb_dr_init(); + mx5_set_host1_vbus_func(mx53_gpio_host1_driver_vbus); + mx5_usbh1_init(); + mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data); + if (mxc_apc_on) { + mxc_register_device(&mxc_esai_device, &esai_data); + mxc_register_device(&mxc_alsa_surround_device, + &mxc_surround_audio_data); + } + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); +} + +static void __init mx53_evk_timer_init(void) +{ + struct clk *uart_clk; + + mx53_clocks_init(32768, 24000000, 22579200, 24576000); + + uart_clk = clk_get_sys("mxcintuart.0", NULL); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx53_evk_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX53_EVK data structure. + */ +MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c new file mode 100644 index 000000000000..3ed2e14e49ba --- /dev/null +++ b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c @@ -0,0 +1,351 @@ +/* + * mx53-evk-pmic-mc13892.c -- i.MX53 3STACK Driver for Atlas MC13892 PMIC + */ + /* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +#define STANDBYSECINV_LSH 11 +#define STANDBYSECINV_WID 1 + +/* Coin cell charger enable */ +#define COINCHEN_LSH 23 +#define COINCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + } +}; + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value; + int register_mask; + + pr_info("Initializing regulators for MX53 EVK \n"); + + /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + /* Set the STANDBYSECINV bit, so that STANDBY pin is + * interpreted as active low. + */ + value = BITFVAL(STANDBYSECINV, 1); + register_mask = BITFMASK(STANDBYSECINV); + pmic_write_reg(REG_POWER_CTL2, value, register_mask); + + /* Disable coin cell charger since the cell is not rechargeable */ + value = BITFVAL(COINCHEN, 0) | BITFVAL(VCOIN, VCOIN_3_0V); + register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct i2c_board_info __initdata mc13892_i2c_device = { + I2C_BOARD_INFO("mc13892", 0x08), + .irq = IOMUX_TO_IRQ_V3(203), + .platform_data = &mc13892_plat, +}; + +int __init mx53_evk_init_mc13892(void) +{ + return i2c_register_board_info(1, &mc13892_i2c_device, 1); +} diff --git a/arch/arm/mach-mx5/mx53_loco.c b/arch/arm/mach-mx5/mx53_loco.c new file mode 100644 index 000000000000..7074dcdf55de --- /dev/null +++ b/arch/arm/mach-mx5/mx53_loco.c @@ -0,0 +1,839 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" +#include "devices.h" +#include "usb.h" + +/*! + * @file mach-mx5/mx53_loco.c + * + * @brief This file contains MX53 loco board specific initialization routines. + * + * @ingroup MSL_MX53 + */ + +/* MX53 LOCO GPIO PIN configurations */ +#define NVDD_FAULT (0*32 + 5) /* GPIO1_5 */ + +#define FEC_INT (1*32 + 4) /* GPIO_2_4 */ +#define HEADPHONE_DEC_B (1*32 + 5) /* GPIO_2_5 */ +#define MIC_DEC_B (1*32 + 6) /* GPIO_2_6 */ +#define USER_UI1 (1*32 + 14) /* GPIO_2_14 */ +#define USER_UI2 (1*32 + 15) /* GPIO_2_15 */ +#define MX53_nONKEY (0*32 + 8) /* GPIO_1_8 */ + +#define SD3_CD (2*32 + 11) /* GPIO_3_11 */ +#define SD3_WP (2*32 + 12) /* GPIO_3_12 */ +#define DISP0_POWER_EN (2*32 + 24) /* GPIO_3_24 */ +#define DISP0_DET_INT (2*32 + 31) /* GPIO_3_31 */ + +#define DISP0_RESET (4*32 + 0) /* GPIO_5_0 */ + +#define CSI0_RTSB (5*32 + 9) /* GPIO_6_9 */ +#define CSI0_PWDN (5*32 + 10) /* GPIO_6_10 */ +#define ACCL_EN (5*32 + 14) /* GPIO_6_14 */ +#define ACCL_INT1_IN (5*32 + 15) /* GPIO_6_15 */ +#define ACCL_INT2_IN (5*32 + 16) /* GPIO_6_16 */ + +#define LCD_BLT_EN (6*32 + 2) /* GPIO_7_2 */ +#define FEC_RST (6*32 + 6) /* GPIO_7_6 */ +#define USER_LED_EN (6*32 + 7) /* GPIO_7_7 */ +#define USB_PWREN (6*32 + 8) /* GPIO_7_8 */ +#define NIRQ (6*32 + 11) /* GPIO7_11 */ + +extern int __init mx53_loco_init_da9052(void); + +static struct pad_desc mx53_loco_pads[] = { + /* FEC */ + MX53_PAD_FEC_MDC__FEC_MDC, + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_REF_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_CRS_DV, + MX53_PAD_FEC_RXD1__FEC_RXD1, + MX53_PAD_FEC_RXD0__FEC_RXD0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TXD1, + MX53_PAD_FEC_TXD0__FEC_TXD0, + /* FEC_nRST */ + MX53_PAD_ATA_DA_0__GPIO_7_6, + /* FEC_nINT */ + MX53_PAD_ATA_DATA4__GPIO_2_4, + /* AUDMUX5 */ + MX53_PAD_KEY_COL0__AUD5_TXC, + MX53_PAD_KEY_ROW0__AUD5_TXD, + MX53_PAD_KEY_COL1__AUD5_TXFS, + MX53_PAD_KEY_ROW1__AUD5_RXD, + /* I2C2 */ + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, + /* SD1 */ + MX53_PAD_SD1_CMD__SD1_CMD, + MX53_PAD_SD1_CLK__SD1_CLK, + MX53_PAD_SD1_DATA0__SD1_DATA0, + MX53_PAD_SD1_DATA1__SD1_DATA1, + MX53_PAD_SD1_DATA2__SD1_DATA2, + MX53_PAD_SD1_DATA3__SD1_DATA3, + /* SD3 */ + MX53_PAD_ATA_DATA8__SD3_DAT0, + MX53_PAD_ATA_DATA9__SD3_DAT1, + MX53_PAD_ATA_DATA10__SD3_DAT2, + MX53_PAD_ATA_DATA11__SD3_DAT3, + MX53_PAD_ATA_DATA0__SD3_DAT4, + MX53_PAD_ATA_DATA1__SD3_DAT5, + MX53_PAD_ATA_DATA2__SD3_DAT6, + MX53_PAD_ATA_DATA3__SD3_DAT7, + MX53_PAD_ATA_IORDY__SD3_CLK, + MX53_PAD_ATA_RESET_B__SD3_CMD, + /* SD3_CD */ + MX53_PAD_EIM_DA11__GPIO_3_11, + /* SD3_WP */ + MX53_PAD_EIM_DA12__GPIO_3_12, + /* VGA */ + MX53_PAD_EIM_OE__DI1_PIN7, + MX53_PAD_EIM_RW__DI1_PIN8, + /* DISPLB */ + MX53_PAD_EIM_D20__SER_DISP0_CS, + MX53_PAD_EIM_D21__DISPB0_SER_CLK, + MX53_PAD_EIM_D22__DISPB0_SER_DIN, + MX53_PAD_EIM_D23__DI0_D0_CS, + /* DISP0_POWER_EN */ + MX53_PAD_EIM_D24__GPIO_3_24, + /* DISP0 DET INT */ + MX53_PAD_EIM_D31__GPIO_3_31, + + /* LVDS */ + MX53_PAD_LVDS0_TX3_P__LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LVDS0_TX0, + MX53_PAD_LVDS1_TX3_P__LVDS1_TX3, + MX53_PAD_LVDS1_TX2_P__LVDS1_TX2, + MX53_PAD_LVDS1_CLK_P__LVDS1_CLK, + MX53_PAD_LVDS1_TX1_P__LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LVDS1_TX0, + /* I2C1 */ + MX53_PAD_CSI0_D8__I2C1_SDA, + MX53_PAD_CSI0_D9__I2C1_SCL, + /* UART1 */ + MX53_PAD_CSI0_D10__UART1_TXD, + MX53_PAD_CSI0_D11__UART1_RXD, + /* CSI0 */ + MX53_PAD_CSI0_D12__CSI0_D12, + MX53_PAD_CSI0_D13__CSI0_D13, + MX53_PAD_CSI0_D14__CSI0_D14, + MX53_PAD_CSI0_D15__CSI0_D15, + MX53_PAD_CSI0_D16__CSI0_D16, + MX53_PAD_CSI0_D17__CSI0_D17, + MX53_PAD_CSI0_D18__CSI0_D18, + MX53_PAD_CSI0_D19__CSI0_D19, + MX53_PAD_CSI0_VSYNC__CSI0_VSYNC, + MX53_PAD_CSI0_MCLK__CSI0_HSYNC, + MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK, + /* DISPLAY */ + MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK, + MX53_PAD_DI0_PIN15__DI0_PIN15, + MX53_PAD_DI0_PIN2__DI0_PIN2, + MX53_PAD_DI0_PIN3__DI0_PIN3, + MX53_PAD_DISP0_DAT0__DISP0_DAT0, + MX53_PAD_DISP0_DAT1__DISP0_DAT1, + MX53_PAD_DISP0_DAT2__DISP0_DAT2, + MX53_PAD_DISP0_DAT3__DISP0_DAT3, + MX53_PAD_DISP0_DAT4__DISP0_DAT4, + MX53_PAD_DISP0_DAT5__DISP0_DAT5, + MX53_PAD_DISP0_DAT6__DISP0_DAT6, + MX53_PAD_DISP0_DAT7__DISP0_DAT7, + MX53_PAD_DISP0_DAT8__DISP0_DAT8, + MX53_PAD_DISP0_DAT9__DISP0_DAT9, + MX53_PAD_DISP0_DAT10__DISP0_DAT10, + MX53_PAD_DISP0_DAT11__DISP0_DAT11, + MX53_PAD_DISP0_DAT12__DISP0_DAT12, + MX53_PAD_DISP0_DAT13__DISP0_DAT13, + MX53_PAD_DISP0_DAT14__DISP0_DAT14, + MX53_PAD_DISP0_DAT15__DISP0_DAT15, + MX53_PAD_DISP0_DAT16__DISP0_DAT16, + MX53_PAD_DISP0_DAT17__DISP0_DAT17, + MX53_PAD_DISP0_DAT18__DISP0_DAT18, + MX53_PAD_DISP0_DAT19__DISP0_DAT19, + MX53_PAD_DISP0_DAT20__DISP0_DAT20, + MX53_PAD_DISP0_DAT21__DISP0_DAT21, + MX53_PAD_DISP0_DAT22__DISP0_DAT22, + MX53_PAD_DISP0_DAT23__DISP0_DAT23, + /* Audio CLK*/ + MX53_PAD_GPIO_0__SSI_EXT1_CLK, + /* PWM */ + MX53_PAD_GPIO_1__PWMO, + /* SPDIF */ + MX53_PAD_GPIO_7__PLOCK, + MX53_PAD_GPIO_17__SPDIF_OUT1, + /* GPIO */ + MX53_PAD_ATA_DA_1__GPIO_7_7, + MX53_PAD_ATA_DA_2__GPIO_7_8, + MX53_PAD_ATA_DATA5__GPIO_2_5, + MX53_PAD_ATA_DATA6__GPIO_2_6, + MX53_PAD_ATA_DATA14__GPIO_2_14, + MX53_PAD_ATA_DATA15__GPIO_2_15, + MX53_PAD_ATA_INTRQ__GPIO_7_2, + MX53_PAD_EIM_WAIT__GPIO_5_0, + MX53_PAD_NANDF_WP_B__GPIO_6_9, + MX53_PAD_NANDF_RB0__GPIO_6_10, + MX53_PAD_NANDF_CS1__GPIO_6_14, + MX53_PAD_NANDF_CS2__GPIO_6_15, + MX53_PAD_NANDF_CS3__GPIO_6_16, + MX53_PAD_GPIO_5__GPIO_1_5, + MX53_PAD_GPIO_16__GPIO_7_11, + MX53_PAD_GPIO_8__GPIO_1_8, +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 800x480 @ 60 Hz , pixel clk @ 32MHz */ + "SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 1600x1200 @ 60 Hz 162M pixel clk*/ + "UXGA", 60, 1600, 1200, 6172, + 304, 64, + 1, 46, + 192, 3, + FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, + /* 2 LVDS modes, had better remove from here */ + { + "1080P60", 60, 1920, 1080, 7692, + 100, 40, + 30, 3, + 10, 2, + 0, + FB_VMODE_NONINTERLACED, + 0,}, + { + "XGA", 60, 1024, 768, 15385, + 220, 40, + 21, 7, + 60, 10, + 0, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { + .pwm_id = 1, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 50000, +}; + +extern void mx5_ipu_reset(void); +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 3, + .reset = mx5_ipu_reset, +}; + +extern void mx5_vpu_reset(void); +static struct mxc_vpu_platform_data mxc_vpu_data = { + .reset = mx5_vpu_reset, +}; + +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "DA9052_BUCK_CORE", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "DA9052_BUCK_CORE", + .lp_reg_id = "DA9052_BUCK_PRO", +}; + +static struct tve_platform_data tve_data = { + .dac_reg = "DA9052_LDO7", +}; + +static struct ldb_platform_data ldb_data = { + .ext_ref = 1, +}; + +static void mxc_iim_enable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg |= 0x10; + writel(reg, ccm_base + 0x64); +} + +static void mxc_iim_disable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg &= ~0x10; + writel(reg, ccm_base + 0x64); +} + +static struct mxc_iim_data iim_data = { + .bank_start = MXC_IIM_MX53_BANK_START_ADDR, + .bank_end = MXC_IIM_MX53_BANK_END_ADDR, + .enable_fuse = mxc_iim_enable_fuse, + .disable_fuse = mxc_iim_disable_fuse, +}; + +static struct resource mxcfb_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "800x480M@55", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, + { + .interface_pix_fmt = IPU_PIX_FMT_GBR24, + .mode_str = "1024x768M-16@60", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +extern int primary_di; +static int __init mxc_init_fb(void) +{ + if (!machine_is_mx53_loco()) + return 0; + + if (primary_di) { + printk(KERN_INFO "DI1 is primary\n"); + /* DI1 -> DP-BG channel: */ + mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[1].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + + /* DI0 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + } else { + printk(KERN_INFO "DI0 is primary\n"); + + /* DI0 -> DP-BG channel: */ + mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[0].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + + /* DI1 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + } + + /* + * DI0/1 DP-FG channel: + */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +device_initcall(mxc_init_fb); + +static void sii902x_hdmi_reset(void) +{ + gpio_set_value(DISP0_RESET, 0); + msleep(10); + gpio_set_value(DISP0_RESET, 1); + msleep(10); +} + +static struct mxc_lcd_platform_data sii902x_hdmi_data = { + .reset = sii902x_hdmi_reset, +}; + +static struct imxi2c_platform_data mxci2c_data = { + .bitrate = 100000, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + .type = "mma8450", + .addr = 0x1C, + }, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "sii902x", + .addr = 0x39, + .irq = IOMUX_TO_IRQ_V3(DISP0_DET_INT), + .platform_data = &sii902x_hdmi_data, + }, +}; + +static int sdhc_write_protect(struct device *dev) +{ + int ret = 0; + + if (to_platform_device(dev)->id == 2) + ret = gpio_get_value(SD3_WP); + + return ret; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret = 0; + + if (to_platform_device(dev)->id == 2) + ret = gpio_get_value(SD3_CD); + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 1, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static int headphone_det_status(void) +{ + return (gpio_get_value(HEADPHONE_DEC_B) == 0); +} + +static int mxc_sgtl5000_init(void); + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 5, + .hp_irq = IOMUX_TO_IRQ_V3(HEADPHONE_DEC_B), + .hp_status = headphone_det_status, + .init = mxc_sgtl5000_init, +}; + +static int mxc_sgtl5000_init(void) +{ + struct clk *ssi_ext1; + int rate; + + ssi_ext1 = clk_get(NULL, "ssi_ext1_clk"); + if (IS_ERR(ssi_ext1)) + return -1; + + rate = clk_round_rate(ssi_ext1, 24000000); + if (rate < 8000000 || rate > 27000000) { + printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n", + rate); + clk_put(ssi_ext1); + return -1; + } + + clk_set_rate(ssi_ext1, rate); + clk_enable(ssi_ext1); + sgtl5000_data.sysclk = rate; + + return 0; +} + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static struct mxc_asrc_platform_data mxc_asrc_data = { + .channel_bits = 4, + .clk_map_ver = 2, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 0, + .spdif_clk_44100 = -1, /* Souce from CKIH1 for 44.1K */ + /* Source from CCM spdif_clk (24M) for 48k and 32k + * It's not accurate + */ + .spdif_clk_48000 = 1, + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static void mx53_loco_usbh1_vbus(bool on) +{ + if (on) + gpio_set_value(USB_PWREN, 1); + else + gpio_set_value(USB_PWREN, 0); +} + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ +{ \ + .gpio = gpio_num, \ + .type = EV_KEY, \ + .code = ev_code, \ + .active_low = act_low, \ + .desc = "btn " descr, \ + .wakeup = wake, \ +} + +static struct gpio_keys_button loco_buttons[] = { + GPIO_BUTTON(MX53_nONKEY, KEY_POWER, 1, "power", 0), + GPIO_BUTTON(USER_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), + GPIO_BUTTON(USER_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), +}; + +static struct gpio_keys_platform_data loco_button_data = { + .buttons = loco_buttons, + .nbuttons = ARRAY_SIZE(loco_buttons), +}; + +static struct platform_device loco_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &loco_button_data, + } +}; + +static void __init loco_add_device_buttons(void) +{ + platform_device_register(&loco_button_device); +} +#else +static void __init loco_add_device_buttons(void) {} +#endif + + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + struct tag *t; + struct tag *mem_tag = 0; + int total_mem = SZ_1G; + int left_mem = 0; + int gpu_mem = SZ_128M; + int fb_mem = SZ_32M; + char *str; + + mxc_set_cpu_type(MXC_CPU_MX53); + + for_each_tag(mem_tag, tags) { + if (mem_tag->hdr.tag == ATAG_MEM) { + total_mem = mem_tag->u.mem.size; + left_mem = total_mem - gpu_mem - fb_mem; + break; + } + } + + for_each_tag(t, tags) { + if (t->hdr.tag == ATAG_CMDLINE) { + str = t->u.cmdline.cmdline; + str = strstr(str, "mem="); + if (str != NULL) { + str += 4; + left_mem = memparse(str, &str); + if (left_mem == 0 || left_mem > total_mem) + left_mem = total_mem - gpu_mem - fb_mem; + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_memory="); + if (str != NULL) { + str += 11; + gpu_mem = memparse(str, &str); + } + + break; + } + } + + if (mem_tag) { + fb_mem = total_mem - left_mem - gpu_mem; + if (fb_mem < 0) { + gpu_mem = total_mem - left_mem; + fb_mem = 0; + } + mem_tag->u.mem.size = left_mem; + + /*reserve memory for gpu*/ + gpu_device.resource[5].start = + mem_tag->u.mem.start + left_mem; + gpu_device.resource[5].end = + gpu_device.resource[5].start + gpu_mem - 1; +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) + if (fb_mem) { + mxcfb_resources[0].start = + gpu_device.resource[5].end + 1; + mxcfb_resources[0].end = + mxcfb_resources[0].start + fb_mem - 1; + } else { + mxcfb_resources[0].start = 0; + mxcfb_resources[0].end = 0; + } +#endif + } +} + +static void __init mx53_loco_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, + ARRAY_SIZE(mx53_loco_pads)); + + /* SD3 */ + gpio_request(SD3_CD, "sd3-cd"); + gpio_direction_input(SD3_CD); + gpio_request(SD3_WP, "sd3-wp"); + gpio_direction_input(SD3_WP); + + /* reset FEC PHY */ + gpio_request(FEC_RST, "fec-rst"); + gpio_direction_output(FEC_RST, 0); + gpio_set_value(FEC_RST, 0); + msleep(1); + gpio_set_value(FEC_RST, 1); + + /* headphone_det_b */ + gpio_request(HEADPHONE_DEC_B, "headphone-dec"); + gpio_direction_input(HEADPHONE_DEC_B); + + /* USB PWR enable */ + gpio_request(USB_PWREN, "usb-pwr"); + gpio_direction_output(USB_PWREN, 0); + + /* Sii902x HDMI controller */ + gpio_request(DISP0_RESET, "disp0-reset"); + gpio_direction_output(DISP0_RESET, 0); + gpio_request(DISP0_DET_INT, "disp0-detect"); + gpio_direction_input(DISP0_DET_INT); + + /* LCD panel power enable */ + gpio_request(DISP0_POWER_EN, "disp0-power-en"); + gpio_direction_output(DISP0_POWER_EN, 1); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "ssi_ext1_clk"); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); + + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(SD3_CD); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(SD3_CD); + + mxc_cpu_common_init(); + mx53_loco_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + + mx53_loco_init_da9052(); + + mxc_register_device(&mxc_rtc_device, NULL); + mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); + mxc_register_device(&mxc_ldb_device, &ldb_data); + mxc_register_device(&mxc_tve_device, &tve_data); + mxc_register_device(&mxcvpu_device, &mxc_vpu_data); + mxc_register_device(&gpu_device, &z160_revision); + mxc_register_device(&mxcscc_device, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&busfreq_device, &bus_freq_data); + mxc_register_device(&mxc_iim_device, &iim_data); + mxc_register_device(&mxc_pwm2_device, NULL); + mxc_register_device(&mxc_pwm1_backlight_device, &mxc_pwm_backlight_data); + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); + mxc_register_device(&ahci_fsl_device, &sata_data); + mxc_register_device(&mxc_fec_device, &fec_data); + /* ASRC is only available for MX53 TO2.0 */ + if (cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) { + mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + clk_put(mxc_asrc_data.asrc_core_clk); + mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); + clk_put(mxc_asrc_data.asrc_audio_clk); + mxc_register_device(&mxc_asrc_device, &mxc_asrc_data); + } + + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mx5_usb_dr_init(); + mx5_set_host1_vbus_func(mx53_loco_usbh1_vbus); + mx5_usbh1_init(); + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); + loco_add_device_buttons(); +} + +static void __init mx53_loco_timer_init(void) +{ + struct clk *uart_clk; + + mx53_clocks_init(32768, 24000000, 0, 0); + + uart_clk = clk_get_sys("mxcintuart.0", NULL); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx53_loco_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX53_LOCO data structure. + */ +MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c b/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c new file mode 100644 index 000000000000..e11243b67043 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +/* + * mx53_loco_pmic_da9053.c -- i.MX53 LOCO driver for pmic da9053 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DA9052_LDO(max, min, rname, suspend_mv) \ +{\ + .constraints = {\ + .name = (rname), \ + .max_uV = (max) * 1000,\ + .min_uV = (min) * 1000,\ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE\ + |REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE,\ + .valid_modes_mask = REGULATOR_MODE_NORMAL,\ + .state_mem = { \ + .uV = suspend_mv * 1000, \ + .mode = REGULATOR_MODE_NORMAL, \ + .enabled = (0 == suspend_mv) ? 0 : 1, \ + .disabled = 0, \ + }, \ + },\ +} + +/* currently the suspend_mv here takes no effects for DA9053 +preset-voltage have to be done in the latest stage during +suspend*/ +static struct regulator_init_data da9052_regulators_init[] = { + DA9052_LDO(DA9052_LDO1_VOLT_UPPER, + DA9052_LDO1_VOLT_LOWER, "DA9052_LDO1", 1300), + DA9052_LDO(DA9052_LDO2_VOLT_UPPER, + DA9052_LDO2_VOLT_LOWER, "DA9052_LDO2", 1300), + DA9052_LDO(DA9052_LDO34_VOLT_UPPER, + DA9052_LDO34_VOLT_LOWER, "DA9052_LDO3", 3300), + DA9052_LDO(DA9052_LDO34_VOLT_UPPER, + DA9052_LDO34_VOLT_LOWER, "DA9052_LDO4", 2775), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO5", 1300), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO6", 1200), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO7", 2750), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO8", 1800), + DA9052_LDO(DA9052_LDO9_VOLT_UPPER, + DA9052_LDO9_VOLT_LOWER, "DA9052_LDO9", 2500), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO10", 1200), + + /* BUCKS */ + DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER, + DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_CORE", 850), + DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER, + DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_PRO", 950), + DA9052_LDO(DA9052_BUCK_MEM_VOLT_UPPER, + DA9052_BUCK_MEM_VOLT_LOWER, "DA9052_BUCK_MEM", 1500), + DA9052_LDO(DA9052_BUCK_PERI_VOLT_UPPER, + DA9052_BUCK_PERI_VOLT_LOWER, "DA9052_BUCK_PERI", 2500) +}; + + +static struct da9052_tsi_platform_data da9052_tsi = { + .pen_up_interval = 50, + .tsi_delay_bit_shift = 6, + .tsi_skip_bit_shift = 3, + .num_gpio_tsi_register = 3, + .tsi_supply_voltage = 2500, + /* This is the DA9052 LDO number used for powering the TSI */ + .tsi_ref_source = 9, + .max_tsi_delay = TSI_DELAY_4SLOTS, + .max_tsi_skip_slot = TSI_SKIP_330SLOTS, +}; + +static struct da9052_led_platform_data da9052_gpio_led[] = { + { + .id = DA9052_LED_4, + .name = "LED_GPIO14", + }, + { + .id = DA9052_LED_5, + .name = "LED_GPIO15", + }, +}; + +static struct da9052_leds_platform_data da9052_gpio_leds = { + .num_leds = ARRAY_SIZE(da9052_gpio_led), + .led = da9052_gpio_led, +}; + + +static struct da9052_bat_platform_data da9052_bat = { + .sw_temp_control_en = 0, + .monitoring_interval = 500, + .sw_bat_temp_threshold = 60, + .sw_junc_temp_threshold = 120, + .hysteresis_window_size = 1, + .current_monitoring_window = 10, + .bat_with_no_resistor = 62, + .bat_capacity_limit_low = 4, + .bat_capacity_full = 100, + .bat_capacity_limit_high = 70, + .chg_hysteresis_const = 89, + .hysteresis_reading_interval = 1000, + .hysteresis_no_of_reading = 10, + .filter_size = 4, + .bat_volt_cutoff = 2800, + .vbat_first_valid_detect_iteration = 3, +}; + +static void da9052_init_ssc_cache(struct da9052 *da9052) +{ + unsigned char cnt; + + /* First initialize all registers as Non-volatile */ + for (cnt = 0; cnt < DA9052_REG_CNT; cnt++) { + da9052->ssc_cache[cnt].type = NON_VOLATILE; + da9052->ssc_cache[cnt].status = INVALID; + da9052->ssc_cache[cnt].val = 0; + } + + /* Now selectively set type for all Volatile registers */ + /* Reg 1 - 9 */ + da9052->ssc_cache[DA9052_STATUSA_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_STATUSB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_STATUSC_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_STATUSD_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_EVENTA_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_EVENTB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_EVENTC_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_EVENTD_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_FAULTLOG_REG].type = VOLATILE; + + /* Reg 15 */ + da9052->ssc_cache[DA9052_CONTROLB_REG].type = VOLATILE; + /* Reg - 17 */ + da9052->ssc_cache[DA9052_CONTROLD_REG].type = VOLATILE; + /* Reg - 60 */ + da9052->ssc_cache[DA9052_SUPPLY_REG].type = VOLATILE; + /* Reg - 62 */ + da9052->ssc_cache[DA9052_CHGBUCK_REG].type = VOLATILE; + + /* Reg 67 - 68 */ + da9052->ssc_cache[DA9052_INPUTCONT_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_CHGTIME_REG].type = VOLATILE; + + /* Reg - 70 */ + da9052->ssc_cache[DA9052_BOOST_REG].type = VOLATILE; + + /* Reg - 81 */ + da9052->ssc_cache[DA9052_ADCMAN_REG].type = VOLATILE; + + /* Reg - 83 - 85 */ + da9052->ssc_cache[DA9052_ADCRESL_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_ADCRESH_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_VDDRES_REG].type = VOLATILE; + + /* Reg - 87 */ + da9052->ssc_cache[DA9052_ICHGAV_REG].type = VOLATILE; + + /* Reg - 90 */ + da9052->ssc_cache[DA9052_TBATRES_REG].type = VOLATILE; + + /* Reg - 95 */ + da9052->ssc_cache[DA9052_ADCIN4RES_REG].type = VOLATILE; + + /* Reg - 98 */ + da9052->ssc_cache[DA9052_ADCIN5RES_REG].type = VOLATILE; + + /* Reg - 101 */ + da9052->ssc_cache[DA9052_ADCIN6RES_REG].type = VOLATILE; + + /* Reg - 104 */ + da9052->ssc_cache[DA9052_TJUNCRES_REG].type = VOLATILE; + + /* Reg 106 - 110 */ + da9052->ssc_cache[DA9052_TSICONTB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_TSIXMSB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_TSIYMSB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_TSILSB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_TSIZMSB_REG].type = VOLATILE; + + /* Reg 111 - 117 */ + da9052->ssc_cache[DA9052_COUNTS_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTMI_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTH_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTD_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTMO_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTY_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_ALARMMI_REG].type = VOLATILE; + + /* Reg 122 - 125 */ + da9052->ssc_cache[DA9052_SECONDA_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_SECONDB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_SECONDC_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_SECONDD_REG].type = VOLATILE; + + /* Following addresses are not assigned to any register */ + da9052->ssc_cache[126].type = VOLATILE; + da9052->ssc_cache[127].type = VOLATILE; +} + + +#define MX53_LOCO_DA9052_IRQ (6*32 + 11) /* GPIO7_11 */ + +static int __init loco_da9052_init(struct da9052 *da9052) +{ + /* Configuring for DA9052 interrupt servce */ + /* s3c_gpio_setpull(DA9052_IRQ_PIN, S3C_GPIO_PULL_UP);*/ + + /* Set interrupt as LOW LEVEL interrupt source */ + set_irq_type(IOMUX_TO_IRQ_V3(MX53_LOCO_DA9052_IRQ), IRQF_TRIGGER_LOW); + + da9052_init_ssc_cache(da9052); + + return 0; +} + +static struct da9052_platform_data __initdata da9052_plat = { + .init = loco_da9052_init, + .num_regulators = ARRAY_SIZE(da9052_regulators_init), + .regulators = da9052_regulators_init, + .led_data = &da9052_gpio_leds, + .tsi_data = &da9052_tsi, + .bat_data = &da9052_bat, + /* .gpio_base = GPIO_BOARD_START, */ +}; + + +static struct i2c_board_info __initdata da9052_i2c_device = { + I2C_BOARD_INFO(DA9052_SSC_I2C_DEVICE_NAME, DA9052_I2C_ADDR >> 1), + .irq = IOMUX_TO_IRQ_V3(MX53_LOCO_DA9052_IRQ), + .platform_data = &da9052_plat, +}; + +int __init mx53_loco_init_da9052(void) +{ + return i2c_register_board_info(0, &da9052_i2c_device, 1); +} diff --git a/arch/arm/mach-mx5/mx53_smd.c b/arch/arm/mach-mx5/mx53_smd.c new file mode 100644 index 000000000000..fd46e9de944a --- /dev/null +++ b/arch/arm/mach-mx5/mx53_smd.c @@ -0,0 +1,1122 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "crm_regs.h" +#include "devices.h" +#include "usb.h" + +/*! + * @file mach-mx5/mx53_smd.c + * + * @brief This file contains MX53 smd board specific initialization routines. + * + * @ingroup MSL_MX53 + */ + +/* MX53 SMD GPIO PIN configurations */ +#define MX53_SMD_KEY_RESET (0*32 + 2) /* GPIO1_2 */ +#define MX53_SMD_SATA_CLK_GPEN (0*32 + 4) /* GPIO1_4 */ +#define MX53_SMD_PMIC_FAULT (0*32 + 5) /* GPIO1_5 */ +#define MX53_SMD_SYS_ON_OFF_CTL (0*32 + 7) /* GPIO1_7 */ +#define MX53_SMD_PMIC_ON_OFF_REQ (0*32 + 8) /* GPIO1_8 */ + +#define MX53_SMD_FEC_INT (1*32 + 4) /* GPIO2_4 */ +#define MX53_SMD_HEADPHONE_DEC (1*32 + 5) /* GPIO2_5 */ +#define MX53_SMD_ZIGBEE_INT (1*32 + 6) /* GPIO2_6 */ +#define MX53_SMD_ZIGBEE_RESET_B (1*32 + 7) /* GPIO2_7 */ +#define MX53_SMD_GPS_RESET_B (1*32 + 12) /* GPIO2_12 */ +#define MX53_SMD_WAKEUP_ZIGBEE (1*32 + 13) /* GPIO2_13 */ +#define MX53_SMD_KEY_VOL_DOWN (1*32 + 14) /* GPIO2_14 */ +#define MX53_SMD_KEY_VOL_UP (1*32 + 15) /* GPIO2_15 */ +#define MX53_SMD_FEC_PWR_EN (1*32 + 16) /* GPIO_2_16 */ +#define MX53_SMD_LID_OPN_CLS_SW (1*32 + 23) /* GPIO_2_23 */ +#define MX53_SMD_GPS_PPS (1*32 + 24) /* GPIO_2_24 */ + +#define MX53_SMD_DCDC1V8_EN (2*32 + 1) /*GPIO_3_1 */ +#define MX53_SMD_AUD_AMP_STBY_B (2*32 + 2) /*GPIO_3_2 */ +#define MX53_SMD_SATA_PWR_EN (2*32 + 3) /*GPIO_3_3 */ +#define MX53_SMD_TPM_OSC_EN (2*32 + 4) /*GPIO_3_4 */ +#define MX53_SMD_WLAN_PD (2*32 + 5) /*GPIO_3_5 */ +#define MX53_SMD_WiFi_BT_PWR_EN (2*32 + 10) /*GPIO_3_10 */ +#define MX53_SMD_RECOVERY_MODE_SW (2*32 + 11) /*GPIO_3_11 */ +#define MX53_SMD_USB_OTG_OC (2*32 + 12) /*GPIO_3_12 */ +#define MX53_SMD_SD1_CD (2*32 + 13) /*GPIO_3_13 */ +#define MX53_SMD_USB_HUB_RESET_B (2*32 + 14) /*GPIO_3_14 */ +#define MX53_SMD_eCOMPASS_INT (2*32 + 15) /*GPIO_3_15 */ +#define MX53_SMD_CAP_TCH_INT1 (2*32 + 20) /* GPIO_3_20 */ +#define MX53_SMD_BT_PRIORITY (2*32 + 21) /* GPIO_3_21 */ +#define MX53_SMD_ALS_INT (2*32 + 22) /* GPIO_3_22 */ +#define MX53_SMD_TPM_INT (2*32 + 26) /* GPIO_3_26 */ +#define MX53_SMD_MODEM_WKUP (2*32 + 27) /* GPIO_3_27 */ +#define MX53_SMD_BT_RESET (2*32 + 28) /* GPIO_3_28 */ +#define MX53_SMD_TPM_RST_B (2*32 + 29) /* GPIO_3_29 */ +#define MX53_SMD_CHRG_OR_CMOS (2*32 + 30) /* GPIO_3_30 */ +#define MX53_SMD_CAP_TCH_INT0 (2*32 + 31) /* GPIO_3_31 */ + +#define MX53_SMD_CHA_ISET (3*32 + 2) /* GPIO_4_2 */ +#define MX53_SMD_SYS_EJECT (3*32 + 3) /* GPIO_4_3 */ +#define MX53_SMD_HDMI_CEC_D (3*32 + 4) /* GPIO_4_4 */ + +#define MX53_SMD_MODEM_DISABLE_B (3*32 + 10) /* GPIO_4_10 */ +#define MX53_SMD_SD1_WP (3*32 + 11) /* GPIO_4_11 */ +#define MX53_SMD_DCDC5V_BB_EN (3*32 + 14) /* GPIO_4_14 */ +#define MX53_SMD_WLAN_HOST_WAKE (3*32 + 15) /* GPIO_4_15 */ + +#define MX53_SMD_HDMI_RESET_B (4*32 + 0) /* GPIO_5_0 */ +#define MX53_SMD_MODEM_RESET_B (4*32 + 2) /* GPIO_5_2 */ +#define MX53_SMD_KEY_INT (4*32 + 4) /* GPIO_5_4 */ + +#define MX53_SMD_CAP_TCH_FUN0 (5*32 + 6) /* GPIO_6_6 */ +#define MX53_SMD_CSI0_RST (5*32 + 9) /* GPIO_6_9 */ +#define MX53_SMD_CSI0_PWN (5*32 + 10) /* GPIO_6_10 */ +#define MX53_SMD_OSC_CKIH1_EN (5*32 + 11) /* GPIO_6_11 */ +#define MX53_SMD_HDMI_INT (5*32 + 12) /* GPIO_6_12 */ +#define MX53_SMD_LCD_PWR_EN (5*32 + 13) /* GPIO_6_13 */ +#define MX53_SMD_ACCL_INT1_IN (5*32 + 15) /* GPIO_6_15 */ +#define MX53_SMD_ACCL_INT2_IN (5*32 + 16) /* GPIO_6_16 */ +#define MX53_SMD_AC_IN (5*32 + 17) /* GPIO_6_17 */ +#define MX53_SMD_PWR_GOOD (5*32 + 18) /* GPIO_6_18 */ + +#define MX53_SMD_CABC_EN0 (6*32 + 2) /* GPIO_7_2 */ +#define MX53_SMD_DOCK_DECTECT (6*32 + 3) /* GPIO_7_3 */ +#define MX53_SMD_FEC_RST (6*32 + 6) /* GPIO_7_6 */ +#define MX53_SMD_USER_DEG_CHG_NONE (6*32 + 7) /* GPIO_7_7 */ +#define MX53_SMD_USB_OTG_PWR_EN (6*32 + 8) /* GPIO_7_8 */ +#define MX53_SMD_DEVELOP_MODE_SW (6*32 + 9) /* GPIO_7_9 */ +#define MX53_SMD_CABC_EN1 (6*32 + 10) /* GPIO_7_10 */ +#define MX53_SMD_PMIC_INT (6*32 + 11) /* GPIO_7_11 */ +#define MX53_SMD_CAP_TCH_FUN1 (6*32 + 13) /* GPIO_7_13 */ + +extern int __init mx53_smd_init_da9052(void); + +static struct pad_desc mx53_smd_pads[] = { + /* DI_VGA_HSYNC */ + MX53_PAD_EIM_OE__DI1_PIN7, + /* HDMI reset */ + MX53_PAD_EIM_WAIT__GPIO_5_0, + /* DI_VGA_VSYNC */ + MX53_PAD_EIM_RW__DI1_PIN8, + /* CSPI1 */ + MX53_PAD_EIM_EB2__CSPI_SS0, + MX53_PAD_EIM_D16__CSPI1_SCLK, + MX53_PAD_EIM_D17__CSPI1_MISO, + MX53_PAD_EIM_D18__CSPI1_MOSI, + MX53_PAD_EIM_D19__CSPI_SS1, + /* BT: UART3*/ + MX53_PAD_EIM_D23__UART3_CTS, + MX53_PAD_EIM_D24_UART3_TXD, + MX53_PAD_EIM_EB3__UART3_RTS, + MX53_PAD_EIM_D25__UART3_RXD, + /* LID_OPN_CLS_SW*/ + MX53_PAD_EIM_CS0__GPIO_2_23, + /* GPS_PPS */ + MX53_PAD_EIM_CS1__GPIO_2_24, + /* FEC_PWR_EN */ + MX53_PAD_EIM_A22__GPIO_2_16, + /* CAP_TCH_FUN0*/ + MX53_PAD_EIM_A23__GPIO_6_6, + /* KEY_INT */ + MX53_PAD_EIM_A24__GPIO_5_4, + /* MODEM_RESET_B */ + MX53_PAD_EIM_A25__GPIO_5_2, + /* CAP_TCH_INT1 */ + MX53_PAD_EIM_D20__GPIO_3_20, + /* BT_PRIORITY */ + MX53_PAD_EIM_D21__GPIO_3_21, + /* ALS_INT */ + MX53_PAD_EIM_D22__GPIO_3_22, + /* TPM_INT */ + MX53_PAD_EIM_D26__GPIO_3_26, + /* MODEM_WKUP */ + MX53_PAD_EIM_D27__GPIO_3_27, + /* BT_RESET */ + MX53_PAD_EIM_D28__GPIO_3_28, + /* TPM_RST_B */ + MX53_PAD_EIM_D29__GPIO_3_29, + /* CHARGER_NOW_OR_CMOS_RUN */ + MX53_PAD_EIM_D30__GPIO_3_30, + /* CAP_TCH_INT0 */ + MX53_PAD_EIM_D31__GPIO_3_31, + /* DCDC1V8_EN */ + MX53_PAD_EIM_DA1__GPIO_3_1, + /* AUD_AMP_STBY_B */ + MX53_PAD_EIM_DA2__GPIO_3_2, + /* SATA_PWR_EN */ + MX53_PAD_EIM_DA3__GPIO_3_3, + /* TPM_OSC_EN */ + MX53_PAD_EIM_DA4__GPIO_3_4, + /* WLAN_PD */ + MX53_PAD_EIM_DA5__GPIO_3_5, + /* WiFi_BT_PWR_EN */ + MX53_PAD_EIM_DA10__GPIO_3_10, + /* RECOVERY_MODE_SW */ + MX53_PAD_EIM_DA11__GPIO_3_11, + /* USB_OTG_OC */ + MX53_PAD_EIM_DA12__GPIO_3_12, + /* SD1_CD */ + MX53_PAD_EIM_DA13__GPIO_3_13, + /* USB_HUB_RESET_B */ + MX53_PAD_EIM_DA14__GPIO_3_14, + /* eCOMPASS_IN */ + MX53_PAD_EIM_DA15__GPIO_3_15, + /* HDMI_INT */ + MX53_PAD_NANDF_WE_B__GPIO_6_12, + /* LCD_PWR_EN */ + MX53_PAD_NANDF_RE_B__GPIO_6_13, + /* CSI0_RST */ + MX53_PAD_NANDF_WP_B__GPIO_6_9, + /* CSI0_PWN */ + MX53_PAD_NANDF_RB0__GPIO_6_10, + /* OSC_CKIH1_EN */ + MX53_PAD_NANDF_CS0__GPIO_6_11, + /* ACCL_INT1_IN */ + MX53_PAD_NANDF_CS2__GPIO_6_15, + /* ACCL_INT2_IN */ + MX53_PAD_NANDF_CS3__GPIO_6_16, + /* AUDMUX */ + MX53_PAD_CSI0_D4__AUD3_TXC, + MX53_PAD_CSI0_D5__AUD3_TXD, + MX53_PAD_CSI0_D6__AUD3_TXFS, + MX53_PAD_CSI0_D7__AUD3_RXD, + /* I2C1 */ + MX53_PAD_CSI0_D8__I2C1_SDA, + MX53_PAD_CSI0_D9__I2C1_SCL, + /* UART1 */ + MX53_PAD_CSI0_D10__UART1_TXD, + MX53_PAD_CSI0_D11__UART1_RXD, + /* CSI0 */ + MX53_PAD_CSI0_D12__CSI0_D12, + MX53_PAD_CSI0_D13__CSI0_D13, + MX53_PAD_CSI0_D14__CSI0_D14, + MX53_PAD_CSI0_D15__CSI0_D15, + MX53_PAD_CSI0_D16__CSI0_D16, + MX53_PAD_CSI0_D17__CSI0_D17, + MX53_PAD_CSI0_D18__CSI0_D18, + MX53_PAD_CSI0_D19__CSI0_D19, + MX53_PAD_CSI0_VSYNC__CSI0_VSYNC, + MX53_PAD_CSI0_MCLK__CSI0_HSYNC, + MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK, + /* DISPLAY */ + MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK, + MX53_PAD_DI0_PIN15__DI0_PIN15, + MX53_PAD_DI0_PIN2__DI0_PIN2, + MX53_PAD_DI0_PIN3__DI0_PIN3, + MX53_PAD_DISP0_DAT0__DISP0_DAT0, + MX53_PAD_DISP0_DAT1__DISP0_DAT1, + MX53_PAD_DISP0_DAT2__DISP0_DAT2, + MX53_PAD_DISP0_DAT3__DISP0_DAT3, + MX53_PAD_DISP0_DAT4__DISP0_DAT4, + MX53_PAD_DISP0_DAT5__DISP0_DAT5, + MX53_PAD_DISP0_DAT6__DISP0_DAT6, + MX53_PAD_DISP0_DAT7__DISP0_DAT7, + MX53_PAD_DISP0_DAT8__DISP0_DAT8, + MX53_PAD_DISP0_DAT9__DISP0_DAT9, + MX53_PAD_DISP0_DAT10__DISP0_DAT10, + MX53_PAD_DISP0_DAT11__DISP0_DAT11, + MX53_PAD_DISP0_DAT12__DISP0_DAT12, + MX53_PAD_DISP0_DAT13__DISP0_DAT13, + MX53_PAD_DISP0_DAT14__DISP0_DAT14, + MX53_PAD_DISP0_DAT15__DISP0_DAT15, + MX53_PAD_DISP0_DAT16__DISP0_DAT16, + MX53_PAD_DISP0_DAT17__DISP0_DAT17, + MX53_PAD_DISP0_DAT18__DISP0_DAT18, + MX53_PAD_DISP0_DAT19__DISP0_DAT19, + MX53_PAD_DISP0_DAT20__DISP0_DAT20, + MX53_PAD_DISP0_DAT21__DISP0_DAT21, + MX53_PAD_DISP0_DAT22__DISP0_DAT22, + MX53_PAD_DISP0_DAT23__DISP0_DAT23, + /* FEC */ + MX53_PAD_FEC_MDC__FEC_MDC, + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_REF_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_CRS_DV, + MX53_PAD_FEC_RXD1__FEC_RXD1, + MX53_PAD_FEC_RXD0__FEC_RXD0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TXD1, + MX53_PAD_FEC_TXD0__FEC_TXD0, + /* AUDMUX5 */ + MX53_PAD_KEY_COL0__AUD5_TXC, + MX53_PAD_KEY_ROW0__AUD5_TXD, + MX53_PAD_KEY_COL1__AUD5_TXFS, + MX53_PAD_KEY_ROW1__AUD5_RXD, + /* MODEM_DISABLE_B */ + MX53_PAD_KEY_COL2__GPIO_4_10, + /* SD1_WP */ + MX53_PAD_KEY_ROW2__GPIO_4_11, + /* I2C2 */ + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, + /* DCDC5V_BB_EN */ + MX53_PAD_KEY_COL4__GPIO_4_14, + /* WLAN_HOST_WAKE */ + MX53_PAD_KEY_ROW4__GPIO_4_15, + /* SD1 */ + MX53_PAD_SD1_CMD__SD1_CMD, + MX53_PAD_SD1_CLK__SD1_CLK, + MX53_PAD_SD1_DATA0__SD1_DATA0, + MX53_PAD_SD1_DATA1__SD1_DATA1, + MX53_PAD_SD1_DATA2__SD1_DATA2, + MX53_PAD_SD1_DATA3__SD1_DATA3, + /* SD2 */ + MX53_PAD_SD2_CMD__SD2_CMD, + MX53_PAD_SD2_CLK__SD2_CLK, + MX53_PAD_SD2_DATA0__SD2_DAT0, + MX53_PAD_SD2_DATA1__SD2_DAT1, + MX53_PAD_SD2_DATA2__SD2_DAT2, + MX53_PAD_SD2_DATA3__SD2_DAT3, + /* UART2 */ + MX53_PAD_ATA_BUFFER_EN__UART2_RXD, + MX53_PAD_ATA_DMARQ__UART2_TXD, + /* DEVELOP_MODE_SW */ + MX53_PAD_ATA_CS_0__GPIO_7_9, + /* CABC_EN1 */ + MX53_PAD_ATA_CS_1__GPIO_7_10, + /* FEC_nRST */ + MX53_PAD_ATA_DA_0__GPIO_7_6, + /* USER_DEBUG_OR_CHARGER_DONE */ + MX53_PAD_ATA_DA_1__GPIO_7_7, + /* USB_OTG_PWR_EN */ + MX53_PAD_ATA_DA_2__GPIO_7_8, + /* SD3 */ + MX53_PAD_ATA_DATA8__SD3_DAT0, + MX53_PAD_ATA_DATA9__SD3_DAT1, + MX53_PAD_ATA_DATA10__SD3_DAT2, + MX53_PAD_ATA_DATA11__SD3_DAT3, + MX53_PAD_ATA_DATA0__SD3_DAT4, + MX53_PAD_ATA_DATA1__SD3_DAT5, + MX53_PAD_ATA_DATA2__SD3_DAT6, + MX53_PAD_ATA_DATA3__SD3_DAT7, + MX53_PAD_ATA_IORDY__SD3_CLK, + MX53_PAD_ATA_RESET_B__SD3_CMD, + /* FEC_nINT */ + MX53_PAD_ATA_DATA4__GPIO_2_4, + /* HEADPHONE DET*/ + MX53_PAD_ATA_DATA5__GPIO_2_5, + /* ZigBee_INT*/ + MX53_PAD_ATA_DATA6__GPIO_2_6, + /* ZigBee_RESET_B */ + MX53_PAD_ATA_DATA7__GPIO_2_7, + /* GPS_RESET_B*/ + MX53_PAD_ATA_DATA12__GPIO_2_12, + /* WAKEUP_ZigBee */ + MX53_PAD_ATA_DATA13__GPIO_2_13, + /* KEY_VOL- */ + MX53_PAD_ATA_DATA14__GPIO_2_14, + /* KEY_VOL+ */ + MX53_PAD_ATA_DATA15__GPIO_2_15, + /* DOCK_DECTECT */ + MX53_PAD_ATA_DIOR__GPIO_7_3, + /* AC_IN */ + MX53_PAD_ATA_DIOW__GPIO_6_17, + /* PWR_GOOD */ + MX53_PAD_ATA_DMACK__GPIO_6_18, + /* CABC_EN0 */ + MX53_PAD_ATA_INTRQ__GPIO_7_2, + MX53_PAD_GPIO_0__SSI_EXT1_CLK, + MX53_PAD_GPIO_1__PWMO, + /* KEY_RESET */ + MX53_PAD_GPIO_2__GPIO_1_2, + /* I2C3 */ + MX53_PAD_GPIO_3__I2C3_SCL, + MX53_PAD_GPIO_6__I2C3_SDA, + /* SATA_CLK_GPEN */ + MX53_PAD_GPIO_4__GPIO_1_4, + /* PMIC_FAULT */ + MX53_PAD_GPIO_5__GPIO_1_5, + /* SYS_ON_OFF_CTL */ + MX53_PAD_GPIO_7__GPIO_1_7, + /* PMIC_ON_OFF_REQ */ + MX53_PAD_GPIO_8__GPIO_1_8, + /* CHA_ISET */ + MX53_PAD_GPIO_12__GPIO_4_2, + /* SYS_EJECT */ + MX53_PAD_GPIO_13__GPIO_4_3, + /* HDMI_CEC_D */ + MX53_PAD_GPIO_14__GPIO_4_4, + /* PMIC_INT */ + MX53_PAD_GPIO_16__GPIO_7_11, + MX53_PAD_GPIO_17__SPDIF_OUT1, + /* CAP_TCH_FUN1 */ + MX53_PAD_GPIO_18__GPIO_7_13, + /* LVDS */ + MX53_PAD_LVDS0_TX3_P__LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LVDS0_TX0, + MX53_PAD_LVDS1_TX3_P__LVDS1_TX3, + MX53_PAD_LVDS1_TX2_P__LVDS1_TX2, + MX53_PAD_LVDS1_CLK_P__LVDS1_CLK, + MX53_PAD_LVDS1_TX1_P__LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LVDS1_TX0, +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 1600x1200 @ 60 Hz 162M pixel clk*/ + "UXGA", 60, 1600, 1200, 6172, + 304, 64, + 1, 46, + 192, 3, + FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, + /* 2 LVDS modes, had better remove from here */ + { + "1080P60", 60, 1920, 1080, 7692, + 100, 40, + 30, 3, + 10, 2, + 0, + FB_VMODE_NONINTERLACED, + 0,}, + { + "XGA", 60, 1024, 768, 15385, + 220, 40, + 21, 7, + 60, 10, + 0, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { + .pwm_id = 1, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 50000, +}; + +extern void mx5_ipu_reset(void); +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 3, + .reset = mx5_ipu_reset, +}; + +extern void mx5_vpu_reset(void); +static struct mxc_vpu_platform_data mxc_vpu_data = { + .reset = mx5_vpu_reset, +}; + +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + + +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = NULL, + .chipselect_inactive = NULL, +}; + +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "DA9052_BUCK_CORE", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + +static struct mxc_bus_freq_platform_data bus_freq_data = { + .gp_reg_id = "DA9052_BUCK_CORE", + .lp_reg_id = "DA9052_BUCK_PRO", +}; + +static struct tve_platform_data tve_data = { + .dac_reg = "DA9052_LDO7", +}; + +static struct ldb_platform_data ldb_data = { + .ext_ref = 1, +}; + +static void mxc_iim_enable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg |= 0x10; + writel(reg, ccm_base + 0x64); +} + +static void mxc_iim_disable_fuse(void) +{ + u32 reg; + + if (!ccm_base) + return; + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg &= ~0x10; + writel(reg, ccm_base + 0x64); +} + +static struct mxc_iim_data iim_data = { + .bank_start = MXC_IIM_MX53_BANK_START_ADDR, + .bank_end = MXC_IIM_MX53_BANK_END_ADDR, + .enable_fuse = mxc_iim_enable_fuse, + .disable_fuse = mxc_iim_disable_fuse, +}; + +static struct resource mxcfb_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "CLAA-WVGA", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, + { + .interface_pix_fmt = IPU_PIX_FMT_GBR24, + .mode_str = "1024x768M-16@60", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +extern int primary_di; +static int __init mxc_init_fb(void) +{ + if (!machine_is_mx53_smd()) + return 0; + + if (primary_di) { + printk(KERN_INFO "DI1 is primary\n"); + /* DI1 -> DP-BG channel: */ + mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[1].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + + /* DI0 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + } else { + printk(KERN_INFO "DI0 is primary\n"); + + /* DI0 -> DP-BG channel: */ + mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[0].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + + /* DI1 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + } + + /* + * DI0/1 DP-FG channel: + */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +device_initcall(mxc_init_fb); + +static void sii902x_hdmi_reset(void) +{ + gpio_set_value(MX53_SMD_HDMI_RESET_B, 0); + msleep(10); + gpio_set_value(MX53_SMD_HDMI_RESET_B, 1); + msleep(10); +} + +static struct mxc_lcd_platform_data sii902x_hdmi_data = { + .reset = sii902x_hdmi_reset, +}; + +static struct imxi2c_platform_data mxci2c_data = { + .bitrate = 100000, +}; + +static struct mxc_camera_platform_data camera_data = { + .analog_regulator = "DA9052_LDO7", + .core_regulator = "DA9052_LDO9", + .mclk = 24000000, + .csi = 0, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + .type = "mma8451", + .addr = 0x1C, + }, + { + .type = "ov3640", + .addr = 0x3C, + .platform_data = (void *)&camera_data, + }, +}; + +static u16 smd_touchkey_martix[4] = { + KEY_BACK, KEY_HOME, KEY_MENU, KEY_SEARCH, +}; + +static struct mpr121_platform_data mpr121_keyboard_platdata = { + .keycount = ARRAY_SIZE(smd_touchkey_martix), + .vdd_uv = 3300000, + .matrix = smd_touchkey_martix, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "mpr121_touchkey", + .addr = 0x5a, + .irq = IOMUX_TO_IRQ_V3(MX53_SMD_KEY_INT), + .platform_data = &mpr121_keyboard_platdata, + }, +}; + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ +{ \ + .gpio = gpio_num, \ + .type = EV_KEY, \ + .code = ev_code, \ + .active_low = act_low, \ + .desc = "btn " descr, \ + .wakeup = wake, \ +} + +static struct gpio_keys_button smd_buttons[] = { + GPIO_BUTTON(MX53_SMD_KEY_VOL_UP, KEY_VOLUMEUP, 1, "volume-up", 0), + GPIO_BUTTON(MX53_SMD_KEY_VOL_DOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0), +}; + +static struct gpio_keys_platform_data smd_button_data = { + .buttons = smd_buttons, + .nbuttons = ARRAY_SIZE(smd_buttons), +}; + +static struct platform_device smd_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &smd_button_data, + } +}; + +static void __init smd_add_device_buttons(void) +{ + platform_device_register(&smd_button_device); +} +#else +static void __init smd_add_device_buttons(void) {} +#endif + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + .type = "sii902x", + .addr = 0x39, + .irq = IOMUX_TO_IRQ_V3(MX53_SMD_HDMI_INT), + .platform_data = &sii902x_hdmi_data, + }, +}; + +static void mx53_gpio_usbotg_driver_vbus(bool on) +{ + if (on) + gpio_set_value(MX53_SMD_USB_OTG_PWR_EN, 1); + else + gpio_set_value(MX53_SMD_USB_OTG_PWR_EN, 0); +} + +static int sdhc_write_protect(struct device *dev) +{ + int ret = 0; + + if (to_platform_device(dev)->id == 0) + ret = gpio_get_value(MX53_SMD_SD1_WP); + + return ret; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret = 0; + + if (to_platform_device(dev)->id == 0) + ret = gpio_get_value(MX53_SMD_SD1_CD); + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc2_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 1, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_DATA_DDR, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 1, + .clock_mmc = "esdhc_clk", +}; + + +static int mxc_sgtl5000_amp_enable(int enable) +{ + gpio_request(MX53_SMD_AUD_AMP_STBY_B, "amp-standby"); + if (enable) + gpio_direction_output(MX53_SMD_AUD_AMP_STBY_B, 1); + else + gpio_direction_output(MX53_SMD_AUD_AMP_STBY_B, 0); + gpio_free(MX53_SMD_AUD_AMP_STBY_B); + return 0; +} + +static int headphone_det_status(void) +{ + return (gpio_get_value(MX53_SMD_HEADPHONE_DEC) == 0); +} + +static int mxc_sgtl5000_init(void); + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 5, + .hp_irq = IOMUX_TO_IRQ_V3(MX53_SMD_HEADPHONE_DEC), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .init = mxc_sgtl5000_init, +}; + +static int mxc_sgtl5000_init(void) +{ + sgtl5000_data.sysclk = 22579200; + return 0; +} + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +static struct mxc_asrc_platform_data mxc_asrc_data = { + .channel_bits = 4, + .clk_map_ver = 2, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 0, + .spdif_clk_44100 = 0, /* Souce from CKIH1 for 44.1K */ + /* Source from CCM spdif_clk (24M) for 48k and 32k + * It's not accurate + */ + .spdif_clk_48000 = 1, + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static void mx53_smd_bt_reset(void) +{ + gpio_request(MX53_SMD_BT_RESET, "bt-reset"); + gpio_direction_output(MX53_SMD_BT_RESET, 0); + /* pull down reset pin at least >5ms */ + mdelay(6); + /* pull up after power supply BT */ + gpio_set_value(MX53_SMD_BT_RESET, 1); + gpio_free(MX53_SMD_BT_RESET); + msleep(100); + /* Bluetooth need some time to reset */ +} + +static int mx53_smd_bt_power_change(int status) +{ + if (status) + mx53_smd_bt_reset(); + + return 0; +} + +static struct platform_device mxc_bt_rfkill = { + .name = "mxc_bt_rfkill", +}; + +static struct mxc_bt_rfkill_platform_data mxc_bt_rfkill_data = { + .power_change = mx53_smd_bt_power_change, +}; + +static void mx53_smd_power_off(void) +{ + gpio_request(MX53_SMD_SYS_ON_OFF_CTL, "power-off"); + gpio_set_value(MX53_SMD_SYS_ON_OFF_CTL, 0); +} +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + struct tag *t; + struct tag *mem_tag = 0; + int total_mem = SZ_1G; + int left_mem = 0; + int gpu_mem = SZ_128M; + int fb_mem = SZ_32M; + char *str; + + mxc_set_cpu_type(MXC_CPU_MX53); + + for_each_tag(mem_tag, tags) { + if (mem_tag->hdr.tag == ATAG_MEM) { + total_mem = mem_tag->u.mem.size; + left_mem = total_mem - gpu_mem - fb_mem; + break; + } + } + + for_each_tag(t, tags) { + if (t->hdr.tag == ATAG_CMDLINE) { + str = t->u.cmdline.cmdline; + str = strstr(str, "mem="); + if (str != NULL) { + str += 4; + left_mem = memparse(str, &str); + if (left_mem == 0 || left_mem > total_mem) + left_mem = total_mem - gpu_mem - fb_mem; + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_memory="); + if (str != NULL) { + str += 11; + gpu_mem = memparse(str, &str); + } + + break; + } + } + + if (mem_tag) { + fb_mem = total_mem - left_mem - gpu_mem; + if (fb_mem < 0) { + gpu_mem = total_mem - left_mem; + fb_mem = 0; + } + mem_tag->u.mem.size = left_mem; + + /*reserve memory for gpu*/ + gpu_device.resource[5].start = + mem_tag->u.mem.start + left_mem; + gpu_device.resource[5].end = + gpu_device.resource[5].start + gpu_mem - 1; +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) + if (fb_mem) { + mxcfb_resources[0].start = + gpu_device.resource[5].end + 1; + mxcfb_resources[0].end = + mxcfb_resources[0].start + fb_mem - 1; + } else { + mxcfb_resources[0].start = 0; + mxcfb_resources[0].end = 0; + } +#endif + } +} + +static void __init mx53_smd_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, + ARRAY_SIZE(mx53_smd_pads)); + + /* SD1 CD */ + gpio_request(MX53_SMD_SD1_CD, "sd1-cd"); + gpio_direction_input(MX53_SMD_SD1_CD); + /* SD1 WP */ + gpio_request(MX53_SMD_SD1_WP, "sd1-wp"); + gpio_direction_input(MX53_SMD_SD1_WP); + + /* reset FEC PHY */ + gpio_request(MX53_SMD_FEC_RST, "fec-rst"); + gpio_direction_output(MX53_SMD_FEC_RST, 0); + gpio_set_value(MX53_SMD_FEC_RST, 0); + msleep(1); + gpio_set_value(MX53_SMD_FEC_RST, 1); + + /* headphone_det_b */ + gpio_request(MX53_SMD_HEADPHONE_DEC, "headphone-dec"); + gpio_direction_input(MX53_SMD_HEADPHONE_DEC); + + /* USB PWR enable */ + gpio_request(MX53_SMD_USB_OTG_PWR_EN, "usb-pwr"); + gpio_direction_output(MX53_SMD_USB_OTG_PWR_EN, 0); + + /* Enable MX53_SMD_DCDC1V8_EN */ + gpio_request(MX53_SMD_DCDC1V8_EN, "dcdc1v8-en"); + gpio_direction_output(MX53_SMD_DCDC1V8_EN, 1); + gpio_set_value(MX53_SMD_DCDC1V8_EN, 1); + + /* Enable OSC_CKIH1_EN for audio */ + gpio_request(MX53_SMD_OSC_CKIH1_EN, "osc-en"); + gpio_direction_output(MX53_SMD_OSC_CKIH1_EN, 1); + gpio_set_value(MX53_SMD_OSC_CKIH1_EN, 1); + + /* Sii902x HDMI controller */ + gpio_request(MX53_SMD_HDMI_RESET_B, "disp0-pwr-en"); + gpio_direction_output(MX53_SMD_HDMI_RESET_B, 0); + gpio_request(MX53_SMD_HDMI_INT, "disp0-det-int"); + gpio_direction_input(MX53_SMD_HDMI_INT); + + /* MPR121 capacitive button */ + gpio_request(MX53_SMD_KEY_INT, "cap-button-irq"); + gpio_direction_input(MX53_SMD_KEY_INT); + gpio_free(MX53_SMD_KEY_INT); + + /* Camera reset */ + gpio_request(MX53_SMD_CSI0_RST, "cam-reset"); + gpio_set_value(MX53_SMD_CSI0_RST, 1); + + /* Camera power down */ + gpio_request(MX53_SMD_CSI0_PWN, "cam-pwdn"); + gpio_direction_output(MX53_SMD_CSI0_PWN, 1); + msleep(1); + gpio_set_value(MX53_SMD_CSI0_PWN, 0); + + /* Enable WiFi/BT Power*/ + gpio_request(MX53_SMD_WiFi_BT_PWR_EN, "bt-wifi-pwren"); + gpio_direction_output(MX53_SMD_WiFi_BT_PWR_EN, 1); + + /* WiFi Power up sequence */ + gpio_request(MX53_SMD_WLAN_PD, "wifi-pd"); + gpio_direction_output(MX53_SMD_WLAN_PD, 1); + mdelay(1); + gpio_set_value(MX53_SMD_WLAN_PD, 0); + mdelay(5); + gpio_set_value(MX53_SMD_WLAN_PD, 1); + gpio_free(MX53_SMD_WLAN_PD); +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "ssi_ext1_clk"); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); + + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(MX53_SMD_SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(MX53_SMD_SD1_CD); + + mxc_cpu_common_init(); + mx53_smd_io_init(); + + pm_power_off = mx53_smd_power_off; + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_devices[2], &mxci2c_data); + mx53_smd_init_da9052(); + + mxc_register_device(&mxc_rtc_device, NULL); + mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); + mxc_register_device(&mxc_ldb_device, &ldb_data); + mxc_register_device(&mxc_tve_device, &tve_data); + mxc_register_device(&mxcvpu_device, &mxc_vpu_data); + mxc_register_device(&gpu_device, &z160_revision); + mxc_register_device(&mxcscc_device, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&busfreq_device, &bus_freq_data); + mxc_register_device(&mxc_iim_device, &iim_data); + mxc_register_device(&mxc_pwm2_device, NULL); + mxc_register_device(&mxc_pwm1_backlight_device, &mxc_pwm_backlight_data); + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc2_device, &mmc2_data); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); + mxc_register_device(&ahci_fsl_device, &sata_data); + /* AHCI SATA PWR EN(DCDC_5V, DCDC_3V3_BB) on SATA bus */ + gpio_request(MX53_SMD_SATA_PWR_EN, "sata-pwr-en"); + gpio_direction_output(MX53_SMD_SATA_PWR_EN, 1); + + mxc_register_device(&mxc_fec_device, &fec_data); + /* ASRC is only available for MX53 TO2.0 */ + if (cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) { + mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + clk_put(mxc_asrc_data.asrc_core_clk); + mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); + clk_put(mxc_asrc_data.asrc_audio_clk); + mxc_register_device(&mxc_asrc_device, &mxc_asrc_data); + } + + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + i2c_register_board_info(2, mxc_i2c2_board_info, + ARRAY_SIZE(mxc_i2c2_board_info)); + + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mx5_set_otghost_vbus_func(mx53_gpio_usbotg_driver_vbus); + mx5_usb_dr_init(); + mx5_usbh1_init(); + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); + mxc_register_device(&mxc_bt_rfkill, &mxc_bt_rfkill_data); + smd_add_device_buttons(); +} + +static void __init mx53_smd_timer_init(void) +{ + struct clk *uart_clk; + + mx53_clocks_init(32768, 24000000, 22579200, 0); + + uart_clk = clk_get_sys("mxcintuart.0", NULL); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx53_smd_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX53_SMD data structure. + */ +MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c b/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c new file mode 100644 index 000000000000..e6cf9e380f30 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +/* + * mx53_smd_pmic_da9053.c -- i.MX53 SMD driver for pmic da9053 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DA9052_LDO(max, min, rname, suspend_mv) \ +{\ + .constraints = {\ + .name = (rname), \ + .max_uV = (max) * 1000,\ + .min_uV = (min) * 1000,\ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE\ + |REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE,\ + .valid_modes_mask = REGULATOR_MODE_NORMAL,\ + .state_mem = { \ + .uV = suspend_mv * 1000, \ + .mode = REGULATOR_MODE_NORMAL, \ + .enabled = (0 == suspend_mv) ? 0 : 1, \ + .disabled = 0, \ + }, \ + },\ +} + +/* currently the suspend_mv field here takes no effects for DA9053 +preset-voltage have to be done in the latest stage during +suspend*/ +static struct regulator_init_data da9052_regulators_init[] = { + DA9052_LDO(DA9052_LDO1_VOLT_UPPER, + DA9052_LDO1_VOLT_LOWER, "DA9052_LDO1", 1300), + DA9052_LDO(DA9052_LDO2_VOLT_UPPER, + DA9052_LDO2_VOLT_LOWER, "DA9052_LDO2", 1300), + DA9052_LDO(DA9052_LDO34_VOLT_UPPER, + DA9052_LDO34_VOLT_LOWER, "DA9052_LDO3", 3300), + DA9052_LDO(DA9052_LDO34_VOLT_UPPER, + DA9052_LDO34_VOLT_LOWER, "DA9052_LDO4", 2775), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO5", 1300), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO6", 1200), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO7", 2750), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO8", 1800), + DA9052_LDO(DA9052_LDO9_VOLT_UPPER, + DA9052_LDO9_VOLT_LOWER, "DA9052_LDO9", 2500), + DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO10", 1200), + + /* BUCKS */ + DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER, + DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_CORE", 850), + DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER, + DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_PRO", 950), + DA9052_LDO(DA9052_BUCK_MEM_VOLT_UPPER, + DA9052_BUCK_MEM_VOLT_LOWER, "DA9052_BUCK_MEM", 1500), + DA9052_LDO(DA9052_BUCK_PERI_VOLT_UPPER, + DA9052_BUCK_PERI_VOLT_LOWER, "DA9052_BUCK_PERI", 2500) +}; + + +#define MX53_SMD_WiFi_BT_PWR_EN (2*32 + 10) /*GPIO_3_10 */ +struct regulator_init_data wifi_bt_reg_initdata = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +static struct fixed_voltage_config wifi_bt_reg_config = { + .supply_name = "wifi_bt", + .microvolts = 3300000, + .gpio = MX53_SMD_WiFi_BT_PWR_EN, + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &wifi_bt_reg_initdata, +}; + +static struct platform_device wifi_bt_reg_device = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &wifi_bt_reg_config, + }, +}; + + +static struct da9052_tsi_platform_data da9052_tsi = { + .pen_up_interval = 50, + .tsi_delay_bit_shift = 6, + .tsi_skip_bit_shift = 3, + .num_gpio_tsi_register = 3, + .tsi_supply_voltage = 2500, + /* This is the DA9052 LDO number used for powering the TSI */ + .tsi_ref_source = 9, + .max_tsi_delay = TSI_DELAY_4SLOTS, + .max_tsi_skip_slot = TSI_SKIP_330SLOTS, +}; + +static struct da9052_led_platform_data da9052_gpio_led[] = { + { + .id = DA9052_LED_4, + .name = "LED_GPIO14", + }, + { + .id = DA9052_LED_5, + .name = "LED_GPIO15", + }, +}; + +static struct da9052_leds_platform_data da9052_gpio_leds = { + .num_leds = ARRAY_SIZE(da9052_gpio_led), + .led = da9052_gpio_led, +}; + + +static struct da9052_bat_platform_data da9052_bat = { + .sw_temp_control_en = 0, + .monitoring_interval = 500, + .sw_bat_temp_threshold = 60, + .sw_junc_temp_threshold = 120, + .hysteresis_window_size = 1, + .current_monitoring_window = 10, + .bat_with_no_resistor = 62, + .bat_capacity_limit_low = 4, + .bat_capacity_full = 100, + .bat_capacity_limit_high = 70, + .chg_hysteresis_const = 89, + .hysteresis_reading_interval = 1000, + .hysteresis_no_of_reading = 10, + .filter_size = 4, + .bat_volt_cutoff = 2800, + .vbat_first_valid_detect_iteration = 3, +}; + +static void da9052_init_ssc_cache(struct da9052 *da9052) +{ + unsigned char cnt; + + /* First initialize all registers as Non-volatile */ + for (cnt = 0; cnt < DA9052_REG_CNT; cnt++) { + da9052->ssc_cache[cnt].type = NON_VOLATILE; + da9052->ssc_cache[cnt].status = INVALID; + da9052->ssc_cache[cnt].val = 0; + } + + /* Now selectively set type for all Volatile registers */ + /* Reg 1 - 9 */ + da9052->ssc_cache[DA9052_STATUSA_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_STATUSB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_STATUSC_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_STATUSD_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_EVENTA_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_EVENTB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_EVENTC_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_EVENTD_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_FAULTLOG_REG].type = VOLATILE; + + /* Reg 15 */ + da9052->ssc_cache[DA9052_CONTROLB_REG].type = VOLATILE; + /* Reg - 17 */ + da9052->ssc_cache[DA9052_CONTROLD_REG].type = VOLATILE; + /* Reg - 60 */ + da9052->ssc_cache[DA9052_SUPPLY_REG].type = VOLATILE; + /* Reg - 62 */ + da9052->ssc_cache[DA9052_CHGBUCK_REG].type = VOLATILE; + + /* Reg 67 - 68 */ + da9052->ssc_cache[DA9052_INPUTCONT_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_CHGTIME_REG].type = VOLATILE; + + /* Reg - 70 */ + da9052->ssc_cache[DA9052_BOOST_REG].type = VOLATILE; + + /* Reg - 81 */ + da9052->ssc_cache[DA9052_ADCMAN_REG].type = VOLATILE; + + /* Reg - 83 - 85 */ + da9052->ssc_cache[DA9052_ADCRESL_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_ADCRESH_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_VDDRES_REG].type = VOLATILE; + + /* Reg - 87 */ + da9052->ssc_cache[DA9052_ICHGAV_REG].type = VOLATILE; + + /* Reg - 90 */ + da9052->ssc_cache[DA9052_TBATRES_REG].type = VOLATILE; + + /* Reg - 95 */ + da9052->ssc_cache[DA9052_ADCIN4RES_REG].type = VOLATILE; + + /* Reg - 98 */ + da9052->ssc_cache[DA9052_ADCIN5RES_REG].type = VOLATILE; + + /* Reg - 101 */ + da9052->ssc_cache[DA9052_ADCIN6RES_REG].type = VOLATILE; + + /* Reg - 104 */ + da9052->ssc_cache[DA9052_TJUNCRES_REG].type = VOLATILE; + + /* Reg 106 - 110 */ + da9052->ssc_cache[DA9052_TSICONTB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_TSIXMSB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_TSIYMSB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_TSILSB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_TSIZMSB_REG].type = VOLATILE; + + /* Reg 111 - 117 */ + da9052->ssc_cache[DA9052_COUNTS_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTMI_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTH_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTD_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTMO_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_COUNTY_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_ALARMMI_REG].type = VOLATILE; + + /* Reg 122 - 125 */ + da9052->ssc_cache[DA9052_SECONDA_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_SECONDB_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_SECONDC_REG].type = VOLATILE; + da9052->ssc_cache[DA9052_SECONDD_REG].type = VOLATILE; + + /* Following addresses are not assigned to any register */ + da9052->ssc_cache[126].type = VOLATILE; + da9052->ssc_cache[127].type = VOLATILE; +} + + +#define MX53_SMD_DA9052_IRQ (6*32 + 11) /* GPIO7_11 */ + +static int __init smd_da9052_init(struct da9052 *da9052) +{ + /* Configuring for DA9052 interrupt servce */ + /* s3c_gpio_setpull(DA9052_IRQ_PIN, S3C_GPIO_PULL_UP);*/ + int ret; + /* Set interrupt as LOW LEVEL interrupt source */ + set_irq_type(IOMUX_TO_IRQ_V3(MX53_SMD_DA9052_IRQ), IRQF_TRIGGER_LOW); + + da9052_init_ssc_cache(da9052); + ret = platform_device_register(&wifi_bt_reg_device); + + return 0; +} + +static struct da9052_platform_data __initdata da9052_plat = { + .init = smd_da9052_init, + .num_regulators = ARRAY_SIZE(da9052_regulators_init), + .regulators = da9052_regulators_init, + .led_data = &da9052_gpio_leds, + .tsi_data = &da9052_tsi, + .bat_data = &da9052_bat, + /* .gpio_base = GPIO_BOARD_START, */ +}; + + +static struct i2c_board_info __initdata da9052_i2c_device = { + I2C_BOARD_INFO(DA9052_SSC_I2C_DEVICE_NAME, DA9052_I2C_ADDR >> 1), + .irq = IOMUX_TO_IRQ_V3(MX53_SMD_DA9052_IRQ), + .platform_data = &da9052_plat, +}; + +int __init mx53_smd_init_da9052(void) +{ + return i2c_register_board_info(0, &da9052_i2c_device, 1); +} diff --git a/arch/arm/mach-mx5/mx53_smd_rfkill.c b/arch/arm/mach-mx5/mx53_smd_rfkill.c new file mode 100644 index 000000000000..f0f95a839381 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_smd_rfkill.c @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file mxc_bt_rfkill.c + * + * @brief This driver is implement a rfkill control interface of bluetooth + * chip on i.MX serial boards. Register the power regulator function and + * reset function in platform data. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int mxc_bt_set_block(void *rfkdata, bool blocked) +{ + struct mxc_bt_rfkill_platform_data *data = rfkdata; + int ret; + + pr_info("rfkill: BT RF going to : %s\n", blocked ? "off" : "on"); + if (!blocked) + ret = data->power_change(1); + else + ret = data->power_change(0); + + return ret; +} + +static const struct rfkill_ops mxc_bt_rfkill_ops = { + .set_block = mxc_bt_set_block, +}; + +static int mxc_bt_rfkill_probe(struct platform_device *dev) +{ + int rc; + struct rfkill *rfk; + + struct mxc_bt_rfkill_platform_data *data = dev->dev.platform_data; + + if (data->power_change == NULL) { + rc = -EINVAL; + dev_err(&dev->dev, "no power_change function\n"); + goto error_check_func; + } + + rfk = rfkill_alloc("mxc-bt", &dev->dev, RFKILL_TYPE_BLUETOOTH, + &mxc_bt_rfkill_ops, data); + + if (!rfk) { + rc = -ENOMEM; + goto error_rfk_alloc; + } + + rfkill_set_led_trigger_name(rfk, "mxc_bt"); + + rc = rfkill_register(rfk); + if (rc) + goto error_rfkill; + + platform_set_drvdata(dev, rfk); + printk(KERN_INFO "mxc_bt_rfkill driver success loaded\n"); + return 0; + +error_rfkill: + rfkill_destroy(rfk); +error_rfk_alloc: +error_check_func: + return rc; +} + +static int __devexit mxc_bt_rfkill_remove(struct platform_device *dev) +{ + struct mxc_bt_rfkill_platform_data *data = dev->dev.platform_data; + struct rfkill *rfk = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + + if (rfk) { + rfkill_unregister(rfk); + rfkill_destroy(rfk); + } + + data->power_change(0); + + return 0; +} + +static struct platform_driver mxc_bt_rfkill_drv = { + .driver = { + .name = "mxc_bt_rfkill", + }, + + .probe = mxc_bt_rfkill_probe, + .remove = __devexit_p(mxc_bt_rfkill_remove), +}; + +static int __init mxc_bt_rfkill_init(void) +{ + return platform_driver_register(&mxc_bt_rfkill_drv); +} + +module_init(mxc_bt_rfkill_init); + +static void __exit mxc_bt_rfkill_exit(void) +{ + platform_driver_unregister(&mxc_bt_rfkill_drv); +} + +module_exit(mxc_bt_rfkill_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("RFKill control interface of BT on MX53 SMD"); diff --git a/arch/arm/mach-mx5/mx53_wp.c b/arch/arm/mach-mx5/mx53_wp.c new file mode 100644 index 000000000000..a09cb735c1d0 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_wp.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include "mx53_wp.h" + +/*! + * @file mach-mx5/mx53_wp.c + * + * @brief This file contains the information about MX53 CPU working points. + * + * @ingroup MSL_MX53 + */ +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +static int num_cpu_wp; +static struct cpu_wp *cpu_wp_table; + +/* working point for auto*/ +static struct cpu_wp cpu_wp_aec[] = { + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1050000,}, +}; + +/* working point for consumer 1G*/ +static struct cpu_wp cpu_wp_ces[] = { + { + .pll_rate = 1000000000, + .cpu_rate = 1000000000, + .pdf = 0, + .mfi = 10, + .mfd = 11, + .mfn = 5, + .cpu_podf = 0, + .cpu_voltage = 1200000,}, + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1050000,}, + { + .pll_rate = 800000000, + .cpu_rate = 400000000, + .cpu_podf = 1, + .cpu_voltage = 950000,}, + { + .pll_rate = 800000000, + .cpu_rate = 160000000, + .cpu_podf = 4, + .cpu_voltage = 900000,}, +}; + +/* working point for consumer 1.2G*/ +static struct cpu_wp cpu_wp_ces_1_2g[] = { + { + .pll_rate = 1200000000, + .cpu_rate = 1200000000, + .pdf = 0, + .mfi = 12, + .mfd = 1, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1300000,}, + { + .pll_rate = 1000000000, + .cpu_rate = 1000000000, + .pdf = 0, + .mfi = 10, + .mfd = 11, + .mfn = 5, + .cpu_podf = 0, + .cpu_voltage = 1200000,}, + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1050000,}, + { + .pll_rate = 800000000, + .cpu_rate = 400000000, + .cpu_podf = 1, + .cpu_voltage = 950000,}, + { + .pll_rate = 800000000, + .cpu_rate = 160000000, + .cpu_podf = 4, + .cpu_voltage = 900000,}, +}; + + +struct cpu_wp *mx53_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_table; +} + +void mx53_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +void mx53_set_cpu_part_number(enum mx53_cpu_part_number part_num) +{ + get_cpu_wp = mx53_get_cpu_wp; + set_num_cpu_wp = mx53_set_num_cpu_wp; + + switch (part_num) { + case IMX53_CEC_1_2G: + cpu_wp_table = cpu_wp_ces_1_2g; + num_cpu_wp = ARRAY_SIZE(cpu_wp_ces_1_2g); + break; + case IMX53_CEC: + cpu_wp_table = cpu_wp_ces; + num_cpu_wp = ARRAY_SIZE(cpu_wp_ces); + break; + case IMX53_AEC: + default: + cpu_wp_table = cpu_wp_aec; + num_cpu_wp = ARRAY_SIZE(cpu_wp_aec); + break; + } +} + + diff --git a/arch/arm/mach-mx5/mx53_wp.h b/arch/arm/mach-mx5/mx53_wp.h new file mode 100644 index 000000000000..353b5320a1b8 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_wp.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ARCH_ARM_MACH_MX53_WP_H__ +#define __ARCH_ARM_MACH_MX53_WP_H__ +#include + +/*! + * @file mach-mx5/mx53_wp.h + * + * @brief This file contains the information about MX53 CPU working points. + * + * @ingroup MSL_MX53 + */ +enum mx53_cpu_part_number { + IMX53_AEC, /* automative and infotainment AP */ + IMX53_CEC, /* Consumer AP, CPU freq is up to 1G */ + IMX53_CEC_1_2G, /* Consumer AP, CPU freq is up to 1.2GHZ */ +}; + +void mx53_set_cpu_part_number(enum mx53_cpu_part_number part_num); + +#endif /*__ARCH_ARM_MACH_MX53_WP_H__ */ + + + diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c new file mode 100644 index 000000000000..f07681be3748 --- /dev/null +++ b/arch/arm/mach-mx5/pm.c @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_ARCH_MX50 +#include +#endif + +#define MXC_SRPG_EMPGC0_SRPGCR (IO_ADDRESS(GPC_BASE_ADDR) + 0x2C0) +#define MXC_SRPG_EMPGC1_SRPGCR (IO_ADDRESS(GPC_BASE_ADDR) + 0x2D0) +#define DATABAHN_CTL_REG0 0 +#define DATABAHN_CTL_REG19 0x4c +#define DATABAHN_CTL_REG79 0x13c +#define DATABAHN_PHY_REG25 0x264 +#define MX53_OFFSET 0x20000000 + +static struct cpu_wp *cpu_wp_tbl; +static int cpu_wp_nr; +static struct clk *cpu_clk; +static struct mxc_pm_platform_data *pm_data; + +#if defined(CONFIG_CPU_FREQ) +static int org_freq; +extern int cpufreq_suspended; +extern int set_cpu_freq(int wp); +#endif + + +static struct device *pm_dev; +struct clk *gpc_dvfs_clk; +extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr); +extern void mx50_suspend(u32 databahn_addr); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void __iomem *databahn_base; +extern void da9053_suspend_cmd(void); +extern void pm_da9053_i2c_init(u32 base_addr); + +extern int iram_ready; +void *suspend_iram_base; +void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL; +void __iomem *suspend_param1; + +#define TZIC_WAKEUP0_OFFSET 0x0E00 +#define TZIC_WAKEUP1_OFFSET 0x0E04 +#define TZIC_WAKEUP2_OFFSET 0x0E08 +#define TZIC_WAKEUP3_OFFSET 0x0E0C +#define GPIO7_0_11_IRQ_BIT (0x1<<11) + +static void mx53_smd_loco_irq_wake_fixup(void) +{ + void __iomem *tzic_base; + tzic_base = ioremap(MX53_TZIC_BASE_ADDR, SZ_4K); + if (NULL == tzic_base) { + pr_err("fail to map MX53_TZIC_BASE_ADDR\n"); + return; + } + __raw_writel(0, tzic_base + TZIC_WAKEUP0_OFFSET); + __raw_writel(0, tzic_base + TZIC_WAKEUP1_OFFSET); + __raw_writel(0, tzic_base + TZIC_WAKEUP2_OFFSET); + /* only enable irq wakeup for da9053 */ + __raw_writel(GPIO7_0_11_IRQ_BIT, tzic_base + TZIC_WAKEUP3_OFFSET); + iounmap(tzic_base); + pr_debug("only da9053 irq is wakeup-enabled\n"); +} + +static int mx5_suspend_enter(suspend_state_t state) +{ + if (gpc_dvfs_clk == NULL) + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); + /* gpc clock is needed for SRPG */ + clk_enable(gpc_dvfs_clk); + switch (state) { + case PM_SUSPEND_MEM: + mxc_cpu_lp_set(STOP_POWER_OFF); + break; + case PM_SUSPEND_STANDBY: + mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + break; + default: + return -EINVAL; + } + + if (tzic_enable_wake(0) != 0) + return -EAGAIN; + + if (state == PM_SUSPEND_MEM) { + local_flush_tlb_all(); + flush_cache_all(); + + if (cpu_is_mx51() || cpu_is_mx53()) { + if (machine_is_mx53_smd() || + machine_is_mx53_loco()) { + mx53_smd_loco_irq_wake_fixup(); + da9053_suspend_cmd(); + } + /* Run the suspend code from iRAM. */ + suspend_in_iram(suspend_param1); + + /*clear the EMPGC0/1 bits */ + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + } else { + if (machine_is_mx50_rdp() && pm_data->suspend_enter) + pm_data->suspend_enter(); + /* Suspend now. */ + suspend_in_iram(databahn_base); + if (machine_is_mx50_rdp() && pm_data->suspend_exit) + pm_data->suspend_exit(); + } + } else { + cpu_do_idle(); + } + clk_disable(gpc_dvfs_clk); + + return 0; +} + + +/* + * Called after processes are frozen, but before we shut down devices. + */ +static int mx5_suspend_prepare(void) +{ +#if defined(CONFIG_CPU_FREQ) +#define MX53_SUSPEND_CPU_WP 400000000 + struct cpufreq_freqs freqs; + u32 suspend_wp = 0; + org_freq = clk_get_rate(cpu_clk); + /* workaround for mx53 to suspend on 400MHZ wp */ + if (cpu_is_mx53()) + for (suspend_wp = 0; suspend_wp < cpu_wp_nr; suspend_wp++) + if (cpu_wp_tbl[suspend_wp].cpu_rate + == MX53_SUSPEND_CPU_WP) + break; + if (suspend_wp == cpu_wp_nr) + suspend_wp = 0; + pr_info("suspend wp cpu=%d\n", cpu_wp_tbl[suspend_wp].cpu_rate); + freqs.old = org_freq / 1000; + freqs.new = cpu_wp_tbl[suspend_wp].cpu_rate / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + cpufreq_suspended = 1; + if (clk_get_rate(cpu_clk) != cpu_wp_tbl[suspend_wp].cpu_rate) { + set_cpu_freq(cpu_wp_tbl[suspend_wp].cpu_rate); + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } +#endif + return 0; +} + +/* + * Called before devices are re-setup. + */ +static void mx5_suspend_finish(void) +{ +#if defined(CONFIG_CPU_FREQ) + struct cpufreq_freqs freqs; + + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = org_freq / 1000; + freqs.cpu = 0; + freqs.flags = 0; + + cpufreq_suspended = 0; + + if (org_freq != clk_get_rate(cpu_clk)) { + set_cpu_freq(org_freq); + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } +#endif +} + +/* + * Called after devices are re-setup, but before processes are thawed. + */ +static void mx5_suspend_end(void) +{ +} + +static int mx5_pm_valid(suspend_state_t state) +{ + return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); +} + +struct platform_suspend_ops mx5_suspend_ops = { + .valid = mx5_pm_valid, + .prepare = mx5_suspend_prepare, + .enter = mx5_suspend_enter, + .finish = mx5_suspend_finish, + .end = mx5_suspend_end, +}; + +static int __devinit mx5_pm_probe(struct platform_device *pdev) +{ + pm_dev = &pdev->dev; + pm_data = pdev->dev.platform_data; + + return 0; +} + +static struct platform_driver mx5_pm_driver = { + .driver = { + .name = "mx5_pm", + }, + .probe = mx5_pm_probe, +}; + +static int __init pm_init(void) +{ + unsigned long iram_paddr; + + pr_info("Static Power Management for Freescale i.MX5\n"); + if (platform_driver_register(&mx5_pm_driver) != 0) { + printk(KERN_ERR "mx5_pm_driver register failed\n"); + return -ENODEV; + } + suspend_set_ops(&mx5_suspend_ops); + /* Move suspend routine into iRAM */ + iram_alloc(SZ_4K, &iram_paddr); + /* Need to remap the area here since we want the memory region + to be executable. */ + suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K, + MT_HIGH_VECTORS); + + if (cpu_is_mx51() || cpu_is_mx53()) { + suspend_param1 = IO_ADDRESS(IOMUXC_BASE_ADDR + 0x4b8); + memcpy(suspend_iram_base, cpu_do_suspend_workaround, + SZ_4K); + } else if (cpu_is_mx50()) { + /* + * Need to run the suspend code from IRAM as the DDR needs + * to be put into self refresh mode manually. + */ + memcpy(suspend_iram_base, mx50_suspend, SZ_4K); + + suspend_param1 = databahn_base; + } + suspend_in_iram = (void *)suspend_iram_base; + + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__); + return PTR_ERR(cpu_clk); + } + printk(KERN_INFO "PM driver module loaded\n"); + + if (machine_is_mx53_smd() || + machine_is_mx53_loco()) + pm_da9053_i2c_init(I2C1_BASE_ADDR - MX53_OFFSET); + + return 0; +} + + +static void __exit pm_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&mx5_pm_driver); +} + +module_init(pm_init); +module_exit(pm_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("PM driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mx5/pm_da9053.c b/arch/arm/mach-mx5/pm_da9053.c new file mode 100644 index 000000000000..6e24fb2823d4 --- /dev/null +++ b/arch/arm/mach-mx5/pm_da9053.c @@ -0,0 +1,385 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/** Defines ******************************************************************** +*******************************************************************************/ + + +/* IMX I2C registers */ +#define IMX_I2C_IADR 0x00 /* i2c slave address */ +#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ +#define IMX_I2C_I2CR 0x08 /* i2c control */ +#define IMX_I2C_I2SR 0x0C /* i2c status */ +#define IMX_I2C_I2DR 0x10 /* i2c transfer data */ + +/* Bits of IMX I2C registers */ +#define I2SR_RXAK 0x01 +#define I2SR_IIF 0x02 +#define I2SR_SRW 0x04 +#define I2SR_IAL 0x10 +#define I2SR_IBB 0x20 +#define I2SR_IAAS 0x40 +#define I2SR_ICF 0x80 +#define I2CR_RSTA 0x04 +#define I2CR_TXAK 0x08 +#define I2CR_MTX 0x10 +#define I2CR_MSTA 0x20 +#define I2CR_IIEN 0x40 +#define I2CR_IEN 0x80 + +static void __iomem *base; +static int stopped; + +/** Functions for IMX I2C adapter driver *************************************** +*******************************************************************************/ + +static int pm_i2c_imx_bus_busy(int for_busy) +{ + unsigned int temp; + + while (1) { + temp = readb(base + IMX_I2C_I2SR); + if (for_busy && (temp & I2SR_IBB)) + break; + if (!for_busy && !(temp & I2SR_IBB)) + break; + pr_debug("waiting bus busy=%d\n", for_busy); + } + + return 0; +} + +static int pm_i2c_imx_trx_complete(void) +{ + unsigned int temp; + while (!((temp = readb(base + IMX_I2C_I2SR)) & I2SR_IIF)) + pr_debug("waiting or I2SR_IIF\n"); + temp &= ~I2SR_IIF; + writeb(temp, base + IMX_I2C_I2SR); + + return 0; +} + +static int pm_i2c_imx_acked(void) +{ + if (readb(base + IMX_I2C_I2SR) & I2SR_RXAK) { + pr_info("<%s> No ACK\n", __func__); + return -EIO; /* No ACK */ + } + return 0; +} + +static int pm_i2c_imx_start(void) +{ + unsigned int temp = 0; + int result; + + /* Enable I2C controller */ + writeb(0, base + IMX_I2C_I2SR); + writeb(I2CR_IEN, base + IMX_I2C_I2CR); + + /* Wait controller to be stable */ + udelay(50); + + /* Start I2C transaction */ + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_MSTA; + writeb(temp, base + IMX_I2C_I2CR); + result = pm_i2c_imx_bus_busy(1); + + temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + return result; +} + +static void pm_i2c_imx_stop(void) +{ + unsigned int temp = 0; + + /* Stop I2C transaction */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~(I2CR_MSTA | I2CR_MTX); + writeb(temp, base + IMX_I2C_I2CR); + + pm_i2c_imx_bus_busy(0); + + /* Disable I2C controller */ + writeb(0, base + IMX_I2C_I2CR); +} + +static int pm_i2c_imx_write(struct i2c_msg *msgs) +{ + int i, result; + + /* write slave address */ + writeb(msgs->addr << 1, base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + + /* write data */ + for (i = 0; i < msgs->len; i++) { + writeb(msgs->buf[i], base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + } + return 0; +} + +static int pm_i2c_imx_read(struct i2c_msg *msgs) +{ + int i, result; + unsigned int temp; + + /* write slave address */ + writeb((msgs->addr << 1) | 0x01, base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + + /* setup bus to read data */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~I2CR_MTX; + if (msgs->len - 1) + temp &= ~I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + readb(base + IMX_I2C_I2DR); /* dummy read */ + + /* read data */ + for (i = 0; i < msgs->len; i++) { + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + if (i == (msgs->len - 1)) { + /* It must generate STOP before read I2DR to prevent + controller from generating another clock cycle */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~(I2CR_MSTA | I2CR_MTX); + writeb(temp, base + IMX_I2C_I2CR); + pm_i2c_imx_bus_busy(0); + stopped = 1; + } else if (i == (msgs->len - 2)) { + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + } + msgs->buf[i] = readb(base + IMX_I2C_I2DR); + } + return 0; +} + +int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num) +{ + unsigned int i, temp; + int result; + + /* Start I2C transfer */ + result = pm_i2c_imx_start(); + if (result) + goto fail0; + + /* read/write data */ + for (i = 0; i < num; i++) { + if (i) { + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_RSTA; + writeb(temp, base + IMX_I2C_I2CR); + result = pm_i2c_imx_bus_busy(1); + if (result) + goto fail0; + } + /* write/read data */ + if (msgs[i].flags & I2C_M_RD) + result = pm_i2c_imx_read(&msgs[i]); + else + result = pm_i2c_imx_write(&msgs[i]); + if (result) + goto fail0; + } + +fail0: + /* Stop I2C transfer */ + pm_i2c_imx_stop(); + + return (result < 0) ? result : num; +} + +void pm_da9053_i2c_init(u32 base_addr) +{ + base = ioremap(base_addr, SZ_4K); +} + +void pm_da9053_i2c_deinit(void) +{ + iounmap(base); +} + +void pm_da9053_read_reg(u8 reg, u8 *value) +{ + unsigned char buf[2] = {0, 0}; + struct i2c_msg i2cmsg[2]; + buf[0] = reg; + i2cmsg[0].addr = 0x48 ; + i2cmsg[0].len = 1; + i2cmsg[0].buf = &buf[0]; + + i2cmsg[0].flags = 0; + + i2cmsg[1].addr = 0x48 ; + i2cmsg[1].len = 1; + i2cmsg[1].buf = &buf[1]; + + i2cmsg[1].flags = I2C_M_RD; + + pm_i2c_imx_xfer(i2cmsg, 2); + *value = buf[1]; +} + +void pm_da9053_write_reg(u8 reg, u8 value) +{ + unsigned char buf[2] = {0, 0}; + struct i2c_msg i2cmsg[2]; + buf[0] = reg; + buf[1] = value; + i2cmsg[0].addr = 0x48 ; + i2cmsg[0].len = 2; + i2cmsg[0].buf = &buf[0]; + i2cmsg[0].flags = 0; + pm_i2c_imx_xfer(i2cmsg, 1); +} + +/* have to hard-code the preset voltage here for they share the register +as the normal setting on Da9053 */ +/* preset buck core to 850 mv */ +#define BUCKCORE_SUSPEND_PRESET 0xCE +/* preset buck core to 950 mv */ +#define BUCKPRO_SUSPEND_PRESET 0xD2 +/* preset ldo6 to 1200 mv */ +#define LDO6_SUSPEND_PRESET 0xC0 +/* preset ldo10 to 1200 mv */ +#define iLDO10_SUSPEND_PRESET 0xC0 +#define CONF_BIT 0x80 + +static u8 volt_settings[DA9052_LDO10_REG - DA9052_BUCKCORE_REG + 1]; +static void pm_da9053_preset_voltage(void) +{ + u8 reg, data; + for (reg = DA9052_BUCKCORE_REG; + reg <= DA9052_LDO10_REG; reg++) { + pm_da9053_read_reg(reg, &data); + volt_settings[reg - DA9052_BUCKCORE_REG] = data; + data |= CONF_BIT; + pm_da9053_write_reg(reg, data); + } + pm_da9053_write_reg(DA9052_BUCKCORE_REG, BUCKCORE_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_BUCKPRO_REG, BUCKPRO_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_LDO6_REG, LDO6_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_LDO10_REG, iLDO10_SUSPEND_PRESET); +} + +#define DA9053_SLEEP_DELAY 0x1f +int da9053_suspend_cmd(void) +{ + unsigned char buf[2] = {0, 0}; + struct clk *i2c_clk; + u8 data; + buf[0] = 29; + + i2c_clk = clk_get(NULL, "i2c_clk"); + if (IS_ERR(i2c_clk)) { + pr_err("unable to get i2c clk\n"); + return PTR_ERR(i2c_clk); + } + clk_enable(i2c_clk); + + pm_da9053_preset_voltage(); + + pm_da9053_read_reg(DA9052_ID01_REG, &data); + data &= ~(DA9052_ID01_DEFSUPPLY | DA9052_ID01_nRESMODE); + pm_da9053_write_reg(DA9052_ID01_REG, data); + + pm_da9053_write_reg(DA9052_SEQB_REG, DA9053_SLEEP_DELAY); + + pm_da9053_read_reg(DA9052_CONTROLB_REG, &data); + data |= DA9052_CONTROLB_DEEPSLEEP; + pm_da9053_write_reg(DA9052_CONTROLB_REG, data); + + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +} + +void da9053_restore_volt_settings(void) +{ + u8 reg; + for (reg = DA9052_BUCKCORE_REG; + reg <= DA9052_LDO10_REG; reg++) + pm_da9053_write_reg(reg, + volt_settings[reg - DA9052_BUCKCORE_REG]); +} + +int da9053_poweroff_cmd(void) +{ + unsigned char buf[2] = {0, 0}; + struct clk *i2c_clk; + u8 data; + buf[0] = 29; + + i2c_clk = clk_get(NULL, "i2c_clk"); + if (IS_ERR(i2c_clk)) { + pr_err("unable to get i2c clk\n"); + return PTR_ERR(i2c_clk); + } + clk_enable(i2c_clk); + + pm_da9053_read_reg(DA9052_CONTROLB_REG, &data); + data |= DA9052_CONTROLB_SHUTDOWN; + pm_da9053_write_reg(DA9052_CONTROLB_REG, data); + + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +} + diff --git a/arch/arm/mach-mx5/regs-apbh.h b/arch/arm/mach-mx5/regs-apbh.h new file mode 100644 index 000000000000..23b9f4baa404 --- /dev/null +++ b/arch/arm/mach-mx5/regs-apbh.h @@ -0,0 +1,512 @@ +/* + * Freescale APBH Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.3 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H + + +#define HW_APBH_CTRL0 (0x00000000) +#define HW_APBH_CTRL0_SET (0x00000004) +#define HW_APBH_CTRL0_CLR (0x00000008) +#define HW_APBH_CTRL0_TOG (0x0000000c) + +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST_EN 0x10000000 +#define BP_APBH_CTRL0_RSVD0 16 +#define BM_APBH_CTRL0_RSVD0 0x0FFF0000 +#define BF_APBH_CTRL0_RSVD0(v) \ + (((v) << 16) & BM_APBH_CTRL0_RSVD0) +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 0 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FFFF +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0001 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0002 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0004 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0008 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0010 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0020 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0040 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0080 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP 0x0100 + +#define HW_APBH_CTRL1 (0x00000010) +#define HW_APBH_CTRL1_SET (0x00000014) +#define HW_APBH_CTRL1_CLR (0x00000018) +#define HW_APBH_CTRL1_TOG (0x0000001c) + +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBH_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBH_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBH_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBH_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBH_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBH_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBH_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBH_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBH_CTRL2 (0x00000020) +#define HW_APBH_CTRL2_SET (0x00000024) +#define HW_APBH_CTRL2_CLR (0x00000028) +#define HW_APBH_CTRL2_TOG (0x0000002c) + +#define BM_APBH_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBH_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBH_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBH_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBH_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBH_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBH_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBH_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBH_CHANNEL_CTRL (0x00000030) +#define HW_APBH_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBH_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBH_CHANNEL_CTRL_TOG (0x0000003c) + +#define BP_APBH_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0001 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0002 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0004 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0008 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0010 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0020 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0040 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0080 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP 0x0100 +#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0001 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0002 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0004 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0008 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0010 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0020 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0040 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0080 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP 0x0100 + +#define HW_APBH_DEVSEL (0x00000040) + +#define BP_APBH_DEVSEL_CH15 30 +#define BM_APBH_DEVSEL_CH15 0xC0000000 +#define BF_APBH_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBH_DEVSEL_CH15) +#define BP_APBH_DEVSEL_CH14 28 +#define BM_APBH_DEVSEL_CH14 0x30000000 +#define BF_APBH_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBH_DEVSEL_CH14) +#define BP_APBH_DEVSEL_CH13 26 +#define BM_APBH_DEVSEL_CH13 0x0C000000 +#define BF_APBH_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBH_DEVSEL_CH13) +#define BP_APBH_DEVSEL_CH12 24 +#define BM_APBH_DEVSEL_CH12 0x03000000 +#define BF_APBH_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBH_DEVSEL_CH12) +#define BP_APBH_DEVSEL_CH11 22 +#define BM_APBH_DEVSEL_CH11 0x00C00000 +#define BF_APBH_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBH_DEVSEL_CH11) +#define BP_APBH_DEVSEL_CH10 20 +#define BM_APBH_DEVSEL_CH10 0x00300000 +#define BF_APBH_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBH_DEVSEL_CH10) +#define BP_APBH_DEVSEL_CH9 18 +#define BM_APBH_DEVSEL_CH9 0x000C0000 +#define BF_APBH_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBH_DEVSEL_CH9) +#define BP_APBH_DEVSEL_CH8 16 +#define BM_APBH_DEVSEL_CH8 0x00030000 +#define BF_APBH_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBH_DEVSEL_CH8) +#define BP_APBH_DEVSEL_CH7 14 +#define BM_APBH_DEVSEL_CH7 0x0000C000 +#define BF_APBH_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBH_DEVSEL_CH7) +#define BP_APBH_DEVSEL_CH6 12 +#define BM_APBH_DEVSEL_CH6 0x00003000 +#define BF_APBH_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBH_DEVSEL_CH6) +#define BP_APBH_DEVSEL_CH5 10 +#define BM_APBH_DEVSEL_CH5 0x00000C00 +#define BF_APBH_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBH_DEVSEL_CH5) +#define BP_APBH_DEVSEL_CH4 8 +#define BM_APBH_DEVSEL_CH4 0x00000300 +#define BF_APBH_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBH_DEVSEL_CH4) +#define BP_APBH_DEVSEL_CH3 6 +#define BM_APBH_DEVSEL_CH3 0x000000C0 +#define BF_APBH_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBH_DEVSEL_CH3) +#define BP_APBH_DEVSEL_CH2 4 +#define BM_APBH_DEVSEL_CH2 0x00000030 +#define BF_APBH_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBH_DEVSEL_CH2) +#define BP_APBH_DEVSEL_CH1 2 +#define BM_APBH_DEVSEL_CH1 0x0000000C +#define BF_APBH_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBH_DEVSEL_CH1) +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x00000003 +#define BF_APBH_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBH_DEVSEL_CH0) + +#define HW_APBH_DMA_BURST_SIZE (0x00000050) + +#define BP_APBH_DMA_BURST_SIZE_CH15 30 +#define BM_APBH_DMA_BURST_SIZE_CH15 0xC0000000 +#define BF_APBH_DMA_BURST_SIZE_CH15(v) \ + (((v) << 30) & BM_APBH_DMA_BURST_SIZE_CH15) +#define BP_APBH_DMA_BURST_SIZE_CH14 28 +#define BM_APBH_DMA_BURST_SIZE_CH14 0x30000000 +#define BF_APBH_DMA_BURST_SIZE_CH14(v) \ + (((v) << 28) & BM_APBH_DMA_BURST_SIZE_CH14) +#define BP_APBH_DMA_BURST_SIZE_CH13 26 +#define BM_APBH_DMA_BURST_SIZE_CH13 0x0C000000 +#define BF_APBH_DMA_BURST_SIZE_CH13(v) \ + (((v) << 26) & BM_APBH_DMA_BURST_SIZE_CH13) +#define BP_APBH_DMA_BURST_SIZE_CH12 24 +#define BM_APBH_DMA_BURST_SIZE_CH12 0x03000000 +#define BF_APBH_DMA_BURST_SIZE_CH12(v) \ + (((v) << 24) & BM_APBH_DMA_BURST_SIZE_CH12) +#define BP_APBH_DMA_BURST_SIZE_CH11 22 +#define BM_APBH_DMA_BURST_SIZE_CH11 0x00C00000 +#define BF_APBH_DMA_BURST_SIZE_CH11(v) \ + (((v) << 22) & BM_APBH_DMA_BURST_SIZE_CH11) +#define BP_APBH_DMA_BURST_SIZE_CH10 20 +#define BM_APBH_DMA_BURST_SIZE_CH10 0x00300000 +#define BF_APBH_DMA_BURST_SIZE_CH10(v) \ + (((v) << 20) & BM_APBH_DMA_BURST_SIZE_CH10) +#define BP_APBH_DMA_BURST_SIZE_CH9 18 +#define BM_APBH_DMA_BURST_SIZE_CH9 0x000C0000 +#define BF_APBH_DMA_BURST_SIZE_CH9(v) \ + (((v) << 18) & BM_APBH_DMA_BURST_SIZE_CH9) +#define BP_APBH_DMA_BURST_SIZE_CH8 16 +#define BM_APBH_DMA_BURST_SIZE_CH8 0x00030000 +#define BF_APBH_DMA_BURST_SIZE_CH8(v) \ + (((v) << 16) & BM_APBH_DMA_BURST_SIZE_CH8) +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH8__BURST8 0x2 +#define BP_APBH_DMA_BURST_SIZE_CH7 14 +#define BM_APBH_DMA_BURST_SIZE_CH7 0x0000C000 +#define BF_APBH_DMA_BURST_SIZE_CH7(v) \ + (((v) << 14) & BM_APBH_DMA_BURST_SIZE_CH7) +#define BP_APBH_DMA_BURST_SIZE_CH6 12 +#define BM_APBH_DMA_BURST_SIZE_CH6 0x00003000 +#define BF_APBH_DMA_BURST_SIZE_CH6(v) \ + (((v) << 12) & BM_APBH_DMA_BURST_SIZE_CH6) +#define BP_APBH_DMA_BURST_SIZE_CH5 10 +#define BM_APBH_DMA_BURST_SIZE_CH5 0x00000C00 +#define BF_APBH_DMA_BURST_SIZE_CH5(v) \ + (((v) << 10) & BM_APBH_DMA_BURST_SIZE_CH5) +#define BP_APBH_DMA_BURST_SIZE_CH4 8 +#define BM_APBH_DMA_BURST_SIZE_CH4 0x00000300 +#define BF_APBH_DMA_BURST_SIZE_CH4(v) \ + (((v) << 8) & BM_APBH_DMA_BURST_SIZE_CH4) +#define BP_APBH_DMA_BURST_SIZE_CH3 6 +#define BM_APBH_DMA_BURST_SIZE_CH3 0x000000C0 +#define BF_APBH_DMA_BURST_SIZE_CH3(v) \ + (((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3) +#define BP_APBH_DMA_BURST_SIZE_CH2 4 +#define BM_APBH_DMA_BURST_SIZE_CH2 0x00000030 +#define BF_APBH_DMA_BURST_SIZE_CH2(v) \ + (((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2) +#define BP_APBH_DMA_BURST_SIZE_CH1 2 +#define BM_APBH_DMA_BURST_SIZE_CH1 0x0000000C +#define BF_APBH_DMA_BURST_SIZE_CH1(v) \ + (((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1) +#define BP_APBH_DMA_BURST_SIZE_CH0 0 +#define BM_APBH_DMA_BURST_SIZE_CH0 0x00000003 +#define BF_APBH_DMA_BURST_SIZE_CH0(v) \ + (((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0) + +#define HW_APBH_DEBUG (0x00000060) + +#define BP_APBH_DEBUG_RSVD 1 +#define BM_APBH_DEBUG_RSVD 0xFFFFFFFE +#define BF_APBH_DEBUG_RSVD(v) \ + (((v) << 1) & BM_APBH_DEBUG_RSVD) +#define BM_APBH_DEBUG_GPMI_ONE_FIFO 0x00000001 + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBH_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 + +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBH_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_READY 0x1F + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBH_VERSION (0x00000800) + +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 +#define BF_APBH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBH_VERSION_MAJOR) +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 +#define BF_APBH_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBH_VERSION_MINOR) +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF +#define BF_APBH_VERSION_STEP(v) \ + (((v) << 0) & BM_APBH_VERSION_STEP) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/mach-mx5/sdma_script_code_mx50.h b/arch/arm/mach-mx5/sdma_script_code_mx50.h new file mode 100644 index 000000000000..49a79213c54b --- /dev/null +++ b/arch/arm/mach-mx5/sdma_script_code_mx50.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SDMA_CODEX.01.00.00" + +*******************************************************************************/ + +#ifndef SDMA_SCRIPT_CODE_MX50_H +#define SDMA_SCRIPT_CODE_MX50_H + + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR_MX50 0 +#define start_SIZE_MX50 18 + +#define core_ADDR_MX50 80 +#define core_SIZE_MX50 232 + +#define common_ADDR_MX50 312 +#define common_SIZE_MX50 330 + +#define ap_2_ap_ADDR_MX50 642 +#define ap_2_ap_SIZE_MX50 41 + +#define app_2_mcu_ADDR_MX50 683 +#define app_2_mcu_SIZE_MX50 64 + +#define mcu_2_app_ADDR_MX50 747 +#define mcu_2_app_SIZE_MX50 70 + +#define uart_2_mcu_ADDR_MX50 817 +#define uart_2_mcu_SIZE_MX50 74 + +#define shp_2_mcu_ADDR_MX50 891 +#define shp_2_mcu_SIZE_MX50 69 + +#define mcu_2_shp_ADDR_MX50 960 +#define mcu_2_shp_SIZE_MX50 72 + +#define uartsh_2_mcu_ADDR_MX50 1032 +#define uartsh_2_mcu_SIZE_MX50 68 + +#define loop_DMAs_routines_ADDR_MX50 1100 +#define loop_DMAs_routines_SIZE_MX50 227 + +#define test_ADDR_MX50 1327 +#define test_SIZE_MX50 63 + +#define signature_ADDR_MX50 1023 +#define signature_SIZE_MX50 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define mcu_2_ssiapp_ADDR_MX50 6144 +#define mcu_2_ssiapp_SIZE_MX50 96 + +#define mcu_2_ssish_ADDR_MX50 6240 +#define mcu_2_ssish_SIZE_MX50 95 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR_MX50 6144 +#define RAM_CODE_SIZE_MX50 191 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +static const short sdma_code_mx50[] = { +0xc1e3, 0x57db, 0x52f3, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d, +0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, 0x7d2c, 0x7c36, 0x0479, +0x7c1f, 0x56ee, 0x0f00, 0x0660, 0x7d05, 0x6509, 0x7e43, 0x620a, +0x7e41, 0x981e, 0x620a, 0x7e3e, 0x6509, 0x7e3c, 0x0512, 0x0512, +0x02ad, 0x0760, 0x7d03, 0x55fb, 0x6dd3, 0x9829, 0x55fb, 0x1d04, +0x6dd3, 0x6ac8, 0x7f2f, 0x1f01, 0x2003, 0x4800, 0x7ce4, 0x9851, +0x55fb, 0x6dd7, 0x0015, 0x7805, 0x6209, 0x6ac8, 0x6209, 0x6ac8, +0x6dd7, 0x9850, 0x55fb, 0x6dd7, 0x0015, 0x0015, 0x7805, 0x620a, +0x6ac8, 0x620a, 0x6ac8, 0x6dd7, 0x9850, 0x55fb, 0x6dd7, 0x0015, +0x0015, 0x0015, 0x7805, 0x620b, 0x6ac8, 0x620b, 0x6ac8, 0x6dd7, +0x7c09, 0x6ddf, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d07, 0xc1fa, +0x57db, 0x9804, 0x0007, 0x68cc, 0x680c, 0xc213, 0xc20a, 0x9801, +0xc1d9, 0xc1e3, 0x57db, 0x52f3, 0x6a21, 0x008f, 0x00d5, 0x7d01, +0x008d, 0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d03, 0x0479, 0x7d32, +0x7c39, 0x0479, 0x7c28, 0x0b70, 0x0311, 0x53eb, 0x0f00, 0x0360, +0x7d05, 0x6509, 0x7e3f, 0x620a, 0x7e3d, 0x9882, 0x620a, 0x7e3a, +0x6509, 0x7e38, 0x0512, 0x0512, 0x02ad, 0x0760, 0x7d0a, 0x5a06, +0x7f31, 0x1f01, 0x2003, 0x4800, 0x7cea, 0x0b70, 0x0311, 0x5313, +0x98b3, 0x5a26, 0x7f27, 0x1f01, 0x2003, 0x4800, 0x7ce0, 0x0b70, +0x0311, 0x5313, 0x98b3, 0x0015, 0x7804, 0x6209, 0x5a06, 0x6209, +0x5a26, 0x98b2, 0x0015, 0x0015, 0x7804, 0x620a, 0x5a06, 0x620a, +0x5a26, 0x98b2, 0x0015, 0x0015, 0x0015, 0x7804, 0x620b, 0x5a06, +0x620b, 0x5a26, 0x7c07, 0x0000, 0x55eb, 0x4d00, 0x7d06, 0xc1fa, +0x57db, 0x9865, 0x0007, 0x680c, 0xc213, 0xc20a, 0x9862 +}; +#endif diff --git a/arch/arm/mach-mx5/sdma_script_code_mx51.h b/arch/arm/mach-mx5/sdma_script_code_mx51.h new file mode 100644 index 000000000000..9a396c92ebea --- /dev/null +++ b/arch/arm/mach-mx5/sdma_script_code_mx51.h @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/******************************************************************************* + + SDMA RELEASE LABEL: "SS15_ELVIS V1.1" + +*******************************************************************************/ + +#ifndef __SDMA_SCRIPT_CODE_H__ +#define __SDMA_SCRIPT_CODE_H__ + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR_MX51 0 +#define start_SIZE_MX51 24 + +#define core_ADDR_MX51 80 +#define core_SIZE_MX51 232 + +#define common_ADDR_MX51 312 +#define common_SIZE_MX51 330 + +#define ap_2_ap_ADDR_MX51 642 +#define ap_2_ap_SIZE_MX51 41 + +#define app_2_mcu_ADDR_MX51 683 +#define app_2_mcu_SIZE_MX51 64 + +#define mcu_2_app_ADDR_MX51 747 +#define mcu_2_app_SIZE_MX51 70 + +#define uart_2_mcu_ADDR_MX51 817 +#define uart_2_mcu_SIZE_MX51 75 + +#define shp_2_mcu_ADDR_MX51 892 +#define shp_2_mcu_SIZE_MX51 69 + +#define mcu_2_shp_ADDR_MX51 961 +#define mcu_2_shp_SIZE_MX51 72 + +#define app_2_per_ADDR_MX51 1033 +#define app_2_per_SIZE_MX51 66 + +#define per_2_app_ADDR_MX51 1099 +#define per_2_app_SIZE_MX51 74 + +#define per_2_shp_ADDR_MX51 1173 +#define per_2_shp_SIZE_MX51 78 + +#define shp_2_per_ADDR_MX51 1251 +#define shp_2_per_SIZE_MX51 72 + +#define uartsh_2_mcu_ADDR_MX51 1323 +#define uartsh_2_mcu_SIZE_MX51 69 + +#define mcu_2_ata_ADDR_MX51 1392 +#define mcu_2_ata_SIZE_MX51 81 + +#define ata_2_mcu_ADDR_MX51 1473 +#define ata_2_mcu_SIZE_MX51 96 + +#define loop_DMAs_routines_ADDR_MX51 1569 +#define loop_DMAs_routines_SIZE_MX51 227 + +#define test_ADDR_MX51 1796 +#define test_SIZE_MX51 63 + +#define signature_ADDR_MX51 1023 +#define signature_SIZE_MX51 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define ext_mem__ipu_ram_ADDR_MX51 6144 +#define ext_mem__ipu_ram_SIZE_MX51 123 + +#define firi_2_mcu_ADDR_MX51 6267 +#define firi_2_mcu_SIZE_MX51 97 + +#define mcu_2_firi_ADDR_MX51 6364 +#define mcu_2_firi_SIZE_MX51 79 + +#define mcu_2_spdif_ADDR_MX51 6443 +#define mcu_2_spdif_SIZE_MX51 59 + +#define mcu_2_ssiapp_ADDR_MX51 6502 +#define mcu_2_ssiapp_SIZE_MX51 98 + +#define mcu_2_ssish_ADDR_MX51 6600 +#define mcu_2_ssish_SIZE_MX51 89 + +#define ssiapp_2_mcu_ADDR_MX51 6689 +#define ssiapp_2_mcu_SIZE_MX51 94 + +#define ssish_2_mcu_ADDR_MX51 6783 +#define ssish_2_mcu_SIZE_MX51 84 + +#define uart_2_per_ADDR_MX51 6867 +#define uart_2_per_SIZE_MX51 73 + +#define uartsh_2_per_ADDR_MX51 6940 +#define uartsh_2_per_SIZE_MX51 67 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR_MX51 6144 +#define RAM_CODE_SIZE_MX51 863 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short sdma_code_mx51[] = { +0x0e70, 0x0611, 0x5616, 0xc13c, 0x7d2a, 0x5ade, 0x008e, 0xc14e, +0x7c26, 0x5be0, 0x5ef0, 0x5ce8, 0x0688, 0x08ff, 0x0011, 0x28ff, +0x00bc, 0x53f6, 0x05df, 0x7d0b, 0x6dc5, 0x03df, 0x7d03, 0x6bd5, +0xd84f, 0x982b, 0x6b05, 0xc681, 0x7e27, 0x7f29, 0x982b, 0x6d01, +0x03df, 0x7d05, 0x6bd5, 0xc6ab, 0x7e18, 0x7f1a, 0x982b, 0x6b05, +0xc621, 0x7e07, 0x7f06, 0x52de, 0x53e6, 0xc159, 0x7dd7, 0x0200, +0x9803, 0x0007, 0x6004, 0x680c, 0x53f6, 0x028e, 0x00a3, 0xc256, +0x048b, 0x0498, 0x0454, 0x068a, 0x982b, 0x0207, 0x680c, 0x6ddf, +0x0107, 0x68ff, 0x60d0, 0x9834, 0x0207, 0x68ff, 0x6d28, 0x0107, +0x6004, 0x680c, 0x9834, 0x0007, 0x68ff, 0x60d0, 0x9834, 0x0288, +0x03a5, 0x3b03, 0x3d03, 0x4d00, 0x7d0a, 0x0804, 0x00a5, 0x00da, +0x7d1a, 0x02a0, 0x7b01, 0x65d8, 0x7eee, 0x65ff, 0x7eec, 0x0804, +0x02d0, 0x7d11, 0x4b00, 0x7c0f, 0x008a, 0x3003, 0x6dcf, 0x6bdf, +0x0015, 0x0015, 0x7b02, 0x65d8, 0x0000, 0x7edd, 0x63ff, 0x7edb, +0x3a03, 0x6dcd, 0x6bdd, 0x008a, 0x7b02, 0x65d8, 0x0000, 0x7ed3, +0x65ff, 0x7ed1, 0x0006, 0x2618, 0x1e10, 0x0b70, 0x0311, 0x5313, +0x58d3, 0x008b, 0x5efb, 0xc13c, 0x7d55, 0x5ac0, 0x5bc8, 0xc14e, +0x7c51, 0x0388, 0x6d04, 0x0dff, 0x0511, 0x1dff, 0x05bc, 0x56fb, +0x6ec3, 0x62c8, 0x7e38, 0x0264, 0x7d0b, 0x0212, 0x3aff, 0x02df, +0x7c05, 0x008f, 0x05a0, 0x0015, 0x0015, 0xd8b5, 0x0400, 0x988f, +0x56fb, 0x6ec3, 0x62c8, 0x0212, 0x3aff, 0x008a, 0x4800, 0x7d02, +0x05a0, 0xd8c0, 0x6a28, 0x7f24, 0x008b, 0x52c0, 0x53c8, 0x04a5, +0xc159, 0x7dd4, 0x0401, 0x0200, 0x9886, 0x1e08, 0x6ec3, 0x7802, +0x62c8, 0x6a0b, 0x7e10, 0x6a28, 0x7f13, 0x0000, 0x2608, 0x0006, +0x1e08, 0x6ec1, 0x7802, 0x62c8, 0x6a09, 0x7e05, 0x6a28, 0x7f08, +0x0000, 0x2608, 0x0006, 0x0007, 0x68cc, 0x6a28, 0x7f01, 0x98d9, +0x0007, 0x6a0c, 0x6a0c, 0x6204, 0x6a04, 0x6a2b, 0x6a28, 0x0007, +0x680c, 0x0454, 0x0200, 0x9883, 0x0b70, 0x0311, 0x5313, 0x58d3, +0x008b, 0x5efb, 0xc13c, 0x7d45, 0x5ac0, 0x5bc8, 0xc14e, 0x56f8, +0x7c40, 0x6ed1, 0x0388, 0x6d00, 0x0dff, 0x0511, 0x1dff, 0x05bc, +0x4d00, 0x7d2f, 0x0e70, 0x0611, 0x522e, 0x02b9, 0x4a00, 0x7c09, +0x52fe, 0x50d3, 0x02b8, 0x4a00, 0x7c04, 0x62ff, 0x7e1c, 0x0400, +0x98f2, 0x008f, 0x00d5, 0x7d0b, 0x008d, 0x05a0, 0x56fb, 0x6ed1, +0x7802, 0x6209, 0x6ac8, 0x0000, 0x7e11, 0x7f0d, 0x98f0, 0x05a0, +0x0015, 0x0015, 0x56fb, 0x6ed3, 0x7802, 0x620b, 0x6ac8, 0x0000, +0x7e05, 0x7f01, 0x98f0, 0x0007, 0x68cc, 0x9920, 0x0007, 0x6a0c, +0x0454, 0x62ff, 0x7efb, 0x008b, 0x52c0, 0x53c8, 0xc159, 0x7dbd, +0x0401, 0x0200, 0x98e2, 0xc1d9, 0xc1e3, 0x57db, 0x52f3, 0x6a01, +0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x56fb, 0x0478, +0x7d28, 0x0479, 0x7c16, 0x0015, 0x0015, 0x0388, 0x620a, 0x0808, +0x7801, 0x0217, 0x5a06, 0x7f1d, 0x620a, 0x0808, 0x7801, 0x0217, +0x5a26, 0x7f17, 0x2301, 0x4b00, 0x7cf1, 0x0b70, 0x0311, 0x5313, +0x995a, 0x0015, 0x0015, 0x0015, 0x7804, 0x620b, 0x5a06, 0x620b, +0x5a26, 0x7c07, 0x0000, 0x55eb, 0x4d00, 0x7d06, 0xc1fa, 0x57db, +0x9930, 0x0007, 0x680c, 0xc213, 0xc20a, 0x992d, 0xc1e3, 0x57db, +0x5fe3, 0x57e3, 0x52f3, 0x6a01, 0x008f, 0x00d5, 0x7d01, 0x008d, +0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, 0x7d2c, 0x7c36, 0x0479, +0x7c1f, 0x56ee, 0x0f00, 0x0660, 0x7d05, 0x6509, 0x7e43, 0x620a, +0x7e41, 0x9986, 0x620a, 0x7e3e, 0x6509, 0x7e3c, 0x0512, 0x0512, +0x02ad, 0x0760, 0x7d03, 0x55fb, 0x6dd3, 0x9991, 0x55fb, 0x1d04, +0x6dd3, 0x6ac8, 0x7f2f, 0x1f01, 0x2003, 0x4800, 0x7ce4, 0x99b9, +0x55fb, 0x6dd7, 0x0015, 0x7805, 0x6209, 0x6ac8, 0x6209, 0x6ac8, +0x6dd7, 0x99b8, 0x55fb, 0x6dd7, 0x0015, 0x0015, 0x7805, 0x620a, +0x6ac8, 0x620a, 0x6ac8, 0x6dd7, 0x99b8, 0x55fb, 0x6dd7, 0x0015, +0x0015, 0x0015, 0x7805, 0x620b, 0x6ac8, 0x620b, 0x6ac8, 0x6dd7, +0x7c09, 0x6ddf, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d07, 0xc1fa, +0x57e3, 0x996c, 0x0007, 0x68cc, 0x680c, 0xc213, 0xc20a, 0x9969, +0xc1d9, 0xc1e3, 0x57db, 0x5fe3, 0x57e3, 0x52f3, 0x6a21, 0x008f, +0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x56fb, 0x0478, 0x7d03, +0x0479, 0x7d2a, 0x7c31, 0x0479, 0x7c20, 0x0b70, 0x0311, 0x53eb, +0x0f00, 0x0360, 0x7d05, 0x6509, 0x7e37, 0x620a, 0x7e35, 0x99ec, +0x620a, 0x7e32, 0x6509, 0x7e30, 0x0512, 0x0512, 0x02ad, 0x0760, +0x7c02, 0x5a06, 0x99f4, 0x5a26, 0x7f27, 0x1f01, 0x2003, 0x4800, +0x7ce8, 0x0b70, 0x0311, 0x5313, 0x9a15, 0x0015, 0x7804, 0x6209, +0x5a06, 0x6209, 0x5a26, 0x9a14, 0x0015, 0x0015, 0x7804, 0x620a, +0x5a06, 0x620a, 0x5a26, 0x9a14, 0x0015, 0x0015, 0x0015, 0x7804, +0x620b, 0x5a06, 0x620b, 0x5a26, 0x7c07, 0x0000, 0x55eb, 0x4d00, +0x7d06, 0xc1fa, 0x57e3, 0x99cf, 0x0007, 0x680c, 0xc213, 0xc20a, +0x99cc, 0xc1e3, 0x57db, 0x52fb, 0x6ac3, 0x52f3, 0x6a05, 0x008f, +0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, +0x7d2b, 0x7c1e, 0x0479, 0x7c33, 0x56ee, 0x0f00, 0x55fb, 0x0760, +0x7d02, 0x6dc3, 0x9a3d, 0x1d04, 0x6dc3, 0x62c8, 0x7e3c, 0x0660, +0x7d02, 0x0210, 0x0212, 0x6a09, 0x7f36, 0x0212, 0x6a09, 0x7f33, +0x0212, 0x6a09, 0x7f30, 0x1f01, 0x2003, 0x4800, 0x7ce7, 0x9a71, +0x55fb, 0x6dc7, 0x0015, 0x0015, 0x0015, 0x7805, 0x62c8, 0x6a0b, +0x62c8, 0x6a0b, 0x6dc7, 0x9a70, 0x55fb, 0x6dc7, 0x0015, 0x0015, +0x7805, 0x62c8, 0x6a0a, 0x62c8, 0x6a0a, 0x6dc7, 0x9a70, 0x55fb, +0x6dc7, 0x0015, 0x7805, 0x62c8, 0x6a09, 0x62c8, 0x6a09, 0x6dc7, +0x7c0a, 0x6a28, 0x57db, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d05, +0xc1fa, 0x57db, 0x9a27, 0xc277, 0x0454, 0xc20a, 0x9a22, 0xc1d9, +0xc1e3, 0x57db, 0x52f3, 0x6a05, 0x008f, 0x00d5, 0x7d01, 0x008d, +0x05a0, 0x56fb, 0x0478, 0x7d03, 0x0479, 0x7d29, 0x7c1f, 0x0479, +0x7c2e, 0x5de3, 0x0d70, 0x0511, 0x55ed, 0x0f00, 0x0760, 0x7d02, +0x5206, 0x9a9b, 0x5226, 0x7e33, 0x0560, 0x7d02, 0x0210, 0x0212, +0x6a09, 0x7f2d, 0x0212, 0x6a09, 0x7f2a, 0x0212, 0x6a09, 0x7f27, +0x1f01, 0x2003, 0x4800, 0x7cea, 0x55e3, 0x9ac6, 0x0015, 0x0015, +0x0015, 0x7804, 0x5206, 0x6a0b, 0x5226, 0x6a0b, 0x9ac5, 0x0015, +0x0015, 0x7804, 0x5206, 0x6a0a, 0x5226, 0x6a0a, 0x9ac5, 0x0015, +0x7804, 0x5206, 0x6a09, 0x5226, 0x6a09, 0x7c09, 0x6a28, 0x7f07, +0x0000, 0x57db, 0x4d00, 0x7d05, 0xc1fa, 0x57db, 0x9a84, 0xc277, +0x0454, 0xc20a, 0x9a81, 0xc1e3, 0x57db, 0x52f3, 0x6ad5, 0x56fb, +0x028e, 0x1a94, 0x6ac3, 0x62c8, 0x0269, 0x7d1e, 0x1e94, 0x6ee3, +0x62d0, 0x5aeb, 0x62c8, 0x0248, 0x6ed3, 0x6ac8, 0x2694, 0x52eb, +0x6ad5, 0x6ee3, 0x62c8, 0x026e, 0x7d27, 0x6ac8, 0x7f23, 0x2501, +0x4d00, 0x7d26, 0x028e, 0x1a98, 0x6ac3, 0x62c8, 0x6ec3, 0x0260, +0x7df1, 0x62d0, 0xc27a, 0x9b18, 0x6ee3, 0x008f, 0x2001, 0x00d5, +0x7d01, 0x008d, 0x05a0, 0x62c8, 0x026e, 0x7d0e, 0x6ac8, 0x7f0a, +0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d09, 0xc1fa, +0x57db, 0x9ad7, 0x0007, 0x6aff, 0x62d0, 0xc27a, 0x0458, 0x0454, +0x6add, 0x7ff8, 0xc20a, 0x9ad4, 0xc1d9, 0xc1e3, 0x57db, 0x52f3, +0x6ad5, 0x56fb, 0x028e, 0x1a94, 0x5202, 0x0269, 0x7d17, 0x1e94, +0x5206, 0x0248, 0x5a06, 0x2694, 0x5206, 0x026e, 0x7d26, 0x6ac8, +0x7f22, 0x2501, 0x4d00, 0x7d27, 0x028e, 0x1a98, 0x5202, 0x0260, +0x7df3, 0x6add, 0x7f18, 0x62d0, 0xc27a, 0x9b5b, 0x008f, 0x2001, +0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5206, 0x026e, 0x7d0e, 0x6ac8, +0x7f0a, 0x2001, 0x7cf9, 0x6add, 0x7f06, 0x0000, 0x4d00, 0x7d0b, +0xc1fa, 0x57db, 0x9b21, 0x0007, 0x6aff, 0x6add, 0x7ffc, 0x62d0, +0xc27a, 0x0458, 0x0454, 0x6add, 0x7ff6, 0xc20a, 0x9b1e +}; +#endif + diff --git a/arch/arm/mach-mx5/sdma_script_code_mx53.h b/arch/arm/mach-mx5/sdma_script_code_mx53.h new file mode 100644 index 000000000000..bfdf74736dcb --- /dev/null +++ b/arch/arm/mach-mx5/sdma_script_code_mx53.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/************************************************************************************ + + SDMA RELEASE LABEL: "SDMA_RITA.01.01.00" + +*************************************************************************************/ + +#ifndef SDMA_SCRIPT_CODE_H +#define SDMA_SCRIPT_CODE_H + + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR_MX53 0 +#define start_SIZE_MX53 22 + +#define core_ADDR_MX53 80 +#define core_SIZE_MX53 232 + +#define common_ADDR_MX53 312 +#define common_SIZE_MX53 330 + +#define ap_2_ap_ADDR_MX53 642 +#define ap_2_ap_SIZE_MX53 41 + +#define app_2_mcu_ADDR_MX53 683 +#define app_2_mcu_SIZE_MX53 64 + +#define mcu_2_app_ADDR_MX53 747 +#define mcu_2_app_SIZE_MX53 70 + +#define uart_2_mcu_ADDR_MX53 817 +#define uart_2_mcu_SIZE_MX53 74 + +#define shp_2_mcu_ADDR_MX53 891 +#define shp_2_mcu_SIZE_MX53 69 + +#define mcu_2_shp_ADDR_MX53 960 +#define mcu_2_shp_SIZE_MX53 72 + +#define uartsh_2_mcu_ADDR_MX53 1032 +#define uartsh_2_mcu_SIZE_MX53 68 + +#define spdif_2_mcu_ADDR_MX53 1100 +#define spdif_2_mcu_SIZE_MX53 34 + +#define mcu_2_spdif_ADDR_MX53 1134 +#define mcu_2_spdif_SIZE_MX53 59 + +#define firi_2_mcu_ADDR_MX53 1193 +#define firi_2_mcu_SIZE_MX53 97 + +#define mcu_2_firi_ADDR_MX53 1290 +#define mcu_2_firi_SIZE_MX53 79 + +#define loop_DMAs_routines_ADDR_MX53 1369 +#define loop_DMAs_routines_SIZE_MX53 227 + +#define test_ADDR_MX53 1596 +#define test_SIZE_MX53 63 + +#define signature_ADDR_MX53 1023 +#define signature_SIZE_MX53 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define mcu_2_ssiapp_ADDR_MX53 6144 +#define mcu_2_ssiapp_SIZE_MX53 98 + +#define mcu_2_ssish_ADDR_MX53 6242 +#define mcu_2_ssish_SIZE_MX53 89 + +#define p_2_p_ADDR_MX53 6331 +#define p_2_p_SIZE_MX53 254 + +#define ssiapp_2_mcu_ADDR_MX53 6585 +#define ssiapp_2_mcu_SIZE_MX53 94 + +#define ssish_2_mcu_ADDR_MX53 6679 +#define ssish_2_mcu_SIZE_MX53 84 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR_MX53 6144 +#define RAM_CODE_SIZE_MX53 619 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short sdma_code_mx53[] = { +0xc1e3, 0x57db, 0x5fe3, 0x57e3, 0x52f3, 0x6a01, 0x008f, 0x00d5, +0x7d01, 0x008d, 0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, 0x7d2c, +0x7c36, 0x0479, 0x7c1f, 0x56ee, 0x0f00, 0x0660, 0x7d05, 0x6509, +0x7e43, 0x620a, 0x7e41, 0x9820, 0x620a, 0x7e3e, 0x6509, 0x7e3c, +0x0512, 0x0512, 0x02ad, 0x0760, 0x7d03, 0x55fb, 0x6dd3, 0x982b, +0x55fb, 0x1d04, 0x6dd3, 0x6ac8, 0x7f2f, 0x1f01, 0x2003, 0x4800, +0x7ce4, 0x9853, 0x55fb, 0x6dd7, 0x0015, 0x7805, 0x6209, 0x6ac8, +0x6209, 0x6ac8, 0x6dd7, 0x9852, 0x55fb, 0x6dd7, 0x0015, 0x0015, +0x7805, 0x620a, 0x6ac8, 0x620a, 0x6ac8, 0x6dd7, 0x9852, 0x55fb, +0x6dd7, 0x0015, 0x0015, 0x0015, 0x7805, 0x620b, 0x6ac8, 0x620b, +0x6ac8, 0x6dd7, 0x7c09, 0x6ddf, 0x7f07, 0x0000, 0x55eb, 0x4d00, +0x7d07, 0xc1fa, 0x57e3, 0x9806, 0x0007, 0x68cc, 0x680c, 0xc213, +0xc20a, 0x9803, 0xc1d9, 0xc1e3, 0x57db, 0x5fe3, 0x57e3, 0x52f3, +0x6a21, 0x008f, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x56fb, +0x0478, 0x7d03, 0x0479, 0x7d2a, 0x7c31, 0x0479, 0x7c20, 0x0b70, +0x0311, 0x53eb, 0x0f00, 0x0360, 0x7d05, 0x6509, 0x7e37, 0x620a, +0x7e35, 0x9886, 0x620a, 0x7e32, 0x6509, 0x7e30, 0x0512, 0x0512, +0x02ad, 0x0760, 0x7c02, 0x5a06, 0x988e, 0x5a26, 0x7f27, 0x1f01, +0x2003, 0x4800, 0x7ce8, 0x0b70, 0x0311, 0x5313, 0x98af, 0x0015, +0x7804, 0x6209, 0x5a06, 0x6209, 0x5a26, 0x98ae, 0x0015, 0x0015, +0x7804, 0x620a, 0x5a06, 0x620a, 0x5a26, 0x98ae, 0x0015, 0x0015, +0x0015, 0x7804, 0x620b, 0x5a06, 0x620b, 0x5a26, 0x7c07, 0x0000, +0x55eb, 0x4d00, 0x7d06, 0xc1fa, 0x57e3, 0x9869, 0x0007, 0x680c, +0xc213, 0xc20a, 0x9866, 0x0b70, 0x0311, 0x5313, 0x076c, 0x7c01, +0xc1d9, 0x5efb, 0x068a, 0x076b, 0x7c01, 0xc1d9, 0x5ef3, 0x59db, +0x58d3, 0x018f, 0x0110, 0x390f, 0x008b, 0xc13c, 0x7d2b, 0x5ac0, +0x5bc8, 0xc14e, 0x7c27, 0x0388, 0x0689, 0x5ce3, 0x0dff, 0x0511, +0x1dff, 0x05bc, 0x073e, 0x4d00, 0x7d18, 0x0870, 0x0011, 0x077e, +0x7d09, 0x077d, 0x7d02, 0x5228, 0x98e6, 0x52f8, 0x54db, 0x02bc, +0x02cc, 0x7c09, 0x077c, 0x7d02, 0x5228, 0x98ef, 0x52f8, 0x54d3, +0x02bc, 0x02cc, 0x7d09, 0x0400, 0x98dd, 0x008b, 0x52c0, 0x53c8, +0xc159, 0x7dd6, 0x0200, 0x98cd, 0x08ff, 0x00bf, 0x077f, 0x7d15, +0x0488, 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x028f, 0x0212, +0x0212, 0x3aff, 0x05da, 0x7c02, 0x073e, 0x9918, 0x02a4, 0x02dd, +0x7d02, 0x073e, 0x9918, 0x075e, 0x9918, 0x55eb, 0x0598, 0x5deb, +0x52f3, 0x54fb, 0x076a, 0x7d26, 0x076c, 0x7d01, 0x9955, 0x076b, +0x7c57, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x992f, 0x5893, +0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, +0x5502, 0x5d04, 0x7c1d, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, +0x7e17, 0x993c, 0x5d04, 0x7f14, 0x0689, 0x5093, 0x4800, 0x7d01, +0x9927, 0x99a0, 0x0015, 0x7806, 0x5502, 0x5d04, 0x074f, 0x5502, +0x5d24, 0x072f, 0x7c01, 0x99a0, 0x0017, 0x076f, 0x7c01, 0x2001, +0x5593, 0x009d, 0x0007, 0xd9a7, 0x98f5, 0x6cd3, 0x0769, 0x7d04, +0x0768, 0x7d02, 0x0e01, 0x9964, 0x5893, 0x00d6, 0x7d01, 0x008e, +0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x5502, 0x6dc8, 0x7c0f, +0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, 0x7e09, 0x9971, 0x6dc8, +0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, 0x995c, 0x99a0, 0x999a, +0x6ac3, 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9987, 0x5893, +0x00d6, 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, +0x65c8, 0x5d04, 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x65c8, +0x7e09, 0x9994, 0x5d04, 0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, +0x997f, 0x99a0, 0x5593, 0x009d, 0x0007, 0x6cff, 0xd9a7, 0x98f5, +0x0000, 0x54e3, 0x55eb, 0x4d00, 0x7c01, 0x98f5, 0x98dd, 0x54e3, +0x55eb, 0x0aff, 0x0211, 0x1aff, 0x077f, 0x7c02, 0x05a0, 0x99b4, +0x009d, 0x058c, 0x05ba, 0x05a0, 0x0210, 0x04ba, 0x04ad, 0x0454, +0x0006, 0xc1e3, 0x57db, 0x52fb, 0x6ac3, 0x52f3, 0x6a05, 0x008f, +0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, +0x7d2b, 0x7c1e, 0x0479, 0x7c33, 0x56ee, 0x0f00, 0x55fb, 0x0760, +0x7d02, 0x6dc3, 0x99d5, 0x1d04, 0x6dc3, 0x62c8, 0x7e3c, 0x0660, +0x7d02, 0x0210, 0x0212, 0x6a09, 0x7f36, 0x0212, 0x6a09, 0x7f33, +0x0212, 0x6a09, 0x7f30, 0x1f01, 0x2003, 0x4800, 0x7ce7, 0x9a09, +0x55fb, 0x6dc7, 0x0015, 0x0015, 0x0015, 0x7805, 0x62c8, 0x6a0b, +0x62c8, 0x6a0b, 0x6dc7, 0x9a08, 0x55fb, 0x6dc7, 0x0015, 0x0015, +0x7805, 0x62c8, 0x6a0a, 0x62c8, 0x6a0a, 0x6dc7, 0x9a08, 0x55fb, +0x6dc7, 0x0015, 0x7805, 0x62c8, 0x6a09, 0x62c8, 0x6a09, 0x6dc7, +0x7c0a, 0x6a28, 0x57db, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d05, +0xc1fa, 0x57db, 0x99bf, 0xc277, 0x0454, 0xc20a, 0x99ba, 0xc1d9, +0xc1e3, 0x57db, 0x52f3, 0x6a05, 0x008f, 0x00d5, 0x7d01, 0x008d, +0x05a0, 0x56fb, 0x0478, 0x7d03, 0x0479, 0x7d29, 0x7c1f, 0x0479, +0x7c2e, 0x5de3, 0x0d70, 0x0511, 0x55ed, 0x0f00, 0x0760, 0x7d02, +0x5206, 0x9a33, 0x5226, 0x7e33, 0x0560, 0x7d02, 0x0210, 0x0212, +0x6a09, 0x7f2d, 0x0212, 0x6a09, 0x7f2a, 0x0212, 0x6a09, 0x7f27, +0x1f01, 0x2003, 0x4800, 0x7cea, 0x55e3, 0x9a5e, 0x0015, 0x0015, +0x0015, 0x7804, 0x5206, 0x6a0b, 0x5226, 0x6a0b, 0x9a5d, 0x0015, +0x0015, 0x7804, 0x5206, 0x6a0a, 0x5226, 0x6a0a, 0x9a5d, 0x0015, +0x7804, 0x5206, 0x6a09, 0x5226, 0x6a09, 0x7c09, 0x6a28, 0x7f07, +0x0000, 0x57db, 0x4d00, 0x7d05, 0xc1fa, 0x57db, 0x9a1c, 0xc277, +0x0454, 0xc20a, 0x9a19 +}; +#endif + diff --git a/arch/arm/mach-mx5/sdram_autogating.c b/arch/arm/mach-mx5/sdram_autogating.c new file mode 100644 index 000000000000..0b05d791c4f9 --- /dev/null +++ b/arch/arm/mach-mx5/sdram_autogating.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sdram_autogating.c + * + * @brief Enable auto clock gating of the EMI_FAST clock using M4IF. + * + * The APIs are for enabling and disabling automatic clock gating of EMI_FAST. + * + * @ingroup PM + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +static struct device *sdram_autogating_dev; +#define M4IF_CNTL_REG0 0x8c +#define M4IF_CNTL_REG1 0x90 + +/* Flag used to indicate if SDRAM M4IF autoclock gating feature is active. */ +static int sdram_autogating_is_active; +static int sdram_autogating_paused; +static void __iomem *m4if_base; + +void start_sdram_autogating(void); +void stop_sdram_autogating(void); +int sdram_autogating_active(void); + +static void enable(void) +{ + u32 reg; + + /* Set the Fast arbitration Power saving timer */ + reg = __raw_readl(m4if_base + M4IF_CNTL_REG1); + reg &= ~0xFF; + reg |= 0x09; + __raw_writel(reg, m4if_base + M4IF_CNTL_REG1); + /*Allow for automatic gating of the EMI internal clock. + * If this is done, emi_intr CCGR bits should be set to 11. + */ + reg = __raw_readl(m4if_base + M4IF_CNTL_REG0); + reg &= ~0x5; + __raw_writel(reg, m4if_base + M4IF_CNTL_REG0); + + sdram_autogating_is_active = 1; +} + +static void disable(void) +{ + u32 reg; + + reg = __raw_readl(m4if_base + M4IF_CNTL_REG0); + reg |= 0x4; + __raw_writel(reg, m4if_base + M4IF_CNTL_REG0); + sdram_autogating_is_active = 0; +} + +int sdram_autogating_active() +{ + return sdram_autogating_is_active; +} + +void start_sdram_autogating() +{ + if (cpu_is_mx50()) + return; + if (sdram_autogating_paused) { + enable(); + sdram_autogating_paused = 0; + } +} + +void stop_sdram_autogating() +{ + if (cpu_is_mx50()) + return; + + if (sdram_autogating_is_active) { + sdram_autogating_paused = 1; + disable(); + } +} + +static ssize_t sdram_autogating_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (sdram_autogating_is_active) + return sprintf(buf, + "M4IF autoclock gating for EMI_FAST enabled\n"); + else + return sprintf(buf, + "M4IF autoclock gating for EMI_FAST disabled\n"); +} + +static ssize_t sdram_autogating_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) + enable(); + else if (strstr(buf, "0") != NULL) { + if (sdram_autogating_is_active) + disable(); + } + return size; +} + +static DEVICE_ATTR(enable, 0644, sdram_autogating_enable_show, + sdram_autogating_enable_store); + +/*! + * This is the probe routine for the auto clockgating of sdram driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit sdram_autogating_probe(struct platform_device *pdev) +{ + struct resource *res; + int err = 0; + + sdram_autogating_dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + return -ENOMEM; + } + m4if_base = ioremap(res->start, res->end - res->start + 1); + + err = sysfs_create_file(&sdram_autogating_dev->kobj, + &dev_attr_enable.attr); + if (err) { + printk(KERN_ERR + "Unable to register sysdev entry for sdram_autogating"); + return err; + } + + sdram_autogating_is_active = 0; + + return 0; +} + +static struct platform_driver sdram_autogating_driver = { + .driver = { + .name = "sdram_autogating", + }, + .probe = sdram_autogating_probe, +}; + +/*! + * Initialise the sdram_autogating_driver. + * + * @return The function always returns 0. + */ + +static int __init sdram_autogating_init(void) +{ + if (platform_driver_register(&sdram_autogating_driver) != 0) { + printk(KERN_ERR "sdram_autogating_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "sdram autogating driver module loaded\n"); + return 0; +} + +static void __exit sdram_autogating_cleanup(void) +{ + sysfs_remove_file(&sdram_autogating_dev->kobj, &dev_attr_enable.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&sdram_autogating_driver); +} + +module_init(sdram_autogating_init); +module_exit(sdram_autogating_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("sdram_autogating driver"); +MODULE_LICENSE("GPL"); + diff --git a/arch/arm/mach-mx5/serial.c b/arch/arm/mach-mx5/serial.c new file mode 100644 index 000000000000..18dfcfb6d696 --- /dev/null +++ b/arch/arm/mach-mx5/serial.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file mach-mx51/serial.c + * + * @brief This file contains the UART initiliazation. + * + * @ingroup MSL_MX51 + */ +#include +#include +#include +#include +#include +#include "serial.h" + +#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) + +/*! + * This is an array where each element holds information about a UART port, + * like base address of the UART, interrupt numbers etc. This structure is + * passed to the serial_core.c file. Based on which UART is used, the core file + * passes back the appropriate port structure as an argument to the control + * functions. + */ +static uart_mxc_port mxc_ports[] = { + [0] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, + .ints_muxed = 1, + .mode = MODE_DCE, + .ir_mode = NO_IRDA, + .enabled = 1, + .cts_threshold = UART1_UCR4_CTSTL, + .dma_enabled = UART1_DMA_ENABLE, + .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, + .rx_threshold = UART1_UFCR_RXTL, + .tx_threshold = UART1_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART1_TX, + .dma_rx_id = MXC_DMA_UART1_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [1] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 1, + }, + .ints_muxed = 1, + .mode = MODE_DCE, + .ir_mode = NO_IRDA, + .enabled = 1, + .cts_threshold = UART2_UCR4_CTSTL, + .dma_enabled = UART2_DMA_ENABLE, + .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, + .rx_threshold = UART2_UFCR_RXTL, + .tx_threshold = UART2_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART2_TX, + .dma_rx_id = MXC_DMA_UART2_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [2] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 2, + }, + .ints_muxed = 1, + .mode = MODE_DCE, + .ir_mode = NO_IRDA, + .enabled = 1, + .cts_threshold = UART3_UCR4_CTSTL, + .dma_enabled = UART3_DMA_ENABLE, + .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, + .rx_threshold = UART3_UFCR_RXTL, + .tx_threshold = UART3_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART3_TX, + .dma_rx_id = MXC_DMA_UART3_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [3] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 3, + }, + .ints_muxed = 1, + .mode = MODE_DCE, + .ir_mode = NO_IRDA, + .enabled = 1, + .cts_threshold = UART4_UCR4_CTSTL, + .dma_enabled = UART4_DMA_ENABLE, + .dma_rxbuf_size = UART4_DMA_RXBUFSIZE, + .rx_threshold = UART4_UFCR_RXTL, + .tx_threshold = UART4_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART4_TX, + .dma_rx_id = MXC_DMA_UART4_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [4] = { + .port = { + .iotype = SERIAL_IO_MEM, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 4, + }, + .ints_muxed = 1, + .mode = MODE_DCE, + .ir_mode = NO_IRDA, + .enabled = 1, + .cts_threshold = UART5_UCR4_CTSTL, + .dma_enabled = UART5_DMA_ENABLE, + .dma_rxbuf_size = UART5_DMA_RXBUFSIZE, + .rx_threshold = UART5_UFCR_RXTL, + .tx_threshold = UART5_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART5_TX, + .dma_rx_id = MXC_DMA_UART5_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, +}; + +static struct resource mxc_uart_resources1[] = { + { + .start = UART1_BASE_ADDR, + .end = UART1_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device1 = { + .name = "mxcintuart", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_uart_resources1), + .resource = mxc_uart_resources1, + .dev = { + .platform_data = &mxc_ports[0], + }, +}; + +static struct resource mxc_uart_resources2[] = { + { + .start = UART2_BASE_ADDR, + .end = UART2_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_UART2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device2 = { + .name = "mxcintuart", + .id = 1, + .num_resources = ARRAY_SIZE(mxc_uart_resources2), + .resource = mxc_uart_resources2, + .dev = { + .platform_data = &mxc_ports[1], + }, +}; + +static struct resource mxc_uart_resources3[] = { + { + .start = UART3_BASE_ADDR, + .end = UART3_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device3 = { + .name = "mxcintuart", + .id = 2, + .num_resources = ARRAY_SIZE(mxc_uart_resources3), + .resource = mxc_uart_resources3, + .dev = { + .platform_data = &mxc_ports[2], + }, +}; + +static struct resource mxc_uart_resources4[] = { + { + .start = UART4_BASE_ADDR, + .end = UART4_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_UART4, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device4 = { + .name = "mxcintuart", + .id = 3, + .num_resources = ARRAY_SIZE(mxc_uart_resources4), + .resource = mxc_uart_resources4, + .dev = { + .platform_data = &mxc_ports[3], + }, +}; + +static struct resource mxc_uart_resources5[] = { + { + .start = UART5_BASE_ADDR, + .end = UART5_BASE_ADDR + 0x0B5, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_UART5, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mxc_uart_device5 = { + .name = "mxcintuart", + .id = 4, + .num_resources = ARRAY_SIZE(mxc_uart_resources5), + .resource = mxc_uart_resources5, + .dev = { + .platform_data = &mxc_ports[4], + }, +}; + +static int __init mxc_init_uart(void) +{ + if (cpu_is_mx53() || cpu_is_mx50()) { + mxc_uart_resources1[0].start -= 0x20000000; + mxc_uart_resources1[0].end -= 0x20000000; + mxc_uart_resources2[0].start -= 0x20000000; + mxc_uart_resources2[0].end -= 0x20000000; + mxc_uart_resources3[0].start -= 0x20000000; + mxc_uart_resources3[0].end -= 0x20000000; + mxc_uart_resources4[0].start -= 0x20000000; + mxc_uart_resources4[0].end -= 0x20000000; + mxc_uart_resources5[0].start -= 0x20000000; + mxc_uart_resources5[0].end -= 0x20000000; + } + + /* Register all the MXC UART platform device structures */ + platform_device_register(&mxc_uart_device1); + platform_device_register(&mxc_uart_device2); + platform_device_register(&mxc_uart_device3); + if (cpu_is_mx53()) { + platform_device_register(&mxc_uart_device4); + platform_device_register(&mxc_uart_device5); + } + return 0; +} + +#else +static int __init mxc_init_uart(void) +{ + return 0; +} +#endif + +arch_initcall(mxc_init_uart); diff --git a/arch/arm/mach-mx5/serial.h b/arch/arm/mach-mx5/serial.h new file mode 100644 index 000000000000..9fbb0b33e4eb --- /dev/null +++ b/arch/arm/mach-mx5/serial.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARCH_ARM_MACH_MX51_SERIAL_H__ +#define __ARCH_ARM_MACH_MX51_SERIAL_H__ + +/* UART 1 configuration */ +/*! + * This specifies the threshold at which the CTS pin is deasserted by the + * RXFIFO. Set this value in Decimal to anything from 0 to 32 for + * hardware-driven hardware flow control. Read the HW spec while specifying + * this value. When using interrupt-driven software controlled hardware + * flow control set this option to -1. + */ +#define UART1_UCR4_CTSTL 16 +/*! + * Specify the size of the DMA receive buffer. The minimum buffer size is 512 + * bytes. The buffer size should be a multiple of 256. + */ +#define UART1_DMA_RXBUFSIZE 1024 +/*! + * Specify the MXC UART's Receive Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the RxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_RXTL 16 +/*! + * Specify the MXC UART's Transmit Trigger Level. This controls the threshold at + * which a maskable interrupt is generated by the TxFIFO. Set this value in + * Decimal to anything from 0 to 32. Read the HW spec while specifying this + * value. + */ +#define UART1_UFCR_TXTL 16 +#define UART1_DMA_ENABLE 0 +/* UART 2 configuration */ +#define UART2_UCR4_CTSTL -1 +#define UART2_DMA_ENABLE 1 +#define UART2_DMA_RXBUFSIZE 512 +#define UART2_UFCR_RXTL 16 +#define UART2_UFCR_TXTL 16 +/* UART 3 configuration */ +#define UART3_UCR4_CTSTL 16 +#define UART3_DMA_ENABLE 0 +#define UART3_DMA_RXBUFSIZE 1024 +#define UART3_UFCR_RXTL 16 +#define UART3_UFCR_TXTL 16 +/* UART 4 configuration */ +#define UART4_UCR4_CTSTL -1 +#define UART4_DMA_ENABLE 0 +#define UART4_DMA_RXBUFSIZE 512 +#define UART4_UFCR_RXTL 16 +#define UART4_UFCR_TXTL 16 +/* UART 5 configuration */ +#define UART5_UCR4_CTSTL -1 +#define UART5_DMA_ENABLE 0 +#define UART5_DMA_RXBUFSIZE 512 +#define UART5_UFCR_RXTL 16 +#define UART5_UFCR_TXTL 16 + +#endif /* __ARCH_ARM_MACH_MX51_SERIAL_H__ */ diff --git a/arch/arm/mach-mx5/suspend.S b/arch/arm/mach-mx5/suspend.S new file mode 100644 index 000000000000..f5aa1cc2f668 --- /dev/null +++ b/arch/arm/mach-mx5/suspend.S @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +#define ARM_CTRL_DCACHE 1 << 2 +#define ARM_CTRL_ICACHE 1 << 12 +#define ARM_AUXCR_L2EN 1 << 1 + + +/* + * cpu_do_suspend_workaround() + * + * Suspend the processor (eg, wait for interrupt). + * + * IRQs are already disabled. + */ +ENTRY(cpu_do_suspend_workaround) + stmfd sp!, {r4,r5,r6,r7,r9,r10,r11} @ Save registers + + mov r6, r0 @save iomux address + /* Disable L1 caches */ + mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg + bic r0, r0, #ARM_CTRL_ICACHE @ Disable ICache + bic r0, r0, #ARM_CTRL_DCACHE @ Disable DCache + mcr p15, 0, r0, c1, c0, 0 @ Update system control reg + + mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR + ands r3, r0, #0x7000000 @ Isolate level of coherency + mov r3, r3, lsr #23 @ Cache level value (naturally aligned) + beq FinishedClean + mov r10, #0 +Loop1Clean: + add r2, r10, r10, lsr #1 @ Work out cache level + mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache Type for this level + and r1, r1, #7 @ Get those 3 bits alone + cmp r1, #2 + blt SkipClean @ No cache or only instruction cache at this level + mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register + mov r1, #0 + .long 0xF57FF06F @ ISB + mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register + and r2, r1, #7 @ Extract the line length field + add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes) + ldr r4, =0x3FF + ands r4, r4, r1, lsr #3 @ R4 is the max number on the way size (right aligned) + clz r5, r4 @ R5 is the bit position of the way size increment + ldr r7, =0x00007FFF + ands r7, r7, r1, lsr #13 @ R7 is the max number of the index size (right aligned) +Loop2Clean: + mov r9, r4 @ R9 working copy of the max way size (right aligned) +Loop3Clean: + orr r11, r10, r9, lsl r5 @ Factor in the way number and cache number into R11 + orr r11, r11, r7, lsl r2 @ Factor in the index number + mcr p15, 0, r11, c7, c14, 2 @ Clean and invalidate by set/way + subs r9, r9, #1 @ Decrement the way number + bge Loop3Clean + subs r7, r7, #1 @ Decrement the index + bge Loop2Clean +SkipClean: + add r10, r10, #2 @ Increment the cache number + cmp r3, r10 + bgt Loop1Clean + +FinishedClean: + + /* Disable L2 cache */ + mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg + bic r0, r0, #ARM_AUXCR_L2EN @ Disable L2 cache + mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg + + /*Set the DDR drive strength to low */ + ldr r10, [r6] + and r10, r10, #0xF1 @ clear bits 2-1 + str r10, [r6] + + .long 0xe320f003 @ Opcode for WFI + + /*Set the DDR drive strength to max */ + orr r10, r10, #0x06 @ set bits 2-1 + str r10, [r6] + + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate inst cache + + /* Invalidate data caches */ + mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR + ands r3, r0, #0x7000000 @ Isolate level of coherency + mov r3, r3, lsr #23 @ Cache level value (naturally aligned) + beq FinishedInvalidate + mov r10, #0 +Loop1Invalidate: + add r2, r10, r10, lsr #1 @ Work out cache level + mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache Type for this level + and r1, r1, #7 @ Get those 3 bits alone + cmp r1, #2 + blt SkipInvalidate @ No cache or only instruction cache at this level + mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register + mov r1, #0 + .long 0xF57FF06F @ ISB + mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register + and r2, r1, #7 @ Extract the line length field + add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes) + ldr r4, =0x3FF + ands r4, r4, r1, lsr #3 @ R4 is the max number on the way size (right aligned) + clz r5, r4 @ R5 is the bit position of the way size increment + ldr r7, =0x00007FFF + ands r7, r7, r1, lsr #13 @ R7 is the max number of the index size (right aligned) +Loop2Invalidate: + mov r9, r4 @ R9 working copy of the max way size (right aligned) +Loop3Invalidate: + orr r11, r10, r9, lsl r5 @ Factor in the way number and cache number into R11 + orr r11, r11, r7, lsl r2 @ Factor in the index number + mcr p15, 0, r11, c7, c6, 2 @ Invalidate by set/way + subs r9, r9, #1 @ Decrement the way number + bge Loop3Invalidate + subs r7, r7, #1 @ Decrement the index + bge Loop2Invalidate +SkipInvalidate: + add r10, r10, #2 @ Increment the cache number + cmp r3, r10 + bgt Loop1Invalidate + +FinishedInvalidate: + + /* Enable L2 cache */ + mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg + orr r0, r0, #ARM_AUXCR_L2EN @ Enable L2 cache + mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg + + /* Enable L1 caches */ + mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg + orr r0, r0, #ARM_CTRL_ICACHE @ Enable ICache + orr r0, r0, #ARM_CTRL_DCACHE @ Enable DCache + mcr p15, 0, r0, c1, c0, 0 @ Update system control reg + + /* Restore registers */ + ldmfd sp!, {r4,r5,r6,r7,r9,r10,r11} + mov pc, lr + + .type cpu_do_suspend, #object +ENTRY(cpu_do_suspend) + .word cpu_do_suspend_workaround + .size cpu_do_suspend_workaround, . - cpu_do_suspend_workaround diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c new file mode 100644 index 000000000000..a04962f64275 --- /dev/null +++ b/arch/arm/mach-mx5/system.c @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "crm_regs.h" + +/*! + * @defgroup MSL_MX51 i.MX51 Machine Specific Layer (MSL) + */ + +/*! + * @file mach-mx51/system.c + * @brief This file contains idle and reset functions. + * + * @ingroup MSL_MX51 + */ + +extern int mxc_jtag_enabled; +extern int iram_ready; +extern int dvfs_core_is_active; +extern void __iomem *ccm_base; +extern void __iomem *databahn_base; +extern int low_bus_freq_mode; +extern void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); +extern void mx50_wait(u32 ccm_base, u32 databahn_addr); +extern void stop_dvfs(void); +extern void *wait_in_iram_base; +extern void __iomem *apll_base; + +static struct clk *gpc_dvfs_clk; +static struct regulator *vpll; +static struct clk *pll1_sw_clk; +static struct clk *osc; +static struct clk *pll1_main_clk; +static struct clk *ddr_clk ; +static int dvfs_core_paused; + +/* set cpu low power mode before WFI instruction */ +void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) +{ + u32 plat_lpc, arm_srpgcr, ccm_clpcr; + u32 empgc0, empgc1; + int stop_mode = 0; + + /* always allow platform to issue a deep sleep mode request */ + plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & + ~(MXC_CORTEXA8_PLAT_LPC_DSM); + ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); + arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); + empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); + + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); + break; + case WAIT_UNCLOCKED_POWER_OFF: + case STOP_POWER_OFF: + plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM + | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; + if (mode == WAIT_UNCLOCKED_POWER_OFF) { + ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); + ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; + ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; + stop_mode = 0; + } else { + ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); + ccm_clpcr |= (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET); + ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; + ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; + stop_mode = 1; + } + + arm_srpgcr |= MXC_SRPGCR_PCR; + if (stop_mode) { + empgc0 |= MXC_SRPGCR_PCR; + empgc1 |= MXC_SRPGCR_PCR; + } + + if (tzic_enable_wake(1) != 0) + return; + break; + case STOP_POWER_ON: + ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); + break; + default: + printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); + return; + } + + __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); + __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); + if (cpu_is_mx51() || (cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) + || cpu_is_mx50_rev(CHIP_REV_1_1) >= 1) + __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); + /* Enable NEON SRPG for all but MX50TO1.0. */ + if (!(cpu_is_mx50_rev(CHIP_REV_1_0) == 1)) + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + if (stop_mode) { + __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); + } +} + +void mxc_pg_enable(struct platform_device *pdev) +{ + if (pdev == NULL) + return; + + if (strcmp(pdev->name, "mxc_ipu") == 0) { + __raw_writel(MXC_PGCR_PCR, MXC_PGC_IPU_PGCR); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_IPU_PGSR); + } else if (strcmp(pdev->name, "mxc_vpu") == 0) { + __raw_writel(MXC_PGCR_PCR, MXC_PGC_VPU_PGCR); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_VPU_PGSR); + } +} + +EXPORT_SYMBOL(mxc_pg_enable); + +void mxc_pg_disable(struct platform_device *pdev) +{ + if (pdev == NULL) + return; + + if (strcmp(pdev->name, "mxc_ipu") == 0) { + __raw_writel(0x0, MXC_PGC_IPU_PGCR); + if (__raw_readl(MXC_PGC_IPU_PGSR) & MXC_PGSR_PSR) + dev_dbg(&pdev->dev, "power gating successful\n"); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_IPU_PGSR); + } else if (strcmp(pdev->name, "mxc_vpu") == 0) { + __raw_writel(0x0, MXC_PGC_VPU_PGCR); + if (__raw_readl(MXC_PGC_VPU_PGSR) & MXC_PGSR_PSR) + dev_dbg(&pdev->dev, "power gating successful\n"); + __raw_writel(MXC_PGSR_PSR, MXC_PGC_VPU_PGSR); + } +} + +EXPORT_SYMBOL(mxc_pg_disable); + +/* To change the idle power mode, need to set arch_idle_mode to a different + * power mode as in enum mxc_cpu_pwr_mode. + * May allow dynamically changing the idle mode. + */ +static int arch_idle_mode = WAIT_UNCLOCKED_POWER_OFF; +/*! + * This function puts the CPU into idle mode. It is called by default_idle() + * in process.c file. + */ +void arch_idle(void) +{ + if (likely(!mxc_jtag_enabled)) { + if (ddr_clk == NULL) + ddr_clk = clk_get(NULL, "ddr_clk"); + if (gpc_dvfs_clk == NULL) + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); + /* gpc clock is needed for SRPG */ + clk_enable(gpc_dvfs_clk); + mxc_cpu_lp_set(arch_idle_mode); + + if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) { + memcpy(wait_in_iram_base, mx50_wait, SZ_4K); + wait_in_iram = (void *)wait_in_iram_base; + if (low_bus_freq_mode) { + u32 reg, cpu_podf; + + reg = __raw_readl(apll_base + 0x50); + reg = 0x120490; + __raw_writel(reg, apll_base + 0x50); + reg = __raw_readl(apll_base + 0x80); + reg |= 1; + __raw_writel(reg, apll_base + 0x80); + + /* Move ARM to be sourced from 24MHz XTAL. + * when ARM is in WFI. + */ + if (pll1_sw_clk == NULL) + pll1_sw_clk = clk_get(NULL, + "pll1_sw_clk"); + if (osc == NULL) + osc = clk_get(NULL, "lp_apm"); + if (pll1_main_clk == NULL) + pll1_main_clk = clk_get(NULL, + "pll1_main_clk"); + + clk_set_parent(pll1_sw_clk, osc); + /* Set the ARM-PODF divider to 1. */ + cpu_podf = __raw_readl(MXC_CCM_CACRR); + __raw_writel(0x01, MXC_CCM_CACRR); + + wait_in_iram(ccm_base, databahn_base); + + /* Set the ARM-POD divider back + * to the original. + */ + __raw_writel(cpu_podf, MXC_CCM_CACRR); + clk_set_parent(pll1_sw_clk, pll1_main_clk); + } else + wait_in_iram(ccm_base, databahn_base); + } else + cpu_do_idle(); + clk_disable(gpc_dvfs_clk); + clk_put(ddr_clk); + } +} + +static int __mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + u32 c; + int timeout; + + /* the process of software reset of IP block is done + in several steps: + + - clear SFTRST and wait for block is enabled; + - clear clock gating (CLKGATE bit); + - set the SFTRST again and wait for block is in reset; + - clear SFTRST and wait for reset completion. + */ + c = __raw_readl(hwreg); + c &= ~(1 << 31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + + if (!just_enable) { + c = __raw_readl(hwreg); + c |= (1 << 31); /* now again set SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* poll until CLKGATE set */ + if (__raw_readl(hwreg) & (1 << 30)) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when resetting\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling " + "after reset\n", __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + } + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 30)) == 0) + break; + + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when unclockgating\n", + __func__, hwreg); + return -ETIME; + } + + return 0; +} + +int mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + int try = 10; + int r; + + while (try--) { + r = __mxs_reset_block(hwreg, just_enable); + if (!r) + break; + pr_debug("%s: try %d failed\n", __func__, 10 - try); + } + return r; +} + diff --git a/arch/arm/mach-mx5/usb.h b/arch/arm/mach-mx5/usb.h new file mode 100644 index 000000000000..6115d3375c05 --- /dev/null +++ b/arch/arm/mach-mx5/usb.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include "devices.h" + +extern int usbotg_init(struct platform_device *pdev); +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_hs_active(void); +extern void gpio_usbotg_hs_inactive(void); +extern struct platform_device *host_pdev_register(struct resource *res, + int n_res, struct fsl_usb2_platform_data *config); + +extern int fsl_usb_host_init(struct platform_device *pdev); +extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata); +extern int gpio_usbotg_utmi_active(void); +extern void gpio_usbotg_utmi_inactive(void); + +extern void __init mx5_usb_dr_init(void); +extern void __init mx5_usbh1_init(void); +extern void __init mx5_usbh2_init(void); + +typedef void (*driver_vbus_func)(bool); +extern void mx5_set_host1_vbus_func(driver_vbus_func); +extern void mx5_set_otghost_vbus_func(driver_vbus_func); +/* + * Used to set pdata->operating_mode before registering the platform_device. + * If OTG is configured, the controller operates in OTG mode, + * otherwise it's either host or device. + */ +#ifdef CONFIG_USB_OTG +#define DR_UDC_MODE FSL_USB2_DR_OTG +#define DR_HOST_MODE FSL_USB2_DR_OTG +#else +#define DR_UDC_MODE FSL_USB2_DR_DEVICE +#define DR_HOST_MODE FSL_USB2_DR_HOST +#endif + diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c new file mode 100644 index 000000000000..d0dba3a3bf38 --- /dev/null +++ b/arch/arm/mach-mx5/usb_dr.c @@ -0,0 +1,314 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "usb.h" +static int usbotg_init_ext(struct platform_device *pdev); +static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata); +static void usbotg_clock_gate(bool on); + +static struct clk *usb_phy1_clk; +static struct clk *usb_oh3_clk; +static struct clk *usb_ahb_clk; +static void usbotg_wakeup_event_clear(void); +extern int clk_get_usecount(struct clk *clk); + +/* Beginning of Common operation for DR port */ + +/* + * platform data structs + * - Which one to use is determined by CONFIG options in usb.h + * - operating_mode plugged at run time + */ +static struct fsl_usb2_platform_data dr_utmi_config = { + .name = "DR", + .platform_init = usbotg_init_ext, + .platform_uninit = usbotg_uninit_ext, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .gpio_usb_active = gpio_usbotg_hs_active, + .gpio_usb_inactive = gpio_usbotg_hs_inactive, + .usb_clock_for_pm = usbotg_clock_gate, + .transceiver = "utmi", +}; + +/* Platform data for wakeup operation */ +static struct fsl_usb2_wakeup_platform_data dr_wakeup_config = { + .name = "DR wakeup", + .usb_clock_for_pm = usbotg_clock_gate, + .usb_wakeup_exhandle = usbotg_wakeup_event_clear, +}; +/* Notes: configure USB clock*/ +static int usbotg_init_ext(struct platform_device *pdev) +{ + struct clk *usb_clk; + + /* the usb_ahb_clk will be enabled in usb_otg_init */ + usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usb_clk); + usb_oh3_clk = usb_clk; + + usb_clk = clk_get(NULL, "usb_phy1_clk"); + clk_enable(usb_clk); + usb_phy1_clk = usb_clk; + + return usbotg_init(pdev); +} + +static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + clk_disable(usb_phy1_clk); + clk_put(usb_phy1_clk); + + clk_disable(usb_oh3_clk); + clk_put(usb_oh3_clk); + + /* usb_ahb_clk will be disabled at usb_common.c */ + usbotg_uninit(pdata); + clk_put(usb_ahb_clk); +} + +/* Below two macros are used at otg mode to indicate usb mode*/ +#define ENABLED_BY_HOST (0x1 << 0) +#define ENABLED_BY_DEVICE (0x1 << 1) +static u32 wakeup_irq_enable_src; /* only useful at otg mode */ +static void __wakeup_irq_enable(bool on, int source) + { + /* otg host and device share the OWIE bit, only when host and device + * all enable the wakeup irq, we can enable the OWIE bit + */ + if (on) { +#ifdef CONFIG_USB_OTG + wakeup_irq_enable_src |= source; + if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { + USBCTRL |= UCTRL_OWIE; + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2; + } +#else + USBCTRL |= UCTRL_OWIE; + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2; +#endif + } else { + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2; + USBCTRL &= ~UCTRL_OWIE; + wakeup_irq_enable_src &= ~source; + /* The interrupt must be disabled for at least 3 clock + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static u32 low_power_enable_src; /* only useful at otg mode */ +static void __phy_lowpower_suspend(bool enable, int source) +{ + if (enable) { + low_power_enable_src |= source; +#ifdef CONFIG_USB_OTG + if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { + pr_debug("phy lowpower enabled\n"); + UOG_PORTSC1 |= PORTSC_PHCD; + } +#else + UOG_PORTSC1 |= PORTSC_PHCD; +#endif + } else { + pr_debug("phy lowpower disable\n"); + UOG_PORTSC1 &= ~PORTSC_PHCD; + low_power_enable_src &= ~source; + } +} + +static void usbotg_clock_gate(bool on) +{ + pr_debug("%s: on is %d\n", __func__, on); + if (on) { + clk_enable(usb_ahb_clk); + clk_enable(usb_oh3_clk); + clk_enable(usb_phy1_clk); + } else { + clk_disable(usb_phy1_clk); + clk_disable(usb_oh3_clk); + clk_disable(usb_ahb_clk); + } + pr_debug("usb_ahb_ref_count:%d, usb_phy_clk1_ref_count:%d\n", clk_get_usecount(usb_ahb_clk), clk_get_usecount(usb_phy1_clk)); +} + +void mx5_set_otghost_vbus_func(driver_vbus_func driver_vbus) +{ + dr_utmi_config.platform_driver_vbus = driver_vbus; +} + +/* The wakeup operation for DR port, it will clear the wakeup irq status + * and re-enable the wakeup + */ +static void usbotg_wakeup_event_clear(void) +{ + int wakeup_req = USBCTRL & UCTRL_OWIR; + + if (wakeup_req != 0) { + printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC); + /* Disable OWIE to clear OWIR, wait 3 clock + * cycles of standly clock(32KHz) + */ + USBCTRL &= ~UCTRL_OWIE; + udelay(100); + USBCTRL |= UCTRL_OWIE; + } +} +/* End of Common operation for DR port */ + + +#ifdef CONFIG_USB_EHCI_ARC_OTG +extern void fsl_usb_recover_hcd(struct platform_device *pdev); +/* Beginning of host related operation for DR port */ +static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __wakeup_irq_enable(enable, ENABLED_BY_HOST); + /* host only care the ID change wakeup event */ + if (enable) { + pr_debug("host wakeup enable\n"); + USBCTRL_HOST2 |= UCTRL_H2OIDWK_EN; + } else { + pr_debug("host wakeup disable\n"); + USBCTRL_HOST2 &= ~UCTRL_H2OIDWK_EN; + /* The interrupt must be disabled for at least 3 clock + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static void _host_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __phy_lowpower_suspend(enable, ENABLED_BY_HOST); +} + +static enum usb_wakeup_event _is_host_wakeup(struct fsl_usb2_platform_data *pdata) +{ + int wakeup_req = USBCTRL & UCTRL_OWIR; + int otgsc = UOG_OTGSC; + + /* if ID change sts, it is a host wakeup event */ + if (wakeup_req && (otgsc & OTGSC_IS_USB_ID)) { + printk(KERN_INFO "otg host ID wakeup\n"); + /* if host ID wakeup, we must clear the b session change sts */ + UOG_OTGSC = otgsc & (~OTGSC_IS_USB_ID); + return WAKEUP_EVENT_ID; + } + if (wakeup_req && (!(otgsc & OTGSC_STS_USB_ID))) { + printk(KERN_INFO "otg host Remote wakeup\n"); + return WAKEUP_EVENT_DPDM; + } + + return WAKEUP_EVENT_INVALID; +} + +static void host_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _host_wakeup_enable(pdata, false); + _host_phy_lowpower_suspend(pdata, false); + fsl_usb_recover_hcd(&mxc_usbdr_host_device); +} +/* End of host related operation for DR port */ +#endif /* CONFIG_USB_EHCI_ARC_OTG */ + + +#ifdef CONFIG_USB_GADGET_ARC +/* Beginning of device related operation for DR port */ +static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __wakeup_irq_enable(enable, ENABLED_BY_DEVICE); + /* if udc is not used by any gadget, we can not enable the vbus wakeup */ + if (!pdata->port_enables) { + USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN; + return; + } + if (enable) { + pr_debug("device wakeup enable\n"); + USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN; + } else { + pr_debug("device wakeup disable\n"); + USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN; + } +} + +static void _device_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __phy_lowpower_suspend(enable, ENABLED_BY_DEVICE); +} + +static enum usb_wakeup_event _is_device_wakeup(struct fsl_usb2_platform_data *pdata) +{ + int wakeup_req = USBCTRL & UCTRL_OWIR; + + if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) && (UOG_OTGSC & OTGSC_IS_B_SESSION_VALID)) { + printk(KERN_INFO "otg udc wakeup\n"); + return WAKEUP_EVENT_VBUS; + } + return WAKEUP_EVENT_INVALID; + +} + +static void device_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _device_wakeup_enable(pdata, false); + _device_phy_lowpower_suspend(pdata, false); +} + +/* end of device related operation for DR port */ +#endif /* CONFIG_USB_GADGET_ARC */ + + +void __init mx5_usb_dr_init(void) +{ +#ifdef CONFIG_USB_OTG + /* wake_up_enalbe is useless, just for usb_register_remote_wakeup execution*/ + dr_utmi_config.wake_up_enable = _device_wakeup_enable; + dr_utmi_config.operating_mode = FSL_USB2_DR_OTG; + dr_utmi_config.wakeup_pdata = &dr_wakeup_config; + platform_device_add_data(&mxc_usbdr_otg_device, &dr_utmi_config, sizeof(dr_utmi_config)); + platform_device_register(&mxc_usbdr_otg_device); + dr_wakeup_config.usb_pdata[0] = mxc_usbdr_otg_device.dev.platform_data; +#endif +#ifdef CONFIG_USB_EHCI_ARC_OTG + dr_utmi_config.operating_mode = DR_HOST_MODE; + dr_utmi_config.wake_up_enable = _host_wakeup_enable; + dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend; + dr_utmi_config.is_wakeup_event = _is_host_wakeup; + dr_utmi_config.wakeup_pdata = &dr_wakeup_config; + dr_utmi_config.wakeup_handler = host_wakeup_handler; + platform_device_add_data(&mxc_usbdr_host_device, &dr_utmi_config, sizeof(dr_utmi_config)); + platform_device_register(&mxc_usbdr_host_device); + dr_wakeup_config.usb_pdata[1] = mxc_usbdr_host_device.dev.platform_data; +#endif +#ifdef CONFIG_USB_GADGET_ARC + dr_utmi_config.operating_mode = DR_UDC_MODE; + dr_utmi_config.wake_up_enable = _device_wakeup_enable; + dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend; + dr_utmi_config.is_wakeup_event = _is_device_wakeup; + dr_utmi_config.wakeup_pdata = &dr_wakeup_config; + dr_utmi_config.wakeup_handler = device_wakeup_handler; + platform_device_add_data(&mxc_usbdr_udc_device, &dr_utmi_config, sizeof(dr_utmi_config)); + platform_device_register(&mxc_usbdr_udc_device); + dr_wakeup_config.usb_pdata[2] = mxc_usbdr_udc_device.dev.platform_data; +#endif + mxc_register_device(&mxc_usbdr_wakeup_device, &dr_wakeup_config); +} diff --git a/arch/arm/mach-mx5/usb_h1.c b/arch/arm/mach-mx5/usb_h1.c new file mode 100644 index 000000000000..197947cfcb3c --- /dev/null +++ b/arch/arm/mach-mx5/usb_h1.c @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "usb.h" +#include "iomux.h" +#include "mx51_pins.h" +static struct clk *usb_phy2_clk; +static struct clk *usb_oh3_clk; +static struct clk *usb_ahb_clk; +extern int clk_get_usecount(struct clk *clk); + +#ifdef CONFIG_USB_EHCI_ARC +extern void fsl_usb_recover_hcd(struct platform_device *pdev); +#else +static void fsl_usb_recover_hcd(struct platform_device *pdev) +{; } +#endif +/* + * USB Host1 HS port + */ +static int gpio_usbh1_active(void) +{ + /* Set USBH1_STP to GPIO and toggle it */ + mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO | + IOMUX_CONFIG_SION); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), "usbh1_stp"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1); + + /* Signal only used on MX51-3DS for reset to PHY.*/ + if (machine_is_mx51_3ds()) { + mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), "eim_d17"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 1); + } + + msleep(100); + + return 0; +} + +static void gpio_usbh1_inactive(void) +{ + /* Signal only used on MX51-3DS for reset to PHY.*/ + if (machine_is_mx51_3ds()) { + gpio_free(IOMUX_TO_GPIO(MX51_PIN_EIM_D17)); + mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_GPIO); + } + + mxc_free_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO); + gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP)); +} + +static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + pr_debug("host1, %s, enable is %d\n", __func__, enable); + if (enable) + USBCTRL |= UCTRL_H1WIE; + else { + USBCTRL &= ~UCTRL_H1WIE; + /* The interrupt must be disabled for at least 3 + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + pr_debug("host1, %s, enable is %d\n", __func__, enable); + if (enable) { + UH1_PORTSC1 |= PORTSC_PHCD; + } else { + UH1_PORTSC1 &= ~PORTSC_PHCD; + } +} + +static void usbh1_clock_gate(bool on) +{ + pr_debug("%s: on is %d\n", __func__, on); + if (on) { + clk_enable(usb_ahb_clk); + clk_enable(usb_oh3_clk); + clk_enable(usb_phy2_clk); + } else { + clk_disable(usb_phy2_clk); + clk_disable(usb_oh3_clk); + clk_disable(usb_ahb_clk); + } +} + +static enum usb_wakeup_event _is_usbh1_wakeup(struct fsl_usb2_platform_data *pdata) +{ + int wakeup_req = USBCTRL & UCTRL_H1WIR; + + if (wakeup_req) + return !WAKEUP_EVENT_INVALID; + + return WAKEUP_EVENT_INVALID; +} + +static void h1_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _wake_up_enable(pdata, false); + _phy_lowpower_suspend(pdata, false); + fsl_usb_recover_hcd(&mxc_usbh1_device); +} + +static void usbh1_wakeup_event_clear(void) +{ + int wakeup_req = USBCTRL & UCTRL_H1WIR; + + if (wakeup_req != 0) { + printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC); + /* Disable H1WIE to clear H1WIR, wait 3 clock + * cycles of standly clock(32KHz) + */ + USBCTRL &= ~UCTRL_H1WIE; + udelay(100); + USBCTRL |= UCTRL_H1WIE; + } +} +static int fsl_usb_host_init_ext(struct platform_device *pdev) +{ + int ret; + struct clk *usb_clk; + + /* the usb_ahb_clk will be enabled in usb_otg_init */ + usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + + if (cpu_is_mx53()) { + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usb_clk); + usb_oh3_clk = usb_clk; + + usb_clk = clk_get(NULL, "usb_phy2_clk"); + clk_enable(usb_clk); + usb_phy2_clk = usb_clk; + } else if (cpu_is_mx50()) { + usb_clk = clk_get(NULL, "usb_phy2_clk"); + clk_enable(usb_clk); + usb_phy2_clk = usb_clk; + } else if (cpu_is_mx51()) { + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usb_clk); + usb_oh3_clk = usb_clk; + } + + ret = fsl_usb_host_init(pdev); + if (ret) + return ret; + + if (cpu_is_mx51()) { + /* setback USBH1_STP to be function */ + mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST | + PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | + PAD_CTL_DRV_VOT_LOW); + gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP)); + } + + /* disable remote wakeup irq */ + USBCTRL &= ~UCTRL_H1WIE; + return 0; +} + +static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + if (cpu_is_mx53()) { + clk_disable(usb_oh3_clk); + clk_put(usb_oh3_clk); + + clk_disable(usb_phy2_clk); + clk_put(usb_phy2_clk); + } else if (cpu_is_mx50()) { + clk_disable(usb_phy2_clk); + clk_put(usb_phy2_clk); + } else if (cpu_is_mx51()) { + clk_disable(usb_oh3_clk); + clk_put(usb_oh3_clk); + } + + fsl_usb_host_uninit(pdata); + /* usb_ahb_clk will be disabled at usb_common.c */ + clk_put(usb_ahb_clk); +} + +static struct fsl_usb2_platform_data usbh1_config = { + .name = "Host 1", + .platform_init = fsl_usb_host_init_ext, + .platform_uninit = fsl_usb_host_uninit_ext, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, + .power_budget = 500, /* 500 mA max power */ + .wake_up_enable = _wake_up_enable, + .usb_clock_for_pm = usbh1_clock_gate, + .phy_lowpower_suspend = _phy_lowpower_suspend, + .is_wakeup_event = _is_usbh1_wakeup, + .wakeup_handler = h1_wakeup_handler, + .transceiver = "utmi", +}; +static struct fsl_usb2_wakeup_platform_data usbh1_wakeup_config = { + .name = "USBH1 wakeup", + .usb_clock_for_pm = usbh1_clock_gate, + .usb_pdata = {&usbh1_config, NULL, NULL}, + .usb_wakeup_exhandle = usbh1_wakeup_event_clear, +}; + +void mx5_set_host1_vbus_func(driver_vbus_func driver_vbus) +{ + usbh1_config.platform_driver_vbus = driver_vbus; +} + +void __init mx5_usbh1_init(void) +{ + if (cpu_is_mx51()) { + usbh1_config.phy_mode = FSL_USB2_PHY_ULPI; + usbh1_config.transceiver = "isp1504"; + usbh1_config.gpio_usb_active = gpio_usbh1_active; + usbh1_config.gpio_usb_inactive = gpio_usbh1_inactive; + } + mxc_register_device(&mxc_usbh1_device, &usbh1_config); + usbh1_config.wakeup_pdata = &usbh1_wakeup_config; + mxc_register_device(&mxc_usbh1_wakeup_device, &usbh1_wakeup_config); +} + diff --git a/arch/arm/mach-mx5/usb_h2.c b/arch/arm/mach-mx5/usb_h2.c new file mode 100644 index 000000000000..516c62dea814 --- /dev/null +++ b/arch/arm/mach-mx5/usb_h2.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include "usb.h" +#include "iomux.h" +#include "mx51_pins.h" + +#ifdef CONFIG_USB_EHCI_ARC +extern void fsl_usb_recover_hcd(struct platform_device *pdev); +#else +static void fsl_usb_recover_hcd(struct platform_device *pdev) +{; } +#endif +/* + * USB Host2 HS port + */ +static int gpio_usbh2_active(void) +{ + /* Set USBH2_STP to GPIO and toggle it */ + mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_GPIO); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), "eim_a26"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1); + + msleep(100); + + return 0; +} + +static void gpio_usbh2_inactive(void) +{ + gpio_free(IOMUX_TO_GPIO(MX51_PIN_EIM_A26)); + mxc_free_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_GPIO); +} + +static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + printk(KERN_DEBUG "host2, %s, enable is %d\n", __func__, enable); + if (enable) + USBCTRL_HOST2 |= UCTRL_H2WIE; + else { + USBCTRL_HOST2 &= ~UCTRL_H2WIE; + /* The interrupt must be disabled for at least 3 + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable) +{ + printk(KERN_DEBUG "host2, %s, enable is %d\n", __func__, enable); + if (enable) { + UH2_PORTSC1 |= PORTSC_PHCD; + } else { + UH2_PORTSC1 &= ~PORTSC_PHCD; + } +} + +static void fsl_usbh2_clock_gate(bool on) +{ + struct clk *usb_clk; + if (on) { + usb_clk = clk_get(NULL, "usb_ahb_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + } else { + usb_clk = clk_get(NULL, "usb_ahb_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + } +} + +static enum usb_wakeup_event _is_usbh2_wakeup(struct fsl_usb2_platform_data *pdata) +{ + int wakeup_req = USBCTRL & UCTRL_H2WIR; + + if (wakeup_req) + return !WAKEUP_EVENT_INVALID; + + return WAKEUP_EVENT_INVALID; +} + +static void h2_wakeup_handler(struct fsl_usb2_platform_data *pdata) +{ + _wake_up_enable(pdata, false); + _phy_lowpower_suspend(pdata, false); + fsl_usb_recover_hcd(&mxc_usbh2_device); +} + +static void usbh2_wakeup_event_clear(void) +{ + int wakeup_req = USBCTRL & UCTRL_H2WIR; + + if (wakeup_req != 0) { + printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC); + /* Disable H2WIE to clear H2WIR, wait 3 clock + * cycles of standly clock(32KHz) + */ + USBCTRL &= ~UCTRL_H2WIE; + udelay(100); + USBCTRL |= UCTRL_H2WIE; + } +} +static int fsl_usb_host_init_ext(struct platform_device *pdev) +{ + int ret = 0; + struct clk *usb_clk; + + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + /* on mx53, there is a hardware limitation that when switch the host2's clk mode + * ,usb phy1 clk must be on, after finish switching this clk can be off */ + if (cpu_is_mx53()) { + usb_clk = clk_get(NULL, "usb_phy1_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + } + + ret = fsl_usb_host_init(pdev); + + if (cpu_is_mx53()) { + usb_clk = clk_get(NULL, "usb_phy1_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + } + + /* setback USBH2_STP to be function */ + mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2); + + return ret; +} + +static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata) +{ + struct clk *usb_clk; + + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + + fsl_usb_host_uninit(pdata); +} + +static struct fsl_usb2_platform_data usbh2_config = { + .name = "Host 2", + .platform_init = fsl_usb_host_init_ext, + .platform_uninit = fsl_usb_host_uninit_ext, + .operating_mode = FSL_USB2_MPH_HOST, + .phy_mode = FSL_USB2_PHY_ULPI, + .power_budget = 500, /* 500 mA max power */ + .wake_up_enable = _wake_up_enable, + .usb_clock_for_pm = fsl_usbh2_clock_gate, + .phy_lowpower_suspend = _phy_lowpower_suspend, + .gpio_usb_active = gpio_usbh2_active, + .gpio_usb_inactive = gpio_usbh2_inactive, + .is_wakeup_event = _is_usbh2_wakeup, + .wakeup_handler = h2_wakeup_handler, + .transceiver = "isp1504", +}; +static struct fsl_usb2_wakeup_platform_data usbh2_wakeup_config = { + .name = "USBH2 wakeup", + .usb_clock_for_pm = fsl_usbh2_clock_gate, + .usb_pdata = {&usbh2_config, NULL, NULL}, + .usb_wakeup_exhandle = usbh2_wakeup_event_clear, +}; +void __init mx5_usbh2_init(void) +{ + usbh2_config.wakeup_pdata = &usbh2_wakeup_config; + mxc_register_device(&mxc_usbh2_device, &usbh2_config); + mxc_register_device(&mxc_usbh2_wakeup_device, &usbh2_wakeup_config); +} diff --git a/arch/arm/mach-mx5/wfi.S b/arch/arm/mach-mx5/wfi.S new file mode 100644 index 000000000000..a6e373f4e08b --- /dev/null +++ b/arch/arm/mach-mx5/wfi.S @@ -0,0 +1,426 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +#define ARM_CTRL_DCACHE 1 << 2 +#define ARM_AUXCR_L2EN 1 << 1 +/* + * cpu_cortexa8_do_idle() + * + * Idle the processor (eg, wait for interrupt). + * + * IRQs are already disabled. + */ +ENTRY(cpu_cortexa8_do_idle) + + mrc p15, 0, r1, c1, c0, 1 @ R1 = auxiliary control reg + ands r2, r1, #ARM_AUXCR_L2EN @ Check if L2 is disabled + beq SkipL2Access + + mrc p15, 0, r2, c1, c0, 0 @ R2 = system control reg + bic r2, r2, #ARM_CTRL_DCACHE @ Disable DCache + mcr p15, 0, r2, c1, c0, 0 @ Update system control reg + + bic r1, r1, #ARM_AUXCR_L2EN @ Disable L2 cache + mcr p15, 0, r1, c1, c0, 1 @ Update aux control reg + + ldr r1, =(0x0 << 6) @ A[6] = 0 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x00] @ Save tag info + + ldr r1, =(0x1 << 6) @ A[6] = 1 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x04] @ Save tag info + + ldr r1, =(0x0 << 3) @ A[6:3] = b0000 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x08] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x0C] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x10] @ Store data info + + ldr r1, =(0x1 << 3) @ A[6:3] = b0001 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x14] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x18] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x1C] @ Store data info + + ldr r1, =(0x2 << 3) @ A[6:3] = b0010 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x20] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x24] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x28] @ Store data info + + ldr r1, =(0x3 << 3) @ A[6:3] = b0011 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x2C] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x30] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x34] @ Store data info + + ldr r1, =(0x4 << 3) @ A[6:3] = b0100 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x38] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x3C] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x40] @ Store data info + + ldr r1, =(0x5 << 3) @ A[6:3] = b0101 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x44] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x48] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x4C] @ Store data info + + ldr r1, =(0x6 << 3) @ A[6:3] = b0110 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x50] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x54] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x58] @ Store data info + + ldr r1, =(0x7 << 3) @ A[6:3] = b0111 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x5C] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x60] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x64] @ Store data info + + ldr r1, =(0x8 << 3) @ A[6:3] = b1000 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x68] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x6C] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x70] @ Store data info + + ldr r1, =(0x9 << 3) @ A[6:3] = b1001 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x74] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x78] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x7C] @ Store data info + + ldr r1, =(0xA << 3) @ A[6:3] = b1010 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x80] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x84] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x88] @ Store data info + + ldr r1, =(0xB << 3) @ A[6:3] = b1011 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x8C] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x90] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0x94] @ Store data info + + ldr r1, =(0xC << 3) @ A[6:3] = b1100 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0x98] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0x9C] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0xA0] @ Store data info + + ldr r1, =(0xD << 3) @ A[6:3] = b1101 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xA4] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0xA8] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0xAC] @ Store data info + + ldr r1, =(0xE << 3) @ A[6:3] = b1110 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xB0] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0xB4] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0xB8] @ Store data info + + ldr r1, =(0xF << 3) @ A[6:3] = b1111 + mcr p15, 0, r1, c15, c9, 3 @ Read L2 Data RAM into L2 data 0-2 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xBC] @ Store data info + mrc p15, 0, r2, c15, c8, 1 @ Move L2 data 1 register to R2 + str r2, [r0, #0xC0] @ Store data info + mrc p15, 0, r2, c15, c8, 5 @ Move L2 data 2 register to R2 + str r2, [r0, #0xC4] @ Store data info + + ldr r1, =(0x2 << 29) | (0x0 << 6) @ WAY = A[31:29] = 2, A[6] = 0 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xC8] @ Save tag info + + ldr r1, =(0x2 << 29) | (0x1 << 6) @ WAY = A[31:29] = 2, A[6] = 1 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xCC] @ Save tag info + + ldr r1, =(0x4 << 29) | (0x0 << 6) @ WAY = A[31:29] = 4, A[6] = 0 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xD0] @ Save tag info + + ldr r1, =(0x4 << 29) | (0x1 << 6) @ WAY = A[31:29] = 4, A[6] = 1 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xD4] @ Save tag info + + ldr r1, =(0x6 << 29) | (0x0 << 6) @ WAY = A[31:29] = 6, A[6] = 0 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xD8] @ Save tag info + + ldr r1, =(0x6 << 29) | (0x1 << 6) @ WAY = A[31:29] = 6, A[6] = 1 + mcr p15, 0, r1, c15, c9, 2 @ Read L2 tag RAM into L2 data 0 register + mrc p15, 0, r2, c15, c8, 0 @ Move L2 data 0 register to R2 + str r2, [r0, #0xDC] @ Save tag info + + .long 0xe320f003 @ Opcode for WFI + + ldr r1, =(0x0 << 6) @ A[6] = 0 + ldr r2, [r0, #0x00] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x1 << 6) @ A[6] = 1 + ldr r2, [r0, #0x04] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x0 << 3) @ A[6:3] = b0000 + ldr r2, [r0, #0x08] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x0C] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x10] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x1 << 3) @ A[6:3] = b0001 + ldr r2, [r0, #0x14] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x18] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x1C] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x2 << 3) @ A[6:3] = b0010 + ldr r2, [r0, #0x20] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x24] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x28] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x3 << 3) @ A[6:3] = b0011 + ldr r2, [r0, #0x2C] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x30] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x34] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x4 << 3) @ A[6:3] = b0100 + ldr r2, [r0, #0x38] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x3C] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x40] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x5 << 3) @ A[6:3] = b0101 + ldr r2, [r0, #0x44] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x48] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x4C] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x6 << 3) @ A[6:3] = b0110 + ldr r2, [r0, #0x50] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x54] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x58] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x7 << 3) @ A[6:3] = b0111 + ldr r2, [r0, #0x5C] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x60] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x64] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x8 << 3) @ A[6:3] = b1000 + ldr r2, [r0, #0x68] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x6C] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x70] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x9 << 3) @ A[6:3] = b1001 + ldr r2, [r0, #0x74] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x78] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x7C] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xA << 3) @ A[6:3] = b1010 + ldr r2, [r0, #0x80] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x84] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x88] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xB << 3) @ A[6:3] = b1011 + ldr r2, [r0, #0x8C] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x90] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0x94] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xC << 3) @ A[6:3] = b1100 + ldr r2, [r0, #0x98] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0x9C] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0xA0] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xD << 3) @ A[6:3] = b1101 + ldr r2, [r0, #0xA4] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0xA8] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0xAC] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xE << 3) @ A[6:3] = b1110 + ldr r2, [r0, #0xB0] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0xB4] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0xB8] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0xF << 3) @ A[6:3] = b1111 + ldr r2, [r0, #0xBC] @ Load data info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + ldr r2, [r0, #0xC0] @ Load data info + mcr p15, 0, r2, c15, c8, 1 @ Move R2 to L2 data 1 register + ldr r2, [r0, #0xC4] @ Load data info + mcr p15, 0, r2, c15, c8, 5 @ Move R2 to L2 data 2 register + mcr p15, 0, r1, c15, c8, 3 @ Write L2 data 0-2 registers to L2 data RAM + + ldr r1, =(0x2 << 29) | (0x0 << 6) @ WAY = A[31:29] = 2, A[6] = 0 + ldr r2, [r0, #0xC8] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x2 << 29) | (0x1 << 6) @ WAY = A[31:29] = 2, A[6] = 1 + ldr r2, [r0, #0xCC] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x4 << 29) | (0x0 << 6) @ WAY = A[31:29] = 4, A[6] = 0 + ldr r2, [r0, #0xD0] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x4 << 29) | (0x1 << 6) @ WAY = A[31:29] = 4, A[6] = 1 + ldr r2, [r0, #0xD4] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x6 << 29) | (0x0 << 6) @ WAY = A[31:29] = 6, A[6] = 0 + ldr r2, [r0, #0xD8] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + ldr r1, =(0x6 << 29) | (0x1 << 6) @ WAY = A[31:29] = 6, A[6] = 1 + ldr r2, [r0, #0xDC] @ Load tag info + mcr p15, 0, r2, c15, c8, 0 @ Move R2 to L2 data 0 register + mcr p15, 0, r1, c15, c8, 2 @ Write L2 data 0 register to L2 tag RAM + + mrc p15, 0, r1, c1, c0, 1 @ R1 = auxiliary control reg + orr r1, r1, #ARM_AUXCR_L2EN @ Enable L2 cache + mcr p15, 0, r1, c1, c0, 1 @ Update aux control reg + + mrc p15, 0, r2, c1, c0, 0 @ R2 = system control reg + orr r2, r2, #ARM_CTRL_DCACHE @ Enable DCache + mcr p15, 0, r2, c1, c0, 0 @ Update system control reg + + b Done + +SkipL2Access: + .long 0xe320f003 @ Opcode for WFI + +Done: + mov pc, lr + + .type cortexa8_idle_workaround, #object +ENTRY(cortexa8_idle_workaround) + .word cpu_cortexa8_do_idle + .size cortexa8_idle_workaround, . - cortexa8_idle_workaround diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 9982eb385c0f..cf793e89315d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -26,6 +26,7 @@ #define CACHE_LINE_SIZE 32 static void __iomem *l2x0_base; +static unsigned long l2x0_aux; static DEFINE_SPINLOCK(l2x0_lock); static uint32_t l2x0_way_mask; /* Bitmask of active ways */ @@ -115,6 +116,18 @@ static inline void l2x0_inv_all(void) spin_unlock_irqrestore(&l2x0_lock, flags); } +static void l2x0_flush_all(void) +{ + unsigned long flags; + + /* clean and invalidate all ways */ + spin_lock_irqsave(&l2x0_lock, flags); + writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY); + cache_wait(l2x0_base + L2X0_CLEAN_INV_WAY, 0xff); + cache_sync(); + spin_unlock_irqrestore(&l2x0_lock, flags); +} + static void l2x0_inv_range(unsigned long start, unsigned long end) { void __iomem *base = l2x0_base; @@ -220,6 +233,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) aux &= aux_mask; aux |= aux_val; + l2x0_aux = aux; /* Determine the number of ways */ switch (cache_id & L2X0_CACHE_ID_PART_MASK) { @@ -268,3 +282,23 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", ways, cache_id, aux); } + +void l2x0_disable(void) +{ + if (readl(l2x0_base + L2X0_CTRL) + && !(readl(l2x0_base + L2X0_DEBUG_CTRL) & 0x2)) { + l2x0_flush_all(); + writel(0, l2x0_base + L2X0_CTRL); + l2x0_flush_all(); + } +} + +void l2x0_enable(void) +{ + if (!readl(l2x0_base + L2X0_CTRL)) { + writel(l2x0_aux, l2x0_base + L2X0_AUX_CTRL); + l2x0_inv_all(); + /* enable L2X0 */ + writel(1, l2x0_base + L2X0_CTRL); + } +} diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 7a5337ed7d68..7a59aa9f3bdb 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -183,6 +183,22 @@ __v6_setup: mrc p15, 0, r0, c1, c0, 0 @ read control register bic r0, r0, r5 @ clear bits them orr r0, r0, r6 @ set them +#ifdef CONFIG_ARM_ERRATA_364296 + /* Workaround for the 364296 ARM1136 r0pX errata (possible cache data + * corruption with hit-under-miss enabled). The conditional code below + * (setting the undocumented bit 31 in the auxiliary control register + * and the FI bit in the control register) disables hit-under-miss + * without putting the processor into full low interrupt latency mode. + */ + ldr r6, =0x4107b360 @ id for ARM1136 r0pX + mrc p15, 0, r5, c0, c0, 0 @ get processor id + bic r5, r5, #0xf @ mask out part bits [3:0] + teq r5, r6 @ check for the faulty core + mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg + orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 + mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg + orreq r0, r0, #(1 << 21) @ low interrupt latency configuration +#endif mov pc, lr @ return to head.S:__ret /* diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c new file mode 100644 index 000000000000..9770493fcfa8 --- /dev/null +++ b/arch/arm/plat-mxc/3ds_debugboard.c @@ -0,0 +1,205 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Jason Wang + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR(n) (n + 0x0) +/* External UART */ +#define UARTA_BASE_ADDR(n) (n + 0x8000) +#define UARTB_BASE_ADDR(n) (n + 0x10000) + +#define BOARD_IO_ADDR(n) (n + 0x20000) +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_INTERNAL_IRQS) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_MAX_EXP_IO_LINES 16 + +/* interrupts like external uart , external ethernet etc*/ +#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0) +#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1) +#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2) +#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3) +#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4) + +static void __iomem *brd_io; +static void expio_ack_irq(u32 irq); + +static struct resource smsc911x_resources[] = { + { + .flags = IORESOURCE_MEM, + } , { + .start = EXPIO_INT_ENET, + .end = EXPIO_INT_ENET, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, +}; + +static struct platform_device smsc_lan9217_device = { + .name = "smsc911x", + .id = 0, + .dev = { + .platform_data = &smsc911x_config, + }, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, +}; + +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) +{ + u32 imr_val; + u32 int_valid; + u32 expio_irq; + + desc->chip->mask(irq); /* irq = gpio irq number */ + + imr_val = __raw_readw(brd_io + INTR_MASK_REG); + int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; + + expio_irq = MXC_BOARD_IRQ_START; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + struct irq_desc *d; + if ((int_valid & 1) == 0) + continue; + d = irq_desc + expio_irq; + if (unlikely(!(d->handle_irq))) + pr_err("\nEXPIO irq: %d unhandled\n", expio_irq); + else + d->handle_irq(expio_irq, d); + } + + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * Irq is an expio virtual irq number + */ +static void expio_mask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg |= (1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static void expio_ack_irq(u32 irq) +{ + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + __raw_writew(1 << expio, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + expio_mask_irq(irq); +} + +static void expio_unmask_irq(u32 irq) +{ + u16 reg; + u32 expio = MXC_IRQ_TO_EXPIO(irq); + + reg = __raw_readw(brd_io + INTR_MASK_REG); + reg &= ~(1 << expio); + __raw_writew(reg, brd_io + INTR_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, +}; + +int __init mxc_expio_init(u32 base, u32 p_irq) +{ + int i; + + brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); + if (brd_io == NULL) + return -ENOMEM; + + if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { + pr_info("3-Stack Debug board not detected\n"); + iounmap(brd_io); + brd_io = NULL; + return -ENODEV; + } + + pr_info("3-Stack Debug board detected, rev = 0x%04X\n", + readw(brd_io + CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq"); + gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq)); + + /* disable the interrupt and clear the status */ + __raw_writew(0, brd_io + INTR_MASK_REG); + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); + __raw_writew(0, brd_io + INTR_RESET_REG); + __raw_writew(0x1F, brd_io + INTR_MASK_REG); + for (i = MXC_EXP_IO_BASE; + i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(p_irq, IRQF_TRIGGER_LOW); + set_irq_chained_handler(p_irq, mxc_expio_irq_handler); + + /* Register Lan device on the debugboard */ + smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); + smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; +#ifdef CONFIG_FEC + smsc_lan9217_device.id = 1; +#endif + platform_device_register(&smsc_lan9217_device); + + return 0; +} diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 7f7ad6f289bd..926379f3f99f 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -1,5 +1,7 @@ if ARCH_MXC +source "arch/arm/plat-mxc/devices/Kconfig" + menu "Freescale MXC Implementations" choice @@ -32,7 +34,12 @@ config ARCH_MX3 bool "MX3-based" select CPU_V6 help - This enables support for systems based on the Freescale i.MX3 family + This enables support for systems based on the Freescale i.MX31 and i.MX32 + +config ARCH_MX37 + bool "MX37-based" + help + This enables support for systems based on Freescale i.MX37 config ARCH_MXC91231 bool "MXC91231-based" @@ -57,6 +64,86 @@ source "arch/arm/mach-mx5/Kconfig" endmenu +config IRAM_ALLOC + bool + default y + select GENERIC_ALLOCATOR + +config MXC_DSP_BRINGUP + bool + depends on ARCH_MXC + +config ARCH_HAS_EVTMON + bool + depends on ARCH_MXC + +config MXC_EMMA + bool + depends on ARCH_MXC + +config MXC_FB_IRAM + bool + depends on ARCH_MXC + +config DMA_ZONE_SIZE + int "DMA memory zone size" + range 0 96 + default 24 + help + This is the size in MB for the DMA zone. The DMA zone is used for + dedicated memory for large contiguous video buffers + +# set iff we need the 1504 transceiver code +config ISP1504_MXC + bool + default y + +# set iff we need the UTMI transceiver code +config UTMI_MXC + bool + default y + depends on ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX5 + +# set iff we need the 1301 transceiver code +config ISP1301_MXC + bool + select I2C_MXC + +# set iff we need the mx13783 transceiver code +config MC13783_MXC + bool + select SPI_MXC + +choice + prompt "Select serial USB transceiver mode" + depends on ISP1301_MXC || MC13783_MXC + default MXC_USB_SU6 + +config MXC_USB_SU6 + bool "Single Ended Unidirectional Mode" + help + If you say yes to this option, the serial tranceiver operates in SU6 mode. + This option will work for either the Freescale MC13783 or Philips ISP1301 + transceiver. + +config MXC_USB_SB3 + bool "Single Ended Bidirectional Mode" + help + If you say yes to this option, the serial tranceiver operates in SB3 mode. + Not recommended for the Freescale MC13783. + +config MXC_USB_DU6 + bool "Differential Unidirectional Mode" + help + If you say yes to this option, the serial tranceiver operates in DU6 mode. + +config MXC_USB_DB4 + bool "Differential Bidirectional Mode" + help + If you say yes to this option, the serial tranceiver operates in DB4 mode. + +endchoice + config MXC_IRQ_PRIOR bool "Use IRQ priority" help @@ -81,12 +168,27 @@ config MXC_PWM help Enable support for the i.MX PWM controller(s). +config MXC_DEBUG_BOARD + bool "Enable MXC debug board(for 3-stack)" + help + The debug board is an integral part of the MXC 3-stack(PDK) + platforms, it can be attached or removed from the peripheral + board. On debug board, several debug devices(ethernet, UART, + buttons, LEDs and JTAG) are implemented. Between the MCU and + these devices, a CPLD is added as a bridge which performs + data/address de-multiplexing and decode, signal level shift, + interrupt control and various board functions. + config MXC_ULPI bool config ARCH_HAS_RNGA bool +config ARCH_HAS_RNGC + bool + depends on ARCH_MXC + config IMX_HAVE_IOMUX_V1 bool @@ -99,4 +201,16 @@ config ARCH_MXC_AUDMUX_V1 config ARCH_MXC_AUDMUX_V2 bool +config MXC_DVFS_PER + bool "Enable DVFS Peripheral" + depends on ARCH_MX37 || ARCH_MX5 + help + Select this if you want to enable HW supported peripheral frequency scaling. + +config MXC_ZQ_CALIBRATION + bool "Enable mDDR/LPDDR2/DDR2 ZQ calibration" + depends on ARCH_MX50 + help + Select this if you're sure it's needed. + endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 895bc3c5e0c0..4319b330b691 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -3,10 +3,16 @@ # # Common support -obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o +obj-y :=cpu.o cpu_common.o system.o gpio.o clock.o snoop.o io.o time.o devices.o usb_common.o usb_wakeup.o + +obj-$(CONFIG_IRAM_ALLOC) += iram.o # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) +ifeq ($(CONFIG_MXC_TZIC),y) obj-$(CONFIG_MXC_TZIC) += tzic.o +else +obj-y += irq.o +endif obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o @@ -17,7 +23,34 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o +obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o ifdef CONFIG_SND_IMX_SOC obj-y += ssi-fiq.o obj-y += ssi-fiq-ksym.o endif + +ifneq ($(CONFIG_ARCH_MX27),y) +obj-y += sdma/ +endif + +obj-$(CONFIG_ARCH_MX37) += dptc.o dvfs_core.o +obj-$(CONFIG_ARCH_MX5) += dvfs_core.o +obj-$(CONFIG_ARCH_MX5) += ahci_sata.o + +# CPU FREQ support +obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o + +# DVFS-PER support +obj-$(CONFIG_MXC_DVFS_PER) += dvfs_per.o + +# USB support +obj-$(CONFIG_ISP1504_MXC) += isp1504xc.o +obj-$(CONFIG_ISP1301_MXC) += isp1301xc.o +obj-$(CONFIG_MC13783_MXC) += mc13783_xc.o +obj-$(CONFIG_UTMI_MXC) += utmixc.o +obj-$(CONFIG_USB) += serialxc.o + +# ZQ calibration +obj-$(CONFIG_MXC_ZQ_CALIBRATION) += zq_calib.o + +obj-y += devices/ diff --git a/arch/arm/plat-mxc/ahci_sata.c b/arch/arm/plat-mxc/ahci_sata.c new file mode 100644 index 000000000000..23aa0ec13160 --- /dev/null +++ b/arch/arm/plat-mxc/ahci_sata.c @@ -0,0 +1,589 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*****************************************************************************\ + * * + * FSL SATA AHCI low level functions * + * return value 1 failure, 0 success * + * * +\*****************************************************************************/ +enum { + HOST_CAP = 0x00, + HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ + HOST_PORTS_IMPL = 0x0c, + HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ + /* Offest used to control the MPLL input clk */ + PHY_CR_CLOCK_FREQ_OVRD = 0x12, + /* Port0 PHY Control */ + PORT_PHY_CTL = 0x178, + /* PORT_PHY_CTL bits */ + PORT_PHY_CTL_CAP_ADR_LOC = 0x10000, + PORT_PHY_CTL_CAP_DAT_LOC = 0x20000, + PORT_PHY_CTL_WRITE_LOC = 0x40000, + PORT_PHY_CTL_READ_LOC = 0x80000, + /* Port0 PHY Status */ + PORT_PHY_SR = 0x17c, + /* PORT_PHY_SR */ + PORT_PHY_STAT_DATA_LOC = 0, + PORT_PHY_STAT_ACK_LOC = 18, + /* SATA PHY Register */ + SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001, + SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008, + SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009, + SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A, + SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017, +}; + +static int write_phy_ctl_ack_polling(u32 data, void __iomem *mmio, + int max_iterations, u32 exp_val) +{ + u32 i, val; + + writel(data, mmio + PORT_PHY_CTL); + + for (i = 0; i < max_iterations + 1; i++) { + val = readl(mmio + PORT_PHY_SR); + val = (val >> PORT_PHY_STAT_ACK_LOC) & 0x1; + if (val == exp_val) + return 0; + if (i == max_iterations) { + printk(KERN_ERR "Wait for CR ACK error!\n"); + return 1; + } + msleep(1); + } + return 0; +} + +static int sata_phy_cr_addr(u32 addr, void __iomem *mmio) +{ + u32 temp_wr_data; + + /* write addr */ + temp_wr_data = addr; + writel(temp_wr_data, mmio + PORT_PHY_CTL); + + /* capture addr */ + temp_wr_data |= PORT_PHY_CTL_CAP_ADR_LOC; + + /* wait for ack */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 1)) + return 1; + + /* deassert cap addr */ + temp_wr_data &= 0xffff; + + /* wait for ack de-assetion */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 0)) + return 1; + + return 0; +} + +static int sata_phy_cr_write(u32 data, void __iomem *mmio) +{ + u32 temp_wr_data; + + /* write data */ + temp_wr_data = data; + + /* capture data */ + temp_wr_data |= PORT_PHY_CTL_CAP_DAT_LOC; + + /* wait for ack */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 1)) + return 1; + + /* deassert cap data */ + temp_wr_data &= 0xffff; + + /* wait for ack de-assetion */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 0)) + return 1; + + /* assert wr signal */ + temp_wr_data |= PORT_PHY_CTL_WRITE_LOC; + + /* wait for ack */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 1)) + return 1; + + /* deassert wr _signal */ + temp_wr_data = 0x0; + + /* wait for ack de-assetion */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 0)) + return 1; + + return 0; +} + +static int sata_phy_cr_read(u32 *data, void __iomem *mmio) +{ + u32 temp_rd_data, temp_wr_data; + + /* assert rd signal */ + temp_wr_data = PORT_PHY_CTL_READ_LOC; + + /* wait for ack */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 1)) + return 1; + + /* after got ack return data */ + temp_rd_data = readl(mmio + PORT_PHY_SR); + *data = (temp_rd_data & 0xffff); + + /* deassert rd _signal */ + temp_wr_data = 0x0 ; + + /* wait for ack de-assetion */ + if (write_phy_ctl_ack_polling(temp_wr_data, mmio, 100, 0)) + return 1; + + return 0; +} + +/* SATA AHCI temperature monitor */ +static ssize_t sata_ahci_current_tmp(struct device *dev, struct device_attribute + *devattr, char *buf) +{ + void __iomem *mmio; + u32 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, adc_out_reg; + u32 str1, str2, str3, str4, read_sum, index; + int m1, m2, a, temp; + + /* map the IO addr */ + mmio = ioremap(MX53_SATA_BASE_ADDR, SZ_2K); + if (mmio == NULL) { + printk(KERN_ERR "Failed to map SATA REGS\n"); + return 1; + } + + /* check rd-wr to reg */ + read_sum = 0; + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio); + sata_phy_cr_write(read_sum, mmio); + sata_phy_cr_read(&read_sum, mmio); + if ((read_sum & 0xffff) != 0) + printk(KERN_ERR "Read/Write REG error, 0x%x!\n", read_sum); + + sata_phy_cr_write(0x5A5A, mmio); + sata_phy_cr_read(&read_sum, mmio); + if ((read_sum & 0xffff) != 0x5A5A) + printk(KERN_ERR "Read/Write REG error, 0x%x!\n", read_sum); + + sata_phy_cr_write(0x1234, mmio); + sata_phy_cr_read(&read_sum, mmio); + if ((read_sum & 0xffff) != 0x1234) + printk(KERN_ERR "Read/Write REG error, 0x%x!\n", read_sum); + + /* stat temperature test */ + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); + sata_phy_cr_read(&mpll_test_reg, mmio); + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); + sata_phy_cr_read(&rtune_ctl_reg, mmio); + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); + sata_phy_cr_read(&dac_ctl_reg, mmio); + + /* mpll_tst.meas_iv ([12:2]) */ + str1 = (mpll_test_reg >> 2) & 0x7FF; + /* rtune_ctl.mode ([1:0]) */ + str2 = (rtune_ctl_reg) & 0x3; + /* dac_ctl.dac_mode ([14:12]) */ + str3 = (dac_ctl_reg >> 12) & 0x7; + /* rtune_ctl.sel_atbp ([4]) */ + str4 = (rtune_ctl_reg >> 4); + + /* Caculate the m1 */ + /* mpll_tst.meas_iv */ + mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2; + /* rtune_ctl.mode */ + rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1); + /* dac_ctl.dac_mode */ + dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12; + /* rtune_ctl.sel_atbp */ + rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4; + + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); + sata_phy_cr_write(mpll_test_reg, mmio); + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); + sata_phy_cr_write(dac_ctl_reg, mmio); + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); + sata_phy_cr_write(rtune_ctl_reg, mmio); + + /* two dummy read */ + index = 0; + read_sum = 0; + adc_out_reg = 0; + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_ADC_OUT, mmio); + while (index < 2) { + sata_phy_cr_read(&adc_out_reg, mmio); + /* check if valid */ + if (adc_out_reg & 0x400) + index = index + 1; + read_sum++; + if (read_sum > 100000) { + printk(KERN_ERR "Read REG more than 100000 times!\n"); + break; + } + } + + index = 0; + read_sum = 0; + while (index < 80) { + sata_phy_cr_read(&adc_out_reg, mmio); + if (adc_out_reg & 0x400) { + read_sum = read_sum + (adc_out_reg & 0x3FF); + index = index + 1; + } + } + /* Use the U32 to make 1000 precision */ + m1 = (read_sum * 1000) / 80; + + /* Caculate the m2 */ + /* rtune_ctl.sel_atbp */ + rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4; + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); + sata_phy_cr_write(rtune_ctl_reg, mmio); + + /* two dummy read */ + index = 0; + read_sum = 0; + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_ADC_OUT, mmio); + while (index < 2) { + sata_phy_cr_read(&adc_out_reg, mmio); + /* check if valid */ + if (adc_out_reg & 0x400) + index = index + 1; + read_sum++; + if (read_sum > 100000) { + printk(KERN_ERR "Read REG more than 100000 times!\n"); + break; + } + } + + index = 0; + read_sum = 0; + while (index < 80) { + /* FIX ME dead loop protection??? */ + sata_phy_cr_read(&adc_out_reg, mmio); + if (adc_out_reg & 0x400) { + read_sum = read_sum + (adc_out_reg & 0x3FF); + index = index + 1; + } + } + /* Use the U32 to make 1000 precision */ + m2 = (read_sum * 1000) / 80; + + /* restore the status */ + /* mpll_tst.meas_iv */ + mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2; + /* rtune_ctl.mode */ + rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2); + /* dac_ctl.dac_mode */ + dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12; + /* rtune_ctl.sel_atbp */ + rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4; + + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_MPLL_TST, mmio); + sata_phy_cr_write(mpll_test_reg, mmio); + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_DAC_CTL, mmio); + sata_phy_cr_write(dac_ctl_reg, mmio); + sata_phy_cr_addr(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio); + sata_phy_cr_write(rtune_ctl_reg, mmio); + + /* Compute temperature */ + if (!(m2 / 1000)) + m2 = 1000; + a = (m2 - m1) / (m2 / 1000); + temp = ((((-559) * a) / 1000) * a) / 1000 + (1379) * a / 1000 + (-458); + + iounmap(mmio); + return sprintf(buf, "SATA AHCI current temperature:%d\n", temp); +} + +static DEVICE_ATTR(temperature, S_IRUGO, sata_ahci_current_tmp, NULL); + +static struct attribute *fsl_sata_ahci_attr[] = { + &dev_attr_temperature.attr, + NULL +}; + +static const struct attribute_group fsl_sata_ahci_group = { + .attrs = fsl_sata_ahci_attr, +}; + +/* HW Initialization, if return 1, initialization is failed. */ +static int sata_init(struct device *dev) +{ + void __iomem *mmio; + struct clk *clk; + int ret = 0; + u32 tmpdata; + struct regulator *reg_2v5, *reg_1v3; + + /* AHCI SATA PWR EN */ + if (machine_is_mx53_smd() || machine_is_mx53_loco()) { + /* PWR(VBUCKPERI and VLDO5) on SATA AHCI */ + reg_2v5 = regulator_get(dev, "DA9052_BUCK_PERI"); + ret = IS_ERR(reg_2v5); + if (ret) { + printk(KERN_ERR "AHCI can't get 2v5 PWR.\n"); + goto err0; + } + ret = regulator_enable(reg_2v5); + if (ret) { + printk(KERN_ERR "AHCI: enable 2v5 regulator error.\n"); + goto err0; + } + msleep(25); + + reg_1v3 = regulator_get(dev, "DA9052_LDO5"); + ret = IS_ERR(reg_1v3); + if (ret) { + printk(KERN_ERR "AHCI can't get 1v3 PWR.\n"); + goto err0; + } + ret = regulator_enable(reg_1v3); + if (ret) { + printk(KERN_ERR "AHCI: enable 1v3 regulator error.\n"); + goto err0; + } + msleep(25); + } + + clk = clk_get(dev, "imx_sata_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get clock.\n"); + goto err0; + } + ret = clk_enable(clk); + if (ret) { + printk(KERN_ERR "AHCI can't enable clock.\n"); + goto err0; + } + + /* Get the AHB clock rate, and configure the TIMER1MS reg later */ + clk = clk_get(NULL, "ahb_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get AHB clock.\n"); + goto err0; + } + + mmio = ioremap(MX53_SATA_BASE_ADDR, SZ_2K); + if (mmio == NULL) { + printk(KERN_ERR "Failed to map SATA REGS\n"); + goto err0; + } + + tmpdata = readl(mmio + HOST_CAP); + if (!(tmpdata & HOST_CAP_SSS)) { + tmpdata |= HOST_CAP_SSS; + writel(tmpdata, mmio + HOST_CAP); + } + + if (!(readl(mmio + HOST_PORTS_IMPL) & 0x1)) + writel((readl(mmio + HOST_PORTS_IMPL) | 0x1), + mmio + HOST_PORTS_IMPL); + + tmpdata = clk_get_rate(clk) / 1000; + writel(tmpdata, mmio + HOST_TIMER1MS); + + if (machine_is_mx53_smd() || machine_is_mx53_loco()) { + /* Internal CLK input is used for AHCI */ + iounmap(mmio); + /* Eanble the IIM CLK */ + clk = clk_get(dev, "iim_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get IIM CLK.\n"); + goto err0; + } + ret = clk_enable(clk); + if (ret) { + printk(KERN_ERR "AHCI can't enable IIM clock.\n"); + goto err0; + } + /* SMD or loco boards use the IC internal clk */ + mmio = ioremap(0x63F98000 + 0x180C, SZ_16); + if (mmio == NULL) { + printk(KERN_ERR "Failed to map IIM interface.\n"); + goto err0; + } + /* USB_PHY1 clk, fuse bank4 row3 bit2 */ + writel((readl(mmio) & (~0x7)) | 0x4, mmio); + iounmap(mmio); + /* release IIM clk */ + clk_disable(clk); + clk_put(clk); + clk = clk_get(dev, "usb_phy1_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get USB PHY1 CLK.\n"); + goto err0; + } + ret = clk_enable(clk); + if (ret) { + printk(KERN_ERR "AHCI Can't enable USB PHY1 clock.\n"); + goto err0; + } + } else { + /* External CLK input is used for AHCI */ + /* write addr */ + tmpdata = PHY_CR_CLOCK_FREQ_OVRD; + writel(tmpdata, mmio + PORT_PHY_CTL); + /* capture addr */ + tmpdata |= PORT_PHY_CTL_CAP_ADR_LOC; + /* Wait for ack */ + if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 1)) { + ret = -EIO; + goto err0; + } + + /* deassert cap data */ + tmpdata &= 0xFFFF; + /* wait for ack de-assertion */ + if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 0)) { + ret = -EIO; + goto err0; + } + + /* write data */ + /* Configure the PHY CLK input refer to different OSC + * For 25MHz, pre[13,14]:01, ncy[12,8]:06, + * ncy5[7,6]:02, int_ctl[5,3]:0, prop_ctl[2,0]:7. + * For 50MHz, pre:00, ncy:06, ncy5:02, int_ctl:0, prop_ctl:7. + */ + /* EVK revA */ + if (board_is_mx53_evk_a()) + tmpdata = (0x1 << 15) | (0x1 << 13) | (0x6 << 8) + | (0x2 << 6) | 0x7; + /* Others are 50MHz */ + else + tmpdata = (0x1 << 15) | (0x0 << 13) | (0x6 << 8) + | (0x2 << 6) | 0x7; + + writel(tmpdata, mmio + PORT_PHY_CTL); + /* capture data */ + tmpdata |= PORT_PHY_CTL_CAP_DAT_LOC; + /* wait for ack */ + if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 1)) { + ret = -EIO; + goto err0; + } + + /* deassert cap data */ + tmpdata &= 0xFFFF; + /* wait for ack de-assertion */ + if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 0)) { + ret = -EIO; + goto err0; + } + + /* assert wr signal and wait for ack */ + if (write_phy_ctl_ack_polling(PORT_PHY_CTL_WRITE_LOC, mmio, + 100, 1)) { + ret = -EIO; + goto err0; + } + /* deassert rd _signal and wait for ack de-assertion */ + if (write_phy_ctl_ack_polling(0, mmio, 100, 0)) { + ret = -EIO; + goto err0; + } + iounmap(mmio); + } + msleep(10); + + /* Add the temperature monitor */ + ret = sysfs_create_group(&dev->kobj, &fsl_sata_ahci_group); + if (ret) + sysfs_remove_group(&dev->kobj, &fsl_sata_ahci_group); + +err0: + reg_1v3 = NULL; + reg_2v5 = NULL; + clk = NULL; + return ret; +} + +static void sata_exit(struct device *dev) +{ + struct clk *clk; + struct regulator *reg_2v5, *reg_1v3; + + sysfs_remove_group(&dev->kobj, &fsl_sata_ahci_group); + clk = clk_get(dev, "usb_phy1_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "AHCI can't get USB PHY1 CLK.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } + + clk = clk_get(dev, "imx_sata_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "IMX SATA can't get clock.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } + + /* AHCI SATA PWR disable */ + if (machine_is_mx53_smd() || machine_is_mx53_loco()) { + reg_2v5 = regulator_get(dev, "DA9052_BUCK_PERI"); + if (IS_ERR(reg_2v5)) { + printk(KERN_ERR "AHCI: get 2v5 regulator error.\n"); + reg_2v5 = NULL; + } else { + regulator_disable(reg_2v5); + regulator_put(reg_2v5); + } + + reg_1v3 = regulator_get(dev, "DA9052_LDO5"); + if (IS_ERR(reg_1v3)) { + printk(KERN_ERR "AHCI: get 2v5 regulator error.\n"); + reg_1v3 = NULL; + } else { + regulator_disable(reg_1v3); + regulator_put(reg_1v3); + } + } +} + +struct ahci_platform_data sata_data = { + .init = sata_init, + .exit = sata_exit, +}; + diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 323ff8ccc877..855145692349 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -4,7 +4,7 @@ * Copyright (C) 2004 - 2005 Nokia corporation * Written by Tuukka Tikkanen * Modified for omap shared clock framework by Tony Lindgren - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -25,6 +25,7 @@ /* #define DEBUG */ #include +#include #include #include #include @@ -35,30 +36,117 @@ #include #include #include +#include #include #include - +#include #include #include +#if (defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX37)) +extern int dvfs_core_is_active; +extern int lp_high_freq; +extern int lp_med_freq; +extern int low_bus_freq_mode; +extern int high_bus_freq_mode; +extern int med_bus_freq_mode; +extern int set_high_bus_freq(int high_freq); +extern int set_low_bus_freq(void); +extern int low_freq_bus_used(void); +#else +int dvfs_core_is_active; +#endif + static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); +static DEFINE_SPINLOCK(clockfw_lock); /*------------------------------------------------------------------------- * Standard clock functions defined in include/linux/clk.h *-------------------------------------------------------------------------*/ +/* + * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all + * MXC architectures have switched to using clkdev. + */ +#ifndef CONFIG_COMMON_CLKDEV +/* + * Retrieve a clock by name. + * + * Note that we first try to use device id on the bus + * and clock name. If this fails, we try to use ".". If this fails, + * we try to use clock name only. + * The reference count to the clock's module owner ref count is incremented. + */ +struct clk *clk_get(struct device *dev, const char *id) +{ + struct clk *p, *clk = ERR_PTR(-ENOENT); + int idno; + const char *str; + + if (id == NULL) + return clk; + + if (dev == NULL || dev->bus != &platform_bus_type) + idno = -1; + else + idno = to_platform_device(dev)->id; + + mutex_lock(&clocks_mutex); + + list_for_each_entry(p, &clocks, node) { + if (p->id == idno && + strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + clk = p; + goto found; + } + } + + str = strrchr(id, '.'); + if (str) { + int cnt = str - id; + str++; + idno = simple_strtol(str, NULL, 10); + list_for_each_entry(p, &clocks, node) { + if (p->id == idno && + strlen(p->name) == cnt && + strncmp(id, p->name, cnt) == 0 && + try_module_get(p->owner)) { + clk = p; + goto found; + } + } + } + + list_for_each_entry(p, &clocks, node) { + if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + clk = p; + goto found; + } + } + + printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id); + +found: + mutex_unlock(&clocks_mutex); + + return clk; +} +EXPORT_SYMBOL(clk_get); +#endif + static void __clk_disable(struct clk *clk) { - if (clk == NULL || IS_ERR(clk)) + if (clk == NULL || IS_ERR(clk) || !clk->usecount) return; - __clk_disable(clk->parent); - __clk_disable(clk->secondary); + if (!(--clk->usecount)) { + __clk_disable(clk->parent); + __clk_disable(clk->secondary); - WARN_ON(!clk->usecount); - if (!(--clk->usecount) && clk->disable) - clk->disable(clk); + if (clk->disable) + clk->disable(clk); + } } static int __clk_enable(struct clk *clk) @@ -66,12 +154,13 @@ static int __clk_enable(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return -EINVAL; - __clk_enable(clk->parent); - __clk_enable(clk->secondary); - - if (clk->usecount++ == 0 && clk->enable) - clk->enable(clk); + if (clk->usecount++ == 0) { + __clk_enable(clk->parent); + __clk_enable(clk->secondary); + if (clk->enable) + clk->enable(clk); + } return 0; } @@ -80,14 +169,46 @@ static int __clk_enable(struct clk *clk) */ int clk_enable(struct clk *clk) { + unsigned long flags; int ret = 0; + if (in_interrupt()) { + printk(KERN_ERR " clk_enable cannot be called in an interrupt context\n"); + dump_stack(); + BUG(); + } + if (clk == NULL || IS_ERR(clk)) return -EINVAL; - mutex_lock(&clocks_mutex); + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) + && (clk_get_usecount(clk) == 0)) { +#if (defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX37)) + if (!(clk->flags & + (AHB_HIGH_SET_POINT | AHB_MED_SET_POINT))) { + if (low_freq_bus_used() && !low_bus_freq_mode) + set_low_bus_freq(); + } else { + if ((clk->flags & AHB_MED_SET_POINT) + && !med_bus_freq_mode) + /* Set to Medium setpoint */ + set_high_bus_freq(0); + else if ((clk->flags & AHB_HIGH_SET_POINT) + && !high_bus_freq_mode) + /* Currently at low or medium set point, + * need to set to high setpoint + */ + set_high_bus_freq(1); + } +#endif + } + + + spin_lock_irqsave(&clockfw_lock, flags); + ret = __clk_enable(clk); - mutex_unlock(&clocks_mutex); + + spin_unlock_irqrestore(&clockfw_lock, flags); return ret; } @@ -99,15 +220,56 @@ EXPORT_SYMBOL(clk_enable); */ void clk_disable(struct clk *clk) { + unsigned long flags; + + if (in_interrupt()) { + printk(KERN_ERR " clk_disable cannot be called in an interrupt context\n"); + dump_stack(); + BUG(); + } + if (clk == NULL || IS_ERR(clk)) return; - mutex_lock(&clocks_mutex); + spin_lock_irqsave(&clockfw_lock, flags); + __clk_disable(clk); - mutex_unlock(&clocks_mutex); + + spin_unlock_irqrestore(&clockfw_lock, flags); + + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) + && (clk_get_usecount(clk) == 0)) { +#if (defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX37)) + if (low_freq_bus_used() && !low_bus_freq_mode) + set_low_bus_freq(); + else + /* Set to either high or medium setpoint. */ + set_high_bus_freq(0); +#endif + } } + EXPORT_SYMBOL(clk_disable); +/*! + * @brief Function to get the usage count for the requested clock. + * + * This function returns the reference count for the clock. + * + * @param clk Handle to clock to disable. + * + * @return Returns the usage count for the requested clock. + */ +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return 0; + + return clk->usecount; +} + +EXPORT_SYMBOL(clk_get_usecount); + /* Retrieve the *current* clock rate. If the clock itself * does not provide a special calculation routine, ask * its parent and so on, until one is able to return @@ -125,6 +287,16 @@ unsigned long clk_get_rate(struct clk *clk) } EXPORT_SYMBOL(clk_get_rate); +#ifndef CONFIG_COMMON_CLKDEV +/* Decrement the clock's module reference count */ +void clk_put(struct clk *clk) +{ + if (clk && !IS_ERR(clk)) + module_put(clk->owner); +} +EXPORT_SYMBOL(clk_put); +#endif + /* Round the requested clock rate to the nearest supported * rate that is less than or equal to the requested rate. * This is dependent on the clock's current parent. @@ -143,14 +315,15 @@ EXPORT_SYMBOL(clk_round_rate); */ int clk_set_rate(struct clk *clk, unsigned long rate) { + unsigned long flags; int ret = -EINVAL; if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) return ret; - mutex_lock(&clocks_mutex); + spin_lock_irqsave(&clockfw_lock, flags); ret = clk->set_rate(clk, rate); - mutex_unlock(&clocks_mutex); + spin_unlock_irqrestore(&clockfw_lock, flags); return ret; } @@ -159,17 +332,27 @@ EXPORT_SYMBOL(clk_set_rate); /* Set the clock's parent to another clock source */ int clk_set_parent(struct clk *clk, struct clk *parent) { + unsigned long flags; int ret = -EINVAL; + struct clk *prev_parent = clk->parent; if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent) || clk->set_parent == NULL) return ret; - mutex_lock(&clocks_mutex); + if (clk->usecount != 0) { + clk_enable(parent); + } + + spin_lock_irqsave(&clockfw_lock, flags); ret = clk->set_parent(clk, parent); if (ret == 0) clk->parent = parent; - mutex_unlock(&clocks_mutex); + spin_unlock_irqrestore(&clockfw_lock, flags); + + if (clk->usecount != 0) { + clk_disable(prev_parent); + } return ret; } @@ -187,6 +370,182 @@ struct clk *clk_get_parent(struct clk *clk) } EXPORT_SYMBOL(clk_get_parent); +/* + * Add a new clock to the clock tree. + */ +int clk_register(struct mxc_clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + mutex_lock(&clocks_mutex); + list_add(&clk->node, &clocks); + mutex_unlock(&clocks_mutex); + + return 0; +} +EXPORT_SYMBOL(clk_register); + +/* Remove a clock from the clock tree */ +void clk_unregister(struct mxc_clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return; + + mutex_lock(&clocks_mutex); + list_del(&clk->node); + mutex_unlock(&clocks_mutex); +} +EXPORT_SYMBOL(clk_unregister); + +#ifdef CONFIG_PROC_FS + +static void *mxc_proc_clocks_seq_start(struct seq_file *file, loff_t *index) +{ + unsigned int i; + unsigned int name_length; + unsigned int longest_length = 0; + struct mxc_clk *current_clock = 0; + struct mxc_clk *clock; + + /* Examine the clock list. */ + + i = 0; + + list_for_each_entry(clock, &clocks, node) { + if (i++ == *index) + current_clock = clock; + name_length = strlen(clock->name); + if (name_length > longest_length) + longest_length = name_length; + } + + /* Check if we found the indicated clock. */ + + if (!current_clock) + return NULL; + + /* Stash the length of the longest clock name for later use. */ + + file->private = (void *) longest_length; + + /* Return success. */ + + return current_clock; +} + +static void *mxc_proc_clocks_seq_next(struct seq_file *file, void *data, + loff_t *index) +{ + struct mxc_clk *current_clock = (struct clk *) data; + + /* Check for nonsense. */ + + if (!current_clock) + return NULL; + + /* Check if the current clock is the last. */ + + if (list_is_last(¤t_clock->node, &clocks)) + return NULL; + + /* Move to the next clock structure. */ + + current_clock = list_entry(current_clock->node.next, + typeof(*current_clock), node); + + (*index)++; + + /* Return the new current clock. */ + + return current_clock; + +} + +static void mxc_proc_clocks_seq_stop(struct seq_file *file, void *data) +{ +} + +static int mxc_proc_clocks_seq_show(struct seq_file *file, void *data) +{ + int result; + struct mxc_clk *clock = (struct mxc_clk *) data; + struct clk *parent = clock->reg_clk->parent; + unsigned int longest_length = (unsigned int) file->private; + unsigned long range_divisor; + const char *range_units; + int rate = clk_get_rate(clock->reg_clk); + + if (rate >= 1000000) { + range_divisor = 1000000; + range_units = "MHz"; + } else if (rate >= 1000) { + range_divisor = 1000; + range_units = "KHz"; + } else { + range_divisor = 1; + range_units = "Hz"; + } + result = seq_printf(file, + "%s-%-d%*s %*s %c%c%c%c%c%c %3d", + clock->name, + clock->reg_clk->id, + longest_length - strlen(clock->name), "", + longest_length + 2, "", + (clock->reg_clk->flags & RATE_PROPAGATES) ? 'P' : '_', + (clock->reg_clk->flags & ALWAYS_ENABLED) ? 'A' : '_', + (clock->reg_clk->flags & RATE_FIXED) ? 'F' : '_', + (clock->reg_clk->flags & CPU_FREQ_TRIG_UPDATE) ? 'T' : '_', + (clock->reg_clk->flags & AHB_HIGH_SET_POINT) ? 'H' : '_', + (clock->reg_clk->flags & AHB_MED_SET_POINT) ? 'M' : '_', + clock->reg_clk->usecount); + + if (result) + return result; + + result = seq_printf(file, " %10lu (%lu%s)\n", + rate, + rate / range_divisor, range_units); + + return result; + +} + +static const struct seq_operations mxc_proc_clocks_seq_ops = { + .start = mxc_proc_clocks_seq_start, + .next = mxc_proc_clocks_seq_next, + .stop = mxc_proc_clocks_seq_stop, + .show = mxc_proc_clocks_seq_show +}; + +static int mxc_proc_clocks_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &mxc_proc_clocks_seq_ops); +} + +static const struct file_operations mxc_proc_clocks_ops = { + .open = mxc_proc_clocks_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int __init mxc_setup_proc_entry(void) +{ + struct proc_dir_entry *res; + + res = create_proc_entry("cpu/clocks", 0, NULL); + if (!res) { + printk(KERN_ERR "Failed to create proc/cpu/clocks\n"); + return -ENOMEM; + } + res->proc_fops = &mxc_proc_clocks_ops; + return 0; +} + +late_initcall(mxc_setup_proc_entry); +#endif /* CONFIG_PROC_FS */ + /* * Get the resulting clock rate from a PLL register value and the input * frequency. PLLs with this register layout can at least be found on diff --git a/arch/arm/plat-mxc/cpu_common.c b/arch/arm/plat-mxc/cpu_common.c new file mode 100644 index 000000000000..702489fc89f3 --- /dev/null +++ b/arch/arm/plat-mxc/cpu_common.c @@ -0,0 +1,98 @@ +/* + * Copyright 2004-2007, 2010 Freescale Semiconductor, + * Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +extern int mxc_early_serial_console_init(unsigned long base, struct clk *clk); + +/*! + * @file plat-mxc/cpu_common.c + * + * @brief This file contains the common CPU initialization code. + * + * @ingroup MSL_MX31 MSL_MXC91321 + */ + +static int __init system_rev_setup(char *p) +{ + system_rev = simple_strtoul(p, NULL, 16); + return 0; +} +early_param("system_rev", system_rev_setup); + +int mxc_jtag_enabled; /* OFF: 0 (default), ON: 1 */ +int uart_at_24; /* OFF: 0 (default); ON: 1 */ +/* + * Here are the JTAG options from the command line. By default JTAG + * is OFF which means JTAG is not connected and WFI is enabled + * + * "on" -- JTAG is connected, so WFI is disabled + * "off" -- JTAG is disconnected, so WFI is enabled + */ + +static int __init jtag_wfi_setup(char *p) +{ + if (memcmp(p, "on", 2) == 0) { + mxc_jtag_enabled = 1; + p += 2; + } else if (memcmp(p, "off", 3) == 0) { + mxc_jtag_enabled = 0; + p += 3; + } + return 0; +} +early_param("jtag", jtag_wfi_setup); + +static int __init uart_parent_setup(char *p) +{ + if (memcmp(p, "on", 2) == 0) { + /* set the UART parent clock to be lp-apm */ + uart_at_24 = 1; + p += 2; + } else if (memcmp(p, "off", 3) == 0) { + uart_at_24 = 0; + p += 3; + } + return 0; +} +early_param("debug_uart", uart_parent_setup); + +void __init mxc_cpu_common_init(void) +{ + pr_info("CPU is %s%x Revision %u.%u\n", + (mxc_cpu() < 0x100) ? "i.MX" : "MXC", + mxc_cpu(), mxc_cpu_rev_major(), mxc_cpu_rev_minor()); +} + +/** + * early_console_setup - setup debugging console + * + * Consoles started here require little enough setup that we can start using + * them very early in the boot process, either right after the machine + * vector initialization, or even before if the drivers can detect their hw. + * + * Returns non-zero if a console couldn't be setup. + * This function is developed based on + * early_console_setup function as defined in arch/ia64/kernel/setup.c + */ +void __init early_console_setup(unsigned long base, struct clk *clk) +{ +#ifdef CONFIG_SERIAL_MXC_CONSOLE + mxc_early_serial_console_init(base, clk); +#endif +} diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c new file mode 100644 index 000000000000..5ba4a71d745e --- /dev/null +++ b/arch/arm/plat-mxc/cpufreq.c @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file cpufreq.c + * + * @brief A driver for the Freescale Semiconductor i.MXC CPUfreq module. + * + * The CPUFREQ driver is for controling CPU frequency. It allows you to change + * the CPU clock speed on the fly. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int cpu_freq_khz_min; +int cpu_freq_khz_max; +int arm_lpm_clk; +int arm_normal_clk; +int cpufreq_suspended; +int cpufreq_trig_needed; + +static struct clk *cpu_clk; +static struct regulator *gp_regulator; +static struct cpu_wp *cpu_wp_tbl; +static struct cpufreq_frequency_table imx_freq_table[6]; +extern int low_bus_freq_mode; +extern int high_bus_freq_mode; +extern int dvfs_core_is_active; +extern int cpu_wp_nr; +extern char *gp_reg_id; + +extern int set_low_bus_freq(void); +extern int set_high_bus_freq(int high_bus_speed); +extern int low_freq_bus_used(void); + +#ifdef CONFIG_ARCH_MX5 +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +#endif + +int set_cpu_freq(int freq) +{ + int ret = 0; + int org_cpu_rate; + int gp_volt = 0; + int i; + + org_cpu_rate = clk_get_rate(cpu_clk); + if (org_cpu_rate == freq) + return ret; + + for (i = 0; i < cpu_wp_nr; i++) { + if (freq == cpu_wp_tbl[i].cpu_rate) + gp_volt = cpu_wp_tbl[i].cpu_voltage; + } + + if (gp_volt == 0) + return ret; + + /*Set the voltage for the GP domain. */ + if (freq > org_cpu_rate) { + ret = regulator_set_voltage(gp_regulator, gp_volt, gp_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); + return ret; + } + } + + ret = clk_set_rate(cpu_clk, freq); + if (ret != 0) { + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + return ret; + } + + if (freq < org_cpu_rate) { + ret = regulator_set_voltage(gp_regulator, gp_volt, gp_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); + return ret; + } + } + + return ret; +} + +static int mxc_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, imx_freq_table); +} + +static unsigned int mxc_get_speed(unsigned int cpu) +{ + if (cpu) + return 0; + + return clk_get_rate(cpu_clk) / 1000; +} + +static int calc_frequency_khz(int target, unsigned int relation) +{ + int i; + + if ((target * 1000) == clk_get_rate(cpu_clk)) + return target; + + if (relation == CPUFREQ_RELATION_H) { + for (i = cpu_wp_nr - 1; i >= 0; i--) { + if (imx_freq_table[i].frequency <= target) + return imx_freq_table[i].frequency; + } + } else if (relation == CPUFREQ_RELATION_L) { + for (i = 0; i < cpu_wp_nr; i++) { + if (imx_freq_table[i].frequency >= target) + return imx_freq_table[i].frequency; + } + } + printk(KERN_ERR "Error: No valid cpufreq relation\n"); + return cpu_freq_khz_max; +} + +static int mxc_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, unsigned int relation) +{ + struct cpufreq_freqs freqs; + int freq_Hz; + int low_freq_bus_ready = 0; + int ret = 0; + + if (dvfs_core_is_active || cpufreq_suspended) { + target_freq = clk_get_rate(cpu_clk) / 1000; + freq_Hz = calc_frequency_khz(target_freq, relation) * 1000; + if (freq_Hz == arm_lpm_clk) + freqs.old = cpu_wp_tbl[cpu_wp_nr - 2].cpu_rate / 1000; + else + freqs.old = arm_lpm_clk / 1000; + + freqs.new = freq_Hz / 1000; + freqs.cpu = 0; + freqs.flags = 0; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + return ret; + } + /* + * Some governors do not respects CPU and policy lower limits + * which leads to bad things (division by zero etc), ensure + * that such things do not happen. + */ + if (target_freq < policy->cpuinfo.min_freq) + target_freq = policy->cpuinfo.min_freq; + + if (target_freq < policy->min) + target_freq = policy->min; + + freq_Hz = calc_frequency_khz(target_freq, relation) * 1000; + + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = freq_Hz / 1000; + freqs.cpu = 0; + freqs.flags = 0; + low_freq_bus_ready = low_freq_bus_used(); + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + if (!dvfs_core_is_active) { + if ((freq_Hz == arm_lpm_clk) && (!low_bus_freq_mode) + && (low_freq_bus_ready)) { + if (freqs.old != freqs.new) + ret = set_cpu_freq(freq_Hz); + set_low_bus_freq(); + + } else { + set_high_bus_freq(0); + ret = set_cpu_freq(freq_Hz); + } + } + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return ret; +} + +static int __init mxc_cpufreq_driver_init(struct cpufreq_policy *policy) +{ + int ret; + int i; + + printk(KERN_INFO "i.MXC CPU frequency driver\n"); + + if (policy->cpu != 0) + return -EINVAL; + + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); + return PTR_ERR(cpu_clk); + } + + gp_regulator = regulator_get(NULL, gp_reg_id); + if (IS_ERR(gp_regulator)) { + clk_put(cpu_clk); + printk(KERN_ERR "%s: failed to get gp regulator\n", __func__); + return PTR_ERR(gp_regulator); + } + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + + cpu_freq_khz_min = cpu_wp_tbl[0].cpu_rate / 1000; + cpu_freq_khz_max = cpu_wp_tbl[0].cpu_rate / 1000; + + for (i = 0; i < cpu_wp_nr; i++) { + imx_freq_table[cpu_wp_nr - 1 - i].index = cpu_wp_nr - i; + imx_freq_table[cpu_wp_nr - 1 - i].frequency = + cpu_wp_tbl[i].cpu_rate / 1000; + + if ((cpu_wp_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min) + cpu_freq_khz_min = cpu_wp_tbl[i].cpu_rate / 1000; + + if ((cpu_wp_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max) + cpu_freq_khz_max = cpu_wp_tbl[i].cpu_rate / 1000; + } + + imx_freq_table[i].index = 0; + imx_freq_table[i].frequency = CPUFREQ_TABLE_END; + + policy->cur = clk_get_rate(cpu_clk) / 1000; + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; + policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; + + arm_lpm_clk = cpu_freq_khz_min * 1000; + arm_normal_clk = cpu_freq_khz_max * 1000; + + /* Manual states, that PLL stabilizes in two CLK32 periods */ + policy->cpuinfo.transition_latency = 10; + + ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); + + if (ret < 0) { + clk_put(cpu_clk); + regulator_put(gp_regulator); + printk(KERN_ERR "%s: failed to register i.MXC CPUfreq\n", + __func__); + return ret; + } + + cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu); + return 0; +} + +static int mxc_cpufreq_suspend(struct cpufreq_policy *policy, + pm_message_t state) +{ + return 0; +} + +static int mxc_cpufreq_resume(struct cpufreq_policy *policy) +{ + return 0; +} + +static int mxc_cpufreq_driver_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + + /* Reset CPU to 665MHz */ + if (!dvfs_core_is_active) + set_cpu_freq(arm_normal_clk); + if (!high_bus_freq_mode) + set_high_bus_freq(1); + + clk_put(cpu_clk); + regulator_put(gp_regulator); + return 0; +} + +static struct cpufreq_driver mxc_driver = { + .flags = CPUFREQ_STICKY, + .verify = mxc_verify_speed, + .target = mxc_set_target, + .get = mxc_get_speed, + .init = mxc_cpufreq_driver_init, + .exit = mxc_cpufreq_driver_exit, + .suspend = mxc_cpufreq_suspend, + .resume = mxc_cpufreq_resume, + .name = "imx", +}; + +static int __devinit mxc_cpufreq_init(void) +{ + return cpufreq_register_driver(&mxc_driver); +} + +static void mxc_cpufreq_exit(void) +{ + cpufreq_unregister_driver(&mxc_driver); +} + +module_init(mxc_cpufreq_init); +module_exit(mxc_cpufreq_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("CPUfreq driver for i.MX"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 56f2fb5cc456..735776d84956 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -18,6 +18,7 @@ #include #include +#include #include #include @@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) return ret; } +struct platform_device *__init imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + int ret = -ENOMEM; + struct platform_device *pdev; + + pdev = platform_device_alloc(name, id); + if (!pdev) + goto err; + + if (res) { + ret = platform_device_add_resources(pdev, res, num_resources); + if (ret) + goto err; + } + + if (data) { + ret = platform_device_add_data(pdev, data, size_data); + if (ret) + goto err; + } + + ret = platform_device_add(pdev); + if (ret) { +err: + platform_device_put(pdev); + return ERR_PTR(ret); + } + + return pdev; +} diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig new file mode 100644 index 000000000000..15ac08ef5f33 --- /dev/null +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -0,0 +1,18 @@ +config IMX_HAVE_PLATFORM_FLEXCAN + select HAVE_CAN_FLEXCAN + bool + +config IMX_HAVE_PLATFORM_IMX_I2C + bool + +config IMX_HAVE_PLATFORM_IMX_UART + bool + +config IMX_HAVE_PLATFORM_MXC_NAND + bool + +config IMX_HAVE_PLATFORM_SPI_IMX + bool + +config IMX_HAVE_PLATFORM_IMX_MMC + bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile new file mode 100644 index 000000000000..e2aa4196bfae --- /dev/null +++ b/arch/arm/plat-mxc/devices/Makefile @@ -0,0 +1,9 @@ +ifdef CONFIG_CAN_FLEXCAN +# the ifdef can be removed once the flexcan driver has been merged +obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +endif +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_MMC) += platform-imx-mmc.o diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c new file mode 100644 index 000000000000..f1260b3f98a7 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde + * Copyright (C) 2010 Freescale Semiconductor + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include + +struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c new file mode 100644 index 000000000000..aa3419faf020 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include + +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-mmc.c b/arch/arm/plat-mxc/devices/platform-imx-mmc.c new file mode 100644 index 000000000000..29fc87315cda --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-mmc.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include +#include + +struct platform_device *__init imx_add_imx_mmc(int id, + resource_size_t iobase, resource_size_t iosize, int irq1, + int irq2, const struct mxc_mmc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq1, + .end = irq1, + .flags = IORESOURCE_IRQ, + }, { + .start = irq2, + .end = irq2, + .flags = IORESOURCE_IRQ, + } + }; + + return imx_add_platform_device("mxsdhci", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c new file mode 100644 index 000000000000..452da740f4c4 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irqrx = soc ## _INT_UART ## _hwid ## RX, \ + .irqtx = soc ## _INT_UART ## _hwid ## TX, \ + .irqrts = soc ## _INT_UART ## _hwid ## RTS, \ + } + +#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_UART ## _hwid, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = { +#define imx1_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0) + imx1_imx_uart_data_entry(0, 1), + imx1_imx_uart_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX1 */ + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { +#define imx21_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_imx_uart_data_entry(0, 1), + imx21_imx_uart_data_entry(1, 2), + imx21_imx_uart_data_entry(2, 3), + imx21_imx_uart_data_entry(3, 4), +}; +#endif + +#ifdef CONFIG_ARCH_MX25 +const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { +#define imx25_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_imx_uart_data_entry(0, 1), + imx25_imx_uart_data_entry(1, 2), + imx25_imx_uart_data_entry(2, 3), + imx25_imx_uart_data_entry(3, 4), + imx25_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_ARCH_MX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { +#define imx27_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_imx_uart_data_entry(0, 1), + imx27_imx_uart_data_entry(1, 2), + imx27_imx_uart_data_entry(2, 3), + imx27_imx_uart_data_entry(3, 4), + imx27_imx_uart_data_entry(4, 5), + imx27_imx_uart_data_entry(5, 6), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_ARCH_MX31 +const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { +#define imx31_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) + imx31_imx_uart_data_entry(0, 1), + imx31_imx_uart_data_entry(1, 2), + imx31_imx_uart_data_entry(2, 3), + imx31_imx_uart_data_entry(3, 4), + imx31_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_ARCH_MX31 */ + +#ifdef CONFIG_ARCH_MX35 +const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { +#define imx35_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) + imx35_imx_uart_data_entry(0, 1), + imx35_imx_uart_data_entry(1, 2), + imx35_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_ARCH_MX35 */ + +#ifdef CONFIG_ARCH_MX51 +const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { +#define imx51_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) + imx51_imx_uart_data_entry(0, 1), + imx51_imx_uart_data_entry(1, 2), + imx51_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_ARCH_MX51 */ + +struct platform_device *__init imx_add_imx_uart_3irq( + const struct imx_imx_uart_3irq_data *data, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqrx, + .end = data->irqrx, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irqtx, + .end = data->irqtx, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irqrts, + .end = data->irqrx, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_imx_uart_1irq( + const struct imx_imx_uart_1irq_data *data, + const struct imxuart_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c new file mode 100644 index 000000000000..f3fd5b6953e0 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata, + resource_size_t iosize) +{ + static int id; + + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} + +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K); +} + +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata) +{ + return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c new file mode 100644 index 000000000000..a72eac3df354 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata) +{ + struct resource res[] = { + { + .start = iobase, + .end = iobase + iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = irq, + .end = irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/dptc.c b/arch/arm/plat-mxc/dptc.c new file mode 100644 index 000000000000..c34b7f042cfb --- /dev/null +++ b/arch/arm/plat-mxc/dptc.c @@ -0,0 +1,640 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dptc.c + * + * @brief Driver for the Freescale Semiconductor MXC DPTC module. + * + * The DPTC driver is designed to control the MXC DPTC hardware. + * hardware. Upon initialization, the DPTC driver initializes the DPTC hardware + * sets up driver nodes attaches to the DPTC interrupt and initializes internal + * data structures. When the DPTC interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and changes + * the CPU voltage according to translation table that is loaded into the driver. + * The driver read method is used to read the log buffer. + * Driver ioctls are used to change driver parameters and enable/disable the + * DVFS operation. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +enum { + DPTC_PTVAI_NOCHANGE = 0x0, + DPTC_PTVAI_DECREASE, + DPTC_PTVAI_INCREASE, + DPTC_PTVAI_EMERG, +}; + +struct device *dev_data0; +struct device *dev_data1; +struct dptc_device *dptc_device_data; + +/*! + * In case the MXC device has multiple DPTC modules, this structure is used to + * store information specific to each DPTC module. + */ +struct dptc_device { + /* DPTC delayed work */ + struct delayed_work dptc_work; + /* DPTC spinlock */ + spinlock_t lock; + /* DPTC regulator */ + struct regulator *dptc_reg; + /* DPTC clock */ + struct clk *dptc_clk; + /* DPTC is active flag */ + int dptc_is_active; + /* turbo mode active flag */ + int turbo_mode_active; + /* DPTC current working point */ + int curr_wp; + /* DPTC vai bits */ + u32 ptvai; + /* The base address of the DPTC */ + void __iomem *membase; + /* The interrupt number used by the DPTC device */ + int irq; + /* DPTC platform data pointer */ + struct mxc_dptc_data *dptc_platform_data; +}; + +static void update_dptc_wp(struct dptc_device *drv_data, u32 wp) +{ + struct mxc_dptc_data *dptc_data = drv_data->dptc_platform_data; + int voltage_uV; + int ret = 0; + + voltage_uV = dptc_data->dptc_wp_allfreq[wp].voltage * 1000; + + __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr0, + drv_data->membase + dptc_data->dcvr0_reg_addr); + __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr1, + drv_data->membase + dptc_data->dcvr0_reg_addr + 0x4); + __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr2, + drv_data->membase + dptc_data->dcvr0_reg_addr + 0x8); + __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr3, + drv_data->membase + dptc_data->dcvr0_reg_addr + 0xC); + + /* Set the voltage */ + ret = regulator_set_voltage(drv_data->dptc_reg, voltage_uV, voltage_uV); + if (ret < 0) + printk(KERN_DEBUG "COULD NOT SET VOLTAGE!!!!!\n"); + + pr_debug("dcvr0-3: 0x%x, 0x%x, 0x%x, 0x%x; vol: %d\n", + dptc_data->dptc_wp_allfreq[wp].dcvr0, + dptc_data->dptc_wp_allfreq[wp].dcvr1, + dptc_data->dptc_wp_allfreq[wp].dcvr2, + dptc_data->dptc_wp_allfreq[wp].dcvr3, + dptc_data->dptc_wp_allfreq[wp].voltage); +} + +static irqreturn_t dptc_irq(int irq, void *dev_id) +{ + struct device *dev = dev_id; + struct dptc_device *drv_data = dev->driver_data; + struct mxc_dptc_data *dptc_data = dev->platform_data; + u32 dptccr = __raw_readl(drv_data->membase + + dptc_data->dptccr_reg_addr); + u32 gpc_cntr = __raw_readl(dptc_data->gpc_cntr_reg_addr); + + gpc_cntr = (gpc_cntr & dptc_data->dptccr); + + if (gpc_cntr) { + drv_data->ptvai = + (dptccr & dptc_data->vai_mask) >> dptc_data->vai_offset; + pr_debug("dptc_irq: vai = 0x%x (0x%x)!!!!!!!\n", + drv_data->ptvai, dptccr); + + /* disable DPTC and mask its interrupt */ + dptccr = (dptccr & ~(dptc_data->dptc_enable_bit)) | + (dptc_data->irq_mask); + dptccr = (dptccr & ~(dptc_data->dptc_nvcr_bit)); + __raw_writel(dptccr, drv_data->membase + + dptc_data->dptccr_reg_addr); + + if (drv_data->turbo_mode_active == 1) + schedule_delayed_work(&drv_data->dptc_work, 0); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static void dptc_workqueue_handler(struct work_struct *work1) +{ + struct delayed_work *dptc_work_tmp = + container_of(work1, struct delayed_work, work); + struct dptc_device *drv_data = + container_of(dptc_work_tmp, struct dptc_device, dptc_work); + struct mxc_dptc_data *dptc_data = drv_data->dptc_platform_data; + u32 dptccr = __raw_readl(drv_data->membase + + dptc_data->dptccr_reg_addr); + + switch (drv_data->ptvai) { + case DPTC_PTVAI_DECREASE: + drv_data->curr_wp++; + break; + case DPTC_PTVAI_INCREASE: + case DPTC_PTVAI_EMERG: + drv_data->curr_wp--; + if (drv_data->curr_wp < 0) { + /* already max voltage */ + drv_data->curr_wp = 0; + printk(KERN_WARNING "dptc: already maximum voltage\n"); + } + break; + + /* Unknown interrupt cause */ + default: + BUG(); + } + + if (drv_data->curr_wp > dptc_data->dptc_wp_supported + || drv_data->curr_wp < 0) { + panic("Can't support this working point: %d\n", + drv_data->curr_wp); + } + update_dptc_wp(drv_data, drv_data->curr_wp); + + /* Enable DPTC and unmask its interrupt */ + dptccr = (dptccr & ~(dptc_data->irq_mask)) | + dptc_data->dptc_nvcr_bit | dptc_data->dptc_enable_bit; + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); +} + +/* Start DPTC unconditionally */ +static int start_dptc(struct device *dev) +{ + struct mxc_dptc_data *dptc_data = dev->platform_data; + struct dptc_device *drv_data = dev->driver_data; + u32 dptccr; + unsigned long flags; + unsigned long clk_rate; + int voltage_uV; + + /* Get the voltage */ + voltage_uV = regulator_get_voltage(drv_data->dptc_reg); + drv_data->curr_wp = + (dptc_data->dptc_wp_allfreq[0].voltage - (voltage_uV / 1000)) / 25; + + update_dptc_wp(drv_data, drv_data->curr_wp); + + /* Set the voltage */ + spin_lock_irqsave(&drv_data->lock, flags); + + clk_rate = clk_get_rate(drv_data->dptc_clk); + + if (clk_rate < dptc_data->clk_max_val) + goto err; + + if (dptc_data->gpc_irq_bit != 0x0) { + /* Enable ARM domain frequency and/or voltage update needed + and enable ARM IRQ */ + __raw_writel(dptc_data->gpc_irq_bit | dptc_data->gpc_adu, + dptc_data->gpc_cntr_reg_addr); + } + + dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr); + + /* Enable DPTC and unmask its interrupt */ + dptccr = ((dptccr & ~(dptc_data->irq_mask)) | dptc_data->enable_config); + + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); + + spin_unlock_irqrestore(&drv_data->lock, flags); + + drv_data->dptc_is_active = 1; + drv_data->turbo_mode_active = 1; + + pr_info("DPTC has been started \n"); + + return 0; + +err: + spin_unlock_irqrestore(&drv_data->lock, flags); + pr_info("DPTC is not enabled\n"); + return -1; +} + +/* Stop DPTC unconditionally */ +static void stop_dptc(struct device *dev) +{ + struct mxc_dptc_data *dptc_data = dev->platform_data; + struct dptc_device *drv_data = dev->driver_data; + u32 dptccr; + + dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr); + + /* disable DPTC and mask its interrupt */ + dptccr = ((dptccr & ~(dptc_data->dptc_enable_bit)) | + dptc_data->irq_mask) & (~dptc_data->dptc_nvcr_bit); + + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); + + /* Restore Turbo Mode voltage to highest wp */ + update_dptc_wp(drv_data, 0); + drv_data->curr_wp = 0; + + regulator_put(drv_data->dptc_reg); + + pr_info("DPTC has been stopped\n"); +} + +/* + This function does not change the working point. It can be + called from an interrupt context. +*/ +void dptc_suspend(int id) +{ + struct mxc_dptc_data *dptc_data; + struct dptc_device *drv_data; + u32 dptccr; + + switch (id) { + case DPTC_GP_ID: + dptc_data = dev_data0->platform_data; + drv_data = dev_data0->driver_data; + break; + case DPTC_LP_ID: + if (dev_data1 == NULL) + return; + + dptc_data = dev_data1->platform_data; + drv_data = dev_data1->driver_data; + break; + /* Unknown DPTC ID */ + default: + return; + } + + if (!drv_data->dptc_is_active) + return; + + dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr); + + /* Disable DPTC and mask its interrupt */ + dptccr = (dptccr & ~(dptc_data->dptc_enable_bit)) | dptc_data->irq_mask; + + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); +} +EXPORT_SYMBOL(dptc_suspend); + +/* + This function does not change the working point. It can be + called from an interrupt context. +*/ +void dptc_resume(int id) +{ + struct mxc_dptc_data *dptc_data; + struct dptc_device *drv_data; + u32 dptccr; + + switch (id) { + case DPTC_GP_ID: + dptc_data = dev_data0->platform_data; + drv_data = dev_data0->driver_data; + break; + case DPTC_LP_ID: + if (dev_data1 == NULL) + return; + + dptc_data = dev_data1->platform_data; + drv_data = dev_data1->driver_data; + break; + /* Unknown DPTC ID */ + default: + return; + } + + if (!drv_data->dptc_is_active) + return; + + __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr0, + drv_data->membase + dptc_data->dcvr0_reg_addr); + __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr1, + drv_data->membase + dptc_data->dcvr0_reg_addr + 0x4); + __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr2, + drv_data->membase + dptc_data->dcvr0_reg_addr + 0x8); + __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr3, + drv_data->membase + dptc_data->dcvr0_reg_addr + 0xC); + + dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr); + + /* Enable DPTC and unmask its interrupt */ + dptccr = (dptccr & ~(dptc_data->irq_mask)) | dptc_data->dptc_enable_bit; + + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); +} +EXPORT_SYMBOL(dptc_resume); + +/*! + * This function is called to put the DPTC in a low power state. + * + */ +void dptc_disable(struct device *dev) +{ + struct dptc_device *drv_data = dev->driver_data; + + if (!(drv_data->dptc_is_active)) + return; + + stop_dptc(dev); + drv_data->dptc_is_active = 0; + drv_data->turbo_mode_active = 0; +} + +/*! + * This function is called to resume the DPTC from a low power state. + * + */ +int dptc_enable(struct device *dev) +{ + struct dptc_device *drv_data = dev->driver_data; + + if (drv_data->dptc_is_active) + return 0; + + return start_dptc(dev); +} + +static ssize_t dptc_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct dptc_device *drv_data = dev->driver_data; + + if (drv_data->dptc_is_active) + return sprintf(buf, "DPTC is enabled\n"); + else + return sprintf(buf, "DPTC is disabled\n"); +} + +static ssize_t dptc_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "0") != NULL) { + dptc_disable(dev); + } else if (strstr(buf, "1") != NULL) { + dptc_enable(dev); + } + + return size; +} + +static DEVICE_ATTR(enable, 0644, dptc_show, dptc_store); + +/*! + * This is the probe routine for the DPTC driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit mxc_dptc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *res; + u32 dptccr = 0; + struct clk *ckih_clk; + struct mxc_dptc_data *dptc_data = pdev->dev.platform_data; + + if (dptc_data == NULL) { + printk(KERN_ERR "DPTC: Pointer to DPTC data is NULL\ + not started\n"); + return -1; + } + + dptc_device_data = kzalloc(sizeof(struct dptc_device), GFP_KERNEL); + if (!dptc_device_data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + + dptc_device_data->membase = ioremap(res->start, + res->end - res->start + 1); + + /* + * Request the DPTC interrupt + */ + dptc_device_data->irq = platform_get_irq(pdev, 0); + if (dptc_device_data->irq < 0) { + ret = dptc_device_data->irq; + goto err2; + } + + ret = + request_irq(dptc_device_data->irq, dptc_irq, IRQF_SHARED, + pdev->name, &pdev->dev); + if (ret) { + printk(KERN_ERR "DPTC: Unable to attach to DPTC interrupt\n"); + goto err2; + } + + dptc_device_data->curr_wp = 0; + dptc_device_data->dptc_is_active = 0; + dptc_device_data->turbo_mode_active = 0; + dptc_device_data->ptvai = 0; + + dptccr = __raw_readl(dptc_device_data->membase + + dptc_data->dptccr_reg_addr); + + printk(KERN_INFO "DPTC mxc_dptc_probe()\n"); + + spin_lock_init(&dptc_device_data->lock); + + if (dptc_data->dptc_wp_allfreq == NULL) { + ckih_clk = clk_get(NULL, "ckih"); + if (cpu_is_mx31() & + (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) & + (clk_get_rate(ckih_clk) == 27000000)) + printk(KERN_ERR "DPTC: DPTC not supported on TO1.x \ + & ckih = 27M\n"); + else + printk(KERN_ERR "DPTC: Pointer to DPTC table is NULL\ + not started\n"); + goto err3; + } + + dptc_device_data->dptc_reg = regulator_get(NULL, dptc_data->reg_id); + if (IS_ERR(dptc_device_data->dptc_reg)) { + clk_put(dptc_device_data->dptc_clk); + printk(KERN_ERR "%s: failed to get regulator\n", __func__); + goto err3; + } + + INIT_DELAYED_WORK(&dptc_device_data->dptc_work, dptc_workqueue_handler); + + /* Enable Reference Circuits */ + dptccr = (dptccr & ~(dptc_data->dcr_mask)) | dptc_data->init_config; + __raw_writel(dptccr, dptc_device_data->membase + + dptc_data->dptccr_reg_addr); + + ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_enable.attr); + if (ret) { + printk(KERN_ERR + "DPTC: Unable to register sysdev entry for dptc"); + goto err3; + } + + if (ret != 0) { + printk(KERN_ERR "DPTC: Unable to start"); + goto err3; + } + + dptc_device_data->dptc_clk = clk_get(NULL, dptc_data->clk_id); + + if (pdev->id == 0) + dev_data0 = &pdev->dev; + else + dev_data1 = &pdev->dev; + + dptc_device_data->dptc_platform_data = pdev->dev.platform_data; + + /* Set driver data */ + platform_set_drvdata(pdev, dptc_device_data); + + return 0; + +err3: + free_irq(dptc_device_data->irq, &pdev->dev); +err2: + iounmap(dptc_device_data->membase); +err1: + dev_err(&pdev->dev, "Failed to probe DPTC\n"); + kfree(dptc_device_data); + return ret; +} + +/*! + * This function is called to put DPTC in a low power state. + * + * @param pdev the device structure + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_dptc_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct dptc_device *drv_data = pdev->dev.driver_data; + + if (drv_data->dptc_is_active) + stop_dptc(&pdev->dev); + + return 0; +} + +/*! + * This function is called to resume the MU from a low power state. + * + * @param dev the device structure + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ +static int mxc_dptc_resume(struct platform_device *pdev) +{ + struct dptc_device *drv_data = pdev->dev.driver_data; + + if (drv_data->dptc_is_active) + return start_dptc(&pdev->dev); + + return 0; +} + +static struct platform_driver mxc_dptc_driver = { + .driver = { + .name = "mxc_dptc", + .owner = THIS_MODULE, + }, + .probe = mxc_dptc_probe, + .suspend = mxc_dptc_suspend, + .resume = mxc_dptc_resume, +}; + +/*! + * This function is called to resume the MU from a low power state. + * + * @param dev the device structure used to give information on which MU + * device (0 through 3 channels) to suspend + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ + +static int __init dptc_init(void) +{ + if (platform_driver_register(&mxc_dptc_driver) != 0) { + printk(KERN_ERR "mxc_dptc_driver register failed\n"); + return -ENODEV; + } + + printk(KERN_INFO "DPTC driver module loaded\n"); + + return 0; +} + +static void __exit dptc_cleanup(void) +{ + free_irq(dptc_device_data->irq, NULL); + iounmap(dptc_device_data->membase); + kfree(dptc_device_data); + + /* Unregister the device structure */ + platform_driver_unregister(&mxc_dptc_driver); + + printk("DPTC driver module unloaded\n"); +} + +module_init(dptc_init); +module_exit(dptc_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DPTC driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c new file mode 100644 index 000000000000..8830dce17e5f --- /dev/null +++ b/arch/arm/plat-mxc/dvfs_core.c @@ -0,0 +1,994 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dvfs_core.c + * + * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module. + * + * Upon initialization, the DVFS driver initializes the DVFS hardware + * sets up driver nodes attaches to the DVFS interrupt and initializes internal + * data structures. When the DVFS interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and + * changes the CPU voltage according to translation table that is loaded into + * the driver. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_DVFSTHRS_UPTHR_MASK 0x0FC00000 +#define MXC_DVFSTHRS_UPTHR_OFFSET 22 +#define MXC_DVFSTHRS_DNTHR_MASK 0x003F0000 +#define MXC_DVFSTHRS_DNTHR_OFFSET 16 +#define MXC_DVFSTHRS_PNCTHR_MASK 0x0000003F +#define MXC_DVFSTHRS_PNCTHR_OFFSET 0 + +#define MXC_DVFSCOUN_DNCNT_MASK 0x00FF0000 +#define MXC_DVFSCOUN_DNCNT_OFFSET 16 +#define MXC_DVFSCOUN_UPCNT_MASK 0x000000FF +#define MXC_DVFSCOUN_UPCNT_OFFSET 0 + +#define MXC_DVFSEMAC_EMAC_MASK 0x000001FF +#define MXC_DVFSEMAC_EMAC_OFFSET 0 + +#define MXC_DVFSCNTR_DVFEV 0x10000000 +#define MXC_DVFSCNTR_LBMI 0x08000000 +#define MXC_DVFSCNTR_LBFL 0x06000000 +#define MXC_DVFSCNTR_DVFIS 0x01000000 +#define MXC_DVFSCNTR_FSVAIM 0x00400000 +#define MXC_DVFSCNTR_FSVAI_MASK 0x00300000 +#define MXC_DVFSCNTR_FSVAI_OFFSET 20 +#define MXC_DVFSCNTR_WFIM 0x00080000 +#define MXC_DVFSCNTR_WFIM_OFFSET 19 +#define MXC_DVFSCNTR_MAXF_MASK 0x00040000 +#define MXC_DVFSCNTR_MAXF_OFFSET 18 +#define MXC_DVFSCNTR_MINF_MASK 0x00020000 +#define MXC_DVFSCNTR_MINF_OFFSET 17 +#define MXC_DVFSCNTR_LTBRSR_MASK 0x00000018 +#define MXC_DVFSCNTR_LTBRSR_OFFSET 3 +#define MXC_DVFSCNTR_DVFEN 0x00000001 + +#define CCM_CDCR_SW_DVFS_EN 0x20 +#define CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER 0x4 + +extern int dvfs_core_is_active; +extern void setup_pll(void); +static struct mxc_dvfs_platform_data *dvfs_data; +static struct device *dvfs_dev; +static struct cpu_wp *cpu_wp_tbl; +int dvfs_core_resume; +int curr_wp; +int old_wp; + +extern int cpufreq_trig_needed; +struct timeval core_prev_intr; + +void dump_dvfs_core_regs(void); +void stop_dvfs(void); +static struct delayed_work dvfs_core_handler; + +/* + * Clock structures + */ +static struct clk *pll1_sw_clk; +static struct clk *cpu_clk; +static struct clk *dvfs_clk; +static struct regulator *core_regulator; + +extern int cpu_wp_nr; +#ifdef CONFIG_ARCH_MX5 +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +#endif + +enum { + FSVAI_FREQ_NOCHANGE = 0x0, + FSVAI_FREQ_INCREASE, + FSVAI_FREQ_DECREASE, + FSVAI_FREQ_EMERG, +}; + +/* + * Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add; 2 for after EMA + */ +#define DVFS_LTBRSR (2 << MXC_DVFSCNTR_LTBRSR_OFFSET) + +extern struct dvfs_wp dvfs_core_setpoint[4]; +extern int low_bus_freq_mode; +extern int high_bus_freq_mode; +extern int set_low_bus_freq(void); +extern int set_high_bus_freq(int high_bus_speed); +extern int low_freq_bus_used(void); + +DEFINE_SPINLOCK(mxc_dvfs_core_lock); + +static void dvfs_load_config(int set_point) +{ + u32 reg; + reg = 0; + + reg |= dvfs_core_setpoint[set_point].upthr << MXC_DVFSTHRS_UPTHR_OFFSET; + reg |= dvfs_core_setpoint[set_point].downthr << + MXC_DVFSTHRS_DNTHR_OFFSET; + reg |= dvfs_core_setpoint[set_point].panicthr; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_THRS); + + reg = 0; + reg |= dvfs_core_setpoint[set_point].downcnt << + MXC_DVFSCOUN_DNCNT_OFFSET; + reg |= dvfs_core_setpoint[set_point].upcnt << MXC_DVFSCOUN_UPCNT_OFFSET; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_COUN); + + /* Set EMAC value */ + __raw_writel((dvfs_core_setpoint[set_point].emac << + MXC_DVFSEMAC_EMAC_OFFSET), + dvfs_data->membase + + MXC_DVFSCORE_EMAC); + + +} + +static int set_cpu_freq(int wp) +{ + int arm_podf; + int podf; + int vinc = 0; + int ret = 0; + int org_cpu_rate; + unsigned long rate = 0; + int gp_volt = 0; + u32 reg; + u32 reg1; + u32 en_sw_dvfs = 0; + unsigned long flags; + + if (cpu_wp_tbl[wp].pll_rate != cpu_wp_tbl[old_wp].pll_rate) { + org_cpu_rate = clk_get_rate(cpu_clk); + rate = cpu_wp_tbl[wp].cpu_rate; + + if (org_cpu_rate == rate) + return ret; + + gp_volt = cpu_wp_tbl[wp].cpu_voltage; + if (gp_volt == 0) + return ret; + + /*Set the voltage for the GP domain. */ + if (rate > org_cpu_rate) { + ret = regulator_set_voltage(core_regulator, gp_volt, + gp_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE\n"); + return ret; + } + udelay(dvfs_data->delay_time); + } + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + /* PLL_RELOCK, set ARM_FREQ_SHIFT_DIVIDER */ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); + /* Check if software_dvfs_en bit set */ + if ((reg & CCM_CDCR_SW_DVFS_EN) != 0) + en_sw_dvfs = CCM_CDCR_SW_DVFS_EN; + else + en_sw_dvfs = 0x0; + reg &= ~(CCM_CDCR_SW_DVFS_EN); + reg &= 0xFFFFFFFB; + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); + + setup_pll(); + /* START the GPC main control FSM */ + /* set VINC */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset); + reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + + if (rate > org_cpu_rate) + reg |= 1 << MXC_GPCVCR_VINC_OFFSET; + + reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) | + (1 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset); + + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK); + reg |= MXC_GPCCNTR_FUPD; + reg |= MXC_GPCCNTR_ADU; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + while (__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) + & 0x4000) + udelay(10); + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + if (rate < org_cpu_rate) { + ret = regulator_set_voltage(core_regulator, + gp_volt, gp_volt); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT SET GP VOLTAGE!!!!\n"); + return ret; + } + udelay(dvfs_data->delay_time); + } + /* set software_dvfs_en bit back to original setting*/ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); + reg &= ~(CCM_CDCR_SW_DVFS_EN); + reg |= en_sw_dvfs; + clk_set_rate(cpu_clk, rate); + } else { + podf = cpu_wp_tbl[wp].cpu_podf; + gp_volt = cpu_wp_tbl[wp].cpu_voltage; + + /* Change arm_podf only */ + /* set ARM_FREQ_SHIFT_DIVIDER */ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); + + /* Check if software_dvfs_en bit set */ + if ((reg & CCM_CDCR_SW_DVFS_EN) != 0) + en_sw_dvfs = CCM_CDCR_SW_DVFS_EN; + else + en_sw_dvfs = 0x0; + + reg &= ~(CCM_CDCR_SW_DVFS_EN | CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER); + reg |= CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER; + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); + + /* Get ARM_PODF */ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset); + arm_podf = reg & 0x07; + if (podf == arm_podf) { + printk(KERN_DEBUG + "No need to change freq and voltage!!!!\n"); + return 0; + } + + /* Check if FSVAI indicate freq up */ + if (podf < arm_podf) { + ret = regulator_set_voltage(core_regulator, + gp_volt, gp_volt); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT SET GP VOLTAGE!!!!\n"); + return 0; + } + udelay(dvfs_data->delay_time); + vinc = 1; + } else { + vinc = 0; + } + + arm_podf = podf; + /* Set ARM_PODF */ + reg &= 0xFFFFFFF8; + reg |= arm_podf; + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + + reg1 = __raw_readl(ccm_base + dvfs_data->ccm_cdhipr_offset); + if ((reg1 & 0x00010000) == 0) + __raw_writel(reg, + ccm_base + dvfs_data->ccm_cacrr_offset); + else { + printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n"); + return 0; + } + /* set VINC */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset); + reg &= + ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) | + (100 << MXC_GPCVCR_VCNT_OFFSET) | + (vinc << MXC_GPCVCR_VINC_OFFSET); + __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset); + + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg &= (~(MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD + | MXC_GPCCNTR_STRT)); + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg |= MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + + /* Wait for arm podf Enable */ + while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) & + MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) { + printk(KERN_DEBUG "Waiting arm_podf enabled!\n"); + udelay(10); + } + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + if (vinc == 0) { + ret = regulator_set_voltage(core_regulator, + gp_volt, gp_volt); + if (ret < 0) { + printk(KERN_DEBUG + "COULD NOT SET GP VOLTAGE!!!!\n"); + return ret; + } + udelay(dvfs_data->delay_time); + } + + /* Clear the ARM_FREQ_SHIFT_DIVIDER and */ + /* set software_dvfs_en bit back to original setting*/ + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); + reg &= ~(CCM_CDCR_SW_DVFS_EN | CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER); + reg |= en_sw_dvfs; + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); + } +#if defined(CONFIG_CPU_FREQ) + cpufreq_trig_needed = 1; +#endif + old_wp = wp; + return ret; +} + +static int start_dvfs(void) +{ + u32 reg, cpu_rate; + unsigned long flags; + + if (dvfs_core_is_active) + return 0; + + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + + clk_enable(dvfs_clk); + + dvfs_load_config(0); + + /* get current working point */ + cpu_rate = clk_get_rate(cpu_clk); + curr_wp = cpu_wp_nr - 1; + do { + if (cpu_rate <= cpu_wp_tbl[curr_wp].cpu_rate) + break; + } while (--curr_wp >= 0); + old_wp = curr_wp; + /* config reg GPC_CNTR */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + + reg &= ~MXC_GPCCNTR_GPCIRQM; + /* GPCIRQ=1, select ARM IRQ */ + reg |= MXC_GPCCNTR_GPCIRQ_ARM; + /* ADU=1, select ARM domain */ + reg |= MXC_GPCCNTR_ADU; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + + /* Set PREDIV bits */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + reg = (reg & ~(dvfs_data->prediv_mask)); + reg |= (dvfs_data->prediv_val) << (dvfs_data->prediv_offset); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + + /* Enable DVFS interrupt */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + /* FSVAIM=0 */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + /* Set MAXF, MINF */ + reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK)); + reg |= 1 << MXC_DVFSCNTR_MAXF_OFFSET; + /* Select ARM domain */ + reg |= MXC_DVFSCNTR_DVFIS; + /* Enable DVFS frequency adjustment interrupt */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + /* Set load tracking buffer register source */ + reg = (reg & ~MXC_DVFSCNTR_LTBRSR_MASK); + reg |= DVFS_LTBRSR; + /* Set DIV3CK */ + reg = (reg & ~(dvfs_data->div3ck_mask)); + reg |= (dvfs_data->div3ck_val) << (dvfs_data->div3ck_offset); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + + /* Enable DVFS */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + reg |= MXC_DVFSCNTR_DVFEN; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + + dvfs_core_is_active = 1; + + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + printk(KERN_DEBUG "DVFS is started\n"); + + return 0; +} + +/*! + * This function is called for module initialization. + * It sets up the DVFS hardware. + * It sets default values for DVFS thresholds and counters. The default + * values was chosen from a set of different reasonable values. They was tested + * and the default values in the driver gave the best results. + * More work should be done to find optimal values. + * + * @return 0 if successful; non-zero otherwise. + * + */ +static int init_dvfs_controller(void) +{ + /* DVFS loading config */ + dvfs_load_config(0); + + return 0; +} + +static irqreturn_t dvfs_irq(int irq, void *dev_id) +{ + u32 reg; + + /* Check if DVFS0 (ARM) id requesting for freqency/voltage update */ + if ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) + & MXC_GPCCNTR_DVFS0CR) == 0) + return IRQ_NONE; + + /* Mask DVFS irq */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + /* FSVAIM=1 */ + reg |= MXC_DVFSCNTR_FSVAIM; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + + /* Mask GPC1 irq */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + + schedule_delayed_work(&dvfs_core_handler, 0); + return IRQ_HANDLED; +} + +static void dvfs_core_work_handler(struct work_struct *work) +{ + u32 fsvai; + u32 reg; + u32 curr_cpu; + int ret = 0; + int maxf = 0, minf = 0; + int low_freq_bus_ready = 0; + int bus_incr = 0, cpu_dcr = 0; + + low_freq_bus_ready = low_freq_bus_used(); + + /* Check DVFS frequency adjustment interrupt status */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + fsvai = (reg & MXC_DVFSCNTR_FSVAI_MASK) >> MXC_DVFSCNTR_FSVAI_OFFSET; + /* Check FSVAI, FSVAI=0 is error */ + if (fsvai == FSVAI_FREQ_NOCHANGE) { + /* Do nothing. Freq change is not required */ + goto END; + } + curr_cpu = clk_get_rate(cpu_clk); + /* If FSVAI indicate freq down, + check arm-clk is not in lowest frequency 200 MHz */ + if (fsvai == FSVAI_FREQ_DECREASE) { + if (curr_cpu == cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) { + minf = 1; + if (low_bus_freq_mode) + goto END; + } else { + /* freq down */ + curr_wp++; + if (curr_wp >= cpu_wp_nr) { + curr_wp = cpu_wp_nr - 1; + goto END; + } + + if (curr_wp == cpu_wp_nr - 1 && !low_freq_bus_ready) { + minf = 1; + dvfs_load_config(1); + } else { + cpu_dcr = 1; + } + } + } else { + if (curr_cpu == cpu_wp_tbl[0].cpu_rate) { + maxf = 1; + goto END; + } else { + if (!high_bus_freq_mode && !cpu_is_mx50()) { + /* bump up LP freq first. */ + bus_incr = 1; + dvfs_load_config(2); + } else { + /* freq up */ + curr_wp = 0; + maxf = 1; + dvfs_load_config(0); + } + } + } + + low_freq_bus_ready = low_freq_bus_used(); + if ((curr_wp == cpu_wp_nr - 1) && (!low_bus_freq_mode) + && (low_freq_bus_ready) && !bus_incr) { + if (cpu_dcr) + ret = set_cpu_freq(curr_wp); + if (!cpu_dcr) { + set_low_bus_freq(); + dvfs_load_config(3); + } else { + dvfs_load_config(2); + cpu_dcr = 0; + } + } else { + if (!high_bus_freq_mode) + set_high_bus_freq(1); + if (!bus_incr) + ret = set_cpu_freq(curr_wp); + bus_incr = 0; + } + + +END: /* Set MAXF, MINF */ + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); + reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK)); + reg |= maxf << MXC_DVFSCNTR_MAXF_OFFSET; + reg |= minf << MXC_DVFSCNTR_MINF_OFFSET; + + /* Enable DVFS interrupt */ + /* FSVAIM=0 */ + reg = (reg & ~MXC_DVFSCNTR_FSVAIM); + reg |= FSVAI_FREQ_NOCHANGE; + /* LBFL=1 */ + reg = (reg & ~MXC_DVFSCNTR_LBFL); + reg |= MXC_DVFSCNTR_LBFL; + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); + /*Unmask GPC1 IRQ */ + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); + reg &= ~MXC_GPCCNTR_GPCIRQM; + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + +#if defined(CONFIG_CPU_FREQ) + if (cpufreq_trig_needed == 1) { + cpufreq_trig_needed = 0; + cpufreq_update_policy(0); + } +#endif +} + + +/*! + * This function disables the DVFS module. + */ +void stop_dvfs(void) +{ + u32 reg = 0; + unsigned long flags; + u32 curr_cpu; + + if (dvfs_core_is_active) { + + /* Mask dvfs irq, disable DVFS */ + reg = __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_CNTR); + /* FSVAIM=1 */ + reg |= MXC_DVFSCNTR_FSVAIM; + __raw_writel(reg, dvfs_data->membase + + MXC_DVFSCORE_CNTR); + + curr_wp = 0; + if (!high_bus_freq_mode) + set_high_bus_freq(1); + + curr_cpu = clk_get_rate(cpu_clk); + if (curr_cpu != cpu_wp_tbl[curr_wp].cpu_rate) { + set_cpu_freq(curr_wp); +#if defined(CONFIG_CPU_FREQ) + if (cpufreq_trig_needed == 1) { + cpufreq_trig_needed = 0; + cpufreq_update_policy(0); + } +#endif + } + spin_lock_irqsave(&mxc_dvfs_core_lock, flags); + + reg = __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_CNTR); + reg = (reg & ~MXC_DVFSCNTR_DVFEN); + __raw_writel(reg, dvfs_data->membase + + MXC_DVFSCORE_CNTR); + + spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); + + dvfs_core_is_active = 0; + + clk_disable(dvfs_clk); + } + + printk(KERN_DEBUG "DVFS is stopped\n"); +} + +void dump_dvfs_core_regs() +{ + struct timeval cur; + u32 diff = 0; + if (core_prev_intr.tv_sec == 0) + do_gettimeofday(&core_prev_intr); + else { + do_gettimeofday(&cur); + diff = (cur.tv_sec - core_prev_intr.tv_sec)*1000000 + + (cur.tv_usec - core_prev_intr.tv_usec); + core_prev_intr = cur; + } + if (diff < 90000) + printk(KERN_DEBUG "diff = %d\n", diff); + + printk(KERN_INFO "THRS = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS)); + printk(KERN_INFO "COUNT = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x04)); + printk(KERN_INFO "SIG1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x08)); + printk(KERN_INFO "SIG0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x0c)); + printk(KERN_INFO "GPC0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x10)); + printk(KERN_INFO "GPC1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x14)); + printk(KERN_INFO "GPBT = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x18)); + printk(KERN_INFO "EMAC = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x1c)); + printk(KERN_INFO "CNTR = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x20)); + printk(KERN_INFO "LTR0_0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x24)); + printk(KERN_INFO "LTR0_1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x28)); + printk(KERN_INFO "LTR1_0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x2c)); + printk(KERN_DEBUG "LTR1_1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x30)); + printk(KERN_INFO "PT0 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x34)); + printk(KERN_INFO "PT1 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x38)); + printk(KERN_INFO "PT2 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x3c)); + printk(KERN_INFO "PT3 = 0x%08x\n", + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x40)); +} + +static ssize_t downthreshold_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%u\n", dvfs_core_setpoint[0].downthr); +} + +static ssize_t downthreshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret = 0; + int val; + ret = sscanf(buf, "%u", &val); + dvfs_core_setpoint[0].downthr = val; + + return size; +} + +static ssize_t downcount_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%u\n", dvfs_core_setpoint[0].downcnt); +} + +static ssize_t downcount_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret = 0; + int val; + ret = sscanf(buf, "%u", &val); + dvfs_core_setpoint[0].downcnt = val; + + return size; +} + + +static ssize_t dvfs_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (dvfs_core_is_active) + return sprintf(buf, "DVFS is enabled\n"); + else + return sprintf(buf, "DVFS is disabled\n"); +} + +static ssize_t dvfs_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) { + if (start_dvfs() != 0) + printk(KERN_ERR "Failed to start DVFS\n"); + } else if (strstr(buf, "0") != NULL) + stop_dvfs(); + + return size; +} + +static ssize_t dvfs_regs_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (dvfs_core_is_active) + dump_dvfs_core_regs(); + return 0; +} + +static ssize_t dvfs_regs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (dvfs_core_is_active) + dump_dvfs_core_regs(); + return 0; + + return size; +} + +static DEVICE_ATTR(enable, 0644, dvfs_enable_show, dvfs_enable_store); +static DEVICE_ATTR(show_regs, 0644, dvfs_regs_show, dvfs_regs_store); + +static DEVICE_ATTR(down_threshold, 0644, downthreshold_show, + downthreshold_store); +static DEVICE_ATTR(down_count, 0644, downcount_show, downcount_store); + +/*! + * This is the probe routine for the DVFS driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + */ +static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) +{ + int err = 0; + struct resource *res; + + printk(KERN_INFO "mxc_dvfs_core_probe\n"); + dvfs_dev = &pdev->dev; + dvfs_data = pdev->dev.platform_data; + + INIT_DELAYED_WORK(&dvfs_core_handler, dvfs_core_work_handler); + + pll1_sw_clk = clk_get(NULL, "pll1_sw_clk"); + if (IS_ERR(pll1_sw_clk)) { + printk(KERN_INFO "%s: failed to get pll1_sw_clk\n", __func__); + return PTR_ERR(pll1_sw_clk); + } + + cpu_clk = clk_get(NULL, dvfs_data->clk1_id); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); + return PTR_ERR(cpu_clk); + } + + dvfs_clk = clk_get(NULL, dvfs_data->clk2_id); + if (IS_ERR(dvfs_clk)) { + printk(KERN_ERR "%s: failed to get dvfs clock\n", __func__); + return PTR_ERR(dvfs_clk); + } + + core_regulator = regulator_get(NULL, dvfs_data->reg_id); + if (IS_ERR(core_regulator)) { + clk_put(cpu_clk); + clk_put(dvfs_clk); + printk(KERN_ERR "%s: failed to get gp regulator\n", __func__); + return PTR_ERR(core_regulator); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + err = -ENODEV; + goto err1; + } + dvfs_data->membase = ioremap(res->start, res->end - res->start + 1); + /* + * Request the DVFS interrupt + */ + dvfs_data->irq = platform_get_irq(pdev, 0); + if (dvfs_data->irq < 0) { + err = dvfs_data->irq; + goto err2; + } + + /* request the DVFS interrupt */ + err = request_irq(dvfs_data->irq, dvfs_irq, IRQF_SHARED, "dvfs", + dvfs_dev); + if (err) { + printk(KERN_ERR + "DVFS: Unable to attach to DVFS interrupt,err = %d", + err); + goto err2; + } + + clk_enable(dvfs_clk); + err = init_dvfs_controller(); + if (err) { + printk(KERN_ERR "DVFS: Unable to initialize DVFS"); + return err; + } + clk_disable(dvfs_clk); + + err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_enable.attr); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for DVFS"); + goto err3; + } + + err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_show_regs.attr); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for DVFS"); + goto err3; + } + + + err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_threshold.attr); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for DVFS"); + goto err3; + } + + err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_count.attr); + if (err) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for DVFS"); + goto err3; + } + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + old_wp = 0; + curr_wp = 0; + dvfs_core_resume = 0; + cpufreq_trig_needed = 0; + + return err; +err3: + free_irq(dvfs_data->irq, dvfs_dev); +err2: + iounmap(dvfs_data->membase); +err1: + dev_err(&pdev->dev, "Failed to probe DVFS CORE\n"); + return err; +} + +/*! + * This function is called to put DVFS in a low power state. + * + * @param pdev the device structure + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_dvfs_core_suspend(struct platform_device *pdev, + pm_message_t state) +{ + if (dvfs_core_is_active) { + dvfs_core_resume = 1; + stop_dvfs(); + } + + return 0; +} + +/*! + * This function is called to resume the MU from a low power state. + * + * @param dev the device structure + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ +static int mxc_dvfs_core_resume(struct platform_device *pdev) +{ + if (dvfs_core_resume) { + dvfs_core_resume = 0; + start_dvfs(); + } + + return 0; +} + +static struct platform_driver mxc_dvfs_core_driver = { + .driver = { + .name = "mxc_dvfs_core", + }, + .probe = mxc_dvfs_core_probe, + .suspend = mxc_dvfs_core_suspend, + .resume = mxc_dvfs_core_resume, +}; + +static int __init dvfs_init(void) +{ + if (platform_driver_register(&mxc_dvfs_core_driver) != 0) { + printk(KERN_ERR "mxc_dvfs_core_driver register failed\n"); + return -ENODEV; + } + + dvfs_core_is_active = 0; + printk(KERN_INFO "DVFS driver module loaded\n"); + return 0; +} + +static void __exit dvfs_cleanup(void) +{ + stop_dvfs(); + + /* release the DVFS interrupt */ + free_irq(dvfs_data->irq, dvfs_dev); + + sysfs_remove_file(&dvfs_dev->kobj, &dev_attr_enable.attr); + + /* Unregister the device structure */ + platform_driver_unregister(&mxc_dvfs_core_driver); + + iounmap(ccm_base); + iounmap(dvfs_data->membase); + clk_put(cpu_clk); + clk_put(dvfs_clk); + + dvfs_core_is_active = 0; + printk(KERN_INFO "DVFS driver module unloaded\n"); + +} + +module_init(dvfs_init); +module_exit(dvfs_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DVFS driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/dvfs_per.c b/arch/arm/plat-mxc/dvfs_per.c new file mode 100644 index 000000000000..84dc200e397f --- /dev/null +++ b/arch/arm/plat-mxc/dvfs_per.c @@ -0,0 +1,936 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dvfs_per.c + * + * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module. + * + * Upon initialization, the DVFS driver initializes the DVFS hardware + * sets up driver nodes attaches to the DVFS interrupt and initializes internal + * data structures. When the DVFS interrupt occurs the driver checks the cause + * of the interrupt (lower frequency, increase frequency or emergency) and + * changes the CPU voltage according to translation table that is loaded into + * the driver. + * + * @ingroup PM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#if defined(CONFIG_ARCH_MX37) +#include +#endif + +/* DVFS PER */ +#define MXC_DVFS_PER_LTR0 0x00 +#define MXC_DVFS_PER_LTR1 0x04 +#define MXC_DVFS_PER_LTR2 0x08 +#define MXC_DVFS_PER_LTR3 0x0C +#define MXC_DVFS_PER_LTBR0 0x10 +#define MXC_DVFS_PER_LTBR1 0x14 +#define MXC_DVFS_PER_PMCR0 0x18 +#define MXC_DVFS_PER_PMCR1 0x1C + +#define DRIVER_NAME "DVFSPER" +#define DVFS_PER_DEBUG 0 + +static int dvfs_per_stop; +static int dvfs_per_low_freq; +static int dvfs_per_suspended; +static volatile int freq_increased; +static int cur_setpoint; +static struct delayed_work dvfs_per_work; +static struct clk *dvfs_clk; +static struct clk *main_bus_clk; +static struct clk *pll2; +static struct clk *lpapm; +static struct clk *cpu_clk; +static struct clk *axi_b_clk; +static struct clk *ahb_clk; +static struct clk *ddr_hf_clk; +static struct regulator *lp_regulator; + +/* Flag used to indicate if dvfs_per is active. */ +static int dvfs_per_is_active; +static int dvfs_per_is_paused; +static int ipu_freq_scaled; + +struct dvfsper_device *dvfsper_device_data; +/* DVFS platform data pointer */ +struct mxc_dvfsper_data *dvfsper_plt_data; +struct timeval prev_intr; + +int start_dvfs_per(void); +void stop_dvfs_per(void); +int dvfs_per_active(void); +int dvfs_per_divider_active(void); +int dvfs_per_pixel_clk_limit(void); + +extern int low_bus_freq_mode; +extern int bus_freq_scaling_is_active; + + +/*! + * In case the MXC device has multiple DVFS modules, this structure is used to + * store information specific to each DVFS module. + */ +struct dvfsper_device { + /* DVFS delayed work */ + struct delayed_work dvfs_work; + /* DVFS regulator */ + struct regulator *dvfs_reg; + /* DVFS clock */ + struct clk *dvfs_clk; + /* The interrupt number used by the DVFS device */ + int irq; +}; +struct dvfs_wp dvfs_per_setpoint[] = {{33, 7, 33, 20, 40, 0x10}, + {18, 0, 33, 25, 10, 0x10}, + /* When LP is at 24MHz */ + {8, 0, 10, 5, 5, 0x2E},}; + +enum { + FSVAI_FREQ_NOCHANGE = 0x0, + FSVAI_FREQ_INCREASE, + FSVAI_FREQ_DECREASE, + FSVAI_FREQ_EMERG, +}; + +#define LOW_BUS_FREQ 24000000 + +DEFINE_SPINLOCK(mxc_dvfs_per_lock); + +static void dvfs_per_load_config(void) +{ + u32 reg; + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); + reg &= ~MXC_DVFSLTR0_UPTHR_MASK; + reg &= ~MXC_DVFSLTR0_DNTHR_MASK; + reg |= dvfs_per_setpoint[cur_setpoint].upthr << + MXC_DVFSLTR0_UPTHR_OFFSET; + reg |= dvfs_per_setpoint[cur_setpoint].downthr << + MXC_DVFSLTR0_DNTHR_OFFSET; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); + reg &= ~MXC_DVFSLTR1_PNCTHR_MASK; + reg &= ~MXC_DVFSLTR1_DNCNT_MASK; + reg &= ~MXC_DVFSLTR1_UPCNT_MASK; + reg |= dvfs_per_setpoint[cur_setpoint].downcnt << + MXC_DVFSLTR1_DNCNT_OFFSET; + reg |= dvfs_per_setpoint[cur_setpoint].upcnt << + MXC_DVFSLTR1_UPCNT_OFFSET; + reg |= dvfs_per_setpoint[cur_setpoint].panicthr << + MXC_DVFSLTR1_PNCTHR_OFFSET; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); + + reg = dvfs_per_setpoint[cur_setpoint].emac << + MXC_DVFSLTR2_EMAC_OFFSET; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR2); +} + +/*! + * This function is called for module initialization. + * It sets up the DVFS hardware. + * It sets default values for DVFS thresholds and counters. The default + * values was chosen from a set of different reasonable values. They was tested + * and the default values in the driver gave the best results. + * More work should be done to find optimal values. + * + * @return 0 if successful; non-zero otherwise. + * + */ +static int init_dvfs_per_controller(void) +{ + u32 reg; + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); + /* DIV3CLK */ + reg &= ~dvfsper_plt_data->div3_mask; + reg |= (dvfsper_plt_data->div3_div << + dvfsper_plt_data->div3_offset); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); + /* Set load tracking buffer register source */ + reg &= ~MXC_DVFSLTR1_LTBRSR; + reg |= MXC_DVFSLTR1_LTBRSR; + reg &= ~MXC_DVFSLTR1_LTBRSH; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); + + /* Enable all the peripheral signals, but VPU and IPU panic*/ + __raw_writel(0x30000, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR1); + /* Disable weighted load tracking signals */ + __raw_writel(0, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR3); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + reg &= ~MXC_DVFSPMCR0_DVFEV; + reg |= MXC_DVFSPMCR0_LBMI; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + + /* DVFS loading config */ + dvfs_per_load_config(); + return 0; +} + +#if DVFS_PER_DEBUG +static void dump_dvfs_per_regs(void) +{ + struct timeval cur; + u32 diff = 0; + if (prev_intr.tv_sec == 0) + do_gettimeofday(&prev_intr); + else { + do_gettimeofday(&cur); + diff = (cur.tv_sec - prev_intr.tv_sec)*1000000 + + (cur.tv_usec - prev_intr.tv_usec); + prev_intr = cur; + } + if (diff < 90000) + printk(KERN_INFO "diff = %d\n", diff); + + printk(KERN_INFO "LTRO = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0)); + printk(KERN_INFO "LTR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1)); + printk(KERN_INFO "LTR2 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR2)); + printk(KERN_INFO "LTR3 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR3)); + printk(KERN_INFO "LBTR0 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTBR0)); + printk(KERN_INFO "LBTR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTBR1)); + printk(KERN_INFO "PMCR0 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0)); + printk(KERN_INFO "PMCR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR1)); +} +#endif + +static irqreturn_t dvfs_per_irq(int irq, void *dev_id) +{ + u32 reg; + + /* Check if DVFS1 (PER) id requesting for freqency/voltage update */ + if ((__raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr) & + MXC_GPCCNTR_DVFS1CR) == 0) + return IRQ_NONE; + /* Mask DVFS irq */ + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + /* FSVAIM=1 */ + reg |= MXC_DVFSPMCR0_FSVAIM; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + /* Mask GPC1 irq */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + if (reg & MXC_DVFSPMCR0_LBFL) { + /* clear LBFL */ + reg = (reg & ~MXC_DVFSPMCR0_LBFL); + reg |= MXC_DVFSPMCR0_LBFL; + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + } + schedule_delayed_work(&dvfs_per_work, 0); + return IRQ_HANDLED; +} + +static void dvfs_per_handler(struct work_struct *work) +{ + u32 fsvai; + u32 reg; + u32 ret; + unsigned long flags; + int retry = 20; + + /* Check DVFS frequency adjustment interrupt status */ + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + fsvai = (reg & MXC_DVFSPMCR0_FSVAI_MASK) >> MXC_DVFSPMCR0_FSVAI_OFFSET; + /* Check FSVAI, FSVAI=0 is error */ + if (fsvai == FSVAI_FREQ_NOCHANGE) { + /* Do nothing. Freq change is not required */ + goto END; + } + +#if DVFS_PER_DEBUG + dump_dvfs_per_regs(); +#endif + /* If FSVAI indicate freq down. */ + if (fsvai == FSVAI_FREQ_DECREASE) { + if (cpu_is_mx51()) { + /*Change the DDR freq to 133Mhz. */ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, 133000000)); + } + +#ifndef DVFS_SW_WORKAROUND + spin_lock_irqsave(&mxc_dvfs_per_lock, flags); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + reg &= ~MXC_DVFSPMCR0_UDCS; + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + + /* Set the peripheral divider */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK); + reg |= MXC_GPCCNTR_FUPD; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->gpc_vcr_reg_addr); + reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) | + (1 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, dvfsper_plt_data->gpc_vcr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + retry = 10; + while ((__raw_readl( + dvfsper_plt_data->gpc_cntr_reg_addr) & 0x4000) + && retry > 0) { + udelay(10); + retry--; + } + spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); +#else + /*Set the frequencies manually */ + rate = clk_get_rate(axi_b_clk); + clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, rate/2)); + + rate = clk_get_rate(ahb_clk); + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, rate/2)); +#endif + dvfs_per_low_freq = 1; + if (clk_get_rate(main_bus_clk) == LOW_BUS_FREQ) { + cur_setpoint = 2; + } else { +#if defined(CONFIG_ARCH_MX37) + dptc_suspend(DPTC_LP_ID); +#endif + cur_setpoint = 1; +#ifndef DVFS_SW_WORKAROUND + clk_set_parent(main_bus_clk, clk_get(NULL, "pll2")); +#endif + } +#ifndef DVFS_SW_WORKAROUND + /* Drop the LP domain voltage */ + ret = regulator_set_voltage(lp_regulator, + dvfsper_plt_data->lp_low, + dvfsper_plt_data->lp_low); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET LP VOLTAGE\n"); + return; + } + udelay(100); +#endif + dvfs_per_load_config(); + } else if ((fsvai == FSVAI_FREQ_INCREASE) || + (fsvai == FSVAI_FREQ_EMERG)) { +#ifndef DVFS_SW_WORKAROUND + /* Increase the LP domain voltage first. */ + ret = regulator_set_voltage(lp_regulator, + dvfsper_plt_data->lp_high, + dvfsper_plt_data->lp_high); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET LP VOLTAGE\n"); + return; + } + udelay(100); +#endif + +#ifndef DVFS_SW_WORKAROUND + spin_lock_irqsave(&mxc_dvfs_per_lock, flags); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + reg |= MXC_DVFSPMCR0_UDCS; + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK); + reg |= MXC_GPCCNTR_FUPD; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->gpc_vcr_reg_addr); + reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= (1 << MXC_GPCVCR_VINC_OFFSET | + 1 << MXC_GPCVCR_VCNTU_OFFSET | + 1 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, dvfsper_plt_data->gpc_vcr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~MXC_GPCCNTR_ADU; + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + retry = 10; + while ((__raw_readl( + dvfsper_plt_data->gpc_cntr_reg_addr) & 0x4000) + && retry > 0) { + udelay(10); + retry--; + } + spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); + + if (retry < 0) + printk(KERN_ERR "****ERROR- DVFS\n"); +#else + /*Set the frequencies manually */ + rate = clk_get_rate(axi_b_clk); + clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, 130000000)); + rate = clk_get_rate(ahb_clk); + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, 130000000)); +#endif + if (cpu_is_mx51()) { + /*Change the DDR freq to 200Mhz. */ + clk_set_rate(ddr_hf_clk, clk_round_rate(ddr_hf_clk, + 200000000)); + } + dvfs_per_low_freq = 0; + if (clk_get_rate(main_bus_clk) == LOW_BUS_FREQ) { + cur_setpoint = 2; + } else { + cur_setpoint = 0; +#if defined(CONFIG_ARCH_MX37) + dptc_resume(DPTC_LP_ID); +#endif +#ifndef DVFS_SW_WORKAROUND + clk_set_parent(main_bus_clk, clk_get(NULL, "pll2")); +#endif + } + dvfs_per_load_config(); + freq_increased = 1; + } + +END: +#if DVFS_PER_DEBUG + dump_dvfs_per_regs(void)(); +#endif + if (dvfs_per_is_active) { + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + /* Enable dVFS interrupt */ + /* FSVAIM=0 */ + reg &= ~MXC_DVFSPMCR0_FSVAI_MASK; + reg |= FSVAI_FREQ_NOCHANGE; + reg = (reg & ~MXC_DVFSPMCR0_FSVAIM); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + /*Unmask GPC1 IRQ */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~MXC_GPCCNTR_GPCIRQM; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + } +} + +static void force_freq_change(void) +{ + u32 reg; + int retry = 50; + + freq_increased = 0; + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + reg |= MXC_DVFSPMCR0_UDCS; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + + if (cpu_is_mx51()) { + /*Change the DDR freq to 133Mhz. */ + clk_set_rate(ddr_hf_clk, clk_round_rate(ddr_hf_clk, 200000000)); + } + +#ifndef DVFS_SW_WORKAROUND + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg |= MXC_GPCCNTR_FUPD; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + reg = __raw_readl(dvfsper_plt_data->gpc_vcr_reg_addr); + reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | + MXC_GPCVCR_VCNT_MASK); + reg |= (1 << MXC_GPCVCR_VINC_OFFSET | + 1 << MXC_GPCVCR_VCNTU_OFFSET | + 20 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, dvfsper_plt_data->gpc_vcr_reg_addr); + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + reg &= ~MXC_GPCCNTR_ADU; + reg |= MXC_GPCCNTR_STRT; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + while ((__raw_readl( + dvfsper_plt_data->gpc_cntr_reg_addr) & 0x4000) + && retry > 0) { + udelay(30); + retry--; + } + freq_increased = 1; + if (retry <= 0) + printk(KERN_ERR "Cannot stop DVFS-PER\n"); +#else + /* Set the frequencies manually */ + rate = clk_get_rate(axi_b_clk); + clk_set_rate(axi_b_clk, clk_round_rate(axi_b_clk, 130000000)); + rate = clk_get_rate(ahb_clk); + clk_set_rate(ahb_clk, clk_round_rate(ahb_clk, 130000000)); +#endif + dvfs_per_low_freq = 0; + +#ifndef DVFS_SW_WORKAROUND + clk_set_parent(main_bus_clk, pll2); +#endif +} + +static int start(void) +{ + u32 reg; + unsigned long flags; + + if (dvfs_per_is_active || dvfs_per_stop) + return 0; + + if (low_bus_freq_mode) + return 0; + + if (bus_freq_scaling_is_active) { + dvfs_per_is_paused = 1; + printk(KERN_INFO "Cannot start DVFS-PER since bus_freq_scaling\ + is active\n"); + return 0; + } + + if (!dvfs_per_pixel_clk_limit()) { + dvfs_per_is_paused = 1; + printk(KERN_INFO "Cannot start DVFS-PER since pixel clock is\ + above 60MHz or divider is not even\n"); + return 0; + } + + stop_sdram_autogating(); + + spin_lock_irqsave(&mxc_dvfs_per_lock, flags); + + clk_enable(dvfs_clk); + + cur_setpoint = 0; + init_dvfs_per_controller(); + + /* config reg GPC_CNTR */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + /* ADU=0, select PER domain */ + reg &= ~MXC_GPCCNTR_ADU; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + /* Select ARM domain */ + reg |= MXC_DVFSPMCR0_DVFIS; + /* Set the UDCS bit */ + reg |= MXC_DVFSPMCR0_UDCS; + /* Enable DVFS interrupt */ + /* FSVAIM=0 */ + reg &= ~MXC_DVFSPMCR0_FSVAIM; + /*Set the FSVAI to no_freq_change */ + reg &= ~MXC_DVFSPMCR0_FSVAI_MASK; + reg |= FSVAI_FREQ_NOCHANGE << MXC_DVFSPMCR0_FSVAI_OFFSET; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + + /* config reg GPC_CNTR */ + reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); + /* GPCIRQ=1, select ARM IRQ */ + reg |= MXC_GPCCNTR_GPCIRQ_ARM; + reg &= ~MXC_GPCCNTR_GPCIRQM; + __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); + + /* Enable DVFS */ + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + reg |= MXC_DVFSPMCR0_DVFEN; + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); + + dvfs_per_is_active = 1; + spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); + + printk(KERN_DEBUG "DVFS PER is started\n"); + + return 0; +} + +/*! + * This function disables the DVFS module. + */ +static void stop(void) +{ + u32 reg = 0; + unsigned long flags; + u32 ret = 0; + + if (dvfs_per_is_active) { + dvfs_per_is_active = 0; +#ifndef DVFS_SW_WORKAROUND + /* Increase the LP domain voltage first. */ + ret = regulator_set_voltage( + lp_regulator, dvfsper_plt_data->lp_high, + dvfsper_plt_data->lp_high); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET LP VOLTAGE\n"); + return; + } + udelay(100); +#endif + + spin_lock_irqsave(&mxc_dvfs_per_lock, flags); + + /* Mask dvfs irq, disable DVFS */ + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + /* FSVAIM=1 */ + reg |= MXC_DVFSPMCR0_FSVAIM; + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + + if (cur_setpoint != 0) + force_freq_change(); + + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + reg = (reg & ~MXC_DVFSPMCR0_DVFEN); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); + + spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); + clk_disable(dvfs_clk); + + start_sdram_autogating(); + } +} + + +int dvfs_per_active() +{ + return dvfs_per_is_active; +} + +int dvfs_per_divider_active() +{ + return dvfs_per_low_freq; +} + +int dvfs_per_pixel_clk_limit() +{ + struct clk *disp0_pixel_clk; + struct clk *disp1_pixel_clk; + int disp0_rate = 0; + int disp1_rate = 0; + int div1 = 0; + int div2 = 0; + int even_div1 = 1; + int even_div2 = 1; + + disp0_pixel_clk = clk_get(NULL, "pixel_clk.0"); + disp1_pixel_clk = clk_get(NULL, "pixel_clk.1"); + + if (disp0_pixel_clk != NULL) + disp0_rate = clk_get_rate(disp0_pixel_clk); + + if (disp1_pixel_clk != NULL) + disp1_rate = clk_get_rate(disp1_pixel_clk); + + /* DVFS-PER will not work if pixel clock divider is odd */ + if (disp0_rate != 0) + div1 = (clk_get_rate( + clk_get_parent(disp0_pixel_clk)) * 10) / disp0_rate; + + if ((div1 % 2) || ((div1 / 10) % 2)) + even_div1 = 0; + + if ((div2 % 2) || ((div2 / 10) % 2)) + even_div2 = 0; + + if (disp1_rate != 0) + div2 = (clk_get_rate( + clk_get_parent(disp1_pixel_clk)) * 10) / disp1_rate; + + if (((disp0_rate < DVFS_MAX_PIX_CLK && even_div1) || + !clk_get_usecount(disp0_pixel_clk)) && + ((disp1_rate < DVFS_MAX_PIX_CLK && even_div2) || + !clk_get_usecount(disp1_pixel_clk))) + ipu_freq_scaled = 1; + else + ipu_freq_scaled = 0; + + clk_put(disp0_pixel_clk); + clk_put(disp1_pixel_clk); + + return ipu_freq_scaled; +} + +int start_dvfs_per(void) +{ + if (dvfs_per_is_paused) { + dvfs_per_is_paused = 0; + return start(); + } + return 0; +} + +void stop_dvfs_per(void) +{ + if (dvfs_per_is_active) { + dvfs_per_is_paused = 1; + stop(); + } +} + +/*! + * Enable DVFS Peripheral + * + */ +int dvfs_enable(struct device *dev) +{ + if (dvfs_per_is_active) + return 0; + return start(); +} + +static ssize_t dvfsper_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) { + dvfs_per_stop = 0; + if (dvfs_enable(dev) != 0) + printk(KERN_ERR "Failed to start DVFS\n"); + } else if (strstr(buf, "0") != NULL) { + dvfs_per_stop = 1; + stop(); + } + return size; +} + +static ssize_t dvfsper_status_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int size = 0; + + if (dvfs_per_is_active) + size = sprintf(buf, "DVFS PER is enabled\n"); + else + size = sprintf(buf, "DVFS PEr is disabled\n"); + + return size; +} + +static DEVICE_ATTR(enable, 0644, dvfsper_status_show, dvfsper_enable_store); + +/*! + * This is the probe routine for the DVFS PER driver. + * + * @param pdev The platform device structure + * + * @return The function returns 0 on success + * + */ +static int __devinit mxc_dvfsper_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *res; + struct mxc_dvfsper_data *dvfsper_data = pdev->dev.platform_data; + + if (dvfsper_data == NULL) { + printk(KERN_ERR "DVFS: Pointer to DVFS data is NULL\ + not started\n"); + return -1; + } + + /* Set driver data */ + platform_set_drvdata(pdev, dvfsper_device_data); + + dvfsper_plt_data = pdev->dev.platform_data; + dvfsper_device_data = kzalloc(sizeof(struct dvfsper_device), + GFP_KERNEL); + if (!dvfsper_device_data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + dvfsper_plt_data->membase = ioremap(res->start, + res->end - res->start + 1); + + /* + * Request the DVFSPER interrupt + */ + dvfsper_device_data->irq = platform_get_irq(pdev, 0); + if (dvfsper_device_data->irq < 0) { + ret = dvfsper_device_data->irq; + goto err1; + } + + ret = + request_irq(dvfsper_device_data->irq, dvfs_per_irq, IRQF_SHARED, + pdev->name, &pdev->dev); + if (ret) { + printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt\n"); + goto err1; + } + + lp_regulator = regulator_get(NULL, dvfsper_data->reg_id); + if (IS_ERR(lp_regulator)) { + printk(KERN_ERR "%s: failed to get lp regulator\n", __func__); + return PTR_ERR(lp_regulator); + } + + INIT_DELAYED_WORK(&dvfs_per_work, dvfs_per_handler); + + main_bus_clk = clk_get(NULL, "main_bus_clk"); + pll2 = clk_get(NULL, "pll2"); + lpapm = clk_get(NULL, "lp_apm"); + cpu_clk = clk_get(NULL, "cpu_clk"); + ahb_clk = clk_get(NULL, "ahb_clk"); + axi_b_clk = clk_get(NULL, "axi_b_clk"); + + if (cpu_is_mx51()) + ddr_hf_clk = clk_get(NULL, "ddr_hf_clk"); + + dvfsper_device_data->dvfs_clk = clk_get(NULL, dvfsper_data->clk_id); + dvfs_clk = dvfsper_device_data->dvfs_clk; + + ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_enable.attr); + + if (ret) { + printk(KERN_ERR + "DVFS: Unable to register sysdev entry for dvfs"); + goto err1; + } + + return 0; +err1: + dev_err(&pdev->dev, "Failed to probe DVFS\n"); + kfree(dvfsper_device_data); + + return ret; +} + +/*! + * This function is called to put DVFS in a low power state. + * + * @param pdev the device structure + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_dvfs_suspend(struct platform_device *pdev, + pm_message_t state) +{ + if (dvfs_per_is_active) { + stop_dvfs_per(); + dvfs_per_suspended = 1; + } + return 0; +} + +/*! + * This function is called to resume the DVFS from a low power state. + * + * @param dev the device structure + * @param level the stage in device suspension process that we want the + * device to be put in + * + * @return The function always returns 0. + */ +static int mxc_dvfs_resume(struct platform_device *pdev) +{ + if (dvfs_per_suspended) { + dvfs_per_suspended = 0; + return start_dvfs_per(); + } + + return 0; +} + +static struct platform_driver mxc_dvfsper_driver = { + .driver = { + .name = "mxc_dvfsper", + .owner = THIS_MODULE, + }, + .probe = mxc_dvfsper_probe, + .suspend = mxc_dvfs_suspend, + .resume = mxc_dvfs_resume, +}; + +static int __init dvfs_per_init(void) +{ + int err = 0; + + if (platform_driver_register(&mxc_dvfsper_driver) != 0) { + printk(KERN_ERR "mxc_dvfsper_driver register failed\n"); + return -ENODEV; + } + printk(KERN_INFO "DVFS PER driver module loaded\n"); + + return err; +} + +static void __exit dvfs_per_cleanup(void) +{ + stop_dvfs_per(); + + /* release the DVFS interrupt */ + free_irq(dvfsper_device_data->irq, NULL); + + clk_put(dvfs_clk); + clk_put(main_bus_clk); + clk_put(pll2); + clk_put(lpapm); + clk_put(cpu_clk); + clk_put(ahb_clk); + clk_put(axi_b_clk); + if (cpu_is_mx51()) + clk_put(ddr_hf_clk); + + /* Unregister the device structure */ + platform_driver_unregister(&mxc_dvfsper_driver); +} + +module_init(dvfs_per_init); +module_exit(dvfs_per_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DVFS PERIPHERAL driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 9ebbd31fe033..985787da2cd0 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -20,9 +20,11 @@ */ #include +#include #include #include #include +#include #include #include @@ -119,6 +121,12 @@ static int gpio_set_irq_type(u32 irq, u32 type) return -EINVAL; } + /* set the correct irq handler */ + if (type & IRQ_TYPE_EDGE_BOTH) + set_irq_handler(irq, handle_edge_irq); + else if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + set_irq_handler(irq, handle_level_irq); + reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ bit = gpio & 0xf; val = __raw_readl(reg) & ~(0x3 << (bit << 1)); @@ -174,11 +182,18 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; + u32 mask = 0xFFFFFFFF; struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); - irq_stat = __raw_readl(port->base + GPIO_ISR) & - __raw_readl(port->base + GPIO_IMR); + if (port->irq_high) { + if (irq == port->irq) + mask = 0x0000FFFF; + else + mask = 0xFFFF0000; + } + irq_stat = __raw_readl(port->base + GPIO_ISR) & + (__raw_readl(port->base + GPIO_IMR) & mask); mxc_gpio_irq_handler(port, irq_stat); } @@ -201,11 +216,44 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) } } +/* + * Set interrupt number "irq" in the GPIO as a wake-up source. + * While system is running all registered GPIO interrupts need to have + * wake-up enabled. When system is suspended, only selected GPIO interrupts + * need to have wake-up enabled. + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * @return This function returns 0 on success. + */ +static int gpio_set_wake_irq(u32 irq, u32 enable) +{ + u32 gpio = irq_to_gpio(irq); + u32 gpio_idx = gpio & 0x1F; + struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32]; + + if (enable) { + port->suspend_wakeup |= (1 << gpio_idx); + if (port->irq_high && (gpio_idx >= 16)) + enable_irq_wake(port->irq_high); + else + enable_irq_wake(port->irq); + } else { + port->suspend_wakeup &= ~(1 << gpio_idx); + if (port->irq_high && (gpio_idx >= 16)) + disable_irq_wake(port->irq_high); + else + disable_irq_wake(port->irq); + } + + return 0; +} + static struct irq_chip gpio_irq_chip = { .ack = gpio_ack_irq, .mask = gpio_mask_irq, .unmask = gpio_unmask_irq, .set_type = gpio_set_irq_type, + .set_wake = gpio_set_wake_irq, }; static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, @@ -265,6 +313,7 @@ static int mxc_gpio_direction_output(struct gpio_chip *chip, int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) { int i, j; + int ret = 0; /* save for local usage */ mxc_gpio_ports = port; @@ -296,10 +345,14 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) /* its a serious configuration bug when it fails */ BUG_ON( gpiochip_add(&port[i].chip) < 0 ); - if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { + if (!cpu_is_mx2() || cpu_is_mx25()) { /* setup one handler for each entry */ set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); set_irq_data(port[i].irq, &port[i]); + if (port[i].irq_high) { + set_irq_chained_handler(port[i].irq_high, mx3_gpio_irq_handler); + set_irq_data(port[i].irq_high, &port[i]); + } } } @@ -309,5 +362,103 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) set_irq_data(port[0].irq, port); } + return ret; +} + +#ifdef CONFIG_PM +/*! + * This function puts the GPIO in low-power mode/state. + * All the interrupts that are enabled are first saved. + * Only those interrupts which registers as a wake source by calling + * enable_irq_wake are enabled. All other interrupts are disabled. + * + * @param dev the system device structure used to give information + * on GPIO to suspend + * @param mesg the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_gpio_suspend(struct sys_device *dev, pm_message_t mesg) +{ + int i; + struct mxc_gpio_port *port = mxc_gpio_ports; + + for (i = 0; i < gpio_table_size; i++) { + void __iomem *isr_reg; + void __iomem *imr_reg; + + isr_reg = port[i].base + GPIO_ISR; + imr_reg = port[i].base + GPIO_IMR; + + if (__raw_readl(isr_reg) & port[i].suspend_wakeup) + return -EPERM; + + port[i].saved_wakeup = __raw_readl(imr_reg); + __raw_writel(port[i].suspend_wakeup, imr_reg); + } + return 0; } + +/*! + * This function brings the GPIO back from low-power state. + * All the interrupts enabled before suspension are re-enabled from + * the saved information. + * + * @param dev the system device structure used to give information + * on GPIO to resume + * + * @return The function always returns 0. + */ +static int mxc_gpio_resume(struct sys_device *dev) +{ + int i; + struct mxc_gpio_port *port = mxc_gpio_ports; + + for (i = 0; i < gpio_table_size; i++) { + void __iomem *isr_reg; + void __iomem *imr_reg; + + isr_reg = port[i].base + GPIO_ISR; + imr_reg = port[i].base + GPIO_IMR; + + __raw_writel(port[i].saved_wakeup, imr_reg); + } + + return 0; +} +#else +#define mxc_gpio_suspend NULL +#define mxc_gpio_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct sysdev_class mxc_gpio_sysclass = { + .name = "mxc_gpio", + .suspend = mxc_gpio_suspend, + .resume = mxc_gpio_resume, +}; + +/*! + * This structure represents GPIO as a system device. + * System devices follow a slightly different driver model. + * They don't need to do dynammic driver binding, can't be probed, + * and don't reside on any type of peripheral bus. + * So, it is represented and treated a little differently. + */ +static struct sys_device mxc_gpio_device = { + .id = 0, + .cls = &mxc_gpio_sysclass, +}; + +static int gpio_sysdev_init(void) +{ + int ret = sysdev_class_register(&mxc_gpio_sysclass); + if (ret) + return ret; + return sysdev_register(&mxc_gpio_device); +} +arch_initcall(gpio_sysdev_init); + diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h new file mode 100644 index 000000000000..b6494e5fa219 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h @@ -0,0 +1,18 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_3DS_DB_H__ +#define __ASM_ARCH_MXC_3DS_DB_H__ + +extern int __init mxc_expio_init(u32 base, u32 p_irq); + +#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h new file mode 100644 index 000000000000..320fd7d11495 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/arc_otg.h @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_ARC_OTG_H__ +#define __ASM_ARCH_MXC_ARC_OTG_H__ + +#ifdef CONFIG_ARCH_MX3 +extern volatile u32 *mx3_usb_otg_addr; +#define OTG_BASE_ADDR mx3_usb_otg_addr +#endif +#define USB_OTGREGS_BASE (OTG_BASE_ADDR + 0x000) +#define USB_H1REGS_BASE (OTG_BASE_ADDR + 0x200) +#define USB_H2REGS_BASE (OTG_BASE_ADDR + 0x400) +#ifdef CONFIG_ARCH_MX5 +#define USB_H3REGS_BASE (OTG_BASE_ADDR + 0x600) +#define USB_OTHERREGS_BASE (OTG_BASE_ADDR + 0x800) +#else +#define USB_OTHERREGS_BASE (OTG_BASE_ADDR + 0x600) +#endif + + +#define USBOTG_REG32(offset) (*((volatile u32 *)(IO_ADDRESS(USB_OTGREGS_BASE + (offset))))) +#define USBOTG_REG16(offset) (*((volatile u16 *)(IO_ADDRESS(USB_OTGREGS_BASE + (offset))))) + +#define USBH1_REG32(offset) (*((volatile u32 *)(IO_ADDRESS(USB_H1REGS_BASE + (offset))))) +#define USBH1_REG16(offset) (*((volatile u16 *)(IO_ADDRESS(USB_H1REGS_BASE + (offset))))) + +#define USBH2_REG32(offset) (*((volatile u32 *)(IO_ADDRESS(USB_H2REGS_BASE + (offset))))) +#define USBH2_REG16(offset) (*((volatile u16 *)(IO_ADDRESS(USB_H2REGS_BASE + (offset))))) + +#define USBOTHER_REG(offset) (*((volatile u32 *)(IO_ADDRESS(USB_OTHERREGS_BASE + (offset))))) + +/* + * OTG registers + */ +#define UOG_ID USBOTG_REG32(0x00) /* Host ID */ +#define UOG_HWGENERAL USBOTG_REG32(0x04) /* Host General */ +#define UOG_HWHOST USBOTG_REG32(0x08) /* Host h/w params */ +#define UOG_HWTXBUF USBOTG_REG32(0x10) /* TX buffer h/w params */ +#define UOG_HWRXBUF USBOTG_REG32(0x14) /* RX buffer h/w params */ +#define UOG_CAPLENGTH USBOTG_REG16(0x100) /* Capability register length */ +#define UOG_HCIVERSION USBOTG_REG16(0x102) /* Host Interface version */ +#define UOG_HCSPARAMS USBOTG_REG32(0x104) /* Host control structural params */ +#define UOG_HCCPARAMS USBOTG_REG32(0x108) /* control capability params */ +#define UOG_DCIVERSION USBOTG_REG32(0x120) /* device interface version */ +/* start EHCI registers: */ +#define UOG_USBCMD USBOTG_REG32(0x140) /* USB command register */ +#define UOG_USBSTS USBOTG_REG32(0x144) /* USB status register */ +#define UOG_USBINTR USBOTG_REG32(0x148) /* interrupt enable register */ +#define UOG_FRINDEX USBOTG_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UOG_PERIODICLISTBASE USBOTG_REG32(0x154) /* host crtlr frame list base addr */ +#define UOG_DEVICEADDR USBOTG_REG32(0x154) /* device crtlr device address */ +#define UOG_ASYNCLISTADDR USBOTG_REG32(0x158) /* host ctrlr next async addr */ +#define UOG_EPLISTADDR USBOTG_REG32(0x158) /* device ctrlr endpoint list addr */ +#define UOG_BURSTSIZE USBOTG_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UOG_TXFILLTUNING USBOTG_REG32(0x164) /* TX FIFO fill tuning */ +#define UOG_ULPIVIEW USBOTG_REG32(0x170) /* ULPI viewport */ +#define UOG_CFGFLAG USBOTG_REG32(0x180) /* configflag (supports HS) */ +#define UOG_PORTSC1 USBOTG_REG32(0x184) /* port status and control */ +/* end EHCI registers: */ +#define UOG_OTGSC USBOTG_REG32(0x1a4) /* OTG status and control */ +#define UOG_USBMODE USBOTG_REG32(0x1a8) /* USB device mode */ +#define UOG_ENDPTSETUPSTAT USBOTG_REG32(0x1ac) /* endpoint setup status */ +#define UOG_ENDPTPRIME USBOTG_REG32(0x1b0) /* endpoint initialization */ +#define UOG_ENDPTFLUSH USBOTG_REG32(0x1b4) /* endpoint de-initialize */ +#define UOG_ENDPTSTAT USBOTG_REG32(0x1b8) /* endpoint status */ +#define UOG_ENDPTCOMPLETE USBOTG_REG32(0x1bc) /* endpoint complete */ +#define UOG_EPCTRL0 USBOTG_REG32(0x1c0) /* endpoint control0 */ +#define UOG_EPCTRL1 USBOTG_REG32(0x1c4) /* endpoint control1 */ +#define UOG_EPCTRL2 USBOTG_REG32(0x1c8) /* endpoint control2 */ +#define UOG_EPCTRL3 USBOTG_REG32(0x1cc) /* endpoint control3 */ +#define UOG_EPCTRL4 USBOTG_REG32(0x1d0) /* endpoint control4 */ +#define UOG_EPCTRL5 USBOTG_REG32(0x1d4) /* endpoint control5 */ +#define UOG_EPCTRL6 USBOTG_REG32(0x1d8) /* endpoint control6 */ +#define UOG_EPCTRL7 USBOTG_REG32(0x1dc) /* endpoint control7 */ + +/* + * Host 1 registers + */ +#define UH1_ID USBH1_REG32(0x00) /* Host ID */ +#define UH1_HWGENERAL USBH1_REG32(0x04) /* Host General */ +#define UH1_HWHOST USBH1_REG32(0x08) /* Host h/w params */ +#define UH1_HWTXBUF USBH1_REG32(0x10) /* TX buffer h/w params */ +#define UH1_HWRXBUF USBH1_REG32(0x14) /* RX buffer h/w params */ +#define UH1_CAPLENGTH USBH1_REG16(0x100) /* Capability register length */ +#define UH1_HCIVERSION USBH1_REG16(0x102) /* Host Interface version */ +#define UH1_HCSPARAMS USBH1_REG32(0x104) /* Host control structural params */ +#define UH1_HCCPARAMS USBH1_REG32(0x108) /* control capability params */ +/* start EHCI registers: */ +#define UH1_USBCMD USBH1_REG32(0x140) /* USB command register */ +#define UH1_USBSTS USBH1_REG32(0x144) /* USB status register */ +#define UH1_USBINTR USBH1_REG32(0x148) /* interrupt enable register */ +#define UH1_FRINDEX USBH1_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UH1_PERIODICLISTBASE USBH1_REG32(0x154) /* host crtlr frame list base addr */ +#define UH1_ASYNCLISTADDR USBH1_REG32(0x158) /* host ctrlr nest async addr */ +#define UH1_BURSTSIZE USBH1_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UH1_TXFILLTUNING USBH1_REG32(0x164) /* TX FIFO fill tuning */ +/* configured_flag (0x180) configflag (supports HS) */ +#define UH1_PORTSC1 USBH1_REG32(0x184) /* port status and control */ +/* end EHCI registers: */ +#define UH1_USBMODE USBH1_REG32(0x1a8) /* USB device mode */ + +/* + * Host 2 registers + */ +#define UH2_ID USBH2_REG32(0x00) /* Host ID */ +#define UH2_HWGENERAL USBH2_REG32(0x04) /* Host General */ +#define UH2_HWHOST USBH2_REG32(0x08) /* Host h/w params */ +#define UH2_HWTXBUF USBH2_REG32(0x10) /* TX buffer h/w params */ +#define UH2_HWRXBUF USBH2_REG32(0x14) /* RX buffer h/w params */ +#define UH2_CAPLENGTH USBH2_REG16(0x100) /* Capability register length */ +#define UH2_HCIVERSION USBH2_REG16(0x102) /* Host Interface version */ +#define UH2_HCSPARAMS USBH2_REG32(0x104) /* Host control structural params */ +#define UH2_HCCPARAMS USBH2_REG32(0x108) /* control capability params */ +/* start EHCI registers: */ +#define UH2_USBCMD USBH2_REG32(0x140) /* USB command register */ +#define UH2_USBSTS USBH2_REG32(0x144) /* USB status register */ +#define UH2_USBINTR USBH2_REG32(0x148) /* interrupt enable register */ +#define UH2_FRINDEX USBH2_REG32(0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UH2_PERIODICLISTBASE USBH2_REG32(0x154) /* host crtlr frame list base addr */ +#define UH2_ASYNCLISTADDR USBH2_REG32(0x158) /* host ctrlr nest async addr */ +#define UH2_BURSTSIZE USBH2_REG32(0x160) /* host ctrlr embedded TT async buf status */ +#define UH2_TXFILLTUNING USBH2_REG32(0x164) /* TX FIFO fill tuning */ +#define UH2_ULPIVIEW USBH2_REG32(0x170) /* ULPI viewport */ +/* configured_flag (0x180) configflag (supports HS) */ +#define UH2_PORTSC1 USBH2_REG32(0x184) /* port status and control */ +/* end EHCI registers */ +#define UH2_USBMODE USBH2_REG32(0x1a8) /* USB device mode */ + +/* + * other regs (not part of ARC core) + */ +#define USBCTRL USBOTHER_REG(0x00) /* USB Control register */ +#define USB_OTG_MIRROR USBOTHER_REG(0x04) /* USB OTG mirror register */ +#define USB_PHY_CTR_FUNC USBOTHER_REG(0x08) /* OTG UTMI PHY Function Control register */ +#define USB_PHY_CTR_FUNC2 USBOTHER_REG(0x0c) /* OTG UTMI PHY Function Control register */ +#define USB_CTRL_1 USBOTHER_REG(0x10) /* USB Cotrol Register 1*/ +#define USBCTRL_HOST2 USBOTHER_REG(0x14) /* USB Cotrol Register 1*/ +#define USBCTRL_HOST3 USBOTHER_REG(0x18) /* USB Cotrol Register 1*/ +#define USBH1_PHY_CTRL0 USBOTHER_REG(0x1c) /* USB Cotrol Register 1*/ +#define USBH1_PHY_CTRL1 USBOTHER_REG(0x20) /* USB Cotrol Register 1*/ +#define USB_CLKONOFF_CTRL USBOTHER_REG(0x24) /* USB Clock on/off Control Register */ + +/* + * register bits + */ + +/* x_PORTSCx */ +#define PORTSC_PTS_MASK (3 << 30) /* parallel xcvr select mask */ +#define PORTSC_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */ +#define PORTSC_PTS_PHILIPS (1 << 30) /* Philips classic */ +#define PORTSC_PTS_ULPI (2 << 30) /* ULPI */ +#define PORTSC_PTS_SERIAL (3 << 30) /* serial */ +#define PORTSC_STS (1 << 29) /* serial xcvr select */ +#define PORTSC_PTW (1 << 28) /* UTMI width */ +#define PORTSC_PHCD (1 << 23) /* Low Power Suspend */ +#define PORTSC_PORT_POWER (1 << 12) /* port power */ +#define PORTSC_LS_MASK (3 << 10) /* Line State mask */ +#define PORTSC_LS_SE0 (0 << 10) /* SE0 */ +#define PORTSC_LS_K_STATE (1 << 10) /* K-state */ +#define PORTSC_LS_J_STATE (2 << 10) /* J-state */ +#define PORTSC_PORT_RESET (1 << 8) /* Port reset */ +#define PORTSC_PORT_SUSPEND (1 << 7) /* Suspend */ +#define PORTSC_PORT_FORCE_RESUME (1 << 6) /* Force port resume */ +#define PORTSC_OVER_CURRENT_CHG (1 << 5) /* over current change */ +#define PORTSC_OVER_CURRENT_ACT (1 << 4) /* over currrent active */ +#define PORTSC_PORT_EN_DIS_CHANGE (1 << 3) /* port {en,dis}able change */ +#define PORTSC_PORT_ENABLE (1 << 2) /* port enabled */ +#define PORTSC_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */ +#define PORTSC_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */ + +#define PORTSC_W1C_BITS \ + (PORTSC_CONNECT_STATUS_CHANGE | \ + PORTSC_PORT_EN_DIS_CHANGE | \ + PORTSC_OVER_CURRENT_CHG) + +/* UOG_OTGSC Register Bits */ +/* control bits: */ +#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0) +#define OTGSC_CTRL_VBUS_CHARGE (1 << 1) +#define OTGSC_CTRL_OTG_TERM (1 << 3) /* controls DM pulldown */ +#define OTGSC_CTRL_DATA_PULSING (1 << 4) +#define OTGSC_CTRL_USB_ID_PU (1 << 5) /* enable ID pullup */ +/* current status: (R/O) */ +#define OTGSC_STS_USB_ID (1 << 8) /* 0=A-device 1=B-device */ +#define OTGSC_STS_A_VBUS_VALID (1 << 9) +#define OTGSC_STS_A_SESSION_VALID (1 << 10) +#define OTGSC_STS_B_SESSION_VALID (1 << 11) +#define OTGSC_STS_B_SESSION_END (1 << 12) +#define OTGSC_STS_1ms_TIMER (1 << 13) +#define OTGSC_STS_DATA_PULSE (1 << 14) +/* interrupt status: (write to clear) */ +#define OTGSC_IS_MASK (0x7f << 16) +#define OTGSC_IS_USB_ID (1 << 16) +#define OTGSC_IS_A_VBUS_VALID (1 << 17) +#define OTGSC_IS_A_SESSION_VALID (1 << 18) +#define OTGSC_IS_B_SESSION_VALID (1 << 19) +#define OTGSC_IS_B_SESSION_END (1 << 20) +#define OTGSC_IS_1ms_TIMER (1 << 21) +#define OTGSC_IS_DATA_PULSE (1 << 22) +/* interrupt enables: */ +#define OTGSC_IE_MASK (0x7f << 24) +#define OTGSC_IE_USB_ID (1 << 24) +#define OTGSC_IE_A_VBUS_VALID (1 << 25) +#define OTGSC_IE_A_SESSION_VALID (1 << 26) +#define OTGSC_IE_B_SESSION_VALID (1 << 27) +#define OTGSC_IE_B_SESSION_END (1 << 28) +#define OTGSC_IE_1ms_TIMER (1 << 29) +#define OTGSC_IE_DATA_PULSE (1 << 30) + +#if 1 /* FIXME these here for compatibility between my names and Leo's */ +/* OTG interrupt enable bit masks */ +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK +#define OTGSC_INTSTS_MASK OTGSC_IS_MASK + +/* OTG interrupt status bit masks */ +#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_IS_MASK +#endif + +/* x_USBMODE */ +#define USBMODE_SLOM (1 << 3) /* setup lockout mode */ +#define USBMODE_ES (1 << 2) /* (big) endian select */ +#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ +#define USBMODE_CM_HOST (3 << 0) /* host */ +#define USBMODE_CM_DEVICE (2 << 0) /* device */ +#define USBMODE_CM_reserved (1 << 0) /* reserved */ + +/* USBCTRL */ +#define UCTRL_OWIR (1 << 31) /* OTG wakeup intr request received */ +#define UCTRL_OSIC_MASK (3 << 29) /* OTG Serial Interface Config: */ +#define UCTRL_OSIC_DU6 (0 << 29) /* Differential/unidirectional 6 wire */ +#define UCTRL_OSIC_DB4 (1 << 29) /* Differential/bidirectional 4 wire */ +#define UCTRL_OSIC_SU6 (2 << 29) /* single-ended/unidirectional 6 wire */ +#define UCTRL_OSIC_SB3 (3 << 29) /* single-ended/bidirectional 3 wire */ + +#define UCTRL_OUIE (1 << 28) /* OTG ULPI intr enable */ +#define UCTRL_OWIE (1 << 27) /* OTG wakeup intr enable */ +#define UCTRL_OBPVAL_RXDP (1 << 26) /* OTG RxDp status in bypass mode */ +#define UCTRL_OBPVAL_RXDM (1 << 25) /* OTG RxDm status in bypass mode */ +#define UCTRL_OPM (1 << 24) /* OTG power mask */ +#define UCTRL_O_PWR_POL (1 << 24) /* OTG power pin polarity */ +#ifdef CONFIG_ARCH_MX5 +#define UCTRL_H2WIR (1 << 17) /* HOST2 wakeup intr request received */ +#else +#define UCTRL_H2WIR (1 << 23) /* HOST2 wakeup intr request received */ +#endif +#define UCTRL_H2SIC_MASK (3 << 21) /* HOST2 Serial Interface Config: */ +#define UCTRL_H2SIC_DU6 (0 << 21) /* Differential/unidirectional 6 wire */ +#define UCTRL_H2SIC_DB4 (1 << 21) /* Differential/bidirectional 4 wire */ +#define UCTRL_H2SIC_SU6 (2 << 21) /* single-ended/unidirectional 6 wire */ +#define UCTRL_H2SIC_SB3 (3 << 21) /* single-ended/bidirectional 3 wire */ + +#ifdef CONFIG_ARCH_MX5 +#define UCTRL_H2UIE (1 << 8) /* HOST2 ULPI intr enable */ +#define UCTRL_H2WIE (1 << 7) /* HOST2 wakeup intr enable */ +#define UCTRL_H2PP 0 /* Power Polarity for uh2 */ +#define UCTRL_H2PM (1 << 4) /* HOST2 power mask */ +#else +#define UCTRL_H2UIE (1 << 20) /* HOST2 ULPI intr enable */ +#define UCTRL_H2WIE (1 << 19) /* HOST2 wakeup intr enable */ +#define UCTRL_H2PP (1 << 18) /* Power Polarity for uh2 */ +#define UCTRL_H2PM (1 << 16) /* HOST2 power mask */ +#endif +#define UCTRL_H2OVBWK_EN (1 << 6) /* OTG VBUS Wakeup Enable */ +#define UCTRL_H2OIDWK_EN (1 << 5) /* OTG ID Wakeup Enable */ + +#define UCTRL_H1WIR (1 << 15) /* HOST1 wakeup intr request received */ +#define UCTRL_H1SIC_MASK (3 << 13) /* HOST1 Serial Interface Config: */ +#define UCTRL_H1SIC_DU6 (0 << 13) /* Differential/unidirectional 6 wire */ +#define UCTRL_H1SIC_DB4 (1 << 13) /* Differential/bidirectional 4 wire */ +#define UCTRL_H1SIC_SU6 (2 << 13) /* single-ended/unidirectional 6 wire */ +#define UCTRL_H1SIC_SB3 (3 << 13) /* single-ended/bidirectional 3 wire */ +#define UCTRL_OLOCKD (1 << 13) /* otg lock disable */ +#define UCTRL_H2LOCKD (1 << 12) /* HOST2 lock disable */ +#define UCTRL_H1UIE (1 << 12) /* Host1 ULPI interrupt enable */ + +#if defined(CONFIG_ARCH_MX37) +/* VBUS wakeup enable, UTMI only */ +#define UCTRL_VBUS_WKUP_EN (1 << 12) +#elif defined(CONFIG_ARCH_MX25) || defined(CONFIG_ARCH_MX35) +#define UCTRL_VBUS_WKUP_EN (1 << 15) +#endif + +#define UCTRL_PP (1 << 11) /* power polarity bit */ +#define UCTRL_H1WIE (1 << 11) /* HOST1 wakeup intr enable */ +#define UCTRL_H1BPVAL_RXDP (1 << 10) /* HOST1 RxDp status in bypass mode */ +#define UCTRL_XCSO (1 << 10) /* Xcvr Clock Select for OTG port */ +#define UCTRL_H1BPVAL_RXDM (1 << 9) /* HOST1 RxDm status in bypass mode */ +#define UCTRL_XCSH2 (1 << 9) /* Xcvr Clock Select for Host port */ +#define UCTRL_H1PM (1 << 8) /* HOST1 power mask */ +#define UCTRL_IP_PULIDP (1 << 8) /* Ipp_Puimpel_Pullup_Dp */ + +#define UCTRL_IP_PUE_UP (1 << 7) /* ipp_pue_pullup_dp */ +#define UCTRL_IP_PUE_DOWN (1 << 6) /* ipp_pue_pulldwn_dpdm */ +#define UCTRL_H2DT (1 << 5) /* HOST2 TLL disabled */ +#define UCTRL_H1DT (1 << 4) /* HOST1 TLL disabled */ +#define UCTRL_USBTE (1 << 4) /* USBT Transceiver enable */ +#define UCTRL_OCPOL (1 << 3) /* OverCurrent Polarity */ +#define UCTRL_OCE (1 << 2) /* OverCurrent Enable */ +#define UCTRL_H2OCPOL (1 << 2) /* OverCurrent Polarity of Host2 */ +#define UCTRL_H2OCS (1 << 1) /* Host OverCurrent State */ +#define UCTRL_BPE (1 << 0) /* bypass mode enable */ +#define UCTRL_OTD (1 << 0) /* OTG TLL Disable */ +#define UCTRL_OOCS (1 << 0) /* OTG OverCurrent State */ + +/* USBCMD */ +#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ +#define UCMD_RESET (1 << 1) /* controller reset */ +#define UCMD_ITC_NO_THRESHOLD (~(0xff << 16)) /* Interrupt Threshold Control */ + +/* OTG_MIRROR */ +#define OTGM_SESEND (1 << 4) /* B device session end */ +#define OTGM_VBUSVAL (1 << 3) /* Vbus valid */ +#define OTGM_BSESVLD (1 << 2) /* B session Valid */ +#define OTGM_ASESVLD (1 << 1) /* A session Valid */ +#define OTGM_IDIDG (1 << 0) /* OTG ID pin status */ + /* 1=high: Operate as B-device */ + /* 0=low : Operate as A-device */ + +/* USB_PHY_CTRL_FUNC */ +/* PHY control0 Register Bit Masks */ +#define USB_UTMI_PHYCTRL_CONF2 (1 << 26) + +#define USB_UTMI_PHYCTRL_UTMI_ENABLE (1 << 24) +#define USB_UTMI_PHYCTRL_CHGRDETEN (1 << 24) /* Enable Charger Detector */ +#define USB_UTMI_PHYCTRL_CHGRDETON (1 << 23) /* Charger Detector Power On Control */ +#define USB_UTMI_PHYCTRL_OC_POL (1 << 9) /* OTG Polarity of Overcurrent */ +#define USB_UTMI_PHYCTRL_OC_DIS (1 << 8) /* OTG Disable Overcurrent Event */ +#define USB_UH1_OC_DIS (1 << 5) /* UH1 Disable Overcurrent Event */ +#define USB_UH1_OC_POL (1 << 6) /* UH1 Polarity of OC,Low active */ +/* USB_PHY_CTRL_FUNC2*/ +#define USB_UTMI_PHYCTRL2_PLLDIV_MASK 0x3 +#define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT 0 +#define USB_UTMI_PHYCTRL2_HSDEVSEL_MASK 0x3 +#define USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT 19 + +/* USB_CTRL_1 */ +#define USB_CTRL_UH1_EXT_CLK_EN (1 << 25) +#define USB_CTRL_UH2_EXT_CLK_EN (1 << 26) +#define USB_CTRL_UH2_CLK_FROM_ULPI_PHY (1 << 2) +/* ULPIVIEW register bits */ +#define ULPIVW_OFF (0x170) +#define ULPIVW_WU (1 << 31) /* Wakeup */ +#define ULPIVW_RUN (1 << 30) /* read/write run */ +#define ULPIVW_WRITE (1 << 29) /* 0=read 1=write */ +#define ULPIVW_SS (1 << 27) /* SyncState */ +#define ULPIVW_PORT_MASK 0x07 /* Port field */ +#define ULPIVW_PORT_SHIFT 24 +#define ULPIVW_ADDR_MASK 0xFF /* data address field */ +#define ULPIVW_ADDR_SHIFT 16 +#define ULPIVW_RDATA_MASK 0xFF /* read data field */ +#define ULPIVW_RDATA_SHIFT 8 +#define ULPIVW_WDATA_MASK 0xFF /* write data field */ +#define ULPIVW_WDATA_SHIFT 0 + +#define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */ +/* USB Clock on/off Control Register */ +#define OTG_AHBCLK_OFF (0x1<<17) /* 1: OFF */ +#define H1_AHBCLK_OFF (0x1<<18) /* 1: OFF */ +extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata); +#endif diff --git a/arch/arm/plat-mxc/include/mach/audio_controls.h b/arch/arm/plat-mxc/include/mach/audio_controls.h new file mode 100644 index 000000000000..d314b9997443 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/audio_controls.h @@ -0,0 +1,220 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file include/asm-arm/arch-mxc/audio_controls.h + * @brief this file implements the mxc sound driver interface to OSS framework + * @ingroup SOUND_DRV + */ +#ifndef __ASM_ARCH_MXC_AUDIO_CONTROLS_H__ +#define __ASM_ARCH_MXC_AUDIO_CONTROLS_H__ + +/*! + * This ioctl can be used to get the adder configuration, use the audio control + * SNDCTL_MC13783_READ_OUT_MIXER.\n + * Possible returned values are : + * @see MC13783_AUDIO_ADDER_STEREO + * @see MC13783_AUDIO_ADDER_STEREO_OPPOSITE + * @see MC13783_AUDIO_ADDER_MONO + * @see MC13783_AUDIO_ADDER_MONO_OPPOSITE + * + */ +#define SNDCTL_MC13783_READ_OUT_ADDER _SIOR('Z', 6, int) + +/*! + * To set the adder configuration, use the audio control + * SNDCTL_MC13783_WRITE_OUT_MIXER. Possible arguments are : \n + * @see MC13783_AUDIO_ADDER_STEREO + * @see MC13783_AUDIO_ADDER_STEREO_OPPOSITE + * @see MC13783_AUDIO_ADDER_MONO + * @see MC13783_AUDIO_ADDER_MONO_OPPOSITE + * + */ +#define SNDCTL_MC13783_WRITE_OUT_ADDER _SIOWR('Z', 7, int) + +/*! + * To get the codec balance configuration, use the audio control + * SNDCTL_MC13783_READ_OUT_BALANCE.\n + * Range is 0 (-21 dB left) to 100 (-21 dB right), linear, 3dB step ; + * 50 is no balance. + * \n Examples: + * \n 0 : -21dB left 50 : balance deactivated 100 : -21 dB right + * + */ +#define SNDCTL_MC13783_READ_OUT_BALANCE _SIOR('Z', 8, int) + +/*! + * To set the codec balance configuration, use the audio control + * SNDCTL_MC13783_WRITE_OUT_BALANCE.\n + * Range is 0 (-21 dB left) to 100 (-21 dB right), linear, 3dB step ; + * 50 is no balance. + * \n Examples: + * \n 0 : -21dB left 50 : balance deactivated 100 : -21 dB right + * + */ +#define SNDCTL_MC13783_WRITE_OUT_BALANCE _SIOWR('Z', 9, int) + +/*! + * To set the codec filter configuration, use the audio control + * SNDCTL_MC13783_WRITE_CODEC_FILTER. + * The new configuration replaces the old one.\n + * Possible arguments are : + * @see MC13783_CODEC_FILTER_DISABLE + * @see MC13783_CODEC_FILTER_HIGH_PASS_IN + * @see MC13783_CODEC_FILTER_HIGH_PASS_OUT + * @see MC13783_CODEC_FILTER_DITHERING \n + * + */ +#define SNDCTL_MC13783_WRITE_CODEC_FILTER _SIOWR('Z', 20, int) + +/*! + * To get the codec filter configuration, use the audio control : + * SNDCTL_MC13783_READ_CODEC_FILTER. + * The new configuration replaces the old one.\n + * Possible returned values are : + * @see MC13783_CODEC_FILTER_DISABLE + * @see MC13783_CODEC_FILTER_HIGH_PASS_IN + * @see MC13783_CODEC_FILTER_HIGH_PASS_OUT + * @see MC13783_CODEC_FILTER_DITHERING \n + * + */ +#define SNDCTL_MC13783_READ_CODEC_FILTER _SIOR('Z', 21, int) + +/* + * To set the clock configuration, use the audio control + * SNDCTL_MC13783_WRITE_MASTER_CLOCK. \n + * Possible arguments are : \n + * 1 : to MCU master \n + * 2 : to MC13783 master + */ +#define SNDCTL_MC13783_WRITE_MASTER_CLOCK _SIOR('Z', 30, int) + +/*! + * To set the output port, use the audio control + * SNDCTL_MC13783_WRITE_PORT.\n + * Possible returned values are : + * \n 1 : to port 4 + * \n 2 : to port 5 + * Possible returned values are : + * \n 1 : port 4 + * \n 2 : port 5 + */ +#define SNDCTL_MC13783_WRITE_PORT _SIOR('Z', 31, int) + +/*! + * Argument for the mc13783 adder configuration + * @see SNDCTL_MC13783_WRITE_OUT_ADDER + * @see SNDCTL_MC13783_READ_OUT_ADDER + */ +#define MC13783_AUDIO_ADDER_STEREO 0x1 +/*! + * Argument for the mc13783 adder configuration + * @see SNDCTL_MC13783_WRITE_OUT_ADDER + * @see SNDCTL_MC13783_READ_OUT_ADDER + */ +#define MC13783_AUDIO_ADDER_STEREO_OPPOSITE 0x2 +/*! + * Argument for the mc13783 adder configuration + * @see SNDCTL_MC13783_WRITE_OUT_ADDER + * @see SNDCTL_MC13783_READ_OUT_ADDER + */ +#define MC13783_AUDIO_ADDER_MONO 0x4 +/*! + * Argument for the mc13783 adder configuration + * @see SNDCTL_MC13783_WRITE_OUT_ADDER + * @see SNDCTL_MC13783_READ_OUT_ADDER + */ +#define MC13783_AUDIO_ADDER_MONO_OPPOSITE 0x8 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_DISABLE 0x0 +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_HIGH_PASS_IN 0x1 +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_HIGH_PASS_OUT 0x2 +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_DITHERING 0x4 + +/*! + * Argument for the system audio clocking selection + * @see MXC_AUDIO_CLOCKING_MCU_MASTER + * @see SNDCTL_CLK_SET_MASTER + */ +#define MXC_AUDIO_CLOCKING_MC13783_MASTER 0x0 + +/*! + * Argument for the system audio clocking selection + * @see MXC_AUDIO_CLOCKING_MC13783_MASTER + * @see SNDCTL_CLK_SET_MASTER + */ +#define MXC_AUDIO_CLOCKING_MCU_MASTER 0x1 + +/*! + * Argument for the DAM output port selection + * @see SNDCTL_DAM_SET_OUT_PORT + * @see MXC_DAM_OUT_PORT_AD2 + */ +#define MXC_DAM_OUT_PORT_AD1 0x0 + +/*! + * Argument for the DAM output port selection + * @see SNDCTL_DAM_SET_OUT_PORT + * @see MXC_DAM_OUT_PORT_AD1 + */ +#define MXC_DAM_OUT_PORT_AD2 0x1 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_DISABLE 0x0 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_HIGH_PASS_IN 0x1 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_HIGH_PASS_OUT 0x2 + +/*! + * Argument for the mc13783 codec filter configuration + * @see SNDCTL_MC13783_WRITE_CODEC_FILTER + * @see SNDCTL_MC13783_READ_CODEC_FILTER + */ +#define MC13783_CODEC_FILTER_DITHERING 0x4 + +#endif /* __ASM_ARCH_MXC_AUDIO_CONTROLS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx35_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx35_3ds.h new file mode 100644 index 000000000000..2bcf9db26177 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx35_3ds.h @@ -0,0 +1,55 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ +#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ + +#include + +#define MXC_PSEUDO_PARENT MXC_INT_FORCE +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX35_GPIO1_1) + +enum { + MCU_INT_HEADPHONE = 0, + MCU_INT_GPS, + MCU_INT_SD1_CD, + MCU_INT_SD1_WP, + MCU_INT_SD2_CD, + MCU_INT_SD2_WP, + MCU_INT_POWER_KEY, + MCU_INT_RTC, + MCU_INT_TS_ADC, + MCU_INT_KEYPAD, +}; + +#define MXC_PSEUDO_IRQ_HEADPHONE (MXC_PSEUDO_IO_BASE + MCU_INT_HEADPHONE) +#define MXC_PSEUDO_IRQ_GPS (MXC_PSEUDO_IO_BASE + MCU_INT_GPS) +#define MXC_PSEUDO_IRQ_SD1_CD (MXC_PSEUDO_IO_BASE + MCU_INT_SD1_CD) +#define MXC_PSEUDO_IRQ_SD1_WP (MXC_PSEUDO_IO_BASE + MCU_INT_SD1_WP) +#define MXC_PSEUDO_IRQ_SD2_CD (MXC_PSEUDO_IO_BASE + MCU_INT_SD2_CD) +#define MXC_PSEUDO_IRQ_SD2_WP (MXC_PSEUDO_IO_BASE + MCU_INT_SD2_WP) +#define MXC_PSEUDO_IRQ_POWER_KEY (MXC_PSEUDO_IO_BASE + MCU_INT_POWER_KEY) +#define MXC_PSEUDO_IRQ_KEYPAD (MXC_PSEUDO_IO_BASE + MCU_INT_KEYPAD) +#define MXC_PSEUDO_IRQ_RTC (MXC_PSEUDO_IO_BASE + MCU_INT_RTC) +#define MXC_PSEUDO_IRQ_TS_ADC (MXC_PSEUDO_IO_BASE + MCU_INT_TS_ADC) + +extern int is_suspend_ops_started(void); +extern int __init mx35_3stack_init_mc13892(void); +extern int __init mx35_3stack_init_mc9s08dz60(void); + +#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h deleted file mode 100644 index 383f1c04df06..000000000000 --- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ -#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ - -#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index 753a5988d85c..b414aafac1f8 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -25,6 +25,12 @@ struct module; +struct mxc_clk { + struct list_head node; + char name[20]; + struct clk *reg_clk; +}; + struct clk { int id; /* Source clock this clk depends on */ @@ -57,8 +63,18 @@ struct clk { int (*set_parent) (struct clk *, struct clk *); }; -int clk_register(struct clk *clk); -void clk_unregister(struct clk *clk); +int clk_register(struct mxc_clk *clk); +void clk_unregister(struct mxc_clk *clk); +int clk_get_usecount(struct clk *clk); +int clk_set_pll_dither(struct clk *clk, unsigned int pll_ppm); + +/* Clock flags */ +#define RATE_PROPAGATES (1 << 0) /* Program children too */ +#define ALWAYS_ENABLED (1 << 1) /* Clock cannot be disabled */ +#define RATE_FIXED (1 << 2) /* Fixed clock rate */ +#define CPU_FREQ_TRIG_UPDATE (1 << 3) /* CPUFREQ trig update */ +#define AHB_HIGH_SET_POINT (1 << 4) /* Requires max AHB clock */ +#define AHB_MED_SET_POINT (1 << 5) /* Requires med AHB clock */ unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref); diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 2941472582d2..75b739d254a3 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -20,7 +20,8 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); -extern void mx51_map_io(void); +extern void mx37_map_io(void); +extern void mx5_map_io(void); extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); extern void tzic_init_irq(void __iomem *); @@ -30,8 +31,9 @@ extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); -extern void mx51_init_irq(void); +extern void mx5_init_irq(void); extern void mxc91231_init_irq(void); +extern void mxc_tzic_init_irq(unsigned long); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); @@ -39,9 +41,16 @@ extern int mx25_clocks_init(void); extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); +extern int mx37_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); extern int mxc91231_clocks_init(unsigned long fref); +extern void mxc_cpu_init(void); +extern void mxc_cpu_common_init(void); +extern void early_console_setup(unsigned long base, struct clk *clk); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); extern void mxc_set_cpu_type(unsigned int type); diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 0b6e11eaeb8c..a5a8df40257c 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -49,7 +49,7 @@ #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include +#include #define UART_PADDR MX51_UART1_BASE_ADDR #define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) #endif diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h new file mode 100644 index 000000000000..6022a6a20376 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Copyright (C) 2010 Freescale Semiconductor + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include +#include + +struct platform_device *imx_add_platform_device(const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data); + +#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE) +#include +struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata); +#else +/* the ifdef can be removed once the flexcan driver has been merged */ +struct flexcan_platform_data; +static inline struct platform_device *__init imx_add_flexcan(int id, + resource_size_t iobase, resource_size_t iosize, + resource_size_t irq, + const struct flexcan_platform_data *pdata) +{ + return NULL; +} +#endif + +#include +struct platform_device *__init imx_add_imx_i2c(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct imxi2c_platform_data *pdata); + +#include +struct imx_imx_uart_3irq_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irqrx; + resource_size_t irqtx; + resource_size_t irqrts; +}; +struct platform_device *__init imx_add_imx_uart_3irq( + const struct imx_imx_uart_3irq_data *data, + const struct imxuart_platform_data *pdata); + +struct imx_imx_uart_1irq_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_uart_1irq( + const struct imx_imx_uart_1irq_data *data, + const struct imxuart_platform_data *pdata); + +#include +struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); +struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, + int irq, const struct mxc_nand_platform_data *pdata); + +#include +struct platform_device *__init imx_add_spi_imx(int id, + resource_size_t iobase, resource_size_t iosize, int irq, + const struct spi_imx_master *pdata); + +#include +struct platform_device *__init imx_add_imx_mmc(int id, + resource_size_t iobase, resource_size_t iosize, int irq1, + int irq2, const struct mxc_mmc_platform_data *pdata); diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h new file mode 100644 index 000000000000..7b10512f892b --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dma.h @@ -0,0 +1,305 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_DMA_H__ +#define __ASM_ARCH_MXC_DMA_H__ + +#include + +#define MXC_DMA_DYNAMIC_CHANNEL 255 + +#define MXC_DMA_DONE 0x0 +#define MXC_DMA_REQUEST_TIMEOUT 0x1 +#define MXC_DMA_TRANSFER_ERROR 0x2 + +/*! This defines the list of device ID's for DMA */ +typedef enum mxc_dma_device { + MXC_DMA_UART1_RX, + MXC_DMA_UART1_TX, + MXC_DMA_UART2_RX, + MXC_DMA_UART2_TX, + MXC_DMA_UART3_RX, + MXC_DMA_UART3_TX, + MXC_DMA_UART4_RX, + MXC_DMA_UART4_TX, + MXC_DMA_UART5_RX, + MXC_DMA_UART5_TX, + MXC_DMA_UART6_RX, + MXC_DMA_UART6_TX, + MXC_DMA_MMC1_WIDTH_1, + MXC_DMA_MMC1_WIDTH_4, + MXC_DMA_MMC2_WIDTH_1, + MXC_DMA_MMC2_WIDTH_4, + MXC_DMA_SSI1_8BIT_RX0, + MXC_DMA_SSI1_8BIT_TX0, + MXC_DMA_SSI1_16BIT_RX0, + MXC_DMA_SSI1_16BIT_TX0, + MXC_DMA_SSI1_24BIT_RX0, + MXC_DMA_SSI1_24BIT_TX0, + MXC_DMA_SSI1_8BIT_RX1, + MXC_DMA_SSI1_8BIT_TX1, + MXC_DMA_SSI1_16BIT_RX1, + MXC_DMA_SSI1_16BIT_TX1, + MXC_DMA_SSI1_24BIT_RX1, + MXC_DMA_SSI1_24BIT_TX1, + MXC_DMA_SSI2_8BIT_RX0, + MXC_DMA_SSI2_8BIT_TX0, + MXC_DMA_SSI2_16BIT_RX0, + MXC_DMA_SSI2_16BIT_TX0, + MXC_DMA_SSI2_24BIT_RX0, + MXC_DMA_SSI2_24BIT_TX0, + MXC_DMA_SSI2_8BIT_RX1, + MXC_DMA_SSI2_8BIT_TX1, + MXC_DMA_SSI2_16BIT_RX1, + MXC_DMA_SSI2_16BIT_TX1, + MXC_DMA_SSI2_24BIT_RX1, + MXC_DMA_SSI2_24BIT_TX1, + MXC_DMA_SSI3_8BIT_RX0, + MXC_DMA_SSI3_8BIT_TX0, + MXC_DMA_SSI3_16BIT_RX0, + MXC_DMA_SSI3_16BIT_TX0, + MXC_DMA_SSI3_24BIT_RX0, + MXC_DMA_SSI3_24BIT_TX0, + MXC_DMA_SSI3_8BIT_RX1, + MXC_DMA_SSI3_8BIT_TX1, + MXC_DMA_SSI3_16BIT_RX1, + MXC_DMA_SSI3_16BIT_TX1, + MXC_DMA_SSI3_24BIT_RX1, + MXC_DMA_SSI3_24BIT_TX1, + MXC_DMA_FIR_RX, + MXC_DMA_FIR_TX, + MXC_DMA_CSPI1_RX, + MXC_DMA_CSPI1_TX, + MXC_DMA_CSPI2_RX, + MXC_DMA_CSPI2_TX, + MXC_DMA_CSPI3_RX, + MXC_DMA_CSPI3_TX, + MXC_DMA_ATA_RX, + MXC_DMA_ATA_TX, + MXC_DMA_MEMORY, + MXC_DMA_FIFO_MEMORY, + MXC_DMA_DSP_PACKET_DATA0_RD, + MXC_DMA_DSP_PACKET_DATA0_WR, + MXC_DMA_DSP_PACKET_DATA1_RD, + MXC_DMA_DSP_PACKET_DATA1_WR, + MXC_DMA_DSP_LOG0_CHNL, + MXC_DMA_DSP_LOG1_CHNL, + MXC_DMA_DSP_LOG2_CHNL, + MXC_DMA_DSP_LOG3_CHNL, + MXC_DMA_CSI_RX, + MXC_DMA_SPDIF_16BIT_TX, + MXC_DMA_SPDIF_16BIT_RX, + MXC_DMA_SPDIF_32BIT_TX, + MXC_DMA_SPDIF_32BIT_RX, + MXC_DMA_ASRC_A_RX, + MXC_DMA_ASRC_A_TX, + MXC_DMA_ASRC_B_RX, + MXC_DMA_ASRC_B_TX, + MXC_DMA_ASRC_C_RX, + MXC_DMA_ASRC_C_TX, + MXC_DMA_ASRCA_ESAI, + MXC_DMA_ASRCB_ESAI, + MXC_DMA_ASRCC_ESAI, + MXC_DMA_ASRCA_SSI1_TX0, + MXC_DMA_ASRCA_SSI1_TX1, + MXC_DMA_ASRCA_SSI2_TX0, + MXC_DMA_ASRCA_SSI2_TX1, + MXC_DMA_ASRCB_SSI1_TX0, + MXC_DMA_ASRCB_SSI1_TX1, + MXC_DMA_ASRCB_SSI2_TX0, + MXC_DMA_ASRCB_SSI2_TX1, + MXC_DMA_ESAI_16BIT_RX, + MXC_DMA_ESAI_16BIT_TX, + MXC_DMA_ESAI_24BIT_RX, + MXC_DMA_ESAI_24BIT_TX, + MXC_DMA_TEST_RAM2D2RAM, + MXC_DMA_TEST_RAM2RAM2D, + MXC_DMA_TEST_RAM2D2RAM2D, + MXC_DMA_TEST_RAM2RAM, + MXC_DMA_TEST_HW_CHAINING, + MXC_DMA_TEST_SW_CHAINING +} mxc_dma_device_t; + +/*! This defines the prototype of callback funtion registered by the drivers */ +typedef void (*mxc_dma_callback_t) (void *arg, int error_status, + unsigned int count); + +/*! This defines the type of DMA transfer requested */ +typedef enum mxc_dma_mode { + MXC_DMA_MODE_READ, + MXC_DMA_MODE_WRITE, +} mxc_dma_mode_t; + +/*! This defines the DMA channel parameters */ +typedef struct mxc_dma_channel { + unsigned int active:1; /*!< When there has a active tranfer, it is set to 1 */ + unsigned int lock; /*!< Defines the channel is allocated or not */ + int curr_buf; /*!< Current buffer */ + mxc_dma_mode_t mode; /*!< Read or Write */ + unsigned int channel; /*!< Channel info */ + unsigned int dynamic:1; /*!< Channel not statically allocated when 1 */ + char *dev_name; /*!< Device name */ + void *private; /*!< Private structure for platform */ + mxc_dma_callback_t cb_fn; /*!< The callback function */ + void *cb_args; /*!< The argument of callback function */ +} mxc_dma_channel_t; + +/*! This structure contains the information about a dma transfer */ +typedef struct mxc_dma_requestbuf { + dma_addr_t src_addr; /*!< source address */ + dma_addr_t dst_addr; /*!< destination address */ + int num_of_bytes; /*!< the length of this transfer : bytes */ +} mxc_dma_requestbuf_t; + +/*! This struct contains the information for asrc special*/ +struct dma_channel_asrc_info { + u32 channs; /*!< data channels in asrc */ +}; + +/*! This struct contains the information for device special*/ +struct dma_channel_info { + struct dma_channel_asrc_info asrc; /*!< asrc special information */ +}; + +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX21) +#include +#else +#include +#endif + +/*! + * This function is generally called by the driver at open time. + * The DMA driver would do any initialization steps that is required + * to get the channel ready for data transfer. + * + * @param channel_id a pre-defined id. The peripheral driver would specify + * the id associated with its peripheral. This would be + * used by the DMA driver to identify the peripheral + * requesting DMA and do the necessary setup on the + * channel associated with the particular peripheral. + * The DMA driver could use static or dynamic DMA channel + * allocation. + * @param dev_name module name or device name + * @param data the customized parameter for special channel. + * @return returns a negative number on error if request for a DMA channel did not + * succeed, returns the channel number to be used on success. + */ +extern int mxc_dma_request_ext(mxc_dma_device_t channel_id, char *dev_name, + struct dma_channel_info *info); + +static inline int mxc_dma_request(mxc_dma_device_t channel_id, char *dev_name) +{ + return mxc_dma_request_ext(channel_id, dev_name, NULL); +} + +/*! + * This function is generally called by the driver at close time. The DMA + * driver would do any cleanup associated with this channel. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +extern int mxc_dma_free(int channel_num); + +/*! + * This function would just configure the buffers specified by the user into + * dma channel. The caller must call mxc_dma_enable to start this transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param dma_buf an array of physical addresses to the user defined + * buffers. The caller must guarantee the dma_buf is + * available until the transfer is completed. + * @param num_buf number of buffers in the array + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not be + * added with DMA for transfer. On Success, it returns 0 + */ +extern int mxc_dma_config(int channel_num, mxc_dma_requestbuf_t *dma_buf, + int num_buf, mxc_dma_mode_t mode); + +/*! + * This function would just configure the scatterlist specified by the + * user into dma channel. This is a slight variation of mxc_dma_config(), + * it is provided for the convenience of drivers that have a scatterlist + * passed into them. It is the calling driver's responsibility to have the + * correct physical address filled in the "dma_address" field of the + * scatterlist. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param sg a scatterlist of buffers. The caller must guarantee + * the dma_buf is available until the transfer is + * completed. + * @param num_buf number of buffers in the array + * @param num_of_bytes total number of bytes to transfer. If set to 0, this + * would imply to use the length field of the scatterlist + * for each DMA transfer. Else it would calculate the size + * for each DMA transfer. + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not + * be added with DMA for transfer. On Success, it returns 0 + */ +extern int mxc_dma_sg_config(int channel_num, struct scatterlist *sg, + int num_buf, int num_of_bytes, + mxc_dma_mode_t mode); + +/*! + * This function is provided if the driver would like to set/change its + * callback function. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param callback a callback function to provide notification on transfer + * completion, user could specify NULL if he does not wish + * to be notified + * @param arg an argument that gets passed in to the callback + * function, used by the user to do any driver specific + * operations. + * @return this function returns a negative number on error if the callback + * could not be set for the channel or 0 on success + */ +extern int mxc_dma_callback_set(int channel_num, mxc_dma_callback_t callback, + void *arg); + +/*! + * This stops the DMA channel and any ongoing transfers. Subsequent use of + * mxc_dma_enable() will restart the channel and restart the transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +extern int mxc_dma_disable(int channel_num); + +/*! + * This starts DMA transfer. Or it restarts DMA on a stopped channel + * previously stopped with mxc_dma_disable(). + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +extern int mxc_dma_enable(int channel_num); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/dmaengine.h b/arch/arm/plat-mxc/include/mach/dmaengine.h new file mode 100644 index 000000000000..8f7c84031ddd --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dmaengine.h @@ -0,0 +1,515 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DMA_H +#define __ASM_ARM_ARCH_DMA_H + +#ifndef ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 8 + +/** + * struct mxs_dma_cmd_bits - MXS DMA hardware command bits. + * + * This structure describes the in-memory layout of the command bits in a DMA + * command. See the appropriate reference manual for a detailed description + * of what these bits mean to the DMA hardware. + */ +struct mxs_dma_cmd_bits { + unsigned int command:2; +#define NO_DMA_XFER 0x00 +#define DMA_WRITE 0x01 +#define DMA_READ 0x02 +#define DMA_SENSE 0x03 + + unsigned int chain:1; + unsigned int irq:1; + unsigned int nand_lock:1; + unsigned int nand_wait_4_ready:1; + unsigned int dec_sem:1; + unsigned int wait4end:1; + unsigned int halt_on_terminate:1; + unsigned int terminate_flush:1; + unsigned int resv2:2; + unsigned int pio_words:4; + unsigned int bytes:16; +}; + +/* fill the word 1 of the DMA channel command structure */ +#define fill_dma_word1(cmdp, _cmd, _chain, _irq, _lock, _wait_ready, _dec_sem,\ + _wait4end, _halt_on_term, _term_flush, _pio_words, _bytes)\ + do { \ + struct mxs_dma_cmd_bits *bits = &(cmdp)->bits; \ + \ + /* reset all the fields first */ \ + (cmdp)->data = 0; \ + \ + bits->command = _cmd; \ + bits->chain = _chain; \ + bits->irq = _irq; \ + bits->nand_lock = _lock; \ + bits->nand_wait_4_ready = _wait_ready; \ + bits->dec_sem = _dec_sem; \ + bits->wait4end = _wait4end; \ + bits->halt_on_terminate = _halt_on_term; \ + bits->terminate_flush = _term_flush; \ + bits->pio_words = _pio_words; \ + bits->bytes = _bytes; \ + } while (0) + +/** + * struct mxs_dma_cmd - MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +struct mxs_dma_cmd { + unsigned long next; + union { + unsigned long data; + struct mxs_dma_cmd_bits bits; + } cmd; + union { + dma_addr_t address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +/** + * struct mxs_dma_desc - MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + * + * @cmd: The MXS DMA hardware command block. + * @flags: Flags that represent the state of this DMA descriptor. + * @address: The physical address of this descriptor. + * @buffer: A convenient place for software to put the virtual address of the + * associated data buffer (the physical address of the buffer + * appears in the DMA command). The MXS platform DMA software doesn't + * use this field -- it is provided as a convenience. + * @node: Links this structure into a list. + */ +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; +#define MXS_DMA_DESC_READY 0x80000000 +#define MXS_DMA_DESC_FIRST 0x00000001 +#define MXS_DMA_DESC_LAST 0x00000002 + dma_addr_t address; + void *buffer; + struct list_head node; +}; + +struct mxs_dma_info { + unsigned int status; +#define MXS_DMA_INFO_ERR 0x00000001 +#define MXS_DMA_INFO_ERR_STAT 0x00010000 + unsigned int buf_addr; +}; + +/** + * struct mxs_dma_chan - MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + * + * @name: A human-readable string that describes how this channel is + * being used or what software "owns" it. This field is set when + * when the channel is reserved by mxs_dma_request(). + * @dev: A pointer to a struct device *, cast to an unsigned long, and + * representing the software that "owns" the channel. This field + * is set when when the channel is reserved by mxs_dma_request(). + * @lock: Arbitrates access to this channel. + * @dma: A pointer to a struct mxs_dma_device representing the driver + * code that operates this channel. + * @flags: Flag bits that represent the state of this channel. + * @active_num: If the channel is not busy, this value is zero. If the channel + * is busy, this field contains the number of DMA command + * descriptors at the head of the active list that the hardware + * has been told to process. This value is set at the moment the + * channel is enabled by mxs_dma_enable(). More descriptors may + * arrive after the channel is enabled, so the number of + * descriptors on the active list may be greater than this value. + * In fact, it should always be active_num + pending_num. + * @pending_num: The number of DMA command descriptors at the tail of the + * active list that the hardware has not been told to process. + * @active: The list of DMA command descriptors either currently being + * processed by the hardware or waiting to be processed. + * Descriptors being processed appear at the head of the list, + * while pending descriptors appear at the tail. The total number + * should always be active_num + pending_num. + * @done: The list of DMA command descriptors that have either been + * processed by the DMA hardware or aborted by a call to + * mxs_dma_disable(). + */ +struct mxs_dma_chan { + const char *name; + unsigned long dev; + spinlock_t lock; + struct mxs_dma_device *dma; + unsigned int flags; +#define MXS_DMA_FLAGS_IDLE 0x00000000 +#define MXS_DMA_FLAGS_BUSY 0x00000001 +#define MXS_DMA_FLAGS_FREE 0x00000000 +#define MXS_DMA_FLAGS_ALLOCATED 0x00010000 +#define MXS_DMA_FLAGS_VALID 0x80000000 + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +/** + * struct mxs_dma_device - DMA channel driver interface. + * + * This structure represents the driver that operates a DMA channel. Every + * struct mxs_dma_chan contains a pointer to a structure of this type, which is + * installed when the driver registers to "own" the channel (see + * mxs_dma_device_register()). + */ +struct mxs_dma_device { + struct list_head node; + const char *name; + void __iomem *base; + unsigned int chan_base; + unsigned int chan_num; + unsigned int data; + struct platform_device *pdev; + + /* operations */ + int (*enable) (struct mxs_dma_chan *, unsigned int); + void (*disable) (struct mxs_dma_chan *, unsigned int); + void (*reset) (struct mxs_dma_device *, unsigned int); + void (*freeze) (struct mxs_dma_device *, unsigned int); + void (*unfreeze) (struct mxs_dma_device *, unsigned int); + int (*read_semaphore) (struct mxs_dma_device *, unsigned int); + void (*add_semaphore) (struct mxs_dma_device *, unsigned int, unsigned); + void (*info)(struct mxs_dma_device *, + unsigned int, struct mxs_dma_info *info); + void (*enable_irq) (struct mxs_dma_device *, unsigned int, int); + int (*irq_is_pending) (struct mxs_dma_device *, unsigned int); + void (*ack_irq) (struct mxs_dma_device *, unsigned int); + + void (*set_target) (struct mxs_dma_device *, unsigned int, int); +}; + +/** + * mxs_dma_device_register - Register a DMA driver. + * + * This function registers a driver for a contiguous group of DMA channels (the + * ordering of DMA channels is specified by the globally unique DMA channel + * numbers given in mach/dma.h). + * + * @pdev: A pointer to a structure that represents the driver. This structure + * contains fields that specify the first DMA channel number and the + * number of channels. + */ +extern int mxs_dma_device_register(struct mxs_dma_device *pdev); + +/** + * mxs_dma_request - Request to reserve a DMA channel. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." + * @name: A human-readable string that identifies the channel owner or the + * purpose of the channel. + */ +extern int mxs_dma_request(int channel, struct device *dev, const char *name); + +/** + * mxs_dma_release - Release a DMA channel. + * + * This function releases a DMA channel from its current owner. + * + * The channel will NOT be released if it's marked "busy" (see + * mxs_dma_enable()). + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." If + * this doesn't match the owner given to mxs_dma_request(), the + * channel will NOT be released. + */ +extern void mxs_dma_release(int channel, struct device *dev); + +/** + * mxs_dma_enable - Enable a DMA channel. + * + * If the given channel has any DMA descriptors on its active list, this + * function causes the DMA hardware to begin processing them. + * + * This function marks the DMA channel as "busy," whether or not there are any + * descriptors to process. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_enable(int channel); + +/** + * mxs_dma_disable - Disable a DMA channel. + * + * This function shuts down a DMA channel and marks it as "not busy." Any + * descriptors on the active list are immediately moved to the head of the + * "done" list, whether or not they have actually been processed by the + * hardware. The "ready" flags of these descriptors are NOT cleared, so they + * still appear to be active. + * + * This function immediately shuts down a DMA channel's hardware, aborting any + * I/O that may be in progress, potentially leaving I/O hardware in an undefined + * state. It is unwise to call this function if there is ANY chance the hardware + * is still processing a command. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_disable(int channel); + +/** + * mxs_dma_reset - Resets the DMA channel hardware. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_reset(int channel); + +/** + * mxs_dma_freeze - Freeze a DMA channel. + * + * This function causes the channel to continuously fail arbitration for bus + * access, which halts all forward progress without losing any state. A call to + * mxs_dma_unfreeze() will cause the channel to continue its current operation + * with no ill effect. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_freeze(int channel); + +/** + * mxs_dma_unfreeze - Unfreeze a DMA channel. + * + * This function reverses the effect of mxs_dma_freeze(), enabling the DMA + * channel to continue from where it was frozen. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ + +extern void mxs_dma_unfreeze(int channel); + +/* get dma channel information */ +extern int mxs_dma_get_info(int channel, struct mxs_dma_info *info); + +/** + * mxs_dma_cooked - Clean up processed DMA descriptors. + * + * This function removes processed DMA descriptors from the "active" list. Pass + * in a non-NULL list head to get the descriptors moved to your list. Pass NULL + * to get the descriptors moved to the channel's "done" list. Descriptors on + * the "done" list can be retrieved with mxs_dma_get_cooked(). + * + * This function marks the DMA channel as "not busy" if no unprocessed + * descriptors remain on the "active" list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: If this is not NULL, it is the list to which the processed + * descriptors should be moved. If this list is NULL, the descriptors + * will be moved to the "done" list. + */ +extern int mxs_dma_cooked(int channel, struct list_head *head); + +/** + * mxs_dma_read_semaphore - Read a DMA channel's hardware semaphore. + * + * As used by the MXS platform's DMA software, the DMA channel's hardware + * semaphore reflects the number of DMA commands the hardware will process, but + * has not yet finished. This is a volatile value read directly from hardware, + * so it must be be viewed as immediately stale. + * + * If the channel is not marked busy, or has finished processing all its + * commands, this value should be zero. + * + * See mxs_dma_append() for details on how DMA command blocks must be configured + * to maintain the expected behavior of the semaphore's value. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_read_semaphore(int channel); + +/** + * mxs_dma_irq_is_pending - Check if a DMA interrupt is pending. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_irq_is_pending(int channel); + +/** + * mxs_dma_enable_irq - Enable or disable DMA interrupt. + * + * This function enables the given DMA channel to interrupt the CPU. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @en: True if the interrupt for this channel should be enabled. False + * otherwise. + */ +extern void mxs_dma_enable_irq(int channel, int en); + +/** + * mxs_dma_ack_irq - Clear DMA interrupt. + * + * The software that is using the DMA channel must register to receive its + * interrupts and, when they arrive, must call this function to clear them. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_ack_irq(int channel); + +/** + * mxs_dma_set_target - Set the target for a DMA channel. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @target: Indicates the target for the channel. + */ +extern void mxs_dma_set_target(int channel, int target); + +/* mxs dma utility functions */ +extern struct mxs_dma_desc *mxs_dma_alloc_desc(void); +extern void mxs_dma_free_desc(struct mxs_dma_desc *); + +/** + * mxs_dma_cmd_address - Return the address of the command within a descriptor. + * + * @desc: The DMA descriptor of interest. + */ +static inline unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) +{ + return desc->address += offsetof(struct mxs_dma_desc, cmd); +} + +/** + * mxs_dma_desc_pending - Check if descriptor is on a channel's active list. + * + * This function returns the state of a descriptor's "ready" flag. This flag is + * usually set only if the descriptor appears on a channel's active list. The + * descriptor may or may not have already been processed by the hardware. + * + * The "ready" flag is set when the descriptor is submitted to a channel by a + * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is + * cleared when a processed descriptor is moved off the active list by a call + * to mxs_dma_cooked(). The "ready" flag is NOT cleared if the descriptor is + * aborted by a call to mxs_dma_disable(). + * + * @desc: The DMA descriptor of interest. + */ +static inline int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc) +{ + return pdesc->flags & MXS_DMA_DESC_READY; +} + +/** + * mxs_dma_desc_append - Add a DMA descriptor to a channel. + * + * If the descriptor list for this channel is not empty, this function sets the + * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so + * it will chain to the new descriptor's command. + * + * Then, this function marks the new descriptor as "ready," adds it to the end + * of the active descriptor list, and increments the count of pending + * descriptors. + * + * The MXS platform DMA software imposes some rules on DMA commands to maintain + * important invariants. These rules are NOT checked, but they must be carefully + * applied by software that uses MXS DMA channels. + * + * Invariant: + * The DMA channel's hardware semaphore must reflect the number of DMA + * commands the hardware will process, but has not yet finished. + * + * Explanation: + * A DMA channel begins processing commands when its hardware semaphore is + * written with a value greater than zero, and it stops processing commands + * when the semaphore returns to zero. + * + * When a channel finishes a DMA command, it will decrement its semaphore if + * the DECREMENT_SEMAPHORE bit is set in that command's flags bits. + * + * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set, + * unless it suits the purposes of the software. For example, one could + * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE + * bit set only in the last one. Then, setting the DMA channel's hardware + * semaphore to one would cause the entire series of five commands to be + * processed. However, this example would violate the invariant given above. + * + * Rule: + * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA + * channel's hardware semaphore will be decremented EVERY time a command is + * processed. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @pdesc: A pointer to the new descriptor. + */ +extern int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +/** + * mxs_dma_desc_add_list - Add a list of DMA descriptors to a channel. + * + * This function marks all the new descriptors as "ready," adds them to the end + * of the active descriptor list, and adds the length of the list to the count + * of pending descriptors. + * + * See mxs_dma_desc_append() for important rules that apply to incoming DMA + * descriptors. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list of DMA descriptors to add. + */ +extern int mxs_dma_desc_add_list(int channel, struct list_head *head); + +/** + * mxs_dma_desc_get_cooked - Retrieve processed DMA descriptors. + * + * This function moves all the descriptors from the DMA channel's "done" list to + * the head of the given list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list that will receive the + * descriptors on the "done" list. + */ +extern int mxs_dma_get_cooked(int channel, struct list_head *head); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/dptc.h b/arch/arm/plat-mxc/include/mach/dptc.h new file mode 100644 index 000000000000..9f5ee9c6fe5d --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dptc.h @@ -0,0 +1,186 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_DPTC_H__ +#define __ASM_ARCH_MXC_DPTC_H__ + +#include + +/*! + * DPTC proc file system entry name + */ +#define PROC_NODE_NAME "dptc" + +int __init init_dptc_controller(dvfs_dptc_params_s *params); + +/*! + * This function enables the DPTC module. this function updates the DPTC + * thresholds, updates the PMIC, unmasks the DPTC interrupt and enables + * the DPTC module + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * + * @return 0 if DPTC module was enabled else returns -EINVAL. + */ +int start_dptc(dvfs_dptc_params_s *params); +/*! + * This function disables the DPTC module. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * + * @return 0 if DPTC module was disabled else returns -EINVAL. + */ +int stop_dptc(dvfs_dptc_params_s *params); +/*! + * This function updates the drivers current working point index. This index is + * used for access the current DTPC table entry and it corresponds to the + * current CPU working point measured by the DPTC hardware. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param new_wp New working point index value to be set. + * + */ +void set_dptc_wp(dvfs_dptc_params_s *params, int new_wp); +/*! + * This function updates the DPTC threshold registers. + * + * @param dvfs_dptc_tables_ptr pointer to the DPTC translation table. + * @param wp current wp value. + * @param freq_index translation table index of the current CPU + * frequency. + * + */ +void update_dptc_thresholds(dvfs_dptc_tables_s *dptc_tables_ptr, + int wp, int freq_index); +/*! + * This function adds a new entry to the DPTC log buffer. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param dptc_log pointer to the DPTC log buffer structure. + * @param wp value of the working point index written + * to the log buffer. + * @param freq_index value of the frequency index written to + * the log buffer. + * + * @return number of log buffer entries. + * + */ + +void add_dptc_log_entry(dvfs_dptc_params_s *params, + dptc_log_s *dptc_log, int wp, int freq_index); + +/*! + * This function updates the CPU voltage, produced by PMIC, by calling PMIC + * driver functions. + * + * @param dptc_tables_ptr pointer to the DPTC translation table. + * @param wp current wp value. + */ +void set_pmic_voltage(dvfs_dptc_tables_s *dptc_tables_ptr, int wp); + +/*! + * This function enables the DPTC reference circuits. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param rc_state each high bit specifies which + * reference circuite to enable. + * @return 0 on success, error code on failure + */ +int enable_ref_circuits(dvfs_dptc_params_s *params, unsigned char rc_state); + +/*! + * This function disables the DPTC reference circuits. + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param rc_state each high bit specifies which + * reference circuite to disable + * @return 0 on success, error code on failure + */ +int disable_ref_circuits(dvfs_dptc_params_s *params, unsigned char rc_state); + +/*! + * This function is the DPTC Interrupt handler. + * This function wakes-up the dptc_workqueue_handler function that handles the + * DPTC interrupt. + */ +void dptc_irq(void); + +/*! + * This function updates the drivers current frequency index.This index is + * used for access the current DTPC table entry and it corresponds to the + * current CPU frequency (each CPU frequency has a separate index number + * according to the loaded DPTC table). + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + * @param freq_index New frequency index value to be set. + * + * @return 0 if the frequency index was updated (the new index is a + * valid index and the DPTC module isn't active) else returns + * -EINVAL. + * + */ +int set_dptc_curr_freq(dvfs_dptc_params_s *params, unsigned int freq_index); + +#ifdef CONFIG_MXC_DVFS_SDMA +/* + * DPTC SDMA callback. + * Updates the PMIC voltage + * + * @param params pointer to the DVFS & DPTC driver parameters structure. + */ +void dptc_sdma_callback(dvfs_dptc_params_s *params); +#endif + +/*! + * This function is called to put the DPTC in a low power state. + * + * @param pdev the device structure used to give information on which + * device to suspend (not relevant for DPTC) + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +int mxc_dptc_suspend(struct platform_device *pdev, pm_message_t state); + +/*! + * This function is called to put the DPTC in a low power state. + * + */ +void dptc_suspend(void); + +/*! + * This function is called to resume the DPTC from a low power state. + * + * @param pdev the device structure used to give information on which + * device to suspend (not relevant for DPTC) + * + * @return The function always returns 0. + */ +int mxc_dptc_resume(struct platform_device *dev); + +/*! + * This function is called to resume the DPTC from a low power state. + * + */ +void dptc_resume(void); + +/*! + * This function initializes DPTC according to turbo mode status + * + * @param status Turbo mode disable, 1 - turbo mode enabled + * + */ +void dptc_set_turbo_mode(unsigned int status); + +#endif /* __ASM_ARCH_MXC_DPTC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h b/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h new file mode 100644 index 000000000000..d24549ab97fe --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dvfs_dptc_struct.h @@ -0,0 +1,169 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file arch-mxc/dvfs_dptc_struct.h + * + * @brief MXC dvfs & dptc structure definitions file. + * + * @ingroup PM_MX27 PM_MX31 PM_MXC91321 PM_MXC91311 + */ +#ifndef __ASM_ARCH_MXC_DVFS_DPTC_STRUCT_H__ +#define __ASM_ARCH_MXC_DVFS_DPTC_STRUCT_H__ + +#include +#include + +/*! + * Number of entries in the DPTC log buffer + */ +#define LOG_ENTRIES 1024 + +/*! + * Log buffer Structure.\n + * This structure records the DPTC changes. \n + * This structure can be read by the user using the proc file system DPTC read entry. + */ +typedef struct { + /*! + * Index to the head of the log buffer + */ + int head; + + /*! + * Index to the tail of the log buffer + */ + int tail; + + /*! + * Mutex to allow access to the log buffer + */ + struct semaphore mutex; + + /*! + * Array of log buffer entries + */ + dptc_log_entry_s entries[LOG_ENTRIES]; +} dptc_log_s; + +/*! + * DPTC driver data structure.\n + * Holds all driver parameters and data structures. + */ +typedef struct { + /*! + * This variable holds the current frequency index + */ + int current_freq_index; + + /*! + * Boolean variable, if TRUE the DPTC module is enabled + * if FALSE the DPTC module is disabled + */ + int dptc_is_active; + + /*! + * Boolean variable, if TRUE turbo mode enable + * if FALSE turbo mode disabled + */ + int turbo_mode_active; + + /*! + * Boolean variable, if TRUE the DVFS module is enabled + * if FALSE the DPTC module is disabled + */ + int dvfs_is_active; + + /*! + * Boolean variable, if TRUE the DPTC module is suspended + */ + int suspended; + + unsigned char rc_state; + + /*! + * Pointer to the DVFS & DPTC translation table + */ + dvfs_dptc_tables_s *dvfs_dptc_tables_ptr; + + /*! + * The DPTC log buffer + */ + dptc_log_s dptc_log_buffer; + + /*! + * The DVFS log buffer + */ + unsigned char *dvfs_log_buffer; + + /*! + * The DVFS log buffer physical address (for SDMA) + */ + dma_addr_t dvfs_log_buffer_phys; + +#ifdef CONFIG_MXC_DVFS_SDMA + /*! + * SDMA channel number + */ + int sdma_channel; + + /*! + * This holds the previous working point + */ + int prev_wp; + + /*! + * Wait entry for predictive DVFS + */ + wait_queue_head_t dvfs_pred_wait; +#endif + + /*! + * This holds the current DVFS mode + */ + unsigned int dvfs_mode; + + /*! + * Log buffer read pointer + */ + unsigned char *read_ptr; + + /* + * Number of characters in log buffer + */ + int chars_in_buffer; +} dvfs_dptc_params_s; + +/*! + * This struct contains the array with values of supported frequencies in Hz + */ +typedef struct { + /* + * Number of supported states + */ + unsigned int num_of_states; + /*! + * Array of frequencies + */ + unsigned int *freqs; +} dvfs_states_table; + +/* + * if not defined define TREU and FALSE values. + */ +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif /* TRUE */ + +#endif diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb.h b/arch/arm/plat-mxc/include/mach/fsl_usb.h new file mode 100644 index 000000000000..71263360dc69 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/fsl_usb.h @@ -0,0 +1,100 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * USB Host side, platform-specific functionality. + */ + +#include +#include + +static void fsl_setup_phy(struct ehci_hcd *ehci, + enum fsl_usb2_phy_modes phy_mode, + int port_offset); + +static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci) +{ + struct fsl_usb2_platform_data *pdata; + + pdata = ehci_to_hcd(ehci)->self.controller->platform_data; + fsl_setup_phy(ehci, pdata->phy_mode, 0); +} + +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd) +{ + unsigned int temp; + struct fsl_usb2_platform_data *pdata; + + pdata = hcd->self.controller->platform_data; + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host) + pdata->xcvr_ops->set_host(); + + /* set host mode */ + temp = readl(hcd->regs + 0x1a8); + writel(temp | USBMODE_CM_HOST, hcd->regs + 0x1a8); +} + +/* Needed for enable PP and i2c/serial transceivers */ +static inline void +fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on) +{ + u32 temp; + + /* HCSPARAMS */ + temp = readl(pdata->regs + 0x104); + /* Port Power Control */ + if (temp & HCSPARAMS_PPC) { + temp = readl(pdata->regs + FSL_SOC_USB_PORTSC1); + if (on) + temp |= PORT_POWER; + else + temp &= ~PORT_POWER; + + writel(temp, pdata->regs + FSL_SOC_USB_PORTSC1); + } + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power) + pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on); +} + +/* Set USB AHB burst length for host */ +static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd) +{ + struct fsl_usb2_platform_data *pdata; + unsigned int temp; + + pdata = hcd->self.controller->platform_data; + if (pdata->change_ahb_burst) { + temp = readl(hcd->regs + FSL_SOC_USB_SBUSCFG); + writel((temp & (~(0x7))) | pdata->ahb_burst_mode, + hcd->regs + FSL_SOC_USB_SBUSCFG); + } + + /* Increase TX fifo threshold for USB+ATA for i.mx35 2.0 */ + if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) { + temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING); + /* Change TX FIFO threshold to be 0x20 */ + writel((temp & (~(0x3f << 16))) | (0x20 << 16), + hcd->regs + FSL_SOC_USB_TXFILLTUNING); + } + + /* Increase TX fifo threshold for USB+SD in Hostx */ + if (cpu_is_mx53() && (strcmp("DR", pdata->name))) { + temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING); + /* Change TX FIFO threshold to be 0x08 */ + writel((temp & (~(0x3f << 16))) | (0x08 << 16), + hcd->regs + FSL_SOC_USB_TXFILLTUNING); + } + +} diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h new file mode 100644 index 000000000000..9bf3c07d7474 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h @@ -0,0 +1,40 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * USB Gadget side, platform-specific functionality. + */ + +#include + +/* Needed for i2c/serial transceivers */ +static inline void +fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_device) + pdata->xcvr_ops->set_device(); +} + +static inline void +fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(1); +} + +static inline void +fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(0); +} diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 7a0dc5aa2479..84cd95df7b44 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -34,9 +34,12 @@ struct mxc_gpio_port { void __iomem *base; int irq; + int irq_high; int virtual_irq_start; struct gpio_chip chip; u32 both_edges; + u32 suspend_wakeup; + u32 saved_wakeup; spinlock_t lock; }; diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4ac43fc..9f6b61788d04 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -22,13 +22,34 @@ #include +/* + * --------------------------------------------------------------------------- + * Processor specific defines + * --------------------------------------------------------------------------- + */ +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_3 0x13 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_1 0x21 +#define CHIP_REV_2_2 0x22 +#define CHIP_REV_2_3 0x23 +#define CHIP_REV_3_0 0x30 +#define CHIP_REV_3_1 0x31 +#define CHIP_REV_3_2 0x32 + +#define BOARD_REV_1 0x000 +#define BOARD_REV_2 0x100 +#define BOARD_REV_3 0x200 + #define IMX_IO_ADDRESS(addr, module) \ ((void __force __iomem *) \ (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) #ifdef CONFIG_ARCH_MX5 -#include +#include #endif #ifdef CONFIG_ARCH_MX3 @@ -37,6 +58,10 @@ #include #endif +#ifdef CONFIG_ARCH_MX37 +#include +#endif + #ifdef CONFIG_ARCH_MX2 # include # ifdef CONFIG_MACH_MX21 @@ -59,6 +84,38 @@ # include #endif +#ifndef __ASSEMBLY__ +extern unsigned int system_rev; +#define board_is_rev(rev) (((system_rev & 0x0F00) == rev) ? 1 : 0) +#endif + +#ifdef CONFIG_ARCH_MX5 +#define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(BOARD_REV_2)) +#define board_is_mx53_evk_a() (cpu_is_mx53() && board_is_rev(BOARD_REV_1)) +#define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(BOARD_REV_3)) +#endif + #include +/*! + * Register an interrupt handler for the SMN as well as the SCC. In some + * implementations, the SMN is not connected at all, and in others, it is + * on the same interrupt line as the SCM. Comment this line out accordingly + */ +#define USE_SMN_INTERRUPT + +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive Irda data. + */ +#define MXC_UART_IR_RXDMUX 0x0004 +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive UART data. + */ +#define MXC_UART_RXDMUX 0x0004 + +#ifndef MXC_INT_FORCE +#define MXC_INT_FORCE -1 +#endif #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/hw_events.h b/arch/arm/plat-mxc/include/mach/hw_events.h new file mode 100644 index 000000000000..3c340fbab500 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/hw_events.h @@ -0,0 +1,65 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * hw_events.h + * include the headset/cvbs interrupt detect + */ + +#ifndef HW_EVENT_H +#define HW_EVENT_H + +#define HW_EVENT_GROUP 2 +#define HWE_DEF_PRIORITY 1 +#define HWE_HIGH_PRIORITY 0 + +typedef enum { + + HWE_PHONEJACK_PLUG = 0, + HWE_BAT_CHARGER_PLUG, + HWE_BAT_CHARGER_OVERVOLTAGE, + HWE_BAT_BATTERY_LOW, + HWE_BAT_POWER_FAILED, + HWE_BAT_CHARGER_FULL, + HWE_POWER_KEY, +} HW_EVENT_T; + +typedef enum { + + PJT_NONE = 0, + PJT_CVBS, + PJT_HEADSET, +} PHONEJACK_TYPE; + +typedef enum { + + PWRK_UNPRESS = 0, + PWRK_PRESS, +} POWERKEY_TYPE; + +typedef enum { + + UNPLUG = 0, + PLUGGED, +} PLUG_TYPE; + +struct mxc_hw_event { + unsigned int event; + int args; +}; + +#ifdef __KERNEL__ +extern int hw_event_send(int priority, struct mxc_hw_event *new_event); +#endif + +#endif /* HW_EVENT_H */ diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index b4f2de769466..0c8cc1fca4e8 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -14,29 +14,33 @@ /* Allow IO space to be anywhere in the memory */ #define IO_SPACE_LIMIT 0xffffffff -#ifdef CONFIG_ARCH_MX3 -#define __arch_ioremap __mx3_ioremap -#define __arch_iounmap __iounmap +extern void __iomem *__mxc_ioremap(unsigned long cookie, size_t size, + unsigned int mtype); -static inline void __iomem * -__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) -{ - if (mtype == MT_DEVICE) { - /* Access all peripherals below 0x80000000 as nonshared device - * but leave l2cc alone. - */ - if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) || - (phys_addr >= 0x30000000 + SZ_1M))) - mtype = MT_DEVICE_NONSHARED; - } - - return __arm_ioremap(phys_addr, size, mtype); -} -#endif +#define __arch_ioremap(a, s, f) __mxc_ioremap(a, s, f) +#define __arch_iounmap __iounmap /* io address mapping macro */ #define __io(a) __typesafe_io(a) #define __mem_pci(a) (a) +/*! + * This function is called to read a CPLD register over CSPI. + * + * @param offset number of the cpld register to be read + * + * @return Returns 0 on success -1 on failure. + */ +unsigned int __weak spi_cpld_read(unsigned int offset); + +/*! + * This function is called to write to a CPLD register over CSPI. + * + * @param offset number of the cpld register to be written + * @param reg_val value to be written + * + * @return Returns 0 on success -1 on failure. + */ +unsigned int __weak spi_cpld_write(unsigned int offset, unsigned int reg_val); #endif diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index cbaed295a2bf..39f9854bcbab 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2008 by Sascha Hauer * * This program is free software; you can redistribute it and/or @@ -554,6 +554,7 @@ enum iomux_pins { #define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) #define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) +#define MX31_PIN_BATT_LINE__GPIO2_17 IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_GPIO) #define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) #define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) #define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) @@ -696,6 +697,7 @@ enum iomux_pins { #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_2__GPIO1_2 IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO) #define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) #define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) #define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) @@ -735,7 +737,7 @@ enum iomux_pins { #define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) #define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) #define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) - +#define MX31_PIN_SRST0__GPIO3_2 IOMUX_MODE(MX31_PIN_SRST0, IOMUX_CONFIG_GPIO) /* * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h index 2a24bae1b878..03996854bbf5 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h @@ -20,6 +20,7 @@ #define __MACH_IOMUX_MX35_H__ #include +#include /* * The naming convention for the pad modes is MX35_PAD___ @@ -1263,5 +1264,10 @@ #define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_GPIO1_1 (0 * 32 + 1) +#define MX35_GPIO1_4 (0 * 32 + 4) +#define MX35_GPIO2_0 (1 * 32 + 0) + +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_IRQ_START + pin) #endif /* __MACH_IOMUX_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h new file mode 100644 index 000000000000..fd4a2e2f4ecc --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h @@ -0,0 +1,596 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX50_H__ +#define __MACH_IOMUX_MX50_H__ + +#include + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +#define NON_MUX_I 0x3FF +#define NON_PAD_I 0x7FF + +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + +#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_WVGA_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) + +#define MX50_SD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST) + +#define MX50_SD3_PAD_DAT (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define MX50_SD3_PAD_CMD (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) +#define MX50_SD3_PAD_CLK (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) +#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) +#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) +#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) + +#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH) + +#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) + +/* HP detect */ +#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, MX50_SD_PAD_CTRL) + +#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC \ + IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, PAD_CTL_PKE) +#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, 0) +#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, 0) + +/* SD1 */ +#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) + +/* SD2 */ +#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) + +/* SD3 */ +#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, \ + MX50_SD3_PAD_CMD) +#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, \ + MX50_SD3_PAD_CLK) +#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) +#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, \ + MX50_SD3_PAD_DAT) + +/* OWIRE */ +#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, \ + MX50_OWIRE_PAD_CTRL) + +/* SSI */ +#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, \ + NO_PAD_CTRL) + +/* UART1 and UART2 */ +#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, \ + MX50_UART_PAD_CTRL) +#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, \ + MX50_UART_PAD_CTRL) + +/* I2C1, I2C2, I2C3 */ +#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) +#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX50_I2C_PAD_CTRL) + +/* EPDC */ +#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, \ + 0x0, 0, MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) +#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, \ + MX50_ELCDIF_PAD_CTRL) + +/* USB */ +#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, \ + MX50_USB_PAD_CTRL) +#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_DSE_HIGH) +#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, \ + MX50_USB_PAD_CTRL) +#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, \ + MX50_USB_PAD_CTRL) + + +/* FEC */ +#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, \ + MX50_FEC_PAD_CTRL) +#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x0, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, \ + PAD_CTL_HYS | PAD_CTL_PKE) +#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, \ + PAD_CTL_DSE_HIGH) + +/* WVGA */ +#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, \ + MX50_WVGA_PAD_CTRL) +#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, \ + MX50_WVGA_PAD_CTRL) + +/* CSPI */ +#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x0, 0, \ + PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | \ + PAD_CTL_DSE_HIGH) +#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, \ + NO_PAD_CTRL) + +/* NAND */ +#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, \ + PAD_CTL_PKE | \ + PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP) +#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) +#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, \ + PAD_CTL_DSE_HIGH) + +/* Keypad */ +#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) + +#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, \ + MX50_SD_PAD_CTRL) +#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, \ + NO_PAD_CTRL) +#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, \ + NO_PAD_CTRL) +#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, \ + NO_PAD_CTRL) +#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, \ + NO_PAD_CTRL) +#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, \ + MX50_KEYPAD_CTRL) +#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, \ + NO_PAD_CTRL) +#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, \ + MX50_KEYPAD_CTRL) +#endif /* __MACH_IOMUX_MX53_H__ */ + diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index ab0f95d953d0..7d5be77f8bbf 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -31,6 +31,8 @@ typedef enum iomux_config { IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ } iomux_pin_cfg_t; +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + /* Pad control groupings */ #define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_DSE_HIGH) @@ -38,36 +40,80 @@ typedef enum iomux_config { PAD_CTL_SRE_FAST) #define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ PAD_CTL_SRE_FAST) +#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) #define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_HYS) #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ PAD_CTL_SRE_FAST) +#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +#define MX51_PAD_CTRL_6 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS) +#define MX51_PAD_CTRL_7 MX51_UART2_PAD_CTRL +#define MX51_PAD_CTRL_8 (PAD_CTL_HYS | PAD_CTL_PKE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) +#define MX51_PAD_CTRL_9 (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_10 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_11 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX51_PAD_CTRL_12 (PAD_CTL_PKE | PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) +#define MX51_PAD_CTRL_13 (PAD_CTL_PKE | PAD_CTL_PUE) + +#define MX51_SDHC_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) + + + /* * The naming convention for the pad modes is MX51_PAD___ * If or refers to a GPIO, it is named * GPIO__ see also iomux-v3.h */ -/* - * FIXME: This was converted using scripts from existing Freescale code to - * this form used upstream. Need to verify the name format. - */ - /* PAD MUX ALT INPSE PATH PADCTRL */ +/* EIM */ +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, \ + 0x9b4, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, \ + 0x9b0, 0, MX51_I2C_PAD_CTRL) +#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, MX51_PAD_CTRL_7) -#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) - -/* Babbage UART3 */ +/* UART3 */ #define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) @@ -78,80 +124,96 @@ typedef enum iomux_config { #define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, PAD_CTL_PKE) +#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) -/* REVISIT: Not sure of these values - - #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL) - #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) - #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -*/ -#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, MX51_PAD_CTRL_3) + +#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12C, 1, 0x0, 0, MX51_PAD_CTRL_2) + +#define MX51_PAD_NANDF_RB5__GPIO_3_13 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) + +/* FEC */ +#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) +#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) + +#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) @@ -162,37 +224,54 @@ typedef enum iomux_config { #define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, PAD_CTL_SRE_SLOW) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, PAD_CTL_SRE_SLOW) #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) - -/* Babbage UART1 */ +#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, MX51_PAD_CTRL_12) +#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX51_PAD_CTRL_8) +#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, \ + IOMUX_CONFIG_SION, \ + 0x0, 0, MX51_PAD_CTRL_8) + +/* Audio */ +#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 0, 0x0, 0, MX51_PAD_CTRL_10) +#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 0, 0x0, 0, MX51_PAD_CTRL_10) + +/* CSPI */ +#define MX51_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_PAD_CTRL_11) +#define MX51_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_PAD_CTRL_11) + +#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) + +/* UART1 */ #define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) #define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) #define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) @@ -202,19 +281,29 @@ typedef enum iomux_config { #define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) #define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) -#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, MX51_PAD_CTRL_1) +#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_OWIRE_LINE__SPDIF_OUT1 IOMUX_PAD(0x638, 0x248, 6, 0x0, 0, MX51_PAD_CTRL_10 | MX51_PAD_CTRL_13) +#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0, 0, MX51_I2C_PAD_CTRL | MX51_PAD_CTRL_13) #define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) + +/* I2C2 */ +#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, \ + 0x09b8, 1, MX51_I2C_PAD_CTRL) +#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, \ + 0x9bc, 1, MX51_I2C_PAD_CTRL) + #define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) @@ -228,25 +317,25 @@ typedef enum iomux_config { #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, MX51_PAD_CTRL_7) +#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, MX51_PAD_CTRL_7) +#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) @@ -259,76 +348,69 @@ typedef enum iomux_config { #define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0, 0, NO_PAD_CTRL) + #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33C, 3, 0x9a0, 1, MX51_PAD_CTRL_7) #define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ - (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) -#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) -/* EIM */ -#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) +/* SD1 */ +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, MX51_SDHC_PAD_CTRL) -#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) +/* SD2 */ +#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1 | IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, MX51_SDHC_PAD_CTRL) + +#define MX51_PAD_GPIO_1_2__PWM_PWMO IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, 2 | IOMUX_CONFIG_SION, 0x9bc, 3, MX51_I2C_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, IOMUX_CONFIG_SION, 0x0, 0, MX51_PAD_CTRL_9) +#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, IOMUX_CONFIG_SION, 0x0 , 1, MX51_PAD_CTRL_6) +#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h new file mode 100644 index 000000000000..0fe881351579 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h @@ -0,0 +1,763 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __MACH_IOMUX_MX53_H__ +#define __MACH_IOMUX_MX53_H__ + +#include + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +#define IOMUX_TO_IRQ_V3(pin) (MXC_GPIO_IRQ_START + pin) + +#define NON_MUX_I 0x3FF +#define NON_PAD_I 0x7FF + +#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX53_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | PAD_CTL_DSE_HIGH) +#define MX53_ESAI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE |\ + PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define MX53_WEIM_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_DSE_HIGH) +#define PAD_CTRL_1 (PAD_CTL_HYS | PAD_CTL_DSE_HIGH) +#define PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH) +#define PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS) +#define PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP) +#define PAD_CTRL_5 (PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) + +#define PAD_CTRL_6 (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW) +#define PAD_CTRL_7 (PAD_CTL_DSE_HIGH | PAD_CTL_SRE_SLOW) +#define PAD_CTRL_8 (PAD_CTL_HYS | PAD_CTL_PKE) + +#define PAD_CTRL_9 (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) + +#define PAD_CTRL_10 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) + +#define PAD_CTRL_11 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) + +#define PAD_CTRL_12 (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) +#define PAD_CTRL_13 (PAD_CTL_SRE_FAST | PAD_CTL_ODE | PAD_CTL_PKE | PAD_CTL_PUE |\ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_HYS) + +#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_CSI0_DATA_EN__CSI0_DATA_EN IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D4__AUD3_TXC IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D5__AUD3_TXD IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D6__AUD3_TXFS IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D7__AUD3_RXD IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D24_UART3_TXD IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, \ + PAD_CTRL_9 | PAD_CTRL_2) +#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, PAD_CTRL_12) +#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) +#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_7__PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) + +/* NAND */ +#define MX53_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, PAD_CTRL_11) +#define MX53_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, PAD_CTRL_11) +#define MX53_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, PAD_CTRL_10) +#define MX53_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, PAD_CTRL_10) + +/* SPI */ +#define MX53_PAD_EIM_EB2__CSPI_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D19__CSPI_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 3, PAD_CTRL_1) + +/* PWM */ +#define MX53_PAD_GPIO_1__PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, NO_PAD_CTRL) + +/* Camera */ +#define MX53_PAD_CSI0_VSYNC__CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_MCLK__CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) + +/* IPU */ +#define MX53_PAD_CSI0_D12__CSI0_D12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D13__CSI0_D13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D14__CSI0_D14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D15__CSI0_D15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D16__CSI0_D16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D17__CSI0_D17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D18__CSI0_D18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D19__CSI0_D19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D20__SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D29__DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D30__DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D31__DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D23__DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A25__DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_OE__DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_EIM_RW__DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_EIM_DA10__DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D21__DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_D22__DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D4__CSI0_D4 IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D5__CSI0_D5 IOMUX_PAD(0x400, 0xD4, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D6__CSI0_D6 IOMUX_PAD(0x404, 0xD8, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D7__CSI0_D7 IOMUX_PAD(0x408, 0xDC, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D8__CSI0_D8 IOMUX_PAD(0x40C, 0xE0, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D9__CSI0_D9 IOMUX_PAD(0x410, 0xE4, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D10__CSI0_D10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_CSI0_D11__CSI0_D11 IOMUX_PAD(0x418, 0xEC, 0, 0x0, \ + 0, NO_PAD_CTRL) + +/* Display */ +#define MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, PAD_CTRL_5) +#define MX53_PAD_DI0_PIN15__DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, PAD_CTRL_5) +#define MX53_PAD_DI0_PIN2__DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DI0_PIN3__DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT0__DISP0_DAT0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT1__DISP0_DAT1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT2__DISP0_DAT2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT3__DISP0_DAT3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT4__DISP0_DAT4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT5__DISP0_DAT5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT6__DISP0_DAT6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT7__DISP0_DAT7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT8__DISP0_DAT8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT9__DISP0_DAT9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT10__DISP0_DAT10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT11__DISP0_DAT11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT12__DISP0_DAT12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT13__DISP0_DAT13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT14__DISP0_DAT14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT15__DISP0_DAT15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT16__DISP0_DAT16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT17__DISP0_DAT17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT18__DISP0_DAT18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT19__DISP0_DAT19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT20__DISP0_DAT20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT21__DISP0_DAT21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT22__DISP0_DAT22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT23__DISP0_DAT23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, PAD_CTRL_7) + +#define MX53_PAD_DI0_PIN15__AUD6_TXC IOMUX_PAD(0x37C, 0x50, 2, 0x0, \ + 0, PAD_CTRL_6) +#define MX53_PAD_DI0_PIN3__AUD6_TXFS IOMUX_PAD(0x384, 0x58, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DI0_PIN4__AUD6_RXD IOMUX_PAD(0x388, 0x5C, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DI0_DISP_CLK__USBH2_DIR IOMUX_PAD(0x378, 0x4C, 2, 0x0, \ + 0, PAD_CTRL_5) +#define MX53_PAD_DISP0_DAT0__USBH2_DAT0 IOMUX_PAD(0x38C, 0x60, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT1__USBH2_DAT1 IOMUX_PAD(0x390, 0x64, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT2__USBH2_DAT2 IOMUX_PAD(0x394, 0x68, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT3__USBH2_DAT3 IOMUX_PAD(0x398, 0x6C, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT4__USBH2_DAT4 IOMUX_PAD(0x39C, 0x70, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT5__USBH2_DAT5 IOMUX_PAD(0x3A0, 0x74, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT6__USBH2_DAT6 IOMUX_PAD(0x3A4, 0x78, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT7__USBH2_DAT7 IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT8__PWM1 IOMUX_PAD(0x3AC, 0x80, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT9__PWM2 IOMUX_PAD(0x3B0, 0x84, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT10__USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT11__USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT12__USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, \ + 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0xA0, 2, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0xA4, 2, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0xA8, 2, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0xAC, 2, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT20__AUD4_TXC IOMUX_PAD(0x3DC, 0xB0, 3, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT21__AUD4_TXD IOMUX_PAD(0x3E0, 0xB4, 3, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT22__AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, \ + 0x0, 0, PAD_CTRL_7) +#define MX53_PAD_DISP0_DAT23__AUD4_SSI_RXD IOMUX_PAD(0x3E8, 0xBC, 3, \ + 0x0, 0, PAD_CTRL_7) + +/* CAN*/ +#define MX53_PAD_KEY_COL2__TXCAN1 IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_KEY_ROW2__RXCAN1 IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, PAD_CTRL_3) +#define MX53_PAD_KEY_COL4__TXCAN2 IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_KEY_ROW4__RXCAN2 IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, PAD_CTRL_3) +#define MX53_PAD_ATA_RESET_B__TXCAN2 IOMUX_PAD(0x608, 0x288, 4, \ + 0x0, 0, PAD_CTRL_4) +#define MX53_PAD_ATA_IORDY__RXCAN2 IOMUX_PAD(0x60C, 0x28C, 4, \ + 0x764, 1, PAD_CTRL_3) + +/* AUD5 */ +#define MX53_PAD_KEY_COL0__AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW0__AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_COL1__AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_KEY_ROW1__AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x0, 0, NO_PAD_CTRL) + +/* I2C1 */ +#define MX53_PAD_CSI0_D8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, PAD_CTRL_13) +#define MX53_PAD_CSI0_D9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, PAD_CTRL_13) + +/* I2C2 */ +#define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, PAD_CTRL_9) +#define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, PAD_CTRL_9) +#define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, \ + 5 | IOMUX_CONFIG_SION, \ + 0x81C, 1, PAD_CTRL_9) + +/* I2C3 */ +#define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, \ + 2 | IOMUX_CONFIG_SION, \ + 0x824, 1, PAD_CTRL_9) +#define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6b4, 0x324, \ + 2 | IOMUX_CONFIG_SION, \ + 0x828, 1, PAD_CTRL_9) +#define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, \ + 6 | IOMUX_CONFIG_SION, \ + 0x828, 2, PAD_CTRL_9) + +/* UART1 */ +#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, \ + 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, \ + 3, MX53_UART_PAD_CTRL) + +/* UART2 */ +#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, \ + 0x0, 0, MX53_UART_PAD_CTRL) + +/* UART3 */ +#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, \ + 0x0, 0, MX53_UART_PAD_CTRL) +#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, \ + 0x884, 5, MX53_UART_PAD_CTRL) +/* CSPI */ +#define MX53_PAD_EIM_D16__CSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D17__CSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, PAD_CTRL_1) +#define MX53_PAD_EIM_D18__CSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, PAD_CTRL_1) + +/* LVDS0 */ +#define MX53_PAD_LVDS0_TX3_P__LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_CLK_P__LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX2_P__LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX1_P__LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS0_TX0_P__LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, NO_PAD_CTRL) + +/* LVDS1 */ +#define MX53_PAD_LVDS1_TX3_P__LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX2_P__LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_CLK_P__LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX1_P__LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_LVDS1_TX0_P__LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) + +/* SD1 */ +#define MX53_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x674, 0x2EC, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x67C, 0x2F4, \ + IOMUX_CONFIG_SION, 0x0, 0, \ + MX53_SDHC_PAD_CTRL | PAD_CTL_HYS) +#define MX53_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA8__SD1_DATA4 IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__SD1_DATA5 IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__SD1_DATA6 IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__SD1_DATA7 IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +/* SD2 */ +#define MX53_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x688, 0x2FC, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x68C, 0x300, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA0__SD2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA1__SD2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA2__SD2_DAT2 IOMUX_PAD(0x694, 0x308, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_SD2_DATA3__SD2_DAT3 IOMUX_PAD(0x690, 0x304, 0, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA12__SD2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, \ + 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA13__SD2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, \ + 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA14__SD2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, \ + 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA15__SD2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, \ + 0, MX53_SDHC_PAD_CTRL) + +/* SD3 */ +#define MX53_PAD_ATA_DATA8__SD3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA9__SD3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA10__SD3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA11__SD3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA0__SD3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA1__SD3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA2__SD3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_DATA3__SD3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, \ + 0x0, 0, MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_RESET_B__SD3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, \ + MX53_SDHC_PAD_CTRL) +#define MX53_PAD_ATA_IORDY__SD3_CLK IOMUX_PAD(0x60C, 0x28C, 2, \ + 0x0, 0, MX53_SDHC_PAD_CTRL | PAD_CTL_HYS) + +/* USB */ +#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) + +/* FEC */ +#define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, MX53_FEC_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__FEC_REF_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_CRS_DV__FEC_CRS_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RXD1__FEC_RXD1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_RXD0__FEC_RXD0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, PAD_CTRL_8) +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_TXD1__FEC_TXD1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_TXD0__FEC_TXD0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, PAD_CTL_DSE_HIGH) +#define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, PAD_CTL_DSE_HIGH) + +#define MX53_PAD_GPIO_0__SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, NO_PAD_CTRL) +#define MX53_PAD_GPIO_0__CLKO IOMUX_PAD(0x6A4, 0x314, 0, \ + 0x0, 0, NO_PAD_CTRL) + +/* MLB */ +#define MX53_PAD_GPIO_2__MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_GPIO_3__MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_GPIO_6__MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, \ + PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_FEC_MDC__MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, \ + 1, PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) +#define MX53_PAD_FEC_TXD1__MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, \ + 1, PAD_CTRL_2 | PAD_CTL_PUS_360K_DOWN | \ + PAD_CTL_HYS) + +/* SPDIF */ +#define MX53_PAD_GPIO_19__SPDIF_TX1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, \ + PAD_CTRL_3 | PAD_CTL_PUS_100K_UP) +#define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, \ + NO_PAD_CTRL) + +/* ESAI */ +#define MX53_PAD_FEC_MDIO__ESAI_SCKR IOMUX_PAD(0x5C4, 0x248, 2, \ + 0x7DC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_REF_CLK__ESAI_FSR IOMUX_PAD(0x5C8, 0x24C, 2, \ + 0x7CC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RX_ER__ESAI_HCKR IOMUX_PAD(0x5CC, 0x250, 2, \ + 0x7D4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_CRS_DV__ESAI_SCKT IOMUX_PAD(0x5D0, 0x254, 2, \ + 0x7E0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RXD1__ESAI_FST IOMUX_PAD(0x5D4, 0x258, 2, \ + 0x7D0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_RXD0__ESAI_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, \ + 0x7D8, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, \ + 0x7F0, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TXD1__ESAI_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, \ + 0x7EC, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_TXD0__ESAI_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, \ + 0x7F4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_FEC_MDC__ESAI_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, \ + 0x7F8, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_NANDF_CS2__ESAI_TX0 IOMUX_PAD(0x5B8, 0x240, 3, \ + 0x7E4, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_NANDF_CS3__ESAI_TX1 IOMUX_PAD(0x5BC, 0x244, 3, \ + 0x7E8, 0, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_GPIO_5__ESAI_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, \ + 0x7EC, 1, MX53_ESAI_PAD_CTRL) +#define MX53_PAD_GPIO_8__ESAI_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, \ + 0x7F8, 1, MX53_ESAI_PAD_CTRL) + +/* WEIM */ +#define MX53_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x460, 0x118, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x464, 0x11C, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x468, 0x120, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x46C, 0x124, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x470, 0x128, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x474, 0x12C, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x478, 0x130, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x47C, 0x134, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x484, 0x13C, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x488, 0x140, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x48C, 0x144, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x490, 0x148, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x494, 0x14C, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x498, 0x150, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x49C, 0x154, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) +#define MX53_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x4A0, 0x158, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) + +#define MX53_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x4D4, 0x188, 0, 0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_RW__EIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, 0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x4D0, 0x184, 0, 0, \ + 0, NO_PAD_CTRL) +#define MX53_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x4AC, 0x160, 0, 0, \ + 0, MX53_WEIM_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX53_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index f2f73d31d5ba..02e06dd7205b 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -1,4 +1,5 @@ /* + * Copyright (C) 2011 Freescale Semiconductor, Inc. * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, * * @@ -54,6 +55,11 @@ struct pad_desc { unsigned select_input:3; }; +struct pad_cfg { + struct pad_desc pd; + int pad_ctrl; +}; + #define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ _select_input, _pad_ctrl) \ { \ @@ -75,7 +81,9 @@ struct pad_desc { #define PAD_CTL_PKE (1 << 7) #define PAD_CTL_PUE (1 << 6) #define PAD_CTL_PUS_100K_DOWN (0 << 4) +#define PAD_CTL_PUS_360K_DOWN (0 << 4) #define PAD_CTL_PUS_47K_UP (1 << 4) +#define PAD_CTL_PUS_75K_UP (1 << 4) #define PAD_CTL_PUS_100K_UP (2 << 4) #define PAD_CTL_PUS_22K_UP (3 << 4) @@ -90,15 +98,20 @@ struct pad_desc { #define PAD_CTL_SRE_SLOW (0 << 0) /* - * setups a single pad in the iomuxer + * read/write a single pad in the iomuxer */ +int mxc_iomux_v3_get_pad(struct pad_desc *pad); int mxc_iomux_v3_setup_pad(struct pad_desc *pad); +int mxc_iomux_v3_setup_pad_ext(struct pad_cfg *pad); /* - * setups mutliple pads + * read/write mutliple pads * convenient way to call the above function with tables */ +int mxc_iomux_v3_get_multiple_pads(struct pad_desc *pad_list, unsigned count); int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); +int mxc_iomux_v3_setup_multiple_pads_ext(struct pad_cfg *pad_list, + unsigned count); /* * Initialise the iomux controller diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 86781f7b0c0c..1f00af566f4d 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -23,7 +23,9 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS /* these are ordered by size to support multi-SoC kernels */ -#if defined CONFIG_ARCH_MX2 +#if defined CONFIG_ARCH_MX53 +#define MXC_GPIO_IRQS (32 * 7) +#elif defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) #elif defined CONFIG_ARCH_MX1 #define MXC_GPIO_IRQS (32 * 4) @@ -35,6 +37,8 @@ #define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX3 #define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX37 +#define MXC_GPIO_IRQS (32 * 3) #endif /* @@ -47,10 +51,17 @@ #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 #define MXC_BOARD_IRQS 80 +#elif defined CONFIG_MACH_MX35_3DS +#define MXC_BOARD_IRQS 32 #else #define MXC_BOARD_IRQS 16 #endif +#ifdef CONFIG_MACH_MX35_3DS +#define MXC_PSEUDO_IO_BASE (MXC_BOARD_IRQ_START + 16) +#endif + + #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS) #ifdef CONFIG_MX3_IPU_IRQS @@ -69,4 +80,10 @@ extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); /* switch betwean IRQ and FIQ */ extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type); +/* + * This function is used to get the AVIC Lo and Hi interrupts + * that are enabled as wake up sources to wake up the core from suspend + */ +void mxc_get_wake_irq(u32 *wake_src[]); + #endif /* __ASM_ARCH_MXC_IRQS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index c4b40c35a6a1..83532f6f7c71 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -11,12 +11,18 @@ #ifndef __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__ +#include +#include + #define MX1_PHYS_OFFSET UL(0x08000000) #define MX21_PHYS_OFFSET UL(0xc0000000) #define MX25_PHYS_OFFSET UL(0x80000000) #define MX27_PHYS_OFFSET UL(0xa0000000) #define MX3x_PHYS_OFFSET UL(0x80000000) +#define MX37_PHYS_OFFSET UL(0x40000000) +#define MX50_PHYS_OFFSET UL(0x70000000) #define MX51_PHYS_OFFSET UL(0x90000000) +#define MX53_PHYS_OFFSET UL(0x70000000) #define MXC91231_PHYS_OFFSET UL(0x90000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) @@ -32,8 +38,12 @@ # define PHYS_OFFSET MX3x_PHYS_OFFSET # elif defined CONFIG_ARCH_MXC91231 # define PHYS_OFFSET MXC91231_PHYS_OFFSET -# elif defined CONFIG_ARCH_MX5 +# elif defined CONFIG_ARCH_MX51 # define PHYS_OFFSET MX51_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX53 +# define PHYS_OFFSET MX53_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX50 +# define PHYS_OFFSET MX50_PHYS_OFFSET # endif #endif @@ -50,6 +60,39 @@ * This is required for i.MX camera driver to capture at least four VGA frames. */ #define CONSISTENT_DMA_SIZE SZ_4M +#else + +#ifdef CONFIG_ARCH_MX5 +#define CONSISTENT_DMA_SIZE (96 * SZ_1M) +#else +#define CONSISTENT_DMA_SIZE (32 * SZ_1M) +#endif + #endif /* CONFIG_MX1_VIDEO */ +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_DMA_ZONE_SIZE +#define MXC_DMA_ZONE_SIZE ((CONFIG_DMA_ZONE_SIZE * SZ_1M) >> PAGE_SHIFT) +#else +#define MXC_DMA_ZONE_SIZE ((12 * SZ_1M) >> PAGE_SHIFT) +#endif + +static inline void __arch_adjust_zones(int node, unsigned long *zone_size, + unsigned long *zhole_size) +{ + if (node != 0) + return; + /* Create separate zone to reserve memory for DMA */ + zone_size[1] = zone_size[0] - MXC_DMA_ZONE_SIZE; + zone_size[0] = MXC_DMA_ZONE_SIZE; + zhole_size[1] = zhole_size[0]; + zhole_size[0] = 0; +} + +#define arch_adjust_zones(node, size, holes) \ + __arch_adjust_zones(node, size, holes) + +#endif + #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h index de2128dada5c..c56268f80ff6 100644 --- a/arch/arm/plat-mxc/include/mach/mmc.h +++ b/arch/arm/plat-mxc/include/mach/mmc.h @@ -33,4 +33,24 @@ struct imxmmc_platform_data { void (*setpower)(struct device *, unsigned int vdd); }; +struct mxc_mmc_platform_data { + unsigned int ocr_mask; /* available voltages */ + unsigned int vendor_ver; + unsigned int caps; + unsigned int min_clk; + unsigned int max_clk; + unsigned int clk_flg; /* 1 clock enable, 0 not */ + unsigned int clk_always_on; /* Needed by SDIO cards and etc */ + unsigned int dll_override_en; /* Enable dll override delay line */ + unsigned int dll_delay_cells; /* The number of delay cells (0-0x3f) */ + unsigned int reserved:16; + unsigned int card_fixed:1; + unsigned int card_inserted_state:1; +/* u32 (*translate_vdd)(struct device *, unsigned int);*/ + unsigned int (*status) (struct device *); + int (*wp_status) (struct device *); + char *power_mmc; + char *clock_mmc; +}; + #endif diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 4eb6e334bda5..f66d461f2749 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -1,6 +1,26 @@ #ifndef __MACH_MX25_H__ #define __MACH_MX25_H__ +/* + * IRAM + */ +#define MX25_IRAM_BASE_ADDR 0x78000000 /* internal ram */ +#define MX25_IRAM_SIZE SZ_128K +#define IRAM_SIZE MX25_IRAM_SIZE + +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define SND_RAM_SIZE 0x10000 +#else +#define SND_RAM_SIZE 0 +#endif + +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) +#define USB_IRAM_SIZE SZ_8K +#else +#define USB_IRAM_SIZE 0 +#endif + #define MX25_AIPS1_BASE_ADDR 0x43f00000 #define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX25_AIPS1_SIZE SZ_1M @@ -11,11 +31,54 @@ #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M +#define MX25_MAX_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x04000) +#define MX25_CLKCTL_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x08000) +#define MX25_ETB_SLOT4_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x0c000) +#define MX25_ETB_SLOT5_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x10000) +#define MX25_AAPE_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x14000) +#define MX25_I2C_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) +#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) +#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) +#define MX25_CAN3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) +#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) +#define MX25_OWIRE_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x9c000) +#define MX25_ATA_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa0000) +#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) +#define MX25_KPP_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa8000) #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) +#define MX25_AUDMUX_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xb0000) +#define MX25_ECT_A_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xb8000) +#define MX25_ECT_B_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xbc000) +#define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) +#define MX25_GPT4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x84000) +#define MX25_GPT3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x88000) +#define MX25_GPT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x8c000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_EPIT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x94000) +#define MX25_EPIT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x98000) +#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) +#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) +#define MX25_SCC_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xac000) +#define MX25_RNGB_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xb0000) +#define MX25_MMC_SDHC1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xb4000) +#define MX25_MMC_SDHC2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xb8000) +#define MX25_SLCDC_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc0000) +#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) +#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) +#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) +#define MX25_SDMA_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd4000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) +#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) +#define MX25_RTIC_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xec000) +#define MX25_IIM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xf0000) +#define MX25_USBOTG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xf4000) +#define OTG_BASE_ADDR MX25_USBOTG_BASE_ADDR +#define MX25_CSI_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xf8000) +#define MX25_SRTC_BASE_ADDR (DRYICE_BASE_ADDR) #define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) #define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) @@ -27,6 +90,8 @@ IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ IMX_IO_ADDRESS(x, MX25_AVIC)) +#define IO_ADDRESS MX25_IO_ADDRESS + #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 @@ -34,15 +99,210 @@ #define MX25_NFC_BASE_ADDR 0xbb000000 #define MX25_DRYICE_BASE_ADDR 0x53ffc000 #define MX25_LCDC_BASE_ADDR 0x53fbc000 +#define LCDC_BASE_ADDR MX25_LCDC_BASE_ADDR + +#define MX25_SPBA0_BASE_ADDR 0x50000000 +#define MX25_SPBA0_BASE_ADDR_VIRT 0xfc100000 +#define MX25_SPBA0_SIZE SZ_1M + +#define MX25_CSPI3_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x04000) +#define MX25_UART4_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x08000) +#define MX25_UART3_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x0c000) +#define MX25_CSPI2_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x10000) +#define MX25_SSI2_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x14000) +#define MX25_ESAI_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x18000) +#define MX25_ATA_DMA_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x20000) +#define MX25_SIM1_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x24000) +#define MX25_SIM2_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x28000) +#define MX25_UART5_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x2c000) +#define MX25_TSC_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x30000) +#define MX25_SSI1_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x34000) +#define MX25_SPBA_CTRL_BASE_ADDR (MX25_SPBA0_BASE_ADDR + 0x3c000) + +/* + * Interrupt numbers + */ +#define MX25_INT_CSPI3 0 +#define MX25_INT_GPT4 1 +#define MX25_INT_OWIRE 2 +#define MX25_INT_I2C 3 +#define MX25_INT_I2C2 4 +#define MX25_INT_UART4 5 +#define MX25_INT_RTIC 6 +#define MX25_INT_ESAI 7 +#define MX25_INT_SDHC2 8 +#define MX25_INT_SDHC1 9 +#define MX25_INT_I2C3 10 +#define MX25_INT_SSI2 11 +#define MX25_INT_SSI1 12 +#define MX25_INT_CSPI2 13 +#define MX25_INT_CSPI1 14 +#define MX25_INT_ATA 15 +#define MX25_INT_GPIO3 16 +#define MX25_INT_CSI 17 +#define MX25_INT_UART3 18 +#define MX25_INT_IIM 19 +#define MX25_INT_SIM1 20 +#define MX25_INT_SIM2 21 +#define MX25_INT_RNG 22 +#define MX25_INT_GPIO4 23 +#define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 -#define MX25_INT_FEC 57 +#define MX25_INT_PWM 26 +#define MX25_INT_EPIT2 27 +#define MX25_INT_EPIT1 28 +#define MX25_INT_GPT3 29 +#define MX25_INT_POWER_FAIL 30 +#define MX25_INT_CRM 31 +#define MX25_INT_UART2 32 #define MX25_INT_NANDFC 33 +#define MX25_INT_SDMA 34 +#define MX25_INT_USB_HTG 35 +#define MX25_INT_PWM2 36 +#define MX25_INT_USB_OTG 37 +#define MX25_INT_SLCDC 38 #define MX25_INT_LCDC 39 +#define MX25_INT_UART5 40 +#define MX25_INT_PWM3 41 +#define MX25_INT_PWM4 42 +#define MX25_INT_CAN1 43 +#define MX25_INT_CAN2 44 +#define MX25_INT_UART1 45 +#define MX25_INT_TSC 46 +#define MX25_INT_ECT 48 +#define MX25_INT_SCC_SCM 49 +#define MX25_INT_SCC_SMN 50 +#define MX25_INT_GPIO2 51 +#define MX25_INT_GPIO1 52 +#define MX25_INT_GPT2 53 +#define MX25_INT_GPT1 54 +#define MX25_INT_WDOG 55 +#define MX25_INT_DRYICE_SEC 56 +#define MX25_INT_FEC 57 +#define MX25_INT_EXT_INT5 58 +#define MX25_INT_EXT_INT4 59 +#define MX25_INT_EXT_INT3 60 +#define MX25_INT_EXT_INT2 61 +#define MX25_INT_EXT_INT1 62 +#define MX25_INT_EXT_INT0 63 + +#define MXC_INT_LCDC MX25_INT_LCDC +#define MXC_INT_GPT MX25_INT_GPT1 +#define MXC_INT_CSI MX25_INT_CSI + +/*! + * Defines for modules using static and dynamic DMA channels + */ +#define MXC_DMA_CHANNEL_IRAM 30 +#define MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART4_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART4_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART5_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART5_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL +#ifdef CONFIG_SDMA_IRAM +#define MXC_DMA_CHANNEL_SSI1_TX (MXC_DMA_CHANNEL_IRAM + 1) +#else +#define MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL +#endif +#define MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ESAI_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ESAI_TX MXC_DMA_DYNAMIC_CHANNEL + +/* + * DMA request assignments + */ +#define DMA_REQ_EXTREQ0 0 +#define DMA_REQ_CCM 1 +#define DMA_REQ_ATA_TX_END 2 +#define DMA_REQ_ATA_TX 3 +#define DMA_REQ_ATA_RX 4 +#define DMA_REQ_CSPI2_RX 6 +#define DMA_REQ_CSPI2_TX 7 +#define DMA_REQ_CSPI1_RX 8 +#define DMA_REQ_CSPI1_TX 9 +#define DMA_REQ_UART3_RX 10 +#define DMA_REQ_UART3_TX 11 +#define DMA_REQ_UART4_RX 12 +#define DMA_REQ_UART4_TX 13 +#define DMA_REQ_EXTREQ1 14 +#define DMA_REQ_EXTREQ2 15 +#define DMA_REQ_UART2_RX 16 +#define DMA_REQ_UART2_TX 17 +#define DMA_REQ_UART1_RX 18 +#define DMA_REQ_UART1_TX 19 +#define DMA_REQ_SSI2_RX1 22 +#define DMA_REQ_SSI2_TX1 23 +#define DMA_REQ_SSI2_RX0 24 +#define DMA_REQ_SSI2_TX0 25 +#define DMA_REQ_SSI1_RX1 26 +#define DMA_REQ_SSI1_TX1 27 +#define DMA_REQ_SSI1_RX0 28 +#define DMA_REQ_SSI1_TX0 29 +#define DMA_REQ_NFC 30 +#define DMA_REQ_ECT 31 +#define DMA_REQ_ESAI_RX 32 +#define DMA_REQ_ESAI_TX 33 +#define DMA_REQ_CSPI3_RX 34 +#define DMA_REQ_CSPI3_TX 35 +#define DMA_REQ_SIM2_RX 36 +#define DMA_REQ_SIM2_TX 37 +#define DMA_REQ_SIM1_RX 38 +#define DMA_REQ_SIM1_TX 39 +#define DMA_REQ_TSC_GCQ 44 +#define DMA_REQ_TSC_TCQ 45 +#define DMA_REQ_UART5_RX 46 +#define DMA_REQ_UART5_TX 47 + +#define IS_MEM_DEVICE_NONSHARED(x) 0 + +/*! + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)IO_ADDRESS(MX25_CCM_BASE_ADDR + 0x28))) +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) #define UART1_BASE_ADDR MX25_UART1_BASE_ADDR #define UART2_BASE_ADDR MX25_UART2_BASE_ADDR #endif +#define CSI_BASE_ADDR MX25_CSI_BASE_ADDR +#define AUDMUX_BASE_ADDR MX25_AUDMUX_BASE_ADDR +#define MXC_INT_ESAI MX25_INT_ESAI +#define SDMA_BASE_ADDR MX25_SDMA_BASE_ADDR +#define SCC_BASE_ADDR MX25_SCC_BASE_ADDR +#define MXC_INT_SCC_SCM MX25_INT_SCC_SCM +#define MXC_INT_SCC_SMN MX25_INT_SCC_SMN +#define DRYICE_BASE_ADDR MX25_DRYICE_BASE_ADDR +#define MXC_INT_DRYICE_NORM MX25_INT_DRYICE +#define MXC_INT_DRYICE_SEC MX25_INT_DRYICE_SEC +#define RNGB_BASE_ADDR MX25_RNGB_BASE_ADDR +#define MXC_INT_RNG MX25_INT_RNG +#define MXC_INT_USB_OTG MX25_INT_USB_OTG + +/*! + * IIM Bank info + **/ +#define MXC_IIM_BANK_START_ADDR 0x0000 +#define MXC_IIM_BANK_END_ADDR 0x007c + #endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index fb90e119c2b5..352eec09e5be 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -138,6 +138,23 @@ static inline void mx31_setup_weimcs(size_t cs, } #endif +/* + * DMA request assignments + */ +#define MX31_DMA_REQ_SDHC2 21 +#define MX31_DMA_REQ_SDHC1 20 +#define MX31_DMA_REQ_FIRI_TX 17 +#define MX31_DMA_REQ_FIRI_RX 16 +#define MX31_DMA_REQ_UART4_TX 13 +#define MX31_DMA_REQ_UART4_RX 12 +#define MX31_DMA_REQ_CSPI3_TX 11 +#define MX31_DMA_REQ_CSPI3_RX 10 +#define MX31_DMA_REQ_UART5_TX 11 +#define MX31_DMA_REQ_UART5_RX 10 +#define MX31_DMA_REQ_UART3_TX 9 +#define MX31_DMA_REQ_UART3_RX 8 +#define MX31_DMA_REQ_SIM 5 + #define MX31_INT_I2C3 3 #define MX31_INT_I2C2 4 #define MX31_INT_MPEG4_ENCODER 5 @@ -197,6 +214,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 +#define ARM11_PMU_IRQ MXC_INT_EVTMON + #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ /* silicon revisions specific to i.MX31 */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 526a55842ae5..9dbe06d097c8 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -1,11 +1,25 @@ #ifndef __MACH_MX35_H__ #define __MACH_MX35_H__ + +/*! + * Define this option to specify we are using the newer SDMA module. + */ +#define MXC_SDMA_V2 + /* * IRAM */ #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ #define MX35_IRAM_SIZE SZ_128K +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define SND_RAM_SIZE 0x10000 +#else +#define SND_RAM_SIZE 0 +#endif + +#define VPU_IRAM_SIZE 0 + #define MX35_L2CC_BASE_ADDR 0x30000000 #define MX35_L2CC_SIZE SZ_1M @@ -18,7 +32,7 @@ #define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) #define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) #define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) +#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) #define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) #define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) #define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) @@ -39,6 +53,10 @@ #define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) #define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) #define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) +#define MX35_SPDIF_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x28000) +#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) +#define MX35_ASRC_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x2C000) +#define MX35_ESAI_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x34000) #define MX35_FEC_BASE_ADDR 0x50038000 #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) @@ -52,6 +70,14 @@ #define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) #define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) #define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) +#define MX35_MMC_SDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xB4000) +#define MX35_MMC_SDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xB8000) +#define MX35_MMC_SDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xBC000) +#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xE4000) +#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xE8000) +#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xF0000) +#define MX35_OTG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xF4000) +#define MX35_MLB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xF8000) #define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) #define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) #define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) @@ -61,7 +87,6 @@ #define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) #define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) -#define MX35_OTG_BASE_ADDR 0x53ff4000 #define MX35_ROMP_BASE_ADDR 0x60000000 #define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 @@ -123,7 +148,7 @@ #define MX35_INT_MMC_SDHC1 7 #define MX35_INT_MMC_SDHC2 8 #define MX35_INT_MMC_SDHC3 9 -#define MX35_INT_I2C 10 +#define MX35_INT_I2C1 10 #define MX35_INT_SSI1 11 #define MX35_INT_SSI2 12 #define MX35_INT_CSPI2 13 @@ -189,6 +214,35 @@ #define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 #define MX35_SYSTEM_REV_NUM 3 +#define MX35_DMA_REQ_ASRC_DMA6 41 +#define MX35_DMA_REQ_ASRC_DMA5 40 +#define MX35_DMA_REQ_ASRC_DMA4 39 +#define MX35_DMA_REQ_ASRC_DMA3 38 +#define MX35_DMA_REQ_ASRC_DMA2 37 +#define MX35_DMA_REQ_ASRC_DMA1 36 +#define MX35_DMA_REQ_RSVD3 35 +#define MX35_DMA_REQ_RSVD2 34 +#define MX35_DMA_REQ_ESAI_TX 33 +#define MX35_DMA_REQ_ESAI_RX 32 +#define MX35_DMA_REQ_IPU 21 +#define MX35_DMA_REQ_RSVD1 20 +#define MX35_DMA_REQ_SPDIF_TX 13 +#define MX35_DMA_REQ_SPDIF_RX 12 +#define MX35_DMA_REQ_UART3_TX 11 +#define MX35_DMA_REQ_UART3_RX 10 +#define MX35_DMA_REQ_MSHC 5 +#define MX35_DMA_REQ_DPTC 1 +#define MX35_DMA_REQ_DVFS 1 + +/*! + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS \ + (*((volatile u32 *)MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR+0x18))) +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR @@ -207,4 +261,10 @@ #define MXC_INT_FEC MX35_INT_FEC #endif +/*! + * IIM bank info + */ +#define MXC_IIM_BANK_START_ADDR 0x0000 +#define MXC_IIM_BANK_END_ADDR 0x007c + #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 7a356de385f5..d5953f1b074a 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -152,16 +152,7 @@ * and returning the virtual address. If the physical address is not mapped, * it returns 0xDEADBEEF */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ - ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ - ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ - ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ - ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ - ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ - 0xDEADBEEF) +#define IO_ADDRESS MX31_IO_ADDRESS /* * define the address mapping macros: in physical address order @@ -196,6 +187,35 @@ #define PCMCIA_IO_ADDRESS(x) \ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) +/* + * DMA request assignments + */ +#define MX3x_DMA_REQ_ECT 31 +#define MX3x_DMA_REQ_NFC 30 +#define MX3x_DMA_REQ_SSI1_TX1 29 +#define MX3x_DMA_REQ_SSI1_RX1 28 +#define MX3x_DMA_REQ_SSI1_TX2 27 +#define MX3x_DMA_REQ_SSI1_RX2 26 +#define MX3x_DMA_REQ_SSI2_TX1 25 +#define MX3x_DMA_REQ_SSI2_RX1 24 +#define MX3x_DMA_REQ_SSI2_TX2 23 +#define MX3x_DMA_REQ_SSI2_RX2 22 +#define MX3x_DMA_REQ_UART1_TX 19 +#define MX3x_DMA_REQ_UART1_RX 18 +#define MX3x_DMA_REQ_UART2_TX 17 +#define MX3x_DMA_REQ_UART2_RX 16 +#define MX3x_DMA_REQ_EXTREQ1 15 +#define MX3x_DMA_REQ_EXTREQ2 14 +#define MX3x_DMA_REQ_CSPI1_TX 9 +#define MX3x_DMA_REQ_CSPI1_RX 8 +#define MX3x_DMA_REQ_CSPI2_TX 7 +#define MX3x_DMA_REQ_CSPI2_RX 6 +#define MX3x_DMA_REQ_ATA_RX 4 +#define MX3x_DMA_REQ_ATA_TX 3 +#define MX3x_DMA_REQ_ATA_TX_END 2 +#define MX3x_DMA_REQ_CCM 1 +#define MX3x_DMA_REQ_EXTREQ0 0 + /* * Interrupt numbers */ @@ -217,6 +237,7 @@ #define MX3x_INT_EPIT1 28 #define MX3x_INT_GPT 29 #define MX3x_INT_POWER_FAIL 30 +#define MX3x_INT_DVFS 31 #define MX3x_INT_UART2 32 #define MX3x_INT_NANDFC 33 #define MX3x_INT_SDMA 34 @@ -389,17 +410,6 @@ static inline int mx31_revision(void) #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG #define MXC_INT_EXT_TV MX3x_INT_EXT_TV #define PROD_SIGNATURE MX3x_PROD_SIGNATURE -#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0 -#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1 -#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2 -#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3 -#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0 -#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1 -#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2 -#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3 -#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0 -#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1 -#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 #define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN #define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM #endif diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 5aad344d5651..45ff0c7c4afb 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -349,9 +349,9 @@ #define MX51_MXC_INT_SLIM_B 28 #define MX51_MXC_INT_SSI1 29 #define MX51_MXC_INT_SSI2 30 -#define MX51_MXC_INT_UART1 31 -#define MX51_MXC_INT_UART2 32 -#define MX51_MXC_INT_UART3 33 +#define MX51_INT_UART1 31 +#define MX51_INT_UART2 32 +#define MX51_INT_UART3 33 #define MX51_MXC_INT_RESV34 34 #define MX51_MXC_INT_RESV35 35 #define MX51_MXC_INT_CSPI1 36 diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h new file mode 100644 index 000000000000..0f5cf5426ffd --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx5x.h @@ -0,0 +1,683 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_MX5X_H__ +#define __ASM_ARCH_MXC_MX5X_H__ + +#ifndef __ASM_ARCH_MXC_HARDWARE_H__ +#error "Do not include directly." +#endif + +/*! + * @file arch-mxc/mx5x.h + * @brief This file contains register definitions. + * + * @ingroup MSL_MX5 + */ + +/*! + * Register an interrupt handler for the SMN as well as the SCC. In some + * implementations, the SMN is not connected at all, and in others, it is + * on the same interrupt line as the SCM. Comment this line out accordingly + */ +#define USE_SMN_INTERRUPT + +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive Irda data. + */ +#define MXC_UART_IR_RXDMUX 0x0004 +/*! + * This option is used to set or clear the RXDMUXSEL bit in control reg 3. + * Certain platforms need this bit to be set in order to receive UART data. + */ +#define MXC_UART_RXDMUX 0x0004 + +/*! + * This option is used to set or clear the dspdma bit in the SDMA config + * register. + */ +#define MXC_SDMA_DSPDMA 0 + +/*! + * Define this option to specify we are using the newer SDMA module. + */ +#define MXC_SDMA_V2 + +/*! + * The maximum frequency that the pixel clock can be at so as to + * activate DVFS-PER. + */ +#define DVFS_MAX_PIX_CLK 54000000 + + +/* IROM + */ +#define IROM_BASE_ADDR 0x0 +#define IROM_SIZE SZ_64K + + /* + * IRAM + */ +#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ +#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ +#define IRAM_PARTITIONS 16 +#define IRAM_SIZE (IRAM_PARTITIONS*SZ_8K) /* 128KB */ + +#if defined(CONFIG_MXC_SECURITY_SCC2) \ + || defined(CONFIG_MXC_SECURITY_SCC2_MODULE) +#define SCC_RAM_SIZE SZ_16K +#else +#define SCC_RAM_SIZE 0 +#endif + +/* + * SCC RAM BASE: last 2 partitions of IRAM on MX51, separate from IRAM on MX53 + */ +#define MX51_SCC_RAM_BASE_ADDR MX51_IRAM_BASE_ADDR +#define MX53_SCC_RAM_BASE_ADDR 0x07000000 + +#ifdef CONFIG_SND_MXC_SOC_IRAM +#define SND_RAM_SIZE 0x6000 +#else +#define SND_RAM_SIZE 0 +#endif + +#ifdef CONFIG_MXC_VPU_IRAM +#define VPU_IRAM_SIZE 0x14000 +#else +#define VPU_IRAM_SIZE 0 +#endif + +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) +#define USB_IRAM_SIZE SZ_8K +#else +#define USB_IRAM_SIZE 0 +#endif + +/* + * NFC + */ +#define MX53_NFC_BASE_ADDR_AXI 0xF7FF0000 /* NAND flash AXI */ +#define MX51_NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ +#define NFC_BASE_ADDR_AXI_VIRT 0xF9000000 +#define NFC_AXI_SIZE SZ_64K + +/* + * Graphics Memory of GPU + */ +#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 +#define MX51_GPU_GMEM_BASE_ADDR 0x20000000 +#define GPU_BASE_ADDR 0x30000000 +#define MX53_GPU2D_BASE_ADDR 0x20000000 +#define MX51_GPU2D_BASE_ADDR 0xD0000000 + +#define MX53_TZIC_BASE_ADDR 0x0FFFC000 +#define MX51_TZIC_BASE_ADDR_T01 0x8FFFC000 +#define MX51_TZIC_BASE_ADDR 0xE0000000 +#define TZIC_SIZE SZ_16K + +/* + * AHCI SATA + */ +#define MX53_SATA_BASE_ADDR 0x10000000 + +/* + * Databahn MX50 + */ +#define MX50_DATABAHN_BASE_ADDR 0x14000000 +#define DATABAHN_CTL_REG19 0x4c +#define DATABAHN_CTL_REG20 0x50 +#define DATABAHN_CTL_REG21 0x54 +#define DATABAHN_CTL_REG22 0x58 +#define DATABAHN_CTL_REG23 0x5c +#define DATABAHN_CTL_REG42 0xa8 +#define DATABAHN_CTL_REG43 0xac +#define DATABAHN_CTL_REG55 0xdc +#define DATABAHN_CTL_REG63 0xFC +#define DATABAHN_CTL_REG73 0x124 +#define DATABAHN_CTL_REG74 0x128 +#define DATABAHN_CTL_REG75 0x12C +#define DATABAHN_CTL_REG83 0x14C +#define LOWPOWER_CONTROL_MASK 0x1F +#define LOWPOWER_AUTOENABLE_MASK 0x1F +#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16) +#define LOWPOWER_EXTERNAL_CNT_OFFSET 16 +#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8) +#define LOWPOWER_INTERNAL_CNT_OFFSET 8 +#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16) +#define LOWPOWER_REFRESH_ENABLE_OFFSET 16 +#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF +#define LOWPOWER_REFRESH_HOLD_OFFSET 0 + + +#define DEBUG_BASE_ADDR 0x40000000 +/*MX53 + 0x2000000 */ +#define DEBUG_SIZE SZ_1M +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) + +#define APBHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000) +#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) +#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000) +#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000) +#define BCH_BASE_ADDR (DEBUG_BASE_ADDR + 0x01008000) +#define ELCDIF_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100A000) +#define EPXP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100C000) +#define DCP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100E000) +#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000) +#define QOSC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01012000) +#define PERFMON_BASE_ADDR (DEBUG_BASE_ADDR + 0x01014000) +#define SSP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01016000) +#define ANATOP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01018000) + +#define MX50_NIC_BASE_ADDR (DEBUG_BASE_ADDR + 0x08000000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x70000000 +#define SPBA0_BASE_ADDR_VIRT 0xFB100000 +#define SPBA0_SIZE SZ_1M + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define ESAI_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) +#define ASRC_BASE_ADDR (SPBA0_BASE_ADDR + 0x0002C000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/*! + * defines for SPBA modules + */ +#define SPBA_SDHC1 0x04 +#define SPBA_SDHC2 0x08 +#define SPBA_UART3 0x0C +#define SPBA_CSPI1 0x10 +#define SPBA_SSI2 0x14 +#define SPBA_ESAI 0x18 +#define SPBA_SDHC3 0x20 +#define SPBA_SDHC4 0x24 +#define SPBA_SPDIF 0x28 +#define SPBA_ASRC 0x2C +#define SPBA_ATA 0x30 +#define SPBA_SLIM 0x34 +#define SPBA_HSI2C 0x38 +#define SPBA_CTRL 0x3C + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x73F00000 +#define AIPS1_BASE_ADDR_VIRT 0xF7E00000 +#define AIPS1_SIZE SZ_1M + +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define CAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C8000) +#define CAN2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000CC000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define MX53_ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000) +#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) +#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */ + +#define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180) +#define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4) +/*! + * Defines for modules using static and dynamic DMA channels + */ +#define MXC_DMA_CHANNEL_IRAM 30 +#define MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SPDIF_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART4_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART4_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART5_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_UART5_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL +#ifdef CONFIG_SDMA_IRAM +#define MXC_DMA_CHANNEL_SSI2_TX (MXC_DMA_CHANNEL_IRAM + 1) +#else /*CONFIG_SDMA_IRAM */ +#define MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL +#endif /*CONFIG_SDMA_IRAM */ +#define MXC_DMA_CHANNEL_SSI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_SSI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCC_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCC_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ESAI_RX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ESAI_TX MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_ESAI MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_ESAI MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCC_ESAI MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_SSI1_TX0 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_SSI1_TX1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_SSI2_TX0 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCA_SSI2_TX1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_SSI1_TX0 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_SSI1_TX1 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_SSI2_TX0 MXC_DMA_DYNAMIC_CHANNEL +#define MXC_DMA_CHANNEL_ASRCB_SSI2_TX1 MXC_DMA_DYNAMIC_CHANNEL + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x83F00000 +#define AIPS2_BASE_ADDR_VIRT 0xF7D00000 +#define AIPS2_SIZE SZ_1M + +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) +#define MLB_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) +#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) /* MX51 */ +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) /* MX51 */ +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) +#define PTP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000FC000) + +/* + * Memory regions and CS + */ +#define GPU_CTRL_BASE_ADDR 0x30000000 +#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 +#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define CS0_BASE_ADDR 0xB0000000 +#define CS1_BASE_ADDR 0xB8000000 +#define MX53_CS1_BASE_ADDR 0xF4000000 +#define CS2_BASE_ADDR 0xC0000000 +#define CS3_BASE_ADDR 0xC8000000 +#define CS4_BASE_ADDR 0xCC000000 +#define CS5_BASE_ADDR 0xCE000000 + +/*! + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + */ +#define IO_ADDRESS(x) \ + (void __force __iomem *) \ + ((((x) >= (unsigned long)SPBA0_BASE_ADDR) && \ + ((x) < (unsigned long)SPBA0_BASE_ADDR + SPBA0_SIZE)) ? \ + SPBA0_IO_ADDRESS(x) : \ + (((x) >= (unsigned long)AIPS1_BASE_ADDR) && \ + ((x) < (unsigned long)AIPS1_BASE_ADDR + AIPS1_SIZE)) ? \ + AIPS1_IO_ADDRESS(x) : \ + (((x) >= (unsigned long)AIPS2_BASE_ADDR) && \ + ((x) < (unsigned long)AIPS2_BASE_ADDR + AIPS2_SIZE)) ? \ + AIPS2_IO_ADDRESS(x) : \ + 0xDEADBEEF) + +/* + * define the address mapping macros: in physical address order + */ +#define SPBA0_IO_ADDRESS(x) \ + (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) + +#define AIPS1_IO_ADDRESS(x) \ + (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) + +#define AIPS2_IO_ADDRESS(x) \ + (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) + +#define MX53_BASE_ADDR(x) (cpu_is_mx53() || cpu_is_mx50() ? (x) - 0x20000000 : (x)) + +#define IS_MEM_DEVICE_NONSHARED(x) 0 + +/* + * DMA request assignments + */ +#define DMA_REQ_SSI3_TX1 47 +#define DMA_REQ_SSI3_RX1 46 +#define DMA_REQ_SSI3_TX2 DMA_REQ_SSI3_TX2_MX51 +#define DMA_REQ_SSI3_TX2_MX53 45 +#define DMA_REQ_SPDIF_MX51 45 +#define DMA_REQ_SSI3_RX2 44 +#define DMA_REQ_UART3_TX_MX53 43 +#define DMA_REQ_UART3_RX_MX53 42 +#define DMA_REQ_SLIM_B_TX 42 /* MX51 */ +#define DMA_REQ_UART3_TX_MX51 44 +#define DMA_REQ_UART3_RX_MX51 43 +#define DMA_REQ_UART3_TX_MX50 43 +#define DMA_REQ_UART3_RX_MX50 42 +#define DMA_REQ_ESAI_TX 41 +#define DMA_REQ_SDHC4_MX51 41 +#define DMA_REQ_ESAI_RX 40 +#define DMA_REQ_SDHC3 40 /* MX51 */ +#define DMA_REQ_CSPI_TX 39 +#define DMA_REQ_CSPI_RX 38 +#define DMA_REQ_ASRC_DMA6 37 +#define DMA_REQ_SSI3_TX2_MX51 37 /* MX51 */ +#define DMA_REQ_ASRC_DMA5 36 +#define DMA_REQ_IPU_MX51 36 +#define DMA_REQ_ASRC_DMA4 35 +#define DMA_REQ_ASRC_DMA3 34 + +#define DMA_REQ_EPIT2 34 /* MX51 */ +#define DMA_REQ_CTI2_1 33 /* MX51 */ +#define DMA_REQ_EMI_WR_MX51 32 +#define DMA_REQ_EMI_WR_MX53 31 +#define DMA_REQ_CTI2_0 31 + +#define DMA_REQ_ASRC_DMA2 33 +#define DMA_REQ_ASRC_DMA1 32 +#define DMA_REQ_EMI_RD 30 +#define DMA_REQ_SSI1_TX1 29 +#define DMA_REQ_SSI1_RX1 28 +#define DMA_REQ_SSI1_TX2 27 +#define DMA_REQ_SSI1_RX2 26 +#define DMA_REQ_SSI2_TX1 25 +#define DMA_REQ_SSI2_RX1 24 +#define DMA_REQ_SSI2_TX2 23 +#define DMA_REQ_SSI2_RX2 22 +/* I2C2 is shared w/SDHC2 on MX53 */ +#define DMA_REQ_SDHC2 21 +/* I2C1 is shared w/SDHC1 on MX53 */ +#define DMA_REQ_SDHC1 20 +#define DMA_REQ_UART1_TX 19 +#define DMA_REQ_UART1_RX 18 + +#define DMA_REQ_UART2_TX 17 /* MX51 */ +#define DMA_REQ_UART2_RX 16 /* MX51 */ +#define DMA_REQ_GPU 15 /* MX51 */ +#define DMA_REQ_EXTREQ1 14 /* MX51 */ + +#define DMA_REQ_UART5_TX 17 +#define DMA_REQ_UART5_RX 16 +#define DMA_REQ_SPDIF_TX 15 +#define DMA_REQ_SPDIF_RX 14 +#define DMA_REQ_EXTREQ0_MX50 14 +#define DMA_REQ_EXTREQ1_MX50 15 +/* UART2 is shared w/FIRI on MX53 */ +#define DMA_REQ_FIRI_TX 13 +#define DMA_REQ_FIRI_RX 12 +#define DMA_REQ_UART2_TX_MX50 13 +#define DMA_REQ_UART2_RX_MX50 12 +#define DMA_REQ_SDHC4_MX53 11 + +#define DMA_REQ_HS_I2C_RX 11 /* MX51 */ +#define DMA_REQ_HS_I2C_TX 10 /* MX51 */ +/* SDHC3 is shared w/I2C3 on MX53 */ +#define DMA_REQ_I2C3 10 +#define DMA_REQ_HS_I2C_RX 11 /* MX51 */ +#define DMA_REQ_HS_I2C_TX 10 /* MX51 */ +#define DMA_REQ_CSPI2_TX 9 +#define DMA_REQ_CSPI2_RX 8 +#define DMA_REQ_CSPI1_TX 7 +#define DMA_REQ_CSPI1_RX 6 +#define DMA_REQ_IPU_MX53 5 +#define DMA_REQ_SLIM_B 5 /* MX51 */ +#define DMA_REQ_ATA_TX_END 4 +#define DMA_REQ_ATA_TX 3 +#define DMA_REQ_UART4_TX_MX50 3 +#define DMA_REQ_ATA_RX 2 +#define DMA_REQ_UART4_RX_MX50 2 +#define DMA_REQ_GPC 1 +#define DMA_REQ_VPU 0 + +/* + * Interrupt numbers + */ +#define MXC_INT_BASE 0 +#define MXC_INT_RESV0 0 +#define MXC_INT_MMC_SDHC1 1 +#define MXC_INT_MMC_SDHC2 2 +#define MXC_INT_MMC_SDHC3 3 +#define MXC_INT_MMC_SDHC4 4 +#define MXC_INT_DAP 5 +#define MXC_INT_SDMA 6 +#define MXC_INT_IOMUX 7 +#define MXC_INT_NFC 8 +#define MXC_INT_VPU 9 +#define MXC_INT_IPU_ERR 10 +#define MXC_INT_IPU_SYN 11 +#define MXC_INT_GPU 12 +#define MXC_INT_UART4 13 +#define MXC_INT_USB_H1 14 +#define MXC_INT_EMI 15 +#define MXC_INT_USB_H2 16 +#define MXC_INT_USB_H3 17 +#define MXC_INT_USB_OTG 18 +#define MXC_INT_SAHARA_H0 19 +#define MXC_INT_DATABAHN 19 /* MX50 */ +#define MXC_INT_SAHARA_H1 20 +#define MXC_INT_ELCDIF 20 /* MX50 */ +#define MXC_INT_SCC_SMN 21 +#define MXC_INT_EPXP 21 /* MX50 */ +#define MXC_INT_SCC_STZ 22 +#define MXC_INT_SCC_SCM 23 +#define MXC_INT_SRTC_NTZ 24 +#define MXC_INT_SRTC_TZ 25 +#define MXC_INT_RTIC 26 +#define MXC_INT_CSU 27 +#define MXC_INT_EPDC 27 /* MX50 */ +#define MXC_INT_SATA 28 +#define MXC_INT_SLIM_B 28 /* MX51 */ +#define MXC_INT_NIC 28 /* MX50 Perfmon IRQ */ +#define MXC_INT_SSI1 29 +#define MXC_INT_SSI2 30 +#define MXC_INT_UART1 31 +#define MXC_INT_UART2 32 +#define MXC_INT_UART3 33 +#define MXC_INT_RTC 34 +#define MXC_INT_PTP 35 +#define MXC_INT_CSPI1 36 +#define MXC_INT_CSPI2 37 +#define MXC_INT_CSPI 38 +#define MXC_INT_GPT 39 +#define MXC_INT_EPIT1 40 +#define MXC_INT_EPIT2 41 +#define MXC_INT_GPIO1_INT7 42 +#define MXC_INT_GPIO1_INT6 43 +#define MXC_INT_GPIO1_INT5 44 +#define MXC_INT_GPIO1_INT4 45 +#define MXC_INT_GPIO1_INT3 46 +#define MXC_INT_GPIO1_INT2 47 +#define MXC_INT_GPIO1_INT1 48 +#define MXC_INT_GPIO1_INT0 49 +#define MXC_INT_GPIO1_LOW 50 +#define MXC_INT_GPIO1_HIGH 51 +#define MXC_INT_GPIO2_LOW 52 +#define MXC_INT_GPIO2_HIGH 53 +#define MXC_INT_GPIO3_LOW 54 +#define MXC_INT_GPIO3_HIGH 55 +#define MXC_INT_GPIO4_LOW 56 +#define MXC_INT_GPIO4_HIGH 57 +#define MXC_INT_WDOG1 58 +#define MXC_INT_WDOG2 59 +#define MXC_INT_KPP 60 +#define MXC_INT_PWM1 61 +#define MXC_INT_I2C1 62 +#define MXC_INT_I2C2 63 +#define MXC_INT_I2C3 64 +#define MXC_INT_HS_I2C 64 /* MX51 */ +#define MXC_INT_MLB 65 +#define MXC_INT_ASRC 66 +#define MXC_INT_SPDIF_MX53 67 +#define MXC_INT_SIM_IPB 67 +#define MXC_INT_SIM_DAT 68 +#define MXC_INT_IIM 69 +#define MXC_INT_ANATOP1 66 /* MX50 what's it? */ +#define MXC_INT_ANATOP2 67 +#define MXC_INT_ANATOP3 68 +#define MXC_INT_ANATOP4 69 +#define MXC_INT_ATA 70 +#define MXC_INT_CCM1 71 +#define MXC_INT_CCM2 72 +#define MXC_INT_GPC1 73 +#define MXC_INT_GPC2 74 +#define MXC_INT_SRC 75 +#define MXC_INT_NM 76 +#define MXC_INT_PMU 77 +#define MXC_INT_CTI_IRQ 78 +#define MXC_INT_CTI1_TG0 79 +#define MXC_INT_CTI1_TG1 80 +#define MXC_INT_ESAI 81 +#define MXC_INT_CAN1 82 +#define MXC_INT_CAN2 83 +#define MXC_INT_MCG_ERR 81 /* MX51 */ +#define MXC_INT_MCG_TMR 82 /* MX51 */ +#define MXC_INT_MCG_FUNC 83 /* MX51 */ +#define MXC_INT_GPU2_IRQ 84 +#define MXC_INT_GPU2_BUSY 85 +#define MXC_INT_UART5 86 +#define MXC_INT_FEC 87 +#define MXC_INT_OWIRE 88 +#define MXC_INT_CTI1_TG2 89 +#define MXC_INT_SJC 90 +#define MXC_INT_SPDIF_MX51 91 +#define MXC_INT_DCP_CHAN1_3 91 /* MX50 */ +#define MXC_INT_TVE 92 +#define MXC_INT_DCP_CHAN0 92 /* MX50 */ +#define MXC_INT_FIRI 93 +#define MXC_INT_DCP_CHAN0_3_SEC 93 /* MX50 */ +#define MXC_INT_PWM2 94 +#define MXC_INT_SLIM_EXP 95 +#define MXC_INT_SSI3 96 +#define MXC_INT_EMI_BOOT 97 +#define MXC_INT_RNGB_BLOCK 97 /* MX50 */ +#define MXC_INT_CTI1_TG3 98 +#define MXC_INT_SMC_RX 99 +#define MXC_INT_VPU_IDLE 100 +#define MXC_INT_RAWNAND_BCH 100 /* MX50 */ +#define MXC_INT_EMI_NFC 101 +#define MXC_INT_GPU_IDLE 102 +#define MXC_INT_RAWNAND_GPMI 102 /* MX50 */ +#define MXC_INT_GPIO5_LOW 103 +#define MXC_INT_GPIO5_HIGH 104 +#define MXC_INT_GPIO6_LOW 105 +#define MXC_INT_GPIO6_HIGH 106 +#define MXC_INT_GPIO7_LOW 107 +#define MXC_INT_GPIO7_HIGH 108 +#define MXC_INT_MSHC 109 /* MX50 */ +#define MXC_INT_APBHDMA_CHAN0 110 +#define MXC_INT_APBHDMA_CHAN1 111 +#define MXC_INT_APBHDMA_CHAN2 112 +#define MXC_INT_APBHDMA_CHAN3 113 +#define MXC_INT_APBHDMA_CHAN4 114 +#define MXC_INT_APBHDMA_CHAN5 115 +#define MXC_INT_APBHDMA_CHAN6 116 +#define MXC_INT_APBHDMA_CHAN7 117 +#define MXC_INT_APBHDMA_CHAN8 118 +#define MXC_INT_APBHDMA_CHAN9 119 +#define MXC_INT_APBHDMA_CHAN10 120 +#define MXC_INT_APBHDMA_CHAN11 121 +#define MXC_INT_APBHDMA_CHAN12 122 +#define MXC_INT_APBHDMA_CHAN13 123 +#define MXC_INT_APBHDMA_CHAN14 124 +#define MXC_INT_APBHDMA_CHAN15 125 + +/*! + * IIM bank info + */ +#define MXC_IIM_MX51_BANK_START_ADDR 0x0800 +#define MXC_IIM_MX51_BANK_END_ADDR 0x147c +#define MXC_IIM_MX53_BANK_START_ADDR 0x0800 +#define MXC_IIM_MX53_BANK_END_ADDR 0x183c +#define MXC_IIM_MX53_BANK_AREA_1_OFFSET 0xc00 +#define MXC_IIM_MX53_MAC_ADDR_OFFSET 0x24 + +#endif /* __ASM_ARCH_MXC_MX5X_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a790bf212972..39cc8a4617e4 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * * This program is free software; you can redistribute it and/or @@ -29,8 +29,12 @@ #define MXC_CPU_MX25 25 #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 +#define MXC_CPU_MX32 32 #define MXC_CPU_MX35 35 +#define MXC_CPU_MX37 37 +#define MXC_CPU_MX50 50 #define MXC_CPU_MX51 51 +#define MXC_CPU_MX53 53 #define MXC_CPU_MXC91231 91231 #ifndef __ASSEMBLY__ @@ -109,7 +113,19 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif -#ifdef CONFIG_ARCH_MX5 +#ifdef CONFIG_ARCH_MX37 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX37 +# endif +# define cpu_is_mx37() (mxc_cpu_type == MXC_CPU_MX37) +#else +# define cpu_is_mx37() (0) +#endif + +#ifdef CONFIG_ARCH_MX51 # ifdef mxc_cpu_type # undef mxc_cpu_type # define mxc_cpu_type __mxc_cpu_type @@ -121,6 +137,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx51() (0) #endif +#ifdef CONFIG_ARCH_MX53 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX53 +# endif +# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) +#else +# define cpu_is_mx53() (0) +#endif + #ifdef CONFIG_ARCH_MXC91231 # ifdef mxc_cpu_type # undef mxc_cpu_type @@ -133,6 +161,137 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mxc91231() (0) #endif +#ifdef CONFIG_ARCH_MX50 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX50 +# endif +# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) +#else +# define cpu_is_mx50() (0) +#endif + +#define cpu_is_mx32() (0) + +/* + * Create inline functions to test for cpu revision + * Function name is cpu_is__rev(rev) + * + * Returns: + * 0 - not the cpu queried + * 1 - cpu and revision match + * 2 - cpu matches, but cpu revision is greater than queried rev + * -1 - cpu matches, but cpu revision is less than queried rev + */ +#ifndef __ASSEMBLY__ +extern unsigned int system_rev; +#define mxc_set_system_rev(part, rev) ({ \ + system_rev = (part << 12) | rev; \ +}) +#define mxc_cpu() (system_rev >> 12) +#define mxc_cpu_rev() (system_rev & 0xFF) +#define mxc_cpu_rev_major() ((system_rev >> 4) & 0xF) +#define mxc_cpu_rev_minor() (system_rev & 0xF) +#define mxc_cpu_is_rev(rev) \ + ((mxc_cpu_rev() == rev) ? 1 : ((mxc_cpu_rev() < rev) ? -1 : 2)) +#define cpu_rev(type, rev) (cpu_is_##type() ? mxc_cpu_is_rev(rev) : 0) + +#define cpu_is_mx21_rev(rev) cpu_rev(mx21, rev) +#define cpu_is_mx25_rev(rev) cpu_rev(mx25, rev) +#define cpu_is_mx27_rev(rev) cpu_rev(mx27, rev) +#define cpu_is_mx31_rev(rev) cpu_rev(mx31, rev) +#define cpu_is_mx35_rev(rev) cpu_rev(mx35, rev) +#define cpu_is_mx37_rev(rev) cpu_rev(mx37, rev) +#define cpu_is_mx50_rev(rev) cpu_rev(mx50, rev) +#define cpu_is_mx51_rev(rev) cpu_rev(mx51, rev) +#define cpu_is_mx53_rev(rev) cpu_rev(mx53, rev) + + +#include + +extern void mxc_wd_reset(void); + +int mxc_snoop_set_config(u32 num, unsigned long base, int size); +int mxc_snoop_get_status(u32 num, u32 *statl, u32 *stath); + +struct platform_device; +void mxc_pg_enable(struct platform_device *pdev); +void mxc_pg_disable(struct platform_device *pdev); + +struct mxc_unifi_platform_data *get_unifi_plat_data(void); + +struct fsl_otp_data { + char **fuse_name; + char *regulator_name; + unsigned int fuse_num; +}; + +struct mxs_dma_plat_data { + unsigned int burst8:1; + unsigned int burst:1; + unsigned int chan_base; + unsigned int chan_num; +}; +#endif /* __ASSEMBLY__ */ + +/* DMA driver defines */ +#define MXC_IDE_DMA_WATERMARK 32 /* DMA watermark level in bytes */ +#define MXC_IDE_DMA_BD_NR (512/3/4) /* Number of BDs per channel */ + +/*! + * DPTC GP and LP ID + */ +#define DPTC_GP_ID 0 +#define DPTC_LP_ID 1 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 + +#if defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX25) +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * 32) + ((pin >> MUX_IO_I) & ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_IRQ_START + IOMUX_TO_GPIO(pin)) +#endif + +#ifndef __ASSEMBLY__ + +struct cpu_wp { + u32 pll_reg; + u32 pll_rate; + u32 cpu_rate; + u32 pdr0_reg; + u32 pdf; + u32 mfi; + u32 mfd; + u32 mfn; + u32 cpu_voltage; + u32 cpu_podf; +}; + +#ifndef CONFIG_ARCH_MX5 +struct cpu_wp *get_cpu_wp(int *wp); +#endif + +enum mxc_cpu_pwr_mode { + WAIT_CLOCKED, /* wfi only */ + WAIT_UNCLOCKED, /* WAIT */ + WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ + STOP_POWER_ON, /* just STOP */ + STOP_POWER_OFF, /* STOP + SRPG */ +}; + +void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode); +int tzic_enable_wake(int is_idle); +void gpio_activate_audio_ports(void); +void gpio_inactivate_audio_ports(void); +void gpio_activate_bt_audio_port(void); +void gpio_inactivate_bt_audio_port(void); +void gpio_activate_esai_ports(void); +void gpio_deactivate_esai_ports(void); + +#endif + #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) /* These are deprecated, use mx[23][157]_setup_weimcs instead. */ #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) @@ -140,6 +299,7 @@ extern unsigned int __mxc_cpu_type; #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) #endif +#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50()) #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) diff --git a/arch/arm/plat-mxc/include/mach/mxc_dptc.h b/arch/arm/plat-mxc/include/mach/mxc_dptc.h new file mode 100644 index 000000000000..4eeff5d8ba72 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_dptc.h @@ -0,0 +1,111 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DPTC Dynamic Process and Temperatur Compensation (DPTC) Driver + */ + +/*! + * @file arch-mxc/mxc_dptc.h + * + * @brief This file contains the DPTC configuration structure definition. + * + * + * @ingroup DPTC + */ + +#ifndef __ASM_ARCH_MXC_DPTC_H__ +#define __ASM_ARCH_MXC_DPTC_H__ + +#ifdef __KERNEL__ + +#include +#include +#include +#include + +#define DPTC_WP_SUPPORTED 17 +#define DPTC_GP_WP_SUPPORTED 7 +#define DPTC_LP_WP_SUPPORTED 9 + +struct dptc_wp { + u32 dcvr0; + u32 dcvr1; + u32 dcvr2; + u32 dcvr3; + u32 voltage; +}; + +/*! + * This structure is used to define the dptc controller's platform + * data. It includes the regulator name string and DPTC clock name string. + */ +struct mxc_dptc_data { + /** Regulator name string */ + char *reg_id; + /* DPTC clock name string */ + char *clk_id; + /* Control reg address */ + unsigned int dptccr_reg_addr; + /* Comparator value reg 0 address */ + unsigned int dcvr0_reg_addr; + /* GPC control reg address */ + unsigned int gpc_cntr_reg_addr; + /* DPTC interrupt status bit */ + unsigned int dptccr; + /* The number of DPTC working points */ + unsigned int dptc_wp_supported; + /* Maximum value of DPTC clock rate */ + unsigned long clk_max_val; + /* DPTC working points */ + struct dptc_wp *dptc_wp_allfreq; + /* DPTC enable bit */ + u32 dptc_enable_bit; + /* DPTC ADU bit */ + int gpc_adu; + /* VAI mask */ + u32 vai_mask; + /* VAI offset */ + int vai_offset; + /* Mask DPTC interrupt */ + u32 irq_mask; + /* DPTC no voltage change request bit */ + u32 dptc_nvcr_bit; + /* ARM interrrupt bit */ + u32 gpc_irq_bit; + /* dptc init config */ + u32 init_config; + /* dptc enable config */ + u32 enable_config; + /* dptc counting range mask */ + u32 dcr_mask; +}; + +/*! + * This function is called to put the DPTC in a low power state. + * + * @param id The DPTC device id. DPTC_GP_ID is for DPTC GP; + * DPTC_LP_ID is for DPTC LP + */ +void dptc_suspend(int id); +/*! + * This function is called to resume the DPTC from a low power state. + * + * @param id The DPTC device id. DPTC_GP_ID is for DPTC GP; + * DPTC_LP_ID is for DPTC LP + */ +void dptc_resume(int id); + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_DPTC_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h new file mode 100644 index 000000000000..35aefaa87966 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver + */ + +/*! + * @file arch-mxc/mxc_dvfs.h + * + * @brief This file contains the DVFS configuration structure definition. + * + * + * @ingroup DVFS + */ + +#ifndef __ASM_ARCH_MXC_DVFS_H__ +#define __ASM_ARCH_MXC_DVFS_H__ + +#ifdef __KERNEL__ + +#include +#include +#include +#include + +extern void __iomem *gpc_base; +extern void __iomem *ccm_base; + +#define MXC_GPCCNTR_GPCIRQ2M (1 << 25) +#define MXC_GPCCNTR_GPCIRQ2 (1 << 24) +#define MXC_GPCCNTR_GPCIRQM (1 << 21) +#define MXC_GPCCNTR_GPCIRQ_ARM (1 << 20) +#define MXC_GPCCNTR_GPCIRQ_SDMA (0 << 20) +#define MXC_GPCCNTR_DVFS0CR (1 << 16) +#define MXC_GPCCNTR_DVFS1CR (1 << 17) +#define MXC_GPCCNTR_ADU_MASK 0x8000 +#define MXC_GPCCNTR_ADU (1 << 15) +#define MXC_GPCCNTR_STRT (1 << 14) +#define MXC_GPCCNTR_FUPD_MASK 0x2000 +#define MXC_GPCCNTR_FUPD (1 << 13) +#define MXC_GPCCNTR_HTRI_MASK 0x0000000F +#define MXC_GPCCNTR_HTRI_OFFSET 0 + +#define MXC_GPCVCR_VINC_MASK 0x00020000 +#define MXC_GPCVCR_VINC_OFFSET 17 +#define MXC_GPCVCR_VCNTU_MASK 0x00010000 +#define MXC_GPCVCR_VCNTU_OFFSET 16 +#define MXC_GPCVCR_VCNT_MASK 0x00007FFF +#define MXC_GPCVCR_VCNT_OFFSET 0 + +/* DVFS-PER */ +#define MXC_DVFSPER_PMCR0_UDCS (1 << 27) +#define MXC_DVFSPER_PMCR0_UDCS_MASK 0x8000000 +#define MXC_DVFSPER_PMCR0_ENABLE_MASK 0x10 +#define MXC_DVFSPER_PMCR0_ENABLE (1 << 4) + +#define MXC_DVFSLTR0_UPTHR_MASK 0x0FC00000 +#define MXC_DVFSLTR0_UPTHR_OFFSET 22 +#define MXC_DVFSLTR0_DNTHR_MASK 0x003F0000 +#define MXC_DVFSLTR0_DNTHR_OFFSET 16 + +#define MXC_DVFSLTR1_PNCTHR_MASK 0x0000003F +#define MXC_DVFSLTR1_PNCTHR_OFFSET 0 +#define MXC_DVFSLTR1_DNCNT_MASK 0x003FC000 +#define MXC_DVFSLTR1_DNCNT_OFFSET 14 +#define MXC_DVFSLTR1_UPCNT_MASK 0x00003FC0 +#define MXC_DVFSLTR1_UPCNT_OFFSET 6 +#define MXC_DVFSLTR1_LTBRSR 0x800000 +#define MXC_DVFSLTR1_LTBRSH 0x400000 + +#define MXC_DVFSLTR2_EMAC_MASK 0x000001FF +#define MXC_DVFSLTR2_EMAC_OFFSET 0 + +#define MXC_DVFSPMCR0_UDCS 0x8000000 +#define MXC_DVFSPMCR0_DVFEV 0x800000 +#define MXC_DVFSPMCR0_DVFIS 0x400000 +#define MXC_DVFSPMCR0_LBMI 0x200000 +#define MXC_DVFSPMCR0_LBFL 0x100000 +#define MXC_DVFSPMCR0_LBFC_MASK 0xC0000 +#define MXC_DVFSPMCR0_LBFC_OFFSET 18 +#define MXC_DVFSPMCR0_FSVAIM 0x00008000 +#define MXC_DVFSPMCR0_FSVAI_MASK 0x00006000 +#define MXC_DVFSPMCR0_FSVAI_OFFSET 13 +#define MXC_DVFSPMCR0_WFIM 0x00000400 +#define MXC_DVFSPMCR0_WFIM_OFFSET 10 +#define MXC_DVFSPMCR0_DVFEN 0x00000010 + +#define MXC_DVFSPMCR1_P1INM 0x00100000 +#define MXC_DVFSPMCR1_P1ISM 0x00080000 +#define MXC_DVFSPMCR1_P1IFM 0x00040000 +#define MXC_DVFSPMCR1_P4PM 0x00020000 +#define MXC_DVFSPMCR1_P2PM 0x00010000 + +/* DVFS CORE register offsets*/ +#define MXC_DVFSCORE_THRS 0x00 +#define MXC_DVFSCORE_COUN 0x04 +#define MXC_DVFSCORE_SIG1 0x08 +#define MXC_DVFSCORE_SIG0 0x0C +#define MXC_DVFSCORE_GPC0 0x10 +#define MXC_DVFSCORE_GPC1 0x14 +#define MXC_DVFSCORE_GPBT 0x18 +#define MXC_DVFSCORE_EMAC 0x1C +#define MXC_DVFSCORE_CNTR 0x20 +#define MXC_DVFSCORE_LTR0_0 0x24 +#define MXC_DVFSCORE_LTR0_1 0x28 +#define MXC_DVFSCORE_LTR1_0 0x2C +#define MXC_DVFSCORE_LTR1_1 0x30 +#define MXC_DVFSCORE_PT0 0x34 +#define MXC_DVFSCORE_PT1 0x38 +#define MXC_DVFSCORE_PT2 0x3C +#define MXC_DVFSCORE_PT3 0x40 + +/* + * DVFS structure + */ +struct dvfs_wp { + int upthr; + int downthr; + int panicthr; + int upcnt; + int downcnt; + int emac; +}; + +struct mxc_dvfs_platform_data { + /** Supply voltage regulator name string */ + char *reg_id; + /* CPU clock name string */ + char *clk1_id; + /* DVFS clock name string */ + char *clk2_id; + /* The base address of the DVFS core */ + void __iomem *membase; + /* The interrupt number used by the DVFS core */ + int irq; + /* GPC control reg offset */ + int gpc_cntr_offset; + /* GPC voltage counter reg offset */ + int gpc_vcr_offset; + /* CCM DVFS control reg offset */ + int ccm_cdcr_offset; + /* CCM ARM clock root reg offset */ + int ccm_cacrr_offset; + /* CCM divider handshake in-progress reg offset */ + int ccm_cdhipr_offset; + /* PREDIV mask */ + u32 prediv_mask; + /* PREDIV offset */ + int prediv_offset; + /* PREDIV value */ + int prediv_val; + /* DIV3CK mask */ + u32 div3ck_mask; + /* DIV3CK offset */ + int div3ck_offset; + /* DIV3CK value */ + int div3ck_val; + /* EMAC value */ + int emac_val; + /* Frequency increase threshold. Increase frequency change request + will be sent if DVFS counter value will be more than this value */ + int upthr_val; + /* Frequency decrease threshold. Decrease frequency change request + will be sent if DVFS counter value will be less than this value */ + int dnthr_val; + /* Panic threshold. Panic frequency change request + will be sent if DVFS counter value will be more than this value */ + int pncthr_val; + /* The amount of times the up threshold should be exceeded + before DVFS will trigger frequency increase request */ + int upcnt_val; + /* The amount of times the down threshold should be exceeded + before DVFS will trigger frequency decrease request */ + int dncnt_val; + /* Delay time in us */ + int delay_time; + /* Number of woking points supported */ + int num_wp; +}; + +/*! + * This structure is used to define the dvfs controller's platform + * data. It includes the regulator name string and DVFS clock name string. + */ +struct mxc_dvfsper_data { + /** Regulator name string */ + char *reg_id; + /* DVFS clock name string */ + char *clk_id; + /* The base address of the DVFS per */ + void __iomem *membase; + /* GPC control reg address */ + void __iomem *gpc_cntr_reg_addr; + /* GPC VCR reg address */ + void __iomem *gpc_vcr_reg_addr; + /* DVFS enable bit */ + u32 dvfs_enable_bit; + /* DVFS ADU bit */ + int gpc_adu; + /* VAI mask */ + u32 vai_mask; + /* VAI offset */ + int vai_offset; + /* Mask DVFS interrupt */ + u32 irq_mask; + /* Div3 clock offset. */ + u32 div3_offset; + /*div3 clock mask. */ + u32 div3_mask; + /*div3 clock divider */ + u32 div3_div; + /* LP voltage - high setpoint*/ + u32 lp_high; + /* LP voltage - low setpoint*/ + u32 lp_low; +}; + +/*! + * This structure is used to define the platform data of bus freq + * driver. It includes the regulator name strings. + */ + +struct mxc_bus_freq_platform_data { + /* VDDGP regulator name */ + char *gp_reg_id; + /* VCC regulator name */ + char *lp_reg_id; +}; + +#if defined(CONFIG_MXC_DVFS_PER) +extern int start_dvfs_per(void); +extern void stop_dvfs_per(void); +extern int dvfs_per_active(void); +extern int dvfs_per_divider_active(void); +extern int dvfs_per_pixel_clk_limit(void); +#else +static inline int start_dvfs_per(void) +{ + return 0; +} + +static inline void stop_dvfs_per(void) +{ +} + +static inline int dvfs_per_active(void) +{ + return 0; +} + +static inline int dvfs_per_divider_active(void) +{ + return 0; +} + +static inline int dvfs_per_pixel_clk_limit(void) +{ + return 0; +} + +#endif + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_DVFS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_edid.h b/arch/arm/plat-mxc/include/mach/mxc_edid.h new file mode 100644 index 000000000000..f36a1d27d158 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_edid.h @@ -0,0 +1,40 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxc_edid.h + * + * @brief MXC EDID tools + * + * @ingroup Framebuffer + */ + +#ifndef MXC_EDID_H +#define MXC_EDID_H + +struct mxc_edid_cfg { + bool cea_underscan; + bool cea_basicaudio; + bool cea_ycbcr444; + bool cea_ycbcr422; + bool hdmi_cap; +}; + +int mxc_edid_read(struct i2c_adapter *adp, unsigned char *edid, + struct mxc_edid_cfg *cfg, struct fb_info *fbi); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_gpc.h b/arch/arm/plat-mxc/include/mach/mxc_gpc.h new file mode 100644 index 000000000000..8581fcc0da28 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_gpc.h @@ -0,0 +1,74 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup LPMD Low-Level Power Management Driver + */ + +/*! + * @file arch-mxc/mxc_gpc.h + * + * @brief This file contains the chip level configuration details and + * public API declarations for GPC module + * + * @ingroup LPMD + */ + +#ifndef __ASM_ARCH_MXC_GPC_H__ +#define __ASM_ARCH_MXC_GPC_H__ + +/* AP Power Gating modules */ +typedef enum { + POWER_GATING_MODULE_AP_EMBEDDED_MEM_DEEPSLEEP, + POWER_GATING_MODULE_DISPLAY_BUFFER, + POWER_GATING_MODULE_EMI_DEEPSLEEP, + POWER_GATING_MODULE_IPU_STOP, + POWER_GATING_MODULE_L2_MEM_STOP, + POWER_GATING_MODULE_ARM_PLATFORM_STOP, +} mxc_pm_ap_power_gating_modules_t; + +/* AP Power Gating pull-down config of modules */ +typedef enum { + POWER_GATING_PULL_DOWN_DISPLAY_BUFFER, + POWER_GATING_PULL_DOWN_EMI, + POWER_GATING_PULL_DOWN_IPU, + POWER_GATING_PULL_DOWN_L2_MEM, + POWER_GATING_PULL_DOWN_ARMPLATFORM, +} mxc_pm_ap_power_gating_pulldown_t; + +/*! + * This function enables/disables the AP power gating by writing the APPCR + * register of the GPC module. + * + * @param enable Enable/Disable module power down + * 0 - disable; 1 - enable + * @param modules The desired module to be power gated + * + */ +void mxc_gpc_powergate_module(int enable, + mxc_pm_ap_power_gating_modules_t module); + +/*! + * This function enables/disables the AP power gating pull down selection of a + * module by writing the APPCR register of the GPC module. + * + * @param enable Enable/Disable module pull down + * 0 - disable; 1 - enable + * @param modules The desired module to be pulled down + * + */ +void mxc_gpc_powergate_pulldown(int enable, + mxc_pm_ap_power_gating_pulldown_t pulldown); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_iim.h b/arch/arm/plat-mxc/include/mach/mxc_iim.h new file mode 100644 index 000000000000..de98687e2565 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_iim.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX_IIM_H__ +#define __IMX_IIM_H__ + +#include +#include + +/* IIM Control Registers */ +struct iim_regs { + u32 stat; + u32 statm; + u32 err; + u32 emask; + u32 fctl; + u32 ua; + u32 la; + u32 sdat; + u32 prev; + u32 srev; + u32 preg_p; + u32 scs0; + u32 scs1; + u32 scs2; + u32 scs3; +}; + +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) + +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) + +#define IIM_PROD_REV_SH 3 +#define IIM_PROD_REV_LEN 5 +#define IIM_SREV_REV_SH 4 +#define IIM_SREV_REV_LEN 4 +#define PROD_SIGNATURE_MX51 0x1 + +#define IIM_ERR_SHIFT 8 +#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT)) +#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT)) + +struct mxc_iim_data { + const s8 *name; + u32 virt_base; + u32 reg_base; + u32 reg_end; + u32 reg_size; + u32 bank_start; + u32 bank_end; + u32 irq; + u32 action; + struct mutex mutex; + struct completion completion; + spinlock_t lock; + struct clk *clk; + struct device *dev; + void (*enable_fuse)(void); + void (*disable_fuse)(void); +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_pm.h b/arch/arm/plat-mxc/include/mach/mxc_pm.h new file mode 100644 index 000000000000..5265ba033416 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_pm.h @@ -0,0 +1,252 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup LPMD Low-Level Power Management Driver + */ + +/*! + * @file arch-mxc/mxc_pm.h + * + * @brief This file contains the chip level configuration details and + * public API declarations for CRM_AP module + * + * @ingroup LPMD + */ + +#ifndef __ASM_ARCH_MXC_PM_H__ +#define __ASM_ARCH_MXC_PM_H__ + +#define WAIT_MODE 111 +#define DOZE_MODE 112 +#define STOP_MODE 113 +#define DSM_MODE 114 +/* + * MXC91231 Break-Point Frequency below which is low frequency and + * above which is high frequency + */ +#define BREAKPT_FREQ ((long)(400000000)) + +#define GATE_STOP_WAIT 9 +#define GATE_STOP 10 + +/* + * Used for MHz conversion + */ +#define MEGA_HERTZ 1000000 + +/* + * If invalid frequency value other than the following + * CORE_133 - ARM desired to run @133MHz, LoV (1.2V) + * CORE_266 - ARM desired to run @266MHz, LoV (1.2V) + * CORE_399 - ARM desired to run @399MHz, LoV (1.2V) + * CORE_532 - ARM desired to run @133MHz, HiV (1.6V) + * are passed then this error is returned, + */ +#define ERR_FREQ_INVALID 1 + +/* + * For MXC91231 Pass1, Integer DVFS greater than 133MHz is not allowed + * due to the hardware issue + */ +#define INTEGER_DVFS_NOT_ALLOW 1 + +/* + * If PLL freq is less than desired ARM frequency during Integer + * DVFS, then return this error + */ +#define PLL_LESS_ARM_ERR 2 + +/* + * Frequency change within the same-lo voltage is not approved. + * Inorder to do Integer DFS, move to the high voltage range and + * then set LFDF and move to the low voltage range + */ +#define INT_DFS_LOW_NOT_ALLOW 3 + +/* + * If the desired AHB or IPG exceeds 133MHz or 66.5MHz respectively, + * then return this error + */ +#define AHB_IPG_EXCEED_LIMIT 4 + +/* + * If the desired ARM frequency is too low to get by PLL scaling + * and the mxc_pm_pllscale API is called, return this error: + */ +#define PLL_DVFS_FREQ_TOO_LOW 5 + +/* + * Invalid frequencies requested + */ +#define MXC_PM_INVALID_PARAM 6 + +/* + * If AHB and/or IPG frequencies are greater than maximum allowed + */ +#define FREQ_OUT_OF_RANGE 2 + +/* + * If AHB and/or IPG frequencies are other than 100 or 50Mhz + */ +#define BUS_FREQ_INVALID 2 + +/* + * If MAX_PDF is greater than max value (8) then return this error + */ +#define AHB_MAX_DIV_ERR 3 + +/* + * If IPG_PDF is greater than max value (2) then return this error + */ +#define IPG_MAX_DIV_ERR 4 + +/* + * If ARM freq is out of range i.e., less than 133 or greater than + * 399 then return this error + */ +#define INVALID_ARM_FREQ 5 + +/* + * This file includes all platform APIs. Some of the APIs are not + * appicable to some platforms. So, this error is used to indicate + * that a particular API is not available + */ +#define MXC_PM_API_NOT_SUPPORTED 6 + +/* + * Error when frequency scaling is attempted while switch between MPLL and + * TPLL is in progress on MXC91321 + */ +#define ERR_DFSP_SWITCH 2 + +/*! + * Additional define for stop mode + */ +#define PM_SUSPEND_STOP ((__force suspend_state_t) 2) + +/*! + * CKOH pins configuration + */ +#define CKOH_AP_SEL 1 +#define CKOH_AHB_SEL 2 +#define CKOH_IP_SEL 3 + +/*! + * Defines for Stop and DSM mode acknowledgements + */ +#define MXC_PM_LOWPWR_ACK_SDMA 0x01 +#define MXC_PM_LOWPWR_ACK_IPU 0x02 +#define MXC_PM_LOWPWR_ACK_MAX 0x04 +#define MXC_PM_LOWPWR_ACK_MQSPI 0x08 +#define MXC_PM_LOWPWR_ACK_USB 0x10 +#define MXC_PM_LOWPWR_ACK_RTIC 0x20 + +/* + * PMIC configuration + */ +#define MXC_PMIC_1_2_VOLT 0xC +#define MXC_PMIC_1_6_VOLT 0x1C +#define MXC_PMIC_1_0_VOLT 0x4 +#if defined(CONFIG_ARCH_MXC91321) || defined(CONFIG_ARCH_MXC91231) +#define MXC_PMIC_DVS_SPEED 0x1 +#else +#define MXC_PMIC_DVS_SPEED 0x3 +#endif + +/*! + * Implementing Level 1 CRM Gate Control. Level 2 gate control + * is provided at module level using LPMD registers + * + * @param group The desired clock gate control register bits. + * Possible values are 0 through 6 + * @param opt The desired option requesting clock to run during stop + * and wait modes or just during the stop mode. Possible + * values are GATE_STOP_WAIT and GATE_STOP. + * + */ +void mxc_pm_clockgate(int group, int opt); + +/*! + * Implementing steps required to transition to low-power modes + * + * @param mode The desired low-power mode. Possible values are, + * WAIT_MODE, STOP_MODE or DSM_MODE + * + */ +void mxc_pm_lowpower(int mode); + +/*! + * Enables acknowledgement from module when entering stop or DSM mode. + * + * @param ack The desired module acknowledgement to enable. + * + */ +void mxc_pm_lp_ack_enable(int ack); + +/*! + * Disables acknowledgement from module when entering stop or DSM mode. + * + * @param ack The desired module acknowledgement to disable. + * + */ +void mxc_pm_lp_ack_disable(int ack); + +/*! + * Implementing steps required to set Integer Scaling + * + * @param armfreq The desired ARM frequency. AHB and IP + * frequency are changed depending on ARM + * frequency and the divider values. + * @param ahbfreq The desired AHB frequency + * @param ipfreq The desired IP frequency + * + * @return Returns 0 on success or + * Returns -PLL_LESS_ARM_ERR if pllfreq is less than + * desired core freq + */ +int mxc_pm_intscale(long armfreq, long ahbfreq, long ipfreq); + +/*! + * To calculate MFI, MFN, MFD values. Using this the output frequency + * whose value is calculated using, + * 2 * REF_FREQ * (MF / PDF), where + * REF_FREQ is 26 Mhz + * MF = MFI + (MFN + MFD) + * PDF is assumed to be 1 + * + * @param armfreq The desired ARM frequency + * @param ahbfreq The desired AHB frequency + * @param ipfreq The desired IP frequency + * + * @return Returns 0 on success or + * Returns -1 on error + */ +int mxc_pm_pllscale(long armfreq, long ahbfreq, long ipfreq); + +/*! + * To change AP core frequency and/or voltage suitably + * + * @param armfreq The desired ARM frequency + * @param ahbfreq The desired AHB frequency + * @param ipfreq The desired IP frequency + * + * @return Returns -ERR_FREQ_INVALID on failure + * Returns 0 on success + */ +int mxc_pm_dvfs(unsigned long armfreq, long ahbfreq, long ipfreq); + +extern void mxc_pm_arch_entry(void *entry, u32 size); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_rfkill.h b/arch/arm/plat-mxc/include/mach/mxc_rfkill.h new file mode 100644 index 000000000000..3a3d41496e15 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_rfkill.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef MXC_RFKILL_H +#define MXC_RFKILL_H + +struct mxc_bt_rfkill_platform_data { + int (*power_change) (int status); +}; + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_scc.h b/arch/arm/plat-mxc/include/mach/mxc_scc.h new file mode 100644 index 000000000000..b803d1683fb4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_scc.h @@ -0,0 +1,45 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file arch-mxc/mxc_scc.h + * + * @brief This is intended to be the file which contains all of code or changes + * needed to port the driver. + * + * @ingroup MXCSCC + */ + +#ifndef __ASM_ARCH_MXC_SCC_H__ +#define __ASM_ARCH_MXC_SCC_H__ + +#include + +/*! + * Expected to come from platform header files. + * This symbol must be the address of the SCC + */ +#define SCC_BASE SCC_BASE_ADDR + +/*! + * This must be the interrupt line number of the SCM interrupt. + */ +#define INT_SCC_SCM MXC_INT_SCC_SCM + +/*! + * if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of + * the SMN interrupt. + */ +#define INT_SCC_SMN MXC_INT_SCC_SMN + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h new file mode 100644 index 000000000000..a26eeed628d1 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_timer.h @@ -0,0 +1,158 @@ +/* + * mxc_timer.h + * + * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA. + */ + +#ifndef __PLAT_MXC_TIMER_H +#define __PLAT_MXC_TIMER_H + +#include +#include + +#ifdef CONFIG_ARCH_IMX +#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR) +#define TIMER_INTERRUPT TIM1_INT + +#define TCTL_VAL TCTL_CLK_PCLK1 +#define TCTL_IRQEN (1<<4) +#define TCTL_FRR (1<<8) +#define TCTL_CLK_PCLK1 (1<<1) +#define TCTL_CLK_PCLK1_4 (2<<1) +#define TCTL_CLK_TIN (3<<1) +#define TCTL_CLK_32 (4<<1) + +#define MXC_TCTL 0x00 +#define MXC_TPRER 0x04 +#define MXC_TCMP 0x08 +#define MXC_TCR 0x0c +#define MXC_TCN 0x10 +#define MXC_TSTAT 0x14 +#define TSTAT_CAPT (1<<1) +#define TSTAT_COMP (1<<0) + +static inline void gpt_irq_disable(void) +{ + unsigned int tmp; + + tmp = __raw_readl(TIMER_BASE + MXC_TCTL); + __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL); +} + +static inline void gpt_irq_enable(void) +{ + __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN, + TIMER_BASE + MXC_TCTL); +} + +static void gpt_irq_acknowledge(void) +{ + __raw_writel(0, TIMER_BASE + MXC_TSTAT); +} + +#elif defined(CONFIG_ARCH_MX2) +#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) +#define TIMER_INTERRUPT MXC_INT_GPT1 + +#define MXC_TCTL 0x00 +#define TCTL_VAL TCTL_CLK_PCLK1 +#define TCTL_CLK_PCLK1 (1<<1) +#define TCTL_CLK_PCLK1_4 (2<<1) +#define TCTL_IRQEN (1<<4) +#define TCTL_FRR (1<<8) +#define MXC_TPRER 0x04 +#define MXC_TCMP 0x08 +#define MXC_TCR 0x0c +#define MXC_TCN 0x10 +#define MXC_TSTAT 0x14 +#define TSTAT_CAPT (1<<1) +#define TSTAT_COMP (1<<0) + +static inline void gpt_irq_disable(void) +{ + unsigned int tmp; + + tmp = __raw_readl(TIMER_BASE + MXC_TCTL); + __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL); +} + +static inline void gpt_irq_enable(void) +{ + __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN, + TIMER_BASE + MXC_TCTL); +} + +static void gpt_irq_acknowledge(void) +{ + __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT); +} + +#else +#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) +#define TIMER_INTERRUPT MXC_INT_GPT + +#define MXC_TCTL 0x00 +#define TCTL_VAL (TCTL_CLK_HIGH_FREQ | TCTL_WAITEN) +#define TCTL_CLK_IPG (1<<6) +#define TCTL_CLK_HIGH_FREQ (2<<6) +#define TCTL_FRR (1<<9) +#define TCTL_WAITEN (1<<3) + +#define MXC_TPRER 0x04 +#define MXC_TSTAT 0x08 +#define TSTAT_OF1 (1<<0) +#define TSTAT_OF2 (1<<1) +#define TSTAT_OF3 (1<<2) +#define TSTAT_IF1 (1<<3) +#define TSTAT_IF2 (1<<4) +#define TSTAT_ROV (1<<5) +#define MXC_IR 0x0c +#define MXC_TCMP 0x10 +#define MXC_TCMP2 0x14 +#define MXC_TCMP3 0x18 +#define MXC_TCR 0x1c +#define MXC_TCN 0x24 + +static inline void gpt_irq_disable(void) +{ + __raw_writel(0, TIMER_BASE + MXC_IR); +} + +static inline void gpt_irq_enable(void) +{ + __raw_writel(1<<0, TIMER_BASE + MXC_IR); +} + +static inline void gpt_irq_acknowledge(void) +{ + __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT); +} +#endif /* CONFIG_ARCH_MX3 */ + +#define TCTL_SWR (1<<15) +#define TCTL_CC (1<<10) +#define TCTL_OM (1<<9) +#define TCTL_CAP_RIS (1<<6) +#define TCTL_CAP_FAL (2<<6) +#define TCTL_CAP_RIS_FAL (3<<6) +#define TCTL_CAP_ENA (1<<5) +#define TCTL_TEN (1<<0) + +#endif diff --git a/arch/arm/plat-mxc/include/mach/mxc_uart.h b/arch/arm/plat-mxc/include/mach/mxc_uart.h new file mode 100644 index 000000000000..a2669ecd542a --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_uart.h @@ -0,0 +1,275 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup UART Universal Asynchronous Receiver Transmitter (UART) Driver + */ + +/*! + * @file arch-mxc/mxc_uart.h + * + * @brief This file contains the UART configuration structure definition. + * + * + * @ingroup UART + */ + +#ifndef __ASM_ARCH_MXC_UART_H__ +#define __ASM_ARCH_MXC_UART_H__ + +#ifdef __KERNEL__ + +#include +#include + +/* + * The modes of the UART ports + */ +#define MODE_DTE 0 +#define MODE_DCE 1 +/* + * Is the UART configured to be a IR port + */ +#define IRDA 0 +#define NO_IRDA 1 + +/*! + * This structure is used to store the the physical and virtual + * addresses of the UART DMA receive buffer. + */ +typedef struct { + /*! + * DMA Receive buffer virtual address + */ + char *rx_buf; + /*! + * DMA Receive buffer physical address + */ + dma_addr_t rx_handle; +} mxc_uart_rxdmamap; + +/*! + * This structure is a way for the low level driver to define their own + * \b uart_port structure. This structure includes the core \b uart_port + * structure that is provided by Linux as an element and has other + * elements that are specifically required by this low-level driver. + */ +typedef struct { + /*! + * The port structure holds all the information about the UART + * port like base address, and so on. + */ + struct uart_port port; + /*! + * Flag to determine if the interrupts are muxed. + */ + int ints_muxed; + /*! + * Array that holds the receive and master interrupt numbers + * when the interrupts are not muxed. + */ + int irqs[2]; + /*! + * Flag to determine the DTE/DCE mode. + */ + int mode; + /*! + * Flag to hold the IR mode of the port. + */ + int ir_mode; + /*! + * Flag to enable/disable the UART port. + */ + int enabled; + /*! + * Flag to indicate if we wish to use hardware-driven hardware + * flow control. + */ + int hardware_flow; + /*! + * Holds the threshold value at which the CTS line is deasserted in + * case we use hardware-driven hardware flow control. + */ + unsigned int cts_threshold; + /*! + * Flag to enable/disable DMA data transfer. + */ + int dma_enabled; + /*! + * Holds the DMA receive buffer size. + */ + int dma_rxbuf_size; + /*! + * DMA Receive buffers information + */ + mxc_uart_rxdmamap *rx_dmamap; + /*! + * DMA RX buffer id + */ + int dma_rxbuf_id; + /*! + * DMA Transmit buffer virtual address + */ + char *tx_buf; + /*! + * DMA Transmit buffer physical address + */ + dma_addr_t tx_handle; + /*! + * Holds the RxFIFO threshold value. + */ + unsigned int rx_threshold; + /*! + * Holds the TxFIFO threshold value. + */ + unsigned int tx_threshold; + /*! + * Information whether this is a shared UART + */ + unsigned int shared; + /*! + * Clock id for UART clock + */ + struct clk *clk; + /*! + * Information whether RXDMUXSEL must be set or not for IR port + */ + int rxd_mux; + int ir_tx_inv; + int ir_rx_inv; + /*! + * DMA ID for transmit + */ + mxc_dma_device_t dma_tx_id; + /*! + * DMA ID for receive + */ + mxc_dma_device_t dma_rx_id; +} uart_mxc_port; + +/* Address offsets of the UART registers */ +#define MXC_UARTURXD 0x000 /* Receive reg */ +#define MXC_UARTUTXD 0x040 /* Transmitter reg */ +#define MXC_UARTUCR1 0x080 /* Control reg 1 */ +#define MXC_UARTUCR2 0x084 /* Control reg 2 */ +#define MXC_UARTUCR3 0x088 /* Control reg 3 */ +#define MXC_UARTUCR4 0x08C /* Control reg 4 */ +#define MXC_UARTUFCR 0x090 /* FIFO control reg */ +#define MXC_UARTUSR1 0x094 /* Status reg 1 */ +#define MXC_UARTUSR2 0x098 /* Status reg 2 */ +#define MXC_UARTUESC 0x09C /* Escape character reg */ +#define MXC_UARTUTIM 0x0A0 /* Escape timer reg */ +#define MXC_UARTUBIR 0x0A4 /* BRM incremental reg */ +#define MXC_UARTUBMR 0x0A8 /* BRM modulator reg */ +#define MXC_UARTUBRC 0x0AC /* Baud rate count reg */ +#define MXC_UARTONEMS 0x0B0 /* One millisecond reg */ +#define MXC_UARTUTS 0x0B4 /* Test reg */ + +/* Bit definations of UCR1 */ +#define MXC_UARTUCR1_ADEN 0x8000 +#define MXC_UARTUCR1_ADBR 0x4000 +#define MXC_UARTUCR1_TRDYEN 0x2000 +#define MXC_UARTUCR1_IDEN 0x1000 +#define MXC_UARTUCR1_RRDYEN 0x0200 +#define MXC_UARTUCR1_RXDMAEN 0x0100 +#define MXC_UARTUCR1_IREN 0x0080 +#define MXC_UARTUCR1_TXMPTYEN 0x0040 +#define MXC_UARTUCR1_RTSDEN 0x0020 +#define MXC_UARTUCR1_SNDBRK 0x0010 +#define MXC_UARTUCR1_TXDMAEN 0x0008 +#define MXC_UARTUCR1_ATDMAEN 0x0004 +#define MXC_UARTUCR1_DOZE 0x0002 +#define MXC_UARTUCR1_UARTEN 0x0001 + +/* Bit definations of UCR2 */ +#define MXC_UARTUCR2_ESCI 0x8000 +#define MXC_UARTUCR2_IRTS 0x4000 +#define MXC_UARTUCR2_CTSC 0x2000 +#define MXC_UARTUCR2_CTS 0x1000 +#define MXC_UARTUCR2_PREN 0x0100 +#define MXC_UARTUCR2_PROE 0x0080 +#define MXC_UARTUCR2_STPB 0x0040 +#define MXC_UARTUCR2_WS 0x0020 +#define MXC_UARTUCR2_RTSEN 0x0010 +#define MXC_UARTUCR2_ATEN 0x0008 +#define MXC_UARTUCR2_TXEN 0x0004 +#define MXC_UARTUCR2_RXEN 0x0002 +#define MXC_UARTUCR2_SRST 0x0001 + +/* Bit definations of UCR3 */ +#define MXC_UARTUCR3_DTREN 0x2000 +#define MXC_UARTUCR3_PARERREN 0x1000 +#define MXC_UARTUCR3_FRAERREN 0x0800 +#define MXC_UARTUCR3_DSR 0x0400 +#define MXC_UARTUCR3_DCD 0x0200 +#define MXC_UARTUCR3_RI 0x0100 +#define MXC_UARTUCR3_RXDSEN 0x0040 +#define MXC_UARTUCR3_AWAKEN 0x0010 +#define MXC_UARTUCR3_DTRDEN 0x0008 +#define MXC_UARTUCR3_RXDMUXSEL 0x0004 +#define MXC_UARTUCR3_INVT 0x0002 + +/* Bit definations of UCR4 */ +#define MXC_UARTUCR4_CTSTL_OFFSET 10 +#define MXC_UARTUCR4_CTSTL_MASK (0x3F << 10) +#define MXC_UARTUCR4_INVR 0x0200 +#define MXC_UARTUCR4_ENIRI 0x0100 +#define MXC_UARTUCR4_REF16 0x0040 +#define MXC_UARTUCR4_IRSC 0x0020 +#define MXC_UARTUCR4_TCEN 0x0008 +#define MXC_UARTUCR4_OREN 0x0002 +#define MXC_UARTUCR4_DREN 0x0001 + +/* Bit definations of UFCR */ +#define MXC_UARTUFCR_RFDIV 0x0200 /* Ref freq div is set to 2 */ +#define MXC_UARTUFCR_RFDIV_OFFSET 7 +#define MXC_UARTUFCR_RFDIV_MASK (0x7 << 7) +#define MXC_UARTUFCR_TXTL_OFFSET 10 +#define MXC_UARTUFCR_DCEDTE 0x0040 + +/* Bit definations of URXD */ +#define MXC_UARTURXD_ERR 0x4000 +#define MXC_UARTURXD_OVRRUN 0x2000 +#define MXC_UARTURXD_FRMERR 0x1000 +#define MXC_UARTURXD_BRK 0x0800 +#define MXC_UARTURXD_PRERR 0x0400 + +/* Bit definations of USR1 */ +#define MXC_UARTUSR1_PARITYERR 0x8000 +#define MXC_UARTUSR1_RTSS 0x4000 +#define MXC_UARTUSR1_TRDY 0x2000 +#define MXC_UARTUSR1_RTSD 0x1000 +#define MXC_UARTUSR1_FRAMERR 0x0400 +#define MXC_UARTUSR1_RRDY 0x0200 +#define MXC_UARTUSR1_AGTIM 0x0100 +#define MXC_UARTUSR1_DTRD 0x0080 +#define MXC_UARTUSR1_AWAKE 0x0010 + +/* Bit definations of USR2 */ +#define MXC_UARTUSR2_TXFE 0x4000 +#define MXC_UARTUSR2_IDLE 0x1000 +#define MXC_UARTUSR2_RIDELT 0x0400 +#define MXC_UARTUSR2_RIIN 0x0200 +#define MXC_UARTUSR2_DCDDELT 0x0040 +#define MXC_UARTUSR2_DCDIN 0x0020 +#define MXC_UARTUSR2_TXDC 0x0008 +#define MXC_UARTUSR2_ORE 0x0002 +#define MXC_UARTUSR2_RDR 0x0001 +#define MXC_UARTUSR2_BRCD 0x0004 + +/* Bit definations of UTS */ +#define MXC_UARTUTS_LOOP 0x1000 + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_UART_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h new file mode 100644 index 000000000000..36165f4268b6 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h @@ -0,0 +1,94 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup VPU Video Processor Unit Driver + */ + +/*! + * @file arch-mxc/mxc_vpu.h + * + * @brief VPU system initialization and file operation definition + * + * @ingroup VPU + */ + +#ifndef __ASM_ARCH_MXC_VPU_H__ +#define __ASM_ARCH_MXC_VPU_H__ + +#include + +struct vpu_mem_desc { + u32 size; + dma_addr_t phy_addr; + u32 cpu_addr; /* cpu address to free the dma mem */ + u32 virt_uaddr; /* virtual user space address */ +}; + +#define VPU_IOC_MAGIC 'V' + +#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0) +#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1) +#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2) +#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3) +#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4) +#define VPU_IOC_VL2CC_FLUSH _IO(VPU_IOC_MAGIC, 5) +#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6) +#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7) +#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8) +#define VPU_IOC_GET_PIC_PARA_ADDR _IO(VPU_IOC_MAGIC, 9) +#define VPU_IOC_GET_USER_DATA_ADDR _IO(VPU_IOC_MAGIC, 10) +#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11) +#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12) + +#define BIT_CODE_RUN 0x000 +#define BIT_CODE_DOWN 0x004 +#define BIT_INT_CLEAR 0x00C +#define BIT_INT_STATUS 0x010 + +#define BIT_WORK_CTRL_BUF_BASE 0x100 +#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4) +#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0) +#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1) +#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2) +#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3) +#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4) +#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5) + +#define BIT_RESET_CTRL 0x11C + +/* i could be 0, 1, 2, 3 */ +#define BIT_RD_PTR_BASE 0x120 +#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8) +#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4) + +/* i could be 0, 1, 2, 3 */ +#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140) +#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4) + +#define BIT_BUSY_FLAG 0x160 +#define BIT_RUN_COMMAND 0x164 +#define BIT_INT_ENABLE 0x170 + +#define BITVAL_PIC_RUN 8 + +#define VPU_SLEEP_REG_VALUE 10 +#define VPU_WAKE_REG_VALUE 11 + +int vl2cc_init(u32 vl2cc_hw_base); +void vl2cc_enable(void); +void vl2cc_flush(void); +void vl2cc_disable(void); +void vl2cc_cleanup(void); + +#endif diff --git a/arch/arm/plat-mxc/include/mach/pcmcia.h b/arch/arm/plat-mxc/include/mach/pcmcia.h new file mode 100644 index 000000000000..8426f15031d9 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pcmcia.h @@ -0,0 +1,218 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_PCMCIA_H__ +#define __ASM_ARCH_MXC_PCMCIA_H__ + +#include + +#define WINDOW_SIZE 0x1000000 /* The size of a window: 16M */ +#define PCMCIA_WINDOWS 5 /* How many windows / socket */ +#define SOCKET_NO 1 /* How many sockets */ + +#define ATTRIBUTE_MEMORY_WINDOW 0 +#define IO_WINDOW 1 +#define COMMON_MEMORY_WINDOW 2 + +/* + * PCMCIA socket + */ +#define PCMCIAPrtSp WINDOW_SIZE /* PCMCIA window size */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ + +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ +#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ + +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ + (PCMCIA_MEM_BASE_ADDR + (Nb) * PCMCIASp) + +#define _PCMCIAAttr(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ + +#define _PCMCIAIO(Nb) /* PCMCIA Attribute [0..1] */ \ + (_PCMCIA (Nb) + (IO_WINDOW) * PCMCIAPrtSp) +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ + (_PCMCIA (Nb) + (COMMON_MEMORY_WINDOW) * PCMCIAPrtSp) + +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ + +/* + * Module: PCMCIA, Addr Range: 0xB8004000 - 0xB8004FFF, Size: 4 Kbyte + */ +#define PCMCIA_BASE_ADDR (PCMCIA_CTL_BASE_ADDR) /* PCMCIA Base Address */ +#define PCMCIA_IO_ADDR(x) (*(volatile u32 *)PCMCIA_IO_ADDRESS(x)) + +#define _reg_PCMCIA_PIPR PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x00) /* PCMCIA input pins register */ +#define _reg_PCMCIA_PSCR PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x04) /* PCMCIA Status Changed Register */ +#define _reg_PCMCIA_PER PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x08) /* PCMCIA Enable Register */ + +/* win: 0-4 */ +#define _reg_PCMCIA_PBR(win) PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x0C + 4 * (win)) /* PCMCIA Base Register x */ +#define _reg_PCMCIA_POR(win) PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x28 + 4 * (win)) /* PCMCIA Option Register x */ +#define _reg_PCMCIA_POFR(win) PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x44 + 4 * (win)) /* PCMCIA Offset Register x */ + +#define _reg_PCMCIA_PGCR PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x60) /* PCMCIA General Control Register */ +#define _reg_PCMCIA_PGSR PCMCIA_IO_ADDR(PCMCIA_BASE_ADDR + 0x64) /* PCMCIA General Status Register */ + +/* PCMCIA_PIPR - PCMCIA Input Pins Register - fields */ +#define PCMCIA_PIPR_POWERON (1 << 8) /* card indicates "power on" */ +#define PCMCIA_PIPR_RDY (1 << 7) /* card is ready */ +#define PCMCIA_PIPR_BVD2 (1 << 6) /* battery voltage 2/SPKR in */ +#define PCMCIA_PIPR_BVD1 (1 << 5) /* battery voltage 1/STSCHG */ +#define PCMCIA_PIPR_CD (3 << 3) /* card detect 1 and 2 */ +#define PCMCIA_PIPR_WP (1 << 2) /* write protect switch enabled */ +#define PCMCIA_PIPR_VS (3 << 0) /* voltage sense bits */ +#define PCMCIA_PIPR_VS_5V (1 << 0) /* 5v */ + +/* PCMCIA_PSCR - PCMCIA Status Change Register - fields */ +#define PCMCIA_PSCR_POWC (1 << 11) /* */ +#define PCMCIA_PSCR_RDYR (1 << 10) /* */ +#define PCMCIA_PSCR_RDYF (1 << 9) /* */ +#define PCMCIA_PSCR_RDYH (1 << 8) /* */ +#define PCMCIA_PSCR_RDYL (1 << 7) /* */ +#define PCMCIA_PSCR_BVDC2 (1 << 6) /* */ +#define PCMCIA_PSCR_BVDC1 (1 << 5) /* */ +#define PCMCIA_PSCR_CDC2 (1 << 4) /* */ +#define PCMCIA_PSCR_CDC1 (1 << 3) /* */ +#define PCMCIA_PSCR_WPC (1 << 2) /* */ +#define PCMCIA_PSCR_VSC2 (1 << 1) /* */ +#define PCMCIA_PSCR_VSC1 (1 << 0) /* */ + +/* PCMCIA_PER - PCMCIA Enable Register - fields */ +#define PCMCIA_PER_ERRINTEN (1 << 12) /* error interrupt enable */ +#define PCMCIA_PER_POWERONEN (1 << 11) /* power on interrupt enable */ +#define PCMCIA_PER_RDYRE (1 << 10) /* RDY/nIREQ pin rising edge */ +#define PCMCIA_PER_RDYFE (1 << 9) /* RDY/nIREQ pin falling edge */ +#define PCMCIA_PER_RDYHE (1 << 8) /* RDY/nIREQ pin high */ +#define PCMCIA_PER_RDYLE (1 << 7) /* RDY/nIREQ pin low */ +#define PCMCIA_PER_BVDE2 (1 << 6) /* battery voltage 2/SPKR in */ +#define PCMCIA_PER_BVDE1 (1 << 5) /* battery voltage 1/STSCHG */ +#define PCMCIA_PER_CDE2 (1 << 4) /* card detect 2 */ +#define PCMCIA_PER_CDE1 (1 << 3) /* card detect 1 */ +#define PCMCIA_PER_WPE (1 << 2) /* write protect */ +#define PCMCIA_PER_VSE2 (1 << 1) /* voltage sense 2 */ +#define PCMCIA_PER_VSE1 (1 << 0) /* voltage sense 1 */ + +/* PCMCIA_POR[0-4] - PCMCIA Option Registers 0-4 - fields */ +#define PCMCIA_POR_PV (1 << 29) /* set iff bank is valid */ +#define PCMCIA_POR_WPEN (1 << 28) /* write protect (WP) input signal is enabled */ +#define PCMCIA_POR_WP (1 << 27) /* write protected */ + +#define PCMCIA_POR_PRS_SHIFT (25) +#define PCMCIA_POR_PRS(x) (((x) & 0x3) << PCMCIA_POR_PRS_SHIFT) +#define PCMCIA_POR_PRS_MASK PCMCIA_POR_PRS(3) /* PCMCIA region select */ +#define PCMCIA_POR_PRS_COMMON (0) /* values of POR_PRS field */ +#define PCMCIA_POR_PRS_TRUE_IDE (1) +#define PCMCIA_POR_PRS_ATTRIBUTE (2) +#define PCMCIA_POR_PRS_IO (3) + +#define PCMCIA_POR_PPS_8 (1 << 24) /* PCMCIA Port size = 8bits */ +#define PCMCIA_POR_PPS_16 (0 << 24) /* PCMCIA Port size = 16bits */ + +#define PCMCIA_POR_PSL_SHIFT (17) /* strobe length */ +#define PCMCIA_POR_PSL(x) (((x) & 0x7F) << PCMCIA_POR_PSL_SHIFT) +#define PCMCIA_POR_PSL_MASK PCMCIA_POR_PSL(0x7f) + +#define PCMCIA_POR_PSST_SHIFT (11) /* strobe setup time */ +#define PCMCIA_POR_PSST(x) (((x) & 0x3F) << PCMCIA_POR_PSST_SHIFT) +#define PCMCIA_POR_PSST_MASK PCMCIA_POR_PSST(0x3f) + +#define PCMCIA_POR_PSHT_SHIFT (5) /* strobe hold time */ +#define PCMCIA_POR_PSHT(x) (((x) & 0x3F) << PCMCIA_POR_PSHT_SHIFT) +#define PCMCIA_POR_PSHT_MASK PCMCIA_POR_PSHT(0x3f) + +#define PCMCIA_POR_BSIZE_SHIFT (0) /* bank size */ +#define PCMCIA_POR_BSIZE(x) (((x) & 0x1F) << PCMCIA_POR_BSIZE_SHIFT) +#define PCMCIA_POR_BSIZE_MASK PCMCIA_POR_BSIZE(0x1F) + +/* some handy BSIZE values */ +#define POR_BSIZE_1 PCMCIA_POR_BSIZE(0x00) +#define POR_BSIZE_2 PCMCIA_POR_BSIZE(0x01) +#define POR_BSIZE_4 PCMCIA_POR_BSIZE(0x03) +#define POR_BSIZE_8 PCMCIA_POR_BSIZE(0x02) +#define POR_BSIZE_16 PCMCIA_POR_BSIZE(0x06) +#define POR_BSIZE_32 PCMCIA_POR_BSIZE(0x07) +#define POR_BSIZE_64 PCMCIA_POR_BSIZE(0x05) +#define POR_BSIZE_128 PCMCIA_POR_BSIZE(0x04) +#define POR_BSIZE_256 PCMCIA_POR_BSIZE(0x0C) +#define POR_BSIZE_512 PCMCIA_POR_BSIZE(0x0D) +#define POR_BSIZE_1K PCMCIA_POR_BSIZE(0x0F) +#define POR_BSIZE_2K PCMCIA_POR_BSIZE(0x0E) + +#define POR_BSIZE_4K PCMCIA_POR_BSIZE(0x0A) +#define POR_BSIZE_8K PCMCIA_POR_BSIZE(0x0B) +#define POR_BSIZE_16K PCMCIA_POR_BSIZE(0x09) +#define POR_BSIZE_32K PCMCIA_POR_BSIZE(0x08) +#define POR_BSIZE_64K PCMCIA_POR_BSIZE(0x18) +#define POR_BSIZE_128K PCMCIA_POR_BSIZE(0x19) +#define POR_BSIZE_256K PCMCIA_POR_BSIZE(0x1B) +#define POR_BSIZE_512K PCMCIA_POR_BSIZE(0x1A) +#define POR_BSIZE_1M PCMCIA_POR_BSIZE(0x1E) +#define POR_BSIZE_2M PCMCIA_POR_BSIZE(0x1F) +#define POR_BSIZE_4M PCMCIA_POR_BSIZE(0x1D) +#define POR_BSIZE_8M PCMCIA_POR_BSIZE(0x1C) +#define POR_BSIZE_16M PCMCIA_POR_BSIZE(0x14) +#define POR_BSIZE_32M PCMCIA_POR_BSIZE(0x15) +#define POR_BSIZE_64M PCMCIA_POR_BSIZE(0x17) + +/* Window size */ +#define POR_1 0x1 +#define POR_2 0x2 +#define POR_4 0x4 +#define POR_8 0x8 +#define POR_16 0x10 +#define POR_32 0x20 +#define POR_64 0x40 +#define POR_128 0x80 +#define POR_256 0x100 +#define POR_512 0x200 + +#define POR_1K 0x400 +#define POR_2K 0x800 +#define POR_4K 0x1000 +#define POR_8K 0x2000 +#define POR_16K 0x4000 +#define POR_32K 0x8000 +#define POR_64K 0x10000 +#define POR_128K 0x20000 +#define POR_256K 0x40000 +#define POR_512K 0x80000 + +#define POR_1M 0x100000 +#define POR_2M 0x200000 +#define POR_4M 0x400000 +#define POR_8M 0x800000 +#define POR_16M 0x1000000 +#define POR_32M 0x2000000 +#define POR_64M 0x4000000 + +/* PCMCIA_PGCR - PCMCIA General Control Register - fields */ +#define PCMCIA_PGCR_LPMEN (1 << 3) /* Low power Mode Enable */ +#define PCMCIA_PGCR_SPKREN (1 << 2) /* SPKROUT routing enable */ +#define PCMCIA_PGCR_POE (1 << 1) /* Controller out enable */ +#define PCMCIA_PGCR_RESET (1 << 0) /* Card reset */ + +/* PCMCIA_PGSR - PCMCIA General Status Register - fields */ +#define PCMCIA_PGSR_NWINE (1 << 4) /* No Window error */ +#define PCMCIA_PGSR_LPE (1 << 3) /* Low Power error */ +#define PCMCIA_PGSR_SE (1 << 2) /* Size error */ +#define PCMCIA_PGSR_CDE (1 << 1) /* Card Detect error */ +#define PCMCIA_PGSR_WPE (1 << 0) /* Write Protect error */ + +#endif /* __ASM_ARCH_MXC_PCMCIA_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/pmic_audio.h b/arch/arm/plat-mxc/include/mach/pmic_audio.h new file mode 100644 index 000000000000..6754d5a6d04e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pmic_audio.h @@ -0,0 +1,2315 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_AUDIO_H__ +#define __ASM_ARCH_MXC_PMIC_AUDIO_H__ + +/*! + * @defgroup PMIC_AUDIO PMIC Audio Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_audio.h + * @brief External definitions for the PMIC Audio Client driver. + * + * The PMIC Audio driver and this API were developed to support the + * audio playback, recording, and mixing capabilities of the power + * management ICs that are available from Freescale Semiconductor, Inc. + * + * The following table shows which audio-related capabilities are supported + * by each power management IC: + * + * @ingroup PMIC_AUDIO + */ + +#include +#include + +/*************************************************************************** + * TYPEDEFS AND ENUMERATIONS * + ***************************************************************************/ + +/*! + * @name General Setup and Audio Device Access Typedefs and Enumerations + * Typedefs and enumerations that are used for initial access to the + * PMIC Audio hardware. + */ +/*@{*/ + +/*! + * @typedef PMIC_AUDIO_HANDLE + * @brief Define typedef for a handle to the PMIC Audio hardware. + * + * Define a "handle" that is returned when the PMIC Audio hardware + * is opened. This handle grants exclusive access to the PMIC Audio + * hardware and must be used in all subsequent function calls. When access + * to the PMIC Audio hardware is no longer required, then a close + * operation must be done with this handle. The handle is no longer valid + * if the close operation was successful. + */ +typedef long *PMIC_AUDIO_HANDLE; + +/*! + * @enum PMIC_AUDIO_EVENTS + * @brief Identify the audio events that have been detected and should be + * handled. + * + * This enumeration defines all of the possible PMIC Audio events. Multiple + * events may be selected when defining a mask and multiple events may be + * signalled together. + * + * Note that the MICROPHONE_DETECT and MICROPHONE_REMOVED events may also be + * used to signal the operation of a serial or parallel microphone switch + * when used with a combined headset+microphone device. In that case the + * HEADSET_DETECT state must also be checked to determine if it's only the + * microphone switch being operated or whether the microphone has truly been + * inserted/removed (along with the headset). + */ +typedef enum { + HEADSET_DETECTED = 1, /*!< Detected headset insertion. */ + HEADSET_STEREO = 2, /*!< Detected stereo headset device. */ + HEADSET_MONO = 4, /*!< Detected mono headset device. */ + HEADSET_THERMAL_SHUTDOWN = 8, /*!< Detected output amplifier + shutdown due to thermal + limits . */ + HEADSET_SHORT_CIRCUIT = 16, /*!< Detected output amplifier + short circuit condition + . */ + HEADSET_REMOVED = 32, /*!< Detected headset removal. */ + MICROPHONE_DETECTED = 64, /*!< Detected microphone insertion. */ + MICROPHONE_REMOVED = 128, /*!< Detected microphone removal. */ + PTT_BUTTON_PRESS = 256, /*!< Detected PTT button down + . */ + PTT_BUTTON_RANGE = 512, /*!< Detected PTT button within + voltage range + . */ + PTT_SHORT_OR_INVALID = 1024 /*!< Detected PTT button outside + of voltage range or invalid + device . */ +} PMIC_AUDIO_EVENTS; + +/*! + * @typedef PMIC_AUDIO_CALLBACK + * @brief Typedef for PMIC Audio event notification callback function. + * + * Define a typedef for the PMIC Audio event notification callback + * function. The signalled events are passed to the function as the first + * argument. The callback function should then process whatever events it + * can and then return the set of unhandled events (if any). + */ +typedef PMIC_AUDIO_EVENTS(*PMIC_AUDIO_CALLBACK) (const PMIC_AUDIO_EVENTS event); + +typedef struct { + int hs_state; + int event_type; +} PMIC_HS_STATE; + +/*! + * @enum PMIC_AUDIO_SOURCE + * @brief Select an audio signal processing component. + * + * This enumeration defines all of the possible PMIC audio signal handling + * components which can be acquired by calling pmic_audio_open(). + * + * Note that the EXTERNAL_STEREO_IN selection is used to simply gain access + * to the stereo input pins. The stereo input signal can then be routed + * directly to the output amplifiers. In this case, no signal processing is + * done by either the Voice CODEC or the Stereo DAC. + */ +typedef enum { + STEREO_DAC, /*!< Open connection to Stereo DAC. */ + VOICE_CODEC, /*!< Open connection to Voice CODEC. */ + EXTERNAL_STEREO_IN /*!< Open connection to external stereo inputs. */ +} PMIC_AUDIO_SOURCE; + +/*@}*/ + +/*! + * @name Data Bus Setup and Configuration Typedefs and Enumerations + * Typedefs and enumerations that are used to define and configure + * the data bus protocol in order to communicate with the Stereo DAC + * or the Voice CODEC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_DATA_BUS + * @brief Select the data bus used to transfer data between the host and + * Voice CODEC and/or the Stereo DAC. + * + * This enumeration defines all of the possible PMIC audio data buses that + * can be used to transfer data between the host and the Voice CODEC and/or + * the Stereo DAC on the PMIC. + * + * Note that the same data bus may be used to transfer audio data to/from + * the Voice CODEC and the Stereo DAC. However, in this case, the data bus + * must be configured for network mode with different timeslots assigned to + * the Voice CODEC and the Stereo DAC. Also, the sampling rates must be + * identical for both the Voice CODEC and the Stereo DAC in order to avoid + * a data bus timing conflict and audio signal distortion. + */ +typedef enum { + AUDIO_DATA_BUS_1, /*!< Use data bus 1 for audio data. */ + AUDIO_DATA_BUS_2 /*!< Use data bus 2 for audio data. */ +} PMIC_AUDIO_DATA_BUS; + +/*! + * @enum PMIC_AUDIO_BUS_PROTOCOL + * @brief Select the data bus protocol to be used. + * + * This enumeration defines all of the possible PMIC audio data bus protocols + * that may be selected. + */ +typedef enum { + NORMAL_MSB_JUSTIFIED_MODE, /*!< Transmit and receive audio data + in normal MSB-justified mode. */ + NETWORK_MODE, /*!< Transmit and receive audio data + in network mode. */ + I2S_MODE, /*!< Transmit and receive audio data + in I2S mode. */ + SPD_IF_MODE /*!< Transmit and receive audio data + in SPD/IF mode . */ +} PMIC_AUDIO_BUS_PROTOCOL; + +/*! + * @enum PMIC_AUDIO_BUS_MODE + * @brief Select the data bus mode to be used. + * + * This enumeration defines all of the possible PMIC audio data bus modes + * that may be selected. When configured in BUS_MASTER_MODE, the PMIC is + * responsible for supplying the data bus clock signals. Alternatively, + * when configured in BUS_SLAVE_MODE, the PMIC will use the data bus clock + * signals that are supplied by the bus master. + */ +typedef enum { + BUS_MASTER_MODE = 0, /*!< Operate as bus master. */ + BUS_SLAVE_MODE = 1 /*!< Operate as bus slave. */ +} PMIC_AUDIO_BUS_MODE; + +/*! + * @enum PMIC_AUDIO_CLOCK_IN_SOURCE + * @brief Select the clock signal source when in bus master mode. + * + * This enumeration defines all of the possible PMIC audio clock signal + * sources that may be selected. One of these clock signal sources must + * be selected in order to use either the Voice CODEC or the Stereo DAC. + * + * When configured in BUS_MASTER_MODE, the PMIC's onboard PLL circuits + * will also be driven by the selected clock input signal. + */ +typedef enum { + CLOCK_IN_DEFAULT, /*!< Just use default (power-up) clock input. */ + CLOCK_IN_CLIA, /*!< Use the CLIA clock source (Stereo DAC + default) . */ + CLOCK_IN_CLIB, /*!< Use the CLIB clock source (Voice CODEC + default) . */ + CLOCK_IN_CLKIN, /*!< Use the CLKIN clock source + . */ + CLOCK_IN_MCLK, /*!< Disable the internal PLL and use the MCLK + clock source (Stereo DAC only) + . */ + CLOCK_IN_FSYNC, /*!< Internal PLL input from external framesync + (Stereo DAC only) . */ + CLOCK_IN_BITCLK /*!< Internal PLL input from external bitclock + (Stereo DAC only) */ +} PMIC_AUDIO_CLOCK_IN_SOURCE; + +/*! + * @enum PMIC_AUDIO_CLOCK_INVERT + * @brief Select whether to invert the frame sync or bit clock signals. + * + * This enumeration enables or disables the inversion of the incoming + * frame sync or bit clock signals. + */ +typedef enum { + NO_INVERT = 0, /*!< Do not invert the clock signals. */ + INVERT_BITCLOCK = 1, /*!< Invert the BCLK input signal. */ + INVERT_FRAMESYNC = 2 /*!< Invert the FSYNC input signal. */ +} PMIC_AUDIO_CLOCK_INVERT; + +/*! + * @enum PMIC_AUDIO_NUMSLOTS + * @brief Select whether to invert the frame sync or bit clock signals. + * + * This enumeration defines all of the possible number of timeslots that may + * be selected when the PMIC is configured as the data bus master. One of these + * options must be selected if the Stereo DAC is to provide the data bus + * clock signals. + * + * Note that the Voice CODEC currently only allows USE_4_TIMESLOTS when + * operating in data bus master mode. + */ +typedef enum { + USE_2_TIMESLOTS, /*!< Configure for 2 timeslots. */ + USE_4_TIMESLOTS, /*!< Configure for 4 timeslots. */ + USE_8_STAR_TIMESLOTS, /*!< Configure for 8 (Left, Right, 6 other) timeslots. */ + USE_8_TIMESLOTS /*!< Configure for 8 timeslots. */ +} PMIC_AUDIO_NUMSLOTS; + +/*! + * @enum PMIC_AUDIO_STDAC_SAMPLING_RATE + * @brief Select the audio data sampling rate for the Stereo DAC. + * + * This enumeration defines all of the possible sampling rates currently + * supported by the Stereo DAC. One of these sampling rates must be selected + * and it must match that of the audio stream or else signal distortion will + * occur. + */ +typedef enum { + STDAC_RATE_8_KHZ, /*!< Use 8 kHz sampling rate. */ + STDAC_RATE_11_025_KHZ, /*!< Use 11.025 kHz sampling rate. */ + STDAC_RATE_12_KHZ, /*!< Use 12 kHz sampling rate. */ + STDAC_RATE_16_KHZ, /*!< Use 16 kHz sampling rate. */ + STDAC_RATE_22_050_KHZ, /*!< Use 22.050 kHz sampling rate. */ + STDAC_RATE_24_KHZ, /*!< Use 24 kHz sampling rate. */ + STDAC_RATE_32_KHZ, /*!< Use 32 kHz sampling rate. */ + STDAC_RATE_44_1_KHZ, /*!< Use 44.1 kHz sampling rate. */ + STDAC_RATE_48_KHZ, /*!< Use 48 kHz sampling rate. */ + STDAC_RATE_64_KHZ, /*!< Use 64 kHz sampling rate + . */ + STDAC_RATE_96_KHZ /*!< Use 96 kHz sampling rate. + . */ +} PMIC_AUDIO_STDAC_SAMPLING_RATE; + +/*! + * @enum PMIC_AUDIO_VCODEC_SAMPLING_RATE + * @brief Select the audio data sampling rate for the Voice CODEC. + * + * This enumeration defines all of the possible sampling rates currently + * supported by the Voice CODEC. One of these sampling rates must be selected + * and it must match that of the audio stream or else signal distortion will + * occur. + */ +typedef enum { + VCODEC_RATE_8_KHZ, /*!< Use 8 kHz sampling rate. */ + VCODEC_RATE_16_KHZ, /*!< Use 16 kHz sampling rate. */ +} PMIC_AUDIO_VCODEC_SAMPLING_RATE; + +/*! + * @enum PMIC_AUDIO_ANTI_POP_RAMP_SPEED + * @brief Select the anti-pop circuitry's ramp up speed. + * + * This enumeration defines all of the possible ramp up speeds for the + * anti-pop circuitry. A slow ramp up speed may be required in order to + * avoid the popping noise that is typically generated during the insertion + * or removal of a headset or microphone. + */ +typedef enum { + ANTI_POP_RAMP_FAST, /*!< Select fast ramp up. */ + ANTI_POP_RAMP_SLOW /*!< Select slow ramp up. */ +} PMIC_AUDIO_ANTI_POP_RAMP_SPEED; + +/*@}*/ + +/*! + * @name General Voice CODEC Configuration Typedefs and Enumerations + * Typedefs and enumerations that are used to define and configure + * the basic operating options for the Voice CODEC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ + * @brief Select the Voice CODEC input clock frequency. + * + * This enumeration defines all of the supported Voice CODEC input clock + * frequencies. One of these frequencies must be selected in order to + * properly configure the Voice CODEC to operate at the required sampling + * rate. + */ +typedef enum { + VCODEC_CLI_13MHZ, /*!< Clock frequency is 13MHz. */ + VCODEC_CLI_15_36MHZ, /*!< Clock frequency is 15.36MHz. */ + VCODEC_CLI_16_8MHZ, /*!< Clock frequency is 16.8MHz + . */ + VCODEC_CLI_26MHZ, /*!< Clock frequency is 26MHz. */ + VCODEC_CLI_33_6MHZ, /*!< Clock frequency is 33.6MHz. */ +} PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ; + +/*! + * @enum PMIC_AUDIO_VCODEC_CONFIG + * @brief Select the Voice CODEC configuration options. + * + * This enumeration is used to enable/disable each of the Voice CODEC options. + * This includes the use of highpass digital filters and audio signal + * loopback modes. + * + * Note that resetting the digital filters is now handled by the + * pmic_audio_digital_filter_reset() API. + */ +typedef enum { + DITHERING = 1, /*!< Enable/disable dithering. */ + INPUT_HIGHPASS_FILTER = 2, /*!< Enable/disable the input high + pass digital filter. */ + OUTPUT_HIGHPASS_FILTER = 4, /*!< Enable/disable the output high + pass digital filter. */ + ANALOG_LOOPBACK = 8, /*!< Enable/disable the analog + loopback path + . */ + DIGITAL_LOOPBACK = 16, /*!< Enable/disable the digital + loopback path. */ + VCODEC_MASTER_CLOCK_OUTPUTS = 32, /*!< Enable/disable the bus master + clock outputs. */ + TRISTATE_TS = 64 /*!< Enable/disable FSYNC, BITCLK, + and TX tristate. */ +} PMIC_AUDIO_VCODEC_CONFIG; + +/*@}*/ + +/*! + * @name General Stereo DAC Configuration Typedefs and Enumerations + * Typedefs and enumerations that are used to define and configure + * the basic operating options for the Stereo DAC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_STDAC_CLOCK_IN_FREQ + * @brief Select the Stereo DAC input clock frequency. + * + * This enumeration defines all of the supported Stereo DAC input clock + * frequencies. One of these frequencies must be selected in order to + * properly configure the Stereo DAC to operate at the required sampling + * rate. + */ +typedef enum { + STDAC_CLI_3_36864MHZ, /*!< Clock frequency is 3.36864MHz + . */ + STDAC_CLI_12MHZ, /*!< Clock frequency is 12MHz. + . */ + STDAC_CLI_13MHZ, /*!< Clock frequency is 13MHz. */ + STDAC_CLI_15_36MHZ, /*!< Clock frequency is 15.36MHz. */ + STDAC_CLI_16_8MHZ, /*!< Clock frequency is 16.8MHz + . */ + STDAC_CLI_26MHZ, /*!< Clock frequency is 26MHz. */ + STDAC_CLI_33_6MHZ, /*!< Clock frequency is 33.6MHz. */ + STDAC_MCLK_PLL_DISABLED, /*!< Use MCLK and disable internal PLL. */ + STDAC_FSYNC_IN_PLL, /*!< Use FSYNC as internal PLL input. */ + STDAC_BCLK_IN_PLL /*!< Use BCLK as internal PLL input. */ +} PMIC_AUDIO_STDAC_CLOCK_IN_FREQ; + +/*! + * @enum PMIC_AUDIO_STDAC_CONFIG + * @brief Select the Stereo DAC configuration options. + * + * This enumeration is used to enable/disable each of the Stereo DAC options. + */ +typedef enum { + STDAC_MASTER_CLOCK_OUTPUTS = 1 /*!< Enable/disable the bus master clock + outputs. */ +} PMIC_AUDIO_STDAC_CONFIG; + +/*@}*/ + +/*! + * @name Voice CODEC Audio Port Mixing Typedefs and Enumerations + * Typedefs and enumerations that are used for setting up the audio mixer + * within the Voice CODEC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_VCODEC_TIMESLOT + * @brief Select the Stereo DAC configuration options. + * + * This enumeration is used to select the timeslot for both the primary and + * secondary (for mc13783-only) audio channels to the Voice CODEC. + */ +typedef enum { + USE_TS0, /*!< Use timeslot 0 for audio signal source + . */ + USE_TS1, /*!< Use timeslot 1 for audio signal source + . */ + USE_TS2, /*!< Use timeslot 2 for audio signal source + . */ + USE_TS3 /*!< Use timeslot 3 for audio signal source + . */ +} PMIC_AUDIO_VCODEC_TIMESLOT; + +/*! + * @enum PMIC_AUDIO_VCODEC_MIX_IN_GAIN + * @brief Select the secondary channel input gain for the Voice CODEC mixer. + * + * This enumeration selects the secondary channel input gain for the Voice + * CODEC mixer. + */ +typedef enum { + VCODEC_NO_MIX, /*!< No audio mixing . */ + VCODEC_MIX_IN_0DB, /*!< Mix with 0dB secondary channel gain + . */ + VCODEC_MIX_IN_MINUS_6DB, /*!< Mix with -6dB secondary channel gain + . */ + VCODEC_MIX_IN_MINUS_12DB, /*!< Mix with -12dB secondary channel gain + . */ +} PMIC_AUDIO_VCODEC_MIX_IN_GAIN; + +/*! + * @enum PMIC_AUDIO_VCODEC_MIX_OUT_GAIN + * @brief Select the output gain for the Voice CODEC mixer. + * + * This enumeration selects the output gain for the Voice CODEC mixer. + */ +typedef enum { + VCODEC_MIX_OUT_0DB, /*!< Select 0dB mixer output gain + . */ + VCODEC_MIX_OUT_MINUS_6DB, /*!< Select -6dB mixer output gain + . */ +} PMIC_AUDIO_VCODEC_MIX_OUT_GAIN; + +/*@}*/ + +/*! + * @name Stereo DAC Audio Port Mixing Typedefs and Enumerations + * Typedefs and enumerations that are used for setting up the audio mixer + * within the Stereo DAC. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_STDAC_TIMESLOTS + * @brief Select the timeslots used to transmit the left and right audio + * channels to the Stereo DAC. + * + * This enumeration is used to select the timeslots used to transmit the + * data corresponding to the left and right audio channels to the Stereo + * DAC. + */ +typedef enum { + USE_TS0_TS1, /*!< Use timeslots 0 and 1 for left and + right channels, respectively. */ + USE_TS2_TS3, /*!< Use timeslots 2 and 3 for left and + right channels, respectively + . */ + USE_TS4_TS5, /*!< Use timeslots 4 and 5 for left and + right channels, respectively + . */ + USE_TS6_TS7 /*!< Use timeslots 6 and 7 for left and + right channels, respectively + . */ +} PMIC_AUDIO_STDAC_TIMESLOTS; + +/*! + * @enum PMIC_AUDIO_STDAC_MIX_IN_GAIN + * @brief Select the secondary channel input gain for the Stereo DAC mixer. + * + * This enumeration is used to select the secondary channel input gain for + * the Stereo DAC mixer. + */ +typedef enum { + STDAC_NO_MIX, /*!< No mixing, keep separate left + and right audio channels. */ + STDAC_MIX_IN_0DB, /*!< Mix left and right audio channels + together with 0dB secondary + channel gain. */ + STDAC_MIX_IN_MINUS_6DB, /*!< Mix left and right audio channels + together with -6dB secondary + channel gain. */ + STDAC_MIX_IN_MINUS_12DB /*!< Mix left and right audio channels + together with -12dB secondary + channel gain . */ +} PMIC_AUDIO_STDAC_MIX_IN_GAIN; + +/*! + * @enum PMIC_AUDIO_STDAC_MIX_OUT_GAIN + * @brief Select the output gain for the Stereo DAC mixer. + * + * This enumeration is used to select the output gain for the Stereo DAC + * mixer. + */ +typedef enum { + STDAC_MIX_OUT_0DB, /*!< Select 0dB mixer output gain. */ + STDAC_MIX_OUT_MINUS_6DB, /*!< Select -6dB mixer output gain + . */ +} PMIC_AUDIO_STDAC_MIX_OUT_GAIN; + +/*@}*/ + +/*! + * @name Microphone Input Typedefs and Enumerations + * Typedefs and enumerations that are used for selecting and setting up + * one or more or microphone inputs for recording. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_MIC_BIAS + * @brief Select the microphone bias circuit to be enabled/disabled. + * + * This enumeration lists all of the available microphone bias circuits that + * may be enabled or disabled. + */ +typedef enum { + NO_BIAS = 0, /*!< No microphone bias circuit selected. */ + MIC_BIAS1 = 1, /*!< Enable/disable microphone bias 1 circuit. */ + MIC_BIAS2 = 2, /*!< Enable/disable microphone bias 2 circuit. */ +} PMIC_AUDIO_MIC_BIAS; + +/*! + * @enum PMIC_AUDIO_INPUT_PORT + * @brief Select an audio input port for recording. + * + * This enumeration lists all of the available audio input ports that may + * be selected for a recording operation. + */ +typedef enum { + NO_MIC, /*!< No microphone input selected. */ + MIC1_LEFT, /*!< Enable left/mono channel microphone input + . */ + MIC1_RIGHT_MIC_MONO, /*!< Enable right channel microphone input. */ + MIC2_AUX, /*!< Enable auxiliary microphone input. */ + TXIN_EXT /*!< Enable external mono input. */ +} PMIC_AUDIO_INPUT_PORT; + +/*! + * @enum PMIC_AUDIO_INPUT_MIC_STATE + * @brief Control whether the input microphone is on/off. + * + * This enumeration allows the currently selected input microphone amplifier + * to be turned on/off. + */ +typedef enum { + MICROPHONE_ON, /*!< Turn microphone input on for recording. */ + MICROPHONE_OFF /*!< Turn microphone input off (mute). */ +} PMIC_AUDIO_INPUT_MIC_STATE; + +/*! + * @enum PMIC_AUDIO_INPUT_CONFIG + * @brief Enable/disable the audio input options. + * + * This enumeration allows for enabling/disabling any of the audio input + * section options. + */ +typedef enum { + MIC_AMP_AUTO_DISABLE = 1 /*!< Enable/disable automatic disabling of + microphone input amplifiers following + headset insertion/removal */ +} PMIC_AUDIO_INPUT_CONFIG; + +/*! + * @enum PMIC_AUDIO_MIC_AMP_MODE + * @brief Select the operating mode for the microphone amplifiers. + * + * This enumeration is used to select the operating mode for the microphone + * amplifier. + */ +typedef enum { + AMP_OFF, /*!< Disable input amplifier. */ + VOLTAGE_TO_VOLTAGE, /*!< Operate input amplifier in + voltage-to-voltage mode + . */ + CURRENT_TO_VOLTAGE /*!< Operate input amplifier in + current-to-voltage mode */ +} PMIC_AUDIO_MIC_AMP_MODE; + +/*! + * @enum PMIC_AUDIO_MIC_GAIN + * @brief Select the microphone amplifier gain level. + * + * This enumeration lists all of the available microphone amplifier gain + * levels. + */ +typedef enum { + MIC_GAIN_MINUS_8DB, /*!< Select -8dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_7DB, /*!< Select -7dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_6DB, /*!< Select -6dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_5DB, /*!< Select -5dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_4DB, /*!< Select -4dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_3DB, /*!< Select -3dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_2DB, /*!< Select -2dB microphone amplifier gain + . */ + MIC_GAIN_MINUS_1DB, /*!< Select -1dB microphone amplifier gain + . */ + MIC_GAIN_0DB, /*!< Select 0dB microphone amplifier gain. */ + MIC_GAIN_PLUS_1DB, /*!< Select 1dB microphone amplifier gain. */ + MIC_GAIN_PLUS_2DB, /*!< Select 2dB microphone amplifier gain. */ + MIC_GAIN_PLUS_3DB, /*!< Select 3dB microphone amplifier gain. */ + MIC_GAIN_PLUS_4DB, /*!< Select 4dB microphone amplifier gain. */ + MIC_GAIN_PLUS_5DB, /*!< Select 5dB microphone amplifier gain. */ + MIC_GAIN_PLUS_6DB, /*!< Select 6dB microphone amplifier gain. */ + MIC_GAIN_PLUS_7DB, /*!< Select 7dB microphone amplifier gain. */ + MIC_GAIN_PLUS_8DB, /*!< Select 8dB microphone amplifier gain. */ + MIC_GAIN_PLUS_9DB, /*!< Select 9dB microphone amplifier gain. */ + MIC_GAIN_PLUS_10DB, /*!< Select 10dB microphone amplifier gain. */ + MIC_GAIN_PLUS_11DB, /*!< Select 11dB microphone amplifier gain. */ + MIC_GAIN_PLUS_12DB, /*!< Select 12dB microphone amplifier gain. */ + MIC_GAIN_PLUS_13DB, /*!< Select 13dB microphone amplifier gain. */ + MIC_GAIN_PLUS_14DB, /*!< Select 14dB microphone amplifier gain. */ + MIC_GAIN_PLUS_15DB, /*!< Select 15dB microphone amplifier gain. */ + MIC_GAIN_PLUS_16DB, /*!< Select 16dB microphone amplifier gain. */ + MIC_GAIN_PLUS_17DB, /*!< Select 17dB microphone amplifier gain. */ + MIC_GAIN_PLUS_18DB, /*!< Select 18dB microphone amplifier gain. */ + MIC_GAIN_PLUS_19DB, /*!< Select 19dB microphone amplifier gain. */ + MIC_GAIN_PLUS_20DB, /*!< Select 20dB microphone amplifier gain. */ + MIC_GAIN_PLUS_21DB, /*!< Select 21dB microphone amplifier gain. */ + MIC_GAIN_PLUS_22DB, /*!< Select 22dB microphone amplifier gain. */ + MIC_GAIN_PLUS_23DB, /*!< Select 23dB microphone amplifier gain. */ + MIC_GAIN_PLUS_24DB, /*!< Select 24dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_25DB, /*!< Select 25dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_26DB, /*!< Select 26dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_27DB, /*!< Select 27dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_28DB, /*!< Select 28dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_29DB, /*!< Select 29dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_30DB, /*!< Select 30dB microphone amplifier gain + . */ + MIC_GAIN_PLUS_31DB /*!< Select 31dB microphone amplifier gain + . */ +} PMIC_AUDIO_MIC_GAIN; + +/*@}*/ + +/*! + * @name Audio Output Section Typedefs and Enumerations + * Typedefs and enumerations that are used for selecting and setting up + * one or more or audio output ports for playback. + */ +/*@{*/ + +/*! + * @enum PMIC_AUDIO_OUTPUT_PORT + * @brief Select the audio output port. + * + * This enumeration lists all of the available audio output ports. One or + * more may be selected as desired to handle the output audio stream from + * either the Voice CODEC or the Stereo DAC. + */ +typedef enum { + MONO_SPEAKER = 1, /*!< Select mono output speaker. */ + MONO_LOUDSPEAKER = 2, /*!< Select mono loudspeaker + . */ + MONO_ALERT = 4, /*!< Select mono alert output */ + MONO_EXTOUT = 8, /*!< Select mono external output */ + MONO_CDCOUT = 16, /*!< Select dedicated Voice CODEC output + . */ + STEREO_LEFT_LOW_POWER = 32, /*!< Select stereo left channel low power + output . */ + STEREO_HEADSET_LEFT = 64, /*!< Select stereo headset left channel. */ + STEREO_HEADSET_RIGHT = 128, /*!< Select stereo headset right channel. */ + STEREO_OUT_LEFT = 256, /*!< Select stereo external left channel + output . */ + STEREO_OUT_RIGHT = 512 /*!< Select stereo external right channel + output . */ +} PMIC_AUDIO_OUTPUT_PORT; + +/*! + * @enum PMIC_AUDIO_OUTPUT_CONFIG + * @brief Enable/disable the audio output section options. + * + * This enumeration is used to enable/disable any of the audio output section + * options. + */ +typedef enum { + MONO_SPEAKER_INVERT_OUT_ONLY = 1, /*!< Enable/disable the non-inverted + mono speaker output */ + MONO_LOUDSPEAKER_COMMON_BIAS = 2, /*!< Enable/disable the loudspeaker + output amplifier common bias + . */ + HEADSET_DETECT_ENABLE = 4, /*!< Enable/disable headset + insertion/removal detection + . */ + STEREO_HEADSET_AMP_AUTO_DISABLE = 8 /*!< Enable/disable automatic + disabling of the stereo headset + output amplifiers following + headset insertion/removal. */ +} PMIC_AUDIO_OUTPUT_CONFIG; + +/*! + * @enum PMIC_AUDIO_STEREO_IN_GAIN + * @brief Select the amplifier gain for the external stereo inputs. + * + * This enumeration is used to select the amplifier gain level to be used for + * the external stereo inputs. + */ +typedef enum { + STEREO_IN_GAIN_0DB, /*!< Select 0dB external stereo signal + input gain. */ + STEREO_IN_GAIN_PLUS_18DB /*!< Select 18dB external stereo signal + input gain . */ +} PMIC_AUDIO_STEREO_IN_GAIN; + +/*! + * @enum PMIC_AUDIO_OUTPUT_PGA_GAIN + * @brief Select the output PGA amplifier gain level. + * + * This enumeration is used to select the output PGA amplifier gain level. + */ +typedef enum { + OUTPGA_GAIN_MINUS_33DB, /*!< Select -33dB output PGA gain + . */ + OUTPGA_GAIN_MINUS_30DB, /*!< Select -30dB output PGA gain + . */ + OUTPGA_GAIN_MINUS_27DB, /*!< Select -27dB output PGA gain + . */ + OUTPGA_GAIN_MINUS_24DB, /*!< Select -24dB output PGA gain. */ + OUTPGA_GAIN_MINUS_21DB, /*!< Select -21dB output PGA gain. */ + OUTPGA_GAIN_MINUS_18DB, /*!< Select -18dB output PGA gain. */ + OUTPGA_GAIN_MINUS_15DB, /*!< Select -15dB output PGA gain. */ + OUTPGA_GAIN_MINUS_12DB, /*!< Select -12dB output PGA gain. */ + OUTPGA_GAIN_MINUS_9DB, /*!< Select -9dB output PGA gain. */ + OUTPGA_GAIN_MINUS_6DB, /*!< Select -6dB output PGA gain. */ + OUTPGA_GAIN_MINUS_3DB, /*!< Select -3dB output PGA gain. */ + OUTPGA_GAIN_0DB, /*!< Select 0dB output PGA gain. */ + OUTPGA_GAIN_PLUS_3DB, /*!< Select 3dB output PGA gain. */ + OUTPGA_GAIN_PLUS_6DB, /*!< Select 6dB output PGA gain. */ + OUTPGA_GAIN_PLUS_9DB, /*!< Select 9dB output PGA gain. + . */ + OUTPGA_GAIN_PLUS_12DB, /*!< Select 12dB output PGA gain + . */ + OUTPGA_GAIN_PLUS_15DB, /*!< Select 15dB output PGA gain + . */ + OUTPGA_GAIN_PLUS_18DB, /*!< Select 18dB output PGA gain + . */ + OUTPGA_GAIN_PLUS_21DB /*!< Select 21dB output PGA gain + . */ +} PMIC_AUDIO_OUTPUT_PGA_GAIN; + +/*! + * @enum PMIC_AUDIO_OUTPUT_BALANCE_GAIN + * @brief Select the left/right channel balance gain level. + * + * This enumeration is used to select the balance gain level that is to be + * separately applied to the left and right audio channels. + */ +typedef enum { + BAL_GAIN_MINUS_21DB, /*!< Select -21dB channel balance + gain . */ + BAL_GAIN_MINUS_18DB, /*!< Select -18dB channel balance + gain . */ + BAL_GAIN_MINUS_15DB, /*!< Select -15dB channel balance + gain . */ + BAL_GAIN_MINUS_12DB, /*!< Select -12dB channel balance + gain . */ + BAL_GAIN_MINUS_9DB, /*!< Select -9dB channel balance + gain . */ + BAL_GAIN_MINUS_6DB, /*!< Select -6dB channel balance + gain . */ + BAL_GAIN_MINUS_3DB, /*!< Select -3dB channel balance + gain . */ + BAL_GAIN_0DB /*!< Select 0dB channel balance gain. */ +} PMIC_AUDIO_OUTPUT_BALANCE_GAIN; + +/*! + * @enum PMIC_AUDIO_MONO_ADDER_MODE + * @brief Select the output mono adder operating mode. + * + * This enumeration is used to select the operating mode for the mono adder + * in the audio output section. + */ +typedef enum { + MONO_ADDER_OFF, /*!< Disable mono adder (keep separate + left and right channels). */ + MONO_ADD_LEFT_RIGHT, /*!< Add left and right channels. */ + MONO_ADD_OPPOSITE_PHASE, /*!< Add left and right channels but + with outputs in opposite phase + . */ + STEREO_OPPOSITE_PHASE /*!< Keep separate left and right + channels but invert phase of + left channel . */ +} PMIC_AUDIO_MONO_ADDER_MODE; + +/*! + * @enum PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + * @brief Select the mono adder output amplifier gain level. + * + * This enumeration is used to select the output amplifier gain level for + * the mono adder. + */ +typedef enum { + MONOADD_GAIN_MINUS_6DB, /*!< Select -6dB mono adder output gain + . */ + MONOADD_GAIN_MINUS_3DB, /*!< Select -3dB mono adder output gain + . */ + MONOADD_GAIN_0DB /*!< Select 0dB mono adder output gain. */ +} PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN; + +/*@}*/ + +/*************************************************************************** + * PMIC-SPECIFIC DEFINITIONS * + ***************************************************************************/ + +/*! + * @name Definition of PMIC-specific Capabilities + * Constants that are used to define PMIC-specific capabilities. + */ +/*@{*/ + +/*! + * Define the minimum Stereo DAC sampling rate (Hz). + */ +extern const unsigned MIN_STDAC_SAMPLING_RATE_HZ; +/*! + * Define the maximum Stereo DAC sampling rate (Hz). + */ +extern const unsigned MAX_STDAC_SAMPLING_RATE_HZ; + +/*@}*/ + +#define DEBUG_AUDIO + +#ifdef __KERNEL__ + +/*************************************************************************** + * PMIC API DEFINITIONS * + ***************************************************************************/ + +/*! + * @name General Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Audio + * hardware. + */ +/*@{*/ + +/*! + * This function enables the Headset detection mechanism in hardware + */ +PMIC_STATUS pmic_audio_set_autodetect(int val); + +/*! + * @brief Request exclusive access to the PMIC Audio hardware. + * + * Attempt to open and gain exclusive access to a key PMIC audio hardware + * component (e.g., the Stereo DAC or the Voice CODEC). Depending upon the + * type of audio operation that is desired and the nature of the audio data + * stream, the Stereo DAC and/or the Voice CODEC will be a required hardware + * component and needs to be acquired by calling this function. + * + * If the open request is successful, then a numeric handle is returned + * and this handle must be used in all subsequent function calls to complete + * the configuration of either the Stereo DAC or the Voice CODEC and along + * with any other associated audio hardware components that will be needed. + * + * The same handle must also be used in the close call when use of the PMIC + * audio hardware is no longer required. + * + * The open request will fail if the requested audio hardware component has + * already been acquired by a previous open call but not yet closed. + * + * @param[out] handle Device handle to be used for subsequent PMIC + * Connectivity API calls. + * @param[in] device The required PMIC audio hardware component. + * + * @retval PMIC_SUCCESS If the open request was successful + * @retval PMIC_PARAMETER_ERROR If the handle argument is NULL. + * @retval PMIC_ERROR If the audio hardware component is + * unavailable. + */ +PMIC_STATUS pmic_audio_open(PMIC_AUDIO_HANDLE * const handle, + const PMIC_AUDIO_SOURCE device); + +/*! + * @brief Terminate further access to the PMIC audio hardware. + * + * Terminate further access to the PMIC audio hardware that was previously + * acquired by calling pmic_audio_open(). This now allows another thread to + * successfully call pmic_audio_open() to gain access. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the close request was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_close(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Configure the data bus protocol to be used. + * + * Provide the parameters needed to properly configure the audio data bus + * protocol so that data can be read/written to either the Stereo DAC or + * the Voice CODEC. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] busID Select data bus to be used. + * @param[in] protocol Select the data bus protocol. + * @param[in] masterSlave Select the data bus timing mode. + * @param[in] numSlots Define the number of timeslots (only if in + * master mode). + * + * @retval PMIC_SUCCESS If the protocol was successful configured. + * @retval PMIC_PARAMETER_ERROR If the handle or the protocol parameters + * are invalid. + */ +PMIC_STATUS pmic_audio_set_protocol(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_DATA_BUS busID, + const PMIC_AUDIO_BUS_PROTOCOL protocol, + const PMIC_AUDIO_BUS_MODE masterSlave, + const PMIC_AUDIO_NUMSLOTS numSlots); + +/*! + * @brief Retrieve the current data bus protocol configuration. + * + * Retrieve the parameters that define the current audio data bus protocol. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] busID The data bus being used. + * @param[out] protocol The data bus protocol being used. + * @param[out] masterSlave The data bus timing mode being used. + * @param[out] numSlots The number of timeslots being used (if in + * master mode). + * + * @retval PMIC_SUCCESS If the protocol was successful retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_get_protocol(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_DATA_BUS * const busID, + PMIC_AUDIO_BUS_PROTOCOL * const protocol, + PMIC_AUDIO_BUS_MODE * const masterSlave, + PMIC_AUDIO_NUMSLOTS * const numSlots); + +/*! + * @brief Enable the Stereo DAC or the Voice CODEC. + * + * Explicitly enable the Stereo DAC or the Voice CODEC to begin audio + * playback or recording as required. This should only be done after + * successfully configuring all of the associated audio components (e.g., + * microphones, amplifiers, etc.). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the device was successful enabled. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the device could not be enabled. + */ +PMIC_STATUS pmic_audio_enable(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Disable the Stereo DAC or the Voice CODEC. + * + * Explicitly disable the Stereo DAC or the Voice CODEC to end audio + * playback or recording as required. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the device was successful disabled. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the device could not be disabled. + */ +PMIC_STATUS pmic_audio_disable(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Reset the selected audio hardware control registers to their + * power on state. + * + * This resets all of the audio hardware control registers currently + * associated with the device handle back to their power on states. For + * example, if the handle is associated with the Stereo DAC and a + * specific output port and output amplifiers, then this function will + * reset all of those components to their power on state. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +PMIC_STATUS pmic_audio_reset(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Reset all audio hardware control registers to their power on state. + * + * This resets all of the audio hardware control registers back to their + * power on states. Use this function with care since it also invalidates + * (i.e., automatically closes) all currently opened device handles. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +PMIC_STATUS pmic_audio_reset_all(void); + +/*! + * @brief Set the Audio callback function. + * + * Register a callback function that will be used to signal PMIC audio + * events. For example, the OSS audio driver should register a callback + * function in order to be notified of headset connect/disconnect events. + * + * @param[in] func A pointer to the callback function. + * @param[in] eventMask A mask selecting events to be notified. + * @param[in] hs_state To know the headset state. + * + * @retval PMIC_SUCCESS If the callback was successfully + * registered. + * @retval PMIC_PARAMETER_ERROR If the handle or the eventMask is invalid. + */ +PMIC_STATUS pmic_audio_set_callback(void *func, + const PMIC_AUDIO_EVENTS eventMask, + PMIC_HS_STATE *hs_state); + +/*! + * @brief Deregisters the existing audio callback function. + * + * Deregister the callback function that was previously registered by calling + * pmic_audio_set_callback(). + * + * + * @retval PMIC_SUCCESS If the callback was successfully + * deregistered. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_clear_callback(void); + +/*! + * @brief Get the current audio callback function settings. + * + * Get the current callback function and event mask. + * + * @param[out] func The current callback function. + * @param[out] eventMask The current event selection mask. + * + * @retval PMIC_SUCCESS If the callback information was + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_get_callback(PMIC_AUDIO_CALLBACK * const func, + PMIC_AUDIO_EVENTS * const eventMask); + +/*! + * @brief Enable the anti-pop circuitry to avoid extra noise when inserting + * or removing a external device (e.g., a headset). + * + * Enable the use of the built-in anti-pop circuitry to prevent noise from + * being generated when an external audio device is inserted or removed + * from an audio plug. A slow ramp speed may be needed to avoid extra noise. + * + * @param[in] rampSpeed The desired anti-pop circuitry ramp speed. + * + * @retval PMIC_SUCCESS If the anti-pop circuitry was successfully + * enabled. + * @retval PMIC_ERROR If the anti-pop circuitry could not be + * enabled. + */ +PMIC_STATUS pmic_audio_antipop_enable(const PMIC_AUDIO_ANTI_POP_RAMP_SPEED + rampSpeed); + +/*! + * @brief Disable the anti-pop circuitry. + * + * Disable the use of the built-in anti-pop circuitry to prevent noise from + * being generated when an external audio device is inserted or removed + * from an audio plug. + * + * @retval PMIC_SUCCESS If the anti-pop circuitry was successfully + * disabled. + * @retval PMIC_ERROR If the anti-pop circuitry could not be + * disabled. + */ +PMIC_STATUS pmic_audio_antipop_disable(void); + +/*! + * @brief Performs a reset of the Voice CODEC/Stereo DAC digital filter. + * + * This function performs a reset of the digital filter using the back-to-back + * SPI write procedure. + * + * @retval PMIC_SUCCESS If the digital filter was successfully + * reset. + * @retval PMIC_ERROR If the digital filter could not be reset. + */ +PMIC_STATUS pmic_audio_digital_filter_reset(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Get the most recent PTT button voltage reading. + * + * This function returns the most recent reading for the PTT button voltage. + * The value may be used during the processing of the PTT_BUTTON_RANGE event + * as part of the headset ID detection process. + * + * @retval PMIC_SUCCESS If the most recent PTT button voltage was + * returned. + * @retval PMIC_PARAMETER_ERROR If a NULL pointer argument was given. + */ +PMIC_STATUS pmic_audio_get_ptt_button_level(unsigned int *const level); + +#ifdef DEBUG_AUDIO + +/*! + * @brief Provide a hexadecimal dump of all PMIC audio registers (DEBUG only). + * + * This function is intended strictly for debugging purposes only (i.e., + * the DEBUG macro must be defined) and will print the current values of the + * following PMIC registers: + * + * - AUD_CODEC (Voice CODEC state) + * - ST_DAC (Stereo DAC state) + * - RX_AUD_AMPS (audio input section state) + * - TX_AUD_AMPS (audio output section state) + * + * The register fields will also be decoded. + */ +void pmic_audio_dump_registers(void); + +#endif /* DEBUG */ + +/*@}*/ + +/*! + * @name General Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice + * CODEC hardware. + */ +/*@{*/ + +/*! + * @brief Set the Voice CODEC clock source and operating characteristics. + * + * Define the Voice CODEC clock source and operating characteristics. This + * must be done before the Voice CODEC is enabled. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] clockIn Select the clock signal source. + * @param[in] clockFreq Select the clock signal frequency. + * @param[in] samplingRate Select the audio data sampling rate. + * @param[in] invert Enable inversion of the frame sync and/or + * bit clock inputs. + * + * @retval PMIC_SUCCESS If the Voice CODEC clock settings were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or clock configuration was + * invalid. + * @retval PMIC_ERROR If the Voice CODEC clock configuration + * could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_clock(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_CLOCK_IN_SOURCE + clockIn, + const PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ + clockFreq, + const PMIC_AUDIO_VCODEC_SAMPLING_RATE + samplingRate, + const PMIC_AUDIO_CLOCK_INVERT invert); + +/*! + * @brief Get the Voice CODEC clock source and operating characteristics. + * + * Get the current Voice CODEC clock source and operating characteristics. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] clockIn The clock signal source. + * @param[out] clockFreq The clock signal frequency. + * @param[out] samplingRate The audio data sampling rate. + * @param[out] invert Inversion of the frame sync and/or + * bit clock inputs is enabled/disabled. + * + * @retval PMIC_SUCCESS If the Voice CODEC clock settings were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle invalid. + * @retval PMIC_ERROR If the Voice CODEC clock configuration + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_clock(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_CLOCK_IN_SOURCE * + const clockIn, + PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ * + const clockFreq, + PMIC_AUDIO_VCODEC_SAMPLING_RATE * + const samplingRate, + PMIC_AUDIO_CLOCK_INVERT * const invert); + +/*! + * @brief Set the Voice CODEC primary audio channel timeslot. + * + * Set the Voice CODEC primary audio channel timeslot. This function must be + * used if the default timeslot for the primary audio channel is to be changed. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] timeslot Select the primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC primary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC primary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_TIMESLOT + timeslot); + +/*! + * @brief Get the current Voice CODEC primary audio channel timeslot. + * + * Get the current Voice CODEC primary audio channel timeslot. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] timeslot The primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC primary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC primary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_VCODEC_TIMESLOT * + const timeslot); + +/*! + * @brief Set the Voice CODEC secondary recording audio channel timeslot. + * + * Set the Voice CODEC secondary audio channel timeslot. This function must be + * used if the default timeslot for the secondary audio channel is to be + * changed. The secondary audio channel timeslot is used to transmit the audio + * data that was recorded by the Voice CODEC from the secondary audio input + * channel. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] timeslot Select the secondary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC secondary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC secondary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_secondary_txslot(const PMIC_AUDIO_HANDLE + handle, + const + PMIC_AUDIO_VCODEC_TIMESLOT + timeslot); + +/*! + * @brief Get the Voice CODEC secondary recording audio channel timeslot. + * + * Get the Voice CODEC secondary audio channel timeslot. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] timeslot The secondary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC secondary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC secondary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_secondary_txslot(const PMIC_AUDIO_HANDLE + handle, + PMIC_AUDIO_VCODEC_TIMESLOT * + const timeslot); + +/*! + * @brief Set/Enable the Voice CODEC options. + * + * Set or enable various Voice CODEC options. The available options include + * the use of dithering, highpass digital filters, and loopback modes. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The Voice CODEC options to enable. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or Voice CODEC options + * were invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * successfully set/enabled. + */ +PMIC_STATUS pmic_audio_vcodec_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_CONFIG config); + +/*! + * @brief Clear/Disable the Voice CODEC options. + * + * Clear or disable various Voice CODEC options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The Voice CODEC options to be cleared/disabled. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the Voice CODEC options + * were invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * cleared/disabled. + */ +PMIC_STATUS pmic_audio_vcodec_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_CONFIG + config); + +/*! + * @brief Get the current Voice CODEC options. + * + * Get the current Voice CODEC options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current set of Voice CODEC options. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_VCODEC_CONFIG * + const config); + +/*! + * @brief Enable the Voice CODEC bypass audio pathway. + * + * Enables the Voice CODEC bypass pathway for audio data. This allows direct + * output of the voltages on the TX data bus line to the output amplifiers + * (bypassing the digital-to-analog converters within the Voice CODEC). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC bypass was successfully + * enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC bypass could not be + * enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_bypass(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Disable the Voice CODEC bypass audio pathway. + * + * Disables the Voice CODEC bypass pathway for audio data. This means that + * the TX data bus line will deliver digital data to the digital-to-analog + * converters within the Voice CODEC. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC bypass was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC bypass could not be + * disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_bypass(const PMIC_AUDIO_HANDLE handle); + +/*@}*/ + +/*! + * @name General Stereo DAC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Stereo + * DAC hardware. + */ +/*@{*/ + +/*! + * @brief Set the Stereo DAC clock source and operating characteristics. + * + * Define the Stereo DAC clock source and operating characteristics. This + * must be done before the Stereo DAC is enabled. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] clockIn Select the clock signal source. + * @param[in] clockFreq Select the clock signal frequency. + * @param[in] samplingRate Select the audio data sampling rate. + * @param[in] invert Enable inversion of the frame sync and/or + * bit clock inputs. + * + * @retval PMIC_SUCCESS If the Stereo DAC clock settings were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or clock configuration was + * invalid. + * @retval PMIC_ERROR If the Stereo DAC clock configuration + * could not be set. + */ +PMIC_STATUS pmic_audio_stdac_set_clock(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_CLOCK_IN_SOURCE clockIn, + const PMIC_AUDIO_STDAC_CLOCK_IN_FREQ + clockFreq, + const PMIC_AUDIO_STDAC_SAMPLING_RATE + samplingRate, + const PMIC_AUDIO_CLOCK_INVERT invert); + +/*! + * @brief Get the Stereo DAC clock source and operating characteristics. + * + * Get the current Stereo DAC clock source and operating characteristics. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] clockIn The clock signal source. + * @param[out] clockFreq The clock signal frequency. + * @param[out] samplingRate The audio data sampling rate. + * @param[out] invert Inversion of the frame sync and/or + * bit clock inputs is enabled/disabled. + * + * @retval PMIC_SUCCESS If the Stereo DAC clock settings were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle invalid. + * @retval PMIC_ERROR If the Stereo DAC clock configuration + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_clock(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_CLOCK_IN_SOURCE * + const clockIn, + PMIC_AUDIO_STDAC_SAMPLING_RATE * + const samplingRate, + PMIC_AUDIO_STDAC_CLOCK_IN_FREQ * + const clockFreq, + PMIC_AUDIO_CLOCK_INVERT * const invert); + +/*! + * @brief Set the Stereo DAC primary audio channel timeslot. + * + * Set the Stereo DAC primary audio channel timeslot. This function must be + * used if the default timeslot for the primary audio channel is to be changed. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] timeslot Select the primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Stereo DAC primary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Stereo DAC primary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_stdac_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_TIMESLOTS + timeslot); + +/*! + * @brief Get the current Stereo DAC primary audio channel timeslot. + * + * Get the current Stereo DAC primary audio channel timeslot. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] timeslot The primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Stereo DAC primary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC primary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STDAC_TIMESLOTS * + const timeslot); + +/*! + * @brief Set/Enable the Stereo DAC options. + * + * Set or enable various Stereo DAC options. The available options include + * enabling/disabling the bus master clock outputs. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The Stereo DAC options to enable. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or Stereo DAC options + * were invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * successfully set/enabled. + */ +PMIC_STATUS pmic_audio_stdac_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_CONFIG config); + +/*! + * @brief Clear/Disable the Stereo DAC options. + * + * Clear or disable various Stereo DAC options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The Stereo DAC options to be cleared/disabled. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the Stereo DAC options + * were invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * cleared/disabled. + */ +PMIC_STATUS pmic_audio_stdac_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_CONFIG config); + +/*! + * @brief Get the current Stereo DAC options. + * + * Get the current Stereo DAC options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current set of Stereo DAC options. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STDAC_CONFIG * const config); + +/*@}*/ + +/*! + * @name Audio Input Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC audio + * input hardware. + */ +/*@{*/ + +/*! + * @brief Set/Enable the audio input section options. + * + * Set or enable various audio input section options. The only available + * option right now is to enable the automatic disabling of the microphone + * input amplifiers when a microphone/headset is inserted or removed. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The audio input section options to enable. + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio input section + * options were invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be successfully set/enabled. + */ +PMIC_STATUS pmic_audio_input_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_CONFIG config); + +/*! + * @brief Clear/Disable the audio input section options. + * + * Clear or disable various audio input section options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The audio input section options to be + * cleared/disabled. + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the audio input section + * options were invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be cleared/disabled. + */ +PMIC_STATUS pmic_audio_input_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_CONFIG config); + +/*! + * @brief Get the current audio input section options. + * + * Get the current audio input section options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current set of audio input section options. + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be retrieved. + */ +PMIC_STATUS pmic_audio_input_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_CONFIG * const config); + +/*@}*/ + +/*! + * @name Audio Recording Using the Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice CODEC + * to perform audio recording. + */ +/*@{*/ + +/*! + * @brief Select the microphone inputs to be used for Voice CODEC recording. + * + * Select left and right microphone inputs for Voice CODEC + * recording. It is possible to disable or not use a particular microphone + * input channel by specifying NO_MIC as a parameter. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] leftChannel Select the left microphone input channel. + * @param[in] rightChannel Select the right microphone input channel. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input ports + * were invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be successfully enabled. + */ +PMIC_STATUS pmic_audio_vcodec_set_mic(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_PORT leftChannel, + const PMIC_AUDIO_INPUT_PORT rightChannel); + +/*! + * @brief Get the current microphone inputs being used for Voice CODEC + * recording. + * + * Get the left and right microphone inputs currently being + * used for Voice CODEC recording. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] leftChannel The left microphone input channel. + * @param[out] rightChannel The right microphone input channel. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_mic(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_PORT * const leftChannel, + PMIC_AUDIO_INPUT_PORT * + const rightChannel); + +/*! + * @brief Enable/disable the microphone input. + * + * This function enables/disables the current microphone input channel. The + * input amplifier is automatically turned off when the microphone input is + * disabled. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] leftChannel The left microphone input channel state. + * @param[in] rightChannel the right microphone input channel state. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully reconfigured. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input states + * were invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be reconfigured. + */ +PMIC_STATUS pmic_audio_vcodec_set_mic_on_off(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_MIC_STATE + leftChannel, + const PMIC_AUDIO_INPUT_MIC_STATE + rightChannel); + +/*! + * @brief Return the current state of the microphone inputs. + * + * This function returns the current state (on/off) of the microphone + * input channels. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] leftChannel The current left microphone input channel + * state. + * @param[out] rightChannel the current right microphone input channel + * state. + * + * @retval PMIC_SUCCESS If the microphone input channel states + * were successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input channel states + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_mic_on_off(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_MIC_STATE * + const leftChannel, + PMIC_AUDIO_INPUT_MIC_STATE * + const rightChannel); + +/*! + * @brief Set the microphone input amplifier mode and gain level. + * + * This function sets the current microphone input amplifier operating mode + * and gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] leftChannelMode The left microphone input amplifier mode. + * @param[in] leftChannelGain The left microphone input amplifier gain level. + * @param[in] rightChannelMode The right microphone input amplifier mode. + * @param[in] rightChannelGain The right microphone input amplifier gain + * level. + * + * @retval PMIC_SUCCESS If the microphone input amplifiers were + * successfully reconfigured. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input amplifier + * modes or gain levels were invalid. + * @retval PMIC_ERROR If the microphone input amplifiers could + * not be reconfigured. + */ +PMIC_STATUS pmic_audio_vcodec_set_record_gain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_AMP_MODE + leftChannelMode, + const PMIC_AUDIO_MIC_GAIN + leftChannelGain, + const PMIC_AUDIO_MIC_AMP_MODE + rightChannelMode, + const PMIC_AUDIO_MIC_GAIN + rightChannelGain); + +/*! + * @brief Get the current microphone input amplifier mode and gain level. + * + * This function gets the current microphone input amplifier operating mode + * and gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] leftChannelMode The left microphone input amplifier mode. + * @param[out] leftChannelGain The left microphone input amplifier gain level. + * @param[out] rightChannelMode The right microphone input amplifier mode. + * @param[out] rightChannelGain The right microphone input amplifier gain + * level. + * + * @retval PMIC_SUCCESS If the microphone input amplifier modes + * and gain levels were successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input amplifier modes + * and gain levels could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_record_gain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_MIC_AMP_MODE * + const leftChannelMode, + PMIC_AUDIO_MIC_GAIN * + const leftChannelGain, + PMIC_AUDIO_MIC_AMP_MODE * + const rightChannelMode, + PMIC_AUDIO_MIC_GAIN * + const rightChannelGain); + +/*! + * @brief Enable a microphone bias circuit. + * + * This function enables one of the available microphone bias circuits. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] biasCircuit The microphone bias circuit to be enabled. + * + * @retval PMIC_SUCCESS If the microphone bias circuit was + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or selected microphone bias + * circuit was invalid. + * @retval PMIC_ERROR If the microphone bias circuit could not + * be enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_micbias(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_BIAS + biasCircuit); + +/*! + * @brief Disable a microphone bias circuit. + * + * This function disables one of the available microphone bias circuits. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] biasCircuit The microphone bias circuit to be disabled. + * + * @retval PMIC_SUCCESS If the microphone bias circuit was + * successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or selected microphone bias + * circuit was invalid. + * @retval PMIC_ERROR If the microphone bias circuit could not + * be disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_micbias(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_BIAS + biasCircuit); + +/*@}*/ + +/*! + * @name Audio Playback Using the Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice CODEC + * to perform audio playback. + */ +/*@{*/ + +/*! + * @brief Configure and enable the Voice CODEC mixer. + * + * This function configures and enables the Voice CODEC mixer. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] rxSecondaryTimeslot The timeslot used for the secondary audio + * channel. + * @param[in] gainIn The secondary audio channel gain level. + * @param[in] gainOut The mixer output gain level. + * + * @retval PMIC_SUCCESS If the Voice CODEC mixer was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mixer configuration + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC mixer could not be + * reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_mixer(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_TIMESLOT + rxSecondaryTimeslot, + const PMIC_AUDIO_VCODEC_MIX_IN_GAIN + gainIn, + const PMIC_AUDIO_VCODEC_MIX_OUT_GAIN + gainOut); + +/*! + * @brief Disable the Voice CODEC mixer. + * + * This function disables the Voice CODEC mixer. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC mixer was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC mixer could not be + * disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_mixer(const PMIC_AUDIO_HANDLE handle); + +/*@}*/ + +/*! + * @name Audio Playback Using the Stereo DAC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Stereo DAC + * to perform audio playback. + */ +/*@{*/ + +/*! + * @brief Configure and enable the Stereo DAC mixer. + * + * This function configures and enables the Stereo DAC mixer. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] rxSecondaryTimeslot The timeslot used for the secondary audio + * channel. + * @param[in] gainIn The secondary audio channel gain level. + * @param[in] gainOut The mixer output gain level. + * + * @retval PMIC_SUCCESS If the Stereo DAC mixer was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mixer configuration + * was invalid. + * @retval PMIC_ERROR If the Stereo DAC mixer could not be + * reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_stdac_enable_mixer(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_TIMESLOTS + rxSecondaryTimeslot, + const PMIC_AUDIO_STDAC_MIX_IN_GAIN + gainIn, + const PMIC_AUDIO_STDAC_MIX_OUT_GAIN + gainOut); + +/*! + * @brief Disable the Stereo DAC mixer. + * + * This function disables the Stereo DAC mixer. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Stereo DAC mixer was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC mixer could not be + * disabled. + */ +PMIC_STATUS pmic_audio_stdac_disable_mixer(const PMIC_AUDIO_HANDLE handle); + +/*@}*/ + +/*! + * @name Audio Output Section Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC audio output + * section to support playback. + */ +/*@{*/ + +/*! + * @brief Select the audio output ports. + * + * This function selects the audio output ports to be used. This also enables + * the appropriate output amplifiers. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] port The audio output ports to be used. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * acquired. + * @retval PMIC_PARAMETER_ERROR If the handle or output ports were + * invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * acquired. + */ +PMIC_STATUS pmic_audio_output_set_port(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PORT port); + +/*! + * @brief Deselect/disable the audio output ports. + * + * This function disables the audio output ports that were previously enabled + * by calling pmic_audio_output_set_port(). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] port The audio output ports to be disabled. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or output ports were + * invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * disabled. + */ +PMIC_STATUS pmic_audio_output_clear_port(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PORT port); + +/*! + * @brief Get the current audio output ports. + * + * This function retrieves the audio output ports that are currently being + * used. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] port The audio output ports currently being used. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_output_get_port(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_PORT * const port); + +/*! + * @brief Set the gain level for the external stereo inputs. + * + * This function sets the gain levels for the external stereo inputs. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] gain The external stereo input gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the gain level could not be set. + */ +PMIC_STATUS pmic_audio_output_set_stereo_in_gain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STEREO_IN_GAIN + gain); + +/*! + * @brief Get the current gain level for the external stereo inputs. + * + * This function retrieves the current gain levels for the external stereo + * inputs. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] gain The current external stereo input gain + * level. + * + * @retval PMIC_SUCCESS If the gain level was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the gain level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_stereo_in_gain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STEREO_IN_GAIN * + const gain); + +/*! + * @brief Set the output PGA gain level. + * + * This function sets the audio output PGA gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] gain The output PGA gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the gain level could not be set. + */ +PMIC_STATUS pmic_audio_output_set_pgaGain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PGA_GAIN + gain); + +/*! + * @brief Get the output PGA gain level. + * + * This function retrieves the current audio output PGA gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] gain The current output PGA gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the gain level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_pgaGain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_PGA_GAIN * + const gain); + +/*! + * @brief Enable the output mixer. + * + * This function enables the output mixer for the audio stream that + * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or + * the external stereo inputs). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mixer was successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mixer could not be enabled. + */ +PMIC_STATUS pmic_audio_output_enable_mixer(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Disable the output mixer. + * + * This function disables the output mixer for the audio stream that + * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or + * the external stereo inputs). + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mixer was successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mixer could not be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_mixer(const PMIC_AUDIO_HANDLE handle); + +/*! + * @brief Configure and enable the output balance amplifiers. + * + * This function configures and enables the output balance amplifiers. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] leftGain The desired left channel gain level. + * @param[in] rightGain The desired right channel gain level. + * + * @retval PMIC_SUCCESS If the output balance amplifiers were + * successfully configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or gain levels were invalid. + * @retval PMIC_ERROR If the output balance amplifiers could not + * be reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_output_set_balance(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_BALANCE_GAIN + leftGain, + const PMIC_AUDIO_OUTPUT_BALANCE_GAIN + rightGain); + +/*! + * @brief Get the current output balance amplifier gain levels. + * + * This function retrieves the current output balance amplifier gain levels. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] leftGain The current left channel gain level. + * @param[out] rightGain The current right channel gain level. + * + * @retval PMIC_SUCCESS If the output balance amplifier gain levels + * were successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the output balance amplifier gain levels + * could be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_balance(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_BALANCE_GAIN * + const leftGain, + PMIC_AUDIO_OUTPUT_BALANCE_GAIN * + const rightGain); + +/*! + * @brief Configure and enable the output mono adder. + * + * This function configures and enables the output mono adder. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] mode The desired mono adder operating mode. + * + * @retval PMIC_SUCCESS If the mono adder was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mono adder mode was + * invalid. + * @retval PMIC_ERROR If the mono adder could not be reconfigured + * or enabled. + */ +PMIC_STATUS pmic_audio_output_enable_mono_adder(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MONO_ADDER_MODE + mode); + +/*! + * @brief Disable the output mono adder. + * + * This function disables the output mono adder. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mono adder was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mono adder could not be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_mono_adder(const PMIC_AUDIO_HANDLE + handle); + +/*! + * @brief Configure the mono adder output gain level. + * + * This function configures the mono adder output amplifier gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] gain The desired output gain level. + * + * @retval PMIC_SUCCESS If the mono adder output amplifier gain + * level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the mono adder output amplifier gain + * level could not be reconfigured. + */ +PMIC_STATUS pmic_audio_output_set_mono_adder_gain(const PMIC_AUDIO_HANDLE + handle, + const + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + gain); + +/*! + * @brief Get the current mono adder output gain level. + * + * This function retrieves the current mono adder output amplifier gain level. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] gain The current output gain level. + * + * @retval PMIC_SUCCESS If the mono adder output amplifier gain + * level was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mono adder output amplifier gain + * level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_mono_adder_gain(const PMIC_AUDIO_HANDLE + handle, + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + * const gain); + +/*! + * @brief Set various audio output section options. + * + * This function sets one or more audio output section configuration + * options. The currently supported options include whether to disable + * the non-inverting mono speaker output, enabling the loudspeaker common + * bias circuit, enabling detection of headset insertion/removal, and + * whether to automatically disable the headset amplifiers when a headset + * insertion/removal has been detected. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The desired audio output section + * configuration options to be set. + * + * @retval PMIC_SUCCESS If the desired configuration options were + * all successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or configuration options + * were invalid. + * @retval PMIC_ERROR If the desired configuration options + * could not be set. + */ +PMIC_STATUS pmic_audio_output_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_CONFIG config); + +/*! + * @brief Clear various audio output section options. + * + * This function clears one or more audio output section configuration + * options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[in] config The desired audio output section + * configuration options to be cleared. + * + * @retval PMIC_SUCCESS If the desired configuration options were + * all successfully cleared. + * @retval PMIC_PARAMETER_ERROR If the handle or configuration options + * were invalid. + * @retval PMIC_ERROR If the desired configuration options + * could not be cleared. + */ +PMIC_STATUS pmic_audio_output_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_CONFIG + config); + +/*! + * @brief Get the current audio output section options. + * + * This function retrieves the current audio output section configuration + * option settings. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current audio output section + * configuration option settings. + * + * @retval PMIC_SUCCESS If the current configuration options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the current configuration options + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_CONFIG * + const config); + +/*! + * @brief Enable the phantom ground circuit that is used to help identify + * the type of headset that has been inserted. + * + * This function enables the phantom ground circuit that is used to help + * identify the type of headset (e.g., stereo or mono) that has been inserted. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the phantom ground circuit was + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the phantom ground circuit could not + * be enabled. + */ +PMIC_STATUS pmic_audio_output_enable_phantom_ground(void); + +/*! + * @brief Disable the phantom ground circuit that is used to help identify + * the type of headset that has been inserted. + * + * This function disables the phantom ground circuit that is used to help + * identify the type of headset (e.g., stereo or mono) that has been inserted. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the phantom ground circuit was + * successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the phantom ground circuit could not + * be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_phantom_ground(void); + +/*! + * @brief Enable/Disable fm output + * + * This function enables/disables the fm output. + * + * @param[in] enable True to enable and false to disable + * + * @retval PMIC_SUCCESS If the fm output was + * successfully enable or disabled + * @retval PMIC_ERROR If the operation fails + */ +PMIC_STATUS pmic_audio_fm_output_enable(bool enable); + +/*@}*/ + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_PMIC_AUDIO_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/pmic_convity.h b/arch/arm/plat-mxc/include/mach/pmic_convity.h new file mode 100644 index 000000000000..62b019112839 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pmic_convity.h @@ -0,0 +1,873 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_CONVITY_H__ +#define __ASM_ARCH_MXC_PMIC_CONVITY_H__ + +/*! + * @defgroup PMIC_CONNECTIVITY PMIC Connectivity Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_convity.h + * @brief External definitions for the PMIC Connectivity Client driver. + * + * The PMIC Connectivity driver and this API were developed to support the + * external connectivity capabilities of several power management ICs that + * are available from Freescale Semiconductor, Inc. + * + * The following operating modes, in terms of external connectivity, are + * supported: + * + * + * + * @ingroup PMIC_CONNECTIVITY + */ + +#include +#include + +/*************************************************************************** + * TYPEDEFS AND ENUMERATIONS * + ***************************************************************************/ + +/*! + * @name General Setup and Configuration Typedefs and Enumerations + * Typedefs and enumerations that are used for initial access to and + * configuration of the PMIC Connectivity hardware. + */ +/*@{*/ + +#define DEBUG_CONVITY + +/*! + * @typedef PMIC_CONVITY_HANDLE + * @brief Define typedef for a handle to the PMIC Connectivity hardware. + * + * Define a "handle" that is returned when the PMIC Connectivity hardware + * is opened. This handle grants exclusive access to the PMIC Connectivity + * hardware and must be used in all subsequent function calls. When access + * to the PMIC Connectivity hardware is no longer required, then a close + * operation must be done with this handle. The handle is no longer valid + * if the close operation was successful. + */ +typedef long PMIC_CONVITY_HANDLE; + +/*! + * @enum PMIC_CONVITY_MODE + * @brief Select the main Connectivity operating mode. + * + * Defines all possible PMIC Connectivity main operating modes. Only one of + * these modes can be active at a time. + */ +typedef enum { + USB, /*!< Select USB mode (this is also the Reset/Default + mode). */ + RS232, /*!< Select RS-232 mode. for SC55112 */ + RS232_1, /*!< Select RS-232_1 mode. */ + RS232_2, /*!< Select RS-232_2 mode. */ + CEA936_MONO, /*!< Select CE-936 Mono mode . */ + CEA936_STEREO, /*!< Select CE-936 Stereo mode . */ + CEA936_TEST_RIGHT, /*!< Select CE-936 Right Channel Test mode + . */ + CEA936_TEST_LEFT /*!< Select CE-936 Left Channel Test mode + . */ +} PMIC_CONVITY_MODE; + +/*! + * @enum PMIC_CONVITY_EVENTS + * @brief Identify the connectivity events that have been detected and should + * be handled. + * + * Defines all possible PMIC Connectivity events. Multiple events may be + * selected when defining a mask. + */ +typedef enum { + USB_DETECT_4V4_RISE = 1, /*!< Detected 4.4V rising edge. */ + USB_DETECT_4V4_FALL = 2, /*!< Detected 4.4V falling edge. */ + USB_DETECT_2V0_RISE = 4, /*!< Detected 2.0V rising edge. */ + USB_DETECT_2V0_FALL = 8, /*!< Detected 2.0V falling edge. */ + USB_DETECT_0V8_RISE = 16, /*!< Detected 0.8V rising edge. */ + USB_DETECT_0V8_FALL = 32, /*!< Detected 0.8V falling edge. */ + USB_DETECT_MINI_A = 64, /*!< Detected USB mini A plug. */ + USB_DETECT_MINI_B = 128, /*!< Detected USB mini B plug. */ + USB_DETECT_NON_USB_ACCESSORY = 256, /*!< Detected a non-USB connection + . */ + USB_DETECT_FACTORY_MODE = 512, /*!< Detected a factory-mode + connection . */ + USB_DP_HI = 1024, + + USB_DM_HI = 2048 +} PMIC_CONVITY_EVENTS; + +/*! + * @typedef PMIC_CONVITY_CALLBACK + * @brief Typedef for PMIC Connectivity event notification callback function. + * + * Define a typedef for the PMIC Connectivity event notification callback + * function. The signalled events are passed to the function as the first + * argument. The callback function should then process whatever events it + * can and then return the set of unhandled events (if any). + */ +typedef void (*PMIC_CONVITY_CALLBACK) (const PMIC_CONVITY_EVENTS event); + +/*@}*/ + +/*! + * @name USB and USB On-The-Go Mode-specific Typedefs and Enumerations + * Typedefs and enumerations that are used only for setting up and controlling + * the USB and USB On-The-Go modes of operation. + */ +/*@{*/ + +/*! + * @enum PMIC_CONVITY_USB_DEVICE_TYPE + * @brief Select the USB device type (either A or B). + * + * Defines all possible USB device types. This must match the physical + * connector being used. + */ +typedef enum { + USB_A_DEVICE, + USB_B_DEVICE +} PMIC_CONVITY_USB_DEVICE_TYPE; + +/*! + * @enum PMIC_CONVITY_USB_SPEED + * @brief Select the USB transceiver operating speed. + * + * Defines all possible USB transceiver operating speeds. Only one + * speed setting may be used at a time. + */ +typedef enum { + USB_LOW_SPEED, /*!< Select 1.5 Mbps. */ + USB_FULL_SPEED, /*!< Select 12 Mbps. */ + USB_HIGH_SPEED /*!< Select 480 Mbps (currently + not supported). */ +} PMIC_CONVITY_USB_SPEED; + +/*! + * @enum PMIC_CONVITY_USB_MODE + * @brief Select the USB transceiver operating mode. + * + * Defines all possible USB transceiver operating modes. Only one + * mode may be used at a time. The selected mode, in combination with + * the USB bus speed, determines the selection of pull-up and pull-down + * resistors. + */ +typedef enum { + USB_HOST, + USB_PERIPHERAL +} PMIC_CONVITY_USB_MODE; + +/*! + * @enum PMIC_CONVITY_USB_POWER_IN + * @brief Select the USB transceiver's power regulator input source. + * + * Defines all possible input power sources for the USB transceiver power + * regulator. Only one power supply source may be selected at a time. + */ +typedef enum { + + USB_POWER_INTERNAL_BOOST, /*!< Select internal power source + with boost. */ + + USB_POWER_VBUS, /*!< Select VBUS power source. */ + + USB_POWER_INTERNAL /*!< Select internal power source + . */ +} PMIC_CONVITY_USB_POWER_IN; + +/*! + * @enum PMIC_CONVITY_USB_POWER_OUT + * @brief Select the USB transceiver power regulator output voltage. + * + * Defines all possible output voltages for the USB transceiver power + * regulator. Only one power output voltage level may be selected at + * a time. + */ +typedef enum { + USB_POWER_2V775, /*!< Select 2.775V output voltage + . */ + USB_POWER_3V3 /*!< Select 3.3V output voltage. */ +} PMIC_CONVITY_USB_POWER_OUT; + +/*! + * @enum PMIC_CONVITY_USB_TRANSCEIVER_MODE + * @brief Select the USB transceiver operating mode. + * + * Defines all valid USB transceiver operating modes. Only one of the + * following USB transceiver modes may be selected at a time. + */ +typedef enum { + USB_TRANSCEIVER_OFF, /*!< USB transceiver currently off + . */ + USB_SINGLE_ENDED_UNIDIR, /*!< Select Single-ended + unidirectional transmit mode. */ + USB_SINGLE_ENDED_UNIDIR_TX, /*!< Select Single-ended + unidirectional transmit mode. */ + USB_SINGLE_ENDED_UNIDIR_RX, /*!< Select Single-ended + unidirectional receive mode. */ + USB_SINGLE_ENDED_BIDIR, /*!< Select Single-ended + bidirectional transmit mode. */ + USB_SINGLE_ENDED_LOW, /*!< Select USB SE0 mode. */ + USB_DIFFERENTIAL_UNIDIR_TX, /*!< Select Differential + unidirectional transmit mode + . */ + USB_DIFFERENTIAL_UNIDIR, /*!< Select Differential + unidirectional transmit mode + . */ + + USB_DIFFERENTIAL_UNIDIR_RX, /*!< Select Differential + unidirectional receive mode. */ + USB_DIFFERENTIAL_BIDIR, /*!< Select Differential + bidirectional transmit mode + */ + USB_SUSPEND_ON, /*!< Select Suspend mode. */ + USB_SUSPEND_OFF, /*!< Terminate Suspend mode. */ + USB_OTG_SRP_DLP_START, /*!< Start USB On-The-Go Session + Request Protocol using Data + Line Pulsing. */ + USB_OTG_SRP_DLP_STOP /*!< Terminate USB On-The-Go Session + Request Protocol using Data + Line Pulsing. */ +} PMIC_CONVITY_USB_TRANSCEIVER_MODE; + +/*! + * @enum PMIC_CONVITY_USB_OTG_CONFIG + * @brief Select the USB On-The-Go configuration options. + * + * Defines all possible USB On-The-Go configuration options. Multiple + * configuration options may be selected at the same time. However, only one + * VBUS current limit may be selected at a time. Selecting more than one + * VBUS current limit will result in undefined and implementation-dependent + * behavior. + */ +typedef enum { + USB_OTG_SE0CONN = 0x00001, /*!< Enable automatic + connection of a pull-up + resistor to VUSB when the + SE0 condition is detected. */ + USB_OTG_DLP_SRP = 0x00002, /*!< Enable use of the hardware + timer to control the + duration of the data line + pulse during the session + request protocol. */ + USB_PULL_OVERRIDE = 0x00004, /*!< Enable automatic disconnect + of pull-up and pull-down + resistors when transmitter + is enabled. */ + + USB_DP150K_PU = 0x00008, + + USB_VBUS_CURRENT_LIMIT_HIGH = 0x00010, /*!< Select current limit to 200mA + for VBUS regulator. */ + USB_VBUS_CURRENT_LIMIT_LOW = 0x00020, /*!< Select low current limit + for VBUS regulator. */ + USB_VBUS_CURRENT_LIMIT_LOW_10MS = 0x00040, /*!< Select low current limit + for VBUS regulator for + 10 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_20MS = 0x00080, /*!< Select low current limit + for VBUS regulator for + 20 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_30MS = 0x00100, /*!< Select low current limit + for VBUS regulator for + 30 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_40MS = 0x00200, /*!< Select low current limit + for VBUS regulator for + 40 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_50MS = 0x00400, /*!< Select low current limit + for VBUS regulator for + 50 ms . */ + USB_VBUS_CURRENT_LIMIT_LOW_60MS = 0x00800, /*!< Select low current limit + for VBUS regulator for + 60 ms . */ + + USB_VBUS_PULLDOWN = 0x01000, /*!< Enable VBUS pull-down. */ + + USB_USBCNTRL = 0x02000, + + USB_UDP_PD = 0x04000, + + USB_UDM_PD = 0x08000, + + USB_PU = 0x10000, + + USBXCVREN = 0x20000 +} PMIC_CONVITY_USB_OTG_CONFIG; +/*@}*/ + +/*! + * @name RS-232 Mode-specific Typedefs and Enumerations + * Typedefs and enumerations that are used only for setting up and controlling + * the RS-232 mode of operation. + */ +/*@{*/ + +/*! + * @enum PMIC_CONVITY_RS232_EXTERNAL + * @brief Select the RS-232 transceiver external connections. + * + * Defines all valid RS-232 transceiver external RX/TX connection options. + * Only one connection mode may be selected at a time. + */ +typedef enum { + RS232_TX_UDM_RX_UDP, /*!< Select RS-232 TX on UDM */ + RS232_TX_UDP_RX_UDM, /*!< Select RS-232 TX on UDP + . */ + RS232_TX_RX_EXTERNAL_DEFAULT /*!< Use power on default. */ +} PMIC_CONVITY_RS232_EXTERNAL; + +/*! + * @enum PMIC_CONVITY_RS232_INTERNAL + * @brief Select the RS-232 transceiver internal connections. + * + * Defines all valid RS-232 transceiver internal RX/TX connection options. + * Only one connection mode can be selected at a time. + */ +typedef enum { + RS232_TX_USE0VM_RX_UDATVP, /*!< Select RS-232 TX from USE0VM + . */ + RS232_TX_UDATVP_RX_URXVM, /*!< Select RS-232 TX from UDATVP + . */ + RS232_TX_UTXDI_RX_URXDO, /*!< Select RS-232 TX from UTXDI + . */ + RS232_TX_RX_INTERNAL_DEFAULT /*!< Use power on default. */ +} PMIC_CONVITY_RS232_INTERNAL; + +/*@}*/ + +/*! + * @name CEA-936 Mode-specific Typedefs and Enumerations + * Typedefs and enumerations that are used only for setting up and controlling + * the CEA-936 mode of operation. + */ +/*@{*/ + +/*! + * @enum PMIC_CONVITY_CEA936_EXIT_SIGNAL + * @brief Select the CEA-936 mode exit signal. + * + * Defines all valid CEA-936 connection termination signals. Only one + * termination signal can be selected at a time. + */ +typedef enum { + CEA936_UID_NO_PULLDOWN, /*!< No UID pull-down . */ + CEA936_UID_PULLDOWN_6MS, /*!< UID pull-down for 6 ms (+/-2 ms) + . */ + CEA936_UID_PULLDOWN, /*!< UID pulled down . */ + CEA936_UDMPULSE /*!< UDM pulsed . */ +} PMIC_CONVITY_CEA936_EXIT_SIGNAL; + +/*@}*/ + +/*************************************************************************** + * PMIC API DEFINITIONS * + ***************************************************************************/ + +/*! + * @name General Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Connectivity + * hardware. + */ +/*@{*/ + +/*! + * @brief Request exclusive access to the PMIC Connectivity hardware. + * + * Attempt to open and gain exclusive access to the PMIC Connectivity + * hardware. An initial operating mode (e.g., USB or RS-232) must also + * be specified. + * + * If the open request is successful, then a numeric handle is returned + * and this handle must be used in all subsequent function calls. The + * same handle must also be used in the close call when use of the PMIC + * connectivity hardware is no longer required. + * + * The open request will fail if another thread has already obtained the + * device handle and has not yet called pmic_convity_close() with it. + * + * @param handle Device handle to be used for subsequent PMIC + * Connectivity API calls. + * @param mode Initial connectivity operating mode. + * + * @retval PMIC_SUCCESS If the open request was successful + * @retval PMIC_ERROR If the connectivity hardware cannot be opened. + */ +PMIC_STATUS pmic_convity_open(PMIC_CONVITY_HANDLE * const handle, + const PMIC_CONVITY_MODE mode); + +/*! + * @brief Terminate further access to the PMIC Connectivity hardware. + * + * Terminate further access to the PMIC Connectivity hardware. This also + * allows another thread to successfully call pmic_convity_open() to gain + * access. + * + * @param handle Device handle from open() call. + * + * @retval PMIC_SUCCESS If the close request was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_close(const PMIC_CONVITY_HANDLE handle); + +/*! + * @brief Set the PMIC Connectivity main operating mode. + * + * Change the current operating mode of the PMIC Connectivity hardware. + * The available connectivity operating modes are hardware-dependent and + * consists of one or more of the following: USB (including USB On-the-Go), + * RS-232, and CEA-936. Requesting an operating mode that is not supported + * by the PMIC hardware will return PMIC_NOT_SUPPORTED. + * + * @param handle Device handle from open() call. + * @param mode Desired operating mode. + * + * @retval PMIC_SUCCESS If the requested mode was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the PMIC hardware does not support + * the desired operating mode. + */ +PMIC_STATUS pmic_convity_set_mode(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_MODE mode); + +/*! + * @brief Get the current PMIC Connectivity main operating mode. + * + * Get the current operating mode for the PMIC Connectivity hardware. + * + * @param handle Device handle from open() call. + * @param mode The current PMIC Connectivity operating mode. + * + * @retval PMIC_SUCCESS If the requested mode was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_get_mode(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_MODE * const mode); + +/*! + * @brief Reset the Connectivity hardware to it's power on state. + * + * Restore all registers to the initial power-on/reset state. + * + * @param handle Device handle from open() call. + * + * @retval PMIC_SUCCESS If the reset was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_reset(const PMIC_CONVITY_HANDLE handle); + +/*! + * @brief Set the Connectivity callback function. + * + * Register a callback function that will be used to signal PMIC Connectivity + * events. For example, the USB subsystem should register a callback function + * in order to be notified of device connect/disconnect events. Note, however, + * that non-USB events may also be signalled depending upon the PMIC hardware + * capabilities. Therefore, the callback function must be able to properly + * handle all of the possible events if support for non-USB peripherals is + * also to be included. + * + * @param handle Device handle from open() call. + * @param func A pointer to the callback function. + * @param eventMask A mask selecting events to be notified. + * + * @retval PMIC_SUCCESS If the callback was successfully registered. + * @retval PMIC_PARAMETER_ERROR If the handle or the eventMask is invalid. + */ +PMIC_STATUS pmic_convity_set_callback(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_CALLBACK func, + const PMIC_CONVITY_EVENTS eventMask); + +/*! + * @brief Deregisters the existing Connectivity callback function. + * + * Deregister the callback function that was previously registered by calling + * pmic_convity_set_callback(). + * + * @param handle Device handle from open() call. + * + * @retval PMIC_SUCCESS If the callback was successfully deregistered. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_clear_callback(const PMIC_CONVITY_HANDLE handle); + +/*! + * @brief Get the current Connectivity callback function settings. + * + * Get the current callback function and event mask. + * + * @param handle Device handle from open() call. + * @param func The current callback function. + * @param eventMask The current event selection mask. + * + * @retval PMIC_SUCCESS If the callback information was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_get_callback(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_CALLBACK * const func, + PMIC_CONVITY_EVENTS * const eventMask); + +/*@}*/ + +/***************************************************************************/ + +/*! + * @name USB and USB On-The-Go APIs + * USB Connectivity mode-specific configuration and setup functions. + */ +/*@{*/ + +/*! + * @brief Set the USB transceiver's operating speed. + * + * Set the USB transceiver speed. + * + * @param handle Device handle from open() call. + * @param speed The desired USB transceiver speed. + * + * @retval PMIC_SUCCESS If the transceiver speed was successfully + * set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the high speed (480 Mbps) mode is + * requested. + */ +PMIC_STATUS pmic_convity_usb_set_speed(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_SPEED speed); + +/*! + * This function enables/disables VUSB and VBUS output. + * This API configures the VUSBEN and VBUSEN bits of USB register + * + * @param handle Device handle from open() call. + * @param out_type true, for VUSB + * false, for VBUS + * @param out if true, output is enabled + * if false, output is disabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ + +PMIC_STATUS pmic_convity_set_output(const PMIC_CONVITY_HANDLE handle, + bool out_type, bool out); + +/*! + * @brief Get the USB transceiver's operating speed. + * + * Get the USB transceiver speed. + * + * @param handle Device handle from open() call. + * @param speed The current USB transceiver speed. + * @param mode The current USB transceiver mode. + * + * @retval PMIC_SUCCESS If the transceiver speed was successfully + * set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * obtained + */ +PMIC_STATUS pmic_convity_usb_get_speed(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_SPEED * const speed, + PMIC_CONVITY_USB_MODE * const mode); + +/*! + * @brief Set the USB transceiver's power supply configuration. + * + * Set the USB transceiver's power supply configuration. + * + * @param handle Device handle from open() call. + * @param pwrin USB transceiver regulator input power source. + * @param pwrout USB transceiver regulator output power level. + * + * @retval PMIC_SUCCESS If the USB transceiver's power supply + * configuration was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the PMIC hardware does not support + * the desired configuration. + */ +PMIC_STATUS pmic_convity_usb_set_power_source(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_POWER_IN + pwrin, + const PMIC_CONVITY_USB_POWER_OUT + pwrout); + +/*! + * @brief Get the USB transceiver's power supply configuration. + * + * Get the USB transceiver's current power supply configuration. + * + * @param handle Device handle from open() call. + * @param pwrin USB transceiver regulator input power source + * @param pwrout USB transceiver regulator output power level + * + * @retval PMIC_SUCCESS If the USB transceiver's power supply + * configuration was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_usb_get_power_source(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_POWER_IN * + const pwrin, + PMIC_CONVITY_USB_POWER_OUT * + const pwrout); + +/*! + * @brief Set the current USB transceiver operating mode. + * + * Set the USB transceiver's operating mode. + * + * @param handle Device handle from open() call. + * @param mode Desired operating mode. + * + * @retval PMIC_SUCCESS If the USB transceiver's operating mode + * was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired USB transceiver mode is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_set_xcvr(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_TRANSCEIVER_MODE + mode); + +/*! + * @brief Get the current USB transceiver operating mode. + * + * Get the USB transceiver's current operating mode. + * + * @param handle Device handle from open() call. + * @param mode Current operating mode. + * + * @retval PMIC_SUCCESS If the USB transceiver's operating mode + * was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_usb_get_xcvr(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_TRANSCEIVER_MODE * + const mode); + +/*! + * @brief Set the current USB On-The-Go data line pulse duration (ms). + * + * Set the Data Line Pulse duration (in milliseconds) for the USB OTG + * Session Request Protocol. + * + * Note that for mc13783 the duration is fixed at 7.5 ms and calling this + * function will simply return PMIC_NOT_SUPPORTED. + * + * @param handle Device handle from open() call. + * @param duration The data line pulse duration (ms). + * + * @retval PMIC_SUCCESS If the pulse duration was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or the data line pulse + * duration is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired data line pulse duration + * is not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_otg_set_dlp_duration(const PMIC_CONVITY_HANDLE + handle, + const unsigned int duration); + +/*! + * @brief Get the current USB On-The-Go data line pulse duration (ms). + * + * Get the current Data Line Pulse duration (in milliseconds) for the USB + * OTG Session Request Protocol. + * + * Note that the Data Line Pulse duration is fixed at 7.5 ms for the mc13783 + * PMIC. Therefore, calling this function while using the mc13783 PMIC will + * simply return PMIC_NOT_SUPPORTED. + * + * @param handle Device handle from open() call. + * @param duration The data line pulse duration (ms). + * + * @retval PMIC_SUCCESS If the pulse duration was successfully + * obtained. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If called using the mc13783 PMIC. + */ +PMIC_STATUS pmic_convity_usb_otg_get_dlp_duration(const PMIC_CONVITY_HANDLE + handle, + unsigned int *const duration); + +/*! + * @brief Start the USB OTG Host Negotiation Protocol (HNP) process. + * + * This function must be called during the start of the HNP process to + * properly reconfigure the pull-up resistor on the D+ line for both + * the USB A and B devices. + * + * @param handle device handle from open() call + * @param deviceType the USB device type (either A or B) + * + * @return PMIC_SUCCESS if the HNP was successfully started + */ +PMIC_STATUS pmic_convity_usb_otg_begin_hnp(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_DEVICE_TYPE + deviceType); + +/*! + * @brief Complete the USB OTG Host Negotiation Protocol (HNP) process. + * + * This function must be called during the end of the HNP process to + * properly reconfigure the pull-up resistor on the D+ line for both + * the USB A and B devices. + * + * @param handle device handle from open() call + * @param deviceType the USB device type (either A or B) + * + * @return PMIC_SUCCESS if the HNP was successfully ended + */ +PMIC_STATUS pmic_convity_usb_otg_end_hnp(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_DEVICE_TYPE + deviceType); + +/*! + * @brief Set the current USB On-The-Go configuration. + * + * Set the USB On-The-Go (OTG) configuration. Multiple configuration settings + * may be OR'd together in a single call. However, selecting conflicting + * settings (e.g., multiple VBUS current limits) will result in undefined + * behavior. + * + * @param handle Device handle from open() call. + * @param cfg Desired USB OTG configuration. + * + * @retval PMIC_SUCCESS If the OTG configuration was successfully + * set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired USB OTG configuration is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_otg_set_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_OTG_CONFIG + cfg); + +/*! + * @brief Clear the current USB On-The-Go configuration. + * + * Clears the USB On-The-Go (OTG) configuration. Multiple configuration settings + * may be OR'd together in a single call. However, selecting conflicting + * settings (e.g., multiple VBUS current limits) will result in undefined + * behavior. + * + * @param handle Device handle from open() call. + * @param cfg USB OTG configuration settings to be cleared. + * + * @retval PMIC_SUCCESS If the OTG configuration was successfully + * cleared. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired USB OTG configuration is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_otg_clear_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_OTG_CONFIG + cfg); + +/*! + * @brief Get the current USB On-The-Go configuration. + * + * Get the current USB On-The-Go (OTG) configuration. + * + * @param handle Device handle from open() call. + * @param cfg The current USB OTG configuration. + * + * @retval PMIC_SUCCESS If the OTG configuration was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_usb_otg_get_config(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_OTG_CONFIG * + const cfg); + +/*@}*/ + +/***************************************************************************/ + +/*! + * @name RS-232 APIs + * RS-232 Connectivity mode-specific configuration and setup functions. + */ +/*@{*/ + +/*! + * @brief Set the current RS-232 operating configuration. + * + * Set the connectivity interface to the selected RS-232 operating mode. + * Note that the RS-232 operating mode will be automatically overridden + * if the USB_EN is asserted at any time (e.g., when a USB device is + * attached). + * + * @param handle Device handle from open() call. + * @param cfgInternal RS-232 transceiver internal connections. + * @param cfgExternal RS-232 transceiver external connections. + * + * @retval PMIC_SUCCESS If the requested RS-232 mode was set. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired RS-232 configuration is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_rs232_set_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_RS232_INTERNAL + cfgInternal, + const PMIC_CONVITY_RS232_EXTERNAL + cfgExternal); + +/*! + * @brief Get the current RS-232 operating configuration. + * + * Get the connectivity interface's current RS-232 operating mode. + * + * @param handle Device handle from open() call. + * @param cfgInternal RS-232 transceiver internal connections. + * @param cfgExternal RS-232 transceiver external connections. + * + * @retval PMIC_SUCCESS If the requested RS-232 mode was retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_convity_rs232_get_config(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_RS232_INTERNAL * + const cfgInternal, + PMIC_CONVITY_RS232_EXTERNAL * + const cfgExternal); + +/***************************************************************************/ + +/*@}*/ + +/*! + * @name CE-936 APIs + * CE-936 Connectivity mode-specific configuration and setup functions. + */ +/*@{*/ + +/*! + * @brief Send a signal to exit CEA-936 mode. + * + * Signal the attached device to exit the current CEA-936 operating mode. + * Returns an error if the current operating mode is not CEA-936. + * + * @param handle Device handle from open() call. + * @param signal Type of exit signal to be sent. + * + * @retval PMIC_SUCCESS If the CEA-936 exit mode signal was sent. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired CEA-936 exit mode signal + * is not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_cea936_exit_signal(const PMIC_CONVITY_HANDLE handle, + const + PMIC_CONVITY_CEA936_EXIT_SIGNAL + signal); + +/*@}*/ + +#endif /* __ASM_ARCH_MXC_PMIC_CONVITY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/pmic_power.h b/arch/arm/plat-mxc/include/mach/pmic_power.h new file mode 100644 index 000000000000..68b8e74e3565 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/pmic_power.h @@ -0,0 +1,1358 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_POWER_H__ +#define __ASM_ARCH_MXC_PMIC_POWER_H__ + +/*! + * @defgroup PMIC_POWER PMIC Power Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_power.h + * @brief This is the header of PMIC power driver. + * + * @ingroup PMIC_POWER + */ + +#include +#include +#include + +/*! + * @name IOCTL user space interface + */ +/*! @{ */ + +/*! + * Turn on a regulator. + */ +#define PMIC_REGULATOR_ON _IOWR('p', 0xf0, int) + +/*! + * Turn off a regulator. + */ +#define PMIC_REGULATOR_OFF _IOWR('p', 0xf1, int) + +/*! + * Set regulator configuration. + */ +#define PMIC_REGULATOR_SET_CONFIG _IOWR('p', 0xf2, int) + +/*! + * Get regulator configuration. + */ +#define PMIC_REGULATOR_GET_CONFIG _IOWR('p', 0xf3, int) + +/*! + * Miscellaneous Power Test. + */ +#define PMIC_POWER_CHECK_MISC _IOWR('p', 0xf4, int) + +/*! @} */ + +/*! + * This enumeration define all power interrupts + */ +typedef enum { + /*! + * BP turn on threshold detection + */ + PWR_IT_BPONI = 0, + /*! + * End of life / low battery detect + */ + PWR_IT_LOBATLI, + /*! + * Low battery warning + */ + PWR_IT_LOBATHI, + /*! + * ON1B event + */ + PWR_IT_ONOFD1I, + /*! + * ON2B event + */ + PWR_IT_ONOFD2I, + /*! + * ON3B event + */ + PWR_IT_ONOFD3I, + /*! + * System reset + */ + PWR_IT_SYSRSTI, + /*! + * Power ready + */ + PWR_IT_PWRRDYI, + /*! + * Power cut event + */ + PWR_IT_PCI, + /*! + * Warm start event + */ + PWR_IT_WARMI, + /*! + * Memory hold event + */ +} t_pwr_int; + +/*! + * VHOLD regulator output voltage setting. + */ +typedef enum { + VH_1_875V, /*!< 1.875V */ + VH_2_5V, /*!< 2.5V */ + VH_1_55V, /*!< 1.55V */ + VH_PASSTHROUGH, /*!< Pass-through mode */ +} t_vhold_voltage; + +/*! + * PMIC power control configuration. + */ + +typedef struct { + bool pc_enable; /*!< Power cut enable */ + unsigned char pc_timer; /*!< Power cut timer value */ + bool pc_count_enable; /*!< Power cut counter enable, + If TURE, Power cuts are disabled + when pc_count > pc_max_count; + If FALSE, Power cuts are not + disabled when + pc_count > pc_max_count */ + unsigned char pc_count; /*!< Power cut count */ + unsigned char pc_max_count; /*!< Power cut maximum count */ + bool warm_enable; /*!< User Off state enable */ + bool user_off_pc; /*!< Automatic transition to user off + during power cut */ + bool clk_32k_enable; /*!< 32 kHz output buffer enable + during memory hold */ + bool clk_32k_user_off; /*!< Keeps the CLK32KMCU active during + user off power cut modes */ + bool en_vbkup1; /*!< enable VBKUP1 regulator */ + bool auto_en_vbkup1; /*!< automatically enable VBKUP1 + regulator in the memory hold + and user of modes */ + t_vhold_voltage vhold_voltage; /*!< output voltage for VBKUP1 */ + bool en_vbkup2; /*!< enable VBKUP2 regulator */ + bool auto_en_vbkup2; /*!< automatically enable VBKUP2 + regulator in the memory hold + and user of modes */ + t_vhold_voltage vhold_voltage2; /*!< output voltage for VBKUP2 */ + unsigned char mem_timer; /*!< duration of the memory hold + timer */ + bool mem_allon; /*!< memory hold timer infinity mode, + If TRUE, the memory hold timer + will be set to infinity and + the mem_timer filed will be + ignored */ +} t_pc_config; + +/*! + * brief PMIC regulators. + */ + +typedef enum { + SW_SW1A = 0, /*!< SW1A or SW1 */ + SW_SW1B, /*!< SW1B */ + SW_SW2A, /*!< SW2A or SW2 */ + SW_SW2B, /*!< SW2B */ + SW_SW3, /*!< SW3 */ + SW_PLL, /*!< PLL */ + REGU_VAUDIO, /*!< VAUDIO */ + REGU_VIOHI, /*!< VIOHI */ + REGU_VIOLO, /*!< VIOLO */ + REGU_VDIG, /*!< VDIG */ + REGU_VGEN, /*!< VGEN */ + REGU_VRFDIG, /*!< VRFDIG */ + REGU_VRFREF, /*!< VRFREF */ + REGU_VRFCP, /*!< VRFCP */ + REGU_VSIM, /*!< VSIM */ + REGU_VESIM, /*!< VESIM */ + REGU_VCAM, /*!< VCAM */ + REGU_VRFBG, /*!< VRFBG */ + REGU_VVIB, /*!< VVIB */ + REGU_VRF1, /*!< VRF1 */ + REGU_VRF2, /*!< VRF2 */ + REGU_VMMC1, /*!< VMMC1 or VMMC */ + REGU_VMMC2, /*!< VMMC2 */ + REGU_GPO1, /*!< GPIO1 */ + REGU_GPO2, /*!< GPO2 */ + REGU_GPO3, /*!< GPO3 */ + REGU_GPO4, /*!< GPO4 */ + REGU_V1, /*!< V1 */ + REGU_V2, /*!< V2 */ + REGU_V3, /*!< V3 */ + REGU_V4, /*!< V4 */ +} t_pmic_regulator; + +/*! + * @enum t_pmic_regulator_voltage_sw1 + * @brief PMIC Switch mode regulator SW1 output voltages. + */ + +typedef enum { + SW1_1V = 0, /*!< 1.0 V */ + SW1_1_1V, /*!< 1.1 V */ + SW1_1_2V, /*!< 1.2 V */ + SW1_1_3V, /*!< 1.3 V */ + SW1_1_4V, /*!< 1.4 V */ + SW1_1_55V, /*!< 1.55 V */ + SW1_1_625V, /*!< 1.625 V */ + SW1_1_875V, /*!< 1.875 V */ +} t_pmic_regulator_voltage_sw1; + +/*! + * @enum t_pmic_regulator_voltage_sw1a + * @brief PMIC regulator SW1A output voltage. + */ +typedef enum { + SW1A_0_9V = 0, /*!< 0.900 V */ + SW1A_0_925V, /*!< 0.925 V */ + SW1A_0_95V, /*!< 0.950 V */ + SW1A_0_975V, /*!< 0.975 V */ + SW1A_1V, /*!< 1.000 V */ + SW1A_1_025V, /*!< 1.025 V */ + SW1A_1_05V, /*!< 1.050 V */ + SW1A_1_075V, /*!< 1.075 V */ + SW1A_1_1V, /*!< 1.100 V */ + SW1A_1_125V, /*!< 1.125 V */ + SW1A_1_15V, /*!< 1.150 V */ + SW1A_1_175V, /*!< 1.175 V */ + SW1A_1_2V, /*!< 1.200 V */ + SW1A_1_225V, /*!< 1.225 V */ + SW1A_1_25V, /*!< 1.250 V */ + SW1A_1_275V, /*!< 1.275 V */ + SW1A_1_3V, /*!< 1.300 V */ + SW1A_1_325V, /*!< 1.325 V */ + SW1A_1_35V, /*!< 1.350 V */ + SW1A_1_375V, /*!< 1.375 V */ + SW1A_1_4V, /*!< 1.400 V */ + SW1A_1_425V, /*!< 1.425 V */ + SW1A_1_45V, /*!< 1.450 V */ + SW1A_1_475V, /*!< 1.475 V */ + SW1A_1_5V, /*!< 1.500 V */ + SW1A_1_525V, /*!< 1.525 V */ + SW1A_1_55V, /*!< 1.550 V */ + SW1A_1_575V, /*!< 1.575 V */ + SW1A_1_6V, /*!< 1.600 V */ + SW1A_1_625V, /*!< 1.625 V */ + SW1A_1_65V, /*!< 1.650 V */ + SW1A_1_675V, /*!< 1.675 V */ + SW1A_1_7V, /*!< 1.700 V */ + SW1A_1_8V = 36, /*!< 1.800 V */ + SW1A_1_85V = 40, /*!< 1.850 V */ + SW1A_2V = 44, /*!< 2_000 V */ + SW1A_2_1V = 48, /*!< 2_100 V */ + SW1A_2_2V = 52, /*!< 2_200 V */ +} t_pmic_regulator_voltage_sw1a; + +/*! + * @enum t_pmic_regulator_voltage_sw1b + * @brief PMIC regulator SW1B output voltage. + */ +typedef enum { + SW1B_0_9V = 0, /*!< 0.900 V */ + SW1B_0_925V, /*!< 0.925 V */ + SW1B_0_95V, /*!< 0.950 V */ + SW1B_0_975V, /*!< 0.975 V */ + SW1B_1V, /*!< 1.000 V */ + SW1B_1_025V, /*!< 1.025 V */ + SW1B_1_05V, /*!< 1.050 V */ + SW1B_1_075V, /*!< 1.075 V */ + SW1B_1_1V, /*!< 1.100 V */ + SW1B_1_125V, /*!< 1.125 V */ + SW1B_1_15V, /*!< 1.150 V */ + SW1B_1_175V, /*!< 1.175 V */ + SW1B_1_2V, /*!< 1.200 V */ + SW1B_1_225V, /*!< 1.225 V */ + SW1B_1_25V, /*!< 1.250 V */ + SW1B_1_275V, /*!< 1.275 V */ + SW1B_1_3V, /*!< 1.300 V */ + SW1B_1_325V, /*!< 1.325 V */ + SW1B_1_35V, /*!< 1.350 V */ + SW1B_1_375V, /*!< 1.375 V */ + SW1B_1_4V, /*!< 1.400 V */ + SW1B_1_425V, /*!< 1.425 V */ + SW1B_1_45V, /*!< 1.450 V */ + SW1B_1_475V, /*!< 1.475 V */ + SW1B_1_5V, /*!< 1.500 V */ + SW1B_1_525V, /*!< 1.525 V */ + SW1B_1_55V, /*!< 1.550 V */ + SW1B_1_575V, /*!< 1.575 V */ + SW1B_1_6V, /*!< 1.600 V */ + SW1B_1_625V, /*!< 1.625 V */ + SW1B_1_65V, /*!< 1.650 V */ + SW1B_1_675V, /*!< 1.675 V */ + SW1B_1_7V, /*!< 1.700 V */ + SW1B_1_8V = 36, /*!< 1.800 V */ + SW1B_1_85V = 40, /*!< 1.850 V */ + SW1B_2V = 44, /*!< 2_000 V */ + SW1B_2_1V = 48, /*!< 2_100 V */ + SW1B_2_2V = 52, /*!< 2_200 V */ +} t_pmic_regulator_voltage_sw1b; + +/*! + * @enum t_pmic_regulator_voltage_sw2 + * @brief PMIC Switch mode regulator SW2 output voltages. + */ +typedef enum { + SW2_1V = 0, /*!< 1.0 V */ + SW2_1_1V, /*!< 1.1 V */ + SW2_1_2V, /*!< 1.2 V */ + SW2_1_3V, /*!< 1.3 V */ + SW2_1_4V, /*!< 1.4 V */ + SW2_1_55V, /*!< 1.55 V */ + SW2_1_625V, /*!< 1.625 V */ + SW2_1_875V, /*!< 1.875 V */ +} t_pmic_regulator_voltage_sw2; + +/*! + * @enum t_pmic_regulator_voltage_sw2a + * @brief PMIC regulator SW2A output voltage. + */ +typedef enum { + SW2A_0_9V = 0, /*!< 0.900 V */ + SW2A_0_925V, /*!< 0.925 V */ + SW2A_0_95V, /*!< 0.950 V */ + SW2A_0_975V, /*!< 0.975 V */ + SW2A_1V, /*!< 1.000 V */ + SW2A_1_025V, /*!< 1.025 V */ + SW2A_1_05V, /*!< 1.050 V */ + SW2A_1_075V, /*!< 1.075 V */ + SW2A_1_1V, /*!< 1.100 V */ + SW2A_1_125V, /*!< 1.125 V */ + SW2A_1_15V, /*!< 1.150 V */ + SW2A_1_175V, /*!< 1.175 V */ + SW2A_1_2V, /*!< 1.200 V */ + SW2A_1_225V, /*!< 1.225 V */ + SW2A_1_25V, /*!< 1.250 V */ + SW2A_1_275V, /*!< 1.275 V */ + SW2A_1_3V, /*!< 1.300 V */ + SW2A_1_325V, /*!< 1.325 V */ + SW2A_1_35V, /*!< 1.350 V */ + SW2A_1_375V, /*!< 1.375 V */ + SW2A_1_4V, /*!< 1.400 V */ + SW2A_1_425V, /*!< 1.425 V */ + SW2A_1_45V, /*!< 1.450 V */ + SW2A_1_475V, /*!< 1.475 V */ + SW2A_1_5V, /*!< 1.500 V */ + SW2A_1_525V, /*!< 1.525 V */ + SW2A_1_55V, /*!< 1.550 V */ + SW2A_1_575V, /*!< 1.575 V */ + SW2A_1_6V, /*!< 1.600 V */ + SW2A_1_625V, /*!< 1.625 V */ + SW2A_1_65V, /*!< 1.650 V */ + SW2A_1_675V, /*!< 1.675 V */ + SW2A_1_7V, /*!< 1.700 V */ + SW2A_1_8V = 36, /*!< 1.800 V */ + SW2A_1_9V = 40, /*!< 1.900 V */ + SW2A_2V = 44, /*!< 2_000 V */ + SW2A_2_1V = 48, /*!< 2_100 V */ + SW2A_2_2V = 52, /*!< 2_200 V */ +} t_pmic_regulator_voltage_sw2a; + +/*! + * @enum t_pmic_regulator_voltage_sw2b + * @brief PMIC regulator SW2B output voltage. + */ +typedef enum { + SW2B_0_9V = 0, /*!< 0.900 V */ + SW2B_0_925V, /*!< 0.925 V */ + SW2B_0_95V, /*!< 0.950 V */ + SW2B_0_975V, /*!< 0.975 V */ + SW2B_1V, /*!< 1.000 V */ + SW2B_1_025V, /*!< 1.025 V */ + SW2B_1_05V, /*!< 1.050 V */ + SW2B_1_075V, /*!< 1.075 V */ + SW2B_1_1V, /*!< 1.100 V */ + SW2B_1_125V, /*!< 1.125 V */ + SW2B_1_15V, /*!< 1.150 V */ + SW2B_1_175V, /*!< 1.175 V */ + SW2B_1_2V, /*!< 1.200 V */ + SW2B_1_225V, /*!< 1.225 V */ + SW2B_1_25V, /*!< 1.250 V */ + SW2B_1_275V, /*!< 1.275 V */ + SW2B_1_3V, /*!< 1.300 V */ + SW2B_1_325V, /*!< 1.325 V */ + SW2B_1_35V, /*!< 1.350 V */ + SW2B_1_375V, /*!< 1.375 V */ + SW2B_1_4V, /*!< 1.400 V */ + SW2B_1_425V, /*!< 1.425 V */ + SW2B_1_45V, /*!< 1.450 V */ + SW2B_1_475V, /*!< 1.475 V */ + SW2B_1_5V, /*!< 1.500 V */ + SW2B_1_525V, /*!< 1.525 V */ + SW2B_1_55V, /*!< 1.550 V */ + SW2B_1_575V, /*!< 1.575 V */ + SW2B_1_6V, /*!< 1.600 V */ + SW2B_1_625V, /*!< 1.625 V */ + SW2B_1_65V, /*!< 1.650 V */ + SW2B_1_675V, /*!< 1.675 V */ + SW2B_1_7V, /*!< 1.700 V */ + SW2B_1_8V = 36, /*!< 1.800 V */ + SW2B_1_9V = 40, /*!< 1.900 V */ + SW2B_2V = 44, /*!< 2_000 V */ + SW2B_2_1V = 48, /*!< 2_100 V */ + SW2B_2_2V = 52, /*!< 2_200 V */ +} t_pmic_regulator_voltage_sw2b; + +/*! + * @enum t_pmic_regulator_voltage_sw3 + * @brief PMIC Switch mode regulator SW3 output voltages. + */ +typedef enum { + SW3_5V = 0, /*!< 5.0 V */ + SW3_5_1V = 0, /*!< 5.1 V */ + SW3_5_6V, /*!< 5.6 V */ +} t_pmic_regulator_voltage_sw3; + +/*! + * @enum t_switcher_factor + * @brief PLL multiplication factor + */ +typedef enum { + FACTOR_28 = 0, /*!< 917 504 kHz */ + FACTOR_29, /*!< 950 272 kHz */ + FACTOR_30, /*!< 983 040 kHz */ + FACTOR_31, /*!< 1 015 808 kHz */ + FACTOR_32, /*!< 1 048 576 kHz */ + FACTOR_33, /*!< 1 081 344 kHz */ + FACTOR_34, /*!< 1 114 112 kHz */ + FACTOR_35, /*!< 1 146 880 kHz */ +} t_switcher_factor; + +/*! + * @enum t_pmic_regulator_voltage_violo + * @brief PMIC regulator VIOLO output voltage. + */ +typedef enum { + VIOLO_1_2V = 0, /*!< 1.2 V */ + VIOLO_1_3V, /*!< 1.3 V */ + VIOLO_1_5V, /*!< 1.5 V */ + VIOLO_1_8V, /*!< 1.8 V */ +} t_pmic_regulator_voltage_violo; + +/*! + * @enum t_pmic_regulator_voltage_vdig + * @brief PMIC regulator VDIG output voltage. + */ +typedef enum { + VDIG_1_2V = 0, /*!< 1.2 V */ + VDIG_1_3V, /*!< 1.3 V */ + VDIG_1_5V, /*!< 1.5 V */ + VDIG_1_8V, /*!< 1.8 V */ +} t_pmic_regulator_voltage_vdig; + +/*! + * @enum t_pmic_regulator_voltage_vgen + * @brief PMIC regulator VGEN output voltage. + */ +typedef enum { + VGEN_1_2V = 0, /*!< 1.2 V */ + VENG_1_3V, /*!< 1.3 V */ + VGEN_1_5V, /*!< 1.5 V */ + VGEN_1_8V, /*!< 1.8 V */ + VGEN_1_1V, /*!< 1.1 V */ + VGEN_2V, /*!< 2 V */ + VGEN_2_775V, /*!< 2.775 V */ + VGEN_2_4V, /*!< 2.4 V */ +} t_pmic_regulator_voltage_vgen; + +/*! + * @enum t_pmic_regulator_voltage_vrfdig + * @brief PMIC regulator VRFDIG output voltage. + */ +typedef enum { + VRFDIG_1_2V = 0, /*!< 1.2 V */ + VRFDIG_1_5V, /*!< 1.5 V */ + VRFDIG_1_8V, /*!< 1.8 V */ + VRFDIG_1_875V, /*!< 1.875 V */ +} t_pmic_regulator_voltage_vrfdig; + +/*! + * @enum t_pmic_regulator_voltage_vrfref + * @brief PMIC regulator VRFREF output voltage. + */ +typedef enum { + VRFREF_2_475V = 0, /*!< 2.475 V */ + VRFREF_2_6V, /*!< 2.600 V */ + VRFREF_2_7V, /*!< 2.700 V */ + VRFREF_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_vrfref; + +/*! + * @enum t_pmic_regulator_voltage_vrfcp + * @brief PMIC regulator VRFCP output voltage. + */ +typedef enum { + VRFCP_2_7V = 0, /*!< 2.700 V */ + VRFCP_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_vrfcp; + +/*! + * @enum t_pmic_regulator_voltage_vsim + * @brief PMIC linear regulator VSIM output voltage. + */ +typedef enum { + VSIM_1_8V = 0, /*!< 1.8 V */ + VSIM_2_9V, /*!< 2.90 V */ + VSIM_3V = 1, /*!< 3 V */ +} t_pmic_regulator_voltage_vsim; + +/*! + * @enum t_pmic_regulator_voltage_vesim + * @brief PMIC regulator VESIM output voltage. + */ +typedef enum { + VESIM_1_8V = 0, /*!< 1.80 V */ + VESIM_2_9V, /*!< 2.90 V */ +} t_pmic_regulator_voltage_vesim; + +/*! + * @enum t_pmic_regulator_voltage_vcam + * @brief PMIC regulator VCAM output voltage. + */ +typedef enum { + VCAM_1_5V = 0, /*!< 1.50 V */ + VCAM_1_8V, /*!< 1.80 V */ + VCAM_2_5V, /*!< 2.50 V */ + VCAM_2_55V, /*!< 2.55 V */ + VCAM_2_6V, /*!< 2.60 V */ + VCAM_2_75V, /*!< 2.75 V */ + VCAM_2_8V, /*!< 2.80 V */ + VCAM_3V, /*!< 3.00 V */ +} t_pmic_regulator_voltage_vcam; + +/*! + * @enum t_pmic_regulator_voltage_vvib + * @brief PMIC linear regulator V_VIB output voltage. + */ +typedef enum { + VVIB_1_3V = 0, /*!< 1.30 V */ + VVIB_1_8V, /*!< 1.80 V */ + VVIB_2V, /*!< 2 V */ + VVIB_3V, /*!< 3 V */ +} t_pmic_regulator_voltage_vvib; + +/*! + * @enum t_pmic_regulator_voltage_vrf1 + * @brief PMIC regulator VRF1 output voltage. + */ +typedef enum { + VRF1_1_5V = 0, /*!< 1.500 V */ + VRF1_1_875V, /*!< 1.875 V */ + VRF1_2_7V, /*!< 2.700 V */ + VRF1_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_vrf1; + +/*! + * @enum t_pmic_regulator_voltage_vrf2 + * @brief PMIC regulator VRF2 output voltage. + */ +typedef enum { + VRF2_1_5V = 0, /*!< 1.500 V */ + VRF2_1_875V, /*!< 1.875 V */ + VRF2_2_7V, /*!< 2.700 V */ + VRF2_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_vrf2; + +/*! + * @enum t_pmic_regulator_voltage_vmmc + * @brief PMIC linear regulator VMMC output voltage. + */ +typedef enum { + VMMC_OFF = 0, /*!< Output off */ + VMMC_1_6V, /*!< 1.6 V */ + VMMC_1_8V, /*!< 1.8 V */ + VMMC_2V, /*!< 2 V */ + VMMC_2_2V, /*!< 2.2 V */ + VMMC_2_4V, /*!< 2.4 V */ + VMMC_2_6V, /*!< 2.6 V */ + VMMC_2_8V, /*!< 2.8 V */ + VMMC_3V, /*!< 3 V */ + VMMC_3_2V, /*!< 3.2 V */ + VMMC_3_3V, /*!< 3.3 V */ + VMMC_3_4V, /*!< 3.4 V */ +} t_pmic_regulator_voltage_vmmc; + +/*! + * @enum t_pmic_regulator_voltage_vmmc1 + * @brief PMIC regulator VMMC1 output voltage. + */ +typedef enum { + VMMC1_1_6V = 0, /*!< 1.60 V */ + VMMC1_1_8V, /*!< 1.80 V */ + VMMC1_2V, /*!< 2.00 V */ + VMMC1_2_6V, /*!< 2.60 V */ + VMMC1_2_7V, /*!< 2.70 V */ + VMMC1_2_8V, /*!< 2.80 V */ + VMMC1_2_9V, /*!< 2.90 V */ + VMMC1_3V, /*!< 3.00 V */ +} t_pmic_regulator_voltage_vmmc1; + +/*! + * @enum t_pmic_regulator_voltage_vmmc2 + * @brief PMIC regulator VMMC2 output voltage. + */ +typedef enum { + VMMC2_1_6V = 0, /*!< 1.60 V */ + VMMC2_1_8V, /*!< 1.80 V */ + VMMC2_2V, /*!< 2.00 V */ + VMMC2_2_6V, /*!< 2.60 V */ + VMMC2_2_7V, /*!< 2.70 V */ + VMMC2_2_8V, /*!< 2.80 V */ + VMMC2_2_9V, /*!< 2.90 V */ + VMMC2_3V, /*!< 3.00 V */ +} t_pmic_regulator_voltage_vmmc2; + +/*! + * @enum t_pmic_regulator_voltage_v1 + * @brief PMIC linear regulator V1 output voltages. + */ +typedef enum { + V1_2_775V = 0, /*!< 2.775 V */ + V1_1_2V, /*!< 1.2 V */ + V1_1_3V, /*!< 1.3 V */ + V1_1_4V, /*!< 1.4 V */ + V1_1_55V, /*!< 1.55 V */ + V1_1_75V, /*!< 1.75 V */ + V1_1_875V, /*!< 1.875 V */ + V1_2_475V, /*!< 2.475 V */ +} t_pmic_regulator_voltage_v1; + +/*! + * @enum t_pmic_regulator_voltage_v2 + * @brief PMIC linear regulator V2 output voltage, V2 has fixed + * output voltage 2.775 volts. + */ +typedef enum { + V2_2_775V = 0, /*!< 2.775 V */ +} t_pmic_regulator_voltage_v2; + +/*! + * @enum t_pmic_regulator_voltage_v3 + * @brief PMIC linear regulator V3 output voltage. + */ +typedef enum { + V3_1_875V = 0, /*!< 1.875 V */ + V3_2_775V, /*!< 2.775 V */ +} t_pmic_regulator_voltage_v3; + +/*! + * @enum t_pmic_regulator_voltage_v4 + * @brief PMIC linear regulator V4 output voltage, V4 has fixed + * output voltage 2.775 volts. + */ +typedef enum { + V4_2_775V = 0, /*!< 2.775 V */ +} t_pmic_regulator_voltage_v4; + +/*! + * @union t_regulator_voltage + * @brief PMIC regulator output voltages. + */ +typedef union { + t_pmic_regulator_voltage_sw1 sw1; /*!< SW1 voltage */ + t_pmic_regulator_voltage_sw1a sw1a; /*!< SW1A voltage */ + t_pmic_regulator_voltage_sw1b sw1b; /*!< SW1B voltage */ + t_pmic_regulator_voltage_sw2 sw2; /*!< SW2 voltage */ + t_pmic_regulator_voltage_sw2a sw2a; /*!< SW2A voltage */ + t_pmic_regulator_voltage_sw2b sw2b; /*!< SW2B voltage */ + t_pmic_regulator_voltage_sw3 sw3; /*!< SW3 voltage */ + t_pmic_regulator_voltage_violo violo; /*!< VIOLO voltage */ + t_pmic_regulator_voltage_vdig vdig; /*!< VDIG voltage */ + t_pmic_regulator_voltage_vgen vgen; /*!< VGEN voltage */ + t_pmic_regulator_voltage_vrfdig vrfdig; /*!< VRFDIG voltage */ + t_pmic_regulator_voltage_vrfref vrfref; /*!< VRFREF voltage */ + t_pmic_regulator_voltage_vrfcp vrfcp; /*!< VRFCP voltage */ + t_pmic_regulator_voltage_vsim vsim; /*!< VSIM voltage */ + t_pmic_regulator_voltage_vesim vesim; /*!< VESIM voltage */ + t_pmic_regulator_voltage_vcam vcam; /*!< VCAM voltage */ + t_pmic_regulator_voltage_vvib vvib; /*!< VVIB voltage */ + t_pmic_regulator_voltage_vrf1 vrf1; /*!< VRF1 voltage */ + t_pmic_regulator_voltage_vrf2 vrf2; /*!< VRF2 voltage */ + t_pmic_regulator_voltage_vmmc vmmc; /*!< VMMC voltage */ + t_pmic_regulator_voltage_vmmc1 vmmc1; /*!< VMMC1 voltage */ + t_pmic_regulator_voltage_vmmc2 vmmc2; /*!< VMMC2 voltage */ + t_pmic_regulator_voltage_v1 v1; /*!< V1 voltage */ + t_pmic_regulator_voltage_v2 v2; /*!< V2 voltage */ + t_pmic_regulator_voltage_v3 v3; /*!< V3 voltage */ + t_pmic_regulator_voltage_v4 v4; /*!< V4 voltage */ +} t_regulator_voltage; + +/*! + * @enum t_pmic_regulator_sw_mode + * @brief define switch mode regulator mode. + * + * The synchronous rectifier can be disabled (and pulse-skipping enabled) + * to improve low current efficiency. Software should disable synchronous + * rectifier / enable the pulse skipping for average loads less than + * approximately 30 mA, depending on the quiescent current penalty due to + * synchronous mode. + */ +typedef enum { + SYNC_RECT = 0, + NO_PULSE_SKIP, + PULSE_SKIP, + LOW_POWER, +} t_pmic_regulator_sw_mode; + +/*! + * Generic PMIC switch mode regulator mode. + */ +typedef t_pmic_regulator_sw_mode t_regulator_sw_mode; +typedef t_pmic_regulator_sw_mode t_regulator_stby_mode; + +/*! + * @enum t_regulator_lp_mode + * @brief Low power mode control modes. + */ + +typedef enum { + /*! + * Low Power Mode is disabled + */ + LOW_POWER_DISABLED = 0, + /*! + * Low Power Mode is controlled by STANDBY pin and/or LVS pin + */ + LOW_POWER_CTRL_BY_PIN, + /*! + * Set Low Power mode no matter of hardware pins + */ + LOW_POWER_EN, + /*! + * Set Low Power mode and control by STANDBY + */ + LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN, +} t_regulator_lp_mode; + +/*! + * @enum t_switcher_dvs_speed + * @brief DVS speed setting + */ +typedef enum { + /*! + * Transition speed is dictated by the current + * limit and input -output conditions + */ + DICTATED = 0, + /*! + * 25mV step each 4us + */ + DVS_4US, + /*! + * 25mV step each 8us + */ + DVS_8US, + /*! + * 25mV step each 16us + */ + DVS_16US, +} t_switcher_dvs_speed; + +/*! + * @struct t_regulator_config + * @brief regulator configuration. + * + */ + +typedef struct { + /*! + * Switch mode regulator operation mode. This field only applies to + * switch mode regulators. + */ + t_regulator_sw_mode mode; + /*! + * Switch mode stby regulator operation mode. This field only applies + * to switch mode regulators. + */ + t_regulator_stby_mode stby_mode; + /*! + * Regulator output voltage. + */ + t_regulator_voltage voltage; + /*! + * Regulator output voltage in LVS mode. + */ + t_regulator_voltage voltage_lvs; + /*! + * Regulator output voltage in standby mode. + */ + t_regulator_voltage voltage_stby; + /*! + * Regulator low power mode. + */ + t_regulator_lp_mode lp_mode; + /*! + * Switcher dvs speed + */ + t_switcher_dvs_speed dvs_speed; + /*! + * Switcher panic mode + */ + bool panic_mode; + /*! + * Switcher softstart + */ + bool softstart; + /*! + * PLL Multiplication factor + */ + t_switcher_factor factor; +} t_regulator_config; + +/*! + * @struct t_regulator_cfg_param + * @brief regulator configuration structure for IOCTL. + * + */ +typedef struct { + /*! + * Regulator. + */ + t_pmic_regulator regulator; + /*! + * Regulator configuration. + */ + t_regulator_config cfg; +} t_regulator_cfg_param; + +/*! + * This struct list all state reads in Power Up Sense + */ +struct t_p_up_sense { + /*! + * power up sense ictest + */ + bool state_ictest; + /*! + * power up sense clksel + */ + bool state_clksel; + /*! + * power up mode supply 1 + */ + bool state_pums1; + /*! + * power up mode supply 2 + */ + bool state_pums2; + /*! + * power up mode supply 3 + */ + bool state_pums3; + /*! + * power up sense charge mode 0 + */ + bool state_chrgmode0; + /*! + * power up sense charge mode 1 + */ + bool state_chrgmode1; + /*! + * power up sense USB mode + */ + bool state_umod; + /*! + * power up sense boot mode enable for USB/RS232 + */ + bool state_usben; + /*! + * power up sense switcher 1a1b joined + */ + bool state_sw_1a1b_joined; + /*! + * power up sense switcher 1a1b joined + */ + bool state_sw_2a2b_joined; +}; + +/*! + * This enumeration define all On_OFF button + */ +typedef enum { + /*! + * ON1B + */ + BT_ON1B = 0, + /*! + * ON2B + */ + BT_ON2B, + /*! + * ON3B + */ + BT_ON3B, +} t_button; + +#ifdef __KERNEL__ +/* EXPORTED FUNCTIONS */ + +/*! + * This function sets user power off in power control register and thus powers + * off the phone. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +void pmic_power_off(void); + +/*! + * This function sets the power control configuration. + * + * @param pc_config power control configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_set_pc_config(t_pc_config *pc_config); + +/*! + * This function retrives the power control configuration. + * + * @param pc_config pointer to power control configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_pc_config(t_pc_config *pc_config); + +/*! + * This function turns on a regulator. + * + * @param regulator The regulator to be turned on. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_on(t_pmic_regulator regulator); + +/*! + * This function turns off a regulator. + * + * @param regulator The regulator to be turned off. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_off(t_pmic_regulator regulator); + +/*! + * This function sets the regulator output voltage. + * + * @param regulator The regulator to be turned off. + * @param voltage The regulator output voltage. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_voltage(t_pmic_regulator regulator, + t_regulator_voltage voltage); + +/*! + * This function retrieves the regulator output voltage. + * + * @param regulator The regulator to be turned off. + * @param voltage Pointer to regulator output voltage. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_voltage(t_pmic_regulator regulator, + t_regulator_voltage *voltage); + +/*! + * This function sets the DVS voltage + * + * @param regulator The regulator to be configured. + * @param dvs The switch Dynamic Voltage Scaling + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_dvs(t_pmic_regulator regulator, + t_regulator_voltage dvs); + +/*! + * This function gets the DVS voltage + * + * @param regulator The regulator to be handled. + * @param dvs The switch Dynamic Voltage Scaling + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_dvs(t_pmic_regulator regulator, + t_regulator_voltage *dvs); + +/*! + * This function sets the standby voltage + * + * @param regulator The regulator to be configured. + * @param stby The switch standby voltage + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_stby(t_pmic_regulator regulator, + t_regulator_voltage stby); + +/*! + * This function gets the standby voltage + * + * @param regulator The regulator to be handled. + * @param stby The switch standby voltage + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_stby(t_pmic_regulator regulator, + t_regulator_voltage *stby); + +/*! + * This function sets the switchers mode. + * + * @param regulator The regulator to be configured. + * @param mode The switcher mode + * @param stby Switch between main and standby. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_mode(t_pmic_regulator regulator, + t_regulator_sw_mode mode, bool stby); + +/*! + * This function gets the switchers mode. + * + * @param regulator The regulator to be handled. + * @param mode The switcher mode. + * @param stby Switch between main and standby. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_mode(t_pmic_regulator regulator, + t_regulator_sw_mode *mode, bool stby); + +/*! + * This function sets the switch dvs speed + * + * @param regulator The regulator to be configured. + * @param speed The dvs speed. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_dvs_speed(t_pmic_regulator regulator, + t_switcher_dvs_speed speed); + +/*! + * This function gets the switch dvs speed + * + * @param regulator The regulator to be handled. + * @param speed The dvs speed. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_dvs_speed(t_pmic_regulator regulator, + t_switcher_dvs_speed *speed); + +/*! + * This function sets the switch panic mode + * + * @param regulator The regulator to be configured. + * @param panic_mode Enable or disable panic mode + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_panic_mode(t_pmic_regulator regulator, + bool panic_mode); + +/*! + * This function gets the switch panic mode + * + * @param regulator The regulator to be handled + * @param panic_mode Enable or disable panic mode + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_panic_mode(t_pmic_regulator regulator, + bool *panic_mode); + +/*! + * This function sets the switch softstart mode + * + * @param regulator The regulator to be configured. + * @param softstart Enable or disable softstart. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_softstart(t_pmic_regulator regulator, + bool softstart); + +/*! + * This function gets the switch softstart mode + * + * @param regulator The regulator to be handled + * @param softstart Enable or disable softstart. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_softstart(t_pmic_regulator regulator, + bool *softstart); + +/*! + * This function sets the PLL multiplication factor + * + * @param regulator The regulator to be configured. + * @param factor The multiplication factor. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_factor(t_pmic_regulator regulator, + t_switcher_factor factor); + +/*! + * This function gets the PLL multiplication factor + * + * @param regulator The regulator to be handled + * @param factor The multiplication factor. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_factor(t_pmic_regulator regulator, + t_switcher_factor *factor); + +/*! + * This function enables or disables low power mode. + * + * @param regulator The regulator to be configured. + * @param mode Select nominal or low power mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_lp_mode(t_pmic_regulator regulator, + t_regulator_lp_mode lp_mode); + +/*! + * This function gets low power mode. + * + * @param regulator The regulator to be handled + * @param mode Select nominal or low power mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_lp_mode(t_pmic_regulator regulator, + t_regulator_lp_mode *lp_mode); + +/*! + * This function sets the regulator configuration. + * + * @param regulator The regulator to be turned off. + * @param config The regulator output configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_config(t_pmic_regulator regulator, + t_regulator_config *config); + +/*! + * This function retrieves the regulator output configuration. + * + * @param regulator The regulator to be turned off. + * @param config Pointer to regulator configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_config(t_pmic_regulator regulator, + t_regulator_config *config); + +/*! + * This function enables automatically VBKUP2 in the memory hold modes. + * + * @param en if true, enable VBKUP2AUTOMH + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_vbkup2_auto_en(bool en); + +/*! + * This function gets state of automatically VBKUP2. + * + * @param en if true, VBKUP2AUTOMH is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_vbkup2_auto_state(bool *en); + +/*! + * This function enables battery detect function. + * + * @param en if true, enable BATTDETEN + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_bat_det_en(bool en); + +/*! + * This function gets state of battery detect function. + * + * @param en if true, BATTDETEN is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_bat_det_state(bool *en); + +/*! + * This function enables control of VVIB by VIBEN pin. + * + * @param en if true, enable VIBPINCTRL + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_vib_pin_en(bool en); + +/*! + * This function gets state of control of VVIB by VIBEN pin. + * @param en if true, VIBPINCTRL is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_gets_vib_pin_state(bool *en); + +/*! + * This function returns power up sense value + * + * @param p_up_sense value of power up sense + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_power_mode_sense(struct t_p_up_sense *p_up_sense); + +/*! + * This function configures the Regen assignment for all regulator + * + * @param regulator type of regulator + * @param en_dis if true, the regulator is enabled by regen. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_regen_assig(t_pmic_regulator regulator, bool en_dis); + +/*! + * This function gets the Regen assignment for all regulator + * + * @param regulator type of regulator + * @param en_dis return value, if true : + * the regulator is enabled by regen. + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_regen_assig(t_pmic_regulator regu, bool *en_dis); + +/*! + * This function sets the Regen polarity. + * + * @param en_dis If true regen is inverted. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_regen_inv(bool en_dis); + +/*! + * This function gets the Regen polarity. + * + * @param en_dis If true regen is inverted. + * + * @return This function returns 0 if successful. + */ + +PMIC_STATUS pmic_power_get_regen_inv(bool *en_dis); + +/*! + * This function enables esim control voltage. + * + * @param vesim if true, enable VESIMESIMEN + * @param vmmc1 if true, enable VMMC1ESIMEN + * @param vmmc2 if true, enable VMMC2ESIMEN + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_esim_v_en(bool vesim, bool vmmc1, bool vmmc2); + +/*! + * This function gets esim control voltage values. + * + * @param vesim if true, enable VESIMESIMEN + * @param vmmc1 if true, enable VMMC1ESIMEN + * @param vmmc2 if true, enable VMMC2ESIMEN + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_gets_esim_v_state(bool *vesim, + bool *vmmc1, bool *vmmc2); + +/*! + * This function enables auto reset after a system reset. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_auto_reset_en(bool en); + +/*! + * This function gets auto reset configuration. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_auto_reset_en(bool *en); + +/*! + * This function configures a system reset on a button. + * + * @param bt type of button. + * @param sys_rst if true, enable the system reset on this button + * @param deb_time sets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_conf_button(t_button bt, bool sys_rst, int deb_time); + +/*! + * This function gets configuration of a button. + * + * @param bt type of button. + * @param sys_rst if true, the system reset is enabled on this button + * @param deb_time gets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_conf_button(t_button bt, + bool *sys_rst, int *deb_time); + +/*! + * This function is used to subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_sub(t_pwr_int event, void *callback); + +/*! + * This function is used to un subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_unsub(t_pwr_int event, void *callback); + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_PMIC_POWER_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h new file mode 100644 index 000000000000..d134d9de6682 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdma.h @@ -0,0 +1,572 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_SDMA_H__ +#define __ASM_ARCH_MXC_SDMA_H__ + +/*! + * @defgroup SDMA Smart Direct Memory Access (SDMA) Driver + */ + +/*! + * @file arch-mxc/sdma.h + * + * @brief This file contains the SDMA API declarations. + * + * SDMA is responsible on moving data between peripherals and memories (MCU, EMI and DSP). + * + * @ingroup SDMA + */ + +#include +#include +#include + +#include +#include + +/*! + * This defines maximum DMA address + */ +#define MAX_DMA_ADDRESS 0xffffffff + +/*! + * This defines maximum number of DMA channels + */ +#ifdef CONFIG_MXC_SDMA_API +#define MAX_DMA_CHANNELS 32 +#define MAX_BD_NUMBER 16 +#define MXC_SDMA_DEFAULT_PRIORITY 1 +#define MXC_SDMA_MIN_PRIORITY 1 +#define MXC_SDMA_MAX_PRIORITY 7 +#else +#define MAX_DMA_CHANNELS 0 +#endif + +#define MXC_FIFO_MEM_DEST_FIXED 0x1 +#define MXC_FIFO_MEM_SRC_FIXED 0x2 + +#define SDMA_ASRC_INFO_WML_OFF 0 +#define SDMA_ASRC_INFO_WML_MASK ((1 << 10) - 1) +#define SDMA_ASRC_INFO_PS (1 << 10) +#define SDMA_ASRC_INFO_PA (1 << 11) +#define SDMA_ASRC_INFO_TXFR_DIR (1 << 14) +#define SDMA_ASRC_INFO_N_OFF (24) +#define SDMA_ASRC_INFO_N_MASK ((1 << 4) - 1) + +#define SDMA_ASRC_P2P_INFO_LWML_OFF 0 +#define SDMA_ASRC_P2P_INFO_LWML_MASK ((1 << 8) - 1) +#define SDMA_ASRC_P2P_INFO_PS (1 << 8) +#define SDMA_ASRC_P2P_INFO_PA (1 << 9) +#define SDMA_ASRC_P2P_INFO_SPDIF (1 << 10) +#define SDMA_ASRC_P2P_INFO_SP (1 << 11) +#define SDMA_ASRC_P2P_INFO_DP (1 << 12) +#define SDMA_ASRC_P2P_INFO_HWML_OFF 14 +#define SDMA_ASRC_P2P_INFO_HWML_MASK ((1 << 10) - 1) +#define SDMA_ASRC_P2P_INFO_LWE (1 << 28) +#define SDMA_ASRC_P2P_INFO_HWE (1 << 29) +#define SDMA_ASRC_P2P_INFO_CONT (1 << 31) + +/*! + * This enumerates transfer types + */ +typedef enum { + emi_2_per = 0, /*!< EMI memory to peripheral */ + emi_2_int, /*!< EMI memory to internal RAM */ + emi_2_emi, /*!< EMI memory to EMI memory */ + emi_2_dsp, /*!< EMI memory to DSP memory */ + per_2_int, /*!< Peripheral to internal RAM */ + per_2_emi, /*!< Peripheral to internal EMI memory */ + per_2_dsp, /*!< Peripheral to DSP memory */ + per_2_per, /*!< Peripheral to Peripheral */ + int_2_per, /*!< Internal RAM to peripheral */ + int_2_int, /*!< Internal RAM to Internal RAM */ + int_2_emi, /*!< Internal RAM to EMI memory */ + int_2_dsp, /*!< Internal RAM to DSP memory */ + dsp_2_per, /*!< DSP memory to peripheral */ + dsp_2_int, /*!< DSP memory to internal RAM */ + dsp_2_emi, /*!< DSP memory to EMI memory */ + dsp_2_dsp, /*!< DSP memory to DSP memory */ + emi_2_dsp_loop, /*!< EMI memory to DSP memory loopback */ + dsp_2_emi_loop, /*!< DSP memory to EMI memory loopback */ + dvfs_pll, /*!< DVFS script with PLL change */ + dvfs_pdr /*!< DVFS script without PLL change */ +} sdma_transferT; + +/*! + * This enumerates peripheral types + */ +typedef enum { + SSI, /*!< MCU domain SSI */ + SSI_SP, /*!< Shared SSI */ + MMC, /*!< MMC */ + SDHC, /*!< SDHC */ + UART, /*!< MCU domain UART */ + UART_SP, /*!< Shared UART */ + FIRI, /*!< FIRI */ + CSPI, /*!< MCU domain CSPI */ + CSPI_SP, /*!< Shared CSPI */ + SIM, /*!< SIM */ + ATA, /*!< ATA */ + CCM, /*!< CCM */ + EXT, /*!< External peripheral */ + MSHC, /*!< Memory Stick Host Controller */ + MSHC_SP, /*!< Shared Memory Stick Host Controller */ + DSP, /*!< DSP */ + MEMORY, /*!< Memory */ + FIFO_MEMORY, /*!< FIFO type Memory */ + SPDIF, /*!< SPDIF */ + IPU_MEMORY, /*!< IPU Memory */ + ASRC, /*!< ASRC */ + ESAI, /*!< ESAI */ +} sdma_periphT; + +#ifndef TRANSFER_32BIT +/*! + * This defines SDMA access data size + */ +#define TRANSFER_32BIT 0x00 +#define TRANSFER_8BIT 0x01 +#define TRANSFER_16BIT 0x02 +#define TRANSFER_24BIT 0x03 + +#endif + +/*! + * This defines maximum device name length passed during mxc_request_dma(). + */ +#define MAX_DEVNAME_LENGTH 32 + +/*! + * This defines SDMA interrupt callback function prototype. + */ +typedef void (*dma_callback_t) (void *arg); + +/*! + * Structure containing sdma channel parameters. + */ +typedef struct { + __u32 watermark_level; /*!< Lower/upper threshold that + * triggers SDMA event + * for p2p, this is event1 watermark level + */ + __u32 per_address; /*!< Peripheral source/destination + * physical address + * for p2p, this is destination address + */ + sdma_periphT peripheral_type; /*!< Peripheral type */ + sdma_transferT transfer_type; /*!< Transfer type */ + int event_id; /*!< Event number, + * needed by all channels + * that started by peripherals dma + * request (per_2_*,*_2_per) + * Not used for memory and DSP + * transfers. + */ + int event_id2; /*!< Second event number, + * used in ATA scripts only. + */ + int bd_number; /*!< Buffer descriptors number. + * If not set, single buffer + * descriptor will be used. + */ + dma_callback_t callback; /*! callback function */ + void *arg; /*! callback argument */ + unsigned long word_size:8; /*!< SDMA data access word size */ + unsigned long ext:1; /*!< 1: extend parameter structure */ +} dma_channel_params; + +typedef struct { + dma_channel_params common; + unsigned long p2p_dir:1; /*!< 0: per2 to per. + * the device of peripheral_type is per. + * 1: per to per2 + * the device of peripheral_type is per2 + */ + unsigned long info_bits; /*!< info field in context */ + unsigned long info_mask; /*!< info field mask in context */ + __u32 watermark_level2; /*!< event2 threshold that + * triggers SDMA event + * just valid for p2p. + */ + __u32 per_address2; /*!< Peripheral source + * physical address. + * just valid for p2p. + */ + struct dma_channel_info info; /*!< the channel special parameter */ +} dma_channel_ext_params; + +/*! + * Structure containing sdma request parameters. + */ +typedef struct { + /*! physical source memory address */ + __u8 *sourceAddr; + /*! physical destination memory address */ + __u8 *destAddr; + /*! amount of data to transfer, + * updated during mxc_dma_get_config + */ + __u16 count; + /*!< DONE bit of the buffer descriptor, + * updated during mxc_dma_get_config + * 0 - means the BD is done and closed by SDMA + * 1 - means the BD is still being processed by SDMA + */ + int bd_done; + /*!< CONT bit of the buffer descriptor, + * set it if full multi-buffer descriptor mechanism + * required. + */ + int bd_cont; + /*!< ERROR bit of the buffer descriptor, + * updated during mxc_dma_get_config. + * If it is set - there was an error during BD processing. + */ + int bd_error; +} dma_request_t; + +/*! + * Structure containing sdma request parameters. + */ +typedef struct { + /*! address of ap_2_ap script */ + int mxc_sdma_ap_2_ap_addr; + /*! address of ap_2_bp script */ + int mxc_sdma_ap_2_bp_addr; + /*! address of ap_2_ap_fixed script */ + int mxc_sdma_ap_2_ap_fixed_addr; + /*! address of bp_2_ap script */ + int mxc_sdma_bp_2_ap_addr; + /*! address of loopback_on_dsp_side script */ + int mxc_sdma_loopback_on_dsp_side_addr; + /*! address of mcu_interrupt_only script */ + int mxc_sdma_mcu_interrupt_only_addr; + + /*! address of firi_2_per script */ + int mxc_sdma_firi_2_per_addr; + /*! address of firi_2_mcu script */ + int mxc_sdma_firi_2_mcu_addr; + /*! address of per_2_firi script */ + int mxc_sdma_per_2_firi_addr; + /*! address of mcu_2_firi script */ + int mxc_sdma_mcu_2_firi_addr; + + /*! address of uart_2_per script */ + int mxc_sdma_uart_2_per_addr; + /*! address of uart_2_mcu script */ + int mxc_sdma_uart_2_mcu_addr; + /*! address of per_2_app script */ + int mxc_sdma_per_2_app_addr; + /*! address of mcu_2_app script */ + int mxc_sdma_mcu_2_app_addr; + /*! address of per_2_per script */ + int mxc_sdma_per_2_per_addr; + + /*! address of uartsh_2_per script */ + int mxc_sdma_uartsh_2_per_addr; + /*! address of uartsh_2_mcu script */ + int mxc_sdma_uartsh_2_mcu_addr; + /*! address of per_2_shp script */ + int mxc_sdma_per_2_shp_addr; + /*! address of mcu_2_shp script */ + int mxc_sdma_mcu_2_shp_addr; + + /*! address of ata_2_mcu script */ + int mxc_sdma_ata_2_mcu_addr; + /*! address of mcu_2_ata script */ + int mxc_sdma_mcu_2_ata_addr; + + /*! address of app_2_per script */ + int mxc_sdma_app_2_per_addr; + /*! address of app_2_mcu script */ + int mxc_sdma_app_2_mcu_addr; + /*! address of shp_2_per script */ + int mxc_sdma_shp_2_per_addr; + /*! address of shp_2_mcu script */ + int mxc_sdma_shp_2_mcu_addr; + + /*! address of mshc_2_mcu script */ + int mxc_sdma_mshc_2_mcu_addr; + /*! address of mcu_2_mshc script */ + int mxc_sdma_mcu_2_mshc_addr; + + /*! address of spdif_2_mcu script */ + int mxc_sdma_spdif_2_mcu_addr; + /*! address of mcu_2_spdif script */ + int mxc_sdma_mcu_2_spdif_addr; + + /*! address of asrc_2_mcu script */ + int mxc_sdma_asrc_2_mcu_addr; + + /*! address of ext_mem_2_ipu script */ + int mxc_sdma_ext_mem_2_ipu_addr; + + /*! address of descrambler script */ + int mxc_sdma_descrambler_addr; + + /*! address of dptc_dvfs script */ + int mxc_sdma_dptc_dvfs_addr; + + int mxc_sdma_utra_addr; + + /*! address of peripheral ssi to mcu script */ + int mxc_sdma_ssiapp_2_mcu_addr; + /*! address of mcu to peripheral ssi script */ + int mxc_sdma_mcu_2_ssiapp_addr; + + /*! address of shared peripheral ssi to mcu script */ + int mxc_sdma_ssish_2_mcu_addr; + /*! address of mcu to shared peripheral ssi script */ + int mxc_sdma_mcu_2_ssish_addr; + + /*! address where ram code starts */ + int mxc_sdma_ram_code_start_addr; + /*! size of the ram code */ + int mxc_sdma_ram_code_size; + + /*! RAM image address */ + unsigned short *mxc_sdma_start_addr; +} sdma_script_start_addrs; + +/*! Structure to store the initialized dma_channel parameters */ +typedef struct mxc_sdma_channel_params { + /*! Channel type (static channel number or dynamic channel) */ + unsigned int channel_num; + /*! Channel priority [0x1(lowest) - 0x7(highest)] */ + unsigned int chnl_priority; + /*! Channel params */ + dma_channel_params chnl_params; +} mxc_sdma_channel_params_t; + +/*! Structure to store the initialized dma_channel extend parameters */ +typedef struct mxc_sdma_channel_ext_params { + /*! Channel type (static channel number or dynamic channel) */ + unsigned int channel_num; + /*! Channel priority [0x1(lowest) - 0x7(highest)] */ + unsigned int chnl_priority; + /*! Channel extend params */ + dma_channel_ext_params chnl_ext_params; +} mxc_sdma_channel_ext_params_t; + +/*! Private SDMA data structure */ +typedef struct mxc_dma_channel_private { + /*! ID of the buffer that was processed */ + unsigned int buf_tail; + /*! Tasklet for the channel */ + struct tasklet_struct chnl_tasklet; + /*! Flag indicates if interrupt is required after every BD transfer */ + int intr_after_every_bd; +} mxc_dma_channel_private_t; + +/*! + * Setup channel according to parameters. + * Must be called once after mxc_request_dma() + * + * @param channel channel number + * @param p channel parameters pointer + * @return 0 on success, error code on fail + */ +int mxc_dma_setup_channel(int channel, dma_channel_params *p); + +/*! + * Setup the channel priority. This can be used to change the default priority + * for the channel. + * + * @param channel channel number + * @param priority priority to be set for the channel + * + * @return 0 on success, error code on failure + */ +int mxc_dma_set_channel_priority(unsigned int channel, unsigned int priority); + +/*! + * Allocates dma channel. + * If channel's value is 0, then the function allocates a free channel + * dynamically and sets its value to channel. + * Else allocates requested channel if it is free. + * If the channel is busy or no free channels (in dynamic allocation) -EBUSY returned. + * + * @param channel pointer to channel number + * @param devicename device name + * @return 0 on success, error code on fail + */ +int mxc_request_dma(int *channel, const char *devicename); + +/*! + * Configures request parameters. Can be called multiple times after + * mxc_request_dma() and mxc_dma_setup_channel(). + * + * + * @param channel channel number + * @param p request parameters pointer + * @param bd_index index of buffer descriptor to set + * @return 0 on success, error code on fail + */ +/* int mxc_dma_set_config(int channel, dma_request_t *p, int bd_index); */ +int mxc_dma_set_config(int channel, dma_request_t *p, int bd_index); + +/*! + * Returns request parameters. + * + * @param channel channel number + * @param p request parameters pointer + * @param bd_index index of buffer descriptor to get + * @return 0 on success, error code on fail + */ +/* int mxc_dma_get_config(int channel, dma_request_t *p, int bd_index); */ +int mxc_dma_get_config(int channel, dma_request_t *p, int bd_index); + +/*! + * This function is used by MXC IPC's write_ex2. It passes the a pointer to the + * data control structure to iapi_write_ipcv2() + * + * @param channel SDMA channel number + * @param ctrl_ptr Data Control structure pointer + */ +int mxc_sdma_write_ipcv2(int channel, void *ctrl_ptr); + +/*! + * This function is used by MXC IPC's read_ex2. It passes the a pointer to the + * data control structure to iapi_read_ipcv2() + * + * @param channel SDMA channel number + * @param ctrl_ptr Data Control structure pointer + */ +int mxc_sdma_read_ipcv2(int channel, void *ctrl_ptr); + +/*! + * Starts dma channel. + * + * @param channel channel number + */ +int mxc_dma_start(int channel); + +/*! + * Stops dma channel. + * + * @param channel channel number + */ +int mxc_dma_stop(int channel); + +/*! + * Frees dma channel. + * + * @param channel channel number + */ +void mxc_free_dma(int channel); + +/*! + * Sets callback function. Used with standard dma api + * for supporting interrupts + * + * @param channel channel number + * @param callback callback function pointer + * @param arg argument for callback function + */ +void mxc_dma_set_callback(int channel, dma_callback_t callback, void *arg); + +/*! + * Allocates uncachable buffer. Uses hash table. + * + * @param size size of allocated buffer + * @return pointer to buffer + */ +void *sdma_malloc(size_t size); + +#ifdef CONFIG_SDMA_IRAM +/*! + * Allocates uncachable buffer from IRAM.. + * + * @param size size of allocated buffer + * @return pointer to buffer + */ +void *sdma_iram_malloc(size_t size); +#endif /*CONFIG_SDMA_IRAM */ + +/*! + * Frees uncachable buffer. Uses hash table. + */ +void sdma_free(void *buf); + +/*! + * Converts virtual to physical address. Uses hash table. + * + * @param buf virtual address pointer + * @return physical address value + */ +unsigned long sdma_virt_to_phys(void *buf); + +/*! + * Converts physical to virtual address. Uses hash table. + * + * @param buf physical address value + * @return virtual address pointer + */ +void *sdma_phys_to_virt(unsigned long buf); + +/*! + * Configures the BD_INTR bit on a buffer descriptor parameters. + * + * + * @param channel channel number + * @param bd_index index of buffer descriptor to set + * @param bd_intr flag to set or clear the BD_INTR bit + */ +void mxc_dma_set_bd_intr(int channel, int bd_index, int bd_intr); + +/*! + * Gets the BD_INTR bit on a buffer descriptor. + * + * + * @param channel channel number + * @param bd_index index of buffer descriptor to set + * + * @return returns the BD_INTR bit status + */ +int mxc_dma_get_bd_intr(int channel, int bd_index); + +/*! + * Stop the current transfer + * + * @param channel channel number + * @param buffer_number number of buffers (beginning with 0), + * whose done bits should be reset to 0 + */ +int mxc_dma_reset(int channel, int buffer_number); + +/*! + * This functions Returns the SDMA paramaters associated for a module + * + * @param channel_id the ID of the module requesting DMA + * @return returns the sdma parameters structure for the device + */ +mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t + channel_id); + +/*! + * This functions marks the SDMA channels that are statically allocated + * + * @param chnl the channel array used to store channel information + */ +void mxc_get_static_channels(mxc_dma_channel_t *chnl); + +/*! + * Initializes SDMA driver + */ +int __init sdma_init(void); + +#define DEFAULT_ERR 1 + +#endif diff --git a/arch/arm/plat-mxc/include/mach/sdram_autogating.h b/arch/arm/plat-mxc/include/mach/sdram_autogating.h new file mode 100644 index 000000000000..5dcc38178279 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdram_autogating.h @@ -0,0 +1,56 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver + */ + +/*! + * @file arch-mxc/sdram_autogating.h + * + * @brief This file contains the SDRAM autogating function prototypes + * + * + * @ingroup PM + */ + +#ifndef __ASM_ARCH_SDRAM_AUTOGATING_H__ +#define __ASM_ARCH_SDRAM_AUTOGATING_H__ + +#ifdef __KERNEL__ + +#include +#include +#include +#include + + +#ifdef CONFIG_ARCH_MX5 +extern void start_sdram_autogating(void); +extern void stop_sdram_autogating(void); +extern int sdram_autogating_active(void); +#else +static inline void start_sdram_autogating(void) +{} + +static inline void stop_sdram_autogating(void) +{} + +static inline int sdram_autogating_active(void) +{ + return 0; +} +#endif + +#endif /*__KERNEL__ */ +#endif /* __ASM_ARCH_MXC_DVFS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index ef00199568de..33fe6f8e5e7f 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -1,7 +1,7 @@ /* * Copyright (C) 1999 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,18 +24,9 @@ #include #include -static inline void arch_idle(void) -{ -#ifdef CONFIG_ARCH_MXC91231 - if (cpu_is_mxc91231()) { - /* Need this to set DSM low-power mode */ - mxc91231_prepare_idle(); - } -#endif - - cpu_do_idle(); -} +void arch_idle(void); void arch_reset(char mode, const char *cmd); +int mxs_reset_block(void __iomem *hwreg, int just_enable); #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 024416ed11cd..145e50495d65 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -1,6 +1,6 @@ /* * Copyright (C) 1999 ARM Limited - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,8 +26,10 @@ #define CLOCK_TICK_RATE 13300000 #elif defined CONFIG_ARCH_MX3 #define CLOCK_TICK_RATE 16625000 +#elif defined CONFIG_ARCH_MX37 +#define CLOCK_TICK_RATE 8000000 #elif defined CONFIG_ARCH_MX25 -#define CLOCK_TICK_RATE 16000000 +#define CLOCK_TICK_RATE 13300000 #elif defined CONFIG_ARCH_MX5 #define CLOCK_TICK_RATE 8000000 #elif defined CONFIG_ARCH_MXC91231 diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index b6d3d0fddc48..d3c46b167ece 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -25,6 +25,7 @@ #include +unsigned int system_rev; static unsigned long uart_base; #define UART(x) (*(volatile unsigned long *)(uart_base + (x))) @@ -67,6 +68,8 @@ static inline void flush(void) #define MX3X_UART1_BASE_ADDR 0x43F90000 #define MX3X_UART2_BASE_ADDR 0x43F94000 #define MX51_UART1_BASE_ADDR 0x73fbc000 +#define MX53_UART1_BASE_ADDR 0x53fbc000 +#define MX50_UART1_BASE_ADDR 0x53fbc000 static __inline__ void __arch_decomp_setup(unsigned long arch_id) { @@ -105,6 +108,14 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MX51_BABBAGE: uart_base = MX51_UART1_BASE_ADDR; break; + case MACH_TYPE_MX53_EVK: + case MACH_TYPE_MX53_ARD: + uart_base = MX53_UART1_BASE_ADDR; + break; + case MACH_TYPE_MX50_ARM2: + case MACH_TYPE_MX50_RDP: + uart_base = MX50_UART1_BASE_ADDR; + break; default: break; } diff --git a/arch/arm/plat-mxc/io.c b/arch/arm/plat-mxc/io.c new file mode 100644 index 000000000000..fd3d9dfca355 --- /dev/null +++ b/arch/arm/plat-mxc/io.c @@ -0,0 +1,42 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * mxc custom ioremap implementation. + */ + +#include +#include +#include +#include + +void *__iomem __mxc_ioremap(unsigned long cookie, size_t size, + unsigned int mtype) +{ +#ifdef CONFIG_ARCH_MX3 + if (cpu_is_mx3() && (mtype == MT_DEVICE) && (cookie < 0x80000000 && cookie != MX3x_L2CC_BASE_ADDR)) + mtype = MT_DEVICE_NONSHARED; +#endif + return __arm_ioremap(cookie, size, mtype); +} + +EXPORT_SYMBOL(__mxc_ioremap); + +void __mxc_iounmap(void __iomem *addr) +{ + extern void __iounmap(volatile void __iomem *addr); + + __iounmap(addr); +} + +EXPORT_SYMBOL(__mxc_iounmap); diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index b318c6a222d5..8734103bf790 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2011 Freescale Semiconductor, Inc. * Copyright (C) 2008 by Sascha Hauer * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, * @@ -31,6 +31,35 @@ static void __iomem *base; +/* + * Read a single pad in the iomuxer + */ +int mxc_iomux_v3_get_pad(struct pad_desc *pad) +{ + pad->mux_mode = __raw_readl(base + pad->mux_ctrl_ofs) & 0xFF; + pad->pad_ctrl = __raw_readl(base + pad->pad_ctrl_ofs) & 0x1FFFF; + pad->select_input = __raw_readl(base + pad->select_input_ofs) & 0x7; + + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_get_pad); + +/* + * Read multiple pads in the iomuxer + */ +int mxc_iomux_v3_get_multiple_pads(struct pad_desc *pad_list, unsigned count) +{ + struct pad_desc *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + mxc_iomux_v3_get_pad(p); + p++; + } + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_get_multiple_pads); /* * setups a single pad in the iomuxer */ @@ -65,6 +94,42 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) } EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); +int mxc_iomux_v3_setup_pad_ext(struct pad_cfg *pd) +{ + struct pad_desc *pad = &(pd->pd); + + if (pad->mux_ctrl_ofs) + __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); + + if (pad->select_input_ofs) + __raw_writel(pad->select_input, + base + pad->select_input_ofs); + + if (pd->pad_ctrl && pad->pad_ctrl_ofs) + __raw_writel(pd->pad_ctrl, base + pad->pad_ctrl_ofs); + else if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs) + __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs); + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_setup_pad_ext); + +int mxc_iomux_v3_setup_multiple_pads_ext(struct pad_cfg *pad_list, + unsigned count) +{ + struct pad_cfg *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = mxc_iomux_v3_setup_pad_ext(p); + if (ret) + return ret; + p++; + } + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads_ext); + void mxc_iomux_v3_init(void __iomem *iomux_v3_base) { base = iomux_v3_base; diff --git a/arch/arm/plat-mxc/iram.c b/arch/arm/plat-mxc/iram.c new file mode 100644 index 000000000000..c63b0a2a9a10 --- /dev/null +++ b/arch/arm/plat-mxc/iram.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include + +static unsigned long iram_phys_base; +static __iomem void *iram_virt_base; +static struct gen_pool *iram_pool; + +#define iram_phys_to_virt(p) (iram_virt_base + ((p) - iram_phys_base)) + +void *iram_alloc(unsigned int size, unsigned long *dma_addr) +{ + if (!iram_pool) + return NULL; + + *dma_addr = gen_pool_alloc(iram_pool, size); + pr_debug("iram alloc - %dB@0x%p\n", size, (void *)*dma_addr); + + WARN_ON(!*dma_addr); + if (!*dma_addr) + return NULL; + + return iram_phys_to_virt(*dma_addr); +} +EXPORT_SYMBOL(iram_alloc); + +void iram_free(unsigned long addr, unsigned int size) +{ + if (!iram_pool) + return; + + gen_pool_free(iram_pool, addr, size); +} +EXPORT_SYMBOL(iram_free); + +int __init iram_init(unsigned long base, unsigned long size) +{ + iram_phys_base = base; + + iram_pool = gen_pool_create(12, -1); + gen_pool_add(iram_pool, base, size, -1); + iram_virt_base = ioremap(iram_phys_base, size); + + pr_info("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base); + return 0; +} diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 778ddfe57d89..91a862933541 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -46,6 +47,11 @@ void __iomem *avic_base; +#define IRQ_BIT(irq) (1 << (irq)) + +static uint32_t saved_wakeup_low, saved_wakeup_high; +static uint32_t suspend_wakeup_low, suspend_wakeup_high; + int imx_irq_set_priority(unsigned char irq, unsigned char prio) { #ifdef CONFIG_MXC_IRQ_PRIOR @@ -102,12 +108,121 @@ static void mxc_unmask_irq(unsigned int irq) __raw_writel(irq, avic_base + AVIC_INTENNUM); } +/*! + * Set interrupt number "irq" in the AVIC as a wake-up source. + * + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * disble as wake-up if equal to zero + * + * @return This function returns 0 on success. + */ +static int mxc_set_wake_irq(unsigned int irq, unsigned int enable) +{ + uint32_t *wakeup_intr; + uint32_t irq_bit; + + if (irq < 32) { + wakeup_intr = &suspend_wakeup_low; + irq_bit = IRQ_BIT(irq); + } else { + wakeup_intr = &suspend_wakeup_high; + irq_bit = IRQ_BIT(irq - 32); + } + + if (enable) { + *wakeup_intr |= irq_bit; + } else { + *wakeup_intr &= ~irq_bit; + } + + return 0; +} + static struct irq_chip mxc_avic_chip = { .ack = mxc_mask_irq, .mask = mxc_mask_irq, .unmask = mxc_unmask_irq, + .set_wake = mxc_set_wake_irq, +}; + +#ifdef CONFIG_PM +/*! + * This function puts the AVIC in low-power mode/state. + * All the interrupts that are enabled are first saved. + * Only those interrupts which registers as a wake source by calling + * enable_irq_wake are enabled. All other interrupts are disabled. + * + * @param dev the system device structure used to give information + * on AVIC to suspend + * @param mesg the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_avic_suspend(struct sys_device *dev, pm_message_t mesg) +{ + saved_wakeup_high = __raw_readl(avic_base + AVIC_INTENABLEH); + saved_wakeup_low = __raw_readl(avic_base + AVIC_INTENABLEL); + + __raw_writel(suspend_wakeup_high, avic_base + AVIC_INTENABLEH); + __raw_writel(suspend_wakeup_low, avic_base + AVIC_INTENABLEL); + + return 0; +} + +/*! + * This function brings the AVIC back from low-power state. + * All the interrupts enabled before suspension are re-enabled from + * the saved information. + * + * @param dev the system device structure used to give information + * on AVIC to resume + * + * @return The function always returns 0. + */ +static int mxc_avic_resume(struct sys_device *dev) +{ + __raw_writel(saved_wakeup_high, avic_base + AVIC_INTENABLEH); + __raw_writel(saved_wakeup_low, avic_base + AVIC_INTENABLEL); + + return 0; +} + +#else +#define mxc_avic_suspend NULL +#define mxc_avic_resume NULL +#endif /* CONFIG_PM */ +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct sysdev_class mxc_avic_sysclass = { + .name = "mxc_irq", + .suspend = mxc_avic_suspend, + .resume = mxc_avic_resume, +}; + +/*! + * This structure represents AVIC as a system device. + * System devices follow a slightly different driver model. + * They don't need to do dynammic driver binding, can't be probed, + * and don't reside on any type of peripheral bus. + * So, it is represented and treated a little differently. + */ +static struct sys_device mxc_avic_device = { + .id = 0, + .cls = &mxc_avic_sysclass, }; +/* + * This function is used to get the AVIC Lo and Hi interrupts + * that are enabled as wake up sources to wake up the core from suspend + */ +void mxc_get_wake_irq(u32 *wake_src[]) +{ + *wake_src[0] = __raw_readl(avic_base + AVIC_INTENABLEL); + *wake_src[1] = __raw_readl(avic_base + AVIC_INTENABLEH); +} + /* * This function initializes the AVIC hardware and disables all the * interrupts. It registers the interrupt enable and disable functions @@ -150,6 +265,33 @@ void __init mxc_init_irq(void __iomem *irqbase) init_FIQ(); #endif + if (MXC_INT_FORCE >= 32) + __raw_writel(1 << (MXC_INT_FORCE & 31), avic_base + AVIC_INTFRCH); + else if (MXC_INT_FORCE >= 0) + __raw_writel(1 << MXC_INT_FORCE, avic_base + AVIC_INTFRCL); + printk(KERN_INFO "MXC IRQ initialized\n"); } +/*! + * This function registers AVIC hardware as a system device. + * System devices will only be suspended with interrupts disabled, and + * after all other devices have been suspended. On resume, they will be + * resumed before any other devices, and also with interrupts disabled. + * + * @return This function returns 0 on success. + */ +static int __init mxc_avic_sysinit(void) +{ + int ret = 0; + + ret = sysdev_class_register(&mxc_avic_sysclass); + if (ret == 0) { + ret = sysdev_register(&mxc_avic_device); + } + + return ret; +} + +arch_initcall(mxc_avic_sysinit); + diff --git a/arch/arm/plat-mxc/isp1301xc.c b/arch/arm/plat-mxc/isp1301xc.c new file mode 100644 index 000000000000..6a5b9dae2134 --- /dev/null +++ b/arch/arm/plat-mxc/isp1301xc.c @@ -0,0 +1,290 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * ISP1301 register addresses,all register of ISP1301 + * is one-byte length register + */ + +/* ISP1301: I2C device address */ +#define ISP1301_DEV_ADDR 0x2D + +/* ISP 1301 register set*/ +#define ISP1301_MODE_REG1_SET 0x04 +#define ISP1301_MODE_REG1_CLR 0x05 + +#define ISP1301_CTRL_REG1_SET 0x06 +#define ISP1301_CTRL_REG1_CLR 0x07 + +#define ISP1301_INT_SRC_REG 0x08 +#define ISP1301_INT_LAT_REG_SET 0x0a +#define ISP1301_INT_LAT_REG_CLR 0x0b +#define ISP1301_INT_FALSE_REG_SET 0x0c +#define ISP1301_INT_FALSE_REG_CLR 0x0d +#define ISP1301_INT_TRUE_REG_SET 0x0e +#define ISP1301_INT_TRUE_REG_CLR 0x0f + +#define ISP1301_CTRL_REG2_SET 0x10 +#define ISP1301_CTRL_REG2_CLR 0x11 + +#define ISP1301_MODE_REG2_SET 0x12 +#define ISP1301_MODE_REG2_CLR 0x13 + +#define ISP1301_BCD_DEV_REG0 0x14 +#define ISP1301_BCD_DEV_REG1 0x15 + +/* OTG Control register bit description */ +#define DP_PULLUP 0x01 +#define DM_PULLUP 0x02 +#define DP_PULLDOWN 0x04 +#define DM_PULLDOWN 0x08 +#define ID_PULLDOWN 0x10 +#define VBUS_DRV 0x20 +#define VBUS_DISCHRG 0x40 +#define VBUS_CHRG 0x80 + +/* Mode Control 1 register bit description */ +#define SPEED_REG 0x01 +#define SUSPEND_REG 0x02 +#define DAT_SE0 0x04 +#define TRANSP_EN 0x08 +#define BDIS_ACON_EN 0x10 +#define OE_INT_EN 0x20 +#define UART_EN 0x40 + +/* Mode Control 2 register bit description */ +#define SPD_SUSP_CTRL 0x02 +#define BI_DI 0x04 + +static int isp1301_attach(struct i2c_adapter *adapter); +static int isp1301_detach(struct i2c_client *client); + +static struct i2c_driver isp1301_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "isp1301 Client", + }, + .attach_adapter = isp1301_attach, + .detach_client = isp1301_detach, +}; + +static struct i2c_client isp1301_i2c_client = { + .name = "isp1301 I2C dev", + .addr = ISP1301_DEV_ADDR, + .driver = &isp1301_i2c_driver, +}; + +static unsigned short normal_i2c[] = { ISP1301_DEV_ADDR, I2C_CLIENT_END }; + +/* Magic definition of all other variables and things */ +I2C_CLIENT_INSMOD; + +static int isp1301_detect_client(struct i2c_adapter *adapter, int address, + int kind) +{ + isp1301_i2c_client.adapter = adapter; + if (i2c_attach_client(&isp1301_i2c_client)) { + isp1301_i2c_client.adapter = NULL; + printk(KERN_ERR "isp1301_attach: i2c_attach_client failed\n"); + return -1; + } + + printk(KERN_INFO "isp1301 Detected\n"); + return 0; +} + +/*! + * isp1301 I2C attach function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int isp1301_attach(struct i2c_adapter *adapter) +{ + return i2c_probe(adapter, &addr_data, &isp1301_detect_client); +} + +/*! + * isp1301 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int isp1301_detach(struct i2c_client *client) +{ + int err; + + if (!isp1301_i2c_client.adapter) + return -1; + + err = i2c_detach_client(&isp1301_i2c_client); + isp1301_i2c_client.adapter = NULL; + + return err; +} + +static void isp1301_init(struct fsl_xcvr_ops *this) +{ + pr_debug("%s\n", __FUNCTION__); + + i2c_add_driver(&isp1301_i2c_driver); +} + +static void isp1301_uninit(struct fsl_xcvr_ops *this) +{ + /* DDD do this for host only:*/ + /* disable OTG VBUS */ + i2c_del_driver(&isp1301_i2c_driver); +} + +/* Write ISP1301 register*/ +static inline void isp1301_write_reg(char reg, char data) +{ + i2c_smbus_write_byte_data(&isp1301_i2c_client, reg, data); +} + +/* read ISP1301 register*/ +static inline char isp1301_read_reg(char reg) +{ + return i2c_smbus_read_byte_data(&isp1301_i2c_client, reg); +} + +/* set ISP1301 as USB host*/ +static inline void isp1301_set_serial_host(void) +{ + pr_debug("%s\n", __FUNCTION__); + + isp1301_write_reg(ISP1301_MODE_REG2_CLR, 0xFF); +#if defined(CONFIG_MXC_USB_SB3) || defined(CONFIG_MXC_USB_DB4) + isp1301_write_reg(ISP1301_MODE_REG2_SET, SPD_SUSP_CTRL | BI_DI); +#else + isp1301_write_reg(ISP1301_MODE_REG2_SET, SPD_SUSP_CTRL); +#endif + + isp1301_write_reg(ISP1301_MODE_REG1_CLR, 0xFF); +#if defined(CONFIG_MXC_USB_SB3) || defined(CONFIG_MXC_USB_SU6) + isp1301_write_reg(ISP1301_MODE_REG1_SET, DAT_SE0 | SPEED_REG); +#else + isp1301_write_reg(ISP1301_MODE_REG1_SET, SPEED_REG); +#endif + + /* configure transceiver for host mode */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, + (VBUS_DRV | DP_PULLDOWN | DM_PULLDOWN)); +} + +/* set ISP1301 as USB device */ +static inline void isp1301_set_serial_dev(void) +{ + pr_debug("%s\n", __FUNCTION__); + + isp1301_write_reg(ISP1301_MODE_REG2_CLR, 0xFF); +#if defined(CONFIG_MXC_USB_SB3) || defined(CONFIG_MXC_USB_DB4) + isp1301_write_reg(ISP1301_MODE_REG2_SET, SPD_SUSP_CTRL | BI_DI); +#else + isp1301_write_reg(ISP1301_MODE_REG2_SET, SPD_SUSP_CTRL); +#endif + + isp1301_write_reg(ISP1301_MODE_REG1_CLR, 0xFF); +#if defined(CONFIG_MXC_USB_SB3) || defined(CONFIG_MXC_USB_SU6) + isp1301_write_reg(ISP1301_MODE_REG1_SET, DAT_SE0 | SPEED_REG); +#else + isp1301_write_reg(ISP1301_MODE_REG1_SET, SPEED_REG); +#endif + + /* FS mode, DP pull down, DM pull down */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, + (DP_PULLDOWN | DM_PULLDOWN | DP_PULLUP)); +} + +static void isp1301_set_vbus_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + pr_debug("%s(on=%d)\n", __FUNCTION__, on); + if (on) { + /* disable D+ pull-up */ + isp1301_write_reg(ISP1301_CTRL_REG1_CLR, DP_PULLUP); + /* enable D+ pull-down */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, DP_PULLDOWN); + /* turn on Vbus */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, VBUS_DRV); + } else { + /* D+ pull up, D- pull down */ + isp1301_write_reg(ISP1301_CTRL_REG1_SET, + (DP_PULLUP | DM_PULLDOWN)); + /* disable D- pull up, disable D+ pull down */ + isp1301_write_reg(ISP1301_CTRL_REG1_CLR, + (DM_PULLUP | DP_PULLDOWN)); + } +} + +/* + * Enable or disable the D+ pullup. + */ +static void isp1301_pullup(int on) +{ + pr_debug("%s(%d)\n", __func__, on); + + if (on) + isp1301_write_reg(ISP1301_CTRL_REG1_SET, DP_PULLUP); + else + isp1301_write_reg(ISP1301_CTRL_REG1_CLR, DP_PULLUP); +} + +static struct fsl_xcvr_ops isp1301_ops_otg = { + .name = "isp1301", + .xcvr_type = PORTSC_PTS_SERIAL, + .init = isp1301_init, + .uninit = isp1301_uninit, + .set_host = isp1301_set_serial_host, + .set_device = isp1301_set_serial_dev, + .set_vbus_power = isp1301_set_vbus_power, + .pullup = isp1301_pullup, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init isp1301xc_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&isp1301_ops_otg); + + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit isp1301xc_exit(void) +{ + fsl_usb_xcvr_unregister(&isp1301_ops_otg); +} + +subsys_initcall(isp1301xc_init); +module_exit(isp1301xc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("isp1301"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/isp1504xc.c b/arch/arm/plat-mxc/isp1504xc.c new file mode 100644 index 000000000000..98c5e7326b59 --- /dev/null +++ b/arch/arm/plat-mxc/isp1504xc.c @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* ISP 1504 register addresses */ +#define ISP1504_VID_LOW 0x00 /* Vendor ID low */ +#define ISP1504_VID_HIGH 0x01 /* Vendor ID high */ +#define ISP1504_PID_LOW 0x02 /* Product ID low */ +#define ISP1504_PID_HIGH 0x03 /* Product ID high */ +#define ISP1504_FUNC 0x04 /* Function Control */ +#define ISP1504_ITFCTL 0x07 /* Interface Control */ +#define ISP1504_OTGCTL 0x0A /* OTG Control */ + +/* add to above register address to access Set/Clear functions */ +#define ISP1504_REG_SET 0x01 +#define ISP1504_REG_CLEAR 0x02 + +/* 1504 OTG Control Register bits */ +#define USE_EXT_VBUS_IND (1 << 7) /* Use ext. Vbus indicator */ +#define DRV_VBUS_EXT (1 << 6) /* Drive Vbus external */ +#define DRV_VBUS (1 << 5) /* Drive Vbus */ +#define CHRG_VBUS (1 << 4) /* Charge Vbus */ +#define DISCHRG_VBUS (1 << 3) /* Discharge Vbus */ +#define DM_PULL_DOWN (1 << 2) /* enable DM Pull Down */ +#define DP_PULL_DOWN (1 << 1) /* enable DP Pull Down */ +#define ID_PULL_UP (1 << 0) /* enable ID Pull Up */ + +/* 1504 OTG Function Control Register bits */ +#define SUSPENDM (1 << 6) /* places the PHY into + low-power mode */ +#define DRV_RESET (1 << 5) /* Active HIGH transceiver + reset */ + +/*! + * read ULPI register 'reg' thru VIEWPORT register 'view' + * + * @param reg register to read + * @param view the ULPI VIEWPORT register address + * @return return isp1504 register value + */ +static u8 isp1504_read(int reg, volatile u32 *view) +{ + u32 data; + + /* make sure interface is running */ + if (!(__raw_readl(view) && ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + do { /* wait for wakeup */ + data = __raw_readl(view); + } while (data & ULPIVW_WU); + } + + /* read the register */ + __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view); + + do { /* wait for completion */ + data = __raw_readl(view); + } while (data & ULPIVW_RUN); + + return (u8) (data >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; +} + +/*! + * set bits into OTG ISP1504 register 'reg' thru VIEWPORT register 'view' + * + * @param bits set value + * @param reg which register + * @param view the ULPI VIEWPORT register address + */ +static void isp1504_set(u8 bits, int reg, volatile u32 *view) +{ + u32 data; + + /* make sure interface is running */ + if (!(__raw_readl(view) && ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + do { /* wait for wakeup */ + data = __raw_readl(view); + } while (data & ULPIVW_WU); + } + + __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | + ((reg + ISP1504_REG_SET) << ULPIVW_ADDR_SHIFT) | + ((bits & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), + view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + +/*! + * clear bits in OTG ISP1504 register 'reg' thru VIEWPORT register 'view' + * + * @param bits bits to clear + * @param reg in this register + * @param view the ULPI VIEWPORT register address + */ +static void isp1504_clear(u8 bits, int reg, volatile u32 *view) +{ + __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | + ((reg + ISP1504_REG_CLEAR) << ULPIVW_ADDR_SHIFT) | + ((bits & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), + view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + +extern __weak int gpio_usbotg_hs_active(void); + +static void isp1508_fix(u32 *view) +{ + if (!machine_is_mx31_3ds()) + gpio_usbotg_hs_active(); + + /* Set bits IND_PASS_THRU and IND_COMPL */ + isp1504_set(0x60, ISP1504_ITFCTL, view); + + /* Set bit USE_EXT_VBUS_IND */ + isp1504_set(USE_EXT_VBUS_IND, ISP1504_OTGCTL, view); +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +static void isp1504_set_vbus_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + u32 *view = pdata->regs + ULPIVW_OFF; + + pr_debug("real %s(on=%d) view=0x%p\n", __FUNCTION__, on, view); + + pr_debug("ULPI Vendor ID 0x%x Product ID 0x%x\n", + (isp1504_read(ISP1504_VID_HIGH, view) << 8) | + isp1504_read(ISP1504_VID_LOW, view), + (isp1504_read(ISP1504_PID_HIGH, view) << 8) | + isp1504_read(ISP1504_PID_LOW, view)); + + pr_debug("OTG Control before=0x%x\n", + isp1504_read(ISP1504_OTGCTL, view)); + + if (on) { + isp1504_set(DRV_VBUS_EXT | /* enable external Vbus */ + DRV_VBUS | /* enable internal Vbus */ + USE_EXT_VBUS_IND | /* use external indicator */ + CHRG_VBUS, /* charge Vbus */ + ISP1504_OTGCTL, view); + + } else { + isp1508_fix(view); + + isp1504_clear(DRV_VBUS_EXT | /* disable external Vbus */ + DRV_VBUS, /* disable internal Vbus */ + ISP1504_OTGCTL, view); + + isp1504_set(USE_EXT_VBUS_IND | /* use external indicator */ + DISCHRG_VBUS, /* discharge Vbus */ + ISP1504_OTGCTL, view); + } + + pr_debug("OTG Control after = 0x%x\n", + isp1504_read(ISP1504_OTGCTL, view)); +} + +/*! + * set remote wakeup + * + * @param view viewport register + */ +static void isp1504_set_remote_wakeup(u32 *view) +{ + __raw_writel(~ULPIVW_WRITE & __raw_readl(view), view); + __raw_writel((1 << ULPIVW_PORT_SHIFT) | __raw_readl(view), view); + __raw_writel(ULPIVW_RUN | __raw_readl(view), view); + + while (__raw_readl(view) & ULPIVW_RUN) /* wait for completion */ + continue; +} + +static void isp1504_init(struct fsl_xcvr_ops *this) +{ + pr_debug("%s:\n", __FUNCTION__); +} + +static void isp1504_uninit(struct fsl_xcvr_ops *this) +{ + pr_debug("%s:\n", __FUNCTION__); +} + +static void isp1504_suspend(struct fsl_xcvr_ops *this) +{ + pr_debug("%s\n", __func__); + + /* send suspend command */ + isp1504_clear(SUSPENDM, ISP1504_FUNC, &UOG_ULPIVIEW); + pr_debug("%s.\n", __func__); +} + +/*! + * Set the 1504 transceiver to the proper mode for testing purposes. + * + * @param view the ULPI VIEWPORT register address + * @param test_mode Set the 1504 transceiver to disable bit stuffing and NRZI + */ + static void isp1504_set_test_mode(u32 *view, enum usb_test_mode test_mode) +{ + if (test_mode == USB_TEST_J || test_mode == USB_TEST_K) { + printk(KERN_INFO "udc: disable bit stuffing and NRZI\n"); + /* Disable bit-stuffing and NRZI encoding. */ + isp1504_set(0x10, 0x04, view); + } +} + +static struct fsl_xcvr_ops isp1504_ops = { + .name = "isp1504", + .xcvr_type = PORTSC_PTS_ULPI, + .init = isp1504_init, + .uninit = isp1504_uninit, + .suspend = isp1504_suspend, + .set_vbus_power = isp1504_set_vbus_power, + .set_remote_wakeup = isp1504_set_remote_wakeup, + .set_test_mode = isp1504_set_test_mode, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); +extern int fsl_usb_xcvr_suspend(struct fsl_xcvr_ops *xcvr_ops); + +static int __init isp1504xc_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&isp1504_ops); + + /* suspend isp1504 */ + if (fsl_usb_xcvr_suspend(&isp1504_ops)) + pr_debug("%s: failed to suspend isp1504\n", __func__); + + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit isp1504xc_exit(void) +{ + fsl_usb_xcvr_unregister(&isp1504_ops); +} + +subsys_initcall(isp1504xc_init); +module_exit(isp1504xc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("isp1504 xcvr driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/mc13783_xc.c b/arch/arm/plat-mxc/mc13783_xc.c new file mode 100644 index 000000000000..9c41fbf5a8a8 --- /dev/null +++ b/arch/arm/plat-mxc/mc13783_xc.c @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Events to be passed to the thread */ +#define MC13783_USB_VBUS_ON 0x0001 +#define MC13783_USB_VBUS_OFF 0x0002 +#define MC13783_USB_DETECT_MINI_A 0x0004 +#define MC13783_USB_DETECT_MINI_B 0x0008 + +extern void otg_set_serial_peripheral(void); +extern void otg_set_serial_host(void); + +static unsigned int p_event; +static PMIC_CONVITY_EVENTS g_event; +static PMIC_CONVITY_HANDLE pmic_handle = (PMIC_CONVITY_HANDLE) NULL; + +static void xc_workqueue_handler(struct work_struct *work); + +DECLARE_WORK(xc_work, xc_workqueue_handler); + +DECLARE_MUTEX(pmic_mx); + +static void pmic_event_handler(const PMIC_CONVITY_EVENTS event) +{ + if (event & USB_DETECT_4V4_RISE) + pr_debug("%s: USB_DETECT_4V4_RISE\n", __func__); + + if (event & USB_DETECT_4V4_FALL) + pr_debug("%s: USB_DETECT_4V4_FALL\n", __func__); + + if (event & USB_DETECT_2V0_RISE) + pr_debug("%s: USB_DETECT_2V0_RISE\n", __func__); + + if (event & USB_DETECT_2V0_FALL) + pr_debug("%s: USB_DETECT_2V0_FALL\n", __func__); + + if (event & USB_DETECT_0V8_RISE) + pr_debug("%s: USB_DETECT_0V8_RISE\n", __func__); + + if (event & USB_DETECT_0V8_FALL) + pr_debug("%s: USB_DETECT_0V8_FALL\n", __func__); + + if (event & USB_DETECT_MINI_B) { + pr_debug("%s: USB_DETECT_MINI_B\n", __func__); + otg_set_serial_peripheral(); + g_event = USB_DETECT_MINI_B; + p_event = MC13783_USB_DETECT_MINI_B; + schedule_work(&xc_work); + } + if (event & USB_DETECT_MINI_A) { + pr_debug("%s: USB_DETECT_MINI_A\n", __func__); + otg_set_serial_host(); + g_event = USB_DETECT_MINI_A; + p_event = MC13783_USB_DETECT_MINI_A; + schedule_work(&xc_work); + } + + /* + * Mini-B cable insertion/removal does not generate cable-detect + * event, so we rely on the VBUS changes to identify a mini-b cable + * connect. This logic is only used if mini-b is the first cable that + * is connected after bootup. At all other times, removal of mini-a + * cable is used to initialize peripheral. + */ + if (g_event != USB_DETECT_MINI_A && g_event != USB_DETECT_MINI_B) { + if ((event & USB_DETECT_0V8_RISE) && + (event & USB_DETECT_2V0_RISE) && + (event & USB_DETECT_4V4_RISE)) { + otg_set_serial_peripheral(); + g_event = USB_DETECT_MINI_B; + p_event = MC13783_USB_DETECT_MINI_B; + schedule_work(&xc_work); + } + } +} + +static int usb_pmic_mod_init(void) +{ + PMIC_STATUS rs = PMIC_ERROR; + + init_MUTEX_LOCKED(&pmic_mx); + + rs = pmic_convity_open(&pmic_handle, USB); + if (rs != PMIC_SUCCESS) { + printk(KERN_ERR "pmic_convity_open returned error %d\n", rs); + return rs; + } + + rs = pmic_convity_set_callback(pmic_handle, pmic_event_handler, + USB_DETECT_4V4_RISE | USB_DETECT_4V4_FALL + | USB_DETECT_2V0_RISE | + USB_DETECT_2V0_FALL | USB_DETECT_0V8_RISE + | USB_DETECT_0V8_FALL | USB_DETECT_MINI_A + | USB_DETECT_MINI_B); + + if (rs != PMIC_SUCCESS) { + printk(KERN_ERR + "pmic_convity_set_callback returned error %d\n", rs); + return rs; + } + + return rs; +} + +static void usb_pmic_mod_exit(void) +{ + PMIC_STATUS rs; + + pmic_convity_set_mode(pmic_handle, RS232_1); + pmic_convity_clear_callback(pmic_handle); + + if (pmic_handle != (PMIC_CONVITY_HANDLE) NULL) { + rs = pmic_convity_close(pmic_handle); + if (rs != PMIC_SUCCESS) { + printk(KERN_ERR + "pmic_convity_close() returned error %d", rs); + } else { + pmic_handle = (PMIC_CONVITY_HANDLE) NULL; + } + } +} + +static inline void mc13783_set_host(void) +{ + PMIC_STATUS rs = PMIC_ERROR; + + rs = pmic_convity_usb_otg_clear_config(pmic_handle, USB_OTG_SE0CONN); + rs |= pmic_convity_usb_otg_clear_config(pmic_handle, USB_PU); + + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_UDM_PD); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_UDP_PD); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "mc13783_set_host failed\n"); + +} + +static inline void mc13783_set_peripheral(void) +{ + PMIC_STATUS rs = PMIC_ERROR; + + rs = pmic_convity_usb_otg_clear_config(pmic_handle, USB_UDM_PD); + rs |= pmic_convity_usb_otg_clear_config(pmic_handle, USB_UDP_PD); + + rs |= pmic_convity_usb_set_speed(pmic_handle, USB_FULL_SPEED); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_OTG_SE0CONN); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_PU); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "mc13783_set_peripheral failed\n"); +} + +void mc13783_set_vbus_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + if (on) { + p_event = MC13783_USB_VBUS_ON; + schedule_work(&xc_work); + } +} + +static struct fsl_xcvr_ops mc13783_ops_otg = { + .name = "mc13783", + .xcvr_type = PORTSC_PTS_SERIAL, + .set_host = mc13783_set_host, + .set_device = mc13783_set_peripheral, + .set_vbus_power = mc13783_set_vbus_power, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static void xc_workqueue_handler(struct work_struct *work) +{ + PMIC_STATUS rs = PMIC_ERROR; + + down(&pmic_mx); + + switch (p_event) { + case MC13783_USB_VBUS_OFF: + mc13783_set_peripheral(); + break; + case MC13783_USB_VBUS_ON: + mc13783_set_host(); + break; + case MC13783_USB_DETECT_MINI_B: + rs = pmic_convity_set_output(pmic_handle, true, false); + rs |= + pmic_convity_usb_otg_clear_config(pmic_handle, + USB_VBUS_CURRENT_LIMIT_LOW_30MS); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "MC13783_USB_VBUS_OFF failed\n"); + break; + case MC13783_USB_DETECT_MINI_A: + rs = pmic_convity_set_output(pmic_handle, true, true); + rs |= + pmic_convity_usb_otg_set_config(pmic_handle, + USB_VBUS_CURRENT_LIMIT_LOW_30MS); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "MC13783_USB_VBUS_ON failed\n"); + break; + default: + break; + } + up(&pmic_mx); +} + +int mc13783xc_init(void) +{ + PMIC_STATUS rs = PMIC_ERROR; + +#if defined(CONFIG_MXC_USB_SB3) + int xc_mode = USB_SINGLE_ENDED_BIDIR; +#elif defined(CONFIG_MXC_USB_SU6) + int xc_mode = USB_SINGLE_ENDED_UNIDIR; +#elif defined(CONFIG_MXC_USB_DB4) + int xc_mode = USB_DIFFERENTIAL_BIDIR; +#else + int xc_mode = USB_DIFFERENTIAL_UNIDIR; +#endif + + rs = usb_pmic_mod_init(); + if (rs != PMIC_SUCCESS) { + usb_pmic_mod_exit(); + printk(KERN_ERR "usb_pmic_mod_init failed\n"); + return rs; + } + + rs = pmic_convity_usb_set_xcvr(pmic_handle, xc_mode); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_OTG_SE0CONN); + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USBXCVREN); + rs |= pmic_convity_set_output(pmic_handle, false, true); + + rs |= pmic_convity_usb_otg_set_config(pmic_handle, USB_PULL_OVERRIDE); + rs |= pmic_convity_usb_otg_clear_config(pmic_handle, USB_USBCNTRL); + rs |= pmic_convity_usb_otg_clear_config(pmic_handle, USB_DP150K_PU); + + if (rs != PMIC_SUCCESS) + printk(KERN_ERR "pmic configuration failed\n"); + + fsl_usb_xcvr_register(&mc13783_ops_otg); + + mc13783_set_peripheral(); + + return rs; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +void mc13783xc_uninit(void) +{ + /* Clear stuff from init */ + pmic_convity_usb_otg_clear_config(pmic_handle, USB_OTG_SE0CONN); + pmic_convity_usb_otg_clear_config(pmic_handle, USBXCVREN); + pmic_convity_set_output(pmic_handle, false, false); + pmic_convity_usb_otg_clear_config(pmic_handle, USB_PULL_OVERRIDE); + + /* Clear host mode */ + pmic_convity_usb_otg_clear_config(pmic_handle, USB_UDP_PD); + pmic_convity_usb_otg_clear_config(pmic_handle, USB_UDM_PD); + + /* Clear peripheral mode */ + pmic_convity_usb_otg_clear_config(pmic_handle, USB_PU); + + /* Vbus off */ + pmic_convity_set_output(pmic_handle, true, false); + pmic_convity_usb_otg_clear_config(pmic_handle, + USB_VBUS_CURRENT_LIMIT_LOW_30MS); + + usb_pmic_mod_exit(); + + fsl_usb_xcvr_unregister(&mc13783_ops_otg); +} + +subsys_initcall(mc13783xc_init); +module_exit(mc13783xc_uninit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("mc13783xc"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index c36f2630ed93..17f36c10c5c3 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -6,6 +6,7 @@ * published by the Free Software Foundation. * * Derived from pxa PWM driver by eric miao + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ #include @@ -16,6 +17,7 @@ #include #include #include +#include #include @@ -36,7 +38,12 @@ #define MX3_PWMCR_CLKSRC_IPG (1 << 16) #define MX3_PWMCR_EN (1 << 0) - +#define MX3_PWMCR_STOPEN (1 << 25) +#define MX3_PWMCR_DOZEEN (1 << 24) +#define MX3_PWMCR_WAITEN (1 << 23) +#define MX3_PWMCR_DBGEN (1 << 22) +#define MX3_PWMCR_CLKSRC_IPG (1 << 16) +#define MX3_PWMCR_CLKSRC_IPG_32k (3 << 16) struct pwm_device { struct list_head node; @@ -50,6 +57,9 @@ struct pwm_device { unsigned int use_count; unsigned int pwm_id; + int pwmo_invert; + void (*enable_pwm_pad)(void); + void (*disable_pwm_pad)(void); }; int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) @@ -57,11 +67,14 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; - if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) { + if (!(cpu_is_mx1() || cpu_is_mx21())) { unsigned long long c; unsigned long period_cycles, duty_cycles, prescale; u32 cr; + if (pwm->pwmo_invert) + duty_ns = period_ns - duty_ns; + c = clk_get_rate(pwm->clk); c = c * period_ns; do_div(c, 1000000000); @@ -77,7 +90,9 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); writel(period_cycles, pwm->mmio_base + MX3_PWMPR); - cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN; + cr = MX3_PWMCR_PRESCALER(prescale) | + MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | + MX3_PWMCR_WAITEN | MX3_PWMCR_DBGEN; if (cpu_is_mx25()) cr |= MX3_PWMCR_CLKSRC_IPG; @@ -103,6 +118,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) * (/2 .. /16). */ u32 max = readl(pwm->mmio_base + MX1_PWMP); + if (pwm->pwmo_invert) + duty_ns = period_ns - duty_ns; u32 p = max * duty_ns / period_ns; writel(max - p, pwm->mmio_base + MX1_PWMS); } else { @@ -115,6 +132,7 @@ EXPORT_SYMBOL(pwm_config); int pwm_enable(struct pwm_device *pwm) { + unsigned long reg; int rc = 0; if (!pwm->clk_enabled) { @@ -122,12 +140,23 @@ int pwm_enable(struct pwm_device *pwm) if (!rc) pwm->clk_enabled = 1; } + + reg = readl(pwm->mmio_base + MX3_PWMCR); + reg |= MX3_PWMCR_EN; + writel(reg, pwm->mmio_base + MX3_PWMCR); + + if (pwm->enable_pwm_pad) + pwm->enable_pwm_pad(); + return rc; } EXPORT_SYMBOL(pwm_enable); void pwm_disable(struct pwm_device *pwm) { + if (pwm->disable_pwm_pad) + pwm->disable_pwm_pad(); + writel(0, pwm->mmio_base + MX3_PWMCR); if (pwm->clk_enabled) { @@ -186,6 +215,7 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) { struct pwm_device *pwm; struct resource *r; + struct mxc_pwm_platform_data *plat_data = pdev->dev.platform_data; int ret = 0; pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); @@ -206,6 +236,11 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev) pwm->use_count = 0; pwm->pwm_id = pdev->id; pwm->pdev = pdev; + if (plat_data != NULL) { + pwm->pwmo_invert = plat_data->pwmo_invert; + pwm->enable_pwm_pad = plat_data->enable_pwm_pad; + pwm->disable_pwm_pad = plat_data->disable_pwm_pad; + } r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (r == NULL) { diff --git a/arch/arm/plat-mxc/sdma/Makefile b/arch/arm/plat-mxc/sdma/Makefile new file mode 100644 index 000000000000..59f94b2da7d0 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/Makefile @@ -0,0 +1,18 @@ +ifneq ($(KBUILD_SRC),) +ccflags-y += -I$(KBUILD_SRC)/arch/arm/plat-mxc/sdma/iapi/include \ + -I$(KBUILD_SRC)/include/linux \ + -DMCU -DOS=LINUX \ + -DL_I_T_T_L_E_ENDIAN=0 -DB_I_G_ENDIAN=1 \ + -DENDIANNESS=L_I_T_T_L_E_ENDIAN +else +ccflags-y += -Iarch/arm/plat-mxc/sdma/iapi/include \ + -Iinclude/linux \ + -DMCU -DOS=LINUX \ + -DL_I_T_T_L_E_ENDIAN=0 -DB_I_G_ENDIAN=1 \ + -DENDIANNESS=L_I_T_T_L_E_ENDIAN +endif + +obj-y += dma_sdma.o +obj-$(CONFIG_MXC_SDMA_API) += sdma.o +obj-$(CONFIG_MXC_SDMA_API) += iapi/ +obj-$(CONFIG_MXC_SDMA_API) += sdma_malloc.o diff --git a/arch/arm/plat-mxc/sdma/dma_sdma.c b/arch/arm/plat-mxc/sdma/dma_sdma.c new file mode 100644 index 000000000000..156127dbbaeb --- /dev/null +++ b/arch/arm/plat-mxc/sdma/dma_sdma.c @@ -0,0 +1,697 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/sdma/dma_sdma.c + * @brief Front-end to the DMA handling. This handles the allocation/freeing + * of DMA channels, and provides a unified interface to the machines + * DMA facilities. This file contains functions for Smart DMA. + * + * @ingroup SDMA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MXC_SDMA_API + +static mxc_dma_channel_t mxc_sdma_channels[MAX_DMA_CHANNELS]; +static mxc_dma_channel_private_t mxc_sdma_private[MAX_DMA_CHANNELS]; + +extern struct clk *mxc_sdma_ahb_clk, *mxc_sdma_ipg_clk; + +/*! + * Tasket to handle processing the channel buffers + * + * @param arg channel id + */ +static void mxc_sdma_channeltasklet(unsigned long arg) +{ + dma_request_t request_t; + dma_channel_params chnl_param; + mxc_dma_channel_t *chnl_info; + mxc_dma_channel_private_t *data_priv; + int bd_intr = 0, error = MXC_DMA_DONE; + + chnl_info = &mxc_sdma_channels[arg]; + data_priv = chnl_info->private; + chnl_param = + mxc_sdma_get_channel_params(chnl_info->channel)->chnl_params; + + mxc_dma_get_config(arg, &request_t, data_priv->buf_tail); + + while (request_t.bd_done == 0) { + bd_intr = mxc_dma_get_bd_intr(arg, data_priv->buf_tail); + data_priv->buf_tail += 1; + if (data_priv->buf_tail >= chnl_param.bd_number) { + data_priv->buf_tail = 0; + } + chnl_info->active = 0; + if (request_t.bd_error) { + error = MXC_DMA_TRANSFER_ERROR; + } + + if (bd_intr != 0) { + chnl_info->cb_fn(chnl_info->cb_args, error, + request_t.count); + error = MXC_DMA_DONE; + } + + if (data_priv->buf_tail == chnl_info->curr_buf) { + break; + } + memset(&request_t, 0, sizeof(dma_request_t)); + mxc_dma_get_config(arg, &request_t, data_priv->buf_tail); + } +} + +/*! + * This function is generally called by the driver at open time. + * The DMA driver would do any initialization steps that is required + * to get the channel ready for data transfer. + * + * @param channel_id a pre-defined id. The peripheral driver would specify + * the id associated with its peripheral. This would be + * used by the DMA driver to identify the peripheral + * requesting DMA and do the necessary setup on the + * channel associated with the particular peripheral. + * The DMA driver could use static or dynamic DMA channel + * allocation. + * @param dev_name module name or device name + * @return returns a negative number on error if request for a DMA channel did not + * succeed, returns the channel number to be used on success. + */ +int mxc_dma_request_ext(mxc_dma_device_t channel_id, char *dev_name, + struct dma_channel_info *info) +{ + mxc_sdma_channel_params_t *chnl; + mxc_dma_channel_private_t *data_priv; + int ret = 0, i = 0, channel_num = 0; + mxc_sdma_channel_ext_params_t *p; + + chnl = mxc_sdma_get_channel_params(channel_id); + if (chnl == NULL) { + return -EINVAL; + } + + if (info) { + if (!chnl->chnl_params.ext) + return -EINVAL; + p = (mxc_sdma_channel_ext_params_t *)chnl; + memcpy(&p->chnl_ext_params.info, info, sizeof(info)); + } + + + /* Enable the SDMA clock */ + clk_enable(mxc_sdma_ahb_clk); + clk_enable(mxc_sdma_ipg_clk); + + channel_num = chnl->channel_num; + if (chnl->channel_num == MXC_DMA_DYNAMIC_CHANNEL) { + /* Get the first free channel */ + for (i = (MAX_DMA_CHANNELS - 1); i > 0; i--) { + /* See if channel is available */ + if ((mxc_sdma_channels[i].dynamic != 1) + || (mxc_sdma_channels[i].lock != 0)) { + continue; + } + channel_num = i; + /* Check to see if we can get this channel */ + ret = mxc_request_dma(&channel_num, dev_name); + if (ret == 0) { + break; + } else { + continue; + } + } + if (ret != 0) { + /* No free channel */ + goto err_ret; + } + } else { + if (mxc_sdma_channels[chnl->channel_num].lock == 1) { + ret = -ENODEV; + goto err_ret; + } + ret = mxc_request_dma(&channel_num, dev_name); + if (ret != 0) { + goto err_ret; + } + } + + ret = mxc_dma_setup_channel(channel_num, &chnl->chnl_params); + + if (ret == 0) { + if (chnl->chnl_priority != MXC_SDMA_DEFAULT_PRIORITY) { + ret = + mxc_dma_set_channel_priority(channel_num, + chnl->chnl_priority); + if (ret != 0) { + pr_info("Failed to set channel prority,\ + continue with the existing \ + priority\n"); + goto err_ret; + } + } + mxc_sdma_channels[channel_num].lock = 1; + if ((chnl->chnl_params.transfer_type == per_2_emi) + || (chnl->chnl_params.transfer_type == dsp_2_emi)) { + mxc_sdma_channels[channel_num].mode = MXC_DMA_MODE_READ; + } else { + mxc_sdma_channels[channel_num].mode = + MXC_DMA_MODE_WRITE; + } + mxc_sdma_channels[channel_num].channel = channel_id; + data_priv = mxc_sdma_channels[channel_num].private; + tasklet_init(&data_priv->chnl_tasklet, + mxc_sdma_channeltasklet, channel_num); + if ((channel_id == MXC_DMA_ATA_RX) + || (channel_id == MXC_DMA_ATA_TX)) { + data_priv->intr_after_every_bd = 0; + } else { + data_priv->intr_after_every_bd = 1; + } + } + err_ret: + if (ret != 0) { + clk_disable(mxc_sdma_ahb_clk); + clk_disable(mxc_sdma_ipg_clk); + channel_num = -ENODEV; + } + + return channel_num; +} + +/*! + * This function is generally called by the driver at close time. The DMA + * driver would do any cleanup associated with this channel. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_free(int channel_num) +{ + mxc_dma_channel_private_t *data_priv; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + mxc_free_dma(channel_num); + + /* Disable the SDMA clock */ + clk_disable(mxc_sdma_ahb_clk); + clk_disable(mxc_sdma_ipg_clk); + + mxc_sdma_channels[channel_num].lock = 0; + mxc_sdma_channels[channel_num].active = 0; + mxc_sdma_channels[channel_num].curr_buf = 0; + data_priv = mxc_sdma_channels[channel_num].private; + data_priv->buf_tail = 0; + tasklet_kill(&data_priv->chnl_tasklet); + + return 0; +} + +/*! + * Callback function called from the SDMA Interrupt routine + * + * @param arg driver specific argument that was registered + */ +static void mxc_dma_chnl_callback(void *arg) +{ + int priv; + mxc_dma_channel_private_t *data_priv; + + priv = (int)arg; + data_priv = mxc_sdma_channels[priv].private; + /* Process the buffers in a tasklet */ + tasklet_schedule(&data_priv->chnl_tasklet); +} + +/*! + * This function would just configure the buffers specified by the user into + * dma channel. The caller must call mxc_dma_enable to start this transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param dma_buf an array of physical addresses to the user defined + * buffers. The caller must guarantee the dma_buf is + * available until the transfer is completed. + * @param num_buf number of buffers in the array + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not be + * added with DMA for transfer. On Success, it returns 0 + */ +int mxc_dma_config(int channel_num, mxc_dma_requestbuf_t *dma_buf, + int num_buf, mxc_dma_mode_t mode) +{ + int ret = 0, i = 0, prev_buf; + mxc_dma_channel_t *chnl_info; + mxc_dma_channel_private_t *data_priv; + mxc_sdma_channel_params_t *chnl; + dma_channel_params chnl_param; + dma_request_t request_t; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (num_buf <= 0) { + return -EINVAL; + } + + chnl_info = &mxc_sdma_channels[channel_num]; + data_priv = chnl_info->private; + if (chnl_info->lock != 1) { + return -ENODEV; + } + + /* Check to see if all buffers are taken */ + if (chnl_info->active == 1) { + return -EBUSY; + } + + chnl = mxc_sdma_get_channel_params(chnl_info->channel); + chnl_param = chnl->chnl_params; + + /* Re-setup the SDMA channel if the transfer direction is changed */ + if ((chnl_param.peripheral_type != MEMORY) && (mode != chnl_info->mode)) { + if (chnl_param.peripheral_type == DSP) { + if (mode == MXC_DMA_MODE_READ) { + chnl_param.transfer_type = dsp_2_emi; + } else { + chnl_param.transfer_type = emi_2_dsp; + } + } else if (chnl_param.peripheral_type == FIFO_MEMORY) { + if (mode == MXC_DMA_MODE_READ) + chnl_param.per_address = MXC_FIFO_MEM_SRC_FIXED; + else + chnl_param.per_address = + MXC_FIFO_MEM_DEST_FIXED; + } else { + if (mode == MXC_DMA_MODE_READ) { + chnl_param.transfer_type = per_2_emi; + } else { + chnl_param.transfer_type = emi_2_per; + } + } + chnl_param.callback = mxc_dma_chnl_callback; + chnl_param.arg = (void *)channel_num; + ret = mxc_dma_setup_channel(channel_num, &chnl_param); + if (ret != 0) { + return ret; + } + if (chnl->chnl_priority != MXC_SDMA_DEFAULT_PRIORITY) { + ret = + mxc_dma_set_channel_priority(channel_num, + chnl->chnl_priority); + if (ret != 0) { + pr_info("Failed to set channel prority,\ + continue with the existing \ + priority\n"); + } + } + chnl_info->mode = mode; + } + + for (i = 0; i < num_buf; i++, dma_buf++) { + /* Check to see if all buffers are taken */ + if (chnl_info->active == 1) { + break; + } + request_t.destAddr = (__u8 *) dma_buf->dst_addr; + request_t.sourceAddr = (__u8 *) dma_buf->src_addr; + request_t.count = dma_buf->num_of_bytes; + request_t.bd_cont = 1; + ret = mxc_dma_set_config(channel_num, &request_t, + chnl_info->curr_buf); + if (ret != 0) { + break; + } + if (data_priv->intr_after_every_bd == 0) { + if (i == num_buf - 1) { + mxc_dma_set_bd_intr(channel_num, + chnl_info->curr_buf, 1); + } else { + mxc_dma_set_bd_intr(channel_num, + chnl_info->curr_buf, 0); + } + } + + prev_buf = chnl_info->curr_buf; + chnl_info->curr_buf += 1; + if (chnl_info->curr_buf >= chnl_param.bd_number) { + chnl_info->curr_buf = 0; + } + if (chnl_info->curr_buf == data_priv->buf_tail) { + if ((data_priv->intr_after_every_bd == 0) + && (i != num_buf - 1)) { + /* + * Set the BD_INTR flag on the last BD that + * was queued + */ + mxc_dma_set_bd_intr(channel_num, prev_buf, 1); + } + chnl_info->active = 1; + } + } + + if (i == 0) { + return -EBUSY; + } + return 0; +} + +/*! + * This function would just configure the scatterlist specified by the + * user into dma channel. This is a slight variation of mxc_dma_config(), + * it is provided for the convenience of drivers that have a scatterlist + * passed into them. It is the calling driver's responsibility to have the + * correct physical address filled in the "dma_address" field of the + * scatterlist. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param sg a scatterlist of buffers. The caller must guarantee + * the dma_buf is available until the transfer is + * completed. + * @param num_buf number of buffers in the array + * @param num_of_bytes total number of bytes to transfer. If set to 0, this + * would imply to use the length field of the scatterlist + * for each DMA transfer. Else it would calculate the size + * for each DMA transfer. + * @param mode specifies whether this is READ or WRITE operation + * @return This function returns a negative number on error if buffer could not + * be added with DMA for transfer. On Success, it returns 0 + */ +int mxc_dma_sg_config(int channel_num, struct scatterlist *sg, + int num_buf, int num_of_bytes, mxc_dma_mode_t mode) +{ + int ret = 0, i = 0; + mxc_dma_requestbuf_t *dma_buf; + + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + dma_buf = + (mxc_dma_requestbuf_t *) kmalloc(num_buf * + sizeof(mxc_dma_requestbuf_t), + GFP_KERNEL); + + if (dma_buf == NULL) { + return -EFAULT; + } + + for (i = 0; i < num_buf; i++) { + if (mode == MXC_DMA_MODE_READ) { + (dma_buf + i)->dst_addr = sg->dma_address; + } else { + (dma_buf + i)->src_addr = sg->dma_address; + } + + if ((num_of_bytes > sg->length) || (num_of_bytes == 0)) { + (dma_buf + i)->num_of_bytes = sg->length; + } else { + (dma_buf + i)->num_of_bytes = num_of_bytes; + } + sg++; + num_of_bytes -= (dma_buf + i)->num_of_bytes; + } + + ret = mxc_dma_config(channel_num, dma_buf, num_buf, mode); + kfree(dma_buf); + return ret; +} + +/*! + * This function is provided if the driver would like to set/change its + * callback function. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @param callback a callback function to provide notification on transfer + * completion, user could specify NULL if he does not wish + * to be notified + * @param arg an argument that gets passed in to the callback + * function, used by the user to do any driver specific + * operations. + * @return this function returns a negative number on error if the callback + * could not be set for the channel or 0 on success + */ +int mxc_dma_callback_set(int channel_num, + mxc_dma_callback_t callback, void *arg) +{ + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + mxc_sdma_channels[channel_num].cb_fn = callback; + mxc_sdma_channels[channel_num].cb_args = arg; + + mxc_dma_set_callback(channel_num, mxc_dma_chnl_callback, + (void *)channel_num); + + return 0; +} + +/*! + * This stops the DMA channel and any ongoing transfers. Subsequent use of + * mxc_dma_enable() will restart the channel and restart the transfer. + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_disable(int channel_num) +{ + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + mxc_dma_stop(channel_num); + return 0; +} + +/*! + * This starts DMA transfer. Or it restarts DMA on a stopped channel + * previously stopped with mxc_dma_disable(). + * + * @param channel_num the channel number returned at request time. This + * would be used by the DMA driver to identify the calling + * driver and do the necessary cleanup on the channel + * associated with the particular peripheral + * @return returns a negative number on error or 0 on success + */ +int mxc_dma_enable(int channel_num) +{ + if ((channel_num >= MAX_DMA_CHANNELS) || (channel_num < 0)) { + return -EINVAL; + } + + if (mxc_sdma_channels[channel_num].lock != 1) { + return -ENODEV; + } + + mxc_dma_start(channel_num); + return 0; +} + +/*! + * Initializes dma structure with dma_operations + * + * @param dma dma structure + * @return returns 0 on success + */ +static int __init mxc_dma_init(void) +{ + int i; + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + mxc_sdma_channels[i].active = 0; + mxc_sdma_channels[i].lock = 0; + mxc_sdma_channels[i].curr_buf = 0; + mxc_sdma_channels[i].dynamic = 1; + mxc_sdma_private[i].buf_tail = 0; + mxc_sdma_channels[i].private = &mxc_sdma_private[i]; + } + /* + * Make statically allocated channels unavailable for dynamic channel + * requests + */ + mxc_get_static_channels(mxc_sdma_channels); + + return 0; +} + +arch_initcall(mxc_dma_init); + +#else +int mxc_request_dma(int *channel, const char *devicename) +{ + return -ENODEV; +} + +int mxc_dma_setup_channel(int channel, dma_channel_params *p) +{ + return -ENODEV; +} + +int mxc_dma_set_channel_priority(unsigned int channel, unsigned int priority) +{ + return -ENODEV; +} + +int mxc_dma_set_config(int channel, dma_request_t *p, int bd_index) +{ + return -ENODEV; +} + +int mxc_dma_get_config(int channel, dma_request_t *p, int bd_index) +{ + return -ENODEV; +} + +int mxc_dma_start(int channel) +{ + return -ENODEV; +} + +int mxc_dma_stop(int channel) +{ + return -ENODEV; +} + +void mxc_free_dma(int channel) +{ +} + +void mxc_dma_set_callback(int channel, dma_callback_t callback, void *arg) +{ +} + +void *sdma_malloc(size_t size) +{ + return 0; +} + +void sdma_free(void *buf) +{ +} + +void *sdma_phys_to_virt(unsigned long buf) +{ + return 0; +} + +unsigned long sdma_virt_to_phys(void *buf) +{ + return 0; +} + +int mxc_dma_request(mxc_dma_device_t channel_id, char *dev_name) +{ + return -ENODEV; +} + +int mxc_dma_free(int channel_num) +{ + return -ENODEV; +} + +int mxc_dma_config(int channel_num, mxc_dma_requestbuf_t *dma_buf, + int num_buf, mxc_dma_mode_t mode) +{ + return -ENODEV; +} + +int mxc_dma_sg_config(int channel_num, struct scatterlist *sg, + int num_buf, int num_of_bytes, mxc_dma_mode_t mode) +{ + return -ENODEV; +} + +int mxc_dma_callback_set(int channel_num, mxc_dma_callback_t callback, + void *arg) +{ + return -ENODEV; +} + +int mxc_dma_disable(int channel_num) +{ + return -ENODEV; +} + +int mxc_dma_enable(int channel_num) +{ + return -ENODEV; +} + +EXPORT_SYMBOL(mxc_request_dma); +EXPORT_SYMBOL(mxc_dma_setup_channel); +EXPORT_SYMBOL(mxc_dma_set_channel_priority); +EXPORT_SYMBOL(mxc_dma_set_config); +EXPORT_SYMBOL(mxc_dma_get_config); +EXPORT_SYMBOL(mxc_dma_start); +EXPORT_SYMBOL(mxc_dma_stop); +EXPORT_SYMBOL(mxc_free_dma); +EXPORT_SYMBOL(mxc_dma_set_callback); +EXPORT_SYMBOL(sdma_malloc); +EXPORT_SYMBOL(sdma_free); +EXPORT_SYMBOL(sdma_phys_to_virt); +EXPORT_SYMBOL(sdma_virt_to_phys); + +#endif + +EXPORT_SYMBOL(mxc_dma_request_ext); +EXPORT_SYMBOL(mxc_dma_free); +EXPORT_SYMBOL(mxc_dma_config); +EXPORT_SYMBOL(mxc_dma_sg_config); +EXPORT_SYMBOL(mxc_dma_callback_set); +EXPORT_SYMBOL(mxc_dma_disable); +EXPORT_SYMBOL(mxc_dma_enable); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Linux SDMA API"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/sdma/iapi/Makefile b/arch/arm/plat-mxc/sdma/iapi/Makefile new file mode 100644 index 000000000000..b6a5d6aebda0 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for I.API sources. +# + +obj-y := src/ \ No newline at end of file diff --git a/arch/arm/plat-mxc/sdma/iapi/include/epm.h b/arch/arm/plat-mxc/sdma/iapi/include/epm.h new file mode 100644 index 000000000000..8d190e242909 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/epm.h @@ -0,0 +1,191 @@ +/* + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_SDMA_REGS_H__ +#define __ASM_ARCH_MXC_SDMA_REGS_H__ + +#include + +/* SDMA Reg definition */ +extern void __iomem *sdma_base; +#define SDMA_BASE_IO_ADDR (sdma_base) + +#define SDMA_H_STATSTOP_ADDR (SDMA_BASE_IO_ADDR + 0x008) +#define SDMA_H_START_ADDR (SDMA_BASE_IO_ADDR + 0x00C) + +#define SDMA_H_C0PTR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x000))) +#define SDMA_H_INTR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x004))) +#define SDMA_H_STATSTOP (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x008))) +#define SDMA_H_START (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x00C))) +#define SDMA_H_EVTOVR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x010))) +#define SDMA_H_DSPOVR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x014))) +#define SDMA_H_HOSTOVR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x018))) +#define SDMA_H_EVTPEND (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x01C))) +#define SDMA_H_DSPENBL (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x020))) +#define SDMA_H_RESET (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x024))) +#define SDMA_H_EVTERR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x028))) +#define SDMA_H_INTRMSK (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x02C))) +#define SDMA_H_PSW (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x030))) +#define SDMA_H_EVTERRDBG (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x034))) +#define SDMA_H_CONFIG (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x038))) +#define SDMA_ONCE_ENB (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x040))) +#define SDMA_ONCE_DATA (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x044))) +#define SDMA_ONCE_INSTR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x048))) +#define SDMA_ONCE_STAT (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x04C))) +#define SDMA_ONCE_CMD (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x050))) +#define SDMA_EVT_MIRROR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x054))) +#define SDMA_ILLINSTADDR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x058))) +#define SDMA_CHN0ADDR (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x05C))) +#define SDMA_ONCE_RTB (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x060))) +#define SDMA_XTRIG_CONF1 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x070))) +#define SDMA_XTRIG_CONF2 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x074))) + +#ifdef MXC_SDMA_V2 +#define SDMA_CHNENBL_0 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x200))) +#define SDMA_CHNENBL_1 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x204))) +#define SDMA_CHNENBL_2 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x208))) +#define SDMA_CHNENBL_3 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x20C))) +#define SDMA_CHNENBL_4 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x210))) +#define SDMA_CHNENBL_5 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x214))) +#define SDMA_CHNENBL_6 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x218))) +#define SDMA_CHNENBL_7 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x21C))) +#define SDMA_CHNENBL_8 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x220))) +#define SDMA_CHNENBL_9 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x224))) +#define SDMA_CHNENBL_10 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x228))) +#define SDMA_CHNENBL_11 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x22C))) +#define SDMA_CHNENBL_12 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x230))) +#define SDMA_CHNENBL_13 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x234))) +#define SDMA_CHNENBL_14 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x238))) +#define SDMA_CHNENBL_15 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x23C))) +#define SDMA_CHNENBL_16 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x240))) +#define SDMA_CHNENBL_17 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x244))) +#define SDMA_CHNENBL_18 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x248))) +#define SDMA_CHNENBL_19 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x24C))) +#define SDMA_CHNENBL_20 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x250))) +#define SDMA_CHNENBL_21 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x254))) +#define SDMA_CHNENBL_22 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x258))) +#define SDMA_CHNENBL_23 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x25C))) +#define SDMA_CHNENBL_24 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x260))) +#define SDMA_CHNENBL_25 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x264))) +#define SDMA_CHNENBL_26 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x268))) +#define SDMA_CHNENBL_27 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x26C))) +#define SDMA_CHNENBL_28 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x270))) +#define SDMA_CHNENBL_29 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x274))) +#define SDMA_CHNENBL_30 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x278))) +#define SDMA_CHNENBL_31 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x27C))) +#define SDMA_CHNENBL_32 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x280))) +#define SDMA_CHNENBL_33 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x284))) +#define SDMA_CHNENBL_34 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x288))) +#define SDMA_CHNENBL_35 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x28C))) +#define SDMA_CHNENBL_36 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x290))) +#define SDMA_CHNENBL_37 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x294))) +#define SDMA_CHNENBL_38 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x298))) +#define SDMA_CHNENBL_39 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x29C))) +#define SDMA_CHNENBL_40 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2A0))) +#define SDMA_CHNENBL_41 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2A4))) +#define SDMA_CHNENBL_42 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2A8))) +#define SDMA_CHNENBL_43 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2AC))) +#define SDMA_CHNENBL_44 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2B0))) +#define SDMA_CHNENBL_45 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2B4))) +#define SDMA_CHNENBL_46 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2B8))) +#define SDMA_CHNENBL_47 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x2BC))) + +#define SDMA_ONCE_COUNT (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x300))) +#define SDMA_ONCE_ECTL (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x304))) +#define SDMA_ONCE_EAA (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x308))) +#define SDMA_ONCE_EAB (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x30C))) +#define SDMA_ONCE_EAM (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x310))) +#define SDMA_ONCE_ED (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x314))) +#define SDMA_ONCE_EDM (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x318))) +#define SDMA_ONCE_PCMATCH (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x31C))) + +#else + +#define SDMA_CHNENBL_0 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x080))) +#define SDMA_CHNENBL_1 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x084))) +#define SDMA_CHNENBL_2 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x088))) +#define SDMA_CHNENBL_3 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x08C))) +#define SDMA_CHNENBL_4 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x090))) +#define SDMA_CHNENBL_5 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x094))) +#define SDMA_CHNENBL_6 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x098))) +#define SDMA_CHNENBL_7 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x09C))) +#define SDMA_CHNENBL_8 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0A0))) +#define SDMA_CHNENBL_9 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0A4))) +#define SDMA_CHNENBL_10 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0A8))) +#define SDMA_CHNENBL_11 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0AC))) +#define SDMA_CHNENBL_12 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0B0))) +#define SDMA_CHNENBL_13 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0B4))) +#define SDMA_CHNENBL_14 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0B8))) +#define SDMA_CHNENBL_15 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0BC))) +#define SDMA_CHNENBL_16 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0C0))) +#define SDMA_CHNENBL_17 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0C4))) +#define SDMA_CHNENBL_18 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0C8))) +#define SDMA_CHNENBL_19 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0CC))) +#define SDMA_CHNENBL_20 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0D0))) +#define SDMA_CHNENBL_21 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0D4))) +#define SDMA_CHNENBL_22 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0D8))) +#define SDMA_CHNENBL_23 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0DC))) +#define SDMA_CHNENBL_24 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0E0))) +#define SDMA_CHNENBL_25 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0E4))) +#define SDMA_CHNENBL_26 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0E8))) +#define SDMA_CHNENBL_27 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0EC))) +#define SDMA_CHNENBL_28 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0F0))) +#define SDMA_CHNENBL_29 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0F4))) +#define SDMA_CHNENBL_30 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0F8))) +#define SDMA_CHNENBL_31 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x0FC))) + +#define SDMA_ONCE_COUNT (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x200))) +#define SDMA_ONCE_ECTL (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x204))) +#define SDMA_ONCE_EAA (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x208))) +#define SDMA_ONCE_EAB (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x20C))) +#define SDMA_ONCE_EAM (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x210))) +#define SDMA_ONCE_ED (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x214))) +#define SDMA_ONCE_EDM (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x218))) +#define SDMA_ONCE_PCMATCH (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x21C))) + +#endif /* MXC_SDMA_V2 */ + +#define SDMA_CHNPRI_0 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x100))) +#define SDMA_CHNPRI_1 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x104))) +#define SDMA_CHNPRI_2 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x108))) +#define SDMA_CHNPRI_3 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x10C))) +#define SDMA_CHNPRI_4 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x110))) +#define SDMA_CHNPRI_5 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x114))) +#define SDMA_CHNPRI_6 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x118))) +#define SDMA_CHNPRI_7 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x11C))) +#define SDMA_CHNPRI_8 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x120))) +#define SDMA_CHNPRI_9 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x124))) +#define SDMA_CHNPRI_10 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x128))) +#define SDMA_CHNPRI_11 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x12C))) +#define SDMA_CHNPRI_12 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x130))) +#define SDMA_CHNPRI_13 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x134))) +#define SDMA_CHNPRI_14 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x138))) +#define SDMA_CHNPRI_15 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x13C))) +#define SDMA_CHNPRI_16 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x140))) +#define SDMA_CHNPRI_17 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x144))) +#define SDMA_CHNPRI_18 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x148))) +#define SDMA_CHNPRI_19 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x14C))) +#define SDMA_CHNPRI_20 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x150))) +#define SDMA_CHNPRI_21 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x154))) +#define SDMA_CHNPRI_22 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x158))) +#define SDMA_CHNPRI_23 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x15C))) +#define SDMA_CHNPRI_24 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x160))) +#define SDMA_CHNPRI_25 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x164))) +#define SDMA_CHNPRI_26 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x168))) +#define SDMA_CHNPRI_27 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x16C))) +#define SDMA_CHNPRI_28 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x170))) +#define SDMA_CHNPRI_29 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x174))) +#define SDMA_CHNPRI_30 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x178))) +#define SDMA_CHNPRI_31 (*((volatile unsigned long *)(SDMA_BASE_IO_ADDR + 0x17C))) + +#endif /* _mcuEpm_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/iapi.h b/arch/arm/plat-mxc/sdma/iapi/include/iapi.h new file mode 100644 index 000000000000..7bb4915f7868 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/iapi.h @@ -0,0 +1,47 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapi.h + * + * $Id iapi.h $ + * + * Description: + * Unique include for the whole IAPI library. + * + * + * http//compass.mot.com/go/115342679 + * + * $Log iapi.h $ + * + * ***************************************************************************/ + +#ifndef _iapi_h +#define _iapi_h + +/* **************************************************************************** + * Include File Section + * ***************************************************************************/ + +#include "sdmaStruct.h" +#include "iapiDefaults.h" +#include "iapiLow.h" +#include "iapiMiddle.h" +#include "iapiHigh.h" + +#ifdef MCU +#include "iapiLowMcu.h" +#include "iapiMiddleMcu.h" +#endif /* MCU */ + +#endif /* _iapi_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h b/arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h new file mode 100644 index 000000000000..6ce00b8da5bb --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/iapiDefaults.h @@ -0,0 +1,126 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiDefaults.h + * + * $Id iapiDefaults.h $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * + * + * + * + * $Log iapiDefaults.h $ + * + *****************************************************************************/ + +#ifndef _iapi_defaults_h +#define _iapi_defaults_h + +/****************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include "sdmaStruct.h" + +/* **************************************************************************** + * Macro-command Section + * ***************************************************************************/ + +/** + * Error codes + * lower 5 bits free to include channel number when available + * and bit number 6 must be set when channel number is available + * + * Note : + * 1) Abbreviations / naming convention : + * - BD : Buffer Descriptor + * - CC : Channel Context + * - CCB : Channel Control Block + * - CD : Channel Descriptor + * - B : Buffer + * - CH : Channel + * + */ +#define IAPI_SUCCESS 0 +#define IAPI_FAILURE -1 +#define IAPI_ERR_CH_AVAILABLE 0x00020 +#define IAPI_ERR_NO_ERROR 0x00000 +#define IAPI_ERR_NO_CCB_DEFINED 0x01000 +#define IAPI_ERR_BD_UNINITIALIZED 0x02000 +#define IAPI_ERR_BD_ALLOCATED 0x03000 +#define IAPI_ERR_BD_ALLOCATION 0x04000 +#define IAPI_ERR_CCB_ALLOC_FAILED 0x05000 +#define IAPI_ERR_CCB_UNINITIALIZED 0x06000 +#define IAPI_ERR_CC_ALREADY_DEFINED 0x07000 +#define IAPI_ERR_CC_ALLOC_FAILED 0x08000 +#define IAPI_ERR_CD_ALREADY_DEFINED 0x09000 +#define IAPI_ERR_CD_ALLOC_FAILED 0x0A000 +#define IAPI_ERR_CD_CHANGE_CH_NUMBER 0x0B000 +#define IAPI_ERR_CD_CHANGE_CCB_PTR 0x0C000 +#define IAPI_ERR_CD_CHANGE_UNKNOWN 0x0D000 +#define IAPI_ERR_CD_CHANGE 0x0E000 +#define IAPI_ERR_CD_UNINITIALIZED 0x0F000 +#define IAPI_ERR_CLOSE 0x10000 +#define IAPI_ERR_B_ALLOC_FAILED 0x11000 +#define IAPI_ERR_CONFIG_OVERRIDE 0x12000 +#define IAPI_ERR_CH_IN_USE 0x13000 +#define IAPI_ERR_CALLBACKSYNCH_UNKNOWN 0x14000 +#define IAPI_ERR_INVALID_PARAMETER 0x15000 +#define IAPI_ERR_TRUST 0x16000 +#define IAPI_ERR_CHANNEL_UNINITIALIZED 0x17000 +#define IAPI_ERR_RROR_BIT_READ 0x18000 +#define IAPI_ERR_RROR_BIT_WRITE 0x19000 +#define IAPI_ERR_NOT_ALLOWED 0x1A000 +#define IAPI_ERR_NO_OS_FN 0x1B000 + +/* + * Global Variable Section + */ + +/* + * Table to hold pointers to the callback functions registered by the users of + *I.API + */ +extern void (*callbackIsrTable[CH_NUM]) (channelDescriptor * cd_p, void *arg); + +/* + * Table to hold user registered data pointers, to be privided in the callback + *function + */ +extern void *userArgTable[CH_NUM]; + +/* channelDescriptor data structure filled with default data*/ +extern channelDescriptor iapi_ChannelDefaults; + +/* Global variable to hold the last error encountered in I.API operations*/ +extern unsigned int iapi_errno; + +/* Used in synchronization, to mark started channels*/ +extern volatile unsigned long iapi_SDMAIntr; + +/* Hold a pointer to the start of the CCB array, to be used in the IRQ routine + *to find the channel descriptor for the channed sending the interrupt to the + *core. + */ +extern channelControlBlock *iapi_CCBHead; + +/* configs_data structure filled with default data*/ +extern configs_data iapi_ConfigDefaults; + +#endif /* iapiDefaults_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h b/arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h new file mode 100644 index 000000000000..999a89872f80 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/iapiHigh.h @@ -0,0 +1,132 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiHigh.h + * + * $Id iapiHigh.h $ + * + * Description: + * prototypes for high level function of I.API + * + * + * http://venerque.sps.mot.com/pjt/sfs/www/iapi/softsim_api.pdf + * + * $Log iapiHigh.h + * + * ***************************************************************************/ + +#ifndef _iapiHigh_h +#define _iapiHigh_h + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "sdmaStruct.h" + +/* **************************************************************************** + * Macro-command Section + *****************************************************************************/ +enum { + IAPI_CHANGE_CHANDESC, + IAPI_CHANGE_BDNUM, + IAPI_CHANGE_BUFFSIZE, + IAPI_CHANGE_CHANBLOCK, + IAPI_CHANGE_INSTANCE, + IAPI_CHANGE_OWNERSHIP, + IAPI_CHANGE_SYNCH, + IAPI_CHANGE_TRUST, + IAPI_CHANGE_CALLBACKFUNC, + IAPI_CHANGE_CHANCCB, + IAPI_CHANGE_PRIORITY, + IAPI_CHANGE_BDWRAP, + IAPI_CHANGE_WATERMARK, + IAPI_CHANGE_SET_BDCONT, + IAPI_CHANGE_UNSET_BDCONT, + IAPI_CHANGE_SET_BDEXTD, + IAPI_CHANGE_UNSET_BDEXTD, + IAPI_CHANGE_EVTMASK1, + IAPI_CHANGE_EVTMASK2, + IAPI_CHANGE_PERIPHADDR, + IAPI_CHANGE_SET_BDINTR, + IAPI_CHANGE_UNSET_BDINTR, + IAPI_CHANGE_SET_TRANSFER_CD, + IAPI_CHANGE_FORCE_CLOSE, + IAPI_CHANGE_SET_TRANSFER, + IAPI_CHANGE_USER_ARG, + IAPI_CHANGE_SET_BUFFERADDR, + IAPI_CHANGE_SET_EXTDBUFFERADDR, + IAPI_CHANGE_SET_COMMAND, + IAPI_CHANGE_SET_COUNT, + IAPI_CHANGE_SET_STATUS, + IAPI_CHANGE_GET_BUFFERADDR, + IAPI_CHANGE_GET_EXTDBUFFERADDR, + IAPI_CHANGE_GET_COMMAND, + IAPI_CHANGE_GET_COUNT, + IAPI_CHANGE_GET_STATUS, + IAPI_CHANGE_SET_ENDIANNESS +}; + +/* + * Public Function Prototype Section + */ +int iapi_Open(channelDescriptor *cd_p, unsigned char channelNumber); +int iapi_Close(channelDescriptor *cd_p); +int iapi_Read(channelDescriptor *cd_p, void *buf, unsigned short nbyte); +int iapi_Write(channelDescriptor *cd_p, void *buf, unsigned short nbyte); +int iapi_MemCopy(channelDescriptor *cd_p, void *dest, void *src, + unsigned long size); +int iapi_IoCtl(channelDescriptor *cd_p, unsigned long ctlRequest, + unsigned long param); + +int iapi_Read_ipcv2(channelDescriptor *cd_p, void *data_control_struct_ipcv2); + +int iapi_Write_ipcv2(channelDescriptor *cd_p, void *data_control_struct_ipcv2); + +#ifdef MCU +int iapi_Init(channelDescriptor *cd_p, configs_data *config_p, + unsigned short *ram_image, unsigned short code_size, + unsigned long start_addr); +#endif /* MCU */ +#ifdef DSP +int iapi_Init(channelDescriptor *cd_p); +#endif /* DSP */ + +int iapi_StartChannel(unsigned char channel); +int iapi_StopChannel(unsigned char channel); +int iapi_SynchChannel(unsigned char channel); + +int iapi_GetChannelNumber(channelDescriptor *cd_p); +unsigned long iapi_GetError(channelDescriptor *cd_p); +int iapi_GetCount(channelDescriptor *cd_p); +int iapi_GetCountAll(channelDescriptor *cd_p); + +#ifndef IRQ_KEYWORD +#define IRQ_KEYWORD +#endif /* IRQ_KEYWORD */ + +IRQ_KEYWORD void IRQ_Handler(void); + +#ifdef MCU +int iapi_GetScript(channelDescriptor *cd_p, void *buf, unsigned short size, + unsigned long address); +int iapi_GetContext(channelDescriptor *cd_p, void *buf, unsigned char channel); +int iapi_SetScript(channelDescriptor *cd_p, void *buf, unsigned short nbyte, + unsigned long destAddr); +int iapi_SetContext(channelDescriptor *cd_p, void *buf, unsigned char channel); +int iapi_AssignScript(channelDescriptor *cd_p, script_data *data_p); + +int iapi_SetChannelEventMapping(unsigned char event, unsigned long channel_map); +#endif /* MCU */ + +#endif /* _iapiHigh_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h b/arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h new file mode 100644 index 000000000000..82a2e2d4be3a --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/iapiLow.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLow.h + * + * $Id iapiLow.h $ + * + * Description: + * prototypes for low level function of I.API + * + * + * + * + * $Log iapiLow.h + * + * ***************************************************************************/ + +#ifndef _iapiLow_h +#define _iapiLow_h + +/* **************************************************************************** + * Boolean identifiers + *****************************************************************************/ +#define NO_OS 0 +#define LINUX 1 +#define SYMBIAN 2 +#define WINCE 3 + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "sdmaStruct.h" +#include "iapiDefaults.h" +#include "iapiOS.h" +#ifdef MCU +#include "iapiLowMcu.h" +#endif /*MCU*/ +#if OS == NO_OS +#include +#elif OS == LINUX +#include +#endif +/* **************************************************************************** + * Macro-command Section + *****************************************************************************/ +#define GOTO_SLEEP(x) (iapi_GotoSleep)(x) +#define INIT_SLEEP(x) (iapi_InitSleep)(x) +/* **************************************************************************** + * Public Function Prototype Section + *****************************************************************************/ +void iapi_lowStartChannel(unsigned char channel); +void iapi_lowStopChannel(unsigned char channel); +void iapi_AttachCallbackISR(channelDescriptor *cd_p, + void (*func_p) (channelDescriptor *cd_p, + void *arg)); +void iapi_DetachCallbackISR(channelDescriptor *cd_p); +void iapi_ChangeCallbackISR(channelDescriptor *cd_p, + void (*func_p) (channelDescriptor *cd_p, + void *arg)); +void iapi_lowSynchChannel(unsigned char channel); +void iapi_SetBufferDescriptor(bufferDescriptor *bd_p, unsigned char command, + unsigned char status, unsigned short count, + void *buffAddr, void *extBufferAddr); + +#endif /* _iapiLow_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h b/arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h new file mode 100644 index 000000000000..a228003b1f5a --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/iapiLowMcu.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLowMcu.h + * + * $Id iapiLowMcu.h $ + * + * Description: + * prototypes for low level function of I.API of MCU side only + * + * + * + * + * $Log iapiLowMcu.h $ + * + * ***************************************************************************/ + +#ifndef _iapiLowMcu_h +#define _iapiLowMcu_h + +/****************************************************************************** + * Include File Section + *****************************************************************************/ +#include "sdmaStruct.h" +#include "iapiDefaults.h" + +/* **************************************************************************** + * Public Function Prototype Section + * ***************************************************************************/ + +void iapi_InitChannelTables(void); +int iapi_ChannelConfig(unsigned char channel, unsigned eventOverride, + unsigned mcuOverride, unsigned dspOverride); +int iapi_Channel0Command(channelDescriptor *cd_p, void *buf, + unsigned short nbyte, unsigned char command); +void iapi_lowGetScript(channelDescriptor *cd_p, void *buf, unsigned short size, + unsigned long address); +void iapi_lowGetContext(channelDescriptor *cd_p, void *buf, + unsigned char channel); +void iapi_lowSetScript(channelDescriptor *cd_p, void *buf, + unsigned short nbyte, unsigned long destAddr); +void iapi_lowSetContext(channelDescriptor *cd_p, void *buf, + unsigned char channel); +int iapi_lowAssignScript(channelDescriptor *cd_p, script_data *data_p); + +int iapi_lowSetChannelEventMapping(unsigned char event, + unsigned long channel_map); + +#endif /* _iapiLowMcu_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h b/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h new file mode 100644 index 000000000000..33529ba064d5 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddle.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiMiddle.h + * + * $Id iapiMiddle.h $ + * + * Description: + * prototypes for middle level function of I.API + * + * + * + * + * $Log iapiMiddle.h + * + * ***************************************************************************/ + +#ifndef _iapiMiddle_h +#define _iapiMiddle_h + +/* **************************************************************************** + * Include File Section + ******************************************************************************/ +#include "sdmaStruct.h" +#ifdef MCU +#include "iapiMiddleMcu.h" +#endif /* MCU */ + +/* **************************************************************************** + * Public Function Prototype Section + ******************************************************************************/ +bufferDescriptor *iapi_AllocBD(channelControlBlock *ccb_p); +int iapi_AllocContext(contextData **ctxd_p, unsigned char channel); +int iapi_AllocChannelDesc(channelDescriptor **cd_p, unsigned char channel); +int iapi_ChangeChannelDesc(channelDescriptor *cd_p, + unsigned char whatToChange, unsigned long newval); +void iapi_InitializeCallbackISR(void (*func_p) (channelDescriptor *cd_p, + void *arg)); +int iapi_InitializeMemory(channelControlBlock *ccb_p); + +#endif /* iapiMiddle_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h b/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h new file mode 100644 index 000000000000..7f6dd27686b2 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/iapiMiddleMcu.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiMiddleMcu.h + * + * $Id iapiMiddleMcu.h $ + * + * Description: + * prototypes for middle level function of I.API + * + * + * + * + * $Log iapiMiddleMcu.h + * + * ***************************************************************************/ + +#ifndef _iapiMiddleMcu_h +#define _iapiMiddleMcu_h + +/* **************************************************************************** + * Include File Section + ******************************************************************************/ +#include "sdmaStruct.h" + +/* **************************************************************************** + * Public Function Prototype Section + ******************************************************************************/ + +#endif /* iapiMiddleMcu_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h b/arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h new file mode 100644 index 000000000000..bec4941b4bd4 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/iapiOS.h @@ -0,0 +1,92 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiOS.h + * + * $Id iapiOS.h $ + * + * Description: + * prototypes for OS level function of I.API + * + * + * + * + * $Log iapiOS.h + * + * ***************************************************************************/ + +#ifndef _iapiOS_h +#define _iapiOS_h + +/* **************************************************************************** + * Boolean identifiers + *****************************************************************************/ +#define NO_OS 0 +#define LINUX 1 +#define SYMBIAN 2 +#define WINCE 3 + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "sdmaStruct.h" +#include "iapiDefaults.h" +#ifdef MCU +#include "iapiLowMcu.h" +#endif /*MCU*/ +#if OS == NO_OS +#include +#elif OS == LINUX +#include +#endif +/* **************************************************************************** + * Macro-command Section + *****************************************************************************/ +#define SDMA_ERAM 0 +#define SDMA_IRAM 1 +#ifdef CONFIG_SDMA_IRAM +#define MALLOC(x, s) (s == SDMA_ERAM) ? (*iapi_Malloc)(x) : (*iapi_iram_Malloc)(x) +#else /*CONFIG_SDMA_IRAM */ +#define MALLOC(x, s) (*iapi_Malloc)(x) +#endif /*CONFIG_SDMA_IRAM */ +#define FREE(x) if (x != NULL) (*iapi_Free)(x) +#define GOTO_SLEEP(x) (iapi_GotoSleep)(x) +#define INIT_SLEEP(x) (iapi_InitSleep)(x) +/* **************************************************************************** + * Public Function Prototype Section + *****************************************************************************/ +#ifdef CONFIG_SDMA_IRAM +extern void *(*iapi_iram_Malloc) (size_t size); +#endif /*CONFIG_SDMA_IRAM */ + +extern void *(*iapi_Malloc) (size_t size); +extern void (*iapi_Free) (void *ptr); + +extern void *(*iapi_Virt2Phys) (void *ptr); +extern void *(*iapi_Phys2Virt) (void *ptr); + +extern void (*iapi_WakeUp) (int); +extern void (*iapi_GotoSleep) (int); +extern void (*iapi_InitSleep) (int); + +extern void *(*iapi_memcpy) (void *dest, const void *src, size_t count); +extern void *(*iapi_memset) (void *dest, int c, size_t count); + +extern void (*iapi_EnableInterrupts) (void); +extern void (*iapi_DisableInterrupts) (void); + +extern int (*iapi_GetChannel) (int); +extern int (*iapi_ReleaseChannel) (int); + +#endif /* _iapiOS_h */ diff --git a/arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h b/arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h new file mode 100644 index 000000000000..02ed065af2fa --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/include/sdmaStruct.h @@ -0,0 +1,509 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: sdmaStruct.h + * + * $Id sdmaStruct.h $ + * + * Description: provides necessary definitions and inclusion for ipcmStruct.c + * + * $Log $ + * + *****************************************************************************/ +#ifndef _sdmaStruct_h +#define _sdmaStruct_h + +/* **************************************************************************** + * Include File Section + ******************************************************************************/ + +/* **************************************************************************** + * Macro-command Section + ******************************************************************************/ + +/** + * Identifier NULL + */ +#ifndef NULL +#define NULL 0 +#endif + +/** + * Boolean identifiers + */ +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +/** + * Number of channels + */ +#define CH_NUM 32 +/** + * Number of events + */ +#ifdef MXC_SDMA_V2 +#define EVENTS_NUM 48 +#else +#define EVENTS_NUM 32 +#endif +/** + * Channel configuration + */ +#define DONT_OWN_CHANNEL 0 +#define OWN_CHANNEL 1 + +/** + * Ownership (value defined to computed decimal value) + */ +#define CH_OWNSHP_OFFSET_EVT 0 +#define CH_OWNSHP_OFFSET_MCU 1 +#define CH_OWNSHP_OFFSET_DSP 2 +/** + * Indexof the greg which holds address to start a script from when channel + * becomes current. + */ +#define SDMA_NUMBER_GREGS 8 + +/** + * Channel contexts management + */ + +#define CHANNEL_CONTEXT_BASE_ADDRESS 0x800 +/** + * Buffer descriptor status values. + */ +#define BD_DONE 0x01 +#define BD_WRAP 0x02 +#define BD_CONT 0x04 +#define BD_INTR 0x08 +#define BD_RROR 0x10 +#define BD_LAST 0x20 +#define BD_EXTD 0x80 + +/** + * Data Node descriptor status values. + */ +#define DND_END_OF_FRAME 0x80 +#define DND_END_OF_XFER 0x40 +#define DND_DONE 0x20 +#define DND_UNUSED 0x01 + +/** + * IPCV2 descriptor status values. + */ +#define BD_IPCV2_END_OF_FRAME 0x40 + +#define IPCV2_MAX_NODES 50 +/** + * Error bit set in the CCB status field by the SDMA, + * in setbd routine, in case of a transfer error + */ +#define DATA_ERROR 0x10000000 + +/** + * Buffer descriptor commands. + */ +#define C0_ADDR 0x01 +#define C0_LOAD 0x02 +#define C0_DUMP 0x03 +#define C0_SETCTX 0x07 +#define C0_GETCTX 0x03 +#define C0_SETDM 0x01 +#define C0_SETPM 0x04 +#define C0_GETDM 0x02 +#define C0_GETPM 0x08 +/** + * Transfer types, encoded in the BD command field + */ +#define TRANSFER_32BIT 0x00 +#define TRANSFER_8BIT 0x01 +#define TRANSFER_16BIT 0x02 +#define TRANSFER_24BIT 0x03 +/** + * Change endianness indicator in the BD command field + */ +#define CHANGE_ENDIANNESS 0x80 +/** + * Size in bytes + */ +#define SDMA_BD_SIZE 8 +#define SDMA_EXTENDED_BD_SIZE 12 +#define BD_NUMBER 4 +/** + * Channel interrupt policy + */ +#define DEFAULT_POLL 0 +#define CALLBACK_ISR 1 +/** + * Channel status + */ +#define UNINITIALIZED 0 +#define INITIALIZED 1 + +/** + * IoCtl particular values + */ +#define SET_BIT_ALL 0xFFFFFFFF +#define BD_NUM_OFFSET 16 +#define BD_NUM_MASK 0xFFFF0000 + +/** + * Maximum values for IoCtl calls, used in high or middle level calls + */ +#define MAX_BD_NUM 256 +#define MAX_BD_SIZE 65536 +#define MAX_BLOCKING 2 +#define MAX_SYNCH 2 +#define MAX_OWNERSHIP 8 +#define MAX_CH_PRIORITY 8 +#define MAX_TRUST 2 +#define MAX_WML 256 + +/** + * Access to channelDescriptor fields + */ +enum { + IAPI_CHANNELNUMBER, + IAPI_BUFFERDESCNUMBER, + IAPI_BUFFERSIZE, + IAPI_BLOCKING, + IAPI_CALLBACKSYNCH, + IAPI_OWNERSHIP, + IAPI_PRIORITY, + IAPI_TRUST, + IAPI_UNUSED, + IAPI_CALLBACKISR_PTR, + IAPI_CCB_PTR, + IAPI_BDWRAP, + IAPI_WML +}; + +/** + * Default values for channel descriptor - nobody ownes the channel + */ +#define CD_DEFAULT_OWNERSHIP 7 + +/** + * User Type Section + */ + +/** + * Command/Mode/Count of buffer descriptors + */ + +#if (ENDIANNESS == B_I_G_ENDIAN) +typedef struct iapi_modeCount_ipcv2 { + unsigned long status:8; + /**< L, E , D bits stored here */ + unsigned long reserved:8; + unsigned long count:16; + /**< +#include + +#include "epm.h" +#include "iapi.h" + +/* **************************************************************************** + * External Reference Section (for compatibility with already developed code) + *****************************************************************************/ +static void iapi_read_ipcv2_callback(struct iapi_channelDescriptor *cd_p, + void *data); + +/* **************************************************************************** + * Global Variable Section + *****************************************************************************/ +#define MAX_CHANNEL 32 + +static dataNodeDescriptor *dnd_read_control_struct[MAX_CHANNEL]; + +/* MASK to get Nullify all the bits of Status in Data Node descriptor apart from L, E and D*/ + +#define GET_LED_MASK 0xE0 + +/*Table defines mapping of Data Node Descriptor to Buffer Descriptor status*/ + +static unsigned char dnd_2_bd_status[] = { + 0x85, /*00 L = 0, E = 0, D = 0 */ + 0x00, /*01 */ + 0x00, /*02 */ + 0x00, /*03 */ + 0x00, /*04 */ + 0x00, /*05 */ + 0x00, /*06 */ + 0x00, /*07 */ + 0x00, /*08 */ + 0x00, /*09 */ + 0x00, /*0A */ + 0x00, /*0B */ + 0x00, /*0C */ + 0x00, /*0D */ + 0x00, /*0E */ + 0x00, /*0F */ + 0x00, /*10 */ + 0x00, /*11 */ + 0x00, /*12 */ + 0x00, /*13 */ + 0x00, /*14 */ + 0x00, /*15 */ + 0x00, /*16 */ + 0x00, /*17 */ + 0x00, /*18 */ + 0x00, /*19 */ + 0x00, /*1A */ + 0x00, /*1B */ + 0x00, /*1C */ + 0x00, /*1D */ + 0x00, /*1E */ + 0x00, /*1F */ + 0x84, /*20 L = 0, E = 0, D = 1 */ + 0x00, /*21 */ + 0x00, /*22 */ + 0x00, /*23 */ + 0x00, /*24 */ + 0x00, /*25 */ + 0x00, /*26 */ + 0x00, /*27 */ + 0x00, /*28 */ + 0x00, /*29 */ + 0x00, /*2A */ + 0x00, /*2B */ + 0x00, /*2C */ + 0x00, /*2D */ + 0x00, /*2E */ + 0x00, /*2F */ + 0x00, /*30 */ + 0x00, /*31 */ + 0x00, /*32 */ + 0x00, /*33 */ + 0x00, /*34 */ + 0x00, /*35 */ + 0x00, /*36 */ + 0x00, /*37 */ + 0x00, /*38 */ + 0x00, /*39 */ + 0x00, /*3A */ + 0x00, /*3B */ + 0x00, /*3C */ + 0x00, /*3D */ + 0x00, /*3E */ + 0x00, /*3F */ + 0xAB, /*40 L = 0, E = 1, D = 0 */ + 0x00, /*41 */ + 0x00, /*42 */ + 0x00, /*43 */ + 0x00, /*44 */ + 0x00, /*45 */ + 0x00, /*46 */ + 0x00, /*47 */ + 0x00, /*48 */ + 0x00, /*49 */ + 0x00, /*4A */ + 0x00, /*4B */ + 0x00, /*4C */ + 0x00, /*4D */ + 0x00, /*4E */ + 0x00, /*4F */ + 0x00, /*50 */ + 0x00, /*51 */ + 0x00, /*52 */ + 0x00, /*53 */ + 0x00, /*54 */ + 0x00, /*55 */ + 0x00, /*56 */ + 0x00, /*57 */ + 0x00, /*58 */ + 0x00, /*59 */ + 0x00, /*5A */ + 0x00, /*5B */ + 0x00, /*5C */ + 0x00, /*5D */ + 0x00, /*5E */ + 0x00, /*5F */ + 0xAA, /*60 L = 0, E = 1, D = 1 */ + 0x00, /*61 */ + 0x00, /*62 */ + 0x00, /*63 */ + 0x00, /*64 */ + 0x00, /*65 */ + 0x00, /*66 */ + 0x00, /*67 */ + 0x00, /*68 */ + 0x00, /*69 */ + 0x00, /*6A */ + 0x00, /*6B */ + 0x00, /*6C */ + 0x00, /*6D */ + 0x00, /*6E */ + 0x00, /*6F */ + 0x00, /*70 */ + 0x00, /*71 */ + 0x00, /*72 */ + 0x00, /*73 */ + 0x00, /*74 */ + 0x00, /*75 */ + 0x00, /*76 */ + 0x00, /*77 */ + 0x00, /*78 */ + 0x00, /*79 */ + 0x00, /*7A */ + 0x00, /*7B */ + 0x00, /*7C */ + 0x00, /*7D */ + 0x00, /*7E */ + 0x00, /*7F */ + 0xC5, /*80 L = 1, E = 0, D = 0 */ + 0x00, /*81 */ + 0x00, /*82 */ + 0x00, /*83 */ + 0x00, /*84 */ + 0x00, /*85 */ + 0x00, /*86 */ + 0x00, /*87 */ + 0x00, /*88 */ + 0x00, /*89 */ + 0x00, /*8A */ + 0x00, /*8B */ + 0x00, /*8C */ + 0x00, /*8D */ + 0x00, /*8E */ + 0x00, /*8F */ + 0x00, /*90 */ + 0x00, /*91 */ + 0x00, /*92 */ + 0x00, /*93 */ + 0x00, /*94 */ + 0x00, /*95 */ + 0x00, /*96 */ + 0x00, /*97 */ + 0x00, /*98 */ + 0x00, /*99 */ + 0x00, /*9A */ + 0x00, /*9B */ + 0x00, /*9C */ + 0x00, /*9D */ + 0x00, /*9E */ + 0x00, /*9F */ + 0xC4, /*A0 L = 1, E = 0, D = 1 */ + 0x00, /*A1 */ + 0x00, /*A2 */ + 0x00, /*A3 */ + 0x00, /*A4 */ + 0x00, /*A5 */ + 0x00, /*A6 */ + 0x00, /*A7 */ + 0x00, /*A8 */ + 0x00, /*A9 */ + 0x00, /*AA*/ 0x00, /*AB*/ 0x00, /*AC*/ 0x00, /*AD*/ 0x00, /*AE*/ 0x00, /*AF*/ 0x00, /*B0 */ + 0x00, /*B1 */ + 0x00, /*B2 */ + 0x00, /*B3 */ + 0x00, /*B4 */ + 0x00, /*B5 */ + 0x00, /*B6 */ + 0x00, /*B7 */ + 0x00, /*B8 */ + 0x00, /*B9 */ + 0x00, /*BA*/ 0x00, /*BB*/ 0x00, /*BC*/ 0x00, /*BD*/ 0x00, /*BE*/ 0x00, /*BF*/ 0xEB, /*C0 L = 1, E = 1, D = 0 */ + 0x00, /*C1 */ + 0x00, /*C2 */ + 0x00, /*C3 */ + 0x00, /*C4 */ + 0x00, /*C5 */ + 0x00, /*C6 */ + 0x00, /*C7 */ + 0x00, /*C8 */ + 0x00, /*C9 */ + 0x00, /*CA*/ 0x00, /*CB*/ 0x00, /*CC*/ 0x00, /*CD*/ 0x00, /*CE*/ 0x00, /*CF*/ 0x00, /*D0 */ + 0x00, /*D1 */ + 0x00, /*D2 */ + 0x00, /*D3 */ + 0x00, /*D4 */ + 0x00, /*D5 */ + 0x00, /*D6 */ + 0x00, /*D7 */ + 0x00, /*D8 */ + 0x00, /*D9 */ + 0x00, /*DA*/ 0x00, /*DB*/ 0x00, /*DC*/ 0x00, /*DD*/ 0x00, /*DE*/ 0x00, /*DF*/ 0xEA, /*E0 L = 1, E = 1, D = 1 */ + 0x00, /*E1 */ + 0x00, /*E2 */ + 0x00, /*E3 */ + 0x00, /*E4 */ + 0x00, /*E5 */ + 0x00, /*E6 */ + 0x00, /*E7 */ + 0x00, /*E8 */ + 0x00, /*E9 */ + 0x00, /*EA*/ 0x00, /*EB*/ 0x00, /*EC*/ 0x00, /*ED*/ 0x00, /*EE*/ 0x00, /*EF*/ 0x00, /*F0 */ + 0x00, /*F1 */ + 0x00, /*F2 */ + 0x00, /*F3 */ + 0x00, /*F4 */ + 0x00, /*F5 */ + 0x00, /*F6 */ + 0x00, /*F7 */ + 0x00, /*F8 */ + 0x00, /*F9 */ + 0x00, /*FA*/ + 0x00, /*FB*/ 0x00, /*FC*/ 0x00, /*FD*/ 0x00, /*FE*/ 0x00 /*FF*/ +}; + +/* **************************************************************************** + * Function Section + *****************************************************************************/ + +/* ***************************************************************************/ +/**Opens an SDMA channel to be used by the library. + * + * Algorithm:\n + * + * - Check if initialization is necessary. + * - Check that user initialized OS dependant functions. + * - Test validity of input parameters + * - Check whole channel control block data structure + * - Finish initializations (tables with default values) + * - Initialize channel 0 is dedicated to communications with SDMA + * - Check channel control block definition + * - if the channel descriptor is not initialized, initialize it with + * the default value + * - If buffer descriptor already allocated, exit with iapi_errno filled + * complete the lowest bits with the number of 'D' bits set + * - Buffer Descriptors allocation + * - Channel's configuration properties (mcu side only) + * - read/write direction => enable/disable channel setting + * + * @param *cd_p -If channelNumber is 0, it is pointer to channel descriptor for the channnel 0 to be opened and + * has default values. + * For other channels,this function should be called after channel 0 has been opened, and it is channel descriptor for + * channel 0.Must be allocated. + * @param channelNumber channel to be opened + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : close failed, return negated value of iapi_errno + */ +int iapi_Open(channelDescriptor *cd_p, unsigned char channelNumber) +{ + channelControlBlock *ccb_p; + channelControlBlock *local_ccb_p; + channelDescriptor *local_cd_p; + bufferDescriptor *bd_p; + unsigned char index = 0; + int result = IAPI_SUCCESS; +#ifdef MCU + volatile unsigned long *channelPriorityMatx; +#endif /* MCU */ + + /* + * 1. Check if initialization is necessary + */ + if (cd_p == NULL) { + result = IAPI_ERR_CD_UNINITIALIZED | + IAPI_ERR_CH_AVAILABLE | channelNumber; + iapi_errno = result; + return -result; + } + + /* Verify these functions every time */ + if ((iapi_GetChannel == NULL) || (iapi_ReleaseChannel == NULL)) { + result = IAPI_ERR_NO_OS_FN | channelNumber; + iapi_errno = result; + return -result; + } + + /* Try to aquire channel */ + if (iapi_GetChannel(channelNumber) != 0) { + result = IAPI_ERR_CH_IN_USE | channelNumber; + iapi_errno = result; + return -result; + } + + if (channelNumber == 0 && cd_p->ccb_ptr == NULL) { + /* Verify that the user initialized all OS dependant functions required + * by the library. + */ + if ((iapi_Malloc == NULL) || (iapi_Free == NULL) + || (iapi_Virt2Phys == NULL) || (iapi_Phys2Virt == NULL) + || (iapi_GotoSleep == NULL) || (iapi_WakeUp == NULL) + || (iapi_InitSleep == NULL) || (iapi_memset == NULL) + || (iapi_memcpy == NULL)) { + result = IAPI_ERR_NO_OS_FN | channelNumber; + iapi_errno = result; + iapi_ReleaseChannel(channelNumber); + return -result; + } + /* Whole channel control block data structure */ + ccb_p = (channelControlBlock *) + MALLOC(CH_NUM * sizeof(channelControlBlock), SDMA_IRAM); + if (ccb_p == NULL) { + result = IAPI_ERR_CCB_ALLOC_FAILED | + IAPI_ERR_CH_AVAILABLE | channelNumber; + iapi_errno = result; + iapi_ReleaseChannel(channelNumber); + return -result; + } + /* Zero-out the CCB structures array just allocated */ + iapi_memset(ccb_p, 0x00, CH_NUM * sizeof(channelControlBlock)); + /* Save the address of the CCB structures array */ + iapi_CCBHead = ccb_p; + + cd_p->ccb_ptr = (struct iapi_channelControlBlock *)ccb_p; + ccb_p->channelDescriptor = cd_p; +#ifdef MCU + /* finish initializations */ + iapi_InitChannelTables(); +#endif /* MCU */ + /* Channel 0 is dedicated to communications with SDMA */ + cd_p->ownership = ((DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + cd_p->bufferDescNumber = 1; + } + + /* + * 2. Check channel control block + */ + ccb_p = cd_p->ccb_ptr; + if (ccb_p == NULL) { + result = + IAPI_ERR_NO_CCB_DEFINED | IAPI_ERR_CH_AVAILABLE | + channelNumber; + iapi_errno = result; + iapi_ReleaseChannel(channelNumber); + return -result; + } + + /* Control block & Descriptor associated with the channel being worked on */ + local_ccb_p = &ccb_p[channelNumber]; + local_cd_p = ccb_p[channelNumber].channelDescriptor; + + /* If the channel is not initialized, initialize it with the default value */ + if (local_cd_p == NULL) { + result = iapi_AllocChannelDesc(&local_cd_p, channelNumber); + if (result != IAPI_SUCCESS) { + iapi_ReleaseChannel(channelNumber); + /* is allready negated from iapi_AllocChannelDesc */ + return result; + } + + local_cd_p->ccb_ptr = + (struct iapi_channelControlBlock *)local_ccb_p; + local_ccb_p->channelDescriptor = local_cd_p; + } + + /* + * 3. If buffer descriptor already allocated, exit with iapi_errno filled + */ + if (local_ccb_p->baseBDptr != NULL) { + bd_p = + (bufferDescriptor *) iapi_Phys2Virt(local_ccb_p->baseBDptr); + result = IAPI_ERR_BD_ALLOCATED; + for (index = 1; index < local_cd_p->bufferDescNumber; index++) { + if ((bd_p->mode.status & BD_DONE) == BD_DONE) { + /* complete the lowest bits with the number of 'D' bits set */ + result++; + } + bd_p++; + } + iapi_errno = result; + iapi_ReleaseChannel(channelNumber); + return -result; + } + + /* + * 4. Buffer Descriptors allocation + */ + iapi_InitializeMemory(local_ccb_p); + +#ifdef MCU + /* + * 5. Channel's configuration properties (mcu side only) + */ + iapi_ChannelConfig(channelNumber, + (local_cd_p->ownership >> CH_OWNSHP_OFFSET_EVT) & + 1UL, + (local_cd_p->ownership >> CH_OWNSHP_OFFSET_MCU) & + 1UL, + (local_cd_p->ownership >> CH_OWNSHP_OFFSET_DSP) & + 1UL); +#endif /* MCU */ + + /* Setting interrupt handling */ + iapi_ChangeCallbackISR(local_cd_p, local_cd_p->callbackISR_ptr); + + /* Call initialization fn for polling synch on this channel */ + INIT_SLEEP(channelNumber); + + /* No user arg pointer yet */ + userArgTable[cd_p->channelNumber] = NULL; + + /* + * 6. read/write direction => enable/disable channel + */ +#ifdef MCU + channelPriorityMatx = &SDMA_CHNPRI_0; + channelPriorityMatx[channelNumber] = 1; +#endif /* MCU */ + + local_ccb_p->status.openedInit = TRUE; + iapi_ReleaseChannel(channelNumber); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/** Attempts to read nbyte from the data buffer descriptor associated with the + * channel channelNumber, into the user's data buffer pointed to by buf. + * + * Algorithm:\n + * - Check data structures are properly initialized: + * - Channel descriptor validity + * - Control block & Descriptor associated with the channel being worked on + * - Check initialization has been done for trusted channels + * - If transfer data size is used, check validity of combination transfer + * size/requested bytes + * - Set the 'D' done bits on all buffer descriptors + * - Starting of the channel + * - Synchronization mechanism handling: + * - for callback: just exit function + * - for polling: call the synchronization function then read data from + * buffer until either nbyte parameter is reached or all buffer descriptors + * have been processed. + * + * Notes:\n + * 1) Virtual DMA SDMA channels are unidirectional, an iapi_Read authorized + * on a channel means that we are expecting to receive from the SDMA. The + * meaning of an interrupt received from the SDMA is therefore that the + * data has been copied from the SDMA to the host's data buffers and is + * already passed on upper layers of the application.\n + * + * @param *cd_p chanenl descriptor for the channel to read from + * @param *buf buffer to receive the data + * @param nbyte number of bytes to read from channel + * + * @return + * - number of bytes read + * - -iapi_errno : in case of failure return negated value of iapi_errno + */ +int iapi_Read(channelDescriptor *cd_p, void *buf, unsigned short nbyte) +{ + int index = 0; + int readBytes; + int toRead; + int result = IAPI_SUCCESS; + unsigned int copyFinished; + int bufsize; + bufferDescriptor *bd_p; + channelControlBlock *ccb_p; + unsigned char *local_buf; + unsigned char chNum; + unsigned char div; + + iapi_errno = IAPI_ERR_NO_ERROR; + + /* + * 1. Check data structures are properly initialized + */ + /* Channel descriptor validity */ + if (cd_p == NULL) { + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Channel control block validity */ + if (cd_p->ccb_ptr == NULL) { + result = IAPI_ERR_CCB_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Control block & Descriptor associated with the channel being worked on */ + chNum = cd_p->channelNumber; + ccb_p = cd_p->ccb_ptr; + + /* Try to aquire channel */ + if (iapi_GetChannel(chNum) != 0) { + result = IAPI_ERR_CH_IN_USE | chNum; + iapi_errno = result; + return -result; + } + + /* Check if channel is already opened/initialized */ + if (ccb_p->status.openedInit == FALSE) { + result = + IAPI_ERR_CHANNEL_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | + chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + + /* Buffer descriptor validity */ + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + if (bd_p == NULL) { + result = + IAPI_ERR_BD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + + /* Check initialization has been done for trusted channels */ + if (cd_p->trust == TRUE) { + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + for (index = 0; index < cd_p->bufferDescNumber; index++) { + if ((bd_p->bufferAddr == NULL) + || (bd_p->mode.count == 0)) { + result = + IAPI_ERR_BD_UNINITIALIZED | + IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + /*If transfer data size is used, check that the required read length is + * divisible by transfer data size expressed in bytes + */ + if (cd_p->useDataSize) { + /*Check for divisibility only if data size different then 8bit */ + if (cd_p->dataSize != TRANSFER_8BIT) { + switch (cd_p->dataSize) { + case TRANSFER_32BIT: + div = 4; + break; + case TRANSFER_16BIT: + div = 2; + break; + case TRANSFER_24BIT: + div = 3; + break; + /*we should not get to default */ + default: + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + /*check the total number of bytes requested */ + if ((nbyte % div) != 0) { + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + /*now check the length of every BD */ + for (index = 0; index < cd_p->bufferDescNumber; index++) { + if ((bd_p->mode.count % div) != 0) { + result = + IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + } + + /* + * 2. Set the 'D' done bits on all buffer descriptors + */ + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + for (index = 0; index < cd_p->bufferDescNumber; index++) { + bd_p->mode.status |= BD_DONE; + bd_p++; + } + + /* + * 3. Starting of the channel + */ + iapi_lowStartChannel(chNum); + ccb_p->status.execute = TRUE; + readBytes = 0; + + /* + * 4. Synchronization mechanism handling + */ + if (cd_p->callbackSynch == DEFAULT_POLL) { + iapi_SynchChannel(chNum); + + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + toRead = nbyte; + copyFinished = FALSE; + local_buf = (unsigned char *)buf; + + /* + * Check the 'RROR' bit on all buffer descriptors, set error number + * and return IAPI_FAILURE if set. + */ + for (index = 0; index < cd_p->bufferDescNumber; index++) { + if (bd_p->mode.status & BD_RROR) { + result = IAPI_ERR_RROR_BIT_READ | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + + /* + * 5. Read loop + */ + + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + while (!copyFinished) { + if (!(bd_p->mode.status & BD_DONE)) { + if (cd_p->trust == FALSE) { + bufsize = cd_p->bufferSize; + } else { + bufsize = bd_p->mode.count; + } + /*if L bit is set, read only "count" bytes and exit the loop */ + if (bd_p->mode.status & BD_LAST) { + bufsize = bd_p->mode.count; + copyFinished = TRUE; + } + if (toRead > bufsize) { + if (cd_p->trust == FALSE) { + iapi_memcpy(local_buf, + iapi_Phys2Virt + (bd_p->bufferAddr), + bufsize); + local_buf += bufsize; + } + readBytes += bufsize; + toRead -= bufsize; + /*advance bd_p only if bit L is not set. The loop will exit anyway. */ + if (!(bd_p->mode.status & BD_LAST)) { + if (bd_p->mode.status & BD_WRAP) { + bd_p = + (bufferDescriptor *) + iapi_Phys2Virt + (ccb_p->baseBDptr); + } else if (((bufferDescriptor *) + iapi_Phys2Virt + (ccb_p->baseBDptr) + + + (cd_p->bufferDescNumber + - + 1) * + sizeof + (bufferDescriptor)) + != bd_p) { + bd_p++; + } else { + /* finished here : end of buffer descriptors */ + copyFinished = TRUE; + } + } + } else { + if (cd_p->trust == FALSE) { + iapi_memcpy(local_buf, + iapi_Phys2Virt + (bd_p->bufferAddr), + toRead); + local_buf += toRead; + } + readBytes += toRead; + toRead = 0; + /* finished successfully : readBytes = nbytes */ + copyFinished = TRUE; + } + } else { + /* finished here : buffer not already done */ + copyFinished = TRUE; + } + } + iapi_ReleaseChannel(chNum); + } + + /* + *If synchronization type is callback, the user of I.API must + *release the channel + */ + return readBytes; +} + +/* ***************************************************************************/ +/*Attempts to write nbyte from the buffer pointed to by buf to the channel + * data buffers associated with the opened channel number channelNumber + * + * Algorithm:\n + * + * - Check data structures are properly initialized: + * - Channel descriptor validity + * - Channel control block validity + * - Buffer descriptor validity + * - If transfer data size is used, check validity of combination transfer + * size/requested bytes + * - Write loop\n + * Write occurs in the buffer acceded form buffer descriptor and continues + * to the "next" buffer which can be:\n + * -# the last BD of the ring so re-start from beginning\n + * -# the last BD of the BD array but no ring so finish\n + * -# (general case) the next BD in the BD array\n + * And copy continues until data fit in the current buffer or the nbyte + * parameter is reached. + * - Starting of the channel + * + * Notes:\n + * 1) Virtual DMA SDMA channels are unidirectionnal, an iapi_Write authorized + * on a channel means that we are expecting to send to the SDMA. The + * meaning of an interrupt received from the SDMA is therfore that the + * data has been delivered to the SDMA. + * + * @param *cd_p chanenl descriptor for the channel to write to + * @param *buf buffer with data to be written + * @param nbyte number of bytes to write to channel + * + * @return + * - number of bytes written + * - -iapi_errno if failure + */ +int iapi_Write(channelDescriptor *cd_p, void *buf, unsigned short nbyte) +{ + unsigned int writtenBytes = 0; + unsigned int toWrite; + int result = IAPI_SUCCESS; + unsigned int copyFinished; + unsigned int buffsize; + unsigned int index = 0; + bufferDescriptor *bd_p; + channelControlBlock *ccb_p; + unsigned char *local_buf; + unsigned char chNum; + unsigned char div; + + iapi_errno = IAPI_ERR_NO_ERROR; + + /* + * 1. Check data structures are properly initialized + */ + /* Channel descriptor validity */ + if (cd_p == NULL) { + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Channel control block validity */ + if (cd_p->ccb_ptr == NULL) { + result = IAPI_ERR_CCB_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Control block & Descriptpor associated with the channel being worked on */ + chNum = cd_p->channelNumber; + ccb_p = cd_p->ccb_ptr; + + /* Try to aquire channel */ + if (iapi_GetChannel(chNum) != 0) { + result = IAPI_ERR_CH_IN_USE | chNum; + iapi_errno = result; + return -result; + } + + /* Buffer descriptor validity */ + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + if (bd_p == NULL) { + result = + IAPI_ERR_BD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + + /* Check initialization has been done for trusted channels */ + if (cd_p->trust == TRUE) { + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + for (index = 0; index < cd_p->bufferDescNumber; index++) { + if ((bd_p->bufferAddr == NULL) + || (bd_p->mode.count == 0)) { + result = + IAPI_ERR_BD_UNINITIALIZED | + IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + /*If transfer data size is used, check that the required write length is + * divisible by transfer data size expressed in bytes + */ + if (cd_p->useDataSize) { + /*Check for divisibility only if data size different then 8bit */ + if (cd_p->dataSize != TRANSFER_8BIT) { + switch (cd_p->dataSize) { + case TRANSFER_32BIT: + div = 4; + break; + case TRANSFER_16BIT: + div = 2; + break; + case TRANSFER_24BIT: + div = 3; + break; + /*we should not get to default */ + default: + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + /*check the total number of bytes requested */ + if ((nbyte % div) != 0) { + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + /*now check the length of every BD */ + for (index = 0; index < cd_p->bufferDescNumber; index++) { + if ((bd_p->mode.count % div) != 0) { + result = + IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + } + + /* + * 2. Write loop + */ + + local_buf = (unsigned char *)buf; + toWrite = nbyte; + copyFinished = FALSE; + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + + while (!copyFinished) { + + /* variable buffsize contains the nb of bytes that the SDMA will transfer at each pass of the while loop */ + + /* in NON trusted mode, buffsize is copied from Channel descriptor bufferSize (same size for all transfers) */ + if (cd_p->trust == FALSE) { + buffsize = cd_p->bufferSize; + } + /* in TRUSTED mode, it's up to the user to specify the size of each buffer thru an IoCtl call */ + /* This IoCtl has directly modified the bd_p->mode.count */ + /* therefore, buffersize is copied from the bd_p->mode.count */ + else { + buffsize = bd_p->mode.count; + } + + /* in any mode (trusted or non trusted), the transfer size must be overridden by */ + /* "toWrite" when there is less remaining bytes to transfer than the current buffer size */ + if (toWrite < buffsize) { + buffsize = toWrite; + } + + if (!(bd_p->mode.status & BD_DONE)) { + /* More data to write than a single buffer can contain */ + if (cd_p->trust == FALSE) { + iapi_memcpy(iapi_Phys2Virt(bd_p->bufferAddr), + local_buf, buffsize); + local_buf += buffsize; + } + + /* update the BD count that will be used by the SDMA to transfer the proper nb of bytes */ + bd_p->mode.count = buffsize; + + bd_p->mode.status |= BD_DONE; + writtenBytes += buffsize; + toWrite -= buffsize; + /* Prepares access to the "next" buffer */ + /* - case 1 - finished successfully : writtenBytes = nbytes */ + if (toWrite == 0) { + copyFinished = TRUE; + } + /* - case 2 - Last BD and WRAP bit set so re-start from beginning */ + /*else if ((bd_p->mode.status & BD_WRAP)){ + bd_p = (bufferDescriptor *)iapi_Phys2Virt(ccb_p->baseBDptr); + } */ + /* - case 3 - Last BD of the BD but nor ring */ + else if (((bufferDescriptor *) + iapi_Phys2Virt(ccb_p->baseBDptr) + + (cd_p->bufferDescNumber - + 1) * sizeof(bufferDescriptor)) == bd_p) { + copyFinished = TRUE; + } + /* - case 4 - general : next BD in the BD array */ + else { + bd_p++; + } + + } else { + /* finished here : buffer not already done */ + copyFinished = TRUE; + } + } + + ccb_p->currentBDptr = ccb_p->baseBDptr; + + /* + * 3. Starting of the channel + */ + iapi_lowStartChannel(chNum); + ccb_p->status.execute = TRUE; + + if (cd_p->callbackSynch == DEFAULT_POLL) { + iapi_SynchChannel(chNum); + /* + * Check the 'RROR' bit on all buffer descriptors, set error number + * and return IAPI_FAILURE if set. + */ + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + for (index = 0; index < cd_p->bufferDescNumber; index++) { + if (bd_p->mode.status & BD_RROR) { + result = IAPI_ERR_RROR_BIT_WRITE | chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + iapi_ReleaseChannel(chNum); + } + + /* + *If synchronization type is callback, the user of I.API must + *release the channel + */ + return writtenBytes; +} + +/* ***************************************************************************/ +/* This function is used to receive data from the SDMA. + * + * Algorithm:\n + * + * The data control structure would be copied to IPCv1 complied Buffer + * Descriptor Array. This array shall be allocated from non cacheable memory. + * It would then provide this buffer descriptor array as an input to SDMA using + * channel control block and then configure the Host Enable (HE) or + * DSP enable (DE) bit of SDMA for the channel used for this transfer depending + * on the source. + * + * Notes:\n + * Virtual DMA channels are unidirectional, an iapi_Write_ipcv2 authorized + * on a channel means that source processor is expecting to send to the destination + * processor. The meaning of an interrupt received from the SDMA notifies that the + * data has been delivered to the destination processor. + * + * @param *cd_p chanenl descriptor for the channel to receive from + * @param *data_control_struct_ipcv2 + + * Data Control structure: + * ------------------------- + * | Data Node Descriptor 1| + * ------------------------- + * | Data Node Descriptor 2| + * ------------------------- + * | : | + * | : | + * ------------------------- + * |Data Node Descriptor n | + * ------------------------- + * + * Data Node Descriptor (Buffer Descriptor): + *------------------------------------------------------------------------------ + *| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0| + *------------------------------------------------------------------------------ + *| L E D R R R R R |<---- Reserved ----> |<- Length-> | + *------------------------------------------------------------------------------ + *| <---------------------------- Data Ptr ----------------------------------->| + *------------------------------------------------------------------------------ + * + * L bit (LAST): If set, means that this buffer of data is the last buffer of the frame + * E bit (END): If set, we reached the end of the buffers passed to the function + * D bit (DONE): Only valid on the read callback. When set, means that the buffer has been + * filled by the SDMA. + * Length: Length of data pointed by this node in bytes + * Data Ptr: Pointer to the data pointed to by this node. + * The Function Shall not be called for the same channel unless the Read callback has been + * received for channel for which it has been called already. + * + * @return + * - IAPI_SUCCESS on success, IAPI_ERROR otherwise + * + *- -iapi_errno if failure + */ + +int iapi_Read_ipcv2(channelDescriptor *cd_p, void *data_control_struct_ipcv2) +{ + channelControlBlock *ccb_p; + +/* The Parameters passed are considered to be validated by the upper layers*/ + + bufferDescriptor_ipcv1_v2 *bd_ipcv2_p; + dataNodeDescriptor *dnd_p = + (dataNodeDescriptor *) data_control_struct_ipcv2; + + ccb_p = cd_p->ccb_ptr; + iapi_errno = IAPI_ERR_NO_ERROR; + + if (ccb_p->baseBDptr == NULL) { + iapi_errno = IAPI_ERR_BD_UNINITIALIZED; + return -(IAPI_ERR_BD_UNINITIALIZED); + } + + ccb_p->currentBDptr = ccb_p->baseBDptr; + + /* Copy the data Node descriptor information to new BDs */ + bd_ipcv2_p = + (bufferDescriptor_ipcv1_v2 *) iapi_Phys2Virt(ccb_p->baseBDptr); + + while (1) { + bd_ipcv2_p->bufferAddr = dnd_p->bufferAddr; + bd_ipcv2_p->mode.count = dnd_p->mode.count; +#ifdef MCU + bd_ipcv2_p->mode.endianness = 1; +#endif +#ifdef DSP + bd_ipcv2_p->mode.endianness = 0; +#endif + + bd_ipcv2_p->mode.status = + dnd_2_bd_status[dnd_p->mode.status & GET_LED_MASK]; + + if ((dnd_p->mode.status & DND_END_OF_XFER) != 0) { + /* Break the loop at End of Transfer */ + break; + + } + bd_ipcv2_p++; + dnd_p++; + + } + /* + * Store the buffer address + */ + dnd_read_control_struct[cd_p->channelNumber] = + (dataNodeDescriptor *) data_control_struct_ipcv2; + /* + * Register the Call Back + */ + + iapi_AttachCallbackISR(cd_p, iapi_read_ipcv2_callback); + + /* + * Starting of the channel + */ + iapi_lowStartChannel(cd_p->channelNumber); + ccb_p->status.execute = TRUE; + + return IAPI_SUCCESS; + +} + +/* ***************************************************************************/ +/* + * The function is used send a group of buffers to SDMA. + * Algorithm:\n + * + * The data control structure would be copied to IPCv1 complied Buffer + * Descriptor Array. This array shall be allocated from non cacheable memory. + * It would then provide this buffer descriptor array as an input to SDMA using + * channel control block and then configure the Host Enable (HE) or + * DSP enable (DE) bit of SDMA for the channel used for this transfer depending + * on the source. + * The Function Shall not be called for the same channel unless the Read callback has been + * received for channel for which it has been called already. + * + * Notes:\n + * Virtual DMA channels are unidirectional, an iapi_Write_ipcv2 authorized + * on a channel means that source processor is expecting to send to the destination + * processor. The meaning of an interrupt received from the SDMA notifies that the + * data has been delivered to the destination processor. + * + * @param *cd_p chanenl descriptor for the channel to write to + * @param *data_control_struct_ipcv2 + + * Data Control structure: + * ------------------------- + * | Data Node Descriptor 1| + * ------------------------- + * | Data Node Descriptor 2| + * ------------------------- + * | : | + * | : | + * ------------------------- + * |Data Node Descriptor n | + * ------------------------- + * + * Data Node Descriptor (Buffer Descriptor): + *------------------------------------------------------------------------------ + *| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0| + *------------------------------------------------------------------------------ + *| L E D R R R R R |<---- Reserved ----> |<- Length-> | + *------------------------------------------------------------------------------ + *| <---------------------------- Data Ptr ----------------------------------->| + *------------------------------------------------------------------------------ + * + * L bit (LAST): If set, means that this buffer of data is the last buffer of the frame + * E bit (END): If set, we reached the end of the buffers passed to the function + * D bit (DONE): Only valid on the read callback. When set, means that the buffer has been + * filled by the SDMA. + * Length: Length of data pointed by this node in bytes + * Data Ptr: Pointer to the data pointed to by this node. + * + * + * @return + * - iapi sucess on success. + * - -iapi_errno if failure + */ + +int iapi_Write_ipcv2(channelDescriptor *cd_p, void *data_control_struct_ipcv2) +{ + + channelControlBlock *ccb_p; + +/* The Parameters passed are considered to be validated by the upper layers*/ + + bufferDescriptor_ipcv1_v2 *bd_ipcv2_p; + dataNodeDescriptor *dnd_p = + (dataNodeDescriptor *) data_control_struct_ipcv2; + ccb_p = cd_p->ccb_ptr; + iapi_errno = IAPI_ERR_NO_ERROR; + + if (ccb_p->baseBDptr == NULL) { + iapi_errno = IAPI_ERR_BD_UNINITIALIZED; + return -(IAPI_ERR_BD_UNINITIALIZED); + } + + ccb_p->currentBDptr = ccb_p->baseBDptr; + + bd_ipcv2_p = + (bufferDescriptor_ipcv1_v2 *) iapi_Phys2Virt(ccb_p->currentBDptr); + /* Copy the data Node descriptor information to new BDs */ + while (1) { + bd_ipcv2_p->bufferAddr = dnd_p->bufferAddr; + bd_ipcv2_p->mode.count = dnd_p->mode.count; + +#ifdef MCU + bd_ipcv2_p->mode.endianness = 1; +#endif +#ifdef DSP + bd_ipcv2_p->mode.endianness = 0; +#endif + + bd_ipcv2_p->mode.status = + dnd_2_bd_status[dnd_p->mode.status & GET_LED_MASK]; + + if ((dnd_p->mode.status & DND_END_OF_XFER) != 0) { + /* Break the loop at End of Transfer */ + break; + } + bd_ipcv2_p++; + dnd_p++; + + } + + /* + * Starting of the channel + */ + iapi_lowStartChannel(cd_p->channelNumber); + ccb_p->status.execute = TRUE; + + return IAPI_SUCCESS; + +} + +/* ***************************************************************************/ +/** Call back ISR for the IPCv2 Receive. + * + * Algorithm:\n + * - This would copy back the informationfrom IPCv1 BD to IPCv2 BD on + * the receiving processor + * + * @return + * - void + */ + +void iapi_read_ipcv2_callback(struct iapi_channelDescriptor *cd_p, void *data) +{ + /*cd_p->ccb_ptr->channelDNDBuffer; */ + dataNodeDescriptor *dnd_p = dnd_read_control_struct[cd_p->channelNumber]; + bufferDescriptor_ipcv1_v2 *bd_ipcv2_p = + (bufferDescriptor_ipcv1_v2 *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + int index = MAX_BD_NUM - 1; + + do { + dnd_p->mode.status = 0; + dnd_p->mode.count = bd_ipcv2_p->mode.count; + + dnd_p->mode.status |= + bd_ipcv2_p->mode.status & BD_DONE ? 0x00 : DND_DONE; + dnd_p->mode.status |= + bd_ipcv2_p-> + mode.status & BD_IPCV2_END_OF_FRAME ? DND_END_OF_FRAME : + 0x00; + dnd_p->mode.status |= + bd_ipcv2_p->mode.status & BD_LAST ? DND_END_OF_XFER : 0x00; + cd_p->ccb_ptr->currentBDptr = + (bufferDescriptor *) iapi_Virt2Phys(bd_ipcv2_p); + + if ((bd_ipcv2_p->mode.status & BD_LAST) != 0 || + (bd_ipcv2_p->mode.status & BD_CONT) == 0) + break; + dnd_p++; + bd_ipcv2_p++; + + } while (index--); + + /*Call back the Original ISR */ + cd_p->callbackISR_ptr(cd_p, data); +} + +/* ***************************************************************************/ +/**Terminates a channel. + * + * Algorithm:\n + * - Check input parameters ans data structures + * - Check that all buffes have been processed (test all 'D' bits) + * - Stop the channel execution + * - Free alocated memory structures + * - Re-instantiate default interrupt handling + * + * @param *cd_p chanenl descriptor for the channel to close + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : close failed + */ +int iapi_Close(channelDescriptor *cd_p) +{ + int index = 0; + int result = IAPI_SUCCESS; + unsigned char chNum; + bufferDescriptor *bd_p; + channelControlBlock *ccb_p; + + /* + * 1. Check input parameters ans data structures + */ + if (cd_p != NULL) { + if (cd_p->ccb_ptr != NULL) { + chNum = cd_p->channelNumber; + ccb_p = cd_p->ccb_ptr; + } else { + result = + IAPI_ERR_NO_CCB_DEFINED | IAPI_ERR_CH_AVAILABLE; + iapi_errno = result; + return -result; + } + } else { + result = IAPI_ERR_CD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE; + iapi_errno = result; + return -result; + } + /* Try to aquire channel */ + if (iapi_GetChannel(chNum) != 0) { + result = IAPI_ERR_CH_IN_USE | chNum; + iapi_errno = result; + return -result; + } + + /* + * 2. Check that all buffes have been processed (test all 'D' bits), + * only if the forceClose bit in channel descriptor is set to FALSE + */ + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + if (bd_p == NULL) { + result = + IAPI_ERR_BD_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + return -result; + } + if (cd_p->forceClose == FALSE) { + for (index = cd_p->bufferDescNumber; index > 0; index--) { + if (bd_p->mode.status & BD_DONE) { + result = + IAPI_ERR_CLOSE | IAPI_ERR_CH_AVAILABLE | + chNum; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } + bd_p++; + } + } + /*if the closing is forced,mark channel unused,set BD ownership to processor */ + else { + ccb_p->status.execute = FALSE; + for (index = cd_p->bufferDescNumber; index > 0; index--) { + bd_p->mode.status &= ~BD_DONE; + bd_p++; + } + } + + /* + * 3. Stop the channel execution + */ + iapi_lowStopChannel(chNum); + + /* + * 4. Free alocated memory structures + */ + if (cd_p->trust == FALSE) { + bd_p = (bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr); + for (index = cd_p->bufferDescNumber; index > 0; index--) { + FREE(iapi_Phys2Virt(bd_p->bufferAddr)); + bd_p++; + } + } + + /* + * 5. Re-instantiate default interrupt handling + */ + iapi_DetachCallbackISR(cd_p); + FREE((bufferDescriptor *) iapi_Phys2Virt(ccb_p->baseBDptr)); + FREE(cd_p); + ccb_p->baseBDptr = NULL; + ccb_p->currentBDptr = NULL; + ccb_p->channelDescriptor = NULL; + ccb_p->status.openedInit = FALSE; + + iapi_ReleaseChannel(chNum); + + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**The request argument selects the control function to be performed. + * + * Algorithm:\n + * + * - Check data structures are properly initialized: + * - Channel descriptor validity + * - Channel control block validity + * - The ctlRequest parameter contains in the lower 16 bits the control code of + * the change to be performed, and in the upper 16 bits, the BD to be + * modified if the change affects a BD od the channel. + * - Selection of the parameter to change and appropriate sanity checks: + * - Channel Descriptor: changes the pointer to the channel descriptor + * structure, the pointer to the new channel descriptor is given in the third + * argument call + * - Buffer Descriptor Number: changes the number of buffer descriptor for the + * channel + * - Buffer size: changes the size of the data buffers pointed to by the + * buffer descriptor; note that all buffer descriptors are assumed to have the + * same size for a given buffer descripotr chain + * - Blocking policy: changes the blocking policy for the read and write calls + * - Ownership: changes direction: turnaround + * - Synchronization method: changes the callback type, default or user. The* + * callback function table is set accordingly + * - Trust property: trust can only be changed through ChangeChannelDesc first + * request, this guarantees the close/open sequence for the channel + * - Callback Interrupt service routine pointer: changes the callback function + * pointer, when this method is used, to replace it with a new one + * - Channel control block pointer: not available + * - Priority: changes the channel priority directly in SDMA register + * - Watermark level: changes the value of the peripheral watermark level that + * passed to the script. The new value is passed in the third parameter call. + * - Wrap bit: changes to set to 1 the Wrap bit of the last buffer descriptor + * + * @param *cd_p channel descriptor for the channel to modify + * @param ctlRequest request control code and, if tha case, number of BD to be + * changed + * @param param parameter for the modification + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : operation failed + */ +int +iapi_IoCtl(channelDescriptor *cd_p, unsigned long ctlRequest, + unsigned long param) +{ + int retvalue; + int result = IAPI_SUCCESS; + unsigned char chNum; + unsigned long clean_ctlRequest; /* lower 16 bits of the ctlRequest */ + unsigned long bd_num; /* upper 16 bits of the ctlRequest */ + + /* + * 1. Check data structures are properly initialized + */ + /* Channel descriptor validity */ + if (cd_p == NULL) { + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Channel control block validity */ + if (cd_p->ccb_ptr == NULL) { + result = IAPI_ERR_CCB_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Control block & Descriptor associated with the channel being worked on */ + chNum = cd_p->channelNumber; + + /* Remove, if exists, BD number specified in upper bits of ctlRequest */ + clean_ctlRequest = ctlRequest & (~BD_NUM_MASK); + + /* Extract, if exists, BD number specified in upper bits of ctlRequest */ + bd_num = (ctlRequest & BD_NUM_MASK) >> BD_NUM_OFFSET; + + /* Check that the bd_num is valid */ + if (bd_num > cd_p->bufferDescNumber) { + result = IAPI_ERR_INVALID_PARAMETER | chNum; + iapi_errno = result; + return -result; + } + + /*All checks OK, try to aquire channel */ + if (iapi_GetChannel(chNum) != 0) { + result = IAPI_ERR_CH_IN_USE | chNum; + iapi_errno = result; + return -result; + } + + /* + * 2. Selection of the parameter to change and appropriate sanity checks + */ + switch (clean_ctlRequest) { + + /* + * Channel Descriptor + * --- Changes the pointer to the channel descriptor structure: the pointer + * to the new channel descriptor is given in the third argument call. + */ + case IAPI_CHANGE_CHANDESC: + if ((void *)param == NULL) { + result = IAPI_ERR_INVALID_PARAMETER; + iapi_errno = result; + iapi_ReleaseChannel(chNum); + return -result; + } else { + channelDescriptor *chParam = + (channelDescriptor *) param; + if (chParam->channelNumber != chNum) { + /* Release ch so it can be aquired by the Close fn */ + iapi_ReleaseChannel(chNum); + result = iapi_Close(cd_p); + if (result == IAPI_SUCCESS) { + FREE((void *)cd_p); + iapi_AllocChannelDesc(&cd_p, + chParam->channelNumber); + iapi_memcpy((void *)cd_p, + (void *)chParam, + sizeof(channelDescriptor)); + /* Channel is released allready, so Open can get the channel */ + result = + iapi_Open(cd_p, + chParam->channelNumber); + if (result != IAPI_SUCCESS) { + return result; /* error code already set in iapi_Open */ + } + } else { + return result; /* error code already set in iapi_Close */ + } + } else { + result = + IAPI_ERR_CD_CHANGE | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_ReleaseChannel(chNum); + iapi_errno = result; + return -result; + } + return IAPI_SUCCESS; + } + + /* + * Buffer Descriptor Number + * --- Changes the number of buffer descriptor for the channel. + */ + case IAPI_CHANGE_BDNUM: + result = + iapi_ChangeChannelDesc(cd_p, IAPI_BUFFERDESCNUMBER, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Buffer size + * --- Changes the size of the data buffers pointed to by the buffer + * descriptor; note that all buffer descriptors are assumed to have the + * same size for a given buffer descripotr chain. + */ + case IAPI_CHANGE_BUFFSIZE: + result = iapi_ChangeChannelDesc(cd_p, IAPI_BUFFERSIZE, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Blocking policy + * --- Changes the blocking policy for the read and write calls. + */ + case IAPI_CHANGE_CHANBLOCK: + result = iapi_ChangeChannelDesc(cd_p, IAPI_BLOCKING, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Ownership + * --- Changes direction: turnaround + */ + case IAPI_CHANGE_OWNERSHIP: + result = iapi_ChangeChannelDesc(cd_p, IAPI_OWNERSHIP, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Synchronization method + * --- Changes the callback type, default or user. The callback function + * table is set accordingly. + */ + case IAPI_CHANGE_SYNCH: + result = + iapi_ChangeChannelDesc(cd_p, IAPI_CALLBACKSYNCH, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Trust property + * --- trust can only be changed through ChangeChannelDesc first request, + * this guarantees the close/open sequence for the channel. + */ + case IAPI_CHANGE_TRUST: + result = iapi_ChangeChannelDesc(cd_p, IAPI_TRUST, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Callback Interrupt service routine pointer + * --- Cahnges the callback function pointer, when this method is used, to + * replace it with a new one. + */ + case IAPI_CHANGE_CALLBACKFUNC: + result = + iapi_ChangeChannelDesc(cd_p, IAPI_CALLBACKISR_PTR, param); + iapi_ReleaseChannel(chNum); + return result; + + /* + * Channel control block pointer + * --- NA + */ + case IAPI_CHANGE_CHANCCB: + result = iapi_ChangeChannelDesc(cd_p, IAPI_CCB_PTR, param); + iapi_ReleaseChannel(chNum); + return result; + +#ifdef MCU + /* + * Priority + * --- Changes the channel priority directly in SDMA register + */ + case IAPI_CHANGE_PRIORITY: + { + volatile unsigned long *ChannelPriorities = + &SDMA_CHNPRI_0; + if (param < MAX_CH_PRIORITY) { + ChannelPriorities[cd_p->channelNumber] = param; + } else { + iapi_ReleaseChannel(chNum); + return IAPI_FAILURE; + } + } + break; +#endif /* MCU */ + + /* + * Wrap + * --- Set to 1 the wrap bit of the last buffer descriptor of the array. + * it provides the possibility to have a circular buffer structure. + */ + case IAPI_CHANGE_BDWRAP: + { + result = + iapi_ChangeChannelDesc(cd_p, IAPI_BDWRAP, param); + iapi_ReleaseChannel(chNum); + return result; + } + + /* + * Watermark + * --- Changes the value of the peripheral watermark level that triggers + * a DMA request. It impacts context of the channel, therefore channel 0 + * must be started to update the context with this new value. + */ + case IAPI_CHANGE_WATERMARK: + { + result = iapi_ChangeChannelDesc(cd_p, IAPI_WML, param); + iapi_ReleaseChannel(chNum); + return result; + } + /* + * INTR + * --- Set the INTR bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_SET_BDINTR: + { + bufferDescriptor *bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if (param == SET_BIT_ALL) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.status |= BD_INTR; + bde_p++; + } + } else if (param < cd_p->bufferDescNumber) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status |= BD_INTR; + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * INTR + * --- Unset the INTR bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_UNSET_BDINTR: + { + bufferDescriptor *bde_p; + + int j = 0; + + retvalue = IAPI_SUCCESS; + if (param == SET_BIT_ALL) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.status &= ~BD_INTR; + bde_p++; + } + } else if (param < cd_p->bufferDescNumber) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status &= ~BD_INTR; + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } +/* + * EventMask1 + * --- Changes the value of the eventMask1 + */ + case IAPI_CHANGE_EVTMASK1: + { + cd_p->eventMask1 = param; + } + break; + /* + * EventMask2 + * --- Changes the value of the eventMask2 + */ + case IAPI_CHANGE_EVTMASK2: + { + cd_p->eventMask2 = param; + } + break; + /* + * Peripheral Address + * --- Changes the value of the peripheralAddr + */ + case IAPI_CHANGE_PERIPHADDR: + { + cd_p->peripheralAddr = param; + } + break; + /* + * Cont + * --- Set the CONT bit on specified BD on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_SET_BDCONT: + { + bufferDescriptor *bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if (param == SET_BIT_ALL) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.status |= BD_CONT; + bde_p++; + } + } else if (param < cd_p->bufferDescNumber) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status |= BD_CONT; + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * Cont + * --- Unset the CONT bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_UNSET_BDCONT: + { + bufferDescriptor *bde_p; + + int j = 0; + + retvalue = IAPI_SUCCESS; + if (param == SET_BIT_ALL) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.status &= ~BD_CONT; + bde_p++; + } + } else if (param < cd_p->bufferDescNumber) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status &= ~BD_CONT; + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + + /* + * EXTD + * --- Set the EXTD bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_SET_BDEXTD: + { + bufferDescriptor *bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if (param == SET_BIT_ALL) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.status |= BD_EXTD; + bde_p++; + } + } else if (param < cd_p->bufferDescNumber) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status |= BD_EXTD; + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * EXTD + * --- Unset the EXTD bit on specified BD or on all BD's if SET_BIT_ALL + * is passed as parameter. + */ + case IAPI_CHANGE_UNSET_BDEXTD: + { + bufferDescriptor *bde_p; + + int j = 0; + + retvalue = IAPI_SUCCESS; + if (param == SET_BIT_ALL) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.status &= ~BD_EXTD; + bde_p++; + } + } else if (param < cd_p->bufferDescNumber) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.status &= ~BD_EXTD; + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + + /* + * TRANSFER SIZE to be used for this channel + * --- Set the transfer size used indicator and code for transfer size in + * the CD + */ + case IAPI_CHANGE_SET_TRANSFER_CD: + { + bufferDescriptor *bde_p; + int j = 0; + retvalue = IAPI_SUCCESS; + if ((param == TRANSFER_8BIT) + || (param == TRANSFER_16BIT) + || (param == TRANSFER_24BIT) + || (param == TRANSFER_32BIT)) { + cd_p->useDataSize = TRUE; + cd_p->dataSize = param; + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.command = param; + bde_p++; + } + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + + /* + * USER_ARG + * --- Set the user selectable pointer to be received by the callback + * function, if IRQ synch is used + */ + case IAPI_CHANGE_USER_ARG: + { + userArgTable[cd_p->channelNumber] = (void *)param; + iapi_ReleaseChannel(chNum); + return IAPI_SUCCESS; + } + /* + * FORCE_CLOSE + * --- Set the forceClose bit in channelDescriptor to value passed in param. + * If this bit is TRUE, the channel in closed even if some BD are still + * owned by the SDMA. + */ + case IAPI_CHANGE_FORCE_CLOSE: + { + retvalue = IAPI_SUCCESS; + if ((param == TRUE) || (param == FALSE)) { + cd_p->forceClose = param; + } else { + iapi_errno = + IAPI_ERR_INVALID_PARAMETER | + cd_p->channelNumber; + retvalue = -iapi_errno; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * TRANSFER type + * --- Set the last 2 bits in the command field of the BD to specify the + * transfer type 8, 16, 24, or 32 bits on all BD's, allready set in the CD + */ + case IAPI_CHANGE_SET_TRANSFER: + { + bufferDescriptor *bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if ((param == TRANSFER_8BIT) + || (param == TRANSFER_16BIT) + || (param == TRANSFER_24BIT) + || (param == TRANSFER_32BIT)) { + bde_p = cd_p->ccb_ptr->baseBDptr; + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.command = param; + bde_p++; + } + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * BUFFER address + * --- Change buffer address in BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_SET_BUFFERADDR: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + + /* DO NOT translate address to physical */ + bde_p->bufferAddr = (void *)param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * BUFFER address + * --- Get the buffer address from the BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_GET_BUFFERADDR: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + /* Translate to virtual */ + *((unsigned long *)param) = + (unsigned long)bde_p->bufferAddr; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * EXTENDED BUFFER address + * --- Change extended buffer address in BD specified in the upper 16 bits + * of the ctlRequest. + */ + case IAPI_CHANGE_SET_EXTDBUFFERADDR: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + + /* DO NOT translate address to physical. The user might want something else + *here + */ + bde_p->extBufferAddr = (void *)param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * EXTENDED BUFFER address + * --- Get extended buffer address from the BD specified in the upper 16 bits + * of the ctlRequest. + */ + case IAPI_CHANGE_GET_EXTDBUFFERADDR: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + + /* DO NOT translate address to vitual - user knows what is here. + */ + *((unsigned long *)param) = + (unsigned long)bde_p->extBufferAddr; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * COMMAND field + * --- Change command field in BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_SET_COMMAND: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + /* Update command field */ + bde_p->mode.command = param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * COMMAND field + * --- Get the command field from the BD specified in the upper 16 bits + * of the ctlRequest. + */ + case IAPI_CHANGE_GET_COMMAND: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + /* Get the command field */ + *((unsigned long *)param) = bde_p->mode.command; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * COUNT field + * --- Change count field in BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_SET_COUNT: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + /* Update count field */ + bde_p->mode.count = param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * COUNT field + * --- Get the count field of the BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_GET_COUNT: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + /* Update count field */ + *((unsigned long *)param) = bde_p->mode.count; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * STATUS field + * --- Change status field in BD specified in the upper 16 bits of the + * ctlRequest. + */ + case IAPI_CHANGE_SET_STATUS: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + /* Update status field */ + bde_p->mode.status = param; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + /* + * STATUS field + * --- Get the status field of the BD specified in the upper 16 bits + * of the ctlRequest. + */ + case IAPI_CHANGE_GET_STATUS: + { + bufferDescriptor *bde_p; + retvalue = IAPI_SUCCESS; + + /* Get pointer to the BD structure to change */ + bde_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bde_p += bd_num; + /* Update status field */ + *((unsigned long *)param) = bde_p->mode.status; + + iapi_ReleaseChannel(chNum); + return retvalue; + } + +#ifdef MCU + /* + * Endianness + * --- Set the ENDIANNESS indicator in the command filed of the specified BD + * or on all BD's if SET_BIT_ALL is passed as parameter. + */ + case IAPI_CHANGE_SET_ENDIANNESS: + { + bufferDescriptor *bde_p; + int j = 0; + + retvalue = IAPI_SUCCESS; + if (param == SET_BIT_ALL) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (j = 0; j < cd_p->bufferDescNumber; j++) { + bde_p->mode.command = CHANGE_ENDIANNESS; + bde_p++; + } + } else if (param < cd_p->bufferDescNumber) { + bde_p = + (bufferDescriptor *) + iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr) + + param; + bde_p->mode.command = CHANGE_ENDIANNESS; + } else { + retvalue = IAPI_FAILURE; + } + iapi_ReleaseChannel(chNum); + return retvalue; + } +#endif + +#ifdef SDMA_SKYE +#ifdef MCU + + /* + * SDMA State + * --- Enter the SDMA into LOCK Mode. No RAM updation allowed except same Context + * update with same PC Value. + */ + case IAPI_ENTER_LOCK_MODE: + { + if (param == RESET_CLEAR_LOCK) { + SDMA_SDMA_LOCK = (1 << RESET_CLR_BIT_OFFSET); + SDMA_SDMA_LOCK = (1 << LOCK_BIT_OFFSET); + iapi_SdmaState = LOCK; + } else if (param == RESET_NOCLEAR_LOCK) { + SDMA_SDMA_LOCK = (1 << LOCK_BIT_OFFSET); + iapi_SdmaState = LOCK; + } + + } + break; + +#endif +#endif + default: + retvalue = + IAPI_ERR_CD_CHANGE_UNKNOWN | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = retvalue; + iapi_ReleaseChannel(chNum); + return -retvalue; + } + + iapi_ReleaseChannel(chNum); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**Initialization of the SDMA - opening of channel 0, download RAM image. + * + * Algorithm:\n + * - open channel 0 + * - if ram_image pointer passed is not NULL, download RAM image to SDMA + * + * @param + * - cd_p channel descriptor pointer for channel 0 + * - ram_image pointer to RAM image to download, or NULL if this operation + * is not required + * - code_size size of the RAM image, in bytes + * - start_addr start address for the RAM image + * + * @return + * - IAPI_SUCCESS if all operations were successful + * - negated I.API error code if any operation failed + */ +#ifdef MCU +int +iapi_Init(channelDescriptor *cd_p, configs_data *config_p, + unsigned short *ram_image, unsigned short code_size, + unsigned long start_addr) +{ +#endif +#ifdef DSP + int + iapi_Init(channelDescriptor *cd_p) { +#endif + + int retvalue = IAPI_SUCCESS; /* Variable to store the results from I.API calls */ + + /* Check initialization not allredy done */ + if (iapi_CCBHead != NULL) { + retvalue = IAPI_ERR_NOT_ALLOWED; + iapi_errno = retvalue; + return -retvalue; + } + /* Be sure SDMA has not started yet */ +#ifdef MCU + SDMA_H_C0PTR = 0x0; +#endif +#ifdef DSP + SDMA_D_C0PTR = 0x0; +#endif + + /*Try to open channel 0 */ + retvalue = iapi_Open(cd_p, 0); + if (retvalue != IAPI_SUCCESS) { + return retvalue; + } +#ifdef MCU + /* Set Command Channel (Channel Zero) */ + SDMA_CHN0ADDR = 0x4050; + + /* Set bits of CONFIG register but with static context switching */ + SDMA_H_CONFIG = + (config_p-> + dspdma << 12) | (config_p->rtdobs << 11) | (config_p->acr + << 4) | (0); + + /* Send the address for the host channel table to the SDMA */ + SDMA_H_C0PTR = (unsigned long)iapi_Virt2Phys(iapi_CCBHead); + /* If required, download the RAM image for SDMA */ + if (ram_image != NULL) { + retvalue = + iapi_SetScript(cd_p, (void *)ram_image, code_size, + start_addr); + } + + /* Set bits of CONFIG register with given context switching mode */ + SDMA_H_CONFIG = + (config_p-> + dspdma << 12) | (config_p->rtdobs << 11) | (config_p->acr + << 4) | + (config_p->csm); + +#endif +#ifdef DSP + /* Send the address for the host channel table to the SDMA */ + SDMA_D_C0PTR = (unsigned long)iapi_Virt2Phys(iapi_CCBHead); +#endif + +#ifdef SDMA_SKYE + iapi_SdmaState = OPEN; +#endif + + return retvalue; + } + +/* ***************************************************************************/ +/**High layer interface for starting a channel + * + * Algorithm:\n + * - call low layer function for starting a channel + * + * @return + * - IAPI_SUCCESS + */ +int iapi_StartChannel(unsigned char channel) +{ + iapi_lowStartChannel(channel); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for stopping a channel + * + * Algorithm:\n + * - call low layer function for stopping a channel + * + * @return + * - IAPI_SUCCESS + */ +int iapi_StopChannel(unsigned char channel) +{ + iapi_lowStopChannel(channel); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for synchronising a channel + * + * Algorithm:\n + * - call low layer function for stopping a channel + * + * @return + * - IAPI_SUCCESS + */ +int iapi_SynchChannel(unsigned char channel) +{ + iapi_lowSynchChannel(channel); + return IAPI_SUCCESS; +} + +#ifdef MCU +/* ***************************************************************************/ +/**High layer interface for getting program memory data from SDMA + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int iapi_GetScript(channelDescriptor *cd_p, void *buf, + unsigned short size, unsigned long address) +{ + iapi_lowGetScript(cd_p, buf, size, address); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for getting data memory from SDMA + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int iapi_GetContext(channelDescriptor *cd_p, void *buf, + unsigned char channel) +{ + iapi_lowGetContext(cd_p, buf, channel); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for set program memory data to SDMA - e.g. scripts + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int iapi_SetScript(channelDescriptor *cd_p, void *buf, + unsigned short nbyte, unsigned long destAddr) +{ + iapi_lowSetScript(cd_p, buf, nbyte, destAddr); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface for set data memory to SDMA - e.g. contexts. + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int iapi_SetContext(channelDescriptor *cd_p, void *buf, + unsigned char channel) +{ + iapi_lowSetContext(cd_p, buf, channel); + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**High layer interface used to associate specified channel with a script. + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int iapi_AssignScript(channelDescriptor *cd_p, script_data *data_p) +{ + /* VERIFY THAT THE CHANNEL IT IS OPENED !!!! */ + return iapi_lowAssignScript(cd_p, data_p); +} + +/* ***************************************************************************/ +/**High layer interface used to associate specified channel with a script. + * + * Algorithm:\n + * - call coresponding low layer function + * + * @return + * - IAPI_SUCCESS + */ +int iapi_SetChannelEventMapping(unsigned char event, + unsigned long channel_map) +{ + return iapi_lowSetChannelEventMapping(event, channel_map); +} +#endif + +#ifdef DSP +#define SDMA_DI SDMA_D_INTR + void IRQ_Handler(); +#pragma interrupt IRQ_Handler +#endif + +#ifdef MCU +#define SDMA_DI SDMA_H_INTR +#endif + +#ifndef IRQ_KEYWORD +#define IRQ_KEYWORD +#endif /* IRQ_KEYWORD */ + +/* ***************************************************************************/ +/** + *@brief Find the first set bit in data parameter. + * + * Find the first set bit in unsigned integer parameter data. Data is scanned + * from MSB to LSB, searching for the set bit. The value returned is the + * offset from the most significant bit of data. If bit 31 is set, the value + * returned is zero. If no bits are set, a value of 32 is returned. This is compliant + * with the MCore FF1 instruction. + * + * + * + * @param + * - data: variable to check + * + * @return + * - the offset of the most significant bit set from the MSB + */ +unsigned int quartz_FF1(unsigned int data) +{ + register unsigned int result = 0; + while ((result <= 31) && !(data & 0x80000000U)) { + data <<= 1U; + result++; + } + + return result; +} + +IRQ_KEYWORD void IRQ_Handler(void) +{ + unsigned int intrReg; /* interrupt register mask for clearing the interrupt bit */ + unsigned char chNum; /* SDMA channel number generating the a IRQ */ + + /* Disable interrupts */ + iapi_DisableInterrupts(); + /* + * Clear interrupt in SDMA DI register => ACK to the SDMA the IT request. + * Get each interrupt number, clear them one after the other. + */ + if (SDMA_DI != 0) { + chNum = + (unsigned char)(CH_NUM - 1 - quartz_FF1(SDMA_DI)); + intrReg = (unsigned int)(1 << chNum); + } else { + chNum = 32; + intrReg = 0; + } + + while (intrReg != 0) { + SDMA_DI &= intrReg; + iapi_SDMAIntr |= intrReg; + iapi_WakeUp(chNum); + if (callbackIsrTable[chNum] != NULL) { + /* release channel before callback, so IoCtl's are available */ + iapi_ReleaseChannel(chNum); + callbackIsrTable[chNum] (iapi_CCBHead + [chNum].channelDescriptor, + userArgTable[chNum]); + } + + chNum = + (unsigned char)(CH_NUM - 1 - quartz_FF1(SDMA_DI)); + intrReg = (unsigned int)(1 << chNum); + } + + /* Enable interrupts */ + iapi_EnableInterrupts(); +} + +/* ***************************************************************************/ +/** + *@brief Perform a memory copy operation, in the memory of the same processor + * + * Size bytes are copied from the src address to dest address. It is used + * the channel pointed by cd_p, which must be configured prior to this call: + * opened, associated with the script to perform the operation - DSP_2_DSP, + * or MCU_2_MCU - and have the synchronization option set. + * + * + * + * @param + * - cd_p: channel configured to perform DSP_2_DSP or MCU_2_MCU transfers + * - dest: destination memory address + * - src : source memory address + * - size: number of bytes to copy from src to dest + * + * @return + * - the offset of the most significant bit set from the MSB + */ + +int iapi_MemCopy(channelDescriptor *cd_p, void *dest, void *src, + unsigned long size) +{ + int result = IAPI_SUCCESS; + bufferDescriptor *bd_p; + + /* Channel descriptor validity */ + if (cd_p == NULL) { + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Check and set correct parameter */ + if (cd_p->trust != TRUE) { + result = iapi_ChangeChannelDesc(cd_p, IAPI_TRUST, TRUE); + } + + if (cd_p->bufferDescNumber != 1) { + result = + iapi_ChangeChannelDesc(cd_p, IAPI_BUFFERDESCNUMBER, + 1); + if (result != IAPI_SUCCESS) { + return result; + } + } + + if (cd_p->bufferSize != size) { + result = + iapi_ChangeChannelDesc(cd_p, IAPI_BUFFERSIZE, size); + if (result != IAPI_SUCCESS) { + return result; + } + } + /* Set addresses */ + bd_p = (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + bd_p->bufferAddr = iapi_Virt2Phys(src); + bd_p->extBufferAddr = iapi_Virt2Phys(dest); + + /* Set mode */ + bd_p->mode.count = size; + bd_p->mode.command = 0x00; + bd_p->mode.status = BD_INTR | BD_EXTD | BD_DONE | BD_WRAP; + + /*Decide if we sleep or not */ + if (cd_p->callbackSynch == DEFAULT_POLL) { + iapi_StartChannel(cd_p->channelNumber); + /* Call synchronization routine */ + iapi_SynchChannel(cd_p->channelNumber); + } else { + /* Just start the channel */ + iapi_StartChannel(cd_p->channelNumber); + } + + return result; +} + +/* ***************************************************************************/ +/**Return the channel number from the channel descriptor + * + * @param cd_p pointer to channel descriptor to obtain the channel number + * + * @return + * - the channel number + * + */ +int iapi_GetChannelNumber(channelDescriptor *cd_p) +{ + return cd_p->channelNumber; +} + +/* ***************************************************************************/ +/**Return the error bit from the current BD of the channel + * + * + * @param cd_p pointer to channel descriptor + * + * @return + * - 0 if no error detected + * - BD_RROR | DATA_ERROR if error detected + * + */ +unsigned long iapi_GetError(channelDescriptor *cd_p) +{ + return (cd_p->ccb_ptr->currentBDptr->mode.status & BD_RROR) | + (*(unsigned long *)&cd_p->ccb_ptr->status & DATA_ERROR); +} + +/* ***************************************************************************/ +/**Return the count from the current BD of the channel + * + * + * @param cd_p pointer to channel descriptor + * + * @return + * - count field of the current BD for the channel + * + */ +int iapi_GetCount(channelDescriptor *cd_p) +{ + return (int)(cd_p->ccb_ptr->currentBDptr->mode.count); +} + +/* ***************************************************************************/ +/**Return the sum of counts for all the BD's owned by the processor for + * the channel specified by the received parameter. + * + * + * @param cd_p pointer to channel descriptor + * + * @return + * - sum of count fields + * + */ +int iapi_GetCountAll(channelDescriptor *cd_p) +{ + int retval = 0; + int i = 0; + bufferDescriptor *bd_p; + + bd_p = cd_p->ccb_ptr->baseBDptr; + + while ((i < cd_p->bufferDescNumber) + && ((bd_p->mode.status & BD_DONE) == 0)) { + retval += bd_p->mode.count; + i++; + bd_p++; + } + return retval; +} diff --git a/arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c b/arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c new file mode 100644 index 000000000000..47611fe52743 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/src/iapiLow.c @@ -0,0 +1,151 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLow.c + * + * $Id iapiLow.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the LOW level functions of the I.API. + * + * + * / + * + * $Log iapiLow.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include +#include +#include "epm.h" +#include "iapiLow.h" + +/** + * Function Section + */ + +/* ***************************************************************************/ +/**Records an ISR callback function pointer into the ISR callback + * function table + * + * @param cd_p channel descriptor to attach callback to + * @param func_p pointer to the callback function to be registered + * + * @return none + */ +void +iapi_AttachCallbackISR(channelDescriptor *cd_p, + void (*func_p) (channelDescriptor *cd_p, void *arg)) +{ + if (cd_p->callbackSynch == CALLBACK_ISR) { + iapi_DisableInterrupts(); + callbackIsrTable[cd_p->channelNumber] = func_p; + iapi_EnableInterrupts(); + } else if (cd_p->callbackSynch == DEFAULT_POLL) { + callbackIsrTable[cd_p->channelNumber] = NULL; + } else { + iapi_errno = + IAPI_ERR_CALLBACKSYNCH_UNKNOWN | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + } +} + +/* ***************************************************************************/ +/**Detaches (removes) an ISR callback function pointer from the ISR callback + * function table + * + * Algorithm:\n + * - Attach a null function to replace the original one. + * + * @param cd_p channel descriptor to detach callback from + * + * @return none + */ +void iapi_DetachCallbackISR(channelDescriptor *cd_p) +{ + iapi_AttachCallbackISR(cd_p, NULL); +} + +/* ***************************************************************************/ +/**Updates an ISR callback function pointer into the ISR callback function + * table + * + * Algorithm:\n + * - Detach the old function pointer (if any) and attach the new one + * + * @param cd_p channel descriptor to attach callback to + * @param func_p pointer to the callback function to be registered + * + * @return none + */ +void +iapi_ChangeCallbackISR(channelDescriptor *cd_p, + void (*func_p) (channelDescriptor *cd_p, void *arg)) +{ + iapi_DetachCallbackISR(cd_p); + iapi_AttachCallbackISR(cd_p, func_p); +} + +/* ***************************************************************************/ +/**Loop while the channel is not done on the SDMA + * + * Algorithm:\n + * - Loop doing nothing but checking the I.API global variable to indicate + * that the channel has been completed (interrupt from SDMA) + * + * Notes:\n + * - The ISR must update the I.API global variable iapi_SDMAIntr. + * + * @param channel channel number to poll on + * + * @return none + */ +void iapi_lowSynchChannel(unsigned char channel) +{ + if (preempt_count() || in_interrupt()) { + while (!((1UL << channel) & iapi_SDMAIntr)) + ; + } else + GOTO_SLEEP(channel); + + iapi_SDMAIntr &= ~(1UL << channel); +} + +/* ***************************************************************************/ +/**Fill the buffer descriptor with the values given in parameter. + * + * @return none + */ +void +iapi_SetBufferDescriptor(bufferDescriptor *bd_p, unsigned char command, + unsigned char status, unsigned short count, + void *buffAddr, void *extBufferAddr) +{ + bd_p->mode.command = command; + bd_p->mode.status = status; + bd_p->mode.count = count; + if (buffAddr != NULL) { + bd_p->bufferAddr = iapi_Virt2Phys(buffAddr); + } else { + bd_p->bufferAddr = buffAddr; + } + bd_p->extBufferAddr = extBufferAddr; +} diff --git a/arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c b/arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c new file mode 100644 index 000000000000..345d36433cf3 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/src/iapiLowMcu.c @@ -0,0 +1,503 @@ +/****************************************************************************** + * + * Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiLowMcu.c + * + * $Id iapiLowMcu.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the LOW level functions of the I.API specific to MCU. + * + * + * http://compass/mot.com/go/115342679 + * + * $Log iapiLowMcu.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include +#include + +#include "epm.h" +#include "iapiLow.h" + +/* **************************************************************************** + * Function Section + *****************************************************************************/ +#ifdef MCU + +/* ***************************************************************************/ +/**Send a command on SDMA's channel zero. + * Check if buffer descriptor is already used by the sdma, if yes return + * an error as c0BDNum is wrong. + * + * Notes\n + * There is an upgrade in the script on the Context load command and + * the fact that the context structure has a fixed length of 20 or 24 + * depending on SDMA versions. + * + * @return + * - IAPI_SUCCESS + * - -iapi_errno if failure + */ +int +iapi_Channel0Command(channelDescriptor *cd_p, void *buf, + unsigned short nbyte, unsigned char command) +{ + channelControlBlock *ccb_p; + bufferDescriptor *bd_p; + int result = IAPI_SUCCESS; + unsigned char chNum; + + /* + * Check data structures are properly initialized + */ + /* Channel descriptor validity */ + if (cd_p == NULL) { + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Channel control block validity */ + if (cd_p->ccb_ptr == NULL) { + result = IAPI_ERR_CCB_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* Control block & Descriptpor associated with the channel being worked on */ + chNum = cd_p->channelNumber; + ccb_p = cd_p->ccb_ptr; + + /* Is channel already in use ? */ + if (ccb_p->baseBDptr != NULL) { + result = IAPI_ERR_BD_ALLOCATED | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + return -result; + } + + /* Allocation of buffer descriptors */ + bd_p = (bufferDescriptor *) MALLOC(sizeof(bufferDescriptor), SDMA_ERAM); + if (bd_p != NULL) { + ccb_p->baseBDptr = (bufferDescriptor *) iapi_Virt2Phys(bd_p); + } else { + result = IAPI_ERR_BD_ALLOCATION | IAPI_ERR_CH_AVAILABLE | chNum; + iapi_errno = result; + return -result; + } + + /* Buffer descriptor setting */ + iapi_SetBufferDescriptor(bd_p, command, BD_WRAP | BD_DONE | BD_INTR, + nbyte, buf, NULL); + + /* Actually the transfer */ + iapi_lowStartChannel(cd_p->channelNumber); + iapi_lowSynchChannel(cd_p->channelNumber); + + /* Cleaning of allocation */ + FREE(bd_p); + ccb_p->baseBDptr = NULL; + + return IAPI_SUCCESS; + +} + +/* ***************************************************************************/ +/**Starts the channel (core specific register) + * + * Algorithm:\n + * - Bit numbered "channel" of HostEnStartReg register is set + * + * @param channel channel to start + * + * @return none + */ +void iapi_lowStartChannel(unsigned char channel) +{ + /* HSTART is a 'write-ones' register */ + writel(1UL << channel, SDMA_H_START_ADDR); +} + +/* ***************************************************************************/ +/**Stops the channel (core specific register) + * + * Algorithm: + * - Bit numbered "channel" of HostEnStopReg register is cleared + * + * Notes:\n + * - This is a write one to clear register + * + * @param channel channel to stop + * + * @return none + */ +void iapi_lowStopChannel(unsigned char channel) +{ + /* Another 'write-ones' register */ + writel(1UL << channel, SDMA_H_STATSTOP_ADDR); +} + +/* ***************************************************************************/ +/**Initialize the initial priority of registers and channel enable + * RAM from the MCU side. No channels are enabled, all priorities are set to 0. + * + * @return none + */ +void iapi_InitChannelTables(void) +{ + + /* No channel is enabled */ + iapi_memset((void *)&SDMA_CHNENBL_0, 0x00, + sizeof(unsigned long) * EVENTS_NUM); + /* All channels have priority 0 */ + iapi_memset((void *)&SDMA_CHNPRI_0, 0x00, + sizeof(unsigned long) * CH_NUM); +} + +/* ***************************************************************************/ +/** The host enable (HE), hosts override (HO), dsp enable (DE), dsp override + * (DO) registers are involved here. + * Host and Dsp enable registers are here to signify that the MCU or DSP side + * have prepared the appropriate buffers and are now ready. If the channel is + * owned by the MCU the override bit for that channel needs to be cleared : + * the host allows the channel to be used.\n + * + * Then the override bits can define (mcuOverride dspOverride):\n + * - 0 0 channel is public: transfer to/from MCU to DSP + * - 0 1 channel if owned by DSP + * - 1 0 channel if owned by MCU + * - 1 1 channel zero config + * + * See also :\n + * IAPI Table 1.1 "Channel configuration properties" + * + * @param channel channel to configure + * @param eventOverride event ownership + * @param mcuOverride ARM ownership + * @param dspOverride DSP ownership + * + * @return + * - -iapi_errno if the 3 override parameters are all set + * - IAPI_SUCCESS in other cases (valid cases) + */ +int +iapi_ChannelConfig(unsigned char channel, unsigned eventOverride, + unsigned mcuOverride, unsigned dspOverride) +{ + int result = IAPI_SUCCESS; + + if ((eventOverride == 1) && (mcuOverride == 1) && (dspOverride == 1)) { + result = IAPI_ERR_CONFIG_OVERRIDE; + iapi_errno = result; + return -result; + } else { + /* + * DSP side + */ + if (dspOverride) { + SDMA_H_DSPOVR &= ~(1 << channel); + } else { + SDMA_H_DSPOVR |= (1 << channel); + } + /* + * Event + */ + if (eventOverride) { + SDMA_H_EVTOVR &= ~(1 << channel); + } else { + SDMA_H_EVTOVR |= (1 << channel); + } + /* + * MCU side + */ + if (mcuOverride) { + SDMA_H_HOSTOVR &= ~(1 << channel); + } else { + SDMA_H_HOSTOVR |= (1 << channel); + } + } + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**Load the context data of a channel from SDMA + * + * Algorithm:\n + * - Setup BD with appropiate parameters + * - Start channel + * - Poll for answer + * + * @param *cd_p channel descriptor for channel 0 + * @param *buf pointer to receive context data + * @param channel channel for which the context data is requested + * + * @return none + */ +void +iapi_lowGetContext(channelDescriptor *cd_p, void *buf, unsigned char channel) +{ + bufferDescriptor *bd_p; + + bd_p = (bufferDescriptor *) iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + /*Setup buffer descriptor with channel 0 command */ + iapi_SetBufferDescriptor(&bd_p[0], + C0_GETDM, + (unsigned char)(BD_DONE | BD_INTR | BD_WRAP | + BD_EXTD), + (unsigned short)sizeof(contextData) / 4, buf, + (void *)(CHANNEL_CONTEXT_BASE_ADDRESS + + (sizeof(contextData) * channel / 4))); + /* Receive, polling method */ + iapi_lowStartChannel(cd_p->channelNumber); + iapi_lowSynchChannel(cd_p->channelNumber); +} + +/* ***************************************************************************/ +/**Read "size" byte /2 at SDMA address (address) and write them in buf + * + * Algorithm:\n + * - Setup BD with appropiate parameters (C0_GETPM) + * - Start channel + * - Poll for answer + * + * Notes\n + * - Parameter "size" is in bytes, it represents the size of "buf", e.g. + * the size in bytes of the script to be loaded. + * - Parameter "address" denotes the RAM address for the script in SDMA + * + * @param *cd_p channel descriptor for channel 0 + * @param *buf pointer to receive the data + * @param size number of bytes to read + * @param address address in SDMA RAM to start reading from + * + * @return none + */ +void +iapi_lowGetScript(channelDescriptor *cd_p, void *buf, unsigned short size, + unsigned long address) +{ + bufferDescriptor *bd_p; + + bd_p = (bufferDescriptor *) iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + /*Setup buffer descriptor with channel 0 command */ + iapi_SetBufferDescriptor(&bd_p[0], C0_GETPM, (unsigned char)(BD_DONE | BD_INTR | BD_WRAP | BD_EXTD), (unsigned short)size / 2, /*count in shorts */ + buf, (void *)address); + /* Receive, polling method */ + iapi_lowStartChannel(cd_p->channelNumber); + iapi_lowSynchChannel(cd_p->channelNumber); +} + +/* ***************************************************************************/ +/**Load a SDMA script to SDMA + * + * Algorithm:\n + * - Setup BD with appropiate parameters (C0_SETPM) + * - Start channel + * - Poll for answer + * + * Notes\b + * - Parameter "size" is in bytes, it represents the size of "buf", e.g. + * the size in bytes of the script to be uploaded. + * - Parameter "address" denotes the RAM address for the script in SDMA + * + * @param *cd_p channel descriptor for channel 0 + * @param *buf pointer to the script + * @param size size of the script, in bytes + * @param address address in SDMA RAM to place the script + * + * @return none + */ +void +iapi_lowSetScript(channelDescriptor *cd_p, void *buf, unsigned short size, + unsigned long address) +{ + bufferDescriptor *bd_p; + + bd_p = (bufferDescriptor *) iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + /*Setup buffer descriptor with channel 0 command */ + iapi_SetBufferDescriptor(&bd_p[0], C0_SETPM, (unsigned char)(BD_DONE | BD_INTR | BD_WRAP | BD_EXTD), (unsigned short)size / 2, /*count in shorts */ + buf, (void *)(address)); + /* Receive, polling method */ + iapi_lowStartChannel(cd_p->channelNumber); + iapi_lowSynchChannel(cd_p->channelNumber); +} + +/* ***************************************************************************/ +/**Load the context for a channel to SDMA + * + * Algorithm:\n + * - Send context and poll for answer. + * + * @param *cd_p channel descriptor for channel 0 + * @param *buf pointer to context data + * @param channel channel to place the context for + * + * @return none + */ +void +iapi_lowSetContext(channelDescriptor *cd_p, void *buf, unsigned char channel) +{ + + bufferDescriptor *local_bd_p; +#ifdef SDMA_SKYE + + unsigned char command = 0; + + local_bd_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + command = channel << 3; + command = command | C0_SETCTX; + iapi_SetBufferDescriptor(&local_bd_p[0], + command, + (unsigned char)(BD_DONE | BD_INTR | BD_WRAP), + (unsigned short)(sizeof(contextData) / 4), + buf, NULL); +#else + + local_bd_p = + (bufferDescriptor *) iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + + iapi_SetBufferDescriptor(&local_bd_p[0], + C0_SETDM, + (unsigned char)(BD_DONE | BD_INTR | BD_WRAP | + BD_EXTD), + (unsigned short)(sizeof(contextData) / 4), buf, + (void *)(2048 + + (sizeof(contextData) / 4) * channel)); +#endif + /* Send */ + iapi_lowStartChannel(cd_p->channelNumber); + iapi_lowSynchChannel(cd_p->channelNumber); + +} + +/* ***************************************************************************/ +/**Associate specified channel with the script starting at the + * specified address. Channel 0 command is used to load the set-up context + * for the channel. The address used must be generated by the GUI tool + * used to create RAM images for SDMA. + * + * Algorithm:\n + * - Set-up and load the context. + * + * @param *cd_p pointer to the channel descriptor of the channel + * @param *data_p: pointer to the data identifying the script to be associated + * with the channel + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : operation failed, return negated value of iapi_errno + */ + +int iapi_lowAssignScript(channelDescriptor *cd_p, script_data * data_p) +{ + contextData *chContext; /* context to be loaded for the channel */ + channelDescriptor *cd0_p; /* pointer to channel descriptor of channel 0 */ + int result = IAPI_SUCCESS; + + /*Verify passed data */ + if (cd_p == NULL || data_p == NULL) { + result = IAPI_ERR_INVALID_PARAMETER; + iapi_errno = result; + return -result; + } + + /* Allocate context and initialize PC to required script start adress */ + chContext = (contextData *) MALLOC(sizeof(contextData), SDMA_ERAM); + if (chContext == NULL) { + result = IAPI_ERR_B_ALLOC_FAILED | cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + iapi_memset(chContext, 0x00, sizeof(contextData)); + chContext->channelState.pc = data_p->load_address; + + /* Send by context the event mask,base address for peripheral + * and watermark level + */ + chContext->gReg[0] = data_p->event_mask2; + chContext->gReg[1] = data_p->event_mask1; + chContext->gReg[6] = data_p->shp_addr; + chContext->gReg[7] = data_p->wml; + if (data_p->per_addr) + chContext->gReg[2] = data_p->per_addr; + + /* Set transmited data to the CD */ + cd_p->watermarkLevel = data_p->wml; + cd_p->eventMask1 = data_p->event_mask1; + cd_p->eventMask2 = data_p->event_mask2; + + /* Get the cd0_p */ + cd0_p = (cd_p->ccb_ptr - cd_p->channelNumber)->channelDescriptor; + + /*load the context */ + iapi_lowSetContext(cd0_p, chContext, cd_p->channelNumber); + + /* release allocated memory */ + FREE(chContext); + + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/** Set the channels to be triggered by an event. The for every channel that + *must be triggered by the event, the corresponding bit from channel_map + *parameter must be set to 1. (e.g. for the event to trigger channels 31 and + *0 one must pass 0x80000001) + * + * + * Algorithm:\n + * - Update the register from Channel Enable RAM with the channel_map + * + * @param event event for which to set the channel association + * @param channel_map channels to be triggered by event. Put the corresponding + * bit from this 32-bit value to 1 for every channel that should be + * triggered by the event. + * + * @return + * - IAPI_SUCCESS : OK + * - -iapi_errno : operation failed, return negated value of iapi_errno + */ +int +iapi_lowSetChannelEventMapping(unsigned char event, unsigned long channel_map) +{ + volatile unsigned long *channelEnableMatx; + int result = IAPI_SUCCESS; + + /* Check validity of event */ + if (event < EVENTS_NUM) { + channelEnableMatx = &SDMA_CHNENBL_0; + channelEnableMatx[event] |= channel_map; + return result; + } else { + result = IAPI_ERR_INVALID_PARAMETER | event; + iapi_errno = result; + return -result; + } +} + +#endif /* MCU */ diff --git a/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c b/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c new file mode 100644 index 000000000000..185489295523 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddle.c @@ -0,0 +1,644 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiMiddle.c + * + * $Id iapiMiddle.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the MIDDLE level functions of the I.API. + * + * + * + * + * $Log iapiMiddle.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include + +#include "iapiLow.h" +#include "iapiMiddle.h" + +/* **************************************************************************** + * Global Variable Section + *****************************************************************************/ + +/* **************************************************************************** + * Function Section + *****************************************************************************/ + +/* ***************************************************************************/ +/**Allocates one Buffer Descriptor structure using information present in the + * channel descriptor. + * + * @param *ccb_p channel control block used to get the channel descriptor + * + * @return + * - pointer on the new Buffer Descriptor + * - NULL if allocation failed + * + */ +bufferDescriptor *iapi_AllocBD(channelControlBlock * ccb_p) +{ + bufferDescriptor *ptrBD = NULL; + + if (ccb_p->channelDescriptor->bufferDescNumber != 0) { +#ifdef CONFIG_SDMA_IRAM + channelDescriptor *cd_p = ccb_p->channelDescriptor; + if (cd_p->channelNumber >= MXC_DMA_CHANNEL_IRAM) { + ptrBD = (bufferDescriptor *) + MALLOC(ccb_p->channelDescriptor->bufferDescNumber * + sizeof(bufferDescriptor), SDMA_IRAM); + } else +#endif /*CONFIG_SDMA_IRAM */ + { + ptrBD = (bufferDescriptor *) + MALLOC(ccb_p->channelDescriptor->bufferDescNumber * + sizeof(bufferDescriptor), SDMA_ERAM); + } + } + if (ptrBD != NULL) { + ptrBD->mode.command = 0; + ptrBD->mode.status = 0; + ptrBD->mode.count = 0; + ptrBD->bufferAddr = NULL; + } + + return ptrBD; +} + +/* ***************************************************************************/ +/**Allocate one channel context data structure. + * + * @param **ctxd_p pointer to context data to be allocated + * @param channel channel number of context data structure + * + * @return + * - IAPI_SUCCESS + * - -iapi_errno if allocation failed + */ +int iapi_AllocContext(contextData **ctxd_p, unsigned char channel) +{ + contextData *ctxData; + int result = IAPI_SUCCESS; + + if (*ctxd_p != NULL) { + result = + IAPI_ERR_CC_ALREADY_DEFINED | IAPI_ERR_CH_AVAILABLE | + channel; + iapi_errno = result; + return -result; + } + + ctxData = (contextData *) MALLOC(sizeof(contextData), SDMA_ERAM); + + if (ctxData != NULL) { + *ctxd_p = ctxData; + return IAPI_SUCCESS; + + } else { + *ctxd_p = NULL; + result = + IAPI_ERR_CC_ALLOC_FAILED | IAPI_ERR_CH_AVAILABLE | channel; + iapi_errno = result; + return -result; + } +} + +/* ***************************************************************************/ +/**Allocates channel description and fill in with default values. + * + * Algorithm:\n + * - Check channel properties. + * - Then modifies the properties of the channel description with default + * + * @param **cd_p pointer to channel descriptor to be allocated + * @param channel channel number of channel descriptor + * + * @return + * - IAPI_SUCCESS + * - -iapi_errno if allocation failed + * + */ +int iapi_AllocChannelDesc(channelDescriptor **cd_p, unsigned char channel) +{ +#ifdef MCU + volatile unsigned long *chPriorities = &SDMA_CHNPRI_0; +#endif /* MCU */ + channelDescriptor *tmpCDptr; + int result = IAPI_SUCCESS; + + if (*cd_p != NULL) { + result = + IAPI_ERR_CD_ALREADY_DEFINED | IAPI_ERR_CH_AVAILABLE | + channel; + iapi_errno = result; + return -result; + } + + tmpCDptr = + (channelDescriptor *) MALLOC(sizeof(channelDescriptor), SDMA_ERAM); + + if (tmpCDptr != NULL) { + iapi_memcpy(tmpCDptr, &iapi_ChannelDefaults, + sizeof(channelDescriptor)); + tmpCDptr->channelNumber = channel; +#ifdef MCU + if (chPriorities[channel] != 0) { + tmpCDptr->priority = chPriorities[channel]; + } else { + chPriorities[channel] = tmpCDptr->priority; + } +#endif + *cd_p = tmpCDptr; + return IAPI_SUCCESS; + } else { + *cd_p = NULL; + result = + IAPI_ERR_CD_ALLOC_FAILED | IAPI_ERR_CH_AVAILABLE | channel; + iapi_errno = result; + return -result; + } +} + +/* ***************************************************************************/ +/**Changes channel description information after performing sanity checks. + * + * Algorithm:\n + * - Check channel properties. + * - Then modifies the properties of the channel description. + * + * @param *cd_p channel descriptor of the channel to change + * @param whatToChange control code indicating the desired change + * @param newval new value + * + * @return + * - IAPI_SUCCESS + * - IAPI_FAILURE if change failed + * + */ +int +iapi_ChangeChannelDesc(channelDescriptor *cd_p, unsigned char whatToChange, + unsigned long newval) +{ + bufferDescriptor *tmpBDptr; + unsigned char index = 0; + int result = IAPI_SUCCESS; + + /* verify parameter validity */ + if (cd_p == NULL) { + result = IAPI_ERR_CD_UNINITIALIZED; + iapi_errno = result; + return -result; + } + + /* verify channel descriptor initialization */ + if (cd_p->ccb_ptr == NULL) { + result = IAPI_ERR_CCB_UNINITIALIZED | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* verify channel is not in use */ + tmpBDptr = + (bufferDescriptor *) iapi_Phys2Virt(cd_p->ccb_ptr->baseBDptr); + for (index = cd_p->bufferDescNumber; index > 0; index--) { + if (tmpBDptr->mode.status & BD_DONE) { + result = IAPI_ERR_CH_IN_USE | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + tmpBDptr++; + } + + /* Select the change accorded to the selector given in parameter */ + switch (whatToChange) { + + /* + * Channel Number + */ + case IAPI_CHANNELNUMBER: + /* Channel number can not be changed (description remains attached) */ + result = IAPI_ERR_CD_CHANGE_CH_NUMBER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + + /* + * Buffer Descriptor Number + */ + case IAPI_BUFFERDESCNUMBER: + if (newval < MAX_BD_NUM) { + if (newval != cd_p->bufferDescNumber) { + /* Free memory used for previous old data */ + if (cd_p->ccb_ptr->baseBDptr != NULL) { + tmpBDptr = (bufferDescriptor *) + iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + for (index = 0; + index < cd_p->bufferDescNumber; + index++) { + if (tmpBDptr->bufferAddr != + NULL) { + if (cd_p->trust == + FALSE) { + FREE(iapi_Phys2Virt(tmpBDptr->bufferAddr)); + } + } + tmpBDptr++; + } + FREE((bufferDescriptor *) + iapi_Phys2Virt((cd_p-> + ccb_ptr)->baseBDptr)); + } + (cd_p->ccb_ptr)->baseBDptr = NULL; + (cd_p->ccb_ptr)->currentBDptr = NULL; + /* Allocate and initialize structures */ + cd_p->bufferDescNumber = (unsigned char)newval; + cd_p->ccb_ptr->status.openedInit = FALSE; + if (IAPI_SUCCESS != + iapi_InitializeMemory(cd_p->ccb_ptr)) { + result = + IAPI_ERR_BD_ALLOCATION | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + cd_p->ccb_ptr->status.openedInit = TRUE; + } + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Buffer size + */ + case IAPI_BUFFERSIZE: + if (newval < MAX_BD_SIZE) { + if (newval != cd_p->bufferSize) { + /* Free memory used for previous old data */ + if (cd_p->ccb_ptr->baseBDptr != NULL) { + tmpBDptr = (bufferDescriptor *) + iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + for (index = 0; + index < cd_p->bufferDescNumber; + index++) { + if (cd_p->trust == FALSE) { + FREE(iapi_Phys2Virt + (tmpBDptr->bufferAddr)); + } + tmpBDptr++; + } + FREE((bufferDescriptor *) + iapi_Phys2Virt((cd_p-> + ccb_ptr)->baseBDptr)); + } + (cd_p->ccb_ptr)->baseBDptr = NULL; + (cd_p->ccb_ptr)->currentBDptr = NULL; + /* Allocate and initialize structures */ + cd_p->bufferSize = (unsigned short)newval; + cd_p->ccb_ptr->status.openedInit = FALSE; + if (IAPI_SUCCESS != + iapi_InitializeMemory(cd_p->ccb_ptr)) { + result = + IAPI_ERR_BD_ALLOCATION | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + cd_p->ccb_ptr->status.openedInit = TRUE; + } + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Blocking / non blocking feature + */ + case IAPI_BLOCKING: + if (newval < MAX_BLOCKING) { + cd_p->blocking = newval; + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Synchronization method + */ + case IAPI_CALLBACKSYNCH: + if (newval < MAX_SYNCH) { + cd_p->callbackSynch = newval; + iapi_ChangeCallbackISR(cd_p, cd_p->callbackISR_ptr); + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Ownership of the channel + */ + case IAPI_OWNERSHIP: +#ifdef DSP + result = IAPI_ERR_NOT_ALLOWED | cd_p->channelNumber; + iapi_errno = result; + return -result; +#endif /* DSP */ +#ifdef MCU + if (newval < MAX_OWNERSHIP) { + cd_p->ownership = newval; + iapi_ChannelConfig(cd_p->channelNumber, + (newval >> CH_OWNSHP_OFFSET_EVT) & 1, + (newval >> CH_OWNSHP_OFFSET_MCU) & 1, + (newval >> CH_OWNSHP_OFFSET_DSP) & + 1); + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + +#endif /* MCU */ + + /* + * Priority + */ + case IAPI_PRIORITY: +#ifdef DSP + result = IAPI_ERR_NOT_ALLOWED | cd_p->channelNumber; + iapi_errno = result; + return -result; +#endif /* DSP */ + +#ifdef MCU + if (newval < MAX_CH_PRIORITY) { + volatile unsigned long *ChannelPriorities = + &SDMA_CHNPRI_0; + ChannelPriorities[cd_p->channelNumber] = newval; + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } +#endif /* MCU */ + + /* + * "Trust" property + */ + case IAPI_TRUST: + if (newval < MAX_TRUST) { + if (cd_p->trust != newval) { + cd_p->trust = newval; + if (newval == FALSE) { + if (IAPI_SUCCESS != + iapi_InitializeMemory + (cd_p->ccb_ptr)) { + result = + IAPI_ERR_BD_ALLOCATION | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + } + } + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Callback function pointer + */ + case IAPI_CALLBACKISR_PTR: + if ((void *)newval != NULL) { + { + union { + void *voidstar; + void (*funcptr) (channelDescriptor * + cd_p, void *arg); + } value; + value.voidstar = (void *)newval; + cd_p->callbackISR_ptr = value.funcptr; + } + iapi_ChangeCallbackISR(cd_p, cd_p->callbackISR_ptr); + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Channel Control Block pointer + */ + case IAPI_CCB_PTR: + cd_p->ccb_ptr = (channelControlBlock *) newval; + cd_p->ccb_ptr->channelDescriptor = cd_p; + break; + + /* + * WRAP/UNWRAP + */ + case IAPI_BDWRAP: + /* point to first BD */ + tmpBDptr = + (bufferDescriptor *) iapi_Phys2Virt(cd_p-> + ccb_ptr->baseBDptr); + /* to point to last BD */ + tmpBDptr += cd_p->bufferDescNumber - 1; + if (newval == TRUE) { + /* wrap last BD */ + tmpBDptr->mode.status |= BD_WRAP; + break; + } else if (newval == FALSE) { + /* unwrap last BD */ + tmpBDptr->mode.status &= ~BD_WRAP; + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + /* + * Watermark level + */ + case IAPI_WML: +#ifdef DSP + result = IAPI_ERR_NOT_ALLOWED | cd_p->channelNumber; + iapi_errno = result; + return -result; +#endif /* DSP */ +#ifdef MCU + if (newval < MAX_WML) { + if (cd_p->watermarkLevel != newval) { + cd_p->watermarkLevel = newval; + } + break; + } else { + result = + IAPI_ERR_INVALID_PARAMETER | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } +#endif /* MCU */ + + /* + * Detect errors + */ + default: + result = IAPI_ERR_CD_CHANGE_UNKNOWN | IAPI_ERR_CH_AVAILABLE | + cd_p->channelNumber; + iapi_errno = result; + return -result; + } + + return IAPI_SUCCESS; +} + +/* ***************************************************************************/ +/**Initialize a table of function pointers that contain the interrupt Service + * Routine callback pointers for the SDMA channels with a default value + * + * Algorithm:\n + * - Loop on each element of the global IAPI variable callbackIsrTable + * + * @param *func_p default callback functon for all SDMA channels + * + * @return none + */ +void +iapi_InitializeCallbackISR(void (*func_p) (channelDescriptor *cd_p, void *arg)) +{ + unsigned long chCnt; + + for (chCnt = 0; chCnt < CH_NUM; chCnt++) { + callbackIsrTable[chCnt] = func_p; + } +} + +/* ***************************************************************************/ +/**For the specified channel control block, attach the array of buffer + * descriptors, the channel description structure and initialize channel's + * status using information in the channel descriptor. + * + * @param *ccb_p pointer to channel control block + * + * @return none + * + */ +int iapi_InitializeMemory(channelControlBlock *ccb_p) +{ + bufferDescriptor *bd_p; + unsigned char index; + int result = IAPI_SUCCESS; + + /* Attach the array of Buffer descriptors */ + bd_p = iapi_AllocBD(ccb_p); + if (bd_p != NULL) { + ccb_p->baseBDptr = (bufferDescriptor *) iapi_Virt2Phys(bd_p); + ccb_p->currentBDptr = ccb_p->baseBDptr; + for (index = 0; + index < ccb_p->channelDescriptor->bufferDescNumber - 1; + index++) { + if (ccb_p->channelDescriptor->trust == TRUE) { + iapi_SetBufferDescriptor(bd_p, + (unsigned char) + ccb_p->channelDescriptor->dataSize, + BD_CONT | BD_EXTD, + ccb_p->channelDescriptor->bufferSize, + NULL, NULL); + } else { + if (ccb_p->channelDescriptor->bufferSize != 0) { + iapi_SetBufferDescriptor(bd_p, + (unsigned char) + ccb_p->channelDescriptor->dataSize, BD_CONT | BD_EXTD, ccb_p->channelDescriptor->bufferSize, MALLOC(ccb_p->channelDescriptor->bufferSize, SDMA_ERAM), NULL); + } + } + bd_p++; + } + + if (ccb_p->channelDescriptor->trust == TRUE) { + iapi_SetBufferDescriptor(bd_p, + (unsigned char) + ccb_p->channelDescriptor-> + dataSize, + BD_EXTD | BD_WRAP | BD_INTR, + ccb_p-> + channelDescriptor->bufferSize, + NULL, NULL); + } else { + if (ccb_p->channelDescriptor->bufferSize != 0) { + iapi_SetBufferDescriptor(bd_p, + (unsigned char) + ccb_p->channelDescriptor->dataSize, + BD_EXTD | BD_WRAP | + BD_INTR, + ccb_p->channelDescriptor->bufferSize, + MALLOC + (ccb_p->channelDescriptor->bufferSize, + SDMA_ERAM), NULL); + } + } + } else { + result = IAPI_ERR_BD_ALLOCATION; + return -result; + } + return result; +} diff --git a/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c b/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c new file mode 100644 index 000000000000..8e7a614fd76a --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/src/iapiMiddleMcu.c @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiMiddleMcu.c + * + * $Id iapiMiddleMcu.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the MIDDLE level functions of the I.API specific to MCU. + * + * + * + * + * $Log iapiMiddleMcu.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include + +#include "iapiLow.h" +#include "iapiMiddle.h" + +/* **************************************************************************** + * Global Variable Section + *****************************************************************************/ + +/*extern void * __HEAP_START; +extern void * __HEAP_END; +*/ + +/* **************************************************************************** + * Function Section + *****************************************************************************/ diff --git a/arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c b/arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c new file mode 100644 index 000000000000..c188d36eda00 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/iapi/src/iapiOS.c @@ -0,0 +1,64 @@ +/****************************************************************************** + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + ****************************************************************************** + * + * File: iapiOS.c + * + * $Id iapiOS.c $ + * + * Description: + * This library is written in C to guarantee functionality and integrity in + * the usage of SDMA virtual DMA channels. This API (Application Programming + * Interface) allow SDMA channels' access in an OPEN, READ, WRITE, CLOSE + * fashion. + * These are the OS level functions of the I.API - are OS dependant and must + * be provided by the user of I.API. + * + * + * / + * + * $Log iapiOS.c $ + * + *****************************************************************************/ + +/* **************************************************************************** + * Include File Section + *****************************************************************************/ +#include "epm.h" +#include "iapiLow.h" + +/** + * Function Section + */ +#ifdef CONFIG_SDMA_IRAM +void *(*iapi_iram_Malloc) (size_t size); +#endif /*CONFIG_SDMA_IRAM */ + +void *(*iapi_Malloc) (size_t size); +void (*iapi_Free) (void *ptr); + +void *(*iapi_Virt2Phys) (void *ptr); +void *(*iapi_Phys2Virt) (void *ptr); + +void (*iapi_WakeUp) (int); +void (*iapi_GotoSleep) (int); +void (*iapi_InitSleep) (int); + +void *(*iapi_memcpy) (void *dest, const void *src, size_t count); +void *(*iapi_memset) (void *dest, int c, size_t count); + +void (*iapi_EnableInterrupts) (void); +void (*iapi_DisableInterrupts) (void); + +int (*iapi_GetChannel) (int); +int (*iapi_ReleaseChannel) (int); diff --git a/arch/arm/plat-mxc/sdma/sdma.c b/arch/arm/plat-mxc/sdma/sdma.c new file mode 100644 index 000000000000..7b3d7ae92eb8 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/sdma.c @@ -0,0 +1,1548 @@ +/* + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/sdma/sdma.c + * @brief This file contains functions for Smart DMA API + * + * SDMA (Smart DMA) is used for transferring data between MCU and peripherals + * + * @ingroup SDMA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "iapi.h" + +#define M3_BASE_ADDRESS CSD0_BASE_ADDR +#define CHAD(ch) sdma_data[0].cd->ccb_ptr[ch].channelDescriptor + +/*! + * SDMA status mutex + */ +static struct semaphore sdma_status_mutex; + +/*! + * SDMA channel sleep queues + */ +static wait_queue_head_t sdma_sleep_queue[MAX_DMA_CHANNELS]; + +/*! + * SDMA channel synchronization + */ +static struct semaphore sdma_synch_mutex[MAX_DMA_CHANNELS]; + +/*! + * SDMA buffers pool initialization function + */ +extern void init_sdma_pool(void); + +/*! + * Flags are save and restored during interrupt handler + */ +unsigned long flags; +struct clk *mxc_sdma_ahb_clk, *mxc_sdma_ipg_clk; +void __iomem *sdma_base; + +/*! + * Structure containing sdma channels information. + */ +typedef struct { + /*! Channel number */ + int channel; + /*! Channel usage name */ + int in_use; + /*! Name of device using the channel */ + char devicename[MAX_DEVNAME_LENGTH]; + /*! Transfer type. Needed for setting SDMA script */ + sdma_transferT transfer_type; + /*! Peripheral type. Needed for setting SDMA script */ + sdma_periphT peripheral_type; + /*! Watermark level of device's fifo */ + __u32 watermark_level; + /*! Peripheral event id */ + int event_id; + /*! Peripheral event id2 (for channels that use 2 events) */ + int event_id2; + /*! Running status (boolean) */ + int running; + /*! buffer descriptors number */ + int bd_number; + /*! callback function */ + dma_callback_t callback; + /*! callback argument */ + void *arg; + /*! SDMA data access word size */ + unsigned long word_size:8; + /*! channel descriptor pointer */ + channelDescriptor *cd; +} sdma_struct; + +/*! + * Used to save the status of channels. + */ +static sdma_struct sdma_data[MAX_DMA_CHANNELS]; + +/*! + * Stores the start address of the SDMA scripts + */ +static sdma_script_start_addrs sdma_script_addrs; + +extern void mxc_sdma_get_script_info(sdma_script_start_addrs *sdma_script_add); + +/*! + * Init sleep mutex of the channel + * + * @param channel channel number + */ +static void sdma_init_sleep(int channel) +{ + init_waitqueue_head(&sdma_sleep_queue[channel]); +} + +/*! + * Puts channel to sleep + * + * @param channel channel number + */ +static void sdma_sleep_channel(int channel) +{ + while ((iapi_SDMAIntr & (1 << channel)) == 0) { + int timeout = 10; /* timeout 10ms */ + timeout = wait_event_interruptible_timeout( + sdma_sleep_queue[channel], + ((iapi_SDMAIntr & (1 << channel)) != + 0), timeout); + if (!timeout) + printk(KERN_WARNING "sdma channel timeout\n"); + } +} + +/*! + * Wake up channel from sleep + * + * @param channel channel number + */ +static void sdma_wakeup_channel(int channel) +{ + wake_up_interruptible(&sdma_sleep_queue[channel]); +} + +/*! + * Sdma interrupt handler routine. + * Calls channels callback function + * + * @param irq the interrupt number + * @param dev_id driver private data + * @return the function returns \b IRQ_RETVAL(1) - interrupt was handled + */ +static irqreturn_t sdma_int_handler(int irq, void *dev_id) +{ + IRQ_Handler(); + return IRQ_RETVAL(1); +} + +/*! + * I.API channel callback function + * + * @param cd channel descriptor structure + * @param channel_data SDMA struct of the current channel + */ +static void iapi_interrupt_callback(channelDescriptor *cd, + sdma_struct *channel_data) +{ + int channel; + dma_callback_t callback; + void *arg; + + channel = channel_data->channel; + + channel_data->running = 0; + + arg = channel_data->arg; + + if (arg == 0) { + arg = (void *)&channel; + } + + callback = channel_data->callback; + + if (callback != 0) { + callback(arg); + } +} + +/*! + * Returns pc of SDMA script according to peripheral and transfer type + * + * @param peripheral_type peripheral type + * @param transfer_type transfer type + * + * @return PC of SDMA script +*/ +static unsigned short sdma_get_pc(sdma_periphT peripheral_type, + sdma_transferT transfer_type) +{ + int res = 0; + + if (peripheral_type == MEMORY) { + switch (transfer_type) { + case emi_2_int: + res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; + break; + case emi_2_emi: + res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; + break; + case int_2_emi: + res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == DSP) { + switch (transfer_type) { + case emi_2_dsp: + res = sdma_script_addrs.mxc_sdma_ap_2_bp_addr; + break; + case dsp_2_emi: + res = sdma_script_addrs.mxc_sdma_bp_2_ap_addr; + break; + case dsp_2_emi_loop: + res = + sdma_script_addrs. + mxc_sdma_loopback_on_dsp_side_addr; + break; + case emi_2_dsp_loop: + res = + sdma_script_addrs.mxc_sdma_mcu_interrupt_only_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == FIRI) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_firi_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_firi_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_firi_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_firi_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == UART) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_uart_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_uart_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_app_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_app_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == UART_SP) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_uartsh_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_uartsh_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_shp_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_shp_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == ATA) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_ata_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_ata_addr; + break; + default: + res = -EINVAL; + } +#ifdef CONFIG_MXC_SSI_DUAL_FIFO + } else if (peripheral_type == CSPI || peripheral_type == EXT || + (peripheral_type == SSI && + !(cpu_is_mx51() || cpu_is_mx53()))) { +#else + } else if (peripheral_type == CSPI || peripheral_type == EXT || + peripheral_type == SSI) { +#endif + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_app_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_app_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_app_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_app_addr; + break; + default: + res = -EINVAL; + } +#ifdef CONFIG_MXC_SSI_DUAL_FIFO + } else if (peripheral_type == MMC || peripheral_type == SDHC || + peripheral_type == CSPI_SP || peripheral_type == ESAI || + peripheral_type == MSHC_SP || + (peripheral_type == SSI_SP && + !(cpu_is_mx51() || cpu_is_mx53()))) { +#else + } else if (peripheral_type == SSI_SP || peripheral_type == MMC || + peripheral_type == SDHC || peripheral_type == CSPI_SP || + peripheral_type == ESAI || peripheral_type == MSHC_SP) { +#endif + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_shp_2_per_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_shp_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_shp_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_shp_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == ASRC) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_shp_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_shp_addr; + break; + case per_2_per: + res = sdma_script_addrs.mxc_sdma_per_2_per_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == MSHC) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_mshc_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_mshc_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == CCM) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_dptc_dvfs_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == FIFO_MEMORY) { + res = sdma_script_addrs.mxc_sdma_ap_2_ap_fixed_addr; + } else if (peripheral_type == SPDIF) { + switch (transfer_type) { + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_spdif_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_spdif_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == IPU_MEMORY) { + if (transfer_type == emi_2_per) { + res = sdma_script_addrs.mxc_sdma_ext_mem_2_ipu_addr; + } else { + res = -EINVAL; + } +#ifdef CONFIG_MXC_SSI_DUAL_FIFO + } else if (peripheral_type == SSI) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_ssiapp_2_mcu_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_ssiapp_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_ssiapp_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_ssiapp_addr; + break; + default: + res = -EINVAL; + } + } else if (peripheral_type == SSI_SP) { + switch (transfer_type) { + case per_2_int: + res = sdma_script_addrs.mxc_sdma_ssish_2_mcu_addr; + break; + case int_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_ssish_addr; + break; + case per_2_emi: + res = sdma_script_addrs.mxc_sdma_ssish_2_mcu_addr; + break; + case emi_2_per: + res = sdma_script_addrs.mxc_sdma_mcu_2_ssish_addr; + break; + default: + res = -EINVAL; + } +#endif + } + + if (res < 0) { + printk(KERN_ERR "SDMA script not found\n"); + } + + return res; + +} + +static inline int sdma_asrc_set_info(dma_channel_params *p, + script_data *pcontext, int eflags) +{ + dma_channel_ext_params *ep = (dma_channel_ext_params *) p; + unsigned int wml, tmp, wml1, wml2; + struct dma_channel_asrc_info *info = &(ep->info.asrc); + wml = 0; + if (p->transfer_type == per_2_per) { + if (!p->ext) + return wml; + wml1 = p->watermark_level; + wml2 = ep->watermark_level2; + if (info->channs) { + wml |= (info->channs & SDMA_ASRC_INFO_N_MASK) << + SDMA_ASRC_INFO_N_OFF; + if (ep->p2p_dir) + wml2 *= info->channs & SDMA_ASRC_INFO_N_MASK; + else + wml1 *= info->channs & SDMA_ASRC_INFO_N_MASK; + } + if (info->channs & 1) { + if (ep->p2p_dir) + wml |= SDMA_ASRC_P2P_INFO_PS; + else + wml |= SDMA_ASRC_P2P_INFO_PA; + } + if (wml1 > wml2) { + tmp = wml2 & SDMA_ASRC_P2P_INFO_LWML_MASK; + wml |= tmp << SDMA_ASRC_P2P_INFO_LWML_OFF; + tmp = wml1 & SDMA_ASRC_P2P_INFO_HWML_MASK; + wml |= tmp << SDMA_ASRC_P2P_INFO_HWML_OFF; + if (eflags & (1 << 31)) + wml |= SDMA_ASRC_P2P_INFO_LWE; + if (eflags & (1 << 30)) + wml |= SDMA_ASRC_P2P_INFO_HWE; + } else { + tmp = wml1 & SDMA_ASRC_P2P_INFO_LWML_MASK; + wml |= tmp << SDMA_ASRC_P2P_INFO_LWML_OFF; + tmp = wml2 & SDMA_ASRC_P2P_INFO_HWML_MASK; + wml |= tmp << SDMA_ASRC_P2P_INFO_HWML_OFF; + wml |= eflags >> 2; + tmp = pcontext->event_mask2; + pcontext->event_mask2 = pcontext->event_mask1; + pcontext->event_mask1 = tmp; + } + } else { + if (p->ext && info->channs) { + wml |= (info->channs & SDMA_ASRC_INFO_N_MASK) << + SDMA_ASRC_INFO_N_OFF; + tmp = (info->channs * p->watermark_level) & + SDMA_ASRC_INFO_WML_MASK; + wml |= tmp << SDMA_ASRC_INFO_WML_OFF; + } else { + tmp = (p->watermark_level & SDMA_ASRC_INFO_WML_MASK); + wml |= tmp << SDMA_ASRC_INFO_WML_OFF; + } + + if (p->transfer_type == per_2_emi) + wml |= SDMA_ASRC_INFO_TXFR_DIR; + + if (p->ext && (info->channs & 1)) { + if (p->transfer_type == per_2_emi) + wml |= SDMA_ASRC_INFO_PS; + else + wml |= SDMA_ASRC_INFO_PA; + } + wml |= eflags; + } + return wml; +} + +/*! + * Downloads channel context according to channel parameters + * + * @param channel channel number + * @param p channel parameters + */ +static int sdma_load_context(int channel, dma_channel_params *p) +{ + script_data context; + int res; + int event1_greater_than_32; + int event2_greater_than_32; + dma_channel_ext_params *ep = (dma_channel_ext_params *) p; + + res = 0; + + memset(&context, 0, sizeof(script_data)); + context.load_address = sdma_get_pc(p->peripheral_type, + p->transfer_type); + + if (context.load_address > 0) { + if ((p->peripheral_type != MEMORY) + && (p->peripheral_type != DSP)) { + /* Handle multiple event channels differently */ + if (p->event_id2) { + if (p->event_id2 < 32) { + context.event_mask2 = + 0x1 << p->event_id2; + event2_greater_than_32 = 0; + } else { + context.event_mask2 = + 0x1 << (p->event_id2 - 32); + event2_greater_than_32 = 1 << 31; + } + if (p->event_id < 32) { + context.event_mask1 = + 0x1 << p->event_id; + event1_greater_than_32 = 0; + } else { + context.event_mask1 = + 0x1 << (p->event_id - 32); + event1_greater_than_32 = 1 << 30; + } + } else { + event1_greater_than_32 = 0; + event2_greater_than_32 = 0; + if (p->event_id < 32) { + context.event_mask1 = + 0x1 << p->event_id; + context.event_mask2 = 0; + } else { + context.event_mask1 = 0; + context.event_mask2 = + 0x1 << (p->event_id - 32); + } + } + + if (p->ext) + context.wml = ep->info_bits; + /* Watermark Level */ + context.wml |= event2_greater_than_32 | + event1_greater_than_32 | p->watermark_level; + + /* Address */ + context.shp_addr = (unsigned long)(p->per_address); + if (p->ext) + context.per_addr = ep->per_address2; + iapi_IoCtl(sdma_data[channel].cd, + IAPI_CHANGE_PERIPHADDR, p->per_address); + } else { + BUG(); /* Need a real address, not the beginning of RAM + context.wml = M3_BASE_ADDRESS; */ + } + + sdma_data[channel].transfer_type = p->transfer_type; + sdma_data[channel].peripheral_type = p->peripheral_type; + sdma_data[channel].watermark_level = p->watermark_level; + iapi_AssignScript(sdma_data[channel].cd, &context); + } else { + res = context.load_address; + } + + return res; +} + +/*! + * Setup channel according to parameters. Must be called once after mxc_request_dma() + * + * @param channel channel number + * @param p channel parameters pointer + * @return 0 on success, error code on fail + */ +int mxc_dma_setup_channel(int channel, dma_channel_params *p) +{ + int err = 0; + int i; + + mxc_dma_stop(channel); + + for (i = 0; i < sdma_data[channel].bd_number; i++) { + iapi_IoCtl(sdma_data[channel].cd, + (i << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_STATUS, (unsigned long)0); + } + + sdma_data[channel].bd_number = (p->bd_number <= 0) ? 1 : p->bd_number; + + sdma_data[channel].word_size = p->word_size; + + sdma_data[channel].event_id = p->event_id; + sdma_data[channel].event_id2 = p->event_id2; + + sdma_data[channel].callback = p->callback; + + sdma_data[channel].arg = p->arg; + + err = iapi_IoCtl(sdma_data[channel].cd, + IAPI_CHANGE_BDNUM, sdma_data[channel].bd_number); + + if (err < 0) { + printk(KERN_ERR "Failed allocating buffer \ +descriptors (0x%x)\n", err); + err = -ENOMEM; + goto setup_channel_fail; + } + + if (channel != 0) { + switch (p->transfer_type) { + case dsp_2_per: + break; + case emi_2_per: + case int_2_per: + case per_2_int: + case per_2_emi: + case per_2_per: + /* + * Peripheral <------> Memory + * evtOvr = 0 dspOvr = 1 + */ + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + if (p->event_id) { + err = iapi_SetChannelEventMapping(p->event_id, + 0x1 << + channel); + } + if (!err && p->event_id2) { + err = iapi_SetChannelEventMapping(p->event_id2, + 0x1 << + channel); + } + break; + case emi_2_dsp: + case int_2_dsp: + case dsp_2_int: + case dsp_2_emi: + case dsp_2_dsp: + /* + * DSP <-----------> Memory + * evtOvr = 1 dspOvr = 0 + */ + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + break; + case emi_2_int: + case emi_2_emi: + case int_2_int: + case int_2_emi: + case emi_2_dsp_loop: + case dsp_2_emi_loop: + /* evtOvr = 1 dspOvr = 1 */ + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + break; + case per_2_dsp: + /* evtOvr = 0 dspOvr = 0 */ + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + err = iapi_SetChannelEventMapping(p->event_id, + 0x1 << channel); + break; + default: + break; + printk(KERN_ERR "Wrong SDMA transfer type\n"); + err = -EINVAL; + } + if (err == 0) { + err = sdma_load_context(channel, p); + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_PRIORITY, + MXC_SDMA_DEFAULT_PRIORITY); + } + } + setup_channel_fail: + return err; +} + +/*! + * Setup the channel priority. This can be used to change the default priority + * for the channel. + * + * @param channel channel number + * @param priority priority to be set for the channel + * + * @return 0 on success, error code on failure + */ +int mxc_dma_set_channel_priority(unsigned int channel, unsigned int priority) +{ + if (priority < MXC_SDMA_MIN_PRIORITY + || priority > MXC_SDMA_MAX_PRIORITY) { + return -EINVAL; + } + return iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_PRIORITY, + priority); +} + +/*! + * Allocates dma channel. + * If channel's value is 0, then the function allocates a free channel + * dynamically and sets its value to channel. + * Else allocates requested channel if it is free. + * If the channel is busy or no free channels (in dynamic allocation) -EBUSY returned. + * + * @param channel pointer to channel number + * @param devicename device name + * @return 0 on success, error code on fail + */ +int mxc_request_dma(int *channel, const char *devicename) +{ + int i, res; + + res = 0; + + down(&sdma_status_mutex); + + /* Dynamic allocation */ + if (*channel == 0) { + for (i = MAX_DMA_CHANNELS - 1; i > 0; i--) { +#ifdef CONFIG_SDMA_IRAM + /*TODO:It will be removed after DPTC used UDMA interface */ + if (i >= MXC_DMA_CHANNEL_IRAM) + continue; +#endif /*CONFIG_SDMA_IRAM */ + if (!sdma_data[i].in_use) { + *channel = i; + break; + } + } + } + + if (*channel > 0 && *channel < MAX_DMA_CHANNELS && + sdma_data[*channel].in_use == 0) { + res = iapi_Open(sdma_data[0].cd, *channel); + + if (res < 0) { + printk(KERN_ERR "Failed iapi_Open channel %d, 0x%x\n", + *channel, res); + } else { + sdma_data[*channel].in_use = 1; + strcpy(sdma_data[*channel].devicename, devicename); + sdma_data[*channel].cd = CHAD(*channel); + + iapi_IoCtl(sdma_data[*channel].cd, IAPI_CHANGE_SYNCH, + CALLBACK_ISR); + iapi_IoCtl(sdma_data[*channel].cd, + IAPI_CHANGE_CALLBACKFUNC, + (unsigned long)iapi_interrupt_callback); + iapi_IoCtl(sdma_data[*channel].cd, + IAPI_CHANGE_USER_ARG, + (unsigned long)&(sdma_data[*channel])); + } + } else { + res = -EBUSY; + } + + up(&sdma_status_mutex); + + return res; +} + +/*! + * Configures request parameters. Can be called multiple times after + * mxc_request_dma() and mxc_dma_setup_channel(). + * + * + * @param channel channel number + * @param p request parameters pointer + * @param bd_index index of buffer descriptor to set + * @return 0 on success, error code on fail + */ +int mxc_dma_set_config(int channel, dma_request_t *p, int bd_index) +{ + unsigned char param; + + if (!sdma_data[channel].in_use) { + return -EINVAL; + } + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_TRANSFER_CD, sdma_data[channel].word_size); + + param = BD_DONE | BD_INTR | BD_EXTD; + + if (sdma_data[channel].bd_number > 1 && p->bd_cont == 1) { + param |= BD_CONT; + } + + if (bd_index == sdma_data[channel].bd_number - 1) { + param |= BD_WRAP; + } + + switch (sdma_data[channel].transfer_type) { + case emi_2_per: + case dsp_2_per: + case int_2_per: + case emi_2_dsp: + case int_2_dsp: + case emi_2_dsp_loop: + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_BUFFERADDR, + (unsigned long)p->sourceAddr); + break; + case per_2_int: + case per_2_emi: + case per_2_dsp: + case dsp_2_int: + case dsp_2_emi: + case dsp_2_dsp: + case dsp_2_emi_loop: + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_BUFFERADDR, + (unsigned long)p->destAddr); + break; + case emi_2_int: + case emi_2_emi: + case int_2_int: + case int_2_emi: + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_BUFFERADDR, + (unsigned long)p->sourceAddr); + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_EXTDBUFFERADDR, + (unsigned long)p->destAddr); + break; + default: + break; + } + + /* Change the endianness for DSP to MCU Data transfers */ + if (sdma_data[channel].transfer_type == dsp_2_emi || + sdma_data[channel].transfer_type == emi_2_dsp) { + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_SET_ENDIANNESS, + SET_BIT_ALL); + } + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_COUNT, p->count); + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | IAPI_CHANGE_SET_STATUS, param); + + return 0; +} + +/*! + * Configures the BD_INTR bit on a buffer descriptor parameters. + * + * + * @param channel channel number + * @param bd_index index of buffer descriptor to set + * @param bd_intr flag to set or clear the BD_INTR bit + * @return 0 on success, error code on fail + */ +void mxc_dma_set_bd_intr(int channel, int bd_index, int bd_intr) +{ + unsigned long param; + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_STATUS, (unsigned long)¶m); + + if (bd_intr) { + param |= BD_INTR; + } else { + param &= ~BD_INTR; + } + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | IAPI_CHANGE_SET_STATUS, param); + +} + +/*! + * Gets the BD_INTR bit on a buffer descriptor. + * + * + * @param channel channel number + * @param bd_index index of buffer descriptor to set + * + * @return returns the BD_INTR bit status + */ +int mxc_dma_get_bd_intr(int channel, int bd_index) +{ + unsigned long bd_status = 0; + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_STATUS, (unsigned long)&bd_status); + + return bd_status & BD_INTR; +} + +/*! + * Stop the current transfer + * + * @param channel channel number + * @param buffer_number number of buffers (beginning with 0), + * whose done bits should be reset to 0 + */ +int mxc_dma_reset(int channel, int buffer_number) +{ + unsigned char param = 0; + int i = 0; + + if (!sdma_data[channel].in_use) { + return -EINVAL; + } + + /* clear the BD_DONE bits for all the necessary buffers */ + for (i = 0; i < buffer_number; i++) { + + iapi_IoCtl(sdma_data[channel].cd, (i << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_STATUS, (unsigned long)¶m); + + /* clear the BD_DONE bit of the buffer */ + param = param & (~BD_DONE); + + iapi_IoCtl(sdma_data[channel].cd, (i << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_STATUS, param); + } + + return 0; +} + +/*! + * Returns request parameters. + * + * @param channel channel number + * @param p request parameters pointer + * @param bd_index index of buffer descriptor to get + * @return 0 on success, error code on fail + */ +int mxc_dma_get_config(int channel, dma_request_t *p, int bd_index) +{ + int err = 0; + unsigned long bd_status; + unsigned long bd_count; + __u8 *sourceAddr; + __u8 *destAddr; + + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_STATUS, (unsigned long)&bd_status); + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_COUNT, (unsigned long)&bd_count); + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_BUFFERADDR, (unsigned long)&sourceAddr); + + switch (sdma_data[channel].transfer_type) { + case emi_2_per: + case dsp_2_per: + case int_2_per: + case emi_2_dsp: + case int_2_dsp: + case emi_2_dsp_loop: + p->sourceAddr = sourceAddr; + break; + case per_2_int: + case per_2_emi: + case per_2_dsp: + case dsp_2_int: + case dsp_2_emi: + case dsp_2_dsp: + case dsp_2_emi_loop: + p->destAddr = sourceAddr; + break; + case emi_2_int: + case emi_2_emi: + case int_2_int: + case int_2_emi: + p->sourceAddr = sourceAddr; + iapi_IoCtl(sdma_data[channel].cd, + (bd_index << BD_NUM_OFFSET) | + IAPI_CHANGE_GET_EXTDBUFFERADDR, + (unsigned long)&destAddr); + p->destAddr = destAddr; + break; + default: + break; + } + + p->count = bd_count; + p->bd_done = bd_status & BD_DONE; + p->bd_cont = bd_status & BD_CONT; + p->bd_error = bd_status & BD_RROR; + + return err; +} + +/*! + * This function is used by MXC IPC's write_ex2. It passes the pointer to the + * data control structure to iapi_write_ipcv2() + * + * @param channel SDMA channel number + * @param ctrl_ptr Data Control structure pointer + */ +int mxc_sdma_write_ipcv2(int channel, void *ctrl_ptr) +{ + return iapi_Write_ipcv2(sdma_data[channel].cd, ctrl_ptr); +} + +/*! + * This function is used by MXC IPC's read_ex2. It passes the pointer to the + * data control structure to iapi_read_ipcv2() + * + * @param channel SDMA channel number + * @param ctrl_ptr Data Control structure pointer + */ +int mxc_sdma_read_ipcv2(int channel, void *ctrl_ptr) +{ + return iapi_Read_ipcv2(sdma_data[channel].cd, ctrl_ptr); +} + +/*! + * Starts dma channel. + * + * @param channel channel number + */ +int mxc_dma_start(int channel) +{ + if (sdma_data[channel].running == 0) { + sdma_data[channel].running = 1; + iapi_StartChannel(channel); + } + + return 0; +} + +/*! + * Stops dma channel. + * + * @param channel channel number + */ +int mxc_dma_stop(int channel) +{ + iapi_StopChannel(channel); + sdma_data[channel].running = 0; + + return 0; +} + +/*! + * Frees dma channel. + * + * @param channel channel number + */ +void mxc_free_dma(int channel) +{ + int i; + + mxc_dma_stop(channel); + + if (sdma_data[channel].event_id != 0) { + iapi_SetChannelEventMapping(sdma_data[channel].event_id, 0x0); + } + if (sdma_data[channel].event_id2 != 0) { + iapi_SetChannelEventMapping(sdma_data[channel].event_id2, 0x0); + } + + sdma_data[channel].event_id = 0; + + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_PRIORITY, 0x0); + iapi_IoCtl(sdma_data[channel].cd, IAPI_CHANGE_OWNERSHIP, + (OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + + for (i = 0; i < sdma_data[channel].bd_number; i++) { + iapi_IoCtl(sdma_data[channel].cd, + (i << BD_NUM_OFFSET) | + IAPI_CHANGE_SET_STATUS, (unsigned long)0); + } + + iapi_Close(sdma_data[channel].cd); + + strcpy(sdma_data[channel].devicename, "not used"); + + sdma_data[channel].in_use = 0; +} + +/*! + * Initializes channel's priorities + * + */ +static void __init init_priorities(void) +{ + iapi_IoCtl(sdma_data[0].cd, IAPI_CHANGE_PRIORITY, 0x7); +} + +/*! + * Initializes events table + */ +static void __init init_event_table(void) +{ + int channel; + + for (channel = 0; channel < MAX_DMA_CHANNELS; channel++) { + iapi_SetChannelEventMapping(channel, 0); + } +} + +/*! + * Sets callback function. Used with standard dma api + * for supporting interrupts + * + * @param channel channel number + * @param callback callback function pointer + * @param arg argument for callback function + */ +void mxc_dma_set_callback(int channel, dma_callback_t callback, void *arg) +{ + sdma_data[channel].callback = callback; + sdma_data[channel].arg = arg; +} + +/*! + * Synchronization function used by I.API + * + * @param channel channel number + */ +static int getChannel(int channel) +{ + if (irqs_disabled() || in_atomic()) { + if (down_trylock(&sdma_synch_mutex[channel])) { + return -EBUSY; + } + } else { + if (down_interruptible(&sdma_synch_mutex[channel])) { + return -EBUSY; + } + } + + return 0; +} + +/*! + * Synchronization function used by I.API + * + * @param channel channel number + */ +static int releaseChannel(int channel) +{ + up(&sdma_synch_mutex[channel]); + return 0; +} + +/*! + * Unmask interrupt function. Used by I.API + * + */ +static void unmask_sdma_interrupt(void) +{ + /* Commented out tp take care of the PREEMPT_RT option + * local_irq_restore(flags); + */ +} + +/*! + * Mask interrupt function. Used by I.API + * + */ +static void mask_sdma_interrupt(void) +{ + /* Commented to take of the PREEMPT_RT option + * local_irq_save(flags); + */ +} + +/*! + * Initializes I.API + */ +static void __init init_iapi_struct(void) +{ + channelDescriptor *cd; + + printk(KERN_INFO "Using SDMA I.API\n"); + + iapi_Malloc = &sdma_malloc; +#ifdef CONFIG_SDMA_IRAM + iapi_iram_Malloc = &sdma_iram_malloc; +#endif /*CONFIG_SDMA_IRAM */ + + iapi_Free = &sdma_free; + iapi_Virt2Phys = (void *(*)(void *))&sdma_virt_to_phys; + iapi_Phys2Virt = (void *(*)(void *))&sdma_phys_to_virt; + iapi_memset = &memset; + iapi_memcpy = &memcpy; + + iapi_GotoSleep = &sdma_sleep_channel; + iapi_WakeUp = &sdma_wakeup_channel; + iapi_InitSleep = &sdma_init_sleep; + iapi_ReleaseChannel = &releaseChannel; + iapi_GetChannel = &getChannel; + + iapi_EnableInterrupts = &unmask_sdma_interrupt; + iapi_DisableInterrupts = &mask_sdma_interrupt; + + cd = kmalloc(sizeof(channelDescriptor), GFP_KERNEL); + + memset(cd, 0, sizeof(channelDescriptor)); + + sdma_data[0].cd = cd; +} + +/*! + * Initializes channel synchronization mutexes + */ +static void __init init_mutexes(void) +{ + int i; + + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + init_MUTEX(&sdma_synch_mutex[i]); + } + + init_MUTEX(&sdma_status_mutex); +} + +/*! + * Channels status read proc file system function + * + * @param buf pointer to the buffer the data shuld be written to. + * @param start pointer to the pointer where the new data is + * written to. + * procedure should update the start pointer to point to + * where in the buffer the data was written. + * @param offset offset from start of the file + * @param count number of bytes to read. + * @param eof pointer to eof flag. sould be set to 1 when + * reaching eof. + * @param data driver specific data pointer. + * + * @return number byte read from the log buffer. + */ +static int proc_read_channels(char *buf, char **start, off_t offset, int count, + int *eof, void *data) +{ + char *log; + char *log_ptr; + char tmp[48]; + int i; + + log = kmalloc(4096, GFP_KERNEL); + memset(log, 0, 4096); + log_ptr = log; + + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + if (sdma_data[i].in_use == 0) { + continue; + } + + memset(tmp, 0, 48); + sprintf(tmp, "Channel %d: %s\n", i, sdma_data[i].devicename); + + strcpy(log_ptr, tmp); + log_ptr += strlen(tmp); + } + + if (offset > strlen(log)) { + *eof = 1; + count = 0; + } else { + if (offset + count > strlen(log)) { + count = strlen(log) - offset; + *eof = 1; + } else { + *eof = 0; + } + + memcpy(buf, log, count); + *start = buf; + kfree(log); + } + + return count; +} + +/*! + * SDMA proc file system read function + */ +static int __init init_proc_fs(void) +{ + struct proc_dir_entry *sdma_proc_dir; + int res; + + res = 0; + + sdma_proc_dir = proc_mkdir("sdma", NULL); + create_proc_read_entry("channels", 0, sdma_proc_dir, + proc_read_channels, NULL); + + if (res < 0) { + printk(KERN_WARNING "Failed create SDMA proc entry\n"); + } + + return res; +} + +/*! + * Initializes SDMA private data + */ +static void __init init_sdma_data(void) +{ + int i; + + memset(sdma_data, 0, sizeof(sdma_struct) * MAX_DMA_CHANNELS); + sdma_data[0].in_use = 1; + strcpy(sdma_data[0].devicename, "MCU"); + + for (i = 0; i < MAX_DMA_CHANNELS; i++) { + sdma_data[i].channel = i; + } +} + +#if defined(CONFIG_MXC_SUPER_GEM) +/*! + * Initialize the Super GEM SDMA channel + * + * @return returns -1 on error, 0 on success. + */ +static int __init init_super_gem(void) +{ + channelDescriptor *cd; + script_data context; + int res = 0; + + res = iapi_Open(sdma_data[0].cd, MXC_DMA_CHANNEL_GEM); + if (res < 0) { + return -1; + } + sdma_data[MXC_DMA_CHANNEL_GEM].in_use = 1; + cd = CHAD(MXC_DMA_CHANNEL_GEM); + memset(&context, 0, sizeof(script_data)); + context.load_address = sdma_script_addrs.mxc_sdma_utra_addr; + context.wml = M3_BASE_ADDRESS; + res = iapi_AssignScript(cd, &context); + if (res < 0) { + iapi_Close(cd); + sdma_data[MXC_DMA_CHANNEL_GEM].in_use = 0; + return -1; + } + res = + iapi_IoCtl(cd, IAPI_CHANGE_OWNERSHIP, + (OWN_CHANNEL << CH_OWNSHP_OFFSET_EVT) | + (DONT_OWN_CHANNEL << CH_OWNSHP_OFFSET_MCU) | + (OWN_CHANNEL << CH_OWNSHP_OFFSET_DSP)); + if (res < 0) { + iapi_Close(cd); + sdma_data[MXC_DMA_CHANNEL_GEM].in_use = 0; + return -1; + } + /* Set EP=1, which is required to start SuperGem script the first time */ + /* This can be done only on the AP side */ + SDMA_H_EVTPEND |= 1 << MXC_DMA_CHANNEL_GEM; + + res = + iapi_SetChannelEventMapping(DMA_REQ_GEM, 1 << MXC_DMA_CHANNEL_GEM); + if (res < 0) { + iapi_Close(cd); + sdma_data[MXC_DMA_CHANNEL_GEM].in_use = 0; + return -1; + } + + return 0; +} +#endif + +int sdma_probe(struct platform_device *pdev) +{ + int res = 0; + int irq; + struct resource *rsrc; + configs_data confreg_data; + + /* Initialize to the default values */ + confreg_data = iapi_ConfigDefaults; + + confreg_data.dspdma = 0; + /* Set ACR bit */ + mxc_sdma_ahb_clk = clk_get(&pdev->dev, "sdma_ahb_clk"); + mxc_sdma_ipg_clk = clk_get(&pdev->dev, "sdma_ipg_clk"); + clk_enable(mxc_sdma_ahb_clk); + clk_enable(mxc_sdma_ipg_clk); + if (clk_get_rate(mxc_sdma_ahb_clk) / clk_get_rate(mxc_sdma_ipg_clk) < 2) { + printk(KERN_INFO "Setting SDMA ACR\n"); + confreg_data.acr = 1; + } + + init_sdma_data(); + + init_sdma_pool(); + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) { + res = -ENODEV; + goto sdma_init_fail; + } + res = request_irq(irq, sdma_int_handler, 0, dev_name(&pdev->dev), 0); + + if (res < 0) { + goto sdma_init_fail; + } + + rsrc = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (rsrc < 0) { + res = -ENODEV; + goto sdma_init_fail; + } + sdma_base = ioremap(rsrc->start, SZ_4K); + if (sdma_base == NULL) + goto sdma_init_fail; + + init_mutexes(); + + init_iapi_struct(); + + mxc_sdma_get_script_info(&sdma_script_addrs); + + res = iapi_Init(sdma_data[0].cd, &confreg_data, + sdma_script_addrs.mxc_sdma_start_addr, + sdma_script_addrs.mxc_sdma_ram_code_size * 2, + sdma_script_addrs.mxc_sdma_ram_code_start_addr); + + if (res < 0) { + free_irq(irq, 0); + goto sdma_init_fail; + } + + init_priorities(); + + init_event_table(); + + init_proc_fs(); + + printk(KERN_INFO "MXC DMA API initialized\n"); + + clk_disable(mxc_sdma_ahb_clk); + clk_disable(mxc_sdma_ipg_clk); + return res; + + sdma_init_fail: + printk(KERN_ERR "Error 0x%x in sdma_init\n", res); + clk_disable(mxc_sdma_ahb_clk); + clk_disable(mxc_sdma_ipg_clk); + return res; +} + +static struct platform_driver sdma_driver = { + .driver = { + .name = "mxc_sdma", + }, + .probe = sdma_probe, +}; + +/*! + * Initializes dma + */ +int __init sdma_init(void) +{ + return platform_driver_register(&sdma_driver); +} +arch_initcall(sdma_init); + +EXPORT_SYMBOL(mxc_request_dma); +EXPORT_SYMBOL(mxc_free_dma); +EXPORT_SYMBOL(mxc_dma_setup_channel); +EXPORT_SYMBOL(mxc_dma_set_channel_priority); +EXPORT_SYMBOL(mxc_dma_set_config); +EXPORT_SYMBOL(mxc_dma_get_config); +EXPORT_SYMBOL(mxc_dma_set_bd_intr); +EXPORT_SYMBOL(mxc_dma_get_bd_intr); +EXPORT_SYMBOL(mxc_dma_reset); +EXPORT_SYMBOL(mxc_sdma_write_ipcv2); +EXPORT_SYMBOL(mxc_sdma_read_ipcv2); +EXPORT_SYMBOL(mxc_dma_start); +EXPORT_SYMBOL(mxc_dma_stop); +EXPORT_SYMBOL(sdma_malloc); +EXPORT_SYMBOL(sdma_free); +EXPORT_SYMBOL(mxc_dma_set_callback); +EXPORT_SYMBOL(sdma_virt_to_phys); +EXPORT_SYMBOL(sdma_phys_to_virt); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Linux SDMA API"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/sdma/sdma_malloc.c b/arch/arm/plat-mxc/sdma/sdma_malloc.c new file mode 100644 index 000000000000..a9f86b327a98 --- /dev/null +++ b/arch/arm/plat-mxc/sdma/sdma_malloc.c @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file plat-mxc/sdma/sdma_malloc.c + * @brief This file contains functions for SDMA non-cacheable buffers allocation + * + * SDMA (Smart DMA) is used for transferring data between MCU and peripherals + * + * @ingroup SDMA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define DEBUG 0 + +#if DEBUG +#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) +#else +#define DPRINTK(fmt, args...) +#endif + +#ifdef CONFIG_SDMA_IRAM +#define IRAM_SDMA_SIZE SZ_4K +#endif + +/*! + * Defines SDMA non-cacheable buffers pool + */ +static struct dma_pool *pool; +static struct gen_pool *sdma_iram_pool; + +/*! + * SDMA memory conversion hashing structure + */ +typedef struct { + struct list_head node; + /*! Virtual address */ + void *virt; + /*! Physical address */ + unsigned long phys; + int size; + bool in_iram; +} virt_phys_struct; + +static struct list_head alloc_list; + +/*! + * Defines the size of each buffer in SDMA pool. + * The size must be at least 512 bytes, because + * sdma channel control blocks array size is 512 bytes + */ +#define SDMA_POOL_SIZE 1024 + +#ifdef CONFIG_SDMA_IRAM +static unsigned long iram_paddr; +static void *iram_vaddr; +#define iram_phys_to_virt(p) (iram_vaddr + ((p) - iram_paddr)) +#define iram_virt_to_phys(v) (iram_paddr + ((v) - iram_vaddr)) +#endif + +/*! + * Virtual to physical address conversion functio + * + * @param buf pointer to virtual address + * + * @return physical address + */ +unsigned long sdma_virt_to_phys(void *buf) +{ + u32 offset = (u32) buf & (~PAGE_MASK); + virt_phys_struct *p; + + DPRINTK("searching for vaddr 0x%p\n", buf); + + list_for_each_entry(p, &alloc_list, node) { + if (((u32)p->virt & PAGE_MASK) == ((u32) buf & PAGE_MASK)) { + return (p->phys & PAGE_MASK) | offset; + } + } + + if (virt_addr_valid(buf)) { + return virt_to_phys(buf); + } + + printk(KERN_WARNING + "SDMA malloc: could not translate virt address 0x%p\n", buf); + return 0; +} + +/*! + * Physical to virtual address conversion functio + * + * @param buf pointer to physical address + * + * @return virtual address + */ +void *sdma_phys_to_virt(unsigned long buf) +{ + u32 offset = buf & (~PAGE_MASK); + virt_phys_struct *p; + + DPRINTK("searching for paddr 0x%p\n", buf); + + list_for_each_entry(p, &alloc_list, node) { + if ((p->phys & PAGE_MASK) == (buf & PAGE_MASK)) { + return (void *)(((u32)p->virt & PAGE_MASK) | offset); + } + } + + printk(KERN_WARNING + "SDMA malloc: could not translate phys address 0x%lx\n", buf); + return 0; +} + +/*! + * Allocates uncacheable buffer + * + * @param size size of allocated buffer + * @return pointer to buffer + */ +void *sdma_malloc(size_t size) +{ + void *buf; + dma_addr_t dma_addr; + virt_phys_struct *p; + + if (size > SDMA_POOL_SIZE) { + printk(KERN_WARNING + "size in sdma_malloc is more than %d bytes\n", + SDMA_POOL_SIZE); + return 0; + } + + buf = dma_pool_alloc(pool, GFP_KERNEL, &dma_addr); + if (buf == 0) + return 0; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + p->virt = buf; + p->phys = dma_addr; + list_add_tail(&p->node, &alloc_list); + + DPRINTK("allocated vaddr 0x%p\n", buf); + return buf; +} + +/*! + * Frees uncacheable buffer + * + * @param buf buffer pointer for deletion + */ +void sdma_free(void *buf) +{ + virt_phys_struct *p; + + list_for_each_entry(p, &alloc_list, node) { + if (p->virt == buf) { + if (p->in_iram) + gen_pool_free(sdma_iram_pool, p->phys, p->size); + else + dma_pool_free(pool, p->virt, p->phys); + list_del(&p->node); + kfree(p); + return; + } + } +} + +#ifdef CONFIG_SDMA_IRAM +/*! + * Allocates uncacheable buffer from IRAM + */ +void *sdma_iram_malloc(size_t size) +{ + virt_phys_struct *p = kzalloc(sizeof(*p), GFP_KERNEL); + unsigned long buf; + + buf = gen_pool_alloc(sdma_iram_pool, size); + if (!buf) { + kfree(p); + return NULL; + } + + p->virt = iram_vaddr + (buf - iram_paddr); + p->phys = buf; + p->size = size; + p->in_iram = true; + list_add_tail(&p->node, &alloc_list); + return p->virt; +} +#endif /*CONFIG_SDMA_IRAM */ + +/*! + * SDMA buffers pool initialization function + */ +void __init init_sdma_pool(void) +{ + pool = dma_pool_create("SDMA", NULL, SDMA_POOL_SIZE, 0, 0); + +#ifdef CONFIG_SDMA_IRAM + iram_vaddr = iram_alloc(SZ_4K, &iram_paddr); + sdma_iram_pool = gen_pool_create(6, -1); + gen_pool_add(sdma_iram_pool, iram_paddr, SZ_4K, -1); +#endif + + INIT_LIST_HEAD(&alloc_list); +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Linux SDMA API"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/serialxc.c b/arch/arm/plat-mxc/serialxc.c new file mode 100644 index 000000000000..be8c75db8aba --- /dev/null +++ b/arch/arm/plat-mxc/serialxc.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static void usb_serial_init(struct fsl_xcvr_ops *this) +{ +} + +static void usb_serial_uninit(struct fsl_xcvr_ops *this) +{ +} + +static struct fsl_xcvr_ops serial_ops = { + .name = "serial", + .xcvr_type = PORTSC_PTS_SERIAL, + .init = usb_serial_init, + .uninit = usb_serial_uninit, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init serialxc_init(void) +{ + pr_debug("%s\n", __FUNCTION__); + + fsl_usb_xcvr_register(&serial_ops); + + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit serialxc_exit(void) +{ + fsl_usb_xcvr_unregister(&serial_ops); +} + +subsys_initcall(serialxc_init); +module_exit(serialxc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("serial xcvr driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/snoop.c b/arch/arm/plat-mxc/snoop.c new file mode 100644 index 000000000000..bc733033d872 --- /dev/null +++ b/arch/arm/plat-mxc/snoop.c @@ -0,0 +1,133 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include + +#ifdef M4IF_BASE_ADDR +#define SNOOP_V2 +#define MAX_SNOOP 2 +#define g_snoop_base (IO_ADDRESS(M4IF_BASE_ADDR) + 0x4C) +#elif defined(M3IF_BASE_ADDR) +#define MAX_SNOOP 1 +#define g_snoop_base (IO_ADDRESS(M3IF_BASE_ADDR) + 0x28) +#else +#define MAX_SNOOP 0 +#define g_snoop_base 0 +#endif + +/* M3IF Snooping Configuration Register 0 (M3IFSCFG0) READ/WRITE*/ +#define SBAR(x) (x * 0x14) +/* M3IF Snooping Configuration Register 1 (M3IFSCFG1) READ/WRITE*/ +#define SERL(x) ((x * 0x14) + 0x4) +/* M3IF Snooping Configuration Register 2 (M3IFSCFG2) READ/WRITE*/ +#define SERH(x) ((x * 0x14) + 0x8) +/* M3IF Snooping Status Register 0 (M3IFSSR0) READ/WRITE */ +#define SSRL(x) ((x * 0x14) + 0xC) +/* M3IF Snooping Status Register 1 (M3IFSSR1) */ +#define SSRH(x) ((x * 0x14) + 0x10) + +#if MAX_SNOOP + +int mxc_snoop_set_config(u32 num, unsigned long base, int size) +{ + u32 reg; + uint32_t msb; + uint32_t seg_size; + uint32_t window_size = 0; + int i; + + if (num >= MAX_SNOOP) { + return -EINVAL; + } + + /* Setup M3IF for snooping */ + if (size) { + + if (base == 0) { + return -EINVAL; + } + + msb = fls(size); + if (!(size & ((1UL << msb) - 1))) + msb--; /* Already aligned to power 2 */ + if (msb < 11) + msb = 11; + + window_size = (1UL << msb); + seg_size = window_size / 64; + + msb -= 11; + + reg = base & ~((1UL << msb) - 1); + reg |= msb << 1; + reg |= 1; /* enable snooping */ + reg |= 0x80; /* Set pulse width to default (M4IF only) */ + __raw_writel(reg, g_snoop_base + SBAR(num)); + + reg = 0; + for (i = 0; i < 32; i++) { + if (i * seg_size >= size) + break; + reg |= 1UL << i; + } + __raw_writel(reg, g_snoop_base + SERL(num)); + + reg = 0; + for (i = 32; i < 64; i++) { + if (i * seg_size >= size) + break; + reg |= 1UL << (i - 32); + } + __raw_writel(reg, g_snoop_base + SERH(num)); + + pr_debug + ("Snooping unit # %d enabled: window size = 0x%X, M3IFSCFG0=0x%08X, M3IFSCFG1=0x%08X, M3IFSCFG2=0x%08X\n", + num, window_size, __raw_readl(g_snoop_base + SBAR(num)), + __raw_readl(g_snoop_base + SERL(num)), + __raw_readl(g_snoop_base + SERH(num))); + } else { + __raw_writel(0, g_snoop_base + SBAR(num)); + } + + return window_size; +} + +EXPORT_SYMBOL(mxc_snoop_set_config); + +int mxc_snoop_get_status(u32 num, u32 *statl, u32 *stath) +{ + if (num >= MAX_SNOOP) { + return -EINVAL; + } + + *statl = __raw_readl(g_snoop_base + SSRL(num)); + *stath = __raw_readl(g_snoop_base + SSRH(num)); + /* DPRINTK("status = 0x%08X%08X\n", stat[1], stat[0]); */ + +#ifdef SNOOP_V2 + __raw_writel(*statl, g_snoop_base + SSRL(num)); + __raw_writel(*stath, g_snoop_base + SSRH(num)); +#else + __raw_writel(0x0, g_snoop_base + SSRL(num)); + __raw_writel(0x0, g_snoop_base + SSRH(num)); +#endif + return 0; +} + +EXPORT_SYMBOL(mxc_snoop_get_status); + +#endif /* MAX_SNOOP */ diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 97f42799fa58..398b4e1e2e06 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -1,7 +1,7 @@ /* * Copyright (C) 1999 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2006-2010 Freescale Semiconductor * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com * @@ -32,6 +32,8 @@ #include static void __iomem *wdog_base; +extern int dvfs_core_is_active; +extern void stop_dvfs(void); /* * Reset the system. It is called by machine_restart(). @@ -46,6 +48,21 @@ void arch_reset(char mode, const char *cmd) return; } #endif + +#ifdef CONFIG_ARCH_MX51 + /* Workaround to reset NFC_CONFIG3 register + * due to the chip warm reset does not reset it + */ + if (cpu_is_mx51() || cpu_is_mx53()) + __raw_writel(0x20600, IO_ADDRESS(NFC_BASE_ADDR) + 0x28); +#endif + +#ifdef CONFIG_ARCH_MX5 + /* Stop DVFS-CORE before reboot. */ + if (dvfs_core_is_active) + stop_dvfs(); +#endif + if (cpu_is_mx1()) { wcr_enable = (1 << 0); } else { diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index f9a1b059a76c..a3f1c7de27f6 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -56,6 +56,7 @@ /* MX31, MX35, MX25, MXC91231, MX5 */ #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ #define V2_TCTL_CLK_IPG (1 << 6) +#define V2_TCTL_CLK_PER (2 << 6) #define V2_TCTL_FRR (1 << 9) #define V2_IR 0x0c #define V2_TSTAT 0x08 @@ -124,6 +125,15 @@ static struct clocksource clocksource_mxc = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +unsigned long long sched_clock(void) +{ + if (!timer_base) + return 0; + + return clocksource_cyc2ns(clocksource_mxc.read(&clocksource_mxc), + clocksource_mxc.mult, clocksource_mxc.shift); +} + static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); @@ -308,7 +318,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) - tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 9b86d2a60d43..857cc0ca9a7a 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -1,5 +1,5 @@ /* - * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -14,11 +14,10 @@ #include #include #include +#include #include - +#include #include - -#include #include /* @@ -26,39 +25,41 @@ * TZIC Registers * ***************************************** */ - -#define TZIC_INTCNTL 0x0000 /* Control register */ -#define TZIC_INTTYPE 0x0004 /* Controller Type register */ -#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ -#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ -#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ -#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ -#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ -#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ -#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ -#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ -#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ -#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ -#define TZIC_PND0 0x0D00 /* Pending Register 0 */ -#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ -#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ -#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ -#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ - -void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ +void __iomem *tzic_base; + +#define TZIC_BASE (tzic_base) +#define TZIC_INTCNTL (TZIC_BASE + 0x0000) /* control register */ +#define TZIC_INTTYPE (TZIC_BASE + 0x0004) /* Controller type register */ +#define TZIC_IMPID (TZIC_BASE + 0x0008) /* Distributor Implementer Identification Register */ +#define TZIC_PRIOMASK (TZIC_BASE + 0x000C) /* Priority Mask Reg */ +#define TZIC_SYNCCTRL (TZIC_BASE + 0x0010) /* Synchronizer Control register */ +#define TZIC_DSMINT (TZIC_BASE + 0x0014) /* DSM interrupt Holdoffregister */ +#define TZIC_INTSEC0 (TZIC_BASE + 0x0080) /* interrupt security register 0 */ +#define TZIC_ENSET0 (TZIC_BASE + 0x0100) /* Enable Set Register 0 */ +#define TZIC_ENCLEAR0 (TZIC_BASE + 0x0180) /* Enable Clear Register 0 */ +#define TZIC_SRCSET0 (TZIC_BASE + 0x0200) /* Source Set Register 0 */ +#define TZIC_SRCCLAR0 (TZIC_BASE + 0x0280) /* Source Clear Register 0 */ +#define TZIC_PRIORITY0 (TZIC_BASE + 0x0400) /* Priority Register 0 */ +#define TZIC_PND0 (TZIC_BASE + 0x0D00) /* Pending Register 0 */ +#define TZIC_HIPND0 (TZIC_BASE + 0x0D80) /* High Priority Pending Register */ +#define TZIC_WAKEUP0 (TZIC_BASE + 0x0E00) /* Wakeup Config Register */ +#define TZIC_SWINT (TZIC_BASE + 0x0F00) /* Software Interrupt Rigger Register */ +#define TZIC_ID0 (TZIC_BASE + 0x0FD0) /* Indentification Register 0 */ + +#define TZIC_NUM_IRQS 128 /** * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC * * @param irq interrupt source number */ -static void tzic_mask_irq(unsigned int irq) +static void mxc_mask_irq(unsigned int irq) { int index, off; index = irq >> 5; off = irq & 0x1F; - __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); + __raw_writel(1 << off, TZIC_ENCLEAR0 + (index << 2)); } /** @@ -66,13 +67,13 @@ static void tzic_mask_irq(unsigned int irq) * * @param irq interrupt source number */ -static void tzic_unmask_irq(unsigned int irq) +static void mxc_unmask_irq(unsigned int irq) { int index, off; index = irq >> 5; off = irq & 0x1F; - __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); + __raw_writel(1 << off, TZIC_ENSET0 + (index << 2)); } static unsigned int wakeup_intr[4]; @@ -86,7 +87,7 @@ static unsigned int wakeup_intr[4]; * * @return This function returns 0 on success. */ -static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) +static int mxc_set_wake_irq(unsigned int irq, unsigned int enable) { unsigned int index, off; @@ -106,54 +107,58 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) static struct irq_chip mxc_tzic_chip = { .name = "MXC_TZIC", - .ack = tzic_mask_irq, - .mask = tzic_mask_irq, - .unmask = tzic_unmask_irq, - .set_wake = tzic_set_wake_irq, + .ack = mxc_mask_irq, + .mask = mxc_mask_irq, + .unmask = mxc_unmask_irq, + .set_wake = mxc_set_wake_irq, }; -/* +/*! * This function initializes the TZIC hardware and disables all the * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. */ -void __init tzic_init_irq(void __iomem *irqbase) +void __init mxc_tzic_init_irq(unsigned long base) { int i; - tzic_base = irqbase; + tzic_base = ioremap(base, SZ_4K); + /* put the TZIC into the reset value with * all interrupts disabled */ - i = __raw_readl(tzic_base + TZIC_INTCNTL); - - __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); - __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); - __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); - - for (i = 0; i < 4; i++) - __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); - + i = __raw_readl(TZIC_INTCNTL); + + __raw_writel(0x80010001, TZIC_INTCNTL); + i = __raw_readl(TZIC_INTCNTL); + __raw_writel(0x1f, TZIC_PRIOMASK); + i = __raw_readl(TZIC_PRIOMASK); + __raw_writel(0x02, TZIC_SYNCCTRL); + i = __raw_readl(TZIC_SYNCCTRL); + for (i = 0; i < 4; i++) { + __raw_writel(0xFFFFFFFF, TZIC_INTSEC0 + i * 4); + } /* disable all interrupts */ - for (i = 0; i < 4; i++) - __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); + for (i = 0; i < 4; i++) { + __raw_writel(0xFFFFFFFF, TZIC_ENCLEAR0 + i * 4); + } /* all IRQ no FIQ Warning :: No selection */ - for (i = 0; i < MXC_INTERNAL_IRQS; i++) { + for (i = 0; i < TZIC_NUM_IRQS; i++) { set_irq_chip(i, &mxc_tzic_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } mxc_register_gpios(); - pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); + printk(KERN_INFO "MXC IRQ initialized\n"); } -/** - * tzic_enable_wake() - enable wakeup interrupt +/*! + * enable wakeup interrupt * - * @param is_idle 1 if called in idle loop (ENSET0 register); + * @param is_idle 1 if called in idle loop (enset registers); * 0 to be used when called from low power entry * @return 0 if successful; non-zero otherwise */ @@ -161,14 +166,20 @@ int tzic_enable_wake(int is_idle) { unsigned int i, v; - __raw_writel(1, tzic_base + TZIC_DSMINT); - if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) + __raw_writel(1, TZIC_DSMINT); + if (unlikely(__raw_readl(TZIC_DSMINT) == 0)) return -EAGAIN; + if (likely(is_idle)) { + for (i = 0; i < 4; i++) { + v = __raw_readl(TZIC_ENSET0 + i * 4); + __raw_writel(v, TZIC_WAKEUP0 + i * 4); + } + } else { for (i = 0; i < 4; i++) { - v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i]; - __raw_writel(v, TZIC_WAKEUP0(i)); + v = wakeup_intr[i]; + __raw_writel(v, TZIC_WAKEUP0 + i * 4); + } } - return 0; } diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c new file mode 100644 index 000000000000..69cbcfc01d6f --- /dev/null +++ b/arch/arm/plat-mxc/usb_common.c @@ -0,0 +1,922 @@ +/* + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + *@defgroup USB ARC OTG USB Driver + */ + +/*! + * @file usb_common.c + * + * @brief platform related part of usb driver. + * @ingroup USB + */ + +/*! + *Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_NUMBER_USB_TRANSCEIVER 6 +struct fsl_xcvr_ops *g_xc_ops[MXC_NUMBER_USB_TRANSCEIVER] = { NULL }; + +enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata) +{ + enum fsl_usb2_modes mode; + mode = FSL_USB_UNKNOWN; + + if (!strcmp("DR", pdata->name)) { + if ((UOG_USBMODE & 0x3) == 0x2) + mode = FSL_USB_DR_DEVICE; + else if ((UOG_USBMODE & 0x3) == 0x3) + mode = FSL_USB_DR_HOST; + } else if (!strcmp("Host 1", pdata->name)) + mode = FSL_USB_MPH_HOST1; + else if (!strcmp("Host 2", pdata->name)) + mode = FSL_USB_MPH_HOST2; + + if (mode == FSL_USB_UNKNOWN) + printk(KERN_ERR "unknow usb mode,name is %s\n", pdata->name); + return mode; +} + +static struct clk *usb_clk; +static struct clk *usb_ahb_clk; + +extern int gpio_usbotg_hs_active(void); +extern int gpio_usbotg_hs_inactive(void); + +/* + * make sure USB_CLK is running at 60 MHz +/- 1000 Hz + */ +static int fsl_check_usbclk(void) +{ + unsigned long freq; + + usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + if (clk_enable(usb_ahb_clk)) { + printk(KERN_ERR "clk_enable(usb_ahb_clk) failed\n"); + return -EINVAL; + } + clk_put(usb_ahb_clk); + + usb_clk = clk_get(NULL, "usb_clk"); + freq = clk_get_rate(usb_clk); + clk_put(usb_clk); + if ((freq < 59999000) || (freq > 60001000)) { + printk(KERN_ERR "USB_CLK=%lu, should be 60MHz\n", freq); + return -1; + } + + return 0; +} + +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops) +{ + int i; + + pr_debug("%s\n", __func__); + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] == NULL) { + g_xc_ops[i] = xcvr_ops; + return; + } + } + + pr_debug("Failed %s\n", __func__); +} +EXPORT_SYMBOL(fsl_usb_xcvr_register); + +void fsl_platform_set_test_mode (struct fsl_usb2_platform_data *pdata, enum usb_test_mode mode) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_test_mode) + pdata->xcvr_ops->set_test_mode((u32 *)(pdata->regs + ULPIVW_OFF), mode); +} +EXPORT_SYMBOL(fsl_platform_set_test_mode); + +void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops) +{ + int i; + + pr_debug("%s\n", __func__); + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] == xcvr_ops) { + g_xc_ops[i] = NULL; + return; + } + } + + pr_debug("Failed %s\n", __func__); +} +EXPORT_SYMBOL(fsl_usb_xcvr_unregister); + +static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name) +{ + int i; + + pr_debug("%s\n", __func__); + if (name == NULL) { + printk(KERN_ERR "get_xcvr(): No tranceiver name\n"); + return NULL; + } + + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (strcmp(g_xc_ops[i]->name, name) == 0) { + return g_xc_ops[i]; + } + } + pr_debug("Failed %s\n", __func__); + return NULL; +} + +/* The dmamask must be set for EHCI to work */ +static u64 ehci_dmamask = ~(u32) 0; + +/*! + * Register an instance of a USB host platform device. + * + * @param res: resource pointer + * @param n_res: number of resources + * @param config: config pointer + * + * @return newly-registered platform_device + * + * The USB controller supports 3 host interfaces, and the + * kernel can be configured to support some number of them. + * Each supported host interface is registered as an instance + * of the "fsl-ehci" device. Call this function multiple times + * to register each host interface. + */ +static int usb_mxc_instance_id; +__init struct platform_device *host_pdev_register(struct resource *res, int n_res, + struct fsl_usb2_platform_data *config) +{ + struct platform_device *pdev; + int rc; + + pr_debug("register host res=0x%p, size=%d\n", res, n_res); + + pdev = platform_device_register_simple("fsl-ehci", + usb_mxc_instance_id, res, n_res); + if (IS_ERR(pdev)) { + pr_debug("can't register %s Host, %ld\n", + config->name, PTR_ERR(pdev)); + return NULL; + } + + pdev->dev.coherent_dma_mask = 0xffffffff; + pdev->dev.dma_mask = &ehci_dmamask; + + /* + * platform_device_add_data() makes a copy of + * the platform_data passed in. That makes it + * impossible to share the same config struct for + * all OTG devices (host,gadget,otg). So, just + * set the platorm_data pointer ourselves. + */ + rc = platform_device_add_data(pdev, config, + sizeof(struct fsl_usb2_platform_data)); + if (rc) { + platform_device_unregister(pdev); + return NULL; + } + + printk(KERN_INFO "usb: %s host (%s) registered\n", config->name, + config->transceiver); + pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n", + pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data); + + usb_mxc_instance_id++; + + return pdev; +} + +static void usbh1_set_serial_xcvr(void) +{ + pr_debug("%s: \n", __func__); + USBCTRL &= ~(UCTRL_H1SIC_MASK | UCTRL_BPE); /* disable bypass mode */ + USBCTRL |= UCTRL_H1SIC_SU6 | /* single-ended / unidir. */ + UCTRL_H1WIE | UCTRL_H1DT | /* disable H1 TLL */ + UCTRL_H1PM; /* power mask */ +} + +static void usbh1_set_ulpi_xcvr(void) +{ + pr_debug("%s: \n", __func__); + + /* Stop then Reset */ + UH1_USBCMD &= ~UCMD_RUN_STOP; + while (UH1_USBCMD & UCMD_RUN_STOP) + ; + + UH1_USBCMD |= UCMD_RESET; + while (UH1_USBCMD & UCMD_RESET) + ; + + /* Select the clock from external PHY */ + USB_CTRL_1 |= USB_CTRL_UH1_EXT_CLK_EN; + + /* select ULPI PHY PTS=2 */ + UH1_PORTSC1 = (UH1_PORTSC1 & ~PORTSC_PTS_MASK) | PORTSC_PTS_ULPI; + + USBCTRL &= ~UCTRL_H1WIE; /* HOST1 wakeup intr disable */ + USBCTRL &= ~UCTRL_H1UIE; /* Host1 ULPI interrupt disable */ + USBCTRL |= UCTRL_H1PM; /* HOST1 power mask */ + USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; /* OC is not used */ + + /* Interrupt Threshold Control:Immediate (no threshold) */ + UH1_USBCMD &= UCMD_ITC_NO_THRESHOLD; + + UH1_USBCMD |= UCMD_RESET; /* reset the controller */ + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} + +static void usbh1_set_utmi_xcvr(void) +{ + u32 tmp; + + /* Stop then Reset */ + UH1_USBCMD &= ~UCMD_RUN_STOP; + while (UH1_USBCMD & UCMD_RUN_STOP) + ; + + UH1_USBCMD |= UCMD_RESET; + while ((UH1_USBCMD) & (UCMD_RESET)) + ; + + /* For OC and PWR, it is board level setting + * The default setting is for mx53 evk + */ + USBCTRL &= ~UCTRL_H1PM; /* Host1 Power Mask */ + USBCTRL &= ~UCTRL_H1WIE; /* Host1 Wakeup Intr Disable */ + USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; /* Over current disable */ + + if (cpu_is_mx50()) { + USBCTRL |= UCTRL_H1PM; /* Host1 Power Mask */ + USB_PHY_CTR_FUNC &= ~USB_UH1_OC_DIS; /* Over current enable */ + /* Over current polarity low active */ + USB_PHY_CTR_FUNC |= USB_UH1_OC_POL; + } + /* set UTMI xcvr */ + tmp = UH1_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_UTMI; + UH1_PORTSC1 = tmp; + + /* Set the PHY clock to 24MHz */ + USBH1_PHY_CTRL1 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; + USBH1_PHY_CTRL1 |= 0x01; + + /* Workaround an IC issue for ehci driver: + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTW with 0 + * means 8 bits tranceiver width, here change + * it back to be 16 bits and do PHY diable and + * then enable. + */ + UH1_PORTSC1 |= PORTSC_PTW; + + /* need to reset the controller here so that the ID pin + * is correctly detected. + */ + /* Stop then Reset */ + UH1_USBCMD &= ~UCMD_RUN_STOP; + while (UH1_USBCMD & UCMD_RUN_STOP) + ; + + UH1_USBCMD |= UCMD_RESET; + while ((UH1_USBCMD) & (UCMD_RESET)) + ; + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for UTMI tranceivers */ + clk_disable(usb_clk); +} + +static void usbh2_set_ulpi_xcvr(void) +{ + u32 tmp; + + pr_debug("%s\n", __func__); + + UH2_USBCMD &= ~UCMD_RUN_STOP; + while (UH2_USBCMD & UCMD_RUN_STOP) + ; + + UH2_USBCMD |= UCMD_RESET; + while (UH2_USBCMD & UCMD_RESET) + + USBCTRL_HOST2 &= ~(UCTRL_H2SIC_MASK | UCTRL_BPE); + USBCTRL_HOST2 &= ~UCTRL_H2WIE; /* wakeup intr enable */ + USBCTRL_HOST2 &= ~UCTRL_H2UIE; /* ULPI intr enable */ + USB_CTRL_1 |= USB_CTRL_UH2_EXT_CLK_EN; + if (cpu_is_mx53()) + USB_CTRL_1 |= USB_CTRL_UH2_CLK_FROM_ULPI_PHY; + if (cpu_is_mx51())/* not tested */ + USBCTRL_HOST2 |= (1 << 12); + /* must set ULPI phy before turning off clock */ + tmp = UH2_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_ULPI; + UH2_PORTSC1 = tmp; + if (cpu_is_mx53()) { + /* turn off the internal 60MHZ clk */ + USB_CLKONOFF_CTRL |= (1 << 21); + } + UH2_USBCMD |= UCMD_RESET; /* reset the controller */ + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} + +static void usbh2_set_serial_xcvr(void) +{ + pr_debug("%s: \n", __func__); + + /* Stop then Reset */ + UH2_USBCMD &= ~UCMD_RUN_STOP; + while (UH2_USBCMD & UCMD_RUN_STOP) + ; + + UH2_USBCMD |= UCMD_RESET; + while (UH2_USBCMD & UCMD_RESET) + ; + + USBCTRL &= ~(UCTRL_H2SIC_MASK); /* Disable bypass mode */ + USBCTRL &= ~(UCTRL_H2PM); /* Power Mask */ + USBCTRL &= ~UCTRL_H2OCPOL; /* OverCurrent Polarity is Low Active */ + USBCTRL &= ~UCTRL_H2WIE; /* Wakeup intr disable */ + USBCTRL |= UCTRL_IP_PUE_DOWN | /* ipp_pue_pulldwn_dpdm */ + UCTRL_USBTE | /* USBT is enabled */ + UCTRL_H2DT; /* Disable H2 TLL */ + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) { + /* Disable Host2 bus Lock for i.MX35 1.0 */ + USBCTRL |= UCTRL_H2LOCKD; + /* USBOTG_PWR low active */ + USBCTRL &= ~UCTRL_PP; + /* OverCurrent Polarity is Low Active */ + USBCTRL &= ~UCTRL_OCPOL; + } else if (cpu_is_mx35_rev(CHIP_REV_2_0) >= 1) { + /* i.MX35 2.0 OTG and Host2 have seperate OC/PWR polarity */ + USBCTRL &= ~UCTRL_H2PP; + USBCTRL &= ~UCTRL_H2OCPOL; + } else if (cpu_is_mx25()) { + /* + * USBH2_PWR and USBH2_OC are active high. + * Must force xcvr clock to "internal" so that + * we can write to PTS field after it's been + * cleared by ehci_turn_off_all_ports(). + */ + USBCTRL |= UCTRL_H2PP | UCTRL_H2OCPOL | UCTRL_XCSH2; + /* Disable Host2 bus Lock */ + USBCTRL |= UCTRL_H2LOCKD; + } + + USBCTRL &= ~(UCTRL_PP); + UH2_PORTSC1 = (UH2_PORTSC1 & (~PORTSC_PTS_MASK)) | PORTSC_PTS_SERIAL; + + if (UH2_HCSPARAMS & HCSPARAMS_PPC) + UH2_PORTSC1 |= PORTSC_PORT_POWER; + + /* Reset controller before set host mode */ + UH2_USBCMD |= UCMD_RESET; + while (UH2_USBCMD & UCMD_RESET) + ; + + msleep(100); +} + +/*! + * Register remote wakeup by this usb controller + * + * @param pdev: platform_device for this usb controller + * + * @return 0 or negative error code in case not supportted. + */ +static int usb_register_remote_wakeup(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct resource *res; + int irq; + + pr_debug("%s: pdev=0x%p \n", __func__, pdev); + if (!(pdata->wake_up_enable)) + return -ECANCELED; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + pdev->dev.power.can_wakeup = 1; + enable_irq_wake(irq); + + return 0; +} + +int fsl_usb_host_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *xops; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); + + xops = fsl_usb_get_xcvr(pdata->transceiver); + if (!xops) { + printk(KERN_ERR "%s transceiver ops missing\n", pdata->name); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + pdata->pdev = pdev; + + if (fsl_check_usbclk() != 0) + return -EINVAL; + + pr_debug("%s: grab pins\n", __func__); + if (pdata->gpio_usb_active && pdata->gpio_usb_active()) + return -EINVAL; + + if (clk_enable(usb_clk)) { + printk(KERN_ERR "clk_enable(usb_clk) failed\n"); + return -EINVAL; + } + + if (cpu_is_mx50()) + /* Turn on AHB CLK for H1*/ + USB_CLKONOFF_CTRL &= ~H1_AHBCLK_OFF; + + /* enable board power supply for xcvr */ + if (pdata->xcvr_pwr) { + if (pdata->xcvr_pwr->regu1) + regulator_enable(pdata->xcvr_pwr->regu1); + if (pdata->xcvr_pwr->regu2) + regulator_enable(pdata->xcvr_pwr->regu2); + } + + if (xops->init) + xops->init(xops); + + if (usb_register_remote_wakeup(pdev)) + pr_debug("%s port is not a wakeup source.\n", pdata->name); + + if (xops->xcvr_type == PORTSC_PTS_SERIAL) { + if (cpu_is_mx35()) { + usbh2_set_serial_xcvr(); + /* Close the internal 60Mhz */ + USBCTRL &= ~UCTRL_XCSH2; + } else if (cpu_is_mx25()) + usbh2_set_serial_xcvr(); + else + usbh1_set_serial_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_ULPI) { + if (!strcmp("Host 1", pdata->name)) + usbh1_set_ulpi_xcvr(); + if (!strcmp("Host 2", pdata->name)) + usbh2_set_ulpi_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_UTMI) { + usbh1_set_utmi_xcvr(); + } + + pr_debug("%s: %s success\n", __func__, pdata->name); + return 0; +} +EXPORT_SYMBOL(fsl_usb_host_init); + +void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata) +{ + pr_debug("%s\n", __func__); + + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdata->xcvr_ops); + + pdata->regs = NULL; + + if (pdata->gpio_usb_inactive) + pdata->gpio_usb_inactive(); + if (pdata->xcvr_type == PORTSC_PTS_SERIAL) { + /* Workaround an IC issue for ehci driver. + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTS with 0 + * means UTMI interface, so here force the Host2 + * port use the internal 60Mhz. + */ + if (cpu_is_mx35()) + USBCTRL |= UCTRL_XCSH2; + clk_disable(usb_clk); + } + + /* disable board power supply for xcvr */ + if (pdata->xcvr_pwr) { + if (pdata->xcvr_pwr->regu1) + regulator_disable(pdata->xcvr_pwr->regu1); + if (pdata->xcvr_pwr->regu2) + regulator_disable(pdata->xcvr_pwr->regu2); + } + + clk_disable(usb_ahb_clk); +} +EXPORT_SYMBOL(fsl_usb_host_uninit); + +static void otg_set_serial_xcvr(void) +{ + pr_debug("%s\n", __func__); +} + +void otg_set_serial_host(void) +{ + pr_debug("%s\n", __func__); + /* set USBCTRL for host operation + * disable: bypass mode, + * set: single-ended/unidir/6 wire, OTG wakeup intr enable, + * power mask + */ + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + +#if defined(CONFIG_MXC_USB_SB3) + USBCTRL |= UCTRL_OSIC_SB3 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_SU6) + USBCTRL |= UCTRL_OSIC_SU6 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_DB4) + USBCTRL |= UCTRL_OSIC_DB4 | UCTRL_OWIE | UCTRL_OPM; +#else + USBCTRL |= UCTRL_OSIC_DU6 | UCTRL_OWIE | UCTRL_OPM; +#endif + + USB_OTG_MIRROR = OTGM_VBUSVAL | OTGM_ASESVLD; /* 0xa */ +} +EXPORT_SYMBOL(otg_set_serial_host); + +void otg_set_serial_peripheral(void) +{ + /* set USBCTRL for device operation + * disable: bypass mode + * set: differential/unidir/6 wire, OTG wakeup intr enable, + * power mask + */ + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + +#if defined(CONFIG_MXC_USB_SB3) + USBCTRL |= UCTRL_OSIC_SB3 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_SU6) + USBCTRL |= UCTRL_OSIC_SU6 | UCTRL_OWIE | UCTRL_OPM; +#elif defined(CONFIG_MXC_USB_DB4) + USBCTRL |= UCTRL_OSIC_DB4 | UCTRL_OWIE | UCTRL_OPM; +#else + USBCTRL |= UCTRL_OSIC_DU6 | UCTRL_OWIE | UCTRL_OPM; +#endif + + USB_OTG_MIRROR = OTGM_VBUSVAL | OTGM_BSESVLD | OTGM_IDIDG; /* oxd */ +} +EXPORT_SYMBOL(otg_set_serial_peripheral); + +static void otg_set_ulpi_xcvr(void) +{ + u32 tmp; + + pr_debug("%s\n", __func__); + USBCTRL &= ~UCTRL_OSIC_MASK; +#if defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MX3) + USBCTRL &= ~UCTRL_BPE; +#endif + USBCTRL |= UCTRL_OUIE | /* ULPI intr enable */ + UCTRL_OWIE | /* OTG wakeup intr enable */ + UCTRL_OPM; /* power mask */ + + /* must set ULPI phy before turning off clock */ + tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_ULPI; + UOG_PORTSC1 = tmp; + + /* need to reset the controller here so that the ID pin + * is correctly detected. + */ + UOG_USBCMD |= UCMD_RESET; + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + /* Turn off the usbpll for ulpi tranceivers */ + clk_disable(usb_clk); +} + +int fsl_usb_xcvr_suspend(struct fsl_xcvr_ops *xcvr_ops) +{ + if (!machine_is_mx31_3ds()) + return -ECANCELED; + + if (xcvr_ops->xcvr_type == PORTSC_PTS_ULPI) { + if (fsl_check_usbclk() != 0) + return -EINVAL; + if (gpio_usbotg_hs_active()) + return -EINVAL; + clk_enable(usb_clk); + + otg_set_ulpi_xcvr(); + + if (xcvr_ops->suspend) + /* suspend transceiver */ + xcvr_ops->suspend(xcvr_ops); + + gpio_usbotg_hs_inactive(); + clk_disable(usb_clk); + } + return 0; +} +EXPORT_SYMBOL(fsl_usb_xcvr_suspend); + +static void otg_set_utmi_xcvr(void) +{ + u32 tmp; + + /* Stop then Reset */ + UOG_USBCMD &= ~UCMD_RUN_STOP; + while (UOG_USBCMD & UCMD_RUN_STOP) + ; + + UOG_USBCMD |= UCMD_RESET; + while ((UOG_USBCMD) & (UCMD_RESET)) + ; + + if (cpu_is_mx53()) + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; + + if (cpu_is_mx51()) { + if (machine_is_mx51_3ds()) { + /* OTG Polarity of Overcurrent is Low active */ + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL; + /* Enable OTG Overcurrent Event */ + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS; + } else { + /* BBG is not using OC */ + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; + } + } else if (cpu_is_mx25()) { + USBCTRL |= UCTRL_OCPOL; + USBCTRL &= ~UCTRL_PP; + } else if (cpu_is_mx50()) { + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; + } else { + /* USBOTG_PWR low active */ + USBCTRL &= ~UCTRL_PP; + /* OverCurrent Polarity is Low Active */ + USBCTRL &= ~UCTRL_OCPOL; + + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) + /* OTG Lock Disable */ + USBCTRL |= UCTRL_OLOCKD; + } + + if (cpu_is_mx51()) + USBCTRL &= ~UCTRL_OPM; /* OTG Power Mask */ + + USBCTRL &= ~UCTRL_OWIE; /* OTG Wakeup Intr Disable */ + + /* set UTMI xcvr */ + tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; + tmp |= PORTSC_PTS_UTMI; + UOG_PORTSC1 = tmp; + + if (cpu_is_mx51()) { + /* Set the PHY clock to 19.2MHz */ + USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; + USB_PHY_CTR_FUNC2 |= 0x01; + } else if (machine_is_mx37_3ds()) { + /* Reference voltage for HS disconnect envelope detector */ + /* adjust the Squelch level */ + USB_PHY_CTR_FUNC2 &= ~(USB_UTMI_PHYCTRL2_HSDEVSEL_MASK << + USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT); + } + + /* Workaround an IC issue for ehci driver: + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTW with 0 + * means 8 bits tranceiver width, here change + * it back to be 16 bits and do PHY diable and + * then enable. + */ + UOG_PORTSC1 |= PORTSC_PTW; + + if (cpu_is_mx35() || cpu_is_mx25()) { + /* Enable UTMI interface in PHY control Reg */ + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE; + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE; + } + + /* need to reset the controller here so that the ID pin + * is correctly detected. + */ + /* Stop then Reset */ + UOG_USBCMD &= ~UCMD_RUN_STOP; + while (UOG_USBCMD & UCMD_RUN_STOP) + ; + + UOG_USBCMD |= UCMD_RESET; + while ((UOG_USBCMD) & (UCMD_RESET)) + ; + + /* allow controller to reset, and leave time for + * the ULPI transceiver to reset too. + */ + msleep(100); + + if (cpu_is_mx37()) { + /* fix USB PHY Power Gating leakage issue for i.MX37 */ + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETON; + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETEN; + } + + /* Turn off the usbpll for UTMI tranceivers */ + clk_disable(usb_clk); +} + +static int mxc_otg_used; + +int usbotg_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *xops; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); + + xops = fsl_usb_get_xcvr(pdata->transceiver); + if (!xops) { + printk(KERN_ERR "DR transceiver ops missing\n"); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + pdata->pdev = pdev; + + if (fsl_check_usbclk() != 0) + return -EINVAL; + if (!mxc_otg_used) { + if (cpu_is_mx50()) + /* Turn on AHB CLK for OTG*/ + USB_CLKONOFF_CTRL &= ~OTG_AHBCLK_OFF; + + pr_debug("%s: grab pins\n", __func__); + if (pdata->gpio_usb_active && pdata->gpio_usb_active()) + return -EINVAL; + + if (clk_enable(usb_clk)) { + printk(KERN_ERR "clk_enable(usb_clk) failed\n"); + return -EINVAL; + } + + if (xops->init) + xops->init(xops); + + UOG_PORTSC1 = UOG_PORTSC1 & ~PORTSC_PHCD; + if (xops->xcvr_type == PORTSC_PTS_SERIAL) { + if (pdata->operating_mode == FSL_USB2_DR_HOST) { + otg_set_serial_host(); + /* need reset */ + UOG_USBCMD |= UCMD_RESET; + msleep(100); + } else if (pdata->operating_mode == FSL_USB2_DR_DEVICE) + otg_set_serial_peripheral(); + otg_set_serial_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_ULPI) { + otg_set_ulpi_xcvr(); + } else if (xops->xcvr_type == PORTSC_PTS_UTMI) { + otg_set_utmi_xcvr(); + } + } + + if (usb_register_remote_wakeup(pdev)) + pr_debug("DR is not a wakeup source.\n"); + + mxc_otg_used++; + pr_debug("%s: success\n", __func__); + return 0; +} +EXPORT_SYMBOL(usbotg_init); + +void usbotg_uninit(struct fsl_usb2_platform_data *pdata) +{ + pr_debug("%s\n", __func__); + + mxc_otg_used--; + if (!mxc_otg_used) { + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdata->xcvr_ops); + + pdata->regs = NULL; + + if (machine_is_mx31_3ds()) { + if (pdata->xcvr_ops && pdata->xcvr_ops->suspend) + pdata->xcvr_ops->suspend(pdata->xcvr_ops); + clk_disable(usb_clk); + } + msleep(1); + UOG_PORTSC1 = UOG_PORTSC1 | PORTSC_PHCD; + if (pdata->gpio_usb_inactive) + pdata->gpio_usb_inactive(); + if (pdata->xcvr_type == PORTSC_PTS_SERIAL) + clk_disable(usb_clk); + clk_disable(usb_ahb_clk); + } +} +EXPORT_SYMBOL(usbotg_uninit); + +/* + * This function is used to debounce the reading value for id/vbus at + * the register of otgsc + */ +void usb_debounce_id_vbus(void) +{ + mdelay(3); +} +EXPORT_SYMBOL(usb_debounce_id_vbus); + +int usb_host_wakeup_irq(struct device *wkup_dev) +{ + int wakeup_req = 0; + struct fsl_usb2_platform_data *pdata = wkup_dev->platform_data; + + if (!strcmp("Host 1", pdata->name)) { + wakeup_req = USBCTRL & UCTRL_H1WIR; + } else if (!strcmp("Host 2", pdata->name)) { + wakeup_req = USBCTRL_HOST2 & UCTRL_H2WIR; + } else if (!strcmp("DR", pdata->name)) { + wakeup_req = USBCTRL & UCTRL_OWIR; + /*if only host mode is enabled, the wakeup event + * must be host wakeup event */ +#ifdef CONFIG_USB_OTG + /* if ID change status, it is host wakeup event */ + if (wakeup_req && (UOG_OTGSC & OTGSC_IS_USB_ID)) + wakeup_req = 0; +#endif + } + + return wakeup_req; +} +EXPORT_SYMBOL(usb_host_wakeup_irq); + +int usb_event_is_otg_wakeup(void) +{ + int ret = (USBCTRL & UCTRL_OWIR) ? 1 : 0; + return ret; +} +EXPORT_SYMBOL(usb_event_is_otg_wakeup); + +void usb_host_set_wakeup(struct device *wkup_dev, bool para) +{ + struct fsl_usb2_platform_data *pdata = wkup_dev->platform_data; + if (pdata->wake_up_enable) + pdata->wake_up_enable(pdata, para); +} +EXPORT_SYMBOL(usb_host_set_wakeup); diff --git a/arch/arm/plat-mxc/usb_wakeup.c b/arch/arm/plat-mxc/usb_wakeup.c new file mode 100644 index 000000000000..1945f7a461f5 --- /dev/null +++ b/arch/arm/plat-mxc/usb_wakeup.c @@ -0,0 +1,220 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct wakeup_ctrl { + int wakeup_irq; + int usb_irq; + struct fsl_usb2_wakeup_platform_data *pdata; + struct task_struct *thread; + struct completion event; +}; +static struct wakeup_ctrl *g_ctrl; + +extern int usb_event_is_otg_wakeup(void); +extern void usb_debounce_id_vbus(void); + +static void wakeup_clk_gate(struct fsl_usb2_wakeup_platform_data *pdata, bool on) +{ + if (pdata->usb_clock_for_pm) + pdata->usb_clock_for_pm(on); +} + +static bool usb2_is_in_lowpower(struct wakeup_ctrl *ctrl) +{ + int i; + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + /* all the usb module related the wakeup is in lowpower mode */ + for (i = 0; i < 3; i++) { + if (pdata->usb_pdata[i]) { + if (pdata->usb_pdata[i]->phy_lowpower_suspend && !pdata->usb_pdata[i]->lowpower) + return false; + } + } + return true; +} + +static void delay_process_wakeup(struct wakeup_ctrl *ctrl) +{ + int i; + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + disable_irq_nosync(ctrl->wakeup_irq); + if ((ctrl->usb_irq > 0) && (ctrl->wakeup_irq != ctrl->usb_irq)) + disable_irq_nosync(ctrl->usb_irq); + + for (i = 0; i < 3; i++) { + if (pdata->usb_pdata[i]) { + pdata->usb_pdata[i]->irq_delay = 1; + } + } + pdata->usb_wakeup_is_pending = true; + complete(&ctrl->event); +} + +static irqreturn_t usb_wakeup_handler(int irq, void *_dev) +{ + struct wakeup_ctrl *ctrl = (struct wakeup_ctrl *)_dev; + irqreturn_t ret = IRQ_NONE; + + if (usb2_is_in_lowpower(ctrl)) { + printk(KERN_INFO "usb wakeup is here\n"); + delay_process_wakeup(ctrl); + ret = IRQ_HANDLED; + } + return ret; +} + +static enum usb_wakeup_event is_wakeup(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->is_wakeup_event) + return pdata->is_wakeup_event(pdata); + else + return WAKEUP_EVENT_INVALID; +} + +static void wakeup_event_handler(struct wakeup_ctrl *ctrl) +{ + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + int already_waked = 0; + enum usb_wakeup_event wakeup_evt; + int i; + + wakeup_clk_gate(ctrl->pdata, true); + + /* In order to get the real id/vbus value */ + if (usb_event_is_otg_wakeup()) + usb_debounce_id_vbus(); + + for (i = 0; i < 3; i++) { + struct fsl_usb2_platform_data *usb_pdata = pdata->usb_pdata[i]; + if (usb_pdata) { + usb_pdata->irq_delay = 0; + wakeup_evt = is_wakeup(usb_pdata); + if (wakeup_evt != WAKEUP_EVENT_INVALID) { + if (usb_pdata->usb_clock_for_pm) + usb_pdata->usb_clock_for_pm(true); + usb_pdata->lowpower = 0; + already_waked = 1; + if (usb_pdata->wakeup_handler) { + usb_pdata->wakeup_handler(usb_pdata); + } + } + } + } + /* If nothing to wakeup, clear wakeup event */ + if ((already_waked == 0) && pdata->usb_wakeup_exhandle) + pdata->usb_wakeup_exhandle(); + + wakeup_clk_gate(ctrl->pdata, false); + pdata->usb_wakeup_is_pending = false; + wake_up(&pdata->wq); +} + +static int wakeup_event_thread(void *param) +{ + struct wakeup_ctrl *ctrl = (struct wakeup_ctrl *)param; + struct sched_param sch_param = {.sched_priority = 1}; + + sched_setscheduler(current, SCHED_RR, &sch_param); + while (1) { + wait_for_completion_interruptible(&ctrl->event); + if (kthread_should_stop()) + break; + wakeup_event_handler(ctrl); + enable_irq(ctrl->wakeup_irq); + if ((ctrl->usb_irq > 0) && (ctrl->wakeup_irq != ctrl->usb_irq)) + enable_irq(ctrl->usb_irq); + } + return 0; +} + +static int wakeup_dev_probe(struct platform_device *pdev) +{ + struct fsl_usb2_wakeup_platform_data *pdata; + struct wakeup_ctrl *ctrl = NULL; + int status; + + printk(KERN_INFO "IMX usb wakeup probe\n"); + + if (!pdev || !pdev->dev.platform_data) + return -ENODEV; + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + pdata = pdev->dev.platform_data; + init_waitqueue_head(&pdata->wq); + pdata->usb_wakeup_is_pending = false; + + ctrl->pdata = pdata; + init_completion(&ctrl->event); + ctrl->wakeup_irq = platform_get_irq(pdev, 0); + status = request_irq(ctrl->wakeup_irq, usb_wakeup_handler, IRQF_SHARED, "usb_wakeup", (void *)ctrl); + if (status) + goto error1; + ctrl->usb_irq = platform_get_irq(pdev, 1); + + ctrl->thread = kthread_run(wakeup_event_thread, (void *)ctrl, "usb_wakeup thread"); + status = IS_ERR(ctrl->thread) ? -1 : 0; + if (status) + goto error2; + g_ctrl = ctrl; + printk(KERN_DEBUG "the wakeup pdata is 0x%p\n", pdata); + + return 0; +error2: + free_irq(ctrl->wakeup_irq, (void *)ctrl); +error1: + kfree(ctrl); + return status; +} + +static int wakeup_dev_exit(struct platform_device *pdev) +{ + if (g_ctrl->thread) { + complete(&g_ctrl->event); + kthread_stop(g_ctrl->thread); + } + free_irq(g_ctrl->wakeup_irq, (void *)g_ctrl); + kfree(g_ctrl); + return 0; +} +static struct platform_driver wakeup_d = { + .probe = wakeup_dev_probe, + .remove = wakeup_dev_exit, + .driver = { + .name = "usb_wakeup", + }, +}; + +static int __init wakeup_dev_init(void) +{ + return platform_driver_register(&wakeup_d); +} +static void __exit wakeup_dev_uninit(void) +{ + platform_driver_unregister(&wakeup_d); +} + +subsys_initcall(wakeup_dev_init); +module_exit(wakeup_dev_uninit); + diff --git a/arch/arm/plat-mxc/utmixc.c b/arch/arm/plat-mxc/utmixc.c new file mode 100644 index 000000000000..59207ab9ff67 --- /dev/null +++ b/arch/arm/plat-mxc/utmixc.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static struct regulator *usbotg_regux; + +static void usb_utmi_init(struct fsl_xcvr_ops *this) +{ +#if defined(CONFIG_MXC_PMIC_MC13892_MODULE) || defined(CONFIG_MXC_PMIC_MC13892) + if (machine_is_mx51_3ds()) { + unsigned int value; + + /* VUSBIN */ + pmic_read_reg(REG_USB1, &value, 0xffffff); + value |= 0x1; + value |= (0x1 << 3); + pmic_write_reg(REG_USB1, value, 0xffffff); + } +#endif +} + +static void usb_utmi_uninit(struct fsl_xcvr_ops *this) +{ +} + +/*! + * set vbus power + * + * @param view viewport register + * @param on power on or off + */ +static void set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on) +{ + struct device *dev = &pdata->pdev->dev; + + pr_debug("real %s(on=%d) pdata=0x%p\n", __func__, on, pdata); + if (machine_is_mx37_3ds()) { + if (on) { + if (!board_is_rev(BOARD_REV_2)) + usbotg_regux = regulator_get(dev, "DCDC2"); + else + usbotg_regux = regulator_get(dev, "SWBST"); + + regulator_enable(usbotg_regux); + } else { + regulator_disable(usbotg_regux); + regulator_put(usbotg_regux); + } + } + if (pdata && pdata->platform_driver_vbus) + pdata->platform_driver_vbus(on); +} + +static struct fsl_xcvr_ops utmi_ops = { + .name = "utmi", + .xcvr_type = PORTSC_PTS_UTMI, + .init = usb_utmi_init, + .uninit = usb_utmi_uninit, + .set_vbus_power = set_power, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init utmixc_init(void) +{ + fsl_usb_xcvr_register(&utmi_ops); + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit utmixc_exit(void) +{ + fsl_usb_xcvr_unregister(&utmi_ops); +} + +subsys_initcall(utmixc_init); +module_exit(utmixc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("utmi xcvr driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/zq_calib.c b/arch/arm/plat-mxc/zq_calib.c new file mode 100644 index 000000000000..8b1b741eb087 --- /dev/null +++ b/arch/arm/plat-mxc/zq_calib.c @@ -0,0 +1,436 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* 10 secs by default, users can change it via sys */ +static int interval = 10; + +static struct device *zq_calib_dev; + +static void mxc_zq_main(struct work_struct *dummy); + +/* Use workqueue */ +static struct workqueue_struct *zq_queue; +static DEFINE_SPINLOCK(zq_lock); +static DECLARE_DELAYED_WORK(zq_work, mxc_zq_main); + +extern void __iomem *databahn_base; + +#define DATABAHN_REG_ZQ_HW_CFG DATABAHN_CTL_REG73 +#define DATABAHN_REG_ZQ_SW_CFG1 DATABAHN_CTL_REG74 +#define DATABAHN_REG_ZQ_SW_CFG2 DATABAHN_CTL_REG75 +#define DATABAHN_REG_ZQ_STATUS DATABAHN_CTL_REG83 + +#define DDR_TYPE_LPDDR2 (0x5 << 8) +static inline bool is_lpddr2(void) +{ + u32 v; + v = __raw_readl(databahn_base); + + return (v & DDR_TYPE_LPDDR2) == DDR_TYPE_LPDDR2; +} + +/*! + * MXC ZQ interface - Compare PU vs the External Resistor (240/300 ohm) + * + * @param pu u32 + * @param pd u32 + * + * @return Return compare result. + */ +static u32 mxc_zq_pu_compare(u32 pu, u32 pd) +{ + u32 data; + + /* set PU+1 & PD+1 value + * when pu=0x1F, set (pu+1) = 0x1F + */ + data = ((pd + 1) << 24) | ((pu + 1) << 16); + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG1); + /* + * set PU & PD value + */ + data = (pd << 8) | pu; + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG2); + /* + * Enable the ZQ comparator, + * need 300ns to complete a ZQ comparison + */ + __raw_writel(1 << 16, databahn_base + DATABAHN_REG_ZQ_HW_CFG); + /* TODO: wait 300ns till comparator output stable */ + ndelay(300); + /* read status bit[0] */ + data = __raw_readl(databahn_base + DATABAHN_REG_ZQ_STATUS); + data &= 0x1; + /* Disable the ZQ comparator to save power */ + __raw_writel(0, databahn_base + DATABAHN_REG_ZQ_HW_CFG); + return data; +} + +/*! + * MXC ZQ interface - Compare PU vs PD + * + * @param pu u32 + * @param pd u32 + * + * @return Return compare result. + */ +static u32 mxc_zq_pd_compare(u32 pu, u32 pd) +{ + u32 data; + + /* set bit[4]=1, select PU/PD comparison */ + /* PD range: 0~0xF */ + /* when pd=0x0F, set (pd+1) = 0x0F */ + data = ((pd + 1) << 24) | ((pu + 1) << 16) | (1 << 4); + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG1); + data = (pd << 8) | pu; + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG2); + /* + * Enable the ZQ comparator, + * need 300ns to complete a ZQ comparison + */ + __raw_writel(1 << 16, databahn_base + DATABAHN_REG_ZQ_HW_CFG); + /* TODO: wait 300ns till comparator output stable */ + ndelay(300); + /* read status bit[0] */ + data = __raw_readl(databahn_base + DATABAHN_REG_ZQ_STATUS); + data &= 0x1; + /* Disable the ZQ comparator to save power */ + __raw_writel(0, databahn_base + DATABAHN_REG_ZQ_HW_CFG); + return data; +} + +/*! + * MXC ZQ interface - Do a full range search of PU to + * match the external resistor + * + * @param start u32 + * + * @return Return pu. + */ +static u32 mxc_zq_pu_calib(u32 start) +{ + u32 i; + u32 data; + u32 zq_pu_val = 0; + + /* + * Compare PU from 0 to 0x1F + * data is the result of the comparator + * the result sequence looks like: + * 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + * Take the First "1" the sequence for PU + */ + for (i = start; i < 32; ++i) { + data = mxc_zq_pu_compare(i, 0); + if (data) { + zq_pu_val = i; + break; + } + } + + return zq_pu_val; +} + +/*! + * MXC ZQ interface - Do a full range search of PD to match + * the PU get from za_pu_calib() + * + * @param start u32 + * @param pu u32 + * + * @return Return pd. + */ +static s32 mxc_zq_pd_calib(u32 start, u32 pu) +{ + u32 i; + u32 data; + u32 zq_pd_val = 0; + + /* + * Compare PD from 0 to 0x0F + * data is the result of the comparator + * the result sequence looks like: + * 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 + * Take the Last "1" in the sequence for PD + */ + for (i = start; i < 15; ++i) { + data = mxc_zq_pd_compare(pu, i); + if (!data && (i > 0)) { + zq_pd_val = i - 1; + break; + } + } + + return zq_pd_val; +} + +/*! + * MXC ZQ interface - Load the PU/PD value to the ZQ buffers by hardware + * + * @param pu u32 + * @param pd u32 + */ +static void mxc_zq_hw_load(u32 pu, u32 pd, u32 pu_pd_sel) +{ + u32 data; + u32 pu_plus_1, pd_plus_1; + + pu_plus_1 = (pu == 0x1F) ? 0x1F : pu + 1; + pd_plus_1 = (pd == 0x0F) ? 0x0F : pd + 1; + + /* + * The PU/PD values stored in register + * DATABAHN_REG_ZQ_SW_CFG1/2 would be loaded + */ + data = (pd << 8) | pu; + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG2); + + data = (pd_plus_1 << 24) | (pu_plus_1 << 16); /* load PD */ + if (pu_pd_sel) + data |= (1 << 4); /* load PU */ + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG1); + + /* + * bit[0]: enable hardware load + * bit[4]: trigger a hardware load. + * + * When the posedge of bit[4] detected, hardware trigger a load. + */ + __raw_writel(0x10011, databahn_base + DATABAHN_REG_ZQ_HW_CFG); + /* + * Clear the zq_hw_load bit for next loading + */ + __raw_writel(0x10001, databahn_base + DATABAHN_REG_ZQ_HW_CFG); + /* + * Delay at least 10us waiting an ddr auto-refresh occurs + * PU PD value are loaded on auto-refresh event + */ + udelay(10); + /* + * Clear the calibration_en (bit[16]) to save power consumption + */ + __raw_writel(0x1, databahn_base + DATABAHN_REG_ZQ_HW_CFG); +} + +/*! + * MXC ZQ interface - Load the PU/PD value to the ZQ buffers by software + * + * @param pu u32 + * @param pd u32 + */ + +static void mxc_zq_sw_load(u32 pu, u32 pd) +{ + u32 data; + + /* + * The PU/PD values stored in register + * DATABAHN_REG_ZQ_SW_CFG1/2 would be loaded. + * */ + data = ((pd + 1) << 24) | ((pu + 1) << 16); + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG1); + data = (pd << 8) | pu; + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG2); + + /* Loading PU value, set pu_pd_sel=0 */ + __raw_writel((0x3 << 20) | (1 << 16), + databahn_base + DATABAHN_REG_ZQ_HW_CFG); + __raw_writel(0x1 << 21, + databahn_base + DATABAHN_REG_ZQ_HW_CFG); + + /* Loading PD value, set pu_pd_sel=1 */ + data = ((pd + 1) << 24) | ((pu + 1) << 16) | (1 << 4); + __raw_writel(data, databahn_base + DATABAHN_REG_ZQ_SW_CFG1); + + /* + * bit[21]: select software load + * bit[20]: enable software load + */ + __raw_writel((0x3 << 20) | (1 << 16), + databahn_base + DATABAHN_REG_ZQ_HW_CFG); + /* clear for next load */ + __raw_writel(0x1 << 21, databahn_base + DATABAHN_REG_ZQ_HW_CFG); +} + +/* + * This function is for ZQ pu calibration + */ +static u32 pu_calib_based_on_pd(u32 start, u32 pd) +{ + u32 i; + u32 data; + u32 zq_pu_val = 0; + + /* + * compare PU from 0 to 0x1F + * data is the result of the comparator + * the result sequence looks like: + * 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + * Pleae take the First "1" in the sequence for PU + */ + for (i = start; i < 32; i++) { + data = mxc_zq_pd_compare(i, pd); + if (data) { + zq_pu_val = i; + break; + } + } + + return zq_pu_val; +} + +/*! + * MXC ZQ interface - PU/PD calib function + * This function Do a complete PU/PD calib and loading process. + */ +static void mxc_zq_main(struct work_struct *dummy) +{ + u32 pu, pd; + + spin_lock(&zq_lock); + /* Search pu value start from 0 */ + pu = mxc_zq_pu_calib(0); + /* Search pd value start from 0 */ + if (is_lpddr2()) { + pd = mxc_zq_pd_calib(0, pu) + 3; + pu = pu_calib_based_on_pd(0, pd); + } else + pd = mxc_zq_pd_calib(0, pu); + dev_dbg(zq_calib_dev, "za_calib: pu = %d, pd = %d\n", pu, pd); + mxc_zq_hw_load(pu, pd, 1); /* Load Pu */ + mxc_zq_hw_load(pu, pd, 0); /* Load Pd */ + /* or do software load alternatively */ + /* zq_sw_load(pu, pd); */ + spin_unlock(&zq_lock); + + queue_delayed_work(zq_queue, &zq_work, + msecs_to_jiffies(interval * 1000)); +} + +static ssize_t interval_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", interval); +} + +static ssize_t interval_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + interval = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(interval, 0644, interval_show, + interval_store); + +static int __devinit mxc_zq_calib_probe(struct platform_device *pdev) +{ + int err = 0; + + zq_calib_dev = &pdev->dev; + zq_queue = create_singlethread_workqueue("zq_calib");; + if (!zq_queue) + return -ENOMEM; + + err = device_create_file(&pdev->dev, &dev_attr_interval); + if (err) { + dev_err(&pdev->dev, + "Unable to create file from interval\n"); + destroy_workqueue(zq_queue); + return err; + } + + mxc_zq_main(NULL); + + return 0; +} + +static int __devexit mxc_zq_calib_remove(struct platform_device *pdev) +{ + cancel_delayed_work(&zq_work); + flush_workqueue(zq_queue); + destroy_workqueue(zq_queue); + device_remove_file(&pdev->dev, &dev_attr_interval); + return 0; +} + +#ifdef CONFIG_PM +static int zq_calib_suspend(struct platform_device *pdev, pm_message_t state) +{ + flush_delayed_work(&zq_work); + + return 0; +} + +static int zq_calib_resume(struct platform_device *pdev) +{ + mxc_zq_main(NULL); + + return 0; +} +#else +#define zq_calib_suspend NULL +#define zq_calib_resume NULL +#endif + +static struct platform_driver mxc_zq_calib_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mxc_zq_calib", + }, + .probe = mxc_zq_calib_probe, + .remove = __exit_p(mxc_zq_calib_remove), + .suspend = zq_calib_suspend, + .resume = zq_calib_resume, +}; + +static int __init mxc_zq_calib_init(void) +{ + return platform_driver_register(&mxc_zq_calib_driver); +} + +static void __exit mxc_zq_calib_exit(void) +{ + platform_driver_unregister(&mxc_zq_calib_driver); +} + +module_init(mxc_zq_calib_init); +module_exit(mxc_zq_calib_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC ZQ Calibration driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxs/Kconfig b/arch/arm/plat-mxs/Kconfig new file mode 100644 index 000000000000..831a24b53789 --- /dev/null +++ b/arch/arm/plat-mxs/Kconfig @@ -0,0 +1,179 @@ +if ARCH_MXS + +menu "Freescale i.MXS implementations" + +choice + prompt "Select i.MXS chip family" + +config ARCH_MX28 + bool "Freescale MX28" + select CPU_ARM926T + select FIQ + select ZONE_DMA + select MXS_ICOLL + select MXS_DMA_ENGINE + select MXS_AUART_DMA_SUPPORT + select ARCH_HAS_CPUFREQ + ---help--- + Support Freescale MX28 chips + +config ARCH_MX23 + bool "Freescale MX23" + select CPU_ARM926T + select FIQ + select ZONE_DMA + select MXS_ICOLL + select MXS_DMA_ENGINE + select MXS_AUART_DMA_SUPPORT + select ARCH_HAS_CPUFREQ + ---help--- + Support Freescale MX23 chips + +endchoice + +if ARCH_MX28 +source arch/arm/mach-mx28/Kconfig +endif + +if ARCH_MX23 +source arch/arm/mach-mx23/Kconfig +endif + +config DMA_ZONE_SIZE + int "DMA memory zone size" + range 0 32 + default 16 + help + This is the size in MB for the DMA zone. The DMA zone is used for + dedicated memory for large contiguous video buffers +endmenu + +config MXS_ICOLL + bool + +config MXS_EARLY_CONSOLE + bool "Enable console early" + default y + help + Enable console early for kernel debug. + +config MXS_DMA_ENGINE + bool "Enable DMA ENGINE support" + default y + help + Support DMA controller on AHB-APBH and AHB-APBX Bridge + +config MXS_LRADC + bool "Low Resolution ADC support" + default y + depends on ARCH_MXS + help + Enable LRADC support + +config MXS_PWM_CHANNELS + int + default 8 + help + The number of pwm channel on Freescale MXS platform. + +menu "Freescale Application UART:" + +config MXS_AUART_DMA_SUPPORT + bool + depends on MXS_DMA_ENGINE + default y + +config MXS_AUART_PORTS + int + default 5 + +config MXS_AUART0_DEVICE_ENABLE + bool "Application uart 0 enabled" + default y + help + Enable applicatoin uart 0 + +config MXS_AUART0_DMA_ENABLE + bool "Set application uart 0 to dma mode" + default n + depends on MXS_AUART_DMA_SUPPORT + help + Set application uart 0 to dma mode + +config MXS_AUART1_DEVICE_ENABLE + bool "Application uart 1 enabled" + default y + help + Enable applicatoin uart 1 + +config MXS_AUART1_DMA_ENABLE + bool "Set application uart 1 to dma mode" + default n + depends on MXS_AUART_DMA_SUPPORT + help + Set application uart 1 to dma mode + +config MXS_AUART2_DEVICE_ENABLE + bool "Application uart 2 enabled" + default y + help + Enable applicatoin uart 2 + +config MXS_AUART2_DMA_ENABLE + bool "Set application uart 2 to dma mode" + default n + depends on MXS_AUART_DMA_SUPPORT + help + Set application uart 2 to dma mode + +config MXS_AUART3_DEVICE_ENABLE + bool "Application uart 3 enabled" + default y + help + Enable applicatoin uart 3 + +config MXS_AUART3_DMA_ENABLE + bool "Set application uart 3 to dma mode" + default n + depends on MXS_AUART_DMA_SUPPORT + help + Set application uart 3 to dma mode + +config MXS_AUART4_DEVICE_ENABLE + bool "Application uart 4 enabled" + default y + help + Enable applicatoin uart 4 + +config MXS_AUART4_DMA_ENABLE + bool "Set application uart 4 to dma mode" + default n + depends on MXS_AUART_DMA_SUPPORT + help + Set application uart 4 to dma mode + +config MXS_RAM_FREQ_SCALING + bool "RAM frequency scaling support" + depends on ARCH_MXS + default y + +choice + prompt "Select MXS RAM chip" + depends on MXS_RAM_FREQ_SCALING + +config MXS_RAM_MDDR + bool "mDDR SDRAM" + depends on ARCH_MX23 +config MXS_RAM_DDR + bool "DDR SDRAM" + depends on ARCH_MX23 + +endchoice + +config IRAM_ALLOC + bool + default y + select GENERIC_ALLOCATOR +endmenu + +endif diff --git a/arch/arm/plat-mxs/Makefile b/arch/arm/plat-mxs/Makefile new file mode 100644 index 000000000000..b583737fe254 --- /dev/null +++ b/arch/arm/plat-mxs/Makefile @@ -0,0 +1,24 @@ +# +# Makefile for the linux kernel. +# +# Object file lists. +obj-y += core.o clock.o pinctrl.o device.o timer-nomatch.o usb_common.o usb_wakeup.o + +obj-$(CONFIG_MXS_TIMER_WITH_MACH) += timer-match.o +obj-$(CONFIG_IRAM_ALLOC) += iram.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o + +obj-$(CONFIG_MXS_UNIQUE_ID) += unique-id.o + +obj-$(CONFIG_MXS_ICOLL) += icoll.o + +obj-$(CONFIG_MXS_DMA_ENGINE) += dmaengine.o dma-apbh.o dma-apbx.o + +obj-$(CONFIG_USB_SUPPORT) += utmixc.o + +obj-$(CONFIG_MXS_LRADC) += lradc.o +# Power Management +obj-$(CONFIG_CPU_FREQ) += cpufreq.o + +# charging/current limitation testing + diff --git a/arch/arm/plat-mxs/clock.c b/arch/arm/plat-mxs/clock.c new file mode 100644 index 000000000000..1b98b1e51164 --- /dev/null +++ b/arch/arm/plat-mxs/clock.c @@ -0,0 +1,325 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern int cpufreq_trig_needed; +static bool (*mxs_enable_h_autoslow)(bool enable); +static void (*mxs_set_h_autoslow_flags)(u16 flags); + +static DEFINE_SPINLOCK(clockfw_lock); + +/* + *------------------------------------------------------------------------- + * Standard clock functions defined in include/linux/clk.h + *------------------------------------------------------------------------- + */ +int __clk_get(struct clk *clk) +{ + if (clk->ref < CLK_REF_LIMIT) + clk->ref += CLK_REF_UNIT; + return clk->ref < CLK_REF_LIMIT; +} + +void __clk_put(struct clk *clk) +{ + if (clk->ref & CLK_REF_LIMIT) + clk->ref -= CLK_REF_UNIT; +} + +static void default_clk_disable(struct clk *clk) +{ + if (clk->enable_reg) + __raw_writel(clk->enable_bits, clk->enable_reg + SET_REGISTER); +} + +static int default_clk_enable(struct clk *clk) +{ + if (clk->enable_reg) + __raw_writel(clk->enable_bits, clk->enable_reg + CLR_REGISTER); + return 0; +} + +static unsigned long default_get_rate(struct clk *clk) +{ + if (clk->parent && clk->parent->get_rate) + return clk->parent->get_rate(clk->parent); + return 0L; +} + +static void __clk_disable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk) || !clk->ref) + return; + + if ((--clk->ref) & CLK_EN_MASK) + return; + + if (clk->disable) + clk->disable(clk); + __clk_disable(clk->secondary); + __clk_disable(clk->parent); +} + +static int __clk_enable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if ((clk->ref++) & CLK_EN_MASK) + return 0; + if (clk->parent) + __clk_enable(clk->parent); + if (clk->secondary) + __clk_enable(clk->secondary); + if (clk->enable) + clk->enable(clk); + return 0; +} + +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret = 0; + int pre_usage; + + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + spin_lock_irqsave(&clockfw_lock, flags); + pre_usage = (clk->ref & CLK_EN_MASK); + + if (clk->set_sys_dependent_parent) + clk->set_sys_dependent_parent(clk); + + ret = __clk_enable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) + && (pre_usage == 0)) { + cpufreq_trig_needed = 1; + cpufreq_update_policy(0); + } + return ret; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (clk == NULL || IS_ERR(clk)) + return; + if (clk->flags & ALWAYS_ENABLED) + return; + spin_lock_irqsave(&clockfw_lock, flags); + __clk_disable(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) + && ((clk->ref & CLK_EN_MASK) == 0)) { + cpufreq_trig_needed = 1; + cpufreq_update_policy(0); + } +} +EXPORT_SYMBOL(clk_disable); + +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return 0; + + return clk->ref & CLK_EN_MASK; +} +EXPORT_SYMBOL(clk_get_usecount); + +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long flags, rate; + if (clk == NULL || IS_ERR(clk) || clk->get_rate == NULL) + return 0UL; + + spin_lock_irqsave(&clockfw_lock, flags); + rate = clk->get_rate(clk); + spin_unlock_irqrestore(&clockfw_lock, flags); + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || IS_ERR(clk) || !clk->round_rate) + return 0; + + if (clk->flags & RATE_FIXED) + return 0; + + if (clk->round_rate) + return clk->round_rate(clk, rate); + return 0; +} +EXPORT_SYMBOL(clk_round_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + int ret = -EINVAL; + + if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) + return ret; + + if (clk->flags & RATE_FIXED) + return ret; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = clk->set_rate(clk, rate); + spin_unlock_irqrestore(&clockfw_lock, flags); + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + unsigned long flags; + int ret = -EINVAL; + struct clk *prev_parent; + + if (clk == NULL || IS_ERR(clk) || parent == NULL || + IS_ERR(parent) || clk->set_parent == NULL || + parent->get_rate == NULL) + return ret; + + if (clk->ref & CLK_EN_MASK) + clk_enable(parent); + + spin_lock_irqsave(&clockfw_lock, flags); + prev_parent = clk->parent; + ret = clk->set_parent(clk, parent); + if (ret) { + spin_unlock_irqrestore(&clockfw_lock, flags); + if (clk->ref & CLK_EN_MASK) + clk_disable(parent); + return ret; + } + + clk->parent = parent; + + spin_unlock_irqrestore(&clockfw_lock, flags); + + if (clk->ref & CLK_EN_MASK) + clk_disable(prev_parent); + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + +struct clk *clk_get_parent(struct clk *clk) +{ + struct clk *ret = NULL; + + if (clk == NULL || IS_ERR(clk)) + return ret; + + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +int clk_register(struct clk_lookup *lookup) +{ + if (lookup == NULL || IS_ERR(lookup) || + lookup->clk == NULL || IS_ERR(lookup->clk)) + return -EINVAL; + + if (lookup->clk->ref & CLK_REF_LIMIT) + return -EEXIST; + + if (!(lookup->clk->enable)) + lookup->clk->enable = default_clk_enable; + if (!(lookup->clk->disable)) + lookup->clk->disable = default_clk_disable; + if (!(lookup->clk->get_rate)) + lookup->clk->get_rate = default_get_rate; + + clkdev_add(lookup); + + return 0; +} +EXPORT_SYMBOL(clk_register); + +void clk_unregister(struct clk_lookup *lookup) +{ + if (lookup == NULL || IS_ERR(lookup) || + lookup->clk == NULL || IS_ERR(lookup->clk)) + return; + + if (lookup->clk->ref & CLK_REF_LIMIT) + return; + + clkdev_drop(lookup); + if (lookup->clk->enable == default_clk_enable) + lookup->clk->enable = NULL; + if (lookup->clk->disable == default_clk_disable) + lookup->clk->disable = NULL; + if (lookup->clk->get_rate == default_get_rate) + lookup->clk->get_rate = NULL; +} +EXPORT_SYMBOL(clk_unregister); + +bool clk_enable_h_autoslow(bool enable) +{ + unsigned long flags; + bool ret = false; + + if (mxs_enable_h_autoslow == NULL) + return ret; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = mxs_enable_h_autoslow(enable); + spin_unlock_irqrestore(&clockfw_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_enable_h_autoslow); + +void clk_set_h_autoslow_flags(u16 mask) +{ + unsigned long flags; + + if (mxs_set_h_autoslow_flags == NULL) + return; + + spin_lock_irqsave(&clockfw_lock, flags); + mxs_set_h_autoslow_flags(mask); + spin_unlock_irqrestore(&clockfw_lock, flags); +} +EXPORT_SYMBOL(clk_set_h_autoslow_flags); + +void clk_en_public_h_asm_ctrl(bool (*enable_func)(bool), + void (*set_func)(u16)) +{ + mxs_enable_h_autoslow = enable_func; + mxs_set_h_autoslow_flags = set_func; +} +EXPORT_SYMBOL(clk_en_public_h_asm_ctrl); diff --git a/arch/arm/plat-mxs/core.c b/arch/arm/plat-mxs/core.c new file mode 100644 index 000000000000..b804a579397c --- /dev/null +++ b/arch/arm/plat-mxs/core.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include + +#include + +#include +#include + +void (*machine_arch_reset) (char mode, const char *cmd); + +void arch_idle(void) +{ + cpu_do_idle(); +} + +void arch_reset(char mode, const char *cmd) +{ + if (machine_arch_reset) + machine_arch_reset(mode, cmd); + else { + void *base = IO_ADDRESS(RTC_PHYS_ADDR); + + __raw_writel(1, base + HW_RTC_WATCHDOG); + __raw_writel(0x80000000, base + HW_RTC_PERSISTENT1_SET); + __raw_writel(BM_RTC_CTRL_WATCHDOGEN, base + HW_RTC_CTRL_SET); + } + cpu_reset(0); +} + +static int __mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + u32 c; + int timeout; + + /* the process of software reset of IP block is done + in several steps: + + - clear SFTRST and wait for block is enabled; + - clear clock gating (CLKGATE bit); + - set the SFTRST again and wait for block is in reset; + - clear SFTRST and wait for reset completion. + */ + c = __raw_readl(hwreg); + c &= ~(1 << 31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + + if (!just_enable) { + c = __raw_readl(hwreg); + c |= (1 << 31); /* now again set SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* poll until CLKGATE set */ + if (__raw_readl(hwreg) & (1 << 30)) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when resetting\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling " + "after reset\n", __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + } + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 30)) == 0) + break; + + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when unclockgating\n", + __func__, hwreg); + return -ETIME; + } + + return 0; +} + +int mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + int try = 10; + int r; + + while (try--) { + r = __mxs_reset_block(hwreg, just_enable); + if (!r) + break; + pr_debug("%s: try %d failed\n", __func__, 10 - try); + } + return r; +} diff --git a/arch/arm/plat-mxs/cpufreq.c b/arch/arm/plat-mxs/cpufreq.c new file mode 100644 index 000000000000..a188b21d9bf4 --- /dev/null +++ b/arch/arm/plat-mxs/cpufreq.c @@ -0,0 +1,527 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +static struct regulator *cpu_regulator; +static struct clk *cpu_clk; +static struct clk *ahb_clk; +static struct clk *x_clk; +static struct clk *emi_clk; +static struct regulator *vddd; +static struct regulator *vdddbo; +static struct regulator *vddio; +static struct regulator *vdda; +static struct cpufreq_frequency_table imx_freq_table[7]; +int cpu_freq_khz_min; +int cpu_freq_khz_max; +int cpufreq_trig_needed; +int cur_freq_table_size; +int lcd_on_freq_table_size; +int lcd_off_freq_table_size; +int high_freq_needed; + +extern char *ahb_clk_id; +extern struct profile profiles[OPERATION_WP_SUPPORTED]; +extern int low_freq_used(void); + +static int set_freq_table(struct cpufreq_policy *policy, int end_index) +{ + int ret = 0; + int i; + int zero_no = 0; + + for (i = 0; i < end_index; i++) { + if (profiles[i].cpu == 0) + zero_no++; + } + + end_index -= zero_no; + + cpu_freq_khz_min = profiles[0].cpu; + cpu_freq_khz_max = profiles[0].cpu; + for (i = 0; i < end_index; i++) { + imx_freq_table[end_index - 1 - i].index = end_index - i; + imx_freq_table[end_index - 1 - i].frequency = + profiles[i].cpu; + + if ((profiles[i].cpu) < cpu_freq_khz_min) + cpu_freq_khz_min = profiles[i].cpu; + + if ((profiles[i].cpu) > cpu_freq_khz_max) + cpu_freq_khz_max = profiles[i].cpu; + } + + imx_freq_table[i].index = 0; + imx_freq_table[i].frequency = CPUFREQ_TABLE_END; + + policy->cur = clk_get_rate(cpu_clk) / 1000; + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; + policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; + + /* Manual states, that PLL stabilizes in two CLK32 periods */ + policy->cpuinfo.transition_latency = 1000; + + ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); + + if (ret < 0) { + printk(KERN_ERR "%s: failed to register i.MXC CPUfreq\n", + __func__); + return ret; + } + + cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu); + + return ret; +} + +static int set_op(struct cpufreq_policy *policy, unsigned int target_freq) +{ + struct cpufreq_freqs freqs; + int ret = 0, i; + + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.cpu = 0; + +/* work around usb problem when in updater firmare mode*/ +#ifdef CONFIG_MXS_UTP + return 0; +#endif + for (i = cur_freq_table_size - 1; i > 0; i--) { + if (profiles[i].cpu <= target_freq && + target_freq < profiles[i - 1].cpu) { + freqs.new = profiles[i].cpu; + break; + } + + if (!vddd && profiles[i].cpu > freqs.old) { + /* can't safely set more than now */ + freqs.new = profiles[i + 1].cpu; + break; + } + } + + if (i == 0) + freqs.new = profiles[i].cpu; + + if ((freqs.old / 1000) == (freqs.new / 1000)) { + if (regulator_get_voltage(vddd) == profiles[i].vddd) + return 0; + } + + if (cpu_regulator && (freqs.old < freqs.new)) { + ret = regulator_set_current_limit(cpu_regulator, + profiles[i].cur, profiles[i].cur); + if (ret) + return ret; + } + + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + if (freqs.old > freqs.new) { + int ss = profiles[i].ss; + + /* change emi while cpu is fastest to minimize + * time spent changing emiclk + */ + clk_set_rate(emi_clk, (profiles[i].emi) * 1000); + clk_set_rate(cpu_clk, (profiles[i].cpu) * 1000); + clk_set_rate(ahb_clk, (profiles[i].ahb) * 1000); + /* x_clk order doesn't really matter */ + clk_set_rate(x_clk, (profiles[i].xbus) * 1000); + timing_ctrl_rams(ss); + + if (vddd && vdddbo && vddio && vdda) { + ret = regulator_set_voltage(vddd, + profiles[i].vddd, + profiles[i].vddd); + if (ret) + ret = regulator_set_voltage(vddd, + profiles[i].vddd, + profiles[i].vddd); + regulator_set_voltage(vdddbo, + profiles[i].vddd_bo, + profiles[i].vddd_bo); + + ret = regulator_set_voltage(vddio, + profiles[i].vddio, + profiles[i].vddio); + if (ret) + ret = regulator_set_voltage(vddio, + profiles[i].vddio, + profiles[i].vddio); + ret = regulator_set_voltage(vdda, + profiles[i].vdda, + profiles[i].vdda); + if (ret) + ret = regulator_set_voltage(vdda, + profiles[i].vdda, + profiles[i].vdda); + } + } else { + int ss = profiles[i].ss; + if (vddd && vdddbo && vddio && vdda) { + ret = regulator_set_voltage(vddd, + profiles[i].vddd, + profiles[i].vddd); + if (ret) + ret = regulator_set_voltage(vddd, + profiles[i].vddd, + profiles[i].vddd); + regulator_set_voltage(vdddbo, + profiles[i].vddd_bo, + profiles[i].vddd_bo); + ret = regulator_set_voltage(vddio, + profiles[i].vddio, + profiles[i].vddio); + if (ret) + ret = regulator_set_voltage(vddio, + profiles[i].vddio, + profiles[i].vddio); + ret = regulator_set_voltage(vdda, + profiles[i].vdda, + profiles[i].vdda); + if (ret) + ret = regulator_set_voltage(vdda, + profiles[i].vdda, + profiles[i].vdda); + } + /* x_clk order doesn't really matter */ + clk_set_rate(x_clk, (profiles[i].xbus) * 1000); + timing_ctrl_rams(ss); + clk_set_rate(cpu_clk, (profiles[i].cpu) * 1000); + clk_set_rate(ahb_clk, (profiles[i].ahb) * 1000); + clk_set_rate(emi_clk, (profiles[i].emi) * 1000); + } + + if (is_hclk_autoslow_ok()) + clk_set_h_autoslow_flags(profiles[i].h_autoslow_flags); + else + clk_enable_h_autoslow(false); + + if (high_freq_needed == 0) + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + if (cpu_regulator && (freqs.old > freqs.new)) /* will not fail */ + regulator_set_current_limit(cpu_regulator, + profiles[i].cur, + profiles[i].cur); + + if (high_freq_needed == 1) { + high_freq_needed = 0; + cur_freq_table_size = lcd_on_freq_table_size; + set_freq_table(policy, cur_freq_table_size); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + } + + return ret; +} + +static int calc_frequency_khz(int target, unsigned int relation) +{ + int i; + + if (target * 1000 == clk_get_rate(cpu_clk)) + return target; + + if (relation == CPUFREQ_RELATION_H) { + for (i = cur_freq_table_size - 1; i >= 0; i--) { + if (imx_freq_table[i].frequency <= target) + return imx_freq_table[i].frequency; + } + } else if (relation == CPUFREQ_RELATION_L) { + for (i = 0; i < cur_freq_table_size; i++) { + if (imx_freq_table[i].frequency >= target) + return imx_freq_table[i].frequency; + } +} + + printk(KERN_ERR "Error: No valid cpufreq relation\n"); + return cpu_freq_khz_max; +} + +static int mxs_target(struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + int freq_KHz; + struct cpufreq_freqs freqs; + int low_freq_bus_ready = 0; + + if (cpufreq_trig_needed == 1) { + /* Set the current working point. */ + cpufreq_trig_needed = 0; + target_freq = clk_get_rate(cpu_clk) / 1000; + low_freq_bus_ready = low_freq_used(); + + if ((target_freq < LCD_ON_CPU_FREQ_KHZ) && + (low_freq_bus_ready == 0)) { + high_freq_needed = 1; + target_freq = LCD_ON_CPU_FREQ_KHZ; + goto change_freq; + } + + target_freq = clk_get_rate(cpu_clk) / 1000; + freq_KHz = calc_frequency_khz(target_freq, relation); + + freqs.old = target_freq; + freqs.new = freq_KHz; + freqs.cpu = 0; + freqs.flags = 0; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + low_freq_bus_ready = low_freq_used(); + if (low_freq_bus_ready) { + int i; + cur_freq_table_size = lcd_off_freq_table_size; + /* find current table index to get + * hbus autoslow flags and enable hbus autoslow. + */ + for (i = cur_freq_table_size - 1; i > 0; i--) { + if (profiles[i].cpu <= target_freq && + target_freq < profiles[i - 1].cpu) { + clk_set_h_autoslow_flags( + profiles[i].h_autoslow_flags); + break; + } + } + } else { + cur_freq_table_size = lcd_on_freq_table_size; + clk_enable_h_autoslow(false); + } + + set_freq_table(policy, cur_freq_table_size); + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + return 0; +} + + /* + * Some governors do not respects CPU and policy lower limits + * which leads to bad things (division by zero etc), ensure + * that such things do not happen. + */ +change_freq: if (target_freq < policy->cpuinfo.min_freq) + target_freq = policy->cpuinfo.min_freq; + + if (target_freq < policy->min) + target_freq = policy->min; + + freq_KHz = calc_frequency_khz(target_freq, relation); + return set_op(policy, freq_KHz); + } + +static unsigned int mxs_getspeed(unsigned int cpu) +{ + if (cpu) + return 0; + + return clk_get_rate(cpu_clk) / 1000; +} + + +static int mxs_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, imx_freq_table); +} + +static int __init mxs_cpu_init(struct cpufreq_policy *policy) +{ + int ret = 0; + int i; + + cpu_clk = clk_get(NULL, "cpu"); + if (IS_ERR(cpu_clk)) { + ret = PTR_ERR(cpu_clk); + goto out_cpu; + } + + ahb_clk = clk_get(NULL, "h"); + if (IS_ERR(ahb_clk)) { + ret = PTR_ERR(ahb_clk); + goto out_ahb; + } + + x_clk = clk_get(NULL, "x"); + if (IS_ERR(ahb_clk)) { + ret = PTR_ERR(x_clk); + goto out_x; + } + + emi_clk = clk_get(NULL, "emi"); + if (IS_ERR(emi_clk)) { + ret = PTR_ERR(emi_clk); + goto out_emi; + } + + if (policy->cpu != 0) + return -EINVAL; + + cpu_regulator = regulator_get(NULL, "cpufreq-1"); + if (IS_ERR(cpu_regulator)) { + printk(KERN_ERR "%s: failed to get CPU regulator\n", __func__); + cpu_regulator = NULL; + ret = PTR_ERR(cpu_regulator); + goto out_cur; + } + + vddd = regulator_get(NULL, "vddd"); + if (IS_ERR(vddd)) { + printk(KERN_ERR "%s: failed to get vddd regulator\n", __func__); + vddd = NULL; + ret = PTR_ERR(vddd); + goto out_cur; + } + + vdddbo = regulator_get(NULL, "vddd_bo"); + if (IS_ERR(vdddbo)) { + vdddbo = NULL; + pr_warning("unable to get vdddbo"); + ret = PTR_ERR(vdddbo); + goto out_cur; + } + + vddio = regulator_get(NULL, "vddio"); + if (IS_ERR(vddio)) { + vddio = NULL; + pr_warning("unable to get vddio"); + ret = PTR_ERR(vddio); + goto out_cur; + } + + vdda = regulator_get(NULL, "vdda"); + if (IS_ERR(vdda)) { + vdda = NULL; + pr_warning("unable to get vdda"); + ret = PTR_ERR(vdda); + goto out_cur; + } + + for (i = 0; i < ARRAY_SIZE(profiles); i++) { + if ((profiles[i].cpu) == LCD_ON_CPU_FREQ_KHZ) { + lcd_on_freq_table_size = i + 1; + break; + } + } + + if (i == ARRAY_SIZE(profiles)) { + pr_warning("unable to find frequency for LCD on"); + printk(KERN_ERR "lcd_on_freq_table_size=%d\n", + lcd_on_freq_table_size); + goto out_cur; + } + + for (i = 0; i < ARRAY_SIZE(profiles); i++) { + if ((profiles[i].cpu) == 0) { + lcd_off_freq_table_size = i; + break; + } + } + + if (i == ARRAY_SIZE(profiles)) + lcd_off_freq_table_size = i; + + /* Set the current working point. */ + set_freq_table(policy, lcd_on_freq_table_size); + cpufreq_trig_needed = 0; + high_freq_needed = 0; + cur_freq_table_size = lcd_on_freq_table_size; + + printk(KERN_INFO "%s: cpufreq init finished\n", __func__); + return 0; +out_cur: + if (cpu_regulator) + regulator_put(cpu_regulator); + if (vddd) + regulator_put(vddd); + if (vddio) + regulator_put(vddio); + if (vdda) + regulator_put(vdda); + + clk_put(emi_clk); +out_emi: + clk_put(x_clk); +out_x: + clk_put(ahb_clk); +out_ahb: + clk_put(cpu_clk); +out_cpu: + return ret; +} + +static int mxs_cpu_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + + /* Reset CPU to 392MHz */ + set_op(policy, profiles[1].cpu); + + clk_put(cpu_clk); + regulator_put(cpu_regulator); + return 0; +} + +static struct cpufreq_driver mxs_driver = { + .flags = CPUFREQ_STICKY, + .verify = mxs_verify_speed, + .target = mxs_target, + .get = mxs_getspeed, + .init = mxs_cpu_init, + .exit = mxs_cpu_exit, + .name = "mxs", +}; + +static int __devinit mxs_cpufreq_init(void) +{ + return cpufreq_register_driver(&mxs_driver); +} + +static void mxs_cpufreq_exit(void) +{ + cpufreq_unregister_driver(&mxs_driver); +} + +module_init(mxs_cpufreq_init); +module_exit(mxs_cpufreq_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("CPUfreq driver for i.MX"); +MODULE_LICENSE("GPL"); + diff --git a/arch/arm/plat-mxs/device.c b/arch/arm/plat-mxs/device.c new file mode 100644 index 000000000000..87a38fa8c3d8 --- /dev/null +++ b/arch/arm/plat-mxs/device.c @@ -0,0 +1,831 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static int mxs_device_num; +static int mxs_device_done; +static DEFINE_MUTEX(device_mutex); +static struct list_head mxs_device_level[] = { + LIST_HEAD_INIT(mxs_device_level[0]), + LIST_HEAD_INIT(mxs_device_level[1]), + LIST_HEAD_INIT(mxs_device_level[2]), + LIST_HEAD_INIT(mxs_device_level[3]), +}; + +static u64 common_dmamask = DMA_BIT_MASK(32); + +void mxs_nop_release(struct device *dev) +{ + /* Nothing */ +} + +int mxs_add_devices(struct platform_device *pdev, int num, int level) +{ + int i, ret = -ENOMEM; + if (pdev == NULL || IS_ERR(pdev) || num <= 0) + return -EINVAL; + + if (level < 0) + level = 0; + else if (level >= ARRAY_SIZE(mxs_device_level)) + level = ARRAY_SIZE(mxs_device_level) - 1; + + mutex_lock(&device_mutex); + if (mxs_device_done) { + ret = 0; + for (i = 0; i < num; i++) + ret |= platform_device_register(pdev + i); + goto out; + } + + if ((mxs_device_num + num) > MXS_MAX_DEVICES) + goto out; + mxs_device_num += num; + for (i = 0; i < num; i++) + list_add_tail(&pdev[i].dev.devres_head, + &mxs_device_level[level]); + ret = 0; +out: + mutex_unlock(&device_mutex); + return ret; +} + +int mxs_add_device(struct platform_device *pdev, int level) +{ + return mxs_add_devices(pdev, 1, level); +} + +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) +static struct platform_device mxs_duart = { + .name = "mxs-duart", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_MXS_DMA_ENGINE) +static struct platform_device mxs_dma[] = { + { + .name = "mxs-dma-apbh", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, + { + .name = "mxs-dma-apbx", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) +static struct platform_device mxs_i2c[] = { +#if defined(CONFIG_I2C_MXS_SELECT0) + { + .name = "mxs-i2c", + .id = 0, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .release = mxs_nop_release, + }, + }, +#endif +#if defined(CONFIG_I2C_MXS_SELECT1) + { + .name = "mxs-i2c", + .id = 1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .release = mxs_nop_release, + }, + }, +#endif +}; +#endif + +#if defined(CONFIG_MTD_NAND_GPMI_NFC) || \ + defined(CONFIG_MTD_NAND_GPMI_NFC_MODULE) +static struct platform_device gpmi_nfc = { + .name = GPMI_NFC_DRIVER_NAME, + .id = 0, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_MMC_MXS) || \ + defined(CONFIG_MMC_MXS_MODULE) +static struct platform_device mxs_mmc[] = { + { + .name = "mxs-mmc", + .id = 0, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .release = mxs_nop_release, + }, + }, + { + .name = "mxs-mmc", + .id = 1, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct platform_device mxs_spi[] = { + { + .name = "mxs-spi", + .id = 0, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE) +static struct platform_device mxs_wdt = { + .name = "mxs-wdt", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_FEC) || \ + defined(CONFIG_FEC_MODULE) +static struct platform_device mxs_fec[] = { + { + .name = "fec", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, + { + .name = "fec", + .id = 1, + .dev = { + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_FEC_L2SWITCH) +static struct platform_device mxs_l2switch[] = { + { + .name = "mxs-l2switch", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) +static struct platform_device mxs_fb = { + .name = "mxs-fb", + .id = 0, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_BACKLIGHT_MXS) || \ + defined(CONFIG_BACKLIGHT_MXS_MODULE) +struct platform_device mxs_bl = { + .name = "mxs-bl", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_VIDEO_MXS_PXP) || \ + defined(CONFIG_VIDEO_MXS_PXP_MODULE) +static struct platform_device mxs_pxp = { + .name = "mxs-pxp", + .id = 0, + .dev = { + .release = mxs_nop_release, + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#endif + +#if defined(CONFIG_RTC_DRV_MXS) || defined(CONFIG_RTC_DRV_MXS_MODULE) +static struct platform_device mxs_rtc = { + .name = "mxs-rtc", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#ifdef CONFIG_MXS_LRADC +static struct platform_device mxs_lradc = { + .name = "mxs-lradc", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_KEYBOARD_MXS) || defined(CONFIG_KEYBOARD_MXS_MODULE) +static struct platform_device mxs_kbd = { + .name = "mxs-kbd", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_TOUCHSCREEN_MXS) || defined(CONFIG_TOUCHSCREEN_MXS_MODULE) +static struct platform_device mxs_ts = { + .name = "mxs-ts", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_SERIAL_MXS_AUART) || defined(CONFIG_SERIAL_MXS_AUART_MODULE) +static struct platform_device mxs_auart[] = { +#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE + { + .name = "mxs-auart", + .id = 0, + .dev = { + .release = mxs_nop_release, + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, +#endif +#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE + { + .name = "mxs-auart", + .id = 1, + .dev = { + .release = mxs_nop_release, + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, +#endif +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE + { + .name = "mxs-auart", + .id = 2, + .dev = { + .release = mxs_nop_release, + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, +#endif +#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE + { + .name = "mxs-auart", + .id = 3, + .dev = { + .release = mxs_nop_release, + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, +#endif +#ifdef CONFIG_MXS_AUART4_DEVICE_ENABLE + { + .name = "mxs-auart", + .id = 4, + .dev = { + .release = mxs_nop_release, + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, +#endif +}; +#endif + +#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE) +static struct platform_device mxs_led = { + .name = "mxs-leds", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_CAN_FLEXCAN) || \ + defined(CONFIG_CAN_FLEXCAN_MODULE) +static struct platform_device mxs_flexcan[] = { + { + .name = "FlexCAN", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, + { + .name = "FlexCAN", + .id = 1, + .dev = { + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_CRYPTO_DEV_DCP) +static struct platform_device mxs_dcp = { + .name = "dcp", + .id = 0, + .dev = { + .release = mxs_nop_release, + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#endif + +#if defined(CONFIG_BATTERY_MXS) +static struct platform_device mxs_battery = { + .name = "mxs-battery", + .id = 0, + .dev = { + .release = mxs_nop_release, + } , +}; +#endif + +#if defined(CONFIG_SND_SOC_SGTL5000) || \ + defined(CONFIG_SND_SOC_SGTL5000_MODULE) +static struct platform_device mxs_sgtl5000[] = { + { + .name = "mxs-sgtl5000", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_MXS_VIIM) || defined(CONFIG_MXS_VIIM_MODULE) +struct platform_device mxs_viim = { + .name = "mxs_viim", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) +static struct platform_device mxs_spdif[] = { + { + .name = "mxs-spdif", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_SND_MXS_SOC_ADC) || \ + defined(CONFIG_SND_MXS_SOC_ADC_MODULE) +static struct platform_device mxs_adc = { + .name = "mxs-adc-audio", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +static struct platform_device busfreq_device = { + .name = "busfreq", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; + +#ifdef CONFIG_MXS_PERSISTENT +static struct platform_device mxs_persistent = { + .name = "mxs-persistent", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#ifdef CONFIG_MXS_PERFMON +static struct platform_device mxs_perfmon = { + .name = "mxs-perfmon", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +#ifdef CONFIG_FSL_OTP +static struct platform_device otp_device = { + .name = "ocotp", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + +static inline void mxs_init_busfreq(void) +{ + (void)platform_device_register(&busfreq_device); +} + +static struct mxs_dev_lookup dev_lookup[] = { +#if defined(CONFIG_SERIAL_MXS_DUART) || \ + defined(CONFIG_SERIAL_MXS_DUART_MODULE) + { + .name = "mxs-duart", + .size = 1, + .pdev = &mxs_duart, + }, +#endif +#if defined(CONFIG_MXS_DMA_ENGINE) + { + .name = "mxs-dma", + .size = ARRAY_SIZE(mxs_dma), + .pdev = mxs_dma, + }, +#endif + +#if defined(CONFIG_I2C_MXS) || \ + defined(CONFIG_I2C_MXS_MODULE) + { + .name = "mxs-i2c", + .size = ARRAY_SIZE(mxs_i2c), + .pdev = mxs_i2c, + }, +#endif + +#if defined(CONFIG_MTD_NAND_GPMI_NFC) || \ + defined(CONFIG_MTD_NAND_GPMI_NFC_MODULE) + { + .name = GPMI_NFC_DRIVER_NAME, + .size = 1, + .pdev = &gpmi_nfc, + }, +#endif + +#if defined(CONFIG_MMC_MXS) || \ + defined(CONFIG_MMC_MXS_MODULE) + { + .name = "mxs-mmc", + .size = ARRAY_SIZE(mxs_mmc), + .pdev = mxs_mmc, + }, +#endif + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) + { + .name = "mxs-spi", + .size = ARRAY_SIZE(mxs_spi), + .pdev = mxs_spi, + }, +#endif + +#if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE) + { + .name = "mxs-wdt", + .size = 1, + .pdev = &mxs_wdt, + }, +#endif + +#if defined(CONFIG_RTC_DRV_MXS) || defined(CONFIG_RTC_DRV_MXS_MODULE) + { + .name = "mxs-rtc", + .size = 1, + .pdev = &mxs_rtc, + }, +#endif + +#if defined(CONFIG_MXS_PERSISTENT) + { + .name = "mxs-persistent", + .size = 1, + .pdev = &mxs_persistent, + }, +#endif + +#if defined(CONFIG_MXS_PERFMON) + { + .name = "mxs-perfmon", + .size = 1, + .pdev = &mxs_perfmon, + }, +#endif + +#if defined(CONFIG_FSL_OTP) + { + .name = "ocotp", + .size = 1, + .pdev = &otp_device, + }, +#endif + +#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) + { + .name = "mxs-fb", + .size = 1, + .pdev = &mxs_fb, + }, +#endif +#if defined(CONFIG_BACKLIGHT_MXS) || \ + defined(CONFIG_BACKLIGHT_MXS_MODULE) + { + .name = "mxs-bl", + .size = 1, + .pdev = &mxs_bl, + }, +#endif + +#if defined(CONFIG_VIDEO_MXS_PXP) || \ + defined(CONFIG_VIDEO_MXS_PXP_MODULE) + { + .name = "mxs-pxp", + .size = 1, + .pdev = &mxs_pxp, + }, +#endif + +#if defined(CONFIG_MXS_VIIM) || defined(CONFIG_MXS_VIIM_MODULE) + { + .name = "mxs_viim", + .size = 1, + .pdev = &mxs_viim, + }, +#endif + +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) + { + .name = "mxs-fec", + .size = ARRAY_SIZE(mxs_fec), + .pdev = mxs_fec, + }, +#endif + +#if defined(CONFIG_FEC_L2SWITCH) + { + .name = "mxs-l2switch", + .size = ARRAY_SIZE(mxs_l2switch), + .pdev = mxs_l2switch, + }, +#endif + +#ifdef CONFIG_MXS_LRADC + { + .name = "mxs-lradc", + .size = 1, + .pdev = &mxs_lradc, + }, +#endif + +#if defined(CONFIG_KEYBOARD_MXS) || defined(CONFIG_KEYBOARD_MXS_MODULE) + { + .name = "mxs-kbd", + .size = 1, + .pdev = &mxs_kbd, + }, +#endif + +#if defined(CONFIG_TOUCHSCREEN_MXS) || defined(CONFIG_TOUCHSCREEN_MXS_MODULE) + { + .name = "mxs-ts", + .size = 1, + .pdev = &mxs_ts, + }, +#endif + +#if defined(CONFIG_SERIAL_MXS_AUART) || defined(CONFIG_SERIAL_MXS_AUART_MODULE) + { + .name = "mxs-auart", + .size = ARRAY_SIZE(mxs_auart), + .pdev = mxs_auart, + }, +#endif + +#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE) + { + .name = "mxs-leds", + .size = 1, + .pdev = &mxs_led, + }, +#endif + +#if defined(CONFIG_CAN_FLEXCAN) || \ + defined(CONFIG_CAN_FLEXCAN_MODULE) + { + .name = "FlexCAN", + .size = ARRAY_SIZE(mxs_flexcan), + .pdev = mxs_flexcan, + }, +#endif + +#if defined(CONFIG_CRYPTO_DEV_DCP) + { + .name = "dcp", + .size = 1, + .pdev = &mxs_dcp, + }, +#endif + +#if defined(CONFIG_BATTERY_MXS) + { + .name = "mxs-battery", + .size = 1, + .pdev = &mxs_battery, + }, +#endif + +#if defined(CONFIG_SND_SOC_SGTL5000) || \ + defined(CONFIG_SND_SOC_SGTL5000_MODULE) + { + .name = "mxs-sgtl5000", + .size = ARRAY_SIZE(mxs_sgtl5000), + .pdev = mxs_sgtl5000, + }, +#endif + +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) + { + .name = "mxs-spdif", + .size = ARRAY_SIZE(mxs_spdif), + .pdev = mxs_spdif, + }, +#endif + +#if defined(CONFIG_SND_MXS_SOC_ADC) || \ + defined(CONFIG_SND_MXS_SOC_ADC_MODULE) + { + .name = "mxs-adc", + .size = 1, + .pdev = &mxs_adc, + }, +#endif + +}; + +struct platform_device *mxs_get_device(char *name, int id) +{ + int i, j; + struct mxs_dev_lookup *lookup; + struct platform_device *pdev = (struct platform_device *)-ENODEV; + if (name == NULL || id < 0 || IS_ERR(name)) + return (struct platform_device *)-EINVAL; + + mutex_lock(&device_mutex); + for (i = 0; i < ARRAY_SIZE(dev_lookup); i++) { + lookup = &dev_lookup[i]; + if (!strcmp(name, lookup->name)) { + if (test_bit(0, &lookup->lock)) { + pdev = (struct platform_device *)-EBUSY; + break; + } + + if (id >= lookup->size) + break; + for (j = 0; j < lookup->size; j++) { + if (id == (lookup->pdev[j]).id) { + pdev = &lookup->pdev[j]; + break; + } + } + break; + } + + } + mutex_unlock(&device_mutex); + return pdev; +} + +struct mxs_dev_lookup *mxs_get_devices(char *name) +{ + int i; + struct mxs_dev_lookup *lookup; + if (name == NULL || IS_ERR(name)) + return (struct mxs_dev_lookup *)-EINVAL; + + mutex_lock(&device_mutex); + for (i = 0; i < ARRAY_SIZE(dev_lookup); i++) { + lookup = &dev_lookup[i]; + if (!strcmp(name, lookup->name)) { + if (test_and_set_bit(0, &lookup->lock)) + lookup = (struct mxs_dev_lookup *)-EBUSY; + mutex_unlock(&device_mutex); + return lookup; + } + + } + mutex_unlock(&device_mutex); + return (struct mxs_dev_lookup *)-ENODEV; +} + +int mxs_device_init(void) +{ + int i, ret = 0; + struct list_head *p, *n; + struct device *dev; + struct platform_device *pdev; + mutex_lock(&device_mutex); + mxs_device_done = 1; + mutex_unlock(&device_mutex); + + for (i = 0; i < ARRAY_SIZE(mxs_device_level); i++) { + list_for_each_safe(p, n, mxs_device_level + i) { + dev = list_entry(p, struct device, devres_head); + list_del(p); + pdev = container_of(dev, struct platform_device, dev); + ret |= platform_device_register(pdev); + } + } + +#if defined(CONFIG_BACKLIGHT_MXS) || \ + defined(CONFIG_BACKLIGHT_MXS_MODULE) + platform_device_register(&mxs_bl); +#endif + + mxs_init_busfreq(); + return ret; +} + +device_initcall(mxs_device_init); diff --git a/arch/arm/plat-mxs/dma-apbh.c b/arch/arm/plat-mxs/dma-apbh.c new file mode 100644 index 000000000000..e7fb96003f6e --- /dev/null +++ b/arch/arm/plat-mxs/dma-apbh.c @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#ifndef BM_APBH_CTRL0_APB_BURST_EN +#define BM_APBH_CTRL0_APB_BURST_EN BM_APBH_CTRL0_APB_BURST4_EN +#endif + +static int mxs_dma_apbh_enable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + unsigned int sem; + struct mxs_dma_device *pdev = pchan->dma; + struct mxs_dma_desc *pdesc; + + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); + if (pdesc == NULL) + return -EFAULT; + + sem = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan)); + sem = (sem & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) { + if (pdesc->cmd.cmd.bits.chain == 0) + return 0; + if (sem < 2) { + if (!sem) + return 0; + pdesc = list_entry(pdesc->node.next, + struct mxs_dma_desc, node); + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBH_CHn_NXTCMDAR(chan)); + } + sem = pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(BF_APBH_CHn_SEMA_INCREMENT_SEMA(sem), + pdev->base + HW_APBH_CHn_SEMA(chan)); + pchan->active_num += sem; + return 0; + } + pchan->active_num += pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBH_CHn_NXTCMDAR(chan)); + __raw_writel(pchan->active_num, pdev->base + HW_APBH_CHn_SEMA(chan)); + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL0_CLR); + return 0; +} + +static void mxs_dma_apbh_disable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + struct mxs_dma_device *pdev = pchan->dma; + __raw_writel(1 << (chan + BP_APBH_CTRL0_CLKGATE_CHANNEL), + pdev->base + HW_APBH_CTRL0_SET); +} + +static void mxs_dma_apbh_reset(struct mxs_dma_device *pdev, unsigned int chan) +{ +#ifdef CONFIG_ARCH_MX28 + __raw_writel(1 << (chan + BP_APBH_CHANNEL_CTRL_RESET_CHANNEL), + pdev->base + HW_APBH_CHANNEL_CTRL_SET); +#endif + +#ifdef CONFIG_ARCH_MX23 + __raw_writel(1 << (chan + BP_APBH_CTRL0_RESET_CHANNEL), + pdev->base + HW_APBH_CTRL0_SET); +#endif +} + +static void mxs_dma_apbh_freeze(struct mxs_dma_device *pdev, unsigned int chan) +{ +#ifdef CONFIG_ARCH_MX28 + __raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_SET); +#endif + +#ifdef CONFIG_ARCH_MX23 + __raw_writel(1 << (chan + BP_APBH_CTRL0_FREEZE_CHANNEL), + pdev->base + HW_APBH_CTRL0_SET); +#endif +} + +static void +mxs_dma_apbh_unfreeze(struct mxs_dma_device *pdev, unsigned int chan) +{ +#ifdef CONFIG_ARCH_MX28 + __raw_writel(1 << chan, pdev->base + HW_APBH_CHANNEL_CTRL_CLR); +#endif + +#ifdef CONFIG_ARCH_MX23 + __raw_writel(1 << (chan + BP_APBH_CTRL0_FREEZE_CHANNEL), + pdev->base + HW_APBH_CTRL0_CLR); +#endif + +} + +static void mxs_dma_apbh_info(struct mxs_dma_device *pdev, + unsigned int chan, struct mxs_dma_info *info) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CTRL2); + info->status = reg >> chan; + info->buf_addr = __raw_readl(pdev->base + HW_APBH_CHn_BAR(chan)); +} + +static int +mxs_dma_apbh_read_semaphore(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CHn_SEMA(chan)); + return (reg & BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE; +} + +static void +mxs_dma_apbh_enable_irq(struct mxs_dma_device *pdev, + unsigned int chan, int enable) +{ + if (enable) { + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_SET); + } else { + __raw_writel(1 << (chan + 16), pdev->base + HW_APBH_CTRL1_CLR); + } +} + +static int +mxs_dma_apbh_irq_is_pending(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBH_CTRL1); + reg |= __raw_readl(pdev->base + HW_APBH_CTRL2); + return reg & (1 << chan); +} + +static void mxs_dma_apbh_ack_irq(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL1_CLR); + __raw_writel(1 << chan, pdev->base + HW_APBH_CTRL2_CLR); +} + +static struct mxs_dma_device mxs_dma_apbh = { + .name = "mxs-dma-apbh", + .enable = mxs_dma_apbh_enable, + .disable = mxs_dma_apbh_disable, + .reset = mxs_dma_apbh_reset, + .freeze = mxs_dma_apbh_freeze, + .unfreeze = mxs_dma_apbh_unfreeze, + .info = mxs_dma_apbh_info, + .read_semaphore = mxs_dma_apbh_read_semaphore, + .enable_irq = mxs_dma_apbh_enable_irq, + .irq_is_pending = mxs_dma_apbh_irq_is_pending, + .ack_irq = mxs_dma_apbh_ack_irq, +}; + +static int __devinit dma_apbh_probe(struct platform_device *pdev) +{ + int i; + struct resource *res; + struct mxs_dma_plat_data *plat; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + mxs_dma_apbh.base = IO_ADDRESS(res->start); + __raw_writel(BM_APBH_CTRL0_SFTRST, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(mxs_dma_apbh.base + HW_APBH_CTRL0_CLR) & + BM_APBH_CTRL0_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -ETIME; + __raw_writel(BM_APBH_CTRL0_CLKGATE, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + plat = (struct mxs_dma_plat_data *)pdev->dev.platform_data; + if (!plat) + return -ENODEV; + if (plat->burst8) + __raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_SET); + else + __raw_writel(BM_APBH_CTRL0_AHB_BURST8_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + if (plat->burst) + __raw_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_SET); + else + __raw_writel(BM_APBH_CTRL0_APB_BURST_EN, + mxs_dma_apbh.base + HW_APBH_CTRL0_CLR); + + mxs_dma_apbh.pdev = pdev; + mxs_dma_apbh.chan_base = plat->chan_base; + mxs_dma_apbh.chan_num = plat->chan_num; + platform_set_drvdata(pdev, &mxs_dma_apbh); + return mxs_dma_device_register(&mxs_dma_apbh); +} + +static int __devexit dma_apbh_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver dma_apbh_driver = { + .probe = dma_apbh_probe, + .remove = __devexit_p(dma_apbh_remove), + .driver = { + .name = "mxs-dma-apbh"}, +}; + +static int __init mxs_dma_apbh_init(void) +{ + return platform_driver_register(&dma_apbh_driver); +} + +fs_initcall(mxs_dma_apbh_init); diff --git a/arch/arm/plat-mxs/dma-apbx.c b/arch/arm/plat-mxs/dma-apbx.c new file mode 100644 index 000000000000..6d77a6933d98 --- /dev/null +++ b/arch/arm/plat-mxs/dma-apbx.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "regs-apbx.h" + +static int mxs_dma_apbx_enable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + unsigned int sem; + struct mxs_dma_device *pdev = pchan->dma; + struct mxs_dma_desc *pdesc; + + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); + if (pdesc == NULL) + return -EFAULT; + sem = __raw_readl(pdev->base + HW_APBX_CHn_SEMA(chan)); + sem = (sem & BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) { + if (pdesc->cmd.cmd.bits.chain == 0) + return 0; + if (sem < 2) { + if (!sem) + return 0; + pdesc = list_entry(pdesc->node.next, + struct mxs_dma_desc, node); + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBX_CHn_NXTCMDAR(chan)); + } + sem = pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(BF_APBX_CHn_SEMA_INCREMENT_SEMA(sem), + pdev->base + HW_APBX_CHn_SEMA(chan)); + pchan->active_num += sem; + return 0; + } + pchan->active_num += pchan->pending_num; + pchan->pending_num = 0; + __raw_writel(mxs_dma_cmd_address(pdesc), + pdev->base + HW_APBX_CHn_NXTCMDAR(chan)); + __raw_writel(pchan->active_num, pdev->base + HW_APBX_CHn_SEMA(chan)); + return 0; +} + +static void mxs_dma_apbx_disable(struct mxs_dma_chan *pchan, unsigned int chan) +{ + struct mxs_dma_device *pdev = pchan->dma; + __raw_writel(0, pdev->base + HW_APBX_CHn_SEMA(chan)); +} + +static void mxs_dma_apbx_reset(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << (chan + BP_APBX_CHANNEL_CTRL_RESET_CHANNEL), + pdev->base + HW_APBX_CHANNEL_CTRL_SET); +} + +static void mxs_dma_apbx_freeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBX_CHANNEL_CTRL_SET); +} + +static void +mxs_dma_apbx_unfreeze(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBX_CHANNEL_CTRL_CLR); +} + +static void mxs_dma_apbx_info(struct mxs_dma_device *pdev, + unsigned int chan, struct mxs_dma_info *info) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBX_CTRL2); + info->status = reg >> chan; + info->buf_addr = __raw_readl(pdev->base + HW_APBX_CHn_BAR(chan)); + reg = __raw_readl(pdev->base + HW_APBX_CHn_CMD(chan)); + info->xfer_count = (reg & BM_APBX_CHn_CMD_XFER_COUNT) >> \ + BP_APBX_CHn_CMD_XFER_COUNT; +} + +static int +mxs_dma_apbx_read_semaphore(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBX_CHn_SEMA(chan)); + return (reg & BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE; +} + +static void +mxs_dma_apbx_enable_irq(struct mxs_dma_device *pdev, + unsigned int chan, int enable) +{ + if (enable) { + __raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL1_SET); + } else { + __raw_writel(1 << (chan + 16), pdev->base + HW_APBX_CTRL1_CLR); + } +} + +static int +mxs_dma_apbx_irq_is_pending(struct mxs_dma_device *pdev, unsigned int chan) +{ + unsigned int reg; + reg = __raw_readl(pdev->base + HW_APBX_CTRL1); + reg |= __raw_readl(pdev->base + HW_APBX_CTRL2); + return reg & (1 << chan); +} + +static void mxs_dma_apbx_ack_irq(struct mxs_dma_device *pdev, unsigned int chan) +{ + __raw_writel(1 << chan, pdev->base + HW_APBX_CTRL1_CLR); + __raw_writel(1 << chan, pdev->base + HW_APBX_CTRL2_CLR); +} + +static struct mxs_dma_device mxs_dma_apbx = { + .name = "mxs-dma-apbx", + .enable = mxs_dma_apbx_enable, + .disable = mxs_dma_apbx_disable, + .reset = mxs_dma_apbx_reset, + .freeze = mxs_dma_apbx_freeze, + .unfreeze = mxs_dma_apbx_unfreeze, + .info = mxs_dma_apbx_info, + .read_semaphore = mxs_dma_apbx_read_semaphore, + .enable_irq = mxs_dma_apbx_enable_irq, + .irq_is_pending = mxs_dma_apbx_irq_is_pending, + .ack_irq = mxs_dma_apbx_ack_irq, +}; + +static int __devinit dma_apbx_probe(struct platform_device *pdev) +{ + int i; + struct resource *res; + struct mxs_dma_plat_data *plat; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + mxs_dma_apbx.base = IO_ADDRESS(res->start); + __raw_writel(BM_APBX_CTRL0_SFTRST, + mxs_dma_apbx.base + HW_APBX_CTRL0_CLR); + for (i = 0; i < 10000; i++) { + if (!(__raw_readl(mxs_dma_apbx.base + HW_APBX_CTRL0_CLR) & + BM_APBX_CTRL0_SFTRST)) + break; + udelay(2); + } + if (i >= 10000) + return -ETIME; + __raw_writel(BM_APBX_CTRL0_CLKGATE, + mxs_dma_apbx.base + HW_APBX_CTRL0_CLR); + + plat = (struct mxs_dma_plat_data *)pdev->dev.platform_data; + if (!plat) + return -ENODEV; + + mxs_dma_apbx.pdev = pdev; + mxs_dma_apbx.chan_base = plat->chan_base; + mxs_dma_apbx.chan_num = plat->chan_num; + platform_set_drvdata(pdev, &mxs_dma_apbx); + return mxs_dma_device_register(&mxs_dma_apbx); +} + +static int __devexit dma_apbx_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver dma_apbx_driver = { + .probe = dma_apbx_probe, + .remove = __devexit_p(dma_apbx_remove), + .driver = { + .name = "mxs-dma-apbx"}, +}; + +static int __init mxs_dma_apbx_init(void) +{ + return platform_driver_register(&dma_apbx_driver); +} + +fs_initcall(mxs_dma_apbx_init); diff --git a/arch/arm/plat-mxs/dmaengine.c b/arch/arm/plat-mxs/dmaengine.c new file mode 100644 index 000000000000..2a41644d2669 --- /dev/null +++ b/arch/arm/plat-mxs/dmaengine.c @@ -0,0 +1,656 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static void *mxs_dma_pool; +static int mxs_dma_alignment = MXS_DMA_ALIGNMENT; + +/* + * The mutex that arbitrates access to the array of structures that represent + * all the DMA channels in the system (see mxs_dma_channels, below). + */ + +static DEFINE_MUTEX(mxs_dma_mutex); + +/* + * The list of DMA drivers that manage various DMA channels. A DMA device + * driver registers to manage DMA channels by calling mxs_dma_device_register(). + */ + +static LIST_HEAD(mxs_dma_devices); + +/* + * The array of struct mxs_dma_chan that represent every DMA channel in the + * system. The index of the structure in the array indicates the specific DMA + * hardware it represents (see mach-mx28/include/mach/dma.h). + */ + +static struct mxs_dma_chan mxs_dma_channels[MAX_DMA_CHANNELS]; + +int mxs_dma_request(int channel, struct device *dev, const char *name) +{ + int ret = 0; + struct mxs_dma_chan *pchan; + + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + + if (!dev || !name) + return -EINVAL; + pchan = mxs_dma_channels + channel; + mutex_lock(&mxs_dma_mutex); + if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID) { + ret = -ENODEV; + goto out; + } + if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED) { + ret = -EBUSY; + goto out; + } + pchan->flags |= MXS_DMA_FLAGS_ALLOCATED; + pchan->name = name; + pchan->dev = (unsigned long)dev; + pchan->active_num = 0; + pchan->pending_num = 0; + spin_lock_init(&pchan->lock); + INIT_LIST_HEAD(&pchan->active); + INIT_LIST_HEAD(&pchan->done); +out: + mutex_unlock(&mxs_dma_mutex); + return ret; +} +EXPORT_SYMBOL(mxs_dma_request); + +void mxs_dma_release(int channel, struct device *dev) +{ + struct mxs_dma_chan *pchan; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + + if (pchan->flags & MXS_DMA_FLAGS_BUSY) + return; + + if (pchan->dev != (unsigned long)dev) + return; + + mutex_lock(&mxs_dma_mutex); + pchan->dev = 0; + pchan->active_num = 0; + pchan->pending_num = 0; + pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED; + mutex_unlock(&mxs_dma_mutex); +} +EXPORT_SYMBOL(mxs_dma_release); + +int mxs_dma_enable(int channel) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + /* + * neednot mutex lock, this function will be called in irq context. + * The mutex may cause process schedule. + */ + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pchan->pending_num && pdma->enable) + ret = pdma->enable(pchan, channel - pdma->chan_base); + pchan->flags |= MXS_DMA_FLAGS_BUSY; + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_enable); + +void mxs_dma_disable(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + if (!(pchan->flags & MXS_DMA_FLAGS_BUSY)) + return; + /* + * neednot mutex lock, this function will be called in irq context. + * The mutex may cause process schedule. + */ + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->disable) + pdma->disable(pchan, channel - pdma->chan_base); + pchan->flags &= ~MXS_DMA_FLAGS_BUSY; + pchan->active_num = 0; + pchan->pending_num = 0; + list_splice_init(&pchan->active, &pchan->done); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_disable); + +int mxs_dma_get_info(int channel, struct mxs_dma_info *info) +{ + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + + if (!info) + return -EINVAL; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EFAULT; + pdma = pchan->dma; + if (pdma->info) + pdma->info(pdma, channel - pdma->chan_base, info); + return 0; +} +EXPORT_SYMBOL(mxs_dma_get_info); + +int mxs_dma_cooked(int channel, struct list_head *head) +{ + int sem; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct list_head *p, *q; + struct mxs_dma_desc *pdesc; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + sem = mxs_dma_read_semaphore(channel); + if (sem < 0) + return sem; + if (sem == pchan->active_num) + return 0; + BUG_ON(sem > pchan->active_num); + spin_lock_irqsave(&pchan->lock, flags); + list_for_each_safe(p, q, &pchan->active) { + if ((pchan->active_num) <= sem) + break; + pdesc = list_entry(p, struct mxs_dma_desc, node); + pdesc->flags &= ~MXS_DMA_DESC_READY; + if (head) + list_move_tail(p, head); + else + list_move_tail(p, &pchan->done); + if (pdesc->flags & MXS_DMA_DESC_LAST) + pchan->active_num--; + } + if (sem == 0) + pchan->flags &= ~MXS_DMA_FLAGS_BUSY; + spin_unlock_irqrestore(&pchan->lock, flags); + + BUG_ON(sem != pchan->active_num); + return 0; +} +EXPORT_SYMBOL(mxs_dma_cooked); + +void mxs_dma_reset(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->reset) + pdma->reset(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_reset); + +void mxs_dma_freeze(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->freeze) + pdma->freeze(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_freeze); + +void mxs_dma_unfreeze(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->unfreeze) + pdma->unfreeze(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_unfreeze); + +int mxs_dma_read_semaphore(int channel) +{ + int ret = -EINVAL; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return ret; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return ret; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->read_semaphore) + ret = pdma->read_semaphore(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_read_semaphore); + +void mxs_dma_enable_irq(int channel, int en) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->enable_irq) + pdma->enable_irq(pdma, channel - pdma->chan_base, en); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_enable_irq); + +int mxs_dma_irq_is_pending(int channel) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return ret; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return ret; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->irq_is_pending) + ret = pdma->irq_is_pending(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_irq_is_pending); + +void mxs_dma_ack_irq(int channel) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->ack_irq) + pdma->ack_irq(pdma, channel - pdma->chan_base); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_ack_irq); + +void mxs_dma_set_target(int channel, int target) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return; + if (pchan->flags & MXS_DMA_FLAGS_BUSY) + return; + pdma = pchan->dma; + spin_lock_irqsave(&pchan->lock, flags); + if (pdma->set_target) + pdma->set_target(pdma, channel - pdma->chan_base, target); + spin_unlock_irqrestore(&pchan->lock, flags); +} +EXPORT_SYMBOL(mxs_dma_set_target); + +/* mxs dma utility function */ +struct mxs_dma_desc *mxs_dma_alloc_desc(void) +{ + struct mxs_dma_desc *pdesc; + unsigned int address; + if (mxs_dma_pool == NULL) + return NULL; + + pdesc = dma_pool_alloc(mxs_dma_pool, GFP_KERNEL, &address); + if (pdesc == NULL) + return NULL; + memset(pdesc, 0, sizeof(*pdesc)); + pdesc->address = address; + return pdesc; +}; +EXPORT_SYMBOL(mxs_dma_alloc_desc); + +void mxs_dma_free_desc(struct mxs_dma_desc *pdesc) +{ + if (pdesc == NULL) + return; + + if (mxs_dma_pool == NULL) + return; + + dma_pool_free(mxs_dma_pool, pdesc, pdesc->address); +} +EXPORT_SYMBOL(mxs_dma_free_desc); + +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc) +{ + int ret = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_desc *last; + struct mxs_dma_device *pdma; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + pdma = pchan->dma; + pdesc->cmd.next = mxs_dma_cmd_address(pdesc); + pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST; + spin_lock_irqsave(&pchan->lock, flags); + if (!list_empty(&pchan->active)) { + last = list_entry(pchan->active.prev, + struct mxs_dma_desc, node); + if (pdesc->cmd.cmd.bits.dec_sem != last->cmd.cmd.bits.dec_sem) { + ret = -EFAULT; + goto out; + } + if (!pdesc->cmd.cmd.bits.dec_sem) { + pdesc->flags &= ~MXS_DMA_DESC_FIRST; + last->flags &= ~MXS_DMA_DESC_LAST; + } + pdesc->cmd.next = last->cmd.next; + last->cmd.next = mxs_dma_cmd_address(pdesc); + last->cmd.cmd.bits.chain = 1; + } + pdesc->flags |= MXS_DMA_DESC_READY; + if (pdesc->flags & MXS_DMA_DESC_FIRST) + pchan->pending_num++; + list_add_tail(&pdesc->node, &pchan->active); +out: + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_desc_append); + +int mxs_dma_desc_add_list(int channel, struct list_head *head) +{ + int ret = 0, size = 0; + unsigned long flags; + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdma; + struct list_head *p; + struct mxs_dma_desc *prev = NULL, *pcur; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + if (list_empty(head)) + return 0; + + pdma = pchan->dma; + list_for_each(p, head) { + pcur = list_entry(p, struct mxs_dma_desc, node); + if (!(pcur->cmd.cmd.bits.dec_sem || pcur->cmd.cmd.bits.chain)) + return -EINVAL; + if (prev) + prev->cmd.next = mxs_dma_cmd_address(pcur); + else + pcur->flags |= MXS_DMA_DESC_FIRST; + pcur->flags |= MXS_DMA_DESC_READY; + prev = pcur; + size++; + } + pcur = list_first_entry(head, struct mxs_dma_desc, node); + prev->cmd.next = mxs_dma_cmd_address(pcur); + prev->flags |= MXS_DMA_DESC_LAST; + + spin_lock_irqsave(&pchan->lock, flags); + if (!list_empty(&pchan->active)) { + pcur = list_entry(pchan->active.next, + struct mxs_dma_desc, node); + if (pcur->cmd.cmd.bits.dec_sem != prev->cmd.cmd.bits.dec_sem) { + ret = -EFAULT; + goto out; + } + prev->cmd.next = mxs_dma_cmd_address(pcur); + prev = list_entry(pchan->active.prev, + struct mxs_dma_desc, node); + pcur = list_first_entry(head, struct mxs_dma_desc, node); + pcur->flags &= ~MXS_DMA_DESC_FIRST; + prev->flags &= ~MXS_DMA_DESC_LAST; + prev->cmd.next = mxs_dma_cmd_address(pcur); + } + list_splice(head, &pchan->active); + pchan->pending_num += size; + if (!(pcur->cmd.cmd.bits.dec_sem) && (pcur->flags & MXS_DMA_DESC_FIRST)) + pchan->pending_num += 1; + else + pchan->pending_num += size; +out: + spin_unlock_irqrestore(&pchan->lock, flags); + return ret; +} +EXPORT_SYMBOL(mxs_dma_desc_add_list); + +int mxs_dma_get_cooked(int channel, struct list_head *head) +{ + unsigned long flags; + struct mxs_dma_chan *pchan; + if ((channel < 0) || (channel >= MAX_DMA_CHANNELS)) + return -EINVAL; + pchan = mxs_dma_channels + channel; + if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) + return -EINVAL; + + if (head == NULL) + return 0; + + spin_lock_irqsave(&pchan->lock, flags); + list_splice(&pchan->done, head); + spin_unlock_irqrestore(&pchan->lock, flags); + return 0; +} +EXPORT_SYMBOL(mxs_dma_get_cooked); + +int mxs_dma_device_register(struct mxs_dma_device *pdev) +{ + int i; + struct mxs_dma_chan *pchan; + + if (pdev == NULL || !pdev->chan_num) + return -EINVAL; + + if ((pdev->chan_base >= MAX_DMA_CHANNELS) || + ((pdev->chan_base + pdev->chan_num) > MAX_DMA_CHANNELS)) + return -EINVAL; + + mutex_lock(&mxs_dma_mutex); + pchan = mxs_dma_channels + pdev->chan_base; + for (i = 0; i < pdev->chan_num; i++, pchan++) { + pchan->dma = pdev; + pchan->flags = MXS_DMA_FLAGS_VALID; + } + list_add(&pdev->node, &mxs_dma_devices); + mutex_unlock(&mxs_dma_mutex); + return 0; +} +EXPORT_SYMBOL(mxs_dma_device_register); + +static int __init mxs_dma_alignment_setup(char *line) +{ + get_option(&line, &mxs_dma_alignment); + mxs_dma_alignment = (mxs_dma_alignment + 3) & (~3); + mxs_dma_alignment = max(mxs_dma_alignment, MXS_DMA_ALIGNMENT); + return 1; +}; + +__setup("mxs-dma-alignment=", mxs_dma_alignment_setup); + +static int mxs_dmaengine_init(void) +{ + mxs_dma_pool = dma_pool_create("mxs_dma", NULL, + sizeof(struct mxs_dma_desc), + mxs_dma_alignment, PAGE_SIZE); + if (mxs_dma_pool == NULL) + return -ENOMEM; + return 0; +} + +subsys_initcall(mxs_dmaengine_init); + +#ifdef CONFIG_PROC_FS + +static void *mxs_dma_proc_seq_start(struct seq_file *file, loff_t * index) +{ + if (*index >= MAX_DMA_CHANNELS) + return NULL; + return mxs_dma_channels + *index; +} + +static void *mxs_dma_proc_seq_next(struct seq_file *file, void *data, + loff_t *index) +{ + if (data == NULL) + return NULL; + + if (*index >= MAX_DMA_CHANNELS) + return NULL; + + return mxs_dma_channels + (*index)++; +} + +static void mxs_dma_proc_seq_stop(struct seq_file *file, void *data) +{ +} + +static int mxs_dma_proc_seq_show(struct seq_file *file, void *data) +{ + struct mxs_dma_chan *pchan; + struct mxs_dma_device *pdev; + + if (data == NULL) + return 0; + + pchan = (struct mxs_dma_chan *)data; + pdev = pchan->dma; + if (pdev == NULL) + return 0; + + return seq_printf(file, "%s-channel%-d (%s)\n", + pdev->name, + pchan - mxs_dma_channels, + pchan->name ? pchan->name : "idle"); +} + +static const struct seq_operations mxc_dma_proc_seq_ops = { + .start = mxs_dma_proc_seq_start, + .next = mxs_dma_proc_seq_next, + .stop = mxs_dma_proc_seq_stop, + .show = mxs_dma_proc_seq_show +}; + +static int mxs_dma_proc_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &mxc_dma_proc_seq_ops); +} + +static const struct file_operations mxs_dma_proc_info_ops = { + .open = mxs_dma_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int __init mxs_dmaengine_info_init(void) +{ + struct proc_dir_entry *res; + res = create_proc_entry("dma-engine", 0, NULL); + if (!res) { + printk(KERN_ERR "Failed to create dma info file \n"); + return -ENOMEM; + } + res->proc_fops = &mxs_dma_proc_info_ops; + return 0; +} + +late_initcall(mxs_dmaengine_info_init); +#endif diff --git a/arch/arm/plat-mxs/gpio.c b/arch/arm/plat-mxs/gpio.c new file mode 100644 index 000000000000..6c67c2bcfc5b --- /dev/null +++ b/arch/arm/plat-mxs/gpio.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#if MXS_ARCH_NR_GPIOS % PINS_PER_BANK +#error "MXS_ARCH_NR_GPIOS must be multipled of PINS_PER_BANK" +#endif + +static struct mxs_gpio_port *mxs_gpios[MXS_ARCH_NR_GPIOS / PINS_PER_BANK]; + +static inline int mxs_valid_gpio(struct mxs_gpio_port *port) +{ + struct mxs_gpio_chip *chip = port->chip; + + if (port->id >= (MXS_ARCH_NR_GPIOS / PINS_PER_BANK)) + return -EINVAL; + + if (port->irq < 0 && port->child_irq > 0) + return -EINVAL; + if (chip->get == NULL || chip->set == NULL || chip->set_dir == NULL) + return -EINVAL; + if (port->child_irq > 0) { + if (chip->get_irq_stat == NULL) + return -EINVAL; + if (chip->mask_irq == NULL || chip->unmask_irq == NULL) + return -EINVAL; + } + return 0; +} + +static int mxs_gpio_request(struct gpio_chip *chip, unsigned int pin) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + return mxs_request_pin(MXS_PIN_ENCODE(port->id, pin), + PIN_GPIO, GPIO_ID_NAME); +} + +static void mxs_gpio_free(struct gpio_chip *chip, unsigned int pin) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + return mxs_release_pin(MXS_PIN_ENCODE(port->id, pin), GPIO_ID_NAME); +} + +static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned int index) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + if (port->child_irq < 0) + return -ENXIO; + return port->child_irq + index; +} + +static int mxs_gpio_get(struct gpio_chip *chip, unsigned int index) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + return port->chip->get(port, index); +} + +static void mxs_gpio_set(struct gpio_chip *chip, unsigned int index, int v) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + port->chip->set(port, index, v); +} + +static int mxs_gpio_output(struct gpio_chip *chip, unsigned int index, int v) +{ + int ret; + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + ret = port->chip->set_dir(port, index, 0); + if (!ret) + port->chip->set(port, index, v); + return ret; +} + +static int mxs_gpio_input(struct gpio_chip *chip, unsigned int index) +{ + struct mxs_gpio_port *port; + port = container_of(chip, struct mxs_gpio_port, port); + return port->chip->set_dir(port, index, 1); +} + +static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) +{ + struct mxs_gpio_port *port = get_irq_data(irq); + int gpio_irq = port->child_irq; + u32 irq_stat = port->chip->get_irq_stat(port); + + desc->chip->mask(irq); + + while (irq_stat) { + if (irq_stat & 1) + generic_handle_irq(gpio_irq); + gpio_irq++; + irq_stat >>= 1; + } + + desc->chip->ack(irq); + desc->chip->unmask(irq); +} + +static int mxs_gpio_set_irq_type(unsigned int irq, unsigned int type) +{ + struct mxs_gpio_port *port; + unsigned int gpio = irq_to_gpio(irq); + port = mxs_gpios[GPIO_TO_BANK(gpio)]; + if (port->child_irq < 0) + return -ENXIO; + if (port->chip->set_irq_type) + return port->chip->set_irq_type(port, GPIO_TO_PINS(gpio), type); + return -ENODEV; +} + +static void mxs_gpio_ack_irq(unsigned int irq) +{ + struct mxs_gpio_port *port; + unsigned int gpio = irq_to_gpio(irq); + port = mxs_gpios[GPIO_TO_BANK(gpio)]; + if (port->child_irq < 0) + return; + if (port->chip->ack_irq) + port->chip->ack_irq(port, GPIO_TO_PINS(gpio)); +} + +static void mxs_gpio_mask_irq(unsigned int irq) +{ + struct mxs_gpio_port *port; + unsigned int gpio = irq_to_gpio(irq); + port = mxs_gpios[GPIO_TO_BANK(gpio)]; + if (port->child_irq < 0) + return; + port->chip->mask_irq(port, GPIO_TO_PINS(gpio)); +} + +static void mxs_gpio_unmask_irq(unsigned int irq) +{ + struct mxs_gpio_port *port; + unsigned int gpio = irq_to_gpio(irq); + port = mxs_gpios[GPIO_TO_BANK(gpio)]; + if (port->child_irq < 0) + return; + port->chip->unmask_irq(port, GPIO_TO_PINS(gpio)); +} + +static struct irq_chip gpio_irq_chip = { + .ack = mxs_gpio_ack_irq, + .mask = mxs_gpio_mask_irq, + .unmask = mxs_gpio_unmask_irq, + .enable = mxs_gpio_unmask_irq, + .disable = mxs_gpio_mask_irq, + .set_type = mxs_gpio_set_irq_type, +}; + +int __init mxs_add_gpio_port(struct mxs_gpio_port *port) +{ + int i, ret; + if (!(port && port->chip)) + return -EINVAL; + + if (mxs_valid_gpio(port)) + return -EINVAL; + + if (mxs_gpios[port->id]) + return -EBUSY; + + mxs_gpios[port->id] = port; + + port->port.base = port->id * PINS_PER_BANK; + port->port.ngpio = PINS_PER_BANK; + port->port.can_sleep = 1; + port->port.exported = 1; + port->port.to_irq = mxs_gpio_to_irq; + port->port.direction_input = mxs_gpio_input; + port->port.direction_output = mxs_gpio_output; + port->port.get = mxs_gpio_get; + port->port.set = mxs_gpio_set; + port->port.request = mxs_gpio_request; + port->port.free = mxs_gpio_free; + port->port.owner = THIS_MODULE; + ret = gpiochip_add(&port->port); + if (ret < 0) + return ret; + + if (port->child_irq < 0) + return 0; + + for (i = 0; i < PINS_PER_BANK; i++) { + gpio_irq_chip.mask(port->child_irq + i); + set_irq_chip(port->child_irq + i, &gpio_irq_chip); + set_irq_handler(port->child_irq + i, handle_level_irq); + set_irq_flags(port->child_irq + i, IRQF_VALID); + } + set_irq_chained_handler(port->irq, mxs_gpio_irq_handler); + set_irq_data(port->irq, port); + return ret; +}; diff --git a/arch/arm/plat-mxs/icoll.c b/arch/arm/plat-mxs/icoll.c new file mode 100644 index 000000000000..1e0b55bd26a9 --- /dev/null +++ b/arch/arm/plat-mxs/icoll.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "regs-icoll.h" + +void __iomem *g_icoll_base; + +/* + * IRQ handling + */ +static void icoll_ack_irq(unsigned int irq) +{ + __raw_writel(0, g_icoll_base + HW_ICOLL_VECTOR); + + /* ACK current interrupt */ + __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, + g_icoll_base + HW_ICOLL_LEVELACK); + + /* Barrier */ + (void)__raw_readl(g_icoll_base + HW_ICOLL_STAT); +} + +static void icoll_mask_irq(unsigned int irq) +{ + __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, + g_icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq)); +} + +static void icoll_unmask_irq(unsigned int irq) +{ + __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, + g_icoll_base + HW_ICOLL_INTERRUPTn_SET(irq)); +} + +static int icoll_set_wake_irq(unsigned int irq, unsigned int enabled) +{ + return 0; +} + +static struct irq_chip icoll_chip = { + .ack = icoll_ack_irq, + .mask = icoll_mask_irq, + .unmask = icoll_unmask_irq, + .set_wake = icoll_set_wake_irq, +}; + +void __init avic_init_irq(void __iomem *base, int nr_irqs) +{ + int i; + g_icoll_base = base; + + /* Reset icoll */ + __raw_writel(BM_ICOLL_CTRL_SFTRST, g_icoll_base + HW_ICOLL_CTRL_CLR); + + for (i = 0; i < 100000; i++) { + if (!(__raw_readl(g_icoll_base + HW_ICOLL_CTRL) & + BM_ICOLL_CTRL_SFTRST)) + break; + udelay(2); + } + if (i >= 100000) { + printk(KERN_ERR "%s:%d timeout when enableing\n", + __func__, __LINE__); + return; + } + __raw_writel(BM_ICOLL_CTRL_CLKGATE, g_icoll_base + HW_ICOLL_CTRL_CLR); + + for (i = 0; i < nr_irqs; i++) { + __raw_writel(0, g_icoll_base + HW_ICOLL_INTERRUPTn(i)); + set_irq_chip(i, &icoll_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + } + + __raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK + (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0), + g_icoll_base + HW_ICOLL_LEVELACK); + __raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK + (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1), + g_icoll_base + HW_ICOLL_LEVELACK); + __raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK + (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2), + g_icoll_base + HW_ICOLL_LEVELACK); + __raw_writel(BF_ICOLL_LEVELACK_IRQLEVELACK + (BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3), + g_icoll_base + HW_ICOLL_LEVELACK); + + __raw_writel(0, g_icoll_base + HW_ICOLL_VECTOR); + /* Barrier */ + (void)__raw_readl(g_icoll_base + HW_ICOLL_STAT); +} + +void mxs_set_irq_fiq(unsigned int irq, unsigned int type) +{ + if (type == 0) + __raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ, + g_icoll_base + + HW_ICOLL_INTERRUPTn_CLR(irq)); + else + __raw_writel(BM_ICOLL_INTERRUPTn_ENFIQ, + g_icoll_base + + HW_ICOLL_INTERRUPTn_SET(irq)); +} +EXPORT_SYMBOL(mxs_set_irq_fiq); + +void mxs_enable_fiq_functionality(int enable) +{ + if (enable) + __raw_writel(BM_ICOLL_CTRL_FIQ_FINAL_ENABLE, + g_icoll_base + HW_ICOLL_CTRL_SET); + else + __raw_writel(BM_ICOLL_CTRL_FIQ_FINAL_ENABLE, + g_icoll_base + HW_ICOLL_CTRL_CLR); + +} +EXPORT_SYMBOL(mxs_enable_fiq_functionality); + diff --git a/arch/arm/plat-mxs/include/mach/arc_otg.h b/arch/arm/plat-mxs/include/mach/arc_otg.h new file mode 100644 index 000000000000..5ba352f90fbe --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/arc_otg.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_ARC_OTG_H__ +#define __ASM_ARCH_MXC_ARC_OTG_H__ + +#include "../../regs-usbphy.h" +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) +#define USB_IRAM_SIZE SZ_8K +#else +#define USB_IRAM_SIZE 0 +#endif + +#define OTG_BASE_ADDR USBCTRL0_PHYS_ADDR +#define USB_OTGREGS_BASE (OTG_BASE_ADDR + 0x000) +/* + * OTG registers + */ +#define UOG_ID (0x00) /* Host ID */ +#define UOG_HWGENERAL (0x04) /* Host General */ +#define UOG_HWHOST (0x08) /* Host h/w params */ +#define UOG_HWTXBUF (0x10) /* TX buffer h/w params */ +#define UOG_HWRXBUF (0x14) /* RX buffer h/w params */ +#define UOG_CAPLENGTH (0x100) /* Capability register length */ +#define UOG_HCIVERSION (0x102) /* Host Interface version */ +#define UOG_HCSPARAMS (0x104) /* Host control structural params */ +#define UOG_HCCPARAMS (0x108) /* control capability params */ +#define UOG_DCIVERSION (0x120) /* device interface version */ +/* start EHCI registers: */ +#define UOG_USBCMD (0x140) /* USB command register */ +#define UOG_USBSTS (0x144) /* USB status register */ +#define UOG_USBINTR (0x148) /* interrupt enable register */ +#define UOG_FRINDEX (0x14c) /* USB frame index */ +/* segment (0x150) addr bits 63:32 if needed */ +#define UOG_PERIODICLISTBASE (0x154) /* host crtlr frame list base addr */ +#define UOG_DEVICEADDR (0x154) /* device crtlr device address */ +#define UOG_ASYNCLISTADDR (0x158) /* host ctrlr next async addr */ +#define UOG_EPLISTADDR (0x158) /* device ctrlr endpoint list addr */ +#define UOG_BURSTSIZE (0x160) /* host ctrlr embedded TT + async buf status */ +#define UOG_TXFILLTUNING (0x164) /* TX FIFO fill tuning */ +#define UOG_ULPIVIEW (0x170) /* ULPI viewport */ +#define UOG_CFGFLAG (0x180) /* configflag (supports HS) */ +#define UOG_PORTSC1 (0x184) /* port status and control */ +/* end EHCI registers: */ +#define UOG_OTGSC (0x1a4) /* OTG status and control */ +#define UOG_USBMODE (0x1a8) /* USB device mode */ +#define UOG_ENDPTSETUPSTAT (0x1ac) /* endpoint setup status */ +#define UOG_ENDPTPRIME (0x1b0) /* endpoint initialization */ +#define UOG_ENDPTFLUSH (0x1b4) /* endpoint de-initialize */ +#define UOG_ENDPTSTAT (0x1b8) /* endpoint status */ +#define UOG_ENDPTCOMPLETE (0x1bc) /* endpoint complete */ +#define UOG_EPCTRL0 (0x1c0) /* endpoint control0 */ +/* + * register bits + */ + +/* x_PORTSCx */ +#define PORTSC_PTS_MASK (3 << 30) /* parallel xcvr mask */ +#define PORTSC_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */ +#define PORTSC_PTS_PHILIPS (1 << 30) /* Philips classic */ +#define PORTSC_PTS_ULPI (2 << 30) /* ULPI */ +#define PORTSC_PTS_SERIAL (3 << 30) /* serial */ +#define PORTSC_STS (1 << 29) /* serial xcvr select */ +#define PORTSC_PTW (1 << 28) /* UTMI width */ +#define PORTSC_PHCD (1 << 23) /* Low Power Suspend */ +#define PORTSC_PORT_POWER (1 << 12) /* port power */ +#define PORTSC_LS_MASK (3 << 10) /* Line State mask */ +#define PORTSC_LS_SE0 (0 << 10) /* SE0 */ +#define PORTSC_LS_K_STATE (1 << 10) /* K-state */ +#define PORTSC_LS_J_STATE (2 << 10) /* J-state */ +#define PORTSC_PORT_RESET (1 << 8) /* Port reset */ +#define PORTSC_PORT_SUSPEND (1 << 7) /* Suspend */ +#define PORTSC_PORT_FORCE_RESUME (1 << 6) /* Force port resume */ +#define PORTSC_OVER_CURRENT_CHG (1 << 5) /* over current change */ +#define PORTSC_OVER_CURRENT_ACT (1 << 4) /* over currrent active */ +#define PORTSC_PORT_EN_DIS_CHANGE (1 << 3) /* port change */ +#define PORTSC_PORT_ENABLE (1 << 2) /* port enabled */ +#define PORTSC_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */ +#define PORTSC_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */ + +#define PORTSC_W1C_BITS \ + (PORTSC_CONNECT_STATUS_CHANGE | \ + PORTSC_PORT_EN_DIS_CHANGE | \ + PORTSC_OVER_CURRENT_CHG) + +/* UOG_OTGSC Register Bits */ +/* control bits: */ +#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0) +#define OTGSC_CTRL_VBUS_CHARGE (1 << 1) +/* controls DM pulldown */ +#define OTGSC_CTRL_OTG_TERM (1 << 3) +#define OTGSC_CTRL_DATA_PULSING (1 << 4) +#define OTGSC_CTRL_USB_ID_PU (1 << 5) +/* current status: (R/O) */ +/* 0=A-device 1=B-device */ +#define OTGSC_STS_USB_ID (1 << 8) +#define OTGSC_STS_A_VBUS_VALID (1 << 9) +#define OTGSC_STS_A_SESSION_VALID (1 << 10) +#define OTGSC_STS_B_SESSION_VALID (1 << 11) +#define OTGSC_STS_B_SESSION_END (1 << 12) +#define OTGSC_STS_1ms_TIMER (1 << 13) +#define OTGSC_STS_DATA_PULSE (1 << 14) +/* interrupt status: (write to clear) */ +#define OTGSC_IS_MASK (0x7f << 16) +#define OTGSC_IS_USB_ID (1 << 16) +#define OTGSC_IS_A_VBUS_VALID (1 << 17) +#define OTGSC_IS_A_SESSION_VALID (1 << 18) +#define OTGSC_IS_B_SESSION_VALID (1 << 19) +#define OTGSC_IS_B_SESSION_END (1 << 20) +#define OTGSC_IS_1ms_TIMER (1 << 21) +#define OTGSC_IS_DATA_PULSE (1 << 22) +/* interrupt enables: */ +#define OTGSC_IE_MASK (0x7f << 24) +#define OTGSC_IE_USB_ID (1 << 24) +#define OTGSC_IE_A_VBUS_VALID (1 << 25) +#define OTGSC_IE_A_SESSION_VALID (1 << 26) +#define OTGSC_IE_B_SESSION_VALID (1 << 27) +#define OTGSC_IE_B_SESSION_END (1 << 28) +#define OTGSC_IE_1ms_TIMER (1 << 29) +#define OTGSC_IE_DATA_PULSE (1 << 30) + +#if 1 /* FIXME these here for compatibility between my names and Leo's */ +/* OTG interrupt enable bit masks */ +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK +#define OTGSC_INTSTS_MASK OTGSC_IS_MASK + +/* OTG interrupt status bit masks */ +#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_IS_MASK +#endif + +/* x_USBMODE */ +#define USBMODE_SLOM (1 << 3) /* setup lockout mode */ +#define USBMODE_ES (1 << 2) /* (big) endian select */ +#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ +#define USBMODE_CM_HOST (3 << 0) /* host */ +#define USBMODE_CM_DEVICE (2 << 0) /* device */ +#define USBMODE_CM_reserved (1 << 0) /* reserved */ + +/* USBCMD */ +#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ +#define UCMD_RESET (1 << 1) /* controller reset */ +#define UCMD_ITC_NO_THRESHOLD (~(0xff << 16)) /* Interrupt Threshold */ + +/* OTG_MIRROR */ +#define OTGM_SESEND (1 << 4) /* B device session end */ +#define OTGM_VBUSVAL (1 << 3) /* Vbus valid */ +#define OTGM_BSESVLD (1 << 2) /* B session Valid */ +#define OTGM_ASESVLD (1 << 1) /* A session Valid */ +#define OTGM_IDIDG (1 << 0) /* OTG ID pin status */ + /* 1=high: Operate as B-device */ + /* 0=low : Operate as A-device */ + +#define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */ + +extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata); +#endif diff --git a/arch/arm/plat-mxs/include/mach/bus_freq.h b/arch/arm/plat-mxs/include/mach/bus_freq.h new file mode 100644 index 000000000000..0c41cd2205ff --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/bus_freq.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef BUS_FREQ_H__ +#define BUS_FREQ_H__ + +#define VERY_HI_RATE 2000000000 +#define LCD_ON_CPU_FREQ_KHZ 261818 +#define OPERATION_WP_SUPPORTED 6 + +struct profile { + int cpu; + int ahb; + int emi; + int ss; + int vddd; + int vddd_bo; + int cur; + int vddio; + int vdda; + u16 xbus; + /* map of the upper 16 bits of HW_CLKCTRL_HBUS register */ + u16 h_autoslow_flags; +}; + +/* map of the upper 16 bits of HW_CLKCTRL_HBUS register */ +int is_hclk_autoslow_ok(void); + +extern int timing_ctrl_rams(int ss); + +#endif diff --git a/arch/arm/plat-mxs/include/mach/clkdev.h b/arch/arm/plat-mxs/include/mach/clkdev.h new file mode 100644 index 000000000000..d6a82c8d5782 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/clkdev.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +extern int __clk_get(struct clk *clk); +extern void __clk_put(struct clk *clk); + +#endif diff --git a/arch/arm/plat-mxs/include/mach/clock.h b/arch/arm/plat-mxs/include/mach/clock.h new file mode 100644 index 000000000000..b506468976b5 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/clock.h @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H +#define __ASM_ARM_ARCH_CLOCK_H + +#ifndef __ASSEMBLER__ + +#include +#include + +struct clk { + int id; + struct clk *parent; + struct clk *secondary; + unsigned long flags; + + int ref; + unsigned int scale_bits; + unsigned int enable_bits; + unsigned int bypass_bits; + unsigned int busy_bits; + unsigned int xtal_busy_bits; + + unsigned int wait:1; + unsigned int invert:1; + + void __iomem *enable_reg; + void __iomem *scale_reg; + void __iomem *bypass_reg; + void __iomem *busy_reg; + + /* + * Function ptr to set the clock to a new rate. The rate must match a + * supported rate returned from round_rate. Leave blank if clock is not + * programmable + */ + int (*set_rate) (struct clk *, unsigned long); + /* + * Function ptr to get the clock rate. + */ + unsigned long (*get_rate) (struct clk *); + /* + * Function ptr to round the requested clock rate to the nearest + * supported rate that is less than or equal to the requested rate. + */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* + * Function ptr to enable the clock. Leave blank if clock can not + * be gated. + */ + int (*enable) (struct clk *); + /* + * Function ptr to disable the clock. Leave blank if clock can not + * be gated. + */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); + + /* Function ptr to change the parent clock depending + * the system configuration at that time. Will only + * change the parent clock if the ref count is 0 (the clock + * is not being used) + */ + int (*set_sys_dependent_parent) (struct clk *); + +}; + +int clk_get_usecount(struct clk *clk); +extern int clk_register(struct clk_lookup *lookup); +extern void clk_unregister(struct clk_lookup *lookup); + +bool clk_enable_h_autoslow(bool enable); +void clk_set_h_autoslow_flags(u16 mask); +void clk_en_public_h_asm_ctrl(bool (*enable_func)(bool), + void (*set_func)(u16)); + +struct mxs_emi_scaling_data { + u32 emi_div; + u32 frac_div; + u32 cur_freq; + u32 new_freq; +}; + + + +#ifdef CONFIG_MXS_RAM_FREQ_SCALING +extern int mxs_ram_freq_scale(struct mxs_emi_scaling_data *); +extern u32 mxs_ram_funcs_sz; +#else +static inline int mxs_ram_freq_scale(struct mxs_emi_scaling_data *p) +{ +} +static u32 mxs_ram_funcs_sz; +#endif + +/* Clock flags */ +/* 0 ~ 16 attribute flags */ +#define ALWAYS_ENABLED (1 << 0) /* Clock cannot be disabled */ +#define RATE_FIXED (1 << 1) /* Fixed clock rate */ +#define CPU_FREQ_TRIG_UPDATE (1 << 2) /* CPUFREQ trig update */ + +/* 16 ~ 23 reservied */ +/* 24 ~ 31 run time flags */ + +#define CLK_REF_UNIT 0x00010000 +#define CLK_REF_LIMIT 0xFFFF0000 +#define CLK_EN_MASK 0x0000FFFF +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/arch/arm/plat-mxs/include/mach/ddi_bc.h b/arch/arm/plat-mxs/include/mach/ddi_bc.h new file mode 100644 index 000000000000..21ca9217cdaa --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/ddi_bc.h @@ -0,0 +1,715 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DDI_BC_H +#define _DDI_BC_H + +#include + +#define DDI_BC_MAX_RESTART_CYCLES 100 + +#define DDI_BC_LIION_CHARGING_VOLTAGE 4200 +#define DDI_BC_ALKALINE_NIMH_CHARGING_VOLTAGE 1750 + +/* brief Defines battery charger states. */ +typedef enum _ddi_bc_State { + /* brief TBD */ + DDI_BC_STATE_UNINITIALIZED = 0, + /* brief TBD */ + DDI_BC_STATE_BROKEN = 1, + /* brief TBD */ + DDI_BC_STATE_DISABLED = 2, + /* brief TBD */ + DDI_BC_STATE_WAITING_TO_CHARGE = 3, + /* brief TBD */ + DDI_BC_STATE_CONDITIONING = 4, + /* brief TBD */ + DDI_BC_STATE_CHARGING = 5, + /* brief TBD */ + DDI_BC_STATE_TOPPING_OFF = 6, + /* brief TBD */ + DDI_BC_STATE_DCDC_MODE_WAITING_TO_CHARGE = 7, + +} ddi_bc_State_t; + +typedef enum _ddi_bc_BrokenReason { + /* brief TBD */ + DDI_BC_BROKEN_UNINITIALIZED = 0, + /* brief TBD */ + DDI_BC_BROKEN_CHARGING_TIMEOUT = 1, + /* brief TBD */ + DDI_BC_BROKEN_FORCED_BY_APPLICATION = 2, + /* brief TBD */ + DDI_BC_BROKEN_EXTERNAL_BATTERY_VOLTAGE_DETECTED = 3, + /* brief TBD */ + DDI_BC_BROKEN_NO_BATTERY_DETECTED = 4, + +} ddi_bc_BrokenReason_t; + +/* brief Defines the battery charger configuration. */ +typedef struct _ddi_bc_Cfg { + /* brief Units in milliseconds. */ + /* */ + /* This field configures the expected period between calls to */ + /* ddi_bc_StateMachine. If die temperature monitoring is */ + /* enabled, then the data sheet recommends the period be around */ + /* 100ms or less. */ + /* */ + /* Note that this period defines the minimum time resolution of */ + /* the battery charger. */ + + uint32_t u32StateMachinePeriod; + + /* brief Units in mA/s. */ + /* */ + /* This field configures the slope of the current ramp. Any */ + /* time the battery charger increases its current draw, it will */ + /* ramp up the current no faster than this rate. */ + /* */ + /* Note that the minimum time resolution of the battery charger */ + /* is the configured period between calls to advance the state */ + /* machine. Also, the hardware has a minimum current resolution */ + /* of 10mA. If the given ramp slope cannot be expressed */ + /* exactly, then the largest expressible smaller slope will be */ + /* the result. If the actual period between calls to */ + /* ddi_bc_StateMachine is irregular, the current may ramp faster */ + /* than indicated. */ + + uint16_t u16CurrentRampSlope; + + /* brief Units in millivolts. */ + /* */ + /* This field configures the threshold conditioning voltage. If */ + /* the battery's voltage is below this value, it will be */ + /* conditioned until its voltage rises above the maximum */ + /* conditioning voltage. After that, the battery will be */ + /* charged normally. */ + /* */ + /* Note that the hardware has a minimum resolution of 8mV. If */ + /* the given voltage cannot be expressed exactly, then the */ + /* smallest expressible larger value will be used. */ + + uint16_t u16ConditioningThresholdVoltage; + + /* brief Units in millivolts. */ + /* */ + /* This field configures the maximum conditioning voltage. If */ + /* the battery charger is conditioning a battery, normal */ + /* charging begins when the voltage rises above this value. */ + /* */ + /* This value should be slightly higher than the threshold */ + /* conditioning voltage because it is measured while a */ + /* conditioning current is actually flowing to the battery. */ + /* With a conditioning current of 0.1C, reasonable values for */ + /* the threshold and maximum conditioning voltages are 2.9V */ + /* and 3.0V respectively. */ + /* */ + /* Note that the hardware has a minimum resolution of 8mV. If */ + /* the given voltage cannot be expressed exactly, then the */ + /* smallest expressible larger value will be used. */ + + uint16_t u16ConditioningMaxVoltage; + + /* brief Units in milliamps. */ + /* */ + /* This field configures the maximum conditioning current. */ + /* This is the maximum current that will be offered to a */ + /* battery while it is being conditioned. A typical value is */ + /* 0.1C. */ + /* */ + /* Note that the hardware has a minimum resolution of 10mA */ + /* (see the data sheet for details). If the given current */ + /* cannot be expressed exactly, then the largest expressible */ + /* smaller value will be used. */ + + uint16_t u16ConditioningCurrent; + + /* brief Units in milliseconds. */ + /* */ + /* This field configures the conditioning time-out. This is */ + /* the maximum amount of time that a battery will be */ + /* conditioned before the battery charger declares it to be */ + /* broken. */ + /* */ + /* Note that the minimum time resolution of the battery */ + /* charger is the configured period between calls to advance */ + /* the state machine. If the given time-out cannot be */ + /* expressed exactly, then the shortest expressible longer */ + /* value will be used. */ + + uint32_t u32ConditioningTimeout; + + /* brief Units in millivolts. */ + /* */ + /* This field configures the final charging voltage. At this */ + /* writing, only two values are permitted: 4100 or 4200. */ + + uint16_t u16ChargingVoltage; + + /* brief Units in milliamps. */ + /* */ + /* This field configures the maximum current offered to a */ + /* charging battery. */ + /* */ + /* Note that the hardware has a minimum resolution of 10mA */ + /* (see the data sheet for details). If the given current */ + /* cannot be expressed exactly, then the largest expressible */ + /* smaller value will be used. */ + + uint16_t u16ChargingCurrent; + + /* brief Units in milliamps. */ + /* */ + /* This field configures the current flow below which a */ + /* charging battery is regarded as fully charged (typical */ + /* 0.1C). At this point, the battery will be topped off. */ + /* */ + /* Note that the hardware has a minimum resolution of 10mA */ + /* (see the data sheet for details). If the given current */ + /* cannot be expressed exactly, then the largest expressible */ + /* smaller value will be used. */ + + uint16_t u16ChargingThresholdCurrent; + + /* brief Units in milliamps. */ + /* */ + /* When charging while the DCDC converter's are enabled, the charger */ + /* is suppling current to both the battery and the Vbat input of the */ + /* DCDC converter. Once the total battery charger current falls */ + /* below this level, the charger will then stop charging until the */ + /* the battery voltage reaches the BC_LOW_DCDCMODE_BATTERY_VOLTAGE */ + /* threshold or until the DCDCs are no longer enabled. */ + /* */ + /* Typically, this value should be left at 180 to avoid the risk */ + /* of topping off the battery too long in DCDC mode and avoid */ + /* exceeding the BC_CHARGING_TIMEOUT time which would put the charger */ + /* driver in the broken state and completely disable charging. */ + /* */ + /* Note that the hardware has a minimum resolution of 10mA */ + /* (see the data sheet for details). If the given current */ + /* cannot be expressed exactly, then the largest expressible */ + /* smaller value will be used. */ + uint16_t u16DdcdModeChargingThresholdCurrent; + + /* brief Units in milliseconds. */ + /* */ + /* This field configures the charging time-out. This is the */ + /* maximum amount of time that a battery will be charged */ + /* before the battery charger declares it to be broken. */ + /* */ + /* Note that the minimum time resolution of the battery */ + /* charger is the configured period between calls to advance */ + /* the state machine. If the given time-out cannot be */ + /* expressed exactly, then the shortest expressible longer */ + /* value will be used. */ + + uint32_t u32ChargingTimeout; + + /* brief Units in milliseconds. */ + /* */ + /* This field configures the top-off period. This is the */ + /* amount of time a battery will be held in the Topping Off */ + /* state before it is declared fully charged. */ + /* */ + /* Note that the minimum time resolution of the battery */ + /* charger is the configured period between calls to advance */ + /* the state machine. If the given time-out cannot be */ + /* expressed exactly, then the shortest expressible longer */ + /* value will be used. */ + + uint32_t u32TopOffPeriod; + + /* brief Units in milliseconds. */ + /* */ + /* This field configures the top-off period when the DCDC */ + /* converters are enabled. To avoid topping off the LiIon */ + /* battery too long and reducing it's long term capacity, */ + /* This time should be kept failry short. */ + /* */ + /* Note that the minimum time resolution of the battery */ + /* charger is the configured period between calls to advance */ + /* the state machine. If the given time-out cannot be */ + /* expressed exactly, then the shortest expressible longer */ + /* value will be used. */ + uint32_t u32DcdcModeTopOffPeriod; + + /* brief Causes the battery charger to use an externally generated bias current */ + /* */ + /* If cleared, this causes the battery charger to use an */ + /* externally generated bias current, which is expected to be */ + /* quite precise. Otherwise, the battery charger will */ + /* generate a lesser-quality bias current internally. */ + + uint8_t useInternalBias:1; + + /* brief Indicates that the battery charger is to monitor the die temperature. */ + /* */ + /* If set, this field indicates that the battery charger is to */ + /* monitor the die temperature. See below for fields that */ + /* configure the details. */ + + uint8_t monitorDieTemp:1; + + /* brief Indicates that the battery charger is to monitor the battery temperature. */ + /* */ + /* If set, this field indicates that the battery charger is to */ + /* monitor the battery temperature. See below for fields that */ + /* configure the details. */ + + uint8_t monitorBatteryTemp:1; + + /* brief Units in degrees centigrade. */ + /* */ + /* Note that the hardware reports die temperature in ranges of */ + /* 10 degree resolution minimum (see the data sheet for */ + /* details). If the battery charger is monitoring the die */ + /* temperature, and it rises to a range that includes a */ + /* temperature greater than or equal to this value, the */ + /* charging current will be clamped to the safe current. */ + + int8_t u8DieTempHigh; + + /* brief Units in degrees centigrade. */ + /* */ + /* Note that the hardware reports die temperature in ranges of */ + /* 10 degrees minimum (see the data sheet for details). If the */ + /* charging current is being clamped because of a high die */ + /* temperature, and it falls to a range that doesn't include a */ + /* temperatures greater than or equal to this value, the */ + /* charging current clamp will be released. */ + + int8_t u8DieTempLow; + + /* brief Units in milliamps. */ + /* */ + /* If the battery charger detects a high die temperature, it */ + /* will clamp the charging current at or below this value. */ + + uint16_t u16DieTempSafeCurrent; + + /* brief If the battery charger is monitoring the battery */ + /* temperature, this field indicates the LRADC channel to */ + /* read. */ + + uint8_t u8BatteryTempChannel; + + /* brief If the battery charger is monitoring the battery */ + /* temperature, and it rises to a measurement greater than or */ + /* equal to this value, the charging current will be clamped */ + /* to the corresponding safe current. */ + + uint16_t u16BatteryTempHigh; + + /* brief If the charging current is being clamped because of a high */ + /* battery temperature, and it falls below this value, the */ + /* charging current clamp will be released. */ + + uint16_t u16BatteryTempLow; + + /* brief Units in milliamps. */ + /* */ + /* If the battery charger detects a high battery temperature, */ + /* it will clamp the charging current at or below this value. */ + + uint16_t u16BatteryTempSafeCurrent; + + /* brief Units in millivolts. */ + /* */ + /* In the WaitingToCharge state, if we are in DCDC */ + /* operating modes, if the battery voltage measurement */ + /* is below this value, we immediately proceed with charging. */ + /* the low criteria for this value is that it must be high */ + /* to not risk the battery voltage getting too low. The */ + /* upper criteria is that you do not want the IR voltage */ + /* drop under heavy loads to make you start charging too soon */ + /* because the goal in DCDC operating mode is to not be constantly */ + /* topping off the battery which can shorten its life */ + + uint16_t u16LowDcdcBatteryVoltage_mv; + + uint32_t u32StateMachineNonChargingPeriod; +} ddi_bc_Cfg_t; + +/* Status returned by Battery Charger functions. */ + +typedef enum _ddi_bc_Status { + /* brief TBD */ + DDI_BC_STATUS_SUCCESS = 0, + /* brief TBD */ + DDI_BC_STATUS_HARDWARE_DISABLED, + /* brief TBD */ + DDI_BC_STATUS_BAD_BATTERY_MODE, + /* brief TBD */ + DDI_BC_STATUS_CLOCK_GATE_CLOSED, + /* brief TBD */ + DDI_BC_STATUS_NOT_INITIALIZED, + /* brief TBD */ + DDI_BC_STATUS_ALREADY_INITIALIZED, + /* brief TBD */ + DDI_BC_STATUS_BROKEN, + /* brief TBD */ + DDI_BC_STATUS_NOT_BROKEN, + /* brief TBD */ + DDI_BC_STATUS_NOT_DISABLED, + /* brief TBD */ + DDI_BC_STATUS_BAD_ARGUMENT, + /* brief TBD */ + DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL, + /* brief TBD */ + DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE, +} ddi_bc_Status_t; + + +/* BCM Event Codes */ + +/* These are the codes that might be published to PMI Subscribers. */ + + +#define DDI_BC_EVENT_GROUP (11<<10) + +/* brief TBD */ +/* todo [PUBS] Add definition(s)... */ +typedef enum { + /* Use the error code group value to make events unique for the EOI */ + /* brief TBD */ + ddi_bc_MinEventCode = DDI_BC_EVENT_GROUP, + /* brief TBD */ + ddi_bc_WaitingToChargeCode, + /* brief TBD */ + ddi_bc_State_ConditioningCode, + /* brief TBD */ + ddi_bc_State_Topping_OffCode, + /* brief TBD */ + ddi_bc_State_BrokenCode, + /* brief TBD */ + ddi_bc_SettingChargeCode, + /* brief TBD */ + ddi_bc_RaisingDieTempAlarmCode, + /* brief TBD */ + ddi_bc_DroppingDieTempAlarmCode, + + /* brief TBD */ + ddi_bc_MaxEventCode, + /* brief TBD */ + ddi_bc_DcdcModeWaitingToChargeCode +} ddi_bc_Event_t; + + +/* Prototypes */ + + + +/* brief Initialize the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* This function initializes the Battery Charger. */ +/* */ +/* param[in] pCfg A pointer to the new configuration. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS */ +/* If the operation succeeded. */ +/* retval DDI_BC_STATUS_ALREADY_INITIALIZED */ +/* If the Battery Charger is already initialized. */ +/* retval DDI_BC_STATUS_HARDWARE_DISABLED */ +/* If the Battery Charger hardware is disabled by a laser fuse. */ +/* retval DDI_BC_STATUS_BAD_BATTERY_MODE */ +/* If the power supply is set up for a non-rechargeable battery. */ +/* retval DDI_BC_STATUS_CLOCK_GATE_CLOSED */ +/* If the clock gate for the power supply registers is closed. */ +/* retval DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE */ +/* If the charging voltage is not either 4100 or 4200. */ +/* retval DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL */ +/* If the LRADC channel number for monitoring battery temperature */ +/* is bad. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_init.c. */ + +extern ddi_bc_Status_t ddi_bc_Init(ddi_bc_Cfg_t *pCfg); + +/* */ +/* brief Report the Battery Charger configuration. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the Battery Charger configuration. */ +/* */ +/* Note that, if the Battery Charger has not yet been initialized, the data */ +/* returned by this function is unknown. */ +/* */ +/* param[in,out] pCfg A pointer to a structure that will receive the data. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern void ddi_bc_QueryCfg(ddi_bc_Cfg_t *pCfg); + +/* */ +/* brief Shut down the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* This function immediately shuts down the Battery Charger hardware and */ +/* returns the state machine to the Uninitialized state. Use this function to */ +/* safely mummify the battery charger before retiring it from memory. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern void ddi_bc_ShutDown(void); + +/* */ +/* brief Advances the state machine. */ +/* */ +/* fntype Function */ +/* */ +/* This function advances the state machine. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_BROKEN If the battery violated a time-out */ +/* and has been declared broken. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_StateMachine(void); + +/* */ +/* brief Get the Battery Charger's current state. */ +/* */ +/* fntype Function */ +/* */ +/* This function returns the current state. */ +/* */ +/* retval The current state. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_State_t ddi_bc_GetState(void); + +/* */ +/* brief Disable the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* This function forces the Battery Charger into the Disabled state. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_SetDisable(void); + +/* */ +/* brief Enable the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* If the Battery Charger is in the Disabled state, this function moves it to */ +/* the Waiting to Charge state. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_NOT_DISABLED If the Battery Charger is not */ +/* disabled. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_SetEnable(void); + +/* */ +/* brief Declare the battery to be broken. */ +/* */ +/* fntype Function */ +/* */ +/* This function forces the Battery Charger into the Broken state. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_SetBroken(void); + +/* */ +/* brief Declare the battery to be fixed. */ +/* */ +/* fntype Function */ +/* */ +/* If the Battery Charger is in the Broken state, this function moves it to */ +/* the Disabled state. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_NOT_BROKEN If the Battery Charger is not broken. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern ddi_bc_Status_t ddi_bc_SetFixed(void); + +/* */ +/* brief Set the current limit. */ +/* */ +/* fntype Function */ +/* */ +/* This function applies a limit to the current that the Battery Charger can */ +/* draw. */ +/* */ +/* param[in] u16Limit The maximum current the Battery Charger can draw */ +/* (in mA). */ +/* */ +/* retval The expressible version of the limit. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern uint16_t ddi_bc_SetCurrentLimit(uint16_t u16Limit); + + +/* */ +/* brief Report the current limit. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the limit to the current that the Battery Charger can */ +/* draw. */ +/* */ +/* retval The current limit. */ +/* */ +/* internal */ +/* see To view the function definition, see ddi_bc_api.c. */ + +extern uint16_t ddi_bc_GetCurrentLimit(void); + + +/* */ +/* brief Set the current threshold. */ +/* */ +/* fntype Function */ +/* */ +/* */ +/* param[in] u16Current Current threshold where charger deactivates (in mA). */ +/* */ +/* */ + +extern uint16_t ddi_bc_SetCurrentThreshold(uint16_t u16Current); + + +/* */ +/* brief Set the battery charger state machine period. */ +/* */ +/* fntype Function */ +/* */ +/* This function sets a new state machine period. The Period and Slope should */ +/* be coordinated to achieve the minimal ramp step current which will minimize */ +/* transients on the system. */ +/* */ +/* param[in] u32StateMachinePeriod (in milliseconds) */ +/* param[in] u16CurrentRampSlope (in mA/s) */ +/* */ +/* retval SUCCESS If all goes well */ +/* retval ERROR_DDI_BCM_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* */ + +extern ddi_bc_Status_t ddi_bc_SetNewPeriodAndSlope(uint32_t + u32StateMachinePeriod, + uint16_t + u16CurrentRampSlope); + + +/* */ +/* brief Report the state machine period. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the battery charger period. */ +/* */ +/* retval The battery charger period (in milliseconds). */ +/* */ + +extern uint32_t ddi_bc_GetStateMachinePeriod(void); + + +/* */ +/* brief Report the current ramp slope. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the current ramp slope. */ +/* */ +/* retval The current ramp slope (in mA/s). */ +/* */ + +extern uint32_t ddi_bc_GetCurrentRampSlope(void); + + +/* */ +/* brief Report the time spent in the present state (milliseconds) */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the time spent in the present charging state. Note that */ +/* for the states that actually charge the battery, this time does not include the */ +/* time spent under alarm conditions such as die termperature alarm or battery */ +/* temperature alarm. */ +/* */ +/* retval The time spent in the current state in milliseconds. */ +/* */ + +uint32_t ddi_bc_GetStateTime(void); + + +/* */ +/* brief Report the reason for being in the broken state */ +/* */ +/* fntype Function */ +/* */ +/* */ +/* retval ddi_bc_BrokenReason_t enumeration */ +/* */ + +ddi_bc_BrokenReason_t ddi_bc_GetBrokenReason(void); + + +/* */ +/* brief Restart the charge cycle */ +/* */ +/* fntype Function */ +/* */ +/* retval SUCCESS */ +/* */ + +ddi_bc_Status_t ddi_bc_ForceChargingToStart(void); + +void fsl_enable_usb_plugindetect(void); + +int fsl_is_usb_plugged(void); + +/* End of file */ + +#endif /* _DDI_BC_H */ +/* @} */ diff --git a/arch/arm/plat-mxs/include/mach/debug-macro.S b/arch/arm/plat-mxs/include/mach/debug-macro.S new file mode 100644 index 000000000000..147cda360cb3 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/debug-macro.S @@ -0,0 +1,42 @@ +/* + * Debugging macro include header + * + * Embedded Alley Solutions, Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + + .macro addruart,rx,tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =MXS_LL_UART_PADDR @ physical + ldrne \rx, =MXS_LL_UART_VADDR @ virtual + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #0] @ data register at 0 + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full + bne 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #0x18] @ UARTFLG + tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy + bne 1001b + .endm diff --git a/arch/arm/plat-mxs/include/mach/device.h b/arch/arm/plat-mxs/include/mach/device.h new file mode 100644 index 000000000000..080add7d8fa2 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/device.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DEVICE_H +#define __ASM_ARM_ARCH_DEVICE_H + +#include +#include +#include +#include +#include + +#include + +#define MXS_MAX_DEVICES 128 + +struct mxs_sys_timer { + struct sys_timer timer; + unsigned char id; + unsigned char clk_sel; + unsigned char resv[2]; + int irq; + struct clk *clk; + void __iomem *base; +}; + +struct mxs_dev_lookup { + char *name; + unsigned long lock; + int size; + struct platform_device *pdev; +}; + +/* Define the Platform special structure for each device type*/ +struct mxs_dma_plat_data { + unsigned int burst8:1; + unsigned int burst:1; + unsigned int chan_base; + unsigned int chan_num; +}; + +struct fsl_otp_data { + char **fuse_name; + char *regulator_name; + unsigned int fuse_num; +}; + +struct mxs_i2c_plat_data { + unsigned int pioqueue_mode:1; +}; + +struct mxs_lradc_plat_data { + unsigned int vddio_voltage; + unsigned int battery_voltage; +}; + +struct mxskbd_keypair { + int raw; + int kcode; +}; + +struct mxs_kbd_plat_data { + struct mxskbd_keypair *keypair; + int channel; + unsigned int btn_enable; /* detect enable bits */ + unsigned int btn_irq_stat; /* detect irq status bits */ + unsigned int btn_irq_ctrl; /* detect irq enable bits */ +}; + +struct mxs_touchscreen_plat_data { + u8 x_plus_chan; + u8 x_minus_chan; + u8 y_plus_chan; + u8 y_minus_chan; + unsigned int x_plus_val; + unsigned int x_minus_val; + unsigned int y_plus_val; + unsigned int y_minus_val; + unsigned int x_plus_mask; + unsigned int x_minus_mask; + unsigned int y_plus_mask; + unsigned int y_minus_mask; +}; + +struct mxs_auart_plat_data { + unsigned int fifo_size:6; + unsigned int dma_mode:1; + unsigned int timeout; + unsigned int dma_rx_buffer_size; + const char *clk; +}; + +struct mxs_pwm_led { + struct led_classdev dev; + const char *name; + unsigned int pwm; +}; + +struct mxs_pwm_leds_plat_data { + unsigned int num; + struct mxs_pwm_led *leds; +}; + +struct mxs_mma7450_platform_data { + char *reg_dvdd_io; + char *reg_avdd; + void (*gpio_pin_get) (void); + void (*gpio_pin_put) (void); + int int1; + int int2; +}; + +struct mxs_spi_platform_data { + int (*hw_pin_init)(void); + int (*hw_pin_release)(void); + + char *clk; +}; + +struct mxs_audio_platform_data { + int intr_id_hp; + int ext_ram; + struct clk *saif_mclock; + + int hp_irq; + int (*hp_status) (void); + + int sysclk; + + int (*init) (void); /* board specific init */ + int (*amp_enable) (int enable); + int (*finit) (void); /* board specific finit */ + void *priv; /* used by board specific functions */ +}; + +struct mxs_persistent_bit_config { + int reg; + int start; + int width; + const char *name; +}; + +struct mxs_platform_persistent_data { + const struct mxs_persistent_bit_config *bit_config_tab; + int bit_config_cnt; +}; + +extern void mxs_timer_init(struct mxs_sys_timer *timer); +extern void mxs_nomatch_timer_init(struct mxs_sys_timer *timer); + +extern void mxs_nop_release(struct device *dev); +extern int mxs_add_devices(struct platform_device *, int num, int level); +extern int mxs_add_device(struct platform_device *, int level); +extern struct platform_device *mxs_get_device(char *name, int id); +extern struct mxs_dev_lookup *mxs_get_devices(char *name); + +extern int iram_init(unsigned long base, unsigned long size); + +/* mxs ssp sd/mmc data definitons */ +struct mxs_mmc_platform_data { + int (*hw_init)(void); + void (*hw_release)(void); + void (*cmd_pullup)(int enable); + int (*get_wp)(void); + unsigned long (*setclock)(unsigned long hz); + unsigned int caps; + unsigned int min_clk; + unsigned int max_clk; + int read_uA; + int write_uA; + char *power_mmc; + char *clock_mmc; +}; +/* end of mxs ssp sd/mmc data definitions */ + +#ifdef CONFIG_MXS_ICOLL +extern void __init avic_init_irq(void __iomem *base, int nr_irqs); +#endif + +#endif diff --git a/arch/arm/plat-mxs/include/mach/dmaengine.h b/arch/arm/plat-mxs/include/mach/dmaengine.h new file mode 100644 index 000000000000..1600d9762a9e --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/dmaengine.h @@ -0,0 +1,518 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_DMA_H +#define __ASM_ARM_ARCH_DMA_H + +#ifndef ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 8 + +/** + * struct mxs_dma_cmd_bits - MXS DMA hardware command bits. + * + * This structure describes the in-memory layout of the command bits in a DMA + * command. See the appropriate reference manual for a detailed description + * of what these bits mean to the DMA hardware. + */ +struct mxs_dma_cmd_bits { + unsigned int command:2; +#define NO_DMA_XFER 0x00 +#define DMA_WRITE 0x01 +#define DMA_READ 0x02 +#define DMA_SENSE 0x03 + + unsigned int chain:1; + unsigned int irq:1; + unsigned int nand_lock:1; + unsigned int nand_wait_4_ready:1; + unsigned int dec_sem:1; + unsigned int wait4end:1; + unsigned int halt_on_terminate:1; + unsigned int terminate_flush:1; + unsigned int resv2:2; + unsigned int pio_words:4; + unsigned int bytes:16; +}; + +/* fill the word 1 of the DMA channel command structure */ +#define fill_dma_word1(cmdp, _cmd, _chain, _irq, _lock, _wait_ready, _dec_sem,\ + _wait4end, _halt_on_term, _term_flush, _pio_words, _bytes)\ + do { \ + struct mxs_dma_cmd_bits *bits = &(cmdp)->bits; \ + \ + /* reset all the fields first */ \ + (cmdp)->data = 0; \ + \ + bits->command = _cmd; \ + bits->chain = _chain; \ + bits->irq = _irq; \ + bits->nand_lock = _lock; \ + bits->nand_wait_4_ready = _wait_ready; \ + bits->dec_sem = _dec_sem; \ + bits->wait4end = _wait4end; \ + bits->halt_on_terminate = _halt_on_term; \ + bits->terminate_flush = _term_flush; \ + bits->pio_words = _pio_words; \ + bits->bytes = _bytes; \ + } while (0) + +/** + * struct mxs_dma_cmd - MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +struct mxs_dma_cmd { + unsigned long next; + union { + unsigned long data; + struct mxs_dma_cmd_bits bits; + } cmd; + union { + dma_addr_t address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +/** + * struct mxs_dma_desc - MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + * + * @cmd: The MXS DMA hardware command block. + * @flags: Flags that represent the state of this DMA descriptor. + * @address: The physical address of this descriptor. + * @buffer: A convenient place for software to put the virtual address of the + * associated data buffer (the physical address of the buffer + * appears in the DMA command). The MXS platform DMA software doesn't + * use this field -- it is provided as a convenience. + * @node: Links this structure into a list. + */ +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; +#define MXS_DMA_DESC_READY 0x80000000 +#define MXS_DMA_DESC_FIRST 0x00000001 +#define MXS_DMA_DESC_LAST 0x00000002 + dma_addr_t address; + void *buffer; + struct list_head node; +}; + +struct mxs_dma_info { + unsigned int status; +#define MXS_DMA_INFO_ERR 0x00000001 +#define MXS_DMA_INFO_ERR_STAT 0x00010000 + unsigned int buf_addr; + unsigned int xfer_count; +}; + +/** + * struct mxs_dma_chan - MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + * + * @name: A human-readable string that describes how this channel is + * being used or what software "owns" it. This field is set when + * when the channel is reserved by mxs_dma_request(). + * @dev: A pointer to a struct device *, cast to an unsigned long, and + * representing the software that "owns" the channel. This field + * is set when when the channel is reserved by mxs_dma_request(). + * @lock: Arbitrates access to this channel. + * @dma: A pointer to a struct mxs_dma_device representing the driver + * code that operates this channel. + * @flags: Flag bits that represent the state of this channel. + * @active_num: If the channel is not busy, this value is zero. If the channel + * is busy, this field contains the number of DMA command + * descriptors at the head of the active list that the hardware + * has been told to process. This value is set at the moment the + * channel is enabled by mxs_dma_enable(). More descriptors may + * arrive after the channel is enabled, so the number of + * descriptors on the active list may be greater than this value. + * In fact, it should always be active_num + pending_num. + * @pending_num: The number of DMA command descriptors at the tail of the + * active list that the hardware has not been told to process. + * @active: The list of DMA command descriptors either currently being + * processed by the hardware or waiting to be processed. + * Descriptors being processed appear at the head of the list, + * while pending descriptors appear at the tail. The total number + * should always be active_num + pending_num. + * @done: The list of DMA command descriptors that have either been + * processed by the DMA hardware or aborted by a call to + * mxs_dma_disable(). + */ +struct mxs_dma_chan { + const char *name; + unsigned long dev; + spinlock_t lock; + struct mxs_dma_device *dma; + unsigned int flags; +#define MXS_DMA_FLAGS_IDLE 0x00000000 +#define MXS_DMA_FLAGS_BUSY 0x00000001 +#define MXS_DMA_FLAGS_FREE 0x00000000 +#define MXS_DMA_FLAGS_ALLOCATED 0x00010000 +#define MXS_DMA_FLAGS_VALID 0x80000000 + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +/** + * struct mxs_dma_device - DMA channel driver interface. + * + * This structure represents the driver that operates a DMA channel. Every + * struct mxs_dma_chan contains a pointer to a structure of this type, which is + * installed when the driver registers to "own" the channel (see + * mxs_dma_device_register()). + */ +struct mxs_dma_device { + struct list_head node; + const char *name; + void __iomem *base; + unsigned int chan_base; + unsigned int chan_num; + unsigned int data; + struct platform_device *pdev; + + /* operations */ + int (*enable) (struct mxs_dma_chan *, unsigned int); + void (*disable) (struct mxs_dma_chan *, unsigned int); + void (*reset) (struct mxs_dma_device *, unsigned int); + void (*freeze) (struct mxs_dma_device *, unsigned int); + void (*unfreeze) (struct mxs_dma_device *, unsigned int); + int (*read_semaphore) (struct mxs_dma_device *, unsigned int); + void (*add_semaphore) (struct mxs_dma_device *, unsigned int, unsigned); + void (*info)(struct mxs_dma_device *, + unsigned int, struct mxs_dma_info *info); + void (*enable_irq) (struct mxs_dma_device *, unsigned int, int); + int (*irq_is_pending) (struct mxs_dma_device *, unsigned int); + void (*ack_irq) (struct mxs_dma_device *, unsigned int); + + void (*set_target) (struct mxs_dma_device *, unsigned int, int); +}; + +/** + * mxs_dma_device_register - Register a DMA driver. + * + * This function registers a driver for a contiguous group of DMA channels (the + * ordering of DMA channels is specified by the globally unique DMA channel + * numbers given in mach/dma.h). + * + * @pdev: A pointer to a structure that represents the driver. This structure + * contains fields that specify the first DMA channel number and the + * number of channels. + */ +extern int mxs_dma_device_register(struct mxs_dma_device *pdev); + +/** + * mxs_dma_request - Request to reserve a DMA channel. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." + * @name: A human-readable string that identifies the channel owner or the + * purpose of the channel. + */ +extern int mxs_dma_request(int channel, struct device *dev, const char *name); + +/** + * mxs_dma_release - Release a DMA channel. + * + * This function releases a DMA channel from its current owner. + * + * The channel will NOT be released if it's marked "busy" (see + * mxs_dma_enable()). + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @dev: A pointer to a struct device representing the channel "owner." If + * this doesn't match the owner given to mxs_dma_request(), the + * channel will NOT be released. + */ +extern void mxs_dma_release(int channel, struct device *dev); + +/** + * mxs_dma_enable - Enable a DMA channel. + * + * If the given channel has any DMA descriptors on its active list, this + * function causes the DMA hardware to begin processing them. + * + * This function marks the DMA channel as "busy," whether or not there are any + * descriptors to process. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_enable(int channel); + +/** + * mxs_dma_disable - Disable a DMA channel. + * + * This function shuts down a DMA channel and marks it as "not busy." Any + * descriptors on the active list are immediately moved to the head of the + * "done" list, whether or not they have actually been processed by the + * hardware. The "ready" flags of these descriptors are NOT cleared, so they + * still appear to be active. + * + * This function immediately shuts down a DMA channel's hardware, aborting any + * I/O that may be in progress, potentially leaving I/O hardware in an undefined + * state. It is unwise to call this function if there is ANY chance the hardware + * is still processing a command. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_disable(int channel); + +/** + * mxs_dma_reset - Resets the DMA channel hardware. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_reset(int channel); + +/** + * mxs_dma_freeze - Freeze a DMA channel. + * + * This function causes the channel to continuously fail arbitration for bus + * access, which halts all forward progress without losing any state. A call to + * mxs_dma_unfreeze() will cause the channel to continue its current operation + * with no ill effect. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_freeze(int channel); + +/** + * mxs_dma_unfreeze - Unfreeze a DMA channel. + * + * This function reverses the effect of mxs_dma_freeze(), enabling the DMA + * channel to continue from where it was frozen. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ + +extern void mxs_dma_unfreeze(int channel); + +/* get dma channel information */ +extern int mxs_dma_get_info(int channel, struct mxs_dma_info *info); + +/** + * mxs_dma_cooked - Clean up processed DMA descriptors. + * + * This function removes processed DMA descriptors from the "active" list. Pass + * in a non-NULL list head to get the descriptors moved to your list. Pass NULL + * to get the descriptors moved to the channel's "done" list. Descriptors on + * the "done" list can be retrieved with mxs_dma_get_cooked(). + * + * This function marks the DMA channel as "not busy" if no unprocessed + * descriptors remain on the "active" list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: If this is not NULL, it is the list to which the processed + * descriptors should be moved. If this list is NULL, the descriptors + * will be moved to the "done" list. + */ +extern int mxs_dma_cooked(int channel, struct list_head *head); + +/** + * mxs_dma_read_semaphore - Read a DMA channel's hardware semaphore. + * + * As used by the MXS platform's DMA software, the DMA channel's hardware + * semaphore reflects the number of DMA commands the hardware will process, but + * has not yet finished. This is a volatile value read directly from hardware, + * so it must be be viewed as immediately stale. + * + * If the channel is not marked busy, or has finished processing all its + * commands, this value should be zero. + * + * See mxs_dma_append() for details on how DMA command blocks must be configured + * to maintain the expected behavior of the semaphore's value. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_read_semaphore(int channel); + +/** + * mxs_dma_irq_is_pending - Check if a DMA interrupt is pending. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern int mxs_dma_irq_is_pending(int channel); + +/** + * mxs_dma_enable_irq - Enable or disable DMA interrupt. + * + * This function enables the given DMA channel to interrupt the CPU. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @en: True if the interrupt for this channel should be enabled. False + * otherwise. + */ +extern void mxs_dma_enable_irq(int channel, int en); + +/** + * mxs_dma_ack_irq - Clear DMA interrupt. + * + * The software that is using the DMA channel must register to receive its + * interrupts and, when they arrive, must call this function to clear them. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + */ +extern void mxs_dma_ack_irq(int channel); + +/** + * mxs_dma_set_target - Set the target for a DMA channel. + * + * This function is NOT used on the i.MX28. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @target: Indicates the target for the channel. + */ +extern void mxs_dma_set_target(int channel, int target); + +/* mxs dma utility functions */ +extern struct mxs_dma_desc *mxs_dma_alloc_desc(void); +extern void mxs_dma_free_desc(struct mxs_dma_desc *); + +/** + * mxs_dma_cmd_address - Return the address of the command within a descriptor. + * + * @desc: The DMA descriptor of interest. + */ +static inline unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc) +{ + return desc->address += offsetof(struct mxs_dma_desc, cmd); +} + +/** + * mxs_dma_desc_pending - Check if descriptor is on a channel's active list. + * + * This function returns the state of a descriptor's "ready" flag. This flag is + * usually set only if the descriptor appears on a channel's active list. The + * descriptor may or may not have already been processed by the hardware. + * + * The "ready" flag is set when the descriptor is submitted to a channel by a + * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is + * cleared when a processed descriptor is moved off the active list by a call + * to mxs_dma_cooked(). The "ready" flag is NOT cleared if the descriptor is + * aborted by a call to mxs_dma_disable(). + * + * @desc: The DMA descriptor of interest. + */ +static inline int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc) +{ + return pdesc->flags & MXS_DMA_DESC_READY; +} + +/** + * mxs_dma_desc_append - Add a DMA descriptor to a channel. + * + * If the descriptor list for this channel is not empty, this function sets the + * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so + * it will chain to the new descriptor's command. + * + * Then, this function marks the new descriptor as "ready," adds it to the end + * of the active descriptor list, and increments the count of pending + * descriptors. + * + * The MXS platform DMA software imposes some rules on DMA commands to maintain + * important invariants. These rules are NOT checked, but they must be carefully + * applied by software that uses MXS DMA channels. + * + * Invariant: + * The DMA channel's hardware semaphore must reflect the number of DMA + * commands the hardware will process, but has not yet finished. + * + * Explanation: + * A DMA channel begins processing commands when its hardware semaphore is + * written with a value greater than zero, and it stops processing commands + * when the semaphore returns to zero. + * + * When a channel finishes a DMA command, it will decrement its semaphore if + * the DECREMENT_SEMAPHORE bit is set in that command's flags bits. + * + * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set, + * unless it suits the purposes of the software. For example, one could + * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE + * bit set only in the last one. Then, setting the DMA channel's hardware + * semaphore to one would cause the entire series of five commands to be + * processed. However, this example would violate the invariant given above. + * + * Rule: + * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA + * channel's hardware semaphore will be decremented EVERY time a command is + * processed. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @pdesc: A pointer to the new descriptor. + */ +extern int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +/** + * mxs_dma_desc_add_list - Add a list of DMA descriptors to a channel. + * + * This function marks all the new descriptors as "ready," adds them to the end + * of the active descriptor list, and adds the length of the list to the count + * of pending descriptors. + * + * See mxs_dma_desc_append() for important rules that apply to incoming DMA + * descriptors. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list of DMA descriptors to add. + */ +extern int mxs_dma_desc_add_list(int channel, struct list_head *head); + +/** + * mxs_dma_desc_get_cooked - Retrieve processed DMA descriptors. + * + * This function moves all the descriptors from the DMA channel's "done" list to + * the head of the given list. + * + * @channel: The channel number. This is one of the globally unique DMA channel + * numbers given in mach/dma.h. + * @head: A pointer to the head of the list that will receive the + * descriptors on the "done" list. + */ +extern int mxs_dma_get_cooked(int channel, struct list_head *head); + +#endif diff --git a/arch/arm/plat-mxs/include/mach/entry-macro.S b/arch/arm/plat-mxs/include/mach/entry-macro.S new file mode 100644 index 000000000000..353a7b2cc8fd --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/entry-macro.S @@ -0,0 +1,36 @@ +/* + * Low-level IRQ helper macros for Freescale MXS-based + * + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =g_icoll_base + ldr \base, [\base] + ldr \irqnr, [\base, #0x70] + cmp \irqnr, #0x7F + moveqs \irqnr, #0 + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/arch/arm/plat-mxs/include/mach/fsl_usb.h b/arch/arm/plat-mxs/include/mach/fsl_usb.h new file mode 100644 index 000000000000..f88324856fc7 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/fsl_usb.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * USB Host side, platform-specific functionality. + */ + +#include +#include + +/* ehci_arc_hc_driver.flags value */ +#define FSL_PLATFORM_HC_FLAGS (HCD_USB2 | HCD_MEMORY) + +static void fsl_setup_phy(struct ehci_hcd *ehci, + enum fsl_usb2_phy_modes phy_mode, + int port_offset); + +static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci) +{ + struct fsl_usb2_platform_data *pdata; + + pdata = ehci_to_hcd(ehci)->self.controller->platform_data; + fsl_setup_phy(ehci, pdata->phy_mode, 0); +} + +static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd) +{ + unsigned int temp; + struct fsl_usb2_platform_data *pdata; + + pdata = hcd->self.controller->platform_data; + + if (pdata->xcvr_ops && pdata->xcvr_ops->set_host) + pdata->xcvr_ops->set_host(); + + /* set host mode */ + temp = readl(hcd->regs + UOG_USBMODE); + writel(temp | USBMODE_CM_HOST, hcd->regs + UOG_USBMODE); +} + +/* Needed for i2c/serial transceivers */ +static inline void +fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power) + pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on); +} + +/* Set USB AHB burst length for host */ +static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd) +{ +} + +void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this); +void fsl_phy_usb_utmi_uninit(struct fsl_xcvr_ops *this); +void fsl_phy_set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on); + diff --git a/arch/arm/plat-mxs/include/mach/fsl_usb_gadget.h b/arch/arm/plat-mxs/include/mach/fsl_usb_gadget.h new file mode 100644 index 000000000000..767b344d7e95 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/fsl_usb_gadget.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * USB Gadget side, platform-specific functionality. + */ + +#include + +/* Needed for i2c/serial transceivers */ +static inline void +fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_device) + pdata->xcvr_ops->set_device(); +} + +static inline void +fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(1); +} + +static inline void +fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->pullup) + pdata->xcvr_ops->pullup(0); +} diff --git a/arch/arm/plat-mxs/include/mach/gpio.h b/arch/arm/plat-mxs/include/mach/gpio.h new file mode 100644 index 000000000000..7b634149ec23 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/gpio.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include +#include + +#define GPIO_ID_NAME "gpio" +/* use gpiolib dispatchers */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq +#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START) + +struct mxs_gpio_port; +struct mxs_gpio_chip { + int (*set_dir) (struct mxs_gpio_port *, int, unsigned int); + int (*get) (struct mxs_gpio_port *, int); + void (*set) (struct mxs_gpio_port *, int, int); + unsigned int (*get_irq_stat) (struct mxs_gpio_port *); + int (*set_irq_type) (struct mxs_gpio_port *, int, unsigned int); + void (*unmask_irq) (struct mxs_gpio_port *, int); + void (*mask_irq) (struct mxs_gpio_port *, int); + void (*ack_irq) (struct mxs_gpio_port *, int); +}; + +struct mxs_gpio_port { + int id; + int irq; + int child_irq; + struct mxs_gpio_chip *chip; + struct gpio_chip port; +}; + +extern int mxs_add_gpio_port(struct mxs_gpio_port *port); + +static inline void +mxs_set_gpio_chip(struct mxs_gpio_port *port, struct mxs_gpio_chip *chip) +{ + if (port && chip) + port->chip = chip; +} + +#endif /* __ASM_ARCH_GPIO_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/hardware.h b/arch/arm/plat-mxs/include/mach/hardware.h new file mode 100644 index 000000000000..c7dd8fe1d31b --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/hardware.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_HARDWARE_H +#define __ASM_ARM_ARCH_HARDWARE_H + +#ifdef CONFIG_ARCH_MX28 +# include +# define cpu_is_mx28() 1 +# else +# define cpu_is_mx28() 0 +#endif + +#ifdef CONFIG_ARCH_MX23 +# include +# define cpu_is_mx23() 1 +# else +# define cpu_is_mx23() 0 +#endif + +#ifndef MXS_EXTEND_IRQS +#define MXS_EXTEND_IRQS 0 +#endif + +#ifndef MXS_ARCH_NR_GPIOS +#define MXS_ARCH_NR_GPIOS 160 +#endif + +#ifndef MXS_EXTEND_NR_GPIOS +#define MXS_EXTEND_NR_GPIOS 0 +#endif + +#define ARCH_NR_GPIOS (MXS_ARCH_NR_GPIOS + MXS_EXTEND_NR_GPIOS) + +#define MXS_GPIO_IRQ_START ARCH_NR_IRQS +#define MXS_EXTEND_IRQ_START (ARCH_NR_IRQS + ARCH_NR_GPIOS) + +#endif /* __ASM_ARM_ARCH_HARDWARE_H */ diff --git a/arch/arm/plat-mxs/include/mach/io.h b/arch/arm/plat-mxs/include/mach/io.h new file mode 100644 index 000000000000..7dff55ef7f12 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/io.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#define SET_REGISTER 0x4 +#define CLR_REGISTER 0x8 +#define TOG_REGISTER 0xC + +struct mxs_io_bank { + unsigned int raw; + unsigned int set; + unsigned int clr; + unsigned int tog; +}; +#endif diff --git a/arch/arm/plat-mxs/include/mach/irqs.h b/arch/arm/plat-mxs/include/mach/irqs.h new file mode 100644 index 000000000000..62165e12a60c --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/irqs.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_IRQS_H__ +#define __ASM_ARCH_IRQS_H__ + +#include + +#define NR_IRQS (ARCH_NR_IRQS + ARCH_NR_GPIOS + MXS_EXTEND_IRQS) + +#ifndef __ASSEMBLY__ +struct irq_ic_info { + unsigned int id_val; + unsigned int id_mask; + const char *name; + unsigned int base; +}; + +#define __irq_ic_info_attr __attribute__((__section__(".irq_ic_info.array"))) + +extern struct irq_ic_info *current_irq_ic_info; + +void mxs_set_irq_fiq(unsigned int irq, unsigned int type); +void mxs_enable_fiq_functionality(int enable); + +#endif + +#endif /* __ASM_ARCH_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/lradc.h b/arch/arm/plat-mxs/include/mach/lradc.h new file mode 100644 index 000000000000..c2c0a7deb0b4 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/lradc.h @@ -0,0 +1,61 @@ +/* + * Freescale STMP37XX/STMP378X LRADC helper interface + * + * Embedded Alley Solutions, Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_PLAT_LRADC_H +#define __ASM_PLAT_LRADC_H + +int hw_lradc_use_channel(int); +int hw_lradc_unuse_channel(int); +extern u32 hw_lradc_vddio(void); +void hw_lradc_set_delay_trigger_kick(int trigger, int value); +void hw_lradc_configure_channel(int channel, int enable_div2, + int enable_acc, int samples); +int hw_lradc_present(int channel); +int hw_lradc_init_ladder(int channel, int trigger, unsigned sampling); +int hw_lradc_stop_ladder(int channel, int trigger); +void hw_lradc_set_delay_trigger(int trigger, u32 trigger_lradc, + u32 delay_triggers, u32 loops, u32 delays); +void hw_lradc_clear_delay_trigger(int trigger, u32 trigger_lradc, + u32 delay_triggers); + + +#define LRADC_CH0 0 +#define LRADC_CH1 1 +#define LRADC_CH2 2 +#define LRADC_CH3 3 +#define LRADC_CH4 4 +#define LRADC_CH5 5 +#define LRADC_CH6 6 +#define LRADC_CH7 7 +#define LRADC_TOUCH_X_PLUS LRADC_CH2 +#define LRADC_TOUCH_Y_PLUS LRADC_CH3 +#define LRADC_TOUCH_X_MINUS LRADC_CH4 +#define LRADC_TOUCH_Y_MINUS LRADC_CH5 +#define VDDIO_VOLTAGE_CH LRADC_CH6 +#define BATTERY_VOLTAGE_CH LRADC_CH7 + +#define LRADC_CLOCK_6MHZ 0 +#define LRADC_CLOCK_4MHZ 1 +#define LRADC_CLOCK_3MHZ 2 +#define LRADC_CLOCK_2MHZ 3 + +#define LRADC_DELAY_TRIGGER_BUTTON 0 +#define LRADC_DELAY_TRIGGER_BATTERY 1 +#define LRADC_DELAY_TRIGGER_TOUCHSCREEN 2 +#define LRADC_DELAY_TRIGGER_DIE 3 + +#endif /* __ASM_PLAT_LRADC_H */ diff --git a/arch/arm/plat-mxs/include/mach/memory.h b/arch/arm/plat-mxs/include/mach/memory.h new file mode 100644 index 000000000000..051b1608cca4 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/memory.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include +#include + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x40000000) + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_DMA_ZONE_SIZE +#define MXS_DMA_ZONE_SIZE ((CONFIG_DMA_ZONE_SIZE * SZ_1M) >> PAGE_SHIFT) +#else +#define MXS_DMA_ZONE_SIZE ((12 * SZ_1M) >> PAGE_SHIFT) +#endif + +static inline void __arch_adjust_zones(int node, unsigned long *zone_size, + unsigned long *zhole_size) +{ + if (node != 0) + return; + /* Create separate zone to reserve memory for DMA */ + zone_size[1] = zone_size[0] - MXS_DMA_ZONE_SIZE; + zone_size[0] = MXS_DMA_ZONE_SIZE; + zhole_size[1] = zhole_size[0]; + zhole_size[0] = 0; +} + +#define arch_adjust_zones(node, size, holes) \ + __arch_adjust_zones(node, size, holes) + +#endif + +#define ISA_DMA_THRESHOLD (0x0003ffffULL) + +#define CONSISTENT_DMA_SIZE SZ_32M + +#endif diff --git a/arch/arm/plat-mxs/include/mach/pinctrl.h b/arch/arm/plat-mxs/include/mach/pinctrl.h new file mode 100644 index 000000000000..6e02149f5ca6 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/pinctrl.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARM_ARCH_PINCTRL_H +#define __ASM_ARM_ARCH_PINCTRL_H + +#include +#include + +#define PINS_PER_BANK 32 +#define GPIO_TO_PINS(gpio) ((gpio) % 32) +#define GPIO_TO_BANK(gpio) ((gpio) / 32) + +#define MXS_PIN_TO_GPIO(p) (((p) & MXS_PIN_PINID_MAX) |\ + ((((p) >> MXS_PIN_BANK_BIT) &\ + MXS_PIN_BANK_MAX) * PINS_PER_BANK)) + +#define MXS_PIN_BANK_BIT 24 +#define MXS_PIN_BANK_MAX (0x7FFFFFFF >> (MXS_PIN_BANK_BIT - 1)) +#define MXS_PIN_PINID_MAX ((1 << MXS_PIN_BANK_BIT) - 1) +#define MXS_PIN_TO_BANK(p) (((p) >> MXS_PIN_BANK_BIT) & MXS_PIN_BANK_MAX) +#define MXS_PIN_TO_PINID(p) ((p) & MXS_PIN_PINID_MAX) + +#define MXS_PIN_ENCODE(b, p) \ + ((((b) & MXS_PIN_BANK_MAX) << MXS_PIN_BANK_BIT) |\ + ((p) & MXS_PIN_PINID_MAX)) + +#define MXS_GPIO_MASK 0x7FFFFFFF +#define MXS_NON_GPIO 0x80000000 +/* + * Each pin may be routed up to four different HW interfaces + * including GPIO + */ +enum pin_fun { + PIN_FUN1 = 0, + PIN_FUN2, + PIN_FUN3, + PIN_GPIO, +}; + +/* + * Each pin may have different output drive strength in range from + * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths. + */ +enum pad_strength { + PAD_4MA = 0, + PAD_8MA, + PAD_12MA, + PAD_RESV, + PAD_CLEAR = PAD_RESV, +}; + +/* + * Each pin can be programmed for 1.8V or 3.3V + */ +enum pad_voltage { + PAD_1_8V = 0, + PAD_3_3V, +}; + +/** + * struct pin_desc - Describes the configuration of a pin. + * + * @name: A human-readable name that identifies the pin. + * @id: A number that identifies the pin (use a macro from a chip- + * specific header file -- e.g., "PINID_PWM0"). + * @fun: The function for which to configure this pin. + * @strength: The drive strength for this pin. Note that this field should be + * ignored and the driver hardware should *not* be configured if the + * "drive" field is not set. + * @voltage: The voltage rail for this pin. Note that this field should be + * ignored and the driver hardware should *not* be configured if the + * "drive" field is not set. + * @pullup: If set, indicates whether the pullup is enabled. Note that this + * field should be ignored and the pullup should *not* be configured + * if the "pull" field is not set. + * @drive: If set, indicates that the driver hardware for this pin should be + * configured. This field does *not* indicate *how* the driver + * hardware should be configured -- only whether or not it should + * be. See the "strength" and "voltage" fields for information about + * how to configure the driver hardware. + * @pull: If set, indicates that the pullup for this pin should be + * configured. This field does *not* indicate *how* the pullup + * should be configured -- only whether or not it should be. See the + * "pullup" field for information about how to configure the pullup. + * @input: For GPIO pins only, this indicates whether the pin is an input. + * @data: The data field is used when the pin is configured to GPIO output + * mode. When data is 0, the pin's output will be 0. + */ +struct pin_desc { + char *name; + unsigned int id; + enum pin_fun fun; + enum pad_strength strength; + enum pad_voltage voltage; + unsigned pullup:1; + unsigned drive:1; + unsigned pull:1; + unsigned output:1; + unsigned data:1; +}; + +struct pin_bank { + const char *label[sizeof(long) * 8]; + unsigned long id; + struct pinctrl_chip *chip; + unsigned long bitmap; + unsigned long gpio_port; +}; + +struct pinctrl_chip { + char *name; + unsigned int nouse; + unsigned int bank_size; + struct pin_bank *banks; + /* OPS */ + int (*pin2id) (struct pinctrl_chip *, unsigned int, unsigned int *); + unsigned int (*get_gpio) (struct pin_bank *, unsigned int); + void (*set_strength) (struct pin_bank *, unsigned int, + enum pad_strength); + void (*set_voltage) (struct pin_bank *, unsigned int, enum pad_voltage); + void (*set_pullup) (struct pin_bank *, unsigned int, int); + void (*set_type) (struct pin_bank *, unsigned int, enum pin_fun); + int (*get_type) (struct pin_bank *, unsigned int); +}; + +extern int __init mxs_set_pinctrl_chip(struct pinctrl_chip *); + +extern unsigned int mxs_pin2gpio(unsigned int); +extern int mxs_request_pin(unsigned int, enum pin_fun, const char *); +extern int mxs_set_type(unsigned int, enum pin_fun, const char *); +extern int mxs_get_type(unsigned int); +extern int mxs_set_strength(unsigned int, enum pad_strength, const char *); +extern int mxs_set_voltage(unsigned int, enum pad_voltage, const char *); +extern int mxs_set_pullup(unsigned int, int, const char *); +extern void mxs_release_pin(unsigned int, const char *); +#endif diff --git a/arch/arm/plat-mxs/include/mach/power.h b/arch/arm/plat-mxs/include/mach/power.h new file mode 100644 index 000000000000..28ee9fa2696d --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/power.h @@ -0,0 +1,64 @@ +/* + * Freescale MXS voltage regulator structure declarations + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __VOLTAGE_H +#define __VOLTAGE_H +#include +#include + +struct mxs_regulator { + struct regulator_desc regulator; + struct mxs_regulator *parent; + struct mxs_platform_regulator_data *rdata; + struct completion done; + + spinlock_t lock; + wait_queue_head_t wait_q; + struct notifier_block nb; + + int mode; + int cur_voltage; + int cur_current; + int next_current; +}; + + +struct mxs_platform_regulator_data { + char name[80]; + char *parent_name; + int (*reg_register)(struct mxs_regulator *sreg); + int (*set_voltage)(struct mxs_regulator *sreg, int uv); + int (*get_voltage)(struct mxs_regulator *sreg); + int (*set_current)(struct mxs_regulator *sreg, int uA); + int (*get_current)(struct mxs_regulator *sreg); + int (*enable)(struct mxs_regulator *sreg); + int (*disable)(struct mxs_regulator *sreg); + int (*is_enabled)(struct mxs_regulator *sreg); + int (*set_mode)(struct mxs_regulator *sreg, int mode); + int (*get_mode)(struct mxs_regulator *sreg); + int (*get_optimum_mode)(struct mxs_regulator *sreg, + int input_uV, int output_uV, int load_uA); + u32 control_reg; + int min_voltage; + int max_voltage; + int max_current; + struct regulation_constraints *cnstraints; +}; + +int mxs_register_regulator( + struct mxs_regulator *reg_data, int reg, + struct regulator_init_data *initdata); + +#endif /* __VOLTAGE_H */ diff --git a/arch/arm/plat-mxs/include/mach/system.h b/arch/arm/plat-mxs/include/mach/system.h new file mode 100644 index 000000000000..faaa2ff3cf13 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/system.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_SYSTEM_H__ +#define __ASM_ARCH_SYSTEM_H__ + +extern void arch_idle(void); + +void arch_reset(char mode, const char *cmd); +extern void (*machine_arch_reset)(char mode, const char *cmd); +int mxs_reset_block(void __iomem *hwreg, int just_enable); +int get_evk_board_version(void); + +#endif /* __ASM_ARCH_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/timex.h b/arch/arm/plat-mxs/include/mach/timex.h new file mode 100644 index 000000000000..d622dda141f2 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/timex.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * System time clock is sourced from the 32k clock + */ +#define CLOCK_TICK_RATE 32000 diff --git a/arch/arm/plat-mxs/include/mach/uncompress.h b/arch/arm/plat-mxs/include/mach/uncompress.h new file mode 100644 index 000000000000..fd4e4f845472 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/uncompress.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_PLAT_UNCOMPRESS_H +#define __ASM_PLAT_UNCOMPRESS_H + +#include + +/* + * Register includes are for when the MMU enabled; we need to define our + * own stuff here for pre-MMU use + */ +#define UART_PORT_BASE DUART_PHYS_ADDR +#define UART(c) (((volatile unsigned *)UART_PORT_BASE)[c]) + +/* + * This does not append a newline + */ +static void putc(char c) +{ + /* Wait for TX fifo empty */ + while ((UART(6) & (1 << 7)) == 0) + continue; + + /* Write byte */ + UART(0) = c; + + /* Wait for last bit to exit the UART */ + while (UART(6) & (1 << 3)) + continue; +} + +#define flush() do { } while (0) +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() + +#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-mxs/include/mach/unique-id.h b/arch/arm/plat-mxs/include/mach/unique-id.h new file mode 100644 index 000000000000..de5e04342ef5 --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/unique-id.h @@ -0,0 +1,30 @@ +/* + * Unique ID interface for ID storage providers + * + * Embedded Alley Solutions, Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __UNIQUE_ID_H +#define __UNIQUE_ID_H + +struct uid_ops { + ssize_t (*id_show)(void *context, char *page, int ascii); + ssize_t (*id_store)(void *context, const char *page, + size_t count, int ascii); +}; + +struct kobject *uid_provider_init(const char *name, + struct uid_ops *ops, void *context); +void uid_provider_remove(const char *name); +#endif diff --git a/arch/arm/plat-mxs/include/mach/vmalloc.h b/arch/arm/plat-mxs/include/mach/vmalloc.h new file mode 100644 index 000000000000..cc6d5cf3133a --- /dev/null +++ b/arch/arm/plat-mxs/include/mach/vmalloc.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#define VMALLOC_END (0xF0000000) diff --git a/arch/arm/plat-mxs/iram.c b/arch/arm/plat-mxs/iram.c new file mode 100644 index 000000000000..c63b0a2a9a10 --- /dev/null +++ b/arch/arm/plat-mxs/iram.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include + +static unsigned long iram_phys_base; +static __iomem void *iram_virt_base; +static struct gen_pool *iram_pool; + +#define iram_phys_to_virt(p) (iram_virt_base + ((p) - iram_phys_base)) + +void *iram_alloc(unsigned int size, unsigned long *dma_addr) +{ + if (!iram_pool) + return NULL; + + *dma_addr = gen_pool_alloc(iram_pool, size); + pr_debug("iram alloc - %dB@0x%p\n", size, (void *)*dma_addr); + + WARN_ON(!*dma_addr); + if (!*dma_addr) + return NULL; + + return iram_phys_to_virt(*dma_addr); +} +EXPORT_SYMBOL(iram_alloc); + +void iram_free(unsigned long addr, unsigned int size) +{ + if (!iram_pool) + return; + + gen_pool_free(iram_pool, addr, size); +} +EXPORT_SYMBOL(iram_free); + +int __init iram_init(unsigned long base, unsigned long size) +{ + iram_phys_base = base; + + iram_pool = gen_pool_create(12, -1); + gen_pool_add(iram_pool, base, size, -1); + iram_virt_base = ioremap(iram_phys_base, size); + + pr_info("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base); + return 0; +} diff --git a/arch/arm/plat-mxs/lradc.c b/arch/arm/plat-mxs/lradc.c new file mode 100644 index 000000000000..3d9089e3ef25 --- /dev/null +++ b/arch/arm/plat-mxs/lradc.c @@ -0,0 +1,385 @@ +/* + * Freescale STMP37XX/STMP378X LRADC helper routines + * + * Embedded Alley Solutions, Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct lradc_device { + struct sys_device sys; + unsigned int base; + unsigned int vddio_voltage; + unsigned int battery_voltage; +}; + +static int channels[8]; + +static __refdata struct lradc_device mxs_lradc; + +int hw_lradc_use_channel(int channel) +{ + if (channel < 0 || channel > 7) + return -EINVAL; + channels[channel]++; + return 0; +} +EXPORT_SYMBOL(hw_lradc_use_channel); + +int hw_lradc_unuse_channel(int channel) +{ + if (channel < 0 || channel > 7) + return -EINVAL; + channels[channel]--; + return 0; +} +EXPORT_SYMBOL(hw_lradc_unuse_channel); + +void hw_lradc_reinit(int enable_ground_ref, unsigned freq) +{ + __raw_writel(BM_LRADC_CTRL0_SFTRST, + mxs_lradc.base + HW_LRADC_CTRL0_SET); + udelay(1); + __raw_writel(BM_LRADC_CTRL0_SFTRST, + mxs_lradc.base + HW_LRADC_CTRL0_CLR); + + /* Clear the Clock Gate for normal operation */ + __raw_writel(BM_LRADC_CTRL0_CLKGATE, + mxs_lradc.base + HW_LRADC_CTRL0_CLR); + + if (enable_ground_ref) + __raw_writel(BM_LRADC_CTRL0_ONCHIP_GROUNDREF, + mxs_lradc.base + HW_LRADC_CTRL0_SET); + else + __raw_writel(BM_LRADC_CTRL0_ONCHIP_GROUNDREF, + mxs_lradc.base + HW_LRADC_CTRL0_CLR); + + __raw_writel(BM_LRADC_CTRL3_CYCLE_TIME, + mxs_lradc.base + HW_LRADC_CTRL3_CLR); + __raw_writel(BF_LRADC_CTRL3_CYCLE_TIME(freq), + mxs_lradc.base + HW_LRADC_CTRL3_SET); + + __raw_writel(BM_LRADC_CTRL4_LRADC6SELECT | BM_LRADC_CTRL4_LRADC7SELECT, + mxs_lradc.base + HW_LRADC_CTRL4_CLR); + __raw_writel(BF_LRADC_CTRL4_LRADC6SELECT(mxs_lradc.vddio_voltage), + mxs_lradc.base + HW_LRADC_CTRL4_SET); + __raw_writel(BF_LRADC_CTRL4_LRADC7SELECT(mxs_lradc.battery_voltage), + mxs_lradc.base + HW_LRADC_CTRL4_SET); +} + +int hw_lradc_init_ladder(int channel, int trigger, unsigned sampling) +{ + /* + * check if the lradc channel is present in this product + */ + if (!hw_lradc_present(channel)) + return -ENODEV; + + hw_lradc_configure_channel(channel, !0 /* div2 */ , + 0 /* acc */ , + 0 /* num_samples */); + + /* Setup the trigger loop forever */ + hw_lradc_set_delay_trigger(trigger, 1 << channel, + 1 << trigger, 0, sampling); + + /* Clear the accumulator & NUM_SAMPLES */ + __raw_writel(0xFFFFFFFF, mxs_lradc.base + HW_LRADC_CHn_CLR(channel)); + return 0; +} + +EXPORT_SYMBOL(hw_lradc_init_ladder); + +int hw_lradc_stop_ladder(int channel, int trigger) +{ + /* + * check if the lradc channel is present in this product + */ + if (!hw_lradc_present(channel)) + return -ENODEV; + hw_lradc_clear_delay_trigger(trigger, 1 << channel, 1 << trigger); + return 0; +} + +EXPORT_SYMBOL(hw_lradc_stop_ladder); + +int hw_lradc_present(int channel) +{ + if (channel < 0 || channel > 7) + return 0; + return __raw_readl(mxs_lradc.base + HW_LRADC_STATUS) + & (1 << (16 + channel)); +} + +EXPORT_SYMBOL(hw_lradc_present); + +void hw_lradc_configure_channel(int channel, int enable_div2, + int enable_acc, int samples) +{ + if (enable_div2) + __raw_writel(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1 << channel), + mxs_lradc.base + HW_LRADC_CTRL2_SET); + else + __raw_writel(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1 << channel), + mxs_lradc.base + HW_LRADC_CTRL2_CLR); + + /* Clear the accumulator & NUM_SAMPLES */ + __raw_writel(0xFFFFFFFF, mxs_lradc.base + HW_LRADC_CHn_CLR(channel)); + + /* Sets NUM_SAMPLES bitfield of HW_LRADC_CHn register. */ + __raw_writel(BM_LRADC_CHn_NUM_SAMPLES, + mxs_lradc.base + HW_LRADC_CHn_CLR(channel)); + __raw_writel(BF_LRADC_CHn_NUM_SAMPLES(samples), + mxs_lradc.base + HW_LRADC_CHn_SET(channel)); + + if (enable_acc) + __raw_writel(BM_LRADC_CHn_ACCUMULATE, + mxs_lradc.base + HW_LRADC_CHn_SET(channel)); + else + __raw_writel(BM_LRADC_CHn_ACCUMULATE, + mxs_lradc.base + HW_LRADC_CHn_CLR(channel)); +} + +EXPORT_SYMBOL(hw_lradc_configure_channel); + +void hw_lradc_set_delay_trigger(int trigger, u32 trigger_lradc, + u32 delay_triggers, u32 loops, u32 delays) +{ + /* set TRIGGER_LRADCS in HW_LRADC_DELAYn */ + __raw_writel(BF_LRADC_DELAYn_TRIGGER_LRADCS(trigger_lradc), + mxs_lradc.base + HW_LRADC_DELAYn_SET(trigger)); + __raw_writel(BF_LRADC_DELAYn_TRIGGER_DELAYS(delay_triggers), + mxs_lradc.base + HW_LRADC_DELAYn_SET(trigger)); + + __raw_writel(BM_LRADC_DELAYn_LOOP_COUNT | BM_LRADC_DELAYn_DELAY, + mxs_lradc.base + HW_LRADC_DELAYn_CLR(trigger)); + __raw_writel(BF_LRADC_DELAYn_LOOP_COUNT(loops), + mxs_lradc.base + HW_LRADC_DELAYn_SET(trigger)); + __raw_writel(BF_LRADC_DELAYn_DELAY(delays), + mxs_lradc.base + HW_LRADC_DELAYn_SET(trigger)); +} + +EXPORT_SYMBOL(hw_lradc_set_delay_trigger); + +void hw_lradc_clear_delay_trigger(int trigger, u32 trigger_lradc, + u32 delay_triggers) +{ + __raw_writel(BF_LRADC_DELAYn_TRIGGER_LRADCS(trigger_lradc), + mxs_lradc.base + HW_LRADC_DELAYn_CLR(trigger)); + __raw_writel(BF_LRADC_DELAYn_TRIGGER_DELAYS(delay_triggers), + mxs_lradc.base + HW_LRADC_DELAYn_CLR(trigger)); +} + +EXPORT_SYMBOL(hw_lradc_clear_delay_trigger); + +void hw_lradc_set_delay_trigger_kick(int trigger, int value) +{ + if (value) + __raw_writel(BM_LRADC_DELAYn_KICK, + mxs_lradc.base + HW_LRADC_DELAYn_SET(trigger)); + else + __raw_writel(BM_LRADC_DELAYn_KICK, + mxs_lradc.base + HW_LRADC_DELAYn_CLR(trigger)); +} + +EXPORT_SYMBOL(hw_lradc_set_delay_trigger_kick); + +u32 hw_lradc_vddio(void) +{ + /* Clear the Soft Reset and Clock Gate for normal operation */ + __raw_writel(BM_LRADC_CTRL0_SFTRST | BM_LRADC_CTRL0_CLKGATE, + mxs_lradc.base + HW_LRADC_CTRL0_CLR); + + /* + * Clear the divide by two for channel 6 since + * it has a HW divide-by-two built in. + */ + __raw_writel(BF_LRADC_CTRL2_DIVIDE_BY_TWO(1 << VDDIO_VOLTAGE_CH), + mxs_lradc.base + HW_LRADC_CTRL2_CLR); + + /* Clear the accumulator & NUM_SAMPLES */ + __raw_writel(0xFFFFFFFF, + mxs_lradc.base + HW_LRADC_CHn_CLR(VDDIO_VOLTAGE_CH)); + + /* Clear the interrupt flag */ + __raw_writel(BM_LRADC_CTRL1_LRADC6_IRQ, + mxs_lradc.base + HW_LRADC_CTRL1_CLR); + + /* + * Get VddIO; this is the max scale value for the button resistor + * ladder. + * schedule ch 6: + */ + __raw_writel(BF_LRADC_CTRL0_SCHEDULE(1 << VDDIO_VOLTAGE_CH), + mxs_lradc.base + HW_LRADC_CTRL0_SET); + + /* wait for completion */ + while ((__raw_readl(mxs_lradc.base + HW_LRADC_CTRL1) + & BM_LRADC_CTRL1_LRADC6_IRQ) != BM_LRADC_CTRL1_LRADC6_IRQ) + cpu_relax(); + + /* Clear the interrupt flag */ + __raw_writel(BM_LRADC_CTRL1_LRADC6_IRQ, + mxs_lradc.base + HW_LRADC_CTRL1_CLR); + + /* read ch 6 value. */ + return __raw_readl(mxs_lradc.base + HW_LRADC_CHn(VDDIO_VOLTAGE_CH)) & + BM_LRADC_CHn_VALUE; +} + +EXPORT_SYMBOL(hw_lradc_vddio); + +#ifdef CONFIG_PM +static u32 lradc_registers[0x16]; +static int do_gate; + +static int hw_lradc_suspend(struct sys_device *dev, pm_message_t state) +{ + int i; + + do_gate = 1; + for (i = 0; i < ARRAY_SIZE(channels); i++) + if (channels[i] > 0) { + do_gate = 0; + break; + } + + for (i = 0; i < ARRAY_SIZE(lradc_registers); i++) + lradc_registers[i] = __raw_readl(mxs_lradc.base + (i << 4)); + + if (do_gate) + __raw_writel(BM_LRADC_CTRL0_CLKGATE, + mxs_lradc.base + HW_LRADC_CTRL0_SET); + return 0; +} + +static int hw_lradc_resume(struct sys_device *dev) +{ + int i; + + if (do_gate) { + __raw_writel(BM_LRADC_CTRL0_SFTRST, + mxs_lradc.base + HW_LRADC_CTRL0_SET); + udelay(10); + __raw_writel(BM_LRADC_CTRL0_SFTRST | + BM_LRADC_CTRL0_CLKGATE, + mxs_lradc.base + HW_LRADC_CTRL0_CLR); + } + for (i = 0; i < ARRAY_SIZE(lradc_registers); i++) + __raw_writel(lradc_registers[i], mxs_lradc.base + (i << 4)); + return 0; +} + +#endif + +static struct sysdev_class mxs_lradc_sysclass = { + .name = "mxs-lradc", +#ifdef CONFIG_PM + .suspend = hw_lradc_suspend, + .resume = hw_lradc_resume, +#endif +}; + +static int lradc_freq = LRADC_CLOCK_6MHZ; + +static int __init lradc_freq_setup(char *str) +{ + long freq; + + if (strict_strtol(str, 0, &freq) < 0) + return 0; + + if (freq < 0) + return 0; + if (freq >= 6) + lradc_freq = LRADC_CLOCK_6MHZ; + else if (freq >= 4) + lradc_freq = LRADC_CLOCK_4MHZ; + else if (freq >= 3) + lradc_freq = LRADC_CLOCK_3MHZ; + else if (freq >= 2) + lradc_freq = LRADC_CLOCK_2MHZ; + else + return 0; + return 1; +} + +__setup("lradc_freq=", lradc_freq_setup); + +static int __devinit mxs_lradc_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mxs_lradc_plat_data *plat_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -ENODEV; + + plat_data = (struct mxs_lradc_plat_data *)(pdev->dev.platform_data); + if (plat_data == NULL) + return -EFAULT; + + mxs_lradc.base = (unsigned int)IO_ADDRESS(res->start); + mxs_lradc.sys.id = -1; + mxs_lradc.sys.cls = &mxs_lradc_sysclass; + mxs_lradc.vddio_voltage = plat_data->vddio_voltage; + mxs_lradc.battery_voltage = plat_data->battery_voltage; + hw_lradc_reinit(0, lradc_freq); + return sysdev_register(&mxs_lradc.sys); +} + +static int __devexit mxs_lradc_remove(struct platform_device *pdev) +{ + sysdev_unregister(&mxs_lradc.sys); + return 0; +} + +static __refdata struct platform_driver mxs_lradc_drv = { + .probe = mxs_lradc_probe, + .remove = __devexit_p(mxs_lradc_remove), + .driver = { + .name = "mxs-lradc", + .owner = THIS_MODULE, + } +}; + +static int __init hw_lradc_init(void) +{ + sysdev_class_register(&mxs_lradc_sysclass); + platform_driver_register(&mxs_lradc_drv); + return 0; +} + +static void __exit hw_lradc_exit(void) +{ + platform_driver_unregister(&mxs_lradc_drv); + sysdev_class_unregister(&mxs_lradc_sysclass); +} + +subsys_initcall(hw_lradc_init); +module_exit(hw_lradc_exit); diff --git a/arch/arm/plat-mxs/pinctrl.c b/arch/arm/plat-mxs/pinctrl.c new file mode 100644 index 000000000000..cdef3e02d495 --- /dev/null +++ b/arch/arm/plat-mxs/pinctrl.c @@ -0,0 +1,215 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +static struct pinctrl_chip *g_chip; + +int mxs_request_pin(unsigned int pin, enum pin_fun fun, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + if (test_and_set_bit(index, &pb->bitmap)) + return -EBUSY; + pb->label[index] = lab; + if (g_chip->set_type) + g_chip->set_type(pb, index, fun); + return 0; +} +EXPORT_SYMBOL(mxs_request_pin); + +int mxs_get_type(unsigned int pin) +{ + int bank, index; + struct pin_bank *pb; + int ret = 0; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + if (g_chip->get_type) + ret = g_chip->get_type(pb, index); + return ret; +} +EXPORT_SYMBOL(mxs_get_type); + +int mxs_set_type(unsigned int pin, enum pin_fun fun, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return -ENOLCK; + if (lab != pb->label[index]) /* label is const string */ + return -EINVAL; + if (g_chip->set_type) + g_chip->set_type(pb, index, fun); + return 0; +} +EXPORT_SYMBOL(mxs_set_type); + +int mxs_set_strength(unsigned int pin, enum pad_strength cfg, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return -ENOLCK; + if (lab != pb->label[index]) /* label is const string */ + return -EINVAL; + if (g_chip->set_strength) + g_chip->set_strength(pb, index, cfg); + return 0; +} +EXPORT_SYMBOL(mxs_set_strength); + +int mxs_set_voltage(unsigned int pin, enum pad_voltage cfg, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return -ENOLCK; + if (lab != pb->label[index]) /* label is const string */ + return -EINVAL; + if (g_chip->set_voltage) + g_chip->set_voltage(pb, index, cfg); + return 0; +} +EXPORT_SYMBOL(mxs_set_voltage); + +int mxs_set_pullup(unsigned int pin, int en, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return -ENOLCK; + if (lab != pb->label[index]) /* label is const string */ + return -EINVAL; + if (g_chip->set_pullup) + g_chip->set_pullup(pb, index, en); + return 0; +} +EXPORT_SYMBOL(mxs_set_pullup); + +void mxs_release_pin(unsigned int pin, const char *lab) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return; + + pb = g_chip->banks + bank; + + if (!test_bit(index, &pb->bitmap)) + return; + if (lab != pb->label[index]) /* label is const string */ + return; + pb->label[index] = NULL; + + clear_bit(index, &pb->bitmap); +} +EXPORT_SYMBOL(mxs_release_pin); + +unsigned int mxs_pin2gpio(unsigned int pin) +{ + int bank, index; + struct pin_bank *pb; + if (g_chip == NULL) + return -ENODEV; + + if (!g_chip->get_gpio) + return -ENODEV; + + bank = g_chip->pin2id(g_chip, pin, &index); + if (bank < 0 || index < 0 || bank >= g_chip->bank_size) + return -EFAULT; + + pb = g_chip->banks + bank; + + return g_chip->get_gpio(pb, index); +} + +int __init mxs_set_pinctrl_chip(struct pinctrl_chip *chip) +{ + if (!(chip && chip->banks && chip->bank_size && + chip->get_gpio && chip->pin2id)) + return -EINVAL; + + if (g_chip) + return -EEXIST; + g_chip = chip; + return 0; +}; diff --git a/arch/arm/plat-mxs/regs-apbx.h b/arch/arm/plat-mxs/regs-apbx.h new file mode 100644 index 000000000000..f788f1303ece --- /dev/null +++ b/arch/arm/plat-mxs/regs-apbx.h @@ -0,0 +1,433 @@ +/* + * Freescale APBX Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.30 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___APBX_H +#define __ARCH_ARM___APBX_H + +#define HW_APBX_CTRL0 (0x00000000) +#define HW_APBX_CTRL0_SET (0x00000004) +#define HW_APBX_CTRL0_CLR (0x00000008) +#define HW_APBX_CTRL0_TOG (0x0000000c) + +#define BM_APBX_CTRL0_SFTRST 0x80000000 +#define BM_APBX_CTRL0_CLKGATE 0x40000000 +#define BP_APBX_CTRL0_RSVD0 0 +#define BM_APBX_CTRL0_RSVD0 0x3FFFFFFF +#define BF_APBX_CTRL0_RSVD0(v) \ + (((v) << 0) & BM_APBX_CTRL0_RSVD0) + +#define HW_APBX_CTRL1 (0x00000010) +#define HW_APBX_CTRL1_SET (0x00000014) +#define HW_APBX_CTRL1_CLR (0x00000018) +#define HW_APBX_CTRL1_TOG (0x0000001c) + +#define BM_APBX_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBX_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBX_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBX_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBX_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBX_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBX_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBX_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBX_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBX_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBX_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBX_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBX_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBX_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBX_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBX_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBX_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBX_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBX_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBX_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBX_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBX_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBX_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBX_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBX_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBX_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBX_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBX_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBX_CTRL2 (0x00000020) +#define HW_APBX_CTRL2_SET (0x00000024) +#define HW_APBX_CTRL2_CLR (0x00000028) +#define HW_APBX_CTRL2_TOG (0x0000002c) + +#define BM_APBX_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBX_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBX_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBX_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBX_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBX_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBX_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBX_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBX_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBX_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBX_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBX_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBX_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBX_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBX_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBX_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBX_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBX_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBX_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBX_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBX_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBX_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBX_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBX_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBX_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBX_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBX_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBX_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBX_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBX_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBX_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBX_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBX_CHANNEL_CTRL (0x00000030) +#define HW_APBX_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBX_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBX_CHANNEL_CTRL_TOG (0x0000003c) + +#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBX_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART4_RX 0x0001 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART4_TX 0x0002 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX 0x0004 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF0 0x0010 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1 0x0020 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C0 0x0040 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C1 0x0080 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX 0x0100 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX 0x0200 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX 0x0400 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX 0x0800 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART2_RX 0x1000 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART2_TX 0x2000 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART3_RX 0x4000 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART3_TX 0x8000 +#define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART4_RX 0x0001 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART4_TX 0x0002 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX 0x0004 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF0 0x0010 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1 0x0020 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C0 0x0040 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C1 0x0080 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX 0x0100 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX 0x0200 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX 0x0400 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX 0x0800 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART2_RX 0x1000 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART2_TX 0x2000 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART3_RX 0x4000 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART3_TX 0x8000 + +#define HW_APBX_DEVSEL (0x00000040) +#define HW_APBX_DEVSEL_SET (0x00000044) +#define HW_APBX_DEVSEL_CLR (0x00000048) +#define HW_APBX_DEVSEL_TOG (0x0000004c) + +#define BP_APBX_DEVSEL_CH15 30 +#define BM_APBX_DEVSEL_CH15 0xC0000000 +#define BF_APBX_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBX_DEVSEL_CH15) +#define BP_APBX_DEVSEL_CH14 28 +#define BM_APBX_DEVSEL_CH14 0x30000000 +#define BF_APBX_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBX_DEVSEL_CH14) +#define BP_APBX_DEVSEL_CH13 26 +#define BM_APBX_DEVSEL_CH13 0x0C000000 +#define BF_APBX_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBX_DEVSEL_CH13) +#define BP_APBX_DEVSEL_CH12 24 +#define BM_APBX_DEVSEL_CH12 0x03000000 +#define BF_APBX_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBX_DEVSEL_CH12) +#define BP_APBX_DEVSEL_CH11 22 +#define BM_APBX_DEVSEL_CH11 0x00C00000 +#define BF_APBX_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBX_DEVSEL_CH11) +#define BP_APBX_DEVSEL_CH10 20 +#define BM_APBX_DEVSEL_CH10 0x00300000 +#define BF_APBX_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBX_DEVSEL_CH10) +#define BP_APBX_DEVSEL_CH9 18 +#define BM_APBX_DEVSEL_CH9 0x000C0000 +#define BF_APBX_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBX_DEVSEL_CH9) +#define BP_APBX_DEVSEL_CH8 16 +#define BM_APBX_DEVSEL_CH8 0x00030000 +#define BF_APBX_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBX_DEVSEL_CH8) +#define BP_APBX_DEVSEL_CH7 14 +#define BM_APBX_DEVSEL_CH7 0x0000C000 +#define BF_APBX_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBX_DEVSEL_CH7) +#define BP_APBX_DEVSEL_CH6 12 +#define BM_APBX_DEVSEL_CH6 0x00003000 +#define BF_APBX_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBX_DEVSEL_CH6) +#define BP_APBX_DEVSEL_CH5 10 +#define BM_APBX_DEVSEL_CH5 0x00000C00 +#define BF_APBX_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBX_DEVSEL_CH5) +#define BP_APBX_DEVSEL_CH4 8 +#define BM_APBX_DEVSEL_CH4 0x00000300 +#define BF_APBX_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBX_DEVSEL_CH4) +#define BP_APBX_DEVSEL_CH3 6 +#define BM_APBX_DEVSEL_CH3 0x000000C0 +#define BF_APBX_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBX_DEVSEL_CH3) +#define BP_APBX_DEVSEL_CH2 4 +#define BM_APBX_DEVSEL_CH2 0x00000030 +#define BF_APBX_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBX_DEVSEL_CH2) +#define BP_APBX_DEVSEL_CH1 2 +#define BM_APBX_DEVSEL_CH1 0x0000000C +#define BF_APBX_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBX_DEVSEL_CH1) +#define BP_APBX_DEVSEL_CH0 0 +#define BM_APBX_DEVSEL_CH0 0x00000003 +#define BF_APBX_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBX_DEVSEL_CH0) + +/* + * multi-register-define name HW_APBX_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define BP_APBX_CHn_CMD_XFER_COUNT 16 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBX_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT) +#define BP_APBX_CHn_CMD_CMDWORDS 12 +#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBX_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS) +#define BP_APBX_CHn_CMD_RSVD1 10 +#define BM_APBX_CHn_CMD_RSVD1 0x00000C00 +#define BF_APBX_CHn_CMD_RSVD1(v) \ + (((v) << 10) & BM_APBX_CHn_CMD_RSVD1) +#define BM_APBX_CHn_CMD_TERMINATEFLUSH 0x00000200 +#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 +#define BP_APBX_CHn_CMD_RSVD0 4 +#define BM_APBX_CHn_CMD_RSVD0 0x00000030 +#define BF_APBX_CHn_CMD_RSVD0(v) \ + (((v) << 4) & BM_APBX_CHn_CMD_RSVD0) +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBX_CHn_CMD_CHAIN 0x00000004 +#define BP_APBX_CHn_CMD_COMMAND 0 +#define BM_APBX_CHn_CMD_COMMAND 0x00000003 +#define BF_APBX_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBX_CHn_CMD_COMMAND) +#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 + +/* + * multi-register-define name HW_APBX_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define BP_APBX_CHn_BAR_ADDRESS 0 +#define BM_APBX_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBX_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define BP_APBX_CHn_SEMA_RSVD2 24 +#define BM_APBX_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBX_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBX_CHn_SEMA_RSVD2) +#define BP_APBX_CHn_SEMA_PHORE 16 +#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBX_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBX_CHn_SEMA_PHORE) +#define BP_APBX_CHn_SEMA_RSVD1 8 +#define BM_APBX_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBX_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBX_CHn_SEMA_RSVD1) +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBX_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define BM_APBX_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBX_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBX_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBX_CHn_DEBUG1_END 0x10000000 +#define BP_APBX_CHn_DEBUG1_RSVD2 25 +#define BM_APBX_CHn_DEBUG1_RSVD2 0x0E000000 +#define BF_APBX_CHn_DEBUG1_RSVD2(v) \ + (((v) << 25) & BM_APBX_CHn_DEBUG1_RSVD2) +#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBX_CHn_DEBUG1_RSVD1 5 +#define BM_APBX_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBX_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBX_CHn_DEBUG1_RSVD1) +#define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBX_CHn_DEBUG1_STATEMACHINE) +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E + +/* + * multi-register-define name HW_APBX_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define BP_APBX_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBX_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBX_CHn_DEBUG2_APB_BYTES) +#define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBX_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBX_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBX_VERSION (0x00000800) + +#define BP_APBX_VERSION_MAJOR 24 +#define BM_APBX_VERSION_MAJOR 0xFF000000 +#define BF_APBX_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBX_VERSION_MAJOR) +#define BP_APBX_VERSION_MINOR 16 +#define BM_APBX_VERSION_MINOR 0x00FF0000 +#define BF_APBX_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBX_VERSION_MINOR) +#define BP_APBX_VERSION_STEP 0 +#define BM_APBX_VERSION_STEP 0x0000FFFF +#define BF_APBX_VERSION_STEP(v) \ + (((v) << 0) & BM_APBX_VERSION_STEP) +#endif /* __ARCH_ARM___APBX_H */ diff --git a/arch/arm/plat-mxs/regs-icoll.h b/arch/arm/plat-mxs/regs-icoll.h new file mode 100644 index 000000000000..f06ac0d4720b --- /dev/null +++ b/arch/arm/plat-mxs/regs-icoll.h @@ -0,0 +1,293 @@ +/* + * Freescale ICOLL Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.50 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___ICOLL_H +#define __ARCH_ARM___ICOLL_H + +#define HW_ICOLL_VECTOR (0x00000000) +#define HW_ICOLL_VECTOR_SET (0x00000004) +#define HW_ICOLL_VECTOR_CLR (0x00000008) +#define HW_ICOLL_VECTOR_TOG (0x0000000c) + +#define BP_ICOLL_VECTOR_IRQVECTOR 2 +#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC +#define BF_ICOLL_VECTOR_IRQVECTOR(v) \ + (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR) +#define BP_ICOLL_VECTOR_RSRVD1 0 +#define BM_ICOLL_VECTOR_RSRVD1 0x00000003 +#define BF_ICOLL_VECTOR_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VECTOR_RSRVD1) + +#define HW_ICOLL_LEVELACK (0x00000010) + +#define BP_ICOLL_LEVELACK_RSRVD1 4 +#define BM_ICOLL_LEVELACK_RSRVD1 0xFFFFFFF0 +#define BF_ICOLL_LEVELACK_RSRVD1(v) \ + (((v) << 4) & BM_ICOLL_LEVELACK_RSRVD1) +#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 +#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F +#define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \ + (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK) +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 + +#define HW_ICOLL_CTRL (0x00000020) +#define HW_ICOLL_CTRL_SET (0x00000024) +#define HW_ICOLL_CTRL_CLR (0x00000028) +#define HW_ICOLL_CTRL_TOG (0x0000002c) + +#define BM_ICOLL_CTRL_SFTRST 0x80000000 +#define BV_ICOLL_CTRL_SFTRST__RUN 0x0 +#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 +#define BM_ICOLL_CTRL_CLKGATE 0x40000000 +#define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 +#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 +#define BP_ICOLL_CTRL_RSRVD3 24 +#define BM_ICOLL_CTRL_RSRVD3 0x3F000000 +#define BF_ICOLL_CTRL_RSRVD3(v) \ + (((v) << 24) & BM_ICOLL_CTRL_RSRVD3) +#define BP_ICOLL_CTRL_VECTOR_PITCH 21 +#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000 +#define BF_ICOLL_CTRL_VECTOR_PITCH(v) \ + (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH) +#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 +#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000 +#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 +#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 +#define BM_ICOLL_CTRL_NO_NESTING 0x00080000 +#define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 +#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 +#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000 +#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 +#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 +#define BP_ICOLL_CTRL_RSRVD1 0 +#define BM_ICOLL_CTRL_RSRVD1 0x0000FFFF +#define BF_ICOLL_CTRL_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_CTRL_RSRVD1) + +#define HW_ICOLL_VBASE (0x00000040) +#define HW_ICOLL_VBASE_SET (0x00000044) +#define HW_ICOLL_VBASE_CLR (0x00000048) +#define HW_ICOLL_VBASE_TOG (0x0000004c) + +#define BP_ICOLL_VBASE_TABLE_ADDRESS 2 +#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC +#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \ + (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS) +#define BP_ICOLL_VBASE_RSRVD1 0 +#define BM_ICOLL_VBASE_RSRVD1 0x00000003 +#define BF_ICOLL_VBASE_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VBASE_RSRVD1) + +#define HW_ICOLL_STAT (0x00000070) + +#define BP_ICOLL_STAT_RSRVD1 7 +#define BM_ICOLL_STAT_RSRVD1 0xFFFFFF80 +#define BF_ICOLL_STAT_RSRVD1(v) \ + (((v) << 7) & BM_ICOLL_STAT_RSRVD1) +#define BP_ICOLL_STAT_VECTOR_NUMBER 0 +#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F +#define BF_ICOLL_STAT_VECTOR_NUMBER(v) \ + (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER) + +/* + * multi-register-define name HW_ICOLL_RAWn + * base 0x000000A0 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_RAWn(n) (0x000000a0 + (n) * 0x10) +#define HW_ICOLL_RAWn_SET(n) (0x000000a4 + (n) * 0x10) +#define HW_ICOLL_RAWn_CLR(n) (0x000000a8 + (n) * 0x10) +#define HW_ICOLL_RAWn_TOG(n) (0x000000ac + (n) * 0x10) +#define BP_ICOLL_RAWn_RAW_IRQS 0 +#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF +#define BF_ICOLL_RAWn_RAW_IRQS(v) (v) + +/* + * multi-register-define name HW_ICOLL_INTERRUPTn + * base 0x00000120 + * count 128 + * offset 0x10 + */ +#define HW_ICOLL_INTERRUPTn(n) (0x00000120 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_SET(n) (0x00000124 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_CLR(n) (0x00000128 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_TOG(n) (0x0000012c + (n) * 0x10) +#define BP_ICOLL_INTERRUPTn_RSRVD1 5 +#define BM_ICOLL_INTERRUPTn_RSRVD1 0xFFFFFFE0 +#define BF_ICOLL_INTERRUPTn_RSRVD1(v) \ + (((v) << 5) & BM_ICOLL_INTERRUPTn_RSRVD1) +#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010 +#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 +#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 +#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 +#define BP_ICOLL_INTERRUPTn_PRIORITY 0 +#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003 +#define BF_ICOLL_INTERRUPTn_PRIORITY(v) \ + (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY) +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 + +#define HW_ICOLL_DEBUG (0x00001120) +#define HW_ICOLL_DEBUG_SET (0x00001124) +#define HW_ICOLL_DEBUG_CLR (0x00001128) +#define HW_ICOLL_DEBUG_TOG (0x0000112c) + +#define BP_ICOLL_DEBUG_INSERVICE 28 +#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000 +#define BF_ICOLL_DEBUG_INSERVICE(v) \ + (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE) +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 +#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000 +#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \ + (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS) +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 +#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000 +#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \ + (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL) +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_RSRVD2 18 +#define BM_ICOLL_DEBUG_RSRVD2 0x000C0000 +#define BF_ICOLL_DEBUG_RSRVD2(v) \ + (((v) << 18) & BM_ICOLL_DEBUG_RSRVD2) +#define BM_ICOLL_DEBUG_FIQ 0x00020000 +#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 +#define BM_ICOLL_DEBUG_IRQ 0x00010000 +#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 +#define BP_ICOLL_DEBUG_RSRVD1 10 +#define BM_ICOLL_DEBUG_RSRVD1 0x0000FC00 +#define BF_ICOLL_DEBUG_RSRVD1(v) \ + (((v) << 10) & BM_ICOLL_DEBUG_RSRVD1) +#define BP_ICOLL_DEBUG_VECTOR_FSM 0 +#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF +#define BF_ICOLL_DEBUG_VECTOR_FSM(v) \ + (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM) +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 + +#define HW_ICOLL_DBGREAD0 (0x00001130) +#define HW_ICOLL_DBGREAD0_SET (0x00001134) +#define HW_ICOLL_DBGREAD0_CLR (0x00001138) +#define HW_ICOLL_DBGREAD0_TOG (0x0000113c) + +#define BP_ICOLL_DBGREAD0_VALUE 0 +#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD0_VALUE(v) (v) + +#define HW_ICOLL_DBGREAD1 (0x00001140) +#define HW_ICOLL_DBGREAD1_SET (0x00001144) +#define HW_ICOLL_DBGREAD1_CLR (0x00001148) +#define HW_ICOLL_DBGREAD1_TOG (0x0000114c) + +#define BP_ICOLL_DBGREAD1_VALUE 0 +#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD1_VALUE(v) (v) + +#define HW_ICOLL_DBGFLAG (0x00001150) +#define HW_ICOLL_DBGFLAG_SET (0x00001154) +#define HW_ICOLL_DBGFLAG_CLR (0x00001158) +#define HW_ICOLL_DBGFLAG_TOG (0x0000115c) + +#define BP_ICOLL_DBGFLAG_RSRVD1 16 +#define BM_ICOLL_DBGFLAG_RSRVD1 0xFFFF0000 +#define BF_ICOLL_DBGFLAG_RSRVD1(v) \ + (((v) << 16) & BM_ICOLL_DBGFLAG_RSRVD1) +#define BP_ICOLL_DBGFLAG_FLAG 0 +#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF +#define BF_ICOLL_DBGFLAG_FLAG(v) \ + (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG) + +/* + * multi-register-define name HW_ICOLL_DBGREQUESTn + * base 0x00001160 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_DBGREQUESTn(n) (0x00001160 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_SET(n) (0x00001164 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_CLR(n) (0x00001168 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_TOG(n) (0x0000116c + (n) * 0x10) +#define BP_ICOLL_DBGREQUESTn_BITS 0 +#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF +#define BF_ICOLL_DBGREQUESTn_BITS(v) (v) + +#define HW_ICOLL_VERSION (0x000011e0) + +#define BP_ICOLL_VERSION_MAJOR 24 +#define BM_ICOLL_VERSION_MAJOR 0xFF000000 +#define BF_ICOLL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ICOLL_VERSION_MAJOR) +#define BP_ICOLL_VERSION_MINOR 16 +#define BM_ICOLL_VERSION_MINOR 0x00FF0000 +#define BF_ICOLL_VERSION_MINOR(v) \ + (((v) << 16) & BM_ICOLL_VERSION_MINOR) +#define BP_ICOLL_VERSION_STEP 0 +#define BM_ICOLL_VERSION_STEP 0x0000FFFF +#define BF_ICOLL_VERSION_STEP(v) \ + (((v) << 0) & BM_ICOLL_VERSION_STEP) +#endif /* __ARCH_ARM___ICOLL_H */ diff --git a/arch/arm/plat-mxs/regs-usbphy.h b/arch/arm/plat-mxs/regs-usbphy.h new file mode 100644 index 000000000000..cf64bfdab0e6 --- /dev/null +++ b/arch/arm/plat-mxs/regs-usbphy.h @@ -0,0 +1,323 @@ +/* + * Freescale USBPHY Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.52 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___USBPHY_H +#define __ARCH_ARM___USBPHY_H + + +#define HW_USBPHY_PWD (0x00000000) +#define HW_USBPHY_PWD_SET (0x00000004) +#define HW_USBPHY_PWD_CLR (0x00000008) +#define HW_USBPHY_PWD_TOG (0x0000000c) + +#define BP_USBPHY_PWD_RSVD2 21 +#define BM_USBPHY_PWD_RSVD2 0xFFE00000 +#define BF_USBPHY_PWD_RSVD2(v) \ + (((v) << 21) & BM_USBPHY_PWD_RSVD2) +#define BM_USBPHY_PWD_RXPWDRX 0x00100000 +#define BM_USBPHY_PWD_RXPWDDIFF 0x00080000 +#define BM_USBPHY_PWD_RXPWD1PT1 0x00040000 +#define BM_USBPHY_PWD_RXPWDENV 0x00020000 +#define BP_USBPHY_PWD_RSVD1 13 +#define BM_USBPHY_PWD_RSVD1 0x0001E000 +#define BF_USBPHY_PWD_RSVD1(v) \ + (((v) << 13) & BM_USBPHY_PWD_RSVD1) +#define BM_USBPHY_PWD_TXPWDV2I 0x00001000 +#define BM_USBPHY_PWD_TXPWDIBIAS 0x00000800 +#define BM_USBPHY_PWD_TXPWDFS 0x00000400 +#define BP_USBPHY_PWD_RSVD0 0 +#define BM_USBPHY_PWD_RSVD0 0x000003FF +#define BF_USBPHY_PWD_RSVD0(v) \ + (((v) << 0) & BM_USBPHY_PWD_RSVD0) + +#define HW_USBPHY_TX (0x00000010) +#define HW_USBPHY_TX_SET (0x00000014) +#define HW_USBPHY_TX_CLR (0x00000018) +#define HW_USBPHY_TX_TOG (0x0000001c) + +#define BP_USBPHY_TX_RSVD5 29 +#define BM_USBPHY_TX_RSVD5 0xE0000000 +#define BF_USBPHY_TX_RSVD5(v) \ + (((v) << 29) & BM_USBPHY_TX_RSVD5) +#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL 26 +#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL 0x1C000000 +#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v) \ + (((v) << 26) & BM_USBPHY_TX_USBPHY_TX_EDGECTRL) +#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT 0x02000000 +#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX 0x01000000 +#define BP_USBPHY_TX_RSVD4 22 +#define BM_USBPHY_TX_RSVD4 0x00C00000 +#define BF_USBPHY_TX_RSVD4(v) \ + (((v) << 22) & BM_USBPHY_TX_RSVD4) +#define BM_USBPHY_TX_TXENCAL45DP 0x00200000 +#define BM_USBPHY_TX_RSVD3 0x00100000 +#define BP_USBPHY_TX_TXCAL45DP 16 +#define BM_USBPHY_TX_TXCAL45DP 0x000F0000 +#define BF_USBPHY_TX_TXCAL45DP(v) \ + (((v) << 16) & BM_USBPHY_TX_TXCAL45DP) +#define BP_USBPHY_TX_RSVD2 14 +#define BM_USBPHY_TX_RSVD2 0x0000C000 +#define BF_USBPHY_TX_RSVD2(v) \ + (((v) << 14) & BM_USBPHY_TX_RSVD2) +#define BM_USBPHY_TX_TXENCAL45DN 0x00002000 +#define BM_USBPHY_TX_RSVD1 0x00001000 +#define BP_USBPHY_TX_TXCAL45DN 8 +#define BM_USBPHY_TX_TXCAL45DN 0x00000F00 +#define BF_USBPHY_TX_TXCAL45DN(v) \ + (((v) << 8) & BM_USBPHY_TX_TXCAL45DN) +#define BP_USBPHY_TX_RSVD0 4 +#define BM_USBPHY_TX_RSVD0 0x000000F0 +#define BF_USBPHY_TX_RSVD0(v) \ + (((v) << 4) & BM_USBPHY_TX_RSVD0) +#define BP_USBPHY_TX_D_CAL 0 +#define BM_USBPHY_TX_D_CAL 0x0000000F +#define BF_USBPHY_TX_D_CAL(v) \ + (((v) << 0) & BM_USBPHY_TX_D_CAL) + +#define HW_USBPHY_RX (0x00000020) +#define HW_USBPHY_RX_SET (0x00000024) +#define HW_USBPHY_RX_CLR (0x00000028) +#define HW_USBPHY_RX_TOG (0x0000002c) + +#define BP_USBPHY_RX_RSVD2 23 +#define BM_USBPHY_RX_RSVD2 0xFF800000 +#define BF_USBPHY_RX_RSVD2(v) \ + (((v) << 23) & BM_USBPHY_RX_RSVD2) +#define BM_USBPHY_RX_RXDBYPASS 0x00400000 +#define BP_USBPHY_RX_RSVD1 7 +#define BM_USBPHY_RX_RSVD1 0x003FFF80 +#define BF_USBPHY_RX_RSVD1(v) \ + (((v) << 7) & BM_USBPHY_RX_RSVD1) +#define BP_USBPHY_RX_DISCONADJ 4 +#define BM_USBPHY_RX_DISCONADJ 0x00000070 +#define BF_USBPHY_RX_DISCONADJ(v) \ + (((v) << 4) & BM_USBPHY_RX_DISCONADJ) +#define BM_USBPHY_RX_RSVD0 0x00000008 +#define BP_USBPHY_RX_ENVADJ 0 +#define BM_USBPHY_RX_ENVADJ 0x00000007 +#define BF_USBPHY_RX_ENVADJ(v) \ + (((v) << 0) & BM_USBPHY_RX_ENVADJ) + +#define HW_USBPHY_CTRL (0x00000030) +#define HW_USBPHY_CTRL_SET (0x00000034) +#define HW_USBPHY_CTRL_CLR (0x00000038) +#define HW_USBPHY_CTRL_TOG (0x0000003c) + +#define BM_USBPHY_CTRL_SFTRST 0x80000000 +#define BM_USBPHY_CTRL_CLKGATE 0x40000000 +#define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000 +#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0 0x10000000 +#define BM_USBPHY_CTRL_RSVD3 0x08000000 +#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS 0x04000000 +#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE 0x02000000 +#define BM_USBPHY_CTRL_FSDLL_RST_EN 0x01000000 +#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP 0x00800000 +#define BM_USBPHY_CTRL_ENIDCHG_WKUP 0x00400000 +#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP 0x00200000 +#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD 0x00100000 +#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE 0x00080000 +#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL 0x00040000 +#define BM_USBPHY_CTRL_WAKEUP_IRQ 0x00020000 +#define BM_USBPHY_CTRL_ENIRQWAKEUP 0x00010000 +#define BM_USBPHY_CTRL_ENUTMILEVEL3 0x00008000 +#define BM_USBPHY_CTRL_ENUTMILEVEL2 0x00004000 +#define BM_USBPHY_CTRL_DATA_ON_LRADC 0x00002000 +#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ 0x00001000 +#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 +#define BM_USBPHY_CTRL_RESUME_IRQ 0x00000400 +#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x00000200 +#define BM_USBPHY_CTRL_RESUMEIRQSTICKY 0x00000100 +#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 +#define BM_USBPHY_CTRL_RSVD1 0x00000040 +#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY 0x00000020 +#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 +#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x00000008 +#define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x00000004 +#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 +#define BM_USBPHY_CTRL_RSVD0 0x00000001 + +#define HW_USBPHY_STATUS (0x00000040) + +#define BP_USBPHY_STATUS_RSVD4 11 +#define BM_USBPHY_STATUS_RSVD4 0xFFFFF800 +#define BF_USBPHY_STATUS_RSVD4(v) \ + (((v) << 11) & BM_USBPHY_STATUS_RSVD4) +#define BM_USBPHY_STATUS_RESUME_STATUS 0x00000400 +#define BM_USBPHY_STATUS_RSVD3 0x00000200 +#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 +#define BM_USBPHY_STATUS_RSVD2 0x00000080 +#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 +#define BP_USBPHY_STATUS_RSVD1 4 +#define BM_USBPHY_STATUS_RSVD1 0x00000030 +#define BF_USBPHY_STATUS_RSVD1(v) \ + (((v) << 4) & BM_USBPHY_STATUS_RSVD1) +#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x00000008 +#define BP_USBPHY_STATUS_RSVD0 0 +#define BM_USBPHY_STATUS_RSVD0 0x00000007 +#define BF_USBPHY_STATUS_RSVD0(v) \ + (((v) << 0) & BM_USBPHY_STATUS_RSVD0) + +#define HW_USBPHY_DEBUG (0x00000050) +#define HW_USBPHY_DEBUG_SET (0x00000054) +#define HW_USBPHY_DEBUG_CLR (0x00000058) +#define HW_USBPHY_DEBUG_TOG (0x0000005c) + +#define BM_USBPHY_DEBUG_RSVD3 0x80000000 +#define BM_USBPHY_DEBUG_CLKGATE 0x40000000 +#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG 0x20000000 +#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH 25 +#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1E000000 +#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) \ + (((v) << 25) & BM_USBPHY_DEBUG_SQUELCHRESETLENGTH) +#define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x01000000 +#define BP_USBPHY_DEBUG_RSVD2 21 +#define BM_USBPHY_DEBUG_RSVD2 0x00E00000 +#define BF_USBPHY_DEBUG_RSVD2(v) \ + (((v) << 21) & BM_USBPHY_DEBUG_RSVD2) +#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT 16 +#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x001F0000 +#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) \ + (((v) << 16) & BM_USBPHY_DEBUG_SQUELCHRESETCOUNT) +#define BP_USBPHY_DEBUG_RSVD1 13 +#define BM_USBPHY_DEBUG_RSVD1 0x0000E000 +#define BF_USBPHY_DEBUG_RSVD1(v) \ + (((v) << 13) & BM_USBPHY_DEBUG_RSVD1) +#define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x00001000 +#define BP_USBPHY_DEBUG_TX2RXCOUNT 8 +#define BM_USBPHY_DEBUG_TX2RXCOUNT 0x00000F00 +#define BF_USBPHY_DEBUG_TX2RXCOUNT(v) \ + (((v) << 8) & BM_USBPHY_DEBUG_TX2RXCOUNT) +#define BP_USBPHY_DEBUG_RSVD0 6 +#define BM_USBPHY_DEBUG_RSVD0 0x000000C0 +#define BF_USBPHY_DEBUG_RSVD0(v) \ + (((v) << 6) & BM_USBPHY_DEBUG_RSVD0) +#define BP_USBPHY_DEBUG_ENHSTPULLDOWN 4 +#define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x00000030 +#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) \ + (((v) << 4) & BM_USBPHY_DEBUG_ENHSTPULLDOWN) +#define BP_USBPHY_DEBUG_HSTPULLDOWN 2 +#define BM_USBPHY_DEBUG_HSTPULLDOWN 0x0000000C +#define BF_USBPHY_DEBUG_HSTPULLDOWN(v) \ + (((v) << 2) & BM_USBPHY_DEBUG_HSTPULLDOWN) +#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x00000002 +#define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x00000001 + +#define HW_USBPHY_DEBUG0_STATUS (0x00000060) + +#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 26 +#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xFC000000 +#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) \ + (((v) << 26) & BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT) +#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 16 +#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x03FF0000 +#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) \ + (((v) << 16) & BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT) +#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0 +#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0x0000FFFF +#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) \ + (((v) << 0) & BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT) + +#define HW_USBPHY_DEBUG1 (0x00000070) +#define HW_USBPHY_DEBUG1_SET (0x00000074) +#define HW_USBPHY_DEBUG1_CLR (0x00000078) +#define HW_USBPHY_DEBUG1_TOG (0x0000007c) + +#define BP_USBPHY_DEBUG1_RSVD1 15 +#define BM_USBPHY_DEBUG1_RSVD1 0xFFFF8000 +#define BF_USBPHY_DEBUG1_RSVD1(v) \ + (((v) << 15) & BM_USBPHY_DEBUG1_RSVD1) +#define BP_USBPHY_DEBUG1_ENTAILADJVD 13 +#define BM_USBPHY_DEBUG1_ENTAILADJVD 0x00006000 +#define BF_USBPHY_DEBUG1_ENTAILADJVD(v) \ + (((v) << 13) & BM_USBPHY_DEBUG1_ENTAILADJVD) +#define BM_USBPHY_DEBUG1_ENTX2TX 0x00001000 +#define BP_USBPHY_DEBUG1_RSVD0 4 +#define BM_USBPHY_DEBUG1_RSVD0 0x00000FF0 +#define BF_USBPHY_DEBUG1_RSVD0(v) \ + (((v) << 4) & BM_USBPHY_DEBUG1_RSVD0) +#define BP_USBPHY_DEBUG1_DBG_ADDRESS 0 +#define BM_USBPHY_DEBUG1_DBG_ADDRESS 0x0000000F +#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) \ + (((v) << 0) & BM_USBPHY_DEBUG1_DBG_ADDRESS) + +#define HW_USBPHY_VERSION (0x00000080) + +#define BP_USBPHY_VERSION_MAJOR 24 +#define BM_USBPHY_VERSION_MAJOR 0xFF000000 +#define BF_USBPHY_VERSION_MAJOR(v) \ + (((v) << 24) & BM_USBPHY_VERSION_MAJOR) +#define BP_USBPHY_VERSION_MINOR 16 +#define BM_USBPHY_VERSION_MINOR 0x00FF0000 +#define BF_USBPHY_VERSION_MINOR(v) \ + (((v) << 16) & BM_USBPHY_VERSION_MINOR) +#define BP_USBPHY_VERSION_STEP 0 +#define BM_USBPHY_VERSION_STEP 0x0000FFFF +#define BF_USBPHY_VERSION_STEP(v) \ + (((v) << 0) & BM_USBPHY_VERSION_STEP) + +#define HW_USBPHY_IP (0x00000090) +#define HW_USBPHY_IP_SET (0x00000094) +#define HW_USBPHY_IP_CLR (0x00000098) +#define HW_USBPHY_IP_TOG (0x0000009c) + +#define BP_USBPHY_IP_RSVD1 25 +#define BM_USBPHY_IP_RSVD1 0xFE000000 +#define BF_USBPHY_IP_RSVD1(v) \ + (((v) << 25) & BM_USBPHY_IP_RSVD1) +#define BP_USBPHY_IP_DIV_SEL 23 +#define BM_USBPHY_IP_DIV_SEL 0x01800000 +#define BF_USBPHY_IP_DIV_SEL(v) \ + (((v) << 23) & BM_USBPHY_IP_DIV_SEL) +#define BV_USBPHY_IP_DIV_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_DIV_SEL__LOWER 0x1 +#define BV_USBPHY_IP_DIV_SEL__LOWEST 0x2 +#define BV_USBPHY_IP_DIV_SEL__UNDEFINED 0x3 +#define BP_USBPHY_IP_LFR_SEL 21 +#define BM_USBPHY_IP_LFR_SEL 0x00600000 +#define BF_USBPHY_IP_LFR_SEL(v) \ + (((v) << 21) & BM_USBPHY_IP_LFR_SEL) +#define BV_USBPHY_IP_LFR_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_LFR_SEL__TIMES_2 0x1 +#define BV_USBPHY_IP_LFR_SEL__TIMES_05 0x2 +#define BV_USBPHY_IP_LFR_SEL__UNDEFINED 0x3 +#define BP_USBPHY_IP_CP_SEL 19 +#define BM_USBPHY_IP_CP_SEL 0x00180000 +#define BF_USBPHY_IP_CP_SEL(v) \ + (((v) << 19) & BM_USBPHY_IP_CP_SEL) +#define BV_USBPHY_IP_CP_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_CP_SEL__TIMES_2 0x1 +#define BV_USBPHY_IP_CP_SEL__TIMES_05 0x2 +#define BV_USBPHY_IP_CP_SEL__UNDEFINED 0x3 +#define BM_USBPHY_IP_TSTI_TX_DP 0x00040000 +#define BM_USBPHY_IP_TSTI_TX_DM 0x00020000 +#define BM_USBPHY_IP_ANALOG_TESTMODE 0x00010000 +#define BP_USBPHY_IP_RSVD0 3 +#define BM_USBPHY_IP_RSVD0 0x0000FFF8 +#define BF_USBPHY_IP_RSVD0(v) \ + (((v) << 3) & BM_USBPHY_IP_RSVD0) +#define BM_USBPHY_IP_EN_USB_CLKS 0x00000004 +#define BM_USBPHY_IP_PLL_LOCKED 0x00000002 +#define BM_USBPHY_IP_PLL_POWER 0x00000001 +#endif /* __ARCH_ARM___USBPHY_H */ diff --git a/arch/arm/plat-mxs/timer-match.c b/arch/arm/plat-mxs/timer-match.c new file mode 100644 index 000000000000..d6429e6955e6 --- /dev/null +++ b/arch/arm/plat-mxs/timer-match.c @@ -0,0 +1,164 @@ +/* + * System timer for Freescale i.MXS + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +static struct mxs_sys_timer *online_timer; + +static irqreturn_t mxs_timer_handler(int irq, void *dev_id); + +static cycle_t mxs_get_cycles(struct clocksource *cs) +{ + return ~__raw_readl(online_timer->base + + HW_TIMROT_RUNNING_COUNTn(online_timer->id)); +} + +static int mxs_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + unsigned int match; + match = __raw_readl(online_timer->base + + HW_TIMROT_RUNNING_COUNTn(online_timer->id)) - delta; + __raw_writel(match, online_timer->base + + HW_TIMROT_MATCH_COUNTn(online_timer->id)); + return (int)(match - + __raw_readl(online_timer->base + + HW_TIMROT_RUNNING_COUNTn(online_timer->id))) + > 0 ? -ETIME : 0; +} + + +static void mxs_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + switch (mode) { + case CLOCK_EVT_MODE_SHUTDOWN: + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(0)); + break; + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_ONESHOT: + __raw_writel(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE, + online_timer->base + HW_TIMROT_ROTCTRL_CLR); + __raw_writel(BF_TIMROT_TIMCTRLn_SELECT(online_timer->clk_sel) | + BM_TIMROT_TIMCTRLn_IRQ_EN | + BM_TIMROT_TIMCTRLn_MATCH_MODE, + online_timer->base + HW_TIMROT_TIMCTRLn(online_timer->id)); + break; + default: + break; + } +} + +static struct clock_event_device mxs_clockevent = { + .name = "mxs tick timer ", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = mxs_set_next_event, + .set_mode = mxs_set_mode, + .rating = 200, +}; + +static struct clocksource mxs_clocksource = { + .name = "mxs clock source", + .rating = 250, + .read = mxs_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS +}; + +static struct irqaction mxs_timer_irq = { + .name = "i.MX/mxs Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = mxs_timer_handler, + .dev_id = &mxs_clockevent, +}; + +static int __init mxs_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + mxs_clocksource.mult = clocksource_hz2mult(c, mxs_clocksource.shift); + clocksource_register(&mxs_clocksource); + return 0; +} + +static int __init mxs_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + mxs_clockevent.mult = div_sc(c, NSEC_PER_SEC, mxs_clockevent.shift); + mxs_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &mxs_clockevent); + mxs_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFFFFF0, + &mxs_clockevent); + mxs_clockevent.cpumask = cpumask_of(0); + + clockevents_register_device(&mxs_clockevent); + return 0; +} + +static irqreturn_t mxs_timer_handler(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + if (__raw_readl(online_timer->base + + HW_TIMROT_TIMCTRLn(online_timer->id)) & + BM_TIMROT_TIMCTRLn_IRQ) { + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + + HW_TIMROT_TIMCTRLn_CLR(online_timer->id)); + c->event_handler(c); + } + return IRQ_HANDLED; +} + +void mxs_timer_init(struct mxs_sys_timer *timer) +{ + if (!timer->base || !timer->clk || IS_ERR(timer->clk)) + return; + if (online_timer) + return; + online_timer = timer; + clk_enable(online_timer->clk); + __raw_writel(BF_TIMROT_TIMCTRLn_SELECT(online_timer->clk_sel) | + BM_TIMROT_TIMCTRLn_IRQ_EN | + BM_TIMROT_TIMCTRLn_MATCH_MODE, + online_timer->base + HW_TIMROT_TIMCTRLn(online_timer->id)); + mxs_clocksource_init(online_timer->clk); + mxs_clockevent_init(online_timer->clk); + setup_irq(online_timer->irq, &mxs_timer_irq); +} + + diff --git a/arch/arm/plat-mxs/timer-nomatch.c b/arch/arm/plat-mxs/timer-nomatch.c new file mode 100644 index 000000000000..db8906192f16 --- /dev/null +++ b/arch/arm/plat-mxs/timer-nomatch.c @@ -0,0 +1,195 @@ +/* + * System timer for Freescale STMP37XX/STMP378X + * + * Embedded Alley Solutions, Inc + * + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifndef HW_TIMROT_TIMCOUNTn +#define HW_TIMROT_TIMCOUNTn HW_TIMROT_RUNNING_COUNTn +#endif +static struct mxs_sys_timer *online_timer; + +static irqreturn_t +mxs_nomatch_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *c = dev_id; + + /* timer 0 */ + if (__raw_readl(online_timer->base + HW_TIMROT_TIMCTRLn(0)) & + BM_TIMROT_TIMCTRLn_IRQ) { + + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(0)); + c->event_handler(c); + } + + /* timer 1 */ + else if (__raw_readl(online_timer->base + HW_TIMROT_TIMCTRLn(1)) + & BM_TIMROT_TIMCTRLn_IRQ) { + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(1)); + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(1)); + __raw_writel(0xFFFF, + online_timer->base + HW_TIMROT_TIMCOUNTn(1)); + } + + return IRQ_HANDLED; +} + +static cycle_t mxs_nomatch_clock_read(struct clocksource *cs) +{ + return ~((__raw_readl(online_timer->base + HW_TIMROT_TIMCOUNTn(1)) + & 0xFFFF0000) >> 16); +} + +static int +mxs_nomatch_timrot_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + /* reload the timer */ + __raw_writel(delta, online_timer->base + HW_TIMROT_TIMCOUNTn(0)); + return 0; +} + +static void +mxs_nomatch_timrot_set_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ +} + +static struct clock_event_device ckevt_timrot = { + .name = "timrot", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_next_event = mxs_nomatch_timrot_set_next_event, + .set_mode = mxs_nomatch_timrot_set_mode, +}; + +static struct clocksource cksrc_mxs_nomatch = { + .name = "mxs clock source", + .rating = 250, + .read = mxs_nomatch_clock_read, + .mask = CLOCKSOURCE_MASK(16), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static struct irqaction mxs_nomatch_timer_irq = { + .name = "mxs_nomatch_timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = mxs_nomatch_timer_interrupt, + .dev_id = &ckevt_timrot, +}; + + +/* + * Set up timer interrupt, and return the current time in seconds. + */ +void mxs_nomatch_timer_init(struct mxs_sys_timer *timer) +{ + + if (online_timer) + return; + + online_timer = timer; + + cksrc_mxs_nomatch.mult = clocksource_hz2mult(clk_get_rate(timer->clk), + cksrc_mxs_nomatch.shift); + ckevt_timrot.mult = div_sc(clk_get_rate(timer->clk), NSEC_PER_SEC, + ckevt_timrot.shift); + ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); + ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); + ckevt_timrot.cpumask = cpumask_of(0); + + /* clear two timers */ + __raw_writel(0, online_timer->base + HW_TIMROT_TIMCOUNTn(0)); + __raw_writel(0, online_timer->base + HW_TIMROT_TIMCOUNTn(1)); + + /* configure them */ + __raw_writel( + (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn(0)); + __raw_writel( + (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn(1)); + + __raw_writel(clk_get_rate(timer->clk) / HZ - 1, + online_timer->base + HW_TIMROT_TIMCOUNTn(0)); + __raw_writel(0xFFFF, online_timer->base + HW_TIMROT_TIMCOUNTn(1)); + + setup_irq(IRQ_TIMER0, &mxs_nomatch_timer_irq); + + clocksource_register(&cksrc_mxs_nomatch); + clockevents_register_device(&ckevt_timrot); +} + +#ifdef CONFIG_PM + +void mxs_nomatch_suspend_timer(void) +{ + __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ, + online_timer->base + HW_TIMROT_TIMCTRLn_CLR(0)); + __raw_writel(BM_TIMROT_ROTCTRL_CLKGATE, + online_timer->base + HW_TIMROT_ROTCTRL_SET); +} + +void mxs_nomatch_resume_timer(void) +{ + __raw_writel(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE, + online_timer->base + HW_TIMROT_ROTCTRL_CLR); + __raw_writel( + 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn(0)); + __raw_writel( + 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ + BM_TIMROT_TIMCTRLn_RELOAD | + BM_TIMROT_TIMCTRLn_UPDATE | + BM_TIMROT_TIMCTRLn_IRQ_EN, + online_timer->base + HW_TIMROT_TIMCTRLn(1)); + __raw_writel(clk_get_rate(online_timer->clk) / HZ - 1, + online_timer->base + HW_TIMROT_TIMCOUNTn(0)); + __raw_writel(0xFFFF, online_timer->base + HW_TIMROT_TIMCOUNTn(1)); +} + +#else + +#define mxs_nomatch_suspend_timer NULL +#define mxs_nomatch_resume_timer NULL + +#endif /* CONFIG_PM */ diff --git a/arch/arm/plat-mxs/unique-id.c b/arch/arm/plat-mxs/unique-id.c new file mode 100644 index 000000000000..adb8286230cc --- /dev/null +++ b/arch/arm/plat-mxs/unique-id.c @@ -0,0 +1,199 @@ +/* + * Unique ID manipulation sysfs access generic functions + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static int unlock; +static spinlock_t u_lock; +static const unsigned long UID_AUTOLOCK_TIMEOUT = HZ * 60 * 3; +static struct timer_list u_timer; + +static void uid_timer_autolock(unsigned long param) +{ + struct timer_list *tmr = (struct timer_list *)param; + + if (spin_trylock(&u_lock)) { + if (unlock) + pr_debug("%s: locked down.\n", __func__); + unlock = 0; + spin_unlock(&u_lock); + } + mod_timer(tmr, jiffies + UID_AUTOLOCK_TIMEOUT); +} + +static LIST_HEAD(uid_provider_list); + +struct uid_provider { + struct kobject *kobj; + struct list_head list; + struct uid_ops *ops; + void *context; +}; + +static struct uid_provider *uid_provider_find(const char *name); + +#define UID_FWD_SYSFS_FILE(var, file, param) \ + static ssize_t var##_show(struct kobject *kobj, \ + struct kobj_attribute *attr, char *buf) \ + { \ + struct uid_provider *p = \ + uid_provider_find(kobject_name(kobj)); \ + ssize_t r; \ + BUG_ON(p == NULL); \ + r = (p->ops && p->ops->file##_show) ? \ + p->ops->file##_show(p->context, buf, param) : 0;\ + return r; \ + } \ + \ + static ssize_t var##_store(struct kobject *kobj, \ + struct kobj_attribute *attr, const char *buf, \ + size_t count) \ + { \ + struct uid_provider *p = \ + uid_provider_find(kobject_name(kobj)); \ + ssize_t r; \ + int ul; \ + BUG_ON(p == NULL); \ + spin_lock(&u_lock); \ + ul = unlock; \ + spin_unlock(&u_lock); \ + if (ul) \ + r = (p->ops && p->ops->file##_store) ? \ + p->ops->file##_store(p->context, buf, count, param) \ + : count; \ + else \ + r = -EACCES; \ + return r; \ + } + +struct kobject *uid_kobj; + +#define UID_ATTR(_name, _varname) \ + static struct kobj_attribute _varname##_attr = \ + __ATTR(_name, 0644, _varname##_show, _varname##_store) + +UID_FWD_SYSFS_FILE(id, id, 1); +UID_FWD_SYSFS_FILE(id_bin, id, 0); +UID_ATTR(id, id); +UID_ATTR(id.bin, id_bin); + +static struct attribute *uid_attrs[] = { + &id_attr.attr, + &id_bin_attr.attr, + NULL +}; + +static struct attribute_group uid_attr_group = { + .attrs = uid_attrs, +}; + +struct kobject *uid_provider_init(const char *name, + struct uid_ops *ops, void *context) +{ + struct uid_provider *new; + int err; + + new = kzalloc(sizeof(*new), GFP_KERNEL); + if (!new) { + err = -ENOMEM; + goto out; + } + + new->kobj = kobject_create_and_add(name, uid_kobj); + if (!new->kobj) { + err = -ENOMEM; + goto out; + } + new->ops = ops; + new->context = context; + + err = sysfs_create_group(new->kobj, &uid_attr_group); + if (err) + goto out2; + + list_add_tail(&new->list, &uid_provider_list); + return new->kobj; +out2: + kobject_del(new->kobj); +out: + kfree(new); + return ERR_PTR(err); +} +EXPORT_SYMBOL_GPL(uid_provider_init); + +static struct uid_provider *uid_provider_find(const char *name) +{ + struct uid_provider *p; + + list_for_each_entry(p, &uid_provider_list, list) { + if (strcmp(kobject_name(p->kobj), name) == 0) + return p; + } + return NULL; +} + +void uid_provider_remove(const char *name) +{ + struct uid_provider *p; + + p = uid_provider_find(name); + if (!p) + return; + kobject_del(p->kobj); + list_del(&p->list); + kfree(p); +} +EXPORT_SYMBOL_GPL(uid_provider_remove); + +static int uid_sysfs_init(void) +{ + int error; + + uid_kobj = kobject_create_and_add("uid", NULL); + if (!uid_kobj) { + error = -ENOMEM; + goto out1; + } + + spin_lock_init(&u_lock); + setup_timer(&u_timer, uid_timer_autolock, (unsigned long)&u_timer); + + /* try to lock each 3 minutes */ + mod_timer(&u_timer, jiffies + UID_AUTOLOCK_TIMEOUT); + return 0; + +out1: + printk(KERN_ERR"%s failed, error %d.", __func__, error); + return error; +} + +module_param(unlock, int, 0600) +core_initcall(uid_sysfs_init); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("dmitry pervushin "); +MODULE_DESCRIPTION("Unique ID simple framework"); diff --git a/arch/arm/plat-mxs/usb_common.c b/arch/arm/plat-mxs/usb_common.c new file mode 100644 index 000000000000..16ef4736b4d0 --- /dev/null +++ b/arch/arm/plat-mxs/usb_common.c @@ -0,0 +1,426 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + *@defgroup USB ARC OTG USB Driver + */ + +/*! + * @file usb_common.c + * + * @brief platform related part of usb driver. + * @ingroup USB + */ + +/*! + *Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define MXC_NUMBER_USB_TRANSCEIVER 6 +struct fsl_xcvr_ops *g_xc_ops[MXC_NUMBER_USB_TRANSCEIVER] = { NULL }; + +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops) +{ + int i; + + pr_debug("%s\n", __func__); + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] == NULL) { + g_xc_ops[i] = xcvr_ops; + return; + } + } + + pr_debug("Failed %s\n", __func__); +} +EXPORT_SYMBOL(fsl_usb_xcvr_register); + +void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops) +{ + int i; + + pr_debug("%s\n", __func__); + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (g_xc_ops[i] == xcvr_ops) { + g_xc_ops[i] = NULL; + return; + } + } + + pr_debug("Failed %s\n", __func__); +} +EXPORT_SYMBOL(fsl_usb_xcvr_unregister); + +void fsl_platform_set_test_mode( + struct fsl_usb2_platform_data *pdata, + enum usb_test_mode mode) +{ +} +EXPORT_SYMBOL(fsl_platform_set_test_mode); + +/* enable/disable high-speed disconnect detector of phy ctrl */ +void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata, + bool enable) +{ + if (enable) + __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, + IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_CTRL_SET); + else + __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, + IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_CTRL_CLR); +} +EXPORT_SYMBOL(fsl_platform_set_usb_phy_dis); + + +#if defined(CONFIG_USB_OTG) +static struct resource *otg_resources; + +struct resource *otg_get_resources(void) +{ + pr_debug("otg_get_resources\n"); + return otg_resources; +} +EXPORT_SYMBOL(otg_get_resources); + +int otg_set_resources(struct resource *resources) +{ + otg_resources = resources; + return 0; +} +EXPORT_SYMBOL(otg_set_resources); +#endif + +/*! + * Register remote wakeup by this usb controller + * + * @param pdev: platform_device for this usb controller + * + * @return 0 or negative error code in case not supportted. + */ +static int usb_register_remote_wakeup(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct resource *res; + int irq; + + pr_debug("%s: pdev=0x%p \n", __func__, pdev); + if (!(pdata->wake_up_enable)) + return -ECANCELED; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + pdev->dev.power.can_wakeup = 1; + enable_irq_wake(irq); + + return 0; +} + +static struct fsl_xcvr_ops *fsl_usb_get_xcvr(char *name) +{ + int i; + + pr_debug("%s\n", __func__); + if (name == NULL) { + printk(KERN_ERR "get_xcvr(): No tranceiver name\n"); + return NULL; + } + + for (i = 0; i < MXC_NUMBER_USB_TRANSCEIVER; i++) { + if (strcmp(g_xc_ops[i]->name, name) == 0) + return g_xc_ops[i]; + } + pr_debug("Failed %s\n", __func__); + return NULL; +} + +/* The dmamask must be set for EHCI to work */ +static u64 ehci_dmamask = ~(u32) 0; + +static int instance_id = ~(u32) 0; +struct platform_device *host_pdev_register(struct resource *res, int n_res, + struct fsl_usb2_platform_data + *config) +{ + struct platform_device *pdev; + int rc; + + pr_debug("register host res=0x%p, size=%d\n", res, n_res); + + pdev = platform_device_register_simple("fsl-ehci", + instance_id, res, n_res); + if (IS_ERR(pdev)) { + pr_debug("can't register %s Host, %ld\n", + config->name, PTR_ERR(pdev)); + return NULL; + } + + pdev->dev.coherent_dma_mask = 0xffffffff; + pdev->dev.dma_mask = &ehci_dmamask; + + /* + * platform_device_add_data() makes a copy of + * the platform_data passed in. That makes it + * impossible to share the same config struct for + * all OTG devices (host,gadget,otg). So, just + * set the platorm_data pointer ourselves. + */ + rc = platform_device_add_data(pdev, config, + sizeof(struct fsl_usb2_platform_data)); + if (rc) { + platform_device_unregister(pdev); + return NULL; + } + + pr_debug(KERN_INFO "usb: %s host (%s) registered\n", config->name, + config->transceiver); + pr_debug("pdev=0x%p dev=0x%p resources=0x%p pdata=0x%p\n", + pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data); + + instance_id++; + + return pdev; +} + +int usb_phy_enable(struct fsl_usb2_platform_data *pdata) +{ + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + void __iomem *usb_reg = pdata->regs; + void __iomem *usbcmd, *phy_ctrl, *portsc; + + /* Reset USB IP */ + usbcmd = usb_reg + UOG_USBCMD; + tmp = __raw_readl(usbcmd); /* usb command */ + tmp &= ~UCMD_RUN_STOP; + __raw_writel(tmp, usbcmd); + while (__raw_readl(usbcmd) & UCMD_RUN_STOP) + ; + + tmp |= UCMD_RESET; + __raw_writel(tmp, usbcmd); + while (__raw_readl(usbcmd) & UCMD_RESET) + ; + mdelay(10); + + /* Reset USBPHY module */ + phy_ctrl = phy_reg + HW_USBPHY_CTRL; + tmp = __raw_readl(phy_ctrl); + tmp |= BM_USBPHY_CTRL_SFTRST; + __raw_writel(tmp, phy_ctrl); + udelay(10); + + /* Remove CLKGATE and SFTRST */ + tmp = __raw_readl(phy_ctrl); + tmp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST); + __raw_writel(tmp, phy_ctrl); + udelay(10); + + /* set UTMI xcvr */ + /* Workaround an IC issue for ehci driver: + * when turn off root hub port power, EHCI set + * PORTSC reserved bits to be 0, but PTW with 0 + * means 8 bits tranceiver width, here change + * it back to be 16 bits and do PHY diable and + * then enable. + */ + portsc = usb_reg + UOG_PORTSC1; + tmp = __raw_readl(portsc); + tmp &= ~PORTSC_PTS_MASK; + tmp |= (PORTSC_PTS_UTMI | PORTSC_PTW); + __raw_writel(tmp, portsc); + + /* Power up the PHY */ + __raw_writel(0, phy_reg + HW_USBPHY_PWD); + + return 0; +} +EXPORT_SYMBOL(usb_phy_enable); + +static int otg_used; + +int usbotg_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *xops; + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); + + xops = fsl_usb_get_xcvr(pdata->transceiver); + if (!xops) { + printk(KERN_ERR "DR transceiver ops missing\n"); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + pdata->pdev = pdev; + + if (!otg_used) { + pr_debug("%s: grab pins\n", __func__); + if (xops->init) + xops->init(xops); + usb_phy_enable(pdata); + } + + if ((pdata->operating_mode == FSL_USB2_DR_HOST) || + (pdata->operating_mode == FSL_USB2_DR_OTG)) { + /* enable FS/LS device */ + __raw_writel(BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_CTRL_ENUTMILEVEL3 + , IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_CTRL_SET); + } + + if (usb_register_remote_wakeup(pdev)) + pr_debug("%s port is not a wakeup source.\n", pdata->name); + + otg_used++; + pr_debug("%s: success\n", __func__); + return 0; +} +EXPORT_SYMBOL(usbotg_init); + +void usbotg_uninit(struct fsl_usb2_platform_data *pdata) +{ + pr_debug("%s\n", __func__); + + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdata->xcvr_ops); + + pdata->regs = NULL; + otg_used--; +} +EXPORT_SYMBOL(usbotg_uninit); + +int fsl_usb_host_init(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_xcvr_ops *xops; + u32 tmp; + void __iomem *phy_reg = IO_ADDRESS(pdata->phy_regs); + + pr_debug("%s: pdev=0x%p pdata=0x%p\n", __func__, pdev, pdata); + + xops = fsl_usb_get_xcvr(pdata->transceiver); + if (!xops) { + printk(KERN_ERR "%s transceiver ops missing\n", pdata->name); + return -EINVAL; + } + pdata->xcvr_ops = xops; + pdata->xcvr_type = xops->xcvr_type; + pdata->pdev = pdev; + + if (xops->init) + xops->init(xops); + usb_phy_enable(pdata); + /* enable FS/LS device */ + tmp = __raw_readl(phy_reg + HW_USBPHY_CTRL); + tmp |= (BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_CTRL_ENUTMILEVEL3); + __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL); + + if (usb_register_remote_wakeup(pdev)) + pr_debug("%s port is not a wakeup source.\n", pdata->name); + + pr_debug("%s: %s success\n", __func__, pdata->name); + return 0; +} +EXPORT_SYMBOL(fsl_usb_host_init); + +void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata) +{ + pr_debug("%s\n", __func__); + + if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) + pdata->xcvr_ops->uninit(pdata->xcvr_ops); + + pdata->regs = NULL; +} +EXPORT_SYMBOL(fsl_usb_host_uninit); + +/* + * This function is used to debounce the reading value for id/vbus at + * the register of otgsc + */ +void usb_debounce_id_vbus(void) +{ + mdelay(3); +} +EXPORT_SYMBOL(usb_debounce_id_vbus); + +int usb_host_wakeup_irq(struct device *wkup_dev) +{ + return 0; +} +EXPORT_SYMBOL(usb_host_wakeup_irq); + +void usb_host_set_wakeup(struct device *wkup_dev, bool para) +{ + struct fsl_usb2_platform_data *pdata = wkup_dev->platform_data; + if (pdata->wake_up_enable) + pdata->wake_up_enable(pdata, para); +} +EXPORT_SYMBOL(usb_host_set_wakeup); + +#ifdef CONFIG_ARCH_MX28 +#define USBPHY_PHYS_ADDR USBPHY0_PHYS_ADDR +#endif + +int usb_event_is_otg_wakeup(void) +{ + u32 wakeup_irq_bits; + wakeup_irq_bits = BM_USBPHY_CTRL_RESUME_IRQ | BM_USBPHY_CTRL_WAKEUP_IRQ; + + if (__raw_readl(IO_ADDRESS(USBPHY_PHYS_ADDR) + HW_USBPHY_STATUS) && wakeup_irq_bits) { + return true; + } + return false; +} +EXPORT_SYMBOL(usb_event_is_otg_wakeup); + +int fsl_is_usb_plugged(void) +{ + return __raw_readl(IO_ADDRESS(USBPHY_PHYS_ADDR) + HW_USBPHY_STATUS) & \ + BM_USBPHY_STATUS_DEVPLUGIN_STATUS; +} +EXPORT_SYMBOL(fsl_is_usb_plugged); + +void fsl_enable_usb_plugindetect(void) +{ + __raw_writel(BM_USBPHY_CTRL_ENDEVPLUGINDETECT, + IO_ADDRESS(USBPHY_PHYS_ADDR) + HW_USBPHY_CTRL_SET); +} +EXPORT_SYMBOL(fsl_enable_usb_plugindetect); + diff --git a/arch/arm/plat-mxs/usb_wakeup.c b/arch/arm/plat-mxs/usb_wakeup.c new file mode 100644 index 000000000000..a020e85445f1 --- /dev/null +++ b/arch/arm/plat-mxs/usb_wakeup.c @@ -0,0 +1,222 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct wakeup_ctrl { + int wakeup_irq; + int usb_irq; + struct fsl_usb2_wakeup_platform_data *pdata; + struct task_struct *thread; + struct completion event; +}; +static struct wakeup_ctrl *g_ctrl; + +extern int usb_event_is_otg_wakeup(void); +extern void usb_debounce_id_vbus(void); + +static void wakeup_clk_gate(struct fsl_usb2_wakeup_platform_data *pdata, bool on) +{ + if (pdata->usb_clock_for_pm) + pdata->usb_clock_for_pm(on); +} + +static bool usb2_is_in_lowpower(struct wakeup_ctrl *ctrl) +{ + int i; + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + /* all the usb module related the wakeup is in lowpower mode */ + for (i = 0; i < 3; i++) { + if (pdata->usb_pdata[i]) { + if (pdata->usb_pdata[i]->phy_lowpower_suspend && !pdata->usb_pdata[i]->lowpower) + return false; + } + } + + return true; +} + +static void delay_process_wakeup(struct wakeup_ctrl *ctrl) +{ + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + disable_irq_nosync(ctrl->wakeup_irq); + if ((ctrl->usb_irq > 0) && (ctrl->wakeup_irq != ctrl->usb_irq)) + disable_irq_nosync(ctrl->usb_irq); + + pdata->usb_wakeup_is_pending = true; + complete(&ctrl->event); +} + +static irqreturn_t usb_wakeup_handler(int irq, void *_dev) +{ + struct wakeup_ctrl *ctrl = (struct wakeup_ctrl *)_dev; + irqreturn_t ret = IRQ_NONE; + if (usb2_is_in_lowpower(ctrl)) { + pr_debug("usb wakeup is here\n"); + delay_process_wakeup(ctrl); + ret = IRQ_HANDLED; + } + return ret; +} + +static enum usb_wakeup_event is_wakeup(struct fsl_usb2_platform_data *pdata) +{ + if (pdata->is_wakeup_event) + return pdata->is_wakeup_event(pdata); + else + return WAKEUP_EVENT_INVALID; +} + +static void wakeup_event_handler(struct wakeup_ctrl *ctrl) +{ + struct fsl_usb2_wakeup_platform_data *pdata = ctrl->pdata; + int already_waked = 0; + enum usb_wakeup_event wakeup_evt; + int i; + + wakeup_clk_gate(ctrl->pdata, true); + + /* In order to get the real id/vbus value */ + if (usb_event_is_otg_wakeup()) + usb_debounce_id_vbus(); + + for (i = 0; i < 3; i++) { + struct fsl_usb2_platform_data *usb_pdata = pdata->usb_pdata[i]; + if (usb_pdata) { + wakeup_evt = is_wakeup(usb_pdata); + if (wakeup_evt != WAKEUP_EVENT_INVALID) { + if (usb2_is_in_lowpower(ctrl)) + if (usb_pdata->usb_clock_for_pm) + usb_pdata->usb_clock_for_pm(true); + usb_pdata->lowpower = 0; + already_waked = 1; + if (usb_pdata->wakeup_handler) { + usb_pdata->wakeup_handler(usb_pdata); + } + } + } + } + + /* If nothing to wakeup, clear wakeup event */ + if ((already_waked == 0) && pdata->usb_wakeup_exhandle) + pdata->usb_wakeup_exhandle(); + + wakeup_clk_gate(ctrl->pdata, false); + pdata->usb_wakeup_is_pending = false; + wake_up(&pdata->wq); +} + +static int wakeup_event_thread(void *param) +{ + struct wakeup_ctrl *ctrl = (struct wakeup_ctrl *)param; + struct sched_param sch_param = {.sched_priority = 1}; + + sched_setscheduler(current, SCHED_RR, &sch_param); + while (1) { + wait_for_completion_interruptible(&ctrl->event); + if (kthread_should_stop()) + break; + wakeup_event_handler(ctrl); + enable_irq(ctrl->wakeup_irq); + if ((ctrl->usb_irq > 0) && (ctrl->wakeup_irq != ctrl->usb_irq)) + enable_irq(ctrl->usb_irq); + } + return 0; +} + +static int wakeup_dev_probe(struct platform_device *pdev) +{ + struct fsl_usb2_wakeup_platform_data *pdata; + struct wakeup_ctrl *ctrl = NULL; + int status; + unsigned long interrupt_flag; + + printk(KERN_INFO "IMX usb wakeup probe\n"); + + if (!pdev || !pdev->dev.platform_data) + return -ENODEV; + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + pdata = pdev->dev.platform_data; + ctrl->pdata = pdata; + init_waitqueue_head(&pdata->wq); + pdata->usb_wakeup_is_pending = false; + + init_completion(&ctrl->event); + ctrl->wakeup_irq = platform_get_irq(pdev, 0); + ctrl->usb_irq = platform_get_irq(pdev, 1); + if (ctrl->wakeup_irq != ctrl->wakeup_irq) + interrupt_flag = IRQF_DISABLED; + else + interrupt_flag = IRQF_SHARED; + status = request_irq(ctrl->wakeup_irq, usb_wakeup_handler, interrupt_flag, "usb_wakeup", (void *)ctrl); + if (status) + goto error1; + + ctrl->thread = kthread_run(wakeup_event_thread, (void *)ctrl, "usb_wakeup thread"); + status = IS_ERR(ctrl->thread) ? -1 : 0; + if (status) + goto error2; + g_ctrl = ctrl; + + printk(KERN_DEBUG "the wakeup pdata is 0x%p\n", pdata); + return 0; +error2: + free_irq(ctrl->wakeup_irq, (void *)ctrl); +error1: + kfree(ctrl); + return status; +} + +static int wakeup_dev_exit(struct platform_device *pdev) +{ + if (g_ctrl->thread) { + complete(&g_ctrl->event); + kthread_stop(g_ctrl->thread); + } + free_irq(g_ctrl->wakeup_irq, (void *)g_ctrl); + kfree(g_ctrl); + return 0; +} +static struct platform_driver wakeup_d = { + .probe = wakeup_dev_probe, + .remove = wakeup_dev_exit, + .driver = { + .name = "usb_wakeup", + }, +}; + +static int __init wakeup_dev_init(void) +{ + return platform_driver_register(&wakeup_d); +} +static void __exit wakeup_dev_uninit(void) +{ + platform_driver_unregister(&wakeup_d); +} + +subsys_initcall(wakeup_dev_init); +module_exit(wakeup_dev_uninit); + diff --git a/arch/arm/plat-mxs/utmixc.c b/arch/arm/plat-mxs/utmixc.c new file mode 100644 index 000000000000..8e842840e87a --- /dev/null +++ b/arch/arm/plat-mxs/utmixc.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +extern void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this); +extern void fsl_phy_usb_utmi_uninit(struct fsl_xcvr_ops *this); +extern void fsl_phy_set_power(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, int on); +#include +#include + + +static void set_vbus_draw(struct fsl_xcvr_ops *this, + struct fsl_usb2_platform_data *pdata, unsigned mA) +{ +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) + & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x20000) { + printk(KERN_INFO "USB enumeration done,current limitation release\r\n"); + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) | + BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT, REGS_POWER_BASE + + HW_POWER_5VCTRL); + } +#endif +} +static struct fsl_xcvr_ops utmi_ops = { + .name = "utmi", + .xcvr_type = PORTSC_PTS_UTMI, + .init = fsl_phy_usb_utmi_init, + .uninit = fsl_phy_usb_utmi_uninit, + .set_vbus_power = fsl_phy_set_power, + .set_vbus_draw = set_vbus_draw, +}; + +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops); + +static int __init utmixc_init(void) +{ + fsl_usb_xcvr_register(&utmi_ops); + return 0; +} + +extern void fsl_usb_xcvr_unregister(struct fsl_xcvr_ops *xcvr_ops); + +static void __exit utmixc_exit(void) +{ + fsl_usb_xcvr_unregister(&utmi_ops); +} + +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + fs_initcall(utmixc_init); +#else + subsys_initcall(utmixc_init); +#endif +module_exit(utmixc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("utmi xcvr driver"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 48cbdcb6bbd4..c43d5bc0bb75 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Mon Jul 12 21:10:14 2010 +# Last update: Thu Dec 30 02:31:56 2010 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -1319,7 +1319,7 @@ mistral MACH_MISTRAL MISTRAL 1315 msm MACH_MSM MSM 1316 ct5910 MACH_CT5910 CT5910 1317 ct5912 MACH_CT5912 CT5912 1318 -hynet_ine MACH_HYNET_INE HYNET_INE 1319 +argonst_mp MACH_HYNET_INE HYNET_INE 1319 hynet_app MACH_HYNET_APP HYNET_APP 1320 msm7200 MACH_MSM7200 MSM7200 1321 msm7600 MACH_MSM7600 MSM7600 1322 @@ -1777,7 +1777,7 @@ wdg002 MACH_WDG002 WDG002 1785 sg560adsl MACH_SG560ADSL SG560ADSL 1786 nextio_n2800_ica MACH_NEXTIO_N2800_ICA NEXTIO_N2800_ICA 1787 dove_db MACH_DOVE_DB DOVE_DB 1788 -marvell_newdb MACH_MARVELL_NEWDB MARVELL_NEWDB 1789 +dove_avng MACH_MARVELL_NEWDB MARVELL_NEWDB 1789 vandihud MACH_VANDIHUD VANDIHUD 1790 magx_e8 MACH_MAGX_E8 MAGX_E8 1791 magx_z6 MACH_MAGX_Z6 MAGX_Z6 1792 @@ -1877,7 +1877,7 @@ ued MACH_UED UED 1885 esiblade MACH_ESIBLADE ESIBLADE 1886 eye02 MACH_EYE02 EYE02 1887 imx27kbd MACH_IMX27KBD IMX27KBD 1888 -sst61vc010_fpga MACH_SST61VC010_FPGA SST61VC010_FPGA 1889 +p87_fpga MACH_SST61VC010_FPGA SST61VC010_FPGA 1889 kixvp435 MACH_KIXVP435 KIXVP435 1890 kixnp435 MACH_KIXNP435 KIXNP435 1891 africa MACH_AFRICA AFRICA 1892 @@ -2308,7 +2308,7 @@ ecac2378 MACH_ECAC2378 ECAC2378 2319 tazkiosk MACH_TAZKIOSK TAZKIOSK 2320 whiterabbit_mch MACH_WHITERABBIT_MCH WHITERABBIT_MCH 2321 sbox9263 MACH_SBOX9263 SBOX9263 2322 -oreo MACH_OREO OREO 2323 +oreo_camera MACH_OREO OREO 2323 smdk6442 MACH_SMDK6442 SMDK6442 2324 openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 incredible MACH_INCREDIBLE INCREDIBLE 2326 @@ -2321,7 +2321,7 @@ mx31txtr MACH_MX31TXTR MX31TXTR 2332 u380 MACH_U380 U380 2333 oamp3_hualu MACH_HUALU_BOARD HUALU_BOARD 2334 npcmx50 MACH_NPCMX50 NPCMX50 2335 -mx51_lange51 MACH_MX51_LANGE51 MX51_LANGE51 2336 +mx51_efikamx MACH_MX51_EFIKAMX MX51_EFIKAMX 2336 mx51_lange52 MACH_MX51_LANGE52 MX51_LANGE52 2337 riom MACH_RIOM RIOM 2338 comcas MACH_COMCAS COMCAS 2339 @@ -2355,7 +2355,7 @@ at91sam9263cs MACH_AT91SAM9263CS AT91SAM9263CS 2366 csb732 MACH_CSB732 CSB732 2367 u8500 MACH_U8500 U8500 2368 huqiu MACH_HUQIU HUQIU 2369 -mx51_kunlun MACH_MX51_KUNLUN MX51_KUNLUN 2370 +mx51_efikasb MACH_MX51_EFIKASB MX51_EFIKASB 2370 pmt1g MACH_PMT1G PMT1G 2371 htcelf MACH_HTCELF HTCELF 2372 armadillo420 MACH_ARMADILLO420 ARMADILLO420 2373 @@ -2374,7 +2374,7 @@ sch_m490 MACH_SCH_M490 SCH_M490 2386 rbl01 MACH_RBL01 RBL01 2387 omnifi MACH_OMNIFI OMNIFI 2388 otavalo MACH_OTAVALO OTAVALO 2389 -sienna MACH_SIENNA SIENNA 2390 +siena MACH_SIENNA SIENNA 2390 htc_excalibur_s620 MACH_HTC_EXCALIBUR_S620 HTC_EXCALIBUR_S620 2391 htc_opal MACH_HTC_OPAL HTC_OPAL 2392 touchbook MACH_TOUCHBOOK TOUCHBOOK 2393 @@ -2446,7 +2446,7 @@ siogentoo1 MACH_SIOGENTOO1 SIOGENTOO1 2458 siogentoo2 MACH_SIOGENTOO2 SIOGENTOO2 2459 sm3k MACH_SM3K SM3K 2460 acer_tempo_f900 MACH_ACER_TEMPO_F900 ACER_TEMPO_F900 2461 -sst61vc010_dev MACH_SST61VC010_DEV SST61VC010_DEV 2462 +p87_dev MACH_SST61VC010_DEV SST61VC010_DEV 2462 glittertind MACH_GLITTERTIND GLITTERTIND 2463 omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464 omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465 @@ -2498,7 +2498,7 @@ hiram MACH_HIRAM HIRAM 2510 phy3250 MACH_PHY3250 PHY3250 2511 ea3250 MACH_EA3250 EA3250 2512 fdi3250 MACH_FDI3250 FDI3250 2513 -whitestone MACH_WHITESTONE WHITESTONE 2514 +htcwhitestone MACH_WHITESTONE WHITESTONE 2514 at91sam9263nit MACH_AT91SAM9263NIT AT91SAM9263NIT 2515 ccmx51 MACH_CCMX51 CCMX51 2516 ccmx51js MACH_CCMX51JS CCMX51JS 2517 @@ -2561,7 +2561,7 @@ magnolia2 MACH_MAGNOLIA2 MAGNOLIA2 2573 emxx MACH_EMXX EMXX 2574 outlaw MACH_OUTLAW OUTLAW 2575 riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576 -riot_vox MACH_RIOT_VOX RIOT_VOX 2577 +riot_gx2 MACH_RIOT_VOX RIOT_VOX 2577 riot_x37 MACH_RIOT_X37 RIOT_X37 2578 mega25mx MACH_MEGA25MX MEGA25MX 2579 benzina2 MACH_BENZINA2 BENZINA2 2580 @@ -2582,7 +2582,7 @@ omap3_bulldog MACH_OMAP3_BULLDOG OMAP3_BULLDOG 2594 pca101 MACH_PCA101 PCA101 2595 buzzc MACH_BUZZC BUZZC 2596 sasie2 MACH_SASIE2 SASIE2 2597 -davinci_cio MACH_DAVINCI_CIO DAVINCI_CIO 2598 +davinci_dm6467_cio MACH_DAVINCI_CIO DAVINCI_CIO 2598 smartmeter_dl MACH_SMARTMETER_DL SMARTMETER_DL 2599 wzl6410 MACH_WZL6410 WZL6410 2600 wzl6410m MACH_WZL6410M WZL6410M 2601 @@ -2591,7 +2591,7 @@ wzl6410i MACH_WZL6410I WZL6410I 2603 spacecom1 MACH_SPACECOM1 SPACECOM1 2604 pingu920 MACH_PINGU920 PINGU920 2605 bravoc MACH_BRAVOC BRAVOC 2606 -cybo2440 MACH_CYBO2440 CYBO2440 2607 +mydev MACH_CYBO2440 CYBO2440 2607 vdssw MACH_VDSSW VDSSW 2608 romulus MACH_ROMULUS ROMULUS 2609 omap_magic MACH_OMAP_MAGIC OMAP_MAGIC 2610 @@ -2622,7 +2622,7 @@ kraken MACH_KRAKEN KRAKEN 2634 gw2388 MACH_GW2388 GW2388 2635 jadecpu MACH_JADECPU JADECPU 2636 carlisle MACH_CARLISLE CARLISLE 2637 -lux_sf9 MACH_LUX_SFT9 LUX_SFT9 2638 +lux_sf9 MACH_LUX_SF9 LUX_SF9 2638 nemid_tb MACH_NEMID_TB NEMID_TB 2639 terrier MACH_TERRIER TERRIER 2640 turbot MACH_TURBOT TURBOT 2641 @@ -2683,7 +2683,7 @@ lkevm MACH_LKEVM LKEVM 2695 mw6410 MACH_MW6410 MW6410 2696 terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697 cpu8000e MACH_CPU8000E CPU8000E 2698 -catania MACH_CATANIA CATANIA 2699 +catania_s MACH_CATANIA CATANIA 2699 tokyo MACH_TOKYO TOKYO 2700 msm7201a_surf MACH_MSM7201A_SURF MSM7201A_SURF 2701 msm7201a_ffa MACH_MSM7201A_FFA MSM7201A_FFA 2702 @@ -2750,7 +2750,7 @@ h6053 MACH_H6053 H6053 2762 smint01 MACH_SMINT01 SMINT01 2763 prtlvt2 MACH_PRTLVT2 PRTLVT2 2764 ap420 MACH_AP420 AP420 2765 -htcshift MACH_HTCSHIFT HTCSHIFT 2766 +htcclio MACH_HTCSHIFT HTCSHIFT 2766 davinci_dm365_fc MACH_DAVINCI_DM365_FC DAVINCI_DM365_FC 2767 msm8x55_surf MACH_MSM8X55_SURF MSM8X55_SURF 2768 msm8x55_ffa MACH_MSM8X55_FFA MSM8X55_FFA 2769 @@ -2761,7 +2761,7 @@ oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773 kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774 ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775 cns3420vb MACH_CNS3420VB CNS3420VB 2776 -lpc2 MACH_LPC2 LPC2 2777 +lpc_evo MACH_LPC2 LPC2 2777 olympus MACH_OLYMPUS OLYMPUS 2778 vortex MACH_VORTEX VORTEX 2779 s5pc200 MACH_S5PC200 S5PC200 2780 @@ -2788,7 +2788,7 @@ ti8168evm MACH_TI8168EVM TI8168EVM 2800 neocoreomap MACH_NEOCOREOMAP NEOCOREOMAP 2801 withings_wbp MACH_WITHINGS_WBP WITHINGS_WBP 2802 dbps MACH_DBPS DBPS 2803 -sbc9261 MACH_SBC9261 SBC9261 2804 +at91sam9261 MACH_SBC9261 SBC9261 2804 pcbfp0001 MACH_PCBFP0001 PCBFP0001 2805 speedy MACH_SPEEDY SPEEDY 2806 chrysaor MACH_CHRYSAOR CHRYSAOR 2807 @@ -2812,7 +2812,7 @@ p565 MACH_P565 P565 2824 acer_a4 MACH_ACER_A4 ACER_A4 2825 davinci_dm368_bip MACH_DAVINCI_DM368_BIP DAVINCI_DM368_BIP 2826 eshare MACH_ESHARE ESHARE 2827 -hw_omapl138_europa MACH_HW_OMAPL138_EUROPA HW_OMAPL138_EUROPA 2828 +omapl138_europa MACH_HW_OMAPL138_EUROPA HW_OMAPL138_EUROPA 2828 wlbargn MACH_WLBARGN WLBARGN 2829 bm170 MACH_BM170 BM170 2830 netspace_mini_v2 MACH_NETSPACE_MINI_V2 NETSPACE_MINI_V2 2831 @@ -2879,7 +2879,7 @@ davinci_picto MACH_DAVINCI_PICTO DAVINCI_PICTO 2891 mecha MACH_MECHA MECHA 2892 bubba3 MACH_BUBBA3 BUBBA3 2893 pupitre MACH_PUPITRE PUPITRE 2894 -tegra_harmony MACH_TEGRA_HARMONY TEGRA_HARMONY 2895 +tegra_unused MACH_TEGRA_HARMONY TEGRA_HARMONY 2895 tegra_vogue MACH_TEGRA_VOGUE TEGRA_VOGUE 2896 tegra_e1165 MACH_TEGRA_E1165 TEGRA_E1165 2897 simplenet MACH_SIMPLENET SIMPLENET 2898 @@ -2896,6 +2896,7 @@ e10 MACH_E10 E10 2908 app3k_robin MACH_APP3K_ROBIN APP3K_ROBIN 2909 pov15hd MACH_POV15HD POV15HD 2910 stella MACH_STELLA STELLA 2911 +htc_iolite MACH_MACH_HTC_IOLITE MACH_HTC_IOLITE 2912 linkstation_lschl MACH_LINKSTATION_LSCHL LINKSTATION_LSCHL 2913 netwalker MACH_NETWALKER NETWALKER 2914 acsx106 MACH_ACSX106 ACSX106 2915 @@ -2950,3 +2951,309 @@ davinci_dm365_dvr MACH_DAVINCI_DM365_DVR DAVINCI_DM365_DVR 2963 netviz MACH_NETVIZ NETVIZ 2964 flexibity MACH_FLEXIBITY FLEXIBITY 2965 wlan_computer MACH_WLAN_COMPUTER WLAN_COMPUTER 2966 +lpc24xx MACH_LPC24XX LPC24XX 2967 +spica MACH_SPICA SPICA 2968 +gpsdisplay MACH_GPSDISPLAY GPSDISPLAY 2969 +bipnet MACH_BIPNET BIPNET 2970 +overo_ctu_inertial MACH_OVERO_CTU_INERTIAL OVERO_CTU_INERTIAL 2971 +davinci_dm355_mmm MACH_DAVINCI_DM355_MMM DAVINCI_DM355_MMM 2972 +pc9260_v2 MACH_PC9260_V2 PC9260_V2 2973 +ptx7545 MACH_PTX7545 PTX7545 2974 +tm_efdc MACH_TM_EFDC TM_EFDC 2975 +remove_me MACH_WALDO1 WALDO1 2976 +omap3_waldo1 MACH_OMAP3_WALDO1 OMAP3_WALDO1 2977 +flyer MACH_FLYER FLYER 2978 +tornado3240 MACH_TORNADO3240 TORNADO3240 2979 +soli_01 MACH_SOLI_01 SOLI_01 2980 +omapl138_europalc MACH_OMAPL138_EUROPALC OMAPL138_EUROPALC 2981 +helios_v1 MACH_HELIOS_V1 HELIOS_V1 2982 +netspace_lite_v2 MACH_NETSPACE_LITE_V2 NETSPACE_LITE_V2 2983 +ssc MACH_SSC SSC 2984 +premierwave_en MACH_PREMIERWAVE_EN PREMIERWAVE_EN 2985 +wasabi MACH_WASABI WASABI 2986 +vivo_w MACH_VIVOW VIVOW 2987 +mx50_rdp MACH_MX50_RDP MX50_RDP 2988 +universal_c210 MACH_UNIVERSAL_C210 UNIVERSAL_C210 2989 +real6410 MACH_REAL6410 REAL6410 2990 +spx_sakura MACH_SPX_SAKURA SPX_SAKURA 2991 +ij3k_2440 MACH_IJ3K_2440 IJ3K_2440 2992 +omap3_bc10 MACH_OMAP3_BC10 OMAP3_BC10 2993 +thebe MACH_THEBE THEBE 2994 +rv082 MACH_RV082 RV082 2995 +armlguest MACH_ARMLGUEST ARMLGUEST 2996 +tjinc1000 MACH_TJINC1000 TJINC1000 2997 +dockstar MACH_DOCKSTAR DOCKSTAR 2998 +ax8008 MACH_AX8008 AX8008 2999 +gnet_sgce MACH_GNET_SGCE GNET_SGCE 3000 +pxwnas_500_1000 MACH_PXWNAS_500_1000 PXWNAS_500_1000 3001 +ea20 MACH_EA20 EA20 3002 +awm2 MACH_AWM2 AWM2 3003 +ti8148evm MACH_TI8148EVM TI8148EVM 3004 +seaboard MACH_SEABOARD SEABOARD 3005 +linkstation_chlv2 MACH_LINKSTATION_CHLV2 LINKSTATION_CHLV2 3006 +tera_pro2_rack MACH_TERA_PRO2_RACK TERA_PRO2_RACK 3007 +rubys MACH_RUBYS RUBYS 3008 +aquarius MACH_AQUARIUS AQUARIUS 3009 +mx53_ard MACH_MX53_ARD MX53_ARD 3010 +mx53_smd MACH_MX53_SMD MX53_SMD 3011 +lswxl MACH_LSWXL LSWXL 3012 +dove_avng_v3 MACH_DOVE_AVNG_V3 DOVE_AVNG_V3 3013 +sdi_ess_9263 MACH_SDI_ESS_9263 SDI_ESS_9263 3014 +jocpu550 MACH_JOCPU550 JOCPU550 3015 +msm8x60_rumi3 MACH_MSM8X60_RUMI3 MSM8X60_RUMI3 3016 +msm8x60_ffa MACH_MSM8X60_FFA MSM8X60_FFA 3017 +yanomami MACH_YANOMAMI YANOMAMI 3018 +gta04 MACH_GTA04 GTA04 3019 +cm_a510 MACH_CM_A510 CM_A510 3020 +omap3_rfs200 MACH_OMAP3_RFS200 OMAP3_RFS200 3021 +kx33xx MACH_KX33XX KX33XX 3022 +ptx7510 MACH_PTX7510 PTX7510 3023 +top9000 MACH_TOP9000 TOP9000 3024 +teenote MACH_TEENOTE TEENOTE 3025 +ts3 MACH_TS3 TS3 3026 +a0 MACH_A0 A0 3027 +fsm9xxx_surf MACH_FSM9XXX_SURF FSM9XXX_SURF 3028 +fsm9xxx_ffa MACH_FSM9XXX_FFA FSM9XXX_FFA 3029 +frrhwcdma60w MACH_FRRHWCDMA60W FRRHWCDMA60W 3030 +remus MACH_REMUS REMUS 3031 +at91cap7xdk MACH_AT91CAP7XDK AT91CAP7XDK 3032 +at91cap7stk MACH_AT91CAP7STK AT91CAP7STK 3033 +kt_sbc_sam9_1 MACH_KT_SBC_SAM9_1 KT_SBC_SAM9_1 3034 +at91sam9263router MACH_ORATISROUTER ORATISROUTER 3035 +armada_xp_db MACH_ARMADA_XP_DB ARMADA_XP_DB 3036 +spdm MACH_SPDM SPDM 3037 +gtib MACH_GTIB GTIB 3038 +dgm3240 MACH_DGM3240 DGM3240 3039 +iv_atlas_i_lpe MACH_ATLAS_I_LPE ATLAS_I_LPE 3040 +htcmega MACH_HTCMEGA HTCMEGA 3041 +tricorder MACH_TRICORDER TRICORDER 3042 +tx28 MACH_TX28 TX28 3043 +bstbrd MACH_BSTBRD BSTBRD 3044 +pwb3090 MACH_PWB3090 PWB3090 3045 +idea6410 MACH_IDEA6410 IDEA6410 3046 +qbc9263 MACH_QBC9263 QBC9263 3047 +borabora MACH_BORABORA BORABORA 3048 +valdez MACH_VALDEZ VALDEZ 3049 +ls9g20 MACH_LS9G20 LS9G20 3050 +mios_v1 MACH_MIOS_V1 MIOS_V1 3051 +s5pc110_crespo MACH_S5PC110_CRESPO S5PC110_CRESPO 3052 +controltek9g20 MACH_CONTROLTEK9G20 CONTROLTEK9G20 3053 +tin307 MACH_TIN307 TIN307 3054 +tin510 MACH_TIN510 TIN510 3055 +ep3505 MACH_EP3517 EP3517 3056 +bluecheese MACH_BLUECHEESE BLUECHEESE 3057 +tem3x30 MACH_TEM3X30 TEM3X30 3058 +harvest_desoto MACH_HARVEST_DESOTO HARVEST_DESOTO 3059 +msm8x60_qrdc MACH_MSM8X60_QRDC MSM8X60_QRDC 3060 +spear900 MACH_SPEAR900 SPEAR900 3061 +pcontrol_g20 MACH_PCONTROL_G20 PCONTROL_G20 3062 +rdstor MACH_RDSTOR RDSTOR 3063 +usdloader MACH_USDLOADER USDLOADER 3064 +tsoploader MACH_TSOPLOADER TSOPLOADER 3065 +kronos MACH_KRONOS KRONOS 3066 +ffcore MACH_FFCORE FFCORE 3067 +mone MACH_MONE MONE 3068 +unit2s MACH_UNIT2S UNIT2S 3069 +acer_a5 MACH_ACER_A5 ACER_A5 3070 +etherpro_isp MACH_ETHERPRO_ISP ETHERPRO_ISP 3071 +stretchs7000 MACH_STRETCHS7000 STRETCHS7000 3072 +p87_smartsim MACH_P87_SMARTSIM P87_SMARTSIM 3073 +tulip MACH_TULIP TULIP 3074 +sunflower MACH_SUNFLOWER SUNFLOWER 3075 +rib MACH_RIB RIB 3076 +clod MACH_CLOD CLOD 3077 +rump MACH_RUMP RUMP 3078 +tenderloin MACH_TENDERLOIN TENDERLOIN 3079 +shortloin MACH_SHORTLOIN SHORTLOIN 3080 +roml1 MACH_CRESPO CRESPO 3081 +antares MACH_ANTARES ANTARES 3082 +wb40n MACH_WB40N WB40N 3083 +herring MACH_HERRING HERRING 3084 +naxy400 MACH_NAXY400 NAXY400 3085 +naxy1200 MACH_NAXY1200 NAXY1200 3086 +vpr200 MACH_VPR200 VPR200 3087 +bug20 MACH_BUG20 BUG20 3088 +goflexnet MACH_GOFLEXNET GOFLEXNET 3089 +torbreck MACH_TORBRECK TORBRECK 3090 +saarb_mg1 MACH_SAARB_MG1 SAARB_MG1 3091 +callisto MACH_CALLISTO CALLISTO 3092 +multhsu MACH_MULTHSU MULTHSU 3093 +saluda MACH_SALUDA SALUDA 3094 +pemp_omap3_apollo MACH_PEMP_OMAP3_APOLLO PEMP_OMAP3_APOLLO 3095 +vc0718 MACH_VC0718 VC0718 3096 +mvblx MACH_MVBLX MVBLX 3097 +inhand_apeiron MACH_INHAND_APEIRON INHAND_APEIRON 3098 +inhand_fury MACH_INHAND_FURY INHAND_FURY 3099 +inhand_siren MACH_INHAND_SIREN INHAND_SIREN 3100 +hdnvp MACH_HDNVP HDNVP 3101 +softwinner MACH_SOFTWINNER SOFTWINNER 3102 +prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103 +nas6210 MACH_NAS6210 NAS6210 3104 +unisdev MACH_UNISDEV UNISDEV 3105 +sbca11 MACH_SBCA11 SBCA11 3106 +saga MACH_SAGA SAGA 3107 +ns_k330 MACH_NS_K330 NS_K330 3108 +tanna MACH_TANNA TANNA 3109 +imate8502 MACH_IMATE8502 IMATE8502 3110 +aspen MACH_ASPEN ASPEN 3111 +daintree_cwac MACH_DAINTREE_CWAC DAINTREE_CWAC 3112 +zmx25 MACH_ZMX25 ZMX25 3113 +maple1 MACH_MAPLE1 MAPLE1 3114 +qsd8x72_surf MACH_QSD8X72_SURF QSD8X72_SURF 3115 +qsd8x72_ffa MACH_QSD8X72_FFA QSD8X72_FFA 3116 +abilene MACH_ABILENE ABILENE 3117 +eigen_ttr MACH_EIGEN_TTR EIGEN_TTR 3118 +iomega_ix2_200 MACH_IOMEGA_IX2_200 IOMEGA_IX2_200 3119 +coretec_vcx7400 MACH_CORETEC_VCX7400 CORETEC_VCX7400 3120 +santiago MACH_SANTIAGO SANTIAGO 3121 +mx257sol MACH_MX257SOL MX257SOL 3122 +strasbourg MACH_STRASBOURG STRASBOURG 3123 +msm8x60_fluid MACH_MSM8X60_FLUID MSM8X60_FLUID 3124 +smartqv5 MACH_SMARTQV5 SMARTQV5 3125 +smartqv3 MACH_SMARTQV3 SMARTQV3 3126 +smartqv7 MACH_SMARTQV7 SMARTQV7 3127 +tegra_paz00 MACH_PAZ00 PAZ00 3128 +acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129 +htc_willow MACH_HTCWILLOW HTCWILLOW 3130 +fwbd_0404 MACH_FWBD_0404 FWBD_0404 3131 +hdgu MACH_HDGU HDGU 3132 +pyramid MACH_PYRAMID PYRAMID 3133 +epiphan MACH_EPIPHAN EPIPHAN 3134 +omap_bender MACH_OMAP_BENDER OMAP_BENDER 3135 +gurnard MACH_GURNARD GURNARD 3136 +gtl_it5100 MACH_GTL_IT5100 GTL_IT5100 3137 +bcm2708 MACH_BCM2708 BCM2708 3138 +mx51_ggc MACH_MX51_GGC MX51_GGC 3139 +sharespace MACH_SHARESPACE SHARESPACE 3140 +haba_knx_explorer MACH_HABA_KNX_EXPLORER HABA_KNX_EXPLORER 3141 +simtec_kirkmod MACH_SIMTEC_KIRKMOD SIMTEC_KIRKMOD 3142 +crux MACH_CRUX CRUX 3143 +mx51_bravo MACH_MX51_BRAVO MX51_BRAVO 3144 +charon MACH_CHARON CHARON 3145 +picocom3 MACH_PICOCOM3 PICOCOM3 3146 +picocom4 MACH_PICOCOM4 PICOCOM4 3147 +serrano MACH_SERRANO SERRANO 3148 +doubleshot MACH_DOUBLESHOT DOUBLESHOT 3149 +evsy MACH_EVSY EVSY 3150 +huashan MACH_HUASHAN HUASHAN 3151 +lausanne MACH_LAUSANNE LAUSANNE 3152 +emerald MACH_EMERALD EMERALD 3153 +tqma35 MACH_TQMA35 TQMA35 3154 +marvel MACH_MARVEL MARVEL 3155 +manuae MACH_MANUAE MANUAE 3156 +chacha MACH_CHACHA CHACHA 3157 +lemon MACH_LEMON LEMON 3158 +csc MACH_CSC CSC 3159 +gira_knxip_router MACH_GIRA_KNXIP_ROUTER GIRA_KNXIP_ROUTER 3160 +t20 MACH_T20 T20 3161 +hdmini MACH_HDMINI HDMINI 3162 +sciphone_g2 MACH_SCIPHONE_G2 SCIPHONE_G2 3163 +express MACH_EXPRESS EXPRESS 3164 +express_kt MACH_EXPRESS_KT EXPRESS_KT 3165 +maximasp MACH_MAXIMASP MAXIMASP 3166 +nitrogen_imx51 MACH_NITROGEN_IMX51 NITROGEN_IMX51 3167 +nitrogen_imx53 MACH_NITROGEN_IMX53 NITROGEN_IMX53 3168 +sunfire MACH_SUNFIRE SUNFIRE 3169 +arowana MACH_AROWANA AROWANA 3170 +tegra_daytona MACH_TEGRA_DAYTONA TEGRA_DAYTONA 3171 +tegra_swordfish MACH_TEGRA_SWORDFISH TEGRA_SWORDFISH 3172 +edison MACH_EDISON EDISON 3173 +svp8500v1 MACH_SVP8500V1 SVP8500V1 3174 +svp8500v2 MACH_SVP8500V2 SVP8500V2 3175 +svp5500 MACH_SVP5500 SVP5500 3176 +b5500 MACH_B5500 B5500 3177 +s5500 MACH_S5500 S5500 3178 +icon MACH_ICON ICON 3179 +elephant MACH_ELEPHANT ELEPHANT 3180 +msm8x60_charm_surf MACH_MSM8X60_FUSION MSM8X60_FUSION 3181 +shooter MACH_SHOOTER SHOOTER 3182 +spade_lte MACH_SPADE_LTE SPADE_LTE 3183 +philhwani MACH_PHILHWANI PHILHWANI 3184 +gsncomm MACH_GSNCOMM GSNCOMM 3185 +strasbourg_a2 MACH_STRASBOURG_A2 STRASBOURG_A2 3186 +mmm MACH_MMM MMM 3187 +davinci_dm365_bv MACH_DAVINCI_DM365_BV DAVINCI_DM365_BV 3188 +ag5evm MACH_AG5EVM AG5EVM 3189 +sc575plc MACH_SC575PLC SC575PLC 3190 +sc575hmi MACH_SC575IPC SC575IPC 3191 +omap3_tdm3730 MACH_OMAP3_TDM3730 OMAP3_TDM3730 3192 +rover_g7 MACH_G7 G7 3193 +top9000_eval MACH_TOP9000_EVAL TOP9000_EVAL 3194 +top9000_su MACH_TOP9000_SU TOP9000_SU 3195 +utm300 MACH_UTM300 UTM300 3196 +tsunagi MACH_TSUNAGI TSUNAGI 3197 +ts75xx MACH_TS75XX TS75XX 3198 +msm8x60_charm_ffa MACH_MSM8X60_FUSN_FFA MSM8X60_FUSN_FFA 3199 +ts47xx MACH_TS47XX TS47XX 3200 +da850_k5 MACH_DA850_K5 DA850_K5 3201 +ax502 MACH_AX502 AX502 3202 +igep0032 MACH_IGEP0032 IGEP0032 3203 +antero MACH_ANTERO ANTERO 3204 +synergy MACH_SYNERGY SYNERGY 3205 +ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 +wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 +punica MACH_PUNICA PUNICA 3208 +trimslice MACH_SBC_NT250 SBC_NT250 3209 +mx27_wmultra MACH_MX27_WMULTRA MX27_WMULTRA 3210 +mackerel MACH_MACKEREL MACKEREL 3211 +pvd_imx27 MACH_MACH_PVD_IMX27 MACH_PVD_IMX27 3212 +fa9x27 MACH_FA9X27 FA9X27 3213 +ns2816tb MACH_NS2816TB NS2816TB 3214 +ns2816_ntpad MACH_NS2816_NTPAD NS2816_NTPAD 3215 +ns2816_ntnb MACH_NS2816_NTNB NS2816_NTNB 3216 +kaen MACH_KAEN KAEN 3217 +nv1000 MACH_NV1000 NV1000 3218 +nuc950ts MACH_NUC950TS NUC950TS 3219 +nokia_rm680 MACH_NOKIA_RM680 NOKIA_RM680 3220 +ast2200 MACH_AST2200 AST2200 3221 +lead MACH_LEAD LEAD 3222 +unino1 MACH_UNINO1 UNINO1 3223 +greeco MACH_GREECO GREECO 3224 +verdi MACH_VERDI VERDI 3225 +dm6446_adbox MACH_DM6446_ADBOX DM6446_ADBOX 3226 +quad_salsa MACH_QUAD_SALSA QUAD_SALSA 3227 +abb_gma_1_1 MACH_ABB_GMA_1_1 ABB_GMA_1_1 3228 +svcid MACH_SVCID SVCID 3229 +msm8960_sim MACH_MSM8960_SIM MSM8960_SIM 3230 +msm8960_rumi3 MACH_MSM8960_RUMI3 MSM8960_RUMI3 3231 +icon_g MACH_ICON_G ICON_G 3232 +mb3 MACH_MB3 MB3 3233 +gsia18s MACH_GSIA18S GSIA18S 3234 +pivicc MACH_PIVICC PIVICC 3235 +pcm048 MACH_PCM048 PCM048 3236 +dds MACH_DDS DDS 3237 +chalten_xa1 MACH_CHALTEN_XA1 CHALTEN_XA1 3238 +ts48xx MACH_TS48XX TS48XX 3239 +tonga2_tfttimer MACH_TONGA2_TFTTIMER TONGA2_TFTTIMER 3240 +whistler MACH_WHISTLER WHISTLER 3241 +asl_phoenix MACH_ASL_PHOENIX ASL_PHOENIX 3242 +at91sam9263otlite MACH_AT91SAM9263OTLITE AT91SAM9263OTLITE 3243 +ddplug MACH_DDPLUG DDPLUG 3244 +d2plug MACH_D2PLUG D2PLUG 3245 +kzm9d MACH_KZM9D KZM9D 3246 +verdi_lte MACH_VERDI_LTE VERDI_LTE 3247 +nanozoom MACH_NANOZOOM NANOZOOM 3248 +dm3730_som_lv MACH_DM3730_SOM_LV DM3730_SOM_LV 3249 +dm3730_torpedo MACH_DM3730_TORPEDO DM3730_TORPEDO 3250 +anchovy MACH_ANCHOVY ANCHOVY 3251 +linux MACH_LINUX LINUX 3252 +re2rev20 MACH_RE2REV20 RE2REV20 3253 +re2rev21 MACH_RE2REV21 RE2REV21 3254 +cns21xx MACH_CNS21XX CNS21XX 3255 +rider MACH_RIDER RIDER 3257 +nsk330 MACH_NSK330 NSK330 3258 +cns2133evb MACH_CNS2133EVB CNS2133EVB 3259 +z3_816x_mod MACH_Z3_816X_MOD Z3_816X_MOD 3260 +z3_814x_mod MACH_Z3_814X_MOD Z3_814X_MOD 3261 +beect MACH_BEECT BEECT 3262 +dma_thunderbug MACH_DMA_THUNDERBUG DMA_THUNDERBUG 3263 +omn_at91sam9g20 MACH_OMN_AT91SAM9G20 OMN_AT91SAM9G20 3264 +mx25_e2s_uc MACH_MX25_E2S_UC MX25_E2S_UC 3265 +mione MACH_MIONE MIONE 3266 +top9000_rcu MACH_TOP9000_RCU TOP9000_RCU 3267 +top9000_bsl MACH_TOP9000_BSL TOP9000_BSL 3268 +kingdom MACH_KINGDOM KINGDOM 3269 +armadillo460 MACH_ARMADILLO460 ARMADILLO460 3270 +lq2 MACH_LQ2 LQ2 3271 +sweda_tms2 MACH_SWEDA_TMS2 SWEDA_TMS2 3272 +mx53_loco MACH_MX53_LOCO MX53_LOCO 3273 diff --git a/block/genhd.c b/block/genhd.c index 59a2db6fecef..aa628253bee1 100644 --- a/block/genhd.c +++ b/block/genhd.c @@ -1006,6 +1006,22 @@ static void disk_release(struct device *dev) free_part_stats(&disk->part0); kfree(disk); } + +static int disk_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct gendisk *disk = dev_to_disk(dev); + struct disk_part_iter piter; + struct hd_struct *part; + int cnt = 0; + + disk_part_iter_init(&piter, disk, 0); + while((part = disk_part_iter_next(&piter))) + cnt++; + disk_part_iter_exit(&piter); + add_uevent_var(env, "NPARTS=%u", cnt); + return 0; +} + struct class block_class = { .name = "block", }; @@ -1024,6 +1040,7 @@ static struct device_type disk_type = { .groups = disk_attr_groups, .release = disk_release, .devnode = block_devnode, + .uevent = disk_uevent, }; #ifdef CONFIG_PROC_FS diff --git a/crypto/Kconfig b/crypto/Kconfig index df332c140f95..1d2523aa896e 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -163,6 +163,14 @@ config CRYPTO_TEST help Quick & dirty crypto test module. +config CRYPTO_CRYPTODEV + tristate "Cryptodev (/dev/crypto) interface" + depends on CRYPTO + select CRYPTO_ALGAPI + help + Device /dev/crypto gives userspace programs access to + kernel crypto algorithms. + comment "Authenticated Encryption with Associated Data" config CRYPTO_CCM diff --git a/crypto/Makefile b/crypto/Makefile index d7e6441df7fe..b7f14d84d92c 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -86,6 +86,8 @@ obj-$(CONFIG_CRYPTO_ANSI_CPRNG) += ansi_cprng.o obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o obj-$(CONFIG_CRYPTO_GHASH) += ghash-generic.o +obj-$(CONFIG_CRYPTO_CRYPTODEV) += cryptodev.o + # # generic algorithms and the async_tx api # diff --git a/crypto/cryptodev.c b/crypto/cryptodev.c new file mode 100644 index 000000000000..5b8d00b02f28 --- /dev/null +++ b/crypto/cryptodev.c @@ -0,0 +1,558 @@ +/* + * Driver for /dev/crypto device (aka CryptoDev) + * + * Copyright (c) 2004 Michal Ludvig , SuSE Labs + * + * Device /dev/crypto provides an interface for + * accessing kernel CryptoAPI algorithms (ciphers, + * hashes) from userspace programs. + * + * /dev/crypto interface was originally introduced in + * OpenBSD and this module attempts to keep the API, + * although a bit extended. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_AUTHOR("Michal Ludvig "); +MODULE_DESCRIPTION("CryptoDev driver"); +MODULE_LICENSE("Dual BSD/GPL"); + +/* ====== Compile-time config ====== */ + +#define CRYPTODEV_STATS + +/* ====== Module parameters ====== */ + +static int verbosity = 0; +module_param(verbosity, int, 0644); +MODULE_PARM_DESC(verbosity, "0: normal, 1: verbose, 2: debug"); + +#ifdef CRYPTODEV_STATS +static int enable_stats = 0; +module_param(enable_stats, int, 0644); +MODULE_PARM_DESC(enable_stats, "collect statictics about cryptodev usage"); +#endif + +/* ====== Debug helpers ====== */ + +#define PFX "cryptodev: " +#define dprintk(level,severity,format,a...) \ + do { \ + if (level <= verbosity) \ + printk(severity PFX "%s[%u]: " format, \ + current->comm, current->pid, \ + ##a); \ + } while (0) + +/* ====== CryptoAPI ====== */ + +struct csession { + struct list_head entry; + struct semaphore sem; + struct crypto_blkcipher *tfm; + uint32_t sid; +#ifdef CRYPTODEV_STATS +#if ! ((COP_ENCRYPT < 2) && (COP_DECRYPT < 2)) +#error Struct csession.stat uses COP_{ENCRYPT,DECRYPT} as indices. Do something! +#endif + unsigned long long stat[2]; + size_t stat_max_size, stat_count; +#endif +}; + +struct fcrypt { + struct list_head list; + struct semaphore sem; +}; + +/* Prepare session for future use. */ +static int +crypto_create_session(struct fcrypt *fcr, struct session_op *sop) +{ + struct csession *ses_new, *ses_ptr; + struct crypto_blkcipher *tfm; + int ret = 0; + char alg_name[MAX_ALG_NAME_LEN+1]; + char alg_full_name[MAX_ALG_NAME_LEN+1]; + const char *mode; + u8 *keyp; + + /* Does the request make sense? */ + if (!sop->cipher == !sop->mac) { + dprintk(1, KERN_DEBUG, "Both 'cipher' and 'mac' set or unset.\n"); + return -EINVAL; + } + + /* Copy-in the algorithm name if necessary. */ + if (!sop->alg_namelen) { + /* Hmm, compatibility with OpenBSD CRYPTO_* constants... + Should we support it? */ + dprintk(2, KERN_DEBUG, "OpenBSD constants are not (yet?) supported.\n"); + return -EINVAL; + } + + if(sop->alg_namelen > MAX_ALG_NAME_LEN) { + dprintk(1, KERN_DEBUG, "Algorithm name too long (%zu > %u)\n", + sop->alg_namelen, MAX_ALG_NAME_LEN); + return -EINVAL; + } + + copy_from_user(alg_name, sop->alg_name, sop->alg_namelen); + alg_name[sop->alg_namelen] = '\0'; + + if(!sop->cipher) { + dprintk(2, KERN_DEBUG, "Hashes are not yet supported.\n"); + return -EINVAL; + } + + switch (sop->cipher & CRYPTO_FLAG_MASK) { + case CRYPTO_FLAG_ECB: mode = "ebc"; break; + case CRYPTO_FLAG_CBC: mode = "cbc"; break; + case CRYPTO_FLAG_CFB: mode = "cfb"; break; + case CRYPTO_FLAG_CTR: mode = "ctr"; break; +#if 0 + /* These modes are not yet supported. */ + case CRYPTO_FLAG_OFB: mode = "ofb"; break; +#endif + default: return -EINVAL; + } + snprintf(alg_full_name, sizeof(alg_full_name) - 1, "%s(%s)", mode, alg_name); + + /* Set-up crypto transform. */ + tfm = crypto_alloc_blkcipher(alg_full_name, 0, 0); + if (!tfm) { + dprintk(1, KERN_DEBUG, "Failed to load transform for %s %s\n", + alg_name, mode); + return -EINVAL; + } + +#if 0 + /* Was correct key length supplied? */ + if ((sop->keylen < crypto_tfm_alg_min_keysize(tfm)) || + (sop->keylen > crypto_tfm_alg_max_keysize(tfm))) { + dprintk(1, KERN_DEBUG, + "Wrong keylen '%zu' for algorithm '%s'. Use %u to %u.\n", + sop->keylen, alg_name, crypto_tfm_alg_min_keysize(tfm), + crypto_tfm_alg_max_keysize(tfm)); + crypto_free_blkcipher(tfm); + return -EINVAL; + } +#endif + + /* Copy the key from user and set to TFM. */ + keyp = kmalloc(sop->keylen, GFP_KERNEL); + if (keyp == NULL) { + dprintk(1, KERN_ERR, + "Unable to allocate key buffer.\n"); + crypto_free_blkcipher(tfm); + return -ENOMEM; + } + copy_from_user(keyp, sop->key, sop->keylen); + ret = crypto_blkcipher_setkey(tfm, keyp, sop->keylen); + kfree(keyp); + if (ret) { + dprintk(2, KERN_DEBUG, + "Setting key failed for %s-%zu-%s: flags=0x%X\n", + alg_name, sop->keylen*8, mode, crypto_blkcipher_tfm(tfm)->crt_flags); + dprintk(2, KERN_DEBUG, + "(see CRYPTO_TFM_RES_* in for details)\n"); + crypto_free_blkcipher(tfm); + return -EINVAL; + } + + /* Create a session and put it to the list. */ + ses_new = kmalloc(sizeof(*ses_new), GFP_KERNEL); + if(!ses_new) + return -ENOMEM; + + memset(ses_new, 0, sizeof(*ses_new)); + get_random_bytes(&ses_new->sid, sizeof(ses_new->sid)); + ses_new->tfm = tfm; + init_MUTEX(&ses_new->sem); + + down(&fcr->sem); +restart: + list_for_each_entry(ses_ptr, &fcr->list, entry) { + /* Check for duplicate SID */ + if (unlikely(ses_new->sid == ses_ptr->sid)) { + get_random_bytes(&ses_new->sid, sizeof(ses_new->sid)); + /* Unless we have a broken RNG this + shouldn't loop forever... ;-) */ + goto restart; + } + } + + list_add(&ses_new->entry, &fcr->list); + up(&fcr->sem); + + dprintk(2, KERN_DEBUG, "Added session 0x%08X (%s-%zu-%s)\n", + ses_new->sid, alg_name, sop->keylen*8, mode); + + /* Fill in some values for the user. */ + sop->ses = ses_new->sid; + sop->blocksize = crypto_blkcipher_blocksize(tfm); + + return 0; +} + +/* Everything that needs to be done when remowing a session. */ +static inline void +crypto_destroy_session(struct csession *ses_ptr) +{ + if(down_trylock(&ses_ptr->sem)) { + dprintk(2, KERN_DEBUG, "Waiting for semaphore of sid=0x%08X\n", + ses_ptr->sid); + down(&ses_ptr->sem); + } + dprintk(2, KERN_DEBUG, "Removed session 0x%08X\n", ses_ptr->sid); +#if defined(CRYPTODEV_STATS) + if(enable_stats) + dprintk(2, KERN_DEBUG, + "Usage in Bytes: enc=%llu, dec=%llu, max=%zu, avg=%lu, cnt=%zu\n", + ses_ptr->stat[COP_ENCRYPT], ses_ptr->stat[COP_DECRYPT], + ses_ptr->stat_max_size, ses_ptr->stat_count > 0 + ? ((unsigned long)(ses_ptr->stat[COP_ENCRYPT]+ + ses_ptr->stat[COP_DECRYPT]) / + ses_ptr->stat_count) : 0, + ses_ptr->stat_count); +#endif + crypto_free_blkcipher(ses_ptr->tfm); + ses_ptr->tfm = NULL; + up(&ses_ptr->sem); + kfree(ses_ptr); +} + +/* Look up a session by ID and remove. */ +static int +crypto_finish_session(struct fcrypt *fcr, uint32_t sid) +{ + struct csession *tmp, *ses_ptr; + struct list_head *head; + int ret = 0; + + down(&fcr->sem); + head = &fcr->list; + list_for_each_entry_safe(ses_ptr, tmp, head, entry) { + if(ses_ptr->sid == sid) { + list_del(&ses_ptr->entry); + crypto_destroy_session(ses_ptr); + break; + } + } + + if (!ses_ptr) { + dprintk(1, KERN_ERR, "Session with sid=0x%08X not found!\n", sid); + ret = -ENOENT; + } + up(&fcr->sem); + + return ret; +} + +/* Remove all sessions when closing the file */ +static int +crypto_finish_all_sessions(struct fcrypt *fcr) +{ + struct csession *tmp, *ses_ptr; + + down(&fcr->sem); + list_for_each_entry_safe(ses_ptr, tmp, &fcr->list, entry) { + list_del(&ses_ptr->entry); + crypto_destroy_session(ses_ptr); + } + up(&fcr->sem); + + return 0; +} + +/* Look up session by session ID. The returned session is locked. */ +static struct csession * +crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid) +{ + struct csession *ses_ptr; + + down(&fcr->sem); + list_for_each_entry(ses_ptr, &fcr->list, entry) { + if(ses_ptr->sid == sid) { + down(&ses_ptr->sem); + break; + } + } + up(&fcr->sem); + + return ses_ptr; +} + +/* This is the main crypto function - feed it with plaintext + and get a ciphertext (or vice versa :-) */ +static int +crypto_run(struct fcrypt *fcr, struct crypt_op *cop) +{ + char *data, *ivp; + char __user *src, __user *dst; + struct scatterlist sg; + struct csession *ses_ptr; + unsigned int ivsize; + size_t nbytes, bufsize; + int ret = 0; + struct blkcipher_desc desc; + + nbytes = cop->len; + + if (cop->op != COP_ENCRYPT && cop->op != COP_DECRYPT) { + dprintk(1, KERN_DEBUG, "invalid operation op=%u\n", cop->op); + return -EINVAL; + } + + ses_ptr = crypto_get_session_by_sid(fcr, cop->ses); + if (!ses_ptr) { + dprintk(1, KERN_ERR, "invalid session ID=0x%08X\n", cop->ses); + return -EINVAL; + } + + if (nbytes % crypto_blkcipher_blocksize(ses_ptr->tfm)) { + dprintk(1, KERN_ERR, + "data size (%zu) isn't a multiple of block size (%u)\n", + nbytes, crypto_blkcipher_blocksize(ses_ptr->tfm)); + ret = -EINVAL; + goto out_unlock; + } + + bufsize = PAGE_SIZE < nbytes ? PAGE_SIZE : nbytes; + data = (char*)__get_free_page(GFP_KERNEL); + + if (unlikely(!data)) { + ret = -ENOMEM; + goto out_unlock; + } + + ivsize = crypto_blkcipher_ivsize(ses_ptr->tfm); + + ivp = kmalloc(ivsize, GFP_KERNEL); + if (unlikely(!ivp)) { + free_page((unsigned long)data); + ret = -ENOMEM; + goto out_unlock; + } + + if (cop->iv) { + copy_from_user(ivp, cop->iv, ivsize); + crypto_blkcipher_set_iv(ses_ptr->tfm, ivp, ivsize); + } + + src = cop->src; + dst = cop->dst; + + desc.tfm = ses_ptr->tfm; + desc.info = NULL; + desc.flags = 0; + + while (nbytes > 0) { + size_t current_len = nbytes > bufsize ? bufsize : nbytes; + + copy_from_user(data, src, current_len); + + sg_set_buf(&sg, data, current_len); + + if (cop->op == COP_DECRYPT) + ret = crypto_blkcipher_decrypt(&desc, &sg, &sg, current_len); + else + ret = crypto_blkcipher_encrypt(&desc, &sg, &sg, current_len); + + if (unlikely(ret)) { + dprintk(0, KERN_ERR, "CryptoAPI failure: flags=0x%x\n", + crypto_blkcipher_tfm(ses_ptr->tfm)->crt_flags); + goto out; + } + + copy_to_user(dst, data, current_len); + + nbytes -= current_len; + src += current_len; + dst += current_len; + } + +#if defined(CRYPTODEV_STATS) + if (enable_stats) { + /* this is safe - we check cop->op at the function entry */ + ses_ptr->stat[cop->op] += cop->len; + if (ses_ptr->stat_max_size < cop->len) + ses_ptr->stat_max_size = cop->len; + ses_ptr->stat_count++; + } +#endif + +out: + free_page((unsigned long)data); + + kfree(ivp); + +out_unlock: + up(&ses_ptr->sem); + + return ret; +} + +/* ====== /dev/crypto ====== */ + +static int +cryptodev_open(struct inode *inode, struct file *filp) +{ + struct fcrypt *fcr; + + fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); + if(!fcr) + return -ENOMEM; + + memset(fcr, 0, sizeof(*fcr)); + init_MUTEX(&fcr->sem); + INIT_LIST_HEAD(&fcr->list); + filp->private_data = fcr; + + return 0; +} + +static int +cryptodev_release(struct inode *inode, struct file *filp) +{ + struct fcrypt *fcr = filp->private_data; + + if(fcr) { + crypto_finish_all_sessions(fcr); + kfree(fcr); + filp->private_data = NULL; + } + return 0; +} + +static int +clonefd(struct file *filp) +{ + int fd; + + fd = get_unused_fd(); + if (fd >= 0) { + get_file(filp); + fd_install(fd, filp); + } + + return fd; +} + +static int +cryptodev_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + struct session_op sop; + struct crypt_op cop; + struct fcrypt *fcr = filp->private_data; + uint32_t ses; + int ret, fd; + + if (!fcr) + BUG(); + + switch (cmd) { + case CRIOGET: + fd = clonefd(filp); + put_user(fd, (int*)arg); + return 0; + + case CIOCGSESSION: + copy_from_user(&sop, (void*)arg, sizeof(sop)); + ret = crypto_create_session(fcr, &sop); + if (ret) + return ret; + copy_to_user((void*)arg, &sop, sizeof(sop)); + return 0; + + case CIOCFSESSION: + get_user(ses, (uint32_t*)arg); + ret = crypto_finish_session(fcr, ses); + return ret; + + case CIOCCRYPT: + copy_from_user(&cop, (void*)arg, sizeof(cop)); + ret = crypto_run(fcr, &cop); + copy_to_user((void*)arg, &cop, sizeof(cop)); + return ret; + + default: + return -EINVAL; + } +} + +struct file_operations cryptodev_fops = { + .owner = THIS_MODULE, + .open = cryptodev_open, + .release = cryptodev_release, + .ioctl = cryptodev_ioctl, +}; + +struct miscdevice cryptodev = { + .minor = CRYPTODEV_MINOR, + .name = "crypto", + .fops = &cryptodev_fops, +}; + +static int +cryptodev_register(void) +{ + int rc; + + rc = misc_register (&cryptodev); + if (rc) { + printk(KERN_ERR PFX "registeration of /dev/crypto failed\n"); + return rc; + } + + return 0; +} + +static void +cryptodev_deregister(void) +{ + misc_deregister(&cryptodev); +} + +/* ====== Module init/exit ====== */ + +int __init +init_cryptodev(void) +{ + int rc; + + rc = cryptodev_register(); + if (rc) + return rc; + + printk(KERN_INFO PFX "driver loaded.\n"); + + return 0; +} + +void __exit +exit_cryptodev(void) +{ + cryptodev_deregister(); + printk(KERN_INFO PFX "driver unloaded.\n"); +} + +module_init(init_cryptodev); +module_exit(exit_cryptodev); diff --git a/drivers/Kconfig b/drivers/Kconfig index a2b902f4d437..21e6f277c8dc 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -111,4 +111,6 @@ source "drivers/xen/Kconfig" source "drivers/staging/Kconfig" source "drivers/platform/Kconfig" + +source "drivers/mxc/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 91874e048552..fd1cbd50acaf 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_INPUT) += input/ obj-$(CONFIG_I2O) += message/ obj-$(CONFIG_RTC_LIB) += rtc/ obj-y += i2c/ media/ +obj-$(CONFIG_I2C_SLAVE) += i2c-slave/ obj-$(CONFIG_PPS) += pps/ obj-$(CONFIG_W1) += w1/ obj-$(CONFIG_POWER_SUPPLY) += power/ @@ -92,6 +93,8 @@ obj-$(CONFIG_EISA) += eisa/ obj-y += lguest/ obj-$(CONFIG_CPU_FREQ) += cpufreq/ obj-$(CONFIG_CPU_IDLE) += cpuidle/ +obj-y += idle/ +obj-$(CONFIG_ARCH_MXC) += mxc/ obj-$(CONFIG_MMC) += mmc/ obj-$(CONFIG_MEMSTICK) += memstick/ obj-$(CONFIG_NEW_LEDS) += leds/ diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index aa85a98d3a4f..c3205953863e 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -382,6 +382,14 @@ config PATA_EFAR If unsure, say N. +config PATA_FSL + tristate "Freescale on-chip PATA support" + depends on (ARCH_MX5 || ARCH_MX37 || ARCH_MX35 || ARCH_MX3 || ARCH_MX27) + help + On Freescale processors, say Y here if you wish to use the on-chip + ATA interface. + If you are unsure, say N to this. + config PATA_HPT366 tristate "HPT 366/368 PATA support" depends on PCI diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 7ef89d73df63..04e27237b993 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_PATA_CS5535) += pata_cs5535.o obj-$(CONFIG_PATA_CS5536) += pata_cs5536.o obj-$(CONFIG_PATA_CYPRESS) += pata_cypress.o obj-$(CONFIG_PATA_EFAR) += pata_efar.o +obj-$(CONFIG_PATA_FSL) += pata_fsl.o obj-$(CONFIG_PATA_HPT366) += pata_hpt366.o obj-$(CONFIG_PATA_HPT37X) += pata_hpt37x.o obj-$(CONFIG_PATA_HPT3X2N) += pata_hpt3x2n.o diff --git a/drivers/ata/pata_fsl.c b/drivers/ata/pata_fsl.c new file mode 100644 index 000000000000..42976f2193aa --- /dev/null +++ b/drivers/ata/pata_fsl.c @@ -0,0 +1,1041 @@ +/* + * Freescale integrated PATA driver + */ + +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "pata_fsl" + +struct pata_fsl_priv { + int ultra; + u8 *fsl_ata_regs; + struct clk *clk; + int dma_rchan; + int dma_wchan; + int dma_done; + int dma_dir; + unsigned int adma_des_paddr; + unsigned int *adma_des_tp; +}; + +struct adma_bd { + unsigned char *sg_buf; + unsigned char *work_buf; + unsigned int dma_address; + int length; +}; + +struct adma_bulk { + struct adma_bd adma_bd_table[64]; + struct ata_queued_cmd *qc; + int sg_ents; + int reserved[2]; +}; + +enum { + /* various constants */ + FSL_ATA_MAX_SG_LEN = ATA_DMA_BOUNDARY << 1, + + /* offsets to registers */ + FSL_ATA_TIMING_REGS = 0x00, + FSL_ATA_FIFO_FILL = 0x20, + FSL_ATA_CONTROL = 0x24, + FSL_ATA_INT_PEND = 0x28, + FSL_ATA_INT_EN = 0x2C, + FSL_ATA_INT_CLEAR = 0x30, + FSL_ATA_FIFO_ALARM = 0x34, + FSL_ATA_ADMA_ERROR_STATUS = 0x38, + FSL_ATA_SYS_DMA_BADDR = 0x3C, + FSL_ATA_ADMA_SYS_ADDR = 0x40, + FSL_ATA_BLOCK_COUNT = 0x48, + FSL_ATA_BURST_LENGTH = 0x4C, + FSL_ATA_SECTOR_SIZE = 0x50, + FSL_ATA_DRIVE_DATA = 0xA0, + FSL_ATA_DRIVE_CONTROL = 0xD8, + + /* bits within FSL_ATA_CONTROL */ + FSL_ATA_CTRL_DMA_SRST = 0x1000, + FSL_ATA_CTRL_DMA_64ADMA = 0x800, + FSL_ATA_CTRL_DMA_32ADMA = 0x400, + FSL_ATA_CTRL_DMA_STAT_STOP = 0x200, + FSL_ATA_CTRL_DMA_ENABLE = 0x100, + FSL_ATA_CTRL_FIFO_RST_B = 0x80, + FSL_ATA_CTRL_ATA_RST_B = 0x40, + FSL_ATA_CTRL_FIFO_TX_EN = 0x20, + FSL_ATA_CTRL_FIFO_RCV_EN = 0x10, + FSL_ATA_CTRL_DMA_PENDING = 0x08, + FSL_ATA_CTRL_DMA_ULTRA = 0x04, + FSL_ATA_CTRL_DMA_WRITE = 0x02, + FSL_ATA_CTRL_IORDY_EN = 0x01, + + /* bits within the interrupt control registers */ + FSL_ATA_INTR_ATA_INTRQ1 = 0x80, + FSL_ATA_INTR_FIFO_UNDERFLOW = 0x40, + FSL_ATA_INTR_FIFO_OVERFLOW = 0x20, + FSL_ATA_INTR_CTRL_IDLE = 0x10, + FSL_ATA_INTR_ATA_INTRQ2 = 0x08, + FSL_ATA_INTR_DMA_ERR = 0x04, + FSL_ATA_INTR_DMA_TRANS_OVER = 0x02, + + /* ADMA Addr Descriptor Attribute Filed */ + FSL_ADMA_DES_ATTR_VALID = 0x01, + FSL_ADMA_DES_ATTR_END = 0x02, + FSL_ADMA_DES_ATTR_INT = 0x04, + FSL_ADMA_DES_ATTR_SET = 0x10, + FSL_ADMA_DES_ATTR_TRAN = 0x20, + FSL_ADMA_DES_ATTR_LINK = 0x30, +}; + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 5 PIO modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t0, t1, t2_8, t2_16, t2i, t4, t9, tA; +} pio_specs[] = { + [0] = { + .t0 = 600, .t1 = 70, .t2_8 = 290, .t2_16 = 165, .t2i = 0, .t4 = + 30, .t9 = 20, .tA = 50,}, + [1] = { + .t0 = 383, .t1 = 50, .t2_8 = 290, .t2_16 = 125, .t2i = 0, .t4 = + 20, .t9 = 15, .tA = 50,}, + [2] = { + .t0 = 240, .t1 = 30, .t2_8 = 290, .t2_16 = 100, .t2i = 0, .t4 = + 15, .t9 = 10, .tA = 50,}, + [3] = { + .t0 = 180, .t1 = 30, .t2_8 = 80, .t2_16 = 80, .t2i = 0, .t4 = + 10, .t9 = 10, .tA = 50,}, + [4] = { + .t0 = 120, .t1 = 25, .t2_8 = 70, .t2_16 = 70, .t2i = 0, .t4 = + 10, .t9 = 10, .tA = 50,}, + }; + +#define NR_PIO_SPECS (sizeof pio_specs / sizeof pio_specs[0]) + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 3 MDMA modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t0M, tD, tH, tJ, tKW, tM, tN, tJNH; +} mdma_specs[] = { + [0] = { + .t0M = 480, .tD = 215, .tH = 20, .tJ = 20, .tKW = 215, .tM = 50, .tN = + 15, .tJNH = 20,}, + [1] = { + .t0M = 150, .tD = 80, .tH = 15, .tJ = 5, .tKW = 50, .tM = 30, .tN = + 10, .tJNH = 15,}, + [2] = { + .t0M = 120, .tD = 70, .tH = 10, .tJ = 5, .tKW = 25, .tM = 25, .tN = + 10, .tJNH = 10,}, + }; + +#define NR_MDMA_SPECS (sizeof mdma_specs / sizeof mdma_specs[0]) + +/* + * This structure contains the timing parameters for + * ATA bus timing in the 6 UDMA modes. The timings + * are in nanoseconds, and are converted to clock + * cycles before being stored in the ATA controller + * timing registers. + */ +static struct { + short t2CYC, tCYC, tDS, tDH, tDVS, tDVH, tCVS, tCVH, tFS_min, tLI_max, + tMLI, tAZ, tZAH, tENV_min, tSR, tRFS, tRP, tACK, tSS, tDZFS; +} udma_specs[] = { + [0] = { + .t2CYC = 235, .tCYC = 114, .tDS = 15, .tDH = 5, .tDVS = 70, .tDVH = + 6, .tCVS = 70, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 50, .tRFS = 75, .tRP = 160, .tACK = 20, .tSS = + 50, .tDZFS = 80,}, + [1] = { + .t2CYC = 156, .tCYC = 75, .tDS = 10, .tDH = 5, .tDVS = 48, .tDVH = + 6, .tCVS = 48, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 30, .tRFS = 70, .tRP = 125, .tACK = 20, .tSS = + 50, .tDZFS = 63,}, + [2] = { + .t2CYC = 117, .tCYC = 55, .tDS = 7, .tDH = 5, .tDVS = 34, .tDVH = + 6, .tCVS = 34, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 20, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS = + 50, .tDZFS = 47,}, + [3] = { + .t2CYC = 86, .tCYC = 39, .tDS = 7, .tDH = 5, .tDVS = 20, .tDVH = + 6, .tCVS = 20, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 20, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS = + 50, .tDZFS = 35,}, + [4] = { + .t2CYC = 57, .tCYC = 25, .tDS = 5, .tDH = 5, .tDVS = 7, .tDVH = + 6, .tCVS = 7, .tCVH = 6, .tFS_min = 0, .tLI_max = + 100, .tMLI = 20, .tAZ = 10, .tZAH = 20, .tENV_min = + 20, .tSR = 50, .tRFS = 60, .tRP = 100, .tACK = 20, .tSS = + 50, .tDZFS = 25,}, + [5] = { + .t2CYC = 38, .tCYC = 17, .tDS = 4, .tDH = 5, .tDVS = 5, .tDVH = + 6, .tCVS = 10, .tCVH = 10, .tFS_min = + 0, .tLI_max = 75, .tMLI = 20, .tAZ = 10, .tZAH = + 20, .tENV_min = 20, .tSR = 20, .tRFS = + 50, .tRP = 85, .tACK = 20, .tSS = 50, .tDZFS = 40,}, +}; + +#define NR_UDMA_SPECS (sizeof udma_specs / sizeof udma_specs[0]) + +struct fsl_ata_time_regs { + u8 time_off, time_on, time_1, time_2w; + u8 time_2r, time_ax, time_pio_rdx, time_4; + u8 time_9, time_m, time_jn, time_d; + u8 time_k, time_ack, time_env, time_rpx; + u8 time_zah, time_mlix, time_dvh, time_dzfs; + u8 time_dvs, time_cvh, time_ss, time_cyc; +}; + +static struct regulator *io_reg; +static struct regulator *core_reg; +static struct adma_bulk adma_info; + +static void +update_timing_config(struct fsl_ata_time_regs *tp, struct ata_host *host) +{ + u32 *lp = (u32 *) tp; + struct pata_fsl_priv *priv = host->private_data; + u32 *ctlp = (u32 *) priv->fsl_ata_regs; + int i; + + for (i = 0; i < 5; i++) { + __raw_writel(*lp, ctlp); + lp++; + ctlp++; + } +} + +/*! + * Calculate values for the ATA bus timing registers and store + * them into the hardware. + * + * @param xfer_mode specifies XFER xfer_mode + * @param pdev specifies platform_device + * + * @return EINVAL speed out of range, or illegal mode + */ +static int set_ata_bus_timing(u8 xfer_mode, struct platform_device *pdev) +{ + struct ata_host *host = dev_get_drvdata(&pdev->dev); + struct pata_fsl_priv *priv = host->private_data; + + /* get the bus clock cycle time, in ns */ + int T = 1 * 1000 * 1000 * 1000 / clk_get_rate(priv->clk); + struct fsl_ata_time_regs tr = { 0 }; + + /* + * every mode gets the same t_off and t_on + */ + tr.time_off = 3; + tr.time_on = 3; + + if (xfer_mode >= XFER_UDMA_0) { + int speed = xfer_mode - XFER_UDMA_0; + if (speed >= NR_UDMA_SPECS) + return -EINVAL; + + tr.time_ack = (udma_specs[speed].tACK + T) / T; + tr.time_env = (udma_specs[speed].tENV_min + T) / T; + tr.time_rpx = (udma_specs[speed].tRP + T) / T + 2; + tr.time_zah = (udma_specs[speed].tZAH + T) / T; + tr.time_mlix = (udma_specs[speed].tMLI + T) / T; + tr.time_dvh = (udma_specs[speed].tDVH + T) / T + 1; + tr.time_dzfs = (udma_specs[speed].tDZFS + T) / T; + + tr.time_dvs = (udma_specs[speed].tDVS + T) / T; + tr.time_cvh = (udma_specs[speed].tCVH + T) / T; + tr.time_ss = (udma_specs[speed].tSS + T) / T; + tr.time_cyc = (udma_specs[speed].tCYC + T) / T; + } else if (xfer_mode >= XFER_MW_DMA_0) { + int speed = xfer_mode - XFER_MW_DMA_0; + if (speed >= NR_MDMA_SPECS) + return -EINVAL; + + tr.time_m = (mdma_specs[speed].tM + T) / T; + tr.time_jn = (mdma_specs[speed].tJNH + T) / T; + tr.time_d = (mdma_specs[speed].tD + T) / T; + + tr.time_k = (mdma_specs[speed].tKW + T) / T; + } else { + int speed = xfer_mode - XFER_PIO_0; + if (speed >= NR_PIO_SPECS) + return -EINVAL; + + tr.time_1 = (pio_specs[speed].t1 + T) / T; + tr.time_2w = (pio_specs[speed].t2_8 + T) / T; + + tr.time_2r = (pio_specs[speed].t2_8 + T) / T; + tr.time_ax = (pio_specs[speed].tA + T) / T + 2; + tr.time_pio_rdx = 1; + tr.time_4 = (pio_specs[speed].t4 + T) / T; + + tr.time_9 = (pio_specs[speed].t9 + T) / T; + } + + update_timing_config(&tr, host); + + return 0; +} + +static void pata_fsl_set_piomode(struct ata_port *ap, struct ata_device *adev) +{ + set_ata_bus_timing(adev->pio_mode, to_platform_device(ap->dev)); +} + +static void pata_fsl_set_dmamode(struct ata_port *ap, struct ata_device *adev) +{ + struct pata_fsl_priv *priv = ap->host->private_data; + + priv->ultra = adev->dma_mode >= XFER_UDMA_0; + + set_ata_bus_timing(adev->dma_mode, to_platform_device(ap->dev)); +} + +static int pata_fsl_port_start(struct ata_port *ap) +{ + return 0; +} + +static void pata_adma_bulk_unmap(struct ata_queued_cmd *qc) +{ + int i; + struct adma_bd *bdp = adma_info.adma_bd_table; + if (adma_info.qc == NULL) + return; + BUG_ON(adma_info.qc != qc); + + adma_info.qc = NULL; + + for (i = 0; i < adma_info.sg_ents; i++) { + if (bdp->work_buf != bdp->sg_buf) { + if (qc->dma_dir == DMA_FROM_DEVICE) { + dma_unmap_single(qc->ap->dev, bdp->dma_address, + bdp->dma_address, DMA_FROM_DEVICE); + memcpy(bdp->sg_buf, bdp->work_buf, bdp->length); + } + dma_free_coherent(qc->ap->dev, bdp->length, + bdp->work_buf, bdp->dma_address); + } + bdp->work_buf = bdp->sg_buf = NULL; + bdp++; + } +} + +static int pata_adma_bulk_map(struct ata_queued_cmd *qc) +{ + unsigned int si; + struct scatterlist *sg; + struct adma_bd *bdp = adma_info.adma_bd_table; + + BUG_ON(adma_info.qc); + + adma_info.qc = qc; + adma_info.sg_ents = 0; + + for_each_sg(qc->sg, sg, qc->n_elem, si) { + /* + * The ADMA mode is used setup the ADMA descriptor table + */ + bdp->sg_buf = sg_virt(sg); + bdp->length = sg->length; + if (sg->dma_address & 0xFFF) { + bdp->work_buf = + dma_alloc_coherent(qc->ap->dev, bdp->length, + &bdp->dma_address, GFP_KERNEL); + if (!bdp->work_buf) { + printk(KERN_WARNING + "can not allocate aligned buffer\n"); + goto fail; + } + if (qc->dma_dir == DMA_TO_DEVICE) + memcpy(bdp->work_buf, bdp->sg_buf, bdp->length); + } else { + bdp->work_buf = bdp->sg_buf; + bdp->dma_address = sg->dma_address; + } + + adma_info.sg_ents++; + bdp++; + } + return 0; + fail: + pata_adma_bulk_unmap(qc); + return -1; +} + +static void dma_callback(void *arg, int error_status, unsigned int count) +{ + struct ata_port *ap = arg; + struct pata_fsl_priv *priv = ap->host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + + priv->dma_done = 1; + /* + * DMA is finished, so unmask INTRQ from the drive to allow the + * normal ISR to fire. + */ + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, ata_regs + FSL_ATA_INT_EN); +} + +static irqreturn_t pata_fsl_adma_intr(int irq, void *dev_instance) +{ + struct ata_host *host = dev_instance; + struct pata_fsl_priv *priv = host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + unsigned int handled = 0; + unsigned int i; + unsigned long flags; + unsigned int pending = __raw_readl(ata_regs + FSL_ATA_INT_PEND); + + if (FSL_ATA_INTR_DMA_TRANS_OVER & pending) { + priv->dma_done = 1; + __raw_writel(pending, ata_regs + FSL_ATA_INT_CLEAR); + handled = 1; + } else if (FSL_ATA_INTR_DMA_ERR & pending) { + printk(KERN_ERR "dma err status 0x%x ...\n", + __raw_readl(ata_regs + FSL_ATA_ADMA_ERROR_STATUS)); + __raw_writel(pending, ata_regs + FSL_ATA_INT_CLEAR); + handled = 1; + i = __raw_readl(ata_regs + FSL_ATA_CONTROL) && 0xFF; + i |= FSL_ATA_CTRL_DMA_SRST | FSL_ATA_CTRL_DMA_32ADMA | + FSL_ATA_CTRL_DMA_ENABLE; + __raw_writel(i, ata_regs + FSL_ATA_CONTROL); + } + + spin_lock_irqsave(&host->lock, flags); + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap; + struct ata_queued_cmd *qc; + + ap = host->ports[i]; + + qc = ata_qc_from_tag(ap, ap->link.active_tag); + raw_local_irq_restore(flags); + pata_adma_bulk_unmap(qc); + raw_local_irq_save(flags); + if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) + handled |= ata_bmdma_port_intr(ap, qc); + } + + spin_unlock_irqrestore(&host->lock, flags); + + return IRQ_RETVAL(handled); +} + +static int pata_fsl_check_atapi_dma(struct ata_queued_cmd *qc) +{ + return 1; /* ATAPI DMA not yet supported */ +} + +unsigned long pata_fsl_bmdma_mode_filter(struct ata_device *adev, + unsigned long xfer_mask) +{ + /* Capability of the controller has been specified in the + * platform data. Do not filter any modes, just return + * the xfer_mask */ + return xfer_mask; +} + +static void pata_fsl_bmdma_setup(struct ata_queued_cmd *qc) +{ + int chan, i; + int dma_mode = 0, dma_ultra; + u32 ata_control; + struct ata_port *ap = qc->ap; + struct pata_fsl_priv *priv = ap->host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + struct fsl_ata_platform_data *plat = ap->dev->platform_data; + int err; + unsigned int si; + + priv->dma_dir = qc->dma_dir; + + /* + * Configure the on-chip ATA interface hardware. + */ + dma_ultra = priv->ultra ? FSL_ATA_CTRL_DMA_ULTRA : 0; + + ata_control = FSL_ATA_CTRL_FIFO_RST_B | + FSL_ATA_CTRL_ATA_RST_B | FSL_ATA_CTRL_DMA_PENDING | dma_ultra; + if (plat->adma_flag) + ata_control |= FSL_ATA_CTRL_DMA_32ADMA | + FSL_ATA_CTRL_DMA_ENABLE; + + if (qc->dma_dir == DMA_TO_DEVICE) { + chan = priv->dma_wchan; + ata_control |= FSL_ATA_CTRL_FIFO_TX_EN | FSL_ATA_CTRL_DMA_WRITE; + dma_mode = MXC_DMA_MODE_WRITE; + } else { + chan = priv->dma_rchan; + ata_control |= FSL_ATA_CTRL_FIFO_RCV_EN; + dma_mode = MXC_DMA_MODE_READ; + } + + __raw_writel(ata_control, ata_regs + FSL_ATA_CONTROL); + __raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_FIFO_ALARM); + + if (plat->adma_flag) { + i = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR; + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2 | i, + ata_regs + FSL_ATA_INT_EN); + } else { + __raw_writel(FSL_ATA_INTR_ATA_INTRQ1, + ata_regs + FSL_ATA_INT_EN); + /* + * Set up the DMA completion callback. + */ + mxc_dma_callback_set(chan, dma_callback, (void *)ap); + } + + /* + * Copy the sg list to an array. + */ + if (plat->adma_flag) { + struct adma_bd *bdp = adma_info.adma_bd_table; + pata_adma_bulk_map(qc); + for (i = 0; i < adma_info.sg_ents; i++) { + priv->adma_des_tp[i << 1] = bdp->length << 12; + priv->adma_des_tp[i << 1] |= FSL_ADMA_DES_ATTR_SET; + priv->adma_des_tp[i << 1] |= FSL_ADMA_DES_ATTR_VALID; + priv->adma_des_tp[(i << 1) + 1] = bdp->dma_address; + priv->adma_des_tp[(i << 1) + 1] |= + FSL_ADMA_DES_ATTR_TRAN; + priv->adma_des_tp[(i << 1) + 1] |= + FSL_ADMA_DES_ATTR_VALID; + if (adma_info.sg_ents == (i + 1)) + priv->adma_des_tp[(i << 1) + 1] |= + FSL_ADMA_DES_ATTR_END; + bdp++; + } + __raw_writel((qc->nbytes / qc->sect_size), ata_regs + + FSL_ATA_BLOCK_COUNT); + __raw_writel(plat->fifo_alarm, ata_regs + FSL_ATA_BURST_LENGTH); + __raw_writel(priv->adma_des_paddr, + ata_regs + FSL_ATA_ADMA_SYS_ADDR); + } else { + int nr_sg = 0; + struct scatterlist tmp[64], *tsg, *sg; + tsg = tmp; + for_each_sg(qc->sg, sg, qc->n_elem, si) { + memcpy(tsg, sg, sizeof(*sg)); + tsg++; + nr_sg++; + } + err = mxc_dma_sg_config(chan, tmp, nr_sg, 0, dma_mode); + if (err) + printk(KERN_ERR "pata_fsl_bmdma_setup: error %d\n", + err); + } +} + +static void pata_fsl_bmdma_start(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct pata_fsl_priv *priv = ap->host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + struct fsl_ata_platform_data *plat = ap->dev->platform_data; + int chan; + int err; + unsigned i; + + if (1 == plat->adma_flag) { + i = FSL_ATA_CTRL_DMA_32ADMA | FSL_ATA_CTRL_DMA_ENABLE; + /* The adma mode is used, set dma_start_stop to 1 */ + __raw_writel(i | __raw_readl(ata_regs + FSL_ATA_CONTROL) | + FSL_ATA_CTRL_DMA_STAT_STOP, + ata_regs + FSL_ATA_CONTROL); + } else { + /* + * Start the channel. + */ + chan = qc->dma_dir == DMA_TO_DEVICE ? priv->dma_wchan : + priv->dma_rchan; + + err = mxc_dma_enable(chan); + if (err) + printk(KERN_ERR "%s: : error %d\n", __func__, err); + } + + priv->dma_done = 0; + + ata_sff_exec_command(ap, &qc->tf); +} + +static void pata_fsl_bmdma_stop(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct pata_fsl_priv *priv = ap->host->private_data; + u8 *ata_regs = priv->fsl_ata_regs; + struct fsl_ata_platform_data *plat = ap->dev->platform_data; + unsigned i; + + if (plat->adma_flag) { + /* The adma mode is used, set dma_start_stop to 0 */ + i = FSL_ATA_CTRL_DMA_32ADMA | FSL_ATA_CTRL_DMA_ENABLE; + __raw_writel((i | __raw_readl(ata_regs + FSL_ATA_CONTROL)) & + (~FSL_ATA_CTRL_DMA_STAT_STOP), + ata_regs + FSL_ATA_CONTROL); + } + + /* do a dummy read as in ata_bmdma_stop */ +#if 0 + ata_sff_dma_pause(ap); +#endif +} + +static u8 pata_fsl_bmdma_status(struct ata_port *ap) +{ + struct pata_fsl_priv *priv = ap->host->private_data; + + return priv->dma_done ? ATA_DMA_INTR : 0; +} + +static void pata_fsl_dma_init(struct ata_port *ap) +{ + struct pata_fsl_priv *priv = ap->host->private_data; + + priv->dma_rchan = -1; + priv->dma_wchan = -1; + + priv->dma_rchan = mxc_dma_request(MXC_DMA_ATA_RX, "MXC ATA RX"); + if (priv->dma_rchan < 0) { + dev_printk(KERN_ERR, ap->dev, "couldn't get RX DMA channel\n"); + goto err_out; + } + + priv->dma_wchan = mxc_dma_request(MXC_DMA_ATA_TX, "MXC ATA TX"); + if (priv->dma_wchan < 0) { + dev_printk(KERN_ERR, ap->dev, "couldn't get TX DMA channel\n"); + goto err_out; + } + + dev_printk(KERN_ERR, ap->dev, "rchan=%d wchan=%d\n", priv->dma_rchan, + priv->dma_wchan); + return; + + err_out: + ap->mwdma_mask = 0; + ap->udma_mask = 0; + mxc_dma_free(priv->dma_rchan); + mxc_dma_free(priv->dma_wchan); + kfree(priv); +} + +#if 0 +static u8 pata_fsl_irq_ack(struct ata_port *ap, unsigned int chk_drq) +{ + unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY; + u8 status; + + status = ata_sff_busy_wait(ap, bits, 1000); + if (status & bits) + if (ata_msg_err(ap)) + printk(KERN_ERR "abnormal status 0x%X\n", status); + + return status; +} +#endif + +static void ata_dummy_noret(struct ata_port *ap) +{ + return; +} + +static struct scsi_host_template pata_fsl_sht = { + .module = THIS_MODULE, + .name = DRV_NAME, + .ioctl = ata_scsi_ioctl, + .queuecommand = ata_scsi_queuecmd, + .can_queue = ATA_DEF_QUEUE, + .this_id = ATA_SHT_THIS_ID, + .sg_tablesize = LIBATA_MAX_PRD, + .cmd_per_lun = ATA_SHT_CMD_PER_LUN, + .emulated = ATA_SHT_EMULATED, + .use_clustering = ATA_SHT_USE_CLUSTERING, + .proc_name = DRV_NAME, + .dma_boundary = FSL_ATA_MAX_SG_LEN, + .slave_configure = ata_scsi_slave_config, + .slave_destroy = ata_scsi_slave_destroy, + .bios_param = ata_std_bios_param, +}; + +static struct ata_port_operations pata_fsl_port_ops = { + .inherits = &ata_bmdma_port_ops, + .set_piomode = pata_fsl_set_piomode, + .set_dmamode = pata_fsl_set_dmamode, + + .check_atapi_dma = pata_fsl_check_atapi_dma, + .cable_detect = ata_cable_unknown, + .mode_filter = pata_fsl_bmdma_mode_filter, + + .bmdma_setup = pata_fsl_bmdma_setup, + .bmdma_start = pata_fsl_bmdma_start, + .bmdma_stop = pata_fsl_bmdma_stop, + .bmdma_status = pata_fsl_bmdma_status, + + .qc_prep = ata_noop_qc_prep, + + .sff_data_xfer = ata_sff_data_xfer_noirq, + .sff_irq_clear = ata_dummy_noret, + .sff_irq_on = ata_sff_irq_on, + + .port_start = pata_fsl_port_start, +}; + +static void fsl_setup_port(struct ata_ioports *ioaddr) +{ + unsigned int shift = 2; + + ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << shift); + ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << shift); + ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << shift); + ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << shift); + ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << shift); + ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << shift); + ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << shift); + ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << shift); + ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << shift); + ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << shift); +} + +/** + * pata_fsl_probe - attach a platform interface + * @pdev: platform device + * + * Register a platform bus integrated ATA host controller + * + * The 3 platform device resources are used as follows: + * + * - I/O Base (IORESOURCE_MEM) virt. addr. of ATA controller regs + * - CTL Base (IORESOURCE_MEM) unused + * - IRQ (IORESOURCE_IRQ) platform IRQ assigned to ATA + * + */ +static int __devinit pata_fsl_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *io_res; + struct ata_host *host; + struct ata_port *ap; + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) + pdev->dev.platform_data; + struct pata_fsl_priv *priv; + u8 *ata_regs; + unsigned int int_enable; + + /* + * Set up resources + */ + if (unlikely(pdev->num_resources != 2)) { + dev_err(&pdev->dev, "invalid number of resources\n"); + return -EINVAL; + } + + /* + * Get an ata_host structure for this device + */ + host = ata_host_alloc(&pdev->dev, 1); + if (!host) + return -ENOMEM; + ap = host->ports[0]; + + /* + * Allocate private data + */ + priv = kzalloc(sizeof(struct pata_fsl_priv), GFP_KERNEL); + if (priv == NULL) { + ret = -ENOMEM; + goto err0; + } + host->private_data = priv; + + /* + * Set up resources + */ + io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ata_regs = + (u8 *) ioremap(io_res->start, io_res->end - io_res->start + 1); + priv->fsl_ata_regs = ata_regs; + ap->ioaddr.cmd_addr = (void *)(ata_regs + FSL_ATA_DRIVE_DATA); + ap->ioaddr.ctl_addr = (void *)(ata_regs + FSL_ATA_DRIVE_CONTROL); + ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr; + ap->ops = &pata_fsl_port_ops; + ap->pio_mask = plat->pio_mask; /* support pio 0~4 */ + ap->mwdma_mask = plat->mwdma_mask; /* support mdma 0~2 */ + ap->udma_mask = plat->udma_mask; + pata_fsl_sht.sg_tablesize = plat->max_sg; + fsl_setup_port(&ap->ioaddr); + + if (plat->adma_flag) { + priv->adma_des_tp = + dma_alloc_coherent(&(pdev->dev), + (2 * plat->max_sg) * + sizeof(unsigned int), + &(priv->adma_des_paddr), GFP_DMA); + if (priv->adma_des_tp == NULL) { + ret = -ENOMEM; + goto err1; + } + } + /* + * Do platform-specific initialization (e.g. allocate pins, + * turn on clock). After this call it is assumed that + * plat->get_clk_rate() can be called to calculate + * timing. + */ + if (plat->init && plat->init(pdev)) { + ret = -ENODEV; + goto err2; + } + + priv->clk = clk_get(&pdev->dev, "ata_clk"); + clk_enable(priv->clk); + + /* Deassert the reset bit to enable the interface */ + __raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL); + + /* Enable Core regulator & IO Regulator */ + if (plat->core_reg != NULL) { + core_reg = regulator_get(&pdev->dev, plat->core_reg); + if (regulator_enable(core_reg)) + printk(KERN_INFO "enable core regulator error.\n"); + msleep(100); + + } else + core_reg = NULL; + + if (plat->io_reg != NULL) { + io_reg = regulator_get(&pdev->dev, plat->io_reg); + if (regulator_enable(io_reg)) + printk(KERN_INFO "enable io regulator error.\n"); + msleep(100); + + } else + io_reg = NULL; + + /* Set initial timing and mode */ + set_ata_bus_timing(XFER_PIO_4, pdev); + + /* get DMA ready */ + if (plat->adma_flag == 0) + pata_fsl_dma_init(ap); + + /* + * Enable the ATA INTRQ interrupt from the bus, but + * only allow the CPU to see it (INTRQ2) at this point. + * INTRQ1, which goes to the DMA, will be enabled later. + */ + int_enable = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR | + FSL_ATA_INTR_ATA_INTRQ2; + if (plat->adma_flag) + __raw_writel(int_enable, ata_regs + FSL_ATA_INT_EN); + else + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, + ata_regs + FSL_ATA_INT_EN); + + /* activate */ + if (plat->adma_flag) + ret = ata_host_activate(host, platform_get_irq(pdev, 0), + pata_fsl_adma_intr, 0, &pata_fsl_sht); + else + ret = ata_host_activate(host, platform_get_irq(pdev, 0), + ata_sff_interrupt, 0, &pata_fsl_sht); + + if (!ret) + return ret; + + clk_disable(priv->clk); + regulator_disable(core_reg); + regulator_disable(io_reg); + err2: + if (plat->adma_flag && priv->adma_des_tp) + dma_free_coherent(&(pdev->dev), + (2 * plat->max_sg + + 1) * sizeof(unsigned int), priv->adma_des_tp, + priv->adma_des_paddr); + err1: + iounmap(ata_regs); + kfree(priv); + err0: + ata_host_detach(host); + return ret; + +} + +/** + * pata_fsl_remove - unplug a platform interface + * @pdev: platform device + * + * A platform bus ATA device has been unplugged. Perform the needed + * cleanup. Also called on module unload for any active devices. + */ +static int __devexit pata_fsl_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ata_host *host = dev_get_drvdata(dev); + struct pata_fsl_priv *priv = host->private_data; + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) + pdev->dev.platform_data; + u8 *ata_regs = priv->fsl_ata_regs; + + __raw_writel(0, ata_regs + FSL_ATA_INT_EN); /* Disable interrupts */ + + ata_host_detach(host); + + clk_disable(priv->clk); + clk_put(priv->clk); + priv->clk = NULL; + + /* Disable Core regulator & IO Regulator */ + if (plat->core_reg != NULL) { + regulator_disable(core_reg); + regulator_put(core_reg); + } + if (plat->io_reg != NULL) { + regulator_disable(io_reg); + regulator_put(io_reg); + } + + if (plat->exit) + plat->exit(); + + if (plat->adma_flag && priv->adma_des_tp) + dma_free_coherent(&(pdev->dev), + (2 * plat->max_sg) * + sizeof(unsigned int), priv->adma_des_tp, + priv->adma_des_paddr); + iounmap(ata_regs); + + kfree(priv); + + return 0; +} + +#ifdef CONFIG_PM +static int pata_fsl_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct ata_host *host = dev_get_drvdata(&pdev->dev); + struct pata_fsl_priv *priv = host->private_data; + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) + pdev->dev.platform_data; + u8 *ata_regs = priv->fsl_ata_regs; + + ata_host_suspend(host, state); + + /* Disable interrupts. */ + __raw_writel(0, ata_regs + FSL_ATA_INT_EN); + + clk_disable(priv->clk); + + if (plat->exit) + plat->exit(); + + return 0; +} + +static int pata_fsl_resume(struct platform_device *pdev) +{ + struct ata_host *host = dev_get_drvdata(&pdev->dev); + struct pata_fsl_priv *priv = host->private_data; + struct fsl_ata_platform_data *plat = (struct fsl_ata_platform_data *) + pdev->dev.platform_data; + u8 *ata_regs = priv->fsl_ata_regs; + unsigned char int_enable; + + if (plat->init && plat->init(pdev)) + return -ENODEV; + + clk_enable(priv->clk); + + /* Deassert the reset bit to enable the interface */ + __raw_writel(FSL_ATA_CTRL_ATA_RST_B, ata_regs + FSL_ATA_CONTROL); + + /* Set initial timing and mode */ + set_ata_bus_timing(XFER_PIO_4, pdev); + + /* + * Enable hardware interrupts. + */ + int_enable = FSL_ATA_INTR_DMA_TRANS_OVER | FSL_ATA_INTR_DMA_ERR | + FSL_ATA_INTR_ATA_INTRQ2; + if (1 == plat->adma_flag) + __raw_writel(int_enable, ata_regs + FSL_ATA_INT_EN); + else + __raw_writel(FSL_ATA_INTR_ATA_INTRQ2, + ata_regs + FSL_ATA_INT_EN); + + ata_host_resume(host); + + return 0; +} +#endif + +static struct platform_driver pata_fsl_driver = { + .probe = pata_fsl_probe, + .remove = __devexit_p(pata_fsl_remove), +#ifdef CONFIG_PM + .suspend = pata_fsl_suspend, + .resume = pata_fsl_resume, +#endif + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init pata_fsl_init(void) +{ + return platform_driver_register(&pata_fsl_driver); + + return 0; +} + +static void __exit pata_fsl_exit(void) +{ + platform_driver_unregister(&pata_fsl_driver); +} + +module_init(pata_fsl_init); +module_exit(pata_fsl_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("low-level driver for Freescale ATA"); +MODULE_LICENSE("GPL"); diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c index 941fcb87e52a..12584ec045b7 100644 --- a/drivers/base/power/main.c +++ b/drivers/base/power/main.c @@ -59,6 +59,7 @@ void device_pm_init(struct device *dev) { dev->power.status = DPM_ON; init_completion(&dev->power.completion); + complete_all(&dev->power.completion); pm_runtime_init(dev); } @@ -190,6 +191,39 @@ static void initcall_debug_report(struct device *dev, ktime_t calltime, error, (unsigned long long)ktime_to_ns(delta) >> 10); } } +#ifdef CONFIG_SUSPEND_DEVICE_TIME_DEBUG +static void suspend_time_debug_start(ktime_t *start) +{ + *start = ktime_get(); +} + +static void suspend_time_debug_report(const char *name, struct device *dev, + ktime_t starttime) +{ + ktime_t rettime; + s64 usecs64; + int usecs; + + if (!dev->driver) + return; + + rettime = ktime_get(); + usecs64 = ktime_to_us(ktime_sub(rettime, starttime)); + usecs = usecs64; + if (usecs == 0) + usecs = 1; + + if (device_suspend_time_threshold + && usecs > device_suspend_time_threshold) + pr_info("PM: device %s:%s %s too slow, it takes \t %ld.%03ld msecs\n", + dev->bus->name, dev_name(dev), name, + usecs / USEC_PER_MSEC, usecs % USEC_PER_MSEC); +} +#else +static void suspend_time_debug_start(ktime_t *start) {} +static void suspend_time_debug_report(const char *name, struct device *dev, + ktime_t starttime) {} +#endif /* CONFIG_SUSPEND_DEVICE_TIME_DEBUG */ /** * dpm_wait - Wait for a PM operation to complete. @@ -227,7 +261,7 @@ static int pm_op(struct device *dev, pm_message_t state) { int error = 0; - ktime_t calltime; + ktime_t calltime, starttime; calltime = initcall_debug_start(dev); @@ -235,13 +269,17 @@ static int pm_op(struct device *dev, #ifdef CONFIG_SUSPEND case PM_EVENT_SUSPEND: if (ops->suspend) { + suspend_time_debug_start(&starttime); error = ops->suspend(dev); + suspend_time_debug_report("suspend", dev, starttime); suspend_report_result(ops->suspend, error); } break; case PM_EVENT_RESUME: if (ops->resume) { + suspend_time_debug_start(&starttime); error = ops->resume(dev); + suspend_time_debug_report("resume", dev, starttime); suspend_report_result(ops->resume, error); } break; diff --git a/drivers/base/power/power.h b/drivers/base/power/power.h index c0bd03c83b9c..354a220a4070 100644 --- a/drivers/base/power/power.h +++ b/drivers/base/power/power.h @@ -10,6 +10,10 @@ static inline void pm_runtime_remove(struct device *dev) {} #endif /* !CONFIG_PM_RUNTIME */ +#ifdef CONFIG_SUSPEND_DEVICE_TIME_DEBUG +extern int device_suspend_time_threshold; +#endif + #ifdef CONFIG_PM_SLEEP /* kernel/power/main.c */ diff --git a/drivers/block/brd.c b/drivers/block/brd.c index f1bf79d9bc0a..bcb50e84cf4b 100644 --- a/drivers/block/brd.c +++ b/drivers/block/brd.c @@ -333,13 +333,14 @@ static int brd_make_request(struct request_queue *q, struct bio *bio) struct bio_vec *bvec; sector_t sector; int i; - int err = -EIO; + int err = 0; sector = bio->bi_sector; if (sector + (bio->bi_size >> SECTOR_SHIFT) > - get_capacity(bdev->bd_disk)) + get_capacity(bdev->bd_disk)) { + err = -EIO; goto out; - + } if (unlikely(bio_rw_flagged(bio, BIO_RW_DISCARD))) { err = 0; discard_from_brd(brd, sector, bio->bi_size); diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig index 058fbccf2f52..bf28acc117ba 100644 --- a/drivers/bluetooth/Kconfig +++ b/drivers/bluetooth/Kconfig @@ -207,4 +207,15 @@ config BT_ATH3K Say Y here to compile support for "Atheros firmware download driver" into the kernel or say M to compile it as module (ath3k). +config BT_HCIUART_ATH + bool "Atheros AR300x Board support" + depends on BT_HCIUART + help + HCIATH (HCI Atheros) is a serial protocol for communication + between Bluetooth device and host with support for Atheros AR300x + power management feature. This protocol is required for + serial Bluetooth devices that are based on Atheros AR300x chips. + + Say Y here to compile support for HCIATH protocol. endmenu + diff --git a/drivers/bluetooth/Makefile b/drivers/bluetooth/Makefile index 7e5aed598121..45d61b7a3a5b 100644 --- a/drivers/bluetooth/Makefile +++ b/drivers/bluetooth/Makefile @@ -23,7 +23,9 @@ btmrvl-y := btmrvl_main.o btmrvl-$(CONFIG_DEBUG_FS) += btmrvl_debugfs.o hci_uart-y := hci_ldisc.o +hci_uart-$(CONFIG_BT_HCIUART_ATH) += hci_ath.o hci_uart-$(CONFIG_BT_HCIUART_H4) += hci_h4.o hci_uart-$(CONFIG_BT_HCIUART_BCSP) += hci_bcsp.o hci_uart-$(CONFIG_BT_HCIUART_LL) += hci_ll.o hci_uart-objs := $(hci_uart-y) + diff --git a/drivers/bluetooth/hci_ath.c b/drivers/bluetooth/hci_ath.c new file mode 100644 index 000000000000..959b044404f0 --- /dev/null +++ b/drivers/bluetooth/hci_ath.c @@ -0,0 +1,386 @@ +/* + * Copyright (c) 2009-2010 Atheros Communications Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "hci_uart.h" + +#ifdef DEBUG +#define ATH_DBG(fmt, arg...) printk(KERN_ERR "[ATH_DBG] (%s) <%s>: " fmt "\n" , __FILE__ , __func__ , ## arg) +#define ATH_INFO(fmt, arg...) printk(KERN_INFO "[ATH_DBG] (%s) <%s>: " fmt "\n" , __FILE__ , __func__ , ## arg) +#else +#define ATH_DBG(fmt, arg...) +#define ATH_INFO(fmt, arg...) +#endif + + +/* HCIATH receiver States */ +#define HCIATH_W4_PACKET_TYPE 0 +#define HCIATH_W4_EVENT_HDR 1 +#define HCIATH_W4_ACL_HDR 2 +#define HCIATH_W4_SCO_HDR 3 +#define HCIATH_W4_DATA 4 + +struct ath_struct { + struct hci_uart *hu; + unsigned int rx_state; + unsigned int rx_count; + unsigned int cur_sleep; + + spinlock_t hciath_lock; + struct sk_buff *rx_skb; + struct sk_buff_head txq; + wait_queue_head_t wqevt; + struct work_struct ctxtsw; +}; + +int ath_wakeup_ar3001(struct tty_struct *tty) +{ + struct termios settings; + int status = 0x00; + mm_segment_t oldfs; + status = tty->driver->ops->tiocmget(tty, NULL); + + ATH_DBG(""); + + if ((status & TIOCM_CTS)) + return status; + + oldfs = get_fs(); + set_fs(KERNEL_DS); + n_tty_ioctl_helper(tty, NULL, TCGETS, (unsigned long)&settings); + + settings.c_cflag &= ~CRTSCTS; + n_tty_ioctl_helper(tty, NULL, TCSETS, (unsigned long)&settings); + set_fs(oldfs); + status = tty->driver->ops->tiocmget(tty, NULL); + + /* Wake up board */ + tty->driver->ops->tiocmset(tty, NULL, 0x00, TIOCM_RTS); + mdelay(20); + + status = tty->driver->ops->tiocmget(tty, NULL); + + tty->driver->ops->tiocmset(tty, NULL, TIOCM_RTS, 0x00); + mdelay(20); + + status = tty->driver->ops->tiocmget(tty, NULL); + oldfs = get_fs(); + set_fs(KERNEL_DS); + n_tty_ioctl_helper(tty, NULL, TCGETS, (unsigned long)&settings); + + settings.c_cflag |= CRTSCTS; + n_tty_ioctl_helper(tty, NULL, TCSETS, (unsigned long)&settings); + set_fs(oldfs); + return status; +} + +static void ath_context_switch(struct work_struct *work) +{ + int status; + struct ath_struct *ath; + struct hci_uart *hu; + struct tty_struct *tty; + + ATH_DBG(""); + + ath = container_of(work, struct ath_struct, ctxtsw); + + hu = ath->hu; + tty = hu->tty; + + /* verify and wake up controller */ + if (ath->cur_sleep) { + + status = ath_wakeup_ar3001(tty); + if (!(status & TIOCM_CTS)) + return; + } + + /* Ready to send Data */ + clear_bit(HCI_UART_SENDING, &hu->tx_state); + hci_uart_tx_wakeup(hu); +} + +int ath_check_sleep_cmd(struct ath_struct *ath, unsigned char *packet) +{ + ATH_DBG(""); + + if (packet[0] == 0x04 && packet[1] == 0xFC) + ath->cur_sleep = packet[3]; + + ATH_DBG("ath->cur_sleep:%d\n", ath->cur_sleep); + + return 0; +} + + +/* Initialize protocol */ +static int ath_open(struct hci_uart *hu) +{ + struct ath_struct *ath; + BT_DBG("hu %p", hu); + ATH_INFO("hu %p", hu); + + ath = kzalloc(sizeof(*ath), GFP_ATOMIC); + if (!ath) + return -ENOMEM; + + skb_queue_head_init(&ath->txq); + spin_lock_init(&ath->hciath_lock); + + ath->cur_sleep = 0; + hu->priv = ath; + ath->hu = hu; + + init_waitqueue_head(&ath->wqevt); + INIT_WORK(&ath->ctxtsw, ath_context_switch); + return 0; +} + +/* Flush protocol data */ +static int ath_flush(struct hci_uart *hu) +{ + struct ath_struct *ath = hu->priv; + BT_DBG("hu %p", hu); + ATH_INFO("hu %p", hu); + skb_queue_purge(&ath->txq); + + return 0; +} + +/* Close protocol */ +static int ath_close(struct hci_uart *hu) +{ + struct ath_struct *ath = hu->priv; + BT_DBG("hu %p", hu); + ATH_INFO("hu %p", hu); + + skb_queue_purge(&ath->txq); + + if (ath->rx_skb) + kfree_skb(ath->rx_skb); + + wake_up_interruptible(&ath->wqevt); + hu->priv = NULL; + kfree(ath); + return 0; +} + +/* Enqueue frame for transmittion */ +static int ath_enqueue(struct hci_uart *hu, struct sk_buff *skb) +{ + struct ath_struct *ath = hu->priv; + if (bt_cb(skb)->pkt_type == HCI_SCODATA_PKT) { + + /* Discard SCO packet.AR3001 does not support SCO over HCI */ + BT_DBG("SCO Packet over HCI received Dropping\n"); + kfree(skb); + return 0; + } + BT_DBG("hu %p skb %p", hu, skb); + ATH_DBG("hu %p skb %p", hu, skb); + + /* Prepend skb with frame type */ + memcpy(skb_push(skb, 1), &bt_cb(skb)->pkt_type, 1); + + skb_queue_tail(&ath->txq, skb); + set_bit(HCI_UART_SENDING, &hu->tx_state); + + schedule_work(&ath->ctxtsw); + return 0; +} + +static struct sk_buff *ath_dequeue(struct hci_uart *hu) +{ + struct ath_struct *ath = hu->priv; + struct sk_buff *skbuf; + + ATH_DBG(""); + + skbuf = skb_dequeue(&ath->txq); + if (skbuf != NULL) + ath_check_sleep_cmd(ath, &skbuf->data[1]); + + return skbuf; +} + +static inline int ath_check_data_len(struct ath_struct *ath, int len) +{ + register int room = skb_tailroom(ath->rx_skb); + BT_DBG("len %d room %d", len, room); + ATH_DBG("len %d room %d", len, room); + + if (len > room) { + BT_ERR("Data length is too large"); + kfree_skb(ath->rx_skb); + ath->rx_state = HCIATH_W4_PACKET_TYPE; + ath->rx_skb = NULL; + ath->rx_count = 0; + } else { + ath->rx_state = HCIATH_W4_DATA; + ath->rx_count = len; + return len; + } + + return 0; +} + +/* Recv data */ +static int ath_recv(struct hci_uart *hu, void *data, int count) +{ + struct ath_struct *ath = hu->priv; + register char *ptr; + struct hci_event_hdr *eh; + struct hci_acl_hdr *ah; + struct hci_sco_hdr *sh; + struct sk_buff *skbuf; + register int len, type, dlen; + + skbuf = NULL; + BT_DBG("hu %p count %d rx_state %d rx_count %d", hu, count, + ath->rx_state, ath->rx_count); + ATH_DBG("hu %p count %d rx_state %d rx_count %d", hu, count, + ath->rx_state, ath->rx_count); + ptr = data; + while (count) { + if (ath->rx_count) { + + len = min_t(unsigned int, ath->rx_count, count); + memcpy(skb_put(ath->rx_skb, len), ptr, len); + ath->rx_count -= len; + count -= len; + ptr += len; + + if (ath->rx_count) + continue; + switch (ath->rx_state) { + case HCIATH_W4_DATA: + hci_recv_frame(ath->rx_skb); + ath->rx_state = HCIATH_W4_PACKET_TYPE; + ath->rx_skb = NULL; + ath->rx_count = 0; + continue; + case HCIATH_W4_EVENT_HDR: + eh = (struct hci_event_hdr *)ath->rx_skb->data; + BT_DBG("Event header: evt 0x%2.2x plen %d", + eh->evt, eh->plen); + ATH_DBG("Event header: evt 0x%2.2x plen %d", + eh->evt, eh->plen); + ath_check_data_len(ath, eh->plen); + continue; + case HCIATH_W4_ACL_HDR: + ah = (struct hci_acl_hdr *)ath->rx_skb->data; + dlen = __le16_to_cpu(ah->dlen); + BT_DBG("ACL header: dlen %d", dlen); + ATH_DBG("ACL header: dlen %d", dlen); + ath_check_data_len(ath, dlen); + continue; + case HCIATH_W4_SCO_HDR: + sh = (struct hci_sco_hdr *)ath->rx_skb->data; + BT_DBG("SCO header: dlen %d", sh->dlen); + ATH_DBG("SCO header: dlen %d", sh->dlen); + ath_check_data_len(ath, sh->dlen); + continue; + } + } + + /* HCIATH_W4_PACKET_TYPE */ + switch (*ptr) { + case HCI_EVENT_PKT: + BT_DBG("Event packet"); + ATH_DBG("Event packet"); + ath->rx_state = HCIATH_W4_EVENT_HDR; + ath->rx_count = HCI_EVENT_HDR_SIZE; + type = HCI_EVENT_PKT; + break; + case HCI_ACLDATA_PKT: + BT_DBG("ACL packet"); + ATH_DBG("ACL packet"); + ath->rx_state = HCIATH_W4_ACL_HDR; + ath->rx_count = HCI_ACL_HDR_SIZE; + type = HCI_ACLDATA_PKT; + break; + case HCI_SCODATA_PKT: + BT_DBG("SCO packet"); + ATH_DBG("SCO packet"); + ath->rx_state = HCIATH_W4_SCO_HDR; + ath->rx_count = HCI_SCO_HDR_SIZE; + type = HCI_SCODATA_PKT; + break; + default: + BT_ERR("Unknown HCI packet type %2.2x", (__u8) *ptr); + hu->hdev->stat.err_rx++; + ptr++; + count--; + continue; + }; + ptr++; + count--; + + /* Allocate packet */ + ath->rx_skb = bt_skb_alloc(HCI_MAX_FRAME_SIZE, GFP_ATOMIC); + if (!ath->rx_skb) { + BT_ERR("Can't allocate mem for new packet"); + ath->rx_state = HCIATH_W4_PACKET_TYPE; + ath->rx_count = 0; + return -ENOMEM; + } + ath->rx_skb->dev = (void *)hu->hdev; + bt_cb(ath->rx_skb)->pkt_type = type; + } return count; +} + +static struct hci_uart_proto athp = { + .id = HCI_UART_ATH, + .open = ath_open, + .close = ath_close, + .recv = ath_recv, + .enqueue = ath_enqueue, + .dequeue = ath_dequeue, + .flush = ath_flush, +}; + +int ath_init(void) +{ + int err = hci_uart_register_proto(&athp); + ATH_INFO(""); + if (!err) + BT_INFO("HCIATH protocol initialized"); + else + BT_ERR("HCIATH protocol registration failed with err %d", err); + return err; +} + +int ath_deinit(void) +{ + ATH_INFO(""); + return hci_uart_unregister_proto(&athp); +} diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c index 76a1abb8f214..b5c2401ee870 100644 --- a/drivers/bluetooth/hci_ldisc.c +++ b/drivers/bluetooth/hci_ldisc.c @@ -542,7 +542,9 @@ static int __init hci_uart_init(void) #ifdef CONFIG_BT_HCIUART_LL ll_init(); #endif - +#ifdef CONFIG_BT_HCIUART_ATH + ath_init(); +#endif return 0; } @@ -559,7 +561,9 @@ static void __exit hci_uart_exit(void) #ifdef CONFIG_BT_HCIUART_LL ll_deinit(); #endif - +#ifdef CONFIG_BT_HCIUART_ATH + ath_deinit(); +#endif /* Release tty registration of line discipline */ if ((err = tty_unregister_ldisc(N_HCI))) BT_ERR("Can't unregister HCI line discipline (%d)", err); diff --git a/drivers/bluetooth/hci_uart.h b/drivers/bluetooth/hci_uart.h index 50113db06b9f..94dd9c529e93 100644 --- a/drivers/bluetooth/hci_uart.h +++ b/drivers/bluetooth/hci_uart.h @@ -33,13 +33,14 @@ #define HCIUARTGETDEVICE _IOR('U', 202, int) /* UART protocols */ -#define HCI_UART_MAX_PROTO 5 +#define HCI_UART_MAX_PROTO 6 #define HCI_UART_H4 0 #define HCI_UART_BCSP 1 #define HCI_UART_3WIRE 2 #define HCI_UART_H4DS 3 #define HCI_UART_LL 4 +#define HCI_UART_ATH 5 struct hci_uart; @@ -91,3 +92,9 @@ int bcsp_deinit(void); int ll_init(void); int ll_deinit(void); #endif + +#ifdef CONFIG_BT_HCIUART_ATH +int ath_init(void); +int ath_deinit(void); +#endif + diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 7cfcc629a7fd..1ec263f676a6 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -426,6 +426,29 @@ config SGI_MBCS If you have an SGI Altix with an attached SABrick say Y or M here, otherwise say N. +config FM_SI4702 + tristate "SI4702 FM device driver" + depends on (MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS) + default n + +config MXC_IIM + tristate "MXC IIM device driver" + depends on ARCH_MXC + help + Support for access to MXC IIM device, most people should say N here. + +config MXS_VIIM + tristate "MXS Virtual IIM device driver" + depends on (ARCH_STMP3XXX || ARCH_MXS || ARCH_MX5) + help + Support for access to MXS Virtual IIM device, most people should say N here. + +config IMX_SIM + tristate "IMX SIM support" + depends on (ARCH_MX5 || ARCH_MX25) + ---help--- + Say Y to enable the SIM driver support. + source "drivers/serial/Kconfig" config UNIX98_PTYS @@ -536,6 +559,22 @@ config BFIN_OTP_WRITE_ENABLE If unsure, say N. +config FSL_OTP + tristate "Freescale On-Chip OTP Memory Support" + depends on (ARCH_MX23 || ARCH_MX28 || ARCH_MX50) + default n + help + If you say Y here, you will get support for a character device + interface into the One Time Programmable memory pages that are + stored on the iMX23/28/50 processor. This will not get you access + to the secure memory pages however. You will need to write your + own secure code and reader for that. + + To compile this driver as a module, choose M here: the module + will be called fsl_otp. + + If unsure, it is safe to say Y. + config PRINTER tristate "Parallel printer support" depends on PARPORT diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 88d6eac69754..310e11bcda19 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -9,6 +9,11 @@ FONTMAPFILE = cp437.uni obj-y += mem.o random.o tty_io.o n_tty.o tty_ioctl.o tty_ldisc.o tty_buffer.o tty_port.o +obj-$(CONFIG_FM_SI4702) += mxc_si4702.o +obj-$(CONFIG_MXC_IIM) += mxc_iim.o +obj-$(CONFIG_MXS_VIIM) += mxs_viim.o +obj-$(CONFIG_IMX_SIM) += imx_sim.o + obj-$(CONFIG_LEGACY_PTYS) += pty.o obj-$(CONFIG_UNIX98_PTYS) += pty.o obj-y += misc.o @@ -65,6 +70,7 @@ obj-$(CONFIG_IBM_BSR) += bsr.o obj-$(CONFIG_SGI_MBCS) += mbcs.o obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o obj-$(CONFIG_BFIN_OTP) += bfin-otp.o +obj-$(CONFIG_FSL_OTP) += fsl_otp.o obj-$(CONFIG_PRINTER) += lp.o diff --git a/drivers/char/fsl_otp.c b/drivers/char/fsl_otp.c new file mode 100644 index 000000000000..fbc52b870d3a --- /dev/null +++ b/drivers/char/fsl_otp.c @@ -0,0 +1,240 @@ +/* + * Freescale On-Chip OTP driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fsl_otp.h" + +static DEFINE_MUTEX(otp_mutex); +static struct kobject *otp_kobj; +static struct attribute **attrs; +static struct kobj_attribute *kattr; +static struct attribute_group attr_group; +static struct fsl_otp_data *otp_data; + +static inline unsigned int get_reg_index(struct kobj_attribute *tmp) +{ + return tmp - kattr; +} + +static int otp_wait_busy(u32 flags) +{ + int count; + u32 c; + + for (count = 10000; count >= 0; count--) { + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags))) + break; + cpu_relax(); + } + if (count < 0) + return -ETIMEDOUT; + return 0; +} + +static ssize_t otp_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + unsigned int index = get_reg_index(attr); + u32 value = 0; + + /* sanity check */ + if (index >= otp_data->fuse_num) + return 0; + + mutex_lock(&otp_mutex); + + if (otp_read_prepare()) { + mutex_unlock(&otp_mutex); + return 0; + } + value = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(index)); + otp_read_post(); + + mutex_unlock(&otp_mutex); + return sprintf(buf, "0x%x\n", value); +} + +static int otp_write_bits(int addr, u32 data, u32 magic) +{ + u32 c; /* for control register */ + + /* init the control register */ + c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL); + c &= ~BM_OCOTP_CTRL_ADDR; + c |= BF(addr, OCOTP_CTRL_ADDR); + c |= BF(magic, OCOTP_CTRL_WR_UNLOCK); + __raw_writel(c, REGS_OCOTP_BASE + HW_OCOTP_CTRL); + + /* init the data register */ + __raw_writel(data, REGS_OCOTP_BASE + HW_OCOTP_DATA); + otp_wait_busy(0); + + mdelay(2); /* Write Postamble */ + return 0; +} + +static ssize_t otp_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + unsigned int index = get_reg_index(attr); + int value; + + /* sanity check */ + if (index >= otp_data->fuse_num) + return 0; + + sscanf(buf, "0x%x", &value); + + mutex_lock(&otp_mutex); + if (otp_write_prepare(otp_data)) { + mutex_unlock(&otp_mutex); + return 0; + } + otp_write_bits(index, value, 0x3e77); + otp_write_post(); + mutex_unlock(&otp_mutex); + return count; +} + +static void free_otp_attr(void) +{ + kfree(attrs); + attrs = NULL; + + kfree(kattr); + kattr = NULL; +} + +static int __init alloc_otp_attr(struct fsl_otp_data *pdata) +{ + int i; + + otp_data = pdata; /* get private data */ + + /* The last one is NULL, which is used to detect the end */ + attrs = kzalloc((otp_data->fuse_num + 1) * sizeof(attrs[0]), + GFP_KERNEL); + kattr = kzalloc(otp_data->fuse_num * sizeof(struct kobj_attribute), + GFP_KERNEL); + + if (!attrs || !kattr) + goto error_out; + + for (i = 0; i < otp_data->fuse_num; i++) { + kattr[i].attr.name = pdata->fuse_name[i]; + kattr[i].attr.mode = 0600; + kattr[i].show = otp_show; + kattr[i].store = otp_store; + + attrs[i] = &kattr[i].attr; + } + memset(&attr_group, 0, sizeof(attr_group)); + attr_group.attrs = attrs; + return 0; + +error_out: + free_otp_attr(); + return -ENOMEM; +} + +static int __devinit fsl_otp_probe(struct platform_device *pdev) +{ + int retval; + struct fsl_otp_data *pdata; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) + return -ENODEV; + + retval = alloc_otp_attr(pdata); + if (retval) + return retval; + + retval = map_ocotp_addr(pdev); + if (retval) + goto error; + + otp_kobj = kobject_create_and_add("fsl_otp", NULL); + if (!otp_kobj) { + retval = -ENOMEM; + goto error; + } + + retval = sysfs_create_group(otp_kobj, &attr_group); + if (retval) + goto error; + + mutex_init(&otp_mutex); + return 0; +error: + kobject_put(otp_kobj); + otp_kobj = NULL; + free_otp_attr(); + unmap_ocotp_addr(); + return retval; +} + +static int otp_remove(struct platform_device *pdev) +{ + kobject_put(otp_kobj); + otp_kobj = NULL; + + free_otp_attr(); + unmap_ocotp_addr(); + return 0; +} + +static struct platform_driver ocotp_driver = { + .probe = fsl_otp_probe, + .remove = otp_remove, + .driver = { + .name = "ocotp", + .owner = THIS_MODULE, + }, +}; + +static int __init fsl_otp_init(void) +{ + return platform_driver_register(&ocotp_driver); +} + +static void __exit fsl_otp_exit(void) +{ + platform_driver_unregister(&ocotp_driver); +} +module_init(fsl_otp_init); +module_exit(fsl_otp_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Huang Shijie "); +MODULE_DESCRIPTION("Common driver for OTP controller"); diff --git a/drivers/char/fsl_otp.h b/drivers/char/fsl_otp.h new file mode 100644 index 000000000000..72ec23450dce --- /dev/null +++ b/drivers/char/fsl_otp.h @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __FREESCALE_OTP__ +#define __FREESCALE_OTP__ + +#define log(a, ...) printk(KERN_INFO "[ %s : %.3d ] "a"\n", \ + __func__, __LINE__, ## __VA_ARGS__) + +static int otp_wait_busy(u32 flags); + +/* IMX23 and IMX28 share most of the defination ========================= */ +#if (defined(CONFIG_ARCH_MX23) || defined(CONFIG_ARCH_MX28)) + +#include +#include +#include +#include +#include + +#if defined(CONFIG_ARCH_MX23) +#include +#else +#include +#endif + +#define REGS_OCOTP_BASE (IO_ADDRESS(OCOTP_PHYS_ADDR)) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +static unsigned long otp_hclk_saved; +static u32 otp_voltage_saved; +struct regulator *regu; + +/* open the bank for the imx23/imx28 */ +static int otp_read_prepare(void) +{ + int r; + + /* [1] set the HCLK */ + /* [2] check BUSY and ERROR bit */ + r = otp_wait_busy(0); + if (r < 0) + goto error; + + /* [3] open bank */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + udelay(10); + + /* [4] wait for BUSY */ + r = otp_wait_busy(0); + return 0; +error: + return r; +} + +static int otp_read_post(void) +{ + /* [5] close bank */ + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_CLR); + return 0; +} + +static int otp_write_prepare(struct fsl_otp_data *otp_data) +{ + struct clk *hclk; + int err = 0; + + /* [1] HCLK to 24MHz. */ + hclk = clk_get(NULL, "hclk"); + if (IS_ERR(hclk)) { + err = PTR_ERR(hclk); + goto out; + } + /* + WARNING ACHTUNG UWAGA + + the code below changes HCLK clock rate to 24M. This is + required to write OTP bits (7.2.2 in STMP378x Target + Specification), and might affect LCD operation, for example. + Moreover, this hacky code changes VDDIO to 2.8V; and resto- + res it only on otp_close(). This may affect... anything. + + You are warned now. + */ + otp_hclk_saved = clk_get_rate(hclk); + clk_set_rate(hclk, 24000); + + /* [2] The voltage is set to 2.8V */ + regu = regulator_get(NULL, otp_data->regulator_name); + otp_voltage_saved = regulator_get_voltage(regu); + regulator_set_voltage(regu, 2800000, 2800000); + + /* [3] wait for BUSY and ERROR */ + err = otp_wait_busy(BM_OCOTP_CTRL_RD_BANK_OPEN); +out: + return err; +} + +static int otp_write_post(void) +{ + struct clk *hclk; + + hclk = clk_get(NULL, "hclk"); + + /* restore the clock and voltage */ + clk_set_rate(hclk, otp_hclk_saved); + regulator_set_voltage(regu, otp_voltage_saved, otp_voltage_saved); + otp_wait_busy(0); + + /* reset */ + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + return 0; +} + +static int __init map_ocotp_addr(struct platform_device *pdev) +{ + return 0; +} +static void unmap_ocotp_addr(void) +{ +} + +#elif defined(CONFIG_ARCH_MX5) /* IMX5 below ============================= */ + +#include +#include +#include +#include "regs-ocotp-v2.h" + +static void *otp_base; +#define REGS_OCOTP_BASE ((unsigned long)otp_base) +#define HW_OCOTP_CUSTn(n) (0x00000030 + (n) * 0x10) +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +#define DEF_RELEX (15) /* > 10.5ns */ + +static int set_otp_timing(void) +{ + struct clk *apb_clk; + unsigned long clk_rate = 0; + unsigned long relex, sclk_count, rd_busy; + u32 timing = 0; + + /* [1] get the clock. It needs the AHB clock,though doc writes APB.*/ + apb_clk = clk_get(NULL, "ahb_clk"); + if (IS_ERR(apb_clk)) { + log("we can not find the clock"); + return -1; + } + clk_rate = clk_get_rate(apb_clk); + + /* do optimization for too many zeros */ + relex = clk_rate / (1000000000 / DEF_RELEX) + 1; + sclk_count = clk_rate / (1000000000 / 5000) + 1 + DEF_RELEX; + rd_busy = clk_rate / (1000000000 / 300) + 1; + + timing = BF(relex, OCOTP_TIMING_RELAX); + timing |= BF(sclk_count, OCOTP_TIMING_SCLK_COUNT); + timing |= BF(rd_busy, OCOTP_TIMING_RD_BUSY); + + __raw_writel(timing, REGS_OCOTP_BASE + HW_OCOTP_TIMING); + return 0; +} + +/* IMX5 does not need to open the bank anymore */ +static int otp_read_prepare(void) +{ + return set_otp_timing(); +} +static int otp_read_post(void) +{ + return 0; +} + +static int otp_write_prepare(struct fsl_otp_data *otp_data) +{ + int ret = 0; + + /* [1] set timing */ + ret = set_otp_timing(); + if (ret) + return ret; + + /* [2] wait */ + otp_wait_busy(0); + return 0; +} +static int otp_write_post(void) +{ + /* Reload all the shadow registers */ + __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + udelay(1); + otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS); + return 0; +} + +static int __init map_ocotp_addr(struct platform_device *pdev) +{ + struct resource *res; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + otp_base = ioremap(res->start, SZ_8K); + if (!otp_base) { + log("Can not remap the OTP iomem!"); + return -1; + } + return 0; +} + +static void unmap_ocotp_addr(void) +{ + iounmap(otp_base); + otp_base = NULL; +} +#endif /* CONFIG_ARCH_MX5 */ +#endif diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index d31483c54883..92bc50685360 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -60,6 +60,30 @@ config HW_RANDOM_AMD If unsure, say Y. +config HW_RANDOM_FSL_RNGA + tristate "Freescale RNGA Random Number Generator" + depends on HW_RANDOM && ARCH_HAS_RNGA && !MXC_SECURITY_RNG + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on Freescale i.MX processors. + + To compile this driver as a module, choose M here: the + module will be called fsl-rnga. + + If unsure, say Y. + +config HW_RANDOM_FSL_RNGC + tristate "Freescale RNGC Random Number Generator" + depends on HW_RANDOM && ARCH_HAS_RNGC && !MXC_SECURITY_RNG + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on Freescale i.MX processors. + + To compile this driver as a module, choose M here: the + module will be called fsl-rngc. + + If unsure, say Y. + config HW_RANDOM_GEODE tristate "AMD Geode HW Random Number Generator support" depends on HW_RANDOM && X86_32 && PCI diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index 4273308aa1e3..d0bf5cca29c7 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -7,6 +7,8 @@ rng-core-y := core.o obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o +obj-$(CONFIG_HW_RANDOM_FSL_RNGA) += fsl-rnga.o +obj-$(CONFIG_HW_RANDOM_FSL_RNGC) += fsl-rngc.o obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o n2-rng-y := n2-drv.o n2-asm.o diff --git a/drivers/char/hw_random/fsl-rnga.c b/drivers/char/hw_random/fsl-rnga.c new file mode 100644 index 000000000000..20b22bc65d53 --- /dev/null +++ b/drivers/char/hw_random/fsl-rnga.c @@ -0,0 +1,238 @@ +/* + * RNG driver for Freescale RNGA + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG) + * (c) Copyright 2003 Red Hat Inc + * + * derived from + * + * Hardware driver for the AMD 768 Random Number Generator (RNG) + * (c) Copyright 2001 Red Hat Inc + * + * derived from + * + * Hardware driver for Intel i810 Random Number Generator (RNG) + * Copyright 2000,2001 Jeff Garzik + * Copyright 2000,2001 Philipp Rumpf + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* RNGA Registers */ +#define RNGA_CONTROL 0x00 +#define RNGA_STATUS 0x04 +#define RNGA_ENTROPY 0x08 +#define RNGA_OUTPUT_FIFO 0x0c +#define RNGA_MODE 0x10 +#define RNGA_VERIFICATION_CONTROL 0x14 +#define RNGA_OSC_CONTROL_COUNTER 0x18 +#define RNGA_OSC1_COUNTER 0x1c +#define RNGA_OSC2_COUNTER 0x20 +#define RNGA_OSC_COUNTER_STATUS 0x24 + +/* RNGA Registers Range */ +#define RNG_ADDR_RANGE 0x28 + +/* RNGA Control Register */ +#define RNGA_CONTROL_SLEEP 0x00000010 +#define RNGA_CONTROL_CLEAR_INT 0x00000008 +#define RNGA_CONTROL_MASK_INTS 0x00000004 +#define RNGA_CONTROL_HIGH_ASSURANCE 0x00000002 +#define RNGA_CONTROL_GO 0x00000001 + +#define RNGA_STATUS_LEVEL_MASK 0x0000ff00 + +/* RNGA Status Register */ +#define RNGA_STATUS_OSC_DEAD 0x80000000 +#define RNGA_STATUS_SLEEP 0x00000010 +#define RNGA_STATUS_ERROR_INT 0x00000008 +#define RNGA_STATUS_FIFO_UNDERFLOW 0x00000004 +#define RNGA_STATUS_LAST_READ_STATUS 0x00000002 +#define RNGA_STATUS_SECURITY_VIOLATION 0x00000001 + +static struct platform_device *rng_dev; + +static int fsl_rnga_data_present(struct hwrng *rng) +{ + int level; + u32 rng_base = (u32) rng->priv; + + /* how many random numbers is in FIFO? [0-16] */ + level = ((__raw_readl(rng_base + RNGA_STATUS) & + RNGA_STATUS_LEVEL_MASK) >> 8); + + return level > 0 ? 1 : 0; +} + +static int fsl_rnga_data_read(struct hwrng *rng, u32 * data) +{ + int err; + u32 ctrl, rng_base = (u32) rng->priv; + + /* retrieve a random number from FIFO */ + *data = __raw_readl(rng_base + RNGA_OUTPUT_FIFO); + + /* some error while reading this random number? */ + err = __raw_readl(rng_base + RNGA_STATUS) & RNGA_STATUS_ERROR_INT; + + /* if error: clear error interrupt, but doesn't return random number */ + if (err) { + dev_dbg(&rng_dev->dev, "Error while reading random number!\n"); + ctrl = __raw_readl(rng_base + RNGA_CONTROL); + __raw_writel(ctrl | RNGA_CONTROL_CLEAR_INT, + rng_base + RNGA_CONTROL); + return 0; + } else + return 4; +} + +static int fsl_rnga_init(struct hwrng *rng) +{ + u32 ctrl, osc, rng_base = (u32) rng->priv; + + /* wake up */ + ctrl = __raw_readl(rng_base + RNGA_CONTROL); + __raw_writel(ctrl & ~RNGA_CONTROL_SLEEP, rng_base + RNGA_CONTROL); + + /* verify if oscillator is working */ + osc = __raw_readl(rng_base + RNGA_STATUS); + if (osc & RNGA_STATUS_OSC_DEAD) { + dev_err(&rng_dev->dev, "RNGA Oscillator is dead!\n"); + return -ENODEV; + } + + /* go running */ + ctrl = __raw_readl(rng_base + RNGA_CONTROL); + __raw_writel(ctrl | RNGA_CONTROL_GO, rng_base + RNGA_CONTROL); + + return 0; +} + +static void fsl_rnga_cleanup(struct hwrng *rng) +{ + u32 ctrl, rng_base = (u32) rng->priv; + + ctrl = __raw_readl(rng_base + RNGA_CONTROL); + + /* stop rnga */ + __raw_writel(ctrl & ~RNGA_CONTROL_GO, rng_base + RNGA_CONTROL); +} + +static struct hwrng fsl_rnga = { + .name = "fsl-rnga", + .init = fsl_rnga_init, + .cleanup = fsl_rnga_cleanup, + .data_present = fsl_rnga_data_present, + .data_read = fsl_rnga_data_read +}; + +static int __init fsl_rnga_probe(struct platform_device *pdev) +{ + int err = -ENODEV; + struct clk *clk; + struct resource *res, *mem; + void __iomem *rng_base = NULL; + + if (rng_dev) + return -EBUSY; + + clk = clk_get(NULL, "rng_clk"); + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Could not get rng_clk!\n"); + err = PTR_ERR(clk); + return err; + } + + clk_enable(clk); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) + return -ENOENT; + + mem = request_mem_region(res->start, res->end - res->start, pdev->name); + + if (mem == NULL) + return -EBUSY; + + dev_set_drvdata(&pdev->dev, mem); + rng_base = ioremap(res->start, res->end - res->start); + + fsl_rnga.priv = (unsigned long)rng_base; + + err = hwrng_register(&fsl_rnga); + if (err) { + dev_err(&pdev->dev, "FSL RNGA registering failed (%d)\n", err); + return err; + } + + rng_dev = pdev; + + dev_info(&pdev->dev, "FSL RNGA Registered.\n"); + + return 0; +} + +static int __exit fsl_rnga_remove(struct platform_device *pdev) +{ + struct resource *mem = dev_get_drvdata(&pdev->dev); + void __iomem *rng_base = (void __iomem *)fsl_rnga.priv; + + hwrng_unregister(&fsl_rnga); + + release_resource(mem); + + iounmap(rng_base); + + return 0; +} + +static struct platform_driver fsl_rnga_driver = { + .driver = { + .name = "fsl_rnga", + .owner = THIS_MODULE, + }, + .remove = __exit_p(fsl_rnga_remove), +}; + +static int __init mod_init(void) +{ + return platform_driver_probe(&fsl_rnga_driver, fsl_rnga_probe); +} + +static void __exit mod_exit(void) +{ + platform_driver_unregister(&fsl_rnga_driver); +} + +module_init(mod_init); +module_exit(mod_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("H/W RNGA driver for i.MX"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/hw_random/fsl-rngc.c b/drivers/char/hw_random/fsl-rngc.c new file mode 100644 index 000000000000..ba518a98c318 --- /dev/null +++ b/drivers/char/hw_random/fsl-rngc.c @@ -0,0 +1,414 @@ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG) + * (c) Copyright 2003 Red Hat Inc + * + * derived from + * + * Hardware driver for the AMD 768 Random Number Generator (RNG) + * (c) Copyright 2001 Red Hat Inc + * + * derived from + * + * Hardware driver for Intel i810 Random Number Generator (RNG) + * Copyright 2000,2001 Jeff Garzik + * Copyright 2000,2001 Philipp Rumpf + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* + * RNG driver for Freescale RNGC + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RNGC_VERSION_MAJOR3 3 + +#define RNGC_VERSION_ID 0x0000 +#define RNGC_COMMAND 0x0004 +#define RNGC_CONTROL 0x0008 +#define RNGC_STATUS 0x000C +#define RNGC_ERROR 0x0010 +#define RNGC_FIFO 0x0014 +#define RNGC_VERIF_CTRL 0x0020 +#define RNGC_OSC_CTRL_COUNT 0x0028 +#define RNGC_OSC_COUNT 0x002C +#define RNGC_OSC_COUNT_STATUS 0x0030 + +#define RNGC_VERID_ZEROS_MASK 0x0f000000 +#define RNGC_VERID_RNG_TYPE_MASK 0xf0000000 +#define RNGC_VERID_RNG_TYPE_SHIFT 28 +#define RNGC_VERID_CHIP_VERSION_MASK 0x00ff0000 +#define RNGC_VERID_CHIP_VERSION_SHIFT 16 +#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00 +#define RNGC_VERID_VERSION_MAJOR_SHIFT 8 +#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff +#define RNGC_VERID_VERSION_MINOR_SHIFT 0 + +#define RNGC_CMD_ZEROS_MASK 0xffffff8c +#define RNGC_CMD_SW_RST 0x00000040 +#define RNGC_CMD_CLR_ERR 0x00000020 +#define RNGC_CMD_CLR_INT 0x00000010 +#define RNGC_CMD_SEED 0x00000002 +#define RNGC_CMD_SELF_TEST 0x00000001 + +#define RNGC_CTRL_ZEROS_MASK 0xfffffc8c +#define RNGC_CTRL_CTL_ACC 0x00000200 +#define RNGC_CTRL_VERIF_MODE 0x00000100 +#define RNGC_CTRL_MASK_ERROR 0x00000040 + +#define RNGC_CTRL_MASK_DONE 0x00000020 +#define RNGC_CTRL_AUTO_SEED 0x00000010 +#define RNGC_CTRL_FIFO_UFLOW_MASK 0x00000003 +#define RNGC_CTRL_FIFO_UFLOW_SHIFT 0 + +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR 0 +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR2 1 +#define RNGC_CTRL_FIFO_UFLOW_BUS_XFR 2 +#define RNGC_CTRL_FIFO_UFLOW_ZEROS_INTR 3 + +#define RNGC_STATUS_ST_PF_MASK 0x00c00000 +#define RNGC_STATUS_ST_PF_SHIFT 22 +#define RNGC_STATUS_ST_PF_TRNG 0x00800000 +#define RNGC_STATUS_ST_PF_PRNG 0x00400000 +#define RNGC_STATUS_ERROR 0x00010000 +#define RNGC_STATUS_FIFO_SIZE_MASK 0x0000f000 +#define RNGC_STATUS_FIFO_SIZE_SHIFT 12 +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00 +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8 +#define RNGC_STATUS_NEXT_SEED_DONE 0x00000040 +#define RNGC_STATUS_SEED_DONE 0x00000020 +#define RNGC_STATUS_ST_DONE 0x00000010 +#define RNGC_STATUS_RESEED 0x00000008 +#define RNGC_STATUS_SLEEP 0x00000004 +#define RNGC_STATUS_BUSY 0x00000002 +#define RNGC_STATUS_SEC_STATE 0x00000001 + +#define RNGC_ERROR_STATUS_ZEROS_MASK 0xffffffc0 +#define RNGC_ERROR_STATUS_BAD_KEY 0x00000040 +#define RNGC_ERROR_STATUS_RAND_ERR 0x00000020 +#define RNGC_ERROR_STATUS_FIFO_ERR 0x00000010 +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008 +#define RNGC_ERROR_STATUS_ST_ERR 0x00000004 +#define RNGC_ERROR_STATUS_OSC_ERR 0x00000002 +#define RNGC_ERROR_STATUS_LFSR_ERR 0x00000001 + +#define RNG_ADDR_RANGE 0x34 + +static DECLARE_COMPLETION(rng_self_testing); +static DECLARE_COMPLETION(rng_seed_done); + +static struct platform_device *rng_dev; + +int irq_rng; + +static int fsl_rngc_data_present(struct hwrng *rng) +{ + int level; + u32 rngc_base = (u32) rng->priv; + + /* how many random numbers are in FIFO? [0-16] */ + level = (__raw_readl(rngc_base + RNGC_STATUS) & + RNGC_STATUS_FIFO_LEVEL_MASK) >> RNGC_STATUS_FIFO_LEVEL_SHIFT; + + return level > 0 ? 1 : 0; +} + +static int fsl_rngc_data_read(struct hwrng *rng, u32 * data) +{ + int err; + u32 rngc_base = (u32) rng->priv; + + /* retrieve a random number from FIFO */ + *data = __raw_readl(rngc_base + RNGC_FIFO); + + /* is there some error while reading this random number? */ + err = __raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR; + + /* if error happened doesn't return random number */ + return err ? 0 : 4; +} + +static irqreturn_t rngc_irq(int irq, void *dev) +{ + int handled = 0; + u32 rngc_base = (u32) dev; + + /* is the seed creation done? */ + if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_SEED_DONE) { + complete(&rng_seed_done); + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + rngc_base + RNGC_COMMAND); + handled = 1; + } + + /* is the self test done? */ + if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ST_DONE) { + complete(&rng_self_testing); + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + rngc_base + RNGC_COMMAND); + handled = 1; + } + + /* is there any error? */ + if (__raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR) { + /* clear interrupt */ + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + rngc_base + RNGC_COMMAND); + handled = 1; + } + + return handled; +} + +static int fsl_rngc_init(struct hwrng *rng) +{ + int err; + u32 cmd, ctrl, osc, rngc_base = (u32) rng->priv; + + INIT_COMPLETION(rng_self_testing); + INIT_COMPLETION(rng_seed_done); + + err = __raw_readl(rngc_base + RNGC_STATUS) & RNGC_STATUS_ERROR; + if (err) { + /* is this a bad keys error ? */ + if (__raw_readl(rngc_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_BAD_KEY) { + dev_err(&rng_dev->dev, "Can't start, Bad Keys.\n"); + return -EIO; + } + } + + /* mask all interrupts, will be unmasked soon */ + ctrl = __raw_readl(rngc_base + RNGC_CONTROL); + __raw_writel(ctrl | RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR, + rngc_base + RNGC_CONTROL); + + /* verify if oscillator is working */ + osc = __raw_readl(rngc_base + RNGC_ERROR); + if (osc & RNGC_ERROR_STATUS_OSC_ERR) { + dev_err(&rng_dev->dev, "RNGC Oscillator is dead!\n"); + return -EIO; + } + + err = request_irq(irq_rng, rngc_irq, 0, "fsl_rngc", (void *)rng->priv); + if (err) { + dev_err(&rng_dev->dev, "Can't get interrupt working.\n"); + return -EIO; + } + + /* do self test, repeat until get success */ + do { + /* clear error */ + cmd = __raw_readl(rngc_base + RNGC_COMMAND); + __raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc_base + RNGC_COMMAND); + + /* unmask all interrupt */ + ctrl = __raw_readl(rngc_base + RNGC_CONTROL); + __raw_writel(ctrl & ~(RNGC_CTRL_MASK_DONE | + RNGC_CTRL_MASK_ERROR), rngc_base + RNGC_CONTROL); + + /* run self test */ + cmd = __raw_readl(rngc_base + RNGC_COMMAND); + __raw_writel(cmd | RNGC_CMD_SELF_TEST, + rngc_base + RNGC_COMMAND); + + wait_for_completion(&rng_self_testing); + + } while (__raw_readl(rngc_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_ST_ERR); + + /* clear interrupt. Is it really necessary here? */ + __raw_writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR, + rngc_base + RNGC_COMMAND); + + /* create seed, repeat while there is some statistical error */ + do { + /* clear error */ + cmd = __raw_readl(rngc_base + RNGC_COMMAND); + __raw_writel(cmd | RNGC_CMD_CLR_ERR, rngc_base + RNGC_COMMAND); + + /* seed creation */ + cmd = __raw_readl(rngc_base + RNGC_COMMAND); + __raw_writel(cmd | RNGC_CMD_SEED, rngc_base + RNGC_COMMAND); + + wait_for_completion(&rng_seed_done); + + } while (__raw_readl(rngc_base + RNGC_ERROR) & + RNGC_ERROR_STATUS_STAT_ERR); + + err = __raw_readl(rngc_base + RNGC_ERROR) & + (RNGC_ERROR_STATUS_STAT_ERR | + RNGC_ERROR_STATUS_RAND_ERR | + RNGC_ERROR_STATUS_FIFO_ERR | + RNGC_ERROR_STATUS_ST_ERR | + RNGC_ERROR_STATUS_OSC_ERR | + RNGC_ERROR_STATUS_LFSR_ERR); + + if (err) { + dev_err(&rng_dev->dev, "FSL RNGC appears inoperable.\n"); + return -EIO; + } + + return 0; +} + +static struct hwrng fsl_rngc = { + .name = "fsl-rngc", + .init = fsl_rngc_init, + .data_present = fsl_rngc_data_present, + .data_read = fsl_rngc_data_read +}; + +static int __init fsl_rngc_probe(struct platform_device *pdev) +{ + int err = -ENODEV; + struct clk *clk; + struct resource *res, *mem; + void __iomem *rngc_base = NULL; + + if (rng_dev) + return -EBUSY; + + clk = clk_get(&pdev->dev, "rng_clk"); + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Can not get rng_clk\n"); + err = PTR_ERR(clk); + return err; + } + + clk_enable(clk); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) + return -ENOENT; + + mem = request_mem_region(res->start, res->end - res->start, pdev->name); + + if (mem == NULL) + return -EBUSY; + + dev_set_drvdata(&pdev->dev, mem); + rngc_base = ioremap(res->start, res->end - res->start); + + fsl_rngc.priv = (unsigned long)rngc_base; + + irq_rng = platform_get_irq(pdev, 0); + + err = hwrng_register(&fsl_rngc); + if (err) { + dev_err(&pdev->dev, "FSL RNGC registering failed (%d)\n", err); + return err; + } + + rng_dev = pdev; + + dev_info(&pdev->dev, "FSL RNGC Registered.\n"); + + return 0; +} + +static int __exit fsl_rngc_remove(struct platform_device *pdev) +{ + struct clk *clk; + struct resource *mem = dev_get_drvdata(&pdev->dev); + void __iomem *rngc_base = (void __iomem *)fsl_rngc.priv; + + clk = clk_get(&pdev->dev, "rng_clk"); + + if (IS_ERR(clk)) + dev_err(&pdev->dev, "Can not get rng_clk\n"); + else + clk_disable(clk); + + hwrng_unregister(&fsl_rngc); + + release_resource(mem); + + iounmap(rngc_base); + + return 0; +} + +static int fsl_rngc_suspend(struct platform_device *pdev, + pm_message_t state) +{ +#ifdef CONFIG_PM + struct clk *clk = clk_get(&pdev->dev, "rng_clk"); + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Can not get rng_clk\n"); + return PTR_ERR(clk); + } + + clk_disable(clk); +#endif + + return 0; +} + +static int fsl_rngc_resume(struct platform_device *pdev) +{ +#ifdef CONFIG_PM + struct clk *clk = clk_get(&pdev->dev, "rng_clk"); + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Can not get rng_clk\n"); + return PTR_ERR(clk); + } + + clk_enable(clk); +#endif + + return 0; +} + +static struct platform_driver fsl_rngc_driver = { + .driver = { + .name = "fsl_rngc", + .owner = THIS_MODULE, + }, + .remove = __exit_p(fsl_rngc_remove), + .suspend = fsl_rngc_suspend, + .resume = fsl_rngc_resume, +}; + +static int __init mod_init(void) +{ + return platform_driver_probe(&fsl_rngc_driver, fsl_rngc_probe); +} + +static void __exit mod_exit(void) +{ + platform_driver_unregister(&fsl_rngc_driver); +} + +module_init(mod_init); +module_exit(mod_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("H/W RNGC driver for i.MX"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/imx_sim.c b/drivers/char/imx_sim.c new file mode 100644 index 000000000000..eba202df4551 --- /dev/null +++ b/drivers/char/imx_sim.c @@ -0,0 +1,1498 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_sim.c + * + * @brief Driver for Freescale IMX SIM interface + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define SIM_INTERNAL_CLK 0 +#define SIM_RFU -1 + +/* Default communication parameters: FI=372, DI=1, PI1=5V, II=50mA, WWT=10 */ +#define SIM_PARAM_DEFAULT { 0, 1, 1, 5, 1, 0, 0, 0, 10 } + +/* Transmit and receive buffer sizes */ +#define SIM_XMT_BUFFER_SIZE 256 +#define SIM_RCV_BUFFER_SIZE 256 + +/* Interface character references */ +#define SIM_IFC_TXI(letter, number) (letter + number * 4) +#define SIM_IFC_TA1 SIM_IFC_TXI(0, 0) +#define SIM_IFC_TB1 SIM_IFC_TXI(0, 1) +#define SIM_IFC_TC1 SIM_IFC_TXI(0, 2) +#define SIM_IFC_TD1 SIM_IFC_TXI(0, 3) +#define SIM_IFC_TA2 SIM_IFC_TXI(1, 0) +#define SIM_IFC_TB2 SIM_IFC_TXI(1, 1) +#define SIM_IFC_TC2 SIM_IFC_TXI(1, 2) +#define SIM_IFC_TD2 SIM_IFC_TXI(1, 3) +#define SIM_IFC_TA3 SIM_IFC_TXI(2, 0) +#define SIM_IFC_TB3 SIM_IFC_TXI(2, 1) +#define SIM_IFC_TC3 SIM_IFC_TXI(2, 2) +#define SIM_IFC_TD3 SIM_IFC_TXI(2, 3) +#define SIM_IFC_TA4 SIM_IFC_TXI(3, 0) +#define SIM_IFC_TB4 SIM_IFC_TXI(3, 1) +#define SIM_IFC_TC4 SIM_IFC_TXI(3, 2) +#define SIM_IFC_TD4 SIM_IFC_TXI(3, 3) + +/* ATR and OPS states */ +#define SIM_STATE_REMOVED 0 +#define SIM_STATE_OPERATIONAL_IDLE 1 +#define SIM_STATE_OPERATIONAL_COMMAND 2 +#define SIM_STATE_OPERATIONAL_RESPONSE 3 +#define SIM_STATE_OPERATIONAL_STATUS1 4 +#define SIM_STATE_OPERATIONAL_STATUS2 5 +#define SIM_STATE_OPERATIONAL_PTS 6 +#define SIM_STATE_DETECTED_ATR_T0 7 +#define SIM_STATE_DETECTED_ATR_TS 8 +#define SIM_STATE_DETECTED_ATR_TXI 9 +#define SIM_STATE_DETECTED_ATR_THB 10 +#define SIM_STATE_DETECTED_ATR_TCK 11 + +/* Definitions of the offset of the SIM hardware registers */ +#define PORT1_CNTL 0x00 /* 00 */ +#define SETUP 0x04 /* 04 */ +#define PORT1_DETECT 0x08 /* 08 */ +#define PORT1_XMT_BUF 0x0C /* 0c */ +#define PORT1_RCV_BUF 0x10 /* 10 */ +#define PORT0_CNTL 0x14 /* 14 */ +#define CNTL 0x18 /* 18 */ +#define CLK_PRESCALER 0x1C /* 1c */ +#define RCV_THRESHOLD 0x20 /* 20 */ +#define ENABLE 0x24 /* 24 */ +#define XMT_STATUS 0x28 /* 28 */ +#define RCV_STATUS 0x2C /* 2c */ +#define INT_MASK 0x30 /* 30 */ +#define PORTO_XMT_BUF 0x34 /* 34 */ +#define PORT0_RCV_BUF 0x38 /* 38 */ +#define PORT0_DETECT 0x3C /* 3c */ +#define DATA_FORMAT 0x40 /* 40 */ +#define XMT_THRESHOLD 0x44 /* 44 */ +#define GUARD_CNTL 0x48 /* 48 */ +#define OD_CONFIG 0x4C /* 4c */ +#define RESET_CNTL 0x50 /* 50 */ +#define CHAR_WAIT 0x54 /* 54 */ +#define GPCNT 0x58 /* 58 */ +#define DIVISOR 0x5C /* 5c */ +#define BWT 0x60 /* 60 */ +#define BGT 0x64 /* 64 */ +#define BWT_H 0x68 /* 68 */ +#define XMT_FIFO_STAT 0x6C /* 6c */ +#define RCV_FIFO_CNT 0x70 /* 70 */ +#define RCV_FIFO_WPTR 0x74 /* 74 */ +#define RCV_FIFO_RPTR 0x78 /* 78 */ + +/* SIM port[0|1]_cntl register bits */ +#define SIM_PORT_CNTL_SFPD (1<<7) +#define SIM_PORT_CNTL_3VOLT (1<<6) +#define SIM_PORT_CNTL_SCSP (1<<5) +#define SIM_PORT_CNTL_SCEN (1<<4) +#define SIM_PORT_CNTL_SRST (1<<3) +#define SIM_PORT_CNTL_STEN (1<<2) +#define SIM_PORT_CNTL_SVEN (1<<1) +#define SIM_PORT_CNTL_SAPD (1<<0) + +/* SIM od_config register bits */ +#define SIM_OD_CONFIG_OD_P1 (1<<1) +#define SIM_OD_CONFIG_OD_P0 (1<<0) + +/* SIM enable register bits */ +#define SIM_ENABLE_XMTEN (1<<1) +#define SIM_ENABLE_RCVEN (1<<0) + +/* SIM int_mask register bits */ +#define SIM_INT_MASK_RFEM (1<<13) +#define SIM_INT_MASK_BGTM (1<<12) +#define SIM_INT_MASK_BWTM (1<<11) +#define SIM_INT_MASK_RTM (1<<10) +#define SIM_INT_MASK_CWTM (1<<9) +#define SIM_INT_MASK_GPCM (1<<8) +#define SIM_INT_MASK_TDTFM (1<<7) +#define SIM_INT_MASK_TFOM (1<<6) +#define SIM_INT_MASK_XTM (1<<5) +#define SIM_INT_MASK_TFEIM (1<<4) +#define SIM_INT_MASK_ETCIM (1<<3) +#define SIM_INT_MASK_OIM (1<<2) +#define SIM_INT_MASK_TCIM (1<<1) +#define SIM_INT_MASK_RIM (1<<0) + +/* SIM xmt_status register bits */ +#define SIM_XMT_STATUS_GPCNT (1<<8) +#define SIM_XMT_STATUS_TDTF (1<<7) +#define SIM_XMT_STATUS_TFO (1<<6) +#define SIM_XMT_STATUS_TC (1<<5) +#define SIM_XMT_STATUS_ETC (1<<4) +#define SIM_XMT_STATUS_TFE (1<<3) +#define SIM_XMT_STATUS_XTE (1<<0) + +/* SIM rcv_status register bits */ +#define SIM_RCV_STATUS_BGT (1<<11) +#define SIM_RCV_STATUS_BWT (1<<10) +#define SIM_RCV_STATUS_RTE (1<<9) +#define SIM_RCV_STATUS_CWT (1<<8) +#define SIM_RCV_STATUS_CRCOK (1<<7) +#define SIM_RCV_STATUS_LRCOK (1<<6) +#define SIM_RCV_STATUS_RDRF (1<<5) +#define SIM_RCV_STATUS_RFD (1<<4) +#define SIM_RCV_STATUS_RFE (1<<1) +#define SIM_RCV_STATUS_OEF (1<<0) + +/* SIM cntl register bits */ +#define SIM_CNTL_BWTEN (1<<15) +#define SIM_CNTL_XMT_CRC_LRC (1<<14) +#define SIM_CNTL_CRCEN (1<<13) +#define SIM_CNTL_LRCEN (1<<12) +#define SIM_CNTL_CWTEN (1<<11) +#define SIM_CNTL_SAMPLE12 (1<<4) +#define SIM_CNTL_ONACK (1<<3) +#define SIM_CNTL_ANACK (1<<2) +#define SIM_CNTL_ICM (1<<1) +#define SIM_CNTL_GPCNT_CLK_SEL(x) ((x&0x03)<<9) +#define SIM_CNTL_GPCNT_CLK_SEL_MASK (0x03<<9) +#define SIM_CNTL_BAUD_SEL(x) ((x&0x07)<<6) +#define SIM_CNTL_BAUD_SEL_MASK (0x07<<6) + +/* SIM rcv_threshold register bits */ +#define SIM_RCV_THRESHOLD_RTH(x) ((x&0x0f)<<9) +#define SIM_RCV_THRESHOLD_RTH_MASK (0x0f<<9) +#define SIM_RCV_THRESHOLD_RDT(x) ((x&0x1ff)<<0) +#define SIM_RCV_THRESHOLD_RDT_MASK (0x1ff<<0) + +/* SIM xmt_threshold register bits */ +#define SIM_XMT_THRESHOLD_XTH(x) ((x&0x0f)<<4) +#define SIM_XMT_THRESHOLD_XTH_MASK (0x0f<<4) +#define SIM_XMT_THRESHOLD_TDT(x) ((x&0x0f)<<0) +#define SIM_XMT_THRESHOLD_TDT_MASK (0x0f<<0) + +/* SIM guard_cntl register bits */ +#define SIM_GUARD_CNTL_RCVR11 (1<<8) +#define SIM_GIARD_CNTL_GETU(x) (x&0xff) +#define SIM_GIARD_CNTL_GETU_MASK (0xff) + +/* SIM port[0|]_detect register bits */ +#define SIM_PORT_DETECT_SPDS (1<<3) +#define SIM_PORT_DETECT_SPDP (1<<2) +#define SIM_PORT_DETECT_SDI (1<<1) +#define SIM_PORT_DETECT_SDIM (1<<0) + +/* END of REGS definitions */ + +/* ATR parser data (the parser state is stored in the main device structure) */ +typedef struct { + uint8_t T0; /* ATR T0 */ + uint8_t TS; /* ATR TS */ + /* ATR TA1, TB1, TC1, TD1, TB1, ... , TD4 */ + uint8_t TXI[16]; + uint8_t THB[15]; /* ATR historical bytes */ + uint8_t TCK; /* ATR checksum */ + uint16_t ifc_valid; /* valid interface characters */ + uint8_t ifc_current_valid; /* calid ifcs in the current batch */ + uint8_t cnt; /* number of current batch */ + uint8_t num_hb; /* number of historical bytes */ +} sim_atrparser_t; + +/* Main SIM driver structure */ +typedef struct { + /* card inserted = 1, ATR received = 2, card removed = 0 */ + int present; + /* current ATR or OPS state */ + int state; + /* current power state */ + int power; + /* error code occured during transfer */ + int errval; + struct clk *clk; /* Clock id */ + uint8_t clk_flag; + struct resource *res; /* IO map memory */ + void __iomem *ioaddr; /* Mapped address */ + int ipb_irq; /* sim ipb IRQ num */ + int dat_irq; /* sim dat IRQ num */ + /* parser for incoming ATR stream */ + sim_atrparser_t atrparser; + /* raw ATR stream received */ + sim_atr_t atr; + /* communication parameters according to ATR */ + sim_param_t param_atr; + /* current communication parameters */ + sim_param_t param; + /* current TPDU or PTS transfer */ + sim_xfer_t xfer; + /* transfer is on the way = 1, idle = 2 */ + int xfer_ongoing; + /* remaining bytes to transmit for the current transfer */ + int xmt_remaining; + /* transmit position */ + int xmt_pos; + /* receive position / number of bytes received */ + int rcv_count; + uint8_t rcv_buffer[SIM_RCV_BUFFER_SIZE]; + uint8_t xmt_buffer[SIM_XMT_BUFFER_SIZE]; + /* transfer completion notifier */ + struct completion xfer_done; + /* async notifier for card and ATR detection */ + struct fasync_struct *fasync; + /* Platform specific data */ + struct mxc_sim_platform_data *plat_data; +} sim_t; + +static int sim_param_F[] = { + SIM_INTERNAL_CLK, 372, 558, 744, 1116, 1488, 1860, SIM_RFU, + SIM_RFU, 512, 768, 1024, 1536, 2048, SIM_RFU, SIM_RFU +}; + +static int sim_param_D[] = { + SIM_RFU, 64 * 1, 64 * 2, 64 * 4, 64 * 8, 64 * 16, SIM_RFU, SIM_RFU, + SIM_RFU, SIM_RFU, 64 * 1 / 2, 64 * 1 / 4, 64 * 1 / 8, 64 * 1 / 16, + 64 * 1 / 32, 64 * 1 / 64 +}; + +static struct miscdevice sim_dev; + +/* Function: sim_calc_param + * + * Description: determine register values depending on communication parameters + * + * Parameters: + * uint32_t fi ATR frequency multiplier index + * uint32_t di ATR frequency divider index + * uint32_t* ptr_divisor location to store divisor result + * uint32_t* ptr_sample12 location to store sample12 result + * + * Return Values: + * SIM_OK calculation finished without errors + * -SIM_E_PARAM_DIVISOR_RANGE calculated divisor > 255 + * -SIM_E_PARAM_FBYD_NOTDIVBY8OR12 F/D not divisable by 12 (as required) + * -SIM_E_PARAM_FBYD_WITHFRACTION F/D has a remainder + * -SIM_E_PARAM_DI_INVALID frequency multiplyer index not supported + * -SIM_E_PARAM_FI_INVALID frequency divider index not supported + */ + +static int sim_calc_param(uint32_t fi, uint32_t di, uint32_t *ptr_divisor, + uint32_t *ptr_sample12) +{ + int32_t errval = SIM_OK; + int32_t f = sim_param_F[fi]; + int32_t d = sim_param_D[di]; + int32_t stage2_fra = (64 * f) % d; + int32_t stage2_div = (64 * f) / d; + uint32_t sample12 = 1; + uint32_t divisor = 31; + + pr_debug("%s entering.\n", __func__); + if ((f > 0) || (d > 0)) { + if (stage2_fra == 0) { + if ((stage2_div % 12) == 0) { + sample12 = 1; + divisor = stage2_div / 12; + } else if ((stage2_div % 8) == 0) { + sample12 = 0; + divisor = stage2_div / 8; + } else + sample12 = -1; + if (sample12 >= 0) { + if (divisor < 256) { + pr_debug("fi=%i", fi); + pr_debug("di=%i", di); + pr_debug("f=%i", f); + pr_debug("d=%i/64", d); + pr_debug("div=%i", stage2_div); + pr_debug("divisor=%i", divisor); + pr_debug("sample12=%i\n", sample12); + + *ptr_divisor = divisor; + *ptr_sample12 = sample12; + errval = SIM_OK; + } else + errval = -SIM_E_PARAM_DIVISOR_RANGE; + } else + errval = -SIM_E_PARAM_FBYD_NOTDIVBY8OR12; + } else + errval = -SIM_E_PARAM_FBYD_WITHFRACTION; + } else + errval = -SIM_E_PARAM_FI_INVALID; + + return errval; +}; + +/* Function: sim_set_param + * + * Description: apply communication parameters (setup devisor and sample12) + * + * Parameters: + * sim_t* sim pointer to SIM device handler + * sim_param_t* param pointer to communication parameters + * + * Return Values: + * see function sim_calc_param + */ + +static int sim_set_param(sim_t *sim, sim_param_t *param) +{ + uint32_t divisor, sample12, reg_data; + int errval; + + pr_debug("%s entering.\n", __func__); + errval = sim_calc_param(param->FI, param->DI, &divisor, &sample12); + if (errval == SIM_OK) { + __raw_writel(divisor, sim->ioaddr + DIVISOR); + if (sample12) { + reg_data = __raw_readl(sim->ioaddr + CNTL); + reg_data |= SIM_CNTL_SAMPLE12; + __raw_writel(reg_data, sim->ioaddr + CNTL); + } else { + reg_data = __raw_readl(sim->ioaddr + CNTL); + reg_data &= ~SIM_CNTL_SAMPLE12; + __raw_writel(reg_data, sim->ioaddr + CNTL); + } + } + + return errval; +}; + +/* Function: sim_atr_received + * + * Description: this function is called whenever a valid ATR has been received. + * It determines the communication parameters from the ATR received and notifies + * the user space application with SIGIO. + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_atr_received(sim_t *sim) +{ + sim_param_t param_default = SIM_PARAM_DEFAULT; + sim->param_atr = param_default; + + pr_debug("%s entering.\n", __func__); + if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TA1))) { + sim->param_atr.FI = sim->atrparser.TXI[SIM_IFC_TA1] >> 4; + sim->param_atr.DI = sim->atrparser.TXI[SIM_IFC_TA1] & 0x0f; + } + if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TB1))) { + sim->param_atr.PI1 = (sim->atrparser.TXI[SIM_IFC_TB1] >> 4) + & 0x07; + sim->param_atr.II = sim->atrparser.TXI[SIM_IFC_TB1] & 0x07f; + } + if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TC1))) + sim->param_atr.N = sim->atrparser.TXI[SIM_IFC_TC1]; + + if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TD1))) + sim->param_atr.T = sim->atrparser.TXI[SIM_IFC_TD1] & 0x0f; + + if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TB2))) + sim->param_atr.PI2 = sim->atrparser.TXI[SIM_IFC_TB2]; + + if (sim->atrparser.ifc_valid & (1 << (SIM_IFC_TC2))) + sim->param_atr.WWT = sim->atrparser.TXI[SIM_IFC_TC2]; + + if (sim->fasync) + kill_fasync(&sim->fasync, SIGIO, POLL_IN); + +}; + +/* Function: sim_xmt_fill + * + * Description: fill the transmit FIFO until the FIFO is full or + * the end of the transmission has been reached. + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_xmt_fill(sim_t *sim) +{ + uint32_t reg_data; + int bytesleft; + + reg_data = __raw_readl(sim->ioaddr + XMT_FIFO_STAT); + bytesleft = 16 - ((reg_data >> 8) & 0x0f); + + pr_debug("txfill: remaining=%i bytesleft=%i\n", + sim->xmt_remaining, bytesleft); + if (bytesleft > sim->xmt_remaining) + bytesleft = sim->xmt_remaining; + + sim->xmt_remaining -= bytesleft; + for (; bytesleft > 0; bytesleft--) { + __raw_writel(sim->xmt_buffer[sim->xmt_pos], + sim->ioaddr + PORT1_XMT_BUF); + sim->xmt_pos++; + }; +/* FIXME: optimization - keep filling until fifo full */ +}; + +/* Function: sim_xmt_start + * + * Description: initiate a transfer + * + * Parameters: + * sim_t* sim pointer to SIM device handler + * int pos position in the xfer transmit buffer + * int count number of bytes to be transmitted + */ + +static void sim_xmt_start(sim_t *sim, int pos, int count) +{ + uint32_t reg_data; + + pr_debug("tx\n"); + sim->xmt_remaining = count; + sim->xmt_pos = pos; + sim_xmt_fill(sim); + + if (sim->xmt_remaining) { + reg_data = __raw_readl(sim->ioaddr + INT_MASK); + reg_data &= ~SIM_INT_MASK_TDTFM; + __raw_writel(reg_data, sim->ioaddr + INT_MASK); + } else { + reg_data = __raw_readl(sim->ioaddr + INT_MASK); + reg_data &= ~SIM_INT_MASK_TCIM; + __raw_writel(reg_data, sim->ioaddr + INT_MASK); + __raw_writel(SIM_XMT_STATUS_TC | SIM_XMT_STATUS_TDTF, + sim->ioaddr + XMT_STATUS); + reg_data = __raw_readl(sim->ioaddr + ENABLE); + reg_data |= SIM_ENABLE_XMTEN; + __raw_writel(reg_data, sim->ioaddr + ENABLE); + } +}; + +/* Function: sim_atr_add + * + * Description: add a byte to the raw ATR string + * + * Parameters: + * sim_t* sim pointer to SIM device handler + * uint8_t data byte to be added + */ + +static void sim_atr_add(sim_t *sim, uint8_t data) +{ + pr_debug("%s entering.\n", __func__); + if (sim->atr.size < SIM_ATR_LENGTH_MAX) + sim->atr.t[sim->atr.size++] = data; + else + printk(KERN_ERR "sim.c: ATR received is too big!\n"); +}; + +/* Function: sim_fsm + * + * Description: main finite state machine running in ISR context. + * + * Parameters: + * sim_t* sim pointer to SIM device handler + * uint8_t data byte received + */ + +static void sim_fsm(sim_t *sim, uint16_t data) +{ + uint32_t temp, i = 0; + switch (sim->state) { + + pr_debug("%s stat is %d \n", __func__, sim->state); + /* OPS FSM */ + + case SIM_STATE_OPERATIONAL_IDLE: + printk(KERN_INFO "data received unexpectidly (%04x)\n", data); + break; + + case SIM_STATE_OPERATIONAL_COMMAND: + if (data == sim->xmt_buffer[1]) { + if (sim->xfer.rcv_length) { + sim->state = SIM_STATE_OPERATIONAL_RESPONSE; + } else { + sim->state = SIM_STATE_OPERATIONAL_STATUS1; + if (sim->xfer.xmt_length > 5) + sim_xmt_start(sim, 5, + sim->xfer.xmt_length - 5); + }; + } else if (((data & 0xf0) == 0x60) | ((data & 0xf0) == 0x90)) { + sim->xfer.sw1 = data; + sim->state = SIM_STATE_OPERATIONAL_STATUS2; + } else { + sim->errval = -SIM_E_NACK; + complete(&sim->xfer_done); + }; + break; + + case SIM_STATE_OPERATIONAL_RESPONSE: + sim->rcv_buffer[sim->rcv_count] = data; + sim->rcv_count++; + if (sim->rcv_count == sim->xfer.rcv_length) + sim->state = SIM_STATE_OPERATIONAL_STATUS1; + break; + + case SIM_STATE_OPERATIONAL_STATUS1: + sim->xfer.sw1 = data; + sim->state = SIM_STATE_OPERATIONAL_STATUS2; + break; + + case SIM_STATE_OPERATIONAL_STATUS2: + sim->xfer.sw2 = data; + sim->state = SIM_STATE_OPERATIONAL_IDLE; + complete(&sim->xfer_done); + break; + + case SIM_STATE_OPERATIONAL_PTS: + sim->rcv_buffer[sim->rcv_count] = data; + sim->rcv_count++; + if (sim->rcv_count == sim->xfer.rcv_length) + sim->state = SIM_STATE_OPERATIONAL_IDLE; + break; + + /* ATR FSM */ + + case SIM_STATE_DETECTED_ATR_T0: + sim_atr_add(sim, data); + pr_debug("T0 %02x\n", data); + sim->atrparser.T0 = data; + sim->state = SIM_STATE_DETECTED_ATR_TS; + break; + + case SIM_STATE_DETECTED_ATR_TS: + sim_atr_add(sim, data); + pr_debug("TS %02x\n", data); + sim->atrparser.TS = data; + if (data & 0xf0) { + sim->atrparser.ifc_current_valid = (data >> 4) & 0x0f; + sim->atrparser.num_hb = data & 0x0f; + sim->atrparser.ifc_valid = 0; + sim->state = SIM_STATE_DETECTED_ATR_TXI; + sim->atrparser.cnt = 0; + } else { + goto sim_fsm_atr_thb; + }; + break; + + case SIM_STATE_DETECTED_ATR_TXI: + sim_atr_add(sim, data); + i = ffs(sim->atrparser.ifc_current_valid) - 1; + pr_debug("T%c%i %02x\n", 'A' + i, sim->atrparser.cnt + 1, data); + sim->atrparser.TXI[SIM_IFC_TXI(i, sim->atrparser.cnt)] = data; + sim->atrparser.ifc_valid |= 1 << SIM_IFC_TXI(i, + sim->atrparser. + cnt); + sim->atrparser.ifc_current_valid &= ~(1 << i); + + if (sim->atrparser.ifc_current_valid == 0) { + if (i == 3) { + sim->atrparser.ifc_current_valid = (data >> 4) + & 0x0f; + sim->atrparser.cnt++; + + if (sim->atrparser.cnt >= 4) { + /* error */ + printk(KERN_ERR "ERROR !\n"); + break; + }; + + if (sim->atrparser.ifc_current_valid == 0) + goto sim_fsm_atr_thb; + } else { +sim_fsm_atr_thb: + if (sim->atrparser.num_hb) { + sim->state = SIM_STATE_DETECTED_ATR_THB; + sim->atrparser.cnt = 0; + } else { + goto sim_fsm_atr_tck; + }; + }; + }; + break; + + case SIM_STATE_DETECTED_ATR_THB: + sim_atr_add(sim, data); + pr_debug("THB%i %02x\n", i, data); + sim->atrparser.THB[sim->atrparser.cnt] = data; + sim->atrparser.cnt++; + + if (sim->atrparser.cnt == sim->atrparser.num_hb) { +sim_fsm_atr_tck: + i = sim->atrparser.ifc_valid & (1 << (SIM_IFC_TD1)); + temp = sim->atrparser.TXI[SIM_IFC_TD1] & 0x0f; + if ((i && temp) == SIM_PROTOCOL_T1) + sim->state = SIM_STATE_DETECTED_ATR_TCK; + else + goto sim_fsm_atr_received; + }; + break; + + case SIM_STATE_DETECTED_ATR_TCK: + sim_atr_add(sim, data); + /* checksum not required for T=0 */ + sim->atrparser.TCK = data; +sim_fsm_atr_received: + sim->state = SIM_STATE_OPERATIONAL_IDLE; + sim->present = SIM_PRESENT_OPERATIONAL; + sim_atr_received(sim); + break; + }; +}; + +/* Function: sim_irq_handler + * + * Description: interrupt service routine. + * + * Parameters: + * int irq interrupt number + * void *dev_id pointer to SIM device handler + * + * Return values: + * IRQ_HANDLED OS specific + */ + +static irqreturn_t sim_irq_handler(int irq, void *dev_id) +{ + uint32_t reg_data, reg_data0, reg_data1; + + sim_t *sim = (sim_t *) dev_id; + + pr_debug("%s entering\n", __func__); + + reg_data0 = __raw_readl(sim->ioaddr + XMT_STATUS); + reg_data1 = __raw_readl(sim->ioaddr + INT_MASK); + if ((reg_data0 & SIM_XMT_STATUS_TC) + && (!(reg_data1 & SIM_INT_MASK_TCIM))) { + pr_debug("TC_IRQ\n"); + __raw_writel(SIM_XMT_STATUS_TC, sim->ioaddr + XMT_STATUS); + reg_data = __raw_readl(sim->ioaddr + INT_MASK); + reg_data |= SIM_INT_MASK_TCIM; + __raw_writel(reg_data, sim->ioaddr + INT_MASK); + reg_data = __raw_readl(sim->ioaddr + ENABLE); + reg_data &= ~SIM_ENABLE_XMTEN; + __raw_writel(reg_data, sim->ioaddr + ENABLE); + }; + + reg_data0 = __raw_readl(sim->ioaddr + XMT_STATUS); + reg_data1 = __raw_readl(sim->ioaddr + INT_MASK); + if ((reg_data0 & SIM_XMT_STATUS_TDTF) + && (!(reg_data1 & SIM_INT_MASK_TDTFM))) { + pr_debug("TDTF_IRQ\n"); + __raw_writel(SIM_XMT_STATUS_TDTF, sim->ioaddr + XMT_STATUS); + sim_xmt_fill(sim); + + if (sim->xmt_remaining == 0) { + __raw_writel(SIM_XMT_STATUS_TC, + sim->ioaddr + XMT_STATUS); + reg_data = __raw_readl(sim->ioaddr + INT_MASK); + reg_data &= ~SIM_INT_MASK_TCIM; + reg_data |= SIM_INT_MASK_TDTFM; + __raw_writel(reg_data, sim->ioaddr + INT_MASK); + }; + }; + + reg_data0 = __raw_readl(sim->ioaddr + RCV_STATUS); + reg_data1 = __raw_readl(sim->ioaddr + INT_MASK); + if ((reg_data0 & SIM_RCV_STATUS_RDRF) + && (!(reg_data1 & SIM_INT_MASK_RIM))) { + pr_debug("%s RDRF_IRQ\n", __func__); + __raw_writel(SIM_RCV_STATUS_RDRF, sim->ioaddr + RCV_STATUS); + + while (__raw_readl(sim->ioaddr + RCV_FIFO_CNT)) { + uint32_t data; + data = __raw_readl(sim->ioaddr + PORT1_RCV_BUF); + pr_debug("RX = %02x state = %i\n", data, sim->state); + if (data & 0x700) { + if (sim->xfer_ongoing) { + /* error */ + printk(KERN_ERR "ERROR !\n"); + return IRQ_HANDLED; + }; + } else + sim_fsm(sim, data); + }; + }; + + reg_data0 = __raw_readl(sim->ioaddr + PORT0_DETECT); + if (reg_data0 & SIM_PORT_DETECT_SDI) { + pr_debug("%s PD_IRQ\n", __func__); + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT); + reg_data |= SIM_PORT_DETECT_SDI; + __raw_writel(reg_data, sim->ioaddr + PORT0_DETECT); + + reg_data0 = __raw_readl(sim->ioaddr + PORT0_DETECT); + if (reg_data0 & SIM_PORT_DETECT_SPDP) { + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT); + reg_data &= ~SIM_PORT_DETECT_SPDS; + __raw_writel(reg_data, sim->ioaddr + PORT0_DETECT); + + if (sim->present != SIM_PRESENT_REMOVED) { + pr_debug("Removed sim card\n"); + sim->present = SIM_PRESENT_REMOVED; + sim->state = SIM_STATE_REMOVED; + + if (sim->fasync) + kill_fasync(&sim->fasync, + SIGIO, POLL_IN); + }; + } else { + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT); + reg_data |= SIM_PORT_DETECT_SPDS; + __raw_writel(reg_data, sim->ioaddr + PORT0_DETECT); + + if (sim->present == SIM_PRESENT_REMOVED) { + pr_debug("Inserted sim card\n"); + sim->state = SIM_STATE_DETECTED_ATR_T0; + sim->present = SIM_PRESENT_DETECTED; + + if (sim->fasync) + kill_fasync(&sim->fasync, + SIGIO, POLL_IN); + }; + }; + }; + + return IRQ_HANDLED; +}; + +/* Function: sim_power_on + * + * Description: run the power on sequence + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_power_on(sim_t *sim) +{ + uint32_t reg_data; + + /* power on sequence */ + pr_debug("%s Powering on the sim port.\n", __func__); + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data |= SIM_PORT_CNTL_SVEN; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + msleep(10); + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data |= SIM_PORT_CNTL_SCEN; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + msleep(10); + reg_data = SIM_RCV_THRESHOLD_RTH(0) | SIM_RCV_THRESHOLD_RDT(1); + __raw_writel(reg_data, sim->ioaddr + RCV_THRESHOLD); + __raw_writel(SIM_RCV_STATUS_RDRF, sim->ioaddr + RCV_STATUS); + reg_data = __raw_readl(sim->ioaddr + INT_MASK); + reg_data &= ~SIM_INT_MASK_RIM; + __raw_writel(reg_data, sim->ioaddr + INT_MASK); + __raw_writel(31, sim->ioaddr + DIVISOR); + reg_data = __raw_readl(sim->ioaddr + CNTL); + reg_data |= SIM_CNTL_SAMPLE12; + __raw_writel(reg_data, sim->ioaddr + CNTL); + reg_data = __raw_readl(sim->ioaddr + ENABLE); + reg_data |= SIM_ENABLE_RCVEN; + __raw_writel(reg_data, sim->ioaddr + ENABLE); + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data |= SIM_PORT_CNTL_SRST; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + pr_debug("%s port0_ctl is 0x%x.\n", __func__, + __raw_readl(sim->ioaddr + PORT0_CNTL)); + sim->power = SIM_POWER_ON; +}; + +/* Function: sim_power_off + * + * Description: run the power off sequence + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_power_off(sim_t *sim) +{ + uint32_t reg_data; + + pr_debug("%s entering.\n", __func__); + /* sim_power_off sequence */ + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data &= ~SIM_PORT_CNTL_SCEN; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + reg_data = __raw_readl(sim->ioaddr + ENABLE); + reg_data &= ~SIM_ENABLE_RCVEN; + __raw_writel(reg_data, sim->ioaddr + ENABLE); + reg_data = __raw_readl(sim->ioaddr + INT_MASK); + reg_data |= SIM_INT_MASK_RIM; + __raw_writel(reg_data, sim->ioaddr + INT_MASK); + __raw_writel(0, sim->ioaddr + RCV_THRESHOLD); + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data &= ~SIM_PORT_CNTL_SRST; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data &= ~SIM_PORT_CNTL_SVEN; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + sim->power = SIM_POWER_OFF; +}; + +/* Function: sim_start + * + * Description: ramp up the SIM interface + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_start(sim_t *sim) +{ + uint32_t reg_data, clk_rate, clk_div = 0; + + pr_debug("%s entering.\n", __func__); + /* Configuring SIM for Operation */ + reg_data = SIM_XMT_THRESHOLD_XTH(0) | SIM_XMT_THRESHOLD_TDT(4); + __raw_writel(reg_data, sim->ioaddr + XMT_THRESHOLD); + __raw_writel(0, sim->ioaddr + SETUP); + /* ~ 4 MHz */ + clk_rate = clk_get_rate(sim->clk); + clk_div = clk_rate / sim->plat_data->clk_rate; + if (clk_rate % sim->plat_data->clk_rate) + clk_div++; + pr_debug("%s prescaler is 0x%x.\n", __func__, clk_div); + __raw_writel(clk_div, sim->ioaddr + CLK_PRESCALER); + + reg_data = SIM_CNTL_GPCNT_CLK_SEL(0) | SIM_CNTL_BAUD_SEL(7) + | SIM_CNTL_SAMPLE12 | SIM_CNTL_ANACK | SIM_CNTL_ICM; + __raw_writel(reg_data, sim->ioaddr + CNTL); + __raw_writel(31, sim->ioaddr + DIVISOR); + reg_data = __raw_readl(sim->ioaddr + OD_CONFIG); + reg_data |= SIM_OD_CONFIG_OD_P0; + __raw_writel(reg_data, sim->ioaddr + OD_CONFIG); + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data |= SIM_PORT_CNTL_3VOLT | SIM_PORT_CNTL_STEN; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + + /* presense detect */ + pr_debug("%s p0_det is 0x%x \n", __func__, + __raw_readl(sim->ioaddr + PORT0_DETECT)); + if (__raw_readl(sim->ioaddr + PORT0_DETECT) & SIM_PORT_DETECT_SPDP) { + pr_debug("%s card removed \n", __func__); + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT); + reg_data &= ~SIM_PORT_DETECT_SPDS; + __raw_writel(reg_data, sim->ioaddr + PORT0_DETECT); + sim->present = SIM_PRESENT_REMOVED; + sim->state = SIM_STATE_REMOVED; + } else { + pr_debug("%s card inserted \n", __func__); + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT); + reg_data |= SIM_PORT_DETECT_SPDS; + __raw_writel(reg_data, sim->ioaddr + PORT0_DETECT); + sim->present = SIM_PRESENT_DETECTED; + sim->state = SIM_STATE_DETECTED_ATR_T0; + }; + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT); + reg_data |= SIM_PORT_DETECT_SDI; + reg_data &= ~SIM_PORT_DETECT_SDIM; + __raw_writel(reg_data, sim->ioaddr + PORT0_DETECT); + + /* + * Since there is no PD0 layout on MX51, assume + * that there is a SIM card in slot defaulty. + * */ + if (0 == (sim->plat_data->detect)) { + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT); + reg_data |= SIM_PORT_DETECT_SPDS; + __raw_writel(reg_data, sim->ioaddr + PORT0_DETECT); + sim->present = SIM_PRESENT_DETECTED; + sim->state = SIM_STATE_DETECTED_ATR_T0; + } + + if (sim->present == SIM_PRESENT_DETECTED) + sim_power_on(sim); + +}; + +/* Function: sim_stop + * + * Description: shut down the SIM interface + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_stop(sim_t *sim) +{ + pr_debug("%s entering.\n", __func__); + __raw_writel(0, sim->ioaddr + SETUP); + __raw_writel(0, sim->ioaddr + ENABLE); + __raw_writel(0, sim->ioaddr + PORT0_CNTL); + __raw_writel(0x06, sim->ioaddr + CNTL); + __raw_writel(0, sim->ioaddr + CLK_PRESCALER); + __raw_writel(0, sim->ioaddr + SETUP); + __raw_writel(0, sim->ioaddr + OD_CONFIG); + __raw_writel(0, sim->ioaddr + XMT_THRESHOLD); + __raw_writel(0xb8, sim->ioaddr + XMT_STATUS); + __raw_writel(4, sim->ioaddr + RESET_CNTL); + mdelay(1); +}; + +/* Function: sim_data_reset + * + * Description: reset a SIM structure to default values + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_data_reset(sim_t *sim) +{ + sim_param_t param_default = SIM_PARAM_DEFAULT; + sim->present = SIM_PRESENT_REMOVED; + sim->state = SIM_STATE_REMOVED; + sim->power = SIM_POWER_OFF; + sim->errval = SIM_OK; + memset(&sim->atrparser, 0, sizeof(sim->atrparser)); + memset(&sim->atr, 0, sizeof(sim->atr)); + sim->param_atr = param_default; + memset(&sim->param, 0, sizeof(sim->param)); + memset(&sim->xfer, 0, sizeof(sim->xfer)); + sim->xfer_ongoing = 0; + sim->xmt_remaining = 0; + sim->xmt_pos = 0; + sim->rcv_count = 0; + memset(sim->rcv_buffer, 0, SIM_RCV_BUFFER_SIZE); + memset(sim->xmt_buffer, 0, SIM_XMT_BUFFER_SIZE); +}; + +/* Function: sim_cold_reset + * + * Description: cold reset the SIM interface, including card + * power down and interface hardware reset. + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_cold_reset(sim_t *sim) +{ + pr_debug("%s entering.\n", __func__); + if (sim->present != SIM_PRESENT_REMOVED) { + sim_power_off(sim); + sim_stop(sim); + sim_data_reset(sim); + sim->state = SIM_STATE_DETECTED_ATR_T0; + sim->present = SIM_PRESENT_DETECTED; + msleep(50); + sim_start(sim); + sim_power_on(sim); + }; +}; + +/* Function: sim_warm_reset + * + * Description: warm reset the SIM interface: just invoke the + * reset signal and reset the SIM structure for the interface. + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static void sim_warm_reset(sim_t *sim) +{ + uint32_t reg_data; + + pr_debug("%s entering.\n", __func__); + if (sim->present != SIM_PRESENT_REMOVED) { + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data |= SIM_PORT_CNTL_SRST; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + sim_data_reset(sim); + msleep(50); + reg_data = __raw_readl(sim->ioaddr + PORT0_CNTL); + reg_data &= ~SIM_PORT_CNTL_SRST; + __raw_writel(reg_data, sim->ioaddr + PORT0_CNTL); + }; +}; + +/* Function: sim_card_lock + * + * Description: physically lock the SIM card. + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static int sim_card_lock(sim_t *sim) +{ + int errval; + + pr_debug("%s entering.\n", __func__); + /* place holder for true physcial locking */ + if (sim->present != SIM_PRESENT_REMOVED) + errval = SIM_OK; + else + errval = -SIM_E_NOCARD; + return errval; +}; + +/* Function: sim_card_eject + * + * Description: physically unlock and eject the SIM card. + * + * Parameters: + * sim_t* sim pointer to SIM device handler + */ + +static int sim_card_eject(sim_t *sim) +{ + int errval; + + pr_debug("%s entering.\n", __func__); + /* place holder for true physcial locking */ + if (sim->present != SIM_PRESENT_REMOVED) + errval = SIM_OK; + else + errval = -SIM_E_NOCARD; + return errval; +}; + +/* Function: sim_ioctl + * + * Description: handle ioctl calls + * + * Parameters: OS specific + */ + +static int sim_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret, errval = SIM_OK; + unsigned long timeout; + + sim_t *sim = (sim_t *) file->private_data; + + pr_debug("%s entering.\n", __func__); + switch (cmd) { + pr_debug("ioctl cmd %d is issued...\n", cmd); + + case SIM_IOCTL_GET_ATR: + if (sim->present != SIM_PRESENT_OPERATIONAL) { + errval = -SIM_E_NOCARD; + break; + }; + ret = copy_to_user((sim_atr_t *) arg, &sim->atr, + sizeof(sim_atr_t)); + if (ret) + errval = -SIM_E_ACCESS; + break; + + case SIM_IOCTL_GET_PARAM_ATR: + if (sim->present != SIM_PRESENT_OPERATIONAL) { + errval = -SIM_E_NOCARD; + break; + }; + ret = copy_to_user((sim_param_t *) arg, &sim->param_atr, + sizeof(sim_param_t)); + if (ret) + errval = -SIM_E_ACCESS; + break; + + case SIM_IOCTL_GET_PARAM: + ret = copy_to_user((sim_param_t *) arg, &sim->param, + sizeof(sim_param_t)); + if (ret) + errval = -SIM_E_ACCESS; + break; + + case SIM_IOCTL_SET_PARAM: + ret = copy_from_user(&sim->param, (sim_param_t *) arg, + sizeof(sim_param_t)); + if (ret) + errval = -SIM_E_ACCESS; + else + errval = sim_set_param(sim, &sim->param); + break; + + case SIM_IOCTL_POWER_ON: + if (sim->power == SIM_POWER_ON) { + errval = -SIM_E_POWERED_ON; + break; + }; + sim_power_on(sim); + break; + + case SIM_IOCTL_POWER_OFF: + if (sim->power == SIM_POWER_OFF) { + errval = -SIM_E_POWERED_OFF; + break; + }; + sim_power_off(sim); + break; + + case SIM_IOCTL_COLD_RESET: + if (sim->power == SIM_POWER_OFF) { + errval = -SIM_E_POWERED_OFF; + break; + }; + sim_cold_reset(sim); + break; + + case SIM_IOCTL_WARM_RESET: + sim_warm_reset(sim); + if (sim->power == SIM_POWER_OFF) { + errval = -SIM_E_POWERED_OFF; + break; + }; + break; + + case SIM_IOCTL_XFER: + if (sim->present != SIM_PRESENT_OPERATIONAL) { + errval = -SIM_E_NOCARD; + break; + }; + + ret = copy_from_user(&sim->xfer, (sim_xfer_t *) arg, + sizeof(sim_xfer_t)); + if (ret) { + errval = -SIM_E_ACCESS; + break; + }; + + ret = copy_from_user(sim->xmt_buffer, sim->xfer.xmt_buffer, + sim->xfer.xmt_length); + if (ret) { + errval = -SIM_E_ACCESS; + break; + }; + + sim->rcv_count = 0; + sim->xfer.sw1 = 0; + sim->xfer.sw2 = 0; + + if (sim->xfer.type == SIM_XFER_TYPE_TPDU) { + if (sim->xfer.xmt_length < 5) { + errval = -SIM_E_TPDUSHORT; + break; + } + sim->state = SIM_STATE_OPERATIONAL_COMMAND; + } else if (sim->xfer.type == SIM_XFER_TYPE_PTS) { + if (sim->xfer.xmt_length == 0) { + errval = -SIM_E_PTSEMPTY; + break; + } + sim->state = SIM_STATE_OPERATIONAL_PTS; + } else { + errval = -SIM_E_INVALIDXFERTYPE; + break; + }; + + if (sim->xfer.xmt_length > SIM_XMT_BUFFER_SIZE) { + errval = -SIM_E_INVALIDXMTLENGTH; + break; + }; + + if (sim->xfer.rcv_length > SIM_XMT_BUFFER_SIZE) { + errval = -SIM_E_INVALIDRCVLENGTH; + break; + }; + + sim->errval = 0; + sim->xfer_ongoing = 1; + init_completion(&sim->xfer_done); + sim_xmt_start(sim, 0, 5); + timeout = + wait_for_completion_interruptible_timeout(&sim->xfer_done, + sim->xfer. + timeout); + sim->xfer_ongoing = 0; + + if (sim->errval) { + errval = sim->errval; + break; + }; + + if (timeout == 0) { + errval = -SIM_E_TIMEOUT; + break; + } + + ret = copy_to_user(sim->xfer.rcv_buffer, sim->rcv_buffer, + sim->xfer.rcv_length); + if (ret) { + errval = -SIM_E_ACCESS; + break; + }; + + ret = copy_to_user((sim_xfer_t *) arg, &sim->xfer, + sizeof(sim_xfer_t)); + if (ret) + errval = -SIM_E_ACCESS; + break; + + case SIM_IOCTL_GET_PRESENSE: + if (put_user(sim->present, (int *)arg)) + errval = -SIM_E_ACCESS; + break; + + case SIM_IOCTL_CARD_LOCK: + errval = sim_card_lock(sim); + break; + + case SIM_IOCTL_CARD_EJECT: + errval = sim_card_eject(sim); + break; + + }; + + return errval; +}; + +/* Function: sim_fasync + * + * Description: async handler + * + * Parameters: OS specific + */ + +static int sim_fasync(int fd, struct file *file, int mode) +{ + sim_t *sim = (sim_t *) file->private_data; + pr_debug("%s entering.\n", __func__); + return fasync_helper(fd, file, mode, &sim->fasync); +} + +/* Function: sim_open + * + * Description: ramp up interface when being opened + * + * Parameters: OS specific + */ + +static int sim_open(struct inode *inode, struct file *file) +{ + int errval = SIM_OK; + + sim_t *sim = dev_get_drvdata(sim_dev.parent); + file->private_data = sim; + + pr_debug("%s entering.\n", __func__); + if (!sim->ioaddr) { + errval = -ENOMEM; + return errval; + } + + if (!(sim->clk_flag)) { + pr_debug("\n%s enable the clock\n", __func__); + clk_enable(sim->clk); + sim->clk_flag = 1; + } + + sim_start(sim); + + return errval; +}; + +/* Function: sim_release + * + * Description: shut down interface when being closed + * + * Parameters: OS specific + */ + +static int sim_release(struct inode *inode, struct file *file) +{ + uint32_t reg_data; + + sim_t *sim = (sim_t *) file->private_data; + + pr_debug("%s entering.\n", __func__); + if (sim->clk_flag) { + pr_debug("\n%s disable the clock\n", __func__); + clk_disable(sim->clk); + sim->clk_flag = 0; + } + + /* disable presense detection */ + reg_data = __raw_readl(sim->ioaddr + PORT0_DETECT); + __raw_writel(reg_data | SIM_PORT_DETECT_SDIM, + sim->ioaddr + PORT0_DETECT); + + if (sim->present != SIM_PRESENT_REMOVED) { + sim_power_off(sim); + if (sim->fasync) + kill_fasync(&sim->fasync, SIGIO, POLL_IN); + }; + + sim_stop(sim); + + sim_fasync(-1, file, 0); + + pr_debug("exit\n"); + return 0; +}; + +static const struct file_operations sim_fops = { + .open = sim_open, + .ioctl = sim_ioctl, + .fasync = sim_fasync, + .release = sim_release +}; + +static struct miscdevice sim_dev = { + MISC_DYNAMIC_MINOR, + "mxc_sim", + &sim_fops +}; + +/*****************************************************************************\ + * * + * Driver init/exit * + * * +\*****************************************************************************/ + +static int sim_probe(struct platform_device *pdev) +{ + int ret = 0; + struct mxc_sim_platform_data *sim_plat = pdev->dev.platform_data; + + sim_t *sim = kzalloc(sizeof(sim_t), GFP_KERNEL); + + if (sim == 0) { + ret = -ENOMEM; + printk(KERN_ERR "Can't get the MEMORY\n"); + return ret; + }; + + BUG_ON(pdev == NULL); + + sim->plat_data = sim_plat; + sim->clk_flag = 0; + + sim->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!sim->res) { + ret = -ENOMEM; + printk(KERN_ERR "Can't get the MEMORY\n"); + goto out; + } + + /* request the sim clk and sim_serial_clk */ + sim->clk = clk_get(NULL, sim->plat_data->clock_sim); + if (IS_ERR(sim->clk)) { + ret = PTR_ERR(sim->clk); + printk(KERN_ERR "Get CLK ERROR !\n"); + goto out; + } + pr_debug("sim clock:%lu\n", clk_get_rate(sim->clk)); + + sim->ipb_irq = platform_get_irq(pdev, 0); + sim->dat_irq = platform_get_irq(pdev, 1); + if (!(sim->ipb_irq | sim->dat_irq)) { + ret = -ENOMEM; + goto out1; + } + + if (!request_mem_region(sim->res->start, + sim->res->end - + sim->res->start + 1, pdev->name)) { + printk(KERN_ERR "request_mem_region failed\n"); + ret = -ENOMEM; + goto out1; + } + + sim->ioaddr = (void *)ioremap(sim->res->start, sim->res->end - + sim->res->start + 1); + if (sim->ipb_irq) + ret = request_irq(sim->ipb_irq, sim_irq_handler, + 0, "mxc_sim_ipb", sim); + if (sim->dat_irq) + ret |= request_irq(sim->dat_irq, sim_irq_handler, + 0, "mxc_sim_dat", sim); + + if (ret) { + printk(KERN_ERR "Can't get the irq\n"); + goto out2; + }; + + platform_set_drvdata(pdev, sim); + sim_dev.parent = &(pdev->dev); + + misc_register(&sim_dev); + + return ret; +out2: + if (sim->ipb_irq) + free_irq(sim->ipb_irq, sim); + if (sim->dat_irq) + free_irq(sim->dat_irq, sim); + release_mem_region(sim->res->start, + sim->res->end - sim->res->start + 1); +out1: + clk_put(sim->clk); +out: + kfree(sim); + return ret; +} + +static int sim_remove(struct platform_device *pdev) +{ + sim_t *sim = platform_get_drvdata(pdev); + + clk_put(sim->clk); + + if (sim->ipb_irq) + free_irq(sim->ipb_irq, sim); + if (sim->dat_irq) + free_irq(sim->dat_irq, sim); + + iounmap(sim->ioaddr); + + kfree(sim); + release_mem_region(sim->res->start, + sim->res->end - sim->res->start + 1); + + misc_deregister(&sim_dev); + return 0; +} + +static struct platform_driver sim_driver = { + .driver = { + .name = "mxc_sim", + }, + .probe = sim_probe, + .remove = sim_remove, + .suspend = NULL, + .resume = NULL, +}; + +static int __init sim_drv_init(void) +{ + return platform_driver_register(&sim_driver); +} + +static void __exit sim_drv_exit(void) +{ + platform_driver_unregister(&sim_driver); +} + +module_init(sim_drv_init); +module_exit(sim_drv_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC SIM Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/mxc_iim.c b/drivers/char/mxc_iim.c new file mode 100644 index 000000000000..bfb16c45380c --- /dev/null +++ b/drivers/char/mxc_iim.c @@ -0,0 +1,644 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mxc_iim_data *iim_data; + +#ifdef MXC_IIM_DEBUG +static inline void dump_reg(void) +{ + struct iim_regs *iim_reg_base = + (struct iim_regs *)iim_data->virt_base; + + dev_dbg(iim_data->dev, "stat: 0x%08x\n", + __raw_readl(&iim_reg_base->stat)); + dev_dbg(iim_data->dev, "statm: 0x%08x\n", + __raw_readl(&iim_reg_base->statm)); + dev_dbg(iim_data->dev, "err: 0x%08x\n", + __raw_readl(&iim_reg_base->err)); + dev_dbg(iim_data->dev, "emask: 0x%08x\n", + __raw_readl(&iim_reg_base->emask)); + dev_dbg(iim_data->dev, "fctl: 0x%08x\n", + __raw_readl(&iim_reg_base->fctl)); + dev_dbg(iim_data->dev, "ua: 0x%08x\n", + __raw_readl(&iim_reg_base->ua)); + dev_dbg(iim_data->dev, "la: 0x%08x\n", + __raw_readl(&iim_reg_base->la)); + dev_dbg(iim_data->dev, "sdat: 0x%08x\n", + __raw_readl(&iim_reg_base->sdat)); + dev_dbg(iim_data->dev, "prev: 0x%08x\n", + __raw_readl(&iim_reg_base->prev)); + dev_dbg(iim_data->dev, "srev: 0x%08x\n", + __raw_readl(&iim_reg_base->srev)); + dev_dbg(iim_data->dev, "preg_p: 0x%08x\n", + __raw_readl(&iim_reg_base->preg_p)); + dev_dbg(iim_data->dev, "scs0: 0x%08x\n", + __raw_readl(&iim_reg_base->scs0)); + dev_dbg(iim_data->dev, "scs1: 0x%08x\n", + __raw_readl(&iim_reg_base->scs1)); + dev_dbg(iim_data->dev, "scs2: 0x%08x\n", + __raw_readl(&iim_reg_base->scs2)); + dev_dbg(iim_data->dev, "scs3: 0x%08x\n", + __raw_readl(&iim_reg_base->scs3)); +} +#endif + +static inline void mxc_iim_disable_irq(void) +{ + struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + + __raw_writel(0x0, &(iim_reg_base->statm)); + __raw_writel(0x0, &(iim_reg_base->emask)); + + dev_dbg(iim_data->dev, "<= %s\n", __func__); +} + +static inline void fuse_op_start(void) +{ + struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + +#ifdef MXC_IIM_DEBUG + dump_reg(); +#endif + + /* Clear the status bits and error bits */ + __raw_writel(0x3, &(iim_reg_base->stat)); + __raw_writel(0xfe, &(iim_reg_base->err)); + /* Generate interrupt */ + __raw_writel(0x3, &(iim_reg_base->statm)); + __raw_writel(0xfe, &(iim_reg_base->emask)); + + dev_dbg(iim_data->dev, "<= %s\n", __func__); +} + +static u32 sense_fuse(s32 bank, s32 row, s32 bit) +{ + s32 addr, addr_l, addr_h; + s32 err = 0; + struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + + init_completion(&(iim_data->completion)); + + iim_data->action = POLL_FUSE_SNSD; + + fuse_op_start(); + + addr = ((bank << 11) | (row << 3) | (bit & 0x7)); + /* Set IIM Program Upper Address */ + addr_h = (addr >> 8) & 0x000000FF; + /* Set IIM Program Lower Address */ + addr_l = (addr & 0x000000FF); + + dev_dbg(iim_data->dev, "%s: addr_h=0x%x, addr_l=0x%x\n", + __func__, addr_h, addr_l); + __raw_writel(addr_h, &(iim_reg_base->ua)); + __raw_writel(addr_l, &(iim_reg_base->la)); + + /* Start sensing */ +#ifdef MXC_IIM_DEBUG + dump_reg(); +#endif + __raw_writel(0x8, &(iim_reg_base->fctl)); + + err = wait_for_completion_timeout(&(iim_data->completion), + msecs_to_jiffies(1000)); + err = (!err) ? -ETIMEDOUT : 0; + if (err) + dev_dbg(iim_data->dev, "Sense timeout!"); + + dev_dbg(iim_data->dev, "<= %s\n", __func__); + + return __raw_readl(&(iim_reg_base->sdat)); +} + +/* Blow fuses based on the bank, row and bit positions (all 0-based) +*/ +static s32 fuse_blow_bit(s32 bank, s32 row, s32 bit) +{ + int addr, addr_l, addr_h, err; + struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + + init_completion(&iim_data->completion); + + iim_data->action = POLL_FUSE_PRGD; + + fuse_op_start(); + + /* Disable IIM Program Protect */ + __raw_writel(0xaa, &(iim_reg_base->preg_p)); + + addr = ((bank << 11) | (row << 3) | (bit & 0x7)); + /* Set IIM Program Upper Address */ + addr_h = (addr >> 8) & 0x000000FF; + /* Set IIM Program Lower Address */ + addr_l = (addr & 0x000000FF); + + dev_dbg(iim_data->dev, "blowing addr_h=0x%x, addr_l=0x%x\n", + addr_h, addr_l); + + __raw_writel(addr_h, &(iim_reg_base->ua)); + __raw_writel(addr_l, &(iim_reg_base->la)); + + /* Start Programming */ +#ifdef MXC_IIM_DEBUG + dump_reg(); +#endif + __raw_writel(0x31, &(iim_reg_base->fctl)); + err = wait_for_completion_timeout(&(iim_data->completion), + msecs_to_jiffies(1000)); + err = (!err) ? -ETIMEDOUT : 0; + if (err) + dev_dbg(iim_data->dev, "Fuse timeout!\n"); + + /* Enable IIM Program Protect */ + __raw_writel(0x0, &(iim_reg_base->preg_p)); + + dev_dbg(iim_data->dev, "<= %s\n", __func__); + + return err; +} + +static void fuse_blow_row(s32 bank, s32 row, s32 value) +{ + u32 i; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + + /* Enable fuse blown */ + if (iim_data->enable_fuse) + iim_data->enable_fuse(); + + for (i = 0; i < 8; i++) { + if (((value >> i) & 0x1) == 0) + continue; + if (fuse_blow_bit(bank, row, i) != 0) { + dev_dbg(iim_data->dev, + "fuse_blow_bit(bank: %d, row: %d, " + "bit: %d failed\n", + bank, row, i); + } + } + + if (iim_data->disable_fuse) + iim_data->disable_fuse(); + + dev_dbg(iim_data->dev, "<= %s\n", __func__); +} + +static irqreturn_t mxc_iim_irq(int irq, void *dev_id) +{ + u32 status, error, rtn = 0; + ulong flags; + struct iim_regs *iim_reg_base = (struct iim_regs *)iim_data->virt_base; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + + spin_lock_irqsave(&iim_data->lock, flags); + + mxc_iim_disable_irq(); +#ifdef MXC_IIM_DEBUG + dump_reg(); +#endif + if (iim_data->action != POLL_FUSE_PRGD && + iim_data->action != POLL_FUSE_SNSD) { + dev_dbg(iim_data->dev, "%s(%d) invalid operation\n", + __func__, iim_data->action); + rtn = 1; + goto out; + } + + /* Test for successful write */ + status = readl(&(iim_reg_base->stat)); + error = readl(&(iim_reg_base->err)); + + if ((status & iim_data->action) != 0 && \ + (error & (iim_data->action >> IIM_ERR_SHIFT)) == 0) { + if (error) { + printk(KERN_NOTICE "Even though the operation" + "seems successful...\n"); + printk(KERN_NOTICE "There are some error(s) " + "at addr=0x%x: 0x%x\n", + (u32)&(iim_reg_base->err), error); + } + __raw_writel(0x3, &(iim_reg_base->stat)); + rtn = 0; + goto out; + } + printk(KERN_NOTICE "%s(%d) failed\n", __func__, iim_data->action); + printk(KERN_NOTICE "status address=0x%x, value=0x%x\n", + (u32)&(iim_reg_base->stat), status); + printk(KERN_NOTICE "There are some error(s) at addr=0x%x: 0x%x\n", + (u32)&(iim_reg_base->err), error); +#ifdef MXC_IIM_DEBUG + dump_reg(); +#endif + +out: + complete(&(iim_data->completion)); + spin_unlock_irqrestore(&iim_data->lock, flags); + + dev_dbg(iim_data->dev, "<= %s\n", __func__); + + return IRQ_RETVAL(rtn); +} + +static loff_t mxc_iim_llseek(struct file *filp, loff_t off, int whence) +{ + loff_t newpos; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + dev_dbg(iim_data->dev, "off: %lld, whence: %d\n", off, whence); + + if (off < iim_data->bank_start || + off > iim_data->bank_end) { + dev_dbg(iim_data->dev, "invalid seek offset: %lld\n", off); + goto invald_arg_out; + } + + switch (whence) { + case 0: /* SEEK_SET */ + newpos = off; + break; + case 1: /* SEEK_CUR */ + newpos = filp->f_pos + off; + break; + case 2: /* SEEK_END */ + newpos = iim_data->bank_end + off; + break; + default: /* can't happen */ + return -EINVAL; + + } + + if (newpos < 0) + return -EINVAL; + filp->f_pos = newpos; + + dev_dbg(iim_data->dev, "newpos: %lld\n", newpos); + + dev_dbg(iim_data->dev, "<= %s\n", __func__); + + return newpos; +invald_arg_out: + return -EINVAL; +} + +static ssize_t mxc_iim_read(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos) +{ + s32 bank; + s8 row, fuse_val; + ssize_t retval = 0; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + dev_dbg(iim_data->dev, "count: %d f_pos: %lld\n", count, *f_pos); + + if (1 != count) + goto invald_arg_out; + if (*f_pos & 0x3) + goto invald_arg_out; + if (*f_pos < iim_data->bank_start || + *f_pos > iim_data->bank_end) { + dev_dbg(iim_data->dev, "bank_start: 0x%08x, bank_end: 0x%08x\n", + iim_data->bank_start, iim_data->bank_end); + goto out; + } + + bank = (*f_pos - iim_data->bank_start) >> 10; + row = ((*f_pos - iim_data->bank_start) & 0x3ff) >> 2; + + dev_dbg(iim_data->dev, "Read fuse at bank:%d row:%d\n", + bank, row); + mutex_lock(&iim_data->mutex); + fuse_val = (s8)sense_fuse(bank, row, 0); + mutex_unlock(&iim_data->mutex); + dev_dbg(iim_data->dev, "fuses at (bank:%d, row:%d) = 0x%x\n", + bank, row, fuse_val); + if (copy_to_user(buf, &fuse_val, count)) { + retval = -EFAULT; + goto out; + } + +out: + retval = count; + dev_dbg(iim_data->dev, "<= %s\n", __func__); + return retval; +invald_arg_out: + retval = -EINVAL; + return retval; +} + +static ssize_t mxc_iim_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + s32 bank; + ulong fuse_val; + s8 row; + s8 *tmp_buf = NULL; + loff_t file_pos = *f_pos; + ssize_t retval = 0; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + dev_dbg(iim_data->dev, "count: %d f_pos: %lld\n", count, file_pos); + + tmp_buf = kmalloc(count + 1, GFP_KERNEL); + if (unlikely(!tmp_buf)) { + retval = -ENOMEM; + goto out; + } + memset(tmp_buf, 0, count + 1); + if (copy_from_user(tmp_buf, buf, count)) { + retval = -EFAULT; + goto out; + } + + if (count > 1 && 0 == file_pos) { + /* Check if file_pos and fuse val are in tmp_buf */ + if (sscanf(tmp_buf, "%x %x", + (s32 *)&file_pos, (s32 *)&fuse_val) < 0) { + dev_info(iim_data->dev, + "Invalid input string: %s\n", tmp_buf); + retval = -EINVAL; + goto out; + } + dev_dbg(iim_data->dev, + "file_pos: 0x%08x, fuse_val: 0x%08x\n", + (s32)file_pos, (s32)fuse_val); + } else if (1 == count) + fuse_val = tmp_buf[0]; + else { + dev_info(iim_data->dev, + "Invalid input: %s, count: %d, file pos: %d\n", + tmp_buf, count, (s32)file_pos); + retval = -EINVAL; + goto out; + } + + if (fuse_val > 0xff) { + dev_info(iim_data->dev, + "Invalid blow value: 0x%08x\n", (s32)fuse_val); + retval = -EINVAL; + goto out; + } + + if (file_pos & 0x3) { + dev_info(iim_data->dev, "file pos is not 4-byte aligned!\n"); + retval = -EINVAL; + goto out; + } + + if (file_pos < iim_data->bank_start || + file_pos > iim_data->bank_end) { + dev_dbg(iim_data->dev, + "bank_start: 0x%08x, bank_end: 0x%08x\n", + iim_data->bank_start, iim_data->bank_end); + dev_info(iim_data->dev, + "file pos out of range: 0x%08x\n", file_pos); + retval = -EINVAL; + goto out; + } + + bank = (file_pos - iim_data->bank_start) >> 10; + row = ((file_pos - iim_data->bank_start) & 0x3ff) >> 2; + + dev_dbg(iim_data->dev, "Blowing fuse at bank:%d row:%d value:%d\n", + bank, row, (int)fuse_val); + mutex_lock(&iim_data->mutex); + fuse_blow_row(bank, row, fuse_val); + fuse_val = sense_fuse(bank, row, 0); + mutex_unlock(&iim_data->mutex); + dev_dbg(iim_data->dev, "fuses at (bank:%d, row:%d) = 0x%x\n", + bank, row, (unsigned int)fuse_val); + + retval = count; +out: + if (tmp_buf) + kfree(tmp_buf); + dev_dbg(iim_data->dev, "<= %s\n", __func__); + return retval; +} + +/*! + * MXC IIM interface - memory map function + * This function maps IIM registers from IIM base address. + * + * @param file struct file * + * @param vma structure vm_area_struct * + * + * @return Return 0 on success or negative error code on error + */ +static int mxc_iim_mmap(struct file *file, struct vm_area_struct *vma) +{ + dev_dbg(iim_data->dev, "=> %s\n", __func__); + + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ + if (remap_pfn_range(vma, + vma->vm_start, + iim_data->reg_base >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) + return -EAGAIN; + + dev_dbg(iim_data->dev, "<= %s\n", __func__); + + return 0; +} + +/*! + * MXC IIM interface - open function + * + * @param inode struct inode * + * @param filp struct file * + * + * @return Return 0 on success or negative error code on error + */ +static int mxc_iim_open(struct inode *inode, struct file *filp) +{ + dev_dbg(iim_data->dev, "=> %s\n", __func__); + + dev_dbg(iim_data->dev, "iim_data addr: 0x%08x\n", (u32)iim_data); + + iim_data->clk = clk_get(NULL, "iim_clk"); + if (IS_ERR(iim_data->clk)) { + dev_err(iim_data->dev, "No IIM clock defined\n"); + return -ENODEV; + } + clk_enable(iim_data->clk); + + mxc_iim_disable_irq(); + + dev_dbg(iim_data->dev, "<= %s\n", __func__); + + return 0; +} + +/*! + * MXC IIM interface - release function + * + * @param inode struct inode * + * @param filp struct file * + * + * @return Return 0 on success or negative error code on error + */ +static int mxc_iim_release(struct inode *inode, struct file *filp) +{ + clk_disable(iim_data->clk); + clk_put(iim_data->clk); + return 0; +} + +static const struct file_operations mxc_iim_fops = { + .read = mxc_iim_read, + .write = mxc_iim_write, + .llseek = mxc_iim_llseek, + .mmap = mxc_iim_mmap, + .open = mxc_iim_open, + .release = mxc_iim_release, +}; + +static struct miscdevice mxc_iim_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "mxc_iim", + .fops = &mxc_iim_fops, +}; + +/*! + * This function is called by the driver framework to get iim base/end address + * and register iim misc device. + * + * @param dev The device structure for IIM passed in by the driver + * framework. + * + * @return Returns 0 on success or negative error code on error + */ +static __devinit int mxc_iim_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret; + + iim_data = pdev->dev.platform_data; + iim_data->dev = &pdev->dev; + iim_data->name = mxc_iim_miscdev.name; + + dev_dbg(iim_data->dev, "=> %s\n", __func__); + + dev_dbg(iim_data->dev, "iim_data addr: 0x%08x " + "bank_start: 0x%04x bank_end: 0x%04x " + "enable_fuse: 0x%08x disable_fuse: 0x%08x\n", + (u32)iim_data, + iim_data->bank_start, iim_data->bank_end, + (u32)iim_data->enable_fuse, + (u32)iim_data->disable_fuse); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) { + dev_err(iim_data->dev, "Unable to get IIM resource\n"); + return -ENODEV; + } + + iim_data->irq = platform_get_irq(pdev, 0); + dev_dbg(iim_data->dev, "irq number: %d\n", iim_data->irq); + if (!iim_data->irq) { + ret = -ENOMEM; + return ret; + } + + ret = request_irq(iim_data->irq, mxc_iim_irq, IRQF_DISABLED, + iim_data->name, iim_data); + if (ret) + return ret; + + iim_data->reg_base = res->start; + iim_data->reg_end = res->end; + iim_data->reg_size = + iim_data->reg_end - iim_data->reg_base + 1; + iim_data->virt_base = + (u32)ioremap(iim_data->reg_base, iim_data->reg_size); + + mutex_init(&(iim_data->mutex)); + spin_lock_init(&(iim_data->lock)); + + ret = misc_register(&mxc_iim_miscdev); + if (ret) + return ret; + + dev_dbg(iim_data->dev, "<= %s\n", __func__); + + return 0; +} + +static int __devexit mxc_iim_remove(struct platform_device *pdev) +{ + free_irq(iim_data->irq, iim_data); + iounmap((void *)iim_data->virt_base); + misc_deregister(&mxc_iim_miscdev); + return 0; +} + +static struct platform_driver mxc_iim_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mxc_iim", + }, + .probe = mxc_iim_probe, + .remove = mxc_iim_remove, +}; + +static int __init mxc_iim_dev_init(void) +{ + return platform_driver_register(&mxc_iim_driver); +} + +static void __exit mxc_iim_dev_cleanup(void) +{ + platform_driver_unregister(&mxc_iim_driver); +} + +module_init(mxc_iim_dev_init); +module_exit(mxc_iim_dev_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC IIM driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(MISC_DYNAMIC_MINOR); diff --git a/drivers/char/mxc_si4702.c b/drivers/char/mxc_si4702.c new file mode 100644 index 000000000000..7d36f2902bb4 --- /dev/null +++ b/drivers/char/mxc_si4702.c @@ -0,0 +1,1223 @@ +/* + * linux/drivers/char/mxc_si4702.c + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SI4702_DEV_NAME "si4702" +#define DEV_MAJOR 0 /* this could be module param */ +#define DEV_MINOR 0 +#define DEV_BASE_MINOR 0 +#define DEV_MINOR_COUNT 256 +#define SI4702_I2C_ADDR 0x10 /* 7bits I2C address */ +#define DELAY_WAIT 0xffff /* loop_counter max value */ +/* register define */ +#define SI4702_DEVICEID 0x00 +#define SI4702_CHIPID 0x01 +#define SI4702_POWERCFG 0x02 +#define SI4702_CHANNEL 0x03 +#define SI4702_SYSCONFIG1 0x04 +#define SI4702_SYSCONFIG2 0x05 +#define SI4702_SYSCONFIG3 0x06 +#define SI4702_TEST1 0x07 +#define SI4702_TEST2 0x08 +#define SI4702_B00TCONFIG 0x09 +#define SI4702_STATUSRSSI 0x0A +#define SI4702_READCHAN 0x0B +#define SI4702_REG_NUM 0x10 +#define SI4702_REG_BYTE (SI4702_REG_NUM * 2) +#define SI4702_DEVICE_ID 0x1242 +#define SI4702_RW_REG_NUM (SI4702_STATUSRSSI - SI4702_POWERCFG) +#define SI4702_RW_OFFSET \ + (SI4702_REG_NUM - SI4702_STATUSRSSI + SI4702_POWERCFG) + +#define SI4702_SPACE_MASK 0x0030 +#define SI4702_SPACE_200K 0x0 +#define SI4702_SPACE_100K 0x10 +#define SI4702_SPACE_50K 0x20 + +#define SI4702_BAND_MASK 0x00c0 +#define SI4702_BAND_LSB 6 + +#define SI4702_SEEKTH_MASK 0xff00 +#define SI4702_SEEKTH_LSB 8 + +#define SI4702_SNR_MASK 0x00f0 +#define SI4702_SNR_LSB 4 + +#define SI4702_CNT_MASK 0x000f +#define SI4702_CNT_LSB 0 + +#define SI4702_VOL_MASK 0x000f +#define SI4702_VOL_LSB 0 + +#define SI4702_CHAN_MASK 0x03ff +#define SI4702_TUNE_BIT 0x8000 +#define SI4702_STC_BIT 0x4000 +#define SI4702_DMUTE_BIT 0x4000 +#define SI4702_SEEKUP_BIT 0x0200 +#define SI4702_SEEK_BIT 0x0100 +#define SI4702_SF_BIT 0x2000 +#define SI4702_ENABLE_BIT 0x0001 +#define SI4702_DISABLE_BIT 0x0040 + +enum { + BAND_USA = 0, + BAND_JAP_W, + BAND_JAP +}; + +struct si4702_info { + int min_band; + int max_band; + int space; + int volume; + int channel; + int mute; +}; + +struct si4702_drvdata { + struct regulator *vio; + struct regulator *vdd; + struct class *radio_class; + struct si4702_info info; + /*by default, dev major is zero, and it's alloc dynamicaly. */ + int major; + int minor; + struct cdev *cdev; + int count; /* open count */ + struct i2c_client *client; + unsigned char reg_rw_buf[SI4702_REG_BYTE]; + struct mxc_fm_platform_data *plat_data; +}; + +static struct si4702_drvdata *si4702_drvdata; + +DEFINE_SPINLOCK(count_lock); + +#ifdef DEBUG +static void si4702_dump_reg(void) +{ + int i, j; + unsigned char *reg_rw_buf; + + if (NULL == si4702_drvdata) + return; + + reg_rw_buf = si4702_drvdata->reg_rw_buf; + + for (i = 0; i < 10; i++) { + j = i * 2 + 12; + pr_debug("reg[%02d] = %04x\n", i, + ((reg_rw_buf[j] << 8) & 0xFF00) + + (reg_rw_buf[j + 1] & 0x00FF)); + } + for (; i < 16; i++) { + j = (i - 10) * 2; + pr_debug("reg[%02d] = %04x\n", i, + ((reg_rw_buf[j] << 8) & 0xFF00) + + (reg_rw_buf[j + 1] & 0x00FF)); + } +} +#else +static void si4702_dump_reg(void) +{ +} +#endif /* DEBUG */ + +/* + *check the si4702 spec for the read/write concequence. + * + *0 2 A F0 A F + *------------------------------- + * buf:0 2 A F + */ +#define REG_to_BUF(reg) (((reg >= 0) && (reg < SI4702_STATUSRSSI)) ? \ + (reg - SI4702_STATUSRSSI + SI4702_REG_NUM) : \ + ((reg >= SI4702_STATUSRSSI) && (reg < SI4702_REG_NUM)) ? \ + (reg - SI4702_STATUSRSSI) : -1) + +static int si4702_read_reg(const int reg, u16 *value) +{ + int ret, index; + unsigned char *reg_rw_buf; + + if (NULL == si4702_drvdata) + return -1; + + reg_rw_buf = si4702_drvdata->reg_rw_buf; + + index = REG_to_BUF(reg); + + if (-1 == index) + return -1; + + ret = + i2c_master_recv(si4702_drvdata->client, reg_rw_buf, + SI4702_REG_BYTE); + + *value = (reg_rw_buf[index * 2] << 8) & 0xFF00; + *value |= reg_rw_buf[index * 2 + 1] & 0x00FF; + + return ret < 0 ? ret : 0; +} + +static int si4702_write_reg(const int reg, const u16 value) +{ + int index, ret; + unsigned char *reg_rw_buf; + + if (NULL == si4702_drvdata) + return -1; + + reg_rw_buf = si4702_drvdata->reg_rw_buf; + + index = REG_to_BUF(reg); + + if (-1 == index) + return -1; + + reg_rw_buf[index * 2] = (value & 0xFF00) >> 8; + reg_rw_buf[index * 2 + 1] = value & 0x00FF; + + ret = i2c_master_send(si4702_drvdata->client, + ®_rw_buf[SI4702_RW_OFFSET * 2], + (SI4702_STATUSRSSI - SI4702_POWERCFG) * 2); + return ret < 0 ? ret : 0; +} + +static void si4702_gpio_get(void) +{ + if (NULL == si4702_drvdata) + return; + + si4702_drvdata->plat_data->gpio_get(); +} + +static void si4702_gpio_put(void) +{ + if (NULL == si4702_drvdata) + return; + + si4702_drvdata->plat_data->gpio_put(); +} + +static void si4702_reset(void) +{ + if (NULL == si4702_drvdata) + return; + + si4702_drvdata->plat_data->reset(); +} + +static void si4702_clock_en(int flag) +{ + if (NULL == si4702_drvdata) + return; + + si4702_drvdata->plat_data->clock_ctl(flag); +} + +static int si4702_id_detect(struct i2c_client *client) +{ + int ret, index; + unsigned int ID = 0; + unsigned char reg_rw_buf[SI4702_REG_BYTE]; + + si4702_gpio_get(); + si4702_reset(); + si4702_clock_en(1); + + ret = i2c_master_recv(client, (char *)reg_rw_buf, SI4702_REG_BYTE); + + si4702_gpio_put(); + + if (ret < 0) + return ret; + + index = REG_to_BUF(SI4702_DEVICEID); + if (index < 0) + return index; + + ID = (reg_rw_buf[index * 2] << 8) & 0xFF00; + ID |= reg_rw_buf[index * 2 + 1] & 0x00FF; + + return ID; +} + +/* valid args 50/100/200 */ +static int si4702_set_space(int space) +{ + u16 reg; + int ret; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG2, ®); + if (ret == -1) + return ret; + + reg &= ~SI4702_SPACE_MASK; + switch (space) { + case 50: + reg |= SI4702_SPACE_50K; + break; + case 100: + reg |= SI4702_SPACE_100K; + break; + case 200: + ret |= SI4702_SPACE_200K; + break; + default: + return -1; + } + + ret = si4702_write_reg(SI4702_SYSCONFIG2, reg); + if (ret == -1) + return ret; + + info = &si4702_drvdata->info; + info->space = space; + return 0; +} + +static int si4702_set_band_range(int band) +{ + u16 reg; + int ret, band_min, band_max; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + switch (band) { + case BAND_USA: + band_min = 87500; + band_max = 108000; + break; + case BAND_JAP_W: + band_min = 76000; + band_max = 108000; + break; + case BAND_JAP: + band_min = 76000; + band_max = 90000; + break; + default: + return -1; + } + + ret = si4702_read_reg(SI4702_SYSCONFIG2, ®); + if (ret == -1) + return ret; + + reg = (reg & ~SI4702_BAND_MASK) + | ((band << SI4702_BAND_LSB) & SI4702_BAND_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG2, reg); + if (ret == -1) + return ret; + + info = &si4702_drvdata->info; + info->min_band = band_min; + info->max_band = band_max; + return 0; +} + +static int si4702_set_seekth(u8 seekth) +{ + u16 reg; + int ret; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG2, ®); + if (ret == -1) + return ret; + + reg = + (reg & ~SI4702_SEEKTH_MASK) | ((seekth << SI4702_SEEKTH_LSB) & + SI4702_SEEKTH_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG2, reg); + if (ret == -1) + return ret; + + return 0; +} + +static int si4702_set_sksnr(u8 sksnr) +{ + u16 reg; + int ret; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG3, ®); + if (ret == -1) + return ret; + + reg = + (reg & ~SI4702_SNR_MASK) | ((sksnr << SI4702_SNR_LSB) & + SI4702_SNR_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG3, reg); + if (ret == -1) + return ret; + + return 0; +} + +static int si4702_set_skcnt(u8 skcnt) +{ + u16 reg; + int ret; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG3, ®); + if (ret == -1) + return ret; + + reg = (reg & ~SI4702_CNT_MASK) | (skcnt & SI4702_CNT_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG3, reg); + if (ret == -1) + return ret; + + return 0; +} + +static int si4702_set_vol(int vol) +{ + u16 reg; + int ret; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + ret = si4702_read_reg(SI4702_SYSCONFIG2, ®); + if (ret == -1) + return ret; + + reg = (reg & ~SI4702_VOL_MASK) | (vol & SI4702_VOL_MASK); + ret = si4702_write_reg(SI4702_SYSCONFIG2, reg); + if (ret == -1) + return ret; + + info = &si4702_drvdata->info; + info->volume = vol; + + return 0; +} + +static u8 si4702_channel_select(u32 freq) +{ + u16 loop_counter = 0; + s16 channel; + u16 si4702_reg_data; + u8 error_ind = 0; + struct i2c_client *client; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + info = &si4702_drvdata->info; + client = si4702_drvdata->client; + + dev_info(&client->dev, "Input frequnce is %d\n", freq); + if (freq < 76000 || freq > 108000) { + dev_err(&client->dev, "Input frequnce is invalid\n"); + return -1; + } + /* convert freq to channel */ + channel = (freq - info->min_band) / info->space; + + si4702_reg_data = SI4702_TUNE_BIT | (channel & SI4702_CHAN_MASK); + /* set channel */ + error_ind = si4702_write_reg(SI4702_CHANNEL, si4702_reg_data); + if (error_ind) { + dev_err(&client->dev, "Failed to set channel\n"); + return -1; + } + dev_info(&client->dev, "Set channel to %d\n", channel); + + /* wait for STC == 1 */ + do { + error_ind = + si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, "Failed to read setted STC\n"); + return -1; + } + if ((si4702_reg_data & SI4702_STC_BIT) != 0) + break; + } while (++loop_counter < DELAY_WAIT); + + /* check loop_counter */ + if (loop_counter >= DELAY_WAIT) { + dev_err(&client->dev, "Can't wait for STC bit set"); + return -1; + } + dev_info(&client->dev, "loop counter %d\n", loop_counter); + + loop_counter = 0; + /* clear tune bit */ + error_ind = si4702_write_reg(SI4702_CHANNEL, 0); + + if (error_ind) { + dev_err(&client->dev, "Failed to set stop tune\n"); + return -1; + } + + /* wait for STC == 0 */ + do { + error_ind = + si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, "Failed to set read STC\n"); + return -1; + } + if ((si4702_reg_data & SI4702_STC_BIT) == 0) + break; + } while (++loop_counter < DELAY_WAIT); + + /* check loop_counter */ + if (loop_counter >= DELAY_WAIT) { + dev_err(&client->dev, "Can't wait for STC bit clean"); + return -1; + } + dev_info(&client->dev, "loop counter %d\n", loop_counter); + + /* read RSSI */ + error_ind = si4702_read_reg(SI4702_READCHAN, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, "Failed to read RSSI\n"); + return -1; + } + + channel = si4702_reg_data & SI4702_CHAN_MASK; + dev_info(&client->dev, "seek finish: channel(%d)\n", channel); + + return 0; +} + +static s32 si4702_channel_seek(s16 dir) +{ + u16 loop_counter = 0; + u16 si4702_reg_data, reg_power_cfg; + u8 error_ind = 0; + u32 channel, freq; + struct i2c_client *client; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + info = &si4702_drvdata->info; + client = si4702_drvdata->client; + + error_ind = si4702_read_reg(SI4702_POWERCFG, ®_power_cfg); + + if (info->mute) { + /* check disable mute */ + reg_power_cfg &= ~SI4702_DMUTE_BIT; + } else { + reg_power_cfg |= SI4702_DMUTE_BIT; + } + + if (dir) { + reg_power_cfg |= SI4702_SEEKUP_BIT; + } else { + reg_power_cfg &= ~SI4702_SEEKUP_BIT; + } + /* start seek */ + reg_power_cfg |= SI4702_SEEK_BIT; + error_ind = si4702_write_reg(SI4702_POWERCFG, reg_power_cfg); + + if (error_ind) { + dev_err(&client->dev, "Failed to set seek start bit\n"); + return -1; + } + + /* wait STC == 1 */ + do { + error_ind = + si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data); + if (error_ind) { + dev_err(&client->dev, "Failed to read STC bit\n"); + return -1; + } + + if ((si4702_reg_data & SI4702_STC_BIT) != 0) + break; + } while (++loop_counter < DELAY_WAIT); + + /* clear seek bit */ + reg_power_cfg &= ~SI4702_SEEK_BIT; + error_ind = si4702_write_reg(SI4702_POWERCFG, reg_power_cfg); + if (error_ind) { + dev_err(&client->dev, "Failed to stop seek\n"); + return -1; + } + + if (loop_counter >= DELAY_WAIT) { + dev_err(&client->dev, "Can't wait for STC bit set\n"); + return -1; + } + + /* check whether SF==1 (seek failed bit) */ + if ((si4702_reg_data & SI4702_SF_BIT) != 0) { + dev_err(&client->dev, "Failed to seek any channel\n"); + return -1; + } + + loop_counter = 0; + /* wait STC == 0 */ + do { + error_ind = + si4702_read_reg(SI4702_STATUSRSSI, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, + "Failed to wait STC bit to clear\n"); + return -1; + } + if ((si4702_reg_data & SI4702_STC_BIT) == 0) + break; + } while (++loop_counter < DELAY_WAIT); + + /* check loop_counter */ + if (loop_counter >= DELAY_WAIT) { + dev_err(&client->dev, "Can't wait for STC bit clean"); + return -1; + } + + error_ind = si4702_read_reg(SI4702_READCHAN, &si4702_reg_data); + + if (error_ind) { + dev_err(&client->dev, "I2C simulate failed\n"); + return -1; + } + + channel = si4702_reg_data & SI4702_CHAN_MASK; + freq = channel * info->space + info->min_band; + dev_err(&client->dev, + "seek finish: channel(%d), freq(%dKHz)\n", channel, freq); + + return 0; +} + +static int si4702_startup(void) +{ + u16 magic = 0, id; + struct i2c_client *client; + struct mxc_fm_platform_data *data; + + if (NULL == si4702_drvdata) + return -1; + + if (si4702_drvdata->vio) + regulator_enable(si4702_drvdata->vio); + if (si4702_drvdata->vdd) + regulator_enable(si4702_drvdata->vdd); + data = si4702_drvdata->plat_data; + client = si4702_drvdata->client; + + /* read prior to write, otherwise write op will fail */ + si4702_read_reg(SI4702_DEVICEID, &id); + dev_err(&client->dev, "si4702: DEVICEID: 0x%x\n", id); + + si4702_clock_en(1); + msleep(100); + + /* disable mute, stereo, seek down, powerup */ + si4702_write_reg(SI4702_POWERCFG, SI4702_DMUTE_BIT | SI4702_ENABLE_BIT); + msleep(500); + si4702_read_reg(SI4702_TEST1, &magic); + if (magic != 0x3C04) + dev_err(&client->dev, "magic number 0x%x.\n", magic); + /* close tune, set channel to 0 */ + si4702_write_reg(SI4702_CHANNEL, 0); + /* disable interrupt, disable GPIO */ + si4702_write_reg(SI4702_SYSCONFIG1, 0); + /* set volume to middle level */ + si4702_set_vol(0xf); + + si4702_set_space(data->space); + si4702_set_band_range(data->band); + si4702_set_seekth(data->seekth); + si4702_set_skcnt(data->skcnt); + si4702_set_sksnr(data->sksnr); + + return 0; +} + +static void si4702_shutdown(void) +{ + if (NULL == si4702_drvdata) + return; + + si4702_write_reg(SI4702_POWERCFG, SI4702_DMUTE_BIT | + SI4702_ENABLE_BIT | SI4702_DISABLE_BIT); + msleep(100); + si4702_clock_en(0); + + if (si4702_drvdata->vdd) + regulator_disable(si4702_drvdata->vdd); + if (si4702_drvdata->vio) + regulator_disable(si4702_drvdata->vio); +} + +enum { + FM_STARTUP = 0, + FM_SHUTDOWN, + FM_RESET, + FM_VOLUP, + FM_VOLDOWN, + FM_SEEK_UP, + FM_SEEK_DOWN, + FM_MUTEON, + FM_MUTEDIS, + FM_SEL, + FM_SEEKTH, + FM_DL, + FM_CTL_MAX +}; + +static const char *const fm_control[FM_CTL_MAX] = { + [FM_STARTUP] = "start", + [FM_SHUTDOWN] = "halt", + [FM_RESET] = "reset", + [FM_VOLUP] = "volup", + [FM_VOLDOWN] = "voldown", + [FM_SEEK_UP] = "seeku", + [FM_SEEK_DOWN] = "seekd", + [FM_MUTEON] = "mute", + [FM_MUTEDIS] = "muted", + [FM_SEL] = "select", + [FM_SEEKTH] = "seekth", + [FM_DL] = "delay" +}; + +static int cmd(unsigned int index, int arg) +{ + struct i2c_client *client; + struct mxc_fm_platform_data *plat_data; + + if (NULL == si4702_drvdata) + return -1; + + client = si4702_drvdata->client; + plat_data = si4702_drvdata->plat_data; + + switch (index) { + case FM_SHUTDOWN: + dev_err(&client->dev, "FM_SHUTDOWN\n"); + si4702_shutdown(); + break; + case FM_STARTUP: + dev_err(&client->dev, "FM_STARTUP\n"); + si4702_reset(); + si4702_startup(); + break; + case FM_RESET: + dev_err(&client->dev, "FM_RESET\n"); + si4702_reset(); + break; + case FM_SEEK_DOWN: + dev_err(&client->dev, "SEEK DOWN\n"); + si4702_channel_seek(0); + break; + case FM_SEEK_UP: + dev_err(&client->dev, "SEEK UP\n"); + si4702_channel_seek(1); + break; + case FM_SEL: + dev_err(&client->dev, "select %d\n", arg * 100); + si4702_channel_select(arg * 100); + break; + case FM_SEEKTH: + dev_err(&client->dev, "seekth = %d\n", arg); + si4702_set_seekth(arg); + break; + case FM_DL: + dev_err(&client->dev, "delay = %d\n", arg); + break; + default: + dev_err(&client->dev, "error command\n"); + break; + } + return 0; +} + +static ssize_t si4702_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct si4702_drvdata *drv_data = dev_get_drvdata(dev); + u16 device_id; + + dev_err(&(drv_data->client->dev), "si4702 show\n"); + si4702_read_reg(SI4702_DEVICEID, &device_id); + pr_info("device id %x\n", device_id); + si4702_dump_reg(); + return 0; +} + +static ssize_t si4702_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int state = 0; + const char *const *s; + char *p = NULL; + int error; + int len, arg = 0; + struct si4702_drvdata *drv_data = dev_get_drvdata(dev); + struct i2c_client *client = drv_data->client; + + dev_err(&client->dev, "si4702 store %d\n", count); + + p = memchr(buf, ' ', count); + if (p) { + len = p - buf; + *p = '\0'; + } else + len = count; + + len -= 1; + dev_err(&client->dev, "cmd %s\n", buf); + + for (s = &fm_control[state]; state < FM_CTL_MAX; s++, state++) { + if (*s && !strncmp(buf, *s, len)) { + break; + } + } + if (state < FM_CTL_MAX && *s) { + if (p) + arg = simple_strtoul(p + 1, NULL, 0); + dev_err(&client->dev, "arg = %d\n", arg); + error = cmd(state, arg); + } else { + dev_err(&client->dev, "error cmd\n"); + error = -EINVAL; + } + + return error ? error : count; +} + +static int ioctl_si4702(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + void __user *argp = (void __user *)arg; + int mute = 0; + u16 data; + int error; + u8 volume; + unsigned int freq; + int dir; + struct i2c_client *client; + struct si4702_info *info; + + if (NULL == si4702_drvdata) + return -1; + + info = &si4702_drvdata->info; + client = si4702_drvdata->client; + + dev_err(&client->dev, "ioctl, cmd: 0x%x, arg: 0x%lx\n", cmd, arg); + + switch (cmd) { + case SI4702_SETVOLUME: + /* get volume from user */ + if (copy_from_user(&volume, argp, sizeof(u8))) { + + dev_err(&client->dev, + "ioctl, copy volume value from user failed\n"); + return -EFAULT; + } + dev_err(&client->dev, "volume %d\n", volume); + /* refill the register value */ + volume &= 0x0f; + if (info->mute) + error = si4702_write_reg(SI4702_POWERCFG, 0x0001); + else + error = si4702_write_reg(SI4702_POWERCFG, 0x4001); + + error = si4702_write_reg(SI4702_CHANNEL, 0); + error = si4702_write_reg(SI4702_SYSCONFIG1, 0); + error = si4702_write_reg(SI4702_SYSCONFIG2, 0x0f10 | volume); + if (error) { + dev_err(&client->dev, "ioctl, set volume failed\n"); + return -EFAULT; + } + /* renew the device info */ + info->volume = volume; + + break; + case SI4702_GETVOLUME: + /* just copy volume value to user */ + if (copy_to_user(argp, &(info->volume), sizeof(unsigned int))) { + dev_err(&client->dev, "ioctl, copy to user failed\n"); + return -EFAULT; + } + break; + case SI4702_MUTEON: + mute = 1; + case SI4702_MUTEOFF: + if (mute) { + /* enable mute */ + si4702_read_reg(SI4702_POWERCFG, &data); + data &= 0x00FF; + error = si4702_write_reg(SI4702_POWERCFG, data); + } else { + si4702_read_reg(SI4702_POWERCFG, &data); + data &= 0x00FF; + data |= 0x4000; + error = si4702_write_reg(SI4702_POWERCFG, data); + } + if (error) { + dev_err(&client->dev, "ioctl, set mute failed\n"); + return -EFAULT; + } + break; + case SI4702_SELECT: + if (copy_from_user(&freq, argp, sizeof(unsigned int))) { + + dev_err(&client->dev, + "ioctl, copy frequence from user failed\n"); + return -EFAULT; + } + /* check frequence */ + if (freq > info->max_band || freq < info->min_band) { + dev_err(&client->dev, + "the frequence select is out of band\n"); + return -EINVAL; + } + if (si4702_channel_select(freq)) { + dev_err(&client->dev, + "ioctl, failed to select channel\n"); + return -EFAULT; + } + break; + case SI4702_SEEK: + if (copy_from_user(&dir, argp, sizeof(int))) { + + dev_err(&client->dev, "ioctl, copy from user failed\n"); + return -EFAULT; + } + /* get seeked channel */ + dir = si4702_channel_seek(dir); + if (dir == -1) { + return -EAGAIN; + } else if (dir == -2) { + return -EFAULT; + } + if (copy_to_user(argp, &dir, sizeof(int))) { + + dev_err(&client->dev, + "ioctl, copy seek frequnce to user failed\n"); + return -EFAULT; + } + break; + default: + dev_err(&client->dev, "SI4702: Invalid ioctl command\n"); + return -EINVAL; + + } + return 0; +} + +static int open_si4702(struct inode *inode, struct file *file) +{ + struct i2c_client *client; + + if (NULL == si4702_drvdata) + return -1; + + client = si4702_drvdata->client; + + spin_lock(&count_lock); + if (si4702_drvdata->count != 0) { + dev_err(&client->dev, "device has been open already\n"); + spin_unlock(&count_lock); + return -EBUSY; + } + si4702_drvdata->count++; + spin_unlock(&count_lock); + + /* request and active GPIO */ + si4702_gpio_get(); + /* reset the si4702 from it's reset pin */ + si4702_reset(); + + /* startup si4702 */ + if (si4702_startup()) { + spin_lock(&count_lock); + si4702_drvdata->count--; + spin_unlock(&count_lock); + return -ENODEV; + } + + return 0; +} + +static int release_si4702(struct inode *inode, struct file *file) +{ + struct i2c_client *client; + + if (NULL == si4702_drvdata) + return -1; + + client = si4702_drvdata->client; + + dev_err(&client->dev, "release\n"); + /* software shutdown */ + si4702_shutdown(); + /* inactive, free GPIO, cut power */ + si4702_gpio_put(); + + spin_lock(&count_lock); + si4702_drvdata->count--; + spin_unlock(&count_lock); + + return 0; +} + +static int si4702_suspend(struct i2c_client *client, pm_message_t state) +{ + return 0; +} + +static int si4702_resume(struct i2c_client *client) +{ + return 0; +} + +static struct device_attribute si4702_dev_attr = { + .attr = { + .name = "si4702_ctl", + .mode = S_IRUSR | S_IWUSR, + }, + .show = si4702_show, + .store = si4702_store, +}; + +static struct file_operations si4702_fops = { + .owner = THIS_MODULE, + .open = open_si4702, + .release = release_si4702, + .ioctl = ioctl_si4702, +}; + +static int __devinit si4702_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct mxc_fm_platform_data *plat_data; + struct si4702_drvdata *drv_data; + struct device *dev; + + dev_info(&client->dev, "si4702 device probe process start.\n"); + + plat_data = (struct mxc_fm_platform_data *)client->dev.platform_data; + if (plat_data == NULL) { + dev_err(&client->dev, "lack of platform data!\n"); + return -ENODEV; + } + + drv_data = kmalloc(sizeof(struct si4702_drvdata), GFP_KERNEL); + if (drv_data == NULL) { + dev_err(&client->dev, "lack of kernel memory!\n"); + return -ENOMEM; + } + memset(drv_data, 0, sizeof(struct si4702_drvdata)); + drv_data->plat_data = plat_data; + drv_data->major = DEV_MAJOR; + drv_data->minor = DEV_MINOR; + drv_data->count = 0; + + /*enable power supply */ + if (plat_data->reg_vio != NULL) { + drv_data->vio = regulator_get(&client->dev, plat_data->reg_vio); + if (drv_data->vio == ERR_PTR(-ENOENT)) + goto free_drv_data; + regulator_enable(drv_data->vio); + } + + /* here, we assume that vio and vdd are not the same */ + if (plat_data->reg_vdd != NULL) { + drv_data->vdd = regulator_get(&client->dev, plat_data->reg_vdd); + if (drv_data->vdd == ERR_PTR(-ENOENT)) + goto disable_vio; + regulator_enable(drv_data->vdd); + } + + /*attach client and check device id */ + if (SI4702_DEVICE_ID != si4702_id_detect(client)) { + dev_err(&client->dev, "id wrong.\n"); + goto disable_vdd; + } + dev_info(&client->dev, "chip id %x detect.\n", SI4702_DEVICE_ID); + drv_data->client = client; + + /*user interface begain */ + /*create device file in sysfs as a user interface, + * also for debug support */ + ret = device_create_file(&client->dev, &si4702_dev_attr); + if (ret) { + dev_err(&client->dev, "create device file failed!\n"); + goto gpio_put; /* shall i use some meanful error code? */ + } + + /*create a char dev for application code access */ + if (drv_data->major) { + ret = register_chrdev(drv_data->major, "si4702", &si4702_fops);; + } else { + ret = register_chrdev(0, "si4702", &si4702_fops); + } + + if (drv_data->major == 0) + drv_data->major = ret; + + /* create class and device for udev information */ + drv_data->radio_class = class_create(THIS_MODULE, "radio"); + if (IS_ERR(drv_data->radio_class)) { + dev_err(&client->dev, "SI4702: failed to create radio class\n"); + goto char_dev_remove; + } + + dev = device_create(drv_data->radio_class, NULL, + MKDEV(drv_data->major, drv_data->minor), NULL, + "si4702"); + if (IS_ERR(dev)) { + dev_err(&client->dev, + "SI4702: failed to create radio class device\n"); + goto class_remove; + } + /*User interface end */ + dev_set_drvdata(&client->dev, drv_data); + si4702_drvdata = drv_data; + + si4702_gpio_get(); + dev_info(&client->dev, "si4702 device probe successfully.\n"); + si4702_shutdown(); + + return 0; + +class_remove: + class_destroy(drv_data->radio_class); +char_dev_remove: + unregister_chrdev(drv_data->major, "si4702"); + device_remove_file(&client->dev, &si4702_dev_attr); +gpio_put: + si4702_gpio_put(); +disable_vdd: + if (plat_data->reg_vdd) { + regulator_disable(drv_data->vdd); + regulator_put(drv_data->vdd); + } +disable_vio: + if (plat_data->reg_vio) { + regulator_disable(drv_data->vio); + regulator_put(drv_data->vio); + } + +free_drv_data: + kfree(drv_data); + + return -ENODEV; +} + +static int __devexit si4702_remove(struct i2c_client *client) +{ + struct mxc_fm_platform_data *plat_data; + struct si4702_drvdata *drv_data = dev_get_drvdata(&client->dev); + + plat_data = (struct mxc_fm_platform_data *)client->dev.platform_data; + + device_destroy(drv_data->radio_class, + MKDEV(drv_data->major, drv_data->minor)); + class_destroy(drv_data->radio_class); + + unregister_chrdev(drv_data->major, "si4702"); + device_remove_file(&client->dev, &si4702_dev_attr); + si4702_gpio_put(); + + if (plat_data->reg_vdd) + regulator_put(drv_data->vdd); + + if (plat_data->reg_vio) + regulator_put(drv_data->vio); + + kfree(si4702_drvdata); + si4702_drvdata = NULL; + + return 0; +} + +static const struct i2c_device_id si4702_id[] = { + {"si4702", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, si4702_id); + +static struct i2c_driver i2c_si4702_driver = { + .driver = { + .name = "si4702", + }, + .probe = si4702_probe, + .remove = si4702_remove, + .suspend = si4702_suspend, + .resume = si4702_resume, + .id_table = si4702_id, +}; + +static int __init init_si4702(void) +{ + /*add to i2c driver */ + pr_info("add si4702 i2c driver\n"); + return i2c_add_driver(&i2c_si4702_driver); +} + +static void __exit exit_si4702(void) +{ + i2c_del_driver(&i2c_si4702_driver); +} + +module_init(init_si4702); +module_exit(exit_si4702); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("SI4702 FM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/char/mxs_viim.c b/drivers/char/mxs_viim.c new file mode 100644 index 000000000000..302d967d12e2 --- /dev/null +++ b/drivers/char/mxs_viim.c @@ -0,0 +1,175 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +static unsigned long iim_reg_base0, iim_reg_end0, iim_reg_size0; +static unsigned long iim_reg_base1, iim_reg_end1, iim_reg_size1; +static struct device *iim_dev; + +/*! + * MXS Virtual IIM interface - memory map function + * This function maps one page size VIIM registers from VIIM base address0 + * if the size of the required virtual memory space is less than or equal to + * one page size, otherwise this function will also map one page size VIIM + * registers from VIIM base address1. + * + * @param file struct file * + * @param vma structure vm_area_struct * + * + * @return Return 0 on success or negative error code on error + */ +static int mxs_viim_mmap(struct file *file, struct vm_area_struct *vma) +{ + size_t size = vma->vm_end - vma->vm_start; + + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ + if (remap_pfn_range(vma, + vma->vm_start, + iim_reg_base0 >> PAGE_SHIFT, + iim_reg_size0, + vma->vm_page_prot)) + return -EAGAIN; + + if (size > iim_reg_size0) { + if (remap_pfn_range(vma, + vma->vm_start + iim_reg_size0, + iim_reg_base1 >> PAGE_SHIFT, + iim_reg_size1, + vma->vm_page_prot)) + return -EAGAIN; + } + + return 0; +} + +/*! + * MXS Virtual IIM interface - open function + * + * @param inode struct inode * + * @param filp struct file * + * + * @return Return 0 on success or negative error code on error + */ +static int mxs_viim_open(struct inode *inode, struct file *filp) +{ + return 0; +} + +/*! + * MXS Virtual IIM interface - release function + * + * @param inode struct inode * + * @param filp struct file * + * + * @return Return 0 on success or negative error code on error + */ +static int mxs_viim_release(struct inode *inode, struct file *filp) +{ + return 0; +} + +static const struct file_operations mxs_viim_fops = { + .mmap = mxs_viim_mmap, + .open = mxs_viim_open, + .release = mxs_viim_release, +}; + +static struct miscdevice mxs_viim_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "mxs_viim", + .fops = &mxs_viim_fops, +}; + +/*! + * This function is called by the driver framework to get virtual iim base/end + * address and register iim misc device. + * + * @param dev The device structure for Virtual IIM passed in by the + * driver framework. + * + * @return Returns 0 on success or negative error code on error + */ +static int mxs_viim_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret; + + iim_dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) { + dev_err(iim_dev, "Unable to get Virtual IIM resource 0\n"); + return -ENODEV; + } + + iim_reg_base0 = res->start; + iim_reg_end0 = res->end; + iim_reg_size0 = iim_reg_end0 - iim_reg_base0 + 1; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (IS_ERR(res)) { + dev_err(iim_dev, "Unable to get Virtual IIM resource 1\n"); + return -ENODEV; + } + + iim_reg_base1 = res->start; + iim_reg_end1 = res->end; + iim_reg_size1 = iim_reg_end1 - iim_reg_base1 + 1; + + ret = misc_register(&mxs_viim_miscdev); + if (ret) + return ret; + + return 0; +} + +static int mxs_viim_remove(struct platform_device *pdev) +{ + misc_deregister(&mxs_viim_miscdev); + return 0; +} + +static struct platform_driver mxs_viim_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mxs_viim", + }, + .probe = mxs_viim_probe, + .remove = mxs_viim_remove, +}; + +static int __init mxs_viim_dev_init(void) +{ + return platform_driver_register(&mxs_viim_driver); +} + +static void __exit mxs_viim_dev_cleanup(void) +{ + platform_driver_unregister(&mxs_viim_driver); +} + +module_init(mxs_viim_dev_init); +module_exit(mxs_viim_dev_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXS Virtual IIM driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(MISC_DYNAMIC_MINOR); diff --git a/drivers/char/random.c b/drivers/char/random.c index 8d85587b6d4f..66c28c3a7871 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -702,6 +702,8 @@ void add_interrupt_randomness(int irq) add_timer_randomness(state, 0x100 + irq); } +EXPORT_SYMBOL_GPL(add_interrupt_randomness); + #ifdef CONFIG_BLOCK void add_disk_randomness(struct gendisk *disk) { diff --git a/drivers/char/regs-ocotp-v2.h b/drivers/char/regs-ocotp-v2.h new file mode 100644 index 000000000000..91eaed0a5be9 --- /dev/null +++ b/drivers/char/regs-ocotp-v2.h @@ -0,0 +1,239 @@ +/* + * Freescale OCOTP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.12 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H + + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) + +#define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 6 +#define BM_OCOTP_CTRL_RSRVD0 0x000000C0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000003F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_TIMING (0x00000010) + +#define BP_OCOTP_TIMING_RSRVD0 22 +#define BM_OCOTP_TIMING_RSRVD0 0xFFC00000 +#define BF_OCOTP_TIMING_RSRVD0(v) \ + (((v) << 22) & BM_OCOTP_TIMING_RSRVD0) +#define BP_OCOTP_TIMING_RD_BUSY 16 +#define BM_OCOTP_TIMING_RD_BUSY 0x003F0000 +#define BF_OCOTP_TIMING_RD_BUSY(v) \ + (((v) << 16) & BM_OCOTP_TIMING_RD_BUSY) +#define BP_OCOTP_TIMING_RELAX 12 +#define BM_OCOTP_TIMING_RELAX 0x0000F000 +#define BF_OCOTP_TIMING_RELAX(v) \ + (((v) << 12) & BM_OCOTP_TIMING_RELAX) +#define BP_OCOTP_TIMING_SCLK_COUNT 0 +#define BM_OCOTP_TIMING_SCLK_COUNT 0x00000FFF +#define BF_OCOTP_TIMING_SCLK_COUNT(v) \ + (((v) << 0) & BM_OCOTP_TIMING_SCLK_COUNT) + +#define HW_OCOTP_DATA (0x00000020) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +#define HW_OCOTP_LOCK (0x00000030) + +#define BP_OCOTP_LOCK_UNALLOCATED 26 +#define BM_OCOTP_LOCK_UNALLOCATED 0xFC000000 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 26) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_PIN 0x02000000 +#define BM_OCOTP_LOCK_DCPKEY_ALT 0x01000000 +#define BM_OCOTP_LOCK_SCC_ALT 0x00800000 +#define BM_OCOTP_LOCK_DCPKEY 0x00400000 +#define BM_OCOTP_LOCK_SWCAP_SHADOW 0x00200000 +#define BM_OCOTP_LOCK_SWCAP 0x00100000 +#define BM_OCOTP_LOCK_HWCAP_SHADOW 0x00080000 +#define BM_OCOTP_LOCK_HWCAP 0x00040000 +#define BM_OCOTP_LOCK_MAC_SHADOW 0x00020000 +#define BM_OCOTP_LOCK_MAC 0x00010000 +#define BM_OCOTP_LOCK_SJC_SHADOW 0x00008000 +#define BM_OCOTP_LOCK_SJC 0x00004000 +#define BM_OCOTP_LOCK_SRK_SHADOW 0x00002000 +#define BM_OCOTP_LOCK_SRK 0x00001000 +#define BM_OCOTP_LOCK_SCC_SHADOW 0x00000800 +#define BM_OCOTP_LOCK_SCC 0x00000400 +#define BM_OCOTP_LOCK_GP_SHADOW 0x00000200 +#define BM_OCOTP_LOCK_GP 0x00000100 +#define BM_OCOTP_LOCK_MEM_MISC_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_MEM_TRIM_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_MEM_TRIM 0x00000020 +#define BM_OCOTP_LOCK_CFG_MISC_SHADOW 0x00000010 +#define BM_OCOTP_LOCK_CFG_BOOT_SHADOW 0x00000008 +#define BM_OCOTP_LOCK_CFG_BOOT 0x00000004 +#define BM_OCOTP_LOCK_CFG_TESTER_SHADOW 0x00000002 +#define BM_OCOTP_LOCK_CFG_TESTER 0x00000001 + +/* + * multi-register-define name HW_OCOTP_CFGn + * base 0x00000040 + * count 7 + * offset 0x10 + */ +#define HW_OCOTP_CFGn(n) (0x00000040 + (n) * 0x10) +#define BP_OCOTP_CFGn_BITS 0 +#define BM_OCOTP_CFGn_BITS 0xFFFFFFFF +#define BF_OCOTP_CFGn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_MEMn + * base 0x000000B0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_MEMn(n) (0x000000b0 + (n) * 0x10) +#define BP_OCOTP_MEMn_BITS 0 +#define BM_OCOTP_MEMn_BITS 0xFFFFFFFF +#define BF_OCOTP_MEMn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_GPn + * base 0x00000110 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_GPn(n) (0x00000110 + (n) * 0x10) +#define BP_OCOTP_GPn_BITS 0 +#define BM_OCOTP_GPn_BITS 0xFFFFFFFF +#define BF_OCOTP_GPn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SCCn + * base 0x00000130 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SCCn(n) (0x00000130 + (n) * 0x10) +#define BP_OCOTP_SCCn_BITS 0 +#define BM_OCOTP_SCCn_BITS 0xFFFFFFFF +#define BF_OCOTP_SCCn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SRKn + * base 0x000001B0 + * count 8 + * offset 0x10 + */ +#define HW_OCOTP_SRKn(n) (0x000001b0 + (n) * 0x10) +#define BP_OCOTP_SRKn_BITS 0 +#define BM_OCOTP_SRKn_BITS 0xFFFFFFFF +#define BF_OCOTP_SRKn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_SJC_RESPn + * base 0x00000230 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_SJC_RESPn(n) (0x00000230 + (n) * 0x10) +#define BP_OCOTP_SJC_RESPn_BITS 0 +#define BM_OCOTP_SJC_RESPn_BITS 0xFFFFFFFF +#define BF_OCOTP_SJC_RESPn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_MACn + * base 0x00000250 + * count 2 + * offset 0x10 + */ +#define HW_OCOTP_MACn(n) (0x00000250 + (n) * 0x10) +#define BP_OCOTP_MACn_BITS 0 +#define BM_OCOTP_MACn_BITS 0xFFFFFFFF +#define BF_OCOTP_MACn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x00000270 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x00000270 + (n) * 0x10) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x000002a0) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_SCS (0x000002b0) +#define HW_OCOTP_SCS_SET (0x000002b4) +#define HW_OCOTP_SCS_CLR (0x000002b8) +#define HW_OCOTP_SCS_TOG (0x000002bc) + +#define BM_OCOTP_SCS_LOCK 0x80000000 +#define BP_OCOTP_SCS_SPARE 1 +#define BM_OCOTP_SCS_SPARE 0x7FFFFFFE +#define BF_OCOTP_SCS_SPARE(v) \ + (((v) << 1) & BM_OCOTP_SCS_SPARE) +#define BM_OCOTP_SCS_HAB_JDE 0x00000001 + +#define HW_OCOTP_VERSION (0x000002c0) + +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index fbf94cf496f0..ef4c102408c9 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -243,4 +243,16 @@ config CRYPTO_DEV_OMAP_SHAM OMAP processors have SHA1/MD5 hw accelerator. Select this if you want to use the OMAP module for SHA1/MD5 algorithms. +config CRYPTO_DEV_DCP + tristate "Support for the DCP engine" + depends on ARCH_MX28 || ARCH_MX23 || ARCH_MX50 + select CRYPTO_ALGAPI + select CRYPTO_BLKCIPHER + help + Say 'Y' here to use the DCP AES and SHA + engine for the CryptoAPI algorithms. + + To compile this driver as a module, choose M here: the module + will be called geode-aes. + endif # CRYPTO_HW diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 6dbbe00c4524..c375d1903e9e 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/ obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o +obj-$(CONFIG_CRYPTO_DEV_DCP) += dcp.o diff --git a/drivers/crypto/dcp.c b/drivers/crypto/dcp.c new file mode 100644 index 000000000000..dcd07a8e1173 --- /dev/null +++ b/drivers/crypto/dcp.c @@ -0,0 +1,1775 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* + * Based on geode-aes.c + * Copyright (C) 2004-2006, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "dcp.h" +#include "dcp_bootstream_ioctl.h" + +/* Following data only used by DCP bootstream interface */ +struct dcpboot_dma_area { + struct dcp_hw_packet hw_packet; + uint16_t block[16]; +}; + +struct dcp { + struct device *dev; + spinlock_t lock; + struct mutex op_mutex[DCP_NUM_CHANNELS]; + struct completion op_wait[DCP_NUM_CHANNELS]; + int wait[DCP_NUM_CHANNELS]; + int dcp_vmi_irq; + int dcp_irq; + u32 dcp_regs_base; + ulong clock_state; + bool chan_in_use[DCP_NUM_CHANNELS]; + + /* Following buffers used in hashing to meet 64-byte len alignment */ + char *buf1; + char *buf2; + dma_addr_t buf1_phys; + dma_addr_t buf2_phys; + struct dcp_hash_coherent_block *buf1_desc; + struct dcp_hash_coherent_block *buf2_desc; + struct dcp_hash_coherent_block *user_buf_desc; + + /* Following data only used by DCP bootstream interface */ + struct dcpboot_dma_area *dcpboot_dma_area; + dma_addr_t dcpboot_dma_area_phys; +}; + +/* cipher flags */ +#define DCP_ENC 0x0001 +#define DCP_DEC 0x0002 +#define DCP_ECB 0x0004 +#define DCP_CBC 0x0008 +#define DCP_CBC_INIT 0x0010 +#define DCP_OTPKEY 0x0020 + +/* hash flags */ +#define DCP_INIT 0x0001 +#define DCP_UPDATE 0x0002 +#define DCP_FINAL 0x0004 + +#define DCP_AES 0x1000 +#define DCP_SHA1 0x2000 +#define DCP_CRC32 0x3000 +#define DCP_COPY 0x4000 +#define DCP_FILL 0x5000 +#define DCP_MODE_MASK 0xf000 + +/* clock defines */ +#define CLOCK_ON 1 +#define CLOCK_OFF 0 + +struct dcp_op { + + unsigned int flags; + + void *src; + dma_addr_t src_phys; + + void *dst; + dma_addr_t dst_phys; + + int len; + + /* the key contains the IV for block modes */ + union { + struct { + u8 key[2 * AES_KEYSIZE_128] + __attribute__ ((__aligned__(32))); + dma_addr_t key_phys; + int keylen; + } cipher; + struct { + u8 digest[SHA256_DIGEST_SIZE] + __attribute__ ((__aligned__(32))); + dma_addr_t digest_phys; + int digestlen; + int init; + } hash; + }; + + union { + struct crypto_blkcipher *blk; + struct crypto_cipher *cip; + struct crypto_hash *hash; + } fallback; + + struct dcp_hw_packet pkt + __attribute__ ((__aligned__(32))); +}; + +struct dcp_hash_coherent_block { + struct dcp_hw_packet pkt[1] + __attribute__ ((__aligned__(32))); + u8 digest[SHA256_DIGEST_SIZE] + __attribute__ ((__aligned__(32))); + unsigned int len; + dma_addr_t src_phys; + void *src; + void *dst; + dma_addr_t my_phys; + u32 hash_sel; + struct dcp_hash_coherent_block *next; +}; + +struct dcp_hash_op { + + unsigned int flags; + + /* the key contains the IV for block modes */ + union { + struct { + u8 key[2 * AES_KEYSIZE_128] + __attribute__ ((__aligned__(32))); + dma_addr_t key_phys; + int keylen; + } cipher; + struct { + u8 digest[SHA256_DIGEST_SIZE] + __attribute__ ((__aligned__(32))); + dma_addr_t digest_phys; + int digestlen; + int init; + } hash; + }; + + u32 length; + struct dcp_hash_coherent_block *head_desc; + struct dcp_hash_coherent_block *tail_desc; +}; + +/* only one */ +static struct dcp *global_sdcp; + +static void dcp_clock(struct dcp *sdcp, ulong state, bool force) +{ + u32 chan; + struct clk *clk = clk_get(sdcp->dev, "dcp_clk"); + + /* unless force is true (used during suspend/resume), if any + * channel is running, then clk is already on, and must stay on */ + if (!force) + for (chan = 0; chan < DCP_NUM_CHANNELS; chan++) + if (sdcp->chan_in_use[chan]) + goto exit; + + if (state == CLOCK_OFF) { + /* gate at clock source */ + if (!IS_ERR(clk)) + clk_disable(clk); + /* gate at DCP */ + else + __raw_writel(BM_DCP_CTRL_CLKGATE, + sdcp->dcp_regs_base + HW_DCP_CTRL_SET); + + sdcp->clock_state = CLOCK_OFF; + + } else { + /* ungate at clock source */ + if (!IS_ERR(clk)) + clk_enable(clk); + /* ungate at DCP */ + else + __raw_writel(BM_DCP_CTRL_CLKGATE, + sdcp->dcp_regs_base + HW_DCP_CTRL_CLR); + + sdcp->clock_state = CLOCK_ON; + } + +exit: + return; +} + +static void dcp_perform_op(struct dcp_op *op) +{ + struct dcp *sdcp = global_sdcp; + struct mutex *mutex; + struct dcp_hw_packet *pkt; + int chan; + u32 pkt1, pkt2; + unsigned long timeout; + dma_addr_t pkt_phys; + u32 stat; + + pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE | BM_DCP_PACKET1_INTERRUPT; + + switch (op->flags & DCP_MODE_MASK) { + + case DCP_AES: + + chan = CIPHER_CHAN; + + /* key is at the payload */ + pkt1 |= BM_DCP_PACKET1_ENABLE_CIPHER; + if ((op->flags & DCP_OTPKEY) == 0) + pkt1 |= BM_DCP_PACKET1_PAYLOAD_KEY; + if (op->flags & DCP_ENC) + pkt1 |= BM_DCP_PACKET1_CIPHER_ENCRYPT; + if (op->flags & DCP_CBC_INIT) + pkt1 |= BM_DCP_PACKET1_CIPHER_INIT; + + pkt2 = BF(0, DCP_PACKET2_CIPHER_CFG) | + BF(0, DCP_PACKET2_KEY_SELECT) | + BF(BV_DCP_PACKET2_CIPHER_SELECT__AES128, + DCP_PACKET2_CIPHER_SELECT); + + if (op->flags & DCP_ECB) + pkt2 |= BF(BV_DCP_PACKET2_CIPHER_MODE__ECB, + DCP_PACKET2_CIPHER_MODE); + else if (op->flags & DCP_CBC) + pkt2 |= BF(BV_DCP_PACKET2_CIPHER_MODE__CBC, + DCP_PACKET2_CIPHER_MODE); + + break; + + case DCP_SHA1: + + chan = HASH_CHAN; + + pkt1 |= BM_DCP_PACKET1_ENABLE_HASH; + if (op->flags & DCP_INIT) + pkt1 |= BM_DCP_PACKET1_HASH_INIT; + if (op->flags & DCP_FINAL) { + pkt1 |= BM_DCP_PACKET1_HASH_TERM; + BUG_ON(op->hash.digest == NULL); + } + + pkt2 = BF(BV_DCP_PACKET2_HASH_SELECT__SHA1, + DCP_PACKET2_HASH_SELECT); + break; + + default: + dev_err(sdcp->dev, "Unsupported mode\n"); + return; + } + + mutex = &sdcp->op_mutex[chan]; + pkt = &op->pkt; + + pkt->pNext = 0; + pkt->pkt1 = pkt1; + pkt->pkt2 = pkt2; + pkt->pSrc = (u32)op->src_phys; + pkt->pDst = (u32)op->dst_phys; + pkt->size = op->len; + pkt->pPayload = chan == CIPHER_CHAN ? + (u32)op->cipher.key_phys : (u32)op->hash.digest_phys; + pkt->stat = 0; + + pkt_phys = dma_map_single(sdcp->dev, pkt, sizeof(*pkt), + DMA_BIDIRECTIONAL); + if (dma_mapping_error(sdcp->dev, pkt_phys)) { + dev_err(sdcp->dev, "Unable to map packet descriptor\n"); + return; + } + + /* submit the work */ + mutex_lock(mutex); + dcp_clock(sdcp, CLOCK_ON, false); + sdcp->chan_in_use[chan] = true; + + __raw_writel(-1, sdcp->dcp_regs_base + HW_DCP_CHnSTAT_CLR(chan)); + + /* Load the work packet pointer and bump the channel semaphore */ + __raw_writel((u32)pkt_phys, sdcp->dcp_regs_base + + HW_DCP_CHnCMDPTR(chan)); + + /* XXX wake from interrupt instead of looping */ + timeout = jiffies + msecs_to_jiffies(1000); + + sdcp->wait[chan] = 0; + __raw_writel(BF(1, DCP_CHnSEMA_INCREMENT), sdcp->dcp_regs_base + + HW_DCP_CHnSEMA(chan)); + while (time_before(jiffies, timeout) && sdcp->wait[chan] == 0) + cpu_relax(); + + if (!time_before(jiffies, timeout)) { + dev_err(sdcp->dev, "Timeout while waiting STAT 0x%08x\n", + __raw_readl(sdcp->dcp_regs_base + HW_DCP_STAT)); + goto out; + } + + stat = __raw_readl(sdcp->dcp_regs_base + HW_DCP_CHnSTAT(chan)); + if ((stat & 0xff) != 0) + dev_err(sdcp->dev, "Channel stat error 0x%02x\n", + __raw_readl(sdcp->dcp_regs_base + + HW_DCP_CHnSTAT(chan)) & 0xff); +out: + sdcp->chan_in_use[chan] = false; + dcp_clock(sdcp, CLOCK_OFF, false); + mutex_unlock(mutex); + dma_unmap_single(sdcp->dev, pkt_phys, sizeof(*pkt), DMA_TO_DEVICE); +} + +static int dcp_aes_setkey_cip(struct crypto_tfm *tfm, const u8 *key, + unsigned int len) +{ + struct dcp_op *op = crypto_tfm_ctx(tfm); + unsigned int ret; + + op->cipher.keylen = len; + + if (len == AES_KEYSIZE_128) { + memcpy(op->cipher.key, key, len); + return 0; + } + + if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) { + /* not supported at all */ + tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + return -EINVAL; + } + + /* + * The requested key size is not supported by HW, do a fallback + */ + op->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; + op->fallback.blk->base.crt_flags |= (tfm->crt_flags & + CRYPTO_TFM_REQ_MASK); + + ret = crypto_cipher_setkey(op->fallback.cip, key, len); + if (ret) { + tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK; + tfm->crt_flags |= (op->fallback.blk->base.crt_flags & + CRYPTO_TFM_RES_MASK); + } + return ret; +} + +static void dcp_aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) +{ + struct dcp *sdcp = global_sdcp; + struct dcp_op *op = crypto_tfm_ctx(tfm); + + if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) { + crypto_cipher_encrypt_one(op->fallback.cip, out, in); + return; + } + + op->src = (void *) in; + op->dst = (void *) out; + op->flags = DCP_AES | DCP_ENC | DCP_ECB; + op->len = AES_KEYSIZE_128; + + /* map the data */ + op->src_phys = dma_map_single(sdcp->dev, (void *)in, AES_KEYSIZE_128, + DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->src_phys)) { + dev_err(sdcp->dev, "Unable to map source\n"); + return; + } + + op->dst_phys = dma_map_single(sdcp->dev, out, AES_KEYSIZE_128, + DMA_FROM_DEVICE); + if (dma_mapping_error(sdcp->dev, op->dst_phys)) { + dev_err(sdcp->dev, "Unable to map dest\n"); + goto err_unmap_src; + } + + op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key, + AES_KEYSIZE_128, DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) { + dev_err(sdcp->dev, "Unable to map key\n"); + goto err_unmap_dst; + } + + /* perform the operation */ + dcp_perform_op(op); + + dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128, + DMA_TO_DEVICE); +err_unmap_dst: + dma_unmap_single(sdcp->dev, op->dst_phys, op->len, DMA_FROM_DEVICE); +err_unmap_src: + dma_unmap_single(sdcp->dev, op->src_phys, op->len, DMA_TO_DEVICE); +} + +static void dcp_aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) +{ + struct dcp *sdcp = global_sdcp; + struct dcp_op *op = crypto_tfm_ctx(tfm); + + if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) { + crypto_cipher_decrypt_one(op->fallback.cip, out, in); + return; + } + + op->src = (void *) in; + op->dst = (void *) out; + op->flags = DCP_AES | DCP_DEC | DCP_ECB; + op->len = AES_KEYSIZE_128; + + /* map the data */ + op->src_phys = dma_map_single(sdcp->dev, (void *)in, AES_KEYSIZE_128, + DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->src_phys)) { + dev_err(sdcp->dev, "Unable to map source\n"); + return; + } + + op->dst_phys = dma_map_single(sdcp->dev, out, AES_KEYSIZE_128, + DMA_FROM_DEVICE); + if (dma_mapping_error(sdcp->dev, op->dst_phys)) { + dev_err(sdcp->dev, "Unable to map dest\n"); + goto err_unmap_src; + } + + op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key, + AES_KEYSIZE_128, DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) { + dev_err(sdcp->dev, "Unable to map key\n"); + goto err_unmap_dst; + } + + /* perform the operation */ + dcp_perform_op(op); + + dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128, + DMA_TO_DEVICE); +err_unmap_dst: + dma_unmap_single(sdcp->dev, op->dst_phys, op->len, DMA_FROM_DEVICE); +err_unmap_src: + dma_unmap_single(sdcp->dev, op->src_phys, op->len, DMA_TO_DEVICE); +} + +static int fallback_init_cip(struct crypto_tfm *tfm) +{ + const char *name = tfm->__crt_alg->cra_name; + struct dcp_op *op = crypto_tfm_ctx(tfm); + + op->fallback.cip = crypto_alloc_cipher(name, 0, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); + + if (IS_ERR(op->fallback.cip)) { + printk(KERN_ERR "Error allocating fallback algo %s\n", name); + return PTR_ERR(op->fallback.cip); + } + + return 0; +} + +static void fallback_exit_cip(struct crypto_tfm *tfm) +{ + struct dcp_op *op = crypto_tfm_ctx(tfm); + + crypto_free_cipher(op->fallback.cip); + op->fallback.cip = NULL; +} + +static struct crypto_alg dcp_aes_alg = { + .cra_name = "aes", + .cra_driver_name = "dcp-aes", + .cra_priority = 300, + .cra_alignmask = 15, + .cra_flags = CRYPTO_ALG_TYPE_CIPHER | + CRYPTO_ALG_NEED_FALLBACK, + .cra_init = fallback_init_cip, + .cra_exit = fallback_exit_cip, + .cra_blocksize = AES_KEYSIZE_128, + .cra_ctxsize = sizeof(struct dcp_op), + .cra_module = THIS_MODULE, + .cra_list = LIST_HEAD_INIT(dcp_aes_alg.cra_list), + .cra_u = { + .cipher = { + .cia_min_keysize = AES_MIN_KEY_SIZE, + .cia_max_keysize = AES_MAX_KEY_SIZE, + .cia_setkey = dcp_aes_setkey_cip, + .cia_encrypt = dcp_aes_encrypt, + .cia_decrypt = dcp_aes_decrypt + } + } +}; + +static int dcp_aes_setkey_blk(struct crypto_tfm *tfm, const u8 *key, + unsigned int len) +{ + struct dcp_op *op = crypto_tfm_ctx(tfm); + unsigned int ret; + + op->cipher.keylen = len; + + if (len == AES_KEYSIZE_128) { + memcpy(op->cipher.key, key, len); + return 0; + } + + if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) { + /* not supported at all */ + tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; + return -EINVAL; + } + + /* + * The requested key size is not supported by HW, do a fallback + */ + op->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; + op->fallback.blk->base.crt_flags |= (tfm->crt_flags & + CRYPTO_TFM_REQ_MASK); + + ret = crypto_blkcipher_setkey(op->fallback.blk, key, len); + if (ret) { + tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK; + tfm->crt_flags |= (op->fallback.blk->base.crt_flags & + CRYPTO_TFM_RES_MASK); + } + return ret; +} + +static int fallback_blk_dec(struct blkcipher_desc *desc, + struct scatterlist *dst, struct scatterlist *src, + unsigned int nbytes) +{ + unsigned int ret; + struct crypto_blkcipher *tfm; + struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm); + + tfm = desc->tfm; + desc->tfm = op->fallback.blk; + + ret = crypto_blkcipher_decrypt_iv(desc, dst, src, nbytes); + + desc->tfm = tfm; + return ret; +} + +static int fallback_blk_enc(struct blkcipher_desc *desc, + struct scatterlist *dst, struct scatterlist *src, + unsigned int nbytes) +{ + unsigned int ret; + struct crypto_blkcipher *tfm; + struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm); + + tfm = desc->tfm; + desc->tfm = op->fallback.blk; + + ret = crypto_blkcipher_encrypt_iv(desc, dst, src, nbytes); + + desc->tfm = tfm; + return ret; +} + +static int fallback_init_blk(struct crypto_tfm *tfm) +{ + const char *name = tfm->__crt_alg->cra_name; + struct dcp_op *op = crypto_tfm_ctx(tfm); + + op->fallback.blk = crypto_alloc_blkcipher(name, 0, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); + + if (IS_ERR(op->fallback.blk)) { + printk(KERN_ERR "Error allocating fallback algo %s\n", name); + return PTR_ERR(op->fallback.blk); + } + + return 0; +} + +static void fallback_exit_blk(struct crypto_tfm *tfm) +{ + struct dcp_op *op = crypto_tfm_ctx(tfm); + + crypto_free_blkcipher(op->fallback.blk); + op->fallback.blk = NULL; +} + +static int +dcp_aes_ecb_decrypt(struct blkcipher_desc *desc, + struct scatterlist *dst, struct scatterlist *src, + unsigned int nbytes) +{ + struct dcp *sdcp = global_sdcp; + struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm); + struct blkcipher_walk walk; + int err; + + if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) + return fallback_blk_dec(desc, dst, src, nbytes); + + blkcipher_walk_init(&walk, dst, src, nbytes); + + /* key needs to be mapped only once */ + op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key, + AES_KEYSIZE_128, DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) { + dev_err(sdcp->dev, "Unable to map key\n"); + return -ENOMEM; + } + + err = blkcipher_walk_virt(desc, &walk); + while (err == 0 && (nbytes = walk.nbytes) > 0) { + op->src = walk.src.virt.addr, + op->dst = walk.dst.virt.addr; + op->flags = DCP_AES | DCP_DEC | + DCP_ECB; + op->len = nbytes - (nbytes % AES_KEYSIZE_128); + + /* map the data */ + op->src_phys = dma_map_single(sdcp->dev, op->src, op->len, + DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->src_phys)) { + dev_err(sdcp->dev, "Unable to map source\n"); + err = -ENOMEM; + break; + } + + op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len, + DMA_FROM_DEVICE); + if (dma_mapping_error(sdcp->dev, op->dst_phys)) { + dma_unmap_single(sdcp->dev, op->src_phys, op->len, + DMA_TO_DEVICE); + dev_err(sdcp->dev, "Unable to map dest\n"); + err = -ENOMEM; + break; + } + + /* perform! */ + dcp_perform_op(op); + + dma_unmap_single(sdcp->dev, op->dst_phys, op->len, + DMA_FROM_DEVICE); + dma_unmap_single(sdcp->dev, op->src_phys, op->len, + DMA_TO_DEVICE); + + nbytes -= op->len; + err = blkcipher_walk_done(desc, &walk, nbytes); + } + + dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128, + DMA_TO_DEVICE); + + return err; +} + +static int +dcp_aes_ecb_encrypt(struct blkcipher_desc *desc, + struct scatterlist *dst, struct scatterlist *src, + unsigned int nbytes) +{ + struct dcp *sdcp = global_sdcp; + struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm); + struct blkcipher_walk walk; + int err, ret; + + if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) + return fallback_blk_enc(desc, dst, src, nbytes); + + blkcipher_walk_init(&walk, dst, src, nbytes); + + /* key needs to be mapped only once */ + op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key, + AES_KEYSIZE_128, DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) { + dev_err(sdcp->dev, "Unable to map key\n"); + return -ENOMEM; + } + + err = blkcipher_walk_virt(desc, &walk); + + err = 0; + while (err == 0 && (nbytes = walk.nbytes) > 0) { + op->src = walk.src.virt.addr, + op->dst = walk.dst.virt.addr; + op->flags = DCP_AES | DCP_ENC | + DCP_ECB; + op->len = nbytes - (nbytes % AES_KEYSIZE_128); + + /* map the data */ + op->src_phys = dma_map_single(sdcp->dev, op->src, op->len, + DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->src_phys)) { + dev_err(sdcp->dev, "Unable to map source\n"); + err = -ENOMEM; + break; + } + + op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len, + DMA_FROM_DEVICE); + if (dma_mapping_error(sdcp->dev, op->dst_phys)) { + dma_unmap_single(sdcp->dev, op->src_phys, op->len, + DMA_TO_DEVICE); + dev_err(sdcp->dev, "Unable to map dest\n"); + err = -ENOMEM; + break; + } + + /* perform! */ + dcp_perform_op(op); + + dma_unmap_single(sdcp->dev, op->dst_phys, op->len, + DMA_FROM_DEVICE); + dma_unmap_single(sdcp->dev, op->src_phys, op->len, + DMA_TO_DEVICE); + + nbytes -= op->len; + ret = blkcipher_walk_done(desc, &walk, nbytes); + } + + dma_unmap_single(sdcp->dev, op->cipher.key_phys, AES_KEYSIZE_128, + DMA_TO_DEVICE); + + return err; +} + + +static struct crypto_alg dcp_aes_ecb_alg = { + .cra_name = "ecb(aes)", + .cra_driver_name = "dcp-ecb-aes", + .cra_priority = 400, + .cra_alignmask = 15, + .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | + CRYPTO_ALG_NEED_FALLBACK, + .cra_init = fallback_init_blk, + .cra_exit = fallback_exit_blk, + .cra_blocksize = AES_KEYSIZE_128, + .cra_ctxsize = sizeof(struct dcp_op), + .cra_type = &crypto_blkcipher_type, + .cra_module = THIS_MODULE, + .cra_list = LIST_HEAD_INIT(dcp_aes_ecb_alg.cra_list), + .cra_u = { + .blkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = dcp_aes_setkey_blk, + .encrypt = dcp_aes_ecb_encrypt, + .decrypt = dcp_aes_ecb_decrypt + } + } +}; + +static int +dcp_aes_cbc_decrypt(struct blkcipher_desc *desc, + struct scatterlist *dst, struct scatterlist *src, + unsigned int nbytes) +{ + struct dcp *sdcp = global_sdcp; + struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm); + struct blkcipher_walk walk; + int err, blockno; + + if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) + return fallback_blk_dec(desc, dst, src, nbytes); + + blkcipher_walk_init(&walk, dst, src, nbytes); + + blockno = 0; + err = blkcipher_walk_virt(desc, &walk); + while (err == 0 && (nbytes = walk.nbytes) > 0) { + op->src = walk.src.virt.addr, + op->dst = walk.dst.virt.addr; + op->flags = DCP_AES | DCP_DEC | + DCP_CBC; + if (blockno == 0) { + op->flags |= DCP_CBC_INIT; + memcpy(op->cipher.key + AES_KEYSIZE_128, walk.iv, + AES_KEYSIZE_128); + } + op->len = nbytes - (nbytes % AES_KEYSIZE_128); + + /* key (+iv) needs to be mapped only once */ + op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key, + AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL); + if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) { + dev_err(sdcp->dev, "Unable to map key\n"); + err = -ENOMEM; + break; + } + + /* map the data */ + op->src_phys = dma_map_single(sdcp->dev, op->src, op->len, + DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->src_phys)) { + dma_unmap_single(sdcp->dev, op->cipher.key_phys, + AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL); + dev_err(sdcp->dev, "Unable to map source\n"); + err = -ENOMEM; + break; + } + + op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len, + DMA_FROM_DEVICE); + if (dma_mapping_error(sdcp->dev, op->dst_phys)) { + dma_unmap_single(sdcp->dev, op->cipher.key_phys, + AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL); + dma_unmap_single(sdcp->dev, op->src_phys, op->len, + DMA_TO_DEVICE); + dev_err(sdcp->dev, "Unable to map dest\n"); + err = -ENOMEM; + break; + } + + /* perform! */ + dcp_perform_op(op); + + dma_unmap_single(sdcp->dev, op->cipher.key_phys, + AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL); + dma_unmap_single(sdcp->dev, op->dst_phys, op->len, + DMA_FROM_DEVICE); + dma_unmap_single(sdcp->dev, op->src_phys, op->len, + DMA_TO_DEVICE); + + nbytes -= op->len; + err = blkcipher_walk_done(desc, &walk, nbytes); + + blockno++; + } + + return err; +} + +static int +dcp_aes_cbc_encrypt(struct blkcipher_desc *desc, + struct scatterlist *dst, struct scatterlist *src, + unsigned int nbytes) +{ + struct dcp *sdcp = global_sdcp; + struct dcp_op *op = crypto_blkcipher_ctx(desc->tfm); + struct blkcipher_walk walk; + int err, ret, blockno; + + if (unlikely(op->cipher.keylen != AES_KEYSIZE_128)) + return fallback_blk_enc(desc, dst, src, nbytes); + + blkcipher_walk_init(&walk, dst, src, nbytes); + + blockno = 0; + + err = blkcipher_walk_virt(desc, &walk); + while (err == 0 && (nbytes = walk.nbytes) > 0) { + op->src = walk.src.virt.addr, + op->dst = walk.dst.virt.addr; + op->flags = DCP_AES | DCP_ENC | + DCP_CBC; + if (blockno == 0) { + op->flags |= DCP_CBC_INIT; + memcpy(op->cipher.key + AES_KEYSIZE_128, walk.iv, + AES_KEYSIZE_128); + } + op->len = nbytes - (nbytes % AES_KEYSIZE_128); + + /* key needs to be mapped only once */ + op->cipher.key_phys = dma_map_single(sdcp->dev, op->cipher.key, + AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL); + if (dma_mapping_error(sdcp->dev, op->cipher.key_phys)) { + dev_err(sdcp->dev, "Unable to map key\n"); + return -ENOMEM; + } + + /* map the data */ + op->src_phys = dma_map_single(sdcp->dev, op->src, op->len, + DMA_TO_DEVICE); + if (dma_mapping_error(sdcp->dev, op->src_phys)) { + dma_unmap_single(sdcp->dev, op->cipher.key_phys, + AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL); + dev_err(sdcp->dev, "Unable to map source\n"); + err = -ENOMEM; + break; + } + + op->dst_phys = dma_map_single(sdcp->dev, op->dst, op->len, + DMA_FROM_DEVICE); + if (dma_mapping_error(sdcp->dev, op->dst_phys)) { + dma_unmap_single(sdcp->dev, op->cipher.key_phys, + AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL); + dma_unmap_single(sdcp->dev, op->src_phys, op->len, + DMA_TO_DEVICE); + dev_err(sdcp->dev, "Unable to map dest\n"); + err = -ENOMEM; + break; + } + + /* perform! */ + dcp_perform_op(op); + + dma_unmap_single(sdcp->dev, op->cipher.key_phys, + AES_KEYSIZE_128 * 2, DMA_BIDIRECTIONAL); + dma_unmap_single(sdcp->dev, op->dst_phys, op->len, + DMA_FROM_DEVICE); + dma_unmap_single(sdcp->dev, op->src_phys, op->len, + DMA_TO_DEVICE); + + nbytes -= op->len; + ret = blkcipher_walk_done(desc, &walk, nbytes); + + blockno++; + } + + return err; +} + +static struct crypto_alg dcp_aes_cbc_alg = { + .cra_name = "cbc(aes)", + .cra_driver_name = "dcp-cbc-aes", + .cra_priority = 400, + .cra_alignmask = 15, + .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | + CRYPTO_ALG_NEED_FALLBACK, + .cra_init = fallback_init_blk, + .cra_exit = fallback_exit_blk, + .cra_blocksize = AES_KEYSIZE_128, + .cra_ctxsize = sizeof(struct dcp_op), + .cra_type = &crypto_blkcipher_type, + .cra_module = THIS_MODULE, + .cra_list = LIST_HEAD_INIT(dcp_aes_cbc_alg.cra_list), + .cra_u = { + .blkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = dcp_aes_setkey_blk, + .encrypt = dcp_aes_cbc_encrypt, + .decrypt = dcp_aes_cbc_decrypt, + .ivsize = AES_KEYSIZE_128, + } + } +}; + +static int dcp_perform_hash_op( + struct dcp_hash_coherent_block *input, + u32 num_desc, bool init, bool terminate) +{ + struct dcp *sdcp = global_sdcp; + int chan; + struct dcp_hw_packet *pkt; + struct dcp_hash_coherent_block *hw; + unsigned long timeout; + u32 stat; + int descno, mapped; + + chan = HASH_CHAN; + + hw = input; + pkt = hw->pkt; + + for (descno = 0; descno < num_desc; descno++) { + + if (descno != 0) { + + /* set next ptr and CHAIN bit in last packet */ + pkt->pNext = hw->next->my_phys + offsetof( + struct dcp_hash_coherent_block, + pkt[0]); + pkt->pkt1 |= BM_DCP_PACKET1_CHAIN; + + /* iterate to next descriptor */ + hw = hw->next; + pkt = hw->pkt; + } + + pkt->pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE | + BM_DCP_PACKET1_ENABLE_HASH; + + if (init && descno == 0) + pkt->pkt1 |= BM_DCP_PACKET1_HASH_INIT; + + pkt->pkt2 = BF(hw->hash_sel, + DCP_PACKET2_HASH_SELECT); + + /* no need to flush buf1 or buf2, which are uncached */ + if (hw->src != sdcp->buf1 && hw->src != sdcp->buf2) { + + /* we have to flush the cache for the buffer */ + hw->src_phys = dma_map_single(sdcp->dev, + hw->src, hw->len, DMA_TO_DEVICE); + + if (dma_mapping_error(sdcp->dev, hw->src_phys)) { + dev_err(sdcp->dev, "Unable to map source\n"); + + /* unmap any previous mapped buffers */ + for (mapped = 0, hw = input; mapped < descno; + mapped++) { + + if (mapped != 0) + hw = hw->next; + if (hw->src != sdcp->buf1 && + hw->src != sdcp->buf2) + dma_unmap_single(sdcp->dev, + hw->src_phys, hw->len, + DMA_TO_DEVICE); + } + + return -EFAULT; + } + } + + pkt->pSrc = (u32)hw->src_phys; + pkt->pDst = 0; + pkt->size = hw->len; + pkt->pPayload = 0; + pkt->stat = 0; + + /* set HASH_TERM bit on last buf if terminate was set */ + if (terminate && (descno == (num_desc - 1))) { + pkt->pkt1 |= BM_DCP_PACKET1_HASH_TERM; + + memset(input->digest, 0, sizeof(input->digest)); + + /* set payload ptr to the 1st buffer's digest */ + pkt->pPayload = (u32)input->my_phys + + offsetof( + struct dcp_hash_coherent_block, + digest); + } + } + + /* submit the work */ + + __raw_writel(-1, sdcp->dcp_regs_base + HW_DCP_CHnSTAT_CLR(chan)); + + mb(); + /* Load the 1st descriptor's physical address */ + __raw_writel((u32)input->my_phys + + offsetof(struct dcp_hash_coherent_block, + pkt[0]), sdcp->dcp_regs_base + HW_DCP_CHnCMDPTR(chan)); + + /* XXX wake from interrupt instead of looping */ + timeout = jiffies + msecs_to_jiffies(1000); + + /* write num_desc into sema register */ + __raw_writel(BF(num_desc, DCP_CHnSEMA_INCREMENT), + sdcp->dcp_regs_base + HW_DCP_CHnSEMA(chan)); + + while (time_before(jiffies, timeout) && + ((__raw_readl(sdcp->dcp_regs_base + + HW_DCP_CHnSEMA(chan)) >> 16) & 0xff) != 0) { + + cpu_relax(); + } + + if (!time_before(jiffies, timeout)) { + dev_err(sdcp->dev, + "Timeout while waiting STAT 0x%08x\n", + __raw_readl(sdcp->dcp_regs_base + HW_DCP_STAT)); + } + + stat = __raw_readl(sdcp->dcp_regs_base + HW_DCP_CHnSTAT(chan)); + if ((stat & 0xff) != 0) + dev_err(sdcp->dev, "Channel stat error 0x%02x\n", + __raw_readl(sdcp->dcp_regs_base + + HW_DCP_CHnSTAT(chan)) & 0xff); + + /* unmap all src buffers */ + for (descno = 0, hw = input; descno < num_desc; descno++) { + if (descno != 0) + hw = hw->next; + if (hw->src != sdcp->buf1 && hw->src != sdcp->buf2) + dma_unmap_single(sdcp->dev, hw->src_phys, hw->len, + DMA_TO_DEVICE); + } + + return 0; + +} + +static int dcp_sha_init(struct shash_desc *desc) +{ + struct dcp *sdcp = global_sdcp; + struct dcp_hash_op *op = shash_desc_ctx(desc); + struct mutex *mutex = &sdcp->op_mutex[HASH_CHAN]; + + mutex_lock(mutex); + dcp_clock(sdcp, CLOCK_ON, false); + sdcp->chan_in_use[HASH_CHAN] = true; + + op->length = 0; + + /* reset the lengths and the pointers of buffer descriptors */ + sdcp->buf1_desc->len = 0; + sdcp->buf1_desc->src = sdcp->buf1; + sdcp->buf2_desc->len = 0; + sdcp->buf2_desc->src = sdcp->buf2; + op->head_desc = sdcp->buf1_desc; + op->tail_desc = sdcp->buf2_desc; + + return 0; +} + +static int dcp_sha_update(struct shash_desc *desc, const u8 *data, + unsigned int length) +{ + struct dcp *sdcp = global_sdcp; + struct dcp_hash_op *op = shash_desc_ctx(desc); + struct dcp_hash_coherent_block *temp; + u32 rem_bytes, bytes_borrowed, hash_sel; + int ret = 0; + + if (strcmp(desc->tfm->base.__crt_alg->cra_name, "sha1") == 0) + hash_sel = BV_DCP_PACKET2_HASH_SELECT__SHA1; + else + hash_sel = BV_DCP_PACKET2_HASH_SELECT__SHA256; + + sdcp->user_buf_desc->src = (void *)data; + sdcp->user_buf_desc->len = length; + + op->tail_desc->len = 0; + + /* check if any pending data from previous updates */ + if (op->head_desc->len) { + + /* borrow from this buffer to make it 64 bytes */ + bytes_borrowed = min(64 - op->head_desc->len, + sdcp->user_buf_desc->len); + + /* copy n bytes to head */ + memcpy(op->head_desc->src + op->head_desc->len, + sdcp->user_buf_desc->src, bytes_borrowed); + op->head_desc->len += bytes_borrowed; + + /* update current buffer's src and len */ + sdcp->user_buf_desc->src += bytes_borrowed; + sdcp->user_buf_desc->len -= bytes_borrowed; + } + + /* Is current buffer unaligned to 64 byte length? + * Each buffer's length must be a multiple of 64 bytes for DCP + */ + rem_bytes = sdcp->user_buf_desc->len % 64; + + /* if length is unaligned, copy remainder to tail */ + if (rem_bytes) { + + memcpy(op->tail_desc->src, (sdcp->user_buf_desc->src + + sdcp->user_buf_desc->len - rem_bytes), + rem_bytes); + + /* update length of current buffer */ + sdcp->user_buf_desc->len -= rem_bytes; + + op->tail_desc->len = rem_bytes; + } + + /* do not send to DCP if length is < 64 */ + if ((op->head_desc->len + sdcp->user_buf_desc->len) >= 64) { + + /* set hash alg to be used (SHA1 or SHA256) */ + op->head_desc->hash_sel = hash_sel; + sdcp->user_buf_desc->hash_sel = hash_sel; + + if (op->head_desc->len) { + op->head_desc->next = sdcp->user_buf_desc; + + ret = dcp_perform_hash_op(op->head_desc, + sdcp->user_buf_desc->len ? 2 : 1, + op->length == 0, false); + } else { + ret = dcp_perform_hash_op(sdcp->user_buf_desc, 1, + op->length == 0, false); + } + + op->length += op->head_desc->len + sdcp->user_buf_desc->len; + op->head_desc->len = 0; + } + + /* if tail has bytes, make it the head for next time */ + if (op->tail_desc->len) { + temp = op->head_desc; + op->head_desc = op->tail_desc; + op->tail_desc = temp; + } + + /* hash_sel to be used by final function */ + op->head_desc->hash_sel = hash_sel; + + return ret; +} + +static int dcp_sha_final(struct shash_desc *desc, u8 *out) +{ + struct dcp_hash_op *op = shash_desc_ctx(desc); + const uint8_t *digest; + struct dcp *sdcp = global_sdcp; + u32 i, digest_len; + struct mutex *mutex = &sdcp->op_mutex[HASH_CHAN]; + int ret = 0; + + /* Send the leftover bytes in head, which can be length 0, + * but DCP still produces hash result in payload ptr. + * Last data bytes need not be 64-byte multiple. + */ + ret = dcp_perform_hash_op(op->head_desc, 1, op->length == 0, true); + + op->length += op->head_desc->len; + + digest_len = (op->head_desc->hash_sel == + BV_DCP_PACKET2_HASH_SELECT__SHA1) ? SHA1_DIGEST_SIZE : + SHA256_DIGEST_SIZE; + + /* hardware reverses the digest (for some unexplicable reason) */ + digest = op->head_desc->digest + digest_len; + for (i = 0; i < digest_len; i++) + *out++ = *--digest; + + sdcp->chan_in_use[HASH_CHAN] = false; + dcp_clock(sdcp, CLOCK_OFF, false); + mutex_unlock(mutex); + + return ret; +} + +static struct shash_alg dcp_sha1_alg = { + .init = dcp_sha_init, + .update = dcp_sha_update, + .final = dcp_sha_final, + .descsize = sizeof(struct dcp_hash_op), + .digestsize = SHA1_DIGEST_SIZE, + .base = { + .cra_name = "sha1", + .cra_driver_name = "sha1-dcp", + .cra_priority = 300, + .cra_blocksize = SHA1_BLOCK_SIZE, + .cra_ctxsize = + sizeof(struct dcp_hash_op), + .cra_module = THIS_MODULE, + } +}; + +static struct shash_alg dcp_sha256_alg = { + .init = dcp_sha_init, + .update = dcp_sha_update, + .final = dcp_sha_final, + .descsize = sizeof(struct dcp_hash_op), + .digestsize = SHA256_DIGEST_SIZE, + .base = { + .cra_name = "sha256", + .cra_driver_name = "sha256-dcp", + .cra_priority = 300, + .cra_blocksize = SHA256_BLOCK_SIZE, + .cra_ctxsize = + sizeof(struct dcp_hash_op), + .cra_module = THIS_MODULE, + } +}; + +static irqreturn_t dcp_common_irq(int irq, void *context) +{ + struct dcp *sdcp = context; + u32 msk; + + /* check */ + msk = __raw_readl(sdcp->dcp_regs_base + HW_DCP_STAT) & + BF(0x0f, DCP_STAT_IRQ); + if (msk == 0) + return IRQ_NONE; + + /* clear this channel */ + __raw_writel(msk, sdcp->dcp_regs_base + HW_DCP_STAT_CLR); + if (msk & BF(0x01, DCP_STAT_IRQ)) + sdcp->wait[0]++; + if (msk & BF(0x02, DCP_STAT_IRQ)) + sdcp->wait[1]++; + if (msk & BF(0x04, DCP_STAT_IRQ)) + sdcp->wait[2]++; + if (msk & BF(0x08, DCP_STAT_IRQ)) + sdcp->wait[3]++; + return IRQ_HANDLED; +} + +static irqreturn_t dcp_vmi_irq(int irq, void *context) +{ + return dcp_common_irq(irq, context); +} + +static irqreturn_t dcp_irq(int irq, void *context) +{ + return dcp_common_irq(irq, context); +} + +/* DCP bootstream verification interface: uses OTP key for crypto */ +static int dcp_bootstream_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct dcp *sdcp = global_sdcp; + struct dcpboot_dma_area *da = sdcp->dcpboot_dma_area; + void __user *argp = (void __user *)arg; + int chan = ROM_DCP_CHAN; + unsigned long timeout; + struct mutex *mutex; + int retVal; + + /* be paranoid */ + if (sdcp == NULL) + return -EBADF; + + if (cmd != DBS_ENC && cmd != DBS_DEC) + return -EINVAL; + + /* copy to (aligned) block */ + if (copy_from_user(da->block, argp, 16)) + return -EFAULT; + + mutex = &sdcp->op_mutex[chan]; + mutex_lock(mutex); + dcp_clock(sdcp, CLOCK_ON, false); + sdcp->chan_in_use[chan] = true; + + __raw_writel(-1, sdcp->dcp_regs_base + + HW_DCP_CHnSTAT_CLR(ROM_DCP_CHAN)); + __raw_writel(BF(ROM_DCP_CHAN_MASK, DCP_STAT_IRQ), + sdcp->dcp_regs_base + HW_DCP_STAT_CLR); + + da->hw_packet.pNext = 0; + da->hw_packet.pkt1 = BM_DCP_PACKET1_DECR_SEMAPHORE | + BM_DCP_PACKET1_ENABLE_CIPHER | BM_DCP_PACKET1_OTP_KEY | + BM_DCP_PACKET1_INTERRUPT | + (cmd == DBS_ENC ? BM_DCP_PACKET1_CIPHER_ENCRYPT : 0); + da->hw_packet.pkt2 = BF(0, DCP_PACKET2_CIPHER_CFG) | + BF(0, DCP_PACKET2_KEY_SELECT) | + BF(BV_DCP_PACKET2_CIPHER_MODE__ECB, DCP_PACKET2_CIPHER_MODE) | + BF(BV_DCP_PACKET2_CIPHER_SELECT__AES128, DCP_PACKET2_CIPHER_SELECT); + da->hw_packet.pSrc = sdcp->dcpboot_dma_area_phys + + offsetof(struct dcpboot_dma_area, block); + da->hw_packet.pDst = da->hw_packet.pSrc; /* in-place */ + da->hw_packet.size = 16; + da->hw_packet.pPayload = 0; + da->hw_packet.stat = 0; + + /* Load the work packet pointer and bump the channel semaphore */ + __raw_writel(sdcp->dcpboot_dma_area_phys + + offsetof(struct dcpboot_dma_area, hw_packet), + sdcp->dcp_regs_base + HW_DCP_CHnCMDPTR(ROM_DCP_CHAN)); + + sdcp->wait[chan] = 0; + __raw_writel(BF(1, DCP_CHnSEMA_INCREMENT), + sdcp->dcp_regs_base + HW_DCP_CHnSEMA(ROM_DCP_CHAN)); + + timeout = jiffies + msecs_to_jiffies(100); + + while (time_before(jiffies, timeout) && sdcp->wait[chan] == 0) + cpu_relax(); + + if (!time_before(jiffies, timeout)) { + dev_err(sdcp->dev, + "Timeout while waiting for operation to complete\n"); + retVal = -ETIMEDOUT; + goto exit; + } + + if ((__raw_readl(sdcp->dcp_regs_base + HW_DCP_CHnSTAT(ROM_DCP_CHAN)) + & 0xff) != 0) { + dev_err(sdcp->dev, "Channel stat error 0x%02x\n", + __raw_readl(sdcp->dcp_regs_base + + HW_DCP_CHnSTAT(ROM_DCP_CHAN)) & 0xff); + retVal = -EFAULT; + goto exit; + } + + if (copy_to_user(argp, da->block, 16)) { + retVal = -EFAULT; + goto exit; + } + + retVal = 0; + +exit: + sdcp->chan_in_use[chan] = false; + dcp_clock(sdcp, CLOCK_OFF, false); + mutex_unlock(mutex); + return retVal; +} + +static const struct file_operations dcp_bootstream_fops = { + .owner = THIS_MODULE, + .ioctl = dcp_bootstream_ioctl, +}; + +static struct miscdevice dcp_bootstream_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = "dcpboot", + .fops = &dcp_bootstream_fops, +}; + +static int dcp_probe(struct platform_device *pdev) +{ + struct dcp *sdcp = NULL; + struct resource *r; + int i, ret; + dma_addr_t hw_phys; + + if (global_sdcp != NULL) { + dev_err(&pdev->dev, "Only one instance allowed\n"); + ret = -ENODEV; + goto err; + } + + /* allocate memory */ + sdcp = kzalloc(sizeof(*sdcp), GFP_KERNEL); + if (sdcp == NULL) { + dev_err(&pdev->dev, "Failed to allocate structure\n"); + ret = -ENOMEM; + goto err; + } + + sdcp->dev = &pdev->dev; + spin_lock_init(&sdcp->lock); + + for (i = 0; i < DCP_NUM_CHANNELS; i++) { + mutex_init(&sdcp->op_mutex[i]); + init_completion(&sdcp->op_wait[i]); + sdcp->chan_in_use[i] = false; + } + + platform_set_drvdata(pdev, sdcp); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "failed to get IORESOURCE_MEM\n"); + ret = -ENXIO; + goto err_kfree; + } + sdcp->dcp_regs_base = (u32) ioremap(r->start, r->end - r->start + 1); + dcp_clock(sdcp, CLOCK_ON, true); + + /* Soft reset and remove the clock gate */ + __raw_writel(BM_DCP_CTRL_SFTRST, sdcp->dcp_regs_base + HW_DCP_CTRL_SET); + + /* At 24Mhz, it takes no more than 4 clocks (160 ns) Maximum for + * the part to reset, reading the register twice should + * be sufficient to get 4 clks delay. + */ + __raw_readl(sdcp->dcp_regs_base + HW_DCP_CTRL); + __raw_readl(sdcp->dcp_regs_base + HW_DCP_CTRL); + + __raw_writel(BM_DCP_CTRL_SFTRST | BM_DCP_CTRL_CLKGATE, + sdcp->dcp_regs_base + HW_DCP_CTRL_CLR); + + /* Initialize control registers */ + __raw_writel(DCP_CTRL_INIT, sdcp->dcp_regs_base + HW_DCP_CTRL); + __raw_writel(DCP_CHANNELCTRL_INIT, sdcp->dcp_regs_base + + HW_DCP_CHANNELCTRL); + + /* We do not enable context switching. Give the context + * buffer pointer an illegal address so if context switching is + * inadvertantly enabled, the dcp will return an error instead of + * trashing good memory. The dcp dma cannot access rom, so any rom + * address will do. + */ + __raw_writel(0xFFFF0000, sdcp->dcp_regs_base + HW_DCP_CONTEXT); + + for (i = 0; i < DCP_NUM_CHANNELS; i++) + __raw_writel(-1, sdcp->dcp_regs_base + HW_DCP_CHnSTAT_CLR(i)); + __raw_writel(-1, sdcp->dcp_regs_base + HW_DCP_STAT_CLR); + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!r) { + dev_err(&pdev->dev, "can't get IRQ resource (0)\n"); + ret = -EIO; + goto err_gate_clk; + } + sdcp->dcp_vmi_irq = r->start; + ret = request_irq(sdcp->dcp_vmi_irq, dcp_vmi_irq, 0, "dcp", + sdcp); + if (ret != 0) { + dev_err(&pdev->dev, "can't request_irq (0)\n"); + goto err_gate_clk; + } + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + if (!r) { + dev_err(&pdev->dev, "can't get IRQ resource (1)\n"); + ret = -EIO; + goto err_free_irq0; + } + sdcp->dcp_irq = r->start; + ret = request_irq(sdcp->dcp_irq, dcp_irq, 0, "dcp", sdcp); + if (ret != 0) { + dev_err(&pdev->dev, "can't request_irq (1)\n"); + goto err_free_irq0; + } + + global_sdcp = sdcp; + + ret = crypto_register_alg(&dcp_aes_alg); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to register aes crypto\n"); + goto err_free_irq1; + } + + ret = crypto_register_alg(&dcp_aes_ecb_alg); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to register aes ecb crypto\n"); + goto err_unregister_aes; + } + + ret = crypto_register_alg(&dcp_aes_cbc_alg); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to register aes cbc crypto\n"); + goto err_unregister_aes_ecb; + } + + /* Allocate the descriptor to be used for user buffer + * passed in by the "update" function from Crypto API + */ + sdcp->user_buf_desc = dma_alloc_coherent(sdcp->dev, + sizeof(struct dcp_hash_coherent_block), &hw_phys, + GFP_KERNEL); + if (sdcp->user_buf_desc == NULL) { + printk(KERN_ERR "Error allocating coherent block\n"); + ret = -ENOMEM; + goto err_unregister_aes_cbc; + } + + sdcp->user_buf_desc->my_phys = hw_phys; + + /* Allocate 2 buffers (head & tail) & its descriptors to deal with + * buffer lengths that are not 64 byte aligned, except for the + * last one. + */ + sdcp->buf1 = dma_alloc_coherent(sdcp->dev, + 64, &sdcp->buf1_phys, GFP_KERNEL); + if (sdcp->buf1 == NULL) { + printk(KERN_ERR "Error allocating coherent block\n"); + ret = -ENOMEM; + goto err_unregister_aes_cbc; + } + + sdcp->buf2 = dma_alloc_coherent(sdcp->dev, + 64, &sdcp->buf2_phys, GFP_KERNEL); + if (sdcp->buf2 == NULL) { + printk(KERN_ERR "Error allocating coherent block\n"); + ret = -ENOMEM; + goto err_unregister_aes_cbc; + } + + sdcp->buf1_desc = dma_alloc_coherent(sdcp->dev, + sizeof(struct dcp_hash_coherent_block), &hw_phys, + GFP_KERNEL); + if (sdcp->buf1_desc == NULL) { + printk(KERN_ERR "Error allocating coherent block\n"); + ret = -ENOMEM; + goto err_unregister_aes_cbc; + } + + sdcp->buf1_desc->my_phys = hw_phys; + sdcp->buf1_desc->src = (void *)sdcp->buf1; + sdcp->buf1_desc->src_phys = sdcp->buf1_phys; + + sdcp->buf2_desc = dma_alloc_coherent(sdcp->dev, + sizeof(struct dcp_hash_coherent_block), &hw_phys, + GFP_KERNEL); + if (sdcp->buf2_desc == NULL) { + printk(KERN_ERR "Error allocating coherent block\n"); + ret = -ENOMEM; + goto err_unregister_aes_cbc; + } + + sdcp->buf2_desc->my_phys = hw_phys; + sdcp->buf2_desc->src = (void *)sdcp->buf2; + sdcp->buf2_desc->src_phys = sdcp->buf2_phys; + + + ret = crypto_register_shash(&dcp_sha1_alg); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to register sha1 hash\n"); + goto err_unregister_aes_cbc; + } + + if (__raw_readl(sdcp->dcp_regs_base + HW_DCP_CAPABILITY1) & + BF_DCP_CAPABILITY1_HASH_ALGORITHMS( + BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA256)) { + + ret = crypto_register_shash(&dcp_sha256_alg); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to register sha256 hash\n"); + goto err_unregister_sha1; + } + } + + /* register dcpboot interface to allow apps (such as kobs-ng) to + * verify files (such as the bootstream) using the OTP key for crypto */ + ret = misc_register(&dcp_bootstream_misc); + if (ret != 0) { + dev_err(&pdev->dev, "Unable to register misc device\n"); + goto err_unregister_sha1; + } + + sdcp->dcpboot_dma_area = dma_alloc_coherent(&pdev->dev, + sizeof(*sdcp->dcpboot_dma_area), &sdcp->dcpboot_dma_area_phys, + GFP_KERNEL); + if (sdcp->dcpboot_dma_area == NULL) { + dev_err(&pdev->dev, + "Unable to allocate DMAable memory \ + for dcpboot interface\n"); + goto err_dereg; + } + + dcp_clock(sdcp, CLOCK_OFF, false); + dev_notice(&pdev->dev, "DCP crypto enabled.!\n"); + return 0; + +err_dereg: + misc_deregister(&dcp_bootstream_misc); +err_unregister_sha1: + crypto_unregister_shash(&dcp_sha1_alg); +err_unregister_aes_cbc: + crypto_unregister_alg(&dcp_aes_cbc_alg); +err_unregister_aes_ecb: + crypto_unregister_alg(&dcp_aes_ecb_alg); +err_unregister_aes: + crypto_unregister_alg(&dcp_aes_alg); +err_free_irq1: + free_irq(sdcp->dcp_irq, sdcp); +err_free_irq0: + free_irq(sdcp->dcp_vmi_irq, sdcp); +err_gate_clk: + dcp_clock(sdcp, CLOCK_OFF, false); +err_kfree: + kfree(sdcp); +err: + + return ret; +} + +static int dcp_remove(struct platform_device *pdev) +{ + struct dcp *sdcp; + + sdcp = platform_get_drvdata(pdev); + platform_set_drvdata(pdev, NULL); + + dcp_clock(sdcp, CLOCK_ON, false); + + free_irq(sdcp->dcp_irq, sdcp); + free_irq(sdcp->dcp_vmi_irq, sdcp); + + /* if head and tail buffers were allocated, free them */ + if (sdcp->buf1) { + dma_free_coherent(sdcp->dev, 64, sdcp->buf1, sdcp->buf1_phys); + dma_free_coherent(sdcp->dev, 64, sdcp->buf2, sdcp->buf2_phys); + + dma_free_coherent(sdcp->dev, + sizeof(struct dcp_hash_coherent_block), + sdcp->buf1_desc, sdcp->buf1_desc->my_phys); + + dma_free_coherent(sdcp->dev, + sizeof(struct dcp_hash_coherent_block), + sdcp->buf2_desc, sdcp->buf2_desc->my_phys); + + dma_free_coherent(sdcp->dev, + sizeof(struct dcp_hash_coherent_block), + sdcp->user_buf_desc, sdcp->user_buf_desc->my_phys); + } + + if (sdcp->dcpboot_dma_area) { + dma_free_coherent(&pdev->dev, sizeof(*sdcp->dcpboot_dma_area), + sdcp->dcpboot_dma_area, sdcp->dcpboot_dma_area_phys); + misc_deregister(&dcp_bootstream_misc); + } + + + crypto_unregister_shash(&dcp_sha1_alg); + + if (__raw_readl(sdcp->dcp_regs_base + HW_DCP_CAPABILITY1) & + BF_DCP_CAPABILITY1_HASH_ALGORITHMS( + BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA256)) + crypto_unregister_shash(&dcp_sha256_alg); + + crypto_unregister_alg(&dcp_aes_cbc_alg); + crypto_unregister_alg(&dcp_aes_ecb_alg); + crypto_unregister_alg(&dcp_aes_alg); + + dcp_clock(sdcp, CLOCK_OFF, true); + iounmap((void *) sdcp->dcp_regs_base); + kfree(sdcp); + global_sdcp = NULL; + + return 0; +} + +static int dcp_suspend(struct platform_device *pdev, + pm_message_t state) +{ +#ifdef CONFIG_PM + struct dcp *sdcp = platform_get_drvdata(pdev); + + if (sdcp->clock_state == CLOCK_ON) { + dcp_clock(sdcp, CLOCK_OFF, true); + /* indicate that clock needs to be turned on upon resume */ + sdcp->clock_state = CLOCK_ON; + } +#endif + return 0; +} + +static int dcp_resume(struct platform_device *pdev) +{ +#ifdef CONFIG_PM + struct dcp *sdcp = platform_get_drvdata(pdev); + + /* if clock was on prior to suspend, turn it back on */ + if (sdcp->clock_state == CLOCK_ON) + dcp_clock(sdcp, CLOCK_ON, true); +#endif + return 0; +} + +static struct platform_driver dcp_driver = { + .probe = dcp_probe, + .remove = dcp_remove, + .suspend = dcp_suspend, + .resume = dcp_resume, + .driver = { + .name = "dcp", + .owner = THIS_MODULE, + }, +}; + +static int __init +dcp_init(void) +{ + return platform_driver_register(&dcp_driver); +} + +static void __exit +dcp_exit(void) +{ + platform_driver_unregister(&dcp_driver); +} + +MODULE_AUTHOR("Pantelis Antoniou "); +MODULE_DESCRIPTION("DCP Crypto Driver"); +MODULE_LICENSE("GPL"); + +module_init(dcp_init); +module_exit(dcp_exit); diff --git a/drivers/crypto/dcp.h b/drivers/crypto/dcp.h new file mode 100644 index 000000000000..a4db91334d06 --- /dev/null +++ b/drivers/crypto/dcp.h @@ -0,0 +1,717 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef DCP_H_ +#define DCP_H_ + +#define CIPHER_CHAN 1 +#define CIPHER_MASK (1 << CIPHER_CHAN) + +#define HASH_CHAN 0 +#define HASH_MASK (1 << HASH_CHAN) + +/* DCP boostream interface uses this channel (same as the ROM) */ +#define ROM_DCP_CHAN 3 +#define ROM_DCP_CHAN_MASK (1 << ROM_DCP_CHAN) + + +#define ALL_MASK (CIPHER_MASK | HASH_MASK | ROM_DCP_CHAN_MASK) + +/* Defines the initialization value for the dcp control register */ +#define DCP_CTRL_INIT \ + (BM_DCP_CTRL_GATHER_RESIDUAL_WRITES | \ + BM_DCP_CTRL_ENABLE_CONTEXT_CACHING | \ + BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 | \ + BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 | \ + BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 | \ + BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3) + +/* Defines the initialization value for the dcp channel control register */ +#define DCP_CHANNELCTRL_INIT \ + BF(ALL_MASK, DCP_CHANNELCTRL_ENABLE_CHANNEL) + +/* DCP work packet 1 value for encryption */ +#define DCP_PKT1_ENCRYPT \ + (BM_DCP_PACKET1_DECR_SEMAPHORE | \ + BM_DCP_PACKET1_ENABLE_CIPHER | \ + BM_DCP_PACKET1_CIPHER_ENCRYPT | \ + BM_DCP_PACKET1_CIPHER_INIT) + +/* DCP work packet 1 value for decryption */ +#define DCP_PKT1_DECRYPT \ + (BM_DCP_PACKET1_DECR_SEMAPHORE | \ + BM_DCP_PACKET1_ENABLE_CIPHER | \ + BM_DCP_PACKET1_CIPHER_INIT) + +/* DCP (decryption) work packet definition */ +struct dcp_hw_packet { + uint32_t pNext; /* next dcp work packet address */ + uint32_t pkt1; /* dcp work packet 1 (control 0) */ + uint32_t pkt2; /* dcp work packet 2 (control 1) */ + uint32_t pSrc; /* source buffer address */ + uint32_t pDst; /* destination buffer address */ + uint32_t size; /* buffer size in bytes */ + uint32_t pPayload; /* payload buffer address */ + uint32_t stat; /* dcp status (written by dcp) */ +}; + +#define DCP_NUM_CHANNELS 4 + +/* DCP Register definitions */ + +#ifndef BF +#define BF(value, field) (((value) << BP_##field) & BM_##field) +#endif + +#define REGS_DCP_SIZE 0x00002000 + +#define HW_DCP_CTRL (0x00000000) +#define HW_DCP_CTRL_SET (0x00000004) +#define HW_DCP_CTRL_CLR (0x00000008) +#define HW_DCP_CTRL_TOG (0x0000000c) + +#define BM_DCP_CTRL_SFTRST 0x80000000 +#define BM_DCP_CTRL_CLKGATE 0x40000000 +#define BM_DCP_CTRL_PRESENT_CRYPTO 0x20000000 +#define BV_DCP_CTRL_PRESENT_CRYPTO__Present 0x1 +#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent 0x0 +#define BM_DCP_CTRL_PRESENT_CSC 0x10000000 +#define BV_DCP_CTRL_PRESENT_CSC__Present 0x1 +#define BV_DCP_CTRL_PRESENT_CSC__Absent 0x0 +#define BP_DCP_CTRL_RSVD1 24 +#define BM_DCP_CTRL_RSVD1 0x0F000000 +#define BF_DCP_CTRL_RSVD1(v) \ + (((v) << 24) & BM_DCP_CTRL_RSVD1) +#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000 +#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000 +#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 0x00200000 +#define BP_DCP_CTRL_RSVD0 9 +#define BM_DCP_CTRL_RSVD0 0x001FFE00 +#define BF_DCP_CTRL_RSVD0(v) \ + (((v) << 9) & BM_DCP_CTRL_RSVD0) +#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE 0x00000100 +#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 +#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF +#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v) \ + (((v) << 0) & BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE) +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 0x01 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 0x02 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 0x04 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3 0x08 + +#define HW_DCP_STAT (0x00000010) +#define HW_DCP_STAT_SET (0x00000014) +#define HW_DCP_STAT_CLR (0x00000018) +#define HW_DCP_STAT_TOG (0x0000001c) + +#define BP_DCP_STAT_RSVD2 29 +#define BM_DCP_STAT_RSVD2 0xE0000000 +#define BF_DCP_STAT_RSVD2(v) \ + (((v) << 29) & BM_DCP_STAT_RSVD2) +#define BM_DCP_STAT_OTP_KEY_READY 0x10000000 +#define BP_DCP_STAT_CUR_CHANNEL 24 +#define BM_DCP_STAT_CUR_CHANNEL 0x0F000000 +#define BF_DCP_STAT_CUR_CHANNEL(v) \ + (((v) << 24) & BM_DCP_STAT_CUR_CHANNEL) +#define BV_DCP_STAT_CUR_CHANNEL__None 0x0 +#define BV_DCP_STAT_CUR_CHANNEL__CH0 0x1 +#define BV_DCP_STAT_CUR_CHANNEL__CH1 0x2 +#define BV_DCP_STAT_CUR_CHANNEL__CH2 0x3 +#define BV_DCP_STAT_CUR_CHANNEL__CH3 0x4 +#define BV_DCP_STAT_CUR_CHANNEL__CSC 0x8 +#define BP_DCP_STAT_READY_CHANNELS 16 +#define BM_DCP_STAT_READY_CHANNELS 0x00FF0000 +#define BF_DCP_STAT_READY_CHANNELS(v) \ + (((v) << 16) & BM_DCP_STAT_READY_CHANNELS) +#define BV_DCP_STAT_READY_CHANNELS__CH0 0x01 +#define BV_DCP_STAT_READY_CHANNELS__CH1 0x02 +#define BV_DCP_STAT_READY_CHANNELS__CH2 0x04 +#define BV_DCP_STAT_READY_CHANNELS__CH3 0x08 +#define BP_DCP_STAT_RSVD1 9 +#define BM_DCP_STAT_RSVD1 0x0000FE00 +#define BF_DCP_STAT_RSVD1(v) \ + (((v) << 9) & BM_DCP_STAT_RSVD1) +#define BM_DCP_STAT_CSCIRQ 0x00000100 +#define BP_DCP_STAT_RSVD0 4 +#define BM_DCP_STAT_RSVD0 0x000000F0 +#define BF_DCP_STAT_RSVD0(v) \ + (((v) << 4) & BM_DCP_STAT_RSVD0) +#define BP_DCP_STAT_IRQ 0 +#define BM_DCP_STAT_IRQ 0x0000000F +#define BF_DCP_STAT_IRQ(v) \ + (((v) << 0) & BM_DCP_STAT_IRQ) + +#define HW_DCP_CHANNELCTRL (0x00000020) +#define HW_DCP_CHANNELCTRL_SET (0x00000024) +#define HW_DCP_CHANNELCTRL_CLR (0x00000028) +#define HW_DCP_CHANNELCTRL_TOG (0x0000002c) + +#define BP_DCP_CHANNELCTRL_RSVD 19 +#define BM_DCP_CHANNELCTRL_RSVD 0xFFF80000 +#define BF_DCP_CHANNELCTRL_RSVD(v) \ + (((v) << 19) & BM_DCP_CHANNELCTRL_RSVD) +#define BP_DCP_CHANNELCTRL_CSC_PRIORITY 17 +#define BM_DCP_CHANNELCTRL_CSC_PRIORITY 0x00060000 +#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v) \ + (((v) << 17) & BM_DCP_CHANNELCTRL_CSC_PRIORITY) +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH 0x3 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED 0x2 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW 0x1 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND 0x0 +#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED 0x00010000 +#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 8 +#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 0x0000FF00 +#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v) \ + (((v) << 8) & BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL) +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0 0x01 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1 0x02 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2 0x04 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3 0x08 +#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 +#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF +#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v) \ + (((v) << 0) & BM_DCP_CHANNELCTRL_ENABLE_CHANNEL) +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0 0x01 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1 0x02 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2 0x04 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3 0x08 + +#define HW_DCP_CAPABILITY0 (0x00000030) + +#define BM_DCP_CAPABILITY0_DISABLE_DECRYPT 0x80000000 +#define BM_DCP_CAPABILITY0_ENABLE_TZONE 0x40000000 +#define BP_DCP_CAPABILITY0_RSVD 12 +#define BM_DCP_CAPABILITY0_RSVD 0x3FFFF000 +#define BF_DCP_CAPABILITY0_RSVD(v) \ + (((v) << 12) & BM_DCP_CAPABILITY0_RSVD) +#define BP_DCP_CAPABILITY0_NUM_CHANNELS 8 +#define BM_DCP_CAPABILITY0_NUM_CHANNELS 0x00000F00 +#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v) \ + (((v) << 8) & BM_DCP_CAPABILITY0_NUM_CHANNELS) +#define BP_DCP_CAPABILITY0_NUM_KEYS 0 +#define BM_DCP_CAPABILITY0_NUM_KEYS 0x000000FF +#define BF_DCP_CAPABILITY0_NUM_KEYS(v) \ + (((v) << 0) & BM_DCP_CAPABILITY0_NUM_KEYS) + +#define HW_DCP_CAPABILITY1 (0x00000040) + +#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS 16 +#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS 0xFFFF0000 +#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v) \ + (((v) << 16) & BM_DCP_CAPABILITY1_HASH_ALGORITHMS) +#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1 0x0001 +#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32 0x0002 +#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA256 0x0004 +#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0 +#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0x0000FFFF +#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v) \ + (((v) << 0) & BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS) +#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128 0x0001 + +#define HW_DCP_CONTEXT (0x00000050) + +#define BP_DCP_CONTEXT_ADDR 0 +#define BM_DCP_CONTEXT_ADDR 0xFFFFFFFF +#define BF_DCP_CONTEXT_ADDR(v) (v) + +#define HW_DCP_KEY (0x00000060) + +#define BP_DCP_KEY_RSVD 8 +#define BM_DCP_KEY_RSVD 0xFFFFFF00 +#define BF_DCP_KEY_RSVD(v) \ + (((v) << 8) & BM_DCP_KEY_RSVD) +#define BP_DCP_KEY_RSVD_INDEX 6 +#define BM_DCP_KEY_RSVD_INDEX 0x000000C0 +#define BF_DCP_KEY_RSVD_INDEX(v) \ + (((v) << 6) & BM_DCP_KEY_RSVD_INDEX) +#define BP_DCP_KEY_INDEX 4 +#define BM_DCP_KEY_INDEX 0x00000030 +#define BF_DCP_KEY_INDEX(v) \ + (((v) << 4) & BM_DCP_KEY_INDEX) +#define BP_DCP_KEY_RSVD_SUBWORD 2 +#define BM_DCP_KEY_RSVD_SUBWORD 0x0000000C +#define BF_DCP_KEY_RSVD_SUBWORD(v) \ + (((v) << 2) & BM_DCP_KEY_RSVD_SUBWORD) +#define BP_DCP_KEY_SUBWORD 0 +#define BM_DCP_KEY_SUBWORD 0x00000003 +#define BF_DCP_KEY_SUBWORD(v) \ + (((v) << 0) & BM_DCP_KEY_SUBWORD) + +#define HW_DCP_KEYDATA (0x00000070) + +#define BP_DCP_KEYDATA_DATA 0 +#define BM_DCP_KEYDATA_DATA 0xFFFFFFFF +#define BF_DCP_KEYDATA_DATA(v) (v) + +#define HW_DCP_PACKET0 (0x00000080) + +#define BP_DCP_PACKET0_ADDR 0 +#define BM_DCP_PACKET0_ADDR 0xFFFFFFFF +#define BF_DCP_PACKET0_ADDR(v) (v) + +#define HW_DCP_PACKET1 (0x00000090) + +#define BP_DCP_PACKET1_TAG 24 +#define BM_DCP_PACKET1_TAG 0xFF000000 +#define BF_DCP_PACKET1_TAG(v) \ + (((v) << 24) & BM_DCP_PACKET1_TAG) +#define BM_DCP_PACKET1_OUTPUT_WORDSWAP 0x00800000 +#define BM_DCP_PACKET1_OUTPUT_BYTESWAP 0x00400000 +#define BM_DCP_PACKET1_INPUT_WORDSWAP 0x00200000 +#define BM_DCP_PACKET1_INPUT_BYTESWAP 0x00100000 +#define BM_DCP_PACKET1_KEY_WORDSWAP 0x00080000 +#define BM_DCP_PACKET1_KEY_BYTESWAP 0x00040000 +#define BM_DCP_PACKET1_TEST_SEMA_IRQ 0x00020000 +#define BM_DCP_PACKET1_CONSTANT_FILL 0x00010000 +#define BM_DCP_PACKET1_HASH_OUTPUT 0x00008000 +#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT 0x00 +#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT 0x01 +#define BM_DCP_PACKET1_CHECK_HASH 0x00004000 +#define BM_DCP_PACKET1_HASH_TERM 0x00002000 +#define BM_DCP_PACKET1_HASH_INIT 0x00001000 +#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800 +#define BM_DCP_PACKET1_OTP_KEY 0x00000400 +#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200 +#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100 +#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT 0x01 +#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT 0x00 +#define BM_DCP_PACKET1_ENABLE_BLIT 0x00000080 +#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040 +#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020 +#define BM_DCP_PACKET1_ENABLE_MEMCOPY 0x00000010 +#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008 +#define BM_DCP_PACKET1_CHAIN 0x00000004 +#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002 +#define BM_DCP_PACKET1_INTERRUPT 0x00000001 + +#define HW_DCP_PACKET2 (0x000000a0) + +#define BP_DCP_PACKET2_CIPHER_CFG 24 +#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000 +#define BF_DCP_PACKET2_CIPHER_CFG(v) \ + (((v) << 24) & BM_DCP_PACKET2_CIPHER_CFG) +#define BP_DCP_PACKET2_RSVD 20 +#define BM_DCP_PACKET2_RSVD 0x00F00000 +#define BF_DCP_PACKET2_RSVD(v) \ + (((v) << 20) & BM_DCP_PACKET2_RSVD) +#define BP_DCP_PACKET2_HASH_SELECT 16 +#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000 +#define BF_DCP_PACKET2_HASH_SELECT(v) \ + (((v) << 16) & BM_DCP_PACKET2_HASH_SELECT) +#define BV_DCP_PACKET2_HASH_SELECT__SHA1 0x00 +#define BV_DCP_PACKET2_HASH_SELECT__CRC32 0x01 +#define BV_DCP_PACKET2_HASH_SELECT__SHA256 0x02 +#define BP_DCP_PACKET2_KEY_SELECT 8 +#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00 +#define BF_DCP_PACKET2_KEY_SELECT(v) \ + (((v) << 8) & BM_DCP_PACKET2_KEY_SELECT) +#define BP_DCP_PACKET2_CIPHER_MODE 4 +#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0 +#define BF_DCP_PACKET2_CIPHER_MODE(v) \ + (((v) << 4) & BM_DCP_PACKET2_CIPHER_MODE) +#define BV_DCP_PACKET2_CIPHER_MODE__ECB 0x00 +#define BV_DCP_PACKET2_CIPHER_MODE__CBC 0x01 +#define BP_DCP_PACKET2_CIPHER_SELECT 0 +#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F +#define BF_DCP_PACKET2_CIPHER_SELECT(v) \ + (((v) << 0) & BM_DCP_PACKET2_CIPHER_SELECT) +#define BV_DCP_PACKET2_CIPHER_SELECT__AES128 0x00 + +#define HW_DCP_PACKET3 (0x000000b0) + +#define BP_DCP_PACKET3_ADDR 0 +#define BM_DCP_PACKET3_ADDR 0xFFFFFFFF +#define BF_DCP_PACKET3_ADDR(v) (v) + +#define HW_DCP_PACKET4 (0x000000c0) + +#define BP_DCP_PACKET4_ADDR 0 +#define BM_DCP_PACKET4_ADDR 0xFFFFFFFF +#define BF_DCP_PACKET4_ADDR(v) (v) + +#define HW_DCP_PACKET5 (0x000000d0) + +#define BP_DCP_PACKET5_COUNT 0 +#define BM_DCP_PACKET5_COUNT 0xFFFFFFFF +#define BF_DCP_PACKET5_COUNT(v) (v) + +#define HW_DCP_PACKET6 (0x000000e0) + +#define BP_DCP_PACKET6_ADDR 0 +#define BM_DCP_PACKET6_ADDR 0xFFFFFFFF +#define BF_DCP_PACKET6_ADDR(v) (v) + +/* + * multi-register-define name HW_DCP_CHnCMDPTR + * base 0x00000100 + * count 4 + * offset 0x40 + */ +#define HW_DCP_CHnCMDPTR(n) (0x00000100 + (n) * 0x40) + +#define BP_DCP_CHnCMDPTR_ADDR 0 +#define BM_DCP_CHnCMDPTR_ADDR 0xFFFFFFFF +#define BF_DCP_CHnCMDPTR_ADDR(v) (v) + +/* + * multi-register-define name HW_DCP_CHnSEMA + * base 0x00000110 + * count 4 + * offset 0x40 + */ +#define HW_DCP_CHnSEMA(n) (0x00000110 + (n) * 0x40) + +#define BP_DCP_CHnSEMA_RSVD2 24 +#define BM_DCP_CHnSEMA_RSVD2 0xFF000000 +#define BF_DCP_CHnSEMA_RSVD2(v) \ + (((v) << 24) & BM_DCP_CHnSEMA_RSVD2) +#define BP_DCP_CHnSEMA_VALUE 16 +#define BM_DCP_CHnSEMA_VALUE 0x00FF0000 +#define BF_DCP_CHnSEMA_VALUE(v) \ + (((v) << 16) & BM_DCP_CHnSEMA_VALUE) +#define BP_DCP_CHnSEMA_RSVD1 8 +#define BM_DCP_CHnSEMA_RSVD1 0x0000FF00 +#define BF_DCP_CHnSEMA_RSVD1(v) \ + (((v) << 8) & BM_DCP_CHnSEMA_RSVD1) +#define BP_DCP_CHnSEMA_INCREMENT 0 +#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF +#define BF_DCP_CHnSEMA_INCREMENT(v) \ + (((v) << 0) & BM_DCP_CHnSEMA_INCREMENT) + +/* + * multi-register-define name HW_DCP_CHnSTAT + * base 0x00000120 + * count 4 + * offset 0x40 + */ +#define HW_DCP_CHnSTAT(n) (0x00000120 + (n) * 0x40) +#define HW_DCP_CHnSTAT_SET(n) (0x00000124 + (n) * 0x40) +#define HW_DCP_CHnSTAT_CLR(n) (0x00000128 + (n) * 0x40) +#define HW_DCP_CHnSTAT_TOG(n) (0x0000012c + (n) * 0x40) + +#define BP_DCP_CHnSTAT_TAG 24 +#define BM_DCP_CHnSTAT_TAG 0xFF000000 +#define BF_DCP_CHnSTAT_TAG(v) \ + (((v) << 24) & BM_DCP_CHnSTAT_TAG) +#define BP_DCP_CHnSTAT_ERROR_CODE 16 +#define BM_DCP_CHnSTAT_ERROR_CODE 0x00FF0000 +#define BF_DCP_CHnSTAT_ERROR_CODE(v) \ + (((v) << 16) & BM_DCP_CHnSTAT_ERROR_CODE) +#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0 0x01 +#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN 0x02 +#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR 0x03 +#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR 0x04 +#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE 0x05 +#define BP_DCP_CHnSTAT_RSVD0 7 +#define BM_DCP_CHnSTAT_RSVD0 0x0000FF80 +#define BF_DCP_CHnSTAT_RSVD0(v) \ + (((v) << 7) & BM_DCP_CHnSTAT_RSVD0) +#define BM_DCP_CHnSTAT_ERROR_PAGEFAULT 0x00000040 +#define BM_DCP_CHnSTAT_ERROR_DST 0x00000020 +#define BM_DCP_CHnSTAT_ERROR_SRC 0x00000010 +#define BM_DCP_CHnSTAT_ERROR_PACKET 0x00000008 +#define BM_DCP_CHnSTAT_ERROR_SETUP 0x00000004 +#define BM_DCP_CHnSTAT_HASH_MISMATCH 0x00000002 +#define BM_DCP_CHnSTAT_RSVD_COMPLETE 0x00000001 + +/* + * multi-register-define name HW_DCP_CHnOPTS + * base 0x00000130 + * count 4 + * offset 0x40 + */ +#define HW_DCP_CHnOPTS(n) (0x00000130 + (n) * 0x40) +#define HW_DCP_CHnOPTS_SET(n) (0x00000134 + (n) * 0x40) +#define HW_DCP_CHnOPTS_CLR(n) (0x00000138 + (n) * 0x40) +#define HW_DCP_CHnOPTS_TOG(n) (0x0000013c + (n) * 0x40) + +#define BP_DCP_CHnOPTS_RSVD 16 +#define BM_DCP_CHnOPTS_RSVD 0xFFFF0000 +#define BF_DCP_CHnOPTS_RSVD(v) \ + (((v) << 16) & BM_DCP_CHnOPTS_RSVD) +#define BP_DCP_CHnOPTS_RECOVERY_TIMER 0 +#define BM_DCP_CHnOPTS_RECOVERY_TIMER 0x0000FFFF +#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v) \ + (((v) << 0) & BM_DCP_CHnOPTS_RECOVERY_TIMER) + +#define HW_DCP_CSCCTRL0 (0x00000300) +#define HW_DCP_CSCCTRL0_SET (0x00000304) +#define HW_DCP_CSCCTRL0_CLR (0x00000308) +#define HW_DCP_CSCCTRL0_TOG (0x0000030c) + +#define BP_DCP_CSCCTRL0_RSVD1 16 +#define BM_DCP_CSCCTRL0_RSVD1 0xFFFF0000 +#define BF_DCP_CSCCTRL0_RSVD1(v) \ + (((v) << 16) & BM_DCP_CSCCTRL0_RSVD1) +#define BM_DCP_CSCCTRL0_CLIP 0x00008000 +#define BM_DCP_CSCCTRL0_UPSAMPLE 0x00004000 +#define BM_DCP_CSCCTRL0_SCALE 0x00002000 +#define BM_DCP_CSCCTRL0_ROTATE 0x00001000 +#define BM_DCP_CSCCTRL0_SUBSAMPLE 0x00000800 +#define BM_DCP_CSCCTRL0_DELTA 0x00000400 +#define BP_DCP_CSCCTRL0_RGB_FORMAT 8 +#define BM_DCP_CSCCTRL0_RGB_FORMAT 0x00000300 +#define BF_DCP_CSCCTRL0_RGB_FORMAT(v) \ + (((v) << 8) & BM_DCP_CSCCTRL0_RGB_FORMAT) +#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565 0x0 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI 0x1 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24 0x2 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I 0x3 +#define BP_DCP_CSCCTRL0_YUV_FORMAT 4 +#define BM_DCP_CSCCTRL0_YUV_FORMAT 0x000000F0 +#define BF_DCP_CSCCTRL0_YUV_FORMAT(v) \ + (((v) << 4) & BM_DCP_CSCCTRL0_YUV_FORMAT) +#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420 0x0 +#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422 0x2 +#define BP_DCP_CSCCTRL0_RSVD0 1 +#define BM_DCP_CSCCTRL0_RSVD0 0x0000000E +#define BF_DCP_CSCCTRL0_RSVD0(v) \ + (((v) << 1) & BM_DCP_CSCCTRL0_RSVD0) +#define BM_DCP_CSCCTRL0_ENABLE 0x00000001 + +#define HW_DCP_CSCSTAT (0x00000310) +#define HW_DCP_CSCSTAT_SET (0x00000314) +#define HW_DCP_CSCSTAT_CLR (0x00000318) +#define HW_DCP_CSCSTAT_TOG (0x0000031c) + +#define BP_DCP_CSCSTAT_RSVD3 24 +#define BM_DCP_CSCSTAT_RSVD3 0xFF000000 +#define BF_DCP_CSCSTAT_RSVD3(v) \ + (((v) << 24) & BM_DCP_CSCSTAT_RSVD3) +#define BP_DCP_CSCSTAT_ERROR_CODE 16 +#define BM_DCP_CSCSTAT_ERROR_CODE 0x00FF0000 +#define BF_DCP_CSCSTAT_ERROR_CODE(v) \ + (((v) << 16) & BM_DCP_CSCSTAT_ERROR_CODE) +#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x01 +#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x02 +#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x03 +#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x04 +#define BP_DCP_CSCSTAT_RSVD2 7 +#define BM_DCP_CSCSTAT_RSVD2 0x0000FF80 +#define BF_DCP_CSCSTAT_RSVD2(v) \ + (((v) << 7) & BM_DCP_CSCSTAT_RSVD2) +#define BM_DCP_CSCSTAT_ERROR_PAGEFAULT 0x00000040 +#define BM_DCP_CSCSTAT_ERROR_DST 0x00000020 +#define BM_DCP_CSCSTAT_ERROR_SRC 0x00000010 +#define BM_DCP_CSCSTAT_RSVD1 0x00000008 +#define BM_DCP_CSCSTAT_ERROR_SETUP 0x00000004 +#define BM_DCP_CSCSTAT_RSVD0 0x00000002 +#define BM_DCP_CSCSTAT_COMPLETE 0x00000001 + +#define HW_DCP_CSCOUTBUFPARAM (0x00000320) + +#define BP_DCP_CSCOUTBUFPARAM_RSVD1 24 +#define BM_DCP_CSCOUTBUFPARAM_RSVD1 0xFF000000 +#define BF_DCP_CSCOUTBUFPARAM_RSVD1(v) \ + (((v) << 24) & BM_DCP_CSCOUTBUFPARAM_RSVD1) +#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE 12 +#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE 0x00FFF000 +#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) \ + (((v) << 12) & BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE) +#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE 0 +#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE 0x00000FFF +#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v) \ + (((v) << 0) & BM_DCP_CSCOUTBUFPARAM_LINE_SIZE) + +#define HW_DCP_CSCINBUFPARAM (0x00000330) + +#define BP_DCP_CSCINBUFPARAM_RSVD1 12 +#define BM_DCP_CSCINBUFPARAM_RSVD1 0xFFFFF000 +#define BF_DCP_CSCINBUFPARAM_RSVD1(v) \ + (((v) << 12) & BM_DCP_CSCINBUFPARAM_RSVD1) +#define BP_DCP_CSCINBUFPARAM_LINE_SIZE 0 +#define BM_DCP_CSCINBUFPARAM_LINE_SIZE 0x00000FFF +#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v) \ + (((v) << 0) & BM_DCP_CSCINBUFPARAM_LINE_SIZE) + +#define HW_DCP_CSCRGB (0x00000340) + +#define BP_DCP_CSCRGB_ADDR 0 +#define BM_DCP_CSCRGB_ADDR 0xFFFFFFFF +#define BF_DCP_CSCRGB_ADDR(v) (v) + +#define HW_DCP_CSCLUMA (0x00000350) + +#define BP_DCP_CSCLUMA_ADDR 0 +#define BM_DCP_CSCLUMA_ADDR 0xFFFFFFFF +#define BF_DCP_CSCLUMA_ADDR(v) (v) + +#define HW_DCP_CSCCHROMAU (0x00000360) + +#define BP_DCP_CSCCHROMAU_ADDR 0 +#define BM_DCP_CSCCHROMAU_ADDR 0xFFFFFFFF +#define BF_DCP_CSCCHROMAU_ADDR(v) (v) + +#define HW_DCP_CSCCHROMAV (0x00000370) + +#define BP_DCP_CSCCHROMAV_ADDR 0 +#define BM_DCP_CSCCHROMAV_ADDR 0xFFFFFFFF +#define BF_DCP_CSCCHROMAV_ADDR(v) (v) + +#define HW_DCP_CSCCOEFF0 (0x00000380) + +#define BP_DCP_CSCCOEFF0_RSVD1 26 +#define BM_DCP_CSCCOEFF0_RSVD1 0xFC000000 +#define BF_DCP_CSCCOEFF0_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCCOEFF0_RSVD1) +#define BP_DCP_CSCCOEFF0_C0 16 +#define BM_DCP_CSCCOEFF0_C0 0x03FF0000 +#define BF_DCP_CSCCOEFF0_C0(v) \ + (((v) << 16) & BM_DCP_CSCCOEFF0_C0) +#define BP_DCP_CSCCOEFF0_UV_OFFSET 8 +#define BM_DCP_CSCCOEFF0_UV_OFFSET 0x0000FF00 +#define BF_DCP_CSCCOEFF0_UV_OFFSET(v) \ + (((v) << 8) & BM_DCP_CSCCOEFF0_UV_OFFSET) +#define BP_DCP_CSCCOEFF0_Y_OFFSET 0 +#define BM_DCP_CSCCOEFF0_Y_OFFSET 0x000000FF +#define BF_DCP_CSCCOEFF0_Y_OFFSET(v) \ + (((v) << 0) & BM_DCP_CSCCOEFF0_Y_OFFSET) + +#define HW_DCP_CSCCOEFF1 (0x00000390) + +#define BP_DCP_CSCCOEFF1_RSVD1 26 +#define BM_DCP_CSCCOEFF1_RSVD1 0xFC000000 +#define BF_DCP_CSCCOEFF1_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCCOEFF1_RSVD1) +#define BP_DCP_CSCCOEFF1_C1 16 +#define BM_DCP_CSCCOEFF1_C1 0x03FF0000 +#define BF_DCP_CSCCOEFF1_C1(v) \ + (((v) << 16) & BM_DCP_CSCCOEFF1_C1) +#define BP_DCP_CSCCOEFF1_RSVD0 10 +#define BM_DCP_CSCCOEFF1_RSVD0 0x0000FC00 +#define BF_DCP_CSCCOEFF1_RSVD0(v) \ + (((v) << 10) & BM_DCP_CSCCOEFF1_RSVD0) +#define BP_DCP_CSCCOEFF1_C4 0 +#define BM_DCP_CSCCOEFF1_C4 0x000003FF +#define BF_DCP_CSCCOEFF1_C4(v) \ + (((v) << 0) & BM_DCP_CSCCOEFF1_C4) + +#define HW_DCP_CSCCOEFF2 (0x000003a0) + +#define BP_DCP_CSCCOEFF2_RSVD1 26 +#define BM_DCP_CSCCOEFF2_RSVD1 0xFC000000 +#define BF_DCP_CSCCOEFF2_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCCOEFF2_RSVD1) +#define BP_DCP_CSCCOEFF2_C2 16 +#define BM_DCP_CSCCOEFF2_C2 0x03FF0000 +#define BF_DCP_CSCCOEFF2_C2(v) \ + (((v) << 16) & BM_DCP_CSCCOEFF2_C2) +#define BP_DCP_CSCCOEFF2_RSVD0 10 +#define BM_DCP_CSCCOEFF2_RSVD0 0x0000FC00 +#define BF_DCP_CSCCOEFF2_RSVD0(v) \ + (((v) << 10) & BM_DCP_CSCCOEFF2_RSVD0) +#define BP_DCP_CSCCOEFF2_C3 0 +#define BM_DCP_CSCCOEFF2_C3 0x000003FF +#define BF_DCP_CSCCOEFF2_C3(v) \ + (((v) << 0) & BM_DCP_CSCCOEFF2_C3) + +#define HW_DCP_CSCCLIP (0x000003d0) + +#define BP_DCP_CSCCLIP_RSVD1 24 +#define BM_DCP_CSCCLIP_RSVD1 0xFF000000 +#define BF_DCP_CSCCLIP_RSVD1(v) \ + (((v) << 24) & BM_DCP_CSCCLIP_RSVD1) +#define BP_DCP_CSCCLIP_HEIGHT 12 +#define BM_DCP_CSCCLIP_HEIGHT 0x00FFF000 +#define BF_DCP_CSCCLIP_HEIGHT(v) \ + (((v) << 12) & BM_DCP_CSCCLIP_HEIGHT) +#define BP_DCP_CSCCLIP_WIDTH 0 +#define BM_DCP_CSCCLIP_WIDTH 0x00000FFF +#define BF_DCP_CSCCLIP_WIDTH(v) \ + (((v) << 0) & BM_DCP_CSCCLIP_WIDTH) + +#define HW_DCP_CSCXSCALE (0x000003e0) + +#define BP_DCP_CSCXSCALE_RSVD1 26 +#define BM_DCP_CSCXSCALE_RSVD1 0xFC000000 +#define BF_DCP_CSCXSCALE_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCXSCALE_RSVD1) +#define BP_DCP_CSCXSCALE_INT 24 +#define BM_DCP_CSCXSCALE_INT 0x03000000 +#define BF_DCP_CSCXSCALE_INT(v) \ + (((v) << 24) & BM_DCP_CSCXSCALE_INT) +#define BP_DCP_CSCXSCALE_FRAC 12 +#define BM_DCP_CSCXSCALE_FRAC 0x00FFF000 +#define BF_DCP_CSCXSCALE_FRAC(v) \ + (((v) << 12) & BM_DCP_CSCXSCALE_FRAC) +#define BP_DCP_CSCXSCALE_WIDTH 0 +#define BM_DCP_CSCXSCALE_WIDTH 0x00000FFF +#define BF_DCP_CSCXSCALE_WIDTH(v) \ + (((v) << 0) & BM_DCP_CSCXSCALE_WIDTH) + +#define HW_DCP_CSCYSCALE (0x000003f0) + +#define BP_DCP_CSCYSCALE_RSVD1 26 +#define BM_DCP_CSCYSCALE_RSVD1 0xFC000000 +#define BF_DCP_CSCYSCALE_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCYSCALE_RSVD1) +#define BP_DCP_CSCYSCALE_INT 24 +#define BM_DCP_CSCYSCALE_INT 0x03000000 +#define BF_DCP_CSCYSCALE_INT(v) \ + (((v) << 24) & BM_DCP_CSCYSCALE_INT) +#define BP_DCP_CSCYSCALE_FRAC 12 +#define BM_DCP_CSCYSCALE_FRAC 0x00FFF000 +#define BF_DCP_CSCYSCALE_FRAC(v) \ + (((v) << 12) & BM_DCP_CSCYSCALE_FRAC) +#define BP_DCP_CSCYSCALE_HEIGHT 0 +#define BM_DCP_CSCYSCALE_HEIGHT 0x00000FFF +#define BF_DCP_CSCYSCALE_HEIGHT(v) \ + (((v) << 0) & BM_DCP_CSCYSCALE_HEIGHT) + +#define HW_DCP_DBGSELECT (0x00000400) + +#define BP_DCP_DBGSELECT_RSVD 8 +#define BM_DCP_DBGSELECT_RSVD 0xFFFFFF00 +#define BF_DCP_DBGSELECT_RSVD(v) \ + (((v) << 8) & BM_DCP_DBGSELECT_RSVD) +#define BP_DCP_DBGSELECT_INDEX 0 +#define BM_DCP_DBGSELECT_INDEX 0x000000FF +#define BF_DCP_DBGSELECT_INDEX(v) \ + (((v) << 0) & BM_DCP_DBGSELECT_INDEX) +#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x01 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13 + +#define HW_DCP_DBGDATA (0x00000410) + +#define BP_DCP_DBGDATA_DATA 0 +#define BM_DCP_DBGDATA_DATA 0xFFFFFFFF +#define BF_DCP_DBGDATA_DATA(v) (v) + +#define HW_DCP_PAGETABLE (0x00000420) + +#define BP_DCP_PAGETABLE_BASE 2 +#define BM_DCP_PAGETABLE_BASE 0xFFFFFFFC +#define BF_DCP_PAGETABLE_BASE(v) \ + (((v) << 2) & BM_DCP_PAGETABLE_BASE) +#define BM_DCP_PAGETABLE_FLUSH 0x00000002 +#define BM_DCP_PAGETABLE_ENABLE 0x00000001 + +#define HW_DCP_VERSION (0x00000430) + +#define BP_DCP_VERSION_MAJOR 24 +#define BM_DCP_VERSION_MAJOR 0xFF000000 +#define BF_DCP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_DCP_VERSION_MAJOR) +#define BP_DCP_VERSION_MINOR 16 +#define BM_DCP_VERSION_MINOR 0x00FF0000 +#define BF_DCP_VERSION_MINOR(v) \ + (((v) << 16) & BM_DCP_VERSION_MINOR) +#define BP_DCP_VERSION_STEP 0 +#define BM_DCP_VERSION_STEP 0x0000FFFF +#define BF_DCP_VERSION_STEP(v) \ + (((v) << 0) & BM_DCP_VERSION_STEP) + + +#endif diff --git a/drivers/crypto/dcp_bootstream_ioctl.h b/drivers/crypto/dcp_bootstream_ioctl.h new file mode 100644 index 000000000000..7c0c07d5a72d --- /dev/null +++ b/drivers/crypto/dcp_bootstream_ioctl.h @@ -0,0 +1,32 @@ +/* + * Freescale DCP driver for bootstream update. Only handles the OTP KEY + * case and can only encrypt/decrypt. + * + * Author: Pantelis Antoniou + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef DCP_BOOTSTREAM_IOCTL_H +#define DCP_BOOTSTREAM_IOCTL_H + +/* remember to have included the proper _IO definition + * file before hand. + * For user space it's + */ + +#define DBS_IOCTL_BASE 'd' + +#define DBS_ENC _IOW(DBS_IOCTL_BASE, 0x00, uint8_t[16]) +#define DBS_DEC _IOW(DBS_IOCTL_BASE, 0x01, uint8_t[16]) + +#endif diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 9e01e96fee94..c61e3e305920 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -118,6 +118,15 @@ config MX3_IPU_IRQS To avoid bloating the irq_desc[] array we allocate a sufficient number of IRQ slots and map them dynamically to specific sources. +config MXC_PXP + bool "MXC PxP support" + select DMA_ENGINE + +config MXC_PXP_CLIENT_DEVICE + bool "MXC PxP Client Device" + default y + depends on MXC_PXP + config TXX9_DMAC tristate "Toshiba TXx9 SoC DMA support" depends on MACH_TX49XX || MACH_TX39XX diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 0fe5ebbfda5d..6b9fadeb9bb1 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_MV_XOR) += mv_xor.o obj-$(CONFIG_DW_DMAC) += dw_dmac.o obj-$(CONFIG_AT_HDMAC) += at_hdmac.o obj-$(CONFIG_MX3_IPU) += ipu/ +obj-$(CONFIG_MXC_PXP) += pxp/ obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o obj-$(CONFIG_SH_DMAE) += shdma.o obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o diff --git a/drivers/dma/pxp/Makefile b/drivers/dma/pxp/Makefile new file mode 100644 index 000000000000..88e51a7fb1e2 --- /dev/null +++ b/drivers/dma/pxp/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_MXC_PXP) += pxp_dma.o +obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o diff --git a/drivers/dma/pxp/pxp_device.c b/drivers/dma/pxp/pxp_device.c new file mode 100644 index 000000000000..70b751141f1c --- /dev/null +++ b/drivers/dma/pxp/pxp_device.c @@ -0,0 +1,512 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static atomic_t open_count = ATOMIC_INIT(0); + +static DEFINE_SPINLOCK(pxp_mem_lock); +static DEFINE_SPINLOCK(pxp_chan_lock); +static LIST_HEAD(head); +static LIST_HEAD(list); +static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL]; + +struct pxp_chan_handle { + int chan_id; + int hist_status; +}; + +/* To track the allocated memory buffer */ +struct memalloc_record { + struct list_head list; + struct pxp_mem_desc mem; +}; + +struct pxp_chan_info { + int chan_id; + struct dma_chan *dma_chan; + struct list_head list; +}; + +static int pxp_alloc_dma_buffer(struct pxp_mem_desc *mem) +{ + mem->cpu_addr = (unsigned long) + dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size), + (dma_addr_t *) (&mem->phys_addr), + GFP_DMA | GFP_KERNEL); + pr_debug("[ALLOC] mem alloc phys_addr = 0x%x\n", mem->phys_addr); + if ((void *)(mem->cpu_addr) == NULL) { + printk(KERN_ERR "Physical memory allocation error!\n"); + return -1; + } + return 0; +} + +static void pxp_free_dma_buffer(struct pxp_mem_desc *mem) +{ + if (mem->cpu_addr != 0) { + dma_free_coherent(0, PAGE_ALIGN(mem->size), + (void *)mem->cpu_addr, mem->phys_addr); + } +} + +static int pxp_free_buffers(void) +{ + struct memalloc_record *rec, *n; + struct pxp_mem_desc mem; + + list_for_each_entry_safe(rec, n, &head, list) { + mem = rec->mem; + if (mem.cpu_addr != 0) { + pxp_free_dma_buffer(&mem); + pr_debug("[FREE] freed paddr=0x%08X\n", mem.phys_addr); + /* delete from list */ + list_del(&rec->list); + kfree(rec); + } + } + + return 0; +} + +/* Callback function triggered after PxP receives an EOF interrupt */ +static void pxp_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + int chan_id = pxp_chan->dma_chan.chan_id; + + pr_debug("DMA Done ISR, chan_id %d\n", chan_id); + + irq_info[chan_id].irq_pending++; + irq_info[chan_id].hist_status = tx_desc->hist_status; + + wake_up_interruptible(&(irq_info[chan_id].waitq)); +} + +static int pxp_ioc_config_chan(unsigned long arg) +{ + struct scatterlist sg[3]; + struct pxp_tx_desc *desc; + struct dma_async_tx_descriptor *txd; + struct pxp_chan_info *info; + struct pxp_config_data pxp_conf; + dma_cookie_t cookie; + int chan_id; + int i, length, ret; + + ret = copy_from_user(&pxp_conf, + (struct pxp_config_data *)arg, + sizeof(struct pxp_config_data)); + if (ret) + return -EFAULT; + + chan_id = pxp_conf.chan_id; + if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL) + return -ENODEV; + + init_waitqueue_head(&(irq_info[chan_id].waitq)); + + /* find the channel */ + spin_lock(&pxp_chan_lock); + list_for_each_entry(info, &list, list) { + if (info->dma_chan->chan_id == chan_id) + break; + } + spin_unlock(&pxp_chan_lock); + + sg_init_table(sg, 3); + + txd = + info->dma_chan->device->device_prep_slave_sg(info->dma_chan, + sg, 3, + DMA_TO_DEVICE, + DMA_PREP_INTERRUPT); + if (!txd) { + pr_err("Error preparing a DMA transaction descriptor.\n"); + return -EIO; + } + + txd->callback_param = txd; + txd->callback = pxp_dma_done; + + desc = to_tx_desc(txd); + + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) { /* S0 */ + memcpy(&desc->proc_data, + &pxp_conf.proc_data, + sizeof(struct pxp_proc_data)); + memcpy(&desc->layer_param.s0_param, + &pxp_conf.s0_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { /* Output */ + memcpy(&desc->layer_param.out_param, + &pxp_conf.out_param, + sizeof(struct pxp_layer_param)); + } else { + /* OverLay */ + memcpy(&desc->layer_param.ol_param, + &pxp_conf.ol_param, + sizeof(struct pxp_layer_param)); + } + + desc = desc->next; + } + + cookie = txd->tx_submit(txd); + if (cookie < 0) { + pr_err("Error tx_submit\n"); + return -EIO; + } + + return 0; +} + +static int pxp_device_open(struct inode *inode, struct file *filp) +{ + atomic_inc(&open_count); + + return 0; +} + +static int pxp_device_release(struct inode *inode, struct file *filp) +{ + if (atomic_dec_and_test(&open_count)) + pxp_free_buffers(); + + return 0; +} + +static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct memalloc_record *rec, *n; + int request_size, found; + + request_size = vma->vm_end - vma->vm_start; + found = 0; + + pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n", + (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff), + request_size); + + spin_lock(&pxp_mem_lock); + list_for_each_entry_safe(rec, n, &head, list) { + if (rec->mem.phys_addr == (vma->vm_pgoff << PAGE_SHIFT) && + (rec->mem.size <= request_size)) { + found = 1; + break; + } + } + spin_unlock(&pxp_mem_lock); + + if (found == 0) + return -ENOMEM; + + vma->vm_flags |= VM_IO | VM_RESERVED; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + request_size, vma->vm_page_prot) ? -EAGAIN : 0; +} + +static int pxp_device_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + + switch (cmd) { + case PXP_IOC_GET_CHAN: + { + struct pxp_chan_info *info; + dma_cap_mask_t mask; + + pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__); + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + pr_err("%d: alloc err\n", __LINE__); + return -ENOMEM; + } + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + info->dma_chan = dma_request_channel(mask, NULL, NULL); + if (!info->dma_chan) { + pr_err("Unsccessfully received channel!\n"); + kfree(info); + return -EBUSY; + } + pr_debug("Successfully received channel." + "chan_id %d\n", info->dma_chan->chan_id); + + spin_lock(&pxp_chan_lock); + list_add_tail(&info->list, &list); + spin_unlock(&pxp_chan_lock); + + if (put_user + (info->dma_chan->chan_id, (u32 __user *) arg)) + return -EFAULT; + + break; + } + case PXP_IOC_PUT_CHAN: + { + int chan_id; + struct pxp_chan_info *info; + + if (get_user(chan_id, (u32 __user *) arg)) + return -EFAULT; + + if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL) + return -ENODEV; + + spin_lock(&pxp_chan_lock); + list_for_each_entry(info, &list, list) { + if (info->dma_chan->chan_id == chan_id) + break; + } + spin_unlock(&pxp_chan_lock); + + pr_debug("%d release chan_id %d\n", __LINE__, + info->dma_chan->chan_id); + /* REVISIT */ + dma_release_channel(info->dma_chan); + spin_lock(&pxp_chan_lock); + list_del_init(&info->list); + spin_unlock(&pxp_chan_lock); + kfree(info); + + break; + } + case PXP_IOC_CONFIG_CHAN: + { + + int ret; + + ret = pxp_ioc_config_chan(arg); + if (ret) + return ret; + + break; + } + case PXP_IOC_START_CHAN: + { + struct pxp_chan_info *info; + int chan_id; + + if (get_user(chan_id, (u32 __user *) arg)) + return -EFAULT; + + /* find the channel */ + spin_lock(&pxp_chan_lock); + list_for_each_entry(info, &list, list) { + if (info->dma_chan->chan_id == chan_id) + break; + } + spin_unlock(&pxp_chan_lock); + + dma_async_issue_pending(info->dma_chan); + + break; + } + case PXP_IOC_GET_PHYMEM: + { + struct memalloc_record *rec; + + rec = kzalloc(sizeof(*rec), GFP_KERNEL); + if (!rec) + return -ENOMEM; + + ret = copy_from_user(&(rec->mem), + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) { + kfree(rec); + return -EFAULT; + } + + pr_debug("[ALLOC] mem alloc size = 0x%x\n", + rec->mem.size); + + ret = pxp_alloc_dma_buffer(&(rec->mem)); + if (ret == -1) { + kfree(rec); + printk(KERN_ERR + "Physical memory allocation error!\n"); + break; + } + ret = copy_to_user((void __user *)arg, &(rec->mem), + sizeof(struct pxp_mem_desc)); + if (ret) { + kfree(rec); + ret = -EFAULT; + break; + } + + spin_lock(&pxp_mem_lock); + list_add(&rec->list, &head); + spin_unlock(&pxp_mem_lock); + + break; + } + case PXP_IOC_PUT_PHYMEM: + { + struct memalloc_record *rec, *n; + struct pxp_mem_desc pxp_mem; + + ret = copy_from_user(&pxp_mem, + (struct pxp_mem_desc *)arg, + sizeof(struct pxp_mem_desc)); + if (ret) + return -EACCES; + + pr_debug("[FREE] mem freed cpu_addr = 0x%x\n", + pxp_mem.cpu_addr); + if ((void *)pxp_mem.cpu_addr != NULL) + pxp_free_dma_buffer(&pxp_mem); + + spin_lock(&pxp_mem_lock); + list_for_each_entry_safe(rec, n, &head, list) { + if (rec->mem.cpu_addr == pxp_mem.cpu_addr) { + /* delete from list */ + list_del(&rec->list); + kfree(rec); + break; + } + } + spin_unlock(&pxp_mem_lock); + + break; + } + case PXP_IOC_WAIT4CMPLT: + { + struct pxp_chan_handle chan_handle; + int ret, chan_id; + + ret = copy_from_user(&chan_handle, + (struct pxp_chan_handle *)arg, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + + chan_id = chan_handle.chan_id; + if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL) + return -ENODEV; + + if (!wait_event_interruptible_timeout + (irq_info[chan_id].waitq, + (irq_info[chan_id].irq_pending != 0), 2 * HZ)) { + pr_warning("pxp blocking: timeout.\n"); + return -ETIME; + } else if (signal_pending(current)) { + printk(KERN_WARNING + "pxp interrupt received.\n"); + return -ERESTARTSYS; + } else + irq_info[chan_id].irq_pending--; + + chan_handle.hist_status = irq_info[chan_id].hist_status; + ret = copy_to_user((struct pxp_chan_handle *)arg, + &chan_handle, + sizeof(struct pxp_chan_handle)); + if (ret) + return -EFAULT; + break; + } + default: + break; + } + + return 0; +} + +static const struct file_operations pxp_device_fops = { + .open = pxp_device_open, + .release = pxp_device_release, + .ioctl = pxp_device_ioctl, + .mmap = pxp_device_mmap, +}; + +static struct miscdevice pxp_device_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "pxp_device", + .fops = &pxp_device_fops, +}; + +static int __devinit pxp_device_probe(struct platform_device *pdev) +{ + int ret; + + /* PxP DMA interface */ + dmaengine_get(); + + ret = misc_register(&pxp_device_miscdev); + if (ret) + return ret; + + pr_debug("PxP_Device Probe Successfully\n"); + return 0; +} + +static int __devexit pxp_device_remove(struct platform_device *pdev) +{ + misc_deregister(&pxp_device_miscdev); + + dmaengine_put(); + + return 0; +} + +static struct platform_driver pxp_client_driver = { + .probe = pxp_device_probe, + .remove = __exit_p(pxp_device_remove), + .driver = { + .name = "pxp-device", + .owner = THIS_MODULE, + }, +}; + +static int __init pxp_device_init(void) +{ + return platform_driver_register(&pxp_client_driver); +} + +static void __exit pxp_device_exit(void) +{ + platform_driver_unregister(&pxp_client_driver); +} + +module_init(pxp_device_init); +module_exit(pxp_device_exit); + +MODULE_DESCRIPTION("i.MX PxP client driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/pxp_dma.c b/drivers/dma/pxp/pxp_dma.c new file mode 100644 index 000000000000..fb43e27bb358 --- /dev/null +++ b/drivers/dma/pxp/pxp_dma.c @@ -0,0 +1,1520 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs-pxp.h" + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +static LIST_HEAD(head); +static int timeout_in_ms = 600; + +struct pxp_dma { + struct dma_device dma; +}; + +struct pxps { + struct platform_device *pdev; + struct clk *clk; + void __iomem *base; + int irq; /* PXP IRQ to the CPU */ + + spinlock_t lock; + struct mutex clk_mutex; + int clk_stat; +#define CLK_STAT_OFF 0 +#define CLK_STAT_ON 1 + int pxp_ongoing; + int lut_state; + + struct device *dev; + struct pxp_dma pxp_dma; + struct pxp_channel channel[NR_PXP_VIRT_CHANNEL]; + wait_queue_head_t done; + struct work_struct work; + + /* describes most recent processing configuration */ + struct pxp_config_data pxp_conf_state; + + /* to turn clock off when pxp is inactive */ + struct timer_list clk_timer; +}; + +#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma) +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) +#define to_pxp(id) container_of(id, struct pxps, pxp_dma) + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +#define PXP_WAITCON ((__raw_readl(pxp->base + HW_PXP_STAT) & \ + BM_PXP_STAT_IRQ) != BM_PXP_STAT_IRQ) + +static uint32_t pxp_s0_formats[] = { + PXP_PIX_FMT_RGB24, + PXP_PIX_FMT_RGB565, + PXP_PIX_FMT_RGB555, + PXP_PIX_FMT_YUV420P, + PXP_PIX_FMT_YUV422P, +}; + +/* + * PXP common functions + */ +static void dump_pxp_reg(struct pxps *pxp) +{ + dev_dbg(pxp->dev, "PXP_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CTRL)); + dev_dbg(pxp->dev, "PXP_STAT 0x%x", + __raw_readl(pxp->base + HW_PXP_STAT)); + dev_dbg(pxp->dev, "PXP_OUTBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_OUTBUF)); + dev_dbg(pxp->dev, "PXP_OUTBUF2 0x%x", + __raw_readl(pxp->base + HW_PXP_OUTBUF2)); + dev_dbg(pxp->dev, "PXP_OUTSIZE 0x%x", + __raw_readl(pxp->base + HW_PXP_OUTSIZE)); + dev_dbg(pxp->dev, "PXP_S0BUF 0x%x", + __raw_readl(pxp->base + HW_PXP_S0BUF)); + dev_dbg(pxp->dev, "PXP_S0UBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_S0UBUF)); + dev_dbg(pxp->dev, "PXP_S0VBUF 0x%x", + __raw_readl(pxp->base + HW_PXP_S0VBUF)); + dev_dbg(pxp->dev, "PXP_S0PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_S0PARAM)); + dev_dbg(pxp->dev, "PXP_S0BACKGROUND 0x%x", + __raw_readl(pxp->base + HW_PXP_S0BACKGROUND)); + dev_dbg(pxp->dev, "PXP_S0CROP 0x%x", + __raw_readl(pxp->base + HW_PXP_S0CROP)); + dev_dbg(pxp->dev, "PXP_S0SCALE 0x%x", + __raw_readl(pxp->base + HW_PXP_S0SCALE)); + dev_dbg(pxp->dev, "PXP_OLn 0x%x", + __raw_readl(pxp->base + HW_PXP_OLn(0))); + dev_dbg(pxp->dev, "PXP_OLnSIZE 0x%x", + __raw_readl(pxp->base + HW_PXP_OLnSIZE(0))); + dev_dbg(pxp->dev, "PXP_OLnPARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_OLnPARAM(0))); + dev_dbg(pxp->dev, "PXP_CSCCOEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSCCOEF0)); + dev_dbg(pxp->dev, "PXP_CSCCOEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSCCOEF1)); + dev_dbg(pxp->dev, "PXP_CSCCOEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSCCOEF2)); + dev_dbg(pxp->dev, "PXP_CSC2CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2CTRL)); + dev_dbg(pxp->dev, "PXP_CSC2COEF0 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF0)); + dev_dbg(pxp->dev, "PXP_CSC2COEF1 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF1)); + dev_dbg(pxp->dev, "PXP_CSC2COEF2 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF2)); + dev_dbg(pxp->dev, "PXP_CSC2COEF3 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF3)); + dev_dbg(pxp->dev, "PXP_CSC2COEF4 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF4)); + dev_dbg(pxp->dev, "PXP_CSC2COEF5 0x%x", + __raw_readl(pxp->base + HW_PXP_CSC2COEF5)); + dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_LUT_CTRL)); + dev_dbg(pxp->dev, "PXP_LUT 0x%x", __raw_readl(pxp->base + HW_PXP_LUT)); + dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST_CTRL)); + dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST2_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST4_PARAM)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2)); + dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x", + __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3)); +} + +static bool is_yuv(u32 pix_fmt) +{ + if ((pix_fmt == PXP_PIX_FMT_YUYV) | + (pix_fmt == PXP_PIX_FMT_UYVY) | + (pix_fmt == PXP_PIX_FMT_Y41P) | + (pix_fmt == PXP_PIX_FMT_YUV444) | + (pix_fmt == PXP_PIX_FMT_NV12) | + (pix_fmt == PXP_PIX_FMT_GREY) | + (pix_fmt == PXP_PIX_FMT_YVU410P) | + (pix_fmt == PXP_PIX_FMT_YUV410P) | + (pix_fmt == PXP_PIX_FMT_YVU420P) | + (pix_fmt == PXP_PIX_FMT_YUV420P) | + (pix_fmt == PXP_PIX_FMT_YUV420P2) | + (pix_fmt == PXP_PIX_FMT_YVU422P) | + (pix_fmt == PXP_PIX_FMT_YUV422P)) { + return true; + } else { + return false; + } +} + +static void pxp_set_ctrl(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 ctrl; + u32 fmt_ctrl; + + /* Configure S0 input format */ + switch (pxp_conf->s0_param.pixel_fmt) { + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV420; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV422; + break; + default: + fmt_ctrl = 0; + } + ctrl = BF_PXP_CTRL_S0_FORMAT(fmt_ctrl); + + /* Configure output format based on out_channel format */ + switch (pxp_conf->out_param.pixel_fmt) { + case PXP_PIX_FMT_RGB24: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB888; + break; + case PXP_PIX_FMT_RGB565: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB565; + break; + case PXP_PIX_FMT_RGB555: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__RGB555; + break; + case PXP_PIX_FMT_YUV420P: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420; + break; + case PXP_PIX_FMT_YUV422P: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422; + break; + case PXP_PIX_FMT_GREY: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8; + break; + default: + fmt_ctrl = 0; + } + ctrl |= BF_PXP_CTRL_OUTBUF_FORMAT(fmt_ctrl); + + ctrl |= BM_PXP_CTRL_CROP; + + if (proc_data->scaling) + ctrl |= BM_PXP_CTRL_SCALE; + if (proc_data->vflip) + ctrl |= BM_PXP_CTRL_VFLIP; + if (proc_data->hflip) + ctrl |= BM_PXP_CTRL_HFLIP; + if (proc_data->rotate) + ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90); + + __raw_writel(ctrl, pxp->base + HW_PXP_CTRL); +} + +static int pxp_start(struct pxps *pxp) +{ + __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET); + __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET); + + return 0; +} + +static void pxp_set_outbuf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUTBUF); + + __raw_writel(BF_PXP_OUTSIZE_WIDTH(out_params->width) | + BF_PXP_OUTSIZE_HEIGHT(out_params->height), + pxp->base + HW_PXP_OUTSIZE); +} + +static void pxp_set_s0colorkey(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (s0_params->color_key == -1) { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_S0COLORKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_S0COLORKEYHIGH); + } else { + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_S0COLORKEYLOW); + __raw_writel(s0_params->color_key, + pxp->base + HW_PXP_S0COLORKEYHIGH); + } +} + +static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no]; + + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) { + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_OLCOLORKEYLOW); + __raw_writel(ol_params->color_key, + pxp->base + HW_PXP_OLCOLORKEYHIGH); + } else { + /* disable color key */ + __raw_writel(0xFFFFFF, pxp->base + HW_PXP_OLCOLORKEYLOW); + __raw_writel(0, pxp->base + HW_PXP_OLCOLORKEYHIGH); + } +} + +static void pxp_set_oln(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + dma_addr_t phys_addr = olparams_data->paddr; + __raw_writel(phys_addr, pxp->base + HW_PXP_OLn(layer_no)); + + /* Fixme */ + __raw_writel(BF_PXP_OLnSIZE_WIDTH(olparams_data->width >> 3) | + BF_PXP_OLnSIZE_HEIGHT(olparams_data->height >> 3), + pxp->base + HW_PXP_OLnSIZE(layer_no)); +} + +static void pxp_set_olparam(int layer_no, struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no]; + u32 olparam; + + olparam = BF_PXP_OLnPARAM_ALPHA(olparams_data->global_alpha); + if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB24) + olparam |= + BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB888); + else + olparam |= + BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB565); + if (olparams_data->global_alpha_enable) + olparam |= + BF_PXP_OLnPARAM_ALPHA_CNTL + (BV_PXP_OLnPARAM_ALPHA_CNTL__Override); + if (olparams_data->color_key_enable) + olparam |= BM_PXP_OLnPARAM_ENABLE_COLORKEY; + if (olparams_data->combine_enable) + olparam |= BM_PXP_OLnPARAM_ENABLE; + __raw_writel(olparam, pxp->base + HW_PXP_OLnPARAM(layer_no)); +} + +static void pxp_set_s0param(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0params_data = &pxp_conf->s0_param; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 s0param; + + s0param = BF_PXP_S0PARAM_XBASE(proc_data->drect.left >> 3); + s0param |= BF_PXP_S0PARAM_YBASE(proc_data->drect.top >> 3); + s0param |= BF_PXP_S0PARAM_WIDTH(s0params_data->width >> 3); + s0param |= BF_PXP_S0PARAM_HEIGHT(s0params_data->height >> 3); + __raw_writel(s0param, pxp->base + HW_PXP_S0PARAM); +} + +static void pxp_set_s0crop(struct pxps *pxp) +{ + u32 s0crop; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + + s0crop = BF_PXP_S0CROP_XBASE(proc_data->srect.left >> 3); + s0crop |= BF_PXP_S0CROP_YBASE(proc_data->srect.top >> 3); + s0crop |= BF_PXP_S0CROP_WIDTH(proc_data->drect.width >> 3); + s0crop |= BF_PXP_S0CROP_HEIGHT(proc_data->drect.height >> 3); + __raw_writel(s0crop, pxp->base + HW_PXP_S0CROP); +} + +static int pxp_set_scaling(struct pxps *pxp) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data; + struct pxp_layer_param *s0params_data = &pxp->pxp_conf_state.s0_param; + + if ((s0params_data->pixel_fmt != PXP_PIX_FMT_YUV420P) && + (s0params_data->pixel_fmt != PXP_PIX_FMT_YUV422P)) { + proc_data->scaling = 0; + ret = -EINVAL; + goto out; + } + + if ((proc_data->srect.width == proc_data->drect.width) && + (proc_data->srect.height == proc_data->drect.height)) { + proc_data->scaling = 0; + __raw_writel(0x10001000, pxp->base + HW_PXP_S0SCALE); + goto out; + } + + proc_data->scaling = 1; + xscale = proc_data->srect.width * 0x1000 / proc_data->drect.width; + yscale = proc_data->srect.height * 0x1000 / proc_data->drect.height; + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_S0SCALE_YSCALE(yscale) | BF_PXP_S0SCALE_XSCALE(xscale); + __raw_writel(s0scale, pxp->base + HW_PXP_S0SCALE); + +out: + pxp_set_ctrl(pxp); + + return ret; +} + +static void pxp_set_bg(struct pxps *pxp) +{ + __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor, + pxp->base + HW_PXP_S0BACKGROUND); +} + +static void pxp_set_lut(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + int lut_op = pxp_conf->proc_data.lut_transform; + u32 reg_val; + int i; + + /* If LUT already configured as needed, return */ + if (pxp->lut_state == lut_op) + return; + + if (lut_op == PXP_LUT_NONE) { + __raw_writel(BM_PXP_LUT_CTRL_BYPASS, + pxp->base + HW_PXP_LUT_CTRL); + } else if (((lut_op & PXP_LUT_INVERT) != 0) + && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) { + /* Fill out LUT table with inverted monochromized values */ + + /* Initialize LUT address to 0 and clear bypass bit */ + __raw_writel(0, pxp->base + HW_PXP_LUT_CTRL); + + /* LUT address pointer auto-increments after each data write */ + for (i = 0; i < 256; i++) { + reg_val = + __raw_readl(pxp->base + + HW_PXP_LUT_CTRL) & BM_PXP_LUT_CTRL_ADDR; + reg_val = (reg_val < 0x80) ? 0x00 : 0xFF; + reg_val = ~reg_val & BM_PXP_LUT_DATA; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT); + } + } else if (lut_op == PXP_LUT_INVERT) { + /* Fill out LUT table with 8-bit inverted values */ + + /* Initialize LUT address to 0 and clear bypass bit */ + __raw_writel(0, pxp->base + HW_PXP_LUT_CTRL); + + /* LUT address pointer auto-increments after each data write */ + for (i = 0; i < 256; i++) { + reg_val = + __raw_readl(pxp->base + + HW_PXP_LUT_CTRL) & BM_PXP_LUT_CTRL_ADDR; + reg_val = ~reg_val & BM_PXP_LUT_DATA; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT); + } + } else if (lut_op == PXP_LUT_BLACK_WHITE) { + /* Fill out LUT table with 8-bit monochromized values */ + + /* Initialize LUT address to 0 and clear bypass bit */ + __raw_writel(0, pxp->base + HW_PXP_LUT_CTRL); + + /* LUT address pointer auto-increments after each data write */ + for (i = 0; i < 256; i++) { + reg_val = + __raw_readl(pxp->base + + HW_PXP_LUT_CTRL) & BM_PXP_LUT_CTRL_ADDR; + reg_val = (reg_val < 0x80) ? 0xFF : 0x00; + reg_val = ~reg_val & BM_PXP_LUT_DATA; + __raw_writel(reg_val, pxp->base + HW_PXP_LUT); + } + } + + pxp->lut_state = lut_op; +} + +static void pxp_set_csc(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0]; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + + bool input_is_YUV = is_yuv(s0_params->pixel_fmt); + bool output_is_YUV = is_yuv(out_params->pixel_fmt); + + if (input_is_YUV && output_is_YUV) { + /* + * Input = YUV, Output = YUV + * No CSC unless we need to do combining + */ + if (ol_params->combine_enable) { + /* Must convert to RGB for combining with RGB overlay */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x04030000, pxp->base + HW_PXP_CSCCOEF0); + __raw_writel(0x01230208, pxp->base + HW_PXP_CSCCOEF1); + __raw_writel(0x076b079c, pxp->base + HW_PXP_CSCCOEF2); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2COEF5); + } else { + /* Input & Output both YUV, so bypass both CSCs */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL); + } + } else if (input_is_YUV && !output_is_YUV) { + /* + * Input = YUV, Output = RGB + * Use CSC1 to convert to RGB + */ + + /* CSC1 - YUV->RGB */ + __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSCCOEF0); + __raw_writel(0x01230204, pxp->base + HW_PXP_CSCCOEF1); + __raw_writel(0x0730079c, pxp->base + HW_PXP_CSCCOEF2); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL); + } else if (!input_is_YUV && output_is_YUV) { + /* + * Input = RGB, Output = YUV + * Use CSC2 to convert to YUV + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0); + + /* CSC2 - RGB->YUV */ + __raw_writel(0x4, pxp->base + HW_PXP_CSC2CTRL); + __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2COEF0); + __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2COEF1); + __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2COEF2); + __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2COEF3); + __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2COEF4); + __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2COEF5); + } else { + /* + * Input = RGB, Output = RGB + * Input & Output both RGB, so bypass both CSCs + */ + + /* CSC1 - Bypass */ + __raw_writel(0x40000000, pxp->base + HW_PXP_CSCCOEF0); + + /* CSC2 - Bypass */ + __raw_writel(0x1, pxp->base + HW_PXP_CSC2CTRL); + } + + /* YCrCb colorspace */ + /* Not sure when we use this...no YCrCb formats are defined for PxP */ + /* + __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR); + __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR); + __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR); + */ + +} + +static void pxp_set_s0buf(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + dma_addr_t Y, U, V; + + Y = s0_params->paddr; + __raw_writel(Y, pxp->base + HW_PXP_S0BUF); + if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) || + (s0_params->pixel_fmt == PXP_PIX_FMT_GREY)) { + /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */ + int s = 2; + U = Y + (s0_params->width * s0_params->height); + V = U + ((s0_params->width * s0_params->height) >> s); + __raw_writel(U, pxp->base + HW_PXP_S0UBUF); + __raw_writel(V, pxp->base + HW_PXP_S0VBUF); + } +} + +/** + * pxp_config() - configure PxP for a processing task + * @pxps: PXP context. + * @pxp_chan: PXP channel. + * @return: 0 on success or negative error code on failure. + */ +static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan) +{ + struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state; + int ol_nr; + int i; + + /* Configure PxP regs */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + ol_nr = pxp_conf_data->layer_nr - 2; + while (ol_nr > 0) { + i = pxp_conf_data->layer_nr - 2 - ol_nr; + pxp_set_oln(i, pxp); + pxp_set_olparam(i, pxp); + /* only the color key in higher overlay will take effect. */ + pxp_set_olcolorkey(i, pxp); + ol_nr--; + } + pxp_set_s0colorkey(pxp); + pxp_set_csc(pxp); + pxp_set_bg(pxp); + pxp_set_lut(pxp); + + pxp_set_s0buf(pxp); + pxp_set_outbuf(pxp); + + return 0; +} + +static void pxp_clk_enable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_ON) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + clk_enable(pxp->clk); + pxp->clk_stat = CLK_STAT_ON; + + mutex_unlock(&pxp->clk_mutex); +} + +static void pxp_clk_disable(struct pxps *pxp) +{ + mutex_lock(&pxp->clk_mutex); + + if (pxp->clk_stat == CLK_STAT_OFF) { + mutex_unlock(&pxp->clk_mutex); + return; + } + + clk_disable(pxp->clk); + pxp->clk_stat = CLK_STAT_OFF; + + mutex_unlock(&pxp->clk_mutex); +} + +static inline void clkoff_callback(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + + pxp_clk_disable(pxp); +} + +static void pxp_clkoff_timer(unsigned long arg) +{ + struct pxps *pxp = (struct pxps *)arg; + + if ((pxp->pxp_ongoing == 0) && list_empty(&head)) + schedule_work(&pxp->work); + else + mod_timer(&pxp->clk_timer, + jiffies + msecs_to_jiffies(timeout_in_ms)); +} + +static struct pxp_tx_desc *pxpdma_first_active(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->active_list.next, struct pxp_tx_desc, list); +} + +static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan) +{ + return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list); +} + +/* called with pxp_chan->lock held */ +static void __pxpdma_dostart(struct pxp_channel *pxp_chan) +{ + struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *desc; + struct pxp_tx_desc *child; + int i = 0; + + /* so far we presume only one transaction on active_list */ + /* S0 */ + desc = pxpdma_first_active(pxp_chan); + memcpy(&pxp->pxp_conf_state.s0_param, + &desc->layer_param.s0_param, sizeof(struct pxp_layer_param)); + memcpy(&pxp->pxp_conf_state.proc_data, + &desc->proc_data, sizeof(struct pxp_proc_data)); + + /* Save PxP configuration */ + list_for_each_entry(child, &desc->tx_list, list) { + if (i == 0) { /* Output */ + memcpy(&pxp->pxp_conf_state.out_param, + &child->layer_param.out_param, + sizeof(struct pxp_layer_param)); + } else { /* Overlay */ + memcpy(&pxp->pxp_conf_state.ol_param[i - 1], + &child->layer_param.ol_param, + sizeof(struct pxp_layer_param)); + } + + i++; + } + pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.s0_param.width, + pxp->pxp_conf_state.s0_param.height, + pxp->pxp_conf_state.s0_param.paddr); + pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__, + pxp->pxp_conf_state.out_param.width, + pxp->pxp_conf_state.out_param.height, + pxp->pxp_conf_state.out_param.paddr); +} + +static void pxpdma_dostart_work(struct pxps *pxp) +{ + struct pxp_channel *pxp_chan = NULL; + unsigned long flags, flags1; + + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + spin_lock_irqsave(&pxp->lock, flags); + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return; + } + + pxp_chan = list_entry(head.next, struct pxp_channel, list); + + spin_lock_irqsave(&pxp_chan->lock, flags1); + if (!list_empty(&pxp_chan->active_list)) { + struct pxp_tx_desc *desc; + /* REVISIT */ + desc = pxpdma_first_active(pxp_chan); + __pxpdma_dostart(pxp_chan); + } + spin_unlock_irqrestore(&pxp_chan->lock, flags1); + + /* Configure PxP */ + pxp_config(pxp, pxp_chan); + + pxp_start(pxp); + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct list_head *list) +{ + struct pxp_tx_desc *desc = NULL; + do { + desc = pxpdma_first_queued(pxp_chan); + list_move_tail(&desc->list, list); + } while (!list_empty(&pxp_chan->queue)); +} + +static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct pxp_tx_desc *desc = to_tx_desc(tx); + struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan); + dma_cookie_t cookie; + unsigned long flags; + + dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n"); + + mutex_lock(&pxp_chan->chan_mutex); + + cookie = pxp_chan->dma_chan.cookie; + + if (++cookie < 0) + cookie = 1; + + /* from dmaengine.h: "last cookie value returned to client" */ + pxp_chan->dma_chan.cookie = cookie; + tx->cookie = cookie; + + /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */ + spin_lock_irqsave(&pxp_chan->lock, flags); + + /* Here we add the tx descriptor to our PxP task queue. */ + list_add_tail(&desc->list, &pxp_chan->queue); + + spin_unlock_irqrestore(&pxp_chan->lock, flags); + + dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n"); + + mutex_unlock(&pxp_chan->chan_mutex); + return cookie; +} + +/* Called with pxp_chan->chan_mutex held */ +static int pxp_desc_alloc(struct pxp_channel *pxp_chan, int n) +{ + struct pxp_tx_desc *desc = vmalloc(n * sizeof(struct pxp_tx_desc)); + + if (!desc) + return -ENOMEM; + + pxp_chan->n_tx_desc = n; + pxp_chan->desc = desc; + INIT_LIST_HEAD(&pxp_chan->active_list); + INIT_LIST_HEAD(&pxp_chan->queue); + INIT_LIST_HEAD(&pxp_chan->free_list); + + while (n--) { + struct dma_async_tx_descriptor *txd = &desc->txd; + + memset(txd, 0, sizeof(*txd)); + INIT_LIST_HEAD(&desc->tx_list); + dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan); + txd->tx_submit = pxp_tx_submit; + + list_add(&desc->list, &pxp_chan->free_list); + + desc++; + } + + return 0; +} + +/** + * pxp_init_channel() - initialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_init_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + unsigned long flags; + struct pxps *pxp = to_pxp(pxp_dma); + int ret = 0, n_desc = 0; + + /* + * We are using _virtual_ channel here. + * Each channel contains all parameters of corresponding layers + * for one transaction; each layer is represented as one descriptor + * (i.e., pxp_tx_desc) here. + */ + + spin_lock_irqsave(&pxp->lock, flags); + + /* max desc nr: S0+OL+OUT = 1+8+1 */ + n_desc = 16; + + spin_unlock_irqrestore(&pxp->lock, flags); + + if (n_desc && !pxp_chan->desc) + ret = pxp_desc_alloc(pxp_chan, n_desc); + + return ret; +} + +/** + * pxp_uninit_channel() - uninitialize a PXP channel. + * @pxp_dma: PXP DMA context. + * @pchan: pointer to the channel object. + * @return 0 on success or negative error code on failure. + */ +static int pxp_uninit_channel(struct pxp_dma *pxp_dma, + struct pxp_channel *pxp_chan) +{ + int ret = 0; + + if (pxp_chan->desc) + vfree(pxp_chan->desc); + + pxp_chan->desc = NULL; + + return ret; +} + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = dev_id; + struct pxp_channel *pxp_chan; + struct pxp_tx_desc *desc; + dma_async_tx_callback callback; + void *callback_param; + unsigned long flags; + u32 hist_status; + + dump_pxp_reg(pxp); + + hist_status = + __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS; + + __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR); + + spin_lock_irqsave(&pxp->lock, flags); + + if (list_empty(&head)) { + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + pxp_chan = list_entry(head.next, struct pxp_channel, list); + list_del_init(&pxp_chan->list); + + if (list_empty(&pxp_chan->active_list)) { + pr_debug("PXP_IRQ pxp_chan->active_list empty. chan_id %d\n", + pxp_chan->dma_chan.chan_id); + pxp->pxp_ongoing = 0; + spin_unlock_irqrestore(&pxp->lock, flags); + return IRQ_NONE; + } + + /* Get descriptor and call callback */ + desc = pxpdma_first_active(pxp_chan); + + pxp_chan->completed = desc->txd.cookie; + + callback = desc->txd.callback; + callback_param = desc->txd.callback_param; + + /* Send histogram status back to caller */ + desc->hist_status = hist_status; + + if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback) + callback(callback_param); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + list_splice_init(&desc->tx_list, &pxp_chan->free_list); + list_move(&desc->list, &pxp_chan->free_list); + + wake_up(&pxp->done); + pxp->pxp_ongoing = 0; + mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms)); + + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +/* called with pxp_chan->lock held */ +static struct pxp_tx_desc *pxpdma_desc_get(struct pxp_channel *pxp_chan) +{ + struct pxp_tx_desc *desc, *_desc; + struct pxp_tx_desc *ret = NULL; + + list_for_each_entry_safe(desc, _desc, &pxp_chan->free_list, list) { + list_del_init(&desc->list); + ret = desc; + break; + } + + return ret; +} + +/* called with pxp_chan->lock held */ +static void pxpdma_desc_put(struct pxp_channel *pxp_chan, + struct pxp_tx_desc *desc) +{ + if (desc) { + struct device *dev = &pxp_chan->dma_chan.dev->device; + struct pxp_tx_desc *child; + unsigned long flags; + + list_for_each_entry(child, &desc->tx_list, list) + dev_info(dev, "moving child desc %p to freelist\n", child); + list_splice_init(&desc->tx_list, &pxp_chan->free_list); + dev_info(dev, "moving desc %p to freelist\n", desc); + list_add(&desc->list, &pxp_chan->free_list); + } +} + +/* Allocate and initialise a transfer descriptor. */ +static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan, + struct scatterlist + *sgl, + unsigned int sg_len, + enum dma_data_direction + direction, + unsigned long tx_flags) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + struct pxp_tx_desc *desc = NULL; + struct pxp_tx_desc *first = NULL, *prev = NULL; + struct scatterlist *sg; + unsigned long flags; + dma_addr_t phys_addr; + int i; + + if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) { + dev_err(chan->device->dev, "Invalid DMA direction %d!\n", + direction); + return NULL; + } + + if (unlikely(sg_len < 2)) + return NULL; + + spin_lock_irqsave(&pxp_chan->lock, flags); + for_each_sg(sgl, sg, sg_len, i) { + desc = pxpdma_desc_get(pxp_chan); + if (!desc) { + pxpdma_desc_put(pxp_chan, first); + dev_err(chan->device->dev, "Can't get DMA desc.\n"); + spin_unlock_irqrestore(&pxp_chan->lock, flags); + return NULL; + } + + phys_addr = sg_dma_address(sg); + + if (!first) { + first = desc; + + desc->layer_param.s0_param.paddr = phys_addr; + } else { + list_add_tail(&desc->list, &first->tx_list); + prev->next = desc; + desc->next = NULL; + + if (i == 1) + desc->layer_param.out_param.paddr = phys_addr; + else + desc->layer_param.ol_param.paddr = phys_addr; + } + + prev = desc; + } + spin_unlock_irqrestore(&pxp_chan->lock, flags); + + pxp->pxp_conf_state.layer_nr = sg_len; + first->txd.flags = tx_flags; + first->len = sg_len; + pr_debug("%s:%d first %p, first->len %d, flags %08x\n", + __func__, __LINE__, first, first->len, first->txd.flags); + + return &first->txd; +} + +static void pxp_issue_pending(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + struct pxps *pxp = to_pxp(pxp_dma); + unsigned long flags0, flags; + + spin_lock_irqsave(&pxp->lock, flags0); + spin_lock_irqsave(&pxp_chan->lock, flags); + + if (!list_empty(&pxp_chan->queue)) { + pxpdma_dequeue(pxp_chan, &pxp_chan->active_list); + pxp_chan->status = PXP_CHANNEL_READY; + list_add_tail(&pxp_chan->list, &head); + } else { + spin_unlock_irqrestore(&pxp_chan->lock, flags); + spin_unlock_irqrestore(&pxp->lock, flags0); + return; + } + spin_unlock_irqrestore(&pxp_chan->lock, flags); + spin_unlock_irqrestore(&pxp->lock, flags0); + + pxp_clk_enable(pxp); + if (!wait_event_interruptible_timeout(pxp->done, PXP_WAITCON, 2 * HZ) || + signal_pending(current)) { + pxp_clk_disable(pxp); + return; + } + + pxp->pxp_ongoing = 1; + pxpdma_dostart_work(pxp); +} + +static void __pxp_terminate_all(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + unsigned long flags; + + /* pchan->queue is modified in ISR, have to spinlock */ + spin_lock_irqsave(&pxp_chan->lock, flags); + list_splice_init(&pxp_chan->queue, &pxp_chan->free_list); + list_splice_init(&pxp_chan->active_list, &pxp_chan->free_list); + + spin_unlock_irqrestore(&pxp_chan->lock, flags); + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; +} + +static int pxp_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + /* Only supports DMA_TERMINATE_ALL */ + if (cmd != DMA_TERMINATE_ALL) + return -ENXIO; + + mutex_lock(&pxp_chan->chan_mutex); + __pxp_terminate_all(chan); + mutex_unlock(&pxp_chan->chan_mutex); + + return 0; +} + +static int pxp_alloc_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + int ret; + + /* dmaengine.c now guarantees to only offer free channels */ + BUG_ON(chan->client_count > 1); + WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE); + + chan->cookie = 1; + pxp_chan->completed = -ENXIO; + + pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id); + ret = pxp_init_channel(pxp_dma, pxp_chan); + if (ret < 0) + goto err_chan; + + pxp_chan->status = PXP_CHANNEL_INITIALIZED; + + dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n", + chan->chan_id, pxp_chan->eof_irq); + + return ret; + +err_chan: + return ret; +} + +static void pxp_free_chan_resources(struct dma_chan *chan) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxp_dma *pxp_dma = to_pxp_dma(chan->device); + + mutex_lock(&pxp_chan->chan_mutex); + + __pxp_terminate_all(chan); + + pxp_chan->status = PXP_CHANNEL_FREE; + + pxp_uninit_channel(pxp_dma, pxp_chan); + + mutex_unlock(&pxp_chan->chan_mutex); +} + +static enum dma_status pxp_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + + if (cookie != chan->cookie) + return DMA_ERROR; + + if (txstate) { + txstate->last = pxp_chan->completed; + txstate->used = chan->cookie; + txstate->residue = 0; + } + return DMA_SUCCESS; +} + +static int pxp_hw_init(struct pxps *pxp) +{ + struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + u32 reg_val; + int i; + + /* Pull PxP out of reset */ + __raw_writel(0, pxp->base + HW_PXP_CTRL); + + /* Config defaults */ + + /* Initialize non-channel-specific PxP parameters */ + proc_data->drect.left = proc_data->srect.left = 0; + proc_data->drect.top = proc_data->srect.top = 0; + proc_data->drect.width = proc_data->srect.width = 0; + proc_data->drect.height = proc_data->srect.height = 0; + proc_data->scaling = 0; + proc_data->hflip = 0; + proc_data->vflip = 0; + proc_data->rotate = 0; + proc_data->bgcolor = 0; + + /* Initialize S0 channel parameters */ + pxp_conf->s0_param.pixel_fmt = pxp_s0_formats[0]; + pxp_conf->s0_param.width = 0; + pxp_conf->s0_param.height = 0; + pxp_conf->s0_param.color_key = -1; + pxp_conf->s0_param.color_key_enable = false; + + /* Initialize OL channel parameters */ + for (i = 0; i < 8; i++) { + pxp_conf->ol_param[i].combine_enable = false; + pxp_conf->ol_param[i].width = 0; + pxp_conf->ol_param[i].height = 0; + pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565; + pxp_conf->ol_param[i].color_key_enable = false; + pxp_conf->ol_param[i].color_key = -1; + pxp_conf->ol_param[i].global_alpha_enable = false; + pxp_conf->ol_param[i].global_alpha = 0; + pxp_conf->ol_param[i].local_alpha_enable = false; + } + + /* Initialize Output channel parameters */ + pxp_conf->out_param.width = 0; + pxp_conf->out_param.height = 0; + pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_RGB565; + + proc_data->overlay_state = 0; + + /* Write default h/w config */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + for (i = 0; i < 8; i++) { + pxp_set_oln(i, pxp); + pxp_set_olparam(i, pxp); + pxp_set_olcolorkey(i, pxp); + } + pxp_set_s0colorkey(pxp); + pxp_set_csc(pxp); + pxp_set_bg(pxp); + pxp_set_lut(pxp); + + /* One-time histogram configuration */ + reg_val = + BF_PXP_HIST_CTRL_PANEL_MODE(BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST_CTRL); + + reg_val = BF_PXP_HIST2_PARAM_VALUE0(0x00) | + BF_PXP_HIST2_PARAM_VALUE1(0x00F); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST2_PARAM); + + reg_val = BF_PXP_HIST4_PARAM_VALUE0(0x00) | + BF_PXP_HIST4_PARAM_VALUE1(0x05) | + BF_PXP_HIST4_PARAM_VALUE2(0x0A) | BF_PXP_HIST4_PARAM_VALUE3(0x0F); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST4_PARAM); + + reg_val = BF_PXP_HIST8_PARAM0_VALUE0(0x00) | + BF_PXP_HIST8_PARAM0_VALUE1(0x02) | + BF_PXP_HIST8_PARAM0_VALUE2(0x04) | BF_PXP_HIST8_PARAM0_VALUE3(0x06); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM0); + reg_val = BF_PXP_HIST8_PARAM1_VALUE4(0x09) | + BF_PXP_HIST8_PARAM1_VALUE5(0x0B) | + BF_PXP_HIST8_PARAM1_VALUE6(0x0D) | BF_PXP_HIST8_PARAM1_VALUE7(0x0F); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM1); + + reg_val = BF_PXP_HIST16_PARAM0_VALUE0(0x00) | + BF_PXP_HIST16_PARAM0_VALUE1(0x01) | + BF_PXP_HIST16_PARAM0_VALUE2(0x02) | + BF_PXP_HIST16_PARAM0_VALUE3(0x03); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM0); + reg_val = BF_PXP_HIST16_PARAM1_VALUE4(0x04) | + BF_PXP_HIST16_PARAM1_VALUE5(0x05) | + BF_PXP_HIST16_PARAM1_VALUE6(0x06) | + BF_PXP_HIST16_PARAM1_VALUE7(0x07); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM1); + reg_val = BF_PXP_HIST16_PARAM2_VALUE8(0x08) | + BF_PXP_HIST16_PARAM2_VALUE9(0x09) | + BF_PXP_HIST16_PARAM2_VALUE10(0x0A) | + BF_PXP_HIST16_PARAM2_VALUE11(0x0B); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM2); + reg_val = BF_PXP_HIST16_PARAM3_VALUE12(0x0C) | + BF_PXP_HIST16_PARAM3_VALUE13(0x0D) | + BF_PXP_HIST16_PARAM3_VALUE14(0x0E) | + BF_PXP_HIST16_PARAM3_VALUE15(0x0F); + __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM3); + + return 0; +} + +static int pxp_dma_init(struct pxps *pxp) +{ + struct pxp_dma *pxp_dma = &pxp->pxp_dma; + struct dma_device *dma = &pxp_dma->dma; + int i; + + dma_cap_set(DMA_SLAVE, dma->cap_mask); + dma_cap_set(DMA_PRIVATE, dma->cap_mask); + + /* Compulsory common fields */ + dma->dev = pxp->dev; + dma->device_alloc_chan_resources = pxp_alloc_chan_resources; + dma->device_free_chan_resources = pxp_free_chan_resources; + dma->device_tx_status = pxp_tx_status; + dma->device_issue_pending = pxp_issue_pending; + + /* Compulsory for DMA_SLAVE fields */ + dma->device_prep_slave_sg = pxp_prep_slave_sg; + dma->device_control = pxp_control; + + /* Initialize PxP Channels */ + INIT_LIST_HEAD(&dma->channels); + for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) { + struct pxp_channel *pxp_chan = pxp->channel + i; + struct dma_chan *dma_chan = &pxp_chan->dma_chan; + + spin_lock_init(&pxp_chan->lock); + mutex_init(&pxp_chan->chan_mutex); + + /* Only one EOF IRQ for PxP, shared by all channels */ + pxp_chan->eof_irq = pxp->irq; + pxp_chan->status = PXP_CHANNEL_FREE; + pxp_chan->completed = -ENXIO; + snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name), + "PXP EOF %d", i); + + dma_chan->device = &pxp_dma->dma; + dma_chan->cookie = 1; + dma_chan->chan_id = i; + list_add_tail(&dma_chan->device_node, &dma->channels); + } + + return dma_async_device_register(&pxp_dma->dma); +} + +static ssize_t clk_off_timeout_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", timeout_in_ms); +} + +static ssize_t clk_off_timeout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + timeout_in_ms = val; + return count; + } + return -EINVAL; +} + +static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show, + clk_off_timeout_store); + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + struct resource *res; + int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) { + err = -ENODEV; + goto exit; + } + + pxp = kzalloc(sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + pxp->dev = &pdev->dev; + + platform_set_drvdata(pdev, pxp); + pxp->irq = irq; + + pxp->pxp_ongoing = 0; + pxp->lut_state = 0; + + spin_lock_init(&pxp->lock); + mutex_init(&pxp->clk_mutex); + + if (!request_mem_region(res->start, resource_size(res), "pxp-mem")) { + err = -EBUSY; + goto freepxp; + } + + pxp->base = ioremap(res->start, SZ_4K); + pxp->pdev = pdev; + + pxp->clk = clk_get(NULL, "pxp_axi"); + clk_enable(pxp->clk); + + err = pxp_hw_init(pxp); + if (err) { + dev_err(&pdev->dev, "failed to initialize hardware\n"); + goto release; + } + clk_disable(pxp->clk); + + err = request_irq(pxp->irq, pxp_irq, 0, "pxp-irq", pxp); + if (err) + goto release; + /* Initialize DMA engine */ + err = pxp_dma_init(pxp); + if (err < 0) + goto err_dma_init; + + if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) { + dev_err(&pdev->dev, + "Unable to create file from clk_off_timeout\n"); + goto err_dma_init; + } + + INIT_WORK(&pxp->work, clkoff_callback); + init_waitqueue_head(&pxp->done); + init_timer(&pxp->clk_timer); + pxp->clk_timer.function = pxp_clkoff_timer; + pxp->clk_timer.data = (unsigned long)pxp; +exit: + return err; +err_dma_init: + free_irq(pxp->irq, pxp); +release: + release_mem_region(res->start, resource_size(res)); +freepxp: + kfree(pxp); + dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe function\n"); + return err; +} + +static int __devexit pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + cancel_work_sync(&pxp->work); + del_timer_sync(&pxp->clk_timer); + free_irq(pxp->irq, pxp); + clk_disable(pxp->clk); + clk_put(pxp->clk); + iounmap(pxp->base); + device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout); + + kfree(pxp); + + return 0; +} + +#ifdef CONFIG_PM +static int pxp_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + pxp_clk_enable(pxp); + while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} + +static int pxp_resume(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + pxp_clk_enable(pxp); + /* Pull PxP out of reset */ + __raw_writel(0, pxp->base + HW_PXP_CTRL); + pxp_clk_disable(pxp); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +static struct platform_driver pxp_driver = { + .driver = { + .name = "mxc-pxp", + }, + .probe = pxp_probe, + .remove = __exit_p(pxp_remove), + .suspend = pxp_suspend, + .resume = pxp_resume, +}; + +static int __init pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} + +subsys_initcall(pxp_init); + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} + +module_exit(pxp_exit); + +MODULE_DESCRIPTION("i.MX PxP driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/pxp/regs-pxp.h b/drivers/dma/pxp/regs-pxp.h new file mode 100644 index 000000000000..b0c1b00fdfa0 --- /dev/null +++ b/drivers/dma/pxp/regs-pxp.h @@ -0,0 +1,949 @@ +/* + * Freescale PXP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.6 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H + + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BM_PXP_CTRL_RSVD 0x20000000 +#define BM_PXP_CTRL_EN_REPEAT 0x10000000 +#define BP_PXP_CTRL_INTERLACED_OUTPUT 26 +#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000 +#define BF_PXP_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000 +#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0 +#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 +#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BM_PXP_CTRL_DELTA 0x00100000 +#define BM_PXP_CTRL_CROP 0x00080000 +#define BM_PXP_CTRL_SCALE 0x00040000 +#define BM_PXP_CTRL_UPSAMPLE 0x00020000 +#define BM_PXP_CTRL_SUBSAMPLE 0x00010000 +#define BP_PXP_CTRL_S0_FORMAT 12 +#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 +#define BF_PXP_CTRL_S0_FORMAT(v) \ + (((v) << 12) & BM_PXP_CTRL_S0_FORMAT) +#define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8 +#define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9 +#define BV_PXP_CTRL_S0_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_S0_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_S0_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_S0_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_S0_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_S0_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_OUTBUF_FORMAT 4 +#define BM_PXP_CTRL_OUTBUF_FORMAT 0x000000F0 +#define BF_PXP_CTRL_OUTBUF_FORMAT(v) \ + (((v) << 4) & BM_PXP_CTRL_OUTBUF_FORMAT) +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P 0x2 +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555 0x3 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV444 0x7 +#define BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8 0x8 +#define BV_PXP_CTRL_OUTBUF_FORMAT__MONOC4 0x9 +#define BV_PXP_CTRL_OUTBUF_FORMAT__UYVY1P422 0xA +#define BV_PXP_CTRL_OUTBUF_FORMAT__VYUY1P422 0xB +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P422 0xC +#define BV_PXP_CTRL_OUTBUF_FORMAT__YUV2P420 0xD +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P422 0xE +#define BV_PXP_CTRL_OUTBUF_FORMAT__YVU2P420 0xF +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000008 +#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) + +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 8 +#define BM_PXP_STAT_RSVD2 0x0000FF00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 8) & BM_PXP_STAT_RSVD2) +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_NEXT_IRQ 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 + +#define HW_PXP_OUTBUF (0x00000020) + +#define BP_PXP_OUTBUF_ADDR 0 +#define BM_PXP_OUTBUF_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF_ADDR(v) (v) + +#define HW_PXP_OUTBUF2 (0x00000030) + +#define BP_PXP_OUTBUF2_ADDR 0 +#define BM_PXP_OUTBUF2_ADDR 0xFFFFFFFF +#define BF_PXP_OUTBUF2_ADDR(v) (v) + +#define HW_PXP_OUTSIZE (0x00000040) + +#define BP_PXP_OUTSIZE_ALPHA 24 +#define BM_PXP_OUTSIZE_ALPHA 0xFF000000 +#define BF_PXP_OUTSIZE_ALPHA(v) \ + (((v) << 24) & BM_PXP_OUTSIZE_ALPHA) +#define BP_PXP_OUTSIZE_WIDTH 12 +#define BM_PXP_OUTSIZE_WIDTH 0x00FFF000 +#define BF_PXP_OUTSIZE_WIDTH(v) \ + (((v) << 12) & BM_PXP_OUTSIZE_WIDTH) +#define BP_PXP_OUTSIZE_HEIGHT 0 +#define BM_PXP_OUTSIZE_HEIGHT 0x00000FFF +#define BF_PXP_OUTSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OUTSIZE_HEIGHT) + +#define HW_PXP_S0BUF (0x00000050) + +#define BP_PXP_S0BUF_ADDR 0 +#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0BUF_ADDR(v) (v) + +#define HW_PXP_S0UBUF (0x00000060) + +#define BP_PXP_S0UBUF_ADDR 0 +#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0UBUF_ADDR(v) (v) + +#define HW_PXP_S0VBUF (0x00000070) + +#define BP_PXP_S0VBUF_ADDR 0 +#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0VBUF_ADDR(v) (v) + +#define HW_PXP_S0PARAM (0x00000080) + +#define BP_PXP_S0PARAM_XBASE 24 +#define BM_PXP_S0PARAM_XBASE 0xFF000000 +#define BF_PXP_S0PARAM_XBASE(v) \ + (((v) << 24) & BM_PXP_S0PARAM_XBASE) +#define BP_PXP_S0PARAM_YBASE 16 +#define BM_PXP_S0PARAM_YBASE 0x00FF0000 +#define BF_PXP_S0PARAM_YBASE(v) \ + (((v) << 16) & BM_PXP_S0PARAM_YBASE) +#define BP_PXP_S0PARAM_WIDTH 8 +#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 +#define BF_PXP_S0PARAM_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0PARAM_WIDTH) +#define BP_PXP_S0PARAM_HEIGHT 0 +#define BM_PXP_S0PARAM_HEIGHT 0x000000FF +#define BF_PXP_S0PARAM_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0PARAM_HEIGHT) + +#define HW_PXP_S0BACKGROUND (0x00000090) + +#define BP_PXP_S0BACKGROUND_COLOR 0 +#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_S0BACKGROUND_COLOR(v) (v) + +#define HW_PXP_S0CROP (0x000000a0) + +#define BP_PXP_S0CROP_XBASE 24 +#define BM_PXP_S0CROP_XBASE 0xFF000000 +#define BF_PXP_S0CROP_XBASE(v) \ + (((v) << 24) & BM_PXP_S0CROP_XBASE) +#define BP_PXP_S0CROP_YBASE 16 +#define BM_PXP_S0CROP_YBASE 0x00FF0000 +#define BF_PXP_S0CROP_YBASE(v) \ + (((v) << 16) & BM_PXP_S0CROP_YBASE) +#define BP_PXP_S0CROP_WIDTH 8 +#define BM_PXP_S0CROP_WIDTH 0x0000FF00 +#define BF_PXP_S0CROP_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0CROP_WIDTH) +#define BP_PXP_S0CROP_HEIGHT 0 +#define BM_PXP_S0CROP_HEIGHT 0x000000FF +#define BF_PXP_S0CROP_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0CROP_HEIGHT) + +#define HW_PXP_S0SCALE (0x000000b0) + +#define BM_PXP_S0SCALE_RSVD2 0x80000000 +#define BP_PXP_S0SCALE_YSCALE 16 +#define BM_PXP_S0SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_S0SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_S0SCALE_YSCALE) +#define BM_PXP_S0SCALE_RSVD1 0x00008000 +#define BP_PXP_S0SCALE_XSCALE 0 +#define BM_PXP_S0SCALE_XSCALE 0x00007FFF +#define BF_PXP_S0SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_S0SCALE_XSCALE) + +#define HW_PXP_S0OFFSET (0x000000c0) + +#define BP_PXP_S0OFFSET_RSVD2 28 +#define BM_PXP_S0OFFSET_RSVD2 0xF0000000 +#define BF_PXP_S0OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_S0OFFSET_RSVD2) +#define BP_PXP_S0OFFSET_YOFFSET 16 +#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_S0OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_S0OFFSET_YOFFSET) +#define BP_PXP_S0OFFSET_RSVD1 12 +#define BM_PXP_S0OFFSET_RSVD1 0x0000F000 +#define BF_PXP_S0OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_S0OFFSET_RSVD1) +#define BP_PXP_S0OFFSET_XOFFSET 0 +#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_S0OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_S0OFFSET_XOFFSET) + +#define HW_PXP_CSCCOEF0 (0x000000d0) + +#define BM_PXP_CSCCOEF0_YCBCR_MODE 0x80000000 +#define BM_PXP_CSCCOEF0_BYPASS 0x40000000 +#define BM_PXP_CSCCOEF0_RSVD1 0x20000000 +#define BP_PXP_CSCCOEF0_C0 18 +#define BM_PXP_CSCCOEF0_C0 0x1FFC0000 +#define BF_PXP_CSCCOEF0_C0(v) \ + (((v) << 18) & BM_PXP_CSCCOEF0_C0) +#define BP_PXP_CSCCOEF0_UV_OFFSET 9 +#define BM_PXP_CSCCOEF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSCCOEF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSCCOEF0_UV_OFFSET) +#define BP_PXP_CSCCOEF0_Y_OFFSET 0 +#define BM_PXP_CSCCOEF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSCCOEF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSCCOEF0_Y_OFFSET) + +#define HW_PXP_CSCCOEF1 (0x000000e0) + +#define BP_PXP_CSCCOEF1_RSVD1 27 +#define BM_PXP_CSCCOEF1_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEF1_RSVD1) +#define BP_PXP_CSCCOEF1_C1 16 +#define BM_PXP_CSCCOEF1_C1 0x07FF0000 +#define BF_PXP_CSCCOEF1_C1(v) \ + (((v) << 16) & BM_PXP_CSCCOEF1_C1) +#define BP_PXP_CSCCOEF1_RSVD0 11 +#define BM_PXP_CSCCOEF1_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEF1_RSVD0) +#define BP_PXP_CSCCOEF1_C4 0 +#define BM_PXP_CSCCOEF1_C4 0x000007FF +#define BF_PXP_CSCCOEF1_C4(v) \ + (((v) << 0) & BM_PXP_CSCCOEF1_C4) + +#define HW_PXP_CSCCOEF2 (0x000000f0) + +#define BP_PXP_CSCCOEF2_RSVD1 27 +#define BM_PXP_CSCCOEF2_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEF2_RSVD1) +#define BP_PXP_CSCCOEF2_C2 16 +#define BM_PXP_CSCCOEF2_C2 0x07FF0000 +#define BF_PXP_CSCCOEF2_C2(v) \ + (((v) << 16) & BM_PXP_CSCCOEF2_C2) +#define BP_PXP_CSCCOEF2_RSVD0 11 +#define BM_PXP_CSCCOEF2_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEF2_RSVD0) +#define BP_PXP_CSCCOEF2_C3 0 +#define BM_PXP_CSCCOEF2_C3 0x000007FF +#define BF_PXP_CSCCOEF2_C3(v) \ + (((v) << 0) & BM_PXP_CSCCOEF2_C3) + +#define HW_PXP_NEXT (0x00000100) +#define HW_PXP_NEXT_SET (0x00000104) +#define HW_PXP_NEXT_CLR (0x00000108) +#define HW_PXP_NEXT_TOG (0x0000010c) + +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 + +#define HW_PXP_S0COLORKEYLOW (0x00000180) + +#define BP_PXP_S0COLORKEYLOW_RSVD1 24 +#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1) +#define BP_PXP_S0COLORKEYLOW_PIXEL 0 +#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL) + +#define HW_PXP_S0COLORKEYHIGH (0x00000190) + +#define BP_PXP_S0COLORKEYHIGH_RSVD1 24 +#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1) +#define BP_PXP_S0COLORKEYHIGH_PIXEL 0 +#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL) + +#define HW_PXP_OLCOLORKEYLOW (0x000001a0) + +#define BP_PXP_OLCOLORKEYLOW_RSVD1 24 +#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1) +#define BP_PXP_OLCOLORKEYLOW_PIXEL 0 +#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL) + +#define HW_PXP_OLCOLORKEYHIGH (0x000001b0) + +#define BP_PXP_OLCOLORKEYHIGH_RSVD1 24 +#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1) +#define BP_PXP_OLCOLORKEYHIGH_PIXEL 0 +#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL) + +#define HW_PXP_DEBUGCTRL (0x000001d0) + +#define BP_PXP_DEBUGCTRL_RSVD 8 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFF00 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 8) & BM_PXP_DEBUGCTRL_RSVD) +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8 + +#define HW_PXP_DEBUG (0x000001e0) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x000001f0) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +/* + * multi-register-define name HW_PXP_OLn + * base 0x00000200 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLn(n) (0x00000200 + (n) * 0x40) +#define BP_PXP_OLn_ADDR 0 +#define BM_PXP_OLn_ADDR 0xFFFFFFFF +#define BF_PXP_OLn_ADDR(v) (v) + +/* + * multi-register-define name HW_PXP_OLnSIZE + * base 0x00000210 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnSIZE(n) (0x00000210 + (n) * 0x40) +#define BP_PXP_OLnSIZE_XBASE 24 +#define BM_PXP_OLnSIZE_XBASE 0xFF000000 +#define BF_PXP_OLnSIZE_XBASE(v) \ + (((v) << 24) & BM_PXP_OLnSIZE_XBASE) +#define BP_PXP_OLnSIZE_YBASE 16 +#define BM_PXP_OLnSIZE_YBASE 0x00FF0000 +#define BF_PXP_OLnSIZE_YBASE(v) \ + (((v) << 16) & BM_PXP_OLnSIZE_YBASE) +#define BP_PXP_OLnSIZE_WIDTH 8 +#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 +#define BF_PXP_OLnSIZE_WIDTH(v) \ + (((v) << 8) & BM_PXP_OLnSIZE_WIDTH) +#define BP_PXP_OLnSIZE_HEIGHT 0 +#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF +#define BF_PXP_OLnSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OLnSIZE_HEIGHT) + +/* + * multi-register-define name HW_PXP_OLnPARAM + * base 0x00000220 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM(n) (0x00000220 + (n) * 0x40) +#define BP_PXP_OLnPARAM_RSVD1 20 +#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000 +#define BF_PXP_OLnPARAM_RSVD1(v) \ + (((v) << 20) & BM_PXP_OLnPARAM_RSVD1) +#define BP_PXP_OLnPARAM_ROP 16 +#define BM_PXP_OLnPARAM_ROP 0x000F0000 +#define BF_PXP_OLnPARAM_ROP(v) \ + (((v) << 16) & BM_PXP_OLnPARAM_ROP) +#define BV_PXP_OLnPARAM_ROP__MASKOL 0x0 +#define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1 +#define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2 +#define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3 +#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4 +#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5 +#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6 +#define BV_PXP_OLnPARAM_ROP__NOT 0x7 +#define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8 +#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9 +#define BV_PXP_OLnPARAM_ROP__XOROL 0xA +#define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xB +#define BP_PXP_OLnPARAM_ALPHA 8 +#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 +#define BF_PXP_OLnPARAM_ALPHA(v) \ + (((v) << 8) & BM_PXP_OLnPARAM_ALPHA) +#define BP_PXP_OLnPARAM_FORMAT 4 +#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 +#define BF_PXP_OLnPARAM_FORMAT(v) \ + (((v) << 4) & BM_PXP_OLnPARAM_FORMAT) +#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0 +#define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1 +#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3 +#define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4 +#define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5 +#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 +#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 +#define BF_PXP_OLnPARAM_ALPHA_CNTL(v) \ + (((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL) +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3 +#define BM_PXP_OLnPARAM_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PXP_OLnPARAM2 + * base 0x00000230 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM2(n) (0x00000230 + (n) * 0x40) +#define BP_PXP_OLnPARAM2_RSVD 0 +#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF +#define BF_PXP_OLnPARAM2_RSVD(v) (v) + +#define HW_PXP_CSC2CTRL (0x00000400) + +#define BP_PXP_CSC2CTRL_RSVD 3 +#define BM_PXP_CSC2CTRL_RSVD 0xFFFFFFF8 +#define BF_PXP_CSC2CTRL_RSVD(v) \ + (((v) << 3) & BM_PXP_CSC2CTRL_RSVD) +#define BP_PXP_CSC2CTRL_CSC_MODE 1 +#define BM_PXP_CSC2CTRL_CSC_MODE 0x00000006 +#define BF_PXP_CSC2CTRL_CSC_MODE(v) \ + (((v) << 1) & BM_PXP_CSC2CTRL_CSC_MODE) +#define BV_PXP_CSC2CTRL_CSC_MODE__YUV2RGB 0x0 +#define BV_PXP_CSC2CTRL_CSC_MODE__YCbCr2RGB 0x1 +#define BV_PXP_CSC2CTRL_CSC_MODE__RGB2YUV 0x2 +#define BV_PXP_CSC2CTRL_CSC_MODE__RGB2YCbCr 0x3 +#define BM_PXP_CSC2CTRL_BYPASS 0x00000001 + +#define HW_PXP_CSC2COEF0 (0x00000410) + +#define BP_PXP_CSC2COEF0_RSVD1 27 +#define BM_PXP_CSC2COEF0_RSVD1 0xF8000000 +#define BF_PXP_CSC2COEF0_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2COEF0_RSVD1) +#define BP_PXP_CSC2COEF0_A2 16 +#define BM_PXP_CSC2COEF0_A2 0x07FF0000 +#define BF_PXP_CSC2COEF0_A2(v) \ + (((v) << 16) & BM_PXP_CSC2COEF0_A2) +#define BP_PXP_CSC2COEF0_RSVD0 11 +#define BM_PXP_CSC2COEF0_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF0_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF0_RSVD0) +#define BP_PXP_CSC2COEF0_A1 0 +#define BM_PXP_CSC2COEF0_A1 0x000007FF +#define BF_PXP_CSC2COEF0_A1(v) \ + (((v) << 0) & BM_PXP_CSC2COEF0_A1) + +#define HW_PXP_CSC2COEF1 (0x00000420) + +#define BP_PXP_CSC2COEF1_RSVD1 27 +#define BM_PXP_CSC2COEF1_RSVD1 0xF8000000 +#define BF_PXP_CSC2COEF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2COEF1_RSVD1) +#define BP_PXP_CSC2COEF1_B1 16 +#define BM_PXP_CSC2COEF1_B1 0x07FF0000 +#define BF_PXP_CSC2COEF1_B1(v) \ + (((v) << 16) & BM_PXP_CSC2COEF1_B1) +#define BP_PXP_CSC2COEF1_RSVD0 11 +#define BM_PXP_CSC2COEF1_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF1_RSVD0) +#define BP_PXP_CSC2COEF1_A3 0 +#define BM_PXP_CSC2COEF1_A3 0x000007FF +#define BF_PXP_CSC2COEF1_A3(v) \ + (((v) << 0) & BM_PXP_CSC2COEF1_A3) + +#define HW_PXP_CSC2COEF2 (0x00000430) + +#define BP_PXP_CSC2COEF2_RSVD1 27 +#define BM_PXP_CSC2COEF2_RSVD1 0xF8000000 +#define BF_PXP_CSC2COEF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2COEF2_RSVD1) +#define BP_PXP_CSC2COEF2_B3 16 +#define BM_PXP_CSC2COEF2_B3 0x07FF0000 +#define BF_PXP_CSC2COEF2_B3(v) \ + (((v) << 16) & BM_PXP_CSC2COEF2_B3) +#define BP_PXP_CSC2COEF2_RSVD0 11 +#define BM_PXP_CSC2COEF2_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF2_RSVD0) +#define BP_PXP_CSC2COEF2_B2 0 +#define BM_PXP_CSC2COEF2_B2 0x000007FF +#define BF_PXP_CSC2COEF2_B2(v) \ + (((v) << 0) & BM_PXP_CSC2COEF2_B2) + +#define HW_PXP_CSC2COEF3 (0x00000440) + +#define BP_PXP_CSC2COEF3_RSVD1 27 +#define BM_PXP_CSC2COEF3_RSVD1 0xF8000000 +#define BF_PXP_CSC2COEF3_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSC2COEF3_RSVD1) +#define BP_PXP_CSC2COEF3_C2 16 +#define BM_PXP_CSC2COEF3_C2 0x07FF0000 +#define BF_PXP_CSC2COEF3_C2(v) \ + (((v) << 16) & BM_PXP_CSC2COEF3_C2) +#define BP_PXP_CSC2COEF3_RSVD0 11 +#define BM_PXP_CSC2COEF3_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF3_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF3_RSVD0) +#define BP_PXP_CSC2COEF3_C1 0 +#define BM_PXP_CSC2COEF3_C1 0x000007FF +#define BF_PXP_CSC2COEF3_C1(v) \ + (((v) << 0) & BM_PXP_CSC2COEF3_C1) + +#define HW_PXP_CSC2COEF4 (0x00000450) + +#define BP_PXP_CSC2COEF4_RSVD1 25 +#define BM_PXP_CSC2COEF4_RSVD1 0xFE000000 +#define BF_PXP_CSC2COEF4_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2COEF4_RSVD1) +#define BP_PXP_CSC2COEF4_D1 16 +#define BM_PXP_CSC2COEF4_D1 0x01FF0000 +#define BF_PXP_CSC2COEF4_D1(v) \ + (((v) << 16) & BM_PXP_CSC2COEF4_D1) +#define BP_PXP_CSC2COEF4_RSVD0 11 +#define BM_PXP_CSC2COEF4_RSVD0 0x0000F800 +#define BF_PXP_CSC2COEF4_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSC2COEF4_RSVD0) +#define BP_PXP_CSC2COEF4_C3 0 +#define BM_PXP_CSC2COEF4_C3 0x000007FF +#define BF_PXP_CSC2COEF4_C3(v) \ + (((v) << 0) & BM_PXP_CSC2COEF4_C3) + +#define HW_PXP_CSC2COEF5 (0x00000460) + +#define BP_PXP_CSC2COEF5_RSVD1 25 +#define BM_PXP_CSC2COEF5_RSVD1 0xFE000000 +#define BF_PXP_CSC2COEF5_RSVD1(v) \ + (((v) << 25) & BM_PXP_CSC2COEF5_RSVD1) +#define BP_PXP_CSC2COEF5_D3 16 +#define BM_PXP_CSC2COEF5_D3 0x01FF0000 +#define BF_PXP_CSC2COEF5_D3(v) \ + (((v) << 16) & BM_PXP_CSC2COEF5_D3) +#define BP_PXP_CSC2COEF5_RSVD0 9 +#define BM_PXP_CSC2COEF5_RSVD0 0x0000FE00 +#define BF_PXP_CSC2COEF5_RSVD0(v) \ + (((v) << 9) & BM_PXP_CSC2COEF5_RSVD0) +#define BP_PXP_CSC2COEF5_D2 0 +#define BM_PXP_CSC2COEF5_D2 0x000001FF +#define BF_PXP_CSC2COEF5_D2(v) \ + (((v) << 0) & BM_PXP_CSC2COEF5_D2) + +#define HW_PXP_LUT_CTRL (0x00000470) + +#define BM_PXP_LUT_CTRL_BYPASS 0x80000000 +#define BP_PXP_LUT_CTRL_RSVD 8 +#define BM_PXP_LUT_CTRL_RSVD 0x7FFFFF00 +#define BF_PXP_LUT_CTRL_RSVD(v) \ + (((v) << 8) & BM_PXP_LUT_CTRL_RSVD) +#define BP_PXP_LUT_CTRL_ADDR 0 +#define BM_PXP_LUT_CTRL_ADDR 0x000000FF +#define BF_PXP_LUT_CTRL_ADDR(v) \ + (((v) << 0) & BM_PXP_LUT_CTRL_ADDR) + +#define HW_PXP_LUT (0x00000480) + +#define BP_PXP_LUT_RSVD 8 +#define BM_PXP_LUT_RSVD 0xFFFFFF00 +#define BF_PXP_LUT_RSVD(v) \ + (((v) << 8) & BM_PXP_LUT_RSVD) +#define BP_PXP_LUT_DATA 0 +#define BM_PXP_LUT_DATA 0x000000FF +#define BF_PXP_LUT_DATA(v) \ + (((v) << 0) & BM_PXP_LUT_DATA) + +#define HW_PXP_HIST_CTRL (0x00000490) + +#define BP_PXP_HIST_CTRL_RSVD 6 +#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0 +#define BF_PXP_HIST_CTRL_RSVD(v) \ + (((v) << 6) & BM_PXP_HIST_CTRL_RSVD) +#define BP_PXP_HIST_CTRL_PANEL_MODE 4 +#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030 +#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \ + (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE) +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2 +#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3 +#define BP_PXP_HIST_CTRL_STATUS 0 +#define BM_PXP_HIST_CTRL_STATUS 0x0000000F +#define BF_PXP_HIST_CTRL_STATUS(v) \ + (((v) << 0) & BM_PXP_HIST_CTRL_STATUS) + +#define HW_PXP_HIST2_PARAM (0x000004a0) + +#define BP_PXP_HIST2_PARAM_RSVD 16 +#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000 +#define BF_PXP_HIST2_PARAM_RSVD(v) \ + (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD) +#define BP_PXP_HIST2_PARAM_RSVD1 13 +#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST2_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1) +#define BP_PXP_HIST2_PARAM_VALUE1 8 +#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST2_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1) +#define BP_PXP_HIST2_PARAM_RSVD0 5 +#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST2_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0) +#define BP_PXP_HIST2_PARAM_VALUE0 0 +#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST2_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0) + +#define HW_PXP_HIST4_PARAM (0x000004b0) + +#define BP_PXP_HIST4_PARAM_RSVD3 29 +#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000 +#define BF_PXP_HIST4_PARAM_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3) +#define BP_PXP_HIST4_PARAM_VALUE3 24 +#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000 +#define BF_PXP_HIST4_PARAM_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3) +#define BP_PXP_HIST4_PARAM_RSVD2 21 +#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000 +#define BF_PXP_HIST4_PARAM_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2) +#define BP_PXP_HIST4_PARAM_VALUE2 16 +#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000 +#define BF_PXP_HIST4_PARAM_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2) +#define BP_PXP_HIST4_PARAM_RSVD1 13 +#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000 +#define BF_PXP_HIST4_PARAM_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1) +#define BP_PXP_HIST4_PARAM_VALUE1 8 +#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00 +#define BF_PXP_HIST4_PARAM_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1) +#define BP_PXP_HIST4_PARAM_RSVD0 5 +#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0 +#define BF_PXP_HIST4_PARAM_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0) +#define BP_PXP_HIST4_PARAM_VALUE0 0 +#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F +#define BF_PXP_HIST4_PARAM_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0) + +#define HW_PXP_HIST8_PARAM0 (0x000004c0) + +#define BP_PXP_HIST8_PARAM0_RSVD3 29 +#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST8_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3) +#define BP_PXP_HIST8_PARAM0_VALUE3 24 +#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST8_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3) +#define BP_PXP_HIST8_PARAM0_RSVD2 21 +#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST8_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2) +#define BP_PXP_HIST8_PARAM0_VALUE2 16 +#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST8_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2) +#define BP_PXP_HIST8_PARAM0_RSVD1 13 +#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST8_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1) +#define BP_PXP_HIST8_PARAM0_VALUE1 8 +#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST8_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1) +#define BP_PXP_HIST8_PARAM0_RSVD0 5 +#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST8_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0) +#define BP_PXP_HIST8_PARAM0_VALUE0 0 +#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST8_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0) + +#define HW_PXP_HIST8_PARAM1 (0x000004d0) + +#define BP_PXP_HIST8_PARAM1_RSVD7 29 +#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST8_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7) +#define BP_PXP_HIST8_PARAM1_VALUE7 24 +#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST8_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7) +#define BP_PXP_HIST8_PARAM1_RSVD6 21 +#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST8_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6) +#define BP_PXP_HIST8_PARAM1_VALUE6 16 +#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST8_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6) +#define BP_PXP_HIST8_PARAM1_RSVD5 13 +#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST8_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5) +#define BP_PXP_HIST8_PARAM1_VALUE5 8 +#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST8_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5) +#define BP_PXP_HIST8_PARAM1_RSVD4 5 +#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST8_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4) +#define BP_PXP_HIST8_PARAM1_VALUE4 0 +#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST8_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM0 (0x000004e0) + +#define BP_PXP_HIST16_PARAM0_RSVD3 29 +#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000 +#define BF_PXP_HIST16_PARAM0_RSVD3(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3) +#define BP_PXP_HIST16_PARAM0_VALUE3 24 +#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000 +#define BF_PXP_HIST16_PARAM0_VALUE3(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3) +#define BP_PXP_HIST16_PARAM0_RSVD2 21 +#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000 +#define BF_PXP_HIST16_PARAM0_RSVD2(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2) +#define BP_PXP_HIST16_PARAM0_VALUE2 16 +#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000 +#define BF_PXP_HIST16_PARAM0_VALUE2(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2) +#define BP_PXP_HIST16_PARAM0_RSVD1 13 +#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000 +#define BF_PXP_HIST16_PARAM0_RSVD1(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1) +#define BP_PXP_HIST16_PARAM0_VALUE1 8 +#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00 +#define BF_PXP_HIST16_PARAM0_VALUE1(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1) +#define BP_PXP_HIST16_PARAM0_RSVD0 5 +#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0 +#define BF_PXP_HIST16_PARAM0_RSVD0(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0) +#define BP_PXP_HIST16_PARAM0_VALUE0 0 +#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F +#define BF_PXP_HIST16_PARAM0_VALUE0(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0) + +#define HW_PXP_HIST16_PARAM1 (0x000004f0) + +#define BP_PXP_HIST16_PARAM1_RSVD7 29 +#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000 +#define BF_PXP_HIST16_PARAM1_RSVD7(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7) +#define BP_PXP_HIST16_PARAM1_VALUE7 24 +#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000 +#define BF_PXP_HIST16_PARAM1_VALUE7(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7) +#define BP_PXP_HIST16_PARAM1_RSVD6 21 +#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000 +#define BF_PXP_HIST16_PARAM1_RSVD6(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6) +#define BP_PXP_HIST16_PARAM1_VALUE6 16 +#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000 +#define BF_PXP_HIST16_PARAM1_VALUE6(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6) +#define BP_PXP_HIST16_PARAM1_RSVD5 13 +#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000 +#define BF_PXP_HIST16_PARAM1_RSVD5(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5) +#define BP_PXP_HIST16_PARAM1_VALUE5 8 +#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00 +#define BF_PXP_HIST16_PARAM1_VALUE5(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5) +#define BP_PXP_HIST16_PARAM1_RSVD4 5 +#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0 +#define BF_PXP_HIST16_PARAM1_RSVD4(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4) +#define BP_PXP_HIST16_PARAM1_VALUE4 0 +#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F +#define BF_PXP_HIST16_PARAM1_VALUE4(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4) + +#define HW_PXP_HIST16_PARAM2 (0x00000500) + +#define BP_PXP_HIST16_PARAM2_RSVD11 29 +#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000 +#define BF_PXP_HIST16_PARAM2_RSVD11(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11) +#define BP_PXP_HIST16_PARAM2_VALUE11 24 +#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000 +#define BF_PXP_HIST16_PARAM2_VALUE11(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11) +#define BP_PXP_HIST16_PARAM2_RSVD10 21 +#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000 +#define BF_PXP_HIST16_PARAM2_RSVD10(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10) +#define BP_PXP_HIST16_PARAM2_VALUE10 16 +#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000 +#define BF_PXP_HIST16_PARAM2_VALUE10(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10) +#define BP_PXP_HIST16_PARAM2_RSVD9 13 +#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000 +#define BF_PXP_HIST16_PARAM2_RSVD9(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9) +#define BP_PXP_HIST16_PARAM2_VALUE9 8 +#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00 +#define BF_PXP_HIST16_PARAM2_VALUE9(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9) +#define BP_PXP_HIST16_PARAM2_RSVD8 5 +#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0 +#define BF_PXP_HIST16_PARAM2_RSVD8(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8) +#define BP_PXP_HIST16_PARAM2_VALUE8 0 +#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F +#define BF_PXP_HIST16_PARAM2_VALUE8(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8) + +#define HW_PXP_HIST16_PARAM3 (0x00000510) + +#define BP_PXP_HIST16_PARAM3_RSVD15 29 +#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000 +#define BF_PXP_HIST16_PARAM3_RSVD15(v) \ + (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15) +#define BP_PXP_HIST16_PARAM3_VALUE15 24 +#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000 +#define BF_PXP_HIST16_PARAM3_VALUE15(v) \ + (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15) +#define BP_PXP_HIST16_PARAM3_RSVD14 21 +#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000 +#define BF_PXP_HIST16_PARAM3_RSVD14(v) \ + (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14) +#define BP_PXP_HIST16_PARAM3_VALUE14 16 +#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000 +#define BF_PXP_HIST16_PARAM3_VALUE14(v) \ + (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14) +#define BP_PXP_HIST16_PARAM3_RSVD13 13 +#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000 +#define BF_PXP_HIST16_PARAM3_RSVD13(v) \ + (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13) +#define BP_PXP_HIST16_PARAM3_VALUE13 8 +#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00 +#define BF_PXP_HIST16_PARAM3_VALUE13(v) \ + (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13) +#define BP_PXP_HIST16_PARAM3_RSVD12 5 +#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0 +#define BF_PXP_HIST16_PARAM3_RSVD12(v) \ + (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12) +#define BP_PXP_HIST16_PARAM3_VALUE12 0 +#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F +#define BF_PXP_HIST16_PARAM3_VALUE12(v) \ + (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 7face915b963..66dd4c3801a8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -343,4 +343,10 @@ config GPIO_JANZ_TTL This driver provides support for driving the pins in output mode only. Input mode is not supported. +config DA9052_GPIO_ENABLE + bool "Dialog DA9052 GPIO" + depends on PMIC_DA9052 + help + Say Y to enable the GPIO driver for the DA9052 chip + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index e53dcff49b4f..7f2963bd7c77 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -35,3 +35,4 @@ obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o obj-$(CONFIG_GPIO_SCH) += sch_gpio.o obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o +obj-$(CONFIG_DA9052_GPIO_ENABLE)+= da9052-gpio.o diff --git a/drivers/gpio/da9052-gpio.c b/drivers/gpio/da9052-gpio.c new file mode 100644 index 000000000000..c5ffcea0651f --- /dev/null +++ b/drivers/gpio/da9052-gpio.c @@ -0,0 +1,731 @@ +/* + * da9052-gpio.c -- GPIO Driver for Dialog DA9052 + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * Author: Dialog Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DRIVER_NAME "da9052-gpio" +static inline struct da9052_gpio_chip *to_da9052_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct da9052_gpio_chip, gp); +} + +void da9052_gpio_notifier(struct da9052_eh_nb *eh_data, unsigned int event) +{ + struct da9052_gpio_chip *gpio = + container_of(eh_data, struct da9052_gpio_chip, eh_data); + kobject_uevent(&gpio->gp.dev->kobj, KOBJ_CHANGE); + printk(KERN_INFO "GPIO8: GPIO\n"); +} + +static u8 create_gpio_config_value(u8 gpio_function, u8 gpio_type, u8 gpio_mode) +{ + /* The format is - + function - 2 bits + type - 1 bit + mode - 1 bit */ + return gpio_function | (gpio_type << 2) | (gpio_mode << 3); +} + +static s32 write_default_gpio_values(struct da9052 *da9052) +{ + struct da9052_ssc_msg msg; + u8 created_val = 0; + +#if (DA9052_GPIO_PIN_0 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0001_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO0_FUNCTION, + DEFAULT_GPIO0_TYPE, DEFAULT_GPIO0_MODE); + msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +#if (DA9052_GPIO_PIN_1 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0001_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO1_FUNCTION, + DEFAULT_GPIO1_TYPE, DEFAULT_GPIO1_MODE); + created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT; + msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +/* GPIO 2-3*/ +#if (DA9052_GPIO_PIN_2 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0203_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO2_FUNCTION, + DEFAULT_GPIO2_TYPE, DEFAULT_GPIO2_MODE); + msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +#if (DA9052_GPIO_PIN_3 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0203_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO3_FUNCTION, + DEFAULT_GPIO3_TYPE, DEFAULT_GPIO3_MODE); + created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT; + msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +/* GPIO 4-5*/ +#if (DA9052_GPIO_PIN_4 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0405_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO4_FUNCTION, + DEFAULT_GPIO4_TYPE, DEFAULT_GPIO4_MODE); + msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +#if (DA9052_GPIO_PIN_5 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0405_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO5_FUNCTION, + DEFAULT_GPIO5_TYPE, DEFAULT_GPIO5_MODE); + created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT; + msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +/* GPIO 6-7*/ +#if (DA9052_GPIO_PIN_6 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0607_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO6_FUNCTION, + DEFAULT_GPIO6_TYPE, DEFAULT_GPIO6_MODE); + msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +#if (DA9052_GPIO_PIN_7 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0607_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO7_FUNCTION, + DEFAULT_GPIO7_TYPE, DEFAULT_GPIO7_MODE); + created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT; + msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +/* GPIO 8-9*/ +#if (DA9052_GPIO_PIN_8 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0809_REG; + msg.data = 0; + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO8_FUNCTION, + DEFAULT_GPIO8_TYPE, DEFAULT_GPIO8_MODE); + msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +#if (DA9052_GPIO_PIN_9 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO0809_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO9_FUNCTION, + DEFAULT_GPIO9_TYPE, DEFAULT_GPIO9_MODE); + created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT; + msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +/* GPIO 10-11*/ +#if (DA9052_GPIO_PIN_10 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO1011_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO10_FUNCTION, + DEFAULT_GPIO10_TYPE, DEFAULT_GPIO10_MODE); + msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +#if (DA9052_GPIO_PIN_11 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO1011_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO11_FUNCTION, + DEFAULT_GPIO11_TYPE, DEFAULT_GPIO11_MODE); + created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT; + msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +/* GPIO 12-13*/ +#if (DA9052_GPIO_PIN_12 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO1213_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO12_FUNCTION, + DEFAULT_GPIO12_TYPE, DEFAULT_GPIO12_MODE); + msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +#if (DA9052_GPIO_PIN_13 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO1213_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO13_FUNCTION, + DEFAULT_GPIO13_TYPE, DEFAULT_GPIO13_MODE); + created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT; + msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +/* GPIO 14-15*/ +#if (DA9052_GPIO_PIN_14 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO1415_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO14_FUNCTION, + DEFAULT_GPIO14_TYPE, DEFAULT_GPIO14_MODE); + msg.data &= DA9052_GPIO_MASK_UPPER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif +#if (DA9052_GPIO_PIN_15 == DA9052_GPIO_CONFIG) + da9052_lock(da9052); + msg.addr = DA9052_GPIO1415_REG; + msg.data = 0; + + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + + created_val = create_gpio_config_value(DEFAULT_GPIO15_FUNCTION, + DEFAULT_GPIO15_TYPE, DEFAULT_GPIO15_MODE); + created_val = created_val << DA9052_GPIO_NIBBLE_SHIFT; + msg.data &= DA9052_GPIO_MASK_LOWER_NIBBLE; + msg.data |= created_val; + + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); +#endif + return 0; +} + +s32 da9052_gpio_read_port(struct da9052_gpio_read_write *read_port, + struct da9052 *da9052) +{ + struct da9052_ssc_msg msg; + u8 shift_value = 0; + u8 port_functionality = 0; + msg.addr = (read_port->port_number / 2) + DA9052_GPIO0001_REG; + msg.data = 0; + da9052_lock(da9052); + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); + port_functionality = + (read_port->port_number % 2) ? + ((msg.data & DA9052_GPIO_ODD_PORT_FUNCTIONALITY) >> + DA9052_GPIO_NIBBLE_SHIFT) : + (msg.data & DA9052_GPIO_EVEN_PORT_FUNCTIONALITY); + + if (port_functionality != INPUT) + return DA9052_GPIO_INVALID_PORTNUMBER; + + if (read_port->port_number >= (DA9052_GPIO_MAX_PORTNUMBER)) + return DA9052_GPIO_INVALID_PORTNUMBER; + + if (read_port->port_number < DA9052_GPIO_MAX_PORTS_PER_REGISTER) + msg.addr = DA9052_STATUSC_REG; + else + msg.addr = DA9052_STATUSD_REG; + msg.data = 0; + + da9052_lock(da9052); + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); + + shift_value = msg.data & + (1 << DA9052_GPIO_SHIFT_COUNT(read_port->port_number)); + read_port->read_write_value = (shift_value >> + DA9052_GPIO_SHIFT_COUNT(read_port->port_number)); + + return 0; +} + +s32 da9052_gpio_multiple_read(struct da9052_gpio_multiple_read *multiple_port, + struct da9052 *da9052) +{ + struct da9052_ssc_msg msg[2]; + u8 port_number = 0; + u8 loop_index = 0; + msg[loop_index++].addr = DA9052_STATUSC_REG; + msg[loop_index++].addr = DA9052_STATUSD_REG; + + da9052_lock(da9052); + if (da9052->read_many(da9052, msg, loop_index)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); + loop_index = 0; + for (port_number = 0; port_number < DA9052_GPIO_MAX_PORTS_PER_REGISTER; + port_number++) { + multiple_port->signal_value[port_number] = + msg[loop_index].data & 1; + msg[loop_index].data = msg[loop_index].data >> 1; + } + loop_index++; + for (port_number = DA9052_GPIO_MAX_PORTS_PER_REGISTER; + port_number < DA9052_GPIO_MAX_PORTNUMBER; port_number++) { + multiple_port->signal_value[port_number] = + msg[loop_index].data & 1; + msg[loop_index].data = msg[loop_index].data >> 1; + } + return 0; +} +EXPORT_SYMBOL(da9052_gpio_multiple_read); + +s32 da9052_gpio_write_port(struct da9052_gpio_read_write *write_port, + struct da9052 *da9052) +{ + struct da9052_ssc_msg msg; + u8 port_functionality = 0; + u8 bit_pos = 0; + msg.addr = DA9052_GPIO0001_REG + (write_port->port_number / 2); + msg.data = 0; + + da9052_lock(da9052); + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); + + port_functionality = + (write_port->port_number % 2) ? + ((msg.data & DA9052_GPIO_ODD_PORT_FUNCTIONALITY) >> + DA9052_GPIO_NIBBLE_SHIFT) : + (msg.data & DA9052_GPIO_EVEN_PORT_FUNCTIONALITY); + + if (port_functionality < 2) + return DA9052_GPIO_INVALID_PORTNUMBER; + + bit_pos = (write_port->port_number % 2) ? + DA9052_GPIO_ODD_PORT_WRITE_MODE : + DA9052_GPIO_EVEN_PORT_WRITE_MODE; + + if (write_port->read_write_value) + msg.data = msg.data | bit_pos; + else + msg.data = (msg.data & ~(bit_pos)); + + da9052_lock(da9052); + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); + return 0; +} + +s32 da9052_gpio_configure_port(struct da9052_gpio *gpio_data, + struct da9052 *da9052) +{ + struct da9052_ssc_msg msg; + u8 register_value = 0; + u8 function = 0; + u8 port_functionality = 0; + msg.addr = (gpio_data->port_number / 2) + DA9052_GPIO0001_REG; + msg.data = 0; + + da9052_lock(da9052); + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); + + port_functionality = + (gpio_data->port_number % 2) ? + ((msg.data & DA9052_GPIO_ODD_PORT_FUNCTIONALITY) >> + DA9052_GPIO_NIBBLE_SHIFT) : + (msg.data & DA9052_GPIO_EVEN_PORT_FUNCTIONALITY); + if (port_functionality < INPUT) + return DA9052_GPIO_INVALID_PORTNUMBER; + if (gpio_data->gpio_config.input.type > ACTIVE_HIGH) + return DA9052_GPIO_INVALID_TYPE; + if (gpio_data->gpio_config.input.mode > DEBOUNCING_ON) + return DA9052_GPIO_INVALID_MODE; + function = gpio_data->gpio_function; + switch (function) { + case INPUT: + register_value = create_gpio_config_value(function, + gpio_data->gpio_config.input.type, + gpio_data->gpio_config.input.mode); + break; + case OUTPUT_OPENDRAIN: + case OUTPUT_PUSHPULL: + register_value = create_gpio_config_value(function, + gpio_data->gpio_config.input.type, + gpio_data->gpio_config.input.mode); + break; + default: + return DA9052_GPIO_INVALID_FUNCTION; + break; + } + + if (gpio_data->port_number % 2) { + msg.data = (msg.data & ~(DA9052_GPIO_MASK_UPPER_NIBBLE)) | + (register_value << DA9052_GPIO_NIBBLE_SHIFT); + } else { + msg.data = (msg.data & ~(DA9052_GPIO_MASK_LOWER_NIBBLE)) | + register_value; + } + da9052_lock(da9052); + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + return -EIO; + } + da9052_unlock(da9052); + return 0; +} + +static s32 da9052_gpio_read(struct gpio_chip *gc, u32 offset) +{ + struct da9052_gpio_chip *gpio; + gpio = to_da9052_gpio(gc); + gpio->read_write.port_number = offset; + da9052_gpio_read_port(&gpio->read_write, gpio->da9052); + return gpio->read_write.read_write_value; +} + +static void da9052_gpio_write(struct gpio_chip *gc, u32 offset, s32 value) +{ + struct da9052_gpio_chip *gpio; + gpio = to_da9052_gpio(gc); + gpio->read_write.port_number = offset; + gpio->read_write.read_write_value = (u8)value; + da9052_gpio_write_port(&gpio->read_write, gpio->da9052); +} + +static s32 da9052_gpio_ip(struct gpio_chip *gc, u32 offset) +{ + struct da9052_gpio_chip *gpio; + gpio = to_da9052_gpio(gc); + gpio->gpio.gpio_function = INPUT; + gpio->gpio.gpio_config.input.type = ACTIVE_LOW; + gpio->gpio.gpio_config.input.mode = DEBOUNCING_ON; + gpio->gpio.port_number = offset; + return da9052_gpio_configure_port(&gpio->gpio, gpio->da9052); +} + +static s32 da9052_gpio_op(struct gpio_chip *gc, u32 offset, s32 value) +{ + struct da9052_gpio_chip *gpio; + gpio = to_da9052_gpio(gc); + gpio->gpio.gpio_function = OUTPUT_PUSHPULL; + gpio->gpio.gpio_config.output.type = SUPPLY_VDD_IO1; + gpio->gpio.gpio_config.output.mode = value; + gpio->gpio.port_number = offset; + return da9052_gpio_configure_port(&gpio->gpio, gpio->da9052); +} + +static int da9052_gpio_to_irq(struct gpio_chip *gc, u32 offset) +{ + struct da9052_gpio_chip *gpio; + gpio = to_da9052_gpio(gc); + kobject_uevent(&gpio->gp.dev->kobj, KOBJ_CHANGE); + printk(KERN_INFO"gpio->gp.base +offset = %d\n", gpio->gp.base + offset); + printk(KERN_INFO"Test1\n\n"); + return gpio->gp.base + offset; +} + +static int __devinit da9052_gpio_probe(struct platform_device *pdev) +{ + struct da9052_gpio_chip *gpio; + struct da9052_platform_data *pdata = (pdev->dev.platform_data); + s32 ret; + gpio = kzalloc(sizeof(*gpio), GFP_KERNEL); + if (gpio == NULL) + return -ENOMEM; + gpio->da9052 = dev_get_drvdata(pdev->dev.parent); + gpio->gp.get = da9052_gpio_read; + gpio->gp.direction_input = da9052_gpio_ip; + gpio->gp.direction_output = da9052_gpio_op; + gpio->gp.set = da9052_gpio_write; + + gpio->gp.base = pdata->gpio_base; + gpio->gp.ngpio = DA9052_GPIO_MAX_PORTNUMBER; + gpio->gp.can_sleep = 1; + gpio->gp.dev = &pdev->dev; + gpio->gp.owner = THIS_MODULE; + gpio->gp.label = "da9052-gpio"; + gpio->gp.to_irq = da9052_gpio_to_irq; + + gpio->eh_data.eve_type = GPI8_EVE; + gpio->eh_data.call_back = &da9052_gpio_notifier; + ret = gpio->da9052->register_event_notifier(gpio->da9052, + &gpio->eh_data); + + ret = write_default_gpio_values(gpio->da9052); + if (ret < 0) { + dev_err(&pdev->dev, "GPIO initial config failed, %d\n", + ret); + goto ret; + } + + ret = gpiochip_add(&gpio->gp); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip, %d\n", + ret); + goto ret; + } + platform_set_drvdata(pdev, gpio); + + return ret; + +ret: + kfree(gpio); + return ret; + +} + +static int __devexit da9052_gpio_remove(struct platform_device *pdev) +{ + struct da9052_gpio_chip *gpio = platform_get_drvdata(pdev); + int ret; + + gpio->da9052->unregister_event_notifier + (gpio->da9052, &gpio->eh_data); + ret = gpiochip_remove(&gpio->gp); + if (ret == 0) + kfree(gpio); + return 0; +} + +static struct platform_driver da9052_gpio_driver = { + .probe = da9052_gpio_probe, + .remove = __devexit_p(da9052_gpio_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init da9052_gpio_init(void) +{ + return platform_driver_register(&da9052_gpio_driver); +} + +static void __exit da9052_gpio_exit(void) +{ + return platform_driver_unregister(&da9052_gpio_driver); +} + +module_init(da9052_gpio_init); +module_exit(da9052_gpio_exit); + +MODULE_AUTHOR("David Dajun Chen "); +MODULE_DESCRIPTION("DA9052 GPIO Device Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index e19cf8eb6ccf..b0fdae27b74c 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -300,6 +300,16 @@ config SENSORS_ATXP1 This driver can also be built as a module. If so, the module will be called atxp1. +config SENSORS_DA9052 + tristate "Dialog DA9052 HWMon" + depends on PMIC_DA9052 + help + Say y here to support the ADC found on + Dialog Semiconductor DA9052 PMIC. + + This driver can also be built as a module. If so, the module + will be called da9052_hwmon. + config SENSORS_DS1621 tristate "Dallas Semiconductor DS1621 and DS1625" depends on I2C @@ -652,6 +662,15 @@ config SENSORS_MAX1619 This driver can also be built as a module. If so, the module will be called max1619. +config SENSORS_MAX17135 + tristate "Maxim MAX17135" + depends on I2C + help + If you say yes here you get support for MAX17135 PMIC sensor. + + This driver can also be built as a module. If so, the module + will be called max17135_sensor. + config SENSORS_MAX6650 tristate "Maxim MAX6650 sensor chip" depends on I2C && EXPERIMENTAL @@ -1166,4 +1185,24 @@ config SENSORS_LIS3LV02D endif # ACPI +config MXC_MMA7450 + tristate "MMA7450 device driver" + depends on MACH_MX31_3DS || MACH_MX23EVK + default n + +config SENSORS_ISL29003 + tristate "ISL29003 Light Sensor" + depends on MACH_MX37_3DS || MACH_MX51_3DS + default y + +config MXC_MMA8450 + tristate "MMA8450 device driver" + depends on I2C + default y + +config MXC_MMA8451 + tristate "MMA8451 device driver" + depends on I2C + default y + endif # HWMON diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 2138ceb1a713..0dfdc7826dfa 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_SENSORS_AMS) += ams/ obj-$(CONFIG_SENSORS_ASC7621) += asc7621.o obj-$(CONFIG_SENSORS_ATXP1) += atxp1.o obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o +obj-$(CONFIG_SENSORS_DA9052) += da9052-adc.o obj-$(CONFIG_SENSORS_DME1737) += dme1737.o obj-$(CONFIG_SENSORS_DS1621) += ds1621.o obj-$(CONFIG_SENSORS_EMC1403) += emc1403.o @@ -78,6 +79,7 @@ obj-$(CONFIG_SENSORS_LTC4215) += ltc4215.o obj-$(CONFIG_SENSORS_LTC4245) += ltc4245.o obj-$(CONFIG_SENSORS_MAX1111) += max1111.o obj-$(CONFIG_SENSORS_MAX1619) += max1619.o +obj-$(CONFIG_SENSORS_MAX17135) += max17135-hwmon.o obj-$(CONFIG_SENSORS_MAX6650) += max6650.o obj-$(CONFIG_SENSORS_MC13783_ADC)+= mc13783-adc.o obj-$(CONFIG_SENSORS_PC87360) += pc87360.o @@ -103,6 +105,10 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o +obj-$(CONFIG_SENSORS_ISL29003) += isl29003.o +obj-$(CONFIG_MXC_MMA7450) += mxc_mma7450.o +obj-$(CONFIG_MXC_MMA8450) += mxc_mma8450.o +obj-$(CONFIG_MXC_MMA8451) += mxc_mma8451.o ifeq ($(CONFIG_HWMON_DEBUG_CHIP),y) EXTRA_CFLAGS += -DDEBUG diff --git a/drivers/hwmon/da9052-adc.c b/drivers/hwmon/da9052-adc.c new file mode 100644 index 000000000000..647e580e2131 --- /dev/null +++ b/drivers/hwmon/da9052-adc.c @@ -0,0 +1,644 @@ +/* + * da9052-adc.c -- ADC Driver for Dialog DA9052 + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * Author: Dialog Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "da9052-adc" + +static const char *input_names[] = { + [DA9052_ADC_VDDOUT] = "VDDOUT", + [DA9052_ADC_ICH] = "CHARGING CURRENT", + [DA9052_ADC_TBAT] = "BATTERY TEMP", + [DA9052_ADC_VBAT] = "BATTERY VOLTAGE", + [DA9052_ADC_ADCIN4] = "ADC INPUT 4", + [DA9052_ADC_ADCIN5] = "ADC INPUT 5", + [DA9052_ADC_ADCIN6] = "ADC INPUT 6", + [DA9052_ADC_TSI] = "TSI", + [DA9052_ADC_TJUNC] = "BATTERY JUNCTION TEMP", + [DA9052_ADC_VBBAT] = "BACK-UP BATTERY TEMP", +}; + + +int da9052_manual_read(struct da9052 *da9052, + unsigned char channel) +{ + unsigned char man_timeout_cnt = DA9052_ADC_MAX_MANCONV_RETRY_COUNT; + struct da9052_ssc_msg msg; + unsigned short calc_data; + unsigned int ret; + u16 data = 0; + + msg.addr = DA9052_ADCMAN_REG; + msg.data = channel; + msg.data = (msg.data | DA9052_ADCMAN_MANCONV); + + mutex_lock(&da9052->manconv_lock); + da9052_lock(da9052); + + ret = da9052->write(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + + /* Wait for the event */ + do { + msg.addr = DA9052_ADCCONT_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + + if (DA9052_ADCCONT_ADCMODE & msg.data) + msleep(1); + else + msleep(10); + + msg.addr = DA9052_ADCMAN_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + + /* Counter to avoid endless while loop */ + man_timeout_cnt--; + if (man_timeout_cnt == 1) { + if (!(msg.data & DA9052_ADCMAN_MANCONV)) + break; + else + goto err_ssc_comm; + } + /* Wait until the MAN_CONV bit is cleared to zero */ + } while (msg.data & DA9052_ADCMAN_MANCONV); + + msg.addr = DA9052_ADCRESH_REG; + msg.data = 0; + + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + + calc_data = (unsigned short)msg.data; + data = (calc_data << 2); + + msg.addr = DA9052_ADCRESL_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + + /* Clear first 14 bits before ORing */ + calc_data = (unsigned short)msg.data & 0x0003; + data |= calc_data; + + mutex_unlock(&da9052->manconv_lock); + + return data; +err_ssc_comm: + mutex_unlock(&da9052->manconv_lock); + da9052_unlock(da9052); + return -EIO; +} +EXPORT_SYMBOL(da9052_manual_read); + +int da9052_read_tjunc(struct da9052 *da9052, char *buf) +{ + struct da9052_ssc_msg msg; + unsigned char temp; + int ret; + + msg.addr = DA9052_TJUNCRES_REG; + msg.data = 0; + + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + + temp = msg.data; + + msg.addr = DA9052_TOFFSET_REG; + msg.data = 0; + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + /* Calculate Junction temperature */ + temp = (temp - msg.data); + *buf = temp; + return 0; +err_ssc_comm: + da9052_unlock(da9052); + return -EIO; +} +EXPORT_SYMBOL(da9052_read_tjunc); + +int da9052_read_tbat_ich(struct da9052 *da9052, char *data, int channel_no) +{ + struct da9052_ssc_msg msg; + int ret; + + /* Read TBAT conversion result */ + switch (channel_no) { + case DA9052_ADC_TBAT: + msg.addr = DA9052_TBATRES_REG; + break; + case DA9052_ADC_ICH: + msg.addr = DA9052_ICHGAV_REG; + break; + default: + return -EINVAL; + } + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + *data = msg.data; + printk(KERN_INFO"msg.data 1= %d\n", msg.data); + msg.data = 28; + da9052_lock(da9052); + ret = da9052->write(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + printk(KERN_INFO"msg.data2 = %d\n", msg.data); + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + da9052_unlock(da9052); + printk(KERN_INFO"msg.data3 = %d\n", msg.data); + return 0; + +err_ssc_comm: + da9052_unlock(da9052); + return ret; +} +EXPORT_SYMBOL(da9052_read_tbat_ich); + +static int da9052_start_adc(struct da9052 *da9052, unsigned channel) +{ + struct da9052_ssc_msg msg; + int ret; + + msg.addr = DA9052_ADCCONT_REG; + msg.data = 0; + + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + + if (channel == DA9052_ADC_VDDOUT) + msg.data = (msg.data | DA9052_ADCCONT_AUTOVDDEN); + else if (channel == DA9052_ADC_ADCIN4) + msg.data = (msg.data | DA9052_ADCCONT_AUTOAD4EN); + else if (channel == DA9052_ADC_ADCIN5) + msg.data = (msg.data | DA9052_ADCCONT_AUTOAD5EN); + else if (channel == DA9052_ADC_ADCIN6) + msg.data = (msg.data | DA9052_ADCCONT_AUTOAD6EN); + else + return -EINVAL; + + ret = da9052->write(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + da9052_unlock(da9052); + return 0; + +err_ssc_comm: + da9052_unlock(da9052); + return -EIO; +} + +static int da9052_stop_adc(struct da9052 *da9052, unsigned channel) +{ + int ret; + struct da9052_ssc_msg msg; + + msg.addr = DA9052_ADCCONT_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + + if (channel == DA9052_ADC_VDDOUT) + msg.data = (msg.data & ~(DA9052_ADCCONT_AUTOVDDEN)); + else if (channel == DA9052_ADC_ADCIN4) + msg.data = (msg.data & ~(DA9052_ADCCONT_AUTOAD4EN)); + else if (channel == DA9052_ADC_ADCIN5) + msg.data = (msg.data & ~(DA9052_ADCCONT_AUTOAD5EN)); + else if (channel == DA9052_ADC_ADCIN6) + msg.data = (msg.data & ~(DA9052_ADCCONT_AUTOAD6EN)); + else + return -EINVAL; + + ret = da9052->write(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + da9052_unlock(da9052); + + return 0; +err_ssc_comm: + da9052_unlock(da9052); + return -EIO; +} + +static ssize_t da9052_adc_read_start_stop(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct da9052_adc_priv *priv = platform_get_drvdata(pdev); + struct da9052_ssc_msg msg; + int channel = to_sensor_dev_attr(devattr)->index; + int ret; + + ret = da9052_start_adc(priv->da9052, channel); + if (ret < 0) + return ret; + + /* Read the ADC converted value */ + switch (channel) { + case DA9052_ADC_VDDOUT: + msg.addr = DA9052_VDDRES_REG; + break; +#if (DA9052_ADC_CONF_ADC4 == 1) + case DA9052_ADC_ADCIN4: + msg.addr = DA9052_ADCIN4RES_REG; + break; +#endif +#if (DA9052_ADC_CONF_ADC5 == 1) + case DA9052_ADC_ADCIN5: + msg.addr = DA9052_ADCIN5RES_REG; + break; +#endif +#if (DA9052_ADC_CONF_ADC6 == 1) + case DA9052_ADC_ADCIN6: + msg.addr = DA9052_ADCIN6RES_REG; + break; +#endif + default: + return -EINVAL; + } + msg.data = 0; + da9052_lock(priv->da9052); + ret = priv->da9052->read(priv->da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + da9052_unlock(priv->da9052); + + ret = da9052_stop_adc(priv->da9052, channel); + if (ret < 0) + return ret; + + return sprintf(buf, "%u\n", msg.data); + +err_ssc_comm: + da9052_unlock(priv->da9052); + return ret; +} + +static ssize_t da9052_adc_read_ich(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct da9052_adc_priv *priv = platform_get_drvdata(pdev); + int ret; + + ret = da9052_read_tbat_ich(priv->da9052, buf, DA9052_ADC_ICH); + if (ret < 0) + return ret; + return sprintf(buf, "%u\n", *buf); +} + +static ssize_t da9052_adc_read_tbat(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct da9052_adc_priv *priv = platform_get_drvdata(pdev); + int ret; + + ret = da9052_read_tbat_ich(priv->da9052, buf, DA9052_ADC_TBAT); + if (ret < 0) + return ret; + return sprintf(buf, "%u\n", *buf); +} + +static ssize_t da9052_adc_read_vbat(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct da9052_adc_priv *priv = platform_get_drvdata(pdev); + s32 ret; + + ret = da9052_manual_read(priv->da9052, DA9052_ADC_VBAT); + if (ret < 0) + return ret; + return sprintf(buf, "%u\n", ret); +} + +static ssize_t da9052_adc_read_tjunc(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct da9052_adc_priv *priv = platform_get_drvdata(pdev); + int ret; + ret = da9052_read_tjunc(priv->da9052, buf); + if (ret < 0) + return ret; + return sprintf(buf, "%u\n", *buf); +} + +static ssize_t da9052_adc_read_vbbat(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct da9052_adc_priv *priv = platform_get_drvdata(pdev); + s32 ret; + + ret = da9052_manual_read(priv->da9052, DA9052_ADC_VBBAT); + if (ret < 0) + return ret; + return sprintf(buf, "%u\n", ret); +} + +static int da9052_adc_hw_init(struct da9052 *da9052) +{ + struct da9052_ssc_msg msg; + int ret; + + /* ADC channel 4 and 5 are by default enabled */ +#if (DA9052_ADC_CONF_ADC4 == 1) + msg.addr = DA9052_GPIO0001_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + + msg.data = (msg.data & ~(DA9052_GPIO0001_GPIO0PIN)); + ret = da9052->write(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + da9052_unlock(da9052); +#endif + +#if (DA9052_ADC_CONF_ADC5 == 1) + msg.addr = DA9052_GPIO0001_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + + msg.data = (msg.data & ~(DA9052_GPIO0001_GPIO0PIN)); + ret = da9052->write(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + da9052_unlock(da9052); +#endif + +#if (DA9052_ADC_CONF_ADC6 == 1) + msg.addr = DA9052_GPIO0203_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto err_ssc_comm; + + msg.data = (msg.data & ~(DA9052_GPIO0203_GPIO2PIN)); + ret = da9052->write(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + da9052_unlock(da9052); +#endif +#if 0 + /* By default configure the Measurement sequence interval to 10ms */ + msg.addr = DA9052_ADCCONT_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + + /* Set the ADC MODE bit for 10msec sampling timer */ + msg.data = (msg.data & ~(DA9052_ADCCONT_ADCMODE)); + ret = da9052->write(da9052, &msg); + if (ret != 0) + goto err_ssc_comm; + da9052_unlock(da9052); +#endif + return 0; +err_ssc_comm: + da9052_unlock(da9052); + return -EIO; +} + +static ssize_t da9052_adc_show_name(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + return sprintf(buf, "da9052-adc\n"); +} + +static ssize_t show_label(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + int channel = to_sensor_dev_attr(devattr)->index; + + return sprintf(buf, "%s\n", input_names[channel]); +} +#define DA9052_ADC_CHANNELS(id, name) \ + static SENSOR_DEVICE_ATTR(in##id##_label, S_IRUGO, show_label, \ + NULL, name) + +DA9052_ADC_CHANNELS(0, DA9052_ADC_VDDOUT); +DA9052_ADC_CHANNELS(1, DA9052_ADC_ICH); +DA9052_ADC_CHANNELS(2, DA9052_ADC_TBAT); +DA9052_ADC_CHANNELS(3, DA9052_ADC_VBAT); +#if (DA9052_ADC_CONF_ADC4 == 1) +DA9052_ADC_CHANNELS(4, DA9052_ADC_ADCIN4); +#endif +#if (DA9052_ADC_CONF_ADC5 == 1) +DA9052_ADC_CHANNELS(5, DA9052_ADC_ADCIN5); +#endif +#if (DA9052_ADC_CONF_ADC6 == 1) +DA9052_ADC_CHANNELS(6, DA9052_ADC_ADCIN6); +#endif +DA9052_ADC_CHANNELS(7, DA9052_ADC_TSI); +DA9052_ADC_CHANNELS(8, DA9052_ADC_TJUNC); +DA9052_ADC_CHANNELS(9, DA9052_ADC_VBBAT); + + +static DEVICE_ATTR(name, S_IRUGO, da9052_adc_show_name, NULL); +static SENSOR_DEVICE_ATTR(read_vddout, S_IRUGO, + da9052_adc_read_start_stop, NULL, + DA9052_ADC_VDDOUT); +static SENSOR_DEVICE_ATTR(read_ich, S_IRUGO, da9052_adc_read_ich, NULL, + DA9052_ADC_ICH); +static SENSOR_DEVICE_ATTR(read_tbat, S_IRUGO, da9052_adc_read_tbat, NULL, + DA9052_ADC_TBAT); +static SENSOR_DEVICE_ATTR(read_vbat, S_IRUGO, da9052_adc_read_vbat, NULL, + DA9052_ADC_VBAT); +#if (DA9052_ADC_CONF_ADC4 == 1) +static SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, da9052_adc_read_start_stop, NULL, + DA9052_ADC_ADCIN4); +#endif +#if (DA9052_ADC_CONF_ADC5 == 1) +static SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, da9052_adc_read_start_stop, NULL, + DA9052_ADC_ADCIN5); +#endif +#if (DA9052_ADC_CONF_ADC6 == 1) +static SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, da9052_adc_read_start_stop, NULL, + DA9052_ADC_ADCIN6); +#endif +static SENSOR_DEVICE_ATTR(read_tjunc, S_IRUGO, da9052_adc_read_tjunc, NULL, + DA9052_ADC_TJUNC); +static SENSOR_DEVICE_ATTR(read_vbbat, S_IRUGO, da9052_adc_read_vbbat, NULL, + DA9052_ADC_VBBAT); + +static struct attribute *da9052_attr[] = { + &dev_attr_name.attr, + &sensor_dev_attr_read_vddout.dev_attr.attr, + &sensor_dev_attr_in0_label.dev_attr.attr, + &sensor_dev_attr_read_ich.dev_attr.attr, + &sensor_dev_attr_in1_label.dev_attr.attr, + &sensor_dev_attr_read_tbat.dev_attr.attr, + &sensor_dev_attr_in2_label.dev_attr.attr, + &sensor_dev_attr_read_vbat.dev_attr.attr, + &sensor_dev_attr_in3_label.dev_attr.attr, +#if (DA9052_ADC_CONF_ADC4 == 1) + &sensor_dev_attr_in4_input.dev_attr.attr, + &sensor_dev_attr_in4_label.dev_attr.attr, +#endif +#if (DA9052_ADC_CONF_ADC5 == 1) + &sensor_dev_attr_in5_input.dev_attr.attr, + &sensor_dev_attr_in5_label.dev_attr.attr, +#endif +#if (DA9052_ADC_CONF_ADC6 == 1) + &sensor_dev_attr_in6_input.dev_attr.attr, + &sensor_dev_attr_in6_label.dev_attr.attr, +#endif + &sensor_dev_attr_in7_label.dev_attr.attr, + &sensor_dev_attr_read_tjunc.dev_attr.attr, + &sensor_dev_attr_in8_label.dev_attr.attr, + &sensor_dev_attr_read_vbbat.dev_attr.attr, + &sensor_dev_attr_in9_label.dev_attr.attr, + NULL +}; + +static const struct attribute_group da9052_group = { + .attrs = da9052_attr, +}; + +static int __init da9052_adc_probe(struct platform_device *pdev) +{ + struct da9052_adc_priv *priv; + int ret; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->da9052 = dev_get_drvdata(pdev->dev.parent); + + platform_set_drvdata(pdev, priv); + + /* Register sysfs hooks */ + ret = sysfs_create_group(&pdev->dev.kobj, &da9052_group); + if (ret) + goto out_err_create1; + + priv->hwmon_dev = hwmon_device_register(&pdev->dev); + if (IS_ERR(priv->hwmon_dev)) { + ret = PTR_ERR(priv->hwmon_dev); + goto out_err_create2; + } + /* Initializes the hardware for ADC module */ + da9052_adc_hw_init(priv->da9052); + + /* Initialize mutex required for ADC Manual read */ + mutex_init(&priv->da9052->manconv_lock); + + return 0; + +out_err_create2: + sysfs_remove_group(&pdev->dev.kobj, &da9052_group); +out_err_create1: + platform_set_drvdata(pdev, NULL); + kfree(priv); + + return ret; +} + +static int __devexit da9052_adc_remove(struct platform_device *pdev) +{ + struct da9052_adc_priv *priv = platform_get_drvdata(pdev); + + mutex_destroy(&priv->da9052->manconv_lock); + + hwmon_device_unregister(priv->hwmon_dev); + + sysfs_remove_group(&pdev->dev.kobj, &da9052_group); + + platform_set_drvdata(pdev, NULL); + kfree(priv); + + return 0; +} + +static struct platform_driver da9052_adc_driver = { + .remove = __devexit_p(da9052_adc_remove), + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + }, +}; + +static int __init da9052_adc_init(void) +{ + return platform_driver_probe(&da9052_adc_driver, da9052_adc_probe); +} +module_init(da9052_adc_init); + +static void __exit da9052_adc_exit(void) +{ + platform_driver_unregister(&da9052_adc_driver); +} +module_exit(da9052_adc_exit); + +MODULE_AUTHOR("David Dajun Chen ") +MODULE_DESCRIPTION("DA9052 ADC driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/hwmon/isl29003.c b/drivers/hwmon/isl29003.c new file mode 100644 index 000000000000..18c9947b3cd8 --- /dev/null +++ b/drivers/hwmon/isl29003.c @@ -0,0 +1,439 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/hwmon/isl29003.c + * + * @brief ISL29003 light sensor Driver + * + * @ingroup + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum isl29003_width { + ISL29003_WIDTH_16 = 0, + ISL29003_WIDTH_12, + ISL29003_WIDTH_8, + ISL29003_WIDTH_4, +}; + +enum isl29003_gain { + ISL29003_GAIN_1000 = 0, + ISL29003_GAIN_4000, + ISL29003_GAIN_16000, + ISL29003_GAIN_64000, +}; + +enum isl29003_mode { + ISL29003_MODE_DIODE1 = 0, + ISL29003_MODE_DIODE2, + ISL29003_MODE_DIODE1_2, +}; + +struct isl29003_param { + enum isl29003_width width; + enum isl29003_gain gain; + enum isl29003_mode mode; +}; + +/* bit definition for ISL29003_CMD reg */ +#define ENABLE 7 +#define ADCPD 6 +#define TIMEING_MODE 5 +#define MODE 2 +#define WIDTH 0 + +/* bit definition for ISL29003_CTRL reg */ +#define INT_FLAG 5 +#define GAIN 2 +#define INT_PERSIST 0 + +enum isl29003_reg { + ISL29003_CMD = 0, + ISL29003_CTRL, + ISL29003_THRS_HI, + ISL29003_THRS_LO, + ISL29003_LSB_S, + ISL29003_MSB_S, + ISL29003_LSB_T, + ISL29003_MSB_T, + ISL29003_SYNC_IIC = 0x80, + ISL29003_CLAR_INT = 0x40 +}; + +/* default configure for ISL29003 */ +#define ISL29003_WIDTH_DEFAULT ISL29003_WIDTH_16 +#define ISL29003_GAIN_DEFAULT ISL29003_GAIN_16000 +#define ISL29003_MODE_DEFAULT ISL29003_MODE_DIODE1 + +/* range table for different GAIN settings */ +int range[4] = { 973, 3892, 15568, 62272 }; + +/* width table for different WIDTH settings */ +int width[4] = { 16, 1, 256, 16 }; + +struct isl29003_data { + struct i2c_client *client; + struct device *hwmon_dev; + struct regulator *vdd_reg; + struct isl29003_param param; + int lux_coeff; + unsigned char enable; +}; + +static struct i2c_client *isl29003_client; + +/*! + * This function do the isl29003 register read. + */ +int isl29003_read(struct i2c_client *client, u8 reg) +{ + return i2c_smbus_read_byte_data(client, reg); +} + +/*! + * This function do the isl29003 register write. + */ +int isl29003_write(struct i2c_client *client, u8 reg, char value) +{ + return i2c_smbus_write_byte_data(client, reg, value); +} + +/*! + * This function do the isl29003 config and enable. + */ +static int isl29003_on(void) +{ + unsigned char cmd; + int err = 0; + struct mxc_lightsensor_platform_data *ls_data; + struct isl29003_data *data = i2c_get_clientdata(isl29003_client); + + if (data->enable) + goto exit; + + ls_data = (struct mxc_lightsensor_platform_data *) + (isl29003_client->dev).platform_data; + + /* coeff=range*100k/rext/2^n */ + data->lux_coeff = range[data->param.gain] * 100 / + ls_data->rext / width[data->param.width]; + + if (data->vdd_reg) + regulator_enable(data->vdd_reg); + msleep(100); + + cmd = data->param.gain << GAIN; + if (isl29003_write(isl29003_client, ISL29003_CTRL, cmd)) { + err = -ENODEV; + goto exit; + } + + cmd = (data->param.width << WIDTH) | (data->param.mode << MODE) | + (1 << ENABLE); + if (isl29003_write(isl29003_client, ISL29003_CMD, cmd)) { + err = -ENODEV; + goto exit; + } + + data->enable = 1; + + pr_info("isl29003 on\n"); + return 0; +exit: + return err; +} + +/*! + * This function shut down the isl29003. + */ +static int isl29003_off(void) +{ + struct isl29003_data *data = i2c_get_clientdata(isl29003_client); + int cmd; + + if (!data->enable) + return 0; + + cmd = isl29003_read(isl29003_client, ISL29003_CMD); + if (cmd < 0) + return -ENODEV; + + cmd = ((cmd | (1 << ADCPD)) & (~(1 << ENABLE))); + if (isl29003_write(isl29003_client, ISL29003_CMD, (char)cmd)) + return -ENODEV; + + if (data->vdd_reg) + regulator_disable(data->vdd_reg); + + data->enable = 0; + + pr_info("isl29003 off\n"); + return 0; +} + +/*! + * This function read the isl29003 lux registers and convert them to the lux + * value. + * + * @output buffer this param holds the lux value, when =-1, read fail + * + * @return 0 + */ +static int isl29003_read_lux(void) +{ + int d; + int lux; + struct isl29003_data *data = i2c_get_clientdata(isl29003_client); + + d = isl29003_read(isl29003_client, ISL29003_MSB_S); + if (d < 0) + goto err; + + lux = d; + d = isl29003_read(isl29003_client, ISL29003_LSB_S); + if (d < 0) + goto err; + + lux = (lux << 8) + d; + + if (data->param.width < ISL29003_WIDTH_8) + lux = (data->lux_coeff * lux) >> 12; + else + lux = data->lux_coeff * lux; + + return lux; +err: + return -1; +} + +static ssize_t ls_enable(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + char *endp; + int enable = simple_strtoul(buf, &endp, 0); + size_t size = endp - buf; + + if (*endp && isspace(*endp)) + size++; + if (size != count) + return -EINVAL; + + if (enable == 1) { + if (isl29003_on()) + pr_info("device open fail\n"); + } + if (enable == 0) { + if (isl29003_off()) + pr_info("device powerdown fail\n"); + } + + return count; +} + +static SENSOR_DEVICE_ATTR(enable, S_IWUGO, NULL, ls_enable, 0); + +static ssize_t show_lux(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%u\n", isl29003_read_lux()); +} + +static SENSOR_DEVICE_ATTR(lux, S_IRUGO, show_lux, NULL, 0); + +static int isl29003_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *did) +{ + int err = 0; + struct isl29003_data *data; + struct regulator *vdd_reg; + struct mxc_lightsensor_platform_data *ls_data; + + ls_data = (struct mxc_lightsensor_platform_data *) + (client->dev).platform_data; + + if (ls_data && ls_data->vdd_reg) + vdd_reg = regulator_get(&client->dev, ls_data->vdd_reg); + else + vdd_reg = NULL; + + /* check the existence of the device */ + if (vdd_reg) + regulator_enable(vdd_reg); + msleep(100); + + if (isl29003_write(client, ISL29003_CMD, 0)) + err = -ENODEV; + + if (!err) + if (isl29003_read(client, ISL29003_CMD)) + err = -ENODEV; + + if (vdd_reg) + regulator_disable(vdd_reg); + if (err < 0) + goto exit1; + + isl29003_client = client; + data = kzalloc(sizeof(struct isl29003_data), GFP_KERNEL); + if (data == NULL) { + err = -ENOMEM; + goto exit1; + } + + i2c_set_clientdata(client, data); + data->client = client; + + data->param.width = ISL29003_WIDTH_DEFAULT; + data->param.gain = ISL29003_GAIN_DEFAULT; + data->param.mode = ISL29003_MODE_DEFAULT; + + data->enable = 0; + + err = device_create_file(&client->dev, + &sensor_dev_attr_enable.dev_attr); + if (err) + goto exit2; + + err = device_create_file(&client->dev, &sensor_dev_attr_lux.dev_attr); + if (err) + goto exit_remove1; + + /* Register sysfs hooks */ + data->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(data->hwmon_dev)) { + err = PTR_ERR(data->hwmon_dev); + goto exit_remove2; + } + + data->vdd_reg = vdd_reg; + return 0; + +exit_remove2: + device_remove_file(&client->dev, &sensor_dev_attr_lux.dev_attr); +exit_remove1: + device_remove_file(&client->dev, &sensor_dev_attr_enable.dev_attr); +exit2: + kfree(data); +exit1: + if (vdd_reg) { + regulator_put(vdd_reg); + vdd_reg = NULL; + } + isl29003_client = NULL; + return err; +} + +static int isl29003_i2c_remove(struct i2c_client *client) +{ + struct isl29003_data *data = i2c_get_clientdata(client); + + if (data->vdd_reg) { + regulator_put(data->vdd_reg); + data->vdd_reg = NULL; + } + hwmon_device_unregister(data->hwmon_dev); + device_remove_file(&client->dev, &sensor_dev_attr_enable.dev_attr); + device_remove_file(&client->dev, &sensor_dev_attr_lux.dev_attr); + kfree(data); + return 0; +} + +static int isl29003_suspend(struct i2c_client *client, pm_message_t message) +{ + int cmd; + + struct isl29003_data *data = i2c_get_clientdata(client); + + if (!data->enable) + goto exit; + + cmd = isl29003_read(client, ISL29003_CMD); + if (cmd < 0) + goto err; + + cmd = (cmd | (1 << ADCPD)); + if (isl29003_write(client, ISL29003_CMD, (char)cmd)) + goto err; +exit: + return 0; +err: + return -ENODEV; +} + +static int isl29003_resume(struct i2c_client *client) +{ + int cmd; + + struct isl29003_data *data = i2c_get_clientdata(client); + + if (!data->enable) + goto exit; + + cmd = isl29003_read(client, ISL29003_CMD); + if (cmd < 0) + goto err; + + cmd = (cmd & (~(1 << ADCPD))); + if (isl29003_write(client, ISL29003_CMD, (char)cmd)) + goto err; +exit: + return 0; +err: + return -ENODEV; +} + +static const struct i2c_device_id isl29003_id[] = { + {"isl29003", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, isl29003_id); + +static struct i2c_driver isl29003_driver = { + .driver = { + .name = "isl29003", + }, + .probe = isl29003_i2c_probe, + .remove = isl29003_i2c_remove, + .suspend = isl29003_suspend, + .resume = isl29003_resume, + .id_table = isl29003_id, +}; + +static int __init isl29003_init(void) +{ + return i2c_add_driver(&isl29003_driver);; +} + +static void __exit isl29003_cleanup(void) +{ + i2c_del_driver(&isl29003_driver); +} + +module_init(isl29003_init); +module_exit(isl29003_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("ISL29003 light sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hwmon/max17135-hwmon.c b/drivers/hwmon/max17135-hwmon.c new file mode 100644 index 000000000000..8aa9aadbd44a --- /dev/null +++ b/drivers/hwmon/max17135-hwmon.c @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * max17135.c + * + * Based on the MAX1619 driver. + * Copyright (C) 2003-2004 Alexey Fisher + * Jean Delvare + * + * The MAX17135 is a sensor chip made by Maxim. + * It reports up to two temperatures (its own plus up to + * one external one). + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Conversions + */ +static int temp_from_reg(int val) +{ + return val >> 8; +} + +/* + * Functions declaration + */ +static int max17135_sensor_probe(struct platform_device *pdev); +static int max17135_sensor_remove(struct platform_device *pdev); + +/* + * Driver data (common to all clients) + */ +static struct platform_driver max17135_sensor_driver = { + .probe = max17135_sensor_probe, + .remove = max17135_sensor_remove, + .driver = { + .name = "max17135_sensor", + }, +}; + + +/* + * Client data (each client gets its own) + */ +struct max17135_data { + struct device *hwmon_dev; +}; + +/* + * Sysfs stuff + */ +static ssize_t show_temp_input1(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int reg_val; + max17135_reg_read(REG_MAX17135_INT_TEMP, ®_val); + return snprintf(buf, PAGE_SIZE, "%d\n", temp_from_reg(reg_val)); +} + +static ssize_t show_temp_input2(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int reg_val; + max17135_reg_read(REG_MAX17135_EXT_TEMP, ®_val); + return snprintf(buf, PAGE_SIZE, "%d\n", temp_from_reg(reg_val)); +} + +show_temp(temp_input1); +show_temp(temp_input2); + +static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp_input1, NULL); +static DEVICE_ATTR(temp2_input, S_IRUGO, show_temp_input2, NULL); + +static struct attribute *max17135_attributes[] = { + &dev_attr_temp1_input.attr, + &dev_attr_temp2_input.attr, + NULL +}; + +static const struct attribute_group max17135_group = { + .attrs = max17135_attributes, +}; + +/* + * Real code + */ +static int max17135_sensor_probe(struct platform_device *pdev) +{ + struct max17135_data *data; + int err; + + data = kzalloc(sizeof(struct max17135_data), GFP_KERNEL); + if (!data) { + err = -ENOMEM; + goto exit; + } + + /* Register sysfs hooks */ + err = sysfs_create_group(&pdev->dev.kobj, &max17135_group); + if (err) + goto exit_free; + + data->hwmon_dev = hwmon_device_register(&pdev->dev); + if (IS_ERR(data->hwmon_dev)) { + err = PTR_ERR(data->hwmon_dev); + goto exit_remove_files; + } + + platform_set_drvdata(pdev, data); + + return 0; + +exit_remove_files: + sysfs_remove_group(&pdev->dev.kobj, &max17135_group); +exit_free: + kfree(data); +exit: + return err; +} + +static int max17135_sensor_remove(struct platform_device *pdev) +{ + struct max17135_data *data = platform_get_drvdata(pdev); + + hwmon_device_unregister(data->hwmon_dev); + sysfs_remove_group(&pdev->dev.kobj, &max17135_group); + + kfree(data); + return 0; +} + +static int __init sensors_max17135_init(void) +{ + return platform_driver_register(&max17135_sensor_driver); +} +module_init(sensors_max17135_init); + +static void __exit sensors_max17135_exit(void) +{ + platform_driver_unregister(&max17135_sensor_driver); +} +module_exit(sensors_max17135_exit); + +MODULE_DESCRIPTION("MAX17135 sensor driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/hwmon/mxc_mma7450.c b/drivers/hwmon/mxc_mma7450.c new file mode 100644 index 000000000000..fa1dd41267eb --- /dev/null +++ b/drivers/hwmon/mxc_mma7450.c @@ -0,0 +1,788 @@ +/* + * linux/drivers/hwmon/mma7450.c + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*include file*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*macro define*/ +#define MMA7450_I2C_ADDR 0x1D +#define DEVICE_NAME "mma7450" +#define POLL_INTERVAL 100 +#define DEBUG + +#define INPUT_FUZZ 4 +#define INPUT_FLAT 4 + +enum { + REG_XOUTL = 0x00, + REG_XOUTH, + REG_YOUTL, + REG_YOUTH, + REG_ZOUTL, + REG_ZOUTH, + REG_XOUT8, + REG_YOUT8, + REG_ZOUT8, + REG_STATUS, + REG_DETSRC, + REG_TOUT, + REG_RESERVED_0, + REG_I2CAD, + REG_USRINF, + REG_WHOAMI, + REG_XOFFL, + REG_XOFFH, + REG_YOFFL, + REG_YOFFH, + REG_ZOFFL, + REG_ZOFFH, + REG_MCTL, + REG_INTRST, + REG_CTL1, + REG_CTL2, + REG_LDTH, + REG_PDTH, + REG_PD, + REG_LT, + REG_TW, + REG_REVERVED_1, +}; + +enum { + MOD_STANDBY = 0, + MOD_MEASURE, + MOD_LEVEL_D, + MOD_PULSE_D, +}; + +enum { + INT_1L_2P = 0, + INT_1P_2L, + INT_1SP_2P, +}; + +struct mma7450_status { + u8 mod; + u8 ctl1; + u8 ctl2; +}; + +/*forward declear*/ +static ssize_t mma7450_show(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t mma7450_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count); +static int mma7450_probe(struct i2c_client *client, + const struct i2c_device_id *id); +static int mma7450_remove(struct i2c_client *client); +static int mma7450_suspend(struct i2c_client *client, pm_message_t state); +static int mma7450_resume(struct i2c_client *client); +static void mma_bh_handler(struct work_struct *work); + +/*definition*/ +static struct regulator *reg_dvdd_io; +static struct regulator *reg_avdd; +static struct i2c_client *mma7450_client; +static struct device *hwmon_dev; +static struct input_polled_dev *mma7450_idev; +static struct mxc_mma7450_platform_data *plat_data; +static u8 mma7450_mode; +static struct device_attribute mma7450_dev_attr = { + .attr = { + .name = "mma7450_ctl", + .mode = S_IRUSR | S_IWUSR, + }, + .show = mma7450_show, + .store = mma7450_store, +}; + +static const struct i2c_device_id mma7450_id[] = { + {"mma7450", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mma7450_id); + +static struct i2c_driver i2c_mma7450_driver = { + .driver = { + .name = "mma7450", + }, + .probe = mma7450_probe, + .remove = mma7450_remove, + .suspend = mma7450_suspend, + .resume = mma7450_resume, + .id_table = mma7450_id, +}; + +static struct mma7450_status mma_status = { + .mod = 0, + .ctl1 = 0, + .ctl2 = 0, +}; + +DECLARE_WORK(mma_work, mma_bh_handler); + +#ifdef DEBUG +enum { + MMA_REG_R = 0, + MMA_REG_W, + MMA_SET_MOD, + MMA_SET_L_THR, + MMA_SET_P_THR, + MMA_SET_INTP, + MMA_SET_INTB, + MMA_SET_G, + MMA_I2C_EABLE, + MMA_OFF_X, + MMA_OFF_Y, + MMA_OFF_Z, + MMA_SELF_TEST, + MMA_SET_LDPL, + MMA_SET_PDPL, + MMA_SET_PDV, + MMA_SET_LTV, + MMA_SET_TW, + MMA_CMD_MAX +}; + +static char *command[MMA_CMD_MAX] = { + [MMA_REG_R] = "readreg", + [MMA_REG_W] = "writereg", + [MMA_SET_MOD] = "setmod", + [MMA_SET_L_THR] = "setlt", + [MMA_SET_P_THR] = "setpt", + [MMA_SET_INTP] = "setintp", + [MMA_SET_INTB] = "setintb", + [MMA_SET_G] = "setg", + [MMA_I2C_EABLE] = "setie", + [MMA_OFF_X] = "setxo", + [MMA_OFF_Y] = "setyo", + [MMA_OFF_Z] = "setzo", + [MMA_SELF_TEST] = "selft", + [MMA_SET_LDPL] = "setldp", + [MMA_SET_PDPL] = "setpdp", + [MMA_SET_PDV] = "setpdv", + [MMA_SET_LTV] = "setltv", + [MMA_SET_TW] = "settw", +}; + +static void set_mod(u8 mode) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL); + /* shall I test the ret value? */ + ret = (ret & ~0x3) | (mode & 0x3); + mma_status.mod = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret); +} + +static void set_level_thr(u8 lth) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_LDTH, lth); +} + +static void set_pulse_thr(u8 pth) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_PDTH, pth); +} + +static void set_int_pin(u8 pin) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL1); + ret = (ret & ~0x1) | (pin & 0x1); + mma_status.ctl1 = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_CTL1, ret); +} + +static void set_int_bit(u8 bit) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL1); + ret = (ret & ~0x6) | ((bit << 1) & 0x6); + mma_status.ctl1 = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_CTL1, ret); +} + +static void set_g_level(u8 gl) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL); + ret = (ret & ~0xC) | ((gl << 2) & 0xC); + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret); +} + +static void set_i2c_enable(u8 i2c_e) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_I2CAD); + ret = (ret & ~0x80) | ((i2c_e << 7) & 0x80); + i2c_smbus_write_byte_data(mma7450_client, REG_I2CAD, ret); +} + +static void set_x_offset(u16 xo) +{ + u8 data; + + data = (xo & 0xFF); + i2c_smbus_write_byte_data(mma7450_client, REG_XOFFL, data); + data = (xo & 0xFF00) >> 8; + i2c_smbus_write_byte_data(mma7450_client, REG_XOFFH, data); +} + +static void set_y_offset(u16 yo) +{ + u8 data; + + data = (yo & 0xFF); + i2c_smbus_write_byte_data(mma7450_client, REG_YOFFL, data); + data = (yo & 0xFF00) >> 8; + i2c_smbus_write_byte_data(mma7450_client, REG_YOFFH, data); +} + +static void set_z_offset(u16 zo) +{ + u8 data; + + data = (zo & 0xFF); + i2c_smbus_write_byte_data(mma7450_client, REG_ZOFFL, data); + data = (zo & 0xFF00) >> 8; + i2c_smbus_write_byte_data(mma7450_client, REG_ZOFFH, data); +} + +static void selftest(u8 st) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL); + ret = (ret & ~0x10) | ((st << 4) & 0x10); + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, ret); +} + +static void set_level_det_p(u8 ldp) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL2); + ret = (ret & ~0x1) | ((ldp << 0) & 0x1); + mma_status.ctl2 = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_CTL2, ret); +} + +static void set_pulse_det_p(u8 pdp) +{ + int ret; + + ret = i2c_smbus_read_byte_data(mma7450_client, REG_CTL2); + ret = (ret & ~0x2) | ((pdp << 1) & 0x2); + mma_status.ctl2 = ret; + i2c_smbus_write_byte_data(mma7450_client, REG_CTL2, ret); +} + +static void set_pulse_duration(u8 pd) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_PD, pd); +} + +static void set_latency_time(u8 lt) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_LT, lt); +} + +static void set_time_window(u8 tw) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_TW, tw); +} + +static void parse_arg(const char *arg, int *reg, int *value) +{ + const char *p; + + for (p = arg;; p++) { + if (*p == ' ' || *p == '\0') + break; + } + + p++; + + *reg = simple_strtoul(arg, NULL, 16); + *value = simple_strtoul(p, NULL, 16); +} + +static void cmd_read_reg(const char *arg) +{ + int reg, value, ret; + + parse_arg(arg, ®, &value); + ret = i2c_smbus_read_byte_data(mma7450_client, reg); + dev_info(&mma7450_client->dev, "read reg0x%x = %x\n", reg, ret); +} + +static void cmd_write_reg(const char *arg) +{ + int reg, value, ret; + + parse_arg(arg, ®, &value); + ret = i2c_smbus_write_byte_data(mma7450_client, reg, value); + dev_info(&mma7450_client->dev, "write reg result %s\n", + ret ? "failed" : "success"); +} + +static int exec_command(const char *buf, size_t count) +{ + const char *p, *s; + const char *arg; + int i, value = 0; + + for (p = buf;; p++) { + if (*p == ' ' || *p == '\0' || p - buf >= count) + break; + } + arg = p + 1; + + for (i = MMA_REG_R; i < MMA_CMD_MAX; i++) { + s = command[i]; + if (s && !strncmp(buf, s, p - buf)) { + dev_info(&mma7450_client->dev, "command %s\n", s); + goto mma_exec_command; + } + } + + dev_err(&mma7450_client->dev, "command is not found\n"); + return -1; + + mma_exec_command: + if (i != MMA_REG_R && i != MMA_REG_W) + value = simple_strtoul(arg, NULL, 16); + + switch (i) { + case MMA_REG_R: + cmd_read_reg(arg); + break; + case MMA_REG_W: + cmd_write_reg(arg); + break; + case MMA_SET_MOD: + set_mod(value); + break; + case MMA_SET_L_THR: + set_level_thr(value); + break; + case MMA_SET_P_THR: + set_pulse_thr(value); + break; + case MMA_SET_INTP: + set_int_pin(value); + break; + case MMA_SET_INTB: + set_int_bit(value); + break; + case MMA_SET_G: + set_g_level(value); + break; + case MMA_I2C_EABLE: + set_i2c_enable(value); + break; + case MMA_OFF_X: + set_x_offset(value); + break; + case MMA_OFF_Y: + set_y_offset(value); + break; + case MMA_OFF_Z: + set_z_offset(value); + break; + case MMA_SELF_TEST: + selftest(value); + break; + case MMA_SET_LDPL: + set_level_det_p(value); + break; + case MMA_SET_PDPL: + set_pulse_det_p(value); + break; + case MMA_SET_PDV: + set_pulse_duration(value); + break; + case MMA_SET_LTV: + set_latency_time(value); + break; + case MMA_SET_TW: + set_time_window(value); + break; + default: + dev_err(&mma7450_client->dev, "command is not found\n"); + break; + } + + return 0; +} + +static ssize_t mma7450_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret, reg; + + for (reg = REG_XOUTL; reg < REG_REVERVED_1; reg++) { + ret = i2c_smbus_read_byte_data(mma7450_client, reg); + dev_info(&mma7450_client->dev, "reg0x%02x:\t%03d\t0x%02x\n", + reg, (s8) ret, ret); + } + + return 0; +} + +static ssize_t mma7450_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + exec_command(buf, count); + + return count; +} + +#else + +static ssize_t mma7450_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return 0; +} + +static ssize_t mma7450_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + return count; +} + +#endif + +static void report_abs(void) +{ + u8 status, mod = mma_status.mod; + s16 x, y, z; + + status = i2c_smbus_read_byte_data(mma7450_client, REG_STATUS); + if (!(status & 0x01)) { /* data ready in measurement mode? */ + return; + } + if ((mod & 0x0c) == 0) { /* 8g range */ + x = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_XOUTL); + x |= 0xFF00 & + (i2c_smbus_read_byte_data(mma7450_client, REG_XOUTH) << 8); + y = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_YOUTL); + y |= 0xFF00 & + (i2c_smbus_read_byte_data(mma7450_client, REG_YOUTH) << 8); + z = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_ZOUTL); + z |= 0xFF00 & + (i2c_smbus_read_byte_data(mma7450_client, REG_ZOUTH) << 8); + } else { /* 2g/4g range */ + x = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_XOUT8); + y = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_YOUT8); + z = 0xFF & i2c_smbus_read_byte_data(mma7450_client, REG_ZOUT8); + } + + status = i2c_smbus_read_byte_data(mma7450_client, REG_STATUS); + if (status & 0x02) { /* data is overwrite */ + return; + } + + /* convert signed 10bits to signed 16bits */ + x = (short)(x << 6) >> 6; + y = (short)(y << 6) >> 6; + z = (short)(z << 6) >> 6; + + input_report_abs(mma7450_idev->input, ABS_X, x); + input_report_abs(mma7450_idev->input, ABS_Y, y); + input_report_abs(mma7450_idev->input, ABS_Z, z); + input_sync(mma7450_idev->input); +} + +static void mma_bh_handler(struct work_struct *work) +{ +} + +static void mma7450_dev_poll(struct input_polled_dev *dev) +{ + report_abs(); +} + +static irqreturn_t mma7450_interrupt(int irq, void *dev_id) +{ + struct input_dev *input_dev = dev_id; + u8 int_bit, int_pin; + + int_bit = mma_status.ctl1 & 0x6; + int_pin = mma_status.ctl1 & 0x1; + + switch (mma_status.mod & 0x03) { + case 1: + /*only int1 report data ready int */ + if (plat_data->int1 != irq) + goto error_bad_int; + schedule_work(&mma_work); + break; + case 2: + /* for level and pulse detection mode, + * choice tasklet to handle interrupt quickly. + * Currently, leave it doing nothing*/ + if (plat_data->int1 == irq) { + if ((int_bit == 0) && (int_pin != 0)) + goto error_bad_int; + if ((int_bit == 0x2) && (int_pin != 0x1)) + goto error_bad_int; + if (int_bit == 0x4) + goto error_bad_int; + } + if (plat_data->int2 == irq) { + if ((int_bit == 0) && (int_pin != 0x1)) + goto error_bad_int; + if ((int_bit == 0x2) && (int_pin != 0)) + goto error_bad_int; + if (int_bit == 0x4) + goto error_bad_int; + } + + dev_info(&input_dev->dev, "motion detected in level mod\n"); + + break; + case 3: + if (plat_data->int1 == irq) { + if ((int_bit == 0) && (int_pin != 0x1)) + goto error_bad_int; + if ((int_bit == 0x2) && (int_pin != 0)) + goto error_bad_int; + if ((int_bit == 0x4) && (int_pin != 0x1)) + goto error_bad_int; + } + if (plat_data->int2 == irq) { + if ((int_bit == 0) && (int_pin != 0)) + goto error_bad_int; + if ((int_bit == 0x2) && (int_pin != 0x1)) + goto error_bad_int; + if ((int_bit == 0x4) && (int_pin != 0)) + goto error_bad_int; + } + + if (mma_status.ctl2 & 0x02) + dev_info(&input_dev->dev, + "freefall detected in pulse mod\n"); + else + dev_info(&input_dev->dev, + "motion detected in pulse mod\n"); + + break; + case 0: + default: + break; + } + error_bad_int: + return IRQ_RETVAL(1); +} + +static int mma7450_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + struct input_dev *idev; + + plat_data = + (struct mxc_mma7450_platform_data *)client->dev.platform_data; + if (plat_data == NULL) { + dev_err(&client->dev, "lack of platform data!\n"); + return -ENODEV; + } + + /*enable power supply */ + /*when to power on/off the power is to be considered later */ + /*shall I check the return value */ + reg_dvdd_io = regulator_get(&client->dev, plat_data->reg_dvdd_io); + if (reg_dvdd_io != ERR_PTR(-ENOENT)) + regulator_enable(reg_dvdd_io); + else + return -EINVAL; + + reg_avdd = regulator_get(&client->dev, plat_data->reg_avdd); + if (reg_avdd != ERR_PTR(-ENOENT)) + regulator_enable(reg_avdd); + else { + regulator_put(reg_dvdd_io); + return -EINVAL; + } + + /*bind the right device to the driver */ + ret = i2c_smbus_read_byte_data(client, REG_I2CAD); + if (MMA7450_I2C_ADDR != (0x7F & ret)) { /*compare the address value */ + dev_err(&client->dev, + "read chip ID 0x%x is not equal to 0x%x!\n", ret, + MMA7450_I2C_ADDR); + goto error_disable_power; + } + mma7450_client = client; + + /*interrupt register */ + /*when to register interrupt is to be considered later */ + + /*create device file in sysfs as user interface */ + ret = device_create_file(&client->dev, &mma7450_dev_attr); + if (ret) { + dev_err(&client->dev, "create device file failed!\n"); + goto error_disable_power; + } + + /*register to hwmon device */ + hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(hwmon_dev)) { + dev_err(&client->dev, "hwmon register failed!\n"); + ret = PTR_ERR(hwmon_dev); + goto error_rm_dev_file; + } + + /*input poll device register */ + mma7450_idev = input_allocate_polled_device(); + if (!mma7450_idev) { + dev_err(&client->dev, "alloc poll device failed!\n"); + ret = -ENOMEM; + goto error_rm_hwmon_dev; + } + mma7450_idev->poll = mma7450_dev_poll; + mma7450_idev->poll_interval = POLL_INTERVAL; + idev = mma7450_idev->input; + idev->name = DEVICE_NAME; + idev->id.bustype = BUS_I2C; + idev->dev.parent = &client->dev; + idev->evbit[0] = BIT_MASK(EV_ABS); + + input_set_abs_params(idev, ABS_X, -512, 512, INPUT_FUZZ, INPUT_FLAT); + input_set_abs_params(idev, ABS_Y, -512, 512, INPUT_FUZZ, INPUT_FLAT); + input_set_abs_params(idev, ABS_Z, -512, 512, INPUT_FUZZ, INPUT_FLAT); + ret = input_register_polled_device(mma7450_idev); + if (ret) { + dev_err(&client->dev, "register poll device failed!\n"); + goto error_free_poll_dev; + } + + /* configure gpio as input for interrupt monitor */ + plat_data->gpio_pin_get(); + + set_irq_type(plat_data->int1, IRQF_TRIGGER_RISING); + /* register interrupt handle */ + ret = request_irq(plat_data->int1, mma7450_interrupt, + IRQF_TRIGGER_RISING, DEVICE_NAME, idev); + + if (ret) { + dev_err(&client->dev, "request_irq(%d) returned error %d\n", + plat_data->int1, ret); + goto error_rm_poll_dev; + } + + set_irq_type(plat_data->int2, IRQF_TRIGGER_RISING); + ret = request_irq(plat_data->int2, mma7450_interrupt, + IRQF_TRIGGER_RISING, DEVICE_NAME, idev); + if (ret) { + dev_err(&client->dev, "request_irq(%d) returned error %d\n", + plat_data->int2, ret); + goto error_free_irq1; + } + + dev_info(&client->dev, "mma7450 device is probed successfully.\n"); + + set_mod(1); + return 0; /*what value shall be return */ + + /*error handle */ + error_free_irq1: + free_irq(plat_data->int1, 0); + error_rm_poll_dev: + input_unregister_polled_device(mma7450_idev); + error_free_poll_dev: + input_free_polled_device(mma7450_idev); + error_rm_hwmon_dev: + hwmon_device_unregister(hwmon_dev); + error_rm_dev_file: + device_remove_file(&client->dev, &mma7450_dev_attr); + error_disable_power: + regulator_disable(reg_dvdd_io); /*shall I check the return value */ + regulator_disable(reg_avdd); + regulator_put(reg_dvdd_io); + regulator_put(reg_avdd); + + return ret; +} + +static int mma7450_remove(struct i2c_client *client) +{ + free_irq(plat_data->int2, mma7450_idev->input); + free_irq(plat_data->int1, mma7450_idev->input); + plat_data->gpio_pin_put(); + input_unregister_polled_device(mma7450_idev); + input_free_polled_device(mma7450_idev); + hwmon_device_unregister(hwmon_dev); + device_remove_file(&client->dev, &mma7450_dev_attr); + regulator_disable(reg_dvdd_io); /*shall I check the return value */ + regulator_disable(reg_avdd); + regulator_put(reg_dvdd_io); + regulator_put(reg_avdd); + return 0; +} + +static int mma7450_suspend(struct i2c_client *client, pm_message_t state) +{ + mma7450_mode = i2c_smbus_read_byte_data(mma7450_client, REG_MCTL); + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, + mma7450_mode & ~0x3); + return 0; +} + +static int mma7450_resume(struct i2c_client *client) +{ + i2c_smbus_write_byte_data(mma7450_client, REG_MCTL, mma7450_mode); + return 0; +} + +static int __init init_mma7450(void) +{ + /*register driver */ + printk(KERN_INFO "add mma i2c driver\n"); + return i2c_add_driver(&i2c_mma7450_driver); +} + +static void __exit exit_mma7450(void) +{ + printk(KERN_INFO "del mma i2c driver.\n"); + return i2c_del_driver(&i2c_mma7450_driver); +} + +module_init(init_mma7450); +module_exit(exit_mma7450); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MMA7450 sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hwmon/mxc_mma8450.c b/drivers/hwmon/mxc_mma8450.c new file mode 100644 index 000000000000..3d4c1ef1f4d9 --- /dev/null +++ b/drivers/hwmon/mxc_mma8450.c @@ -0,0 +1,390 @@ +/* + * mma8450.c - Linux kernel modules for 3-Axis Orientation/Motion + * Detection Sensor + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Defines + */ +#define assert(expr)\ + if (!(expr)) {\ + printk(KERN_ERR "Assertion failed! %s,%d,%s,%s\n",\ + __FILE__, __LINE__, __func__, #expr);\ + } + +#define MMA8450_DRV_NAME "mma8450" +#define MMA8450_I2C_ADDR 0x1C +#define MMA8450_ID 0xC6 +#define MMA8450_STATUS 0x00 +#define MODE_CHANGE_DELAY_MS 100 +#define POLL_INTERVAL 100 +#define INPUT_FUZZ 32 +#define INPUT_FLAT 32 + +/* register enum for mma8450 registers */ +enum { + MMA8450_STATUS1 = 0x00, + MMA8450_OUT_X8, + MMA8450_OUT_Y8, + MMA8450_OUT_Z8, + + MMA8450_STATUS2, + MMA8450_OUT_X_LSB, + MMA8450_OUT_X_MSB, + MMA8450_OUT_Y_LSB, + MMA8450_OUT_Y_MSB, + MMA8450_OUT_Z_LSB, + MMA8450_OUT_Z_MSB, + + MMA8450_STATUS3, + MMA8450_OUT_X_DELTA, + MMA8450_OUT_Y_DELTA, + MMA8450_OUT_Z_DELTA, + + MMA8450_WHO_AM_I, + + MMA8450_F_STATUS, + MMA8450_F_8DATA, + MMA8450_F_12DATA, + MMA8450_F_SETUP, + + MMA8450_SYSMOD, + MMA8450_INT_SOURCE, + MMA8450_XYZ_DATA_CFG, + MMA8450_HP_FILTER_CUTOFF, + + MMA8450_PL_STATUS, + MMA8450_PL_PRE_STATUS, + MMA8450_PL_CFG, + MMA8450_PL_COUNT, + MMA8450_PL_BF_ZCOMP, + MMA8450_PL_P_L_THS_REG1, + MMA8450_PL_P_L_THS_REG2, + MMA8450_PL_P_L_THS_REG3, + MMA8450_PL_L_P_THS_REG1, + MMA8450_PL_L_P_THS_REG2, + MMA8450_PL_L_P_THS_REG3, + + MMA8450_FF_MT_CFG_1, + MMA8450_FF_MT_SRC_1, + MMA8450_FF_MT_THS_1, + MMA8450_FF_MT_COUNT_1, + MMA8450_FF_MT_CFG_2, + MMA8450_FF_MT_SRC_2, + MMA8450_FF_MT_THS_2, + MMA8450_FF_MT_COUNT_2, + + MMA8450_TRANSIENT_CFG, + MMA8450_TRANSIENT_SRC, + MMA8450_TRANSIENT_THS, + MMA8450_TRANSIENT_COUNT, + + MMA8450_PULSE_CFG, + MMA8450_PULSE_SRC, + MMA8450_PULSE_THSX, + MMA8450_PULSE_THSY, + MMA8450_PULSE_THSZ, + MMA8450_PULSE_TMLT, + MMA8450_PULSE_LTCY, + MMA8450_PULSE_WIND, + + MMA8450_ASLP_COUNT, + MMA8450_CTRL_REG1, + MMA8450_CTRL_REG2, + MMA8450_CTRL_REG3, + MMA8450_CTRL_REG4, + MMA8450_CTRL_REG5, + + MMA8450_OFF_X, + MMA8450_OFF_Y, + MMA8450_OFF_Z, + + MMA8450_REG_END, +}; + +enum { + MODE_STANDBY, + MODE_2G, + MODE_4G, + MODE_8G, +}; + +/* mma8450 status */ +struct mma8450_status { + u8 mode; + u8 ctl_reg2; + u8 ctl_reg1; +}; + +static struct mma8450_status mma_status = { + .mode = 0, + .ctl_reg2 = 0, + .ctl_reg1 = 0 +}; + +static struct device *hwmon_dev; +static struct i2c_client *mma8450_i2c_client; +static struct input_polled_dev *mma8450_idev; + +/* + * Initialization function + */ +static int mma8450_init_client(struct i2c_client *client) +{ + int result; + + mma_status.mode = MODE_2G; + + result = i2c_smbus_write_byte_data(client, MMA8450_XYZ_DATA_CFG, 0x07); + assert(result == 0); + + result = + i2c_smbus_write_byte_data(client, MMA8450_CTRL_REG1, + mma_status.mode); + assert(result == 0); + + mdelay(MODE_CHANGE_DELAY_MS); + + return result; +} + +/* + * read sensor data from mma8450 + */ +static int mma8450_read_data(short *x, short *y, short *z) +{ + u8 tmp_data[7]; + + if (i2c_smbus_read_i2c_block_data + (mma8450_i2c_client, MMA8450_OUT_X_LSB, 7, tmp_data) < 7) { + dev_err(&mma8450_i2c_client->dev, "i2c block read failed\n"); + return -3; + } + + *x = ((tmp_data[1] << 8) & 0xff00) | ((tmp_data[0] << 4) & 0x00f0); + *y = ((tmp_data[3] << 8) & 0xff00) | ((tmp_data[2] << 4) & 0x00f0); + *z = ((tmp_data[5] << 8) & 0xff00) | ((tmp_data[4] << 4) & 0x00f0); + + *x = (short)(*x) >> 4; + *y = (short)(*y) >> 4; + *z = (short)(*z) >> 4; + + if (mma_status.mode == MODE_4G) { + (*x) = (*x) << 1; + (*y) = (*y) << 1; + (*z) = (*z) << 1; + } else if (mma_status.mode == MODE_8G) { + (*x) = (*x) << 2; + (*y) = (*y) << 2; + (*z) = (*z) << 2; + } + + return 0; +} + +static void report_abs(void) +{ + short x, y, z; + int result; + + do { + result = + i2c_smbus_read_byte_data(mma8450_i2c_client, + MMA8450_STATUS3); + } while (!(result & 0x08)); /* wait for new data */ + + if (mma8450_read_data(&x, &y, &z) != 0) + return; + + input_report_abs(mma8450_idev->input, ABS_X, x); + input_report_abs(mma8450_idev->input, ABS_Y, y); + input_report_abs(mma8450_idev->input, ABS_Z, z); + input_sync(mma8450_idev->input); +} + +static void mma8450_dev_poll(struct input_polled_dev *dev) +{ + report_abs(); +} + +/* + * I2C init/probing/exit functions + */ +static int __devinit mma8450_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int result; + struct i2c_adapter *adapter; + struct input_dev *idev; + + mma8450_i2c_client = client; + adapter = to_i2c_adapter(client->dev.parent); + + result = i2c_check_functionality(adapter, + I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA); + assert(result); + + printk(KERN_INFO "check mma8450 chip ID\n"); + result = i2c_smbus_read_byte_data(client, MMA8450_WHO_AM_I); + + if (MMA8450_ID != (result)) { + dev_err(&client->dev, + "read chip ID 0x%x is not equal to 0x%x!\n", result, + MMA8450_ID); + printk(KERN_INFO "read chip ID failed\n"); + result = -EINVAL; + goto err_detach_client; + } + + /* Initialize the MMA8450 chip */ + result = mma8450_init_client(client); + assert(result == 0); + + hwmon_dev = hwmon_device_register(&client->dev); + assert(!(IS_ERR(hwmon_dev))); + + dev_info(&client->dev, "build time %s %s\n", __DATE__, __TIME__); + + /*input poll device register */ + mma8450_idev = input_allocate_polled_device(); + if (!mma8450_idev) { + dev_err(&client->dev, "alloc poll device failed!\n"); + result = -ENOMEM; + return result; + } + mma8450_idev->poll = mma8450_dev_poll; + mma8450_idev->poll_interval = POLL_INTERVAL; + idev = mma8450_idev->input; + idev->name = MMA8450_DRV_NAME; + idev->id.bustype = BUS_I2C; + idev->dev.parent = &client->dev; + idev->evbit[0] = BIT_MASK(EV_ABS); + + input_set_abs_params(idev, ABS_X, -8192, 8191, INPUT_FUZZ, INPUT_FLAT); + input_set_abs_params(idev, ABS_Y, -8192, 8191, INPUT_FUZZ, INPUT_FLAT); + input_set_abs_params(idev, ABS_Z, -8192, 8191, INPUT_FUZZ, INPUT_FLAT); + result = input_register_polled_device(mma8450_idev); + if (result) { + dev_err(&client->dev, "register poll device failed!\n"); + return result; + } + + return result; + +err_detach_client: + return result; +} + +static int __devexit mma8450_remove(struct i2c_client *client) +{ + int result; + mma_status.ctl_reg1 = + i2c_smbus_read_byte_data(client, MMA8450_CTRL_REG1); + result = + i2c_smbus_write_byte_data(client, MMA8450_CTRL_REG1, + mma_status.ctl_reg1 & 0xFC); + assert(result == 0); + + hwmon_device_unregister(hwmon_dev); + + return result; +} + +static int mma8450_suspend(struct i2c_client *client, pm_message_t mesg) +{ + int result; + mma_status.ctl_reg1 = + i2c_smbus_read_byte_data(client, MMA8450_CTRL_REG1); + result = + i2c_smbus_write_byte_data(client, MMA8450_CTRL_REG1, + mma_status.ctl_reg1 & 0xFC); + assert(result == 0); + return result; +} + +static int mma8450_resume(struct i2c_client *client) +{ + int result; + result = + i2c_smbus_write_byte_data(client, MMA8450_CTRL_REG1, + mma_status.mode); + assert(result == 0); + return result; +} + +static const struct i2c_device_id mma8450_id[] = { + {MMA8450_DRV_NAME, 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mma8450_id); + +static struct i2c_driver mma8450_driver = { + .driver = { + .name = MMA8450_DRV_NAME, + .owner = THIS_MODULE, + }, + .suspend = mma8450_suspend, + .resume = mma8450_resume, + .probe = mma8450_probe, + .remove = __devexit_p(mma8450_remove), + .id_table = mma8450_id, +}; + +static int __init mma8450_init(void) +{ + /* register driver */ + int res; + + res = i2c_add_driver(&mma8450_driver); + if (res < 0) { + printk(KERN_INFO "add mma8450 i2c driver failed\n"); + return -ENODEV; + } + printk(KERN_INFO "add mma8450 i2c driver\n"); + + return res; +} + +static void __exit mma8450_exit(void) +{ + printk(KERN_INFO "remove mma8450 i2c driver.\n"); + i2c_del_driver(&mma8450_driver); +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MMA8450 3-Axis Orientation/Motion Detection Sensor driver"); +MODULE_LICENSE("GPL"); + +module_init(mma8450_init); +module_exit(mma8450_exit); diff --git a/drivers/hwmon/mxc_mma8451.c b/drivers/hwmon/mxc_mma8451.c new file mode 100644 index 000000000000..901be5cedb37 --- /dev/null +++ b/drivers/hwmon/mxc_mma8451.c @@ -0,0 +1,371 @@ +/* + * mma8451.c - Linux kernel modules for 3-Axis Orientation/Motion + * Detection Sensor + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Defines + */ +#define assert(expr)\ + if (!(expr)) {\ + printk(KERN_ERR "Assertion failed! %s,%d,%s,%s\n",\ + __FILE__, __LINE__, __func__, #expr);\ + } + +#define MMA8451_DRV_NAME "mma8451" +#define MMA8451_I2C_ADDR 0x1C +#define MMA8451_ID 0x1A + +#define POLL_INTERVAL 100 +#define INPUT_FUZZ 32 +#define INPUT_FLAT 32 +#define MODE_CHANGE_DELAY_MS 100 + +/* register enum for mma8451 registers */ +enum { + MMA8451_STATUS = 0x00, + MMA8451_OUT_X_MSB, + MMA8451_OUT_X_LSB, + MMA8451_OUT_Y_MSB, + MMA8451_OUT_Y_LSB, + MMA8451_OUT_Z_MSB, + MMA8451_OUT_Z_LSB, + + MMA8451_F_SETUP = 0x09, + MMA8451_TRIG_CFG, + MMA8451_SYSMOD, + MMA8451_INT_SOURCE, + MMA8451_WHO_AM_I, + MMA8451_XYZ_DATA_CFG, + MMA8451_HP_FILTER_CUTOFF, + + MMA8451_PL_STATUS, + MMA8451_PL_CFG, + MMA8451_PL_COUNT, + MMA8451_PL_BF_ZCOMP, + MMA8451_P_L_THS_REG, + + MMA8451_FF_MT_CFG, + MMA8451_FF_MT_SRC, + MMA8451_FF_MT_THS, + MMA8451_FF_MT_COUNT, + + MMA8451_TRANSIENT_CFG = 0x1D, + MMA8451_TRANSIENT_SRC, + MMA8451_TRANSIENT_THS, + MMA8451_TRANSIENT_COUNT, + + MMA8451_PULSE_CFG, + MMA8451_PULSE_SRC, + MMA8451_PULSE_THSX, + MMA8451_PULSE_THSY, + MMA8451_PULSE_THSZ, + MMA8451_PULSE_TMLT, + MMA8451_PULSE_LTCY, + MMA8451_PULSE_WIND, + + MMA8451_ASLP_COUNT, + MMA8451_CTRL_REG1, + MMA8451_CTRL_REG2, + MMA8451_CTRL_REG3, + MMA8451_CTRL_REG4, + MMA8451_CTRL_REG5, + + MMA8451_OFF_X, + MMA8451_OFF_Y, + MMA8451_OFF_Z, + + MMA8451_REG_END, +}; + +enum { + MODE_2G = 0, + MODE_4G, + MODE_8G, +}; + +/* mma8451 status */ +struct mma8451_status { + u8 mode; + u8 ctl_reg1; +}; + +static struct mma8451_status mma_status = { + .mode = 0, + .ctl_reg1 = 0 +}; + +static struct input_polled_dev *mma8451_idev; +static struct device *hwmon_dev; +static int test_test_mode = 1; +static struct i2c_client *mma8451_i2c_client; + +/*************************************************************** + * + * Initialization function + * + **************************************************************/ +static int mma8451_init_client(struct i2c_client *client) +{ + int result; + + mma_status.ctl_reg1 = 0x00; + result = + i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, + mma_status.ctl_reg1); + assert(result == 0); + + mma_status.mode = MODE_2G; + result = + i2c_smbus_write_byte_data(client, MMA8451_XYZ_DATA_CFG, + mma_status.mode); + assert(result == 0); + + mma_status.ctl_reg1 |= 0x01; + result = + i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, + mma_status.ctl_reg1); + assert(result == 0); + + mdelay(MODE_CHANGE_DELAY_MS); + + return result; +} + +/*************************************************************** +* +* read sensor data from mma8451 +* +***************************************************************/ +static int mma8451_read_data(short *x, short *y, short *z) +{ + u8 tmp_data[7]; + + if (i2c_smbus_read_i2c_block_data + (mma8451_i2c_client, MMA8451_OUT_X_MSB, 7, tmp_data) < 7) { + dev_err(&mma8451_i2c_client->dev, "i2c block read failed\n"); + return -3; + } + + *x = ((tmp_data[0] << 8) & 0xff00) | tmp_data[1]; + *y = ((tmp_data[2] << 8) & 0xff00) | tmp_data[3]; + *z = ((tmp_data[4] << 8) & 0xff00) | tmp_data[5]; + + *x = (short)(*x) >> 2; + *y = (short)(*y) >> 2; + *z = (short)(*z) >> 2; + + if (mma_status.mode == MODE_4G) { + (*x) = (*x) << 1; + (*y) = (*y) << 1; + (*z) = (*z) << 1; + } else if (mma_status.mode == MODE_8G) { + (*x) = (*x) << 2; + (*y) = (*y) << 2; + (*z) = (*z) << 2; + } + + return 0; +} + +static void report_abs(void) +{ + short x, y, z; + int result; + + do { + result = + i2c_smbus_read_byte_data(mma8451_i2c_client, + MMA8451_STATUS); + } while (!(result & 0x08)); /* wait for new data */ + + if (mma8451_read_data(&x, &y, &z) != 0) + return; + + input_report_abs(mma8451_idev->input, ABS_X, x); + input_report_abs(mma8451_idev->input, ABS_Y, y); + input_report_abs(mma8451_idev->input, ABS_Z, z); + input_sync(mma8451_idev->input); +} + +static void mma8451_dev_poll(struct input_polled_dev *dev) +{ + report_abs(); +} + +static int __devinit mma8451_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int result; + mma8451_i2c_client = client; + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + + struct input_dev *idev; + + result = i2c_check_functionality(adapter, + I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA); + assert(result); + + printk(KERN_INFO "check mma8451 chip ID\n"); + result = i2c_smbus_read_byte_data(client, MMA8451_WHO_AM_I); + + if (MMA8451_ID != result) { + dev_err(&client->dev, + "read chip ID 0x%x is not equal to 0x%x!\n", result, + MMA8451_ID); + printk(KERN_INFO "read chip ID failed\n"); + result = -EINVAL; + goto err_detach_client; + } + + /* Initialize the MMA8451 chip */ + result = mma8451_init_client(client); + assert(result == 0); + + hwmon_dev = hwmon_device_register(&client->dev); + assert(!(IS_ERR(hwmon_dev))); + + dev_info(&client->dev, "build time %s %s\n", __DATE__, __TIME__); + + /*input poll device register */ + mma8451_idev = input_allocate_polled_device(); + if (!mma8451_idev) { + dev_err(&client->dev, "alloc poll device failed!\n"); + result = -ENOMEM; + return result; + } + mma8451_idev->poll = mma8451_dev_poll; + mma8451_idev->poll_interval = POLL_INTERVAL; + idev = mma8451_idev->input; + idev->name = MMA8451_DRV_NAME; + idev->id.bustype = BUS_I2C; + idev->dev.parent = &client->dev; + idev->evbit[0] = BIT_MASK(EV_ABS); + + input_set_abs_params(idev, ABS_X, -8192, 8191, INPUT_FUZZ, INPUT_FLAT); + input_set_abs_params(idev, ABS_Y, -8192, 8191, INPUT_FUZZ, INPUT_FLAT); + input_set_abs_params(idev, ABS_Z, -8192, 8191, INPUT_FUZZ, INPUT_FLAT); + result = input_register_polled_device(mma8451_idev); + if (result) { + dev_err(&client->dev, "register poll device failed!\n"); + return result; + } + return result; + +err_detach_client: + return result; +} + +static int __devexit mma8451_remove(struct i2c_client *client) +{ + int result; + mma_status.ctl_reg1 = + i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1); + result = + i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, + mma_status.ctl_reg1 & 0xFE); + assert(result == 0); + + hwmon_device_unregister(hwmon_dev); + + return result; +} + +static int mma8451_suspend(struct i2c_client *client, pm_message_t mesg) +{ + int result; + mma_status.ctl_reg1 = + i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1); + result = + i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, + mma_status.ctl_reg1 & 0xFE); + assert(result == 0); + return result; +} + +static int mma8451_resume(struct i2c_client *client) +{ + int result; + result = + i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, + mma_status.ctl_reg1); + assert(result == 0); + return result; +} + +static const struct i2c_device_id mma8451_id[] = { + {MMA8451_DRV_NAME, 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mma8451_id); + +static struct i2c_driver mma8451_driver = { + .driver = { + .name = MMA8451_DRV_NAME, + .owner = THIS_MODULE, + }, + .suspend = mma8451_suspend, + .resume = mma8451_resume, + .probe = mma8451_probe, + .remove = __devexit_p(mma8451_remove), + .id_table = mma8451_id, +}; + +static int __init mma8451_init(void) +{ + /* register driver */ + int res; + + res = i2c_add_driver(&mma8451_driver); + if (res < 0) { + printk(KERN_INFO "add mma8451 i2c driver failed\n"); + return -ENODEV; + } + printk(KERN_INFO "add mma8451 i2c driver\n"); + + return res; +} + +static void __exit mma8451_exit(void) +{ + printk(KERN_INFO "remove mma8451 i2c driver.\n"); + i2c_del_driver(&mma8451_driver); +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MMA8451 3-Axis Orientation/Motion Detection Sensor driver"); +MODULE_LICENSE("GPL"); + +module_init(mma8451_init); +module_exit(mma8451_exit); diff --git a/drivers/i2c-slave/Kconfig b/drivers/i2c-slave/Kconfig new file mode 100644 index 000000000000..89717e15e784 --- /dev/null +++ b/drivers/i2c-slave/Kconfig @@ -0,0 +1,39 @@ +# +# I2C slave subsystem configuration +# + +menuconfig I2C_SLAVE + bool "I2C Slave support" + depends on HAS_IOMEM + ---help--- + I2C (pronounce: I-square-C) is a slow serial bus protocol used in + many micro controller applications and developed by Philips. + + If you want I2C Slave support, you should say Y here. + + This I2C Slave support can also be built as a module. If so, the module + will be called i2c-slave. + +if I2C_SLAVE + +config I2C_SLAVE_CORE + tristate "I2C SLAVE CORE" + default y + ---help--- + i2c slave core. + +config MXC_I2C_SLAVE + tristate "MXC I2C SLAVE" + depends on I2C_SLAVE_CORE + default y + ---help--- + mxc i2c slave support. + +config I2C_SLAVE_CLIENT + tristate "I2C SLAVE CLIENT" + default y + ---help--- + i2c slave client that used when the master is on the same board. + this is for i2c master which is on the same board with the slave. + +endif # I2C_SLAVE diff --git a/drivers/i2c-slave/Makefile b/drivers/i2c-slave/Makefile new file mode 100644 index 000000000000..a7b08c919af9 --- /dev/null +++ b/drivers/i2c-slave/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the i2c slave. +# + +i2c_slave-objs := i2c_slave_ring_buffer.o i2c_slave_device.o i2c_slave_core.o +obj-$(CONFIG_I2C_SLAVE_CORE) += i2c_slave.o +obj-$(CONFIG_MXC_I2C_SLAVE) += mxc_i2c_slave.o +obj-$(CONFIG_I2C_SLAVE_CLIENT) += i2c_slave_client.o diff --git a/drivers/i2c-slave/i2c_slave_client.c b/drivers/i2c-slave/i2c_slave_client.c new file mode 100644 index 000000000000..05bed361f5ca --- /dev/null +++ b/drivers/i2c-slave/i2c_slave_client.c @@ -0,0 +1,81 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include + +struct i2c_client *i2c_slave_client; +static int i2c_slave_client_probe(struct i2c_client *adapter); +static int i2c_slave_client_remove(struct i2c_client *client); +static struct i2c_driver i2c_slave_client_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "i2c-slave-client", + }, + .probe = i2c_slave_client_probe, + .remove = i2c_slave_client_remove, +}; + +/*! + * ov2640 I2C attach function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int i2c_slave_client_probe(struct i2c_client *client) +{ + i2c_slave_client = client; + return 0; +} + +/*! + * ov2640 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int i2c_slave_client_remove(struct i2c_client *client) +{ + return 0; +} + +/*! + * ov2640 init function + * + * @return Error code indicating success or failure + */ +static __init int i2c_slave_client_init(void) +{ + return i2c_add_driver(&i2c_slave_client_driver); +} + +/*! + * OV2640 cleanup function + * + * @return Error code indicating success or failure + */ +static void __exit i2c_slave_client_clean(void) +{ + i2c_del_driver(&i2c_slave_client_driver); +} + +module_init(i2c_slave_client_init); +module_exit(i2c_slave_client_clean); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("I2c Slave Client Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/i2c-slave/i2c_slave_core.c b/drivers/i2c-slave/i2c_slave_core.c new file mode 100644 index 000000000000..4d3a21a5f45f --- /dev/null +++ b/drivers/i2c-slave/i2c_slave_core.c @@ -0,0 +1,359 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include "i2c_slave_device.h" + +int i2c_slave_major; + +static ssize_t i2c_slave_read(struct file *fd, char __user *buf, size_t len, + loff_t *ptr) +{ + i2c_slave_device_t *dev; + void *kbuf; + int ret; + + if (len == 0) + return 0; + + kbuf = kmalloc(len, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + goto error0; + } + + dev = (i2c_slave_device_t *) fd->private_data; + if (!dev) { + ret = -ENODEV; + goto error1; + } + + ret = i2c_slave_device_read(dev, len, kbuf); + if (ret <= 0 || copy_to_user(buf, kbuf, len)) { + ret = -EFAULT; + } + + error1: + kfree(kbuf); + error0: + return ret; +} + +static ssize_t i2c_slave_write(struct file *fd, const char __user *buf, + size_t len, loff_t *ptr) +{ + i2c_slave_device_t *dev; + void *kbuf; + int ret; + + if (len == 0) + return 0; + + kbuf = kmalloc(len, GFP_KERNEL); + if (!kbuf) { + ret = -ENOMEM; + goto error0; + } + if (copy_from_user(kbuf, buf, len)) { + ret = -EFAULT; + goto error1; + } + + dev = (i2c_slave_device_t *) fd->private_data; + if (!dev) { + ret = -ENODEV; + goto error1; + } + + ret = i2c_slave_device_write(dev, len, (u8 *) kbuf); + + error1: + kfree(kbuf); + error0: + return ret; +} + +static int i2c_slave_ioctl(struct inode *inode, struct file *fd, + unsigned code, unsigned long value) +{ + /*todo */ + return 0; +} + +static int i2c_slave_open(struct inode *inode, struct file *fd) +{ + int ret; + unsigned int id; + i2c_slave_device_t *dev; + id = iminor(inode); + + if (id >= I2C_SLAVE_DEVICE_MAX) { + ret = -ENODEV; + goto error; + } + + dev = i2c_slave_device_find(id); + if (!dev) { + ret = -ENODEV; + goto error; + } + + i2c_slave_rb_clear(dev->receive_buffer); + i2c_slave_rb_clear(dev->send_buffer); + + if (i2c_slave_device_start(dev)) { + ret = -EBUSY; + goto error; + } + + fd->private_data = (void *)dev; + ret = 0; + + error: + return ret; +} + +static int i2c_slave_release(struct inode *inode, struct file *fd) +{ + int ret; + unsigned int id; + i2c_slave_device_t *dev; + id = iminor(inode); + + if (id >= I2C_SLAVE_DEVICE_MAX) { + ret = -ENODEV; + goto error; + } + + dev = i2c_slave_device_find(id); + if (!dev) { + ret = -ENODEV; + goto error; + } + + if (i2c_slave_device_stop(dev)) { + ret = -EBUSY; + goto error; + } + + ret = 0; + + error: + return ret; +} + +static const struct file_operations i2c_slave_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .read = i2c_slave_read, + .write = i2c_slave_write, + .ioctl = i2c_slave_ioctl, + .open = i2c_slave_open, + .release = i2c_slave_release, +}; + +static int i2c_slave_bus_match(struct device *dev, struct device_driver *drv) +{ + return 0; +} + +/* +static int i2c_slave_bus_probe(struct device *dev) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + return driver->probe(dev); + } else { + dev_err(dev, "%s: no driver\n", __func__); + return -ENODEV; + } +} +*/ + +static int i2c_slave_bus_remove(struct device *dev) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + if (!driver->remove) { + return 0; + } else { + return driver->remove(dev); + } + } else { + + dev_err(dev, "%s: no driver\n", __func__); + return -ENODEV; + } +} + +static void i2c_slave_bus_shutdown(struct device *dev) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + + driver->shutdown(dev); + } else { + + dev_err(dev, "%s: no driver\n", __func__); + return; + } +} +static int i2c_slave_bus_suspend(struct device *dev, pm_message_t state) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + + if (!driver->suspend) { + return 0; + } else { + return driver->suspend(dev, state); + } + } else { + + dev_err(dev, "%s: no driver\n", __func__); + return -ENODEV; + } +} + +static int i2c_slave_bus_resume(struct device *dev) +{ + struct device_driver *driver = dev->driver; + + if (driver) { + + if (!driver->resume) { + return 0; + } else { + return driver->resume(dev); + } + } else { + + dev_err(dev, "%s: no driver\n", __func__); + return -ENODEV; + } +} + +struct bus_type i2c_slave_bus_type = { + .name = "i2c-slave", + .match = i2c_slave_bus_match, + .remove = i2c_slave_bus_remove, + .shutdown = i2c_slave_bus_shutdown, + .suspend = i2c_slave_bus_suspend, + .resume = i2c_slave_bus_resume, +}; + +EXPORT_SYMBOL_GPL(i2c_slave_bus_type); + +static int i2c_slave_driver_probe(struct device *dev) +{ + return 0; +} + +static int i2c_slave_driver_remove(struct device *dev) +{ + return 0; +} + +static int i2c_slave_driver_shutdown(struct device *dev) +{ + return 0; +} + +static int i2c_slave_driver_suspend(struct device *dev, pm_message_t state) +{ + return 0; +} + +static int i2c_slave_driver_resume(struct device *dev) +{ + return 0; +} + +extern struct class *i2c_slave_class; + +static struct device_driver i2c_slave_driver = { + .name = "i2c-slave", + .owner = THIS_MODULE, + .bus = &i2c_slave_bus_type, + .probe = i2c_slave_driver_probe, + .remove = i2c_slave_driver_remove, + .shutdown = i2c_slave_driver_shutdown, + .suspend = i2c_slave_driver_suspend, + .resume = i2c_slave_driver_resume, +}; + +static int __init i2c_slave_dev_init(void) +{ + int ret; + + printk(KERN_INFO "i2c slave /dev entries driver\n"); + + ret = bus_register(&i2c_slave_bus_type); + if (ret) { + printk(KERN_ERR "%s: bus_register error\n", __func__); + goto out; + } + + i2c_slave_class = class_create(THIS_MODULE, "i2c-slave"); + if (IS_ERR(i2c_slave_class)) { + pr_err("%s: class_create error\n", __func__); + goto out_unreg_bus; + } + + i2c_slave_major = register_chrdev(0, "i2c-slave", &i2c_slave_fops); + if (i2c_slave_major <= 0) { + pr_err("%s: register_chrdev error\n", __func__); + goto out_unreg_class; + } + + ret = driver_register(&i2c_slave_driver); + if (ret) { + pr_err("%s: driver_register error\n", __func__); + goto out_unreg_chrdev; + } + + return 0; + + out_unreg_chrdev: + unregister_chrdev(i2c_slave_major, "i2c-slave"); + out_unreg_class: + class_destroy(i2c_slave_class); + out_unreg_bus: + bus_unregister(&i2c_slave_bus_type); + out: + pr_err("%s: init error\n", __func__); + return ret; +} + +static void __exit i2c_dev_exit(void) +{ + driver_unregister(&i2c_slave_driver); + class_destroy(i2c_slave_class); + unregister_chrdev(i2c_slave_major, "i2c-slave"); + bus_unregister(&i2c_slave_bus_type); +} + +module_init(i2c_slave_dev_init); +module_exit(i2c_dev_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("I2C Slave Driver Core"); +MODULE_LICENSE("GPL"); diff --git a/drivers/i2c-slave/i2c_slave_device.c b/drivers/i2c-slave/i2c_slave_device.c new file mode 100644 index 000000000000..1968a00aa693 --- /dev/null +++ b/drivers/i2c-slave/i2c_slave_device.c @@ -0,0 +1,271 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include "i2c_slave_device.h" +static i2c_slave_device_t *i2c_slave_devices[I2C_SLAVE_DEVICE_MAX]; +struct class *i2c_slave_class; +static int i2c_slave_device_get_id(void) +{ + int i; + for (i = 0; i < I2C_SLAVE_DEVICE_MAX; i++) { + if (!i2c_slave_devices[i]) + return i; + } + return -1; +} + +i2c_slave_device_t *i2c_slave_device_find(int id) +{ + if (id >= 0 && id < I2C_SLAVE_DEVICE_MAX) + return i2c_slave_devices[id]; + + else + return NULL; +} +void i2c_slave_device_set_name(i2c_slave_device_t *device, char *name) +{ + device->name = name; +} + +void i2c_slave_device_set_address(i2c_slave_device_t *device, u8 address) +{ + device->address = address; +} + +u8 i2c_slave_device_get_addr(i2c_slave_device_t *device) +{ + return device->address; +} + +int i2c_slave_device_set_freq(i2c_slave_device_t *device, u32 freq) +{ + /*TODO: freq check */ + device->scl_freq = freq; + return 0; +} + +u32 i2c_slave_device_get_freq(i2c_slave_device_t *device) +{ + return device->scl_freq; +} + +/*used by the specific i2c device to register itself to the core.*/ +i2c_slave_device_t *i2c_slave_device_alloc(void) +{ + int id; + i2c_slave_device_t *device; + id = i2c_slave_device_get_id(); + if (id < 0) { + goto error; + } + device = + (i2c_slave_device_t *) kzalloc(sizeof(i2c_slave_device_t), + GFP_KERNEL); + if (!device) { + printk(KERN_ERR "%s: alloc device error\n", __func__); + goto error_device; + } + device->receive_buffer = i2c_slave_rb_alloc(PAGE_SIZE); + if (!device->receive_buffer) { + printk(KERN_ERR "%s: alloc receive buffer error\n", __func__); + goto error_receive_buffer; + } + device->send_buffer = i2c_slave_rb_alloc(PAGE_SIZE); + if (!device->send_buffer) { + printk(KERN_ERR "%s: alloc send buffer error\n", __func__); + goto error_send_buffer; + } + device->id = id; + return device; + + error_send_buffer: + kfree(device->receive_buffer); + error_receive_buffer: + kfree((void *)device); + error_device: + pr_debug(KERN_ERR "%s: no memory\n", __func__); + error: + return 0; +} + +void i2c_slave_device_free(i2c_slave_device_t *dev) +{ + i2c_slave_rb_release(dev->receive_buffer); + i2c_slave_rb_release(dev->send_buffer); + kfree(dev); +} + +int i2c_slave_device_register(i2c_slave_device_t *device) +{ + device->dev = device_create(i2c_slave_class, NULL, + MKDEV(i2c_slave_major, device->id), + NULL, "slave-i2c-%d", device->id); + if (!device->dev) { + return -1; + } + i2c_slave_devices[device->id] = device; + return 0; +} + +void i2c_slave_device_unregister(i2c_slave_device_t *device) +{ + device_destroy(i2c_slave_class, MKDEV(i2c_slave_major, device->id)); + i2c_slave_devices[device->id] = 0; + i2c_slave_device_free(device); +} + +/* + this two functions are used by i2c slave core to start or stop the specific i2c device. +*/ +int i2c_slave_device_start(i2c_slave_device_t *device) +{ + return device->start(device); +} + +int i2c_slave_device_stop(i2c_slave_device_t *device) +{ + return device->stop(device); +} + +/* + this two functions are used by i2c slave core to get data by the specific i2c slave device + or send data to it to feed i2c master's need. + + @mod: async(1) or sync(0) mode. +*/ +int i2c_slave_device_read(i2c_slave_device_t *device, int num, u8 *data) +{ + int read_num, read_total = 0; + int step = 1000; + u8 *read_buf = data; + printk(KERN_INFO "%s: device id=%d, num=%d\n", __func__, device->id, + num); + read_num = i2c_slave_rb_consume(device->receive_buffer, num, read_buf); + read_total += read_num; + read_buf += read_num; + step--; + while ((read_total < num) && step) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(HZ / 10); + if (!signal_pending(current)) { + } else { + /*TODO*/ break; + } + read_num = + i2c_slave_rb_consume(device->receive_buffer, + num - read_total, read_buf); + num -= read_num; + read_buf += read_num; + step--; + } + return read_total; +} +int i2c_slave_device_write(i2c_slave_device_t *device, int num, u8 *data) +{ + int write_num, write_total = 0; + int step = 1000; + u8 *buf_index = data; + write_num = i2c_slave_rb_produce(device->send_buffer, num, buf_index); + write_total += write_num; + buf_index += write_num; + step--; + while (write_total < num && step) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(HZ / 10); + if (!signal_pending(current)) { + } else { + /*TODO*/ step = 0; + break; + } + write_num = + i2c_slave_rb_produce(device->send_buffer, num - write_total, + buf_index); + write_total += write_num; + buf_index += write_num; + step--; + } + while (step && i2c_slave_rb_num(device->send_buffer)) { + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(HZ / 10); + if (!signal_pending(current)) { + step--; + } else { + /*TODO*/ step = 0; + break; + } + } + if (!step) { + write_total -= i2c_slave_rb_num(device->send_buffer); + i2c_slave_rb_clear(device->send_buffer); + } + return write_total; +} + +/* + * this 2 functions used by the specific i2c slave device when they got data from master(produce), + * or is request by master(consume). + */ +int i2c_slave_device_produce(i2c_slave_device_t *device, int num, u8 *data) +{ + int ret; + ret = i2c_slave_rb_produce(device->receive_buffer, num, data); + return ret; +} +int i2c_slave_device_consume(i2c_slave_device_t *device, int num, u8 *data) +{ + return i2c_slave_rb_consume(device->send_buffer, num, data); +} + +EXPORT_SYMBOL(i2c_slave_device_set_name); +EXPORT_SYMBOL(i2c_slave_device_set_address); +EXPORT_SYMBOL(i2c_slave_device_get_addr); +EXPORT_SYMBOL(i2c_slave_device_find); +EXPORT_SYMBOL(i2c_slave_device_set_freq); +EXPORT_SYMBOL(i2c_slave_device_get_freq); + +/* +* used by the specific i2c device to register itself to the core. +*/ +EXPORT_SYMBOL(i2c_slave_device_alloc); +EXPORT_SYMBOL(i2c_slave_device_free); +EXPORT_SYMBOL(i2c_slave_device_register); +EXPORT_SYMBOL(i2c_slave_device_unregister); + +/* + this two functions are used by i2c slave core to start or stop the specific i2c device. +*/ +EXPORT_SYMBOL(i2c_slave_device_start); +EXPORT_SYMBOL(i2c_slave_device_stop); + +/* + this two functions are used by i2c slave core to get data by the specific i2c slave device + or send data to it for it to feed i2c master's need. + + @mod: async(1) or sync(0) mode. +*/ +EXPORT_SYMBOL(i2c_slave_device_read); +EXPORT_SYMBOL(i2c_slave_device_write); + +/* +* this 2 functions used by the specific i2c slave device when they got data from master, +* or is request by master. +*/ +EXPORT_SYMBOL(i2c_slave_device_produce); +EXPORT_SYMBOL(i2c_slave_device_consume); diff --git a/drivers/i2c-slave/i2c_slave_device.h b/drivers/i2c-slave/i2c_slave_device.h new file mode 100644 index 000000000000..472782cd230d --- /dev/null +++ b/drivers/i2c-slave/i2c_slave_device.h @@ -0,0 +1,79 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __I2C_SLAVE_H__ +#define __I2C_SLAVE_H__ + +#include +#include "i2c_slave_ring_buffer.h" + +#define I2C_SLAVE_DEVICE_MAX 256 +extern int i2c_slave_major; + +typedef struct i2c_slave_device { + struct list_head list; + u8 address; + u32 scl_freq; + char *name; + i2c_slave_ring_buffer_t *receive_buffer; + i2c_slave_ring_buffer_t *send_buffer; + int (*start) (struct i2c_slave_device *); + int (*stop) (struct i2c_slave_device *); + /*int (*set_freq)(struct i2c_slave_device*); + int (*set_addr)(struct i2c_slave_device*);*/ + void *private_data; + struct device *dev; + int id; +} i2c_slave_device_t; + +/* + used by the specific device to set some infomations. +*/ +void i2c_slave_device_set_name(i2c_slave_device_t *device, char *name); +void i2c_slave_device_set_address(i2c_slave_device_t *device, u8 address); +i2c_slave_device_t *i2c_slave_device_find(int id); +u8 i2c_slave_device_get_addr(i2c_slave_device_t *device); +int i2c_slave_device_set_freq(i2c_slave_device_t *device, u32 freq); +u32 i2c_slave_device_get_freq(i2c_slave_device_t *device); + +/* +**used by the specific i2c device to register itself to the core. +*/ +i2c_slave_device_t *i2c_slave_device_alloc(void); +void i2c_slave_device_free(i2c_slave_device_t *); +int i2c_slave_device_register(i2c_slave_device_t *device); +void i2c_slave_device_unregister(i2c_slave_device_t *device); + +/* + this two functions are used by i2c slave core to start or stop the specific i2c device. +*/ +int i2c_slave_device_start(i2c_slave_device_t *device); +int i2c_slave_device_stop(i2c_slave_device_t *device); + +/* + this two functions are used by i2c slave core to get data by the specific i2c slave device + or send data to it for it to feed i2c master's need. + + @mod: async(1) or sync(0) mode. +*/ +int i2c_slave_device_read(i2c_slave_device_t *device, int num, u8 *data); +int i2c_slave_device_write(i2c_slave_device_t *device, int num, u8 *data); + +/* +*this 2 functions used by the specific i2c slave device when they got data from master, +*or is requested by master. +*/ +int i2c_slave_device_produce(i2c_slave_device_t *device, int num, u8 *data); +int i2c_slave_device_consume(i2c_slave_device_t *device, int num, u8 *data); + +#endif diff --git a/drivers/i2c-slave/i2c_slave_ring_buffer.c b/drivers/i2c-slave/i2c_slave_ring_buffer.c new file mode 100644 index 000000000000..2f7be580c197 --- /dev/null +++ b/drivers/i2c-slave/i2c_slave_ring_buffer.c @@ -0,0 +1,185 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include "i2c_slave_ring_buffer.h" + +i2c_slave_ring_buffer_t *i2c_slave_rb_alloc(int size) +{ + i2c_slave_ring_buffer_t *ring_buf; + + ring_buf = + (i2c_slave_ring_buffer_t *) kzalloc(sizeof(i2c_slave_ring_buffer_t), + GFP_KERNEL); + if (!ring_buf) { + pr_debug("%s: alloc ring_buf error\n", __func__); + goto error; + } + + ring_buf->buffer = kmalloc(size, GFP_KERNEL); + if (!ring_buf->buffer) { + pr_debug("%s: alloc buffer error\n", __func__); + goto error1; + } + + ring_buf->total = size; + + ring_buf->lock = __SPIN_LOCK_UNLOCKED(ring_buf->lock); + return ring_buf; + + error1: + kfree(ring_buf); + error: + return NULL; +} + +void i2c_slave_rb_release(i2c_slave_ring_buffer_t *ring) +{ + unsigned long flags; + + spin_lock_irqsave(ring->lock, flags); + kfree(ring->buffer); + spin_unlock_irqrestore(ring->lock, flags); + kfree(ring); +} + +int i2c_slave_rb_produce(i2c_slave_ring_buffer_t *ring, int num, char *data) +{ + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(ring->lock, flags); + + if (ring->start < ring->end) { + if ((ring->start + num) < ring->end) { /*have enough space */ + memcpy(&ring->buffer[ring->start], data, num); + ring->start += num; + ret = num; + } else { /*space not enough, just copy part of it. */ + ret = ring->end - ring->start; + memcpy(&ring->buffer[ring->start], data, ret); + ring->start += ret; + ring->full = 1; + } + } else if (ring->start >= ring->end && !ring->full) { + if (ring->start + num <= ring->total) { /*space enough */ + ret = num; + memcpy(&ring->buffer[ring->start], data, ret); + ring->start += ret; + } else { /*turn ring->start around */ + ret = ring->total - ring->start; + memcpy(&ring->buffer[ring->start], data, ret); + ring->start = 0; + num -= ret; + data += ret; + if (num < ring->end) { /*space enough */ + ret += num; + memcpy(&ring->buffer[ring->start], data, num); + } else { /*space not enough, just copy part of it. */ + ret += ring->end; + memcpy(&ring->buffer[ring->start], data, + ring->end); + ring->start = ring->end; + ring->full = 1; + } + } + } else { /*(ring->data == ring->end) && ring->full ) : full */ + ret = 0; + } + + spin_unlock_irqrestore(ring->lock, flags); + return ret; +} + +int i2c_slave_rb_consume(i2c_slave_ring_buffer_t *ring, int num, char *data) +{ + int ret; + unsigned long flags; + spin_lock_irqsave(ring->lock, flags); + if (num <= 0) { + ret = 0; + goto out; + } + + if (ring->start > ring->end) { + if (num <= ring->start - ring->end) { /*enough */ + ret = num; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end += ret; + } else { /*not enough */ + ret = ring->start - ring->end; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end += ret; + } + } else if (ring->start < ring->end || ring->full) { + if (num <= ring->total - ring->end) { + ret = ring->total - ring->end; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end += ret; + } else if (num <= ring->total - ring->end + ring->start) { + ret = ring->total - ring->end; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end = 0; + data += ret; + num -= ret; + memcpy(data, &ring->buffer[ring->end], num); + ring->end = num; + ret += num; + } else { + ret = ring->total - ring->end; + memcpy(data, &ring->buffer[ring->end], ret); + ring->end = 0; + data += ret; + num -= ret; + memcpy(data, &ring->buffer[ring->end], ring->start); + ring->end = ring->start; + ret += ring->start; + } + ring->full = 0; + } else { /*empty */ + ret = 0; + } + + out: + spin_unlock_irqrestore(ring->lock, flags); + + return ret; +} + +int i2c_slave_rb_num(i2c_slave_ring_buffer_t *ring) +{ + int ret; + unsigned long flags; + spin_lock_irqsave(ring->lock, flags); + if (ring->start > ring->end) { + ret = ring->start - ring->end; + } else if (ring->start < ring->end) { + ret = ring->total - ring->end + ring->start; + } else if (ring->full) { + ret = ring->total; + } else { + ret = 0; + } + spin_unlock_irqrestore(ring->lock, flags); + return ret; +} + +void i2c_slave_rb_clear(i2c_slave_ring_buffer_t *ring) +{ + unsigned long flags; + spin_lock_irqsave(ring->lock, flags); + + ring->start = ring->end = 0; + ring->full = 0; + spin_unlock_irqrestore(ring->lock, flags); +} diff --git a/drivers/i2c-slave/i2c_slave_ring_buffer.h b/drivers/i2c-slave/i2c_slave_ring_buffer.h new file mode 100644 index 000000000000..32fc21b618ed --- /dev/null +++ b/drivers/i2c-slave/i2c_slave_ring_buffer.h @@ -0,0 +1,39 @@ +#ifndef __BUFFER_MANAGER_H__ +#define __BUFFER_MANAGER_H__ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include + +typedef struct i2c_slave_ring_buffer { + int start; + int end; + int total; + bool full; + char *buffer; + spinlock_t lock; +} i2c_slave_ring_buffer_t; + +i2c_slave_ring_buffer_t *i2c_slave_rb_alloc(int size); + +void i2c_slave_rb_release(i2c_slave_ring_buffer_t *ring); + +int i2c_slave_rb_produce(i2c_slave_ring_buffer_t *ring, int num, char *data); + +int i2c_slave_rb_consume(i2c_slave_ring_buffer_t *ring, int num, char *data); + +int i2c_slave_rb_num(i2c_slave_ring_buffer_t *ring); + +void i2c_slave_rb_clear(i2c_slave_ring_buffer_t *ring); + +#endif diff --git a/drivers/i2c-slave/mxc_i2c_slave.c b/drivers/i2c-slave/mxc_i2c_slave.c new file mode 100644 index 000000000000..347c015afd22 --- /dev/null +++ b/drivers/i2c-slave/mxc_i2c_slave.c @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "i2c_slave_device.h" +#include "mxc_i2c_slave.h" +#include "mxc_i2c_slave_reg.h" + +struct mxc_i2c_slave_clk { + int reg_value; + int div; +}; + +static const struct mxc_i2c_slave_clk i2c_clk_table[] = { + {0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28}, + {0, 30}, {1, 32}, {0x24, 32}, {2, 36}, + {0x25, 36}, {0x26, 40}, {3, 42}, {0x27, 44}, + {4, 48}, {0x28, 48}, {5, 52}, {0x29, 56}, + {6, 60}, {0x2A, 64}, {7, 72}, {0x2B, 72}, + {8, 80}, {0x2C, 80}, {9, 88}, {0x2D, 96}, + {0xA, 104}, {0x2E, 112}, {0xB, 128}, {0x2F, 128}, + {0xC, 144}, {0xD, 160}, {0x30, 160}, {0xE, 192}, + {0x31, 192}, {0x32, 224}, {0xF, 240}, {0x33, 256}, + {0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384}, + {0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512}, + {0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768}, + {0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024}, + {0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536}, + {0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048}, + {0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840}, + {0, 0} +}; + +extern void gpio_i2c_active(int i2c_num); +extern void gpio_i2c_inactive(int i2c_num); + +static irqreturn_t interrupt_handler(int irq, void *dev_id) +{ + u16 status, ctl; + int num; + u16 data; + struct mxc_i2c_slave_device *mxc_i2c = + (struct mxc_i2c_slave_device *)dev_id; + + status = readw(mxc_i2c->reg_base + MXC_I2SR); + ctl = readw(mxc_i2c->reg_base + MXC_I2CR); + + dev_dbg(mxc_i2c->dev->dev, "status=%x, ctl=%x\n", status, ctl); + + if (status & MXC_I2SR_IAAS) { + if (status & MXC_I2SR_SRW) { + /*slave send */ + num = + i2c_slave_device_consume(mxc_i2c->dev, 1, + (u8 *) &data); + if (num < 1) { + /*FIXME:not ready to send data */ + printk(KERN_ERR + " i2c-slave:%s:data not ready\n", + __func__); + } else { + ctl |= MXC_I2CR_MTX; + writew(ctl, mxc_i2c->reg_base + MXC_I2CR); + /*send data */ + writew(data, mxc_i2c->reg_base + MXC_I2DR); + } + + } else { + /*slave receive */ + ctl &= ~MXC_I2CR_MTX; + writew(ctl, mxc_i2c->reg_base + MXC_I2CR); + + /*dummy read */ + data = readw(mxc_i2c->reg_base + MXC_I2DR); + } + } else { + /*slave send */ + if (ctl & MXC_I2CR_MTX) { + if (!(status & MXC_I2SR_RXAK)) { /*ACK received */ + num = + i2c_slave_device_consume(mxc_i2c->dev, 1, + (u8 *) &data); + if (num < 1) { + /*FIXME:not ready to send data */ + printk(KERN_ERR + " i2c-slave:%s:data not ready\n", + __func__); + } else { + ctl |= MXC_I2CR_MTX; + writew(ctl, + mxc_i2c->reg_base + MXC_I2CR); + writew(data, + mxc_i2c->reg_base + MXC_I2DR); + } + } else { + /*no ACK. */ + /*dummy read */ + ctl &= ~MXC_I2CR_MTX; + writew(ctl, mxc_i2c->reg_base + MXC_I2CR); + data = readw(mxc_i2c->reg_base + MXC_I2DR); + } + } else { /*read */ + ctl &= ~MXC_I2CR_MTX; + writew(ctl, mxc_i2c->reg_base + MXC_I2CR); + + /*read */ + data = readw(mxc_i2c->reg_base + MXC_I2DR); + i2c_slave_device_produce(mxc_i2c->dev, 1, + (u8 *) &data); + } + + } + + writew(0x0, mxc_i2c->reg_base + MXC_I2SR); + + return IRQ_HANDLED; +} + +static int start(i2c_slave_device_t *device) +{ + volatile unsigned int cr; + unsigned int addr; + struct mxc_i2c_slave_device *mxc_dev; + + mxc_dev = (struct mxc_i2c_slave_device *)device->private_data; + if (!mxc_dev) { + dev_err(device->dev, "%s: get mxc_dev error\n", __func__); + return -ENODEV; + } + + clk_enable(mxc_dev->clk); + /* Set the frequency divider */ + writew(mxc_dev->clkdiv, mxc_dev->reg_base + MXC_IFDR); + + /* Set the Slave bit */ + cr = readw(mxc_dev->reg_base + MXC_I2CR); + cr &= (!MXC_I2CR_MSTA); + writew(cr, mxc_dev->reg_base + MXC_I2CR); + + /*Set Slave Address */ + addr = mxc_dev->dev->address << 1; + writew(addr, mxc_dev->reg_base + MXC_IADR); + + /* Clear the status register */ + writew(0x0, mxc_dev->reg_base + MXC_I2SR); + + /* Enable I2C and its interrupts */ + writew(MXC_I2CR_IEN, mxc_dev->reg_base + MXC_I2CR); + writew(MXC_I2CR_IEN | MXC_I2CR_IIEN, mxc_dev->reg_base + MXC_I2CR); + + return 0; + +} + +static int stop(i2c_slave_device_t *device) +{ + struct mxc_i2c_slave_device *mxc_dev; + + mxc_dev = (struct mxc_i2c_slave_device *)device->private_data; + + writew(0x0, mxc_dev->reg_base + MXC_I2CR); + clk_disable(mxc_dev->clk); + + return 0; +} + +static int mxc_i2c_slave_probe(struct platform_device *pdev) +{ + int i; + u32 clk_freq; + struct resource *res; + struct mxc_i2c_slave_device *mxc_dev; + + mxc_dev = kzalloc(sizeof(struct mxc_i2c_slave_device), GFP_KERNEL); + if (!mxc_dev) { + goto error0; + } + mxc_dev->dev = i2c_slave_device_alloc(); + if (mxc_dev->dev == 0) { + dev_err(&pdev->dev, "%s: i2c_slave_device_alloc error\n", + __func__); + goto error1; + } + + i2c_slave_device_set_address(mxc_dev->dev, MXC_I2C_SLAVE_ADDRESS); + i2c_slave_device_set_freq(mxc_dev->dev, MXC_I2C_SLAVE_FREQ); + i2c_slave_device_set_name(mxc_dev->dev, MXC_I2C_SLAVE_NAME); + mxc_dev->dev->start = start; + mxc_dev->dev->stop = stop; + + mxc_dev->dev->private_data = mxc_dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "%s: get resource error\n", __func__); + goto error2; + } + mxc_dev->reg_base = ioremap(res->start, res->end - res->start + 1); + + mxc_dev->irq = platform_get_irq(pdev, 0); + if (mxc_dev->irq < 0) { + dev_err(&pdev->dev, "%s: get irq error\n", __func__); + goto error3; + } + if (request_irq(mxc_dev->irq, interrupt_handler, + 0, mxc_dev->dev->name, mxc_dev) < 0) { + dev_err(&pdev->dev, "%s: request_irq error\n", __func__); + goto error3; + } + + /*i2c id on soc */ + mxc_dev->id = pdev->id; + + gpio_i2c_active(mxc_dev->id); + + /*clock */ + mxc_dev->clk = clk_get(&pdev->dev, "i2c_clk"); + clk_freq = clk_get_rate(mxc_dev->clk); + mxc_dev->clkdiv = -1; + if (mxc_dev->dev->scl_freq) { + /* Calculate divider and round up any fractional part */ + int div = (clk_freq + mxc_dev->dev->scl_freq - 1) / + mxc_dev->dev->scl_freq; + for (i = 0; i2c_clk_table[i].div != 0; i++) { + if (i2c_clk_table[i].div >= div) { + mxc_dev->clkdiv = i2c_clk_table[i].reg_value; + break; + } + } + } + if (mxc_dev->clkdiv == -1) { + i--; + mxc_dev->clkdiv = 0x1F; /* Use max divider */ + } + dev_dbg(&pdev->dev, + "i2c slave speed is %d/%d = %d bps, reg val = 0x%02X\n", + clk_freq, i2c_clk_table[i].div, clk_freq / i2c_clk_table[i].div, + mxc_dev->clkdiv); + + if (i2c_slave_device_register(mxc_dev->dev) < 0) { + dev_err(&pdev->dev, "%s: i2c_slave_device_register error\n", + __func__); + goto error4; + } + + platform_set_drvdata(pdev, (void *)mxc_dev); + + /*start(mxc_dev->dev); */ + return 0; + + error4: + free_irq(mxc_dev->irq, mxc_dev); + error3: + iounmap(mxc_dev->reg_base); + error2: + i2c_slave_device_free(mxc_dev->dev); + error1: + kfree(mxc_dev); + error0: + return -ENODEV; +} + +static int mxc_i2c_slave_remove(struct platform_device *pdev) +{ + struct mxc_i2c_slave_device *mxc_dev; + mxc_dev = (struct mxc_i2c_slave_device *)platform_get_drvdata(pdev); + + i2c_slave_device_unregister(mxc_dev->dev); + free_irq(mxc_dev->irq, mxc_dev); + iounmap(mxc_dev->reg_base); + kfree((void *)mxc_dev); + + return 0; +} + +static int mxc_i2c_slave_suspend(struct platform_device *pdev, + pm_message_t state) +{ + return 0; +} + +static int mxc_i2c_slave_resume(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver mxci2c_slave_driver = { + .driver = { + .name = "mxc_i2c_slave", + .owner = THIS_MODULE, + }, + .probe = mxc_i2c_slave_probe, + .remove = mxc_i2c_slave_remove, + .suspend = mxc_i2c_slave_suspend, + .resume = mxc_i2c_slave_resume, +}; + +static int __init mxc_i2c_slave_init(void) +{ + /* Register the device driver structure. */ + return platform_driver_register(&mxci2c_slave_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxc_i2c_slave_exit(void) +{ + platform_driver_unregister(&mxci2c_slave_driver); +} + +module_init(mxc_i2c_slave_init); +module_exit(mxc_i2c_slave_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC I2C Slave Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/i2c-slave/mxc_i2c_slave.h b/drivers/i2c-slave/mxc_i2c_slave.h new file mode 100644 index 000000000000..b3045dc4a2c5 --- /dev/null +++ b/drivers/i2c-slave/mxc_i2c_slave.h @@ -0,0 +1,44 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_I2C_SLAVE_H__ +#define __MXC_I2C_SLAVE_H__ + +#include +#include "i2c_slave_device.h" + +#define MXC_I2C_SLAVE_NAME "MXC_I2C_SLAVE" +#define MXC_I2C_SLAVE_ADDRESS 0x55 +#define MXC_I2C_SLAVE_FREQ (1000*100) + +struct mxc_i2c_slave_device { + /*! + * The default clock divider value to be used. + */ + unsigned int clkdiv; + + /*! + * The clock source for the device. + */ + struct clk *clk; + + /*i2c id on soc */ + int id; + + int irq; + unsigned long reg_base; + bool state; /*0:stop, 1:start */ + i2c_slave_device_t *dev; +}; + +#endif diff --git a/drivers/i2c-slave/mxc_i2c_slave_reg.h b/drivers/i2c-slave/mxc_i2c_slave_reg.h new file mode 100644 index 000000000000..52a04e06f810 --- /dev/null +++ b/drivers/i2c-slave/mxc_i2c_slave_reg.h @@ -0,0 +1,41 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_I2C_SLAVE_REG_H__ +#define __MXC_I2C_SLAVE_REG_H__ + +/* Address offsets of the I2C registers */ +#define MXC_IADR 0x00 /* Address Register */ +#define MXC_IFDR 0x04 /* Freq div register */ +#define MXC_I2CR 0x08 /* Control regsiter */ +#define MXC_I2SR 0x0C /* Status register */ +#define MXC_I2DR 0x10 /* Data I/O register */ + +/* Bit definitions of I2CR */ +#define MXC_I2CR_IEN 0x0080 +#define MXC_I2CR_IIEN 0x0040 +#define MXC_I2CR_MSTA 0x0020 +#define MXC_I2CR_MTX 0x0010 +#define MXC_I2CR_TXAK 0x0008 +#define MXC_I2CR_RSTA 0x0004 + +/* Bit definitions of I2SR */ +#define MXC_I2SR_ICF 0x0080 +#define MXC_I2SR_IAAS 0x0040 +#define MXC_I2SR_IBB 0x0020 +#define MXC_I2SR_IAL 0x0010 +#define MXC_I2SR_SRW 0x0004 +#define MXC_I2SR_IIF 0x0002 +#define MXC_I2SR_RXAK 0x0001 + +#endif /* __MXC_I2C_REG_H__ */ diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index bceafbfa7268..d72d0f0ccb44 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -431,6 +431,64 @@ config I2C_MPC This driver can also be built as a module. If so, the module will be called i2c-mpc. +config I2C_MXC + tristate "MXC I2C support" + depends on I2C && ARCH_MXC + help + If you say yes to this option, support will be included for Freescale + MXC I2C modules. + + This driver can also be built as a module. + +config I2C_MXC_HS + tristate "MXC HIGH SPEED I2C support" + depends on I2C && ARCH_MXC + help + If you say yes to this option, support will be included for Freescale + MXC HIGH SPEED I2C modules. + + This driver can also be built as a module. + +config I2C_MXS + tristate "MXS I2C Support" + depends on I2C && ARCH_MXS + help + If you say yes to this option, support will be included for Freescale + MXS I2C modules. + +config I2C_MXS_SELECT0 + bool "Enable I2C0 module" + default y + depends on I2C_MXS + help + Enable MXS I2C0 Module + +config I2C_MXS_SELECT0_PIOQUEUE_MODE + tristate "MXS I2C0 PIOQUEUE MODE Support" + depends on (I2C_MXS_SELECT0 && !ARCH_MX23) + help + say yes if you are sure transfer length is eqaul to or less than 24 bytes. + Otherwise say no to use DMA mode by default. + +config I2C_MXS_SELECT1 + bool "Enable I2C1 module" + depends on (I2C_MXS && !ARCH_MX23) + help + Enable MXS I2C1 Module + +config I2C_MXS_SELECT1_PIOQUEUE_MODE + tristate "MXS I2C1 PIOQUEUE MODE Support" + depends on I2C_MXS_SELECT1 + help + say yes if you are sure transfer length is eqaul to or less than 24 bytes. + Otherwise say no to use DMA mode by default. + +config I2C_STMP378X + tristate "STMP378x I2C adapter" + depends on MACH_STMP378X + help + TBD + config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" depends on (MV64X60 || PLAT_ORION) && EXPERIMENTAL diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 936880bd1dc5..0b25b7baa449 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -74,6 +74,10 @@ obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o obj-$(CONFIG_I2C_STUB) += i2c-stub.o obj-$(CONFIG_SCx200_ACB) += scx200_acb.o obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o +obj-$(CONFIG_I2C_MXC) += mxc_i2c.o +obj-$(CONFIG_I2C_MXC_HS) += mxc_i2c_hs.o +obj-$(CONFIG_I2C_STMP378X) += i2c-stmp378x.o +obj-$(CONFIG_I2C_MXS) += i2c-mxs.o ifeq ($(CONFIG_I2C_DEBUG_BUS),y) EXTRA_CFLAGS += -DDEBUG diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c new file mode 100644 index 000000000000..852b2eda5dc4 --- /dev/null +++ b/drivers/i2c/busses/i2c-mxs.c @@ -0,0 +1,611 @@ +/* + * Freescale MX28 I2C bus driver + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "i2c-mxs.h" + +/* 2 for read, 1 for write */ +#define NR_DESC 3 +static struct mxs_dma_desc *desc[NR_DESC]; +static dma_addr_t i2c_buf_phys; +static u8 *i2c_buf_virt; + +#define CMD_I2C_SELECT (BM_I2C_CTRL0_RETAIN_CLOCK | \ + BM_I2C_CTRL0_PRE_SEND_START | \ + BM_I2C_CTRL0_MASTER_MODE | \ + BM_I2C_CTRL0_DIRECTION | \ + BF_I2C_CTRL0_XFER_COUNT(1)) +#define CMD_I2C_WRITE (BM_I2C_CTRL0_PRE_SEND_START | \ + BM_I2C_CTRL0_MASTER_MODE | \ + BM_I2C_CTRL0_DIRECTION) +#define CMD_I2C_READ (BM_I2C_CTRL0_SEND_NAK_ON_LAST | \ + BM_I2C_CTRL0_MASTER_MODE) + +/* Hack for platform which does not support PioQueue Mode */ +#if !defined(HW_I2C_QUEUECMD) || \ + !defined(HW_I2C_QUEUEDATA) || \ + !defined(HW_I2C_QUEUECTRL_CLR) || \ + !defined(HW_I2C_QUEUECTRL_SET) +#warning "Pio Queue Mode *NOT* Support!" +#define HW_I2C_QUEUECMD HW_I2C_VERSION +#define HW_I2C_QUEUEDATA HW_I2C_VERSION +#define HW_I2C_QUEUECTRL_SET HW_I2C_VERSION +#define HW_I2C_QUEUECTRL_CLR HW_I2C_VERSION +#endif + +static void hw_i2c_dmachan_reset(struct mxs_i2c_dev *dev) +{ + mxs_dma_disable(dev->dma_chan); + mxs_dma_reset(dev->dma_chan); + mxs_dma_ack_irq(dev->dma_chan); +} + +static mxs_i2c_reset(struct mxs_i2c_dev *mxs_i2c) +{ + hw_i2c_dmachan_reset(mxs_i2c); + mxs_dma_enable_irq(mxs_i2c->dma_chan, 1); + mxs_reset_block((void __iomem *)mxs_i2c->regbase, 0); + __raw_writel(0x0000FF00, mxs_i2c->regbase + HW_I2C_CTRL1_SET); +} + +static int hw_i2c_dma_init(struct platform_device *pdev) +{ + struct mxs_i2c_dev *mxs_i2c = platform_get_drvdata(pdev); + int i, ret; + + ret = mxs_dma_request(mxs_i2c->dma_chan, &pdev->dev, "i2c"); + if (ret) + return ret; + + for (i = 0; i < NR_DESC; i++) { + desc[i] = mxs_dma_alloc_desc(); + if (desc[i] == NULL) + goto err; + } + + i2c_buf_virt = dma_alloc_coherent(&pdev->dev, + PAGE_SIZE, &i2c_buf_phys, GFP_KERNEL); + if (i2c_buf_virt == NULL) + goto err; + + hw_i2c_dmachan_reset(mxs_i2c); + mxs_dma_enable_irq(mxs_i2c->dma_chan, 1); + + return 0; + +err: + while (--i >= 0) + mxs_dma_free_desc(desc[i]); + + return -ENOMEM; +} + +static void hw_i2c_dma_uninit(struct platform_device *pdev) +{ + struct mxs_i2c_dev *mxs_i2c = platform_get_drvdata(pdev); + int i; + LIST_HEAD(list); + + mxs_dma_enable_irq(mxs_i2c->dma_chan, 0); + mxs_dma_get_cooked(mxs_i2c->dma_chan, &list); + mxs_dma_disable(mxs_i2c->dma_chan); + + for (i = 0; i < NR_DESC; i++) + mxs_dma_free_desc(desc[i]); + + hw_i2c_dmachan_reset(mxs_i2c); + + dma_free_coherent(&pdev->dev, PAGE_SIZE, i2c_buf_virt, i2c_buf_phys); + + mxs_dma_release(mxs_i2c->dma_chan, &pdev->dev); +} + +static void hw_i2c_pioq_setup_read(struct mxs_i2c_dev *dev, + u8 addr, void *buff, int len, int flags) +{ + u32 queuecmd; + u32 queuedata; + + WARN_ONCE(len > 24, "choose DMA mode if xfer len > 24 bytes\n"); + + /* fill queue cmd */ + queuecmd = CMD_I2C_SELECT; + __raw_writel(queuecmd, dev->regbase + HW_I2C_QUEUECMD); + + /* fill data (slave addr) */ + queuedata = (addr << 1) | I2C_READ; + __raw_writel(queuedata, dev->regbase + HW_I2C_DATA); + + /* fill queue cmd */ + queuecmd = CMD_I2C_READ | flags; + queuecmd |= BF_I2C_CTRL0_XFER_COUNT(len) | flags; + __raw_writel(queuecmd, dev->regbase + HW_I2C_QUEUECMD); + +} + +static void hw_i2c_dma_setup_read(u8 addr, void *buff, int len, int flags) +{ + if (len > (PAGE_SIZE - 4)) + BUG(); + + memset(&desc[0]->cmd, 0, sizeof(desc[0]->cmd)); + memset(&desc[1]->cmd, 0, sizeof(desc[1]->cmd)); + + desc[0]->cmd.cmd.bits.bytes = 1; + desc[0]->cmd.cmd.bits.pio_words = 1; + desc[0]->cmd.cmd.bits.wait4end = 1; + desc[0]->cmd.cmd.bits.dec_sem = 1; + desc[0]->cmd.cmd.bits.irq = 0; + desc[0]->cmd.cmd.bits.chain = 1; + desc[0]->cmd.cmd.bits.command = DMA_READ; + desc[0]->cmd.address = i2c_buf_phys; + desc[0]->cmd.pio_words[0] = CMD_I2C_SELECT; + i2c_buf_virt[0] = (addr << 1) | I2C_READ; + + desc[1]->cmd.cmd.bits.bytes = len; + desc[1]->cmd.cmd.bits.pio_words = 1; + desc[1]->cmd.cmd.bits.wait4end = 1; + desc[1]->cmd.cmd.bits.dec_sem = 1; + desc[1]->cmd.cmd.bits.irq = 1; + desc[1]->cmd.cmd.bits.command = DMA_WRITE; + desc[1]->cmd.address = (u32) i2c_buf_phys + 1; + desc[1]->cmd.pio_words[0] = CMD_I2C_READ; + desc[1]->cmd.pio_words[0] |= BF_I2C_CTRL0_XFER_COUNT(len) | flags; +} + +static void hw_i2c_pioq_setup_write(struct mxs_i2c_dev *dev, + u8 addr, void *buff, int len, int flags) +{ + int align_len, i; + u8 slaveaddr; + u32 queuecmd; + u8 *buf1; + u32 *buf2; + + WARN_ONCE(len > 24, "choose DMA mode if xfer len > 24 bytes\n"); + + align_len = (len + 1 + 3) & ~3; + + buf1 = (u8 *) dev->buf; + buf2 = (u32 *) dev->buf; + + /* fill queue cmd */ + queuecmd = CMD_I2C_WRITE; + queuecmd |= BF_I2C_CTRL0_XFER_COUNT(len + 1) | flags; + __raw_writel(queuecmd, dev->regbase + HW_I2C_QUEUECMD); + + /* fill data (slave addr) */ + slaveaddr = (addr << 1) | I2C_WRITE; + memcpy(buf1, &slaveaddr, 1); + + memcpy(&buf1[1], buff, len); + + /* fill data */ + for (i = 0; i < align_len / 4; i++) + __raw_writel(*buf2++, dev->regbase + HW_I2C_DATA); +} + +static void hw_i2c_dma_setup_write(u8 addr, void *buff, int len, int flags) +{ + memset(&desc[2]->cmd, 0, sizeof(desc[2]->cmd)); + + desc[2]->cmd.cmd.bits.bytes = len + 1; + desc[2]->cmd.cmd.bits.pio_words = 1; + desc[2]->cmd.cmd.bits.wait4end = 1; + desc[2]->cmd.cmd.bits.dec_sem = 1; + desc[2]->cmd.cmd.bits.irq = 1; + desc[2]->cmd.cmd.bits.command = DMA_READ; + desc[2]->cmd.address = i2c_buf_phys; + desc[2]->cmd.pio_words[0] = CMD_I2C_WRITE; + desc[2]->cmd.pio_words[0] |= BM_I2C_CTRL0_POST_SEND_STOP; + desc[2]->cmd.pio_words[0] |= BF_I2C_CTRL0_XFER_COUNT(len + 1) | flags; + + i2c_buf_virt[0] = (addr << 1) | I2C_WRITE; + memcpy(&i2c_buf_virt[1], buff, len); +} + +static void hw_i2c_pioq_run(struct mxs_i2c_dev *dev) +{ + __raw_writel(0x20, dev->regbase + HW_I2C_QUEUECTRL_SET); +} + +static void hw_i2c_dma_run(struct mxs_i2c_dev *dev, int dir) +{ + if (dir == I2C_READ) { + mxs_dma_desc_append(dev->dma_chan, desc[0]); + mxs_dma_desc_append(dev->dma_chan, desc[1]); + } else + mxs_dma_desc_append(dev->dma_chan, desc[2]); + + mxs_dma_enable(dev->dma_chan); +} + +static void hw_i2c_pioq_stop(struct mxs_i2c_dev *dev) +{ + __raw_writel(0x20, dev->regbase + HW_I2C_QUEUECTRL_CLR); +} + +static void hw_i2c_finish_read(struct mxs_i2c_dev *dev, void *buff, int len) +{ + int i, align_len; + u8 *buf1; + u32 *buf2; + + if (dev->flags & MXS_I2C_PIOQUEUE_MODE) { + align_len = (len + 3) & ~3; + + buf1 = (u8 *) dev->buf; + buf2 = (u32 *) dev->buf; + + for (i = 0; i < align_len / 4; i++) + *buf2++ = __raw_readl(dev->regbase + HW_I2C_QUEUEDATA); + + memcpy(buff, buf1, len); + } else + memcpy(buff, &i2c_buf_virt[1], len); +} + +/* + * Low level master read/write transaction. + */ +static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, + struct i2c_msg *msg, int stop) +{ + struct mxs_i2c_dev *dev = i2c_get_adapdata(adap); + int err; + int flags; + + init_completion(&dev->cmd_complete); + dev->cmd_err = 0; + + dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", + msg->addr, msg->len, msg->flags, stop); + + if ((msg->len == 0) || (msg->len > (PAGE_SIZE - 1))) + return -EINVAL; + + flags = stop ? BM_I2C_CTRL0_POST_SEND_STOP : 0; + + if (msg->flags & I2C_M_RD) { + if (dev->flags & MXS_I2C_PIOQUEUE_MODE) { + hw_i2c_pioq_setup_read(dev, + msg->addr, + msg->buf, msg->len, flags); + hw_i2c_pioq_run(dev); + } else { + hw_i2c_dma_setup_read(msg->addr, + msg->buf, msg->len, flags); + + hw_i2c_dma_run(dev, I2C_READ); + } + } else { + if (dev->flags & MXS_I2C_PIOQUEUE_MODE) { + hw_i2c_pioq_setup_write(dev, + msg->addr, + msg->buf, msg->len, flags); + hw_i2c_pioq_run(dev); + } else { + hw_i2c_dma_setup_write(msg->addr, + msg->buf, msg->len, flags); + hw_i2c_dma_run(dev, I2C_WRITE); + } + } + + err = wait_for_completion_interruptible_timeout(&dev->cmd_complete, + msecs_to_jiffies(1000) + ); + if (err <= 0) { + mxs_i2c_reset(dev); + dev_dbg(dev->dev, "controller is timed out\n"); + return -ETIMEDOUT; + } + + if ((!dev->cmd_err) && (msg->flags & I2C_M_RD)) + hw_i2c_finish_read(dev, msg->buf, msg->len); + + dev_dbg(dev->dev, "Done with err=%d\n", dev->cmd_err); + + return dev->cmd_err; +} + +static int +mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) +{ + int i; + int err; + + if (!msgs->len) + return -EINVAL; + + for (i = 0; i < num; i++) { + err = mxs_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); + if (err) + break; + } + + if (err == 0) + err = num; + + return err; +} + +static u32 mxs_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); +} + +static irqreturn_t mxs_i2c_dma_isr(int this_irq, void *dev_id) +{ + struct mxs_i2c_dev *mxs_i2c = dev_id; + + LIST_HEAD(list); + mxs_dma_ack_irq(mxs_i2c->dma_chan); + mxs_dma_cooked(mxs_i2c->dma_chan, &list); + + complete(&mxs_i2c->cmd_complete); + + return IRQ_HANDLED; +} + +static void mxs_i2c_task(struct work_struct *work) +{ + struct mxs_i2c_dev *mxs_i2c = container_of(work, + struct mxs_i2c_dev, work); + mxs_i2c_reset(mxs_i2c); + complete(&mxs_i2c->cmd_complete); +} + +#define I2C_IRQ_MASK 0x000000FF +static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) +{ + struct mxs_i2c_dev *mxs_i2c = dev_id; + u32 stat; + u32 done_mask = + BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | BM_I2C_CTRL1_BUS_FREE_IRQ; + + stat = __raw_readl(mxs_i2c->regbase + HW_I2C_CTRL1) & I2C_IRQ_MASK; + if (!stat) + return IRQ_NONE; + + if (stat & BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ) { + mxs_i2c->cmd_err = -EREMOTEIO; + /* it takes long time to reset i2c */ + schedule_work(&mxs_i2c->work); + goto done; + } + + /* Don't care about BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ */ + if (stat & (BM_I2C_CTRL1_EARLY_TERM_IRQ | + BM_I2C_CTRL1_MASTER_LOSS_IRQ | + BM_I2C_CTRL1_SLAVE_STOP_IRQ | BM_I2C_CTRL1_SLAVE_IRQ)) { + mxs_i2c->cmd_err = -EIO; + complete(&mxs_i2c->cmd_complete); + goto done; + } + + if ((stat & done_mask) == done_mask && + (mxs_i2c->flags & MXS_I2C_PIOQUEUE_MODE)) + + complete(&mxs_i2c->cmd_complete); + +done: + __raw_writel(stat, mxs_i2c->regbase + HW_I2C_CTRL1_CLR); + return IRQ_HANDLED; +} + +static const struct i2c_algorithm mxs_i2c_algo = { + .master_xfer = mxs_i2c_xfer, + .functionality = mxs_i2c_func, +}; + +static int mxs_i2c_probe(struct platform_device *pdev) +{ + struct mxs_i2c_dev *mxs_i2c; + struct mxs_i2c_plat_data *pdata; + struct i2c_adapter *adap; + struct resource *res; + int err = 0; + + mxs_i2c = kzalloc(sizeof(struct mxs_i2c_dev), GFP_KERNEL); + if (!mxs_i2c) { + dev_err(&pdev->dev, "no mem \n"); + return -ENOMEM; + } + + pdata = pdev->dev.platform_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no register base resource\n"); + err = -ENODEV; + goto nores; + } + mxs_i2c->regbase = (unsigned long)IO_ADDRESS(res->start); + + res = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!res) { + dev_err(&pdev->dev, "no dma channel resource\n"); + err = -ENODEV; + goto nores; + } + mxs_i2c->dma_chan = res->start; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, "no err_irq resource\n"); + err = -ENODEV; + goto nores; + } + mxs_i2c->irq_err = res->start; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + if (!res) { + dev_err(&pdev->dev, "no dma_irq resource\n"); + err = -ENODEV; + goto nores; + } + mxs_i2c->irq_dma = res->start; + + mxs_i2c->dev = &pdev->dev; + mxs_i2c->flags = pdata->pioqueue_mode ? + MXS_I2C_PIOQUEUE_MODE : MXS_I2C_DMA_MODE; + + err = + request_irq(mxs_i2c->irq_err, mxs_i2c_isr, 0, pdev->name, mxs_i2c); + if (err) { + dev_err(&pdev->dev, "Can't get IRQ\n"); + goto no_err_irq; + } + + err = + request_irq(mxs_i2c->irq_dma, mxs_i2c_dma_isr, 0, pdev->name, + mxs_i2c); + if (err) { + dev_err(&pdev->dev, "Can't get IRQ\n"); + goto no_dma_irq; + } + + /* reset I2C module */ + mxs_reset_block((void __iomem *)mxs_i2c->regbase, 1); + platform_set_drvdata(pdev, mxs_i2c); + + if (mxs_i2c->flags & MXS_I2C_PIOQUEUE_MODE) + __raw_writel(0x04, mxs_i2c->regbase + HW_I2C_QUEUECTRL_SET); + + mxs_i2c->buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (mxs_i2c->buf == NULL) { + dev_err(&pdev->dev, "HW Init failed\n"); + goto init_failed; + } else { + err = hw_i2c_dma_init(pdev); + if (err) { + dev_err(&pdev->dev, "HW Init failed\n"); + goto init_failed; + } + } + + /* Will catch all error (IRQ mask) */ + __raw_writel(0x0000FF00, mxs_i2c->regbase + HW_I2C_CTRL1_SET); + + adap = &mxs_i2c->adapter; + strncpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_HWMON; + adap->algo = &mxs_i2c_algo; + adap->dev.parent = &pdev->dev; + adap->nr = pdev->id; + i2c_set_adapdata(adap, mxs_i2c); + err = i2c_add_numbered_adapter(adap); + if (err) { + dev_err(&pdev->dev, "Failed to add adapter\n"); + goto no_i2c_adapter; + + } + + INIT_WORK(&mxs_i2c->work, mxs_i2c_task); + + return 0; + +no_i2c_adapter: + __raw_writel(BM_I2C_CTRL0_SFTRST, mxs_i2c->regbase + HW_I2C_CTRL0_SET); + + if (mxs_i2c->flags & MXS_I2C_DMA_MODE) + hw_i2c_dma_uninit(pdev); + else + kfree(mxs_i2c->buf); +init_failed: + free_irq(mxs_i2c->irq_dma, mxs_i2c); +no_dma_irq: + free_irq(mxs_i2c->irq_err, mxs_i2c); +no_err_irq: +nores: + kfree(mxs_i2c); + return err; +} + +static int mxs_i2c_remove(struct platform_device *pdev) +{ + struct mxs_i2c_dev *mxs_i2c = platform_get_drvdata(pdev); + int res; + + res = i2c_del_adapter(&mxs_i2c->adapter); + if (res) + return -EBUSY; + + __raw_writel(BM_I2C_CTRL0_SFTRST, mxs_i2c->regbase + HW_I2C_CTRL0_SET); + + if (mxs_i2c->flags & MXS_I2C_DMA_MODE) + hw_i2c_dma_uninit(pdev); + if (mxs_i2c->flags & MXS_I2C_PIOQUEUE_MODE) + hw_i2c_pioq_stop(mxs_i2c); + + platform_set_drvdata(pdev, NULL); + + free_irq(mxs_i2c->irq_err, mxs_i2c); + free_irq(mxs_i2c->irq_dma, mxs_i2c); + + kfree(mxs_i2c->buf); + kfree(mxs_i2c); + return 0; +} + +static struct platform_driver mxs_i2c_driver = { + .driver = { + .name = "mxs-i2c", + .owner = THIS_MODULE, + }, + .probe = mxs_i2c_probe, + .remove = __devexit_p(mxs_i2c_remove), +}; + +static int __init mxs_i2c_init(void) +{ + return platform_driver_register(&mxs_i2c_driver); +} + +subsys_initcall(mxs_i2c_init); + +static void __exit mxs_i2c_exit(void) +{ + platform_driver_unregister(&mxs_i2c_driver); +} + +module_exit(mxs_i2c_exit); + +MODULE_AUTHOR("Embedded Alley Solutions, Inc/Freescale Inc"); +MODULE_DESCRIPTION("MXS I2C Bus Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/i2c/busses/i2c-mxs.h b/drivers/i2c/busses/i2c-mxs.h new file mode 100644 index 000000000000..1a35385b793b --- /dev/null +++ b/drivers/i2c/busses/i2c-mxs.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _I2C_H +#define _I2C_H + +#define I2C_READ 1 +#define I2C_WRITE 0 + +struct mxs_i2c_dev { + struct device *dev; + void *buf; + unsigned long regbase; + u32 flags; +#define MXS_I2C_DMA_MODE 0x1 +#define MXS_I2C_PIOQUEUE_MODE 0x2 + int dma_chan; + int irq_dma; + int irq_err; + struct completion cmd_complete; + u32 cmd_err; + struct i2c_adapter adapter; + spinlock_t lock; + wait_queue_head_t queue; + struct work_struct work; +}; +#endif diff --git a/drivers/i2c/busses/mxc_i2c.c b/drivers/i2c/busses/mxc_i2c.c new file mode 100644 index 000000000000..b47f9db4b476 --- /dev/null +++ b/drivers/i2c/busses/mxc_i2c.c @@ -0,0 +1,808 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_i2c.c + * + * @brief Driver for the Freescale Semiconductor MXC I2C buses. + * + * Based on i2c driver algorithm for PCF8584 adapters + * + * @ingroup MXCI2C + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_i2c_reg.h" + +/*! + * In case the MXC device has multiple I2C modules, this structure is used to + * store information specific to each I2C module. + */ +typedef struct { + /*! + * This structure is used to identify the physical i2c bus along with + * the access algorithms necessary to access it. + */ + struct i2c_adapter adap; + + /*! + * This waitqueue is used to wait for the data transfer to complete. + */ + wait_queue_head_t wq; + + /*! + * The base address of the I2C device. + */ + void __iomem *membase; + + /*! + * The interrupt number used by the I2C device. + */ + int irq; + + /*! + * The default clock divider value to be used. + */ + unsigned int clkdiv; + + /*! + * The clock source for the device. + */ + struct clk *clk; + + /*! + * The current power state of the device + */ + bool low_power; + + /*! + * Boolean to indicate if data was transferred + */ + bool transfer_done; + + /*! + * Boolean to indicate if we received an ACK for the data transmitted + */ + bool tx_success; +} mxc_i2c_device; + +struct clk_div_table { + int reg_value; + int div; +}; + +static const struct clk_div_table i2c_clk_table[] = { + {0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28}, + {0, 30}, {1, 32}, {0x24, 32}, {2, 36}, + {0x25, 36}, {0x26, 40}, {3, 42}, {0x27, 44}, + {4, 48}, {0x28, 48}, {5, 52}, {0x29, 56}, + {6, 60}, {0x2A, 64}, {7, 72}, {0x2B, 72}, + {8, 80}, {0x2C, 80}, {9, 88}, {0x2D, 96}, + {0xA, 104}, {0x2E, 112}, {0xB, 128}, {0x2F, 128}, + {0xC, 144}, {0xD, 160}, {0x30, 160}, {0xE, 192}, + {0x31, 192}, {0x32, 224}, {0xF, 240}, {0x33, 256}, + {0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384}, + {0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512}, + {0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768}, + {0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024}, + {0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536}, + {0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048}, + {0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840}, + {0, 0} +}; + +extern void gpio_i2c_active(int i2c_num); +extern void gpio_i2c_inactive(int i2c_num); + +/*! + * Transmit a \b STOP signal to the slave device. + * + * @param dev the mxc i2c structure used to get to the right i2c device + */ +static void mxc_i2c_stop(mxc_i2c_device *dev) +{ + unsigned int cr, sr; + int retry = 16; + + cr = readw(dev->membase + MXC_I2CR); + cr &= ~(MXC_I2CR_MSTA | MXC_I2CR_MTX); + writew(cr, dev->membase + MXC_I2CR); + + /* Wait till the Bus Busy bit is reset */ + sr = readw(dev->membase + MXC_I2SR); + while (retry-- && ((sr & MXC_I2SR_IBB))) { + udelay(3); + sr = readw(dev->membase + MXC_I2SR); + } + if (retry <= 0) + dev_err(&dev->adap.dev, "Could not set I2C Bus Busy bit" + " to zero.\n"); +} + +/*! + * Wait for the transmission of the data byte to complete. This function waits + * till we get a signal from the interrupt service routine indicating completion + * of the address cycle or we time out. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param trans_flag transfer flag + * + * + * @return The function returns 0 on success or -1 if an ack was not received + */ + +static int mxc_i2c_wait_for_tc(mxc_i2c_device *dev, int trans_flag) +{ + int retry = 16; + + while (retry-- && !dev->transfer_done) { + wait_event_interruptible_timeout(dev->wq, + dev->transfer_done, + dev->adap.timeout); + } + dev->transfer_done = false; + + if (retry <= 0) { + /* Unable to send data */ + dev_err(&dev->adap.dev, "Data not transmitted\n"); + return -1; + } + + if (!dev->tx_success) { + /* An ACK was not received for transmitted byte */ + dev_err(&dev->adap.dev, "ACK not received \n"); + return -1; + } + + return 0; +} + +/*! + * Transmit a \b START signal to the slave device. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param *msg pointer to a message structure that contains the slave + * address + * + * @return The function returns EBUSY on failure, 0 on success. + */ +static int mxc_i2c_start(mxc_i2c_device *dev, struct i2c_msg *msg) +{ + volatile unsigned int cr, sr; + unsigned int addr_trans; + int retry = 16; + + /* + * Set the slave address and the requested transfer mode + * in the data register + */ + addr_trans = msg->addr << 1; + if (msg->flags & I2C_M_RD) { + addr_trans |= 0x01; + } + + /* Set the Master bit */ + cr = readw(dev->membase + MXC_I2CR); + cr |= MXC_I2CR_MSTA; + writew(cr, dev->membase + MXC_I2CR); + + /* Wait till the Bus Busy bit is set */ + sr = readw(dev->membase + MXC_I2SR); + while (retry-- && (!(sr & MXC_I2SR_IBB))) { + udelay(3); + sr = readw(dev->membase + MXC_I2SR); + } + if (retry <= 0) { + dev_err(&dev->adap.dev, "Could not grab Bus ownership\n"); + return -EBUSY; + } + + /* Set the Transmit bit */ + cr = readw(dev->membase + MXC_I2CR); + cr |= MXC_I2CR_MTX; + writew(cr, dev->membase + MXC_I2CR); + + writew(addr_trans, dev->membase + MXC_I2DR); + return 0; +} + +/*! + * Transmit a \b REPEAT START to the slave device + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param *msg pointer to a message structure that contains the slave + * address + */ +static int mxc_i2c_repstart(mxc_i2c_device *dev, struct i2c_msg *msg) +{ + volatile unsigned int cr, sr; + unsigned int addr_trans; + int retry = 16; + + /* + * Set the slave address and the requested transfer mode + * in the data register + */ + addr_trans = msg->addr << 1; + if (msg->flags & I2C_M_RD) { + addr_trans |= 0x01; + } + cr = readw(dev->membase + MXC_I2CR); + cr |= MXC_I2CR_RSTA; + writew(cr, dev->membase + MXC_I2CR); + /* Wait till the Bus Busy bit is set */ + sr = readw(dev->membase + MXC_I2SR); + while (retry-- && (!(sr & MXC_I2SR_IBB))) { + udelay(3); + sr = readw(dev->membase + MXC_I2SR); + } + if (retry <= 0) { + dev_err(&dev->adap.dev, "Could not grab Bus ownership\n"); + return -EBUSY; + } + writew(addr_trans, dev->membase + MXC_I2DR); + return 0; +} + +/*! + * Read the received data. The function waits till data is available or times + * out. Generates a stop signal if this is the last message to be received. + * Sends an ack for all the bytes received except the last byte. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param *msg pointer to a message structure that contains the slave + * address and a pointer to the receive buffer + * @param last indicates that this is the last message to be received + * @param addr_comp flag indicates that we just finished the address cycle + * + * @return The function returns the number of bytes read or -1 on time out. + */ +static int mxc_i2c_readbytes(mxc_i2c_device *dev, struct i2c_msg *msg, + int last, int addr_comp) +{ + int i; + char *buf = msg->buf; + int len = msg->len; + volatile unsigned int cr; + + cr = readw(dev->membase + MXC_I2CR); + /* + * Clear MTX to switch to receive mode. + */ + cr &= ~MXC_I2CR_MTX; + /* + * Clear the TXAK bit to gen an ack when receiving only one byte. + */ + if (len == 1) { + cr |= MXC_I2CR_TXAK; + } else { + cr &= ~MXC_I2CR_TXAK; + } + writew(cr, dev->membase + MXC_I2CR); + /* + * Dummy read only at the end of an address cycle + */ + if (addr_comp > 0) { + readw(dev->membase + MXC_I2DR); + } + + for (i = 0; i < len; i++) { + /* + * Wait for data transmission to complete + */ + if (mxc_i2c_wait_for_tc(dev, msg->flags)) { + mxc_i2c_stop(dev); + return -1; + } + /* + * Do not generate an ACK for the last byte + */ + if (i == (len - 2)) { + cr = readw(dev->membase + MXC_I2CR); + cr |= MXC_I2CR_TXAK; + writew(cr, dev->membase + MXC_I2CR); + } else if (i == (len - 1)) { + if (last) { + mxc_i2c_stop(dev); + } + } + /* Read the data */ + *buf++ = readw(dev->membase + MXC_I2DR); + } + + return i; +} + +/*! + * Write the data to the data register. Generates a stop signal if this is + * the last message to be sent or if no ack was received for the data sent. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param *msg pointer to a message structure that contains the slave + * address and data to be sent + * @param last indicates that this is the last message to be received + * + * @return The function returns the number of bytes written or -1 on time out + * or if no ack was received for the data that was sent. + */ +static int mxc_i2c_writebytes(mxc_i2c_device *dev, struct i2c_msg *msg, + int last) +{ + int i; + char *buf = msg->buf; + int len = msg->len; + volatile unsigned int cr; + + cr = readw(dev->membase + MXC_I2CR); + /* Set MTX to switch to transmit mode */ + cr |= MXC_I2CR_MTX; + writew(cr, dev->membase + MXC_I2CR); + + for (i = 0; i < len; i++) { + /* + * Write the data + */ + writew(*buf++, dev->membase + MXC_I2DR); + if (mxc_i2c_wait_for_tc(dev, msg->flags)) { + mxc_i2c_stop(dev); + return -1; + } + } + if (last > 0) { + mxc_i2c_stop(dev); + } + + return i; +} + +/*! + * Function enables the I2C module and initializes the registers. + * + * @param dev the mxc i2c structure used to get to the right i2c device + * @param trans_flag transfer flag + */ +static void mxc_i2c_module_en(mxc_i2c_device *dev, int trans_flag) +{ + clk_enable(dev->clk); + /* Set the frequency divider */ + writew(dev->clkdiv, dev->membase + MXC_IFDR); + /* Clear the status register */ + writew(0x0, dev->membase + MXC_I2SR); + /* Enable I2C and its interrupts */ + writew(MXC_I2CR_IEN, dev->membase + MXC_I2CR); + writew(MXC_I2CR_IEN | MXC_I2CR_IIEN, dev->membase + MXC_I2CR); +} + +/*! + * Disables the I2C module. + * + * @param dev the mxc i2c structure used to get to the right i2c device + */ +static void mxc_i2c_module_dis(mxc_i2c_device *dev) +{ + writew(0x0, dev->membase + MXC_I2CR); + clk_disable(dev->clk); +} + +/*! + * The function is registered in the adapter structure. It is called when an MXC + * driver wishes to transfer data to a device connected to the I2C device. + * + * @param adap adapter structure for the MXC i2c device + * @param msgs[] array of messages to be transferred to the device + * @param num number of messages to be transferred to the device + * + * @return The function returns the number of messages transferred, + * \b -EREMOTEIO on I2C failure and a 0 if the num argument is + * less than 0. + */ +static int mxc_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], + int num) +{ + mxc_i2c_device *dev = (mxc_i2c_device *) (i2c_get_adapdata(adap)); + int i, ret = 0, addr_comp = 0; + volatile unsigned int sr; + int retry = 5; + + if (dev->low_power) { + dev_err(&dev->adap.dev, "I2C Device in low power mode\n"); + return -EREMOTEIO; + } + + if (num < 1) { + return 0; + } + + mxc_i2c_module_en(dev, msgs[0].flags); + sr = readw(dev->membase + MXC_I2SR); + /* + * Check bus state + */ + + while ((sr & MXC_I2SR_IBB) && retry--) { + udelay(5); + sr = readw(dev->membase + MXC_I2SR); + } + + if ((sr & MXC_I2SR_IBB) && retry < 0) { + mxc_i2c_module_dis(dev); + dev_err(&dev->adap.dev, "Bus busy\n"); + return -EREMOTEIO; + } + + dev->transfer_done = false; + dev->tx_success = false; + for (i = 0; i < num && ret >= 0; i++) { + addr_comp = 0; + /* + * Send the slave address and transfer direction in the + * address cycle + */ + if (i == 0) { + /* + * Send a start or repeat start signal + */ + if (mxc_i2c_start(dev, &msgs[0])) + return -EREMOTEIO; + /* Wait for the address cycle to complete */ + if (mxc_i2c_wait_for_tc(dev, msgs[0].flags)) { + mxc_i2c_stop(dev); + mxc_i2c_module_dis(dev); + return -EREMOTEIO; + } + addr_comp = 1; + } else { + /* + * Generate repeat start only if required i.e the address + * changed or the transfer direction changed + */ + if ((msgs[i].addr != msgs[i - 1].addr) || + ((msgs[i].flags & I2C_M_RD) != + (msgs[i - 1].flags & I2C_M_RD))) { + mxc_i2c_repstart(dev, &msgs[i]); + /* Wait for the address cycle to complete */ + if (mxc_i2c_wait_for_tc(dev, msgs[i].flags)) { + mxc_i2c_stop(dev); + mxc_i2c_module_dis(dev); + return -EREMOTEIO; + } + addr_comp = 1; + } + } + + /* Transfer the data */ + if (msgs[i].flags & I2C_M_RD) { + /* Read the data */ + ret = mxc_i2c_readbytes(dev, &msgs[i], (i + 1 == num), + addr_comp); + if (ret < 0) { + dev_err(&dev->adap.dev, "mxc_i2c_readbytes:" + " fail.\n"); + break; + } + } else { + /* Write the data */ + ret = mxc_i2c_writebytes(dev, &msgs[i], (i + 1 == num)); + if (ret < 0) { + dev_err(&dev->adap.dev, "mxc_i2c_writebytes:" + " fail.\n"); + break; + } + } + } + + mxc_i2c_module_dis(dev); + /* + * Decrease by 1 as we do not want Start message to be included in + * the count + */ + return (i < 0 ? ret : i); +} + +/*! + * Returns the i2c functionality supported by this driver. + * + * @param adap adapter structure for this i2c device + * + * @return Returns the functionality that is supported. + */ +static u32 mxc_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +/*! + * Stores the pointers for the i2c algorithm functions. The algorithm functions + * is used by the i2c bus driver to talk to the i2c bus + */ +static struct i2c_algorithm mxc_i2c_algorithm = { + .master_xfer = mxc_i2c_xfer, + .functionality = mxc_i2c_func +}; + +/*! + * Interrupt Service Routine. It signals to the process about the data transfer + * completion. Also sets a flag if bus arbitration is lost. + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_HANDLED. + */ +static irqreturn_t mxc_i2c_handler(int irq, void *dev_id) +{ + mxc_i2c_device *dev = dev_id; + volatile unsigned int sr, cr; + + sr = readw(dev->membase + MXC_I2SR); + cr = readw(dev->membase + MXC_I2CR); + + /* + * Clear the interrupt bit + */ + writew(0x0, dev->membase + MXC_I2SR); + + if (sr & MXC_I2SR_IAL) { + dev_err(&dev->adap.dev, "Bus Arbitration lost\n"); + } else { + /* Interrupt due byte transfer completion */ + dev->tx_success = true; + /* Check if RXAK is received in Transmit mode */ + if ((cr & MXC_I2CR_MTX) && (sr & MXC_I2SR_RXAK)) { + dev->tx_success = false; + } + dev->transfer_done = true; + wake_up_interruptible(&dev->wq); + } + + return IRQ_HANDLED; +} + +/*! + * This function is called to put the I2C adapter in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which I2C + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure. + */ +static int mxci2c_suspend_noirq(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + mxc_i2c_device *mxcdev = platform_get_drvdata(pdev); + volatile unsigned int sr = 0; + + if (mxcdev == NULL) { + return -1; + } + + /* Prevent further calls to be processed */ + mxcdev->low_power = true; + /* Wait till we finish the current transfer */ + sr = readw(mxcdev->membase + MXC_I2SR); + while (sr & MXC_I2SR_IBB) { + msleep(10); + sr = readw(mxcdev->membase + MXC_I2SR); + } + gpio_i2c_inactive(mxcdev->adap.id); + + return 0; +} + +/*! + * This function is called to bring the I2C adapter back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which I2C + * to resume + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxci2c_resume_noirq(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + mxc_i2c_device *mxcdev = platform_get_drvdata(pdev); + + if (mxcdev == NULL) + return -1; + + mxcdev->low_power = false; + gpio_i2c_active(mxcdev->adap.id); + + return 0; +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function always returns 0. + */ +static int mxci2c_probe(struct platform_device *pdev) +{ + mxc_i2c_device *mxc_i2c; + struct mxc_i2c_platform_data *i2c_plat_data = pdev->dev.platform_data; + struct resource *res; + int id = pdev->id; + u32 clk_freq; + int ret = 0; + int i; + + mxc_i2c = kzalloc(sizeof(mxc_i2c_device), GFP_KERNEL); + if (!mxc_i2c) { + return -ENOMEM; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + mxc_i2c->membase = ioremap(res->start, res->end - res->start + 1); + + /* + * Request the I2C interrupt + */ + mxc_i2c->irq = platform_get_irq(pdev, 0); + if (mxc_i2c->irq < 0) { + ret = mxc_i2c->irq; + goto err2; + } + + ret = request_irq(mxc_i2c->irq, mxc_i2c_handler, + 0, pdev->name, mxc_i2c); + if (ret < 0) { + goto err2; + } + + init_waitqueue_head(&mxc_i2c->wq); + + mxc_i2c->low_power = false; + + gpio_i2c_active(id); + + mxc_i2c->clk = clk_get(&pdev->dev, "i2c_clk"); + clk_freq = clk_get_rate(mxc_i2c->clk); + mxc_i2c->clkdiv = -1; + if (i2c_plat_data->i2c_clk) { + /* Calculate divider and round up any fractional part */ + int div = (clk_freq + i2c_plat_data->i2c_clk - 1) / + i2c_plat_data->i2c_clk; + for (i = 0; i2c_clk_table[i].div != 0; i++) { + if (i2c_clk_table[i].div >= div) { + mxc_i2c->clkdiv = i2c_clk_table[i].reg_value; + break; + } + } + } + if (mxc_i2c->clkdiv == -1) { + i--; + mxc_i2c->clkdiv = 0x1F; /* Use max divider */ + } + dev_dbg(&pdev->dev, "i2c speed is %d/%d = %d bps, reg val = 0x%02X\n", + clk_freq, i2c_clk_table[i].div, + clk_freq / i2c_clk_table[i].div, mxc_i2c->clkdiv); + + /* + * Set the adapter information + */ + strlcpy(mxc_i2c->adap.name, pdev->name, 48); + mxc_i2c->adap.id = mxc_i2c->adap.nr = id; + mxc_i2c->adap.algo = &mxc_i2c_algorithm; + mxc_i2c->adap.timeout = 1; + platform_set_drvdata(pdev, mxc_i2c); + i2c_set_adapdata(&mxc_i2c->adap, mxc_i2c); + ret = i2c_add_numbered_adapter(&mxc_i2c->adap); + if (ret < 0) + goto err3; + + printk(KERN_INFO "MXC I2C driver\n"); + return 0; + + err3: + free_irq(mxc_i2c->irq, mxc_i2c); + gpio_i2c_inactive(id); + err2: + iounmap(mxc_i2c->membase); + err1: + dev_err(&pdev->dev, "failed to probe i2c adapter\n"); + kfree(mxc_i2c); + return ret; +} + +/*! + * Dissociates the driver from the I2C device. + * + * @param pdev the device structure used to give information on which I2C + * to remove + * + * @return The function always returns 0. + */ +static int mxci2c_remove(struct platform_device *pdev) +{ + mxc_i2c_device *mxc_i2c = platform_get_drvdata(pdev); + int id = pdev->id; + + free_irq(mxc_i2c->irq, mxc_i2c); + i2c_del_adapter(&mxc_i2c->adap); + gpio_i2c_inactive(id); + clk_put(mxc_i2c->clk); + platform_set_drvdata(pdev, NULL); + iounmap(mxc_i2c->membase); + kfree(mxc_i2c); + return 0; +} + +static struct dev_pm_ops mxci2c_dev_pm_ops = { + .suspend_noirq = mxci2c_suspend_noirq, + .resume_noirq = mxci2c_resume_noirq, +}; + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxci2c_driver = { + .driver = { + .name = "mxc_i2c", + .owner = THIS_MODULE, + .pm = &mxci2c_dev_pm_ops, + }, + .probe = mxci2c_probe, + .remove = mxci2c_remove, +}; + +/*! + * Function requests the interrupts and registers the i2c adapter structures. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxc_i2c_init(void) +{ + /* Register the device driver structure. */ + return platform_driver_register(&mxci2c_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxc_i2c_exit(void) +{ + platform_driver_unregister(&mxci2c_driver); +} + +subsys_initcall(mxc_i2c_init); +module_exit(mxc_i2c_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC I2C driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/i2c/busses/mxc_i2c_hs.c b/drivers/i2c/busses/mxc_i2c_hs.c new file mode 100644 index 000000000000..60262741cd54 --- /dev/null +++ b/drivers/i2c/busses/mxc_i2c_hs.c @@ -0,0 +1,553 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_i2c_hs_reg.h" + +typedef struct { + struct device *dev; + + void __iomem *reg_base_virt; + unsigned long reg_base_phy; + int irq; + unsigned int speed; + struct clk *ipg_clk; + struct clk *serial_clk; + bool low_power; + + struct i2c_msg *msg; + int index; +} mxc_i2c_hs; + +struct clk_div_table { + int reg_value; + int div; +}; + +static const struct clk_div_table i2c_clk_table[] = { + {0x0, 16}, {0x1, 18}, {0x2, 20}, {0x3, 22}, + {0x20, 24}, {0x21, 26}, {0x22, 28}, {0x23, 30}, + {0x4, 32}, {0x5, 36}, {0x6, 40}, {0x7, 44}, + {0x24, 48}, {0x25, 52}, {0x26, 56}, {0x27, 60}, + {0x8, 64}, {0x9, 72}, {0xa, 80}, {0xb, 88}, + {0x28, 96}, {0x29, 104}, {0x2a, 112}, {0x2b, 120}, + {0xc, 128}, {0xd, 144}, {0xe, 160}, {0xf, 176}, + {0x2c, 192}, {0x2d, 208}, {0x2e, 224}, {0x2f, 240}, + {0x10, 256}, {0x11, 288}, {0x12, 320}, {0x13, 352}, + {0x30, 384}, {0x31, 416}, {0x32, 448}, {0x33, 480}, + {0x14, 512}, {0x15, 576}, {0x16, 640}, {0x17, 704}, + {0x34, 768}, {0x35, 832}, {0x36, 896}, {0x37, 960}, + {0x18, 1024}, {0x19, 1152}, {0x1a, 1280}, {0x1b, 1408}, + {0x38, 1536}, {0x39, 1664}, {0x3a, 1792}, {0x3b, 1920}, + {0x1c, 2048}, {0x1d, 2304}, {0x1e, 2560}, {0x1f, 2816}, + {0x3c, 3072}, {0x3d, 3328}, {0x3E, 3584}, {0x3F, 3840}, + {-1, -1} +}; + +static struct i2c_adapter *adap; + +extern void gpio_i2c_hs_inactive(void); +extern void gpio_i2c_hs_active(void); + +static u16 reg_read(mxc_i2c_hs *i2c_hs, u32 reg_offset) +{ + return __raw_readw(i2c_hs->reg_base_virt + reg_offset); +} + +static void reg_write(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 data) +{ + __raw_writew(data, i2c_hs->reg_base_virt + reg_offset); +} + +static void reg_set_mask(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 mask) +{ + u16 value; + + value = reg_read(i2c_hs, reg_offset); + value |= mask; + reg_write(i2c_hs, reg_offset, value); +} +static void reg_clear_mask(mxc_i2c_hs *i2c_hs, u32 reg_offset, u16 mask) +{ + u16 value; + + value = reg_read(i2c_hs, reg_offset); + value &= ~mask; + reg_write(i2c_hs, reg_offset, value); +} + +static void mxci2c_hs_set_div(mxc_i2c_hs *i2c_hs) +{ + unsigned long clk_freq; + int i; + int div = -1;; + + clk_freq = clk_get_rate(i2c_hs->serial_clk); + if (i2c_hs->speed) { + div = (clk_freq + i2c_hs->speed - 1) / i2c_hs->speed; + for (i = 0; i2c_clk_table[i].div >= 0; i++) { + if (i2c_clk_table[i].div >= div) { + div = i2c_clk_table[i].reg_value; + reg_write(i2c_hs, HIFSFDR, div); + break; + } + } + } +} + +static int mxci2c_hs_enable(mxc_i2c_hs *i2c_hs) +{ + gpio_i2c_hs_active(); + clk_enable(i2c_hs->ipg_clk); + clk_enable(i2c_hs->serial_clk); + mxci2c_hs_set_div(i2c_hs); + reg_write(i2c_hs, HICR, reg_read(i2c_hs, HICR) | HICR_HIEN); + + return 0; +} + +static int mxci2c_hs_disable(mxc_i2c_hs *i2c_hs) +{ + reg_write(i2c_hs, HICR, reg_read(i2c_hs, HICR) & (~HICR_HIEN)); + clk_disable(i2c_hs->ipg_clk); + clk_disable(i2c_hs->serial_clk); + + return 0; +} + +static int mxci2c_hs_bus_busy(mxc_i2c_hs *i2c_hs) +{ + u16 value; + int retry = 1000; + + while (retry--) { + value = reg_read(i2c_hs, HISR); + if (value & HISR_HIBB) { + udelay(1); + } else { + break; + } + } + + if (retry <= 0) { + dev_dbg(NULL, "%s: Bus Busy!\n", __func__); + return 1; + } else { + return 0; + } +} + +static int mxci2c_hs_start(mxc_i2c_hs *i2c_hs, int repeat_start, u16 address) +{ + u16 mask; + int ret = 0; + + mxci2c_hs_bus_busy(i2c_hs); + + /*7 bit address */ + reg_clear_mask(i2c_hs, HICR, HICR_ADDR_MODE); + + /*send start */ + if (repeat_start) + mask = HICR_RSTA; + else + mask = HICR_MSTA; + reg_set_mask(i2c_hs, HICR, mask); + + return ret; +} + +static int mxci2c_hs_stop(mxc_i2c_hs *i2c_hs) +{ + reg_clear_mask(i2c_hs, HICR, HICR_MSTA); + reg_clear_mask(i2c_hs, HICR, HICR_HIIEN); + + return 0; +} + +static int mxci2c_wait_writefifo(mxc_i2c_hs *i2c_hs) +{ + int i, num, left; + int retry, ret = 0; + + retry = 10000; + while (retry--) { + udelay(10); + if (reg_read(i2c_hs, HISR) & (HISR_TDE | HISR_TDC_ZERO)) { + if (i2c_hs->index < i2c_hs->msg->len) { + left = i2c_hs->msg->len - i2c_hs->index; + num = + (left > + HITFR_MAX_COUNT) ? HITFR_MAX_COUNT : left; + for (i = 0; i < num; i++) { + reg_write(i2c_hs, HITDR, + i2c_hs->msg->buf[i2c_hs-> + index + i]); + } + i2c_hs->index += num; + } else { + if (reg_read(i2c_hs, HISR) & HISR_TDC_ZERO) { + msleep(1); + break; + } + } + } + } + + if (retry <= 0) { + printk(KERN_ERR "%s:wait error\n", __func__); + ret = -1; + } + + return ret; +} + +static int mxci2c_wait_readfifo(mxc_i2c_hs *i2c_hs) +{ + int i, num, left; + int retry, ret = 0; + u16 value; + + retry = 10000; + while (retry--) { + udelay(10); + value = reg_read(i2c_hs, HISR); + if (value & (HISR_RDF | HISR_RDC_ZERO)) { + if (i2c_hs->index < i2c_hs->msg->len) { + left = i2c_hs->msg->len - i2c_hs->index; + num = + (left > + HITFR_MAX_COUNT) ? HITFR_MAX_COUNT : left; + for (i = 0; i < num; i++) { + i2c_hs->msg->buf[i2c_hs->index + i] = + reg_read(i2c_hs, HIRDR); + } + i2c_hs->index += num; + } else { + if (value & HISR_RDC_ZERO) { + break; + } + } + } + } + + if (retry <= 0) { + printk(KERN_ERR "%s:wait error\n", __func__); + ret = -1; + } + + return ret; +} + +static int mxci2c_hs_read(mxc_i2c_hs *i2c_hs, int repeat_start, + struct i2c_msg *msg) +{ + int ret; + + if (msg->len > HIRDCR_MAX_COUNT) { + printk(KERN_ERR "%s: error: msg too long, max longth 256\n", + __func__); + return -1; + } + + ret = 0; + i2c_hs->msg = msg; + i2c_hs->index = 0; + + /*set address */ + reg_write(i2c_hs, HIMADR, HIMADR_LSB_ADR(msg->addr)); + + /*receive mode */ + reg_clear_mask(i2c_hs, HICR, HICR_MTX); + + reg_clear_mask(i2c_hs, HICR, HICR_HIIEN); + + /*FIFO*/ reg_set_mask(i2c_hs, HIRFR, HIRFR_RFEN | HIRFR_RFWM(7)); + reg_set_mask(i2c_hs, HIRFR, HIRFR_RFLSH); + + /*TDCR*/ + reg_write(i2c_hs, HIRDCR, HIRDCR_RDC_EN | HIRDCR_RDC(msg->len)); + + mxci2c_hs_start(i2c_hs, repeat_start, msg->addr); + + ret = mxci2c_wait_readfifo(i2c_hs); + + if (ret < 0) + return ret; + else + return msg->len; +} + +static int mxci2c_hs_write(mxc_i2c_hs *i2c_hs, int repeat_start, + struct i2c_msg *msg) +{ + int ret, i; + + if (msg->len > HITDCR_MAX_COUNT) { + printk(KERN_ERR "%s: error: msg too long, max longth 256\n", + __func__); + return -1; + } + + ret = 0; + i2c_hs->msg = msg; + i2c_hs->index = 0; + + /*set address */ + reg_write(i2c_hs, HIMADR, HIMADR_LSB_ADR(msg->addr)); + + /*transmit mode */ + reg_set_mask(i2c_hs, HICR, HICR_MTX); + + reg_clear_mask(i2c_hs, HICR, HICR_HIIEN); + + /* TDCR */ + reg_write(i2c_hs, HITDCR, HITDCR_TDC_EN | HITDCR_TDC(msg->len)); + + /* FIFO */ + reg_set_mask(i2c_hs, HITFR, HITFR_TFEN); + reg_set_mask(i2c_hs, HITFR, HITFR_TFLSH); + + if (msg->len > HITFR_MAX_COUNT) + i2c_hs->index = HITFR_MAX_COUNT; + else { + i2c_hs->index = msg->len; + } + + for (i = 0; i < i2c_hs->index; i++) { + reg_write(i2c_hs, HITDR, msg->buf[i]); + } + + mxci2c_hs_start(i2c_hs, repeat_start, msg->addr); + + ret = mxci2c_wait_writefifo(i2c_hs); + + if (ret < 0) + return ret; + else + return msg->len; +} + +static int mxci2c_hs_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], + int num) +{ + int i; + int ret = -EIO; + + mxc_i2c_hs *i2c_hs = (mxc_i2c_hs *) (i2c_get_adapdata(adap)); + + if (i2c_hs->low_power) { + dev_err(&adap->dev, "I2C Device in low power mode\n"); + return -EREMOTEIO; + } + + if (num < 1) { + return 0; + } + + mxci2c_hs_enable(i2c_hs); + + for (i = 0; i < num; i++) { + if (msgs[i].flags & I2C_M_RD) { + ret = mxci2c_hs_read(i2c_hs, 0, &msgs[i]); + if (ret < 0) + break; + } else { + ret = mxci2c_hs_write(i2c_hs, 0, &msgs[i]); + if (ret < 0) + break; + } + mxci2c_hs_stop(i2c_hs); + } + mxci2c_hs_stop(i2c_hs); + + mxci2c_hs_disable(i2c_hs); + + if (ret < 0) + return ret; + + return i; +} + +static u32 mxci2c_hs_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +/*! + * Stores the pointers for the i2c algorithm functions. The algorithm functions + * is used by the i2c bus driver to talk to the i2c bus + */ +static struct i2c_algorithm mxci2c_hs_algorithm = { + .master_xfer = mxci2c_hs_xfer, + .functionality = mxci2c_hs_func +}; + +static int mxci2c_hs_probe(struct platform_device *pdev) +{ + mxc_i2c_hs *i2c_hs; + struct mxc_i2c_platform_data *i2c_plat_data = pdev->dev.platform_data; + struct resource *res; + int id = pdev->id; + int ret = 0; + + i2c_hs = kzalloc(sizeof(mxc_i2c_hs), GFP_KERNEL); + if (!i2c_hs) { + return -ENOMEM; + } + + i2c_hs->dev = &pdev->dev; + + i2c_hs->speed = i2c_plat_data->i2c_clk; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + i2c_hs->reg_base_virt = ioremap(res->start, res->end - res->start + 1); + i2c_hs->reg_base_phy = res->start; + + i2c_hs->ipg_clk = clk_get(&pdev->dev, "hsi2c_clk"); + i2c_hs->serial_clk = clk_get(&pdev->dev, "hsi2c_serial_clk"); + + /* + * Request the I2C interrupt + */ + i2c_hs->irq = platform_get_irq(pdev, 0); + if (i2c_hs->irq < 0) { + ret = i2c_hs->irq; + goto err1; + } + + i2c_hs->low_power = false; + + /* + * Set the adapter information + */ + adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL); + if (!adap) { + ret = -ENODEV; + goto err1; + } + strlcpy(adap->name, pdev->name, 48); + adap->id = adap->nr = id; + adap->algo = &mxci2c_hs_algorithm; + adap->timeout = 1; + platform_set_drvdata(pdev, i2c_hs); + i2c_set_adapdata(adap, i2c_hs); + ret = i2c_add_numbered_adapter(adap); + if (ret < 0) { + goto err2; + } + + printk(KERN_INFO "MXC HS I2C driver\n"); + return 0; + + err2: + kfree(adap); + err1: + dev_err(&pdev->dev, "failed to probe high speed i2c adapter\n"); + iounmap(i2c_hs->reg_base_virt); + kfree(i2c_hs); + return ret; +} + +static int mxci2c_hs_suspend(struct platform_device *pdev, pm_message_t state) +{ + mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev); + + if (i2c_hs == NULL) { + return -1; + } + + /* Prevent further calls to be processed */ + i2c_hs->low_power = true; + + gpio_i2c_hs_inactive(); + + return 0; +} + +static int mxci2c_hs_resume(struct platform_device *pdev) +{ + mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev); + + if (i2c_hs == NULL) + return -1; + + i2c_hs->low_power = false; + gpio_i2c_hs_active(); + + return 0; +} + +static int mxci2c_hs_remove(struct platform_device *pdev) +{ + mxc_i2c_hs *i2c_hs = platform_get_drvdata(pdev); + + i2c_del_adapter(adap); + gpio_i2c_hs_inactive(); + platform_set_drvdata(pdev, NULL); + iounmap(i2c_hs->reg_base_virt); + kfree(i2c_hs); + return 0; +} + +static struct platform_driver mxci2c_hs_driver = { + .driver = { + .name = "mxc_i2c_hs", + .owner = THIS_MODULE, + }, + .probe = mxci2c_hs_probe, + .remove = mxci2c_hs_remove, + .suspend = mxci2c_hs_suspend, + .resume = mxci2c_hs_resume, +}; + +/*! + * Function requests the interrupts and registers the i2c adapter structures. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxci2c_hs_init(void) +{ + /* Register the device driver structure. */ + return platform_driver_register(&mxci2c_hs_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxci2c_hs_exit(void) +{ + platform_driver_unregister(&mxci2c_hs_driver); +} + +subsys_initcall(mxci2c_hs_init); +module_exit(mxci2c_hs_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC HIGH SPEED I2C driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/i2c/busses/mxc_i2c_hs_reg.h b/drivers/i2c/busses/mxc_i2c_hs_reg.h new file mode 100644 index 000000000000..5a017cb17765 --- /dev/null +++ b/drivers/i2c/busses/mxc_i2c_hs_reg.h @@ -0,0 +1,97 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_I2C_HS_REG_H__ +#define __MXC_I2C_HS_REG_H__ + +#define HISADR 0x00 + +#define HIMADR 0x04 +#define HIMADR_LSB_ADR(x) ((x) << 1) +#define HIMADR_MSB_ADR(x) (((x) & 0x7) << 8) + +#define HICR 0x08 +#define HICR_HIEN 0x1 +#define HICR_DMA_EN_RX 0x2 +#define HICR_DMA_EN_TR 0x4 +#define HICR_RSTA 0x8 +#define HICR_TXAK 0x10 +#define HICR_MTX 0x20 +#define HICR_MSTA 0x40 +#define HICR_HIIEN 0x80 +#define HICR_ADDR_MODE 0x100 +#define HICR_MST_CODE(x) (((x)&0x7) << 9) +#define HICR_HSM_EN 0x1000 +#define HICR_SAMC(x) (((x)&0x3) << 13) +#define SAMC_7_10 0 +#define SMAC_7 1 +#define SMAC_10 2 + +#define HISR 0x0c +#define HISR_RDF 0x1 +#define HISR_TDE 0x2 +#define HISR_HIAAS 0x4 +#define HISR_HIAL 0x8 +#define HISR_BTD 0x10 +#define HISR_RDC_ZERO 0x20 +#define HISR_TDC_ZERO 0x40 +#define HISR_RXAK 0x80 +#define HISR_HIBB 0x100 +#define HISR_SRW 0x200 +#define HISR_SADDR_MODE 0x400 +#define HISR_SHS_MODE 0x800 + +#define HIIMR 0x10 +#define HIIMR_RDF 0x1 +#define HIIMR_TDE 0x2 +#define HIIMR_AAS 0x4 +#define HIIMR_AL 0x8 +#define HIIMR_BTD 0x10 +#define HIIMR_RDC 0x20 +#define HIIMR_TDC 0x40 +#define HIIMR_RXAK 0x80 + +#define HITDR 0x14 + +#define HIRDR 0x18 + +#define HIFSFDR 0x1c + +#define HIHSFDR 0x20 + +#define HITFR 0x24 +#define HITFR_TFEN 0x1 +#define HITFR_TFLSH 0x2 +#define HITFR_TFWM(x) (((x) & 0x7) << 2) +#define HITFR_TFC(x) (((x) >> 8) & 0xF) +#define HITFR_MAX_COUNT 8 + +#define HIRFR 0x28 +#define HIRFR_RFEN 0x1 +#define HIRFR_RFLSH 0x2 +#define HIRFR_RFWM(x) (((x) & 0x7) << 2) +#define HIRFR_RFC(x) (((x) >> 8) & 0xF) +#define HIRFR_MAX_COUNT 8 + +#define HITDCR 0x2c +#define HITDCR_TDC(x) ((x) & 0xFF) +#define HITDCR_TDC_EN 0x100 +#define HITDCR_TDC_RSTA 0x200 +#define HITDCR_MAX_COUNT 0xFF + +#define HIRDCR 0x30 +#define HIRDCR_RDC(x) ((x) & 0xFF) +#define HIRDCR_RDC_EN 0x100 +#define HIRDCR_RDC_RSTA 0x200 +#define HIRDCR_MAX_COUNT 0xFF + +#endif diff --git a/drivers/i2c/busses/mxc_i2c_reg.h b/drivers/i2c/busses/mxc_i2c_reg.h new file mode 100644 index 000000000000..2f81036c6626 --- /dev/null +++ b/drivers/i2c/busses/mxc_i2c_reg.h @@ -0,0 +1,40 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_I2C_REG_H__ +#define __MXC_I2C_REG_H__ + +/* Address offsets of the I2C registers */ +#define MXC_IADR 0x00 /* Address Register */ +#define MXC_IFDR 0x04 /* Freq div register */ +#define MXC_I2CR 0x08 /* Control regsiter */ +#define MXC_I2SR 0x0C /* Status register */ +#define MXC_I2DR 0x10 /* Data I/O register */ + +/* Bit definitions of I2CR */ +#define MXC_I2CR_IEN 0x0080 +#define MXC_I2CR_IIEN 0x0040 +#define MXC_I2CR_MSTA 0x0020 +#define MXC_I2CR_MTX 0x0010 +#define MXC_I2CR_TXAK 0x0008 +#define MXC_I2CR_RSTA 0x0004 + +/* Bit definitions of I2SR */ +#define MXC_I2SR_ICF 0x0080 +#define MXC_I2SR_IAAS 0x0040 +#define MXC_I2SR_IBB 0x0020 +#define MXC_I2SR_IAL 0x0010 +#define MXC_I2SR_SRW 0x0004 +#define MXC_I2SR_IIF 0x0002 +#define MXC_I2SR_RXAK 0x0001 + +#endif /* __MXC_I2C_REG_H__ */ diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c index 2ee6c7a68bdc..bef498c538f1 100644 --- a/drivers/input/evdev.c +++ b/drivers/input/evdev.c @@ -72,8 +72,12 @@ static void evdev_event(struct input_handle *handle, struct evdev *evdev = handle->private; struct evdev_client *client; struct input_event event; + struct timespec ts; + + ktime_get_ts(&ts); + event.time.tv_sec = ts.tv_sec; + event.time.tv_usec = ts.tv_nsec / NSEC_PER_USEC; - do_gettimeofday(&event.time); event.type = type; event.code = code; event.value = value; diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig index 1ba25145b333..c58bb7a49e7f 100644 --- a/drivers/input/keyboard/Kconfig +++ b/drivers/input/keyboard/Kconfig @@ -426,4 +426,41 @@ config KEYBOARD_W90P910 To compile this driver as a module, choose M here: the module will be called w90p910_keypad. +config KEYBOARD_MXC + tristate "MXC Keypad Driver" + depends on ARCH_MXC + help + This is the Keypad driver for the Freescale MXC application + processors. + +config KEYBOARD_MXS + tristate "MXS keyboard" + depends on ARCH_MXS + help + This is the Keypad driver for the Freescale mxs soc + + +config KEYBOARD_MC9S08DZ60 + tristate "mc9s08dz60 keyboard" + depends on MXC_PMIC_MC9S08DZ60 + help + -to be written- + +config KEYBOARD_MPR084 + tristate "Freescale MPR084 Touch Keypad Driver" + depends on ARCH_MX37 + help + This is the Keypad driver for the Freescale Proximity Capacitive + Touch Sensor controller chip. + +config KEYBOARD_MPR121 + tristate "Freescale MPR121 Touch Keypad Driver" + depends on I2C + help + Say Y here if you have the touchkey Freescale Proximity Capacitive + Touch Sensor controller chip in your system. + + If unsure, say N. + + To compile this driver as a module, choose M here endif diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile index 4596d0c6f922..e3344b875d81 100644 --- a/drivers/input/keyboard/Makefile +++ b/drivers/input/keyboard/Makefile @@ -38,3 +38,9 @@ obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o obj-$(CONFIG_KEYBOARD_W90P910) += w90p910_keypad.o +obj-$(CONFIG_KEYBOARD_MXC) += mxc_keyb.o +obj-$(CONFIG_KEYBOARD_MXC) += mxc_pwrkey.o +obj-$(CONFIG_KEYBOARD_MPR084) += mpr084.o +obj-$(CONFIG_KEYBOARD_MXS) += mxs-kbd.o +obj-$(CONFIG_KEYBOARD_MC9S08DZ60) += mc9s08dz60_keyb.o +obj-$(CONFIG_KEYBOARD_MPR121) += mpr121.o diff --git a/drivers/input/keyboard/mc9s08dz60_keyb.c b/drivers/input/keyboard/mc9s08dz60_keyb.c new file mode 100644 index 000000000000..87ab5d3eda0a --- /dev/null +++ b/drivers/input/keyboard/mc9s08dz60_keyb.c @@ -0,0 +1,248 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc9s08dz60keyb.c + * + * @brief Driver for the Freescale Semiconductor MXC keypad port. + * + * The keypad driver is designed as a standard Input driver which interacts + * with low level keypad port hardware. Upon opening, the Keypad driver + * initializes the keypad port. When the keypad interrupt happens the driver + * calles keypad polling timer and scans the keypad matrix for key + * press/release. If all key press/release happened it comes out of timer and + * waits for key press interrupt. The scancode for key press and release events + * are passed to Input subsytem. + * + * @ingroup keypad + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MOD_NAME "mc9s08dz60-keyb" +/* + * Module header file + */ + +/*! Input device structure. */ +static struct input_dev *mc9s08dz60kbd_dev; +static unsigned int key_status; +static int keypad_irq; +static unsigned int key_code_map[8] = { + KEY_LEFT, + KEY_DOWN, + 0, + 0, + KEY_UP, + KEY_RIGHT, + 0, + 0, +}; +static unsigned int keycodes_size = 8; + +static void read_key_handler(struct work_struct *work); +static DECLARE_WORK(key_pad_event, read_key_handler); + + +static void read_key_handler(struct work_struct *work) +{ + unsigned int val1, val2; + int pre_val, curr_val, i; + val1 = val2 = 0xff; + mcu_pmic_read_reg(REG_MCU_KPD_1, &val1, 0xff); + mcu_pmic_read_reg(REG_MCU_KPD_2, &val2, 0xff); + pr_debug("key pressed, 0x%02x%02x\n", val2, val1); + for (i = 0; i < 8; i++) { + curr_val = (val1 >> i) & 0x1; + if (curr_val > 0) + input_event(mc9s08dz60kbd_dev, EV_KEY, + key_code_map[i], 1); + else { + pre_val = (key_status >> i) & 0x1; + if (pre_val > 0) + input_event(mc9s08dz60kbd_dev, EV_KEY, + key_code_map[i], 0); + } + } + key_status = val1; + +} + +static irqreturn_t mc9s08dz60kpp_interrupt(int irq, void *dev_id) +{ + schedule_work(&key_pad_event); + return IRQ_RETVAL(1); +} + +/*! + * This function is called when the keypad driver is opened. + * Since keypad initialization is done in __init, nothing is done in open. + * + * @param dev Pointer to device inode + * + * @result The function always return 0 + */ +static int mc9s08dz60kpp_open(struct input_dev *dev) +{ + return 0; +} + +/*! + * This function is called close the keypad device. + * Nothing is done in this function, since every thing is taken care in + * __exit function. + * + * @param dev Pointer to device inode + * + */ +static void mc9s08dz60kpp_close(struct input_dev *dev) +{ +} + + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration. Otherwise returns + * specific error code. + */ +static int mc9s08dz60kpp_probe(struct platform_device *pdev) +{ + int i, irq; + int retval; + + retval = mcu_pmic_write_reg(REG_MCU_KPD_CONTROL, 0x1, 0x1); + if (retval != 0) { + pr_info("mc9s08dz60 keypad: mcu not detected!\n"); + return retval; + } + + irq = platform_get_irq(pdev, 0); + retval = request_irq(irq, mc9s08dz60kpp_interrupt, + 0, MOD_NAME, MOD_NAME); + if (retval) { + pr_debug("KPP: request_irq(%d) returned error %d\n", + irq, retval); + return retval; + } + keypad_irq = irq; + + mc9s08dz60kbd_dev = input_allocate_device(); + if (!mc9s08dz60kbd_dev) { + pr_info(KERN_ERR "mc9s08dz60kbd_dev: \ + not enough memory for input device\n"); + retval = -ENOMEM; + goto err1; + } + + mc9s08dz60kbd_dev->name = "mc9s08dz60kpd"; + mc9s08dz60kbd_dev->id.bustype = BUS_HOST; + mc9s08dz60kbd_dev->open = mc9s08dz60kpp_open; + mc9s08dz60kbd_dev->close = mc9s08dz60kpp_close; + + retval = input_register_device(mc9s08dz60kbd_dev); + if (retval < 0) { + pr_info(KERN_ERR + "mc9s08dz60kbd_dev: failed to register input device\n"); + goto err2; + } + + __set_bit(EV_KEY, mc9s08dz60kbd_dev->evbit); + + for (i = 0; i < keycodes_size; i++) + __set_bit(key_code_map[i], mc9s08dz60kbd_dev->keybit); + + device_init_wakeup(&pdev->dev, 1); + + pr_info("mc9s08dz60 keypad probed\n"); + + return 0; + +err2: + input_free_device(mc9s08dz60kbd_dev); +err1: + free_irq(irq, MOD_NAME); + return retval; +} + +/*! + * Dissociates the driver from the kpp device. + * + * @param pdev the device structure used to give information on which SDHC + * to remove + * + * @return The function always returns 0. + */ +static int mc9s08dz60kpp_remove(struct platform_device *pdev) +{ + free_irq(keypad_irq, MOD_NAME); + input_unregister_device(mc9s08dz60kbd_dev); + + if (mc9s08dz60kbd_dev) + input_free_device(mc9s08dz60kbd_dev); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mc9s08dz60kpd_driver = { + .driver = { + .name = "mc9s08dz60keypad", + .bus = &platform_bus_type, + }, + .probe = mc9s08dz60kpp_probe, + .remove = mc9s08dz60kpp_remove +}; + +static int __init mc9s08dz60kpp_init(void) +{ + pr_info(KERN_INFO "mc9s08dz60 keypad loaded\n"); + platform_driver_register(&mc9s08dz60kpd_driver); + return 0; +} + +static void __exit mc9s08dz60kpp_cleanup(void) +{ + platform_driver_unregister(&mc9s08dz60kpd_driver); +} + +module_init(mc9s08dz60kpp_init); +module_exit(mc9s08dz60kpp_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Keypad Controller Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/keyboard/mpr084.c b/drivers/input/keyboard/mpr084.c new file mode 100644 index 000000000000..d0d5a9fb0809 --- /dev/null +++ b/drivers/input/keyboard/mpr084.c @@ -0,0 +1,500 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file linux/drivers/input/keyboard/mpr084.c + * + * @brief Driver for the Freescale MPR084 I2C Touch Sensor KeyPad module. + * + * + * + * @ingroup Keypad + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Definitions + */ +#define DEBUG 0 + +#define KEY_COUNT 8 + +/* + *Registers in MPR084 + */ +#define MPR084_FIFO_ADDR 0x00 +#define MPR084_FAULT_ADDR 0x01 +#define MPR084_TPS_ADDR 0x02 +#define MPR084_TPC_ADDR 0x03 +#define MPR084_STR1_ADDR 0x04 +#define MPR084_STR2_ADDR 0x05 +#define MPR084_STR3_ADDR 0x06 +#define MPR084_STR4_ADDR 0x07 +#define MPR084_STR5_ADDR 0x08 +#define MPR084_STR6_ADDR 0x09 +#define MPR084_STR7_ADDR 0x0A +#define MPR084_STR8_ADDR 0x0B +#define MPR084_ECEM_ADDR 0x0C +#define MPR084_MNTP_ADDR 0x0D +#define MPR084_MTC_ADDR 0x0E +#define MPR084_TASP_ADDR 0x0F +#define MPR084_SC_ADDR 0x10 +#define MPR084_LPC_ADDR 0x11 +#define MPR084_SKT_ADDR 0x12 +#define MPR084_CONFIG_ADDR 0x13 +#define MPR084_SI_ADDR 0x14 +#define MPR084_ADDR_MINI MPR084_FIFO_ADDR +#define MPR084_ADDR_MAX MPR084_SI_ADDR + +/* FIFO registers */ +#define MPR084_FIFO_MORE_DATA_FLAG 0x80 +#define MPR084_FIFO_NO_DATA_FLAG 0x40 +#define MPR084_FIFO_OVERFLOW_FLAG 0x20 +#define MPR084_FIFO_PAD_IS_TOUCHED 0x10 +#define MPR084_FIFO_POSITION_MASK 0x0F + +#define DRIVER_NAME "mpr084" + +struct mpr084_data { + struct i2c_client *client; + struct device_driver driver; + struct input_dev *idev; + struct task_struct *tstask; + struct completion kpirq_completion; + int kpirq; + int kp_thread_cnt; + int opened; +}; + +static int kpstatus[KEY_COUNT]; +static struct mxc_keyp_platform_data *keypad; +static const unsigned short *mxckpd_keycodes; +static struct regulator *vdd_reg; + +static int mpr084_read_register(struct mpr084_data *data, + unsigned char regaddr, int *value) +{ + int ret = 0; + unsigned char regvalue; + + ret = i2c_master_send(data->client, ®addr, 1); + if (ret < 0) + goto err; + udelay(20); + ret = i2c_master_recv(data->client, ®value, 1); + if (ret < 0) + goto err; + *value = regvalue; + + return ret; +err: + return -ENODEV; +} + +static int mpr084_write_register(struct mpr084_data *data, + u8 regaddr, u8 regvalue) +{ + int ret = 0; + unsigned char msgbuf[2]; + + msgbuf[0] = regaddr; + msgbuf[1] = regvalue; + ret = i2c_master_send(data->client, msgbuf, 2); + if (ret < 0) { + printk(KERN_ERR "%s - Error in writing to I2C Register %d \n", + __func__, regaddr); + return ret; + } + + return ret; +} + + +static irqreturn_t mpr084_keypadirq(int irq, void *v) +{ + struct mpr084_data *d = v; + + disable_irq(d->kpirq); + complete(&d->kpirq_completion); + return IRQ_HANDLED; +} + +static int mpr084ts_thread(void *v) +{ + struct mpr084_data *d = v; + int ret = 0, fifo = 0; + int index = 0, currentstatus = 0; + + if (d->kp_thread_cnt) + return -EINVAL; + d->kp_thread_cnt = 1; + while (1) { + + if (kthread_should_stop()) + break; + /* Wait for keypad interrupt */ + if (wait_for_completion_interruptible_timeout + (&d->kpirq_completion, HZ) <= 0) + continue; + + ret = mpr084_read_register(d, MPR084_FIFO_ADDR, &fifo); + if (ret < 0) { + printk(KERN_ERR + "%s: Err in reading keypad FIFO register \n\n", + __func__); + } else { + if (fifo & MPR084_FIFO_OVERFLOW_FLAG) + printk(KERN_ERR + "%s: FIFO overflow \n\n", __func__); + while (!(fifo & MPR084_FIFO_NO_DATA_FLAG)) { + index = fifo & MPR084_FIFO_POSITION_MASK; + currentstatus = + fifo & MPR084_FIFO_PAD_IS_TOUCHED; + /*Scan key map for changes */ + if ((currentstatus) ^ (kpstatus[index])) { + if (!(currentstatus)) { + /*Key released. */ + input_event(d->idev, EV_KEY, + mxckpd_keycodes + [index], 0); + } else { + /* Key pressed. */ + input_event(d->idev, EV_KEY, + mxckpd_keycodes + [index], 1); + } + /*Store current keypad status */ + kpstatus[index] = currentstatus; + } + mpr084_read_register(d, MPR084_FIFO_ADDR, + &fifo); + if (fifo & MPR084_FIFO_OVERFLOW_FLAG) + printk(KERN_ERR + "%s: FIFO overflow \n\n", + __func__); + } + } + /* Re-enable interrupts */ + enable_irq(d->kpirq); + } + + d->kp_thread_cnt = 0; + return 0; +} + +/*! + * This function puts the Keypad controller in low-power mode/state. + * + * @param pdev the device structure used to give information on Keypad + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mpr084_suspend(struct i2c_client *client, pm_message_t state) +{ + struct mpr084_data *d = i2c_get_clientdata(client); + + if (!IS_ERR(d->tstask) && d->opened) + kthread_stop(d->tstask); + + return 0; +} + +/*! + * This function brings the Keypad controller back from low-power state. + * + * @param pdev the device structure used to give information on Keypad + * to resume + * + * @return The function always returns 0. + */ +static int mpr084_resume(struct i2c_client *client) +{ + struct mpr084_data *d = i2c_get_clientdata(client); + + if (d->opened) + d->tstask = kthread_run(mpr084ts_thread, d, DRIVER_NAME "kpd"); + + return 0; +} + +static int mpr084_idev_open(struct input_dev *idev) +{ + struct mpr084_data *d = input_get_drvdata(idev); + int ret = 0; + + d->tstask = kthread_run(mpr084ts_thread, d, DRIVER_NAME "kpd"); + if (IS_ERR(d->tstask)) + ret = PTR_ERR(d->tstask); + else + d->opened++; + return ret; +} + +static void mpr084_idev_close(struct input_dev *idev) +{ + struct mpr084_data *d = input_get_drvdata(idev); + + if (!IS_ERR(d->tstask)) + kthread_stop(d->tstask); + if (d->opened > 0) + d->opened--; +} + +static int mpr084_driver_register(struct mpr084_data *data) +{ + struct input_dev *idev; + int ret = 0; + + if (data->kpirq) { + ret = + request_irq(data->kpirq, mpr084_keypadirq, + IRQF_TRIGGER_FALLING, DRIVER_NAME, data); + if (!ret) { + init_completion(&data->kpirq_completion); + set_irq_wake(data->kpirq, 1); + } else { + printk(KERN_ERR "%s: cannot grab irq %d\n", + __func__, data->kpirq); + } + + } + idev = input_allocate_device(); + data->idev = idev; + input_set_drvdata(idev, data); + idev->name = DRIVER_NAME; + idev->open = mpr084_idev_open; + idev->close = mpr084_idev_close; + if (!ret) + ret = input_register_device(idev); + + return ret; +} + +static int mpr084_i2c_remove(struct i2c_client *client) +{ + struct mpr084_data *d = i2c_get_clientdata(client); + + free_irq(d->kpirq, d); + input_unregister_device(d->idev); + if (keypad->inactive) + keypad->inactive(); + + /*Disable the Regulator*/ + if (keypad->vdd_reg) { + regulator_disable(vdd_reg); + regulator_put(vdd_reg); + } + + return 0; +} + +static int mpr084_configure(struct mpr084_data *data) +{ + int ret = 0, regValue = 0; + + ret = mpr084_write_register(data, MPR084_TPC_ADDR, 0x1d); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR1_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR2_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR3_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR4_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR5_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR6_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR7_ADDR, 0x10); + if (ret < 0) + goto err; + ret = mpr084_write_register(data, MPR084_STR8_ADDR, 0x10); + if (ret < 0) + goto err; + /* channel enable mask: enable all */ + ret = mpr084_write_register(data, MPR084_ECEM_ADDR, 0xff); + if (ret < 0) + goto err; + /*two conccurrent touch position allowed */ + ret = mpr084_write_register(data, MPR084_MNTP_ADDR, 0x02); + if (ret < 0) + goto err; + + /* master tick period*/ + ret = mpr084_write_register(data, MPR084_MTC_ADDR, 0x05); + if (ret < 0) + goto err; + + + /*Sample period */ + ret = mpr084_write_register(data, MPR084_TASP_ADDR, 0x02); + if (ret < 0) + goto err; + + + /* disable sournder*/ + ret = mpr084_write_register(data, MPR084_SC_ADDR, 0x00); + if (ret < 0) + goto err; + + /* stuck key timeout */ + ret = mpr084_write_register(data, MPR084_SKT_ADDR, 0x01); + if (ret < 0) + goto err; + + /*enabled IRQEN, RUNE, IRQR */ + ret = mpr084_read_register(data, MPR084_CONFIG_ADDR, ®Value); + if (ret < 0) { + printk(KERN_ERR + "%s: Err in reading keypad CONFIGADDR register \n\n", + __func__); + goto err; + } + regValue |= 0x03; + ret = mpr084_write_register(data, MPR084_CONFIG_ADDR, regValue); + if (ret < 0) + goto err; + return ret; +err: + return -ENODEV; +} + +static int mpr084_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct mpr084_data *data; + int err = 0, i = 0; +#if DEBUG + int regValue = 0; +#endif + data = kzalloc(sizeof(struct mpr084_data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + i2c_set_clientdata(client, data); + data->client = client; + data->kpirq = client->irq; + err = mpr084_driver_register(data); + if (err < 0) + goto exit_free; + keypad = (struct mxc_keyp_platform_data *)(client->dev).platform_data; + if (keypad->active) + keypad->active(); + + /*Enable the Regulator*/ + if (keypad && keypad->vdd_reg) { + vdd_reg = regulator_get(&client->dev, keypad->vdd_reg); + if (!IS_ERR(vdd_reg)) + regulator_enable(vdd_reg); + else + vdd_reg = NULL; + } else + vdd_reg = NULL; + + mxckpd_keycodes = keypad->matrix; + data->idev->keycode = &mxckpd_keycodes; + data->idev->keycodesize = sizeof(unsigned char); + data->idev->keycodemax = KEY_COUNT; + data->idev->id.bustype = BUS_I2C; + __set_bit(EV_KEY, data->idev->evbit); + for (i = 0; i < 8; i++) + __set_bit(mxckpd_keycodes[i], data->idev->keybit); + err = mpr084_configure(data); + if (err == -ENODEV) { + free_irq(data->kpirq, data); + input_unregister_device(data->idev); + goto exit_free; + } + +#if DEBUG + for (i = MPR084_ADDR_MINI; i <= MPR084_ADDR_MAX; i++) { + err = mpr084_read_register(data, i, ®Value); + if (err < 0) { + printk(KERN_ERR + "%s: Err in reading keypad CONFIGADDR register \n\n", + __func__); + goto exit_free; + } + printk("MPR084 Register id: %d, Value:%d \n", i, regValue); + + } +#endif + memset(kpstatus, 0, sizeof(kpstatus)); + printk(KERN_INFO "%s: Device Attached\n", __func__); + return 0; +exit_free: + /*disable the Regulator*/ + if (vdd_reg) { + regulator_disable(vdd_reg); + regulator_put(vdd_reg); + vdd_reg = NULL; + } + kfree(data); + return err; +} + +static const struct i2c_device_id mpr084_id[] = { + { "mpr084", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, mpr084_id); + +static struct i2c_driver mpr084_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .probe = mpr084_i2c_probe, + .remove = mpr084_i2c_remove, + .suspend = mpr084_suspend, + .resume = mpr084_resume, + .command = NULL, + .id_table = mpr084_id, +}; +static int __init mpr084_init(void) +{ + return i2c_add_driver(&mpr084_driver); +} + +static void __exit mpr084_exit(void) +{ + i2c_del_driver(&mpr084_driver); +} + +MODULE_AUTHOR("Freescale Semiconductor Inc"); +MODULE_DESCRIPTION("MPR084 Touch KeyPad Controller driver"); +MODULE_LICENSE("GPL"); +module_init(mpr084_init); +module_exit(mpr084_exit); diff --git a/drivers/input/keyboard/mpr121.c b/drivers/input/keyboard/mpr121.c new file mode 100644 index 000000000000..6a723235805d --- /dev/null +++ b/drivers/input/keyboard/mpr121.c @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * mpr121.c - Touchkey driver for Freescale MPR121 Capacitive Touch + * Sensor Controllor + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mpr121_touchkey_data { + struct i2c_client *client; + struct input_dev *input_dev; + unsigned int key_val; + int statusbits; + int keycount; + u16 keycodes[MPR121_MAX_KEY_COUNT]; +}; + +struct mpr121_init_register { + int addr; + u8 val; +}; + +static struct mpr121_init_register init_reg_table[] = { + {MHD_RISING_ADDR, 0x1}, + {NHD_RISING_ADDR, 0x1}, + {NCL_RISING_ADDR, 0x0}, + {FDL_RISING_ADDR, 0x0}, + {MHD_FALLING_ADDR, 0x1}, + {NHD_FALLING_ADDR, 0x1}, + {NCL_FALLING_ADDR, 0xff}, + {FDL_FALLING_ADDR, 0x02}, + {FILTER_CONF_ADDR, 0x04}, + {AFE_CONF_ADDR, 0x0b}, + {AUTO_CONFIG_CTRL_ADDR, 0x0b}, +}; + +static irqreturn_t mpr_touchkey_interrupt(int irq, void *dev_id) +{ + struct mpr121_touchkey_data *data = dev_id; + struct i2c_client *client = data->client; + struct input_dev *input = data->input_dev; + unsigned int key_num, pressed; + int reg; + + reg = i2c_smbus_read_byte_data(client, ELE_TOUCH_STATUS_1_ADDR); + if (reg < 0) { + dev_err(&client->dev, "i2c read error [%d]\n", reg); + goto out; + } + + reg <<= 8; + reg |= i2c_smbus_read_byte_data(client, ELE_TOUCH_STATUS_0_ADDR); + if (reg < 0) { + dev_err(&client->dev, "i2c read error [%d]\n", reg); + goto out; + } + + reg &= TOUCH_STATUS_MASK; + /* use old press bit to figure out which bit changed */ + key_num = ffs(reg ^ data->statusbits) - 1; + /* use the bit check the press status */ + pressed = (reg & (1 << (key_num))) >> key_num; + data->statusbits = reg; + data->key_val = data->keycodes[key_num]; + + input_report_key(input, data->key_val, pressed); + input_sync(input); + + dev_dbg(&client->dev, "key %d %d %s\n", key_num, data->key_val, + pressed ? "pressed" : "released"); + +out: + return IRQ_HANDLED; +} + +static int mpr121_phys_init(struct mpr121_platform_data *pdata, + struct mpr121_touchkey_data *data, + struct i2c_client *client) +{ + struct mpr121_init_register *reg; + unsigned char usl, lsl, tl; + int i, t, vdd, ret; + + /* setup touch/release threshold for ele0-ele11 */ + for (i = 0; i <= MPR121_MAX_KEY_COUNT; i++) { + t = ELE0_TOUCH_THRESHOLD_ADDR + (i * 2); + ret = i2c_smbus_write_byte_data(client, t, TOUCH_THRESHOLD); + if (ret < 0) + goto err_i2c_write; + ret = i2c_smbus_write_byte_data(client, t + 1, + RELEASE_THRESHOLD); + if (ret < 0) + goto err_i2c_write; + } + /* setup init register */ + for (i = 0; i < ARRAY_SIZE(init_reg_table); i++) { + reg = &init_reg_table[i]; + ret = i2c_smbus_write_byte_data(client, reg->addr, reg->val); + if (ret < 0) + goto err_i2c_write; + } + /* setup auto-register by vdd,the formula please ref:AN3889 */ + vdd = pdata->vdd_uv / 1000; + usl = ((vdd - 700) * 256) / vdd; + lsl = (usl * 65) / 100; + tl = (usl * 90) / 100; + ret = i2c_smbus_write_byte_data(client, AUTO_CONFIG_USL_ADDR, usl); + if (ret < 0) + goto err_i2c_write; + ret = i2c_smbus_write_byte_data(client, AUTO_CONFIG_LSL_ADDR, lsl); + if (ret < 0) + goto err_i2c_write; + ret = i2c_smbus_write_byte_data(client, AUTO_CONFIG_TL_ADDR, tl); + if (ret < 0) + goto err_i2c_write; + ret = i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR, + data->keycount); + if (ret < 0) + goto err_i2c_write; + + dev_info(&client->dev, "mpr121: config as enable %x of electrode.\n", + data->keycount); + + return 0; + +err_i2c_write: + dev_err(&client->dev, "i2c write error[%d]\n", ret); + return ret; +} + +static int __devinit mpr_touchkey_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct mpr121_platform_data *pdata; + struct mpr121_touchkey_data *data; + struct input_dev *input_dev; + int error; + int i; + + pdata = client->dev.platform_data; + if (!pdata) { + dev_err(&client->dev, "no platform data defined\n"); + return -EINVAL; + } + + data = kzalloc(sizeof(struct mpr121_touchkey_data), GFP_KERNEL); + input_dev = input_allocate_device(); + if (!data || !input_dev) { + dev_err(&client->dev, "Falied to allocate memory\n"); + error = -ENOMEM; + goto err_free_mem; + } + + data->client = client; + data->input_dev = input_dev; + data->keycount = pdata->keycount; + + if (data->keycount > MPR121_MAX_KEY_COUNT) { + dev_err(&client->dev, "Too many key defined\n"); + error = -EINVAL; + goto err_free_mem; + } + + error = mpr121_phys_init(pdata, data, client); + if (error < 0) { + dev_err(&client->dev, "Failed to init register\n"); + goto err_free_mem; + } + + i2c_set_clientdata(client, data); + + input_dev->name = "FSL MPR121 Touchkey"; + input_dev->id.bustype = BUS_I2C; + input_dev->dev.parent = &client->dev; + input_dev->keycode = pdata->matrix; + input_dev->keycodesize = sizeof(pdata->matrix[0]); + input_dev->keycodemax = data->keycount; + + for (i = 0; i < input_dev->keycodemax; i++) { + __set_bit(pdata->matrix[i], input_dev->keybit); + data->keycodes[i] = pdata->matrix[i]; + input_set_capability(input_dev, EV_KEY, pdata->matrix[i]); + } + input_set_drvdata(input_dev, data); + + error = request_threaded_irq(client->irq, NULL, + mpr_touchkey_interrupt, + IRQF_TRIGGER_FALLING, + client->dev.driver->name, data); + if (error) { + dev_err(&client->dev, "Failed to register interrupt\n"); + goto err_free_mem; + } + + error = input_register_device(input_dev); + if (error) + goto err_free_irq; + i2c_set_clientdata(client, data); + device_init_wakeup(&client->dev, pdata->wakeup); + dev_info(&client->dev, "Mpr121 touch keyboard init success.\n"); + return 0; + +err_free_irq: + free_irq(client->irq, data); +err_free_mem: + input_free_device(input_dev); + kfree(data); + return error; +} + +static int __devexit mpr_touchkey_remove(struct i2c_client *client) +{ + struct mpr121_touchkey_data *data = i2c_get_clientdata(client); + + free_irq(client->irq, data); + input_unregister_device(data->input_dev); + kfree(data); + + return 0; +} + +#ifdef CONFIG_PM +static int mpr_suspend(struct i2c_client *client, pm_message_t mesg) +{ + if (device_may_wakeup(&client->dev)) + enable_irq_wake(client->irq); + + i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR, 0x00); + + return 0; +} + +static int mpr_resume(struct i2c_client *client) +{ + struct mpr121_touchkey_data *data = i2c_get_clientdata(client); + + if (device_may_wakeup(&client->dev)) + disable_irq_wake(client->irq); + + i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR, data->keycount); + + return 0; +} +#else +static int mpr_suspend(struct i2c_client *client, pm_message_t mesg) {} +static int mpr_resume(struct i2c_client *client) {} +#endif + +static const struct i2c_device_id mpr121_id[] = { + {"mpr121_touchkey", 0}, + { } +}; + +static struct i2c_driver mpr_touchkey_driver = { + .driver = { + .name = "mpr121", + .owner = THIS_MODULE, + }, + .id_table = mpr121_id, + .probe = mpr_touchkey_probe, + .remove = __devexit_p(mpr_touchkey_remove), + .suspend = mpr_suspend, + .resume = mpr_resume, +}; + +static int __init mpr_touchkey_init(void) +{ + return i2c_add_driver(&mpr_touchkey_driver); +} + +static void __exit mpr_touchkey_exit(void) +{ + i2c_del_driver(&mpr_touchkey_driver); +} + +module_init(mpr_touchkey_init); +module_exit(mpr_touchkey_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Touch Key driver for FSL MPR121 Chip"); diff --git a/drivers/input/keyboard/mxc_keyb.c b/drivers/input/keyboard/mxc_keyb.c new file mode 100644 index 000000000000..740140f3f0e2 --- /dev/null +++ b/drivers/input/keyboard/mxc_keyb.c @@ -0,0 +1,1203 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_keyb.c + * + * @brief Driver for the Freescale Semiconductor MXC keypad port. + * + * The keypad driver is designed as a standard Input driver which interacts + * with low level keypad port hardware. Upon opening, the Keypad driver + * initializes the keypad port. When the keypad interrupt happens the driver + * calles keypad polling timer and scans the keypad matrix for key + * press/release. If all key press/release happened it comes out of timer and + * waits for key press interrupt. The scancode for key press and release events + * are passed to Input subsytem. + * + * @ingroup keypad + */ + +/*! + * Comment KPP_DEBUG to disable debug messages + */ +#define KPP_DEBUG 0 + +#if KPP_DEBUG +#define DEBUG +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * Keypad Module Name + */ +#define MOD_NAME "mxckpd" + +/*! + * XLATE mode selection + */ +#define KEYPAD_XLATE 0 + +/*! + * RAW mode selection + */ +#define KEYPAD_RAW 1 + +/*! + * Maximum number of keys. + */ +#define MAXROW 8 +#define MAXCOL 8 +#define MXC_MAXKEY (MAXROW * MAXCOL) + +/*! + * This define indicates break scancode for every key release. A constant + * of 128 is added to the key press scancode. + */ +#define MXC_KEYRELEASE 128 + +/* + * _reg_KPP_KPCR _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR + * The offset of Keypad Control Register Address + */ +#define KPCR 0x00 + +/* + * The offset of Keypad Status Register Address + */ +#define KPSR 0x02 + +/* + * The offset of Keypad Data Direction Address + */ +#define KDDR 0x04 + +/* + * The offset of Keypad Data Register + */ +#define KPDR 0x06 + +/* + * Key Press Interrupt Status bit + */ +#define KBD_STAT_KPKD 0x01 + +/* + * Key Release Interrupt Status bit + */ +#define KBD_STAT_KPKR 0x02 + +/* + * Key Depress Synchronizer Chain Status bit + */ +#define KBD_STAT_KDSC 0x04 + +/* + * Key Release Synchronizer Status bit + */ +#define KBD_STAT_KRSS 0x08 + +/* + * Key Depress Interrupt Enable Status bit + */ +#define KBD_STAT_KDIE 0x100 + +/* + * Key Release Interrupt Enable + */ +#define KBD_STAT_KRIE 0x200 + +/* + * Keypad Clock Enable + */ +#define KBD_STAT_KPPEN 0x400 + +/*! + * Buffer size of keypad queue. Should be a power of 2. + */ +#define KPP_BUF_SIZE 128 + +/*! + * Test whether bit is set for integer c + */ +#define TEST_BIT(c, n) ((c) & (0x1 << (n))) + +/*! + * Set nth bit in the integer c + */ +#define BITSET(c, n) ((c) | (1 << (n))) + +/*! + * Reset nth bit in the integer c + */ +#define BITRESET(c, n) ((c) & ~(1 << (n))) + +/*! + * This enum represents the keypad state machine to maintain debounce logic + * for key press/release. + */ +enum KeyState { + + /*! + * Key press state. + */ + KStateUp, + + /*! + * Key press debounce state. + */ + KStateFirstDown, + + /*! + * Key release state. + */ + KStateDown, + + /*! + * Key release debounce state. + */ + KStateFirstUp +}; + +/*! + * Keypad Private Data Structure + */ +struct keypad_priv { + + /*! + * Keypad state machine. + */ + enum KeyState iKeyState; + + /*! + * Number of rows configured in the keypad matrix + */ + unsigned long kpp_rows; + + /*! + * Number of Columns configured in the keypad matrix + */ + unsigned long kpp_cols; + + /*! + * Timer used for Keypad polling. + */ + struct timer_list poll_timer; + + /*! + * The base address + */ + void __iomem *base; +}; +/*! + * This structure holds the keypad private data structure. + */ +static struct keypad_priv kpp_dev; + +/*! Indicates if the key pad device is enabled. */ +static unsigned int key_pad_enabled; + +/*! Input device structure. */ +static struct input_dev *mxckbd_dev; + +/*! KPP clock handle. */ +static struct clk *kpp_clk; + +/*! This static variable indicates whether a key event is pressed/released. */ +static unsigned short KPress; + +/*! cur_rcmap and prev_rcmap array is used to detect key press and release. */ +static unsigned short *cur_rcmap; /* max 64 bits (8x8 matrix) */ +static unsigned short *prev_rcmap; + +/*! + * Debounce polling period(10ms) in system ticks. + */ +static unsigned short KScanRate = (10 * HZ) / 1000; + +static struct keypad_data *keypad; + +static int has_leaning_key; +/*! + * These arrays are used to store press and release scancodes. + */ +static short **press_scancode; +static short **release_scancode; + +static const unsigned short *mxckpd_keycodes; +static unsigned short mxckpd_keycodes_size; + +#define press_left_code 30 +#define press_right_code 29 +#define press_up_code 28 +#define press_down_code 27 + +#define rel_left_code 158 +#define rel_right_code 157 +#define rel_up_code 156 +#define rel_down_code 155 +/*! + * These functions are used to configure and the GPIO pins for keypad to + * activate and deactivate it. + */ +extern void gpio_keypad_active(void); +extern void gpio_keypad_inactive(void); + +/*! + * This function is called for generating scancodes for key press and + * release on keypad for the board. + * + * @param row Keypad row pressed on the keypad matrix. + * @param col Keypad col pressed on the keypad matrix. + * @param press Indicated key press/release. + * + * @return Key press/release Scancode. + */ +static signed short mxc_scan_matrix_leaning_key(int row, int col, int press) +{ + static unsigned first_row; + static unsigned first_set, flag; + signed short scancode = -1; + + if (press) { + if ((3 == col) && ((3 == row) || + (4 == row) || (5 == row) || (6 == row))) { + if (first_set == 0) { + first_set = 1; + first_row = row; + } else { + first_set = 0; + if (((first_row == 6) || (first_row == 3)) + && ((row == 6) || (row == 3))) + scancode = press_down_code; + else if (((first_row == 3) || (first_row == 5)) + && ((row == 3) || (row == 5))) + scancode = press_left_code; + else if (((first_row == 6) || (first_row == 4)) + && ((row == 6) || (row == 4))) + scancode = press_right_code; + else if (((first_row == 4) || (first_row == 5)) + && ((row == 4) || (row == 5))) + scancode = press_up_code; + KPress = 1; + kpp_dev.iKeyState = KStateUp; + pr_debug("Press (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + } + } else { + /* + * check for other keys only + * if the cursor key presses + * are not detected may be + * this needs better logic + */ + if ((0 == (cur_rcmap[3] & BITSET(0, 3))) && + (0 == (cur_rcmap[4] & BITSET(0, 3))) && + (0 == (cur_rcmap[5] & BITSET(0, 3))) && + (0 == (cur_rcmap[6] & BITSET(0, 3)))) { + scancode = ((col * kpp_dev.kpp_rows) + row); + KPress = 1; + kpp_dev.iKeyState = KStateUp; + flag = 1; + pr_debug("Press (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + } + } + } else { + if ((flag == 0) && (3 == col) + && ((3 == row) || (4 == row) || (5 == row) + || (6 == row))) { + if (first_set == 0) { + first_set = 1; + first_row = row; + } else { + first_set = 0; + if (((first_row == 6) || (first_row == 3)) + && ((row == 6) || (row == 3))) + scancode = rel_down_code; + else if (((first_row == 3) || (first_row == 5)) + && ((row == 3) || (row == 5))) + scancode = rel_left_code; + else if (((first_row == 6) || (first_row == 4)) + && ((row == 6) || (row == 4))) + scancode = rel_right_code; + else if (((first_row == 4) || (first_row == 5)) + && ((row == 4) || (row == 5))) + scancode = rel_up_code; + KPress = 0; + kpp_dev.iKeyState = KStateDown; + pr_debug("Release (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + } + } else { + /* + * check for other keys only + * if the cursor key presses + * are not detected may be + * this needs better logic + */ + if ((0 == (prev_rcmap[3] & BITSET(0, 3))) && + (0 == (prev_rcmap[4] & BITSET(0, 3))) && + (0 == (cur_rcmap[5] & BITSET(0, 3))) && + (0 == (cur_rcmap[6] & BITSET(0, 3)))) { + scancode = ((col * kpp_dev.kpp_rows) + row) + + MXC_KEYRELEASE; + KPress = 0; + flag = 0; + kpp_dev.iKeyState = KStateDown; + pr_debug("Release (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + } + } + } + return scancode; +} + +/*! + * This function is called to scan the keypad matrix to find out the key press + * and key release events. Make scancode and break scancode are generated for + * key press and key release events. + * + * The following scanning sequence are done for + * keypad row and column scanning, + * -# Write 1's to KPDR[15:8], setting column data to 1's + * -# Configure columns as totem pole outputs(for quick discharging of keypad + * capacitance) + * -# Configure columns as open-drain + * -# Write a single column to 0, others to 1. + * -# Sample row inputs and save data. Multiple key presses can be detected on + * a single column. + * -# Repeat steps the above steps for remaining columns. + * -# Return all columns to 0 in preparation for standby mode. + * -# Clear KPKD and KPKR status bit(s) by writing to a 1, + * Set the KPKR synchronizer chain by writing "1" to KRSS register, + * Clear the KPKD synchronizer chain by writing "1" to KDSC register + * + * @result Number of key pressed/released. + */ +static int mxc_kpp_scan_matrix(void) +{ + unsigned short reg_val; + int col, row; + short scancode = 0; + int keycnt = 0; /* How many keys are still pressed */ + + /* + * wmb() linux kernel function which guarantees orderings in write + * operations + */ + wmb(); + + /* save cur keypad matrix to prev */ + + memcpy(prev_rcmap, cur_rcmap, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + + for (col = 0; col < kpp_dev.kpp_cols; col++) { /* Col */ + /* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */ + reg_val = __raw_readw(kpp_dev.base + KPDR); + reg_val |= 0xff00; + __raw_writew(reg_val, kpp_dev.base + KPDR); + + /* + * 3. Configure columns as totem pole outputs(for quick + * discharging of keypad capacitance) + */ + reg_val = __raw_readw(kpp_dev.base + KPCR); + reg_val &= 0x00ff; + __raw_writew(reg_val, kpp_dev.base + KPCR); + + udelay(2); + + /* + * 4. Configure columns as open-drain + */ + reg_val = __raw_readw(kpp_dev.base + KPCR); + reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; + __raw_writew(reg_val, kpp_dev.base + KPCR); + + /* + * 5. Write a single column to 0, others to 1. + * 6. Sample row inputs and save data. Multiple key presses + * can be detected on a single column. + * 7. Repeat steps 2 - 6 for remaining columns. + */ + + /* Col bit starts at 8th bit in KPDR */ + reg_val = __raw_readw(kpp_dev.base + KPDR); + reg_val &= ~(1 << (8 + col)); + __raw_writew(reg_val, kpp_dev.base + KPDR); + + /* Delay added to avoid propagating the 0 from column to row + * when scanning. */ + + udelay(5); + + /* Read row input */ + reg_val = __raw_readw(kpp_dev.base + KPDR); + for (row = 0; row < kpp_dev.kpp_rows; row++) { /* sample row */ + if (TEST_BIT(reg_val, row) == 0) { + cur_rcmap[row] = BITSET(cur_rcmap[row], col); + keycnt++; + } + } + } + + /* + * 8. Return all columns to 0 in preparation for standby mode. + * 9. Clear KPKD and KPKR status bit(s) by writing to a .1., + * set the KPKR synchronizer chain by writing "1" to KRSS register, + * clear the KPKD synchronizer chain by writing "1" to KDSC register + */ + reg_val = 0x00; + __raw_writew(reg_val, kpp_dev.base + KPDR); + reg_val = __raw_readw(kpp_dev.base + KPDR); + reg_val = __raw_readw(kpp_dev.base + KPSR); + reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS | + KBD_STAT_KDSC; + __raw_writew(reg_val, kpp_dev.base + KPSR); + + /* Check key press status change */ + + /* + * prev_rcmap array will contain the previous status of the keypad + * matrix. cur_rcmap array will contains the present status of the + * keypad matrix. If a bit is set in the array, that (row, col) bit is + * pressed, else it is not pressed. + * + * XORing these two variables will give us the change in bit for + * particular row and column. If a bit is set in XOR output, then that + * (row, col) has a change of status from the previous state. From + * the diff variable the key press and key release of row and column + * are found out. + * + * If the key press is determined then scancode for key pressed + * can be generated using the following statement: + * scancode = ((row * 8) + col); + * + * If the key release is determined then scancode for key release + * can be generated using the following statement: + * scancode = ((row * 8) + col) + MXC_KEYRELEASE; + */ + for (row = 0; row < kpp_dev.kpp_rows; row++) { + unsigned char diff; + + /* + * Calculate the change in the keypad row status + */ + diff = prev_rcmap[row] ^ cur_rcmap[row]; + + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((diff >> col) & 0x1) { + /* There is a status change on col */ + if ((prev_rcmap[row] & BITSET(0, col)) == 0) { + /* + * Previous state is 0, so now + * a key is pressed + */ + if (has_leaning_key) { + scancode = + mxc_scan_matrix_leaning_key + (row, col, 1); + } else { + scancode = + ((row * kpp_dev.kpp_cols) + + col); + KPress = 1; + kpp_dev.iKeyState = KStateUp; + } + pr_debug("Press (%d, %d) scan=%d " + "Kpress=%d\n", + row, col, scancode, KPress); + press_scancode[row][col] = + (short)scancode; + } else { + /* + * Previous state is not 0, so + * now a key is released + */ + if (has_leaning_key) { + scancode = + mxc_scan_matrix_leaning_key + (row, col, 0); + } else { + scancode = + (row * kpp_dev.kpp_cols) + + col + MXC_KEYRELEASE; + KPress = 0; + kpp_dev.iKeyState = KStateDown; + } + + pr_debug + ("Release (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + release_scancode[row][col] = + (short)scancode; + keycnt++; + } + } + } + } + + /* + * This switch case statement is the + * implementation of state machine of debounce + * logic for key press/release. + * The explaination of state machine is as + * follows: + * + * KStateUp State: + * This is in intial state of the state machine + * this state it checks for any key presses. + * The key press can be checked using the + * variable KPress. If KPress is set, then key + * press is identified and switches the to + * KStateFirstDown state for key press to + * debounce. + * + * KStateFirstDown: + * After debounce delay(10ms), if the KPress is + * still set then pass scancode generated to + * input device and change the state to + * KStateDown, else key press debounce is not + * satisfied so change the state to KStateUp. + * + * KStateDown: + * In this state it checks for any key release. + * If KPress variable is cleared, then key + * release is indicated and so, switch the + * state to KStateFirstUp else to state + * KStateDown. + * + * KStateFirstUp: + * After debounce delay(10ms), if the KPress is + * still reset then pass the key release + * scancode to input device and change + * the state to KStateUp else key release is + * not satisfied so change the state to + * KStateDown. + */ + switch (kpp_dev.iKeyState) { + case KStateUp: + if (KPress) { + /* First Down (must debounce). */ + kpp_dev.iKeyState = KStateFirstDown; + } else { + /* Still UP.(NO Changes) */ + kpp_dev.iKeyState = KStateUp; + } + break; + + case KStateFirstDown: + if (KPress) { + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((press_scancode[row][col] != -1)) { + /* Still Down, so add scancode */ + scancode = + press_scancode[row][col]; + input_event(mxckbd_dev, EV_KEY, + mxckpd_keycodes + [scancode], 1); + if (mxckpd_keycodes[scancode] == + KEY_LEFTSHIFT) { + input_event(mxckbd_dev, + EV_KEY, + KEY_3, 1); + } + kpp_dev.iKeyState = KStateDown; + press_scancode[row][col] = -1; + } + } + } + } else { + /* Just a bounce */ + kpp_dev.iKeyState = KStateUp; + } + break; + + case KStateDown: + if (KPress) { + /* Still down (no change) */ + kpp_dev.iKeyState = KStateDown; + } else { + /* First Up. Must debounce */ + kpp_dev.iKeyState = KStateFirstUp; + } + break; + + case KStateFirstUp: + if (KPress) { + /* Just a bounce */ + kpp_dev.iKeyState = KStateDown; + } else { + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((release_scancode[row][col] != -1)) { + scancode = + release_scancode[row][col]; + scancode = + scancode - MXC_KEYRELEASE; + input_event(mxckbd_dev, EV_KEY, + mxckpd_keycodes + [scancode], 0); + if (mxckpd_keycodes[scancode] == + KEY_LEFTSHIFT) { + input_event(mxckbd_dev, + EV_KEY, + KEY_3, 0); + } + kpp_dev.iKeyState = KStateUp; + release_scancode[row][col] = -1; + } + } + } + } + break; + + default: + return -EBADRQC; + break; + } + + return keycnt; +} + +/*! + * This function is called to start the timer for scanning the keypad if there + * is any key press. Currently this interval is set to 10 ms. When there are + * no keys pressed on the keypad we return back, waiting for a keypad key + * press interrupt. + * + * @param data Opaque data passed back by kernel. Not used. + */ +static void mxc_kpp_handle_timer(unsigned long data) +{ + unsigned short reg_val; + int i; + + if (key_pad_enabled == 0) { + return; + } + if (mxc_kpp_scan_matrix() == 0) { + /* + * Stop scanning and wait for interrupt. + * Enable press interrupt and disable release interrupt. + */ + __raw_writew(0x00FF, kpp_dev.base + KPDR); + reg_val = __raw_readw(kpp_dev.base + KPSR); + reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, kpp_dev.base + KPSR); + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, kpp_dev.base + KPSR); + + /* + * No more keys pressed... make sure unwanted key codes are + * not given upstairs + */ + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * + kpp_dev.kpp_cols); + } + return; + } + + /* + * There are still some keys pressed, continue to scan. + * We shall scan again in 10 ms. This has to be tuned according + * to the requirement. + */ + kpp_dev.poll_timer.expires = jiffies + KScanRate; + kpp_dev.poll_timer.function = mxc_kpp_handle_timer; + add_timer(&kpp_dev.poll_timer); +} + +/*! + * This function is the keypad Interrupt handler. + * This function checks for keypad status register (KPSR) for key press + * and interrupt. If key press interrupt has occurred, then the key + * press interrupt in the KPSR are disabled. + * It then calls mxc_kpp_scan_matrix to check for any key pressed/released. + * If any key is found to be pressed, then a timer is set to call + * mxc_kpp_scan_matrix function for every 10 ms. + * + * @param irq The Interrupt number + * @param dev_id Driver private data + * + * @result The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxc_kpp_interrupt(int irq, void *dev_id) +{ + unsigned short reg_val; + + /* Delete the polling timer */ + del_timer(&kpp_dev.poll_timer); + reg_val = __raw_readw(kpp_dev.base + KPSR); + + /* Check if it is key press interrupt */ + if (reg_val & KBD_STAT_KPKD) { + /* + * Disable key press(KDIE status bit) interrupt + */ + reg_val &= ~KBD_STAT_KDIE; + __raw_writew(reg_val, kpp_dev.base + KPSR); + } else { + /* spurious interrupt */ + return IRQ_RETVAL(0); + } + /* + * Check if any keys are pressed, if so start polling. + */ + mxc_kpp_handle_timer(0); + + return IRQ_RETVAL(1); +} + +/*! + * This function is called when the keypad driver is opened. + * Since keypad initialization is done in __init, nothing is done in open. + * + * @param dev Pointer to device inode + * + * @result The function always return 0 + */ +static int mxc_kpp_open(struct input_dev *dev) +{ + return 0; +} + +/*! + * This function is called close the keypad device. + * Nothing is done in this function, since every thing is taken care in + * __exit function. + * + * @param dev Pointer to device inode + * + */ +static void mxc_kpp_close(struct input_dev *dev) +{ +} + +#ifdef CONFIG_PM +/*! + * This function puts the Keypad controller in low-power mode/state. + * If Keypad is enabled as a wake source(i.e. it can resume the system + * from suspend mode), the Keypad controller doesn't enter low-power state. + * + * @param pdev the device structure used to give information on Keypad + * to suspend + * @param state the power state the device is entering + * + * @return return -1 when the keypad is pressed. Otherwise, return 0 + */ +static int mxc_kpp_suspend(struct platform_device *pdev, pm_message_t state) +{ + /* When the keypad is still pressed, clean up registers and timers */ + if (timer_pending(&kpp_dev.poll_timer)) + return -1; + + if (device_may_wakeup(&pdev->dev)) { + enable_irq_wake(keypad->irq); + } else { + disable_irq(keypad->irq); + key_pad_enabled = 0; + clk_disable(kpp_clk); + gpio_keypad_inactive(); + } + + return 0; +} + +/*! + * This function brings the Keypad controller back from low-power state. + * If Keypad is enabled as a wake source(i.e. it can resume the system + * from suspend mode), the Keypad controller doesn't enter low-power state. + * + * @param pdev the device structure used to give information on Keypad + * to resume + * + * @return The function always returns 0. + */ +static int mxc_kpp_resume(struct platform_device *pdev) +{ + if (device_may_wakeup(&pdev->dev)) { + disable_irq_wake(keypad->irq); + } else { + gpio_keypad_active(); + clk_enable(kpp_clk); + key_pad_enabled = 1; + enable_irq(keypad->irq); + } + + return 0; +} + +#else +#define mxc_kpp_suspend NULL +#define mxc_kpp_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This function is called to free the allocated memory for local arrays + */ +static void mxc_kpp_free_allocated(void) +{ + + int i; + + if (press_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (press_scancode[i]) + kfree(press_scancode[i]); + } + kfree(press_scancode); + } + + if (release_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (release_scancode[i]) + kfree(release_scancode[i]); + } + kfree(release_scancode); + } + + if (cur_rcmap) + kfree(cur_rcmap); + + if (prev_rcmap) + kfree(prev_rcmap); + + if (mxckbd_dev) + input_free_device(mxckbd_dev); +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration. Otherwise returns + * specific error code. + */ +static int mxc_kpp_probe(struct platform_device *pdev) +{ + int i, irq; + int retval; + unsigned int reg_val; + struct resource *res; + + keypad = (struct keypad_data *)pdev->dev.platform_data; + + kpp_dev.kpp_cols = keypad->colmax; + kpp_dev.kpp_rows = keypad->rowmax; + key_pad_enabled = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + kpp_dev.base = ioremap(res->start, res->end - res->start + 1); + if (!kpp_dev.base) + return -ENOMEM; + + irq = platform_get_irq(pdev, 0); + keypad->irq = irq; + + /* Enable keypad clock */ + kpp_clk = clk_get(&pdev->dev, "kpp_clk"); + clk_enable(kpp_clk); + + /* IOMUX configuration for keypad */ + gpio_keypad_active(); + + /* Configure keypad */ + + /* Enable number of rows in keypad (KPCR[7:0]) + * Configure keypad columns as open-drain (KPCR[15:8]) + * + * Configure the rows/cols in KPP + * LSB nibble in KPP is for 8 rows + * MSB nibble in KPP is for 8 cols + */ + reg_val = __raw_readw(kpp_dev.base + KPCR); + reg_val |= (1 << keypad->rowmax) - 1; /* LSB */ + reg_val |= ((1 << keypad->colmax) - 1) << 8; /* MSB */ + __raw_writew(reg_val, kpp_dev.base + KPCR); + + /* Write 0's to KPDR[15:8] */ + reg_val = __raw_readw(kpp_dev.base + KPDR); + reg_val &= 0x00ff; + __raw_writew(reg_val, kpp_dev.base + KPDR); + + /* Configure columns as output, rows as input (KDDR[15:0]) */ + reg_val = __raw_readw(kpp_dev.base + KDDR); + reg_val |= 0xff00; + reg_val &= 0xff00; + __raw_writew(reg_val, kpp_dev.base + KDDR); + + reg_val = __raw_readw(kpp_dev.base + KPSR); + reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KPKD; + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, kpp_dev.base + KPSR); + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, kpp_dev.base + KPSR); + + has_leaning_key = keypad->learning; + mxckpd_keycodes = keypad->matrix; + mxckpd_keycodes_size = keypad->rowmax * keypad->colmax; + + if ((keypad->matrix == (void *)0) + || (mxckpd_keycodes_size == 0)) { + retval = -ENODEV; + goto err1; + } + + mxckbd_dev = input_allocate_device(); + if (!mxckbd_dev) { + printk(KERN_ERR + "mxckbd_dev: not enough memory for input device\n"); + retval = -ENOMEM; + goto err1; + } + + mxckbd_dev->keycode = (void *)mxckpd_keycodes; + mxckbd_dev->keycodesize = sizeof(mxckpd_keycodes[0]); + mxckbd_dev->keycodemax = mxckpd_keycodes_size; + mxckbd_dev->name = "mxckpd"; + mxckbd_dev->id.bustype = BUS_HOST; + mxckbd_dev->open = mxc_kpp_open; + mxckbd_dev->close = mxc_kpp_close; + + retval = input_register_device(mxckbd_dev); + if (retval < 0) { + printk(KERN_ERR + "mxckbd_dev: failed to register input device\n"); + goto err2; + } + + /* allocate required memory */ + press_scancode = kmalloc(kpp_dev.kpp_rows * sizeof(press_scancode[0]), + GFP_KERNEL); + release_scancode = + kmalloc(kpp_dev.kpp_rows * sizeof(release_scancode[0]), GFP_KERNEL); + + if (!press_scancode || !release_scancode) { + retval = -ENOMEM; + goto err3; + } + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + press_scancode[i] = kmalloc(kpp_dev.kpp_cols + * sizeof(press_scancode[0][0]), + GFP_KERNEL); + release_scancode[i] = + kmalloc(kpp_dev.kpp_cols * sizeof(release_scancode[0][0]), + GFP_KERNEL); + + if (!press_scancode[i] || !release_scancode[i]) { + retval = -ENOMEM; + goto err3; + } + } + + cur_rcmap = + kmalloc(kpp_dev.kpp_rows * sizeof(cur_rcmap[0]), GFP_KERNEL); + prev_rcmap = + kmalloc(kpp_dev.kpp_rows * sizeof(prev_rcmap[0]), GFP_KERNEL); + + if (!cur_rcmap || !prev_rcmap) { + retval = -ENOMEM; + goto err3; + } + + __set_bit(EV_KEY, mxckbd_dev->evbit); + + for (i = 0; i < mxckpd_keycodes_size; i++) + __set_bit(mxckpd_keycodes[i], mxckbd_dev->keybit); + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * kpp_dev.kpp_cols); + } + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + memset(prev_rcmap, 0, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + + key_pad_enabled = 1; + /* Initialize the polling timer */ + init_timer(&kpp_dev.poll_timer); + + /* + * Request for IRQ number for keypad port. The Interrupt handler + * function (mxc_kpp_interrupt) is called when ever interrupt occurs on + * keypad port. + */ + retval = request_irq(irq, mxc_kpp_interrupt, 0, MOD_NAME, MOD_NAME); + if (retval) { + pr_debug("KPP: request_irq(%d) returned error %d\n", + irq, retval); + goto err3; + } + + /* By default, devices should wakeup if they can */ + /* So keypad is set as "should wakeup" as it can */ + device_init_wakeup(&pdev->dev, 1); + + return 0; + + err3: + mxc_kpp_free_allocated(); + err2: + input_free_device(mxckbd_dev); + err1: + free_irq(irq, MOD_NAME); + clk_disable(kpp_clk); + clk_put(kpp_clk); + return retval; +} + +/*! + * Dissociates the driver from the kpp device. + * + * @param pdev the device structure used to give information on which SDHC + * to remove + * + * @return The function always returns 0. + */ +static int mxc_kpp_remove(struct platform_device *pdev) +{ + unsigned short reg_val; + + /* + * Clear the KPKD status flag (write 1 to it) and synchronizer chain. + * Set KDIE control bit, clear KRIE control bit (avoid false release + * events. Disable the keypad GPIO pins. + */ + __raw_writew(0x00, kpp_dev.base + KPCR); + __raw_writew(0x00, kpp_dev.base + KPDR); + __raw_writew(0x00, kpp_dev.base + KDDR); + + reg_val = __raw_readw(kpp_dev.base + KPSR); + reg_val |= KBD_STAT_KPKD; + reg_val &= ~KBD_STAT_KRSS; + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, kpp_dev.base + KPSR); + + gpio_keypad_inactive(); + clk_disable(kpp_clk); + clk_put(kpp_clk); + + KPress = 0; + + del_timer(&kpp_dev.poll_timer); + + free_irq(keypad->irq, MOD_NAME); + input_unregister_device(mxckbd_dev); + + mxc_kpp_free_allocated(); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_kpd_driver = { + .driver = { + .name = "mxc_keypad", + .bus = &platform_bus_type, + }, + .suspend = mxc_kpp_suspend, + .resume = mxc_kpp_resume, + .probe = mxc_kpp_probe, + .remove = mxc_kpp_remove +}; + +/*! + * This function is called for module initialization. + * It registers keypad char driver and requests for KPP irq number. This + * function does the initialization of the keypad device. + * + * The following steps are used for keypad configuration,\n + * -# Enable number of rows in the keypad control register (KPCR[7:0}).\n + * -# Write 0's to KPDR[15:8]\n + * -# Configure keypad columns as open-drain (KPCR[15:8])\n + * -# Configure columns as output, rows as input (KDDR[15:0])\n + * -# Clear the KPKD status flag (write 1 to it) and synchronizer chain\n + * -# Set KDIE control bit, clear KRIE control bit\n + * In this function the keypad queue initialization is done. + * The keypad IOMUX configuration are done here.* + + * + * @return 0 on success and a non-zero value on failure. + */ +static int __init mxc_kpp_init(void) +{ + printk(KERN_INFO "MXC keypad loaded\n"); + platform_driver_register(&mxc_kpd_driver); + return 0; +} + +/*! + * This function is called whenever the module is removed from the kernel. It + * unregisters the keypad driver from kernel and frees the irq number. + * This function puts the keypad to standby mode. The keypad interrupts are + * disabled. It calls gpio_keypad_inactive function to switch gpio + * configuration into default state. + * + */ +static void __exit mxc_kpp_cleanup(void) +{ + platform_driver_unregister(&mxc_kpd_driver); +} + +module_init(mxc_kpp_init); +module_exit(mxc_kpp_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Keypad Controller Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/keyboard/mxc_pwrkey.c b/drivers/input/keyboard/mxc_pwrkey.c new file mode 100644 index 000000000000..7e8ae02c8fee --- /dev/null +++ b/drivers/input/keyboard/mxc_pwrkey.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mxc_pwrkey_priv { + + struct input_dev *input; + int value; + int (*get_status) (int); +}; + +static struct mxc_pwrkey_priv *mxc_pwrkey; + +static void pwrkey_event_handler(void *param) +{ + int pressed; + + pressed = mxc_pwrkey->get_status((int)param); + + if (pressed) { + input_report_key( + mxc_pwrkey->input, mxc_pwrkey->value, 1); + pr_info("%s_Keydown\n", __func__); + } else { + input_report_key( + mxc_pwrkey->input, mxc_pwrkey->value, 0); + pr_info("%s_Keyup\n", __func__); + } +} + +static int mxcpwrkey_probe(struct platform_device *pdev) +{ + int retval; + struct input_dev *input; + struct power_key_platform_data *pdata = pdev->dev.platform_data; + + if (mxc_pwrkey) { + dev_warn(&pdev->dev, "two power key??\n"); + return -EBUSY; + } + + if (!pdata || !pdata->get_key_status) { + dev_err(&pdev->dev, "can not get platform data\n"); + return -EINVAL; + } + + mxc_pwrkey = kmalloc(sizeof(struct mxc_pwrkey_priv), GFP_KERNEL); + if (!mxc_pwrkey) { + dev_err(&pdev->dev, "can not allocate private data"); + return -ENOMEM; + } + + input = input_allocate_device(); + if (!input) { + dev_err(&pdev->dev, "no memory for input device\n"); + retval = -ENOMEM; + goto err1; + } + + input->name = "mxc_power_key"; + input->phys = "mxcpwrkey/input0"; + input->id.bustype = BUS_HOST; + input->evbit[0] = BIT_MASK(EV_KEY); + + mxc_pwrkey->value = pdata->key_value; + mxc_pwrkey->get_status = pdata->get_key_status; + mxc_pwrkey->input = input; + pdata->register_pwrkey(pwrkey_event_handler); + + input_set_capability(input, EV_KEY, mxc_pwrkey->value); + + retval = input_register_device(input); + if (retval < 0) { + dev_err(&pdev->dev, "failed to register input device\n"); + goto err2; + } + + printk(KERN_INFO "PMIC powerkey probe\n"); + + return 0; + +err2: + input_free_device(input); +err1: + kfree(mxc_pwrkey); + mxc_pwrkey = NULL; + + return retval; +} + +static int mxcpwrkey_remove(struct platform_device *pdev) +{ + input_unregister_device(mxc_pwrkey->input); + input_free_device(mxc_pwrkey->input); + kfree(mxc_pwrkey); + mxc_pwrkey = NULL; + + return 0; +} + +static struct platform_driver mxcpwrkey_driver = { + .driver = { + .name = "mxcpwrkey", + }, + .probe = mxcpwrkey_probe, + .remove = mxcpwrkey_remove, +}; + +static int __init mxcpwrkey_init(void) +{ + return platform_driver_register(&mxcpwrkey_driver); +} + +static void __exit mxcpwrkey_exit(void) +{ + platform_driver_unregister(&mxcpwrkey_driver); +} + +module_init(mxcpwrkey_init); +module_exit(mxcpwrkey_exit); + + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("MXC board power key Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/keyboard/mxs-kbd.c b/drivers/input/keyboard/mxs-kbd.c new file mode 100644 index 000000000000..20daee01aae4 --- /dev/null +++ b/drivers/input/keyboard/mxs-kbd.c @@ -0,0 +1,365 @@ +/* + * Keypad ladder driver for Freescale MXS boards + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define BUTTON_PRESS_THRESHOLD 3300 +#define LRADC_NOISE_MARGIN 100 + +/* this value represents the the lradc value at 3.3V ( 3.3V / 0.000879 V/b ) */ +#define TARGET_VDDIO_LRADC_VALUE 3754 + +struct mxskbd_data { + struct input_dev *input; + int last_button; + int irq; + int btn_irq; + struct mxskbd_keypair *keycodes; + unsigned int base; + int chan; + unsigned int btn_enable; /* detect enable bits */ + unsigned int btn_irq_stat; /* detect irq status bits */ + unsigned int btn_irq_ctrl; /* detect irq enable bits */ +}; + +static int delay1 = 500; +static int delay2 = 200; + +static int mxskbd_open(struct input_dev *dev); +static void mxskbd_close(struct input_dev *dev); + +static struct mxskbd_data *mxskbd_data_alloc(struct platform_device *pdev, + struct mxskbd_keypair *keys) +{ + struct mxskbd_data *d = kzalloc(sizeof(*d), GFP_KERNEL); + + if (!d) + return NULL; + + if (!keys) { + dev_err(&pdev->dev, + "No keycodes in platform_data, bailing out.\n"); + kfree(d); + return NULL; + } + d->keycodes = keys; + + d->input = input_allocate_device(); + if (!d->input) { + kfree(d); + return NULL; + } + + d->input->phys = "onboard"; + d->input->uniq = "0000'0000"; + d->input->name = pdev->name; + d->input->id.bustype = BUS_HOST; + d->input->open = mxskbd_open; + d->input->close = mxskbd_close; + d->input->dev.parent = &pdev->dev; + + set_bit(EV_KEY, d->input->evbit); + set_bit(EV_REL, d->input->evbit); + set_bit(EV_REP, d->input->evbit); + + + d->last_button = -1; + + while (keys->raw >= 0) { + set_bit(keys->kcode, d->input->keybit); + keys++; + } + + return d; +} + +static inline struct input_dev *GET_INPUT_DEV(struct mxskbd_data *d) +{ + BUG_ON(!d); + return d->input; +} + +static void mxskbd_data_free(struct mxskbd_data *d) +{ + if (!d) + return; + if (d->input) + input_free_device(d->input); + kfree(d); +} + +static unsigned mxskbd_decode_button(struct mxskbd_keypair *codes, + int raw_button) + +{ + pr_debug("Decoding %d\n", raw_button); + while (codes->raw != -1) { + if ((raw_button >= (codes->raw - LRADC_NOISE_MARGIN)) && + (raw_button < (codes->raw + LRADC_NOISE_MARGIN))) { + pr_debug("matches code 0x%x = %d\n", + codes->kcode, codes->kcode); + return codes->kcode; + } + codes++; + } + return (unsigned)-1; /* invalid key */ +} + + +static irqreturn_t mxskbd_irq_handler(int irq, void *dev_id) +{ + struct platform_device *pdev = dev_id; + struct mxskbd_data *devdata = platform_get_drvdata(pdev); + u16 raw_button, normalized_button, vddio; + unsigned btn; + + if (devdata->btn_irq == irq) { + __raw_writel(devdata->btn_irq_stat, + devdata->base + HW_LRADC_CTRL1_CLR); + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << devdata->chan, + devdata->base + HW_LRADC_CTRL1_CLR); + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << devdata->chan, + devdata->base + HW_LRADC_CTRL1_SET); + return IRQ_HANDLED; + } + + raw_button = __raw_readl(devdata->base + HW_LRADC_CHn(devdata->chan)) & + BM_LRADC_CHn_VALUE; + vddio = hw_lradc_vddio(); + BUG_ON(vddio == 0); + + normalized_button = (raw_button * TARGET_VDDIO_LRADC_VALUE) / + vddio; + + if (normalized_button < BUTTON_PRESS_THRESHOLD && + devdata->last_button < 0) { + btn = mxskbd_decode_button(devdata->keycodes, + normalized_button); + if (btn < KEY_MAX) { + devdata->last_button = btn; + input_report_key(GET_INPUT_DEV(devdata), + devdata->last_button, !0); + } else + dev_err(&pdev->dev, "Invalid button: raw = %d, " + "normalized = %d, vddio = %d\n", + raw_button, normalized_button, vddio); + } else if (devdata->last_button > 0 && + normalized_button >= BUTTON_PRESS_THRESHOLD) { + input_report_key(GET_INPUT_DEV(devdata), + devdata->last_button, 0); + devdata->last_button = -1; + if (devdata->btn_irq > 0) + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << + devdata->chan, + devdata->base + HW_LRADC_CTRL1_CLR); + } + + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << devdata->chan, + devdata->base + HW_LRADC_CTRL1_CLR); + return IRQ_HANDLED; +} + +static int mxskbd_open(struct input_dev *dev) +{ + /* enable clock */ + return 0; +} + +static void mxskbd_close(struct input_dev *dev) +{ + /* disable clock */ +} + +static void mxskbd_hwinit(struct platform_device *pdev) +{ + struct mxskbd_data *d = platform_get_drvdata(pdev); + + hw_lradc_init_ladder(d->chan, LRADC_DELAY_TRIGGER_BUTTON, 200); + if (d->btn_irq > 0) { + __raw_writel(d->btn_enable, d->base + HW_LRADC_CTRL0_SET); + __raw_writel(d->btn_irq_ctrl, d->base + HW_LRADC_CTRL1_SET); + } else { + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << d->chan, + d->base + HW_LRADC_CTRL1_CLR); + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << d->chan, + d->base + HW_LRADC_CTRL1_SET); + } + hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_BUTTON, !0); +} + +#ifdef CONFIG_PM +static int mxskbd_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mxskbd_data *d = platform_get_drvdata(pdev); + + hw_lradc_stop_ladder(d->chan, LRADC_DELAY_TRIGGER_BUTTON); + hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_BUTTON, 0); + hw_lradc_unuse_channel(d->chan); + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << d->chan, + d->base + HW_LRADC_CTRL1_CLR); + mxskbd_close(d->input); + return 0; +} + +static int mxskbd_resume(struct platform_device *pdev) +{ + struct mxskbd_data *d = platform_get_drvdata(pdev); + + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << d->chan, + d->base + HW_LRADC_CTRL1_SET); + mxskbd_open(d->input); + hw_lradc_use_channel(d->chan); + mxskbd_hwinit(pdev); + return 0; +} +#endif + +static int __devinit mxskbd_probe(struct platform_device *pdev) +{ + int err = 0; + struct resource *res; + struct mxskbd_data *d; + struct mxs_kbd_plat_data *plat_data; + + plat_data = (struct mxs_kbd_plat_data *)pdev->dev.platform_data; + if (plat_data == NULL) + return -ENODEV; + + /* Create and register the input driver. */ + d = mxskbd_data_alloc(pdev, plat_data->keypair); + if (!d) { + dev_err(&pdev->dev, "Cannot allocate driver structures\n"); + err = -ENOMEM; + goto err_out; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + err = -ENODEV; + goto err_out; + } + d->base = (unsigned int)IO_ADDRESS(res->start); + d->chan = plat_data->channel; + d->irq = platform_get_irq(pdev, 0); + d->btn_irq = platform_get_irq(pdev, 1); + d->btn_enable = plat_data->btn_enable; + d->btn_irq_stat = plat_data->btn_irq_stat; + d->btn_irq_ctrl = plat_data->btn_irq_ctrl; + + platform_set_drvdata(pdev, d); + + err = request_irq(d->irq, mxskbd_irq_handler, + IRQF_DISABLED, pdev->name, pdev); + if (err) { + dev_err(&pdev->dev, "Cannot request keypad IRQ\n"); + goto err_free_dev; + } + + if (d->btn_irq > 0) { + err = request_irq(d->btn_irq, mxskbd_irq_handler, + IRQF_DISABLED, pdev->name, pdev); + if (err) { + dev_err(&pdev->dev, + "Cannot request keybad detect IRQ\n"); + goto err_free_irq; + } + } + + /* Register the input device */ + err = input_register_device(GET_INPUT_DEV(d)); + if (err) + goto err_free_irq2; + + /* these two have to be set after registering the input device */ + d->input->rep[REP_DELAY] = delay1; + d->input->rep[REP_PERIOD] = delay2; + + hw_lradc_use_channel(d->chan); + mxskbd_hwinit(pdev); + + return 0; + +err_free_irq2: + platform_set_drvdata(pdev, NULL); + if (d->btn_irq > 0) + free_irq(d->btn_irq, pdev); +err_free_irq: + free_irq(d->irq, pdev); +err_free_dev: + mxskbd_data_free(d); +err_out: + return err; +} + +static int __devexit mxskbd_remove(struct platform_device *pdev) +{ + struct mxskbd_data *d = platform_get_drvdata(pdev); + + hw_lradc_unuse_channel(d->chan); + input_unregister_device(GET_INPUT_DEV(d)); + free_irq(d->irq, pdev); + if (d->btn_irq > 0) + free_irq(d->btn_irq, pdev); + mxskbd_data_free(d); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver mxskbd_driver = { + .probe = mxskbd_probe, + .remove = __devexit_p(mxskbd_remove), +#ifdef CONFIG_PM + .suspend = mxskbd_suspend, + .resume = mxskbd_resume, +#endif + .driver = { + .name = "mxs-kbd", + }, +}; + +static int __init mxskbd_init(void) +{ + return platform_driver_register(&mxskbd_driver); +} + +static void __exit mxskbd_exit(void) +{ + platform_driver_unregister(&mxskbd_driver); +} + +module_init(mxskbd_init); +module_exit(mxskbd_exit); +MODULE_DESCRIPTION("Freescale keyboard driver for mxs family"); +MODULE_AUTHOR("dmitry pervushin ") +MODULE_LICENSE("GPL"); diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index c44b9eafc556..e407e142ccca 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -390,4 +390,14 @@ config INPUT_PCAP To compile this driver as a module, choose M here: the module will be called pcap_keys. +config INPUT_DA9052_ONKEY + tristate "Dialog DA9052 Onkey" + depends on PMIC_DA9052 + help + Support the ONKEY of Dialog DA9052 PMICs as an input device + reporting power button status. + + To compile this driver as a module, choose M here: the module + will be called da9052_onkey. + endif diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 71fe57d8023f..c8231a783221 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -37,4 +37,4 @@ obj-$(CONFIG_INPUT_WINBOND_CIR) += winbond-cir.o obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o - +obj-$(CONFIG_INPUT_DA9052_ONKEY) += da9052_onkey.o diff --git a/drivers/input/misc/da9052_onkey.c b/drivers/input/misc/da9052_onkey.c new file mode 100644 index 000000000000..dc3bf46420fb --- /dev/null +++ b/drivers/input/misc/da9052_onkey.c @@ -0,0 +1,148 @@ +#include +#include +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "da9052-onkey" + +struct da9052_onkey_data { + struct da9052 *da9052; + struct da9052_eh_nb eh_data; + struct input_dev *input; + struct delayed_work polling_work; +}; + +static void da9052_onkey_work_func(struct work_struct *work) +{ + struct da9052_onkey_data *da9052_onkey = + container_of(work, struct da9052_onkey_data, polling_work.work); + struct da9052_ssc_msg msg; + unsigned int ret; + int value; + + da9052_lock(da9052_onkey->da9052); + msg.addr = DA9052_STATUSA_REG; + ret = da9052_onkey->da9052->read(da9052_onkey->da9052, &msg); + if (ret) { + da9052_unlock(da9052_onkey->da9052); + return; + } + da9052_unlock(da9052_onkey->da9052); + value = (msg.data & DA9052_STATUSA_NONKEY) ? 0 : 1; + + input_report_key(da9052_onkey->input, KEY_POWER, value); + input_sync(da9052_onkey->input); + + /* if key down, polling for up */ + if (value) + schedule_delayed_work(&da9052_onkey->polling_work, HZ/10); +} + +static void da9052_onkey_report_event(struct da9052_eh_nb *eh_data, + unsigned int event) +{ + struct da9052_onkey_data *da9052_onkey = + container_of(eh_data, struct da9052_onkey_data, eh_data); + cancel_delayed_work(&da9052_onkey->polling_work); + schedule_delayed_work(&da9052_onkey->polling_work, 0); + +} + +static int __devinit da9052_onkey_probe(struct platform_device *pdev) +{ + struct da9052_onkey_data *da9052_onkey; + int error; + + da9052_onkey = kzalloc(sizeof(*da9052_onkey), GFP_KERNEL); + da9052_onkey->input = input_allocate_device(); + if (!da9052_onkey->input) { + dev_err(&pdev->dev, "failed to allocate data device\n"); + error = -ENOMEM; + goto fail1; + } + da9052_onkey->da9052 = dev_get_drvdata(pdev->dev.parent); + + if (!da9052_onkey->input) { + dev_err(&pdev->dev, "failed to allocate input device\n"); + error = -ENOMEM; + goto fail2; + } + + da9052_onkey->input->evbit[0] = BIT_MASK(EV_KEY); + da9052_onkey->input->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER); + da9052_onkey->input->name = "da9052-onkey"; + da9052_onkey->input->phys = "da9052-onkey/input0"; + da9052_onkey->input->dev.parent = &pdev->dev; + INIT_DELAYED_WORK(&da9052_onkey->polling_work, da9052_onkey_work_func); + + /* Set the EH structure */ + da9052_onkey->eh_data.eve_type = ONKEY_EVE; + da9052_onkey->eh_data.call_back = &da9052_onkey_report_event; + error = da9052_onkey->da9052->register_event_notifier( + da9052_onkey->da9052, + &da9052_onkey->eh_data); + if (error) + goto fail2; + + error = input_register_device(da9052_onkey->input); + if (error) { + dev_err(&pdev->dev, "Unable to register input\ + device,error: %d\n", error); + goto fail3; + } + + platform_set_drvdata(pdev, da9052_onkey); + + return 0; + +fail3: + da9052_onkey->da9052->unregister_event_notifier(da9052_onkey->da9052, + &da9052_onkey->eh_data); +fail2: + input_free_device(da9052_onkey->input); +fail1: + kfree(da9052_onkey); + return error; +} + +static int __devexit da9052_onkey_remove(struct platform_device *pdev) +{ + struct da9052_onkey_data *da9052_onkey = pdev->dev.platform_data; + da9052_onkey->da9052->unregister_event_notifier(da9052_onkey->da9052, + &da9052_onkey->eh_data); + input_unregister_device(da9052_onkey->input); + kfree(da9052_onkey); + + return 0; +} + +static struct platform_driver da9052_onkey_driver = { + .probe = da9052_onkey_probe, + .remove = __devexit_p(da9052_onkey_remove), + .driver = { + .name = "da9052-onkey", + .owner = THIS_MODULE, + } +}; + +static int __init da9052_onkey_init(void) +{ + return platform_driver_register(&da9052_onkey_driver); +} + +static void __exit da9052_onkey_exit(void) +{ + platform_driver_unregister(&da9052_onkey_driver); +} + +module_init(da9052_onkey_init); +module_exit(da9052_onkey_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("David Dajun Chen "); +MODULE_DESCRIPTION("Onkey driver for DA9052"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 3b9d5e2105d7..2f43f6fb2360 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -268,6 +268,46 @@ config TOUCHSCREEN_HP7XX To compile this driver as a module, choose M here: the module will be called jornada720_ts. +config TOUCHSCREEN_MXC + tristate "MXC touchscreen input driver" + depends on MXC_MC13783_ADC || MXC_MC13892_ADC + help + Say Y here if you have an MXC based board with touchscreen + attached to it. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called mxc_ts. + +config TOUCHSCREEN_IMX_ADC + tristate "Freescale i.MX ADC touchscreen input driver" + depends on IMX_ADC + help + Say Y here if you have a Freescale i.MX based board with a + touchscreen interfaced to the processor's integrated ADC. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called imx_adc_ts. + +config TOUCHSCREEN_STMP3XXX + tristate "STMP3XXX LRADC-based touchscreen" + depends on ARCH_STMP3XXX + select SERIO + help + Say Y here if you want to enable TMP3XXX LRADC-based touchscreen. + module will be called stmp3xxx_ts. + +config TOUCHSCREEN_MXS + tristate "MXS LRADC-based touchscreen" + depends on ARCH_MXS + select SERIO + help + Say Y here if you want to enable MXS LRADC-based touchscreen. + module will be called mxs-ts. + config TOUCHSCREEN_HTCPEN tristate "HTC Shift X9500 touchscreen" depends on ISA @@ -603,4 +643,23 @@ config TOUCHSCREEN_TPS6507X To compile this driver as a module, choose M here: the module will be called tps6507x_ts. +config TOUCHSCREEN_DA9052 + tristate "Dialog DA9052 TSI" + depends on PMIC_DA9052 + help + Say y here to support the touchscreen found on + Dialog Semiconductor DA9052 PMIC + +config TOUCHSCREEN_MAX11801 + tristate "MAXIM MAX11801 touchscreen" + depends on I2C + help + Say Y here if you have a MAX11801 touchscreen + controller + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called max11801_ts + endif diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 497964a7a214..5a46b99a6907 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -27,6 +27,10 @@ obj-$(CONFIG_TOUCHSCREEN_MK712) += mk712.o obj-$(CONFIG_TOUCHSCREEN_HP600) += hp680_ts_input.o obj-$(CONFIG_TOUCHSCREEN_HP7XX) += jornada720_ts.o obj-$(CONFIG_TOUCHSCREEN_HTCPEN) += htcpen.o +obj-$(CONFIG_TOUCHSCREEN_MXC) += mxc_ts.o +obj-$(CONFIG_TOUCHSCREEN_IMX_ADC) += imx_adc_ts.o +obj-$(CONFIG_TOUCHSCREEN_STMP3XXX) += stmp3xxx_ts.o +obj-$(CONFIG_TOUCHSCREEN_MXS) += mxs-ts.o obj-$(CONFIG_TOUCHSCREEN_USB_COMPOSITE) += usbtouchscreen.o obj-$(CONFIG_TOUCHSCREEN_PCAP) += pcap_ts.o obj-$(CONFIG_TOUCHSCREEN_PENMOUNT) += penmount.o @@ -47,3 +51,5 @@ obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o obj-$(CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE) += zylonite-wm97xx.o obj-$(CONFIG_TOUCHSCREEN_W90X900) += w90p910_ts.o obj-$(CONFIG_TOUCHSCREEN_TPS6507X) += tps6507x-ts.o +obj-$(CONFIG_TOUCHSCREEN_DA9052) += da9052_tsi.o da9052_tsi_filter.o da9052_tsi_calibrate.o +obj-$(CONFIG_TOUCHSCREEN_MAX11801) += max11801_ts.o diff --git a/drivers/input/touchscreen/da9052_tsi.c b/drivers/input/touchscreen/da9052_tsi.c new file mode 100644 index 000000000000..a0c7aa9a1de9 --- /dev/null +++ b/drivers/input/touchscreen/da9052_tsi.c @@ -0,0 +1,1449 @@ +/* + * da9052_tsi.c -- TSI driver for Dialog DA9052 + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * Author: Dialog Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define WAIT_FOR_PEN_DOWN 0 +#define WAIT_FOR_SAMPLING 1 +#define SAMPLING_ACTIVE 2 + +static ssize_t __init da9052_tsi_create_input_dev(struct input_dev **ip_dev, + u8 n); +static ssize_t read_da9052_reg(struct da9052 *da9052, u8 reg_addr); +static ssize_t write_da9052_reg(struct da9052 *da9052, u8 reg_addr, u8 data); + +static void da9052_tsi_reg_pendwn_event(struct da9052_ts_priv *priv); +static void da9052_tsi_reg_datardy_event(struct da9052_ts_priv *priv); +static ssize_t da9052_tsi_config_delay(struct da9052_ts_priv *priv, + enum TSI_DELAY delay); +static ssize_t da9052_tsi_config_measure_seq(struct da9052_ts_priv *priv, + enum TSI_MEASURE_SEQ seq); +static ssize_t da9052_tsi_config_state(struct da9052_ts_priv *ts, + enum TSI_STATE state); +static ssize_t da9052_tsi_set_sampling_mode(struct da9052_ts_priv *priv, + u8 interval); +static ssize_t da9052_tsi_config_skip_slots(struct da9052_ts_priv *priv, + enum TSI_SLOT_SKIP skip); +static ssize_t da9052_tsi_config_pen_detect(struct da9052_ts_priv *priv, + u8 flag); +static ssize_t da9052_tsi_disable_irq(struct da9052_ts_priv *priv, + enum TSI_IRQ tsi_irq); +static ssize_t da9052_tsi_enable_irq(struct da9052_ts_priv *priv, + enum TSI_IRQ tsi_irq); +static ssize_t da9052_tsi_config_manual_mode(struct da9052_ts_priv *priv, + u8 coordinate); +static ssize_t da9052_tsi_config_auto_mode(struct da9052_ts_priv *priv, + u8 state); +static ssize_t da9052_tsi_config_gpio(struct da9052_ts_priv *priv); +static ssize_t da9052_tsi_config_power_supply(struct da9052_ts_priv *priv, + u8 state); +static struct da9052_tsi_info *get_tsi_drvdata(void); +static void da9052_tsi_penup_event(struct da9052_ts_priv *priv); +static s32 da9052_tsi_get_rawdata(struct da9052_tsi_reg *buf, u8 cnt); +static ssize_t da9052_tsi_reg_proc_thread(void *ptr); +static ssize_t da9052_tsi_resume(struct platform_device *dev); +static ssize_t da9052_tsi_suspend(struct platform_device *dev, + pm_message_t state); +/* void tsi_reg_proc_work(struct work_struct *work); */ + +struct da9052_tsi tsi_reg; +struct da9052_tsi_info gda9052_tsi_info; + +static ssize_t write_da9052_reg(struct da9052 *da9052, u8 reg_addr, u8 data) +{ + ssize_t ret = 0; + struct da9052_ssc_msg ssc_msg; + + ssc_msg.addr = reg_addr; + ssc_msg.data = data; + ret = da9052->write(da9052, &ssc_msg); + if (ret) { + DA9052_DEBUG("%s: ", __func__); + DA9052_DEBUG("da9052_ssc_write Failed %d\n", ret); + } + + return ret; +} + +static ssize_t read_da9052_reg(struct da9052 *da9052, u8 reg_addr) +{ + ssize_t ret = 0; + struct da9052_ssc_msg ssc_msg; + + ssc_msg.addr = reg_addr; + ssc_msg.data = 0; + ret = da9052->read(da9052, &ssc_msg); + if (ret) { + DA9052_DEBUG("%s: ",__FUNCTION__); + DA9052_DEBUG("da9052_ssc_read Failed => %d\n" ,ret); + return -ret; + } + return ssc_msg.data; +} + +static struct da9052_tsi_info *get_tsi_drvdata(void) +{ + return &gda9052_tsi_info; +} + +static ssize_t da9052_tsi_config_measure_seq(struct da9052_ts_priv *priv, + enum TSI_MEASURE_SEQ seq) +{ + ssize_t ret = 0; + u8 data = 0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (seq > 1) + return -EINVAL; + + da9052_lock(priv->da9052); + ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG); + if (ret < 0) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("read_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + + data = (u8)ret; + + if (seq == XYZP_MODE) + data = enable_xyzp_mode(data); + else if (seq == XP_MODE) + data = enable_xp_mode(data); + else { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("Invalid Value passed \n" ); + da9052_unlock(priv->da9052); + return -EINVAL; + } + + ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG(" write_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + + ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data; + + return 0; +} + +static ssize_t da9052_tsi_set_sampling_mode(struct da9052_ts_priv *priv, + u8 mode) +{ + u8 data = 0; + ssize_t ret = 0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + da9052_lock(priv->da9052); + + ret = read_da9052_reg(priv->da9052, DA9052_ADCCONT_REG); + if (ret < 0) { + DA9052_DEBUG("DA9052_TSI:%s:", __FUNCTION__); + DA9052_DEBUG("read_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + data = (u8)ret; + + if (mode == ECONOMY_MODE) + data = adc_mode_economy_mode(data); + else if (mode == FAST_MODE) + data = adc_mode_fast_mode(data); + else { + DA9052_DEBUG("DA9052_TSI:%s:", __FUNCTION__); + DA9052_DEBUG("Invalid interval passed \n" ); + da9052_unlock(priv->da9052); + return -EINVAL; + } + + ret = write_da9052_reg(priv->da9052, DA9052_ADCCONT_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI:%s:", __FUNCTION__); + DA9052_DEBUG("write_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + + switch (mode) { + case ECONOMY_MODE: + priv->tsi_reg_data_poll_interval = + TSI_ECO_MODE_REG_DATA_PROCESSING_INTERVAL; + priv->tsi_raw_data_poll_interval = + TSI_ECO_MODE_RAW_DATA_PROCESSING_INTERVAL; + break; + case FAST_MODE: + priv->tsi_reg_data_poll_interval = + TSI_FAST_MODE_REG_DATA_PROCESSING_INTERVAL; + priv->tsi_raw_data_poll_interval = + TSI_FAST_MODE_RAW_DATA_PROCESSING_INTERVAL; + break; + default: + DA9052_DEBUG("DA9052_TSI:%s:", __FUNCTION__); + DA9052_DEBUG("Invalid interval passed \n" ); + return -EINVAL; + } + + ts->tsi_penup_count = + (u32)priv->tsi_pdata->pen_up_interval / + priv->tsi_reg_data_poll_interval; + + return 0; +} + +static ssize_t da9052_tsi_config_delay(struct da9052_ts_priv *priv, + enum TSI_DELAY delay) +{ + ssize_t ret = 0; + u8 data = 0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (delay > priv->tsi_pdata->max_tsi_delay) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG(" invalid value for tsi delay!!!\n" ); + return -EINVAL; + } + + da9052_lock(priv->da9052); + + ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG); + if(ret < 0) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("read_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + + data = clear_bits((u8)ret, DA9052_TSICONTA_TSIDELAY); + + data = set_bits(data, (delay << priv->tsi_pdata->tsi_delay_bit_shift)); + + ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG(" write_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + + ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data; + + return 0; +} + +ssize_t da9052_tsi_config_skip_slots(struct da9052_ts_priv *priv, + enum TSI_SLOT_SKIP skip) +{ + ssize_t ret = 0; + u8 data = 0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (skip > priv->tsi_pdata->max_tsi_skip_slot) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG(" invalid value for tsi skip slots!!!\n" ); + return -EINVAL; + } + + da9052_lock(priv->da9052); + + ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG); + if (ret < 0) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("read_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + + data = clear_bits((u8)ret, DA9052_TSICONTA_TSISKIP); + + data = set_bits(data, (skip << priv->tsi_pdata->tsi_skip_bit_shift)); + + ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI:da9052_tsi_config_skip_slots:"); + DA9052_DEBUG(" write_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + + ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data; + + return 0; +} + +static ssize_t da9052_tsi_config_state(struct da9052_ts_priv *priv, + enum TSI_STATE state) +{ + s32 ret; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (ts->tsi_conf.state == state) + return 0; + + switch (state) { + case TSI_AUTO_MODE: + ts->tsi_zero_data_cnt = 0; + priv->early_data_flag = TRUE; + priv->debounce_over = FALSE; + priv->win_reference_valid = FALSE; + + clean_tsi_fifos(priv); + + ret = da9052_tsi_config_auto_mode(priv, DISABLE); + if (ret) + return ret; + + ret = da9052_tsi_config_manual_mode(priv, DISABLE); + if (ret) + return ret; + + ret = da9052_tsi_config_power_supply(priv, DISABLE); + if (ret) + return ret; + + ret = da9052_tsi_enable_irq(priv, TSI_PEN_DWN); + if (ret) + return ret; + ts->tsi_conf.tsi_pendown_irq_mask = RESET; + + ret = da9052_tsi_disable_irq(priv, TSI_DATA_RDY); + if (ret) + return ret; + ts->tsi_conf.tsi_ready_irq_mask = SET; + + da9052_tsi_reg_pendwn_event(priv); + da9052_tsi_reg_datardy_event(priv); + + ret = da9052_tsi_config_pen_detect(priv, ENABLE); + if (ret) + return ret; + break; + + case TSI_IDLE: + ts->pen_dwn_event = RESET; + + ret = da9052_tsi_config_pen_detect(priv, DISABLE); + if (ret) + return ret; + + ret = da9052_tsi_config_auto_mode(priv, DISABLE); + if (ret) + return ret; + + ret = da9052_tsi_config_manual_mode(priv, DISABLE); + if (ret) + return ret; + + ret = da9052_tsi_config_power_supply(priv, DISABLE); + if (ret) + return ret; + + if (ts->pd_reg_status) { + priv->da9052->unregister_event_notifier(priv->da9052, + &priv->pd_nb); + ts->pd_reg_status = RESET; + } + break; + + default: + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG(" Invalid state passed"); + return -EINVAL; + } + + ts->tsi_conf.state = state; + + return 0; +} + +static void da9052_tsi_reg_pendwn_event(struct da9052_ts_priv *priv) +{ + ssize_t ret = 0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (ts->pd_reg_status) { + DA9052_DEBUG("%s: Pen down ",__FUNCTION__); + DA9052_DEBUG("Registeration is already done \n"); + return; + } + + priv->pd_nb.eve_type = PEN_DOWN_EVE; + priv->pd_nb.call_back = &da9052_tsi_pen_down_handler; + + ret = priv->da9052->register_event_notifier(priv->da9052, &priv->pd_nb); + if (ret) { + DA9052_DEBUG("%s: EH Registeration",__FUNCTION__); + DA9052_DEBUG(" Failed: ret = %d\n",ret ); + ts->pd_reg_status = RESET; + } else + ts->pd_reg_status = SET; + + priv->os_data_cnt = 0; + priv->raw_data_cnt = 0; + + return; +} + +static void da9052_tsi_reg_datardy_event(struct da9052_ts_priv *priv) +{ + ssize_t ret = 0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if(ts->datardy_reg_status) + { + DA9052_DEBUG("%s: Data Ready ",__FUNCTION__); + DA9052_DEBUG("Registeration is already done \n"); + return; + } + + priv->datardy_nb.eve_type = TSI_READY_EVE; + priv->datardy_nb.call_back = &da9052_tsi_data_ready_handler; + + ret = priv->da9052->register_event_notifier(priv->da9052, + &priv->datardy_nb); + + if(ret) + { + DA9052_DEBUG("%s: EH Registeration",__FUNCTION__); + DA9052_DEBUG(" Failed: ret = %d\n",ret ); + ts->datardy_reg_status = RESET; + } else + ts->datardy_reg_status = SET; + + return; +} + +static ssize_t __init da9052_tsi_create_input_dev(struct input_dev **ip_dev, + u8 n) +{ + u8 i; + s32 ret; + struct input_dev *dev = NULL; + + if (!n) + return -EINVAL; + + for (i = 0; i < n; i++) { + dev = input_allocate_device(); + if (!dev) { + DA9052_DEBUG(KERN_ERR "%s:%s():memory allocation for \ + inputdevice failed\n", __FILE__, + __FUNCTION__); + return -ENOMEM; + } + + ip_dev[i] = dev; + switch (i) { + case TSI_INPUT_DEVICE_OFF: + dev->name = DA9052_TSI_INPUT_DEV; + dev->phys = "input(tsi)"; + break; + default: + break; + } + } + dev->id.vendor = DA9052_VENDOR_ID; + dev->id.product = DA9052_PRODUCT_ID; + dev->id.bustype = BUS_RS232; + dev->id.version = TSI_VERSION; + dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); + dev->evbit[0] = (BIT_MASK(EV_SYN) | + BIT_MASK(EV_KEY) | + BIT_MASK(EV_ABS)); + + input_set_abs_params(dev, ABS_X, 0, DA9052_DISPLAY_X_MAX, 0, 0); + input_set_abs_params(dev, ABS_Y, 0, DA9052_DISPLAY_Y_MAX, 0, 0); + input_set_abs_params(dev, ABS_PRESSURE, 0, DA9052_TOUCH_PRESSURE_MAX, + 0, 0); + + ret = input_register_device(dev); + if (ret) { + DA9052_DEBUG(KERN_ERR "%s: Could ", __FUNCTION__); + DA9052_DEBUG("not register input device(touchscreen)!\n"); + ret = -EIO; + goto fail; + } + return 0; + +fail: + for (; i-- != 0; ) + input_free_device(ip_dev[i]); + return -EINVAL; +} + +static ssize_t __init da9052_tsi_init_drv(struct da9052_ts_priv *priv) +{ + u8 cnt = 0; + ssize_t ret = 0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if ((DA9052_GPIO_PIN_3 != DA9052_GPIO_CONFIG_TSI) || + (DA9052_GPIO_PIN_4 != DA9052_GPIO_CONFIG_TSI) || + (DA9052_GPIO_PIN_5 != DA9052_GPIO_CONFIG_TSI) || + (DA9052_GPIO_PIN_6 != DA9052_GPIO_CONFIG_TSI) || + (DA9052_GPIO_PIN_7 != DA9052_GPIO_CONFIG_TSI)) { + printk(KERN_ERR"DA9052_TSI: Configure DA9052 GPIO "); + printk(KERN_ERR"pins for TSI\n"); + return -EINVAL; + } + + ret = da9052_tsi_config_gpio(priv); + + ret = da9052_tsi_config_state(priv, TSI_IDLE); + ts->tsi_conf.state = TSI_IDLE; + + da9052_tsi_config_measure_seq(priv, TSI_MODE_VALUE); + + da9052_tsi_config_skip_slots(priv, TSI_SLOT_SKIP_VALUE); + + da9052_tsi_config_delay(priv, TSI_DELAY_VALUE); + + da9052_tsi_set_sampling_mode(priv, DEFAULT_TSI_SAMPLING_MODE); + + ts->tsi_calib = get_calib_config(); + + ret = da9052_tsi_create_input_dev(ts->input_devs, NUM_INPUT_DEVS); + if (ret) { + DA9052_DEBUG("DA9052_TSI: %s: ", __FUNCTION__); + DA9052_DEBUG("da9052_tsi_create_input_dev Failed \n" ); + return ret; + } + + da9052_init_tsi_fifos(priv); + + init_completion(&priv->tsi_reg_proc_thread.notifier); + priv->tsi_reg_proc_thread.state = ACTIVE; + priv->tsi_reg_proc_thread.pid = + kernel_thread(da9052_tsi_reg_proc_thread, + priv, CLONE_KERNEL | SIGCHLD); + + init_completion(&priv->tsi_raw_proc_thread.notifier); + priv->tsi_raw_proc_thread.state = ACTIVE; + priv->tsi_raw_proc_thread.pid = + kernel_thread(da9052_tsi_raw_proc_thread, + priv, CLONE_KERNEL | SIGCHLD); + + ret = da9052_tsi_config_state(priv, DEFAULT_TSI_STATE); + if (ret) { + for (cnt = 0; cnt < NUM_INPUT_DEVS; cnt++) { + if (ts->input_devs[cnt] != NULL) + input_free_device(ts->input_devs[cnt]); + } + } + + return 0; +} + +u32 da9052_tsi_get_input_dev(u8 off) +{ + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (off > NUM_INPUT_DEVS-1) + return -EINVAL; + + return (u32)ts->input_devs[off]; +} + +static ssize_t da9052_tsi_config_pen_detect(struct da9052_ts_priv *priv, + u8 flag) +{ + u8 data; + u32 ret; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + da9052_lock(priv->da9052); + ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG); + if (ret < 0) { + DA9052_DEBUG("%s:", __FUNCTION__); + DA9052_DEBUG(" read_da9052_reg Failed\n" ); + da9052_unlock(priv->da9052); + return ret; + } + + if (flag == ENABLE) + data = set_bits((u8)ret, DA9052_TSICONTA_PENDETEN); + else if (flag == DISABLE) + data = clear_bits((u8)ret, DA9052_TSICONTA_PENDETEN); + else { + DA9052_DEBUG("%s:", __FUNCTION__); + DA9052_DEBUG(" Invalid flag passed \n" ); + da9052_unlock(priv->da9052); + return -EINVAL; + } + + ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data); + if (ret < 0) { + DA9052_DEBUG("%s:", __FUNCTION__); + DA9052_DEBUG(" write_da9052_reg Failed\n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + + ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data; + return 0; +} + +static ssize_t da9052_tsi_disable_irq(struct da9052_ts_priv *priv, + enum TSI_IRQ tsi_irq) +{ + u8 data = 0; + ssize_t ret =0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + da9052_lock(priv->da9052); + ret = read_da9052_reg(priv->da9052, DA9052_IRQMASKB_REG); + if (ret < 0) { + DA9052_DEBUG("DA9052_TSI:da9052_tsi_disable_irq:"); + DA9052_DEBUG("read_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + data = ret; + switch (tsi_irq) { + case TSI_PEN_DWN: + data = mask_pendwn_irq(data); + break; + case TSI_DATA_RDY: + data = mask_tsi_rdy_irq(data); + break; + default: + DA9052_DEBUG("DA9052_TSI:da9052_tsi_disable_irq:"); + DA9052_DEBUG("Invalid IRQ passed \n" ); + da9052_unlock(priv->da9052); + return -EINVAL; + } + ret = write_da9052_reg(priv->da9052, DA9052_IRQMASKB_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI:da9052_tsi_disable_irq:"); + DA9052_DEBUG("write_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + switch (tsi_irq) { + case TSI_PEN_DWN: + ts->tsi_conf.tsi_pendown_irq_mask = SET; + break; + case TSI_DATA_RDY: + ts->tsi_conf.tsi_ready_irq_mask = SET; + break; + default: + return -EINVAL; + } + + return 0; + +} + +static ssize_t da9052_tsi_enable_irq(struct da9052_ts_priv *priv, + enum TSI_IRQ tsi_irq) +{ + u8 data =0; + ssize_t ret =0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + da9052_lock(priv->da9052); + ret = read_da9052_reg(priv->da9052, DA9052_IRQMASKB_REG); + if (ret < 0) { + DA9052_DEBUG("DA9052_TSI:da9052_tsi_enable_irq:"); + DA9052_DEBUG("read_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + + data = ret; + switch (tsi_irq) { + case TSI_PEN_DWN: + data = unmask_pendwn_irq(data); + break; + case TSI_DATA_RDY: + data = unmask_tsi_rdy_irq(data); + break; + default: + DA9052_DEBUG("DA9052_TSI:da9052_tsi_enable_irq:"); + DA9052_DEBUG("Invalid IRQ passed \n" ); + da9052_unlock(priv->da9052); + return -EINVAL; + } + ret = write_da9052_reg(priv->da9052, DA9052_IRQMASKB_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI:da9052_tsi_enable_irq:"); + DA9052_DEBUG("write_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + switch (tsi_irq) { + case TSI_PEN_DWN: + ts->tsi_conf.tsi_pendown_irq_mask = RESET; + break; + case TSI_DATA_RDY: + ts->tsi_conf.tsi_ready_irq_mask = RESET; + break; + default: + return -EINVAL; + } + + return 0; + } + +static ssize_t da9052_tsi_config_gpio(struct da9052_ts_priv *priv) +{ + u8 idx = 0; + ssize_t ret = 0; + struct da9052_ssc_msg ssc_msg[priv->tsi_pdata->num_gpio_tsi_register]; + + ssc_msg[idx++].addr = DA9052_GPIO0203_REG; + ssc_msg[idx++].addr = DA9052_GPIO0405_REG; + ssc_msg[idx++].addr = DA9052_GPIO0607_REG; + + da9052_lock(priv->da9052); + ret = priv->da9052->read_many(priv->da9052, ssc_msg,idx); + if (ret) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("da9052_ssc_read_many Failed\n" ); + da9052_unlock(priv->da9052); + return ret; + } + + idx = 0; + ssc_msg[idx].data = clear_bits(ssc_msg[idx].data, + DA9052_GPIO0203_GPIO3PIN); + idx++; + ssc_msg[idx].data = clear_bits(ssc_msg[idx].data, + (DA9052_GPIO0405_GPIO4PIN | DA9052_GPIO0405_GPIO5PIN)); + idx++; + ssc_msg[idx].data = clear_bits(ssc_msg[idx].data, + (DA9052_GPIO0607_GPIO6PIN | DA9052_GPIO0607_GPIO7PIN)); + idx++; + + ret = priv->da9052->write_many(priv->da9052, ssc_msg,idx); + if (ret) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("da9052_ssc_read_many Failed\n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + + return 0; +} + +s32 da9052_pm_configure_ldo(struct da9052_ts_priv *priv, + struct da9052_ldo_config ldo_config) +{ + struct da9052_ssc_msg msg; + u8 reg_num; + u8 ldo_volt; + u8 ldo_volt_bit = 0; + u8 ldo_conf_bit = 0; + u8 ldo_en_bit = 0; + s8 ldo_pd_bit = -1; + s32 ret = 0; + + DA9052_DEBUG("I am in function: %s\n", __FUNCTION__); + if (validate_ldo9_mV(ldo_config.ldo_volt)) + return INVALID_LDO9_VOLT_VALUE; + + ldo_volt = ldo9_mV_to_reg(ldo_config.ldo_volt); + + reg_num = DA9052_LDO9_REG; + ldo_volt_bit = DA9052_LDO9_VLDO9; + ldo_conf_bit = DA9052_LDO9_LDO9CONF; + ldo_en_bit = DA9052_LDO9_LDO9EN; + + da9052_lock(priv->da9052); + + msg.addr = reg_num; + + ret = priv->da9052->read(priv->da9052, &msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EINVAL; + } + msg.data = ldo_volt | + (ldo_config.ldo_conf ? ldo_conf_bit : 0) | + (msg.data & ldo_en_bit); + + ret = priv->da9052->write(priv->da9052, &msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EINVAL; + } + + if (-1 != ldo_pd_bit) { + msg.addr = DA9052_PULLDOWN_REG; + ret = priv->da9052->read(priv->da9052, &msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EINVAL; + } + + msg.data = (ldo_config.ldo_pd ? + set_bits(msg.data, ldo_pd_bit) : + clear_bits(msg.data, ldo_pd_bit)); + + ret = priv->da9052->write(priv->da9052, &msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EINVAL; + } + + } + da9052_unlock(priv->da9052); + + return 0; +} + + +s32 da9052_pm_set_ldo(struct da9052_ts_priv *priv, u8 ldo_num, u8 flag) +{ + struct da9052_ssc_msg msg; + u8 reg_num = 0; + u8 value = 0; + s32 ret = 0; + + DA9052_DEBUG("I am in function: %s\n", __FUNCTION__); + + reg_num = DA9052_LDO9_REG; + value = DA9052_LDO9_LDO9EN; + da9052_lock(priv->da9052); + + msg.addr = reg_num; + + ret = priv->da9052->read(priv->da9052, &msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EINVAL; + } + + msg.data = flag ? + set_bits(msg.data, value) : + clear_bits(msg.data, value); + + ret = priv->da9052->write(priv->da9052, &msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EINVAL; + } + + da9052_unlock(priv->da9052); + + return 0; +} + +static ssize_t da9052_tsi_config_power_supply(struct da9052_ts_priv *priv, + u8 state) +{ + struct da9052_ldo_config ldo_config; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (state != ENABLE && state != DISABLE) { + DA9052_DEBUG("DA9052_TSI: %s: ", __FUNCTION__); + DA9052_DEBUG("Invalid state Passed\n" ); + return -EINVAL; + } + + ldo_config.ldo_volt = priv->tsi_pdata->tsi_supply_voltage; + ldo_config.ldo_num = priv->tsi_pdata->tsi_ref_source; + ldo_config.ldo_conf = RESET; + + if (da9052_pm_configure_ldo(priv, ldo_config)) + return -EINVAL; + + if (da9052_pm_set_ldo(priv, priv->tsi_pdata->tsi_ref_source, state)) + return -EINVAL; + + if (state == ENABLE) + ts->tsi_conf.ldo9_en = SET; + else + ts->tsi_conf.ldo9_en = RESET; + + return 0; +} + +static ssize_t da9052_tsi_config_auto_mode(struct da9052_ts_priv *priv, + u8 state) +{ + u8 data; + s32 ret = 0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (state != ENABLE && state != DISABLE) + return -EINVAL; + + da9052_lock(priv->da9052); + + ret = read_da9052_reg(priv->da9052, DA9052_TSICONTA_REG); + if (ret < 0) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("read_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + + data = (u8)ret; + + if (state == ENABLE) + data = set_auto_tsi_en(data); + else if (state == DISABLE) + data = reset_auto_tsi_en(data); + else { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("Invalid Parameter Passed \n" ); + da9052_unlock(priv->da9052); + return -EINVAL; + } + + ret = write_da9052_reg(priv->da9052, DA9052_TSICONTA_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG(" Failed to configure Auto TSI mode\n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + ts->tsi_conf.auto_cont.da9052_tsi_cont_a = data; + return 0; +} + +static ssize_t da9052_tsi_config_manual_mode(struct da9052_ts_priv *priv, + u8 state) +{ + u8 data = 0; + ssize_t ret=0; + struct da9052_tsi_info *ts = get_tsi_drvdata(); + + if (state != ENABLE && state != DISABLE) { + DA9052_DEBUG("DA9052_TSI: %s: ", __FUNCTION__); + DA9052_DEBUG("Invalid state Passed\n" ); + return -EINVAL; + } + + da9052_lock(priv->da9052); + + ret = read_da9052_reg(priv->da9052, DA9052_TSICONTB_REG); + if (ret < 0) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("read_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + + data = (u8)ret; + if (state == DISABLE) + data = disable_tsi_manual_mode(data); + else + data = enable_tsi_manual_mode(data); + + ret = write_da9052_reg(priv->da9052, DA9052_TSICONTB_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("write_da9052_reg Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + + if (state == DISABLE) + ts->tsi_conf.man_cont.tsi_cont_b.tsi_man = RESET; + else + ts->tsi_conf.man_cont.tsi_cont_b.tsi_man = SET; + + data = 0; + data = set_bits(data, DA9052_ADC_TSI); + + ret = write_da9052_reg(priv->da9052, DA9052_ADCMAN_REG, data); + if (ret) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG("ADC write Failed \n" ); + da9052_unlock(priv->da9052); + return ret; + } + da9052_unlock(priv->da9052); + + return 0; +} + +static u32 da9052_tsi_get_reg_data(struct da9052_ts_priv *priv) +{ + u32 free_cnt, copy_cnt, cnt; + + if (down_interruptible(&priv->tsi_reg_fifo.lock)) + return 0; + + copy_cnt = 0; + + if ((priv->tsi_reg_fifo.head - priv->tsi_reg_fifo.tail) > 1) { + free_cnt = get_reg_free_space_cnt(priv); + if (free_cnt > TSI_POLL_SAMPLE_CNT) + free_cnt = TSI_POLL_SAMPLE_CNT; + + cnt = da9052_tsi_get_rawdata( + &priv->tsi_reg_fifo.data[priv->tsi_reg_fifo.tail], + free_cnt); + + if (cnt > free_cnt) { + DA9052_DEBUG("EH copied more data"); + return -EINVAL; + } + + copy_cnt = cnt; + + while (cnt--) + incr_with_wrap_reg_fifo(priv->tsi_reg_fifo.tail); + + } else if ((priv->tsi_reg_fifo.head - priv->tsi_reg_fifo.tail) <= 0) { + + free_cnt = (TSI_REG_DATA_BUF_SIZE - priv->tsi_reg_fifo.tail); + if (free_cnt > TSI_POLL_SAMPLE_CNT) { + free_cnt = TSI_POLL_SAMPLE_CNT; + + cnt = da9052_tsi_get_rawdata( + &priv->tsi_reg_fifo.data[priv->tsi_reg_fifo.tail], + free_cnt); + if (cnt > free_cnt) { + DA9052_DEBUG("EH copied more data"); + return -EINVAL; + } + copy_cnt = cnt; + + while (cnt--) + incr_with_wrap_reg_fifo( + priv->tsi_reg_fifo.tail); + } else { + if (free_cnt) { + cnt = da9052_tsi_get_rawdata( + &priv-> + tsi_reg_fifo.data[priv-> + tsi_reg_fifo.tail], + free_cnt + ); + if (cnt > free_cnt) { + DA9052_DEBUG("EH copied more data"); + return -EINVAL; + } + copy_cnt = cnt; + while (cnt--) + incr_with_wrap_reg_fifo( + priv->tsi_reg_fifo.tail); + } + free_cnt = priv->tsi_reg_fifo.head; + if (free_cnt > TSI_POLL_SAMPLE_CNT - copy_cnt) + free_cnt = TSI_POLL_SAMPLE_CNT - copy_cnt; + if (free_cnt) { + cnt = da9052_tsi_get_rawdata( + &priv->tsi_reg_fifo.data[priv-> + tsi_reg_fifo.tail], free_cnt + ); + if (cnt > free_cnt) { + DA9052_DEBUG("EH copied more data"); + return -EINVAL; + } + + copy_cnt += cnt; + + while (cnt--) + incr_with_wrap_reg_fifo( + priv->tsi_reg_fifo.tail); + } + } + } else + copy_cnt = 0; + + up(&priv->tsi_reg_fifo.lock); + + return copy_cnt; +} + + +static ssize_t da9052_tsi_reg_proc_thread(void *ptr) +{ + u32 data_cnt; + struct da9052_tsi_info *ts; + struct da9052_ts_priv *priv = (struct da9052_ts_priv *)ptr; + + set_freezable(); + + while (priv->tsi_reg_proc_thread.state == ACTIVE) { + + try_to_freeze(); + + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(msecs_to_jiffies(priv-> + tsi_reg_data_poll_interval)); + + ts = get_tsi_drvdata(); + + if (!ts->pen_dwn_event) + continue; + + data_cnt = da9052_tsi_get_reg_data(priv); + + da9052_tsi_process_reg_data(priv); + + if (data_cnt) + ts->tsi_zero_data_cnt = 0; + else { + if ((++(ts->tsi_zero_data_cnt)) > + ts->tsi_penup_count) { + ts->pen_dwn_event = RESET; + da9052_tsi_penup_event(priv); + } + } + } + + complete_and_exit(&priv->tsi_reg_proc_thread.notifier, 0); + return 0; +} + + +static void da9052_tsi_penup_event(struct da9052_ts_priv *priv) +{ + + struct da9052_tsi_info *ts = get_tsi_drvdata(); + struct input_dev *ip_dev = + (struct input_dev *)da9052_tsi_get_input_dev( + (u8)TSI_INPUT_DEVICE_OFF); + + if (da9052_tsi_config_auto_mode(priv, DISABLE)) + goto exit; + + ts->tsi_conf.auto_cont.tsi_cont_a.auto_tsi_en = RESET; + + if (da9052_tsi_config_power_supply(priv, ENABLE)) + goto exit; + + ts->tsi_conf.ldo9_en = RESET; + + if (da9052_tsi_enable_irq(priv, TSI_PEN_DWN)) + goto exit; + + ts->tsi_conf.tsi_pendown_irq_mask = RESET; + + tsi_reg.tsi_state = WAIT_FOR_PEN_DOWN; + + ts->tsi_zero_data_cnt = 0; + priv->early_data_flag = TRUE; + priv->debounce_over = FALSE; + priv->win_reference_valid = FALSE; + + printk(KERN_INFO "The raw data count is %d \n", priv->raw_data_cnt); + printk(KERN_INFO "The OS data count is %d \n", priv->os_data_cnt); + printk(KERN_INFO "PEN UP DECLARED \n"); + input_report_abs(ip_dev, BTN_TOUCH, 0); + input_sync(ip_dev); + priv->os_data_cnt = 0; + priv->raw_data_cnt = 0; + +exit: + clean_tsi_fifos(priv); + return; +} + +void da9052_tsi_pen_down_handler(struct da9052_eh_nb *eh_data, u32 event) +{ + ssize_t ret = 0; + struct da9052_ts_priv *priv = + container_of(eh_data, struct da9052_ts_priv, pd_nb); + struct da9052_tsi_info *ts = get_tsi_drvdata(); + struct input_dev *ip_dev = + (struct input_dev*)da9052_tsi_get_input_dev( + (u8)TSI_INPUT_DEVICE_OFF); + + if (tsi_reg.tsi_state != WAIT_FOR_PEN_DOWN) + return; + DA9052_DEBUG("EH notified the pendown event 0x%x\n", event); + + tsi_reg.tsi_state = WAIT_FOR_SAMPLING; + + if (ts->tsi_conf.state != TSI_AUTO_MODE) { + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG(" Configure TSI to auto mode.\n" ); + DA9052_DEBUG("DA9052_TSI: %s:", __FUNCTION__); + DA9052_DEBUG(" Then call this API.\n" ); + goto fail; + } + + if (da9052_tsi_config_power_supply(priv, ENABLE)) + goto fail; + + if (da9052_tsi_disable_irq(priv, TSI_PEN_DWN)) + goto fail; + + if (da9052_tsi_enable_irq(priv, TSI_DATA_RDY)) + goto fail; + + if (da9052_tsi_config_auto_mode(priv, ENABLE)) + goto fail; + ts->tsi_conf.auto_cont.tsi_cont_a.auto_tsi_en = SET; + + input_sync(ip_dev); + + ts->tsi_rdy_event = (DA9052_EVENTB_ETSIREADY & (event>>8)); + ts->pen_dwn_event = (DA9052_EVENTB_EPENDOWN & (event>>8)); + + tsi_reg.tsi_state = SAMPLING_ACTIVE; + + goto success; + +fail: + if (ts->pd_reg_status) { + priv->da9052->unregister_event_notifier(priv->da9052, + &priv->pd_nb); + ts->pd_reg_status = RESET; + + priv->da9052->register_event_notifier(priv->da9052, + &priv->datardy_nb); + da9052_tsi_reg_pendwn_event(priv); + } + +success: + ret = 0; + printk(KERN_INFO "Exiting PEN DOWN HANDLER \n"); +} + +void da9052_tsi_data_ready_handler(struct da9052_eh_nb *eh_data, u32 event) +{ + struct da9052_ssc_msg tsi_data[4]; + s32 ret; + struct da9052_ts_priv *priv = + container_of(eh_data, struct da9052_ts_priv, datardy_nb); + + if (tsi_reg.tsi_state != SAMPLING_ACTIVE) + return; + + tsi_data[0].addr = DA9052_TSIXMSB_REG; + tsi_data[1].addr = DA9052_TSIYMSB_REG; + tsi_data[2].addr = DA9052_TSILSB_REG; + tsi_data[3].addr = DA9052_TSIZMSB_REG; + + tsi_data[0].data = 0; + tsi_data[1].data = 0; + tsi_data[2].data = 0; + tsi_data[3].data = 0; + + da9052_lock(priv->da9052); + + ret = priv->da9052->read_many(priv->da9052, tsi_data, 4); + if (ret) { + DA9052_DEBUG("Error in reading TSI data \n" ); + da9052_unlock(priv->da9052); + return; + } + da9052_unlock(priv->da9052); + + mutex_lock(&tsi_reg.tsi_fifo_lock); + + tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_end].x_msb = tsi_data[0].data; + tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_end].y_msb = tsi_data[1].data; + tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_end].lsb = tsi_data[2].data; + tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_end].z_msb = tsi_data[3].data; + incr_with_wrap(tsi_reg.tsi_fifo_end); + + if (tsi_reg.tsi_fifo_end == tsi_reg.tsi_fifo_start) + tsi_reg.tsi_fifo_start++; + + mutex_unlock(&tsi_reg.tsi_fifo_lock); + +} + +static s32 da9052_tsi_get_rawdata(struct da9052_tsi_reg *buf, u8 cnt) { + u32 data_cnt = 0; + u32 rem_data_cnt = 0; + + mutex_lock(&tsi_reg.tsi_fifo_lock); + + if (tsi_reg.tsi_fifo_start < tsi_reg.tsi_fifo_end) { + data_cnt = (tsi_reg.tsi_fifo_end - tsi_reg.tsi_fifo_start); + + if (cnt < data_cnt) + data_cnt = cnt; + + memcpy(buf, &tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_start], + sizeof(struct da9052_tsi_reg) * data_cnt); + + tsi_reg.tsi_fifo_start += data_cnt; + + if (tsi_reg.tsi_fifo_start == tsi_reg.tsi_fifo_end) { + tsi_reg.tsi_fifo_start = 0; + tsi_reg.tsi_fifo_end = 0; + } + } else if (tsi_reg.tsi_fifo_start > tsi_reg.tsi_fifo_end) { + data_cnt = ((TSI_FIFO_SIZE - tsi_reg.tsi_fifo_start) + + tsi_reg.tsi_fifo_end); + + if (cnt < data_cnt) + data_cnt = cnt; + + if (data_cnt <= (TSI_FIFO_SIZE - tsi_reg.tsi_fifo_start)) { + memcpy(buf, &tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_start], + sizeof(struct da9052_tsi_reg) * data_cnt); + + tsi_reg.tsi_fifo_start += data_cnt; + if (tsi_reg.tsi_fifo_start >= TSI_FIFO_SIZE) + tsi_reg.tsi_fifo_start = 0; + } else { + memcpy(buf, &tsi_reg.tsi_fifo[tsi_reg.tsi_fifo_start], + sizeof(struct da9052_tsi_reg) + * (TSI_FIFO_SIZE - tsi_reg.tsi_fifo_start)); + + rem_data_cnt = (data_cnt - + (TSI_FIFO_SIZE - tsi_reg.tsi_fifo_start)); + + memcpy(buf, &tsi_reg.tsi_fifo[0], + sizeof(struct da9052_tsi_reg) * rem_data_cnt); + + tsi_reg.tsi_fifo_start = rem_data_cnt; + } + + if (tsi_reg.tsi_fifo_start == tsi_reg.tsi_fifo_end) { + tsi_reg.tsi_fifo_start = 0; + tsi_reg.tsi_fifo_end = 0; + } + } else + data_cnt = 0; + + mutex_unlock(&tsi_reg.tsi_fifo_lock); + + return data_cnt; +} + +static ssize_t da9052_tsi_suspend(struct platform_device *dev, + pm_message_t state) +{ + printk(KERN_INFO "%s: called\n", __FUNCTION__); + return 0; +} + +static ssize_t da9052_tsi_resume(struct platform_device *dev) +{ + printk(KERN_INFO "%s: called\n", __FUNCTION__); + return 0; +} + +static s32 __devinit da9052_tsi_probe(struct platform_device *pdev) +{ + + struct da9052_ts_priv *priv; + struct da9052_tsi_platform_data *pdata = pdev->dev.platform_data; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->da9052 = dev_get_drvdata(pdev->dev.parent); + platform_set_drvdata(pdev, priv); + + priv->tsi_pdata = pdata; + + if (da9052_tsi_init_drv(priv)) + return -EFAULT; + + mutex_init(&tsi_reg.tsi_fifo_lock); + tsi_reg.tsi_state = WAIT_FOR_PEN_DOWN; + + printk(KERN_INFO "TSI Drv Successfully Inserted %s\n", + DA9052_TSI_DEVICE_NAME); + return 0; +} + +static int __devexit da9052_tsi_remove(struct platform_device *pdev) +{ + struct da9052_ts_priv *priv = platform_get_drvdata(pdev); + struct da9052_tsi_info *ts = get_tsi_drvdata(); + s32 ret = 0, i = 0; + + ret = da9052_tsi_config_state(priv, TSI_IDLE); + if (!ret) + return -EINVAL; + + if (ts->pd_reg_status) { + priv->da9052->unregister_event_notifier(priv->da9052, + &priv->pd_nb); + ts->pd_reg_status = RESET; + } + + if (ts->datardy_reg_status) { + priv->da9052->unregister_event_notifier(priv->da9052, + &priv->datardy_nb); + ts->datardy_reg_status = RESET; + } + + mutex_destroy(&tsi_reg.tsi_fifo_lock); + + priv->tsi_reg_proc_thread.state = INACTIVE; + wait_for_completion(&priv->tsi_reg_proc_thread.notifier); + + priv->tsi_raw_proc_thread.state = INACTIVE; + wait_for_completion(&priv->tsi_raw_proc_thread.notifier); + + for (i = 0; i < NUM_INPUT_DEVS; i++) { + input_unregister_device(ts->input_devs[i]); + } + + platform_set_drvdata(pdev, NULL); + DA9052_DEBUG(KERN_DEBUG "Removing %s \n", DA9052_TSI_DEVICE_NAME); + + return 0; +} + +static struct platform_driver da9052_tsi_driver = { + .probe = da9052_tsi_probe, + .remove = __devexit_p(da9052_tsi_remove), + .suspend = da9052_tsi_suspend, + .resume = da9052_tsi_resume, + .driver = { + .name = DA9052_TSI_DEVICE_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init da9052_tsi_init(void) +{ + printk("DA9052 TSI Device Driver, v1.0\n"); + return platform_driver_register(&da9052_tsi_driver); +} +module_init(da9052_tsi_init); + +static void __exit da9052_tsi_exit(void) +{ + printk(KERN_ERR "TSI Driver %s Successfully Removed \n", + DA9052_TSI_DEVICE_NAME); + return; + +} +module_exit(da9052_tsi_exit); + +MODULE_DESCRIPTION("Touchscreen driver for Dialog Semiconductor DA9052"); +MODULE_AUTHOR("Dialog Semiconductor Ltd "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/input/touchscreen/da9052_tsi_calibrate.c b/drivers/input/touchscreen/da9052_tsi_calibrate.c new file mode 100644 index 000000000000..4ffd0bbe7483 --- /dev/null +++ b/drivers/input/touchscreen/da9052_tsi_calibrate.c @@ -0,0 +1,107 @@ +/* + * da9052_tsi_calibrate.c -- TSI Calibration driver for Dialog DA9052 + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * Author: Dialog Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include + +static struct Calib_xform_matrix_t xform = { + .An = DA9052_TSI_CALIB_AN, + .Bn = DA9052_TSI_CALIB_BN, + .Cn = DA9052_TSI_CALIB_CN, + .Dn = DA9052_TSI_CALIB_DN, + .En = DA9052_TSI_CALIB_EN, + .Fn = DA9052_TSI_CALIB_FN, + .Divider = DA9052_TSI_CALIB_DIVIDER +}; + +static struct calib_cfg_t calib = { + .calibrate_flag = TSI_USE_CALIBRATION, +}; + +struct calib_cfg_t *get_calib_config(void) +{ + return &calib; +} + +ssize_t da9052_tsi_set_calib_matrix(struct da9052_tsi_data *displayPtr, + struct da9052_tsi_data *screenPtr) +{ + + int retValue = SUCCESS ; + + xform.Divider = ((screenPtr[0].x - screenPtr[1].x) + * (screenPtr[1].y - screenPtr[2].y)) + - ((screenPtr[1].x - screenPtr[2].x) + * (screenPtr[0].y - screenPtr[1].y)); + + if (xform.Divider == 0) + retValue = -FAILURE; + else { + xform.An = ((displayPtr[0].x - displayPtr[1].x) + * (screenPtr[1].y - screenPtr[2].y)) + - ((displayPtr[1].x - displayPtr[2].x) + * (screenPtr[0].y - screenPtr[1].y)); + + xform.Bn = ((displayPtr[1].x - displayPtr[2].x) + * (screenPtr[0].x - screenPtr[1].x)) + - ((screenPtr[1].x - screenPtr[2].x) + * (displayPtr[0].x - displayPtr[1].x)); + + xform.Cn = (displayPtr[0].x * xform.Divider) + - (screenPtr[0].x * xform.An) + - (screenPtr[0].y * xform.Bn); + + xform.Dn = ((displayPtr[0].y - displayPtr[1].y) + * (screenPtr[1].y - screenPtr[2].y)) + - ((displayPtr[1].y - displayPtr[2].y) + * (screenPtr[0].y - screenPtr[1].y)); + + xform.En = ((displayPtr[1].y - displayPtr[2].y) + * (screenPtr[0].x - screenPtr[1].x)) + - ((screenPtr[1].x - screenPtr[2].x) + * (displayPtr[0].y - displayPtr[1].y)); + + xform.Fn = (displayPtr[0].y * xform.Divider) + - (screenPtr[0].x * xform.Dn) + - (screenPtr[0].y * xform.En); + } + + return retValue; +} + +ssize_t da9052_tsi_get_calib_display_point(struct da9052_tsi_data *displayPtr) +{ + int retValue = TRUE; + struct da9052_tsi_data screen_coord; + + screen_coord = *displayPtr; + if (xform.Divider != 0) { + displayPtr->x = ((xform.An * screen_coord.x) + + (xform.Bn * screen_coord.y) + + xform.Cn + ) / xform.Divider; + + displayPtr->y = ((xform.Dn * screen_coord.x) + + (xform.En * screen_coord.y) + + xform.Fn + ) / xform.Divider; + } else + retValue = FALSE; + +#if DA9052_TSI_CALIB_DATA_PROFILING + printk("C\tX\t%4d\tY\t%4d\n", + displayPtr->x, + displayPtr->y); +#endif + return retValue; +} diff --git a/drivers/input/touchscreen/da9052_tsi_filter.c b/drivers/input/touchscreen/da9052_tsi_filter.c new file mode 100644 index 000000000000..16467edf386f --- /dev/null +++ b/drivers/input/touchscreen/da9052_tsi_filter.c @@ -0,0 +1,489 @@ +/* + * da9052_tsi_filter.c -- TSI filter driver for Dialog DA9052 + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * Author: Dialog Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include + +#define get_abs(x) (x < 0 ? ((-1) * x) : (x)) + +#define WITHIN_WINDOW(x, y) ((get_abs(x) <= TSI_X_WINDOW_SIZE) && \ + (get_abs(y) <= TSI_Y_WINDOW_SIZE)) + +#define FIRST_SAMPLE 0 + +#define incr_with_wrap_raw_fifo(x) \ + if (++x >= TSI_RAW_DATA_BUF_SIZE) \ + x = 0 + +#define decr_with_wrap_raw_fifo(x) \ + if (--x < 0) \ + x = (TSI_RAW_DATA_BUF_SIZE-1) + +static u32 get_raw_data_cnt(struct da9052_ts_priv *priv); +static void da9052_tsi_convert_reg_to_coord(struct da9052_ts_priv *priv, + struct da9052_tsi_data *raw_data); +static inline void clean_tsi_reg_fifo(struct da9052_ts_priv *priv); +static inline void clean_tsi_raw_fifo(struct da9052_ts_priv *priv); + +#if (ENABLE_AVERAGE_FILTER) +static void da9052_tsi_avrg_filter(struct da9052_ts_priv *priv, + struct da9052_tsi_data *tsi_avg_data); + +#endif +#if (ENABLE_TSI_DEBOUNCE) +static s32 da9052_tsi_calc_debounce_data(struct da9052_ts_priv *priv, + struct da9052_tsi_data *raw_data); + +#endif +# if (ENABLE_WINDOW_FILTER) +static s32 diff_within_window(struct da9052_tsi_data *prev_raw_data, + struct da9052_tsi_data *cur_raw_data); +#endif +static s32 da9052_tsi_window_filter(struct da9052_ts_priv *ts, + struct da9052_tsi_data *raw_data); + +void clean_tsi_fifos(struct da9052_ts_priv *priv) +{ + clean_tsi_raw_fifo(priv); + clean_tsi_reg_fifo(priv); +} + +void __init da9052_init_tsi_fifos(struct da9052_ts_priv *priv) +{ + init_MUTEX(&priv->tsi_raw_fifo.lock); + init_MUTEX(&priv->tsi_reg_fifo.lock); + + clean_tsi_raw_fifo(priv); + clean_tsi_reg_fifo(priv); +} + +u32 get_reg_data_cnt(struct da9052_ts_priv *priv) +{ + u8 reg_data_cnt; + + if (priv->tsi_reg_fifo.head <= priv->tsi_reg_fifo.tail) { + reg_data_cnt = (priv->tsi_reg_fifo.tail - + priv->tsi_reg_fifo.head); + } else { + reg_data_cnt = (priv->tsi_reg_fifo.tail + + (TSI_REG_DATA_BUF_SIZE - + priv->tsi_reg_fifo.head)); + } + + return reg_data_cnt; +} + +u32 get_reg_free_space_cnt(struct da9052_ts_priv *priv) +{ + u32 free_cnt; + + if (priv->tsi_reg_fifo.head <= priv->tsi_reg_fifo.tail) { + free_cnt = ((TSI_REG_DATA_BUF_SIZE - 1) - + (priv->tsi_reg_fifo.tail - priv->tsi_reg_fifo.head)); + } else + free_cnt = ((priv->tsi_reg_fifo.head - priv->tsi_reg_fifo.tail) + - 1); + + return free_cnt; +} + +void da9052_tsi_process_reg_data(struct da9052_ts_priv *priv) +{ + s32 ret; + struct da9052_tsi_data tmp_raw_data; + u32 reg_data_cnt; + + if (down_interruptible(&priv->tsi_reg_fifo.lock)) + return; + + reg_data_cnt = get_reg_data_cnt(priv); + + while (reg_data_cnt-- > 0) { + + ret = 0; + + if (get_raw_data_cnt(priv) >= (TSI_RAW_DATA_BUF_SIZE - 1)) { + DA9052_DEBUG("%s: RAW data FIFO is full\n", + __FUNCTION__); + break; + } + + da9052_tsi_convert_reg_to_coord(priv, &tmp_raw_data); + + if ((tmp_raw_data.x < TS_X_MIN) || + (tmp_raw_data.x > TS_X_MAX) || + (tmp_raw_data.y < TS_Y_MIN) || + (tmp_raw_data.y > TS_Y_MAX)) { + DA9052_DEBUG("%s: ", __FUNCTION__); + DA9052_DEBUG("sample beyond touchscreen panel "); + DA9052_DEBUG("dimensions\n"); + continue; + } + +#if (ENABLE_TSI_DEBOUNCE) + if (debounce_over == FALSE) { + ret = + da9052_tsi_calc_debounce_data(priv, &tmp_raw_data); + if (ret != SUCCESS) + continue; + } +#endif + +# if (ENABLE_WINDOW_FILTER) + ret = da9052_tsi_window_filter(priv, &tmp_raw_data); + if (ret != SUCCESS) + continue; +#endif + priv->early_data_flag = FALSE; + + if (down_interruptible(&priv->tsi_raw_fifo.lock)) { + DA9052_DEBUG("%s: Failed to ", __FUNCTION__); + DA9052_DEBUG("acquire RAW FIFO Lock!\n"); + + up(&priv->tsi_reg_fifo.lock); + return; + } + + priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.tail] = tmp_raw_data; + incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.tail); + + up(&priv->tsi_raw_fifo.lock); + } + + + up(&priv->tsi_reg_fifo.lock); + + return; +} + +static u32 get_raw_data_cnt(struct da9052_ts_priv *priv) +{ + u32 raw_data_cnt; + + if (priv->tsi_raw_fifo.head <= priv->tsi_raw_fifo.tail) + raw_data_cnt = + (priv->tsi_raw_fifo.tail - priv->tsi_raw_fifo.head); + else + raw_data_cnt = + (priv->tsi_raw_fifo.tail + (TSI_RAW_DATA_BUF_SIZE - + priv->tsi_raw_fifo.head)); + + return raw_data_cnt; +} + +static void da9052_tsi_convert_reg_to_coord(struct da9052_ts_priv *priv, + struct da9052_tsi_data *raw_data) +{ + + struct da9052_tsi_reg *src; + struct da9052_tsi_data *dst = raw_data; + + src = &priv->tsi_reg_fifo.data[priv->tsi_reg_fifo.head]; + + dst->x = (src->x_msb << X_MSB_SHIFT); + dst->x |= (src->lsb & X_LSB_MASK) >> X_LSB_SHIFT; + + dst->y = (src->y_msb << Y_MSB_SHIFT); + dst->y |= (src->lsb & Y_LSB_MASK) >> Y_LSB_SHIFT; + + dst->z = (src->z_msb << Z_MSB_SHIFT); + dst->z |= (src->lsb & Z_LSB_MASK) >> Z_LSB_SHIFT; + +#if DA9052_TSI_RAW_DATA_PROFILING + printk("R\tX\t%4d\tY\t%4d\tZ\t%4d\n", + (u16)dst->x, + (u16)dst->y, + (u16)dst->z); +#endif + priv->raw_data_cnt++; + incr_with_wrap_reg_fifo(priv->tsi_reg_fifo.head); +} + +#if (ENABLE_AVERAGE_FILTER) +static void da9052_tsi_avrg_filter(struct da9052_ts_priv *priv, + struct da9052_tsi_data *tsi_avg_data) +{ + u8 cnt; + + if (down_interruptible(&priv->tsi_raw_fifo.lock)) { + printk("%s: No RAW Lock !\n", __FUNCTION__); + return; + } + + (*tsi_avg_data) = priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head]; + incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.head); + + for (cnt = 2; cnt <= TSI_AVERAGE_FILTER_SIZE; cnt++) { + + tsi_avg_data->x += + priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].x; + tsi_avg_data->y += + priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].y; + tsi_avg_data->z += + priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].z; + + incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.head); + } + + up(&priv->tsi_raw_fifo.lock); + + tsi_avg_data->x /= TSI_AVERAGE_FILTER_SIZE; + tsi_avg_data->y /= TSI_AVERAGE_FILTER_SIZE; + tsi_avg_data->z /= TSI_AVERAGE_FILTER_SIZE; + +#if DA9052_TSI_AVG_FLT_DATA_PROFILING + printk("A\tX\t%4d\tY\t%4d\tZ\t%4d\n", + (u16)tsi_avg_data->x, + (u16)tsi_avg_data->y, + (u16)tsi_avg_data->z); +#endif + + return; +} +#endif + +s32 da9052_tsi_raw_proc_thread(void *ptr) +{ + struct da9052_tsi_data coord; + u8 calib_ok, range_ok; + struct calib_cfg_t *tsi_calib = get_calib_config(); + struct input_dev *ip_dev = (struct input_dev *) + da9052_tsi_get_input_dev( + (u8)TSI_INPUT_DEVICE_OFF); + struct da9052_ts_priv *priv = (struct da9052_ts_priv *)ptr; + + set_freezable(); + + while (priv->tsi_raw_proc_thread.state == ACTIVE) { + + try_to_freeze(); + + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout( + msecs_to_jiffies(priv->tsi_raw_data_poll_interval)); + + if (priv->early_data_flag || (get_raw_data_cnt(priv) == 0)) + continue; + + calib_ok = TRUE; + range_ok = TRUE; + +#if (ENABLE_AVERAGE_FILTER) + + if (get_raw_data_cnt(priv) < TSI_AVERAGE_FILTER_SIZE) + continue; + + da9052_tsi_avrg_filter(priv, &coord); + +#else + + if (down_interruptible(&priv->tsi_raw_fifo.lock)) + continue; + + coord = priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head]; + incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.head); + + up(&priv->tsi_raw_fifo.lock); + +#endif + + if (tsi_calib->calibrate_flag) { + calib_ok = da9052_tsi_get_calib_display_point(&coord); + + if ((coord.x < DISPLAY_X_MIN) || + (coord.x > DISPLAY_X_MAX) || + (coord.y < DISPLAY_Y_MIN) || + (coord.y > DISPLAY_Y_MAX)) + range_ok = FALSE; + } + + if (calib_ok && range_ok) { + input_report_abs(ip_dev, BTN_TOUCH, 1); + input_report_abs(ip_dev, ABS_X, coord.x); + input_report_abs(ip_dev, ABS_Y, coord.y); + input_sync(ip_dev); + + priv->os_data_cnt++; + +#if DA9052_TSI_OS_DATA_PROFILING + printk("O\tX\t%4d\tY\t%4d\tZ\t%4d\n", (u16)coord.x, + (u16)coord.y, (u16)coord.z); +#endif + } else { + if (!calib_ok) { + DA9052_DEBUG("%s: ", __FUNCTION__); + DA9052_DEBUG("calibration Failed\n"); + } + if (!range_ok) { + DA9052_DEBUG("%s: ", __FUNCTION__); + DA9052_DEBUG("sample beyond display "); + DA9052_DEBUG("panel dimension\n"); + } + } + } + priv->tsi_raw_proc_thread.thread_task = NULL; + complete_and_exit(&priv->tsi_raw_proc_thread.notifier, 0); + return 0; + +} + +#if (ENABLE_TSI_DEBOUNCE) +static s32 da9052_tsi_calc_debounce_data(struct da9052_tsi_data *raw_data) +{ +#if (TSI_DEBOUNCE_DATA_CNT) + u8 cnt; + struct da9052_tsi_data temp = {.x = 0, .y = 0, .z = 0}; + + priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.tail] = (*raw_data); + incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.tail); + + if (get_raw_data_cnt(priv) <= TSI_DEBOUNCE_DATA_CNT) + return -FAILURE; + + for (cnt = 1; cnt <= TSI_DEBOUNCE_DATA_CNT; cnt++) { + temp.x += priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].x; + temp.y += priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].y; + temp.z += priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.head].z; + + incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.head); + } + + temp.x /= TSI_DEBOUNCE_DATA_CNT; + temp.y /= TSI_DEBOUNCE_DATA_CNT; + temp.z /= TSI_DEBOUNCE_DATA_CNT; + + priv->tsi_raw_fifo.tail = priv->tsi_raw_fifo.head; + priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.tail] = temp; + incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.tail); + +#if DA9052_TSI_PRINT_DEBOUNCED_DATA + printk("D: X: %d Y: %d Z: %d\n", + (u16)temp.x, (u16)temp.y, (u16)temp.z); +#endif + +#endif + priv->debounce_over = TRUE; + + return 0; +} +#endif + +# if (ENABLE_WINDOW_FILTER) +static s32 diff_within_window(struct da9052_tsi_data *prev_raw_data, + struct da9052_tsi_data *cur_raw_data) +{ + s32 ret = -EINVAL; + s32 x, y; + x = ((cur_raw_data->x) - (prev_raw_data->x)); + y = ((cur_raw_data->y) - (prev_raw_data->y)); + + if (WITHIN_WINDOW(x, y)) { + +#if DA9052_TSI_WIN_FLT_DATA_PROFILING + printk("W\tX\t%4d\tY\t%4d\tZ\t%4d\n", + (u16)cur_raw_data->x, + (u16)cur_raw_data->y, + (u16)cur_raw_data->z); +#endif + ret = 0; + } + return ret; +} + +static s32 da9052_tsi_window_filter(struct da9052_ts_priv *priv, + struct da9052_tsi_data *raw_data) +{ + u8 ref_found; + u32 cur, next; + s32 ret = -EINVAL; + static struct da9052_tsi_data prev_raw_data; + + if (priv->win_reference_valid == TRUE) { + +#if DA9052_TSI_PRINT_PREVIOUS_DATA + printk("P: X: %d Y: %d Z: %d\n", + (u16)prev_raw_data.x, (u16)prev_raw_data.y, + (u16)prev_raw_data.z); +#endif + ret = diff_within_window(&prev_raw_data, raw_data); + if (!ret) + prev_raw_data = (*raw_data); + } else { + priv->tsi_raw_fifo.data[priv->tsi_raw_fifo.tail] = (*raw_data); + incr_with_wrap_raw_fifo(priv->tsi_raw_fifo.tail); + + if (get_raw_data_cnt(priv) == SAMPLE_CNT_FOR_WIN_REF) { + + ref_found = FALSE; + + next = cur = priv->tsi_raw_fifo.head; + incr_with_wrap_raw_fifo(next); + + while (next <= priv->tsi_raw_fifo.tail) { + ret = diff_within_window( + &priv->tsi_raw_fifo.data[cur], + &priv->tsi_raw_fifo.data[next] + ); + if (ret == SUCCESS) { + ref_found = TRUE; + break; + } + incr_with_wrap_raw_fifo(cur); + incr_with_wrap_raw_fifo(next); + + } + + if (ref_found == FALSE) + priv->tsi_raw_fifo.tail = + priv->tsi_raw_fifo.head; + else { + prev_raw_data = priv->tsi_raw_fifo.data[cur]; + + prev_raw_data.x += + priv->tsi_raw_fifo.data[next].x; + prev_raw_data.y += + priv->tsi_raw_fifo.data[next].y; + prev_raw_data.z += + priv->tsi_raw_fifo.data[next].z; + + prev_raw_data.x = prev_raw_data.x / 2; + prev_raw_data.y = prev_raw_data.y / 2; + prev_raw_data.z = prev_raw_data.z / 2; + + (*raw_data) = prev_raw_data; + + priv->tsi_raw_fifo.tail = + priv->tsi_raw_fifo.head; + + priv->win_reference_valid = TRUE; + ret = SUCCESS; + } + } + } + return ret; +} +#endif +static inline void clean_tsi_reg_fifo(struct da9052_ts_priv *priv) +{ + priv->tsi_reg_fifo.head = FIRST_SAMPLE; + priv->tsi_reg_fifo.tail = FIRST_SAMPLE; +} + +static inline void clean_tsi_raw_fifo(struct da9052_ts_priv *priv) +{ + priv->tsi_raw_fifo.head = FIRST_SAMPLE; + priv->tsi_raw_fifo.tail = FIRST_SAMPLE; +} + diff --git a/drivers/input/touchscreen/imx_adc_ts.c b/drivers/input/touchscreen/imx_adc_ts.c new file mode 100644 index 000000000000..797eff5672dc --- /dev/null +++ b/drivers/input/touchscreen/imx_adc_ts.c @@ -0,0 +1,114 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file imx_adc_ts.c + * + * @brief Driver for the Freescale Semiconductor i.MX ADC touchscreen. + * + * This touchscreen driver is designed as a standard input driver. It is a + * wrapper around the low level ADC driver. Much of the hardware configuration + * and touchscreen functionality is implemented in the low level ADC driver. + * During initialization, this driver creates a kernel thread. This thread + * then calls the ADC driver to obtain touchscreen values continously. These + * values are then passed to the input susbsystem. + * + * @ingroup touchscreen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX_ADC_TS_NAME "imx_adc_ts" + +static struct input_dev *imx_inputdev; +static u32 input_ts_installed; + +static int ts_thread(void *arg) +{ + struct t_touch_screen ts_sample; + int wait = 0; + daemonize("imx_adc_ts"); + while (input_ts_installed) { + try_to_freeze(); + + memset(&ts_sample, 0, sizeof(ts_sample)); + if (0 != imx_adc_get_touch_sample(&ts_sample, !wait)) + continue; + + input_report_abs(imx_inputdev, ABS_X, ts_sample.x_position); + input_report_abs(imx_inputdev, ABS_Y, ts_sample.y_position); + input_report_abs(imx_inputdev, ABS_PRESSURE, + ts_sample.contact_resistance); + input_sync(imx_inputdev); + wait = ts_sample.contact_resistance; + msleep(10); + } + + return 0; +} + +static int __init imx_adc_ts_init(void) +{ + int retval; + + if (!is_imx_adc_ready()) + return -ENODEV; + + imx_inputdev = input_allocate_device(); + if (!imx_inputdev) { + pr_err("imx_ts_init: not enough memory for input device\n"); + return -ENOMEM; + } + + imx_inputdev->name = IMX_ADC_TS_NAME; + imx_inputdev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + imx_inputdev->keybit[BIT_WORD(BTN_TOUCH)] |= BIT_MASK(BTN_TOUCH); + imx_inputdev->absbit[0] = + BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) | BIT_MASK(ABS_PRESSURE); + retval = input_register_device(imx_inputdev); + if (retval < 0) { + input_free_device(imx_inputdev); + return retval; + } + + input_ts_installed = 1; + kthread_run(ts_thread, NULL, "ts_thread"); + pr_info("i.MX ADC input touchscreen loaded.\n"); + return 0; +} + +static void __exit imx_adc_ts_exit(void) +{ + input_ts_installed = 0; + input_unregister_device(imx_inputdev); + + if (imx_inputdev) { + input_free_device(imx_inputdev); + imx_inputdev = NULL; + } +} + +late_initcall(imx_adc_ts_init); +module_exit(imx_adc_ts_exit); + +MODULE_DESCRIPTION("i.MX ADC input touchscreen driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/touchscreen/max11801_ts.c b/drivers/input/touchscreen/max11801_ts.c new file mode 100644 index 000000000000..7e3dc09ca73f --- /dev/null +++ b/drivers/input/touchscreen/max11801_ts.c @@ -0,0 +1,351 @@ +/* + * max11801_ts.c - Driver for MAXI MAX11801 - A Resistive touch screen + * controller with i2c interface + * + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + */ + +/* This driver is aim for support the serial of MAXI touch chips + * max11801-max11803, the main different of this 4 chips can get from + * this table + * ---------------------------------------------- + * | CHIP | AUTO MODE SUPPORT | INTERFACE | + * |--------------------------------------------| + * | max11800 | YES | SPI | + * | max11801 | YES | I2C | + * | max11802 | NO | SPI | + * | max11803 | NO | I2C | + * ---------------------------------------------- + * + * Currently, this driver only support max11801. + * */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register Address define */ +#define GENERNAL_STATUS_REG 0x00 +#define GENERNAL_CONF_REG 0x01 +#define MESURE_RES_CONF_REG 0x02 +#define MESURE_AVER_CONF_REG 0x03 +#define ADC_SAMPLE_TIME_CONF_REG 0x04 +#define PANEL_SETUPTIME_CONF_REG 0x05 +#define DELAY_CONVERSION_CONF_REG 0x06 +#define TOUCH_DETECT_PULLUP_CONF_REG 0x07 +#define AUTO_MODE_TIME_CONF_REG 0x08 /* only for max11800/max11801 */ +#define APERTURE_CONF_REG 0x09 /* only for max11800/max11801 */ +#define AUX_MESURE_CONF_REG 0x0a +#define OP_MODE_CONF_REG 0x0b + +#define FIFO_RD_CMD (0x50 << 1) +#define MAX11801_FIFO_INT (1 << 2) +#define MAX11801_FIFO_OVERFLOW (1 << 3) + +#define READ_BUFFER_XYZ1Z2_SIZE 16 +#define XY_BUFSIZE 4 + +#define MAX11801_MAX_XC 0xfff +#define MAX11801_MAX_YC 0xfff + +#define MEASURE_TAG_OFFSET 2 +#define MEASURE_TAG_MASK (3 << MEASURE_TAG_OFFSET) +#define EVENT_TAG_OFFSET 0 +#define EVENT_TAG_MASK (3 << EVENT_TAG_OFFSET) +#define EVENT_X_TAG (0 << MEASURE_TAG_OFFSET) +#define EVENT_Y_TAG (1 << MEASURE_TAG_OFFSET) + +enum { + EVENT_INIT, + EVENT_MIDDLE, + EVENT_RELEASE, + EVENT_FIFO_END +}; + +#ifdef CALIBRATION +/** + * calibration array refers to + * (delta_x[0], delta_x[1], delta_x[2], delta_y[0], delta_y[1], + * delta_y[2], delta). + * Which generated by calibration service. + * In this driver when we got touch pointer (x', y') from PMIC ADC, + * we calculate the display pointer (x,y) by: + * x = (delta_x[0] * x' + delta_x[1] * y' + delta_x[2]) / delta; + * y = (delta_y[0] * x' + delta_y[1] * y' + delta_y[2]) / delta; + */ +static int calibration[7]; +module_param_array(calibration, int, NULL, S_IRUGO | S_IWUSR); +#endif + +struct max11801_data { + struct i2c_client *client; + struct input_dev *input_dev; + struct delayed_work work; + struct workqueue_struct *workq; +}; + +static u8 read_register(struct i2c_client *client, int addr) +{ + /* This chip ignore LSB of register address */ + return i2c_smbus_read_byte_data(client, addr << 1); +} + +static int max11801_write_reg(struct i2c_client *client, int addr, int data) +{ + /* This chip ignore LSB of register address */ + return i2c_smbus_write_byte_data(client, addr << 1, data); +} + +#ifdef CALIBRATION +static void calibration_pointer(int *x_orig, int *y_orig) +{ + int x, y; + if (calibration[6] == 0) + return; + x = calibration[0] * (*x_orig) + + calibration[1] * (*y_orig) + + calibration[2]; + x /= calibration[6]; + if (x < 0) + x = 0; + y = calibration[3] * (*x_orig) + + calibration[4] * (*y_orig) + + calibration[5]; + y /= calibration[6]; + if (y < 0) + y = 0; + + *x_orig = x; + *y_orig = y; +} +#else +static void calibration_pointer(int *x_orig, int *y_orig) +{ + /* Currently, calibration algorithm will be overflow in XGA + * resolution. */ + /* Here work around for android touch screen and LCD 's rotation */ + /* Will remove after calibration algorithm ok. */ + int x, y; + /* Swap x, y */ + x = *y_orig; + y = *x_orig; + /* Swap X */ + x = MAX11801_MAX_XC - x; + *x_orig = x; + *y_orig = y; +} +#endif + +static void maxi_ts_work(struct work_struct *work) +{ + struct max11801_data *data = container_of(to_delayed_work(work), + struct max11801_data, work); + struct i2c_client *client = data->client; + unsigned int x, y; + int status, i, ret; + u8 buf[XY_BUFSIZE]; + + status = read_register(data->client, GENERNAL_STATUS_REG); + while (status & (MAX11801_FIFO_INT | MAX11801_FIFO_OVERFLOW)) { + + status = read_register(data->client, GENERNAL_STATUS_REG); + + ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_CMD, + XY_BUFSIZE, buf); + if (ret < 4) { + dev_err(&client->dev, "event not enough\n"); + continue; + } + + for (i = 0; i < XY_BUFSIZE; i += 2) { + if ((buf[i+1] & MEASURE_TAG_MASK) == EVENT_X_TAG) + x = (buf[i] << 4) + (buf[i+1] >> 4); + else if ((buf[i+1] & MEASURE_TAG_MASK) == EVENT_Y_TAG) + y = (buf[i] << 4) + (buf[i+1] >> 4); + } + + if ((buf[1] & EVENT_TAG_MASK) != (buf[3] & EVENT_TAG_MASK)) + continue; + + switch (buf[1] & EVENT_TAG_MASK) { + case EVENT_INIT: + case EVENT_MIDDLE: + dev_dbg(&client->dev, "before cali: x :%d y: %d\n", + x, y); + calibration_pointer(&x, &y); + dev_dbg(&client->dev, "after cali: x :%d y: %d\n", + x, y); + input_report_abs(data->input_dev, ABS_X, x); + input_report_abs(data->input_dev, ABS_Y, y); + input_report_abs(data->input_dev, ABS_PRESSURE, 1); + input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1); + input_sync(data->input_dev); + break; + case EVENT_RELEASE: + input_report_abs(data->input_dev, ABS_PRESSURE, 0); + input_event(data->input_dev, EV_KEY, BTN_TOUCH, 0); + input_sync(data->input_dev); + break; + case EVENT_FIFO_END: + break; + } + } + enable_irq(client->irq); +} + +static void max11801_ts_phy_init(struct max11801_data *data) +{ + struct i2c_client *client = data->client; + + /* Average X,Y, take 16 samples, average eight media sample */ + max11801_write_reg(client, MESURE_AVER_CONF_REG, 0xff); + /* X,Y panel setup time set to 20us */ + max11801_write_reg(client, PANEL_SETUPTIME_CONF_REG, 0x11); + /* Rough pullup time (2uS), Fine pullup time (10us) */ + max11801_write_reg(client, TOUCH_DETECT_PULLUP_CONF_REG, 0x10); + /* Auto mode init period = 5ms , scan period = 5ms*/ + max11801_write_reg(client, AUTO_MODE_TIME_CONF_REG, 0xaa); + /* Aperture X,Y set to +- 4LSB */ + max11801_write_reg(client, APERTURE_CONF_REG, 0x33); + /* Enable Power, enable Automode, enable Aperture, enable Average X,Y */ + max11801_write_reg(client, OP_MODE_CONF_REG, 0x36); +} + +static irqreturn_t max11801_irq(int irq, void *dev) +{ + struct max11801_data *data = dev; + disable_irq_nosync(irq); + queue_delayed_work(data->workq, &data->work, 0); + return IRQ_HANDLED; +} + +static int __devinit max11801_ts_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct max11801_data *data; + struct input_dev *input_dev; + int ret; + + data = kzalloc(sizeof(struct max11801_data), GFP_KERNEL); + if (!data) { + dev_err(&client->dev, "Failed to allocate memory\n"); + return -ENOMEM; + } + +#ifdef CALIBRATION + memset(calibration, 0, sizeof(calibration)); +#endif + + input_dev = input_allocate_device(); + if (!input_dev) { + dev_err(&client->dev, "Failed to allocate memory\n"); + ret = -ENOMEM; + goto err_free_mem; + } + + data->client = client; + data->input_dev = input_dev; + max11801_ts_phy_init(data); + INIT_DELAYED_WORK(&data->work, maxi_ts_work); + data->workq = create_singlethread_workqueue("max11801_ts"); + if (!data->workq) { + dev_err(&client->dev, "Failed to create workqueue\n"); + ret = -ENOMEM; + goto err_free_wq; + } + + input_dev->name = "max11801_ts"; + input_dev->id.bustype = BUS_I2C; + input_dev->dev.parent = &client->dev; + + __set_bit(EV_ABS, input_dev->evbit); + __set_bit(EV_KEY, input_dev->evbit); + __set_bit(BTN_TOUCH, input_dev->keybit); + __set_bit(ABS_X, input_dev->absbit); + __set_bit(ABS_Y, input_dev->absbit); + __set_bit(ABS_PRESSURE, input_dev->absbit); +#ifndef CALIBRATION + input_set_abs_params(input_dev, ABS_X, 0, MAX11801_MAX_XC, 0, 0); + input_set_abs_params(input_dev, ABS_Y, 0, MAX11801_MAX_YC, 0, 0); +#endif + input_set_drvdata(input_dev, data); + + ret = request_irq(client->irq, max11801_irq, + IRQF_TRIGGER_LOW, "max11801_ts", data); + if (ret < 0) { + dev_err(&client->dev, "Failed to register interrupt\n"); + goto err_free_dev; + } + + ret = input_register_device(data->input_dev); + if (ret < 0) + goto err_free_irq; + i2c_set_clientdata(client, data); + return 0; + +err_free_irq: + free_irq(client->irq, data); +err_free_wq: + destroy_workqueue(data->workq); +err_free_dev: + input_free_device(input_dev); +err_free_mem: + kfree(data); + return ret; +} + +static __devexit int max11801_ts_remove(struct i2c_client *client) +{ + struct max11801_data *data = i2c_get_clientdata(client); + + free_irq(client->irq, data); + cancel_delayed_work_sync(&data->work); + destroy_workqueue(data->workq); + input_unregister_device(data->input_dev); + input_free_device(data->input_dev); + kfree(data); + + return 0; +} + +static const struct i2c_device_id max11801_ts_id[] = { + {"max11801", 0}, + { } +}; +MODULE_DEVICE_TABLE(i2c, max11801_ts_id); + +static struct i2c_driver max11801_ts_driver = { + .probe = max11801_ts_probe, + .remove = __devexit_p(max11801_ts_remove), + .driver = { + .name = "max11801_ts", + }, + .id_table = max11801_ts_id, +}; + +static int __init max11801_ts_init(void) +{ + return i2c_add_driver(&max11801_ts_driver); +} + +static void __exit max11801_ts_exit(void) +{ + i2c_del_driver(&max11801_ts_driver); +} + +module_init(max11801_ts_init); +module_exit(max11801_ts_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Touchscreen driver for MAXI MAX11801 controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/touchscreen/mxc_ts.c b/drivers/input/touchscreen/mxc_ts.c new file mode 100644 index 000000000000..0783188e8376 --- /dev/null +++ b/drivers/input/touchscreen/mxc_ts.c @@ -0,0 +1,189 @@ +/* + * Freescale touchscreen driver + * + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/*! + * @file mxc_ts.c + * + * @brief Driver for the Freescale Semiconductor MXC touchscreen with calibration support. + * + * The touchscreen driver is designed as a standard input driver which is a + * wrapper over low level PMIC driver. Most of the hardware configuration and + * touchscreen functionality is implemented in the low level PMIC driver. During + * initialization, this driver creates a kernel thread. This thread then calls + * PMIC driver to obtain touchscreen values continously. These values are then + * passed to the input susbsystem. + * + * @ingroup touchscreen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_TS_NAME "mxc_ts" + +static struct input_dev *mxc_inputdev; +static struct task_struct *tstask; +/** + * calibration array refers to + * (delta_x[0], delta_x[1], delta_x[2], delta_y[0], delta_y[1], delta_y[2], delta). + * Which generated by calibration service. + * In this driver when we got touch pointer (x', y') from PMIC ADC, + * we calculate the display pointer (x,y) by: + * x = (delta_x[0] * x' + delta_x[1] * y' + delta_x[2]) / delta; + * y = (delta_y[0] * x' + delta_y[1] * y' + delta_y[2]) / delta; + */ +static int calibration[7]; +module_param_array(calibration, int, NULL, S_IRUGO | S_IWUSR); + +static int ts_thread(void *arg) +{ + t_touch_screen ts_sample; + s32 wait = 0; + + do { + int x, y; + static int last_x = -1, last_y = -1, last_press = -1; + + memset(&ts_sample, 0, sizeof(t_touch_screen)); + if (0 != pmic_adc_get_touch_sample(&ts_sample, !wait)) + continue; + if (!(ts_sample.contact_resistance || wait)) + continue; + + if (ts_sample.x_position == 0 && ts_sample.y_position == 0 && + ts_sample.contact_resistance == 0) { + x = last_x; + y = last_y; + } else if (calibration[6] == 0) { + x = ts_sample.x_position; + y = ts_sample.y_position; + } else { + x = calibration[0] * (int)ts_sample.x_position + + calibration[1] * (int)ts_sample.y_position + + calibration[2]; + x /= calibration[6]; + if (x < 0) + x = 0; + y = calibration[3] * (int)ts_sample.x_position + + calibration[4] * (int)ts_sample.y_position + + calibration[5]; + y /= calibration[6]; + if (y < 0) + y = 0; + } + + if (x != last_x) { + input_report_abs(mxc_inputdev, ABS_X, x); + last_x = x; + } + if (y != last_y) { + input_report_abs(mxc_inputdev, ABS_Y, y); + last_y = y; + } + + /* report pressure */ + input_report_abs(mxc_inputdev, ABS_PRESSURE, + ts_sample.contact_resistance); +#ifdef CONFIG_MXC_PMIC_MC13892 + /* workaround for aplite ADC resistance large range value */ + if (ts_sample.contact_resistance > 22) + ts_sample.contact_resistance = 1; + else + ts_sample.contact_resistance = 0; +#endif + /* report the BTN_TOUCH */ + if (ts_sample.contact_resistance != last_press) + input_event(mxc_inputdev, EV_KEY, + BTN_TOUCH, ts_sample.contact_resistance); + + input_sync(mxc_inputdev); + last_press = ts_sample.contact_resistance; + + wait = ts_sample.contact_resistance; + msleep(20); + + } while (!kthread_should_stop()); + + return 0; +} + +static int __init mxc_ts_init(void) +{ + int retval; + + if (!is_pmic_adc_ready()) + return -ENODEV; + + mxc_inputdev = input_allocate_device(); + if (!mxc_inputdev) { + printk(KERN_ERR + "mxc_ts_init: not enough memory\n"); + return -ENOMEM; + } + + mxc_inputdev->name = MXC_TS_NAME; + mxc_inputdev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + mxc_inputdev->keybit[BIT_WORD(BTN_TOUCH)] |= BIT_MASK(BTN_TOUCH); + mxc_inputdev->absbit[0] = + BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) | BIT_MASK(ABS_PRESSURE); + retval = input_register_device(mxc_inputdev); + if (retval < 0) { + input_free_device(mxc_inputdev); + return retval; + } + + tstask = kthread_run(ts_thread, NULL, "mxc_ts"); + if (IS_ERR(tstask)) { + printk(KERN_ERR + "mxc_ts_init: failed to create kthread"); + tstask = NULL; + return -1; + } + printk("mxc input touchscreen loaded\n"); + return 0; +} + +static void __exit mxc_ts_exit(void) +{ + if (tstask) + kthread_stop(tstask); + + input_unregister_device(mxc_inputdev); + + if (mxc_inputdev) { + input_free_device(mxc_inputdev); + mxc_inputdev = NULL; + } +} + +late_initcall(mxc_ts_init); +module_exit(mxc_ts_exit); + +MODULE_DESCRIPTION("MXC touchscreen driver with calibration"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/touchscreen/mxs-ts.c b/drivers/input/touchscreen/mxs-ts.c new file mode 100644 index 000000000000..fce77fd49e0f --- /dev/null +++ b/drivers/input/touchscreen/mxs-ts.c @@ -0,0 +1,464 @@ +/* + * Freesclae MXS Touchscreen driver + * + * Author: Vitaly Wool + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define TOUCH_DEBOUNCE_TOLERANCE 100 + +struct mxs_ts_info { + int touch_irq; + int device_irq; + unsigned int base; + u8 x_plus_chan; + u8 x_minus_chan; + u8 y_plus_chan; + u8 y_minus_chan; + + unsigned int x_plus_val; + unsigned int x_minus_val; + unsigned int y_plus_val; + unsigned int y_minus_val; + unsigned int x_plus_mask; + unsigned int x_minus_mask; + unsigned int y_plus_mask; + unsigned int y_minus_mask; + + struct input_dev *idev; + enum { + TS_STATE_DISABLED, + TS_STATE_TOUCH_DETECT, + TS_STATE_TOUCH_VERIFY, + TS_STATE_X_PLANE, + TS_STATE_Y_PLANE, + } state; + u16 x; + u16 y; + int sample_count; +}; + +static inline void enter_state_touch_detect(struct mxs_ts_info *info) +{ + __raw_writel(0xFFFFFFFF, + info->base + HW_LRADC_CHn_CLR(info->x_plus_chan)); + __raw_writel(0xFFFFFFFF, + info->base + HW_LRADC_CHn_CLR(info->y_plus_chan)); + __raw_writel(0xFFFFFFFF, + info->base + HW_LRADC_CHn_CLR(info->x_minus_chan)); + __raw_writel(0xFFFFFFFF, + info->base + HW_LRADC_CHn_CLR(info->y_minus_chan)); + + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << info->y_minus_chan, + info->base + HW_LRADC_CTRL1_CLR); + __raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ, + info->base + HW_LRADC_CTRL1_CLR); + /* + * turn off the yplus and yminus pullup and pulldown, and turn off touch + * detect (enables yminus, and xplus through a resistor.On a press, + * xplus is pulled down) + */ + __raw_writel(info->y_plus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->y_minus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->x_plus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->x_minus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE, + info->base + HW_LRADC_CTRL0_SET); + hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 0); + info->state = TS_STATE_TOUCH_DETECT; + info->sample_count = 0; +} + +static inline void enter_state_disabled(struct mxs_ts_info *info) +{ + __raw_writel(info->y_plus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->y_minus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->x_plus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->x_minus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE, + info->base + HW_LRADC_CTRL0_CLR); + hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 0); + info->state = TS_STATE_DISABLED; + info->sample_count = 0; +} + + +static inline void enter_state_x_plane(struct mxs_ts_info *info) +{ + __raw_writel(info->y_plus_val, info->base + HW_LRADC_CTRL0_SET); + __raw_writel(info->y_minus_val, info->base + HW_LRADC_CTRL0_SET); + __raw_writel(info->x_plus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->x_minus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE, + info->base + HW_LRADC_CTRL0_CLR); + hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1); + + info->state = TS_STATE_X_PLANE; + info->sample_count = 0; +} + +static inline void enter_state_y_plane(struct mxs_ts_info *info) +{ + __raw_writel(info->y_plus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->y_minus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->x_plus_val, info->base + HW_LRADC_CTRL0_SET); + __raw_writel(info->x_minus_val, info->base + HW_LRADC_CTRL0_SET); + __raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE, + info->base + HW_LRADC_CTRL0_CLR); + hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1); + info->state = TS_STATE_Y_PLANE; + info->sample_count = 0; +} + +static inline void enter_state_touch_verify(struct mxs_ts_info *info) +{ + __raw_writel(info->y_plus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->y_minus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->x_plus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(info->x_minus_mask, info->base + HW_LRADC_CTRL0_CLR); + __raw_writel(BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE, + info->base + HW_LRADC_CTRL0_SET); + info->state = TS_STATE_TOUCH_VERIFY; + hw_lradc_set_delay_trigger_kick(LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1); + info->sample_count = 0; +} + +static void process_lradc(struct mxs_ts_info *info, u16 x, u16 y, + int pressure) +{ + switch (info->state) { + case TS_STATE_X_PLANE: + pr_debug("%s: x plane state, sample_count %d\n", __func__, + info->sample_count); + if (info->sample_count < 2) { + info->x = x; + info->sample_count++; + } else { + if (abs(info->x - x) > TOUCH_DEBOUNCE_TOLERANCE) + info->sample_count = 1; + else { + u16 x_c = info->x * (info->sample_count - 1); + info->x = (x_c + x) / info->sample_count; + info->sample_count++; + } + } + if (info->sample_count > 4) + enter_state_y_plane(info); + else + hw_lradc_set_delay_trigger_kick( + LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1); + break; + + case TS_STATE_Y_PLANE: + pr_debug("%s: y plane state, sample_count %d\n", __func__, + info->sample_count); + if (info->sample_count < 2) { + info->y = y; + info->sample_count++; + } else { + if (abs(info->y - y) > TOUCH_DEBOUNCE_TOLERANCE) + info->sample_count = 1; + else { + u16 y_c = info->y * (info->sample_count - 1); + info->y = (y_c + y) / info->sample_count; + info->sample_count++; + } + } + if (info->sample_count > 4) + enter_state_touch_verify(info); + else + hw_lradc_set_delay_trigger_kick( + LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1); + break; + + case TS_STATE_TOUCH_VERIFY: + pr_debug("%s: touch verify state, sample_count %d\n", __func__, + info->sample_count); + pr_debug("%s: x %d, y %d\n", __func__, info->x, info->y); + input_report_abs(info->idev, ABS_X, info->x); + input_report_abs(info->idev, ABS_Y, info->y); + input_report_abs(info->idev, ABS_PRESSURE, pressure); + input_sync(info->idev); + /* fall through */ + case TS_STATE_TOUCH_DETECT: + pr_debug("%s: touch detect state, sample_count %d\n", __func__, + info->sample_count); + if (pressure) { + input_report_abs(info->idev, ABS_PRESSURE, pressure); + enter_state_x_plane(info); + hw_lradc_set_delay_trigger_kick( + LRADC_DELAY_TRIGGER_TOUCHSCREEN, 1); + } else + enter_state_touch_detect(info); + break; + + default: + printk(KERN_ERR "%s: unknown touchscreen state %d\n", __func__, + info->state); + } +} + +static irqreturn_t ts_handler(int irq, void *dev_id) +{ + struct mxs_ts_info *info = dev_id; + u16 x_plus, y_plus; + int pressure = 0; + + if (irq == info->touch_irq) + __raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ, + info->base + HW_LRADC_CTRL1_CLR); + else if (irq == info->device_irq) + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << info->y_minus_chan, + info->base + HW_LRADC_CTRL1_CLR); + + /* get x, y values */ + x_plus = __raw_readl(info->base + HW_LRADC_CHn(info->x_plus_chan)) & + BM_LRADC_CHn_VALUE; + y_plus = __raw_readl(info->base + HW_LRADC_CHn(info->y_plus_chan)) & + BM_LRADC_CHn_VALUE; + + /* pressed? */ + if (__raw_readl(info->base + HW_LRADC_STATUS) & + BM_LRADC_STATUS_TOUCH_DETECT_RAW) + pressure = 1; + + pr_debug("%s: irq %d, x_plus %d, y_plus %d, pressure %d\n", + __func__, irq, x_plus, y_plus, pressure); + + process_lradc(info, x_plus, y_plus, pressure); + + return IRQ_HANDLED; +} + +static int __devinit mxs_ts_probe(struct platform_device *pdev) +{ + struct input_dev *idev; + struct mxs_ts_info *info; + int ret = 0; + struct resource *res; + struct mxs_touchscreen_plat_data *plat_data; + + plat_data = (struct mxs_touchscreen_plat_data *)pdev->dev.platform_data; + if (plat_data == NULL) + return -ENODEV; + + idev = input_allocate_device(); + if (idev == NULL) + return -ENOMEM; + + info = kzalloc(sizeof(struct mxs_ts_info), GFP_KERNEL); + if (info == NULL) { + ret = -ENOMEM; + goto out_nomem_info; + } + + idev->name = "MXS touchscreen"; + idev->evbit[0] = BIT(EV_ABS); + input_set_abs_params(idev, ABS_X, 0, 0xFFF, 0, 0); + input_set_abs_params(idev, ABS_Y, 0, 0xFFF, 0, 0); + input_set_abs_params(idev, ABS_PRESSURE, 0, 1, 0, 0); + + ret = input_register_device(idev); + if (ret) + goto out_nomem; + + info->idev = idev; + info->x_plus_chan = plat_data->x_plus_chan; + info->x_minus_chan = plat_data->x_minus_chan; + info->y_plus_chan = plat_data->y_plus_chan; + info->y_minus_chan = plat_data->y_minus_chan; + info->x_plus_val = plat_data->x_plus_val; + info->x_minus_val = plat_data->x_minus_val; + info->y_plus_val = plat_data->y_plus_val; + info->y_minus_val = plat_data->y_minus_val; + info->x_plus_mask = plat_data->x_plus_mask; + info->x_minus_mask = plat_data->x_minus_mask; + info->y_plus_mask = plat_data->y_plus_mask; + info->y_minus_mask = plat_data->y_minus_mask; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk(KERN_ERR "%s: couldn't get MEM resource\n", __func__); + ret = -ENODEV; + goto out_nodev; + } + info->base = (unsigned int)IO_ADDRESS(res->start); + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + printk(KERN_ERR "%s: couldn't get IRQ resource\n", __func__); + ret = -ENODEV; + goto out_nodev; + } + info->touch_irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + if (!res) { + printk(KERN_ERR "%s: couldn't get IRQ resource\n", __func__); + ret = -ENODEV; + goto out_nodev; + } + info->device_irq = res->start; + + ret = request_irq(info->touch_irq, ts_handler, IRQF_DISABLED, + "mxs_ts_touch", info); + if (ret) + goto out_nodev; + + ret = request_irq(info->device_irq, ts_handler, IRQF_DISABLED, + "mxs_ts_dev", info); + if (ret) { + free_irq(info->touch_irq, info); + goto out_nodev; + } + enter_state_touch_detect(info); + + hw_lradc_use_channel(info->x_plus_chan); + hw_lradc_use_channel(info->x_minus_chan); + hw_lradc_use_channel(info->y_plus_chan); + hw_lradc_use_channel(info->y_minus_chan); + hw_lradc_configure_channel(info->x_plus_chan, 0, 0, 0); + hw_lradc_configure_channel(info->x_minus_chan, 0, 0, 0); + hw_lradc_configure_channel(info->y_plus_chan, 0, 0, 0); + hw_lradc_configure_channel(info->y_minus_chan, 0, 0, 0); + + /* Clear the accumulator & NUM_SAMPLES for the channels */ + __raw_writel(0xFFFFFFFF, + info->base + HW_LRADC_CHn_CLR(info->x_plus_chan)); + __raw_writel(0xFFFFFFFF, + info->base + HW_LRADC_CHn_CLR(info->x_minus_chan)); + __raw_writel(0xFFFFFFFF, + info->base + HW_LRADC_CHn_CLR(info->y_plus_chan)); + __raw_writel(0xFFFFFFFF, + info->base + HW_LRADC_CHn_CLR(info->y_minus_chan)); + + hw_lradc_set_delay_trigger(LRADC_DELAY_TRIGGER_TOUCHSCREEN, + 0x3c, 0, 0, 8); + + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ << info->y_minus_chan, + info->base + HW_LRADC_CTRL1_CLR); + __raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ, + info->base + HW_LRADC_CTRL1_CLR); + + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << info->y_minus_chan, + info->base + HW_LRADC_CTRL1_SET); + __raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, + info->base + HW_LRADC_CTRL1_SET); + + platform_set_drvdata(pdev, info); + device_init_wakeup(&pdev->dev, 1); + goto out; + +out_nodev: + input_free_device(idev); +out_nomem: + kfree(info); +out_nomem_info: + kfree(idev); +out: + return ret; +} + +static int __devexit mxs_ts_remove(struct platform_device *pdev) +{ + struct mxs_ts_info *info = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + hw_lradc_unuse_channel(info->x_plus_chan); + hw_lradc_unuse_channel(info->x_minus_chan); + hw_lradc_unuse_channel(info->y_plus_chan); + hw_lradc_unuse_channel(info->y_minus_chan); + + __raw_writel(BM_LRADC_CTRL1_LRADC0_IRQ_EN << info->y_minus_chan, + info->base + HW_LRADC_CTRL1_CLR); + __raw_writel(BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, + info->base + HW_LRADC_CTRL1_CLR); + + free_irq(info->device_irq, info); + free_irq(info->touch_irq, info); + input_free_device(info->idev); + + enter_state_disabled(info); + kfree(info->idev); + kfree(info); + return 0; +} + +#ifdef CONFIG_PM +static int mxs_ts_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct mxs_ts_info *info = platform_get_drvdata(pdev); + + if (!device_may_wakeup(&pdev->dev)) { + hw_lradc_unuse_channel(info->x_plus_chan); + hw_lradc_unuse_channel(info->x_minus_chan); + hw_lradc_unuse_channel(info->y_plus_chan); + hw_lradc_unuse_channel(info->y_minus_chan); + } + return 0; +} + +static int mxs_ts_resume(struct platform_device *pdev) +{ + struct mxs_ts_info *info = platform_get_drvdata(pdev); + + if (!device_may_wakeup(&pdev->dev)) { + hw_lradc_use_channel(info->x_plus_chan); + hw_lradc_use_channel(info->x_minus_chan); + hw_lradc_use_channel(info->y_plus_chan); + hw_lradc_use_channel(info->y_minus_chan); + } + return 0; +} +#endif + +static struct platform_driver mxs_ts_driver = { + .probe = mxs_ts_probe, + .remove = __devexit_p(mxs_ts_remove), +#ifdef CONFIG_PM + .suspend = mxs_ts_suspend, + .resume = mxs_ts_resume, +#endif + .driver = { + .name = "mxs-ts", + }, +}; + +static int __init mxs_ts_init(void) +{ + return platform_driver_register(&mxs_ts_driver); +} + +static void __exit mxs_ts_exit(void) +{ + platform_driver_unregister(&mxs_ts_driver); +} + +module_init(mxs_ts_init); +module_exit(mxs_ts_exit); diff --git a/drivers/input/touchscreen/tsc2007.c b/drivers/input/touchscreen/tsc2007.c index be23780e8a3e..cf8a4daee39a 100644 --- a/drivers/input/touchscreen/tsc2007.c +++ b/drivers/input/touchscreen/tsc2007.c @@ -295,6 +295,13 @@ static int __devinit tsc2007_probe(struct i2c_client *client, ts->get_pendown_state = pdata->get_pendown_state; ts->clear_penirq = pdata->clear_penirq; + pdata->init_platform_hw(); + + if (tsc2007_xfer(ts, PWRDOWN) < 0) { + err = -ENODEV; + goto err_no_dev; + } + snprintf(ts->phys, sizeof(ts->phys), "%s/input0", dev_name(&client->dev)); @@ -338,6 +345,8 @@ static int __devinit tsc2007_probe(struct i2c_client *client, pdata->exit_platform_hw(); err_free_mem: input_free_device(input_dev); + err_no_dev: + pdata->exit_platform_hw(); kfree(ts); return err; } diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 81bf25e67ce1..196270d08960 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -33,6 +33,17 @@ config LEDS_ATMEL_PWM This option enables support for LEDs driven using outputs of the dedicated PWM controller found on newer Atmel SOCs. +config LEDS_MXS + tristate "Support for PWM LEDs on MXS" + depends on LEDS_CLASS && ARCH_MXS + help + This option enables support for the LEDs connected to PWM + outputs on the Freescale MXS SOC. + +config LEDS_MC13892 + tristate "LED Support for mc13892 pmic" + depends on LEDS_CLASS && MXC_MC13892_LIGHT + config LEDS_LOCOMO tristate "LED Support for Locomo device" depends on SHARP_LOCOMO @@ -235,6 +246,16 @@ config LEDS_DA903X This option enables support for on-chip LED drivers found on Dialog Semiconductor DA9030/DA9034 PMICs. +config LEDS_DA9052 + tristate "Dialog DA9052 LEDS" + depends on PMIC_DA9052 + help + This option enables support for on-chip LED drivers found + on Dialog Semiconductor DA9052 PMICs. + + To compile this driver as a module, choose M here: the + module will be called leds-da9052. + config LEDS_DAC124S085 tristate "LED Support for DAC124S085 SPI DAC" depends on SPI diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 2493de499374..8285efc54a03 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_LEDS_TRIGGERS) += led-triggers.o obj-$(CONFIG_LEDS_88PM860X) += leds-88pm860x.o obj-$(CONFIG_LEDS_ATMEL_PWM) += leds-atmel-pwm.o obj-$(CONFIG_LEDS_BD2802) += leds-bd2802.o +obj-$(CONFIG_LEDS_MC13892) += leds-mc13892.o obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o obj-$(CONFIG_LEDS_MIKROTIK_RB532) += leds-rb532.o obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o @@ -28,6 +29,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o obj-$(CONFIG_LEDS_FSG) += leds-fsg.o obj-$(CONFIG_LEDS_PCA955X) += leds-pca955x.o obj-$(CONFIG_LEDS_DA903X) += leds-da903x.o +obj-$(CONFIG_LEDS_DA9052) += leds-da9052.o obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o obj-$(CONFIG_LEDS_PWM) += leds-pwm.o @@ -37,6 +39,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o +obj-$(CONFIG_LEDS_MXS) += leds-mxs-pwm.o # LED SPI Drivers obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o diff --git a/drivers/leds/leds-da9052.c b/drivers/leds/leds-da9052.c new file mode 100644 index 000000000000..187d4d2372e0 --- /dev/null +++ b/drivers/leds/leds-da9052.c @@ -0,0 +1,307 @@ +/* + * leds-da9052.c -- LED Driver for Dialog DA9052 + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * Author: Dialog Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DRIVER_NAME "da9052-leds" + +#define DA9052_LED4_PRESENT 1 +#define DA9052_LED5_PRESENT 1 + + +struct da9052_led_data { + struct led_classdev cdev; + struct work_struct work; + struct da9052 *da9052; + int id; + int new_brightness; + int is_led4_present; + int is_led5_present; +}; + +#define GPIO14_PIN 2 /* GPO Open Drain */ +#define GPIO14_TYPE 0 /* VDD_IO1 */ +#define GPIO14_MODE 1 /* Output High */ + +#define GPIO15_PIN 2 /* GPO Open Drain */ +#define GPIO15_TYPE 0 /* VDD_IO1 */ +#define GPIO15_MODE 1 /* Output High */ + +#define MAXIMUM_PWM 95 +#define MASK_GPIO14 0x0F +#define MASK_GPIO15 0xF0 +#define GPIO15_PIN_BIT_POSITION 4 + +static void da9052_led_work(struct work_struct *work) +{ + struct da9052_led_data *led = container_of(work, + struct da9052_led_data, work); + int reg = 0; + int led_dim_bit = 0; + struct da9052_ssc_msg msg; + int ret = 0; + + switch (led->id) { + case DA9052_LED_4: + reg = DA9052_LED4CONT_REG; + led_dim_bit = DA9052_LED4CONT_LED4DIM; + break; + case DA9052_LED_5: + reg = DA9052_LED5CONT_REG; + led_dim_bit = DA9052_LED5CONT_LED5DIM; + break; + } + + if (led->new_brightness > MAXIMUM_PWM) + led->new_brightness = MAXIMUM_PWM; + + /* Always enable DIM feature + * This feature can be disabled if required + */ + msg.addr = reg; + msg.data = led->new_brightness | led_dim_bit; + da9052_lock(led->da9052); + ret = led->da9052->write(led->da9052, &msg); + if (ret) { + da9052_unlock(led->da9052); + return; + } + da9052_unlock(led->da9052); +} + +static void da9052_led_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct da9052_led_data *led; + + led = container_of(led_cdev, struct da9052_led_data, cdev); + led->new_brightness = value; + schedule_work(&led->work); +} + +static int __devinit da9052_led_setup(struct da9052_led_data *led) +{ + int reg = 0; + int ret = 0; + + struct da9052_ssc_msg msg; + + switch (led->id) { + case DA9052_LED_4: + reg = DA9052_LED4CONT_REG; + break; + case DA9052_LED_5: + reg = DA9052_LED5CONT_REG; + break; + } + + msg.addr = reg; + msg.data = 0; + + da9052_lock(led->da9052); + ret = led->da9052->write(led->da9052, &msg); + if (ret) { + da9052_unlock(led->da9052); + return ret; + } + da9052_unlock(led->da9052); + return ret; +} + +static int da9052_leds_prepare(struct da9052_led_data *led) +{ + int ret = 0; + struct da9052_ssc_msg msg; + + da9052_lock(led->da9052); + + if (1 == led->is_led4_present) { + msg.addr = DA9052_GPIO1415_REG; + msg.data = 0; + + ret = led->da9052->read(led->da9052, &msg); + if (ret) + goto out; + msg.data = msg.data & ~(MASK_GPIO14); + msg.data = msg.data | ( + GPIO14_PIN | + (GPIO14_TYPE ? DA9052_GPIO1415_GPIO14TYPE : 0) | + (GPIO14_MODE ? DA9052_GPIO1415_GPIO14MODE : 0)); + + ret = led->da9052->write(led->da9052, &msg); + if (ret) + goto out; + } + + if (1 == led->is_led5_present) { + msg.addr = DA9052_GPIO1415_REG; + msg.data = 0; + + ret = led->da9052->read(led->da9052, &msg); + if (ret) + goto out; + msg.data = msg.data & ~(MASK_GPIO15); + msg.data = msg.data | + (((GPIO15_PIN << GPIO15_PIN_BIT_POSITION) | + (GPIO15_TYPE ? DA9052_GPIO1415_GPIO15TYPE : 0) | + (GPIO15_MODE ? DA9052_GPIO1415_GPIO15MODE : 0)) + ); + ret = led->da9052->write(led->da9052, &msg); + if (ret) + goto out; + } + + da9052_unlock(led->da9052); + return ret; +out: + da9052_unlock(led->da9052); + return ret; +} + +static int __devinit da9052_led_probe(struct platform_device *pdev) +{ + struct da9052_leds_platform_data *pdata = (pdev->dev.platform_data); + struct da9052_led_platform_data *led_cur; + struct da9052_led_data *led, *led_dat; + int ret, i; + int init_led = 0; + + if (pdata->num_leds < 1 || pdata->num_leds > DA9052_LED_MAX) { + dev_err(&pdev->dev, "Invalid led count %d\n", pdata->num_leds); + return -EINVAL; + } + + led = kzalloc(sizeof(*led) * pdata->num_leds, GFP_KERNEL); + if (led == NULL) { + dev_err(&pdev->dev, "failed to alloc memory\n"); + return -ENOMEM; + } + + led->is_led4_present = DA9052_LED4_PRESENT; + led->is_led5_present = DA9052_LED5_PRESENT; + + for (i = 0; i < pdata->num_leds; i++) { + led_dat = &led[i]; + led_cur = &pdata->led[i]; + if (led_cur->id < 0) { + dev_err(&pdev->dev, "invalid id %d\n", led_cur->id); + ret = -EINVAL; + goto err_register; + } + + if (init_led & (1 << led_cur->id)) { + dev_err(&pdev->dev, "led %d already initialized\n", + led_cur->id); + ret = -EINVAL; + goto err_register; + } + + init_led |= 1 << led_cur->id; + + led_dat->cdev.name = led_cur->name; + // led_dat->cdev.default_trigger = led_cur[i]->default_trigger; + led_dat->cdev.brightness_set = da9052_led_set; + led_dat->cdev.brightness = LED_OFF; + led_dat->id = led_cur->id; + led_dat->da9052 = dev_get_drvdata(pdev->dev.parent); + + INIT_WORK(&led_dat->work, da9052_led_work); + + ret = led_classdev_register(pdev->dev.parent, &led_dat->cdev); + if (ret) { + dev_err(&pdev->dev, "failed to register led %d\n", + led_dat->id); + goto err_register; + + } + ret = da9052_led_setup(led_dat); + if (ret) { + dev_err(&pdev->dev, "unable to init led %d\n", + led_dat->id); + i++; + goto err_register; + } + } + ret = da9052_leds_prepare(led); + if (ret) { + dev_err(&pdev->dev, "unable to init led driver\n"); + goto err_free; + } + + platform_set_drvdata(pdev, led); + return 0; + +err_register: + for (i = i - 1; i >= 0; i--) { + led_classdev_unregister(&led[i].cdev); + cancel_work_sync(&led[i].work); + } + +err_free: + kfree(led); + return ret; +} + +static int __devexit da9052_led_remove(struct platform_device *pdev) +{ + struct da9052_leds_platform_data *pdata = + (struct da9052_leds_platform_data *)pdev->dev.platform_data; + struct da9052_led_data *led = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < pdata->num_leds; i++) { + da9052_led_setup(&led[i]); + led_classdev_unregister(&led[i].cdev); + cancel_work_sync(&led[i].work); + } + + kfree(led); + return 0; +} + +static struct platform_driver da9052_led_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, + .probe = da9052_led_probe, + .remove = __devexit_p(da9052_led_remove), +}; + +static int __init da9052_led_init(void) +{ + return platform_driver_register(&da9052_led_driver); +} +module_init(da9052_led_init); + +static void __exit da9052_led_exit(void) +{ + platform_driver_unregister(&da9052_led_driver); +} +module_exit(da9052_led_exit); + +MODULE_AUTHOR("Dialog Semiconductor Ltd "); +MODULE_DESCRIPTION("LED driver for Dialog DA9052 PMIC"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/leds/leds-mc13892.c b/drivers/leds/leds-mc13892.c new file mode 100644 index 000000000000..ec7ae4316b4d --- /dev/null +++ b/drivers/leds/leds-mc13892.c @@ -0,0 +1,153 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +static void mc13892_led_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct platform_device *dev = to_platform_device(led_cdev->dev->parent); + int led_ch; + + switch (dev->id) { + case 'r': + led_ch = LIT_RED; + break; + case 'g': + led_ch = LIT_GREEN; + break; + case 'b': + led_ch = LIT_BLUE; + break; + default: + return; + } + + /* set current with medium value, in case current is too large */ + mc13892_bklit_set_current(led_ch, LIT_CURR_12); + /* max duty cycle is 63, brightness needs to be divided by 4 */ + mc13892_bklit_set_dutycycle(led_ch, value / 4); + +} + +static int mc13892_led_remove(struct platform_device *dev) +{ + struct led_classdev *led_cdev = platform_get_drvdata(dev); + + led_classdev_unregister(led_cdev); + kfree(led_cdev->name); + kfree(led_cdev); + + return 0; +} + +#define LED_NAME_LEN 16 + +static int mc13892_led_probe(struct platform_device *dev) +{ + int ret; + struct led_classdev *led_cdev; + char *name; + + led_cdev = kzalloc(sizeof(struct led_classdev), GFP_KERNEL); + if (led_cdev == NULL) { + dev_err(&dev->dev, "No memory for device\n"); + return -ENOMEM; + } + name = kzalloc(LED_NAME_LEN, GFP_KERNEL); + if (name == NULL) { + dev_err(&dev->dev, "No memory for device\n"); + ret = -ENOMEM; + goto exit_err; + } + + strcpy(name, dev->name); + ret = strlen(dev->name); + if (ret > LED_NAME_LEN - 2) { + dev_err(&dev->dev, "led name is too long\n"); + goto exit_err1; + } + name[ret] = dev->id; + name[ret + 1] = '\0'; + led_cdev->name = name; + led_cdev->brightness_set = mc13892_led_set; + + ret = led_classdev_register(&dev->dev, led_cdev); + if (ret < 0) { + dev_err(&dev->dev, "led_classdev_register failed\n"); + goto exit_err1; + } + + platform_set_drvdata(dev, led_cdev); + + return 0; + exit_err1: + kfree(led_cdev->name); + exit_err: + kfree(led_cdev); + return ret; +} + +#ifdef CONFIG_PM +static int mc13892_led_suspend(struct platform_device *dev, pm_message_t state) +{ + struct led_classdev *led_cdev = platform_get_drvdata(dev); + + led_classdev_suspend(led_cdev); + return 0; +} + +static int mc13892_led_resume(struct platform_device *dev) +{ + struct led_classdev *led_cdev = platform_get_drvdata(dev); + + led_classdev_resume(led_cdev); + return 0; +} +#else +#define mc13892_led_suspend NULL +#define mc13892_led_resume NULL +#endif + +static struct platform_driver mc13892_led_driver = { + .probe = mc13892_led_probe, + .remove = mc13892_led_remove, + .suspend = mc13892_led_suspend, + .resume = mc13892_led_resume, + .driver = { + .name = "pmic_leds", + .owner = THIS_MODULE, + }, +}; + +static int __init mc13892_led_init(void) +{ + return platform_driver_register(&mc13892_led_driver); +} + +static void __exit mc13892_led_exit(void) +{ + platform_driver_unregister(&mc13892_led_driver); +} + +module_init(mc13892_led_init); +module_exit(mc13892_led_exit); + +MODULE_DESCRIPTION("Led driver for PMIC mc13892"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/leds/leds-mxs-pwm.c b/drivers/leds/leds-mxs-pwm.c new file mode 100644 index 000000000000..a546900a44d0 --- /dev/null +++ b/drivers/leds/leds-mxs-pwm.c @@ -0,0 +1,217 @@ +/* + * Freescale MXS PWM LED driver + * + * Author: Drew Benedetti + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +/* + * PWM enables are the lowest bits of HW_PWM_CTRL register + */ +#define BM_PWM_CTRL_PWM_ENABLE ((1<<(CONFIG_MXS_PWM_CHANNELS)) - 1) +#define BF_PWM_CTRL_PWM_ENABLE(n) ((1<<(n)) & BM_PWM_CTRL_PWM_ENABLE) + +#define BF_PWM_PERIODn_SETTINGS \ + (BF_PWM_PERIODn_CDIV(5) | /* divide by 64 */ \ + BF_PWM_PERIODn_INACTIVE_STATE(3) | /* low */ \ + BF_PWM_PERIODn_ACTIVE_STATE(2) | /* high */ \ + BF_PWM_PERIODn_PERIOD(LED_FULL)) /* 255 cycles */ + +struct mxs_pwm_leds { + struct clk *pwm_clk; + unsigned int base; + unsigned int led_num; + struct mxs_pwm_led *leds; +}; + +static struct mxs_pwm_leds leds; + +static void mxs_pwm_led_brightness_set(struct led_classdev *pled, + enum led_brightness value) +{ + struct mxs_pwm_led *pwm_led; + + pwm_led = container_of(pled, struct mxs_pwm_led, dev); + + if (pwm_led->pwm < CONFIG_MXS_PWM_CHANNELS) { + __raw_writel(BF_PWM_CTRL_PWM_ENABLE(pwm_led->pwm), + leds.base + HW_PWM_CTRL_CLR); + __raw_writel(BF_PWM_ACTIVEn_INACTIVE(LED_FULL) | + BF_PWM_ACTIVEn_ACTIVE(value), + leds.base + HW_PWM_ACTIVEn(pwm_led->pwm)); + __raw_writel(BF_PWM_PERIODn_SETTINGS, + leds.base + HW_PWM_PERIODn(pwm_led->pwm)); + __raw_writel(BF_PWM_CTRL_PWM_ENABLE(pwm_led->pwm), + leds.base + HW_PWM_CTRL_SET); + } +} + +static int __devinit mxs_pwm_led_probe(struct platform_device *pdev) +{ + struct mxs_pwm_leds_plat_data *plat_data; + struct resource *res; + struct led_classdev *led; + unsigned int pwmn; + int leds_in_use = 0, rc = 0; + int i; + + plat_data = (struct mxs_pwm_leds_plat_data *)pdev->dev.platform_data; + if (plat_data == NULL) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -ENODEV; + leds.base = (unsigned int)IO_ADDRESS(res->start); + + mxs_reset_block((void __iomem *)leds.base, 1); + + leds.led_num = plat_data->num; + if (leds.led_num <= 0 || leds.led_num > CONFIG_MXS_PWM_CHANNELS) + return -EFAULT; + leds.leds = plat_data->leds; + if (leds.leds == NULL) + return -EFAULT; + + leds.pwm_clk = clk_get(&pdev->dev, "pwm"); + if (IS_ERR(leds.pwm_clk)) { + rc = PTR_ERR(leds.pwm_clk); + return rc; + } + + clk_enable(leds.pwm_clk); + + for (i = 0; i < leds.led_num; i++) { + pwmn = leds.leds[i].pwm; + if (pwmn >= CONFIG_MXS_PWM_CHANNELS) { + dev_err(&pdev->dev, + "[led-pwm%d]:PWM %d doesn't exist\n", + i, pwmn); + continue; + } + led = &(leds.leds[i].dev); + led->name = leds.leds[i].name; + led->brightness = LED_HALF; + led->flags = 0; + led->brightness_set = mxs_pwm_led_brightness_set; + led->default_trigger = 0; + + rc = led_classdev_register(&pdev->dev, led); + if (rc < 0) { + dev_err(&pdev->dev, + "Unable to register LED device %d (err=%d)\n", + i, rc); + continue; + } + + leds_in_use++; + + /* Set default brightness */ + mxs_pwm_led_brightness_set(led, LED_HALF); + } + + if (leds_in_use == 0) { + dev_info(&pdev->dev, "No PWM LEDs available\n"); + clk_disable(leds.pwm_clk); + clk_put(leds.pwm_clk); + return -ENODEV; + } + return 0; +} + +static int __devexit mxs_pwm_led_remove(struct platform_device *pdev) +{ + int i; + unsigned int pwm; + for (i = 0; i < leds.led_num; i++) { + pwm = leds.leds[i].pwm; + __raw_writel(BF_PWM_CTRL_PWM_ENABLE(pwm), + leds.base + HW_PWM_CTRL_CLR); + __raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) | + BF_PWM_ACTIVEn_ACTIVE(0), + leds.base + HW_PWM_ACTIVEn(pwm)); + __raw_writel(BF_PWM_PERIODn_SETTINGS, + leds.base + HW_PWM_PERIODn(pwm)); + led_classdev_unregister(&leds.leds[i].dev); + } + + clk_disable(leds.pwm_clk); + clk_put(leds.pwm_clk); + + return 0; +} + +#ifdef CONFIG_PM +static int mxs_led_suspend(struct platform_device *dev, pm_message_t state) +{ + int i; + + for (i = 0; i < leds.led_num; i++) + led_classdev_suspend(&leds.leds[i].dev); + return 0; +} + +static int mxs_led_resume(struct platform_device *dev) +{ + int i; + + for (i = 0; i < leds.led_num; i++) + led_classdev_resume(&leds.leds[i].dev); + return 0; +} +#else +#define mxs_led_suspend NULL +#define mxs_led_resume NULL +#endif + + +static struct platform_driver mxs_pwm_led_driver = { + .probe = mxs_pwm_led_probe, + .remove = __devexit_p(mxs_pwm_led_remove), + .suspend = mxs_led_suspend, + .resume = mxs_led_resume, + .driver = { + .name = "mxs-leds", + }, +}; + +static int __init mxs_pwm_led_init(void) +{ + return platform_driver_register(&mxs_pwm_led_driver); +} + +static void __exit mxs_pwm_led_exit(void) +{ + platform_driver_unregister(&mxs_pwm_led_driver); +} + +module_init(mxs_pwm_led_init); +module_exit(mxs_pwm_led_exit); + +MODULE_AUTHOR("Drew Benedetti "); +MODULE_DESCRIPTION("mxs PWM LED driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index bdbc9d305419..dfd3eba81b11 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -678,6 +678,56 @@ config VIDEO_W9966 Check out for more information. +config VIDEO_MXC_CAMERA + tristate "MXC Video For Linux Camera" + depends on VIDEO_DEV && ARCH_MXC + default y + ---help--- + This is the video4linux2 capture driver based on MXC IPU/eMMA module. + +source "drivers/media/video/mxc/capture/Kconfig" + +config VIDEO_MXC_OUTPUT + tristate "MXC Video For Linux Video Output" + depends on VIDEO_DEV && ARCH_MXC + default y + ---help--- + This is the video4linux2 output driver based on MXC IPU/eMMA module. + +source "drivers/media/video/mxc/output/Kconfig" + +config VIDEO_MXS_PXP + tristate "MXS PxP" + depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MXS + select VIDEOBUF_DMA_CONTIG + ---help--- + This is a video4linux driver for the Freescale PxP + (Pixel Pipeline). This module supports output overlay of + the MXS framebuffer on a video stream. + + To compile this driver as a module, choose M here: the + module will be called pxp. + +config VIDEO_MXC_PXP_V4L2 + tristate "MXC PxP V4L2 driver" + depends on VIDEO_DEV && VIDEO_V4L2 && ARCH_MX5 + select VIDEOBUF_DMA_CONTIG + ---help--- + This is a video4linux driver for the Freescale PxP + (Pixel Pipeline). This module supports output overlay of + the MXC framebuffer on a video stream. + + To compile this driver as a module, choose M here. + +config VIDEO_MXC_OPL + tristate + depends on VIDEO_DEV && ARCH_MXC + default n + ---help--- + This is the ARM9-optimized OPL (Open Primitives Library) software + rotation/mirroring implementation. It may be used by eMMA video + capture or output device. + config VIDEO_CPIA tristate "CPiA Video For Linux (DEPRECATED)" depends on VIDEO_V4L1 diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index cc93859d3164..81588bcd91ea 100644 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile @@ -94,6 +94,15 @@ obj-$(CONFIG_VIDEO_W9966) += w9966.o obj-$(CONFIG_VIDEO_PMS) += pms.o obj-$(CONFIG_VIDEO_VINO) += vino.o obj-$(CONFIG_VIDEO_STRADIS) += stradis.o +obj-$(CONFIG_VIDEO_MXC_IPU_CAMERA) += mxc/capture/ +obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += mxc/capture/ +obj-$(CONFIG_VIDEO_MXC_IPU_OUTPUT) += mxc/output/ +obj-$(CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT) += mxc/output/ +obj-$(CONFIG_VIDEO_MXC_EMMA_OUTPUT) += mxc/output/ +obj-$(CONFIG_VIDEO_MXC_PXP_V4L2) += mxc/output/ +obj-$(CONFIG_VIDEO_MXC_OPL) += mxc/opl/ +obj-$(CONFIG_VIDEO_PXP) += pxp.o +obj-$(CONFIG_VIDEO_MXS_PXP) += mxs_pxp.o obj-$(CONFIG_VIDEO_CPIA) += cpia.o obj-$(CONFIG_VIDEO_CPIA_PP) += cpia_pp.o obj-$(CONFIG_VIDEO_CPIA_USB) += cpia_usb.o diff --git a/drivers/media/video/mxc/capture/Kconfig b/drivers/media/video/mxc/capture/Kconfig new file mode 100644 index 000000000000..2e3cb56de14c --- /dev/null +++ b/drivers/media/video/mxc/capture/Kconfig @@ -0,0 +1,125 @@ +if VIDEO_MXC_CAMERA + +menu "MXC Camera/V4L2 PRP Features support" +config VIDEO_MXC_IPU_CAMERA + bool + depends on VIDEO_MXC_CAMERA && MXC_IPU + default y + +config VIDEO_MXC_EMMA_CAMERA + tristate "MX27 eMMA support" + depends on VIDEO_MXC_CAMERA && MXC_EMMA && FB_MXC_SYNC_PANEL + select VIDEO_MXC_OPL + default y + +config VIDEO_MXC_CSI_CAMERA + tristate "MX25 CSI camera support" + depends on !VIDEO_MXC_EMMA_CAMERA + +config VIDEO_MXC_CSI_DMA + bool "CSI-DMA Still Image Capture support" + depends on VIDEO_MXC_EMMA_CAMERA + default n + ---help--- + Use CSI-DMA method instead of CSI-PrP link to capture still image. This allows + to use less physical contiguous memory to capture big resolution still image. But + with this method the CSC (Color Space Conversion) and resize are not supported. + If unsure, say N. + +choice + prompt "Select Camera/TV Decoder" + default MXC_CAMERA_OV3640 + depends on VIDEO_MXC_CAMERA + +config MXC_CAMERA_MC521DA + tristate "Magnachip mc521da camera support" + select I2C_MXC + depends on VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the mc521da Camera with your MXC system, say Y here. + +config MXC_EMMA_CAMERA_MICRON111 + tristate "Micron mt9v111 camera support with eMMA" + select I2C_MXC + depends on VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the mt9v111 Camera with your MXC system, say Y here. + +config MXC_CAMERA_OV2640_EMMA + tristate "OmniVision ov2640 camera support with eMMA" + depends on VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the ov2640 Camera with your MXC system, say Y here. + +config MXC_CAMERA_MICRON111 + tristate "Micron mt9v111 camera support" + select I2C_MXC + depends on ! VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the mt9v111 Camera with your MXC system, say Y here. + +config MXC_CAMERA_OV2640 + tristate "OmniVision ov2640 camera support" + depends on !VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the ov2640 Camera with your MXC system, say Y here. + +config MXC_CAMERA_OV3640 + tristate "OmniVision ov3640 camera support" + depends on !VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the ov3640 Camera with your MXC system, say Y here. + +config MXC_CAMERA_OV5640 + tristate "OmniVision ov5640 camera support" + depends on !VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the ov5640 Camera with your MXC system, say Y here. + +config MXC_CAMERA_OV5642 + tristate "OmniVision ov5642 camera support" + depends on !VIDEO_MXC_EMMA_CAMERA + ---help--- + If you plan to use the ov5642 Camera with your MXC system, say Y here. + +config MXC_TVIN_ADV7180 + tristate "Analog Device adv7180 TV Decoder Input support" + depends on (MACH_MX35_3DS || MACH_MX51_3DS) + ---help--- + If you plan to use the adv7180 video decoder with your MXC system, say Y here. + +endchoice + +config MXC_IPU_PRP_VF_SDC + tristate "Pre-Processor VF SDC library" + depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_SYNC_PANEL + default y + ---help--- + Use case PRP_VF_SDC: + Preprocessing image from smart sensor for viewfinder and + displaying it on synchronous display with SDC use case. + If SDC BG is selected, Rotation will not be supported. + CSI -> IC (PRP VF) -> MEM + MEM -> IC (ROT) -> MEM + MEM -> SDC (FG/BG) + +config MXC_IPU_PRP_ENC + tristate "Pre-processor Encoder library" + depends on VIDEO_MXC_IPU_CAMERA + default y + ---help--- + Use case PRP_ENC: + Preprocessing image from smart sensor for encoder. + CSI -> IC (PRP ENC) -> MEM + +config MXC_IPU_CSI_ENC + tristate "IPU CSI Encoder library" + depends on VIDEO_MXC_IPU_CAMERA + default y + ---help--- + Use case IPU_CSI_ENC: + Get raw image with CSI from smart sensor for encoder. + CSI -> MEM +endmenu + +endif diff --git a/drivers/media/video/mxc/capture/Makefile b/drivers/media/video/mxc/capture/Makefile new file mode 100644 index 000000000000..fda685d63d7b --- /dev/null +++ b/drivers/media/video/mxc/capture/Makefile @@ -0,0 +1,44 @@ +ifeq ($(CONFIG_VIDEO_MXC_IPU_CAMERA),y) + obj-$(CONFIG_VIDEO_MXC_CAMERA) += mxc_v4l2_capture.o + obj-$(CONFIG_MXC_IPU_PRP_VF_SDC) += ipu_prp_vf_sdc.o ipu_prp_vf_sdc_bg.o + obj-$(CONFIG_MXC_IPU_PRP_ENC) += ipu_prp_enc.o ipu_still.o + obj-$(CONFIG_MXC_IPU_CSI_ENC) += ipu_csi_enc.o ipu_still.o +endif + +obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += fsl_csi.o csi_v4l2_capture.o + +mx27_capture-objs := mx27_prphw.o mx27_prpsw.o emma_v4l2_capture.o +obj-$(CONFIG_VIDEO_MXC_EMMA_CAMERA) += mx27_csi.o mx27_capture.o + +mc521da_camera-objs := mc521da.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_MC521DA) += mc521da_camera.o + +emma_mt9v111_camera-objs := emma_mt9v111.o sensor_clock.o +obj-$(CONFIG_MXC_EMMA_CAMERA_MICRON111) += emma_mt9v111_camera.o + +mt9v111_camera-objs := mt9v111.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_MICRON111) += mt9v111_camera.o + +hv7161_camera-objs := hv7161.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_HV7161) += hv7161_camera.o + +s5k3aaex_camera-objs := s5k3aaex.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_S5K3AAEX) += s5k3aaex_camera.o + +emma_ov2640_camera-objs := emma_ov2640.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_OV2640_EMMA) += emma_ov2640_camera.o + +ov2640_camera-objs := ov2640.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_OV2640) += ov2640_camera.o + +ov3640_camera-objs := ov3640.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_OV3640) += ov3640_camera.o + +ov5640_camera-objs := ov5640.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_OV5640) += ov5640_camera.o + +ov5642_camera-objs := ov5642.o sensor_clock.o +obj-$(CONFIG_MXC_CAMERA_OV5642) += ov5642_camera.o + +adv7180_tvin-objs := adv7180.o +obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o diff --git a/drivers/media/video/mxc/capture/adv7180.c b/drivers/media/video/mxc/capture/adv7180.c new file mode 100644 index 000000000000..3e811d48f097 --- /dev/null +++ b/drivers/media/video/mxc/capture/adv7180.c @@ -0,0 +1,1024 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file adv7180.c + * + * @brief Analog Device ADV7180 video decoder functions + * + * @ingroup Camera + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" + +static struct regulator *dvddio_regulator; +static struct regulator *dvdd_regulator; +static struct regulator *avdd_regulator; +static struct regulator *pvdd_regulator; +static struct mxc_tvin_platform_data *tvin_plat; + +extern void gpio_sensor_active(void); +extern void gpio_sensor_inactive(void); + +static int adv7180_probe(struct i2c_client *adapter, + const struct i2c_device_id *id); +static int adv7180_detach(struct i2c_client *client); + +static const struct i2c_device_id adv7180_id[] = { + {"adv7180", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, adv7180_id); + +static struct i2c_driver adv7180_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "adv7180", + }, + .probe = adv7180_probe, + .remove = adv7180_detach, + .id_table = adv7180_id, +}; + +/*! + * Maintains the information on the current state of the sesor. + */ +struct sensor { + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + v4l2_std_id std_id; +} adv7180_data; + +/*! List of input video formats supported. The video formats is corresponding + * with v4l2 id in video_fmt_t + */ +typedef enum { + ADV7180_NTSC = 0, /*!< Locked on (M) NTSC video signal. */ + ADV7180_PAL, /*!< (B, G, H, I, N)PAL video signal. */ + ADV7180_NOT_LOCKED, /*!< Not locked on a signal. */ +} video_fmt_idx; + +/*! Number of video standards supported (including 'not locked' signal). */ +#define ADV7180_STD_MAX (ADV7180_PAL + 1) + +/*! Video format structure. */ +typedef struct { + int v4l2_id; /*!< Video for linux ID. */ + char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */ + u16 raw_width; /*!< Raw width. */ + u16 raw_height; /*!< Raw height. */ + u16 active_width; /*!< Active width. */ + u16 active_height; /*!< Active height. */ +} video_fmt_t; + +/*! Description of video formats supported. + * + * PAL: raw=720x625, active=720x576. + * NTSC: raw=720x525, active=720x480. + */ +static video_fmt_t video_fmts[] = { + { /*! NTSC */ + .v4l2_id = V4L2_STD_NTSC, + .name = "NTSC", + .raw_width = 720, /* SENS_FRM_WIDTH */ + .raw_height = 525, /* SENS_FRM_HEIGHT */ + .active_width = 720, /* ACT_FRM_WIDTH plus 1 */ + .active_height = 480, /* ACT_FRM_WIDTH plus 1 */ + }, + { /*! (B, G, H, I, N) PAL */ + .v4l2_id = V4L2_STD_PAL, + .name = "PAL", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + }, + { /*! Unlocked standard */ + .v4l2_id = V4L2_STD_ALL, + .name = "Autodetect", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + }, +}; + +/*!* Standard index of ADV7180. */ +static video_fmt_idx video_idx = ADV7180_PAL; + +/*! @brief This mutex is used to provide mutual exclusion. + * + * Create a mutex that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * and variables that were defined above. + */ +static DECLARE_MUTEX(mutex); + +#define IF_NAME "adv7180" +#define ADV7180_INPUT_CTL 0x00 /* Input Control */ +#define ADV7180_STATUS_1 0x10 /* Status #1 */ +#define ADV7180_BRIGHTNESS 0x0a /* Brightness */ +#define ADV7180_IDENT 0x11 /* IDENT */ +#define ADV7180_VSYNC_FIELD_CTL_1 0x31 /* VSYNC Field Control #1 */ +#define ADV7180_MANUAL_WIN_CTL 0x3d /* Manual Window Control */ +#define ADV7180_SD_SATURATION_CB 0xe3 /* SD Saturation Cb */ +#define ADV7180_SD_SATURATION_CR 0xe4 /* SD Saturation Cr */ +#define ADV7180_PWR_MNG 0x0f /* Power Management */ + +/* supported controls */ +/* This hasn't been fully implemented yet. + * This is how it should work, though. */ +static struct v4l2_queryctrl adv7180_qctrl[] = { + { + .id = V4L2_CID_BRIGHTNESS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Brightness", + .minimum = 0, /* check this value */ + .maximum = 255, /* check this value */ + .step = 1, /* check this value */ + .default_value = 127, /* check this value */ + .flags = 0, + }, { + .id = V4L2_CID_SATURATION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Saturation", + .minimum = 0, /* check this value */ + .maximum = 255, /* check this value */ + .step = 0x1, /* check this value */ + .default_value = 127, /* check this value */ + .flags = 0, + } +}; + +/*********************************************************************** + * I2C transfert. + ***********************************************************************/ + +/*! Read one register from a ADV7180 i2c slave device. + * + * @param *reg register in the device we wish to access. + * + * @return 0 if success, an error code otherwise. + */ +static inline int adv7180_read(u8 reg) +{ + int val; + val = i2c_smbus_read_byte_data(adv7180_data.i2c_client, reg); + if (val < 0) { + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:read reg error: reg=%2x \n", __func__, reg); + return -1; + } + return val; +} + +/*! Write one register of a ADV7180 i2c slave device. + * + * @param *reg register in the device we wish to access. + * + * @return 0 if success, an error code otherwise. + */ +static int adv7180_write_reg(u8 reg, u8 val) +{ + if (i2c_smbus_write_byte_data(adv7180_data.i2c_client, reg, val) < 0) { + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:write reg error:reg=%2x,val=%2x\n", __func__, + reg, val); + return -1; + } + return 0; +} + +/*********************************************************************** + * mxc_v4l2_capture interface. + ***********************************************************************/ + +/*! + * Return attributes of current video standard. + * Since this device autodetects the current standard, this function also + * sets the values that need to be changed if the standard changes. + * There is no set std equivalent function. + * + * @return None. + */ +static void adv7180_get_std(v4l2_std_id *std) +{ + int tmp; + int idx; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_get_std\n"); + + /* Make sure power on */ + if (tvin_plat->pwdn) + tvin_plat->pwdn(0); + + /* Read the AD_RESULT to get the detect output video standard */ + tmp = adv7180_read(ADV7180_STATUS_1) & 0x70; + + down(&mutex); + if (tmp == 0x40) { + /* PAL */ + *std = V4L2_STD_PAL; + idx = ADV7180_PAL; + } else if (tmp == 0) { + /*NTSC*/ + *std = V4L2_STD_NTSC; + idx = ADV7180_NTSC; + } else { + *std = V4L2_STD_ALL; + idx = ADV7180_NOT_LOCKED; + dev_dbg(&adv7180_data.i2c_client->dev, + "Got invalid video standard! \n"); + } + up(&mutex); + + /* This assumes autodetect which this device uses. */ + if (*std != adv7180_data.std_id) { + video_idx = idx; + adv7180_data.std_id = *std; + adv7180_data.pix.width = video_fmts[video_idx].raw_width; + adv7180_data.pix.height = video_fmts[video_idx].raw_height; + } +} + +/*********************************************************************** + * IOCTL Functions from v4l2_int_ioctl_desc. + ***********************************************************************/ + +/*! + * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num + * s: pointer to standard V4L2 device structure + * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure + * + * Gets slave interface parameters. + * Calculates the required xclk value to support the requested + * clock parameters in p. This value is returned in the p + * parameter. + * + * vidioc_int_g_ifparm returns platform-specific information about the + * interface settings used by the sensor. + * + * Called on open. + */ +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_ifparm\n"); + + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + /* Initialize structure to 0s then set any non-0 values. */ + memset(p, 0, sizeof(*p)); + p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */ + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.nobt_hs_inv = 1; + + /* ADV7180 has a dedicated clock so no clock settings needed. */ + + return 0; +} + +/*! + * Sets the camera power. + * + * s pointer to the camera device + * on if 1, power is to be turned on. 0 means power is to be turned off + * + * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num + * @s: pointer to standard V4L2 device structure + * @on: power state to which device is to be set + * + * Sets devices power state to requrested state, if possible. + * This is called on open, close, suspend and resume. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_power\n"); + + if (on && !sensor->on) { + gpio_sensor_active(); + + /* Make sure pwoer on */ + if (tvin_plat->pwdn) + tvin_plat->pwdn(0); + + if (adv7180_write_reg(ADV7180_PWR_MNG, 0) != 0) + return -EIO; + } else if (!on && sensor->on) { + if (adv7180_write_reg(ADV7180_PWR_MNG, 0x24) != 0) + return -EIO; + gpio_sensor_inactive(); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_parm\n"); + + switch (a->type) { + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + break; + + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + pr_debug("ioctl_g_parm:type is unknown %d\n", a->type); + break; + } + + return 0; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + * + * This driver cannot change these settings. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_parm\n"); + + switch (a->type) { + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + break; + } + + return 0; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_fmt_cap\n"); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" Returning size of %dx%d\n", + sensor->pix.width, sensor->pix.height); + f->fmt.pix = sensor->pix; + break; + + case V4L2_BUF_TYPE_PRIVATE: { + v4l2_std_id std; + adv7180_get_std(&std); + f->fmt.pix.pixelformat = (u32)std; + } + break; + + default: + f->fmt.pix = sensor->pix; + break; + } + + return 0; +} + +/*! + * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl + * @s: pointer to standard V4L2 device structure + * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure + * + * If the requested control is supported, returns the control information + * from the video_control[] array. Otherwise, returns -EINVAL if the + * control is not supported. + */ +static int ioctl_queryctrl(struct v4l2_int_device *s, + struct v4l2_queryctrl *qc) +{ + int i; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_queryctrl\n"); + + for (i = 0; i < ARRAY_SIZE(adv7180_qctrl); i++) + if (qc->id && qc->id == adv7180_qctrl[i].id) { + memcpy(qc, &(adv7180_qctrl[i]), + sizeof(*qc)); + return 0; + } + + return -EINVAL; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_g_ctrl\n"); + + /* Make sure power on */ + if (tvin_plat->pwdn) + tvin_plat->pwdn(0); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_BRIGHTNESS\n"); + adv7180_data.brightness = adv7180_read(ADV7180_BRIGHTNESS); + vc->value = adv7180_data.brightness; + break; + case V4L2_CID_CONTRAST: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_CONTRAST\n"); + vc->value = adv7180_data.contrast; + break; + case V4L2_CID_SATURATION: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_SATURATION\n"); + adv7180_data.saturation = adv7180_read(ADV7180_SD_SATURATION_CB); + vc->value = adv7180_data.saturation; + break; + case V4L2_CID_HUE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_HUE\n"); + vc->value = adv7180_data.hue; + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_RED_BALANCE\n"); + vc->value = adv7180_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_BLUE_BALANCE\n"); + vc->value = adv7180_data.blue; + break; + case V4L2_CID_GAMMA: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_EXPOSURE\n"); + vc->value = adv7180_data.ae_mode; + break; + case V4L2_CID_AUTOGAIN: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_VFLIP\n"); + break; + default: + dev_dbg(&adv7180_data.i2c_client->dev, + " Default case\n"); + vc->value = 0; + ret = -EPERM; + break; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + u8 tmp; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_s_ctrl\n"); + + /* Make sure power on */ + if (tvin_plat->pwdn) + tvin_plat->pwdn(0); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_BRIGHTNESS\n"); + tmp = vc->value; + adv7180_write_reg(ADV7180_BRIGHTNESS, tmp); + adv7180_data.brightness = vc->value; + break; + case V4L2_CID_CONTRAST: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_CONTRAST\n"); + break; + case V4L2_CID_SATURATION: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_SATURATION\n"); + tmp = vc->value; + adv7180_write_reg(ADV7180_SD_SATURATION_CB, tmp); + adv7180_write_reg(ADV7180_SD_SATURATION_CR, tmp); + adv7180_data.saturation = vc->value; + break; + case V4L2_CID_HUE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_HUE\n"); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_RED_BALANCE\n"); + break; + case V4L2_CID_BLUE_BALANCE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_BLUE_BALANCE\n"); + break; + case V4L2_CID_GAMMA: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_EXPOSURE\n"); + break; + case V4L2_CID_AUTOGAIN: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + dev_dbg(&adv7180_data.i2c_client->dev, + " V4L2_CID_VFLIP\n"); + break; + default: + dev_dbg(&adv7180_data.i2c_client->dev, + " Default case\n"); + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_g_chip_ident - V4L2 sensor interface handler for + * VIDIOC_DBG_G_CHIP_IDENT ioctl + * @s: pointer to standard V4L2 device structure + * @id: pointer to int + * + * Return 0. + */ +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, + "adv7180_decoder"); + ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_ADV7180; + + return 0; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_init\n"); + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180:ioctl_dev_init\n"); + return 0; +} + +/*! + * This structure defines all the ioctls for this module. + */ +static struct v4l2_int_ioctl_desc adv7180_ioctl_desc[] = { + + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, + + /*! + * Delinitialise the dev. at slave detach. + * The complement of ioctl_dev_init. + */ +/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */ + + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init}, + + /*! + * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. + */ +/* {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */ + + /*! + * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. + * This ioctl is used to negotiate the image capture size and + * pixel format without actually making it take effect. + */ +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, + + /*! + * If the requested format is supported, configures the HW to use that + * format, returns error code if format not supported or HW can't be + * correctly configured. + */ +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, + {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl}, + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl}, + {vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *)ioctl_g_chip_ident}, +}; + +static struct v4l2_int_slave adv7180_slave = { + .ioctls = adv7180_ioctl_desc, + .num_ioctls = ARRAY_SIZE(adv7180_ioctl_desc), +}; + +static struct v4l2_int_device adv7180_int_device = { + .module = THIS_MODULE, + .name = "adv7180", + .type = v4l2_int_type_slave, + .u = { + .slave = &adv7180_slave, + }, +}; + + +/*********************************************************************** + * I2C client and driver. + ***********************************************************************/ + +/*! ADV7180 Reset function. + * + * @return None. + */ +static void adv7180_hard_reset(bool cvbs) +{ + dev_dbg(&adv7180_data.i2c_client->dev, + "In adv7180:adv7180_hard_reset\n"); + + if (cvbs) { + /* Set CVBS input on AIN1 */ + adv7180_write_reg(ADV7180_INPUT_CTL, 0x00); + } else { + /* + * Set YPbPr input on AIN1,4,5 and normal + * operations(autodection of all stds). + */ + adv7180_write_reg(ADV7180_INPUT_CTL, 0x09); + } + + /* Datasheet recommends */ + adv7180_write_reg(ADV7180_VSYNC_FIELD_CTL_1, 0x02); + adv7180_write_reg(ADV7180_MANUAL_WIN_CTL, 0xa2); +} + +/*! ADV7180 I2C attach function. + * + * @param *adapter struct i2c_adapter *. + * + * @return Error code indicating success or failure. + */ + +/*! + * ADV7180 I2C probe function. + * Function set in i2c_driver struct. + * Called by insmod. + * + * @param *adapter I2C adapter descriptor. + * + * @return Error code indicating success or failure. + */ +static int adv7180_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int rev_id; + int ret = 0; + tvin_plat = client->dev.platform_data; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_probe\n"); + + if (tvin_plat->dvddio_reg) { + dvddio_regulator = + regulator_get(&client->dev, tvin_plat->dvddio_reg); + if (!IS_ERR_VALUE((unsigned long)dvddio_regulator)) { + regulator_set_voltage(dvddio_regulator, 3300000, 3300000); + if (regulator_enable(dvddio_regulator) != 0) + return -ENODEV; + } + } + + if (tvin_plat->dvdd_reg) { + dvdd_regulator = + regulator_get(&client->dev, tvin_plat->dvdd_reg); + if (!IS_ERR_VALUE((unsigned long)dvdd_regulator)) { + regulator_set_voltage(dvdd_regulator, 1800000, 1800000); + if (regulator_enable(dvdd_regulator) != 0) + return -ENODEV; + } + } + + if (tvin_plat->avdd_reg) { + avdd_regulator = + regulator_get(&client->dev, tvin_plat->avdd_reg); + if (!IS_ERR_VALUE((unsigned long)avdd_regulator)) { + regulator_set_voltage(avdd_regulator, 1800000, 1800000); + if (regulator_enable(avdd_regulator) != 0) + return -ENODEV; + } + } + + if (tvin_plat->pvdd_reg) { + pvdd_regulator = + regulator_get(&client->dev, tvin_plat->pvdd_reg); + if (!IS_ERR_VALUE((unsigned long)pvdd_regulator)) { + regulator_set_voltage(pvdd_regulator, 1800000, 1800000); + if (regulator_enable(pvdd_regulator) != 0) + return -ENODEV; + } + } + + + if (tvin_plat->reset) + tvin_plat->reset(); + + if (tvin_plat->pwdn) + tvin_plat->pwdn(0); + + msleep(1); + + /* Set initial values for the sensor struct. */ + memset(&adv7180_data, 0, sizeof(adv7180_data)); + adv7180_data.i2c_client = client; + adv7180_data.streamcap.timeperframe.denominator = 30; + adv7180_data.streamcap.timeperframe.numerator = 1; + adv7180_data.std_id = V4L2_STD_ALL; + video_idx = ADV7180_NOT_LOCKED; + adv7180_data.pix.width = video_fmts[video_idx].raw_width; + adv7180_data.pix.height = video_fmts[video_idx].raw_height; + adv7180_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */ + adv7180_data.pix.priv = 1; /* 1 is used to indicate TV in */ + adv7180_data.on = true; + + gpio_sensor_active(); + + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:adv7180 probe i2c address is 0x%02X \n", + __func__, adv7180_data.i2c_client->addr); + + /*! Read the revision ID of the tvin chip */ + rev_id = adv7180_read(ADV7180_IDENT); + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:Analog Device adv7%2X0 detected! \n", __func__, + rev_id); + + /*! ADV7180 initialization. */ + adv7180_hard_reset(tvin_plat->cvbs); + + pr_debug(" type is %d (expect %d)\n", + adv7180_int_device.type, v4l2_int_type_slave); + pr_debug(" num ioctls is %d\n", + adv7180_int_device.u.slave->num_ioctls); + + /* This function attaches this structure to the /dev/video0 device. + * The pointer in priv points to the mt9v111_data structure here.*/ + adv7180_int_device.priv = &adv7180_data; + ret = v4l2_int_device_register(&adv7180_int_device); + + return ret; +} + +/*! + * ADV7180 I2C detach function. + * Called on rmmod. + * + * @param *client struct i2c_client*. + * + * @return Error code indicating success or failure. + */ +static int adv7180_detach(struct i2c_client *client) +{ + struct mxc_tvin_platform_data *plat_data = client->dev.platform_data; + + dev_dbg(&adv7180_data.i2c_client->dev, + "%s:Removing %s video decoder @ 0x%02X from adapter %s \n", + __func__, IF_NAME, client->addr << 1, client->adapter->name); + + if (plat_data->pwdn) + plat_data->pwdn(1); + + if (dvddio_regulator) { + regulator_disable(dvddio_regulator); + regulator_put(dvddio_regulator); + } + + if (dvdd_regulator) { + regulator_disable(dvdd_regulator); + regulator_put(dvdd_regulator); + } + + if (avdd_regulator) { + regulator_disable(avdd_regulator); + regulator_put(avdd_regulator); + } + + if (pvdd_regulator) { + regulator_disable(pvdd_regulator); + regulator_put(pvdd_regulator); + } + + v4l2_int_device_unregister(&adv7180_int_device); + + return 0; +} + +/*! + * ADV7180 init function. + * Called on insmod. + * + * @return Error code indicating success or failure. + */ +static __init int adv7180_init(void) +{ + u8 err = 0; + + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_init\n"); + + /* Tells the i2c driver what functions to call for this driver. */ + err = i2c_add_driver(&adv7180_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * ADV7180 cleanup function. + * Called on rmmod. + * + * @return Error code indicating success or failure. + */ +static void __exit adv7180_clean(void) +{ + dev_dbg(&adv7180_data.i2c_client->dev, "In adv7180_clean\n"); + i2c_del_driver(&adv7180_i2c_driver); + gpio_sensor_inactive(); +} + +module_init(adv7180_init); +module_exit(adv7180_clean); + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("Anolog Device ADV7180 video decoder driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/csi_v4l2_capture.c b/drivers/media/video/mxc/capture/csi_v4l2_capture.c new file mode 100644 index 000000000000..cf224e0673f0 --- /dev/null +++ b/drivers/media/video/mxc/capture/csi_v4l2_capture.c @@ -0,0 +1,1466 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/media/video/mxc/capture/csi_v4l2_capture.c + * This file is derived from mxc_v4l2_capture.c + * + * @brief MX25 Video For Linux 2 driver + * + * @ingroup MXC_V4L2_CAPTURE + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "fsl_csi.h" + +static int video_nr = -1; +static cam_data *g_cam; + +static int csi_v4l2_master_attach(struct v4l2_int_device *slave); +static void csi_v4l2_master_detach(struct v4l2_int_device *slave); +static u8 camera_power(cam_data *cam, bool cameraOn); + +/*! Information about this driver. */ +static struct v4l2_int_master csi_v4l2_master = { + .attach = csi_v4l2_master_attach, + .detach = csi_v4l2_master_detach, +}; + +static struct v4l2_int_device csi_v4l2_int_device = { + .module = THIS_MODULE, + .name = "csi_v4l2_cap", + .type = v4l2_int_type_master, + .u = { + .master = &csi_v4l2_master, + }, +}; + +/*! + * Camera V4l2 callback function. + * + * @param mask u32 + * @param dev void device structure + * + * @return none + */ +static void camera_callback(u32 mask, void *dev) +{ + struct mxc_v4l_frame *done_frame; + struct mxc_v4l_frame *ready_frame; + cam_data *cam; + + cam = (cam_data *) dev; + if (cam == NULL) + return; + + if (list_empty(&cam->working_q)) { + pr_err("ERROR: v4l2 capture: %s: " + "working queue empty\n", __func__); + return; + } + + done_frame = + list_entry(cam->working_q.next, struct mxc_v4l_frame, queue); + if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { + done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE; + done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; + if (list_empty(&cam->ready_q)) { + cam->skip_frame++; + } else { + ready_frame = list_entry(cam->ready_q.next, + struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&ready_frame->queue, &cam->working_q); + + if (cam->ping_pong_csi == 1) { + __raw_writel(cam->frame[ready_frame->index]. + paddress, CSI_CSIDMASA_FB1); + } else { + __raw_writel(cam->frame[ready_frame->index]. + paddress, CSI_CSIDMASA_FB2); + } + } + + /* Added to the done queue */ + list_del(cam->working_q.next); + list_add_tail(&done_frame->queue, &cam->done_q); + cam->enc_counter++; + wake_up_interruptible(&cam->enc_queue); + } else { + pr_err("ERROR: v4l2 capture: %s: " + "buffer not queued\n", __func__); + } + + return; +} + +/*! + * Make csi ready for capture image. + * + * @param cam structure cam_data * + * + * @return status 0 success + */ +static int csi_cap_image(cam_data *cam) +{ + unsigned int value; + + value = __raw_readl(CSI_CSICR3); + __raw_writel(value | BIT_DMA_REFLASH_RFF | BIT_FRMCNT_RST, CSI_CSICR3); + value = __raw_readl(CSI_CSISR); + __raw_writel(value, CSI_CSISR); + + return 0; +} + +/*************************************************************************** + * Functions for handling Frame buffers. + **************************************************************************/ + +/*! + * Free frame buffers + * + * @param cam Structure cam_data * + * + * @return status 0 success. + */ +static int csi_free_frame_buf(cam_data *cam) +{ + int i; + + pr_debug("MVC: In %s\n", __func__); + + for (i = 0; i < FRAME_NUM; i++) { + if (cam->frame[i].vaddress != 0) { + dma_free_coherent(0, cam->frame[i].buffer.length, + cam->frame[i].vaddress, + cam->frame[i].paddress); + cam->frame[i].vaddress = 0; + } + } + + return 0; +} + +/*! + * Allocate frame buffers + * + * @param cam Structure cam_data * + * @param count int number of buffer need to allocated + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int csi_allocate_frame_buf(cam_data *cam, int count) +{ + int i; + + pr_debug("In MVC:%s- size=%d\n", + __func__, cam->v2f.fmt.pix.sizeimage); + for (i = 0; i < count; i++) { + cam->frame[i].vaddress = dma_alloc_coherent(0, PAGE_ALIGN + (cam->v2f.fmt. + pix.sizeimage), + &cam->frame[i]. + paddress, + GFP_DMA | + GFP_KERNEL); + if (cam->frame[i].vaddress == 0) { + pr_err("ERROR: v4l2 capture: " + "%s failed.\n", __func__); + csi_free_frame_buf(cam); + return -ENOBUFS; + } + cam->frame[i].buffer.index = i; + cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; + cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cam->frame[i].buffer.length = PAGE_ALIGN(cam->v2f.fmt. + pix.sizeimage); + cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP; + cam->frame[i].buffer.m.offset = cam->frame[i].paddress; + cam->frame[i].index = i; + } + + return 0; +} + +/*! + * Free frame buffers status + * + * @param cam Structure cam_data * + * + * @return none + */ +static void csi_free_frames(cam_data *cam) +{ + int i; + + pr_debug("In MVC: %s\n", __func__); + + for (i = 0; i < FRAME_NUM; i++) + cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; + + cam->skip_frame = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); + + return; +} + +/*! + * Return the buffer status + * + * @param cam Structure cam_data * + * @param buf Structure v4l2_buffer * + * + * @return status 0 success, EINVAL failed. + */ +static int csi_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf) +{ + pr_debug("In MVC: %s\n", __func__); + + if (buf->index < 0 || buf->index >= FRAME_NUM) { + pr_err("ERROR: v4l2 capture: %s buffers " + "not allocated\n", __func__); + return -EINVAL; + } + + memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf)); + + return 0; +} + +/*! + * Indicates whether the palette is supported. + * + * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_UYVY or V4L2_PIX_FMT_YUV420 + * + * @return 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + return (palette == V4L2_PIX_FMT_RGB565) || + (palette == V4L2_PIX_FMT_UYVY) || (palette == V4L2_PIX_FMT_YUV420); +} + +/*! + * Start stream I/O + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int csi_streamon(cam_data *cam) +{ + struct mxc_v4l_frame *frame; + + pr_debug("In MVC: %s\n", __func__); + + if (NULL == cam) { + pr_err("ERROR: v4l2 capture: %s cam parameter is NULL\n", + __func__); + return -1; + } + + /* move the frame from readyq to workingq */ + if (list_empty(&cam->ready_q)) { + pr_err("ERROR: v4l2 capture: %s: " + "ready_q queue empty\n", __func__); + return -1; + } + frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&frame->queue, &cam->working_q); + __raw_writel(cam->frame[frame->index].paddress, CSI_CSIDMASA_FB1); + + if (list_empty(&cam->ready_q)) { + pr_err("ERROR: v4l2 capture: %s: " + "ready_q queue empty\n", __func__); + return -1; + } + frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&frame->queue, &cam->working_q); + __raw_writel(cam->frame[frame->index].paddress, CSI_CSIDMASA_FB2); + + cam->capture_pid = current->pid; + cam->capture_on = true; + csi_cap_image(cam); + csi_enable_int(1); + + return 0; +} + +/*! + * Stop stream I/O + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int csi_streamoff(cam_data *cam) +{ + unsigned int cr3; + + pr_debug("In MVC: %s\n", __func__); + + if (cam->capture_on == false) + return 0; + + csi_disable_int(); + cam->capture_on = false; + + /* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */ + __raw_writel(0, CSI_CSIDMASA_FB1); + __raw_writel(0, CSI_CSIDMASA_FB2); + cr3 = __raw_readl(CSI_CSICR3); + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); + + csi_free_frames(cam); + csi_free_frame_buf(cam); + + return 0; +} + +/*! + * start the viewfinder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int start_preview(cam_data *cam) +{ + unsigned long fb_addr = (unsigned long)cam->v4l2_fb.base; + + __raw_writel(fb_addr, CSI_CSIDMASA_FB1); + __raw_writel(fb_addr, CSI_CSIDMASA_FB2); + __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, CSI_CSICR3); + + csi_enable_int(0); + + return 0; +} + +/*! + * shut down the viewfinder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int stop_preview(cam_data *cam) +{ + csi_disable_int(); + + /* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */ + __raw_writel(0, CSI_CSIDMASA_FB1); + __raw_writel(0, CSI_CSIDMASA_FB2); + __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, CSI_CSICR3); + + return 0; +} + +/*************************************************************************** + * VIDIOC Functions. + **************************************************************************/ + +/*! + * + * @param cam structure cam_data * + * + * @param f structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int csi_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f) +{ + int retval = 0; + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + f->fmt.pix = cam->v2f.fmt.pix; + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); + f->fmt.win = cam->win; + break; + default: + pr_debug(" type is invalid\n"); + retval = -EINVAL; + } + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + + return retval; +} + +/*! + * V4L2 - csi_v4l2_s_fmt function + * + * @param cam structure cam_data * + * + * @param f structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int csi_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f) +{ + int retval = 0; + int size = 0; + int bytesperline = 0; + int *width, *height; + + pr_debug("In MVC: %s\n", __func__); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + if (!valid_mode(f->fmt.pix.pixelformat)) { + pr_err("ERROR: v4l2 capture: %s: format " + "not supported\n", __func__); + return -EINVAL; + } + + /* Handle case where size requested is larger than cuurent + * camera setting. */ + if ((f->fmt.pix.width > cam->crop_bounds.width) + || (f->fmt.pix.height > cam->crop_bounds.height)) { + /* Need the logic here, calling vidioc_s_param if + * camera can change. */ + pr_debug("csi_v4l2_s_fmt size changed\n"); + } + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + height = &f->fmt.pix.width; + width = &f->fmt.pix.height; + } else { + width = &f->fmt.pix.width; + height = &f->fmt.pix.height; + } + + if ((cam->crop_bounds.width / *width > 8) || + ((cam->crop_bounds.width / *width == 8) && + (cam->crop_bounds.width % *width))) { + *width = cam->crop_bounds.width / 8; + if (*width % 8) + *width += 8 - *width % 8; + pr_err("ERROR: v4l2 capture: width exceeds limit " + "resize to %d.\n", *width); + } + + if ((cam->crop_bounds.height / *height > 8) || + ((cam->crop_bounds.height / *height == 8) && + (cam->crop_bounds.height % *height))) { + *height = cam->crop_bounds.height / 8; + if (*height % 8) + *height += 8 - *height % 8; + pr_err("ERROR: v4l2 capture: height exceeds limit " + "resize to %d.\n", *height); + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_RGB565: + size = f->fmt.pix.width * f->fmt.pix.height * 2; + csi_set_16bit_imagpara(f->fmt.pix.width, + f->fmt.pix.height); + bytesperline = f->fmt.pix.width * 2; + break; + case V4L2_PIX_FMT_UYVY: + size = f->fmt.pix.width * f->fmt.pix.height * 2; + csi_set_16bit_imagpara(f->fmt.pix.width, + f->fmt.pix.height); + bytesperline = f->fmt.pix.width * 2; + break; + case V4L2_PIX_FMT_YUV420: + size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; + csi_set_12bit_imagpara(f->fmt.pix.width, + f->fmt.pix.height); + bytesperline = f->fmt.pix.width; + break; + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_RGB24: + case V4L2_PIX_FMT_BGR24: + case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_RGB32: + case V4L2_PIX_FMT_NV12: + default: + pr_debug(" case not supported\n"); + break; + } + + if (f->fmt.pix.bytesperline < bytesperline) + f->fmt.pix.bytesperline = bytesperline; + else + bytesperline = f->fmt.pix.bytesperline; + + if (f->fmt.pix.sizeimage < size) + f->fmt.pix.sizeimage = size; + else + size = f->fmt.pix.sizeimage; + + cam->v2f.fmt.pix = f->fmt.pix; + + if (cam->v2f.fmt.pix.priv != 0) { + if (copy_from_user(&cam->offset, + (void *)cam->v2f.fmt.pix.priv, + sizeof(cam->offset))) { + retval = -EFAULT; + break; + } + } + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + pr_debug(" type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); + cam->win = f->fmt.win; + break; + default: + retval = -EINVAL; + } + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + + return retval; +} + +/*! + * V4L2 - csi_v4l2_s_param function + * Allows setting of capturemode and frame rate. + * + * @param cam structure cam_data * + * @param parm structure v4l2_streamparm * + * + * @return status 0 success, EINVAL failed + */ +static int csi_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) +{ + struct v4l2_ifparm ifparm; + struct v4l2_format cam_fmt; + struct v4l2_streamparm currentparm; + int err = 0; + + pr_debug("In %s\n", __func__); + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + pr_err(KERN_ERR "%s invalid type\n", __func__); + return -EINVAL; + } + + /* Stop the viewfinder */ + if (cam->overlay_on == true) + stop_preview(cam); + + currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + /* First check that this device can support the changes requested. */ + err = vidioc_int_g_parm(cam->sensor, ¤tparm); + if (err) { + pr_err("%s: vidioc_int_g_parm returned an error %d\n", + __func__, err); + goto exit; + } + + pr_debug(" Current capabilities are %x\n", + currentparm.parm.capture.capability); + pr_debug(" Current capturemode is %d change to %d\n", + currentparm.parm.capture.capturemode, + parm->parm.capture.capturemode); + pr_debug(" Current framerate is %d change to %d\n", + currentparm.parm.capture.timeperframe.denominator, + parm->parm.capture.timeperframe.denominator); + + err = vidioc_int_s_parm(cam->sensor, parm); + if (err) { + pr_err("%s: vidioc_int_s_parm returned an error %d\n", + __func__, err); + goto exit; + } + + vidioc_int_g_ifparm(cam->sensor, &ifparm); + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + pr_debug(" g_fmt_cap returns widthxheight of input as %d x %d\n", + cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); + +exit: + return err; +} + +/*! + * Dequeue one V4L capture buffer + * + * @param cam structure cam_data * + * @param buf structure v4l2_buffer * + * + * @return status 0 success, EINVAL invalid frame number + * ETIME timeout, ERESTARTSYS interrupted by user + */ +static int csi_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) +{ + int retval = 0; + struct mxc_v4l_frame *frame; + unsigned long lock_flags; + + if (!wait_event_interruptible_timeout(cam->enc_queue, + cam->enc_counter != 0, 10 * HZ)) { + pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout " + "enc_counter %x\n", cam->enc_counter); + return -ETIME; + } else if (signal_pending(current)) { + pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() " + "interrupt received\n"); + return -ERESTARTSYS; + } + + spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags); + + cam->enc_counter--; + + frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue); + list_del(cam->done_q.next); + + if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) { + frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE; + } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { + pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " + "Buffer not filled.\n"); + frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; + retval = -EINVAL; + } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) { + pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " + "Buffer not queued.\n"); + retval = -EINVAL; + } + + spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags); + + buf->bytesused = cam->v2f.fmt.pix.sizeimage; + buf->index = frame->index; + buf->flags = frame->buffer.flags; + buf->m = cam->frame[frame->index].buffer.m; + + return retval; +} + +/*! + * V4L interface - open function + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int csi_v4l_open(struct file *file) +{ + struct v4l2_ifparm ifparm; + struct v4l2_format cam_fmt; + struct video_device *dev = video_devdata(file); + cam_data *cam = video_get_drvdata(dev); + int err = 0; + + pr_debug(" device name is %s\n", dev->name); + + if (!cam) { + pr_err("ERROR: v4l2 capture: Internal error, " + "cam_data not found!\n"); + return -EBADF; + } + + down(&cam->busy_lock); + err = 0; + if (signal_pending(current)) + goto oops; + + if (cam->open_count++ == 0) { + wait_event_interruptible(cam->power_queue, + cam->low_power == false); + + cam->enc_counter = 0; + cam->skip_frame = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); + + vidioc_int_g_ifparm(cam->sensor, &ifparm); + + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + csi_enable_mclk(CSI_MCLK_I2C, true, true); + vidioc_int_init(cam->sensor); + } + + file->private_data = dev; + +oops: + up(&cam->busy_lock); + return err; +} + +/*! + * V4L interface - close function + * + * @param file struct file * + * + * @return 0 success + */ +static int csi_v4l_close(struct file *file) +{ + struct video_device *dev = video_devdata(file); + int err = 0; + cam_data *cam = video_get_drvdata(dev); + + pr_debug("In MVC:%s\n", __func__); + + if (!cam) { + pr_err("ERROR: v4l2 capture: Internal error, " + "cam_data not found!\n"); + return -EBADF; + } + + /* for the case somebody hit the ctrl C */ + if (cam->overlay_pid == current->pid) { + err = stop_preview(cam); + cam->overlay_on = false; + } + + if (--cam->open_count == 0) { + wait_event_interruptible(cam->power_queue, + cam->low_power == false); + file->private_data = NULL; + csi_enable_mclk(CSI_MCLK_I2C, false, false); + } + + return err; +} + +/* + * V4L interface - read function + * + * @param file struct file * + * @param read buf char * + * @param count size_t + * @param ppos structure loff_t * + * + * @return bytes read + */ +static ssize_t csi_v4l_read(struct file *file, char *buf, size_t count, + loff_t *ppos) +{ + int err = 0; + struct video_device *dev = video_devdata(file); + cam_data *cam = video_get_drvdata(dev); + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + /* Stop the viewfinder */ + if (cam->overlay_on == true) + stop_preview(cam); + + if (cam->still_buf_vaddr == NULL) { + cam->still_buf_vaddr = dma_alloc_coherent(0, + PAGE_ALIGN + (cam->v2f.fmt. + pix.sizeimage), + &cam-> + still_buf[0], + GFP_DMA | GFP_KERNEL); + if (cam->still_buf_vaddr == NULL) { + pr_err("alloc dma memory failed\n"); + return -ENOMEM; + } + cam->still_counter = 0; + __raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB2); + __raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB1); + __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, + CSI_CSICR3); + __raw_writel(__raw_readl(CSI_CSISR), CSI_CSISR); + __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, + CSI_CSICR3); + csi_enable_int(1); + } + + wait_event_interruptible(cam->still_queue, cam->still_counter); + csi_disable_int(); + err = copy_to_user(buf, cam->still_buf_vaddr, + cam->v2f.fmt.pix.sizeimage); + + if (cam->still_buf_vaddr != NULL) { + dma_free_coherent(0, PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + cam->still_buf_vaddr, cam->still_buf[0]); + cam->still_buf[0] = 0; + cam->still_buf_vaddr = NULL; + } + + if (cam->overlay_on == true) + start_preview(cam); + + up(&cam->busy_lock); + if (err < 0) + return err; + + return cam->v2f.fmt.pix.sizeimage - err; +} + +/*! + * V4L interface - ioctl function + * + * @param file struct file* + * + * @param ioctlnr unsigned int + * + * @param arg void* + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static long csi_v4l_do_ioctl(struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *dev = video_devdata(file); + cam_data *cam = video_get_drvdata(dev); + int retval = 0; + unsigned long lock_flags; + + pr_debug("In MVC: %s, %x\n", __func__, ioctlnr); + wait_event_interruptible(cam->power_queue, cam->low_power == false); + /* make this _really_ smp-safe */ + if (down_interruptible(&cam->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + /*! + * V4l2 VIDIOC_G_FMT ioctl + */ + case VIDIOC_G_FMT:{ + struct v4l2_format *gf = arg; + pr_debug(" case VIDIOC_G_FMT\n"); + retval = csi_v4l2_g_fmt(cam, gf); + break; + } + + /*! + * V4l2 VIDIOC_S_FMT ioctl + */ + case VIDIOC_S_FMT:{ + struct v4l2_format *sf = arg; + pr_debug(" case VIDIOC_S_FMT\n"); + retval = csi_v4l2_s_fmt(cam, sf); + vidioc_int_s_fmt_cap(cam->sensor, sf); + break; + } + + /*! + * V4l2 VIDIOC_OVERLAY ioctl + */ + case VIDIOC_OVERLAY:{ + int *on = arg; + pr_debug(" case VIDIOC_OVERLAY\n"); + if (*on) { + cam->overlay_on = true; + cam->overlay_pid = current->pid; + start_preview(cam); + } + if (!*on) { + stop_preview(cam); + cam->overlay_on = false; + } + break; + } + + /*! + * V4l2 VIDIOC_G_FBUF ioctl + */ + case VIDIOC_G_FBUF:{ + struct v4l2_framebuffer *fb = arg; + *fb = cam->v4l2_fb; + fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY; + break; + } + + /*! + * V4l2 VIDIOC_S_FBUF ioctl + */ + case VIDIOC_S_FBUF:{ + struct v4l2_framebuffer *fb = arg; + cam->v4l2_fb = *fb; + break; + } + + case VIDIOC_G_PARM:{ + struct v4l2_streamparm *parm = arg; + pr_debug(" case VIDIOC_G_PARM\n"); + vidioc_int_g_parm(cam->sensor, parm); + break; + } + + case VIDIOC_S_PARM:{ + struct v4l2_streamparm *parm = arg; + pr_debug(" case VIDIOC_S_PARM\n"); + retval = csi_v4l2_s_param(cam, parm); + break; + } + + case VIDIOC_QUERYCAP:{ + struct v4l2_capability *cap = arg; + pr_debug(" case VIDIOC_QUERYCAP\n"); + strcpy(cap->driver, "csi_v4l2"); + cap->version = KERNEL_VERSION(0, 1, 11); + cap->capabilities = V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_VIDEO_OUTPUT_OVERLAY | V4L2_CAP_READWRITE; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + break; + } + + case VIDIOC_S_CROP: + pr_debug(" case not supported\n"); + break; + + case VIDIOC_REQBUFS: { + struct v4l2_requestbuffers *req = arg; + pr_debug(" case VIDIOC_REQBUFS\n"); + + if (req->count > FRAME_NUM) { + pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " + "not enough buffers\n"); + req->count = FRAME_NUM; + } + + if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) || + (req->memory != V4L2_MEMORY_MMAP)) { + pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " + "wrong buffer type\n"); + retval = -EINVAL; + break; + } + + csi_streamoff(cam); + csi_free_frame_buf(cam); + cam->skip_frame = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); + retval = csi_allocate_frame_buf(cam, req->count); + break; + } + + case VIDIOC_QUERYBUF: { + struct v4l2_buffer *buf = arg; + int index = buf->index; + pr_debug(" case VIDIOC_QUERYBUF\n"); + + if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + retval = -EINVAL; + break; + } + + memset(buf, 0, sizeof(buf)); + buf->index = index; + retval = csi_v4l2_buffer_status(cam, buf); + break; + } + + case VIDIOC_QBUF: { + struct v4l2_buffer *buf = arg; + int index = buf->index; + pr_debug(" case VIDIOC_QBUF\n"); + + spin_lock_irqsave(&cam->queue_int_lock, lock_flags); + cam->frame[index].buffer.m.offset = buf->m.offset; + if ((cam->frame[index].buffer.flags & 0x7) == + V4L2_BUF_FLAG_MAPPED) { + cam->frame[index].buffer.flags |= V4L2_BUF_FLAG_QUEUED; + if (cam->skip_frame > 0) { + list_add_tail(&cam->frame[index].queue, + &cam->working_q); + cam->skip_frame = 0; + + if (cam->ping_pong_csi == 1) { + __raw_writel(cam->frame[index].paddress, + CSI_CSIDMASA_FB1); + } else { + __raw_writel(cam->frame[index].paddress, + CSI_CSIDMASA_FB2); + } + } else { + list_add_tail(&cam->frame[index].queue, + &cam->ready_q); + } + } else if (cam->frame[index].buffer.flags & + V4L2_BUF_FLAG_QUEUED) { + pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " + "buffer already queued\n"); + retval = -EINVAL; + } else if (cam->frame[index].buffer. + flags & V4L2_BUF_FLAG_DONE) { + pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " + "overwrite done buffer.\n"); + cam->frame[index].buffer.flags &= + ~V4L2_BUF_FLAG_DONE; + cam->frame[index].buffer.flags |= + V4L2_BUF_FLAG_QUEUED; + retval = -EINVAL; + } + buf->flags = cam->frame[index].buffer.flags; + spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags); + + break; + } + + case VIDIOC_DQBUF: { + struct v4l2_buffer *buf = arg; + pr_debug(" case VIDIOC_DQBUF\n"); + + retval = csi_v4l_dqueue(cam, buf); + + break; + } + + case VIDIOC_STREAMON: { + pr_debug(" case VIDIOC_STREAMON\n"); + retval = csi_streamon(cam); + break; + } + + case VIDIOC_STREAMOFF: { + pr_debug(" case VIDIOC_STREAMOFF\n"); + retval = csi_streamoff(cam); + break; + } + + case VIDIOC_S_CTRL: + case VIDIOC_G_STD: + case VIDIOC_G_OUTPUT: + case VIDIOC_S_OUTPUT: + case VIDIOC_ENUMSTD: + case VIDIOC_G_CROP: + case VIDIOC_CROPCAP: + case VIDIOC_S_STD: + case VIDIOC_G_CTRL: + case VIDIOC_ENUM_FMT: + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_ENUMINPUT: + case VIDIOC_G_INPUT: + case VIDIOC_S_INPUT: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + case VIDIOC_ENUMOUTPUT: + default: + pr_debug(" case not supported\n"); + retval = -EINVAL; + break; + } + + up(&cam->busy_lock); + return retval; +} + +/* + * V4L interface - ioctl function + * + * @return None + */ +static long csi_v4l_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + return video_usercopy(file, cmd, arg, csi_v4l_do_ioctl); +} + +/*! + * V4L interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error + */ +static int csi_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *dev = video_devdata(file); + unsigned long size; + int res = 0; + cam_data *cam = video_get_drvdata(dev); + + pr_debug("%s\n", __func__); + pr_debug("\npgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + size = vma->vm_end - vma->vm_start; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + pr_err("ERROR: v4l2 capture: %s : " + "remap_pfn_range failed\n", __func__); + res = -ENOBUFS; + goto csi_mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + +csi_mmap_exit: + up(&cam->busy_lock); + return res; +} + +/*! + * This structure defines the functions to be called in this driver. + */ +static struct v4l2_file_operations csi_v4l_fops = { + .owner = THIS_MODULE, + .open = csi_v4l_open, + .release = csi_v4l_close, + .read = csi_v4l_read, + .ioctl = csi_v4l_ioctl, + .mmap = csi_mmap, +}; + +static struct video_device csi_v4l_template = { + .name = "Mx25 Camera", + .fops = &csi_v4l_fops, + .release = video_device_release, +}; + +/*! + * This function can be used to release any platform data on closing. + */ +static void camera_platform_release(struct device *device) +{ +} + +/*! Device Definition for csi v4l2 device */ +static struct platform_device csi_v4l2_devices = { + .name = "csi_v4l2", + .dev = { + .release = camera_platform_release, + }, + .id = 0, +}; + +/*! + * initialize cam_data structure + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static void init_camera_struct(cam_data *cam) +{ + pr_debug("In MVC: %s\n", __func__); + + /* Default everything to 0 */ + memset(cam, 0, sizeof(cam_data)); + + init_MUTEX(&cam->param_lock); + init_MUTEX(&cam->busy_lock); + + cam->video_dev = video_device_alloc(); + if (cam->video_dev == NULL) + return; + + *(cam->video_dev) = csi_v4l_template; + + video_set_drvdata(cam->video_dev, cam); + dev_set_drvdata(&csi_v4l2_devices.dev, (void *)cam); + cam->video_dev->minor = -1; + + init_waitqueue_head(&cam->enc_queue); + init_waitqueue_head(&cam->still_queue); + + cam->streamparm.parm.capture.capturemode = 0; + + cam->standard.index = 0; + cam->standard.id = V4L2_STD_UNKNOWN; + cam->standard.frameperiod.denominator = 30; + cam->standard.frameperiod.numerator = 1; + cam->standard.framelines = 480; + cam->standard_autodetect = true; + cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod; + cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + cam->overlay_on = false; + cam->capture_on = false; + cam->skip_frame = 0; + cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY; + + cam->v2f.fmt.pix.sizeimage = 480 * 640 * 2; + cam->v2f.fmt.pix.bytesperline = 640 * 2; + cam->v2f.fmt.pix.width = 640; + cam->v2f.fmt.pix.height = 480; + cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_UYVY; + cam->win.w.width = 160; + cam->win.w.height = 160; + cam->win.w.left = 0; + cam->win.w.top = 0; + cam->still_counter = 0; + + cam->enc_callback = camera_callback; + csi_start_callback(cam); + init_waitqueue_head(&cam->power_queue); + spin_lock_init(&cam->queue_int_lock); + spin_lock_init(&cam->dqueue_int_lock); +} + +/*! + * camera_power function + * Turns Sensor power On/Off + * + * @param cam cam data struct + * @param cameraOn true to turn camera on, false to turn off power. + * + * @return status + */ +static u8 camera_power(cam_data *cam, bool cameraOn) +{ + pr_debug("In MVC: %s on=%d\n", __func__, cameraOn); + + if (cameraOn == true) { + csi_enable_mclk(CSI_MCLK_I2C, true, true); + vidioc_int_s_power(cam->sensor, 1); + } else { + csi_enable_mclk(CSI_MCLK_I2C, false, false); + vidioc_int_s_power(cam->sensor, 0); + } + return 0; +} + +/*! + * This function is called to put the sensor in a low power state. + * Refer to the document driver-model/driver.txt in the kernel source tree + * for more information. + * + * @param pdev the device structure used to give information on which I2C + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure. + */ +static int csi_v4l2_suspend(struct platform_device *pdev, pm_message_t state) +{ + cam_data *cam = platform_get_drvdata(pdev); + + pr_debug("In MVC: %s\n", __func__); + + if (cam == NULL) + return -1; + + cam->low_power = true; + + if (cam->overlay_on == true) + stop_preview(cam); + + camera_power(cam, false); + + return 0; +} + +/*! + * This function is called to bring the sensor back from a low power state. + * Refer to the document driver-model/driver.txt in the kernel source tree + * for more information. + * + * @param pdev the device structure + * + * @return The function returns 0 on success and -1 on failure + */ +static int csi_v4l2_resume(struct platform_device *pdev) +{ + cam_data *cam = platform_get_drvdata(pdev); + + pr_debug("In MVC: %s\n", __func__); + + if (cam == NULL) + return -1; + + cam->low_power = false; + wake_up_interruptible(&cam->power_queue); + camera_power(cam, true); + + if (cam->overlay_on == true) + start_preview(cam); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver csi_v4l2_driver = { + .driver = { + .name = "csi_v4l2", + }, + .probe = NULL, + .remove = NULL, +#ifdef CONFIG_PM + .suspend = csi_v4l2_suspend, + .resume = csi_v4l2_resume, +#endif + .shutdown = NULL, +}; + +/*! + * Initializes the camera driver. + */ +static int csi_v4l2_master_attach(struct v4l2_int_device *slave) +{ + cam_data *cam = slave->u.slave->master->priv; + struct v4l2_format cam_fmt; + + pr_debug("In MVC: %s\n", __func__); + pr_debug(" slave.name = %s\n", slave->name); + pr_debug(" master.name = %s\n", slave->u.slave->master->name); + + cam->sensor = slave; + if (slave == NULL) { + pr_err("ERROR: v4l2 capture: slave parameter not valid.\n"); + return -1; + } + + csi_enable_mclk(CSI_MCLK_I2C, true, true); + vidioc_int_dev_init(slave); + csi_enable_mclk(CSI_MCLK_I2C, false, false); + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + /* Used to detect TV in (type 1) vs. camera (type 0) */ + cam->device_type = cam_fmt.fmt.pix.priv; + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + + return 0; +} + +/*! + * Disconnects the camera driver. + */ +static void csi_v4l2_master_detach(struct v4l2_int_device *slave) +{ + pr_debug("In MVC: %s\n", __func__); + + vidioc_int_dev_exit(slave); +} + +/*! + * Entry point for the V4L2 + * + * @return Error code indicating success or failure + */ +static __init int camera_init(void) +{ + u8 err = 0; + + /* Register the device driver structure. */ + err = platform_driver_register(&csi_v4l2_driver); + if (err != 0) { + pr_err("ERROR: v4l2 capture:camera_init: " + "platform_driver_register failed.\n"); + return err; + } + + /* Create g_cam and initialize it. */ + g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL); + if (g_cam == NULL) { + pr_err("ERROR: v4l2 capture: failed to register camera\n"); + platform_driver_unregister(&csi_v4l2_driver); + return -1; + } + init_camera_struct(g_cam); + + /* Set up the v4l2 device and register it */ + csi_v4l2_int_device.priv = g_cam; + /* This function contains a bug that won't let this be rmmod'd. */ + v4l2_int_device_register(&csi_v4l2_int_device); + + /* Register the platform device */ + err = platform_device_register(&csi_v4l2_devices); + if (err != 0) { + pr_err("ERROR: v4l2 capture: camera_init: " + "platform_device_register failed.\n"); + platform_driver_unregister(&csi_v4l2_driver); + kfree(g_cam); + g_cam = NULL; + return err; + } + + /* register v4l video device */ + if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr) + == -1) { + platform_device_unregister(&csi_v4l2_devices); + platform_driver_unregister(&csi_v4l2_driver); + kfree(g_cam); + g_cam = NULL; + pr_err("ERROR: v4l2 capture: video_register_device failed\n"); + return -1; + } + pr_debug(" Video device registered: %s #%d\n", + g_cam->video_dev->name, g_cam->video_dev->minor); + + return err; +} + +/*! + * Exit and cleanup for the V4L2 + */ +static void __exit camera_exit(void) +{ + pr_debug("In MVC: %s\n", __func__); + + if (g_cam->open_count) { + pr_err("ERROR: v4l2 capture:camera open " + "-- setting ops to NULL\n"); + } else { + pr_info("V4L2 freeing image input device\n"); + v4l2_int_device_unregister(&csi_v4l2_int_device); + csi_stop_callback(g_cam); + video_unregister_device(g_cam->video_dev); + platform_driver_unregister(&csi_v4l2_driver); + platform_device_unregister(&csi_v4l2_devices); + + kfree(g_cam); + g_cam = NULL; + } +} + +module_init(camera_init); +module_exit(camera_exit); + +module_param(video_nr, int, 0444); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2 capture driver for Mx25 based cameras"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff --git a/drivers/media/video/mxc/capture/fsl_csi.c b/drivers/media/video/mxc/capture/fsl_csi.c new file mode 100644 index 000000000000..3de83762bbc6 --- /dev/null +++ b/drivers/media/video/mxc/capture/fsl_csi.c @@ -0,0 +1,287 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_csi.c, this file is derived from mx27_csi.c + * + * @brief mx25 CMOS Sensor interface functions + * + * @ingroup CSI + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_v4l2_capture.h" +#include "fsl_csi.h" + +static bool g_csi_mclk_on; +static csi_irq_callback_t g_callback; +static void *g_callback_data; +static struct clk csi_mclk; + +static irqreturn_t csi_irq_handler(int irq, void *data) +{ + cam_data *cam = (cam_data *) data; + unsigned long status = __raw_readl(CSI_CSISR); + unsigned long cr3 = __raw_readl(CSI_CSICR3); + unsigned int frame_count = (cr3 >> 16) & 0xFFFF; + + __raw_writel(status, CSI_CSISR); + + if (status & BIT_SOF_INT) { + /* reflash the embeded DMA controller */ + if (frame_count % 2 == 1) + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); + } + + if (status & BIT_DMA_TSF_DONE_FB1) { + if (cam->capture_on) { + cam->ping_pong_csi = 1; + cam->enc_callback(0, cam); + } else { + cam->still_counter++; + wake_up_interruptible(&cam->still_queue); + } + } + + if (status & BIT_DMA_TSF_DONE_FB2) { + if (cam->capture_on) { + cam->ping_pong_csi = 2; + cam->enc_callback(0, cam); + } else { + cam->still_counter++; + wake_up_interruptible(&cam->still_queue); + } + } + + if (g_callback) + g_callback(g_callback_data, status); + + pr_debug("CSI status = 0x%08lX\n", status); + + return IRQ_HANDLED; +} + +static void csihw_reset_frame_count(void) +{ + __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3); +} + +static void csihw_reset(void) +{ + csihw_reset_frame_count(); + __raw_writel(CSICR1_RESET_VAL, CSI_CSICR1); + __raw_writel(CSICR2_RESET_VAL, CSI_CSICR2); + __raw_writel(CSICR3_RESET_VAL, CSI_CSICR3); +} + +/*! + * csi_init_interface + * Init csi interface + */ +void csi_init_interface(void) +{ + unsigned int val = 0; + unsigned int imag_para; + + val |= BIT_SOF_POL; + val |= BIT_REDGE; + val |= BIT_GCLK_MODE; + val |= BIT_HSYNC_POL; + val |= BIT_PACK_DIR; + val |= BIT_FCC; + val |= BIT_SWAP16_EN; + val |= 1 << SHIFT_MCLKDIV; + __raw_writel(val, CSI_CSICR1); + + imag_para = (640 << 16) | 960; + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + val = 0x1010; + val |= BIT_DMA_REFLASH_RFF; + __raw_writel(val, CSI_CSICR3); +} +EXPORT_SYMBOL(csi_init_interface); + +/*! + * csi_enable_mclk + * + * @param src enum define which source to control the clk + * CSI_MCLK_VF CSI_MCLK_ENC CSI_MCLK_RAW CSI_MCLK_I2C + * @param flag true to enable mclk, false to disable mclk + * @param wait true to wait 100ms make clock stable, false not wait + * + * @return 0 for success + */ +int32_t csi_enable_mclk(int src, bool flag, bool wait) +{ + if (flag == true) { + csi_mclk_enable(); + if (wait == true) + msleep(10); + pr_debug("Enable csi clock from source %d\n", src); + g_csi_mclk_on = true; + } else { + csi_mclk_disable(); + pr_debug("Disable csi clock from source %d\n", src); + g_csi_mclk_on = false; + } + + return 0; +} +EXPORT_SYMBOL(csi_enable_mclk); + +/*! + * csi_read_mclk_flag + * + * @return gcsi_mclk_source + */ +int csi_read_mclk_flag(void) +{ + return 0; +} +EXPORT_SYMBOL(csi_read_mclk_flag); + +void csi_start_callback(void *data) +{ + cam_data *cam = (cam_data *) data; + + if (request_irq(MXC_INT_CSI, csi_irq_handler, 0, "csi", cam) < 0) + pr_debug("CSI error: irq request fail\n"); + +} +EXPORT_SYMBOL(csi_start_callback); + +void csi_stop_callback(void *data) +{ + cam_data *cam = (cam_data *) data; + + free_irq(MXC_INT_CSI, cam); +} +EXPORT_SYMBOL(csi_stop_callback); + +void csi_enable_int(int arg) +{ + unsigned long cr1 = __raw_readl(CSI_CSICR1); + + cr1 |= BIT_SOF_INTEN; + if (arg == 1) { + /* still capture needs DMA intterrupt */ + cr1 |= BIT_FB1_DMA_DONE_INTEN; + cr1 |= BIT_FB2_DMA_DONE_INTEN; + } + __raw_writel(cr1, CSI_CSICR1); +} +EXPORT_SYMBOL(csi_enable_int); + +void csi_disable_int(void) +{ + unsigned long cr1 = __raw_readl(CSI_CSICR1); + + cr1 &= ~BIT_SOF_INTEN; + cr1 &= ~BIT_FB1_DMA_DONE_INTEN; + cr1 &= ~BIT_FB2_DMA_DONE_INTEN; + __raw_writel(cr1, CSI_CSICR1); +} +EXPORT_SYMBOL(csi_disable_int); + +void csi_set_16bit_imagpara(int width, int height) +{ + int imag_para = 0; + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + imag_para = (width << 16) | (height * 2); + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + /* reflash the embeded DMA controller */ + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); +} +EXPORT_SYMBOL(csi_set_16bit_imagpara); + +void csi_set_12bit_imagpara(int width, int height) +{ + int imag_para = 0; + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + imag_para = (width << 16) | (height * 3 / 2); + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + /* reflash the embeded DMA controller */ + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); +} +EXPORT_SYMBOL(csi_set_12bit_imagpara); + +static void csi_mclk_recalc(struct clk *clk) +{ + u32 div; + unsigned long rate; + + div = (__raw_readl(CSI_CSICR1) & BIT_MCLKDIV) >> SHIFT_MCLKDIV; + if (div == 0) + div = 1; + else + div = div * 2; + + rate = clk_get_rate(clk->parent) / div; + clk_set_rate(clk, rate); +} + +void csi_mclk_enable(void) +{ + __raw_writel(__raw_readl(CSI_CSICR1) | BIT_MCLKEN, CSI_CSICR1); +} + +void csi_mclk_disable(void) +{ + __raw_writel(__raw_readl(CSI_CSICR1) & ~BIT_MCLKEN, CSI_CSICR1); +} + +int32_t __init csi_init_module(void) +{ + int ret = 0; + struct clk *per_clk; + + csihw_reset(); + csi_init_interface(); + + per_clk = clk_get(NULL, "csi_clk"); + if (IS_ERR(per_clk)) + return PTR_ERR(per_clk); + + clk_put(per_clk); + csi_mclk.parent = per_clk; + clk_enable(per_clk); + csi_mclk_recalc(&csi_mclk); + + return ret; +} + +void __exit csi_cleanup_module(void) +{ + clk_disable(&csi_mclk); +} + +module_init(csi_init_module); +module_exit(csi_cleanup_module); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("fsl CSI driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/fsl_csi.h b/drivers/media/video/mxc/capture/fsl_csi.h new file mode 100644 index 000000000000..4d6babd3691d --- /dev/null +++ b/drivers/media/video/mxc/capture/fsl_csi.h @@ -0,0 +1,198 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_csi.h + * + * @brief mx25 CMOS Sensor interface functions + * + * @ingroup CSI + */ + +#ifndef MX25_CSI_H +#define MX25_CSI_H + +#include +#include + +/* reset values */ +#define CSICR1_RESET_VAL 0x40000800 +#define CSICR2_RESET_VAL 0x0 +#define CSICR3_RESET_VAL 0x0 + +/* csi control reg 1 */ +#define BIT_SWAP16_EN (0x1 << 31) +#define BIT_EXT_VSYNC (0x1 << 30) +#define BIT_EOF_INT_EN (0x1 << 29) +#define BIT_PRP_IF_EN (0x1 << 28) +#define BIT_CCIR_MODE (0x1 << 27) +#define BIT_COF_INT_EN (0x1 << 26) +#define BIT_SF_OR_INTEN (0x1 << 25) +#define BIT_RF_OR_INTEN (0x1 << 24) +#define BIT_SFF_DMA_DONE_INTEN (0x1 << 22) +#define BIT_STATFF_INTEN (0x1 << 21) +#define BIT_FB2_DMA_DONE_INTEN (0x1 << 20) +#define BIT_FB1_DMA_DONE_INTEN (0x1 << 19) +#define BIT_RXFF_INTEN (0x1 << 18) +#define BIT_SOF_POL (0x1 << 17) +#define BIT_SOF_INTEN (0x1 << 16) +#define BIT_MCLKDIV (0xF << 12) +#define BIT_HSYNC_POL (0x1 << 11) +#define BIT_CCIR_EN (0x1 << 10) +#define BIT_MCLKEN (0x1 << 9) +#define BIT_FCC (0x1 << 8) +#define BIT_PACK_DIR (0x1 << 7) +#define BIT_CLR_STATFIFO (0x1 << 6) +#define BIT_CLR_RXFIFO (0x1 << 5) +#define BIT_GCLK_MODE (0x1 << 4) +#define BIT_INV_DATA (0x1 << 3) +#define BIT_INV_PCLK (0x1 << 2) +#define BIT_REDGE (0x1 << 1) +#define BIT_PIXEL_BIT (0x1 << 0) + +#define SHIFT_MCLKDIV 12 + +/* control reg 3 */ +#define BIT_FRMCNT (0xFFFF << 16) +#define BIT_FRMCNT_RST (0x1 << 15) +#define BIT_DMA_REFLASH_RFF (0x1 << 14) +#define BIT_DMA_REFLASH_SFF (0x1 << 13) +#define BIT_DMA_REQ_EN_RFF (0x1 << 12) +#define BIT_DMA_REQ_EN_SFF (0x1 << 11) +#define BIT_STATFF_LEVEL (0x7 << 8) +#define BIT_HRESP_ERR_EN (0x1 << 7) +#define BIT_RXFF_LEVEL (0x7 << 4) +#define BIT_TWO_8BIT_SENSOR (0x1 << 3) +#define BIT_ZERO_PACK_EN (0x1 << 2) +#define BIT_ECC_INT_EN (0x1 << 1) +#define BIT_ECC_AUTO_EN (0x1 << 0) + +#define SHIFT_FRMCNT 16 + +/* csi status reg */ +#define BIT_SFF_OR_INT (0x1 << 25) +#define BIT_RFF_OR_INT (0x1 << 24) +#define BIT_DMA_TSF_DONE_SFF (0x1 << 22) +#define BIT_STATFF_INT (0x1 << 21) +#define BIT_DMA_TSF_DONE_FB2 (0x1 << 20) +#define BIT_DMA_TSF_DONE_FB1 (0x1 << 19) +#define BIT_RXFF_INT (0x1 << 18) +#define BIT_EOF_INT (0x1 << 17) +#define BIT_SOF_INT (0x1 << 16) +#define BIT_F2_INT (0x1 << 15) +#define BIT_F1_INT (0x1 << 14) +#define BIT_COF_INT (0x1 << 13) +#define BIT_HRESP_ERR_INT (0x1 << 7) +#define BIT_ECC_INT (0x1 << 1) +#define BIT_DRDY (0x1 << 0) + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 +#endif + +#define CSI_CSICR1 (IO_ADDRESS(CSI_BASE_ADDR)) +#define CSI_CSICR2 (IO_ADDRESS(CSI_BASE_ADDR + 0x4)) +#define CSI_CSICR3 (IO_ADDRESS(CSI_BASE_ADDR + 0x8)) +#define CSI_STATFIFO (IO_ADDRESS(CSI_BASE_ADDR + 0xC)) +#define CSI_CSIRXFIFO (IO_ADDRESS(CSI_BASE_ADDR + 0x10)) +#define CSI_CSIRXCNT (IO_ADDRESS(CSI_BASE_ADDR + 0x14)) +#define CSI_CSISR (IO_ADDRESS(CSI_BASE_ADDR + 0x18)) + +#define CSI_CSIDBG (IO_ADDRESS(CSI_BASE_ADDR + 0x1C)) +#define CSI_CSIDMASA_STATFIFO (IO_ADDRESS(CSI_BASE_ADDR + 0x20)) +#define CSI_CSIDMATS_STATFIFO (IO_ADDRESS(CSI_BASE_ADDR + 0x24)) +#define CSI_CSIDMASA_FB1 (IO_ADDRESS(CSI_BASE_ADDR + 0x28)) +#define CSI_CSIDMASA_FB2 (IO_ADDRESS(CSI_BASE_ADDR + 0x2C)) +#define CSI_CSIFBUF_PARA (IO_ADDRESS(CSI_BASE_ADDR + 0x30)) +#define CSI_CSIIMAG_PARA (IO_ADDRESS(CSI_BASE_ADDR + 0x34)) + +#define CSI_CSIRXFIFO_PHYADDR (CSI_BASE_ADDR + 0x10) + +static inline void csi_clear_status(unsigned long status) +{ + __raw_writel(status, CSI_CSISR); +} + +struct csi_signal_cfg_t { + unsigned data_width:3; + unsigned clk_mode:2; + unsigned ext_vsync:1; + unsigned Vsync_pol:1; + unsigned Hsync_pol:1; + unsigned pixclk_pol:1; + unsigned data_pol:1; + unsigned sens_clksrc:1; +}; + +struct csi_config_t { + /* control reg 1 */ + unsigned int swap16_en:1; + unsigned int ext_vsync:1; + unsigned int eof_int_en:1; + unsigned int prp_if_en:1; + unsigned int ccir_mode:1; + unsigned int cof_int_en:1; + unsigned int sf_or_inten:1; + unsigned int rf_or_inten:1; + unsigned int sff_dma_done_inten:1; + unsigned int statff_inten:1; + unsigned int fb2_dma_done_inten:1; + unsigned int fb1_dma_done_inten:1; + unsigned int rxff_inten:1; + unsigned int sof_pol:1; + unsigned int sof_inten:1; + unsigned int mclkdiv:4; + unsigned int hsync_pol:1; + unsigned int ccir_en:1; + unsigned int mclken:1; + unsigned int fcc:1; + unsigned int pack_dir:1; + unsigned int gclk_mode:1; + unsigned int inv_data:1; + unsigned int inv_pclk:1; + unsigned int redge:1; + unsigned int pixel_bit:1; + + /* control reg 3 */ + unsigned int frmcnt:16; + unsigned int frame_reset:1; + unsigned int dma_reflash_rff:1; + unsigned int dma_reflash_sff:1; + unsigned int dma_req_en_rff:1; + unsigned int dma_req_en_sff:1; + unsigned int statff_level:3; + unsigned int hresp_err_en:1; + unsigned int rxff_level:3; + unsigned int two_8bit_sensor:1; + unsigned int zero_pack_en:1; + unsigned int ecc_int_en:1; + unsigned int ecc_auto_en:1; + /* fifo counter */ + unsigned int rxcnt; +}; + +typedef void (*csi_irq_callback_t) (void *data, unsigned long status); + +int32_t csi_enable_mclk(int src, bool flag, bool wait); +void csi_init_interface(void); +void csi_set_16bit_imagpara(int width, int height); +void csi_set_12bit_imagpara(int width, int height); +int csi_read_mclk_flag(void); +void csi_start_callback(void *data); +void csi_stop_callback(void *data); +void csi_enable_int(int arg); +void csi_disable_int(void); +void csi_mclk_enable(void); +void csi_mclk_disable(void); diff --git a/drivers/media/video/mxc/capture/ipu_csi_enc.c b/drivers/media/video/mxc/capture/ipu_csi_enc.c new file mode 100644 index 000000000000..c8a4dab78cc7 --- /dev/null +++ b/drivers/media/video/mxc/capture/ipu_csi_enc.c @@ -0,0 +1,357 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_csi_enc.c + * + * @brief CSI Use case for video capture + * + * @ingroup IPU + */ + +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +#ifdef CAMERA_DBG + #define CAMERA_TRACE(x) (printk)x +#else + #define CAMERA_TRACE(x) +#endif + +/* + * Function definitions + */ + +/*! + * csi ENC callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t csi_enc_callback(int irq, void *dev_id) +{ + cam_data *cam = (cam_data *) dev_id; + + if (cam->enc_callback == NULL) + return IRQ_HANDLED; + + cam->enc_callback(irq, dev_id); + return IRQ_HANDLED; +} + +/*! + * CSI ENC enable channel setup function + * + * @param cam struct cam_data * mxc capture instance + * + * @return status + */ +static int csi_enc_setup(cam_data *cam) +{ + ipu_channel_params_t params; + u32 pixel_fmt; + int err = 0, sensor_protocol = 0; + dma_addr_t dummy = cam->dummy_frame.buffer.m.offset; + + CAMERA_TRACE("In csi_enc_setup\n"); + if (!cam) { + printk(KERN_ERR "cam private is NULL\n"); + return -ENXIO; + } + + memset(¶ms, 0, sizeof(ipu_channel_params_t)); + params.csi_mem.csi = cam->csi; + + sensor_protocol = ipu_csi_get_sensor_protocol(cam->csi); + switch (sensor_protocol) { + case IPU_CSI_CLK_MODE_GATED_CLK: + case IPU_CSI_CLK_MODE_NONGATED_CLK: + case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE: + case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR: + case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR: + params.csi_mem.interlaced = false; + break; + case IPU_CSI_CLK_MODE_CCIR656_INTERLACED: + case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR: + case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR: + params.csi_mem.interlaced = true; + break; + default: + printk(KERN_ERR "sensor protocol unsupported\n"); + return -EINVAL; + } + + if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + pixel_fmt = IPU_PIX_FMT_YUV420P; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) + pixel_fmt = IPU_PIX_FMT_YUV422P; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) + pixel_fmt = IPU_PIX_FMT_UYVY; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pixel_fmt = IPU_PIX_FMT_YUYV; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) + pixel_fmt = IPU_PIX_FMT_NV12; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) + pixel_fmt = IPU_PIX_FMT_BGR24; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) + pixel_fmt = IPU_PIX_FMT_RGB24; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) + pixel_fmt = IPU_PIX_FMT_RGB565; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) + pixel_fmt = IPU_PIX_FMT_BGR32; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) + pixel_fmt = IPU_PIX_FMT_RGB32; + else { + printk(KERN_ERR "format not supported\n"); + return -EINVAL; + } + + ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, true, true); + + err = ipu_init_channel(CSI_MEM, ¶ms); + if (err != 0) { + printk(KERN_ERR "ipu_init_channel %d\n", err); + return err; + } + + err = ipu_init_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, + pixel_fmt, cam->v2f.fmt.pix.width, + cam->v2f.fmt.pix.height, + cam->v2f.fmt.pix.width, IPU_ROTATE_NONE, + dummy, dummy, + cam->offset.u_offset, + cam->offset.v_offset); + if (err != 0) { + printk(KERN_ERR "CSI_MEM output buffer\n"); + return err; + } + err = ipu_enable_channel(CSI_MEM); + if (err < 0) { + printk(KERN_ERR "ipu_enable_channel CSI_MEM\n"); + return err; + } + + return err; +} + +/*! + * function to update physical buffer address for encorder IDMA channel + * + * @param eba physical buffer address for encorder IDMA channel + * @param buffer_num int buffer 0 or buffer 1 + * + * @return status + */ +static int csi_enc_eba_update(dma_addr_t eba, int *buffer_num) +{ + int err = 0; + + pr_debug("eba %x\n", eba); + err = ipu_update_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, + *buffer_num, eba); + if (err != 0) { + ipu_clear_buffer_ready(CSI_MEM, IPU_OUTPUT_BUFFER, + *buffer_num); + + err = ipu_update_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, + *buffer_num, eba); + if (err != 0) { + pr_err("ERROR: v4l2 capture: fail to update " + "buf%d\n", *buffer_num); + return err; + } + } + + ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, *buffer_num); + + *buffer_num = (*buffer_num == 0) ? 1 : 0; + + return 0; +} + +/*! + * Enable encoder task + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int csi_enc_enabling_tasks(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n"); + + cam->dummy_frame.vaddress = dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + &cam->dummy_frame.paddress, + GFP_DMA | GFP_KERNEL); + if (cam->dummy_frame.vaddress == 0) { + pr_err("ERROR: v4l2 capture: Allocate dummy frame " + "failed.\n"); + return -ENOBUFS; + } + cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE; + cam->dummy_frame.buffer.length = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress; + + ipu_clear_irq(IPU_IRQ_CSI0_OUT_EOF); + err = ipu_request_irq(IPU_IRQ_CSI0_OUT_EOF, + csi_enc_callback, 0, "Mxc Camera", cam); + if (err != 0) { + printk(KERN_ERR "Error registering rot irq\n"); + return err; + } + + err = csi_enc_setup(cam); + if (err != 0) { + printk(KERN_ERR "csi_enc_setup %d\n", err); + return err; + } + + return err; +} + +/*! + * Disable encoder task + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +static int csi_enc_disabling_tasks(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + ipu_free_irq(IPU_IRQ_CSI0_OUT_EOF, cam); + + err = ipu_disable_channel(CSI_MEM, true); + + ipu_uninit_channel(CSI_MEM); + + if (cam->dummy_frame.vaddress != 0) { + dma_free_coherent(0, cam->dummy_frame.buffer.length, + cam->dummy_frame.vaddress, + cam->dummy_frame.paddress); + cam->dummy_frame.vaddress = 0; + } + ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, false, false); + + return err; +} + +/*! + * Enable csi + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int csi_enc_enable_csi(void *private) +{ + cam_data *cam = (cam_data *) private; + + return ipu_enable_csi(cam->csi); +} + +/*! + * Disable csi + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int csi_enc_disable_csi(void *private) +{ + cam_data *cam = (cam_data *) private; + + return ipu_disable_csi(cam->csi); +} + +/*! + * function to select CSI ENC as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +int csi_enc_select(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam) { + cam->enc_update_eba = csi_enc_eba_update; + cam->enc_enable = csi_enc_enabling_tasks; + cam->enc_disable = csi_enc_disabling_tasks; + cam->enc_enable_csi = csi_enc_enable_csi; + cam->enc_disable_csi = csi_enc_disable_csi; + } else { + err = -EIO; + } + + return err; +} + +/*! + * function to de-select CSI ENC as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +int csi_enc_deselect(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam) { + cam->enc_update_eba = NULL; + cam->enc_enable = NULL; + cam->enc_disable = NULL; + cam->enc_enable_csi = NULL; + cam->enc_disable_csi = NULL; + } + + return err; +} + +/*! + * Init the Encorder channels + * + * @return Error code indicating success or failure + */ +__init int csi_enc_init(void) +{ + return 0; +} + +/*! + * Deinit the Encorder channels + * + */ +void __exit csi_enc_exit(void) +{ +} + +module_init(csi_enc_init); +module_exit(csi_enc_exit); + +EXPORT_SYMBOL(csi_enc_select); +EXPORT_SYMBOL(csi_enc_deselect); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("CSI ENC Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/ipu_prp_enc.c b/drivers/media/video/mxc/capture/ipu_prp_enc.c new file mode 100644 index 000000000000..67637dd150fc --- /dev/null +++ b/drivers/media/video/mxc/capture/ipu_prp_enc.c @@ -0,0 +1,530 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_enc.c + * + * @brief IPU Use case for PRP-ENC + * + * @ingroup IPU + */ + +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +#ifdef CAMERA_DBG + #define CAMERA_TRACE(x) (printk)x +#else + #define CAMERA_TRACE(x) +#endif + +static ipu_rotate_mode_t grotation = IPU_ROTATE_NONE; + +/* + * Function definitions + */ + +/*! + * IPU ENC callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prp_enc_callback(int irq, void *dev_id) +{ + cam_data *cam = (cam_data *) dev_id; + + if (cam->enc_callback == NULL) + return IRQ_HANDLED; + + cam->enc_callback(irq, dev_id); + + return IRQ_HANDLED; +} + +/*! + * PrpENC enable channel setup function + * + * @param cam struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_enc_setup(cam_data *cam) +{ + ipu_channel_params_t enc; + int err = 0; + dma_addr_t dummy = 0xdeadbeaf; + + CAMERA_TRACE("In prp_enc_setup\n"); + if (!cam) { + printk(KERN_ERR "cam private is NULL\n"); + return -ENXIO; + } + memset(&enc, 0, sizeof(ipu_channel_params_t)); + + ipu_csi_get_window_size(&enc.csi_prp_enc_mem.in_width, + &enc.csi_prp_enc_mem.in_height, cam->csi); + + enc.csi_prp_enc_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; + enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.width; + enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.height; + enc.csi_prp_enc_mem.csi = cam->csi; + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.height; + enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.width; + } + + if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV420P; + pr_info("YUV420\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV422P; + pr_info("YUV422P\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUYV; + pr_info("YUYV\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_UYVY; + pr_info("UYVY\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_NV12; + pr_info("NV12\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR24; + pr_info("BGR24\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB24; + pr_info("RGB24\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB565; + pr_info("RGB565\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR32; + pr_info("BGR32\n"); + } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) { + enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB32; + pr_info("RGB32\n"); + } else { + printk(KERN_ERR "format not supported\n"); + return -EINVAL; + } + + err = ipu_init_channel(CSI_PRP_ENC_MEM, &enc); + if (err != 0) { + printk(KERN_ERR "ipu_init_channel %d\n", err); + return err; + } + + ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, true, true); + + grotation = cam->rotation; + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + if (cam->rot_enc_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_enc_buf_size[0], + cam->rot_enc_bufs_vaddr[0], + cam->rot_enc_bufs[0]); + } + if (cam->rot_enc_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_enc_buf_size[1], + cam->rot_enc_bufs_vaddr[1], + cam->rot_enc_bufs[1]); + } + cam->rot_enc_buf_size[0] = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->rot_enc_bufs_vaddr[0] = + (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[0], + &cam->rot_enc_bufs[0], + GFP_DMA | GFP_KERNEL); + if (!cam->rot_enc_bufs_vaddr[0]) { + printk(KERN_ERR "alloc enc_bufs0\n"); + return -ENOMEM; + } + cam->rot_enc_buf_size[1] = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->rot_enc_bufs_vaddr[1] = + (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[1], + &cam->rot_enc_bufs[1], + GFP_DMA | GFP_KERNEL); + if (!cam->rot_enc_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_enc_buf_size[0], + cam->rot_enc_bufs_vaddr[0], + cam->rot_enc_bufs[0]); + cam->rot_enc_bufs_vaddr[0] = NULL; + cam->rot_enc_bufs[0] = 0; + printk(KERN_ERR "alloc enc_bufs1\n"); + return -ENOMEM; + } + + err = ipu_init_channel_buffer(CSI_PRP_ENC_MEM, + IPU_OUTPUT_BUFFER, + enc.csi_prp_enc_mem.out_pixel_fmt, + enc.csi_prp_enc_mem.out_width, + enc.csi_prp_enc_mem.out_height, + enc.csi_prp_enc_mem.out_width, + IPU_ROTATE_NONE, + cam->rot_enc_bufs[0], + cam->rot_enc_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "CSI_PRP_ENC_MEM err\n"); + return err; + } + + err = ipu_init_channel(MEM_ROT_ENC_MEM, NULL); + if (err != 0) { + printk(KERN_ERR "MEM_ROT_ENC_MEM channel err\n"); + return err; + } + + err = ipu_init_channel_buffer(MEM_ROT_ENC_MEM, IPU_INPUT_BUFFER, + enc.csi_prp_enc_mem.out_pixel_fmt, + enc.csi_prp_enc_mem.out_width, + enc.csi_prp_enc_mem.out_height, + enc.csi_prp_enc_mem.out_width, + cam->rotation, + cam->rot_enc_bufs[0], + cam->rot_enc_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "MEM_ROT_ENC_MEM input buffer\n"); + return err; + } + + err = + ipu_init_channel_buffer(MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER, + enc.csi_prp_enc_mem.out_pixel_fmt, + enc.csi_prp_enc_mem.out_height, + enc.csi_prp_enc_mem.out_width, + cam->v2f.fmt.pix.bytesperline / + bytes_per_pixel(enc.csi_prp_enc_mem. + out_pixel_fmt), + IPU_ROTATE_NONE, dummy, dummy, + cam->offset.u_offset, + cam->offset.v_offset); + if (err != 0) { + printk(KERN_ERR "MEM_ROT_ENC_MEM output buffer\n"); + return err; + } + + err = ipu_link_channels(CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM); + if (err < 0) { + printk(KERN_ERR + "link CSI_PRP_ENC_MEM-MEM_ROT_ENC_MEM\n"); + return err; + } + + err = ipu_enable_channel(CSI_PRP_ENC_MEM); + if (err < 0) { + printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n"); + return err; + } + err = ipu_enable_channel(MEM_ROT_ENC_MEM); + if (err < 0) { + printk(KERN_ERR "ipu_enable_channel MEM_ROT_ENC_MEM\n"); + return err; + } + + ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, 1); + } else { + err = + ipu_init_channel_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, + enc.csi_prp_enc_mem.out_pixel_fmt, + enc.csi_prp_enc_mem.out_width, + enc.csi_prp_enc_mem.out_height, + cam->v2f.fmt.pix.bytesperline / + bytes_per_pixel(enc.csi_prp_enc_mem. + out_pixel_fmt), + cam->rotation, dummy, dummy, + cam->offset.u_offset, + cam->offset.v_offset); + if (err != 0) { + printk(KERN_ERR "CSI_PRP_ENC_MEM output buffer\n"); + return err; + } + err = ipu_enable_channel(CSI_PRP_ENC_MEM); + if (err < 0) { + printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n"); + return err; + } + } + + return err; +} + +/*! + * function to update physical buffer address for encorder IDMA channel + * + * @param eba physical buffer address for encorder IDMA channel + * @param buffer_num int buffer 0 or buffer 1 + * + * @return status + */ +static int prp_enc_eba_update(dma_addr_t eba, int *buffer_num) +{ + int err = 0; + + pr_debug("eba %x\n", eba); + if (grotation >= IPU_ROTATE_90_RIGHT) { + err = ipu_update_channel_buffer(MEM_ROT_ENC_MEM, + IPU_OUTPUT_BUFFER, *buffer_num, + eba); + } else { + err = ipu_update_channel_buffer(CSI_PRP_ENC_MEM, + IPU_OUTPUT_BUFFER, *buffer_num, + eba); + } + if (err != 0) { + if (grotation >= IPU_ROTATE_90_RIGHT) { + ipu_clear_buffer_ready(MEM_ROT_ENC_MEM, + IPU_OUTPUT_BUFFER, + *buffer_num); + err = ipu_update_channel_buffer(MEM_ROT_ENC_MEM, + IPU_OUTPUT_BUFFER, + *buffer_num, + eba); + } else { + ipu_clear_buffer_ready(CSI_PRP_ENC_MEM, + IPU_OUTPUT_BUFFER, + *buffer_num); + err = ipu_update_channel_buffer(CSI_PRP_ENC_MEM, + IPU_OUTPUT_BUFFER, + *buffer_num, + eba); + } + + if (err != 0) { + pr_err("ERROR: v4l2 capture: fail to update " + "buf%d\n", *buffer_num); + return err; + } + } + + if (grotation >= IPU_ROTATE_90_RIGHT) { + ipu_select_buffer(MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER, + *buffer_num); + } else { + ipu_select_buffer(CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, + *buffer_num); + } + + *buffer_num = (*buffer_num == 0) ? 1 : 0; + return 0; +} + +/*! + * Enable encoder task + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_enc_enabling_tasks(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n"); + + cam->dummy_frame.vaddress = dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + &cam->dummy_frame.paddress, + GFP_DMA | GFP_KERNEL); + if (cam->dummy_frame.vaddress == 0) { + pr_err("ERROR: v4l2 capture: Allocate dummy frame " + "failed.\n"); + return -ENOBUFS; + } + cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE; + cam->dummy_frame.buffer.length = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress; + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + err = ipu_request_irq(IPU_IRQ_PRP_ENC_ROT_OUT_EOF, + prp_enc_callback, 0, "Mxc Camera", cam); + } else { + err = ipu_request_irq(IPU_IRQ_PRP_ENC_OUT_EOF, + prp_enc_callback, 0, "Mxc Camera", cam); + } + if (err != 0) { + printk(KERN_ERR "Error registering rot irq\n"); + return err; + } + + err = prp_enc_setup(cam); + if (err != 0) { + printk(KERN_ERR "prp_enc_setup %d\n", err); + return err; + } + + return err; +} + +/*! + * Disable encoder task + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +static int prp_enc_disabling_tasks(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_free_irq(IPU_IRQ_PRP_ENC_ROT_OUT_EOF, cam); + } else { + ipu_free_irq(IPU_IRQ_PRP_ENC_OUT_EOF, cam); + } + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_unlink_channels(CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM); + } + + err = ipu_disable_channel(CSI_PRP_ENC_MEM, true); + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + err |= ipu_disable_channel(MEM_ROT_ENC_MEM, true); + } + + ipu_uninit_channel(CSI_PRP_ENC_MEM); + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + ipu_uninit_channel(MEM_ROT_ENC_MEM); + } + + if (cam->dummy_frame.vaddress != 0) { + dma_free_coherent(0, cam->dummy_frame.buffer.length, + cam->dummy_frame.vaddress, + cam->dummy_frame.paddress); + cam->dummy_frame.vaddress = 0; + } + ipu_csi_enable_mclk_if(CSI_MCLK_ENC, cam->csi, false, false); + + return err; +} + +/*! + * Enable csi + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_enc_enable_csi(void *private) +{ + cam_data *cam = (cam_data *) private; + + return ipu_enable_csi(cam->csi); +} + +/*! + * Disable csi + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_enc_disable_csi(void *private) +{ + cam_data *cam = (cam_data *) private; + + return ipu_disable_csi(cam->csi); +} + +/*! + * function to select PRP-ENC as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +int prp_enc_select(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam) { + cam->enc_update_eba = prp_enc_eba_update; + cam->enc_enable = prp_enc_enabling_tasks; + cam->enc_disable = prp_enc_disabling_tasks; + cam->enc_enable_csi = prp_enc_enable_csi; + cam->enc_disable_csi = prp_enc_disable_csi; + } else { + err = -EIO; + } + + return err; +} + +/*! + * function to de-select PRP-ENC as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return int + */ +int prp_enc_deselect(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + if (cam) { + cam->enc_update_eba = NULL; + cam->enc_enable = NULL; + cam->enc_disable = NULL; + cam->enc_enable_csi = NULL; + cam->enc_disable_csi = NULL; + if (cam->rot_enc_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_enc_buf_size[0], + cam->rot_enc_bufs_vaddr[0], + cam->rot_enc_bufs[0]); + cam->rot_enc_bufs_vaddr[0] = NULL; + cam->rot_enc_bufs[0] = 0; + } + if (cam->rot_enc_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_enc_buf_size[1], + cam->rot_enc_bufs_vaddr[1], + cam->rot_enc_bufs[1]); + cam->rot_enc_bufs_vaddr[1] = NULL; + cam->rot_enc_bufs[1] = 0; + } + } + + return err; +} + +/*! + * Init the Encorder channels + * + * @return Error code indicating success or failure + */ +__init int prp_enc_init(void) +{ + return 0; +} + +/*! + * Deinit the Encorder channels + * + */ +void __exit prp_enc_exit(void) +{ +} + +module_init(prp_enc_init); +module_exit(prp_enc_exit); + +EXPORT_SYMBOL(prp_enc_select); +EXPORT_SYMBOL(prp_enc_deselect); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP ENC Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/ipu_prp_sw.h b/drivers/media/video/mxc/capture/ipu_prp_sw.h new file mode 100644 index 000000000000..85dd102471f8 --- /dev/null +++ b/drivers/media/video/mxc/capture/ipu_prp_sw.h @@ -0,0 +1,36 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_sw.h + * + * @brief This file contains the IPU PRP use case driver header. + * + * @ingroup IPU + */ + +#ifndef _INCLUDE_IPU__PRP_SW_H_ +#define _INCLUDE_IPU__PRP_SW_H_ + +int csi_enc_select(void *private); +int csi_enc_deselect(void *private); +int prp_enc_select(void *private); +int prp_enc_deselect(void *private); +int prp_vf_sdc_select(void *private); +int prp_vf_sdc_select_bg(void *private); +int prp_vf_sdc_deselect(void *private); +int prp_vf_sdc_deselect_bg(void *private); +int prp_still_select(void *private); +int prp_still_deselect(void *private); + +#endif diff --git a/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c new file mode 100644 index 000000000000..27fa92f165d0 --- /dev/null +++ b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c @@ -0,0 +1,482 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_vf_sdc.c + * + * @brief IPU Use case for PRP-VF + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +#define OVERLAY_FB_SUPPORT_NONSTD (cpu_is_mx5()) + +/* + * Function definitions + */ + +/*! + * prpvf_start - start the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_start(void *private) +{ + struct fb_var_screeninfo fbvar; + struct fb_info *fbi = NULL; + cam_data *cam = (cam_data *) private; + ipu_channel_params_t vf; + u32 vf_out_format = 0; + u32 size = 2, temp = 0; + int err = 0, i = 0; + short *tmp, color; + + if (!cam) { + printk(KERN_ERR "private is NULL\n"); + return -EIO; + } + + if (cam->overlay_active == true) { + pr_debug("already started.\n"); + return 0; + } + + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strcmp(idstr, "DISP3 FG") == 0) { + fbi = registered_fb[i]; + break; + } + } + + if (fbi == NULL) { + printk(KERN_ERR "DISP3 FG fb not found\n"); + return -EPERM; + } + + fbvar = fbi->var; + + /* Store the overlay frame buffer's original std */ + cam->fb_origin_std = fbvar.nonstd; + + if (OVERLAY_FB_SUPPORT_NONSTD) { + /* Use DP to do CSC so that we can get better performance */ + vf_out_format = IPU_PIX_FMT_UYVY; + fbvar.nonstd = vf_out_format; + color = 0x80; + } else { + vf_out_format = IPU_PIX_FMT_RGB565; + fbvar.nonstd = 0; + color = 0x0; + } + + fbvar.bits_per_pixel = 16; + fbvar.xres = fbvar.xres_virtual = cam->win.w.width; + fbvar.yres = cam->win.w.height; + fbvar.yres_virtual = cam->win.w.height * 2; + fbvar.yoffset = 0; + fbvar.activate |= FB_ACTIVATE_FORCE; + fb_set_var(fbi, &fbvar); + + ipu_disp_set_window_pos(MEM_FG_SYNC, cam->win.w.left, + cam->win.w.top); + + /* Fill black color for framebuffer */ + tmp = (short *) fbi->screen_base; + for (i = 0; i < (fbi->fix.line_length * fbi->var.yres)/2; + i++, tmp++) + *tmp = color; + + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_UNBLANK); + release_console_sem(); + + /* correct display ch buffer address */ + ipu_update_channel_buffer(MEM_FG_SYNC, IPU_INPUT_BUFFER, + 0, fbi->fix.smem_start + + (fbi->fix.line_length * fbvar.yres)); + ipu_update_channel_buffer(MEM_FG_SYNC, IPU_INPUT_BUFFER, + 1, fbi->fix.smem_start); + + memset(&vf, 0, sizeof(ipu_channel_params_t)); + ipu_csi_get_window_size(&vf.csi_prp_vf_mem.in_width, + &vf.csi_prp_vf_mem.in_height, cam->csi); + vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; + vf.csi_prp_vf_mem.out_width = cam->win.w.width; + vf.csi_prp_vf_mem.out_height = cam->win.w.height; + vf.csi_prp_vf_mem.csi = cam->csi; + if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) { + vf.csi_prp_vf_mem.out_width = cam->win.w.height; + vf.csi_prp_vf_mem.out_height = cam->win.w.width; + } + vf.csi_prp_vf_mem.out_pixel_fmt = vf_out_format; + size = cam->win.w.width * cam->win.w.height * size; + + err = ipu_init_channel(CSI_PRP_VF_MEM, &vf); + if (err != 0) + goto out_5; + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], + (dma_addr_t) cam->vf_bufs[0]); + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], + (dma_addr_t) cam->vf_bufs[1]); + } + cam->vf_bufs_size[0] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, + cam->vf_bufs_size[0], + (dma_addr_t *) & + cam->vf_bufs[0], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[0] == NULL) { + printk(KERN_ERR "Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_4; + } + cam->vf_bufs_size[1] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, + cam->vf_bufs_size[1], + (dma_addr_t *) & + cam->vf_bufs[1], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[1] == NULL) { + printk(KERN_ERR "Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]); + + if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) { + err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, + vf_out_format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + IPU_ROTATE_NONE, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + goto out_3; + } + + err = ipu_init_channel(MEM_ROT_VF_MEM, NULL); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n"); + goto out_3; + } + + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER, + vf_out_format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + cam->vf_rotation, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n"); + goto out_2; + } + + if (cam->vf_rotation < IPU_ROTATE_90_RIGHT) { + temp = vf.csi_prp_vf_mem.out_width; + vf.csi_prp_vf_mem.out_width = + vf.csi_prp_vf_mem.out_height; + vf.csi_prp_vf_mem.out_height = temp; + } + + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, + vf_out_format, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + IPU_ROTATE_NONE, + fbi->fix.smem_start + + (fbi->fix.line_length * + fbi->var.yres), + fbi->fix.smem_start, 0, 0); + + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); + goto out_2; + } + + err = ipu_link_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); + if (err < 0) { + printk(KERN_ERR + "Error link CSI_PRP_VF_MEM-MEM_ROT_VF_MEM\n"); + goto out_2; + } + + err = ipu_link_channels(MEM_ROT_VF_MEM, MEM_FG_SYNC); + if (err < 0) { + printk(KERN_ERR + "Error link MEM_ROT_VF_MEM-MEM_FG_SYNC\n"); + goto out_1; + } + + ipu_enable_channel(CSI_PRP_VF_MEM); + ipu_enable_channel(MEM_ROT_VF_MEM); + + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1); + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 1); + } else { + err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, + vf_out_format, cam->win.w.width, + cam->win.w.height, + cam->win.w.width, + cam->vf_rotation, + fbi->fix.smem_start + + (fbi->fix.line_length * + fbi->var.yres), + fbi->fix.smem_start, 0, 0); + if (err != 0) { + printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n"); + goto out_4; + } + + err = ipu_link_channels(CSI_PRP_VF_MEM, MEM_FG_SYNC); + if (err < 0) { + printk(KERN_ERR "Error linking ipu channels\n"); + goto out_4; + } + + ipu_enable_channel(CSI_PRP_VF_MEM); + + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 1); + } + + cam->overlay_active = true; + return err; + +out_1: + ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); +out_2: + if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) { + ipu_uninit_channel(MEM_ROT_VF_MEM); + } +out_3: + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], + (dma_addr_t) cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], + (dma_addr_t) cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } +out_4: + ipu_uninit_channel(CSI_PRP_VF_MEM); +out_5: + return err; +} + +/*! + * prpvf_stop - stop the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_stop(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0, i = 0; + struct fb_info *fbi = NULL; + struct fb_var_screeninfo fbvar; + + if (cam->overlay_active == false) + return 0; + + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strcmp(idstr, "DISP3 FG") == 0) { + fbi = registered_fb[i]; + break; + } + } + + if (fbi == NULL) { + printk(KERN_ERR "DISP3 FG fb not found\n"); + return -EPERM; + } + + if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) { + ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); + ipu_unlink_channels(MEM_ROT_VF_MEM, MEM_FG_SYNC); + } else { + ipu_unlink_channels(CSI_PRP_VF_MEM, MEM_FG_SYNC); + } + + ipu_disable_channel(CSI_PRP_VF_MEM, true); + + if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) { + ipu_disable_channel(MEM_ROT_VF_MEM, true); + ipu_uninit_channel(MEM_ROT_VF_MEM); + } + ipu_uninit_channel(CSI_PRP_VF_MEM); + + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_POWERDOWN); + release_console_sem(); + + /* Set the overlay frame buffer std to what it is used to be */ + fbvar = fbi->var; + fbvar.nonstd = cam->fb_origin_std; + fbvar.activate |= FB_ACTIVATE_FORCE; + fb_set_var(fbi, &fbvar); + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], + (dma_addr_t) cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], + (dma_addr_t) cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + + cam->overlay_active = false; + return err; +} + +/*! + * Enable csi + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_vf_enable_csi(void *private) +{ + cam_data *cam = (cam_data *) private; + + return ipu_enable_csi(cam->csi); +} + +/*! + * Disable csi + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_vf_disable_csi(void *private) +{ + cam_data *cam = (cam_data *) private; + + return ipu_disable_csi(cam->csi); +} + +/*! + * function to select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return status + */ +int prp_vf_sdc_select(void *private) +{ + cam_data *cam; + int err = 0; + if (private) { + cam = (cam_data *) private; + cam->vf_start_sdc = prpvf_start; + cam->vf_stop_sdc = prpvf_stop; + cam->vf_enable_csi = prp_vf_enable_csi; + cam->vf_disable_csi = prp_vf_disable_csi; + cam->overlay_active = false; + } else + err = -EIO; + + return err; +} + +/*! + * function to de-select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return int + */ +int prp_vf_sdc_deselect(void *private) +{ + cam_data *cam; + int err = 0; + err = prpvf_stop(private); + + if (private) { + cam = (cam_data *) private; + cam->vf_start_sdc = NULL; + cam->vf_stop_sdc = NULL; + cam->vf_enable_csi = NULL; + cam->vf_disable_csi = NULL; + } + return err; +} + +/*! + * Init viewfinder task. + * + * @return Error code indicating success or failure + */ +__init int prp_vf_sdc_init(void) +{ + return 0; +} + +/*! + * Deinit viewfinder task. + * + * @return Error code indicating success or failure + */ +void __exit prp_vf_sdc_exit(void) +{ +} + +module_init(prp_vf_sdc_init); +module_exit(prp_vf_sdc_exit); + +EXPORT_SYMBOL(prp_vf_sdc_select); +EXPORT_SYMBOL(prp_vf_sdc_deselect); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP VF SDC Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c new file mode 100644 index 000000000000..4e21f0c93b32 --- /dev/null +++ b/drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c @@ -0,0 +1,443 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_prp_vf_sdc_bg.c + * + * @brief IPU Use case for PRP-VF back-ground + * + * @ingroup IPU + */ +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +static int buffer_num; +static int buffer_ready; + +/* + * Function definitions + */ + +/*! + * SDC V-Sync callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prpvf_sdc_vsync_callback(int irq, void *dev_id) +{ + pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num); + if (buffer_ready > 0) { + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0); + buffer_ready--; + } + + return IRQ_HANDLED; +} + +/*! + * VF EOF callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prpvf_vf_eof_callback(int irq, void *dev_id) +{ + pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num); + + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER, buffer_num); + + buffer_num = (buffer_num == 0) ? 1 : 0; + + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, buffer_num); + buffer_ready++; + return IRQ_HANDLED; +} + +/*! + * prpvf_start - start the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_start(void *private) +{ + cam_data *cam = (cam_data *) private; + ipu_channel_params_t vf; + u32 format; + u32 offset; + u32 bpp, size = 3; + int err = 0; + + if (!cam) { + printk(KERN_ERR "private is NULL\n"); + return -EIO; + } + + if (cam->overlay_active == true) { + pr_debug("already start.\n"); + return 0; + } + + format = cam->v4l2_fb.fmt.pixelformat; + if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) { + bpp = 3, size = 3; + pr_info("BGR24\n"); + } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) { + bpp = 2, size = 2; + pr_info("RGB565\n"); + } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) { + bpp = 4, size = 4; + pr_info("BGR32\n"); + } else { + printk(KERN_ERR + "unsupported fix format from the framebuffer.\n"); + return -EINVAL; + } + + offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top + + size * cam->win.w.left; + + if (cam->v4l2_fb.base == 0) { + printk(KERN_ERR "invalid frame buffer address.\n"); + } else { + offset += (u32) cam->v4l2_fb.base; + } + + memset(&vf, 0, sizeof(ipu_channel_params_t)); + ipu_csi_get_window_size(&vf.csi_prp_vf_mem.in_width, + &vf.csi_prp_vf_mem.in_height, cam->csi); + vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; + vf.csi_prp_vf_mem.out_width = cam->win.w.width; + vf.csi_prp_vf_mem.out_height = cam->win.w.height; + vf.csi_prp_vf_mem.csi = cam->csi; + if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) { + vf.csi_prp_vf_mem.out_width = cam->win.w.height; + vf.csi_prp_vf_mem.out_height = cam->win.w.width; + } + vf.csi_prp_vf_mem.out_pixel_fmt = format; + size = cam->win.w.width * cam->win.w.height * size; + + err = ipu_init_channel(CSI_PRP_VF_MEM, &vf); + if (err != 0) + goto out_4; + + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, true, true); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); + } + cam->vf_bufs_size[0] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, + cam->vf_bufs_size[0], + &cam->vf_bufs[0], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[0] == NULL) { + printk(KERN_ERR "Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + cam->vf_bufs_size[1] = PAGE_ALIGN(size); + cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, + cam->vf_bufs_size[1], + &cam->vf_bufs[1], + GFP_DMA | + GFP_KERNEL); + if (cam->vf_bufs_vaddr[1] == NULL) { + printk(KERN_ERR "Error to allocate vf buffer\n"); + err = -ENOMEM; + goto out_3; + } + + err = ipu_init_channel_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, + format, vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + IPU_ROTATE_NONE, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n"); + goto out_3; + } + err = ipu_init_channel(MEM_ROT_VF_MEM, NULL); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n"); + goto out_3; + } + + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_INPUT_BUFFER, + format, vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + cam->vf_rotation, cam->vf_bufs[0], + cam->vf_bufs[1], 0, 0); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n"); + goto out_2; + } + + if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) { + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_height, + vf.csi_prp_vf_mem.out_width, + cam->overlay_fb->var.xres * bpp, + IPU_ROTATE_NONE, offset, 0, 0, 0); + + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); + goto out_2; + } + } else { + err = ipu_init_channel_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, + format, + vf.csi_prp_vf_mem.out_width, + vf.csi_prp_vf_mem.out_height, + cam->overlay_fb->var.xres * bpp, + IPU_ROTATE_NONE, offset, 0, 0, 0); + if (err != 0) { + printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); + goto out_2; + } + } + + ipu_clear_irq(IPU_IRQ_PRP_VF_OUT_EOF); + err = ipu_request_irq(IPU_IRQ_PRP_VF_OUT_EOF, prpvf_vf_eof_callback, + 0, "Mxc Camera", cam); + if (err != 0) { + printk(KERN_ERR + "Error registering IPU_IRQ_PRP_VF_OUT_EOF irq.\n"); + goto out_2; + } + + ipu_clear_irq(IPU_IRQ_BG_SF_END); + err = ipu_request_irq(IPU_IRQ_BG_SF_END, prpvf_sdc_vsync_callback, + 0, "Mxc Camera", NULL); + if (err != 0) { + printk(KERN_ERR "Error registering IPU_IRQ_BG_SF_END irq.\n"); + goto out_1; + } + + ipu_enable_channel(CSI_PRP_VF_MEM); + ipu_enable_channel(MEM_ROT_VF_MEM); + + buffer_num = 0; + buffer_ready = 0; + ipu_select_buffer(CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); + + cam->overlay_active = true; + return err; + + out_1: + ipu_free_irq(IPU_IRQ_PRP_VF_OUT_EOF, NULL); + out_2: + ipu_uninit_channel(MEM_ROT_VF_MEM); + out_3: + ipu_uninit_channel(CSI_PRP_VF_MEM); + out_4: + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + if (cam->rot_vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + return err; +} + +/*! + * prpvf_stop - stop the vf task + * + * @param private cam_data * mxc v4l2 main structure + * + */ +static int prpvf_stop(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (cam->overlay_active == false) + return 0; + + ipu_free_irq(IPU_IRQ_BG_SF_END, NULL); + + ipu_free_irq(IPU_IRQ_PRP_VF_OUT_EOF, cam); + + ipu_disable_channel(CSI_PRP_VF_MEM, true); + ipu_disable_channel(MEM_ROT_VF_MEM, true); + ipu_uninit_channel(CSI_PRP_VF_MEM); + ipu_uninit_channel(MEM_ROT_VF_MEM); + ipu_csi_enable_mclk_if(CSI_MCLK_VF, cam->csi, false, false); + + if (cam->vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->vf_bufs_size[0], + cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); + cam->vf_bufs_vaddr[0] = NULL; + cam->vf_bufs[0] = 0; + } + if (cam->vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->vf_bufs_size[1], + cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); + cam->vf_bufs_vaddr[1] = NULL; + cam->vf_bufs[1] = 0; + } + if (cam->rot_vf_bufs_vaddr[0]) { + dma_free_coherent(0, cam->rot_vf_buf_size[0], + cam->rot_vf_bufs_vaddr[0], + cam->rot_vf_bufs[0]); + cam->rot_vf_bufs_vaddr[0] = NULL; + cam->rot_vf_bufs[0] = 0; + } + if (cam->rot_vf_bufs_vaddr[1]) { + dma_free_coherent(0, cam->rot_vf_buf_size[1], + cam->rot_vf_bufs_vaddr[1], + cam->rot_vf_bufs[1]); + cam->rot_vf_bufs_vaddr[1] = NULL; + cam->rot_vf_bufs[1] = 0; + } + + buffer_num = 0; + buffer_ready = 0; + cam->overlay_active = false; + return 0; +} + +/*! + * Enable csi + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_vf_enable_csi(void *private) +{ + cam_data *cam = (cam_data *) private; + + return ipu_enable_csi(cam->csi); +} + +/*! + * Disable csi + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_vf_disable_csi(void *private) +{ + cam_data *cam = (cam_data *) private; + + return ipu_disable_csi(cam->csi); +} + +/*! + * function to select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return status + */ +int prp_vf_sdc_select_bg(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (cam) { + cam->vf_start_sdc = prpvf_start; + cam->vf_stop_sdc = prpvf_stop; + cam->vf_enable_csi = prp_vf_enable_csi; + cam->vf_disable_csi = prp_vf_disable_csi; + cam->overlay_active = false; + } + + return 0; +} + +/*! + * function to de-select PRP-VF as the working path + * + * @param private cam_data * mxc v4l2 main structure + * + * @return status + */ +int prp_vf_sdc_deselect_bg(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + err = prpvf_stop(private); + + if (cam) { + cam->vf_start_sdc = NULL; + cam->vf_stop_sdc = NULL; + cam->vf_enable_csi = NULL; + cam->vf_disable_csi = NULL; + } + return err; +} + +/*! + * Init viewfinder task. + * + * @return Error code indicating success or failure + */ +__init int prp_vf_sdc_init_bg(void) +{ + return 0; +} + +/*! + * Deinit viewfinder task. + * + * @return Error code indicating success or failure + */ +void __exit prp_vf_sdc_exit_bg(void) +{ +} + +module_init(prp_vf_sdc_init_bg); +module_exit(prp_vf_sdc_exit_bg); + +EXPORT_SYMBOL(prp_vf_sdc_select_bg); +EXPORT_SYMBOL(prp_vf_sdc_deselect_bg); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/ipu_still.c b/drivers/media/video/mxc/capture/ipu_still.c new file mode 100644 index 000000000000..ded24623ce2a --- /dev/null +++ b/drivers/media/video/mxc/capture/ipu_still.c @@ -0,0 +1,268 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_still.c + * + * @brief IPU Use case for still image capture + * + * @ingroup IPU + */ + +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +static int callback_eof_flag; +#ifndef CONFIG_MXC_IPU_V1 +static int buffer_num; +#endif + +#ifdef CONFIG_MXC_IPU_V1 +static int callback_flag; +/* + * Function definitions + */ +/*! + * CSI EOF callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prp_csi_eof_callback(int irq, void *dev_id) +{ + ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, + callback_flag%2 ? 1 : 0); + if (callback_flag == 0) + ipu_enable_channel(CSI_MEM); + + callback_flag++; + return IRQ_HANDLED; +} +#endif + +/*! + * CSI callback function. + * + * @param irq int irq line + * @param dev_id void * device id + * + * @return status IRQ_HANDLED for handled + */ +static irqreturn_t prp_still_callback(int irq, void *dev_id) +{ + cam_data *cam = (cam_data *) dev_id; + + callback_eof_flag++; + if (callback_eof_flag < 5) { +#ifndef CONFIG_MXC_IPU_V1 + buffer_num = (buffer_num == 0) ? 1 : 0; + ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, buffer_num); +#endif + } else { + cam->still_counter++; + wake_up_interruptible(&cam->still_queue); + } + + return IRQ_HANDLED; +} + +/*! + * start csi->mem task + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_still_start(void *private) +{ + cam_data *cam = (cam_data *) private; + u32 pixel_fmt; + int err; + ipu_channel_params_t params; + + if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + pixel_fmt = IPU_PIX_FMT_YUV420P; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) + pixel_fmt = IPU_PIX_FMT_NV12; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) + pixel_fmt = IPU_PIX_FMT_YUV422P; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) + pixel_fmt = IPU_PIX_FMT_UYVY; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + pixel_fmt = IPU_PIX_FMT_YUYV; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) + pixel_fmt = IPU_PIX_FMT_BGR24; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) + pixel_fmt = IPU_PIX_FMT_RGB24; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) + pixel_fmt = IPU_PIX_FMT_RGB565; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) + pixel_fmt = IPU_PIX_FMT_BGR32; + else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) + pixel_fmt = IPU_PIX_FMT_RGB32; + else { + printk(KERN_ERR "format not supported\n"); + return -EINVAL; + } + + ipu_csi_enable_mclk_if(CSI_MCLK_RAW, cam->csi, true, true); + + memset(¶ms, 0, sizeof(params)); + err = ipu_init_channel(CSI_MEM, ¶ms); + if (err != 0) + return err; + + err = ipu_init_channel_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, + pixel_fmt, cam->v2f.fmt.pix.width, + cam->v2f.fmt.pix.height, + cam->v2f.fmt.pix.width, IPU_ROTATE_NONE, + cam->still_buf[0], cam->still_buf[1], + 0, 0); + if (err != 0) + return err; + +#ifdef CONFIG_MXC_IPU_V1 + ipu_clear_irq(IPU_IRQ_SENSOR_OUT_EOF); + err = ipu_request_irq(IPU_IRQ_SENSOR_OUT_EOF, prp_still_callback, + 0, "Mxc Camera", cam); + if (err != 0) { + printk(KERN_ERR "Error registering irq.\n"); + return err; + } + callback_flag = 0; + callback_eof_flag = 0; + ipu_clear_irq(IPU_IRQ_SENSOR_EOF); + err = ipu_request_irq(IPU_IRQ_SENSOR_EOF, prp_csi_eof_callback, + 0, "Mxc Camera", NULL); + if (err != 0) { + printk(KERN_ERR "Error IPU_IRQ_SENSOR_EOF \n"); + return err; + } +#else + callback_eof_flag = 0; + buffer_num = 0; + + ipu_clear_irq(IPU_IRQ_CSI0_OUT_EOF); + err = ipu_request_irq(IPU_IRQ_CSI0_OUT_EOF, prp_still_callback, + 0, "Mxc Camera", cam); + if (err != 0) { + printk(KERN_ERR "Error registering irq.\n"); + return err; + } + + ipu_select_buffer(CSI_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_enable_channel(CSI_MEM); + ipu_enable_csi(cam->csi); +#endif + + return err; +} + +/*! + * stop csi->mem encoder task + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +static int prp_still_stop(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + +#ifdef CONFIG_MXC_IPU_V1 + ipu_free_irq(IPU_IRQ_SENSOR_EOF, NULL); + ipu_free_irq(IPU_IRQ_SENSOR_OUT_EOF, cam); +#else + ipu_free_irq(IPU_IRQ_CSI0_OUT_EOF, cam); +#endif + + ipu_disable_csi(cam->csi); + ipu_disable_channel(CSI_MEM, true); + ipu_uninit_channel(CSI_MEM); + ipu_csi_enable_mclk_if(CSI_MCLK_RAW, cam->csi, false, false); + + return err; +} + +/*! + * function to select CSI_MEM as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +int prp_still_select(void *private) +{ + cam_data *cam = (cam_data *) private; + + if (cam) { + cam->csi_start = prp_still_start; + cam->csi_stop = prp_still_stop; + } + + return 0; +} + +/*! + * function to de-select CSI_MEM as the working path + * + * @param private struct cam_data * mxc capture instance + * + * @return status + */ +int prp_still_deselect(void *private) +{ + cam_data *cam = (cam_data *) private; + int err = 0; + + err = prp_still_stop(cam); + + if (cam) { + cam->csi_start = NULL; + cam->csi_stop = NULL; + } + + return err; +} + +/*! + * Init the Encorder channels + * + * @return Error code indicating success or failure + */ +__init int prp_still_init(void) +{ + return 0; +} + +/*! + * Deinit the Encorder channels + * + */ +void __exit prp_still_exit(void) +{ +} + +module_init(prp_still_init); +module_exit(prp_still_exit); + +EXPORT_SYMBOL(prp_still_select); +EXPORT_SYMBOL(prp_still_deselect); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IPU PRP STILL IMAGE Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/mt9v111.c b/drivers/media/video/mxc/capture/mt9v111.c new file mode 100644 index 000000000000..ccf3ea24024e --- /dev/null +++ b/drivers/media/video/mxc/capture/mt9v111.c @@ -0,0 +1,1076 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mt9v111.c + * + * @brief mt9v111 camera driver functions + * + * @ingroup Camera + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "mt9v111.h" + +#ifdef MT9V111_DEBUG +static u16 testpattern; +#endif + +static mt9v111_conf mt9v111_device; + +/*! + * Holds the current frame rate. + */ +static int reset_frame_rate = MT9V111_FRAME_RATE; + +struct sensor { + const struct mt9v111_platform_data *platform_data; + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + +} mt9v111_data; + +extern void gpio_sensor_active(void); +extern void gpio_sensor_inactive(void); + +static int mt9v111_probe(struct i2c_client *client, + const struct i2c_device_id *id); +static int mt9v111_remove(struct i2c_client *client); + +static const struct i2c_device_id mt9v111_id[] = { + {"mt9v111", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mt9v111_id); + +static struct i2c_driver mt9v111_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mt9v111", + }, + .probe = mt9v111_probe, + .remove = mt9v111_remove, + .id_table = mt9v111_id, +/* To add power management add .suspend and .resume functions */ +}; + +/* + * Function definitions + */ + +#ifdef MT9V111_DEBUG +static inline int mt9v111_read_reg(u8 reg) +{ + int val = i2c_smbus_read_word_data(mt9v111_data.i2c_client, reg); + if (val != -1) + val = cpu_to_be16(val); + return val; +} +#endif + +/*! + * Writes to the register via I2C. + */ +static inline int mt9v111_write_reg(u8 reg, u16 val) +{ + pr_debug("In mt9v111_write_reg (0x%x, 0x%x)\n", reg, val); + pr_debug(" write reg %x val %x.\n", reg, val); + + return i2c_smbus_write_word_data(mt9v111_data.i2c_client, + reg, cpu_to_be16(val)); +} + +/*! + * Initialize mt9v111_sensor_lib + * Libarary for Sensor configuration through I2C + * + * @param coreReg Core Registers + * @param ifpReg IFP Register + * + * @return status + */ +static u8 mt9v111_sensor_lib(mt9v111_coreReg *coreReg, mt9v111_IFPReg *ifpReg) +{ + u8 reg; + u16 data; + u8 error = 0; + + pr_debug("In mt9v111_sensor_lib\n"); + + /* + * setup to IFP registers + */ + reg = MT9V111I_ADDR_SPACE_SEL; + data = ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + /* Operation Mode Control */ + reg = MT9V111I_MODE_CONTROL; + data = ifpReg->modeControl; + mt9v111_write_reg(reg, data); + + /* Output format */ + reg = MT9V111I_FORMAT_CONTROL; + data = ifpReg->formatControl; /* Set bit 12 */ + mt9v111_write_reg(reg, data); + + /* AE limit 4 */ + reg = MT9V111I_SHUTTER_WIDTH_LIMIT_AE; + data = ifpReg->gainLimitAE; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_OUTPUT_FORMAT_CTRL2; + data = ifpReg->outputFormatCtrl2; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_AE_SPEED; + data = ifpReg->AESpeed; + mt9v111_write_reg(reg, data); + + /* output image size */ + reg = MT9V111i_H_PAN; + data = 0x8000 | ifpReg->HPan; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_ZOOM; + data = 0x8000 | ifpReg->HZoom; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_SIZE; + data = 0x8000 | ifpReg->HSize; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_PAN; + data = 0x8000 | ifpReg->VPan; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_ZOOM; + data = 0x8000 | ifpReg->VZoom; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_V_SIZE; + data = 0x8000 | ifpReg->VSize; + mt9v111_write_reg(reg, data); + + reg = MT9V111i_H_PAN; + data = ~0x8000 & ifpReg->HPan; + mt9v111_write_reg(reg, data); +#if 0 + reg = MT9V111I_UPPER_SHUTTER_DELAY_LIM; + data = ifpReg->upperShutterDelayLi; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_SHUTTER_60; + data = ifpReg->shutter_width_60; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_SEARCH_FLICK_60; + data = ifpReg->search_flicker_60; + mt9v111_write_reg(reg, data); +#endif + + /* + * setup to sensor core registers + */ + reg = MT9V111I_ADDR_SPACE_SEL; + data = coreReg->addressSelect; + mt9v111_write_reg(reg, data); + + /* enable changes and put the Sync bit on */ + reg = MT9V111S_OUTPUT_CTRL; + data = MT9V111S_OUTCTRL_SYNC | MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000; + mt9v111_write_reg(reg, data); + + /* min PIXCLK - Default */ + reg = MT9V111S_PIXEL_CLOCK_SPEED; + data = coreReg->pixelClockSpeed; + mt9v111_write_reg(reg, data); + + /* Setup image flipping / Dark rows / row/column skip */ + reg = MT9V111S_READ_MODE; + data = coreReg->readMode; + mt9v111_write_reg(reg, data); + + /* zoom 0 */ + reg = MT9V111S_DIGITAL_ZOOM; + data = coreReg->digitalZoom; + mt9v111_write_reg(reg, data); + + /* min H-blank */ + reg = MT9V111S_HOR_BLANKING; + data = coreReg->horizontalBlanking; + mt9v111_write_reg(reg, data); + + /* min V-blank */ + reg = MT9V111S_VER_BLANKING; + data = coreReg->verticalBlanking; + mt9v111_write_reg(reg, data); + + reg = MT9V111S_SHUTTER_WIDTH; + data = coreReg->shutterWidth; + mt9v111_write_reg(reg, data); + + reg = MT9V111S_SHUTTER_DELAY; + data = ifpReg->upperShutterDelayLi; + mt9v111_write_reg(reg, data); + + /* changes become effective */ + reg = MT9V111S_OUTPUT_CTRL; + data = MT9V111S_OUTCTRL_CHIP_ENABLE | 0x3000; + mt9v111_write_reg(reg, data); + + return error; +} + +/*! + * MT9V111 frame rate calculate + * + * @param frame_rate int * + * @param mclk int + * @return None + */ +static void mt9v111_rate_cal(int *frame_rate, int mclk) +{ + int num_clock_per_row; + int max_rate = 0; + + pr_debug("In mt9v111_rate_cal\n"); + + num_clock_per_row = (MT9V111_MAX_WIDTH + 114 + MT9V111_HORZBLANK_MIN) + * 2; + max_rate = mclk / (num_clock_per_row * + (MT9V111_MAX_HEIGHT + MT9V111_VERTBLANK_DEFAULT)); + + if ((*frame_rate > max_rate) || (*frame_rate == 0)) { + *frame_rate = max_rate; + } + + mt9v111_device.coreReg->verticalBlanking + = mclk / (*frame_rate * num_clock_per_row) - MT9V111_MAX_HEIGHT; + + reset_frame_rate = *frame_rate; +} + +/*! + * MT9V111 sensor configuration + */ +void mt9v111_config(void) +{ + pr_debug("In mt9v111_config\n"); + + mt9v111_device.coreReg->addressSelect = MT9V111I_SEL_SCA; + mt9v111_device.ifpReg->addrSpaceSel = MT9V111I_SEL_IFP; + + mt9v111_device.coreReg->windowHeight = MT9V111_WINHEIGHT; + mt9v111_device.coreReg->windowWidth = MT9V111_WINWIDTH; + mt9v111_device.coreReg->zoomColStart = 0; + mt9v111_device.coreReg->zomRowStart = 0; + mt9v111_device.coreReg->digitalZoom = 0x0; + + mt9v111_device.coreReg->verticalBlanking = MT9V111_VERTBLANK_DEFAULT; + mt9v111_device.coreReg->horizontalBlanking = MT9V111_HORZBLANK_MIN; + mt9v111_device.coreReg->pixelClockSpeed = 0; + mt9v111_device.coreReg->readMode = 0xd0a1; + + mt9v111_device.ifpReg->outputFormatCtrl2 = 0; + mt9v111_device.ifpReg->gainLimitAE = 0x300; + mt9v111_device.ifpReg->AESpeed = 0x80; + + /* here is the default value */ + mt9v111_device.ifpReg->formatControl = 0xc800; + mt9v111_device.ifpReg->modeControl = 0x708e; + mt9v111_device.ifpReg->awbSpeed = 0x4514; + mt9v111_device.coreReg->shutterWidth = 0xf8; + + /* output size */ + mt9v111_device.ifpReg->HPan = 0; + mt9v111_device.ifpReg->HZoom = MT9V111_MAX_WIDTH; + mt9v111_device.ifpReg->HSize = MT9V111_MAX_WIDTH; + mt9v111_device.ifpReg->VPan = 0; + mt9v111_device.ifpReg->VZoom = MT9V111_MAX_HEIGHT; + mt9v111_device.ifpReg->VSize = MT9V111_MAX_HEIGHT; +} + +/*! + * mt9v111 sensor set saturtionn + * + * @param saturation int + + * @return Error code of 0. + */ +static int mt9v111_set_saturation(int saturation) +{ + u8 reg; + u16 data; + pr_debug("In mt9v111_set_saturation(%d)\n", + saturation); + + switch (saturation) { + case 150: + mt9v111_device.ifpReg->awbSpeed = 0x6D14; + break; + case 100: + mt9v111_device.ifpReg->awbSpeed = 0x4514; + break; + case 75: + mt9v111_device.ifpReg->awbSpeed = 0x4D14; + break; + case 50: + mt9v111_device.ifpReg->awbSpeed = 0x5514; + break; + case 37: + mt9v111_device.ifpReg->awbSpeed = 0x5D14; + break; + case 25: + mt9v111_device.ifpReg->awbSpeed = 0x6514; + break; + default: + mt9v111_device.ifpReg->awbSpeed = 0x4514; + break; + } + + reg = MT9V111I_ADDR_SPACE_SEL; + data = mt9v111_device.ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + /* Operation Mode Control */ + reg = MT9V111I_AWB_SPEED; + data = mt9v111_device.ifpReg->awbSpeed; + mt9v111_write_reg(reg, data); + + return 0; +} + +/*! + * mt9v111 sensor set Auto Exposure measurement window mode configuration + * + * @param ae_mode int + * @return Error code of 0 (no Error) + */ +static int mt9v111_set_ae_mode(int ae_mode) +{ + u8 reg; + u16 data; + + pr_debug("In mt9v111_set_ae_mode(%d)\n", + ae_mode); + + /* Currently this driver only supports auto and manual exposure + * modes. */ + if ((ae_mode > 1) || (ae_mode << 0)) + return -EPERM; + + /* + * The auto exposure is set in bit 14. + * Other values are set for: + * -on the fly defect correction is on (bit 13). + * -aperature correction knee enabled (bit 12). + * -ITU_R BT656 synchronization codes are embedded in the image (bit 7) + * -AE measurement window is weighted sum of large and center windows + * (bits 2-3). + * -auto white balance is on (bit 1). + * -normal color processing (bit 4 = 0). + */ + /* V4L2_EXPOSURE_AUTO = 0; needs register setting of 0x708E */ + /* V4L2_EXPOSURE_MANUAL = 1 needs register setting of 0x308E */ + mt9v111_device.ifpReg->modeControl &= 0x3fff; + mt9v111_device.ifpReg->modeControl |= (ae_mode & 0x03) << 14; + mt9v111_data.ae_mode = ae_mode; + + reg = MT9V111I_ADDR_SPACE_SEL; + data = mt9v111_device.ifpReg->addrSpaceSel; + mt9v111_write_reg(reg, data); + + reg = MT9V111I_MODE_CONTROL; + data = mt9v111_device.ifpReg->modeControl; + mt9v111_write_reg(reg, data); + + return 0; +} + +/*! + * mt9v111 sensor get AE measurement window mode configuration + * + * @param ae_mode int * + * @return None + */ +static void mt9v111_get_ae_mode(int *ae_mode) +{ + pr_debug("In mt9v111_get_ae_mode(%d)\n", *ae_mode); + + if (ae_mode != NULL) { + *ae_mode = (mt9v111_device.ifpReg->modeControl & 0xc) >> 2; + } +} + +#ifdef MT9V111_DEBUG +/*! + * Set sensor to test mode, which will generate test pattern. + * + * @return none + */ +static void mt9v111_test_pattern(bool flag) +{ + u16 data; + + /* switch to sensor registers */ + mt9v111_write_reg(MT9V111I_ADDR_SPACE_SEL, MT9V111I_SEL_SCA); + + if (flag == true) { + testpattern = MT9V111S_OUTCTRL_TEST_MODE; + + data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) & 0xBF; + mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data); + + mt9v111_write_reg(MT9V111S_TEST_DATA, 0); + + /* changes take effect */ + data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000; + mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data); + } else { + testpattern = 0; + + data = mt9v111_read_reg(MT9V111S_ROW_NOISE_CTRL) | 0x40; + mt9v111_write_reg(MT9V111S_ROW_NOISE_CTRL, data); + + /* changes take effect */ + data = MT9V111S_OUTCTRL_CHIP_ENABLE | testpattern | 0x3000; + mt9v111_write_reg(MT9V111S_OUTPUT_CTRL, data); + } +} +#endif + + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +/*! + * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num + * s: pointer to standard V4L2 device structure + * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure + * + * Gets slave interface parameters. + * Calculates the required xclk value to support the requested + * clock parameters in p. This value is returned in the p + * parameter. + * + * vidioc_int_g_ifparm returns platform-specific information about the + * interface settings used by the sensor. + * + * Given the image capture format in pix, the nominal frame period in + * timeperframe, calculate the required xclk frequency. + * + * Called on open. + */ +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + pr_debug("In mt9v111:ioctl_g_ifparm\n"); + + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = MT9V111_MCLK; + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = MT9V111_CLK_MIN; + p->u.bt656.clock_max = MT9V111_CLK_MAX; + + return 0; +} + +/*! + * Sets the camera power. + * + * s pointer to the camera device + * on if 1, power is to be turned on. 0 means power is to be turned off + * + * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num + * @s: pointer to standard V4L2 device structure + * @on: power state to which device is to be set + * + * Sets devices power state to requrested state, if possible. + * This is called on suspend and resume. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + pr_debug("In mt9v111:ioctl_s_power\n"); + + sensor->on = on; + + if (on) + gpio_sensor_active(); + else + gpio_sensor_inactive(); + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + int ret = 0; + struct v4l2_captureparm *cparm = &a->parm.capture; + /* s->priv points to mt9v111_data */ + + pr_debug("In mt9v111:ioctl_g_parm\n"); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = mt9v111_data.streamcap.capability; + cparm->timeperframe = + mt9v111_data.streamcap.timeperframe; + cparm->capturemode = mt9v111_data.streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_err(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \ + "but %d\n", a->type); + ret = -EINVAL; + break; + + default: + pr_err(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + int ret = 0; + struct v4l2_captureparm *cparm = &a->parm.capture; + /* s->priv points to mt9v111_data */ + + pr_debug("In mt9v111:ioctl_s_parm\n"); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + + /* Check that the new frame rate is allowed. + * Changing the frame rate is not allowed on this + *camera. */ + if (cparm->timeperframe.denominator != + mt9v111_data.streamcap.timeperframe.denominator) { + pr_err("ERROR: mt9v111: ioctl_s_parm: " \ + "This camera does not allow frame rate " + "changes.\n"); + ret = -EINVAL; + } else { + mt9v111_data.streamcap.timeperframe = + cparm->timeperframe; + /* Call any camera functions to match settings. */ + } + + /* Check that new capture mode is supported. */ + if ((cparm->capturemode != 0) && + !(cparm->capturemode & V4L2_MODE_HIGHQUALITY)) { + pr_err("ERROR: mt9v111: ioctl_s_parm: " \ + "unsupported capture mode\n"); + ret = -EINVAL; + } else { + mt9v111_data.streamcap.capturemode = + cparm->capturemode; + /* Call any camera functions to match settings. */ + /* Right now this camera only supports 1 mode. */ + } + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_err(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \ + "but %d\n", a->type); + ret = -EINVAL; + break; + + default: + pr_err(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return 0; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + /* s->priv points to mt9v111_data */ + + pr_debug("In mt9v111:ioctl_g_fmt_cap.\n"); + pr_debug(" Returning size of %dx%d\n", + sensor->pix.width, sensor->pix.height); + + f->fmt.pix = sensor->pix; + + return 0; +} + +/*! + * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl + * @s: pointer to standard V4L2 device structure + * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure + * + * If the requested control is supported, returns the control information + * from the video_control[] array. Otherwise, returns -EINVAL if the + * control is not supported. + */ +static int ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qc) +{ + pr_debug("In mt9v111:ioctl_queryctrl\n"); + + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + pr_debug("In mt9v111:ioctl_g_ctrl\n"); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + pr_debug(" V4L2_CID_BRIGHTNESS\n"); + vc->value = mt9v111_data.brightness; + break; + case V4L2_CID_CONTRAST: + pr_debug(" V4L2_CID_CONTRAST\n"); + vc->value = mt9v111_data.contrast; + break; + case V4L2_CID_SATURATION: + pr_debug(" V4L2_CID_SATURATION\n"); + vc->value = mt9v111_data.saturation; + break; + case V4L2_CID_HUE: + pr_debug(" V4L2_CID_HUE\n"); + vc->value = mt9v111_data.hue; + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + vc->value = 0; + break; + case V4L2_CID_DO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_DO_WHITE_BALANCE\n"); + vc->value = 0; + break; + case V4L2_CID_RED_BALANCE: + pr_debug(" V4L2_CID_RED_BALANCE\n"); + vc->value = mt9v111_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + pr_debug(" V4L2_CID_BLUE_BALANCE\n"); + vc->value = mt9v111_data.blue; + break; + case V4L2_CID_GAMMA: + pr_debug(" V4L2_CID_GAMMA\n"); + vc->value = 0; + break; + case V4L2_CID_EXPOSURE: + pr_debug(" V4L2_CID_EXPOSURE\n"); + vc->value = mt9v111_data.ae_mode; + break; + case V4L2_CID_AUTOGAIN: + pr_debug(" V4L2_CID_AUTOGAIN\n"); + vc->value = 0; + break; + case V4L2_CID_GAIN: + pr_debug(" V4L2_CID_GAIN\n"); + vc->value = 0; + break; + case V4L2_CID_HFLIP: + pr_debug(" V4L2_CID_HFLIP\n"); + vc->value = 0; + break; + case V4L2_CID_VFLIP: + pr_debug(" V4L2_CID_VFLIP\n"); + vc->value = 0; + break; + default: + pr_debug(" Default case\n"); + return -EPERM; + break; + } + + return 0; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In mt9v111:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + pr_debug(" V4L2_CID_BRIGHTNESS\n"); + break; + case V4L2_CID_CONTRAST: + pr_debug(" V4L2_CID_CONTRAST\n"); + break; + case V4L2_CID_SATURATION: + pr_debug(" V4L2_CID_SATURATION\n"); + retval = mt9v111_set_saturation(vc->value); + break; + case V4L2_CID_HUE: + pr_debug(" V4L2_CID_HUE\n"); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + pr_debug(" V4L2_CID_RED_BALANCE\n"); + break; + case V4L2_CID_BLUE_BALANCE: + pr_debug(" V4L2_CID_BLUE_BALANCE\n"); + break; + case V4L2_CID_GAMMA: + pr_debug(" V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + pr_debug(" V4L2_CID_EXPOSURE\n"); + retval = mt9v111_set_ae_mode(vc->value); + break; + case V4L2_CID_AUTOGAIN: + pr_debug(" V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + pr_debug(" V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + pr_debug(" V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + pr_debug(" V4L2_CID_VFLIP\n"); + break; + default: + pr_debug(" Default case\n"); + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + pr_debug("In mt9v111:ioctl_init\n"); + + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + uint32_t clock_rate = MT9V111_MCLK; + + pr_debug("In mt9v111:ioctl_dev_init\n"); + + gpio_sensor_active(); + + set_mclk_rate(&clock_rate); + mt9v111_rate_cal(&reset_frame_rate, clock_rate); + mt9v111_sensor_lib(mt9v111_device.coreReg, mt9v111_device.ifpReg); + + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc mt9v111_ioctl_desc[] = { + + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, + + /*! + * Delinitialise the dev. at slave detach. + * The complement of ioctl_dev_init. + */ +/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *) ioctl_dev_exit}, */ + + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *) ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *) ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init}, + + /*! + * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. + */ +/* {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, */ + + /*! + * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. + * This ioctl is used to negotiate the image capture size and + * pixel format without actually making it take effect. + */ +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *) ioctl_try_fmt_cap}, */ + + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*) ioctl_g_fmt_cap}, + + /*! + * If the requested format is supported, configures the HW to use that + * format, returns error code if format not supported or HW can't be + * correctly configured. + */ +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*) ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*) ioctl_s_parm}, +/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *) ioctl_queryctrl}, */ + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*) ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*) ioctl_s_ctrl}, +}; + +static struct v4l2_int_slave mt9v111_slave = { + .ioctls = mt9v111_ioctl_desc, + .num_ioctls = ARRAY_SIZE(mt9v111_ioctl_desc), +}; + +static struct v4l2_int_device mt9v111_int_device = { + .module = THIS_MODULE, + .name = "mt9v111", + .type = v4l2_int_type_slave, + .u = { + .slave = &mt9v111_slave, + }, +}; + +/*! + * mt9v111 I2C probe function + * Function set in i2c_driver struct. + * Called by insmod mt9v111_camera.ko. + * + * @return Error code indicating success or failure + */ +static int mt9v111_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + + pr_debug("In mt9v111_probe device id is %s\n", id->name); + + /* Set initial values for the sensor struct. */ + memset(&mt9v111_data, 0, sizeof(mt9v111_data)); + mt9v111_data.i2c_client = client; + pr_debug(" client name is %s\n", client->name); + mt9v111_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; + mt9v111_data.pix.width = MT9V111_MAX_WIDTH; + mt9v111_data.pix.height = MT9V111_MAX_HEIGHT; + mt9v111_data.streamcap.capability = 0; /* No higher resolution or frame + * frame rate changes supported. + */ + mt9v111_data.streamcap.timeperframe.denominator = MT9V111_FRAME_RATE; + mt9v111_data.streamcap.timeperframe.numerator = 1; + + mt9v111_int_device.priv = &mt9v111_data; + + pr_debug(" type is %d (expect %d)\n", + mt9v111_int_device.type, v4l2_int_type_slave); + pr_debug(" num ioctls is %d\n", + mt9v111_int_device.u.slave->num_ioctls); + + /* This function attaches this structure to the /dev/video0 device. + * The pointer in priv points to the mt9v111_data structure here.*/ + retval = v4l2_int_device_register(&mt9v111_int_device); + + return retval; +} + +/*! + * Function set in i2c_driver struct. + * Called on rmmod mt9v111_camera.ko + */ +static int mt9v111_remove(struct i2c_client *client) +{ + pr_debug("In mt9v111_remove\n"); + + v4l2_int_device_unregister(&mt9v111_int_device); + return 0; +} + +/*! + * MT9V111 init function. + * Called by insmod mt9v111_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int mt9v111_init(void) +{ + u8 err; + + pr_debug("In mt9v111_init\n"); + + /* Allocate memory for state structures. */ + mt9v111_device.coreReg = (mt9v111_coreReg *) + kmalloc(sizeof(mt9v111_coreReg), GFP_KERNEL); + if (!mt9v111_device.coreReg) + return -1; + memset(mt9v111_device.coreReg, 0, sizeof(mt9v111_coreReg)); + + mt9v111_device.ifpReg = (mt9v111_IFPReg *) + kmalloc(sizeof(mt9v111_IFPReg), GFP_KERNEL); + if (!mt9v111_device.ifpReg) { + kfree(mt9v111_device.coreReg); + mt9v111_device.coreReg = NULL; + return -1; + } + memset(mt9v111_device.ifpReg, 0, sizeof(mt9v111_IFPReg)); + + /* Set contents of the just created structures. */ + mt9v111_config(); + + /* Tells the i2c driver what functions to call for this driver. */ + err = i2c_add_driver(&mt9v111_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * MT9V111 cleanup function. + * Called on rmmod mt9v111_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit mt9v111_clean(void) +{ + pr_debug("In mt9v111_clean()\n"); + + i2c_del_driver(&mt9v111_i2c_driver); + gpio_sensor_inactive(); + + if (mt9v111_device.coreReg) { + kfree(mt9v111_device.coreReg); + mt9v111_device.coreReg = NULL; + } + + if (mt9v111_device.ifpReg) { + kfree(mt9v111_device.ifpReg); + mt9v111_device.ifpReg = NULL; + } +} + +module_init(mt9v111_init); +module_exit(mt9v111_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Mt9v111 Camera Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/mt9v111.h b/drivers/media/video/mxc/capture/mt9v111.h new file mode 100644 index 000000000000..6b9d37b5decd --- /dev/null +++ b/drivers/media/video/mxc/capture/mt9v111.h @@ -0,0 +1,431 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Camera Sensor Drivers + */ + +/*! + * @file mt9v111.h + * + * @brief MT9V111 Camera Header file + * + * This header file contains defines and structures for the iMagic mi8012 + * aka the Micron mt9v111 camera. + * + * @ingroup Camera + */ + +#ifndef MT9V111_H_ +#define MT9V111_H_ + +/*! + * Basic camera values + */ +#define MT9V111_FRAME_RATE 30 +#define MT9V111_MCLK 27000000 /* Desired clock rate */ +#define MT9V111_CLK_MIN 12000000 /* This clock rate yields 15 fps */ +#define MT9V111_CLK_MAX 27000000 +#define MT9V111_MAX_WIDTH 640 /* Max width for this camera */ +#define MT9V111_MAX_HEIGHT 480 /* Max height for this camera */ + +/*! + * mt9v111 IFP REGISTER BANK MAP + */ +#define MT9V111I_ADDR_SPACE_SEL 0x1 +#define MT9V111I_BASE_MAXTRIX_SIGN 0x2 +#define MT9V111I_BASE_MAXTRIX_SCALE15 0x3 +#define MT9V111I_BASE_MAXTRIX_SCALE69 0x4 +#define MT9V111I_APERTURE_GAIN 0x5 +#define MT9V111I_MODE_CONTROL 0x6 +#define MT9V111I_SOFT_RESET 0x7 +#define MT9V111I_FORMAT_CONTROL 0x8 +#define MT9V111I_BASE_MATRIX_CFK1 0x9 +#define MT9V111I_BASE_MATRIX_CFK2 0xa +#define MT9V111I_BASE_MATRIX_CFK3 0xb +#define MT9V111I_BASE_MATRIX_CFK4 0xc +#define MT9V111I_BASE_MATRIX_CFK5 0xd +#define MT9V111I_BASE_MATRIX_CFK6 0xe +#define MT9V111I_BASE_MATRIX_CFK7 0xf +#define MT9V111I_BASE_MATRIX_CFK8 0x10 +#define MT9V111I_BASE_MATRIX_CFK9 0x11 +#define MT9V111I_AWB_POSITION 0x12 +#define MT9V111I_AWB_RED_GAIN 0x13 +#define MT9V111I_AWB_BLUE_GAIN 0x14 +#define MT9V111I_DELTA_MATRIX_CF_SIGN 0x15 +#define MT9V111I_DELTA_MATRIX_CF_D1 0x16 +#define MT9V111I_DELTA_MATRIX_CF_D2 0x17 +#define MT9V111I_DELTA_MATRIX_CF_D3 0x18 +#define MT9V111I_DELTA_MATRIX_CF_D4 0x19 +#define MT9V111I_DELTA_MATRIX_CF_D5 0x1a +#define MT9V111I_DELTA_MATRIX_CF_D6 0x1b +#define MT9V111I_DELTA_MATRIX_CF_D7 0x1c +#define MT9V111I_DELTA_MATRIX_CF_D8 0x1d +#define MT9V111I_DELTA_MATRIX_CF_D9 0x1e +#define MT9V111I_LUMINANCE_LIMIT_WB 0x20 +#define MT9V111I_RBG_MANUUAL_WB 0x21 +#define MT9V111I_AWB_RED_LIMIT 0x22 +#define MT9V111I_AWB_BLUE_LIMIT 0x23 +#define MT9V111I_MATRIX_ADJUST_LIMIT 0x24 +#define MT9V111I_AWB_SPEED 0x25 +#define MT9V111I_H_BOUND_AE 0x26 +#define MT9V111I_V_BOUND_AE 0x27 +#define MT9V111I_H_BOUND_AE_CEN_WIN 0x2b +#define MT9V111I_V_BOUND_AE_CEN_WIN 0x2c +#define MT9V111I_BOUND_AWB_WIN 0x2d +#define MT9V111I_AE_PRECISION_TARGET 0x2e +#define MT9V111I_AE_SPEED 0x2f +#define MT9V111I_RED_AWB_MEASURE 0x30 +#define MT9V111I_LUMA_AWB_MEASURE 0x31 +#define MT9V111I_BLUE_AWB_MEASURE 0x32 +#define MT9V111I_LIMIT_SHARP_SATU_CTRL 0x33 +#define MT9V111I_LUMA_OFFSET 0x34 +#define MT9V111I_CLIP_LIMIT_OUTPUT_LUMI 0x35 +#define MT9V111I_GAIN_LIMIT_AE 0x36 +#define MT9V111I_SHUTTER_WIDTH_LIMIT_AE 0x37 +#define MT9V111I_UPPER_SHUTTER_DELAY_LIM 0x39 +#define MT9V111I_OUTPUT_FORMAT_CTRL2 0x3a +#define MT9V111I_IPF_BLACK_LEVEL_SUB 0x3b +#define MT9V111I_IPF_BLACK_LEVEL_ADD 0x3c +#define MT9V111I_ADC_LIMIT_AE_ADJ 0x3d +#define MT9V111I_GAIN_THRE_CCAM_ADJ 0x3e +#define MT9V111I_LINEAR_AE 0x3f +#define MT9V111I_THRESHOLD_EDGE_DEFECT 0x47 +#define MT9V111I_LUMA_SUM_MEASURE 0x4c +#define MT9V111I_TIME_ADV_SUM_LUMA 0x4d +#define MT9V111I_MOTION 0x52 +#define MT9V111I_GAMMA_KNEE_Y12 0x53 +#define MT9V111I_GAMMA_KNEE_Y34 0x54 +#define MT9V111I_GAMMA_KNEE_Y56 0x55 +#define MT9V111I_GAMMA_KNEE_Y78 0x56 +#define MT9V111I_GAMMA_KNEE_Y90 0x57 +#define MT9V111I_GAMMA_VALUE_Y0 0x58 +#define MT9V111I_SHUTTER_60 0x59 +#define MT9V111I_SEARCH_FLICK_60 0x5c +#define MT9V111I_RATIO_IMAGE_GAIN_BASE 0x5e +#define MT9V111I_RATIO_IMAGE_GAIN_DELTA 0x5f +#define MT9V111I_SIGN_VALUE_REG5F 0x60 +#define MT9V111I_AE_GAIN 0x62 +#define MT9V111I_MAX_GAIN_AE 0x67 +#define MT9V111I_LENS_CORRECT_CTRL 0x80 +#define MT9V111I_SHADING_PARAMETER1 0x81 +#define MT9V111I_SHADING_PARAMETER2 0x82 +#define MT9V111I_SHADING_PARAMETER3 0x83 +#define MT9V111I_SHADING_PARAMETER4 0x84 +#define MT9V111I_SHADING_PARAMETER5 0x85 +#define MT9V111I_SHADING_PARAMETER6 0x86 +#define MT9V111I_SHADING_PARAMETER7 0x87 +#define MT9V111I_SHADING_PARAMETER8 0x88 +#define MT9V111I_SHADING_PARAMETER9 0x89 +#define MT9V111I_SHADING_PARAMETER10 0x8A +#define MT9V111I_SHADING_PARAMETER11 0x8B +#define MT9V111I_SHADING_PARAMETER12 0x8C +#define MT9V111I_SHADING_PARAMETER13 0x8D +#define MT9V111I_SHADING_PARAMETER14 0x8E +#define MT9V111I_SHADING_PARAMETER15 0x8F +#define MT9V111I_SHADING_PARAMETER16 0x90 +#define MT9V111I_SHADING_PARAMETER17 0x91 +#define MT9V111I_SHADING_PARAMETER18 0x92 +#define MT9V111I_SHADING_PARAMETER19 0x93 +#define MT9V111I_SHADING_PARAMETER20 0x94 +#define MT9V111I_SHADING_PARAMETER21 0x95 +#define MT9V111i_FLASH_CTRL 0x98 +#define MT9V111i_LINE_COUNTER 0x99 +#define MT9V111i_FRAME_COUNTER 0x9A +#define MT9V111i_H_PAN 0xA5 +#define MT9V111i_H_ZOOM 0xA6 +#define MT9V111i_H_SIZE 0xA7 +#define MT9V111i_V_PAN 0xA8 +#define MT9V111i_V_ZOOM 0xA9 +#define MT9V111i_V_SIZE 0xAA + +#define MT9V111I_SEL_IFP 0x1 +#define MT9V111I_SEL_SCA 0x4 +#define MT9V111I_FC_RGB_OR_YUV 0x1000 + +/*! + * Mt9v111 SENSOR CORE REGISTER BANK MAP + */ +#define MT9V111S_ADDR_SPACE_SEL 0x1 +#define MT9V111S_COLUMN_START 0x2 +#define MT9V111S_WIN_HEIGHT 0x3 +#define MT9V111S_WIN_WIDTH 0x4 +#define MT9V111S_HOR_BLANKING 0x5 +#define MT9V111S_VER_BLANKING 0x6 +#define MT9V111S_OUTPUT_CTRL 0x7 +#define MT9V111S_ROW_START 0x8 +#define MT9V111S_SHUTTER_WIDTH 0x9 +#define MT9V111S_PIXEL_CLOCK_SPEED 0xa +#define MT9V111S_RESTART 0xb +#define MT9V111S_SHUTTER_DELAY 0xc +#define MT9V111S_RESET 0xd +#define MT9V111S_COLUMN_START_IN_ZOOM 0x12 +#define MT9V111S_ROW_START_IN_ZOOM 0x13 +#define MT9V111S_DIGITAL_ZOOM 0x1e +#define MT9V111S_READ_MODE 0x20 +#define MT9V111S_DAC_CTRL 0x27 +#define MT9V111S_GREEN1_GAIN 0x2b +#define MT9V111S_BLUE_GAIN 0x2c +#define MT9V111S_READ_GAIN 0x2d +#define MT9V111S_GREEN2_GAIN 0x2e +#define MT9V111S_ROW_NOISE_CTRL 0x30 +#define MT9V111S_DARK_TARGET_W 0x31 +#define MT9V111S_TEST_DATA 0x32 +#define MT9V111S_GLOBAL_GAIN 0x35 +#define MT9V111S_SENSOR_CORE_VERSION 0x36 +#define MT9V111S_DARK_TARGET_WO 0x37 +#define MT9V111S_VERF_DAC 0x41 +#define MT9V111S_VCM_VCL 0x42 +#define MT9V111S_DISABLE_BYPASS 0x58 +#define MT9V111S_CALIB_MEAN_TEST 0x59 +#define MT9V111S_DARK_G1_AVE 0x5B +#define MT9V111S_DARK_G2_AVE 0x5C +#define MT9V111S_DARK_R_AVE 0x5D +#define MT9V111S_DARK_B_AVE 0x5E +#define MT9V111S_CAL_THRESHOLD 0x5f +#define MT9V111S_CAL_G1 0x60 +#define MT9V111S_CAL_G2 0x61 +#define MT9V111S_CAL_CTRL 0x62 +#define MT9V111S_CAL_R 0x63 +#define MT9V111S_CAL_B 0x64 +#define MT9V111S_CHIP_ENABLE 0xF1 +#define MT9V111S_CHIP_VERSION 0xFF + +/* OUTPUT_CTRL */ +#define MT9V111S_OUTCTRL_SYNC 0x1 +#define MT9V111S_OUTCTRL_CHIP_ENABLE 0x2 +#define MT9V111S_OUTCTRL_TEST_MODE 0x40 + +/* READ_MODE */ +#define MT9V111S_RM_NOBADFRAME 0x1 +#define MT9V111S_RM_NODESTRUCT 0x2 +#define MT9V111S_RM_COLUMNSKIP 0x4 +#define MT9V111S_RM_ROWSKIP 0x8 +#define MT9V111S_RM_BOOSTEDRESET 0x1000 +#define MT9V111S_RM_COLUMN_LATE 0x10 +#define MT9V111S_RM_ROW_LATE 0x80 +#define MT9V111S_RM_RIGTH_TO_LEFT 0x4000 +#define MT9V111S_RM_BOTTOM_TO_TOP 0x8000 + +/*! I2C Slave Address */ +#define MT9V111_I2C_ADDRESS 0x48 + +/*! + * The image resolution enum for the mt9v111 sensor + */ +typedef enum { + MT9V111_OutputResolution_VGA = 0, /*!< VGA size */ + MT9V111_OutputResolution_QVGA, /*!< QVGA size */ + MT9V111_OutputResolution_CIF, /*!< CIF size */ + MT9V111_OutputResolution_QCIF, /*!< QCIF size */ + MT9V111_OutputResolution_QQVGA, /*!< QQVGA size */ + MT9V111_OutputResolution_SXGA /*!< SXGA size */ +} MT9V111_OutputResolution; + +enum { + MT9V111_WINWIDTH = 0x287, + MT9V111_WINWIDTH_DEFAULT = 0x287, + MT9V111_WINWIDTH_MIN = 0x9, + + MT9V111_WINHEIGHT = 0x1E7, + MT9V111_WINHEIGHT_DEFAULT = 0x1E7, + + MT9V111_HORZBLANK_DEFAULT = 0x26, + MT9V111_HORZBLANK_MIN = 0x9, + MT9V111_HORZBLANK_MAX = 0x3FF, + + MT9V111_VERTBLANK_DEFAULT = 0x4, + MT9V111_VERTBLANK_MIN = 0x3, + MT9V111_VERTBLANK_MAX = 0xFFF, +}; + +/*! + * Mt9v111 Core Register structure. + */ +typedef struct { + u32 addressSelect; /*!< select address bank for Core Register 0x4 */ + u32 columnStart; /*!< Starting Column */ + u32 windowHeight; /*!< Window Height */ + u32 windowWidth; /*!< Window Width */ + u32 horizontalBlanking; /*!< Horizontal Blank time, in pixels */ + u32 verticalBlanking; /*!< Vertical Blank time, in pixels */ + u32 outputControl; /*!< Register to control sensor output */ + u32 rowStart; /*!< Starting Row */ + u32 shutterWidth; + u32 pixelClockSpeed; /*!< pixel date rate */ + u32 restart; /*!< Abandon the readout of current frame */ + u32 shutterDelay; + u32 reset; /*!< reset the sensor to the default mode */ + u32 zoomColStart; /*!< Column start in the Zoom mode */ + u32 zomRowStart; /*!< Row start in the Zoom mode */ + u32 digitalZoom; /*!< 1 means zoom by 2 */ + u32 readMode; /*!< Readmode: aspects of the readout of the sensor */ + u32 dACStandbyControl; + u32 green1Gain; /*!< Gain Settings */ + u32 blueGain; + u32 redGain; + u32 green2Gain; + u32 rowNoiseControl; + u32 darkTargetwNC; + u32 testData; /*!< test mode */ + u32 globalGain; + u32 chipVersion; + u32 darkTargetwoNC; + u32 vREFDACs; + u32 vCMandVCL; + u32 disableBypass; + u32 calibMeanTest; + u32 darkG1average; + u32 darkG2average; + u32 darkRaverage; + u32 darkBaverage; + u32 calibThreshold; + u32 calibGreen1; + u32 calibGreen2; + u32 calibControl; + u32 calibRed; + u32 calibBlue; + u32 chipEnable; /*!< Image core Registers written by image flow processor */ +} mt9v111_coreReg; + +/*! + * Mt9v111 IFP Register structure. + */ +typedef struct { + u32 addrSpaceSel; /*!< select address bank for Core Register 0x1 */ + u32 baseMaxtrixSign; /*!< sign of coefficient for base color correction matrix */ + u32 baseMaxtrixScale15; /*!< scaling of color correction coefficient K1-5 */ + u32 baseMaxtrixScale69; /*!< scaling of color correction coefficient K6-9 */ + u32 apertureGain; /*!< sharpening */ + u32 modeControl; /*!< bit 7 CCIR656 sync codes are embedded in the image */ + u32 softReset; /*!< Image processing mode: 1 reset mode, 0 operational mode */ + u32 formatControl; /*!< bit12 1 for RGB565, 0 for YcrCb */ + u32 baseMatrixCfk1; /*!< K1 Color correction coefficient */ + u32 baseMatrixCfk2; /*!< K2 Color correction coefficient */ + u32 baseMatrixCfk3; /*!< K3 Color correction coefficient */ + u32 baseMatrixCfk4; /*!< K4 Color correction coefficient */ + u32 baseMatrixCfk5; /*!< K5 Color correction coefficient */ + u32 baseMatrixCfk6; /*!< K6 Color correction coefficient */ + u32 baseMatrixCfk7; /*!< K7 Color correction coefficient */ + u32 baseMatrixCfk8; /*!< K8 Color correction coefficient */ + u32 baseMatrixCfk9; /*!< K9 Color correction coefficient */ + u32 awbPosition; /*!< Current position of AWB color correction matrix */ + u32 awbRedGain; /*!< Current value of AWB red channel gain */ + u32 awbBlueGain; /*!< Current value of AWB blue channel gain */ + u32 deltaMatrixCFSign; /*!< Sign of coefficients of delta color correction matrix register */ + u32 deltaMatrixCFD1; /*!< D1 Delta coefficient */ + u32 deltaMatrixCFD2; /*!< D2 Delta coefficient */ + u32 deltaMatrixCFD3; /*!< D3 Delta coefficient */ + u32 deltaMatrixCFD4; /*!< D4 Delta coefficient */ + u32 deltaMatrixCFD5; /*!< D5 Delta coefficient */ + u32 deltaMatrixCFD6; /*!< D6 Delta coefficient */ + u32 deltaMatrixCFD7; /*!< D7 Delta coefficient */ + u32 deltaMatrixCFD8; /*!< D8 Delta coefficient */ + u32 deltaMatrixCFD9; /*!< D9 Delta coefficient */ + u32 lumLimitWB; /*!< Luminance range of pixels considered in WB statistics */ + u32 RBGManualWB; /*!< Red and Blue color channel gains for manual white balance */ + u32 awbRedLimit; /*!< Limits on Red channel gain adjustment through AWB */ + u32 awbBlueLimit; /*!< Limits on Blue channel gain adjustment through AWB */ + u32 matrixAdjLimit; /*!< Limits on color correction matrix adjustment through AWB */ + u32 awbSpeed; /*!< AWB speed and color saturation control */ + u32 HBoundAE; /*!< Horizontal boundaries of AWB measurement window */ + u32 VBoundAE; /*!< Vertical boundaries of AWB measurement window */ + u32 HBoundAECenWin; /*!< Horizontal boundaries of AE measurement window for backlight compensation */ + u32 VBoundAECenWin; /*!< Vertical boundaries of AE measurement window for backlight compensation */ + u32 boundAwbWin; /*!< Boundaries of AWB measurement window */ + u32 AEPrecisionTarget; /*!< Auto exposure target and precision control */ + u32 AESpeed; /*!< AE speed and sensitivity control register */ + u32 redAWBMeasure; /*!< Measure of the red channel value used by AWB */ + u32 lumaAWBMeasure; /*!< Measure of the luminance channel value used by AWB */ + u32 blueAWBMeasure; /*!< Measure of the blue channel value used by AWB */ + u32 limitSharpSatuCtrl; /*!< Automatic control of sharpness and color saturation */ + u32 lumaOffset; /*!< Luminance offset control (brightness control) */ + u32 clipLimitOutputLumi; /*!< Clipping limits for output luminance */ + u32 gainLimitAE; /*!< Imager gain limits for AE adjustment */ + u32 shutterWidthLimitAE; /*!< Shutter width (exposure time) limits for AE adjustment */ + u32 upperShutterDelayLi; /*!< Upper Shutter Delay Limit */ + u32 outputFormatCtrl2; /*!< Output Format Control 2 + 00 = 16-bit RGB565. + 01 = 15-bit RGB555. + 10 = 12-bit RGB444x. + 11 = 12-bit RGBx444. */ + u32 ipfBlackLevelSub; /*!< IFP black level subtraction */ + u32 ipfBlackLevelAdd; /*!< IFP black level addition */ + u32 adcLimitAEAdj; /*!< ADC limits for AE adjustment */ + u32 agimnThreCamAdj; /*!< Gain threshold for CCM adjustment */ + u32 linearAE; + u32 thresholdEdgeDefect; /*!< Edge threshold for interpolation and defect correction */ + u32 lumaSumMeasure; /*!< Luma measured by AE engine */ + u32 timeAdvSumLuma; /*!< Time-averaged luminance value tracked by auto exposure */ + u32 motion; /*!< 1 when motion is detected */ + u32 gammaKneeY12; /*!< Gamma knee points Y1 and Y2 */ + u32 gammaKneeY34; /*!< Gamma knee points Y3 and Y4 */ + u32 gammaKneeY56; /*!< Gamma knee points Y5 and Y6 */ + u32 gammaKneeY78; /*!< Gamma knee points Y7 and Y8 */ + u32 gammaKneeY90; /*!< Gamma knee points Y9 and Y10 */ + u32 gammaKneeY0; /*!< Gamma knee point Y0 */ + u32 shutter_width_60; + u32 search_flicker_60; + u32 ratioImageGainBase; + u32 ratioImageGainDelta; + u32 signValueReg5F; + u32 aeGain; + u32 maxGainAE; + u32 lensCorrectCtrl; + u32 shadingParameter1; /*!< Shade Parameters */ + u32 shadingParameter2; + u32 shadingParameter3; + u32 shadingParameter4; + u32 shadingParameter5; + u32 shadingParameter6; + u32 shadingParameter7; + u32 shadingParameter8; + u32 shadingParameter9; + u32 shadingParameter10; + u32 shadingParameter11; + u32 shadingParameter12; + u32 shadingParameter13; + u32 shadingParameter14; + u32 shadingParameter15; + u32 shadingParameter16; + u32 shadingParameter17; + u32 shadingParameter18; + u32 shadingParameter19; + u32 shadingParameter20; + u32 shadingParameter21; + u32 flashCtrl; /*!< Flash control */ + u32 lineCounter; /*!< Line counter */ + u32 frameCounter; /*!< Frame counter */ + u32 HPan; /*!< Horizontal pan in decimation */ + u32 HZoom; /*!< Horizontal zoom in decimation */ + u32 HSize; /*!< Horizontal output size iIn decimation */ + u32 VPan; /*!< Vertical pan in decimation */ + u32 VZoom; /*!< Vertical zoom in decimation */ + u32 VSize; /*!< Vertical output size in decimation */ +} mt9v111_IFPReg; + +/*! + * mt9v111 Config structure + */ +typedef struct { + mt9v111_coreReg *coreReg; /*!< Sensor Core Register Bank */ + mt9v111_IFPReg *ifpReg; /*!< IFP Register Bank */ +} mt9v111_conf; + +typedef struct { + u8 index; + u16 width; + u16 height; +} mt9v111_image_format; + +#endif /* MT9V111_H_ */ diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c new file mode 100644 index 000000000000..83c98ad6d280 --- /dev/null +++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c @@ -0,0 +1,2812 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/media/video/mxc/capture/mxc_v4l2_capture.c + * + * @brief Mxc Video For Linux 2 driver + * + * @ingroup MXC_V4L2_CAPTURE + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" +#include "ipu_prp_sw.h" + +static int video_nr = -1, local_buf_num; +static cam_data *g_cam; + +/*! This data is used for the output to the display. */ +#define MXC_V4L2_CAPTURE_NUM_OUTPUTS 3 +#define MXC_V4L2_CAPTURE_NUM_INPUTS 2 +static struct v4l2_output mxc_capture_outputs[MXC_V4L2_CAPTURE_NUM_OUTPUTS] = { + { + .index = 0, + .name = "DISP3 BG", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN, + }, + { + .index = 1, + .name = "DISP3 BG - DI1", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN, + }, + { + .index = 2, + .name = "DISP3 FG", + .type = V4L2_OUTPUT_TYPE_ANALOG, + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN, + }, +}; + +static struct v4l2_input mxc_capture_inputs[MXC_V4L2_CAPTURE_NUM_INPUTS] = { + { + .index = 0, + .name = "CSI IC MEM", + .type = V4L2_INPUT_TYPE_CAMERA, + .audioset = 0, + .tuner = 0, + .std = V4L2_STD_UNKNOWN, + .status = 0, + }, + { + .index = 1, + .name = "CSI MEM", + .type = V4L2_INPUT_TYPE_CAMERA, + .audioset = 0, + .tuner = 0, + .std = V4L2_STD_UNKNOWN, + .status = V4L2_IN_ST_NO_POWER, + }, +}; + +/*! List of TV input video formats supported. The video formats is corresponding + * to the v4l2_id in video_fmt_t. + * Currently, only PAL and NTSC is supported. Needs to be expanded in the + * future. + */ +typedef enum { + TV_NTSC = 0, /*!< Locked on (M) NTSC video signal. */ + TV_PAL, /*!< (B, G, H, I, N)PAL video signal. */ + TV_NOT_LOCKED, /*!< Not locked on a signal. */ +} video_fmt_idx; + +/*! Number of video standards supported (including 'not locked' signal). */ +#define TV_STD_MAX (TV_NOT_LOCKED + 1) + +/*! Video format structure. */ +typedef struct { + int v4l2_id; /*!< Video for linux ID. */ + char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */ + u16 raw_width; /*!< Raw width. */ + u16 raw_height; /*!< Raw height. */ + u16 active_width; /*!< Active width. */ + u16 active_height; /*!< Active height. */ + u16 active_top; /*!< Active top. */ + u16 active_left; /*!< Active left. */ +} video_fmt_t; + +/*! + * Description of video formats supported. + * + * PAL: raw=720x625, active=720x576. + * NTSC: raw=720x525, active=720x480. + */ +static video_fmt_t video_fmts[] = { + { /*! NTSC */ + .v4l2_id = V4L2_STD_NTSC, + .name = "NTSC", + .raw_width = 720, /* SENS_FRM_WIDTH */ + .raw_height = 525, /* SENS_FRM_HEIGHT */ + .active_width = 720, /* ACT_FRM_WIDTH */ + .active_height = 480, /* ACT_FRM_HEIGHT */ + .active_top = 13, + .active_left = 0, + }, + { /*! (B, G, H, I, N) PAL */ + .v4l2_id = V4L2_STD_PAL, + .name = "PAL", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + .active_top = 0, + .active_left = 0, + }, + { /*! Unlocked standard */ + .v4l2_id = V4L2_STD_ALL, + .name = "Autodetect", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + .active_top = 0, + .active_left = 0, + }, +}; + +/*!* Standard index of TV. */ +static video_fmt_idx video_index = TV_NOT_LOCKED; + +static int mxc_v4l2_master_attach(struct v4l2_int_device *slave); +static void mxc_v4l2_master_detach(struct v4l2_int_device *slave); +static int start_preview(cam_data *cam); +static int stop_preview(cam_data *cam); + +/*! Information about this driver. */ +static struct v4l2_int_master mxc_v4l2_master = { + .attach = mxc_v4l2_master_attach, + .detach = mxc_v4l2_master_detach, +}; + +static struct v4l2_int_device mxc_v4l2_int_device = { + .module = THIS_MODULE, + .name = "mxc_v4l2_cap", + .type = v4l2_int_type_master, + .u = { + .master = &mxc_v4l2_master, + }, +}; + +/*************************************************************************** + * Functions for handling Frame buffers. + **************************************************************************/ + +/*! + * Free frame buffers + * + * @param cam Structure cam_data * + * + * @return status 0 success. + */ +static int mxc_free_frame_buf(cam_data *cam) +{ + int i; + + pr_debug("MVC: In mxc_free_frame_buf\n"); + + for (i = 0; i < FRAME_NUM; i++) { + if (cam->frame[i].vaddress != 0) { + dma_free_coherent(0, cam->frame[i].buffer.length, + cam->frame[i].vaddress, + cam->frame[i].paddress); + cam->frame[i].vaddress = 0; + } + } + + return 0; +} + +/*! + * Allocate frame buffers + * + * @param cam Structure cam_data* + * @param count int number of buffer need to allocated + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int mxc_allocate_frame_buf(cam_data *cam, int count) +{ + int i; + + pr_debug("In MVC:mxc_allocate_frame_buf - size=%d\n", + cam->v2f.fmt.pix.sizeimage); + + for (i = 0; i < count; i++) { + cam->frame[i].vaddress = + dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + &cam->frame[i].paddress, + GFP_DMA | GFP_KERNEL); + if (cam->frame[i].vaddress == 0) { + pr_err("ERROR: v4l2 capture: " + "mxc_allocate_frame_buf failed.\n"); + mxc_free_frame_buf(cam); + return -ENOBUFS; + } + cam->frame[i].buffer.index = i; + cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; + cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cam->frame[i].buffer.length = + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); + cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP; + cam->frame[i].buffer.m.offset = cam->frame[i].paddress; + cam->frame[i].index = i; + } + + return 0; +} + +/*! + * Free frame buffers status + * + * @param cam Structure cam_data * + * + * @return none + */ +static void mxc_free_frames(cam_data *cam) +{ + int i; + + pr_debug("In MVC:mxc_free_frames\n"); + + for (i = 0; i < FRAME_NUM; i++) { + cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; + } + + cam->enc_counter = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); +} + +/*! + * Return the buffer status + * + * @param cam Structure cam_data * + * @param buf Structure v4l2_buffer * + * + * @return status 0 success, EINVAL failed. + */ +static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf) +{ + pr_debug("In MVC:mxc_v4l2_buffer_status\n"); + + if (buf->index < 0 || buf->index >= FRAME_NUM) { + pr_err("ERROR: v4l2 capture: mxc_v4l2_buffer_status buffers " + "not allocated\n"); + return -EINVAL; + } + + memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf)); + return 0; +} + +/*************************************************************************** + * Functions for handling the video stream. + **************************************************************************/ + +/*! + * Indicates whether the palette is supported. + * + * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + return ((palette == V4L2_PIX_FMT_RGB565) || + (palette == V4L2_PIX_FMT_BGR24) || + (palette == V4L2_PIX_FMT_RGB24) || + (palette == V4L2_PIX_FMT_BGR32) || + (palette == V4L2_PIX_FMT_RGB32) || + (palette == V4L2_PIX_FMT_YUV422P) || + (palette == V4L2_PIX_FMT_UYVY) || + (palette == V4L2_PIX_FMT_YUYV) || + (palette == V4L2_PIX_FMT_YUV420) || + (palette == V4L2_PIX_FMT_NV12)); +} + +/*! + * Start the encoder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int mxc_streamon(cam_data *cam) +{ + struct mxc_v4l_frame *frame; + int err = 0; + + pr_debug("In MVC:mxc_streamon\n"); + + if (NULL == cam) { + pr_err("ERROR! cam parameter is NULL\n"); + return -1; + } + + if (cam->capture_on) { + pr_err("ERROR: v4l2 capture: Capture stream has been turned " + " on\n"); + return -1; + } + + if (list_empty(&cam->ready_q)) { + pr_err("ERROR: v4l2 capture: mxc_streamon buffer has not been " + "queued yet\n"); + return -EINVAL; + } + + cam->capture_pid = current->pid; + + if (cam->overlay_on == true) + stop_preview(cam); + + if (cam->enc_enable) { + err = cam->enc_enable(cam); + if (err != 0) { + return err; + } + } + + cam->ping_pong_csi = 0; + local_buf_num = 0; + if (cam->enc_update_eba) { + frame = + list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&frame->queue, &cam->working_q); + frame->ipu_buf_num = cam->ping_pong_csi; + err = cam->enc_update_eba(frame->buffer.m.offset, + &cam->ping_pong_csi); + + frame = + list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); + list_del(cam->ready_q.next); + list_add_tail(&frame->queue, &cam->working_q); + frame->ipu_buf_num = cam->ping_pong_csi; + err |= cam->enc_update_eba(frame->buffer.m.offset, + &cam->ping_pong_csi); + } else { + return -EINVAL; + } + + if (cam->overlay_on == true) + start_preview(cam); + + if (cam->enc_enable_csi) { + err = cam->enc_enable_csi(cam); + if (err != 0) + return err; + } + + cam->capture_on = true; + + return err; +} + +/*! + * Shut down the encoder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int mxc_streamoff(cam_data *cam) +{ + int err = 0; + + pr_debug("In MVC:mxc_streamoff\n"); + + if (cam->capture_on == false) + return 0; + + if (cam->enc_disable_csi) { + err = cam->enc_disable_csi(cam); + if (err != 0) + return err; + } + if (cam->enc_disable) + err = cam->enc_disable(cam); + + mxc_free_frames(cam); + mxc_capture_inputs[cam->current_input].status |= V4L2_IN_ST_NO_POWER; + cam->capture_on = false; + return err; +} + +/*! + * Valid and adjust the overlay window size, position + * + * @param cam structure cam_data * + * @param win struct v4l2_window * + * + * @return 0 + */ +static int verify_preview(cam_data *cam, struct v4l2_window *win) +{ + int i = 0, width_bound = 0, height_bound = 0; + int *width, *height; + unsigned int ipu_ch = CHAN_NONE; + struct fb_info *bg_fbi = NULL, *fbi = NULL; + bool foregound_fb; + mm_segment_t old_fs; + + pr_debug("In MVC: verify_preview\n"); + + do { + fbi = (struct fb_info *)registered_fb[i]; + if (fbi == NULL) { + pr_err("ERROR: verify_preview frame buffer NULL.\n"); + return -1; + } + + /* Which DI supports 2 layers? */ + if (strncmp(fbi->fix.id, "DISP3 BG", 8) == 0) { + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN, + (unsigned long)&ipu_ch); + set_fs(old_fs); + } + if (ipu_ch == MEM_BG_SYNC) { + bg_fbi = fbi; + pr_debug("Found background frame buffer.\n"); + } + } + + /* Found the frame buffer to preview on. */ + if (strcmp(fbi->fix.id, + mxc_capture_outputs[cam->output].name) == 0) { + if (strcmp(fbi->fix.id, "DISP3 FG") == 0) + foregound_fb = true; + + cam->overlay_fb = fbi; + break; + } + } while (++i < FB_MAX); + + if (foregound_fb) { + width_bound = bg_fbi->var.xres; + height_bound = bg_fbi->var.yres; + + if (win->w.width + win->w.left > bg_fbi->var.xres || + win->w.height + win->w.top > bg_fbi->var.yres) { + pr_err("ERROR: FG window position exceeds.\n"); + return -1; + } + } else { + /* 4 bytes alignment for BG */ + width_bound = cam->overlay_fb->var.xres; + height_bound = cam->overlay_fb->var.yres; + + if (cam->overlay_fb->var.bits_per_pixel == 24) { + win->w.left -= win->w.left % 4; + } else if (cam->overlay_fb->var.bits_per_pixel == 16) { + win->w.left -= win->w.left % 2; + } + + if (win->w.width + win->w.left > cam->overlay_fb->var.xres) + win->w.width = cam->overlay_fb->var.xres - win->w.left; + if (win->w.height + win->w.top > cam->overlay_fb->var.yres) + win->w.height = cam->overlay_fb->var.yres - win->w.top; + } + + /* stride line limitation */ + win->w.height -= win->w.height % 8; + win->w.width -= win->w.width % 8; + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + height = &win->w.width; + width = &win->w.height; + } else { + width = &win->w.width; + height = &win->w.height; + } + + if (*width == 0 || *height == 0) { + pr_err("ERROR: v4l2 capture: width or height" + " too small.\n"); + return -EINVAL; + } + + if ((cam->crop_bounds.width / *width > 8) || + ((cam->crop_bounds.width / *width == 8) && + (cam->crop_bounds.width % *width))) { + *width = cam->crop_bounds.width / 8; + if (*width % 8) + *width += 8 - *width % 8; + if (*width + win->w.left > width_bound) { + pr_err("ERROR: v4l2 capture: width exceeds " + "resize limit.\n"); + return -1; + } + pr_err("ERROR: v4l2 capture: width exceeds limit. " + "Resize to %d.\n", + *width); + } + + if ((cam->crop_bounds.height / *height > 8) || + ((cam->crop_bounds.height / *height == 8) && + (cam->crop_bounds.height % *height))) { + *height = cam->crop_bounds.height / 8; + if (*height % 8) + *height += 8 - *height % 8; + if (*height + win->w.top > height_bound) { + pr_err("ERROR: v4l2 capture: height exceeds " + "resize limit.\n"); + return -1; + } + pr_err("ERROR: v4l2 capture: height exceeds limit " + "resize to %d.\n", + *height); + } + + return 0; +} + +/*! + * start the viewfinder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int start_preview(cam_data *cam) +{ + int err = 0; + + pr_debug("MVC: start_preview\n"); + + if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) + err = prp_vf_sdc_select(cam); + else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY) + err = prp_vf_sdc_select_bg(cam); + if (err != 0) + return err; + + err = cam->vf_start_sdc(cam); + if (err != 0) + return err; + + if (cam->vf_enable_csi) + err = cam->vf_enable_csi(cam); + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + return err; +} + +/*! + * shut down the viewfinder job + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static int stop_preview(cam_data *cam) +{ + int err = 0; + + pr_debug("MVC: stop preview\n"); + + if (cam->vf_disable_csi) { + err = cam->vf_disable_csi(cam); + if (err != 0) + return err; + } + + if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) + err = prp_vf_sdc_deselect(cam); + else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY) + err = prp_vf_sdc_deselect_bg(cam); + + return err; +} + +/*************************************************************************** + * VIDIOC Functions. + **************************************************************************/ + +/*! + * V4L2 - mxc_v4l2_g_fmt function + * + * @param cam structure cam_data * + * + * @param f structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f) +{ + int retval = 0; + + pr_debug("In MVC: mxc_v4l2_g_fmt type=%d\n", f->type); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + f->fmt.pix = cam->v2f.fmt.pix; + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); + f->fmt.win = cam->win; + break; + default: + pr_debug(" type is invalid\n"); + retval = -EINVAL; + } + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + return retval; +} + +/*! + * V4L2 - mxc_v4l2_s_fmt function + * + * @param cam structure cam_data * + * + * @param f structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f) +{ + int retval = 0; + int size = 0; + int bytesperline = 0; + int *width, *height; + + pr_debug("In MVC: mxc_v4l2_s_fmt\n"); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + if (!valid_mode(f->fmt.pix.pixelformat)) { + pr_err("ERROR: v4l2 capture: mxc_v4l2_s_fmt: format " + "not supported\n"); + return -EINVAL; + } + + /* + * Force the capture window resolution to be crop bounds + * for CSI MEM input mode. + */ + if (strcmp(mxc_capture_inputs[cam->current_input].name, + "CSI MEM") == 0) { + f->fmt.pix.width = cam->crop_current.width; + f->fmt.pix.height = cam->crop_current.height; + } + + if (cam->rotation >= IPU_ROTATE_90_RIGHT) { + height = &f->fmt.pix.width; + width = &f->fmt.pix.height; + } else { + width = &f->fmt.pix.width; + height = &f->fmt.pix.height; + } + + /* stride line limitation */ + *width -= *width % 8; + *height -= *height % 8; + + if (*width == 0 || *height == 0) { + pr_err("ERROR: v4l2 capture: width or height" + " too small.\n"); + return -EINVAL; + } + + if ((cam->crop_current.width / *width > 8) || + ((cam->crop_current.width / *width == 8) && + (cam->crop_current.width % *width))) { + *width = cam->crop_current.width / 8; + if (*width % 8) + *width += 8 - *width % 8; + pr_err("ERROR: v4l2 capture: width exceeds limit " + "resize to %d.\n", + *width); + } + + if ((cam->crop_current.height / *height > 8) || + ((cam->crop_current.height / *height == 8) && + (cam->crop_current.height % *height))) { + *height = cam->crop_current.height / 8; + if (*height % 8) + *height += 8 - *height % 8; + pr_err("ERROR: v4l2 capture: height exceeds limit " + "resize to %d.\n", + *height); + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_RGB565: + size = f->fmt.pix.width * f->fmt.pix.height * 2; + bytesperline = f->fmt.pix.width * 2; + break; + case V4L2_PIX_FMT_BGR24: + size = f->fmt.pix.width * f->fmt.pix.height * 3; + bytesperline = f->fmt.pix.width * 3; + break; + case V4L2_PIX_FMT_RGB24: + size = f->fmt.pix.width * f->fmt.pix.height * 3; + bytesperline = f->fmt.pix.width * 3; + break; + case V4L2_PIX_FMT_BGR32: + size = f->fmt.pix.width * f->fmt.pix.height * 4; + bytesperline = f->fmt.pix.width * 4; + break; + case V4L2_PIX_FMT_RGB32: + size = f->fmt.pix.width * f->fmt.pix.height * 4; + bytesperline = f->fmt.pix.width * 4; + break; + case V4L2_PIX_FMT_YUV422P: + size = f->fmt.pix.width * f->fmt.pix.height * 2; + bytesperline = f->fmt.pix.width; + break; + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_YUYV: + size = f->fmt.pix.width * f->fmt.pix.height * 2; + bytesperline = f->fmt.pix.width * 2; + break; + case V4L2_PIX_FMT_YUV420: + size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; + bytesperline = f->fmt.pix.width; + break; + case V4L2_PIX_FMT_NV12: + size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; + bytesperline = f->fmt.pix.width; + break; + default: + break; + } + + if (f->fmt.pix.bytesperline < bytesperline) { + f->fmt.pix.bytesperline = bytesperline; + } else { + bytesperline = f->fmt.pix.bytesperline; + } + + if (f->fmt.pix.sizeimage < size) { + f->fmt.pix.sizeimage = size; + } else { + size = f->fmt.pix.sizeimage; + } + + cam->v2f.fmt.pix = f->fmt.pix; + + if (cam->v2f.fmt.pix.priv != 0) { + if (copy_from_user(&cam->offset, + (void *)cam->v2f.fmt.pix.priv, + sizeof(cam->offset))) { + retval = -EFAULT; + break; + } + } + break; + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + pr_debug(" type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); + retval = verify_preview(cam, &f->fmt.win); + cam->win = f->fmt.win; + break; + default: + retval = -EINVAL; + } + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + return retval; +} + +/*! + * get control param + * + * @param cam structure cam_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) +{ + int status = 0; + + pr_debug("In MVC:mxc_v4l2_g_ctrl\n"); + + /* probably don't need to store the values that can be retrieved, + * locally, but they are for now. */ + switch (c->id) { + case V4L2_CID_HFLIP: + /* This is handled in the ipu. */ + if (cam->rotation == IPU_ROTATE_HORIZ_FLIP) + c->value = 1; + break; + case V4L2_CID_VFLIP: + /* This is handled in the ipu. */ + if (cam->rotation == IPU_ROTATE_VERT_FLIP) + c->value = 1; + break; + case V4L2_CID_MXC_ROT: + /* This is handled in the ipu. */ + c->value = cam->rotation; + break; + case V4L2_CID_BRIGHTNESS: + if (cam->sensor) { + c->value = cam->bright; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->bright = c->value; + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + status = -ENODEV; + } + break; + case V4L2_CID_HUE: + if (cam->sensor) { + c->value = cam->hue; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->hue = c->value; + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + status = -ENODEV; + } + break; + case V4L2_CID_CONTRAST: + if (cam->sensor) { + c->value = cam->contrast; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->contrast = c->value; + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + status = -ENODEV; + } + break; + case V4L2_CID_SATURATION: + if (cam->sensor) { + c->value = cam->saturation; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->saturation = c->value; + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + status = -ENODEV; + } + break; + case V4L2_CID_RED_BALANCE: + if (cam->sensor) { + c->value = cam->red; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->red = c->value; + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + status = -ENODEV; + } + break; + case V4L2_CID_BLUE_BALANCE: + if (cam->sensor) { + c->value = cam->blue; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->blue = c->value; + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + status = -ENODEV; + } + break; + case V4L2_CID_BLACK_LEVEL: + if (cam->sensor) { + c->value = cam->ae_mode; + status = vidioc_int_g_ctrl(cam->sensor, c); + cam->ae_mode = c->value; + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + status = -ENODEV; + } + break; + default: + pr_err("ERROR: v4l2 capture: unsupported ioctrl!\n"); + } + + return status; +} + +/*! + * V4L2 - set_control function + * V4L2_CID_PRIVATE_BASE is the extention for IPU preprocessing. + * 0 for normal operation + * 1 for vertical flip + * 2 for horizontal flip + * 3 for horizontal and vertical flip + * 4 for 90 degree rotation + * @param cam structure cam_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) +{ + int ret = 0; + int tmp_rotation = IPU_ROTATE_NONE; + + pr_debug("In MVC:mxc_v4l2_s_ctrl\n"); + + switch (c->id) { + case V4L2_CID_HFLIP: + /* This is done by the IPU */ + if (c->value == 1) { + if ((cam->rotation != IPU_ROTATE_VERT_FLIP) && + (cam->rotation != IPU_ROTATE_180)) + cam->rotation = IPU_ROTATE_HORIZ_FLIP; + else + cam->rotation = IPU_ROTATE_180; + } else { + if (cam->rotation == IPU_ROTATE_HORIZ_FLIP) + cam->rotation = IPU_ROTATE_NONE; + if (cam->rotation == IPU_ROTATE_180) + cam->rotation = IPU_ROTATE_VERT_FLIP; + } + break; + case V4L2_CID_VFLIP: + /* This is done by the IPU */ + if (c->value == 1) { + if ((cam->rotation != IPU_ROTATE_HORIZ_FLIP) && + (cam->rotation != IPU_ROTATE_180)) + cam->rotation = IPU_ROTATE_VERT_FLIP; + else + cam->rotation = IPU_ROTATE_180; + } else { + if (cam->rotation == IPU_ROTATE_VERT_FLIP) + cam->rotation = IPU_ROTATE_NONE; + if (cam->rotation == IPU_ROTATE_180) + cam->rotation = IPU_ROTATE_HORIZ_FLIP; + } + break; + case V4L2_CID_MXC_ROT: + case V4L2_CID_MXC_VF_ROT: + /* This is done by the IPU */ + switch (c->value) { + case V4L2_MXC_ROTATE_NONE: + tmp_rotation = IPU_ROTATE_NONE; + break; + case V4L2_MXC_ROTATE_VERT_FLIP: + tmp_rotation = IPU_ROTATE_VERT_FLIP; + break; + case V4L2_MXC_ROTATE_HORIZ_FLIP: + tmp_rotation = IPU_ROTATE_HORIZ_FLIP; + break; + case V4L2_MXC_ROTATE_180: + tmp_rotation = IPU_ROTATE_180; + break; + case V4L2_MXC_ROTATE_90_RIGHT: + tmp_rotation = IPU_ROTATE_90_RIGHT; + break; + case V4L2_MXC_ROTATE_90_RIGHT_VFLIP: + tmp_rotation = IPU_ROTATE_90_RIGHT_VFLIP; + break; + case V4L2_MXC_ROTATE_90_RIGHT_HFLIP: + tmp_rotation = IPU_ROTATE_90_RIGHT_HFLIP; + break; + case V4L2_MXC_ROTATE_90_LEFT: + tmp_rotation = IPU_ROTATE_90_LEFT; + break; + default: + ret = -EINVAL; + } + + if (c->id == V4L2_CID_MXC_VF_ROT) + cam->vf_rotation = tmp_rotation; + else + cam->rotation = tmp_rotation; + + break; + case V4L2_CID_HUE: + if (cam->sensor) { + cam->hue = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + ret = -ENODEV; + } + break; + case V4L2_CID_CONTRAST: + if (cam->sensor) { + cam->contrast = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + ret = -ENODEV; + } + break; + case V4L2_CID_BRIGHTNESS: + if (cam->sensor) { + cam->bright = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + ret = -ENODEV; + } + break; + case V4L2_CID_SATURATION: + if (cam->sensor) { + cam->saturation = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + ret = -ENODEV; + } + break; + case V4L2_CID_RED_BALANCE: + if (cam->sensor) { + cam->red = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + ret = -ENODEV; + } + break; + case V4L2_CID_BLUE_BALANCE: + if (cam->sensor) { + cam->blue = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + ret = -ENODEV; + } + break; + case V4L2_CID_EXPOSURE: + if (cam->sensor) { + cam->ae_mode = c->value; + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + ret = vidioc_int_s_ctrl(cam->sensor, c); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); + } else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + ret = -ENODEV; + } + break; + case V4L2_CID_MXC_FLASH: +#ifdef CONFIG_MXC_IPU_V1 + ipu_csi_flash_strobe(true); +#endif + break; + default: + pr_debug(" default case\n"); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * V4L2 - mxc_v4l2_s_param function + * Allows setting of capturemode and frame rate. + * + * @param cam structure cam_data * + * @param parm structure v4l2_streamparm * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) +{ + struct v4l2_ifparm ifparm; + struct v4l2_format cam_fmt; + struct v4l2_streamparm currentparm; + ipu_csi_signal_cfg_t csi_param; + int err = 0; + + pr_debug("In mxc_v4l2_s_param\n"); + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n"); + return -EINVAL; + } + + /* Stop the viewfinder */ + if (cam->overlay_on == true) { + stop_preview(cam); + } + + currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + /* First check that this device can support the changes requested. */ + err = vidioc_int_g_parm(cam->sensor, ¤tparm); + if (err) { + pr_err("%s: vidioc_int_g_parm returned an error %d\n", + __func__, err); + goto exit; + } + + pr_debug(" Current capabilities are %x\n", + currentparm.parm.capture.capability); + pr_debug(" Current capturemode is %d change to %d\n", + currentparm.parm.capture.capturemode, + parm->parm.capture.capturemode); + pr_debug(" Current framerate is %d change to %d\n", + currentparm.parm.capture.timeperframe.denominator, + parm->parm.capture.timeperframe.denominator); + + /* This will change any camera settings needed. */ + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + err = vidioc_int_s_parm(cam->sensor, parm); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + if (err) { + pr_err("%s: vidioc_int_s_parm returned an error %d\n", + __func__, err); + goto exit; + } + + /* If resolution changed, need to re-program the CSI */ + /* Get new values. */ + vidioc_int_g_ifparm(cam->sensor, &ifparm); + + csi_param.data_width = 0; + csi_param.clk_mode = 0; + csi_param.ext_vsync = 0; + csi_param.Vsync_pol = 0; + csi_param.Hsync_pol = 0; + csi_param.pixclk_pol = 0; + csi_param.data_pol = 0; + csi_param.sens_clksrc = 0; + csi_param.pack_tight = 0; + csi_param.force_eof = 0; + csi_param.data_en_pol = 0; + csi_param.data_fmt = 0; + csi_param.csi = 0; + csi_param.mclk = 0; + + /* This may not work on other platforms. Check when adding a new one.*/ + pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr); + if (ifparm.u.bt656.clock_curr == 0) { + csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED; + } else { + csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK; + } + + csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv; + + if (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT) { + csi_param.data_width = IPU_CSI_DATA_WIDTH_8; + } else if (ifparm.u.bt656.mode + == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) { + csi_param.data_width = IPU_CSI_DATA_WIDTH_10; + } else { + csi_param.data_width = IPU_CSI_DATA_WIDTH_8; + } + + csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv; + csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv; + csi_param.ext_vsync = ifparm.u.bt656.bt_sync_correct; + + /* if the capturemode changed, the size bounds will have changed. */ + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); + pr_debug(" g_fmt_cap returns widthxheight of input as %d x %d\n", + cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); + + csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat; + + cam->crop_bounds.top = cam->crop_bounds.left = 0; + cam->crop_bounds.width = cam_fmt.fmt.pix.width; + cam->crop_bounds.height = cam_fmt.fmt.pix.height; + + /* + * Set the default current cropped resolution to be the same with + * the cropping boundary(except for tvin module). + */ + if (cam->device_type != 1) { + cam->crop_current.width = cam->crop_bounds.width; + cam->crop_current.height = cam->crop_bounds.height; + } + + /* This essentially loses the data at the left and bottom of the image + * giving a digital zoom image, if crop_current is less than the full + * size of the image. */ + ipu_csi_set_window_size(cam->crop_current.width, + cam->crop_current.height, cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, + cam->csi); + ipu_csi_init_interface(cam->crop_bounds.width, + cam->crop_bounds.height, + cam_fmt.fmt.pix.pixelformat, csi_param); + + +exit: + if (cam->overlay_on == true) + start_preview(cam); + + return err; +} + +/*! + * V4L2 - mxc_v4l2_s_std function + * + * Sets the TV standard to be used. + * + * @param cam structure cam_data * + * @param parm structure v4l2_streamparm * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_s_std(cam_data *cam, v4l2_std_id e) +{ + pr_debug("In mxc_v4l2_s_std %Lx\n", e); + if (e == V4L2_STD_PAL) { + pr_debug(" Setting standard to PAL %Lx\n", V4L2_STD_PAL); + cam->standard.id = V4L2_STD_PAL; + video_index = TV_PAL; + } else if (e == V4L2_STD_NTSC) { + pr_debug(" Setting standard to NTSC %Lx\n", + V4L2_STD_NTSC); + /* Get rid of the white dot line in NTSC signal input */ + cam->standard.id = V4L2_STD_NTSC; + video_index = TV_NTSC; + } else { + cam->standard.id = V4L2_STD_ALL; + video_index = TV_NOT_LOCKED; + pr_err("ERROR: unrecognized std! %Lx (PAL=%Lx, NTSC=%Lx\n", + e, V4L2_STD_PAL, V4L2_STD_NTSC); + } + + cam->standard.index = video_index; + strcpy(cam->standard.name, video_fmts[video_index].name); + cam->crop_bounds.width = video_fmts[video_index].raw_width; + cam->crop_bounds.height = video_fmts[video_index].raw_height; + cam->crop_current.width = video_fmts[video_index].active_width; + cam->crop_current.height = video_fmts[video_index].active_height; + cam->crop_current.top = video_fmts[video_index].active_top; + cam->crop_current.left = video_fmts[video_index].active_left; + + return 0; +} + +/*! + * V4L2 - mxc_v4l2_g_std function + * + * Gets the TV standard from the TV input device. + * + * @param cam structure cam_data * + * + * @param e structure v4l2_streamparm * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2_g_std(cam_data *cam, v4l2_std_id *e) +{ + struct v4l2_format tv_fmt; + + pr_debug("In mxc_v4l2_g_std\n"); + + if (cam->device_type == 1) { + /* Use this function to get what the TV-In device detects the + * format to be. pixelformat is used to return the std value + * since the interface has no vidioc_g_std.*/ + tv_fmt.type = V4L2_BUF_TYPE_PRIVATE; + vidioc_int_g_fmt_cap(cam->sensor, &tv_fmt); + + /* If the TV-in automatically detects the standard, then if it + * changes, the settings need to change. */ + if (cam->standard_autodetect) { + if (cam->standard.id != tv_fmt.fmt.pix.pixelformat) { + pr_debug("MVC: mxc_v4l2_g_std: " + "Changing standard\n"); + mxc_v4l2_s_std(cam, tv_fmt.fmt.pix.pixelformat); + } + } + + *e = tv_fmt.fmt.pix.pixelformat; + } + + return 0; +} + +/*! + * Dequeue one V4L capture buffer + * + * @param cam structure cam_data * + * @param buf structure v4l2_buffer * + * + * @return status 0 success, EINVAL invalid frame number, + * ETIME timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) +{ + int retval = 0; + struct mxc_v4l_frame *frame; + unsigned long lock_flags; + + pr_debug("In MVC:mxc_v4l_dqueue\n"); + + if (!wait_event_interruptible_timeout(cam->enc_queue, + cam->enc_counter != 0, 10 * HZ)) { + pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout " + "enc_counter %x\n", + cam->enc_counter); + return -ETIME; + } else if (signal_pending(current)) { + pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() " + "interrupt received\n"); + return -ERESTARTSYS; + } + + spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags); + + cam->enc_counter--; + + frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue); + list_del(cam->done_q.next); + if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) { + frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE; + } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { + pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " + "Buffer not filled.\n"); + frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; + retval = -EINVAL; + } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) { + pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " + "Buffer not queued.\n"); + retval = -EINVAL; + } + + buf->bytesused = cam->v2f.fmt.pix.sizeimage; + buf->index = frame->index; + buf->flags = frame->buffer.flags; + buf->m = cam->frame[frame->index].buffer.m; + buf->timestamp = cam->frame[frame->index].buffer.timestamp; + + spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags); + return retval; +} + +/*! + * V4L interface - open function + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l_open(struct file *file) +{ + struct v4l2_ifparm ifparm; + struct v4l2_format cam_fmt; + ipu_csi_signal_cfg_t csi_param; + struct video_device *dev = video_devdata(file); + cam_data *cam = video_get_drvdata(dev); + int err = 0; + + pr_debug("\nIn MVC: mxc_v4l_open\n"); + pr_debug(" device name is %s\n", dev->name); + + if (!cam) { + pr_err("ERROR: v4l2 capture: Internal error, " + "cam_data not found!\n"); + return -EBADF; + } + + if (cam->sensor == NULL || + cam->sensor->type != v4l2_int_type_slave) { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + return -EAGAIN; + } + + down(&cam->busy_lock); + err = 0; + if (signal_pending(current)) + goto oops; + + if (cam->open_count++ == 0) { + wait_event_interruptible(cam->power_queue, + cam->low_power == false); + + if (strcmp(mxc_capture_inputs[cam->current_input].name, + "CSI MEM") == 0) { +#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE) + err = csi_enc_select(cam); +#endif + } else if (strcmp(mxc_capture_inputs[cam->current_input].name, + "CSI IC MEM") == 0) { +#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) + err = prp_enc_select(cam); +#endif + } + + cam->enc_counter = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); + + vidioc_int_g_ifparm(cam->sensor, &ifparm); + + csi_param.sens_clksrc = 0; + + csi_param.clk_mode = 0; + csi_param.data_pol = 0; + csi_param.ext_vsync = 0; + + csi_param.pack_tight = 0; + csi_param.force_eof = 0; + csi_param.data_en_pol = 0; + csi_param.mclk = ifparm.u.bt656.clock_curr; + + csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv; + + /* Once we handle multiple inputs this will need to change. */ + csi_param.csi = 0; + + if (ifparm.u.bt656.mode + == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT) + csi_param.data_width = IPU_CSI_DATA_WIDTH_8; + else if (ifparm.u.bt656.mode + == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) + csi_param.data_width = IPU_CSI_DATA_WIDTH_10; + else + csi_param.data_width = IPU_CSI_DATA_WIDTH_8; + + + csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv; + csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv; + + csi_param.csi = cam->csi; + + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); + + /* Reset the sizes. Needed to prevent carryover of last + * operation.*/ + cam->crop_bounds.top = cam->crop_bounds.left = 0; + cam->crop_bounds.width = cam_fmt.fmt.pix.width; + cam->crop_bounds.height = cam_fmt.fmt.pix.height; + + /* This also is the max crop size for this device. */ + cam->crop_defrect.top = cam->crop_defrect.left = 0; + cam->crop_defrect.width = cam_fmt.fmt.pix.width; + cam->crop_defrect.height = cam_fmt.fmt.pix.height; + + /* At this point, this is also the current image size. */ + cam->crop_current.top = cam->crop_current.left = 0; + cam->crop_current.width = cam_fmt.fmt.pix.width; + cam->crop_current.height = cam_fmt.fmt.pix.height; + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat; + pr_debug("On Open: Input to ipu size is %d x %d\n", + cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); + ipu_csi_set_window_size(cam->crop_current.width, + cam->crop_current.width, + cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, + cam->csi); + ipu_csi_init_interface(cam->crop_bounds.width, + cam->crop_bounds.height, + cam_fmt.fmt.pix.pixelformat, + csi_param); + + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + true, true); + vidioc_int_init(cam->sensor); + + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, + false, false); +} + + file->private_data = dev; + + oops: + up(&cam->busy_lock); + return err; +} + +/*! + * V4L interface - close function + * + * @param file struct file * + * + * @return 0 success + */ +static int mxc_v4l_close(struct file *file) +{ + struct video_device *dev = video_devdata(file); + int err = 0; + cam_data *cam = video_get_drvdata(dev); + + pr_debug("In MVC:mxc_v4l_close\n"); + + if (!cam) { + pr_err("ERROR: v4l2 capture: Internal error, " + "cam_data not found!\n"); + return -EBADF; + } + + /* for the case somebody hit the ctrl C */ + if (cam->overlay_pid == current->pid) { + err = stop_preview(cam); + cam->overlay_on = false; + } + if (cam->capture_pid == current->pid) { + err |= mxc_streamoff(cam); + wake_up_interruptible(&cam->enc_queue); + } + + if (--cam->open_count == 0) { + wait_event_interruptible(cam->power_queue, + cam->low_power == false); + pr_info("mxc_v4l_close: release resource\n"); + + if (strcmp(mxc_capture_inputs[cam->current_input].name, + "CSI MEM") == 0) { +#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE) + err |= csi_enc_deselect(cam); +#endif + } else if (strcmp(mxc_capture_inputs[cam->current_input].name, + "CSI IC MEM") == 0) { +#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) + err |= prp_enc_deselect(cam); +#endif + } + + mxc_free_frame_buf(cam); + file->private_data = NULL; + + /* capture off */ + wake_up_interruptible(&cam->enc_queue); + mxc_free_frames(cam); + cam->enc_counter++; + } + + return err; +} + +#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC) || \ + defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) || \ + defined(CONFIG_MXC_IPU_CSI_ENC_MODULE) +/* + * V4L interface - read function + * + * @param file struct file * + * @param read buf char * + * @param count size_t + * @param ppos structure loff_t * + * + * @return bytes read + */ +static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count, + loff_t *ppos) +{ + int err = 0; + u8 *v_address[2]; + struct video_device *dev = video_devdata(file); + cam_data *cam = video_get_drvdata(dev); + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + /* Stop the viewfinder */ + if (cam->overlay_on == true) + stop_preview(cam); + + v_address[0] = dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + &cam->still_buf[0], + GFP_DMA | GFP_KERNEL); + + v_address[1] = dma_alloc_coherent(0, + PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), + &cam->still_buf[1], + GFP_DMA | GFP_KERNEL); + + if (!v_address[0] || !v_address[1]) { + err = -ENOBUFS; + goto exit0; + } + + err = prp_still_select(cam); + if (err != 0) { + err = -EIO; + goto exit0; + } + + cam->still_counter = 0; + err = cam->csi_start(cam); + if (err != 0) { + err = -EIO; + goto exit1; + } + + if (!wait_event_interruptible_timeout(cam->still_queue, + cam->still_counter != 0, + 10 * HZ)) { + pr_err("ERROR: v4l2 capture: mxc_v4l_read timeout counter %x\n", + cam->still_counter); + err = -ETIME; + goto exit1; + } + err = copy_to_user(buf, v_address[1], cam->v2f.fmt.pix.sizeimage); + + exit1: + prp_still_deselect(cam); + + exit0: + if (v_address[0] != 0) + dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[0], + cam->still_buf[0]); + if (v_address[1] != 0) + dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[1], + cam->still_buf[1]); + + cam->still_buf[0] = cam->still_buf[1] = 0; + + if (cam->overlay_on == true) { + start_preview(cam); + } + + up(&cam->busy_lock); + if (err < 0) + return err; + + return cam->v2f.fmt.pix.sizeimage - err; +} +#endif + +/*! + * V4L interface - ioctl function + * + * @param file struct file* + * + * @param ioctlnr unsigned int + * + * @param arg void* + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static long mxc_v4l_do_ioctl(struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *dev = video_devdata(file); + cam_data *cam = video_get_drvdata(dev); + int retval = 0; + unsigned long lock_flags; + + pr_debug("In MVC: mxc_v4l_do_ioctl %x\n", ioctlnr); + wait_event_interruptible(cam->power_queue, cam->low_power == false); + /* make this _really_ smp-safe */ + if (down_interruptible(&cam->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + /*! + * V4l2 VIDIOC_QUERYCAP ioctl + */ + case VIDIOC_QUERYCAP: { + struct v4l2_capability *cap = arg; + pr_debug(" case VIDIOC_QUERYCAP\n"); + strcpy(cap->driver, "mxc_v4l2"); + cap->version = KERNEL_VERSION(0, 1, 11); + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_STREAMING | + V4L2_CAP_READWRITE; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + break; + } + + /*! + * V4l2 VIDIOC_G_FMT ioctl + */ + case VIDIOC_G_FMT: { + struct v4l2_format *gf = arg; + pr_debug(" case VIDIOC_G_FMT\n"); + retval = mxc_v4l2_g_fmt(cam, gf); + break; + } + + /*! + * V4l2 VIDIOC_S_FMT ioctl + */ + case VIDIOC_S_FMT: { + struct v4l2_format *sf = arg; + pr_debug(" case VIDIOC_S_FMT\n"); + retval = mxc_v4l2_s_fmt(cam, sf); + break; + } + + /*! + * V4l2 VIDIOC_REQBUFS ioctl + */ + case VIDIOC_REQBUFS: { + struct v4l2_requestbuffers *req = arg; + pr_debug(" case VIDIOC_REQBUFS\n"); + + if (req->count > FRAME_NUM) { + pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " + "not enough buffers\n"); + req->count = FRAME_NUM; + } + + if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) || + (req->memory != V4L2_MEMORY_MMAP)) { + pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " + "wrong buffer type\n"); + retval = -EINVAL; + break; + } + + mxc_streamoff(cam); + mxc_free_frame_buf(cam); + cam->enc_counter = 0; + INIT_LIST_HEAD(&cam->ready_q); + INIT_LIST_HEAD(&cam->working_q); + INIT_LIST_HEAD(&cam->done_q); + + retval = mxc_allocate_frame_buf(cam, req->count); + break; + } + + /*! + * V4l2 VIDIOC_QUERYBUF ioctl + */ + case VIDIOC_QUERYBUF: { + struct v4l2_buffer *buf = arg; + int index = buf->index; + pr_debug(" case VIDIOC_QUERYBUF\n"); + + if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + pr_err("ERROR: v4l2 capture: " + "VIDIOC_QUERYBUFS: " + "wrong buffer type\n"); + retval = -EINVAL; + break; + } + + memset(buf, 0, sizeof(buf)); + buf->index = index; + + down(&cam->param_lock); + retval = mxc_v4l2_buffer_status(cam, buf); + up(&cam->param_lock); + break; + } + + /*! + * V4l2 VIDIOC_QBUF ioctl + */ + case VIDIOC_QBUF: { + struct v4l2_buffer *buf = arg; + int index = buf->index; + pr_debug(" case VIDIOC_QBUF\n"); + + spin_lock_irqsave(&cam->queue_int_lock, lock_flags); + if ((cam->frame[index].buffer.flags & 0x7) == + V4L2_BUF_FLAG_MAPPED) { + cam->frame[index].buffer.flags |= + V4L2_BUF_FLAG_QUEUED; + list_add_tail(&cam->frame[index].queue, + &cam->ready_q); + } else if (cam->frame[index].buffer. + flags & V4L2_BUF_FLAG_QUEUED) { + pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " + "buffer already queued\n"); + retval = -EINVAL; + } else if (cam->frame[index].buffer. + flags & V4L2_BUF_FLAG_DONE) { + pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " + "overwrite done buffer.\n"); + cam->frame[index].buffer.flags &= + ~V4L2_BUF_FLAG_DONE; + cam->frame[index].buffer.flags |= + V4L2_BUF_FLAG_QUEUED; + retval = -EINVAL; + } + + buf->flags = cam->frame[index].buffer.flags; + spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags); + break; + } + + /*! + * V4l2 VIDIOC_DQBUF ioctl + */ + case VIDIOC_DQBUF: { + struct v4l2_buffer *buf = arg; + pr_debug(" case VIDIOC_DQBUF\n"); + + if ((cam->enc_counter == 0) && + (file->f_flags & O_NONBLOCK)) { + retval = -EAGAIN; + break; + } + + retval = mxc_v4l_dqueue(cam, buf); + + break; + } + + /*! + * V4l2 VIDIOC_STREAMON ioctl + */ + case VIDIOC_STREAMON: { + pr_debug(" case VIDIOC_STREAMON\n"); + retval = mxc_streamon(cam); + break; + } + + /*! + * V4l2 VIDIOC_STREAMOFF ioctl + */ + case VIDIOC_STREAMOFF: { + pr_debug(" case VIDIOC_STREAMOFF\n"); + retval = mxc_streamoff(cam); + break; + } + + /*! + * V4l2 VIDIOC_G_CTRL ioctl + */ + case VIDIOC_G_CTRL: { + pr_debug(" case VIDIOC_G_CTRL\n"); + retval = mxc_v4l2_g_ctrl(cam, arg); + break; + } + + /*! + * V4l2 VIDIOC_S_CTRL ioctl + */ + case VIDIOC_S_CTRL: { + pr_debug(" case VIDIOC_S_CTRL\n"); + retval = mxc_v4l2_s_ctrl(cam, arg); + break; + } + + /*! + * V4l2 VIDIOC_CROPCAP ioctl + */ + case VIDIOC_CROPCAP: { + struct v4l2_cropcap *cap = arg; + pr_debug(" case VIDIOC_CROPCAP\n"); + if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + cap->bounds = cam->crop_bounds; + cap->defrect = cam->crop_defrect; + break; + } + + /*! + * V4l2 VIDIOC_G_CROP ioctl + */ + case VIDIOC_G_CROP: { + struct v4l2_crop *crop = arg; + pr_debug(" case VIDIOC_G_CROP\n"); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + crop->c = cam->crop_current; + break; + } + + /*! + * V4l2 VIDIOC_S_CROP ioctl + */ + case VIDIOC_S_CROP: { + struct v4l2_crop *crop = arg; + struct v4l2_rect *b = &cam->crop_bounds; + pr_debug(" case VIDIOC_S_CROP\n"); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && + crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { + retval = -EINVAL; + break; + } + + crop->c.top = (crop->c.top < b->top) ? b->top + : crop->c.top; + if (crop->c.top > b->top + b->height) + crop->c.top = b->top + b->height - 1; + if (crop->c.height > b->top + b->height - crop->c.top) + crop->c.height = + b->top + b->height - crop->c.top; + + crop->c.left = (crop->c.left < b->left) ? b->left + : crop->c.left; + if (crop->c.left > b->left + b->width) + crop->c.left = b->left + b->width - 1; + if (crop->c.width > b->left - crop->c.left + b->width) + crop->c.width = + b->left - crop->c.left + b->width; + + crop->c.width -= crop->c.width % 8; + crop->c.left -= crop->c.left % 4; + cam->crop_current = crop->c; + + pr_debug(" Cropping Input to ipu size %d x %d\n", + cam->crop_current.width, + cam->crop_current.height); + ipu_csi_set_window_size(cam->crop_current.width, + cam->crop_current.height, + cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, + cam->csi); + break; + } + + /*! + * V4l2 VIDIOC_OVERLAY ioctl + */ + case VIDIOC_OVERLAY: { + int *on = arg; + pr_debug(" VIDIOC_OVERLAY on=%d\n", *on); + if (*on) { + cam->overlay_on = true; + cam->overlay_pid = current->pid; + retval = start_preview(cam); + } + if (!*on) { + retval = stop_preview(cam); + cam->overlay_on = false; + } + break; + } + + /*! + * V4l2 VIDIOC_G_FBUF ioctl + */ + case VIDIOC_G_FBUF: { + struct v4l2_framebuffer *fb = arg; + pr_debug(" case VIDIOC_G_FBUF\n"); + *fb = cam->v4l2_fb; + fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY; + break; + } + + /*! + * V4l2 VIDIOC_S_FBUF ioctl + */ + case VIDIOC_S_FBUF: { + struct v4l2_framebuffer *fb = arg; + pr_debug(" case VIDIOC_S_FBUF\n"); + cam->v4l2_fb = *fb; + break; + } + + case VIDIOC_G_PARM: { + struct v4l2_streamparm *parm = arg; + pr_debug(" case VIDIOC_G_PARM\n"); + if (cam->sensor) + retval = vidioc_int_g_parm(cam->sensor, parm); + else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + retval = -ENODEV; + } + break; + } + + case VIDIOC_S_PARM: { + struct v4l2_streamparm *parm = arg; + pr_debug(" case VIDIOC_S_PARM\n"); + if (cam->sensor) + retval = mxc_v4l2_s_param(cam, parm); + else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + retval = -ENODEV; + } + break; + } + + /* linux v4l2 bug, kernel c0485619 user c0405619 */ + case VIDIOC_ENUMSTD: { + struct v4l2_standard *e = arg; + pr_debug(" case VIDIOC_ENUMSTD\n"); + *e = cam->standard; + break; + } + + case VIDIOC_G_STD: { + v4l2_std_id *e = arg; + pr_debug(" case VIDIOC_G_STD\n"); + if (cam->sensor) + retval = mxc_v4l2_g_std(cam, e); + else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + retval = -ENODEV; + } + break; + } + + case VIDIOC_S_STD: { + v4l2_std_id *e = arg; + pr_debug(" case VIDIOC_S_STD\n"); + retval = mxc_v4l2_s_std(cam, *e); + + break; + } + + case VIDIOC_ENUMOUTPUT: { + struct v4l2_output *output = arg; + pr_debug(" case VIDIOC_ENUMOUTPUT\n"); + if (output->index >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) { + retval = -EINVAL; + break; + } + *output = mxc_capture_outputs[output->index]; + + break; + } + case VIDIOC_G_OUTPUT: { + int *p_output_num = arg; + pr_debug(" case VIDIOC_G_OUTPUT\n"); + *p_output_num = cam->output; + break; + } + + case VIDIOC_S_OUTPUT: { + int *p_output_num = arg; + pr_debug(" case VIDIOC_S_OUTPUT\n"); + if (*p_output_num >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) { + retval = -EINVAL; + break; + } + cam->output = *p_output_num; + break; + } + + case VIDIOC_ENUMINPUT: { + struct v4l2_input *input = arg; + pr_debug(" case VIDIOC_ENUMINPUT\n"); + if (input->index >= MXC_V4L2_CAPTURE_NUM_INPUTS) { + retval = -EINVAL; + break; + } + *input = mxc_capture_inputs[input->index]; + break; + } + + case VIDIOC_G_INPUT: { + int *index = arg; + pr_debug(" case VIDIOC_G_INPUT\n"); + *index = cam->current_input; + break; + } + + case VIDIOC_S_INPUT: { + int *index = arg; + pr_debug(" case VIDIOC_S_INPUT\n"); + if (*index >= MXC_V4L2_CAPTURE_NUM_INPUTS) { + retval = -EINVAL; + break; + } + + if (*index == cam->current_input) + break; + + if ((mxc_capture_inputs[cam->current_input].status & + V4L2_IN_ST_NO_POWER) == 0) { + retval = mxc_streamoff(cam); + if (retval) + break; + mxc_capture_inputs[cam->current_input].status |= + V4L2_IN_ST_NO_POWER; + } + + if (strcmp(mxc_capture_inputs[*index].name, "CSI MEM") == 0) { +#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE) + retval = csi_enc_select(cam); + if (retval) + break; +#endif + } else if (strcmp(mxc_capture_inputs[*index].name, + "CSI IC MEM") == 0) { +#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) + retval = prp_enc_select(cam); + if (retval) + break; +#endif + } + + mxc_capture_inputs[*index].status &= ~V4L2_IN_ST_NO_POWER; + cam->current_input = *index; + break; + } + case VIDIOC_ENUM_FMT: { + struct v4l2_fmtdesc *f = arg; + if (cam->sensor) + retval = vidioc_int_enum_fmt_cap(cam->sensor, f); + else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + retval = -ENODEV; + } + break; + } + case VIDIOC_ENUM_FRAMESIZES: { + struct v4l2_frmsizeenum *fsize = arg; + if (cam->sensor) + retval = vidioc_int_enum_framesizes(cam->sensor, fsize); + else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + retval = -ENODEV; + } + break; + } + case VIDIOC_DBG_G_CHIP_IDENT: { + struct v4l2_dbg_chip_ident *p = arg; + p->ident = V4L2_IDENT_NONE; + p->revision = 0; + if (cam->sensor) + retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p); + else { + pr_err("ERROR: v4l2 capture: slave not found!\n"); + retval = -ENODEV; + } + break; + } + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + default: + pr_debug(" case default or not supported\n"); + retval = -EINVAL; + break; + } + + up(&cam->busy_lock); + return retval; +} + +/* + * V4L interface - ioctl function + * + * @return None + */ +static long mxc_v4l_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + pr_debug("In MVC:mxc_v4l_ioctl\n"); + return video_usercopy(file, cmd, arg, mxc_v4l_do_ioctl); +} + +/*! + * V4L interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error + */ +static int mxc_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *dev = video_devdata(file); + unsigned long size; + int res = 0; + cam_data *cam = video_get_drvdata(dev); + + pr_debug("In MVC:mxc_mmap\n"); + pr_debug(" pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + size = vma->vm_end - vma->vm_start; + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + pr_err("ERROR: v4l2 capture: mxc_mmap: " + "remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + + mxc_mmap_exit: + up(&cam->busy_lock); + return res; +} + +/*! + * V4L interface - poll function + * + * @param file structure file * + * + * @param wait structure poll_table_struct * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_poll(struct file *file, struct poll_table_struct *wait) +{ + struct video_device *dev = video_devdata(file); + cam_data *cam = video_get_drvdata(dev); + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + pr_debug("In MVC:mxc_poll\n"); + + if (down_interruptible(&cam->busy_lock)) + return -EINTR; + + queue = &cam->enc_queue; + poll_wait(file, queue, wait); + + up(&cam->busy_lock); + + return res; +} + +/*! + * This structure defines the functions to be called in this driver. + */ +static struct v4l2_file_operations mxc_v4l_fops = { + .owner = THIS_MODULE, + .open = mxc_v4l_open, + .release = mxc_v4l_close, + .read = mxc_v4l_read, + .ioctl = mxc_v4l_ioctl, + .mmap = mxc_mmap, + .poll = mxc_poll, +}; + +static struct video_device mxc_v4l_template = { + .name = "Mxc Camera", + .fops = &mxc_v4l_fops, + .release = video_device_release, +}; + +/*! + * This function can be used to release any platform data on closing. + */ +static void camera_platform_release(struct device *device) +{ +} + +/*! + * Camera V4l2 callback function. + * + * @param mask u32 + * + * @param dev void device structure + * + * @return status + */ +static void camera_callback(u32 mask, void *dev) +{ + struct mxc_v4l_frame *done_frame; + struct mxc_v4l_frame *ready_frame; + struct timeval cur_time; + + cam_data *cam = (cam_data *) dev; + if (cam == NULL) + return; + + pr_debug("In MVC:camera_callback\n"); + + if (!list_empty(&cam->working_q)) { + do_gettimeofday(&cur_time); + + done_frame = list_entry(cam->working_q.next, + struct mxc_v4l_frame, + queue); + + if (done_frame->ipu_buf_num != local_buf_num) + goto next; + + /* + * Set the current time to done frame buffer's + * timestamp. Users can use this information to judge + * the frame's usage. + */ + done_frame->buffer.timestamp = cur_time; + + if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { + done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE; + done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; + + /* Added to the done queue */ + list_del(cam->working_q.next); + list_add_tail(&done_frame->queue, &cam->done_q); + + /* Wake up the queue */ + cam->enc_counter++; + wake_up_interruptible(&cam->enc_queue); + } else + pr_err("ERROR: v4l2 capture: camera_callback: " + "buffer not queued\n"); + } + +next: + if (!list_empty(&cam->ready_q)) { + ready_frame = list_entry(cam->ready_q.next, + struct mxc_v4l_frame, + queue); + if (cam->enc_update_eba) + if (cam->enc_update_eba(ready_frame->buffer.m.offset, + &cam->ping_pong_csi) == 0) { + list_del(cam->ready_q.next); + list_add_tail(&ready_frame->queue, + &cam->working_q); + ready_frame->ipu_buf_num = local_buf_num; + } + } else { + if (cam->enc_update_eba) + cam->enc_update_eba( + cam->dummy_frame.buffer.m.offset, + &cam->ping_pong_csi); + } + + local_buf_num = (local_buf_num == 0) ? 1 : 0; + + return; +} + +/*! + * initialize cam_data structure + * + * @param cam structure cam_data * + * + * @return status 0 Success + */ +static void init_camera_struct(cam_data *cam, struct platform_device *pdev) +{ + pr_debug("In MVC: init_camera_struct\n"); + + /* Default everything to 0 */ + memset(cam, 0, sizeof(cam_data)); + + init_MUTEX(&cam->param_lock); + init_MUTEX(&cam->busy_lock); + + cam->video_dev = video_device_alloc(); + if (cam->video_dev == NULL) + return; + + *(cam->video_dev) = mxc_v4l_template; + + video_set_drvdata(cam->video_dev, cam); + dev_set_drvdata(&pdev->dev, (void *)cam); + cam->video_dev->minor = -1; + + init_waitqueue_head(&cam->enc_queue); + init_waitqueue_head(&cam->still_queue); + + /* setup cropping */ + cam->crop_bounds.left = 0; + cam->crop_bounds.width = 640; + cam->crop_bounds.top = 0; + cam->crop_bounds.height = 480; + cam->crop_current = cam->crop_defrect = cam->crop_bounds; + ipu_csi_set_window_size(cam->crop_current.width, + cam->crop_current.height, cam->csi); + ipu_csi_set_window_pos(cam->crop_current.left, + cam->crop_current.top, cam->csi); + cam->streamparm.parm.capture.capturemode = 0; + + cam->standard.index = 0; + cam->standard.id = V4L2_STD_UNKNOWN; + cam->standard.frameperiod.denominator = 30; + cam->standard.frameperiod.numerator = 1; + cam->standard.framelines = 480; + cam->standard_autodetect = true; + cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod; + cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + cam->overlay_on = false; + cam->capture_on = false; + cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY; + + cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2; + cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2; + cam->v2f.fmt.pix.width = 288; + cam->v2f.fmt.pix.height = 352; + cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420; + cam->win.w.width = 160; + cam->win.w.height = 160; + cam->win.w.left = 0; + cam->win.w.top = 0; + + cam->csi = 0; /* Need to determine how to set this correctly with + * multiple video input devices. */ + + cam->enc_callback = camera_callback; + init_waitqueue_head(&cam->power_queue); + spin_lock_init(&cam->queue_int_lock); + spin_lock_init(&cam->dqueue_int_lock); +} + +static ssize_t show_streaming(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct video_device *video_dev = container_of(dev, + struct video_device, dev); + cam_data *g_cam = video_get_drvdata(video_dev); + + if (g_cam->capture_on) + return sprintf(buf, "stream on\n"); + else + return sprintf(buf, "stream off\n"); +} +static DEVICE_ATTR(fsl_v4l2_capture_property, S_IRUGO, show_streaming, NULL); + +static ssize_t show_overlay(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct video_device *video_dev = container_of(dev, + struct video_device, dev); + cam_data *g_cam = video_get_drvdata(video_dev); + + if (g_cam->overlay_on) + return sprintf(buf, "overlay on\n"); + else + return sprintf(buf, "overlay off\n"); +} +static DEVICE_ATTR(fsl_v4l2_overlay_property, S_IRUGO, show_overlay, NULL); + +/*! + * This function is called to probe the devices if registered. + * + * @param pdev the device structure used to give information on which device + * to probe + * + * @return The function returns 0 on success and -1 on failure. + */ +static int mxc_v4l2_probe(struct platform_device *pdev) +{ + /* Create g_cam and initialize it. */ + g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL); + if (g_cam == NULL) { + pr_err("ERROR: v4l2 capture: failed to register camera\n"); + return -1; + } + init_camera_struct(g_cam, pdev); + pdev->dev.release = camera_platform_release; + + /* Set up the v4l2 device and register it*/ + mxc_v4l2_int_device.priv = g_cam; + /* This function contains a bug that won't let this be rmmod'd. */ + v4l2_int_device_register(&mxc_v4l2_int_device); + + /* register v4l video device */ + if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr) + == -1) { + kfree(g_cam); + g_cam = NULL; + pr_err("ERROR: v4l2 capture: video_register_device failed\n"); + return -1; + } + pr_debug(" Video device registered: %s #%d\n", + g_cam->video_dev->name, g_cam->video_dev->minor); + + if (device_create_file(&g_cam->video_dev->dev, + &dev_attr_fsl_v4l2_capture_property)) + dev_err(&pdev->dev, "Error on creating sysfs file" + " for capture\n"); + + if (device_create_file(&g_cam->video_dev->dev, + &dev_attr_fsl_v4l2_overlay_property)) + dev_err(&pdev->dev, "Error on creating sysfs file" + " for overlay\n"); + + return 0; +} + +/*! + * This function is called to remove the devices when device unregistered. + * + * @param pdev the device structure used to give information on which device + * to remove + * + * @return The function returns 0 on success and -1 on failure. + */ +static int mxc_v4l2_remove(struct platform_device *pdev) +{ + + if (g_cam->open_count) { + pr_err("ERROR: v4l2 capture:camera open " + "-- setting ops to NULL\n"); + return -EBUSY; + } else { + device_remove_file(&g_cam->video_dev->dev, + &dev_attr_fsl_v4l2_capture_property); + device_remove_file(&g_cam->video_dev->dev, + &dev_attr_fsl_v4l2_overlay_property); + + pr_info("V4L2 freeing image input device\n"); + v4l2_int_device_unregister(&mxc_v4l2_int_device); + video_unregister_device(g_cam->video_dev); + + mxc_free_frame_buf(g_cam); + kfree(g_cam); + g_cam = NULL; + } + + pr_info("V4L2 unregistering video\n"); + return 0; +} + +/*! + * This function is called to put the sensor in a low power state. + * Refer to the document driver-model/driver.txt in the kernel source tree + * for more information. + * + * @param pdev the device structure used to give information on which I2C + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure. + */ +static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state) +{ + cam_data *cam = platform_get_drvdata(pdev); + + pr_debug("In MVC:mxc_v4l2_suspend\n"); + + if (cam == NULL) { + return -1; + } + + cam->low_power = true; + + if (cam->overlay_on == true) + stop_preview(cam); + if ((cam->capture_on == true) && cam->enc_disable) { + cam->enc_disable(cam); + } + + if (cam->sensor) + vidioc_int_s_power(cam->sensor, 0); + + return 0; +} + +/*! + * This function is called to bring the sensor back from a low power state. + * Refer to the document driver-model/driver.txt in the kernel source tree + * for more information. + * + * @param pdev the device structure + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxc_v4l2_resume(struct platform_device *pdev) +{ + cam_data *cam = platform_get_drvdata(pdev); + + pr_debug("In MVC:mxc_v4l2_resume\n"); + + if (cam == NULL) { + return -1; + } + + cam->low_power = false; + wake_up_interruptible(&cam->power_queue); + + if (cam->sensor) + vidioc_int_s_power(cam->sensor, 1); + + if (cam->overlay_on == true) + start_preview(cam); + if (cam->capture_on == true) + mxc_streamon(cam); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_v4l2_driver = { + .driver = { + .name = "mxc_v4l2_capture", + }, + .probe = mxc_v4l2_probe, + .remove = mxc_v4l2_remove, + .suspend = mxc_v4l2_suspend, + .resume = mxc_v4l2_resume, + .shutdown = NULL, +}; + +/*! + * Initializes the camera driver. + */ +static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) +{ + cam_data *cam = slave->u.slave->master->priv; + struct v4l2_format cam_fmt; + + pr_debug("In MVC: mxc_v4l2_master_attach\n"); + pr_debug(" slave.name = %s\n", slave->name); + pr_debug(" master.name = %s\n", slave->u.slave->master->name); + + cam->sensor = slave; + if (slave == NULL) { + pr_err("ERROR: v4l2 capture: slave parameter not valid.\n"); + return -1; + } + + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, true, true); + vidioc_int_s_power(cam->sensor, 1); + vidioc_int_dev_init(slave); + ipu_csi_enable_mclk_if(CSI_MCLK_I2C, cam->csi, false, false); + cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); + + /* Used to detect TV in (type 1) vs. camera (type 0)*/ + cam->device_type = cam_fmt.fmt.pix.priv; + + /* Set the input size to the ipu for this device */ + cam->crop_bounds.top = cam->crop_bounds.left = 0; + cam->crop_bounds.width = cam_fmt.fmt.pix.width; + cam->crop_bounds.height = cam_fmt.fmt.pix.height; + + /* This also is the max crop size for this device. */ + cam->crop_defrect.top = cam->crop_defrect.left = 0; + cam->crop_defrect.width = cam_fmt.fmt.pix.width; + cam->crop_defrect.height = cam_fmt.fmt.pix.height; + + /* At this point, this is also the current image size. */ + cam->crop_current.top = cam->crop_current.left = 0; + cam->crop_current.width = cam_fmt.fmt.pix.width; + cam->crop_current.height = cam_fmt.fmt.pix.height; + + pr_debug("End of %s: v2f pix widthxheight %d x %d\n", + __func__, + cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); + pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", + __func__, + cam->crop_bounds.width, cam->crop_bounds.height); + pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", + __func__, + cam->crop_defrect.width, cam->crop_defrect.height); + pr_debug("End of %s: crop_current widthxheight %d x %d\n", + __func__, + cam->crop_current.width, cam->crop_current.height); + + return 0; +} + +/*! + * Disconnects the camera driver. + */ +static void mxc_v4l2_master_detach(struct v4l2_int_device *slave) +{ + pr_debug("In MVC:mxc_v4l2_master_detach\n"); + vidioc_int_dev_exit(slave); +} + +/*! + * Entry point for the V4L2 + * + * @return Error code indicating success or failure + */ +static __init int camera_init(void) +{ + u8 err = 0; + + pr_debug("In MVC:camera_init\n"); + + /* Register the device driver structure. */ + err = platform_driver_register(&mxc_v4l2_driver); + if (err != 0) { + pr_err("ERROR: v4l2 capture:camera_init: " + "platform_driver_register failed.\n"); + return err; + } + + return err; +} + +/*! + * Exit and cleanup for the V4L2 + */ +static void __exit camera_exit(void) +{ + pr_debug("In MVC: camera_exit\n"); + + platform_driver_unregister(&mxc_v4l2_driver); +} + +module_init(camera_init); +module_exit(camera_exit); + +module_param(video_nr, int, 0444); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2 capture driver for Mxc based cameras"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.h b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h new file mode 100644 index 000000000000..3f53d6029146 --- /dev/null +++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h @@ -0,0 +1,207 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup MXC_V4L2_CAPTURE MXC V4L2 Video Capture Driver + */ +/*! + * @file mxc_v4l2_capture.h + * + * @brief mxc V4L2 capture device API Header file + * + * It include all the defines for frame operations, also three structure defines + * use case ops structure, common v4l2 driver structure and frame structure. + * + * @ingroup MXC_V4L2_CAPTURE + */ +#ifndef __MXC_V4L2_CAPTURE_H__ +#define __MXC_V4L2_CAPTURE_H__ + +#include +#include +#include +#include +#include + +#include + +#define FRAME_NUM 3 + +/*! + * v4l2 frame structure. + */ +struct mxc_v4l_frame { + u32 paddress; + void *vaddress; + int count; + int width; + int height; + + struct v4l2_buffer buffer; + struct list_head queue; + int index; + int ipu_buf_num; +}; + +/* Only for old version. Will go away soon. */ +typedef struct { + u8 clk_mode; + u8 ext_vsync; + u8 Vsync_pol; + u8 Hsync_pol; + u8 pixclk_pol; + u8 data_pol; + u8 data_width; + u8 pack_tight; + u8 force_eof; + u8 data_en_pol; + u16 width; + u16 height; + u32 pixel_fmt; + u32 mclk; + u16 active_width; + u16 active_height; +} sensor_interface; + +/* Sensor control function */ +/* Only for old version. Will go away soon. */ +struct camera_sensor { + void (*set_color) (int bright, int saturation, int red, int green, + int blue); + void (*get_color) (int *bright, int *saturation, int *red, int *green, + int *blue); + void (*set_ae_mode) (int ae_mode); + void (*get_ae_mode) (int *ae_mode); + sensor_interface *(*config) (int *frame_rate, int high_quality); + sensor_interface *(*reset) (void); + void (*get_std) (v4l2_std_id *std); + void (*set_std) (v4l2_std_id std); + unsigned int csi; +}; + +/*! + * common v4l2 driver structure. + */ +typedef struct _cam_data { + struct video_device *video_dev; + int device_type; + + /* semaphore guard against SMP multithreading */ + struct semaphore busy_lock; + + int open_count; + + /* params lock for this camera */ + struct semaphore param_lock; + + /* Encoder */ + struct list_head ready_q; + struct list_head done_q; + struct list_head working_q; + int ping_pong_csi; + spinlock_t queue_int_lock; + spinlock_t dqueue_int_lock; + struct mxc_v4l_frame frame[FRAME_NUM]; + struct mxc_v4l_frame dummy_frame; + int skip_frame; + wait_queue_head_t enc_queue; + int enc_counter; + dma_addr_t rot_enc_bufs[2]; + void *rot_enc_bufs_vaddr[2]; + int rot_enc_buf_size[2]; + enum v4l2_buf_type type; + + /* still image capture */ + wait_queue_head_t still_queue; + int still_counter; + dma_addr_t still_buf[2]; + void *still_buf_vaddr; + + /* overlay */ + struct v4l2_window win; + struct v4l2_framebuffer v4l2_fb; + dma_addr_t vf_bufs[2]; + void *vf_bufs_vaddr[2]; + int vf_bufs_size[2]; + dma_addr_t rot_vf_bufs[2]; + void *rot_vf_bufs_vaddr[2]; + int rot_vf_buf_size[2]; + bool overlay_active; + int output; + struct fb_info *overlay_fb; + int fb_origin_std; + + /* v4l2 format */ + struct v4l2_format v2f; + int rotation; /* for IPUv1 and IPUv3, this means encoder rotation */ + int vf_rotation; /* viewfinder rotation only for IPUv1 and IPUv3 */ + struct v4l2_mxc_offset offset; + + /* V4l2 control bit */ + int bright; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + /* standard */ + struct v4l2_streamparm streamparm; + struct v4l2_standard standard; + bool standard_autodetect; + + /* crop */ + struct v4l2_rect crop_bounds; + struct v4l2_rect crop_defrect; + struct v4l2_rect crop_current; + + int (*enc_update_eba) (dma_addr_t eba, int *bufferNum); + int (*enc_enable) (void *private); + int (*enc_disable) (void *private); + int (*enc_enable_csi) (void *private); + int (*enc_disable_csi) (void *private); + void (*enc_callback) (u32 mask, void *dev); + int (*vf_start_adc) (void *private); + int (*vf_stop_adc) (void *private); + int (*vf_start_sdc) (void *private); + int (*vf_stop_sdc) (void *private); + int (*vf_enable_csi) (void *private); + int (*vf_disable_csi) (void *private); + int (*csi_start) (void *private); + int (*csi_stop) (void *private); + + /* misc status flag */ + bool overlay_on; + bool capture_on; + int overlay_pid; + int capture_pid; + bool low_power; + wait_queue_head_t power_queue; + unsigned int csi; + int current_input; + + /* camera sensor interface */ + struct camera_sensor *cam_sensor; /* old version */ + struct v4l2_int_device *sensor; +} cam_data; + +#if defined(CONFIG_MXC_IPU_V1) || defined(CONFIG_VIDEO_MXC_EMMA_CAMERA) \ + || defined(CONFIG_VIDEO_MXC_CSI_CAMERA_MODULE) \ + || defined(CONFIG_VIDEO_MXC_CSI_CAMERA) +void set_mclk_rate(uint32_t *p_mclk_freq); +#else +void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi); +#endif +#endif /* __MXC_V4L2_CAPTURE_H__ */ diff --git a/drivers/media/video/mxc/capture/ov2640.c b/drivers/media/video/mxc/capture/ov2640.c new file mode 100644 index 000000000000..be774c235a19 --- /dev/null +++ b/drivers/media/video/mxc/capture/ov2640.c @@ -0,0 +1,1081 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ov2640.c + * + * @brief ov2640 camera driver functions + * + * @ingroup Camera + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "mxc_v4l2_capture.h" + +#define MIN_FPS 5 +#define MAX_FPS 30 +#define DEFAULT_FPS 30 + +#define OV2640_XCLK_MIN 6000000 +#define OV2640_XCLK_MAX 27000000 + +/* +enum ov2640_mode { + ov2640_mode_1600_1120, + ov2640_mode_800_600 +}; +*/ + +struct reg_value { + u8 reg; + u8 value; + int delay_ms; +}; + +static struct reg_value ov2640_setting_1600_1120[] = { +#ifdef CONFIG_MACH_MX25_3DS + {0xff, 0x01, 0}, {0x12, 0x80, 5}, {0xff, 0x00, 0}, {0x2c, 0xff, 0}, + {0x2e, 0xdf, 0}, {0xff, 0x01, 0}, {0x3c, 0x32, 0}, {0x11, 0x00, 0}, + {0x09, 0x02, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0}, + {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0}, + {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x02, 0}, + {0x35, 0x58, 0}, {0x22, 0x0a, 0}, {0x37, 0x40, 0}, {0x23, 0x00, 0}, + {0x34, 0xa0, 0}, {0x36, 0x1a, 0}, {0x06, 0x02, 0}, {0x07, 0xc0, 0}, + {0x0d, 0xb7, 0}, {0x0e, 0x01, 0}, {0x4c, 0x00, 0}, {0x4a, 0x81, 0}, + {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0}, + {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x3f, 0}, {0x61, 0x70, 0}, + {0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0}, {0x28, 0x30, 0}, + {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 0x00, 0}, {0x70, 0x02, 0}, + {0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x3d, 0x34, 0}, {0x5a, 0x57, 0}, + {0x4f, 0xbb, 0}, {0x50, 0x9c, 0}, {0xff, 0x00, 0}, {0xe5, 0x7f, 0}, + {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0xe0, 0x14, 0}, {0x76, 0xff, 0}, + {0x33, 0xa0, 0}, {0x42, 0x20, 0}, {0x43, 0x18, 0}, {0x4c, 0x00, 0}, + {0x87, 0xd0, 0}, {0x88, 0x3f, 0}, {0xd7, 0x01, 0}, {0xd9, 0x10, 0}, + {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0}, {0x7c, 0x00, 0}, + {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0}, {0x7d, 0x48, 0}, + {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0}, {0x7d, 0x0e, 0}, + {0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0}, {0x91, 0x31, 0}, + {0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0}, {0x91, 0x7e, 0}, + {0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0}, {0x91, 0xa3, 0}, + {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0}, {0x91, 0xe8, 0}, + {0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0}, {0x93, 0xe3, 0}, + {0x93, 0x05, 0}, {0x93, 0x05, 0}, {0x93, 0x00, 0}, {0x93, 0x04, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x96, 0x00, 0}, + {0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0}, {0x97, 0x0c, 0}, + {0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0}, {0x97, 0x26, 0}, + {0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0}, {0x97, 0x00, 0}, + {0x97, 0x00, 0}, {0xc3, 0xed, 0}, {0xa4, 0x00, 0}, {0xa8, 0x00, 0}, + {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, {0xc7, 0x10, 0}, + {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, {0xb9, 0x7c, 0}, + {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, {0xb0, 0xc5, 0}, + {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, {0xc0, 0xc8, 0}, + {0xc1, 0x96, 0}, {0x86, 0x1d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0}, + {0x52, 0x2c, 0}, {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0}, + {0x57, 0x00, 0}, {0x5a, 0x90, 0}, {0x5b, 0x2c, 0}, {0x5c, 0x05, 0}, + {0xc3, 0xed, 0}, {0x7f, 0x00, 0}, {0xda, 0x00, 0}, {0xe5, 0x1f, 0}, + {0xe1, 0x77, 0}, {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0}, + {0xff, 0x00, 0}, {0xe0, 0x04, 0}, {0xc0, 0xc8, 0}, {0xc1, 0x96, 0}, + {0x86, 0x3d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0}, {0x52, 0x2c, 0}, + {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0}, {0x57, 0x00, 0}, + {0x5a, 0x40, 0}, {0x5b, 0xf0, 0}, {0x5c, 0x01, 0}, {0xd3, 0x82, 0}, + {0xe0, 0x00, 1000} +#else + {0xff, 0x1, 0}, {0x12, 0x80, 1}, {0xff, 0, 0}, {0x2c, 0xff, 0}, + {0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0}, {0x11, 0x01, 0}, + {0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0}, + {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0}, + {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x82, 0}, + {0x35, 0x88, 0}, {0x22, 0x0a, 0}, {0x37, 0x40, 0}, {0x23, 0x00, 0}, + {0x34, 0xa0, 0}, {0x36, 0x1a, 0}, {0x06, 0x02, 0}, {0x07, 0xc0, 0}, + {0x0d, 0xb7, 0}, {0x0e, 0x01, 0}, {0x4c, 0x00, 0}, {0x4a, 0x81, 0}, + {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0}, + {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x3f, 0}, {0x0c, 0x3c, 0}, + {0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0}, {0x60, 0x55, 0}, + {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0}, + {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 00, 0}, + {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x3d, 0x34, 0}, + {0x5a, 0x57, 0}, {0x4f, 0xbb, 0}, {0x50, 0x9c, 0}, {0xff, 0x00, 0}, + {0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0}, + {0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0}, + {0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0xd7, 0x03, 0}, + {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0}, + {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0}, + {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0}, + {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0}, + {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0}, + {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0}, + {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0}, + {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0}, + {0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0}, {0x93, 0x00, 0}, + {0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0}, + {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0}, + {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0}, + {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0}, {0xa8, 0x00, 0}, + {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, {0xc7, 0x10, 0}, + {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, {0xb9, 0x7c, 0}, + {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, {0xb0, 0xc5, 0}, + {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, {0xa6, 0x00, 0}, + {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0}, {0xa7, 0x31, 0}, + {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, + {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, + {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, + {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0xc8, 0}, {0xc1, 0x96, 0}, + {0x86, 0x3d, 0}, {0x50, 0x00, 0}, {0x51, 0x90, 0}, {0x52, 0x18, 0}, + {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x88, 0}, {0x57, 0x00, 0}, + {0x5a, 0x90, 0}, {0x5b, 0x18, 0}, {0x5c, 0x05, 0}, {0xc3, 0xef, 0}, + {0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0}, {0xe1, 0x67, 0}, + {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0} +#endif +}; + +static struct reg_value ov2640_setting_800_600[] = { +#ifdef CONFIG_MACH_MX25_3DS + {0xff, 0x01, 0}, {0x12, 0x80, 5}, {0xff, 0x00, 0}, {0x2c, 0xff, 0}, + {0x2e, 0xdf, 0}, {0xff, 0x01, 0}, {0x3c, 0x32, 0}, {0x11, 0x00, 0}, + {0x09, 0x02, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, {0x14, 0x48, 0}, + {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, {0x3b, 0xfb, 0}, + {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, {0x39, 0x92, 0}, + {0x35, 0xda, 0}, {0x22, 0x1a, 0}, {0x37, 0xc3, 0}, {0x23, 0x00, 0}, + {0x34, 0xc0, 0}, {0x36, 0x1a, 0}, {0x06, 0x88, 0}, {0x07, 0xc0, 0}, + {0x0d, 0x87, 0}, {0x0e, 0x41, 0}, {0x4c, 0x00, 0}, + {0x48, 0x00, 0}, {0x5b, 0x00, 0}, {0x42, 0x03, 0}, {0x4a, 0x81, 0}, + {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, {0x26, 0x82, 0}, + {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x22, 0}, {0x0c, 0x3c, 0}, + {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, {0x20, 0x80, 0}, + {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, {0x6e, 0x00, 0}, + {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, {0x12, 0x40, 0}, + {0x17, 0x11, 0}, {0x18, 0x43, 0}, {0x19, 0x00, 0}, {0x1a, 0x4b, 0}, + {0x32, 0x09, 0}, {0x37, 0xc0, 0}, {0x4f, 0xca, 0}, {0x50, 0xa8, 0}, + {0x5a, 0x23, 0}, {0x6d, 0x00, 0}, {0x3d, 0x38, 0}, {0xff, 0x00, 0}, + {0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0xe0, 0x14, 0}, + {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0}, {0x43, 0x18, 0}, + {0x4c, 0x00, 0}, {0x87, 0xd5, 0}, {0x88, 0x3f, 0}, {0xd7, 0x01, 0}, + {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, {0xc9, 0x80, 0}, + {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, {0x7d, 0x48, 0}, + {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, {0x7d, 0x10, 0}, + {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, {0x91, 0x1a, 0}, + {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, {0x91, 0x75, 0}, + {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, {0x91, 0x96, 0}, + {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, {0x91, 0xd7, 0}, + {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, {0x93, 0x06, 0}, + {0x93, 0xe3, 0}, {0x93, 0x05, 0}, {0x93, 0x05, 0}, {0x93, 0x00, 0}, + {0x93, 0x04, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, {0x97, 0x02, 0}, + {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, {0x97, 0x28, 0}, + {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, {0x97, 0x80, 0}, + {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xc3, 0xed, 0}, {0xa4, 0x00, 0}, + {0xa8, 0x00, 0}, {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, + {0xc7, 0x10, 0}, {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, + {0xb9, 0x7c, 0}, {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, + {0xb0, 0xc5, 0}, {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, + {0xc0, 0x64, 0}, {0xc1, 0x4b, 0}, {0x8c, 0x00, 0}, {0x86, 0x3d, 0}, + {0x50, 0x00, 0}, {0x51, 0xc8, 0}, {0x52, 0x96, 0}, {0x53, 0x00, 0}, + {0x54, 0x00, 0}, {0x55, 0x00, 0}, {0x5a, 0xc8, 0}, {0x5b, 0x96, 0}, + {0x5c, 0x00, 0}, {0xd3, 0x82, 0}, {0xc3, 0xed, 0}, {0x7f, 0x00, 0}, + {0xda, 0x00, 0}, {0xe5, 0x1f, 0}, {0xe1, 0x67, 0}, {0xe0, 0x00, 0}, + {0xdd, 0x7f, 0}, {0x05, 0x00, 0}, {0xff, 0x00, 0}, {0xe0, 0x04, 0}, + {0xc0, 0x64, 0}, {0xc1, 0x4b, 0}, {0x8c, 0x00, 0}, {0x86, 0x3d, 0}, + {0x50, 0x00, 0}, {0x51, 0xc8, 0}, {0x52, 0x96, 0}, {0x53, 0x00, 0}, + {0x54, 0x00, 0}, {0x55, 0x00, 0}, {0x5a, 0xa0, 0}, {0x5b, 0x78, 0}, + {0x5c, 0x00, 0}, {0xd3, 0x82, 0}, {0xe0, 0x00, 1000} +#else + {0xff, 0, 0}, {0xff, 1, 0}, {0x12, 0x80, 1}, {0xff, 00, 0}, + {0x2c, 0xff, 0}, {0x2e, 0xdf, 0}, {0xff, 0x1, 0}, {0x3c, 0x32, 0}, + {0x11, 0x01, 0}, {0x09, 0x00, 0}, {0x04, 0x28, 0}, {0x13, 0xe5, 0}, + {0x14, 0x48, 0}, {0x2c, 0x0c, 0}, {0x33, 0x78, 0}, {0x3a, 0x33, 0}, + {0x3b, 0xfb, 0}, {0x3e, 0x00, 0}, {0x43, 0x11, 0}, {0x16, 0x10, 0}, + {0x39, 0x92, 0}, {0x35, 0xda, 0}, {0x22, 0x1a, 0}, {0x37, 0xc3, 0}, + {0x23, 0x00, 0}, {0x34, 0xc0, 0}, {0x36, 0x1a, 0}, {0x06, 0x88, 0}, + {0x07, 0xc0, 0}, {0x0d, 0x87, 0}, {0x0e, 0x41, 0}, {0x4c, 0x00, 0}, + {0x4a, 0x81, 0}, {0x21, 0x99, 0}, {0x24, 0x40, 0}, {0x25, 0x38, 0}, + {0x26, 0x82, 0}, {0x5c, 0x00, 0}, {0x63, 0x00, 0}, {0x46, 0x22, 0}, + {0x0c, 0x3c, 0}, {0x5d, 0x55, 0}, {0x5e, 0x7d, 0}, {0x5f, 0x7d, 0}, + {0x60, 0x55, 0}, {0x61, 0x70, 0}, {0x62, 0x80, 0}, {0x7c, 0x05, 0}, + {0x20, 0x80, 0}, {0x28, 0x30, 0}, {0x6c, 0x00, 0}, {0x6d, 0x80, 0}, + {0x6e, 00, 0}, {0x70, 0x02, 0}, {0x71, 0x94, 0}, {0x73, 0xc1, 0}, + {0x12, 0x40, 0}, {0x17, 0x11, 0}, {0x18, 0x43, 0}, {0x19, 0x00, 0}, + {0x1a, 0x4b, 0}, {0x32, 0x09, 0}, {0x37, 0xc0, 0}, {0x4f, 0xca, 0}, + {0x50, 0xa8, 0}, {0x6d, 0x00, 0}, {0x3d, 0x38, 0}, {0xff, 0x00, 0}, + {0xe5, 0x7f, 0}, {0xf9, 0xc0, 0}, {0x41, 0x24, 0}, {0x44, 0x06, 0}, + {0xe0, 0x14, 0}, {0x76, 0xff, 0}, {0x33, 0xa0, 0}, {0x42, 0x20, 0}, + {0x43, 0x18, 0}, {0x4c, 0x00, 0}, {0x87, 0xd0, 0}, {0x88, 0x3f, 0}, + {0xd7, 0x03, 0}, {0xd9, 0x10, 0}, {0xd3, 0x82, 0}, {0xc8, 0x08, 0}, + {0xc9, 0x80, 0}, {0x7c, 0x00, 0}, {0x7d, 0x00, 0}, {0x7c, 0x03, 0}, + {0x7d, 0x48, 0}, {0x7d, 0x48, 0}, {0x7c, 0x08, 0}, {0x7d, 0x20, 0}, + {0x7d, 0x10, 0}, {0x7d, 0x0e, 0}, {0x90, 0x00, 0}, {0x91, 0x0e, 0}, + {0x91, 0x1a, 0}, {0x91, 0x31, 0}, {0x91, 0x5a, 0}, {0x91, 0x69, 0}, + {0x91, 0x75, 0}, {0x91, 0x7e, 0}, {0x91, 0x88, 0}, {0x91, 0x8f, 0}, + {0x91, 0x96, 0}, {0x91, 0xa3, 0}, {0x91, 0xaf, 0}, {0x91, 0xc4, 0}, + {0x91, 0xd7, 0}, {0x91, 0xe8, 0}, {0x91, 0x20, 0}, {0x92, 0x00, 0}, + {0x93, 0x06, 0}, {0x93, 0xe3, 0}, {0x93, 0x03, 0}, {0x93, 0x03, 0}, + {0x93, 0x00, 0}, {0x93, 0x02, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, {0x93, 0x00, 0}, + {0x93, 0x00, 0}, {0x96, 0x00, 0}, {0x97, 0x08, 0}, {0x97, 0x19, 0}, + {0x97, 0x02, 0}, {0x97, 0x0c, 0}, {0x97, 0x24, 0}, {0x97, 0x30, 0}, + {0x97, 0x28, 0}, {0x97, 0x26, 0}, {0x97, 0x02, 0}, {0x97, 0x98, 0}, + {0x97, 0x80, 0}, {0x97, 0x00, 0}, {0x97, 0x00, 0}, {0xa4, 0x00, 0}, + {0xa8, 0x00, 0}, {0xc5, 0x11, 0}, {0xc6, 0x51, 0}, {0xbf, 0x80, 0}, + {0xc7, 0x10, 0}, {0xb6, 0x66, 0}, {0xb8, 0xa5, 0}, {0xb7, 0x64, 0}, + {0xb9, 0x7c, 0}, {0xb3, 0xaf, 0}, {0xb4, 0x97, 0}, {0xb5, 0xff, 0}, + {0xb0, 0xc5, 0}, {0xb1, 0x94, 0}, {0xb2, 0x0f, 0}, {0xc4, 0x5c, 0}, + {0xa6, 0x00, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x1b, 0}, + {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, + {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, + {0xa7, 0x18, 0}, {0xa7, 0x20, 0}, {0xa7, 0xd8, 0}, {0xa7, 0x19, 0}, + {0xa7, 0x31, 0}, {0xa7, 0x00, 0}, {0xa7, 0x18, 0}, {0xc0, 0x64, 0}, + {0xc1, 0x4b, 0}, {0x86, 0x1d, 0}, {0x50, 0x00, 0}, {0x51, 0xc8, 0}, + {0x52, 0x96, 0}, {0x53, 0x00, 0}, {0x54, 0x00, 0}, {0x55, 0x00, 0}, + {0x57, 0x00, 0}, {0x5a, 0xc8, 0}, {0x5b, 0x96, 0}, {0x5c, 0x00, 0}, + {0xc3, 0xef, 0}, {0x7f, 0x00, 0}, {0xda, 0x01, 0}, {0xe5, 0x1f, 0}, + {0xe1, 0x67, 0}, {0xe0, 0x00, 0}, {0xdd, 0x7f, 0}, {0x05, 0x00, 0} +#endif +}; + +/*! + * Maintains the information on the current state of the sesor. + */ +struct sensor { + const struct ov2640_platform_data *platform_data; + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 csi; + u32 mclk; + +} ov2640_data; + +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; + +extern void gpio_sensor_active(void); +extern void gpio_sensor_inactive(void); + +/* list of image formats supported by this sensor */ +/* +const static struct v4l2_fmtdesc ov2640_formats[] = { + { + .description = "YUYV (YUV 4:2:2), packed", + .pixelformat = V4L2_PIX_FMT_UYVY, + }, +}; + */ + +static int ov2640_init_mode(struct sensor *s) +{ + int ret = -1; + struct reg_value *setting; + int i, num; + + pr_debug("In ov2640:ov2640_init_mode capturemode is %d\n", + s->streamcap.capturemode); + + if (s->streamcap.capturemode & V4L2_MODE_HIGHQUALITY) { + s->pix.width = 1600; + s->pix.height = 1120; + setting = ov2640_setting_1600_1120; + num = ARRAY_SIZE(ov2640_setting_1600_1120); + } else { + s->pix.width = 800; + s->pix.height = 600; + setting = ov2640_setting_800_600; + num = ARRAY_SIZE(ov2640_setting_800_600); + } + + for (i = 0; i < num; i++) { + ret = i2c_smbus_write_byte_data(s->i2c_client, + setting[i].reg, + setting[i].value); + if (ret < 0) { + pr_err("write reg error: reg=%x, val=%x\n", + setting[i].reg, setting[i].value); + return ret; + } + if (setting[i].delay_ms > 0) + msleep(setting[i].delay_ms); + } + + return ret; +} + +/* At present only support change to 15fps(only for SVGA mode) */ +static int ov2640_set_fps(struct sensor *s, int fps) +{ + int ret = 0; + + if (i2c_smbus_write_byte_data(s->i2c_client, 0xff, 0x01) < 0) { + pr_err("in %s,change to sensor addr failed\n", __func__); + ret = -EPERM; + } + + /* change the camera framerate to 15fps(only for SVGA mode) */ + if (i2c_smbus_write_byte_data(s->i2c_client, 0x11, 0x01) < 0) { + pr_err("change camera to 15fps failed\n"); + ret = -EPERM; + } + + return ret; +} + +static int ov2640_set_format(struct sensor *s, int format) +{ + int ret = 0; + + if (i2c_smbus_write_byte_data(s->i2c_client, 0xff, 0x00) < 0) + ret = -EPERM; + + if (format == V4L2_PIX_FMT_RGB565) { + /* set RGB565 format */ + if (i2c_smbus_write_byte_data(s->i2c_client, 0xda, 0x08) < 0) + ret = -EPERM; + + if (i2c_smbus_write_byte_data(s->i2c_client, 0xd7, 0x03) < 0) + ret = -EPERM; + } else if (format == V4L2_PIX_FMT_YUV420) { + /* set YUV420 format */ + if (i2c_smbus_write_byte_data(s->i2c_client, 0xda, 0x00) < 0) + ret = -EPERM; + + if (i2c_smbus_write_byte_data(s->i2c_client, 0xd7, 0x1b) < 0) + ret = -EPERM; + } else { + pr_debug("format not supported\n"); + } + + return ret; +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +/*! + * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num + * s: pointer to standard V4L2 device structure + * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure + * + * Gets slave interface parameters. + * Calculates the required xclk value to support the requested + * clock parameters in p. This value is returned in the p + * parameter. + * + * vidioc_int_g_ifparm returns platform-specific information about the + * interface settings used by the sensor. + * + * Given the image capture format in pix, the nominal frame period in + * timeperframe, calculate the required xclk frequency. + * + * Called on open. + */ +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + pr_debug("In ov2640:ioctl_g_ifparm\n"); + + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = ov2640_data.mclk; + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = OV2640_XCLK_MIN; + p->u.bt656.clock_max = OV2640_XCLK_MAX; + + return 0; +} + +/*! + * Sets the camera power. + * + * s pointer to the camera device + * on if 1, power is to be turned on. 0 means power is to be turned off + * + * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num + * @s: pointer to standard V4L2 device structure + * @on: power state to which device is to be set + * + * Sets devices power state to requrested state, if possible. + * This is called on open, close, suspend and resume. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + pr_debug("In ov2640:ioctl_s_power\n"); + + if (on && !sensor->on) { + gpio_sensor_active(); + if (io_regulator) + if (regulator_enable(io_regulator) != 0) + return -EIO; + if (core_regulator) + if (regulator_enable(core_regulator) != 0) + return -EIO; + if (gpo_regulator) + if (regulator_enable(gpo_regulator) != 0) + return -EIO; + if (analog_regulator) + if (regulator_enable(analog_regulator) != 0) + return -EIO; + } else if (!on && sensor->on) { + if (analog_regulator) + regulator_disable(analog_regulator); + if (core_regulator) + regulator_disable(core_regulator); + if (io_regulator) + regulator_disable(io_regulator); + if (gpo_regulator) + regulator_disable(gpo_regulator); + gpio_sensor_inactive(); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + pr_debug("In ov2640:ioctl_g_parm\n"); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_err(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \ + "but %d\n", a->type); + ret = -EINVAL; + break; + + default: + pr_err(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + int ret = 0; + + pr_debug("In ov2640:ioctl_s_parm\n"); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) + || (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + tgt_fps = timeperframe->denominator + / timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + sensor->streamcap.timeperframe = *timeperframe; + sensor->streamcap.capturemode = + (u32)a->parm.capture.capturemode; + + ret = ov2640_init_mode(sensor); + if (tgt_fps == 15) + ov2640_set_fps(sensor, tgt_fps); + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_err(" type is not V4L2_BUF_TYPE_VIDEO_CAPTURE " \ + "but %d\n", a->type); + ret = -EINVAL; + break; + + default: + pr_err(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_fmt_cap - V4L2 sensor interface handler for ioctl_s_fmt_cap + * set camera output format and resolution format + * + * @s: pointer to standard V4L2 device structure + * @arg: pointer to parameter, according this to set camera + * + * Returns 0 if set succeed, else return -1 + */ +static int ioctl_s_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + u32 format = f->fmt.pix.pixelformat; + int size = 0, ret = 0; + + size = f->fmt.pix.width * f->fmt.pix.height; + switch (format) { + case V4L2_PIX_FMT_RGB565: + if (size > 640 * 480) + sensor->streamcap.capturemode = V4L2_MODE_HIGHQUALITY; + else + sensor->streamcap.capturemode = 0; + ret = ov2640_init_mode(sensor); + + ret = ov2640_set_format(sensor, V4L2_PIX_FMT_RGB565); + break; + case V4L2_PIX_FMT_UYVY: + if (size > 640 * 480) + sensor->streamcap.capturemode = V4L2_MODE_HIGHQUALITY; + else + sensor->streamcap.capturemode = 0; + ret = ov2640_init_mode(sensor); + break; + case V4L2_PIX_FMT_YUV420: + if (size > 640 * 480) + sensor->streamcap.capturemode = V4L2_MODE_HIGHQUALITY; + else + sensor->streamcap.capturemode = 0; + ret = ov2640_init_mode(sensor); + + /* YUYV: width * 2, YY: width */ + ret = ov2640_set_format(sensor, V4L2_PIX_FMT_YUV420); + break; + default: + pr_debug("case not supported\n"); + break; + } + + return ret; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + pr_debug("In ov2640:ioctl_g_fmt_cap.\n"); + + f->fmt.pix = sensor->pix; + + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + pr_debug("In ov2640:ioctl_g_ctrl\n"); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = ov2640_data.brightness; + break; + case V4L2_CID_HUE: + vc->value = ov2640_data.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = ov2640_data.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = ov2640_data.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = ov2640_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = ov2640_data.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = ov2640_data.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In ov2640:ioctl_s_ctrl %d\n", vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + pr_debug(" V4L2_CID_BRIGHTNESS\n"); + break; + case V4L2_CID_CONTRAST: + pr_debug(" V4L2_CID_CONTRAST\n"); + break; + case V4L2_CID_SATURATION: + pr_debug(" V4L2_CID_SATURATION\n"); + break; + case V4L2_CID_HUE: + pr_debug(" V4L2_CID_HUE\n"); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + pr_debug( + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + pr_debug(" V4L2_CID_RED_BALANCE\n"); + break; + case V4L2_CID_BLUE_BALANCE: + pr_debug(" V4L2_CID_BLUE_BALANCE\n"); + break; + case V4L2_CID_GAMMA: + pr_debug(" V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + pr_debug(" V4L2_CID_EXPOSURE\n"); + break; + case V4L2_CID_AUTOGAIN: + pr_debug(" V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + pr_debug(" V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + pr_debug(" V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + pr_debug(" V4L2_CID_VFLIP\n"); + break; + default: + pr_debug(" Default case\n"); + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + pr_debug("In ov2640:ioctl_init\n"); + + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct sensor *sensor = s->priv; + u32 tgt_xclk; /* target xclk */ + + pr_debug("In ov2640:ioctl_dev_init\n"); + + gpio_sensor_active(); + ov2640_data.on = true; + + tgt_xclk = ov2640_data.mclk; + tgt_xclk = min(tgt_xclk, (u32)OV2640_XCLK_MAX); + tgt_xclk = max(tgt_xclk, (u32)OV2640_XCLK_MIN); + ov2640_data.mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", + tgt_xclk / 1000000); + set_mclk_rate(&ov2640_data.mclk); + + return ov2640_init_mode(sensor); +} + +/*! + * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num + * @s: pointer to standard V4L2 device structure + * + * Delinitialise the device when slave detaches to the master. + */ +static int ioctl_dev_exit(struct v4l2_int_device *s) +{ + pr_debug("In ov2640:ioctl_dev_exit\n"); + + gpio_sensor_inactive(); + + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc ov2640_ioctl_desc[] = { + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, + {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func*)ioctl_dev_exit}, + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init}, +/* {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */ +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, + {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_s_fmt_cap}, + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, +/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */ + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl}, +}; + +static struct v4l2_int_slave ov2640_slave = { + .ioctls = ov2640_ioctl_desc, + .num_ioctls = ARRAY_SIZE(ov2640_ioctl_desc), +}; + +static struct v4l2_int_device ov2640_int_device = { + .module = THIS_MODULE, + .name = "ov2640", + .type = v4l2_int_type_slave, + .u = { + .slave = &ov2640_slave, + }, +}; + +/*! + * ov2640 I2C attach function + * Function set in i2c_driver struct. + * Called by insmod ov2640_camera.ko. + * + * @param client struct i2c_client* + * @return Error code indicating success or failure + */ +static int ov2640_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + struct mxc_camera_platform_data *plat_data = client->dev.platform_data; + + pr_debug("In ov2640_probe (RH_BT565)\n"); + + /* Set initial values for the sensor struct. */ + memset(&ov2640_data, 0, sizeof(ov2640_data)); + ov2640_data.i2c_client = client; + ov2640_data.mclk = 24000000; + ov2640_data.mclk = plat_data->mclk; + ov2640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; + ov2640_data.pix.width = 800; + ov2640_data.pix.height = 600; + ov2640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY + | V4L2_CAP_TIMEPERFRAME; + ov2640_data.streamcap.capturemode = 0; + ov2640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; + ov2640_data.streamcap.timeperframe.numerator = 1; + + if (plat_data->io_regulator) { + io_regulator = + regulator_get(&client->dev, plat_data->io_regulator); + if (!IS_ERR(io_regulator)) { + regulator_set_voltage(io_regulator, 2800000, 2800000); + if (regulator_enable(io_regulator) != 0) { + pr_err("%s:io set voltage error\n", __func__); + goto err1; + } else { + dev_dbg(&client->dev, + "%s:io set voltage ok\n", __func__); + } + } else + io_regulator = NULL; + } + + if (plat_data->core_regulator) { + core_regulator = + regulator_get(&client->dev, plat_data->core_regulator); + if (!IS_ERR(core_regulator)) { + regulator_set_voltage(core_regulator, + 1300000, 1300000); + if (regulator_enable(core_regulator) != 0) { + pr_err("%s:core set voltage error\n", __func__); + goto err2; + } else { + dev_dbg(&client->dev, + "%s:core set voltage ok\n", __func__); + } + } else + core_regulator = NULL; + } + + if (plat_data->analog_regulator) { + analog_regulator = + regulator_get(&client->dev, plat_data->analog_regulator); + if (!IS_ERR(analog_regulator)) { + regulator_set_voltage(analog_regulator, 2000000, 2000000); + if (regulator_enable(analog_regulator) != 0) { + pr_err("%s:analog set voltage error\n", + __func__); + goto err3; + } else { + dev_dbg(&client->dev, + "%s:analog set voltage ok\n", __func__); + } + } else + analog_regulator = NULL; + } + + if (plat_data->gpo_regulator) { + gpo_regulator = + regulator_get(&client->dev, plat_data->gpo_regulator); + if (!IS_ERR(gpo_regulator)) { + if (regulator_enable(gpo_regulator) != 0) { + pr_err("%s:gpo3 set voltage error\n", __func__); + goto err4; + } else { + dev_dbg(&client->dev, + "%s:gpo3 set voltage ok\n", __func__); + } + } else + gpo_regulator = NULL; + } + + /* This function attaches this structure to the /dev/video0 device. + * The pointer in priv points to the ov2640_data structure here.*/ + ov2640_int_device.priv = &ov2640_data; + retval = v4l2_int_device_register(&ov2640_int_device); + + return retval; + +err4: + if (analog_regulator) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator); + } +err3: + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } +err2: + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } +err1: + return -1; +} + +/*! + * ov2640 I2C detach function + * Called on rmmod ov2640_camera.ko + * + * @param client struct i2c_client* + * @return Error code indicating success or failure + */ +static int ov2640_remove(struct i2c_client *client) +{ + pr_debug("In ov2640_remove\n"); + + v4l2_int_device_unregister(&ov2640_int_device); + + if (gpo_regulator) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator); + } + + if (analog_regulator) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator); + } + + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } + + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } + + return 0; +} + +static const struct i2c_device_id ov2640_id[] = { + {"ov2640", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov2640_id); + +static struct i2c_driver ov2640_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov2640", + }, + .probe = ov2640_probe, + .remove = ov2640_remove, + .id_table = ov2640_id, +/* To add power management add .suspend and .resume functions */ +}; + +/*! + * ov2640 init function + * Called by insmod ov2640_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int ov2640_init(void) +{ + u8 err; + + pr_debug("In ov2640_init\n"); + + err = i2c_add_driver(&ov2640_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * OV2640 cleanup function + * Called on rmmod ov2640_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit ov2640_clean(void) +{ + pr_debug("In ov2640_clean\n"); + i2c_del_driver(&ov2640_i2c_driver); +} + +module_init(ov2640_init); +module_exit(ov2640_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OV2640 Camera Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/capture/ov3640.c b/drivers/media/video/mxc/capture/ov3640.c new file mode 100644 index 000000000000..0613ea28508c --- /dev/null +++ b/drivers/media/video/mxc/capture/ov3640.c @@ -0,0 +1,1499 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" + +#define OV3640_VOLTAGE_ANALOG 2800000 +#define OV3640_VOLTAGE_DIGITAL_CORE 1500000 +#define OV3640_VOLTAGE_DIGITAL_IO 1800000 +#define OV3640_VOLTAGE_DIGITAL_GPO 2800000 + +#define MIN_FPS 15 +#define MAX_FPS 30 +#define DEFAULT_FPS 30 + +#define OV3640_XCLK_MIN 6000000 +#define OV3640_XCLK_MAX 24000000 + +enum ov3640_mode { + ov3640_mode_MIN = 0, + ov3640_mode_VGA_640_480 = 0, + ov3640_mode_QVGA_320_240 = 1, + ov3640_mode_XGA_1024_768 = 2, + ov3640_mode_QXGA_2048_1536 = 3, + ov3640_mode_NTSC_720_480 = 4, + ov3640_mode_PAL_720_576 = 5, + ov3640_mode_MAX = 5 +}; + +enum ov3640_frame_rate { + ov3640_15_fps, + ov3640_30_fps +}; + +struct reg_value { + u16 u16RegAddr; + u8 u8Val; + u8 u8Mask; + u32 u32Delay_ms; +}; + +struct ov3640_mode_info { + enum ov3640_mode mode; + u32 width; + u32 height; + struct reg_value *init_data_ptr; + u32 init_data_size; +}; + +/*! + * Maintains the information on the current state of the sesor. + */ +struct sensor { + const struct ov3640_platform_data *platform_data; + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 mclk; + int csi; +} ov3640_data; + +static struct reg_value ov3640_setting_15fps_QXGA_2048_1536[] = { +#if 0 + /* The true 15fps QXGA setting. */ + {0x3012, 0x80, 0, 0}, {0x304d, 0x41, 0, 0}, {0x3087, 0x16, 0, 0}, + {0x30aa, 0x45, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x13, 0, 0}, {0x30d7, 0x10, 0, 0}, {0x309e, 0x00, 0, 0}, + {0x3602, 0x26, 0, 0}, {0x3603, 0x4D, 0, 0}, {0x364c, 0x04, 0, 0}, + {0x360c, 0x12, 0, 0}, {0x361e, 0x00, 0, 0}, {0x361f, 0x11, 0, 0}, + {0x3633, 0x03, 0, 0}, {0x3629, 0x3c, 0, 0}, {0x300e, 0x33, 0, 0}, + {0x300f, 0x21, 0, 0}, {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, + {0x304c, 0x81, 0, 0}, {0x3029, 0x47, 0, 0}, {0x3070, 0x00, 0, 0}, + {0x3071, 0xEC, 0, 0}, {0x301C, 0x06, 0, 0}, {0x3072, 0x00, 0, 0}, + {0x3073, 0xC5, 0, 0}, {0x301D, 0x07, 0, 0}, {0x3018, 0x38, 0, 0}, + {0x3019, 0x30, 0, 0}, {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, + {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, {0x303c, 0x08, 0, 0}, + {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0}, {0x303F, 0x0c, 0, 0}, + {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, + {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, + {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0}, {0x3015, 0x12, 0, 0}, + {0x3014, 0x04, 0, 0}, {0x3013, 0xf7, 0, 0}, {0x3104, 0x02, 0, 0}, + {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, + {0x3308, 0xa5, 0, 0}, {0x3316, 0xff, 0, 0}, {0x3317, 0x00, 0, 0}, + {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, {0x3300, 0x13, 0, 0}, + {0x3301, 0xd6, 0, 0}, {0x3302, 0xef, 0, 0}, {0x30b8, 0x20, 0, 0}, + {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3304, 0x00, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x02, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, + {0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, + {0x3025, 0x18, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x0c, 0, 0}, + {0x335f, 0x68, 0, 0}, {0x3360, 0x18, 0, 0}, {0x3361, 0x0c, 0, 0}, + {0x3362, 0x68, 0, 0}, {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, + {0x3403, 0x42, 0, 0}, {0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0}, + {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, {0x3507, 0x06, 0, 0}, + {0x350a, 0x4f, 0, 0}, {0x3600, 0xc4, 0, 0}, +#endif + /* + * Only support 7.5fps for QXGA to workaround screen tearing issue + * for 15fps when capturing still image. + */ + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, + {0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0}, + {0x3400, 0x00, 0, 0}, {0x3404, 0x02, 0, 0}, {0x3600, 0xc4, 0, 0}, + {0x3088, 0x08, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, + {0x308b, 0x00, 0, 0}, {0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, + {0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0}, +}; + +static struct reg_value ov3640_setting_15fps_XGA_1024_768[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, + {0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0}, + {0x3400, 0x01, 0, 0}, {0x3404, 0x1d, 0, 0}, {0x3600, 0xc4, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, + {0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, + {0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0}, + {0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0}, + {0x3362, 0x34, 0, 0}, {0x3363, 0x00, 0, 0}, {0x3364, 0x00, 0, 0}, + {0x3403, 0x00, 0, 0}, {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, + {0x308a, 0x03, 0, 0}, {0x308b, 0x00, 0, 0}, {0x307c, 0x10, 0, 0}, + {0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0}, +}; + +static struct reg_value ov3640_setting_30fps_XGA_1024_768[] = { + {0x0, 0x0, 0} +}; + +static struct reg_value ov3640_setting_15fps_VGA_640_480[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, + {0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0}, + {0x3400, 0x00, 0, 0}, {0x3404, 0x42, 0, 0}, {0x3600, 0xc4, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, + {0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, + {0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0}, + {0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0}, + {0x3362, 0x12, 0, 0}, {0x3363, 0x80, 0, 0}, {0x3364, 0xe0, 0, 0}, + {0x3403, 0x00, 0, 0}, {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, + {0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0}, {0x307c, 0x10, 0, 0}, + {0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x00, 0, 0}, +}; + +static struct reg_value ov3640_setting_30fps_VGA_640_480[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x0c, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x3300, 0x13, 0, 0}, {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, + {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0x10, 0x30, 0}, {0x3304, 0x00, 0x03, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x02, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3012, 0x10, 0, 0}, + {0x3023, 0x06, 0, 0}, {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, + {0x302a, 0x03, 0, 0}, {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, + {0x300d, 0x01, 0, 0}, {0x30d7, 0x80, 0x80, 0}, {0x3069, 0x00, 0x40, 0}, + {0x303e, 0x00, 0, 0}, {0x303f, 0xc0, 0, 0}, {0x3302, 0x20, 0x20, 0}, + {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, + {0x3362, 0x12, 0, 0}, {0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0}, + {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, + {0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0}, {0x3362, 0x12, 0, 0}, + {0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, {0x308a, 0x01, 0, 0}, + {0x308b, 0xe0, 0, 0}, {0x300e, 0x37, 0, 0}, {0x300f, 0xe1, 0, 0}, + {0x3010, 0x22, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x84, 0, 0}, + {0x3014, 0x04, 0, 0}, {0x3015, 0x02, 0, 0}, {0x302e, 0x00, 0, 0}, + {0x302d, 0x00, 0, 0}, +}; + +static struct reg_value ov3640_setting_15fps_QVGA_320_240[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x00, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x04, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, + {0x30bb, 0x08, 0, 0}, {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, + {0x3100, 0x02, 0, 0}, {0x3301, 0xde, 0, 0}, {0x3304, 0x00, 0, 0}, + {0x3400, 0x00, 0, 0}, {0x3404, 0x42, 0, 0}, {0x3600, 0xc4, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x3020, 0x01, 0, 0}, {0x3021, 0x1d, 0, 0}, + {0x3022, 0x00, 0, 0}, {0x3023, 0x0a, 0, 0}, {0x3024, 0x08, 0, 0}, + {0x3025, 0x00, 0, 0}, {0x3026, 0x06, 0, 0}, {0x3027, 0x00, 0, 0}, + {0x335f, 0x68, 0, 0}, {0x3360, 0x00, 0, 0}, {0x3361, 0x00, 0, 0}, + {0x3362, 0x01, 0, 0}, {0x3363, 0x40, 0, 0}, {0x3364, 0xf0, 0, 0}, + {0x3403, 0x00, 0, 0}, {0x3088, 0x01, 0, 0}, {0x3089, 0x40, 0, 0}, + {0x308a, 0x00, 0, 0}, {0x308b, 0xf0, 0, 0}, {0x307c, 0x10, 0, 0}, + {0x3090, 0xc0, 0, 0}, {0x304c, 0x84, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3011, 0x01, 0, 0}, +}; + +static struct reg_value ov3640_setting_30fps_QVGA_320_240[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309c, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0}, + {0x30d7, 0x10, 0, 0}, {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, + {0x3016, 0x82, 0, 0}, {0x3018, 0x38, 0, 0}, {0x3019, 0x30, 0, 0}, + {0x301a, 0x61, 0, 0}, {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, + {0x3082, 0x20, 0, 0}, {0x3015, 0x12, 0, 0}, {0x3014, 0x0c, 0, 0}, + {0x3013, 0xf7, 0, 0}, {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, + {0x303e, 0x06, 0, 0}, {0x303f, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, + {0x3031, 0x26, 0, 0}, {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, + {0x3034, 0xea, 0, 0}, {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, + {0x3037, 0x6a, 0, 0}, {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, + {0x3106, 0x00, 0, 0}, {0x3107, 0xff, 0, 0}, {0x3300, 0x12, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, + {0x3314, 0x42, 0, 0}, {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, + {0x3310, 0xd0, 0, 0}, {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, + {0x330d, 0x18, 0, 0}, {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, + {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, + {0x336a, 0x52, 0, 0}, {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, + {0x3300, 0x13, 0, 0}, {0x30b8, 0x20, 0, 0}, {0x30b9, 0x17, 0, 0}, + {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0x10, 0x30, 0}, {0x3304, 0x00, 0x03, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x02, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x308d, 0x04, 0, 0}, + {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, {0x3012, 0x10, 0, 0}, + {0x3023, 0x06, 0, 0}, {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, + {0x302a, 0x03, 0, 0}, {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, + {0x300d, 0x01, 0, 0}, {0x30d7, 0x80, 0x80, 0}, {0x3069, 0x00, 0x40, 0}, + {0x303e, 0x00, 0, 0}, {0x303f, 0xc0, 0, 0}, {0x3302, 0x20, 0x20, 0}, + {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, + {0x3362, 0x34, 0, 0}, {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, + {0x3403, 0x42, 0, 0}, {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, + {0x308a, 0x03, 0, 0}, {0x308b, 0x00, 0, 0}, {0x3362, 0x12, 0, 0}, + {0x3363, 0x88, 0, 0}, {0x3364, 0xe4, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x02, 0, 0}, {0x3089, 0x80, 0, 0}, {0x308a, 0x01, 0, 0}, + {0x308b, 0xe0, 0, 0}, {0x300e, 0x37, 0, 0}, {0x300f, 0xe1, 0, 0}, + {0x3010, 0x22, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x84, 0, 0}, +}; + +static struct reg_value ov3640_setting_15fps_NTSC_720_480[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309C, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x304c, 0x81, 0, 0}, {0x30d7, 0x10, 0, 0}, + {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, {0x3016, 0x82, 0, 0}, + {0x3018, 0x48, 0, 0}, {0x3019, 0x40, 0, 0}, {0x301a, 0x82, 0, 0}, + {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, + {0x3015, 0x12, 0, 0}, {0x3014, 0x84, 0, 0}, {0x3013, 0xf7, 0, 0}, + {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0}, + {0x303F, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0}, + {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0}, + {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0}, + {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0}, + {0x3107, 0xff, 0, 0}, {0x3300, 0x13, 0, 0}, {0x3301, 0xde, 0, 0}, + {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, {0x3314, 0x42, 0, 0}, + {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, {0x3310, 0xd0, 0, 0}, + {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, + {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, {0x330b, 0x1c, 0, 0}, + {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, {0x336a, 0x52, 0, 0}, + {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, {0x30b8, 0x20, 0, 0}, + {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, + {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x00, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x3088, 0x08, 0, 0}, + {0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, + {0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, + {0x30a9, 0xb5, 0, 0}, {0x3317, 0x04, 0, 0}, {0x3316, 0xf8, 0, 0}, + {0x3312, 0x17, 0, 0}, {0x3314, 0x30, 0, 0}, {0x3313, 0x23, 0, 0}, + {0x3315, 0x3e, 0, 0}, {0x3311, 0x9e, 0, 0}, {0x3310, 0xc0, 0, 0}, + {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, {0x330e, 0x5e, 0, 0}, + {0x330f, 0x6c, 0, 0}, {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, + {0x3307, 0x11, 0, 0}, {0x3308, 0x25, 0, 0}, {0x3340, 0x20, 0, 0}, + {0x3341, 0x50, 0, 0}, {0x3342, 0x18, 0, 0}, {0x3343, 0x23, 0, 0}, + {0x3344, 0xad, 0, 0}, {0x3345, 0xd0, 0, 0}, {0x3346, 0xb8, 0, 0}, + {0x3347, 0xb4, 0, 0}, {0x3348, 0x04, 0, 0}, {0x3349, 0x98, 0, 0}, + {0x3355, 0x02, 0, 0}, {0x3358, 0x44, 0, 0}, {0x3359, 0x44, 0, 0}, + {0x3300, 0x13, 0, 0}, {0x3367, 0x23, 0, 0}, {0x3368, 0xBB, 0, 0}, + {0x3369, 0xD6, 0, 0}, {0x336A, 0x2A, 0, 0}, {0x336B, 0x07, 0, 0}, + {0x336C, 0x00, 0, 0}, {0x336D, 0x23, 0, 0}, {0x336E, 0xC3, 0, 0}, + {0x336F, 0xDE, 0, 0}, {0x3370, 0x2b, 0, 0}, {0x3371, 0x07, 0, 0}, + {0x3372, 0x00, 0, 0}, {0x3373, 0x23, 0, 0}, {0x3374, 0x9e, 0, 0}, + {0x3375, 0xD6, 0, 0}, {0x3376, 0x29, 0, 0}, {0x3377, 0x07, 0, 0}, + {0x3378, 0x00, 0, 0}, {0x332a, 0x1d, 0, 0}, {0x331b, 0x08, 0, 0}, + {0x331c, 0x16, 0, 0}, {0x331d, 0x2d, 0, 0}, {0x331e, 0x54, 0, 0}, + {0x331f, 0x66, 0, 0}, {0x3320, 0x73, 0, 0}, {0x3321, 0x80, 0, 0}, + {0x3322, 0x8c, 0, 0}, {0x3323, 0x95, 0, 0}, {0x3324, 0x9d, 0, 0}, + {0x3325, 0xac, 0, 0}, {0x3326, 0xb8, 0, 0}, {0x3327, 0xcc, 0, 0}, + {0x3328, 0xdd, 0, 0}, {0x3329, 0xee, 0, 0}, {0x332e, 0x04, 0, 0}, + {0x332f, 0x04, 0, 0}, {0x3331, 0x02, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x00, 0, 0}, {0x3610, 0x40, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x307C, 0x10, 0, 0}, {0x3012, 0x10, 0, 0}, {0x3023, 0x06, 0, 0}, + {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, {0x302a, 0x03, 0, 0}, + {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, {0x300d, 0x01, 0, 0}, + {0x30d7, 0x90, 0, 0}, {0x3069, 0x04, 0, 0}, {0x303e, 0x00, 0, 0}, + {0x303f, 0xc0, 0, 0}, {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, + {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, {0x3362, 0x34, 0, 0}, + {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x03, 0, 0}, + {0x308b, 0x00, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, + {0x3361, 0x04, 0, 0}, {0x3362, 0x23, 0, 0}, {0x3363, 0x28, 0, 0}, + {0x3364, 0x5c, 0, 0}, {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0}, + {0x3089, 0xD0, 0, 0}, {0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0}, + {0x304c, 0x83, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3011, 0x00, 0, 0}, {0x3010, 0x81, 0, 0}, {0x302e, 0x00, 0, 0}, + {0x302d, 0x00, 0, 0}, {0x3071, 0xeb, 0, 0}, {0x301C, 0x02, 0, 0}, + {0x3404, 0x02, 0, 0}, +}; + +static struct reg_value ov3640_setting_15fps_PAL_720_576[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309C, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x304c, 0x81, 0, 0}, {0x30d7, 0x10, 0, 0}, + {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, {0x3016, 0x82, 0, 0}, + {0x3018, 0x48, 0, 0}, {0x3019, 0x40, 0, 0}, {0x301a, 0x82, 0, 0}, + {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, + {0x3015, 0x12, 0, 0}, {0x3014, 0x84, 0, 0}, {0x3013, 0xf7, 0, 0}, + {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0}, + {0x303F, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0}, + {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0}, + {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0}, + {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0}, + {0x3107, 0xff, 0, 0}, {0x3300, 0x13, 0, 0}, {0x3301, 0xde, 0, 0}, + {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, {0x3314, 0x42, 0, 0}, + {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, {0x3310, 0xd0, 0, 0}, + {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, + {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, {0x330b, 0x1c, 0, 0}, + {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, {0x336a, 0x52, 0, 0}, + {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, {0x30b8, 0x20, 0, 0}, + {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, + {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x00, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x3088, 0x08, 0, 0}, + {0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, + {0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, + {0x30a9, 0xb5, 0, 0}, {0x3317, 0x04, 0, 0}, {0x3316, 0xf8, 0, 0}, + {0x3312, 0x17, 0, 0}, {0x3314, 0x30, 0, 0}, {0x3313, 0x23, 0, 0}, + {0x3315, 0x3e, 0, 0}, {0x3311, 0x9e, 0, 0}, {0x3310, 0xc0, 0, 0}, + {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, {0x330e, 0x5e, 0, 0}, + {0x330f, 0x6c, 0, 0}, {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, + {0x3307, 0x11, 0, 0}, {0x3308, 0x25, 0, 0}, {0x3340, 0x20, 0, 0}, + {0x3341, 0x50, 0, 0}, {0x3342, 0x18, 0, 0}, {0x3343, 0x23, 0, 0}, + {0x3344, 0xad, 0, 0}, {0x3345, 0xd0, 0, 0}, {0x3346, 0xb8, 0, 0}, + {0x3347, 0xb4, 0, 0}, {0x3348, 0x04, 0, 0}, {0x3349, 0x98, 0, 0}, + {0x3355, 0x02, 0, 0}, {0x3358, 0x44, 0, 0}, {0x3359, 0x44, 0, 0}, + {0x3300, 0x13, 0, 0}, {0x3367, 0x23, 0, 0}, {0x3368, 0xBB, 0, 0}, + {0x3369, 0xD6, 0, 0}, {0x336A, 0x2A, 0, 0}, {0x336B, 0x07, 0, 0}, + {0x336C, 0x00, 0, 0}, {0x336D, 0x23, 0, 0}, {0x336E, 0xC3, 0, 0}, + {0x336F, 0xDE, 0, 0}, {0x3370, 0x2b, 0, 0}, {0x3371, 0x07, 0, 0}, + {0x3372, 0x00, 0, 0}, {0x3373, 0x23, 0, 0}, {0x3374, 0x9e, 0, 0}, + {0x3375, 0xD6, 0, 0}, {0x3376, 0x29, 0, 0}, {0x3377, 0x07, 0, 0}, + {0x3378, 0x00, 0, 0}, {0x332a, 0x1d, 0, 0}, {0x331b, 0x08, 0, 0}, + {0x331c, 0x16, 0, 0}, {0x331d, 0x2d, 0, 0}, {0x331e, 0x54, 0, 0}, + {0x331f, 0x66, 0, 0}, {0x3320, 0x73, 0, 0}, {0x3321, 0x80, 0, 0}, + {0x3322, 0x8c, 0, 0}, {0x3323, 0x95, 0, 0}, {0x3324, 0x9d, 0, 0}, + {0x3325, 0xac, 0, 0}, {0x3326, 0xb8, 0, 0}, {0x3327, 0xcc, 0, 0}, + {0x3328, 0xdd, 0, 0}, {0x3329, 0xee, 0, 0}, {0x332e, 0x04, 0, 0}, + {0x332f, 0x04, 0, 0}, {0x3331, 0x02, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x00, 0, 0}, {0x3610, 0x40, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x307C, 0x10, 0, 0}, {0x3012, 0x10, 0, 0}, {0x3023, 0x06, 0, 0}, + {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, {0x302a, 0x03, 0, 0}, + {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, {0x300d, 0x01, 0, 0}, + {0x30d7, 0x90, 0, 0}, {0x3069, 0x04, 0, 0}, {0x303e, 0x00, 0, 0}, + {0x303f, 0xc0, 0, 0}, {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, + {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, {0x3362, 0x34, 0, 0}, + {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x03, 0, 0}, + {0x308b, 0x00, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, + {0x3361, 0x04, 0, 0}, {0x3362, 0x23, 0, 0}, {0x3363, 0x28, 0, 0}, + {0x3364, 0x5c, 0, 0}, {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0}, + {0x3089, 0xD0, 0, 0}, {0x308a, 0x02, 0, 0}, {0x308b, 0x40, 0, 0}, + {0x304c, 0x83, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3011, 0x00, 0, 0}, {0x3010, 0x81, 0, 0}, {0x302e, 0x00, 0, 0}, + {0x302d, 0x00, 0, 0}, {0x3071, 0xeb, 0, 0}, {0x301C, 0x02, 0, 0}, + {0x3404, 0x02, 0, 0}, +}; + +static struct reg_value ov3640_setting_30fps_NTSC_720_480[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3087, 0x16, 0, 0}, {0x309C, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x304c, 0x81, 0, 0}, {0x30d7, 0x10, 0, 0}, + {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, {0x3016, 0x82, 0, 0}, + {0x3018, 0x48, 0, 0}, {0x3019, 0x40, 0, 0}, {0x301a, 0x82, 0, 0}, + {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, + {0x3015, 0x12, 0, 0}, {0x3014, 0x84, 0, 0}, {0x3013, 0xf7, 0, 0}, + {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0}, + {0x303F, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0}, + {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0}, + {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0}, + {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0}, + {0x3107, 0xff, 0, 0}, {0x3300, 0x13, 0, 0}, {0x3301, 0xde, 0, 0}, + {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, {0x3314, 0x42, 0, 0}, + {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, {0x3310, 0xd0, 0, 0}, + {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, + {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, {0x330b, 0x1c, 0, 0}, + {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, {0x336a, 0x52, 0, 0}, + {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, {0x30b8, 0x20, 0, 0}, + {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, + {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x00, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x3088, 0x08, 0, 0}, + {0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, + {0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, + {0x30a9, 0xb5, 0, 0}, {0x3317, 0x04, 0, 0}, {0x3316, 0xf8, 0, 0}, + {0x3312, 0x17, 0, 0}, {0x3314, 0x30, 0, 0}, {0x3313, 0x23, 0, 0}, + {0x3315, 0x3e, 0, 0}, {0x3311, 0x9e, 0, 0}, {0x3310, 0xc0, 0, 0}, + {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, {0x330e, 0x5e, 0, 0}, + {0x330f, 0x6c, 0, 0}, {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, + {0x3307, 0x11, 0, 0}, {0x3308, 0x25, 0, 0}, {0x3340, 0x20, 0, 0}, + {0x3341, 0x50, 0, 0}, {0x3342, 0x18, 0, 0}, {0x3343, 0x23, 0, 0}, + {0x3344, 0xad, 0, 0}, {0x3345, 0xd0, 0, 0}, {0x3346, 0xb8, 0, 0}, + {0x3347, 0xb4, 0, 0}, {0x3348, 0x04, 0, 0}, {0x3349, 0x98, 0, 0}, + {0x3355, 0x02, 0, 0}, {0x3358, 0x44, 0, 0}, {0x3359, 0x44, 0, 0}, + {0x3300, 0x13, 0, 0}, {0x3367, 0x23, 0, 0}, {0x3368, 0xBB, 0, 0}, + {0x3369, 0xD6, 0, 0}, {0x336A, 0x2A, 0, 0}, {0x336B, 0x07, 0, 0}, + {0x336C, 0x00, 0, 0}, {0x336D, 0x23, 0, 0}, {0x336E, 0xC3, 0, 0}, + {0x336F, 0xDE, 0, 0}, {0x3370, 0x2b, 0, 0}, {0x3371, 0x07, 0, 0}, + {0x3372, 0x00, 0, 0}, {0x3373, 0x23, 0, 0}, {0x3374, 0x9e, 0, 0}, + {0x3375, 0xD6, 0, 0}, {0x3376, 0x29, 0, 0}, {0x3377, 0x07, 0, 0}, + {0x3378, 0x00, 0, 0}, {0x332a, 0x1d, 0, 0}, {0x331b, 0x08, 0, 0}, + {0x331c, 0x16, 0, 0}, {0x331d, 0x2d, 0, 0}, {0x331e, 0x54, 0, 0}, + {0x331f, 0x66, 0, 0}, {0x3320, 0x73, 0, 0}, {0x3321, 0x80, 0, 0}, + {0x3322, 0x8c, 0, 0}, {0x3323, 0x95, 0, 0}, {0x3324, 0x9d, 0, 0}, + {0x3325, 0xac, 0, 0}, {0x3326, 0xb8, 0, 0}, {0x3327, 0xcc, 0, 0}, + {0x3328, 0xdd, 0, 0}, {0x3329, 0xee, 0, 0}, {0x332e, 0x04, 0, 0}, + {0x332f, 0x04, 0, 0}, {0x3331, 0x02, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x00, 0, 0}, {0x3610, 0x40, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x307C, 0x10, 0, 0}, {0x3012, 0x10, 0, 0}, {0x3023, 0x06, 0, 0}, + {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, {0x302a, 0x03, 0, 0}, + {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, {0x300d, 0x01, 0, 0}, + {0x30d7, 0x90, 0, 0}, {0x3069, 0x04, 0, 0}, {0x303e, 0x00, 0, 0}, + {0x303f, 0xc0, 0, 0}, {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, + {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, {0x3362, 0x34, 0, 0}, + {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x03, 0, 0}, + {0x308b, 0x00, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, + {0x3361, 0x04, 0, 0}, {0x3362, 0x23, 0, 0}, {0x3363, 0x28, 0, 0}, + {0x3364, 0x5c, 0, 0}, {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0}, + {0x3089, 0xD0, 0, 0}, {0x308a, 0x01, 0, 0}, {0x308b, 0xe0, 0, 0}, + {0x304c, 0x83, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0xA1, 0, 0}, + {0x3011, 0x00, 0, 0}, {0x3010, 0x81, 0, 0}, {0x3014, 0x84, 0, 0}, + {0x302e, 0x00, 0, 0}, {0x302d, 0x00, 0, 0}, {0x3071, 0xeb, 0, 0}, + {0x301C, 0x02, 0, 0}, {0x3404, 0x02, 0, 0}, +}; + +static struct reg_value ov3640_setting_30fps_PAL_720_576[] = { + {0x3012, 0x80, 0, 0}, {0x304d, 0x45, 0, 0}, {0x30a7, 0x5e, 0, 0}, + {0x3086, 0x16, 0, 0}, {0x309C, 0x1a, 0, 0}, {0x30a2, 0xe4, 0, 0}, + {0x30aa, 0x42, 0, 0}, {0x30b0, 0xff, 0, 0}, {0x30b1, 0xff, 0, 0}, + {0x30b2, 0x10, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x304c, 0x81, 0, 0}, {0x30d7, 0x10, 0, 0}, + {0x30d9, 0x0d, 0, 0}, {0x30db, 0x08, 0, 0}, {0x3016, 0x82, 0, 0}, + {0x3018, 0x48, 0, 0}, {0x3019, 0x40, 0, 0}, {0x301a, 0x82, 0, 0}, + {0x307d, 0x00, 0, 0}, {0x3087, 0x02, 0, 0}, {0x3082, 0x20, 0, 0}, + {0x3015, 0x12, 0, 0}, {0x3014, 0x84, 0, 0}, {0x3013, 0xf7, 0, 0}, + {0x303c, 0x08, 0, 0}, {0x303d, 0x18, 0, 0}, {0x303e, 0x06, 0, 0}, + {0x303F, 0x0c, 0, 0}, {0x3030, 0x62, 0, 0}, {0x3031, 0x26, 0, 0}, + {0x3032, 0xe6, 0, 0}, {0x3033, 0x6e, 0, 0}, {0x3034, 0xea, 0, 0}, + {0x3035, 0xae, 0, 0}, {0x3036, 0xa6, 0, 0}, {0x3037, 0x6a, 0, 0}, + {0x3104, 0x02, 0, 0}, {0x3105, 0xfd, 0, 0}, {0x3106, 0x00, 0, 0}, + {0x3107, 0xff, 0, 0}, {0x3300, 0x13, 0, 0}, {0x3301, 0xde, 0, 0}, + {0x3302, 0xcf, 0, 0}, {0x3312, 0x26, 0, 0}, {0x3314, 0x42, 0, 0}, + {0x3313, 0x2b, 0, 0}, {0x3315, 0x42, 0, 0}, {0x3310, 0xd0, 0, 0}, + {0x3311, 0xbd, 0, 0}, {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, + {0x330e, 0x56, 0, 0}, {0x330f, 0x5c, 0, 0}, {0x330b, 0x1c, 0, 0}, + {0x3306, 0x5c, 0, 0}, {0x3307, 0x11, 0, 0}, {0x336a, 0x52, 0, 0}, + {0x3370, 0x46, 0, 0}, {0x3376, 0x38, 0, 0}, {0x30b8, 0x20, 0, 0}, + {0x30b9, 0x17, 0, 0}, {0x30ba, 0x04, 0, 0}, {0x30bb, 0x08, 0, 0}, + {0x3507, 0x06, 0, 0}, {0x350a, 0x4f, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x00, 0, 0}, {0x3600, 0xc0, 0, 0}, {0x3088, 0x08, 0, 0}, + {0x3089, 0x00, 0, 0}, {0x308a, 0x06, 0, 0}, {0x308b, 0x00, 0, 0}, + {0x308d, 0x04, 0, 0}, {0x3086, 0x03, 0, 0}, {0x3086, 0x00, 0, 0}, + {0x30a9, 0xb5, 0, 0}, {0x3317, 0x04, 0, 0}, {0x3316, 0xf8, 0, 0}, + {0x3312, 0x17, 0, 0}, {0x3314, 0x30, 0, 0}, {0x3313, 0x23, 0, 0}, + {0x3315, 0x3e, 0, 0}, {0x3311, 0x9e, 0, 0}, {0x3310, 0xc0, 0, 0}, + {0x330c, 0x18, 0, 0}, {0x330d, 0x18, 0, 0}, {0x330e, 0x5e, 0, 0}, + {0x330f, 0x6c, 0, 0}, {0x330b, 0x1c, 0, 0}, {0x3306, 0x5c, 0, 0}, + {0x3307, 0x11, 0, 0}, {0x3308, 0x25, 0, 0}, {0x3340, 0x20, 0, 0}, + {0x3341, 0x50, 0, 0}, {0x3342, 0x18, 0, 0}, {0x3343, 0x23, 0, 0}, + {0x3344, 0xad, 0, 0}, {0x3345, 0xd0, 0, 0}, {0x3346, 0xb8, 0, 0}, + {0x3347, 0xb4, 0, 0}, {0x3348, 0x04, 0, 0}, {0x3349, 0x98, 0, 0}, + {0x3355, 0x02, 0, 0}, {0x3358, 0x44, 0, 0}, {0x3359, 0x44, 0, 0}, + {0x3300, 0x13, 0, 0}, {0x3367, 0x23, 0, 0}, {0x3368, 0xBB, 0, 0}, + {0x3369, 0xD6, 0, 0}, {0x336A, 0x2A, 0, 0}, {0x336B, 0x07, 0, 0}, + {0x336C, 0x00, 0, 0}, {0x336D, 0x23, 0, 0}, {0x336E, 0xC3, 0, 0}, + {0x336F, 0xDE, 0, 0}, {0x3370, 0x2b, 0, 0}, {0x3371, 0x07, 0, 0}, + {0x3372, 0x00, 0, 0}, {0x3373, 0x23, 0, 0}, {0x3374, 0x9e, 0, 0}, + {0x3375, 0xD6, 0, 0}, {0x3376, 0x29, 0, 0}, {0x3377, 0x07, 0, 0}, + {0x3378, 0x00, 0, 0}, {0x332a, 0x1d, 0, 0}, {0x331b, 0x08, 0, 0}, + {0x331c, 0x16, 0, 0}, {0x331d, 0x2d, 0, 0}, {0x331e, 0x54, 0, 0}, + {0x331f, 0x66, 0, 0}, {0x3320, 0x73, 0, 0}, {0x3321, 0x80, 0, 0}, + {0x3322, 0x8c, 0, 0}, {0x3323, 0x95, 0, 0}, {0x3324, 0x9d, 0, 0}, + {0x3325, 0xac, 0, 0}, {0x3326, 0xb8, 0, 0}, {0x3327, 0xcc, 0, 0}, + {0x3328, 0xdd, 0, 0}, {0x3329, 0xee, 0, 0}, {0x332e, 0x04, 0, 0}, + {0x332f, 0x04, 0, 0}, {0x3331, 0x02, 0, 0}, {0x3100, 0x02, 0, 0}, + {0x3301, 0xde, 0, 0}, {0x3304, 0xfc, 0, 0}, {0x3400, 0x00, 0, 0}, + {0x3404, 0x00, 0, 0}, {0x3610, 0x40, 0, 0}, {0x304c, 0x81, 0, 0}, + {0x307C, 0x10, 0, 0}, {0x3012, 0x10, 0, 0}, {0x3023, 0x06, 0, 0}, + {0x3026, 0x03, 0, 0}, {0x3027, 0x04, 0, 0}, {0x302a, 0x03, 0, 0}, + {0x302b, 0x10, 0, 0}, {0x3075, 0x24, 0, 0}, {0x300d, 0x01, 0, 0}, + {0x30d7, 0x90, 0, 0}, {0x3069, 0x04, 0, 0}, {0x303e, 0x00, 0, 0}, + {0x303f, 0xc0, 0, 0}, {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, + {0x3360, 0x0c, 0, 0}, {0x3361, 0x04, 0, 0}, {0x3362, 0x34, 0, 0}, + {0x3363, 0x08, 0, 0}, {0x3364, 0x04, 0, 0}, {0x3403, 0x42, 0, 0}, + {0x3088, 0x04, 0, 0}, {0x3089, 0x00, 0, 0}, {0x308a, 0x03, 0, 0}, + {0x308b, 0x00, 0, 0}, {0x300e, 0x32, 0, 0}, {0x300f, 0x21, 0, 0}, + {0x3010, 0x20, 0, 0}, {0x3011, 0x01, 0, 0}, {0x304c, 0x82, 0, 0}, + {0x3302, 0xef, 0, 0}, {0x335f, 0x34, 0, 0}, {0x3360, 0x0c, 0, 0}, + {0x3361, 0x04, 0, 0}, {0x3362, 0x23, 0, 0}, {0x3363, 0x28, 0, 0}, + {0x3364, 0x5c, 0, 0}, {0x3403, 0x42, 0, 0}, {0x3088, 0x02, 0, 0}, + {0x3089, 0xD0, 0, 0}, {0x308a, 0x02, 0, 0}, {0x308b, 0x40, 0, 0}, + {0x304c, 0x83, 0, 0}, {0x300e, 0x39, 0, 0}, {0x300f, 0xA1, 0, 0}, + {0x3011, 0x00, 0, 0}, {0x3010, 0x81, 0, 0}, {0x3014, 0x84, 0, 0}, + {0x302e, 0x00, 0, 0}, {0x302d, 0x00, 0, 0}, {0x3071, 0xeb, 0, 0}, + {0x301C, 0x02, 0, 0}, {0x3404, 0x02, 0, 0}, +}; + +static struct ov3640_mode_info ov3640_mode_info_data[2][ov3640_mode_MAX + 1] = { + { + {ov3640_mode_VGA_640_480, 640, 480, + ov3640_setting_15fps_VGA_640_480, + ARRAY_SIZE(ov3640_setting_15fps_VGA_640_480)}, + {ov3640_mode_QVGA_320_240, 320, 240, + ov3640_setting_15fps_QVGA_320_240, + ARRAY_SIZE(ov3640_setting_15fps_QVGA_320_240)}, + {ov3640_mode_XGA_1024_768, 1024, 768, + ov3640_setting_15fps_XGA_1024_768, + ARRAY_SIZE(ov3640_setting_15fps_XGA_1024_768)}, + {ov3640_mode_QXGA_2048_1536, 2048, 1536, + ov3640_setting_15fps_QXGA_2048_1536, + ARRAY_SIZE(ov3640_setting_15fps_QXGA_2048_1536)}, + {ov3640_mode_NTSC_720_480, 720, 480, + ov3640_setting_15fps_NTSC_720_480, + ARRAY_SIZE(ov3640_setting_15fps_NTSC_720_480)}, + {ov3640_mode_PAL_720_576, 720, 576, + ov3640_setting_15fps_PAL_720_576, + ARRAY_SIZE(ov3640_setting_15fps_PAL_720_576)}, + }, + { + {ov3640_mode_VGA_640_480, 640, 480, + ov3640_setting_30fps_VGA_640_480, + ARRAY_SIZE(ov3640_setting_30fps_VGA_640_480)}, + {ov3640_mode_QVGA_320_240, 320, 240, + ov3640_setting_30fps_QVGA_320_240, + ARRAY_SIZE(ov3640_setting_30fps_QVGA_320_240)}, + {ov3640_mode_XGA_1024_768, 1024, 768, + ov3640_setting_30fps_XGA_1024_768, + ARRAY_SIZE(ov3640_setting_30fps_XGA_1024_768)}, + {ov3640_mode_QXGA_2048_1536, 0, 0, NULL, 0}, + {ov3640_mode_NTSC_720_480, 720, 480, + ov3640_setting_30fps_NTSC_720_480, + ARRAY_SIZE(ov3640_setting_30fps_NTSC_720_480)}, + {ov3640_mode_PAL_720_576, 720, 576, + ov3640_setting_30fps_PAL_720_576, + ARRAY_SIZE(ov3640_setting_30fps_PAL_720_576)}, + }, +}; + +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; +static struct mxc_camera_platform_data *camera_plat; + +static int ov3640_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int ov3640_remove(struct i2c_client *client); + +static s32 ov3640_read_reg(u16 reg, u8 *val); +static s32 ov3640_write_reg(u16 reg, u8 val); + +static const struct i2c_device_id ov3640_id[] = { + {"ov3640", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov3640_id); + +static struct i2c_driver ov3640_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov3640", + }, + .probe = ov3640_probe, + .remove = ov3640_remove, + .id_table = ov3640_id, +}; + +extern void gpio_sensor_active(unsigned int csi_index); +extern void gpio_sensor_inactive(unsigned int csi); + +static s32 ov3640_write_reg(u16 reg, u8 val) +{ + u8 au8Buf[3] = {0}; + + au8Buf[0] = reg >> 8; + au8Buf[1] = reg & 0xff; + au8Buf[2] = val; + + if (i2c_master_send(ov3640_data.i2c_client, au8Buf, 3) < 0) { + pr_err("%s:write reg error:reg=%x,val=%x\n", + __func__, reg, val); + return -1; + } + + return 0; +} + +static s32 ov3640_read_reg(u16 reg, u8 *val) +{ + u8 au8RegBuf[2] = {0}; + u8 u8RdVal = 0; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (2 != i2c_master_send(ov3640_data.i2c_client, au8RegBuf, 2)) { + pr_err("%s:write reg error:reg=%x\n", + __func__, reg); + return -1; + } + + if (1 != i2c_master_recv(ov3640_data.i2c_client, &u8RdVal, 1)) { + pr_err("%s:read reg error:reg=%x,val=%x\n", + __func__, reg, u8RdVal); + return -1; + } + + *val = u8RdVal; + + return u8RdVal; +} + +static int ov3640_init_mode(enum ov3640_frame_rate frame_rate, + enum ov3640_mode mode) +{ + struct reg_value *pModeSetting = NULL; + s32 i = 0; + s32 iModeSettingArySize = 0; + register u32 Delay_ms = 0; + register u16 RegAddr = 0; + register u8 Mask = 0; + register u8 Val = 0; + u8 RegVal = 0; + int retval = 0; + + if (mode > ov3640_mode_MAX || mode < ov3640_mode_MIN) { + pr_err("Wrong ov3640 mode detected!\n"); + return -1; + } + + pModeSetting = ov3640_mode_info_data[frame_rate][mode].init_data_ptr; + iModeSettingArySize = + ov3640_mode_info_data[frame_rate][mode].init_data_size; + + ov3640_data.pix.width = ov3640_mode_info_data[frame_rate][mode].width; + ov3640_data.pix.height = ov3640_mode_info_data[frame_rate][mode].height; + + if (ov3640_data.pix.width == 0 || ov3640_data.pix.height == 0 || + pModeSetting == NULL || iModeSettingArySize == 0) + return -EINVAL; + + for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) { + Delay_ms = pModeSetting->u32Delay_ms; + RegAddr = pModeSetting->u16RegAddr; + Val = pModeSetting->u8Val; + Mask = pModeSetting->u8Mask; + + if (Mask) { + retval = ov3640_read_reg(RegAddr, &RegVal); + if (retval < 0) + goto err; + + RegVal &= ~(u8)Mask; + Val &= Mask; + Val |= RegVal; + } + + retval = ov3640_write_reg(RegAddr, Val); + if (retval < 0) + goto err; + + if (Delay_ms) + msleep(Delay_ms); + } +err: + return retval; +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = ov3640_data.mclk; + pr_debug(" clock_curr=mclk=%d\n", ov3640_data.mclk); + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = OV3640_XCLK_MIN; + p->u.bt656.clock_max = OV3640_XCLK_MAX; + p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ + + return 0; +} + +/*! + * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + if (on && !sensor->on) { + gpio_sensor_active(ov3640_data.csi); + if (io_regulator) + if (regulator_enable(io_regulator) != 0) + return -EIO; + if (core_regulator) + if (regulator_enable(core_regulator) != 0) + return -EIO; + if (gpo_regulator) + if (regulator_enable(gpo_regulator) != 0) + return -EIO; + if (analog_regulator) + if (regulator_enable(analog_regulator) != 0) + return -EIO; + /* Make sure power on */ + if (camera_plat->pwdn) + camera_plat->pwdn(0); + + } else if (!on && sensor->on) { + if (analog_regulator) + regulator_disable(analog_regulator); + if (core_regulator) + regulator_disable(core_regulator); + if (io_regulator) + regulator_disable(io_regulator); + if (gpo_regulator) + regulator_disable(gpo_regulator); + gpio_sensor_inactive(ov3640_data.csi); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + enum ov3640_frame_rate frame_rate; + int ret = 0; + + /* Make sure power on */ + if (camera_plat->pwdn) + camera_plat->pwdn(0); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) || + (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + + /* Actual frame rate we use */ + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps == 15) + frame_rate = ov3640_15_fps; + else if (tgt_fps == 30) + frame_rate = ov3640_30_fps; + else { + pr_err(" The camera frame rate is not supported!\n"); + return -EINVAL; + } + + sensor->streamcap.timeperframe = *timeperframe; + sensor->streamcap.capturemode = + (u32)a->parm.capture.capturemode; + + ret = ov3640_init_mode(frame_rate, + sensor->streamcap.capturemode); + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not " \ + "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + f->fmt.pix = sensor->pix; + + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = ov3640_data.brightness; + break; + case V4L2_CID_HUE: + vc->value = ov3640_data.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = ov3640_data.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = ov3640_data.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = ov3640_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = ov3640_data.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = ov3640_data.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In ov3640:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + break; + case V4L2_CID_CONTRAST: + break; + case V4L2_CID_SATURATION: + break; + case V4L2_CID_HUE: + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + break; + case V4L2_CID_DO_WHITE_BALANCE: + break; + case V4L2_CID_RED_BALANCE: + break; + case V4L2_CID_BLUE_BALANCE: + break; + case V4L2_CID_GAMMA: + break; + case V4L2_CID_EXPOSURE: + break; + case V4L2_CID_AUTOGAIN: + break; + case V4L2_CID_GAIN: + break; + case V4L2_CID_HFLIP: + break; + case V4L2_CID_VFLIP: + break; + default: + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ioctl_enum_framesizes(struct v4l2_int_device *s, + struct v4l2_frmsizeenum *fsize) +{ + if (fsize->index > ov3640_mode_MAX) + return -EINVAL; + + fsize->pixel_format = ov3640_data.pix.pixelformat; + fsize->discrete.width = + max(ov3640_mode_info_data[0][fsize->index].width, + ov3640_mode_info_data[1][fsize->index].width); + fsize->discrete.height = + max(ov3640_mode_info_data[0][fsize->index].height, + ov3640_mode_info_data[1][fsize->index].height); + return 0; +} + +/*! + * ioctl_g_chip_ident - V4L2 sensor interface handler for + * VIDIOC_DBG_G_CHIP_IDENT ioctl + * @s: pointer to standard V4L2 device structure + * @id: pointer to int + * + * Return 0. + */ +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov3640_camera"); + + return 0; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + + return 0; +} + +/*! + * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT + * @s: pointer to standard V4L2 device structure + * @fmt: pointer to standard V4L2 fmt description structure + * + * Return 0. + */ +static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, + struct v4l2_fmtdesc *fmt) +{ + if (fmt->index > ov3640_mode_MAX) + return -EINVAL; + + fmt->pixelformat = ov3640_data.pix.pixelformat; + + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct sensor *sensor = s->priv; + u32 tgt_xclk; /* target xclk */ + u32 tgt_fps; /* target frames per secound */ + enum ov3640_frame_rate frame_rate; + + gpio_sensor_active(ov3640_data.csi); + ov3640_data.on = true; + + /* mclk */ + tgt_xclk = ov3640_data.mclk; + tgt_xclk = min(tgt_xclk, (u32)OV3640_XCLK_MAX); + tgt_xclk = max(tgt_xclk, (u32)OV3640_XCLK_MIN); + ov3640_data.mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); + set_mclk_rate(&ov3640_data.mclk, ov3640_data.csi); + + /* Default camera frame rate is set in probe */ + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 15) + frame_rate = ov3640_15_fps; + else if (tgt_fps == 30) + frame_rate = ov3640_30_fps; + else + return -EINVAL; /* Only support 15fps or 30fps now. */ + + return ov3640_init_mode(frame_rate, + sensor->streamcap.capturemode); +} + +/*! + * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num + * @s: pointer to standard V4L2 device structure + * + * Delinitialise the device when slave detaches to the master. + */ +static int ioctl_dev_exit(struct v4l2_int_device *s) +{ + gpio_sensor_inactive(ov3640_data.csi); + + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc ov3640_ioctl_desc[] = { + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, + {vidioc_int_dev_exit_num, ioctl_dev_exit}, + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init}, + {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, +/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */ + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl}, + {vidioc_int_enum_framesizes_num, + (v4l2_int_ioctl_func *)ioctl_enum_framesizes}, + {vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *)ioctl_g_chip_ident}, +}; + +static struct v4l2_int_slave ov3640_slave = { + .ioctls = ov3640_ioctl_desc, + .num_ioctls = ARRAY_SIZE(ov3640_ioctl_desc), +}; + +static struct v4l2_int_device ov3640_int_device = { + .module = THIS_MODULE, + .name = "ov3640", + .type = v4l2_int_type_slave, + .u = { + .slave = &ov3640_slave, + }, +}; + +/*! + * ov3640 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int ov3640_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + struct mxc_camera_platform_data *plat_data = client->dev.platform_data; + + /* Set initial values for the sensor struct. */ + memset(&ov3640_data, 0, sizeof(ov3640_data)); + ov3640_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ + ov3640_data.mclk = plat_data->mclk; + ov3640_data.csi = plat_data->csi; + + ov3640_data.i2c_client = client; + ov3640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; + ov3640_data.pix.width = 640; + ov3640_data.pix.height = 480; + ov3640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + ov3640_data.streamcap.capturemode = 0; + ov3640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; + ov3640_data.streamcap.timeperframe.numerator = 1; + + if (plat_data->io_regulator) { + io_regulator = regulator_get(&client->dev, + plat_data->io_regulator); + if (!IS_ERR(io_regulator)) { + regulator_set_voltage(io_regulator, + OV3640_VOLTAGE_DIGITAL_IO, + OV3640_VOLTAGE_DIGITAL_IO); + if (regulator_enable(io_regulator) != 0) { + pr_err("%s:io set voltage error\n", __func__); + goto err1; + } else { + dev_dbg(&client->dev, + "%s:io set voltage ok\n", __func__); + } + } else + io_regulator = NULL; + } + + if (plat_data->core_regulator) { + core_regulator = regulator_get(&client->dev, + plat_data->core_regulator); + if (!IS_ERR(core_regulator)) { + regulator_set_voltage(core_regulator, + OV3640_VOLTAGE_DIGITAL_CORE, + OV3640_VOLTAGE_DIGITAL_CORE); + if (regulator_enable(core_regulator) != 0) { + pr_err("%s:core set voltage error\n", __func__); + goto err2; + } else { + dev_dbg(&client->dev, + "%s:core set voltage ok\n", __func__); + } + } else + core_regulator = NULL; + } + + if (plat_data->analog_regulator) { + analog_regulator = regulator_get(&client->dev, + plat_data->analog_regulator); + if (!IS_ERR(analog_regulator)) { + regulator_set_voltage(analog_regulator, + OV3640_VOLTAGE_ANALOG, + OV3640_VOLTAGE_ANALOG); + if (regulator_enable(analog_regulator) != 0) { + pr_err("%s:analog set voltage error\n", + __func__); + goto err3; + } else { + dev_dbg(&client->dev, + "%s:analog set voltage ok\n", __func__); + } + } else + analog_regulator = NULL; + } + + if (plat_data->gpo_regulator) { + gpo_regulator = regulator_get(&client->dev, + plat_data->gpo_regulator); + if (!IS_ERR(gpo_regulator)) { + regulator_set_voltage(gpo_regulator, + OV3640_VOLTAGE_DIGITAL_GPO, + OV3640_VOLTAGE_DIGITAL_GPO); + if (regulator_enable(gpo_regulator) != 0) { + pr_err("%s:gpo enable error\n", __func__); + goto err4; + } else { + dev_dbg(&client->dev, + "%s:gpo enable ok\n", __func__); + } + } else + gpo_regulator = NULL; + } + + if (plat_data->pwdn) + plat_data->pwdn(0); + + camera_plat = plat_data; + + ov3640_int_device.priv = &ov3640_data; + retval = v4l2_int_device_register(&ov3640_int_device); + + return retval; + +err4: + if (analog_regulator) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator); + } +err3: + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } +err2: + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } +err1: + return -1; +} + +/*! + * ov3640 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int ov3640_remove(struct i2c_client *client) +{ + v4l2_int_device_unregister(&ov3640_int_device); + + if (gpo_regulator) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator); + } + + if (analog_regulator) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator); + } + + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } + + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } + + return 0; +} + +/*! + * ov3640 init function + * Called by insmod ov3640_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int ov3640_init(void) +{ + u8 err; + + err = i2c_add_driver(&ov3640_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * OV3640 cleanup function + * Called on rmmod ov3640_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit ov3640_clean(void) +{ + i2c_del_driver(&ov3640_i2c_driver); +} + +module_init(ov3640_init); +module_exit(ov3640_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OV3640 Camera Driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_ALIAS("CSI"); diff --git a/drivers/media/video/mxc/capture/ov5640.c b/drivers/media/video/mxc/capture/ov5640.c new file mode 100644 index 000000000000..7a687a097072 --- /dev/null +++ b/drivers/media/video/mxc/capture/ov5640.c @@ -0,0 +1,1527 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" + +#define OV5640_VOLTAGE_ANALOG 2800000 +#define OV5640_VOLTAGE_DIGITAL_CORE 1500000 +#define OV5640_VOLTAGE_DIGITAL_IO 1800000 + +#define MIN_FPS 15 +#define MAX_FPS 30 +#define DEFAULT_FPS 30 + +#define OV5640_XCLK_MIN 6000000 +#define OV5640_XCLK_MAX 24000000 + +enum ov5640_mode { + ov5640_mode_MIN = 0, + ov5640_mode_VGA_640_480 = 0, + ov5640_mode_QVGA_320_240 = 1, + ov5640_mode_NTSC_720_480 = 2, + ov5640_mode_PAL_720_576 = 3, + ov5640_mode_720P_1280_720 = 4, + ov5640_mode_1080P_1920_1080 = 5, + ov5640_mode_QSXGA_2592_1944 = 6, + ov5640_mode_MAX = 6 +}; + +enum ov5640_frame_rate { + ov5640_15_fps, + ov5640_30_fps +}; + +struct reg_value { + u16 u16RegAddr; + u8 u8Val; + u8 u8Mask; + u32 u32Delay_ms; +}; + +struct ov5640_mode_info { + enum ov5640_mode mode; + u32 width; + u32 height; + struct reg_value *init_data_ptr; + u32 init_data_size; +}; + +/*! + * Maintains the information on the current state of the sesor. + */ +struct sensor { + const struct ov5640_platform_data *platform_data; + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 mclk; + int csi; +} ov5640_data; + +static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = { + {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3008, 0x42, 0, 0}, + {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, + {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, {0x3036, 0x69, 0, 0}, + {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x2e, 0, 0}, + {0x3632, 0xe2, 0, 0}, {0x3633, 0x23, 0, 0}, {0x3621, 0xe0, 0, 0}, + {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, + {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, + {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, + {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, + {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, + {0x3635, 0x1c, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, + {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, + {0x3c06, 0x00, 0, 0}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, + {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, + {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0}, + {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0}, + {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0}, + {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, + {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0}, + {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0}, + {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, + {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x21, 0, 0}, + {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0}, + {0x3a03, 0xb0, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, + {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x06, 0, 0}, + {0x3a0d, 0x08, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xb0, 0, 0}, + {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0}, + {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x5000, 0xa7, 0, 0}, {0x5001, 0x83, 0, 0}, + {0x5180, 0xff, 0, 0}, {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, + {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, + {0x5186, 0x09, 0, 0}, {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, + {0x5189, 0x75, 0, 0}, {0x518a, 0x54, 0, 0}, {0x518b, 0xe0, 0, 0}, + {0x518c, 0xb2, 0, 0}, {0x518d, 0x42, 0, 0}, {0x518e, 0x3d, 0, 0}, + {0x518f, 0x56, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, + {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, + {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, + {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, + {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, + {0x519e, 0x38, 0, 0}, {0x5381, 0x1c, 0, 0}, {0x5382, 0x5a, 0, 0}, + {0x5383, 0x06, 0, 0}, {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, + {0x5386, 0x88, 0, 0}, {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, + {0x5389, 0x10, 0, 0}, {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, + {0x5300, 0x08, 0, 0}, {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, + {0x5303, 0x00, 0, 0}, {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, + {0x5306, 0x08, 0, 0}, {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, + {0x530a, 0x30, 0, 0}, {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, + {0x5480, 0x01, 0, 0}, {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, + {0x5483, 0x28, 0, 0}, {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, + {0x5486, 0x71, 0, 0}, {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, + {0x5489, 0x91, 0, 0}, {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, + {0x548c, 0xb8, 0, 0}, {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, + {0x548f, 0xea, 0, 0}, {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, + {0x5583, 0x40, 0, 0}, {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, + {0x558a, 0x00, 0, 0}, {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, + {0x5801, 0x15, 0, 0}, {0x5802, 0x10, 0, 0}, {0x5803, 0x10, 0, 0}, + {0x5804, 0x15, 0, 0}, {0x5805, 0x23, 0, 0}, {0x5806, 0x0c, 0, 0}, + {0x5807, 0x08, 0, 0}, {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, + {0x580a, 0x08, 0, 0}, {0x580b, 0x0c, 0, 0}, {0x580c, 0x07, 0, 0}, + {0x580d, 0x03, 0, 0}, {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, + {0x5810, 0x03, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x07, 0, 0}, + {0x5813, 0x03, 0, 0}, {0x5814, 0x00, 0, 0}, {0x5815, 0x00, 0, 0}, + {0x5816, 0x03, 0, 0}, {0x5817, 0x07, 0, 0}, {0x5818, 0x0b, 0, 0}, + {0x5819, 0x08, 0, 0}, {0x581a, 0x05, 0, 0}, {0x581b, 0x05, 0, 0}, + {0x581c, 0x07, 0, 0}, {0x581d, 0x0b, 0, 0}, {0x581e, 0x2a, 0, 0}, + {0x581f, 0x16, 0, 0}, {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, + {0x5822, 0x15, 0, 0}, {0x5823, 0x29, 0, 0}, {0x5824, 0xbf, 0, 0}, + {0x5825, 0xaf, 0, 0}, {0x5826, 0x9f, 0, 0}, {0x5827, 0xaf, 0, 0}, + {0x5828, 0xdf, 0, 0}, {0x5829, 0x6f, 0, 0}, {0x582a, 0x8e, 0, 0}, + {0x582b, 0xab, 0, 0}, {0x582c, 0x9e, 0, 0}, {0x582d, 0x7f, 0, 0}, + {0x582e, 0x4f, 0, 0}, {0x582f, 0x89, 0, 0}, {0x5830, 0x86, 0, 0}, + {0x5831, 0x98, 0, 0}, {0x5832, 0x6f, 0, 0}, {0x5833, 0x4f, 0, 0}, + {0x5834, 0x6e, 0, 0}, {0x5835, 0x7b, 0, 0}, {0x5836, 0x7e, 0, 0}, + {0x5837, 0x6f, 0, 0}, {0x5838, 0xde, 0, 0}, {0x5839, 0xbf, 0, 0}, + {0x583a, 0x9f, 0, 0}, {0x583b, 0xbf, 0, 0}, {0x583c, 0xec, 0, 0}, + {0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, + {0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, + {0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3035, 0x11, 0, 0}, + {0x3036, 0x46, 0, 0}, +}; + +static struct reg_value ov5640_setting_30fps_VGA_640_480[] = { + {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3008, 0x42, 0, 0}, + {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, + {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0}, + {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x2e, 0, 0}, + {0x3632, 0xe2, 0, 0}, {0x3633, 0x23, 0, 0}, {0x3621, 0xe0, 0, 0}, + {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, + {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, + {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, + {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, + {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, + {0x3635, 0x1c, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, + {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, + {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0}, + {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, + {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, + {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, + {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, + {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, + {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, + {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, + {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, + {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x62, 0, 0}, + {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, + {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, + {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, + {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0}, + {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, + {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, + {0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, + {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, + {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, + {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x75, 0, 0}, + {0x518a, 0x54, 0, 0}, {0x518b, 0xe0, 0, 0}, {0x518c, 0xb2, 0, 0}, + {0x518d, 0x42, 0, 0}, {0x518e, 0x3d, 0, 0}, {0x518f, 0x56, 0, 0}, + {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, + {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, + {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, + {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, {0x519e, 0x38, 0, 0}, + {0x5381, 0x1c, 0, 0}, {0x5382, 0x5a, 0, 0}, {0x5383, 0x06, 0, 0}, + {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, + {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, + {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, + {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, + {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, + {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, + {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, + {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, + {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, + {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, + {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, + {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, + {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, + {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x15, 0, 0}, + {0x5802, 0x10, 0, 0}, {0x5803, 0x10, 0, 0}, {0x5804, 0x15, 0, 0}, + {0x5805, 0x23, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, + {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, + {0x580b, 0x0c, 0, 0}, {0x580c, 0x07, 0, 0}, {0x580d, 0x03, 0, 0}, + {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, + {0x5811, 0x07, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, + {0x5814, 0x00, 0, 0}, {0x5815, 0x00, 0, 0}, {0x5816, 0x03, 0, 0}, + {0x5817, 0x07, 0, 0}, {0x5818, 0x0b, 0, 0}, {0x5819, 0x08, 0, 0}, + {0x581a, 0x05, 0, 0}, {0x581b, 0x05, 0, 0}, {0x581c, 0x07, 0, 0}, + {0x581d, 0x0b, 0, 0}, {0x581e, 0x2a, 0, 0}, {0x581f, 0x16, 0, 0}, + {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, + {0x5823, 0x29, 0, 0}, {0x5824, 0xbf, 0, 0}, {0x5825, 0xaf, 0, 0}, + {0x5826, 0x9f, 0, 0}, {0x5827, 0xaf, 0, 0}, {0x5828, 0xdf, 0, 0}, + {0x5829, 0x6f, 0, 0}, {0x582a, 0x8e, 0, 0}, {0x582b, 0xab, 0, 0}, + {0x582c, 0x9e, 0, 0}, {0x582d, 0x7f, 0, 0}, {0x582e, 0x4f, 0, 0}, + {0x582f, 0x89, 0, 0}, {0x5830, 0x86, 0, 0}, {0x5831, 0x98, 0, 0}, + {0x5832, 0x6f, 0, 0}, {0x5833, 0x4f, 0, 0}, {0x5834, 0x6e, 0, 0}, + {0x5835, 0x7b, 0, 0}, {0x5836, 0x7e, 0, 0}, {0x5837, 0x6f, 0, 0}, + {0x5838, 0xde, 0, 0}, {0x5839, 0xbf, 0, 0}, {0x583a, 0x9f, 0, 0}, + {0x583b, 0xbf, 0, 0}, {0x583c, 0xec, 0, 0}, {0x5025, 0x00, 0, 0}, + {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, + {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0}, + {0x3008, 0x02, 0, 0}, {0x3035, 0x11, 0, 0}, +}; + +static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = { + {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3008, 0x42, 0, 0}, + {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, + {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0}, + {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x2e, 0, 0}, + {0x3632, 0xe2, 0, 0}, {0x3633, 0x23, 0, 0}, {0x3621, 0xe0, 0, 0}, + {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, + {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, + {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, + {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, + {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, + {0x3635, 0x1c, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, + {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, + {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0}, + {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, + {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, + {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, + {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, + {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, + {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, + {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, + {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, + {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x62, 0, 0}, + {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, + {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, + {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, + {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0}, + {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, + {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, + {0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, + {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, + {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, + {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x75, 0, 0}, + {0x518a, 0x54, 0, 0}, {0x518b, 0xe0, 0, 0}, {0x518c, 0xb2, 0, 0}, + {0x518d, 0x42, 0, 0}, {0x518e, 0x3d, 0, 0}, {0x518f, 0x56, 0, 0}, + {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, + {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, + {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, + {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, {0x519e, 0x38, 0, 0}, + {0x5381, 0x1c, 0, 0}, {0x5382, 0x5a, 0, 0}, {0x5383, 0x06, 0, 0}, + {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, + {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, + {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, + {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, + {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, + {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, + {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, + {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, + {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, + {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, + {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, + {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, + {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, + {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x15, 0, 0}, + {0x5802, 0x10, 0, 0}, {0x5803, 0x10, 0, 0}, {0x5804, 0x15, 0, 0}, + {0x5805, 0x23, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, + {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, + {0x580b, 0x0c, 0, 0}, {0x580c, 0x07, 0, 0}, {0x580d, 0x03, 0, 0}, + {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, + {0x5811, 0x07, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, + {0x5814, 0x00, 0, 0}, {0x5815, 0x00, 0, 0}, {0x5816, 0x03, 0, 0}, + {0x5817, 0x07, 0, 0}, {0x5818, 0x0b, 0, 0}, {0x5819, 0x08, 0, 0}, + {0x581a, 0x05, 0, 0}, {0x581b, 0x05, 0, 0}, {0x581c, 0x07, 0, 0}, + {0x581d, 0x0b, 0, 0}, {0x581e, 0x2a, 0, 0}, {0x581f, 0x16, 0, 0}, + {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, + {0x5823, 0x29, 0, 0}, {0x5824, 0xbf, 0, 0}, {0x5825, 0xaf, 0, 0}, + {0x5826, 0x9f, 0, 0}, {0x5827, 0xaf, 0, 0}, {0x5828, 0xdf, 0, 0}, + {0x5829, 0x6f, 0, 0}, {0x582a, 0x8e, 0, 0}, {0x582b, 0xab, 0, 0}, + {0x582c, 0x9e, 0, 0}, {0x582d, 0x7f, 0, 0}, {0x582e, 0x4f, 0, 0}, + {0x582f, 0x89, 0, 0}, {0x5830, 0x86, 0, 0}, {0x5831, 0x98, 0, 0}, + {0x5832, 0x6f, 0, 0}, {0x5833, 0x4f, 0, 0}, {0x5834, 0x6e, 0, 0}, + {0x5835, 0x7b, 0, 0}, {0x5836, 0x7e, 0, 0}, {0x5837, 0x6f, 0, 0}, + {0x5838, 0xde, 0, 0}, {0x5839, 0xbf, 0, 0}, {0x583a, 0x9f, 0, 0}, + {0x583b, 0xbf, 0, 0}, {0x583c, 0xec, 0, 0}, {0x5025, 0x00, 0, 0}, + {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, + {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0}, + {0x3008, 0x02, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3808, 0x01, 0, 0}, + {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, +}; + +static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { + {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3008, 0x42, 0, 0}, + {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, + {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0}, + {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x2e, 0, 0}, + {0x3632, 0xe2, 0, 0}, {0x3633, 0x23, 0, 0}, {0x3621, 0xe0, 0, 0}, + {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, + {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, + {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, + {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, + {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, + {0x3635, 0x1c, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, + {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, + {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0}, + {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, + {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, + {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, + {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, + {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, + {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, + {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, + {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x60, 0, 0}, + {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x62, 0, 0}, + {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, + {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, + {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, + {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0}, + {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, + {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, + {0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, + {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, + {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, + {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x75, 0, 0}, + {0x518a, 0x54, 0, 0}, {0x518b, 0xe0, 0, 0}, {0x518c, 0xb2, 0, 0}, + {0x518d, 0x42, 0, 0}, {0x518e, 0x3d, 0, 0}, {0x518f, 0x56, 0, 0}, + {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, + {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, + {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, + {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, {0x519e, 0x38, 0, 0}, + {0x5381, 0x1c, 0, 0}, {0x5382, 0x5a, 0, 0}, {0x5383, 0x06, 0, 0}, + {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, + {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, + {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, + {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, + {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, + {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, + {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, + {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, + {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, + {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, + {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, + {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, + {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, + {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x15, 0, 0}, + {0x5802, 0x10, 0, 0}, {0x5803, 0x10, 0, 0}, {0x5804, 0x15, 0, 0}, + {0x5805, 0x23, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, + {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, + {0x580b, 0x0c, 0, 0}, {0x580c, 0x07, 0, 0}, {0x580d, 0x03, 0, 0}, + {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, + {0x5811, 0x07, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, + {0x5814, 0x00, 0, 0}, {0x5815, 0x00, 0, 0}, {0x5816, 0x03, 0, 0}, + {0x5817, 0x07, 0, 0}, {0x5818, 0x0b, 0, 0}, {0x5819, 0x08, 0, 0}, + {0x581a, 0x05, 0, 0}, {0x581b, 0x05, 0, 0}, {0x581c, 0x07, 0, 0}, + {0x581d, 0x0b, 0, 0}, {0x581e, 0x2a, 0, 0}, {0x581f, 0x16, 0, 0}, + {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, + {0x5823, 0x29, 0, 0}, {0x5824, 0xbf, 0, 0}, {0x5825, 0xaf, 0, 0}, + {0x5826, 0x9f, 0, 0}, {0x5827, 0xaf, 0, 0}, {0x5828, 0xdf, 0, 0}, + {0x5829, 0x6f, 0, 0}, {0x582a, 0x8e, 0, 0}, {0x582b, 0xab, 0, 0}, + {0x582c, 0x9e, 0, 0}, {0x582d, 0x7f, 0, 0}, {0x582e, 0x4f, 0, 0}, + {0x582f, 0x89, 0, 0}, {0x5830, 0x86, 0, 0}, {0x5831, 0x98, 0, 0}, + {0x5832, 0x6f, 0, 0}, {0x5833, 0x4f, 0, 0}, {0x5834, 0x6e, 0, 0}, + {0x5835, 0x7b, 0, 0}, {0x5836, 0x7e, 0, 0}, {0x5837, 0x6f, 0, 0}, + {0x5838, 0xde, 0, 0}, {0x5839, 0xbf, 0, 0}, {0x583a, 0x9f, 0, 0}, + {0x583b, 0xbf, 0, 0}, {0x583c, 0xec, 0, 0}, {0x5025, 0x00, 0, 0}, + {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, + {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0}, + {0x3008, 0x02, 0, 0}, {0x3035, 0x11, 0, 0}, +}; + +static struct reg_value ov5640_setting_30fps_PAL_720_576[] = { + {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3008, 0x42, 0, 0}, + {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, + {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0}, + {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x2e, 0, 0}, + {0x3632, 0xe2, 0, 0}, {0x3633, 0x23, 0, 0}, {0x3621, 0xe0, 0, 0}, + {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, + {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, + {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, + {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, + {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, + {0x3635, 0x1c, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, + {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, + {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0}, + {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, + {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, + {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, + {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, + {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, + {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, + {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, + {0x3811, 0x62, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, + {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x62, 0, 0}, + {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, + {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, + {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, + {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0}, + {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, + {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, + {0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, + {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, + {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, + {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x75, 0, 0}, + {0x518a, 0x54, 0, 0}, {0x518b, 0xe0, 0, 0}, {0x518c, 0xb2, 0, 0}, + {0x518d, 0x42, 0, 0}, {0x518e, 0x3d, 0, 0}, {0x518f, 0x56, 0, 0}, + {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, + {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, + {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, + {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, {0x519e, 0x38, 0, 0}, + {0x5381, 0x1c, 0, 0}, {0x5382, 0x5a, 0, 0}, {0x5383, 0x06, 0, 0}, + {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, + {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, + {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, + {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, + {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, + {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, + {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, + {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, + {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, + {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, + {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, + {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, + {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, + {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x15, 0, 0}, + {0x5802, 0x10, 0, 0}, {0x5803, 0x10, 0, 0}, {0x5804, 0x15, 0, 0}, + {0x5805, 0x23, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, + {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, + {0x580b, 0x0c, 0, 0}, {0x580c, 0x07, 0, 0}, {0x580d, 0x03, 0, 0}, + {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, + {0x5811, 0x07, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, + {0x5814, 0x00, 0, 0}, {0x5815, 0x00, 0, 0}, {0x5816, 0x03, 0, 0}, + {0x5817, 0x07, 0, 0}, {0x5818, 0x0b, 0, 0}, {0x5819, 0x08, 0, 0}, + {0x581a, 0x05, 0, 0}, {0x581b, 0x05, 0, 0}, {0x581c, 0x07, 0, 0}, + {0x581d, 0x0b, 0, 0}, {0x581e, 0x2a, 0, 0}, {0x581f, 0x16, 0, 0}, + {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, + {0x5823, 0x29, 0, 0}, {0x5824, 0xbf, 0, 0}, {0x5825, 0xaf, 0, 0}, + {0x5826, 0x9f, 0, 0}, {0x5827, 0xaf, 0, 0}, {0x5828, 0xdf, 0, 0}, + {0x5829, 0x6f, 0, 0}, {0x582a, 0x8e, 0, 0}, {0x582b, 0xab, 0, 0}, + {0x582c, 0x9e, 0, 0}, {0x582d, 0x7f, 0, 0}, {0x582e, 0x4f, 0, 0}, + {0x582f, 0x89, 0, 0}, {0x5830, 0x86, 0, 0}, {0x5831, 0x98, 0, 0}, + {0x5832, 0x6f, 0, 0}, {0x5833, 0x4f, 0, 0}, {0x5834, 0x6e, 0, 0}, + {0x5835, 0x7b, 0, 0}, {0x5836, 0x7e, 0, 0}, {0x5837, 0x6f, 0, 0}, + {0x5838, 0xde, 0, 0}, {0x5839, 0xbf, 0, 0}, {0x583a, 0x9f, 0, 0}, + {0x583b, 0xbf, 0, 0}, {0x583c, 0xec, 0, 0}, {0x5025, 0x00, 0, 0}, + {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, + {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0}, + {0x3008, 0x02, 0, 0}, {0x3035, 0x11, 0, 0}, +}; + +static struct reg_value ov5640_setting_30fps_720P_1280_720[] = { + {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3008, 0x42, 0, 0}, + {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, + {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x69, 0, 0}, + {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x2e, 0, 0}, + {0x3632, 0xe2, 0, 0}, {0x3633, 0x23, 0, 0}, {0x3621, 0xe0, 0, 0}, + {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, + {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, + {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, + {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, + {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, + {0x3635, 0x1c, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, + {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, + {0x3c06, 0x00, 0, 0}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, + {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, + {0x3820, 0x41, 0, 0}, {0x3821, 0x27, 0, 0}, {0x3814, 0x31, 0, 0}, + {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, + {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0}, + {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0}, + {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, + {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0}, + {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0}, + {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, + {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x62, 0, 0}, + {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, + {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0}, + {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0}, + {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0}, + {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3002, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xff, 0, 0}, + {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0}, + {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x04, 0, 0}, + {0x5000, 0xa7, 0, 0}, {0x5001, 0x83, 0, 0}, {0x5180, 0xff, 0, 0}, + {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, + {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, + {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x75, 0, 0}, + {0x518a, 0x54, 0, 0}, {0x518b, 0xe0, 0, 0}, {0x518c, 0xb2, 0, 0}, + {0x518d, 0x42, 0, 0}, {0x518e, 0x3d, 0, 0}, {0x518f, 0x56, 0, 0}, + {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, + {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, + {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, + {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, {0x519e, 0x38, 0, 0}, + {0x5381, 0x1c, 0, 0}, {0x5382, 0x5a, 0, 0}, {0x5383, 0x06, 0, 0}, + {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, + {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, + {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, + {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, + {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, + {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, + {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, + {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, + {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, + {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, + {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, + {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, + {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, + {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x15, 0, 0}, + {0x5802, 0x10, 0, 0}, {0x5803, 0x10, 0, 0}, {0x5804, 0x15, 0, 0}, + {0x5805, 0x23, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, + {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, + {0x580b, 0x0c, 0, 0}, {0x580c, 0x07, 0, 0}, {0x580d, 0x03, 0, 0}, + {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, + {0x5811, 0x07, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, + {0x5814, 0x00, 0, 0}, {0x5815, 0x00, 0, 0}, {0x5816, 0x03, 0, 0}, + {0x5817, 0x07, 0, 0}, {0x5818, 0x0b, 0, 0}, {0x5819, 0x08, 0, 0}, + {0x581a, 0x05, 0, 0}, {0x581b, 0x05, 0, 0}, {0x581c, 0x07, 0, 0}, + {0x581d, 0x0b, 0, 0}, {0x581e, 0x2a, 0, 0}, {0x581f, 0x16, 0, 0}, + {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, + {0x5823, 0x29, 0, 0}, {0x5824, 0xbf, 0, 0}, {0x5825, 0xaf, 0, 0}, + {0x5826, 0x9f, 0, 0}, {0x5827, 0xaf, 0, 0}, {0x5828, 0xdf, 0, 0}, + {0x5829, 0x6f, 0, 0}, {0x582a, 0x8e, 0, 0}, {0x582b, 0xab, 0, 0}, + {0x582c, 0x9e, 0, 0}, {0x582d, 0x7f, 0, 0}, {0x582e, 0x4f, 0, 0}, + {0x582f, 0x89, 0, 0}, {0x5830, 0x86, 0, 0}, {0x5831, 0x98, 0, 0}, + {0x5832, 0x6f, 0, 0}, {0x5833, 0x4f, 0, 0}, {0x5834, 0x6e, 0, 0}, + {0x5835, 0x7b, 0, 0}, {0x5836, 0x7e, 0, 0}, {0x5837, 0x6f, 0, 0}, + {0x5838, 0xde, 0, 0}, {0x5839, 0xbf, 0, 0}, {0x583a, 0x9f, 0, 0}, + {0x583b, 0xbf, 0, 0}, {0x583c, 0xec, 0, 0}, {0x5025, 0x00, 0, 0}, + {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, + {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0}, + {0x3008, 0x02, 0, 0}, {0x3035, 0x21, 0, 0}, {0x3002, 0x1c, 0, 0}, + {0x3006, 0xc3, 0, 0}, {0x3821, 0x07, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0}, + {0x460b, 0x37, 0, 0}, +}; + +static struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { + {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3008, 0x42, 0, 0}, + {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, + {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x69, 0, 0}, + {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x2e, 0, 0}, + {0x3632, 0xe2, 0, 0}, {0x3633, 0x23, 0, 0}, {0x3621, 0xe0, 0, 0}, + {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, + {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, + {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, + {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, + {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, + {0x3635, 0x1c, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, + {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, + {0x3c06, 0x00, 0, 0}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, + {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, + {0x3820, 0x41, 0, 0}, {0x3821, 0x26, 0, 0}, {0x3814, 0x11, 0, 0}, + {0x3815, 0x11, 0, 0}, {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, + {0x3802, 0x01, 0, 0}, {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, + {0x3805, 0xef, 0, 0}, {0x3806, 0x05, 0, 0}, {0x3807, 0xf2, 0, 0}, + {0x3808, 0x07, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, + {0x380b, 0x38, 0, 0}, {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, + {0x380e, 0x04, 0, 0}, {0x380f, 0x60, 0, 0}, {0x3810, 0x00, 0, 0}, + {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, + {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x62, 0, 0}, + {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x04, 0, 0}, + {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x50, 0, 0}, + {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0}, {0x3a15, 0x60, 0, 0}, + {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3002, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xff, 0, 0}, + {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0}, + {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3824, 0x04, 0, 0}, + {0x5000, 0xa7, 0, 0}, {0x5001, 0x83, 0, 0}, {0x5180, 0xff, 0, 0}, + {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, + {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, + {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x75, 0, 0}, + {0x518a, 0x54, 0, 0}, {0x518b, 0xe0, 0, 0}, {0x518c, 0xb2, 0, 0}, + {0x518d, 0x42, 0, 0}, {0x518e, 0x3d, 0, 0}, {0x518f, 0x56, 0, 0}, + {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, + {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, + {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, + {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, {0x519e, 0x38, 0, 0}, + {0x5381, 0x1c, 0, 0}, {0x5382, 0x5a, 0, 0}, {0x5383, 0x06, 0, 0}, + {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, + {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, + {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, + {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, + {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, + {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, + {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, + {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, + {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, + {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, + {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, + {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, + {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, + {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x15, 0, 0}, + {0x5802, 0x10, 0, 0}, {0x5803, 0x10, 0, 0}, {0x5804, 0x15, 0, 0}, + {0x5805, 0x23, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, + {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, + {0x580b, 0x0c, 0, 0}, {0x580c, 0x07, 0, 0}, {0x580d, 0x03, 0, 0}, + {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, + {0x5811, 0x07, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, + {0x5814, 0x00, 0, 0}, {0x5815, 0x00, 0, 0}, {0x5816, 0x03, 0, 0}, + {0x5817, 0x07, 0, 0}, {0x5818, 0x0b, 0, 0}, {0x5819, 0x08, 0, 0}, + {0x581a, 0x05, 0, 0}, {0x581b, 0x05, 0, 0}, {0x581c, 0x07, 0, 0}, + {0x581d, 0x0b, 0, 0}, {0x581e, 0x2a, 0, 0}, {0x581f, 0x16, 0, 0}, + {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, + {0x5823, 0x29, 0, 0}, {0x5824, 0xbf, 0, 0}, {0x5825, 0xaf, 0, 0}, + {0x5826, 0x9f, 0, 0}, {0x5827, 0xaf, 0, 0}, {0x5828, 0xdf, 0, 0}, + {0x5829, 0x6f, 0, 0}, {0x582a, 0x8e, 0, 0}, {0x582b, 0xab, 0, 0}, + {0x582c, 0x9e, 0, 0}, {0x582d, 0x7f, 0, 0}, {0x582e, 0x4f, 0, 0}, + {0x582f, 0x89, 0, 0}, {0x5830, 0x86, 0, 0}, {0x5831, 0x98, 0, 0}, + {0x5832, 0x6f, 0, 0}, {0x5833, 0x4f, 0, 0}, {0x5834, 0x6e, 0, 0}, + {0x5835, 0x7b, 0, 0}, {0x5836, 0x7e, 0, 0}, {0x5837, 0x6f, 0, 0}, + {0x5838, 0xde, 0, 0}, {0x5839, 0xbf, 0, 0}, {0x583a, 0x9f, 0, 0}, + {0x583b, 0xbf, 0, 0}, {0x583c, 0xec, 0, 0}, {0x5025, 0x00, 0, 0}, + {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, + {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0}, + {0x3008, 0x02, 0, 0}, {0x3035, 0x21, 0, 0}, {0x3002, 0x1c, 0, 0}, + {0x3006, 0xc3, 0, 0}, {0x3821, 0x06, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x501f, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0}, + {0x460b, 0x37, 0, 0}, +}; + +static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = { + { + {ov5640_mode_VGA_640_480, 0, 0, NULL, 0}, + {ov5640_mode_QVGA_320_240, 0, 0, NULL, 0}, + {ov5640_mode_NTSC_720_480, 0, 0, NULL, 0}, + {ov5640_mode_PAL_720_576, 0, 0, NULL, 0}, + {ov5640_mode_720P_1280_720, 0, 0, NULL, 0}, + {ov5640_mode_1080P_1920_1080, 0, 0, NULL, 0}, + {ov5640_mode_QSXGA_2592_1944, 2592, 1944, + ov5640_setting_15fps_QSXGA_2592_1944, + ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)}, + }, + { + {ov5640_mode_VGA_640_480, 640, 480, + ov5640_setting_30fps_VGA_640_480, + ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)}, + {ov5640_mode_QVGA_320_240, 320, 240, + ov5640_setting_30fps_QVGA_320_240, + ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)}, + {ov5640_mode_NTSC_720_480, 720, 480, + ov5640_setting_30fps_NTSC_720_480, + ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)}, + {ov5640_mode_PAL_720_576, 720, 576, + ov5640_setting_30fps_PAL_720_576, + ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)}, + {ov5640_mode_720P_1280_720, 1280, 720, + ov5640_setting_30fps_720P_1280_720, + ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)}, + {ov5640_mode_1080P_1920_1080, 1920, 1080, + ov5640_setting_30fps_1080P_1920_1080, + ARRAY_SIZE(ov5640_setting_30fps_1080P_1920_1080)}, + {ov5640_mode_QSXGA_2592_1944, 0, 0, NULL, 0}, + }, +}; + +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; +static struct mxc_camera_platform_data *camera_plat; + +static int ov5640_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int ov5640_remove(struct i2c_client *client); + +static s32 ov5640_read_reg(u16 reg, u8 *val); +static s32 ov5640_write_reg(u16 reg, u8 val); + +static const struct i2c_device_id ov5640_id[] = { + {"ov5640", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov5640_id); + +static struct i2c_driver ov5640_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov5640", + }, + .probe = ov5640_probe, + .remove = ov5640_remove, + .id_table = ov5640_id, +}; + +extern void gpio_sensor_active(unsigned int csi_index); +extern void gpio_sensor_inactive(unsigned int csi); + +static s32 ov5640_write_reg(u16 reg, u8 val) +{ + u8 au8Buf[3] = {0}; + + au8Buf[0] = reg >> 8; + au8Buf[1] = reg & 0xff; + au8Buf[2] = val; + + if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) { + pr_err("%s:write reg error:reg=%x,val=%x\n", + __func__, reg, val); + return -1; + } + + return 0; +} + +static s32 ov5640_read_reg(u16 reg, u8 *val) +{ + u8 au8RegBuf[2] = {0}; + u8 u8RdVal = 0; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (2 != i2c_master_send(ov5640_data.i2c_client, au8RegBuf, 2)) { + pr_err("%s:write reg error:reg=%x\n", + __func__, reg); + return -1; + } + + if (1 != i2c_master_recv(ov5640_data.i2c_client, &u8RdVal, 1)) { + pr_err("%s:read reg error:reg=%x,val=%x\n", + __func__, reg, u8RdVal); + return -1; + } + + *val = u8RdVal; + + return u8RdVal; +} + +static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, + enum ov5640_mode mode) +{ + struct reg_value *pModeSetting = NULL; + s32 i = 0; + s32 iModeSettingArySize = 0; + register u32 Delay_ms = 0; + register u16 RegAddr = 0; + register u8 Mask = 0; + register u8 Val = 0; + u8 RegVal = 0; + int retval = 0; + + if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) { + pr_err("Wrong ov5640 mode detected!\n"); + return -1; + } + + pModeSetting = ov5640_mode_info_data[frame_rate][mode].init_data_ptr; + iModeSettingArySize = + ov5640_mode_info_data[frame_rate][mode].init_data_size; + + ov5640_data.pix.width = ov5640_mode_info_data[frame_rate][mode].width; + ov5640_data.pix.height = ov5640_mode_info_data[frame_rate][mode].height; + + if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 || + pModeSetting == NULL || iModeSettingArySize == 0) + return -EINVAL; + + for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) { + Delay_ms = pModeSetting->u32Delay_ms; + RegAddr = pModeSetting->u16RegAddr; + Val = pModeSetting->u8Val; + Mask = pModeSetting->u8Mask; + + if (Mask) { + retval = ov5640_read_reg(RegAddr, &RegVal); + if (retval < 0) + goto err; + + RegVal &= ~(u8)Mask; + Val &= Mask; + Val |= RegVal; + } + + retval = ov5640_write_reg(RegAddr, Val); + if (retval < 0) + goto err; + + if (Delay_ms) + msleep(Delay_ms); + } +err: + return retval; +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = ov5640_data.mclk; + pr_debug(" clock_curr=mclk=%d\n", ov5640_data.mclk); + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = OV5640_XCLK_MIN; + p->u.bt656.clock_max = OV5640_XCLK_MAX; + p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ + + return 0; +} + +/*! + * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + if (on && !sensor->on) { + gpio_sensor_active(ov5640_data.csi); + if (io_regulator) + if (regulator_enable(io_regulator) != 0) + return -EIO; + if (core_regulator) + if (regulator_enable(core_regulator) != 0) + return -EIO; + if (gpo_regulator) + if (regulator_enable(gpo_regulator) != 0) + return -EIO; + if (analog_regulator) + if (regulator_enable(analog_regulator) != 0) + return -EIO; + /* Make sure power on */ + if (camera_plat->pwdn) + camera_plat->pwdn(0); + + } else if (!on && sensor->on) { + if (analog_regulator) + regulator_disable(analog_regulator); + if (core_regulator) + regulator_disable(core_regulator); + if (io_regulator) + regulator_disable(io_regulator); + if (gpo_regulator) + regulator_disable(gpo_regulator); + gpio_sensor_inactive(ov5640_data.csi); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + enum ov5640_frame_rate frame_rate; + int ret = 0; + + /* Make sure power on */ + if (camera_plat->pwdn) + camera_plat->pwdn(0); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) || + (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + + /* Actual frame rate we use */ + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps == 15) + frame_rate = ov5640_15_fps; + else if (tgt_fps == 30) + frame_rate = ov5640_30_fps; + else { + pr_err(" The camera frame rate is not supported!\n"); + return -EINVAL; + } + + sensor->streamcap.timeperframe = *timeperframe; + sensor->streamcap.capturemode = + (u32)a->parm.capture.capturemode; + + ret = ov5640_init_mode(frame_rate, + sensor->streamcap.capturemode); + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not " \ + "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + f->fmt.pix = sensor->pix; + + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = ov5640_data.brightness; + break; + case V4L2_CID_HUE: + vc->value = ov5640_data.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = ov5640_data.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = ov5640_data.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = ov5640_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = ov5640_data.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = ov5640_data.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In ov5640:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + break; + case V4L2_CID_CONTRAST: + break; + case V4L2_CID_SATURATION: + break; + case V4L2_CID_HUE: + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + break; + case V4L2_CID_DO_WHITE_BALANCE: + break; + case V4L2_CID_RED_BALANCE: + break; + case V4L2_CID_BLUE_BALANCE: + break; + case V4L2_CID_GAMMA: + break; + case V4L2_CID_EXPOSURE: + break; + case V4L2_CID_AUTOGAIN: + break; + case V4L2_CID_GAIN: + break; + case V4L2_CID_HFLIP: + break; + case V4L2_CID_VFLIP: + break; + default: + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ioctl_enum_framesizes(struct v4l2_int_device *s, + struct v4l2_frmsizeenum *fsize) +{ + if (fsize->index > ov5640_mode_MAX) + return -EINVAL; + + fsize->pixel_format = ov5640_data.pix.pixelformat; + fsize->discrete.width = + max(ov5640_mode_info_data[0][fsize->index].width, + ov5640_mode_info_data[1][fsize->index].width); + fsize->discrete.height = + max(ov5640_mode_info_data[0][fsize->index].height, + ov5640_mode_info_data[1][fsize->index].height); + return 0; +} + +/*! + * ioctl_g_chip_ident - V4L2 sensor interface handler for + * VIDIOC_DBG_G_CHIP_IDENT ioctl + * @s: pointer to standard V4L2 device structure + * @id: pointer to int + * + * Return 0. + */ +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov5640_camera"); + + return 0; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + + return 0; +} + +/*! + * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT + * @s: pointer to standard V4L2 device structure + * @fmt: pointer to standard V4L2 fmt description structure + * + * Return 0. + */ +static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, + struct v4l2_fmtdesc *fmt) +{ + if (fmt->index > ov5640_mode_MAX) + return -EINVAL; + + fmt->pixelformat = ov5640_data.pix.pixelformat; + + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct sensor *sensor = s->priv; + u32 tgt_xclk; /* target xclk */ + u32 tgt_fps; /* target frames per secound */ + enum ov5640_frame_rate frame_rate; + + gpio_sensor_active(ov5640_data.csi); + ov5640_data.on = true; + + /* mclk */ + tgt_xclk = ov5640_data.mclk; + tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX); + tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN); + ov5640_data.mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); + set_mclk_rate(&ov5640_data.mclk, ov5640_data.csi); + + /* Default camera frame rate is set in probe */ + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 15) + frame_rate = ov5640_15_fps; + else if (tgt_fps == 30) + frame_rate = ov5640_30_fps; + else + return -EINVAL; /* Only support 15fps or 30fps now. */ + + return ov5640_init_mode(frame_rate, + sensor->streamcap.capturemode); +} + +/*! + * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num + * @s: pointer to standard V4L2 device structure + * + * Delinitialise the device when slave detaches to the master. + */ +static int ioctl_dev_exit(struct v4l2_int_device *s) +{ + gpio_sensor_inactive(ov5640_data.csi); + + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc ov5640_ioctl_desc[] = { + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, + {vidioc_int_dev_exit_num, ioctl_dev_exit}, + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init}, + {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, +/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */ + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl}, + {vidioc_int_enum_framesizes_num, + (v4l2_int_ioctl_func *)ioctl_enum_framesizes}, + {vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *)ioctl_g_chip_ident}, +}; + +static struct v4l2_int_slave ov5640_slave = { + .ioctls = ov5640_ioctl_desc, + .num_ioctls = ARRAY_SIZE(ov5640_ioctl_desc), +}; + +static struct v4l2_int_device ov5640_int_device = { + .module = THIS_MODULE, + .name = "ov5640", + .type = v4l2_int_type_slave, + .u = { + .slave = &ov5640_slave, + }, +}; + +/*! + * ov5640 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int ov5640_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + struct mxc_camera_platform_data *plat_data = client->dev.platform_data; + + /* Set initial values for the sensor struct. */ + memset(&ov5640_data, 0, sizeof(ov5640_data)); + ov5640_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ + ov5640_data.mclk = plat_data->mclk; + ov5640_data.csi = plat_data->csi; + + ov5640_data.i2c_client = client; + ov5640_data.pix.pixelformat = V4L2_PIX_FMT_YUYV; + ov5640_data.pix.width = 640; + ov5640_data.pix.height = 480; + ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + ov5640_data.streamcap.capturemode = 0; + ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; + ov5640_data.streamcap.timeperframe.numerator = 1; + + if (plat_data->io_regulator) { + io_regulator = regulator_get(&client->dev, + plat_data->io_regulator); + if (!IS_ERR(io_regulator)) { + regulator_set_voltage(io_regulator, + OV5640_VOLTAGE_DIGITAL_IO, + OV5640_VOLTAGE_DIGITAL_IO); + if (regulator_enable(io_regulator) != 0) { + pr_err("%s:io set voltage error\n", __func__); + goto err1; + } else { + dev_dbg(&client->dev, + "%s:io set voltage ok\n", __func__); + } + } else + io_regulator = NULL; + } + + if (plat_data->core_regulator) { + core_regulator = regulator_get(&client->dev, + plat_data->core_regulator); + if (!IS_ERR(core_regulator)) { + regulator_set_voltage(core_regulator, + OV5640_VOLTAGE_DIGITAL_CORE, + OV5640_VOLTAGE_DIGITAL_CORE); + if (regulator_enable(core_regulator) != 0) { + pr_err("%s:core set voltage error\n", __func__); + goto err2; + } else { + dev_dbg(&client->dev, + "%s:core set voltage ok\n", __func__); + } + } else + core_regulator = NULL; + } + + if (plat_data->analog_regulator) { + analog_regulator = regulator_get(&client->dev, + plat_data->analog_regulator); + if (!IS_ERR(analog_regulator)) { + regulator_set_voltage(analog_regulator, + OV5640_VOLTAGE_ANALOG, + OV5640_VOLTAGE_ANALOG); + if (regulator_enable(analog_regulator) != 0) { + pr_err("%s:analog set voltage error\n", + __func__); + goto err3; + } else { + dev_dbg(&client->dev, + "%s:analog set voltage ok\n", __func__); + } + } else + analog_regulator = NULL; + } + + if (plat_data->pwdn) + plat_data->pwdn(0); + + camera_plat = plat_data; + + ov5640_int_device.priv = &ov5640_data; + retval = v4l2_int_device_register(&ov5640_int_device); + + return retval; + +err3: + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } +err2: + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } +err1: + return -1; +} + +/*! + * ov5640 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int ov5640_remove(struct i2c_client *client) +{ + v4l2_int_device_unregister(&ov5640_int_device); + + if (gpo_regulator) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator); + } + + if (analog_regulator) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator); + } + + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } + + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } + + return 0; +} + +/*! + * ov5640 init function + * Called by insmod ov5640_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int ov5640_init(void) +{ + u8 err; + + err = i2c_add_driver(&ov5640_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * OV5640 cleanup function + * Called on rmmod ov5640_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit ov5640_clean(void) +{ + i2c_del_driver(&ov5640_i2c_driver); +} + +module_init(ov5640_init); +module_exit(ov5640_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OV5640 Camera Driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_ALIAS("CSI"); diff --git a/drivers/media/video/mxc/capture/ov5642.c b/drivers/media/video/mxc/capture/ov5642.c new file mode 100644 index 000000000000..ae184fdf57a5 --- /dev/null +++ b/drivers/media/video/mxc/capture/ov5642.c @@ -0,0 +1,2105 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_v4l2_capture.h" + +#define OV5642_VOLTAGE_ANALOG 2800000 +#define OV5642_VOLTAGE_DIGITAL_CORE 1500000 +#define OV5642_VOLTAGE_DIGITAL_IO 1800000 + +#define MIN_FPS 15 +#define MAX_FPS 30 +#define DEFAULT_FPS 30 + +#define OV5642_XCLK_MIN 6000000 +#define OV5642_XCLK_MAX 24000000 + +enum ov5642_mode { + ov5642_mode_MIN = 0, + ov5642_mode_VGA_640_480 = 0, + ov5642_mode_QVGA_320_240 = 1, + ov5642_mode_NTSC_720_480 = 2, + ov5642_mode_PAL_720_576 = 3, + ov5642_mode_720P_1280_720 = 4, + ov5642_mode_1080P_1920_1080 = 5, + ov5642_mode_QSXGA_2592_1944 = 6, + ov5642_mode_MAX = 6 +}; + +enum ov5642_frame_rate { + ov5642_15_fps, + ov5642_30_fps +}; + +struct reg_value { + u16 u16RegAddr; + u8 u8Val; + u8 u8Mask; + u32 u32Delay_ms; +}; + +struct ov5642_mode_info { + enum ov5642_mode mode; + u32 width; + u32 height; + struct reg_value *init_data_ptr; + u32 init_data_size; +}; + +/*! + * Maintains the information on the current state of the sesor. + */ +struct sensor { + const struct ov5642_platform_data *platform_data; + struct v4l2_int_device *v4l2_int_device; + struct i2c_client *i2c_client; + struct v4l2_pix_format pix; + struct v4l2_captureparm streamcap; + bool on; + + /* control settings */ + int brightness; + int hue; + int contrast; + int saturation; + int red; + int green; + int blue; + int ae_mode; + + u32 mclk; + int csi; +} ov5642_data; + +static struct reg_value ov5642_setting_15fps_QSXGA_2592_1944[] = { + {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, + {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, + {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0}, + {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0}, + {0x3011, 0x08, 0, 0}, {0x3010, 0x00, 0, 0}, {0x3604, 0x60, 0, 0}, + {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0}, + {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, + {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, + {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0}, + {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, + {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0}, + {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, + {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, + {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0}, + {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, + {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0}, + {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0}, + {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0}, + {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0}, + {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0}, + {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0}, + {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0}, + {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, + {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, + {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0}, + {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, + {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0}, + {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0}, + {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, + {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, + {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, + {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0}, + {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0}, + {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, + {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0}, + {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, + {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, + {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, + {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, + {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, + {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, + {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, + {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, + {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, + {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, + {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, + {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, + {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, + {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, + {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, + {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, + {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, + {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, + {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, + {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, + {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, + {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, + {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, + {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, + {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, + {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, + {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, + {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, + {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, + {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, + {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, + {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, + {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, + {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, + {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, + {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, + {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, + {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, + {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, + {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, + {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, + {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, + {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, + {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, + {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, + {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, + {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, + {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, + {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, + {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, + {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, + {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, + {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, + {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, + {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, + {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, + {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, + {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, + {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, + {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, + {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, + {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, + {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, + {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, + {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, + {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, + {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, + {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, + {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, + {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, + {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, + {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, + {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, + {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, + {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, + {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, + {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, + {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, + {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, + {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, + {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, + {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, + {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, + {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, + {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, + {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, + {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, + {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, + {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, + {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, + {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, + {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, + {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, + {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, + {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, + {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, + {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, + {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, + {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, + {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, + {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, + {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, + {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, + {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, + {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, + {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, + {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, + {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, + {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, + {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, + {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, + {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, + {0x302b, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x460b, 0x37, 0, 0}, + {0x471c, 0xd0, 0, 0}, {0x471d, 0x05, 0, 0}, {0x3815, 0x01, 0, 0}, + {0x3818, 0xc0, 0, 0}, {0x501f, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x3002, 0x1c, 0, 0}, {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0}, + {0x3012, 0x01, 0, 0}, +}; + +static struct reg_value ov5642_setting_30fps_VGA_640_480[] = { + {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, + {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, + {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, + {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, + {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, + {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, + {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, + {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, + {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, + {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, + {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, + {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, + {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, + {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, + {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, + {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, + {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, + {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, + {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, + {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, + {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, + {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, + {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, + {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, + {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0}, + {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, + {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, + {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, + {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, + {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, + {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, + {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, + {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, + {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, + {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, + {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, + {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, + {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, + {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, + {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, + {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, + {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, + {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, + {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, + {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, + {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, + {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, + {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, + {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, + {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, + {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, + {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, + {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, + {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, + {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, + {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, + {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, + {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, + {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, + {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, + {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, + {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, + {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, + {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, + {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, + {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, + {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, + {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, + {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, + {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, + {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, + {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, + {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, + {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, + {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, + {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, + {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, + {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, + {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, + {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, + {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, + {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, + {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, + {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, + {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, + {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, + {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, + {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, + {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, + {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, + {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, + {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, + {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, + {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, + {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, + {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, + {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, + {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, + {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, + {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, + {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, + {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, + {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, + {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, + {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, + {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, + {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, + {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, + {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, + {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, + {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, + {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, + {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, + {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, + {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, + {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, + {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, + {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, + {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, + {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, + {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, + {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, + {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, + {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, + {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, + {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, + {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, + {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, + {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, + {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, + {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, + {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, + {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, + {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, + {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, + {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, + {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, + {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, + {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, + {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, + {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, + {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, + {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, + {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, + {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, + {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, + {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, + {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, + {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, + {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, + {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, + {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, + {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, + {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, + {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, + {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, + {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, + {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, +}; + +static struct reg_value ov5642_setting_30fps_QVGA_320_240[] = { + {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, + {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, + {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, + {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, + {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, + {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, + {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, + {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, + {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, + {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, + {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, + {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, + {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, + {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, + {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, + {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, + {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, + {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, + {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, + {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, + {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, + {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, + {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, + {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, + {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0}, + {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, + {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, + {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, + {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, + {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, + {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, + {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, + {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, + {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, + {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, + {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, + {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, + {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, + {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, + {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, + {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, + {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, + {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, + {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, + {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, + {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, + {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, + {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, + {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, + {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, + {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, + {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, + {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, + {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, + {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, + {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, + {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, + {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, + {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, + {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, + {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, + {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, + {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, + {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, + {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, + {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, + {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, + {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, + {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, + {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, + {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, + {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, + {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, + {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, + {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, + {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, + {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, + {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, + {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, + {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, + {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, + {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, + {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, + {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, + {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, + {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, + {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, + {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, + {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, + {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, + {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, + {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, + {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, + {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, + {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, + {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, + {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, + {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, + {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, + {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, + {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, + {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, + {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, + {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, + {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, + {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, + {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, + {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, + {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, + {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, + {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, + {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, + {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, + {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, + {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, + {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, + {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, + {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, + {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, + {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, + {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, + {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, + {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, + {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, + {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, + {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, + {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, + {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, + {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, + {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, + {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, + {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, + {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, + {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, + {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, + {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, + {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, + {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, + {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, + {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, + {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, + {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, + {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, + {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, + {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, + {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, + {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, + {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, + {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, + {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, + {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, + {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, + {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, + {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, + {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, + {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, + {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, + {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3808, 0x01, 0, 0}, + {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, +}; + +static struct reg_value ov5642_setting_30fps_NTSC_720_480[] = { + {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, + {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, + {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, + {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, + {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, + {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, + {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, + {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, + {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, + {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, + {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, + {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, + {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, + {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, + {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, + {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, + {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, + {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, + {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, + {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, + {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, + {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, + {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, + {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, + {0x3803, 0x08, 0, 0}, {0x3827, 0x3c, 0, 0}, {0x3810, 0x80, 0, 0}, + {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, + {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0x58, 0, 0}, + {0x5686, 0x03, 0, 0}, {0x5687, 0x58, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, + {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, + {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, + {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, + {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, + {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, + {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, + {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, + {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, + {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, + {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, + {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, + {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, + {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, + {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, + {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, + {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, + {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, + {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, + {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, + {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, + {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, + {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, + {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, + {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, + {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, + {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, + {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, + {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, + {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, + {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, + {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, + {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, + {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, + {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, + {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, + {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, + {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, + {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, + {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, + {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, + {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, + {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, + {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, + {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, + {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, + {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, + {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, + {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, + {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, + {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, + {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, + {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, + {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, + {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, + {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, + {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, + {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, + {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, + {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, + {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, + {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, + {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, + {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, + {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, + {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, + {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, + {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, + {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, + {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, + {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, + {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, + {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, + {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, + {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, + {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, + {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, + {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, + {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, + {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, + {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, + {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, + {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, + {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, + {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, + {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, + {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, + {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, + {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, + {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, + {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, + {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, + {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, + {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, + {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, + {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, + {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, + {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, + {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, + {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, + {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, + {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, + {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, + {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, + {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, + {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, + {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, + {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, + {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, + {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, + {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, + {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, + {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, + {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, + {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, + {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, + {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, + {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, + {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, + {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, + {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, + {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, + {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, + {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, + {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, + {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, + {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, + {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, + {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, + {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, + {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, +}; + +static struct reg_value ov5642_setting_30fps_PAL_720_576[] = { + {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, + {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, + {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, + {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, + {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, + {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, + {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, + {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, + {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, + {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, + {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, + {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, + {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, + {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, + {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, + {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, + {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, + {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, + {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, + {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, + {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xd8, 0, 0}, + {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, + {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, + {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, + {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, + {0x3803, 0x08, 0, 0}, {0x3827, 0x3c, 0, 0}, {0x3810, 0x80, 0, 0}, + {0x3804, 0x04, 0, 0}, {0x3805, 0xb0, 0, 0}, {0x5682, 0x05, 0, 0}, + {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0x58, 0, 0}, + {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, + {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, + {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, + {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, + {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, + {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, + {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, + {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, + {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, + {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, + {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, + {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, + {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, + {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, + {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, + {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, + {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, + {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, + {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, + {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, + {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, + {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, + {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, + {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, + {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, + {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, + {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, + {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, + {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, + {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, + {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, + {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, + {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, + {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, + {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, + {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, + {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, + {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, + {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, + {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, + {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, + {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, + {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, + {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, + {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, + {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, + {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, + {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, + {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, + {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, + {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, + {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, + {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, + {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, + {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, + {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, + {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, + {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, + {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, + {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, + {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, + {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, + {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, + {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, + {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, + {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, + {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, + {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, + {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, + {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, + {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, + {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, + {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, + {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, + {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, + {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, + {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, + {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, + {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, + {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, + {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, + {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, + {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, + {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, + {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, + {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, + {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, + {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, + {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, + {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, + {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, + {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, + {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, + {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, + {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, + {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, + {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, + {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, + {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, + {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, + {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, + {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, + {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, + {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, + {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, + {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, + {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, + {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, + {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, + {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, + {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, + {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, + {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, + {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, + {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, + {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, + {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, + {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, + {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, + {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, + {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, + {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, + {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, + {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, + {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, + {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, + {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, + {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, + {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, + {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, + {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, + {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, +}; + +static struct reg_value ov5642_setting_30fps_720P_1280_720[] = { + {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, + {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, + {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0}, + {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0}, + {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0}, + {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0}, + {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, + {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, + {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0}, + {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, + {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0}, + {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, + {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, + {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0}, + {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, + {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0}, + {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0}, + {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0}, + {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0}, + {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0}, + {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0}, + {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0}, + {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, + {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, + {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0}, + {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, + {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0}, + {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0}, + {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, + {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, + {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, + {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0}, + {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0}, + {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, + {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0}, + {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, + {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, + {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, + {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, + {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, + {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, + {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, + {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, + {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, + {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, + {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, + {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, + {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, + {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, + {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, + {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, + {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, + {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, + {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, + {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, + {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, + {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, + {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, + {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, + {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, + {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, + {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, + {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, + {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, + {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, + {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, + {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, + {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, + {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, + {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, + {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, + {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, + {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, + {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, + {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, + {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, + {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, + {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, + {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, + {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, + {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, + {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, + {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, + {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, + {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, + {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, + {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, + {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, + {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, + {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, + {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, + {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, + {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, + {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, + {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, + {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, + {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, + {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, + {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, + {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, + {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, + {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, + {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, + {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, + {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, + {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, + {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, + {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, + {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, + {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, + {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, + {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, + {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, + {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, + {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, + {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, + {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, + {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, + {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, + {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, + {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, + {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, + {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, + {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, + {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, + {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, + {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, + {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, + {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, + {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, + {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, + {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, + {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, + {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, + {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, + {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, + {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, + {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, + {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, + {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, + {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, + {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, + {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, + {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, + {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, + {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, + {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, + {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x08, 0, 0}, + {0x350c, 0x02, 0, 0}, {0x350d, 0xe4, 0, 0}, {0x3621, 0xc9, 0, 0}, + {0x370a, 0x81, 0, 0}, {0x3803, 0x08, 0, 0}, {0x3804, 0x05, 0, 0}, + {0x3805, 0x00, 0, 0}, {0x3806, 0x02, 0, 0}, {0x3807, 0xd0, 0, 0}, + {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, + {0x380b, 0xd0, 0, 0}, {0x380c, 0x08, 0, 0}, {0x380d, 0x72, 0, 0}, + {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0xc0, 0, 0}, + {0x3818, 0xc9, 0, 0}, {0x381c, 0x10, 0, 0}, {0x381d, 0xa0, 0, 0}, + {0x381e, 0x05, 0, 0}, {0x381f, 0xb0, 0, 0}, {0x3820, 0x00, 0, 0}, + {0x3821, 0x00, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3a08, 0x1b, 0, 0}, + {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x17, 0, 0}, {0x3a0b, 0x20, 0, 0}, + {0x3a0d, 0x02, 0, 0}, {0x3a0e, 0x01, 0, 0}, {0x401c, 0x04, 0, 0}, + {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, {0x5686, 0x02, 0, 0}, + {0x5687, 0xcc, 0, 0}, {0x5001, 0x7f, 0, 0}, {0x589b, 0x06, 0, 0}, + {0x589a, 0xc5, 0, 0}, {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0}, + {0x460c, 0x20, 0, 0}, {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0}, + {0x471d, 0x05, 0, 0}, {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0}, + {0x501f, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0}, + {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0}, +}; + +static struct reg_value ov5642_setting_30fps_1080P_1920_1080[] = { + {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, + {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, + {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0}, + {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0}, + {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0}, + {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0}, + {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, + {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, + {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0}, + {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, + {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0}, + {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, + {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, + {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0}, + {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, + {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0}, + {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0}, + {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0}, + {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0}, + {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, + {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0}, + {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0}, + {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0}, + {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0}, + {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, + {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, + {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0}, + {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, + {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, + {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0}, + {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0}, + {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, + {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, + {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, + {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, + {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0}, + {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0}, + {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, + {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0}, + {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, + {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, + {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, + {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, + {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, + {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, + {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, + {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, + {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, + {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, + {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, + {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, + {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, + {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, + {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, + {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, + {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, + {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, + {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, + {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, + {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, + {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, + {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, + {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, + {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, + {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, + {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, + {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, + {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, + {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, + {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, + {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, + {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, + {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, + {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, + {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, + {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, + {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, + {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, + {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, + {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, + {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, + {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, + {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, + {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, + {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, + {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, + {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, + {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, + {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, + {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, + {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, + {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, + {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, + {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, + {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, + {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, + {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, + {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, + {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, + {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, + {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, + {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, + {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, + {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, + {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, + {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, + {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, + {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, + {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, + {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, + {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, + {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, + {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, + {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, + {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, + {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, + {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, + {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, + {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, + {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, + {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, + {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, + {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, + {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, + {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, + {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, + {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, + {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, + {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, + {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, + {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, + {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, + {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, + {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, + {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, + {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, + {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, + {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, + {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, + {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, + {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, + {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, + {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, + {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, + {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, + {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, + {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, + {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, + {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, + {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, + {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, + {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, + {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x07, 0, 0}, + {0x350c, 0x04, 0, 0}, {0x350d, 0x58, 0, 0}, {0x3801, 0x8a, 0, 0}, + {0x3803, 0x0a, 0, 0}, {0x3804, 0x07, 0, 0}, {0x3805, 0x80, 0, 0}, + {0x3806, 0x04, 0, 0}, {0x3807, 0x38, 0, 0}, {0x3808, 0x07, 0, 0}, + {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, + {0x380c, 0x09, 0, 0}, {0x380d, 0xd6, 0, 0}, {0x380e, 0x04, 0, 0}, + {0x380f, 0x58, 0, 0}, {0x381c, 0x11, 0, 0}, {0x381d, 0xba, 0, 0}, + {0x381e, 0x04, 0, 0}, {0x381f, 0x48, 0, 0}, {0x3820, 0x04, 0, 0}, + {0x3821, 0x18, 0, 0}, {0x3a08, 0x14, 0, 0}, {0x3a09, 0xe0, 0, 0}, + {0x3a0a, 0x11, 0, 0}, {0x3a0b, 0x60, 0, 0}, {0x3a0d, 0x04, 0, 0}, + {0x3a0e, 0x03, 0, 0}, {0x5682, 0x07, 0, 0}, {0x5683, 0x60, 0, 0}, + {0x5686, 0x04, 0, 0}, {0x5687, 0x1c, 0, 0}, {0x5001, 0x7f, 0, 0}, + {0x3503, 0x00, 0, 0}, {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, + {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0}, {0x471d, 0x05, 0, 0}, + {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0}, {0x501f, 0x00, 0, 0}, + {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3819, 0x80, 0, 0}, + {0x5002, 0xe0, 0, 0}, +}; + +static struct ov5642_mode_info ov5642_mode_info_data[2][ov5642_mode_MAX + 1] = { + { + {ov5642_mode_VGA_640_480, 0, 0, NULL, 0}, + {ov5642_mode_QVGA_320_240, 0, 0, NULL, 0}, + {ov5642_mode_NTSC_720_480, 0, 0, NULL, 0}, + {ov5642_mode_PAL_720_576, 0, 0, NULL, 0}, + {ov5642_mode_720P_1280_720, 0, 0, NULL, 0}, + {ov5642_mode_1080P_1920_1080, 0, 0, NULL, 0}, + {ov5642_mode_QSXGA_2592_1944, 2592, 1944, + ov5642_setting_15fps_QSXGA_2592_1944, + ARRAY_SIZE(ov5642_setting_15fps_QSXGA_2592_1944)}, + }, + { + {ov5642_mode_VGA_640_480, 640, 480, + ov5642_setting_30fps_VGA_640_480, + ARRAY_SIZE(ov5642_setting_30fps_VGA_640_480)}, + {ov5642_mode_QVGA_320_240, 320, 240, + ov5642_setting_30fps_QVGA_320_240, + ARRAY_SIZE(ov5642_setting_30fps_QVGA_320_240)}, + {ov5642_mode_NTSC_720_480, 720, 480, + ov5642_setting_30fps_NTSC_720_480, + ARRAY_SIZE(ov5642_setting_30fps_NTSC_720_480)}, + {ov5642_mode_PAL_720_576, 720, 576, + ov5642_setting_30fps_PAL_720_576, + ARRAY_SIZE(ov5642_setting_30fps_PAL_720_576)}, + {ov5642_mode_720P_1280_720, 1280, 720, + ov5642_setting_30fps_720P_1280_720, + ARRAY_SIZE(ov5642_setting_30fps_720P_1280_720)}, + {ov5642_mode_1080P_1920_1080, 1920, 1080, + ov5642_setting_30fps_1080P_1920_1080, + ARRAY_SIZE(ov5642_setting_30fps_1080P_1920_1080)}, + {ov5642_mode_QSXGA_2592_1944, 0, 0, NULL, 0}, + }, +}; + +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; +static struct mxc_camera_platform_data *camera_plat; + +static int ov5642_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int ov5642_remove(struct i2c_client *client); + +static s32 ov5642_read_reg(u16 reg, u8 *val); +static s32 ov5642_write_reg(u16 reg, u8 val); + +static const struct i2c_device_id ov5642_id[] = { + {"ov5642", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ov5642_id); + +static struct i2c_driver ov5642_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ov5642", + }, + .probe = ov5642_probe, + .remove = ov5642_remove, + .id_table = ov5642_id, +}; + +extern void gpio_sensor_active(unsigned int csi_index); +extern void gpio_sensor_inactive(unsigned int csi); + +static s32 ov5642_write_reg(u16 reg, u8 val) +{ + u8 au8Buf[3] = {0}; + + au8Buf[0] = reg >> 8; + au8Buf[1] = reg & 0xff; + au8Buf[2] = val; + + if (i2c_master_send(ov5642_data.i2c_client, au8Buf, 3) < 0) { + pr_err("%s:write reg error:reg=%x,val=%x\n", + __func__, reg, val); + return -1; + } + + return 0; +} + +static s32 ov5642_read_reg(u16 reg, u8 *val) +{ + u8 au8RegBuf[2] = {0}; + u8 u8RdVal = 0; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (2 != i2c_master_send(ov5642_data.i2c_client, au8RegBuf, 2)) { + pr_err("%s:write reg error:reg=%x\n", + __func__, reg); + return -1; + } + + if (1 != i2c_master_recv(ov5642_data.i2c_client, &u8RdVal, 1)) { + pr_err("%s:read reg error:reg=%x,val=%x\n", + __func__, reg, u8RdVal); + return -1; + } + + *val = u8RdVal; + + return u8RdVal; +} + +static int ov5642_init_mode(enum ov5642_frame_rate frame_rate, + enum ov5642_mode mode) +{ + struct reg_value *pModeSetting = NULL; + s32 i = 0; + s32 iModeSettingArySize = 0; + register u32 Delay_ms = 0; + register u16 RegAddr = 0; + register u8 Mask = 0; + register u8 Val = 0; + u8 RegVal = 0; + int retval = 0; + + if (mode > ov5642_mode_MAX || mode < ov5642_mode_MIN) { + pr_err("Wrong ov5642 mode detected!\n"); + return -1; + } + + pModeSetting = ov5642_mode_info_data[frame_rate][mode].init_data_ptr; + iModeSettingArySize = + ov5642_mode_info_data[frame_rate][mode].init_data_size; + + ov5642_data.pix.width = ov5642_mode_info_data[frame_rate][mode].width; + ov5642_data.pix.height = ov5642_mode_info_data[frame_rate][mode].height; + + if (ov5642_data.pix.width == 0 || ov5642_data.pix.height == 0 || + pModeSetting == NULL || iModeSettingArySize == 0) + return -EINVAL; + + for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) { + Delay_ms = pModeSetting->u32Delay_ms; + RegAddr = pModeSetting->u16RegAddr; + Val = pModeSetting->u8Val; + Mask = pModeSetting->u8Mask; + + if (Mask) { + retval = ov5642_read_reg(RegAddr, &RegVal); + if (retval < 0) + goto err; + + RegVal &= ~(u8)Mask; + Val &= Mask; + Val |= RegVal; + } + + retval = ov5642_write_reg(RegAddr, Val); + if (retval < 0) + goto err; + + if (Delay_ms) + msleep(Delay_ms); + } +err: + return retval; +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = ov5642_data.mclk; + pr_debug(" clock_curr=mclk=%d\n", ov5642_data.mclk); + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = OV5642_XCLK_MIN; + p->u.bt656.clock_max = OV5642_XCLK_MAX; + p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ + + return 0; +} + +/*! + * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + if (on && !sensor->on) { + gpio_sensor_active(ov5642_data.csi); + if (io_regulator) + if (regulator_enable(io_regulator) != 0) + return -EIO; + if (core_regulator) + if (regulator_enable(core_regulator) != 0) + return -EIO; + if (gpo_regulator) + if (regulator_enable(gpo_regulator) != 0) + return -EIO; + if (analog_regulator) + if (regulator_enable(analog_regulator) != 0) + return -EIO; + /* Make sure power on */ + if (camera_plat->pwdn) + camera_plat->pwdn(0); + + } else if (!on && sensor->on) { + if (analog_regulator) + regulator_disable(analog_regulator); + if (core_regulator) + regulator_disable(core_regulator); + if (io_regulator) + regulator_disable(io_regulator); + if (gpo_regulator) + regulator_disable(gpo_regulator); + gpio_sensor_inactive(ov5642_data.csi); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + enum ov5642_frame_rate frame_rate; + int ret = 0; + + /* Make sure power on */ + if (camera_plat->pwdn) + camera_plat->pwdn(0); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) || + (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + + /* Actual frame rate we use */ + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps == 15) + frame_rate = ov5642_15_fps; + else if (tgt_fps == 30) + frame_rate = ov5642_30_fps; + else { + pr_err(" The camera frame rate is not supported!\n"); + return -EINVAL; + } + + sensor->streamcap.timeperframe = *timeperframe; + sensor->streamcap.capturemode = + (u32)a->parm.capture.capturemode; + + ret = ov5642_init_mode(frame_rate, + sensor->streamcap.capturemode); + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not " \ + "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + f->fmt.pix = sensor->pix; + + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = ov5642_data.brightness; + break; + case V4L2_CID_HUE: + vc->value = ov5642_data.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = ov5642_data.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = ov5642_data.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = ov5642_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = ov5642_data.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = ov5642_data.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In ov5642:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + break; + case V4L2_CID_CONTRAST: + break; + case V4L2_CID_SATURATION: + break; + case V4L2_CID_HUE: + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + break; + case V4L2_CID_DO_WHITE_BALANCE: + break; + case V4L2_CID_RED_BALANCE: + break; + case V4L2_CID_BLUE_BALANCE: + break; + case V4L2_CID_GAMMA: + break; + case V4L2_CID_EXPOSURE: + break; + case V4L2_CID_AUTOGAIN: + break; + case V4L2_CID_GAIN: + break; + case V4L2_CID_HFLIP: + break; + case V4L2_CID_VFLIP: + break; + default: + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ioctl_enum_framesizes(struct v4l2_int_device *s, + struct v4l2_frmsizeenum *fsize) +{ + if (fsize->index > ov5642_mode_MAX) + return -EINVAL; + + fsize->pixel_format = ov5642_data.pix.pixelformat; + fsize->discrete.width = + max(ov5642_mode_info_data[0][fsize->index].width, + ov5642_mode_info_data[1][fsize->index].width); + fsize->discrete.height = + max(ov5642_mode_info_data[0][fsize->index].height, + ov5642_mode_info_data[1][fsize->index].height); + return 0; +} + +/*! + * ioctl_g_chip_ident - V4L2 sensor interface handler for + * VIDIOC_DBG_G_CHIP_IDENT ioctl + * @s: pointer to standard V4L2 device structure + * @id: pointer to int + * + * Return 0. + */ +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov5642_camera"); + + return 0; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + + return 0; +} + +/*! + * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT + * @s: pointer to standard V4L2 device structure + * @fmt: pointer to standard V4L2 fmt description structure + * + * Return 0. + */ +static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, + struct v4l2_fmtdesc *fmt) +{ + if (fmt->index > ov5642_mode_MAX) + return -EINVAL; + + fmt->pixelformat = ov5642_data.pix.pixelformat; + + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct sensor *sensor = s->priv; + u32 tgt_xclk; /* target xclk */ + u32 tgt_fps; /* target frames per secound */ + enum ov5642_frame_rate frame_rate; + + gpio_sensor_active(ov5642_data.csi); + ov5642_data.on = true; + + /* mclk */ + tgt_xclk = ov5642_data.mclk; + tgt_xclk = min(tgt_xclk, (u32)OV5642_XCLK_MAX); + tgt_xclk = max(tgt_xclk, (u32)OV5642_XCLK_MIN); + ov5642_data.mclk = tgt_xclk; + + pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); + set_mclk_rate(&ov5642_data.mclk, ov5642_data.csi); + + /* Default camera frame rate is set in probe */ + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 15) + frame_rate = ov5642_15_fps; + else if (tgt_fps == 30) + frame_rate = ov5642_30_fps; + else + return -EINVAL; /* Only support 15fps or 30fps now. */ + + return ov5642_init_mode(frame_rate, + sensor->streamcap.capturemode); +} + +/*! + * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num + * @s: pointer to standard V4L2 device structure + * + * Delinitialise the device when slave detaches to the master. + */ +static int ioctl_dev_exit(struct v4l2_int_device *s) +{ + gpio_sensor_inactive(ov5642_data.csi); + + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc ov5642_ioctl_desc[] = { + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, + {vidioc_int_dev_exit_num, ioctl_dev_exit}, + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init}, + {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, +/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */ + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl}, + {vidioc_int_enum_framesizes_num, + (v4l2_int_ioctl_func *)ioctl_enum_framesizes}, + {vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *)ioctl_g_chip_ident}, +}; + +static struct v4l2_int_slave ov5642_slave = { + .ioctls = ov5642_ioctl_desc, + .num_ioctls = ARRAY_SIZE(ov5642_ioctl_desc), +}; + +static struct v4l2_int_device ov5642_int_device = { + .module = THIS_MODULE, + .name = "ov5642", + .type = v4l2_int_type_slave, + .u = { + .slave = &ov5642_slave, + }, +}; + +/*! + * ov5642 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +static int ov5642_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + struct mxc_camera_platform_data *plat_data = client->dev.platform_data; + + /* Set initial values for the sensor struct. */ + memset(&ov5642_data, 0, sizeof(ov5642_data)); + ov5642_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ + ov5642_data.mclk = plat_data->mclk; + ov5642_data.csi = plat_data->csi; + + ov5642_data.i2c_client = client; + ov5642_data.pix.pixelformat = V4L2_PIX_FMT_YUYV; + ov5642_data.pix.width = 640; + ov5642_data.pix.height = 480; + ov5642_data.streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + ov5642_data.streamcap.capturemode = 0; + ov5642_data.streamcap.timeperframe.denominator = DEFAULT_FPS; + ov5642_data.streamcap.timeperframe.numerator = 1; + + if (plat_data->io_regulator) { + io_regulator = regulator_get(&client->dev, + plat_data->io_regulator); + if (!IS_ERR(io_regulator)) { + regulator_set_voltage(io_regulator, + OV5642_VOLTAGE_DIGITAL_IO, + OV5642_VOLTAGE_DIGITAL_IO); + if (regulator_enable(io_regulator) != 0) { + pr_err("%s:io set voltage error\n", __func__); + goto err1; + } else { + dev_dbg(&client->dev, + "%s:io set voltage ok\n", __func__); + } + } else + io_regulator = NULL; + } + + if (plat_data->core_regulator) { + core_regulator = regulator_get(&client->dev, + plat_data->core_regulator); + if (!IS_ERR(core_regulator)) { + regulator_set_voltage(core_regulator, + OV5642_VOLTAGE_DIGITAL_CORE, + OV5642_VOLTAGE_DIGITAL_CORE); + if (regulator_enable(core_regulator) != 0) { + pr_err("%s:core set voltage error\n", __func__); + goto err2; + } else { + dev_dbg(&client->dev, + "%s:core set voltage ok\n", __func__); + } + } else + core_regulator = NULL; + } + + if (plat_data->analog_regulator) { + analog_regulator = regulator_get(&client->dev, + plat_data->analog_regulator); + if (!IS_ERR(analog_regulator)) { + regulator_set_voltage(analog_regulator, + OV5642_VOLTAGE_ANALOG, + OV5642_VOLTAGE_ANALOG); + if (regulator_enable(analog_regulator) != 0) { + pr_err("%s:analog set voltage error\n", + __func__); + goto err3; + } else { + dev_dbg(&client->dev, + "%s:analog set voltage ok\n", __func__); + } + } else + analog_regulator = NULL; + } + + if (plat_data->pwdn) + plat_data->pwdn(0); + + camera_plat = plat_data; + + ov5642_int_device.priv = &ov5642_data; + retval = v4l2_int_device_register(&ov5642_int_device); + + return retval; + +err3: + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } +err2: + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } +err1: + return -1; +} + +/*! + * ov5642 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int ov5642_remove(struct i2c_client *client) +{ + v4l2_int_device_unregister(&ov5642_int_device); + + if (gpo_regulator) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator); + } + + if (analog_regulator) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator); + } + + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } + + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } + + return 0; +} + +/*! + * ov5642 init function + * Called by insmod ov5642_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int ov5642_init(void) +{ + u8 err; + + err = i2c_add_driver(&ov5642_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d \n", + __func__, err); + + return err; +} + +/*! + * OV5642 cleanup function + * Called on rmmod ov5642_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit ov5642_clean(void) +{ + i2c_del_driver(&ov5642_i2c_driver); +} + +module_init(ov5642_init); +module_exit(ov5642_clean); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OV5642 Camera Driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_ALIAS("CSI"); diff --git a/drivers/media/video/mxc/capture/sensor_clock.c b/drivers/media/video/mxc/capture/sensor_clock.c new file mode 100644 index 000000000000..643919a45fbd --- /dev/null +++ b/drivers/media/video/mxc/capture/sensor_clock.c @@ -0,0 +1,97 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sensor_clock.c + * + * @brief camera clock function + * + * @ingroup Camera + */ +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_MXC_IPU_V1) || defined(CONFIG_VIDEO_MXC_EMMA_CAMERA) \ + || defined(CONFIG_VIDEO_MXC_CSI_CAMERA_MODULE) \ + || defined(CONFIG_VIDEO_MXC_CSI_CAMERA) +/* + * set_mclk_rate + * + * @param p_mclk_freq mclk frequence + * + */ +void set_mclk_rate(uint32_t *p_mclk_freq) +{ + struct clk *clk; + uint32_t freq = 0; + + clk = clk_get(NULL, "csi_clk"); + + freq = clk_round_rate(clk, *p_mclk_freq); + clk_set_rate(clk, freq); + + *p_mclk_freq = freq; + + clk_put(clk); + pr_debug("mclk frequency = %d\n", *p_mclk_freq); +} +#else +/* + * set_mclk_rate + * + * @param p_mclk_freq mclk frequence + * @param csi csi 0 or csi 1 + * + */ +void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi) +{ + struct clk *clk; + uint32_t freq = 0; + char *mclk; + + if (cpu_is_mx53()) { + if (csi == 0) + mclk = "ssi_ext1_clk"; + else { + pr_err("invalid csi num %d\n", csi); + return; + } + } else { + if (csi == 0) { + mclk = "csi_mclk1"; + } else if (csi == 1) { + mclk = "csi_mclk2"; + } else { + pr_err("invalid csi num %d\n", csi); + return; + } + } + + clk = clk_get(NULL, mclk); + + freq = clk_round_rate(clk, *p_mclk_freq); + clk_set_rate(clk, freq); + + *p_mclk_freq = freq; + + clk_put(clk); + pr_debug("%s frequency = %d\n", mclk, *p_mclk_freq); +} +#endif + +/* Exported symbols for modules. */ +EXPORT_SYMBOL(set_mclk_rate); diff --git a/drivers/media/video/mxc/opl/Makefile b/drivers/media/video/mxc/opl/Makefile new file mode 100644 index 000000000000..092a62c5ac4a --- /dev/null +++ b/drivers/media/video/mxc/opl/Makefile @@ -0,0 +1,5 @@ +opl-objs := opl_mod.o rotate90_u16.o rotate270_u16.o \ + rotate90_u16_qcif.o rotate270_u16_qcif.o \ + vmirror_u16.o hmirror_rotate180_u16.o + +obj-$(CONFIG_VIDEO_MXC_OPL) += opl.o diff --git a/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c b/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c new file mode 100644 index 000000000000..6737f3a54d46 --- /dev/null +++ b/drivers/media/video/mxc/opl/hmirror_rotate180_u16.c @@ -0,0 +1,259 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include "opl.h" + +static inline u32 rot_left_u16(u16 x, unsigned int n) +{ + return (x << n) | (x >> (16 - n)); +} + +static inline u32 rot_left_u32(u32 x, unsigned int n) +{ + return (x << n) | (x >> (32 - n)); +} + +static inline u32 byte_swap_u32(u32 x) +{ + u32 t1, t2, t3; + + t1 = x ^ ((x << 16) | x >> 16); + t2 = t1 & 0xff00ffff; + t3 = (x >> 8) | (x << 24); + return t3 ^ (t2 >> 8); +} + +static int opl_hmirror_u16_by1(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror); +static int opl_hmirror_u16_by2(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror); +static int opl_hmirror_u16_by4(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror); +static int opl_hmirror_u16_by8(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror); + +int opl_hmirror_u16(const u8 *src, int src_line_stride, int width, int height, + u8 *dst, int dst_line_stride) +{ + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + if (width % 8 == 0) + return opl_hmirror_u16_by8(src, src_line_stride, width, height, + dst, dst_line_stride, 0); + else if (width % 4 == 0) + return opl_hmirror_u16_by4(src, src_line_stride, width, height, + dst, dst_line_stride, 0); + else if (width % 2 == 0) + return opl_hmirror_u16_by2(src, src_line_stride, width, height, + dst, dst_line_stride, 0); + else /* (width % 1) */ + return opl_hmirror_u16_by1(src, src_line_stride, width, height, + dst, dst_line_stride, 0); +} + +int opl_rotate180_u16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride) +{ + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + if (width % 8 == 0) + return opl_hmirror_u16_by8(src, src_line_stride, width, height, + dst, dst_line_stride, 1); + else if (width % 4 == 0) + return opl_hmirror_u16_by4(src, src_line_stride, width, height, + dst, dst_line_stride, 1); + else if (width % 2 == 0) + return opl_hmirror_u16_by2(src, src_line_stride, width, height, + dst, dst_line_stride, 1); + else /* (width % 1) */ + return opl_hmirror_u16_by1(src, src_line_stride, width, height, + dst, dst_line_stride, 1); +} + +static int opl_hmirror_u16_by1(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror) +{ + const u8 *src_row_addr; + const u8 *psrc; + u8 *dst_row_addr, *pdst; + int i, j; + u16 pixel; + + src_row_addr = src; + if (vmirror) { + dst_row_addr = dst + dst_line_stride * (height - 1); + dst_line_stride = -dst_line_stride; + } else + dst_row_addr = dst; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* Loop over each pixel */ + psrc = src_row_addr; + pdst = dst_row_addr + (width - 1) * BYTES_PER_PIXEL + - (BYTES_PER_PIXEL - BYTES_PER_PIXEL); + for (j = 0; j < width; j++) { + pixel = *(u16 *) psrc; + *(u16 *) pdst = pixel; + psrc += BYTES_PER_PIXEL; + pdst -= BYTES_PER_PIXEL; + } + src_row_addr += src_line_stride; + dst_row_addr += dst_line_stride; + } + + return OPLERR_SUCCESS; +} + +static int opl_hmirror_u16_by2(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror) +{ + const u8 *src_row_addr; + const u8 *psrc; + u8 *dst_row_addr, *pdst; + int i, j; + u32 pixelsin, pixelsout; + + src_row_addr = src; + if (vmirror) { + dst_row_addr = dst + dst_line_stride * (height - 1); + dst_line_stride = -dst_line_stride; + } else + dst_row_addr = dst; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* Loop over each pixel */ + psrc = src_row_addr; + pdst = dst_row_addr + (width - 2) * BYTES_PER_PIXEL; + for (j = 0; j < (width >> 1); j++) { + pixelsin = *(u32 *) psrc; + pixelsout = rot_left_u32(pixelsin, 16); + *(u32 *) pdst = pixelsout; + psrc += BYTES_PER_2PIXEL; + pdst -= BYTES_PER_2PIXEL; + } + src_row_addr += src_line_stride; + dst_row_addr += dst_line_stride; + } + + return OPLERR_SUCCESS; +} + +static int opl_hmirror_u16_by4(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror) +{ + const u8 *src_row_addr; + const u8 *psrc; + u8 *dst_row_addr, *pdst; + int i, j; + + union doubleword { + u64 dw; + u32 w[2]; + }; + + union doubleword inbuf; + union doubleword outbuf; + + src_row_addr = src; + if (vmirror) { + dst_row_addr = dst + dst_line_stride * (height - 1); + dst_line_stride = -dst_line_stride; + } else + dst_row_addr = dst; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* Loop over each pixel */ + psrc = src_row_addr; + pdst = dst_row_addr + (width - 4) * BYTES_PER_PIXEL; + for (j = 0; j < (width >> 2); j++) { + inbuf.dw = *(u64 *) psrc; + outbuf.w[0] = rot_left_u32(inbuf.w[1], 16); + outbuf.w[1] = rot_left_u32(inbuf.w[0], 16); + *(u64 *) pdst = outbuf.dw; + psrc += BYTES_PER_4PIXEL; + pdst -= BYTES_PER_4PIXEL; + } + src_row_addr += src_line_stride; + dst_row_addr += dst_line_stride; + } + return OPLERR_SUCCESS; +} + +static int opl_hmirror_u16_by8(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror) +{ + const u8 *src_row_addr; + const u8 *psrc; + u8 *dst_row_addr, *pdst; + int i, j; + + src_row_addr = src; + if (vmirror) { + dst_row_addr = dst + dst_line_stride * (height - 1); + dst_line_stride = -dst_line_stride; + } else + dst_row_addr = dst; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* Loop over each pixel */ + psrc = src_row_addr; + pdst = dst_row_addr + (width - 1) * BYTES_PER_PIXEL - 2; + for (j = (width >> 3); j > 0; j--) { + __asm__ volatile ( + "ldmia %0!,{r2-r5}\n\t" + "mov r6, r2\n\t" + "mov r7, r3\n\t" + "mov r2, r5, ROR #16\n\t" + "mov r3, r4, ROR #16\n\t" + "mov r4, r7, ROR #16\n\t" + "mov r5, r6, ROR #16\n\t" + "stmda %1!,{r2-r5}\n\t" + + : "+r"(psrc), "+r"(pdst) + : "0"(psrc), "1"(pdst) + : "r2", "r3", "r4", "r5", "r6", "r7", + "memory" + ); + } + src_row_addr += src_line_stride; + dst_row_addr += dst_line_stride; + } + + return OPLERR_SUCCESS; +} + +EXPORT_SYMBOL(opl_hmirror_u16); +EXPORT_SYMBOL(opl_rotate180_u16); diff --git a/drivers/media/video/mxc/opl/opl.h b/drivers/media/video/mxc/opl/opl.h new file mode 100644 index 000000000000..0f6519d604b9 --- /dev/null +++ b/drivers/media/video/mxc/opl/opl.h @@ -0,0 +1,162 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup OPLIP OPL Image Processing + */ +/*! + * @file opl.h + * + * @brief The OPL (Open Primitives Library) Image Processing library defines + * efficient functions for rotation and mirroring. + * + * It includes ARM9-optimized rotation and mirroring functions. It is derived + * from the original OPL project which is found at sourceforge.freescale.net. + * + * @ingroup OPLIP + */ +#ifndef __OPL_H__ +#define __OPL_H__ + +#include + +#define BYTES_PER_PIXEL 2 +#define CACHE_LINE_WORDS 8 +#define BYTES_PER_WORD 4 + +#define BYTES_PER_2PIXEL (BYTES_PER_PIXEL * 2) +#define BYTES_PER_4PIXEL (BYTES_PER_PIXEL * 4) +#define BYTES_PER_8PIXEL (BYTES_PER_PIXEL * 8) + +#define QCIF_Y_WIDTH 176 +#define QCIF_Y_HEIGHT 144 + +/*! Enumerations of opl error code */ +enum opl_error { + OPLERR_SUCCESS = 0, + OPLERR_NULL_PTR, + OPLERR_BAD_ARG, + OPLERR_DIV_BY_ZERO, + OPLERR_OVER_FLOW, + OPLERR_UNDER_FLOW, + OPLERR_MISALIGNED, +}; + +/*! + * @brief Rotate a 16bbp buffer 90 degrees clockwise. + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate90_u16(const u8 *src, int src_line_stride, int width, int height, + u8 *dst, int dst_line_stride); + +/*! + * @brief Rotate a 16bbp buffer 180 degrees clockwise. + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate180_u16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride); + +/*! + * @brief Rotate a 16bbp buffer 270 degrees clockwise + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate270_u16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride); + +/*! + * @brief Mirror a 16bpp buffer horizontally + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_hmirror_u16(const u8 *src, int src_line_stride, int width, int height, + u8 *dst, int dst_line_stride); + +/*! + * @brief Mirror a 16bpp buffer vertically + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_vmirror_u16(const u8 *src, int src_line_stride, int width, int height, + u8 *dst, int dst_line_stride); + +/*! + * @brief Rotate a 16bbp buffer 90 degrees clockwise and mirror vertically + * It is equivalent to rotate 270 degree and mirror horizontally + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate90_vmirror_u16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride); + +/*! + * @brief Rotate a 16bbp buffer 270 degrees clockwise and mirror vertically + * It is equivalent to rotate 90 degree and mirror horizontally + * + * @param src Pointer to the input buffer + * @param src_line_stride Length in bytes of a raster line of the input buffer + * @param width Width in pixels of the region in the input buffer + * @param height Height in pixels of the region in the input buffer + * @param dst Pointer to the output buffer + * @param dst_line_stride Length in bytes of a raster line of the output buffer + * + * @return Standard OPL error code. See enumeration for possible result codes. + */ +int opl_rotate270_vmirror_u16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride); + +#endif /* __OPL_H__ */ diff --git a/drivers/media/video/mxc/opl/opl_mod.c b/drivers/media/video/mxc/opl/opl_mod.c new file mode 100644 index 000000000000..6761f37988da --- /dev/null +++ b/drivers/media/video/mxc/opl/opl_mod.c @@ -0,0 +1,30 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +static __init int opl_init(void) +{ + return 0; +} + +static void __exit opl_exit(void) +{ +} + +module_init(opl_init); +module_exit(opl_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("OPL Software Rotation/Mirroring"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/opl/rotate270_u16.c b/drivers/media/video/mxc/opl/rotate270_u16.c new file mode 100644 index 000000000000..8b995212aeff --- /dev/null +++ b/drivers/media/video/mxc/opl/rotate270_u16.c @@ -0,0 +1,285 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include "opl.h" + +static int opl_rotate270_u16_by16(const u8 *src, int src_line_stride, + int width, int height, u8 *dst, + int dst_line_stride, int vmirror); +static int opl_rotate270_u16_by4(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror); +static int opl_rotate270_vmirror_u16_both(const u8 *src, int src_line_stride, + int width, int height, u8 *dst, + int dst_line_stride, int vmirror); +int opl_rotate270_u16_qcif(const u8 *src, u8 *dst); + +int opl_rotate270_u16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride) +{ + return opl_rotate270_vmirror_u16_both(src, src_line_stride, width, + height, dst, dst_line_stride, 0); +} + +int opl_rotate270_vmirror_u16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride) +{ + return opl_rotate270_vmirror_u16_both(src, src_line_stride, width, + height, dst, dst_line_stride, 1); +} + +static int opl_rotate270_vmirror_u16_both(const u8 *src, int src_line_stride, + int width, int height, u8 *dst, + int dst_line_stride, int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL; + const int BLOCK_SIZE_PIXELS_BY4 = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL / 4; + + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + /* The QCIF algorithm doesn't support vertical mirroring */ + if (vmirror == 0 && width == QCIF_Y_WIDTH && height == QCIF_Y_HEIGHT + && src_line_stride == QCIF_Y_WIDTH * 2 + && src_line_stride == QCIF_Y_HEIGHT * 2) + return opl_rotate270_u16_qcif(src, dst); + else if (width % BLOCK_SIZE_PIXELS == 0 + && height % BLOCK_SIZE_PIXELS == 0) + return opl_rotate270_u16_by16(src, src_line_stride, width, + height, dst, dst_line_stride, + vmirror); + else if (width % BLOCK_SIZE_PIXELS_BY4 == 0 + && height % BLOCK_SIZE_PIXELS_BY4 == 0) + return opl_rotate270_u16_by4(src, src_line_stride, width, + height, dst, dst_line_stride, + vmirror); + else + return OPLERR_BAD_ARG; +} + +/* + * Rotate Counter Clockwise, divide RGB component into 16 row strips, read + * non sequentially and write sequentially. This is done in 16 line strips + * so that the cache is used better. Cachelines are 8 words = 32 bytes. Pixels + * are 2 bytes. The 16 reads will be cache misses, but the next 240 should + * be from cache. The writes to the output buffer will be sequential for 16 + * writes. + * + * Example: + * Input data matrix: output matrix + * + * 0 | 1 | 2 | 3 | 4 | 4 | 0 | 0 | 3 | + * 4 | 3 | 2 | 1 | 0 | 3 | 1 | 9 | 6 | + * 6 | 7 | 8 | 9 | 0 | 2 | 2 | 8 | 2 | + * 5 | 3 | 2 | 6 | 3 | 1 | 3 | 7 | 3 | + * ^ 0 | 4 | 6 | 5 | < Write the input data sequentially + * Read first column + * Start at the bottom + * Move to next column and repeat + * + * Loop over k decreasing (blocks) + * in_block_ptr = src + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k) + * * BLOCK_SIZE_PIXELS) * (RGB_WIDTH_BYTES) + * out_block_ptr = dst + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k) + * * BLOCK_SIZE_BYTES) + (RGB_WIDTH_PIXELS - 1) + * * RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + * + * Loop over i decreasing (width) + * Each pix: + * in_block_ptr += RGB_WIDTH_BYTES + * out_block_ptr += 4 + * + * Each row of block: + * in_block_ptr -= RGB_WIDTH_BYTES * BLOCK_SIZE_PIXELS - 2 + * out_block_ptr -= RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + 2 * BLOCK_SIZE_PIXELS; + * + * It may perform vertical mirroring too depending on the vmirror flag. + */ +static int opl_rotate270_u16_by16(const u8 *src, int src_line_stride, + int width, int height, u8 *dst, + int dst_line_stride, int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL; + const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS + - BYTES_PER_PIXEL; + const int OUT_INDEX = vmirror ? + -dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS + : dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS; + const u8 *in_block_ptr; + u8 *out_block_ptr; + int i, k; + + for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) { + in_block_ptr = src + (((height / BLOCK_SIZE_PIXELS) - k) + * BLOCK_SIZE_PIXELS) * src_line_stride; + out_block_ptr = dst + (((height / BLOCK_SIZE_PIXELS) - k) + * BLOCK_SIZE_PIXELS * BYTES_PER_PIXEL) + + (width - 1) * dst_line_stride; + + /* + * For vertical mirroring the writing starts from the + * first line + */ + if (vmirror) + out_block_ptr -= dst_line_stride * (width - 1); + + for (i = width; i > 0; i--) { + __asm__ volatile ( + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + : "+r" (in_block_ptr), "+r"(out_block_ptr) /* output */ + : "0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride) /* input */ + : "r2", "r3", "r4", "r5", "memory" /* modify */ + ); + in_block_ptr -= IN_INDEX; + out_block_ptr -= OUT_INDEX; + } + } + + return OPLERR_SUCCESS; +} + +/* + * Rotate Counter Clockwise, divide RGB component into 4 row strips, read + * non sequentially and write sequentially. This is done in 4 line strips + * so that the cache is used better. Cachelines are 8 words = 32 bytes. Pixels + * are 2 bytes. The 4 reads will be cache misses, but the next 60 should + * be from cache. The writes to the output buffer will be sequential for 4 + * writes. + * + * Example: + * Input data matrix: output matrix + * + * 0 | 1 | 2 | 3 | 4 | 4 | 0 | 0 | 3 | + * 4 | 3 | 2 | 1 | 0 | 3 | 1 | 9 | 6 | + * 6 | 7 | 8 | 9 | 0 | 2 | 2 | 8 | 2 | + * 5 | 3 | 2 | 6 | 3 | 1 | 3 | 7 | 3 | + * ^ 0 | 4 | 6 | 5 | < Write the input data sequentially + * Read first column + * Start at the bottom + * Move to next column and repeat + * + * Loop over k decreasing (blocks) + * in_block_ptr = src + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k) + * * BLOCK_SIZE_PIXELS) * (RGB_WIDTH_BYTES) + * out_block_ptr = dst + (((RGB_HEIGHT_PIXELS / BLOCK_SIZE_PIXELS) - k) + * * BLOCK_SIZE_BYTES) + (RGB_WIDTH_PIXELS - 1) + * * RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + * + * Loop over i decreasing (width) + * Each pix: + * in_block_ptr += RGB_WIDTH_BYTES + * out_block_ptr += 4 + * + * Each row of block: + * in_block_ptr -= RGB_WIDTH_BYTES * BLOCK_SIZE_PIXELS - 2 + * out_block_ptr -= RGB_HEIGHT_PIXELS * BYTES_PER_PIXEL + 2 * BLOCK_SIZE_PIXELS; + * + * It may perform vertical mirroring too depending on the vmirror flag. + */ +static int opl_rotate270_u16_by4(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL / 4; + const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS + - BYTES_PER_PIXEL; + const int OUT_INDEX = vmirror ? + -dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS + : dst_line_stride + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS; + const u8 *in_block_ptr; + u8 *out_block_ptr; + int i, k; + + for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) { + in_block_ptr = src + (((height / BLOCK_SIZE_PIXELS) - k) + * BLOCK_SIZE_PIXELS) * src_line_stride; + out_block_ptr = dst + (((height / BLOCK_SIZE_PIXELS) - k) + * BLOCK_SIZE_PIXELS * BYTES_PER_PIXEL) + + (width - 1) * dst_line_stride; + + /* + * For vertical mirroring the writing starts from the + * first line + */ + if (vmirror) + out_block_ptr -= dst_line_stride * (width - 1); + + for (i = width; i > 0; i--) { + __asm__ volatile ( + "ldrh r2, [%0], %4\n\t" + "ldrh r3, [%0], %4\n\t" + "ldrh r4, [%0], %4\n\t" + "ldrh r5, [%0], %4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + : "+r" (in_block_ptr), "+r"(out_block_ptr) /* output */ + : "0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride) /* input */ + : "r2", "r3", "r4", "r5", "memory" /* modify */ + ); + in_block_ptr -= IN_INDEX; + out_block_ptr -= OUT_INDEX; + } + } + + return OPLERR_SUCCESS; +} + +EXPORT_SYMBOL(opl_rotate270_u16); +EXPORT_SYMBOL(opl_rotate270_vmirror_u16); diff --git a/drivers/media/video/mxc/opl/rotate270_u16_qcif.S b/drivers/media/video/mxc/opl/rotate270_u16_qcif.S new file mode 100644 index 000000000000..84e6630e84ba --- /dev/null +++ b/drivers/media/video/mxc/opl/rotate270_u16_qcif.S @@ -0,0 +1,70 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include + + .text + .align 2 +ENTRY(opl_rotate270_u16_qcif) + STMFD sp!,{r4-r10} + MOV r12,#0x160 + MOV r10,#0x90 + MOV r3,r10,LSR #4 +.L1.16: + RSB r2,r3,r10,LSR #4 + MOV r5,r2,LSL #5 + MOV r4,r12,LSR #1 + SMULBB r4,r5,r4 + ADD r2,r1,r2,LSL #5 + ADD r5,r2,#0xc000 + ADD r5,r5,#0x4e0 + MOV r2,r12,LSR #1 + ADD r4,r0,r4 +.L1.52: + LDRH r6,[r4],r12 + LDRH r7,[r4],r12 + LDRH r8,[r4],r12 + LDRH r9,[r4],r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + SUBS r2,r2,#1 + LDRH r6,[r4],r12 + LDRH r7,[r4],r12 + LDRH r8,[r4],r12 + LDRH r9,[r4],r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + LDRH r6,[r4],r12 + LDRH r7,[r4],r12 + LDRH r8,[r4],r12 + LDRH r9,[r4],r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + LDRH r6,[r4],r12 + LDRH r7,[r4],r12 + LDRH r8,[r4],r12 + LDRH r9,[r4],r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + SUB r4,r4,#0x1500 + STMIA r5,{r6,r7} + SUB r5,r5,#0x138 + SUB r4,r4,#0xfe + BGT .L1.52 + SUBS r3,r3,#1 + BGT .L1.16 + LDMFD sp!,{r4-r10} + BX lr + .size opl_rotate270_u16_qcif, . - opl_rotate270_u16_qcif diff --git a/drivers/media/video/mxc/opl/rotate90_u16.c b/drivers/media/video/mxc/opl/rotate90_u16.c new file mode 100644 index 000000000000..f52ca87da1dc --- /dev/null +++ b/drivers/media/video/mxc/opl/rotate90_u16.c @@ -0,0 +1,220 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include "opl.h" + +static int opl_rotate90_u16_by16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror); +static int opl_rotate90_u16_by4(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror); +static int opl_rotate90_vmirror_u16_both(const u8 *src, int src_line_stride, + int width, int height, u8 *dst, + int dst_line_stride, int vmirror); +int opl_rotate90_u16_qcif(const u8 *src, u8 *dst); + +int opl_rotate90_u16(const u8 *src, int src_line_stride, int width, int height, + u8 *dst, int dst_line_stride) +{ + return opl_rotate90_vmirror_u16_both(src, src_line_stride, width, + height, dst, dst_line_stride, 0); +} + +int opl_rotate90_vmirror_u16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride) +{ + return opl_rotate90_vmirror_u16_both(src, src_line_stride, width, + height, dst, dst_line_stride, 1); +} + +static int opl_rotate90_vmirror_u16_both(const u8 *src, int src_line_stride, + int width, int height, u8 *dst, + int dst_line_stride, int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL; + const int BLOCK_SIZE_PIXELS_BY4 = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL / 4; + + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + /* The QCIF algorithm doesn't support vertical mirroring */ + if (vmirror == 0 && width == QCIF_Y_WIDTH && height == QCIF_Y_HEIGHT + && src_line_stride == QCIF_Y_WIDTH * 2 + && src_line_stride == QCIF_Y_HEIGHT * 2) + return opl_rotate90_u16_qcif(src, dst); + else if (width % BLOCK_SIZE_PIXELS == 0 + && height % BLOCK_SIZE_PIXELS == 0) + return opl_rotate90_u16_by16(src, src_line_stride, width, + height, dst, dst_line_stride, + vmirror); + else if (width % BLOCK_SIZE_PIXELS_BY4 == 0 + && height % BLOCK_SIZE_PIXELS_BY4 == 0) + return opl_rotate90_u16_by4(src, src_line_stride, width, height, + dst, dst_line_stride, vmirror); + else + return OPLERR_BAD_ARG; +} + +/* + * Performs clockwise rotation (and possibly vertical mirroring depending + * on the vmirror flag) using block sizes of 16x16 + * The algorithm is similar to 270 degree clockwise rotation algorithm + */ +static int opl_rotate90_u16_by16(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL; + const int BLOCK_SIZE_BYTES = BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS; + const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS + + BYTES_PER_PIXEL; + const int OUT_INDEX = vmirror ? + -dst_line_stride - BLOCK_SIZE_BYTES + : dst_line_stride - BLOCK_SIZE_BYTES; + const u8 *in_block_ptr; + u8 *out_block_ptr; + int i, k; + + for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) { + in_block_ptr = src + src_line_stride * (height - 1) + - (src_line_stride * BLOCK_SIZE_PIXELS * + (height / BLOCK_SIZE_PIXELS - k)); + out_block_ptr = dst + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS * + ((height / BLOCK_SIZE_PIXELS) - k); + + /* + * For vertical mirroring the writing starts from the + * bottom line + */ + if (vmirror) + out_block_ptr += dst_line_stride * (width - 1); + + for (i = width; i > 0; i--) { + __asm__ volatile ( + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + : "+r" (in_block_ptr), "+r"(out_block_ptr) /* output */ + : "0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride) /* input */ + : "r2", "r3", "r4", "r5", "memory" /* modify */ + ); + in_block_ptr += IN_INDEX; + out_block_ptr += OUT_INDEX; + } + } + + return OPLERR_SUCCESS; +} + +/* + * Performs clockwise rotation (and possibly vertical mirroring depending + * on the vmirror flag) using block sizes of 4x4 + * The algorithm is similar to 270 degree clockwise rotation algorithm + */ +static int opl_rotate90_u16_by4(const u8 *src, int src_line_stride, int width, + int height, u8 *dst, int dst_line_stride, + int vmirror) +{ + const int BLOCK_SIZE_PIXELS = CACHE_LINE_WORDS * BYTES_PER_WORD + / BYTES_PER_PIXEL / 4; + const int BLOCK_SIZE_BYTES = BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS; + const int IN_INDEX = src_line_stride * BLOCK_SIZE_PIXELS + + BYTES_PER_PIXEL; + const int OUT_INDEX = vmirror ? + -dst_line_stride - BLOCK_SIZE_BYTES + : dst_line_stride - BLOCK_SIZE_BYTES; + const u8 *in_block_ptr; + u8 *out_block_ptr; + int i, k; + + for (k = height / BLOCK_SIZE_PIXELS; k > 0; k--) { + in_block_ptr = src + src_line_stride * (height - 1) + - (src_line_stride * BLOCK_SIZE_PIXELS * + (height / BLOCK_SIZE_PIXELS - k)); + out_block_ptr = dst + BYTES_PER_PIXEL * BLOCK_SIZE_PIXELS + * ((height / BLOCK_SIZE_PIXELS) - k); + + /* + * For horizontal mirroring the writing starts from the + * bottom line + */ + if (vmirror) + out_block_ptr += dst_line_stride * (width - 1); + + for (i = width; i > 0; i--) { + __asm__ volatile ( + "ldrh r2, [%0], -%4\n\t" + "ldrh r3, [%0], -%4\n\t" + "ldrh r4, [%0], -%4\n\t" + "ldrh r5, [%0], -%4\n\t" + "orr r2, r2, r3, lsl #16\n\t" + "orr r4, r4, r5, lsl #16\n\t" + "str r2, [%1], #4\n\t" + "str r4, [%1], #4\n\t" + + : "+r" (in_block_ptr), "+r"(out_block_ptr) /* output */ + : "0"(in_block_ptr), "1"(out_block_ptr), "r"(src_line_stride) /* input */ + : "r2", "r3", "r4", "r5", "memory" /* modify */ + ); + in_block_ptr += IN_INDEX; + out_block_ptr += OUT_INDEX; + } + } + + return OPLERR_SUCCESS; +} + +EXPORT_SYMBOL(opl_rotate90_u16); +EXPORT_SYMBOL(opl_rotate90_vmirror_u16); diff --git a/drivers/media/video/mxc/opl/rotate90_u16_qcif.S b/drivers/media/video/mxc/opl/rotate90_u16_qcif.S new file mode 100644 index 000000000000..082b32fac39d --- /dev/null +++ b/drivers/media/video/mxc/opl/rotate90_u16_qcif.S @@ -0,0 +1,71 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include + + .text + .align 2 +ENTRY(opl_rotate90_u16_qcif) + STMFD sp!,{r4-r10} + MOV r12,#0x160 + MOV r10,#0x90 + MOV r3,r10,LSR #4 +.L1.216: + RSB r2,r3,r10,LSR #4 + MOV r4,#0x20 + SMULBB r5,r4,r2 + MOV r4,#0x1600 + SMULBB r2,r4,r2 + ADD r4,r0,#0xc000 + ADD r4,r4,#0x4a0 + SUB r4,r4,r2 + MOV r2,r12,LSR #1 + ADD r5,r1,r5 +.L1.256: + LDRH r6,[r4],-r12 + LDRH r7,[r4],-r12 + LDRH r8,[r4],-r12 + LDRH r9,[r4],-r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + SUBS r2,r2,#1 + LDRH r6,[r4],-r12 + LDRH r7,[r4],-r12 + LDRH r8,[r4],-r12 + LDRH r9,[r4],-r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + LDRH r6,[r4],-r12 + LDRH r7,[r4],-r12 + LDRH r8,[r4],-r12 + LDRH r9,[r4],-r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + STMIA r5!,{r6,r7} + LDRH r6,[r4],-r12 + LDRH r7,[r4],-r12 + LDRH r8,[r4],-r12 + LDRH r9,[r4],-r12 + ORR r6,r6,r7,LSL #16 + ORR r7,r8,r9,LSL #16 + ADD r4,r4,#0x1600 + STMIA r5!,{r6,r7} + ADD r5,r5,#0x100 + ADD r4,r4,#2 + BGT .L1.256 + SUBS r3,r3,#1 + BGT .L1.216 + LDMFD sp!,{r4-r10} + BX lr + .size opl_rotate90_u16_qcif, . - opl_rotate90_u16_qcif diff --git a/drivers/media/video/mxc/opl/vmirror_u16.c b/drivers/media/video/mxc/opl/vmirror_u16.c new file mode 100644 index 000000000000..03e51efcd9ef --- /dev/null +++ b/drivers/media/video/mxc/opl/vmirror_u16.c @@ -0,0 +1,46 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include "opl.h" + +int opl_vmirror_u16(const u8 *src, int src_line_stride, int width, int height, + u8 *dst, int dst_line_stride) +{ + const u8 *src_row_addr; + u8 *dst_row_addr; + int i; + + if (!src || !dst) + return OPLERR_NULL_PTR; + + if (width == 0 || height == 0 || src_line_stride == 0 + || dst_line_stride == 0) + return OPLERR_BAD_ARG; + + src_row_addr = src; + dst_row_addr = dst + (height - 1) * dst_line_stride; + + /* Loop over all rows */ + for (i = 0; i < height; i++) { + /* memcpy each row */ + memcpy(dst_row_addr, src_row_addr, BYTES_PER_PIXEL * width); + src_row_addr += src_line_stride; + dst_row_addr -= dst_line_stride; + } + + return OPLERR_SUCCESS; +} + +EXPORT_SYMBOL(opl_vmirror_u16); diff --git a/drivers/media/video/mxc/output/Kconfig b/drivers/media/video/mxc/output/Kconfig new file mode 100644 index 000000000000..2153ad248907 --- /dev/null +++ b/drivers/media/video/mxc/output/Kconfig @@ -0,0 +1,28 @@ +config VIDEO_MXC_IPU_OUTPUT + bool "IPU v4l2 support" + depends on VIDEO_MXC_OUTPUT && MXC_IPU + default y + ---help--- + This is the video4linux2 driver for IPU post processing video output. + +config VIDEO_MXC_IPUV1_WVGA_OUTPUT + bool "IPUv1 WVGA v4l2 display support" + depends on VIDEO_MXC_OUTPUT && MXC_IPU + default n + ---help--- + This is the video4linux2 driver for IPUv1 WVGA post processing video output. + +config VIDEO_MXC_EMMA_OUTPUT + bool + depends on VIDEO_MXC_OUTPUT && MXC_EMMA && FB_MXC_SYNC_PANEL + default y + ---help--- + This is the video4linux2 driver for EMMA post processing video output. + +config VIDEO_MXC_OUTPUT_FBSYNC + bool "Synchronize the output with LCDC refresh" + depends on VIDEO_MXC_EMMA_OUTPUT + default y + ---help--- + Synchronize the post-processing with LCDC EOF (End of Frame) to + prevent tearing issue. If unsure, say Y. diff --git a/drivers/media/video/mxc/output/Makefile b/drivers/media/video/mxc/output/Makefile new file mode 100644 index 000000000000..500442544902 --- /dev/null +++ b/drivers/media/video/mxc/output/Makefile @@ -0,0 +1,14 @@ +ifeq ($(CONFIG_VIDEO_MXC_EMMA_OUTPUT),y) + mx27_output-objs := mx27_v4l2_output.o mx27_pp.o + obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mx27_output.o +endif + +ifeq ($(CONFIG_VIDEO_MXC_IPU_OUTPUT),y) + obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mxc_v4l2_output.o +endif +ifeq ($(CONFIG_VIDEO_MXC_PXP_V4L2),y) + obj-$(CONFIG_VIDEO_MXC_PXP_V4L2) += mxc_pxp_v4l2.o +endif +ifeq ($(CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT),y) + obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mx31_v4l2_wvga_output.o +endif diff --git a/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c b/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c new file mode 100644 index 000000000000..fe4346ee56dd --- /dev/null +++ b/drivers/media/video/mxc/output/mx31_v4l2_wvga_output.c @@ -0,0 +1,1928 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/media/video/mxc/output/mxc_v4l2_output.c + * + * @brief MXC V4L2 Video Output Driver + * + * Video4Linux2 Output Device using MXC IPU Post-processing functionality. + * + * @ingroup MXC_V4L2_OUTPUT + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mxc_v4l2_output.h" + +vout_data *g_vout; +#define SDC_FG_FB_FORMAT IPU_PIX_FMT_RGB565 + +struct v4l2_output mxc_outputs[2] = { + { + .index = MXC_V4L2_OUT_2_SDC, + .name = "DISP3 Video Out", + .type = V4L2_OUTPUT_TYPE_ANALOG, /* not really correct, + but no other choice */ + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN}, + { + .index = MXC_V4L2_OUT_2_ADC, + .name = "DISPx Video Out", + .type = V4L2_OUTPUT_TYPE_ANALOG, /* not really correct, + but no other choice */ + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN} +}; + +static int video_nr = 16; +static DEFINE_SPINLOCK(g_lock); +static unsigned int g_pp_out_number; +static unsigned int g_pp_in_number; + +/* debug counters */ +uint32_t g_irq_cnt; +uint32_t g_buf_output_cnt; +uint32_t g_buf_q_cnt; +uint32_t g_buf_dq_cnt; + +static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) +{ + return ((type == IPU_INPUT_BUFFER) ? ((uint32_t) ch & 0xFF) : + ((type == IPU_OUTPUT_BUFFER) ? (((uint32_t) ch >> 8) & 0xFF) + : (((uint32_t) ch >> 16) & 0xFF))); +}; + +static inline uint32_t DMAParamAddr(uint32_t dma_ch) +{ + return 0x10000 | (dma_ch << 4); +}; + +#define QUEUE_SIZE (MAX_FRAME_NUM + 1) +static inline int queue_size(v4l_queue *q) +{ + if (q->tail >= q->head) + return q->tail - q->head; + else + return (q->tail + QUEUE_SIZE) - q->head; +} + +static inline int queue_buf(v4l_queue *q, int idx) +{ + if (((q->tail + 1) % QUEUE_SIZE) == q->head) + return -1; /* queue full */ + q->list[q->tail] = idx; + q->tail = (q->tail + 1) % QUEUE_SIZE; + return 0; +} + +static inline int dequeue_buf(v4l_queue *q) +{ + int ret; + if (q->tail == q->head) + return -1; /* queue empty */ + ret = q->list[q->head]; + q->head = (q->head + 1) % QUEUE_SIZE; + return ret; +} + +static inline int peek_next_buf(v4l_queue *q) +{ + if (q->tail == q->head) + return -1; /* queue empty */ + return q->list[q->head]; +} + +static inline unsigned long get_jiffies(struct timeval *t) +{ + struct timeval cur; + + if (t->tv_usec >= 1000000) { + t->tv_sec += t->tv_usec / 1000000; + t->tv_usec = t->tv_usec % 1000000; + } + + do_gettimeofday(&cur); + if ((t->tv_sec < cur.tv_sec) + || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec))) + return jiffies; + + if (t->tv_usec < cur.tv_usec) { + cur.tv_sec = t->tv_sec - cur.tv_sec - 1; + cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec; + } else { + cur.tv_sec = t->tv_sec - cur.tv_sec; + cur.tv_usec = t->tv_usec - cur.tv_usec; + } + + return jiffies + timeval_to_jiffies(&cur); +} + +/*! + * Private function to free buffers + * + * @param bufs_paddr Array of physical address of buffers to be freed + * + * @param bufs_vaddr Array of virtual address of buffers to be freed + * + * @param num_buf Number of buffers to be freed + * + * @param size Size for each buffer to be free + * + * @return status 0 success. + */ +static int mxc_free_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + if (bufs_vaddr[i] != 0) { + dma_free_coherent(0, size, bufs_vaddr[i], + bufs_paddr[i]); + pr_debug("freed @ paddr=0x%08X\n", (u32) bufs_paddr[i]); + bufs_paddr[i] = 0; + bufs_vaddr[i] = NULL; + } + } + return 0; +} + +/*! + * Private function to allocate buffers + * + * @param bufs_paddr Output array of physical address of buffers allocated + * + * @param bufs_vaddr Output array of virtual address of buffers allocated + * + * @param num_buf Input number of buffers to allocate + * + * @param size Input size for each buffer to allocate + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int mxc_allocate_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + bufs_vaddr[i] = dma_alloc_coherent(0, size, + &bufs_paddr[i], + GFP_DMA | GFP_KERNEL); + + if (bufs_vaddr[i] == 0) { + mxc_free_buffers(bufs_paddr, bufs_vaddr, i, size); + printk(KERN_ERR "dma_alloc_coherent failed.\n"); + return -ENOBUFS; + } + pr_debug("allocated @ paddr=0x%08X, size=%d.\n", + (u32) bufs_paddr[i], size); + } + + return 0; +} + +/* + * Returns bits per pixel for given pixel format + * + * @param pixelformat V4L2_PIX_FMT_RGB565, + * V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return bits per pixel of pixelformat + */ +static u32 fmt_to_bpp(u32 pixelformat) +{ + u32 bpp; + + switch (pixelformat) { + case V4L2_PIX_FMT_RGB565: + bpp = 16; + break; + case V4L2_PIX_FMT_BGR24: + case V4L2_PIX_FMT_RGB24: + bpp = 24; + break; + case V4L2_PIX_FMT_BGR32: + case V4L2_PIX_FMT_RGB32: + bpp = 32; + break; + default: + bpp = 8; + break; + } + return bpp; +} + +static u32 bpp_to_fmt(struct fb_info *fbi) +{ + if (fbi->var.nonstd) + return fbi->var.nonstd; + + if (fbi->var.bits_per_pixel == 24) + return V4L2_PIX_FMT_BGR24; + else if (fbi->var.bits_per_pixel == 32) + return V4L2_PIX_FMT_BGR32; + else if (fbi->var.bits_per_pixel == 16) + return V4L2_PIX_FMT_RGB565; + + return 0; +} + +static void mxc_v4l2out_timer_handler(unsigned long arg) +{ + int index; + unsigned long timeout; + unsigned long lock_flags = 0; + vout_data *vout = (vout_data *) arg; + + dev_dbg(vout->video_dev->dev, "timer handler: %lu\n", jiffies); + + spin_lock_irqsave(&g_lock, lock_flags); + + if ((vout->state == STATE_STREAM_STOPPING) + || (vout->state == STATE_STREAM_OFF)) + goto exit0; + /* + * If timer occurs before IPU h/w is ready, then set the state to + * paused and the timer will be set again when next buffer is queued + * or PP comletes + */ + if (vout->ipu_buf[0] != -1) { + dev_dbg(vout->video_dev->dev, "IPU buffer busy\n"); + vout->state = STATE_STREAM_PAUSED; + goto exit0; + } + + /* One frame buffer should be ready here */ + if (vout->frame_count % 2 == 1) { + /* set BUF0 rdy */ + if (ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 0) < + 0) + pr_debug("error selecting display buf 0"); + } else { + if (ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 1) < + 0) + pr_debug("error selecting display buf 1"); + } + + /* Dequeue buffer and pass to IPU */ + index = dequeue_buf(&vout->ready_q); + if (index == -1) { /* no buffers ready, should never occur */ + dev_err(vout->video_dev->dev, + "mxc_v4l2out: timer - no queued buffers ready\n"); + goto exit0; + } + + g_buf_dq_cnt++; + vout->frame_count++; + vout->ipu_buf[1] = vout->ipu_buf[0] = index; + + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + 0, + vout->v4l2_bufs[vout->ipu_buf[0]].m. + offset) < 0) + goto exit0; + + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + 1, + vout->v4l2_bufs[vout->ipu_buf[0]].m. + offset + vout->v2f.fmt.pix.width / 2) < 0) + goto exit0; + + /* All buffer should now ready in IPU out, tranfer to display buf */ + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, + 0, + vout-> + display_bufs[(vout->frame_count - + 1) % 2]) < 0) { + dev_err(vout->video_dev->dev, + "unable to update buffer %d address\n", + vout->next_rdy_ipu_buf); + goto exit0; + } + if (ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, + 1, + vout-> + display_bufs[(vout->frame_count - + 1) % 2] + + vout->crop_current.width / 2 * + bytes_per_pixel(SDC_FG_FB_FORMAT)) < 0) { + dev_err(vout->video_dev->dev, + "unable to update buffer %d address\n", + vout->next_rdy_ipu_buf); + goto exit0; + } + + if (ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0) < 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + goto exit0; + } + + if (ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0) < 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + goto exit0; + } + + /* Setup timer for next buffer */ + index = peek_next_buf(&vout->ready_q); + if (index != -1) { + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = + vout->start_jiffies + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index].timestamp); + + if (jiffies >= timeout) { + dev_dbg(vout->video_dev->dev, + "warning: timer timeout already expired.\n"); + } + if (mod_timer(&vout->output_timer, timeout)) + dev_dbg(vout->video_dev->dev, + "warning: timer was already set\n"); + + dev_dbg(vout->video_dev->dev, + "timer handler next schedule: %lu\n", timeout); + } else { + vout->state = STATE_STREAM_PAUSED; + } + +exit0: + spin_unlock_irqrestore(&g_lock, lock_flags); +} + +extern void _ipu_write_param_mem(uint32_t addr, uint32_t *data, + uint32_t numWords); + +static irqreturn_t mxc_v4l2out_pp_in_irq_handler(int irq, void *dev_id) +{ + unsigned long lock_flags = 0; + vout_data *vout = dev_id; + uint32_t u_offset; + uint32_t v_offset; + uint32_t local_params[4]; + uint32_t width, height; + uint32_t dma_chan; + + spin_lock_irqsave(&g_lock, lock_flags); + g_irq_cnt++; + + dma_chan = channel_2_dma(vout->post_proc_ch, IPU_INPUT_BUFFER); + memset(&local_params, 0, sizeof(local_params)); + + if (g_pp_in_number % 2 == 1) { + u_offset = vout->offset.u_offset - vout->v2f.fmt.pix.width / 4; + v_offset = vout->offset.v_offset - vout->v2f.fmt.pix.width / 4; + width = vout->v2f.fmt.pix.width / 2; + height = vout->v2f.fmt.pix.height; + local_params[3] = + (uint32_t) ((width - 1) << 12) | ((uint32_t) (height - + 1) << 24); + local_params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32)); + local_params[2] = u_offset >> (64 - 53); + local_params[2] |= v_offset << (79 - 64); + local_params[3] |= v_offset >> (96 - 79); + _ipu_write_param_mem(DMAParamAddr(dma_chan), local_params, 4); + + if (ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 1) < + 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + } + } else { + u_offset = vout->offset.u_offset; + v_offset = vout->offset.v_offset; + width = vout->v2f.fmt.pix.width / 2; + height = vout->v2f.fmt.pix.height; + local_params[3] = + (uint32_t) ((width - 1) << 12) | ((uint32_t) (height - + 1) << 24); + local_params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32)); + local_params[2] = u_offset >> (64 - 53); + local_params[2] |= v_offset << (79 - 64); + local_params[3] |= v_offset >> (96 - 79); + _ipu_write_param_mem(DMAParamAddr(dma_chan), local_params, 4); + } + g_pp_in_number++; + + spin_unlock_irqrestore(&g_lock, lock_flags); + + return IRQ_HANDLED; +} + +static irqreturn_t mxc_v4l2out_pp_out_irq_handler(int irq, void *dev_id) +{ + vout_data *vout = dev_id; + int index; + unsigned long timeout; + u32 lock_flags = 0; + + spin_lock_irqsave(&g_lock, lock_flags); + + if (g_pp_out_number % 2 == 1) { + if (ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 1) + < 0) { + dev_err(vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + } + } else { + if (vout->ipu_buf[0] != -1) { + vout->v4l2_bufs[vout->ipu_buf[0]].flags = + V4L2_BUF_FLAG_DONE; + queue_buf(&vout->done_q, vout->ipu_buf[0]); + wake_up_interruptible(&vout->v4l_bufq); + vout->ipu_buf[0] = -1; + } + index = peek_next_buf(&vout->ready_q); + if (vout->state == STATE_STREAM_STOPPING) { + if ((vout->ipu_buf[0] == -1) + && (vout->ipu_buf[1] == -1)) + vout->state = STATE_STREAM_OFF; + } else if ((vout->state == STATE_STREAM_PAUSED) + && (index != -1)) { + /*! + * Setup timer for next buffer, + * when stream has been paused + */ + pr_debug("next index %d\n", index); + + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0)) + timeout = + vout->start_jiffies + + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index]. + timestamp); + + if (jiffies >= timeout) { + pr_debug + ("warning: timer timeout" + "already expired.\n"); + } + + vout->state = STATE_STREAM_ON; + + if (mod_timer(&vout->output_timer, timeout)) + pr_debug("warning: timer was already set\n"); + + pr_debug("timer handler next schedule: %lu\n", timeout); + } + } + g_pp_out_number++; + + spin_unlock_irqrestore(&g_lock, lock_flags); + return IRQ_HANDLED; +} + +/*! + * Start the output stream + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamon(vout_data *vout) +{ + struct device *dev = vout->video_dev->dev; + ipu_channel_params_t params; + struct mxcfb_pos fb_pos; + struct fb_var_screeninfo fbvar; + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + int pp_in_buf[2]; + u16 out_width; + u16 out_height; + ipu_channel_t display_input_ch = MEM_PP_MEM; + bool use_direct_adc = false; + mm_segment_t old_fs; + + if (!vout) + return -EINVAL; + + if (vout->state != STATE_STREAM_OFF) + return -EBUSY; + + if (queue_size(&vout->ready_q) < 2) { + dev_err(dev, "2 buffers not been queued yet!\n"); + return -EINVAL; + } + + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + + vout->next_done_ipu_buf = vout->next_rdy_ipu_buf = 0; + vout->ipu_buf[0] = pp_in_buf[0] = dequeue_buf(&vout->ready_q); + vout->ipu_buf[1] = pp_in_buf[1] = vout->ipu_buf[0]; + vout->frame_count = 1; + g_pp_out_number = 1; + g_pp_in_number = 1; + + ipu_enable_irq(IPU_IRQ_PP_IN_EOF); + ipu_enable_irq(IPU_IRQ_PP_OUT_EOF); + + /* Init Display Channel */ +#ifdef CONFIG_FB_MXC_ASYNC_PANEL + if (vout->cur_disp_output < DISP3) { + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, 0); + fbi = NULL; + if (ipu_can_rotate_in_place(vout->rotate)) { + dev_dbg(dev, "Using PP direct to ADC channel\n"); + use_direct_adc = true; + vout->display_ch = MEM_PP_ADC; + vout->post_proc_ch = MEM_PP_ADC; + + memset(¶ms, 0, sizeof(params)); + params.mem_pp_adc.in_width = vout->v2f.fmt.pix.width; + params.mem_pp_adc.in_height = vout->v2f.fmt.pix.height; + params.mem_pp_adc.in_pixel_fmt = + vout->v2f.fmt.pix.pixelformat; + params.mem_pp_adc.out_width = out_width; + params.mem_pp_adc.out_height = out_height; + params.mem_pp_adc.out_pixel_fmt = SDC_FG_FB_FORMAT; +#ifdef CONFIG_FB_MXC_EPSON_PANEL + params.mem_pp_adc.out_left = + 2 + vout->crop_current.left; +#else + params.mem_pp_adc.out_left = + 12 + vout->crop_current.left; +#endif + params.mem_pp_adc.out_top = vout->crop_current.top; + if (ipu_init_channel( + vout->post_proc_ch, ¶ms) != 0) { + dev_err(dev, "Error initializing PP chan\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + params.mem_pp_adc. + in_pixel_fmt, + params.mem_pp_adc.in_width, + params.mem_pp_adc.in_height, + vout->v2f.fmt.pix. + bytesperline / + bytes_per_pixel(params. + mem_pp_adc. + in_pixel_fmt), + vout->rotate, + vout-> + v4l2_bufs[pp_in_buf[0]].m. + offset, + vout-> + v4l2_bufs[pp_in_buf[1]].m. + offset, + vout->offset.u_offset, + vout->offset.v_offset) != + 0) { + dev_err(dev, "Error initializing PP in buf\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_adc. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, 0, 0, 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP" + "output buffer\n"); + return -EINVAL; + } + + } else { + dev_dbg(dev, "Using ADC SYS2 channel\n"); + vout->display_ch = ADC_SYS2; + vout->post_proc_ch = MEM_PP_MEM; + + if (vout->display_bufs[0]) { + mxc_free_buffers(vout->display_bufs, + vout->display_bufs_vaddr, + 2, vout->display_buf_size); + } + + vout->display_buf_size = vout->crop_current.width * + vout->crop_current.height * + fmt_to_bpp(SDC_FG_FB_FORMAT) / 8; + mxc_allocate_buffers(vout->display_bufs, + vout->display_bufs_vaddr, + 2, vout->display_buf_size); + + memset(¶ms, 0, sizeof(params)); + params.adc_sys2.disp = vout->cur_disp_output; + params.adc_sys2.ch_mode = WriteTemplateNonSeq; +#ifdef CONFIG_FB_MXC_EPSON_PANEL + params.adc_sys2.out_left = 2 + vout->crop_current.left; +#else + params.adc_sys2.out_left = 12 + vout->crop_current.left; +#endif + params.adc_sys2.out_top = vout->crop_current.top; + if (ipu_init_channel(ADC_SYS2, ¶ms) < 0) + return -EINVAL; + + if (ipu_init_channel_buffer(vout->display_ch, + IPU_INPUT_BUFFER, + SDC_FG_FB_FORMAT, + out_width, out_height, + out_width, IPU_ROTATE_NONE, + vout->display_bufs[0], + vout->display_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing SDC FG buffer\n"); + return -EINVAL; + } + } + } else +#endif + { /* Use SDC */ + dev_dbg(dev, "Using SDC channel\n"); + + fbvar = fbi->var; + if (vout->cur_disp_output == 3) { + vout->display_ch = MEM_FG_SYNC; + fbvar.bits_per_pixel = 16; + fbvar.nonstd = IPU_PIX_FMT_UYVY; + + fbvar.xres = fbvar.xres_virtual = out_width; + fbvar.yres = out_height; + fbvar.yres_virtual = out_height * 2; + } else if (vout->cur_disp_output == 5) { + vout->display_ch = MEM_DC_SYNC; + fbvar.bits_per_pixel = 16; + fbvar.nonstd = IPU_PIX_FMT_UYVY; + + fbvar.xres = fbvar.xres_virtual = out_width; + fbvar.yres = out_height; + fbvar.yres_virtual = out_height * 2; + } else { + vout->display_ch = MEM_BG_SYNC; + } + + fbvar.activate |= FB_ACTIVATE_FORCE; + fb_set_var(fbi, &fbvar); + + fb_pos.x = vout->crop_current.left; + fb_pos.y = vout->crop_current.top; + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS, + (unsigned long)&fb_pos); + set_fs(old_fs); + } + + vout->display_bufs[1] = fbi->fix.smem_start; + vout->display_bufs[0] = fbi->fix.smem_start + + (fbi->fix.line_length * fbi->var.yres); + vout->display_buf_size = vout->crop_current.width * + vout->crop_current.height * fbi->var.bits_per_pixel / 8; + + vout->post_proc_ch = MEM_PP_MEM; + } + + /* Init PP */ + if (use_direct_adc == false) { + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.height; + out_height = vout->crop_current.width; + } + memset(¶ms, 0, sizeof(params)); + params.mem_pp_mem.in_width = vout->v2f.fmt.pix.width / 2; + params.mem_pp_mem.in_height = vout->v2f.fmt.pix.height; + params.mem_pp_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat; + params.mem_pp_mem.out_width = out_width / 2; + params.mem_pp_mem.out_height = out_height; + if (vout->display_ch == ADC_SYS2) + params.mem_pp_mem.out_pixel_fmt = SDC_FG_FB_FORMAT; + else + params.mem_pp_mem.out_pixel_fmt = bpp_to_fmt(fbi); + if (ipu_init_channel(vout->post_proc_ch, ¶ms) != 0) { + dev_err(dev, "Error initializing PP channel\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + params.mem_pp_mem.in_pixel_fmt, + params.mem_pp_mem.in_width, + params.mem_pp_mem.in_height, + vout->v2f.fmt.pix.bytesperline / + bytes_per_pixel(params.mem_pp_mem. + in_pixel_fmt), + IPU_ROTATE_NONE, + vout->v4l2_bufs[pp_in_buf[0]].m. + offset, + vout->v4l2_bufs[pp_in_buf[0]].m. + offset + params.mem_pp_mem.in_width, + vout->offset.u_offset, + vout->offset.v_offset) != 0) { + dev_err(dev, "Error initializing PP input buffer\n"); + return -EINVAL; + } + + if (!ipu_can_rotate_in_place(vout->rotate)) { + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + if (mxc_allocate_buffers + (vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size) < 0) + return -ENOBUFS; + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + IPU_ROTATE_NONE, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing" + "PP output buffer\n"); + return -EINVAL; + } + + if (ipu_init_channel(MEM_ROT_PP_MEM, NULL) != 0) { + dev_err(dev, + "Error initializing PP ROT channel\n"); + return -EINVAL; + } + + if (ipu_init_channel_buffer(MEM_ROT_PP_MEM, + IPU_INPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP ROT" + "input buffer\n"); + return -EINVAL; + } + + /* swap width and height */ + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + } + + if (ipu_init_channel_buffer(MEM_ROT_PP_MEM, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_width, + IPU_ROTATE_NONE, + vout->display_bufs[0], + vout->display_bufs[1], 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP" + "output buffer\n"); + return -EINVAL; + } + + if (ipu_link_channels(vout->post_proc_ch, + MEM_ROT_PP_MEM) < 0) + return -EINVAL; + + ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 1); + + ipu_enable_channel(MEM_ROT_PP_MEM); + + display_input_ch = MEM_ROT_PP_MEM; + } else { + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_pp_mem. + out_pixel_fmt, + out_width / 2, + out_height, + out_width, + vout->rotate, + vout->display_bufs[0], + vout->display_bufs[0] + + + out_width / 2 * + bytes_per_pixel + (SDC_FG_FB_FORMAT), 0, + 0) != 0) { + dev_err(dev, + "Error initializing PP" + "output buffer\n"); + return -EINVAL; + } + } + if (ipu_unlink_channels( + display_input_ch, vout->display_ch) < 0) { + dev_err(dev, "Error linking ipu channels\n"); + return -EINVAL; + } + } + + vout->state = STATE_STREAM_PAUSED; + + ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0); + + if (use_direct_adc == false) { + ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0); + ipu_enable_channel(vout->post_proc_ch); + + if (fbi) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_UNBLANK); + release_console_sem(); + } else { + ipu_enable_channel(vout->display_ch); + } + } else { + ipu_enable_channel(vout->post_proc_ch); + } + + vout->start_jiffies = jiffies; + dev_dbg(dev, + "streamon: start time = %lu jiffies\n", vout->start_jiffies); + + return 0; +} + +/*! + * Shut down the voutera + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamoff(vout_data *vout) +{ + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + int i, retval = 0; + unsigned long lockflag = 0; + + if (!vout) + return -EINVAL; + + if (vout->state == STATE_STREAM_OFF) + return 0; + + spin_lock_irqsave(&g_lock, lockflag); + + del_timer(&vout->output_timer); + + if (vout->state == STATE_STREAM_ON) + vout->state = STATE_STREAM_STOPPING; + + ipu_disable_irq(IPU_IRQ_PP_IN_EOF); + ipu_disable_irq(IPU_IRQ_PP_OUT_EOF); + + spin_unlock_irqrestore(&g_lock, lockflag); + + if (vout->post_proc_ch == MEM_PP_MEM) { /* SDC or ADC with Rotation */ + if (!ipu_can_rotate_in_place(vout->rotate)) { + ipu_unlink_channels(MEM_PP_MEM, MEM_ROT_PP_MEM); + ipu_unlink_channels(MEM_ROT_PP_MEM, vout->display_ch); + ipu_disable_channel(MEM_ROT_PP_MEM, true); + + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + } else { + ipu_unlink_channels(MEM_PP_MEM, vout->display_ch); + } + ipu_disable_channel(MEM_PP_MEM, true); + + if (vout->display_ch == ADC_SYS2) { + ipu_disable_channel(vout->display_ch, true); + ipu_uninit_channel(vout->display_ch); + } else { + fbi->var.activate |= FB_ACTIVATE_FORCE; + fb_set_var(fbi, &fbi->var); + + if (vout->display_ch == MEM_FG_SYNC) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_POWERDOWN); + release_console_sem(); + } + + vout->display_bufs[0] = 0; + vout->display_bufs[1] = 0; + } + + ipu_uninit_channel(MEM_PP_MEM); + if (!ipu_can_rotate_in_place(vout->rotate)) + ipu_uninit_channel(MEM_ROT_PP_MEM); + } else { /* ADC Direct */ + ipu_disable_channel(MEM_PP_ADC, true); + ipu_uninit_channel(MEM_PP_ADC); + } + vout->ready_q.head = vout->ready_q.tail = 0; + vout->done_q.head = vout->done_q.tail = 0; + for (i = 0; i < vout->buffer_cnt; i++) { + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + + vout->state = STATE_STREAM_OFF; + +#ifdef CONFIG_FB_MXC_ASYNC_PANEL + if (vout->cur_disp_output < DISP3) { + if (vout->display_bufs[0] != 0) { + mxc_free_buffers(vout->display_bufs, + vout->display_bufs_vaddr, 2, + vout->display_buf_size); + } + + mxcfb_set_refresh_mode(registered_fb + [vout-> + output_fb_num[vout->cur_disp_output]], + MXCFB_REFRESH_PARTIAL, 0); + } +#endif + + return retval; +} + +/* + * Valid whether the palette is supported + * + * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return 1 if supported, 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + return ((palette == V4L2_PIX_FMT_RGB565) || + (palette == V4L2_PIX_FMT_BGR24) || + (palette == V4L2_PIX_FMT_RGB24) || + (palette == V4L2_PIX_FMT_BGR32) || + (palette == V4L2_PIX_FMT_RGB32) || + (palette == V4L2_PIX_FMT_NV12) || + (palette == V4L2_PIX_FMT_YUV422P) || + (palette == V4L2_PIX_FMT_YUV420)); +} + +/* + * V4L2 - Handles VIDIOC_G_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_g_fmt(vout_data *vout, struct v4l2_format *f) +{ + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + *f = vout->v2f; + return 0; +} + +/* + * V4L2 - Handles VIDIOC_S_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_s_fmt(vout_data *vout, struct v4l2_format *f) +{ + int retval = 0; + u32 size = 0; + u32 bytesperline; + + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + goto err0; + } + if (!valid_mode(f->fmt.pix.pixelformat)) { + dev_err(vout->video_dev->dev, "pixel format not supported\n"); + retval = -EINVAL; + goto err0; + } + + bytesperline = (f->fmt.pix.width * fmt_to_bpp(f->fmt.pix.pixelformat)) / + 8; + if (f->fmt.pix.bytesperline < bytesperline) { + f->fmt.pix.bytesperline = bytesperline; + } else { + bytesperline = f->fmt.pix.bytesperline; + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUV422P: + /* byteperline for YUV planar formats is for + Y plane only */ + size = bytesperline * f->fmt.pix.height * 2; + break; + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_NV12: + size = (bytesperline * f->fmt.pix.height * 3) / 2; + break; + default: + size = bytesperline * f->fmt.pix.height; + break; + } + + /* Return the actual size of the image to the app */ + if (f->fmt.pix.sizeimage < size) + f->fmt.pix.sizeimage = size; + else + size = f->fmt.pix.sizeimage; + + vout->v2f.fmt.pix = f->fmt.pix; + if (vout->v2f.fmt.pix.priv != 0) { + if (copy_from_user(&vout->offset, + (void *)vout->v2f.fmt.pix.priv, + sizeof(vout->offset))) { + retval = -EFAULT; + goto err0; + } + } else { + vout->offset.u_offset = 0; + vout->offset.v_offset = 0; + } + + retval = 0; +err0: + return retval; +} + +/* + * V4L2 - Handles VIDIOC_G_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_get_v42lout_control(vout_data *vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + return (vout->rotate & IPU_ROTATE_HORIZ_FLIP) ? 1 : 0; + case V4L2_CID_VFLIP: + return (vout->rotate & IPU_ROTATE_VERT_FLIP) ? 1 : 0; + case (V4L2_CID_PRIVATE_BASE + 1): + return vout->rotate; + default: + return -EINVAL; + } +} + +/* + * V4L2 - Handles VIDIOC_S_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_set_v42lout_control(vout_data *vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + vout->rotate |= c->value ? IPU_ROTATE_HORIZ_FLIP : + IPU_ROTATE_NONE; + break; + case V4L2_CID_VFLIP: + vout->rotate |= c->value ? IPU_ROTATE_VERT_FLIP : + IPU_ROTATE_NONE; + break; + case V4L2_CID_MXC_ROT: + vout->rotate = c->value; + break; + default: + return -EINVAL; + } + return 0; +} + +/*! + * V4L2 interface - open function + * + * @param inode structure inode * + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l2out_open(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + int err; + + if (!vout) + return -ENODEV; + + down(&vout->busy_lock); + + err = -EINTR; + if (signal_pending(current)) + goto oops; + + if (vout->open_count++ == 0) { + ipu_request_irq(IPU_IRQ_PP_IN_EOF, + mxc_v4l2out_pp_in_irq_handler, + 0, dev->name, vout); + ipu_request_irq(IPU_IRQ_PP_OUT_EOF, + mxc_v4l2out_pp_out_irq_handler, + 0, dev->name, vout); + + init_waitqueue_head(&vout->v4l_bufq); + + init_timer(&vout->output_timer); + vout->output_timer.function = mxc_v4l2out_timer_handler; + vout->output_timer.data = (unsigned long)vout; + + vout->state = STATE_STREAM_OFF; + vout->rotate = IPU_ROTATE_NONE; + g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0; + + } + + file->private_data = dev; + + up(&vout->busy_lock); + + return 0; + +oops: + up(&vout->busy_lock); + return err; +} + +/*! + * V4L2 interface - close function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @return 0 success + */ +static int mxc_v4l2out_close(struct inode *inode, struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + + if (--vout->open_count == 0) { + if (vout->state != STATE_STREAM_OFF) + mxc_v4l2out_streamoff(vout); + + ipu_free_irq(IPU_IRQ_PP_IN_EOF, vout); + ipu_free_irq(IPU_IRQ_PP_OUT_EOF, vout); + + file->private_data = NULL; + + mxc_free_buffers(vout->queue_buf_paddr, vout->queue_buf_vaddr, + vout->buffer_cnt, vout->queue_buf_size); + vout->buffer_cnt = 0; + mxc_free_buffers(vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + + /* capture off */ + wake_up_interruptible(&vout->v4l_bufq); + } + + return 0; +} + +/*! + * V4L2 interface - ioctl function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @param ioctlnr unsigned int + * + * @param arg void * + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static int +mxc_v4l2out_do_ioctl(struct inode *inode, struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *vdev = file->private_data; + vout_data *vout = video_get_drvdata(vdev); + int retval = 0; + int i = 0; + + if (!vout) + return -EBADF; + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + case VIDIOC_QUERYCAP: + { + struct v4l2_capability *cap = arg; + strcpy(cap->driver, "mxc_v4l2_output"); + cap->version = 0; + cap->capabilities = + V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + retval = 0; + break; + } + case VIDIOC_G_FMT: + { + struct v4l2_format *gf = arg; + retval = mxc_v4l2out_g_fmt(vout, gf); + break; + } + case VIDIOC_S_FMT: + { + struct v4l2_format *sf = arg; + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + retval = mxc_v4l2out_s_fmt(vout, sf); + break; + } + case VIDIOC_REQBUFS: + { + struct v4l2_requestbuffers *req = arg; + if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (req->memory != V4L2_MEMORY_MMAP)) { + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS: incorrect" + "buffer type\n"); + retval = -EINVAL; + break; + } + + if (req->count == 0) + mxc_v4l2out_streamoff(vout); + + if (vout->state == STATE_STREAM_OFF) { + if (vout->queue_buf_paddr[0] != 0) { + mxc_free_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS:" + "freed buffers\n"); + } + vout->buffer_cnt = 0; + } else { + dev_dbg(vdev->dev, + "VIDIOC_REQBUFS: Buffer is in use\n"); + retval = -EBUSY; + break; + } + + if (req->count == 0) + break; + + if (req->count < MIN_FRAME_NUM) + req->count = MIN_FRAME_NUM; + else if (req->count > MAX_FRAME_NUM) + req->count = MAX_FRAME_NUM; + vout->buffer_cnt = req->count; + vout->queue_buf_size = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + + retval = mxc_allocate_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + if (retval < 0) + break; + + /* Init buffer queues */ + vout->done_q.head = 0; + vout->done_q.tail = 0; + vout->ready_q.head = 0; + vout->ready_q.tail = 0; + + for (i = 0; i < vout->buffer_cnt; i++) { + memset(&(vout->v4l2_bufs[i]), 0, + sizeof(vout->v4l2_bufs[i])); + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].memory = V4L2_MEMORY_MMAP; + vout->v4l2_bufs[i].index = i; + vout->v4l2_bufs[i].type = + V4L2_BUF_TYPE_VIDEO_OUTPUT; + vout->v4l2_bufs[i].length = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + vout->v4l2_bufs[i].m.offset = + (unsigned long)vout->queue_buf_paddr[i]; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + break; + } + case VIDIOC_QUERYBUF: + { + struct v4l2_buffer *buf = arg; + u32 type = buf->type; + int index = buf->index; + + if ((type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + dev_dbg(vdev->dev, + "VIDIOC_QUERYBUFS: incorrect" + "buffer type\n"); + retval = -EINVAL; + break; + } + down(&vout->param_lock); + memcpy(buf, &(vout->v4l2_bufs[index]), sizeof(*buf)); + up(&vout->param_lock); + break; + } + case VIDIOC_QBUF: + { + struct v4l2_buffer *buf = arg; + int index = buf->index; + unsigned long lock_flags; + + if ((buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + retval = -EINVAL; + break; + } + + dev_dbg(vdev->dev, "VIDIOC_QBUF: %d\n", buf->index); + + /* mmapped buffers are L1 WB cached, + * so we need to clean them */ + if (buf->flags & V4L2_BUF_FLAG_MAPPED) + flush_cache_all(); + + spin_lock_irqsave(&g_lock, lock_flags); + + memcpy(&(vout->v4l2_bufs[index]), buf, sizeof(*buf)); + vout->v4l2_bufs[index].flags |= V4L2_BUF_FLAG_QUEUED; + + g_buf_q_cnt++; + queue_buf(&vout->ready_q, index); + if (vout->state == STATE_STREAM_PAUSED) { + unsigned long timeout; + + index = peek_next_buf(&vout->ready_q); + + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == + 0) + && (vout->v4l2_bufs[index].timestamp. + tv_usec == 0)) + timeout = + vout->start_jiffies + + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index]. + timestamp); + + if (jiffies >= timeout) { + dev_dbg(vout->video_dev->dev, + "warning: timer timeout" + "already expired.\n"); + } + vout->output_timer.expires = timeout; + dev_dbg(vdev->dev, + "QBUF: frame #%u timeout @" + " %lu jiffies, current = %lu\n", + vout->frame_count, timeout, jiffies); + add_timer(&vout->output_timer); + vout->state = STATE_STREAM_ON; + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + break; + } + case VIDIOC_DQBUF: + { + struct v4l2_buffer *buf = arg; + int idx; + + if ((queue_size(&vout->done_q) == 0) && + (file->f_flags & O_NONBLOCK)) { + retval = -EAGAIN; + break; + } + + if (!wait_event_interruptible_timeout(vout->v4l_bufq, + queue_size(&vout-> + done_q) + != 0, 10 * HZ)) { + dev_dbg(vdev->dev, "VIDIOC_DQBUF: timeout\n"); + retval = -ETIME; + break; + } else if (signal_pending(current)) { + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: interrupt received\n"); + retval = -ERESTARTSYS; + break; + } + idx = dequeue_buf(&vout->done_q); + if (idx == -1) { /* No frame free */ + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: no free buffers\n"); + retval = -EAGAIN; + break; + } + if ((vout->v4l2_bufs[idx].flags & V4L2_BUF_FLAG_DONE) == + 0) + dev_dbg(vdev->dev, + "VIDIOC_DQBUF: buffer in done q, " + "but not flagged as done\n"); + + vout->v4l2_bufs[idx].flags = 0; + memcpy(buf, &(vout->v4l2_bufs[idx]), sizeof(*buf)); + dev_dbg(vdev->dev, "VIDIOC_DQBUF: %d\n", buf->index); + break; + } + case VIDIOC_STREAMON: + { + retval = mxc_v4l2out_streamon(vout); + break; + } + case VIDIOC_STREAMOFF: + { + retval = mxc_v4l2out_streamoff(vout); + break; + } + case VIDIOC_G_CTRL: + { + retval = mxc_get_v42lout_control(vout, arg); + break; + } + case VIDIOC_S_CTRL: + { + retval = mxc_set_v42lout_control(vout, arg); + break; + } + case VIDIOC_CROPCAP: + { + struct v4l2_cropcap *cap = arg; + + if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + + cap->bounds = vout->crop_bounds[vout->cur_disp_output]; + cap->defrect = vout->crop_bounds[vout->cur_disp_output]; + retval = 0; + break; + } + case VIDIOC_G_CROP: + { + struct v4l2_crop *crop = arg; + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + crop->c = vout->crop_current; + break; + } + case VIDIOC_S_CROP: + { + struct v4l2_crop *crop = arg; + struct v4l2_rect *b = + &(vout->crop_bounds[vout->cur_disp_output]); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + if (crop->c.height < 0) { + retval = -EINVAL; + break; + } + if (crop->c.width < 0) { + retval = -EINVAL; + break; + } + + /* only full screen supported for SDC BG */ + if (vout->cur_disp_output == 4) { + crop->c = vout->crop_current; + break; + } + + if (crop->c.top < b->top) + crop->c.top = b->top; + if (crop->c.top >= b->top + b->height) + crop->c.top = b->top + b->height - 1; + if (crop->c.height > b->top - crop->c.top + b->height) + crop->c.height = + b->top - crop->c.top + b->height; + + if (crop->c.left < b->left) + crop->c.left = b->left; + if (crop->c.left >= b->left + b->width) + crop->c.left = b->left + b->width - 1; + if (crop->c.width > b->left - crop->c.left + b->width) + crop->c.width = + b->left - crop->c.left + b->width; + + /* stride line limitation */ + crop->c.height -= crop->c.height % 8; + crop->c.width -= crop->c.width % 8; + + vout->crop_current = crop->c; + break; + } + case VIDIOC_ENUMOUTPUT: + { + struct v4l2_output *output = arg; + + if ((output->index >= 5) || + (vout->output_enabled[output->index] == false)) { + retval = -EINVAL; + break; + } + + if (output->index < 3) { + *output = mxc_outputs[MXC_V4L2_OUT_2_ADC]; + output->name[4] = '0' + output->index; + } else { + *output = mxc_outputs[MXC_V4L2_OUT_2_SDC]; + } + break; + } + case VIDIOC_G_OUTPUT: + { + int *p_output_num = arg; + + *p_output_num = vout->cur_disp_output; + break; + } + case VIDIOC_S_OUTPUT: + { + int *p_output_num = arg; + int fbnum; + struct v4l2_rect *b; + + if ((*p_output_num >= MXC_V4L2_OUT_NUM_OUTPUTS) || + (vout->output_enabled[*p_output_num] == false)) { + retval = -EINVAL; + break; + } + + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + + vout->cur_disp_output = *p_output_num; + + /* Update bounds in case they have changed */ + b = &vout->crop_bounds[vout->cur_disp_output]; + + fbnum = vout->output_fb_num[vout->cur_disp_output]; + if (vout->cur_disp_output == 3) + fbnum = vout->output_fb_num[4]; + + b->width = registered_fb[fbnum]->var.xres; + b->height = registered_fb[fbnum]->var.yres; + + vout->crop_current = *b; + break; + } + case VIDIOC_ENUM_FMT: + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_G_PARM: + case VIDIOC_ENUMSTD: + case VIDIOC_G_STD: + case VIDIOC_S_STD: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + default: + retval = -EINVAL; + break; + } + + up(&vout->busy_lock); + return retval; +} + +/* + * V4L2 interface - ioctl function + * + * @return None + */ +static int +mxc_v4l2out_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + return video_usercopy(inode, file, cmd, arg, mxc_v4l2out_do_ioctl); +} + +/*! + * V4L2 interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, + * ENOBUFS remap_page error + */ +static int mxc_v4l2out_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *vdev = video_devdata(file); + unsigned long size = vma->vm_end - vma->vm_start; + int res = 0; + int i; + vout_data *vout = video_get_drvdata(vdev); + + dev_dbg(vdev->dev, "pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + for (i = 0; i < vout->buffer_cnt; i++) { + if ((vout->v4l2_bufs[i].m.offset == + (vma->vm_pgoff << PAGE_SHIFT)) && + (vout->v4l2_bufs[i].length >= size)) { + vout->v4l2_bufs[i].flags |= V4L2_BUF_FLAG_MAPPED; + break; + } + } + if (i == vout->buffer_cnt) { + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + /* make buffers inner write-back, outer write-thru cacheable */ + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + dev_dbg(vdev->dev, "mmap remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + +mxc_mmap_exit: + up(&vout->busy_lock); + return res; +} + +/*! + * V4L2 interface - poll function + * + * @param file structure file * + * + * @param wait structure poll_table * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_v4l2out_poll(struct file *file, poll_table * wait) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + queue = &vout->v4l_bufq; + poll_wait(file, queue, wait); + + up(&vout->busy_lock); + return res; +} + +static struct +file_operations mxc_v4l2out_fops = { + .owner = THIS_MODULE, + .open = mxc_v4l2out_open, + .release = mxc_v4l2out_close, + .ioctl = mxc_v4l2out_ioctl, + .mmap = mxc_v4l2out_mmap, + .poll = mxc_v4l2out_poll, +}; + +static struct video_device mxc_v4l2out_template = { + .owner = THIS_MODULE, + .name = "MXC Video Output", + .type = 0, + .type2 = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING, + .fops = &mxc_v4l2out_fops, + .release = video_device_release, +}; + +/*! + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxc_v4l2out_probe(struct platform_device *pdev) +{ + int i; + vout_data *vout; + + /* + * Allocate sufficient memory for the fb structure + */ + g_vout = vout = kmalloc(sizeof(vout_data), GFP_KERNEL); + + if (!vout) + return 0; + + memset(vout, 0, sizeof(vout_data)); + + vout->video_dev = video_device_alloc(); + if (vout->video_dev == NULL) + return -1; + vout->video_dev->dev = &pdev->dev; + vout->video_dev->minor = -1; + + *(vout->video_dev) = mxc_v4l2out_template; + + /* register v4l device */ + if (video_register_device(vout->video_dev, + VFL_TYPE_GRABBER, video_nr) == -1) { + dev_dbg(&pdev->dev, "video_register_device failed\n"); + return 0; + } + dev_info(&pdev->dev, "Registered device video%d\n", + vout->video_dev->minor & 0x1f); + vout->video_dev->dev = &pdev->dev; + + video_set_drvdata(vout->video_dev, vout); + + init_MUTEX(&vout->param_lock); + init_MUTEX(&vout->busy_lock); + + /* setup outputs and cropping */ + vout->cur_disp_output = -1; + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strncmp(idstr, "DISP", 4) == 0) { + int disp_num = idstr[4] - '0'; + if (disp_num == 3) { + if (strcmp(idstr, "DISP3 BG - DI1") == 0) + disp_num = 5; + else if (strncmp(idstr, "DISP3 BG", 8) == 0) + disp_num = 4; + } + vout->crop_bounds[disp_num].left = 0; + vout->crop_bounds[disp_num].top = 0; + vout->crop_bounds[disp_num].width = + registered_fb[i]->var.xres; + vout->crop_bounds[disp_num].height = + registered_fb[i]->var.yres; + vout->output_enabled[disp_num] = true; + vout->output_fb_num[disp_num] = i; + if (vout->cur_disp_output == -1) + vout->cur_disp_output = disp_num; + } + + } + vout->crop_current = vout->crop_bounds[vout->cur_disp_output]; + + platform_set_drvdata(pdev, vout); + + return 0; +} + +static int mxc_v4l2out_remove(struct platform_device *pdev) +{ + vout_data *vout = platform_get_drvdata(pdev); + + if (vout->video_dev) { + if (-1 != vout->video_dev->minor) + video_unregister_device(vout->video_dev); + else + video_device_release(vout->video_dev); + vout->video_dev = NULL; + } + + platform_set_drvdata(pdev, NULL); + + kfree(vout); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_v4l2out_driver = { + .driver = { + .name = "MXC Video Output", + }, + .probe = mxc_v4l2out_probe, + .remove = mxc_v4l2out_remove, +}; + +static struct platform_device mxc_v4l2out_device = { + .name = "MXC Video Output", + .id = 0, +}; + +/*! + * mxc v4l2 init function + * + */ +static int mxc_v4l2out_init(void) +{ + u8 err = 0; + + err = platform_driver_register(&mxc_v4l2out_driver); + if (err == 0) + platform_device_register(&mxc_v4l2out_device); + return err; +} + +/*! + * mxc v4l2 cleanup function + * + */ +static void mxc_v4l2out_clean(void) +{ + video_unregister_device(g_vout->video_dev); + + platform_driver_unregister(&mxc_v4l2out_driver); + platform_device_unregister(&mxc_v4l2out_device); + kfree(g_vout); + g_vout = NULL; +} + +module_init(mxc_v4l2out_init); +module_exit(mxc_v4l2out_clean); + +module_param(video_nr, int, 0444); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2-driver for MXC video output"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff --git a/drivers/media/video/mxc/output/mxc_pxp_v4l2.c b/drivers/media/video/mxc/output/mxc_pxp_v4l2.c new file mode 100644 index 000000000000..2855bb675d1d --- /dev/null +++ b/drivers/media/video/mxc/output/mxc_pxp_v4l2.c @@ -0,0 +1,1237 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "mxc_pxp_v4l2.h" + +#define PXP_DRIVER_NAME "pxp-v4l2" +#define PXP_DRIVER_MAJOR 2 +#define PXP_DRIVER_MINOR 0 + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +#define V4L2_OUTPUT_TYPE_INTERNAL 4 + +static struct pxp_data_format pxp_s0_formats[] = { + { + .name = "24-bit RGB", + .bpp = 4, + .fourcc = V4L2_PIX_FMT_RGB24, + .colorspace = V4L2_COLORSPACE_SRGB, + }, { + .name = "16-bit RGB 5:6:5", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_RGB565, + .colorspace = V4L2_COLORSPACE_SRGB, + }, { + .name = "16-bit RGB 5:5:5", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_RGB555, + .colorspace = V4L2_COLORSPACE_SRGB, + }, { + .name = "YUV 4:2:0 Planar", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_YUV420, + .colorspace = V4L2_COLORSPACE_JPEG, + }, { + .name = "YUV 4:2:2 Planar", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_YUV422P, + .colorspace = V4L2_COLORSPACE_JPEG, + }, +}; + +static unsigned int v4l2_fmt_to_pxp_fmt(u32 v4l2_pix_fmt) +{ + u32 pxp_fmt = 0; + + if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB24) + pxp_fmt = PXP_PIX_FMT_RGB24; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB565) + pxp_fmt = PXP_PIX_FMT_RGB565; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555) + pxp_fmt = PXP_PIX_FMT_RGB555; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555) + pxp_fmt = PXP_PIX_FMT_RGB555; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV420) + pxp_fmt = PXP_PIX_FMT_YUV420P; + else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV422P) + pxp_fmt = PXP_PIX_FMT_YUV422P; + + return pxp_fmt; +} +struct v4l2_queryctrl pxp_controls[] = { + { + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Horizontal Flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Vertical Flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_PRIVATE_BASE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Rotation", + .minimum = 0, + .maximum = 270, + .step = 90, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_PRIVATE_BASE + 1, + .name = "Background Color", + .minimum = 0, + .maximum = 0xFFFFFF, + .step = 1, + .default_value = 0, + .flags = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_PRIVATE_BASE + 2, + .name = "Set S0 Chromakey", + .minimum = -1, + .maximum = 0xFFFFFF, + .step = 1, + .default_value = -1, + .flags = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_PRIVATE_BASE + 3, + .name = "YUV Colorspace", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + .type = V4L2_CTRL_TYPE_BOOLEAN, + }, +}; + +/* callback function */ +static void video_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct pxps *pxp = pxp_chan->client; + struct videobuf_buffer *vb; + + dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n", + tx_desc->txd.cookie, + pxp->active ? sg_dma_address(&pxp->active->sg[0]) : 0); + + spin_lock(&pxp->lock); + if (pxp->active) { + vb = &pxp->active->vb; + + list_del_init(&vb->queue); + vb->state = VIDEOBUF_DONE; + do_gettimeofday(&vb->ts); + vb->field_count++; + wake_up(&vb->done); + } + + if (list_empty(&pxp->outq)) { + pxp->active = NULL; + spin_unlock(&pxp->lock); + + return; + } + + pxp->active = list_entry(pxp->outq.next, + struct pxp_buffer, vb.queue); + pxp->active->vb.state = VIDEOBUF_ACTIVE; + spin_unlock(&pxp->lock); +} + +static int acquire_dma_channel(struct pxps *pxp) +{ + dma_cap_mask_t mask; + struct dma_chan *chan; + struct pxp_channel **pchan = &pxp->pxp_channel[0]; + + if (*pchan) { + struct videobuf_buffer *vb, *_vb; + dma_release_channel(&(*pchan)->dma_chan); + *pchan = NULL; + pxp->active = NULL; + list_for_each_entry_safe(vb, _vb, &pxp->outq, queue) { + list_del_init(&vb->queue); + vb->state = VIDEOBUF_ERROR; + wake_up(&vb->done); + } + } + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + chan = dma_request_channel(mask, NULL, NULL); + if (!chan) + return -EBUSY; + + *pchan = to_pxp_channel(chan); + (*pchan)->client = pxp; + + return 0; +} + +static int _get_fbinfo(struct fb_info **fbi) +{ + int i; + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strcmp(idstr, "mxc_elcdif_fb") == 0) { + *fbi = registered_fb[i]; + return 0; + } + } + + return -ENODEV; +} + +static int pxp_set_fbinfo(struct pxps *pxp) +{ + struct fb_info *fbi; + struct v4l2_framebuffer *fb = &pxp->fb; + int err; + + err = _get_fbinfo(&fbi); + if (err) + return err; + + fb->fmt.width = fbi->var.xres; + fb->fmt.height = fbi->var.yres; + if (fbi->var.bits_per_pixel == 16) + fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565; + else + fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24; + fb->base = (void *)fbi->fix.smem_start; + + return 0; +} + +static int _get_cur_fb_blank(struct pxps *pxp) +{ + struct fb_info *fbi; + mm_segment_t old_fs; + int err = 0; + + err = _get_fbinfo(&fbi); + if (err) + return err; + + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + err = fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_BLANK, + (unsigned int)(&pxp->fb_blank)); + set_fs(old_fs); + } + + return err; +} + +static int set_fb_blank(int blank) +{ + struct fb_info *fbi; + int err = 0; + + err = _get_fbinfo(&fbi); + if (err) + return err; + + acquire_console_sem(); + fb_blank(fbi, blank); + release_console_sem(); + + return err; +} + +static int pxp_set_cstate(struct pxps *pxp, struct v4l2_control *vc) +{ + + if (vc->id == V4L2_CID_HFLIP) { + pxp->pxp_conf.proc_data.hflip = vc->value; + } else if (vc->id == V4L2_CID_VFLIP) { + pxp->pxp_conf.proc_data.vflip = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE) { + if (vc->value % 90) + return -ERANGE; + pxp->pxp_conf.proc_data.rotate = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) { + pxp->pxp_conf.proc_data.bgcolor = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) { + pxp->pxp_conf.s0_param.color_key = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) { + pxp->pxp_conf.proc_data.yuv = vc->value; + } + + return 0; +} + +static int pxp_get_cstate(struct pxps *pxp, struct v4l2_control *vc) +{ + if (vc->id == V4L2_CID_HFLIP) + vc->value = pxp->pxp_conf.proc_data.hflip; + else if (vc->id == V4L2_CID_VFLIP) + vc->value = pxp->pxp_conf.proc_data.vflip; + else if (vc->id == V4L2_CID_PRIVATE_BASE) + vc->value = pxp->pxp_conf.proc_data.rotate; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) + vc->value = pxp->pxp_conf.proc_data.bgcolor; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) + vc->value = pxp->pxp_conf.s0_param.color_key; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) + vc->value = pxp->pxp_conf.proc_data.yuv; + + return 0; +} + +static int pxp_enumoutput(struct file *file, void *fh, + struct v4l2_output *o) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if ((o->index < 0) || (o->index > 1)) + return -EINVAL; + + memset(o, 0, sizeof(struct v4l2_output)); + if (o->index == 0) { + strcpy(o->name, "PxP Display Output"); + pxp->output = 0; + } else { + strcpy(o->name, "PxP Virtual Output"); + pxp->output = 1; + } + o->type = V4L2_OUTPUT_TYPE_INTERNAL; + o->std = 0; + o->reserved[0] = pxp->outb_phys; + + return 0; +} + +static int pxp_g_output(struct file *file, void *fh, + unsigned int *i) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + *i = pxp->output; + + return 0; +} + +static int pxp_s_output(struct file *file, void *fh, + unsigned int i) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_pix_format *fmt = &pxp->fb.fmt; + int bpp; + + if ((i < 0) || (i > 1)) + return -EINVAL; + + if (pxp->outb) + return 0; + + /* Output buffer is same format as fbdev */ + if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) + bpp = 4; + else + bpp = 2; + + pxp->outb_size = fmt->width * fmt->height * bpp; + pxp->outb = kmalloc(fmt->width * fmt->height * bpp, GFP_KERNEL); + pxp->outb_phys = virt_to_phys(pxp->outb); + dma_map_single(NULL, pxp->outb, + fmt->width * fmt->height * bpp, DMA_TO_DEVICE); + + pxp->pxp_conf.out_param.width = fmt->width; + pxp->pxp_conf.out_param.height = fmt->height; + if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) + pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB24; + else + pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB565; + + return 0; +} + +static int pxp_enum_fmt_video_output(struct file *file, void *fh, + struct v4l2_fmtdesc *fmt) +{ + enum v4l2_buf_type type = fmt->type; + int index = fmt->index; + + if ((fmt->index < 0) || (fmt->index >= ARRAY_SIZE(pxp_s0_formats))) + return -EINVAL; + + memset(fmt, 0, sizeof(struct v4l2_fmtdesc)); + fmt->index = index; + fmt->type = type; + fmt->pixelformat = pxp_s0_formats[index].fourcc; + strcpy(fmt->description, pxp_s0_formats[index].name); + + return 0; +} + +static int pxp_g_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct v4l2_pix_format *pf = &f->fmt.pix; + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct pxp_data_format *fmt = pxp->s0_fmt; + + pf->width = pxp->pxp_conf.s0_param.width; + pf->height = pxp->pxp_conf.s0_param.height; + pf->pixelformat = fmt->fourcc; + pf->field = V4L2_FIELD_NONE; + pf->bytesperline = fmt->bpp * pf->width; + pf->sizeimage = pf->bytesperline * pf->height; + pf->colorspace = fmt->colorspace; + pf->priv = 0; + + return 0; +} + +static struct pxp_data_format *pxp_get_format(struct v4l2_format *f) +{ + struct pxp_data_format *fmt; + int i; + + for (i = 0; i < ARRAY_SIZE(pxp_s0_formats); i++) { + fmt = &pxp_s0_formats[i]; + if (fmt->fourcc == f->fmt.pix.pixelformat) + break; + } + + if (i == ARRAY_SIZE(pxp_s0_formats)) + return NULL; + + return &pxp_s0_formats[i]; +} + +static int pxp_try_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + int w = f->fmt.pix.width; + int h = f->fmt.pix.height; + struct pxp_data_format *fmt = pxp_get_format(f); + + if (!fmt) + return -EINVAL; + + w = min(w, 2040); + w = max(w, 8); + h = min(h, 2040); + h = max(h, 8); + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.width = w; + f->fmt.pix.height = h; + f->fmt.pix.pixelformat = fmt->fourcc; + + return 0; +} + +static int pxp_s_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_pix_format *pf = &f->fmt.pix; + int ret; + + ret = acquire_dma_channel(pxp); + if (ret < 0) + return ret; + + ret = pxp_try_fmt_video_output(file, fh, f); + if (ret == 0) { + pxp->s0_fmt = pxp_get_format(f); + pxp->pxp_conf.s0_param.pixel_fmt = + v4l2_fmt_to_pxp_fmt(pxp->s0_fmt->fourcc); + pxp->pxp_conf.s0_param.width = pf->width; + pxp->pxp_conf.s0_param.height = pf->height; + } + + + return ret; +} + +static int pxp_g_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + + memset(wf, 0, sizeof(struct v4l2_window)); + wf->chromakey = pxp->s1_chromakey; + wf->global_alpha = pxp->global_alpha; + wf->field = V4L2_FIELD_NONE; + wf->clips = NULL; + wf->clipcount = 0; + wf->bitmap = NULL; + wf->w.left = pxp->pxp_conf.proc_data.srect.left; + wf->w.top = pxp->pxp_conf.proc_data.srect.top; + wf->w.width = pxp->pxp_conf.proc_data.srect.width; + wf->w.height = pxp->pxp_conf.proc_data.srect.height; + + return 0; +} + +static int pxp_try_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + struct v4l2_rect srect; + u32 s1_chromakey = wf->chromakey; + u8 global_alpha = wf->global_alpha; + + memcpy(&srect, &(wf->w), sizeof(struct v4l2_rect)); + + pxp_g_fmt_output_overlay(file, fh, f); + + wf->chromakey = s1_chromakey; + wf->global_alpha = global_alpha; + + /* Constrain parameters to the input buffer */ + wf->w.left = srect.left; + wf->w.top = srect.top; + wf->w.width = min(srect.width, + ((__s32)pxp->pxp_conf.s0_param.width - wf->w.left)); + wf->w.height = min(srect.height, + ((__s32)pxp->pxp_conf.s0_param.height - wf->w.top)); + + return 0; +} + +static int pxp_s_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + int ret = pxp_try_fmt_output_overlay(file, fh, f); + + if (ret == 0) { + pxp->global_alpha = wf->global_alpha; + pxp->s1_chromakey = wf->chromakey; + pxp->pxp_conf.proc_data.srect.left = wf->w.left; + pxp->pxp_conf.proc_data.srect.top = wf->w.top; + pxp->pxp_conf.proc_data.srect.width = wf->w.width; + pxp->pxp_conf.proc_data.srect.height = wf->w.height; + pxp->pxp_conf.ol_param[0].global_alpha = pxp->global_alpha; + pxp->pxp_conf.ol_param[0].color_key = pxp->s1_chromakey; + pxp->pxp_conf.ol_param[0].color_key_enable = + pxp->s1_chromakey_state; + } + + return ret; +} + +static int pxp_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *r) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_reqbufs(&pxp->s0_vbq, r); +} + +static int pxp_querybuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_querybuf(&pxp->s0_vbq, b); +} + +static int pxp_qbuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_qbuf(&pxp->s0_vbq, b); +} + +static int pxp_dqbuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_dqbuf(&pxp->s0_vbq, b, file->f_flags & O_NONBLOCK); +} + +static int pxp_streamon(struct file *file, void *priv, + enum v4l2_buf_type t) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + if (t != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + + _get_cur_fb_blank(pxp); + set_fb_blank(FB_BLANK_UNBLANK); + + ret = videobuf_streamon(&pxp->s0_vbq); + + if (!ret && (pxp->output == 0)) + mxc_elcdif_frame_addr_setup(pxp->outb_phys); + + return ret; +} + +static int pxp_streamoff(struct file *file, void *priv, + enum v4l2_buf_type t) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT)) + return -EINVAL; + + ret = videobuf_streamoff(&pxp->s0_vbq); + + if (!ret) + mxc_elcdif_frame_addr_setup((dma_addr_t)pxp->fb.base); + + if (pxp->fb_blank) + set_fb_blank(FB_BLANK_POWERDOWN); + + return ret; +} + +static int pxp_buf_setup(struct videobuf_queue *q, + unsigned int *count, unsigned *size) +{ + struct pxps *pxp = q->priv_data; + + *size = pxp->pxp_conf.s0_param.width * + pxp->pxp_conf.s0_param.height * pxp->s0_fmt->bpp; + + if (0 == *count) + *count = PXP_DEF_BUFS; + + return 0; +} + +static void pxp_buf_free(struct videobuf_queue *q, struct pxp_buffer *buf) +{ + struct videobuf_buffer *vb = &buf->vb; + struct dma_async_tx_descriptor *txd = buf->txd; + + BUG_ON(in_interrupt()); + + pr_debug("%s (vb=0x%p) 0x%08lx %d\n", __func__, + vb, vb->baddr, vb->bsize); + + /* + * This waits until this buffer is out of danger, i.e., until it is no + * longer in STATE_QUEUED or STATE_ACTIVE + */ + videobuf_waiton(vb, 0, 0); + if (txd) + async_tx_ack(txd); + + videobuf_dma_contig_free(q, vb); + buf->txd = NULL; + + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static int pxp_buf_prepare(struct videobuf_queue *q, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct pxps *pxp = q->priv_data; + struct pxp_config_data *pxp_conf = &pxp->pxp_conf; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb); + struct pxp_tx_desc *desc; + int ret = 0; + int i, length; + + vb->width = pxp->pxp_conf.s0_param.width; + vb->height = pxp->pxp_conf.s0_param.height; + vb->size = vb->width * vb->height * pxp->s0_fmt->bpp; + vb->field = V4L2_FIELD_NONE; + if (vb->state != VIDEOBUF_NEEDS_INIT) + pxp_buf_free(q, buf); + + if (vb->state == VIDEOBUF_NEEDS_INIT) { + struct pxp_channel *pchan = pxp->pxp_channel[0]; + struct scatterlist *sg = &buf->sg; + + /* This actually (allocates and) maps buffers */ + ret = videobuf_iolock(q, vb, NULL); + if (ret) { + pr_err("fail to call videobuf_iolock, ret = %d\n", ret); + goto fail; + } + + /* + * sg[0] for input(S0) + * Sg[1] for output + */ + sg_init_table(sg, 3); + + buf->txd = pchan->dma_chan.device->device_prep_slave_sg( + &pchan->dma_chan, sg, 3, DMA_FROM_DEVICE, + DMA_PREP_INTERRUPT); + if (!buf->txd) { + ret = -EIO; + goto fail; + } + + buf->txd->callback_param = buf->txd; + buf->txd->callback = video_dma_done; + + desc = to_tx_desc(buf->txd); + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) {/* S0 */ + memcpy(&desc->proc_data, proc_data, + sizeof(struct pxp_proc_data)); + pxp_conf->s0_param.paddr = + videobuf_to_dma_contig(vb); + memcpy(&desc->layer_param.s0_param, + &pxp_conf->s0_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { /* Output */ + if (proc_data->rotate % 180) { + pxp_conf->out_param.width = + pxp->fb.fmt.height; + pxp_conf->out_param.height = + pxp->fb.fmt.width; + } else { + pxp_conf->out_param.width = + pxp->fb.fmt.width; + pxp_conf->out_param.height = + pxp->fb.fmt.height; + } + + pxp_conf->out_param.paddr = pxp->outb_phys; + memcpy(&desc->layer_param.out_param, + &pxp_conf->out_param, + sizeof(struct pxp_layer_param)); + } else if (pxp_conf->ol_param[0].combine_enable) { + /* Overlay */ + pxp_conf->ol_param[0].paddr = + (dma_addr_t)pxp->fb.base; + pxp_conf->ol_param[0].width = pxp->fb.fmt.width; + pxp_conf->ol_param[0].height = + pxp->fb.fmt.height; + pxp_conf->ol_param[0].pixel_fmt = + pxp_conf->out_param.pixel_fmt; + memcpy(&desc->layer_param.ol_param, + &pxp_conf->ol_param[0], + sizeof(struct pxp_layer_param)); + } + + desc = desc->next; + } + + vb->state = VIDEOBUF_PREPARED; + } + + return 0; + +fail: + pxp_buf_free(q, buf); + return ret; +} + + +static void pxp_buf_queue(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + struct pxps *pxp = q->priv_data; + struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb); + struct dma_async_tx_descriptor *txd = buf->txd; + struct pxp_channel *pchan = pxp->pxp_channel[0]; + dma_cookie_t cookie; + + BUG_ON(!irqs_disabled()); + + list_add_tail(&vb->queue, &pxp->outq); + + if (!pxp->active) { + pxp->active = buf; + vb->state = VIDEOBUF_ACTIVE; + } else { + vb->state = VIDEOBUF_QUEUED; + } + + spin_unlock_irq(&pxp->lock); + + cookie = txd->tx_submit(txd); + dev_dbg(&pxp->pdev->dev, "Submitted cookie %d DMA 0x%08x\n", + cookie, sg_dma_address(&buf->sg[0])); + mdelay(5); + /* trigger ePxP */ + dma_async_issue_pending(&pchan->dma_chan); + + spin_lock_irq(&pxp->lock); + + if (cookie >= 0) + return; + + /* Submit error */ + pr_err("%s: Submit error\n", __func__); + vb->state = VIDEOBUF_PREPARED; + + list_del_init(&vb->queue); + + if (pxp->active == buf) + pxp->active = NULL; +} + +static void pxp_buf_release(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + struct pxps *pxp = q->priv_data; + struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb); + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) && + !list_empty(&vb->queue)) { + vb->state = VIDEOBUF_ERROR; + + list_del_init(&vb->queue); + if (pxp->active == buf) + pxp->active = NULL; + } + spin_unlock_irqrestore(&pxp->lock, flags); + + pxp_buf_free(q, buf); +} + +static struct videobuf_queue_ops pxp_vbq_ops = { + .buf_setup = pxp_buf_setup, + .buf_prepare = pxp_buf_prepare, + .buf_queue = pxp_buf_queue, + .buf_release = pxp_buf_release, +}; + +static int pxp_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + memset(cap, 0, sizeof(*cap)); + strcpy(cap->driver, "pxp"); + strcpy(cap->card, "pxp"); + strlcpy(cap->bus_info, dev_name(&pxp->pdev->dev), + sizeof(cap->bus_info)); + + cap->version = (PXP_DRIVER_MAJOR << 8) + PXP_DRIVER_MINOR; + + cap->capabilities = V4L2_CAP_VIDEO_OUTPUT | + V4L2_CAP_VIDEO_OUTPUT_OVERLAY | + V4L2_CAP_STREAMING; + + return 0; +} + +static int pxp_g_fbuf(struct file *file, void *priv, + struct v4l2_framebuffer *fb) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + memset(fb, 0, sizeof(*fb)); + + fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY | + V4L2_FBUF_CAP_CHROMAKEY | + V4L2_FBUF_CAP_LOCAL_ALPHA | + V4L2_FBUF_CAP_GLOBAL_ALPHA; + + if (pxp->global_alpha_state) + fb->flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA; + if (pxp->s1_chromakey_state) + fb->flags |= V4L2_FBUF_FLAG_CHROMAKEY; + + return 0; +} + +static int pxp_s_fbuf(struct file *file, void *priv, + struct v4l2_framebuffer *fb) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + pxp->overlay_state = + (fb->flags & V4L2_FBUF_FLAG_OVERLAY) != 0; + pxp->global_alpha_state = + (fb->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) != 0; + pxp->s1_chromakey_state = + (fb->flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0; + + pxp->pxp_conf.ol_param[0].combine_enable = pxp->overlay_state; + pxp->pxp_conf.ol_param[0].global_alpha_enable = pxp->global_alpha_state; + + return 0; +} + +static int pxp_g_crop(struct file *file, void *fh, + struct v4l2_crop *c) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) + return -EINVAL; + + c->c.left = pxp->pxp_conf.proc_data.drect.left; + c->c.top = pxp->pxp_conf.proc_data.drect.top; + c->c.width = pxp->pxp_conf.proc_data.drect.width; + c->c.height = pxp->pxp_conf.proc_data.drect.height; + + return 0; +} + +static int pxp_s_crop(struct file *file, void *fh, + struct v4l2_crop *c) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int l = c->c.left; + int t = c->c.top; + int w = c->c.width; + int h = c->c.height; + int fbw = pxp->fb.fmt.width; + int fbh = pxp->fb.fmt.height; + + if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) + return -EINVAL; + + /* Constrain parameters to FB limits */ + w = min(w, fbw); + w = max(w, PXP_MIN_PIX); + h = min(h, fbh); + h = max(h, PXP_MIN_PIX); + if ((l + w) > fbw) + l = 0; + if ((t + h) > fbh) + t = 0; + + /* Round up values to PxP pixel block */ + l = roundup(l, PXP_MIN_PIX); + t = roundup(t, PXP_MIN_PIX); + w = roundup(w, PXP_MIN_PIX); + h = roundup(h, PXP_MIN_PIX); + + pxp->pxp_conf.proc_data.drect.left = l; + pxp->pxp_conf.proc_data.drect.top = t; + pxp->pxp_conf.proc_data.drect.width = w; + pxp->pxp_conf.proc_data.drect.height = h; + + return 0; +} + +static int pxp_queryctrl(struct file *file, void *priv, + struct v4l2_queryctrl *qc) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (qc->id && qc->id == pxp_controls[i].id) { + memcpy(qc, &(pxp_controls[i]), sizeof(*qc)); + return 0; + } + + return -EINVAL; +} + +static int pxp_g_ctrl(struct file *file, void *priv, + struct v4l2_control *vc) +{ + int i; + + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (vc->id == pxp_controls[i].id) + return pxp_get_cstate(pxp, vc); + + return -EINVAL; +} + +static int pxp_s_ctrl(struct file *file, void *priv, + struct v4l2_control *vc) +{ + int i; + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (vc->id == pxp_controls[i].id) { + if (vc->value < pxp_controls[i].minimum || + vc->value > pxp_controls[i].maximum) + return -ERANGE; + return pxp_set_cstate(pxp, vc); + } + + return -EINVAL; +} + +void pxp_release(struct video_device *vfd) +{ + struct pxps *pxp = video_get_drvdata(vfd); + + spin_lock(&pxp->lock); + video_device_release(vfd); + spin_unlock(&pxp->lock); +} + +static int pxp_open(struct file *file) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + mutex_lock(&pxp->mutex); + pxp->users++; + + if (pxp->users > 1) { + pxp->users--; + ret = -EBUSY; + goto out; + } +out: + mutex_unlock(&pxp->mutex); + if (ret) + return ret; + + videobuf_queue_dma_contig_init(&pxp->s0_vbq, + &pxp_vbq_ops, + &pxp->pdev->dev, + &pxp->lock, + V4L2_BUF_TYPE_VIDEO_OUTPUT, + V4L2_FIELD_NONE, + sizeof(struct pxp_buffer), + pxp); + dev_dbg(&pxp->pdev->dev, "call pxp_open\n"); + + return 0; +} + +static int pxp_close(struct file *file) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + videobuf_stop(&pxp->s0_vbq); + videobuf_mmap_free(&pxp->s0_vbq); + pxp->active = NULL; + kfree(pxp->outb); + pxp->outb = NULL; + + mutex_lock(&pxp->mutex); + pxp->users--; + mutex_unlock(&pxp->mutex); + + return 0; +} + +static int pxp_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret; + + ret = videobuf_mmap_mapper(&pxp->s0_vbq, vma); + + return ret; +} + +static const struct v4l2_file_operations pxp_fops = { + .owner = THIS_MODULE, + .open = pxp_open, + .release = pxp_close, + .ioctl = video_ioctl2, + .mmap = pxp_mmap, +}; + +static const struct v4l2_ioctl_ops pxp_ioctl_ops = { + .vidioc_querycap = pxp_querycap, + + .vidioc_reqbufs = pxp_reqbufs, + .vidioc_querybuf = pxp_querybuf, + .vidioc_qbuf = pxp_qbuf, + .vidioc_dqbuf = pxp_dqbuf, + + .vidioc_streamon = pxp_streamon, + .vidioc_streamoff = pxp_streamoff, + + .vidioc_enum_output = pxp_enumoutput, + .vidioc_g_output = pxp_g_output, + .vidioc_s_output = pxp_s_output, + + .vidioc_enum_fmt_vid_out = pxp_enum_fmt_video_output, + .vidioc_try_fmt_vid_out = pxp_try_fmt_video_output, + .vidioc_g_fmt_vid_out = pxp_g_fmt_video_output, + .vidioc_s_fmt_vid_out = pxp_s_fmt_video_output, + + .vidioc_try_fmt_vid_out_overlay = pxp_try_fmt_output_overlay, + .vidioc_g_fmt_vid_out_overlay = pxp_g_fmt_output_overlay, + .vidioc_s_fmt_vid_out_overlay = pxp_s_fmt_output_overlay, + + .vidioc_g_fbuf = pxp_g_fbuf, + .vidioc_s_fbuf = pxp_s_fbuf, + + .vidioc_g_crop = pxp_g_crop, + .vidioc_s_crop = pxp_s_crop, + + .vidioc_queryctrl = pxp_queryctrl, + .vidioc_g_ctrl = pxp_g_ctrl, + .vidioc_s_ctrl = pxp_s_ctrl, +}; + +static const struct video_device pxp_template = { + .name = "PxP", + .vfl_type = V4L2_CAP_VIDEO_OUTPUT | + V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_STREAMING, + .fops = &pxp_fops, + .release = pxp_release, + .minor = -1, + .ioctl_ops = &pxp_ioctl_ops, +}; + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + int err = 0; + + pxp = kzalloc(sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + dev_set_drvdata(&pdev->dev, pxp); + + INIT_LIST_HEAD(&pxp->outq); + spin_lock_init(&pxp->lock); + mutex_init(&pxp->mutex); + + pxp->pdev = pdev; + + pxp->vdev = video_device_alloc(); + if (!pxp->vdev) { + dev_err(&pdev->dev, "video_device_alloc() failed\n"); + err = -ENOMEM; + goto freeirq; + } + + memcpy(pxp->vdev, &pxp_template, sizeof(pxp_template)); + video_set_drvdata(pxp->vdev, pxp); + + err = video_register_device(pxp->vdev, VFL_TYPE_GRABBER, 0); + if (err) { + dev_err(&pdev->dev, "failed to register video device\n"); + goto freevdev; + } + + err = pxp_set_fbinfo(pxp); + if (err) { + dev_err(&pdev->dev, "failed to call pxp_set_fbinfo\n"); + goto freevdev; + } + + dev_info(&pdev->dev, "initialized\n"); + +exit: + return err; + +freevdev: + video_device_release(pxp->vdev); + +freeirq: + kfree(pxp); + + return err; +} + +static int __devexit pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + video_unregister_device(pxp->vdev); + video_device_release(pxp->vdev); + + kfree(pxp); + + return 0; +} + +static struct platform_driver pxp_driver = { + .driver = { + .name = PXP_DRIVER_NAME, + }, + .probe = pxp_probe, + .remove = __exit_p(pxp_remove), +}; + + +static int __devinit pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} + +module_init(pxp_init); +module_exit(pxp_exit); + +MODULE_DESCRIPTION("MXC PxP V4L2 driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxc/output/mxc_pxp_v4l2.h b/drivers/media/video/mxc/output/mxc_pxp_v4l2.h new file mode 100644 index 000000000000..d17eea571374 --- /dev/null +++ b/drivers/media/video/mxc/output/mxc_pxp_v4l2.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X PxP driver + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#ifndef _MXC_PXP_V4L2_H +#define _MXC_PXP_V4L2_H + +#include +#include + +struct pxp_buffer { + /* Must be first! */ + struct videobuf_buffer vb; + + /* One descriptor per scatterlist (per frame) */ + struct dma_async_tx_descriptor *txd; + + struct scatterlist sg[3]; +}; + +struct pxps { + struct platform_device *pdev; + + spinlock_t lock; + struct mutex mutex; + int users; + + struct video_device *vdev; + + struct videobuf_queue s0_vbq; + struct pxp_buffer *active; + struct list_head outq; + struct pxp_channel *pxp_channel[1]; /* We need 1 channel */ + struct pxp_config_data pxp_conf; + + int output; + u32 *outb; + dma_addr_t outb_phys; + u32 outb_size; + + /* Current S0 configuration */ + struct pxp_data_format *s0_fmt; + + struct v4l2_framebuffer fb; + + /* Output overlay support */ + int overlay_state; + int global_alpha_state; + u8 global_alpha; + int s1_chromakey_state; + u32 s1_chromakey; + + int fb_blank; +}; + +struct pxp_data_format { + char *name; + unsigned int bpp; + u32 fourcc; + enum v4l2_colorspace colorspace; +}; + +#endif diff --git a/drivers/media/video/mxc/output/mxc_v4l2_output.c b/drivers/media/video/mxc/output/mxc_v4l2_output.c new file mode 100644 index 000000000000..86cd795d6bd6 --- /dev/null +++ b/drivers/media/video/mxc/output/mxc_v4l2_output.c @@ -0,0 +1,2793 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/media/video/mxc/output/mxc_v4l2_output.c + * + * @brief MXC V4L2 Video Output Driver + * + * Video4Linux2 Output Device using MXC IPU Post-processing functionality. + * + * @ingroup MXC_V4L2_OUTPUT + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_v4l2_output.h" + +#define INTERLACED_CONTENT(vout) (((cpu_is_mx51_rev(CHIP_REV_2_0) >= 1) || \ + cpu_is_mx53()) && \ + (((vout)->field_fmt == V4L2_FIELD_INTERLACED_TB) || \ + ((vout)->field_fmt == V4L2_FIELD_INTERLACED_BT))) +#define LOAD_3FIELDS(vout) ((INTERLACED_CONTENT(vout)) && \ + ((vout)->motion_sel != HIGH_MOTION)) + +struct v4l2_output mxc_outputs[1] = { + { + .index = MXC_V4L2_OUT_2_SDC, + .name = "DISP3 Video Out", + .type = V4L2_OUTPUT_TYPE_ANALOG, /* not really correct, + but no other choice */ + .audioset = 0, + .modulator = 0, + .std = V4L2_STD_UNKNOWN} +}; + +static int video_nr = 16; +static DEFINE_SPINLOCK(g_lock); +static int last_index_n; +static unsigned int ipu_ic_out_max_width_size; +static unsigned int ipu_ic_out_max_height_size; +/* debug counters */ +uint32_t g_irq_cnt; +uint32_t g_buf_output_cnt; +uint32_t g_buf_q_cnt; +uint32_t g_buf_dq_cnt; + +#define QUEUE_SIZE (MAX_FRAME_NUM + 1) +static __inline int queue_size(v4l_queue *q) +{ + if (q->tail >= q->head) + return q->tail - q->head; + else + return (q->tail + QUEUE_SIZE) - q->head; +} + +static __inline int queue_buf(v4l_queue *q, int idx) +{ + if (((q->tail + 1) % QUEUE_SIZE) == q->head) + return -1; /* queue full */ + q->list[q->tail] = idx; + q->tail = (q->tail + 1) % QUEUE_SIZE; + return 0; +} + +static __inline int dequeue_buf(v4l_queue *q) +{ + int ret; + if (q->tail == q->head) + return -1; /* queue empty */ + ret = q->list[q->head]; + q->head = (q->head + 1) % QUEUE_SIZE; + return ret; +} + +static __inline int peek_next_buf(v4l_queue *q) +{ + if (q->tail == q->head) + return -1; /* queue empty */ + return q->list[q->head]; +} + +static __inline unsigned long get_jiffies(struct timeval *t) +{ + struct timeval cur; + + if (t->tv_usec >= 1000000) { + t->tv_sec += t->tv_usec / 1000000; + t->tv_usec = t->tv_usec % 1000000; + } + + do_gettimeofday(&cur); + if ((t->tv_sec < cur.tv_sec) + || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec))) + return jiffies; + + if (t->tv_usec < cur.tv_usec) { + cur.tv_sec = t->tv_sec - cur.tv_sec - 1; + cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec; + } else { + cur.tv_sec = t->tv_sec - cur.tv_sec; + cur.tv_usec = t->tv_usec - cur.tv_usec; + } + + return jiffies + timeval_to_jiffies(&cur); +} + +/*! + * Private function to free buffers + * + * @param bufs_paddr Array of physical address of buffers to be freed + * + * @param bufs_vaddr Array of virtual address of buffers to be freed + * + * @param num_buf Number of buffers to be freed + * + * @param size Size for each buffer to be free + * + * @return status 0 success. + */ +static int mxc_free_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + if (bufs_vaddr[i] != 0) { + dma_free_coherent(0, size, bufs_vaddr[i], + bufs_paddr[i]); + pr_debug("freed @ paddr=0x%08X\n", (u32) bufs_paddr[i]); + bufs_paddr[i] = 0; + bufs_vaddr[i] = NULL; + } + } + return 0; +} + +/*! + * Private function to allocate buffers + * + * @param bufs_paddr Output array of physical address of buffers allocated + * + * @param bufs_vaddr Output array of virtual address of buffers allocated + * + * @param num_buf Input number of buffers to allocate + * + * @param size Input size for each buffer to allocate + * + * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. + */ +static int mxc_allocate_buffers(dma_addr_t bufs_paddr[], void *bufs_vaddr[], + int num_buf, int size) +{ + int i; + + for (i = 0; i < num_buf; i++) { + bufs_vaddr[i] = dma_alloc_coherent(0, size, + &bufs_paddr[i], + GFP_DMA | GFP_KERNEL); + + if (bufs_vaddr[i] == 0) { + mxc_free_buffers(bufs_paddr, bufs_vaddr, i, size); + printk(KERN_ERR "dma_alloc_coherent failed.\n"); + return -ENOBUFS; + } + pr_debug("allocated @ paddr=0x%08X, size=%d.\n", + (u32) bufs_paddr[i], size); + } + + return 0; +} + +/* + * Returns bits per pixel for given pixel format + * + * @param pixelformat V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return bits per pixel of pixelformat + */ +static u32 fmt_to_bpp(u32 pixelformat) +{ + u32 bpp; + + bpp = 8 * bytes_per_pixel(pixelformat); + return bpp; +} + +static bool format_is_yuv(u32 pixelformat) +{ + switch (pixelformat) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YVU420: + case V4L2_PIX_FMT_YUV444: + case V4L2_PIX_FMT_NV12: + return true; + break; + } + return false; +} + +static u32 bpp_to_fmt(struct fb_info *fbi) +{ + if (fbi->var.nonstd) + return fbi->var.nonstd; + + if (fbi->var.bits_per_pixel == 24) + return V4L2_PIX_FMT_BGR24; + else if (fbi->var.bits_per_pixel == 32) + return V4L2_PIX_FMT_BGR32; + else if (fbi->var.bits_per_pixel == 16) + return V4L2_PIX_FMT_RGB565; + + return 0; +} + +/* + * we are using double buffer for video playback, ipu need make + * sure current buffer should not be the same buffer of next display + * one. + */ +static int select_display_buffer(vout_data *vout, int next_buf) +{ + int ret = 0; + + vout->disp_buf_num = next_buf; + if (ipu_get_cur_buffer_idx(vout->display_ch, IPU_INPUT_BUFFER) + != next_buf) + ret = ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, + next_buf); + else + dev_dbg(&vout->video_dev->dev, + "display buffer not ready for select\n"); + return ret; +} + +static void setup_next_buf_timer(vout_data *vout, int index) +{ + unsigned long timeout; + + /* Setup timer for next buffer */ + /* if timestamp is 0, then default to 30fps */ + if ((vout->v4l2_bufs[index].timestamp.tv_sec == 0) + && (vout->v4l2_bufs[index].timestamp.tv_usec == 0) + && vout->start_jiffies) + timeout = + vout->start_jiffies + vout->frame_count * HZ / 30; + else + timeout = + get_jiffies(&vout->v4l2_bufs[index].timestamp); + + if (jiffies >= timeout) { + dev_dbg(&vout->video_dev->dev, + "warning: timer timeout already expired.\n"); + } + if (mod_timer(&vout->output_timer, timeout)) + dev_dbg(&vout->video_dev->dev, + "warning: timer was already set\n"); + + dev_dbg(&vout->video_dev->dev, + "timer handler next schedule: %lu\n", timeout); +} + +static int finish_previous_frame(vout_data *vout) +{ + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + mm_segment_t old_fs; + int ret = 0, try = 0; + + /* make sure buf[vout->disp_buf_num] in showing */ + while (ipu_check_buffer_ready(vout->display_ch, + IPU_INPUT_BUFFER, vout->disp_buf_num)) { + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + ret = fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC, + (unsigned int)NULL); + set_fs(old_fs); + + if ((ret < 0) || (try == 1)) { + /* + * ic_bypass need clear display buffer ready for next update. + * when fb doing blank and unblank, it has chance to go into + * dead loop: fb unblank just after buffer 1 ready selected. + */ + ipu_clear_buffer_ready(vout->display_ch, IPU_INPUT_BUFFER, + vout->disp_buf_num); + } + } + try++; + } + + return ret; +} + +static int show_current_frame(vout_data *vout) +{ + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + mm_segment_t old_fs; + int ret = 0; + + /* make sure buf[vout->disp_buf_num] begin to show */ + if (ipu_get_cur_buffer_idx(vout->display_ch, IPU_INPUT_BUFFER) + != vout->disp_buf_num) { + /* wait for display frame finish */ + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + ret = fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC, + (unsigned int)NULL); + set_fs(old_fs); + } + } + + return ret; +} + +static void icbypass_work_func(struct work_struct *work) +{ + vout_data *vout = + container_of(work, vout_data, icbypass_work); + int index, ret; + int last_buf; + unsigned long lock_flags = 0; + + finish_previous_frame(vout); + + spin_lock_irqsave(&g_lock, lock_flags); + + index = dequeue_buf(&vout->ready_q); + if (index == -1) { /* no buffers ready, should never occur */ + dev_err(&vout->video_dev->dev, + "mxc_v4l2out: timer - no queued buffers ready\n"); + goto exit; + } + g_buf_dq_cnt++; + vout->frame_count++; + + vout->ipu_buf[vout->next_rdy_ipu_buf] = index; + ret = ipu_update_channel_buffer(vout->display_ch, IPU_INPUT_BUFFER, + vout->next_rdy_ipu_buf, + vout->v4l2_bufs[index].m.offset); + ret += select_display_buffer(vout, vout->next_rdy_ipu_buf); + if (ret < 0) { + dev_err(&vout->video_dev->dev, + "unable to update buffer %d address rc=%d\n", + vout->next_rdy_ipu_buf, ret); + goto exit; + } + spin_unlock_irqrestore(&g_lock, lock_flags); + show_current_frame(vout); + spin_lock_irqsave(&g_lock, lock_flags); + vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf; + + last_buf = vout->ipu_buf[vout->next_done_ipu_buf]; + if (last_buf != -1) { + g_buf_output_cnt++; + vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE; + queue_buf(&vout->done_q, last_buf); + wake_up_interruptible(&vout->v4l_bufq); + vout->ipu_buf[vout->next_done_ipu_buf] = -1; + vout->next_done_ipu_buf = !vout->next_done_ipu_buf; + } + + if (g_buf_output_cnt > 0) { + /* Setup timer for next buffer */ + index = peek_next_buf(&vout->ready_q); + if (index != -1) + setup_next_buf_timer(vout, index); + else + vout->state = STATE_STREAM_PAUSED; + + if (vout->state == STATE_STREAM_STOPPING) { + if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) { + vout->state = STATE_STREAM_OFF; + } + } + } +exit: + spin_unlock_irqrestore(&g_lock, lock_flags); +} + +static int get_cur_fb_blank(vout_data *vout) +{ + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + mm_segment_t old_fs; + int ret = 0; + + /* Check BG blank first, if BG is blank, FG should be blank too */ + if (vout->display_ch == MEM_FG_SYNC) { + int i, bg_found = 0; + for (i = 0; i < num_registered_fb; i++) { + struct fb_info *bg_fbi; + char *idstr = registered_fb[i]->fix.id; + if (strncmp(idstr, "DISP3 BG", 8) == 0) { + bg_found = 1; + bg_fbi = registered_fb[i]; + if (bg_fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + ret = bg_fbi->fbops->fb_ioctl(bg_fbi, + MXCFB_GET_FB_BLANK, + (unsigned int)(&vout->fb_blank)); + set_fs(old_fs); + } + } + if (bg_found) { + if (vout->fb_blank == FB_BLANK_UNBLANK) + break; + else + return ret; + } + } + } + + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + ret = fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_BLANK, + (unsigned int)(&vout->fb_blank)); + set_fs(old_fs); + } + + return ret; +} + +static void mxc_v4l2out_timer_handler(unsigned long arg) +{ + int index, ret; + unsigned long lock_flags = 0; + vout_data *vout = (vout_data *) arg; + static int old_fb_blank = FB_BLANK_UNBLANK; + + spin_lock_irqsave(&g_lock, lock_flags); + + if ((vout->state == STATE_STREAM_STOPPING) + || (vout->state == STATE_STREAM_OFF)) + goto exit0; + + /* + * If timer occurs before IPU h/w is ready, then set the state to + * paused and the timer will be set again when next buffer is queued + * or PP comletes + */ + if (vout->ipu_buf[vout->next_rdy_ipu_buf] != -1) { + dev_dbg(&vout->video_dev->dev, "IPU buffer busy\n"); + vout->state = STATE_STREAM_PAUSED; + goto exit0; + } + + /* VDI need both buffer done before update buffer? */ + if (INTERLACED_CONTENT(vout) && + (vout->ipu_buf[!vout->next_rdy_ipu_buf] != -1)) { + dev_dbg(&vout->video_dev->dev, "IPU buffer busy\n"); + vout->state = STATE_STREAM_PAUSED; + goto exit0; + } + + /* Handle ic bypass mode in work queue */ + if (vout->ic_bypass) { + if (queue_work(vout->v4l_wq, &vout->icbypass_work) == 0) { + dev_err(&vout->video_dev->dev, + "ic bypass work was in queue already!\n "); + vout->state = STATE_STREAM_PAUSED; + } + goto exit0; + } + + get_cur_fb_blank(vout); + if (vout->fb_blank == FB_BLANK_UNBLANK) { + /* if first come back from fb blank, recover correct stack */ + if (old_fb_blank != FB_BLANK_UNBLANK) { + if (vout->next_disp_ipu_buf == 1) + ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 0); + else + ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 1); + } + if (ipu_get_cur_buffer_idx(vout->display_ch, IPU_INPUT_BUFFER) + == vout->next_disp_ipu_buf) { + dev_dbg(&vout->video_dev->dev, "IPU disp busy\n"); + index = peek_next_buf(&vout->ready_q); + setup_next_buf_timer(vout, index); + old_fb_blank = vout->fb_blank; + goto exit0; + } + } + old_fb_blank = vout->fb_blank; + + /* Dequeue buffer and pass to IPU */ + index = dequeue_buf(&vout->ready_q); + if (index == -1) { /* no buffers ready, should never occur */ + dev_err(&vout->video_dev->dev, + "mxc_v4l2out: timer - no queued buffers ready\n"); + goto exit0; + } + g_buf_dq_cnt++; + vout->frame_count++; + + /* update next buffer */ + if (LOAD_3FIELDS(vout)) { + int index_n = index; + int index_p = last_index_n; + vout->ipu_buf_p[vout->next_rdy_ipu_buf] = last_index_n; + vout->ipu_buf[vout->next_rdy_ipu_buf] = index; + vout->ipu_buf_n[vout->next_rdy_ipu_buf] = index; + ret = ipu_update_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + vout->next_rdy_ipu_buf, + vout->v4l2_bufs[index].m.offset); + ret += ipu_update_channel_buffer(MEM_VDI_PRP_VF_MEM_P, + IPU_INPUT_BUFFER, + vout->next_rdy_ipu_buf, + vout->v4l2_bufs[index_p].m.offset + vout->bytesperline); + ret += ipu_update_channel_buffer(MEM_VDI_PRP_VF_MEM_N, + IPU_INPUT_BUFFER, + vout->next_rdy_ipu_buf, + vout->v4l2_bufs[index_n].m.offset + vout->bytesperline); + last_index_n = index; + } else { + vout->ipu_buf[vout->next_rdy_ipu_buf] = index; + if (vout->pp_split) { + vout->ipu_buf[!vout->next_rdy_ipu_buf] = index; + /* always left stripe */ + ret = ipu_update_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + 0,/* vout->next_rdy_ipu_buf,*/ + (vout->v4l2_bufs[index].m.offset) + + vout->pp_left_stripe.input_column + + vout->pp_up_stripe.input_column * vout->bytesperline); + + /* the U/V offset has to be updated inside of IDMAC */ + /* according to stripe offset */ + ret += ipu_update_channel_offset(vout->post_proc_ch, + IPU_INPUT_BUFFER, + vout->v2f.fmt.pix.pixelformat, + vout->v2f.fmt.pix.width, + vout->v2f.fmt.pix.height, + vout->bytesperline, + vout->offset.u_offset, + vout->offset.v_offset, + vout->pp_up_stripe.input_column, + vout->pp_left_stripe.input_column); + } else + ret = ipu_update_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + vout->next_rdy_ipu_buf, + vout->v4l2_bufs[index].m.offset); + } + + if (ret < 0) { + dev_err(&vout->video_dev->dev, + "unable to update buffer %d address rc=%d\n", + vout->next_rdy_ipu_buf, ret); + goto exit0; + } + + /* set next buffer ready */ + if (LOAD_3FIELDS(vout)) + ret = ipu_select_multi_vdi_buffer(vout->next_rdy_ipu_buf); + else + ret = ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + vout->next_rdy_ipu_buf); + if (ret < 0) { + dev_err(&vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + goto exit0; + } + + /* Split mode use buf 0 only, no need swith buf */ + if (!vout->pp_split) + vout->next_rdy_ipu_buf = !vout->next_rdy_ipu_buf; + + /* Always assume display in double buffers */ + vout->next_disp_ipu_buf = !vout->next_disp_ipu_buf; + + /* Setup timer for next buffer */ + index = peek_next_buf(&vout->ready_q); + if (index != -1) + setup_next_buf_timer(vout, index); + else + vout->state = STATE_STREAM_PAUSED; + + if (vout->state == STATE_STREAM_STOPPING) { + if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) { + vout->state = STATE_STREAM_OFF; + } + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + + return; + +exit0: + spin_unlock_irqrestore(&g_lock, lock_flags); +} + +static irqreturn_t mxc_v4l2out_work_irq_handler(int irq, void *dev_id) +{ + int last_buf; + int index; + unsigned long lock_flags = 0; + vout_data *vout = dev_id; + int pp_out_buf_left_right = 0; + int disp_buf_num = 0; + int disp_buf_num_next = 1; + int local_buffer = 0; + int pp_out_buf_offset = 0; + int pp_out_buf_up_down = 0; + int release_buffer = 0; + u32 eba_offset = 0; + u32 vertical_offset = 0; + u16 x_pos; + u16 y_pos; + int ret = -1; + + spin_lock_irqsave(&g_lock, lock_flags); + + g_irq_cnt++; + + /* Process previous buffer */ + if (LOAD_3FIELDS(vout)) + last_buf = vout->ipu_buf_p[vout->next_done_ipu_buf]; + else + last_buf = vout->ipu_buf[vout->next_done_ipu_buf]; + + if (last_buf != -1) { + /* If IC split mode on, update output buffer number */ + if (vout->pp_split) { + pp_out_buf_up_down = vout->pp_split_buf_num & 1;/* left/right stripe */ + pp_out_buf_left_right = (vout->pp_split_buf_num >> 1) & 1; /* up/down */ + local_buffer = (vout->pp_split == 1) ? pp_out_buf_up_down : + pp_out_buf_left_right; + disp_buf_num = vout->pp_split_buf_num >> 2; + disp_buf_num_next = + ((vout->pp_split_buf_num + (vout->pp_split << 0x1)) & 7) >> 2; + if ((!pp_out_buf_left_right) || + ((!pp_out_buf_up_down) && (vout->pp_split == 1))) { + if (vout->pp_split == 1) { + eba_offset = ((pp_out_buf_left_right + pp_out_buf_up_down) & 1) ? + vout->pp_right_stripe.input_column : + vout->pp_left_stripe.input_column; + vertical_offset = pp_out_buf_up_down ? + vout->pp_up_stripe.input_column : + vout->pp_down_stripe.input_column; + + } else { + eba_offset = pp_out_buf_left_right ? + vout->pp_left_stripe.input_column : + vout->pp_right_stripe.input_column; + vertical_offset = pp_out_buf_left_right ? + vout->pp_up_stripe.input_column : + vout->pp_down_stripe.input_column; + } + + ret = ipu_update_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + (1 - local_buffer), + (vout->v4l2_bufs[vout->ipu_buf[disp_buf_num]].m.offset) + + eba_offset + vertical_offset * vout->bytesperline); + ret += ipu_update_channel_offset(vout->post_proc_ch, + IPU_INPUT_BUFFER, + vout->v2f.fmt.pix.pixelformat, + vout->v2f.fmt.pix.width, + vout->v2f.fmt.pix.height, + vout->bytesperline, + vout->offset.u_offset, + vout->offset.v_offset, + vertical_offset, + eba_offset); + + /* select right stripe */ + ret += ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + (1 - local_buffer)); + if (ret < 0) + dev_err(&vout->video_dev->dev, + "unable to set IPU buffer ready\n"); + } + + /* offset for next buffer's EBA */ + eba_offset = 0; + if (vout->pp_split == 1) { + pp_out_buf_offset = ((vout->pp_split_buf_num >> 1) & 1) ? + vout->pp_left_stripe.output_column : + vout->pp_right_stripe.output_column; + + eba_offset = ((vout->pp_split_buf_num & 1) ? + vout->pp_down_stripe.output_column : + vout->pp_up_stripe.output_column); + + } else { + pp_out_buf_offset = ((vout->pp_split_buf_num >> 1) & 1) ? + vout->pp_right_stripe.output_column : + vout->pp_left_stripe.output_column; + eba_offset = ((vout->pp_split_buf_num >> 1) & 1) ? + vout->pp_down_stripe.output_column : + vout->pp_up_stripe.output_column; + } + + if (vout->cur_disp_output == 5) { + x_pos = (vout->crop_current.left / 8) * 8; + y_pos = vout->crop_current.top; + eba_offset += (vout->xres * y_pos + x_pos) * vout->bpp / 8; + } + + + /* next buffer update */ + eba_offset = vout->display_bufs[disp_buf_num_next] + + pp_out_buf_offset + eba_offset; + + ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, + local_buffer, eba_offset); + + /* next buffer ready */ + ret = ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, local_buffer); + + /* next stripe_buffer index 0..7 */ + vout->pp_split_buf_num = (vout->pp_split_buf_num + vout->pp_split) & 0x7; + } else { + disp_buf_num = vout->next_done_ipu_buf; + ret += ipu_select_buffer(vout->display_input_ch, IPU_OUTPUT_BUFFER, + vout->next_done_ipu_buf); + } + + /* release buffer. For split mode: if second stripe is done */ + release_buffer = vout->pp_split ? (!(vout->pp_split_buf_num & 0x3)) : 1; + if (release_buffer) { + if (vout->fb_blank == FB_BLANK_UNBLANK) + select_display_buffer(vout, disp_buf_num); + g_buf_output_cnt++; + vout->v4l2_bufs[last_buf].flags = V4L2_BUF_FLAG_DONE; + queue_buf(&vout->done_q, last_buf); + wake_up_interruptible(&vout->v4l_bufq); + vout->ipu_buf[vout->next_done_ipu_buf] = -1; + if (LOAD_3FIELDS(vout)) { + vout->ipu_buf_p[vout->next_done_ipu_buf] = -1; + vout->ipu_buf_n[vout->next_done_ipu_buf] = -1; + } + /* split mode use buf 0 only, no need switch buf */ + if (!vout->pp_split) + vout->next_done_ipu_buf = !vout->next_done_ipu_buf; + } + } /* end of last_buf != -1 */ + + index = peek_next_buf(&vout->ready_q); + if (vout->state == STATE_STREAM_STOPPING) { + if ((vout->ipu_buf[0] == -1) && (vout->ipu_buf[1] == -1)) { + vout->state = STATE_STREAM_OFF; + } + } else if ((vout->state == STATE_STREAM_PAUSED) + && (index != -1)) { + /* Setup timer for next buffer, when stream has been paused */ + pr_debug("next index %d\n", index); + setup_next_buf_timer(vout, index); + vout->state = STATE_STREAM_ON; + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + + return IRQ_HANDLED; +} + +/*! + * Initialize VDI channels + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int init_VDI_channel(vout_data *vout, ipu_channel_params_t params) +{ + struct device *dev = &vout->video_dev->dev; + + if (ipu_init_channel(MEM_VDI_PRP_VF_MEM, ¶ms) != 0) { + dev_dbg(dev, "Error initializing VDI current channel\n"); + return -EINVAL; + } + if (LOAD_3FIELDS(vout)) { + if (ipu_init_channel(MEM_VDI_PRP_VF_MEM_P, ¶ms) != 0) { + dev_err(dev, "Error initializing VDI previous channel\n"); + return -EINVAL; + } + if (ipu_init_channel(MEM_VDI_PRP_VF_MEM_N, ¶ms) != 0) { + dev_err(dev, "Error initializing VDI next channel\n"); + return -EINVAL; + } + } + return 0; +} + +/*! + * Initialize VDI channel buffers + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int init_VDI_in_channel_buffer(vout_data *vout, uint32_t in_pixel_fmt, + uint16_t in_width, uint16_t in_height, + uint32_t stride, + uint32_t u_offset, uint32_t v_offset) +{ + struct device *dev = &vout->video_dev->dev; + + if (ipu_init_channel_buffer(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER, + in_pixel_fmt, in_width, in_height, stride, + IPU_ROTATE_NONE, + vout->v4l2_bufs[vout->ipu_buf[0]].m.offset, + vout->v4l2_bufs[vout->ipu_buf[0]].m.offset, + u_offset, v_offset) != 0) { + dev_err(dev, "Error initializing VDI current input buffer\n"); + return -EINVAL; + } + if (LOAD_3FIELDS(vout)) { + if (ipu_init_channel_buffer(MEM_VDI_PRP_VF_MEM_P, + IPU_INPUT_BUFFER, + in_pixel_fmt, in_width, in_height, + stride, IPU_ROTATE_NONE, + vout->v4l2_bufs[vout->ipu_buf_p[0]].m.offset+vout->bytesperline, + vout->v4l2_bufs[vout->ipu_buf_p[0]].m.offset+vout->bytesperline, + u_offset, v_offset) != 0) { + dev_err(dev, "Error initializing VDI previous input buffer\n"); + return -EINVAL; + } + if (ipu_init_channel_buffer(MEM_VDI_PRP_VF_MEM_N, + IPU_INPUT_BUFFER, + in_pixel_fmt, in_width, in_height, + stride, IPU_ROTATE_NONE, + vout->v4l2_bufs[vout->ipu_buf_n[0]].m.offset+vout->bytesperline, + vout->v4l2_bufs[vout->ipu_buf_n[0]].m.offset+vout->bytesperline, + u_offset, v_offset) != 0) { + dev_err(dev, "Error initializing VDI next input buffer\n"); + return -EINVAL; + } + } + return 0; +} + +/*! + * Initialize VDI path + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int init_VDI(ipu_channel_params_t params, vout_data *vout, + struct device *dev, struct fb_info *fbi, + u16 out_width, u16 out_height) +{ + params.mem_prp_vf_mem.in_width = vout->v2f.fmt.pix.width; + params.mem_prp_vf_mem.in_height = vout->v2f.fmt.pix.height; + params.mem_prp_vf_mem.motion_sel = vout->motion_sel; + params.mem_prp_vf_mem.field_fmt = vout->field_fmt; + params.mem_prp_vf_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat; + params.mem_prp_vf_mem.out_width = out_width; + params.mem_prp_vf_mem.out_height = out_height; + params.mem_prp_vf_mem.out_pixel_fmt = bpp_to_fmt(fbi); + + if (init_VDI_channel(vout, params) != 0) { + dev_err(dev, "Error init_VDI_channel channel\n"); + return -EINVAL; + } + + if (init_VDI_in_channel_buffer(vout, + params.mem_prp_vf_mem.in_pixel_fmt, + params.mem_prp_vf_mem.in_width, + params.mem_prp_vf_mem.in_height, + bytes_per_pixel(params.mem_prp_vf_mem. + in_pixel_fmt), + vout->offset.u_offset, + vout->offset.v_offset) != 0) { + return -EINVAL; + } + + if (!ipu_can_rotate_in_place(vout->rotate)) { + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + if (mxc_allocate_buffers + (vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size) < 0) { + return -ENOBUFS; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_prp_vf_mem. + out_pixel_fmt, out_width, + out_height, out_width, + IPU_ROTATE_NONE, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, 0) != 0) { + dev_err(dev, "Error initializing PRP output buffer\n"); + return -EINVAL; + } + + if (ipu_init_channel(MEM_ROT_VF_MEM, NULL) != 0) { + dev_err(dev, "Error initializing PP ROT channel\n"); + return -EINVAL; + } + if (ipu_init_channel_buffer(MEM_ROT_VF_MEM, + IPU_INPUT_BUFFER, + params.mem_prp_vf_mem. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, 0) != 0) { + dev_err(dev, + "Error initializing PP ROT input buffer\n"); + return -EINVAL; + } + + /* swap width and height */ + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + } + + if (ipu_init_channel_buffer(MEM_ROT_VF_MEM, + IPU_OUTPUT_BUFFER, + params.mem_prp_vf_mem. + out_pixel_fmt, out_width, + out_height, out_width, + IPU_ROTATE_NONE, + vout->display_bufs[0], + vout->display_bufs[1], 0, 0) != 0) { + dev_err(dev, + "Error initializing PP-VDI output buffer\n"); + return -EINVAL; + } + + if (ipu_link_channels(vout->post_proc_ch, MEM_ROT_VF_MEM) < 0) + return -EINVAL; + + vout->display_input_ch = MEM_ROT_VF_MEM; + ipu_enable_channel(MEM_ROT_VF_MEM); + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_ROT_VF_MEM, IPU_OUTPUT_BUFFER, 1); + } else { + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params.mem_prp_vf_mem. + out_pixel_fmt, out_width, + out_height, out_width, + vout->rotate, + vout->display_bufs[0], + vout->display_bufs[1], 0, 0) != 0) { + dev_err(dev, + "Error initializing PP-VDI output buffer\n"); + return -EINVAL; + } + } + return 0; +} + +/*! + * Initialize PP path + * + * @param params structure ipu_channel_params_t + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int init_PP(ipu_channel_params_t *params, vout_data *vout, + struct device *dev, struct fb_info *fbi, + u16 out_width, u16 out_height) +{ + u16 in_width, out_stride; /* stride of output channel */ + u32 eba_offset; + u16 x_pos; + u16 y_pos; + dma_addr_t phy_addr0; + dma_addr_t phy_addr1; + + eba_offset = 0; + x_pos = 0; + y_pos = 0; + + params->mem_pp_mem.out_pixel_fmt = bpp_to_fmt(fbi); + + if (vout->cur_disp_output == 5) { + x_pos = (vout->crop_current.left / 8) * 8; + y_pos = vout->crop_current.top; + eba_offset = (vout->xres*y_pos + x_pos) * + bytes_per_pixel(params->mem_pp_mem.out_pixel_fmt); + } + + vout->bpp = fmt_to_bpp(params->mem_pp_mem.out_pixel_fmt); + out_stride = vout->xres * + bytes_per_pixel(params->mem_pp_mem.out_pixel_fmt); + in_width = params->mem_pp_mem.in_width = vout->v2f.fmt.pix.width; + params->mem_pp_mem.in_height = vout->v2f.fmt.pix.height; + params->mem_pp_mem.in_pixel_fmt = vout->v2f.fmt.pix.pixelformat; + params->mem_pp_mem.out_width = out_width; + params->mem_pp_mem.out_height = out_height; + params->mem_pp_mem.outh_resize_ratio = 0; /* 0 means unused */ + params->mem_pp_mem.outv_resize_ratio = 0; /* 0 means unused */ + /* split IC by two stripes, the by pass is impossible*/ + if (vout->pp_split) { + vout->pp_left_stripe.input_column = 0; + vout->pp_left_stripe.output_column = 0; + vout->pp_right_stripe.input_column = 0; + vout->pp_right_stripe.output_column = 0; + vout->pp_up_stripe.input_column = 0; + vout->pp_up_stripe.output_column = 0; + vout->pp_down_stripe.input_column = 0; + vout->pp_down_stripe.output_column = 0; + if (vout->pp_split != 3) { + ipu_calc_stripes_sizes( + params->mem_pp_mem.in_width, /* input frame width;>1 */ + params->mem_pp_mem.out_width, /* output frame width; >1 */ + ipu_ic_out_max_width_size, + (((unsigned long long)1) << 32), /* 32bit for fractional*/ + 1, /* equal stripes */ + params->mem_pp_mem.in_pixel_fmt, + params->mem_pp_mem.out_pixel_fmt, + &(vout->pp_left_stripe), + &(vout->pp_right_stripe)); + + vout->pp_left_stripe.input_column = vout->pp_left_stripe.input_column * + fmt_to_bpp(vout->v2f.fmt.pix.pixelformat) / 8; + vout->pp_left_stripe.output_column = vout->pp_left_stripe.output_column * + fmt_to_bpp(params->mem_pp_mem.out_pixel_fmt) / 8; + vout->pp_right_stripe.input_column = vout->pp_right_stripe.input_column * + fmt_to_bpp(vout->v2f.fmt.pix.pixelformat) / 8; + vout->pp_right_stripe.output_column = vout->pp_right_stripe.output_column * + fmt_to_bpp(params->mem_pp_mem.out_pixel_fmt) / 8; + + + /* updare parameters */ + params->mem_pp_mem.in_width = vout->pp_left_stripe.input_width; + params->mem_pp_mem.out_width = vout->pp_left_stripe.output_width; + out_width = vout->pp_left_stripe.output_width; + /* for using in ic_init*/ + params->mem_pp_mem.outh_resize_ratio = vout->pp_left_stripe.irr; + } + if (vout->pp_split != 2) { + ipu_calc_stripes_sizes( + params->mem_pp_mem.in_height, /* input frame width;>1 */ + params->mem_pp_mem.out_height, /* output frame width; >1 */ + ipu_ic_out_max_height_size, + (((unsigned long long)1) << 32),/* 32bit for fractional */ + 1, /* equal stripes */ + params->mem_pp_mem.in_pixel_fmt, + params->mem_pp_mem.out_pixel_fmt, + &(vout->pp_up_stripe), + &(vout->pp_down_stripe)); + vout->pp_down_stripe.output_column = vout->pp_down_stripe.output_column * out_stride; + vout->pp_up_stripe.output_column = vout->pp_up_stripe.output_column * out_stride; + params->mem_pp_mem.outv_resize_ratio = vout->pp_up_stripe.irr; + params->mem_pp_mem.in_height = vout->pp_up_stripe.input_width;/*height*/ + out_height = vout->pp_up_stripe.output_width;/*height*/ + if (vout->pp_split == 3) + vout->pp_split = 2;/*2 vertical stripe as two horizontal stripes */ + } + vout->pp_split_buf_num = 0; + } + + if (ipu_init_channel(vout->post_proc_ch, params) != 0) { + dev_err(dev, "Error initializing PP channel\n"); + return -EINVAL; + } + + /* always enable double buffer */ + phy_addr0 = vout->v4l2_bufs[vout->ipu_buf[0]].m.offset; + if (vout->ipu_buf[1] == -1) + phy_addr1 = phy_addr0; + else + phy_addr1 = vout->v4l2_bufs[vout->ipu_buf[1]].m.offset; + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_INPUT_BUFFER, + params->mem_pp_mem.in_pixel_fmt, + params->mem_pp_mem.in_width, + params->mem_pp_mem.in_height, + vout->v2f.fmt.pix.bytesperline / + bytes_per_pixel(params->mem_pp_mem. + in_pixel_fmt), + IPU_ROTATE_NONE, + phy_addr0, + phy_addr1, + vout->offset.u_offset, + vout->offset.v_offset) != 0) { + dev_err(dev, "Error initializing PP input buffer\n"); + return -EINVAL; + } + + if (!ipu_can_rotate_in_place(vout->rotate)) { + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + if (mxc_allocate_buffers + (vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size) < 0) { + return -ENOBUFS; + } + + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params->mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_stride, + IPU_ROTATE_NONE, + vout->rot_pp_bufs[0] + eba_offset, + vout->rot_pp_bufs[1] + eba_offset, 0, 0) != 0) { + dev_err(dev, "Error initializing PP output buffer\n"); + return -EINVAL; + } + + if (ipu_init_channel(MEM_ROT_PP_MEM, NULL) != 0) { + dev_err(dev, "Error initializing PP ROT channel\n"); + return -EINVAL; + } + if (ipu_init_channel_buffer(MEM_ROT_PP_MEM, + IPU_INPUT_BUFFER, + params->mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_stride, + vout->rotate, + vout->rot_pp_bufs[0], + vout->rot_pp_bufs[1], 0, 0) != 0) { + dev_err(dev, + "Error initializing PP ROT input buffer\n"); + return -EINVAL; + } + + /* swap width and height */ + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + } + + if (ipu_init_channel_buffer(MEM_ROT_PP_MEM, + IPU_OUTPUT_BUFFER, + params->mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_stride, + IPU_ROTATE_NONE, + vout->display_bufs[0] + eba_offset, + vout->display_bufs[1] + eba_offset, 0, 0) != 0) { + dev_err(dev, "Error initializing PP output buffer\n"); + return -EINVAL; + } + + if (ipu_link_channels(vout->post_proc_ch, MEM_ROT_PP_MEM) < 0) + return -EINVAL; + + vout->display_input_ch = MEM_ROT_PP_MEM; + ipu_enable_channel(MEM_ROT_PP_MEM); + ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_ROT_PP_MEM, IPU_OUTPUT_BUFFER, 1); + } else { + if (ipu_init_channel_buffer(vout->post_proc_ch, + IPU_OUTPUT_BUFFER, + params->mem_pp_mem. + out_pixel_fmt, out_width, + out_height, out_stride, + vout->rotate, + vout->display_bufs[0] + eba_offset, + vout->display_bufs[1] + eba_offset, 0, 0) != 0) { + dev_err(dev, "Error initializing PP output buffer\n"); + return -EINVAL; + } + } + + /* fix EBAs for IDMAC channels */ + if (vout->pp_split) { + ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + 0, + vout->v4l2_bufs[vout->ipu_buf[0]].m.offset + + vout->pp_left_stripe.input_column + + vout->pp_up_stripe.input_column * vout->bytesperline); + + + ipu_update_channel_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, + 1, + vout->v4l2_bufs[vout->ipu_buf[0]].m.offset + + vout->pp_right_stripe.input_column + + vout->pp_up_stripe.input_column * vout->bytesperline); + + ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, + 0, + vout->display_bufs[0] + eba_offset + + vout->pp_left_stripe.output_column + + vout->pp_up_stripe.output_column); + + ipu_update_channel_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, + 1, + vout->display_bufs[0] + eba_offset + + vout->pp_right_stripe.output_column + + vout->pp_up_stripe.output_column); + } + + return 0; +} + +/*! + * Start the output stream + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamon(vout_data *vout) +{ + struct device *dev = &vout->video_dev->dev; + ipu_channel_params_t params; + struct mxcfb_pos fb_pos; + struct fb_var_screeninfo fbvar; + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + u16 out_width; + u16 out_height; + mm_segment_t old_fs; + unsigned int ipu_ch = CHAN_NONE; + unsigned int fb_fmt; + int rc = 0; + + dev_dbg(dev, "mxc_v4l2out_streamon: field format=%d\n", + vout->field_fmt); + + if (!vout) + return -EINVAL; + + if (vout->state != STATE_STREAM_OFF) + return -EBUSY; + + if (queue_size(&vout->ready_q) < 2) { + dev_err(dev, "2 buffers not been queued yet!\n"); + return -EINVAL; + } + + if ((vout->field_fmt == V4L2_FIELD_BOTTOM) || (vout->field_fmt == V4L2_FIELD_TOP)) { + dev_err(dev, "4 queued buffers need, not supported yet!\n"); + return -EINVAL; + } + + /* + * params init, check whether operation exceed the IC limitation: + * whether split mode used ( ipu version >= ipuv3 only) + */ + g_irq_cnt = g_buf_output_cnt = g_buf_q_cnt = g_buf_dq_cnt = 0; + out_width = vout->crop_current.width; + out_height = vout->crop_current.height; + vout->disp_buf_num = 0; + vout->next_done_ipu_buf = 0; + vout->next_rdy_ipu_buf = vout->next_disp_ipu_buf = 1; + vout->pp_split = 0; + ipu_ic_out_max_height_size = 1024; +#ifdef CONFIG_MXC_IPU_V1 + if (cpu_is_mx35()) + ipu_ic_out_max_width_size = 800; + else + ipu_ic_out_max_width_size = 720; +#else + ipu_ic_out_max_width_size = 1024; +#endif + if ((out_width > ipu_ic_out_max_width_size) || + (out_height > ipu_ic_out_max_height_size)) + vout->pp_split = 4; + if (!INTERLACED_CONTENT(vout)) { + vout->ipu_buf[0] = dequeue_buf(&vout->ready_q); + /* split IC by two stripes, the by pass is impossible*/ + if ((out_width != vout->v2f.fmt.pix.width || + out_height != vout->v2f.fmt.pix.height) && + vout->pp_split) { + vout->next_done_ipu_buf = vout->next_rdy_ipu_buf = 0; + vout->ipu_buf[1] = vout->ipu_buf[0]; + vout->frame_count = 1; + if ((out_width > ipu_ic_out_max_width_size) && + (out_height > ipu_ic_out_max_height_size)) + vout->pp_split = 1; /*4 stripes*/ + else if (!(out_height > ipu_ic_out_max_height_size)) + vout->pp_split = 2; /*two horizontal stripes */ + else + vout->pp_split = 3; /*2 vertical stripes*/ + } else { + vout->ipu_buf[1] = -1; + vout->frame_count = 1; + } + } else if (!LOAD_3FIELDS(vout)) { + vout->ipu_buf[0] = dequeue_buf(&vout->ready_q); + vout->ipu_buf[1] = -1; + vout->frame_count = 1; + } else { + vout->ipu_buf_p[0] = dequeue_buf(&vout->ready_q); + vout->ipu_buf[0] = dequeue_buf(&vout->ready_q); + vout->ipu_buf_n[0] = vout->ipu_buf[0]; + vout->ipu_buf_p[1] = -1; + vout->ipu_buf[1] = -1; + vout->ipu_buf_n[1] = -1; + last_index_n = vout->ipu_buf_n[0]; + vout->frame_count = 2; + } + + /* + * Bypass IC if resizing and rotation are not needed + * Meanwhile, apply IC bypass to SDC only + */ + fbvar = fbi->var; + vout->xres = fbvar.xres; + vout->yres = fbvar.yres; + + if (vout->cur_disp_output == 3 || vout->cur_disp_output == 5) { + fb_fmt = vout->v2f.fmt.pix.pixelformat; + + /* DC channel can not use CSC */ + if (vout->cur_disp_output == 5) { + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_GET_DIFMT, + (unsigned long)&fb_fmt); + set_fs(old_fs); + } + } + + fbvar.bits_per_pixel = 16; + if (format_is_yuv(fb_fmt)) + fbvar.nonstd = IPU_PIX_FMT_UYVY; + else + fbvar.nonstd = 0; + if (vout->cur_disp_output == 3) { + fbvar.xres = out_width; + fbvar.yres = out_height; + vout->xres = fbvar.xres; + vout->yres = fbvar.yres; + } + + fbvar.xres_virtual = fbvar.xres; + fbvar.yres_virtual = fbvar.yres * 2; + } + + if (out_width == vout->v2f.fmt.pix.width && + out_height == vout->v2f.fmt.pix.height && + vout->xres == out_width && + vout->yres == out_height && + ipu_can_rotate_in_place(vout->rotate) && + (vout->bytesperline == + bytes_per_pixel(vout->v2f.fmt.pix.pixelformat) * out_width) && + !INTERLACED_CONTENT(vout)) { + vout->ic_bypass = 1; + } else { + vout->ic_bypass = 0; + } + +#ifdef CONFIG_MXC_IPU_V1 + /* IPUv1 needs IC to do CSC */ + if (format_is_yuv(vout->v2f.fmt.pix.pixelformat) != + format_is_yuv(bpp_to_fmt(fbi))) +#else + /* DC channel needs IC to do CSC */ + if ((format_is_yuv(vout->v2f.fmt.pix.pixelformat) != + format_is_yuv(fb_fmt)) && + (vout->cur_disp_output == 5)) + vout->ic_bypass = 0; +#endif + + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN, + (unsigned long)&ipu_ch); + set_fs(old_fs); + } + + if (ipu_ch == CHAN_NONE) { + dev_err(dev, "Can not get display ipu channel\n"); + return -EINVAL; + } + + vout->display_ch = ipu_ch; + + if (vout->ic_bypass) { + dev_info(dev, "Bypassing IC\n"); + vout->pp_split = 0; + switch (vout->v2f.fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YVU420: + case V4L2_PIX_FMT_NV12: + fbvar.bits_per_pixel = 12; + break; + case V4L2_PIX_FMT_YUV422P: + fbvar.bits_per_pixel = 16; + break; + default: + fbvar.bits_per_pixel = 8* + bytes_per_pixel(vout->v2f.fmt.pix.pixelformat); + } + fbvar.nonstd = vout->v2f.fmt.pix.pixelformat; + } + + /* Init display channel through fb API */ + fbvar.yoffset = 0; + fbvar.activate |= FB_ACTIVATE_FORCE; + acquire_console_sem(); + fbi->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(fbi, &fbvar); + fbi->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); + + if (fbi->fbops->fb_ioctl && vout->display_ch == MEM_FG_SYNC) { + fb_pos.x = vout->crop_current.left; + fb_pos.y = vout->crop_current.top; + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS, + (unsigned long)&fb_pos); + set_fs(old_fs); + } + + vout->display_bufs[1] = fbi->fix.smem_start; + vout->display_bufs[0] = fbi->fix.smem_start + + (fbi->fix.line_length * vout->yres); + vout->display_buf_size = vout->xres * + vout->yres * fbi->var.bits_per_pixel / 8; + + /* fill black color for init fb, we assume fb has double buffer*/ + if (format_is_yuv(vout->v2f.fmt.pix.pixelformat)) { + int i; + + if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) || + (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) || + (!vout->ic_bypass)) { + short * tmp = (short *) fbi->screen_base; + short color; + if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + color = 0x8000; + else + color = 0x80; + for (i = 0; i < (fbi->fix.line_length * fbi->var.yres_virtual)/2; + i++, tmp++) + *tmp = color; + } else if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) || + (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420) || + (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)) { + char * base = (char *)fbi->screen_base; + int j, screen_size = fbi->var.xres * fbi->var.yres; + + for (j = 0; j < 2; j++) { + memset(base, 0, screen_size); + base += screen_size; + for (i = 0; i < screen_size/2; i++, base++) + *base = 0x80; + } + } else if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) { + char * base = (char *)fbi->screen_base; + int j, screen_size = fbi->var.xres * fbi->var.yres; + + for (j = 0; j < 2; j++) { + memset(base, 0, screen_size); + base += screen_size; + for (i = 0; i < screen_size; i++, base++) + *base = 0x80; + } + } + } else + memset(fbi->screen_base, 0x0, + fbi->fix.line_length * fbi->var.yres_virtual); + + if (INTERLACED_CONTENT(vout)) + vout->post_proc_ch = MEM_VDI_PRP_VF_MEM; + else if (!vout->ic_bypass) + vout->post_proc_ch = MEM_PP_MEM; + + /* Init IC channel */ + if (!vout->ic_bypass) { + if (vout->rotate >= IPU_ROTATE_90_RIGHT) { + out_width = vout->crop_current.height; + out_height = vout->crop_current.width; + } + vout->display_input_ch = vout->post_proc_ch; + memset(¶ms, 0, sizeof(params)); + if (INTERLACED_CONTENT(vout)) { + if (vout->pp_split) { + dev_err(&vout->video_dev->dev, "VDI split has not supported yet.\n"); + return -1; + } else + rc = init_VDI(params, vout, dev, fbi, out_width, out_height); + } else { + rc = init_PP(¶ms, vout, dev, fbi, out_width, out_height); + } + if (rc < 0) + return rc; + } + + if (!vout->ic_bypass) { + switch (vout->display_input_ch) { + case MEM_PP_MEM: + vout->work_irq = IPU_IRQ_PP_OUT_EOF; + break; + case MEM_VDI_PRP_VF_MEM: + vout->work_irq = IPU_IRQ_PRP_VF_OUT_EOF; + break; + case MEM_ROT_VF_MEM: + vout->work_irq = IPU_IRQ_PRP_VF_ROT_OUT_EOF; + break; + case MEM_ROT_PP_MEM: + vout->work_irq = IPU_IRQ_PP_ROT_OUT_EOF; + break; + default: + dev_err(&vout->video_dev->dev, + "not support channel, should not be here\n"); + } + } else + vout->work_irq = -1; + + if (!vout->ic_bypass && (vout->work_irq > 0)) { + ipu_clear_irq(vout->work_irq); + ipu_request_irq(vout->work_irq, + mxc_v4l2out_work_irq_handler, + 0, vout->video_dev->name, vout); + } + + vout->state = STATE_STREAM_PAUSED; + + /* Enable display and IC channels */ + if (fbi) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_UNBLANK); + release_console_sem(); + vout->fb_blank = FB_BLANK_UNBLANK; + } else { + ipu_enable_channel(vout->display_ch); + } + + /* correct display ch buffer address */ + ipu_update_channel_buffer(vout->display_ch, IPU_INPUT_BUFFER, + 0, vout->display_bufs[0]); + ipu_update_channel_buffer(vout->display_ch, IPU_INPUT_BUFFER, + 1, vout->display_bufs[1]); + + if (!vout->ic_bypass) { +#ifndef CONFIG_MXC_IPU_V1 + ipu_enable_channel(vout->post_proc_ch); +#endif + if (LOAD_3FIELDS(vout)) { + ipu_enable_channel(MEM_VDI_PRP_VF_MEM_P); + ipu_enable_channel(MEM_VDI_PRP_VF_MEM_N); + ipu_select_multi_vdi_buffer(0); + } else + ipu_select_buffer(vout->post_proc_ch, IPU_INPUT_BUFFER, 0); + ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(vout->post_proc_ch, IPU_OUTPUT_BUFFER, 1); +#ifdef CONFIG_MXC_IPU_V1 + ipu_enable_channel(vout->post_proc_ch); +#endif + } else { + ipu_update_channel_buffer(vout->display_ch, + IPU_INPUT_BUFFER, + 0, vout->v4l2_bufs[vout->ipu_buf[0]].m.offset); + if (vout->offset.u_offset || vout->offset.v_offset) + /* only update u/v offset */ + ipu_update_channel_offset(vout->display_ch, + IPU_INPUT_BUFFER, + vout->v2f.fmt.pix.pixelformat, + vout->v2f.fmt.pix.width, + vout->v2f.fmt.pix.height, + vout->bytesperline, + vout->offset.u_offset, + vout->offset.v_offset, + 0, + 0); + ipu_select_buffer(vout->display_ch, IPU_INPUT_BUFFER, 0); + queue_work(vout->v4l_wq, &vout->icbypass_work); + } + + vout->start_jiffies = jiffies; + + msleep(1); + + dev_dbg(dev, + "streamon: start time = %lu jiffies\n", vout->start_jiffies); + + return 0; +} + +/*! + * Shut down the voutera + * + * @param vout structure vout_data * + * + * @return status 0 Success + */ +static int mxc_v4l2out_streamoff(vout_data *vout) +{ + struct fb_info *fbi = + registered_fb[vout->output_fb_num[vout->cur_disp_output]]; + int i, retval = 0; + unsigned long lockflag = 0; + + if (!vout) + return -EINVAL; + + if (vout->state == STATE_STREAM_OFF) { + return 0; + } + + if (!vout->ic_bypass) + ipu_free_irq(vout->work_irq, vout); + + if (vout->ic_bypass) + cancel_work_sync(&vout->icbypass_work); + + /* fill black color for fb, we assume fb has double buffer*/ + if (format_is_yuv(vout->v2f.fmt.pix.pixelformat)) { + int i; + + if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) || + (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) || + (!vout->ic_bypass)) { + short * tmp = (short *) fbi->screen_base; + short color; + if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) + color = 0x8000; + else + color = 0x80; + for (i = 0; i < (fbi->fix.line_length * fbi->var.yres_virtual)/2; + i++, tmp++) + *tmp = color; + } else if ((vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) || + (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420) || + (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)) { + char * base = (char *)fbi->screen_base; + int j, screen_size = fbi->var.xres * fbi->var.yres; + + for (j = 0; j < 2; j++) { + memset(base, 0, screen_size); + base += screen_size; + for (i = 0; i < screen_size/2; i++, base++) + *base = 0x80; + } + } else if (vout->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) { + char * base = (char *)fbi->screen_base; + int j, screen_size = fbi->var.xres * fbi->var.yres; + + for (j = 0; j < 2; j++) { + memset(base, 0, screen_size); + base += screen_size; + for (i = 0; i < screen_size; i++, base++) + *base = 0x80; + } + } + } else + memset(fbi->screen_base, 0x0, + fbi->fix.line_length * fbi->var.yres_virtual); + + spin_lock_irqsave(&g_lock, lockflag); + + del_timer(&vout->output_timer); + + if (vout->state == STATE_STREAM_ON) { + vout->state = STATE_STREAM_STOPPING; + } + + spin_unlock_irqrestore(&g_lock, lockflag); + + if (vout->display_ch == MEM_FG_SYNC) { + struct mxcfb_pos fb_pos; + mm_segment_t old_fs; + + fb_pos.x = 0; + fb_pos.y = 0; + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS, + (unsigned long)&fb_pos); + set_fs(old_fs); + } + } + + if (vout->ic_bypass) { + fbi->var.activate |= FB_ACTIVATE_FORCE; + acquire_console_sem(); + fbi->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(fbi, &fbi->var); + fbi->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); + + if (vout->display_ch == MEM_FG_SYNC) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_POWERDOWN); + release_console_sem(); + } + + vout->display_bufs[0] = 0; + vout->display_bufs[1] = 0; + } else if (vout->post_proc_ch == MEM_PP_MEM || + vout->post_proc_ch == MEM_PRP_VF_MEM) { + /* SDC with Rotation */ + if (!ipu_can_rotate_in_place(vout->rotate)) { + ipu_unlink_channels(MEM_PP_MEM, MEM_ROT_PP_MEM); + ipu_disable_channel(MEM_ROT_PP_MEM, true); + + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + } + ipu_disable_channel(MEM_PP_MEM, true); + + fbi->var.activate |= FB_ACTIVATE_FORCE; + acquire_console_sem(); + fbi->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(fbi, &fbi->var); + fbi->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); + + if (vout->display_ch == MEM_FG_SYNC) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_POWERDOWN); + release_console_sem(); + } + + vout->display_bufs[0] = 0; + vout->display_bufs[1] = 0; + + ipu_uninit_channel(MEM_PP_MEM); + if (!ipu_can_rotate_in_place(vout->rotate)) + ipu_uninit_channel(MEM_ROT_PP_MEM); + } else if (INTERLACED_CONTENT(vout) && + (vout->post_proc_ch == MEM_VDI_PRP_VF_MEM)) { + if (!ipu_can_rotate_in_place(vout->rotate)) { + ipu_unlink_channels(MEM_VDI_PRP_VF_MEM, + MEM_ROT_VF_MEM); + ipu_disable_channel(MEM_ROT_VF_MEM, true); + + if (vout->rot_pp_bufs[0]) { + mxc_free_buffers(vout->rot_pp_bufs, + vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + } + } + + ipu_disable_channel(MEM_VDI_PRP_VF_MEM, true); + if (LOAD_3FIELDS(vout)) { + ipu_disable_channel(MEM_VDI_PRP_VF_MEM_P, true); + ipu_disable_channel(MEM_VDI_PRP_VF_MEM_N, true); + } + + fbi->var.activate |= FB_ACTIVATE_FORCE; + acquire_console_sem(); + fbi->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(fbi, &fbi->var); + fbi->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); + + if (vout->display_ch == MEM_FG_SYNC) { + acquire_console_sem(); + fb_blank(fbi, FB_BLANK_POWERDOWN); + release_console_sem(); + } + + vout->display_bufs[0] = 0; + vout->display_bufs[1] = 0; + + ipu_uninit_channel(MEM_VDI_PRP_VF_MEM); + if (LOAD_3FIELDS(vout)) { + ipu_uninit_channel(MEM_VDI_PRP_VF_MEM_P); + ipu_uninit_channel(MEM_VDI_PRP_VF_MEM_N); + } + if (!ipu_can_rotate_in_place(vout->rotate)) + ipu_uninit_channel(MEM_ROT_VF_MEM); + } + + vout->ready_q.head = vout->ready_q.tail = 0; + vout->done_q.head = vout->done_q.tail = 0; + for (i = 0; i < vout->buffer_cnt; i++) { + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + + vout->post_proc_ch = CHAN_NONE; + vout->state = STATE_STREAM_OFF; + + return retval; +} + +/* + * Valid whether the palette is supported + * + * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 + * + * @return 1 if supported, 0 if failed + */ +static inline int valid_mode(u32 palette) +{ + return ((palette == V4L2_PIX_FMT_RGB565) || + (palette == V4L2_PIX_FMT_BGR24) || + (palette == V4L2_PIX_FMT_RGB24) || + (palette == V4L2_PIX_FMT_BGR32) || + (palette == V4L2_PIX_FMT_RGB32) || + (palette == V4L2_PIX_FMT_NV12) || + (palette == V4L2_PIX_FMT_UYVY) || + (palette == V4L2_PIX_FMT_YUYV) || + (palette == V4L2_PIX_FMT_YUV422P) || + (palette == V4L2_PIX_FMT_YUV444) || + (palette == V4L2_PIX_FMT_YUV420)); +} + +/* + * V4L2 - Handles VIDIOC_G_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_g_fmt(vout_data *vout, struct v4l2_format *f) +{ + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + return -EINVAL; + } + *f = vout->v2f; + return 0; +} + +/* + * V4L2 - Handles VIDIOC_S_FMT Ioctl + * + * @param vout structure vout_data * + * + * @param v4l2_format structure v4l2_format * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_v4l2out_s_fmt(vout_data *vout, struct v4l2_format *f) +{ + int retval = 0; + u32 size = 0; + u32 bytesperline; + + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + goto err0; + } + if (!valid_mode(f->fmt.pix.pixelformat)) { + dev_err(&vout->video_dev->dev, "pixel format not supported\n"); + retval = -EINVAL; + goto err0; + } + + bytesperline = (f->fmt.pix.width * fmt_to_bpp(f->fmt.pix.pixelformat)) / + 8; + if (f->fmt.pix.bytesperline < bytesperline) { + f->fmt.pix.bytesperline = bytesperline; + } else { + bytesperline = f->fmt.pix.bytesperline; + } + vout->bytesperline = bytesperline; + + /* Based on http://v4l2spec.bytesex.org/spec/x6386.htm#V4L2-FIELD */ + vout->field_fmt = f->fmt.pix.field; + switch (vout->field_fmt) { + /* Images are in progressive format, not interlaced */ + case V4L2_FIELD_NONE: + break; + /* The two fields of a frame are passed in separate buffers, + in temporal order, i. e. the older one first. */ + case V4L2_FIELD_ALTERNATE: + dev_err(&vout->video_dev->dev, + "V4L2_FIELD_ALTERNATE field format not supported yet!\n"); + break; + case V4L2_FIELD_INTERLACED_TB: + case V4L2_FIELD_INTERLACED_BT: + if (cpu_is_mx51() || cpu_is_mx53()) + break; + dev_err(&vout->video_dev->dev, + "De-interlacing not supported in this device!\n"); + vout->field_fmt = V4L2_FIELD_NONE; + break; + default: + vout->field_fmt = V4L2_FIELD_NONE; + break; + } + + switch (f->fmt.pix.pixelformat) { + case V4L2_PIX_FMT_YUV422P: + /* byteperline for YUV planar formats is for + Y plane only */ + size = bytesperline * f->fmt.pix.height * 2; + break; + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_NV12: + size = (bytesperline * f->fmt.pix.height * 3) / 2; + break; + default: + size = bytesperline * f->fmt.pix.height; + break; + } + + /* Return the actual size of the image to the app */ + if (f->fmt.pix.sizeimage < size) { + f->fmt.pix.sizeimage = size; + } else { + size = f->fmt.pix.sizeimage; + } + + vout->v2f.fmt.pix = f->fmt.pix; + if (vout->v2f.fmt.pix.priv != 0) { + if (copy_from_user(&vout->offset, + (void *)vout->v2f.fmt.pix.priv, + sizeof(vout->offset))) { + retval = -EFAULT; + goto err0; + } + } else { + vout->offset.u_offset = 0; + vout->offset.v_offset = 0; + } + + retval = 0; + err0: + return retval; +} + +/* + * V4L2 - Handles VIDIOC_G_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_get_v42lout_control(vout_data *vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + return (vout->rotate & IPU_ROTATE_HORIZ_FLIP) ? 1 : 0; + case V4L2_CID_VFLIP: + return (vout->rotate & IPU_ROTATE_VERT_FLIP) ? 1 : 0; + case (V4L2_CID_PRIVATE_BASE + 1): + return vout->rotate; + default: + return -EINVAL; + } +} + +/* + * V4L2 - Handles VIDIOC_S_CTRL Ioctl + * + * @param vout structure vout_data * + * + * @param c structure v4l2_control * + * + * @return status 0 success, EINVAL failed + */ +static int mxc_set_v42lout_control(vout_data *vout, struct v4l2_control *c) +{ + switch (c->id) { + case V4L2_CID_HFLIP: + vout->rotate |= c->value ? IPU_ROTATE_HORIZ_FLIP : + IPU_ROTATE_NONE; + break; + case V4L2_CID_VFLIP: + vout->rotate |= c->value ? IPU_ROTATE_VERT_FLIP : + IPU_ROTATE_NONE; + break; + case V4L2_CID_MXC_ROT: + vout->rotate = c->value; + break; + case V4L2_CID_MXC_MOTION: + vout->motion_sel = c->value; + break; + default: + return -EINVAL; + } + return 0; +} + +/*! + * V4L2 interface - open function + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENODEV timeout, ERESTARTSYS interrupted by user + */ +static int mxc_v4l2out_open(struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + int err; + + if (!vout) { + return -ENODEV; + } + + down(&vout->busy_lock); + + err = -EINTR; + if (signal_pending(current)) + goto oops; + + + if (vout->open_count++ == 0) { + init_waitqueue_head(&vout->v4l_bufq); + + init_timer(&vout->output_timer); + vout->output_timer.function = mxc_v4l2out_timer_handler; + vout->output_timer.data = (unsigned long)vout; + + vout->state = STATE_STREAM_OFF; + vout->rotate = IPU_ROTATE_NONE; + + vout->v4l_wq = create_singlethread_workqueue("v4l2q"); + if (!vout->v4l_wq) { + dev_dbg(&dev->dev, + "Could not create work queue\n"); + err = -ENOMEM; + goto oops; + } + + INIT_WORK(&vout->icbypass_work, icbypass_work_func); + } + + file->private_data = dev; + + up(&vout->busy_lock); + + return 0; + + oops: + up(&vout->busy_lock); + return err; +} + +/*! + * V4L2 interface - close function + * + * @param file struct file * + * + * @return 0 success + */ +static int mxc_v4l2out_close(struct file *file) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + + if (--vout->open_count == 0) { + if (vout->state != STATE_STREAM_OFF) + mxc_v4l2out_streamoff(vout); + + file->private_data = NULL; + + mxc_free_buffers(vout->queue_buf_paddr, vout->queue_buf_vaddr, + vout->buffer_cnt, vout->queue_buf_size); + vout->buffer_cnt = 0; + mxc_free_buffers(vout->rot_pp_bufs, vout->rot_pp_bufs_vaddr, 2, + vout->display_buf_size); + + /* capture off */ + wake_up_interruptible(&vout->v4l_bufq); + + flush_workqueue(vout->v4l_wq); + destroy_workqueue(vout->v4l_wq); + } + + return 0; +} + +/*! + * V4L2 interface - ioctl function + * + * @param file struct file * + * + * @param ioctlnr unsigned int + * + * @param arg void * + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static long +mxc_v4l2out_do_ioctl(struct file *file, + unsigned int ioctlnr, void *arg) +{ + struct video_device *vdev = file->private_data; + vout_data *vout = video_get_drvdata(vdev); + int retval = 0; + int i = 0; + + if (!vout) + return -EBADF; + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EBUSY; + + switch (ioctlnr) { + case VIDIOC_QUERYCAP: + { + struct v4l2_capability *cap = arg; + strcpy(cap->driver, "mxc_v4l2_output"); + cap->version = 0; + cap->capabilities = + V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING; + cap->card[0] = '\0'; + cap->bus_info[0] = '\0'; + retval = 0; + break; + } + case VIDIOC_G_FMT: + { + struct v4l2_format *gf = arg; + retval = mxc_v4l2out_g_fmt(vout, gf); + break; + } + case VIDIOC_S_FMT: + { + struct v4l2_format *sf = arg; + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + retval = mxc_v4l2out_s_fmt(vout, sf); + break; + } + case VIDIOC_REQBUFS: + { + struct v4l2_requestbuffers *req = arg; + if ((req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (req->memory != V4L2_MEMORY_MMAP)) { + dev_dbg(&vdev->dev, + "VIDIOC_REQBUFS: incorrect buffer type\n"); + retval = -EINVAL; + break; + } + + if (req->count == 0) + mxc_v4l2out_streamoff(vout); + + if (vout->state == STATE_STREAM_OFF) { + if (vout->queue_buf_paddr[0] != 0) { + mxc_free_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + dev_dbg(&vdev->dev, + "VIDIOC_REQBUFS: freed buffers\n"); + } + vout->buffer_cnt = 0; + } else { + dev_dbg(&vdev->dev, + "VIDIOC_REQBUFS: Buffer is in use\n"); + retval = -EBUSY; + break; + } + + if (req->count == 0) + break; + + if (req->count < MIN_FRAME_NUM) { + req->count = MIN_FRAME_NUM; + } else if (req->count > MAX_FRAME_NUM) { + req->count = MAX_FRAME_NUM; + } + vout->buffer_cnt = req->count; + vout->queue_buf_size = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + + retval = mxc_allocate_buffers(vout->queue_buf_paddr, + vout->queue_buf_vaddr, + vout->buffer_cnt, + vout->queue_buf_size); + if (retval < 0) + break; + + /* Init buffer queues */ + vout->done_q.head = 0; + vout->done_q.tail = 0; + vout->ready_q.head = 0; + vout->ready_q.tail = 0; + + for (i = 0; i < vout->buffer_cnt; i++) { + memset(&(vout->v4l2_bufs[i]), 0, + sizeof(vout->v4l2_bufs[i])); + vout->v4l2_bufs[i].flags = 0; + vout->v4l2_bufs[i].memory = V4L2_MEMORY_MMAP; + vout->v4l2_bufs[i].index = i; + vout->v4l2_bufs[i].type = + V4L2_BUF_TYPE_VIDEO_OUTPUT; + vout->v4l2_bufs[i].length = + PAGE_ALIGN(vout->v2f.fmt.pix.sizeimage); + vout->v4l2_bufs[i].m.offset = + (unsigned long)vout->queue_buf_paddr[i]; + vout->v4l2_bufs[i].timestamp.tv_sec = 0; + vout->v4l2_bufs[i].timestamp.tv_usec = 0; + } + break; + } + case VIDIOC_QUERYBUF: + { + struct v4l2_buffer *buf = arg; + u32 type = buf->type; + int index = buf->index; + + if ((type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + dev_dbg(&vdev->dev, + "VIDIOC_QUERYBUFS: incorrect buffer type\n"); + retval = -EINVAL; + break; + } + down(&vout->param_lock); + memcpy(buf, &(vout->v4l2_bufs[index]), sizeof(*buf)); + up(&vout->param_lock); + break; + } + case VIDIOC_QBUF: + { + struct v4l2_buffer *buf = arg; + int index = buf->index; + unsigned long lock_flags; + int param[5][3]; + + if ((buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) || + (index >= vout->buffer_cnt)) { + retval = -EINVAL; + break; + } + + dev_dbg(&vdev->dev, "VIDIOC_QBUF: %d field = %d\n", buf->index, buf->field); + + /* mmapped buffers are L1 WB cached, + * so we need to clean them */ + if (buf->memory & V4L2_MEMORY_MMAP) { + flush_cache_all(); + } + + spin_lock_irqsave(&g_lock, lock_flags); + + memcpy(&(vout->v4l2_bufs[index]), buf, sizeof(*buf)); + vout->v4l2_bufs[index].flags |= V4L2_BUF_FLAG_QUEUED; + + g_buf_q_cnt++; + if (vout->v4l2_bufs[index].reserved) + if (!copy_from_user(¶m[0][0], + (void *)vout-> + v4l2_bufs[index] + .reserved, sizeof(param))) + ipu_set_csc_coefficients(vout-> + display_ch, + param); + queue_buf(&vout->ready_q, index); + if (vout->state == STATE_STREAM_PAUSED) { + index = peek_next_buf(&vout->ready_q); + setup_next_buf_timer(vout, index); + vout->state = STATE_STREAM_ON; + } + + spin_unlock_irqrestore(&g_lock, lock_flags); + break; + } + case VIDIOC_DQBUF: + { + struct v4l2_buffer *buf = arg; + int idx; + + if ((queue_size(&vout->done_q) == 0) && + (file->f_flags & O_NONBLOCK)) { + retval = -EAGAIN; + break; + } + + if (!wait_event_interruptible_timeout(vout->v4l_bufq, + queue_size(&vout-> + done_q) + != 0, 10 * HZ)) { + dev_dbg(&vdev->dev, "VIDIOC_DQBUF: timeout\n"); + retval = -ETIME; + break; + } else if (signal_pending(current)) { + dev_dbg(&vdev->dev, + "VIDIOC_DQBUF: interrupt received\n"); + retval = -ERESTARTSYS; + break; + } + idx = dequeue_buf(&vout->done_q); + if (idx == -1) { /* No frame free */ + dev_dbg(&vdev->dev, + "VIDIOC_DQBUF: no free buffers, returning\n"); + retval = -EAGAIN; + break; + } + if ((vout->v4l2_bufs[idx].flags & V4L2_BUF_FLAG_DONE) == + 0) + dev_dbg(&vdev->dev, + "VIDIOC_DQBUF: buffer in done q, but not " + "flagged as done\n"); + + vout->v4l2_bufs[idx].flags = 0; + memcpy(buf, &(vout->v4l2_bufs[idx]), sizeof(*buf)); + dev_dbg(&vdev->dev, "VIDIOC_DQBUF: %d\n", buf->index); + break; + } + case VIDIOC_STREAMON: + { + retval = mxc_v4l2out_streamon(vout); + break; + } + case VIDIOC_STREAMOFF: + { + retval = mxc_v4l2out_streamoff(vout); + break; + } + case VIDIOC_G_CTRL: + { + retval = mxc_get_v42lout_control(vout, arg); + break; + } + case VIDIOC_S_CTRL: + { + retval = mxc_set_v42lout_control(vout, arg); + break; + } + case VIDIOC_CROPCAP: + { + struct v4l2_cropcap *cap = arg; + + if (cap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + + cap->bounds = vout->crop_bounds[vout->cur_disp_output]; + cap->defrect = vout->crop_bounds[vout->cur_disp_output]; + retval = 0; + break; + } + case VIDIOC_G_CROP: + { + struct v4l2_crop *crop = arg; + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + crop->c = vout->crop_current; + break; + } + case VIDIOC_S_CROP: + { + struct v4l2_crop *crop = arg; + struct v4l2_rect *b = + &(vout->crop_bounds[vout->cur_disp_output]); + + if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + retval = -EINVAL; + break; + } + if (crop->c.height < 0) { + retval = -EINVAL; + break; + } + if (crop->c.width < 0) { + retval = -EINVAL; + break; + } + + /* only full screen supported for SDC BG and SDC DC */ + if (vout->cur_disp_output == 4) { + crop->c = vout->crop_current; + break; + } + + if (crop->c.top < b->top) + crop->c.top = b->top; + if (crop->c.top >= b->top + b->height) + crop->c.top = b->top + b->height - 1; + if (crop->c.height > b->top - crop->c.top + b->height) + crop->c.height = + b->top - crop->c.top + b->height; + + if (crop->c.left < b->left) + crop->c.left = b->left; + if (crop->c.left >= b->left + b->width) + crop->c.left = b->left + b->width - 1; + if (crop->c.width > b->left - crop->c.left + b->width) + crop->c.width = + b->left - crop->c.left + b->width; + + /* stride line limitation */ + crop->c.height -= crop->c.height % 8; + crop->c.width -= crop->c.width % 8; + + vout->crop_current = crop->c; + break; + } + case VIDIOC_ENUMOUTPUT: + { + struct v4l2_output *output = arg; + + if ((output->index >= 5) || + (vout->output_enabled[output->index] == false)) { + retval = -EINVAL; + break; + } + + if (output->index >= 3) + *output = mxc_outputs[MXC_V4L2_OUT_2_SDC]; + break; + } + case VIDIOC_G_OUTPUT: + { + int *p_output_num = arg; + + *p_output_num = vout->cur_disp_output; + break; + } + case VIDIOC_S_OUTPUT: + { + int *p_output_num = arg; + int fbnum; + struct v4l2_rect *b; + + if ((*p_output_num >= MXC_V4L2_OUT_NUM_OUTPUTS) || + (vout->output_enabled[*p_output_num] == false)) { + retval = -EINVAL; + break; + } + + if (vout->state != STATE_STREAM_OFF) { + retval = -EBUSY; + break; + } + + vout->cur_disp_output = *p_output_num; + + /* Update bounds in case they have changed */ + b = &vout->crop_bounds[vout->cur_disp_output]; + + fbnum = vout->output_fb_num[vout->cur_disp_output]; + + /* + * For FG overlay, it uses BG window parameter as + * limitation reference; and BG must be enabled to + * support FG. + */ + if (vout->cur_disp_output == 3) { + unsigned int i, ipu_ch = CHAN_NONE; + struct fb_info *fbi; + mm_segment_t old_fs; + + for (i = 0; i < num_registered_fb; i++) { + fbi = registered_fb[i]; + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, + MXCFB_GET_FB_IPU_CHAN, + (unsigned long)&ipu_ch); + set_fs(old_fs); + } + if (ipu_ch == CHAN_NONE) { + dev_err(&vdev->dev, + "Can't get disp ipu channel\n"); + retval = -EINVAL; + break; + } + + if (ipu_ch == MEM_BG_SYNC) { + fbnum = i; + break; + } + } + } + + b->width = registered_fb[fbnum]->var.xres; + b->height = registered_fb[fbnum]->var.yres; + + vout->crop_current = *b; + break; + } + case VIDIOC_ENUM_FMT: + case VIDIOC_TRY_FMT: + case VIDIOC_QUERYCTRL: + case VIDIOC_G_PARM: + case VIDIOC_ENUMSTD: + case VIDIOC_G_STD: + case VIDIOC_S_STD: + case VIDIOC_G_TUNER: + case VIDIOC_S_TUNER: + case VIDIOC_G_FREQUENCY: + case VIDIOC_S_FREQUENCY: + default: + retval = -EINVAL; + break; + } + + up(&vout->busy_lock); + return retval; +} + +/* + * V4L2 interface - ioctl function + * + * @return None + */ +static long +mxc_v4l2out_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + return video_usercopy(file, cmd, arg, mxc_v4l2out_do_ioctl); +} + +/*! + * V4L2 interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, + * ENOBUFS remap_page error + */ +static int mxc_v4l2out_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *vdev = video_devdata(file); + unsigned long size = vma->vm_end - vma->vm_start; + int res = 0; + int i; + vout_data *vout = video_get_drvdata(vdev); + + dev_dbg(&vdev->dev, "pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + for (i = 0; i < vout->buffer_cnt; i++) { + if ((vout->v4l2_bufs[i].m.offset == + (vma->vm_pgoff << PAGE_SHIFT)) && + (vout->v4l2_bufs[i].length >= size)) { + vout->v4l2_bufs[i].flags |= V4L2_BUF_FLAG_MAPPED; + break; + } + } + if (i == vout->buffer_cnt) { + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + /* make buffers inner write-back, outer write-thru cacheable */ + /* vma->vm_page_prot = pgprot_outer_wrthru(vma->vm_page_prot);*/ + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + dev_dbg(&vdev->dev, "mmap remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mxc_mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + + mxc_mmap_exit: + up(&vout->busy_lock); + return res; +} + +/*! + * V4L2 interface - poll function + * + * @param file structure file * + * + * @param wait structure poll_table_struct * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_v4l2out_poll(struct file *file, struct poll_table_struct * wait) +{ + struct video_device *dev = video_devdata(file); + vout_data *vout = video_get_drvdata(dev); + + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + if (down_interruptible(&vout->busy_lock)) + return -EINTR; + + queue = &vout->v4l_bufq; + poll_wait(file, queue, wait); + + up(&vout->busy_lock); + return res; +} + +static struct +v4l2_file_operations mxc_v4l2out_fops = { + .owner = THIS_MODULE, + .open = mxc_v4l2out_open, + .release = mxc_v4l2out_close, + .ioctl = mxc_v4l2out_ioctl, + .mmap = mxc_v4l2out_mmap, + .poll = mxc_v4l2out_poll, +}; + +static struct video_device mxc_v4l2out_template = { + .name = "MXC Video Output", + .vfl_type = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING, + .fops = &mxc_v4l2out_fops, + .release = video_device_release, +}; + +static ssize_t show_streaming(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct video_device *video_dev = container_of(dev, + struct video_device, dev); + vout_data *vout = video_get_drvdata(video_dev); + + if (vout->state == STATE_STREAM_OFF) + return sprintf(buf, "stream off\n"); + else if (vout->state == STATE_STREAM_PAUSED) + return sprintf(buf, "stream paused\n"); + else + return sprintf(buf, "stream on\n"); +} +static DEVICE_ATTR(fsl_v4l2_output_property, S_IRUGO, show_streaming, NULL); + +/*! + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxc_v4l2out_probe(struct platform_device *pdev) +{ + int i; + vout_data *vout; + + /* + * Allocate sufficient memory for the fb structure + */ + vout = kmalloc(sizeof(vout_data), GFP_KERNEL); + + if (!vout) + return 0; + + memset(vout, 0, sizeof(vout_data)); + + vout->video_dev = video_device_alloc(); + if (vout->video_dev == NULL) + return -1; + vout->video_dev->minor = -1; + + *(vout->video_dev) = mxc_v4l2out_template; + + /* register v4l device */ + if (video_register_device(vout->video_dev, + VFL_TYPE_GRABBER, video_nr) == -1) { + dev_dbg(&pdev->dev, "video_register_device failed\n"); + return 0; + } + dev_info(&pdev->dev, "Registered device video%d\n", + vout->video_dev->minor & 0x1f); + /*vout->video_dev->dev = &pdev->dev;*/ + + video_set_drvdata(vout->video_dev, vout); + + init_MUTEX(&vout->param_lock); + init_MUTEX(&vout->busy_lock); + + /* setup outputs and cropping */ + vout->cur_disp_output = -1; + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strncmp(idstr, "DISP", 4) == 0) { + int disp_num = idstr[4] - '0'; + if (disp_num == 3) { + if (strcmp(idstr, "DISP3 BG - DI1") == 0) + disp_num = 5; + else if (strncmp(idstr, "DISP3 BG", 8) == 0) + disp_num = 4; + } + vout->crop_bounds[disp_num].left = 0; + vout->crop_bounds[disp_num].top = 0; + vout->crop_bounds[disp_num].width = + registered_fb[i]->var.xres; + vout->crop_bounds[disp_num].height = + registered_fb[i]->var.yres; + vout->output_enabled[disp_num] = true; + vout->output_fb_num[disp_num] = i; + if (vout->cur_disp_output == -1) { + vout->cur_disp_output = disp_num; + } + } + + } + vout->crop_current = vout->crop_bounds[vout->cur_disp_output]; + + platform_set_drvdata(pdev, vout); + + if (device_create_file(&vout->video_dev->dev, + &dev_attr_fsl_v4l2_output_property)) + dev_err(&pdev->dev, "Error on creating file\n"); + + return 0; +} + +static int mxc_v4l2out_remove(struct platform_device *pdev) +{ + vout_data *vout = platform_get_drvdata(pdev); + + if (vout->video_dev) { + device_remove_file(&vout->video_dev->dev, + &dev_attr_fsl_v4l2_output_property); + video_unregister_device(vout->video_dev); + vout->video_dev = NULL; + } + + platform_set_drvdata(pdev, NULL); + + kfree(vout); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_v4l2out_driver = { + .driver = { + .name = "mxc_v4l2_output", + }, + .probe = mxc_v4l2out_probe, + .remove = mxc_v4l2out_remove, +}; + +/*! + * mxc v4l2 init function + * + */ +static int mxc_v4l2out_init(void) +{ + return platform_driver_register(&mxc_v4l2out_driver); +} + +/*! + * mxc v4l2 cleanup function + * + */ +static void mxc_v4l2out_clean(void) +{ + platform_driver_unregister(&mxc_v4l2out_driver); +} + +module_init(mxc_v4l2out_init); +module_exit(mxc_v4l2out_clean); + +module_param(video_nr, int, 0444); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("V4L2-driver for MXC video output"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("video"); diff --git a/drivers/media/video/mxc/output/mxc_v4l2_output.h b/drivers/media/video/mxc/output/mxc_v4l2_output.h new file mode 100644 index 000000000000..c26194f5ff90 --- /dev/null +++ b/drivers/media/video/mxc/output/mxc_v4l2_output.h @@ -0,0 +1,157 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup MXC_V4L2_OUTPUT MXC V4L2 Video Output Driver + */ +/*! + * @file mxc_v4l2_output.h + * + * @brief MXC V4L2 Video Output Driver Header file + * + * Video4Linux2 Output Device using MXC IPU Post-processing functionality. + * + * @ingroup MXC_V4L2_OUTPUT + */ +#ifndef __MXC_V4L2_OUTPUT_H__ +#define __MXC_V4L2_OUTPUT_H__ + +#include + +#ifdef __KERNEL__ + +#include +#include +#include + +#define MIN_FRAME_NUM 2 +#define MAX_FRAME_NUM 30 + +#define MXC_V4L2_OUT_NUM_OUTPUTS 6 +#define MXC_V4L2_OUT_2_SDC 0 + + +typedef struct { + int list[MAX_FRAME_NUM + 1]; + int head; + int tail; +} v4l_queue; + +/*! + * States for the video stream + */ +typedef enum { + STATE_STREAM_OFF, + STATE_STREAM_ON, + STATE_STREAM_PAUSED, + STATE_STREAM_STOPPING, +} v4lout_state; + +/*! + * common v4l2 driver structure. + */ +typedef struct _vout_data { + struct video_device *video_dev; + /*! + * semaphore guard against SMP multithreading + */ + struct semaphore busy_lock; + + /*! + * number of process that have device open + */ + int open_count; + + /*! + * params lock for this camera + */ + struct semaphore param_lock; + + struct timer_list output_timer; + struct workqueue_struct *v4l_wq; + struct work_struct icbypass_work; + int disp_buf_num; + int fb_blank; + unsigned long start_jiffies; + u32 frame_count; + + v4l_queue ready_q; + v4l_queue done_q; + + s8 next_rdy_ipu_buf; + s8 next_done_ipu_buf; + s8 next_disp_ipu_buf; + s8 ipu_buf[2]; + s8 ipu_buf_p[2]; + s8 ipu_buf_n[2]; + volatile v4lout_state state; + + int cur_disp_output; + int output_fb_num[MXC_V4L2_OUT_NUM_OUTPUTS]; + int output_enabled[MXC_V4L2_OUT_NUM_OUTPUTS]; + struct v4l2_framebuffer v4l2_fb; + int ic_bypass; + u32 work_irq; + ipu_channel_t display_ch; + ipu_channel_t post_proc_ch; + ipu_channel_t display_input_ch; + + /*! + * FRAME_NUM-buffering, so we need a array + */ + int buffer_cnt; + dma_addr_t queue_buf_paddr[MAX_FRAME_NUM]; + void *queue_buf_vaddr[MAX_FRAME_NUM]; + u32 queue_buf_size; + struct v4l2_buffer v4l2_bufs[MAX_FRAME_NUM]; + u32 display_buf_size; + dma_addr_t display_bufs[2]; + void *display_bufs_vaddr[2]; + dma_addr_t rot_pp_bufs[2]; + void *rot_pp_bufs_vaddr[2]; + + /*! + * Poll wait queue + */ + wait_queue_head_t v4l_bufq; + + /*! + * v4l2 format + */ + struct v4l2_format v2f; + struct v4l2_mxc_offset offset; + ipu_rotate_mode_t rotate; + + /* crop */ + struct v4l2_rect crop_bounds[MXC_V4L2_OUT_NUM_OUTPUTS]; + struct v4l2_rect crop_current; + u32 bytesperline; + enum v4l2_field field_fmt; + ipu_motion_sel motion_sel; + + /* PP split fot two stripes*/ + int pp_split; /* 0,1 */ + struct stripe_param pp_left_stripe; + struct stripe_param pp_right_stripe; /* struct for split parameters */ + struct stripe_param pp_up_stripe; + struct stripe_param pp_down_stripe; + /* IC ouput buffer number. Counting from 0 to 7 */ + int pp_split_buf_num; /* 0..7 */ + u16 bpp ; /* bit per pixel */ + u16 xres; /* width of physical frame (BGs) */ + u16 yres; /* heigth of physical frame (BGs)*/ + +} vout_data; + +#endif +#endif /* __MXC_V4L2_OUTPUT_H__ */ diff --git a/drivers/media/video/mxs_pxp.c b/drivers/media/video/mxs_pxp.c new file mode 100644 index 000000000000..93549ffe4198 --- /dev/null +++ b/drivers/media/video/mxs_pxp.c @@ -0,0 +1,1414 @@ +/* + * Freescale MXS PxP driver + * + * Author: Matt Porter + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "mxs_pxp.h" + +#define PXP_BASE_ADDR IO_ADDRESS(PXP_PHYS_ADDR) + +#define PXP_DRIVER_NAME "mxs-pxp" +#define PXP_DRIVER_MAJOR 1 +#define PXP_DRIVER_MINOR 0 + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +#define V4L2_OUTPUT_TYPE_INTERNAL 4 + +#define PXP_WAITCON ((__raw_readl(PXP_BASE_ADDR + HW_PXP_NEXT) & \ + BM_PXP_NEXT_ENABLED) != BM_PXP_NEXT_ENABLED) + +#define REG_OFFSET 0x10 +#define REGS1_NUMS 16 +#define REGS2_NUMS 5 +#define REGS3_NUMS 32 +static u32 regs1[REGS1_NUMS]; +static u32 regs2[REGS2_NUMS]; +static u32 regs3[REGS3_NUMS]; + +static struct pxp_data_format pxp_s0_formats[] = { + { + .name = "24-bit RGB", + .bpp = 4, + .fourcc = V4L2_PIX_FMT_RGB24, + .colorspace = V4L2_COLORSPACE_SRGB, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB888, + }, + { + .name = "16-bit RGB 5:6:5", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_RGB565, + .colorspace = V4L2_COLORSPACE_SRGB, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB565, + }, + { + .name = "16-bit RGB 5:5:5", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_RGB555, + .colorspace = V4L2_COLORSPACE_SRGB, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB555, + }, + { + .name = "YUV 4:2:0 Planar", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_YUV420, + .colorspace = V4L2_COLORSPACE_JPEG, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__YUV420, + }, + { + .name = "YUV 4:2:2 Planar", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_YUV422P, + .colorspace = V4L2_COLORSPACE_JPEG, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__YUV422, + }, +}; + +struct v4l2_queryctrl pxp_controls[] = { + { + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Horizontal Flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + }, + { + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Vertical Flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + }, + { + .id = V4L2_CID_PRIVATE_BASE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Rotation", + .minimum = 0, + .maximum = 270, + .step = 90, + .default_value = 0, + .flags = 0, + }, + { + .id = V4L2_CID_PRIVATE_BASE + 1, + .name = "Background Color", + .minimum = 0, + .maximum = 0xFFFFFF, + .step = 1, + .default_value = 0, + .flags = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, + { + .id = V4L2_CID_PRIVATE_BASE + 2, + .name = "Set S0 Chromakey", + .minimum = -1, + .maximum = 0xFFFFFF, + .step = 1, + .default_value = -1, + .flags = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, + { + .id = V4L2_CID_PRIVATE_BASE + 3, + .name = "YUV Colorspace", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + .type = V4L2_CTRL_TYPE_BOOLEAN, + }, +}; + +static void pxp_set_ctrl(struct pxps *pxp) +{ + u32 ctrl; + + ctrl = BF_PXP_CTRL_S0_FORMAT(pxp->s0_fmt->ctrl_s0_fmt); + ctrl |= BF_PXP_CTRL_OUTBUF_FORMAT(BV_PXP_CTRL_OUTBUF_FORMAT__RGB888); + ctrl |= BM_PXP_CTRL_CROP; + + if (pxp->scaling) + ctrl |= BM_PXP_CTRL_SCALE; + if (pxp->vflip) + ctrl |= BM_PXP_CTRL_VFLIP; + if (pxp->hflip) + ctrl |= BM_PXP_CTRL_HFLIP; + if (pxp->rotate) + ctrl |= BF_PXP_CTRL_ROTATE(pxp->rotate / 90); + + ctrl |= BM_PXP_CTRL_IRQ_ENABLE; + if (pxp->active) + ctrl |= BM_PXP_CTRL_ENABLE; + + __raw_writel(ctrl, PXP_BASE_ADDR + HW_PXP_CTRL); + pxp->regs_virt->ctrl = ctrl; +} + +static void pxp_set_outbuf(struct pxps *pxp) +{ + pxp->regs_virt->outbuf = pxp->outb_phys; + /* Always equal to the FB size */ + if (pxp->rotate % 180) + pxp->regs_virt->outsize = + BF_PXP_OUTSIZE_WIDTH(pxp->fb.fmt.height) | + BF_PXP_OUTSIZE_HEIGHT(pxp->fb.fmt.width); + else + pxp->regs_virt->outsize = + BF_PXP_OUTSIZE_WIDTH(pxp->fb.fmt.width) | + BF_PXP_OUTSIZE_HEIGHT(pxp->fb.fmt.height); +} + +static void pxp_set_s0colorkey(struct pxps *pxp) +{ + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (pxp->s0_chromakey == -1) { + /* disable color key */ + pxp->regs_virt->s0colorkeylow = 0xFFFFFF; + pxp->regs_virt->s0colorkeyhigh = 0; + } else { + pxp->regs_virt->s0colorkeylow = pxp->s0_chromakey; + pxp->regs_virt->s0colorkeyhigh = pxp->s0_chromakey; + } +} + +static void pxp_set_s1colorkey(struct pxps *pxp) +{ + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (pxp->s1_chromakey_state != 0 && pxp->s1_chromakey != -1) { + pxp->regs_virt->olcolorkeylow = pxp->s1_chromakey; + pxp->regs_virt->olcolorkeyhigh = pxp->s1_chromakey; + } else { + /* disable color key */ + pxp->regs_virt->olcolorkeylow = 0xFFFFFF; + pxp->regs_virt->olcolorkeyhigh = 0; + } +} + +static void pxp_set_oln(struct pxps *pxp) +{ + pxp->regs_virt->ol0.ol = (u32) pxp->fb.base; + if (pxp->rotate % 180) + pxp->regs_virt->ol0.olsize = + BF_PXP_OLnSIZE_WIDTH(pxp->fb.fmt.height >> 3) | + BF_PXP_OLnSIZE_HEIGHT(pxp->fb.fmt.width >> 3); + else + pxp->regs_virt->ol0.olsize = + BF_PXP_OLnSIZE_WIDTH(pxp->fb.fmt.width >> 3) | + BF_PXP_OLnSIZE_HEIGHT(pxp->fb.fmt.height >> 3); +} + +static void pxp_set_olparam(struct pxps *pxp) +{ + u32 olparam; + struct v4l2_pix_format *fmt = &pxp->fb.fmt; + + olparam = BF_PXP_OLnPARAM_ALPHA(pxp->global_alpha); + if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) + olparam |= + BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB888); + else + olparam |= + BF_PXP_OLnPARAM_FORMAT(BV_PXP_OLnPARAM_FORMAT__RGB565); + if (pxp->global_alpha_state) + olparam |= + BF_PXP_OLnPARAM_ALPHA_CNTL + (BV_PXP_OLnPARAM_ALPHA_CNTL__Override); + if (pxp->s1_chromakey_state) + olparam |= BM_PXP_OLnPARAM_ENABLE_COLORKEY; + if (pxp->overlay_state) + olparam |= BM_PXP_OLnPARAM_ENABLE; + + pxp->regs_virt->ol0.olparam = olparam; +} + +static void pxp_set_s0param(struct pxps *pxp) +{ + u32 s0param; + + s0param = BF_PXP_S0PARAM_XBASE(pxp->drect.left >> 3); + s0param |= BF_PXP_S0PARAM_YBASE(pxp->drect.top >> 3); + s0param |= BF_PXP_S0PARAM_WIDTH(pxp->s0_width >> 3); + s0param |= BF_PXP_S0PARAM_HEIGHT(pxp->s0_height >> 3); + pxp->regs_virt->s0param = s0param; +} + +static void pxp_set_s0crop(struct pxps *pxp) +{ + u32 s0crop; + + s0crop = BF_PXP_S0CROP_XBASE(pxp->srect.left >> 3); + s0crop |= BF_PXP_S0CROP_YBASE(pxp->srect.top >> 3); + s0crop |= BF_PXP_S0CROP_WIDTH(pxp->drect.width >> 3); + s0crop |= BF_PXP_S0CROP_HEIGHT(pxp->drect.height >> 3); + pxp->regs_virt->s0crop = s0crop; +} + +static int pxp_set_scaling(struct pxps *pxp) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + + if ((pxp->s0_fmt->fourcc != V4L2_PIX_FMT_YUV420) && + (pxp->s0_fmt->fourcc != V4L2_PIX_FMT_YUV422P)) { + pxp->scaling = 0; + ret = -EINVAL; + goto out; + } + + if ((pxp->srect.width == pxp->drect.width) && + (pxp->srect.height == pxp->drect.height)) { + pxp->regs_virt->s0scale = 0x10001000; + pxp->scaling = 0; + goto out; + } + + pxp->scaling = 1; + xscale = pxp->srect.width * 0x1000 / pxp->drect.width; + yscale = pxp->srect.height * 0x1000 / pxp->drect.height; + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_S0SCALE_YSCALE(yscale) | BF_PXP_S0SCALE_XSCALE(xscale); + pxp->regs_virt->s0scale = s0scale; + +out: + pxp_set_ctrl(pxp); + + return ret; +} + +static int pxp_set_fbinfo(struct pxps *pxp) +{ + struct fb_var_screeninfo var; + struct fb_fix_screeninfo fix; + struct v4l2_framebuffer *fb = &pxp->fb; + int err; + + err = mxsfb_get_info(&var, &fix); + + fb->fmt.width = var.xres; + fb->fmt.height = var.yres; + if (var.bits_per_pixel == 16) + fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565; + else + fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24; + fb->base = (void *)fix.smem_start; + return err; +} + +static void pxp_set_s0bg(struct pxps *pxp) +{ + pxp->regs_virt->s0background = pxp->s0_bgcolor; +} + +static void pxp_set_csc(struct pxps *pxp) +{ + if (pxp->yuv) { + /* YUV colorspace */ + __raw_writel(0x04030000, PXP_BASE_ADDR + HW_PXP_CSCCOEFF0); + __raw_writel(0x01230208, PXP_BASE_ADDR + HW_PXP_CSCCOEFF1); + __raw_writel(0x076b079b, PXP_BASE_ADDR + HW_PXP_CSCCOEFF2); + } else { + /* YCrCb colorspace */ + __raw_writel(0x84ab01f0, PXP_BASE_ADDR + HW_PXP_CSCCOEFF0); + __raw_writel(0x01230204, PXP_BASE_ADDR + HW_PXP_CSCCOEFF1); + __raw_writel(0x0730079c, PXP_BASE_ADDR + HW_PXP_CSCCOEFF2); + } +} + +static int pxp_set_cstate(struct pxps *pxp, struct v4l2_control *vc) +{ + + if (vc->id == V4L2_CID_HFLIP) + pxp->hflip = vc->value; + else if (vc->id == V4L2_CID_VFLIP) + pxp->vflip = vc->value; + else if (vc->id == V4L2_CID_PRIVATE_BASE) { + if (vc->value % 90) + return -ERANGE; + pxp->rotate = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) { + pxp->s0_bgcolor = vc->value; + pxp_set_s0bg(pxp); + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) { + pxp->s0_chromakey = vc->value; + pxp_set_s0colorkey(pxp); + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) { + pxp->yuv = vc->value; + pxp_set_csc(pxp); + } + + pxp_set_ctrl(pxp); + + return 0; +} + +static int pxp_get_cstate(struct pxps *pxp, struct v4l2_control *vc) +{ + if (vc->id == V4L2_CID_HFLIP) + vc->value = pxp->hflip; + else if (vc->id == V4L2_CID_VFLIP) + vc->value = pxp->vflip; + else if (vc->id == V4L2_CID_PRIVATE_BASE) + vc->value = pxp->rotate; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) + vc->value = pxp->s0_bgcolor; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) + vc->value = pxp->s0_chromakey; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) + vc->value = pxp->yuv; + + return 0; +} + +static int pxp_enumoutput(struct file *file, void *fh, struct v4l2_output *o) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if ((o->index < 0) || (o->index > 1)) + return -EINVAL; + + memset(o, 0, sizeof(struct v4l2_output)); + if (o->index == 0) { + strcpy(o->name, "PxP Display Output"); + pxp->output = 0; + } else { + strcpy(o->name, "PxP Virtual Output"); + pxp->output = 1; + } + o->type = V4L2_OUTPUT_TYPE_INTERNAL; + o->std = 0; + o->reserved[0] = pxp->outb_phys; + + return 0; +} + +static int pxp_g_output(struct file *file, void *fh, unsigned int *i) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + *i = pxp->output; + + return 0; +} + +static int pxp_s_output(struct file *file, void *fh, unsigned int i) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_pix_format *fmt = &pxp->fb.fmt; + int bpp; + + if ((i < 0) || (i > 1)) + return -EINVAL; + + if (pxp->outb) + goto out; + + /* Output buffer is same format as fbdev */ + if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) + bpp = 4; + else + bpp = 2; + + pxp->outb = kmalloc(fmt->width * fmt->height * bpp, GFP_KERNEL); + pxp->outb_phys = virt_to_phys(pxp->outb); + dma_map_single(NULL, pxp->outb, + fmt->width * fmt->height * bpp, DMA_TO_DEVICE); + +out: + pxp_set_outbuf(pxp); + + return 0; +} + +static int pxp_enum_fmt_video_output(struct file *file, void *fh, + struct v4l2_fmtdesc *fmt) +{ + enum v4l2_buf_type type = fmt->type; + int index = fmt->index; + + if ((fmt->index < 0) || (fmt->index >= ARRAY_SIZE(pxp_s0_formats))) + return -EINVAL; + + memset(fmt, 0, sizeof(struct v4l2_fmtdesc)); + fmt->index = index; + fmt->type = type; + fmt->pixelformat = pxp_s0_formats[index].fourcc; + strcpy(fmt->description, pxp_s0_formats[index].name); + + return 0; +} + +static int pxp_g_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct v4l2_pix_format *pf = &f->fmt.pix; + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct pxp_data_format *fmt = pxp->s0_fmt; + + pf->width = pxp->s0_width; + pf->height = pxp->s0_height; + pf->pixelformat = fmt->fourcc; + pf->field = V4L2_FIELD_NONE; + pf->bytesperline = fmt->bpp * pf->width; + pf->sizeimage = pf->bytesperline * pf->height; + pf->colorspace = fmt->colorspace; + pf->priv = 0; + + return 0; +} + +static struct pxp_data_format *pxp_get_format(struct v4l2_format *f) +{ + struct pxp_data_format *fmt; + int i; + + for (i = 0; i < ARRAY_SIZE(pxp_s0_formats); i++) { + fmt = &pxp_s0_formats[i]; + if (fmt->fourcc == f->fmt.pix.pixelformat) + break; + } + + if (i == ARRAY_SIZE(pxp_s0_formats)) + return NULL; + + return &pxp_s0_formats[i]; +} + +static int pxp_try_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + int w = f->fmt.pix.width; + int h = f->fmt.pix.height; + struct pxp_data_format *fmt = pxp_get_format(f); + + if (!fmt) + return -EINVAL; + + w = min(w, 2040); + w = max(w, 8); + h = min(h, 2040); + h = max(h, 8); + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.width = w; + f->fmt.pix.height = h; + f->fmt.pix.pixelformat = fmt->fourcc; + + return 0; +} + +static int pxp_s_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_pix_format *pf = &f->fmt.pix; + int ret = pxp_try_fmt_video_output(file, fh, f); + + if (ret == 0) { + pxp->s0_fmt = pxp_get_format(f); + pxp->s0_width = pf->width; + pxp->s0_height = pf->height; + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + } + + return ret; +} + +static int pxp_g_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + + memset(wf, 0, sizeof(struct v4l2_window)); + wf->chromakey = pxp->s1_chromakey; + wf->global_alpha = pxp->global_alpha; + wf->field = V4L2_FIELD_NONE; + wf->clips = NULL; + wf->clipcount = 0; + wf->bitmap = NULL; + wf->w.left = pxp->srect.left; + wf->w.top = pxp->srect.top; + wf->w.width = pxp->srect.width; + wf->w.height = pxp->srect.height; + + return 0; +} + +static int pxp_try_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + struct v4l2_rect srect; + u32 s1_chromakey = wf->chromakey; + u8 global_alpha = wf->global_alpha; + + memcpy(&srect, &(wf->w), sizeof(struct v4l2_rect)); + + pxp_g_fmt_output_overlay(file, fh, f); + + wf->chromakey = s1_chromakey; + wf->global_alpha = global_alpha; + + /* Constrain parameters to the input buffer */ + wf->w.left = srect.left; + wf->w.top = srect.top; + wf->w.width = min(srect.width, ((__s32) pxp->s0_width - wf->w.left)); + wf->w.height = min(srect.height, ((__s32) pxp->s0_height - wf->w.top)); + + return 0; +} + +static int pxp_s_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + int ret = pxp_try_fmt_output_overlay(file, fh, f); + + if (ret == 0) { + pxp->srect.left = wf->w.left; + pxp->srect.top = wf->w.top; + pxp->srect.width = wf->w.width; + pxp->srect.height = wf->w.height; + pxp->global_alpha = wf->global_alpha; + pxp->s1_chromakey = wf->chromakey; + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + pxp_set_olparam(pxp); + pxp_set_s1colorkey(pxp); + } + + return ret; +} + +static int pxp_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *r) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_reqbufs(&pxp->s0_vbq, r); +} + +static int pxp_querybuf(struct file *file, void *priv, struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_querybuf(&pxp->s0_vbq, b); +} + +static int pxp_qbuf(struct file *file, void *priv, struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_qbuf(&pxp->s0_vbq, b); +} + +static int pxp_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_dqbuf(&pxp->s0_vbq, b, file->f_flags & O_NONBLOCK); +} + +static int pxp_streamon(struct file *file, void *priv, enum v4l2_buf_type t) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT)) + return -EINVAL; + + pxp_set_outbuf(pxp); + ret = videobuf_streamon(&pxp->s0_vbq); + msleep(20); + + if (!ret && (pxp->output == 0)) + mxsfb_cfg_pxp(1, pxp->outb_phys); + + return ret; +} + +static int pxp_streamoff(struct file *file, void *priv, enum v4l2_buf_type t) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT)) + return -EINVAL; + + cancel_work_sync(&pxp->work); + ret = videobuf_streamoff(&pxp->s0_vbq); + msleep(20); + + if (!ret) + mxsfb_cfg_pxp(0, 0); + + return ret; +} + +static int pxp_buf_setup(struct videobuf_queue *q, + unsigned int *count, unsigned *size) +{ + struct pxps *pxp = q->priv_data; + + *size = pxp->s0_width * pxp->s0_height * pxp->s0_fmt->bpp; + + if (0 == *count) + *count = PXP_DEF_BUFS; + + return 0; +} + +static void pxp_buf_free(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + if (in_interrupt()) + BUG(); + + videobuf_dma_contig_free(q, vb); + + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static int pxp_buf_prepare(struct videobuf_queue *q, + struct videobuf_buffer *vb, enum v4l2_field field) +{ + struct pxps *pxp = q->priv_data; + int ret = 0; + + vb->width = pxp->s0_width; + vb->height = pxp->s0_height; + vb->size = vb->width * vb->height * pxp->s0_fmt->bpp; + vb->field = V4L2_FIELD_NONE; + vb->state = VIDEOBUF_NEEDS_INIT; + + ret = videobuf_iolock(q, vb, NULL); + if (ret) + goto fail; + vb->state = VIDEOBUF_PREPARED; + + return 0; + +fail: + pxp_buf_free(q, vb); + return ret; +} + +static void pxp_buf_next(struct pxps *pxp) +{ + dma_addr_t Y, U, V; + + if (pxp->active) { + pxp->active->state = VIDEOBUF_ACTIVE; + Y = videobuf_to_dma_contig(pxp->active); + pxp->regs_virt->s0buf = Y; + if ((pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV420) || + (pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV422P)) { + int s = 1; /* default to YUV 4:2:2 */ + if (pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV420) + s = 2; + U = Y + (pxp->s0_width * pxp->s0_height); + V = U + ((pxp->s0_width * pxp->s0_height) >> s); + pxp->regs_virt->s0ubuf = U; + pxp->regs_virt->s0vbuf = V; + } + pxp->regs_virt->ctrl = + __raw_readl(PXP_BASE_ADDR + + HW_PXP_CTRL) | BM_PXP_CTRL_ENABLE; + } + + __raw_writel(pxp->regs_phys, PXP_BASE_ADDR + HW_PXP_NEXT); +} + +static void pxp_next_handle(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + struct pxp_buffer *buf, *next; + unsigned long flags; + + if (pxp->next_queue_ended == 1) + return; + + spin_lock_irqsave(&pxp->lock, flags); + + while (!list_empty(&pxp->nextq)) { + spin_unlock_irqrestore(&pxp->lock, flags); + + if (!wait_event_interruptible_timeout(pxp->done, PXP_WAITCON, + 5 * HZ) + || signal_pending(current)) { + spin_lock_irqsave(&pxp->lock, flags); + list_for_each_entry_safe(buf, next, &pxp->nextq, queue) + list_del(&buf->queue); + spin_unlock_irqrestore(&pxp->lock, flags); + pxp->next_queue_ended = 1; + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + buf = list_entry(pxp->nextq.next, struct pxp_buffer, queue); + list_del_init(&buf->queue); + pxp->active = &buf->vb; + pxp->active->state = VIDEOBUF_QUEUED; + pxp_buf_next(pxp); + } + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxp_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + struct pxps *pxp = q->priv_data; + struct pxp_buffer *buf; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + + if (list_empty(&pxp->outq)) { + list_add_tail(&vb->queue, &pxp->outq); + vb->state = VIDEOBUF_QUEUED; + + pxp->active = vb; + pxp_buf_next(pxp); + } else { + list_add_tail(&vb->queue, &pxp->outq); + + buf = container_of(vb, struct pxp_buffer, vb); + list_add_tail(&buf->queue, &pxp->nextq); + queue_work(pxp->workqueue, &pxp->work); + } + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxp_buf_release(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + pxp_buf_free(q, vb); +} + +static struct videobuf_queue_ops pxp_vbq_ops = { + .buf_setup = pxp_buf_setup, + .buf_prepare = pxp_buf_prepare, + .buf_queue = pxp_buf_queue, + .buf_release = pxp_buf_release, +}; + +static int pxp_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + memset(cap, 0, sizeof(*cap)); + strcpy(cap->driver, "pxp"); + strcpy(cap->card, "pxp"); + strlcpy(cap->bus_info, dev_name(&pxp->pdev->dev), + sizeof(cap->bus_info)); + + cap->version = (PXP_DRIVER_MAJOR << 8) + PXP_DRIVER_MINOR; + + cap->capabilities = V4L2_CAP_VIDEO_OUTPUT | + V4L2_CAP_VIDEO_OUTPUT_OVERLAY | V4L2_CAP_STREAMING; + + return 0; +} + +static int pxp_g_fbuf(struct file *file, void *priv, + struct v4l2_framebuffer *fb) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + memset(fb, 0, sizeof(*fb)); + + fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY | + V4L2_FBUF_CAP_CHROMAKEY | + V4L2_FBUF_CAP_LOCAL_ALPHA | V4L2_FBUF_CAP_GLOBAL_ALPHA; + + if (pxp->global_alpha_state) + fb->flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA; + if (pxp->local_alpha_state) + fb->flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA; + if (pxp->s1_chromakey_state) + fb->flags |= V4L2_FBUF_FLAG_CHROMAKEY; + + return 0; +} + +static int pxp_s_fbuf(struct file *file, void *priv, + struct v4l2_framebuffer *fb) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + pxp->overlay_state = (fb->flags & V4L2_FBUF_FLAG_OVERLAY) != 0; + pxp->global_alpha_state = + (fb->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) != 0; + pxp->local_alpha_state = (fb->flags & V4L2_FBUF_FLAG_LOCAL_ALPHA) != 0; + /* Global alpha overrides local alpha if both are requested */ + if (pxp->global_alpha_state && pxp->local_alpha_state) + pxp->local_alpha_state = 0; + pxp->s1_chromakey_state = (fb->flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0; + + pxp_set_olparam(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + + return 0; +} + +static int pxp_g_crop(struct file *file, void *fh, struct v4l2_crop *c) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) + return -EINVAL; + + c->c.left = pxp->drect.left; + c->c.top = pxp->drect.top; + c->c.width = pxp->drect.width; + c->c.height = pxp->drect.height; + + return 0; +} + +static int pxp_s_crop(struct file *file, void *fh, struct v4l2_crop *c) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int l = c->c.left; + int t = c->c.top; + int w = c->c.width; + int h = c->c.height; + int fbw = pxp->fb.fmt.width; + int fbh = pxp->fb.fmt.height; + + if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) + return -EINVAL; + + /* Constrain parameters to FB limits */ + w = min(w, fbw); + w = max(w, PXP_MIN_PIX); + h = min(h, fbh); + h = max(h, PXP_MIN_PIX); + if ((l + w) > fbw) + l = 0; + if ((t + h) > fbh) + t = 0; + + /* Round up values to PxP pixel block */ + l = roundup(l, PXP_MIN_PIX); + t = roundup(t, PXP_MIN_PIX); + w = roundup(w, PXP_MIN_PIX); + h = roundup(h, PXP_MIN_PIX); + + pxp->drect.left = l; + pxp->drect.top = t; + pxp->drect.width = w; + pxp->drect.height = h; + + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + + return 0; +} + +static int pxp_queryctrl(struct file *file, void *priv, + struct v4l2_queryctrl *qc) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (qc->id && qc->id == pxp_controls[i].id) { + memcpy(qc, &(pxp_controls[i]), sizeof(*qc)); + return 0; + } + + return -EINVAL; +} + +static int pxp_g_ctrl(struct file *file, void *priv, struct v4l2_control *vc) +{ + int i; + + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (vc->id == pxp_controls[i].id) + return pxp_get_cstate(pxp, vc); + + return -EINVAL; +} + +static int pxp_s_ctrl(struct file *file, void *priv, struct v4l2_control *vc) +{ + int i; + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (vc->id == pxp_controls[i].id) { + if (vc->value < pxp_controls[i].minimum || + vc->value > pxp_controls[i].maximum) + return -ERANGE; + return pxp_set_cstate(pxp, vc); + } + + return -EINVAL; +} + +void pxp_release(struct video_device *vfd) +{ + struct pxps *pxp = video_get_drvdata(vfd); + + spin_lock(&pxp->lock); + video_device_release(vfd); + spin_unlock(&pxp->lock); +} + +static int pxp_hw_init(struct pxps *pxp) +{ + struct fb_var_screeninfo var; + struct fb_fix_screeninfo fix; + int err; + + err = mxsfb_get_info(&var, &fix); + if (err) + return err; + + /* Pull PxP out of reset */ + __raw_writel(0, PXP_BASE_ADDR + HW_PXP_CTRL); + + /* Config defaults */ + pxp->active = NULL; + + pxp->s0_fmt = &pxp_s0_formats[0]; + pxp->drect.left = pxp->srect.left = 0; + pxp->drect.top = pxp->srect.top = 0; + pxp->drect.width = pxp->srect.width = pxp->s0_width = var.xres; + pxp->drect.height = pxp->srect.height = pxp->s0_height = var.yres; + pxp->s0_bgcolor = 0; + + pxp->output = 0; + err = pxp_set_fbinfo(pxp); + if (err) + return err; + + pxp->scaling = 0; + pxp->hflip = 0; + pxp->vflip = 0; + pxp->rotate = 0; + pxp->yuv = 0; + + pxp->overlay_state = 0; + pxp->global_alpha_state = 0; + pxp->global_alpha = 0; + pxp->local_alpha_state = 0; + pxp->s1_chromakey_state = 0; + pxp->s1_chromakey = -1; + pxp->s0_chromakey = -1; + + /* Write default h/w config */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_oln(pxp); + pxp_set_olparam(pxp); + pxp_set_s0colorkey(pxp); + pxp_set_s1colorkey(pxp); + pxp_set_csc(pxp); + + return 0; +} + +static int pxp_open(struct file *file) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + mutex_lock(&pxp->mutex); + pxp->users++; + + if (pxp->users > 1) { + pxp->users--; + ret = -EBUSY; + goto out; + } +out: + mutex_unlock(&pxp->mutex); + if (ret) + return ret; + + pxp->next_queue_ended = 0; + pxp->workqueue = create_singlethread_workqueue("pxp"); + + videobuf_queue_dma_contig_init(&pxp->s0_vbq, + &pxp_vbq_ops, + &pxp->pdev->dev, + &pxp->lock, + V4L2_BUF_TYPE_VIDEO_OUTPUT, + V4L2_FIELD_NONE, + sizeof(struct pxp_buffer), pxp); + + return 0; +} + +static int pxp_close(struct file *file) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if (pxp->workqueue) { + flush_workqueue(pxp->workqueue); + destroy_workqueue(pxp->workqueue); + } + + videobuf_stop(&pxp->s0_vbq); + videobuf_mmap_free(&pxp->s0_vbq); + pxp->active = NULL; + + mutex_lock(&pxp->mutex); + pxp->users--; + mutex_unlock(&pxp->mutex); + + return 0; +} + +static int pxp_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret; + + ret = videobuf_mmap_mapper(&pxp->s0_vbq, vma); + + return ret; +} + +static const struct v4l2_file_operations pxp_fops = { + .owner = THIS_MODULE, + .open = pxp_open, + .release = pxp_close, + .ioctl = video_ioctl2, + .mmap = pxp_mmap, +}; + +static const struct v4l2_ioctl_ops pxp_ioctl_ops = { + .vidioc_querycap = pxp_querycap, + + .vidioc_reqbufs = pxp_reqbufs, + .vidioc_querybuf = pxp_querybuf, + .vidioc_qbuf = pxp_qbuf, + .vidioc_dqbuf = pxp_dqbuf, + + .vidioc_streamon = pxp_streamon, + .vidioc_streamoff = pxp_streamoff, + + .vidioc_enum_output = pxp_enumoutput, + .vidioc_g_output = pxp_g_output, + .vidioc_s_output = pxp_s_output, + + .vidioc_enum_fmt_vid_out = pxp_enum_fmt_video_output, + .vidioc_try_fmt_vid_out = pxp_try_fmt_video_output, + .vidioc_g_fmt_vid_out = pxp_g_fmt_video_output, + .vidioc_s_fmt_vid_out = pxp_s_fmt_video_output, + + .vidioc_try_fmt_vid_out_overlay = pxp_try_fmt_output_overlay, + .vidioc_g_fmt_vid_out_overlay = pxp_g_fmt_output_overlay, + .vidioc_s_fmt_vid_out_overlay = pxp_s_fmt_output_overlay, + + .vidioc_g_fbuf = pxp_g_fbuf, + .vidioc_s_fbuf = pxp_s_fbuf, + + .vidioc_g_crop = pxp_g_crop, + .vidioc_s_crop = pxp_s_crop, + + .vidioc_queryctrl = pxp_queryctrl, + .vidioc_g_ctrl = pxp_g_ctrl, + .vidioc_s_ctrl = pxp_s_ctrl, +}; + +static const struct video_device pxp_template = { + .name = "PxP", + .vfl_type = V4L2_CAP_VIDEO_OUTPUT | + V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_STREAMING, + .fops = &pxp_fops, + .release = pxp_release, + .minor = -1, + .ioctl_ops = &pxp_ioctl_ops, +}; + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = (struct pxps *)dev_id; + struct videobuf_buffer *vb; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + + __raw_writel(BM_PXP_STAT_IRQ, PXP_BASE_ADDR + HW_PXP_STAT_CLR); + + if (list_empty(&pxp->outq)) { + pr_warning("irq: outq empty!!!\n"); + goto out; + } + + vb = list_entry(pxp->outq.next, struct videobuf_buffer, queue); + list_del_init(&vb->queue); + + vb->state = VIDEOBUF_DONE; + do_gettimeofday(&vb->ts); + vb->field_count++; + + wake_up(&vb->done); + wake_up(&pxp->done); +out: + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + struct resource *res; + int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) { + err = -ENODEV; + goto exit; + } + + pxp = kzalloc(sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + dev_set_drvdata(&pdev->dev, pxp); + pxp->res = res; + pxp->irq = irq; + + pxp->regs_virt = dma_alloc_coherent(NULL, + PAGE_ALIGN(sizeof + (struct pxp_registers)), + &pxp->regs_phys, GFP_KERNEL); + if (pxp->regs_virt == NULL) { + dev_err(&pdev->dev, "failed to allocate pxp_register object\n"); + err = -ENOMEM; + goto exit; + } + + init_waitqueue_head(&pxp->done); + + INIT_WORK(&pxp->work, pxp_next_handle); + INIT_LIST_HEAD(&pxp->outq); + INIT_LIST_HEAD(&pxp->nextq); + spin_lock_init(&pxp->lock); + mutex_init(&pxp->mutex); + + if (!request_mem_region(res->start, res->end - res->start + 1, + PXP_DRIVER_NAME)) { + err = -EBUSY; + goto freepxp; + } + + pxp->regs = (void __iomem *)res->start; /* it is already ioremapped */ + pxp->pdev = pdev; + + err = request_irq(pxp->irq, pxp_irq, 0, PXP_DRIVER_NAME, pxp); + + if (err) { + dev_err(&pdev->dev, "interrupt register failed\n"); + goto release; + } + + pxp->vdev = video_device_alloc(); + if (!pxp->vdev) { + dev_err(&pdev->dev, "video_device_alloc() failed\n"); + err = -ENOMEM; + goto freeirq; + } + + memcpy(pxp->vdev, &pxp_template, sizeof(pxp_template)); + video_set_drvdata(pxp->vdev, pxp); + + err = video_register_device(pxp->vdev, VFL_TYPE_GRABBER, 0); + if (err) { + dev_err(&pdev->dev, "failed to register video device\n"); + goto freevdev; + } + + err = pxp_hw_init(pxp); + if (err) { + dev_err(&pdev->dev, "failed to initialize hardware\n"); + goto freevdev; + } + + dev_info(&pdev->dev, "initialized\n"); + +exit: + return err; + +freevdev: + video_device_release(pxp->vdev); + +freeirq: + free_irq(pxp->irq, pxp); + +release: + release_mem_region(res->start, res->end - res->start + 1); + +freepxp: + kfree(pxp); + + return err; +} + +static int __devexit pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + video_unregister_device(pxp->vdev); + video_device_release(pxp->vdev); + + if (pxp->regs_virt) + dma_free_coherent(0, PAGE_ALIGN(sizeof(struct pxp_registers)), + pxp->regs_virt, pxp->regs_phys); + kfree(pxp->outb); + kfree(pxp); + + return 0; +} + +#ifdef CONFIG_PM +static int pxp_suspend(struct platform_device *pdev, pm_message_t state) +{ + int i; + + while (__raw_readl(PXP_BASE_ADDR + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE) + ; + + for (i = 0; i < REGS1_NUMS; i++) + regs1[i] = + __raw_readl(PXP_BASE_ADDR + HW_PXP_CTRL + REG_OFFSET * i); + + for (i = 0; i < REGS2_NUMS; i++) + regs2[i] = + __raw_readl(PXP_BASE_ADDR + HW_PXP_S0COLORKEYLOW + + REG_OFFSET * i); + + for (i = 0; i < REGS3_NUMS; i++) + regs3[i] = + __raw_readl(PXP_BASE_ADDR + HW_PXP_OLn(0) + REG_OFFSET * i); + + __raw_writel(BM_PXP_CTRL_SFTRST, PXP_BASE_ADDR + HW_PXP_CTRL); + + return 0; +} + +static int pxp_resume(struct platform_device *pdev) +{ + int i; + + /* Pull PxP out of reset */ + __raw_writel(0, PXP_BASE_ADDR + HW_PXP_CTRL); + + for (i = 0; i < REGS1_NUMS; i++) + __raw_writel(regs1[i], + PXP_BASE_ADDR + HW_PXP_CTRL + REG_OFFSET * i); + + for (i = 0; i < REGS2_NUMS; i++) + __raw_writel(regs2[i], + PXP_BASE_ADDR + HW_PXP_S0COLORKEYLOW + + REG_OFFSET * i); + + for (i = 0; i < REGS3_NUMS; i++) + __raw_writel(regs3[i], + PXP_BASE_ADDR + HW_PXP_OLn(0) + REG_OFFSET * i); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +static struct platform_driver pxp_driver = { + .driver = { + .name = PXP_DRIVER_NAME, + }, + .probe = pxp_probe, + .remove = __exit_p(pxp_remove), + .suspend = pxp_suspend, + .resume = pxp_resume, +}; + +static int __devinit pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} + +module_init(pxp_init); +module_exit(pxp_exit); + +MODULE_DESCRIPTION("STMP37xx PxP driver"); +MODULE_AUTHOR("Matt Porter "); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/mxs_pxp.h b/drivers/media/video/mxs_pxp.h new file mode 100644 index 000000000000..6538388fa4cd --- /dev/null +++ b/drivers/media/video/mxs_pxp.h @@ -0,0 +1,158 @@ +/* + * Freescale MXS PxP driver + * + * Author: Matt Porter + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef CONFIG_ARCH_MX23 +#define BF_PXP_CTRL_OUTBUF_FORMAT(v) BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v) + +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB8888 \ + BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888 \ + BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB888P \ + BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P +#define BV_PXP_CTRL_OUTBUF_FORMAT__ARGB1555 \ + BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB565 \ + BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565 +#define BV_PXP_CTRL_OUTBUF_FORMAT__RGB555 \ + BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555 + +#define BF_PXP_OUTSIZE_WIDTH(v) BF_PXP_RGBSIZE_WIDTH(v) +#define BF_PXP_OUTSIZE_HEIGHT(v) BF_PXP_RGBSIZE_HEIGHT(v) + +/* The maximum down scaling factor is 1/2 */ +#define PXP_DOWNSCALE_THRESHOLD 0x2000 +#else +/* The maximum down scaling factor is 1/4 */ +#define PXP_DOWNSCALE_THRESHOLD 0x4000 +#endif + +struct pxp_overlay_registers { + u32 ol; + u32 olsize; + u32 olparam; + u32 olparam2; +}; + +/* Registers feed for PXP_NEXT */ +struct pxp_registers { + u32 ctrl; + u32 outbuf; + u32 outbuf2; + u32 outsize; + u32 s0buf; + u32 s0ubuf; + u32 s0vbuf; + u32 s0param; + u32 s0background; + u32 s0crop; + u32 s0scale; + u32 s0offset; + u32 s0colorkeylow; + u32 s0colorkeyhigh; + u32 olcolorkeylow; + u32 olcolorkeyhigh; + + struct pxp_overlay_registers ol0; + struct pxp_overlay_registers ol1; + struct pxp_overlay_registers ol2; + struct pxp_overlay_registers ol3; + struct pxp_overlay_registers ol4; + struct pxp_overlay_registers ol5; + struct pxp_overlay_registers ol6; + struct pxp_overlay_registers ol7; +}; + +struct pxp_buffer { + /* Must be first! */ + struct videobuf_buffer vb; + struct list_head queue; +}; + +struct pxps { + struct platform_device *pdev; + struct resource *res; + int irq; + void __iomem *regs; + + struct work_struct work; + struct workqueue_struct *workqueue; + spinlock_t lock; + struct mutex mutex; + int users; + + struct video_device *vdev; + + struct videobuf_queue s0_vbq; + struct videobuf_buffer *active; + struct list_head outq; + struct list_head nextq; + + int output; + u32 *outb; + dma_addr_t outb_phys; + + /* Current S0 configuration */ + struct pxp_data_format *s0_fmt; + u32 s0_width; + u32 s0_height; + u32 s0_bgcolor; + u32 s0_chromakey; + + struct v4l2_framebuffer fb; + struct v4l2_rect drect; + struct v4l2_rect srect; + + /* Transformation support */ + int scaling; + int hflip; + int vflip; + int rotate; + int yuv; + + /* Output overlay support */ + int overlay_state; + int global_alpha_state; + u8 global_alpha; + int local_alpha_state; + int s1_chromakey_state; + u32 s1_chromakey; + + /* PXP_NEXT */ + u32 regs_phys; + struct pxp_registers *regs_virt; + wait_queue_head_t done; + int next_queue_ended; +}; + +struct pxp_data_format { + char *name; + unsigned int bpp; + u32 fourcc; + enum v4l2_colorspace colorspace; + u32 ctrl_s0_fmt; +}; + +extern int mxsfb_get_info(struct fb_var_screeninfo *var, + struct fb_fix_screeninfo *fix); +extern void mxsfb_cfg_pxp(int enable, dma_addr_t pxp_phys); diff --git a/drivers/media/video/pxp.c b/drivers/media/video/pxp.c new file mode 100644 index 000000000000..5ef30c4a8f82 --- /dev/null +++ b/drivers/media/video/pxp.c @@ -0,0 +1,1409 @@ +/* + * Freescale STMP378X PxP driver + * + * Author: Matt Porter + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "pxp.h" + +#define PXP_DRIVER_NAME "stmp3xxx-pxp" +#define PXP_DRIVER_MAJOR 1 +#define PXP_DRIVER_MINOR 0 + +#define PXP_DEF_BUFS 2 +#define PXP_MIN_PIX 8 + +#define V4L2_OUTPUT_TYPE_INTERNAL 4 + +#define PXP_WAITCON ((__raw_readl(HW_PXP_NEXT_ADDR) & BM_PXP_NEXT_ENABLED) \ + != BM_PXP_NEXT_ENABLED) + +#define REG_OFFSET 0x10 +#define REGS1_NUMS 16 +#define REGS2_NUMS 5 +#define REGS3_NUMS 32 +static u32 regs1[REGS1_NUMS]; +static u32 regs2[REGS2_NUMS]; +static u32 regs3[REGS3_NUMS]; + +static struct pxp_data_format pxp_s0_formats[] = { + { + .name = "24-bit RGB", + .bpp = 4, + .fourcc = V4L2_PIX_FMT_RGB24, + .colorspace = V4L2_COLORSPACE_SRGB, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB888, + }, { + .name = "16-bit RGB 5:6:5", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_RGB565, + .colorspace = V4L2_COLORSPACE_SRGB, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB565, + }, { + .name = "16-bit RGB 5:5:5", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_RGB555, + .colorspace = V4L2_COLORSPACE_SRGB, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__RGB555, + }, { + .name = "YUV 4:2:0 Planar", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_YUV420, + .colorspace = V4L2_COLORSPACE_JPEG, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__YUV420, + }, { + .name = "YUV 4:2:2 Planar", + .bpp = 2, + .fourcc = V4L2_PIX_FMT_YUV422P, + .colorspace = V4L2_COLORSPACE_JPEG, + .ctrl_s0_fmt = BV_PXP_CTRL_S0_FORMAT__YUV422, + }, +}; + +struct v4l2_queryctrl pxp_controls[] = { + { + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Horizontal Flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Vertical Flip", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_PRIVATE_BASE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Rotation", + .minimum = 0, + .maximum = 270, + .step = 90, + .default_value = 0, + .flags = 0, + }, { + .id = V4L2_CID_PRIVATE_BASE + 1, + .name = "Background Color", + .minimum = 0, + .maximum = 0xFFFFFF, + .step = 1, + .default_value = 0, + .flags = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_PRIVATE_BASE + 2, + .name = "Set S0 Chromakey", + .minimum = -1, + .maximum = 0xFFFFFF, + .step = 1, + .default_value = -1, + .flags = 0, + .type = V4L2_CTRL_TYPE_INTEGER, + }, { + .id = V4L2_CID_PRIVATE_BASE + 3, + .name = "YUV Colorspace", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + .flags = 0, + .type = V4L2_CTRL_TYPE_BOOLEAN, + }, +}; + +static void pxp_set_ctrl(struct pxps *pxp) +{ + u32 ctrl; + + ctrl = BF(pxp->s0_fmt->ctrl_s0_fmt, PXP_CTRL_S0_FORMAT); + ctrl |= + BF(BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888, PXP_CTRL_OUTPUT_RGB_FORMAT); + ctrl |= BM_PXP_CTRL_CROP; + + if (pxp->scaling) + ctrl |= BM_PXP_CTRL_SCALE; + if (pxp->vflip) + ctrl |= BM_PXP_CTRL_VFLIP; + if (pxp->hflip) + ctrl |= BM_PXP_CTRL_HFLIP; + if (pxp->rotate) + ctrl |= BF(pxp->rotate/90, PXP_CTRL_ROTATE); + + ctrl |= BM_PXP_CTRL_IRQ_ENABLE; + if (pxp->active) + ctrl |= BM_PXP_CTRL_ENABLE; + + __raw_writel(ctrl, HW_PXP_CTRL_ADDR); + pxp->regs_virt->ctrl = ctrl; +} + +static void pxp_set_rgbbuf(struct pxps *pxp) +{ + pxp->regs_virt->rgbbuf = pxp->outb_phys; + /* Always equal to the FB size */ + pxp->regs_virt->rgbsize = BF(pxp->fb.fmt.width, PXP_RGBSIZE_WIDTH) | + BF(pxp->fb.fmt.height, PXP_RGBSIZE_HEIGHT); +} + +static void pxp_set_s0colorkey(struct pxps *pxp) +{ + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (pxp->s0_chromakey == -1) { + /* disable color key */ + pxp->regs_virt->s0colorkeylow = 0xFFFFFF; + pxp->regs_virt->s0colorkeyhigh = 0; + } else { + pxp->regs_virt->s0colorkeylow = pxp->s0_chromakey; + pxp->regs_virt->s0colorkeyhigh = pxp->s0_chromakey; + } +} + +static void pxp_set_s1colorkey(struct pxps *pxp) +{ + /* Low and high are set equal. V4L does not allow a chromakey range */ + if (pxp->s1_chromakey_state != 0 && pxp->s1_chromakey != -1) { + pxp->regs_virt->olcolorkeylow = pxp->s1_chromakey; + pxp->regs_virt->olcolorkeyhigh = pxp->s1_chromakey; + } else { + /* disable color key */ + pxp->regs_virt->olcolorkeylow = 0xFFFFFF; + pxp->regs_virt->olcolorkeyhigh = 0; + } +} + +static void pxp_set_oln(struct pxps *pxp) +{ + pxp->regs_virt->ol0.ol = (u32)pxp->fb.base; + pxp->regs_virt->ol0.olsize = + BF(pxp->fb.fmt.width >> 3, PXP_OLnSIZE_WIDTH) | + BF(pxp->fb.fmt.height >> 3, PXP_OLnSIZE_HEIGHT); +} + +static void pxp_set_olparam(struct pxps *pxp) +{ + u32 olparam; + struct v4l2_pix_format *fmt = &pxp->fb.fmt; + + olparam = BF(pxp->global_alpha, PXP_OLnPARAM_ALPHA); + if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) + olparam |= + BF(BV_PXP_OLnPARAM_FORMAT__RGB888, PXP_OLnPARAM_FORMAT); + else + olparam |= + BF(BV_PXP_OLnPARAM_FORMAT__RGB565, PXP_OLnPARAM_FORMAT); + if (pxp->global_alpha_state) + olparam |= BF(BV_PXP_OLnPARAM_ALPHA_CNTL__Override, + PXP_OLnPARAM_ALPHA_CNTL); + if (pxp->s1_chromakey_state) + olparam |= BM_PXP_OLnPARAM_ENABLE_COLORKEY; + if (pxp->overlay_state) + olparam |= BM_PXP_OLnPARAM_ENABLE; + + pxp->regs_virt->ol0.olparam = olparam; +} + +static void pxp_set_s0param(struct pxps *pxp) +{ + u32 s0param; + + s0param = BF(pxp->drect.left >> 3, PXP_S0PARAM_XBASE); + s0param |= BF(pxp->drect.top >> 3, PXP_S0PARAM_YBASE); + s0param |= BF(pxp->s0_width >> 3, PXP_S0PARAM_WIDTH); + s0param |= BF(pxp->s0_height >> 3, PXP_S0PARAM_HEIGHT); + pxp->regs_virt->s0param = s0param; +} + +static void pxp_set_s0crop(struct pxps *pxp) +{ + u32 s0crop; + + s0crop = BF(pxp->srect.left >> 3, PXP_S0CROP_XBASE); + s0crop |= BF(pxp->srect.top >> 3, PXP_S0CROP_YBASE); + s0crop |= BF(pxp->drect.width >> 3, PXP_S0CROP_WIDTH); + s0crop |= BF(pxp->drect.height >> 3, PXP_S0CROP_HEIGHT); + pxp->regs_virt->s0crop = s0crop; +} + +static int pxp_set_scaling(struct pxps *pxp) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + + if ((pxp->s0_fmt->fourcc != V4L2_PIX_FMT_YUV420) && + (pxp->s0_fmt->fourcc != V4L2_PIX_FMT_YUV422P)) { + pxp->scaling = 0; + ret = -EINVAL; + goto out; + } + + if ((pxp->srect.width == pxp->drect.width) && + (pxp->srect.height == pxp->drect.height)) { + pxp->scaling = 0; + goto out; + } + + pxp->scaling = 1; + xscale = pxp->srect.width * 0x1000 / pxp->drect.width; + yscale = pxp->srect.height * 0x1000 / pxp->drect.height; + s0scale = BF(yscale, PXP_S0SCALE_YSCALE) | + BF(xscale, PXP_S0SCALE_XSCALE); + pxp->regs_virt->s0scale = s0scale; + +out: + pxp_set_ctrl(pxp); + + return ret; +} + +static int pxp_set_fbinfo(struct pxps *pxp) +{ + struct fb_var_screeninfo var; + struct fb_fix_screeninfo fix; + struct v4l2_framebuffer *fb = &pxp->fb; + int err; + + err = stmp3xxxfb_get_info(&var, &fix); + + fb->fmt.width = var.xres; + fb->fmt.height = var.yres; + if (var.bits_per_pixel == 16) + fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565; + else + fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24; + fb->base = (void *)fix.smem_start; + return err; +} + +static void pxp_set_s0bg(struct pxps *pxp) +{ + pxp->regs_virt->s0background = pxp->s0_bgcolor; +} + +static void pxp_set_csc(struct pxps *pxp) +{ + if (pxp->yuv) { + /* YUV colorspace */ + __raw_writel(0x04030000, HW_PXP_CSCCOEFF0_ADDR); + __raw_writel(0x01230208, HW_PXP_CSCCOEFF1_ADDR); + __raw_writel(0x076b079c, HW_PXP_CSCCOEFF2_ADDR); + } else { + /* YCrCb colorspace */ + __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR); + __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR); + __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR); + } +} + +static int pxp_set_cstate(struct pxps *pxp, struct v4l2_control *vc) +{ + + if (vc->id == V4L2_CID_HFLIP) + pxp->hflip = vc->value; + else if (vc->id == V4L2_CID_VFLIP) + pxp->vflip = vc->value; + else if (vc->id == V4L2_CID_PRIVATE_BASE) { + if (vc->value % 90) + return -ERANGE; + pxp->rotate = vc->value; + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) { + pxp->s0_bgcolor = vc->value; + pxp_set_s0bg(pxp); + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) { + pxp->s0_chromakey = vc->value; + pxp_set_s0colorkey(pxp); + } else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) { + pxp->yuv = vc->value; + pxp_set_csc(pxp); + } + + pxp_set_ctrl(pxp); + + return 0; +} + +static int pxp_get_cstate(struct pxps *pxp, struct v4l2_control *vc) +{ + if (vc->id == V4L2_CID_HFLIP) + vc->value = pxp->hflip; + else if (vc->id == V4L2_CID_VFLIP) + vc->value = pxp->vflip; + else if (vc->id == V4L2_CID_PRIVATE_BASE) + vc->value = pxp->rotate; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) + vc->value = pxp->s0_bgcolor; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) + vc->value = pxp->s0_chromakey; + else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) + vc->value = pxp->yuv; + + return 0; +} + +static int pxp_enumoutput(struct file *file, void *fh, + struct v4l2_output *o) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if ((o->index < 0) || (o->index > 1)) + return -EINVAL; + + memset(o, 0, sizeof(struct v4l2_output)); + if (o->index == 0) { + strcpy(o->name, "PxP Display Output"); + pxp->output = 0; + } else { + strcpy(o->name, "PxP Virtual Output"); + pxp->output = 1; + } + o->type = V4L2_OUTPUT_TYPE_INTERNAL; + o->std = 0; + o->reserved[0] = pxp->outb_phys; + + return 0; +} + +static int pxp_g_output(struct file *file, void *fh, + unsigned int *i) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + *i = pxp->output; + + return 0; +} + +static int pxp_s_output(struct file *file, void *fh, + unsigned int i) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_pix_format *fmt = &pxp->fb.fmt; + int bpp; + + if ((i < 0) || (i > 1)) + return -EINVAL; + + if (pxp->outb) + goto out; + + /* Output buffer is same format as fbdev */ + if (fmt->pixelformat == V4L2_PIX_FMT_RGB24) + bpp = 4; + else + bpp = 2; + + pxp->outb = kmalloc(fmt->width * fmt->height * bpp, GFP_KERNEL); + pxp->outb_phys = virt_to_phys(pxp->outb); + dma_map_single(NULL, pxp->outb, + fmt->width * fmt->height * bpp, DMA_TO_DEVICE); + +out: + pxp_set_rgbbuf(pxp); + + return 0; +} + +static int pxp_enum_fmt_video_output(struct file *file, void *fh, + struct v4l2_fmtdesc *fmt) +{ + enum v4l2_buf_type type = fmt->type; + int index = fmt->index; + + if ((fmt->index < 0) || (fmt->index >= ARRAY_SIZE(pxp_s0_formats))) + return -EINVAL; + + memset(fmt, 0, sizeof(struct v4l2_fmtdesc)); + fmt->index = index; + fmt->type = type; + fmt->pixelformat = pxp_s0_formats[index].fourcc; + strcpy(fmt->description, pxp_s0_formats[index].name); + + return 0; +} + +static int pxp_g_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct v4l2_pix_format *pf = &f->fmt.pix; + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct pxp_data_format *fmt = pxp->s0_fmt; + + pf->width = pxp->s0_width; + pf->height = pxp->s0_height; + pf->pixelformat = fmt->fourcc; + pf->field = V4L2_FIELD_NONE; + pf->bytesperline = fmt->bpp * pf->width; + pf->sizeimage = pf->bytesperline * pf->height; + pf->colorspace = fmt->colorspace; + pf->priv = 0; + + return 0; +} + +static struct pxp_data_format *pxp_get_format(struct v4l2_format *f) +{ + struct pxp_data_format *fmt; + int i; + + for (i = 0; i < ARRAY_SIZE(pxp_s0_formats); i++) { + fmt = &pxp_s0_formats[i]; + if (fmt->fourcc == f->fmt.pix.pixelformat) + break; + } + + if (i == ARRAY_SIZE(pxp_s0_formats)) + return NULL; + + return &pxp_s0_formats[i]; +} + +static int pxp_try_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + int w = f->fmt.pix.width; + int h = f->fmt.pix.height; + struct pxp_data_format *fmt = pxp_get_format(f); + + if (!fmt) + return -EINVAL; + + w = min(w, 2040); + w = max(w, 8); + h = min(h, 2040); + h = max(h, 8); + f->fmt.pix.field = V4L2_FIELD_NONE; + f->fmt.pix.width = w; + f->fmt.pix.height = h; + f->fmt.pix.pixelformat = fmt->fourcc; + + return 0; +} + +static int pxp_s_fmt_video_output(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_pix_format *pf = &f->fmt.pix; + int ret = pxp_try_fmt_video_output(file, fh, f); + + if (ret == 0) { + pxp->s0_fmt = pxp_get_format(f); + pxp->s0_width = pf->width; + pxp->s0_height = pf->height; + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + } + + return ret; +} + +static int pxp_g_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + + memset(wf, 0, sizeof(struct v4l2_window)); + wf->chromakey = pxp->s1_chromakey; + wf->global_alpha = pxp->global_alpha; + wf->field = V4L2_FIELD_NONE; + wf->clips = NULL; + wf->clipcount = 0; + wf->bitmap = NULL; + wf->w.left = pxp->srect.left; + wf->w.top = pxp->srect.top; + wf->w.width = pxp->srect.width; + wf->w.height = pxp->srect.height; + + return 0; +} + +static int pxp_try_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + struct v4l2_rect srect; + u32 s1_chromakey = wf->chromakey; + u8 global_alpha = wf->global_alpha; + + memcpy(&srect, &(wf->w), sizeof(struct v4l2_rect)); + + pxp_g_fmt_output_overlay(file, fh, f); + + wf->chromakey = s1_chromakey; + wf->global_alpha = global_alpha; + + /* Constrain parameters to the input buffer */ + wf->w.left = srect.left; + wf->w.top = srect.top; + wf->w.width = min(srect.width, ((__s32)pxp->s0_width - wf->w.left)); + wf->w.height = min(srect.height, ((__s32)pxp->s0_height - wf->w.top)); + + return 0; +} + +static int pxp_s_fmt_output_overlay(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + struct v4l2_window *wf = &f->fmt.win; + int ret = pxp_try_fmt_output_overlay(file, fh, f); + + if (ret == 0) { + pxp->srect.left = wf->w.left; + pxp->srect.top = wf->w.top; + pxp->srect.width = wf->w.width; + pxp->srect.height = wf->w.height; + pxp->global_alpha = wf->global_alpha; + pxp->s1_chromakey = wf->chromakey; + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + pxp_set_olparam(pxp); + pxp_set_s1colorkey(pxp); + } + + return ret; +} + +static int pxp_reqbufs(struct file *file, void *priv, + struct v4l2_requestbuffers *r) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_reqbufs(&pxp->s0_vbq, r); +} + +static int pxp_querybuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_querybuf(&pxp->s0_vbq, b); +} + +static int pxp_qbuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_qbuf(&pxp->s0_vbq, b); +} + +static int pxp_dqbuf(struct file *file, void *priv, + struct v4l2_buffer *b) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + return videobuf_dqbuf(&pxp->s0_vbq, b, file->f_flags & O_NONBLOCK); +} + +static int pxp_streamon(struct file *file, void *priv, + enum v4l2_buf_type t) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT)) + return -EINVAL; + + ret = videobuf_streamon(&pxp->s0_vbq); + + if (!ret && (pxp->output == 0)) + stmp3xxxfb_cfg_pxp(1, pxp->outb_phys); + + return ret; +} + +static int pxp_streamoff(struct file *file, void *priv, + enum v4l2_buf_type t) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT)) + return -EINVAL; + + ret = videobuf_streamoff(&pxp->s0_vbq); + + if (!ret) + stmp3xxxfb_cfg_pxp(0, 0); + + return ret; +} + +static int pxp_buf_setup(struct videobuf_queue *q, + unsigned int *count, unsigned *size) +{ + struct pxps *pxp = q->priv_data; + + *size = pxp->s0_width * pxp->s0_height * pxp->s0_fmt->bpp; + + if (0 == *count) + *count = PXP_DEF_BUFS; + + return 0; +} + +static void pxp_buf_free(struct videobuf_queue *q, struct videobuf_buffer *vb) +{ + if (in_interrupt()) + BUG(); + + videobuf_dma_contig_free(q, vb); + + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static int pxp_buf_prepare(struct videobuf_queue *q, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct pxps *pxp = q->priv_data; + int ret = 0; + + vb->width = pxp->s0_width; + vb->height = pxp->s0_height; + vb->size = vb->width * vb->height * pxp->s0_fmt->bpp; + vb->field = V4L2_FIELD_NONE; + vb->state = VIDEOBUF_NEEDS_INIT; + + ret = videobuf_iolock(q, vb, NULL); + if (ret) + goto fail; + vb->state = VIDEOBUF_PREPARED; + + return 0; + +fail: + pxp_buf_free(q, vb); + return ret; +} + +static void pxp_buf_next(struct pxps *pxp) +{ + dma_addr_t Y, U, V; + + if (pxp->active) { + pxp->active->state = VIDEOBUF_ACTIVE; + Y = videobuf_to_dma_contig(pxp->active); + pxp->regs_virt->s0buf = Y; + if ((pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV420) || + (pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV422P)) { + int s = 1; /* default to YUV 4:2:2 */ + if (pxp->s0_fmt->fourcc == V4L2_PIX_FMT_YUV420) + s = 2; + U = Y + (pxp->s0_width * pxp->s0_height); + V = U + ((pxp->s0_width * pxp->s0_height) >> s); + pxp->regs_virt->s0ubuf = U; + pxp->regs_virt->s0vbuf = V; + } + pxp->regs_virt->ctrl = + __raw_readl(HW_PXP_CTRL_ADDR) | BM_PXP_CTRL_ENABLE; + } + + __raw_writel(pxp->regs_phys, HW_PXP_NEXT_ADDR); +} + +static void pxp_next_handle(struct work_struct *w) +{ + struct pxps *pxp = container_of(w, struct pxps, work); + struct pxp_buffer *buf, *next; + unsigned long flags; + + if (pxp->next_queue_ended == 1) + return; + + spin_lock_irqsave(&pxp->lock, flags); + + while (!list_empty(&pxp->nextq)) { + spin_unlock_irqrestore(&pxp->lock, flags); + + if (!wait_event_interruptible_timeout(pxp->done, PXP_WAITCON, + 5 * HZ) || signal_pending(current)) { + spin_lock_irqsave(&pxp->lock, flags); + list_for_each_entry_safe(buf, next, &pxp->nextq, queue) + list_del(&buf->queue); + spin_unlock_irqrestore(&pxp->lock, flags); + pxp->next_queue_ended = 1; + return; + } + + spin_lock_irqsave(&pxp->lock, flags); + buf = list_entry(pxp->nextq.next, + struct pxp_buffer, + queue); + list_del_init(&buf->queue); + pxp->active = &buf->vb; + pxp->active->state = VIDEOBUF_QUEUED; + pxp_buf_next(pxp); + } + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxp_buf_queue(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + struct pxps *pxp = q->priv_data; + struct pxp_buffer *buf; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + + if (list_empty(&pxp->outq)) { + list_add_tail(&vb->queue, &pxp->outq); + vb->state = VIDEOBUF_QUEUED; + + pxp->active = vb; + pxp_buf_next(pxp); + } else { + list_add_tail(&vb->queue, &pxp->outq); + + buf = container_of(vb, struct pxp_buffer, vb); + list_add_tail(&buf->queue, &pxp->nextq); + queue_work(pxp->workqueue, &pxp->work); + } + + spin_unlock_irqrestore(&pxp->lock, flags); +} + +static void pxp_buf_release(struct videobuf_queue *q, + struct videobuf_buffer *vb) +{ + pxp_buf_free(q, vb); +} + +static struct videobuf_queue_ops pxp_vbq_ops = { + .buf_setup = pxp_buf_setup, + .buf_prepare = pxp_buf_prepare, + .buf_queue = pxp_buf_queue, + .buf_release = pxp_buf_release, +}; + +static int pxp_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + memset(cap, 0, sizeof(*cap)); + strcpy(cap->driver, "pxp"); + strcpy(cap->card, "pxp"); + strlcpy(cap->bus_info, dev_name(&pxp->pdev->dev), sizeof(cap->bus_info)); + + cap->version = (PXP_DRIVER_MAJOR << 8) + PXP_DRIVER_MINOR; + + cap->capabilities = V4L2_CAP_VIDEO_OUTPUT | + V4L2_CAP_VIDEO_OUTPUT_OVERLAY | + V4L2_CAP_STREAMING; + + return 0; +} + +static int pxp_g_fbuf(struct file *file, void *priv, + struct v4l2_framebuffer *fb) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + memset(fb, 0, sizeof(*fb)); + + fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY | + V4L2_FBUF_CAP_CHROMAKEY | + V4L2_FBUF_CAP_LOCAL_ALPHA | + V4L2_FBUF_CAP_GLOBAL_ALPHA; + + if (pxp->global_alpha_state) + fb->flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA; + if (pxp->local_alpha_state) + fb->flags |= V4L2_FBUF_FLAG_LOCAL_ALPHA; + if (pxp->s1_chromakey_state) + fb->flags |= V4L2_FBUF_FLAG_CHROMAKEY; + + return 0; +} + +static int pxp_s_fbuf(struct file *file, void *priv, + struct v4l2_framebuffer *fb) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + pxp->overlay_state = + (fb->flags & V4L2_FBUF_FLAG_OVERLAY) != 0; + pxp->global_alpha_state = + (fb->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) != 0; + pxp->local_alpha_state = + (fb->flags & V4L2_FBUF_FLAG_LOCAL_ALPHA) != 0; + /* Global alpha overrides local alpha if both are requested */ + if (pxp->global_alpha_state && pxp->local_alpha_state) + pxp->local_alpha_state = 0; + pxp->s1_chromakey_state = + (fb->flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0; + + pxp_set_olparam(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + + return 0; +} + +static int pxp_g_crop(struct file *file, void *fh, + struct v4l2_crop *c) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) + return -EINVAL; + + c->c.left = pxp->drect.left; + c->c.top = pxp->drect.top; + c->c.width = pxp->drect.width; + c->c.height = pxp->drect.height; + + return 0; +} + +static int pxp_s_crop(struct file *file, void *fh, + struct v4l2_crop *c) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int l = c->c.left; + int t = c->c.top; + int w = c->c.width; + int h = c->c.height; + int fbw = pxp->fb.fmt.width; + int fbh = pxp->fb.fmt.height; + + if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) + return -EINVAL; + + /* Constrain parameters to FB limits */ + w = min(w, fbw); + w = max(w, PXP_MIN_PIX); + h = min(h, fbh); + h = max(h, PXP_MIN_PIX); + if ((l + w) > fbw) + l = 0; + if ((t + h) > fbh) + t = 0; + + /* Round up values to PxP pixel block */ + l = roundup(l, PXP_MIN_PIX); + t = roundup(t, PXP_MIN_PIX); + w = roundup(w, PXP_MIN_PIX); + h = roundup(h, PXP_MIN_PIX); + + pxp->drect.left = l; + pxp->drect.top = t; + pxp->drect.width = w; + pxp->drect.height = h; + + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_scaling(pxp); + + return 0; +} + +static int pxp_queryctrl(struct file *file, void *priv, + struct v4l2_queryctrl *qc) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (qc->id && qc->id == pxp_controls[i].id) { + memcpy(qc, &(pxp_controls[i]), sizeof(*qc)); + return 0; + } + + return -EINVAL; +} + +static int pxp_g_ctrl(struct file *file, void *priv, + struct v4l2_control *vc) +{ + int i; + + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (vc->id == pxp_controls[i].id) + return pxp_get_cstate(pxp, vc); + + return -EINVAL; +} + +static int pxp_s_ctrl(struct file *file, void *priv, + struct v4l2_control *vc) +{ + int i; + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) + if (vc->id == pxp_controls[i].id) { + if (vc->value < pxp_controls[i].minimum || + vc->value > pxp_controls[i].maximum) + return -ERANGE; + return pxp_set_cstate(pxp, vc); + } + + return -EINVAL; +} + +void pxp_release(struct video_device *vfd) +{ + struct pxps *pxp = video_get_drvdata(vfd); + + spin_lock(&pxp->lock); + video_device_release(vfd); + spin_unlock(&pxp->lock); +} + +static int pxp_hw_init(struct pxps *pxp) +{ + struct fb_var_screeninfo var; + struct fb_fix_screeninfo fix; + int err; + + err = stmp3xxxfb_get_info(&var, &fix); + if (err) + return err; + + /* Pull PxP out of reset */ + __raw_writel(0, HW_PXP_CTRL_ADDR); + + /* Config defaults */ + pxp->active = NULL; + + pxp->s0_fmt = &pxp_s0_formats[0]; + pxp->drect.left = pxp->srect.left = 0; + pxp->drect.top = pxp->srect.top = 0; + pxp->drect.width = pxp->srect.width = pxp->s0_width = var.xres; + pxp->drect.height = pxp->srect.height = pxp->s0_height = var.yres; + pxp->s0_bgcolor = 0; + + pxp->output = 0; + err = pxp_set_fbinfo(pxp); + if (err) + return err; + + pxp->scaling = 0; + pxp->hflip = 0; + pxp->vflip = 0; + pxp->rotate = 0; + pxp->yuv = 0; + + pxp->overlay_state = 0; + pxp->global_alpha_state = 0; + pxp->global_alpha = 0; + pxp->local_alpha_state = 0; + pxp->s1_chromakey_state = 0; + pxp->s1_chromakey = -1; + pxp->s0_chromakey = -1; + + /* Write default h/w config */ + pxp_set_ctrl(pxp); + pxp_set_s0param(pxp); + pxp_set_s0crop(pxp); + pxp_set_oln(pxp); + pxp_set_olparam(pxp); + pxp_set_s0colorkey(pxp); + pxp_set_s1colorkey(pxp); + pxp_set_csc(pxp); + + return 0; +} + +static int pxp_open(struct file *file) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret = 0; + + mutex_lock(&pxp->mutex); + pxp->users++; + + if (pxp->users > 1) { + pxp->users--; + ret = -EBUSY; + goto out; + } +out: + mutex_unlock(&pxp->mutex); + if (ret) + return ret; + + pxp->next_queue_ended = 0; + pxp->workqueue = create_singlethread_workqueue("pxp"); + + videobuf_queue_dma_contig_init(&pxp->s0_vbq, + &pxp_vbq_ops, + &pxp->pdev->dev, + &pxp->lock, + V4L2_BUF_TYPE_VIDEO_OUTPUT, + V4L2_FIELD_NONE, + sizeof(struct pxp_buffer), + pxp); + + return 0; +} + +static int pxp_close(struct file *file) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + + if (pxp->workqueue) + destroy_workqueue(pxp->workqueue); + + videobuf_stop(&pxp->s0_vbq); + videobuf_mmap_free(&pxp->s0_vbq); + pxp->active = NULL; + + mutex_lock(&pxp->mutex); + pxp->users--; + mutex_unlock(&pxp->mutex); + + return 0; +} + +static int pxp_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct pxps *pxp = video_get_drvdata(video_devdata(file)); + int ret; + + ret = videobuf_mmap_mapper(&pxp->s0_vbq, vma); + + return ret; +} + +static const struct v4l2_file_operations pxp_fops = { + .owner = THIS_MODULE, + .open = pxp_open, + .release = pxp_close, + .ioctl = video_ioctl2, + .mmap = pxp_mmap, +}; + +static const struct v4l2_ioctl_ops pxp_ioctl_ops = { + .vidioc_querycap = pxp_querycap, + + .vidioc_reqbufs = pxp_reqbufs, + .vidioc_querybuf = pxp_querybuf, + .vidioc_qbuf = pxp_qbuf, + .vidioc_dqbuf = pxp_dqbuf, + + .vidioc_streamon = pxp_streamon, + .vidioc_streamoff = pxp_streamoff, + + .vidioc_enum_output = pxp_enumoutput, + .vidioc_g_output = pxp_g_output, + .vidioc_s_output = pxp_s_output, + + .vidioc_enum_fmt_vid_out = pxp_enum_fmt_video_output, + .vidioc_try_fmt_vid_out = pxp_try_fmt_video_output, + .vidioc_g_fmt_vid_out = pxp_g_fmt_video_output, + .vidioc_s_fmt_vid_out = pxp_s_fmt_video_output, + + .vidioc_try_fmt_vid_out_overlay = pxp_try_fmt_output_overlay, + .vidioc_g_fmt_vid_out_overlay = pxp_g_fmt_output_overlay, + .vidioc_s_fmt_vid_out_overlay = pxp_s_fmt_output_overlay, + + .vidioc_g_fbuf = pxp_g_fbuf, + .vidioc_s_fbuf = pxp_s_fbuf, + + .vidioc_g_crop = pxp_g_crop, + .vidioc_s_crop = pxp_s_crop, + + .vidioc_queryctrl = pxp_queryctrl, + .vidioc_g_ctrl = pxp_g_ctrl, + .vidioc_s_ctrl = pxp_s_ctrl, +}; + +static const struct video_device pxp_template = { + .name = "PxP", + .vfl_type = V4L2_CAP_VIDEO_OUTPUT | + V4L2_CAP_VIDEO_OVERLAY | + V4L2_CAP_STREAMING, + .fops = &pxp_fops, + .release = pxp_release, + .minor = -1, + .ioctl_ops = &pxp_ioctl_ops, +}; + +static irqreturn_t pxp_irq(int irq, void *dev_id) +{ + struct pxps *pxp = (struct pxps *)dev_id; + struct videobuf_buffer *vb; + unsigned long flags; + + spin_lock_irqsave(&pxp->lock, flags); + + __raw_writel(BM_PXP_STAT_IRQ, HW_PXP_STAT_CLR_ADDR); + + if (list_empty(&pxp->outq)) { + pr_warning("irq: outq empty!!!\n"); + goto out; + } + + vb = list_entry(pxp->outq.next, + struct videobuf_buffer, + queue); + list_del_init(&vb->queue); + + vb->state = VIDEOBUF_DONE; + do_gettimeofday(&vb->ts); + vb->field_count++; + + wake_up(&vb->done); + wake_up(&pxp->done); +out: + spin_unlock_irqrestore(&pxp->lock, flags); + + return IRQ_HANDLED; +} + +static int pxp_notifier_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct pxps *pxp = container_of(self, struct pxps, nb); + + switch (event) { + case STMP3XXX_LCDIF_PANEL_INIT: + pxp_set_fbinfo(pxp); + break; + default: + break; + } + return 0; +} + +static int pxp_probe(struct platform_device *pdev) +{ + struct pxps *pxp; + struct resource *res; + int irq; + int err = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res || irq < 0) { + err = -ENODEV; + goto exit; + } + + pxp = kzalloc(sizeof(*pxp), GFP_KERNEL); + if (!pxp) { + dev_err(&pdev->dev, "failed to allocate control object\n"); + err = -ENOMEM; + goto exit; + } + + dev_set_drvdata(&pdev->dev, pxp); + pxp->res = res; + pxp->irq = irq; + + pxp->regs_virt = dma_alloc_coherent(NULL, + PAGE_ALIGN(sizeof(struct pxp_registers)), + &pxp->regs_phys, GFP_KERNEL); + if (pxp->regs_virt == NULL) { + dev_err(&pdev->dev, "failed to allocate pxp_register object\n"); + err = -ENOMEM; + goto exit; + } + + init_waitqueue_head(&pxp->done); + + INIT_WORK(&pxp->work, pxp_next_handle); + INIT_LIST_HEAD(&pxp->outq); + INIT_LIST_HEAD(&pxp->nextq); + spin_lock_init(&pxp->lock); + mutex_init(&pxp->mutex); + + if (!request_mem_region(res->start, res->end - res->start + 1, + PXP_DRIVER_NAME)) { + err = -EBUSY; + goto freepxp; + } + + pxp->regs = (void __iomem *)res->start; /* it is already ioremapped */ + pxp->pdev = pdev; + + err = request_irq(pxp->irq, pxp_irq, 0, PXP_DRIVER_NAME, pxp); + + if (err) { + dev_err(&pdev->dev, "interrupt register failed\n"); + goto release; + } + + pxp->vdev = video_device_alloc(); + if (!pxp->vdev) { + dev_err(&pdev->dev, "video_device_alloc() failed\n"); + err = -ENOMEM; + goto freeirq; + } + + memcpy(pxp->vdev, &pxp_template, sizeof(pxp_template)); + video_set_drvdata(pxp->vdev, pxp); + + err = video_register_device(pxp->vdev, VFL_TYPE_GRABBER, 0); + if (err) { + dev_err(&pdev->dev, "failed to register video device\n"); + goto freevdev; + } + + err = pxp_hw_init(pxp); + if (err) { + dev_err(&pdev->dev, "failed to initialize hardware\n"); + goto freevdev; + } + + pxp->nb.notifier_call = pxp_notifier_callback, + stmp3xxx_lcdif_register_client(&pxp->nb); + dev_info(&pdev->dev, "initialized\n"); + +exit: + return err; + +freevdev: + video_device_release(pxp->vdev); + +freeirq: + free_irq(pxp->irq, pxp); + +release: + release_mem_region(res->start, res->end - res->start + 1); + +freepxp: + kfree(pxp); + + return err; +} + +static int __devexit pxp_remove(struct platform_device *pdev) +{ + struct pxps *pxp = platform_get_drvdata(pdev); + + stmp3xxx_lcdif_unregister_client(&pxp->nb); + video_unregister_device(pxp->vdev); + video_device_release(pxp->vdev); + + if (pxp->regs_virt) + dma_free_coherent(0, PAGE_ALIGN(sizeof(struct pxp_registers)), + pxp->regs_virt, pxp->regs_phys); + kfree(pxp->outb); + kfree(pxp); + + return 0; +} + +#ifdef CONFIG_PM +static int pxp_suspend(struct platform_device *pdev, pm_message_t state) +{ + int i; + + while (__raw_readl(HW_PXP_CTRL_ADDR) & BM_PXP_CTRL_ENABLE) + ; + + for (i = 0; i < REGS1_NUMS; i++) + regs1[i] = __raw_readl(HW_PXP_CTRL_ADDR + REG_OFFSET * i); + + for (i = 0; i < REGS2_NUMS; i++) + regs2[i] = __raw_readl(HW_PXP_PAGETABLE_ADDR + REG_OFFSET * i); + + for (i = 0; i < REGS3_NUMS; i++) + regs3[i] = __raw_readl(HW_PXP_OLn_ADDR(0) + REG_OFFSET * i); + + __raw_writel(BM_PXP_CTRL_SFTRST, HW_PXP_CTRL_ADDR); + + return 0; +} + +static int pxp_resume(struct platform_device *pdev) +{ + int i; + + /* Pull PxP out of reset */ + __raw_writel(0, HW_PXP_CTRL_ADDR); + + for (i = 0; i < REGS1_NUMS; i++) + __raw_writel(regs1[i], HW_PXP_CTRL_ADDR + REG_OFFSET * i); + + for (i = 0; i < REGS2_NUMS; i++) + __raw_writel(regs2[i], HW_PXP_PAGETABLE_ADDR + REG_OFFSET * i); + + for (i = 0; i < REGS3_NUMS; i++) + __raw_writel(regs3[i], HW_PXP_OLn_ADDR(0) + REG_OFFSET * i); + + return 0; +} +#else +#define pxp_suspend NULL +#define pxp_resume NULL +#endif + +static struct platform_driver pxp_driver = { + .driver = { + .name = PXP_DRIVER_NAME, + }, + .probe = pxp_probe, + .remove = __exit_p(pxp_remove), + .suspend = pxp_suspend, + .resume = pxp_resume, +}; + + +static int __devinit pxp_init(void) +{ + return platform_driver_register(&pxp_driver); +} + +static void __exit pxp_exit(void) +{ + platform_driver_unregister(&pxp_driver); +} + +module_init(pxp_init); +module_exit(pxp_exit); + +MODULE_DESCRIPTION("STMP37xx PxP driver"); +MODULE_AUTHOR("Matt Porter "); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/video/pxp.h b/drivers/media/video/pxp.h new file mode 100644 index 000000000000..11b41dcc6ade --- /dev/null +++ b/drivers/media/video/pxp.h @@ -0,0 +1,130 @@ +/* + * Freescale STMP378X PxP driver + * + * Author: Matt Porter + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +struct pxp_overlay_registers { + u32 ol; + u32 olsize; + u32 olparam; + u32 olparam2; +}; + +/* Registers feed for PXP_NEXT */ +struct pxp_registers { + u32 ctrl; + u32 rgbbuf; + u32 rgbbuf2; + u32 rgbsize; + u32 s0buf; + u32 s0ubuf; + u32 s0vbuf; + u32 s0param; + u32 s0background; + u32 s0crop; + u32 s0scale; + u32 s0offset; + u32 s0colorkeylow; + u32 s0colorkeyhigh; + u32 olcolorkeylow; + u32 olcolorkeyhigh; + + struct pxp_overlay_registers ol0; + struct pxp_overlay_registers ol1; + struct pxp_overlay_registers ol2; + struct pxp_overlay_registers ol3; + struct pxp_overlay_registers ol4; + struct pxp_overlay_registers ol5; + struct pxp_overlay_registers ol6; + struct pxp_overlay_registers ol7; +}; + +struct pxp_buffer { + /* Must be first! */ + struct videobuf_buffer vb; + struct list_head queue; +}; + +struct pxps { + struct platform_device *pdev; + struct resource *res; + int irq; + void __iomem *regs; + + struct work_struct work; + struct workqueue_struct *workqueue; + spinlock_t lock; + struct mutex mutex; + int users; + + struct video_device *vdev; + + struct videobuf_queue s0_vbq; + struct videobuf_buffer *active; + struct list_head outq; + struct list_head nextq; + + int output; + u32 *outb; + dma_addr_t outb_phys; + + /* Current S0 configuration */ + struct pxp_data_format *s0_fmt; + u32 s0_width; + u32 s0_height; + u32 s0_bgcolor; + u32 s0_chromakey; + + struct v4l2_framebuffer fb; + struct v4l2_rect drect; + struct v4l2_rect srect; + + /* Transformation support */ + int scaling; + int hflip; + int vflip; + int rotate; + int yuv; + + /* Output overlay support */ + int overlay_state; + int global_alpha_state; + u8 global_alpha; + int local_alpha_state; + int s1_chromakey_state; + u32 s1_chromakey; + + /* PXP_NEXT */ + u32 regs_phys; + struct pxp_registers *regs_virt; + wait_queue_head_t done; + int next_queue_ended; + + /* notifier for PXP when fb changed */ + struct notifier_block nb; +}; + +struct pxp_data_format { + char *name; + unsigned int bpp; + u32 fourcc; + enum v4l2_colorspace colorspace; + u32 ctrl_s0_fmt; +}; + +extern int stmp3xxxfb_get_info(struct fb_var_screeninfo *var, + struct fb_fix_screeninfo *fix); +extern void stmp3xxxfb_cfg_pxp(int enable, dma_addr_t pxp_phys); diff --git a/drivers/media/video/videobuf-dma-contig.c b/drivers/media/video/videobuf-dma-contig.c index 74730c624cfc..f57db6034a25 100644 --- a/drivers/media/video/videobuf-dma-contig.c +++ b/drivers/media/video/videobuf-dma-contig.c @@ -292,7 +292,7 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q, mem->size = PAGE_ALIGN(buf->bsize); mem->vaddr = dma_alloc_coherent(q->dev, mem->size, - &mem->dma_handle, GFP_KERNEL); + &mem->dma_handle, GFP_DMA); if (!mem->vaddr) { dev_err(q->dev, "dma_alloc_coherent size %ld failed\n", mem->size); @@ -306,7 +306,7 @@ static int __videobuf_mmap_mapper(struct videobuf_queue *q, size = vma->vm_end - vma->vm_start; size = (size < mem->size) ? size : mem->size; - vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + vma->vm_page_prot = pgprot_writethru(vma->vm_page_prot); retval = remap_pfn_range(vma, vma->vm_start, mem->dma_handle >> PAGE_SHIFT, size, vma->vm_page_prot); diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 9da0e504bbe9..0da643fe59f6 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -347,6 +347,15 @@ config MFD_WM8994 core support for the WM8994, in order to use the actual functionaltiy of the device other drivers must be enabled. +config MFD_LTC3589 + bool + depends on GENERIC_HARDIRQS + +config MFD_LTC3589_I2C + bool "Support for Linear LTC3589 with I2C" + select MFD_LTC3589 + depends on I2C=y && GENERIC_HARDIRQS + config MFD_PCF50633 tristate "Support for NXP PCF50633" depends on I2C @@ -366,6 +375,17 @@ config MFD_MC13783 additional drivers must be enabled in order to use the functionality of the device. +config PMIC_DA9052 + tristate "Dialog DA9052 with SPI/I2C" + depends on SPI_MASTER=y + depends on I2C=y + select MFD_CORE + help + SPI/I2C Support for the Dialog semiconductor DA9052 PMIC. + This driver provides common support for accessing the device, + additional drivers must be enabled in order to use the + functionality of the device. + config PCF50633_ADC tristate "Support for NXP PCF50633 ADC" depends on MFD_PCF50633 @@ -482,6 +502,13 @@ config MFD_JANZ_CMODIO host many different types of MODULbus daughterboards, including CAN and GPIO controllers. +config MFD_MAX17135 + tristate "MAX17135 PMIC core" + depends on I2C + help + This is the MAX17135 PMIC support. It includes + core support for communication with the MAX17135 chip. + endif # MFD_SUPPORT menu "Multimedia Capabilities Port drivers" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index fb503e77dc60..36919bd16e85 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -29,6 +29,8 @@ obj-$(CONFIG_MFD_WM8350) += wm8350.o obj-$(CONFIG_MFD_WM8350_I2C) += wm8350-i2c.o obj-$(CONFIG_MFD_WM8994) += wm8994-core.o wm8994-irq.o +obj-$(CONFIG_REGULATOR_LTC3589) += ltc3589-i2c.o + obj-$(CONFIG_TPS65010) += tps65010.o obj-$(CONFIG_TPS6507X) += tps6507x.o obj-$(CONFIG_MENELAUS) += menelaus.o @@ -71,3 +73,10 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o obj-$(CONFIG_LPC_SCH) += lpc_sch.o obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o +obj-$(CONFIG_MFD_MAX17135) += max17135-core.o + +#ifeq ($(CONFIG_PMIC_DA9052),y) +da9052-objs := da9052-spi.o da9052-i2c.o da9052-core.o +obj-$(CONFIG_PMIC_DA9052) += da9052.o +#endif + diff --git a/drivers/mfd/da9052-core.c b/drivers/mfd/da9052-core.c new file mode 100644 index 000000000000..68e8393a455f --- /dev/null +++ b/drivers/mfd/da9052-core.c @@ -0,0 +1,521 @@ +/* + * da9052-core.c -- Device access for Dialog DA9052 + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * Author: Dialog Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SUCCESS 0 +#define FAILURE 1 + +struct da9052_eh_nb eve_nb_array[EVE_CNT]; +static struct da9052_ssc_ops ssc_ops; +struct mutex manconv_lock; +static struct semaphore eve_nb_array_lock; + +void da9052_lock(struct da9052 *da9052) +{ + mutex_lock(&da9052->ssc_lock); +} +EXPORT_SYMBOL(da9052_lock); + +void da9052_unlock(struct da9052 *da9052) +{ + mutex_unlock(&da9052->ssc_lock); +} +EXPORT_SYMBOL(da9052_unlock); + +int da9052_ssc_write(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg) +{ + int ret = 0; + + /* Reg address should be a valid address on PAGE0 or PAGE1 */ + if ((sscmsg->addr < DA9052_PAGE0_REG_START) || + (sscmsg->addr > DA9052_PAGE1_REG_END) || + ((sscmsg->addr > DA9052_PAGE0_REG_END) && + (sscmsg->addr < DA9052_PAGE1_REG_START))) + return INVALID_REGISTER; + + ret = ssc_ops.write(da9052, sscmsg); + + /* Update local cache if required */ + if (!ret) { + /* Check if this register is Non-volatile*/ + if (da9052->ssc_cache[sscmsg->addr].type != VOLATILE) { + /* Update value */ + da9052->ssc_cache[sscmsg->addr].val = sscmsg->data; + /* Make this cache entry valid */ + da9052->ssc_cache[sscmsg->addr].status = VALID; + } + } + + return ret; +} + +int da9052_ssc_read(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg) +{ + int ret = 0; + + /* Reg addr should be a valid address on PAGE0 or PAGE1 */ + if ((sscmsg->addr < DA9052_PAGE0_REG_START) || + (sscmsg->addr > DA9052_PAGE1_REG_END) || + ((sscmsg->addr > DA9052_PAGE0_REG_END) && + (sscmsg->addr < DA9052_PAGE1_REG_START))) + return INVALID_REGISTER; + + /* + * Check if this is a Non-volatile register, if yes then return value - + * from cache instead of actual reading from hardware. Before reading - + * cache entry, make sure that the entry is valid + */ + /* The read request is for Non-volatile register */ + /* Check if we have valid cached value for this */ + if (da9052->ssc_cache[sscmsg->addr].status == VALID) { + /* We have valid cached value, copy this value */ + sscmsg->data = da9052->ssc_cache[sscmsg->addr].val; + + return 0; + } + + ret = ssc_ops.read(da9052, sscmsg); + + /* Update local cache if required */ + if (!ret) { + /* Check if this register is Non-volatile*/ + if (da9052->ssc_cache[sscmsg->addr].type != VOLATILE) { + /* Update value */ + da9052->ssc_cache[sscmsg->addr].val = sscmsg->data; + /* Make this cache entry valid */ + da9052->ssc_cache[sscmsg->addr].status = VALID; + } + } + + return ret; +} + +int da9052_ssc_write_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg, + int msg_no) +{ + int ret = 0; + int cnt = 0; + + /* Check request size */ + if (msg_no > MAX_READ_WRITE_CNT) + return -EIO; + + ret = ssc_ops.write_many(da9052, sscmsg, msg_no); + /* Update local cache, if required */ + for (cnt = 0; cnt < msg_no; cnt++) { + /* Check if this register is Non-volatile*/ + if (da9052->ssc_cache[sscmsg[cnt].addr].type != VOLATILE) { + /* Update value */ + da9052->ssc_cache[sscmsg[cnt].addr].val = + sscmsg[cnt].data; + /* Make this cache entry valid */ + da9052->ssc_cache[sscmsg[cnt].addr].status = VALID; + } + } + return ret; +} + +int da9052_ssc_read_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg, + int msg_no) +{ + int ret = 0; + int cnt = 0; + + /* Check request size */ + if (msg_no > MAX_READ_WRITE_CNT) + return -EIO; + + ret = ssc_ops.read_many(da9052, sscmsg, msg_no); + /* Update local cache, if required */ + for (cnt = 0; cnt < msg_no; cnt++) { + /* Check if this register is Non-volatile*/ + if (da9052->ssc_cache[sscmsg[cnt].addr].type + != VOLATILE) { + /* Update value */ + da9052->ssc_cache[sscmsg[cnt].addr].val = + sscmsg[cnt].data; + /* Make this cache entry valid */ + da9052->ssc_cache[sscmsg[cnt].addr].status = VALID; + } + } + return ret; +} + +static irqreturn_t da9052_eh_isr(int irq, void *dev_id) +{ + struct da9052 *da9052 = dev_id; + /* Schedule work to be done */ + schedule_work(&da9052->eh_isr_work); + /* Disable IRQ */ + disable_irq_nosync(da9052->irq); + return IRQ_HANDLED; +} + +int eh_register_nb(struct da9052 *da9052, struct da9052_eh_nb *nb) +{ + + if (nb == NULL) { + printk(KERN_INFO "EH REGISTER FUNCTION FAILED\n"); + return -EINVAL; + } + + if (nb->eve_type >= EVE_CNT) { + printk(KERN_INFO "Invalid DA9052 Event Type\n"); + return -EINVAL; + } + + /* Initialize list head inside notifier block */ + INIT_LIST_HEAD(&nb->nb_list); + + /* Acquire NB array lock */ + if (down_interruptible(&eve_nb_array_lock)) + return -EAGAIN; + + /* Add passed NB to corresponding EVENT list */ + list_add_tail(&nb->nb_list, &(eve_nb_array[nb->eve_type].nb_list)); + + /* Release NB array lock */ + up(&eve_nb_array_lock); + + return 0; +} + +int eh_unregister_nb(struct da9052 *da9052, struct da9052_eh_nb *nb) +{ + + if (nb == NULL) + return -EINVAL; + + /* Acquire nb array lock */ + if (down_interruptible(&eve_nb_array_lock)) + return -EAGAIN; + + /* Remove passed NB from list */ + list_del_init(&(nb->nb_list)); + + /* Release NB array lock */ + up(&eve_nb_array_lock); + + return 0; +} + +static int process_events(struct da9052 *da9052, int events_sts) +{ + + int cnt = 0; + int tmp_events_sts = 0; + unsigned char event = 0; + + struct list_head *ptr; + struct da9052_eh_nb *nb_ptr; + + /* Now we have retrieved all events, process them one by one */ + //for (cnt = 0; cnt < PRIO_CNT; cnt++) { + for (cnt = 0; cnt < EVE_CNT; cnt++) { + /* + * Starting with highest priority event, + * traverse through all event + */ + tmp_events_sts = events_sts; + + /* Find the event associated with higher priority */ + + /* KPIT NOTE: This is commented as we are not using prioritization */ + // event = eve_prio_map[cnt]; + event = cnt; + + /* Check if interrupt is received for this event */ + /* KPIT : event is commneted to not use prioritization */ + //if (!((tmp_events_sts >> event) & 0x1)) { + if (!((tmp_events_sts >> cnt) & 0x1)) + /* Event bit is not set for this event */ + /* Move to next priority event */ + continue; + + if (event == PEN_DOWN_EVE) { + if (list_empty(&(eve_nb_array[event].nb_list))) + continue; + } + /* Event bit is set, execute all registered call backs */ + if (down_interruptible(&eve_nb_array_lock)){ + printk(KERN_CRIT "Can't acquire eve_nb_array_lock \n"); + return -EIO; + } + + list_for_each(ptr, &(eve_nb_array[event].nb_list)) { + /* + * nb_ptr will point to the structure in which + * nb_list is embedded + */ + nb_ptr = list_entry(ptr, struct da9052_eh_nb, nb_list); + nb_ptr->call_back(nb_ptr, events_sts); + } + up(&eve_nb_array_lock); + } + return 0; +} + +void eh_workqueue_isr(struct work_struct *work) +{ + struct da9052 *da9052 = + container_of(work, struct da9052, eh_isr_work); + + struct da9052_ssc_msg eve_data[4]; + int events_sts, ret; + unsigned char cnt = 0; + + /* nIRQ is asserted, read event registeres to know what happened */ + events_sts = 0; + + /* Prepare ssc message to read all four event registers */ + for (cnt = 0; cnt < 4; cnt++) { + eve_data[cnt].addr = (DA9052_EVENTA_REG + cnt); + eve_data[cnt].data = 0; + } + + /* Now read all event registers */ + da9052_lock(da9052); + + ret = da9052_ssc_read_many(da9052, eve_data, 4); + if (ret) { + enable_irq(da9052->irq); + da9052_unlock(da9052); + return; + } + + /* Collect all events */ + for (cnt = 0; cnt < 4; cnt++) + events_sts |= (eve_data[cnt].data << (8 * cnt)); + + /* Check if we really got any event */ + if (events_sts == 0) { + enable_irq(da9052->irq); + da9052_unlock(da9052); + return; + } + da9052_unlock(da9052); + + /* Process all events occurred */ + process_events(da9052, events_sts); + + da9052_lock(da9052); + /* Now clear EVENT registers */ + for (cnt = 0; cnt < 4; cnt++) { + if (eve_data[cnt].data) { + ret = da9052_ssc_write(da9052, &eve_data[cnt]); + if (ret) { + enable_irq(da9052->irq); + da9052_unlock(da9052); + return; + } + } + } + da9052_unlock(da9052); + + /* + * This delay is necessary to avoid hardware fake interrupts + * from DA9052. + */ + udelay(50); + /* Enable HOST interrupt */ + enable_irq(da9052->irq); +} + +static void da9052_eh_restore_irq(struct da9052 *da9052) +{ + /* Put your platform and board specific code here */ + free_irq(da9052->irq, NULL); +} + +static int da9052_add_subdevice_pdata(struct da9052 *da9052, + const char *name, void *pdata, size_t pdata_size) +{ + struct mfd_cell cell = { + .name = name, + .platform_data = pdata, + .data_size = pdata_size, + }; + return mfd_add_devices(da9052->dev, -1, &cell, 1, NULL, 0); +} + +static int da9052_add_subdevice(struct da9052 *da9052, const char *name) +{ + return da9052_add_subdevice_pdata(da9052, name, NULL, 0); +} + +static int add_da9052_devices(struct da9052 *da9052) +{ + s32 ret = 0; + struct da9052_platform_data *pdata = da9052->dev->platform_data; + struct da9052_leds_platform_data leds_data = { + .num_leds = pdata->led_data->num_leds, + .led = pdata->led_data->led, + }; + struct da9052_regulator_platform_data regulator_pdata = { + .regulators = pdata->regulators, + }; + + struct da9052_tsi_platform_data tsi_data = *(pdata->tsi_data); + struct da9052_bat_platform_data bat_data = *(pdata->bat_data); + + if (pdata && pdata->init) { + ret = pdata->init(da9052); + if (ret != 0) + return ret; + } else + pr_err("No platform initialisation supplied\n"); + ret = da9052_add_subdevice(da9052, "da9052-rtc"); + if (ret) + return ret; + ret = da9052_add_subdevice(da9052, "da9052-onkey"); + if (ret) + return ret; + + ret = da9052_add_subdevice(da9052, "WLED-1"); + if (ret) + return ret; + + ret = da9052_add_subdevice(da9052, "WLED-2"); + if (ret) + return ret; + + ret = da9052_add_subdevice(da9052, "WLED-3"); + if (ret) + return ret; + + ret = da9052_add_subdevice(da9052, "da9052-adc"); + if (ret) + return ret; + + ret = da9052_add_subdevice(da9052, "da9052-wdt"); + if (ret) + return ret; + + ret = da9052_add_subdevice_pdata(da9052, "da9052-leds", + &leds_data, sizeof(leds_data)); + if (ret) + return ret; + + ret = da9052_add_subdevice_pdata(da9052, "da9052-regulator", + ®ulator_pdata, sizeof(regulator_pdata)); + if (ret) + return ret; + + ret = da9052_add_subdevice_pdata(da9052, "da9052-tsi", + &tsi_data, sizeof(tsi_data)); + if (ret) + return ret; + + ret = da9052_add_subdevice_pdata(da9052, "da9052-bat", + &bat_data, sizeof(bat_data)); + if (ret) + return ret; + + return ret; +} + +int da9052_ssc_init(struct da9052 *da9052) +{ + int cnt; + struct da9052_platform_data *pdata; + struct da9052_ssc_msg ssc_msg; + + /* Initialize eve_nb_array */ + for (cnt = 0; cnt < EVE_CNT; cnt++) + INIT_LIST_HEAD(&(eve_nb_array[cnt].nb_list)); + + /* Initialize mutex required for ADC Manual read */ + mutex_init(&manconv_lock); + + /* Initialize NB array lock */ + init_MUTEX(&eve_nb_array_lock); + + /* Assign the read-write function pointers */ + da9052->read = da9052_ssc_read; + da9052->write = da9052_ssc_write; + da9052->read_many = da9052_ssc_read_many; + da9052->write_many = da9052_ssc_write_many; + + if (SPI == da9052->connecting_device && ssc_ops.write == NULL) { + /* Assign the read/write pointers to SPI/read/write */ + ssc_ops.write = da9052_spi_write; + ssc_ops.read = da9052_spi_read; + ssc_ops.write_many = da9052_spi_write_many; + ssc_ops.read_many = da9052_spi_read_many; + } + else if (I2C == da9052->connecting_device && ssc_ops.write == NULL) { + /* Assign the read/write pointers to SPI/read/write */ + ssc_ops.write = da9052_i2c_write; + ssc_ops.read = da9052_i2c_read; + ssc_ops.write_many = da9052_i2c_write_many; + ssc_ops.read_many = da9052_i2c_read_many; + } else + return -1; + + /* Assign the EH notifier block register/de-register functions */ + da9052->register_event_notifier = eh_register_nb; + da9052->unregister_event_notifier = eh_unregister_nb; + + /* Initialize ssc lock */ + mutex_init(&da9052->ssc_lock); + + pdata = da9052->dev->platform_data; + add_da9052_devices(da9052); + + INIT_WORK(&da9052->eh_isr_work, eh_workqueue_isr); + + ssc_msg.addr = DA9052_IRQMASKA_REG; + ssc_msg.data = 0xff; + da9052->write(da9052, &ssc_msg); + ssc_msg.addr = DA9052_IRQMASKC_REG; + ssc_msg.data = 0xff; + da9052->write(da9052, &ssc_msg); + if (request_irq(da9052->irq, da9052_eh_isr, IRQ_TYPE_LEVEL_LOW, + DA9052_EH_DEVICE_NAME, da9052)) + return -EIO; + enable_irq_wake(da9052->irq); + + return 0; +} + +void da9052_ssc_exit(struct da9052 *da9052) +{ + printk(KERN_INFO "DA9052: Unregistering SSC device.\n"); + mutex_destroy(&manconv_lock); + /* Restore IRQ line */ + da9052_eh_restore_irq(da9052); + free_irq(da9052->irq, NULL); + mutex_destroy(&da9052->ssc_lock); + mutex_destroy(&da9052->eve_nb_lock); + return; +} + +MODULE_AUTHOR("Dialog Semiconductor Ltd "); +MODULE_DESCRIPTION("DA9052 MFD Core"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DA9052_SSC_DEVICE_NAME); diff --git a/drivers/mfd/da9052-i2c.c b/drivers/mfd/da9052-i2c.c new file mode 100644 index 000000000000..4f050896d962 --- /dev/null +++ b/drivers/mfd/da9052-i2c.c @@ -0,0 +1,377 @@ +/* + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * da9052-i2c.c: I2C SSC (Synchronous Serial Communication) driver for DA9052 + */ + +#include +#include +#include +#include +#include + +static struct da9052 *da9052_i2c; + +#define I2C_CONNECTED 0 + +static int da9052_i2c_is_connected(void) +{ + + struct da9052_ssc_msg msg; + + //printk("Entered da9052_i2c_is_connected.............\n"); + + msg.addr = DA9052_INTERFACE_REG; + + /* Test spi connectivity by performing read of the GPIO_0-1 register */ + if ( 0 != da9052_i2c_read(da9052_i2c, &msg)) { + printk("da9052_i2c_is_connected - i2c read failed.............\n"); + return -1; + } + else { + printk("da9052_i2c_is_connected - i2c read success..............\n"); + return 0; + } + +} + +static int __devinit da9052_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct i2c_adapter *adapter; + // printk("\n\tEntered da9052_i2c_is_probe.............\n"); + + da9052_i2c = kzalloc(sizeof(struct da9052), GFP_KERNEL); + + if (!da9052_i2c) + return -ENOMEM; + + /* Get the bus driver handler */ + adapter = to_i2c_adapter(client->dev.parent); + + /* Check i2c bus driver supports byte data transfer */ + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_info(&client->dev,\ + "Error in %s:i2c_check_functionality\n", __func__); + return -ENODEV;; + } + + /* Store handle to i2c client */ + da9052_i2c->i2c_client = client; + da9052_i2c->irq = client->irq; + + da9052_i2c->dev = &client->dev; + + /* Initialize i2c data structure here*/ + da9052_i2c->adapter = adapter; + + /* host i2c driver looks only first 7 bits for the slave address */ + da9052_i2c->slave_addr = DA9052_I2C_ADDR >> 1; + + /* Store the i2c client data */ + i2c_set_clientdata(client, da9052_i2c); + + /* Validate I2C connectivity */ + if ( I2C_CONNECTED == da9052_i2c_is_connected()) { + /* I2C is connected */ + da9052_i2c->connecting_device = I2C; + if( 0!= da9052_ssc_init(da9052_i2c) ) + return -ENODEV; + } + else { + return -ENODEV; + } + + //printk("Exiting da9052_i2c_probe.....\n"); + + return 0; +} + +static int da9052_i2c_remove(struct i2c_client *client) +{ + + struct da9052 *da9052 = i2c_get_clientdata(client); + + mfd_remove_devices(da9052->dev); + kfree(da9052); + return 0; +} + +int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg) +{ + struct i2c_msg i2cmsg; + unsigned char buf[2] = {0}; + int ret = 0; + + /* Copy the ssc msg to local character buffer */ + buf[0] = msg->addr; + buf[1] = msg->data; + + /*Construct a i2c msg for a da9052 driver ssc message request */ + i2cmsg.addr = da9052->slave_addr; + i2cmsg.len = 2; + i2cmsg.buf = buf; + + /* To write the data on I2C set flag to zero */ + i2cmsg.flags = 0; + + /* Start the i2c transfer by calling host i2c driver function */ + ret = i2c_transfer(da9052->adapter, &i2cmsg, 1); + + if (ret < 0) { + dev_info(&da9052->i2c_client->dev,\ + "_%s:master_xfer Failed!!\n", __func__); + return ret; + } + + return 0; +} + +int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg) +{ + + /*Get the da9052_i2c client details*/ + unsigned char buf[2] = {0, 0}; + struct i2c_msg i2cmsg[2]; + int ret = 0; + + /* Copy SSC Msg to local character buffer */ + buf[0] = msg->addr; + + /*Construct a i2c msg for a da9052 driver ssc message request */ + i2cmsg[0].addr = da9052->slave_addr ; + i2cmsg[0].len = 1; + i2cmsg[0].buf = &buf[0]; + + /*To write the data on I2C set flag to zero */ + i2cmsg[0].flags = 0; + + /* Read the data from da9052*/ + /*Construct a i2c msg for a da9052 driver ssc message request */ + i2cmsg[1].addr = da9052->slave_addr ; + i2cmsg[1].len = 1; + i2cmsg[1].buf = &buf[1]; + + /*To read the data on I2C set flag to I2C_M_RD */ + i2cmsg[1].flags = I2C_M_RD; + + /* Start the i2c transfer by calling host i2c driver function */ + ret = i2c_transfer(da9052->adapter, i2cmsg, 2); + if (ret < 0) { + dev_info(&da9052->i2c_client->dev,\ + "2 - %s:master_xfer Failed!!\n", __func__); + return ret; + } + + msg->data = *i2cmsg[1].buf; + + return 0; +} + +int da9052_i2c_write_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no) +{ + + struct i2c_msg i2cmsg; + unsigned char data_buf[MAX_READ_WRITE_CNT+1]; + struct da9052_ssc_msg ctrlb_msg; + struct da9052_ssc_msg *msg_queue = sscmsg; + int ret = 0; + /* Flag to check if requested registers are contiguous */ + unsigned char cont_data = 1; + unsigned char cnt = 0; + + /* Check if requested registers are contiguous */ + for (cnt = 1; cnt < msg_no; cnt++) { + if ((msg_queue[cnt].addr - msg_queue[cnt-1].addr) != 1) { + /* Difference is not 1, i.e. non-contiguous registers */ + cont_data = 0; + break; + } + } + + if (cont_data == 0) { + /* Requested registers are non-contiguous */ + for (cnt = 0; cnt < msg_no; cnt++) { + ret = da9052->write(da9052, &msg_queue[cnt]); + if (ret != 0) + return ret; + } + return 0; + } + /* + * Requested registers are contiguous + * or PAGE WRITE sequence of I2C transactions is as below + * (slave_addr + reg_addr + data_1 + data_2 + ...) + * First read current WRITE MODE via CONTROL_B register of DA9052 + */ + ctrlb_msg.addr = DA9052_CONTROLB_REG; + ctrlb_msg.data = 0x0; + ret = da9052->read(da9052, &ctrlb_msg); + + if (ret != 0) + return ret; + + /* Check if PAGE WRITE mode is set */ + if (ctrlb_msg.data & DA9052_CONTROLB_WRITEMODE) { + /* REPEAT WRITE mode is configured */ + /* Now set DA9052 into PAGE WRITE mode */ + ctrlb_msg.data &= ~DA9052_CONTROLB_WRITEMODE; + ret = da9052->write(da9052, &ctrlb_msg); + + if (ret != 0) + return ret; + } + + /* Put first register address */ + data_buf[0] = msg_queue[0].addr; + + for (cnt = 0; cnt < msg_no; cnt++) + data_buf[cnt+1] = msg_queue[cnt].data; + + /* Construct a i2c msg for PAGE WRITE */ + i2cmsg.addr = da9052->slave_addr ; + /* First register address + all data*/ + i2cmsg.len = (msg_no + 1); + i2cmsg.buf = data_buf; + + /*To write the data on I2C set flag to zero */ + i2cmsg.flags = 0; + + /* Start the i2c transfer by calling host i2c driver function */ + ret = i2c_transfer(da9052->adapter, &i2cmsg, 1); + if (ret < 0) { + dev_info(&da9052->i2c_client->dev,\ + "1 - i2c_transfer function falied in [%s]!!!\n", __func__); + return ret; + } + + return 0; +} + +int da9052_i2c_read_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no) +{ + + struct i2c_msg i2cmsg; + unsigned char data_buf[MAX_READ_WRITE_CNT]; + struct da9052_ssc_msg *msg_queue = sscmsg; + int ret = 0; + /* Flag to check if requested registers are contiguous */ + unsigned char cont_data = 1; + unsigned char cnt = 0; + + /* Check if requested registers are contiguous */ + for (cnt = 1; cnt < msg_no; cnt++) { + if ((msg_queue[cnt].addr - msg_queue[cnt-1].addr) != 1) { + /* Difference is not 1, i.e. non-contiguous registers */ + cont_data = 0; + break; + } + } + + if (cont_data == 0) { + /* Requested registers are non-contiguous */ + for (cnt = 0; cnt < msg_no; cnt++) { + ret = da9052->read(da9052, &msg_queue[cnt]); + if (ret != 0) { + dev_info(&da9052->i2c_client->dev,\ + "Error in %s", __func__); + return ret; + } + } + return 0; + } + + /* + * We want to perform PAGE READ via I2C + * For PAGE READ sequence of I2C transactions is as below + * (slave_addr + reg_addr) + (slave_addr + data_1 + data_2 + ...) + */ + /* Copy address of first register */ + data_buf[0] = msg_queue[0].addr; + + /* Construct a i2c msg for first transaction of PAGE READ i.e. write */ + i2cmsg.addr = da9052->slave_addr ; + i2cmsg.len = 1; + i2cmsg.buf = data_buf; + + /*To write the data on I2C set flag to zero */ + i2cmsg.flags = 0; + + /* Start the i2c transfer by calling host i2c driver function */ + ret = i2c_transfer(da9052->adapter, &i2cmsg, 1); + if (ret < 0) { + dev_info(&da9052->i2c_client->dev,\ + "1 - i2c_transfer function falied in [%s]!!!\n", __func__); + return ret; + } + + /* Now Read the data from da9052 */ + /* Construct a i2c msg for second transaction of PAGE READ i.e. read */ + i2cmsg.addr = da9052->slave_addr ; + i2cmsg.len = msg_no; + i2cmsg.buf = data_buf; + + /*To read the data on I2C set flag to I2C_M_RD */ + i2cmsg.flags = I2C_M_RD; + + /* Start the i2c transfer by calling host i2c driver function */ + ret = i2c_transfer(da9052->adapter, + &i2cmsg, 1); + if (ret < 0) { + dev_info(&da9052->i2c_client->dev,\ + "2 - i2c_transfer function falied in [%s]!!!\n", __func__); + return ret; + } + + /* Gather READ data */ + for (cnt = 0; cnt < msg_no; cnt++) + sscmsg[cnt].data = data_buf[cnt]; + + return 0; +} + +static struct i2c_device_id da9052_ssc_id[] = { + { DA9052_SSC_I2C_DEVICE_NAME, 0}, + {} +}; + +static struct i2c_driver da9052_i2c_driver = { + .driver = { + .name = DA9052_SSC_I2C_DEVICE_NAME, + .owner = THIS_MODULE, + }, + .probe = da9052_i2c_probe, + .remove = da9052_i2c_remove, + .id_table = da9052_ssc_id, +}; + +static int __init da9052_i2c_init(void) +{ + int ret = 0; + // printk("\n\nEntered da9052_i2c_init................\n\n"); + ret = i2c_add_driver(&da9052_i2c_driver); + if (ret != 0) { + printk(KERN_ERR "Unable to register %s\n", DA9052_SSC_I2C_DEVICE_NAME); + return ret; + } + return 0; +} +subsys_initcall(da9052_i2c_init); + +static void __exit da9052_i2c_exit(void) +{ + i2c_del_driver(&da9052_i2c_driver); +} +module_exit(da9052_i2c_exit); + +MODULE_AUTHOR("Dialog Semiconductor Ltd "); +MODULE_DESCRIPTION("I2C driver for Dialog DA9052 PMIC"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DA9052_SSC_I2C_DEVICE_NAME); diff --git a/drivers/mfd/da9052-spi.c b/drivers/mfd/da9052-spi.c new file mode 100644 index 000000000000..9dd90c2d19f9 --- /dev/null +++ b/drivers/mfd/da9052-spi.c @@ -0,0 +1,399 @@ +/* + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * da9052-spi.c: SPI SSC (Synchronous Serial Communication) driver for DA9052 + */ + +#include +#include +#include +#include +#include + + +struct da9052 *da9052_spi; + +#define SPI_CONNECTED 0 + +static int da9052_spi_is_connected(void) +{ + + struct da9052_ssc_msg msg; + + //printk("Entered da9052_spi_is_connected.............\n"); + + msg.addr = DA9052_INTERFACE_REG; + + /* Test spi connectivity by performing read of the GPIO_0-1 register and then verify the read value*/ + if ( 0 != da9052_spi_read(da9052_spi, &msg)) { + printk("da9052_spi_is_connected - spi read failed.............\n"); + return -1; + } + else if( 0x88 != msg.data ){ + printk("da9052_spi_is_connected - spi read failed. Msg data =%x ..............\n",msg.data); + return -1; + } + + return 0; + +} + +static int da9052_spi_probe(struct spi_device *spi) +{ + //printk("\n\tEntered da9052_spi_probe.....\n"); + + da9052_spi = kzalloc(sizeof(struct da9052), GFP_KERNEL); + + if (!da9052_spi) + return -ENOMEM; + + + spi->mode = SPI_MODE_0 | SPI_CPOL; + spi->bits_per_word = 8; + spi_setup(spi); + + da9052_spi->dev = &spi->dev; + + da9052_spi->spi_dev = spi; + + /* + * Allocate memory for RX/TX bufferes used in single register read/write + */ + da9052_spi->spi_rx_buf = kmalloc(2, GFP_KERNEL | GFP_DMA); + if (!da9052_spi->spi_rx_buf) + return -ENOMEM; + + da9052_spi->spi_tx_buf = kmalloc(2, GFP_KERNEL | GFP_DMA); + if (!da9052_spi->spi_tx_buf) + return -ENOMEM; + + da9052_spi->spi_active_page = PAGECON_0; + da9052_spi->rw_pol = 1; + + + dev_set_drvdata(&spi->dev, da9052_spi); + + + /* Validate SPI connectivity */ + if ( SPI_CONNECTED == da9052_spi_is_connected()) { + /* SPI is connected */ + da9052_spi->connecting_device = SPI; + if( 0 != da9052_ssc_init(da9052_spi) ) + return -ENODEV; + } + else { + return -ENODEV; + } + + //printk("Exiting da9052_spi_probe.....\n"); + + return 0; +} + +static int da9052_spi_remove(struct spi_device *spi) +{ + struct da9052 *da9052 = dev_get_drvdata(&spi->dev); + + printk("Entered da9052_spi_remove()\n"); + if(SPI == da9052->connecting_device ) { + da9052_ssc_exit(da9052); + } + mfd_remove_devices(&spi->dev); + kfree(da9052->spi_rx_buf); + kfree(da9052->spi_tx_buf); + kfree(da9052); + return 0; +} + +static struct spi_driver da9052_spi_driver = { + .driver = { + .name = DA9052_SSC_SPI_DEVICE_NAME, + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = da9052_spi_probe, + .remove = __devexit_p(da9052_spi_remove), +}; + + +static int da9052_spi_set_page(struct da9052 *da9052, unsigned char page) +{ + + struct da9052_ssc_msg sscmsg; + struct spi_message message; + struct spi_transfer xfer; + int ret = 0; + + printk("Entered da9052_spi_set_page.....\n"); + if ((page != PAGECON_0) && ((page != PAGECON_128))) + return INVALID_PAGE; + + /* Current configuration is PAGE-0 and write request for PAGE-1 */ + /* set register address */ + sscmsg.addr = DA9052_PAGECON0_REG; + /* set value */ + sscmsg.data = page; + + /* Check value of R/W_POL bit of INTERFACE register */ + if (!da9052->rw_pol) { + /* We need to set 0th bit for write operation */ + sscmsg.addr = ((sscmsg.addr << 1) | RW_POL); + } else { + /* We need to reset 0th bit for write operation */ + sscmsg.addr = (sscmsg.addr << 1); + } + + /* SMDK-6410 host SPI driver specific stuff */ + + /* Build our spi message */ + printk("da9052_spi_set_page - Calling spi_message_init.....\n"); + spi_message_init(&message); + memset(&xfer, 0, sizeof(xfer)); + + xfer.len = 2; + xfer.tx_buf = da9052->spi_tx_buf; + xfer.rx_buf = da9052->spi_rx_buf; + + da9052->spi_tx_buf[0] = sscmsg.addr; + da9052->spi_tx_buf[1] = sscmsg.data; + + printk("da9052_spi_set_page - Calling spi_message_add_tail.....\n"); + spi_message_add_tail(&xfer, &message); + + /* Now, do the i/o */ + printk("da9052_spi_set_page - Calling spi_sync.....\n"); + ret = spi_sync(da9052->spi_dev, &message); + + if (ret == 0) { + /* Active Page set successfully */ + da9052->spi_active_page = page; + return 0; + } else { + /* Error in setting Active Page */ + return ret; + } + + return 0; +} + +int da9052_spi_write(struct da9052 *da9052, struct da9052_ssc_msg *msg) +{ + + struct spi_message message; + struct spi_transfer xfer; + int ret; + + /* + * We need a seperate copy of da9052_ssc_msg so that caller's + * copy remains intact + */ + struct da9052_ssc_msg sscmsg; + + /* Copy callers data in to our local copy */ + sscmsg.addr = msg->addr; + sscmsg.data = msg->data; + + if ((sscmsg.addr > PAGE_0_END) && + (da9052->spi_active_page == PAGECON_0)) { + /* + * Current configuration is PAGE-0 and write request + * for PAGE-1 + */ + da9052_spi_set_page(da9052, PAGECON_128); + /* Set register address accordindly */ + sscmsg.addr = (sscmsg.addr - PAGE_1_START); + } else if ((sscmsg.addr < PAGE_1_START) && + (da9052->spi_active_page == PAGECON_128)) { + /* + * Current configuration is PAGE-1 and write request + * for PAGE-0 + */ + da9052_spi_set_page(da9052, PAGECON_0); + } else if (sscmsg.addr > PAGE_0_END) { + /* + * Current configuration is PAGE-1 and write request + * for PAGE-1. Just need to adjust register address + */ + sscmsg.addr = (sscmsg.addr - PAGE_1_START); + } + + /* Check value of R/W_POL bit of INTERFACE register */ + if (!da9052->rw_pol) { + /* We need to set 0th bit for write operation */ + sscmsg.addr = ((sscmsg.addr << 1) | RW_POL); + } else { + /* We need to reset 0th bit for write operation */ + sscmsg.addr = (sscmsg.addr << 1); + } + + /* SMDK-6410 host SPI driver specific stuff */ + + /* Build our spi message */ + spi_message_init(&message); + memset(&xfer, 0, sizeof(xfer)); + + xfer.len = 2; + xfer.tx_buf = da9052->spi_tx_buf; + xfer.rx_buf = da9052->spi_rx_buf; + + da9052->spi_tx_buf[0] = sscmsg.addr; + da9052->spi_tx_buf[1] = sscmsg.data; + + spi_message_add_tail(&xfer, &message); + + /* Now, do the i/o */ + ret = spi_sync(da9052->spi_dev, &message); + + return ret; +} + +int da9052_spi_write_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg, + int msg_no) +{ + int cnt,ret=0; + + for(cnt = 0; cnt < msg_no; cnt++, sscmsg++) { + ret = da9052_ssc_write(da9052,sscmsg); + if(ret != 0) + { + printk("Error in %s", __FUNCTION__); + return -EIO; + } + } + + return 0; +} + +int da9052_spi_read(struct da9052 *da9052, struct da9052_ssc_msg *msg) +{ + + struct spi_message message; + struct spi_transfer xfer; + int ret; + + /* + * We need a seperate copy of da9052_ssc_msg so that + * caller's copy remains intact + */ + struct da9052_ssc_msg sscmsg; + + + /* Copy callers data in to our local copy */ + sscmsg.addr = msg->addr; + sscmsg.data = msg->data; + + if ((sscmsg.addr > PAGE_0_END) && + (da9052->spi_active_page == PAGECON_0)) { + /* + * Current configuration is PAGE-0 and + * read request for PAGE-1 + */ + printk("da9052_spi_read - if PAGECON_128.....\n"); + da9052_spi_set_page(da9052, PAGECON_128); + /* Set register address accordindly */ + sscmsg.addr = (sscmsg.addr - PAGE_1_START); + } else if ((sscmsg.addr < PAGE_1_START) && + (da9052->spi_active_page == PAGECON_128)) { + /* + * Current configuration is PAGE-1 and + * write request for PAGE-0 + */ + printk("da9052_spi_read - if PAGECON_0.....\n"); + da9052_spi_set_page(da9052, PAGECON_0); + } else if (sscmsg.addr > PAGE_0_END) { + /* + * Current configuration is PAGE-1 and write + * request for PAGE-1 + * Just need to adjust register address + */ + sscmsg.addr = (sscmsg.addr - PAGE_1_START); + } + + /* Check value of R/W_POL bit of INTERFACE register */ + if (da9052->rw_pol) { + /* We need to set 0th bit for read operation */ + sscmsg.addr = ((sscmsg.addr << 1) | RW_POL); + } else { + /* We need to reset 0th bit for write operation */ + sscmsg.addr = (sscmsg.addr << 1); + } + + /* SMDK-6410 host SPI driver specific stuff */ + + /* Build our spi message */ + spi_message_init(&message); + memset(&xfer, 0, sizeof(xfer)); + + xfer.len = 2; + xfer.tx_buf = da9052->spi_tx_buf; + xfer.rx_buf = da9052->spi_rx_buf; + + da9052->spi_tx_buf[0] = sscmsg.addr; + da9052->spi_tx_buf[1] = 0xff; + + da9052->spi_rx_buf[0] = 0; + da9052->spi_rx_buf[1] = 0; + + spi_message_add_tail(&xfer, &message); + + /* Now, do the i/o */ + ret = spi_sync(da9052->spi_dev, &message); + + if (ret == 0) { + /* Update read value in callers copy */ + msg->data = da9052->spi_rx_buf[1]; + return 0; + } else { + return ret; + } + + + return 0; +} + +int da9052_spi_read_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg, + int msg_no) +{ + int cnt,ret=0; + + for(cnt = 0; cnt < msg_no; cnt++, sscmsg++) { + ret = da9052_ssc_read(da9052,sscmsg); + if(ret != 0) + { + printk("Error in %s", __FUNCTION__); + return -EIO; + } + } + + return 0; +} + +static int __init da9052_spi_init(void) +{ + int ret = 0; + //printk("Entered da9052_spi_init.....\n"); + ret = spi_register_driver(&da9052_spi_driver); + if (ret != 0) { + printk(KERN_ERR "Unable to register %s\n", DA9052_SSC_SPI_DEVICE_NAME); + return ret; + } + return 0; +} +module_init(da9052_spi_init); + +static void __exit da9052_spi_exit(void) +{ + spi_unregister_driver(&da9052_spi_driver); +} + +module_exit(da9052_spi_exit); + +MODULE_AUTHOR("Dialog Semiconductor Ltd "); +MODULE_DESCRIPTION("SPI driver for Dialog DA9052 PMIC"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DA9052_SSC_SPI_DEVICE_NAME); diff --git a/drivers/mfd/ltc3589-i2c.c b/drivers/mfd/ltc3589-i2c.c new file mode 100644 index 000000000000..db0017e30827 --- /dev/null +++ b/drivers/mfd/ltc3589-i2c.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file ltc3589-i2c.c + * @brief This is the generic I2C driver for Linear 3589 PMIC. + * + * @ingroup PMIC_CORE + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static inline int ltc3589_i2c_read(struct ltc3589 *ltc, u8 reg) +{ + return i2c_smbus_read_byte_data(ltc->i2c_client, reg); +} + +static inline int ltc3589_i2c_write(struct ltc3589 *ltc, u8 reg, u8 val) +{ + return i2c_smbus_write_byte_data(ltc->i2c_client, reg, val); +} + +static int ltc3589_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct ltc3589 *ltc3589; + struct ltc3589_platform_data *plat_data = i2c->dev.platform_data; + int ret = 0; + + ltc3589 = kzalloc(sizeof(struct ltc3589), GFP_KERNEL); + if (ltc3589 == NULL) + return -ENOMEM; + + i2c_set_clientdata(i2c, ltc3589); + ltc3589->dev = &i2c->dev; + ltc3589->i2c_client = i2c; + ltc3589->read_dev = ltc3589_i2c_read; + ltc3589->write_dev = ltc3589_i2c_write; + + if (ltc3589_i2c_read(ltc3589, 0x33) < 0) { + kfree(ltc3589); + return -ENODEV; + } + + /* so far, we got matched chip on board */ + + ltc3589_client = i2c; + if (plat_data && plat_data->init) { + ret = plat_data->init(ltc3589); + if (ret != 0) + return -EINVAL; + } + + dev_info(&i2c->dev, "Loaded\n"); + + return 0; +} + +static int ltc3589_i2c_remove(struct i2c_client *i2c) +{ + struct ltc3589 *ltc3589 = i2c_get_clientdata(i2c); + + kfree(ltc3589); + return 0; +} + +static const struct i2c_device_id ltc3589_id[] = { + { "ltc3589", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ltc3589_id); + + +static struct i2c_driver ltc3589_i2c_driver = { + .driver = { + .name = "ltc3589", + .owner = THIS_MODULE, + }, + .probe = ltc3589_i2c_probe, + .remove = ltc3589_i2c_remove, + .id_table = ltc3589_id, +}; + +static int __init ltc3589_i2c_init(void) +{ + return i2c_add_driver(<c3589_i2c_driver); +} +/* init early so consumer devices can complete system boot */ +subsys_initcall(ltc3589_i2c_init); + +static void __exit ltc3589_i2c_exit(void) +{ + i2c_del_driver(<c3589_i2c_driver); +} +module_exit(ltc3589_i2c_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("I2C support for the Linear PMIC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/max17135-core.c b/drivers/mfd/max17135-core.c new file mode 100644 index 000000000000..0be007fbcb40 --- /dev/null +++ b/drivers/mfd/max17135-core.c @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +/*! + * @file pmic/core/max17135.c + * @brief This file contains MAX17135 specific PMIC code. This implementaion + * may differ for each PMIC chip. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +struct i2c_client *max17135_client; + +static const unsigned short normal_i2c[] = {0x48, I2C_CLIENT_END}; + +int max17135_reg_read(int reg_num, unsigned int *reg_val) +{ + int result; + + if (max17135_client == NULL) + return PMIC_ERROR; + + if ((reg_num == REG_MAX17135_EXT_TEMP) || + (reg_num == REG_MAX17135_INT_TEMP)) { + result = i2c_smbus_read_word_data(max17135_client, reg_num); + if (result < 0) { + dev_err(&max17135_client->dev, + "Unable to read MAX17135 register via I2C\n"); + return PMIC_ERROR; + } + /* Swap bytes for dword read */ + result = (result >> 8) | ((result & 0xFF) << 8); + } else { + result = i2c_smbus_read_byte_data(max17135_client, reg_num); + if (result < 0) { + dev_err(&max17135_client->dev, + "Unable to read MAX17135 register via I2C\n"); + return PMIC_ERROR; + } + } + + *reg_val = result; + return PMIC_SUCCESS; +} + +int max17135_reg_write(int reg_num, const unsigned int reg_val) +{ + int result; + + if (max17135_client == NULL) + return PMIC_ERROR; + + result = i2c_smbus_write_byte_data(max17135_client, reg_num, reg_val); + if (result < 0) { + dev_err(&max17135_client->dev, + "Unable to write MAX17135 register via I2C\n"); + return PMIC_ERROR; + } + + return PMIC_SUCCESS; +} + +static int max17135_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct max17135 *max17135; + struct max17135_platform_data *pdata = client->dev.platform_data; + int ret = 0; + + if (!pdata || !pdata->init) + return -ENODEV; + + /* Create the PMIC data structure */ + max17135 = kzalloc(sizeof(struct max17135), GFP_KERNEL); + if (max17135 == NULL) { + kfree(client); + return -ENOMEM; + } + + /* Initialize the PMIC data structure */ + i2c_set_clientdata(client, max17135); + max17135->dev = &client->dev; + max17135->i2c_client = client; + + max17135_client = client; + + if (pdata && pdata->init) { + ret = pdata->init(max17135); + if (ret != 0) + goto err; + } + + dev_info(&client->dev, "PMIC MAX17135 for eInk display\n"); + + return ret; +err: + kfree(max17135); + + return ret; +} + + +static int max17135_remove(struct i2c_client *i2c) +{ + struct max17135 *max17135 = i2c_get_clientdata(i2c); + int i; + + for (i = 0; i < ARRAY_SIZE(max17135->pdev); i++) + platform_device_unregister(max17135->pdev[i]); + + kfree(max17135); + + return 0; +} + +static int max17135_suspend(struct i2c_client *client, pm_message_t state) +{ + return 0; +} + +static int max17135_resume(struct i2c_client *client) +{ + return 0; +} + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int max17135_detect(struct i2c_client *client, + struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + u8 chip_rev, chip_id; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -ENODEV; + + /* detection */ + if (i2c_smbus_read_byte_data(client, + REG_MAX17135_PRODUCT_REV) != 0) { + dev_err(&adapter->dev, + "Max17135 PMIC not found!\n"); + return -ENODEV; + } + + /* identification */ + chip_rev = i2c_smbus_read_byte_data(client, + REG_MAX17135_PRODUCT_REV); + chip_id = i2c_smbus_read_byte_data(client, + REG_MAX17135_PRODUCT_ID); + + if (chip_rev != 0x00 || chip_id != 0x4D) { /* identification failed */ + dev_info(&adapter->dev, + "Unsupported chip (man_id=0x%02X, " + "chip_id=0x%02X).\n", chip_rev, chip_id); + return -ENODEV; + } + + strlcpy(info->type, "max17135_sensor", I2C_NAME_SIZE); + + return 0; +} + +static const struct i2c_device_id max17135_id[] = { + { "max17135", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, max17135_id); + + +static struct i2c_driver max17135_driver = { + .driver = { + .name = "max17135", + .owner = THIS_MODULE, + }, + .probe = max17135_probe, + .remove = max17135_remove, + .suspend = max17135_suspend, + .resume = max17135_resume, + .id_table = max17135_id, + .detect = max17135_detect, + .address_list = &normal_i2c, +}; + +static int __init max17135_init(void) +{ + return i2c_add_driver(&max17135_driver); +} + +static void __exit max17135_exit(void) +{ + i2c_del_driver(&max17135_driver); +} + +/* + * Module entry points + */ +subsys_initcall_sync(max17135_init); +module_exit(max17135_exit); diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c index b5807484b4c9..1ff6ddfd6aaf 100644 --- a/drivers/mfd/wm8350-core.c +++ b/drivers/mfd/wm8350-core.c @@ -721,7 +721,8 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq, } } - wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0); + /*mask gpio and rtc interrupt*/ + wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x50); wm8350_client_dev_register(wm8350, "wm8350-codec", &(wm8350->codec.pdev)); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 26386a92f5aa..c13aa6fe558a 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -353,6 +353,24 @@ config VMWARE_BALLOON To compile this driver as a module, choose M here: the module will be called vmware_balloon. +config MXS_PERSISTENT + tristate "MX23/MX28 persistent bit" + depends on ARCH_MXS + default y + +config MXS_PERFMON + tristate "i.MX Performance Monitor" + depends on ARCH_MX28 || ARCH_MX50 + default y + +config ANDROID_PMEM + bool "Android pmem allocator" + default n + +config UID_STAT + bool "UID based statistics tracking exported to /proc/uid_stat" + default n + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 6ed06a19474a..281eb2e73e1f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -28,6 +28,10 @@ obj-$(CONFIG_DS1682) += ds1682.o obj-$(CONFIG_TI_DAC7512) += ti_dac7512.o obj-$(CONFIG_C2PORT) += c2port/ obj-$(CONFIG_IWMC3200TOP) += iwmc3200top/ +obj-$(CONFIG_MXS_PERSISTENT) += mxs-persistent.o +obj-$(CONFIG_MXS_PERFMON) += mxs-perfmon.o obj-y += eeprom/ obj-y += cb710/ obj-$(CONFIG_VMWARE_BALLOON) += vmware_balloon.o +obj-$(CONFIG_ANDROID_PMEM) += pmem.o +obj-$(CONFIG_UID_STAT) += uid_stat.o diff --git a/drivers/misc/mxs-perfmon.c b/drivers/misc/mxs-perfmon.c new file mode 100644 index 000000000000..51228ec3bf89 --- /dev/null +++ b/drivers/misc/mxs-perfmon.c @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "regs-perfmon.h" + +#define MONITOR "Monitor" + +struct mxs_perfmon_cmd_config { + int field; + int val; + const char *cmd; +}; + +static struct mxs_perfmon_cmd_config +common_perfmon_cmd_config[] = { + {.val = 1, .cmd = "start", .field = BM_PERFMON_CTRL_RUN }, + {.val = 0, .cmd = "stop", .field = BM_PERFMON_CTRL_RUN }, + {.val = 1, .cmd = "fetch", .field = BM_PERFMON_CTRL_SNAP }, + {.val = 1, .cmd = "clear", .field = BM_PERFMON_CTRL_CLR }, + {.val = 1, .cmd = "read", .field = BM_PERFMON_CTRL_READ_EN }, + {.val = 0, .cmd = "write", .field = BM_PERFMON_CTRL_READ_EN } +}; + +static struct mxs_perfmon_bit_config +common_perfmon_bit_config[] = { + {.reg = HW_PERFMON_CTRL, .name = MONITOR, + .field = ~0 }, + {.reg = HW_PERFMON_CTRL, .name = "Trap-En", + .field = BM_PERFMON_CTRL_TRAP_ENABLE }, + {.reg = HW_PERFMON_CTRL, .name = "Trap-In-Range", + .field = BM_PERFMON_CTRL_TRAP_IN_RANGE }, + {.reg = HW_PERFMON_CTRL, .name = "Latency-En", + .field = BM_PERFMON_CTRL_LATENCY_ENABLE }, + {.reg = HW_PERFMON_CTRL, .name = "Trap-IRQ", + .field = BM_PERFMON_CTRL_TRAP_IRQ }, + {.reg = HW_PERFMON_CTRL, .name = "Latency-IRQ", + .field = BM_PERFMON_CTRL_LATENCY_IRQ }, + {.reg = HW_PERFMON_TRAP_ADDR_LOW, .name = "Trap-Low", + .field = BM_PERFMON_TRAP_ADDR_LOW_ADDR }, + {.reg = HW_PERFMON_TRAP_ADDR_HIGH, .name = "Trap-High", + .field = BM_PERFMON_TRAP_ADDR_HIGH_ADDR }, + {.reg = HW_PERFMON_LAT_THRESHOLD, .name = "Latency-Threshold", + .field = BM_PERFMON_LAT_THRESHOLD_VALUE }, + {.reg = HW_PERFMON_ACTIVE_CYCLE, .name = "Active-Cycle", + .field = BM_PERFMON_ACTIVE_CYCLE_COUNT }, + {.reg = HW_PERFMON_TRANSFER_COUNT, .name = "Transfer-count", + .field = BM_PERFMON_TRANSFER_COUNT_VALUE }, + {.reg = HW_PERFMON_TOTAL_LATENCY, .name = "Latency-count", + .field = BM_PERFMON_TOTAL_LATENCY_COUNT }, + {.reg = HW_PERFMON_DATA_COUNT, .name = "Data-count", + .field = BM_PERFMON_DATA_COUNT_COUNT }, + {.reg = HW_PERFMON_MAX_LATENCY, .name = "ABurst", + .field = BM_PERFMON_MAX_LATENCY_ABURST }, + {.reg = HW_PERFMON_MAX_LATENCY, .name = "ALen", + .field = BM_PERFMON_MAX_LATENCY_ALEN }, + {.reg = HW_PERFMON_MAX_LATENCY, .name = "ASize", + .field = BM_PERFMON_MAX_LATENCY_ASIZE }, + {.reg = HW_PERFMON_MAX_LATENCY, .name = "TAGID", + .field = BM_PERFMON_MAX_LATENCY_TAGID }, + {.reg = HW_PERFMON_MAX_LATENCY, .name = "Max-Count", + .field = BM_PERFMON_MAX_LATENCY_COUNT } +}; + +static struct mxs_platform_perfmon_data common_perfmon_data = { + .bit_config_tab = common_perfmon_bit_config, + .bit_config_cnt = ARRAY_SIZE(common_perfmon_bit_config), +}; + +struct mxs_perfmon_data { + struct device *dev; + struct mxs_platform_perfmon_data *pdata; + struct mxs_platform_perfmon_data *pdata_common; + int count; + struct attribute_group attr_group; + unsigned int base; + unsigned int initial; + /* attribute ** follow */ + /* device_attribute follow */ +}; + +#define pd_attribute_ptr(x) \ + ((struct attribute **)((x) + 1)) +#define pd_device_attribute_ptr(x) \ + ((struct device_attribute *)(pd_attribute_ptr(x) + (x)->count + 1)) + +static inline u32 perfmon_reg_read(struct mxs_perfmon_data *pdata, + int reg) +{ + return __raw_readl(pdata->base + reg); +} + +static inline void perfmon_reg_write(struct mxs_perfmon_data *pdata, + u32 val, int reg) +{ + __raw_writel(val, pdata->base + reg); +} + +static int get_offset_form_field(int field) +{ + int offset = 0; + + if (!field) + return offset; + + while (!(field & 0x1)) { + field >>= 1; + offset++; + } + + return offset; +} + +static ssize_t +perfmon_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxs_perfmon_data *pd = platform_get_drvdata(pdev); + struct device_attribute *devattr = pd_device_attribute_ptr(pd); + struct mxs_perfmon_bit_config *pb; + int idx; + u32 val; + ssize_t result = 0; + + idx = attr - devattr; + if ((unsigned int)idx >= pd->count) + return -EINVAL; + + if (idx < pd->pdata->bit_config_cnt) { + pb = &pd->pdata->bit_config_tab[idx]; + pb->reg = HW_PERFMON_MASTER_EN; + } else + pb = &pd->pdata_common->bit_config_tab \ + [idx - pd->pdata->bit_config_cnt]; + + if (!pd->initial) { + mxs_reset_block((void *)pd->base, true); + pd->initial = true; + } + + if (!memcmp(pb->name, MONITOR, sizeof(MONITOR))) { + /* cat monitor command, we return monitor status */ + val = perfmon_reg_read(pd, pb->reg); + + if (val & BV_PERFMON_CTRL_RUN__RUN) + result += sprintf(buf, "Run mode\r\n"); + else + result += sprintf(buf, "Stop mode\r\n"); + + if (val & BM_PERFMON_CTRL_READ_EN) + result += \ + sprintf(buf + result, "PM Read Activities\r\n"); + else + result += \ + sprintf(buf + result, "PM Write Activities\r\n"); + + return result; + } + + /* read value and shift */ + val = perfmon_reg_read(pd, pb->reg); + val &= pb->field; + val >>= get_offset_form_field(pb->field); + + return sprintf(buf, "0x%x\n", val); +} + +static ssize_t +perfmon_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxs_perfmon_data *pd = platform_get_drvdata(pdev); + struct device_attribute *devattr = pd_device_attribute_ptr(pd); + struct mxs_perfmon_bit_config *pb; + int idx, r; + unsigned long val, newval; + + idx = attr - devattr; + if ((unsigned int)idx >= pd->count) + return -EINVAL; + + if (!buf) + return -EINVAL; + + if (idx < pd->pdata->bit_config_cnt) { + pb = &pd->pdata->bit_config_tab[idx]; + pb->reg = HW_PERFMON_MASTER_EN; + } else + pb = &pd->pdata_common->bit_config_tab \ + [idx - pd->pdata->bit_config_cnt]; + + if (!pd->initial) { + mxs_reset_block((void *)pd->base, true); + pd->initial = true; + } + + if (!memcmp(pb->name, MONITOR, sizeof(MONITOR))) { + /* it's a cmd */ + int scan, size; + const struct mxs_perfmon_cmd_config *pcfg; + + size = ARRAY_SIZE(common_perfmon_cmd_config); + for (scan = 0; scan < size; scan++) { + pcfg = &common_perfmon_cmd_config[scan]; + if (!memcmp(buf, pcfg->cmd, strlen(pcfg->cmd))) { + val = perfmon_reg_read(pd, HW_PERFMON_CTRL); + val &= ~pcfg->field; + val |= \ + pcfg->val << get_offset_form_field(pcfg->field); + perfmon_reg_write(pd, val, HW_PERFMON_CTRL); + + return count; + } + } + if (scan == ARRAY_SIZE(common_perfmon_cmd_config)) + return -EINVAL; + } + /* get value to write */ + if (buf && (count >= 2) && buf[0] == '0' && buf[1] == 'x') + r = strict_strtoul(buf, 16, &val); + else + r = strict_strtoul(buf, 10, &val); + + if (r != 0) + return r; + + /* verify it fits */ + if ((unsigned int)val > (pb->field >> get_offset_form_field(pb->field))) + return -EINVAL; + + newval = perfmon_reg_read(pd, pb->reg); + newval &= ~pb->field; + newval |= val << get_offset_form_field(pb->field); + perfmon_reg_write(pd, newval, pb->reg); + + return count; +} + + +static int __devinit mxs_perfmon_probe(struct platform_device *pdev) +{ + struct mxs_perfmon_data *pd; + struct mxs_platform_perfmon_data *pdata; + struct mxs_platform_perfmon_data *pdata_common; + struct resource *res; + struct mxs_perfmon_bit_config *pb; + struct attribute **attr; + struct device_attribute *devattr; + int i, cnt, size; + int err; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) + return -ENODEV; + + pdata_common = &common_perfmon_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -ENODEV; + + cnt = pdata->bit_config_cnt + pdata_common->bit_config_cnt; + size = sizeof(*pd) + + (cnt + 1) * sizeof(struct atrribute *) + + cnt * sizeof(struct device_attribute); + pd = kzalloc(size, GFP_KERNEL); + if (pd == NULL) + return -ENOMEM; + pd->dev = &pdev->dev; + pd->pdata = pdata; + pd->pdata_common = pdata_common; + pd->base = (unsigned int)ioremap(res->start, res->end - res->start); + pd->initial = false; + + platform_set_drvdata(pdev, pd); + pd->count = cnt; + attr = pd_attribute_ptr(pd); + devattr = pd_device_attribute_ptr(pd); + + /* build the attributes structures */ + pd->attr_group.attrs = attr; + pb = pdata->bit_config_tab; + for (i = 0; i < pdata->bit_config_cnt; i++) { + devattr[i].attr.name = pb[i].name; + devattr[i].attr.mode = S_IWUSR | S_IRUGO; + devattr[i].show = perfmon_show; + devattr[i].store = perfmon_store; + attr[i] = &devattr[i].attr; + } + pb = pdata_common->bit_config_tab; + for (i = 0; i < pdata_common->bit_config_cnt; i++) { + devattr[i + pdata->bit_config_cnt].attr.name = pb[i].name; + devattr[i + pdata->bit_config_cnt].attr.mode = \ + S_IWUSR | S_IRUGO; + devattr[i + pdata->bit_config_cnt].show = perfmon_show; + devattr[i + pdata->bit_config_cnt].store = perfmon_store; + attr[i + pdata->bit_config_cnt] = \ + &devattr[i + pdata->bit_config_cnt].attr; + } + + err = sysfs_create_group(&pdev->dev.kobj, &pd->attr_group); + if (err != 0) { + platform_set_drvdata(pdev, NULL); + kfree(pd); + return err; + } + + return 0; +} + +static int __devexit mxs_perfmon_remove(struct platform_device *pdev) +{ + struct mxs_perfmon_data *pd; + + pd = platform_get_drvdata(pdev); + sysfs_remove_group(&pdev->dev.kobj, &pd->attr_group); + platform_set_drvdata(pdev, NULL); + kfree(pd); + + return 0; +} + +#ifdef CONFIG_PM +static int +mxs_perfmon_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int mxs_perfmon_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define mxs_perfmon_suspend NULL +#define mxs_perfmon_resume NULL +#endif + +static struct platform_driver mxs_perfmon_driver = { + .probe = mxs_perfmon_probe, + .remove = __exit_p(mxs_perfmon_remove), + .suspend = mxs_perfmon_suspend, + .resume = mxs_perfmon_resume, + .driver = { + .name = "mxs-perfmon", + .owner = THIS_MODULE, + }, +}; + +static int __init mxs_perfmon_init(void) +{ + return platform_driver_register(&mxs_perfmon_driver); +} + +static void __exit mxs_perfmon_exit(void) +{ + platform_driver_unregister(&mxs_perfmon_driver); +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Performance Monitor user-access driver"); +MODULE_LICENSE("GPL"); + +module_init(mxs_perfmon_init); +module_exit(mxs_perfmon_exit); diff --git a/drivers/misc/mxs-persistent.c b/drivers/misc/mxs-persistent.c new file mode 100644 index 000000000000..6acb006489d0 --- /dev/null +++ b/drivers/misc/mxs-persistent.c @@ -0,0 +1,271 @@ +/* + * Freescale STMP378X Persistent bits manipulation driver + * + * Author: Pantelis Antoniou + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct mxs_persistent_data { + struct device *dev; + struct mxs_platform_persistent_data *pdata; + int count; + struct attribute_group attr_group; + unsigned int base; + /* attribute ** follow */ + /* device_attribute follow */ +}; + +#define pd_attribute_ptr(x) \ + ((struct attribute **)((x) + 1)) +#define pd_device_attribute_ptr(x) \ + ((struct device_attribute *)(pd_attribute_ptr(x) + (x)->count + 1)) + +static inline u32 persistent_reg_read(struct mxs_persistent_data *pdata, + int reg) +{ + u32 msk; + + /* wait for stable value */ + msk = BF_RTC_STAT_STALE_REGS((0x1 << reg)); + while (__raw_readl(pdata->base + HW_RTC_STAT) & msk) + cpu_relax(); + + return __raw_readl(pdata->base + 0x60 + (reg * 0x10)); +} + +static inline void persistent_reg_wait_settle(struct mxs_persistent_data *pdata + , int reg) +{ + u32 msk; + + /* wait until the change is propagated */ + msk = BF_RTC_STAT_NEW_REGS((0x1 << reg)); + while (__raw_readl(pdata->base + HW_RTC_STAT) & msk) + cpu_relax(); +} + +static inline void persistent_reg_write(struct mxs_persistent_data *pdata, + u32 val, int reg) +{ + __raw_writel(val, pdata->base + 0x60 + (reg * 0x10)); + persistent_reg_wait_settle(pdata, reg); +} + +static inline void persistent_reg_set(struct mxs_persistent_data *pdata, + u32 val, int reg) +{ + __raw_writel(val, pdata->base + 0x60 + (reg * 0x10) + 0x4); + persistent_reg_wait_settle(pdata, reg); +} + +static inline void persistent_reg_clr(struct mxs_persistent_data *pdata, + u32 val, int reg) +{ + __raw_writel(val, pdata->base + 0x60 + (reg * 0x10) + 0x8); + persistent_reg_wait_settle(pdata, reg); +} + +static inline void persistent_reg_tog(struct mxs_persistent_data *pdata, + u32 val, int reg) +{ + __raw_writel(val, pdata->base + 0x60 + (reg * 0x10) + 0xc); + persistent_reg_wait_settle(pdata, reg); +} + +static ssize_t +persistent_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxs_persistent_data *pd = platform_get_drvdata(pdev); + struct device_attribute *devattr = pd_device_attribute_ptr(pd); + const struct mxs_persistent_bit_config *pb; + int idx; + u32 val; + + idx = attr - devattr; + if ((unsigned int)idx >= pd->count) + return -EINVAL; + + pb = &pd->pdata->bit_config_tab[idx]; + + /* read value and shift */ + val = persistent_reg_read(pd, pb->reg); + val >>= pb->start; + val &= (1 << pb->width) - 1; + + return sprintf(buf, "%u\n", val); +} + +static ssize_t +persistent_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxs_persistent_data *pd = platform_get_drvdata(pdev); + struct device_attribute *devattr = pd_device_attribute_ptr(pd); + const struct mxs_persistent_bit_config *pb; + int idx, r; + unsigned long val, msk; + + idx = attr - devattr; + if ((unsigned int)idx >= pd->count) + return -EINVAL; + + pb = &pd->pdata->bit_config_tab[idx]; + + /* get value to write */ + r = strict_strtoul(buf, 10, &val); + if (r != 0) + return r; + + /* verify it fits */ + if ((unsigned int)val > (1 << pb->width) - 1) + return -EINVAL; + + /* lockless update, first clear the area */ + msk = ((1 << pb->width) - 1) << pb->start; + persistent_reg_clr(pd, msk, pb->reg); + + /* shift into position */ + val <<= pb->start; + persistent_reg_set(pd, val, pb->reg); + + return count; +} + + +static int __devinit mxs_persistent_probe(struct platform_device *pdev) +{ + struct mxs_persistent_data *pd; + struct mxs_platform_persistent_data *pdata; + struct resource *res; + const struct mxs_persistent_bit_config *pb; + struct attribute **attr; + struct device_attribute *devattr; + int i, cnt, size; + int err; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -ENODEV; + + cnt = pdata->bit_config_cnt; + size = sizeof(*pd) + + (cnt + 1) * sizeof(struct atrribute *) + + cnt * sizeof(struct device_attribute); + pd = kzalloc(size, GFP_KERNEL); + if (pd == NULL) + return -ENOMEM; + pd->dev = &pdev->dev; + pd->pdata = pdata; + pd->base = (unsigned int)IO_ADDRESS(res->start); + + platform_set_drvdata(pdev, pd); + pd->count = cnt; + attr = pd_attribute_ptr(pd); + devattr = pd_device_attribute_ptr(pd); + + /* build the attributes structures */ + pd->attr_group.attrs = attr; + pb = pdata->bit_config_tab; + for (i = 0; i < cnt; i++) { + devattr[i].attr.name = pb[i].name; + devattr[i].attr.mode = S_IWUSR | S_IRUGO; + devattr[i].show = persistent_show; + devattr[i].store = persistent_store; + attr[i] = &devattr[i].attr; + } + + err = sysfs_create_group(&pdev->dev.kobj, &pd->attr_group); + if (err != 0) { + platform_set_drvdata(pdev, NULL); + kfree(pd); + return err; + } + + return 0; +} + +static int __devexit mxs_persistent_remove(struct platform_device *pdev) +{ + struct mxs_persistent_data *pd; + + pd = platform_get_drvdata(pdev); + sysfs_remove_group(&pdev->dev.kobj, &pd->attr_group); + platform_set_drvdata(pdev, NULL); + kfree(pd); + + return 0; +} + +#ifdef CONFIG_PM +static int +mxs_persistent_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int mxs_persistent_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define mxs_persistent_suspend NULL +#define mxs_persistent_resume NULL +#endif + +static struct platform_driver mxs_persistent_driver = { + .probe = mxs_persistent_probe, + .remove = __exit_p(mxs_persistent_remove), + .suspend = mxs_persistent_suspend, + .resume = mxs_persistent_resume, + .driver = { + .name = "mxs-persistent", + .owner = THIS_MODULE, + }, +}; + +static int __init mxs_persistent_init(void) +{ + return platform_driver_register(&mxs_persistent_driver); +} + +static void __exit mxs_persistent_exit(void) +{ + platform_driver_unregister(&mxs_persistent_driver); +} + +MODULE_AUTHOR("Pantelis Antoniou "); +MODULE_DESCRIPTION("Persistent bits user-access driver"); +MODULE_LICENSE("GPL"); + +module_init(mxs_persistent_init); +module_exit(mxs_persistent_exit); diff --git a/drivers/misc/pmem.c b/drivers/misc/pmem.c new file mode 100644 index 000000000000..0e1651dfe324 --- /dev/null +++ b/drivers/misc/pmem.c @@ -0,0 +1,1340 @@ +/* drivers/android/pmem.c + * + * Copyright (C) 2007 Google, Inc. + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PMEM_MAX_DEVICES 10 +#define PMEM_MAX_ORDER 128 +#define PMEM_MIN_ALLOC PAGE_SIZE + +#define PMEM_DEBUG 1 + +/* indicates that a refernce to this file has been taken via get_pmem_file, + * the file should not be released until put_pmem_file is called */ +#define PMEM_FLAGS_BUSY 0x1 +/* indicates that this is a suballocation of a larger master range */ +#define PMEM_FLAGS_CONNECTED (0x1 << 1) +/* indicates this is a master and not a sub allocation and that it is mmaped */ +#define PMEM_FLAGS_MASTERMAP (0x1 << 2) +/* submap and unsubmap flags indicate: + * 00: subregion has never been mmaped + * 10: subregion has been mmaped, reference to the mm was taken + * 11: subretion has ben released, refernece to the mm still held + * 01: subretion has been released, reference to the mm has been released + */ +#define PMEM_FLAGS_SUBMAP (0x1 << 3) +#define PMEM_FLAGS_UNSUBMAP (0x1 << 4) + + +struct pmem_data { + /* in alloc mode: an index into the bitmap + * in no_alloc mode: the size of the allocation */ + int index; + /* see flags above for descriptions */ + unsigned int flags; + /* protects this data field, if the mm_mmap sem will be held at the + * same time as this sem, the mm sem must be taken first (as this is + * the order for vma_open and vma_close ops */ + struct rw_semaphore sem; + /* info about the mmaping process */ + struct vm_area_struct *vma; + /* task struct of the mapping process */ + struct task_struct *task; + /* process id of teh mapping process */ + pid_t pid; + /* file descriptor of the master */ + int master_fd; + /* file struct of the master */ + struct file *master_file; + /* a list of currently available regions if this is a suballocation */ + struct list_head region_list; + /* a linked list of data so we can access them for debugging */ + struct list_head list; +#if PMEM_DEBUG + int ref; +#endif +}; + +struct pmem_bits { + unsigned allocated:1; /* 1 if allocated, 0 if free */ + unsigned order:7; /* size of the region in pmem space */ +}; + +struct pmem_region_node { + struct pmem_region region; + struct list_head list; +}; + +#define PMEM_DEBUG_MSGS 0 +#if PMEM_DEBUG_MSGS +#define DLOG(fmt, args...) \ + do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \ + ##args); } \ + while (0) +#else +#define DLOG(x...) do {} while (0) +#endif + +struct pmem_info { + struct miscdevice dev; + /* physical start address of the remaped pmem space */ + unsigned long base; + /* vitual start address of the remaped pmem space */ + unsigned char __iomem *vbase; + /* total size of the pmem space */ + unsigned long size; + /* number of entries in the pmem space */ + unsigned long num_entries; + /* pfn of the garbage page in memory */ + unsigned long garbage_pfn; + /* index of the garbage page in the pmem space */ + int garbage_index; + /* the bitmap for the region indicating which entries are allocated + * and which are free */ + struct pmem_bits *bitmap; + /* indicates the region should not be managed with an allocator */ + unsigned no_allocator; + /* indicates maps of this region should be cached, if a mix of + * cached and uncached is desired, set this and open the device with + * O_SYNC to get an uncached region */ + unsigned cached; + unsigned buffered; + /* in no_allocator mode the first mapper gets the whole space and sets + * this flag */ + unsigned allocated; + /* for debugging, creates a list of pmem file structs, the + * data_list_sem should be taken before pmem_data->sem if both are + * needed */ + struct semaphore data_list_sem; + struct list_head data_list; + /* pmem_sem protects the bitmap array + * a write lock should be held when modifying entries in bitmap + * a read lock should be held when reading data from bits or + * dereferencing a pointer into bitmap + * + * pmem_data->sem protects the pmem data of a particular file + * Many of the function that require the pmem_data->sem have a non- + * locking version for when the caller is already holding that sem. + * + * IF YOU TAKE BOTH LOCKS TAKE THEM IN THIS ORDER: + * down(pmem_data->sem) => down(bitmap_sem) + */ + struct rw_semaphore bitmap_sem; + + long (*ioctl)(struct file *, unsigned int, unsigned long); + int (*release)(struct inode *, struct file *); +}; + +static struct pmem_info pmem[PMEM_MAX_DEVICES]; +static int id_count; + +#define PMEM_IS_FREE(id, index) (!(pmem[id].bitmap[index].allocated)) +#define PMEM_ORDER(id, index) pmem[id].bitmap[index].order +#define PMEM_BUDDY_INDEX(id, index) (index ^ (1 << PMEM_ORDER(id, index))) +#define PMEM_NEXT_INDEX(id, index) (index + (1 << PMEM_ORDER(id, index))) +#define PMEM_OFFSET(index) (index * PMEM_MIN_ALLOC) +#define PMEM_START_ADDR(id, index) (PMEM_OFFSET(index) + pmem[id].base) +#define PMEM_LEN(id, index) ((1 << PMEM_ORDER(id, index)) * PMEM_MIN_ALLOC) +#define PMEM_END_ADDR(id, index) (PMEM_START_ADDR(id, index) + \ + PMEM_LEN(id, index)) +#define PMEM_START_VADDR(id, index) (PMEM_OFFSET(id, index) + pmem[id].vbase) +#define PMEM_END_VADDR(id, index) (PMEM_START_VADDR(id, index) + \ + PMEM_LEN(id, index)) +#define PMEM_REVOKED(data) (data->flags & PMEM_FLAGS_REVOKED) +#define PMEM_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK))) +#define PMEM_IS_SUBMAP(data) ((data->flags & PMEM_FLAGS_SUBMAP) && \ + (!(data->flags & PMEM_FLAGS_UNSUBMAP))) + +static int pmem_release(struct inode *, struct file *); +static int pmem_mmap(struct file *, struct vm_area_struct *); +static int pmem_open(struct inode *, struct file *); +static long pmem_ioctl(struct file *, unsigned int, unsigned long); + +struct file_operations pmem_fops = { + .release = pmem_release, + .mmap = pmem_mmap, + .open = pmem_open, + .unlocked_ioctl = pmem_ioctl, +}; + +static int get_id(struct file *file) +{ + return MINOR(file->f_dentry->d_inode->i_rdev); +} + +int is_pmem_file(struct file *file) +{ + int id; + + if (unlikely(!file || !file->f_dentry || !file->f_dentry->d_inode)) + return 0; + id = get_id(file); + if (unlikely(id >= PMEM_MAX_DEVICES)) + return 0; + if (unlikely(file->f_dentry->d_inode->i_rdev != + MKDEV(MISC_MAJOR, pmem[id].dev.minor))) + return 0; + return 1; +} + +static int has_allocation(struct file *file) +{ + struct pmem_data *data; + /* check is_pmem_file first if not accessed via pmem_file_ops */ + + if (unlikely(!file->private_data)) + return 0; + data = (struct pmem_data *)file->private_data; + if (unlikely(data->index < 0)) + return 0; + return 1; +} + +static int is_master_owner(struct file *file) +{ + struct file *master_file; + struct pmem_data *data; + int put_needed, ret = 0; + + if (!is_pmem_file(file) || !has_allocation(file)) + return 0; + data = (struct pmem_data *)file->private_data; + if (PMEM_FLAGS_MASTERMAP & data->flags) + return 1; + master_file = fget_light(data->master_fd, &put_needed); + if (master_file && data->master_file == master_file) + ret = 1; + fput_light(master_file, put_needed); + return ret; +} + +static int pmem_free(int id, int index) +{ + /* caller should hold the write lock on pmem_sem! */ + int buddy, curr = index; + DLOG("index %d\n", index); + + if (pmem[id].no_allocator) { + pmem[id].allocated = 0; + return 0; + } + /* clean up the bitmap, merging any buddies */ + pmem[id].bitmap[curr].allocated = 0; + /* find a slots buddy Buddy# = Slot# ^ (1 << order) + * if the buddy is also free merge them + * repeat until the buddy is not free or end of the bitmap is reached + */ + do { + buddy = PMEM_BUDDY_INDEX(id, curr); + if (PMEM_IS_FREE(id, buddy) && + PMEM_ORDER(id, buddy) == PMEM_ORDER(id, curr)) { + PMEM_ORDER(id, buddy)++; + PMEM_ORDER(id, curr)++; + curr = min(buddy, curr); + } else { + break; + } + } while (curr < pmem[id].num_entries); + + return 0; +} + +static void pmem_revoke(struct file *file, struct pmem_data *data); + +static int pmem_release(struct inode *inode, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + struct pmem_region_node *region_node; + struct list_head *elt, *elt2; + int id = get_id(file), ret = 0; + + + down(&pmem[id].data_list_sem); + /* if this file is a master, revoke all the memory in the connected + * files */ + if (PMEM_FLAGS_MASTERMAP & data->flags) { + struct pmem_data *sub_data; + list_for_each(elt, &pmem[id].data_list) { + sub_data = list_entry(elt, struct pmem_data, list); + down_read(&sub_data->sem); + if (PMEM_IS_SUBMAP(sub_data) && + file == sub_data->master_file) { + up_read(&sub_data->sem); + pmem_revoke(file, sub_data); + } else + up_read(&sub_data->sem); + } + } + list_del(&data->list); + up(&pmem[id].data_list_sem); + + + down_write(&data->sem); + + /* if its not a conencted file and it has an allocation, free it */ + if (!(PMEM_FLAGS_CONNECTED & data->flags) && has_allocation(file)) { + down_write(&pmem[id].bitmap_sem); + ret = pmem_free(id, data->index); + up_write(&pmem[id].bitmap_sem); + } + + /* if this file is a submap (mapped, connected file), downref the + * task struct */ + if (PMEM_FLAGS_SUBMAP & data->flags) + if (data->task) { + put_task_struct(data->task); + data->task = NULL; + } + + file->private_data = NULL; + + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, list); + list_del(elt); + kfree(region_node); + } + BUG_ON(!list_empty(&data->region_list)); + + up_write(&data->sem); + kfree(data); + if (pmem[id].release) + ret = pmem[id].release(inode, file); + + return ret; +} + +static int pmem_open(struct inode *inode, struct file *file) +{ + struct pmem_data *data; + int id = get_id(file); + int ret = 0; + + DLOG("current %u file %p(%d)\n", current->pid, file, file_count(file)); + /* setup file->private_data to indicate its unmapped */ + /* you can only open a pmem device one time */ + if (file->private_data != &pmem[id].dev && + file->private_data != NULL) { + return -1; + } + data = kmalloc(sizeof(struct pmem_data), GFP_KERNEL); + if (!data) { + printk("pmem: unable to allocate memory for pmem metadata."); + return -1; + } + data->flags = 0; + data->index = -1; + data->task = NULL; + data->vma = NULL; + data->pid = 0; + data->master_file = NULL; +#if PMEM_DEBUG + data->ref = 0; +#endif + INIT_LIST_HEAD(&data->region_list); + init_rwsem(&data->sem); + + file->private_data = data; + INIT_LIST_HEAD(&data->list); + + down(&pmem[id].data_list_sem); + list_add(&data->list, &pmem[id].data_list); + up(&pmem[id].data_list_sem); + return ret; +} + +static unsigned long pmem_order(unsigned long len) +{ + int i; + + len = (len + PMEM_MIN_ALLOC - 1)/PMEM_MIN_ALLOC; + len--; + for (i = 0; i < sizeof(len)*8; i++) + if (len >> i == 0) + break; + return i; +} + +static int pmem_allocate(int id, unsigned long len) +{ + /* caller should hold the write lock on pmem_sem! */ + /* return the corresponding pdata[] entry */ + int curr = 0; + int end = pmem[id].num_entries; + int best_fit = -1; + unsigned long order = pmem_order(len); + + if (pmem[id].no_allocator) { + DLOG("no allocator"); + if ((len > pmem[id].size) || pmem[id].allocated) + return -1; + pmem[id].allocated = 1; + return len; + } + + if (order > PMEM_MAX_ORDER) + return -1; + DLOG("order %lx\n", order); + + /* look through the bitmap: + * if you find a free slot of the correct order use it + * otherwise, use the best fit (smallest with size > order) slot + */ + while (curr < end) { + if (PMEM_IS_FREE(id, curr)) { + if (PMEM_ORDER(id, curr) == (unsigned char)order) { + /* set the not free bit and clear others */ + best_fit = curr; + break; + } + if (PMEM_ORDER(id, curr) > (unsigned char)order && + (best_fit < 0 || + PMEM_ORDER(id, curr) < PMEM_ORDER(id, best_fit))) + best_fit = curr; + } + curr = PMEM_NEXT_INDEX(id, curr); + } + + /* if best_fit < 0, there are no suitable slots, + * return an error + */ + if (best_fit < 0) { + printk("pmem: no space left to allocate!\n"); + return -1; + } + + /* now partition the best fit: + * split the slot into 2 buddies of order - 1 + * repeat until the slot is of the correct order + */ + while (PMEM_ORDER(id, best_fit) > (unsigned char)order) { + int buddy; + PMEM_ORDER(id, best_fit) -= 1; + buddy = PMEM_BUDDY_INDEX(id, best_fit); + PMEM_ORDER(id, buddy) = PMEM_ORDER(id, best_fit); + } + pmem[id].bitmap[best_fit].allocated = 1; + return best_fit; +} + +static pgprot_t phys_mem_access_prot(struct file *file, pgprot_t vma_prot) +{ + int id = get_id(file); + +#ifdef pgprot_writecombine + if (pmem[id].cached == 0 || file->f_flags & O_SYNC) + return pgprot_writecombine(vma_prot); +#endif + +#ifdef pgprot_ext_buffered + else if (pmem[id].buffered) + return pgprot_ext_buffered(vma_prot); +#endif + return vma_prot; +} + +static unsigned long pmem_start_addr(int id, struct pmem_data *data) +{ + if (pmem[id].no_allocator) + return PMEM_START_ADDR(id, 0); + else + return PMEM_START_ADDR(id, data->index); + +} + +static void *pmem_start_vaddr(int id, struct pmem_data *data) +{ + return pmem_start_addr(id, data) - pmem[id].base + pmem[id].vbase; +} + +static unsigned long pmem_len(int id, struct pmem_data *data) +{ + if (pmem[id].no_allocator) + return data->index; + else + return PMEM_LEN(id, data->index); +} + +static int pmem_map_garbage(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + int i, garbage_pages = len >> PAGE_SHIFT; + + vma->vm_flags |= VM_IO | VM_RESERVED | VM_PFNMAP | VM_SHARED | VM_WRITE; + for (i = 0; i < garbage_pages; i++) { + if (vm_insert_pfn(vma, vma->vm_start + offset + (i * PAGE_SIZE), + pmem[id].garbage_pfn)) + return -EAGAIN; + } + return 0; +} + +static int pmem_unmap_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + int garbage_pages; + DLOG("unmap offset %lx len %lx\n", offset, len); + + BUG_ON(!PMEM_IS_PAGE_ALIGNED(len)); + + garbage_pages = len >> PAGE_SHIFT; + zap_page_range(vma, vma->vm_start + offset, len, NULL); + pmem_map_garbage(id, vma, data, offset, len); + return 0; +} + +static int pmem_map_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + DLOG("map offset %lx len %lx\n", offset, len); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_start)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_end)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(len)); + BUG_ON(!PMEM_IS_PAGE_ALIGNED(offset)); + + if (io_remap_pfn_range(vma, vma->vm_start + offset, + (pmem_start_addr(id, data) + offset) >> PAGE_SHIFT, + len, vma->vm_page_prot)) { + return -EAGAIN; + } + return 0; +} + +static int pmem_remap_pfn_range(int id, struct vm_area_struct *vma, + struct pmem_data *data, unsigned long offset, + unsigned long len) +{ + /* hold the mm semp for the vma you are modifying when you call this */ + BUG_ON(!vma); + zap_page_range(vma, vma->vm_start + offset, len, NULL); + return pmem_map_pfn_range(id, vma, data, offset, len); +} + +static void pmem_vma_open(struct vm_area_struct *vma) +{ + struct file *file = vma->vm_file; + struct pmem_data *data = file->private_data; + int id = get_id(file); + /* this should never be called as we don't support copying pmem + * ranges via fork */ + BUG_ON(!has_allocation(file)); + down_write(&data->sem); + /* remap the garbage pages, forkers don't get access to the data */ + pmem_unmap_pfn_range(id, vma, data, 0, vma->vm_start - vma->vm_end); + up_write(&data->sem); +} + +static void pmem_vma_close(struct vm_area_struct *vma) +{ + struct file *file = vma->vm_file; + struct pmem_data *data = file->private_data; + + DLOG("current %u ppid %u file %p count %d\n", current->pid, + current->parent->pid, file, file_count(file)); + if (unlikely(!is_pmem_file(file) || !has_allocation(file))) { + printk(KERN_WARNING "pmem: something is very wrong, you are " + "closing a vm backing an allocation that doesn't " + "exist!\n"); + return; + } + down_write(&data->sem); + if (data->vma == vma) { + data->vma = NULL; + if ((data->flags & PMEM_FLAGS_CONNECTED) && + (data->flags & PMEM_FLAGS_SUBMAP)) + data->flags |= PMEM_FLAGS_UNSUBMAP; + } + /* the kernel is going to free this vma now anyway */ + up_write(&data->sem); +} + +static struct vm_operations_struct vm_ops = { + .open = pmem_vma_open, + .close = pmem_vma_close, +}; + +static int pmem_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct pmem_data *data; + int index; + unsigned long vma_size = vma->vm_end - vma->vm_start; + int ret = 0, id = get_id(file); + + if (vma->vm_pgoff || !PMEM_IS_PAGE_ALIGNED(vma_size)) { +#if PMEM_DEBUG + printk(KERN_ERR "pmem: mmaps must be at offset zero, aligned" + " and a multiple of pages_size.\n"); +#endif + return -EINVAL; + } + + data = (struct pmem_data *)file->private_data; + down_write(&data->sem); + /* check this file isn't already mmaped, for submaps check this file + * has never been mmaped */ + if ((data->flags & PMEM_FLAGS_SUBMAP) || + (data->flags & PMEM_FLAGS_UNSUBMAP)) { +#if PMEM_DEBUG + printk(KERN_ERR "pmem: you can only mmap a pmem file once, " + "this file is already mmaped. %x\n", data->flags); +#endif + ret = -EINVAL; + goto error; + } + /* if file->private_data == unalloced, alloc*/ + if (data && data->index == -1) { + down_write(&pmem[id].bitmap_sem); + index = pmem_allocate(id, vma->vm_end - vma->vm_start); + up_write(&pmem[id].bitmap_sem); + data->index = index; + } + /* either no space was available or an error occured */ + if (!has_allocation(file)) { + ret = -EINVAL; + printk("pmem: could not find allocation for map.\n"); + goto error; + } + + if (pmem_len(id, data) < vma_size) { +#if PMEM_DEBUG + printk(KERN_WARNING "pmem: mmap size [%lu] does not match" + "size of backing region [%lu].\n", vma_size, + pmem_len(id, data)); +#endif + ret = -EINVAL; + goto error; + } + + vma->vm_pgoff = pmem_start_addr(id, data) >> PAGE_SHIFT; + vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_page_prot); + + if (data->flags & PMEM_FLAGS_CONNECTED) { + struct pmem_region_node *region_node; + struct list_head *elt; + if (pmem_map_garbage(id, vma, data, 0, vma_size)) { + printk("pmem: mmap failed in kernel!\n"); + ret = -EAGAIN; + goto error; + } + list_for_each(elt, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + DLOG("remapping file: %p %lx %lx\n", file, + region_node->region.offset, + region_node->region.len); + if (pmem_remap_pfn_range(id, vma, data, + region_node->region.offset, + region_node->region.len)) { + ret = -EAGAIN; + goto error; + } + } + data->flags |= PMEM_FLAGS_SUBMAP; + get_task_struct(current->group_leader); + data->task = current->group_leader; + data->vma = vma; +#if PMEM_DEBUG + data->pid = current->pid; +#endif + DLOG("submmapped file %p vma %p pid %u\n", file, vma, + current->pid); + } else { + if (pmem_map_pfn_range(id, vma, data, 0, vma_size)) { + printk(KERN_INFO "pmem: mmap failed in kernel!\n"); + ret = -EAGAIN; + goto error; + } + data->flags |= PMEM_FLAGS_MASTERMAP; + data->pid = current->pid; + } + vma->vm_ops = &vm_ops; +error: + up_write(&data->sem); + return ret; +} + +/* the following are the api for accessing pmem regions by other drivers + * from inside the kernel */ +int get_pmem_user_addr(struct file *file, unsigned long *start, + unsigned long *len) +{ + struct pmem_data *data; + if (!is_pmem_file(file) || !has_allocation(file)) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: requested pmem data from invalid" + "file.\n"); +#endif + return -1; + } + data = (struct pmem_data *)file->private_data; + down_read(&data->sem); + if (data->vma) { + *start = data->vma->vm_start; + *len = data->vma->vm_end - data->vma->vm_start; + } else { + *start = 0; + *len = 0; + } + up_read(&data->sem); + return 0; +} + +int get_pmem_addr(struct file *file, unsigned long *start, + unsigned long *vstart, unsigned long *len) +{ + struct pmem_data *data; + int id; + + if (!is_pmem_file(file) || !has_allocation(file)) + return -1; + + data = (struct pmem_data *)file->private_data; + if (data->index == -1) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: requested pmem data from file with no " + "allocation.\n"); + return -1; +#endif + } + id = get_id(file); + + down_read(&data->sem); + *start = pmem_start_addr(id, data); + *len = pmem_len(id, data); + *vstart = (unsigned long)pmem_start_vaddr(id, data); + up_read(&data->sem); +#if PMEM_DEBUG + down_write(&data->sem); + data->ref++; + up_write(&data->sem); +#endif + return 0; +} + +int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart, + unsigned long *len, struct file **filp) +{ + struct file *file; + + file = fget(fd); + if (unlikely(file == NULL)) { + printk(KERN_INFO "pmem: requested data from file descriptor " + "that doesn't exist."); + return -1; + } + + if (get_pmem_addr(file, start, vstart, len)) + goto end; + + if (filp) + *filp = file; + return 0; +end: + fput(file); + return -1; +} + +void put_pmem_file(struct file *file) +{ + struct pmem_data *data; + int id; + + if (!is_pmem_file(file)) + return; + id = get_id(file); + data = (struct pmem_data *)file->private_data; +#if PMEM_DEBUG + down_write(&data->sem); + if (data->ref == 0) { + printk("pmem: pmem_put > pmem_get %s (pid %d)\n", + pmem[id].dev.name, data->pid); + BUG(); + } + data->ref--; + up_write(&data->sem); +#endif + fput(file); +} + +void flush_pmem_file(struct file *file, unsigned long offset, unsigned long len) +{ + struct pmem_data *data; + int id; + void *vaddr; + struct pmem_region_node *region_node; + struct list_head *elt; + void *flush_start, *flush_end; + + if (!is_pmem_file(file) || !has_allocation(file)) + return; + + id = get_id(file); + data = (struct pmem_data *)file->private_data; + if (!pmem[id].cached || file->f_flags & O_SYNC) + return; + + down_read(&data->sem); + vaddr = pmem_start_vaddr(id, data); + /* if this isn't a submmapped file, flush the whole thing */ + if (unlikely(!(data->flags & PMEM_FLAGS_CONNECTED))) { + dmac_flush_range(vaddr, vaddr + pmem_len(id, data)); + goto end; + } + /* otherwise, flush the region of the file we are drawing */ + list_for_each(elt, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, list); + if ((offset >= region_node->region.offset) && + ((offset + len) <= (region_node->region.offset + + region_node->region.len))) { + flush_start = vaddr + region_node->region.offset; + flush_end = flush_start + region_node->region.len; + dmac_flush_range(flush_start, flush_end); + break; + } + } +end: + up_read(&data->sem); +} + +static int pmem_connect(unsigned long connect, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + struct pmem_data *src_data; + struct file *src_file; + int ret = 0, put_needed; + + down_write(&data->sem); + /* retrieve the src file and check it is a pmem file with an alloc */ + src_file = fget_light(connect, &put_needed); + DLOG("connect %p to %p\n", file, src_file); + if (!src_file) { + printk("pmem: src file not found!\n"); + ret = -EINVAL; + goto err_no_file; + } + if (unlikely(!is_pmem_file(src_file) || !has_allocation(src_file))) { + printk(KERN_INFO "pmem: src file is not a pmem file or has no " + "alloc!\n"); + ret = -EINVAL; + goto err_bad_file; + } + src_data = (struct pmem_data *)src_file->private_data; + + if (has_allocation(file) && (data->index != src_data->index)) { + printk("pmem: file is already mapped but doesn't match this" + " src_file!\n"); + ret = -EINVAL; + goto err_bad_file; + } + data->index = src_data->index; + data->flags |= PMEM_FLAGS_CONNECTED; + data->master_fd = connect; + data->master_file = src_file; + +err_bad_file: + fput_light(src_file, put_needed); +err_no_file: + up_write(&data->sem); + return ret; +} + +static void pmem_unlock_data_and_mm(struct pmem_data *data, + struct mm_struct *mm) +{ + up_write(&data->sem); + if (mm != NULL) { + up_write(&mm->mmap_sem); + mmput(mm); + } +} + +static int pmem_lock_data_and_mm(struct file *file, struct pmem_data *data, + struct mm_struct **locked_mm) +{ + int ret = 0; + struct mm_struct *mm = NULL; + *locked_mm = NULL; +lock_mm: + down_read(&data->sem); + if (PMEM_IS_SUBMAP(data)) { + mm = get_task_mm(data->task); + if (!mm) { +#if PMEM_DEBUG + printk("pmem: can't remap task is gone!\n"); +#endif + up_read(&data->sem); + return -1; + } + } + up_read(&data->sem); + + if (mm) + down_write(&mm->mmap_sem); + + down_write(&data->sem); + /* check that the file didn't get mmaped before we could take the + * data sem, this should be safe b/c you can only submap each file + * once */ + if (PMEM_IS_SUBMAP(data) && !mm) { + pmem_unlock_data_and_mm(data, mm); + goto lock_mm; + } + /* now check that vma.mm is still there, it could have been + * deleted by vma_close before we could get the data->sem */ + if ((data->flags & PMEM_FLAGS_UNSUBMAP) && (mm != NULL)) { + /* might as well release this */ + if (data->flags & PMEM_FLAGS_SUBMAP) { + put_task_struct(data->task); + data->task = NULL; + /* lower the submap flag to show the mm is gone */ + data->flags &= ~(PMEM_FLAGS_SUBMAP); + } + pmem_unlock_data_and_mm(data, mm); + return -1; + } + *locked_mm = mm; + return ret; +} + +int pmem_remap(struct pmem_region *region, struct file *file, + unsigned operation) +{ + int ret; + struct pmem_region_node *region_node; + struct mm_struct *mm = NULL; + struct list_head *elt, *elt2; + int id = get_id(file); + struct pmem_data *data = (struct pmem_data *)file->private_data; + + /* pmem region must be aligned on a page boundry */ + if (unlikely(!PMEM_IS_PAGE_ALIGNED(region->offset) || + !PMEM_IS_PAGE_ALIGNED(region->len))) { +#if PMEM_DEBUG + printk("pmem: request for unaligned pmem suballocation " + "%lx %lx\n", region->offset, region->len); +#endif + return -EINVAL; + } + + /* if userspace requests a region of len 0, there's nothing to do */ + if (region->len == 0) + return 0; + + /* lock the mm and data */ + ret = pmem_lock_data_and_mm(file, data, &mm); + if (ret) + return 0; + + /* only the owner of the master file can remap the client fds + * that back in it */ + if (!is_master_owner(file)) { +#if PMEM_DEBUG + printk("pmem: remap requested from non-master process\n"); +#endif + ret = -EINVAL; + goto err; + } + + /* check that the requested range is within the src allocation */ + if (unlikely((region->offset > pmem_len(id, data)) || + (region->len > pmem_len(id, data)) || + (region->offset + region->len > pmem_len(id, data)))) { +#if PMEM_DEBUG + printk(KERN_INFO "pmem: suballoc doesn't fit in src_file!\n"); +#endif + ret = -EINVAL; + goto err; + } + + if (operation == PMEM_MAP) { + region_node = kmalloc(sizeof(struct pmem_region_node), + GFP_KERNEL); + if (!region_node) { + ret = -ENOMEM; +#if PMEM_DEBUG + printk(KERN_INFO "No space to allocate metadata!"); +#endif + goto err; + } + region_node->region = *region; + list_add(®ion_node->list, &data->region_list); + } else if (operation == PMEM_UNMAP) { + int found = 0; + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + if (region->len == 0 || + (region_node->region.offset == region->offset && + region_node->region.len == region->len)) { + list_del(elt); + kfree(region_node); + found = 1; + } + } + if (!found) { +#if PMEM_DEBUG + printk("pmem: Unmap region does not map any mapped " + "region!"); +#endif + ret = -EINVAL; + goto err; + } + } + + if (data->vma && PMEM_IS_SUBMAP(data)) { + if (operation == PMEM_MAP) + ret = pmem_remap_pfn_range(id, data->vma, data, + region->offset, region->len); + else if (operation == PMEM_UNMAP) + ret = pmem_unmap_pfn_range(id, data->vma, data, + region->offset, region->len); + } + +err: + pmem_unlock_data_and_mm(data, mm); + return ret; +} + +static void pmem_revoke(struct file *file, struct pmem_data *data) +{ + struct pmem_region_node *region_node; + struct list_head *elt, *elt2; + struct mm_struct *mm = NULL; + int id = get_id(file); + int ret = 0; + + data->master_file = NULL; + ret = pmem_lock_data_and_mm(file, data, &mm); + /* if lock_data_and_mm fails either the task that mapped the fd, or + * the vma that mapped it have already gone away, nothing more + * needs to be done */ + if (ret) + return; + /* unmap everything */ + /* delete the regions and region list nothing is mapped any more */ + if (data->vma) + list_for_each_safe(elt, elt2, &data->region_list) { + region_node = list_entry(elt, struct pmem_region_node, + list); + pmem_unmap_pfn_range(id, data->vma, data, + region_node->region.offset, + region_node->region.len); + list_del(elt); + kfree(region_node); + } + /* delete the master file */ + pmem_unlock_data_and_mm(data, mm); +} + +static void pmem_get_size(struct pmem_region *region, struct file *file) +{ + struct pmem_data *data = (struct pmem_data *)file->private_data; + int id = get_id(file); + + if (!has_allocation(file)) { + region->offset = 0; + region->len = 0; + return; + } else { + region->offset = pmem_start_addr(id, data); + region->len = pmem_len(id, data); + } + DLOG("offset %lx len %lx\n", region->offset, region->len); +} + + +static long pmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct pmem_data *data; + int id = get_id(file); + + switch (cmd) { + case PMEM_GET_PHYS: + { + struct pmem_region region; + DLOG("get_phys\n"); + if (!has_allocation(file)) { + region.offset = 0; + region.len = 0; + } else { + data = (struct pmem_data *)file->private_data; + region.offset = pmem_start_addr(id, data); + region.len = pmem_len(id, data); + } + printk(KERN_INFO + "pmem: request for physical address of pmem region " + "from process %d.\n", current->pid); + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_MAP: + { + struct pmem_region region; + if (copy_from_user(®ion, (void __user *)arg, + sizeof(struct pmem_region))) + return -EFAULT; + data = (struct pmem_data *)file->private_data; + return pmem_remap(®ion, file, PMEM_MAP); + } + break; + case PMEM_UNMAP: + { + struct pmem_region region; + if (copy_from_user(®ion, (void __user *)arg, + sizeof(struct pmem_region))) + return -EFAULT; + data = (struct pmem_data *)file->private_data; + return pmem_remap(®ion, file, PMEM_UNMAP); + break; + } + case PMEM_GET_SIZE: + { + struct pmem_region region; + DLOG("get_size\n"); + pmem_get_size(®ion, file); + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_GET_TOTAL_SIZE: + { + struct pmem_region region; + DLOG("get total size\n"); + region.offset = 0; + get_id(file); + region.len = pmem[id].size; + if (copy_to_user((void __user *)arg, ®ion, + sizeof(struct pmem_region))) + return -EFAULT; + break; + } + case PMEM_ALLOCATE: + { + if (has_allocation(file)) + return -EINVAL; + data = (struct pmem_data *)file->private_data; + data->index = pmem_allocate(id, arg); + break; + } + case PMEM_CONNECT: + DLOG("connect\n"); + return pmem_connect(arg, file); + break; + case PMEM_CACHE_FLUSH: + { + struct pmem_region region; + DLOG("flush\n"); + if (copy_from_user(®ion, (void __user *)arg, + sizeof(struct pmem_region))) + return -EFAULT; + flush_pmem_file(file, region.offset, region.len); + break; + } + default: + if (pmem[id].ioctl) + return pmem[id].ioctl(file, cmd, arg); + return -EINVAL; + } + return 0; +} + +#if PMEM_DEBUG +static ssize_t debug_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t debug_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct list_head *elt, *elt2; + struct pmem_data *data; + struct pmem_region_node *region_node; + int id = (int)file->private_data; + const int debug_bufmax = 4096; + static char buffer[4096]; + int n = 0; + + DLOG("debug open\n"); + n = scnprintf(buffer, debug_bufmax, + "pid #: mapped regions (offset, len) (offset,len)...\n"); + + down(&pmem[id].data_list_sem); + list_for_each(elt, &pmem[id].data_list) { + data = list_entry(elt, struct pmem_data, list); + down_read(&data->sem); + n += scnprintf(buffer + n, debug_bufmax - n, "pid %u:", + data->pid); + list_for_each(elt2, &data->region_list) { + region_node = list_entry(elt2, struct pmem_region_node, + list); + n += scnprintf(buffer + n, debug_bufmax - n, + "(%lx,%lx) ", + region_node->region.offset, + region_node->region.len); + } + n += scnprintf(buffer + n, debug_bufmax - n, "\n"); + up_read(&data->sem); + } + up(&pmem[id].data_list_sem); + + n++; + buffer[n] = 0; + return simple_read_from_buffer(buf, count, ppos, buffer, n); +} + +static struct file_operations debug_fops = { + .read = debug_read, + .open = debug_open, +}; +#endif + +int pmem_setup(struct android_pmem_platform_data *pdata, + long (*ioctl)(struct file *, unsigned int, unsigned long), + int (*release)(struct inode *, struct file *)) +{ + int err = 0; + int i, index = 0; + int id = id_count; + id_count++; + + pmem[id].no_allocator = pdata->no_allocator; + pmem[id].cached = pdata->cached; + pmem[id].buffered = pdata->buffered; + pmem[id].base = pdata->start; + pmem[id].size = pdata->size; + pmem[id].ioctl = ioctl; + pmem[id].release = release; + init_rwsem(&pmem[id].bitmap_sem); + init_MUTEX(&pmem[id].data_list_sem); + INIT_LIST_HEAD(&pmem[id].data_list); + pmem[id].dev.name = pdata->name; + pmem[id].dev.minor = id; + pmem[id].dev.fops = &pmem_fops; + printk(KERN_INFO "%s: %d init\n", pdata->name, pdata->cached); + + err = misc_register(&pmem[id].dev); + if (err) { + printk(KERN_ALERT "Unable to register pmem driver!\n"); + goto err_cant_register_device; + } + pmem[id].num_entries = pmem[id].size / PMEM_MIN_ALLOC; + + pmem[id].bitmap = kmalloc(pmem[id].num_entries * + sizeof(struct pmem_bits), GFP_KERNEL); + if (!pmem[id].bitmap) + goto err_no_mem_for_metadata; + + memset(pmem[id].bitmap, 0, sizeof(struct pmem_bits) * + pmem[id].num_entries); + + for (i = sizeof(pmem[id].num_entries) * 8 - 1; i >= 0; i--) { + if ((pmem[id].num_entries) & 1<name, S_IFREG | S_IRUGO, NULL, (void *)id, + &debug_fops); +#endif + return 0; +error_cant_remap: + kfree(pmem[id].bitmap); +err_no_mem_for_metadata: + misc_deregister(&pmem[id].dev); +err_cant_register_device: + return -1; +} + +static int pmem_probe(struct platform_device *pdev) +{ + struct android_pmem_platform_data *pdata; + + if (!pdev || !pdev->dev.platform_data) { + printk(KERN_ALERT "Unable to probe pmem!\n"); + return -1; + } + pdata = pdev->dev.platform_data; + return pmem_setup(pdata, NULL, NULL); +} + + +static int pmem_remove(struct platform_device *pdev) +{ + int id = pdev->id; + __free_page(pfn_to_page(pmem[id].garbage_pfn)); + misc_deregister(&pmem[id].dev); + return 0; +} + +static struct platform_driver pmem_driver = { + .probe = pmem_probe, + .remove = pmem_remove, + .driver = { .name = "android_pmem" } +}; + + +static int __init pmem_init(void) +{ + return platform_driver_register(&pmem_driver); +} + +static void __exit pmem_exit(void) +{ + platform_driver_unregister(&pmem_driver); +} + +module_init(pmem_init); +module_exit(pmem_exit); + diff --git a/drivers/misc/regs-perfmon.h b/drivers/misc/regs-perfmon.h new file mode 100644 index 000000000000..2f12885b3baf --- /dev/null +++ b/drivers/misc/regs-perfmon.h @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.36 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___PERFMON_H +#define __ARCH_ARM___PERFMON_H + + +#define HW_PERFMON_CTRL (0x00000000) +#define HW_PERFMON_CTRL_SET (0x00000004) +#define HW_PERFMON_CTRL_CLR (0x00000008) +#define HW_PERFMON_CTRL_TOG (0x0000000c) + +#define BM_PERFMON_CTRL_SFTRST 0x80000000 +#define BV_PERFMON_CTRL_SFTRST__RUN 0x0 +#define BV_PERFMON_CTRL_SFTRST__RESET 0x1 +#define BM_PERFMON_CTRL_CLKGATE 0x40000000 +#define BV_PERFMON_CTRL_CLKGATE__RUN 0x0 +#define BV_PERFMON_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_PERFMON_CTRL_RSVD2 24 +#define BM_PERFMON_CTRL_RSVD2 0x3F000000 +#define BF_PERFMON_CTRL_RSVD2(v) \ + (((v) << 24) & BM_PERFMON_CTRL_RSVD2) +#define BP_PERFMON_CTRL_IRQ_MID 16 +#define BM_PERFMON_CTRL_IRQ_MID 0x00FF0000 +#define BF_PERFMON_CTRL_IRQ_MID(v) \ + (((v) << 16) & BM_PERFMON_CTRL_IRQ_MID) +#define BP_PERFMON_CTRL_RSVD1 13 +#define BM_PERFMON_CTRL_RSVD1 0x0000E000 +#define BF_PERFMON_CTRL_RSVD1(v) \ + (((v) << 13) & BM_PERFMON_CTRL_RSVD1) +#define BM_PERFMON_CTRL_BUS_ERR_IRQ 0x00001000 +#define BM_PERFMON_CTRL_LATENCY_IRQ 0x00000800 +#define BM_PERFMON_CTRL_TRAP_IRQ 0x00000400 +#define BM_PERFMON_CTRL_BUS_ERR_IRQ_EN 0x00000200 +#define BM_PERFMON_CTRL_LATENCY_IRQ_EN 0x00000100 +#define BM_PERFMON_CTRL_TRAP_IRQ_EN 0x00000080 +#define BM_PERFMON_CTRL_LATENCY_ENABLE 0x00000040 +#define BM_PERFMON_CTRL_TRAP_IN_RANGE 0x00000020 +#define BM_PERFMON_CTRL_TRAP_ENABLE 0x00000010 +#define BM_PERFMON_CTRL_READ_EN 0x00000008 +#define BM_PERFMON_CTRL_CLR 0x00000004 +#define BM_PERFMON_CTRL_SNAP 0x00000002 +#define BM_PERFMON_CTRL_RUN 0x00000001 +#define BV_PERFMON_CTRL_RUN__HALT 0x0 +#define BV_PERFMON_CTRL_RUN__RUN 0x1 + +#define HW_PERFMON_MASTER_EN (0x00000010) + +#define BP_PERFMON_MASTER_EN_RSVD0 16 +#define BM_PERFMON_MASTER_EN_RSVD0 0xFFFF0000 +#define BF_PERFMON_MASTER_EN_RSVD0(v) \ + (((v) << 16) & BM_PERFMON_MASTER_EN_RSVD0) +#define BM_PERFMON_MASTER_EN_MID15 0x00008000 +#define BM_PERFMON_MASTER_EN_MID14 0x00004000 +#define BM_PERFMON_MASTER_EN_MID13 0x00002000 +#define BM_PERFMON_MASTER_EN_MID12 0x00001000 +#define BM_PERFMON_MASTER_EN_MID11 0x00000800 +#define BM_PERFMON_MASTER_EN_MID10 0x00000400 +#define BM_PERFMON_MASTER_EN_MID9 0x00000200 +#define BM_PERFMON_MASTER_EN_MID8 0x00000100 +#define BM_PERFMON_MASTER_EN_MID7 0x00000080 +#define BM_PERFMON_MASTER_EN_MID6 0x00000040 +#define BM_PERFMON_MASTER_EN_MID5 0x00000020 +#define BM_PERFMON_MASTER_EN_MID4 0x00000010 +#define BM_PERFMON_MASTER_EN_MID3 0x00000008 +#define BM_PERFMON_MASTER_EN_MID2 0x00000004 +#define BM_PERFMON_MASTER_EN_MID1 0x00000002 +#define BM_PERFMON_MASTER_EN_MID0 0x00000001 + +#define HW_PERFMON_TRAP_ADDR_LOW (0x00000020) + +#define BP_PERFMON_TRAP_ADDR_LOW_ADDR 0 +#define BM_PERFMON_TRAP_ADDR_LOW_ADDR 0xFFFFFFFF +#define BF_PERFMON_TRAP_ADDR_LOW_ADDR(v) (v) + +#define HW_PERFMON_TRAP_ADDR_HIGH (0x00000030) + +#define BP_PERFMON_TRAP_ADDR_HIGH_ADDR 0 +#define BM_PERFMON_TRAP_ADDR_HIGH_ADDR 0xFFFFFFFF +#define BF_PERFMON_TRAP_ADDR_HIGH_ADDR(v) (v) + +#define HW_PERFMON_LAT_THRESHOLD (0x00000040) + +#define BP_PERFMON_LAT_THRESHOLD_RSVD0 12 +#define BM_PERFMON_LAT_THRESHOLD_RSVD0 0xFFFFF000 +#define BF_PERFMON_LAT_THRESHOLD_RSVD0(v) \ + (((v) << 12) & BM_PERFMON_LAT_THRESHOLD_RSVD0) +#define BP_PERFMON_LAT_THRESHOLD_VALUE 0 +#define BM_PERFMON_LAT_THRESHOLD_VALUE 0x00000FFF +#define BF_PERFMON_LAT_THRESHOLD_VALUE(v) \ + (((v) << 0) & BM_PERFMON_LAT_THRESHOLD_VALUE) + +#define HW_PERFMON_ACTIVE_CYCLE (0x00000050) + +#define BP_PERFMON_ACTIVE_CYCLE_COUNT 0 +#define BM_PERFMON_ACTIVE_CYCLE_COUNT 0xFFFFFFFF +#define BF_PERFMON_ACTIVE_CYCLE_COUNT(v) (v) + +#define HW_PERFMON_TRANSFER_COUNT (0x00000060) + +#define BP_PERFMON_TRANSFER_COUNT_VALUE 0 +#define BM_PERFMON_TRANSFER_COUNT_VALUE 0xFFFFFFFF +#define BF_PERFMON_TRANSFER_COUNT_VALUE(v) (v) + +#define HW_PERFMON_TOTAL_LATENCY (0x00000070) + +#define BP_PERFMON_TOTAL_LATENCY_COUNT 0 +#define BM_PERFMON_TOTAL_LATENCY_COUNT 0xFFFFFFFF +#define BF_PERFMON_TOTAL_LATENCY_COUNT(v) (v) + +#define HW_PERFMON_DATA_COUNT (0x00000080) + +#define BP_PERFMON_DATA_COUNT_COUNT 0 +#define BM_PERFMON_DATA_COUNT_COUNT 0xFFFFFFFF +#define BF_PERFMON_DATA_COUNT_COUNT(v) (v) + +#define HW_PERFMON_MAX_LATENCY (0x00000090) + +#define BP_PERFMON_MAX_LATENCY_ABURST 30 +#define BM_PERFMON_MAX_LATENCY_ABURST 0xC0000000 +#define BF_PERFMON_MAX_LATENCY_ABURST(v) \ + (((v) << 30) & BM_PERFMON_MAX_LATENCY_ABURST) +#define BP_PERFMON_MAX_LATENCY_ALEN 26 +#define BM_PERFMON_MAX_LATENCY_ALEN 0x3C000000 +#define BF_PERFMON_MAX_LATENCY_ALEN(v) \ + (((v) << 26) & BM_PERFMON_MAX_LATENCY_ALEN) +#define BP_PERFMON_MAX_LATENCY_ASIZE 23 +#define BM_PERFMON_MAX_LATENCY_ASIZE 0x03800000 +#define BF_PERFMON_MAX_LATENCY_ASIZE(v) \ + (((v) << 23) & BM_PERFMON_MAX_LATENCY_ASIZE) +#define BP_PERFMON_MAX_LATENCY_TAGID 15 +#define BM_PERFMON_MAX_LATENCY_TAGID 0x007F8000 +#define BF_PERFMON_MAX_LATENCY_TAGID(v) \ + (((v) << 15) & BM_PERFMON_MAX_LATENCY_TAGID) +#define BP_PERFMON_MAX_LATENCY_RSVD0 12 +#define BM_PERFMON_MAX_LATENCY_RSVD0 0x00007000 +#define BF_PERFMON_MAX_LATENCY_RSVD0(v) \ + (((v) << 12) & BM_PERFMON_MAX_LATENCY_RSVD0) +#define BP_PERFMON_MAX_LATENCY_COUNT 0 +#define BM_PERFMON_MAX_LATENCY_COUNT 0x00000FFF +#define BF_PERFMON_MAX_LATENCY_COUNT(v) \ + (((v) << 0) & BM_PERFMON_MAX_LATENCY_COUNT) + +#define HW_PERFMON_DEBUG (0x000000a0) + +#define BP_PERFMON_DEBUG_RSVD 2 +#define BM_PERFMON_DEBUG_RSVD 0xFFFFFFFC +#define BF_PERFMON_DEBUG_RSVD(v) \ + (((v) << 2) & BM_PERFMON_DEBUG_RSVD) +#define BM_PERFMON_DEBUG_TOTAL_CYCLE_CLR_EN 0x00000002 +#define BM_PERFMON_DEBUG_ERR_MID 0x00000001 + +#define HW_PERFMON_VERSION (0x000000b0) + +#define BP_PERFMON_VERSION_MAJOR 24 +#define BM_PERFMON_VERSION_MAJOR 0xFF000000 +#define BF_PERFMON_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PERFMON_VERSION_MAJOR) +#define BP_PERFMON_VERSION_MINOR 16 +#define BM_PERFMON_VERSION_MINOR 0x00FF0000 +#define BF_PERFMON_VERSION_MINOR(v) \ + (((v) << 16) & BM_PERFMON_VERSION_MINOR) +#define BP_PERFMON_VERSION_STEP 0 +#define BM_PERFMON_VERSION_STEP 0x0000FFFF +#define BF_PERFMON_VERSION_STEP(v) \ + (((v) << 0) & BM_PERFMON_VERSION_STEP) +#endif /* __ARCH_ARM___PERFMON_H */ diff --git a/drivers/misc/uid_stat.c b/drivers/misc/uid_stat.c new file mode 100644 index 000000000000..e6760b56083c --- /dev/null +++ b/drivers/misc/uid_stat.c @@ -0,0 +1,153 @@ +/* drivers/misc/uid_stat.c + * + * Copyright (C) 2008 - 2009 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(uid_lock); +static LIST_HEAD(uid_list); +static struct proc_dir_entry *parent; + +struct uid_stat { + struct list_head link; + uid_t uid; + atomic_t tcp_rcv; + atomic_t tcp_snd; +}; + +static struct uid_stat *find_uid_stat(uid_t uid) { + unsigned long flags; + struct uid_stat *entry; + + spin_lock_irqsave(&uid_lock, flags); + list_for_each_entry(entry, &uid_list, link) { + if (entry->uid == uid) { + spin_unlock_irqrestore(&uid_lock, flags); + return entry; + } + } + spin_unlock_irqrestore(&uid_lock, flags); + return NULL; +} + +static int tcp_snd_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + unsigned int bytes; + char *p = page; + struct uid_stat *uid_entry = (struct uid_stat *) data; + if (!data) + return 0; + + bytes = (unsigned int) (atomic_read(&uid_entry->tcp_snd) + INT_MIN); + p += sprintf(p, "%u\n", bytes); + len = (p - page) - off; + *eof = (len <= count) ? 1 : 0; + *start = page + off; + return len; +} + +static int tcp_rcv_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + unsigned int bytes; + char *p = page; + struct uid_stat *uid_entry = (struct uid_stat *) data; + if (!data) + return 0; + + bytes = (unsigned int) (atomic_read(&uid_entry->tcp_rcv) + INT_MIN); + p += sprintf(p, "%u\n", bytes); + len = (p - page) - off; + *eof = (len <= count) ? 1 : 0; + *start = page + off; + return len; +} + +/* Create a new entry for tracking the specified uid. */ +static struct uid_stat *create_stat(uid_t uid) { + unsigned long flags; + char uid_s[32]; + struct uid_stat *new_uid; + struct proc_dir_entry *entry; + + /* Create the uid stat struct and append it to the list. */ + if ((new_uid = kmalloc(sizeof(struct uid_stat), GFP_KERNEL)) == NULL) + return NULL; + + new_uid->uid = uid; + /* Counters start at INT_MIN, so we can track 4GB of network traffic. */ + atomic_set(&new_uid->tcp_rcv, INT_MIN); + atomic_set(&new_uid->tcp_snd, INT_MIN); + + spin_lock_irqsave(&uid_lock, flags); + list_add_tail(&new_uid->link, &uid_list); + spin_unlock_irqrestore(&uid_lock, flags); + + sprintf(uid_s, "%d", uid); + entry = proc_mkdir(uid_s, parent); + + /* Keep reference to uid_stat so we know what uid to read stats from. */ + create_proc_read_entry("tcp_snd", S_IRUGO, entry , tcp_snd_read_proc, + (void *) new_uid); + + create_proc_read_entry("tcp_rcv", S_IRUGO, entry, tcp_rcv_read_proc, + (void *) new_uid); + + return new_uid; +} + +int uid_stat_tcp_snd(uid_t uid, int size) { + struct uid_stat *entry; + if ((entry = find_uid_stat(uid)) == NULL && + ((entry = create_stat(uid)) == NULL)) { + return -1; + } + atomic_add(size, &entry->tcp_snd); + return 0; +} + +int uid_stat_tcp_rcv(uid_t uid, int size) { + struct uid_stat *entry; + if ((entry = find_uid_stat(uid)) == NULL && + ((entry = create_stat(uid)) == NULL)) { + return -1; + } + atomic_add(size, &entry->tcp_rcv); + return 0; +} + +static int __init uid_stat_init(void) +{ + parent = proc_mkdir("uid_stat", NULL); + if (!parent) { + pr_err("uid_stat: failed to create proc entry\n"); + return -1; + } + return 0; +} + +__initcall(uid_stat_init); diff --git a/drivers/mmc/card/Kconfig b/drivers/mmc/card/Kconfig index 3f2a912659af..10ba9a035a58 100644 --- a/drivers/mmc/card/Kconfig +++ b/drivers/mmc/card/Kconfig @@ -50,3 +50,15 @@ config MMC_TEST This driver is only of interest to those developing or testing a host driver. Most people should say N here. + +config SDIO_UNIFI_FS + tristate "UniFi SDIO glue for Freescale MMC/SDIO" + depends on (MMC_MXC || MMC_IMX_ESDHCI) + depends on (MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS) + help + This provides an interface between the CSR UniFi WiFi + driver and the Freescale MMC/SDIO interface. + If you have a MXC platform with a UniFi WiFi chip, + say M here. + + If unsure, say N. diff --git a/drivers/mmc/card/Makefile b/drivers/mmc/card/Makefile index 0d407514f67d..bbcf742d0ea1 100644 --- a/drivers/mmc/card/Makefile +++ b/drivers/mmc/card/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_MMC_TEST) += mmc_test.o obj-$(CONFIG_SDIO_UART) += sdio_uart.o +obj-$(CONFIG_SDIO_UNIFI_FS) += unifi_fs/ diff --git a/drivers/mmc/card/unifi_fs/Makefile b/drivers/mmc/card/unifi_fs/Makefile new file mode 100644 index 000000000000..381d4a2d1fd5 --- /dev/null +++ b/drivers/mmc/card/unifi_fs/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_SDIO_UNIFI_FS) = unifi_fs.o +unifi_fs-objs = fs_lx.o diff --git a/drivers/mmc/card/unifi_fs/fs_lx.c b/drivers/mmc/card/unifi_fs/fs_lx.c new file mode 100644 index 000000000000..d449e6c13258 --- /dev/null +++ b/drivers/mmc/card/unifi_fs/fs_lx.c @@ -0,0 +1,683 @@ +/* + * fs_lx.c - Freescale SDIO glue module for UniFi. + * + * Copyright (C) 2008 Cambridge Silicon Radio Ltd. + * + * Important: + * This module does not support more than one device driver instances. + * + */ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#include "fs_sdio_api.h" + +struct regulator_unifi { + struct regulator *reg_gpo1; + struct regulator *reg_gpo2; + struct regulator *reg_1v5_ana_bb; + struct regulator *reg_vdd_vpa; + struct regulator *reg_1v5_dd; +}; + +static struct sdio_driver sdio_unifi_driver; + +static int fs_sdio_probe(struct sdio_func *func, + const struct sdio_device_id *id); +static void fs_sdio_remove(struct sdio_func *func); +static void fs_sdio_irq(struct sdio_func *func); +static int fs_sdio_suspend(struct device *dev, pm_message_t state); +static int fs_sdio_resume(struct device *dev); + +/* Globals to store the context to this module and the device driver */ +static struct sdio_dev *available_sdio_dev; +static struct fs_driver *available_driver; +struct mxc_unifi_platform_data *plat_data; + +extern void mxc_mmc_force_detect(int id); + +enum sdio_cmd_direction { + CMD_READ, + CMD_WRITE, +}; + +static int fsl_io_rw_direct(struct mmc_card *card, int write, unsigned fn, + unsigned addr, u8 in, u8 *out) +{ + struct mmc_command cmd; + int err; + + BUG_ON(!card); + BUG_ON(fn > 7); + + memset(&cmd, 0, sizeof(struct mmc_command)); + + cmd.opcode = SD_IO_RW_DIRECT; + cmd.arg = write ? 0x80000000 : 0x00000000; + cmd.arg |= fn << 28; + cmd.arg |= (write && out) ? 0x08000000 : 0x00000000; + cmd.arg |= addr << 9; + cmd.arg |= in; + cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; + + err = mmc_wait_for_cmd(card->host, &cmd, 0); + if (err) + return err; + + if (mmc_host_is_spi(card->host)) { + /* host driver already reported errors */ + } else { + if (cmd.resp[0] & R5_ERROR) + return -EIO; + if (cmd.resp[0] & R5_FUNCTION_NUMBER) + return -EINVAL; + if (cmd.resp[0] & R5_OUT_OF_RANGE) + return -ERANGE; + } + + if (out) { + if (mmc_host_is_spi(card->host)) + *out = (cmd.resp[0] >> 8) & 0xFF; + else + *out = cmd.resp[0] & 0xFF; + } + + return 0; +} + + +int fs_sdio_readb(struct sdio_dev *fdev, int funcnum, unsigned long addr, + unsigned char *pdata) +{ + int err; + char val; + + sdio_claim_host(fdev->func); + if (funcnum == 0) + val = sdio_f0_readb(fdev->func, (unsigned int)addr, &err); + else + val = sdio_readb(fdev->func, (unsigned int)addr, &err); + sdio_release_host(fdev->func); + if (!err) + *pdata = val; + else + printk(KERN_ERR "fs_lx: readb error,fun=%d,addr=%d,data=%d," + "err=%d\n", funcnum, (int)addr, *pdata, err); + + return err; +} +EXPORT_SYMBOL(fs_sdio_readb); + +int fs_sdio_writeb(struct sdio_dev *fdev, int funcnum, unsigned long addr, + unsigned char data) +{ + int err; + + sdio_claim_host(fdev->func); + if (funcnum == 0) + err = fsl_io_rw_direct(fdev->func->card, 1, 0, addr, + data, NULL); + else + sdio_writeb(fdev->func, data, (unsigned int)addr, &err); + sdio_release_host(fdev->func); + + if (err) + printk(KERN_ERR "fs_lx: writeb error,fun=%d,addr=%d,data=%d," + "err=%d\n", funcnum, (int)addr, data, err); + return err; +} +EXPORT_SYMBOL(fs_sdio_writeb); + +int fs_sdio_block_rw(struct sdio_dev *fdev, int funcnum, unsigned long addr, + unsigned char *pdata, unsigned int count, int direction) +{ + int err; + + sdio_claim_host(fdev->func); + if (direction == CMD_READ) + err = sdio_memcpy_fromio(fdev->func, pdata, addr, count); + else + err = sdio_memcpy_toio(fdev->func, addr, pdata, count); + sdio_release_host(fdev->func); + + return err; +} +EXPORT_SYMBOL(fs_sdio_block_rw); + +int fs_sdio_enable_interrupt(struct sdio_dev *fdev, int enable) +{ + struct mmc_host *host = fdev->func->card->host; + unsigned long flags; + + spin_lock_irqsave(&fdev->lock, flags); + if (enable) { + if (!fdev->int_enabled) { + fdev->int_enabled = 1; + host->ops->enable_sdio_irq(host, 1); + } + } else { + if (fdev->int_enabled) { + host->ops->enable_sdio_irq(host, 0); + fdev->int_enabled = 0; + } + } + spin_unlock_irqrestore(&fdev->lock, flags); + + return 0; +} +EXPORT_SYMBOL(fs_sdio_enable_interrupt); + +int fs_sdio_disable(struct sdio_dev *fdev) +{ + int err; + sdio_claim_host(fdev->func); + err = sdio_disable_func(fdev->func); + sdio_release_host(fdev->func); + if (err) + printk(KERN_ERR "fs_lx:fs_sdio_disable error,err=%d\n", err); + return err; +} +EXPORT_SYMBOL(fs_sdio_disable); + +int fs_sdio_enable(struct sdio_dev *fdev) +{ + int err = 0; + + sdio_claim_host(fdev->func); + err = sdio_disable_func(fdev->func); + err = sdio_enable_func(fdev->func); + sdio_release_host(fdev->func); + if (err) + printk(KERN_ERR "fs_lx:fs_sdio_enable error,err=%d\n", err); + return err; +} +EXPORT_SYMBOL(fs_sdio_enable); + +int fs_sdio_set_max_clock_speed(struct sdio_dev *fdev, int max_khz) +{ + struct mmc_card *card = fdev->func->card; + + /* Respect the host controller's min-max. */ + max_khz *= 1000; + if (max_khz < card->host->f_min) + max_khz = card->host->f_min; + if (max_khz > card->host->f_max) + max_khz = card->host->f_max; + + card->host->ios.clock = max_khz; + card->host->ops->set_ios(card->host, &card->host->ios); + + return max_khz / 1000; +} +EXPORT_SYMBOL(fs_sdio_set_max_clock_speed); + +int fs_sdio_set_block_size(struct sdio_dev *fdev, int blksz) +{ + return 0; +} +EXPORT_SYMBOL(fs_sdio_set_block_size); + +/* + * --------------------------------------------------------------------------- + * + * Turn on the power of WIFI card + * + * --------------------------------------------------------------------------- + */ +static void fs_unifi_power_on(void) +{ + struct regulator_unifi *reg_unifi; + unsigned int tmp; + + reg_unifi = plat_data->priv; + + if (reg_unifi->reg_gpo1) + regulator_enable(reg_unifi->reg_gpo1); + if (reg_unifi->reg_gpo2) + regulator_enable(reg_unifi->reg_gpo2); + + if (plat_data->enable) + plat_data->enable(1); + + if (reg_unifi->reg_1v5_ana_bb) { + regulator_set_voltage(reg_unifi->reg_1v5_ana_bb, + 1500000, 1500000); + regulator_enable(reg_unifi->reg_1v5_ana_bb); + } + if (reg_unifi->reg_vdd_vpa) { + tmp = regulator_get_voltage(reg_unifi->reg_vdd_vpa); + if (tmp < 3000000 || tmp > 3600000) + regulator_set_voltage(reg_unifi->reg_vdd_vpa, + 3000000, 3000000); + regulator_enable(reg_unifi->reg_vdd_vpa); + } + /* WL_1V5DD should come on last, 10ms after other supplies */ + msleep(10); + if (reg_unifi->reg_1v5_dd) { + regulator_set_voltage(reg_unifi->reg_1v5_dd, + 1500000, 1500000); + regulator_enable(reg_unifi->reg_1v5_dd); + } + msleep(10); +} + +/* + * --------------------------------------------------------------------------- + * + * Turn off the power of WIFI card + * + * --------------------------------------------------------------------------- + */ +static void fs_unifi_power_off(void) +{ + struct regulator_unifi *reg_unifi; + + reg_unifi = plat_data->priv; + if (reg_unifi->reg_1v5_dd) + regulator_disable(reg_unifi->reg_1v5_dd); + if (reg_unifi->reg_vdd_vpa) + regulator_disable(reg_unifi->reg_vdd_vpa); + + if (reg_unifi->reg_1v5_ana_bb) + regulator_disable(reg_unifi->reg_1v5_ana_bb); + + if (plat_data->enable) + plat_data->enable(0); + + if (reg_unifi->reg_gpo2) + regulator_disable(reg_unifi->reg_gpo2); + + if (reg_unifi->reg_gpo1) + regulator_disable(reg_unifi->reg_gpo1); +} + +/* This should be made conditional on being slot 2 too - so we can + * use a plug in card in slot 1 + */ +int fs_sdio_hard_reset(struct sdio_dev *fdev) +{ + return 0; +} +EXPORT_SYMBOL(fs_sdio_hard_reset); + +static const struct sdio_device_id fs_sdio_ids[] = { + {SDIO_DEVICE(0x032a, 0x0001)}, + { /* end: all zeroes */ }, +}; + +static struct sdio_driver sdio_unifi_driver = { + .name = "fs_unifi", + .probe = fs_sdio_probe, + .remove = fs_sdio_remove, + .id_table = fs_sdio_ids, + .drv = { + .suspend = fs_sdio_suspend, + .resume = fs_sdio_resume, + } +}; + +int fs_sdio_register_driver(struct fs_driver *driver) +{ + int ret, retry; + + /* Switch us on, sdio device may exist if power is on by default. */ + plat_data->hardreset(0); + if (available_sdio_dev) + mxc_mmc_force_detect(plat_data->host_id); + /* Wait for card removed */ + for (retry = 0; retry < 100; retry++) { + if (!available_sdio_dev) + break; + msleep(100); + } + if (retry == 100) + printk(KERN_ERR "fs_sdio_register_driver: sdio device exists, " + "timeout for card removed"); + fs_unifi_power_on(); + plat_data->hardreset(1); + msleep(500); + mxc_mmc_force_detect(plat_data->host_id); + for (retry = 0; retry < 100; retry++) { + if (available_sdio_dev) + break; + msleep(50); + } + if (retry == 100) + printk(KERN_ERR "fs_sdio_register_driver: Timeout waiting" + " for card added\n"); + /* Store the context to the device driver to the global */ + available_driver = driver; + + /* + * If available_sdio_dev is not NULL, probe has been called, + * so pass the probe to the registered driver + */ + if (available_sdio_dev) { + /* Store the context to the new device driver */ + available_sdio_dev->driver = driver; + + printk(KERN_INFO "fs_sdio_register_driver: Glue exists, add " + "device driver and register IRQ\n"); + driver->probe(available_sdio_dev); + + /* Register the IRQ handler to the SDIO IRQ. */ + sdio_claim_host(available_sdio_dev->func); + ret = sdio_claim_irq(available_sdio_dev->func, fs_sdio_irq); + sdio_release_host(available_sdio_dev->func); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(fs_sdio_register_driver); + +void fs_sdio_unregister_driver(struct fs_driver *driver) +{ + /* + * If available_sdio_dev is not NULL, probe has been called, + * so pass the remove to the registered driver to clean up. + */ + if (available_sdio_dev) { + struct mmc_host *host = available_sdio_dev->func->card->host; + + printk(KERN_INFO "fs_sdio_unregister_driver: Glue exists, " + "unregister IRQ and remove device driver\n"); + + /* Unregister the IRQ handler first. */ + sdio_claim_host(available_sdio_dev->func); + sdio_release_irq(available_sdio_dev->func); + sdio_release_host(available_sdio_dev->func); + + driver->remove(available_sdio_dev); + + if (!available_sdio_dev->int_enabled) { + available_sdio_dev->int_enabled = 1; + host->ops->enable_sdio_irq(host, 1); + } + + /* Invalidate the context to the device driver */ + available_sdio_dev->driver = NULL; + } + + /* invalidate the context to the device driver to the global */ + available_driver = NULL; + /* Power down the UniFi */ + fs_unifi_power_off(); + +} +EXPORT_SYMBOL(fs_sdio_unregister_driver); + +static void fs_sdio_irq(struct sdio_func *func) +{ + struct sdio_dev *fdev = (struct sdio_dev *)sdio_get_drvdata(func); + if (fdev->driver) { + if (fdev->driver->card_int_handler) + fdev->driver->card_int_handler(fdev); + } +} + +#ifdef CONFIG_PM +static int fs_sdio_suspend(struct device *dev, pm_message_t state) +{ + struct sdio_dev *fdev = available_sdio_dev; + + /* Pass event to the registered driver. */ + if (fdev->driver) + if (fdev->driver->suspend) + fdev->driver->suspend(fdev, state); + + return 0; +} + +static int fs_sdio_resume(struct device *dev) +{ + struct sdio_dev *fdev = available_sdio_dev; + + /* Pass event to the registered driver. */ + if (fdev->driver) + if (fdev->driver->resume) + fdev->driver->resume(fdev); + + return 0; +} +#else +#define fs_sdio_suspend NULL +#define fs_sdio_resume NULL +#endif + +static int fs_sdio_probe(struct sdio_func *func, + const struct sdio_device_id *id) +{ + struct sdio_dev *fdev; + + /* Allocate our private context */ + fdev = kmalloc(sizeof(struct sdio_dev), GFP_KERNEL); + if (!fdev) + return -ENOMEM; + available_sdio_dev = fdev; + memset(fdev, 0, sizeof(struct sdio_dev)); + fdev->func = func; + fdev->vendor_id = id->vendor; + fdev->device_id = id->device; + fdev->max_blocksize = func->max_blksize; + fdev->int_enabled = 1; + spin_lock_init(&fdev->lock); + + /* Store our context in the MMC driver */ + printk(KERN_INFO "fs_sdio_probe: Add glue driver\n"); + sdio_set_drvdata(func, fdev); + + return 0; +} + +static void fs_sdio_remove(struct sdio_func *func) +{ + struct sdio_dev *fdev = (struct sdio_dev *)sdio_get_drvdata(func); + struct mmc_host *host = func->card->host; + + /* If there is a registered device driver, pass on the remove */ + if (fdev->driver) { + printk(KERN_INFO "fs_sdio_remove: Free IRQ and remove device " + "driver\n"); + /* Unregister the IRQ handler first. */ + sdio_claim_host(fdev->func); + sdio_release_irq(func); + sdio_release_host(fdev->func); + + fdev->driver->remove(fdev); + + if (!fdev->int_enabled) { + fdev->int_enabled = 1; + host->ops->enable_sdio_irq(host, 1); + } + } + + /* Unregister the card context from the MMC driver. */ + sdio_set_drvdata(func, NULL); + + /* Invalidate the global to our context. */ + available_sdio_dev = NULL; + kfree(fdev); +} + +static int fs_unifi_init(void) +{ + struct regulator_unifi *reg_unifi; + struct regulator *reg; + int err = 0; + + plat_data = get_unifi_plat_data(); + + if (!plat_data) + return -ENOENT; + + reg_unifi = kzalloc(sizeof(struct regulator_unifi), GFP_KERNEL); + if (!reg_unifi) + return -ENOMEM; + + if (plat_data->reg_gpo1) { + reg = regulator_get(NULL, plat_data->reg_gpo1); + if (!IS_ERR(reg)) + reg_unifi->reg_gpo1 = reg; + else { + err = -EINVAL; + goto err_reg_gpo1; + } + } + + if (plat_data->reg_gpo2) { + reg = regulator_get(NULL, plat_data->reg_gpo2); + if (!IS_ERR(reg)) + reg_unifi->reg_gpo2 = reg; + else { + err = -EINVAL; + goto err_reg_gpo2; + } + } + + if (plat_data->reg_1v5_ana_bb) { + reg = regulator_get(NULL, plat_data->reg_1v5_ana_bb); + if (!IS_ERR(reg)) + reg_unifi->reg_1v5_ana_bb = reg; + else { + err = -EINVAL; + goto err_reg_1v5_ana_bb; + } + } + + if (plat_data->reg_vdd_vpa) { + reg = regulator_get(NULL, plat_data->reg_vdd_vpa); + if (!IS_ERR(reg)) + reg_unifi->reg_vdd_vpa = reg; + else { + err = -EINVAL; + goto err_reg_vdd_vpa; + } + } + + if (plat_data->reg_1v5_dd) { + reg = regulator_get(NULL, plat_data->reg_1v5_dd); + if (!IS_ERR(reg)) + reg_unifi->reg_1v5_dd = reg; + else { + err = -EINVAL; + goto err_reg_1v5_dd; + } + } + plat_data->priv = reg_unifi; + return 0; + +err_reg_1v5_dd: + if (reg_unifi->reg_vdd_vpa) + regulator_put(reg_unifi->reg_vdd_vpa); +err_reg_vdd_vpa: + if (reg_unifi->reg_1v5_ana_bb) + regulator_put(reg_unifi->reg_1v5_ana_bb); +err_reg_1v5_ana_bb: + if (reg_unifi->reg_gpo2) + regulator_put(reg_unifi->reg_gpo2); +err_reg_gpo2: + if (reg_unifi->reg_gpo1) + regulator_put(reg_unifi->reg_gpo1); +err_reg_gpo1: + kfree(reg_unifi); + return err; +} + +int fs_unifi_remove(void) +{ + struct regulator_unifi *reg_unifi; + + reg_unifi = plat_data->priv; + plat_data->priv = NULL; + + if (reg_unifi->reg_1v5_dd) + regulator_put(reg_unifi->reg_1v5_dd); + if (reg_unifi->reg_vdd_vpa) + regulator_put(reg_unifi->reg_vdd_vpa); + + if (reg_unifi->reg_1v5_ana_bb) + regulator_put(reg_unifi->reg_1v5_ana_bb); + + if (reg_unifi->reg_gpo2) + regulator_put(reg_unifi->reg_gpo2); + + if (reg_unifi->reg_gpo1) + regulator_put(reg_unifi->reg_gpo1); + + kfree(reg_unifi); + return 0; +} + +/* Module init and exit, register and unregister to the SDIO/MMC driver */ +static int __init fs_sdio_init(void) +{ + int err; + + printk(KERN_INFO "Freescale: Register to MMC/SDIO driver\n"); + /* Sleep a bit - otherwise if the mmc subsystem has just started, it + * will allow us to register, then immediatly remove us! + */ + msleep(10); + err = fs_unifi_init(); + if (err) { + printk(KERN_ERR "Error: fs_unifi_init failed!\n"); + return err; + } + err = sdio_register_driver(&sdio_unifi_driver); + if (err) { + printk(KERN_ERR "Error: register sdio_unifi_driver failed!\n"); + fs_unifi_remove(); + } + return err; +} + +module_init(fs_sdio_init); + +static void __exit fs_sdio_exit(void) +{ + printk(KERN_INFO "Freescale: Unregister from MMC/SDIO driver\n"); + sdio_unregister_driver(&sdio_unifi_driver); + fs_unifi_remove(); +} + +module_exit(fs_sdio_exit); + +MODULE_DESCRIPTION("Freescale SDIO glue driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/card/unifi_fs/fs_sdio_api.h b/drivers/mmc/card/unifi_fs/fs_sdio_api.h new file mode 100644 index 000000000000..d23531509d62 --- /dev/null +++ b/drivers/mmc/card/unifi_fs/fs_sdio_api.h @@ -0,0 +1,68 @@ +/* + *fs_sdio_api.h - Freescale SDIO glue module API for UniFi. + * + * Copyright (C) 2008 Cambridge Silicon Radio Ltd. + * + */ +/* + * Copyright 2008-2010 Freescale Semiconductor + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef _FS_SDIO_API_H +#define _FS_SDIO_API_H + +struct sdio_dev; + +struct fs_driver { + const char *name; + int (*probe)(struct sdio_dev *fdev); + void (*remove)(struct sdio_dev *fdev); + void (*card_int_handler)(struct sdio_dev *fdev); + void (*suspend)(struct sdio_dev *fdev, pm_message_t state); + void (*resume)(struct sdio_dev *fdev); +}; + +int fs_sdio_readb(struct sdio_dev *fdev, int funcnum, + unsigned long addr, unsigned char *pdata); +int fs_sdio_writeb(struct sdio_dev *fdev, int funcnum, + unsigned long addr, unsigned char data); +int fs_sdio_block_rw(struct sdio_dev *fdev, int funcnum, + unsigned long addr, unsigned char *pdata, + unsigned int count, int direction); + +int fs_sdio_register_driver(struct fs_driver *driver); +void fs_sdio_unregister_driver(struct fs_driver *driver); +int fs_sdio_set_block_size(struct sdio_dev *fdev, int blksz); +int fs_sdio_set_max_clock_speed(struct sdio_dev *fdev, int max_khz); +int fs_sdio_enable_interrupt(struct sdio_dev *fdev, int enable); +int fs_sdio_enable(struct sdio_dev *fdev); +int fs_sdio_hard_reset(struct sdio_dev *fdev); + +struct sdio_dev { + /**< Device driver for this module. */ + struct fs_driver *driver; + + struct sdio_func *func; + + /**< Data private to the device driver. */ + void *drv_data; + + int int_enabled; + spinlock_t lock; + + uint16_t vendor_id; /**< Vendor ID of the card. */ + uint16_t device_id; /**< Device ID of the card. */ + + /**< Maximum block size supported. */ + int max_blocksize; +}; + + +#endif /* #ifndef _FS_SDIO_API_H */ diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 89f7a25b7ac1..95e13c2bbd59 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -122,7 +122,7 @@ static int mmc_decode_csd(struct mmc_card *card) * v1.2 has extra information in bits 15, 11 and 10. */ csd_struct = UNSTUFF_BITS(resp, 126, 2); - if (csd_struct != 1 && csd_struct != 2) { + if (csd_struct < 1 || csd_struct > 3) { printk(KERN_ERR "%s: unrecognised CSD structure version %d\n", mmc_hostname(card->host), csd_struct); return -EINVAL; @@ -222,10 +222,18 @@ static int mmc_read_ext_csd(struct mmc_card *card) ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; - if (card->ext_csd.sectors) + + /* Cards with density > 2GiB are sector addressed */ + if (card->ext_csd.sectors > (2u * 1024 * 1024 * 1024) / 512) mmc_card_set_blockaddr(card); } + card->ext_csd.boot_info = ext_csd[EXT_CSD_BOOT_INFO]; + card->ext_csd.boot_size_mult = ext_csd[EXT_CSD_BOOT_SIZE_MULT]; + card->ext_csd.boot_config = ext_csd[EXT_CSD_BOOT_CONFIG]; + card->ext_csd.boot_bus_width = ext_csd[EXT_CSD_BOOT_BUS_WIDTH]; + card->ext_csd.card_type = ext_csd[EXT_CSD_CARD_TYPE]; + switch (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_MASK) { case EXT_CSD_CARD_TYPE_52 | EXT_CSD_CARD_TYPE_26: card->ext_csd.hs_max_dtr = 52000000; @@ -238,6 +246,9 @@ static int mmc_read_ext_csd(struct mmc_card *card) printk(KERN_WARNING "%s: card is mmc v4 but doesn't " "support any high-speed modes.\n", mmc_hostname(card->host)); + printk(KERN_WARNING "%s: card type is 0x%x\n", + mmc_hostname(card->host), ext_csd[EXT_CSD_CARD_TYPE]); + goto out; } if (card->ext_csd.rev >= 3) { @@ -255,6 +266,281 @@ out: return err; } +/* configure the boot partitions */ +static ssize_t +setup_boot_partitions(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int err, busy = 0; + u32 part, new_part; + u8 *ext_csd, boot_config; + struct mmc_command cmd; + struct mmc_card *card = container_of(dev, struct mmc_card, dev); + + BUG_ON(!card); + + sscanf(buf, "%d\n", &part); + + if (card->csd.mmca_vsn < CSD_SPEC_VER_4) { + printk(KERN_ERR "%s: invalid mmc version" + " mmc version is below version 4!)\n", + mmc_hostname(card->host)); + return -EINVAL; + } + + /* it's a normal SD/MMC but user request to configure boot partition */ + if (card->ext_csd.boot_size_mult <= 0) { + printk(KERN_ERR "%s: this is a normal SD/MMC card" + " but you request to access boot partition!\n", + mmc_hostname(card->host)); + return -EINVAL; + } + + ext_csd = kmalloc(512, GFP_KERNEL); + if (!ext_csd) { + printk(KERN_ERR "%s: could not allocate a buffer to " + "receive the ext_csd.\n", mmc_hostname(card->host)); + return -ENOMEM; + } + + mmc_claim_host(card->host); + err = mmc_send_ext_csd(card, ext_csd); + if (err) { + printk(KERN_ERR "%s: unable to read EXT_CSD.\n", + mmc_hostname(card->host)); + goto err_rtn; + } + + /* enable the boot partition in boot mode */ + /* boot enable be - + * 0x00 - disable boot enable. + * 0x08 - boot partition 1 is enabled for boot. + * 0x10 - boot partition 2 is enabled for boot. + * 0x38 - User area is enabled for boot. + */ + switch (part & EXT_CSD_BOOT_PARTITION_ENABLE_MASK) { + case 0: + boot_config = (ext_csd[EXT_CSD_BOOT_CONFIG] + & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK + & ~EXT_CSD_BOOT_ACK_ENABLE); + break; + case EXT_CSD_BOOT_PARTITION_PART1: + boot_config = ((ext_csd[EXT_CSD_BOOT_CONFIG] + & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK) + | EXT_CSD_BOOT_PARTITION_PART1 + | EXT_CSD_BOOT_ACK_ENABLE); + break; + case EXT_CSD_BOOT_PARTITION_PART2: + boot_config = ((ext_csd[EXT_CSD_BOOT_CONFIG] + & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK) + | EXT_CSD_BOOT_PARTITION_PART2 + | EXT_CSD_BOOT_ACK_ENABLE); + break; + case EXT_CSD_BOOT_PARTITION_ENABLE_MASK: + boot_config = ((ext_csd[EXT_CSD_BOOT_CONFIG] + | EXT_CSD_BOOT_PARTITION_ENABLE_MASK) + & ~EXT_CSD_BOOT_ACK_ENABLE); + break; + default: + printk(KERN_ERR "%s: wrong boot config parameter" + " 00 (disable boot), 08 (enable boot1)," + "16 (enable boot2), 56 (User area)\n", + mmc_hostname(card->host)); + err = -EINVAL; + goto err_rtn; + } + + /* switch the partitions that used to be accessed in OS layer */ + /* partition must be - + * 0 - user area + * 1 - boot partition 1 + * 2 - boot partition 2 + */ + if ((part & EXT_CSD_BOOT_PARTITION_ACCESS_MASK) > 2) { + printk(KERN_ERR "%s: wrong partition id" + " 0 (user area), 1 (boot1), 2 (boot2)\n", + mmc_hostname(card->host)); + err = -EINVAL; + goto err_rtn; + } + + /* Send SWITCH command to change partition for access */ + boot_config &= ~EXT_CSD_BOOT_PARTITION_ACCESS_MASK; + boot_config |= (part & EXT_CSD_BOOT_PARTITION_ACCESS_MASK); + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BOOT_CONFIG, boot_config); + if (err) { + printk(KERN_ERR "%s: fail to send SWITCH command" + " to card to swich partition for access!\n", + mmc_hostname(card->host)); + goto err_rtn; + } + + /* waiting for the card to finish the busy state */ + do { + memset(&cmd, 0, sizeof(struct mmc_command)); + + cmd.opcode = MMC_SEND_STATUS; + cmd.arg = card->rca << 16; + cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; + + err = mmc_wait_for_cmd(card->host, &cmd, 0); + if (err || busy > 100) { + printk(KERN_ERR "%s: failed to wait for" + "the busy state to end.\n", + mmc_hostname(card->host)); + break; + } + + if (!busy && !(cmd.resp[0] & R1_READY_FOR_DATA)) { + printk(KERN_INFO "%s: card is in busy state" + "pls wait for busy state to end.\n", + mmc_hostname(card->host)); + } + busy++; + } while (!(cmd.resp[0] & R1_READY_FOR_DATA)); + + /* Now check whether it works */ + err = mmc_send_ext_csd(card, ext_csd); + if (err) { + printk(KERN_ERR "%s: %d unable to re-read EXT_CSD.\n", + mmc_hostname(card->host), err); + goto err_rtn; + } + + new_part = ext_csd[EXT_CSD_BOOT_CONFIG] & + EXT_CSD_BOOT_PARTITION_ACCESS_MASK; + if ((part & EXT_CSD_BOOT_PARTITION_ACCESS_MASK) != new_part) { + printk(KERN_ERR "%s: after SWITCH, current part id %d is not" + " same as requested partition %d!\n", + mmc_hostname(card->host), new_part, part); + goto err_rtn; + } + card->ext_csd.boot_config = ext_csd[EXT_CSD_BOOT_CONFIG]; + +err_rtn: + mmc_release_host(card->host); + kfree(ext_csd); + if (err) + return err; + else + return count; +} + +/* configure the boot bus */ +static ssize_t +setup_boot_bus(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int err, busy = 0; + u32 boot_bus, new_bus; + u8 *ext_csd; + struct mmc_command cmd; + struct mmc_card *card = container_of(dev, struct mmc_card, dev); + + BUG_ON(!card); + + sscanf(buf, "%d\n", &boot_bus); + + if (card->csd.mmca_vsn < CSD_SPEC_VER_4) { + printk(KERN_ERR "%s: invalid mmc version" + " mmc version is below version 4!)\n", + mmc_hostname(card->host)); + return -EINVAL; + } + + /* it's a normal SD/MMC but user request to configure boot bus */ + if (card->ext_csd.boot_size_mult <= 0) { + printk(KERN_ERR "%s: this is a normal SD/MMC card" + " but you request to configure boot bus !\n", + mmc_hostname(card->host)); + return -EINVAL; + } + + ext_csd = kmalloc(512, GFP_KERNEL); + if (!ext_csd) { + printk(KERN_ERR "%s: could not allocate a buffer to " + "receive the ext_csd.\n", mmc_hostname(card->host)); + return -ENOMEM; + } + + mmc_claim_host(card->host); + err = mmc_send_ext_csd(card, ext_csd); + if (err) { + printk(KERN_ERR "%s: unable to read EXT_CSD.\n", + mmc_hostname(card->host)); + goto err_rtn; + } + + /* Configure the boot bus width when boot partition is enabled */ + if (((boot_bus & EXT_CSD_BOOT_BUS_WIDTH_MODE_MASK) >> 3) > 2 + || (boot_bus & EXT_CSD_BOOT_BUS_WIDTH_WIDTH_MASK) > 2 + || (boot_bus & ~EXT_CSD_BOOT_BUS_WIDTH_MASK) > 0) { + printk(KERN_ERR "%s: Invalid inputs!\n", + mmc_hostname(card->host)); + err = -EINVAL; + goto err_rtn; + } + + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BOOT_BUS_WIDTH, boot_bus); + if (err) { + printk(KERN_ERR "%s: fail to send SWITCH command to " + "card to swich partition for access!\n", + mmc_hostname(card->host)); + goto err_rtn; + } + + /* waiting for the card to finish the busy state */ + do { + memset(&cmd, 0, sizeof(struct mmc_command)); + + cmd.opcode = MMC_SEND_STATUS; + cmd.arg = card->rca << 16; + cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; + + err = mmc_wait_for_cmd(card->host, &cmd, 0); + if (err || busy > 100) { + printk(KERN_ERR "%s: failed to wait for" + "the busy state to end.\n", + mmc_hostname(card->host)); + break; + } + + if (!busy && !(cmd.resp[0] & R1_READY_FOR_DATA)) { + printk(KERN_INFO "%s: card is in busy state" + "pls wait for busy state to end.\n", + mmc_hostname(card->host)); + } + busy++; + } while (!(cmd.resp[0] & R1_READY_FOR_DATA)); + + /* Now check whether it works */ + err = mmc_send_ext_csd(card, ext_csd); + if (err) { + printk(KERN_ERR "%s: %d unable to re-read EXT_CSD.\n", + mmc_hostname(card->host), err); + goto err_rtn; + } + + new_bus = ext_csd[EXT_CSD_BOOT_BUS_WIDTH]; + if (boot_bus != new_bus) { + printk(KERN_ERR "%s: after SWITCH, current boot bus mode %d" + " is not same as requested bus mode %d!\n", + mmc_hostname(card->host), new_bus, boot_bus); + goto err_rtn; + } + card->ext_csd.boot_bus_width = ext_csd[EXT_CSD_BOOT_BUS_WIDTH]; + +err_rtn: + mmc_release_host(card->host); + kfree(ext_csd); + if (err) + return err; + else + return count; +} + MMC_DEV_ATTR(cid, "%08x%08x%08x%08x\n", card->raw_cid[0], card->raw_cid[1], card->raw_cid[2], card->raw_cid[3]); MMC_DEV_ATTR(csd, "%08x%08x%08x%08x\n", card->raw_csd[0], card->raw_csd[1], @@ -267,6 +553,114 @@ MMC_DEV_ATTR(name, "%s\n", card->cid.prod_name); MMC_DEV_ATTR(oemid, "0x%04x\n", card->cid.oemid); MMC_DEV_ATTR(serial, "0x%08x\n", card->cid.serial); +static ssize_t mmc_boot_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + char *boot_partition[8] = { + "Device not boot enabled", + "Boot partition 1 enabled", + "Boot partition 2 enabled", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "User area enabled for boot"}; + + char *boot_partition_access[8] = { + "No access to boot partition", + "R/W boot partition 1", + "R/W boot partition 2", + "R/W Replay Protected Memory Block (RPMB)", + "Access to General Purpose partition 1", + "Access to General Purpose partition 2", + "Access to General Purpose partition 3", + "Access to General Purpose partition 4"}; + + char *bus_width[4] = { + "x1 (sdr) or x4 (ddr) bus width in boot operation mode", + "x4 (sdr/ddr) bus width in boot operation mode", + "x8 (sdr/ddr) bus width in boot operation mode", + "Reserved"}; + + char *boot_mode[4] = { + "Use single data rate + backward compatible timings in boot operation", + "Use single data rate + high speed timings in boot operation mode", + "Use dual data rate in boot operation", + "Reserved"}; + + int partition; + int access; + int width; + int mode; + struct mmc_card *card = container_of(dev, struct mmc_card, dev); + + /* read it again because user may change it */ + mmc_claim_host(card->host); + mmc_read_ext_csd(card); + mmc_release_host(card->host); + + partition = (card->ext_csd.boot_config >> 3) & 0x7; + access = card->ext_csd.boot_config & 0x7; + width = card->ext_csd.boot_bus_width & 0x3; + mode = (card->ext_csd.boot_bus_width >> 3) & 0x3; + + return sprintf(buf, + "boot_info:0x%02x;\n" + " ALT_BOOT_MODE:%x - %s\n" + " DDR_BOOT_MODE:%x - %s\n" + " HS_BOOTMODE:%x - %s\n" + "boot_size:%04dKB\n" + "boot_partition:0x%02x;\n" + " BOOT_ACK:%x - %s\n" + " BOOT_PARTITION-ENABLE: %x - %s\n" + " PARTITION_ACCESS:%x - %s\n" + "boot_bus:0x%02x\n" + " BOOT_MODE:%x - %s\n" + " RESET_BOOT_BUS_WIDTH:%x - %s\n" + " BOOT_BUS_WIDTH:%x - %s\n", + + card->ext_csd.boot_info, + !!(card->ext_csd.boot_info & 0x1), + (card->ext_csd.boot_info & 0x1) ? + "Supports alternate boot method" : + "Does not support alternate boot method", + !!(card->ext_csd.boot_info & 0x2), + (card->ext_csd.boot_info & 0x2) ? + "Supports alternate dual data rate during boot" : + "Does not support dual data rate during boot", + !!(card->ext_csd.boot_info & 0x4), + (card->ext_csd.boot_info & 0x4) ? + "Supports high speed timing during boot" : + "Does not support high speed timing during boot", + + card->ext_csd.boot_size_mult * 128, + + card->ext_csd.boot_config, + !!(card->ext_csd.boot_config & 0x40), + (card->ext_csd.boot_config & 0x40) ? + "Boot acknowledge sent during boot operation" : + "No boot acknowledge sent", + partition, + boot_partition[partition], + access, + boot_partition_access[access], + + card->ext_csd.boot_bus_width, + mode, + boot_mode[mode], + !!(card->ext_csd.boot_bus_width & 0x4), + (card->ext_csd.boot_bus_width & 0x4) ? + "Retain boot bus width and boot mode after boot operation" : + "Reset bus width to x1, single data rate and backward" + "compatible timings after boot operation", + width, + bus_width[width]); +} + +DEVICE_ATTR(boot_config, S_IWUGO, NULL, setup_boot_partitions); +DEVICE_ATTR(boot_bus_config, S_IWUGO, NULL, setup_boot_bus); +DEVICE_ATTR(boot_info, S_IRUGO, mmc_boot_info_show, NULL); + static struct attribute *mmc_std_attrs[] = { &dev_attr_cid.attr, &dev_attr_csd.attr, @@ -277,6 +671,9 @@ static struct attribute *mmc_std_attrs[] = { &dev_attr_name.attr, &dev_attr_oemid.attr, &dev_attr_serial.attr, + &dev_attr_boot_info.attr, + &dev_attr_boot_config.attr, + &dev_attr_boot_bus_config.attr, NULL, }; @@ -447,10 +844,21 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, * Activate wide bus (if supported). */ if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) && - (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) { + (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR))) { unsigned ext_csd_bit, bus_width; - if (host->caps & MMC_CAP_8_BIT_DATA) { + if ((host->caps & MMC_CAP_8_BIT_DATA) && + (host->caps & MMC_CAP_DATA_DDR) && + (card->ext_csd.card_type & MMC_DDR_MODE_MASK)) { + ext_csd_bit = EXT_CSD_BUS_WIDTH_8_DDR; + bus_width = MMC_BUS_WIDTH_8 | MMC_BUS_WIDTH_DDR; + } else if ((host->caps & MMC_CAP_4_BIT_DATA) && + (host->caps & MMC_CAP_DATA_DDR) && + (card->ext_csd.card_type & MMC_DDR_MODE_MASK)) { + ext_csd_bit = EXT_CSD_BUS_WIDTH_4_DDR; + bus_width = MMC_BUS_WIDTH_4 | MMC_BUS_WIDTH_DDR; + } else if (host->caps & MMC_CAP_8_BIT_DATA) { ext_csd_bit = EXT_CSD_BUS_WIDTH_8; bus_width = MMC_BUS_WIDTH_8; } else { diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index f06d06e7fdfa..951f1fd2661f 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -313,6 +313,59 @@ config MMC_SPI If unsure, or if your system has no SPI master driver, say N. +config MMC_MXC + tristate "Freescale MXC Multimedia Card Interface support" + depends on ARCH_MXC && MMC + help + This selects the Freescale MXC Multimedia card Interface. + If you have a MXC platform with a Multimedia Card slot, + say Y or M here. + +config MMC_IMX_ESDHCI + tristate "Freescale i.MX Secure Digital Host Controller Interface support" + depends on ARCH_MXC && MMC + help + This selects the Freescale i.MX Multimedia card Interface. + If you have a i.MX platform with a Multimedia Card slot, + say Y or M here. + + If unsure, say N. + +config MMC_IMX_ESDHCI_SELECT2 + bool "Enable second ESDHCI port" + depends on MMC_IMX_ESDHCI && ARCH_MX25 + default n + help + Enable the second ESDHC port + +config MMC_IMX_ESDHCI_PIO_MODE + bool "Freescale i.MX Secure Digital Host Controller Interface PIO mode" + depends on MMC_IMX_ESDHC != n + default n + help + This set the Freescale i.MX Multimedia card Interface to PIO mode. + If you have a i.MX platform with a Multimedia Card slot, + and want test it with PIO mode. + say Y here. + + If unsure, say N. + +config MMC_STMP3XXX + tristate "STMP37xx/378x MMC support" + depends on MMC && ARCH_STMP3XXX + help + Select Y if you would like to access STMP37xx/378x MMC support. + + If unsure, say N. + +config MMC_MXS + tristate "MXS MMC support" + depends on MMC && (ARCH_MX28 || ARCH_MX23) + help + Select Y if you would like to access MXS MMC support. + + If unsure, say N. + config MMC_S3C tristate "Samsung S3C SD/MMC Card Interface support" depends on ARCH_S3C2410 @@ -371,6 +424,7 @@ config MMC_SDRICOH_CS help Say Y here if your Notebook reports a Ricoh Bay1Controller PCMCIA card whenever you insert a MMC or SD card into the card slot. + say Y or M here. To compile this driver as a module, choose M here: the module will be called sdricoh_cs. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index e30c2ee48894..70643ebe0e57 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -9,12 +9,14 @@ endif obj-$(CONFIG_MMC_ARMMMCI) += mmci.o obj-$(CONFIG_MMC_PXA) += pxamci.o obj-$(CONFIG_MMC_IMX) += imxmmc.o -obj-$(CONFIG_MMC_MXC) += mxcmmc.o +obj-$(CONFIG_MMC_MXC) += mxc_mmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o +obj-$(CONFIG_MMC_IMX_ESDHCI) += mx_sdhci.o +obj-$(CONFIG_MMC_MXS) += mxs-mmc.o obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o obj-$(CONFIG_MMC_OMAP) += omap.o diff --git a/drivers/mmc/host/mx_sdhci.c b/drivers/mmc/host/mx_sdhci.c new file mode 100644 index 000000000000..54910b72d6b0 --- /dev/null +++ b/drivers/mmc/host/mx_sdhci.c @@ -0,0 +1,2289 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx_sdhci.c + * + * @brief Driver for the Freescale Semiconductor MXC eSDHC modules. + * + * This driver code is based on sdhci.c, by Pierre Ossman "); + * This driver supports Enhanced Secure Digital Host Controller + * modules eSDHC of MXC. eSDHC is also referred as enhanced MMC/SD + * controller. + * + * @ingroup MMC_SD + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "mx_sdhci.h" + +#define DRIVER_NAME "mxsdhci" + +#define DBG(f, x...) \ + pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) + +static unsigned int debug_quirks; +static int last_op_dir; + +/* + * Different quirks to handle when the hardware deviates from a strict + * interpretation of the SDHCI specification. + */ + +/* Controller doesn't honor resets unless we touch the clock register */ +#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) +/* Controller has bad caps bits, but really supports DMA */ +#define SDHCI_QUIRK_FORCE_DMA (1<<1) +/* Controller doesn't like to be reset when there is no card inserted. */ +#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) +/* Controller doesn't like clearing the power reg before a change */ +#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) +/* Controller has flaky internal state so reset it on each ios change */ +#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) +/* Controller has an unusable DMA engine */ +#define SDHCI_QUIRK_BROKEN_DMA (1<<5) +/* Controller can only DMA from 32-bit aligned addresses */ +#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6) +/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ +#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7) +/* Controller needs to be reset after each request to stay stable */ +#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8) +/* Controller needs voltage and power writes to happen separately */ +#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9) +/* Controller has an off-by-one issue with timeout value */ +#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<10) +/* Controller only support the PIO */ +#define SDHCI_QUIRK_ONLY_PIO (1<<16) +/* Controller support the External DMA */ +#define SDHCI_QUIRK_EXTERNAL_DMA_MODE (1<<17) +/* Controller support the Internal Simple DMA */ +#define SDHCI_QUIRK_INTERNAL_SIMPLE_DMA (1<<18) +/* Controller support the Internal Advanced DMA */ +#define SDHCI_QUIRK_INTERNAL_ADVANCED_DMA (1<<19) + +/* + * defines the mxc flags refer to the special hw pre-conditons and behavior + */ +static unsigned int mxc_quirks; +#ifdef CONFIG_MMC_IMX_ESDHCI_PIO_MODE +static unsigned int debug_quirks = SDHCI_QUIRK_ONLY_PIO; +#else +static unsigned int debug_quirks; +#endif +static unsigned int mxc_wml_value = 512; +static unsigned int *adma_des_table; + +#ifndef MXC_SDHCI_NUM +#define MXC_SDHCI_NUM 4 +#endif + +static struct sdhci_chip *mxc_fix_chips[MXC_SDHCI_NUM]; + +static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); +static void sdhci_finish_data(struct sdhci_host *); + +static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); +static void sdhci_finish_command(struct sdhci_host *); + +/* Used to active the SD bus */ +extern void gpio_sdhc_active(int module); +extern void gpio_sdhc_inactive(int module); +static void sdhci_dma_irq(void *devid, int error, unsigned int cnt); + +void mxc_mmc_force_detect(int id) +{ + struct sdhci_host *host; + if ((id < 0) || (id >= MXC_SDHCI_NUM)) + return; + if (!mxc_fix_chips[id]) + return; + host = mxc_fix_chips[id]->hosts[0]; + if (host->detect_irq) + return; + + schedule_work(&host->cd_wq); + return; +} + +EXPORT_SYMBOL(mxc_mmc_force_detect); + +static void sdhci_dumpregs(struct sdhci_host *host) +{ + printk(KERN_INFO DRIVER_NAME + ": ============== REGISTER DUMP ==============\n"); + + printk(KERN_INFO DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", + readl(host->ioaddr + SDHCI_DMA_ADDRESS), + readl(host->ioaddr + SDHCI_HOST_VERSION)); + printk(KERN_INFO DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", + (readl(host->ioaddr + SDHCI_BLOCK_SIZE) & 0xFFFF), + (readl(host->ioaddr + SDHCI_BLOCK_COUNT) >> 16)); + printk(KERN_INFO DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", + readl(host->ioaddr + SDHCI_ARGUMENT), + readl(host->ioaddr + SDHCI_TRANSFER_MODE)); + printk(KERN_INFO DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", + readl(host->ioaddr + SDHCI_PRESENT_STATE), + readl(host->ioaddr + SDHCI_HOST_CONTROL)); + printk(KERN_INFO DRIVER_NAME ": Clock: 0x%08x\n", + readl(host->ioaddr + SDHCI_CLOCK_CONTROL)); + printk(KERN_INFO DRIVER_NAME ": Int stat: 0x%08x\n", + readl(host->ioaddr + SDHCI_INT_STATUS)); + printk(KERN_INFO DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", + readl(host->ioaddr + SDHCI_INT_ENABLE), + readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); + printk(KERN_INFO DRIVER_NAME ": Caps: 0x%08x\n", + readl(host->ioaddr + SDHCI_CAPABILITIES)); + + printk(KERN_INFO DRIVER_NAME + ": ===========================================\n"); +} + +/*****************************************************************************\ + * * + * Low level functions * + * * +\*****************************************************************************/ + +static void sdhci_reset(struct sdhci_host *host, u8 mask) +{ + unsigned long tmp; + unsigned long mask_u32; + unsigned long reg_save = 0; + + if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { + if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & + SDHCI_CARD_PRESENT)) + return; + } + + if (mask & SDHCI_RESET_ALL) + host->clock = 0; + else if (host->flags & SDHCI_CD_PRESENT) + reg_save = readl(host->ioaddr + SDHCI_HOST_CONTROL); + + tmp = readl(host->ioaddr + SDHCI_CLOCK_CONTROL) | (mask << 24); + mask_u32 = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE); + writel(tmp, host->ioaddr + SDHCI_CLOCK_CONTROL); + + /* Wait max 100 ms */ + tmp = 5000; + + /* hw clears the bit when it's done */ + while ((readl(host->ioaddr + SDHCI_CLOCK_CONTROL) >> 24) & mask) { + if (tmp == 0) { + printk(KERN_ERR "%s: Reset 0x%x never completed.\n", + mmc_hostname(host->mmc), (int)mask); + sdhci_dumpregs(host); + return; + } + tmp--; + udelay(20); + } + /* + * The INT_EN SIG_EN regs have been modified after reset. + * re-configure them ag. + */ + if (!(mask & SDHCI_RESET_ALL) && (host->flags & SDHCI_CD_PRESENT)) + writel(reg_save, host->ioaddr + SDHCI_HOST_CONTROL); + if (host->flags & SDHCI_USE_DMA) + mask_u32 &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL); + if (mxc_wml_value == 512) + writel(SDHCI_WML_128_WORDS, host->ioaddr + SDHCI_WML); + else + writel(SDHCI_WML_16_WORDS, host->ioaddr + SDHCI_WML); + writel(mask_u32 | SDHCI_INT_CARD_INT, host->ioaddr + SDHCI_INT_ENABLE); + writel(mask_u32, host->ioaddr + SDHCI_SIGNAL_ENABLE); + last_op_dir = 0; +} + +static void sdhci_init(struct sdhci_host *host) +{ + u32 intmask; + + sdhci_reset(host, SDHCI_RESET_ALL); + + intmask = SDHCI_INT_ADMA_ERROR | + SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | + SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | + SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | + SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE; + + if (cpu_is_mx50_rev(CHIP_REV_1_1) < 0 + || cpu_is_mx53_rev(CHIP_REV_2_0) < 0) + intmask |= SDHCI_INT_ACMD12ERR; + + if (host->flags & SDHCI_USE_DMA) + intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL); + /* Configure the WML rege */ + if (mxc_wml_value == 512) + writel(SDHCI_WML_128_WORDS, host->ioaddr + SDHCI_WML); + else + writel(SDHCI_WML_16_WORDS, host->ioaddr + SDHCI_WML); + writel(intmask | SDHCI_INT_CARD_INT, host->ioaddr + SDHCI_INT_ENABLE); + writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); +} + +static void sdhci_activate_led(struct sdhci_host *host) +{ + u32 ctrl; + + ctrl = readl(host->ioaddr + SDHCI_HOST_CONTROL); + ctrl |= SDHCI_CTRL_LED; + writel(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); +} + +static void sdhci_deactivate_led(struct sdhci_host *host) +{ + u32 ctrl; + + ctrl = readl(host->ioaddr + SDHCI_HOST_CONTROL); + ctrl &= ~SDHCI_CTRL_LED; + writel(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); +} + +/*****************************************************************************\ + * * + * Core functions * + * * +\*****************************************************************************/ + +static inline char *sdhci_sg_to_buffer(struct sdhci_host *host) +{ + return sg_virt(host->cur_sg); +} + +static inline int sdhci_next_sg(struct sdhci_host *host) +{ + /* + * Skip to next SG entry. + */ + host->cur_sg++; + host->num_sg--; + + /* + * Any entries left? + */ + if (host->num_sg > 0) { + host->offset = 0; + host->remain = host->cur_sg->length; + } + + return host->num_sg; +} + +static void sdhci_read_block_pio(struct sdhci_host *host) +{ + int blksize, chunk_remain; + u32 data; + char *buffer; + int size; + + DBG("PIO reading\n"); + + blksize = host->data->blksz; + chunk_remain = 0; + data = 0; + + buffer = sdhci_sg_to_buffer(host) + host->offset; + + while (blksize) { + if (chunk_remain == 0) { + data = readl(host->ioaddr + SDHCI_BUFFER); + chunk_remain = min(blksize, 4); + } + + size = min(host->remain, chunk_remain); + + chunk_remain -= size; + blksize -= size; + host->offset += size; + host->remain -= size; + + while (size) { + *buffer = data & 0xFF; + buffer++; + data >>= 8; + size--; + } + + if (host->remain == 0) { + if (sdhci_next_sg(host) == 0) { + BUG_ON(blksize != 0); + return; + } + buffer = sdhci_sg_to_buffer(host); + } + } +} + +static void sdhci_write_block_pio(struct sdhci_host *host) +{ + int blksize, chunk_remain; + u32 data; + char *buffer; + int bytes, size; + + DBG("PIO writing\n"); + + blksize = host->data->blksz; + chunk_remain = 4; + data = 0; + + bytes = 0; + buffer = sdhci_sg_to_buffer(host) + host->offset; + + while (blksize) { + size = min(host->remain, chunk_remain); + + chunk_remain -= size; + blksize -= size; + host->offset += size; + host->remain -= size; + + while (size) { + data >>= 8; + data |= (u32) *buffer << 24; + buffer++; + size--; + } + + if (chunk_remain == 0) { + writel(data, host->ioaddr + SDHCI_BUFFER); + chunk_remain = min(blksize, 4); + } + + if (host->remain == 0) { + if (sdhci_next_sg(host) == 0) { + BUG_ON(blksize != 0); + return; + } + buffer = sdhci_sg_to_buffer(host); + } + } +} + +static void sdhci_transfer_pio(struct sdhci_host *host) +{ + u32 mask; + + BUG_ON(!host->data); + + if (host->num_sg == 0) + return; + + if (host->data->flags & MMC_DATA_READ) + mask = SDHCI_DATA_AVAILABLE; + else + mask = SDHCI_SPACE_AVAILABLE; + + while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { + if (host->data->flags & MMC_DATA_READ) + sdhci_read_block_pio(host); + else + sdhci_write_block_pio(host); + + if (host->num_sg == 0) + break; + } + + DBG("PIO transfer complete.\n"); +} + +static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) +{ + u32 count; + unsigned target_timeout, current_timeout; + + WARN_ON(host->data); + + if (data == NULL) + return; + + /* Sanity checks */ + BUG_ON(data->blksz * data->blocks > 524288); + BUG_ON(data->blksz > host->mmc->max_blk_size); + BUG_ON(data->blocks > 65535); + + host->data = data; + host->data_early = 0; + + /* timeout in us */ + target_timeout = data->timeout_ns / 1000 + + data->timeout_clks / host->clock; + + /* + * Figure out needed cycles. + * We do this in steps in order to fit inside a 32 bit int. + * The first step is the minimum timeout, which will have a + * minimum resolution of 6 bits: + * (1) 2^13*1000 > 2^22, + * (2) host->timeout_clk < 2^16 + * => + * (1) / (2) > 2^6 + */ + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < target_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + /* + * Compensate for an off-by-one error in the CaFe hardware; otherwise, + * a too-small count gives us interrupt timeouts. + */ + if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) + count++; + + if (count >= 0xF) { + DBG(KERN_WARNING "%s: Too large timeout requested!\n", + mmc_hostname(host->mmc)); + count = 0xE; + } + + /* Set the max time-out value to level up the compatibility */ + count = 0xE; + + count = + (count << 16) | (readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & + 0xFFF0FFFF); + writel(count, host->ioaddr + SDHCI_CLOCK_CONTROL); + + if (host->flags & SDHCI_USE_DMA) + host->flags |= SDHCI_REQ_USE_DMA; + + if (unlikely((host->flags & SDHCI_REQ_USE_DMA) && + (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && + ((data->blksz * data->blocks) & 0x3))) { + DBG("Reverting to PIO because of transfer size (%d)\n", + data->blksz * data->blocks); + host->flags &= ~SDHCI_REQ_USE_DMA; + } + + /* + * The assumption here being that alignment is the same after + * translation to device address space. + */ + if (unlikely((host->flags & SDHCI_REQ_USE_DMA) && + (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && + (data->sg->offset & 0x3))) { + DBG("Reverting to PIO because of bad alignment\n"); + host->flags &= ~SDHCI_REQ_USE_DMA; + } + + if (cpu_is_mx25() && (data->blksz * data->blocks < 0x10)) { + host->flags &= ~SDHCI_REQ_USE_DMA; + DBG("Reverting to PIO in small data transfer.\n"); + writel(readl(host->ioaddr + SDHCI_INT_ENABLE) + | SDHCI_INT_DATA_AVAIL + | SDHCI_INT_SPACE_AVAIL, + host->ioaddr + SDHCI_INT_ENABLE); + writel(readl(host->ioaddr + SDHCI_SIGNAL_ENABLE) + | SDHCI_INT_DATA_AVAIL + | SDHCI_INT_SPACE_AVAIL, + host->ioaddr + SDHCI_SIGNAL_ENABLE); + } else if (cpu_is_mx25() && (host->flags & SDHCI_USE_DMA)) { + host->flags |= SDHCI_REQ_USE_DMA; + DBG("Reverting to DMA in large data transfer.\n"); + writel(readl(host->ioaddr + SDHCI_INT_ENABLE) + & ~(SDHCI_INT_DATA_AVAIL + | SDHCI_INT_SPACE_AVAIL), + host->ioaddr + SDHCI_INT_ENABLE); + writel(readl(host->ioaddr + SDHCI_SIGNAL_ENABLE) + & ~(SDHCI_INT_DATA_AVAIL + | SDHCI_INT_SPACE_AVAIL), + host->ioaddr + SDHCI_SIGNAL_ENABLE); + } + + if (host->flags & SDHCI_REQ_USE_DMA) { + int i; + struct scatterlist *tsg; + + host->dma_size = data->blocks * data->blksz; + count = + dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, + (data-> + flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : + DMA_TO_DEVICE); + BUG_ON(count != data->sg_len); + DBG("Configure the sg DMA, %s, len is 0x%x, count is %d\n", + (data->flags & MMC_DATA_READ) + ? "DMA_FROM_DEIVCE" : "DMA_TO_DEVICE", host->dma_size, + count); + + /* Make sure the ADMA mode is selected. */ + i = readl(host->ioaddr + SDHCI_HOST_CONTROL); + i |= SDHCI_CTRL_ADMA; + writel(i, host->ioaddr + SDHCI_HOST_CONTROL); + + tsg = data->sg; + /* ADMA mode is used, create the descriptor table */ + for (i = 0; i < count; i++) { + if (tsg->dma_address & 0xFFF) { + DBG(KERN_ERR "ADMA addr isn't 4K aligned.\n"); + DBG(KERN_ERR "0x%x\n", tsg->dma_address); + DBG(KERN_ERR "Changed to Single DMA mode.\n"); + goto Single_DMA; + } + adma_des_table[2 * i] = tsg->length << 12; + adma_des_table[2 * i] |= FSL_ADMA_DES_ATTR_SET; + adma_des_table[2 * i] |= FSL_ADMA_DES_ATTR_VALID; + adma_des_table[2 * i + 1] = tsg->dma_address; + adma_des_table[2 * i + 1] |= FSL_ADMA_DES_ATTR_TRAN; + adma_des_table[2 * i + 1] |= FSL_ADMA_DES_ATTR_VALID; + if (count == (i + 1)) + adma_des_table[2 * i + 1] |= + FSL_ADMA_DES_ATTR_END; + tsg++; + } + + /* Write the physical address to ADMA address reg */ + writel(virt_to_phys(adma_des_table), + host->ioaddr + SDHCI_ADMA_ADDRESS); + Single_DMA: + /* Rollback to the Single DMA mode */ + i = readl(host->ioaddr + SDHCI_HOST_CONTROL); + i &= ~SDHCI_CTRL_ADMA; + writel(i, host->ioaddr + SDHCI_HOST_CONTROL); + /* Single DMA mode is used */ + writel(sg_dma_address(data->sg), + host->ioaddr + SDHCI_DMA_ADDRESS); + } else if ((host->flags & SDHCI_USE_EXTERNAL_DMA) && + (data->blocks * data->blksz >= mxc_wml_value)) { + host->dma_size = data->blocks * data->blksz; + DBG("Configure the External DMA, %s, len is 0x%x\n", + (data->flags & MMC_DATA_READ) + ? "DMA_FROM_DEIVCE" : "DMA_TO_DEVICE", host->dma_size); + + if (data->blksz & 0x3) { + printk(KERN_ERR + "mxc_mci: block size not multiple of 4 bytes\n"); + } + + if (data->flags & MMC_DATA_READ) + host->dma_dir = DMA_FROM_DEVICE; + else + host->dma_dir = DMA_TO_DEVICE; + + host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, + data->sg_len, host->dma_dir); + + if (data->flags & MMC_DATA_READ) { + mxc_dma_sg_config(host->dma, data->sg, data->sg_len, + host->dma_size, MXC_DMA_MODE_READ); + } else { + mxc_dma_sg_config(host->dma, data->sg, data->sg_len, + host->dma_size, MXC_DMA_MODE_WRITE); + } + } else { + host->cur_sg = data->sg; + host->num_sg = data->sg_len; + + host->offset = 0; + host->remain = host->cur_sg->length; + } + + /* We do not handle DMA boundaries, so set it to max (512 KiB) */ + writel((data->blocks << 16) | SDHCI_MAKE_BLKSZ(0, data->blksz), + host->ioaddr + SDHCI_BLOCK_SIZE); +} + +static void sdhci_finish_data(struct sdhci_host *host) +{ + struct mmc_data *data; + u16 blocks; + + BUG_ON(!host->data); + + data = host->data; + host->data = NULL; + + if (host->flags & SDHCI_REQ_USE_DMA) { + dma_unmap_sg(&(host->chip->pdev)->dev, data->sg, data->sg_len, + (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : + DMA_TO_DEVICE); + } + if ((host->flags & SDHCI_USE_EXTERNAL_DMA) && + (host->dma_size >= mxc_wml_value) && (data != NULL)) { + dma_unmap_sg(mmc_dev(host->mmc), data->sg, + host->dma_len, host->dma_dir); + host->dma_size = 0; + } + + /* + * Controller doesn't count down when in single block mode. + */ + if (data->blocks == 1) + blocks = (data->error == 0) ? 0 : 1; + else { + blocks = readl(host->ioaddr + SDHCI_BLOCK_COUNT) >> 16; + if (cpu_is_mx50_rev(CHIP_REV_1_1) >= 1 + || cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) { + if (readl(host->ioaddr + SDHCI_VENDOR_SPEC) & 0x2) + writel(readl(host->ioaddr + SDHCI_VENDOR_SPEC) + & ~0x2, + host->ioaddr + SDHCI_VENDOR_SPEC); + } + } + data->bytes_xfered = data->blksz * data->blocks; + + if ((data->stop) && !(cpu_is_mx50_rev(CHIP_REV_1_1) < 0 + || cpu_is_mx53_rev(CHIP_REV_2_0) < 0)) { + /* + * The controller needs a reset of internal state machines + * upon error conditions. + */ + if (data->error) { + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + } + + sdhci_send_command(host, data->stop); + } else + queue_work(host->workqueue, &host->finish_wq); +} + +static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) +{ + int flags; + u32 tmp, mask, mode = 0; + unsigned long timeout; + + DBG("sdhci_send_command 0x%x is starting...\n", cmd->opcode); + WARN_ON(host->cmd); + + /* Wait max 10 ms */ + timeout = 500; + + mask = SDHCI_CMD_INHIBIT; + if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) + mask |= SDHCI_DATA_INHIBIT; + + /* We shouldn't wait for data inihibit for stop commands, even + though they might use busy signaling */ + if (host->mrq->data && (cmd == host->mrq->data->stop)) + mask &= ~SDHCI_DATA_INHIBIT; + + while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { + if (timeout == 0) { + printk(KERN_ERR "%s: Controller never released " + "inhibit bit(s).\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + cmd->error = -EIO; + queue_work(host->workqueue, &host->finish_wq); + return; + } + timeout--; + udelay(20); + } + + mod_timer(&host->timer, jiffies + 10 * HZ); + + host->cmd = cmd; + + sdhci_prepare_data(host, cmd->data); + + writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); + + /* Set up the transfer mode */ + if (cmd->data != NULL) { + mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_DPSEL; + if (cmd->data->blocks > 1) { + mode |= SDHCI_TRNS_MULTI; + if (cpu_is_mx50_rev(CHIP_REV_1_1) < 0 + || cpu_is_mx53_rev(CHIP_REV_2_0) < 0) { + /* Fix multi-blk operations no INT bug + * by SW workaround. + */ + mode |= SDHCI_TRNS_ACMD12; + if (cmd->opcode == 0x35) { + tmp = readl(host->ioaddr + + SDHCI_INT_ENABLE); + tmp &= ~SDHCI_INT_ACMD12ERR; + writel(tmp, host->ioaddr + + SDHCI_INT_ENABLE); + } else { + tmp = readl(host->ioaddr + + SDHCI_INT_ENABLE); + tmp |= SDHCI_INT_ACMD12ERR; + writel(tmp, host->ioaddr + + SDHCI_INT_ENABLE); + } + } else if (cpu_is_mx50_rev(CHIP_REV_1_1) >= 1 + || cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) { + /* Fix SDIO read no INT bug + * set bit1 of Vendor Spec Registor + */ + if (cmd->opcode == 0x35 && (cmd->data->flags + & MMC_DATA_READ)) + timeout = readl(host->ioaddr + + SDHCI_VENDOR_SPEC); + timeout |= 0x2; + writel(timeout, host->ioaddr + + SDHCI_VENDOR_SPEC); + } + } + if (cmd->data->flags & MMC_DATA_READ) + mode |= SDHCI_TRNS_READ; + else + mode &= ~SDHCI_TRNS_READ; + if (host->flags & SDHCI_REQ_USE_DMA) + mode |= SDHCI_TRNS_DMA; + if (host->flags & SDHCI_USE_EXTERNAL_DMA) + DBG("Prepare data completely in %s transfer mode.\n", + "EXTTERNAL DMA"); + } + + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { + printk(KERN_ERR "%s: Unsupported response type!\n", + mmc_hostname(host->mmc)); + cmd->error = -EINVAL; + queue_work(host->workqueue, &host->finish_wq); + return; + } + + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags = SDHCI_CMD_RESP_SHORT_BUSY; + else + flags = SDHCI_CMD_RESP_SHORT; + + if (cmd->flags & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + if (cmd->data) + flags |= SDHCI_CMD_DATA; + + mode |= SDHCI_MAKE_CMD(cmd->opcode, flags); + if (host->mmc->ios.bus_width & MMC_BUS_WIDTH_DDR) { + /* Eanble the DDR mode */ + mode |= SDHCI_TRNS_DDR_EN; + } else + mode &= ~SDHCI_TRNS_DDR_EN; + /* Configure the cmd type for cmd12 */ + if (cmd->opcode == 12) + mode |= SDHCI_TRNS_ABORTCMD; + /* + * Some delay is mandatory required between CMD6 and CMD13 after + * switch to DDR mode when Sandisk eMMC44 soldered on SMD board + */ + if (cmd->opcode == 0xd) + mdelay(5); + DBG("Complete sending cmd, transfer mode would be 0x%x.\n", mode); + writel(mode, host->ioaddr + SDHCI_TRANSFER_MODE); +} + +static void sdhci_finish_command(struct sdhci_host *host) +{ + int i; + + BUG_ON(host->cmd == NULL); + + if (host->cmd->flags & MMC_RSP_PRESENT) { + if (host->cmd->flags & MMC_RSP_136) { + /* CRC is stripped so we need to do some shifting. */ + for (i = 0; i < 4; i++) { + host->cmd->resp[i] = readl(host->ioaddr + + SDHCI_RESPONSE + (3 - + i) + * 4) << 8; + if (i != 3) + host->cmd->resp[i] |= + readb(host->ioaddr + + SDHCI_RESPONSE + (3 - i) * 4 - + 1); + } + } else { + host->cmd->resp[0] = + readl(host->ioaddr + SDHCI_RESPONSE); + } + } + + host->cmd->error = 0; + + if (host->data && host->data_early) + sdhci_finish_data(host); + + if (!host->cmd->data) + queue_work(host->workqueue, &host->finish_wq); + + host->cmd = NULL; +} + +static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +{ + /*This variable holds the value of clock divider, prescaler */ + int div = 0, prescaler = 0; + int clk_rate = 0; + u32 clk; + unsigned long timeout; + struct mmc_ios ios = host->mmc->ios; + + if (clock == 0) { + host->clock = 0; + return; + } + + if (clock == host->clock && !(ios.bus_width & MMC_BUS_WIDTH_DDR)) + return; + + clk_rate = clk_get_rate(host->clk); + clk = readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & ~SDHCI_CLOCK_MASK; + if (cpu_is_mx53() || cpu_is_mx50()) + writel(clk | SDHCI_CLOCK_SDCLKFS1, + host->ioaddr + SDHCI_CLOCK_CONTROL); + else + writel(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); + + if (clock == host->min_clk) + prescaler = 16; + else if (cpu_is_mx53() || cpu_is_mx50()) + prescaler = 1; + else + prescaler = 0; + while (prescaler <= 0x80) { + for (div = 0; div <= 0xF; div++) { + int x; + if (prescaler != 0) + x = (clk_rate / (div + 1)) / (prescaler * 2); + else + x = clk_rate / (div + 1); + + DBG("x=%d, clock=%d %d\n", x, clock, div); + if (x <= clock) + break; + } + if (div < 0x10) + break; + if (prescaler == 0) + prescaler = 1; + else + prescaler <<= 1; + } + DBG("prescaler = 0x%x, divider = 0x%x\n", prescaler, div); + clk |= (prescaler << 8) | (div << 4); + + /* Disable clock auto gate to get better compatibility */ + clk |= SDHCI_CLOCK_PER_EN | SDHCI_CLOCK_HLK_EN + | SDHCI_CLOCK_IPG_EN; + + /* Configure the clock delay line */ + if ((host->plat_data->vendor_ver >= ESDHC_VENDOR_V3) + && host->plat_data->dll_override_en) + writel((host->plat_data->dll_delay_cells << 10) + | DLL_CTRL_SLV_OVERRIDE, + host->ioaddr + SDHCI_DLL_CONTROL); + + /* Configure the clock control register */ + clk |= + (readl(host->ioaddr + SDHCI_CLOCK_CONTROL) & (~SDHCI_CLOCK_MASK)); + if (host->plat_data->vendor_ver < ESDHC_VENDOR_V22) + writel(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); + else + writel(clk | SDHCI_CLOCK_SD_EN, + host->ioaddr + SDHCI_CLOCK_CONTROL); + + /* Wait max 10 ms */ + timeout = 500; + while (timeout > 0) { + timeout--; + udelay(20); + } + + if (prescaler != 0) + host->clock = (clk_rate / (div + 1)) / (prescaler * 2); + else + host->clock = clk_rate / (div + 1); +} + +static void sdhci_set_power(struct sdhci_host *host, unsigned short power) +{ + int voltage = 0; + + /* There is no PWR CTL REG */ + if (host->power == power) + return; + + if (host->regulator_mmc) { + if (power == (unsigned short)-1) { + regulator_disable(host->regulator_mmc); + DBG("mmc power off\n"); + } else { + if (power == 7) + voltage = 1800000; + else if (power >= 8) + voltage = 2000000 + (power - 8) * 100000; + regulator_set_voltage(host->regulator_mmc, + voltage, voltage); + + if (regulator_enable(host->regulator_mmc) == 0) { + DBG("mmc power on\n"); + msleep(1); + } + } + } + + host->power = power; +} + +/*****************************************************************************\ + * * + * MMC callbacks * + * * +\*****************************************************************************/ + +static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host; + unsigned long flags; + + host = mmc_priv(mmc); + + /* Enable the clock */ + if (!host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + + spin_lock_irqsave(&host->lock, flags); + + WARN_ON(host->mrq != NULL); + + sdhci_activate_led(host); + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) { + if (mrq->cmd && mrq->data) { + if (mrq->data->flags & MMC_DATA_READ) + last_op_dir = 1; + else { + if (last_op_dir) + sdhci_reset(host, + SDHCI_RESET_CMD | + SDHCI_RESET_DATA); + } + } + } + + if (host->flags & SDHCI_USE_EXTERNAL_DMA) + spin_unlock_irqrestore(&host->lock, flags); + + host->mrq = mrq; + if (!(host->flags & SDHCI_CD_PRESENT)) { + host->mrq->cmd->error = -ENOMEDIUM; + queue_work(host->workqueue, &host->finish_wq); + } else + sdhci_send_command(host, mrq->cmd); + + if (!(host->flags & SDHCI_USE_EXTERNAL_DMA)) + spin_unlock_irqrestore(&host->lock, flags); + + mmiowb(); +} + +static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host; + unsigned long flags; + u32 tmp; + mxc_dma_device_t dev_id = 0; + + DBG("%s: clock %u, bus %u, power %u, vdd %u\n", DRIVER_NAME, + ios->clock, ios->bus_width, ios->power_mode, ios->vdd); + + host = mmc_priv(mmc); + + if (ios->clock && !host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + + /* Configure the External DMA mode */ + if (host->flags & SDHCI_USE_EXTERNAL_DMA) { + host->dma_dir = DMA_NONE; + if (mmc->ios.bus_width != host->mode) { + mxc_dma_free(host->dma); + if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) { + if (host->id == 0) + dev_id = MXC_DMA_MMC1_WIDTH_4; + else + dev_id = MXC_DMA_MMC2_WIDTH_4; + } else { + if (host->id == 0) + dev_id = MXC_DMA_MMC1_WIDTH_1; + else + dev_id = MXC_DMA_MMC2_WIDTH_1; + } + host->dma = mxc_dma_request(dev_id, "MXC MMC"); + if (host->dma < 0) + DBG("Cannot allocate MMC DMA channel\n"); + mxc_dma_callback_set(host->dma, sdhci_dma_irq, + (void *)host); + /* Configure the WML rege */ + if (mxc_wml_value == 512) + writel(SDHCI_WML_128_WORDS, + host->ioaddr + SDHCI_WML); + else + writel(SDHCI_WML_16_WORDS, + host->ioaddr + SDHCI_WML); + } + } + + host->mode = mmc->ios.bus_width; + + spin_lock_irqsave(&host->lock, flags); + + /* + * Reset the chip on each power off. + * Should clear out any weird states. + */ + if (ios->power_mode == MMC_POWER_OFF) { + writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); + sdhci_init(host); + } + + sdhci_set_clock(host, ios->clock); + + spin_unlock_irqrestore(&host->lock, flags); + if (ios->power_mode == MMC_POWER_OFF) + sdhci_set_power(host, -1); + else { + sdhci_set_power(host, ios->vdd); + if (!readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)) { + tmp = readl(host->ioaddr + SDHCI_INT_ENABLE); + if (host->sdio_enable) + writel(tmp, host->ioaddr + SDHCI_SIGNAL_ENABLE); + else + writel(tmp & ~SDHCI_INT_CARD_INT, + host->ioaddr + SDHCI_SIGNAL_ENABLE); + } + } + + spin_lock_irqsave(&host->lock, flags); + tmp = readl(host->ioaddr + SDHCI_HOST_CONTROL); + + if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_4) { + tmp &= ~SDHCI_CTRL_8BITBUS; + tmp |= SDHCI_CTRL_4BITBUS; + } else if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_8) { + tmp &= ~SDHCI_CTRL_4BITBUS; + tmp |= SDHCI_CTRL_8BITBUS; + } else if (ios->bus_width == MMC_BUS_WIDTH_1) { + tmp &= ~SDHCI_CTRL_4BITBUS; + tmp &= ~SDHCI_CTRL_8BITBUS; + } + + if (host->flags & SDHCI_USE_DMA) + tmp |= SDHCI_CTRL_ADMA; + + writel(tmp, host->ioaddr + SDHCI_HOST_CONTROL); + + /* + * Some (ENE) controllers go apeshit on some ios operation, + * signalling timeout and CRC errors even on CMD0. Resetting + * it on each ios seems to solve the problem. + */ + if (host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) + sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); +} + +static int sdhci_get_ro(struct mmc_host *mmc) +{ + struct sdhci_host *host; + + host = mmc_priv(mmc); + + if (host->plat_data->wp_status) + return host->plat_data->wp_status(mmc->parent); + else + return 0; +} + +static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct sdhci_host *host; + unsigned long flags; + u32 ier, prot, present; + + host = mmc_priv(mmc); + + /* Enable the clock */ + if (!host->plat_data->clk_flg) { + clk_enable(host->clk); + host->plat_data->clk_flg = 1; + } + + spin_lock_irqsave(&host->lock, flags); + + if (enable) { + if (host->sdio_enable++) + goto exit_unlock; + } else { + if (--(host->sdio_enable)) + goto exit_unlock; + } + + ier = readl(host->ioaddr + SDHCI_INT_ENABLE); + prot = readl(host->ioaddr + SDHCI_HOST_CONTROL); + + if (enable) { + ier |= SDHCI_INT_CARD_INT; + prot |= SDHCI_CTRL_D3CD; + present = readl(host->ioaddr + SDHCI_PRESENT_STATE); + if ((present & SDHCI_CARD_INT_MASK) != SDHCI_CARD_INT_ID) + writel(SDHCI_INT_CARD_INT, + host->ioaddr + SDHCI_INT_STATUS); + } else { + ier &= ~SDHCI_INT_CARD_INT; + prot &= ~SDHCI_CTRL_D3CD; + } + + writel(prot, host->ioaddr + SDHCI_HOST_CONTROL); + writel(ier, host->ioaddr + SDHCI_INT_ENABLE); + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); + + /* + * Using D3CD to manually driver the HW to re-sample the SDIO interrupt + * on bus one more time to guarantee the SDIO interrupt signal sent + * from card during the interrupt signal disabled period will not + * be lost. + */ + prot |= SDHCI_CTRL_CDSS; + writel(prot, host->ioaddr + SDHCI_HOST_CONTROL); + prot &= ~SDHCI_CTRL_D3CD; + writel(prot, host->ioaddr + SDHCI_HOST_CONTROL); + prot |= SDHCI_CTRL_D3CD; + writel(prot, host->ioaddr + SDHCI_HOST_CONTROL); + + mmiowb(); + exit_unlock: + spin_unlock_irqrestore(&host->lock, flags); +} + +static const struct mmc_host_ops sdhci_ops = { + .request = sdhci_request, + .set_ios = sdhci_set_ios, + .get_ro = sdhci_get_ro, + .enable_sdio_irq = sdhci_enable_sdio_irq, +}; + +/*****************************************************************************\ + * * + * Tasklets * + * * +\*****************************************************************************/ + +static void sdhci_tasklet_card(unsigned long param) +{ + struct sdhci_host *host; + unsigned long flags; + unsigned int cd_status = 0; + + host = (struct sdhci_host *)param; + + if (host->flags & SDHCI_CD_PRESENT) + host->flags &= ~SDHCI_CD_PRESENT; + else + host->flags |= SDHCI_CD_PRESENT; + /* Detect there is a card in slot or not */ + DBG("cd_status=%d %s\n", cd_status, + (host->flags & SDHCI_CD_PRESENT) ? "inserted" : "removed"); + + spin_lock_irqsave(&host->lock, flags); + + if (!(host->flags & SDHCI_CD_PRESENT)) { + if (host->mrq) { + printk(KERN_ERR "%s: Card removed during transfer!\n", + mmc_hostname(host->mmc)); + printk(KERN_ERR "%s: Resetting controller.\n", + mmc_hostname(host->mmc)); + + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + + host->mrq->cmd->error = -ENOMEDIUM; + queue_work(host->workqueue, &host->finish_wq); + } + } + + spin_unlock_irqrestore(&host->lock, flags); + + mmc_detect_change(host->mmc, msecs_to_jiffies(200)); +} + +static void sdhci_finish_worker(struct work_struct *work) +{ + struct sdhci_host *host = container_of(work, struct sdhci_host, + finish_wq); + unsigned long flags; + int req_done; + struct mmc_request *mrq; + + spin_lock_irqsave(&host->lock, flags); + + del_timer(&host->timer); + + mrq = host->mrq; + + /* + * The controller needs a reset of internal state machines + * upon error conditions. + */ + if (mrq->cmd->error || + (mrq->data && (mrq->data->error || + (mrq->data->stop && mrq->data->stop->error))) || + (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { + + /* Some controllers need this kick or reset won't work here */ + if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { + unsigned int clock; + + /* This is to force an update */ + clock = host->clock; + host->clock = 0; + sdhci_set_clock(host, clock); + } + + /* Spec says we should do both at the same time, but Ricoh + controllers do not like that. */ + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + } + + host->mrq = NULL; + host->cmd = NULL; + host->data = NULL; + + sdhci_deactivate_led(host); + + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); + + /* Stop the clock when the req is done */ + req_done = !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & + (SDHCI_DATA_ACTIVE | SDHCI_DOING_WRITE | SDHCI_DOING_READ)); + if (req_done && host->plat_data->clk_flg && + !(host->plat_data->clk_always_on) && + !(host->mmc->card && mmc_card_sdio(host->mmc->card))) { + clk_disable(host->clk); + host->plat_data->clk_flg = 0; + } + + mmc_request_done(host->mmc, mrq); +} + +static void sdhci_timeout_timer(unsigned long data) +{ + struct sdhci_host *host; + unsigned long tmp, flags; + + host = (struct sdhci_host *)data; + + spin_lock_irqsave(&host->lock, flags); + + if (host->mrq) { + printk(KERN_ERR "%s: Timeout waiting for hardware " + "interrupt.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + + if (host->data) { + host->data->error = -ETIMEDOUT; + sdhci_finish_data(host); + } else { + if (host->cmd) + host->cmd->error = -ETIMEDOUT; + else + host->mrq->cmd->error = -ETIMEDOUT; + + queue_work(host->workqueue, &host->finish_wq); + } + + if (!readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)) { + printk(KERN_ERR "%s, ERROR SIG_INT is 0.\n", __func__); + tmp = readl(host->ioaddr + SDHCI_INT_ENABLE); + if (host->sdio_enable) + writel(tmp, host->ioaddr + SDHCI_SIGNAL_ENABLE); + else + writel(tmp & ~SDHCI_INT_CARD_INT, + host->ioaddr + SDHCI_SIGNAL_ENABLE); + if (!host->plat_data->status(host->mmc->parent)) + schedule_work(&host->cd_wq); + } + } + + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); +} + +static void sdhci_cd_timer(unsigned long data) +{ + struct sdhci_host *host; + + host = (struct sdhci_host *)data; + host->flags |= SDHCI_CD_TIMEOUT; + schedule_work(&host->cd_wq); +} + +/*****************************************************************************\ + * * + * Interrupt handling * + * * +\*****************************************************************************/ + +static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) +{ + BUG_ON(intmask == 0); + + if (!host->cmd) { + printk(KERN_ERR "%s: Got command interrupt 0x%08x even " + "though no command operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + sdhci_dumpregs(host); + return; + } + + if (intmask & SDHCI_INT_TIMEOUT) + host->cmd->error = -ETIMEDOUT; + else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | + SDHCI_INT_INDEX)) + host->cmd->error = -EILSEQ; + + if (cpu_is_mx50_rev(CHIP_REV_1_1) < 0 + || cpu_is_mx53_rev(CHIP_REV_2_0) < 0) { + if (intmask & SDHCI_INT_ACMD12ERR) { + int tmp = 0; + tmp = readl(host->ioaddr + SDHCI_ACMD12_ERR); + if (tmp & (SDHCI_ACMD12_ERR_CE | SDHCI_ACMD12_ERR_IE | + SDHCI_ACMD12_ERR_EBE)) + host->cmd->error = -EILSEQ; + else if (tmp & SDHCI_ACMD12_ERR_TOE) + host->cmd->error = -ETIMEDOUT; + } + } + + if (host->cmd->error) + queue_work(host->workqueue, &host->finish_wq); + else if (intmask & SDHCI_INT_RESPONSE) + sdhci_finish_command(host); +} + +static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) +{ + u32 intsave = 0; + + BUG_ON(intmask == 0); + + if (!host->data) { + /* + * A data end interrupt is sent together with the response + * for the stop command. + */ + if (intmask & SDHCI_INT_DATA_END) + return; + + printk(KERN_ERR "%s: Got data interrupt 0x%08x even " + "though no data operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + sdhci_dumpregs(host); + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + return; + } + + /* Mask the INT */ + intsave = readl(host->ioaddr + SDHCI_INT_ENABLE); + writel(intsave & (~(intmask & SDHCI_INT_DATA_RE_MASK)), + host->ioaddr + SDHCI_INT_ENABLE); + + if (intmask & SDHCI_INT_DATA_TIMEOUT) + host->data->error = -ETIMEDOUT; + else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) + host->data->error = -EILSEQ; + + if (host->data->error) + sdhci_finish_data(host); + else { + if ((host->flags & SDHCI_USE_EXTERNAL_DMA) && + (host->dma_size >= mxc_wml_value)) { + /* Use DMA if transfer size is greater than fifo size */ + if (intmask & (SDHCI_INT_DATA_AVAIL | + SDHCI_INT_SPACE_AVAIL)) { + intsave &= ~SDHCI_INT_DATA_RE_MASK; + if (mxc_dma_enable(host->dma) < 0) { + printk(KERN_ERR "ENABLE SDMA ERR.\n"); + intsave |= SDHCI_INT_DATA_RE_MASK; + } + } + } else { + if (intmask & (SDHCI_INT_DATA_AVAIL | + SDHCI_INT_SPACE_AVAIL)) + sdhci_transfer_pio(host); + } + + /* + * We currently don't do anything fancy with DMA + * boundaries, but as we can't disable the feature + * we need to at least restart the transfer. + */ + if ((intmask & SDHCI_INT_DMA_END) && + (!(intmask & SDHCI_INT_DATA_END))) + writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS), + host->ioaddr + SDHCI_DMA_ADDRESS); + + if (intmask & SDHCI_INT_DATA_END) { + if (host->cmd) { + /* + * Data managed to finish before the + * command completed. Make sure we do + * things in the proper order. + */ + host->data_early = 1; + } else { + + if (host->plat_data->vendor_ver + < ESDHC_VENDOR_V22) { + /* + * There are the DATA END INT when + * writing is not complete. Double + * check on it. TO2 has been fixed it. + */ + intmask = readl(host->ioaddr + + SDHCI_PRESENT_STATE); + if (intmask & SDHCI_DATA_ACTIVE) + goto data_irq_out; + } + sdhci_finish_data(host); + } + } + } + data_irq_out: + /* Enable the INT */ + writel(intsave, host->ioaddr + SDHCI_INT_ENABLE); +} + +/*! +* This function is called by DMA Interrupt Service Routine to indicate +* requested DMA transfer is completed. +* +* @param devid pointer to device specific structure +* @param error any DMA error +* @param cnt amount of data that was transferred +*/ +static void sdhci_dma_irq(void *devid, int error, unsigned int cnt) +{ + u32 intsave = 0; + int ret; + struct sdhci_host *host = devid; + + DBG("%s: error: %d Transferred bytes:%d\n", DRIVER_NAME, error, cnt); + if (host->flags & SDHCI_USE_EXTERNAL_DMA) { + /* + * Stop the DMA transfer here, the data_irq would be called + * to process the others + */ + ret = mxc_dma_disable(host->dma); + if (ret < 0) + printk(KERN_ERR "Disable dma channel err %d\n", ret); + + if (error) { + DBG("Error in DMA transfer\n"); + return; + } + intsave = readl(host->ioaddr + SDHCI_INT_ENABLE); + intsave |= SDHCI_INT_DATA_RE_MASK; + writel(intsave, host->ioaddr + SDHCI_INT_ENABLE); + } +} + +/* woke queue handler func */ +static void esdhc_cd_callback(struct work_struct *work) +{ + unsigned long flags; + unsigned int cd_status = 0; + struct sdhci_host *host = container_of(work, struct sdhci_host, cd_wq); + + do { + if (host->detect_irq == 0) + break; + cd_status = host->plat_data->status(host->mmc->parent); + if (cd_status) + set_irq_type(host->detect_irq, IRQF_TRIGGER_FALLING); + else + set_irq_type(host->detect_irq, IRQF_TRIGGER_RISING); + } while (cd_status != host->plat_data->status(host->mmc->parent)); + + cd_status = host->plat_data->status(host->mmc->parent); + + DBG("cd_status=%d %s\n", cd_status, cd_status ? "removed" : "inserted"); + /* If there is no card, call the card detection func + * immediately. */ + if (!cd_status) { + /* If there is a card in the slot, the timer is start + * to work. Then the card detection would be carried + * after the timer is timeout. + * */ + if (host->flags & SDHCI_CD_TIMEOUT) + host->flags &= ~SDHCI_CD_TIMEOUT; + else { + mod_timer(&host->cd_timer, jiffies + HZ / 4); + return; + } + } + + cd_status = host->plat_data->status(host->mmc->parent); + if (cd_status) + host->flags &= ~SDHCI_CD_PRESENT; + else + host->flags |= SDHCI_CD_PRESENT; + /* Detect there is a card in slot or not */ + DBG("cd_status=%d %s\n", cd_status, + (host->flags & SDHCI_CD_PRESENT) ? "inserted" : "removed"); + + spin_lock_irqsave(&host->lock, flags); + + if (!(host->flags & SDHCI_CD_PRESENT)) { + printk(KERN_INFO + "%s: Card removed and resetting controller.\n", + mmc_hostname(host->mmc)); + if (host->mrq) { + struct mmc_data *data; + data = host->data; + host->data = NULL; + + printk(KERN_ERR + "%s: Card removed during transfer!\n", + mmc_hostname(host->mmc)); + printk(KERN_ERR + "%s: Resetting controller.\n", + mmc_hostname(host->mmc)); + + if ((host->flags & SDHCI_USE_EXTERNAL_DMA) && + (data != NULL)) { + dma_unmap_sg(mmc_dev(host->mmc), data->sg, + host->dma_len, host->dma_dir); + host->dma_size = 0; + } + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + + host->mrq->cmd->error = -ENOMEDIUM; + queue_work(host->workqueue, &host->finish_wq); + } + + if (host->init_flag > 0) + /* The initialization of sdhc controller has been + * done in the resume func */ + host->init_flag--; + else + sdhci_init(host); + } + + spin_unlock_irqrestore(&host->lock, flags); + + if (host->flags & SDHCI_CD_PRESENT) { + del_timer(&host->cd_timer); + mmc_detect_change(host->mmc, msecs_to_jiffies(100)); + } else + mmc_detect_change(host->mmc, 0); +} + +/*! +* Card detection interrupt service routine registered to handle +* the SDHC interrupts. This interrupt routine handles card +* insertion and card removal interrupts. +* +* @param irq the interrupt number +* @param devid driver private data +* +* @return The function returns \b IRQ_RETVAL(1) +*/ +static irqreturn_t sdhci_cd_irq(int irq, void *dev_id) +{ + struct sdhci_host *host = dev_id; + + schedule_work(&host->cd_wq); + + return IRQ_HANDLED; +} + +static irqreturn_t sdhci_irq(int irq, void *dev_id) +{ + irqreturn_t result; + struct sdhci_host *host = dev_id; + u32 intmask; + int cardint = 0; + + spin_lock(&host->lock); + + intmask = readl(host->ioaddr + SDHCI_INT_STATUS); + + if (!intmask || intmask == 0xffffffff) { + result = IRQ_NONE; + goto out; + } + + DBG("*** %s got interrupt: 0x%08x\n", mmc_hostname(host->mmc), intmask); + + if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + writel(intmask & + (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), + host->ioaddr + SDHCI_INT_STATUS); + tasklet_schedule(&host->card_tasklet); + } + + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); + + if (intmask & SDHCI_INT_CMD_MASK) { + writel(intmask & SDHCI_INT_CMD_MASK, + host->ioaddr + SDHCI_INT_STATUS); + sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); + } + + if (intmask & SDHCI_INT_DATA_MASK) { + writel(intmask & SDHCI_INT_DATA_MASK, + host->ioaddr + SDHCI_INT_STATUS); + if (cpu_is_mx35_rev(CHIP_REV_2_0) < 0) { + if (! + (readl(host->ioaddr + SDHCI_TRANSFER_MODE) & + SDHCI_TRNS_READ)) + intmask &= ~SDHCI_INT_DATA_END_BIT; + } + if (intmask & SDHCI_INT_DATA_MASK) + sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); + } + + intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); + + intmask &= ~SDHCI_INT_ERROR; + + if (intmask & SDHCI_INT_BUS_POWER) { + printk(KERN_ERR "%s: Card is consuming too much power!\n", + mmc_hostname(host->mmc)); + writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); + } + + intmask &= ~SDHCI_INT_BUS_POWER; + + if (intmask & SDHCI_INT_CARD_INT) + cardint = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE) & + SDHCI_INT_CARD_INT; + + intmask &= ~SDHCI_INT_CARD_INT; + + if (intmask) { + printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", + mmc_hostname(host->mmc), intmask); + sdhci_dumpregs(host); + + writel(intmask, host->ioaddr + SDHCI_INT_STATUS); + } + + result = IRQ_HANDLED; + + mmiowb(); + out: + spin_unlock(&host->lock); + + /* + * We have to delay this as it calls back into the driver. + */ + if (cardint) + mmc_signal_sdio_irq(host->mmc); + + return result; +} + +/*****************************************************************************\ + * * + * Suspend/resume * + * * +\*****************************************************************************/ + +#ifdef CONFIG_PM + +static int sdhci_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct sdhci_chip *chip; + int i, ret; + + chip = dev_get_drvdata(&pdev->dev); + if (!chip) + return 0; + + DBG("Suspending...\n"); + + for (i = 0; i < chip->num_slots; i++) { + if (!chip->hosts[i]) + continue; + ret = mmc_suspend_host(chip->hosts[i]->mmc); + if (ret) { + for (i--; i >= 0; i--) + mmc_resume_host(chip->hosts[i]->mmc); + return ret; + } + } + + for (i = 0; i < chip->num_slots; i++) { + if (!chip->hosts[i]) + continue; + free_irq(chip->hosts[i]->irq, chip->hosts[i]); + } + + return 0; +} + +static int sdhci_resume(struct platform_device *pdev) +{ + struct sdhci_chip *chip; + int i, ret; + + chip = dev_get_drvdata(&pdev->dev); + if (!chip) + return 0; + + DBG("Resuming...\n"); + + for (i = 0; i < chip->num_slots; i++) { + if (!chip->hosts[i]) + continue; + ret = request_irq(chip->hosts[i]->irq, sdhci_irq, + IRQF_SHARED, + mmc_hostname(chip->hosts[i]->mmc), + chip->hosts[i]); + if (ret) + return ret; + sdhci_init(chip->hosts[i]); + chip->hosts[i]->init_flag = 2; + mmiowb(); + ret = mmc_resume_host(chip->hosts[i]->mmc); + if (ret) + return ret; + } + + return 0; +} + +#else /* CONFIG_PM */ + +#define sdhci_suspend NULL +#define sdhci_resume NULL + +#endif /* CONFIG_PM */ + +/*****************************************************************************\ + * * + * Device probing/removal * + * * +\*****************************************************************************/ + +static int __devinit sdhci_probe_slot(struct platform_device + *pdev, int slot) +{ + struct mxc_mmc_platform_data *mmc_plat = pdev->dev.platform_data; + int ret = 0; + unsigned int version, caps; + struct sdhci_chip *chip; + struct mmc_host *mmc; + struct sdhci_host *host; + mxc_dma_device_t dev_id = 0; + + if (!mmc_plat) + return -EINVAL; + + chip = dev_get_drvdata(&pdev->dev); + BUG_ON(!chip); + + mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); + if (!mmc) + return -ENOMEM; + + host = mmc_priv(mmc); + host->mmc = mmc; + host->id = pdev->id; + host->dma = -1; + host->plat_data = mmc_plat; + if (!host->plat_data) { + ret = -EINVAL; + goto out0; + } + + host->chip = chip; + chip->hosts[slot] = host; + + /* Get pwr supply for eSDHC */ + if (NULL != mmc_plat->power_mmc) { + host->regulator_mmc = + regulator_get(&pdev->dev, mmc_plat->power_mmc); + if (IS_ERR(host->regulator_mmc)) { + ret = PTR_ERR(host->regulator_mmc); + goto out1; + } + if (regulator_enable(host->regulator_mmc) == 0) { + DBG("mmc power on\n"); + msleep(1); + } + } + + /* Active the eSDHC bus */ + gpio_sdhc_active(pdev->id); + + /* Get the SDHC clock from clock system APIs */ + host->clk = clk_get(&pdev->dev, mmc_plat->clock_mmc); + if (NULL == host->clk) { + printk(KERN_ERR "MXC MMC can't get clock.\n"); + goto out1; + } + DBG("SDHC:%d clock:%lu\n", pdev->id, clk_get_rate(host->clk)); + + host->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!host->res) { + ret = -ENOMEM; + goto out2; + } + host->irq = platform_get_irq(pdev, 0); + if (!host->irq) { + ret = -ENOMEM; + goto out2; + } + host->detect_irq = platform_get_irq(pdev, 1); + if (!host->detect_irq) { + if (mmc_plat->card_inserted_state) + host->flags |= SDHCI_CD_PRESENT; + else + host->flags &= ~SDHCI_CD_PRESENT; + if ((pdev->id >= 0) && (pdev->id < MXC_SDHCI_NUM)) + mxc_fix_chips[pdev->id] = chip; + goto no_detect_irq; + } + + do { + ret = host->plat_data->status(host->mmc->parent); + if (ret) + set_irq_type(host->detect_irq, IRQF_TRIGGER_FALLING); + else + set_irq_type(host->detect_irq, IRQF_TRIGGER_RISING); + } while (ret != host->plat_data->status(host->mmc->parent)); + + ret = host->plat_data->status(host->mmc->parent); + if (ret) + host->flags &= ~SDHCI_CD_PRESENT; + else + host->flags |= SDHCI_CD_PRESENT; + + no_detect_irq: + DBG("slot %d at 0x%x, irq %d \n", slot, host->res->start, host->irq); + if (!request_mem_region(host->res->start, + host->res->end - + host->res->start + 1, pdev->name)) { + printk(KERN_ERR "request_mem_region failed\n"); + ret = -ENOMEM; + goto out2; + } + host->ioaddr = (void *)ioremap(host->res->start, host->res->end - + host->res->start + 1); + if (!host->ioaddr) { + ret = -ENOMEM; + goto out3; + } + + sdhci_reset(host, SDHCI_RESET_ALL); + + version = readl(host->ioaddr + SDHCI_HOST_VERSION); + host->plat_data->vendor_ver = (version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT; + version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; + if (version != 1) { + printk(KERN_ERR "%s: Unknown controller version (%d). " + "You may experience problems.\n", mmc_hostname(mmc), + version); + } + + caps = readl(host->ioaddr + SDHCI_CAPABILITIES); + + if (chip->quirks & SDHCI_QUIRK_FORCE_DMA) + host->flags |= SDHCI_USE_DMA; + else if (!(caps & SDHCI_CAN_DO_DMA)) + DBG("Controller doesn't have DMA capability\n"); + else if (chip-> + quirks & (SDHCI_QUIRK_INTERNAL_ADVANCED_DMA | + SDHCI_QUIRK_INTERNAL_SIMPLE_DMA)) + host->flags |= SDHCI_USE_DMA; + else if (chip->quirks & (SDHCI_QUIRK_EXTERNAL_DMA_MODE)) + host->flags |= SDHCI_USE_EXTERNAL_DMA; + else + host->flags &= ~SDHCI_USE_DMA; + + /* + * These definitions of eSDHC are not compatible with the SD Host + * Controller Spec v2.0 + */ + host->min_clk = mmc_plat->min_clk; + host->max_clk = mmc_plat->max_clk; + host->timeout_clk = 1024 * 1000; /* Just set the value temply. */ + + /* + * Set host parameters. + */ + mmc->ops = &sdhci_ops; + mmc->f_min = host->min_clk; + mmc->f_max = host->max_clk; + mmc->caps = MMC_CAP_SDIO_IRQ; + mmc->caps |= mmc_plat->caps; + + if (caps & SDHCI_CAN_DO_HISPD) + mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; + + mmc->ocr_avail = mmc_plat->ocr_mask; + if (caps & SDHCI_CAN_VDD_330) + mmc->ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; + if (caps & SDHCI_CAN_VDD_300) + mmc->ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; + if (caps & SDHCI_CAN_VDD_180) + mmc->ocr_avail |= MMC_VDD_165_195; + + if (mmc->ocr_avail == 0) { + printk(KERN_ERR "%s: Hardware doesn't report any " + "support voltages.\n", mmc_hostname(mmc)); + ret = -ENODEV; + goto out3; + } + + spin_lock_init(&host->lock); + + /* + * Maximum number of segments. Hardware cannot do scatter lists. + */ + if (host->flags & SDHCI_USE_DMA) + mmc->max_hw_segs = 1; + else + mmc->max_hw_segs = 16; + mmc->max_phys_segs = 16; + + /* + * Maximum number of sectors in one transfer. Limited by DMA boundary + * size (512KiB). + */ + if (host->flags & SDHCI_USE_EXTERNAL_DMA) + mmc->max_req_size = 32 * 1024; + else + mmc->max_req_size = 524288; + + /* + * Maximum segment size. Could be one segment with the maximum number + * of bytes. + */ + mmc->max_seg_size = mmc->max_req_size; + + /* + * Maximum block size. This varies from controller to controller and + * is specified in the capabilities register. + */ + mmc->max_blk_size = + (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; + if (mmc->max_blk_size > 3) { + printk(KERN_WARNING "%s: Invalid maximum block size, " + "assuming 512 bytes\n", mmc_hostname(mmc)); + mmc->max_blk_size = 512; + } else + mmc->max_blk_size = 512 << mmc->max_blk_size; + + /* + * Maximum block count. + */ + mmc->max_blk_count = 65535; + + /* + * Apply a continous physical memory used for storing the ADMA + * descriptor table. + */ + if (host->flags & SDHCI_USE_DMA) { + adma_des_table = kcalloc((2 * (mmc->max_phys_segs) + 1), + sizeof(unsigned int), GFP_DMA); + if (adma_des_table == NULL) { + printk(KERN_ERR "Cannot allocate ADMA memory\n"); + ret = -ENOMEM; + goto out3; + } + } + + /* + * Init tasklets. + */ + tasklet_init(&host->card_tasklet, + sdhci_tasklet_card, (unsigned long)host); + + /* initialize the work queue */ + host->workqueue = create_workqueue("esdhc_wq"); + INIT_WORK(&host->cd_wq, esdhc_cd_callback); + INIT_WORK(&host->finish_wq, sdhci_finish_worker); + + setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); + setup_timer(&host->cd_timer, sdhci_cd_timer, (unsigned long)host); + + if (host->detect_irq) { + ret = request_irq(host->detect_irq, sdhci_cd_irq, 0, + pdev->name, host); + if (ret) + goto out4; + } + + ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, pdev->name, host); + if (ret) + goto out5; + + sdhci_init(host); + + if (host->flags & SDHCI_USE_EXTERNAL_DMA) { + /* Apply the 1-bit SDMA channel. */ + if (host->id == 0) + dev_id = MXC_DMA_MMC1_WIDTH_1; + else + dev_id = MXC_DMA_MMC2_WIDTH_1; + host->dma = mxc_dma_request(dev_id, "MXC MMC"); + if (host->dma < 0) { + DBG("Cannot allocate MMC DMA channel\n"); + goto out6; + } + mxc_dma_callback_set(host->dma, sdhci_dma_irq, (void *)host); + } + + mmiowb(); + + if (mmc_add_host(mmc) < 0) + goto out6; + if (host->flags & SDHCI_USE_EXTERNAL_DMA) + printk(KERN_INFO "%s: SDHCI detect irq %d irq %d %s\n", + mmc_hostname(mmc), host->detect_irq, host->irq, + "EXTERNAL DMA"); + else + printk(KERN_INFO "%s: SDHCI detect irq %d irq %d %s\n", + mmc_hostname(mmc), host->detect_irq, host->irq, + (host->flags & SDHCI_USE_DMA) ? "INTERNAL DMA" : "PIO"); + + return 0; + + out6: + free_irq(host->irq, host); + out5: + if (host->detect_irq) + free_irq(host->detect_irq, host); + else { + if ((pdev->id >= 0) && (pdev->id < MXC_SDHCI_NUM)) + mxc_fix_chips[pdev->id] = chip; + } + out4: + del_timer_sync(&host->timer); + del_timer_sync(&host->cd_timer); + tasklet_kill(&host->card_tasklet); + destroy_workqueue(host->workqueue); + out3: + if (host->flags & SDHCI_USE_DMA) + kfree(adma_des_table); + release_mem_region(host->res->start, + host->res->end - host->res->start + 1); + out2: + clk_disable(host->clk); + host->plat_data->clk_flg = 0; + clk_put(host->clk); + out1: + gpio_sdhc_inactive(pdev->id); + out0: + mmc_free_host(mmc); + return ret; +} + +static void sdhci_remove_slot(struct platform_device *pdev, int slot) +{ + struct sdhci_chip *chip; + struct mmc_host *mmc; + struct sdhci_host *host; + + chip = dev_get_drvdata(&pdev->dev); + host = chip->hosts[slot]; + mmc = host->mmc; + + chip->hosts[slot] = NULL; + + mmc_remove_host(mmc); + + sdhci_reset(host, SDHCI_RESET_ALL); + + if (host->detect_irq) + free_irq(host->detect_irq, host); + else { + if ((pdev->id >= 0) && (pdev->id < MXC_SDHCI_NUM)) + mxc_fix_chips[pdev->id] = NULL; + } + free_irq(host->irq, host); + if (chip->quirks & SDHCI_QUIRK_EXTERNAL_DMA_MODE) { + host->flags &= ~SDHCI_USE_EXTERNAL_DMA; + mxc_dma_free(host->dma); + } + + del_timer_sync(&host->timer); + + tasklet_kill(&host->card_tasklet); + flush_workqueue(host->workqueue); + destroy_workqueue(host->workqueue); + + if (host->flags & SDHCI_USE_DMA) + kfree(adma_des_table); + release_mem_region(host->res->start, + host->res->end - host->res->start + 1); + clk_disable(host->clk); + host->plat_data->clk_flg = 0; + clk_put(host->clk); + mmc_free_host(mmc); + gpio_sdhc_inactive(pdev->id); +} + +static int sdhci_probe(struct platform_device *pdev) +{ + int ret = 0, i; + u8 slots = 1; + struct sdhci_chip *chip; + + printk(KERN_INFO DRIVER_NAME ": MXC SDHCI Controller Driver. \n"); + BUG_ON(pdev == NULL); + + chip = kzalloc(sizeof(struct sdhci_chip) + + sizeof(struct sdhci_host *) * slots, GFP_KERNEL); + if (!chip) { + ret = -ENOMEM; + goto err; + } + + /* Distinguish different platform */ + if (machine_is_mx37_3ds()) { + mxc_quirks = SDHCI_QUIRK_EXTERNAL_DMA_MODE; + } else { + mxc_quirks = SDHCI_QUIRK_INTERNAL_ADVANCED_DMA | + SDHCI_QUIRK_INTERNAL_SIMPLE_DMA; + } + chip->pdev = pdev; + chip->quirks = mxc_quirks; + + if (debug_quirks) + chip->quirks = debug_quirks; + + chip->num_slots = slots; + dev_set_drvdata(&pdev->dev, chip); + + for (i = 0; i < slots; i++) { + ret = sdhci_probe_slot(pdev, i); + if (ret) { + for (i--; i >= 0; i--) + sdhci_remove_slot(pdev, i); + goto free; + } + } + + return 0; + + free: + dev_set_drvdata(&pdev->dev, NULL); + kfree(chip); + + err: + return ret; +} + +static int sdhci_remove(struct platform_device *pdev) +{ + int i; + struct sdhci_chip *chip; + + chip = dev_get_drvdata(&pdev->dev); + + if (chip) { + for (i = 0; i < chip->num_slots; i++) + sdhci_remove_slot(pdev, i); + + dev_set_drvdata(&pdev->dev, NULL); + + kfree(chip); + } + + return 0; +} + +static struct platform_driver sdhci_driver = { + .driver = { + .name = DRIVER_NAME, + }, + .probe = sdhci_probe, + .remove = sdhci_remove, + .suspend = sdhci_suspend, + .resume = sdhci_resume, +}; + +/*****************************************************************************\ + * * + * Driver init/exit * + * * +\*****************************************************************************/ + +static int __init sdhci_drv_init(void) +{ + printk(KERN_INFO DRIVER_NAME + ": MXC Secure Digital Host Controller Interface driver\n"); + return platform_driver_register(&sdhci_driver); +} + +static void __exit sdhci_drv_exit(void) +{ + DBG("Exiting\n"); + + platform_driver_unregister(&sdhci_driver); +} + +module_init(sdhci_drv_init); +module_exit(sdhci_drv_exit); + +module_param(debug_quirks, uint, 0444); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Secure Digital Host Controller Interface driver"); +MODULE_LICENSE("GPL"); + +MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); diff --git a/drivers/mmc/host/mx_sdhci.h b/drivers/mmc/host/mx_sdhci.h new file mode 100644 index 000000000000..0cf988717282 --- /dev/null +++ b/drivers/mmc/host/mx_sdhci.h @@ -0,0 +1,302 @@ +/* + * linux/drivers/mmc/host/mx_sdhci.h - Secure Digital Host + * Controller Interface driver + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +/* + * Controller registers + */ + +#define SDHCI_DMA_ADDRESS 0x00 + +#define SDHCI_BLOCK_SIZE 0x04 +#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 13) | (blksz & 0x1FFF)) + +#define SDHCI_BLOCK_COUNT 0x04 + +#define SDHCI_ARGUMENT 0x08 + +#define SDHCI_TRANSFER_MODE 0x0C +#define SDHCI_TRNS_DMA 0x00000001 +#define SDHCI_TRNS_BLK_CNT_EN 0x00000002 +#define SDHCI_TRNS_ACMD12 0x00000004 +#define SDHCI_TRNS_DDR_EN 0x00000008 +#define SDHCI_TRNS_READ 0x00000010 +#define SDHCI_TRNS_MULTI 0x00000020 +#define SDHCI_TRNS_DPSEL 0x00200000 +#define SDHCI_TRNS_ABORTCMD 0x00C00000 +#define SDHCI_TRNS_MASK 0xFFFF0000 + +#define SDHCI_COMMAND 0x0E +#define SDHCI_CMD_RESP_MASK 0x03 +#define SDHCI_CMD_CRC 0x08 +#define SDHCI_CMD_INDEX 0x10 +#define SDHCI_CMD_DATA 0x20 + +#define SDHCI_CMD_RESP_NONE 0x00 +#define SDHCI_CMD_RESP_LONG 0x01 +#define SDHCI_CMD_RESP_SHORT 0x02 +#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 + +#define SDHCI_MAKE_CMD(c, f) ((((c & 0xff) << 8) | (f & 0xff)) << 16) + +#define SDHCI_RESPONSE 0x10 + +#define SDHCI_BUFFER 0x20 + +#define SDHCI_PRESENT_STATE 0x24 +#define SDHCI_CMD_INHIBIT 0x00000001 +#define SDHCI_DATA_INHIBIT 0x00000002 +#define SDHCI_DATA_ACTIVE 0x00000004 +#define SDHCI_DOING_WRITE 0x00000100 +#define SDHCI_DOING_READ 0x00000200 +#define SDHCI_SPACE_AVAILABLE 0x00000400 +#define SDHCI_DATA_AVAILABLE 0x00000800 +#define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_WRITE_PROTECT 0x00080000 +#define SDHCI_DAT0_IDLE 0x01000000 +#define SDHCI_CARD_INT_MASK 0x0E000000 +#define SDHCI_CARD_INT_ID 0x0C000000 + +#define SDHCI_HOST_CONTROL 0x28 +#define SDHCI_CTRL_LED 0x00000001 +#define SDHCI_CTRL_4BITBUS 0x00000002 +#define SDHCI_CTRL_8BITBUS 0x00000004 +#define SDHCI_CTRL_HISPD 0x00000004 +#define SDHCI_CTRL_CDSS 0x80 +#define SDHCI_CTRL_DMA_MASK 0x18 +#define SDHCI_CTRL_SDMA 0x00 +#define SDHCI_CTRL_ADMA1 0x08 +#define SDHCI_CTRL_ADMA32 0x10 +#define SDHCI_CTRL_ADMA64 0x18 +#define SDHCI_CTRL_D3CD 0x00000008 +#define SDHCI_CTRL_ADMA 0x00000100 +/* wake up control */ +#define SDHCI_CTRL_WECINS 0x04000000 + +#define SDHCI_POWER_CONTROL 0x29 +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +#define SDHCI_BLOCK_GAP_CONTROL 0x2A + +#define SDHCI_WAKE_UP_CONTROL 0x2B + +#define SDHCI_CLOCK_CONTROL 0x2C +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_CLOCK_SD_EN 0x00000008 +#define SDHCI_CLOCK_PER_EN 0x00000004 +#define SDHCI_CLOCK_HLK_EN 0x00000002 +#define SDHCI_CLOCK_IPG_EN 0x00000001 +#define SDHCI_CLOCK_SDCLKFS1 0x00000100 +#define SDHCI_CLOCK_MASK 0x0000FFFF + +#define SDHCI_TIMEOUT_CONTROL 0x2E + +#define SDHCI_SOFTWARE_RESET 0x2F +#define SDHCI_RESET_ALL 0x01 +#define SDHCI_RESET_CMD 0x02 +#define SDHCI_RESET_DATA 0x04 + +#define SDHCI_INT_STATUS 0x30 +#define SDHCI_INT_ENABLE 0x34 +#define SDHCI_SIGNAL_ENABLE 0x38 +#define SDHCI_INT_RESPONSE 0x00000001 +#define SDHCI_INT_DATA_END 0x00000002 +#define SDHCI_INT_DMA_END 0x00000008 +#define SDHCI_INT_SPACE_AVAIL 0x00000010 +#define SDHCI_INT_DATA_AVAIL 0x00000020 +#define SDHCI_INT_CARD_INSERT 0x00000040 +#define SDHCI_INT_CARD_REMOVE 0x00000080 +#define SDHCI_INT_CARD_INT 0x00000100 +#define SDHCI_INT_ERROR 0x00008000 +#define SDHCI_INT_TIMEOUT 0x00010000 +#define SDHCI_INT_CRC 0x00020000 +#define SDHCI_INT_END_BIT 0x00040000 +#define SDHCI_INT_INDEX 0x00080000 +#define SDHCI_INT_DATA_TIMEOUT 0x00100000 +#define SDHCI_INT_DATA_CRC 0x00200000 +#define SDHCI_INT_DATA_END_BIT 0x00400000 +#define SDHCI_INT_BUS_POWER 0x00800000 +#define SDHCI_INT_ACMD12ERR 0x01000000 +#define SDHCI_INT_ADMA_ERROR 0x10000000 + +#define SDHCI_INT_NORMAL_MASK 0x00007FFF +#define SDHCI_INT_ERROR_MASK 0xFFFF8000 + +#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ + SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ + SDHCI_INT_ACMD12ERR) +#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ + SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ + SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) +#define SDHCI_INT_DATA_RE_MASK (SDHCI_INT_DMA_END | \ + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL) + +#define SDHCI_ACMD12_ERR 0x3C +#define SDHCI_ACMD12_ERR_NE 0x00000001 +#define SDHCI_ACMD12_ERR_TOE 0x00000002 +#define SDHCI_ACMD12_ERR_EBE 0x00000004 +#define SDHCI_ACMD12_ERR_CE 0x00000008 +#define SDHCI_ACMD12_ERR_IE 0x00000010 +#define SDHCI_ACMD12_ERR_CNIBE 0x00000080 + +/* 3E-3F reserved */ + +#define SDHCI_CAPABILITIES 0x40 +#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F +#define SDHCI_TIMEOUT_CLK_SHIFT 0 +#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 +#define SDHCI_CLOCK_BASE_MASK 0x00003F00 +#define SDHCI_CLOCK_BASE_SHIFT 8 +#define SDHCI_MAX_BLOCK_MASK 0x00030000 +#define SDHCI_MAX_BLOCK_SHIFT 16 +#define SDHCI_CAN_DO_ADMA2 0x00080000 +#define SDHCI_CAN_DO_ADMA1 0x00100000 +#define SDHCI_CAN_DO_HISPD 0x00200000 +#define SDHCI_CAN_DO_DMA 0x00400000 +#define SDHCI_CAN_VDD_330 0x01000000 +#define SDHCI_CAN_VDD_300 0x02000000 +#define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT 0x10000000 + +/* 44-47 reserved for more caps */ +#define SDHCI_WML 0x44 +#define SDHCI_WML_4_WORDS 0x00040004 +#define SDHCI_WML_16_WORDS 0x00100010 +#define SDHCI_WML_64_WORDS 0x00400040 +#define SDHCI_WML_128_WORDS 0x00800080 + +#define SDHCI_MAX_CURRENT 0x48 + +/* 4C-4F reserved for more max current */ + +#define SDHCI_SET_ACMD12_ERROR 0x50 +#define SDHCI_SET_INT_ERROR 0x52 + +#define SDHCI_ADMA_ERROR 0x54 + +/* 55-57 reserved */ + +#define SDHCI_ADMA_ADDRESS 0x58 + +/* 60-FB reserved */ +#define SDHCI_DLL_CONTROL 0x60 +#define DLL_CTRL_ENABLE 0x00000001 +#define DLL_CTRL_RESET 0x00000002 +#define DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define DLL_CTRL_SLV_DLY_TAR 0x00000000 +#define DLL_CTRL_SLV_UP_INT 0x00200000 +#define DLL_CTRL_REF_UP_INT 0x20000000 + +#define SDHCI_DLL_STATUS 0x64 +#define DLL_STS_SLV_LOCK 0x00000001 +#define DLL_STS_REF_LOCK 0x00000002 + +/* ADMA Addr Descriptor Attribute Filed */ +enum { + FSL_ADMA_DES_ATTR_VALID = 0x01, + FSL_ADMA_DES_ATTR_END = 0x02, + FSL_ADMA_DES_ATTR_INT = 0x04, + FSL_ADMA_DES_ATTR_SET = 0x10, + FSL_ADMA_DES_ATTR_TRAN = 0x20, + FSL_ADMA_DES_ATTR_LINK = 0x30, +}; + +#define SDHCI_VENDOR_SPEC 0xC0 + +#define SDHCI_HOST_VERSION 0xFC +#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define ESDHC_VENDOR_V22 0x12 +#define ESDHC_VENDOR_V3 0x13 + +struct sdhci_chip; + +struct sdhci_host { + struct sdhci_chip *chip; + struct mmc_host *mmc; /* MMC structure */ + +#ifdef CONFIG_LEDS_CLASS + struct led_classdev led; /* LED control */ +#endif + + spinlock_t lock; /* Mutex */ + + int init_flag; /* Host has been initialized */ + int flags; /* Host attributes */ +#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */ +#define SDHCI_REQ_USE_DMA (1<<1) /* Use DMA for this req. */ +#define SDHCI_USE_EXTERNAL_DMA (1<<2) /* Use the External DMA */ +#define SDHCI_CD_PRESENT (1<<8) /* CD present */ +#define SDHCI_WP_ENABLED (1<<9) /* Write protect */ +#define SDHCI_CD_TIMEOUT (1<<10) /* cd timer is expired */ + + unsigned int max_clk; /* Max possible freq (MHz) */ + unsigned int min_clk; /* Min possible freq (MHz) */ + unsigned int timeout_clk; /* Timeout freq (KHz) */ + + unsigned int clock; /* Current clock (MHz) */ + unsigned short power; /* Current voltage */ + struct regulator *regulator_mmc; /*! Regulator */ + + struct mmc_request *mrq; /* Current request */ + struct mmc_command *cmd; /* Current command */ + struct mmc_data *data; /* Current data request */ + unsigned int data_early:1; /* Data finished before cmd */ + + unsigned int id; /* Id for SD/MMC block */ + int mode; /* SD/MMC mode */ + int dma; /* DMA channel number. */ + unsigned int dma_size; /* Number of Bytes in DMA */ + unsigned int dma_len; /* Length of the s-g list */ + unsigned int dma_dir; /* DMA transfer direction */ + + struct scatterlist *cur_sg; /* We're working on this */ + int num_sg; /* Entries left */ + int offset; /* Offset into current sg */ + int remain; /* Bytes left in current */ + + struct resource *res; /* IO map memory */ + int irq; /* Device IRQ */ + int detect_irq; /* Card Detect IRQ number. */ + int sdio_enable; /* sdio interrupt enable number. */ + struct clk *clk; /* Clock id */ + int bar; /* PCI BAR index */ + unsigned long addr; /* Bus address */ + void __iomem *ioaddr; /* Mapped address */ + + struct tasklet_struct card_tasklet; /* Tasklet structures */ + struct workqueue_struct *workqueue; + struct work_struct finish_wq; + struct work_struct cd_wq; /* card detection work queue */ + /* Platform specific data */ + struct mxc_mmc_platform_data *plat_data; + + struct timer_list timer; /* Timer for timeouts */ + struct timer_list cd_timer; /* Timer for cd */ +}; + +struct sdhci_chip { + struct platform_device *pdev; + + unsigned long quirks; + + int num_slots; /* Slots on controller */ + struct sdhci_host *hosts[0]; /* Pointers to hosts */ +}; diff --git a/drivers/mmc/host/mxc_mmc.c b/drivers/mmc/host/mxc_mmc.c new file mode 100644 index 000000000000..bc803b141990 --- /dev/null +++ b/drivers/mmc/host/mxc_mmc.c @@ -0,0 +1,1534 @@ +/* + * linux/drivers/mmc/host/mxc_mmc.c - Freescale MXC/i.MX MMC driver + * + * based on imxmmc.c + * Copyright (C) 2004 Sascha Hauer, Pengutronix + * + * derived from pxamci.c by Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_mmc.c + * + * @brief Driver for the Freescale Semiconductor MXC SDHC modules. + * + * This driver code is based on imxmmc.c, by Sascha Hauer, + * Pengutronix . This driver supports both Secure Digital + * Host Controller modules (SDHC1 and SDHC2) of MXC. SDHC is also referred as + * MMC/SD controller. This code is not tested for SD cards. + * + * @ingroup MMC_SD + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_mmc.h" + +#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) + +/* + * This define is used to test the driver without using DMA + */ +#define MXC_MMC_DMA_ENABLE + +/*! + * Maxumum length of s/g list, only length of 1 is currently supported + */ +#define NR_SG 1 + +#ifdef CONFIG_MMC_DEBUG +static void dump_cmd(struct mmc_command *cmd) +{ + printk(KERN_INFO "%s: CMD: opcode: %d ", DRIVER_NAME, cmd->opcode); + printk(KERN_INFO "arg: 0x%08x ", cmd->arg); + printk(KERN_INFO "flags: 0x%08x\n", cmd->flags); +} + +static void dump_status(const char *func, int sts) +{ + unsigned int bitset; + printk(KERN_INFO "%s:status: ", func); + while (sts) { + /* Find the next bit set */ + bitset = sts & ~(sts - 1); + switch (bitset) { + case STATUS_CARD_INSERTION: + printk(KERN_INFO "CARD_INSERTION|"); + break; + case STATUS_CARD_REMOVAL: + printk(KERN_INFO "CARD_REMOVAL |"); + break; + case STATUS_YBUF_EMPTY: + printk(KERN_INFO "YBUF_EMPTY |"); + break; + case STATUS_XBUF_EMPTY: + printk(KERN_INFO "XBUF_EMPTY |"); + break; + case STATUS_YBUF_FULL: + printk(KERN_INFO "YBUF_FULL |"); + break; + case STATUS_XBUF_FULL: + printk(KERN_INFO "XBUF_FULL |"); + break; + case STATUS_BUF_UND_RUN: + printk(KERN_INFO "BUF_UND_RUN |"); + break; + case STATUS_BUF_OVFL: + printk(KERN_INFO "BUF_OVFL |"); + break; + case STATUS_READ_OP_DONE: + printk(KERN_INFO "READ_OP_DONE |"); + break; + case STATUS_WR_CRC_ERROR_CODE_MASK: + printk(KERN_INFO "WR_CRC_ERROR_CODE |"); + break; + case STATUS_READ_CRC_ERR: + printk(KERN_INFO "READ_CRC_ERR |"); + break; + case STATUS_WRITE_CRC_ERR: + printk(KERN_INFO "WRITE_CRC_ERR |"); + break; + case STATUS_SDIO_INT_ACTIVE: + printk(KERN_INFO "SDIO_INT_ACTIVE |"); + break; + case STATUS_END_CMD_RESP: + printk(KERN_INFO "END_CMD_RESP |"); + break; + case STATUS_WRITE_OP_DONE: + printk(KERN_INFO "WRITE_OP_DONE |"); + break; + case STATUS_CARD_BUS_CLK_RUN: + printk(KERN_INFO "CARD_BUS_CLK_RUN |"); + break; + case STATUS_BUF_READ_RDY: + printk(KERN_INFO "BUF_READ_RDY |"); + break; + case STATUS_BUF_WRITE_RDY: + printk(KERN_INFO "BUF_WRITE_RDY |"); + break; + case STATUS_RESP_CRC_ERR: + printk(KERN_INFO "RESP_CRC_ERR |"); + break; + case STATUS_TIME_OUT_RESP: + printk(KERN_INFO "TIME_OUT_RESP |"); + break; + case STATUS_TIME_OUT_READ: + printk(KERN_INFO "TIME_OUT_READ |"); + break; + default: + printk(KERN_INFO "Invalid Status Register value0x%x\n", + bitset); + break; + } + sts &= ~bitset; + } + printk(KERN_INFO "\n"); +} +#endif + +/*! + * This structure is a way for the low level driver to define their own + * \b mmc_host structure. This structure includes the core \b mmc_host + * structure that is provided by Linux MMC/SD Bus protocol driver as an + * element and has other elements that are specifically required by this + * low-level driver. + */ +struct mxcmci_host { + /*! + * The mmc structure holds all the information about the device + * structure, current SDHC io bus settings, the current OCR setting, + * devices attached to this host, and so on. + */ + struct mmc_host *mmc; + + /*! + * This variable is used for locking the host data structure from + * multiple access. + */ + spinlock_t lock; + + /*! + * Resource structure, which will maintain base addresses and IRQs. + */ + struct resource *res; + + /*! + * Base address of SDHC, used in readl and writel. + */ + void *base; + + /*! + * SDHC IRQ number. + */ + int irq; + + /*! + * Card Detect IRQ number. + */ + int detect_irq; + + /*! + * Clock id to hold ipg_perclk. + */ + struct clk *clk; + /*! + * MMC mode. + */ + int mode; + + /*! + * DMA channel number. + */ + int dma; + + /*! + * Pointer to hold MMC/SD request. + */ + struct mmc_request *req; + + /*! + * Pointer to hold MMC/SD command. + */ + struct mmc_command *cmd; + + /*! + * Pointer to hold MMC/SD data. + */ + struct mmc_data *data; + + /*! + * Holds the number of bytes to transfer using DMA. + */ + unsigned int dma_size; + + /*! + * Value to store in Command and Data Control Register + * - currently unused + */ + unsigned int cmdat; + + /*! + * Regulator + */ + struct regulator *regulator_mmc; + + /*! + * Current vdd settting + */ + int current_vdd; + + /*! + * Power mode - currently unused + */ + unsigned int power_mode; + + /*! + * DMA address for scatter-gather transfers + */ + dma_addr_t sg_dma; + + /*! + * Length of the scatter-gather list + */ + unsigned int dma_len; + + /*! + * Holds the direction of data transfer. + */ + unsigned int dma_dir; + + /*! + * Id for MMC block. + */ + unsigned int id; + + /*! + * Note whether this driver has been suspended. + */ + unsigned int mxc_mmc_suspend_flag; + + /*! + * sdio_irq enable/disable ref count + */ + int sdio_irq_cnt; + + /*! + * Platform specific data + */ + struct mxc_mmc_platform_data *plat_data; +}; + +extern void gpio_sdhc_active(int module); +extern void gpio_sdhc_inactive(int module); + +#ifdef MXC_MMC_DMA_ENABLE +static void mxcmci_dma_irq(void *devid, int error, unsigned int cnt); +#endif +static int mxcmci_data_done(struct mxcmci_host *host, unsigned int stat); + +/* Wait count to start the clock */ +#define CMD_WAIT_CNT 100 + +#define MAX_HOST 10 +static struct mmc_host *hosts[MAX_HOST]; + +void mxc_mmc_force_detect(int id) +{ + if (id < MAX_HOST) + mmc_detect_change(hosts[id], msecs_to_jiffies(100)); +} + +EXPORT_SYMBOL(mxc_mmc_force_detect); + +/*! + This function sets the SDHC register to stop the clock and waits for the + * clock stop indication. + */ +static void mxcmci_stop_clock(struct mxcmci_host *host, bool wait) +{ + int wait_cnt = 0; + while (1) { + __raw_writel(STR_STP_CLK_STOP_CLK, + host->base + MMC_STR_STP_CLK); + + if (!wait) + break; + + wait_cnt = CMD_WAIT_CNT; + while (wait_cnt--) { + if (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_CARD_BUS_CLK_RUN)) + break; + } + + if (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_CARD_BUS_CLK_RUN)) + break; + } +} + +/*! + * This function sets the SDHC register to start the clock and waits for the + * clock start indication. When the clock starts SDHC module starts processing + * the command in CMD Register with arguments in ARG Register. + * + * @param host Pointer to MMC/SD host structure + * @param wait Boolean value to indicate whether to wait for the clock to start or come out instantly + */ +static void mxcmci_start_clock(struct mxcmci_host *host, bool wait) +{ + int wait_cnt; + +#ifdef CONFIG_MMC_DEBUG + dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS)); +#endif + + while (1) { + __raw_writel(STR_STP_CLK_START_CLK, + host->base + MMC_STR_STP_CLK); + if (!wait) + break; + + wait_cnt = CMD_WAIT_CNT; + while (wait_cnt--) { + if (__raw_readl(host->base + MMC_STATUS) & + STATUS_CARD_BUS_CLK_RUN) { + break; + } + } + + if (__raw_readl(host->base + MMC_STATUS) & + STATUS_CARD_BUS_CLK_RUN) { + break; + } + } +#ifdef CONFIG_MMC_DEBUG + dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS)); +#endif + pr_debug("%s:CLK_RATE: 0x%08x\n", DRIVER_NAME, + __raw_readl(host->base + MMC_CLK_RATE)); +} + +/*! + * This function resets the SDHC host. + * + * @param host Pointer to MMC/SD host structure + */ +static void mxcmci_softreset(struct mxcmci_host *host) +{ + /* reset sequence */ + __raw_writel(0x8, host->base + MMC_STR_STP_CLK); + __raw_writel(0x9, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x1, host->base + MMC_STR_STP_CLK); + __raw_writel(0x3f, host->base + MMC_CLK_RATE); + + __raw_writel(0xff, host->base + MMC_RES_TO); + __raw_writel(512, host->base + MMC_BLK_LEN); + __raw_writel(1, host->base + MMC_NOB); +} + +/*! + * This function is called to setup SDHC register for data transfer. + * The function allocates DMA buffers, configures the DMA channel. + * Start the DMA channel to transfer data. When DMA is not enabled this + * function set ups only Number of Block and Block Length registers. + * + * @param host Pointer to MMC/SD host structure + * @param data Pointer to MMC/SD data structure + */ +static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) +{ + unsigned int nob = data->blocks; + + if (data->flags & MMC_DATA_STREAM) { + nob = 0xffff; + } + + host->data = data; + + __raw_writel(nob, host->base + MMC_NOB); + __raw_writel(data->blksz, host->base + MMC_BLK_LEN); + + host->dma_size = data->blocks * data->blksz; + pr_debug("%s:Request bytes to transfer:%d\n", DRIVER_NAME, + host->dma_size); + +#ifdef MXC_MMC_DMA_ENABLE + if (host->dma_size <= (16 << host->mmc->ios.bus_width)) { + return; + } + + if (data->blksz & 0x3) { + printk(KERN_ERR + "mxc_mci: block size not multiple of 4 bytes\n"); + } + + if (data->flags & MMC_DATA_READ) { + host->dma_dir = DMA_FROM_DEVICE; + } else { + host->dma_dir = DMA_TO_DEVICE; + } + host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, + host->dma_dir); + + if (data->flags & MMC_DATA_READ) { + mxc_dma_sg_config(host->dma, data->sg, data->sg_len, + host->dma_size, MXC_DMA_MODE_READ); + } else { + mxc_dma_sg_config(host->dma, data->sg, data->sg_len, + host->dma_size, MXC_DMA_MODE_WRITE); + } +#endif +} + +/*! + * This function is called by \b mxcmci_request() function to setup the SDHC + * register to issue command. This function disables the card insertion and + * removal detection interrupt. + * + * @param host Pointer to MMC/SD host structure + * @param cmd Pointer to MMC/SD command structure + * @param cmdat Value to store in Command and Data Control Register + */ +static void mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, + unsigned int cmdat) +{ + WARN_ON(host->cmd != NULL); + host->cmd = cmd; + + switch (RSP_TYPE(mmc_resp_type(cmd))) { + case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */ + cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1; + break; + case RSP_TYPE(MMC_RSP_R3): + cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3; + break; + case RSP_TYPE(MMC_RSP_R2): + cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2; + break; + default: + /* No Response required */ + break; + } + + if (cmd->opcode == MMC_GO_IDLE_STATE) { + cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ + } + + if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) { + cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; + } + + __raw_writel(cmd->opcode, host->base + MMC_CMD); + __raw_writel(cmd->arg, host->base + MMC_ARG); + + __raw_writel(cmdat, host->base + MMC_CMD_DAT_CONT); + + if (!(__raw_readl(host->base + MMC_STATUS) & STATUS_CARD_BUS_CLK_RUN)) + mxcmci_start_clock(host, true); +} + +/*! + * This function is called to complete the command request. + * This function enables insertion or removal interrupt. + * + * @param host Pointer to MMC/SD host structure + * @param req Pointer to MMC/SD command request structure + */ +static void mxcmci_finish_request(struct mxcmci_host *host, + struct mmc_request *req) +{ + + host->req = NULL; + host->cmd = NULL; + host->data = NULL; + + mmc_request_done(host->mmc, req); +} + +/*! + * This function is called when the requested command is completed. + * This function reads the response from the card and data if the command is for + * data transfer. This function checks for CRC error in response FIFO or + * data FIFO. + * + * @param host Pointer to MMC/SD host structure + * @param stat Content of SDHC Status Register + * + * @return This function returns 0 if there is no pending command, otherwise 1 + * always. + */ +static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) +{ + struct mmc_command *cmd = host->cmd; + struct mmc_data *data = host->data; + int i; + u32 a, b, c; + u32 temp_data; + unsigned int status; + unsigned long *buf; + u8 *buf8; + int no_of_bytes; + int no_of_words; + + if (!cmd) { + /* There is no command for completion */ + return 0; + } + + /* As this function finishes the command, initialize cmd to NULL */ + host->cmd = NULL; + + /* check for Time out errors */ + if (stat & STATUS_TIME_OUT_RESP) { + __raw_writel(STATUS_TIME_OUT_RESP, host->base + MMC_STATUS); + pr_debug("%s: CMD %d TIMEOUT\n", DRIVER_NAME, cmd->opcode); + cmd->error = -ETIMEDOUT; + /* + * Reinitialized the controller to clear the unknown + * error state. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR); + } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { + __raw_writel(STATUS_RESP_CRC_ERR, host->base + MMC_STATUS); + printk(KERN_ERR "%s: cmd %d CRC error\n", DRIVER_NAME, + cmd->opcode); + cmd->error = -EILSEQ; + /* + * Reinitialized the controller to clear the unknown + * error state. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR); + } + + /* Read response from the card */ + switch (RSP_TYPE(mmc_resp_type(cmd))) { + case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */ + a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + c = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + cmd->resp[0] = a << 24 | b << 8 | c >> 8; + break; + case RSP_TYPE(MMC_RSP_R3): /* r3, r4 */ + a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + c = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + cmd->resp[0] = a << 24 | b << 8 | c >> 8; + break; + case RSP_TYPE(MMC_RSP_R2): + for (i = 0; i < 4; i++) { + a = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + b = __raw_readl(host->base + MMC_RES_FIFO) & 0xffff; + cmd->resp[i] = a << 16 | b; + } + break; + default: + break; + } + + pr_debug("%s: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", DRIVER_NAME, + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + + if (!host->data || cmd->error) { + /* complete the command */ + mxcmci_finish_request(host, host->req); + return 1; + } + + /* The command has a data transfer */ +#ifdef MXC_MMC_DMA_ENABLE + /* Use DMA if transfer size is greater than fifo size */ + if (host->dma_size > (16 << host->mmc->ios.bus_width)) { + mxc_dma_enable(host->dma); + return 1; + } +#endif + /* Use PIO tranfer of data */ + buf = (unsigned long *)sg_virt(data->sg); + buf8 = (u8 *) buf; + + /* calculate the number of bytes requested for transfer */ + no_of_bytes = data->blocks * data->blksz; + no_of_words = (no_of_bytes + 3) / 4; + pr_debug("no_of_words=%d\n", no_of_words); + + if (data->flags & MMC_DATA_READ) { + for (i = 0; i < no_of_words; i++) { + /* wait for buffers to be ready for read */ + while (!(__raw_readl(host->base + MMC_STATUS) & + (STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE))) + ; + + pr_debug("status is 0x%x\n", + __raw_readl(host->base + MMC_STATUS)); + /* read 32 bit data */ + temp_data = __raw_readl(host->base + MMC_BUFFER_ACCESS); + if (SD_APP_SEND_SCR == cmd->opcode) { + pr_debug("CMD51 read out 0x%x\n", temp_data); + if (temp_data == 0xFFFFFFFF) + temp_data = 0; + } + if (no_of_bytes >= 4) { + *buf++ = temp_data; + no_of_bytes -= 4; + } else { + do { + *buf8++ = temp_data; + temp_data = temp_data >> 8; + } while (--no_of_bytes); + } + } + + /* wait for read operation completion bit */ + while (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_READ_OP_DONE)) + ; + + /* check for time out and CRC errors */ + status = __raw_readl(host->base + MMC_STATUS); + if (status & STATUS_TIME_OUT_READ) { + printk(KERN_ERR "%s: Read time out occurred\n", + DRIVER_NAME); + data->error = -ETIMEDOUT; + __raw_writel(STATUS_TIME_OUT_READ, + host->base + MMC_STATUS); + /* + * Reinitialized the controller to clear the unknown + * error state. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, + host->base + MMC_INT_CNTR); + } else if (status & STATUS_READ_CRC_ERR) { + printk(KERN_ERR "%s: Read CRC error occurred\n", + DRIVER_NAME); + if (SD_APP_SEND_SCR != cmd->opcode) + data->error = -EILSEQ; + __raw_writel(STATUS_READ_CRC_ERR, + host->base + MMC_STATUS); + /* + * Reinitialized the controller to clear the unknown + * error state. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, + host->base + MMC_INT_CNTR); + } + __raw_writel(STATUS_READ_OP_DONE, host->base + MMC_STATUS); + + pr_debug("%s: Read %u words\n", DRIVER_NAME, i); + } else { + for (i = 0; i < no_of_words; i++) { + + /* wait for buffers to be ready for write */ + while (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_BUF_WRITE_RDY)) + ; + + /* write 32 bit data */ + __raw_writel(*buf++, host->base + MMC_BUFFER_ACCESS); + if (__raw_readl(host->base + MMC_STATUS) & + STATUS_WRITE_OP_DONE) { + break; + } + } + + /* wait for write operation completion bit */ + while (!(__raw_readl(host->base + MMC_STATUS) & + STATUS_WRITE_OP_DONE)) + ; + + /* check for CRC errors */ + status = __raw_readl(host->base + MMC_STATUS); + if (status & STATUS_WRITE_CRC_ERR) { + printk(KERN_ERR "%s: Write CRC error occurred\n", + DRIVER_NAME); + data->error = -EILSEQ; + __raw_writel(STATUS_WRITE_CRC_ERR, + host->base + MMC_STATUS); + } + __raw_writel(STATUS_WRITE_OP_DONE, host->base + MMC_STATUS); + pr_debug("%s: Written %u words\n", DRIVER_NAME, i); + } + + /* complete the data transfer request */ + mxcmci_data_done(host, status); + + return 1; +} + +/*! + * This function is called when the data transfer is completed either by DMA + * or by core. This function is called to clean up the DMA buffer and to send + * STOP transmission command for commands to transfer data. This function + * completes request issued by the MMC/SD core driver. + * + * @param host pointer to MMC/SD host structure. + * @param stat content of SDHC Status Register + * + * @return This function returns 0 if no data transfer otherwise return 1 + * always. + */ +static int mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) +{ + struct mmc_data *data = host->data; + + if (!data) { + return 0; + } +#ifdef MXC_MMC_DMA_ENABLE + if (host->dma_size > (16 << host->mmc->ios.bus_width)) { + dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, + host->dma_dir); + } +#endif + if (__raw_readl(host->base + MMC_STATUS) & STATUS_ERR_MASK) { + printk(KERN_ERR "%s: request failed. status: 0x%08x\n", + DRIVER_NAME, __raw_readl(host->base + MMC_STATUS)); + } + + host->data = NULL; + data->bytes_xfered = host->dma_size; + + if (host->req->stop && !(data->error)) { + mxcmci_stop_clock(host, true); + mxcmci_start_cmd(host, host->req->stop, 0); + } else { + mxcmci_finish_request(host, host->req); + } + + return 1; +} + +/*! + * GPIO interrupt service routine registered to handle the SDHC interrupts. + * This interrupt routine handles card insertion and card removal interrupts. + * + * @param irq the interrupt number + * @param devid driver private data + * @param regs holds a snapshot of the processor's context before the + * processor entered the interrupt code + * + * @return The function returns \b IRQ_RETVAL(1) + */ +static irqreturn_t mxcmci_gpio_irq(int irq, void *devid) +{ + struct mxcmci_host *host = devid; + int card_gpio_status = host->plat_data->status(host->mmc->parent); + + pr_debug("%s: MMC%d status=%d %s\n", DRIVER_NAME, host->id, + card_gpio_status, card_gpio_status ? "removed" : "inserted"); + + if (card_gpio_status == host->plat_data->card_inserted_state) { + /* + * Reinitialized the controller to clear the unknown + * error state when a card is inserted. + */ + mxcmci_softreset(host); + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + __raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR); + + mmc_detect_change(host->mmc, msecs_to_jiffies(100)); + } else { + mxcmci_cmd_done(host, STATUS_TIME_OUT_RESP); + mmc_detect_change(host->mmc, msecs_to_jiffies(50)); + } + + do { + card_gpio_status = host->plat_data->status(host->mmc->parent); + if (card_gpio_status) { + set_irq_type(host->detect_irq, IRQF_TRIGGER_FALLING); + } else { + set_irq_type(host->detect_irq, IRQF_TRIGGER_RISING); + } + } while (card_gpio_status != + host->plat_data->status(host->mmc->parent)); + + return IRQ_HANDLED; +} + +/*! + * Interrupt service routine registered to handle the SDHC interrupts. + * This interrupt routine handles end of command, card insertion and + * card removal interrupts. If the interrupt is card insertion or removal then + * inform the MMC/SD core driver to detect the change in physical connections. + * If the command is END_CMD_RESP read the Response FIFO. If DMA is not enabled + * and data transfer is associated with the command then read or write the data + * from or to the BUFFER_ACCESS FIFO. + * + * @param irq the interrupt number + * @param devid driver private data + * @param regs holds a snapshot of the processor's context before the + * processor entered the interrupt code + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + */ +static irqreturn_t mxcmci_irq(int irq, void *devid) +{ + struct mxcmci_host *host = devid; + struct mmc_data *data = host->data; + unsigned int status = 0; + u32 intctrl; + + if (host->mxc_mmc_suspend_flag == 1) { + clk_enable(host->clk); + } + + status = __raw_readl(host->base + MMC_STATUS); + pr_debug("MXC MMC IRQ status is 0x%x.\n", status); +#ifdef CONFIG_MMC_DEBUG + dump_status(__FUNCTION__, status); +#endif + if (status & STATUS_END_CMD_RESP) { + __raw_writel(STATUS_END_CMD_RESP, host->base + MMC_STATUS); + mxcmci_cmd_done(host, status); + } +#ifdef MXC_MMC_DMA_ENABLE + /* + * If read length < fifo length, STATUS_END_CMD_RESP and + * STATUS_READ_OP_DONE may come together. In this case, it's using PIO + * mode, we ignore STATUS_READ_OP_DONE. + */ + if ((status & (STATUS_WRITE_OP_DONE | STATUS_READ_OP_DONE)) && + !(status & STATUS_END_CMD_RESP)) { + pr_debug(KERN_INFO "MXC MMC IO OP DONE INT.\n"); + intctrl = __raw_readl(host->base + MMC_INT_CNTR); + __raw_writel((~(INT_CNTR_WRITE_OP_DONE | INT_CNTR_READ_OP_DONE) + & intctrl), host->base + MMC_INT_CNTR); + + pr_debug("%s:READ/WRITE OPERATION DONE\n", DRIVER_NAME); + /* check for time out and CRC errors */ + status = __raw_readl(host->base + MMC_STATUS); + if (status & STATUS_READ_OP_DONE) { + if (status & STATUS_TIME_OUT_READ) { + pr_debug("%s: Read time out occurred\n", + DRIVER_NAME); + data->error = -ETIMEDOUT; + __raw_writel(STATUS_TIME_OUT_READ, + host->base + MMC_STATUS); + } else if (status & STATUS_READ_CRC_ERR) { + pr_debug("%s: Read CRC error occurred\n", + DRIVER_NAME); + data->error = -EILSEQ; + __raw_writel(STATUS_READ_CRC_ERR, + host->base + MMC_STATUS); + } + __raw_writel(STATUS_READ_OP_DONE, + host->base + MMC_STATUS); + } + + /* check for CRC errors */ + if (status & STATUS_WRITE_OP_DONE) { + if (status & STATUS_WRITE_CRC_ERR) { + printk(KERN_ERR + "%s: Write CRC error occurred\n", + DRIVER_NAME); + data->error = -EILSEQ; + __raw_writel(STATUS_WRITE_CRC_ERR, + host->base + MMC_STATUS); + } + __raw_writel(STATUS_WRITE_OP_DONE, + host->base + MMC_STATUS); + } + + mxcmci_data_done(host, status); + } +#endif + status = __raw_readl(host->base + MMC_STATUS); + intctrl = __raw_readl(host->base + MMC_INT_CNTR); + if ((status & STATUS_SDIO_INT_ACTIVE) + && (intctrl & INT_CNTR_SDIO_IRQ_EN)) { + __raw_writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_STATUS); + + /*Here we do not handle the sdio interrupt to client driver + if the host is in suspend state */ + if (host->mxc_mmc_suspend_flag == 0) { + mmc_signal_sdio_irq(host->mmc); + } + } + return IRQ_HANDLED; +} + +/*! + * This function is called by MMC/SD Bus Protocol driver to issue a MMC + * and SD commands to the SDHC. + * + * @param mmc Pointer to MMC/SD host structure + * @param req Pointer to MMC/SD command request structure + */ +static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) +{ + struct mxcmci_host *host = mmc_priv(mmc); + /* Holds the value of Command and Data Control Register */ + unsigned long cmdat; + + WARN_ON(host->req != NULL); + + host->req = req; +#ifdef CONFIG_MMC_DEBUG + dump_cmd(req->cmd); + dump_status(__FUNCTION__, __raw_readl(host->base + MMC_STATUS)); +#endif + + cmdat = 0; + if (req->data) { + mxcmci_setup_data(host, req->data); + + cmdat |= CMD_DAT_CONT_DATA_ENABLE; + + if (req->data->flags & MMC_DATA_WRITE) { + cmdat |= CMD_DAT_CONT_WRITE; + } + if (req->data->flags & MMC_DATA_STREAM) { + printk(KERN_ERR + "MXC MMC does not support stream mode\n"); + } + } + mxcmci_start_cmd(host, req->cmd, cmdat); +} + +/*! + * This function is called by MMC/SD Bus Protocol driver to change the clock + * speed of MMC or SD card + * + * @param mmc Pointer to MMC/SD host structure + * @param ios Pointer to MMC/SD I/O type structure + */ +static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct mxcmci_host *host = mmc_priv(mmc); + /*This variable holds the value of clock prescaler */ + int prescaler; + int clk_rate = clk_get_rate(host->clk); + int voltage = 0; +#ifdef MXC_MMC_DMA_ENABLE + mxc_dma_device_t dev_id = 0; +#endif + + pr_debug("%s: clock %u, bus %lu, power %u, vdd %u\n", DRIVER_NAME, + ios->clock, 1UL << ios->bus_width, ios->power_mode, ios->vdd); + + host->dma_dir = DMA_NONE; + +#ifdef MXC_MMC_DMA_ENABLE + if (mmc->ios.bus_width != host->mode) { + mxc_dma_free(host->dma); + if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) { + if (host->id == 0) { + dev_id = MXC_DMA_MMC1_WIDTH_4; + } else { + dev_id = MXC_DMA_MMC2_WIDTH_4; + } + } else { + if (host->id == 0) { + dev_id = MXC_DMA_MMC1_WIDTH_1; + } else { + dev_id = MXC_DMA_MMC2_WIDTH_1; + } + } + host->dma = mxc_dma_request(dev_id, "MXC MMC"); + if (host->dma < 0) { + printk(KERN_ERR "Cannot allocate MMC DMA channel\n"); + } + host->mode = mmc->ios.bus_width; + mxc_dma_callback_set(host->dma, mxcmci_dma_irq, (void *)host); + } +#endif + + if ((ios->vdd != host->current_vdd) && host->regulator_mmc) { + if (ios->vdd == 7) + voltage = 1800000; + else if (ios->vdd >= 8) + voltage = 2000000 + (ios->vdd - 8) * 100000; + regulator_set_voltage(host->regulator_mmc, voltage, voltage); + } + host->current_vdd = ios->vdd; + + if (ios->power_mode != host->power_mode && host->regulator_mmc) { + if (ios->power_mode == MMC_POWER_UP) { + if (regulator_enable(host->regulator_mmc) == 0) { + pr_debug("mmc power on\n"); + msleep(1); + } + } else if (ios->power_mode == MMC_POWER_OFF) { + regulator_disable(host->regulator_mmc); + pr_debug("mmc power off\n"); + } + } + host->power_mode = ios->power_mode; + + /* + * Vary divider first, then prescaler. + **/ + if (ios->clock) { + unsigned int clk_dev = 0; + + /* + * when prescaler = 16, CLK_20M = CLK_DIV / 2 + */ + if (ios->clock == mmc->f_min) + prescaler = 16; + else + prescaler = 0; + + /* clk_dev =1, CLK_DIV = ipg_perclk/2 */ + while (prescaler <= 0x800) { + for (clk_dev = 1; clk_dev <= 0xF; clk_dev++) { + int x; + if (prescaler != 0) { + x = (clk_rate / (clk_dev + 1)) / + (prescaler * 2); + } else { + x = clk_rate / (clk_dev + 1); + } + + pr_debug("x=%d, clock=%d %d\n", x, ios->clock, + clk_dev); + if (x <= ios->clock) { + break; + } + } + if (clk_dev < 0x10) { + break; + } + if (prescaler == 0) + prescaler = 1; + else + prescaler <<= 1; + } + + pr_debug("prescaler = 0x%x, divider = 0x%x\n", prescaler, + clk_dev); + mxcmci_stop_clock(host, true); + __raw_writel((prescaler << 4) | clk_dev, + host->base + MMC_CLK_RATE); + mxcmci_start_clock(host, false); + } else { + mxcmci_stop_clock(host, true); + } +} + +static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + struct mxcmci_host *host = mmc_priv(mmc); + u32 intctrl; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + + if (enable) + host->sdio_irq_cnt++; + else + host->sdio_irq_cnt--; + + if (host->sdio_irq_cnt == 1 || host->sdio_irq_cnt == 0) { + intctrl = __raw_readl(host->base + MMC_INT_CNTR); + intctrl &= ~INT_CNTR_SDIO_IRQ_EN; + if (host->sdio_irq_cnt) + intctrl |= INT_CNTR_SDIO_IRQ_EN; + __raw_writel(intctrl, host->base + MMC_INT_CNTR); + } + + spin_unlock_irqrestore(&host->lock, flags); +} + +static int mxcmci_get_ro(struct mmc_host *mmc) +{ + struct mxcmci_host *host = mmc_priv(mmc); + + if (host->plat_data->wp_status) + return host->plat_data->wp_status(mmc->parent); + else + return 0; +} + +/*! + * MMC/SD host operations structure. + * These functions are registered with MMC/SD Bus protocol driver. + */ +static struct mmc_host_ops mxcmci_ops = { + .request = mxcmci_request, + .set_ios = mxcmci_set_ios, + .get_ro = mxcmci_get_ro, + .enable_sdio_irq = mxcmci_enable_sdio_irq, +}; + +#ifdef MXC_MMC_DMA_ENABLE +/*! + * This function is called by DMA Interrupt Service Routine to indicate + * requested DMA transfer is completed. + * + * @param devid pointer to device specific structure + * @param error any DMA error + * @param cnt amount of data that was transferred + */ +static void mxcmci_dma_irq(void *devid, int error, unsigned int cnt) +{ + struct mxcmci_host *host = devid; + u32 status; + ulong nob, blk_size, i, blk_len; + + mxc_dma_disable(host->dma); + + if (error) { + printk(KERN_ERR "Error in DMA transfer\n"); + status = __raw_readl(host->base + MMC_STATUS); +#ifdef CONFIG_MMC_DEBUG + dump_status(__FUNCTION__, status); +#endif + mxcmci_data_done(host, status); + return; + } + pr_debug("%s: Transfered bytes:%d\n", DRIVER_NAME, cnt); + nob = __raw_readl(host->base + MMC_REM_NOB); + blk_size = __raw_readl(host->base + MMC_REM_BLK_SIZE); + blk_len = __raw_readl(host->base + MMC_BLK_LEN); + pr_debug("%s: REM_NOB:%lu REM_BLK_SIZE:%lu\n", DRIVER_NAME, nob, + blk_size); + i = 0; + + /* Enable the WRITE OP Done INT */ + status = __raw_readl(host->base + MMC_INT_CNTR); + __raw_writel((INT_CNTR_READ_OP_DONE | INT_CNTR_WRITE_OP_DONE | status), + host->base + MMC_INT_CNTR); +} +#endif + +/*! + * This function is called during the driver binding process. Based on the SDHC + * module that is being probed this function adds the appropriate SDHC module + * structure in the core driver. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration and initialization + * of SDHC module. Otherwise returns specific error code. + */ +static int mxcmci_probe(struct platform_device *pdev) +{ + struct mxc_mmc_platform_data *mmc_plat = pdev->dev.platform_data; + struct mmc_host *mmc; + struct mxcmci_host *host = NULL; + int card_gpio_status; + int ret = -ENODEV; + + if (!mmc_plat) { + return -EINVAL; + } + + mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev); + if (!mmc) { + return -ENOMEM; + } + host = mmc_priv(mmc); + platform_set_drvdata(pdev, mmc); + + mmc->ops = &mxcmci_ops; + mmc->ocr_avail = mmc_plat->ocr_mask; + + /* Hack to work with LP1070 */ + if (mmc->ocr_avail && ~(MMC_VDD_31_32 - 1) == 0) + mmc->ocr_avail |= MMC_VDD_31_32; + + mmc->max_phys_segs = NR_SG; + mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; + + mmc->f_min = mmc_plat->min_clk; + mmc->f_max = mmc_plat->max_clk; + mmc->max_req_size = 32 * 1024; + mmc->max_seg_size = mmc->max_req_size; + mmc->max_blk_count = 32; + + spin_lock_init(&host->lock); + host->mmc = mmc; + host->dma = -1; + host->dma_dir = DMA_NONE; + host->id = pdev->id; + host->mxc_mmc_suspend_flag = 0; + host->mode = -1; + host->plat_data = mmc_plat; + if (!host->plat_data) { + ret = -EINVAL; + goto out0; + } + + /* Get pwr supply for SDHC */ + if (NULL != mmc_plat->power_mmc) { + host->regulator_mmc = + regulator_get(&pdev->dev, mmc_plat->power_mmc); + if (IS_ERR(host->regulator_mmc)) { + ret = PTR_ERR(host->regulator_mmc); + goto out1; + } + if (!regulator_is_enabled(host->regulator_mmc)) { + if (regulator_enable(host->regulator_mmc) == 0) { + pr_debug("mmc power on\n"); + msleep(1); + } + } + } + + gpio_sdhc_active(pdev->id); + + host->clk = clk_get(&pdev->dev, "sdhc_clk"); + pr_debug("SDHC:%d clock:%lu\n", pdev->id, clk_get_rate(host->clk)); + clk_enable(host->clk); + + host->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!host->res) { + ret = -ENOMEM; + goto out2; + } + + if (!request_mem_region(host->res->start, + host->res->end - + host->res->start + 1, pdev->name)) { + printk(KERN_ERR "request_mem_region failed\n"); + ret = -ENOMEM; + goto out2; + } + host->base = (void *)IO_ADDRESS(host->res->start); + if (!host->base) { + ret = -ENOMEM; + goto out3; + } + + host->irq = platform_get_irq(pdev, 0); + if (!host->irq) { + ret = -ENOMEM; + goto out3; + } + + if (!host->plat_data->card_fixed) { + host->detect_irq = platform_get_irq(pdev, 1); + if (!host->detect_irq) + goto out3; + + do { + card_gpio_status = + host->plat_data->status(host->mmc->parent); + if (card_gpio_status) + set_irq_type(host->detect_irq, + IRQF_TRIGGER_FALLING); + else + set_irq_type(host->detect_irq, + IRQF_TRIGGER_RISING); + + } while (card_gpio_status != + host->plat_data->status(host->mmc->parent)); + + ret = request_irq(host->detect_irq, mxcmci_gpio_irq, 0, + pdev->name, host); + if (ret) + goto out3; + } + + mxcmci_softreset(host); + + if (__raw_readl(host->base + MMC_REV_NO) != SDHC_REV_NO) { + printk(KERN_ERR "%s: wrong rev.no. 0x%08x. aborting.\n", + pdev->name, MMC_REV_NO); + goto out3; + } + __raw_writel(READ_TO_VALUE, host->base + MMC_READ_TO); + + __raw_writel(INT_CNTR_END_CMD_RES, host->base + MMC_INT_CNTR); + + ret = request_irq(host->irq, mxcmci_irq, 0, pdev->name, host); + if (ret) { + goto out4; + } + + ret = mmc_add_host(mmc); + if (ret < 0) + goto out5; + + printk(KERN_INFO "%s-%d found\n", pdev->name, pdev->id); + if (host->id < MAX_HOST) + hosts[host->id] = host->mmc; + + return 0; + + out5: + free_irq(host->irq, host); + out4: + free_irq(host->detect_irq, host); + out3: + release_mem_region(pdev->resource[0].start, + pdev->resource[0].end - pdev->resource[0].start + 1); + out2: + clk_disable(host->clk); + regulator_disable(host->regulator_mmc); + regulator_put(host->regulator_mmc); + out1: + gpio_sdhc_inactive(pdev->id); + out0: + mmc_free_host(mmc); + platform_set_drvdata(pdev, NULL); + return ret; +} + +/*! + * Dissociates the driver from the SDHC device. Removes the appropriate SDHC + * module structure from the core driver. + * + * @param pdev the device structure used to give information on which SDHC + * to remove + * + * @return The function always returns 0. + */ +static int mxcmci_remove(struct platform_device *pdev) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + + if (mmc) { + struct mxcmci_host *host = mmc_priv(mmc); + + hosts[host->id] = NULL; + mmc_remove_host(mmc); + free_irq(host->irq, host); + free_irq(host->detect_irq, host); +#ifdef MXC_MMC_DMA_ENABLE + mxc_dma_free(host->dma); +#endif + release_mem_region(host->res->start, + host->res->end - host->res->start + 1); + mmc_free_host(mmc); + if (NULL != host->regulator_mmc) + regulator_put(host->regulator_mmc); + gpio_sdhc_inactive(pdev->id); + } + platform_set_drvdata(pdev, NULL); + return 0; +} + +#ifdef CONFIG_PM + +/*! + * This function is called to put the SDHC in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which SDHC + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxcmci_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct mxcmci_host *host = mmc_priv(mmc); + int ret = 0; + + if (mmc) { + host->mxc_mmc_suspend_flag = 1; + ret = mmc_suspend_host(mmc, state); + } + + clk_disable(host->clk); + /* + * The CD INT should be disabled in the suspend + * and enabled in resumed. + * Otherwise, the system would be halt when wake + * up with the situation that there is a card + * insertion during the system is in suspend mode. + */ + disable_irq(host->detect_irq); + + gpio_sdhc_inactive(pdev->id); + + if (host->regulator_mmc) + regulator_disable(host->regulator_mmc); + + return ret; +} + +/*! + * This function is called to bring the SDHC back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which SDHC + * to resume + * + * @return The function always returns 0. + */ +static int mxcmci_resume(struct platform_device *pdev) +{ + struct mmc_host *mmc = platform_get_drvdata(pdev); + struct mxcmci_host *host = mmc_priv(mmc); + int ret = 0; + + /* + * Note that a card insertion interrupt will cause this + * driver to resume automatically. In that case we won't + * actually have to do any work here. Return success. + */ + if (!host->mxc_mmc_suspend_flag) { + return 0; + } + + /* enable pwr supply for SDHC */ + if (host->regulator_mmc && !regulator_is_enabled(host->regulator_mmc)) { + regulator_enable(host->regulator_mmc); + msleep(1); + } + + gpio_sdhc_active(pdev->id); + + clk_enable(host->clk); + + if (mmc) { + ret = mmc_resume_host(mmc); + host->mxc_mmc_suspend_flag = 0; + } + + enable_irq(host->detect_irq); + + return ret; +} +#else +#define mxcmci_suspend NULL +#define mxcmci_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcmci_driver = { + .driver = { + .name = "mxcmci", + }, + .probe = mxcmci_probe, + .remove = mxcmci_remove, + .suspend = mxcmci_suspend, + .resume = mxcmci_resume, +}; + +/*! + * This function is used to initialize the MMC/SD driver module. The function + * registers the power management callback functions with the kernel and also + * registers the MMC/SD callback functions with the core MMC/SD driver. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxcmci_init(void) +{ + printk(KERN_INFO "MXC MMC/SD driver\n"); + return platform_driver_register(&mxcmci_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxcmci_exit(void) +{ + platform_driver_unregister(&mxcmci_driver); +} + +module_init(mxcmci_init); +module_exit(mxcmci_exit); + +MODULE_DESCRIPTION("MXC Multimedia Card Interface Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/host/mxc_mmc.h b/drivers/mmc/host/mxc_mmc.h new file mode 100644 index 000000000000..d86cc8f7c726 --- /dev/null +++ b/drivers/mmc/host/mxc_mmc.h @@ -0,0 +1,124 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_MMC_REG_H__ +#define __MXC_MMC_REG_H__ + +/*! + * @defgroup MMC_SD MMC/SD Driver + */ + +/*! + * @file mxc_mmc.h + * + * @brief Driver for the Freescale Semiconductor MXC SDHC modules. + * + * This file defines offsets and bits of SDHC registers. SDHC is also referred as + * MMC/SD controller + * + * @ingroup MMC_SD + */ + +/*! + * Number of SDHC modules + */ + +#define SDHC_MMC_WML 16 +#define SDHC_SD_WML 64 +#define DRIVER_NAME "MXCMMC" +#define SDHC_MEM_SIZE 16384 +#define SDHC_REV_NO 0x400 +#define READ_TO_VALUE 0x2db4 + +/* Address offsets of the SDHC registers */ +#define MMC_STR_STP_CLK 0x00 /* Clock Control Reg */ +#define MMC_STATUS 0x04 /* Status Reg */ +#define MMC_CLK_RATE 0x08 /* Clock Rate Reg */ +#define MMC_CMD_DAT_CONT 0x0C /* Command and Data Control Reg */ +#define MMC_RES_TO 0x10 /* Response Time-out Reg */ +#define MMC_READ_TO 0x14 /* Read Time-out Reg */ +#define MMC_BLK_LEN 0x18 /* Block Length Reg */ +#define MMC_NOB 0x1C /* Number of Blocks Reg */ +#define MMC_REV_NO 0x20 /* Revision Number Reg */ +#define MMC_INT_CNTR 0x24 /* Interrupt Control Reg */ +#define MMC_CMD 0x28 /* Command Number Reg */ +#define MMC_ARG 0x2C /* Command Argument Reg */ +#define MMC_RES_FIFO 0x34 /* Command Response Reg */ +#define MMC_BUFFER_ACCESS 0x38 /* Data Buffer Access Reg */ +#define MMC_REM_NOB 0x40 /* Remaining NOB Reg */ +#define MMC_REM_BLK_SIZE 0x44 /* Remaining Block Size Reg */ + +/* Bit definitions for STR_STP_CLK */ +#define STR_STP_CLK_RESET (1<<3) +#define STR_STP_CLK_START_CLK (1<<1) +#define STR_STP_CLK_STOP_CLK (1<<0) + +/* Bit definitions for STATUS */ +#define STATUS_CARD_INSERTION (1<<31) +#define STATUS_CARD_REMOVAL (1<<30) +#define STATUS_YBUF_EMPTY (1<<29) +#define STATUS_XBUF_EMPTY (1<<28) +#define STATUS_YBUF_FULL (1<<27) +#define STATUS_XBUF_FULL (1<<26) +#define STATUS_BUF_UND_RUN (1<<25) +#define STATUS_BUF_OVFL (1<<24) +#define STATUS_SDIO_INT_ACTIVE (1<<14) +#define STATUS_END_CMD_RESP (1<<13) +#define STATUS_WRITE_OP_DONE (1<<12) +#define STATUS_READ_OP_DONE (1<<11) +#define STATUS_WR_CRC_ERROR_CODE_MASK (3<<9) +#define STATUS_CARD_BUS_CLK_RUN (1<<8) +#define STATUS_BUF_READ_RDY (1<<7) +#define STATUS_BUF_WRITE_RDY (1<<6) +#define STATUS_RESP_CRC_ERR (1<<5) +#define STATUS_READ_CRC_ERR (1<<3) +#define STATUS_WRITE_CRC_ERR (1<<2) +#define STATUS_TIME_OUT_RESP (1<<1) +#define STATUS_TIME_OUT_READ (1<<0) +#define STATUS_ERR_MASK 0x3f + +/* Clock rate definitions */ +#define CLK_RATE_PRESCALER(x) ((x) & 0xF) +#define CLK_RATE_CLK_DIVIDER(x) (((x) & 0xF) << 4) + +/* Bit definitions for CMD_DAT_CONT */ +#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1<<12) +#define CMD_DAT_CONT_STOP_READWAIT (1<<11) +#define CMD_DAT_CONT_START_READWAIT (1<<10) +#define CMD_DAT_CONT_BUS_WIDTH_1 (0<<8) +#define CMD_DAT_CONT_BUS_WIDTH_4 (2<<8) +#define CMD_DAT_CONT_INIT (1<<7) +#define CMD_DAT_CONT_WRITE (1<<4) +#define CMD_DAT_CONT_DATA_ENABLE (1<<3) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R1 (1) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R2 (2) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R3 (3) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R4 (4) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R5 (5) +#define CMD_DAT_CONT_RESPONSE_FORMAT_R6 (6) + +/* Bit definitions for INT_CNTR */ +#define INT_CNTR_SDIO_INT_WKP_EN (1<<18) +#define INT_CNTR_CARD_INSERTION_WKP_EN (1<<17) +#define INT_CNTR_CARD_REMOVAL_WKP_EN (1<<16) +#define INT_CNTR_CARD_INSERTION_EN (1<<15) +#define INT_CNTR_CARD_REMOVAL_EN (1<<14) +#define INT_CNTR_SDIO_IRQ_EN (1<<13) +#define INT_CNTR_DAT0_EN (1<<12) +#define INT_CNTR_BUF_READ_EN (1<<4) +#define INT_CNTR_BUF_WRITE_EN (1<<3) +#define INT_CNTR_END_CMD_RES (1<<2) +#define INT_CNTR_WRITE_OP_DONE (1<<1) +#define INT_CNTR_READ_OP_DONE (1<<0) + +#endif /* __MXC_MMC_REG_H__ */ diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c new file mode 100644 index 000000000000..bd5e47423129 --- /dev/null +++ b/drivers/mmc/host/mxs-mmc.c @@ -0,0 +1,1327 @@ +/* + * Portions copyright (C) 2003 Russell King, PXA MMCI Driver + * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver + * + * Copyright 2008 Embedded Alley Solutions, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define DRIVER_NAME "mxs-mmc" + +/* + * Card detect polling timeout + */ +#define MXS_MMC_DETECT_TIMEOUT (HZ/2) + +/* Max value supported for XFER_COUNT */ +#define SSP_BUFFER_SIZE (65535) + +#ifndef BF +#define BF(value, field) (((value) << BP_##field) & BM_##field) +#endif + +#ifndef HW_SSP_XFER_SIZE +#define HW_SSP_XFER_SIZE (0xFFFFFFFF) +#endif +#ifndef HW_SSP_BLOCK_SIZE +#define HW_SSP_BLOCK_SIZE (0xFFFFFFFF) +#endif + +#ifndef BP_SSP_XFER_SIZE_XFER_COUNT +#define BP_SSP_XFER_SIZE_XFER_COUNT BP_SSP_CTRL0_XFER_COUNT +#endif +#ifndef BM_SSP_XFER_SIZE_XFER_COUNT +#define BM_SSP_XFER_SIZE_XFER_COUNT BM_SSP_CTRL0_XFER_COUNT +#endif +#ifndef BF_SSP_XFER_SIZE_XFER_COUNT +#define BF_SSP_XFER_SIZE_XFER_COUNT(v) \ + (((v) << 0) & BM_SSP_CTRL0_XFER_COUNT) +#endif + +#ifndef BP_SSP_BLOCK_SIZE_BLOCK_COUNT +#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 8 +#endif +#ifndef BM_SSP_BLOCK_SIZE_BLOCK_COUNT +#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT 0x0000FF00 +#endif +#ifndef BF_SSP_BLOCK_SIZE_BLOCK_COUNT +#define BF_SSP_BLOCK_SIZE_BLOCK_COUNT(v) \ + (((v) << 8) & BM_SSP_BLOCK_SIZE_BLOCK_COUNT) +#endif +#ifndef BP_SSP_BLOCK_SIZE_BLOCK_SIZE +#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 16 +#endif +#ifndef BM_SSP_BLOCK_SIZE_BLOCK_SIZE +#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0x000F0000 +#endif +#ifndef BF_SSP_BLOCK_SIZE_BLOCK_SIZE +#define BF_SSP_BLOCK_SIZE_BLOCK_SIZE(v) \ + (((v) << 16) & BM_SSP_BLOCK_SIZE_BLOCK_SIZE) +#endif +#ifndef BM_SSP_CMD0_DBL_DATA_RATE_EN +#define BM_SSP_CMD0_DBL_DATA_RATE_EN 0x02000000 +#endif + +struct mxs_mmc_host { + struct device *dev; + struct mmc_host *mmc; + + struct clk *clk; + unsigned int clkrt; + + struct mmc_request *mrq; + struct mmc_command *cmd; + struct mmc_data *data; + + /* data bus width 0:1bit, 1:4bit, 2:8bit */ + unsigned char bus_width; + + /* Whether SD card is present */ + unsigned present:1; + + /* Polling timer */ + struct timer_list timer; + + /* SSP interface which MMC/SD card slot is attached to */ + void __iomem *ssp_base; + + /* DMA channel used for this host */ + unsigned int dmach; + + /* IRQs */ + int dmairq, errirq; + + /* DMA descriptor to transfer data over SSP interface */ + struct mxs_dma_desc *dma_desc; + + /* DMA buffer */ + dma_addr_t dma_buf_phys; + char *dma_buf; + + struct completion dma_done; + /* status on last interrupt */ + u32 status; + int read_uA, write_uA; + struct regulator *regulator; /*! Regulator */ + + spinlock_t lock; + int sdio_irq_en; +}; + +/* Return read only state of card */ +static int mxs_mmc_get_ro(struct mmc_host *mmc) +{ + struct mxs_mmc_host *host = mmc_priv(mmc); + struct mxs_mmc_platform_data *mmc_data = host->dev->platform_data; + + if (mmc_data && mmc_data->get_wp) + return mmc_data->get_wp(); + + return 0; +} + +/* Detect if card is plugged */ +static inline int mxs_mmc_is_plugged(struct mxs_mmc_host *host) +{ + u32 status = __raw_readl(host->ssp_base + HW_SSP_STATUS); + return !(status & BM_SSP_STATUS_CARD_DETECT); +} + +static void mxs_mmc_reset(struct mxs_mmc_host *host); +/* Card detection polling function */ +static void mxs_mmc_detect_poll(unsigned long arg) +{ + struct mxs_mmc_host *host = (struct mxs_mmc_host *)arg; + int card_status; + + card_status = mxs_mmc_is_plugged(host); + if (card_status != host->present) { + /* Reset MMC block */ + mxs_mmc_reset(host); + host->present = card_status; + mmc_detect_change(host->mmc, 0); + } + + mod_timer(&host->timer, jiffies + MXS_MMC_DETECT_TIMEOUT); +} + +#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ + BM_SSP_CTRL1_RESP_ERR_IRQ | \ + BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ + BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ + BM_SSP_CTRL1_DATA_CRC_IRQ | \ + BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ + BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ + BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) + +#define MXS_MMC_ERR_BITS (BM_SSP_CTRL1_RESP_ERR_IRQ | \ + BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ + BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ + BM_SSP_CTRL1_DATA_CRC_IRQ | \ + BM_SSP_CTRL1_RECV_TIMEOUT_IRQ) + +/* SSP DMA interrupt handler */ +static irqreturn_t mmc_irq_handler(int irq, void *dev_id) +{ + struct mxs_mmc_host *host = dev_id; + u32 c1; + + c1 = __raw_readl(host->ssp_base + HW_SSP_CTRL1); + __raw_writel(c1 & MXS_MMC_IRQ_BITS, + host->ssp_base + HW_SSP_CTRL1_CLR); + if (irq == host->dmairq) { + dev_dbg(host->dev, "dma irq 0x%x and stop DMA.\n", irq); + mxs_dma_ack_irq(host->dmach); + /* STOP the dma transfer here. */ + mxs_dma_cooked(host->dmach, NULL); + } + + if ((irq == host->dmairq) || (c1 & MXS_MMC_ERR_BITS)) + if (host->cmd) { + host->status = + __raw_readl(host->ssp_base + HW_SSP_STATUS); + complete(&host->dma_done); + } + + if ((c1 & BM_SSP_CTRL1_SDIO_IRQ) && (c1 & BM_SSP_CTRL1_SDIO_IRQ_EN)) + mmc_signal_sdio_irq(host->mmc); + + return IRQ_HANDLED; +} + +/* + * Check for MMC command errors + * Returns error code or zerro if no errors + */ +static inline int mxs_mmc_cmd_error(u32 status) +{ + int err = 0; + + if (status & BM_SSP_STATUS_TIMEOUT) + err = -ETIMEDOUT; + else if (status & BM_SSP_STATUS_RESP_TIMEOUT) + err = -ETIMEDOUT; + else if (status & BM_SSP_STATUS_RESP_CRC_ERR) + err = -EILSEQ; + else if (status & BM_SSP_STATUS_RESP_ERR) + err = -EIO; + + return err; +} + +/* Send the BC command to the device */ +static void mxs_mmc_bc(struct mxs_mmc_host *host) +{ + struct mmc_command *cmd = host->cmd; + struct mxs_dma_desc *dma_desc = host->dma_desc; + unsigned long flags; + + dma_desc->cmd.cmd.bits.command = NO_DMA_XFER; + dma_desc->cmd.cmd.bits.irq = 1; + dma_desc->cmd.cmd.bits.dec_sem = 1; + dma_desc->cmd.cmd.bits.wait4end = 1; + dma_desc->cmd.cmd.bits.pio_words = 3; + dma_desc->cmd.cmd.bits.bytes = 0; + + dma_desc->cmd.pio_words[0] = BM_SSP_CTRL0_ENABLE | + BM_SSP_CTRL0_IGNORE_CRC; + dma_desc->cmd.pio_words[1] = BF(cmd->opcode, SSP_CMD0_CMD) | + BM_SSP_CMD0_APPEND_8CYC; + dma_desc->cmd.pio_words[2] = BF(cmd->arg, SSP_CMD1_CMD_ARG); + + if (host->sdio_irq_en) { + dma_desc->cmd.pio_words[0] |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; + dma_desc->cmd.pio_words[1] |= BM_SSP_CMD0_CONT_CLKING_EN \ + | BM_SSP_CMD0_SLOW_CLKING_EN; + } + + init_completion(&host->dma_done); + mxs_dma_reset(host->dmach); + if (mxs_dma_desc_append(host->dmach, host->dma_desc) < 0) + dev_err(host->dev, "mmc_dma_desc_append failed\n"); + dev_dbg(host->dev, "%s start DMA.\n", __func__); + if (mxs_dma_enable(host->dmach) < 0) + dev_err(host->dev, "mmc_dma_enable failed\n"); + + wait_for_completion(&host->dma_done); + + cmd->error = mxs_mmc_cmd_error(host->status); + + if (cmd->error) { + dev_dbg(host->dev, "Command error 0x%x\n", cmd->error); + mxs_dma_reset(host->dmach); + } + mxs_dma_disable(host->dmach); +} + +/* Send the ac command to the device */ +static void mxs_mmc_ac(struct mxs_mmc_host *host) +{ + struct mmc_command *cmd = host->cmd; + struct mxs_dma_desc *dma_desc = host->dma_desc; + u32 ignore_crc, resp, long_resp; + u32 ssp_ctrl0; + u32 ssp_cmd0; + u32 ssp_cmd1; + unsigned long flags; + + ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? + 0 : BM_SSP_CTRL0_IGNORE_CRC; + resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? + BM_SSP_CTRL0_GET_RESP : 0; + long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? + BM_SSP_CTRL0_LONG_RESP : 0; + + dma_desc->cmd.cmd.bits.command = NO_DMA_XFER; + dma_desc->cmd.cmd.bits.irq = 1; + dma_desc->cmd.cmd.bits.dec_sem = 1; + dma_desc->cmd.cmd.bits.wait4end = 1; + dma_desc->cmd.cmd.bits.pio_words = 3; + dma_desc->cmd.cmd.bits.bytes = 0; + + ssp_ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | long_resp | resp; + ssp_cmd0 = BF(cmd->opcode, SSP_CMD0_CMD); + ssp_cmd1 = BF(cmd->arg, SSP_CMD1_CMD_ARG); + + if (host->sdio_irq_en) { + ssp_ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; + ssp_cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN \ + | BM_SSP_CMD0_SLOW_CLKING_EN; + } + + dma_desc->cmd.pio_words[0] = ssp_ctrl0; + dma_desc->cmd.pio_words[1] = ssp_cmd0; + dma_desc->cmd.pio_words[2] = ssp_cmd1; + + mxs_dma_reset(host->dmach); + init_completion(&host->dma_done); + if (mxs_dma_desc_append(host->dmach, host->dma_desc) < 0) + dev_err(host->dev, "mmc_dma_desc_append failed\n"); + dev_dbg(host->dev, "%s start DMA.\n", __func__); + if (mxs_dma_enable(host->dmach) < 0) + dev_err(host->dev, "mmc_dma_enable failed\n"); + wait_for_completion(&host->dma_done); + + switch (mmc_resp_type(cmd)) { + case MMC_RSP_NONE: + while (__raw_readl(host->ssp_base + HW_SSP_CTRL0) + & BM_SSP_CTRL0_RUN) + continue; + break; + case MMC_RSP_R1: + case MMC_RSP_R1B: + case MMC_RSP_R3: + cmd->resp[0] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP0); + break; + case MMC_RSP_R2: + cmd->resp[3] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP0); + cmd->resp[2] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP1); + cmd->resp[1] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP2); + cmd->resp[0] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP3); + break; + default: + dev_warn(host->dev, "Unsupported response type 0x%x\n", + mmc_resp_type(cmd)); + BUG(); + break; + } + + cmd->error = mxs_mmc_cmd_error(host->status); + + if (cmd->error) { + dev_dbg(host->dev, "Command error 0x%x\n", cmd->error); + mxs_dma_reset(host->dmach); + } + mxs_dma_disable(host->dmach); +} + +/* Copy data between sg list and dma buffer */ +static unsigned int mxs_sg_dma_copy(struct mxs_mmc_host *host, + unsigned int size, int to_dma) +{ + struct mmc_data *data = host->cmd->data; + unsigned int copy_size, bytes_copied = 0; + struct scatterlist *sg; + char *dmabuf = host->dma_buf; + char *sgbuf; + int len, i; + + sg = data->sg; + len = data->sg_len; + + /* + * Just loop through all entries. Size might not + * be the entire list though so make sure that + * we do not transfer too much. + */ + for (i = 0; i < len; i++) { + sgbuf = kmap_atomic(sg_page(&sg[i]), KM_BIO_SRC_IRQ) + + sg[i].offset; + copy_size = size < sg[i].length ? size : sg[i].length; + if (to_dma) + memcpy(dmabuf, sgbuf, copy_size); + else + memcpy(sgbuf, dmabuf, copy_size); + kunmap_atomic(sgbuf, KM_BIO_SRC_IRQ); + + dmabuf += sg[i].length; + + bytes_copied += copy_size; + size -= copy_size; + + if (size == 0) + break; + } + + return bytes_copied; +} + +/* Convert ns to tick count according to the current sclk speed */ +static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) +{ + const unsigned int ssp_timeout_mul = 4096; + /* + * Calculate ticks in ms since ns are large numbers + * and might overflow + */ + const unsigned int clock_per_ms = clock_rate / 1000; + const unsigned int ms = ns / 1000; + const unsigned int ticks = ms * clock_per_ms; + const unsigned int ssp_ticks = ticks / ssp_timeout_mul; + + BUG_ON(ssp_ticks == 0); + return ssp_ticks; +} + +static void __init_reg(struct device *dev, struct regulator **pp_reg) +{ +#if 0 + /* Up to now, there is not pwr ctrl. Just keep it for future usage. */ + struct regulator *reg = *pp_reg; + + if (!reg) { + reg = regulator_get(NULL, "mmc_ssp-1"); + if (reg && !IS_ERR(reg)) + regulator_set_mode(reg, REGULATOR_MODE_NORMAL); + else + reg = NULL; + *pp_reg = reg; + } +#endif +} + +/* Send adtc command to the card */ +static void mxs_mmc_adtc(struct mxs_mmc_host *host) +{ + struct mmc_command *cmd = host->cmd; + struct mxs_dma_desc *dma_desc = host->dma_desc; + int ignore_crc, resp, long_resp; + int is_reading = 0; + unsigned int copy_size; + unsigned int ssp_ver_major; + + u32 ssp_ctrl0; + u32 ssp_cmd0; + u32 ssp_cmd1; + u32 timeout; + u32 val; + + u32 data_size = cmd->data->blksz * cmd->data->blocks; + u32 log2_block_size; + unsigned long flags; + + ignore_crc = mmc_resp_type(cmd) & MMC_RSP_CRC ? 0 : 1; + resp = mmc_resp_type(cmd) & MMC_RSP_PRESENT ? 1 : 0; + long_resp = mmc_resp_type(cmd) & MMC_RSP_136 ? 1 : 0; + + dev_dbg(host->dev, "ADTC command:\n" + "response: %d, ignore crc: %d\n" + "data list: %u, blocksz: %u, blocks: %u, timeout: %uns %uclks, " + "flags: 0x%x\n", resp, ignore_crc, cmd->data->sg_len, + cmd->data->blksz, cmd->data->blocks, cmd->data->timeout_ns, + cmd->data->timeout_clks, cmd->data->flags); + + if (cmd->data->flags & MMC_DATA_WRITE) { + dev_dbg(host->dev, "Data Write\n"); + copy_size = mxs_sg_dma_copy(host, data_size, 1); + BUG_ON(copy_size < data_size); + is_reading = 0; + if (!host->regulator) + __init_reg(host->dev, &host->regulator); + if (host->regulator) + regulator_set_current_limit(host->regulator, + host->write_uA, + host->write_uA); + } else if (cmd->data->flags & MMC_DATA_READ) { + dev_dbg(host->dev, "Data Read\n"); + is_reading = 1; + if (!host->regulator) + __init_reg(host->dev, &host->regulator); + if (host->regulator) + regulator_set_current_limit(host->regulator, + host->read_uA, + host->read_uA); + } else { + dev_warn(host->dev, "Unsuspported data mode, 0x%x\n", + cmd->data->flags); + BUG(); + } + + BUG_ON(cmd->data->flags & MMC_DATA_STREAM); + /* BUG_ON((data_size % 8) > 0); */ + + /* when is_reading is set, DMA controller performs WRITE operation. */ + dma_desc->cmd.cmd.bits.command = is_reading ? DMA_WRITE : DMA_READ; + dma_desc->cmd.cmd.bits.irq = 1; + dma_desc->cmd.cmd.bits.dec_sem = 1; + dma_desc->cmd.cmd.bits.wait4end = 1; + dma_desc->cmd.cmd.bits.pio_words = 3; + dma_desc->cmd.cmd.bits.bytes = data_size; + + ssp_ver_major = __raw_readl(host->ssp_base + HW_SSP_VERSION) >> 24; + dev_dbg(host->dev, "ssp ver major is 0x%x\n", ssp_ver_major); + if (ssp_ver_major > 3) { + __raw_writel(data_size, host->ssp_base + HW_SSP_XFER_SIZE); + ssp_ctrl0 = (ignore_crc ? BM_SSP_CTRL0_IGNORE_CRC : 0) | + (resp ? BM_SSP_CTRL0_GET_RESP : 0) | + (long_resp ? BM_SSP_CTRL0_LONG_RESP : 0) | + (is_reading ? BM_SSP_CTRL0_READ : 0) | + BM_SSP_CTRL0_DATA_XFER | BM_SSP_CTRL0_WAIT_FOR_IRQ | + BM_SSP_CTRL0_ENABLE; + if (host->bus_width == 2) + ssp_ctrl0 |= BF(BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT, + SSP_CTRL0_BUS_WIDTH); + else if (host->bus_width == 1) + ssp_ctrl0 |= BF(BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT, + SSP_CTRL0_BUS_WIDTH); + else + ssp_ctrl0 |= BF(BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT, + SSP_CTRL0_BUS_WIDTH); + } else + ssp_ctrl0 = (ignore_crc ? BM_SSP_CTRL0_IGNORE_CRC : 0) | + (resp ? BM_SSP_CTRL0_GET_RESP : 0) | + (long_resp ? BM_SSP_CTRL0_LONG_RESP : 0) | + (is_reading ? BM_SSP_CTRL0_READ : 0) | + BM_SSP_CTRL0_DATA_XFER | BM_SSP_CTRL0_WAIT_FOR_IRQ | + BM_SSP_CTRL0_ENABLE | + BF(data_size, SSP_XFER_SIZE_XFER_COUNT) | + BF(host->bus_width ? + BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT : + BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT, + SSP_CTRL0_BUS_WIDTH); + + /* + * We need to set the hardware register to the logarithm to base 2 of + * the block size. + */ + log2_block_size = ilog2(cmd->data->blksz); + dev_dbg(host->dev, "%s blksz is 0x%x.\n", __func__, log2_block_size); + + if (ssp_ver_major > 3) { + /* Configure the CMD0 */ + ssp_cmd0 = BF(cmd->opcode, SSP_CMD0_CMD); + + /* Configure the BLOCK SIZE and BLOCK COUNT */ + if ((1<data->blksz) { + BUG_ON(cmd->data->blocks > 1); + __raw_writel(0, host->ssp_base + HW_SSP_BLOCK_SIZE); + } else{ + val = BF(log2_block_size, SSP_BLOCK_SIZE_BLOCK_SIZE) | + BF(cmd->data->blocks - 1, SSP_BLOCK_SIZE_BLOCK_COUNT); + __raw_writel(val, host->ssp_base + HW_SSP_BLOCK_SIZE); + if (host->mmc->ios.bus_width & MMC_BUS_WIDTH_DDR) { + /* + * Enable the DDR mode + * Make sure the POLARITY bit is cleared + */ + __raw_writel(BM_SSP_CTRL1_POLARITY, \ + host->ssp_base + HW_SSP_CTRL1_CLR); + ssp_cmd0 |= BM_SSP_CMD0_DBL_DATA_RATE_EN; + } else { + __raw_writel(BM_SSP_CTRL1_POLARITY, \ + host->ssp_base + HW_SSP_CTRL1_SET); + ssp_cmd0 &= ~BM_SSP_CMD0_DBL_DATA_RATE_EN; + } + + } + } else { + if ((1<data->blksz) { + BUG_ON(cmd->data->blocks > 1); + ssp_cmd0 = + BF(0, SSP_BLOCK_SIZE_BLOCK_SIZE) | + BF(cmd->opcode, SSP_CMD0_CMD) | + BF(0, SSP_BLOCK_SIZE_BLOCK_COUNT); + } else + ssp_cmd0 = + BF(log2_block_size, SSP_BLOCK_SIZE_BLOCK_SIZE) | + BF(cmd->opcode, SSP_CMD0_CMD) | + BF(cmd->data->blocks - 1, SSP_BLOCK_SIZE_BLOCK_COUNT); + } + if (host->sdio_irq_en) { + ssp_ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; + ssp_cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN \ + | BM_SSP_CMD0_SLOW_CLKING_EN; + } + if ((cmd->opcode == 12) || (cmd->opcode == 53)) + ssp_cmd0 |= BM_SSP_CMD0_APPEND_8CYC; + + ssp_cmd1 = BF(cmd->arg, SSP_CMD1_CMD_ARG); + + dma_desc->cmd.pio_words[0] = ssp_ctrl0; + dma_desc->cmd.pio_words[1] = ssp_cmd0; + dma_desc->cmd.pio_words[2] = ssp_cmd1; + + /* Set the timeout count */ + timeout = mxs_ns_to_ssp_ticks(host->clkrt, cmd->data->timeout_ns); + val = __raw_readl(host->ssp_base + HW_SSP_TIMING); + val &= ~(BM_SSP_TIMING_TIMEOUT); + val |= BF(timeout, SSP_TIMING_TIMEOUT); + __raw_writel(val, host->ssp_base + HW_SSP_TIMING); + + init_completion(&host->dma_done); + mxs_dma_reset(host->dmach); + if (mxs_dma_desc_append(host->dmach, host->dma_desc) < 0) + dev_err(host->dev, "mmc_dma_desc_append failed\n"); + dev_dbg(host->dev, "%s start DMA.\n", __func__); + if (mxs_dma_enable(host->dmach) < 0) + dev_err(host->dev, "mmc_dma_enable failed\n"); + wait_for_completion(&host->dma_done); + if (host->regulator) + regulator_set_current_limit(host->regulator, 0, 0); + + switch (mmc_resp_type(cmd)) { + case MMC_RSP_NONE: + break; + case MMC_RSP_R1: + case MMC_RSP_R3: + cmd->resp[0] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP0); + break; + case MMC_RSP_R2: + cmd->resp[3] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP0); + cmd->resp[2] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP1); + cmd->resp[1] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP2); + cmd->resp[0] = + __raw_readl(host->ssp_base + HW_SSP_SDRESP3); + break; + default: + dev_warn(host->dev, "Unsupported response type 0x%x\n", + mmc_resp_type(cmd)); + BUG(); + break; + } + + cmd->error = mxs_mmc_cmd_error(host->status); + + if (cmd->error) { + dev_dbg(host->dev, "Command error 0x%x\n", cmd->error); + mxs_dma_reset(host->dmach); + } else { + if (is_reading) { + cmd->data->bytes_xfered = + mxs_sg_dma_copy(host, data_size, 0); + } else + cmd->data->bytes_xfered = data_size; + + dev_dbg(host->dev, "Transferred %u bytes\n", + cmd->data->bytes_xfered); + } + mxs_dma_disable(host->dmach); +} + +/* Begin sedning a command to the card */ +static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, + struct mmc_command *cmd) +{ + dev_dbg(host->dev, "MMC command:\n" + "type: 0x%x opcode: %u, arg: %u, flags 0x%x retries: %u\n", + mmc_cmd_type(cmd), cmd->opcode, cmd->arg, cmd->flags, + cmd->retries); + + host->cmd = cmd; + + switch (mmc_cmd_type(cmd)) { + case MMC_CMD_BC: + mxs_mmc_bc(host); + break; + case MMC_CMD_BCR: + mxs_mmc_ac(host); + break; + case MMC_CMD_AC: + mxs_mmc_ac(host); + break; + case MMC_CMD_ADTC: + mxs_mmc_adtc(host); + break; + default: + dev_warn(host->dev, "Unknown MMC command\n"); + BUG(); + break; + } + + dev_dbg(host->dev, "response: %u %u %u %u errors: %u\n", + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], + cmd->error); +} + +/* Handle MMC request */ +static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct mxs_mmc_host *host = mmc_priv(mmc); + + dev_dbg(host->dev, "MMC request\n"); + BUG_ON(host->mrq != NULL); + host->mrq = mrq; + + mxs_mmc_start_cmd(host, mrq->cmd); + + if (mrq->data && mrq->data->stop) { + dev_dbg(host->dev, "Stop opcode is %u\n", + mrq->data->stop->opcode); + mxs_mmc_start_cmd(host, mrq->data->stop); + } + + host->mrq = NULL; + mmc_request_done(mmc, mrq); +} + +/* + * Change divisors to reflect the rate of 'hz'. Note that we should not + * play with clock rate, because the same source is used to clock both + * SSP ports. + */ +static void +mxs_set_sclk_speed(struct mxs_mmc_host *host, unsigned int hz) +{ + unsigned long ssp, bus_clk = 0; + u32 div1, div2; + u32 val; + struct mxs_mmc_platform_data *mmc_data = host->dev->platform_data; + + if (mmc_data && mmc_data->setclock) { + /* using SSP1, no timeout, clock rate 1 */ + __raw_writel(BF(0xFFFF, SSP_TIMING_TIMEOUT) | + BF(2, SSP_TIMING_CLOCK_DIVIDE) | + BF(0, SSP_TIMING_CLOCK_RATE), + host->ssp_base + HW_SSP_TIMING); + + /* + if the SSP is buggy and platform provides callback... + well, let it be. + */ + host->clkrt = mmc_data->setclock(hz); + dev_dbg(host->dev, "Setting clock rate to %d Hz" + "(requested %d)\n", + host->clkrt, hz); + dev_dbg(host->dev, "source %ldk\n", + clk_get_rate(host->clk)); + + return; + } + + /* + ...but the RightIdea(tm) is to set divisors to match + the requested clock. + */ + ssp = clk_get_rate(host->clk); + + for (div1 = 2; div1 < 254; div1 += 2) { + div2 = ssp / hz / div1; + if (div2 < 0x100) + break; + } + if (div1 >= 254) { + dev_err(host->dev, "Cannot set clock to %dHz\n", hz); + return; + } + + if (div2 == 0) + bus_clk = ssp / div1; + else + bus_clk = ssp / div1 / div2; + + dev_dbg(host->dev, "Setting clock rate to %ld Hz [%x+%x] " + "(requested %d), source %ldk\n", + bus_clk, div1, div2, hz, ssp); + + val = __raw_readl(host->ssp_base + HW_SSP_TIMING); + val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); + val |= BF(div1, SSP_TIMING_CLOCK_DIVIDE) | + BF(div2 - 1, SSP_TIMING_CLOCK_RATE); + __raw_writel(val, host->ssp_base + HW_SSP_TIMING); + + host->clkrt = bus_clk; +} + +/* Configure card */ +static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct mxs_mmc_host *host = mmc_priv(mmc); + struct mxs_mmc_platform_data *mmc_data; + + dev_dbg(host->dev, "MMC set ios:\n" + "Clock %u, vdd %u, bus_mode %u, chip_select %u, " + "power mode %u, bus_width %u\n", ios->clock, ios->vdd, + ios->bus_mode, ios->chip_select, ios->power_mode, + ios->bus_width); + + mmc_data = host->dev->platform_data; + + if (mmc_data->cmd_pullup) { + if (ios->bus_mode == MMC_BUSMODE_PUSHPULL) + mmc_data->cmd_pullup(0); + else + mmc_data->cmd_pullup(1); + } else + dev_warn(host->dev, + "Platform does not support CMD pin pullup control\n"); + + if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_8) + host->bus_width = 2; + else if ((ios->bus_width & ~MMC_BUS_WIDTH_DDR) == MMC_BUS_WIDTH_4) + host->bus_width = 1; + else + host->bus_width = 0; + dev_dbg(host->dev, "MMC bus_width %u\n", host->bus_width); + + if (ios->clock > 0) + mxs_set_sclk_speed(host, ios->clock); +} + +static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) +{ + unsigned long flags; + struct mxs_mmc_host *host = mmc_priv(mmc); + + spin_lock_irqsave(&host->lock, flags); + + if (enable) { + if (host->sdio_irq_en) + goto exit; + host->sdio_irq_en = 1; + __raw_writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, host->ssp_base + \ + HW_SSP_CTRL0_SET); + __raw_writel(BM_SSP_CTRL1_SDIO_IRQ_EN, host->ssp_base + \ + HW_SSP_CTRL1_SET); + + if (__raw_readl(host->ssp_base + \ + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ) + mmc_signal_sdio_irq(host->mmc); + + } else { + if (host->sdio_irq_en == 0) + goto exit; + host->sdio_irq_en = 0; + __raw_writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, \ + host->ssp_base + HW_SSP_CTRL0_CLR); + __raw_writel(BM_SSP_CTRL1_SDIO_IRQ_EN, \ + host->ssp_base + HW_SSP_CTRL1_CLR); + } + +exit: + spin_unlock_irqrestore(&host->lock, flags); + return; +} + +static const struct mmc_host_ops mxs_mmc_ops = { + .request = mxs_mmc_request, + .get_ro = mxs_mmc_get_ro, + .set_ios = mxs_mmc_set_ios, + .enable_sdio_irq = mxs_mmc_enable_sdio_irq, +}; + +/* + * MXS MMC/SD driver initialization + */ + +/* Reset ssp peripheral to default values */ +static void mxs_mmc_reset(struct mxs_mmc_host *host) +{ + u32 ssp_ctrl0; + u32 ssp_ctrl1; + + mxs_reset_block(host->ssp_base, 0); + + /* Configure SSP Control Register 0 */ + ssp_ctrl0 = + BM_SSP_CTRL0_IGNORE_CRC | + BF(BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT, SSP_CTRL0_BUS_WIDTH); + + /* Configure SSP Control Register 1 */ + ssp_ctrl1 = + BM_SSP_CTRL1_DMA_ENABLE | + BM_SSP_CTRL1_POLARITY | + BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | + BM_SSP_CTRL1_DATA_CRC_IRQ_EN | + BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | + BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | + BM_SSP_CTRL1_RESP_ERR_IRQ_EN | + BF(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS, SSP_CTRL1_WORD_LENGTH) | + BF(BV_SSP_CTRL1_SSP_MODE__SD_MMC, SSP_CTRL1_SSP_MODE); + + __raw_writel(BF(0xFFFF, SSP_TIMING_TIMEOUT) | + BF(2, SSP_TIMING_CLOCK_DIVIDE) | + BF(0, SSP_TIMING_CLOCK_RATE), + host->ssp_base + HW_SSP_TIMING); + + if (host->sdio_irq_en) { + ssp_ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; + ssp_ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; + } + + /* Write the SSP Control Register 0 and 1 values out to the interface */ + __raw_writel(ssp_ctrl0, host->ssp_base + HW_SSP_CTRL0); + __raw_writel(ssp_ctrl1, host->ssp_base + HW_SSP_CTRL1); +} + +static void mxs_mmc_irq_release(struct mxs_mmc_host *host) +{ + free_irq(host->dmairq, host); + free_irq(host->errirq, host); +} + +static int __init mxs_mmc_irq_init(struct mxs_mmc_host *host) +{ + int ret; + + ret = request_irq(host->dmairq, mmc_irq_handler, 0, + DRIVER_NAME " dma", host); + if (ret) { + dev_err(host->dev, "Unable to set up DMA irq handler\n"); + goto out0; + } + + ret = request_irq(host->errirq, mmc_irq_handler, IRQF_SHARED, + DRIVER_NAME " error", host); + if (ret) { + dev_err(host->dev, "Unable to set up SSP error irq handler\n"); + goto out1; + } + return 0; + +out1: + free_irq(host->dmairq, host); +out0: + return ret; +} + +/* Allocate and initialise the DMA chains */ +static int mxs_mmc_dma_init(struct mxs_mmc_host *host, int reset) +{ + int ret = 0; + + if (!reset) { + /* Allocate DMA channel */ + ret = mxs_dma_request(host->dmach, + host->dev, "MXS MMC/SD"); + if (ret) { + dev_err(host->dev, "Unable to request DMA channel\n"); + return ret; + } + + host->dma_buf = dma_alloc_coherent(host->dev, SSP_BUFFER_SIZE, + &host->dma_buf_phys, + GFP_DMA); + if (host->dma_buf == NULL) { + dev_err(host->dev, "Unable to allocate DMA memory\n"); + ret = -ENOMEM; + goto out_mem; + } + + host->dma_desc = mxs_dma_alloc_desc(); + if (host->dma_desc == NULL) { + dev_err(host->dev, + "Unable to allocate DMA descriptor\n"); + ret = -ENOMEM; + goto out_cmd; + } + + host->dma_desc->cmd.next = (u32) host->dma_desc->address; + host->dma_desc->cmd.address = (u32) host->dma_buf_phys; + host->dma_desc->buffer = host->dma_buf; + } + + /* Reset DMA channel */ + mxs_dma_reset(host->dmach); + + /* Enable DMA interrupt */ + mxs_dma_ack_irq(host->dmach); + mxs_dma_enable_irq(host->dmach, 1); + + return 0; + +out_cmd: + dma_free_coherent(host->dev, SSP_BUFFER_SIZE, host->dma_buf, + host->dma_buf_phys); +out_mem: + mxs_dma_release(host->dmach, host->dev); + + return ret; +} + +static void mxs_mmc_dma_release(struct mxs_mmc_host *host) +{ + mxs_dma_reset(host->dmach); + + mxs_dma_enable_irq(host->dmach, 0); + mxs_dma_disable(host->dmach); + mxs_dma_get_cooked(host->dmach, NULL); + + dma_free_coherent(host->dev, SSP_BUFFER_SIZE, host->dma_buf, + host->dma_buf_phys); + + mxs_dma_free_desc(host->dma_desc); + mxs_dma_release(host->dmach, host->dev); +} + +/* Probe peripheral for connected cards */ +static int __init mxs_mmc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mxs_mmc_platform_data *mmc_data; + struct mxs_mmc_host *host; + struct mmc_host *mmc; + struct resource *r; + int err = 0; + unsigned int ssp_ver_major; + + mmc_data = dev->platform_data; + if (mmc_data == NULL) { + err = -EINVAL; + dev_err(dev, "Missing platform data\n"); + goto out; + } + + /* Allocate main MMC host structure */ + mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), dev); + if (!mmc) { + dev_err(dev, "Unable to allocate MMC host\n"); + err = -ENOMEM; + goto out; + } + host = mmc_priv(mmc); + + host->read_uA = mmc_data->read_uA; + host->write_uA = mmc_data->write_uA; + if (mmc_data->power_mmc != NULL) + host->regulator = regulator_get(NULL, mmc_data->power_mmc); + if (host->regulator && !IS_ERR(host->regulator)) + regulator_set_mode(host->regulator, REGULATOR_MODE_NORMAL); + else + host->regulator = NULL; + + /* get resources: */ + + /* + * 1. io memory + */ + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "failed to get IORESOURCE_MEM\n"); + err = -ENXIO; + goto out_res; + } + host->ssp_base = IO_ADDRESS(r->start); + + /* + * 2. DMA channel + */ + r = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!r) { + dev_err(&pdev->dev, "failed to get IORESOURCE_DMA\n"); + err = -ENXIO; + goto out_res; + } + host->dmach = r->start; + + /* + * 3. two IRQs + */ + host->dmairq = platform_get_irq(pdev, 0); + if (host->dmairq < 0) { + dev_err(&pdev->dev, "failed to get IORESOURCE_IRQ/0\n"); + err = host->dmairq; + goto out_res; + } + + host->errirq = platform_get_irq(pdev, 1); + if (host->errirq < 0) { + dev_err(&pdev->dev, "failed to get IORESOURCE_IRQ/1\n"); + err = host->errirq; + goto out_res; + } + + /* Set up MMC pins */ + if (mmc_data->hw_init) { + err = mmc_data->hw_init(); + if (err) { + dev_err(dev, "MMC HW configuration failed\n"); + goto out_res; + } + } + + host->mmc = mmc; + host->dev = dev; + + host->sdio_irq_en = 0; + + /* Set minimal clock rate */ + host->clk = clk_get(dev, mmc_data->clock_mmc); + if (IS_ERR(host->clk)) { + err = PTR_ERR(host->clk); + dev_err(dev, "Clocks initialization failed\n"); + goto out_clk; + } + + clk_enable(host->clk); + mxs_set_sclk_speed(host, mmc_data->min_clk); + + /* Reset MMC block */ + mxs_mmc_reset(host); + + /* Enable DMA */ + err = mxs_mmc_dma_init(host, 0); + if (err) { + dev_err(dev, "DMA init failed\n"); + goto out_dma; + } + + /* Set up interrupt handlers */ + err = mxs_mmc_irq_init(host); + if (err) { + dev_err(dev, "IRQ initialization failed\n"); + goto out_irq; + } + + /* Get current card status for further cnanges tracking */ + host->present = mxs_mmc_is_plugged(host); + + /* Add a card detection polling timer */ + init_timer(&host->timer); + host->timer.function = mxs_mmc_detect_poll; + host->timer.data = (unsigned long)host; + host->timer.expires = jiffies + MXS_MMC_DETECT_TIMEOUT; + add_timer(&host->timer); + + mmc->ops = &mxs_mmc_ops; + mmc->f_min = mmc_data->min_clk; + mmc->f_max = mmc_data->max_clk; + mmc->caps = mmc_data->caps; + mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; + mmc->caps |= MMC_CAP_SDIO_IRQ; + + /* Maximum block count requests. */ + mmc->max_blk_size = 512; + ssp_ver_major = __raw_readl(host->ssp_base + HW_SSP_VERSION) >> 24; + dev_dbg(host->dev, "ssp ver major is 0x%x\n", ssp_ver_major); + if (ssp_ver_major > 3) { + mmc->max_blk_count = SSP_BUFFER_SIZE / 512; + mmc->max_hw_segs = SSP_BUFFER_SIZE / 512; + mmc->max_phys_segs = SSP_BUFFER_SIZE / 512; + mmc->max_req_size = SSP_BUFFER_SIZE; + mmc->max_seg_size = SSP_BUFFER_SIZE; + } else { + mmc->max_blk_count = SSP_BUFFER_SIZE / 512 - 1; + mmc->max_hw_segs = SSP_BUFFER_SIZE / 512 - 1; + mmc->max_phys_segs = SSP_BUFFER_SIZE / 512 - 1; + mmc->max_req_size = SSP_BUFFER_SIZE - 512; + mmc->max_seg_size = SSP_BUFFER_SIZE - 512; + } + + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + + platform_set_drvdata(pdev, mmc); + + spin_lock_init(&host->lock); + + err = mmc_add_host(mmc); + if (err) { + dev_err(dev, "Oh God. mmc_add_host failed\n"); + goto out_all; + } + + dev_info(&pdev->dev, "%s: MXS SSP MMC DMAIRQ %d ERRIRQ %d \n", + mmc_hostname(mmc), host->dmairq, host->errirq); + + return err; + +out_all: + +out_irq: + mxs_mmc_dma_release(host); +out_dma: + clk_disable(host->clk); +out_clk: + if (mmc_data->hw_release) + mmc_data->hw_release(); +out_res: + mmc_free_host(mmc); +out: + return err; +} + +static int __exit mxs_mmc_remove(struct platform_device *pdev) +{ + struct mxs_mmc_host *host; + struct mxs_mmc_platform_data *mmc_data; + struct mmc_host *mmc; + + dev_info(&pdev->dev, "Removing\n"); + + mmc_data = pdev->dev.platform_data; + mmc = platform_get_drvdata(pdev); + platform_set_drvdata(pdev, NULL); + + host = mmc_priv(mmc); + mmc_remove_host(mmc); + + /* Disable SSP clock */ + clk_disable(host->clk); + clk_put(host->clk); + + /* Release IRQs */ + mxs_mmc_irq_release(host); + + /* Delete card detection timer */ + del_timer(&host->timer); + + /* Release DMA */ + mxs_mmc_dma_release(host); + if (host->regulator) + regulator_put(host->regulator); + + mmc_free_host(mmc); + + if (mmc_data->hw_release) + mmc_data->hw_release(); + + return 0; +} + +#ifdef CONFIG_PM +static int mxs_mmc_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct mxs_mmc_host *host; + struct mxs_mmc_platform_data *mmc_data; + struct mmc_host *mmc; + int ret = 0; + + dev_dbg(&pdev->dev, "Suspending\n"); + + mmc_data = pdev->dev.platform_data; + mmc = platform_get_drvdata(pdev); + host = mmc_priv(mmc); + + ret = mmc_suspend_host(mmc); + if (!ret) { + if (mmc_data && mmc_data->hw_release) + mmc_data->hw_release(); + clk_disable(host->clk); + } + return ret; +} + +static int mxs_mmc_resume(struct platform_device *pdev) +{ + struct mxs_mmc_host *host; + struct mxs_mmc_platform_data *mmc_data; + struct mmc_host *mmc; + + dev_dbg(&pdev->dev, "Resuming\n"); + + mmc_data = pdev->dev.platform_data; + mmc = platform_get_drvdata(pdev); + host = mmc_priv(mmc); + + clk_enable(host->clk); + + if (mmc_data->hw_init) + mmc_data->hw_init(); + mxs_mmc_reset(host); + mxs_mmc_dma_init(host, 1); + + return mmc_resume_host(mmc); +} +#else +#define mxs_mmc_suspend NULL +#define mxs_mmc_resume NULL +#endif /* CONFIG_PM */ + +static struct platform_driver mxs_mmc_driver = { + .probe = mxs_mmc_probe, + .remove = __exit_p(mxs_mmc_remove), + .suspend = mxs_mmc_suspend, + .resume = mxs_mmc_resume, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init mxs_mmc_init(void) +{ + int ret = 0; + + printk(KERN_INFO DRIVER_NAME + ": MXS SSP Controller MMC Interface driver\n"); + ret = platform_driver_register(&mxs_mmc_driver); + if (ret < 0) + return ret; + + return ret; +} + +static void __exit mxs_mmc_exit(void) +{ + platform_driver_unregister(&mxs_mmc_driver); +} + +module_init(mxs_mmc_init); +module_exit(mxs_mmc_exit); + +MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index f8210bf2d241..20224423d617 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -342,4 +342,12 @@ source "drivers/mtd/lpddr/Kconfig" source "drivers/mtd/ubi/Kconfig" +config MTD_UBI_BLOCK + tristate "Simple mtdblock-like FTL over UBI volumes" + depends on MTD_UBI + select MTD_BLKDEVS + default n + help + This enables cached block access to UBI volumes + endif # MTD diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 760abc533395..d3fbad6e434e 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -33,3 +33,4 @@ inftl-objs := inftlcore.o inftlmount.o obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ obj-$(CONFIG_MTD_UBI) += ubi/ +obj-$(CONFIG_MTD_UBI_BLOCK) += ubiblock.o diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig index 35081ce77fbd..5079ad7553f0 100644 --- a/drivers/mtd/devices/Kconfig +++ b/drivers/mtd/devices/Kconfig @@ -78,6 +78,14 @@ config MTD_DATAFLASH_OTP other key product data. The second half is programmed with a unique-to-each-chip bit pattern at the factory. +config MTD_MXC_DATAFLASH + tristate "Support for AT DataFlash via FSL SPI interface" + depends on SPI_MASTER && EXPERIMENTAL + help + This enables access to AT DataFlash chips, using FSL SPI. + Sometimes DataFlash chips are packaged inside MMC-format + cards; at this writing, the MMC stack won't handle those. + config MTD_M25P80 tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)" depends on SPI_MASTER && EXPERIMENTAL diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile index f3226b1d38fc..93a8fefbefdf 100644 --- a/drivers/mtd/devices/Makefile +++ b/drivers/mtd/devices/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o obj-$(CONFIG_MTD_M25P80) += m25p80.o obj-$(CONFIG_MTD_SST25L) += sst25l.o +obj-$(CONFIG_MTD_MXC_DATAFLASH) += mxc_dataflash.o diff --git a/drivers/mtd/devices/mxc_dataflash.c b/drivers/mtd/devices/mxc_dataflash.c new file mode 100644 index 000000000000..0ed701d6778c --- /dev/null +++ b/drivers/mtd/devices/mxc_dataflash.c @@ -0,0 +1,1037 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * (c) 2005 MontaVista Software, Inc. + * + * This code is based on mtd_dataflash.c by adding FSL spi access. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +/* + * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in + * each chip, which may be used for double buffered I/O; but this driver + * doesn't (yet) use these for any kind of i/o overlap or prefetching. + * + * Sometimes DataFlash is packaged in MMC-format cards, although the + * MMC stack can't (yet?) distinguish between MMC and DataFlash + * protocols during enumeration. + */ + +/* reads can bypass the buffers */ +#define OP_READ_CONTINUOUS 0xE8 +#define OP_READ_PAGE 0xD2 + +/* group B requests can run even while status reports "busy" */ +#define OP_READ_STATUS 0xD7 /* group B */ + +/* move data between host and buffer */ +#define OP_READ_BUFFER1 0xD4 /* group B */ +#define OP_READ_BUFFER2 0xD6 /* group B */ +#define OP_WRITE_BUFFER1 0x84 /* group B */ +#define OP_WRITE_BUFFER2 0x87 /* group B */ + +/* erasing flash */ +#define OP_ERASE_PAGE 0x81 +#define OP_ERASE_BLOCK 0x50 + +/* move data between buffer and flash */ +#define OP_TRANSFER_BUF1 0x53 +#define OP_TRANSFER_BUF2 0x55 +#define OP_MREAD_BUFFER1 0xD4 +#define OP_MREAD_BUFFER2 0xD6 +#define OP_MWERASE_BUFFER1 0x83 +#define OP_MWERASE_BUFFER2 0x86 +#define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */ +#define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */ + +/* write to buffer, then write-erase to flash */ +#define OP_PROGRAM_VIA_BUF1 0x82 +#define OP_PROGRAM_VIA_BUF2 0x85 + +/* compare buffer to flash */ +#define OP_COMPARE_BUF1 0x60 +#define OP_COMPARE_BUF2 0x61 + +/* read flash to buffer, then write-erase to flash */ +#define OP_REWRITE_VIA_BUF1 0x58 +#define OP_REWRITE_VIA_BUF2 0x59 + +/* newer chips report JEDEC manufacturer and device IDs; chip + * serial number and OTP bits; and per-sector writeprotect. + */ +#define OP_READ_ID 0x9F +#define OP_READ_SECURITY 0x77 +#define OP_WRITE_SECURITY_REVC 0x9A +#define OP_WRITE_SECURITY 0x9B /* revision D */ + +#define SPI_FIFOSIZE 24 /* Bust size in bytes */ +#define CMD_SIZE 4 +#define DUMY_SIZE 4 + +struct dataflash { + uint8_t command[4]; + char name[24]; + + unsigned partitioned:1; + + unsigned short page_offset; /* offset in flash address */ + unsigned int page_size; /* of bytes per page */ + + struct mutex lock; + struct spi_device *spi; + + struct mtd_info mtd; +}; + +#ifdef CONFIG_MTD_PARTITIONS +#define mtd_has_partitions() (1) +#else +#define mtd_has_partitions() (0) +#endif + +/* ......................................................................... */ + +/* + * This function initializes the SPI device parameters. + */ +static inline int spi_nor_setup(struct spi_device *spi, u8 bst_len) +{ + spi->bits_per_word = bst_len << 3; + + return spi_setup(spi); +} + +/* + * This function perform spi read/write transfer. + */ +static int spi_read_write(struct spi_device *spi, u8 * buf, u32 len) +{ + struct spi_message m; + struct spi_transfer t; + + if (len > SPI_FIFOSIZE || len <= 0) + return -1; + + spi_nor_setup(spi, len); + + spi_message_init(&m); + memset(&t, 0, sizeof t); + + t.tx_buf = buf; + t.rx_buf = buf; + t.len = ((len - 1) >> 2) + 1; + + spi_message_add_tail(&t, &m); + + if (spi_sync(spi, &m) != 0 || m.status != 0) { + printk(KERN_ERR "%s: error\n", __func__); + return -1; + } + + DEBUG(MTD_DEBUG_LEVEL2, "%s: len: 0x%x success\n", __func__, len); + + return 0; + +} + +/* + * Return the status of the DataFlash device. + */ +static inline int dataflash_status(struct spi_device *spi) +{ + /* NOTE: at45db321c over 25 MHz wants to write + * a dummy byte after the opcode... + */ + ssize_t retval; + + u16 val = OP_READ_STATUS << 8; + + retval = spi_read_write(spi, (u8 *)&val, 2); + + if (retval < 0) + return retval; + + DEBUG(MTD_DEBUG_LEVEL2, "%s: status: 0x%x\n", __func__, val & 0xff); + + return val & 0xff; +} + +/* + * Poll the DataFlash device until it is READY. + * This usually takes 5-20 msec or so; more for sector erase. + */ +static int dataflash_waitready(struct spi_device *spi) +{ + int status; + + for (;;) { + status = dataflash_status(spi); + if (status < 0) { + DEBUG(MTD_DEBUG_LEVEL1, "%s: status %d?\n", + dev_name(&spi->dev), status); + status = 0; + } + + if (status & (1 << 7)) /* RDY/nBSY */ + return status; + + msleep(3); + } +} + +/* ......................................................................... */ + +/* + * Erase pages of flash. + */ +static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) +{ + struct dataflash *priv = (struct dataflash *)mtd->priv; + struct spi_device *spi = priv->spi; + unsigned blocksize = priv->page_size << 3; + uint8_t *command; + uint32_t rem; + + DEBUG(MTD_DEBUG_LEVEL2, "%s: erase addr=0x%llx len 0x%llx\n", + dev_name(&spi->dev), (long long)instr->addr, + (long long)instr->len); + + /* Sanity checks */ + if (instr->addr + instr->len > mtd->size) + return -EINVAL; + div_u64_rem(instr->len, priv->page_size, &rem); + if (rem) + return -EINVAL; + div_u64_rem(instr->addr, priv->page_size, &rem); + if (rem) + return -EINVAL; + + command = priv->command; + + mutex_lock(&priv->lock); + while (instr->len > 0) { + unsigned int pageaddr; + int status; + int do_block; + + /* Calculate flash page address; use block erase (for speed) if + * we're at a block boundary and need to erase the whole block. + */ + pageaddr = div_u64(instr->addr, priv->page_size); + do_block = (pageaddr & 0x7) == 0 && instr->len >= blocksize; + pageaddr = pageaddr << priv->page_offset; + + command[3] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE; + command[2] = (uint8_t) (pageaddr >> 16); + command[1] = (uint8_t) (pageaddr >> 8); + command[0] = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "ERASE %s: (%x) %x %x %x [%i]\n", + do_block ? "block" : "page", + command[0], command[1], command[2], command[3], pageaddr); + + status = spi_read_write(spi, command, 4); + (void)dataflash_waitready(spi); + + if (status < 0) { + printk(KERN_ERR "%s: erase %x, err %d\n", + dev_name(&spi->dev), pageaddr, status); + /* REVISIT: can retry instr->retries times; or + * giveup and instr->fail_addr = instr->addr; + */ + continue; + } + + if (do_block) { + instr->addr += blocksize; + instr->len -= blocksize; + } else { + instr->addr += priv->page_size; + instr->len -= priv->page_size; + } + } + mutex_unlock(&priv->lock); + + /* Inform MTD subsystem that erase is complete */ + instr->state = MTD_ERASE_DONE; + mtd_erase_callback(instr); + + return 0; +} + +/* + * Read from the DataFlash device. + * from : Start offset in flash device + * len : Amount to read + * retlen : About of data actually read + * buf : Buffer containing the data + */ +static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf) +{ + struct dataflash *priv = mtd->priv; + struct spi_device *spi = priv->spi; + u32 addr; + int rx_len = 0, count = 0, i = 0; + u_char txer[SPI_FIFOSIZE]; + u_char *s = txer; + u_char *d = buf; + int cmd_len = CMD_SIZE + DUMY_SIZE; + int status = 0; + + DEBUG(MTD_DEBUG_LEVEL2, "%s: read 0x%x..0x%x\n", + dev_name(&priv->spi->dev), (unsigned)from, (unsigned)(from + len)); + + *retlen = 0; + + /* Sanity checks */ + if (!len) + return 0; + + if (from + len > mtd->size) + return -EINVAL; + + /* Calculate flash page/byte address */ + addr = (((unsigned)from / priv->page_size) << priv->page_offset) + + ((unsigned)from % priv->page_size); + + mutex_unlock(&priv->lock); + + while (len > 0) { + + rx_len = len > (SPI_FIFOSIZE - cmd_len) ? + SPI_FIFOSIZE - cmd_len : len; + + txer[3] = OP_READ_CONTINUOUS; + txer[2] = (addr >> 16) & 0xff; + txer[1] = (addr >> 8) & 0xff; + txer[0] = addr & 0xff; + + status = spi_read_write(spi, txer, + roundup(rx_len, 4) + cmd_len); + if (status) { + mutex_unlock(&priv->lock); + return status; + } + + s = txer + cmd_len; + + for (i = rx_len; i >= 0; i -= 4, s += 4) { + if (i < 4) { + if (i == 1) { + *d = s[3]; + } else if (i == 2) { + *d++ = s[3]; + *d++ = s[2]; + } else if (i == 3) { + *d++ = s[3]; + *d++ = s[2]; + *d++ = s[1]; + } + + break; + } + + *d++ = s[3]; + *d++ = s[2]; + *d++ = s[1]; + *d++ = s[0]; + } + + /* updaate */ + len -= rx_len; + addr += rx_len; + count += rx_len; + + DEBUG(MTD_DEBUG_LEVEL2, + "%s: left:0x%x, from:0x%08x, to:0x%p, done: 0x%x\n", + __func__, len, (u32) addr, d, count); + } + + *retlen = count; + + DEBUG(MTD_DEBUG_LEVEL2, "%s: %d bytes read\n", __func__, count); + + mutex_unlock(&priv->lock); + + return status; +} + +/* + * Write to the DataFlash device. + * to : Start offset in flash device + * len : Amount to write + * retlen : Amount of data actually written + * buf : Buffer containing the data + */ +static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + struct dataflash *priv = mtd->priv; + struct spi_device *spi = priv->spi; + u32 pageaddr, addr, offset, writelen; + size_t remaining = len; + u_char *writebuf = (u_char *) buf; + int status = -EINVAL; + u_char txer[SPI_FIFOSIZE] = { 0 }; + uint8_t *command = priv->command; + u_char *d = txer; + u_char *s = (u_char *) buf; + int delta = 0, l = 0, i = 0, count = 0; + + DEBUG(MTD_DEBUG_LEVEL2, "%s: write 0x%x..0x%x\n", + dev_name(&spi->dev), (unsigned)to, (unsigned)(to + len)); + + *retlen = 0; + + /* Sanity checks */ + if (!len) + return 0; + + if ((to + len) > mtd->size) + return -EINVAL; + + pageaddr = ((unsigned)to / priv->page_size); + offset = ((unsigned)to % priv->page_size); + if (offset + len > priv->page_size) + writelen = priv->page_size - offset; + else + writelen = len; + + mutex_lock(&priv->lock); + + while (remaining > 0) { + DEBUG(MTD_DEBUG_LEVEL3, "write @ %i:%i len=%i\n", + pageaddr, offset, writelen); + + addr = pageaddr << priv->page_offset; + + /* (1) Maybe transfer partial page to Buffer1 */ + if (writelen != priv->page_size) { + command[3] = OP_TRANSFER_BUF1; + command[2] = (addr & 0x00FF0000) >> 16; + command[1] = (addr & 0x0000FF00) >> 8; + command[0] = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "TRANSFER: (%x) %x %x %x\n", + command[3], command[2], command[1], command[0]); + + status = spi_read_write(spi, command, CMD_SIZE); + if (status) { + mutex_unlock(&priv->lock); + return status; + + } + + (void)dataflash_waitready(spi); + } + + count = writelen; + while (count) { + d = txer; + l = count > (SPI_FIFOSIZE - CMD_SIZE) ? + SPI_FIFOSIZE - CMD_SIZE : count; + + delta = l % 4; + if (delta) { + switch (delta) { + case 1: + d[0] = OP_WRITE_BUFFER1; + d[6] = (offset >> 8) & 0xff; + d[5] = offset & 0xff; + d[4] = *s++; + break; + case 2: + d[1] = OP_WRITE_BUFFER1; + d[7] = (offset >> 8) & 0xff; + d[6] = offset & 0xff; + d[5] = *s++; + d[4] = *s++; + break; + case 3: + d[2] = OP_WRITE_BUFFER1; + d[0] = (offset >> 8) & 0xff; + d[7] = offset & 0xff; + d[6] = *s++; + d[5] = *s++; + d[4] = *s++; + break; + default: + break; + } + + DEBUG(MTD_DEBUG_LEVEL3, + "WRITEBUF: (%x) %x %x %x\n", + txer[3], txer[2], txer[1], txer[0]); + + status = spi_read_write(spi, txer, + delta + CMD_SIZE); + if (status) { + mutex_unlock(&priv->lock); + return status; + } + + /* update */ + count -= delta; + offset += delta; + l -= delta; + } + + d[3] = OP_WRITE_BUFFER1; + d[1] = (offset >> 8) & 0xff; + d[0] = offset & 0xff; + + for (i = 0, d += 4; i < l / 4; i++, d += 4) { + d[3] = *s++; + d[2] = *s++; + d[1] = *s++; + d[0] = *s++; + } + + DEBUG(MTD_DEBUG_LEVEL3, "WRITEBUF: (%x) %x %x %x\n", + txer[3], txer[2], txer[1], txer[0]); + + status = spi_read_write(spi, txer, l + CMD_SIZE); + if (status) { + mutex_unlock(&priv->lock); + return status; + } + + /* update */ + count -= l; + offset += l; + } + + /* (2) Program full page via Buffer1 */ + command[3] = OP_MWERASE_BUFFER1; + command[2] = (addr >> 16) & 0xff; + command[1] = (addr >> 8) & 0xff; + + DEBUG(MTD_DEBUG_LEVEL3, "PROGRAM: (%x) %x %x %x\n", + command[3], command[2], command[1], command[0]); + + status = spi_read_write(spi, command, CMD_SIZE); + if (status) { + mutex_unlock(&priv->lock); + return status; + } + + (void)dataflash_waitready(spi); + + remaining -= writelen; + pageaddr++; + offset = 0; + writebuf += writelen; + *retlen += writelen; + + if (remaining > priv->page_size) + writelen = priv->page_size; + else + writelen = remaining; + } + mutex_unlock(&priv->lock); + + return status; +} + +/* ......................................................................... */ + +#ifdef CONFIG_MTD_DATAFLASH_OTP + +static int dataflash_get_otp_info(struct mtd_info *mtd, + struct otp_info *info, size_t len) +{ + /* Report both blocks as identical: bytes 0..64, locked. + * Unless the user block changed from all-ones, we can't + * tell whether it's still writable; so we assume it isn't. + */ + info->start = 0; + info->length = 64; + info->locked = 1; + return sizeof(*info); +} + +static ssize_t otp_read(struct spi_device *spi, unsigned base, + uint8_t *buf, loff_t off, size_t len) +{ + struct dataflash *priv = mtd->priv; + struct spi_device *spi = priv->spi; + int rx_len = 0, count = 0, i = 0; + u_char txer[SPI_FIFOSIZE]; + u_char *s = txer; + u_char *d = NULL; + int cmd_len = CMD_SIZE; + int status; + + if (off > 64) + return -EINVAL; + + if ((off + len) > 64) + len = 64 - off; + if (len == 0) + return len; + + /* to make simple, we read 64 out */ + l = base + 64; + + d = kzalloc(l, GFP_KERNEL); + if (!d) + return -ENOMEM; + + while (l > 0) { + + rx_len = l > (SPI_FIFOSIZE - cmd_len) ? + SPI_FIFOSIZE - cmd_len : l; + + txer[3] = OP_READ_SECURITY; + + status = spi_read_write(spi, txer, rx_len + cmd_len); + if (status) { + mutex_unlock(&priv->lock); + return status; + } + + s = txer + cmd_len; + for (i = rx_len; i >= 0; i -= 4, s += 4) { + + *d++ = s[3]; + *d++ = s[2]; + *d++ = s[1]; + *d++ = s[0]; + } + + /* updaate */ + l -= rx_len; + addr += rx_len; + count += rx_len; + + DEBUG(MTD_DEBUG_LEVEL2, + "%s: left:0x%x, from:0x%08x, to:0x%p, done: 0x%x\n", + __func__, len, (u32) addr, d, count); + } + + d -= count; + memcpy(buf, d + base + off, len); + + mutex_unlock(&priv->lock); + + return len; +} + +static int dataflash_read_fact_otp(struct mtd_info *mtd, + loff_t from, size_t len, size_t *retlen, + u_char *buf) +{ + struct dataflash *priv = (struct dataflash *)mtd->priv; + int status; + + /* 64 bytes, from 0..63 ... start at 64 on-chip */ + mutex_lock(&priv->lock); + status = otp_read(priv->spi, 64, buf, from, len); + mutex_unlock(&priv->lock); + + if (status < 0) + return status; + *retlen = status; + return 0; +} + +static int dataflash_read_user_otp(struct mtd_info *mtd, + loff_t from, size_t len, size_t *retlen, + u_char *buf) +{ + struct dataflash *priv = (struct dataflash *)mtd->priv; + int status; + + /* 64 bytes, from 0..63 ... start at 0 on-chip */ + mutex_lock(&priv->lock); + status = otp_read(priv->spi, 0, buf, from, len); + mutex_unlock(&priv->lock); + + if (status < 0) + return status; + *retlen = status; + return 0; +} + +static int dataflash_write_user_otp(struct mtd_info *mtd, + loff_t from, size_t len, size_t *retlen, + u_char *buf) +{ + printk(KERN_ERR "%s not support!!\n", __func__); + return 0; +} + +static char *otp_setup(struct mtd_info *device, char revision) +{ + device->get_fact_prot_info = dataflash_get_otp_info; + device->read_fact_prot_reg = dataflash_read_fact_otp; + device->get_user_prot_info = dataflash_get_otp_info; + device->read_user_prot_reg = dataflash_read_user_otp; + + /* rev c parts (at45db321c and at45db1281 only!) use a + * different write procedure; not (yet?) implemented. + */ + if (revision > 'c') + device->write_user_prot_reg = dataflash_write_user_otp; + + return ", OTP"; +} + +#else + +static char *otp_setup(struct mtd_info *device, char revision) +{ + return " (OTP)"; +} + +#endif + +/* ......................................................................... */ + +/* + * Register DataFlash device with MTD subsystem. + */ +static int __devinit +add_dataflash_otp(struct spi_device *spi, char *name, + int nr_pages, int pagesize, int pageoffset, char revision) +{ + struct dataflash *priv; + struct mtd_info *device; + struct flash_platform_data *pdata = spi->dev.platform_data; + char *otp_tag = ""; + + priv = kzalloc(sizeof *priv, GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->lock); + priv->spi = spi; + priv->page_size = pagesize; + priv->page_offset = pageoffset; + + /* name must be usable with cmdlinepart */ + sprintf(priv->name, "spi%d.%d-%s", + spi->master->bus_num, spi->chip_select, name); + + device = &priv->mtd; + device->name = (pdata && pdata->name) ? pdata->name : priv->name; + device->size = nr_pages * pagesize; + device->erasesize = pagesize; + device->writesize = pagesize; + device->owner = THIS_MODULE; + device->type = MTD_DATAFLASH; + device->flags = MTD_CAP_NORFLASH; + device->erase = dataflash_erase; + device->read = dataflash_read; + device->write = dataflash_write; + device->priv = priv; + + if (revision >= 'c') + otp_tag = otp_setup(device, revision); + + dev_info(&spi->dev, "%s (%llx KBytes) pagesize %d bytes%s\n", + name, DIV_ROUND_UP(device->size, 1024), pagesize, otp_tag); + dev_set_drvdata(&spi->dev, priv); + + if (mtd_has_partitions()) { + struct mtd_partition *parts; + int nr_parts = 0; + +#ifdef CONFIG_MTD_CMDLINE_PARTS + static const char *part_probes[] = { "cmdlinepart", NULL, }; + + nr_parts = parse_mtd_partitions(device, part_probes, &parts, 0); +#endif + + if (nr_parts <= 0 && pdata && pdata->parts) { + parts = pdata->parts; + nr_parts = pdata->nr_parts; + } + + if (nr_parts > 0) { + priv->partitioned = 1; + return add_mtd_partitions(device, parts, nr_parts); + } + } else if (pdata && pdata->nr_parts) + dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", + pdata->nr_parts, device->name); + + return add_mtd_device(device) == 1 ? -ENODEV : 0; +} + +static inline int __devinit +add_dataflash(struct spi_device *spi, char *name, + int nr_pages, int pagesize, int pageoffset) +{ + return add_dataflash_otp(spi, name, nr_pages, pagesize, pageoffset, 0); +} + +struct flash_info { + char *name; + + /* JEDEC id has a high byte of zero plus three data bytes: + * the manufacturer id, then a two byte device id. + */ + uint32_t jedec_id; + + /* The size listed here is what works with OP_ERASE_PAGE. */ + unsigned nr_pages; + uint16_t pagesize; + uint16_t pageoffset; + + uint16_t flags; +#define SUP_POW2PS 0x0002 /* supports 2^N byte pages */ +#define IS_POW2PS 0x0001 /* uses 2^N byte pages */ +}; + +static struct flash_info __devinitdata dataflash_data[] = { + + /* + * NOTE: chips with SUP_POW2PS (rev D and up) need two entries, + * one with IS_POW2PS and the other without. The entry with the + * non-2^N byte page size can't name exact chip revisions without + * losing backwards compatibility for cmdlinepart. + * + * These newer chips also support 128-byte security registers (with + * 64 bytes one-time-programmable) and software write-protection. + */ + {"AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS}, + {"at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS}, + + {"AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS}, + {"at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS}, + + {"AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS}, + {"at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS}, + + {"AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS}, + {"at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS}, + + {"AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS}, + {"at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS}, + + {"AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */ + + {"AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS}, + {"at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS}, + + {"AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS}, + {"at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS}, +}; + +static struct flash_info *__devinit jedec_probe(struct spi_device *spi) +{ + int tmp; + u32 code = OP_READ_ID << 24; + u32 jedec; + struct flash_info *info; + int status; + + /* JEDEC also defines an optional "extended device information" + * string for after vendor-specific data, after the three bytes + * we use here. Supporting some chips might require using it. + * + * If the vendor ID isn't Atmel's (0x1f), assume this call failed. + * That's not an error; only rev C and newer chips handle it, and + * only Atmel sells these chips. + */ + + tmp = spi_read_write(spi, (u8 *)&code, 4); + if (tmp < 0) { + DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", + dev_name(&spi->dev), tmp); + return NULL; + } + + jedec = code & 0xFFFFFF; + + for (tmp = 0, info = dataflash_data; + tmp < ARRAY_SIZE(dataflash_data); tmp++, info++) { + if (info->jedec_id == jedec) { + DEBUG(MTD_DEBUG_LEVEL1, "%s: OTP, sector protect%s\n", + dev_name(&spi->dev), (info->flags & SUP_POW2PS) + ? ", binary pagesize" : ""); + if (info->flags & SUP_POW2PS) { + status = dataflash_status(spi); + if (status < 0) { + DEBUG(MTD_DEBUG_LEVEL1, + "%s: status error %d\n", + dev_name(&spi->dev), status); + return ERR_PTR(status); + } + if (status & 0x1) { + if (info->flags & IS_POW2PS) + return info; + } else { + if (!(info->flags & IS_POW2PS)) + return info; + } + } + } + } + + /* + * Treat other chips as errors ... we won't know the right page + * size (it might be binary) even when we can tell which density + * class is involved (legacy chip id scheme). + */ + dev_warn(&spi->dev, "JEDEC id %06x not handled\n", jedec); + return ERR_PTR(-ENODEV); +} + +/* + * Detect and initialize DataFlash device, using JEDEC IDs on newer chips + * or else the ID code embedded in the status bits: + * + * Device Density ID code #Pages PageSize Offset + * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 + * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9 + * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 + * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 + * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 + * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 + * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11 + * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 + */ +static int __devinit dataflash_probe(struct spi_device *spi) +{ + int status; + struct flash_info *info; + + /* + * Try to detect dataflash by JEDEC ID. + * If it succeeds we know we have either a C or D part. + * D will support power of 2 pagesize option. + * Both support the security register, though with different + * write procedures. + */ + info = jedec_probe(spi); + if (IS_ERR(info)) + return PTR_ERR(info); + if (info != NULL) + return add_dataflash_otp(spi, info->name, info->nr_pages, + info->pagesize, info->pageoffset, + (info->flags & SUP_POW2PS) ? 'd' : + 'c'); + + /* + * Older chips support only legacy commands, identifing + * capacity using bits in the status byte. + */ + status = dataflash_status(spi); + if (status <= 0 || status == 0xff) { + DEBUG(MTD_DEBUG_LEVEL1, "%s: status error %d\n", + dev_name(&spi->dev), status); + if (status == 0 || status == 0xff) + status = -ENODEV; + return status; + } + + /* if there's a device there, assume it's dataflash. + * board setup should have set spi->max_speed_max to + * match f(car) for continuous reads, mode 0 or 3. + */ + switch (status & 0x3c) { + case 0x0c: /* 0 0 1 1 x x */ + status = add_dataflash(spi, "AT45DB011B", 512, 264, 9); + break; + case 0x14: /* 0 1 0 1 x x */ + status = add_dataflash(spi, "AT45DB021B", 1024, 264, 9); + break; + case 0x1c: /* 0 1 1 1 x x */ + status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9); + break; + case 0x24: /* 1 0 0 1 x x */ + status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9); + break; + case 0x2c: /* 1 0 1 1 x x */ + status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10); + break; + case 0x34: /* 1 1 0 1 x x */ + status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10); + break; + case 0x38: /* 1 1 1 x x x */ + case 0x3c: + status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11); + break; + /* obsolete AT45DB1282 not (yet?) supported */ + default: + DEBUG(MTD_DEBUG_LEVEL1, "%s: unsupported device (%x)\n", + dev_name(&spi->dev), status & 0x3c); + status = -ENODEV; + } + + if (status < 0) + DEBUG(MTD_DEBUG_LEVEL1, "%s: add_dataflash --> %d\n", + dev_name(&spi->dev), status); + + return status; +} + +static int __devexit dataflash_remove(struct spi_device *spi) +{ + struct dataflash *flash = dev_get_drvdata(&spi->dev); + int status; + + DEBUG(MTD_DEBUG_LEVEL1, "%s: remove\n", dev_name(&spi->dev)); + + if (mtd_has_partitions() && flash->partitioned) + status = del_mtd_partitions(&flash->mtd); + else + status = del_mtd_device(&flash->mtd); + if (status == 0) + kfree(flash); + return status; +} + +static struct spi_driver dataflash_driver = { + .driver = { + .name = "mxc_dataflash", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + + .probe = dataflash_probe, + .remove = __devexit_p(dataflash_remove), + + /* FIXME: investigate suspend and resume... */ +}; + +static int __init dataflash_init(void) +{ + return spi_register_driver(&dataflash_driver); +} + +module_init(dataflash_init); + +static void __exit dataflash_exit(void) +{ + spi_unregister_driver(&dataflash_driver); +} + +module_exit(dataflash_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MTD DataFlash driver"); diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index f22bc9f05ddb..5362bc4a000d 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -551,4 +551,14 @@ config MTD_PISMO When built as a module, it will be called pismo.ko +config MTD_MXC + bool "Map driver for Freescale MXC boards" + depends on MTD && ARCH_MXC + default y + select MTD_CFI + select MTD_PARTITIONS + help + This enables access to the flash chips on Freescale MXC based + platforms. If you have such a board, say 'Y'. + endmenu diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index bb035cd54c72..556db2ec6253 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o obj-$(CONFIG_MTD_VMU) += vmu-flash.o obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o +obj-$(CONFIG_MTD_MXC) += mxc_nor.o diff --git a/drivers/mtd/maps/mxc_nor.c b/drivers/mtd/maps/mxc_nor.c new file mode 100644 index 000000000000..d969f95a67a3 --- /dev/null +++ b/drivers/mtd/maps/mxc_nor.c @@ -0,0 +1,181 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * (c) 2005 MontaVista Software, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DVR_VER "2.0" + +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; +#endif + +struct mxcflash_info { + struct mtd_partition *parts; + struct mtd_info *mtd; + struct map_info map; +}; + +/*! + * @defgroup NOR_MTD NOR Flash MTD Driver + */ + +/*! + * @file mxc_nor.c + * + * @brief This file contains the MTD Mapping information on the MXC. + * + * @ingroup NOR_MTD + */ + +static int __devinit mxcflash_probe(struct platform_device *pdev) +{ + int err, nr_parts = 0; + struct mxcflash_info *info; + struct flash_platform_data *flash = pdev->dev.platform_data; + struct resource *res = pdev->resource; + unsigned long size = res->end - res->start + 1; + + info = kzalloc(sizeof(struct mxcflash_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + if (!request_mem_region(res->start, size, "flash")) { + err = -EBUSY; + goto out_free_info; + } + info->map.virt = ioremap(res->start, size); + if (!info->map.virt) { + err = -ENOMEM; + goto out_release_mem_region; + } + info->map.name = dev_name(&pdev->dev); + info->map.phys = res->start; + info->map.size = size; + info->map.bankwidth = flash->width; + + simple_map_init(&info->map); + info->mtd = do_map_probe(flash->map_name, &info->map); + if (!info->mtd) { + err = -EIO; + goto out_iounmap; + } + info->mtd->owner = THIS_MODULE; + +#ifdef CONFIG_MTD_PARTITIONS + nr_parts = + parse_mtd_partitions(info->mtd, part_probes, &info->parts, 0); + if (nr_parts > 0) { + add_mtd_partitions(info->mtd, info->parts, nr_parts); + } else if (flash->parts) { + add_mtd_partitions(info->mtd, flash->parts, flash->nr_parts); + } else +#endif + { + printk(KERN_NOTICE "MXC flash: no partition info " + "available, registering whole flash\n"); + add_mtd_device(info->mtd); + } + + platform_set_drvdata(pdev, info); + return 0; + + out_iounmap: + iounmap(info->map.virt); + out_release_mem_region: + release_mem_region(res->start, size); + out_free_info: + kfree(info); + + return err; +} + +static int __devexit mxcflash_remove(struct platform_device *pdev) +{ + + struct mxcflash_info *info = platform_get_drvdata(pdev); + struct flash_platform_data *flash = pdev->dev.platform_data; + + platform_set_drvdata(pdev, NULL); + + if (info) { + if (info->parts) { + del_mtd_partitions(info->mtd); + kfree(info->parts); + } else if (flash->parts) + del_mtd_partitions(info->mtd); + else + del_mtd_device(info->mtd); + + map_destroy(info->mtd); + release_mem_region(info->map.phys, info->map.size); + iounmap((void __iomem *)info->map.virt); + kfree(info); + } + return 0; +} + +static struct platform_driver mxcflash_driver = { + .driver = { + .name = "mxc_nor_flash", + }, + .probe = mxcflash_probe, + .remove = __devexit_p(mxcflash_remove), +}; + +/*! + * This is the module's entry function. It passes board specific + * config details into the MTD physmap driver which then does the + * real work for us. After this function runs, our job is done. + * + * @return 0 if successful; non-zero otherwise + */ +static int __init mxc_mtd_init(void) +{ + pr_info("MXC MTD nor Driver %s\n", DVR_VER); + if (platform_driver_register(&mxcflash_driver) != 0) { + printk(KERN_ERR "Driver register failed for mxcflash_driver\n"); + return -ENODEV; + } + return 0; +} + +/*! + * This function is the module's exit function. It's empty because the + * MTD physmap driver is doing the real work and our job was done after + * mxc_mtd_init() runs. + */ +static void __exit mxc_mtd_exit(void) +{ + platform_driver_unregister(&mxcflash_driver); +} + +module_init(mxc_mtd_init); +module_exit(mxc_mtd_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MTD map and partitions for Freescale MXC boards"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/mtd_blkdevs.c b/drivers/mtd/mtd_blkdevs.c index 03e19c1965cc..39f48524e986 100644 --- a/drivers/mtd/mtd_blkdevs.c +++ b/drivers/mtd/mtd_blkdevs.c @@ -485,13 +485,16 @@ int register_mtd_blktrans(struct mtd_blktrans_ops *tr) mutex_lock(&mtd_table_mutex); ret = register_blkdev(tr->major, tr->name); - if (ret) { + if (ret < 0) { printk(KERN_WARNING "Unable to register %s block device on major %d: %d\n", tr->name, tr->major, ret); mutex_unlock(&mtd_table_mutex); return ret; } + if (ret) + tr->major = ret; + tr->blkshift = ffs(tr->blksize) - 1; INIT_LIST_HEAD(&tr->devs); diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c index 91c8013cf0d9..8bebfa55cd4a 100644 --- a/drivers/mtd/mtdchar.c +++ b/drivers/mtd/mtdchar.c @@ -304,6 +304,7 @@ static ssize_t mtd_write(struct file *file, const char __user *buf, size_t count case MTD_MODE_RAW: { struct mtd_oob_ops ops; + memset(&ops, 0, sizeof(struct mtd_oob_ops)); ops.mode = MTD_OOB_RAW; ops.datbuf = kbuf; diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index ffc3720929f1..d6849c45e3b0 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -432,6 +432,68 @@ config MTD_NAND_NANDSIM The simulator may simulate various NAND flash chips for the MTD nand layer. +config MTD_NAND_IMX_NFC + tristate "i.MX NAND Flash Controller driver" + depends on MTD_NAND && (ARCH_MX2 || ARCH_MX3 || ARCH_MX5) + help + Enables the i.MX NAND Flash controller driver. + +config MTD_NAND_MXC + tristate "MXC NAND support" + depends on MTD_NAND && ARCH_MXC_HAS_NFC_V1 + help + This enables the driver for the NAND flash controller on the + MXC processors. + +config MTD_NAND_MXC_V2 + tristate "MXC NAND Version 2 support" + depends on MTD_NAND && ARCH_MXC_HAS_NFC_V2 + help + This enables the driver for the version 2 of NAND flash controller + on the MXC processors. + +config MTD_NAND_MXC_V3 + tristate "MXC NAND Version 3 support" + depends on MTD_NAND && ARCH_MXC_HAS_NFC_V3 + help + This enables the driver for the version 3 of NAND flash controller + on the MXC processors. + +config MTD_NAND_MXC_SWECC + bool "Software ECC support " + depends on MTD_NAND_MXC || MTD_NAND_MXC_V2 || MTD_NAND_MXC_V3 + help + This enables the support for Software ECC handling. By + default MXC NAND controller Hardware ECC is supported. + + +config MTD_NAND_MXC_FORCE_CE + bool "NAND chip select operation support" + depends on MTD_NAND_MXC || MTD_NAND_MXC_V2|| MTD_NAND_MXC_V3 + help + This enables the NAND chip select by using CE control line. By + default CE operation is disabled. + +config MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + bool "ECC correction in S/W" + depends on MTD_NAND_MXC + help + This enables the Option2 NFC ECC correction in software. By + default Option 1 is selected. Enable if you need option2 ECC correction. + +config MXC_NAND_LOW_LEVEL_ERASE + bool "Low level NAND erase" + depends on MTD_NAND_MXC || MTD_NAND_MXC_V2 || MTD_NAND_MXC_V3 + help + This enables the erase of whole NAND flash. By + default low level erase operation is disabled. + +config MTD_NAND_GPMI_NFC + tristate "GPMI NAND Flash Controller driver" + depends on MTD_NAND && (ARCH_MX23 || ARCH_MX28 || ARCH_MX50) + help + Enables NAND Flash support. + config MTD_NAND_PLATFORM tristate "Support for generic platform NAND driver" depends on MTD_NAND diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index e8ab884ba47b..87ab9180433c 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -38,7 +38,11 @@ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o +obj-$(CONFIG_MTD_NAND_IMX_NFC) += imx_nfc.o obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o +obj-$(CONFIG_MTD_NAND_MXC_V2) += mxc_nd2.o nand_device_info.o +obj-$(CONFIG_MTD_NAND_MXC_V3) += mxc_nd2.o nand_device_info.o +obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc/ nand_device_info.o obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o diff --git a/drivers/mtd/nand/gpmi-nfc/Makefile b/drivers/mtd/nand/gpmi-nfc/Makefile new file mode 100644 index 000000000000..5ce3d86bb921 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/Makefile @@ -0,0 +1,10 @@ +obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc.o +gpmi-nfc-objs += gpmi-nfc-main.o +gpmi-nfc-objs += gpmi-nfc-hal-common.o +gpmi-nfc-objs += gpmi-nfc-hal-v0.o +gpmi-nfc-objs += gpmi-nfc-hal-v1.o +gpmi-nfc-objs += gpmi-nfc-hal-v2.o +gpmi-nfc-objs += gpmi-nfc-rom-common.o +gpmi-nfc-objs += gpmi-nfc-rom-v0.o +gpmi-nfc-objs += gpmi-nfc-rom-v1.o +gpmi-nfc-objs += gpmi-nfc-mil.o diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h new file mode 100644 index 000000000000..9af4feb29021 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v0.h @@ -0,0 +1,550 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __GPMI_NFC_BCH_REGS_H +#define __GPMI_NFC_BCH_REGS_H + +/*============================================================================*/ + +#define HW_BCH_CTRL (0x00000000) +#define HW_BCH_CTRL_SET (0x00000004) +#define HW_BCH_CTRL_CLR (0x00000008) +#define HW_BCH_CTRL_TOG (0x0000000c) + +#define BM_BCH_CTRL_SFTRST 0x80000000 +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 +#define BM_BCH_CTRL_CLKGATE 0x40000000 +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3F800000 +#define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & BM_BCH_CTRL_RSVD5) +#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x00300000 +#define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & BM_BCH_CTRL_RSVD4) +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 +#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) +#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 +#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0x0000F800 +#define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & BM_BCH_CTRL_RSVD3) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 +#define BM_BCH_CTRL_RSVD2 0x00000200 +#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0x000000F0 +#define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & BM_BCH_CTRL_RSVD1) +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 +#define BM_BCH_CTRL_RSVD0 0x00000002 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 + +/*============================================================================*/ + +#define HW_BCH_STATUS0 (0x00000010) + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xFFF00000 +#define BF_BCH_STATUS0_HANDLE(v) \ + (((v) << 20) & BM_BCH_STATUS0_HANDLE) +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 +#define BF_BCH_STATUS0_COMPLETED_CE(v) \ + (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 +#define BF_BCH_STATUS0_STATUS_BLK0(v) \ + (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0x000000E0 +#define BF_BCH_STATUS0_RSVD1(v) \ + (((v) << 5) & BM_BCH_STATUS0_RSVD1) +#define BM_BCH_STATUS0_ALLONES 0x00000010 +#define BM_BCH_STATUS0_CORRECTED 0x00000008 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x00000003 +#define BF_BCH_STATUS0_RSVD0(v) \ + (((v) << 0) & BM_BCH_STATUS0_RSVD0) + +/*============================================================================*/ + +#define HW_BCH_MODE (0x00000020) + +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xFFFFFF00 +#define BF_BCH_MODE_RSVD(v) \ + (((v) << 8) & BM_BCH_MODE_RSVD) +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF +#define BF_BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) + +/*============================================================================*/ + +#define HW_BCH_ENCODEPTR (0x00000030) + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF +#define BF_BCH_ENCODEPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DATAPTR (0x00000040) + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_DATAPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_METAPTR (0x00000050) + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_METAPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_LAYOUTSELECT (0x00000070) + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \ + (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \ + (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \ + (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \ + (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \ + (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \ + (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \ + (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \ + (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \ + (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \ + (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \ + (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \ + (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \ + (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \ + (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \ + (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \ + (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) + +/*============================================================================*/ + +#define HW_BCH_FLASH0LAYOUT0 (0x00000080) + +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) +#define BP_BCH_FLASH0LAYOUT0_ECC0 12 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0) +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH0LAYOUT1 (0x00000090) + +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH0LAYOUT1_ECCN 12 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN) +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH1LAYOUT0 (0x000000a0) + +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) +#define BP_BCH_FLASH1LAYOUT0_ECC0 12 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0) +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH1LAYOUT1 (0x000000b0) + +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH1LAYOUT1_ECCN 12 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN) +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH2LAYOUT0 (0x000000c0) + +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) +#define BP_BCH_FLASH2LAYOUT0_ECC0 12 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0) +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH2LAYOUT1 (0x000000d0) + +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH2LAYOUT1_ECCN 12 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN) +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH3LAYOUT0 (0x000000e0) + +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) +#define BP_BCH_FLASH3LAYOUT0_ECC0 12 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0) +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH3LAYOUT1 (0x000000f0) + +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH3LAYOUT1_ECCN 12 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN) +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_DEBUG0 (0x00000100) +#define HW_BCH_DEBUG0_SET (0x00000104) +#define HW_BCH_DEBUG0_CLR (0x00000108) +#define HW_BCH_DEBUG0_TOG (0x0000010c) + +#define BP_BCH_DEBUG0_RSVD1 27 +#define BM_BCH_DEBUG0_RSVD1 0xF8000000 +#define BF_BCH_DEBUG0_RSVD1(v) \ + (((v) << 27) & BM_BCH_DEBUG0_RSVD1) +#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000 +#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000 +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \ + (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0x000000C0 +#define BF_BCH_DEBUG0_RSVD0(v) \ + (((v) << 6) & BM_BCH_DEBUG0_RSVD0) +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \ + (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) + +/*============================================================================*/ + +#define HW_BCH_DBGKESREAD (0x00000110) + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGKESREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGCSFEREAD (0x00000120) + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGSYNDGENREAD (0x00000130) + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGAHBMREAD (0x00000140) + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_BLOCKNAME (0x00000150) + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_BCH_BLOCKNAME_NAME(v) (v) + +/*============================================================================*/ + +#define HW_BCH_VERSION (0x00000160) + +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xFF000000 +#define BF_BCH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_BCH_VERSION_MAJOR) +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0x00FF0000 +#define BF_BCH_VERSION_MINOR(v) \ + (((v) << 16) & BM_BCH_VERSION_MINOR) +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0x0000FFFF +#define BF_BCH_VERSION_STEP(v) \ + (((v) << 0) & BM_BCH_VERSION_STEP) + +/*============================================================================*/ + +#endif diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h new file mode 100644 index 000000000000..692db086de4d --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v1.h @@ -0,0 +1,557 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Xml Revision: 2.5 + * Template revision: 26195 + */ + +#ifndef __GPMI_NFC_BCH_REGS_H +#define __GPMI_NFC_BCH_REGS_H + +/*============================================================================*/ + +#define HW_BCH_CTRL (0x00000000) +#define HW_BCH_CTRL_SET (0x00000004) +#define HW_BCH_CTRL_CLR (0x00000008) +#define HW_BCH_CTRL_TOG (0x0000000c) + +#define BM_BCH_CTRL_SFTRST 0x80000000 +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 +#define BM_BCH_CTRL_CLKGATE 0x40000000 +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3F800000 +#define BF_BCH_CTRL_RSVD5(v) \ + (((v) << 23) & BM_BCH_CTRL_RSVD5) +#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x00300000 +#define BF_BCH_CTRL_RSVD4(v) \ + (((v) << 20) & BM_BCH_CTRL_RSVD4) +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 +#define BF_BCH_CTRL_M2M_LAYOUT(v) \ + (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) +#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 +#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0x0000F800 +#define BF_BCH_CTRL_RSVD3(v) \ + (((v) << 11) & BM_BCH_CTRL_RSVD3) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 +#define BM_BCH_CTRL_RSVD2 0x00000200 +#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0x000000F0 +#define BF_BCH_CTRL_RSVD1(v) \ + (((v) << 4) & BM_BCH_CTRL_RSVD1) +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 +#define BM_BCH_CTRL_RSVD0 0x00000002 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 + +/*============================================================================*/ + +#define HW_BCH_STATUS0 (0x00000010) + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xFFF00000 +#define BF_BCH_STATUS0_HANDLE(v) \ + (((v) << 20) & BM_BCH_STATUS0_HANDLE) +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 +#define BF_BCH_STATUS0_COMPLETED_CE(v) \ + (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 +#define BF_BCH_STATUS0_STATUS_BLK0(v) \ + (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0x000000E0 +#define BF_BCH_STATUS0_RSVD1(v) \ + (((v) << 5) & BM_BCH_STATUS0_RSVD1) +#define BM_BCH_STATUS0_ALLONES 0x00000010 +#define BM_BCH_STATUS0_CORRECTED 0x00000008 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x00000003 +#define BF_BCH_STATUS0_RSVD0(v) \ + (((v) << 0) & BM_BCH_STATUS0_RSVD0) + +/*============================================================================*/ + +#define HW_BCH_MODE (0x00000020) + +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xFFFFFF00 +#define BF_BCH_MODE_RSVD(v) \ + (((v) << 8) & BM_BCH_MODE_RSVD) +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF +#define BF_BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) + +/*============================================================================*/ + +#define HW_BCH_ENCODEPTR (0x00000030) + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF +#define BF_BCH_ENCODEPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DATAPTR (0x00000040) + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_DATAPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_METAPTR (0x00000050) + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_METAPTR_ADDR(v) (v) + +/*============================================================================*/ + +#define HW_BCH_LAYOUTSELECT (0x00000070) + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \ + (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \ + (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \ + (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \ + (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \ + (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \ + (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \ + (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \ + (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \ + (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \ + (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \ + (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \ + (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \ + (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \ + (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \ + (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \ + (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) + +/*============================================================================*/ + +#define HW_BCH_FLASH0LAYOUT0 (0x00000080) + +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) +#define BP_BCH_FLASH0LAYOUT0_ECC0 12 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0) +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH0LAYOUT1 (0x00000090) + +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH0LAYOUT1_ECCN 12 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN) +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH1LAYOUT0 (0x000000a0) + +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) +#define BP_BCH_FLASH1LAYOUT0_ECC0 12 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0) +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH1LAYOUT1 (0x000000b0) + +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH1LAYOUT1_ECCN 12 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN) +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH2LAYOUT0 (0x000000c0) + +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) +#define BP_BCH_FLASH2LAYOUT0_ECC0 12 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0) +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH2LAYOUT1 (0x000000d0) + +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH2LAYOUT1_ECCN 12 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN) +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH3LAYOUT0 (0x000000e0) + +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) +#define BP_BCH_FLASH3LAYOUT0_ECC0 12 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0) +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) + +/*============================================================================*/ + +#define HW_BCH_FLASH3LAYOUT1 (0x000000f0) + +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH3LAYOUT1_ECCN 12 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN) +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) + +/*============================================================================*/ + +#define HW_BCH_DEBUG0 (0x00000100) +#define HW_BCH_DEBUG0_SET (0x00000104) +#define HW_BCH_DEBUG0_CLR (0x00000108) +#define HW_BCH_DEBUG0_TOG (0x0000010c) + +#define BP_BCH_DEBUG0_RSVD1 27 +#define BM_BCH_DEBUG0_RSVD1 0xF8000000 +#define BF_BCH_DEBUG0_RSVD1(v) \ + (((v) << 27) & BM_BCH_DEBUG0_RSVD1) +#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000 +#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000 +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \ + (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0x000000C0 +#define BF_BCH_DEBUG0_RSVD0(v) \ + (((v) << 6) & BM_BCH_DEBUG0_RSVD0) +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \ + (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) + +/*============================================================================*/ + +#define HW_BCH_DBGKESREAD (0x00000110) + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGKESREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGCSFEREAD (0x00000120) + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGSYNDGENREAD (0x00000130) + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_DBGAHBMREAD (0x00000140) + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) + +/*============================================================================*/ + +#define HW_BCH_BLOCKNAME (0x00000150) + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_BCH_BLOCKNAME_NAME(v) (v) + +/*============================================================================*/ + +#define HW_BCH_VERSION (0x00000160) + +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xFF000000 +#define BF_BCH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_BCH_VERSION_MAJOR) +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0x00FF0000 +#define BF_BCH_VERSION_MINOR(v) \ + (((v) << 16) & BM_BCH_VERSION_MINOR) +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0x0000FFFF +#define BF_BCH_VERSION_STEP(v) \ + (((v) << 0) & BM_BCH_VERSION_STEP) + +/*============================================================================*/ + +#endif diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h new file mode 100644 index 000000000000..46c0ceb6ddff --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-bch-regs-v2.h @@ -0,0 +1,567 @@ +/* + * Freescale BCH Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.3 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___BCH_H +#define __ARCH_ARM___BCH_H + + +#define HW_BCH_CTRL (0x00000000) +#define HW_BCH_CTRL_SET (0x00000004) +#define HW_BCH_CTRL_CLR (0x00000008) +#define HW_BCH_CTRL_TOG (0x0000000c) + +#define BM_BCH_CTRL_SFTRST 0x80000000 +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 +#define BM_BCH_CTRL_CLKGATE 0x40000000 +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3F800000 +#define BF_BCH_CTRL_RSVD5(v) \ + (((v) << 23) & BM_BCH_CTRL_RSVD5) +#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x00300000 +#define BF_BCH_CTRL_RSVD4(v) \ + (((v) << 20) & BM_BCH_CTRL_RSVD4) +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 +#define BF_BCH_CTRL_M2M_LAYOUT(v) \ + (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) +#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 +#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0x0000F800 +#define BF_BCH_CTRL_RSVD3(v) \ + (((v) << 11) & BM_BCH_CTRL_RSVD3) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 +#define BM_BCH_CTRL_RSVD2 0x00000200 +#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0x000000F0 +#define BF_BCH_CTRL_RSVD1(v) \ + (((v) << 4) & BM_BCH_CTRL_RSVD1) +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 +#define BM_BCH_CTRL_RSVD0 0x00000002 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 + +#define HW_BCH_STATUS0 (0x00000010) + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xFFF00000 +#define BF_BCH_STATUS0_HANDLE(v) \ + (((v) << 20) & BM_BCH_STATUS0_HANDLE) +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 +#define BF_BCH_STATUS0_COMPLETED_CE(v) \ + (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 +#define BF_BCH_STATUS0_STATUS_BLK0(v) \ + (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0x000000E0 +#define BF_BCH_STATUS0_RSVD1(v) \ + (((v) << 5) & BM_BCH_STATUS0_RSVD1) +#define BM_BCH_STATUS0_ALLONES 0x00000010 +#define BM_BCH_STATUS0_CORRECTED 0x00000008 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x00000003 +#define BF_BCH_STATUS0_RSVD0(v) \ + (((v) << 0) & BM_BCH_STATUS0_RSVD0) + +#define HW_BCH_MODE (0x00000020) + +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xFFFFFF00 +#define BF_BCH_MODE_RSVD(v) \ + (((v) << 8) & BM_BCH_MODE_RSVD) +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF +#define BF_BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) + +#define HW_BCH_ENCODEPTR (0x00000030) + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF +#define BF_BCH_ENCODEPTR_ADDR(v) (v) + +#define HW_BCH_DATAPTR (0x00000040) + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_DATAPTR_ADDR(v) (v) + +#define HW_BCH_METAPTR (0x00000050) + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_METAPTR_ADDR(v) (v) + +#define HW_BCH_LAYOUTSELECT (0x00000070) + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \ + (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \ + (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \ + (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \ + (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \ + (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \ + (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \ + (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \ + (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \ + (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \ + (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \ + (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \ + (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \ + (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \ + (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \ + (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \ + (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) + +#define HW_BCH_FLASH0LAYOUT0 (0x00000080) + +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) +#define BP_BCH_FLASH0LAYOUT0_ECC0 11 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F800 +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \ + (((v) << 11) & BM_BCH_FLASH0LAYOUT0_ECC0) +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC32 0x10 +#define BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x000003FF +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH0LAYOUT1 (0x00000090) + +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH0LAYOUT1_ECCN 11 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F800 +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \ + (((v) << 11) & BM_BCH_FLASH0LAYOUT1_ECCN) +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC32 0x10 +#define BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x000003FF +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH1LAYOUT0 (0x000000a0) + +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) +#define BP_BCH_FLASH1LAYOUT0_ECC0 11 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F800 +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \ + (((v) << 11) & BM_BCH_FLASH1LAYOUT0_ECC0) +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC32 0x10 +#define BM_BCH_FLASH1LAYOUT0_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x000003FF +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH1LAYOUT1 (0x000000b0) + +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH1LAYOUT1_ECCN 11 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F800 +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \ + (((v) << 11) & BM_BCH_FLASH1LAYOUT1_ECCN) +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC32 0x10 +#define BM_BCH_FLASH1LAYOUT1_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x000003FF +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH2LAYOUT0 (0x000000c0) + +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) +#define BP_BCH_FLASH2LAYOUT0_ECC0 11 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F800 +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \ + (((v) << 11) & BM_BCH_FLASH2LAYOUT0_ECC0) +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC32 0x10 +#define BM_BCH_FLASH2LAYOUT0_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x000003FF +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH2LAYOUT1 (0x000000d0) + +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH2LAYOUT1_ECCN 11 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F800 +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \ + (((v) << 11) & BM_BCH_FLASH2LAYOUT1_ECCN) +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC32 0x10 +#define BM_BCH_FLASH2LAYOUT1_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x000003FF +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH3LAYOUT0 (0x000000e0) + +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) +#define BP_BCH_FLASH3LAYOUT0_ECC0 11 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F800 +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \ + (((v) << 11) & BM_BCH_FLASH3LAYOUT0_ECC0) +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC22 0xB +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC24 0xC +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC26 0xD +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC28 0xE +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC30 0xF +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC32 0x10 +#define BM_BCH_FLASH3LAYOUT0_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x000003FF +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH3LAYOUT1 (0x000000f0) + +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH3LAYOUT1_ECCN 11 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F800 +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \ + (((v) << 11) & BM_BCH_FLASH3LAYOUT1_ECCN) +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC22 0xB +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC24 0xC +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC26 0xD +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC28 0xE +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC30 0xF +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC32 0x10 +#define BM_BCH_FLASH3LAYOUT1_GF13_0_GF14_1 0x00000400 +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x000003FF +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) + +#define HW_BCH_DEBUG0 (0x00000100) +#define HW_BCH_DEBUG0_SET (0x00000104) +#define HW_BCH_DEBUG0_CLR (0x00000108) +#define HW_BCH_DEBUG0_TOG (0x0000010c) + +#define BP_BCH_DEBUG0_RSVD1 25 +#define BM_BCH_DEBUG0_RSVD1 0xFE000000 +#define BF_BCH_DEBUG0_RSVD1(v) \ + (((v) << 25) & BM_BCH_DEBUG0_RSVD1) +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \ + (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0x000000C0 +#define BF_BCH_DEBUG0_RSVD0(v) \ + (((v) << 6) & BM_BCH_DEBUG0_RSVD0) +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \ + (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) + +#define HW_BCH_DBGKESREAD (0x00000110) + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGKESREAD_VALUES(v) (v) + +#define HW_BCH_DBGCSFEREAD (0x00000120) + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) + +#define HW_BCH_DBGSYNDGENREAD (0x00000130) + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) + +#define HW_BCH_DBGAHBMREAD (0x00000140) + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) + +#define HW_BCH_BLOCKNAME (0x00000150) + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_BCH_BLOCKNAME_NAME(v) (v) + +#define HW_BCH_VERSION (0x00000160) + +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xFF000000 +#define BF_BCH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_BCH_VERSION_MAJOR) +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0x00FF0000 +#define BF_BCH_VERSION_MINOR(v) \ + (((v) << 16) & BM_BCH_VERSION_MINOR) +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0x0000FFFF +#define BF_BCH_VERSION_STEP(v) \ + (((v) << 0) & BM_BCH_VERSION_STEP) +#endif /* __ARCH_ARM___BCH_H */ diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h new file mode 100644 index 000000000000..2f9fce609a34 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v0.h @@ -0,0 +1,416 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __GPMI_NFC_GPMI_REGS_H +#define __GPMI_NFC_GPMI_REGS_H + +/*============================================================================*/ + +#define HW_GPMI_CTRL0 (0x00000000) +#define HW_GPMI_CTRL0_SET (0x00000004) +#define HW_GPMI_CTRL0_CLR (0x00000008) +#define HW_GPMI_CTRL0_TOG (0x0000000c) + +#define BM_GPMI_CTRL0_SFTRST 0x80000000 +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_GPMI_CTRL0_RUN 0x20000000 +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 +#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000 +#define BM_GPMI_CTRL0_UDMA 0x04000000 +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 +#define BF_GPMI_CTRL0_COMMAND_MODE(v) \ + (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 +#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00300000 +#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & BM_GPMI_CTRL0_CS) +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 +#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_GPMI_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_COMPARE (0x00000010) + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 +#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK) +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF +#define BF_GPMI_COMPARE_REFERENCE(v) \ + (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) + +/*============================================================================*/ + +#define HW_GPMI_ECCCTRL (0x00000020) +#define HW_GPMI_ECCCTRL_SET (0x00000024) +#define HW_GPMI_ECCCTRL_CLR (0x00000028) +#define HW_GPMI_ECCCTRL_TOG (0x0000002c) + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 +#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 +#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3 +#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 +#define BF_GPMI_ECCCTRL_RSVD1(v) (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ + (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF +#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001 + +/*============================================================================*/ + +#define HW_GPMI_ECCCOUNT (0x00000030) + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 +#define BF_GPMI_ECCCOUNT_RSVD2(v) (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF +#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_PAYLOAD (0x00000040) + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC +#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 +#define BF_GPMI_PAYLOAD_RSVD0(v) (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +/*============================================================================*/ + +#define HW_GPMI_AUXILIARY (0x00000050) + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC +#define BF_GPMI_AUXILIARY_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 +#define BF_GPMI_AUXILIARY_RSVD0(v) (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +/*============================================================================*/ + +#define HW_GPMI_CTRL1 (0x00000060) +#define HW_GPMI_CTRL1_SET (0x00000064) +#define HW_GPMI_CTRL1_CLR (0x00000068) +#define HW_GPMI_CTRL1_TOG (0x0000006c) + +#define BP_GPMI_CTRL1_RSVD2 24 +#define BM_GPMI_CTRL1_RSVD2 0xFF000000 +#define BF_GPMI_CTRL1_RSVD2(v) \ + (((v) << 24) & BM_GPMI_CTRL1_RSVD2) +#define BM_GPMI_CTRL1_CE3_SEL 0x00800000 +#define BM_GPMI_CTRL1_CE2_SEL 0x00400000 +#define BM_GPMI_CTRL1_CE1_SEL 0x00200000 +#define BM_GPMI_CTRL1_CE0_SEL 0x00100000 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BP_GPMI_CTRL1_GPMI_MODE 0 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 +#define BP_GPMI_CTRL1_DLL_ENABLE 17 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BF_GPMI_CTRL1_RDN_DELAY(v) \ + (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x00000080 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x00000040 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x00000020 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x00000010 +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 + +/*============================================================================*/ + +#define HW_GPMI_TIMING0 (0x00000070) + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 +#define BF_GPMI_TIMING0_RSVD1(v) \ + (((v) << 24) & BM_GPMI_TIMING0_RSVD1) +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ + (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING0_DATA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF +#define BF_GPMI_TIMING0_DATA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_TIMING1 (0x00000080) + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF +#define BF_GPMI_TIMING1_RSVD1(v) \ + (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +/*============================================================================*/ + +#define HW_GPMI_TIMING2 (0x00000090) + +#define BP_GPMI_TIMING2_UDMA_TRP 24 +#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000 +#define BF_GPMI_TIMING2_UDMA_TRP(v) \ + (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP) +#define BP_GPMI_TIMING2_UDMA_ENV 16 +#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000 +#define BF_GPMI_TIMING2_UDMA_ENV(v) \ + (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV) +#define BP_GPMI_TIMING2_UDMA_HOLD 8 +#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING2_UDMA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD) +#define BP_GPMI_TIMING2_UDMA_SETUP 0 +#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF +#define BF_GPMI_TIMING2_UDMA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_DATA (0x000000a0) + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF +#define BF_GPMI_DATA_DATA(v) (v) + +/*============================================================================*/ + +#define HW_GPMI_STAT (0x000000b0) + +#define BM_GPMI_STAT_PRESENT 0x80000000 +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 +#define BP_GPMI_STAT_RSVD1 12 +#define BM_GPMI_STAT_RSVD1 0x7FFFF000 +#define BF_GPMI_STAT_RSVD1(v) \ + (((v) << 12) & BM_GPMI_STAT_RSVD1) +#define BP_GPMI_STAT_RDY_TIMEOUT 8 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00000F00 +#define BF_GPMI_STAT_RDY_TIMEOUT(v) \ + (((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT) +#define BM_GPMI_STAT_ATA_IRQ 0x00000080 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000040 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000020 +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000010 +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000008 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000004 +#define BM_GPMI_STAT_DEV1_ERROR 0x00000002 +#define BM_GPMI_STAT_DEERROR 0x00000001 + +/*============================================================================*/ + +#define HW_GPMI_DEBUG (0x000000c0) + +#define BM_GPMI_DEBUG_READY3 0x80000000 +#define BM_GPMI_DEBUG_READY2 0x40000000 +#define BM_GPMI_DEBUG_READY1 0x20000000 +#define BM_GPMI_DEBUG_READY0 0x10000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x08000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x04000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x02000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x01000000 +#define BM_GPMI_DEBUG_SENSE3 0x00800000 +#define BM_GPMI_DEBUG_SENSE2 0x00400000 +#define BM_GPMI_DEBUG_SENSE1 0x00200000 +#define BM_GPMI_DEBUG_SENSE0 0x00100000 +#define BM_GPMI_DEBUG_DMAREQ3 0x00080000 +#define BM_GPMI_DEBUG_DMAREQ2 0x00040000 +#define BM_GPMI_DEBUG_DMAREQ1 0x00020000 +#define BM_GPMI_DEBUG_DMAREQ0 0x00010000 +#define BP_GPMI_DEBUG_CMD_END 12 +#define BM_GPMI_DEBUG_CMD_END 0x0000F000 +#define BF_GPMI_DEBUG_CMD_END(v) \ + (((v) << 12) & BM_GPMI_DEBUG_CMD_END) +#define BP_GPMI_DEBUG_UDMA_STATE 8 +#define BM_GPMI_DEBUG_UDMA_STATE 0x00000F00 +#define BF_GPMI_DEBUG_UDMA_STATE(v) \ + (((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE) +#define BM_GPMI_DEBUG_BUSY 0x00000080 +#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 +#define BP_GPMI_DEBUG_PIN_STATE 4 +#define BM_GPMI_DEBUG_PIN_STATE 0x00000070 +#define BF_GPMI_DEBUG_PIN_STATE(v) \ + (((v) << 4) & BM_GPMI_DEBUG_PIN_STATE) +#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG_MAIN_STATE 0 +#define BM_GPMI_DEBUG_MAIN_STATE 0x0000000F +#define BF_GPMI_DEBUG_MAIN_STATE(v) \ + (((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE) +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA + +/*============================================================================*/ + +#define HW_GPMI_VERSION (0x000000d0) + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 +#define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 +#define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & BM_GPMI_VERSION_MINOR) +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF +#define BF_GPMI_VERSION_STEP(v) (((v) << 0) & BM_GPMI_VERSION_STEP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG2 (0x000000e0) + +#define BP_GPMI_DEBUG2_RSVD1 16 +#define BM_GPMI_DEBUG2_RSVD1 0xFFFF0000 +#define BF_GPMI_DEBUG2_RSVD1(v) (((v) << 16) & BM_GPMI_DEBUG2_RSVD1) +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \ + (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F +#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG3 (0x000000f0) + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \ + (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \ + (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +/*============================================================================*/ +#endif diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h new file mode 100644 index 000000000000..dcb3b7d3fc88 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v1.h @@ -0,0 +1,421 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Xml Revision: 2.2 + * Template revision: 26195 + */ + +#ifndef __GPMI_NFC_GPMI_REGS_H +#define __GPMI_NFC_GPMI_REGS_H + +/*============================================================================*/ + +#define HW_GPMI_CTRL0 (0x00000000) +#define HW_GPMI_CTRL0_SET (0x00000004) +#define HW_GPMI_CTRL0_CLR (0x00000008) +#define HW_GPMI_CTRL0_TOG (0x0000000c) + +#define BM_GPMI_CTRL0_SFTRST 0x80000000 +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_GPMI_CTRL0_RUN 0x20000000 +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 +#define BM_GPMI_CTRL0_LOCK_CS 0x08000000 +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 +#define BM_GPMI_CTRL0_UDMA 0x04000000 +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 +#define BF_GPMI_CTRL0_COMMAND_MODE(v) \ + (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00700000 +#define BF_GPMI_CTRL0_CS(v) \ + (((v) << 20) & BM_GPMI_CTRL0_CS) +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 +#define BF_GPMI_CTRL0_ADDRESS(v) \ + (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_GPMI_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_COMPARE (0x00000010) + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 +#define BF_GPMI_COMPARE_MASK(v) \ + (((v) << 16) & BM_GPMI_COMPARE_MASK) +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF +#define BF_GPMI_COMPARE_REFERENCE(v) \ + (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) + +/*============================================================================*/ + +#define HW_GPMI_ECCCTRL (0x00000020) +#define HW_GPMI_ECCCTRL_SET (0x00000024) +#define HW_GPMI_ECCCTRL_CLR (0x00000028) +#define HW_GPMI_ECCCTRL_TOG (0x0000002c) + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 +#define BF_GPMI_ECCCTRL_HANDLE(v) \ + (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 +#define BF_GPMI_ECCCTRL_ECC_CMD(v) \ + (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 +#define BF_GPMI_ECCCTRL_RSVD1(v) \ + (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ + (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF + +/*============================================================================*/ + +#define HW_GPMI_ECCCOUNT (0x00000030) + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 +#define BF_GPMI_ECCCOUNT_RSVD2(v) \ + (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF +#define BF_GPMI_ECCCOUNT_COUNT(v) \ + (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) + +/*============================================================================*/ + +#define HW_GPMI_PAYLOAD (0x00000040) + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC +#define BF_GPMI_PAYLOAD_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 +#define BF_GPMI_PAYLOAD_RSVD0(v) \ + (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +/*============================================================================*/ + +#define HW_GPMI_AUXILIARY (0x00000050) + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC +#define BF_GPMI_AUXILIARY_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 +#define BF_GPMI_AUXILIARY_RSVD0(v) \ + (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +/*============================================================================*/ + +#define HW_GPMI_CTRL1 (0x00000060) +#define HW_GPMI_CTRL1_SET (0x00000064) +#define HW_GPMI_CTRL1_CLR (0x00000068) +#define HW_GPMI_CTRL1_TOG (0x0000006c) + +#define BP_GPMI_CTRL1_RSVD2 25 +#define BM_GPMI_CTRL1_RSVD2 0xFE000000 +#define BF_GPMI_CTRL1_RSVD2(v) \ + (((v) << 25) & BM_GPMI_CTRL1_RSVD2) +#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000 +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 +#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000 +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \ + (((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL) +#define BM_GPMI_CTRL1_RSVD1 0x00200000 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 +#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 +#define BP_GPMI_CTRL1_DLL_ENABLE 17 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BF_GPMI_CTRL1_RDN_DELAY(v) \ + (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 +#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080 +#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070 +#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) \ + (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 + +/*============================================================================*/ + +#define HW_GPMI_TIMING0 (0x00000070) + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 +#define BF_GPMI_TIMING0_RSVD1(v) \ + (((v) << 24) & BM_GPMI_TIMING0_RSVD1) +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ + (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING0_DATA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF +#define BF_GPMI_TIMING0_DATA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_TIMING1 (0x00000080) + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF +#define BF_GPMI_TIMING1_RSVD1(v) \ + (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +/*============================================================================*/ + +#define HW_GPMI_TIMING2 (0x00000090) + +#define BP_GPMI_TIMING2_UDMA_TRP 24 +#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000 +#define BF_GPMI_TIMING2_UDMA_TRP(v) \ + (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP) +#define BP_GPMI_TIMING2_UDMA_ENV 16 +#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000 +#define BF_GPMI_TIMING2_UDMA_ENV(v) \ + (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV) +#define BP_GPMI_TIMING2_UDMA_HOLD 8 +#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING2_UDMA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD) +#define BP_GPMI_TIMING2_UDMA_SETUP 0 +#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF +#define BF_GPMI_TIMING2_UDMA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP) + +/*============================================================================*/ + +#define HW_GPMI_DATA (0x000000a0) + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF +#define BF_GPMI_DATA_DATA(v) (v) + +#define HW_GPMI_STAT (0x000000b0) + +#define BP_GPMI_STAT_READY_BUSY 24 +#define BM_GPMI_STAT_READY_BUSY 0xFF000000 +#define BF_GPMI_STAT_READY_BUSY(v) \ + (((v) << 24) & BM_GPMI_STAT_READY_BUSY) +#define BP_GPMI_STAT_RDY_TIMEOUT 16 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000 +#define BF_GPMI_STAT_RDY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT) +#define BM_GPMI_STAT_DEV7_ERROR 0x00008000 +#define BM_GPMI_STAT_DEV6_ERROR 0x00004000 +#define BM_GPMI_STAT_DEV5_ERROR 0x00002000 +#define BM_GPMI_STAT_DEV4_ERROR 0x00001000 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000800 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000400 +#define BM_GPMI_STAT_DEERROR 0x00000200 +#define BM_GPMI_STAT_DEV0_ERROR 0x00000100 +#define BP_GPMI_STAT_RSVD1 5 +#define BM_GPMI_STAT_RSVD1 0x000000E0 +#define BF_GPMI_STAT_RSVD1(v) \ + (((v) << 5) & BM_GPMI_STAT_RSVD1) +#define BM_GPMI_STAT_ATA_IRQ 0x00000010 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004 +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000002 +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 +#define BM_GPMI_STAT_PRESENT 0x00000001 +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 + +/*============================================================================*/ + +#define HW_GPMI_DEBUG (0x000000c0) + +#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000 +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \ + (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#define BP_GPMI_DEBUG_DMA_SENSE 16 +#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000 +#define BF_GPMI_DEBUG_DMA_SENSE(v) \ + (((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE) +#define BP_GPMI_DEBUG_DMAREQ 8 +#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00 +#define BF_GPMI_DEBUG_DMAREQ(v) \ + (((v) << 8) & BM_GPMI_DEBUG_DMAREQ) +#define BP_GPMI_DEBUG_CMD_END 0 +#define BM_GPMI_DEBUG_CMD_END 0x000000FF +#define BF_GPMI_DEBUG_CMD_END(v) \ + (((v) << 0) & BM_GPMI_DEBUG_CMD_END) + +/*============================================================================*/ + +#define HW_GPMI_VERSION (0x000000d0) + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 +#define BF_GPMI_VERSION_MAJOR(v) \ + (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 +#define BF_GPMI_VERSION_MINOR(v) \ + (((v) << 16) & BM_GPMI_VERSION_MINOR) +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF +#define BF_GPMI_VERSION_STEP(v) \ + (((v) << 0) & BM_GPMI_VERSION_STEP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG2 (0x000000e0) + +#define BP_GPMI_DEBUG2_RSVD1 28 +#define BM_GPMI_DEBUG2_RSVD1 0xF0000000 +#define BF_GPMI_DEBUG2_RSVD1(v) \ + (((v) << 28) & BM_GPMI_DEBUG2_RSVD1) +#define BP_GPMI_DEBUG2_UDMA_STATE 24 +#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000 +#define BF_GPMI_DEBUG2_UDMA_STATE(v) \ + (((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE) +#define BM_GPMI_DEBUG2_BUSY 0x00800000 +#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG2_BUSY__ENABLED 0x1 +#define BP_GPMI_DEBUG2_PIN_STATE 20 +#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000 +#define BF_GPMI_DEBUG2_PIN_STATE(v) \ + (((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE) +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG2_MAIN_STATE 16 +#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000 +#define BF_GPMI_DEBUG2_MAIN_STATE(v) \ + (((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE) +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \ + (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F +#define BF_GPMI_DEBUG2_RDN_TAP(v) \ + (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +/*============================================================================*/ + +#define HW_GPMI_DEBUG3 (0x000000f0) + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \ + (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \ + (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +/*============================================================================*/ + +#endif diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h new file mode 100644 index 000000000000..3baa9012da69 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-gpmi-regs-v2.h @@ -0,0 +1,511 @@ +/* + * Freescale GPMI Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.19 + * Template revision: 1.3 + */ + +#ifndef __ARCH_ARM___GPMI_H +#define __ARCH_ARM___GPMI_H + + +#define HW_GPMI_CTRL0 (0x00000000) +#define HW_GPMI_CTRL0_SET (0x00000004) +#define HW_GPMI_CTRL0_CLR (0x00000008) +#define HW_GPMI_CTRL0_TOG (0x0000000c) + +#define BM_GPMI_CTRL0_SFTRST 0x80000000 +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_GPMI_CTRL0_RUN 0x20000000 +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 +#define BM_GPMI_CTRL0_LOCK_CS 0x08000000 +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 +#define BM_GPMI_CTRL0_UDMA 0x04000000 +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 +#define BP_GPMI_CTRL0_COMMAND_MODE 24 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 +#define BF_GPMI_CTRL0_COMMAND_MODE(v) \ + (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 +#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00700000 +#define BF_GPMI_CTRL0_CS(v) \ + (((v) << 20) & BM_GPMI_CTRL0_CS) +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 +#define BF_GPMI_CTRL0_ADDRESS(v) \ + (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_GPMI_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) + +#define HW_GPMI_COMPARE (0x00000010) + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 +#define BF_GPMI_COMPARE_MASK(v) \ + (((v) << 16) & BM_GPMI_COMPARE_MASK) +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF +#define BF_GPMI_COMPARE_REFERENCE(v) \ + (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) + +#define HW_GPMI_ECCCTRL (0x00000020) +#define HW_GPMI_ECCCTRL_SET (0x00000024) +#define HW_GPMI_ECCCTRL_CLR (0x00000028) +#define HW_GPMI_ECCCTRL_TOG (0x0000002c) + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 +#define BF_GPMI_ECCCTRL_HANDLE(v) \ + (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 +#define BP_GPMI_ECCCTRL_ECC_CMD 13 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 +#define BF_GPMI_ECCCTRL_ECC_CMD(v) \ + (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 +#define BF_GPMI_ECCCTRL_RSVD1(v) \ + (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ + (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF + +#define HW_GPMI_ECCCOUNT (0x00000030) + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 +#define BF_GPMI_ECCCOUNT_RSVD2(v) \ + (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF +#define BF_GPMI_ECCCOUNT_COUNT(v) \ + (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) + +#define HW_GPMI_PAYLOAD (0x00000040) + +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC +#define BF_GPMI_PAYLOAD_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 +#define BF_GPMI_PAYLOAD_RSVD0(v) \ + (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +#define HW_GPMI_AUXILIARY (0x00000050) + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC +#define BF_GPMI_AUXILIARY_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 +#define BF_GPMI_AUXILIARY_RSVD0(v) \ + (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +#define HW_GPMI_CTRL1 (0x00000060) +#define HW_GPMI_CTRL1_SET (0x00000064) +#define HW_GPMI_CTRL1_CLR (0x00000068) +#define HW_GPMI_CTRL1_TOG (0x0000006c) + +#define BM_GPMI_CTRL1_DEV_CLK_STOP 0x80000000 +#define BM_GPMI_CTRL1_SSYNC_CLK_STOP 0x40000000 +#define BM_GPMI_CTRL1_WRITE_CLK_STOP 0x20000000 +#define BM_GPMI_CTRL1_TOGGLE_MODE 0x10000000 +#define BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN 0x08000000 +#define BM_GPMI_CTRL1_UPDATE_CS 0x04000000 +#define BM_GPMI_CTRL1_SSYNCMODE 0x02000000 +#define BV_GPMI_CTRL1_SSYNCMODE__ASYNC 0x0 +#define BV_GPMI_CTRL1_SSYNCMODE__SSYNC 0x1 +#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000 +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22 +#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000 +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \ + (((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL) +#define BM_GPMI_CTRL1_RSVD1 0x00200000 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 +#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BF_GPMI_CTRL1_RDN_DELAY(v) \ + (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 +#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080 +#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070 +#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) \ + (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL) +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 + +#define HW_GPMI_TIMING0 (0x00000070) + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 +#define BF_GPMI_TIMING0_RSVD1(v) \ + (((v) << 24) & BM_GPMI_TIMING0_RSVD1) +#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ + (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING0_DATA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF +#define BF_GPMI_TIMING0_DATA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) + +#define HW_GPMI_TIMING1 (0x00000080) + +#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF +#define BF_GPMI_TIMING1_RSVD1(v) \ + (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +#define HW_GPMI_TIMING2 (0x00000090) + +#define BP_GPMI_TIMING2_RSVD1 27 +#define BM_GPMI_TIMING2_RSVD1 0xF8000000 +#define BF_GPMI_TIMING2_RSVD1(v) \ + (((v) << 27) & BM_GPMI_TIMING2_RSVD1) +#define BP_GPMI_TIMING2_READ_LATENCY 24 +#define BM_GPMI_TIMING2_READ_LATENCY 0x07000000 +#define BF_GPMI_TIMING2_READ_LATENCY(v) \ + (((v) << 24) & BM_GPMI_TIMING2_READ_LATENCY) +#define BP_GPMI_TIMING2_RSVD0 21 +#define BM_GPMI_TIMING2_RSVD0 0x00E00000 +#define BF_GPMI_TIMING2_RSVD0(v) \ + (((v) << 21) & BM_GPMI_TIMING2_RSVD0) +#define BP_GPMI_TIMING2_CE_DELAY 16 +#define BM_GPMI_TIMING2_CE_DELAY 0x001F0000 +#define BF_GPMI_TIMING2_CE_DELAY(v) \ + (((v) << 16) & BM_GPMI_TIMING2_CE_DELAY) +#define BP_GPMI_TIMING2_PREAMBLE_DELAY 12 +#define BM_GPMI_TIMING2_PREAMBLE_DELAY 0x0000F000 +#define BF_GPMI_TIMING2_PREAMBLE_DELAY(v) \ + (((v) << 12) & BM_GPMI_TIMING2_PREAMBLE_DELAY) +#define BP_GPMI_TIMING2_POSTAMBLE_DELAY 8 +#define BM_GPMI_TIMING2_POSTAMBLE_DELAY 0x00000F00 +#define BF_GPMI_TIMING2_POSTAMBLE_DELAY(v) \ + (((v) << 8) & BM_GPMI_TIMING2_POSTAMBLE_DELAY) +#define BP_GPMI_TIMING2_CMDADD_PAUSE 4 +#define BM_GPMI_TIMING2_CMDADD_PAUSE 0x000000F0 +#define BF_GPMI_TIMING2_CMDADD_PAUSE(v) \ + (((v) << 4) & BM_GPMI_TIMING2_CMDADD_PAUSE) +#define BP_GPMI_TIMING2_DATA_PAUSE 0 +#define BM_GPMI_TIMING2_DATA_PAUSE 0x0000000F +#define BF_GPMI_TIMING2_DATA_PAUSE(v) \ + (((v) << 0) & BM_GPMI_TIMING2_DATA_PAUSE) + +#define HW_GPMI_DATA (0x000000a0) + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF +#define BF_GPMI_DATA_DATA(v) (v) + +#define HW_GPMI_STAT (0x000000b0) + +#define BP_GPMI_STAT_READY_BUSY 24 +#define BM_GPMI_STAT_READY_BUSY 0xFF000000 +#define BF_GPMI_STAT_READY_BUSY(v) \ + (((v) << 24) & BM_GPMI_STAT_READY_BUSY) +#define BP_GPMI_STAT_RDY_TIMEOUT 16 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000 +#define BF_GPMI_STAT_RDY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT) +#define BM_GPMI_STAT_DEV7_ERROR 0x00008000 +#define BM_GPMI_STAT_DEV6_ERROR 0x00004000 +#define BM_GPMI_STAT_DEV5_ERROR 0x00002000 +#define BM_GPMI_STAT_DEV4_ERROR 0x00001000 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000800 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000400 +#define BM_GPMI_STAT_DEV1_ERROR 0x00000200 +#define BM_GPMI_STAT_DEV0_ERROR 0x00000100 +#define BP_GPMI_STAT_RSVD1 5 +#define BM_GPMI_STAT_RSVD1 0x000000E0 +#define BF_GPMI_STAT_RSVD1(v) \ + (((v) << 5) & BM_GPMI_STAT_RSVD1) +#define BM_GPMI_STAT_ATA_IRQ 0x00000010 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004 +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000002 +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 +#define BM_GPMI_STAT_PRESENT 0x00000001 +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 + +#define HW_GPMI_DEBUG (0x000000c0) + +#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000 +#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \ + (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END) +#define BP_GPMI_DEBUG_DMA_SENSE 16 +#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000 +#define BF_GPMI_DEBUG_DMA_SENSE(v) \ + (((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE) +#define BP_GPMI_DEBUG_DMAREQ 8 +#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00 +#define BF_GPMI_DEBUG_DMAREQ(v) \ + (((v) << 8) & BM_GPMI_DEBUG_DMAREQ) +#define BP_GPMI_DEBUG_CMD_END 0 +#define BM_GPMI_DEBUG_CMD_END 0x000000FF +#define BF_GPMI_DEBUG_CMD_END(v) \ + (((v) << 0) & BM_GPMI_DEBUG_CMD_END) + +#define HW_GPMI_VERSION (0x000000d0) + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 +#define BF_GPMI_VERSION_MAJOR(v) \ + (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 +#define BF_GPMI_VERSION_MINOR(v) \ + (((v) << 16) & BM_GPMI_VERSION_MINOR) +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF +#define BF_GPMI_VERSION_STEP(v) \ + (((v) << 0) & BM_GPMI_VERSION_STEP) + +#define HW_GPMI_DEBUG2 (0x000000e0) + +#define BP_GPMI_DEBUG2_RSVD1 28 +#define BM_GPMI_DEBUG2_RSVD1 0xF0000000 +#define BF_GPMI_DEBUG2_RSVD1(v) \ + (((v) << 28) & BM_GPMI_DEBUG2_RSVD1) +#define BP_GPMI_DEBUG2_UDMA_STATE 24 +#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000 +#define BF_GPMI_DEBUG2_UDMA_STATE(v) \ + (((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE) +#define BM_GPMI_DEBUG2_BUSY 0x00800000 +#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG2_BUSY__ENABLED 0x1 +#define BP_GPMI_DEBUG2_PIN_STATE 20 +#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000 +#define BF_GPMI_DEBUG2_PIN_STATE(v) \ + (((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE) +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG2_MAIN_STATE 16 +#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000 +#define BF_GPMI_DEBUG2_MAIN_STATE(v) \ + (((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE) +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \ + (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F +#define BF_GPMI_DEBUG2_RDN_TAP(v) \ + (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +#define HW_GPMI_DEBUG3 (0x000000f0) + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \ + (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \ + (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) + +#define HW_GPMI_READ_DDR_DLL_CTRL (0x00000100) + +#define BP_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000 +#define BF_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(v) \ + (((v) << 28) & BM_GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT) +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(v) \ + (((v) << 20) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT) +#define BP_GPMI_READ_DDR_DLL_CTRL_RSVD1 18 +#define BM_GPMI_READ_DDR_DLL_CTRL_RSVD1 0x000C0000 +#define BF_GPMI_READ_DDR_DLL_CTRL_RSVD1(v) \ + (((v) << 18) & BM_GPMI_READ_DDR_DLL_CTRL_RSVD1) +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00 +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) \ + (((v) << 10) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL) +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON 0x00000100 +#define BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE 0x00000080 +#define BP_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078 +#define BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(v) \ + (((v) << 3) & BM_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET) +#define BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define BM_GPMI_READ_DDR_DLL_CTRL_RESET 0x00000002 +#define BM_GPMI_READ_DDR_DLL_CTRL_ENABLE 0x00000001 + +#define HW_GPMI_WRITE_DDR_DLL_CTRL (0x00000110) + +#define BP_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 28 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT 0xF0000000 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(v) \ + (((v) << 28) & BM_GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT) +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 20 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT 0x0FF00000 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(v) \ + (((v) << 20) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT) +#define BP_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 18 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1 0x000C0000 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_RSVD1(v) \ + (((v) << 18) & BM_GPMI_WRITE_DDR_DLL_CTRL_RSVD1) +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 10 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL 0x0003FC00 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(v) \ + (((v) << 10) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL) +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE 0x00000200 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON 0x00000100 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE 0x00000080 +#define BP_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 3 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET 0x00000078 +#define BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(v) \ + (((v) << 3) & BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET) +#define BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD 0x00000004 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_RESET 0x00000002 +#define BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE 0x00000001 + +#define HW_GPMI_READ_DDR_DLL_STS (0x00000120) + +#define BP_GPMI_READ_DDR_DLL_STS_RSVD1 25 +#define BM_GPMI_READ_DDR_DLL_STS_RSVD1 0xFE000000 +#define BF_GPMI_READ_DDR_DLL_STS_RSVD1(v) \ + (((v) << 25) & BM_GPMI_READ_DDR_DLL_STS_RSVD1) +#define BP_GPMI_READ_DDR_DLL_STS_REF_SEL 17 +#define BM_GPMI_READ_DDR_DLL_STS_REF_SEL 0x01FE0000 +#define BF_GPMI_READ_DDR_DLL_STS_REF_SEL(v) \ + (((v) << 17) & BM_GPMI_READ_DDR_DLL_STS_REF_SEL) +#define BM_GPMI_READ_DDR_DLL_STS_REF_LOCK 0x00010000 +#define BP_GPMI_READ_DDR_DLL_STS_RSVD0 9 +#define BM_GPMI_READ_DDR_DLL_STS_RSVD0 0x0000FE00 +#define BF_GPMI_READ_DDR_DLL_STS_RSVD0(v) \ + (((v) << 9) & BM_GPMI_READ_DDR_DLL_STS_RSVD0) +#define BP_GPMI_READ_DDR_DLL_STS_SLV_SEL 1 +#define BM_GPMI_READ_DDR_DLL_STS_SLV_SEL 0x000001FE +#define BF_GPMI_READ_DDR_DLL_STS_SLV_SEL(v) \ + (((v) << 1) & BM_GPMI_READ_DDR_DLL_STS_SLV_SEL) +#define BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK 0x00000001 + +#define HW_GPMI_WRITE_DDR_DLL_STS (0x00000130) + +#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD1 25 +#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD1 0xFE000000 +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD1(v) \ + (((v) << 25) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD1) +#define BP_GPMI_WRITE_DDR_DLL_STS_REF_SEL 17 +#define BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL 0x01FE0000 +#define BF_GPMI_WRITE_DDR_DLL_STS_REF_SEL(v) \ + (((v) << 17) & BM_GPMI_WRITE_DDR_DLL_STS_REF_SEL) +#define BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK 0x00010000 +#define BP_GPMI_WRITE_DDR_DLL_STS_RSVD0 9 +#define BM_GPMI_WRITE_DDR_DLL_STS_RSVD0 0x0000FE00 +#define BF_GPMI_WRITE_DDR_DLL_STS_RSVD0(v) \ + (((v) << 9) & BM_GPMI_WRITE_DDR_DLL_STS_RSVD0) +#define BP_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 1 +#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL 0x000001FE +#define BF_GPMI_WRITE_DDR_DLL_STS_SLV_SEL(v) \ + (((v) << 1) & BM_GPMI_WRITE_DDR_DLL_STS_SLV_SEL) +#define BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK 0x00000001 +#endif /* __ARCH_ARM___GPMI_H */ diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c new file mode 100644 index 000000000000..e90a934b5c10 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-common.c @@ -0,0 +1,898 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/** + * gpmi_nfc_bch_isr - BCH interrupt service routine. + * + * @interrupt_number: The interrupt number. + * @cookie: A cookie that contains a pointer to the owning device + * data structure. + */ +irqreturn_t gpmi_nfc_bch_isr(int irq, void *cookie) +{ + struct gpmi_nfc_data *this = cookie; + struct nfc_hal *nfc = this->nfc; + + /* Clear the interrupt. */ + nfc->clear_bch(this); + + /* Release the base level. */ + complete(&(nfc->bch_done)); + + return IRQ_HANDLED; +} + +/** + * gpmi_nfc_dma_isr - DMA interrupt service routine. + * + * @interrupt_number: The interrupt number. + * @cookie: A cookie that contains a pointer to the owning device + * data structure. + */ +irqreturn_t gpmi_nfc_dma_isr(int irq, void *cookie) +{ + struct gpmi_nfc_data *this = cookie; + struct nfc_hal *nfc = this->nfc; + + /* Acknowledge the DMA channel's interrupt. */ + mxs_dma_ack_irq(nfc->isr_dma_channel); + + /* Release the base level. */ + complete(&(nfc->dma_done)); + + return IRQ_HANDLED; +} + +/** + * gpmi_nfc_dma_init() - Initializes DMA. + * + * @this: Per-device data. + */ +int gpmi_nfc_dma_init(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + int i; + int error; + + /* Allocate the DMA descriptors. */ + for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++) { + nfc->dma_descriptors[i] = mxs_dma_alloc_desc(); + if (!nfc->dma_descriptors[i]) { + dev_err(dev, "Cannot allocate all DMA descriptors.\n"); + error = -ENOMEM; + goto exit_descriptor_allocation; + } + } + return 0; + +exit_descriptor_allocation: + while (--i >= 0) + mxs_dma_free_desc(this->nfc->dma_descriptors[i]); + return error; +} + +/** + * gpmi_nfc_dma_exit() - Shuts down DMA. + * + * @this: Per-device data. + */ +void gpmi_nfc_dma_exit(struct gpmi_nfc_data *this) +{ + struct nfc_hal *nfc = this->nfc; + int i; + + /* Free the DMA descriptors. */ + for (i = 0; i < NFC_DMA_DESCRIPTOR_COUNT; i++) + mxs_dma_free_desc(nfc->dma_descriptors[i]); +} + +/** + * gpmi_nfc_set_geometry() - Shared NFC geometry configuration. + * + * In principle, computing the NFC geometry is version-specific. However, at + * this writing all, versions share the same page model, so this code can also + * be shared. + * + * @this: Per-device data. + */ +int gpmi_nfc_set_geometry(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct nfc_geometry *geometry = &this->nfc_geometry; + struct boot_rom_helper *rom = this->rom; + struct mtd_info *mtd = &this->mil.mtd; + unsigned int metadata_size; + unsigned int status_size; + unsigned int chunk_data_size_in_bits; + unsigned int chunk_ecc_size_in_bits; + unsigned int chunk_total_size_in_bits; + unsigned int block_mark_chunk_number; + unsigned int block_mark_chunk_bit_offset; + unsigned int block_mark_bit_offset; + + /* At this writing, we support only BCH. */ + geometry->ecc_algorithm = "BCH"; + + /* + * We always choose a metadata size of 10. Don't try to make sense of + * it -- this is really only for historical compatibility. + */ + geometry->metadata_size_in_bytes = 10; + + /* ECC chunks */ + geometry->ecc_chunk_size_in_bytes = 512; + if (is_ddr_nand(&this->device_info)) + geometry->ecc_chunk_size_in_bytes = 1024; + + /* Compute the page size, include page and oob. */ + geometry->page_size_in_bytes = mtd->writesize + mtd->oobsize; + + /* + * Compute the total number of ECC chunks in a page. This includes the + * slightly larger chunk at the beginning of the page, which contains + * both data and metadata. + */ + geometry->ecc_chunk_count = mtd->writesize / + geometry->ecc_chunk_size_in_bytes; + + /* + * We use the same ECC strength for all chunks, including the first one. + * At this writing, we base our ECC strength choice entirely on the + * the physical page geometry. In the future, this should be changed to + * pay attention to the detailed device information we gathered earlier. + */ + geometry->ecc_strength = 0; + + switch (mtd->writesize) { + case 2048: + geometry->ecc_strength = 8; + break; + case 4096: + switch (mtd->oobsize) { + case 128: + geometry->ecc_strength = 8; + break; + case 218: + geometry->ecc_strength = 16; + break; + } + break; + case 8192: + geometry->ecc_strength = 24; + /* + * ONFI/TOGGLE nand needs GF14, so re-culculate DMA page size. + * The ONFI nand must do the reculation, + * else it will fail in DMA. + */ + if (is_ddr_nand(&this->device_info)) + geometry->page_size_in_bytes = + mtd->writesize + + geometry->metadata_size_in_bytes + + (geometry->ecc_strength * 14 * 8 / + geometry->ecc_chunk_count); + break; + } + + if (!geometry->ecc_strength) { + dev_err(dev, "Unsupported page geometry.\n"); + return !0; + } + + /* + * The payload buffer contains the data area of a page. The ECC engine + * only needs what's required to hold the data. + */ + geometry->payload_size_in_bytes = mtd->writesize; + + /* + * In principle, computing the auxiliary buffer geometry is NFC + * version-specific. However, at this writing, all versions share the + * same model, so this code can also be shared. + * + * The auxiliary buffer contains the metadata and the ECC status. The + * metadata is padded to the nearest 32-bit boundary. The ECC status + * contains one byte for every ECC chunk, and is also padded to the + * nearest 32-bit boundary. + */ + metadata_size = (geometry->metadata_size_in_bytes + 0x3) & ~0x3; + status_size = (geometry->ecc_chunk_count + 0x3) & ~0x3; + + geometry->auxiliary_size_in_bytes = metadata_size + status_size; + geometry->auxiliary_status_offset = metadata_size; + + /* Check if we're going to do block mark swapping. */ + if (!rom->swap_block_mark) + return 0; + + /* + * If control arrives here, we're doing block mark swapping, so we need + * to compute the byte and bit offsets of the physical block mark within + * the ECC-based view of the page data. In principle, this isn't a + * difficult computation -- but it's very important and it's easy to get + * it wrong, so we do it carefully. + * + * Note that this calculation is simpler because we use the same ECC + * strength for all chunks, including the zero'th one, which contains + * the metadata. The calculation would be slightly more complicated + * otherwise. + * + * We start by computing the physical bit offset of the block mark. We + * then subtract the number of metadata and ECC bits appearing before + * the mark to arrive at its bit offset within the data alone. + */ + + /* Compute some important facts about chunk geometry. */ + chunk_data_size_in_bits = geometry->ecc_chunk_size_in_bytes * 8; + + /* ONFI nand needs GF14 */ + if (is_ddr_nand(&this->device_info)) + chunk_ecc_size_in_bits = geometry->ecc_strength * 14; + else + chunk_ecc_size_in_bits = geometry->ecc_strength * 13; + + chunk_total_size_in_bits = + chunk_data_size_in_bits + chunk_ecc_size_in_bits; + + /* Compute the bit offset of the block mark within the physical page. */ + block_mark_bit_offset = mtd->writesize * 8; + + /* Subtract the metadata bits. */ + block_mark_bit_offset -= geometry->metadata_size_in_bytes * 8; + + /* + * Compute the chunk number (starting at zero) in which the block mark + * appears. + */ + block_mark_chunk_number = + block_mark_bit_offset / chunk_total_size_in_bits; + + /* + * Compute the bit offset of the block mark within its chunk, and + * validate it. + */ + block_mark_chunk_bit_offset = + block_mark_bit_offset - + (block_mark_chunk_number * chunk_total_size_in_bits); + + if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) { + /* + * If control arrives here, the block mark actually appears in + * the ECC bits of this chunk. This wont' work. + */ + dev_err(dev, "Unsupported page geometry " + "(block mark in ECC): %u:%u\n", + mtd->writesize, mtd->oobsize); + return !0; + } + + /* + * Now that we know the chunk number in which the block mark appears, + * we can subtract all the ECC bits that appear before it. + */ + block_mark_bit_offset -= + block_mark_chunk_number * chunk_ecc_size_in_bits; + + /* + * We now know the absolute bit offset of the block mark within the + * ECC-based data. We can now compute the byte offset and the bit + * offset within the byte. + */ + geometry->block_mark_byte_offset = block_mark_bit_offset / 8; + geometry->block_mark_bit_offset = block_mark_bit_offset % 8; + + return 0; +} + +/** + * gpmi_nfc_dma_go - Run a DMA channel. + * + * @this: Per-device data structure. + * @dma_channel: The DMA channel we're going to use. + */ +int gpmi_nfc_dma_go(struct gpmi_nfc_data *this, int dma_channel) +{ + struct device *dev = this->dev; + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + unsigned long timeout; + int error; + LIST_HEAD(tmp_desc_list); + + /* Get ready... */ + nfc->isr_dma_channel = dma_channel; + init_completion(&nfc->dma_done); + mxs_dma_enable_irq(dma_channel, 1); + + /* Go! */ + mxs_dma_enable(dma_channel); + + /* Wait for it to finish. */ + timeout = wait_for_completion_timeout(&nfc->dma_done, + msecs_to_jiffies(1000)); + error = (!timeout) ? -ETIMEDOUT : 0; + if (error) { + struct mxs_dma_info info; + + mxs_dma_get_info(dma_channel, &info); + dev_err(dev, "[%s] Chip: %u, DMA Channel: %d, Error %d\n", + __func__, dma_channel - resources->dma_low_channel, + dma_channel, error); + } else { + /* Clear out the descriptors we just ran. */ + mxs_dma_cooked(dma_channel, &tmp_desc_list); + } + + /* Shut the DMA channel down. */ + mxs_dma_reset(dma_channel); + mxs_dma_enable_irq(dma_channel, 0); + mxs_dma_disable(dma_channel); + return error; +} + +/* + * This function is used in BCH reading or BCH writing. + * It will wait for the BCH interrupt as long as one second. + * Actually, we will wait for two interrupts, the DMA interrupt and + * BCH interrupt. + * + * @this: Per-device data structure. + * @dma_channel: DMA channel + * + */ +int start_dma_with_bch_irq(struct gpmi_nfc_data *this, int dma_channel) +{ + struct nfc_hal *nfc = this->nfc; + int error = 0; + + /* Prepare to receive an interrupt from the BCH block. */ + init_completion(&nfc->bch_done); + + /* Go! */ + error = gpmi_nfc_dma_go(this, dma_channel); + if (error) + printk(KERN_ERR "[ %s ] DMA error\n", __func__); + + /* Wait for the interrupt from the BCH block. */ + error = wait_for_completion_timeout(&nfc->bch_done, + msecs_to_jiffies(1000)); + error = (!error) ? -ETIMEDOUT : 0; + if (error) + printk(KERN_ERR "[ %s ] bch timeout!!!\n", __func__); + return error; +} + +/* This function is called in non-BCH DMA operations */ +int start_dma_without_bch_irq(struct gpmi_nfc_data *this, int dma_channel) +{ + int error = 0; + + /* Go! */ + error = gpmi_nfc_dma_go(this, dma_channel); + if (error) + printk(KERN_ERR "[ %s ] DMA error\n", __func__); + return error; +} + +/** + * ns_to_cycles - Converts time in nanoseconds to cycles. + * + * @ntime: The time, in nanoseconds. + * @period: The cycle period, in nanoseconds. + * @min: The minimum allowable number of cycles. + */ +static unsigned int ns_to_cycles(unsigned int time, + unsigned int period, unsigned int min) +{ + unsigned int k; + + /* + * Compute the minimum number of cycles that entirely contain the + * given time. + */ + k = (time + period - 1) / period; + return max(k, min); +} + +/** + * gpmi_compute_hardware_timing - Apply timing to current hardware conditions. + * + * @this: Per-device data. + * @hardware_timing: A pointer to a hardware timing structure that will receive + * the results of our calculations. + */ +int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this, + struct gpmi_nfc_hardware_timing *hw) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct nfc_hal *nfc = this->nfc; + struct nand_chip *nand = &this->mil.nand; + struct gpmi_nfc_timing target = nfc->timing; + bool improved_timing_is_available; + unsigned long clock_frequency_in_hz; + unsigned int clock_period_in_ns; + bool dll_use_half_periods; + unsigned int dll_delay_shift; + unsigned int max_sample_delay_in_ns; + unsigned int address_setup_in_cycles; + unsigned int data_setup_in_ns; + unsigned int data_setup_in_cycles; + unsigned int data_hold_in_cycles; + int ideal_sample_delay_in_ns; + unsigned int sample_delay_factor; + int tEYE; + unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns; + unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns; + + /* + * If there are multiple chips, we need to relax the timings to allow + * for signal distortion due to higher capacitance. + */ + if (nand->numchips > 2) { + target.data_setup_in_ns += 10; + target.data_hold_in_ns += 10; + target.address_setup_in_ns += 10; + } else if (nand->numchips > 1) { + target.data_setup_in_ns += 5; + target.data_hold_in_ns += 5; + target.address_setup_in_ns += 5; + } + + /* Check if improved timing information is available. */ + improved_timing_is_available = + (target.tREA_in_ns >= 0) && + (target.tRLOH_in_ns >= 0) && + (target.tRHOH_in_ns >= 0) ; + + /* Inspect the clock. */ + clock_frequency_in_hz = nfc->clock_frequency_in_hz; + clock_period_in_ns = 1000000000 / clock_frequency_in_hz; + + /* + * The NFC quantizes setup and hold parameters in terms of clock cycles. + * Here, we quantize the setup and hold timing parameters to the + * next-highest clock period to make sure we apply at least the + * specified times. + * + * For data setup and data hold, the hardware interprets a value of zero + * as the largest possible delay. This is not what's intended by a zero + * in the input parameter, so we impose a minimum of one cycle. + */ + data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns, + clock_period_in_ns, 1); + data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns, + clock_period_in_ns, 1); + address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns, + clock_period_in_ns, 0); + + /* + * The clock's period affects the sample delay in a number of ways: + * + * (1) The NFC HAL tells us the maximum clock period the sample delay + * DLL can tolerate. If the clock period is greater than half that + * maximum, we must configure the DLL to be driven by half periods. + * + * (2) We need to convert from an ideal sample delay, in ns, to a + * "sample delay factor," which the NFC uses. This factor depends on + * whether we're driving the DLL with full or half periods. + * Paraphrasing the reference manual: + * + * AD = SDF x 0.125 x RP + * + * where: + * + * AD is the applied delay, in ns. + * SDF is the sample delay factor, which is dimensionless. + * RP is the reference period, in ns, which is a full clock period + * if the DLL is being driven by full periods, or half that if + * the DLL is being driven by half periods. + * + * Let's re-arrange this in a way that's more useful to us: + * + * 8 + * SDF = AD x ---- + * RP + * + * The reference period is either the clock period or half that, so this + * is: + * + * 8 AD x DDF + * SDF = AD x ----- = -------- + * f x P P + * + * where: + * + * f is 1 or 1/2, depending on how we're driving the DLL. + * P is the clock period. + * DDF is the DLL Delay Factor, a dimensionless value that + * incorporates all the constants in the conversion. + * + * DDF will be either 8 or 16, both of which are powers of two. We can + * reduce the cost of this conversion by using bit shifts instead of + * multiplication or division. Thus: + * + * AD << DDS + * SDF = --------- + * P + * + * or + * + * AD = (SDF >> DDS) x P + * + * where: + * + * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF. + */ + if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) { + dll_use_half_periods = true; + dll_delay_shift = 3 + 1; + } else { + dll_use_half_periods = false; + dll_delay_shift = 3; + } + + /* + * Compute the maximum sample delay the NFC allows, under current + * conditions. If the clock is running too slowly, no sample delay is + * possible. + */ + if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns) + max_sample_delay_in_ns = 0; + else { + + /* + * Compute the delay implied by the largest sample delay factor + * the NFC allows. + */ + + max_sample_delay_in_ns = + (nfc->max_sample_delay_factor * clock_period_in_ns) >> + dll_delay_shift; + + /* + * Check if the implied sample delay larger than the NFC + * actually allows. + */ + + if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns) + max_sample_delay_in_ns = nfc->max_dll_delay_in_ns; + + } + + /* + * Check if improved timing information is available. If not, we have to + * use a less-sophisticated algorithm. + */ + + if (!improved_timing_is_available) { + + /* + * Fold the read setup time required by the NFC into the ideal + * sample delay. + */ + + ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns + + nfc->internal_data_setup_in_ns; + + /* + * The ideal sample delay may be greater than the maximum + * allowed by the NFC. If so, we can trade off sample delay time + * for more data setup time. + * + * In each iteration of the following loop, we add a cycle to + * the data setup time and subtract a corresponding amount from + * the sample delay until we've satisified the constraints or + * can't do any better. + */ + + while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) && + (data_setup_in_cycles < nfc->max_data_setup_cycles)) { + + data_setup_in_cycles++; + ideal_sample_delay_in_ns -= clock_period_in_ns; + + if (ideal_sample_delay_in_ns < 0) + ideal_sample_delay_in_ns = 0; + + } + + /* + * Compute the sample delay factor that corresponds most closely + * to the ideal sample delay. If the result is too large for the + * NFC, use the maximum value. + * + * Notice that we use the ns_to_cycles function to compute the + * sample delay factor. We do this because the form of the + * computation is the same as that for calculating cycles. + */ + + sample_delay_factor = + ns_to_cycles( + ideal_sample_delay_in_ns << dll_delay_shift, + clock_period_in_ns, 0); + + if (sample_delay_factor > nfc->max_sample_delay_factor) + sample_delay_factor = nfc->max_sample_delay_factor; + + /* Skip to the part where we return our results. */ + + goto return_results; + + } + + /* + * If control arrives here, we have more detailed timing information, + * so we can use a better algorithm. + */ + + /* + * Fold the read setup time required by the NFC into the maximum + * propagation delay. + */ + + max_prop_delay_in_ns += nfc->internal_data_setup_in_ns; + + /* + * Earlier, we computed the number of clock cycles required to satisfy + * the data setup time. Now, we need to know the actual nanoseconds. + */ + + data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles; + + /* + * Compute tEYE, the width of the data eye when reading from the NAND + * Flash. The eye width is fundamentally determined by the data setup + * time, perturbed by propagation delays and some characteristics of the + * NAND Flash device. + * + * start of the eye = max_prop_delay + tREA + * end of the eye = min_prop_delay + tRHOH + data_setup + */ + + tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns + + (int)data_setup_in_ns; + + tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns; + + /* + * The eye must be open. If it's not, we can try to open it by + * increasing its main forcer, the data setup time. + * + * In each iteration of the following loop, we increase the data setup + * time by a single clock cycle. We do this until either the eye is + * open or we run into NFC limits. + */ + + while ((tEYE <= 0) && + (data_setup_in_cycles < nfc->max_data_setup_cycles)) { + /* Give a cycle to data setup. */ + data_setup_in_cycles++; + /* Synchronize the data setup time with the cycles. */ + data_setup_in_ns += clock_period_in_ns; + /* Adjust tEYE accordingly. */ + tEYE += clock_period_in_ns; + } + + /* + * When control arrives here, the eye is open. The ideal time to sample + * the data is in the center of the eye: + * + * end of the eye + start of the eye + * --------------------------------- - data_setup + * 2 + * + * After some algebra, this simplifies to the code immediately below. + */ + + ideal_sample_delay_in_ns = + ((int)max_prop_delay_in_ns + + (int)target.tREA_in_ns + + (int)min_prop_delay_in_ns + + (int)target.tRHOH_in_ns - + (int)data_setup_in_ns) >> 1; + + /* + * The following figure illustrates some aspects of a NAND Flash read: + * + * + * __ _____________________________________ + * RDN \_________________/ + * + * <---- tEYE -----> + * /-----------------\ + * Read Data ----------------------------< >--------- + * \-----------------/ + * ^ ^ ^ ^ + * | | | | + * |<--Data Setup -->|<--Delay Time -->| | + * | | | | + * | | | + * | |<-- Quantized Delay Time -->| + * | | | + * + * + * We have some issues we must now address: + * + * (1) The *ideal* sample delay time must not be negative. If it is, we + * jam it to zero. + * + * (2) The *ideal* sample delay time must not be greater than that + * allowed by the NFC. If it is, we can increase the data setup + * time, which will reduce the delay between the end of the data + * setup and the center of the eye. It will also make the eye + * larger, which might help with the next issue... + * + * (3) The *quantized* sample delay time must not fall either before the + * eye opens or after it closes (the latter is the problem + * illustrated in the above figure). + */ + + /* Jam a negative ideal sample delay to zero. */ + + if (ideal_sample_delay_in_ns < 0) + ideal_sample_delay_in_ns = 0; + + /* + * Extend the data setup as needed to reduce the ideal sample delay + * below the maximum permitted by the NFC. + */ + + while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) && + (data_setup_in_cycles < nfc->max_data_setup_cycles)) { + + /* Give a cycle to data setup. */ + data_setup_in_cycles++; + /* Synchronize the data setup time with the cycles. */ + data_setup_in_ns += clock_period_in_ns; + /* Adjust tEYE accordingly. */ + tEYE += clock_period_in_ns; + + /* + * Decrease the ideal sample delay by one half cycle, to keep it + * in the middle of the eye. + */ + ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1); + + /* Jam a negative ideal sample delay to zero. */ + if (ideal_sample_delay_in_ns < 0) + ideal_sample_delay_in_ns = 0; + + } + + /* + * Compute the sample delay factor that corresponds to the ideal sample + * delay. If the result is too large, then use the maximum allowed + * value. + * + * Notice that we use the ns_to_cycles function to compute the sample + * delay factor. We do this because the form of the computation is the + * same as that for calculating cycles. + */ + + sample_delay_factor = + ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift, + clock_period_in_ns, 0); + + if (sample_delay_factor > nfc->max_sample_delay_factor) + sample_delay_factor = nfc->max_sample_delay_factor; + + /* + * These macros conveniently encapsulate a computation we'll use to + * continuously evaluate whether or not the data sample delay is inside + * the eye. + */ + + #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns) + + #define QUANTIZED_DELAY \ + ((int) ((sample_delay_factor * clock_period_in_ns) >> \ + dll_delay_shift)) + + #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY)) + + #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1)) + + /* + * While the quantized sample time falls outside the eye, reduce the + * sample delay or extend the data setup to move the sampling point back + * toward the eye. Do not allow the number of data setup cycles to + * exceed the maximum allowed by the NFC. + */ + + while (SAMPLE_IS_NOT_WITHIN_THE_EYE && + (data_setup_in_cycles < nfc->max_data_setup_cycles)) { + + /* + * If control arrives here, the quantized sample delay falls + * outside the eye. Check if it's before the eye opens, or after + * the eye closes. + */ + + if (QUANTIZED_DELAY > IDEAL_DELAY) { + + /* + * If control arrives here, the quantized sample delay + * falls after the eye closes. Decrease the quantized + * delay time and then go back to re-evaluate. + */ + + if (sample_delay_factor != 0) + sample_delay_factor--; + + continue; + + } + + /* + * If control arrives here, the quantized sample delay falls + * before the eye opens. Shift the sample point by increasing + * data setup time. This will also make the eye larger. + */ + + /* Give a cycle to data setup. */ + data_setup_in_cycles++; + /* Synchronize the data setup time with the cycles. */ + data_setup_in_ns += clock_period_in_ns; + /* Adjust tEYE accordingly. */ + tEYE += clock_period_in_ns; + + /* + * Decrease the ideal sample delay by one half cycle, to keep it + * in the middle of the eye. + */ + ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1); + + /* ...and one less period for the delay time. */ + ideal_sample_delay_in_ns -= clock_period_in_ns; + + /* Jam a negative ideal sample delay to zero. */ + if (ideal_sample_delay_in_ns < 0) + ideal_sample_delay_in_ns = 0; + + /* + * We have a new ideal sample delay, so re-compute the quantized + * delay. + */ + + sample_delay_factor = + ns_to_cycles( + ideal_sample_delay_in_ns << dll_delay_shift, + clock_period_in_ns, 0); + + if (sample_delay_factor > nfc->max_sample_delay_factor) + sample_delay_factor = nfc->max_sample_delay_factor; + + } + + /* Control arrives here when we're ready to return our results. */ + +return_results: + hw->data_setup_in_cycles = data_setup_in_cycles; + hw->data_hold_in_cycles = data_hold_in_cycles; + hw->address_setup_in_cycles = address_setup_in_cycles; + hw->use_half_periods = dll_use_half_periods; + hw->sample_delay_factor = sample_delay_factor; + + /* Return success. */ + return 0; +} diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c new file mode 100644 index 000000000000..a1e22a003e53 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v0.c @@ -0,0 +1,664 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +#include "gpmi-nfc-gpmi-regs-v0.h" +#include "gpmi-nfc-bch-regs-v0.h" + +/** + * init() - Initializes the NFC hardware. + * + * @this: Per-device data. + */ +static int init(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + int error; + + /* Initialize DMA. */ + error = gpmi_nfc_dma_init(this); + if (error) + return error; + + /* Enable the clock. It will stay on until the end of set_geometry(). */ + clk_enable(resources->clock); + + /* Reset the GPMI block. */ + mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true); + + /* Choose NAND mode. */ + __raw_writel(BM_GPMI_CTRL1_GPMI_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* Set the IRQ polarity. */ + __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable write protection. */ + __raw_writel(BM_GPMI_CTRL1_DEV_RESET, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Select BCH ECC. */ + __raw_writel(BM_GPMI_CTRL1_BCH_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable the clock. */ + clk_disable(resources->clock); + + return 0; +} + +/** + * set_geometry() - Configures the NFC geometry. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_geometry *nfc = &this->nfc_geometry; + unsigned int block_count; + unsigned int block_size; + unsigned int metadata_size; + unsigned int ecc_strength; + unsigned int page_size; + + /* We make the abstract choices in a common function. */ + if (gpmi_nfc_set_geometry(this)) + return !0; + + /* Translate the abstract choices into register fields. */ + block_count = nfc->ecc_chunk_count - 1; + block_size = nfc->ecc_chunk_size_in_bytes; + metadata_size = nfc->metadata_size_in_bytes; + ecc_strength = nfc->ecc_strength >> 1; + page_size = nfc->page_size_in_bytes; + + /* Enable the clock. */ + clk_enable(resources->clock); + + /* + * Reset the BCH block. Notice that we pass in true for the just_enable + * flag. This is because the soft reset for the version 0 BCH block + * doesn't work. If you try to soft reset the BCH block, it becomes + * unusable until the next hard reset. + */ + mxs_reset_block(resources->bch_regs, true); + + /* Configure layout 0. */ + __raw_writel( + BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) | + BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) | + BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) | + BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT0); + + __raw_writel( + BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | + BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) | + BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT1); + + /* Set *all* chip selects to use layout 0. */ + __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT); + + /* Enable interrupts. */ + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, + resources->bch_regs + HW_BCH_CTRL_SET); + + /* Disable the clock. */ + clk_disable(resources->clock); + + return 0; +} + +/** + * set_timing() - Configures the NFC timing. + * + * @this: Per-device data. + * @timing: The timing of interest. + */ +static int set_timing(struct gpmi_nfc_data *this, + const struct gpmi_nfc_timing *timing) +{ + struct nfc_hal *nfc = this->nfc; + + /* Accept the new timing. */ + nfc->timing = *timing; + return 0; +} + +/** + * get_timing() - Retrieves the NFC hardware timing. + * + * @this: Per-device data. + * @clock_frequency_in_hz: The clock frequency, in Hz, during the current + * I/O transaction. If no I/O transaction is in + * progress, this is the clock frequency during the + * most recent I/O transaction. + * @hardware_timing: The hardware timing configuration in effect during + * the current I/O transaction. If no I/O transaction + * is in progress, this is the hardware timing + * configuration during the most recent I/O + * transaction. + */ +static void get_timing(struct gpmi_nfc_data *this, + unsigned long *clock_frequency_in_hz, + struct gpmi_nfc_hardware_timing *hardware_timing) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + unsigned char *gpmi_regs = resources->gpmi_regs; + uint32_t register_image; + + /* Return the clock frequency. */ + *clock_frequency_in_hz = nfc->clock_frequency_in_hz; + + /* We'll be reading the hardware, so let's enable the clock. */ + clk_enable(resources->clock); + + /* Retrieve the hardware timing. */ + register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0); + + hardware_timing->data_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_SETUP) >> + BP_GPMI_TIMING0_DATA_SETUP; + + hardware_timing->data_hold_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_HOLD) >> + BP_GPMI_TIMING0_DATA_HOLD; + + hardware_timing->address_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >> + BP_GPMI_TIMING0_ADDRESS_SETUP; + + register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1); + + hardware_timing->use_half_periods = + (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >> + BP_GPMI_CTRL1_HALF_PERIOD; + + hardware_timing->sample_delay_factor = + (register_image & BM_GPMI_CTRL1_RDN_DELAY) >> + BP_GPMI_CTRL1_RDN_DELAY; + + /* We're done reading the hardware, so disable the clock. */ + clk_disable(resources->clock); +} + +/** + * exit() - Shuts down the NFC hardware. + * + * @this: Per-device data. + */ +static void exit(struct gpmi_nfc_data *this) +{ + gpmi_nfc_dma_exit(this); +} + +/** + * begin() - Begin NFC I/O. + * + * @this: Per-device data. + */ +static void begin(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_hardware_timing hw; + unsigned char *gpmi_regs = resources->gpmi_regs; + unsigned int clock_period_in_ns; + uint32_t register_image; + unsigned int dll_wait_time_in_us; + + /* Enable the clock. */ + clk_enable(resources->clock); + + /* Get the timing information we need. */ + nfc->clock_frequency_in_hz = clk_get_rate(resources->clock); + clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz; + + gpmi_nfc_compute_hardware_timing(this, &hw); + + /* Set up all the simple timing parameters. */ + register_image = + BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) | + BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) | + BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ; + + __raw_writel(register_image, gpmi_regs + HW_GPMI_TIMING0); + + /* + * HEY - PAY ATTENTION! + * + * DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD. + */ + __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* Clear out the DLL control fields. */ + __raw_writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR); + __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* If no sample delay is called for, return immediately. */ + if (!hw.sample_delay_factor) + return; + + /* Configure the HALF_PERIOD flag. */ + + if (hw.use_half_periods) + __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, + gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Set the delay factor. */ + __raw_writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor), + gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Enable the DLL. */ + __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET); + + /* + * After we enable the GPMI DLL, we have to wait 64 clock cycles before + * we can use the GPMI. + * + * Calculate the amount of time we need to wait, in microseconds. + */ + dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000; + + if (!dll_wait_time_in_us) + dll_wait_time_in_us = 1; + + /* Wait for the DLL to settle. */ + udelay(dll_wait_time_in_us); +} + +/** + * end() - End NFC I/O. + * + * @this: Per-device data. + */ +static void end(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + /* Disable the clock. */ + clk_disable(resources->clock); +} + +/** + * clear_bch() - Clears a BCH interrupt. + * + * @this: Per-device data. + */ +static void clear_bch(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, + resources->bch_regs + HW_BCH_CTRL_CLR); +} + +/** + * is_ready() - Returns the ready/busy status of the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + */ +static int is_ready(struct gpmi_nfc_data *this, unsigned chip) +{ + struct resources *resources = &this->resources; + uint32_t mask; + uint32_t register_image; + + /* Extract and return the status. */ + mask = BM_GPMI_DEBUG_READY0 << chip; + register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_DEBUG); + return !!(register_image & mask); +} + +/** + * send_command() - Sends a command and associated addresses. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the command bytes. + * @length: The number of bytes in the buffer. + */ +static int send_command(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that sends out the command. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_CLE; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_READ, 1, 1, 0, 0, 1, 1, 0, 0, 3, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BM_GPMI_CTRL0_ADDRESS_INCREMENT | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * send_data() - Sends data to the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the data. + * @length: The number of bytes in the buffer. + */ +static int send_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that writes a buffer out. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_READ, 0, 1, 0, 0, 1, 1, 0, 0, 4, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * read_data() - Receives data from the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that will receive the data. + * @length: The number of bytes to read. + */ +static int read_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that reads the data. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_WRITE, 1, 0, 0, 0, 1, 1, 0, 0, 1, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* + * A DMA descriptor that waits for the command to end and the chip to + * become ready. + * + * I think we actually should *not* be waiting for the chip to become + * ready because, after all, we don't care. I think the original code + * did that and no one has re-thought it yet. + */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 0, 1, 0, 1, 1, 1, 0, 0, 4, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * send_page() - Sends a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int send_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* A DMA descriptor that does an ECC page read. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 0, 1, 0, 0, 1, 1, 0, 0, 6, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_with_bch_irq(this, dma_channel); +} + +/** + * read_page() - Reads a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int read_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Wait for the chip to report ready. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Enable the BCH block and read. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 0, 1, 1, 0, 0, 6, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Disable the BCH block */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 1, 1, 1, 0, 0, 3, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Deassert the NAND lock and interrupt. */ + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0); + (*d)->cmd.address = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_with_bch_irq(this, dma_channel); +} + +/* This structure represents the NFC HAL for this version of the hardware. */ +struct nfc_hal gpmi_nfc_hal_v0 = { + .version = 0, + .description = "4-chip GPMI and BCH", + .max_chip_count = 4, + .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >> + BP_GPMI_TIMING0_DATA_SETUP), + .internal_data_setup_in_ns = 0, + .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >> + BP_GPMI_CTRL1_RDN_DELAY), + .max_dll_clock_period_in_ns = 32, + .max_dll_delay_in_ns = 16, + .init = init, + .set_geometry = set_geometry, + .set_timing = set_timing, + .get_timing = get_timing, + .exit = exit, + .begin = begin, + .end = end, + .clear_bch = clear_bch, + .is_ready = is_ready, + .send_command = send_command, + .send_data = send_data, + .read_data = read_data, + .send_page = send_page, + .read_page = read_page, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c new file mode 100644 index 000000000000..80c71c4f7817 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v1.c @@ -0,0 +1,625 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include "gpmi-nfc.h" +#include "gpmi-nfc-gpmi-regs-v1.h" +#include "gpmi-nfc-bch-regs-v1.h" + +/** + * init() - Initializes the NFC hardware. + * + * @this: Per-device data. + */ +static int init(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + int error; + + /* Initialize DMA. */ + error = gpmi_nfc_dma_init(this); + if (error) + return error; + + /* Enable the clock. */ + clk_enable(resources->clock); + + /* Reset the GPMI block. */ + mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true); + + /* Choose NAND mode. */ + __raw_writel(BM_GPMI_CTRL1_GPMI_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* Set the IRQ polarity. */ + __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable write protection. */ + __raw_writel(BM_GPMI_CTRL1_DEV_RESET, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Select BCH ECC. */ + __raw_writel(BM_GPMI_CTRL1_BCH_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable the clock. */ + clk_disable(resources->clock); + + return 0; +} + +/** + * set_geometry() - Configures the NFC geometry. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_geometry *nfc = &this->nfc_geometry; + unsigned int block_count; + unsigned int block_size; + unsigned int metadata_size; + unsigned int ecc_strength; + unsigned int page_size; + + /* We make the abstract choices in a common function. */ + if (gpmi_nfc_set_geometry(this)) + return !0; + + /* Translate the abstract choices into register fields. */ + block_count = nfc->ecc_chunk_count - 1; + block_size = nfc->ecc_chunk_size_in_bytes; + metadata_size = nfc->metadata_size_in_bytes; + ecc_strength = nfc->ecc_strength >> 1; + page_size = nfc->page_size_in_bytes; + + /* Enable the clock. */ + clk_enable(resources->clock); + + /* + * Reset the BCH block. Notice that we pass in true for the just_enable + * flag. This is because the soft reset for the version 0 BCH block + * doesn't work and the version 1 BCH block is similar enough that we + * suspect the same (though this has not been officially tested). If you + * try to soft reset a version 0 BCH block, it becomes unusable until + * the next hard reset. + */ + mxs_reset_block(resources->bch_regs, true); + + /* Configure layout 0. */ + __raw_writel( + BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) | + BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) | + BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) | + BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT0); + + __raw_writel( + BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | + BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) | + BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) , + resources->bch_regs + HW_BCH_FLASH0LAYOUT1); + + /* Set *all* chip selects to use layout 0. */ + __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT); + + /* Enable interrupts. */ + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, + resources->bch_regs + HW_BCH_CTRL_SET); + + /* Disable the clock. */ + clk_disable(resources->clock); + + return 0; +} + +/** + * set_timing() - Configures the NFC timing. + * + * @this: Per-device data. + * @timing: The timing of interest. + */ +static int set_timing(struct gpmi_nfc_data *this, + const struct gpmi_nfc_timing *timing) +{ + struct nfc_hal *nfc = this->nfc; + + /* Accept the new timing. */ + nfc->timing = *timing; + return 0; +} + +/** + * get_timing() - Retrieves the NFC hardware timing. + * + * @this: Per-device data. + * @clock_frequency_in_hz: The clock frequency, in Hz, during the current + * I/O transaction. If no I/O transaction is in + * progress, this is the clock frequency during the + * most recent I/O transaction. + * @hardware_timing: The hardware timing configuration in effect during + * the current I/O transaction. If no I/O transaction + * is in progress, this is the hardware timing + * configuration during the most recent I/O + * transaction. + */ +static void get_timing(struct gpmi_nfc_data *this, + unsigned long *clock_frequency_in_hz, + struct gpmi_nfc_hardware_timing *hardware_timing) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + unsigned char *gpmi_regs = resources->gpmi_regs; + uint32_t register_image; + + /* Return the clock frequency. */ + + *clock_frequency_in_hz = nfc->clock_frequency_in_hz; + + /* We'll be reading the hardware, so let's enable the clock. */ + + clk_enable(resources->clock); + + /* Retrieve the hardware timing. */ + + register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0); + + hardware_timing->data_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_SETUP) >> + BP_GPMI_TIMING0_DATA_SETUP; + + hardware_timing->data_hold_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_HOLD) >> + BP_GPMI_TIMING0_DATA_HOLD; + + hardware_timing->address_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >> + BP_GPMI_TIMING0_ADDRESS_SETUP; + + register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1); + + hardware_timing->use_half_periods = + (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >> + BP_GPMI_CTRL1_HALF_PERIOD; + + hardware_timing->sample_delay_factor = + (register_image & BM_GPMI_CTRL1_RDN_DELAY) >> + BP_GPMI_CTRL1_RDN_DELAY; + + /* We're done reading the hardware, so disable the clock. */ + + clk_disable(resources->clock); + +} + +/** + * exit() - Shuts down the NFC hardware. + * + * @this: Per-device data. + */ +static void exit(struct gpmi_nfc_data *this) +{ + gpmi_nfc_dma_exit(this); +} + +/** + * begin() - Begin NFC I/O. + * + * @this: Per-device data. + */ +static void begin(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_hardware_timing hw; + + /* Enable the clock. */ + clk_enable(resources->clock); + + /* Get the timing information we need. */ + nfc->clock_frequency_in_hz = clk_get_rate(resources->clock); + gpmi_nfc_compute_hardware_timing(this, &hw); + + /* Apply the hardware timing. */ + + /* Coming soon - the clock handling code isn't ready yet. */ +} + +/** + * end() - End NFC I/O. + * + * @this: Per-device data. + */ +static void end(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + /* Disable the clock. */ + clk_disable(resources->clock); +} + +/** + * clear_bch() - Clears a BCH interrupt. + * + * @this: Per-device data. + */ +static void clear_bch(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, + resources->bch_regs + HW_BCH_CTRL_CLR); +} + +/** + * is_ready() - Returns the ready/busy status of the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + */ +static int is_ready(struct gpmi_nfc_data *this, unsigned chip) +{ + struct resources *resources = &this->resources; + uint32_t mask; + uint32_t register_image; + + /* Extract and return the status. */ + mask = BF_GPMI_STAT_READY_BUSY(1 << chip); + register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT); + return !!(register_image & mask); +} + +/** + * send_command() - Sends a command and associated addresses. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the command bytes. + * @length: The number of bytes in the buffer. + */ +static int send_command(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that sends out the command. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_CLE; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_READ, 1, 1, 0, 0, 1, 1, 0, 0, 3, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BM_GPMI_CTRL0_ADDRESS_INCREMENT | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * send_data() - Sends data to the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the data. + * @length: The number of bytes in the buffer. + */ +static int send_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that writes a buffer out. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_READ, 0, 1, 0, 0, 1, 1, 0, 0, 4, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * read_data() - Receives data from the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that will receive the data. + * @length: The number of bytes to read. + */ +static int read_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that reads the data. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_WRITE, 1, 0, 0, 0, 1, 1, 0, 0, 1, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* + * A DMA descriptor that waits for the command to end and the chip to + * become ready. + * + * I think we actually should *not* be waiting for the chip to become + * ready because, after all, we don't care. I think the original code + * did that and no one has re-thought it yet. + */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 0, 1, 0, 1, 1, 1, 0, 0, 4, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * send_page() - Sends a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int send_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Compute the DMA channel. */ + + dma_channel = resources->dma_low_channel + chip; + + /* A DMA descriptor that does an ECC page read. */ + + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 0, 1, 0, 0, 1, 1, 0, 0, 6, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + (*d)->cmd.pio_words[1] = 0; + + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_with_bch_irq(this, dma_channel); +} + +/** + * read_page() - Reads a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int read_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + + /* Wait for the chip to report ready. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(0) ; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Enable the BCH block and read. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__DECODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 0, 1, 1, 0, 0, 6, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = + BM_GPMI_ECCCTRL_ENABLE_ECC | + BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | + BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + (*d)->cmd.pio_words[3] = nfc_geo->page_size_in_bytes; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Disable the BCH block */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 1, 1, 1, 0, 0, 3, 0); + (*d)->cmd.address = 0; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(nfc_geo->page_size_in_bytes) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Deassert the NAND lock and interrupt. */ + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0); + (*d)->cmd.address = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_with_bch_irq(this, dma_channel); +} + +/* This structure represents the NFC HAL for this version of the hardware. */ + +struct nfc_hal gpmi_nfc_hal_v1 = { + .version = 1, + .description = "8-chip GPMI and BCH", + .max_chip_count = 8, + .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >> + BP_GPMI_TIMING0_DATA_SETUP), + .internal_data_setup_in_ns = 0, + .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >> + BP_GPMI_CTRL1_RDN_DELAY), + .max_dll_clock_period_in_ns = 32, + .max_dll_delay_in_ns = 16, + .init = init, + .set_geometry = set_geometry, + .set_timing = set_timing, + .get_timing = get_timing, + .exit = exit, + .begin = begin, + .end = end, + .clear_bch = clear_bch, + .is_ready = is_ready, + .send_command = send_command, + .send_data = send_data, + .read_data = read_data, + .send_page = send_page, + .read_page = read_page, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c new file mode 100644 index 000000000000..a92dfa69bdf1 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-hal-v2.c @@ -0,0 +1,918 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include "gpmi-nfc.h" +#include "gpmi-nfc-gpmi-regs-v2.h" +#include "gpmi-nfc-bch-regs-v2.h" + +#define FEATURE_SIZE (4) /* p1, p2, p3, p4 */ + +/* + * How many clocks do we need in low power mode? + * We try to list them : + * GMPI : gpmi_apb_clk, gpmi_io_clk + * BCH : bch_clk, bch_apb_clk + * DMA(RAM) : apbh_dma_clk, ddr_clk(RAM), ahb_max_clk(RAM) + * (APBHDMA fetches DMA descriptors from DDR + * through AHB-MAX/PL301) + * NAND : + * ONFI NAND : pll1_main_clk + */ +static struct clk *ddr_clk; +static struct clk *apbh_dma_clk; +static struct clk *ahb_max_clk; + +static void setup_ddr_timing_onfi(struct gpmi_nfc_data *this) +{ + uint32_t value; + struct resources *resources = &this->resources; + + /* set timing 2 register */ + value = BF_GPMI_TIMING2_DATA_PAUSE(0x6) + | BF_GPMI_TIMING2_CMDADD_PAUSE(0x4) + | BF_GPMI_TIMING2_POSTAMBLE_DELAY(0x2) + | BF_GPMI_TIMING2_PREAMBLE_DELAY(0x4) + | BF_GPMI_TIMING2_CE_DELAY(0x2) + | BF_GPMI_TIMING2_READ_LATENCY(0x2); + + __raw_writel(value, resources->gpmi_regs + HW_GPMI_TIMING2); + + /* set timing 1 register */ + __raw_writel(BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(0x500), + resources->gpmi_regs + HW_GPMI_TIMING1); + + /* Put GPMI in NAND mode, disable device reset, and make certain + IRQRDY polarity is active high. */ + value = BV_GPMI_CTRL1_GPMI_MODE__NAND + | BM_GPMI_CTRL1_GANGED_RDYBUSY + | BF_GPMI_CTRL1_WRN_DLY_SEL(0x3) + | (BV_GPMI_CTRL1_DEV_RESET__DISABLED << 3) + | (BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH << 2); + + __raw_writel(value, resources->gpmi_regs + HW_GPMI_CTRL1_SET); +} + +/* This must be called in the context of enabling necessary clocks */ +static void common_ddr_init(struct resources *resources) +{ + uint32_t value; + + /* [6] enable both write & read DDR DLLs */ + value = BM_GPMI_READ_DDR_DLL_CTRL_REFCLK_ON | + BM_GPMI_READ_DDR_DLL_CTRL_ENABLE | + BF_GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(0x2) | + BF_GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(0x7); + + __raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL); + + /* [7] reset read */ + __raw_writel(value | BM_GPMI_READ_DDR_DLL_CTRL_RESET, + resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL); + value = value & ~BM_GPMI_READ_DDR_DLL_CTRL_RESET; + __raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL); + + value = BM_GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON | + BM_GPMI_WRITE_DDR_DLL_CTRL_ENABLE | + BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(0x2) | + BF_GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(0x7) , + + __raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL); + + /* [8] reset write */ + __raw_writel(value | BM_GPMI_WRITE_DDR_DLL_CTRL_RESET, + resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL); + __raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL); + + /* [9] wait for locks for read and write */ + do { + uint32_t read_status, write_status; + uint32_t r_mask, w_mask; + + read_status = __raw_readl(resources->gpmi_regs + + HW_GPMI_READ_DDR_DLL_STS); + write_status = __raw_readl(resources->gpmi_regs + + HW_GPMI_WRITE_DDR_DLL_STS); + + r_mask = (BM_GPMI_READ_DDR_DLL_STS_REF_LOCK | + BM_GPMI_READ_DDR_DLL_STS_SLV_LOCK); + w_mask = (BM_GPMI_WRITE_DDR_DLL_STS_REF_LOCK | + BM_GPMI_WRITE_DDR_DLL_STS_SLV_LOCK); + + if (((read_status & r_mask) == r_mask) + && ((write_status & w_mask) == w_mask)) + break; + } while (1); + + /* [10] force update of read/write */ + value = __raw_readl(resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL); + __raw_writel(value | BM_GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD, + resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL); + __raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL); + + value = __raw_readl(resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL); + __raw_writel(value | BM_GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD, + resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL); + __raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL); + + /* [11] set gate update */ + value = __raw_readl(resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL); + value |= BM_GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE; + __raw_writel(value, resources->gpmi_regs + HW_GPMI_READ_DDR_DLL_CTRL); + + value = __raw_readl(resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL); + value |= BM_GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE; + __raw_writel(value, resources->gpmi_regs + HW_GPMI_WRITE_DDR_DLL_CTRL); +} + +static int enable_ddr_onfi(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct mil *mil = &this->mil; + struct nand_chip *nand = &this->mil.nand; + struct mtd_info *mtd = &mil->mtd; + int saved_chip_number = 0; + uint8_t device_feature[FEATURE_SIZE]; + int mode = 0;/* there is 5 mode available, default is 0 */ + + saved_chip_number = mil->current_chip; + nand->select_chip(mtd, 0); + + /* [0] set proper timing */ + __raw_writel(BF_GPMI_TIMING0_ADDRESS_SETUP(0x1) + | BF_GPMI_TIMING0_DATA_HOLD(0x3) + | BF_GPMI_TIMING0_DATA_SETUP(0x3), + resources->gpmi_regs + HW_GPMI_TIMING0); + + /* [1] send SET FEATURE commond to NAND */ + memset(device_feature, 0, sizeof(device_feature)); + device_feature[0] = (0x1 << 4) | (mode & 0x7); + + nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + nand->cmdfunc(mtd, NAND_CMD_SET_FEATURE, 1, -1); + nand->write_buf(mtd, device_feature, FEATURE_SIZE); + + /* [2] set clk divider */ + __raw_writel(BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* [3] about the clock, pay attention! */ + nand->select_chip(mtd, saved_chip_number); + { + struct clk *pll1; + pll1 = clk_get(NULL, "pll1_main_clk"); + if (IS_ERR(pll1)) { + printk(KERN_INFO "No PLL1 clock\n"); + return -EINVAL; + } + clk_set_parent(resources->clock, pll1); + clk_set_rate(resources->clock, 20000000); + } + nand->select_chip(mtd, 0); + + /* [4] setup timing */ + setup_ddr_timing_onfi(this); + + /* [5] set to SYNC mode */ + __raw_writel(BM_GPMI_CTRL1_TOGGLE_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_CLR); + __raw_writel(BM_GPMI_CTRL1_SSYNCMODE | BM_GPMI_CTRL1_GANGED_RDYBUSY, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* common DDR initialization */ + common_ddr_init(resources); + + nand->select_chip(mtd, saved_chip_number); + + printk(KERN_INFO "Micron ONFI NAND enters synchronous mode %d\n", mode); + return 0; +} + +static void setup_ddr_timing_toggle(struct gpmi_nfc_data *this) +{ + uint32_t value; + struct resources *resources = &this->resources; + + /* set timing 2 register */ + value = BF_GPMI_TIMING2_DATA_PAUSE(0x6) + | BF_GPMI_TIMING2_CMDADD_PAUSE(0x4) + | BF_GPMI_TIMING2_POSTAMBLE_DELAY(0x3) + | BF_GPMI_TIMING2_PREAMBLE_DELAY(0x2) + | BF_GPMI_TIMING2_CE_DELAY(0x2) + | BF_GPMI_TIMING2_READ_LATENCY(0x2); + + __raw_writel(value, resources->gpmi_regs + HW_GPMI_TIMING2); + + /* set timing 1 register */ + __raw_writel(BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(0x500), + resources->gpmi_regs + HW_GPMI_TIMING1); + + /* Put GPMI in NAND mode, disable device reset, and make certain + IRQRDY polarity is active high. */ + value = BV_GPMI_CTRL1_GPMI_MODE__NAND + | BM_GPMI_CTRL1_GANGED_RDYBUSY + | (BV_GPMI_CTRL1_DEV_RESET__DISABLED << 3) + | (BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH << 2); + + __raw_writel(value, resources->gpmi_regs + HW_GPMI_CTRL1_SET); +} + +static int enable_ddr_toggle(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct mil *mil = &this->mil; + struct nand_chip *nand = &this->mil.nand; + struct mtd_info *mtd = &mil->mtd; + int saved_chip_number = mil->current_chip; + + nand->select_chip(mtd, 0); + + /* [0] set proper timing */ + __raw_writel(BF_GPMI_TIMING0_ADDRESS_SETUP(0x5) + | BF_GPMI_TIMING0_DATA_HOLD(0xa) + | BF_GPMI_TIMING0_DATA_SETUP(0xa), + resources->gpmi_regs + HW_GPMI_TIMING0); + + /* [2] set clk divider */ + __raw_writel(BM_GPMI_CTRL1_GPMI_CLK_DIV2_EN, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* [3] about the clock, pay attention! */ + nand->select_chip(mtd, saved_chip_number); + { + struct clk *pll1; + unsigned long rate; + + pll1 = clk_get(NULL, "pll1_main_clk"); + if (IS_ERR(pll1)) { + printk(KERN_INFO "No PLL1 clock\n"); + return -EINVAL; + } + + /* toggle nand : 133/66 MHz */ + rate = 33000000; + clk_set_parent(resources->clock, pll1); + clk_set_rate(resources->clock, rate); + } + nand->select_chip(mtd, 0); + + /* [4] setup timing */ + setup_ddr_timing_toggle(this); + + /* [5] set to TOGGLE mode */ + __raw_writel(BM_GPMI_CTRL1_SSYNCMODE, + resources->gpmi_regs + HW_GPMI_CTRL1_CLR); + __raw_writel(BM_GPMI_CTRL1_TOGGLE_MODE | BM_GPMI_CTRL1_GANGED_RDYBUSY, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* common DDR initialization */ + common_ddr_init(resources); + + nand->select_chip(mtd, saved_chip_number); + + printk(KERN_INFO "-- Sumsung TOGGLE NAND is enabled now. --\n"); + return 0; +} + +/* To check if we need to initialize something else*/ +static int extra_init(struct gpmi_nfc_data *this) +{ + ddr_clk = clk_get(NULL, "ddr_clk"); + if (IS_ERR(ddr_clk)) { + printk(KERN_ERR "The ddr clock is gone!"); + ddr_clk = NULL; + return -ENOENT; + } + apbh_dma_clk = clk_get(NULL, "apbh_dma_clk"); + if (IS_ERR(apbh_dma_clk)) { + printk(KERN_ERR "The APBH_DMA clock is gone!"); + apbh_dma_clk = NULL; + return -ENOENT; + } + ahb_max_clk = clk_get(NULL, "ahb_max_clk"); + if (IS_ERR(ahb_max_clk)) { + printk(KERN_ERR "The APBH_DMA clock is gone!"); + ahb_max_clk = NULL; + return -ENOENT; + } + + if (is_ddr_nand(&this->device_info)) { + switch (this->device_info.manufacturer_code) { + case NAND_MFR_MICRON: + return enable_ddr_onfi(this); + case NAND_MFR_SAMSUNG: + return enable_ddr_toggle(this); + default: + printk(KERN_ERR "You should not reach here.\n"); + BUG(); + } + } + return 0; +} + +/** + * init() - Initializes the NFC hardware. + * + * @this: Per-device data. + */ +static int init(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + int error; + + /* Initialize DMA. */ + error = gpmi_nfc_dma_init(this); + if (error) + return error; + + /* Enable the clock. */ + clk_enable(resources->clock); + + /* Reset the GPMI block. */ + mxs_reset_block(resources->gpmi_regs + HW_GPMI_CTRL0, true); + + /* Choose NAND mode. */ + __raw_writel(BM_GPMI_CTRL1_GPMI_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_CLR); + + /* Set the IRQ polarity. */ + __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable write protection. */ + __raw_writel(BM_GPMI_CTRL1_DEV_RESET, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Select BCH ECC. */ + __raw_writel(BM_GPMI_CTRL1_BCH_MODE, + resources->gpmi_regs + HW_GPMI_CTRL1_SET); + + /* Disable the clock. */ + clk_disable(resources->clock); + + return 0; +} + +/** + * set_geometry() - Configures the NFC geometry. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_geometry *nfc = &this->nfc_geometry; + unsigned int block_count; + unsigned int block_size; + unsigned int metadata_size; + unsigned int ecc_strength; + unsigned int page_size; + uint32_t value; + + /* We make the abstract choices in a common function. */ + if (gpmi_nfc_set_geometry(this)) + return !0; + + /* Translate the abstract choices into register fields. */ + block_count = nfc->ecc_chunk_count - 1; + block_size = nfc->ecc_chunk_size_in_bytes >> 2; + metadata_size = nfc->metadata_size_in_bytes; + ecc_strength = nfc->ecc_strength >> 1; + page_size = nfc->page_size_in_bytes; + + /* Enable the clock. */ + clk_enable(resources->clock); + + /* + * Reset the BCH block. Notice that we pass in true for the just_enable + * flag. This is because the soft reset for the version 0 BCH block + * doesn't work and the version 1 BCH block is similar enough that we + * suspect the same (though this has not been officially tested). If you + * try to soft reset a version 0 BCH block, it becomes unusable until + * the next hard reset. + */ + mxs_reset_block(resources->bch_regs, false); + + /* Configure layout 0. */ + value = BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) | + BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) | + BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) | + BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size); + if (is_ddr_nand(&this->device_info)) + value |= BM_BCH_FLASH0LAYOUT0_GF13_0_GF14_1; + + __raw_writel(value, resources->bch_regs + HW_BCH_FLASH0LAYOUT0); + + value = BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | + BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) | + BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size); + if (is_ddr_nand(&this->device_info)) + value |= BM_BCH_FLASH0LAYOUT1_GF13_0_GF14_1; + + __raw_writel(value, resources->bch_regs + HW_BCH_FLASH0LAYOUT1); + + /* Set *all* chip selects to use layout 0. */ + __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT); + + /* Enable interrupts. */ + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, + resources->bch_regs + HW_BCH_CTRL_SET); + + /* Disable the clock. */ + clk_disable(resources->clock); + + return 0; +} + +/** + * set_timing() - Configures the NFC timing. + * + * @this: Per-device data. + * @timing: The timing of interest. + */ +static int set_timing(struct gpmi_nfc_data *this, + const struct gpmi_nfc_timing *timing) +{ + struct nfc_hal *nfc = this->nfc; + + /* Accept the new timing. */ + nfc->timing = *timing; + return 0; +} + +/** + * get_timing() - Retrieves the NFC hardware timing. + * + * @this: Per-device data. + * @clock_frequency_in_hz: The clock frequency, in Hz, during the current + * I/O transaction. If no I/O transaction is in + * progress, this is the clock frequency during the + * most recent I/O transaction. + * @hardware_timing: The hardware timing configuration in effect during + * the current I/O transaction. If no I/O transaction + * is in progress, this is the hardware timing + * configuration during the most recent I/O + * transaction. + */ +static void get_timing(struct gpmi_nfc_data *this, + unsigned long *clock_frequency_in_hz, + struct gpmi_nfc_hardware_timing *hardware_timing) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + unsigned char *gpmi_regs = resources->gpmi_regs; + uint32_t register_image; + + /* Return the clock frequency. */ + *clock_frequency_in_hz = nfc->clock_frequency_in_hz; + + /* We'll be reading the hardware, so let's enable the clock. */ + clk_enable(resources->clock); + + /* Retrieve the hardware timing. */ + register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0); + + hardware_timing->data_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_SETUP) >> + BP_GPMI_TIMING0_DATA_SETUP; + + hardware_timing->data_hold_in_cycles = + (register_image & BM_GPMI_TIMING0_DATA_HOLD) >> + BP_GPMI_TIMING0_DATA_HOLD; + + hardware_timing->address_setup_in_cycles = + (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >> + BP_GPMI_TIMING0_ADDRESS_SETUP; + + register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1); + + hardware_timing->use_half_periods = + (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >> + BP_GPMI_CTRL1_HALF_PERIOD; + + hardware_timing->sample_delay_factor = + (register_image & BM_GPMI_CTRL1_RDN_DELAY) >> + BP_GPMI_CTRL1_RDN_DELAY; + + /* We're done reading the hardware, so disable the clock. */ + clk_disable(resources->clock); +} + +/** + * exit() - Shuts down the NFC hardware. + * + * @this: Per-device data. + */ +static void exit(struct gpmi_nfc_data *this) +{ + gpmi_nfc_dma_exit(this); +} + +/** + * begin() - Begin NFC I/O. + * + * @this: Per-device data. + */ +static void begin(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_hardware_timing hw; + + /* Enable the clock. */ + if (ddr_clk) + clk_enable(ddr_clk); + if (apbh_dma_clk) + clk_enable(apbh_dma_clk); + if (ahb_max_clk) + clk_enable(ahb_max_clk); + clk_enable(resources->clock); + + /* Get the timing information we need. */ + nfc->clock_frequency_in_hz = clk_get_rate(resources->clock); + gpmi_nfc_compute_hardware_timing(this, &hw); + + /* Apply the hardware timing. */ + + /* Coming soon - the clock handling code isn't ready yet. */ + +} + +/** + * end() - End NFC I/O. + * + * @this: Per-device data. + */ +static void end(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + clk_disable(resources->clock); + if (ahb_max_clk) + clk_disable(ahb_max_clk); + if (apbh_dma_clk) + clk_disable(apbh_dma_clk); + if (ddr_clk) + clk_disable(ddr_clk); +} + +/** + * clear_bch() - Clears a BCH interrupt. + * + * @this: Per-device data. + */ +static void clear_bch(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, + resources->bch_regs + HW_BCH_CTRL_CLR); +} + +/** + * is_ready() - Returns the ready/busy status of the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + */ +static int is_ready(struct gpmi_nfc_data *this, unsigned chip) +{ + struct resources *resources = &this->resources; + uint32_t mask; + uint32_t register_image; + + /* Extract and return the status. */ + mask = BF_GPMI_STAT_READY_BUSY(1 << 0); + register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT); + return !!(register_image & mask); +} + +/** + * send_command() - Sends a command and associated addresses. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the command bytes. + * @length: The number of bytes in the buffer. + */ +static int send_command(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that sends out the command. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_CLE; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_READ, 0, 1, 1, 0, 1, 1, 1, 0, 3, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BM_GPMI_CTRL0_LOCK_CS | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BM_GPMI_CTRL0_ADDRESS_INCREMENT | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * send_data() - Sends data to the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that contains the data. + * @length: The number of bytes in the buffer. + */ +static int send_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that writes a buffer out. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_READ, 0, 1, 0, 0, 1, 1, 0, 0, 4, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + (*d)->cmd.pio_words[3] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * read_data() - Receives data from the given chip. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @buffer: The physical address of a buffer that will receive the data. + * @length: The number of bytes to read. + */ +static int read_data(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t buffer, unsigned int length) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + + /* A DMA descriptor that reads the data. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + DMA_WRITE, 0, 1, 0, 0, 1, 1, 1, 0, 1, length); + (*d)->cmd.address = buffer; + + (*d)->cmd.pio_words[0] = + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | + BM_GPMI_CTRL0_WORD_LENGTH | + BF_GPMI_CTRL0_CS(chip) | + BF_GPMI_CTRL0_ADDRESS(address) | + BF_GPMI_CTRL0_XFER_COUNT(length) ; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_without_bch_irq(this, dma_channel); +} + +/** + * send_page() - Sends a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int send_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mxs_dma_desc **d = nfc->dma_descriptors; + struct nand_device_info *info = &this->device_info; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + uint32_t page_size; + uint32_t busw; + + /* DDR use the 16-bit for DATA transmission! */ + if (is_ddr_nand(info)) { + busw = BV_GPMI_CTRL0_WORD_LENGTH__16_BIT; + page_size = nfc_geo->page_size_in_bytes >> 1; + } else { + busw = BM_GPMI_CTRL0_WORD_LENGTH; + page_size = nfc_geo->page_size_in_bytes; + } + + /* A DMA descriptor that does an ECC page read. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 0, 1, 0, 0, 1, 1, 0, 0, 6, 0); + (*d)->cmd.address = 0; + (*d)->cmd.pio_words[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) + | BF_GPMI_CTRL0_CS(chip) + | BF_GPMI_CTRL0_ADDRESS(address) + | BF_GPMI_CTRL0_XFER_COUNT(0) + | busw; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = BM_GPMI_ECCCTRL_ENABLE_ECC + | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) + | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ; + (*d)->cmd.pio_words[3] = page_size; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_with_bch_irq(this, dma_channel); +} + +/** + * read_page() - Reads a page, using ECC. + * + * @this: Per-device data. + * @chip: The chip of interest. + * @payload: The physical address of the payload buffer. + * @auxiliary: The physical address of the auxiliary buffer. + */ +static int read_page(struct gpmi_nfc_data *this, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary) +{ + struct resources *resources = &this->resources; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct nand_device_info *info = &this->device_info; + struct mxs_dma_desc **d = nfc->dma_descriptors; + int dma_channel = resources->dma_low_channel + chip; + uint32_t command_mode; + uint32_t address; + uint32_t ecc_command; + uint32_t buffer_mask; + uint32_t page_size; + uint32_t busw; + + /* DDR use the 16-bit for DATA transmission! */ + if (is_ddr_nand(info)) { + busw = BV_GPMI_CTRL0_WORD_LENGTH__16_BIT; + page_size = nfc_geo->page_size_in_bytes >> 1; + } else { + busw = BM_GPMI_CTRL0_WORD_LENGTH; + page_size = nfc_geo->page_size_in_bytes; + } + + /* Wait for the chip to report ready. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0); + (*d)->cmd.address = 0; + (*d)->cmd.pio_words[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) + | BF_GPMI_CTRL0_CS(chip) + | BF_GPMI_CTRL0_ADDRESS(address) + | BF_GPMI_CTRL0_XFER_COUNT(0) + | busw; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Enable the BCH block and read. */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__DECODE; + buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | + BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 0, 0, 1, 0, 0, 6, 0); + (*d)->cmd.address = 0; + (*d)->cmd.pio_words[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) + | BF_GPMI_CTRL0_CS(chip) + | BF_GPMI_CTRL0_ADDRESS(address) + | BF_GPMI_CTRL0_XFER_COUNT(page_size) + | busw; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = BM_GPMI_ECCCTRL_ENABLE_ECC + | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) + | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask); + (*d)->cmd.pio_words[3] = page_size; + (*d)->cmd.pio_words[4] = payload; + (*d)->cmd.pio_words[5] = auxiliary; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Disable the BCH block */ + command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; + address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; + + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 1, 0, 0, 1, 0, 1, 0, 0, 3, 0); + (*d)->cmd.address = 0; + (*d)->cmd.pio_words[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) + | BF_GPMI_CTRL0_CS(chip) + | BF_GPMI_CTRL0_ADDRESS(address) + | BF_GPMI_CTRL0_XFER_COUNT(page_size) + | busw; + (*d)->cmd.pio_words[1] = 0; + (*d)->cmd.pio_words[2] = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + d++; + + /* Deassert the NAND lock and interrupt. */ + fill_dma_word1(&(*d)->cmd.cmd, + NO_DMA_XFER, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0); + (*d)->cmd.address = 0; + + mxs_dma_desc_append(dma_channel, (*d)); + + return start_dma_with_bch_irq(this, dma_channel); +} + +/* This structure represents the NFC HAL for this version of the hardware. */ +struct nfc_hal gpmi_nfc_hal_v2 = { + .version = 2, + .description = "8-chip GPMI and BCH", + .max_chip_count = 8, + .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >> + BP_GPMI_TIMING0_DATA_SETUP), + .internal_data_setup_in_ns = 0, + .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >> + BP_GPMI_CTRL1_RDN_DELAY), + .max_dll_clock_period_in_ns = 32, + .max_dll_delay_in_ns = 16, + .init = init, + .extra_init = extra_init, + .set_geometry = set_geometry, + .set_timing = set_timing, + .get_timing = get_timing, + .exit = exit, + .begin = begin, + .end = end, + .clear_bch = clear_bch, + .is_ready = is_ready, + .send_command = send_command, + .send_data = send_data, + .read_data = read_data, + .send_page = send_page, + .read_page = read_page, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c new file mode 100644 index 000000000000..32bc08160987 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c @@ -0,0 +1,1889 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include "gpmi-nfc.h" +#include "linux/slab.h" + +static int enable_gpmi_nand = { 0 }; + +/* + * This structure contains the "safe" GPMI timing that should succeed with any + * NAND Flash device (although, with less-than-optimal performance). + */ + +static struct gpmi_nfc_timing safe_timing = { + .data_setup_in_ns = 80, + .data_hold_in_ns = 60, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, +}; + +/* + * This array has a pointer to every NFC HAL structure. The probing process will + * find and install the one that matches the version given by the platform. + */ + +static struct nfc_hal *(nfc_hals[]) = { + /* i.mx23 */ + &gpmi_nfc_hal_v0, + /* i.mx28 */ + &gpmi_nfc_hal_v1, + /* i.mx50 */ + &gpmi_nfc_hal_v2, +}; + +/* + * This array has a pointer to every Boot ROM Helper structure. The probing + * process will find and install the one that matches the version given by the + * platform. + */ + +static struct boot_rom_helper *(boot_rom_helpers[]) = { + &gpmi_nfc_boot_rom_helper_v0, + &gpmi_nfc_boot_rom_helper_v1, +}; + +/** + * show_device_report() - Contains a shell script that creates a handy report. + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_report(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + static const char *script = + "GPMISysDirectory=/sys/bus/platform/devices/gpmi-nfc.0\n" + "\n" + "NodeList='\n" + "physical_geometry\n" + "nfc_info\n" + "nfc_geometry\n" + "timing\n" + "timing_diagram\n" + "rom_geometry\n" + "mtd_nand_info\n" + "mtd_info\n" + "'\n" + "\n" + "cd ${GPMISysDirectory}\n" + "\n" + "printf '\\n'\n" + "\n" + "for NodeName in ${NodeList}\n" + "do\n" + "\n" + " printf '--------------------------------------------\\n'\n" + " printf '%s\\n' ${NodeName}\n" + " printf '--------------------------------------------\\n'\n" + " printf '\\n'\n" + "\n" + " cat ${NodeName}\n" + "\n" + " printf '\\n'\n" + "\n" + "done\n" + ; + + return sprintf(buf, "%s", script); + +} + +/** + * show_device_numchips() - Shows the number of physical chips. + * + * This node is made obsolete by the physical_geometry node, but we keep it for + * backward compatibility (especially for kobs). + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_numchips(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct nand_chip *nand = &this->mil.nand; + + return sprintf(buf, "%d\n", nand->numchips); +} + +/** + * show_device_nfc_info() - Shows the NFC-specific information. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_nfc_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct nfc_hal *nfc = this->nfc; + + return sprintf(buf, + "Version : %u\n" + "Description : %s\n" + "Max Chip Count : %u\n" + "Max Data Setup Cycles : 0x%x\n" + "Internal Data Setup in ns : %u\n" + "Max Sample Delay Factor : 0x%x\n" + "Max DLL Clock Period in ns: %u\n" + "Max DLL Delay in ns : %u\n" + , + nfc->version, + nfc->description, + nfc->max_chip_count, + nfc->max_data_setup_cycles, + nfc->internal_data_setup_in_ns, + nfc->max_sample_delay_factor, + nfc->max_dll_clock_period_in_ns, + nfc->max_dll_delay_in_ns + ); + +} + +/** + * show_device_nfc_geometry() - Shows the NFC view of the device geometry. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_nfc_geometry(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct nfc_geometry *nfc = &this->nfc_geometry; + + return sprintf(buf, + "ECC Algorithm : %s\n" + "ECC Strength : %u\n" + "Page Size in Bytes : %u\n" + "Metadata Size in Bytes : %u\n" + "ECC Chunk Size in Bytes: %u\n" + "ECC Chunk Count : %u\n" + "Payload Size in Bytes : %u\n" + "Auxiliary Size in Bytes: %u\n" + "Auxiliary Status Offset: %u\n" + "Block Mark Byte Offset : %u\n" + "Block Mark Bit Offset : %u\n" + , + nfc->ecc_algorithm, + nfc->ecc_strength, + nfc->page_size_in_bytes, + nfc->metadata_size_in_bytes, + nfc->ecc_chunk_size_in_bytes, + nfc->ecc_chunk_count, + nfc->payload_size_in_bytes, + nfc->auxiliary_size_in_bytes, + nfc->auxiliary_status_offset, + nfc->block_mark_byte_offset, + nfc->block_mark_bit_offset + ); + +} + +/** + * show_device_rom_geometry() - Shows the Boot ROM Helper's geometry. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_rom_geometry(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct boot_rom_geometry *rom = &this->rom_geometry; + + return sprintf(buf, + "Boot Area Count : %u\n" + "Boot Area Size in Bytes : %u\n" + "Stride Size in Pages : %u\n" + "Seach Area Stride Exponent: %u\n" + , + rom->boot_area_count, + rom->boot_area_size_in_bytes, + rom->stride_size_in_pages, + rom->search_area_stride_exponent + ); + +} + +/** + * show_device_mtd_nand_info() - Shows the device's MTD NAND-specific info. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_mtd_nand_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int o = 0; + unsigned int i; + unsigned int j; + static const unsigned int columns = 8; + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + struct nand_chip *nand = &mil->nand; + + o += sprintf(buf + o, + "Options : 0x%08x\n" + "Chip Count : %u\n" + "Chip Size in Bytes : %llu\n" + "Minimum Writable Size in Bytes: %u\n" + "Page Shift : %u\n" + "Page Mask : 0x%x\n" + "Block Shift : %u\n" + "BBT Block Shift : %u\n" + "Chip Shift : %u\n" + "Block Mark Offset : %u\n" + "Cached Page Number : %d\n" + , + nand->options, + nand->numchips, + nand->chipsize, + nand->subpagesize, + nand->page_shift, + nand->pagemask, + nand->phys_erase_shift, + nand->bbt_erase_shift, + nand->chip_shift, + nand->badblockpos, + nand->pagebuf + ); + + o += sprintf(buf + o, + "ECC Byte Count : %u\n" + , + nand->ecc.layout->eccbytes + ); + + /* Loop over rows. */ + + for (i = 0; (i * columns) < nand->ecc.layout->eccbytes; i++) { + + /* Loop over columns within rows. */ + + for (j = 0; j < columns; j++) { + + if (((i * columns) + j) >= nand->ecc.layout->eccbytes) + break; + + o += sprintf(buf + o, " %3u", + nand->ecc.layout->eccpos[(i * columns) + j]); + + } + + o += sprintf(buf + o, "\n"); + + } + + o += sprintf(buf + o, + "OOB Available Bytes : %u\n" + , + nand->ecc.layout->oobavail + ); + + j = 0; + + for (i = 0; j < nand->ecc.layout->oobavail; i++) { + + j += nand->ecc.layout->oobfree[i].length; + + o += sprintf(buf + o, + " [%3u, %2u]\n" + , + nand->ecc.layout->oobfree[i].offset, + nand->ecc.layout->oobfree[i].length + ); + + } + + return o; + +} + +/** + * show_device_mtd_info() - Shows the device's MTD-specific information. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_mtd_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int o = 0; + unsigned int i; + unsigned int j; + static const unsigned int columns = 8; + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + + o += sprintf(buf + o, + "Name : %s\n" + "Type : %u\n" + "Flags : 0x%08x\n" + "Size in Bytes : %llu\n" + "Erase Region Count : %d\n" + "Erase Size in Bytes: %u\n" + "Write Size in Bytes: %u\n" + "OOB Size in Bytes : %u\n" + "Errors Corrected : %u\n" + "Failed Reads : %u\n" + "Bad Block Count : %u\n" + "BBT Block Count : %u\n" + , + mtd->name, + mtd->type, + mtd->flags, + mtd->size, + mtd->numeraseregions, + mtd->erasesize, + mtd->writesize, + mtd->oobsize, + mtd->ecc_stats.corrected, + mtd->ecc_stats.failed, + mtd->ecc_stats.badblocks, + mtd->ecc_stats.bbtblocks + ); + + o += sprintf(buf + o, + "ECC Byte Count : %u\n" + , + mtd->ecclayout->eccbytes + ); + + /* Loop over rows. */ + + for (i = 0; (i * columns) < mtd->ecclayout->eccbytes; i++) { + + /* Loop over columns within rows. */ + + for (j = 0; j < columns; j++) { + + if (((i * columns) + j) >= mtd->ecclayout->eccbytes) + break; + + o += sprintf(buf + o, " %3u", + mtd->ecclayout->eccpos[(i * columns) + j]); + + } + + o += sprintf(buf + o, "\n"); + + } + + o += sprintf(buf + o, + "OOB Available Bytes: %u\n" + , + mtd->ecclayout->oobavail + ); + + j = 0; + + for (i = 0; j < mtd->ecclayout->oobavail; i++) { + + j += mtd->ecclayout->oobfree[i].length; + + o += sprintf(buf + o, + " [%3u, %2u]\n" + , + mtd->ecclayout->oobfree[i].offset, + mtd->ecclayout->oobfree[i].length + ); + + } + + return o; + +} + +/** + * show_device_timing_diagram() - Shows a timing diagram. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_timing_diagram(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_timing timing = nfc->timing; + struct gpmi_nfc_hardware_timing hardware_timing; + unsigned long clock_frequency_in_hz; + unsigned long clock_period_in_ns; + unsigned int data_setup_in_ns; + unsigned int dll_delay_shift; + unsigned int sample_delay_in_ns; + unsigned int tDS_in_ns; + unsigned int tOPEN_in_ns; + unsigned int tCLOSE_in_ns; + unsigned int tEYE_in_ns; + unsigned int tDELAY_in_ns; + unsigned int tDS; + unsigned int tOPEN; + unsigned int tCLOSE; + unsigned int tEYE; + unsigned int tDELAY; + const unsigned int diagram_width_in_chars = 55; + unsigned int diagram_width_in_ns; + int o = 0; + unsigned int i; + + /* + * If there are any timing characteristics we need, but don't know, we + * pretend they're zero. + */ + + if (timing.tREA_in_ns < 0) + timing.tREA_in_ns = 0; + + if (timing.tRHOH_in_ns < 0) + timing.tRHOH_in_ns = 0; + + /* Get information about the current/last I/O transaction. */ + + nfc->get_timing(this, &clock_frequency_in_hz, &hardware_timing); + + clock_period_in_ns = 1000000000 / clock_frequency_in_hz; + + /* Compute basic timing facts. */ + + data_setup_in_ns = + hardware_timing.data_setup_in_cycles * clock_period_in_ns; + + /* Compute data sample delay facts. */ + + dll_delay_shift = 3; + + if (hardware_timing.use_half_periods) + dll_delay_shift++; + + sample_delay_in_ns = + (hardware_timing.sample_delay_factor * clock_period_in_ns) >> + dll_delay_shift; + + /* Compute the basic metrics in the diagram, in nanoseconds. */ + + tDS_in_ns = data_setup_in_ns; + tOPEN_in_ns = pdata->max_prop_delay_in_ns + timing.tREA_in_ns; + tCLOSE_in_ns = pdata->min_prop_delay_in_ns + timing.tRHOH_in_ns; + tEYE_in_ns = tDS_in_ns + tCLOSE_in_ns - tOPEN_in_ns; + tDELAY_in_ns = sample_delay_in_ns; + + /* + * We need to translate nanosecond timings into character widths in the + * diagram. The first step is to discover how "wide" the diagram is in + * nanoseconds. That depends on which happens latest: the sample point + * or the close of the eye. + */ + + if (tCLOSE_in_ns >= tDELAY_in_ns) + diagram_width_in_ns = tDS_in_ns + tCLOSE_in_ns; + else + diagram_width_in_ns = tDS_in_ns + tDELAY_in_ns; + + /* Convert the metrics that appear in the diagram. */ + + tDS = (tDS_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + tOPEN = (tOPEN_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + tCLOSE = (tCLOSE_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + tEYE = (tEYE_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + tDELAY = (tDELAY_in_ns * diagram_width_in_chars) / diagram_width_in_ns; + + /* + * Show the results. + * + * This code is really ugly, but it draws a pretty picture :) + */ + + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "Sample ______"); + for (i = 0; i < tDS; i++) + o += sprintf(buf + o, "_"); + if (tDELAY > 0) + for (i = 0; i < (tDELAY - 1); i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "|"); + for (i = 0; i < (diagram_width_in_chars - (tDS + tDELAY)); i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "Strobe "); + for (i = 0; i < tDS; i++) + o += sprintf(buf + o, " "); + o += sprintf(buf + o, "|"); + if (tDELAY > 1) { + for (i = 2; i < tDELAY; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, " tDELAY\n"); + + + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " tDS "); + o += sprintf(buf + o, "|"); + if (tDS > 1) { + for (i = 2; i < tDS; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " ______"); + for (i = 0; i < tDS; i++) + o += sprintf(buf + o, " "); + for (i = 0; i < (diagram_width_in_chars - tDS); i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "RDN "); + if (tDS > 0) { + if (tDS == 1) + o += sprintf(buf + o, "V"); + else { + o += sprintf(buf + o, "\\"); + for (i = 2; i < tDS; i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "/"); + } + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " tOPEN "); + o += sprintf(buf + o, "|"); + if (tOPEN > 1) { + for (i = 2; i < tOPEN; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " "); + for (i = 0; i < tDS; i++) + o += sprintf(buf + o, " "); + o += sprintf(buf + o, "|"); + if (tCLOSE > 1) { + for (i = 2; i < tCLOSE; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, " tCLOSE\n"); + + + o += sprintf(buf + o, " "); + for (i = 0; i < tOPEN; i++) + o += sprintf(buf + o, " "); + if (tEYE > 2) { + o += sprintf(buf + o, " "); + for (i = 2; i < tEYE; i++) + o += sprintf(buf + o, "_"); + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, "Data ______"); + for (i = 0; i < tOPEN; i++) + o += sprintf(buf + o, "_"); + if (tEYE > 0) { + if (tEYE == 1) + o += sprintf(buf + o, "|"); + else { + o += sprintf(buf + o, "/"); + for (i = 2; i < tEYE; i++) + o += sprintf(buf + o, " "); + o += sprintf(buf + o, "\\"); + } + } + for (i = 0; i < (diagram_width_in_chars - (tOPEN + tEYE)); i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " "); + for (i = 0; i < tOPEN; i++) + o += sprintf(buf + o, " "); + if (tEYE > 0) { + if (tEYE == 1) + o += sprintf(buf + o, "|"); + else { + o += sprintf(buf + o, "\\"); + for (i = 2; i < tEYE; i++) + o += sprintf(buf + o, "_"); + o += sprintf(buf + o, "/"); + } + } + o += sprintf(buf + o, "\n"); + + + o += sprintf(buf + o, " "); + for (i = 0; i < tOPEN; i++) + o += sprintf(buf + o, " "); + o += sprintf(buf + o, "|"); + if (tEYE > 1) { + for (i = 2; i < tEYE; i++) + o += sprintf(buf + o, "-"); + o += sprintf(buf + o, "|"); + } + o += sprintf(buf + o, " tEYE\n"); + + + o += sprintf(buf + o, "\n"); + o += sprintf(buf + o, "tDS : %u ns\n", tDS_in_ns); + o += sprintf(buf + o, "tOPEN : %u ns\n", tOPEN_in_ns); + o += sprintf(buf + o, "tCLOSE: %u ns\n", tCLOSE_in_ns); + o += sprintf(buf + o, "tEYE : %u ns\n", tEYE_in_ns); + o += sprintf(buf + o, "tDELAY: %u ns\n", tDELAY_in_ns); + o += sprintf(buf + o, "\n"); + + + return o; + +} + +/** + * store_device_invalidate_page_cache() - Invalidates the device's page cache. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_invalidate_page_cache(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + + /* Invalidate the page cache. */ + + this->mil.nand.pagebuf = -1; + + /* Return success. */ + + return size; + +} + +/** + * store_device_mark_block_bad() - Marks a block as bad. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_mark_block_bad(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + unsigned long block_number; + loff_t byte_address; + int error; + + /* Look for nonsense. */ + + if (!size) + return -EINVAL; + + /* Try to understand the block number. */ + + if (strict_strtoul(buf, 0, &block_number)) + return -EINVAL; + + /* Compute the byte address of this block. */ + + byte_address = block_number << nand->phys_erase_shift; + + /* Attempt to mark the block bad. */ + + error = mtd->block_markbad(mtd, byte_address); + + if (error) + return error; + + /* Return success. */ + + return size; + +} + +/** + * show_device_ignorebad() - Shows the value of the 'ignorebad' flag. + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_ignorebad(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + + return sprintf(buf, "%d\n", mil->ignore_bad_block_marks); +} + +/** + * store_device_ignorebad() - Sets the value of the 'ignorebad' flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_ignorebad(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + const char *p = buf; + unsigned long v; + + /* Try to make sense of what arrived from user space. */ + + if (strict_strtoul(p, 0, &v) < 0) + return size; + + if (v > 0) + v = 1; + + /* Only do something if the value is changing. */ + + if (v != mil->ignore_bad_block_marks) { + + if (v) { + + /* + * If control arrives here, we want to begin ignoring + * bad block marks. Reach into the NAND Flash MTD data + * structures and set the in-memory BBT pointer to NULL. + * This will cause the NAND Flash MTD code to believe + * that it never created a BBT and force it to call our + * block_bad function. + * + * See mil_block_bad for more details. + */ + + mil->saved_bbt = mil->nand.bbt; + mil->nand.bbt = 0; + + } else { + + /* + * If control arrives here, we want to stop ignoring + * bad block marks. Restore the NAND Flash MTD's pointer + * to its in-memory BBT. + */ + + mil->nand.bbt = mil->saved_bbt; + + } + + mil->ignore_bad_block_marks = v; + + } + + return size; + +} + +/** + * show_device_inject_ecc_error() - Shows the device's error injection flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_inject_ecc_error(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + + return sprintf(buf, "%d\n", mil->inject_ecc_error); + +} + +/** + * store_device_inject_ecc_error() - Sets the device's error injection flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_inject_ecc_error(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct mil *mil = &this->mil; + long new_inject_ecc_error; + + /* Look for nonsense. */ + + if (!size) + return -EINVAL; + + /* Try to understand the ECC error count. */ + + if (strict_strtol(buf, 0, &new_inject_ecc_error)) + return -EINVAL; + + /* Store the value. */ + + mil->inject_ecc_error = new_inject_ecc_error; + + /* Return success. */ + + return size; + +} + +/** + * show_device_timing_help() - Show help for setting timing. + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_timing_help(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + static const char *help = + ",,
,," + ",,\n"; + + return sprintf(buf, "%s", help); + +} + +/** + * show_device_timing() - Shows the current timing. + * + * @d: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_timing(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct nfc_hal *nfc = this->nfc; + struct gpmi_nfc_timing *recorded = &nfc->timing; + unsigned long clock_frequency_in_hz; + unsigned long clock_period_in_ns; + struct gpmi_nfc_hardware_timing hardware; + unsigned int effective_data_setup_in_ns; + unsigned int effective_data_hold_in_ns; + unsigned int effective_address_setup_in_ns; + unsigned int dll_delay_shift; + unsigned int effective_sample_delay_in_ns; + + /* Get information about the current/last I/O transaction. */ + + nfc->get_timing(this, &clock_frequency_in_hz, &hardware); + + clock_period_in_ns = 1000000000 / clock_frequency_in_hz; + + /* Compute basic timing facts. */ + + effective_data_setup_in_ns = + hardware.data_setup_in_cycles * clock_period_in_ns; + effective_data_hold_in_ns = + hardware.data_hold_in_cycles * clock_period_in_ns; + effective_address_setup_in_ns = + hardware.address_setup_in_cycles * clock_period_in_ns; + + /* Compute data sample delay facts. */ + + dll_delay_shift = 3; + + if (hardware.use_half_periods) + dll_delay_shift++; + + effective_sample_delay_in_ns = + (hardware.sample_delay_factor * clock_period_in_ns) >> + dll_delay_shift; + + /* Show the results. */ + + return sprintf(buf, + "Minimum Propagation Delay in ns : %u\n" + "Maximum Propagation Delay in ns : %u\n" + "Clock Frequency in Hz : %lu\n" + "Clock Period in ns : %lu\n" + "Recorded Data Setup in ns : %d\n" + "Hardware Data Setup in cycles : %u\n" + "Effective Data Setup in ns : %u\n" + "Recorded Data Hold in ns : %d\n" + "Hardware Data Hold in cycles : %u\n" + "Effective Data Hold in ns : %u\n" + "Recorded Address Setup in ns : %d\n" + "Hardware Address Setup in cycles: %u\n" + "Effective Address Setup in ns : %u\n" + "Using Half Period : %s\n" + "Recorded Sample Delay in ns : %d\n" + "Hardware Sample Delay Factor : %u\n" + "Effective Sample Delay in ns : %u\n" + "Recorded tREA in ns : %d\n" + "Recorded tRLOH in ns : %d\n" + "Recorded tRHOH in ns : %d\n" + , + pdata->min_prop_delay_in_ns, + pdata->max_prop_delay_in_ns, + clock_frequency_in_hz, + clock_period_in_ns, + recorded->data_setup_in_ns, + hardware .data_setup_in_cycles, + effective_data_setup_in_ns, + recorded->data_hold_in_ns, + hardware .data_hold_in_cycles, + effective_data_hold_in_ns, + recorded->address_setup_in_ns, + hardware .address_setup_in_cycles, + effective_address_setup_in_ns, + hardware .use_half_periods ? "Yes" : "No", + recorded->gpmi_sample_delay_in_ns, + hardware .sample_delay_factor, + effective_sample_delay_in_ns, + recorded->tREA_in_ns, + recorded->tRLOH_in_ns, + recorded->tRHOH_in_ns); + +} + +/** + * store_device_timing() - Sets the current timing. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_timing(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpmi_nfc_data *this = dev_get_drvdata(dev); + struct nfc_hal *nfc = this->nfc; + const char *p = buf; + const char *q; + char tmps[20]; + long t; + struct gpmi_nfc_timing new; + + int8_t *field_pointers[] = { + &new.data_setup_in_ns, + &new.data_hold_in_ns, + &new.address_setup_in_ns, + &new.gpmi_sample_delay_in_ns, + &new.tREA_in_ns, + &new.tRLOH_in_ns, + &new.tRHOH_in_ns, + NULL, + }; + + int8_t **field_pointer = field_pointers; + + /* + * Loop over comma-separated timing values in the incoming buffer, + * assigning them to fields in the timing structure as we go along. + */ + + while (*field_pointer != NULL) { + + /* Clear out the temporary buffer. */ + + memset(tmps, 0, sizeof(tmps)); + + /* Copy the timing value into the temporary buffer. */ + + q = strchr(p, ','); + if (q) + strncpy(tmps, p, min_t(int, sizeof(tmps) - 1, q - p)); + else + strncpy(tmps, p, sizeof(tmps) - 1); + + /* Attempt to convert the current timing value. */ + + if (strict_strtol(tmps, 0, &t) < 0) + return -EINVAL; + + if ((t > 127) || (t < -128)) + return -EINVAL; + + /* Assign this value to the current field. */ + + **field_pointer = (int8_t) t; + field_pointer++; + + /* Check if we ran out of input too soon. */ + + if (!q && *field_pointer) + return -EINVAL; + + /* Move past the comma to the next timing value. */ + + p = q + 1; + + } + + /* Hand over the timing to the NFC. */ + + nfc->set_timing(this, &new); + + /* Return success. */ + + return size; + +} + +/* Device attributes that appear in sysfs. */ + +static DEVICE_ATTR(report , 0555, show_device_report , 0); +static DEVICE_ATTR(numchips , 0444, show_device_numchips , 0); +static DEVICE_ATTR(nfc_info , 0444, show_device_nfc_info , 0); +static DEVICE_ATTR(nfc_geometry , 0444, show_device_nfc_geometry , 0); +static DEVICE_ATTR(rom_geometry , 0444, show_device_rom_geometry , 0); +static DEVICE_ATTR(mtd_nand_info , 0444, show_device_mtd_nand_info , 0); +static DEVICE_ATTR(mtd_info , 0444, show_device_mtd_info , 0); +static DEVICE_ATTR(timing_diagram , 0444, show_device_timing_diagram , 0); +static DEVICE_ATTR(timing_help , 0444, show_device_timing_help , 0); + +static DEVICE_ATTR(invalidate_page_cache, 0644, + 0, store_device_invalidate_page_cache); + +static DEVICE_ATTR(mark_block_bad, 0200, + 0, store_device_mark_block_bad); + +static DEVICE_ATTR(ignorebad, 0644, + show_device_ignorebad, store_device_ignorebad); + +static DEVICE_ATTR(inject_ecc_error, 0644, + show_device_inject_ecc_error, store_device_inject_ecc_error); + +static DEVICE_ATTR(timing, 0644, + show_device_timing, store_device_timing); + +static struct device_attribute *device_attributes[] = { + &dev_attr_report, + &dev_attr_numchips, + &dev_attr_nfc_info, + &dev_attr_nfc_geometry, + &dev_attr_rom_geometry, + &dev_attr_mtd_nand_info, + &dev_attr_mtd_info, + &dev_attr_invalidate_page_cache, + &dev_attr_mark_block_bad, + &dev_attr_ignorebad, + &dev_attr_inject_ecc_error, + &dev_attr_timing, + &dev_attr_timing_help, + &dev_attr_timing_diagram, +}; + +/** + * validate_the_platform() - Validates information about the platform. + * + * @pdev: A pointer to the platform device data structure. + */ +static int validate_the_platform(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gpmi_nfc_platform_data *pdata = pdev->dev.platform_data; + + /* Validate the clock name. */ + + if (!pdata->clock_name) { + dev_err(dev, "No clock name\n"); + return -ENXIO; + } + + /* Validate the partitions. */ + + if ((pdata->partitions && (!pdata->partition_count)) || + (!pdata->partitions && (pdata->partition_count))) { + dev_err(dev, "Bad partition data\n"); + return -ENXIO; + } + + /* Return success */ + + return 0; + +} + +/** + * acquire_register_block() - Tries to acquire and map a register block. + * + * @this: Per-device data. + * @resource_name: The name of the resource. + * @reg_block_base: A pointer to a variable that will receive the address of + * the mapped register block. + */ +static int acquire_register_block(struct gpmi_nfc_data *this, + const char *resource_name, void **reg_block_base) +{ + struct platform_device *pdev = this->pdev; + struct device *dev = this->dev; + void *p; + struct resource *r; + + /* Attempt to get information about the given resource. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name); + + if (!r) { + dev_err(dev, "Can't get resource information for '%s'\n", + resource_name); + return -ENXIO; + } + + /* Attempt to remap the register block. */ + + p = ioremap(r->start, r->end - r->start + 1); + + if (!p) { + dev_err(dev, "Can't remap %s\n", resource_name); + return -EIO; + } + + /* If control arrives here, everything went fine. */ + + *reg_block_base = p; + + return 0; + +} + +/** + * release_register_block() - Releases a register block. + * + * @this: Per-device data. + * @reg_block_base: A pointer to the mapped register block. + */ +static void release_register_block(struct gpmi_nfc_data *this, + void *reg_block_base) +{ + iounmap(reg_block_base); +} + +/** + * acquire_interrupt() - Tries to acquire an interrupt. + * + * @this: Per-device data. + * @resource_name: The name of the resource. + * @interrupt_handler: A pointer to the function that will handle interrupts + * from this interrupt number. + * @lno: A pointer to a variable that will receive the acquired + * interrupt number(low part). + * @hno: A pointer to a variable that will receive the acquired + * interrupt number(high part). + */ +static int acquire_interrupt( + struct gpmi_nfc_data *this, const char *resource_name, + irq_handler_t interrupt_handler, int *lno, int *hno) +{ + struct platform_device *pdev = this->pdev; + struct device *dev = this->dev; + int error = 0; + struct resource *r; + int i; + + /* Attempt to get information about the given resource. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, resource_name); + + if (!r) { + dev_err(dev, "Can't get resource information for '%s'\n", + resource_name); + return -ENXIO; + } + + /* Attempt to own the interrupt. */ + for (i = r->start; i <= r->end; i++) { + error = request_irq(i, interrupt_handler, 0, + resource_name, this); + + if (error) { + dev_err(dev, "Can't own %s\n", resource_name); + + /* Free all the irq's we've already acquired. */ + + while ((i - r->start) >= 0) { + free_irq(i, this); + i--; + } + + return -EIO; + } + } + + /* If control arrives here, everything went fine. */ + + *lno = r->start; + *hno = r->end; + + return 0; + +} + +/** + * release_interrupt() - Releases an interrupt. + * + * @this: Per-device data. + * @interrupt_number: The interrupt number. + */ +static void release_interrupt(struct gpmi_nfc_data *this, + int low_interrupt_number, int high_interrupt_number) +{ + int i; + for (i = low_interrupt_number; i <= high_interrupt_number; i++) + free_irq(i, this); +} + +/** + * acquire_dma_channels() - Tries to acquire DMA channels. + * + * @this: Per-device data. + * @resource_name: The name of the resource. + * @low_channel: A pointer to a variable that will receive the acquired + * low DMA channel number. + * @high_channel: A pointer to a variable that will receive the acquired + * high DMA channel number. + */ +static int acquire_dma_channels( + struct gpmi_nfc_data *this, const char *resource_name, + unsigned *low_channel, unsigned *high_channel) +{ + struct platform_device *pdev = this->pdev; + struct device *dev = this->dev; + int error = 0; + struct resource *r; + unsigned int dma_channel; + + /* Attempt to get information about the given resource. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_DMA, resource_name); + + if (!r) { + dev_err(dev, "Can't get resource information for '%s'\n", + resource_name); + return -ENXIO; + } + + /* Loop over DMA channels, attempting to own them. */ + + for (dma_channel = r->start; dma_channel <= r->end; dma_channel++) { + + /* Attempt to own the current channel. */ + + error = mxs_dma_request(dma_channel, dev, resource_name); + + /* Check if we successfully acquired the current channel. */ + + if (error) { + + dev_err(dev, "Can't acquire DMA channel %u\n", + dma_channel); + + /* Free all the channels we've already acquired. */ + + while (--dma_channel >= 0) + mxs_dma_release(dma_channel, dev); + + return error; + + } + + /* + * If control arrives here, we successfully acquired the + * current channel. Continue initializing it. + */ + + mxs_dma_reset(dma_channel); + mxs_dma_ack_irq(dma_channel); + + } + + /* If control arrives here, all went well. */ + + *low_channel = r->start; + *high_channel = r->end; + + return 0; + +} + +/** + * release_dma_channels() - Releases DMA channels. + * + * @this: Per-device data. + * @low_channel: The low DMA channel number. + * @high_channel: The high DMA channel number. + */ +static void release_dma_channels(struct gpmi_nfc_data *this, + unsigned low_channel, unsigned high_channel) +{ + struct device *dev = this->dev; + unsigned int i; + + for (i = low_channel; i <= high_channel; i++) + mxs_dma_release(i, dev); +} + +/** + * acquire_clock() - Tries to acquire a clock. + * + * @this: Per-device data. + * @resource_name: The name of the clock. + * @high_channel: A pointer to a variable that will receive the acquired + * clock address. + */ +static int acquire_clock(struct gpmi_nfc_data *this, + const char *clock_name, struct clk **clock) +{ + struct device *dev = this->dev; + int error = 0; + struct clk *c; + + /* Try to get the clock. */ + + c = clk_get(dev, clock_name); + + if (IS_ERR(c)) { + error = PTR_ERR(c); + dev_err(dev, "Can't own clock %s\n", clock_name); + return error; + } + + /* If control arrives here, everything went fine. */ + + *clock = c; + + return 0; + +} + +/** + * release_clock() - Releases a clock. + * + * @this: Per-device data. + * @clock: A pointer to the clock structure. + */ +static void release_clock(struct gpmi_nfc_data *this, struct clk *clock) +{ + clk_disable(clock); + clk_put(clock); +} + +/** + * acquire_resources() - Tries to acquire resources. + * + * @this: Per-device data. + */ +static int acquire_resources(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct resources *resources = &this->resources; + int error = 0; + + /* Attempt to acquire the GPMI register block. */ + + error = acquire_register_block(this, + GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, &(resources->gpmi_regs)); + + if (error) + goto exit_gpmi_regs; + + /* Attempt to acquire the BCH register block. */ + + error = acquire_register_block(this, + GPMI_NFC_BCH_REGS_ADDR_RES_NAME, &(resources->bch_regs)); + + if (error) + goto exit_bch_regs; + + /* Attempt to acquire the BCH interrupt. */ + + error = acquire_interrupt(this, + GPMI_NFC_BCH_INTERRUPT_RES_NAME, + gpmi_nfc_bch_isr, + &(resources->bch_low_interrupt), + &(resources->bch_high_interrupt)); + + if (error) + goto exit_bch_interrupt; + + /* Attempt to acquire the DMA channels. */ + + error = acquire_dma_channels(this, + GPMI_NFC_DMA_CHANNELS_RES_NAME, + &(resources->dma_low_channel), &(resources->dma_high_channel)); + + if (error) + goto exit_dma_channels; + + /* Attempt to acquire the DMA interrupt. */ + + error = acquire_interrupt(this, + GPMI_NFC_DMA_INTERRUPT_RES_NAME, + gpmi_nfc_dma_isr, + &(resources->dma_low_interrupt), + &(resources->dma_high_interrupt)); + + if (error) + goto exit_dma_interrupt; + + /* Attempt to acquire our clock. */ + + error = acquire_clock(this, pdata->clock_name, &(resources->clock)); + + if (error) + goto exit_clock; + + /* If control arrives here, all went well. */ + + return 0; + + /* Control arrives here if something went wrong. */ + +exit_clock: + release_interrupt(this, + resources->dma_low_interrupt, resources->dma_high_interrupt); +exit_dma_interrupt: + release_dma_channels(this, + resources->dma_low_channel, resources->dma_high_channel); +exit_dma_channels: + release_interrupt(this, + resources->bch_low_interrupt, resources->bch_high_interrupt); +exit_bch_interrupt: + release_register_block(this, resources->bch_regs); +exit_bch_regs: + release_register_block(this, resources->gpmi_regs); +exit_gpmi_regs: + + return error; + +} + +/** + * release_resources() - Releases resources. + * + * @this: Per-device data. + */ +static void release_resources(struct gpmi_nfc_data *this) +{ + struct resources *resources = &this->resources; + + release_clock(this, resources->clock); + release_register_block(this, resources->gpmi_regs); + release_register_block(this, resources->bch_regs); + release_interrupt(this, + resources->bch_low_interrupt, resources->bch_low_interrupt); + release_dma_channels(this, + resources->dma_low_channel, resources->dma_high_channel); + release_interrupt(this, + resources->dma_low_interrupt, resources->dma_high_interrupt); +} + +/** + * set_up_nfc_hal() - Sets up the NFC HAL. + * + * @this: Per-device data. + */ +static int set_up_nfc_hal(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct device *dev = this->dev; + struct nfc_hal *nfc; + int error = 0; + unsigned int i; + + /* Attempt to find an NFC HAL that matches the given version. */ + + for (i = 0; i < ARRAY_SIZE(nfc_hals); i++) { + + nfc = nfc_hals[i]; + + if (nfc->version == pdata->nfc_version) { + this->nfc = nfc; + break; + } + + } + + /* Check if we found a HAL. */ + + if (i >= ARRAY_SIZE(nfc_hals)) { + dev_err(dev, "Unkown NFC version %u\n", pdata->nfc_version); + return -ENXIO; + } + + pr_info("NFC: Version %u, %s\n", nfc->version, nfc->description); + + /* + * Check if we can handle the number of chips called for by the platform + * data. + */ + + if (pdata->max_chip_count > nfc->max_chip_count) { + dev_err(dev, "Platform data calls for %u chips " + "but NFC supports a max of %u.\n", + pdata->max_chip_count, nfc->max_chip_count); + return -ENXIO; + } + + /* Initialize the NFC HAL. */ + + error = nfc->init(this); + + if (error) + return error; + + /* Set up safe timing. */ + + nfc->set_timing(this, &safe_timing); + + /* + * If control arrives here, all is well. + */ + + return 0; + +} + +/** + * set_up_boot_rom_helper() - Sets up the Boot ROM Helper. + * + * @this: Per-device data. + */ +static int set_up_boot_rom_helper(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct device *dev = this->dev; + unsigned int i; + struct boot_rom_helper *rom; + + /* Attempt to find a Boot ROM Helper that matches the given version. */ + + for (i = 0; i < ARRAY_SIZE(boot_rom_helpers); i++) { + + rom = boot_rom_helpers[i]; + + if (rom->version == pdata->boot_rom_version) { + this->rom = rom; + break; + } + + } + + /* Check if we found a Boot ROM Helper. */ + + if (i >= ARRAY_SIZE(boot_rom_helpers)) { + dev_err(dev, "Unkown Boot ROM version %u\n", + pdata->boot_rom_version); + return -ENXIO; + } + + pr_info("Boot ROM: Version %u, %s\n", rom->version, rom->description); + + /* + * If control arrives here, all is well. + */ + + return 0; + +} + +/** + * manage_sysfs_files() - Creates/removes sysfs files for this device. + * + * @this: Per-device data. + */ +static void manage_sysfs_files(struct gpmi_nfc_data *this, int create) +{ + struct device *dev = this->dev; + int error; + unsigned int i; + struct device_attribute **attr; + + for (i = 0, attr = device_attributes; + i < ARRAY_SIZE(device_attributes); i++, attr++) { + + if (create) { + error = device_create_file(dev, *attr); + if (error) { + while (--attr >= device_attributes) + device_remove_file(dev, *attr); + return; + } + } else { + device_remove_file(dev, *attr); + } + + } + +} + +/** + * gpmi_nfc_probe() - Probes for a device and, if possible, takes ownership. + * + * @pdev: A pointer to the platform device data structure. + */ +static int gpmi_nfc_probe(struct platform_device *pdev) +{ + int error = 0; + struct device *dev = &pdev->dev; + struct gpmi_nfc_platform_data *pdata = pdev->dev.platform_data; + struct gpmi_nfc_data *this = 0; + + /* Validate the platform device data. */ + + error = validate_the_platform(pdev); + + if (error) + goto exit_validate_platform; + + /* Allocate memory for the per-device data. */ + + this = kzalloc(sizeof(*this), GFP_KERNEL); + + if (!this) { + dev_err(dev, "Failed to allocate per-device memory\n"); + error = -ENOMEM; + goto exit_allocate_this; + } + + /* Set up our data structures. */ + + platform_set_drvdata(pdev, this); + + this->pdev = pdev; + this->dev = &pdev->dev; + this->pdata = pdata; + + /* Acquire the resources we need. */ + + error = acquire_resources(this); + + if (error) + goto exit_acquire_resources; + + /* Set up the NFC. */ + + error = set_up_nfc_hal(this); + + if (error) + goto exit_nfc_init; + + /* Set up the platform. */ + + if (pdata->platform_init) + error = pdata->platform_init(pdata->max_chip_count); + + if (error) + goto exit_platform_init; + + /* Set up the Boot ROM Helper. */ + + error = set_up_boot_rom_helper(this); + + if (error) + goto exit_boot_rom_helper_init; + + /* Initialize the MTD Interface Layer. */ + + error = gpmi_nfc_mil_init(this); + + if (error) + goto exit_mil_init; + + /* Create sysfs entries for this device. */ + + manage_sysfs_files(this, true); + + /* Return success. */ + + return 0; + + /* Error return paths begin here. */ + +exit_mil_init: +exit_boot_rom_helper_init: + if (pdata->platform_exit) + pdata->platform_exit(pdata->max_chip_count); +exit_platform_init: + this->nfc->exit(this); +exit_nfc_init: + release_resources(this); +exit_acquire_resources: + platform_set_drvdata(pdev, NULL); + kfree(this); +exit_allocate_this: +exit_validate_platform: + return error; + +} + +/** + * gpmi_nfc_remove() - Dissociates this driver from the given device. + * + * @pdev: A pointer to the platform device data structure. + */ +static int __exit gpmi_nfc_remove(struct platform_device *pdev) +{ + struct gpmi_nfc_data *this = platform_get_drvdata(pdev); + struct gpmi_nfc_platform_data *pdata = this->pdata; + + manage_sysfs_files(this, false); + gpmi_nfc_mil_exit(this); + if (pdata->platform_exit) + pdata->platform_exit(pdata->max_chip_count); + this->nfc->exit(this); + release_resources(this); + platform_set_drvdata(pdev, NULL); + kfree(this); + + return 0; +} + +#ifdef CONFIG_PM + +/** + * gpmi_nfc_suspend() - Puts the NFC into a low power state. + * + * @pdev: A pointer to the platform device data structure. + * @state: The new power state. + */ +static int gpmi_nfc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +/** + * gpmi_nfc_resume() - Brings the NFC back from a low power state. + * + * @pdev: A pointer to the platform device data structure. + */ +static int gpmi_nfc_resume(struct platform_device *pdev) +{ + return 0; +} + +#else + +#define suspend NULL +#define resume NULL + +#endif /* CONFIG_PM */ + +/* + * This structure represents this driver to the platform management system. + */ +static struct platform_driver gpmi_nfc_driver = { + .driver = { + .name = GPMI_NFC_DRIVER_NAME, + }, + .probe = gpmi_nfc_probe, + .remove = __exit_p(gpmi_nfc_remove), + .suspend = gpmi_nfc_suspend, + .resume = gpmi_nfc_resume, +}; + +/** + * gpmi_nfc_init() - Initializes this module. + */ +static int __init gpmi_nfc_init(void) +{ + + pr_info("i.MX GPMI NFC\n"); + +#ifdef CONFIG_ARCH_MX50 + if (enable_gpmi_nand == 0) + return 0; +#endif + + /* Register this driver with the platform management system. */ + + if (platform_driver_register(&gpmi_nfc_driver) != 0) { + pr_err("i.MX GPMI NFC driver registration failed\n"); + return -ENODEV; + } + + /* Return success. */ + + return 0; + +} + +/** + * gpmi_nfc_exit() - Deactivates this module. + */ +static void __exit gpmi_nfc_exit(void) +{ + platform_driver_unregister(&gpmi_nfc_driver); +} + +static int __init gpmi_nand_setup(char *__unused) +{ + enable_gpmi_nand = 1; + return 1; +} +__setup("gpmi:nand", gpmi_nand_setup); + +module_init(gpmi_nfc_init); +module_exit(gpmi_nfc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c new file mode 100644 index 000000000000..efb0f93c234e --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-mil.c @@ -0,0 +1,1929 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include "gpmi-nfc.h" +#include "linux/slab.h" + +/* + * Indicates the driver should register the MTD that represents the entire + * medium, thus making it visible. + */ + +static int register_main_mtd; +module_param(register_main_mtd, int, 0400); + +/* + * Indicates the driver should attempt to perform DMA directly to/from buffers + * passed into this driver. This is true by default. If false, the driver will + * *always* copy incoming/outgoing data to/from its own DMA buffers. + */ + +static int map_io_buffers = true; +module_param(map_io_buffers, int, 0600); + +/* add our owner bbt descriptor */ +static uint8_t scan_ff_pattern[] = { 0xff }; +static struct nand_bbt_descr gpmi_bbt_descr = { + .options = 0, + .offs = 0, + .len = 1, + .pattern = scan_ff_pattern +}; + +/** + * mil_outgoing_buffer_dma_begin() - Begins DMA on an outgoing buffer. + * + * @this: Per-device data. + * @source: The source buffer. + * @length: The length of the data in the source buffer. + * @alt_virt: The virtual address of an alternate buffer which is ready to be + * used for DMA. + * @alt_phys: The physical address of an alternate buffer which is ready to be + * used for DMA. + * @alt_size: The size of the alternate buffer. + * @use_virt: A pointer to a variable that will receive the virtual address to + * use. + * @use_phys: A pointer to a variable that will receive the physical address to + * use. + */ +static int mil_outgoing_buffer_dma_begin(struct gpmi_nfc_data *this, + const void *source, unsigned length, + void *alt_virt, dma_addr_t alt_phys, unsigned alt_size, + const void **use_virt, dma_addr_t *use_phys) +{ + struct device *dev = this->dev; + dma_addr_t source_phys = ~0; + + /* + * If we can, we want to use the caller's buffer directly for DMA. Check + * if the system will let us map them. + */ + if (map_io_buffers && virt_addr_valid(source)) + source_phys = + dma_map_single(dev, + (void *) source, length, DMA_TO_DEVICE); + + if (dma_mapping_error(dev, source_phys)) { + /* + * If control arrives here, we're not mapping the source buffer. + * Make sure the alternate is large enough. + */ + if (alt_size < length) { + dev_err(dev, "Alternate buffer is too small " + "for outgoing I/O\n"); + return -ENOMEM; + } + + /* + * Copy the contents of the source buffer into the alternate + * buffer and set up the return values accordingly. + */ + memcpy(alt_virt, source, length); + + *use_virt = alt_virt; + *use_phys = alt_phys; + } else { + /* + * If control arrives here, we're mapping the source buffer. Set + * up the return values accordingly. + */ + *use_virt = source; + *use_phys = source_phys; + } + return 0; +} + +/** + * mil_outgoing_buffer_dma_end() - Ends DMA on an outgoing buffer. + * + * @this: Per-device data. + * @source: The source buffer. + * @length: The length of the data in the source buffer. + * @alt_virt: The virtual address of an alternate buffer which was ready to be + * used for DMA. + * @alt_phys: The physical address of an alternate buffer which was ready to + * be used for DMA. + * @alt_size: The size of the alternate buffer. + * @used_virt: The virtual address that was used. + * @used_phys: The physical address that was used. + */ +static void mil_outgoing_buffer_dma_end(struct gpmi_nfc_data *this, + const void *source, unsigned length, + void *alt_virt, dma_addr_t alt_phys, unsigned alt_size, + const void *used_virt, dma_addr_t used_phys) +{ + struct device *dev = this->dev; + + /* + * Check if we used the source buffer, and it's not one of our own DMA + * buffers. If so, we need to unmap it. + */ + if (used_virt == source) + dma_unmap_single(dev, used_phys, length, DMA_TO_DEVICE); +} + +/** + * mil_incoming_buffer_dma_begin() - Begins DMA on an incoming buffer. + * + * @this: Per-device data. + * @destination: The destination buffer. + * @length: The length of the data that will arrive. + * @alt_virt: The virtual address of an alternate buffer which is ready + * to be used for DMA. + * @alt_phys: The physical address of an alternate buffer which is ready + * to be used for DMA. + * @alt_size: The size of the alternate buffer. + * @use_virt: A pointer to a variable that will receive the virtual address + * to use. + * @use_phys: A pointer to a variable that will receive the physical address + * to use. + */ +static int mil_incoming_buffer_dma_begin(struct gpmi_nfc_data *this, + void *destination, unsigned length, + void *alt_virt, dma_addr_t alt_phys, unsigned alt_size, + void **use_virt, dma_addr_t *use_phys) +{ + struct device *dev = this->dev; + dma_addr_t destination_phys = ~0; + + /* + * If we can, we want to use the caller's buffer directly for DMA. Check + * if the system will let us map them. + */ + if (map_io_buffers && virt_addr_valid(destination) && + !((int)destination & 0x3) && 0) + destination_phys = + dma_map_single(dev, + (void *) destination, length, DMA_FROM_DEVICE); + + if (dma_mapping_error(dev, destination_phys)) { + /* + * If control arrives here, we're not mapping the destination + * buffer. Make sure the alternate is large enough. + */ + if (alt_size < length) { + dev_err(dev, "Alternate buffer is too small " + "for incoming I/O\n"); + return -ENOMEM; + } + + /* Set up the return values to use the alternate. */ + *use_virt = alt_virt; + *use_phys = alt_phys; + } else { + /* + * If control arrives here, we're mapping the destination + * buffer. Set up the return values accordingly. + */ + *use_virt = destination; + *use_phys = destination_phys; + } + return 0; +} + +/** + * mil_incoming_buffer_dma_end() - Ends DMA on an incoming buffer. + * + * @this: Per-device data. + * @destination: The destination buffer. + * @length: The length of the data that arrived. + * @alt_virt: The virtual address of an alternate buffer which was ready to + * be used for DMA. + * @alt_phys: The physical address of an alternate buffer which was ready to + * be used for DMA. + * @alt_size: The size of the alternate buffer. + * @used_virt: The virtual address that was used. + * @used_phys: The physical address that was used. + */ +static void mil_incoming_buffer_dma_end(struct gpmi_nfc_data *this, + void *destination, unsigned length, + void *alt_virt, dma_addr_t alt_phys, unsigned alt_size, + void *used_virt, dma_addr_t used_phys) +{ + struct device *dev = this->dev; + + /* + * Check if we used the destination buffer, and it's not one of our own + * DMA buffers. If so, we need to unmap it. + */ + if (used_virt == destination) + dma_unmap_single(dev, used_phys, length, DMA_FROM_DEVICE); + else + memcpy(destination, alt_virt, length); +} + +/* Free all the DMA buffers */ +static void mil_free_dma_buffer(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct mil *mil = &this->mil; + + /* Free the DMA buffer, if it has been allocated. */ + if (mil->page_buffer_virt && virt_addr_valid(mil->page_buffer_virt)) + dma_free_coherent(dev, mil->page_buffer_size, + mil->page_buffer_virt, + mil->page_buffer_phys); + mil->page_buffer_size = 0; + mil->page_buffer_virt = 0; + mil->page_buffer_phys = ~0; + + /* Free the command buffer, if it's been allocated. */ + if (mil->cmd_virt) + dma_free_coherent(dev, MIL_COMMAND_BUFFER_SIZE, + mil->cmd_virt, mil->cmd_phys); + mil->cmd_virt = 0; + mil->cmd_phys = ~0; +} + +/* Allocate the DMA command buffer and DMA page buffer */ +static int mil_alloc_dma_buffer(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mil *mil = &this->mil; + + /* Allocate a command buffer. */ + mil->cmd_virt = dma_alloc_coherent(dev, MIL_COMMAND_BUFFER_SIZE, + &mil->cmd_phys, GFP_DMA); + if (!mil->cmd_virt) + goto error_alloc; + + /* + * Allocate the page buffer. + * + * Both the payload buffer and the auxiliary buffer must appear on + * 32-bit boundaries. We presume the size of the payload buffer is a + * power of two and is much larger than four, which guarantees the + * auxiliary buffer will appear on a 32-bit boundary. + */ + mil->page_buffer_size = nfc_geo->payload_size_in_bytes + + nfc_geo->auxiliary_size_in_bytes; + mil->page_buffer_virt = dma_alloc_coherent(dev, mil->page_buffer_size, + &mil->page_buffer_phys, GFP_DMA); + if (!mil->page_buffer_virt) + goto error_alloc; + + /* Slice up the page buffer. */ + mil->payload_virt = mil->page_buffer_virt; + mil->payload_phys = mil->page_buffer_phys; + mil->auxiliary_virt = ((char *) mil->payload_virt) + + nfc_geo->payload_size_in_bytes; + mil->auxiliary_phys = mil->payload_phys + + nfc_geo->payload_size_in_bytes; + return 0; + +error_alloc: + printk(KERN_ERR "allocate DMA buffer error!!\n"); + mil_free_dma_buffer(this); + dump_stack(); + return -ENOMEM; +} + +/** + * mil_cmd_ctrl - MTD Interface cmd_ctrl() + * + * This is the function that we install in the cmd_ctrl function pointer of the + * owning struct nand_chip. The only functions in the reference implementation + * that use these functions pointers are cmdfunc and select_chip. + * + * In this driver, we implement our own select_chip, so this function will only + * be called by the reference implementation's cmdfunc. For this reason, we can + * ignore the chip enable bit and concentrate only on sending bytes to the + * NAND Flash. + * + * @mtd: The owning MTD. + * @data: The value to push onto the data signals. + * @ctrl: The values to push onto the control signals. + */ +static void mil_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct mil *mil = &this->mil; + struct nfc_hal *nfc = this->nfc; + int error; +#if defined(CONFIG_MTD_DEBUG) + unsigned int i; + char display[MIL_COMMAND_BUFFER_SIZE * 5]; +#endif + + /* + * Every operation begins with a command byte and a series of zero or + * more address bytes. These are distinguished by either the Address + * Latch Enable (ALE) or Command Latch Enable (CLE) signals being + * asserted. When MTD is ready to execute the command, it will deassert + * both latch enables. + * + * Rather than run a separate DMA operation for every single byte, we + * queue them up and run a single DMA operation for the entire series + * of command and data bytes. + */ + if ((ctrl & (NAND_ALE | NAND_CLE))) { + if (data != NAND_CMD_NONE) + mil->cmd_virt[mil->command_length++] = data; + return; + } + + /* + * If control arrives here, MTD has deasserted both the ALE and CLE, + * which means it's ready to run an operation. Check if we have any + * bytes to send. + */ + if (!mil->command_length) + return; + + /* Hand the command over to the NFC. */ +#if defined(CONFIG_MTD_DEBUG) + display[0] = 0; + for (i = 0; i < mil->command_length; i++) + sprintf(display + strlen(display), " 0x%02x", + mil->cmd_virt[i] & 0xff); + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc cmd_ctrl] command: %s\n", display); +#endif + + error = nfc->send_command(this, + mil->current_chip, mil->cmd_phys, mil->command_length); + if (error) { + dev_err(dev, "[%s] Chip: %u, Error %d\n", + __func__, mil->current_chip, error); + print_hex_dump(KERN_ERR, + " Command Bytes: ", DUMP_PREFIX_NONE, 16, 1, + mil->cmd_virt, mil->command_length, 0); + } + + /* Reset. */ + mil->command_length = 0; +} + +/** + * mil_dev_ready() - MTD Interface dev_ready() + * + * @mtd: A pointer to the owning MTD. + */ +static int mil_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct nfc_hal *nfc = this->nfc; + struct mil *mil = &this->mil; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc dev_ready]\n"); + + return nfc->is_ready(this, mil->current_chip); +} + +/** + * mil_select_chip() - MTD Interface select_chip() + * + * @mtd: A pointer to the owning MTD. + * @chip: The chip number to select, or -1 to select no chip. + */ +static void mil_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct mil *mil = &this->mil; + struct nfc_hal *nfc = this->nfc; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc select_chip] chip: %d\n", chip); + + /* Figure out what kind of transition this is. */ + if ((mil->current_chip < 0) && (chip >= 0)) { + nfc->begin(this); + } else if ((mil->current_chip >= 0) && (chip < 0)) { + nfc->end(this); + } else { + } + + mil->current_chip = chip; +} + +/** + * mil_read_buf() - MTD Interface read_buf(). + * + * @mtd: A pointer to the owning MTD. + * @buf: The destination buffer. + * @len: The number of bytes to read. + */ +static void mil_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mil *mil = &this->mil; + void *use_virt = 0; + dma_addr_t use_phys = ~0; + int error; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc readbuf] len: %d\n", len); + + /* Set up DMA. */ + error = mil_incoming_buffer_dma_begin(this, buf, len, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + &use_virt, &use_phys); + if (error) { + dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__); + return; + } + + /* Ask the NFC. */ + nfc->read_data(this, mil->current_chip, use_phys, len); + + /* Finish with DMA. */ + mil_incoming_buffer_dma_end(this, buf, len, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + use_virt, use_phys); +} + +/** + * mil_write_buf() - MTD Interface write_buf(). + * + * @mtd: A pointer to the owning MTD. + * @buf: The source buffer. + * @len: The number of bytes to read. + */ +static void mil_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mil *mil = &this->mil; + const void *use_virt = 0; + dma_addr_t use_phys = ~0; + int error; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc writebuf] len: %d\n", len); + /* Set up DMA. */ + error = mil_outgoing_buffer_dma_begin(this, buf, len, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + &use_virt, &use_phys); + if (error) { + dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__); + return; + } + + /* Ask the NFC. */ + nfc->send_data(this, mil->current_chip, use_phys, len); + + /* Finish with DMA. */ + mil_outgoing_buffer_dma_end(this, buf, len, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + use_virt, use_phys); +} + +/** + * mil_read_byte() - MTD Interface read_byte(). + * + * @mtd: A pointer to the owning MTD. + */ +static uint8_t mil_read_byte(struct mtd_info *mtd) +{ + uint8_t byte; + + mil_read_buf(mtd, (uint8_t *)&byte, 1); + return byte; +} + +/** + * mil_handle_block_mark_swapping() - Handles block mark swapping. + * + * Note that, when this function is called, it doesn't know whether it's + * swapping the block mark, or swapping it *back* -- but it doesn't matter + * because the the operation is the same. + * + * @this: Per-device data. + * @payload: A pointer to the payload buffer. + * @auxiliary: A pointer to the auxiliary buffer. + */ +static void mil_handle_block_mark_swapping(struct gpmi_nfc_data *this, + void *payload, void *auxiliary) +{ + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct boot_rom_helper *rom = this->rom; + unsigned char *p; + unsigned char *a; + unsigned int bit; + unsigned char mask; + unsigned char from_data; + unsigned char from_oob; + + /* Check if we're doing block mark swapping. */ + if (!rom->swap_block_mark) + return; + + /* + * If control arrives here, we're swapping. Make some convenience + * variables. + */ + bit = nfc_geo->block_mark_bit_offset; + p = ((unsigned char *) payload) + nfc_geo->block_mark_byte_offset; + a = auxiliary; + + /* + * Get the byte from the data area that overlays the block mark. Since + * the ECC engine applies its own view to the bits in the page, the + * physical block mark won't (in general) appear on a byte boundary in + * the data. + */ + from_data = (p[0] >> bit) | (p[1] << (8 - bit)); + + /* Get the byte from the OOB. */ + from_oob = a[0]; + + /* Swap them. */ + a[0] = from_data; + + mask = (0x1 << bit) - 1; + p[0] = (p[0] & mask) | (from_oob << bit); + + mask = ~0 << bit; + p[1] = (p[1] & mask) | (from_oob >> (8 - bit)); +} + +/** + * mil_ecc_read_page() - MTD Interface ecc.read_page(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the destination buffer. + */ +static int mil_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, + uint8_t *buf, int page) +{ + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct mil *mil = &this->mil; + void *payload_virt = 0; + dma_addr_t payload_phys = ~0; + void *auxiliary_virt = 0; + dma_addr_t auxiliary_phys = ~0; + unsigned int i; + unsigned char *status; + unsigned int failed; + unsigned int corrected; + int error = 0; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_read_page]\n"); + + /* + * Set up DMA. + * + * Notice that we don't try to use the caller's buffer as the auxiliary. + * We need to do a lot of fiddling to deliver the OOB, so there's no + * point. + */ + error = mil_incoming_buffer_dma_begin(this, buf, mtd->writesize, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + &payload_virt, &payload_phys); + if (error) { + dev_err(dev, "[%s] Inadequate DMA buffer\n", __func__); + error = -ENOMEM; + goto exit_payload; + } + auxiliary_virt = mil->auxiliary_virt; + auxiliary_phys = mil->auxiliary_phys; + + /* Ask the NFC. */ + error = nfc->read_page(this, mil->current_chip, + payload_phys, auxiliary_phys); + if (error) { + dev_err(dev, "[%s] Error in ECC-based read: %d\n", + __func__, error); + goto exit_nfc; + } + + /* Handle block mark swapping. */ + mil_handle_block_mark_swapping(this, payload_virt, auxiliary_virt); + + /* Loop over status bytes, accumulating ECC status. */ + failed = 0; + corrected = 0; + status = ((unsigned char *) auxiliary_virt) + + nfc_geo->auxiliary_status_offset; + + for (i = 0; i < nfc_geo->ecc_chunk_count; i++, status++) { + if ((*status == 0x00) || (*status == 0xff)) + continue; + + if (*status == 0xfe) { + failed++; + continue; + } + corrected += *status; + } + + /* + * Propagate ECC status to the owning MTD only when failed or + * corrected times nearly reaches our ECC correction threshold. + */ + if (failed || corrected >= (nfc_geo->ecc_strength - 1)) { + mtd->ecc_stats.failed += failed; + mtd->ecc_stats.corrected += corrected; + } + + /* + * It's time to deliver the OOB bytes. See mil_ecc_read_oob() for + * details about our policy for delivering the OOB. + * + * We fill the caller's buffer with set bits, and then copy the block + * mark to th caller's buffer. Note that, if block mark swapping was + * necessary, it has already been done, so we can rely on the first + * byte of the auxiliary buffer to contain the block mark. + */ + memset(nand->oob_poi, ~0, mtd->oobsize); + nand->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0]; + +exit_nfc: + mil_incoming_buffer_dma_end(this, buf, mtd->writesize, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + payload_virt, payload_phys); +exit_payload: + return error; +} + +/** + * mil_ecc_write_page() - MTD Interface ecc.write_page(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the source buffer. + */ +static void mil_ecc_write_page(struct mtd_info *mtd, + struct nand_chip *nand, const uint8_t *buf) +{ + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct nfc_hal *nfc = this->nfc; + struct nfc_geometry *nfc_geo = &this->nfc_geometry; + struct boot_rom_helper *rom = this->rom; + struct mil *mil = &this->mil; + const void *payload_virt = 0; + dma_addr_t payload_phys = ~0; + const void *auxiliary_virt = 0; + dma_addr_t auxiliary_phys = ~0; + int error; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_write_page]\n"); + + /* Set up DMA. */ + if (rom->swap_block_mark) { + /* + * If control arrives here, we're doing block mark swapping. + * Since we can't modify the caller's buffers, we must copy them + * into our own. + */ + memcpy(mil->payload_virt, buf, mtd->writesize); + payload_virt = mil->payload_virt; + payload_phys = mil->payload_phys; + + memcpy(mil->auxiliary_virt, nand->oob_poi, + nfc_geo->auxiliary_size_in_bytes); + auxiliary_virt = mil->auxiliary_virt; + auxiliary_phys = mil->auxiliary_phys; + + /* Handle block mark swapping. */ + mil_handle_block_mark_swapping(this, + (void *) payload_virt, (void *) auxiliary_virt); + } else { + /* + * If control arrives here, we're not doing block mark swapping, + * so we can to try and use the caller's buffers. + */ + error = mil_outgoing_buffer_dma_begin(this, + buf, mtd->writesize, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + &payload_virt, &payload_phys); + if (error) { + dev_err(dev, "[%s] Inadequate payload DMA buffer\n", + __func__); + return; + } + + error = mil_outgoing_buffer_dma_begin(this, + nand->oob_poi, mtd->oobsize, + mil->auxiliary_virt, mil->auxiliary_phys, + nfc_geo->auxiliary_size_in_bytes, + &auxiliary_virt, &auxiliary_phys); + if (error) { + dev_err(dev, "[%s] Inadequate auxiliary DMA buffer\n", + __func__); + goto exit_auxiliary; + } + } + + /* Ask the NFC. */ + error = nfc->send_page(this, mil->current_chip, + payload_phys, auxiliary_phys); + if (error) + dev_err(dev, "[%s] Error in ECC-based write: %d\n", + __func__, error); + + /* Return. */ + if (!rom->swap_block_mark) + mil_outgoing_buffer_dma_end(this, nand->oob_poi, mtd->oobsize, + mil->auxiliary_virt, mil->auxiliary_phys, + nfc_geo->auxiliary_size_in_bytes, + auxiliary_virt, auxiliary_phys); +exit_auxiliary: + if (!rom->swap_block_mark) + mil_outgoing_buffer_dma_end(this, buf, mtd->writesize, + mil->payload_virt, mil->payload_phys, + nfc_geo->payload_size_in_bytes, + payload_virt, payload_phys); +} + +/** + * mil_hook_block_markbad() - Hooked MTD Interface block_markbad(). + * + * This function is a veneer that replaces the function originally installed by + * the NAND Flash MTD code. See the description of the marking_a_bad_block field + * in struct mil for more information about this. + * + * @mtd: A pointer to the MTD. + * @ofs: Byte address of the block to mark. + */ +static int mil_hook_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + register struct nand_chip *chip = mtd->priv; + struct gpmi_nfc_data *this = chip->priv; + struct mil *mil = &this->mil; + int ret; + + mil->marking_a_bad_block = true; + ret = mil->hooked_block_markbad(mtd, ofs); + mil->marking_a_bad_block = false; + return ret; +} + +/** + * mil_ecc_read_oob() - MTD Interface ecc.read_oob(). + * + * There are several places in this driver where we have to handle the OOB and + * block marks. This is the function where things are the most complicated, so + * this is where we try to explain it all. All the other places refer back to + * here. + * + * These are the rules, in order of decreasing importance: + * + * 1) Nothing the caller does can be allowed to imperil the block mark, so all + * write operations take measures to protect it. + * + * 2) In read operations, the first byte of the OOB we return must reflect the + * true state of the block mark, no matter where that block mark appears in + * the physical page. + * + * 3) ECC-based read operations return an OOB full of set bits (since we never + * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads + * return). + * + * 4) "Raw" read operations return a direct view of the physical bytes in the + * page, using the conventional definition of which bytes are data and which + * are OOB. This gives the caller a way to see the actual, physical bytes + * in the page, without the distortions applied by our ECC engine. + * + * + * What we do for this specific read operation depends on two questions: + * + * 1) Are we doing a "raw" read, or an ECC-based read? + * + * 2) Are we using block mark swapping or transcription? + * + * There are four cases, illustrated by the following Karnaugh map: + * + * | Raw | ECC-based | + * -------------+-------------------------+-------------------------+ + * | Read the conventional | | + * | OOB at the end of the | | + * Swapping | page and return it. It | | + * | contains exactly what | | + * | we want. | Read the block mark and | + * -------------+-------------------------+ return it in a buffer | + * | Read the conventional | full of set bits. | + * | OOB at the end of the | | + * | page and also the block | | + * Transcribing | mark in the metadata. | | + * | Copy the block mark | | + * | into the first byte of | | + * | the OOB. | | + * -------------+-------------------------+-------------------------+ + * + * Note that we break rule #4 in the Transcribing/Raw case because we're not + * giving an accurate view of the actual, physical bytes in the page (we're + * overwriting the block mark). That's OK because it's more important to follow + * rule #2. + * + * It turns out that knowing whether we want an "ECC-based" or "raw" read is not + * easy. When reading a page, for example, the NAND Flash MTD code calls our + * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an + * ECC-based or raw view of the page is implicit in which function it calls + * (there is a similar pair of ECC-based/raw functions for writing). + * + * Since MTD assumes the OOB is not covered by ECC, there is no pair of + * ECC-based/raw functions for reading or or writing the OOB. The fact that the + * caller wants an ECC-based or raw view of the page is not propagated down to + * this driver. + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @page: The page number to read. + * @sndcmd: Indicates this function should send a command to the chip before + * reading the out-of-band bytes. This is only false for small page + * chips that support auto-increment. + */ +static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, + int page, int sndcmd) +{ + struct gpmi_nfc_data *this = nand->priv; + struct boot_rom_helper *rom = this->rom; + + DEBUG(MTD_DEBUG_LEVEL2, "[gpmi_nfc ecc_read_oob] " + "page: 0x%06x, sndcmd: %s\n", page, sndcmd ? "Yes" : "No"); + + /* clear the OOB buffer */ + memset(nand->oob_poi, ~0, mtd->oobsize); + + /* Read out the conventional OOB. */ + nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); + nand->read_buf(mtd, nand->oob_poi, mtd->oobsize); + + /* + * Now, we want to make sure the block mark is correct. In the + * Swapping/Raw case, we already have it. Otherwise, we need to + * explicitly read it. + */ + if (!rom->swap_block_mark) { + /* Read the block mark into the first byte of the OOB buffer. */ + nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + nand->oob_poi[0] = nand->read_byte(mtd); + } + + /* + * Return true, indicating that the next call to this function must send + * a command. + */ + return true; +} + +/** + * mil_ecc_write_oob() - MTD Interface ecc.write_oob(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @page: The page number to write. + */ +static int mil_ecc_write_oob(struct mtd_info *mtd, + struct nand_chip *nand, int page) +{ + struct gpmi_nfc_data *this = nand->priv; + struct device *dev = this->dev; + struct mil *mil = &this->mil; + struct boot_rom_helper *rom = this->rom; + uint8_t block_mark = 0; + int block_mark_column; + int status; + int error = 0; + + DEBUG(MTD_DEBUG_LEVEL2, + "[gpmi_nfc ecc_write_oob] page: 0x%06x\n", page); + /* + * There are fundamental incompatibilities between the i.MX GPMI NFC and + * the NAND Flash MTD model that make it essentially impossible to write + * the out-of-band bytes. + * + * We permit *ONE* exception. If the *intent* of writing the OOB is to + * mark a block bad, we can do that. + */ + if (!mil->marking_a_bad_block) { + dev_emerg(dev, "This driver doesn't support writing the OOB\n"); + WARN_ON(1); + error = -EIO; + goto exit; + } + + /* + * If control arrives here, we're marking a block bad. First, figure out + * where the block mark is. + * + * If we're using swapping, the block mark is in the conventional + * location. Otherwise, we're using transcription, and the block mark + * appears in the first byte of the page. + */ + if (rom->swap_block_mark) + block_mark_column = mtd->writesize; + else + block_mark_column = 0; + + /* Write the block mark. */ + nand->cmdfunc(mtd, NAND_CMD_SEQIN, block_mark_column, page); + nand->write_buf(mtd, &block_mark, 1); + nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + + status = nand->waitfunc(mtd, nand); + + /* Check if it worked. */ + if (status & NAND_STATUS_FAIL) + error = -EIO; +exit: + return error; +} + +/** + * mil_block_bad - Claims all blocks are good. + * + * In principle, this function is *only* called when the NAND Flash MTD system + * isn't allowed to keep an in-memory bad block table, so it is forced to ask + * the driver for bad block information. + * + * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so + * this function is *only* called when we take it away. + * + * We take away the in-memory BBT when the user sets the "ignorebad" parameter, + * which indicates that all blocks should be reported good. + * + * Thus, this function is only called when we want *all* blocks to look good, + * so it *always* return success. + * + * @mtd: Ignored. + * @ofs: Ignored. + * @getchip: Ignored. + */ +static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + return 0; +} + + +/** + * mil_set_nfc_geometry() - Set up the NFC geometry. + * + * This function calls the NFC HAL to select an NFC geometry that is compatible + * with the medium's physical geometry. + * + * @this: Per-device data. + */ +static int mil_set_nfc_geometry(struct gpmi_nfc_data *this) +{ + struct nfc_hal *nfc = this->nfc; +#if defined(DETAILED_INFO) + struct nfc_geometry *geo = &this->nfc_geometry; +#endif + /* Set the NFC geometry. */ + if (nfc->set_geometry(this)) + return !0; + + #if defined(DETAILED_INFO) + pr_info("------------\n"); + pr_info("NFC Geometry\n"); + pr_info("------------\n"); + pr_info("ECC Algorithm : %s\n", geo->ecc_algorithm); + pr_info("ECC Strength : %u\n", geo->ecc_strength); + pr_info("Page Size in Bytes : %u\n", geo->page_size_in_bytes); + pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size_in_bytes); + pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size_in_bytes); + pr_info("ECC Chunk Count : %u\n", geo->ecc_chunk_count); + pr_info("Payload Size in Bytes : %u\n", geo->payload_size_in_bytes); + pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size_in_bytes); + pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset); + pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset); + pr_info("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset); + #endif + + return 0; +} + +/** + * mil_set_boot_rom_helper_geometry() - Set up the Boot ROM Helper geometry. + * + * @this: Per-device data. + */ +static int mil_set_boot_rom_helper_geometry(struct gpmi_nfc_data *this) +{ + struct boot_rom_helper *rom = this->rom; +#if defined(DETAILED_INFO) + struct boot_rom_geometry *geo = &this->rom_geometry; +#endif + + /* Set the Boot ROM Helper geometry. */ + if (rom->set_geometry(this)) + return !0; + + #if defined(DETAILED_INFO) + pr_info("-----------------\n"); + pr_info("Boot ROM Geometry\n"); + pr_info("-----------------\n"); + pr_info("Boot Area Count : %u\n", geo->boot_area_count); + pr_info("Boot Area Size in Bytes : %u (0x%x)\n", + geo->boot_area_size_in_bytes, geo->boot_area_size_in_bytes); + pr_info("Stride Size in Pages : %u\n", geo->stride_size_in_pages); + pr_info("Search Area Stride Exponent: %u\n", + geo->search_area_stride_exponent); + #endif + return 0; +} + +/** + * mil_set_geometry() - Set up the medium geometry. + * + * @this: Per-device data. + */ +static int mil_set_geometry(struct gpmi_nfc_data *this) +{ + /* Free the temporary DMA memory for read ID case */ + mil_free_dma_buffer(this); + + /* Set up the NFC geometry. */ + if (mil_set_nfc_geometry(this)) + return -ENXIO; + + /* Alloc the new DMA buffers according to the pagesize and oobsize */ + return mil_alloc_dma_buffer(this); +} + +/** + * mil_pre_bbt_scan() - Prepare for the BBT scan. + * + * @this: Per-device data. + */ +static int mil_pre_bbt_scan(struct gpmi_nfc_data *this) +{ + struct boot_rom_helper *rom = this->rom; + int error = 0; + + if (mil_set_boot_rom_helper_geometry(this)) + return -ENXIO; + + /* This is ROM arch-specific initilization before the BBT scanning. */ + if (rom->rom_extra_init) + error = rom->rom_extra_init(this); + return error; +} + +/** + * mil_scan_bbt() - MTD Interface scan_bbt(). + * + * The HIL calls this function once, when it initializes the NAND Flash MTD. + * + * @mtd: A pointer to the owning MTD. + */ +static int mil_scan_bbt(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd->priv; + struct gpmi_nfc_data *this = nand->priv; + int error; + + /* + * Tell MTD users that the out-of-band area can't be written. + * + * This flag is not part of the standard kernel source tree. It comes + * from a patch that touches both MTD and JFFS2. + * + * The problem is that, without this patch, JFFS2 believes it can write + * the data area and the out-of-band area separately. This is wrong for + * two reasons: + * + * 1) Our NFC distributes out-of-band bytes throughout the page, + * intermingled with the data, and covered by the same ECC. + * Thus, it's not possible to write the out-of-band bytes and + * data bytes separately. + * + * 2) Large page (MLC) Flash chips don't support partial page + * writes. You must write the entire page at a time. Thus, even + * if our NFC didn't force you to write out-of-band and data + * bytes together, it would *still* be a bad idea to do + * otherwise. + */ + mtd->flags &= ~MTD_OOB_WRITEABLE; + + /* Prepare for the BBT scan. */ + error = mil_pre_bbt_scan(this); + if (error) + return error; + + /* use the default BBT implementation */ + return nand_default_bbt(mtd); +} + +/** + * mil_boot_areas_init() - Initializes boot areas. + * + * @this: Per-device data. + */ +static int mil_boot_areas_init(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct boot_rom_geometry *rom = &this->rom_geometry; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + struct nand_device_info *info = &this->device_info; + int mtd_support_is_adequate; + unsigned int i; + struct mtd_partition partitions[4]; + struct mtd_info *search_mtd; + struct mtd_info *chip_0_remainder_mtd = 0; + struct mtd_info *medium_remainder_mtd = 0; + struct mtd_info *concatenate[2]; + + /* + * Here we declare the static strings we use to name partitions. We use + * static strings because, as of 2.6.31, the partitioning code *always* + * registers the partition MTDs it creates and leaves behind *no* other + * trace of its work. So, once we've created a partition, we must search + * the master MTD table to find the MTDs we created. Since we're using + * static strings, we can simply search the master table for an MTD with + * a name field pointing to a known address. + */ + static char *chip_0_boot_name = "gpmi-nfc-0-boot"; + static char *chip_0_remainder_name = "gpmi-nfc-0-remainder"; + static char *chip_1_boot_name = "gpmi-nfc-1-boot"; + static char *medium_remainder_name = "gpmi-nfc-remainder"; + static char *general_use_name = "gpmi-nfc-general-use"; + + /* Check if we're protecting the boot areas.*/ + if (!rom->boot_area_count) { + /* + * If control arrives here, we're not protecting the boot areas. + * In this case, there are not boot area partitons, and the main + * MTD is the general use MTD. + */ + mil->general_use_mtd = &mil->mtd; + + return 0; + } + + /* + * If control arrives here, we're protecting the boot areas. Check if we + * have the MTD support we need. + */ + pr_info("Boot area protection is enabled.\n"); + + if (rom->boot_area_count > 1) { + /* + * If the Boot ROM wants more than one boot area, then we'll + * need to create partitions *and* concatenate them. + */ + #if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT) + mtd_support_is_adequate = true; + #else + mtd_support_is_adequate = false; + #endif + } else if (rom->boot_area_count == 1) { + /* + * If the Boot ROM wants only one boot area, then we only need + * to create partitions -- we don't need to concatenate them. + */ + #if defined(CONFIG_MTD_PARTITIONS) + mtd_support_is_adequate = true; + #else + mtd_support_is_adequate = false; + #endif + } else { + /* + * If control arrives here, we're protecting the boot area, but + * somehow the boot area count was set to zero. This doesn't + * make any sense. + */ + dev_err(dev, "Internal error: boot area count is " + "incorrectly set to zero."); + return -ENXIO; + } + + if (!mtd_support_is_adequate) { + dev_err(dev, "Configured MTD support is inadequate to " + "protect the boot area(s)."); + return -ENXIO; + } + + /* + * If control arrives here, we're protecting boot areas and we have + * everything we need to do so. + * + * We have special code to handle the case for one boot area. + * + * The code that handles "more than one" boot area actually only handles + * two. We *could* write the general case, but that would take a lot of + * time to both write and test -- and, right now, we don't have a chip + * that cares. + */ + + /* Check if a boot area is larger than a single chip. */ + if (rom->boot_area_size_in_bytes > info->chip_size_in_bytes) { + dev_emerg(dev, "Boot area size is larger than a chip"); + return -ENXIO; + } + + if (rom->boot_area_count == 1) { +#if defined(CONFIG_MTD_PARTITIONS) + /* + * We partition the medium like so: + * + * +------+----------------------------------------------------+ + * | Boot | General Use | + * +------+----------------------------------------------------+ + */ + + /* Chip 0 Boot */ + partitions[0].name = chip_0_boot_name; + partitions[0].offset = 0; + partitions[0].size = rom->boot_area_size_in_bytes; + partitions[0].mask_flags = 0; + + /* General Use */ + partitions[1].name = general_use_name; + partitions[1].offset = rom->boot_area_size_in_bytes; + partitions[1].size = MTDPART_SIZ_FULL; + partitions[1].mask_flags = 0; + + /* Construct and register the partitions. */ + add_mtd_partitions(mtd, partitions, 2); + + /* Find the general use MTD. */ + i = 0; + while ((search_mtd = get_mtd_device(0, i))) { + /* Check if we got nonsense. */ + if ((!search_mtd) || (search_mtd == ERR_PTR(-ENODEV))) + break; + + /* Check if the current MTD is one of our remainders. */ + if (search_mtd->name == general_use_name) + mil->general_use_mtd = search_mtd; + + /* Put the MTD back. We only wanted a quick look. */ + put_mtd_device(search_mtd); + + i++; + } + + if (!mil->general_use_mtd) { + dev_emerg(dev, "Can't find general use MTD"); + BUG(); + } +#endif + } else if (rom->boot_area_count == 2) { +#if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT) + /* + * If control arrives here, there is more than one boot area. + * We partition the medium and concatenate the remainders like + * so: + * + * --- Chip 0 --- --- Chip 1 --- ... ------- Chip N ------- + * / \ / \ + * +----+----------+----+--------------- ... ------------------+ + * |Boot|Remainder |Boot| Remainder | + * +----+----------+----+--------------- ... ------------------+ + * | | / / + * | | / / + * | | / / + * | |/ / + * +----------+----------- ... ----------------------+ + * | General Use | + * +---------------------- ... ----------------------+ + * + * Notice that the results we leave in the master MTD table + * look like this: + * + * * Chip 0 Boot Area + * * Chip 1 Boot Area + * * General Use + * + * Some user space programs expect the boot partitions to + * appear first. This is naive, but let's try not to cause + * any trouble, where we can avoid it. + */ + + /* Chip 0 Boot */ + partitions[0].name = chip_0_boot_name; + partitions[0].offset = 0; + partitions[0].size = rom->boot_area_size_in_bytes; + partitions[0].mask_flags = 0; + + /* Chip 1 Boot */ + partitions[1].name = chip_1_boot_name; + partitions[1].offset = nand->chipsize; + partitions[1].size = rom->boot_area_size_in_bytes; + partitions[1].mask_flags = 0; + + /* Chip 0 Remainder */ + partitions[2].name = chip_0_remainder_name; + partitions[2].offset = rom->boot_area_size_in_bytes; + partitions[2].size = nand->chipsize - + rom->boot_area_size_in_bytes; + partitions[2].mask_flags = 0; + + /* Medium Remainder */ + partitions[3].name = medium_remainder_name; + partitions[3].offset = nand->chipsize + + rom->boot_area_size_in_bytes; + partitions[3].size = MTDPART_SIZ_FULL; + partitions[3].mask_flags = 0; + + /* Construct and register the partitions. */ + add_mtd_partitions(mtd, partitions, 4); + + /* Find the remainder partitions. */ + i = 0; + while ((search_mtd = get_mtd_device(0, i))) { + /* Check if we got nonsense. */ + if ((!search_mtd) || (search_mtd == ERR_PTR(-ENODEV))) + break; + + /* Check if the current MTD is one of our remainders. */ + if (search_mtd->name == chip_0_remainder_name) + chip_0_remainder_mtd = search_mtd; + + if (search_mtd->name == medium_remainder_name) + medium_remainder_mtd = search_mtd; + + /* Put the MTD back. We only wanted a quick look. */ + put_mtd_device(search_mtd); + + i++; + } + + if (!chip_0_remainder_mtd || !medium_remainder_mtd) { + dev_emerg(dev, "Can't find remainder partitions"); + BUG(); + } + + /* + * Unregister the remainder MTDs. Note that we are *not* + * destroying these MTDs -- we're just removing from the + * globally-visible list. There's no need for anyone to see + * these. + */ + del_mtd_device(chip_0_remainder_mtd); + del_mtd_device(medium_remainder_mtd); + + /* Concatenate the remainders and register the result. */ + concatenate[0] = chip_0_remainder_mtd; + concatenate[1] = medium_remainder_mtd; + + mil->general_use_mtd = mtd_concat_create(concatenate, + 2, general_use_name); + + add_mtd_device(mil->general_use_mtd); +#endif + + } else { + dev_err(dev, "Boot area count greater than two is " + "unimplemented.\n"); + return -ENXIO; + } + + return 0; +} + +/** + * mil_boot_areas_exit() - Shuts down boot areas. + * + * @this: Per-device data. + */ +static void mil_boot_areas_exit(struct gpmi_nfc_data *this) +{ + struct boot_rom_geometry *rom = &this->rom_geometry; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + + /* Check if we're protecting the boot areas.*/ + if (!rom->boot_area_count) { + /* + * If control arrives here, we're not protecting the boot areas. + * That means we never created any boot area partitions, and the + * general use MTD is just the main MTD. + */ + mil->general_use_mtd = 0; + + return; + } + + /* + * If control arrives here, we're protecting the boot areas. + * + * Start by checking if there is more than one boot area. If so, then + * we both partitioned the medium and then concatenated some of the + * partitions to form the general use MTD. The first step is to get rid + * of the concatenation. + */ + #if defined(CONFIG_MTD_PARTITIONS) && defined(CONFIG_MTD_CONCAT) + if (rom->boot_area_count > 1) { + del_mtd_device(mil->general_use_mtd); + mtd_concat_destroy(mil->general_use_mtd); + } + #endif + + /* + * At this point, we're left only with the partitions of the main MTD. + * Delete them. + */ + #if defined(CONFIG_MTD_PARTITIONS) + del_mtd_partitions(mtd); + #endif + + /* The general use MTD no longer exists. */ + mil->general_use_mtd = 0; +} + +/** + * mil_construct_ubi_partitions() - Constructs partitions for UBI. + * + * MTD uses a 64-bit value to express the size of MTDs, but UBI is still using + * a 32-bit value. For this reason, UBI can't work on top of an MTD with size + * greater than 2GiB. In this function, we examine the general use MTD and, if + * it's larger than 2GiB, we construct a set of partitions for that MTD such + * that none are too large for UBI to comprehend. + * + * @this: Per-device data. + */ +static void mil_construct_ubi_partitions(struct gpmi_nfc_data *this) +{ +#if defined(CONFIG_MTD_PARTITIONS) + struct device *dev = this->dev; + struct mil *mil = &this->mil; + unsigned int partition_count; + struct mtd_partition *partitions; + unsigned int name_size; + char *names; + unsigned int memory_block_size; + unsigned int i; + + static const char *name_prefix = "gpmi-nfc-ubi-"; + + /* + * If the general use MTD isn't larger than 2GiB, we have nothing to do. + */ + if (mil->general_use_mtd->size <= SZ_2G) + return; + + /* + * If control arrives here, the general use MTD is larger than 2GiB. We + * need to split it up into some number of partitions. Find out how many + * 2GiB partitions we'll be creating. + */ + partition_count = mil->general_use_mtd->size >> 31; + + /* + * If the MTD size doesn't evenly divide by 2GiB, we'll need another + * partition to hold the extra. + */ + if (mil->general_use_mtd->size & ((1 << 30) - 1)) + partition_count++; + + /* + * We're going to allocate a single memory block to contain all the + * partition structures and their names. Calculate how large it must be. + */ + name_size = strlen(name_prefix) + 4; + + memory_block_size = (sizeof(*partitions) + name_size) * partition_count; + + /* + * Attempt to allocate the block. + */ + partitions = kzalloc(memory_block_size, GFP_KERNEL); + if (!partitions) { + dev_err(dev, "Could not allocate memory for UBI partitions.\n"); + return; + } + + names = (char *)(partitions + partition_count); + + /* Loop over partitions, filling in the details. */ + for (i = 0; i < partition_count; i++) { + partitions[i].name = names; + partitions[i].size = SZ_2G; + partitions[i].offset = MTDPART_OFS_NXTBLK; + + sprintf(names, "%s%u", name_prefix, i); + names += name_size; + } + + /* Adjust the last partition to take up the remainder. */ + partitions[i - 1].size = MTDPART_SIZ_FULL; + + /* Record everything in the device data structure. */ + mil->partitions = partitions; + mil->partition_count = partition_count; + mil->ubi_partition_memory = partitions; +#endif +} + +/** + * mil_partitions_init() - Initializes partitions. + * + * @this: Per-device data. + */ +static int mil_partitions_init(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + int error; + + /* + * Set up the boot areas. When this function returns, if there has been + * no error, the boot area partitions (if any) will have been created + * and registered. Also, the general_use_mtd field will point to an MTD + * we can use. + */ + error = mil_boot_areas_init(this); + if (error) + return error; + + /* + * If we've been told to, register the MTD that represents the entire + * medium. Normally, we don't register the main MTD because we only want + * to expose the medium through the boot area partitions and the general + * use partition. + * + * We do this *after* setting up the boot areas because, for historical + * reasons, we like the lowest-numbered MTDs to be the boot areas. + */ + if (register_main_mtd) { + pr_info("Registering the main MTD.\n"); + add_mtd_device(mtd); + } + +#if defined(CONFIG_MTD_PARTITIONS) + /* + * If control arrives here, partitioning is available. + * + * There are three possible sets of partitions we might apply, in order + * of decreasing priority: + * + * 1) Partitions dynamically discovered from sources defined by the + * platform. These can come from, for example, the command line or + * a partition table. + * + * 2) Partitions attached to the platform data. + * + * 3) Partitions we generate to deal with limitations in UBI. + * + * Recall that the pointer to the general use MTD *may* just point to + * the main MTD. + */ + + /* + * First, try to get partition information from the sources defined by + * the platform. + */ + if (pdata->partition_source_types) + mil->partition_count = + parse_mtd_partitions(mil->general_use_mtd, + pdata->partition_source_types, + &mil->partitions, 0); + + /* + * Check if we got anything. If not, then accept whatever partitions are + * attached to the platform data. + */ + if ((mil->partition_count <= 0) && (pdata->partitions)) { + mil->partition_count = mil->partition_count; + mil->partitions = mil->partitions; + } + + /* + * If we still don't have any partitions to apply, then we might want to + * apply some of our own, to account for UBI's limitations. + */ + if (!mil->partition_count) + mil_construct_ubi_partitions(this); + + /* If we came up with any partitions, apply them. */ + if (mil->partition_count) + add_mtd_partitions(mil->general_use_mtd, + mil->partitions, + mil->partition_count); +#endif + return 0; +} + +/** + * mil_partitions_exit() - Shuts down partitions. + * + * @this: Per-device data. + */ +static void mil_partitions_exit(struct gpmi_nfc_data *this) +{ + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + + /* Check if we applied any partitions to the general use MTD. */ + #if defined(CONFIG_MTD_PARTITIONS) + + if (mil->partition_count) + del_mtd_partitions(mil->general_use_mtd); + + kfree(mil->ubi_partition_memory); + + #endif + + /* + * If we were told to register the MTD that represents the entire + * medium, unregister it now. Note that this does *not* "destroy" the + * MTD - it merely unregisters it. That's important because all our + * other MTDs depend on this one. + */ + if (register_main_mtd) + del_mtd_device(mtd); + + /* Tear down the boot areas. */ + mil_boot_areas_exit(this); +} + +/* + * This function is used to set the mtd->pagesize, mtd->oobsize, + * mtd->erasesize. Yes, we also do some initialization. + * + * Return with the bus width. 0 for 8-bit, -1 for error. + */ +static int gpmi_init_size(struct mtd_info *mtd, struct nand_chip *nand, + u8 *id_bytes) +{ + struct gpmi_nfc_data *this = nand->priv; + struct nfc_hal *nfc = this->nfc; + struct mil *mil = &this->mil; + struct nand_ecclayout *layout = &mil->oob_layout; + struct nand_device_info *info; + struct gpmi_nfc_timing timing; + int error; + + /* Look up this device in our database. */ + info = nand_device_get_info(id_bytes); + if (!info) { + pr_err("Unrecognized NAND Flash device.\n"); + return -1; + } + + /* Display the information we discovered. */ + #if defined(DETAILED_INFO) + pr_info("-----------------------------\n"); + pr_info("NAND Flash Device Information\n"); + pr_info("-----------------------------\n"); + nand_device_print_info(info); + #endif + + /* + * Init the right NAND/MTD parameters which will be used + * in the following mil_set_geometry(). + */ + mtd->writesize = 1 << (fls(info->page_total_size_in_bytes) - 1); + mtd->erasesize = mtd->writesize * info->block_size_in_pages; + mtd->oobsize = info->page_total_size_in_bytes - mtd->writesize; + nand->chipsize = info->chip_size_in_bytes; + + /* Configure the struct nand_ecclayout. */ + layout->eccbytes = 0; + layout->oobavail = mtd->oobsize; + layout->oobfree[0].offset = 0; + layout->oobfree[0].length = mtd->oobsize; + + nand->ecc.layout = layout; + + /* + * Copy the device info into the per-device data. We can't just keep + * the pointer because that storage is reclaimed after initialization. + */ + this->device_info = *info; + this->device_info.description = kstrdup(info->description, GFP_KERNEL); + + /* Set up geometry. */ + error = mil_set_geometry(this); + if (error) + return -1; + + /* Set up timing. */ + timing.data_setup_in_ns = info->data_setup_in_ns; + timing.data_hold_in_ns = info->data_hold_in_ns; + timing.address_setup_in_ns = info->address_setup_in_ns; + timing.gpmi_sample_delay_in_ns = info->gpmi_sample_delay_in_ns; + timing.tREA_in_ns = info->tREA_in_ns; + timing.tRLOH_in_ns = info->tRLOH_in_ns; + timing.tRHOH_in_ns = info->tRHOH_in_ns; + + error = nfc->set_timing(this, &timing); + if (error) + return -1; + + if (nfc->extra_init) { + error = nfc->extra_init(this); + if (error != 0) + return -1; + } + + /* We only use 8-bit bus now, not 16-bit. */ + return 0; +} + +/** + * gpmi_nfc_mil_init() - Initializes the MTD Interface Layer. + * + * @this: Per-device data. + */ +int gpmi_nfc_mil_init(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + int error = 0; + + /* Initialize MIL data. */ + mil->current_chip = -1; + mil->command_length = 0; + + mil->page_buffer_virt = 0; + mil->page_buffer_phys = ~0; + mil->page_buffer_size = 0; + + /* Initialize the MTD data structures. */ + mtd->priv = nand; + mtd->name = "gpmi-nfc-main"; + mtd->owner = THIS_MODULE; + nand->priv = this; + + /* + * Signal Control + */ + nand->cmd_ctrl = mil_cmd_ctrl; + + /* + * Chip Control + * + * We rely on the reference implementations of: + * - cmdfunc + * - waitfunc + */ + nand->dev_ready = mil_dev_ready; + nand->select_chip = mil_select_chip; + + /* + * Low-level I/O + * + * We don't support a 16-bit NAND Flash bus, so we don't implement + * read_word. + * + * We rely on the reference implentation of verify_buf. + */ + nand->read_byte = mil_read_byte; + nand->read_buf = mil_read_buf; + nand->write_buf = mil_write_buf; + + /* + * ECC Control + * + * None of these functions are necessary for us: + * - ecc.hwctl + * - ecc.calculate + * - ecc.correct + */ + + /* + * ECC-aware I/O + * + * We rely on the reference implementations of: + * - ecc.read_page_raw + * - ecc.write_page_raw + */ + nand->ecc.read_page = mil_ecc_read_page; + nand->ecc.write_page = mil_ecc_write_page; + + /* + * High-level I/O + * + * We rely on the reference implementations of: + * - write_page + * - erase_cmd + */ + nand->ecc.read_oob = mil_ecc_read_oob; + nand->ecc.write_oob = mil_ecc_write_oob; + + /* + * Bad Block Management + * + * We rely on the reference implementations of: + * - block_bad + * - block_markbad + */ + nand->block_bad = mil_block_bad; + nand->scan_bbt = mil_scan_bbt; + nand->init_size = gpmi_init_size; + nand->badblock_pattern = &gpmi_bbt_descr; + + /* + * Error Recovery Functions + * + * We don't fill in the errstat function pointer because it's optional + * and we don't have a need for it. + */ + + /* + * Set up NAND Flash options. Specifically: + * + * - Disallow partial page writes. + */ + nand->options |= NAND_NO_SUBPAGE_WRITE; + + /* + * Tell the NAND Flash MTD system that we'll be handling ECC with our + * own hardware. It turns out that we still have to fill in the ECC size + * because the MTD code will divide by it -- even though it doesn't + * actually care. + */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = 1; + + /* Allocate a temporary DMA buffer for reading ID in the nand_scan() */ + this->nfc_geometry.payload_size_in_bytes = 1024; + this->nfc_geometry.auxiliary_size_in_bytes = 128; + error = mil_alloc_dma_buffer(this); + if (error) + goto exit_dma_allocation; + + /* + * Ask the NAND Flash system to scan for chips. + * + * This will fill in reference implementations for all the members of + * the MTD structures that we didn't set, and will make the medium fully + * usable. + */ + pr_info("Scanning for NAND Flash chips...\n"); + error = nand_scan(mtd, pdata->max_chip_count); + if (error) { + dev_err(dev, "Chip scan failed\n"); + goto exit_nand_scan; + } + + /* + * Hook some operations at the MTD level. See the descriptions of the + * saved function pointer fields for details about why we hook these. + */ + mil->hooked_block_markbad = mtd->block_markbad; + mtd->block_markbad = mil_hook_block_markbad; + + /* Construct partitions as necessary. */ + error = mil_partitions_init(this); + if (error) + goto exit_partitions; + + return 0; + +exit_partitions: + nand_release(&mil->mtd); +exit_nand_scan: + mil_free_dma_buffer(this); +exit_dma_allocation: + return error; +} + +/** + * gpmi_nfc_mil_exit() - Shuts down the MTD Interface Layer. + * + * @this: Per-device data. + */ +void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this) +{ + struct mil *mil = &this->mil; + + /* Shut down partitions as necessary. */ + mil_partitions_exit(this); + + /* Get MTD to let go of our MTD. */ + nand_release(&mil->mtd); + + /* Free all the DMA buffer, if it's been allocated. */ + mil_free_dma_buffer(this); +} diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c new file mode 100644 index 000000000000..0cd0b39141fd --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-common.c @@ -0,0 +1,59 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/** + * gpmi_nfc_rom_helper_set_geometry() - Sets geometry for the Boot ROM Helper. + * + * @this: Per-device data. + */ +int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this) +{ + struct boot_rom_geometry *geometry = &this->rom_geometry; + + /* + * Set the boot block stride size. + * + * In principle, we should be reading this from the OTP bits, since + * that's where the ROM is going to get it. In fact, we don't have any + * way to read the OTP bits, so we go with the default and hope for the + * best. + */ + + geometry->stride_size_in_pages = 64; + + /* + * Set the search area stride exponent. + * + * In principle, we should be reading this from the OTP bits, since + * that's where the ROM is going to get it. In fact, we don't have any + * way to read the OTP bits, so we go with the default and hope for the + * best. + */ + + geometry->search_area_stride_exponent = 2; + + /* Return success. */ + + return 0; + +} diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c new file mode 100644 index 000000000000..78f6a438125b --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v0.c @@ -0,0 +1,330 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/* + * Useful variables for Boot ROM Helper version 0. + */ + +static const char *fingerprint = "STMP"; + +/** + * set_geometry() - Sets geometry for the Boot ROM Helper. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct boot_rom_geometry *geometry = &this->rom_geometry; + struct nand_chip *nand = &this->mil.nand; + int error; + + /* Version-independent geometry. */ + error = gpmi_nfc_rom_helper_set_geometry(this); + if (error) + return error; + + /* + * Check if the platform data indicates we are to protect the boot area. + */ + if (!pdata->boot_area_size_in_bytes) { + geometry->boot_area_count = 0; + geometry->boot_area_size_in_bytes = 0; + return 0; + } + + /* + * If control arrives here, we are supposed to set up partitions to + * protect the boot areas. In this version of the ROM, the number of + * boot areas and their size depends on the number of chips. + */ + if (nand->numchips == 1) { + geometry->boot_area_count = 1; + geometry->boot_area_size_in_bytes = + pdata->boot_area_size_in_bytes * 2; + } else { + geometry->boot_area_count = 2; + geometry->boot_area_size_in_bytes = + pdata->boot_area_size_in_bytes; + } + return 0; +} + +/** + * check_transcription_stamp() - Checks for a transcription stamp. + * + * Returns 0 if a stamp is not found. + * + * @this: Per-device data. + */ +static int check_transcription_stamp(struct gpmi_nfc_data *this) +{ + struct boot_rom_geometry *rom_geo = &this->rom_geometry; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + unsigned int search_area_size_in_strides; + unsigned int stride; + unsigned int page; + loff_t byte; + uint8_t *buffer = nand->buffers->databuf; + int saved_chip_number; + int found_an_ncb_fingerprint = false; + + /* Compute the number of strides in a search area. */ + search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent; + + /* Select chip 0. */ + saved_chip_number = mil->current_chip; + nand->select_chip(mtd, 0); + + /* + * Loop through the first search area, looking for the NCB fingerprint. + */ + pr_info("Scanning for an NCB fingerprint...\n"); + + for (stride = 0; stride < search_area_size_in_strides; stride++) { + /* Compute the page and byte addresses. */ + page = stride * rom_geo->stride_size_in_pages; + byte = page * mtd->writesize; + + pr_info(" Looking for a fingerprint in page 0x%x\n", page); + + /* + * Read the NCB fingerprint. The fingerprint is four bytes long + * and starts in the 12th byte of the page. + */ + nand->cmdfunc(mtd, NAND_CMD_READ0, 12, page); + nand->read_buf(mtd, buffer, strlen(fingerprint)); + + /* Look for the fingerprint. */ + if (!memcmp(buffer, fingerprint, strlen(fingerprint))) { + found_an_ncb_fingerprint = true; + break; + } + + } + + /* Deselect chip 0. */ + nand->select_chip(mtd, saved_chip_number); + + if (found_an_ncb_fingerprint) + pr_info(" Found a fingerprint\n"); + else + pr_info(" No fingerprint found\n"); + return found_an_ncb_fingerprint; +} + +/** + * write_transcription_stamp() - Writes a transcription stamp. + * + * @this: Per-device data. + */ +static int write_transcription_stamp(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct boot_rom_geometry *rom_geo = &this->rom_geometry; + struct nand_device_info *info = &this->device_info; + struct mil *mil = &this->mil; + struct mtd_info *mtd = &mil->mtd; + struct nand_chip *nand = &mil->nand; + unsigned int block_size_in_pages; + unsigned int search_area_size_in_strides; + unsigned int search_area_size_in_pages; + unsigned int search_area_size_in_blocks; + unsigned int block; + unsigned int stride; + unsigned int page; + loff_t byte; + uint8_t *buffer = nand->buffers->databuf; + int saved_chip_number; + int status; + + /* Compute the search area geometry. */ + block_size_in_pages = info->block_size_in_pages; + search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent; + search_area_size_in_pages = search_area_size_in_strides * + rom_geo->stride_size_in_pages; + search_area_size_in_blocks = + (search_area_size_in_pages + (block_size_in_pages - 1)) / + block_size_in_pages; + + #if defined(DETAILED_INFO) + pr_info("--------------------\n"); + pr_info("Search Area Geometry\n"); + pr_info("--------------------\n"); + pr_info("Search Area Size in Blocks : %u", search_area_size_in_blocks); + pr_info("Search Area Size in Strides: %u", search_area_size_in_strides); + pr_info("Search Area Size in Pages : %u", search_area_size_in_pages); + #endif + + /* Select chip 0. */ + saved_chip_number = mil->current_chip; + nand->select_chip(mtd, 0); + + /* Loop over blocks in the first search area, erasing them. */ + pr_info("Erasing the search area...\n"); + + for (block = 0; block < search_area_size_in_blocks; block++) { + /* Compute the page address. */ + page = block * block_size_in_pages; + + /* Erase this block. */ + pr_info(" Erasing block 0x%x\n", block); + nand->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); + nand->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); + + /* Wait for the erase to finish. */ + status = nand->waitfunc(mtd, nand); + if (status & NAND_STATUS_FAIL) + dev_err(dev, "[%s] Erase failed.\n", __func__); + } + + /* Write the NCB fingerprint into the page buffer. */ + memset(buffer, ~0, mtd->writesize); + memset(nand->oob_poi, ~0, mtd->oobsize); + memcpy(buffer + 12, fingerprint, strlen(fingerprint)); + + /* Loop through the first search area, writing NCB fingerprints. */ + pr_info("Writing NCB fingerprints...\n"); + for (stride = 0; stride < search_area_size_in_strides; stride++) { + /* Compute the page and byte addresses. */ + page = stride * rom_geo->stride_size_in_pages; + byte = page * mtd->writesize; + + /* Write the first page of the current stride. */ + pr_info(" Writing an NCB fingerprint in page 0x%x\n", page); + nand->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + nand->ecc.write_page_raw(mtd, nand, buffer); + nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + + /* Wait for the write to finish. */ + status = nand->waitfunc(mtd, nand); + if (status & NAND_STATUS_FAIL) + dev_err(dev, "[%s] Write failed.\n", __func__); + } + + /* Deselect chip 0. */ + nand->select_chip(mtd, saved_chip_number); + return 0; +} + +static int imx23_rom_extra_init(struct gpmi_nfc_data *this) +{ + struct device *dev = this->dev; + struct mil *mil = &this->mil; + struct nand_chip *nand = &mil->nand; + struct mtd_info *mtd = &mil->mtd; + struct nand_device_info *info = &this->device_info; + unsigned int block_count; + unsigned int block; + int chip; + int page; + loff_t byte; + uint8_t block_mark; + int error = 0; + + /* + * If control arrives here, we can't use block mark swapping, which + * means we're forced to use transcription. First, scan for the + * transcription stamp. If we find it, then we don't have to do + * anything -- the block marks are already transcribed. + */ + if (check_transcription_stamp(this)) + return 0; + + /* + * If control arrives here, we couldn't find a transcription stamp, so + * so we presume the block marks are in the conventional location. + */ + pr_info("Transcribing bad block marks...\n"); + + /* Compute the number of blocks in the entire medium. */ + block_count = info->chip_size_in_bytes >> nand->phys_erase_shift; + + /* + * Loop over all the blocks in the medium, transcribing block marks as + * we go. + */ + for (block = 0; block < block_count; block++) { + /* + * Compute the chip, page and byte addresses for this block's + * conventional mark. + */ + chip = block >> (nand->chip_shift - nand->phys_erase_shift); + page = block << (nand->phys_erase_shift - nand->page_shift); + byte = block << nand->phys_erase_shift; + + /* Select the chip. */ + nand->select_chip(mtd, chip); + + /* Send the command to read the conventional block mark. */ + nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); + + /* Read the conventional block mark. */ + block_mark = nand->read_byte(mtd); + + /* + * Check if the block is marked bad. If so, we need to mark it + * again, but this time the result will be a mark in the + * location where we transcribe block marks. + * + * Notice that we have to explicitly set the marking_a_bad_block + * member before we call through the block_markbad function + * pointer in the owning struct nand_chip. If we could call + * though the block_markbad function pointer in the owning + * struct mtd_info, which we have hooked, then this would be + * taken care of for us. Unfortunately, we can't because that + * higher-level code path will do things like consulting the + * in-memory bad block table -- which doesn't even exist yet! + * So, we have to call at a lower level and handle some details + * ourselves. + */ + if (block_mark != 0xff) { + pr_info("Transcribing mark in block %u\n", block); + mil->marking_a_bad_block = true; + error = nand->block_markbad(mtd, byte); + mil->marking_a_bad_block = false; + if (error) + dev_err(dev, "Failed to mark block bad with " + "error %d\n", error); + } + + /* Deselect the chip. */ + nand->select_chip(mtd, -1); + } + + /* Write the stamp that indicates we've transcribed the block marks. */ + write_transcription_stamp(this); + return 0; +} + +/* This structure represents the Boot ROM Helper for this version. */ +struct boot_rom_helper gpmi_nfc_boot_rom_helper_v0 = { + .version = 0, + .description = "Single/dual-chip boot area, " + "no block mark swapping", + .swap_block_mark = false, + .set_geometry = set_geometry, + .rom_extra_init = imx23_rom_extra_init, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c new file mode 100644 index 000000000000..699dea8d9533 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-rom-v1.c @@ -0,0 +1,80 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gpmi-nfc.h" + +/** + * set_geometry() - Sets geometry for the Boot ROM Helper. + * + * @this: Per-device data. + */ +static int set_geometry(struct gpmi_nfc_data *this) +{ + struct gpmi_nfc_platform_data *pdata = this->pdata; + struct boot_rom_geometry *geometry = &this->rom_geometry; + int error; + + /* Version-independent geometry. */ + + error = gpmi_nfc_rom_helper_set_geometry(this); + + if (error) + return error; + + /* + * Check if the platform data indicates we are to protect the boot area. + */ + + if (!pdata->boot_area_size_in_bytes) { + geometry->boot_area_count = 0; + geometry->boot_area_size_in_bytes = 0; + return 0; + } + + /* + * If control arrives here, we are supposed to set up partitions to + * protect the boot areas. In this version of the ROM, we support only + * one boot area. + */ + + geometry->boot_area_count = 1; + + /* + * Use the platform's boot area size. + */ + + geometry->boot_area_size_in_bytes = pdata->boot_area_size_in_bytes; + + /* Return success. */ + + return 0; + +} + +/* This structure represents the Boot ROM Helper for this version. */ + +struct boot_rom_helper gpmi_nfc_boot_rom_helper_v1 = { + .version = 1, + .description = "Single-chip boot area, " + "block mark swapping supported", + .swap_block_mark = true, + .set_geometry = set_geometry, +}; diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h new file mode 100644 index 000000000000..3ba69d876b53 --- /dev/null +++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h @@ -0,0 +1,588 @@ +/* + * Freescale GPMI NFC NAND Flash Driver + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008 Embedded Alley Solutions, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H +#define __DRIVERS_MTD_NAND_GPMI_NFC_H + +/* Linux header files. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Platform header files. */ + +#include +#include +#include + +/* Driver header files. */ + +#include "../nand_device_info.h" + +/* + *------------------------------------------------------------------------------ + * Fundamental Macros + *------------------------------------------------------------------------------ + */ + +/* Define this macro to enable detailed information messages. */ + +#define DETAILED_INFO + +/* + *------------------------------------------------------------------------------ + * Fundamental Data Structures + *------------------------------------------------------------------------------ + */ + +/** + * struct resources - The collection of resources the driver needs. + * + * @gpmi_regs: A pointer to the GPMI registers. + * @bch_regs: A pointer to the BCH registers. + * @bch_interrupt: The BCH interrupt number. + * @dma_low_channel: The low DMA channel. + * @dma_high_channel: The high DMA channel. + * @dma_interrupt: The DMA interrupt number. + * @clock: A pointer to the struct clk for the NFC's clock. + */ + +struct resources { + void *gpmi_regs; + void *bch_regs; + unsigned int bch_low_interrupt; + unsigned int bch_high_interrupt; + unsigned int dma_low_channel; + unsigned int dma_high_channel; + unsigned int dma_low_interrupt; + unsigned int dma_high_interrupt; + struct clk *clock; +}; + +/** + * struct mil - State for the MTD Interface Layer. + * + * @nand: The NAND Flash MTD data structure that represents + * the NAND Flash medium. + * @mtd: The MTD data structure that represents the NAND + * Flash medium. + * @oob_layout: A structure that describes how bytes are laid out + * in the OOB. + * @general_use_mtd: A pointer to an MTD we export for general use. + * This *may* simply be a pointer to the mtd field, if + * we've been instructed NOT to protect the boot + * areas. + * @partitions: A pointer to a set of partitions applied to the + * general use MTD. + * @partition_count: The number of partitions. + * @ubi_partition_memory: If not NULL, a block of memory used to create a set + * of partitions that help with the problem that UBI + * can't handle an MTD larger than 2GiB. + * @current_chip: The chip currently selected by the NAND Fash MTD + * code. A negative value indicates that no chip is + * selected. + * @command_length: The length of the command that appears in the + * command buffer (see cmd_virt, below). + * @inject_ecc_error: Indicates the driver should inject a "fake" ECC + * error into the next read operation that uses ECC. + * User space programs can set this value through the + * sysfs node of the same name. If this value is less + * than zero, the driver will inject an uncorrectable + * ECC error. If this value is greater than zero, the + * driver will inject that number of correctable + * errors, capped by the maximum possible number of + * errors that could appear in a single read. + * @ignore_bad_block_marks: Indicates we are ignoring bad block marks. + * @saved_bbt: A saved pointer to the in-memory NAND Flash MTD bad + * block table. See show_device_ignorebad() for more + * details. + * @marking_a_bad_block: Indicates the caller is marking a bad block. See + * mil_ecc_write_oob() for details. + * @hooked_block_markbad: A pointer to the block_markbad() function we + * we "hooked." See mil_ecc_write_oob() for details. + * @cmd_virt: A pointer to a DMA-coherent buffer in which we + * accumulate command bytes before we give them to the + * NFC layer. See mil_cmd_ctrl() for more details. + * @cmd_phys: The physical address for the cmd_virt buffer. + * @page_buffer_virt: A pointer to a DMA-coherent buffer we use for + * reading and writing pages. This buffer includes + * space for both the payload data and the auxiliary + * data (including status bytes, but not syndrome + * bytes). + * @page_buffer_phys: The physical address for the page_buffer_virt + * buffer. + * @page_buffer_size: The size of the page buffer. + * @payload_virt: A pointer to a location in the page buffer used + * for payload bytes. The size of this buffer is + * determined by struct nfc_geometry. + * @payload_phys: The physical address for payload_virt. + * @payload_size: The size of the payload area in the page buffer. + * @auxiliary_virt: A pointer to a location in the page buffer used + * for auxiliary bytes. The size of this buffer is + * determined by struct nfc_geometry. + * @auxiliary_phys: The physical address for auxiliary_virt. + * @auxiliary_size: The size of the auxiliary area in the page buffer. + */ + +#define MIL_COMMAND_BUFFER_SIZE (10) + +struct mil { + + /* MTD Data Structures */ + + struct nand_chip nand; + struct mtd_info mtd; + struct nand_ecclayout oob_layout; + + /* Partitioning and Boot Area Protection */ + + struct mtd_info *general_use_mtd; + struct mtd_partition *partitions; + unsigned int partition_count; + void *ubi_partition_memory; + + /* General-use Variables */ + + int current_chip; + unsigned int command_length; + int inject_ecc_error; + int ignore_bad_block_marks; + void *saved_bbt; + + /* MTD Function Pointer Hooks */ + int marking_a_bad_block; + int (*hooked_block_markbad)(struct mtd_info *mtd, + loff_t ofs); + + /* DMA Buffers */ + + char *cmd_virt; + dma_addr_t cmd_phys; + + void *page_buffer_virt; + dma_addr_t page_buffer_phys; + unsigned int page_buffer_size; + + void *payload_virt; + dma_addr_t payload_phys; + + void *auxiliary_virt; + dma_addr_t auxiliary_phys; + +}; + +/** + * struct nfc_geometry - NFC geometry description. + * + * This structure describes the NFC's view of the medium geometry. + * + * @ecc_algorithm: The human-readable name of the ECC algorithm + * (e.g., "Reed-Solomon" or "BCH"). + * @ecc_strength: A number that describes the strength of the ECC + * algorithm. + * @page_size_in_bytes: The size, in bytes, of a physical page, including + * both data and OOB. + * @metadata_size_in_bytes: The size, in bytes, of the metadata. + * @ecc_chunk_size_in_bytes: The size, in bytes, of a single ECC chunk. Note + * the first chunk in the page includes both data and + * metadata, so it's a bit larger than this value. + * @ecc_chunk_count: The number of ECC chunks in the page, + * @payload_size_in_bytes: The size, in bytes, of the payload buffer. + * @auxiliary_size_in_bytes: The size, in bytes, of the auxiliary buffer. + * @auxiliary_status_offset: The offset into the auxiliary buffer at which + * the ECC status appears. + * @block_mark_byte_offset: The byte offset in the ECC-based page view at + * which the underlying physical block mark appears. + * @block_mark_bit_offset: The bit offset into the ECC-based page view at + * which the underlying physical block mark appears. + */ + +struct nfc_geometry { + char *ecc_algorithm; + unsigned int ecc_strength; + unsigned int page_size_in_bytes; + unsigned int metadata_size_in_bytes; + unsigned int ecc_chunk_size_in_bytes; + unsigned int ecc_chunk_count; + unsigned int payload_size_in_bytes; + unsigned int auxiliary_size_in_bytes; + unsigned int auxiliary_status_offset; + unsigned int block_mark_byte_offset; + unsigned int block_mark_bit_offset; +}; + +/** + * struct boot_rom_geometry - Boot ROM geometry description. + * + * This structure encapsulates decisions made by the Boot ROM Helper. + * + * @boot_area_count: The number of boot areas. The first boot area + * appears at the beginning of chip 0, the next + * at the beginning of chip 1, etc. + * @boot_area_size_in_bytes: The size, in bytes, of each boot area. + * @stride_size_in_pages: The size of a boot block stride, in pages. + * @search_area_stride_exponent: The logarithm to base 2 of the size of a + * search area in boot block strides. + */ + +struct boot_rom_geometry { + unsigned int boot_area_count; + unsigned int boot_area_size_in_bytes; + unsigned int stride_size_in_pages; + unsigned int search_area_stride_exponent; +}; + +/** + * struct gpmi_nfc_data - i.MX NFC per-device data. + * + * Note that the "device" managed by this driver represents the NAND Flash + * controller *and* the NAND Flash medium behind it. Thus, the per-device data + * structure has information about the controller, the chips to which it is + * connected, and properties of the medium as a whole. + * + * @dev: A pointer to the owning struct device. + * @pdev: A pointer to the owning struct platform_device. + * @pdata: A pointer to the device's platform data. + * @resources: Information about system resources used by this driver. + * @device_info: A structure that contains detailed information about + * the NAND Flash device. + * @nfc: A pointer to a structure that represents the underlying + * NFC hardware. + * @nfc_geometry: A description of the medium geometry as viewed by the + * NFC. + * @rom: A pointer to a structure that represents the underlying + * Boot ROM. + * @rom_geometry: A description of the medium geometry as viewed by the + * Boot ROM. + * @mil: A collection of information used by the MTD Interface + * Layer. + */ + +struct gpmi_nfc_data { + + /* System Interface */ + struct device *dev; + struct platform_device *pdev; + struct gpmi_nfc_platform_data *pdata; + + /* Resources */ + struct resources resources; + + /* Flash Hardware */ + struct nand_device_info device_info; + + /* NFC HAL */ + struct nfc_hal *nfc; + struct nfc_geometry nfc_geometry; + + /* Boot ROM Helper */ + struct boot_rom_helper *rom; + struct boot_rom_geometry rom_geometry; + + /* MTD Interface Layer */ + struct mil mil; + +}; + +/** + * struct gpmi_nfc_timing - GPMI NFC timing parameters. + * + * This structure contains the fundamental timing attributes for the NAND Flash + * bus and the GPMI NFC hardware. + * + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the + * maximum of tDS and tWP. A negative value + * indicates this characteristic isn't known. + * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the + * maximum of tDH, tWH and tREH. A negative value + * indicates this characteristic isn't known. + * @address_setup_in_ns: The address setup time, in nanoseconds. Usually + * the maximum of tCLS, tCS and tALS. A negative + * value indicates this characteristic isn't known. + * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value + * indicates this characteristic isn't known. + * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic isn't + * known. + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic isn't + * known. + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic isn't + * known. + */ + +struct gpmi_nfc_timing { + int8_t data_setup_in_ns; + int8_t data_hold_in_ns; + int8_t address_setup_in_ns; + int8_t gpmi_sample_delay_in_ns; + int8_t tREA_in_ns; + int8_t tRLOH_in_ns; + int8_t tRHOH_in_ns; +}; + +/** + * struct gpmi_nfc_hardware_timing - GPMI NFC hardware timing parameters. + * + * This structure contains timing information expressed in a form directly + * usable by the GPMI NFC hardware. + * + * @data_setup_in_cycles: The data setup time, in cycles. + * @data_hold_in_cycles: The data hold time, in cycles. + * @address_setup_in_cycles: The address setup time, in cycles. + * @use_half_periods: Indicates the clock is running slowly, so the + * NFC DLL should use half-periods. + * @sample_delay_factor: The sample delay factor. + */ + +struct gpmi_nfc_hardware_timing { + uint8_t data_setup_in_cycles; + uint8_t data_hold_in_cycles; + uint8_t address_setup_in_cycles; + bool use_half_periods; + uint8_t sample_delay_factor; +}; + +/** + * struct nfc_hal - GPMI NFC HAL + * + * This structure embodies an abstract interface to the underlying NFC hardware. + * + * @version: The NFC hardware version. + * @description: A pointer to a human-readable description of + * the NFC hardware. + * @max_chip_count: The maximum number of chips the NFC can + * possibly support (this value is a constant for + * each NFC version). This may *not* be the actual + * number of chips connected. + * @max_data_setup_cycles: The maximum number of data setup cycles that + * can be expressed in the hardware. + * @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires + * for data read internal setup. In the Reference + * Manual, see the chapter "High-Speed NAND + * Timing" for more details. + * @max_sample_delay_factor: The maximum sample delay factor that can be + * expressed in the hardware. + * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the + * sample delay DLL hardware can possibly work + * with (the DLL is unusable with longer periods). + * If the full-cycle period is greater than HALF + * this value, the DLL must be configured to use + * half-periods. + * @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the + * DLL can implement. + * @dma_descriptors: A pool of DMA descriptors. + * @isr_dma_channel: The DMA channel with which the NFC HAL is + * working. We record this here so the ISR knows + * which DMA channel to acknowledge. + * @dma_done: The completion structure used for DMA + * interrupts. + * @bch_done: The completion structure used for BCH + * interrupts. + * @timing: The current timing configuration. + * @clock_frequency_in_hz: The clock frequency, in Hz, during the current + * I/O transaction. If no I/O transaction is in + * progress, this is the clock frequency during + * the most recent I/O transaction. + * @hardware_timing: The hardware timing configuration in effect + * during the current I/O transaction. If no I/O + * transaction is in progress, this is the + * hardware timing configuration during the most + * recent I/O transaction. + * @init: Initializes the NFC hardware and data + * structures. This function will be called after + * everything has been set up for communication + * with the NFC itself, but before the platform + * has set up off-chip communication. Thus, this + * function must not attempt to communicate with + * the NAND Flash hardware. + * @set_geometry: Configures the NFC hardware and data structures + * to match the physical NAND Flash geometry. + * @set_geometry: Configures the NFC hardware and data structures + * to match the physical NAND Flash geometry. + * @set_timing: Configures the NFC hardware and data structures + * to match the given NAND Flash bus timing. + * @get_timing: Returns the the clock frequency, in Hz, and + * the hardware timing configuration during the + * current I/O transaction. If no I/O transaction + * is in progress, this is the timing state during + * the most recent I/O transaction. + * @exit: Shuts down the NFC hardware and data + * structures. This function will be called after + * the platform has shut down off-chip + * communication but while communication with the + * NFC itself still works. + * @clear_bch: Clears a BCH interrupt (intended to be called + * by a more general interrupt handler to do + * device-specific clearing). + * @is_ready: Returns true if the given chip is ready. + * @begin: Begins an interaction with the NFC. This + * function must be called before *any* of the + * following functions so the NFC can prepare + * itself. + * @end: Ends interaction with the NFC. This function + * should be called to give the NFC a chance to, + * among other things, enter a lower-power state. + * @send_command: Sends the given buffer of command bytes. + * @send_data: Sends the given buffer of data bytes. + * @read_data: Reads data bytes into the given buffer. + * @send_page: Sends the given given data and OOB bytes, + * using the ECC engine. + * @read_page: Reads a page through the ECC engine and + * delivers the data and OOB bytes to the given + * buffers. + */ + +#define NFC_DMA_DESCRIPTOR_COUNT (4) + +struct nfc_hal { + + /* Hardware attributes. */ + + const unsigned int version; + const char *description; + const unsigned int max_chip_count; + const unsigned int max_data_setup_cycles; + const unsigned int internal_data_setup_in_ns; + const unsigned int max_sample_delay_factor; + const unsigned int max_dll_clock_period_in_ns; + const unsigned int max_dll_delay_in_ns; + + /* Working variables. */ + + struct mxs_dma_desc *dma_descriptors[NFC_DMA_DESCRIPTOR_COUNT]; + int isr_dma_channel; + struct completion dma_done; + struct completion bch_done; + struct gpmi_nfc_timing timing; + unsigned long clock_frequency_in_hz; + + /* Configuration functions. */ + + int (*init) (struct gpmi_nfc_data *); + int (*extra_init) (struct gpmi_nfc_data *); + int (*set_geometry)(struct gpmi_nfc_data *); + int (*set_timing) (struct gpmi_nfc_data *, + const struct gpmi_nfc_timing *); + void (*get_timing) (struct gpmi_nfc_data *, + unsigned long *clock_frequency_in_hz, + struct gpmi_nfc_hardware_timing *); + void (*exit) (struct gpmi_nfc_data *); + + /* Call these functions to begin and end I/O. */ + + void (*begin) (struct gpmi_nfc_data *); + void (*end) (struct gpmi_nfc_data *); + + /* Call these I/O functions only between begin() and end(). */ + + void (*clear_bch) (struct gpmi_nfc_data *); + int (*is_ready) (struct gpmi_nfc_data *, unsigned chip); + int (*send_command)(struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*send_data) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*read_data) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t buffer, unsigned length); + int (*send_page) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary); + int (*read_page) (struct gpmi_nfc_data *, unsigned chip, + dma_addr_t payload, dma_addr_t auxiliary); +}; + +/** + * struct boot_rom_helper - Boot ROM Helper + * + * This structure embodies the interface to an object that assists the driver + * in making decisions that relate to the Boot ROM. + * + * @version: The Boot ROM version. + * @description: A pointer to a human-readable description of the + * Boot ROM. + * @swap_block_mark: Indicates that the Boot ROM will swap the block + * mark with the first byte of the OOB. + * @set_geometry: Configures the Boot ROM geometry. + * @rom_extra_init: Arch-specific init. + */ + +struct boot_rom_helper { + const unsigned int version; + const char *description; + const int swap_block_mark; + int (*set_geometry) (struct gpmi_nfc_data *); + int (*rom_extra_init) (struct gpmi_nfc_data *); +}; + +/* + *------------------------------------------------------------------------------ + * External Symbols + *------------------------------------------------------------------------------ + */ + +/* NFC HAL Common Services */ + +extern irqreturn_t gpmi_nfc_bch_isr(int irq, void *cookie); +extern irqreturn_t gpmi_nfc_dma_isr(int irq, void *cookie); +extern int gpmi_nfc_dma_init(struct gpmi_nfc_data *this); +extern void gpmi_nfc_dma_exit(struct gpmi_nfc_data *this); +extern int gpmi_nfc_set_geometry(struct gpmi_nfc_data *this); +extern int gpmi_nfc_dma_go(struct gpmi_nfc_data *this, int dma_channel); +extern int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this, + struct gpmi_nfc_hardware_timing *hw); +extern int start_dma_with_bch_irq(struct gpmi_nfc_data *this, int dma_channel); +extern int start_dma_without_bch_irq(struct gpmi_nfc_data *this, + int dma_channel); + +/* NFC HAL Structures */ + +extern struct nfc_hal gpmi_nfc_hal_v0; +extern struct nfc_hal gpmi_nfc_hal_v1; +extern struct nfc_hal gpmi_nfc_hal_v2; + +/* Boot ROM Helper Common Services */ + +extern int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this); + +/* Boot ROM Helper Structures */ + +extern struct boot_rom_helper gpmi_nfc_boot_rom_helper_v0; +extern struct boot_rom_helper gpmi_nfc_boot_rom_helper_v1; + +/* MTD Interface Layer */ + +extern int gpmi_nfc_mil_init(struct gpmi_nfc_data *this); +extern void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this); + +#endif diff --git a/drivers/mtd/nand/imx_nfc.c b/drivers/mtd/nand/imx_nfc.c new file mode 100644 index 000000000000..065ff338b06d --- /dev/null +++ b/drivers/mtd/nand/imx_nfc.c @@ -0,0 +1,8286 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_VERSION "1.0" + +/* Define this macro to enable event reporting. */ + +#define EVENT_REPORTING + +/* + * For detailed information that will be helpful in understanding this driver, + * see: + * + * Documentation/imx_nfc.txt + */ + +/* + * Macros that describe NFC hardware have names of the form: + * + * NFC_* + * + * Macros that apply only to specific versions of the NFC have names of the + * following form: + * + * NFC___* + * + * where: + * + * is the major version of the NFC hardware. + * is the minor version of the NFC hardware. + * + * The minor version can be 'X', which means that the macro applies to *all* + * NFCs of the same major version. + * + * For NFC versions with only one set of registers, macros that give offsets + * against the base address have names of the form: + * + * *_REG_OFF + * + * Macros that give the position of a field's LSB within a given register have + * names of the form: + * + * *__POS + * + * Macros that mask a field within a given register have names of the form: + * + * *__MSK + */ + +/* + * Macro definitions for ALL NFC versions. + */ + +#define NFC_MAIN_BUF_SIZE (512) + +/* + * Macro definitions for version 1.0 NFCs. + */ + +#define NFC_1_0_BUF_SIZE_REG_OFF (0x00) +#define NFC_1_0_BUF_ADDR_REG_OFF (0x04) +#define NFC_1_0_FLASH_ADDR_REG_OFF (0x06) +#define NFC_1_0_FLASH_CMD_REG_OFF (0x08) +#define NFC_1_0_CONFIG_REG_OFF (0x0A) +#define NFC_1_0_ECC_STATUS_RESULT_REG_OFF (0x0C) +#define NFC_1_0_RSLTMAIN_AREA_REG_OFF (0x0E) +#define NFC_1_0_RSLTSPARE_AREA_REG_OFF (0x10) +#define NFC_1_0_WRPROT_REG_OFF (0x12) +#define NFC_1_0_UNLOCKSTART_BLKADDR_REG_OFF (0x14) +#define NFC_1_0_UNLOCKEND_BLKADDR_REG_OFF (0x16) +#define NFC_1_0_NF_WRPRST_REG_OFF (0x18) + +#define NFC_1_0_CONFIG1_REG_OFF (0x1A) +#define NFC_1_0_CONFIG1_NF_CE_POS (7) +#define NFC_1_0_CONFIG1_NF_CE_MSK (0x1 << 7) + +#define NFC_1_0_CONFIG2_REG_OFF (0x1C) + +/* +* Macro definitions for version 2.X NFCs. +*/ + +#define NFC_2_X_FLASH_ADDR_REG_OFF (0x06) +#define NFC_2_X_FLASH_CMD_REG_OFF (0x08) +#define NFC_2_X_CONFIG_REG_OFF (0x0A) + +#define NFC_2_X_WR_PROT_REG_OFF (0x12) + +#define NFC_2_X_NF_WR_PR_ST_REG_OFF (0x18) + +#define NFC_2_X_CONFIG2_REG_OFF (0x1C) +#define NFC_2_X_CONFIG2_FCMD_POS (0) +#define NFC_2_X_CONFIG2_FCMD_MSK (0x1 << 0) +#define NFC_2_X_CONFIG2_FADD_POS (1) +#define NFC_2_X_CONFIG2_FADD_MSK (0x1 << 1) +#define NFC_2_X_CONFIG2_FDI_POS (2) +#define NFC_2_X_CONFIG2_FDI_MSK (0x1 << 2) +#define NFC_2_X_CONFIG2_FDO_POS (3) +#define NFC_2_X_CONFIG2_FDO_MSK (0x7 << 3) +#define NFC_2_X_CONFIG2_INT_POS (15) +#define NFC_2_X_CONFIG2_INT_MSK (0x1 << 15) + +/* +* Macro definitions for version 2.0 NFCs. +*/ + +#define NFC_2_0_BUF_ADDR_REG_OFF (0x04) +#define NFC_2_0_BUF_ADDR_RBA_POS (0) +#define NFC_2_0_BUF_ADDR_RBA_MSK (0xf << 0) + +#define NFC_2_0_ECC_STATUS_REG_OFF (0x0C) +#define NFC_2_0_ECC_STATUS_NOSER1_POS (0) +#define NFC_2_0_ECC_STATUS_NOSER1_MSK (0xF << 0) +#define NFC_2_0_ECC_STATUS_NOSER2_POS (4) +#define NFC_2_0_ECC_STATUS_NOSER2_MSK (0xF << 4) +#define NFC_2_0_ECC_STATUS_NOSER3_POS (8) +#define NFC_2_0_ECC_STATUS_NOSER3_MSK (0xF << 8) +#define NFC_2_0_ECC_STATUS_NOSER4_POS (12) +#define NFC_2_0_ECC_STATUS_NOSER4_MSK (0xF << 12) + +#define NFC_2_0_CONFIG1_REG_OFF (0x1A) +#define NFC_2_0_CONFIG1_SP_EN_POS (2) +#define NFC_2_0_CONFIG1_SP_EN_MSK (0x1 << 2) +#define NFC_2_0_CONFIG1_ECC_EN_POS (3) +#define NFC_2_0_CONFIG1_ECC_EN_MSK (0x1 << 3) +#define NFC_2_0_CONFIG1_INT_MSK_POS (4) +#define NFC_2_0_CONFIG1_INT_MSK_MSK (0x1 << 4) +#define NFC_2_0_CONFIG1_NF_BIG_POS (5) +#define NFC_2_0_CONFIG1_NF_BIG_MSK (0x1 << 5) +#define NFC_2_0_CONFIG1_NFC_RST_POS (6) +#define NFC_2_0_CONFIG1_NFC_RST_MSK (0x1 << 6) +#define NFC_2_0_CONFIG1_NF_CE_POS (7) +#define NFC_2_0_CONFIG1_NF_CE_MSK (0x1 << 7) +#define NFC_2_0_CONFIG1_ONE_CYLE_POS (8) +#define NFC_2_0_CONFIG1_ONE_CYLE_MSK (0x1 << 8) +#define NFC_2_0_CONFIG1_MLC_POS (9) +#define NFC_2_0_CONFIG1_MLC_MSK (0x1 << 9) + +#define NFC_2_0_UNLOCK_START_REG_OFF (0x14) +#define NFC_2_0_UNLOCK_END_REG_OFF (0x16) + +/* +* Macro definitions for version 2.1 NFCs. +*/ + +#define NFC_2_1_BUF_ADDR_REG_OFF (0x04) +#define NFC_2_1_BUF_ADDR_RBA_POS (0) +#define NFC_2_1_BUF_ADDR_RBA_MSK (0x7 << 0) +#define NFC_2_1_BUF_ADDR_CS_POS (4) +#define NFC_2_1_BUF_ADDR_CS_MSK (0x3 << 4) + +#define NFC_2_1_ECC_STATUS_REG_OFF (0x0C) +#define NFC_2_1_ECC_STATUS_NOSER1_POS (0) +#define NFC_2_1_ECC_STATUS_NOSER1_MSK (0xF << 0) +#define NFC_2_1_ECC_STATUS_NOSER2_POS (4) +#define NFC_2_1_ECC_STATUS_NOSER2_MSK (0xF << 4) +#define NFC_2_1_ECC_STATUS_NOSER3_POS (8) +#define NFC_2_1_ECC_STATUS_NOSER3_MSK (0xF << 8) +#define NFC_2_1_ECC_STATUS_NOSER4_POS (12) +#define NFC_2_1_ECC_STATUS_NOSER4_MSK (0xF << 12) + +#define NFC_2_1_CONFIG1_REG_OFF (0x1A) +#define NFC_2_1_CONFIG1_ECC_MODE_POS (0) +#define NFC_2_1_CONFIG1_ECC_MODE_MSK (0x1 << 0) +#define NFC_2_1_CONFIG1_DMA_MODE_POS (1) +#define NFC_2_1_CONFIG1_DMA_MODE_MSK (0x1 << 1) +#define NFC_2_1_CONFIG1_SP_EN_POS (2) +#define NFC_2_1_CONFIG1_SP_EN_MSK (0x1 << 2) +#define NFC_2_1_CONFIG1_ECC_EN_POS (3) +#define NFC_2_1_CONFIG1_ECC_EN_MSK (0x1 << 3) +#define NFC_2_1_CONFIG1_INT_MSK_POS (4) +#define NFC_2_1_CONFIG1_INT_MSK_MSK (0x1 << 4) +#define NFC_2_1_CONFIG1_NF_BIG_POS (5) +#define NFC_2_1_CONFIG1_NF_BIG_MSK (0x1 << 5) +#define NFC_2_1_CONFIG1_NFC_RST_POS (6) +#define NFC_2_1_CONFIG1_NFC_RST_MSK (0x1 << 6) +#define NFC_2_1_CONFIG1_NF_CE_POS (7) +#define NFC_2_1_CONFIG1_NF_CE_MSK (0x1 << 7) +#define NFC_2_1_CONFIG1_SYM_POS (8) +#define NFC_2_1_CONFIG1_SYM_MSK (0x1 << 8) +#define NFC_2_1_CONFIG1_PPB_POS (9) +#define NFC_2_1_CONFIG1_PPB_MSK (0x3 << 9) +#define NFC_2_1_CONFIG1_FP_INT_POS (11) +#define NFC_2_1_CONFIG1_FP_INT_MSK (0x1 << 11) + +#define NFC_2_1_UNLOCK_START_0_REG_OFF (0x20) +#define NFC_2_1_UNLOCK_END_0_REG_OFF (0x22) +#define NFC_2_1_UNLOCK_START_1_REG_OFF (0x24) +#define NFC_2_1_UNLOCK_END_1_REG_OFF (0x26) +#define NFC_2_1_UNLOCK_START_2_REG_OFF (0x28) +#define NFC_2_1_UNLOCK_END_2_REG_OFF (0x2A) +#define NFC_2_1_UNLOCK_START_3_REG_OFF (0x2C) +#define NFC_2_1_UNLOCK_END_3_REG_OFF (0x2E) + +/* +* Macro definitions for version 3.X NFCs. +*/ + +/* +* Macro definitions for version 3.1 NFCs. +*/ + +#define NFC_3_1_FLASH_ADDR_CMD_REG_OFF (0x00) +#define NFC_3_1_CONFIG1_REG_OFF (0x04) +#define NFC_3_1_ECC_STATUS_RESULT_REG_OFF (0x08) +#define NFC_3_1_LAUNCH_NFC_REG_OFF (0x0C) + +#define NFC_3_1_WRPROT_REG_OFF (0x00) +#define NFC_3_1_WRPROT_UNLOCK_BLK_ADD0_REG_OFF (0x04) +#define NFC_3_1_CONFIG2_REG_OFF (0x14) +#define NFC_3_1_IPC_REG_OFF (0x18) + +/* +* Macro definitions for version 3.2 NFCs. +*/ + +#define NFC_3_2_CMD_REG_OFF (0x00) + +#define NFC_3_2_ADD0_REG_OFF (0x04) +#define NFC_3_2_ADD1_REG_OFF (0x08) +#define NFC_3_2_ADD2_REG_OFF (0x0C) +#define NFC_3_2_ADD3_REG_OFF (0x10) +#define NFC_3_2_ADD4_REG_OFF (0x14) +#define NFC_3_2_ADD5_REG_OFF (0x18) +#define NFC_3_2_ADD6_REG_OFF (0x1C) +#define NFC_3_2_ADD7_REG_OFF (0x20) +#define NFC_3_2_ADD8_REG_OFF (0x24) +#define NFC_3_2_ADD9_REG_OFF (0x28) +#define NFC_3_2_ADD10_REG_OFF (0x2C) +#define NFC_3_2_ADD11_REG_OFF (0x30) + +#define NFC_3_2_CONFIG1_REG_OFF (0x34) +#define NFC_3_2_CONFIG1_SP_EN_POS (0) +#define NFC_3_2_CONFIG1_SP_EN_MSK (0x1 << 0) +#define NFC_3_2_CONFIG1_NF_CE_POS (1) +#define NFC_3_2_CONFIG1_NF_CE_MSK (0x1 << 1) +#define NFC_3_2_CONFIG1_RST_POS (2) +#define NFC_3_2_CONFIG1_RST_MSK (0x1 << 2) +#define NFC_3_2_CONFIG1_RBA_POS (4) +#define NFC_3_2_CONFIG1_RBA_MSK (0x7 << 4) +#define NFC_3_2_CONFIG1_ITER_POS (8) +#define NFC_3_2_CONFIG1_ITER_MSK (0xf << 8) +#define NFC_3_2_CONFIG1_CS_POS (12) +#define NFC_3_2_CONFIG1_CS_MSK (0x7 << 12) +#define NFC_3_2_CONFIG1_STATUS_POS (16) +#define NFC_3_2_CONFIG1_STATUS_MSK (0xFFFF<<16) + +#define NFC_3_2_ECC_STATUS_REG_OFF (0x38) +#define NFC_3_2_ECC_STATUS_NOBER1_POS (0) +#define NFC_3_2_ECC_STATUS_NOBER1_MSK (0xF << 0) +#define NFC_3_2_ECC_STATUS_NOBER2_POS (4) +#define NFC_3_2_ECC_STATUS_NOBER2_MSK (0xF << 4) +#define NFC_3_2_ECC_STATUS_NOBER3_POS (8) +#define NFC_3_2_ECC_STATUS_NOBER3_MSK (0xF << 8) +#define NFC_3_2_ECC_STATUS_NOBER4_POS (12) +#define NFC_3_2_ECC_STATUS_NOBER4_MSK (0xF << 12) +#define NFC_3_2_ECC_STATUS_NOBER5_POS (16) +#define NFC_3_2_ECC_STATUS_NOBER5_MSK (0xF << 16) +#define NFC_3_2_ECC_STATUS_NOBER6_POS (20) +#define NFC_3_2_ECC_STATUS_NOBER6_MSK (0xF << 20) +#define NFC_3_2_ECC_STATUS_NOBER7_POS (24) +#define NFC_3_2_ECC_STATUS_NOBER7_MSK (0xF << 24) +#define NFC_3_2_ECC_STATUS_NOBER8_POS (28) +#define NFC_3_2_ECC_STATUS_NOBER8_MSK (0xF << 28) + + +#define NFC_3_2_STATUS_SUM_REG_OFF (0x3C) +#define NFC_3_2_STATUS_SUM_NAND_SUM_POS (0x0) +#define NFC_3_2_STATUS_SUM_NAND_SUM_MSK (0xFF << 0) +#define NFC_3_2_STATUS_SUM_ECC_SUM_POS (8) +#define NFC_3_2_STATUS_SUM_ECC_SUM_MSK (0xFF << 8) + +#define NFC_3_2_LAUNCH_REG_OFF (0x40) +#define NFC_3_2_LAUNCH_FCMD_POS (0) +#define NFC_3_2_LAUNCH_FCMD_MSK (0x1 << 0) +#define NFC_3_2_LAUNCH_FADD_POS (1) +#define NFC_3_2_LAUNCH_FADD_MSK (0x1 << 1) +#define NFC_3_2_LAUNCH_FDI_POS (2) +#define NFC_3_2_LAUNCH_FDI_MSK (0x1 << 2) +#define NFC_3_2_LAUNCH_FDO_POS (3) +#define NFC_3_2_LAUNCH_FDO_MSK (0x7 << 3) +#define NFC_3_2_LAUNCH_AUTO_PROG_POS (6) +#define NFC_3_2_LAUNCH_AUTO_PROG_MSK (0x1 << 6) +#define NFC_3_2_LAUNCH_AUTO_READ_POS (7) +#define NFC_3_2_LAUNCH_AUTO_READ_MSK (0x1 << 7) +#define NFC_3_2_LAUNCH_AUTO_ERASE_POS (9) +#define NFC_3_2_LAUNCH_AUTO_ERASE_MSK (0x1 << 9) +#define NFC_3_2_LAUNCH_COPY_BACK0_POS (10) +#define NFC_3_2_LAUNCH_COPY_BACK0_MSK (0x1 << 10) +#define NFC_3_2_LAUNCH_COPY_BACK1_POS (11) +#define NFC_3_2_LAUNCH_COPY_BACK1_MSK (0x1 << 11) +#define NFC_3_2_LAUNCH_AUTO_STATUS_POS (12) +#define NFC_3_2_LAUNCH_AUTO_STATUS_MSK (0x1 << 12) + +#define NFC_3_2_WRPROT_REG_OFF (0x00) +#define NFC_3_2_WRPROT_WPC_POS (0) +#define NFC_3_2_WRPROT_WPC_MSK (0x7 << 0) +#define NFC_3_2_WRPROT_CS2L_POS (3) +#define NFC_3_2_WRPROT_CS2L_MSK (0x7 << 3) +#define NFC_3_2_WRPROT_BLS_POS (6) +#define NFC_3_2_WRPROT_BLS_MSK (0x3 << 6) +#define NFC_3_2_WRPROT_LTS0_POS (8) +#define NFC_3_2_WRPROT_LTS0_MSK (0x1 << 8) +#define NFC_3_2_WRPROT_LS0_POS (9) +#define NFC_3_2_WRPROT_LS0_MSK (0x1 << 9) +#define NFC_3_2_WRPROT_US0_POS (10) +#define NFC_3_2_WRPROT_US0_MSK (0x1 << 10) +#define NFC_3_2_WRPROT_LTS1_POS (11) +#define NFC_3_2_WRPROT_LTS1_MSK (0x1 << 11) +#define NFC_3_2_WRPROT_LS1_POS (12) +#define NFC_3_2_WRPROT_LS1_MSK (0x1 << 12) +#define NFC_3_2_WRPROT_US1_POS (13) +#define NFC_3_2_WRPROT_US1_MSK (0x1 << 13) +#define NFC_3_2_WRPROT_LTS2_POS (14) +#define NFC_3_2_WRPROT_LTS2_MSK (0x1 << 14) +#define NFC_3_2_WRPROT_LS2_POS (15) +#define NFC_3_2_WRPROT_LS2_MSK (0x1 << 15) +#define NFC_3_2_WRPROT_US2_POS (16) +#define NFC_3_2_WRPROT_US2_MSK (0x1 << 16) +#define NFC_3_2_WRPROT_LTS3_POS (17) +#define NFC_3_2_WRPROT_LTS3_MSK (0x1 << 17) +#define NFC_3_2_WRPROT_LS3_POS (18) +#define NFC_3_2_WRPROT_LS3_MSK (0x1 << 18) +#define NFC_3_2_WRPROT_US3_POS (19) +#define NFC_3_2_WRPROT_US3_MSK (0x1 << 19) +#define NFC_3_2_WRPROT_LTS4_POS (20) +#define NFC_3_2_WRPROT_LTS4_MSK (0x1 << 20) +#define NFC_3_2_WRPROT_LS4_POS (21) +#define NFC_3_2_WRPROT_LS4_MSK (0x1 << 21) +#define NFC_3_2_WRPROT_US4_POS (22) +#define NFC_3_2_WRPROT_US4_MSK (0x1 << 22) +#define NFC_3_2_WRPROT_LTS5_POS (23) +#define NFC_3_2_WRPROT_LTS5_MSK (0x1 << 23) +#define NFC_3_2_WRPROT_LS5_POS (24) +#define NFC_3_2_WRPROT_LS5_MSK (0x1 << 24) +#define NFC_3_2_WRPROT_US5_POS (25) +#define NFC_3_2_WRPROT_US5_MSK (0x1 << 25) +#define NFC_3_2_WRPROT_LTS6_POS (26) +#define NFC_3_2_WRPROT_LTS6_MSK (0x1 << 26) +#define NFC_3_2_WRPROT_LS6_POS (27) +#define NFC_3_2_WRPROT_LS6_MSK (0x1 << 27) +#define NFC_3_2_WRPROT_US6_POS (28) +#define NFC_3_2_WRPROT_US6_MSK (0x1 << 28) +#define NFC_3_2_WRPROT_LTS7_POS (29) +#define NFC_3_2_WRPROT_LTS7_MSK (0x1 << 29) +#define NFC_3_2_WRPROT_LS7_POS (30) +#define NFC_3_2_WRPROT_LS7_MSK (0x1 << 30) +#define NFC_3_2_WRPROT_US7_POS (31) +#define NFC_3_2_WRPROT_US7_MSK (0x1 << 31) + +#define NFC_3_2_UNLOCK_BLK_ADD0_REG_OFF (0x04) +#define NFC_3_2_UNLOCK_BLK_ADD0_USBA0_POS (0) +#define NFC_3_2_UNLOCK_BLK_ADD0_USBA0_MSK (0xFFFF << 0) +#define NFC_3_2_UNLOCK_BLK_ADD0_UEBA0_POS (16) +#define NFC_3_2_UNLOCK_BLK_ADD0_UEBA0_MSK (0xFFFF<<16) + +#define NFC_3_2_UNLOCK_BLK_ADD1_REG_OFF (0x08) +#define NFC_3_2_UNLOCK_BLK_ADD1_USBA1_POS (0) +#define NFC_3_2_UNLOCK_BLK_ADD1_USBA1_MSK (0xFFFF << 0) +#define NFC_3_2_UNLOCK_BLK_ADD1_UEBA1_POS (16) +#define NFC_3_2_UNLOCK_BLK_ADD1_UEBA1_MSK (0xFFFF<<16) + +#define NFC_3_2_UNLOCK_BLK_ADD2_REG_OFF (0x0C) +#define NFC_3_2_UNLOCK_BLK_ADD2_USBA2_POS (0) +#define NFC_3_2_UNLOCK_BLK_ADD2_USBA2_MSK (0xFFFF << 0) +#define NFC_3_2_UNLOCK_BLK_ADD2_UEBA2_POS (16) +#define NFC_3_2_UNLOCK_BLK_ADD2_UEBA2_MSK (0xFFFF<<16) + +#define NFC_3_2_UNLOCK_BLK_ADD3_REG_OFF (0x10) +#define NFC_3_2_UNLOCK_BLK_ADD3_USBA3_POS (0) +#define NFC_3_2_UNLOCK_BLK_ADD3_USBA3_MSK (0xFFFF << 0) +#define NFC_3_2_UNLOCK_BLK_ADD3_UEBA3_POS (16) +#define NFC_3_2_UNLOCK_BLK_ADD3_UEBA3_MSK (0xFFFF<<16) + +#define NFC_3_2_UNLOCK_BLK_ADD4_REG_OFF (0x14) +#define NFC_3_2_UNLOCK_BLK_ADD4_USBA4_POS (0) +#define NFC_3_2_UNLOCK_BLK_ADD4_USBA4_MSK (0xFFFF << 0) +#define NFC_3_2_UNLOCK_BLK_ADD4_UEBA4_POS (16) +#define NFC_3_2_UNLOCK_BLK_ADD4_UEBA4_MSK (0xFFFF<<16) + +#define NFC_3_2_UNLOCK_BLK_ADD5_REG_OFF (0x18) +#define NFC_3_2_UNLOCK_BLK_ADD5_USBA5_POS (0) +#define NFC_3_2_UNLOCK_BLK_ADD5_USBA5_MSK (0xFFFF << 0) +#define NFC_3_2_UNLOCK_BLK_ADD5_UEBA5_POS (16) +#define NFC_3_2_UNLOCK_BLK_ADD5_UEBA5_MSK (0xFFFF<<16) + +#define NFC_3_2_UNLOCK_BLK_ADD6_REG_OFF (0x1C) +#define NFC_3_2_UNLOCK_BLK_ADD6_USBA6_POS (0) +#define NFC_3_2_UNLOCK_BLK_ADD6_USBA6_MSK (0xFFFF << 0) +#define NFC_3_2_UNLOCK_BLK_ADD6_UEBA6_POS (16) +#define NFC_3_2_UNLOCK_BLK_ADD6_UEBA6_MSK (0xFFFF<<16) + +#define NFC_3_2_UNLOCK_BLK_ADD7_REG_OFF (0x20) +#define NFC_3_2_UNLOCK_BLK_ADD7_USBA7_POS (0) +#define NFC_3_2_UNLOCK_BLK_ADD7_USBA7_MSK (0xFFFF << 0) +#define NFC_3_2_UNLOCK_BLK_ADD7_UEBA7_POS (16) +#define NFC_3_2_UNLOCK_BLK_ADD7_UEBA7_MSK (0xFFFF<<16) + +#define NFC_3_2_CONFIG2_REG_OFF (0x24) +#define NFC_3_2_CONFIG2_PS_POS (0) +#define NFC_3_2_CONFIG2_PS_MSK (0x3 << 0) +#define NFC_3_2_CONFIG2_SYM_POS (2) +#define NFC_3_2_CONFIG2_SYM_MSK (0x1 << 2) +#define NFC_3_2_CONFIG2_ECC_EN_POS (3) +#define NFC_3_2_CONFIG2_ECC_EN_MSK (0x1 << 3) +#define NFC_3_2_CONFIG2_CMD_PHASES_POS (4) +#define NFC_3_2_CONFIG2_CMD_PHASES_MSK (0x1 << 4) +#define NFC_3_2_CONFIG2_ADDR_PHASES0_POS (5) +#define NFC_3_2_CONFIG2_ADDR_PHASES0_MSK (0x1 << 5) +#define NFC_3_2_CONFIG2_ECC_MODE_POS (6) +#define NFC_3_2_CONFIG2_ECC_MODE_MSK (0x1 << 6) +#define NFC_3_2_CONFIG2_PPB_POS (7) +#define NFC_3_2_CONFIG2_PPB_MSK (0x3 << 7) +#define NFC_3_2_CONFIG2_EDC_POS (9) +#define NFC_3_2_CONFIG2_EDC_MSK (0x7 << 9) +#define NFC_3_2_CONFIG2_ADDR_PHASES1_POS (12) +#define NFC_3_2_CONFIG2_ADDR_PHASES1_MSK (0x3 << 12) +#define NFC_3_2_CONFIG2_AUTO_DONE_MSK_POS (14) +#define NFC_3_2_CONFIG2_AUTO_DONE_MSK_MSK (0x1 << 14) +#define NFC_3_2_CONFIG2_INT_MSK_POS (15) +#define NFC_3_2_CONFIG2_INT_MSK_MSK (0x1 << 15) +#define NFC_3_2_CONFIG2_SPAS_POS (16) +#define NFC_3_2_CONFIG2_SPAS_MSK (0xFF << 16) +#define NFC_3_2_CONFIG2_ST_CMD_POS (24) +#define NFC_3_2_CONFIG2_ST_CMD_MSK (0xFF << 24) + +#define NFC_3_2_CONFIG3_REG_OFF (0x28) +#define NFC_3_2_CONFIG3_ADD_OP_POS (0) +#define NFC_3_2_CONFIG3_ADD_OP_MSK (0x3 << 0) +#define NFC_3_2_CONFIG3_TOO_POS (2) +#define NFC_3_2_CONFIG3_TOO_MSK (0x1 << 2) +#define NFC_3_2_CONFIG3_FW_POS (3) +#define NFC_3_2_CONFIG3_FW_MSK (0x1 << 3) +#define NFC_3_2_CONFIG3_SB2R_POS (4) +#define NFC_3_2_CONFIG3_SB2R_MSK (0x7 << 4) +#define NFC_3_2_CONFIG3_NF_BIG_POS (7) +#define NFC_3_2_CONFIG3_NF_BIG_MSK (0x1 << 7) +#define NFC_3_2_CONFIG3_SBB_POS (8) +#define NFC_3_2_CONFIG3_SBB_MSK (0x7 << 8) +#define NFC_3_2_CONFIG3_DMA_MODE_POS (11) +#define NFC_3_2_CONFIG3_DMA_MODE_MSK (0x1 << 11) +#define NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS (12) +#define NFC_3_2_CONFIG3_NUM_OF_DEVICES_MSK (0x7 << 12) +#define NFC_3_2_CONFIG3_RBB_MODE_POS (15) +#define NFC_3_2_CONFIG3_RBB_MODE_MSK (0x1 << 15) +#define NFC_3_2_CONFIG3_FMP_POS (16) +#define NFC_3_2_CONFIG3_FMP_MSK (0xF << 16) +#define NFC_3_2_CONFIG3_NO_SDMA_POS (20) +#define NFC_3_2_CONFIG3_NO_SDMA_MSK (0x1 << 20) + +#define NFC_3_2_IPC_REG_OFF (0x2C) +#define NFC_3_2_IPC_CREQ_POS (0) +#define NFC_3_2_IPC_CREQ_MSK (0x1 << 0) +#define NFC_3_2_IPC_CACK_POS (1) +#define NFC_3_2_IPC_CACK_MSK (0x1 << 1) +#define NFC_3_2_IPC_DMA_STATUS_POS (26) +#define NFC_3_2_IPC_DMA_STATUS_MSK (0x3 << 26) +#define NFC_3_2_IPC_RB_B_POS (28) +#define NFC_3_2_IPC_RB_B_MSK (0x1 << 28) +#define NFC_3_2_IPC_LPS_POS (29) +#define NFC_3_2_IPC_LPS_MSK (0x1 << 29) +#define NFC_3_2_IPC_AUTO_PROG_DONE_POS (30) +#define NFC_3_2_IPC_AUTO_PROG_DONE_MSK (0x1 << 30) +#define NFC_3_2_IPC_INT_POS (31) +#define NFC_3_2_IPC_INT_MSK (0x1 << 31) + +#define NFC_3_2_AXI_ERR_ADD_REG_OFF (0x30) + +/** + * enum override - Choices for overrides. + * + * Some functions of this driver can be overriden at run time. This is a + * convenient enumerated type for all such options. + */ + +enum override { + NEVER = -1, + DRIVER_CHOICE = 0, + ALWAYS = 1, +}; + +/** + * struct physical_geometry - Physical geometry description. + * + * This structure describes the physical geometry of the medium. + * + * @chip_count: The number of chips in the medium. + * @chip_size: The size, in bytes, of a single chip (excluding the + * out-of-band bytes). + * @block_size: The size, in bytes, of a single block (excluding the + * out-of-band bytes). + * @page_data_size: The size, in bytes, of the data area in a page (excluding + * the out-of-band bytes). + * @page_oob_size: The size, in bytes, of the out-of-band area in a page. + */ + +struct physical_geometry { + unsigned int chip_count; + uint64_t chip_size; + unsigned int block_size; + unsigned int page_data_size; + unsigned int page_oob_size; +}; + +/** + * struct nfc_geometry - NFC geometry description. + * + * This structure describes the NFC's view of the medium geometry, which may be + * different from the physical geometry (for example, we treat pages that are + * physically 2K+112 as if they are 2K+64). + * + * @page_data_size: The size of the data area in a page (excluding the + * out-of-band bytes). This is almost certain to be the same + * as the physical data size. + * @page_oob_size: The size of the out-of-band area in a page. This may be + * different from the physical OOB size. + * @ecc_algorithm: The name of the ECC algorithm (e.g., "Reed-Solomon" or + * "BCH"). + * @ecc_strength: A number that describes the strength of the ECC algorithm. + * For example, various i.MX SoC's support ECC-1, ECC-4 or + * ECC-8 of the Reed-Solomon ECC algorithm. + * @buffer_count: The number of main/spare buffers used with this geometry. + * @spare_buf_size: The number of bytes held in each spare buffer. + * @spare_buf_spill: The number of extra bytes held in the last spare buffer. + * @mtd_layout: The MTD layout that best matches the geometry described by + * the rest of this structure. The logical layer might not use + * this structure, especially when interleaving. + */ + +struct nfc_geometry { + const unsigned int page_data_size; + const unsigned int page_oob_size; + const char *ecc_algorithm; + const int ecc_strength; + const unsigned int buffer_count; + const unsigned int spare_buf_size; + const unsigned int spare_buf_spill; + struct nand_ecclayout mtd_layout; +}; + +/** + * struct logical_geometry - Logical geometry description. + * + * This structure describes the logical geometry we expose to MTD. This geometry + * may be different from the physical or NFC geometries, especially when + * interleaving. + * + * @chip_count: The number of chips in the medium. + * @chip_size: The size, in bytes, of a single chip (excluding the + * out-of-band bytes). + * @usable_size: The size, in bytes, of the medium that MTD can actually + * use. This may be less than the chip size multiplied by the + * number of chips. + * @block_size: The size, in bytes, of a single block (excluding the + * out-of-band bytes). + * @page_data_size: The size of the data area in a page (excluding the + * out-of-band bytes). + * @page_oob_size: The size of the out-of-band area in a page. + */ + +struct logical_geometry { + unsigned int chip_count; + uint32_t chip_size; + uint32_t usable_size; + unsigned int block_size; + unsigned int page_data_size; + unsigned int page_oob_size; + struct nand_ecclayout *mtd_layout; +}; + +/** + * struct imx_nfc_data - i.MX NFC per-device data. + * + * Note that the "device" managed by this driver represents the NAND Flash + * controller *and* the NAND Flash medium behind it. Thus, the per-device data + * structure has information about the controller, the chips to which it is + * connected, and properties of the medium as a whole. + * + * @dev: A pointer to the owning struct device. + * @pdev: A pointer to the owning struct platform_device. + * @pdata: A pointer to the device's platform data. + * @buffers: A pointer to the NFC buffers. + * @primary_regs: A pointer to the NFC primary registers. + * @secondary_regs: A pointer to the NFC secondary registers. + * @clock: A pointer to the NFC struct clk. + * @interrupt: The NFC interrupt number. + * @physical_geometry: A description of the medium's physical geometry. + * @nfc: A pointer to the NFC HAL. + * @nfc_geometry: A description of the medium geometry as viewed by the + * NFC. + * @done: The struct completion we use to handle interrupts. + * @logical_geometry: A description of the logical geometry exposed to MTD. + * @interrupt_override: Can override how the driver uses interrupts when + * waiting for the NFC. + * @auto_op_override: Can override whether the driver uses automatic NFC + * operations. + * @inject_ecc_error: Indicates that the driver should inject an ECC error in + * the next read operation that uses ECC. User space + * programs can set this value through the sysfs node of + * the same name. If this value is less than zero, the + * driver will inject an uncorrectable ECC error. If this + * value is greater than zero, the driver will inject that + * number of correctable errors, capped at whatever + * possible maximum currently applies. + * @current_chip: The chip currently selected by the NAND Fash MTD HIL. + * A negative value indicates that no chip is selected. + * We use this field to detect when the HIL begins and + * ends essential transactions. This helps us to know when + * we should turn the NFC clock on or off. + * @command: The last command the HIL tried to send by calling + * cmdfunc(). Later functions use this information to + * adjust their behavior. The sentinel value ~0 indicates + * no command. + * @command_is_new: Indicates the command has just come down to cmdfunc() + * from the HIL and hasn't yet been handled. Other + * functions use this to adjust their behavior. + * @page_address: The current page address of interest. For reads, this + * information arrives in calls to cmdfunc(), but we don't + * actually use it until later. + * @nand: The data structure that represents this NAND Flash + * medium to the MTD NAND Flash system. + * @mtd: The data structure that represents this NAND Flash + * medium to MTD. + * @partitions: A pointer to a set of partitions collected from one of + * several possible sources (e.g., the boot loader, the + * kernel command line, etc.). See the global variable + * partition_source_types for the list of partition + * sources we examine. If this member is NULL, then no + * partitions were discovered. + * @partition_count: The number of discovered partitions. + */ + +struct imx_nfc_data { + + /* System Interface */ + struct device *dev; + struct platform_device *pdev; + + /* Platform Configuration */ + struct imx_nfc_platform_data *pdata; + void *buffers; + void *primary_regs; + void *secondary_regs; + struct clk *clock; + unsigned int interrupt; + + /* Flash Hardware */ + struct physical_geometry physical_geometry; + + /* NFC HAL and NFC Utilities */ + struct nfc_hal *nfc; + struct nfc_geometry *nfc_geometry; + struct completion done; + + /* Medium Abstraction Layer */ + struct logical_geometry logical_geometry; + enum override interrupt_override; + enum override auto_op_override; + int inject_ecc_error; + + /* MTD Interface Layer */ + int current_chip; + unsigned int command; + int command_is_new; + int page_address; + + /* NAND Flash MTD */ + struct nand_chip nand; + + /* MTD */ + struct mtd_info mtd; + struct mtd_partition *partitions; + unsigned int partition_count; + +}; + +/** + * struct nfc_hal - i.MX NFC HAL + * + * This structure embodies an abstract interface to the underlying NFC hardware. + * + * @major_version: The major version number of the NFC to which this + * structure applies. + * @minor_version: The minor version number of the NFC to which this + * structure applies. + * @max_chip_count: The maximum number of chips the NFC can possibly + * support. This may *not* be the actual number of chips + * currently connected. This value is constant for NFC's + * of a given version. + * @max_buffer_count: The number of main/spare buffers available in the NFC's + * memory. This value is constant for NFC's of a given + * version. + * @spare_buf_stride: The stride, in bytes, from the beginning of one spare + * buffer to the beginning of the next one. This value is + * constant for NFC's of a given version. + * @has_secondary_regs: Indicates if the NFC has a secondary register set that + * must be mapped in. + * @can_be_symmetric: Indicates if the NFC supports a "symmetric" clock. When + * the clock is "symmetric," the hardware waits one NFC + * clock for every read/write cycle. When the clock is + * "asymmetric," the hardware waits two NFC clocks for + * every read/write cycle. + * @init: Initializes the NFC and any version-specific data + * structures. This function will be called after + * everything has been set up for communication with the + * NFC itself, but before the platform has set up off-chip + * communication. Thus, this function must not attempt to + * communicate with the NAND Flash hardware. A non-zero + * return value indicates failure. + * @set_geometry: Based on the physical geometry, this function selects + * an NFC geometry structure and configures the NFC + * hardware to match. A non-zero return value indicates + * failure. + * @exit: Shuts down the NFC and cleans up version-specific data + * structures. This function will be called after the + * platform has shut down off-chip communication but while + * communication with the NFC still works. + * @set_closest_cycle: Configures the hardware to make the NAND Flash bus + * cycle period as close as possible to the given cycle + * period. This function is called during boot up and may + * assume that, at the time it's called, the parent clock + * is running at the highest rate it will ever run. Thus, + * this function need never worry that the NAND Flash bus + * will run faster and potentially make it impossible to + * communicate with the NAND Flash device -- it will only + * run slower. + * @mask_interrupt: Masks the NFC's interrupt. + * @unmask_interrupt: Unmasks the NFC's interrupt. + * @clear_interrupt: Clears the NFC's interrupt. + * @is_interrupting: Returns true if the NFC is interrupting. + * @is_ready: Returns true if all the chips in the medium are ready. + * This member may be set to NULL, which indicates that + * the underlying NFC hardware doesn't expose ready/busy + * signals. + * @set_force_ce: If passed true, forces the hardware chip enable signal + * for the current chip to be asserted always. If passed + * false, causes the chip enable signal to be asserted + * only during I/O. + * @set_ecc: Sets ECC on or off. + * @get_ecc_status: Examines the hardware ECC status and returns: + * == 0 => No errors. + * > 0 => The number of corrected errors. + * < 0 => There were uncorrectable errors. + * @get_symmetric: Gets the current symmetric clock setting. For versions + * that don't support symmetric clocks, this function + * always returns false. + * @set_symmetric: For versions that support symmetric clocks, sets + * whether or not the clock is symmetric. + * @select_chip: Selects the current chip. + * @command_cycle: Sends a command code and then returns immediately + * *without* waiting for the NFC to finish. + * @write_cycle: Applies a single write cycle to the current chip, + * sending the given byte, and waiting for the NFC to + * finish. + * @read_cycle: Applies a single read cycle to the current chip and + * returns the result, necessarily waiting for the NFC to + * finish. The width of the result is the same as the + * width of the Flash bus. + * @read_page: Applies read cycles to the current chip to read an + * entire page into the NFC. Note that ECC is enabled or + * disabled with the set_ecc function pointer (see above). + * This function waits for the NFC to finish before + * returning. + * @send_page: Applies write cycles to send an entire page from the + * NFC to the current chip. Note that ECC is enabled or + * disabled with the set_ecc function pointer (see above). + * This function waits for the NFC to finish before + * returning. + * @start_auto_read: Starts an automatic read operation. A NULL pointer + * indicates automatic read operations aren't available + * with this NFC version. + * @wait_for_auto_read: Blocks until an automatic read operation is ready for + * the CPU to copy a page out of the NFC. + * @resume_auto_read: Resumes an automatic read operation after the CPU has + * copied a page out. + * @start_auto_write: Starts an automatic write operation. A NULL pointer + * indicates automatic write operations aren't available + * with this NFC version. + * @wait_for_auto_write: Blocks until an automatic write operation is ready for + * the CPU to copy a page into the NFC. + * @start_auto_erase: Starts an automatic erase operation. A NULL pointer + * indicates automatic erase operations aren't available + * with this NFC version. + */ + +struct nfc_hal { + const unsigned int major_version; + const unsigned int minor_version; + const unsigned int max_chip_count; + const unsigned int max_buffer_count; + const unsigned int spare_buf_stride; + const int has_secondary_regs; + const int can_be_symmetric; + int (*init) (struct imx_nfc_data *); + int (*set_geometry) (struct imx_nfc_data *); + void (*exit) (struct imx_nfc_data *); + int (*set_closest_cycle) (struct imx_nfc_data *, unsigned ns); + void (*mask_interrupt) (struct imx_nfc_data *); + void (*unmask_interrupt) (struct imx_nfc_data *); + void (*clear_interrupt) (struct imx_nfc_data *); + int (*is_interrupting) (struct imx_nfc_data *); + int (*is_ready) (struct imx_nfc_data *); + void (*set_force_ce) (struct imx_nfc_data *, int on); + void (*set_ecc) (struct imx_nfc_data *, int on); + int (*get_ecc_status) (struct imx_nfc_data *); + int (*get_symmetric) (struct imx_nfc_data *); + void (*set_symmetric) (struct imx_nfc_data *, int on); + void (*select_chip) (struct imx_nfc_data *, int chip); + void (*command_cycle) (struct imx_nfc_data *, unsigned cmd); + void (*write_cycle) (struct imx_nfc_data *, unsigned byte); + unsigned (*read_cycle) (struct imx_nfc_data *); + void (*read_page) (struct imx_nfc_data *); + void (*send_page) (struct imx_nfc_data *); + int (*start_auto_read) (struct imx_nfc_data *, + unsigned start, unsigned count, unsigned column, unsigned page); + int (*wait_for_auto_read) (struct imx_nfc_data *); + int (*resume_auto_read) (struct imx_nfc_data *); + int (*start_auto_write) (struct imx_nfc_data *, + unsigned start, unsigned count, unsigned column, unsigned page); + int (*wait_for_auto_write)(struct imx_nfc_data *); + int (*start_auto_erase) (struct imx_nfc_data *, + unsigned start, unsigned count, unsigned page); +}; + +/* + * This variable controls whether or not probing is enabled. If false, then + * the driver will refuse to probe. The "enable" module parameter controls the + * value of this variable. + */ + +static int imx_nfc_module_enable = true; + +#ifdef EVENT_REPORTING + +/* + * This variable controls whether the driver reports event information by + * printing to the console. The "report_events" module parameter controls the + * value of this variable. + */ + +static int imx_nfc_module_report_events; /* implicitly initialized false*/ + +#endif + +/* + * This variable potentially overrides the driver's choice to interleave. The + * "interleave_override" module parameter controls the value of this variable. + */ + +static enum override imx_nfc_module_interleave_override = DRIVER_CHOICE; + +/* + * When set, this variable forces the driver to use the bytewise copy functions + * to get data in and out of the NFC. This is intended for testing, not typical + * use. + */ + +static int imx_nfc_module_force_bytewise_copy; /* implicitly initialized false*/ + +/* + * The list of algorithms we use to get partition information from the + * environment. + */ + +#ifdef CONFIG_MTD_PARTITIONS +static const char *partition_source_types[] = { "cmdlinepart", NULL }; +#endif + +/* + * The following structures describe the NFC geometries we support. + * + * Notice that pieces of some structure definitions are commented out and edited + * because various parts of the MTD system can't handle the way our hardware + * formats the out-of-band area. + * + * Here are the problems: + * + * - struct nand_ecclayout expects no more than 64 ECC bytes. + * + * The eccpos member of struct nand_ecclayout can't hold more than 64 ECC + * byte positions. Some of our formats have more so, unedited, they won't + * even compile. We comment out all ECC byte positions after the 64th one. + * + * - struct nand_ecclayout expects no more than 8 free spans. + * + * The oobfree member of struct nand_ecclayout can't hold more than 8 free + * spans. Some of our formats have more so, unedited, they won't even + * compile. We comment out all free spans after the eighth one. + * + * - The MEMGETOOBSEL command in the mtdchar driver. + * + * The mtdchar ioctl command MEMGETOOBSEL checks the number of ECC bytes + * against the length of the eccpos array in struct nand_oobinfo + * (see include/mtd/mtd-abi.h). This array can handle up to 32 ECC bytes, + * but some of our formats have more. + * + * To make this work, we cap the value assigned to eccbytes at 32. + * + * Notice that struct nand_oobinfo, used by mtdchar, is *different* from the + * struct nand_ecclayout that MTD uses internally. The latter structure + * can accomodate up to 64 ECC byte positions. Thus, we declare up to 64 + * ECC byte positions here, even if the advertised number of ECC bytes is + * less. + * + * This command is obsolete and, if no one used it, we wouldn't care about + * this problem. Unfortunately The nandwrite program uses it, and everyone + * expects nandwrite to work (it's how everyone usually lays down their + * JFFS2 file systems). + */ + +static struct nfc_geometry nfc_geometry_512_16_RS_ECC1 = { + .page_data_size = 512, + .page_oob_size = 16, + .ecc_algorithm = "Reed-Solomon", + .ecc_strength = 1, + .buffer_count = 1, + .spare_buf_size = 16, + .spare_buf_spill = 0, + .mtd_layout = { + .eccbytes = 5, + .eccpos = {6, 7, 8, 9, 10}, + .oobavail = 11, + .oobfree = { {0, 6}, {11, 5} }, + } +}; + +static struct nfc_geometry nfc_geometry_512_16_RS_ECC4 = { + .page_data_size = 512, + .page_oob_size = 16, + .ecc_algorithm = "Reed-Solomon", + .ecc_strength = 4, + .buffer_count = 1, + .spare_buf_size = 16, + .spare_buf_spill = 0, + .mtd_layout = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobavail = 7, + .oobfree = { {0, 7} }, + } +}; + +static struct nfc_geometry nfc_geometry_512_16_BCH_ECC4 = { + .page_data_size = 512, + .page_oob_size = 16, + .ecc_algorithm = "BCH", + .ecc_strength = 4, + .buffer_count = 1, + .spare_buf_size = 16, + .spare_buf_spill = 0, + .mtd_layout = { + .eccbytes = 8, + .eccpos = {8, 9, 10, 11, 12, 13, 14, 15}, + .oobavail = 8, + .oobfree = { {0, 8} }, + } +}; + +static struct nfc_geometry nfc_geometry_2K_64_RS_ECC4 = { + .page_data_size = 2048, + .page_oob_size = 64, + .ecc_algorithm = "Reed-Solomon", + .ecc_strength = 4, + .buffer_count = 4, + .spare_buf_size = 16, + .spare_buf_spill = 0, + .mtd_layout = { + .eccbytes = 32 /*9 * 4*/, /* See notes above. */ + .eccpos = { + + (0*16)+7 , (0*16)+8 , (0*16)+9 , (0*16)+10, (0*16)+11, + (0*16)+12, (0*16)+13, (0*16)+14, (0*16)+15, + + (1*16)+7 , (1*16)+8 , (1*16)+9 , (1*16)+10, (1*16)+11, + (1*16)+12, (1*16)+13, (1*16)+14, (1*16)+15, + + (2*16)+7 , (2*16)+8 , (2*16)+9 , (2*16)+10, (2*16)+11, + (2*16)+12, (2*16)+13, (2*16)+14, (2*16)+15, + + (3*16)+7 , (3*16)+8 , (3*16)+9 , (3*16)+10, (3*16)+11, + (3*16)+12, (3*16)+13, (3*16)+14, (3*16)+15, + + }, + .oobavail = 7 * 4, + .oobfree = { + {(0*16)+0, 7}, + {(1*16)+0, 7}, + {(2*16)+0, 7}, + {(3*16)+0, 7}, + }, + } +}; + +static struct nfc_geometry nfc_geometry_2K_64_BCH_ECC4 = { + .page_data_size = 2048, + .page_oob_size = 64, + .ecc_algorithm = "BCH", + .ecc_strength = 4, + .buffer_count = 4, + .spare_buf_size = 16, + .spare_buf_spill = 0, + .mtd_layout = { + .eccbytes = 8 * 4, + .eccpos = { + + (0*16)+8 , (0*16)+9 , (0*16)+10, (0*16)+11, + (0*16)+12, (0*16)+13, (0*16)+14, (0*16)+15, + + (1*16)+8 , (1*16)+9 , (1*16)+10, (1*16)+11, + (1*16)+12, (1*16)+13, (1*16)+14, (1*16)+15, + + (2*16)+8 , (2*16)+9 , (2*16)+10, (2*16)+11, + (2*16)+12, (2*16)+13, (2*16)+14, (2*16)+15, + + (3*16)+8 , (3*16)+9 , (3*16)+10, (3*16)+11, + (3*16)+12, (3*16)+13, (3*16)+14, (3*16)+15, + + }, + .oobavail = 8 * 4, + .oobfree = { + {(0*16)+0, 8}, + {(1*16)+0, 8}, + {(2*16)+0, 8}, + {(3*16)+0, 8}, + }, + } +}; + +static struct nfc_geometry nfc_geometry_4K_128_BCH_ECC4 = { + .page_data_size = 4096, + .page_oob_size = 128, + .ecc_algorithm = "BCH", + .ecc_strength = 4, + .buffer_count = 8, + .spare_buf_size = 16, + .spare_buf_spill = 0, + .mtd_layout = { + .eccbytes = 8 * 8, + .eccpos = { + + (0*16)+8 , (0*16)+9 , (0*16)+10, (0*16)+11, + (0*16)+12, (0*16)+13, (0*16)+14, (0*16)+15, + + (1*16)+8 , (1*16)+9 , (1*16)+10, (1*16)+11, + (1*16)+12, (1*16)+13, (1*16)+14, (1*16)+15, + + (2*16)+8 , (2*16)+9 , (2*16)+10, (2*16)+11, + (2*16)+12, (2*16)+13, (2*16)+14, (2*16)+15, + + (3*16)+8 , (3*16)+9 , (3*16)+10, (3*16)+11, + (3*16)+12, (3*16)+13, (3*16)+14, (3*16)+15, + + (4*16)+8 , (4*16)+9 , (4*16)+10, (4*16)+11, + (4*16)+12, (4*16)+13, (4*16)+14, (4*16)+15, + + (5*16)+8 , (5*16)+9 , (5*16)+10, (5*16)+11, + (5*16)+12, (5*16)+13, (5*16)+14, (5*16)+15, + + (6*16)+8 , (6*16)+9 , (6*16)+10, (6*16)+11, + (6*16)+12, (6*16)+13, (6*16)+14, (6*16)+15, + + (7*16)+8 , (7*16)+9 , (7*16)+10, (7*16)+11, + (7*16)+12, (7*16)+13, (7*16)+14, (7*16)+15, + + }, + .oobavail = 8 * 8, + .oobfree = { + {(0*16)+0, 8}, + {(1*16)+0, 8}, + {(2*16)+0, 8}, + {(3*16)+0, 8}, + {(4*16)+0, 8}, + {(5*16)+0, 8}, + {(6*16)+0, 8}, + {(7*16)+0, 8}, + }, + } +}; + +static struct nfc_geometry nfc_geometry_4K_218_BCH_ECC8 = { + .page_data_size = 4096, + .page_oob_size = 218, + .ecc_algorithm = "BCH", + .ecc_strength = 8, + .buffer_count = 8, + .spare_buf_size = 26, + .spare_buf_spill = 10, + .mtd_layout = { + .eccbytes = 32 /*10 * 8*/, /* See notes above. */ + .eccpos = { + + (0*26)+12, (0*26)+13, (0*26)+14, (0*26)+15, (0*26)+16, + (0*26)+17, (0*26)+18, (0*26)+19, (0*26)+20, (0*26)+21, + + (1*26)+12, (1*26)+13, (1*26)+14, (1*26)+15, (1*26)+16, + (1*26)+17, (1*26)+18, (1*26)+19, (1*26)+20, (1*26)+21, + + (2*26)+12, (2*26)+13, (2*26)+14, (2*26)+15, (2*26)+16, + (2*26)+17, (2*26)+18, (2*26)+19, (2*26)+20, (2*26)+21, + + (3*26)+12, (3*26)+13, (3*26)+14, (3*26)+15, (3*26)+16, + (3*26)+17, (3*26)+18, (3*26)+19, (3*26)+20, (3*26)+21, + + (4*26)+12, (4*26)+13, (4*26)+14, (4*26)+15, (4*26)+16, + (4*26)+17, (4*26)+18, (4*26)+19, (4*26)+20, (4*26)+21, + + (5*26)+12, (5*26)+13, (5*26)+14, (5*26)+15, (5*26)+16, + (5*26)+17, (5*26)+18, (5*26)+19, (5*26)+20, (5*26)+21, + + (6*26)+12, (6*26)+13, (6*26)+14, (6*26)+15, + /* See notes above. + (6*26)+16, + (6*26)+17, (6*26)+18, (6*26)+19, (6*26)+20, (6*26)+21, + + (7*26)+12, (7*26)+13, (7*26)+14, (7*26)+15, (7*26)+16, + (7*26)+17, (7*26)+18, (7*26)+19, (7*26)+20, (7*26)+21, + */ + + }, + .oobavail = 96 /*(16 * 8) + 10*/, /* See notes above. */ + .oobfree = { + {(0*26)+0, 12}, {(0*26)+22, 4}, + {(1*26)+0, 12}, {(1*26)+22, 4}, + {(2*26)+0, 12}, {(2*26)+22, 4}, + {(3*26)+0, 48}, /* See notes above. */ + /* See notes above. + {(3*26)+0, 12}, {(3*26)+22, 4}, + {(4*26)+0, 12}, {(4*26)+22, 4}, + {(5*26)+0, 12}, {(5*26)+22, 4}, + {(6*26)+0, 12}, {(6*26)+22, 4}, + {(7*26)+0, 12}, {(7*26)+22, 4 + 10}, + */ + }, + } +}; + +/* + * When the logical geometry differs from the NFC geometry (e.g., + * interleaving), we synthesize a layout rather than use the one that comes with + * the NFC geometry. See mal_set_logical_geometry(). + */ + +static struct nand_ecclayout synthetic_layout; + +/* + * These structures describe how the BBT code will find block marks in the OOB + * area of a page. Don't be confused by the fact that this is the same type used + * to describe bad block tables. Some of the same information is needed, so the + * designers use the same structure for two conceptually distinct functions. + */ + +static uint8_t block_mark_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr small_page_block_mark_descriptor = { + .options = NAND_BBT_SCAN2NDPAGE, + .offs = 5, + .len = 1, + .pattern = block_mark_pattern, +}; + +static struct nand_bbt_descr large_page_block_mark_descriptor = { + .options = NAND_BBT_SCAN2NDPAGE, + .offs = 0, + .len = 2, + .pattern = block_mark_pattern, +}; + +/* + * Bad block table descriptors for the main and mirror tables. + */ + +static uint8_t bbt_main_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t bbt_mirror_pattern[] = { '1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descriptor = { + .options = + NAND_BBT_LASTBLOCK | + NAND_BBT_CREATE | + NAND_BBT_WRITE | + NAND_BBT_2BIT | + NAND_BBT_VERSION | + NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_main_pattern, +}; + +static struct nand_bbt_descr bbt_mirror_descriptor = { + .options = + NAND_BBT_LASTBLOCK | + NAND_BBT_CREATE | + NAND_BBT_WRITE | + NAND_BBT_2BIT | + NAND_BBT_VERSION | + NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_mirror_pattern, +}; + +#ifdef EVENT_REPORTING + +/** + * struct event - A single record in the event trace. + * + * @time: The time at which the event occurred. + * @nesting: Indicates function call nesting. + * @description: A description of the event. + */ + +struct event { + ktime_t time; + unsigned int nesting; + char *description; +}; + +/** + * The event trace. + * + * @overhead: The delay to take a time stamp and nothing else. + * @nesting: The current nesting level. + * @overflow: Indicates the trace overflowed. + * @next: Index of the next event to write. + * @events: The array of events. + */ + +#define MAX_EVENT_COUNT (200) + +static struct { + ktime_t overhead; + int nesting; + int overflow; + unsigned int next; + struct event events[MAX_EVENT_COUNT]; +} event_trace; + +/** + * reset_event_trace() - Resets the event trace. + */ +static void reset_event_trace(void) +{ + event_trace.nesting = 0; + event_trace.overflow = false; + event_trace.next = 0; +} + +/** + * add_event() - Adds an event to the event trace. + * + * @description: A description of the event. + * @delta: A delta to the nesting level for this event [-1, 0, 1]. + */ +static inline void add_event(char *description, int delta) +{ + struct event *event; + + if (!imx_nfc_module_report_events) + return; + + if (event_trace.overflow) + return; + + if (event_trace.next >= MAX_EVENT_COUNT) { + event_trace.overflow = true; + return; + } + + event = event_trace.events + event_trace.next; + + event->time = ktime_get(); + + event->description = description; + + if (!delta) + event->nesting = event_trace.nesting; + else if (delta < 0) { + event->nesting = event_trace.nesting - 1; + event_trace.nesting -= 2; + } else { + event->nesting = event_trace.nesting + 1; + event_trace.nesting += 2; + } + + if (event_trace.nesting < 0) + event_trace.nesting = 0; + + event_trace.next++; + +} + +/** + * add_state_event_l() - Adds an event to display some state. + * + * @address: The address to examine. + * @mask: A mask to apply to the contents of the given address. + * @clear: An event message to add if the result is zero. + * @not_zero: An event message to add if the result is not zero. + */ +static void add_state_event_l(void *address, uint32_t mask, + char *zero, char *not_zero) +{ + int state; + state = !!(__raw_readl(address) & mask); + if (state) + add_event(not_zero, 0); + else + add_event(zero, 0); +} + +/** + * start_event_trace() - Starts an event trace and adds the first event. + * + * @description: A description of the first event. + */ +static void start_event_trace(char *description) +{ + + ktime_t t0; + ktime_t t1; + + if (!imx_nfc_module_report_events) + return; + + reset_event_trace(); + + t0 = ktime_get(); + t1 = ktime_get(); + + event_trace.overhead = ktime_sub(t1, t0); + + add_event(description, 1); + +} + +/** + * dump_event_trace() - Dumps the event trace. + */ +static void dump_event_trace(void) +{ + unsigned int i; + time_t seconds; + long nanoseconds; + char line[100]; + int o; + struct event *first_event; + struct event *last_event; + struct event *matching_event; + struct event *event; + ktime_t delta; + + /* Check if event reporting is turned off. */ + + if (!imx_nfc_module_report_events) + return; + + /* Print important facts about this event trace. */ + + printk(KERN_DEBUG "\n+--------------\n"); + + printk(KERN_DEBUG "| Overhead : [%d:%d]\n", + event_trace.overhead.tv.sec, + event_trace.overhead.tv.nsec); + + if (!event_trace.next) { + printk(KERN_DEBUG "| No Events\n"); + return; + } + + first_event = event_trace.events; + last_event = event_trace.events + (event_trace.next - 1); + + delta = ktime_sub(last_event->time, first_event->time); + printk(KERN_DEBUG "| Elapsed Time: [%d:%d]\n", + delta.tv.sec, delta.tv.nsec); + + if (event_trace.overflow) + printk(KERN_DEBUG "| Overflow!\n"); + + /* Print the events in this history. */ + + for (i = 0, event = event_trace.events; + i < event_trace.next; i++, event++) { + + /* Get the delta between this event and the previous event. */ + + if (!i) { + seconds = 0; + nanoseconds = 0; + } else { + delta = ktime_sub(event[0].time, event[-1].time); + seconds = delta.tv.sec; + nanoseconds = delta.tv.nsec; + } + + /* Print the current event. */ + + o = 0; + + o = snprintf(line, sizeof(line) - o, "| [%ld:% 10ld]%*s %s", + seconds, nanoseconds, + event->nesting, "", + event->description); + /* Check if this is the last event in a nested series. */ + + if (i && (event[0].nesting < event[-1].nesting)) { + + for (matching_event = event - 1;; matching_event--) { + + if (matching_event < event_trace.events) { + matching_event = 0; + break; + } + + if (matching_event->nesting == event->nesting) + break; + + } + + if (matching_event) { + delta = ktime_sub(event->time, + matching_event->time); + o += snprintf(line + o, sizeof(line) - o, + " <%d:%d]", delta.tv.sec, + delta.tv.nsec); + } + + } + + /* Check if this is the first event in a nested series. */ + + if ((i < event_trace.next - 1) && + (event[0].nesting < event[1].nesting)) { + + for (matching_event = event + 1;; matching_event++) { + + if (matching_event >= + (event_trace.events+event_trace.next)) { + matching_event = 0; + break; + } + + if (matching_event->nesting == event->nesting) + break; + + } + + if (matching_event) { + delta = ktime_sub(matching_event->time, + event->time); + o += snprintf(line + o, sizeof(line) - o, + " [%d:%d>", delta.tv.sec, + delta.tv.nsec); + } + + } + + printk(KERN_DEBUG "%s\n", line); + + } + + printk(KERN_DEBUG "+--------------\n"); + +} + +/** + * stop_event_trace() - Stops an event trace. + * + * @description: A description of the last event. + */ +static void stop_event_trace(char *description) +{ + struct event *event; + + if (!imx_nfc_module_report_events) + return; + + /* + * We want the end of the trace, no matter what happens. If the trace + * has already overflowed, or is about to, just jam this event into the + * last spot. Otherwise, add this event like any other. + */ + + if (event_trace.overflow || (event_trace.next >= MAX_EVENT_COUNT)) { + event = event_trace.events + (MAX_EVENT_COUNT - 1); + event->time = ktime_get(); + event->description = description; + event->nesting = 0; + } else { + add_event(description, -1); + } + + dump_event_trace(); + reset_event_trace(); + +} + +#else /* EVENT_REPORTING */ + +#define start_event_trace(description) do {} while (0) +#define add_event(description, delta) do {} while (0) +#define add_state_event_l(address, mask, zero, not_zero) do {} while (0) +#define stop_event_trace(description) do {} while (0) +#define dump_event_trace() do {} while (0) + +#endif /* EVENT_REPORTING */ + +/** + * unimplemented() - Announces intentionally unimplemented features. + * + * @this: Per-device data. + * @msg: A message about the unimplemented feature. + */ +static inline void unimplemented(struct imx_nfc_data *this, const char * msg) +{ + dev_err(this->dev, "Intentionally unimplemented: %s", msg); +} + +/** + * raw_read_mask_w() - Reads masked bits in a 16-bit hardware register. + */ +static inline uint16_t raw_read_mask_w(uint16_t mask, void *address) +{ + return __raw_readw(address) & mask; +} + +/** + * raw_set_mask_w() - Sets bits in a 16-bit hardware register. + */ +static inline void raw_set_mask_w(uint16_t mask, void *address) +{ + __raw_writew(__raw_readw(address) | mask, address); +} + +/** + * raw_clr_mask_w() - Clears bits in a 16-bit hardware register. + */ +static inline void raw_clr_mask_w(uint16_t mask, void *address) +{ + __raw_writew(__raw_readw(address) & (~mask), address); +} + +/** + * raw_read_mask_l() - Reads masked bits in a 32-bit hardware register. + */ +static inline uint32_t raw_read_mask_l(uint32_t mask, void *address) +{ + return __raw_readl(address) & mask; +} + +/** + * raw_set_mask_l() - Sets bits in a 32-bit hardware register. + */ +static inline void raw_set_mask_l(uint32_t mask, void *address) +{ + __raw_writel(__raw_readl(address) | mask, address); +} + +/** + * raw_clr_mask_l() - Clears bits in a 32-bit hardware register. + */ +static inline void raw_clr_mask_l(uint32_t mask, void *address) +{ + __raw_writel(__raw_readl(address) & (~mask), address); +} + +/** + * is_large_page_chip() - Returns true for large page media. + * + * @this: Per-device data. + */ +static inline int is_large_page_chip(struct imx_nfc_data *this) +{ + return (this->physical_geometry.page_data_size > 512); +} + +/** + * is_small_page_chip() - Returns true for small page media. + * + * @this: Per-device data. + */ +static inline int is_small_page_chip(struct imx_nfc_data *this) +{ + return !is_large_page_chip(this); +} + +/** + * get_cycle_in_ns() - Returns the given device's cycle period, in ns. + * + * @this: Per-device data. + */ +static inline unsigned get_cycle_in_ns(struct imx_nfc_data *this) +{ + unsigned long cycle_in_ns; + + cycle_in_ns = 1000000000 / clk_get_rate(this->clock); + + if (!this->nfc->get_symmetric(this)) + cycle_in_ns *= 2; + + return cycle_in_ns; + +} + +/** + * nfc_util_set_best_cycle() - Sets the closest possible NAND Flash bus cycle. + * + * This function computes the clock setup that will best approximate the given + * target Flash bus cycle period. + * + * For some NFC versions, we can make the clock "symmetric." When the clock + * is "symmetric," the hardware waits one NFC clock for every read/write cycle. + * When the clock is "asymmetric," the hardware waits two NFC clocks for every + * read/write cycle. Thus, making the clock asymmetric essentially divides the + * NFC clock by two. + * + * We compute the target frequency that matches the given target period. We then + * discover the closest available match with that frequency and the closest + * available match with double that frequency (for use with an asymmetric + * clock). We implement the best choice of original clock and symmetric or + * asymmetric setting, preferring symmetric clocks. + * + * @this: Per-device data. + * @ns: The target cycle period, in nanoseconds. + * @no_asym: Disallow making the clock asymmetric. + * @no_sym: Disallow making the clock symmetric. + */ +static int nfc_util_set_best_cycle(struct imx_nfc_data *this, + unsigned int ns, int no_asym, int no_sym) +{ + unsigned long target_hz; + long symmetric_hz; + long symmetric_delta_hz; + long asymmetric_hz; + long asymmetric_delta_hz; + unsigned long best_hz; + int best_symmetry_setting; + struct device *dev = this->dev; + + /* The target cycle period must be greater than zero. */ + + if (!ns) + return -EINVAL; + + /* Compute the target frequency. */ + + target_hz = 1000000000 / ns; + + /* Find out how close we can get with a symmetric clock. */ + + if (!no_sym && this->nfc->can_be_symmetric) + symmetric_hz = clk_round_rate(this->clock, target_hz); + else + symmetric_hz = -EINVAL; + + /* Find out how close we can get with an asymmetric clock. */ + + if (!no_asym) + asymmetric_hz = clk_round_rate(this->clock, target_hz * 2); + else + asymmetric_hz = -EINVAL; + + /* Does anything work at all? */ + + if ((symmetric_hz == -EINVAL) && (asymmetric_hz == -EINVAL)) { + dev_err(dev, "Can't support Flash bus cycle of %uns\n", ns); + return -EINVAL; + } + + /* Discover the best match. */ + + if ((symmetric_hz != -EINVAL) && (asymmetric_hz != -EINVAL)) { + + symmetric_delta_hz = target_hz - symmetric_hz; + asymmetric_delta_hz = target_hz - (asymmetric_hz / 2); + + if (symmetric_delta_hz <= asymmetric_delta_hz) + best_symmetry_setting = true; + else + best_symmetry_setting = false; + + } else if (symmetric_hz != -EINVAL) { + best_symmetry_setting = true; + } else { + best_symmetry_setting = false; + } + + best_hz = best_symmetry_setting ? symmetric_hz : asymmetric_hz; + + /* Implement the best match. */ + + this->nfc->set_symmetric(this, best_symmetry_setting); + + return clk_set_rate(this->clock, best_hz); + +} + +/** + * nfc_util_wait_for_the_nfc() - Waits for the NFC to finish an operation. + * + * @this: Per-device data. + * @use_irq: Indicates that we should wait for an interrupt rather than polling + * and delaying. + */ +static void nfc_util_wait_for_the_nfc(struct imx_nfc_data *this, int use_irq) +{ + unsigned spin_count; + struct device *dev = this->dev; + + /* Apply the override, if any. */ + + switch (this->interrupt_override) { + + case NEVER: + use_irq = false; + break; + + case DRIVER_CHOICE: + break; + + case ALWAYS: + use_irq = true; + break; + + } + + /* Check if we're using interrupts. */ + + if (use_irq) { + + /* + * If control arrives here, the caller wants to use interrupts. + * Presumably, this operation is known to take a very long time. + */ + + if (this->nfc->is_interrupting(this)) { + add_event("Waiting for the NFC (early interrupt)", 1); + this->nfc->clear_interrupt(this); + } else { + add_event("Waiting for the NFC (interrupt)", 1); + this->nfc->unmask_interrupt(this); + wait_for_completion(&this->done); + } + + add_event("NFC done", -1); + + } else { + + /* + * If control arrives here, the caller doesn't want to use + * interrupts. Presumably, this operation is too quick to + * justify the overhead. Leave the interrupt masked, and loop + * until the interrupt bit lights up, or we time out. + * + * We spin for a maximum of about 2ms before declaring a time + * out. No operation we could possibly spin on should take that + * long. + */ + + spin_count = 2000; + + add_event("Waiting for the NFC (polling)", 1); + + for (; spin_count > 0; spin_count--) { + + if (this->nfc->is_interrupting(this)) { + this->nfc->clear_interrupt(this); + add_event("NFC done", -1); + return; + } + + udelay(1); + + } + + /* Timed out. */ + + add_event("Timed out", -1); + + dev_err(dev, "[wait_for_the_nfc] ===== Time Out =====\n"); + dump_event_trace(); + + } + +} + +/** + * nfc_util_bytewise_copy_from_nfc_mem() - Copies bytes from the NFC memory. + * + * @from: A pointer to the source memory. + * @to: A pointer to the destination memory. + * @size: The number of bytes to copy. + */ +static void nfc_util_bytewise_copy_from_nfc_mem(const void *from, + void *to, size_t n) +{ + unsigned int i; + const uint8_t *f = from; + uint8_t *t = to; + uint16_t *p; + uint16_t x; + + for (i = 0; i < n; i++, f++, t++) { + + p = (uint16_t *) (((unsigned long) f) & ~((unsigned long) 1)); + + x = __raw_readw(p); + + if (((unsigned long) f) & 0x1) + *t = (x >> 8) & 0xff; + else + *t = (x >> 0) & 0xff; + + } + +} + +/** + * nfc_util_bytewise_copy_to_nfc_mem() - Copies bytes to the NFC memory. + * + * @from: A pointer to the source memory. + * @to: A pointer to the destination memory. + * @size: The number of bytes to copy. + */ +static void nfc_util_bytewise_copy_to_nfc_mem(const void *from, + void *to, size_t n) +{ + unsigned int i; + const uint8_t *f = from; + uint8_t *t = to; + uint16_t *p; + uint16_t x; + + for (i = 0; i < n; i++, f++, t++) { + + p = (uint16_t *) (((unsigned long) t) & ~((unsigned long) 1)); + + x = __raw_readw(p); + + if (((unsigned long) t) & 0x1) + ((uint8_t *)(&x))[1] = *f; + else + ((uint8_t *)(&x))[0] = *f; + + __raw_writew(x, p); + + } + +} + +/** + * nfc_util_copy_from_nfc_mem() - Copies from the NFC memory to main memory. + * + * @from: A pointer to the source memory. + * @to: A pointer to the destination memory. + * @size: The number of bytes to copy. + */ +static void nfc_util_copy_from_nfc_mem(const void *from, void *to, size_t n) +{ + unsigned int chunk_count; + + /* + * Check if we're testing bytewise copies. + */ + + if (imx_nfc_module_force_bytewise_copy) + goto force_bytewise_copy; + + /* + * We'd like to use memcpy to get data out of the NFC but, because that + * memory responds only to 16- and 32-byte reads, we can only do so + * safely if both the start and end of both the source and destination + * are perfectly aligned on 4-byte boundaries. + */ + + if (!(((unsigned long) from) & 0x3) && !(((unsigned long) to) & 0x3)) { + + /* + * If control arrives here, both the source and destination are + * aligned on 4-byte boundaries. Compute the number of whole, + * 4-byte chunks we can move. + */ + + chunk_count = n / 4; + + /* + * Move all the chunks we can, and then update the pointers and + * byte count to show what's left. + */ + + if (chunk_count) { + memcpy(to, from, chunk_count * 4); + from += chunk_count * 4; + to += chunk_count * 4; + n -= chunk_count * 4; + } + + } + + /* + * Move what's left. + */ + +force_bytewise_copy: + + nfc_util_bytewise_copy_from_nfc_mem(from, to, n); + +} + +/** + * nfc_util_copy_to_nfc_mem() - Copies from main memory to the NFC memory. + * + * @from: A pointer to the source memory. + * @to: A pointer to the destination memory. + * @size: The number of bytes to copy. + */ +static void nfc_util_copy_to_nfc_mem(const void *from, void *to, size_t n) +{ + unsigned int chunk_count; + + /* + * Check if we're testing bytewise copies. + */ + + if (imx_nfc_module_force_bytewise_copy) + goto force_bytewise_copy; + + /* + * We'd like to use memcpy to get data into the NFC but, because that + * memory responds only to 16- and 32-byte writes, we can only do so + * safely if both the start and end of both the source and destination + * are perfectly aligned on 4-byte boundaries. + */ + + if (!(((unsigned long) from) & 0x3) && !(((unsigned long) to) & 0x3)) { + + /* + * If control arrives here, both the source and destination are + * aligned on 4-byte boundaries. Compute the number of whole, + * 4-byte chunks we can move. + */ + + chunk_count = n / 4; + + /* + * Move all the chunks we can, and then update the pointers and + * byte count to show what's left. + */ + + if (chunk_count) { + memcpy(to, from, chunk_count * 4); + from += chunk_count * 4; + to += chunk_count * 4; + n -= chunk_count * 4; + } + + } + + /* + * Move what's left. + */ + +force_bytewise_copy: + + nfc_util_bytewise_copy_to_nfc_mem(from, to, n); + +} + +/** + * nfc_util_copy_from_the_nfc() - Copies bytes out of the NFC. + * + * This function makes the data in the NFC look like a contiguous, model page. + * + * @this: Per-device data. + * @start: The index of the starting byte in the NFC. + * @buf: A pointer to the destination buffer. + * @len: The number of bytes to copy out. + */ +static void nfc_util_copy_from_the_nfc(struct imx_nfc_data *this, + unsigned int start, uint8_t *buf, unsigned int len) +{ + unsigned int i; + unsigned int count; + unsigned int offset; + unsigned int data_size; + unsigned int oob_size; + unsigned int total_size; + void *spare_base; + unsigned int first_spare; + void *from; + struct nfc_geometry *geometry = this->nfc_geometry; + + /* + * During initialization, the HIL will attempt to read ID bytes. For + * some NFC hardware versions, the ID bytes are deposited in the NFC + * memory, so this function will be called to deliver them. At that + * point, we won't know the NFC geometry. That's OK because we're only + * going to be reading a byte at a time. + * + * If we don't yet know the NFC geometry, just plug in some values that + * make things work for now. + */ + + if (unlikely(!geometry)) { + data_size = NFC_MAIN_BUF_SIZE; + oob_size = 0; + } else { + data_size = geometry->page_data_size; + oob_size = geometry->page_oob_size; + } + + total_size = data_size + oob_size; + + /* Validate. */ + + if ((start >= total_size) || ((start + len) > total_size)) { + dev_err(this->dev, "Bad copy from NFC memory: [%u, %u]\n", + start, len); + return; + } + + /* Check if we're copying anything at all. */ + + if (!len) + return; + + /* Check if anything comes from the main area. */ + + if (start < data_size) { + + /* Compute the bytes to copy from the main area. */ + + count = min(len, data_size - start); + + /* Copy. */ + + nfc_util_copy_from_nfc_mem(this->buffers + start, buf, count); + + buf += count; + start += count; + len -= count; + + } + + /* Check if we're done. */ + + if (!len) + return; + + /* Compute the base address of the spare buffers. */ + + spare_base = this->buffers + + (this->nfc->max_buffer_count * NFC_MAIN_BUF_SIZE); + + /* Discover in which spare buffer the copying begins. */ + + first_spare = (start - data_size) / geometry->spare_buf_size; + + /* Check if anything comes from the regular spare buffer area. */ + + if (first_spare < geometry->buffer_count) { + + /* Start copying from spare buffers. */ + + for (i = first_spare; i < geometry->buffer_count; i++) { + + /* Compute the offset into this spare area. */ + + offset = start - + (data_size + (geometry->spare_buf_size * i)); + + /* Compute the address of that offset. */ + + from = spare_base + offset + + (this->nfc->spare_buf_stride * i); + + /* Compute the bytes to copy from this spare area. */ + + count = min(len, geometry->spare_buf_size - offset); + + /* Copy. */ + + nfc_util_copy_from_nfc_mem(from, buf, count); + + buf += count; + start += count; + len -= count; + + } + + } + + /* Check if we're done. */ + + if (!len) + return; + + /* Compute the offset into the extra spare area. */ + + offset = start - + (data_size + (geometry->spare_buf_size*geometry->buffer_count)); + + /* Compute the address of that offset. */ + + from = spare_base + offset + + (this->nfc->spare_buf_stride * geometry->buffer_count); + + /* Compute the bytes to copy from the extra spare area. */ + + count = min(len, geometry->spare_buf_spill - offset); + + /* Copy. */ + + nfc_util_copy_from_nfc_mem(from, buf, count); + +} + +/** + * nfc_util_copy_to_the_nfc() - Copies bytes into the NFC memory. + * + * This function makes the data in the NFC look like a contiguous, model page. + * + * @this: Per-device data. + * @buf: A pointer to the source buffer. + * @start: The index of the starting byte in the NFC memory. + * @len: The number of bytes to copy in. + */ +static void nfc_util_copy_to_the_nfc(struct imx_nfc_data *this, + const uint8_t *buf, unsigned int start, unsigned int len) +{ + unsigned int i; + unsigned int count; + unsigned int offset; + unsigned int data_size; + unsigned int oob_size; + unsigned int total_size; + void *spare_base; + unsigned int first_spare; + void *to; + struct nfc_geometry *geometry = this->nfc_geometry; + + /* Establish some important facts. */ + + data_size = geometry->page_data_size; + oob_size = geometry->page_oob_size; + total_size = data_size + oob_size; + + /* Validate. */ + + if ((start >= total_size) || ((start + len) > total_size)) { + dev_err(this->dev, "Bad copy to NFC memory: [%u, %u]\n", + start, len); + return; + } + + /* Check if we're copying anything at all. */ + + if (!len) + return; + + /* Check if anything goes to the main area. */ + + if (start < data_size) { + + /* Compute the bytes to copy to the main area. */ + + count = min(len, data_size - start); + + /* Copy. */ + + nfc_util_copy_to_nfc_mem(buf, this->buffers + start, count); + + buf += count; + start += count; + len -= count; + + } + + /* Check if we're done. */ + + if (!len) + return; + + /* Compute the base address of the spare buffers. */ + + spare_base = this->buffers + + (this->nfc->max_buffer_count * NFC_MAIN_BUF_SIZE); + + /* Discover in which spare buffer the copying begins. */ + + first_spare = (start - data_size) / geometry->spare_buf_size; + + /* Check if anything goes to the regular spare buffer area. */ + + if (first_spare < geometry->buffer_count) { + + /* Start copying to spare buffers. */ + + for (i = first_spare; i < geometry->buffer_count; i++) { + + /* Compute the offset into this spare area. */ + + offset = start - + (data_size + (geometry->spare_buf_size * i)); + + /* Compute the address of that offset. */ + + to = spare_base + offset + + (this->nfc->spare_buf_stride * i); + + /* Compute the bytes to copy to this spare area. */ + + count = min(len, geometry->spare_buf_size - offset); + + /* Copy. */ + + nfc_util_copy_to_nfc_mem(buf, to, count); + + buf += count; + start += count; + len -= count; + + } + + } + + /* Check if we're done. */ + + if (!len) + return; + + /* Compute the offset into the extra spare area. */ + + offset = start - + (data_size + (geometry->spare_buf_size*geometry->buffer_count)); + + /* Compute the address of that offset. */ + + to = spare_base + offset + + (this->nfc->spare_buf_stride * geometry->buffer_count); + + /* Compute the bytes to copy to the extra spare area. */ + + count = min(len, geometry->spare_buf_spill - offset); + + /* Copy. */ + + nfc_util_copy_to_nfc_mem(buf, to, count); + +} + +/** + * nfc_util_isr() - i.MX NFC ISR. + * + * @irq: The arriving interrupt number. + * @context: A cookie for this ISR. + */ +static irqreturn_t nfc_util_isr(int irq, void *cookie) +{ + struct imx_nfc_data *this = cookie; + this->nfc->mask_interrupt(this); + this->nfc->clear_interrupt(this); + complete(&this->done); + return IRQ_HANDLED; +} + +/** + * nfc_util_send_cmd() - Sends a command to the current chip, without waiting. + * + * @this: Per-device data. + * @command: The command code. + */ + +static void nfc_util_send_cmd(struct imx_nfc_data *this, unsigned int command) +{ + + add_event("Entering nfc_util_send_cmd", 1); + + this->nfc->command_cycle(this, command); + + add_event("Exiting nfc_util_send_cmd", -1); + +} + +/** + * nfc_util_send_cmd_and_addrs() - Sends a cmd and addrs to the current chip. + * + * This function conveniently combines sending a command, and then sending + * optional addresses, waiting for the NFC to finish will all steps. + * + * @this: Per-device data. + * @command: The command code. + * @column: The column address to send, or -1 if no column address applies. + * @page: The page address to send, or -1 if no page address applies. + */ + +static void nfc_util_send_cmd_and_addrs(struct imx_nfc_data *this, + unsigned command, int column, int page) +{ + uint32_t page_mask; + + add_event("Entering nfc_util_send_cmd_and_addrs", 1); + + /* Send the command.*/ + + add_event("Sending the command...", 0); + + nfc_util_send_cmd(this, command); + + nfc_util_wait_for_the_nfc(this, false); + + /* Send the addresses. */ + + add_event("Sending the addresses...", 0); + + if (column != -1) { + + this->nfc->write_cycle(this, (column >> 0) & 0xff); + + if (is_large_page_chip(this)) + this->nfc->write_cycle(this, (column >> 8) & 0xff); + + } + + if (page != -1) { + + page_mask = this->nand.pagemask; + + do { + this->nfc->write_cycle(this, page & 0xff); + page_mask >>= 8; + page >>= 8; + } while (page_mask != 0); + + } + + add_event("Exiting nfc_util_send_cmd_and_addrs", -1); + +} + +/** + * nfc_2_x_exit() - Version-specific shut down. + * + * @this: Per-device data. + */ +static void nfc_2_x_exit(struct imx_nfc_data *this) +{ +} + +/** + * nfc_2_x_clear_interrupt() - Clears an interrupt. + * + * @this: Per-device data. + */ +static void nfc_2_x_clear_interrupt(struct imx_nfc_data *this) +{ + void *base = this->primary_regs; + raw_clr_mask_w(NFC_2_X_CONFIG2_INT_MSK, base + NFC_2_X_CONFIG2_REG_OFF); +} + +/** + * nfc_2_x_is_interrupting() - Returns the interrupt bit status. + * + * @this: Per-device data. + */ +static int nfc_2_x_is_interrupting(struct imx_nfc_data *this) +{ + void *base = this->primary_regs; + return raw_read_mask_w(NFC_2_X_CONFIG2_INT_MSK, + base + NFC_2_X_CONFIG2_REG_OFF); +} + +/** + * nfc_2_x_command_cycle() - Sends a command. + * + * @this: Per-device data. + * @command: The command code. + */ +static void nfc_2_x_command_cycle(struct imx_nfc_data *this, unsigned command) +{ + void *base = this->primary_regs; + + /* Write the command we want to send. */ + + __raw_writew(command, base + NFC_2_X_FLASH_CMD_REG_OFF); + + /* Launch a command cycle. */ + + __raw_writew(NFC_2_X_CONFIG2_FCMD_MSK, base + NFC_2_X_CONFIG2_REG_OFF); + +} + +/** + * nfc_2_x_write_cycle() - Writes a single byte. + * + * @this: Per-device data. + * @byte: The byte. + */ +static void nfc_2_x_write_cycle(struct imx_nfc_data *this, unsigned int byte) +{ + void *base = this->primary_regs; + + /* Give the NFC the byte we want to write. */ + + __raw_writew(byte, base + NFC_2_X_FLASH_ADDR_REG_OFF); + + /* Launch an address cycle. + * + * This is *sort* of a hack, but not really. The intent of the NFC + * design is for this operation to send an address byte. In fact, the + * NFC neither knows nor cares what we're sending. It justs runs a write + * cycle. + */ + + __raw_writew(NFC_2_X_CONFIG2_FADD_MSK, base + NFC_2_X_CONFIG2_REG_OFF); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, false); + +} + +/** + * nfc_2_0_init() - Version-specific hardware initialization. + * + * @this: Per-device data. + */ +static int nfc_2_0_init(struct imx_nfc_data *this) +{ + void *base = this->primary_regs; + + /* Initialize the interrupt machinery. */ + + this->nfc->mask_interrupt(this); + this->nfc->clear_interrupt(this); + + /* Unlock the NFC memory. */ + + __raw_writew(0x2, base + NFC_2_X_CONFIG_REG_OFF); + + /* Set the unlocked block range to cover the entire medium. */ + + __raw_writew(0 , base + NFC_2_0_UNLOCK_START_REG_OFF); + __raw_writew(~0, base + NFC_2_0_UNLOCK_END_REG_OFF); + + /* Unlock all blocks. */ + + __raw_writew(0x4, base + NFC_2_X_WR_PROT_REG_OFF); + + /* Return success. */ + + return 0; + +} + +/** + * nfc_2_0_mask_interrupt() - Masks interrupts. + * + * @this: Per-device data. + */ +static void nfc_2_0_mask_interrupt(struct imx_nfc_data *this) +{ + void *base = this->primary_regs; + raw_set_mask_w(NFC_2_0_CONFIG1_INT_MSK_MSK, + base + NFC_2_0_CONFIG1_REG_OFF); +} + +/** + * nfc_2_0_unmask_interrupt() - Unmasks interrupts. + * + * @this: Per-device data. + */ +static void nfc_2_0_unmask_interrupt(struct imx_nfc_data *this) +{ + void *base = this->primary_regs; + raw_clr_mask_w(NFC_2_0_CONFIG1_INT_MSK_MSK, + base + NFC_2_0_CONFIG1_REG_OFF); +} + +/** + * nfc_2_0_set_ecc() - Turns ECC on or off. + * + * @this: Per-device data. + * @on: Indicates if ECC should be on or off. + */ +static void nfc_2_0_set_ecc(struct imx_nfc_data *this, int on) +{ + void *base = this->primary_regs; + + if (on) + raw_set_mask_w(NFC_2_0_CONFIG1_ECC_EN_MSK, + base + NFC_2_0_CONFIG1_REG_OFF); + else + raw_clr_mask_w(NFC_2_0_CONFIG1_ECC_EN_MSK, + base + NFC_2_0_CONFIG1_REG_OFF); + +} + +/** + * nfc_2_0_get_ecc_status() - Reports ECC errors. + * + * @this: Per-device data. + */ +static int nfc_2_0_get_ecc_status(struct imx_nfc_data *this) +{ + unsigned int i; + void *base = this->primary_regs; + uint16_t status_reg; + unsigned int buffer_status[4]; + int status; + + /* Get the entire status register. */ + + status_reg = __raw_readw(base + NFC_2_0_ECC_STATUS_REG_OFF); + + /* Pick out the status for each buffer. */ + + buffer_status[0] = (status_reg & NFC_2_0_ECC_STATUS_NOSER1_MSK) + >> NFC_2_0_ECC_STATUS_NOSER1_POS; + + buffer_status[1] = (status_reg & NFC_2_0_ECC_STATUS_NOSER2_MSK) + >> NFC_2_0_ECC_STATUS_NOSER2_POS; + + buffer_status[2] = (status_reg & NFC_2_0_ECC_STATUS_NOSER3_MSK) + >> NFC_2_0_ECC_STATUS_NOSER3_POS; + + buffer_status[3] = (status_reg & NFC_2_0_ECC_STATUS_NOSER4_MSK) + >> NFC_2_0_ECC_STATUS_NOSER4_POS; + + /* Loop through the buffers we're actually using. */ + + status = 0; + + for (i = 0; i < this->nfc_geometry->buffer_count; i++) { + + if (buffer_status[i] > this->nfc_geometry->ecc_strength) { + status = -1; + break; + } + + status += buffer_status[i]; + + } + + /* Return the final result. */ + + return status; + +} + +/** + * nfc_2_0_get_symmetric() - Indicates if the clock is symmetric. + * + * @this: Per-device data. + */ +static int nfc_2_0_get_symmetric(struct imx_nfc_data *this) +{ + void *base = this->primary_regs; + + return !!raw_read_mask_w(NFC_2_0_CONFIG1_ONE_CYLE_MSK, + base + NFC_2_0_CONFIG1_REG_OFF); + +} + +/** + * nfc_2_0_set_symmetric() - Turns symmetric clock mode on or off. + * + * @this: Per-device data. + */ +static void nfc_2_0_set_symmetric(struct imx_nfc_data *this, int on) +{ + void *base = this->primary_regs; + + if (on) + raw_set_mask_w(NFC_2_0_CONFIG1_ONE_CYLE_MSK, + base + NFC_2_0_CONFIG1_REG_OFF); + else + raw_clr_mask_w(NFC_2_0_CONFIG1_ONE_CYLE_MSK, + base + NFC_2_0_CONFIG1_REG_OFF); + +} + +/** + * nfc_2_0_set_geometry() - Configures for the medium geometry. + * + * @this: Per-device data. + */ +static int nfc_2_0_set_geometry(struct imx_nfc_data *this) +{ + struct physical_geometry *physical = &this->physical_geometry; + + /* Select an NFC geometry. */ + + switch (physical->page_data_size) { + + case 512: + this->nfc_geometry = &nfc_geometry_512_16_RS_ECC4; + break; + + case 2048: + this->nfc_geometry = &nfc_geometry_2K_64_RS_ECC4; + break; + + default: + dev_err(this->dev, "NFC can't handle page size: %u", + physical->page_data_size); + return !0; + break; + + } + + /* + * This NFC version receives page size information from a register + * that's external to the NFC. We must rely on platform-specific code + * to set this register for us. + */ + + return this->pdata->set_page_size(physical->page_data_size); + +} + +/** + * nfc_2_0_select_chip() - Selects the current chip. + * + * @this: Per-device data. + * @chip: The chip number to select, or -1 to select no chip. + */ +static void nfc_2_0_select_chip(struct imx_nfc_data *this, int chip) +{ +} + +/** + * nfc_2_0_read_cycle() - Applies a single read cycle to the current chip. + * + * @this: Per-device data. + */ +static unsigned int nfc_2_0_read_cycle(struct imx_nfc_data *this) +{ + uint8_t byte; + unsigned int result; + void *base = this->primary_regs; + + /* Read into main buffer 0. */ + + __raw_writew(0x0, base + NFC_2_0_BUF_ADDR_REG_OFF); + + /* Launch a "Data Out" operation. */ + + __raw_writew(0x4 << NFC_2_X_CONFIG2_FDO_POS, + base + NFC_2_X_CONFIG2_REG_OFF); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, false); + + /* Get the result from the NFC memory. */ + + nfc_util_copy_from_the_nfc(this, 0, &byte, 1); + result = byte; + + /* Return the results. */ + + return result; + +} + +/** + * nfc_2_0_read_page() - Reads a page from the current chip into the NFC. + * + * @this: Per-device data. + */ +static void nfc_2_0_read_page(struct imx_nfc_data *this) +{ + unsigned int i; + void *base = this->primary_regs; + + /* Loop over the number of buffers in use. */ + + for (i = 0; i < this->nfc_geometry->buffer_count; i++) { + + /* Make the NFC read into the current buffer. */ + + __raw_writew(i << NFC_2_0_BUF_ADDR_RBA_POS, + base + NFC_2_0_BUF_ADDR_REG_OFF); + + /* Launch a page data out operation. */ + + __raw_writew(0x1 << NFC_2_X_CONFIG2_FDO_POS, + base + NFC_2_X_CONFIG2_REG_OFF); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, true); + + } + +} + +/** + * nfc_2_0_send_page() - Sends a page from the NFC to the current chip. + * + * @this: Per-device data. + */ +static void nfc_2_0_send_page(struct imx_nfc_data *this) +{ + unsigned int i; + void *base = this->primary_regs; + + /* Loop over the number of buffers in use. */ + + for (i = 0; i < this->nfc_geometry->buffer_count; i++) { + + /* Make the NFC send from the current buffer. */ + + __raw_writew(i << NFC_2_0_BUF_ADDR_RBA_POS, + base + NFC_2_0_BUF_ADDR_REG_OFF); + + /* Launch a page data in operation. */ + + __raw_writew(0x1 << NFC_2_X_CONFIG2_FDI_POS, + base + NFC_2_X_CONFIG2_REG_OFF); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, true); + + } + +} + +/** + * nfc_3_2_init() - Hardware initialization. + * + * @this: Per-device data. + */ +static int nfc_3_2_init(struct imx_nfc_data *this) +{ + int error; + unsigned int no_sdma; + unsigned int fmp; + unsigned int rbb_mode; + unsigned int num_of_devices; + unsigned int dma_mode; + unsigned int sbb; + unsigned int nf_big; + unsigned int sb2r; + unsigned int fw; + unsigned int too; + unsigned int add_op; + uint32_t config3; + void *primary_base = this->primary_regs; + void *secondary_base = this->secondary_regs; + + /* Initialize the interrupt machinery. */ + + this->nfc->mask_interrupt(this); + this->nfc->clear_interrupt(this); + + /* Set up the clock. */ + + error = this->nfc->set_closest_cycle(this, + this->pdata->target_cycle_in_ns); + + if (error) + return !0; + + /* We never read the spare area alone. */ + + raw_clr_mask_l(NFC_3_2_CONFIG1_SP_EN_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* Tell the NFC the "Read Status" command code. */ + + raw_clr_mask_l(NFC_3_2_CONFIG2_ST_CMD_MSK, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); + + raw_set_mask_l(NAND_CMD_STATUS << NFC_3_2_CONFIG2_ST_CMD_POS, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); + + /* + * According to erratum ENGcm09051, the CONFIG3 register doesn't reset + * correctly, so we need to re-build the entire register just in case. + */ + + /* + * Set the NO_SDMA bit to tell the NFC that we are NOT using SDMA. If + * you clear this bit (to indicates you *are* using SDMA), but you + * don't actually set up SDMA, the NFC has been observed to crash the + * hardware when it asserts its DMA request signals. In the future, we + * *may* use SDMA, but it's not worth the effort at this writing. + */ + + no_sdma = 0x1; + + /* + * Set the default FIFO Mode Protection (128 bytes). FMP doesn't work if + * the NO_SDMA bit is set. + */ + + fmp = 0x2; + + /* + * The rbb_mode bit determines how the NFC figures out whether chips are + * ready during automatic operations only (this has no effect on atomic + * operations). The two choices are either to monitor the ready/busy + * signals, or to read the status register. We monitor the ready/busy + * signals. + */ + + rbb_mode = 0x1; + + /* + * We don't yet know how many devices are connected. We'll find out in + * out in nfc_3_2_set_geometry(). + */ + + num_of_devices = 0; + + /* Set the default DMA mode. */ + + dma_mode = 0x0; + + /* Set the default status busy bit. */ + + sbb = 0x6; + + /* Little-endian (the default). */ + + nf_big = 0x0; + + /* Set the default (standard) status bit to record. */ + + sb2r = 0x0; + + /* We support only 8-bit Flash bus width. */ + + fw = 0x1; + + /* We don't support "two-on-one." */ + + too = 0x0; + + /* Set the addressing option. */ + + add_op = 0x3; + + /* Set the CONFIG3 register. */ + + config3 = 0; + + config3 |= no_sdma << NFC_3_2_CONFIG3_NO_SDMA_POS; + config3 |= fmp << NFC_3_2_CONFIG3_FMP_POS; + config3 |= rbb_mode << NFC_3_2_CONFIG3_RBB_MODE_POS; + config3 |= num_of_devices << NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS; + config3 |= dma_mode << NFC_3_2_CONFIG3_DMA_MODE_POS; + config3 |= sbb << NFC_3_2_CONFIG3_SBB_POS; + config3 |= nf_big << NFC_3_2_CONFIG3_NF_BIG_POS; + config3 |= sb2r << NFC_3_2_CONFIG3_SB2R_POS; + config3 |= fw << NFC_3_2_CONFIG3_FW_POS; + config3 |= too << NFC_3_2_CONFIG3_TOO_POS; + config3 |= add_op << NFC_3_2_CONFIG3_ADD_OP_POS; + + __raw_writel(config3, secondary_base + NFC_3_2_CONFIG3_REG_OFF); + + /* Return success. */ + + return 0; + +} + +/** + * nfc_3_2_set_geometry() - Configures for the medium geometry. + * + * @this: Per-device data. + */ +static int nfc_3_2_set_geometry(struct imx_nfc_data *this) +{ + unsigned int ps; + unsigned int cmd_phases; + unsigned int pages_per_chip; + unsigned int addr_phases0; + unsigned int addr_phases1; + unsigned int pages_per_block; + unsigned int ecc_mode; + unsigned int ppb; + unsigned int spas; + unsigned int mask; + uint32_t config2; + unsigned int num_of_devices; + uint32_t config3; + unsigned int x; + unsigned int chip; + struct physical_geometry *physical = &this->physical_geometry; + void *secondary_base = this->secondary_regs; + + /* + * Select an NFC geometry based on the physical geometry and the + * capabilities of this NFC. + */ + + switch (physical->page_data_size) { + + case 512: + this->nfc_geometry = &nfc_geometry_512_16_BCH_ECC4; + ps = 0; + break; + + case 2048: + this->nfc_geometry = &nfc_geometry_2K_64_BCH_ECC4; + ps = 1; + break; + + case 4096: + + switch (this->physical_geometry.page_oob_size) { + + case 128: + this->nfc_geometry = &nfc_geometry_4K_128_BCH_ECC4; + break; + + case 218: + this->nfc_geometry = &nfc_geometry_4K_218_BCH_ECC8; + break; + + default: + dev_err(this->dev, + "NFC can't handle page geometry: %u+%u", + physical->page_data_size, + physical->page_oob_size); + return !0; + break; + + } + + ps = 2; + + break; + + default: + dev_err(this->dev, "NFC can't handle page size: %u", + physical->page_data_size); + return !0; + break; + + } + + /* Compute the ECC mode. */ + + switch (this->nfc_geometry->ecc_strength) { + + case 4: + ecc_mode = 0; + break; + + case 8: + ecc_mode = 1; + break; + + default: + dev_err(this->dev, "NFC can't handle ECC strength: %u", + this->nfc_geometry->ecc_strength); + return !0; + break; + + } + + /* Compute the pages per block. */ + + pages_per_block = physical->block_size / physical->page_data_size; + + switch (pages_per_block) { + case 32: + ppb = 0; + break; + case 64: + ppb = 1; + break; + case 128: + ppb = 2; + break; + case 256: + ppb = 3; + break; + default: + dev_err(this->dev, "NFC can't handle pages per block: %d", + pages_per_block); + return !0; + break; + } + + /* + * The hardware needs to know the physical size of the spare area, in + * units of half-words (16 bits). This may be different from the amount + * of the spare area we actually expose to MTD. For example, for for + * 2K+112, we only expose 64 spare bytes, but the hardware needs to know + * the real facts. + */ + + spas = this->physical_geometry.page_oob_size >> 1; + + /* + * The number of command phases needed to read a page is directly + * dependent on whether this is a small page or large page device. Large + * page devices need more address phases, terminated by a second command + * phase. + */ + + cmd_phases = is_large_page_chip(this) ? 1 : 0; + + /* + * The num_adr_phases1 field contains the number of phases needed to + * transmit addresses for read and program operations. This is the sum + * of the number of phases for a page address and the number of phases + * for a column address. + * + * The number of phases for a page address is the number of bytes needed + * to contain a page address. + * + * The number of phases for a column address is the number of bytes + * needed to contain a column address. + * + * After computing the sum, we subtract three because a value of zero in + * this field indicates three address phases, and this is the minimum + * number of phases the hardware can comprehend. + * + * We compute the number of phases based on the *physical* geometry, not + * the NFC geometry. For example, even if we are treating a very large + * device as if it contains fewer pages than it actually does, the + * hardware still needs the additional address phases. + */ + + pages_per_chip = + physical->chip_size >> (fls(physical->page_data_size) - 1); + + addr_phases1 = (fls(pages_per_chip) >> 3) + 1; + + addr_phases1 += (fls(physical->page_data_size) >> 3) + 1; + + addr_phases1 -= 3; + + /* + * The num_adr_phases0 field contains the number of phases needed to + * transmit a page address for an erase operation. That is, this is + * the value of addr_phases1, less the number of phases for the column + * address. + * + * The hardware expresses this phase count as one or two cycles less + * than the count indicated by add_phases1 (see the reference manual). + */ + + addr_phases0 = is_large_page_chip(this) ? 1 : 0; + + /* Set the CONFIG2 register. */ + + mask = + NFC_3_2_CONFIG2_PS_MSK | + NFC_3_2_CONFIG2_CMD_PHASES_MSK | + NFC_3_2_CONFIG2_ADDR_PHASES0_MSK | + NFC_3_2_CONFIG2_ECC_MODE_MSK | + NFC_3_2_CONFIG2_PPB_MSK | + NFC_3_2_CONFIG2_ADDR_PHASES1_MSK | + NFC_3_2_CONFIG2_SPAS_MSK ; + + config2 = __raw_readl(secondary_base + NFC_3_2_CONFIG2_REG_OFF); + + config2 &= ~mask; + + config2 |= ps << NFC_3_2_CONFIG2_PS_POS; + config2 |= cmd_phases << NFC_3_2_CONFIG2_CMD_PHASES_POS; + config2 |= addr_phases0 << NFC_3_2_CONFIG2_ADDR_PHASES0_POS; + config2 |= ecc_mode << NFC_3_2_CONFIG2_ECC_MODE_POS; + config2 |= ppb << NFC_3_2_CONFIG2_PPB_POS; + config2 |= addr_phases1 << NFC_3_2_CONFIG2_ADDR_PHASES1_POS; + config2 |= spas << NFC_3_2_CONFIG2_SPAS_POS; + + config2 = __raw_writel(config2, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); + + /* + * Compute the num_of_devices field. + * + * It's very important to set this field correctly. This controls the + * set of ready/busy lines to which the NFC listens with automatic + * transactions. If this number is too large, the NFC will listen to + * ready/busy signals that are electrically floating, or it will try to + * read the status registers of chips that don't exist. Conversely, if + * the number is too small, the NFC could believe an operation is + * finished when some chips are still busy. + */ + + num_of_devices = physical->chip_count - 1; + + /* Set the CONFIG3 register. */ + + mask = NFC_3_2_CONFIG3_NUM_OF_DEVICES_MSK; + + config3 = __raw_readl(secondary_base + NFC_3_2_CONFIG3_REG_OFF); + + config3 &= ~mask; + + config3 |= num_of_devices << NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS; + + __raw_writel(config3, secondary_base + NFC_3_2_CONFIG3_REG_OFF); + + /* + * Check if the physical chip count is a power of 2. If not, then + * automatic operations aren't available. This is because we use an + * addressing option (see the ADD_OP field of CONFIG3) that requires + * a number of chips that is a power of 2. + */ + + if (ffs(physical->chip_count) != fls(physical->chip_count)) { + this->nfc->start_auto_read = 0; + this->nfc->start_auto_write = 0; + this->nfc->start_auto_erase = 0; + } + + /* Unlock the NFC RAM. */ + + x = __raw_readl(secondary_base + NFC_3_2_WRPROT_REG_OFF); + x &= ~NFC_3_2_WRPROT_BLS_MSK; + x |= 0x2 << NFC_3_2_WRPROT_BLS_POS; + __raw_writel(x, secondary_base + NFC_3_2_WRPROT_REG_OFF); + + /* Loop over chip selects, setting the unlocked ranges. */ + + for (chip = 0; chip < this->nfc->max_chip_count; chip++) { + + /* Set the unlocked range to cover the entire chip.*/ + + __raw_writel(0xffff0000, secondary_base + + NFC_3_2_UNLOCK_BLK_ADD0_REG_OFF + (chip * 4)); + + /* Unlock. */ + + x = __raw_readl(secondary_base + NFC_3_2_WRPROT_REG_OFF); + x &= ~(NFC_3_2_WRPROT_CS2L_MSK | NFC_3_2_WRPROT_WPC_MSK); + x |= chip << NFC_3_2_WRPROT_CS2L_POS; + x |= 0x4 << NFC_3_2_WRPROT_WPC_POS ; + __raw_writel(x, secondary_base + NFC_3_2_WRPROT_REG_OFF); + + } + + /* Return success. */ + + return 0; + +} + +/** + * nfc_3_2_exit() - Hardware cleanup. + * + * @this: Per-device data. + */ +static void nfc_3_2_exit(struct imx_nfc_data *this) +{ +} + +/** + * nfc_3_2_set_closest_cycle() - Version-specific hardware cleanup. + * + * @this: Per-device data. + */ +static int nfc_3_2_set_closest_cycle(struct imx_nfc_data *this, unsigned ns) +{ + struct clk *parent_clock; + unsigned long parent_clock_rate_in_hz; + unsigned long sym_low_clock_rate_in_hz; + unsigned long asym_low_clock_rate_in_hz; + unsigned int sym_high_cycle_in_ns; + unsigned int asym_high_cycle_in_ns; + + /* + * According to ENGcm09121: + * + * - If the NFC is set to SYMMETRIC mode, the NFC clock divider must + * divide the EMI Slow Clock by NO MORE THAN 4. + * + * - If the NFC is set for ASYMMETRIC mode, the NFC clock divider must + * divide the EMI Slow Clock by NO MORE THAN 3. + * + * We need to compute the corresponding cycle time constraints. Start + * by getting information about the parent clock. + */ + + parent_clock = clk_get_parent(this->clock); + parent_clock_rate_in_hz = clk_get_rate(parent_clock); + + /* Compute the limit frequencies. */ + + sym_low_clock_rate_in_hz = parent_clock_rate_in_hz / 4; + asym_low_clock_rate_in_hz = parent_clock_rate_in_hz / 3; + + /* Compute the corresponding limit cycle periods. */ + + sym_high_cycle_in_ns = 1000000000 / sym_low_clock_rate_in_hz; + asym_high_cycle_in_ns = (1000000000 / asym_low_clock_rate_in_hz) * 2; + + /* Attempt to implement the given cycle. */ + + return nfc_util_set_best_cycle(this, ns, + ns > asym_high_cycle_in_ns, ns > sym_high_cycle_in_ns); + +} + +/** + * nfc_3_2_mask_interrupt() - Masks interrupts. + * + * @this: Per-device data. + */ +static void nfc_3_2_mask_interrupt(struct imx_nfc_data *this) +{ + void *secondary_base = this->secondary_regs; + raw_set_mask_l(NFC_3_2_CONFIG2_INT_MSK_MSK, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); +} + +/** + * nfc_3_2_unmask_interrupt() - Unmasks interrupts. + * + * @this: Per-device data. + */ +static void nfc_3_2_unmask_interrupt(struct imx_nfc_data *this) +{ + void *secondary_base = this->secondary_regs; + raw_clr_mask_l(NFC_3_2_CONFIG2_INT_MSK_MSK, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); +} + +/** + * nfc_3_2_clear_interrupt() - Clears an interrupt. + * + * @this: Per-device data. + */ +static void nfc_3_2_clear_interrupt(struct imx_nfc_data *this) +{ + int done; + void *secondary_base = this->secondary_regs; + + /* Request IP bus interface access. */ + + raw_set_mask_l(NFC_3_2_IPC_CREQ_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); + + /* Wait for access. */ + + do + done = !!raw_read_mask_l(NFC_3_2_IPC_CACK_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); + while (!done); + + /* Clear the interrupt. */ + + raw_clr_mask_l(NFC_3_2_IPC_INT_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); + + /* Release the IP bus interface. */ + + raw_clr_mask_l(NFC_3_2_IPC_CREQ_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); + +} + +/** + * nfc_3_2_is_interrupting() - Returns the interrupt bit status. + * + * @this: Per-device data. + */ +static int nfc_3_2_is_interrupting(struct imx_nfc_data *this) +{ + void *secondary_base = this->secondary_regs; + return !!raw_read_mask_l(NFC_3_2_IPC_INT_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); +} + +/** + * nfc_3_2_is_ready() - Returns the ready/busy status. + * + * @this: Per-device data. + */ +static int nfc_3_2_is_ready(struct imx_nfc_data *this) +{ + void *secondary_base = this->secondary_regs; + return !!raw_read_mask_l(NFC_3_2_IPC_RB_B_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); +} + +/** + * nfc_3_2_set_force_ce() - Can force CE to be asserted always. + * + * @this: Per-device data. + * @on: Indicates if the hardware CE signal should be asserted always. + */ +static void nfc_3_2_set_force_ce(struct imx_nfc_data *this, int on) +{ + void *primary_base = this->primary_regs; + + if (on) + raw_set_mask_l(NFC_3_2_CONFIG1_NF_CE_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + else + raw_clr_mask_l(NFC_3_2_CONFIG1_NF_CE_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + +} + +/** + * nfc_3_2_set_ecc() - Turns ECC on or off. + * + * @this: Per-device data. + * @on: Indicates if ECC should be on or off. + */ +static void nfc_3_2_set_ecc(struct imx_nfc_data *this, int on) +{ + void *secondary_base = this->secondary_regs; + + if (on) + raw_set_mask_l(NFC_3_2_CONFIG2_ECC_EN_MSK, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); + else + raw_clr_mask_l(NFC_3_2_CONFIG2_ECC_EN_MSK, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); + +} + +/** + * nfc_3_2_get_ecc_status() - Reports ECC errors. + * + * @this: Per-device data. + */ +static int nfc_3_2_get_ecc_status(struct imx_nfc_data *this) +{ + unsigned int i; + void *base = this->primary_regs; + uint16_t status_reg; + unsigned int buffer_status[8]; + int status; + + /* Get the entire status register. */ + + status_reg = __raw_readw(base + NFC_3_2_ECC_STATUS_REG_OFF); + + /* Pick out the status for each buffer. */ + + buffer_status[0] = (status_reg & NFC_3_2_ECC_STATUS_NOBER1_MSK) + >> NFC_3_2_ECC_STATUS_NOBER1_POS; + + buffer_status[1] = (status_reg & NFC_3_2_ECC_STATUS_NOBER2_MSK) + >> NFC_3_2_ECC_STATUS_NOBER2_POS; + + buffer_status[2] = (status_reg & NFC_3_2_ECC_STATUS_NOBER3_MSK) + >> NFC_3_2_ECC_STATUS_NOBER3_POS; + + buffer_status[3] = (status_reg & NFC_3_2_ECC_STATUS_NOBER4_MSK) + >> NFC_3_2_ECC_STATUS_NOBER4_POS; + + buffer_status[4] = (status_reg & NFC_3_2_ECC_STATUS_NOBER5_MSK) + >> NFC_3_2_ECC_STATUS_NOBER5_POS; + + buffer_status[5] = (status_reg & NFC_3_2_ECC_STATUS_NOBER6_MSK) + >> NFC_3_2_ECC_STATUS_NOBER6_POS; + + buffer_status[6] = (status_reg & NFC_3_2_ECC_STATUS_NOBER7_MSK) + >> NFC_3_2_ECC_STATUS_NOBER7_POS; + + buffer_status[7] = (status_reg & NFC_3_2_ECC_STATUS_NOBER8_MSK) + >> NFC_3_2_ECC_STATUS_NOBER8_POS; + + /* Loop through the buffers we're actually using. */ + + status = 0; + + for (i = 0; i < this->nfc_geometry->buffer_count; i++) { + + if (buffer_status[i] > this->nfc_geometry->ecc_strength) { + status = -1; + break; + } + + status += buffer_status[i]; + + } + + /* Return the final result. */ + + return status; + +} + +/** + * nfc_3_2_get_symmetric() - Indicates if the clock is symmetric. + * + * @this: Per-device data. + */ +static int nfc_3_2_get_symmetric(struct imx_nfc_data *this) +{ + void *secondary_base = this->secondary_regs; + + return !!raw_read_mask_w(NFC_3_2_CONFIG2_SYM_MSK, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); + +} + +/** + * nfc_3_2_set_symmetric() - Turns symmetric clock mode on or off. + * + * @this: Per-device data. + */ +static void nfc_3_2_set_symmetric(struct imx_nfc_data *this, int on) +{ + void *secondary_base = this->secondary_regs; + + if (on) + raw_set_mask_l(NFC_3_2_CONFIG2_SYM_MSK, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); + else + raw_clr_mask_l(NFC_3_2_CONFIG2_SYM_MSK, + secondary_base + NFC_3_2_CONFIG2_REG_OFF); + +} + +/** + * nfc_3_2_select_chip() - Selects the current chip. + * + * @this: Per-device data. + * @chip: The chip number to select, or -1 to select no chip. + */ +static void nfc_3_2_select_chip(struct imx_nfc_data *this, int chip) +{ + unsigned long x; + void *primary_base = this->primary_regs; + + if (chip < 0) + return; + + x = __raw_readl(primary_base + NFC_3_2_CONFIG1_REG_OFF); + + x &= ~NFC_3_2_CONFIG1_CS_MSK; + + x |= (chip << NFC_3_2_CONFIG1_CS_POS) & NFC_3_2_CONFIG1_CS_MSK; + + __raw_writel(x, primary_base + NFC_3_2_CONFIG1_REG_OFF); + +} + +/** + * nfc_3_2_command_cycle() - Sends a command. + * + * @this: Per-device data. + * @command: The command code. + */ +static void nfc_3_2_command_cycle(struct imx_nfc_data *this, unsigned command) +{ + void *primary_base = this->primary_regs; + + /* Write the command we want to send. */ + + __raw_writel(command, primary_base + NFC_3_2_CMD_REG_OFF); + + /* Launch a command cycle. */ + + __raw_writel(NFC_3_2_LAUNCH_FCMD_MSK, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + +} + +/** + * nfc_3_2_write_cycle() - writes a single byte. + * + * @this: Per-device data. + * @byte: The byte. + */ +static void nfc_3_2_write_cycle(struct imx_nfc_data *this, unsigned int byte) +{ + void *primary_base = this->primary_regs; + + /* Give the NFC the byte we want to write. */ + + __raw_writel(byte, primary_base + NFC_3_2_ADD0_REG_OFF); + + /* Launch an address cycle. + * + * This is *sort* of a hack, but not really. The intent of the NFC + * design is for this operation to send an address byte. In fact, the + * NFC neither knows nor cares what we're sending. It justs runs a write + * cycle. + */ + + __raw_writel(NFC_3_2_LAUNCH_FADD_MSK, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, false); + +} + +/** + * nfc_3_2_read_cycle() - Applies a single read cycle to the current chip. + * + * @this: Per-device data. + */ +static unsigned int nfc_3_2_read_cycle(struct imx_nfc_data *this) +{ + unsigned int result; + void *primary_base = this->primary_regs; + + /* Launch a "Data Out" operation. */ + + __raw_writel(0x4 << NFC_3_2_LAUNCH_FDO_POS, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, false); + + /* Get the result. */ + + result = __raw_readl(primary_base + NFC_3_2_CONFIG1_REG_OFF) + >> NFC_3_2_CONFIG1_STATUS_POS; + result &= 0xff; + + /* Return the result. */ + + return result; + +} + +/** + * nfc_3_2_read_page() - Reads a page into the NFC memory. + * + * @this: Per-device data. + */ +static void nfc_3_2_read_page(struct imx_nfc_data *this) +{ + void *primary_base = this->primary_regs; + + /* Start reading into buffer 0. */ + + raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* Launch a page data out operation. */ + + __raw_writel(0x1 << NFC_3_2_LAUNCH_FDO_POS, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, true); + +} + +/** + * nfc_3_2_send_page() - Sends a page from the NFC to the current chip. + * + * @this: Per-device data. + */ +static void nfc_3_2_send_page(struct imx_nfc_data *this) +{ + void *primary_base = this->primary_regs; + + /* Start sending from buffer 0. */ + + raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* Launch a page data in operation. */ + + __raw_writel(NFC_3_2_LAUNCH_FDI_MSK, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, true); + +} + +/** + * nfc_3_2_add_state_events() - Adds events to display important state. + * + * @this: Per-device data. + */ +static void nfc_3_2_add_state_events(struct imx_nfc_data *this) +{ +#ifdef EVENT_REPORTING + void *secondary_base = this->secondary_regs; + + add_state_event_l + ( + secondary_base + NFC_3_2_IPC_REG_OFF, + NFC_3_2_IPC_INT_MSK, + " Interrupt : 0", + " Interrupt : X" + ); + + add_state_event_l + ( + secondary_base + NFC_3_2_IPC_REG_OFF, + NFC_3_2_IPC_AUTO_PROG_DONE_MSK, + " auto_prog_done: 0", + " auto_prog_done: X" + ); + + add_state_event_l + ( + secondary_base + NFC_3_2_IPC_REG_OFF, + NFC_3_2_IPC_RB_B_MSK, + " Medium : Busy", + " Medium : Ready" + ); +#endif +} + +/** + * nfc_3_2_get_auto_loop_params() - Gets automatic operation loop parameters. + * + * This function and the corresponding "setter" enable the automatic operations + * to keep some state as they iterate over chips. + * + * The most "obvious" way to save state would be to allocate a private data + * structure and hang it off the owning struct nfc_hal. On the other hand, + * writing the code to allocate the memory and then release it when the NFC + * shuts down is annoying - and we have some perfectly good memory in the NFC + * hardware that we can use. Since we only use two commands at a time, we can + * stash our loop limits and loop index in the top 16 bits of the NAND_CMD + * register. To paraphrase the reference manual: + * + * + * NAND_CMD + * + * |<-- 4 bits -->|<-- 4 bits -->|<-- 8 bits -->| + * +----------------+---------------+--------------------------------+ + * | First | Last | Loop Index | + * +----------------+---------------+--------------------------------+ + * | NAND COMMAND1 | NAND COMMAND0 | + * +--------------------------------+--------------------------------+ + * |<-- 16 bits -->|<-- 16 bits -->| + * + * + * @this: Per-device data. + * @first: A pointer to a variable that will receive the first chip number. + * @last: A pointer to a variable that will receive the last chip number. + * @index: A pointer to a variable that will receive the current chip number. + */ +static void nfc_3_2_get_auto_loop_params(struct imx_nfc_data *this, + unsigned *first, unsigned *last, unsigned *index) +{ + uint32_t x; + void *primary_base = this->primary_regs; + + x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF); + + *first = (x >> 28) & 0x0f; + *last = (x >> 24) & 0x0f; + *index = (x >> 16) & 0xff; + +} + +/** + * nfc_3_2_set_auto_loop_params() - Sets automatic operation loop parameters. + * + * See nfc_3_2_get_auto_loop_params() for detailed information about these + * functions. + * + * @this: Per-device data. + * @first: The first chip number. + * @last: The last chip number. + * @index: The current chip number. + */ +static void nfc_3_2_set_auto_loop_params(struct imx_nfc_data *this, + unsigned first, unsigned last, unsigned index) +{ + uint32_t x; + void *primary_base = this->primary_regs; + + x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF); + + x &= 0x0000ffff; + x |= (first & 0x0f) << 28; + x |= (last & 0x0f) << 24; + x |= (index & 0xff) << 16; + + __raw_writel(x, primary_base + NFC_3_2_CMD_REG_OFF); + +} + +/** + * nfc_3_2_get_auto_addresses() - Gets automatic operation addresses. + * + * @this: Per-device data. + * @group: The address group number. + * @chip: A pointer to a variable that will receive the chip number. + * @column: A pointer to a variable that will receive the column address. + * A NULL pointer indicates there is no column address. + * @page: A pointer to a variable that will receive the page address. + */ +static void nfc_3_2_get_auto_addresses(struct imx_nfc_data *this, + unsigned group, unsigned *chip, unsigned *column, unsigned *page) +{ + uint32_t x; + unsigned int chip_count; + unsigned int cs_width; + unsigned int cs_mask; + unsigned int page_lsbs; + unsigned int page_msbs; + uint32_t *low; + uint16_t *high; + void *primary_base = this->primary_regs; + void *secondary_base = this->secondary_regs; + + /* + * The width of the chip select field depends on the number of connected + * chips. + * + * Notice that these computations work only if the number of chips is a + * power of 2. In fact, that is a fundamental limitation for using + * automatic operations. + */ + + x = __raw_readl(secondary_base + NFC_3_2_CONFIG3_REG_OFF); + + chip_count = + (x & NFC_3_2_CONFIG3_NUM_OF_DEVICES_MSK) >> + NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS; + chip_count++; + + cs_width = ffs(chip_count) - 1; + cs_mask = chip_count - 1; + + /* Construct pointers to the pieces of the given address group. */ + + low = primary_base + NFC_3_2_ADD0_REG_OFF; + low += group; + + high = primary_base + NFC_3_2_ADD8_REG_OFF; + high += group; + + /* Check if there's a column address. */ + + if (column) { + + /* + * The low 32 bits of the address group look like this: + * + * 16 - n n + * | <- bits ->|<->|<- 16 bits ->| + * +-------------+---+----------------+ + * | Page LSBs |CS | Column | + * +-------------+---+----------------+ + */ + + x = __raw_readl(low); + + *column = x & 0xffff; + *chip = (x >> 16) & cs_mask; + page_lsbs = x >> (16 + cs_width); + + /* The high 16 bits contain the MSB's of the page address. */ + + page_msbs = __raw_readw(high); + + *page = (page_msbs << (16 - cs_width)) | page_lsbs; + + } else { + + /* + * The low 32 bits of the address group look like this: + * + * n + * | <- (32 - n) bits ->|<->| + * +-----------------------------+---+ + * | Page LSBs |CS | + * +-----------------------------+---+ + */ + + x = __raw_readl(low); + + *chip = x & cs_mask; + page_lsbs = x >> cs_width; + + /* The high 16 bits contain the MSB's of the page address. */ + + page_msbs = __raw_readw(high); + + *page = (page_msbs << (32 - cs_width)) | page_lsbs; + + } + +} + +/** + * nfc_3_2_set_auto_addresses() - Sets automatic operation addresses. + * + * @this: Per-device data. + * @group: The address group number. + * @chip: The chip number. + * @column: The column address. The sentinel value ~0 indicates that there is + * no column address. + * @page: The page address. + */ +static void nfc_3_2_set_auto_addresses(struct imx_nfc_data *this, + unsigned group, unsigned chip, unsigned column, unsigned page) +{ + uint32_t x; + unsigned chip_count; + unsigned int cs_width; + unsigned int cs_mask; + uint32_t *low; + uint16_t *high; + void *primary_base = this->primary_regs; + void *secondary_base = this->secondary_regs; + + /* + * The width of the chip select field depends on the number of connected + * chips. + * + * Notice that these computations work only if the number of chips is a + * power of 2. In fact, that is a fundamental limitation for using + * automatic operations. + */ + + x = __raw_readl(secondary_base + NFC_3_2_CONFIG3_REG_OFF); + + chip_count = + (x & NFC_3_2_CONFIG3_NUM_OF_DEVICES_MSK) >> + NFC_3_2_CONFIG3_NUM_OF_DEVICES_POS; + chip_count++; + + cs_width = ffs(chip_count) - 1; + cs_mask = chip_count - 1; + + /* Construct pointers to the pieces of the given address group. */ + + low = primary_base + NFC_3_2_ADD0_REG_OFF; + low += group; + + high = primary_base + NFC_3_2_ADD8_REG_OFF; + high += group; + + /* Check if we have a column address. */ + + if (column != ~0) { + + /* + * The low 32 bits of the address group look like this: + * + * 16 - n n + * | <- bits ->|<->|<- 16 bits ->| + * +-------------+---+----------------+ + * | Page LSBs |CS | Column | + * +-------------+---+----------------+ + */ + + x = 0; + x |= column & 0xffff; + x |= (chip & cs_mask) << 16; + x |= page << (16 + cs_width); + + __raw_writel(x, low); + + /* The high 16 bits contain the MSB's of the page address. */ + + x = (page >> (16 - cs_width)) & 0xffff; + + __raw_writew(x, high); + + } else { + + /* + * The low 32 bits of the address group look like this: + * + * n + * | <- (32 - n) bits ->|<->| + * +-----------------------------+---+ + * | Page LSBs |CS | + * +-----------------------------+---+ + */ + + x = 0; + x |= chip & cs_mask; + x |= page << cs_width; + + __raw_writel(x, low); + + /* The high 16 bits contain the MSB's of the page address. */ + + x = (page >> (32 - cs_width)) & 0xffff; + + __raw_writew(x, high); + + } + +} + +/** + * nfc_3_2_start_auto_read() - Starts an automatic read. + * + * This function returns 0 if everything went well. + * + * @this: Per-device data. + * @start: The first physical chip number on which to operate. + * @count: The number of physical chips on which to operate. + * @column: The column address. + * @page: The page address. + */ +static int nfc_3_2_start_auto_read(struct imx_nfc_data *this, + unsigned start, unsigned count, unsigned column, unsigned page) +{ + uint32_t x; + int return_value = 0; + void *primary_base = this->primary_regs; + + add_event("Entering nfc_3_2_start_auto_read", 1); + + /* Check for nonsense. */ + + if ((start > 7) || (!count) || (count > 8)) { + return_value = !0; + goto exit; + } + + /* Set state. */ + + nfc_3_2_set_auto_loop_params(this, start, start + count - 1, start); + nfc_3_2_set_auto_addresses(this, 0, start, column, page); + + /* Set up for ONE iteration at a time. */ + + raw_clr_mask_l(NFC_3_2_CONFIG1_ITER_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* Reset to buffer 0. */ + + raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* + * Set up the commands. Note that the number of command phases was + * configured in the set_geometry() function so, even though we're + * giving both commands here, they won't necessarily both be used. + */ + + x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF); + + x &= 0xffff0000; + x |= NAND_CMD_READ0 << 0; + x |= NAND_CMD_READSTART << 8; + + __raw_writel(x, primary_base + NFC_3_2_CMD_REG_OFF); + + /* Launch the operation. */ + + add_event("Launching", 0); + + __raw_writel(NFC_3_2_LAUNCH_AUTO_READ_MSK, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + +exit: /* Return. */ + + add_event("Exiting nfc_3_2_start_auto_read", -1); + + return return_value; + +} + +/** + * nfc_3_2_wait_for_auto_read() - Waits until auto read is ready for the CPU. + * + * This function returns 0 if everything went well. + * + * @this: Per-device data. + */ +static int nfc_3_2_wait_for_auto_read(struct imx_nfc_data *this) +{ + unsigned int first; + unsigned int last; + unsigned int index; + int return_value = 0; + + add_event("Entering nfc_3_2_wait_for_auto_read", 1); + + /* Get state. */ + + nfc_3_2_get_auto_loop_params(this, &first, &last, &index); + + /* This function should be called for every chip. */ + + if ((index < first) || (index > last)) { + return_value = !0; + goto exit; + } + + /* Wait for the NFC to completely finish and interrupt. */ + + nfc_util_wait_for_the_nfc(this, true); + +exit: /* Return. */ + + add_event("Exiting nfc_3_2_wait_for_auto_read", -1); + + return return_value; + +} + +/** + * nfc_3_2_resume_auto_read() - Resumes auto read after CPU intervention. + * + * This function returns 0 if everything went well. + * + * @this: Per-device data. + */ +static int nfc_3_2_resume_auto_read(struct imx_nfc_data *this) +{ + unsigned int first; + unsigned int last; + unsigned int index; + unsigned int chip; + unsigned int column; + unsigned int page; + int return_value = 0; + void *primary_base = this->primary_regs; + + add_event("Entering nfc_3_2_resume_auto_read", 1); + + /* Get state. */ + + nfc_3_2_get_auto_loop_params(this, &first, &last, &index); + nfc_3_2_get_auto_addresses(this, 0, &chip, &column, &page); + + /* This function should be called for every chip, except the last. */ + + if ((index < first) || (index >= last)) { + return_value = !0; + goto exit; + } + + /* Move to the next chip. */ + + index++; + + /* Update state. */ + + nfc_3_2_set_auto_loop_params(this, first, last, index); + nfc_3_2_set_auto_addresses(this, 0, index, column, page); + + /* Reset to buffer 0. */ + + raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* Launch the operation. */ + + add_event("Launching", 0); + + __raw_writel(NFC_3_2_LAUNCH_AUTO_READ_MSK, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + +exit: /* Return. */ + + add_event("Exiting nfc_3_2_resume_auto_read", -1); + + return return_value; + +} + +/** + * nfc_3_2_start_auto_write() - Starts an automatic write. + * + * This function returns 0 if everything went well. + * + * @this: Per-device data. + * @start: The first physical chip number on which to operate. + * @count: The number of physical chips on which to operate. + * @column: The column address. + * @page: The page address. + */ +static int nfc_3_2_start_auto_write(struct imx_nfc_data *this, + unsigned start, unsigned count, unsigned column, unsigned page) +{ + uint32_t x; + int return_value = 0; + void *primary_base = this->primary_regs; + void *secondary_base = this->secondary_regs; + + add_event("Entering nfc_3_2_start_auto_write", 1); + + /* Check for nonsense. */ + + if ((start > 7) || (!count) || (count > 8)) { + return_value = !0; + goto exit; + } + + /* Set state. */ + + nfc_3_2_set_auto_loop_params(this, start, start + count - 1, start); + nfc_3_2_set_auto_addresses(this, 0, start, column, page); + + /* Set up for ONE iteration at a time. */ + + raw_clr_mask_l(NFC_3_2_CONFIG1_ITER_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* Set up the commands. */ + + x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF); + + x &= 0xffff0000; + x |= NAND_CMD_SEQIN << 0; + x |= NAND_CMD_PAGEPROG << 8; + + __raw_writel(x, primary_base + NFC_3_2_CMD_REG_OFF); + + /* Clear the auto_prog_done bit. */ + + raw_clr_mask_l(NFC_3_2_IPC_AUTO_PROG_DONE_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); + +exit: /* Return. */ + + add_event("Exiting nfc_3_2_start_auto_write", -1); + + return return_value; + +} + +/** + * nfc_3_2_wait_for_auto_write() - Waits for auto write to be writey for the CPU. + * + * This function returns 0 if everything went well. + * + * @this: Per-device data. + */ +static int nfc_3_2_wait_for_auto_write(struct imx_nfc_data *this) +{ + unsigned int first; + unsigned int last; + unsigned int index; + unsigned int chip; + unsigned int column; + unsigned int page; + uint32_t x; + int interrupt; + int transmitted; + int ready; + int return_value = 0; + void *primary_base = this->primary_regs; + void *secondary_base = this->secondary_regs; + + add_event("Entering nfc_3_2_wait_for_auto_write", 1); + + /* Get state. */ + + nfc_3_2_get_auto_loop_params(this, &first, &last, &index); + nfc_3_2_get_auto_addresses(this, 0, &chip, &column, &page); + + /* This function should be called for every chip. */ + + if ((index < first) || (index > last)) { + return_value = !0; + goto exit; + } + + /* Reset to buffer 0. */ + + raw_clr_mask_l(NFC_3_2_CONFIG1_RBA_MSK, + primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* Launch the operation. */ + + nfc_3_2_add_state_events(this); + + add_event("Launching", 0); + + __raw_writel(NFC_3_2_LAUNCH_AUTO_PROG_MSK, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + + nfc_3_2_add_state_events(this); + + /* Wait for the NFC to transmit the page. */ + + add_event("Spinning while the NFC transmits the page...", 0); + + do + transmitted = !!raw_read_mask_l(NFC_3_2_IPC_AUTO_PROG_DONE_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); + while (!transmitted); + + /* + * When control arrives here, the auto_prog_done bit is set. This + * indicates the NFC has finished transmitting the current page. The CPU + * is now free to write the next page into the NFC's memory. The Flash + * hardware is still busy programming the page into its storage array. + * + * Clear the auto_prog_done bit. This is analogous to acknowledging an + * interrupt. + */ + + nfc_3_2_add_state_events(this); + + add_event("Acknowledging the page...", 0); + + raw_clr_mask_l(NFC_3_2_IPC_AUTO_PROG_DONE_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); + + nfc_3_2_add_state_events(this); + + /* + * If this is *not* the last iteration, move to the next chip and return + * to the caller so he can put the next page in the NFC buffer. + */ + + if (index < last) { + + add_event("Moving to the next chip...", 0); + + index++; + + nfc_3_2_set_auto_loop_params(this, first, last, index); + nfc_3_2_set_auto_addresses(this, 0, index, column, page); + + goto exit; + + } + + /* + * If control arrives here, this is the last iteration, so it's time to + * close out the entire operation. We need to wait for the medium to be + * ready and then acknowledge the final interrupt. + * + * Because of the way the NFC hardware works, the code here requires a + * bit of explanation. The most important rule is: + * + * During automatic operations, the NFC sets its + * interrupt bit *whenever* it sees the ready/busy + * signal transition from "Busy" to "Ready". + * + * Recall that the ready/busy signals from all the chips in the medium + * are "wire-anded." Thus, the NFC will only see that the medium is + * ready if *all* chips are ready. + * + * Because of variability in NAND Flash timing, the medium *may* have + * become ready during previous iterations, which means the interrupt + * bit *may* be set at this moment. This is a "left-over" interrupt, and + * can complicate our logic. + * + * The two bits of state that interest us here are the interrupt bit + * and the ready/busy bit. It boils down to the following truth table: + * + * | Interrupt | Ready/Busy | Description + * +------------+------------+--------------- + * | | | Busy medium and no left-over interrupt. + * | 0 | 0 | The final interrupt will arrive in the + * | | | future. + * +------------+------------+--------------- + * | | | Ready medium and no left-over interrupt. + * | 0 | 1 | There will be no final interrupt. This + * | | | case should be impossible. + * +------------+------------+--------------- + * | | | Busy medium and left-over interrupt. + * | 1 | 0 | The final interrupt will arrive in the + * | | | future. This is the hard case. + * +------------+------------+--------------- + * | | | Ready medium and left-over interrupt. + * | 1 | 1 | The final interrupt has already + * | | | arrived. Acknowledge it and exit. + * +------------+------------+--------------- + * + * Case #3 is a small problem. If we clear the interrupt, we may or may + * not have another interrupt following. + */ + + /* Sample the IPC register. */ + + x = __raw_readl(secondary_base + NFC_3_2_IPC_REG_OFF); + + interrupt = !!(x & NFC_3_2_IPC_INT_MSK); + ready = !!(x & NFC_3_2_IPC_RB_B_MSK); + + /* Check for the easy cases. */ + + if (!interrupt && !ready) { + add_event("Waiting for the final interrupt..." , 0); + nfc_util_wait_for_the_nfc(this, true); + goto exit; + } else if (!interrupt && ready) { + add_event("Done." , 0); + goto exit; + } else if (interrupt && ready) { + add_event("Acknowledging the final interrupt..." , 0); + nfc_util_wait_for_the_nfc(this, false); + goto exit; + + } + + /* + * If control arrives here, we hit case #3. Begin by acknowledging the + * interrupt we have right now. + */ + + add_event("Clearing the left-over interrupt..." , 0); + nfc_util_wait_for_the_nfc(this, false); + + /* + * Check the ready/busy bit again. If the medium is still busy, then + * we're going to get one more interrupt. + */ + + ready = !!raw_read_mask_l(NFC_3_2_IPC_RB_B_MSK, + secondary_base + NFC_3_2_IPC_REG_OFF); + + if (!ready) { + add_event("Waiting for the final interrupt..." , 0); + nfc_util_wait_for_the_nfc(this, true); + } + +exit: /* Return. */ + + add_event("Exiting nfc_3_2_wait_for_auto_write", -1); + + return return_value; + +} + +/** + * nfc_3_2_start_auto_erase() - Starts an automatic erase. + * + * This function returns 0 if everything went well. + * + * @this: Per-device data. + * @start: The first physical chip number on which to operate. + * @count: The number of physical chips on which to operate. + * @page: The page address. + */ +static int nfc_3_2_start_auto_erase(struct imx_nfc_data *this, + unsigned start, unsigned count, unsigned page) +{ + uint32_t x; + unsigned i; + int return_value = 0; + void *primary_base = this->primary_regs; + + add_event("Entering nfc_3_2_start_auto_erase", 1); + + /* Check for nonsense. */ + + if ((start > 7) || (!count) || (count > 8)) { + return_value = !0; + goto exit; + } + + /* Set up the commands. */ + + x = __raw_readl(primary_base + NFC_3_2_CMD_REG_OFF); + + x &= 0xffff0000; + x |= NAND_CMD_ERASE1 << 0; + x |= NAND_CMD_ERASE2 << 8; + + __raw_writel(x, primary_base + NFC_3_2_CMD_REG_OFF); + + /* Set the iterations. */ + + x = __raw_readl(primary_base + NFC_3_2_CONFIG1_REG_OFF); + + x &= ~NFC_3_2_CONFIG1_ITER_MSK; + x |= ((count - 1) << NFC_3_2_CONFIG1_ITER_POS) & + NFC_3_2_CONFIG1_ITER_MSK; + + __raw_writel(x, primary_base + NFC_3_2_CONFIG1_REG_OFF); + + /* Loop over chips, setting up the address groups. */ + + for (i = 0; i < count; i++) + nfc_3_2_set_auto_addresses(this, i, start + i, ~0, page); + + /* Launch the operation. */ + + add_event("Launching", 0); + + __raw_writel(NFC_3_2_LAUNCH_AUTO_ERASE_MSK, + primary_base + NFC_3_2_LAUNCH_REG_OFF); + +exit: /* Return. */ + + add_event("Exiting nfc_3_2_start_auto_erase", -1); + + return return_value; + +} + +/* + * At this point, we've defined all the version-specific primitives. We're now + * ready to construct the NFC HAL structures for every version. + */ + +struct nfc_hal nfc_1_0_hal = { + .major_version = 1, + .minor_version = 0, + .max_chip_count = 1, + .max_buffer_count = 4, + .spare_buf_stride = 16, + .has_secondary_regs = 0, + .can_be_symmetric = 0, + }; + +struct nfc_hal nfc_2_0_hal = { + .major_version = 2, + .minor_version = 0, + .max_chip_count = 1, + .max_buffer_count = 4, + .spare_buf_stride = 16, + .has_secondary_regs = false, + .can_be_symmetric = true, + .init = nfc_2_0_init, + .set_geometry = nfc_2_0_set_geometry, + .exit = nfc_2_x_exit, + .mask_interrupt = nfc_2_0_mask_interrupt, + .unmask_interrupt = nfc_2_0_unmask_interrupt, + .clear_interrupt = nfc_2_x_clear_interrupt, + .is_interrupting = nfc_2_x_is_interrupting, + .is_ready = 0, /* Ready/Busy not exposed. */ + .set_ecc = nfc_2_0_set_ecc, + .get_ecc_status = nfc_2_0_get_ecc_status, + .get_symmetric = nfc_2_0_get_symmetric, + .set_symmetric = nfc_2_0_set_symmetric, + .select_chip = nfc_2_0_select_chip, + .command_cycle = nfc_2_x_command_cycle, + .write_cycle = nfc_2_x_write_cycle, + .read_cycle = nfc_2_0_read_cycle, + .read_page = nfc_2_0_read_page, + .send_page = nfc_2_0_send_page, + .start_auto_read = 0, /* Not supported. */ + .wait_for_auto_read = 0, /* Not supported. */ + .resume_auto_read = 0, /* Not supported. */ + .start_auto_write = 0, /* Not supported. */ + .wait_for_auto_write = 0, /* Not supported. */ + .start_auto_erase = 0, /* Not supported. */ + }; + +struct nfc_hal nfc_2_1_hal = { + .major_version = 2, + .minor_version = 1, + .max_chip_count = 4, + .max_buffer_count = 8, + .spare_buf_stride = 64, + .has_secondary_regs = 0, + .can_be_symmetric = !0, + }; + +struct nfc_hal nfc_3_1_hal = { + .major_version = 3, + .minor_version = 1, + .max_chip_count = 4, + .max_buffer_count = 8, + .spare_buf_stride = 64, + .has_secondary_regs = !0, + .can_be_symmetric = !0, + }; + +struct nfc_hal nfc_3_2_hal = { + .major_version = 3, + .minor_version = 2, + .max_chip_count = 8, + .max_buffer_count = 8, + .spare_buf_stride = 64, + .has_secondary_regs = true, + .can_be_symmetric = true, + .init = nfc_3_2_init, + .set_geometry = nfc_3_2_set_geometry, + .exit = nfc_3_2_exit, + .set_closest_cycle = nfc_3_2_set_closest_cycle, + .mask_interrupt = nfc_3_2_mask_interrupt, + .unmask_interrupt = nfc_3_2_unmask_interrupt, + .clear_interrupt = nfc_3_2_clear_interrupt, + .is_interrupting = nfc_3_2_is_interrupting, + .is_ready = nfc_3_2_is_ready, + .set_force_ce = nfc_3_2_set_force_ce, + .set_ecc = nfc_3_2_set_ecc, + .get_ecc_status = nfc_3_2_get_ecc_status, + .get_symmetric = nfc_3_2_get_symmetric, + .set_symmetric = nfc_3_2_set_symmetric, + .select_chip = nfc_3_2_select_chip, + .command_cycle = nfc_3_2_command_cycle, + .write_cycle = nfc_3_2_write_cycle, + .read_cycle = nfc_3_2_read_cycle, + .read_page = nfc_3_2_read_page, + .send_page = nfc_3_2_send_page, + .start_auto_read = nfc_3_2_start_auto_read, + .wait_for_auto_read = nfc_3_2_wait_for_auto_read, + .resume_auto_read = nfc_3_2_resume_auto_read, + .start_auto_write = nfc_3_2_start_auto_write, + .wait_for_auto_write = nfc_3_2_wait_for_auto_write, + .start_auto_erase = nfc_3_2_start_auto_erase, + }; + +/* + * This array has a pointer to every NFC HAL structure. The probing process will + * find the one that matches the version given by the platform. + */ + +struct nfc_hal *(nfc_hals[]) = { + &nfc_1_0_hal, + &nfc_2_0_hal, + &nfc_2_1_hal, + &nfc_3_1_hal, + &nfc_3_2_hal, +}; + +/** + * mal_init() - Initialize the Medium Abstraction Layer. + * + * @this: Per-device data. + */ +static void mal_init(struct imx_nfc_data *this) +{ + this->interrupt_override = DRIVER_CHOICE; + this->auto_op_override = DRIVER_CHOICE; + this->inject_ecc_error = 0; +} + +/** + * mal_set_physical_geometry() - Set up the physical medium geometry. + * + * This function retrieves the physical geometry information discovered by + * nand_scan(), corrects it, and records it in the per-device data structure. + * + * @this: Per-device data. + */ +static int mal_set_physical_geometry(struct imx_nfc_data *this) +{ + struct mtd_info *mtd = &this->mtd; + struct nand_chip *nand = &this->nand; + struct device *dev = this->dev; + uint8_t manufacturer_id; + uint8_t device_id; + unsigned int block_size_in_pages; + unsigned int chip_size_in_blocks; + unsigned int chip_size_in_pages; + uint64_t medium_size_in_bytes; + struct physical_geometry *physical = &this->physical_geometry; + + /* + * Begin by transcribing exactly what the MTD code discovered. If there + * are any mistakes, we'll fix them in a moment. + */ + + physical->chip_count = nand->numchips; + physical->chip_size = nand->chipsize; + physical->block_size = mtd->erasesize; + physical->page_data_size = mtd->writesize; + physical->page_oob_size = mtd->oobsize; + + /* Read some of the ID bytes from the first NAND Flash chip. */ + + nand->select_chip(mtd, 0); + + nfc_util_send_cmd_and_addrs(this, NAND_CMD_READID, 0x00, -1); + + manufacturer_id = nand->read_byte(mtd); + device_id = nand->read_byte(mtd); + + /* + * Most manufacturers sell 4K page devices with 218 out-of-band bytes + * per page to accomodate ECC-8. + * + * Samsung and Hynix claim their parts have better reliability, so they + * only need ECC-4 and they have only 128 out-of-band bytes. + * + * The MTD code pays no attention to the manufacturer ID (something that + * eventually will have to change), so it believes that all 4K pages + * have 218 out-of-band bytes. + * + * We correct that mistake here. + */ + + if (physical->page_data_size == 4096) { + if ((manufacturer_id == NAND_MFR_SAMSUNG) || + (manufacturer_id == NAND_MFR_HYNIX)) { + physical->page_oob_size = 128; + } + } + + /* Compute some interesting facts. */ + + block_size_in_pages = + physical->block_size / physical->page_data_size; + chip_size_in_pages = + physical->chip_size >> (fls(physical->page_data_size) - 1); + chip_size_in_blocks = + physical->chip_size >> (fls(physical->block_size) - 1); + medium_size_in_bytes = + physical->chip_size * physical->chip_count; + + /* Report. */ + + dev_dbg(dev, "-----------------\n"); + dev_dbg(dev, "Physical Geometry\n"); + dev_dbg(dev, "-----------------\n"); + dev_dbg(dev, "Chip Count : %d\n", physical->chip_count); + dev_dbg(dev, "Page Data Size in Bytes: %u (0x%x)\n", + physical->page_data_size, physical->page_data_size); + dev_dbg(dev, "Page OOB Size in Bytes : %u\n", + physical->page_oob_size); + dev_dbg(dev, "Block Size in Bytes : %u (0x%x)\n", + physical->block_size, physical->block_size); + dev_dbg(dev, "Block Size in Pages : %u (0x%x)\n", + block_size_in_pages, block_size_in_pages); + dev_dbg(dev, "Chip Size in Bytes : %llu (0x%llx)\n", + physical->chip_size, physical->chip_size); + dev_dbg(dev, "Chip Size in Pages : %u (0x%x)\n", + chip_size_in_pages, chip_size_in_pages); + dev_dbg(dev, "Chip Size in Blocks : %u (0x%x)\n", + chip_size_in_blocks, chip_size_in_blocks); + dev_dbg(dev, "Medium Size in Bytes : %llu (0x%llx)\n", + medium_size_in_bytes, medium_size_in_bytes); + + /* Return success. */ + + return 0; + +} + +/** + * mal_set_nfc_geometry() - Set up the NFC geometry. + * + * This function calls the NFC HAL to select an NFC geometry that is compatible + * with the medium's physical geometry. + * + * @this: Per-device data. + */ +static int mal_set_nfc_geometry(struct imx_nfc_data *this) +{ + struct device *dev = this->dev; + struct nfc_geometry *nfc; + + /* Set the NFC geometry. */ + + if (this->nfc->set_geometry(this)) + return !0; + + /* Get a pointer to the new NFC geometry information. */ + + nfc = this->nfc_geometry; + + /* Report. */ + + dev_dbg(dev, "------------\n"); + dev_dbg(dev, "NFC Geometry\n"); + dev_dbg(dev, "------------\n"); + dev_dbg(dev, "Page Data Size in Bytes: %u (0x%x)\n", + nfc->page_data_size, nfc->page_data_size); + dev_dbg(dev, "Page OOB Size in Bytes : %u\n", nfc->page_oob_size); + dev_dbg(dev, "ECC Algorithm : %s\n", nfc->ecc_algorithm); + dev_dbg(dev, "ECC Strength : %d\n", nfc->ecc_strength); + dev_dbg(dev, "Buffer Count : %u\n", nfc->buffer_count); + dev_dbg(dev, "Spare Buffer Size : %u\n", nfc->spare_buf_size); + dev_dbg(dev, "Spare Buffer Spillover : %u\n", nfc->spare_buf_spill); + dev_dbg(dev, "Auto Read Available : %s\n", + this->nfc->start_auto_read ? "Yes" : "No"); + dev_dbg(dev, "Auto Write Available : %s\n", + this->nfc->start_auto_write ? "Yes" : "No"); + dev_dbg(dev, "Auto Erase Available : %s\n", + this->nfc->start_auto_erase ? "Yes" : "No"); + + /* Return success. */ + + return 0; + +} + +/** + * mal_set_logical_geometry() - Set up the logical medium geometry. + * + * This function constructs the logical geometry that we will expose to MTD, + * based on the physical and NFC geometries, and whether or not interleaving is + * on. + * + * @this: Per-device data. + */ +static int mal_set_logical_geometry(struct imx_nfc_data *this) +{ + const uint32_t max_medium_size_in_bytes = ~0; + int we_are_interleaving; + uint64_t physical_medium_size_in_bytes; + unsigned int usable_blocks; + unsigned int block_size_in_pages; + unsigned int chip_size_in_blocks; + unsigned int chip_size_in_pages; + unsigned int usable_medium_size_in_pages; + unsigned int usable_medium_size_in_blocks; + struct physical_geometry *physical = &this->physical_geometry; + struct nfc_geometry *nfc = this->nfc_geometry; + struct logical_geometry *logical = &this->logical_geometry; + struct device *dev = this->dev; + + /* Figure out if we're interleaving. */ + + we_are_interleaving = this->pdata->interleave; + + switch (imx_nfc_module_interleave_override) { + + case NEVER: + we_are_interleaving = false; + break; + + case DRIVER_CHOICE: + break; + + case ALWAYS: + we_are_interleaving = true; + break; + + } + + /* Compute the physical size of the medium. */ + + physical_medium_size_in_bytes = + physical->chip_count * physical->chip_size; + + /* Compute the logical geometry. */ + + if (!we_are_interleaving) { + + /* + * At this writing, MTD uses unsigned 32-bit variables to + * represent the size of the medium. If the physical medium is + * larger than that, the logical medium must be smaller. Here, + * we compute the total number of physical blocks in the medium + * that we can actually use. + */ + + if (physical_medium_size_in_bytes <= max_medium_size_in_bytes) { + usable_blocks = + physical_medium_size_in_bytes >> + (ffs(physical->block_size) - 1); + } else { + usable_blocks = + max_medium_size_in_bytes / physical->block_size; + } + + /* Set up the logical geometry. + * + * Notice that the usable medium size is not necessarily the + * same as the chip size multiplied by the number of physical + * chips. We can't afford to touch the physical chip size + * because the NAND Flash MTD code *requires* it to be a power + * of 2. + */ + + logical->chip_count = physical->chip_count; + logical->chip_size = physical->chip_size; + logical->usable_size = usable_blocks * physical->block_size; + logical->block_size = physical->block_size; + logical->page_data_size = nfc->page_data_size; + + /* Use the MTD layout that best matches the NFC geometry. */ + + logical->mtd_layout = &nfc->mtd_layout; + logical->page_oob_size = nfc->mtd_layout.eccbytes + + nfc->mtd_layout.oobavail; + + } else { + + /* + * If control arrives here, we are interleaving. Specifically, + * we are "horizontally concatenating" the pages in all the + * physical chips. + * + * - A logical page will be the size of a physical page + * multiplied by the number of physical chips. + * + * - A logical block will have the same number of pages as a + * physical block but, since the logical page size is larger, + * the logical block size is larger. + * + * - The entire medium will appear to be a single chip. + * + * At this writing, MTD uses unsigned 32-bit variables to + * represent the size of the medium. If the physical medium is + * larger than that, the logical medium must be smaller. + * + * The NAND Flash MTD code represents the size of a single chip + * as an unsigned 32-bit value. It also *requires* that the size + * of a chip be a power of two. Thus, the largest possible chip + * size is 2GiB. + * + * When interleaving, the entire medium appears to be one chip. + * Thus, when interleaving, the largest possible medium size is + * 2GiB. + */ + + if (physical_medium_size_in_bytes <= max_medium_size_in_bytes) { + logical->chip_size = + 0x1 << (fls(physical_medium_size_in_bytes) - 1); + } else { + logical->chip_size = + 0x1 << (fls(max_medium_size_in_bytes) - 1); + } + + /* + * If control arrives here, we're interleaving. The logical + * geometry is very different from the physical geometry. + */ + + logical->chip_count = 1; + logical->usable_size = logical->chip_size; + logical->block_size = + physical->block_size * physical->chip_count; + logical->page_data_size = + nfc->page_data_size * physical->chip_count; + + /* + * Since the logical geometry doesn't match the physical + * geometry, we can't use the MTD layout that matches the + * NFC geometry. We synthesize one here. + * + * Our "logical" OOB will be the concatenation of the first 5 + * bytes of the "physical" OOB of every chip. This has some + * important properties: + * + * - This will make the block mark of every physical chip + * visible (even for small page chips, which put their block + * mark in the 5th OOB byte). + * + * - None of the NFC controllers put ECC in the first 5 OOB + * bytes, so this layout exposes no ECC. + */ + + logical->page_oob_size = 5 * physical->chip_count; + + synthetic_layout.eccbytes = 0; + synthetic_layout.oobavail = 5 * physical->chip_count; + synthetic_layout.oobfree[0].offset = 0; + synthetic_layout.oobfree[0].length = synthetic_layout.oobavail; + + /* Install the synthetic layout. */ + + logical->mtd_layout = &synthetic_layout; + + } + + /* Compute some interesting facts. */ + + block_size_in_pages = logical->block_size / logical->page_data_size; + chip_size_in_pages = logical->chip_size / logical->page_data_size; + chip_size_in_blocks = logical->chip_size / logical->block_size; + usable_medium_size_in_pages = + logical->usable_size / logical->page_data_size; + usable_medium_size_in_blocks = + logical->usable_size / logical->block_size; + + /* Report. */ + + dev_dbg(dev, "----------------\n"); + dev_dbg(dev, "Logical Geometry\n"); + dev_dbg(dev, "----------------\n"); + dev_dbg(dev, "Chip Count : %d\n", logical->chip_count); + dev_dbg(dev, "Page Data Size in Bytes: %u (0x%x)\n", + logical->page_data_size, logical->page_data_size); + dev_dbg(dev, "Page OOB Size in Bytes : %u\n", + logical->page_oob_size); + dev_dbg(dev, "Block Size in Bytes : %u (0x%x)\n", + logical->block_size, logical->block_size); + dev_dbg(dev, "Block Size in Pages : %u (0x%x)\n", + block_size_in_pages, block_size_in_pages); + dev_dbg(dev, "Chip Size in Bytes : %u (0x%x)\n", + logical->chip_size, logical->chip_size); + dev_dbg(dev, "Chip Size in Pages : %u (0x%x)\n", + chip_size_in_pages, chip_size_in_pages); + dev_dbg(dev, "Chip Size in Blocks : %u (0x%x)\n", + chip_size_in_blocks, chip_size_in_blocks); + dev_dbg(dev, "Physical Size in Bytes : %llu (0x%llx)\n", + physical_medium_size_in_bytes, physical_medium_size_in_bytes); + dev_dbg(dev, "Usable Size in Bytes : %u (0x%x)\n", + logical->usable_size, logical->usable_size); + dev_dbg(dev, "Usable Size in Pages : %u (0x%x)\n", + usable_medium_size_in_pages, usable_medium_size_in_pages); + dev_dbg(dev, "Usable Size in Blocks : %u (0x%x)\n", + usable_medium_size_in_blocks, usable_medium_size_in_blocks); + + /* Return success. */ + + return 0; + +} + +/** + * mal_set_mtd_geometry() - Set up the MTD geometry. + * + * This function adjusts the owning MTD data structures to match the logical + * geometry we've chosen. + * + * @this: Per-device data. + */ +static int mal_set_mtd_geometry(struct imx_nfc_data *this) +{ + struct logical_geometry *logical = &this->logical_geometry; + struct mtd_info *mtd = &this->mtd; + struct nand_chip *nand = &this->nand; + + /* Configure the struct mtd_info. */ + + mtd->size = logical->usable_size; + mtd->erasesize = logical->block_size; + mtd->writesize = logical->page_data_size; + mtd->ecclayout = logical->mtd_layout; + mtd->oobavail = mtd->ecclayout->oobavail; + mtd->oobsize = mtd->ecclayout->oobavail + mtd->ecclayout->eccbytes; + mtd->subpage_sft = 0; /* We don't support sub-page writing. */ + + /* Configure the struct nand_chip. */ + + nand->numchips = logical->chip_count; + nand->chipsize = logical->chip_size; + nand->page_shift = ffs(logical->page_data_size) - 1; + nand->pagemask = (nand->chipsize >> nand->page_shift) - 1; + nand->subpagesize = mtd->writesize >> mtd->subpage_sft; + nand->phys_erase_shift = ffs(logical->block_size) - 1; + nand->bbt_erase_shift = nand->phys_erase_shift; + nand->chip_shift = ffs(logical->chip_size) - 1; + nand->oob_poi = nand->buffers->databuf+logical->page_data_size; + nand->ecc.layout = logical->mtd_layout; + + /* Set up the pattern that describes block marks. */ + + if (is_small_page_chip(this)) + nand->badblock_pattern = &small_page_block_mark_descriptor; + else + nand->badblock_pattern = &large_page_block_mark_descriptor; + + /* Return success. */ + + return 0; +} + +/** + * mal_set_geometry() - Set up the medium geometry. + * + * @this: Per-device data. + */ +static int mal_set_geometry(struct imx_nfc_data *this) +{ + + /* Set up the various layers of geometry, in this specific order. */ + + if (mal_set_physical_geometry(this)) + return !0; + + if (mal_set_nfc_geometry(this)) + return !0; + + if (mal_set_logical_geometry(this)) + return !0; + + if (mal_set_mtd_geometry(this)) + return !0; + + /* Return success. */ + + return 0; + +} + +/** + * mal_reset() - Resets the given chip. + * + * This is the fully-generalized reset operation, including support for + * interleaving. All reset operations funnel through here. + * + * @this: Per-device data. + * @chip: The logical chip of interest. + */ +static void mal_reset(struct imx_nfc_data *this, unsigned chip) +{ + int we_are_interleaving; + unsigned int start; + unsigned int end; + unsigned int i; + struct physical_geometry *physical = &this->physical_geometry; + struct logical_geometry *logical = &this->logical_geometry; + + add_event("Entering mal_get_status", 1); + + /* Establish some important facts. */ + + we_are_interleaving = logical->chip_count != physical->chip_count; + + /* Choose the loop bounds. */ + + if (we_are_interleaving) { + start = 0; + end = physical->chip_count; + } else { + start = chip; + end = start + 1; + } + + /* Loop over physical chips. */ + + add_event("Looping over physical chips...", 0); + + for (i = start; i < end; i++) { + + /* Select the current chip. */ + + this->nfc->select_chip(this, i); + + /* Reset the current chip. */ + + add_event("Resetting...", 0); + + nfc_util_send_cmd(this, NAND_CMD_RESET); + nfc_util_wait_for_the_nfc(this, false); + + } + + add_event("Exiting mal_get_status", -1); + +} + +/** + * mal_get_status() - Abstracted status retrieval. + * + * For media with a single chip, or concatenated chips, the HIL explicitly + * addresses a single chip at a time and wants the status from that chip only. + * + * For interleaved media, we must combine the individual chip states. At this + * writing, the NAND MTD system knows about the following bits in status + * registers: + * + * +------------------------+-------+---------+ + * | | | Combine | + * | Macro | Value | With | + * +------------------------+-------+---------+ + * | NAND_STATUS_FAIL | 0x01 | OR | + * | NAND_STATUS_FAIL_N1 | 0x02 | OR | + * | NAND_STATUS_TRUE_READY | 0x20 | AND | + * | NAND_STATUS_READY | 0x40 | AND | + * | NAND_STATUS_WP | 0x80 | AND | + * +------------------------+-------+---------+ + * + * @this: Per-device data. + * @chip: The logical chip of interest. + */ +static uint8_t mal_get_status(struct imx_nfc_data *this, unsigned chip) +{ + int we_are_interleaving; + unsigned int start; + unsigned int end; + unsigned int i; + unsigned int x; + unsigned int or_mask; + unsigned int and_mask; + uint8_t status; + struct physical_geometry *physical = &this->physical_geometry; + struct logical_geometry *logical = &this->logical_geometry; + + add_event("Entering mal_get_status", 1); + + /* Establish some important facts. */ + + we_are_interleaving = logical->chip_count != physical->chip_count; + + /* Compute the masks we need. */ + + or_mask = NAND_STATUS_FAIL | NAND_STATUS_FAIL_N1; + and_mask = NAND_STATUS_TRUE_READY | NAND_STATUS_READY | NAND_STATUS_WP; + + /* Assume the chip is successful, ready and writeable. */ + + status = and_mask & ~or_mask; + + /* Choose the loop bounds. */ + + if (we_are_interleaving) { + start = 0; + end = physical->chip_count; + } else { + start = chip; + end = start + 1; + } + + /* Loop over physical chips. */ + + add_event("Looping over physical chips...", 0); + + for (i = start; i < end; i++) { + + /* Select the current chip. */ + + this->nfc->select_chip(this, i); + + /* Get the current chip's status. */ + + add_event("Sending the command...", 0); + + nfc_util_send_cmd(this, NAND_CMD_STATUS); + nfc_util_wait_for_the_nfc(this, false); + + add_event("Reading the status...", 0); + + x = this->nfc->read_cycle(this); + + /* Fold this chip's status into the combined status. */ + + status |= (x & or_mask); + status &= (x & and_mask) | or_mask; + + } + + add_event("Exiting mal_get_status", -1); + + return status; + +} + +/** + * mal_read_a_page() - Abstracted page read. + * + * This function returns the ECC status for the entire read operation. A + * positive return value indicates the number of errors that were corrected + * (symbol errors for Reed-Solomon hardware engines, bit errors for BCH hardware + * engines). A negative return value indicates that the ECC engine failed to + * correct all errors and the data is corrupted. A zero return value indicates + * there were no errors at all. + * + * @this: Per-device data. + * @use_ecc: Indicates if we're to use ECC. + * @chip: The logical chip of interest. + * @page: The logical page number to read. + * @data: A pointer to the destination data buffer. If this pointer is null, + * that indicates the caller doesn't want the data. + * @oob: A pointer to the destination OOB buffer. If this pointer is null, + * that indicates the caller doesn't want the OOB. + */ +static int mal_read_a_page(struct imx_nfc_data *this, int use_ecc, + unsigned chip, unsigned page, uint8_t *data, uint8_t *oob) +{ + int we_are_interleaving; + int use_automatic_op; + unsigned int start; + unsigned int end; + unsigned int current_chip; + unsigned int oob_bytes_to_copy; + unsigned int data_bytes_to_copy; + int status; + unsigned int worst_case_ecc_status; + int return_value = 0; + struct physical_geometry *physical = &this->physical_geometry; + struct nfc_geometry *nfc = this->nfc_geometry; + struct logical_geometry *logical = &this->logical_geometry; + + add_event("Entering mal_read_a_page", 1); + + /* Establish some important facts. */ + + we_are_interleaving = logical->chip_count != physical->chip_count; + use_automatic_op = !!this->nfc->start_auto_read; + + /* Apply the automatic operation override, if any. */ + + switch (this->auto_op_override) { + + case NEVER: + use_automatic_op = false; + break; + + case DRIVER_CHOICE: + break; + + case ALWAYS: + if (this->nfc->start_auto_read) + use_automatic_op = true; + break; + + } + + /* Set up ECC. */ + + this->nfc->set_ecc(this, use_ecc); + + /* Check if we're interleaving and set up the loop iterations. */ + + if (we_are_interleaving) { + + start = 0; + end = physical->chip_count; + + data_bytes_to_copy = + this->logical_geometry.page_data_size / + this->physical_geometry.chip_count; + oob_bytes_to_copy = + this->logical_geometry.page_oob_size / + this->physical_geometry.chip_count; + + } else { + + start = chip; + end = start + 1; + + data_bytes_to_copy = this->logical_geometry.page_data_size; + oob_bytes_to_copy = this->logical_geometry.page_oob_size; + + } + + /* If we're using the automatic operation, start it now. */ + + if (use_automatic_op) { + add_event("Starting the automatic operation...", 0); + this->nfc->start_auto_read(this, start, end - start, 0, page); + } + + /* Loop over physical chips. */ + + add_event("Looping over physical chips...", 0); + + for (current_chip = start; current_chip < end; current_chip++) { + + /* Check if we're using the automatic operation. */ + + if (use_automatic_op) { + + add_event("Waiting...", 0); + this->nfc->wait_for_auto_read(this); + + } else { + + /* Select the current chip. */ + + this->nfc->select_chip(this, current_chip); + + /* Set up the chip. */ + + add_event("Sending the command and addresses...", 0); + + nfc_util_send_cmd_and_addrs(this, + NAND_CMD_READ0, 0, page); + + if (is_large_page_chip(this)) { + add_event("Sending the final command...", 0); + nfc_util_send_cmd(this, NAND_CMD_READSTART); + } + + /* Wait till the page is ready. */ + + add_event("Waiting for the page to arrive...", 0); + + nfc_util_wait_for_the_nfc(this, true); + + /* Read the page. */ + + add_event("Reading the page...", 0); + + this->nfc->read_page(this); + + } + + /* Copy a page out of the NFC. */ + + add_event("Copying from the NFC...", 0); + + if (oob) { + nfc_util_copy_from_the_nfc(this, + nfc->page_data_size, oob, oob_bytes_to_copy); + oob += oob_bytes_to_copy; + } + + if (data) { + nfc_util_copy_from_the_nfc(this, + 0, data, data_bytes_to_copy); + data += data_bytes_to_copy; + } + + /* + * If we're using ECC, and we haven't already seen an ECC + * failure, continue to gather ECC status. Note that, if we + * *do* see an ECC failure, we continue to read because the + * client might want the data for forensic purposes. + */ + + if (use_ecc && (return_value >= 0)) { + + add_event("Getting ECC status...", 0); + + status = this->nfc->get_ecc_status(this); + + if (status >= 0) + return_value += status; + else + return_value = -1; + + } + + /* Check if we're using the automatic operation. */ + + if (use_automatic_op) { + + /* + * If this is not the last iteration, resume the + * automatic operation. + */ + + if (current_chip < (end - 1)) { + add_event("Resuming...", 0); + this->nfc->resume_auto_read(this); + } + + } + + } + + /* Check if we're supposed to inject an ECC error. */ + + if (use_ecc && this->inject_ecc_error) { + + /* Inject the appropriate error. */ + + if (this->inject_ecc_error < 0) { + + add_event("Injecting an uncorrectable error...", 0); + + return_value = -1; + + } else { + + add_event("Injecting correctable errors...", 0); + + worst_case_ecc_status = + physical->chip_count * + nfc->buffer_count * + nfc->ecc_strength; + + if (this->inject_ecc_error > worst_case_ecc_status) + return_value = worst_case_ecc_status; + else + return_value = this->inject_ecc_error; + + } + + /* Stop injecting further errors. */ + + this->inject_ecc_error = 0; + + } + + /* Return. */ + + add_event("Exiting mal_read_a_page", -1); + + return return_value; + +} + +/** + * mal_write_a_page() - Abstracted page write. + * + * This function returns zero if the operation succeeded, or -EIO if the + * operation failed. + * + * @this: Per-device data. + * @use_ecc: Indicates if we're to use ECC. + * @chip: The logical chip of interest. + * @page: The logical page number to write. + * @data: A pointer to the source data buffer. + * @oob: A pointer to the source OOB buffer. + */ +static int mal_write_a_page(struct imx_nfc_data *this, int use_ecc, + unsigned chip, unsigned page, const uint8_t *data, const uint8_t *oob) +{ + int we_are_interleaving; + int use_automatic_op; + unsigned int start; + unsigned int end; + unsigned int current_chip; + unsigned int oob_bytes_to_copy; + unsigned int data_bytes_to_copy; + int return_value = 0; + struct physical_geometry *physical = &this->physical_geometry; + struct nfc_geometry *nfc = this->nfc_geometry; + struct logical_geometry *logical = &this->logical_geometry; + + add_event("Entering mal_write_a_page", 1); + + /* Establish some important facts. */ + + we_are_interleaving = logical->chip_count != physical->chip_count; + use_automatic_op = !!this->nfc->start_auto_write; + + /* Apply the automatic operation override, if any. */ + + switch (this->auto_op_override) { + + case NEVER: + use_automatic_op = false; + break; + + case DRIVER_CHOICE: + break; + + case ALWAYS: + if (this->nfc->start_auto_write) + use_automatic_op = true; + break; + + } + + /* Set up ECC. */ + + this->nfc->set_ecc(this, use_ecc); + + /* Check if we're interleaving and set up the loop iterations. */ + + if (we_are_interleaving) { + + start = 0; + end = physical->chip_count; + + data_bytes_to_copy = + this->logical_geometry.page_data_size / + this->physical_geometry.chip_count; + oob_bytes_to_copy = + this->logical_geometry.page_oob_size / + this->physical_geometry.chip_count; + + } else { + + start = chip; + end = start + 1; + + data_bytes_to_copy = this->logical_geometry.page_data_size; + oob_bytes_to_copy = this->logical_geometry.page_oob_size; + + } + + /* If we're using the automatic operation, start the hardware now. */ + + if (use_automatic_op) { + add_event("Starting the automatic operation...", 0); + this->nfc->start_auto_write(this, start, end - start, 0, page); + } + + /* Loop over physical chips. */ + + add_event("Looping over physical chips...", 0); + + for (current_chip = start; current_chip < end; current_chip++) { + + /* Copy a page into the NFC. */ + + add_event("Copying to the NFC...", 0); + + nfc_util_copy_to_the_nfc(this, oob, nfc->page_data_size, + oob_bytes_to_copy); + oob += oob_bytes_to_copy; + + nfc_util_copy_to_the_nfc(this, data, 0, data_bytes_to_copy); + + data += data_bytes_to_copy; + + /* Check if we're using the automatic operation. */ + + if (use_automatic_op) { + + /* Wait for the write operation to finish. */ + + add_event("Waiting...", 0); + + this->nfc->wait_for_auto_write(this); + + } else { + + /* Select the current chip. */ + + this->nfc->select_chip(this, current_chip); + + /* Set up the chip. */ + + add_event("Sending the command and addresses...", 0); + + nfc_util_send_cmd_and_addrs(this, + NAND_CMD_SEQIN, 0, page); + + /* Send the page. */ + + add_event("Sending the page...", 0); + + this->nfc->send_page(this); + + /* Start programming the page. */ + + add_event("Programming the page...", 0); + + nfc_util_send_cmd(this, NAND_CMD_PAGEPROG); + + /* Wait until the page is finished. */ + + add_event("Waiting...", 0); + + nfc_util_wait_for_the_nfc(this, true); + + } + + } + + /* Get status. */ + + add_event("Gathering status...", 0); + + if (mal_get_status(this, chip) & NAND_STATUS_FAIL) { + add_event("Bad status", 0); + return_value = -EIO; + } else { + add_event("Good status", 0); + } + + /* Return. */ + + add_event("Exiting mal_write_a_page", -1); + + return return_value; + +} + +/** + * mal_erase_a_block() - Abstract block erase operation. + * + * Note that this function does *not* wait for the operation to finish. The + * caller is expected to call waitfunc() at some later time. + * + * @this: Per-device data. + * @chip: The logical chip of interest. + * @page: A logical page address that identifies the block to erase. + */ +static void mal_erase_a_block(struct imx_nfc_data *this, + unsigned chip, unsigned page) +{ + int we_are_interleaving; + int use_automatic_op; + unsigned int start; + unsigned int end; + unsigned int i; + struct physical_geometry *physical = &this->physical_geometry; + struct logical_geometry *logical = &this->logical_geometry; + + add_event("Entering mal_erase_a_block", 1); + + /* Establish some important facts. */ + + we_are_interleaving = logical->chip_count != physical->chip_count; + use_automatic_op = !!this->nfc->start_auto_erase; + + /* Apply the automatic operation override, if any. */ + + switch (this->auto_op_override) { + + case NEVER: + use_automatic_op = false; + break; + + case DRIVER_CHOICE: + break; + + case ALWAYS: + if (this->nfc->start_auto_erase) + use_automatic_op = true; + break; + + } + + /* Choose the loop bounds. */ + + if (we_are_interleaving) { + start = 0; + end = physical->chip_count; + } else { + start = chip; + end = start + 1; + } + + /* Check if we're using the automatic operation. */ + + if (use_automatic_op) { + + /* + * Start the operation. Note that we don't wait for it to + * finish because the HIL will call our waitfunc(). + */ + + add_event("Starting the automatic operation...", 0); + + this->nfc->start_auto_erase(this, start, end - start, page); + + } else { + + /* Loop over physical chips. */ + + add_event("Looping over physical chips...", 0); + + for (i = start; i < end; i++) { + + /* Select the current chip. */ + + this->nfc->select_chip(this, i); + + /* Set up the chip. */ + + nfc_util_send_cmd_and_addrs(this, + NAND_CMD_ERASE1, -1, page); + + /* Start the erase. */ + + nfc_util_send_cmd(this, NAND_CMD_ERASE2); + + /* + * If this is the last time through the loop, break out + * now so we don't try to wait (the HIL will call our + * waitfunc() for the final wait). + */ + + if (i >= (end - 1)) + break; + + /* Wait for the erase on the current chip to finish. */ + + nfc_util_wait_for_the_nfc(this, true); + + } + + } + + add_event("Exiting mal_erase_a_block", -1); + +} + +/** + * mal_is_block_bad() - Abstract bad block check. + * + * @this: Per-device data. + * @chip: The logical chip of interest. + * @page: The logical page number to read. + */ + #if 0 + +/* TODO: Finish this function and plug it in. */ + +static int mal_is_block_bad(struct imx_nfc_data *this, + unsigned chip, unsigned page) +{ + int we_are_interleaving; + unsigned int start; + unsigned int end; + unsigned int i; + uint8_t *p; + int return_value = 0; + struct nand_chip *nand = &this->nand; + struct physical_geometry *physical = &this->physical_geometry; + struct logical_geometry *logical = &this->logical_geometry; + + /* Figure out if we're interleaving. */ + + we_are_interleaving = logical->chip_count != physical->chip_count; + + /* + * We're about to use the NAND Flash MTD layer's buffer, so invalidate + * the page cache. + */ + + this->nand.pagebuf = -1; + + /* + * Read the OOB of the given page, using the NAND Flash MTD's buffer. + * + * Notice that ECC is off, which it *must* be when scanning block marks. + */ + + mal_read_a_page(this, false, + this->current_chip, this->page_address, 0, nand->oob_poi); + + /* Choose the loop bounds. */ + + if (we_are_interleaving) { + start = 0; + end = physical->chip_count; + } else { + start = chip; + end = start + 1; + } + + /* Start scanning at the beginning of the OOB data. */ + + p = nand->oob_poi; + + /* Loop over physical chips. */ + + add_event("Looping over physical chips...", 0); + + for (i = start; i < end; i++, p += 5) { + + /* Examine the OOB for this chip. */ + + if (p[nand->badblockpos] != 0xff) { + return_value = !0; + break; + } + + } + + /* Return. */ + + return return_value; + +} +#endif + +/** + * mil_init() - Initializes the MTD Interface Layer. + * + * @this: Per-device data. + */ +static void mil_init(struct imx_nfc_data *this) +{ + this->current_chip = -1; /* No chip is selected yet. */ + this->command_is_new = false; /* No command yet. */ +} + +/** + * mil_cmd_ctrl() - MTD Interface cmd_ctrl() + * + * @mtd: A pointer to the owning MTD. + * @dat: The data signals to present to the chip. + * @ctrl: The control signals to present to the chip. + */ +static void mil_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); +} + +/** + * mil_dev_ready() - MTD Interface dev_ready() + * + * @mtd: A pointer to the owning MTD. + */ +static int mil_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc dev_ready]\n"); + + add_event("Entering mil_dev_ready", 1); + + if (this->nfc->is_ready(this)) { + add_event("Exiting mil_dev_ready - Returning ready", -1); + return !0; + } else { + add_event("Exiting mil_dev_ready - Returning busy", -1); + return 0; + } + +} + +/** + * mil_select_chip() - MTD Interface select_chip() + * + * @mtd: A pointer to the owning MTD. + * @chip: The chip number to select, or -1 to select no chip. + */ +static void mil_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc select_chip] chip: %d\n", chip); + + /* Figure out what kind of transition this is. */ + + if ((this->current_chip < 0) && (chip >= 0)) { + start_event_trace("Entering mil_select_chip"); + if (this->pdata->force_ce) + this->nfc->set_force_ce(this, true); + clk_enable(this->clock); + add_event("Exiting mil_select_chip", -1); + } else if ((this->current_chip >= 0) && (chip < 0)) { + add_event("Entering mil_select_chip", 1); + if (this->pdata->force_ce) + this->nfc->set_force_ce(this, false); + clk_disable(this->clock); + stop_event_trace("Exiting mil_select_chip"); + } else { + add_event("Entering mil_select_chip", 1); + add_event("Exiting mil_select_chip", -1); + } + + this->current_chip = chip; + +} + +/** + * mil_cmdfunc() - MTD Interface cmdfunc() + * + * This function handles NAND Flash command codes from the HIL. Since only the + * HIL calls this function (none of the reference implementations we use do), it + * needs to handle very few command codes. + * + * @mtd: A pointer to the owning MTD. + * @command: The command code. + * @column: The column address associated with this command code, or -1 if no + * column address applies. + * @page: The page address associated with this command code, or -1 if no + * page address applies. + */ +static void mil_cmdfunc(struct mtd_info *mtd, + unsigned command, int column, int page) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc cmdfunc] command: 0x%02x, " + "column: 0x%04x, page: 0x%06x\n", command, column, page); + + add_event("Entering mil_cmdfunc", 1); + + /* Record the command and the fact that it hasn't yet been sent. */ + + this->command = command; + this->command_is_new = true; + + /* + * Process the command code. + * + * Note the default case to trap unrecognized codes. Thus, every command + * we support must have a case here, even if we don't have to do any + * pre-processing work. If the HIL changes and starts sending commands + * we haven't explicitly implemented, this will warn us. + */ + + switch (command) { + + case NAND_CMD_READ0: + add_event("NAND_CMD_READ0", 0); + /* + * After calling this function to send the command and + * addresses, the HIL will call ecc.read_page() or + * ecc.read_page_raw() to collect the data. + * + * The column address from the HIL is always zero. The only + * information we need to keep from this call is the page + * address. + */ + this->page_address = page; + break; + + case NAND_CMD_STATUS: + add_event("NAND_CMD_STATUS", 0); + /* + * After calling this function to send the command, the HIL + * will call read_byte() once to collect the status. + */ + break; + + case NAND_CMD_READID: + add_event("NAND_CMD_READID", 0); + /* + * After calling this function to send the command, the HIL + * will call read_byte() repeatedly to collect ID bytes. + */ + break; + + case NAND_CMD_RESET: + add_event("NAND_CMD_RESET", 0); + mal_reset(this, this->current_chip); + break; + + default: + dev_emerg(this->dev, "Unsupported NAND Flash command code: " + "0x%02x\n", command); + BUG(); + break; + + } + + add_event("Exiting mil_cmdfunc", -1); + +} + +/** + * mil_waitfunc() - MTD Interface waifunc() + * + * This function blocks until the current chip is ready and then returns the + * contents of the chip's status register. The HIL only calls this function + * after starting an erase operation. + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + */ +static int mil_waitfunc(struct mtd_info *mtd, struct nand_chip *nand) +{ + int status; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc waitfunc]\n"); + + add_event("Entering mil_waitfunc", 1); + + /* Wait for the NFC to finish. */ + + nfc_util_wait_for_the_nfc(this, true); + + /* Get the status. */ + + status = mal_get_status(this, this->current_chip); + + add_event("Exiting mil_waitfunc", -1); + + return status; + +} + +/** + * mil_read_byte() - MTD Interface read_byte(). + * + * @mtd: A pointer to the owning MTD. + */ +static uint8_t mil_read_byte(struct mtd_info *mtd) +{ + uint8_t byte = 0; + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + + add_event("Entering mil_read_byte", 1); + + /* + * The command sent by the HIL before it called this function determines + * how we get the byte we're going to return. + */ + + switch (this->command) { + + case NAND_CMD_STATUS: + add_event("NAND_CMD_STATUS", 0); + byte = mal_get_status(this, this->current_chip); + break; + + case NAND_CMD_READID: + add_event("NAND_CMD_READID", 0); + + /* + * Check if the command is new. If so, then the HIL just + * recently called cmdfunc(), so the current chip isn't selected + * and the command hasn't been sent to the chip. + */ + + if (this->command_is_new) { + add_event("Sending the \"Read ID\" command...", 0); + this->nfc->select_chip(this, this->current_chip); + nfc_util_send_cmd_and_addrs(this, + NAND_CMD_READID, 0, -1); + this->command_is_new = false; + } + + /* Read the ID byte. */ + + add_event("Reading the ID byte...", 0); + + byte = this->nfc->read_cycle(this); + + break; + + default: + dev_emerg(this->dev, "Unsupported NAND Flash command code: " + "0x%02x\n", this->command); + BUG(); + break; + + } + + DEBUG(MTD_DEBUG_LEVEL2, + "[imx_nfc read_byte] Returning: 0x%02x\n", byte); + + add_event("Exiting mil_read_byte", -1); + + return byte; + +} + +/** + * mil_read_word() - MTD Interface read_word(). + * + * @mtd: A pointer to the owning MTD. + */ +static uint16_t mil_read_word(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); + return 0; +} + +/** + * mil_read_buf() - MTD Interface read_buf(). + * + * @mtd: A pointer to the owning MTD. + * @buf: The destination buffer. + * @len: The number of bytes to read. + */ +static void mil_read_buf(struct mtd_info *mtd, uint8_t * buf, int len) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); +} + +/** + * mil_write_buf() - MTD Interface write_buf(). + * + * @mtd: A pointer to the owning MTD. + * @buf: The source buffer. + * @len: The number of bytes to read. + */ +static void mil_write_buf(struct mtd_info *mtd, const uint8_t * buf, int len) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); +} + +/** + * mil_verify_buf() - MTD Interface verify_buf(). + * + * @mtd: A pointer to the owning MTD. + * @buf: The destination buffer. + * @len: The number of bytes to read. + */ +static int mil_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); + return 0; +} + +/** + * mil_ecc_hwctl() - MTD Interface ecc.hwctl(). + * + * @mtd: A pointer to the owning MTD. + * @mode: The ECC mode. + */ +static void mil_ecc_hwctl(struct mtd_info *mtd, int mode) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); +} + +/** + * mil_ecc_calculate() - MTD Interface ecc.calculate(). + * + * @mtd: A pointer to the owning MTD. + * @dat: A pointer to the source data. + * @ecc_code: A pointer to a buffer that will receive the resulting ECC. + */ +static int mil_ecc_calculate(struct mtd_info *mtd, + const uint8_t *dat, uint8_t *ecc_code) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); + return 0; +} + +/** + * mil_ecc_correct() - MTD Interface ecc.correct(). + * + * @mtd: A pointer to the owning MTD. + * @dat: A pointer to the source data. + * @read_ecc: A pointer to the ECC that was read from the medium. + * @calc_ecc: A pointer to the ECC that was calculated for the source data. + */ +static int mil_ecc_correct(struct mtd_info *mtd, + uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); + return 0; +} + +/** + * mil_ecc_read_page() - MTD Interface ecc.read_page(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the destination buffer. + */ +static int mil_ecc_read_page(struct mtd_info *mtd, + struct nand_chip *nand, uint8_t *buf) +{ + int ecc_status; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc ecc_read_page]\n"); + + add_event("Entering mil_ecc_read_page", 1); + + /* Read the page. */ + + ecc_status = + mal_read_a_page(this, true, this->current_chip, + this->page_address, buf, nand->oob_poi); + + /* Propagate ECC information. */ + + if (ecc_status < 0) { + add_event("ECC Failure", 0); + mtd->ecc_stats.failed++; + } else if (ecc_status > 0) { + add_event("ECC Corrections", 0); + mtd->ecc_stats.corrected += ecc_status; + } + + add_event("Exiting mil_ecc_read_page", -1); + + return 0; + +} + +/** + * mil_ecc_read_page_raw() - MTD Interface ecc.read_page_raw(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the destination buffer. + */ +static int mil_ecc_read_page_raw(struct mtd_info *mtd, + struct nand_chip *nand, uint8_t *buf) +{ + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc ecc_read_page_raw]\n"); + + add_event("Entering mil_ecc_read_page_raw", 1); + + mal_read_a_page(this, false, this->current_chip, + this->page_address, buf, nand->oob_poi); + + add_event("Exiting mil_ecc_read_page_raw", -1); + + return 0; + +} + +/** + * mil_ecc_write_page() - MTD Interface ecc.write_page(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the source buffer. + */ +static void mil_ecc_write_page(struct mtd_info *mtd, + struct nand_chip *nand, const uint8_t *buf) +{ + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); +} + +/** + * mil_ecc_write_page_raw() - MTD Interface ecc.write_page_raw(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the source buffer. + */ +static void mil_ecc_write_page_raw(struct mtd_info *mtd, + struct nand_chip *nand, const uint8_t *buf) +{ + struct imx_nfc_data *this = nand->priv; + unimplemented(this, __func__); +} + +/** + * mil_write_page() - MTD Interface ecc.write_page(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @buf: A pointer to the source buffer. + * @page: The page number to write. + * @cached: Indicates cached programming (ignored). + * @raw: Indicates not to use ECC. + */ +static int mil_write_page(struct mtd_info *mtd, + struct nand_chip *nand, const uint8_t *buf, + int page, int cached, int raw) +{ + int return_value; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc write_page]\n"); + + add_event("Entering mil_write_page", 1); + + return_value = mal_write_a_page(this, !raw, + this->current_chip, page, buf, nand->oob_poi); + + add_event("Exiting mil_write_page", -1); + + return return_value; + +} + +/** + * mil_ecc_read_oob() - MTD Interface read_oob(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @page: The page number to read. + * @sndcmd: Indicates this function should send a command to the chip before + * reading the out-of-band bytes. This is only false for small page + * chips that support auto-increment. + */ +static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, + int page, int sndcmd) +{ + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc ecc_read_oob] " + "page: 0x%06x, sndcmd: %s\n", page, sndcmd ? "Yes" : "No"); + + add_event("Entering mil_ecc_read_oob", 1); + + mal_read_a_page(this, false, + this->current_chip, page, 0, nand->oob_poi); + + add_event("Exiting mil_ecc_read_oob", -1); + + /* + * Return true, indicating that the next call to this function must send + * a command. + */ + + return true; + +} + +/** + * mil_ecc_write_oob() - MTD Interface write_oob(). + * + * @mtd: A pointer to the owning MTD. + * @nand: A pointer to the owning NAND Flash MTD. + * @page: The page number to write. + */ +static int mil_ecc_write_oob(struct mtd_info *mtd, + struct nand_chip *nand, int page) +{ + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc ecc_write_oob] page: 0x%06x\n", page); + + /* + * There are fundamental incompatibilities between the i.MX NFC and the + * NAND Flash MTD model that make it essentially impossible to write the + * out-of-band bytes. + */ + + dev_emerg(this->dev, "This driver doesn't support writing the OOB\n"); + WARN_ON(1); + + /* Return status. */ + + return -EIO; + +} + +/** + * mil_erase_cmd() - MTD Interface erase_cmd(). + * + * We set the erase_cmd pointer in struct nand_chip to point to this function. + * Thus, the HIL will call here for all erase operations. + * + * Strictly speaking, since the erase_cmd pointer is marked "Internal," we + * shouldn't be doing this. However, the only reason the HIL uses that pointer + * is to install a different function for erasing conventional NAND Flash or AND + * Flash. Since AND Flash is obsolete and we don't support it, this isn't + * important. + * + * Furthermore, to cleanly implement interleaving (which is critical to speeding + * up erase operations), we want to "hook into" the operation at the highest + * semantic level possible. If we don't hook this function, then the only way + * we'll know that an erase is happening is when the HIL calls cmdfunc() with + * an erase command. Implementing interleaving at that level is roughly a + * billion times less desirable. + * + * This function does *not* wait for the operation to finish. The HIL will call + * waitfunc() later to wait for the operation to finish. + * + * @mtd: A pointer to the owning MTD. + * @page: A page address that identifies the block to erase. + */ +static void mil_erase_cmd(struct mtd_info *mtd, int page) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc erase_cmd] page: 0x%06x\n", page); + + add_event("Entering mil_erase_cmd", 1); + + mal_erase_a_block(this, this->current_chip, page); + + add_event("Exiting mil_erase_cmd", -1); + +} + +/** + * mil_block_bad() - MTD Interface block_bad(). + * + * @mtd: A pointer to the owning MTD. + * @ofs: The offset of the block of interest, from the start of the medium. + * @getchip: Indicates this function must acquire the MTD before using it. + */ +#if 0 + +/* TODO: Finish this function and plug it in. */ + +static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + unsigned int chip; + unsigned int page; + int return_value; + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc block_bad] page: 0x%06x\n", page); + + add_event("Entering mil_block_bad", 1); + + /* Compute the logical chip number that contains the given offset. */ + + chip = (unsigned int) (ofs >> nand->chip_shift); + + /* Compute the logical page address within the logical chip. */ + + page = ((unsigned int) (ofs >> nand->page_shift)) & nand->pagemask; + + /* Check if the block is bad. */ + + return_value = mal_is_block_bad(this, chip, page); + + if (return_value) + add_event("Bad block", 0); + + /* Return. */ + + add_event("Exiting mil_block_bad", -1); + + return return_value; + +} +#endif + +/** + * mil_scan_bbt() - MTD Interface scan_bbt(). + * + * The HIL calls this function once, when it initializes the NAND Flash MTD. + * + * Nominally, the purpose of this function is to look for or create the bad + * block table. In fact, since the HIL calls this function at the very end of + * the initialization process started by nand_scan(), and the HIL doesn't have a + * more formal mechanism, everyone "hooks" this function to continue the + * initialization process. + * + * At this point, the physical NAND Flash chips have been identified and + * counted, so we know the physical geometry. This enables us to make some + * important configuration decisions. + * + * The return value of this function propogates directly back to this driver's + * call to nand_scan(). Anything other than zero will cause this driver to + * tear everything down and declare failure. + * + * @mtd: A pointer to the owning MTD. + */ +static int mil_scan_bbt(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd->priv; + struct imx_nfc_data *this = nand->priv; + + DEBUG(MTD_DEBUG_LEVEL2, "[imx_nfc scan_bbt] \n"); + + add_event("Entering mil_scan_bbt", 1); + + /* + * We replace the erase_cmd() function that the MTD NAND Flash system + * has installed with our own. See mil_erase_cmd() for the reasons. + */ + + nand->erase_cmd = mil_erase_cmd; + + /* + * Tell MTD users that the out-of-band area can't be written. + * + * This flag is not part of the standard kernel source tree. It comes + * from a patch that touches both MTD and JFFS2. + * + * The problem is that, without this patch, JFFS2 believes it can write + * the data area and the out-of-band area separately. This is wrong for + * two reasons: + * + * 1) Our NFC distributes out-of-band bytes throughout the page, + * intermingled with the data, and covered by the same ECC. + * Thus, it's not possible to write the out-of-band bytes and + * data bytes separately. + * + * 2) Large page (MLC) Flash chips don't support partial page + * writes. You must write the entire page at a time. Thus, even + * if our NFC didn't force you to write out-of-band and data + * bytes together, it would *still* be a bad idea to do + * otherwise. + */ + + mtd->flags &= ~MTD_OOB_WRITEABLE; + + /* Set up geometry. */ + + mal_set_geometry(this); + + /* We use the reference implementation for bad block management. */ + + add_event("Exiting mil_scan_bbt", -1); + + return nand_scan_bbt(mtd, nand->badblock_pattern); + +} + +/** + * parse_bool_param() - Parses the value of a boolean parameter string. + * + * @s: The string to parse. + */ +static int parse_bool_param(const char *s) +{ + + if (!strcmp(s, "1") || !strcmp(s, "on") || + !strcmp(s, "yes") || !strcmp(s, "true")) { + return 1; + } else if (!strcmp(s, "0") || !strcmp(s, "off") || + !strcmp(s, "no") || !strcmp(s, "false")) { + return 0; + } else { + return -1; + } + +} + +/** + * set_module_enable() - Controls whether this driver is enabled. + * + * Note that this state can be controlled from the command line. Disabling this + * driver is sometimes useful for debugging. + * + * @s: The new value of the parameter. + * @kp: The owning kernel parameter. + */ +static int set_module_enable(const char *s, struct kernel_param *kp) +{ + + switch (parse_bool_param(s)) { + + case 1: + imx_nfc_module_enable = true; + break; + + case 0: + imx_nfc_module_enable = false; + break; + + default: + return -EINVAL; + break; + + } + + return 0; + +} + +/** + * get_module_enable() - Indicates whether this driver is enabled. + * + * @p: A pointer to a (small) buffer that will receive the response. + * @kp: The owning kernel parameter. + */ +static int get_module_enable(char *p, struct kernel_param *kp) +{ + p[0] = imx_nfc_module_enable ? '1' : '0'; + p[1] = 0; + return 1; +} + +#ifdef EVENT_REPORTING + +/** + * set_module_report_events() - Controls whether this driver reports events. + * + * @s: The new value of the parameter. + * @kp: The owning kernel parameter. + */ +static int set_module_report_events(const char *s, struct kernel_param *kp) +{ + + switch (parse_bool_param(s)) { + + case 1: + imx_nfc_module_report_events = true; + break; + + case 0: + imx_nfc_module_report_events = false; + reset_event_trace(); + break; + + default: + return -EINVAL; + break; + + } + + return 0; + +} + +/** + * get_module_report_events() - Indicates whether the driver reports events. + * + * @p: A pointer to a (small) buffer that will receive the response. + * @kp: The owning kernel parameter. + */ +static int get_module_report_events(char *p, struct kernel_param *kp) +{ + p[0] = imx_nfc_module_report_events ? '1' : '0'; + p[1] = 0; + return 1; +} + +/** + * set_module_dump_events() - Forces the driver to dump current events. + * + * @s: The new value of the parameter. + * @kp: The owning kernel parameter. + */ +static int set_module_dump_events(const char *s, struct kernel_param *kp) +{ + dump_event_trace(); + return 0; +} + +#endif /*EVENT_REPORTING*/ + +/** + * set_module_interleave_override() - Controls the interleave override. + * + * @s: The new value of the parameter. + * @kp: The owning kernel parameter. + */ +static int set_module_interleave_override(const char *s, + struct kernel_param *kp) +{ + + if (!strcmp(s, "-1")) + imx_nfc_module_interleave_override = NEVER; + else if (!strcmp(s, "0")) + imx_nfc_module_interleave_override = DRIVER_CHOICE; + else if (!strcmp(s, "1")) + imx_nfc_module_interleave_override = ALWAYS; + else + return -EINVAL; + + return 0; + +} + +/** + * get_module_interleave_override() - Indicates the interleave override state. + * + * @p: A pointer to a (small) buffer that will receive the response. + * @kp: The owning kernel parameter. + */ +static int get_module_interleave_override(char *p, struct kernel_param *kp) +{ + return sprintf(p, "%d", imx_nfc_module_interleave_override); +} + +/** + * set_force_bytewise_copy() - Controls forced bytewise copy from/to the NFC. + * + * @s: The new value of the parameter. + * @kp: The owning kernel parameter. + */ +static int set_module_force_bytewise_copy(const char *s, + struct kernel_param *kp) +{ + + switch (parse_bool_param(s)) { + + case 1: + imx_nfc_module_force_bytewise_copy = true; + break; + + case 0: + imx_nfc_module_force_bytewise_copy = false; + break; + + default: + return -EINVAL; + break; + + } + + return 0; + +} + +/** + * get_force_bytewise_copy() - Indicates whether bytewise copy is being forced. + * + * @p: A pointer to a (small) buffer that will receive the response. + * @kp: The owning kernel parameter. + */ +static int get_module_force_bytewise_copy(char *p, struct kernel_param *kp) +{ + p[0] = imx_nfc_module_force_bytewise_copy ? '1' : '0'; + p[1] = 0; + return 1; +} + +/* Module attributes that appear in sysfs. */ + +module_param_call(enable, set_module_enable, get_module_enable, 0, 0444); +MODULE_PARM_DESC(enable, "enables/disables probing"); + +#ifdef EVENT_REPORTING +module_param_call(report_events, + set_module_report_events, get_module_report_events, 0, 0644); +MODULE_PARM_DESC(report_events, "enables/disables event reporting"); + +module_param_call(dump_events, set_module_dump_events, 0, 0, 0644); +MODULE_PARM_DESC(dump_events, "forces current event dump"); +#endif + +module_param_call(interleave_override, set_module_interleave_override, + get_module_interleave_override, 0, 0444); +MODULE_PARM_DESC(interleave_override, "overrides interleaving choice"); + +module_param_call(force_bytewise_copy, set_module_force_bytewise_copy, + get_module_force_bytewise_copy, 0, 0644); +MODULE_PARM_DESC(force_bytewise_copy, "forces bytewise copy from/to NFC"); + +/** + * show_device_platform_info() - Shows the device's platform information. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_platform_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int o = 0; + unsigned int i; + void *buffer_base; + void *primary_base; + void *secondary_base; + unsigned int interrupt_number; + struct resource *r; + struct imx_nfc_data *this = dev_get_drvdata(dev); + struct platform_device *pdev = this->pdev; + struct imx_nfc_platform_data *pdata = this->pdata; + struct mtd_partition *partition; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, + IMX_NFC_BUFFERS_ADDR_RES_NAME); + + buffer_base = (void *) r->start; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, + IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME); + + primary_base = (void *) r->start; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, + IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME); + + secondary_base = (void *) r->start; + + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, + IMX_NFC_INTERRUPT_RES_NAME); + + interrupt_number = r->start; + + o += sprintf(buf, + "NFC Major Version : %u\n" + "NFC Minor Version : %u\n" + "Force CE : %s\n" + "Target Cycle in ns : %u\n" + "Clock Name : %s\n" + "Interleave : %s\n" + "Buffer Base : 0x%p\n" + "Primary Registers Base : 0x%p\n" + "Secondary Registers Base: 0x%p\n" + "Interrupt Number : %u\n" + , + pdata->nfc_major_version, + pdata->nfc_minor_version, + pdata->force_ce ? "Yes" : "No", + pdata->target_cycle_in_ns, + pdata->clock_name, + pdata->interleave ? "Yes" : "No", + buffer_base, + primary_base, + secondary_base, + interrupt_number + ); + + #ifdef CONFIG_MTD_PARTITIONS + + o += sprintf(buf + o, + "Partition Count : %u\n" + , + pdata->partition_count + ); + + /* Loop over partitions. */ + + for (i = 0; i < pdata->partition_count; i++) { + + partition = pdata->partitions + i; + + o += sprintf(buf+o, " [%d]\n", i); + o += sprintf(buf+o, " Name : %s\n", partition->name); + + switch (partition->offset) { + + case MTDPART_OFS_NXTBLK: + o += sprintf(buf+o, " Offset: " + "MTDPART_OFS_NXTBLK\n"); + break; + case MTDPART_OFS_APPEND: + o += sprintf(buf+o, " Offset: " + "MTDPART_OFS_APPEND\n"); + break; + default: + o += sprintf(buf+o, " Offset: %u (%u MiB)\n", + partition->offset, + partition->offset / (1024 * 1024)); + break; + + } + + if (partition->size == MTDPART_SIZ_FULL) { + o += sprintf(buf+o, " Size : " + "MTDPART_SIZ_FULL\n"); + } else { + o += sprintf(buf+o, " Size : %u (%u MiB)\n", + partition->size, + partition->size / (1024 * 1024)); + } + + } + + #endif + + return o; + +} + +/** + * show_device_physical_geometry() - Shows the physical Flash device geometry. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_physical_geometry(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + struct physical_geometry *physical = &this->physical_geometry; + + return sprintf(buf, + "Chip Count : %u\n" + "Chip Size in Bytes : %llu\n" + "Block Size in Bytes : %u\n" + "Page Data Size in Bytes: %u\n" + "Page OOB Size in Bytes : %u\n" + , + physical->chip_count, + physical->chip_size, + physical->block_size, + physical->page_data_size, + physical->page_oob_size + ); + +} + +/** + * show_device_nfc_info() - Shows the NFC-specific information. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_nfc_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long parent_clock_rate_in_hz; + unsigned long clock_rate_in_hz; + struct clk *parent_clock; + struct imx_nfc_data *this = dev_get_drvdata(dev); + struct nfc_hal *nfc = this->nfc; + + parent_clock = clk_get_parent(this->clock); + parent_clock_rate_in_hz = clk_get_rate(parent_clock); + clock_rate_in_hz = clk_get_rate(this->clock); + + return sprintf(buf, + "Major Version : %u\n" + "Minor Version : %u\n" + "Max Chip Count : %u\n" + "Max Buffer Count : %u\n" + "Spare Buffer Stride : %u\n" + "Has Secondary Registers : %s\n" + "Can Be Symmetric : %s\n" + "Exposes Ready/Busy : %s\n" + "Parent Clock Rate in Hz : %lu\n" + "Clock Rate in Hz : %lu\n" + "Symmetric Clock : %s\n" + , + nfc->major_version, + nfc->minor_version, + nfc->max_chip_count, + nfc->max_buffer_count, + nfc->spare_buf_stride, + nfc->has_secondary_regs ? "Yes" : "No", + nfc->can_be_symmetric ? "Yes" : "No", + nfc->is_ready ? "Yes" : "No", + parent_clock_rate_in_hz, + clock_rate_in_hz, + this->nfc->get_symmetric(this) ? "Yes" : "No" + ); + +} + +/** + * show_device_nfc_geometry() - Shows the NFC view of the device geometry. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_nfc_geometry(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + + return sprintf(buf, + "Page Data Size in Bytes : %u\n" + "Page OOB Size in Bytes : %u\n" + "ECC Algorithm : %s\n" + "ECC Strength : %u\n" + "Buffers in Use : %u\n" + "Spare Buffer Size in Use: %u\n" + "Spare Buffer Spillover : %u\n" + , + this->nfc_geometry->page_data_size, + this->nfc_geometry->page_oob_size, + this->nfc_geometry->ecc_algorithm, + this->nfc_geometry->ecc_strength, + this->nfc_geometry->buffer_count, + this->nfc_geometry->spare_buf_size, + this->nfc_geometry->spare_buf_spill + ); + +} + +/** + * show_device_logical_geometry() - Shows the logical device geometry. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_logical_geometry(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + struct logical_geometry *logical = &this->logical_geometry; + + return sprintf(buf, + "Chip Count : %u\n" + "Chip Size in Bytes : %u\n" + "Usable Size in Bytes : %u\n" + "Block Size in Bytes : %u\n" + "Page Data Size in Bytes: %u\n" + "Page OOB Size in Bytes : %u\n" + , + logical->chip_count, + logical->chip_size, + logical->usable_size, + logical->block_size, + logical->page_data_size, + logical->page_oob_size + ); + +} + +/** + * show_device_mtd_nand_info() - Shows the device's MTD NAND-specific info. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_mtd_nand_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int o = 0; + unsigned int i; + unsigned int j; + static const unsigned int columns = 8; + struct imx_nfc_data *this = dev_get_drvdata(dev); + struct nand_chip *nand = &this->nand; + + o += sprintf(buf + o, + "Options : 0x%08x\n" + "Chip Count : %u\n" + "Chip Size : %lu\n" + "Minimum Writable Size: %u\n" + "Page Shift : %u\n" + "Page Mask : 0x%x\n" + "Block Shift : %u\n" + "BBT Block Shift : %u\n" + "Chip Shift : %u\n" + "Block Mark Offset : %u\n" + "Cached Page Number : %d\n" + , + nand->options, + nand->numchips, + nand->chipsize, + nand->subpagesize, + nand->page_shift, + nand->pagemask, + nand->phys_erase_shift, + nand->bbt_erase_shift, + nand->chip_shift, + nand->badblockpos, + nand->pagebuf + ); + + o += sprintf(buf + o, + "ECC Byte Count : %u\n" + , + nand->ecc.layout->eccbytes + ); + + /* Loop over rows. */ + + for (i = 0; (i * columns) < nand->ecc.layout->eccbytes; i++) { + + /* Loop over columns within rows. */ + + for (j = 0; j < columns; j++) { + + if (((i * columns) + j) >= nand->ecc.layout->eccbytes) + break; + + o += sprintf(buf + o, " %3u", + nand->ecc.layout->eccpos[(i * columns) + j]); + + } + + o += sprintf(buf + o, "\n"); + + } + + o += sprintf(buf + o, + "OOB Available Bytes : %u\n" + , + nand->ecc.layout->oobavail + ); + + j = 0; + + for (i = 0; j < nand->ecc.layout->oobavail; i++) { + + j += nand->ecc.layout->oobfree[i].length; + + o += sprintf(buf + o, + " [%3u, %2u]\n" + , + nand->ecc.layout->oobfree[i].offset, + nand->ecc.layout->oobfree[i].length + ); + + } + + return o; + +} + +/** + * show_device_mtd_info() - Shows the device's MTD-specific information. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_mtd_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int o = 0; + unsigned int i; + unsigned int j; + static const unsigned int columns = 8; + struct imx_nfc_data *this = dev_get_drvdata(dev); + struct mtd_info *mtd = &this->mtd; + + o += sprintf(buf + o, + "Name : %s\n" + "Type : %u\n" + "Flags : 0x%08x\n" + "Size in Bytes : %u\n" + "Erase Region Count : %d\n" + "Erase Size in Bytes: %u\n" + "Write Size in Bytes: %u\n" + "OOB Size in Bytes : %u\n" + "Errors Corrected : %u\n" + "Failed Reads : %u\n" + "Bad Block Count : %u\n" + "BBT Block Count : %u\n" + , + mtd->name, + mtd->type, + mtd->flags, + mtd->size, + mtd->numeraseregions, + mtd->erasesize, + mtd->writesize, + mtd->oobsize, + mtd->ecc_stats.corrected, + mtd->ecc_stats.failed, + mtd->ecc_stats.badblocks, + mtd->ecc_stats.bbtblocks + ); + + o += sprintf(buf + o, + "ECC Byte Count : %u\n" + , + mtd->ecclayout->eccbytes + ); + + /* Loop over rows. */ + + for (i = 0; (i * columns) < mtd->ecclayout->eccbytes; i++) { + + /* Loop over columns within rows. */ + + for (j = 0; j < columns; j++) { + + if (((i * columns) + j) >= mtd->ecclayout->eccbytes) + break; + + o += sprintf(buf + o, " %3u", + mtd->ecclayout->eccpos[(i * columns) + j]); + + } + + o += sprintf(buf + o, "\n"); + + } + + o += sprintf(buf + o, + "OOB Available Bytes: %u\n" + , + mtd->ecclayout->oobavail + ); + + j = 0; + + for (i = 0; j < mtd->ecclayout->oobavail; i++) { + + j += mtd->ecclayout->oobfree[i].length; + + o += sprintf(buf + o, + " [%3u, %2u]\n" + , + mtd->ecclayout->oobfree[i].offset, + mtd->ecclayout->oobfree[i].length + ); + + } + + return o; + +} + +/** + * show_device_bbt_pages() - Shows the pages in which BBT's appear. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_bbt_pages(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int o = 0; + unsigned int i; + struct imx_nfc_data *this = dev_get_drvdata(dev); + struct nand_chip *nand = &this->nand; + + /* Loop over main BBT pages. */ + + if (nand->bbt_td) + for (i = 0; i < NAND_MAX_CHIPS; i++) + o += sprintf(buf + o, "%d: 0x%08x\n", + i, nand->bbt_td->pages[i]); + + /* Loop over mirror BBT pages. */ + + if (nand->bbt_md) + for (i = 0; i < NAND_MAX_CHIPS; i++) + o += sprintf(buf + o, "%d: 0x%08x\n", + i, nand->bbt_md->pages[i]); + + return o; + +} + +/** + * show_device_cycle_in_ns() - Shows the device's cycle in ns. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_cycle_in_ns(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + return sprintf(buf, "%u\n", get_cycle_in_ns(this)); +} + +/** + * store_device_cycle_in_ns() - Sets the device's cycle in ns. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_cycle_in_ns(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int error; + unsigned long new_cycle_in_ns; + struct imx_nfc_data *this = dev_get_drvdata(dev); + + /* Look for nonsense. */ + + if (!size) + return -EINVAL; + + /* Try to understand the new cycle period. */ + + if (strict_strtoul(buf, 0, &new_cycle_in_ns)) + return -EINVAL; + + /* Try to implement the new cycle period. */ + + error = this->nfc->set_closest_cycle(this, new_cycle_in_ns); + + if (error) + return -EINVAL; + + /* Return success. */ + + return size; + +} + +/** + * show_device_interrupt_override() - Shows the device's interrupt override. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_interrupt_override(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + + switch (this->interrupt_override) { + + case NEVER: + return sprintf(buf, "-1\n"); + break; + + case DRIVER_CHOICE: + return sprintf(buf, "0\n"); + break; + + case ALWAYS: + return sprintf(buf, "1\n"); + break; + + default: + return sprintf(buf, "?\n"); + break; + + } + +} + +/** + * store_device_interrupt_override() - Sets the device's interrupt override. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_interrupt_override(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + + if (!strcmp(buf, "-1")) + this->interrupt_override = NEVER; + else if (!strcmp(buf, "0")) + this->interrupt_override = DRIVER_CHOICE; + else if (!strcmp(buf, "1")) + this->interrupt_override = ALWAYS; + else + return -EINVAL; + + return size; + +} + +/** + * show_device_auto_op_override() - Shows the device's automatic op override. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_auto_op_override(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + + switch (this->auto_op_override) { + + case NEVER: + return sprintf(buf, "-1\n"); + break; + + case DRIVER_CHOICE: + return sprintf(buf, "0\n"); + break; + + case ALWAYS: + return sprintf(buf, "1\n"); + break; + + default: + return sprintf(buf, "?\n"); + break; + + } + +} + +/** + * store_device_auto_op_override() - Sets the device's automatic op override. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_auto_op_override(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + + if (!strcmp(buf, "-1")) + this->auto_op_override = NEVER; + else if (!strcmp(buf, "0")) + this->auto_op_override = DRIVER_CHOICE; + else if (!strcmp(buf, "1")) + this->auto_op_override = ALWAYS; + else + return -EINVAL; + + return size; + +} + +/** + * show_device_inject_ecc_error() - Shows the device's error injection flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_inject_ecc_error(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", this->inject_ecc_error); + +} + +/** + * store_device_inject_ecc_error() - Sets the device's error injection flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_inject_ecc_error(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + unsigned long new_inject_ecc_error; + struct imx_nfc_data *this = dev_get_drvdata(dev); + + /* Look for nonsense. */ + + if (!size) + return -EINVAL; + + /* Try to understand the new cycle period. */ + + if (strict_strtol(buf, 0, &new_inject_ecc_error)) + return -EINVAL; + + /* Store the value. */ + + this->inject_ecc_error = new_inject_ecc_error; + + /* Return success. */ + + return size; + +} + +/** + * store_device_invalidate_page_cache() - Invalidates the device's page cache. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_invalidate_page_cache(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct imx_nfc_data *this = dev_get_drvdata(dev); + + /* Invalidate the page cache. */ + + this->nand.pagebuf = -1; + + /* Return success. */ + + return size; + +} + +/* Device attributes that appear in sysfs. */ + +static DEVICE_ATTR(platform_info , 0444, show_device_platform_info , 0); +static DEVICE_ATTR(physical_geometry, 0444, show_device_physical_geometry, 0); +static DEVICE_ATTR(nfc_info , 0444, show_device_nfc_info , 0); +static DEVICE_ATTR(nfc_geometry , 0444, show_device_nfc_geometry , 0); +static DEVICE_ATTR(logical_geometry , 0444, show_device_logical_geometry , 0); +static DEVICE_ATTR(mtd_nand_info , 0444, show_device_mtd_nand_info , 0); +static DEVICE_ATTR(mtd_info , 0444, show_device_mtd_info , 0); +static DEVICE_ATTR(bbt_pages , 0444, show_device_bbt_pages , 0); + +static DEVICE_ATTR(cycle_in_ns, 0644, + show_device_cycle_in_ns, store_device_cycle_in_ns); + +static DEVICE_ATTR(interrupt_override, 0644, + show_device_interrupt_override, store_device_interrupt_override); + +static DEVICE_ATTR(auto_op_override, 0644, + show_device_auto_op_override, store_device_auto_op_override); + +static DEVICE_ATTR(inject_ecc_error, 0644, + show_device_inject_ecc_error, store_device_inject_ecc_error); + +static DEVICE_ATTR(invalidate_page_cache, 0644, + 0, store_device_invalidate_page_cache); + +static struct device_attribute *device_attributes[] = { + &dev_attr_platform_info, + &dev_attr_physical_geometry, + &dev_attr_nfc_info, + &dev_attr_nfc_geometry, + &dev_attr_logical_geometry, + &dev_attr_mtd_nand_info, + &dev_attr_mtd_info, + &dev_attr_bbt_pages, + &dev_attr_cycle_in_ns, + &dev_attr_interrupt_override, + &dev_attr_auto_op_override, + &dev_attr_inject_ecc_error, + &dev_attr_invalidate_page_cache, +}; + +/** + * validate_the_platform() - Validates information about the platform. + * + * Note that this function doesn't validate the NFC version. That's done when + * the probing process attempts to configure for the specific hardware version. + * + * @pdev: A pointer to the platform device. + */ +static int validate_the_platform(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx_nfc_platform_data *pdata = pdev->dev.platform_data; + + /* Validate the clock name. */ + + if (!pdata->clock_name) { + dev_err(dev, "No clock name\n"); + return -ENXIO; + } + + /* Validate the partitions. */ + + if ((pdata->partitions && (!pdata->partition_count)) || + (!pdata->partitions && (pdata->partition_count))) { + dev_err(dev, "Bad partition data\n"); + return -ENXIO; + } + + /* Return success */ + + return 0; + +} + +/** + * set_up_the_nfc_hal() - Sets up for the specific NFC hardware HAL. + * + * @this: Per-device data. + */ +static int set_up_the_nfc_hal(struct imx_nfc_data *this) +{ + unsigned int i; + struct nfc_hal *p; + struct imx_nfc_platform_data *pdata = this->pdata; + + for (i = 0; i < ARRAY_SIZE(nfc_hals); i++) { + + p = nfc_hals[i]; + + /* + * Restrict to 3.2 until others are fully implemented. + * + * TODO: Remove this. + */ + + if ((p->major_version != 3) && (p->minor_version != 2)) + continue; + + if ((p->major_version == pdata->nfc_major_version) && + (p->minor_version == pdata->nfc_minor_version)) { + this->nfc = p; + return 0; + break; + } + + } + + dev_err(this->dev, "Unkown NFC version %d.%d\n", + pdata->nfc_major_version, pdata->nfc_minor_version); + + return !0; + +} + +/** + * acquire_resources() - Tries to acquire resources. + * + * @this: Per-device data. + */ +static int acquire_resources(struct imx_nfc_data *this) +{ + + int error = 0; + struct platform_device *pdev = this->pdev; + struct device *dev = this->dev; + struct imx_nfc_platform_data *pdata = this->pdata; + struct resource *r; + + /* Find the buffers and map them. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, + IMX_NFC_BUFFERS_ADDR_RES_NAME); + + if (!r) { + dev_err(dev, "Can't get '%s'\n", IMX_NFC_BUFFERS_ADDR_RES_NAME); + error = -ENXIO; + goto exit_buffers; + } + + this->buffers = ioremap(r->start, r->end - r->start + 1); + + if (!this->buffers) { + dev_err(dev, "Can't remap buffers\n"); + error = -EIO; + goto exit_buffers; + } + + /* Find the primary registers and map them. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, + IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME); + + if (!r) { + dev_err(dev, "Can't get '%s'\n", + IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME); + error = -ENXIO; + goto exit_primary_registers; + } + + this->primary_regs = ioremap(r->start, r->end - r->start + 1); + + if (!this->primary_regs) { + dev_err(dev, "Can't remap the primary registers\n"); + error = -EIO; + goto exit_primary_registers; + } + + /* Check for secondary registers. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, + IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME); + + if (r && !this->nfc->has_secondary_regs) { + + dev_err(dev, "Resource '%s' should not be present\n", + IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME); + error = -ENXIO; + goto exit_secondary_registers; + + } + + if (this->nfc->has_secondary_regs) { + + if (!r) { + dev_err(dev, "Can't get '%s'\n", + IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME); + error = -ENXIO; + goto exit_secondary_registers; + } + + this->secondary_regs = ioremap(r->start, r->end - r->start + 1); + + if (!this->secondary_regs) { + dev_err(dev, + "Can't remap the secondary registers\n"); + error = -EIO; + goto exit_secondary_registers; + } + + } + + /* Find out what our interrupt is and try to own it. */ + + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, + IMX_NFC_INTERRUPT_RES_NAME); + + if (!r) { + dev_err(dev, "Can't get '%s'\n", IMX_NFC_INTERRUPT_RES_NAME); + error = -ENXIO; + goto exit_irq; + } + + this->interrupt = r->start; + + error = request_irq(this->interrupt, + nfc_util_isr, 0, this->dev->bus_id, this); + + if (error) { + dev_err(dev, "Can't own interrupt %d\n", this->interrupt); + goto exit_irq; + } + + /* Find out the name of our clock and try to own it. */ + + this->clock = clk_get(dev, pdata->clock_name); + + if (this->clock == ERR_PTR(-ENOENT)) { + dev_err(dev, "Can't get clock '%s'\n", pdata->clock_name); + error = -ENXIO; + goto exit_clock; + } + + /* Return success. */ + + return 0; + + /* Error return paths begin here. */ + +exit_clock: + free_irq(this->interrupt, this); +exit_irq: + if (this->secondary_regs) + iounmap(this->secondary_regs); +exit_secondary_registers: + iounmap(this->primary_regs); +exit_primary_registers: + iounmap(this->buffers); +exit_buffers: + return error; + +} + +/** + * release_resources() - Releases resources. + * + * @this: Per-device data. + */ +static void release_resources(struct imx_nfc_data *this) +{ + + /* Release our clock. */ + + clk_disable(this->clock); + clk_put(this->clock); + + /* Release our interrupt. */ + + free_irq(this->interrupt, this); + + /* Release mapped memory. */ + + iounmap(this->buffers); + iounmap(this->primary_regs); + if (this->secondary_regs) + iounmap(this->secondary_regs); + +} + +/** + * register_with_mtd() - Registers this medium with MTD. + * + * @this: Per-device data. + */ +static int register_with_mtd(struct imx_nfc_data *this) +{ + int error = 0; + struct mtd_info *mtd = &this->mtd; + struct nand_chip *nand = &this->nand; + struct device *dev = this->dev; + struct imx_nfc_platform_data *pdata = this->pdata; + + /* Link the MTD structures together, along with our own data. */ + + mtd->priv = nand; + nand->priv = this; + + /* Prepare the MTD structure. */ + + mtd->owner = THIS_MODULE; + + /* + * Signal Control Functions + */ + + nand->cmd_ctrl = mil_cmd_ctrl; + + /* + * Chip Control Functions + * + * Not all of our NFC hardware versions expose Ready/Busy signals. For + * versions that don't, the is_ready function pointer will be NULL. In + * those cases, we leave the dev_ready member unassigned, which will + * cause the HIL to use a reference implementation's algorithm to + * discover when the hardware is ready. + */ + + nand->select_chip = mil_select_chip; + nand->cmdfunc = mil_cmdfunc; + nand->waitfunc = mil_waitfunc; + + if (this->nfc->is_ready) + nand->dev_ready = mil_dev_ready; + + /* + * Low-level I/O Functions + */ + + nand->read_byte = mil_read_byte; + nand->read_word = mil_read_word; + nand->read_buf = mil_read_buf; + nand->write_buf = mil_write_buf; + nand->verify_buf = mil_verify_buf; + + /* + * ECC Control Functions + */ + + nand->ecc.hwctl = mil_ecc_hwctl; + nand->ecc.calculate = mil_ecc_calculate; + nand->ecc.correct = mil_ecc_correct; + + /* + * ECC-Aware I/O Functions + */ + + nand->ecc.read_page = mil_ecc_read_page; + nand->ecc.read_page_raw = mil_ecc_read_page_raw; + nand->ecc.write_page = mil_ecc_write_page; + nand->ecc.write_page_raw = mil_ecc_write_page_raw; + + /* + * High-level I/O Functions + */ + + nand->write_page = mil_write_page; + nand->ecc.read_oob = mil_ecc_read_oob; + nand->ecc.write_oob = mil_ecc_write_oob; + + /* + * Bad Block Marking Functions + * + * We want to use the reference block_bad and block_markbad + * implementations, so we don't assign those members. + */ + + nand->scan_bbt = mil_scan_bbt; + + /* + * Error Recovery Functions + * + * We don't fill in the errstat function pointer because it's optional + * and we don't have a need for it. + */ + + /* + * Device Attributes + * + * We don't fill in the chip_delay member because we don't have a need + * for it. + * + * We support only 8-bit Flash bus width. + */ + + /* + * ECC Attributes + * + * Members that aren't set here are configured by a version-specific + * set_geometry() function. + */ + + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = NFC_MAIN_BUF_SIZE; + nand->ecc.prepad = 0; + nand->ecc.postpad = 0; + + /* + * Bad Block Management Attributes + * + * We don't fill in the following attributes: + * + * badblockpos + * bbt + * badblock_pattern + * bbt_erase_shift + * + * These attributes aren't hardware-specific, and the HIL makes fine + * choices without our help. + */ + + nand->options |= NAND_USE_FLASH_BBT; + nand->bbt_td = &bbt_main_descriptor; + nand->bbt_md = &bbt_mirror_descriptor; + + /* + * Device Control + * + * We don't fill in the controller attribute. In principle, we could set + * up a structure to represent the controller. However, since it's + * vanishingly improbable that we'll have more than one medium behind + * the controller, it's not worth the effort. We let the HIL handle it. + */ + + /* + * Memory-mapped I/O + * + * We don't fill in the following attributes: + * + * IO_ADDR_R + * IO_ADDR_W + * + * None of these are necessary because we don't have a memory-mapped + * implementation. + */ + + /* + * Install a "fake" ECC layout. + * + * We'll be calling nand_scan() to do the final MTD setup. If we haven't + * already chosen an ECC layout, then nand_scan() will choose one based + * on the part geometry it discovers. Unfortunately, it doesn't make + * good choices. It would be best if we could install the correct ECC + * layout now, before we call nand_scan(). We can't do that because we + * don't know the medium geometry yet. Here, we install a "fake" ECC + * layout just to stop nand_scan() from trying to pick on for itself. + * Later, in imx_nfc_scan_bbt(), when we know the medium geometry, we'll + * install the correct choice. + * + * Of course, this tactic depends critically on nand_scan() not using + * the fake layout before we can install a good one. This is in fact the + * case. + */ + + nand->ecc.layout = &nfc_geometry_512_16_RS_ECC1.mtd_layout; + + /* + * Ask the NAND Flash system to scan for chips. + * + * This will fill in reference implementations for all the members of + * the MTD structures that we didn't set, and will make the medium fully + * usable. + */ + + error = nand_scan(mtd, this->nfc->max_chip_count); + + if (error) { + dev_err(dev, "Chip scan failed\n"); + error = -ENXIO; + goto exit_scan; + } + + /* Register the MTD that represents the entire medium. */ + + mtd->name = "NAND Flash Medium"; + + add_mtd_device(mtd); + + /* Check if we're doing partitions and register MTD's accordingly. */ + + #ifdef CONFIG_MTD_PARTITIONS + + /* + * Look for partition information. If we find some, install + * them. Otherwise, use the partitions handed to us by the + * platform. + */ + + this->partition_count = + parse_mtd_partitions(mtd, partition_source_types, + &this->partitions, 0); + + if ((this->partition_count <= 0) && (pdata->partitions)) { + this->partition_count = pdata->partition_count; + this->partitions = pdata->partitions; + } + + if (this->partitions) + add_mtd_partitions(mtd, this->partitions, + this->partition_count); + + #endif + + /* Return success. */ + + return 0; + + /* Error return paths begin here. */ + +exit_scan: + return error; + +} + +/** + * unregister_with_mtd() - Unregisters this medium with MTD. + * + * @this: Per-device data. + */ +static void unregister_with_mtd(struct imx_nfc_data *this) +{ + + /* Get MTD to let go. */ + + nand_release(&this->mtd); + +} + +/** + * manage_sysfs_files() - Creates/removes sysfs files for this device. + * + * @this: Per-device data. + */ +static void manage_sysfs_files(struct imx_nfc_data *this, int create) +{ + int error; + unsigned int i; + struct device_attribute **attr; + + for (i = 0, attr = device_attributes; + i < ARRAY_SIZE(device_attributes); i++, attr++) { + + if (create) { + error = device_create_file(this->dev, *attr); + if (error) { + while (--attr >= device_attributes) + device_remove_file(this->dev, *attr); + return; + } + } else { + device_remove_file(this->dev, *attr); + } + + } + +} + +/** + * imx_nfc_probe() - Probes for a device and, if possible, takes ownership. + * + * @pdev: A pointer to the platform device. + */ +static int imx_nfc_probe(struct platform_device *pdev) +{ + int error = 0; + char *symmetric_clock; + struct clk *parent_clock; + unsigned long parent_clock_rate_in_hz; + unsigned long parent_clock_rate_in_mhz; + unsigned long nfc_clock_rate_in_hz; + unsigned long nfc_clock_rate_in_mhz; + unsigned long clock_divisor; + unsigned long cycle_in_ns; + struct device *dev = &pdev->dev; + struct imx_nfc_platform_data *pdata = pdev->dev.platform_data; + struct imx_nfc_data *this = 0; + + /* Say hello. */ + + dev_info(dev, "Probing...\n"); + + /* Check if we're enabled. */ + + if (!imx_nfc_module_enable) { + dev_info(dev, "Disabled\n"); + return -ENXIO; + } + + /* Validate the platform device data. */ + + error = validate_the_platform(pdev); + + if (error) + goto exit_validate_platform; + + /* Allocate memory for the per-device data. */ + + this = kzalloc(sizeof(*this), GFP_KERNEL); + + if (!this) { + dev_err(dev, "Failed to allocate per-device memory\n"); + error = -ENOMEM; + goto exit_allocate_this; + } + + /* Link our per-device data to the owning device. */ + + platform_set_drvdata(pdev, this); + + /* Fill in the convenience pointers in our per-device data. */ + + this->pdev = pdev; + this->dev = &pdev->dev; + this->pdata = pdata; + + /* Initialize the interrupt service pathway. */ + + init_completion(&this->done); + + /* Set up the NFC HAL. */ + + error = set_up_the_nfc_hal(this); + + if (error) + goto exit_set_up_nfc_hal; + + /* Attempt to acquire the resources we need. */ + + error = acquire_resources(this); + + if (error) + goto exit_acquire_resources; + + /* Initialize the NFC HAL. */ + + if (this->nfc->init(this)) { + error = -ENXIO; + goto exit_nfc_init; + } + + /* Tell the platform we're bringing this device up. */ + + if (pdata->init) + error = pdata->init(); + + if (error) + goto exit_platform_init; + + /* Report. */ + + parent_clock = clk_get_parent(this->clock); + parent_clock_rate_in_hz = clk_get_rate(parent_clock); + parent_clock_rate_in_mhz = parent_clock_rate_in_hz / 1000000; + nfc_clock_rate_in_hz = clk_get_rate(this->clock); + nfc_clock_rate_in_mhz = nfc_clock_rate_in_hz / 1000000; + + clock_divisor = parent_clock_rate_in_hz / nfc_clock_rate_in_hz; + symmetric_clock = this->nfc->get_symmetric(this) ? "Yes" : "No"; + cycle_in_ns = get_cycle_in_ns(this); + + dev_dbg(dev, "-------------\n"); + dev_dbg(dev, "Configuration\n"); + dev_dbg(dev, "-------------\n"); + dev_dbg(dev, "NFC Version : %d.%d\n" , this->nfc->major_version, + this->nfc->minor_version); + dev_dbg(dev, "Buffers : 0x%p\n" , this->buffers); + dev_dbg(dev, "Primary Regs : 0x%p\n" , this->primary_regs); + dev_dbg(dev, "Secondary Regs : 0x%p\n" , this->secondary_regs); + dev_dbg(dev, "Interrupt : %u\n" , this->interrupt); + dev_dbg(dev, "Clock Name : %s\n" , pdata->clock_name); + dev_dbg(dev, "Parent Clock Rate: %lu Hz (%lu MHz)\n", + parent_clock_rate_in_hz, + parent_clock_rate_in_mhz); + dev_dbg(dev, "Clock Divisor : %lu\n", clock_divisor); + dev_dbg(dev, "NFC Clock Rate : %lu Hz (%lu MHz)\n", + nfc_clock_rate_in_hz, + nfc_clock_rate_in_mhz); + dev_dbg(dev, "Symmetric Clock : %s\n" , symmetric_clock); + dev_dbg(dev, "Actual Cycle : %lu ns\n" , cycle_in_ns); + dev_dbg(dev, "Target Cycle : %u ns\n" , pdata->target_cycle_in_ns); + + /* Initialize the Medium Abstraction Layer. */ + + mal_init(this); + + /* Initialize the MTD Interface Layer. */ + + mil_init(this); + + /* Register this medium with MTD. */ + + error = register_with_mtd(this); + + if (error) + goto exit_mtd_registration; + + /* Create sysfs entries for this device. */ + + manage_sysfs_files(this, true); + + /* Return success. */ + + return 0; + + /* Error return paths begin here. */ + +exit_mtd_registration: + if (pdata->exit) + pdata->exit(); +exit_platform_init: + this->nfc->exit(this); +exit_nfc_init: +exit_acquire_resources: +exit_set_up_nfc_hal: + platform_set_drvdata(pdev, NULL); + kfree(this); +exit_allocate_this: +exit_validate_platform: + return error; + +} + +/** + * imx_nfc_remove() - Dissociates this driver from the given device. + * + * @pdev: A pointer to the device. + */ +static int __exit imx_nfc_remove(struct platform_device *pdev) +{ + struct imx_nfc_data *this = platform_get_drvdata(pdev); + + /* Remove sysfs entries for this device. */ + + manage_sysfs_files(this, false); + + /* Unregister with the NAND Flash MTD system. */ + + unregister_with_mtd(this); + + /* Tell the platform we're shutting down this device. */ + + if (this->pdata->exit) + this->pdata->exit(); + + /* Shut down the NFC. */ + + this->nfc->exit(this); + + /* Release our resources. */ + + release_resources(this); + + /* Unlink our per-device data from the platform device. */ + + platform_set_drvdata(pdev, NULL); + + /* Free our per-device data. */ + + kfree(this); + + /* Return success. */ + + return 0; +} + +#ifdef CONFIG_PM + +/** + * suspend() - Puts the NFC in a low power state. + * + * Refer to Documentation/driver-model/driver.txt for more information. + * + * @pdev: A pointer to the device. + * @state: The new power state. + */ + +static int imx_nfc_suspend(struct platform_device *pdev, pm_message_t state) +{ + int error = 0; + struct imx_nfc_data *this = platform_get_drvdata(pdev); + struct mtd_info *mtd = &this->mtd; + struct device *dev = &this->pdev->dev; + + dev_dbg(dev, "Suspending...\n"); + + /* Suspend MTD's use of this device. */ + + error = mtd->suspend(mtd); + + /* Suspend the actual hardware. */ + + clk_disable(this->clock); + + return error; + +} + +/** + * resume() - Brings the NFC back from a low power state. + * + * Refer to Documentation/driver-model/driver.txt for more information. + * + * @pdev: A pointer to the device. + */ +static int imx_nfc_resume(struct platform_device *pdev) +{ + struct imx_nfc_data *this = platform_get_drvdata(pdev); + struct mtd_info *mtd = &this->mtd; + struct device *dev = &this->pdev->dev; + + dev_dbg(dev, "Resuming...\n"); + + /* Resume MTD's use of this device. */ + + mtd->resume(mtd); + + return 0; + +} + +#else + +#define suspend NULL +#define resume NULL + +#endif /* CONFIG_PM */ + +/* + * This structure represents this driver to the platform management system. + */ +static struct platform_driver imx_nfc_driver = { + .driver = { + .name = IMX_NFC_DRIVER_NAME, + }, + .probe = imx_nfc_probe, + .remove = __exit_p(imx_nfc_remove), + .suspend = imx_nfc_suspend, + .resume = imx_nfc_resume, +}; + +/** + * imx_nfc_init() - Initializes this module. + */ +static int __init imx_nfc_init(void) +{ + + pr_info("i.MX NFC driver %s\n", DRIVER_VERSION); + + /* Register this driver with the platform management system. */ + + if (platform_driver_register(&imx_nfc_driver) != 0) { + pr_err("i.MX NFC driver registration failed\n"); + return -ENODEV; + } + + return 0; + +} + +/** + * imx_nfc_exit() - Deactivates this module. + */ +static void __exit imx_nfc_exit(void) +{ + pr_debug("i.MX NFC driver exiting...\n"); + platform_driver_unregister(&imx_nfc_driver); +} + +module_init(imx_nfc_init); +module_exit(imx_nfc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("i.MX NAND Flash Controller Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 88785032322a..66f38d598e13 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mtd/nand/mxc_nd.c b/drivers/mtd/nand/mxc_nd.c new file mode 100644 index 000000000000..7344bafa77fa --- /dev/null +++ b/drivers/mtd/nand/mxc_nd.c @@ -0,0 +1,1413 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_nd.h" + +#define DVR_VER "2.1" + +struct mxc_mtd_s { + struct mtd_info mtd; + struct nand_chip nand; + struct mtd_partition *parts; + struct device *dev; +}; + +static struct mxc_mtd_s *mxc_nand_data; + +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 +/* + * Macros to get half word and bit positions of ECC + */ +#define COLPOS(x) ((x) >> 4) +#define BITPOS(x) ((x) & 0xf) + +/* Define single bit Error positions in Main & Spare area */ +#define MAIN_SINGLEBIT_ERROR 0x4 +#define SPARE_SINGLEBIT_ERROR 0x1 + +struct nand_info { + bool bSpareOnly; + bool bStatusRequest; + u16 colAddr; +}; + +static struct nand_info g_nandfc_info; + +#ifdef CONFIG_MTD_NAND_MXC_SWECC +static int hardware_ecc; +#else +static int hardware_ecc = 1; +#endif + +#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 +static int Ecc_disabled; +#endif + +static int is2k_Pagesize; + +static struct clk *nfc_clk; + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_8 = { + .eccbytes = 5, + .eccpos = {6, 7, 8, 9, 10}, + .oobfree = {{0, 5}, {11, 5} } +}; + +static struct nand_ecclayout nand_hw_eccoob_16 = { + .eccbytes = 5, + .eccpos = {6, 7, 8, 9, 10}, + .oobfree = {{0, 6}, {12, 4} } +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 20, + .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, + 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, + .oobfree = { + {.offset = 0, + .length = 5}, + + {.offset = 11, + .length = 10}, + + {.offset = 27, + .length = 10}, + + {.offset = 43, + .length = 10}, + + {.offset = 59, + .length = 5} + } +}; + +/*! + * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors + */ + +/*! + * @file mxc_nd.c + * + * @brief This file contains the hardware specific layer for NAND Flash on + * MXC processor + * + * @ingroup NAND_MTD + */ + +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; +#endif + +static wait_queue_head_t irq_waitq; + +static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) +{ + NFC_CONFIG1 |= NFC_INT_MSK; /* Disable interrupt */ + wake_up(&irq_waitq); + + return IRQ_RETVAL(1); +} + +/*! + * This function polls the NANDFC to wait for the basic operation to complete by + * checking the INT bit of config2 register. + * + * @param maxRetries number of retry attempts (separated by 1 us) + * @param param parameter for debug + * @param useirq True if IRQ should be used rather than polling + */ +static void wait_op_done(int maxRetries, u16 param, bool useirq) +{ + if (useirq) { + if ((NFC_CONFIG2 & NFC_INT) == 0) { + NFC_CONFIG1 &= ~NFC_INT_MSK; /* Enable interrupt */ + wait_event(irq_waitq, NFC_CONFIG2 & NFC_INT); + } + NFC_CONFIG2 &= ~NFC_INT; + } else { + while (maxRetries-- > 0) { + if (NFC_CONFIG2 & NFC_INT) { + NFC_CONFIG2 &= ~NFC_INT; + break; + } + udelay(1); + } + if (maxRetries <= 0) + DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n", + __FUNCTION__, param); + } +} + +/*! + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @param cmd command for NAND Flash + * @param useirq True if IRQ should be used rather than polling + */ +static void send_cmd(u16 cmd, bool useirq) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd, useirq); + + NFC_FLASH_CMD = (u16) cmd; + NFC_CONFIG2 = NFC_CMD; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, cmd, useirq); +} + +/*! + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @param addr address to be written to NFC. + * @param islast True if this is the last address cycle for command + */ +static void send_addr(u16 addr, bool islast) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr, islast); + + NFC_FLASH_ADDR = addr; + NFC_CONFIG2 = NFC_ADDR; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, addr, islast); +} + +/*! + * This function requests the NANDFC to initate the transfer + * of data currently in the NANDFC RAM buffer to the NAND device. + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param bSpareOnly set true if only the spare area is transferred + */ +static void send_prog_page(u8 buf_id, bool bSpareOnly) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", bSpareOnly); + + /* NANDFC buffer 0 is used for page read/write */ + + NFC_BUF_ADDR = buf_id; + + /* Configure spare or page+spare access */ + if (!is2k_Pagesize) { + if (bSpareOnly) { + NFC_CONFIG1 |= NFC_SP_EN; + } else { + NFC_CONFIG1 &= ~(NFC_SP_EN); + } + } + NFC_CONFIG2 = NFC_INPUT; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, bSpareOnly, true); +} + +/*! + * This function will correct the single bit ECC error + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param eccpos Ecc byte and bit position + * @param bSpareOnly set to true if only spare area needs correction + */ + +static void mxc_nd_correct_error(u8 buf_id, u16 eccpos, bool bSpareOnly) +{ + u16 col; + u8 pos; + volatile u16 *buf; + + /* Get col & bit position of error + these macros works for both 8 & 16 bits */ + col = COLPOS(eccpos); /* Get half-word position */ + pos = BITPOS(eccpos); /* Get bit position */ + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nd_correct_error (col=%d pos=%d)\n", col, pos); + + /* Set the pointer for main / spare area */ + if (!bSpareOnly) { + buf = (volatile u16 *)(MAIN_AREA0 + col + (256 * buf_id)); + } else { + buf = (volatile u16 *)(SPARE_AREA0 + col + (8 * buf_id)); + } + + /* Fix the data */ + *buf ^= (1 << pos); +} + +/*! + * This function will maintains state of single bit Error + * in Main & spare area + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param spare set to true if only spare area needs correction + */ +static void mxc_nd_correct_ecc(u8 buf_id, bool spare) +{ +#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + static int lastErrMain, lastErrSpare; /* To maintain single bit + error in previous page */ +#endif + u16 value, ecc_status; + /* Read the ECC result */ + ecc_status = NFC_ECC_STATUS_RESULT; + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nd_correct_ecc (Ecc status=%x)\n", ecc_status); + +#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + /* Check for Error in Mainarea */ + if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) { + /* Check for error in previous page */ + if (lastErrMain && !spare) { + value = NFC_RSLTMAIN_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, false); + } else { + /* Set if single bit error in current page */ + lastErrMain = 1; + } + } else { + /* Reset if no single bit error in current page */ + lastErrMain = 0; + } + + /* Check for Error in Sparearea */ + if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) { + /* Check for error in previous page */ + if (lastErrSpare) { + value = NFC_RSLTSPARE_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, true); + } else { + /* Set if single bit error in current page */ + lastErrSpare = 1; + } + } else { + /* Reset if no single bit error in current page */ + lastErrSpare = 0; + } +#else + if (((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) + || ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR)) { + if (Ecc_disabled) { + if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) { + value = NFC_RSLTMAIN_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, false); + } + if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) { + value = NFC_RSLTSPARE_AREA; + /* Correct single bit error in Mainarea + NFC will not correct the error in + current page */ + mxc_nd_correct_error(buf_id, value, true); + } + + } else { + /* Disable ECC */ + NFC_CONFIG1 &= ~(NFC_ECC_EN); + Ecc_disabled = 1; + } + } else if (ecc_status == 0) { + if (Ecc_disabled) { + /* Enable ECC */ + NFC_CONFIG1 |= NFC_ECC_EN; + Ecc_disabled = 0; + } + } else { + /* 2-bit Error Do nothing */ + } +#endif /* CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 */ + +} + +/*! + * This function requests the NANDFC to initated the transfer + * of data from the NAND device into in the NANDFC ram buffer. + * + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param bSpareOnly set true if only the spare area is transferred + */ +static void send_read_page(u8 buf_id, bool bSpareOnly) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", bSpareOnly); + + /* NANDFC buffer 0 is used for page read/write */ + NFC_BUF_ADDR = buf_id; + + /* Configure spare or page+spare access */ + if (!is2k_Pagesize) { + if (bSpareOnly) { + NFC_CONFIG1 |= NFC_SP_EN; + } else { + NFC_CONFIG1 &= ~(NFC_SP_EN); + } + } + + NFC_CONFIG2 = NFC_OUTPUT; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, bSpareOnly, true); + + /* If there are single bit errors in + two consecutive page reads then + the error is not corrected by the + NFC for the second page. + Correct single bit error in driver */ + + mxc_nd_correct_ecc(buf_id, bSpareOnly); +} + +/*! + * This function requests the NANDFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + struct nand_chip *this = &mxc_nand_data->nand; + + /* NANDFC buffer 0 is used for device ID output */ + NFC_BUF_ADDR = 0x0; + + /* Read ID into main buffer */ + NFC_CONFIG1 &= (~(NFC_SP_EN)); + NFC_CONFIG2 = NFC_ID; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, 0, true); + + if (this->options & NAND_BUSWIDTH_16) { + volatile u16 *mainBuf = MAIN_AREA0; + + /* + * Pack the every-other-byte result for 16-bit ID reads + * into every-byte as the generic code expects and various + * chips implement. + */ + + mainBuf[0] = (mainBuf[0] & 0xff) | ((mainBuf[1] & 0xff) << 8); + mainBuf[1] = (mainBuf[2] & 0xff) | ((mainBuf[3] & 0xff) << 8); + mainBuf[2] = (mainBuf[4] & 0xff) | ((mainBuf[5] & 0xff) << 8); + } +} + +/*! + * This function requests the NANDFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ + volatile u16 *mainBuf = MAIN_AREA1; + u32 store; + u16 ret; + /* Issue status request to NAND device */ + + /* store the main area1 first word, later do recovery */ + store = *((u32 *) mainBuf); + /* + * NANDFC buffer 1 is used for device status to prevent + * corruption of read/write buffer on status requests. + */ + NFC_BUF_ADDR = 1; + + /* Read status into main buffer */ + NFC_CONFIG1 &= (~(NFC_SP_EN)); + NFC_CONFIG2 = NFC_STATUS; + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, 0, true); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + ret = mainBuf[0]; + *((u32 *) mainBuf) = store; + + return ret; +} + +/*! + * This functions is used by upper layer to checks if device is ready + * + * @param mtd MTD structure for the NAND Flash + * + * @return 0 if device is busy else 1 + */ +static int mxc_nand_dev_ready(struct mtd_info *mtd) +{ + /* + * NFC handles R/B internally.Therefore,this function + * always returns status as ready. + */ + return 1; +} + +static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + /* + * If HW ECC is enabled, we turn it on during init. There is + * no need to enable again here. + */ +} + +static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + /* + * 1-Bit errors are automatically corrected in HW. No need for + * additional correction. 2-Bit errors cannot be corrected by + * HW ECC, so we need to return failure + */ + u16 ecc_status = NFC_ECC_STATUS_RESULT; + + if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { + DEBUG(MTD_DEBUG_LEVEL0, + "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); + return -1; + } + + return 0; +} + +static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + /* + * Just return success. HW ECC does not read/write the NFC spare + * buffer. Only the FLASH spare area contains the calcuated ECC. + */ + return 0; +} + +/*! + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char mxc_nand_read_byte(struct mtd_info *mtd) +{ + u_char retVal = 0; + u16 col, rdWord; + volatile u16 *mainBuf = MAIN_AREA0; + volatile u16 *spareBuf = SPARE_AREA0; + + /* Check for status request */ + if (g_nandfc_info.bStatusRequest) { + return get_dev_status() & 0xFF; + } + + /* Get column for 16-bit access */ + col = g_nandfc_info.colAddr >> 1; + + /* If we are accessing the spare region */ + if (g_nandfc_info.bSpareOnly) { + rdWord = spareBuf[col]; + } else { + rdWord = mainBuf[col]; + } + + /* Pick upper/lower byte of word from RAM buffer */ + if (g_nandfc_info.colAddr & 0x1) { + retVal = (rdWord >> 8) & 0xFF; + } else { + retVal = rdWord & 0xFF; + } + + /* Update saved column address */ + g_nandfc_info.colAddr++; + + return retVal; +} + +/*! + * This function reads word from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 mxc_nand_read_word(struct mtd_info *mtd) +{ + u16 col; + u16 rdWord, retVal; + volatile u16 *p; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_read_word(col = %d)\n", g_nandfc_info.colAddr); + + col = g_nandfc_info.colAddr; + /* Adjust saved column address */ + if (col < mtd->writesize && g_nandfc_info.bSpareOnly) + col += mtd->writesize; + + if (col < mtd->writesize) + p = (MAIN_AREA0) + (col >> 1); + else + p = (SPARE_AREA0) + ((col - mtd->writesize) >> 1); + + if (col & 1) { + rdWord = *p; + retVal = (rdWord >> 8) & 0xff; + rdWord = *(p + 1); + retVal |= (rdWord << 8) & 0xff00; + + } else { + retVal = *p; + + } + + /* Update saved column address */ + g_nandfc_info.colAddr = col + 2; + + return retVal; +} + +/*! + * This function writes data of length \b len to buffer \b buf. The data to be + * written on NAND Flash is first copied to RAMbuffer. After the Data Input + * Operation by the NFC, the data is written to NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be written to NAND Flash + * @param len number of bytes to be written + */ +static void mxc_nand_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + int n; + int col; + int i = 0; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_write_buf(col = %d, len = %d)\n", g_nandfc_info.colAddr, + len); + + col = g_nandfc_info.colAddr; + + /* Adjust saved column address */ + if (col < mtd->writesize && g_nandfc_info.bSpareOnly) + col += mtd->writesize; + + n = mtd->writesize + mtd->oobsize - col; + n = min(len, n); + + DEBUG(MTD_DEBUG_LEVEL3, + "%s:%d: col = %d, n = %d\n", __FUNCTION__, __LINE__, col, n); + + while (n) { + volatile u32 *p; + if (col < mtd->writesize) + p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3)); + else + p = (volatile u32 *)((ulong) (SPARE_AREA0) - + mtd->writesize + (col & ~3)); + + DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __FUNCTION__, + __LINE__, p); + + if (((col | (int)&buf[i]) & 3) || n < 16) { + u32 data = 0; + + if (col & 3 || n < 4) + data = *p; + + switch (col & 3) { + case 0: + if (n) { + data = (data & 0xffffff00) | + (buf[i++] << 0); + n--; + col++; + } + case 1: + if (n) { + data = (data & 0xffff00ff) | + (buf[i++] << 8); + n--; + col++; + } + case 2: + if (n) { + data = (data & 0xff00ffff) | + (buf[i++] << 16); + n--; + col++; + } + case 3: + if (n) { + data = (data & 0x00ffffff) | + (buf[i++] << 24); + n--; + col++; + } + } + + *p = data; + } else { + int m = mtd->writesize - col; + + if (col >= mtd->writesize) + m += mtd->oobsize; + + m = min(n, m) & ~3; + + DEBUG(MTD_DEBUG_LEVEL3, + "%s:%d: n = %d, m = %d, i = %d, col = %d\n", + __FUNCTION__, __LINE__, n, m, i, col); + + memcpy((void *)(p), &buf[i], m); + col += m; + i += m; + n -= m; + } + } + /* Update saved column address */ + g_nandfc_info.colAddr = col; + +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be read from NAND Flash + * @param len number of bytes to be read + */ +static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len) +{ + + int n; + int col; + int i = 0; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_read_buf(col = %d, len = %d)\n", g_nandfc_info.colAddr, + len); + + col = g_nandfc_info.colAddr; + /* Adjust saved column address */ + if (col < mtd->writesize && g_nandfc_info.bSpareOnly) + col += mtd->writesize; + + n = mtd->writesize + mtd->oobsize - col; + n = min(len, n); + + while (n) { + volatile u32 *p; + + if (col < mtd->writesize) + p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3)); + else + p = (volatile u32 *)((ulong) (SPARE_AREA0) - + mtd->writesize + (col & ~3)); + + if (((col | (int)&buf[i]) & 3) || n < 16) { + u32 data; + + data = *p; + switch (col & 3) { + case 0: + if (n) { + buf[i++] = (u8) (data); + n--; + col++; + } + case 1: + if (n) { + buf[i++] = (u8) (data >> 8); + n--; + col++; + } + case 2: + if (n) { + buf[i++] = (u8) (data >> 16); + n--; + col++; + } + case 3: + if (n) { + buf[i++] = (u8) (data >> 24); + n--; + col++; + } + } + } else { + int m = mtd->writesize - col; + + if (col >= mtd->writesize) + m += mtd->oobsize; + + m = min(n, m) & ~3; + memcpy(&buf[i], (void *)(p), m); + col += m; + i += m; + n -= m; + } + } + /* Update saved column address */ + g_nandfc_info.colAddr = col; + +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be verified + * @param len length of the data to be verified + * + * @return -EFAULT if error else 0 + * + */ +static int +mxc_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) +{ + return -EFAULT; +} + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @param mtd MTD structure for the NAND Flash + * @param chip val indicating select or deselect + */ +static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) +{ +#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE + if (chip > 0) { + DEBUG(MTD_DEBUG_LEVEL0, + "ERROR: Illegal chip select (chip = %d)\n", chip); + return; + } + + if (chip == -1) { + NFC_CONFIG1 &= (~(NFC_CE)); + return; + } + + NFC_CONFIG1 |= NFC_CE; +#endif + + switch (chip) { + case -1: + /* Disable the NFC clock */ + clk_disable(nfc_clk); + break; + case 0: + /* Enable the NFC clock */ + clk_enable(nfc_clk); + break; + + default: + break; + } +} + +/*! + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * @param command command for NAND Flash + * @param column column offset for the page read + * @param page_addr page to be read from NAND Flash + */ +static void mxc_nand_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + bool useirq = true; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", + command, column, page_addr); + + /* + * Reset command state information + */ + g_nandfc_info.bStatusRequest = false; + + /* Reset column address to 0 */ + g_nandfc_info.colAddr = 0; + + /* + * Command pre-processing step + */ + switch (command) { + + case NAND_CMD_STATUS: + g_nandfc_info.bStatusRequest = true; + break; + + case NAND_CMD_READ0: + g_nandfc_info.colAddr = column; + g_nandfc_info.bSpareOnly = false; + useirq = false; + break; + + case NAND_CMD_READOOB: + g_nandfc_info.colAddr = column; + g_nandfc_info.bSpareOnly = true; + useirq = false; + if (is2k_Pagesize) + command = NAND_CMD_READ0; /* only READ0 is valid */ + break; + + case NAND_CMD_SEQIN: + if (column >= mtd->writesize) { + if (is2k_Pagesize) { + /** + * FIXME: before send SEQIN command for write OOB, + * We must read one page out. + * For K9F1GXX has no READ1 command to set current HW + * pointer to spare area, we must write the whole page including OOB together. + */ + /* call itself to read a page */ + mxc_nand_command(mtd, NAND_CMD_READ0, 0, + page_addr); + } + g_nandfc_info.colAddr = column - mtd->writesize; + g_nandfc_info.bSpareOnly = true; + /* Set program pointer to spare region */ + if (!is2k_Pagesize) + send_cmd(NAND_CMD_READOOB, false); + } else { + g_nandfc_info.bSpareOnly = false; + g_nandfc_info.colAddr = column; + /* Set program pointer to page start */ + if (!is2k_Pagesize) + send_cmd(NAND_CMD_READ0, false); + } + useirq = false; + break; + + case NAND_CMD_PAGEPROG: +#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + if (Ecc_disabled) { + /* Enable Ecc for page writes */ + NFC_CONFIG1 |= NFC_ECC_EN; + } +#endif + + send_prog_page(0, g_nandfc_info.bSpareOnly); + + if (is2k_Pagesize) { + /* data in 4 areas datas */ + send_prog_page(1, g_nandfc_info.bSpareOnly); + send_prog_page(2, g_nandfc_info.bSpareOnly); + send_prog_page(3, g_nandfc_info.bSpareOnly); + } + + break; + + case NAND_CMD_ERASE1: + useirq = false; + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(command, useirq); + + /* + * Write out column address, if necessary + */ + if (column != -1) { + /* + * MXC NANDFC can only perform full page+spare or + * spare-only read/write. When the upper layers + * layers perform a read/write buf operation, + * we will used the saved column adress to index into + * the full page. + */ + send_addr(0, page_addr == -1); + if (is2k_Pagesize) + /* another col addr cycle for 2k page */ + send_addr(0, false); + } + + /* + * Write out page address, if necessary + */ + if (page_addr != -1) { + send_addr((page_addr & 0xff), false); /* paddr_0 - p_addr_7 */ + + if (is2k_Pagesize) { + /* One more address cycle for higher density devices */ + if (mtd->size >= 0x10000000) { + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff, false); + send_addr((page_addr >> 16) & 0xff, true); + } else + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff, true); + } else { + /* One more address cycle for higher density devices */ + if (mtd->size >= 0x4000000) { + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff, false); + send_addr((page_addr >> 16) & 0xff, true); + } else + /* paddr_8 - paddr_15 */ + send_addr((page_addr >> 8) & 0xff, true); + } + } + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_RESET: + break; + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (is2k_Pagesize) { + /* send read confirm command */ + send_cmd(NAND_CMD_READSTART, true); + /* read for each AREA */ + send_read_page(0, g_nandfc_info.bSpareOnly); + send_read_page(1, g_nandfc_info.bSpareOnly); + send_read_page(2, g_nandfc_info.bSpareOnly); + send_read_page(3, g_nandfc_info.bSpareOnly); + } else { + send_read_page(0, g_nandfc_info.bSpareOnly); + } + break; + + case NAND_CMD_READID: + send_read_id(); + break; + + case NAND_CMD_PAGEPROG: +#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 + if (Ecc_disabled) { + /* Disble Ecc after page writes */ + NFC_CONFIG1 &= ~(NFC_ECC_EN); + } +#endif + break; + + case NAND_CMD_STATUS: + break; + + case NAND_CMD_ERASE2: + break; + } +} + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks. */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = NAND_BBT_SCAN2NDPAGE, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +/* Generic flash bbt decriptors +*/ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +static int mxc_nand_scan_bbt(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* Config before scanning */ + /* Do not rely on NFMS_BIT, set/clear NFMS bit based on mtd->writesize */ + if (mtd->writesize == 2048) { + NFMS |= (1 << NFMS_BIT); + is2k_Pagesize = 1; + } else { + if ((NFMS >> NFMS_BIT) & 0x1) { /* This case strangly happened on MXC91321 P1.2.2 */ + printk(KERN_INFO + "Oops... NFMS Bit set for 512B Page, resetting it. [RCSR: 0x%08x]\n", + NFMS); + NFMS &= ~(1 << NFMS_BIT); + } + is2k_Pagesize = 0; + } + + if (is2k_Pagesize) + this->ecc.layout = &nand_hw_eccoob_2k; + + /* jffs2 not write oob */ + mtd->flags &= ~MTD_OOB_WRITEABLE; + + /* use flash based bbt */ + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + + /* update flash based bbt */ + this->options |= NAND_USE_FLASH_BBT; + + if (!this->badblock_pattern) { + if (mtd->writesize == 2048) + this->badblock_pattern = &smallpage_memorybased; + else + this->badblock_pattern = (mtd->writesize > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + /* Build bad block table */ + return nand_scan_bbt(mtd, this->badblock_pattern); +} + +#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE +static void mxc_low_erase(struct mtd_info *mtd) +{ + + struct nand_chip *this = mtd->priv; + unsigned int page_addr, addr; + u_char status; + + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : mxc_low_erase:Erasing NAND\n"); + for (addr = 0; addr < this->chipsize; addr += mtd->erasesize) { + page_addr = addr / mtd->writesize; + mxc_nand_command(mtd, NAND_CMD_ERASE1, -1, page_addr); + mxc_nand_command(mtd, NAND_CMD_ERASE2, -1, -1); + mxc_nand_command(mtd, NAND_CMD_STATUS, -1, -1); + status = mxc_nand_read_byte(mtd); + if (status & NAND_STATUS_FAIL) { + printk(KERN_ERR + "ERASE FAILED(block = %d,status = 0x%x)\n", + addr / mtd->erasesize, status); + } + } + +} +#endif +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and + * remove functions + * + * @return The function always returns 0. + */ +static int __init mxcnd_probe(struct platform_device *pdev) +{ + struct nand_chip *this; + struct mtd_info *mtd; + struct flash_platform_data *flash = pdev->dev.platform_data; + int nr_parts = 0; + + int err = 0; + /* Allocate memory for MTD device structure and private data */ + mxc_nand_data = kzalloc(sizeof(struct mxc_mtd_s), GFP_KERNEL); + if (!mxc_nand_data) { + printk(KERN_ERR "%s: failed to allocate mtd_info\n", + __FUNCTION__); + err = -ENOMEM; + goto out; + } + memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info)); + + mxc_nand_data->dev = &pdev->dev; + /* structures must be linked */ + this = &mxc_nand_data->nand; + mtd = &mxc_nand_data->mtd; + mtd->priv = this; + mtd->owner = THIS_MODULE; + + /* 50 us command delay time */ + this->chip_delay = 5; + + this->priv = mxc_nand_data; + this->dev_ready = mxc_nand_dev_ready; + this->cmdfunc = mxc_nand_command; + this->select_chip = mxc_nand_select_chip; + this->read_byte = mxc_nand_read_byte; + this->read_word = mxc_nand_read_word; + this->write_buf = mxc_nand_write_buf; + this->read_buf = mxc_nand_read_buf; + this->verify_buf = mxc_nand_verify_buf; + this->scan_bbt = mxc_nand_scan_bbt; + + nfc_clk = clk_get(&pdev->dev, "nfc_clk"); + clk_enable(nfc_clk); + + NFC_CONFIG1 |= NFC_INT_MSK; + init_waitqueue_head(&irq_waitq); + err = request_irq(MXC_INT_NANDFC, mxc_nfc_irq, 0, "mxc_nd", NULL); + if (err) { + goto out_1; + } + + if (hardware_ecc) { + this->ecc.calculate = mxc_nand_calculate_ecc; + this->ecc.hwctl = mxc_nand_enable_hwecc; + this->ecc.correct = mxc_nand_correct_data; + this->ecc.mode = NAND_ECC_HW; + this->ecc.size = 512; + this->ecc.bytes = 3; + this->ecc.layout = &nand_hw_eccoob_8; + NFC_CONFIG1 |= NFC_ECC_EN; + } else { + this->ecc.mode = NAND_ECC_SOFT; + } + + /* Reset NAND */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* preset operation */ + /* Unlock the internal RAM Buffer */ + NFC_CONFIG = 0x2; + + /* Blocks to be unlocked */ + NFC_UNLOCKSTART_BLKADDR = 0x0; + NFC_UNLOCKEND_BLKADDR = 0x4000; + + /* Unlock Block Command for given address range */ + NFC_WRPROT = 0x4; + + /* NAND bus width determines access funtions used by upper layer */ + if (flash->width == 2) { + this->options |= NAND_BUSWIDTH_16; + this->ecc.layout = &nand_hw_eccoob_16; + } else { + this->options |= 0; + } + + is2k_Pagesize = 0; + + /* Scan to find existence of the device */ + if (nand_scan(mtd, 1)) { + DEBUG(MTD_DEBUG_LEVEL0, + "MXC_ND: Unable to find any NAND device.\n"); + err = -ENXIO; + goto out_1; + } + + /* Register the partitions */ +#ifdef CONFIG_MTD_PARTITIONS + nr_parts = + parse_mtd_partitions(mtd, part_probes, &mxc_nand_data->parts, 0); + if (nr_parts > 0) + add_mtd_partitions(mtd, mxc_nand_data->parts, nr_parts); + else if (flash->parts) + add_mtd_partitions(mtd, flash->parts, flash->nr_parts); + else +#endif + { + pr_info("Registering %s as whole device\n", mtd->name); + add_mtd_device(mtd); + } +#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE + /* Erase all the blocks of a NAND */ + mxc_low_erase(mtd); +#endif + + platform_set_drvdata(pdev, mtd); + return 0; + + out_1: + kfree(mxc_nand_data); + out: + return err; + +} + + /*! + * Dissociates the driver from the device. + * + * @param pdev the device structure used to give information on which + * + * @return The function always returns 0. + */ + +static int __exit mxcnd_remove(struct platform_device *pdev) +{ + struct mtd_info *mtd = platform_get_drvdata(pdev); + + clk_put(nfc_clk); + platform_set_drvdata(pdev, NULL); + + if (mxc_nand_data) { + nand_release(mtd); + free_irq(MXC_INT_NANDFC, NULL); + kfree(mxc_nand_data); + } + + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function is called to put the NAND in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device information structure + * + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure + */ + +static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mtd_info *info = platform_get_drvdata(pdev); + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n"); + if (info) + ret = info->suspend(info); + + /* Disable the NFC clock */ + clk_disable(nfc_clk); + + return ret; +} + +/*! + * This function is called to bring the NAND back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device information structure + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcnd_resume(struct platform_device *pdev) +{ + struct mtd_info *info = platform_get_drvdata(pdev); + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n"); + /* Enable the NFC clock */ + clk_enable(nfc_clk); + + if (info) { + info->resume(info); + } + + return ret; +} + +#else +#define mxcnd_suspend NULL +#define mxcnd_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcnd_driver = { + .driver = { + .name = "mxc_nand_flash", + }, + .probe = mxcnd_probe, + .remove = __exit_p(mxcnd_remove), + .suspend = mxcnd_suspend, + .resume = mxcnd_resume, +}; + +/*! + * Main initialization routine + * @return 0 if successful; non-zero otherwise + */ +static int __init mxc_nd_init(void) +{ + /* Register the device driver structure. */ + pr_info("MXC MTD nand Driver %s\n", DVR_VER); + if (platform_driver_register(&mxcnd_driver) != 0) { + printk(KERN_ERR "Driver register failed for mxcnd_driver\n"); + return -ENODEV; + } + return 0; +} + +/*! + * Clean up routine + */ +static void __exit mxc_nd_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&mxcnd_driver); +} + +module_init(mxc_nd_init); +module_exit(mxc_nd_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC NAND MTD driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/nand/mxc_nd.h b/drivers/mtd/nand/mxc_nd.h new file mode 100644 index 000000000000..a2a257c3897c --- /dev/null +++ b/drivers/mtd/nand/mxc_nd.h @@ -0,0 +1,112 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_nd.h + * + * @brief This file contains the NAND Flash Controller register information. + * + * + * @ingroup NAND_MTD + */ + +#ifndef __MXC_ND_H__ +#define __MXC_ND_H__ + +#include + +/* + * Addresses for NFC registers + */ +#define NFC_BUF_SIZE (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE00))) +#define NFC_BUF_ADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE04))) +#define NFC_FLASH_ADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE06))) +#define NFC_FLASH_CMD (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE08))) +#define NFC_CONFIG (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0A))) +#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0C))) +#define NFC_RSLTMAIN_AREA (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0E))) +#define NFC_RSLTSPARE_AREA (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE10))) +#define NFC_WRPROT (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE12))) +#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE14))) +#define NFC_UNLOCKEND_BLKADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE16))) +#define NFC_NF_WRPRST (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE18))) +#define NFC_CONFIG1 (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE1A))) +#define NFC_CONFIG2 (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE1C))) + +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x000) +#define MAIN_AREA1 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x200) +#define MAIN_AREA2 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x400) +#define MAIN_AREA3 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x600) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#define SPARE_AREA0 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x800) +#define SPARE_AREA1 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x810) +#define SPARE_AREA2 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x820) +#define SPARE_AREA3 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x830) + +/*! + * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command + * operation + */ +#define NFC_CMD 0x1 + +/*! + * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address + * operation + */ +#define NFC_ADDR 0x2 + +/*! + * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input + * operation + */ +#define NFC_INPUT 0x4 + +/*! + * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data Output + * operation + */ +#define NFC_OUTPUT 0x8 + +/*! + * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID + * operation + */ +#define NFC_ID 0x10 + +/*! + * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read Status + * operation + */ +#define NFC_STATUS 0x20 + +/*! + * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status + * operation + */ +#define NFC_INT 0x8000 + +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) + +#endif /* MXCND_H */ diff --git a/drivers/mtd/nand/mxc_nd2.c b/drivers/mtd/nand/mxc_nd2.c new file mode 100644 index 000000000000..6b362ce05bb3 --- /dev/null +++ b/drivers/mtd/nand/mxc_nd2.c @@ -0,0 +1,1756 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_nd2.h" +#include "nand_device_info.h" + +#define DVR_VER "3.0" + +/* Global address Variables */ +static void __iomem *nfc_axi_base, *nfc_ip_base; +static int nfc_irq; + +struct mxc_mtd_s { + struct mtd_info mtd; + struct nand_chip nand; + struct mtd_partition *parts; + struct device *dev; + int disable_bi_swap; /* disable bi swap */ + int ignore_bad_block; /* ignore bad block marker */ + void *saved_bbt; + int (*saved_block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); + int clk_active; +}; + +static struct mxc_mtd_s *mxc_nand_data; + +/* + * Define delay timeout value + */ +#define TROP_US_DELAY (1000 * 1000) + +struct nand_info { + bool bStatusRequest; + u16 colAddr; +}; + +static struct nand_info g_nandfc_info; + +#ifdef CONFIG_MTD_NAND_MXC_SWECC +static int hardware_ecc; +#else +static int hardware_ecc = 1; +#endif + +static u8 num_of_interleave = 1; + +static u8 *data_buf; +static u8 *oob_buf; + +static int g_page_mask; + +static struct clk *nfc_clk; + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_512 = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobavail = 4, + .oobfree = {{0, 4} } +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobavail = 4, + .oobfree = {{2, 4} } +}; + +static struct nand_ecclayout nand_hw_eccoob_4k = { + .eccbytes = 9, + .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, + .oobavail = 4, + .oobfree = {{2, 4} } +}; + +/*! + * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors + */ + +/*! + * @file mxc_nd2.c + * + * @brief This file contains the hardware specific layer for NAND Flash on + * MXC processor + * + * @ingroup NAND_MTD + */ + +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; +#endif + +static wait_queue_head_t irq_waitq; + +static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) +{ + /* Disable Interuupt */ + raw_write(raw_read(REG_NFC_INTRRUPT) | NFC_INT_MSK, REG_NFC_INTRRUPT); + wake_up(&irq_waitq); + + return IRQ_HANDLED; +} + +static void mxc_nand_bi_swap(struct mtd_info *mtd) +{ + u16 ma, sa, nma, nsa; + + if (!IS_LARGE_PAGE_NAND) + return; + + /* Disable bi swap if the user set disable_bi_swap at sys entry */ + if (mxc_nand_data->disable_bi_swap) + return; + + ma = __raw_readw(BAD_BLK_MARKER_MAIN); + sa = __raw_readw(BAD_BLK_MARKER_SP); + + nma = (ma & 0xFF00) | (sa >> 8); + nsa = (sa & 0x00FF) | (ma << 8); + + __raw_writew(nma, BAD_BLK_MARKER_MAIN); + __raw_writew(nsa, BAD_BLK_MARKER_SP); +} + +static void nfc_memcpy(void *dest, void *src, int len) +{ + u8 *d = dest; + u8 *s = src; + + while (len > 0) { + if (len >= 4) { + *(u32 *)d = *(u32 *)s; + d += 4; + s += 4; + len -= 4; + } else { + *(u16 *)d = *(u16 *)s; + len -= 2; + break; + } + } + + if (len) + BUG(); +} + +/* + * Functions to transfer data to/from spare erea. + */ +static void +copy_spare(struct mtd_info *mtd, void *pbuf, void *pspare, int len, bool bfrom) +{ + u16 i, j; + u16 m = mtd->oobsize; + u16 n = mtd->writesize >> 9; + u8 *d = (u8 *) pbuf; + u8 *s = (u8 *) pspare; + u16 t = SPARE_LEN; + + m /= num_of_interleave; + n /= num_of_interleave; + + j = (m / n >> 1) << 1; + + if (bfrom) { + for (i = 0; i < n - 1; i++) + nfc_memcpy(&d[i * j], &s[i * t], j); + + /* the last section */ + nfc_memcpy(&d[i * j], &s[i * t], len - i * j); + } else { + for (i = 0; i < n - 1; i++) + nfc_memcpy(&s[i * t], &d[i * j], j); + + /* the last section */ + nfc_memcpy(&s[i * t], &d[i * j], len - i * j); + } +} + +/*! + * This function polls the NFC to wait for the basic operation to complete by + * checking the INT bit of config2 register. + * + * @param maxRetries number of retry attempts (separated by 1 us) + * @param useirq True if IRQ should be used rather than polling + */ +static void wait_op_done(int maxRetries, bool useirq) +{ + if (useirq) { + if ((raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT) == 0) { + /* enable interrupt */ + raw_write(raw_read(REG_NFC_INTRRUPT) & ~NFC_INT_MSK, + REG_NFC_INTRRUPT); + if (!wait_event_timeout(irq_waitq, + (raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT), + msecs_to_jiffies(TROP_US_DELAY / 1000)) > 0) { + /* disable interrupt */ + raw_write(raw_read(REG_NFC_INTRRUPT) + | NFC_INT_MSK, REG_NFC_INTRRUPT); + + printk(KERN_WARNING "%s(%d): INT not set\n", + __func__, __LINE__); + return; + } + } + WRITE_NFC_IP_REG((raw_read(REG_NFC_OPS_STAT) & + ~NFC_OPS_STAT), REG_NFC_OPS_STAT); + } else { + while (1) { + maxRetries--; + if (raw_read(REG_NFC_OPS_STAT) & NFC_OPS_STAT) { + WRITE_NFC_IP_REG((raw_read(REG_NFC_OPS_STAT) & + ~NFC_OPS_STAT), + REG_NFC_OPS_STAT); + break; + } + udelay(1); + if (maxRetries <= 0) { + printk(KERN_WARNING "%s(%d): INT not set\n", + __func__, __LINE__); + break; + } + } + } +} + +static inline void send_atomic_cmd(u16 cmd, bool useirq) +{ + /* fill command */ + raw_write(cmd, REG_NFC_FLASH_CMD); + + /* send out command */ + raw_write(NFC_CMD, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, useirq); +} + +static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr); +static int mxc_check_ecc_status(struct mtd_info *mtd); + +#ifdef NFC_AUTO_MODE_ENABLE +/*! + * This function handle the interleave related work + * @param mtd mtd info + * @param cmd command + */ +static void auto_cmd_interleave(struct mtd_info *mtd, u16 cmd) +{ + u32 i, page_addr, ncs; + u32 j = num_of_interleave; + struct nand_chip *this = mtd->priv; + u32 addr_low = raw_read(NFC_FLASH_ADDR0); + u32 addr_high = raw_read(NFC_FLASH_ADDR8); + u8 *dbuf = data_buf; + u8 *obuf = oob_buf; + u32 dlen = mtd->writesize / j; + u32 olen = mtd->oobsize / j; + + /* adjust the addr value + * since ADD_OP mode is 01 + */ + if (cmd == NAND_CMD_ERASE2) + page_addr = addr_low; + else + page_addr = addr_low >> 16 | addr_high << 16; + + ncs = NFC_GET_NFC_ACTIVE_CS(); + + if (j > 1) { + page_addr *= j; + } else { + page_addr *= this->numchips; + page_addr += ncs; + } + + switch (cmd) { + case NAND_CMD_PAGEPROG: + for (i = 0; i < j; i++) { + /* reset addr cycle */ + mxc_do_addr_cycle(mtd, 0, page_addr++); + + /* data transfer */ + memcpy(MAIN_AREA0, dbuf, dlen); + copy_spare(mtd, obuf, SPARE_AREA0, olen, false); + mxc_nand_bi_swap(mtd); + + /* update the value */ + dbuf += dlen; + obuf += olen; + + NFC_SET_RBA(0); + raw_write(NFC_AUTO_PROG, REG_NFC_OPS); + + /* wait auto_prog_done bit set */ + while (!(raw_read(REG_NFC_OPS_STAT) & NFC_OP_DONE)) + ; + } + + wait_op_done(TROP_US_DELAY, true); + while (!(raw_read(REG_NFC_OPS_STAT) & NFC_RB)); + + break; + case NAND_CMD_READSTART: + for (i = 0; i < j; i++) { + /* reset addr cycle */ + mxc_do_addr_cycle(mtd, 0, page_addr++); + + NFC_SET_RBA(0); + raw_write(NFC_AUTO_READ, REG_NFC_OPS); + wait_op_done(TROP_US_DELAY, true); + + /* check ecc error */ + mxc_check_ecc_status(mtd); + + /* data transfer */ + mxc_nand_bi_swap(mtd); + memcpy(dbuf, MAIN_AREA0, dlen); + copy_spare(mtd, obuf, SPARE_AREA0, olen, true); + + /* update the value */ + dbuf += dlen; + obuf += olen; + } + break; + case NAND_CMD_ERASE2: + for (i = 0; i < j; i++) { + mxc_do_addr_cycle(mtd, -1, page_addr++); + raw_write(NFC_AUTO_ERASE, REG_NFC_OPS); + wait_op_done(TROP_US_DELAY, true); + } + break; + case NAND_CMD_RESET: + for (i = 0; i < j; i++) { + if (j > 1) + NFC_SET_NFC_ACTIVE_CS(i); + send_atomic_cmd(cmd, false); + } + break; + default: + break; + } +} +#endif + +static void send_addr(u16 addr, bool useirq); + +/*! + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @param cmd command for NAND Flash + * @param useirq True if IRQ should be used rather than polling + */ +static void send_cmd(struct mtd_info *mtd, u16 cmd, bool useirq) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd, useirq); + +#ifdef NFC_AUTO_MODE_ENABLE + switch (cmd) { + case NAND_CMD_READ0: + case NAND_CMD_READOOB: + raw_write(NAND_CMD_READ0, REG_NFC_FLASH_CMD); + break; + case NAND_CMD_SEQIN: + case NAND_CMD_ERASE1: + raw_write(cmd, REG_NFC_FLASH_CMD); + break; + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE2: + case NAND_CMD_READSTART: + raw_write(raw_read(REG_NFC_FLASH_CMD) | cmd << NFC_CMD_1_SHIFT, + REG_NFC_FLASH_CMD); + auto_cmd_interleave(mtd, cmd); + break; + case NAND_CMD_READID: + send_atomic_cmd(cmd, useirq); + send_addr(0, false); + break; + case NAND_CMD_RESET: + auto_cmd_interleave(mtd, cmd); + break; + case NAND_CMD_STATUS: + send_atomic_cmd(cmd, useirq); + break; + default: + break; + } +#else + send_atomic_cmd(cmd, useirq); +#endif +} + +/*! + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @param addr address to be written to NFC. + * @param useirq True if IRQ should be used rather than polling + */ +static void send_addr(u16 addr, bool useirq) +{ + DEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr, useirq); + + /* fill address */ + raw_write((addr << NFC_FLASH_ADDR_SHIFT), REG_NFC_FLASH_ADDR); + + /* send out address */ + raw_write(NFC_ADDR, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, useirq); +} + +/*! + * This function requests the NFC to initate the transfer + * of data currently in the NFC RAM buffer to the NAND device. + * + * @param buf_id Specify Internal RAM Buffer number + */ +static void send_prog_page(u8 buf_id) +{ +#ifndef NFC_AUTO_MODE_ENABLE + DEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__); + + /* set ram buffer id */ + NFC_SET_RBA(buf_id); + + /* transfer data from NFC ram to nand */ + raw_write(NFC_INPUT, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, true); +#endif +} + +/*! + * This function requests the NFC to initated the transfer + * of data from the NAND device into in the NFC ram buffer. + * + * @param buf_id Specify Internal RAM Buffer number + */ +static void send_read_page(u8 buf_id) +{ +#ifndef NFC_AUTO_MODE_ENABLE + DEBUG(MTD_DEBUG_LEVEL3, "%s(%d)\n", __FUNCTION__, buf_id); + + /* set ram buffer id */ + NFC_SET_RBA(buf_id); + + /* transfer data from nand to NFC ram */ + raw_write(NFC_OUTPUT, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, true); +#endif +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + /* Set RBA bits for BUFFER0 */ + NFC_SET_RBA(0); + + /* Read ID into main buffer */ + raw_write(NFC_ID, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, false); + +} + +#ifdef NFC_AUTO_MODE_ENABLE +static inline void read_dev_status(u16 *status) +{ + u32 mask = 0xFF << 16; + + /* use atomic mode to read status instead + of using auto mode,auto-mode has issues + and the status is not correct. + */ + raw_write(NFC_STATUS, REG_NFC_OPS); + + wait_op_done(TROP_US_DELAY, true); + + *status = (raw_read(NFC_CONFIG1) & mask) >> 16; + +} +#endif + +/*! + * This function requests the NFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ +#ifdef NFC_AUTO_MODE_ENABLE + int i; + u16 status = 0; + int cs = NFC_GET_NFC_ACTIVE_CS(); + + for (i = 0; i < num_of_interleave; i++) { + + /* set ative cs */ + NFC_SET_NFC_ACTIVE_CS(i); + + /* FIXME, NFC Auto erase may have + * problem, have to pollingit until + * the nand get idle, otherwise + * it may get error + */ + read_dev_status(&status); + if (status & NAND_STATUS_FAIL) + break; + } + + /* Restore active CS */ + NFC_SET_NFC_ACTIVE_CS(cs); + + return status; +#else + volatile u16 *mainBuf = MAIN_AREA1; + u8 val = 1; + u16 ret; + + /* Set ram buffer id */ + NFC_SET_RBA(val); + + /* Read status into main buffer */ + raw_write(NFC_STATUS, REG_NFC_OPS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY, true); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + ret = *mainBuf; + + return ret; +#endif +} + +static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), REG_NFC_ECC_EN); + return; +} + +/* + * Function to record the ECC corrected/uncorrected errors resulted + * after a page read. This NFC detects and corrects upto to 4 symbols + * of 9-bits each. + */ +static int mxc_check_ecc_status(struct mtd_info *mtd) +{ + u32 ecc_stat, err; + int no_subpages = 1; + int ret = 0; + u8 ecc_bit_mask = 0xf; + + no_subpages = mtd->writesize >> 9; + + no_subpages /= num_of_interleave; + + ecc_stat = GET_NFC_ECC_STATUS(); + do { + err = ecc_stat & ecc_bit_mask; + if (err == ecc_bit_mask) { + mtd->ecc_stats.failed++; + printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); + return -1; + } else { + ret += err; + } + ecc_stat >>= 4; + } while (--no_subpages); + + pr_debug("Correctable ECC Error(%d)\n", ret); + + return ret; +} + +/* + * Function to correct the detected errors. This NFC corrects all the errors + * detected. So this function just return 0. + */ +static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + return 0; +} + +/* + * Function to calculate the ECC for the data to be stored in the Nand device. + * This NFC has a hardware RS(511,503) ECC engine together with the RS ECC + * CONTROL blocks are responsible for detection and correction of up to + * 8 symbols of 9 bits each in 528 byte page. + * So this function is just return 0. + */ + +static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + return 0; +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be read from NAND Flash + * @param len number of bytes to be read + */ +static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len) +{ + u16 col = g_nandfc_info.colAddr; + + if (mtd->writesize) { + + int j = mtd->writesize - col; + int n = mtd->oobsize + j; + + n = min(n, len); + + if (j > 0) { + if (n > j) { + memcpy(buf, &data_buf[col], j); + memcpy(buf + j, &oob_buf[0], n - j); + } else { + memcpy(buf, &data_buf[col], n); + } + } else { + col -= mtd->writesize; + memcpy(buf, &oob_buf[col], len); + } + + /* update */ + g_nandfc_info.colAddr += n; + + } else { + /* At flash identify phase, + * mtd->writesize has not been + * set correctly, it should + * be zero.And len will less 2 + */ + memcpy(buf, &data_buf[col], len); + + /* update */ + g_nandfc_info.colAddr += len; + } + +} + +/*! + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static uint8_t mxc_nand_read_byte(struct mtd_info *mtd) +{ + uint8_t ret; + + /* Check for status request */ + if (g_nandfc_info.bStatusRequest) { + return get_dev_status() & 0xFF; + } + + mxc_nand_read_buf(mtd, &ret, 1); + + return ret; +} + +/*! + * This function reads word from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 mxc_nand_read_word(struct mtd_info *mtd) +{ + u16 ret; + + mxc_nand_read_buf(mtd, (uint8_t *) &ret, sizeof(u16)); + + return ret; +} + +/*! + * This function reads byte from the NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char mxc_nand_read_byte16(struct mtd_info *mtd) +{ + /* Check for status request */ + if (g_nandfc_info.bStatusRequest) { + return get_dev_status() & 0xFF; + } + + return mxc_nand_read_word(mtd) & 0xFF; +} + +/*! + * This function writes data of length \b len from buffer \b buf to the NAND + * internal RAM buffer's MAIN area 0. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be written to NAND Flash + * @param len number of bytes to be written + */ +static void mxc_nand_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + u16 col = g_nandfc_info.colAddr; + int j = mtd->writesize - col; + int n = mtd->oobsize + j; + + n = min(n, len); + + if (j > 0) { + if (n > j) { + memcpy(&data_buf[col], buf, j); + memcpy(&oob_buf[0], buf + j, n - j); + } else { + memcpy(&data_buf[col], buf, n); + } + } else { + col -= mtd->writesize; + memcpy(&oob_buf[col], buf, len); + } + + /* update */ + g_nandfc_info.colAddr += n; +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @param mtd MTD structure for the NAND Flash + * @param buf data to be verified + * @param len length of the data to be verified + * + * @return -EFAULT if error else 0 + * + */ +static int mxc_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, + int len) +{ + u_char *s = data_buf; + + const u_char *p = buf; + + for (; len > 0; len--) { + if (*p++ != *s++) + return -EFAULT; + } + + return 0; +} + +/*! + * This function will enable NFC clock + * + */ +static inline void mxc_nand_clk_enable(void) +{ + if (!mxc_nand_data->clk_active) { + clk_enable(nfc_clk); + mxc_nand_data->clk_active = 1; + } +} + +/*! + * This function will disable NFC clock + * + */ +static inline void mxc_nand_clk_disable(void) +{ + if (mxc_nand_data->clk_active) { + clk_disable(nfc_clk); + mxc_nand_data->clk_active = 0; + } +} + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @param mtd MTD structure for the NAND Flash + * @param chip val indicating select or deselect + */ +static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) +{ + + switch (chip) { + case -1: + /* Disable the NFC clock */ + mxc_nand_clk_disable(); + + break; + case 0 ... NFC_GET_MAXCHIP_SP(): + /* Enable the NFC clock */ + mxc_nand_clk_enable(); + NFC_SET_NFC_ACTIVE_CS(chip); + + break; + + default: + break; + } +} + +/* + * Function to perform the address cycles. + */ +static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) +{ +#ifdef NFC_AUTO_MODE_ENABLE + + if (page_addr != -1 && column != -1) { + u32 mask = 0xFFFF; + /* the column address */ + raw_write(column & mask, NFC_FLASH_ADDR0); + raw_write((raw_read(NFC_FLASH_ADDR0) | + ((page_addr & mask) << 16)), NFC_FLASH_ADDR0); + /* the row address */ + raw_write(((raw_read(NFC_FLASH_ADDR8) & (mask << 16)) | + ((page_addr & (mask << 16)) >> 16)), + NFC_FLASH_ADDR8); + } else if (page_addr != -1) { + raw_write(page_addr, NFC_FLASH_ADDR0); + raw_write(0, NFC_FLASH_ADDR8); + } + + DEBUG(MTD_DEBUG_LEVEL3, + "AutoMode:the ADDR REGS value is (0x%x, 0x%x)\n", + raw_read(NFC_FLASH_ADDR0), raw_read(NFC_FLASH_ADDR8)); +#else + + u32 page_mask = g_page_mask; + + if (column != -1) { + send_addr(column & 0xFF, true); + if (IS_2K_PAGE_NAND) { + /* another col addr cycle for 2k page */ + send_addr((column >> 8) & 0xF, true); + } else if (IS_4K_PAGE_NAND) { + /* another col addr cycle for 4k page */ + send_addr((column >> 8) & 0x1F, true); + } + } + if (page_addr != -1) { + do { + send_addr((page_addr & 0xff), true); + page_mask >>= 8; + page_addr >>= 8; + } while (page_mask != 0); + } +#endif +} + +/*! + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * + * @param mtd MTD structure for the NAND Flash + * @param command command for NAND Flash + * @param column column offset for the page read + * @param page_addr page to be read from NAND Flash + */ +static void mxc_nand_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + bool useirq = true; + + DEBUG(MTD_DEBUG_LEVEL3, + "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", + command, column, page_addr); + /* + * Reset command state information + */ + g_nandfc_info.bStatusRequest = false; + + /* + * Command pre-processing step + */ + switch (command) { + case NAND_CMD_STATUS: + g_nandfc_info.colAddr = 0; + g_nandfc_info.bStatusRequest = true; + break; + + case NAND_CMD_READ0: + g_nandfc_info.colAddr = column; + break; + + case NAND_CMD_READOOB: + g_nandfc_info.colAddr = column; + command = NAND_CMD_READ0; + break; + + case NAND_CMD_SEQIN: + if (column != 0) { + + /* FIXME: before send SEQIN command for + * partial write,We need read one page out. + * FSL NFC does not support partial write + * It alway send out 512+ecc+512+ecc ... + * for large page nand flash. But for small + * page nand flash, it did support SPARE + * ONLY operation. But to make driver + * simple. We take the same as large page,read + * whole page out and update. As for MLC nand + * NOP(num of operation) = 1. Partial written + * on one programed page is not allowed! We + * can't limit it on the driver, it need the + * upper layer applicaiton take care it + */ + + mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); + } + + g_nandfc_info.colAddr = column; + column = 0; + + break; + + case NAND_CMD_PAGEPROG: +#ifndef NFC_AUTO_MODE_ENABLE + /* FIXME:the NFC interal buffer + * access has some limitation, it + * does not allow byte access. To + * make the code simple and ease use + * not every time check the address + * alignment.Use the temp buffer + * to accomadate the data.since We + * know data_buf will be at leat 4 + * byte alignment, so we can use + * memcpy safely + */ + nfc_memcpy(MAIN_AREA0, data_buf, mtd->writesize); + copy_spare(mtd, oob_buf, SPARE_AREA0, mtd->oobsize, false); + mxc_nand_bi_swap(mtd); +#endif + + if (IS_LARGE_PAGE_NAND) + PROG_PAGE(); + else + send_prog_page(0); + + break; + + case NAND_CMD_ERASE1: + break; + case NAND_CMD_ERASE2: + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(mtd, command, useirq); + + mxc_do_addr_cycle(mtd, column, page_addr); + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (IS_LARGE_PAGE_NAND) { + /* send read confirm command */ + send_cmd(mtd, NAND_CMD_READSTART, true); + /* read for each AREA */ + READ_PAGE(); + } else { + send_read_page(0); + } + +#ifndef NFC_AUTO_MODE_ENABLE + /* FIXME, the NFC interal buffer + * access has some limitation, it + * does not allow byte access. To + * make the code simple and ease use + * not every time check the address + * alignment.Use the temp buffer + * to accomadate the data.since We + * know data_buf will be at leat 4 + * byte alignment, so we can use + * memcpy safely + */ + mxc_nand_bi_swap(mtd); + nfc_memcpy(data_buf, MAIN_AREA0, mtd->writesize); + copy_spare(mtd, oob_buf, SPARE_AREA0, mtd->oobsize, true); +#endif + + break; + + case NAND_CMD_READID: + send_read_id(); + g_nandfc_info.colAddr = column; + nfc_memcpy(data_buf, MAIN_AREA0, 2048); + + break; + } +} + +static int mxc_nand_read_oob(struct mtd_info *mtd, + struct nand_chip *chip, int page, int sndcmd) +{ + if (sndcmd) { + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); + sndcmd = 0; + } + + memcpy(chip->oob_poi, oob_buf, mtd->oobsize); + + return sndcmd; +} + +static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + +#ifndef NFC_AUTO_MODE_ENABLE + mxc_check_ecc_status(mtd); +#endif + + memcpy(buf, data_buf, mtd->writesize); + memcpy(chip->oob_poi, oob_buf, mtd->oobsize); + + return 0; +} + +static void mxc_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + memcpy(data_buf, buf, mtd->writesize); + memcpy(oob_buf, chip->oob_poi, mtd->oobsize); + +} + +/*! + * mxc_nand_block_bad - Claims all blocks are good + * In principle, this function is *only* called when the NAND Flash MTD system + * isn't allowed to keep an in-memory bad block table, so it is forced to ask + * the driver for bad block information. + * + * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so + * this function is *only* called when we take it away. + * + * We take away the in-memory BBT when the user sets the "ignorebad" parameter, + * which indicates that all blocks should be reported good. + * + * Thus, this function is only called when we want *all* blocks to look good, + * so it *always* return success. + * + * @mtd: Ignored. + * @ofs: Ignored. + * @getchip: Ignored. + */ +static int mxc_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + return 0; +} + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks. */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = NAND_BBT_SCAN2NDPAGE, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +/* Generic flash bbt decriptors +*/ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +static int mxc_nand_scan_bbt(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + g_page_mask = this->pagemask; + + if (IS_2K_PAGE_NAND) { + NFC_SET_NFMS(1 << NFMS_NF_PG_SZ); + this->ecc.layout = &nand_hw_eccoob_2k; + } else if (IS_4K_PAGE_NAND) { + NFC_SET_NFMS(1 << NFMS_NF_PG_SZ); + this->ecc.layout = &nand_hw_eccoob_4k; + } else { + this->ecc.layout = &nand_hw_eccoob_512; + } + + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = this->ecc.layout; + + /* jffs2 not write oob */ + mtd->flags &= ~MTD_OOB_WRITEABLE; + + /* fix up the offset */ + largepage_memorybased.offs = BAD_BLK_MARKER_OOB_OFFS; + + /* keep compatible for bbt table with old soc */ + if (cpu_is_mx53()) { + bbt_mirror_descr.offs = BAD_BLK_MARKER_OOB_OFFS + 2; + bbt_main_descr.offs = BAD_BLK_MARKER_OOB_OFFS + 2; + bbt_mirror_descr.veroffs = bbt_mirror_descr.offs + 4; + bbt_main_descr.veroffs = bbt_main_descr.offs + 4; + } + + /* use flash based bbt */ + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + + /* update flash based bbt */ + this->options |= NAND_USE_FLASH_BBT; + + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->writesize > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + + /* Build bad block table */ + return nand_scan_bbt(mtd, this->badblock_pattern); +} + +static int mxc_get_resources(struct platform_device *pdev) +{ + struct resource *r; + int error = 0; + +#define MXC_NFC_NO_IP_REG \ + (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx32() || cpu_is_mx35()) + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + error = -ENXIO; + goto out_0; + } + nfc_axi_base = ioremap(r->start, resource_size(r)); + + if (!MXC_NFC_NO_IP_REG) { + r = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!r) { + error = -ENXIO; + goto out_1; + } + } + nfc_ip_base = ioremap(r->start, resource_size(r)); + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!r) { + error = -ENXIO; + goto out_2; + } + nfc_irq = r->start; + + init_waitqueue_head(&irq_waitq); + error = request_irq(nfc_irq, mxc_nfc_irq, 0, "mxc_nd", NULL); + if (error) + goto out_3; + + return 0; +out_3: +out_2: + if (!MXC_NFC_NO_IP_REG) + iounmap(nfc_ip_base); +out_1: + iounmap(nfc_axi_base); +out_0: + return error; +} + +static void mxc_nfc_init(void) +{ + /* Disable interrupt */ + raw_write((raw_read(REG_NFC_INTRRUPT) | NFC_INT_MSK), REG_NFC_INTRRUPT); + + /* disable spare enable */ + raw_write(raw_read(REG_NFC_SP_EN) & ~NFC_SP_EN, REG_NFC_SP_EN); + + /* Unlock the internal RAM Buffer */ + raw_write(NFC_SET_BLS(NFC_BLS_UNLCOKED), REG_NFC_BLS); + + if (!(cpu_is_mx53())) { + /* Blocks to be unlocked */ + UNLOCK_ADDR(0x0, 0xFFFF); + + /* Unlock Block Command for given address range */ + raw_write(NFC_SET_WPC(NFC_WPC_UNLOCK), REG_NFC_WPC); + } + + /* Enable symetric mode by default except mx37TO1.0 */ + if (!(cpu_is_mx37_rev(CHIP_REV_1_0) == 1)) + raw_write(raw_read(REG_NFC_ONE_CYCLE) | + NFC_ONE_CYCLE, REG_NFC_ONE_CYCLE); +} + +static int mxc_alloc_buf(void) +{ + int err = 0; + + data_buf = kzalloc(NAND_MAX_PAGESIZE, GFP_KERNEL); + if (!data_buf) { + printk(KERN_ERR "%s: failed to allocate data_buf\n", __func__); + err = -ENOMEM; + goto out; + } + oob_buf = kzalloc(NAND_MAX_OOBSIZE, GFP_KERNEL); + if (!oob_buf) { + printk(KERN_ERR "%s: failed to allocate oob_buf\n", __func__); + err = -ENOMEM; + goto out; + } + + out: + return err; +} + +static void mxc_free_buf(void) +{ + kfree(data_buf); + kfree(oob_buf); +} + +int nand_scan_mid(struct mtd_info *mtd) +{ + int i; + uint8_t id_bytes[NAND_DEVICE_ID_BYTE_COUNT]; + struct nand_chip *this = mtd->priv; + struct nand_device_info *dev_info; + + if (!IS_LARGE_PAGE_NAND) + return 0; + + /* Read ID bytes from the first NAND Flash chip. */ + this->select_chip(mtd, 0); + + this->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + + for (i = 0; i < NAND_DEVICE_ID_BYTE_COUNT; i++) + id_bytes[i] = this->read_byte(mtd); + + /* Get information about this device, based on the ID bytes. */ + dev_info = nand_device_get_info(id_bytes); + + /* Check if we understand this device. */ + if (!dev_info) { + printk(KERN_ERR "Unrecognized NAND Flash device.\n"); + return !0; + } + + /* Correct mtd setting */ + this->chipsize = dev_info->chip_size_in_bytes; + mtd->size = dev_info->chip_size_in_bytes * this->numchips; + mtd->writesize = dev_info->page_total_size_in_bytes & ~0x3ff; + mtd->oobsize = dev_info->page_total_size_in_bytes & 0x3ff; + mtd->erasesize = dev_info->block_size_in_pages * mtd->writesize; + + /* Calculate the address shift from the page size */ + this->page_shift = ffs(mtd->writesize) - 1; + /* Convert chipsize to number of pages per chip -1. */ + this->pagemask = (this->chipsize >> this->page_shift) - 1; + + this->bbt_erase_shift = this->phys_erase_shift = + ffs(mtd->erasesize) - 1; + this->chip_shift = ffs(this->chipsize) - 1; + + return 0; +} + +/*! + * show_device_disable_bi_swap() + * Shows the value of the 'disable_bi_swap' flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_disable_bi_swap(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", mxc_nand_data->disable_bi_swap); +} + +/*! + * store_device_disable_bi_swap() + * Sets the value of the 'disable_bi_swap' flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_disable_bi_swap(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + const char *p = buf; + unsigned long v; + + /* Try to make sense of what arrived from user space. */ + + if (strict_strtoul(p, 0, &v) < 0) + return size; + + if (v > 0) + v = 1; + mxc_nand_data->disable_bi_swap = v; + return size; + +} + +static DEVICE_ATTR(disable_bi_swap, 0644, + show_device_disable_bi_swap, store_device_disable_bi_swap); + +/*! + * show_device_ignorebad() + * Shows the value of the 'ignore_bad_block' flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer that will receive a representation of the attribute. + */ +static ssize_t show_device_ignorebad(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", mxc_nand_data->ignore_bad_block); +} + +/*! + * store_device_ignorebad() + * Sets the value of the 'ignore_bad_block' flag. + * + * @dev: The device of interest. + * @attr: The attribute of interest. + * @buf: A buffer containing a new attribute value. + * @size: The size of the buffer. + */ +static ssize_t store_device_ignorebad(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + const char *p = buf; + unsigned long v; + + /* Try to make sense of what arrived from user space. */ + + if (strict_strtoul(p, 0, &v) < 0) + return size; + + if (v > 0) + v = 1; + + /* Only do something if the value is changing. */ + if (v != mxc_nand_data->ignore_bad_block) { + if (v) { + /* + * If control arrives here, we want to begin ignoring + * bad block marks. Reach into the NAND Flash MTD data + * structures and set the in-memory BBT pointer to NULL. + * This will cause the NAND Flash MTD code to believe + * that it never created a BBT and force it to call our + * block_bad function. + */ + mxc_nand_data->saved_bbt = mxc_nand_data->nand.bbt; + mxc_nand_data->nand.bbt = 0; + mxc_nand_data->saved_block_bad = + mxc_nand_data->nand.block_bad; + mxc_nand_data->nand.block_bad = + mxc_nand_block_bad; + } else { + /* + * If control arrives here, we want to stop ignoring + * bad block marks. Restore the NAND Flash MTD's pointer + * to its in-memory BBT. + */ + mxc_nand_data->nand.bbt = mxc_nand_data->saved_bbt; + mxc_nand_data->nand.block_bad = + mxc_nand_data->saved_block_bad; + } + mxc_nand_data->ignore_bad_block = v; + } + + return size; + +} + +static DEVICE_ATTR(ignorebad, 0644, + show_device_ignorebad, store_device_ignorebad); + + +static struct device_attribute *device_attributes[] = { + &dev_attr_disable_bi_swap, + &dev_attr_ignorebad, +}; +/*! + * manage_sysfs_files() - Creates/removes sysfs files for this device. + * + * @create: create/remove the sys entry. + */ +static void manage_sysfs_files(int create) +{ + struct device *dev = mxc_nand_data->dev; + int error; + unsigned int i; + struct device_attribute **attr; + + for (i = 0, attr = device_attributes; + i < ARRAY_SIZE(device_attributes); i++, attr++) { + + if (create) { + error = device_create_file(dev, *attr); + if (error) { + while (--attr >= device_attributes) + device_remove_file(dev, *attr); + return; + } + } else { + device_remove_file(dev, *attr); + } + } + +} + + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and + * remove functions + * + * @return The function always returns 0. + */ +static int __devinit mxcnd_probe(struct platform_device *pdev) +{ + struct nand_chip *this; + struct mtd_info *mtd; + struct flash_platform_data *flash = pdev->dev.platform_data; + int nr_parts = 0, err = 0; + + /* get the resource */ + err = mxc_get_resources(pdev); + if (err) + goto out; + + /* init the nfc */ + mxc_nfc_init(); + + /* init data buf */ + if (mxc_alloc_buf()) + goto out; + + /* Allocate memory for MTD device structure and private data */ + mxc_nand_data = kzalloc(sizeof(struct mxc_mtd_s), GFP_KERNEL); + if (!mxc_nand_data) { + printk(KERN_ERR "%s: failed to allocate mtd_info\n", + __FUNCTION__); + err = -ENOMEM; + goto out; + } + + memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info)); + + mxc_nand_data->dev = &pdev->dev; + /* structures must be linked */ + this = &mxc_nand_data->nand; + mtd = &mxc_nand_data->mtd; + mtd->priv = this; + mtd->owner = THIS_MODULE; + + this->priv = mxc_nand_data; + this->cmdfunc = mxc_nand_command; + this->select_chip = mxc_nand_select_chip; + this->read_byte = mxc_nand_read_byte; + this->read_word = mxc_nand_read_word; + this->write_buf = mxc_nand_write_buf; + this->read_buf = mxc_nand_read_buf; + this->verify_buf = mxc_nand_verify_buf; + this->scan_bbt = mxc_nand_scan_bbt; + + /* NAND bus width determines access funtions used by upper layer */ + if (flash->width == 2) { + this->read_byte = mxc_nand_read_byte16; + this->options |= NAND_BUSWIDTH_16; + NFC_SET_NFMS(1 << NFMS_NF_DWIDTH); + } else { + NFC_SET_NFMS(0); + } + + nfc_clk = clk_get(&pdev->dev, "nfc_clk"); + clk_enable(nfc_clk); + mxc_nand_data->clk_active = 1; + + if (hardware_ecc) { + this->ecc.read_page = mxc_nand_read_page; + this->ecc.write_page = mxc_nand_write_page; + this->ecc.read_oob = mxc_nand_read_oob; + this->ecc.layout = &nand_hw_eccoob_512; + this->ecc.calculate = mxc_nand_calculate_ecc; + this->ecc.hwctl = mxc_nand_enable_hwecc; + this->ecc.correct = mxc_nand_correct_data; + this->ecc.mode = NAND_ECC_HW; + this->ecc.size = 512; + this->ecc.bytes = 9; + raw_write((raw_read(REG_NFC_ECC_EN) | NFC_ECC_EN), + REG_NFC_ECC_EN); + } else { + this->ecc.mode = NAND_ECC_SOFT; + raw_write((raw_read(REG_NFC_ECC_EN) & ~NFC_ECC_EN), + REG_NFC_ECC_EN); + } + + /* config the gpio */ + if (flash->init) + flash->init(); + + /* Reset NAND */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Scan to find existence of the device */ + if (nand_scan_ident(mtd, NFC_GET_MAXCHIP_SP(), NULL) + || nand_scan_mid(mtd) + || nand_scan_tail(mtd)) { + DEBUG(MTD_DEBUG_LEVEL0, + "MXC_ND2: Unable to find any NAND device.\n"); + err = -ENXIO; + goto out_1; + } + + /* Register the partitions */ +#ifdef CONFIG_MTD_PARTITIONS + nr_parts = + parse_mtd_partitions(mtd, part_probes, &mxc_nand_data->parts, 0); + if (nr_parts > 0) + add_mtd_partitions(mtd, mxc_nand_data->parts, nr_parts); + else if (flash->parts) + add_mtd_partitions(mtd, flash->parts, flash->nr_parts); + else +#endif + { + pr_info("Registering %s as whole device\n", mtd->name); + add_mtd_device(mtd); + } + + /* Create sysfs entries for this device. */ + manage_sysfs_files(true); + + platform_set_drvdata(pdev, mtd); + + return 0; + + out_1: + kfree(mxc_nand_data); + out: + return err; + +} + + /*! + * Dissociates the driver from the device. + * + * @param pdev the device structure used to give information on which + * + * @return The function always returns 0. + */ + +static int __exit mxcnd_remove(struct platform_device *pdev) +{ + struct mtd_info *mtd = platform_get_drvdata(pdev); + struct flash_platform_data *flash = pdev->dev.platform_data; + + if (flash->exit) + flash->exit(); + + manage_sysfs_files(false); + mxc_free_buf(); + + mxc_nand_clk_disable(); + clk_put(nfc_clk); + platform_set_drvdata(pdev, NULL); + + if (mxc_nand_data) { + nand_release(mtd); + free_irq(nfc_irq, NULL); + kfree(mxc_nand_data); + } + + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function is called to put the NAND in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device information structure + * + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure + */ + +static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state) +{ + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND2 : NAND suspend\n"); + + /* Disable the NFC clock */ + mxc_nand_clk_disable(); + + return 0; +} + +/*! + * This function is called to bring the NAND back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device information structure + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcnd_resume(struct platform_device *pdev) +{ + DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND2 : NAND resume\n"); + + /* Enable the NFC clock */ + mxc_nand_clk_enable(); + + return 0; +} + +#else +#define mxcnd_suspend NULL +#define mxcnd_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcnd_driver = { + .driver = { + .name = "mxc_nandv2_flash", + }, + .probe = mxcnd_probe, + .remove = __exit_p(mxcnd_remove), + .suspend = mxcnd_suspend, + .resume = mxcnd_resume, +}; + +/*! + * Main initialization routine + * @return 0 if successful; non-zero otherwise + */ +static int __init mxc_nd_init(void) +{ + /* Register the device driver structure. */ + pr_info("MXC MTD nand Driver %s\n", DVR_VER); + if (platform_driver_register(&mxcnd_driver) != 0) { + printk(KERN_ERR "Driver register failed for mxcnd_driver\n"); + return -ENODEV; + } + return 0; +} + +/*! + * Clean up routine + */ +static void __exit mxc_nd_cleanup(void) +{ + /* Unregister the device structure */ + platform_driver_unregister(&mxcnd_driver); +} + +module_init(mxc_nd_init); +module_exit(mxc_nd_cleanup); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC NAND MTD driver Version 2-5"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/nand/mxc_nd2.h b/drivers/mtd/nand/mxc_nd2.h new file mode 100644 index 000000000000..4120c2aa1722 --- /dev/null +++ b/drivers/mtd/nand/mxc_nd2.h @@ -0,0 +1,718 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_nd2.h + * + * @brief This file contains the NAND Flash Controller register information. + * + * + * @ingroup NAND_MTD + */ + +#ifndef __MXC_ND2_H__ +#define __MXC_ND2_H__ + +#include + +#define IS_2K_PAGE_NAND ((mtd->writesize / num_of_interleave) \ + == NAND_PAGESIZE_2KB) +#define IS_4K_PAGE_NAND ((mtd->writesize / num_of_interleave) \ + == NAND_PAGESIZE_4KB) +#define IS_LARGE_PAGE_NAND ((mtd->writesize / num_of_interleave) > 512) + +#define GET_NAND_OOB_SIZE (mtd->oobsize / num_of_interleave) +#define GET_NAND_PAGE_SIZE (mtd->writesize / num_of_interleave) + +#define NAND_PAGESIZE_2KB 2048 +#define NAND_PAGESIZE_4KB 4096 + +/* + * main area for bad block marker is in the last data section + * the spare area for swapped bad block marker is the second + * byte of last spare section + */ +#define NAND_SECTIONS (GET_NAND_PAGE_SIZE >> 9) +#define NAND_OOB_PER_SECTION (((GET_NAND_OOB_SIZE / NAND_SECTIONS) >> 1) << 1) +#define NAND_CHUNKS (GET_NAND_PAGE_SIZE / (512 + NAND_OOB_PER_SECTION)) + +#define BAD_BLK_MARKER_MAIN_OFFS \ + (GET_NAND_PAGE_SIZE - NAND_CHUNKS * NAND_OOB_PER_SECTION) + +#define BAD_BLK_MARKER_SP_OFFS (NAND_CHUNKS * SPARE_LEN) + +#define BAD_BLK_MARKER_OOB_OFFS (NAND_CHUNKS * NAND_OOB_PER_SECTION) + +#define BAD_BLK_MARKER_MAIN \ + ((u32)MAIN_AREA0 + BAD_BLK_MARKER_MAIN_OFFS) + +#define BAD_BLK_MARKER_SP \ + ((u32)SPARE_AREA0 + BAD_BLK_MARKER_SP_OFFS) + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3 +/* + * For V3 NFC registers Definition + */ + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) /* mx37 */ +#define MXC_INT_NANDFC MXC_INT_EMI +#define NFC_FLASH_ADDR_CMD (nfc_axi_base + 0x1E00) +#define NFC_CONFIG1 (nfc_axi_base + 0x1E04) +#define NFC_ECC_STATUS_RESULT (nfc_axi_base + 0x1E08) +#define LAUNCH_NFC (nfc_axi_base + 0x1E0c) +#define NFC_WRPROT (nfc_ip_base + 0x00) +#define NFC_WRPROT_UNLOCK_BLK_ADD0 (nfc_ip_base + 0x04) +#define NFC_CONFIG2 (nfc_ip_base + 0x14) +#define NFC_IPC (nfc_ip_base + 0x18) +#elif defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) /* mx51 */ +#define MXC_INT_NANDFC MXC_INT_NFC +#define NFC_AUTO_MODE_ENABLE +#define NFC_FLASH_CMD (nfc_axi_base + 0x1E00) +#define NFC_FLASH_ADDR0 (nfc_axi_base + 0x1E04) +#define NFC_FLASH_ADDR8 (nfc_axi_base + 0x1E24) +#define NFC_CONFIG1 (nfc_axi_base + 0x1E34) +#define NFC_ECC_STATUS_RESULT (nfc_axi_base + 0x1E38) +#define NFC_ECC_STATUS_SUM (nfc_axi_base + 0x1E3C) +#define LAUNCH_NFC (nfc_axi_base + 0x1E40) +#define NFC_WRPROT (nfc_ip_base + 0x00) +#define NFC_WRPROT_UNLOCK_BLK_ADD0 (nfc_ip_base + 0x04) +#define NFC_CONFIG2 (nfc_ip_base + 0x24) +#define NFC_CONFIG3 (nfc_ip_base + 0x28) +#define NFC_IPC (nfc_ip_base + 0x2C) +#define NFC_DELAY_LINE (nfc_ip_base + 0x34) +#else /* skye */ +#define NFC_FLASH_ADDR_CMD (nfc_axi_base + 0xE00) +#define NFC_CONFIG1 (nfc_axi_base + 0xE04) +#define NFC_ECC_STATUS_RESULT (nfc_axi_base + 0xE08) +#define LAUNCH_NFC (nfc_axi_base + 0xE0C) +#define NFC_WRPROT (nfc_ip_base + 0x00) +#define NFC_WRPROT_UNLOCK_BLK_ADD0 (nfc_ip_base + 0x04) +#define NFC_CONFIG2 (nfc_ip_base + 0x14) +#define NFC_IPC (nfc_ip_base + 0x18) +#endif +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 ((u16 *)(nfc_axi_base + 0x000)) +#define MAIN_AREA1 ((u16 *)(nfc_axi_base + 0x200)) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \ + defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define SPARE_AREA0 ((u16 *)(nfc_axi_base + 0x1000)) +#define SPARE_LEN 64 +#define SPARE_COUNT 8 +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) +#else +#define SPARE_AREA0 ((u16 *)(nfc_axi_base + 0x800)) +#define SPARE_LEN 16 +#define SPARE_COUNT 4 +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) +#endif + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \ + defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define NFC_SPAS_WIDTH 8 +#define NFC_SPAS_SHIFT 16 + +#define NFC_SET_SPAS(v) \ + raw_write((((raw_read(NFC_CONFIG2) & \ + NFC_FIELD_RESET(NFC_SPAS_WIDTH, NFC_SPAS_SHIFT)) | ((v) << 16))), \ + NFC_CONFIG2) + +#define NFC_SET_ECC_MODE(v) \ +do { \ + if (cpu_is_mx53() > 0) { \ + if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \ + raw_write(((raw_read(NFC_CONFIG2) & \ + ~(3 << 6)) | \ + NFC_ECC_MODE_16), NFC_CONFIG2); \ + else \ + raw_write(((raw_read(NFC_CONFIG2) & \ + ~(3 << 6)) | \ + NFC_ECC_MODE_4), NFC_CONFIG2); \ + } else if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { \ + if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \ + raw_write(((raw_read(NFC_CONFIG2) & \ + ~(1 << 6)) | \ + NFC_ECC_MODE_8), NFC_CONFIG2); \ + else \ + raw_write(((raw_read(NFC_CONFIG2) & \ + ~(1 << 6)) | \ + NFC_ECC_MODE_4), NFC_CONFIG2); \ + } else { \ + if ((v) == NFC_SPAS_218 || (v) == NFC_SPAS_112) \ + raw_write(((raw_read(NFC_CONFIG2) & \ + ~(1 << 6)) | \ + NFC_ECC_MODE_4), NFC_CONFIG2); \ + else \ + raw_write(((raw_read(NFC_CONFIG2) & \ + ~(1 << 6)) | \ + NFC_ECC_MODE_8), NFC_CONFIG2); \ + } \ +} while (0) + +#define WRITE_NFC_IP_REG(val, reg) \ + do { \ + raw_write(raw_read(NFC_IPC) | NFC_IPC_CREQ, NFC_IPC); \ + while (!(raw_read(NFC_IPC) & NFC_IPC_ACK)) \ + ; \ + raw_write(val, reg); \ + raw_write(raw_read(NFC_IPC) & ~NFC_IPC_CREQ, NFC_IPC); \ + } while (0) + +#else +#define NFC_SET_SPAS(v) +#define NFC_SET_ECC_MODE(v) +#define NFC_SET_NFMS(v) (NFMS |= (v)) + +#define WRITE_NFC_IP_REG(val, reg) \ + raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \ + REG_NFC_OPS_STAT) +#endif + +#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT); + +/*! + * Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for + * Specific operation + */ +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 /* mx51 */ +#define NFC_AUTO_PROG 0x40 +#define NFC_AUTO_READ 0x80 +#define NFC_AUTO_ERASE 0x200 +#define NFC_COPY_BACK_0 0x400 +#define NFC_COPY_BACK_1 0x800 +#define NFC_AUTO_STATE 0x1000 +#endif + +/* Bit Definitions for NFC_IPC*/ +#define NFC_OPS_STAT (1 << 31) + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 /* mx51 */ +#define NFC_OP_DONE (1 << 30) +#define NFC_RB (1 << 28) +#define NFC_PS_WIDTH 2 +#define NFC_PS_SHIFT 0 +#define NFC_PS_512 0 +#define NFC_PS_2K 1 +#define NFC_PS_4K 2 +#else +#define NFC_RB (1 << 29) +#endif + +#define NFC_ONE_CYCLE (1 << 2) + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 /* mx51 */ +#define NFC_INT_MSK (1 << 15) +#define NFC_AUTO_PROG_DONE_MSK (1 << 14) +#define NFC_NUM_ADDR_PHASE1_WIDTH 2 +#define NFC_NUM_ADDR_PHASE1_SHIFT 12 + +#define NFC_NUM_ADDR_PHASE0_WIDTH 1 +#define NFC_NUM_ADDR_PHASE0_SHIFT 5 + +#define NFC_ONE_LESS_PHASE1 0 +#define NFC_TWO_LESS_PHASE1 1 + +#define NFC_FLASH_ADDR_SHIFT 0 +#else +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_FLASH_ADDR_SHIFT 16 +#endif + +#define NFC_UNLOCK_END_ADDR_SHIFT 16 + +/* Bit definition for NFC_CONFIGRATION_1 */ +#define NFC_SP_EN (1 << 0) +#define NFC_CE (1 << 1) +#define NFC_RST (1 << 2) +#define NFC_ECC_EN (1 << 3) + +#define NFC_FIELD_RESET(width, shift) (~((((1 << (width)) - 1) << (shift)))) + +#define NFC_RBA_SHIFT 4 + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \ + defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) /* mx51 */ +#define NFC_RBA_WIDTH 3 +#else +#define NFC_RBA_WIDTH 2 +#endif + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) /* mx51 */ +#define NFC_ITERATION_SHIFT 8 +#define NFC_ITERATION_WIDTH 4 +#define NFC_ACTIVE_CS_SHIFT 12 +#define NFC_ACTIVE_CS_WIDTH 3 +/* bit definition for CONFIGRATION3 */ +#define NFC_NO_SDMA (1 << 20) +#define NFC_FMP_SHIFT 16 +#define NFC_FMP_WIDTH 4 +#define NFC_RBB_MODE (1 << 15) +#define NFC_NUM_OF_DEVICES_SHIFT 12 +#define NFC_NUM_OF_DEVICES_WIDTH 4 +#define NFC_DMA_MODE_SHIFT 11 +#define NFC_DMA_MODE_WIDTH 1 +#define NFC_SBB_SHIFT 8 +#define NFC_SBB_WIDTH 3 +#define NFC_BIG (1 << 7) +#define NFC_SB2R_SHIFT 4 +#define NFC_SB2R_WIDTH 3 +#define NFC_FW_SHIFT 3 +#define NFC_FW_WIDTH 1 +#define NFC_TOO (1 << 2) +#define NFC_ADD_OP_SHIFT 0 +#define NFC_ADD_OP_WIDTH 2 +#define NFC_FW_8 1 +#define NFC_FW_16 0 +#define NFC_ST_CMD_SHITF 24 +#define NFC_ST_CMD_WIDTH 8 +#endif + +#define NFC_PPB_32 (0 << 7) +#define NFC_PPB_64 (1 << 7) +#define NFC_PPB_128 (2 << 7) +#define NFC_PPB_256 (3 << 7) +#define NFC_PPB_RESET (~(3 << 7)) + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define NFC_BLS_LOCKED (0 << 6) +#define NFC_BLS_LOCKED_DEFAULT (1 << 6) +#define NFC_BLS_UNLCOKED (2 << 6) +#define NFC_BLS_RESET (~(3 << 6)) +#else +#define NFC_BLS_LOCKED (0 << 16) +#define NFC_BLS_LOCKED_DEFAULT (1 << 16) +#define NFC_BLS_UNLCOKED (2 << 16) +#define NFC_BLS_RESET (~(3 << 16)) +#endif + +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_WPC_RESET (~(7)) +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_1) || \ + defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define NFC_ECC_MODE_4 (0x0 << 6) +#define NFC_ECC_MODE_8 (0x1 << 6) +#define NFC_ECC_MODE_16 (0x3 << 6) +#define NFC_SPAS_16 8 +#define NFC_SPAS_64 32 +#define NFC_SPAS_128 64 +#define NFC_SPAS_112 56 +#define NFC_SPAS_218 109 +#define NFC_IPC_CREQ (1 << 0) +#define NFC_IPC_ACK (1 << 1) +#endif + +#define REG_NFC_OPS_STAT NFC_IPC +#define REG_NFC_INTRRUPT NFC_CONFIG2 +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR0 +#define REG_NFC_FLASH_CMD NFC_FLASH_CMD +#else +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR_CMD +#define REG_NFC_FLASH_CMD NFC_FLASH_ADDR_CMD +#endif +#define REG_NFC_OPS LAUNCH_NFC +#define REG_NFC_SET_RBA NFC_CONFIG1 +#define REG_NFC_RB NFC_IPC +#define REG_NFC_ECC_EN NFC_CONFIG2 +#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT +#define REG_NFC_CE NFC_CONFIG1 +#define REG_NFC_RST NFC_CONFIG1 +#define REG_NFC_PPB NFC_CONFIG2 +#define REG_NFC_SP_EN NFC_CONFIG1 +#define REG_NFC_BLS NFC_WRPROT +#define REG_UNLOCK_BLK_ADD0 NFC_WRPROT_UNLOCK_BLK_ADD0 +#define REG_UNLOCK_BLK_ADD1 NFC_WRPROT_UNLOCK_BLK_ADD1 +#define REG_UNLOCK_BLK_ADD2 NFC_WRPROT_UNLOCK_BLK_ADD2 +#define REG_UNLOCK_BLK_ADD3 NFC_WRPROT_UNLOCK_BLK_ADD3 +#define REG_NFC_WPC NFC_WRPROT +#define REG_NFC_ONE_CYCLE NFC_CONFIG2 + +/* NFC V3 Specific MACRO functions definitions */ +#define raw_write(v, a) __raw_writel(v, a) +#define raw_read(a) __raw_readl(a) + +/* Set RBA buffer id*/ +#define NFC_SET_RBA(val) \ + raw_write((raw_read(REG_NFC_SET_RBA) & \ + (NFC_FIELD_RESET(NFC_RBA_WIDTH, NFC_RBA_SHIFT))) | \ + ((val) << NFC_RBA_SHIFT), REG_NFC_SET_RBA); + +#define NFC_SET_PS(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_PS_WIDTH, NFC_PS_SHIFT))) | \ + ((val) << NFC_PS_SHIFT), NFC_CONFIG2); + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_2 +#define UNLOCK_ADDR(start_addr, end_addr) \ +{ \ + int i = 0; \ + for (; i < NAND_MAX_CHIPS; i++) \ + raw_write(start_addr | \ + (end_addr << NFC_UNLOCK_END_ADDR_SHIFT), \ + REG_UNLOCK_BLK_ADD0 + (i << 2)); \ +} +#define NFC_SET_NFC_ACTIVE_CS(val) \ + raw_write((raw_read(NFC_CONFIG1) & \ + (NFC_FIELD_RESET(NFC_ACTIVE_CS_WIDTH, NFC_ACTIVE_CS_SHIFT))) | \ + ((val) << NFC_ACTIVE_CS_SHIFT), NFC_CONFIG1); + +#define NFC_GET_NFC_ACTIVE_CS() \ + ((raw_read(NFC_CONFIG1) >> NFC_ACTIVE_CS_SHIFT) & \ + ((1 << NFC_ACTIVE_CS_WIDTH) - 1)) + +#define NFC_GET_MAXCHIP_SP() 8 + +#else +#define UNLOCK_ADDR(start_addr, end_addr) \ + raw_write(start_addr | \ + (end_addr << NFC_UNLOCK_END_ADDR_SHIFT), REG_UNLOCK_BLK_ADD0); + +#define NFC_SET_NFC_ACTIVE_CS(val) +#define NFC_GET_NFC_ACTIVE_CS() +#define NFC_GET_MAXCHIP_SP() 1 +#endif + +#define NFC_SET_BLS(val) ((raw_read(REG_NFC_BLS) & NFC_BLS_RESET) | val) +#define NFC_SET_WPC(val) ((raw_read(REG_NFC_WPC) & NFC_WPC_RESET) | val) +#define CHECK_NFC_RB (raw_read(REG_NFC_RB) & NFC_RB) + +#if defined(CONFIG_ARCH_MXC_HAS_NFC_V3_2) +#define NFC_SET_NFC_NUM_ADDR_PHASE1(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE1_WIDTH, \ + NFC_NUM_ADDR_PHASE1_SHIFT))) | \ + ((val) << NFC_NUM_ADDR_PHASE1_SHIFT), NFC_CONFIG2); + +#define NFC_SET_NFC_NUM_ADDR_PHASE0(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_NUM_ADDR_PHASE0_WIDTH, \ + NFC_NUM_ADDR_PHASE0_SHIFT))) | \ + ((val) << NFC_NUM_ADDR_PHASE0_SHIFT), NFC_CONFIG2); + +#define NFC_SET_NFC_ITERATION(val) \ + raw_write((raw_read(NFC_CONFIG1) & \ + (NFC_FIELD_RESET(NFC_ITERATION_WIDTH, NFC_ITERATION_SHIFT))) | \ + ((val) << NFC_ITERATION_SHIFT), NFC_CONFIG1); + +#define NFC_SET_FW(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_FW_WIDTH, NFC_FW_SHIFT))) | \ + ((val) << NFC_FW_SHIFT), NFC_CONFIG3); + +#define NFC_SET_NUM_OF_DEVICE(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_NUM_OF_DEVICES_WIDTH, \ + NFC_NUM_OF_DEVICES_SHIFT))) | \ + ((val) << NFC_NUM_OF_DEVICES_SHIFT), NFC_CONFIG3); + +#define NFC_SET_ADD_OP_MODE(val) \ + raw_write((raw_read(NFC_CONFIG3) & \ + (NFC_FIELD_RESET(NFC_ADD_OP_WIDTH, NFC_ADD_OP_SHIFT))) | \ + ((val) << NFC_ADD_OP_SHIFT), NFC_CONFIG3); + +#define NFC_SET_ADD_CS_MODE(val) \ +{ \ + NFC_SET_ADD_OP_MODE(val); \ + NFC_SET_NUM_OF_DEVICE(this->numchips - 1); \ +} + +#define NFC_SET_ST_CMD(val) \ + raw_write((raw_read(NFC_CONFIG2) & \ + (NFC_FIELD_RESET(NFC_ST_CMD_WIDTH, \ + NFC_ST_CMD_SHITF))) | \ + ((val) << NFC_ST_CMD_SHITF), NFC_CONFIG2); + +#define NFMS_NF_DWIDTH 0 +#define NFMS_NF_PG_SZ 1 +#define NFC_CMD_1_SHIFT 8 + +#define NUM_OF_ADDR_CYCLE (fls(g_page_mask) >> 3) +#define SET_NFC_DELAY_LINE(val) raw_write((val), NFC_DELAY_LINE) + +/*should set the fw,ps,spas,ppb*/ +#define NFC_SET_NFMS(v) \ +do { \ + if (!(v)) \ + NFC_SET_FW(NFC_FW_8); \ + if (((v) & (1 << NFMS_NF_DWIDTH))) \ + NFC_SET_FW(NFC_FW_16); \ + if (((v) & (1 << NFMS_NF_PG_SZ))) { \ + if (IS_2K_PAGE_NAND) { \ + NFC_SET_PS(NFC_PS_2K); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \ + } else if (IS_4K_PAGE_NAND) { \ + NFC_SET_PS(NFC_PS_4K); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_TWO_LESS_PHASE1); \ + } else { \ + NFC_SET_PS(NFC_PS_512); \ + NFC_SET_NFC_NUM_ADDR_PHASE1(NUM_OF_ADDR_CYCLE - 1); \ + NFC_SET_NFC_NUM_ADDR_PHASE0(NFC_ONE_LESS_PHASE1); \ + } \ + NFC_SET_ADD_CS_MODE(1); \ + NFC_SET_SPAS(GET_NAND_OOB_SIZE >> 1); \ + NFC_SET_ECC_MODE(GET_NAND_OOB_SIZE >> 1); \ + NFC_SET_ST_CMD(0x70); \ + raw_write(raw_read(NFC_CONFIG3) | NFC_NO_SDMA, NFC_CONFIG3); \ + raw_write(raw_read(NFC_CONFIG3) | NFC_RBB_MODE, NFC_CONFIG3); \ + if (cpu_is_mx51()) \ + SET_NFC_DELAY_LINE(0); \ + } \ +} while (0) +#endif + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V3_1 +#define NFC_SET_NFMS(v) +#endif + +#define READ_PAGE() send_read_page(0) +#define PROG_PAGE() send_prog_page(0) + +#elif CONFIG_ARCH_MXC_HAS_NFC_V2 + +/* + * For V1/V2 NFC registers Definition + */ + +/* + * Addresses for NFC registers + */ +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define NFC_REG_BASE (nfc_axi_base + 0x1000) +#else +#define NFC_REG_BASE nfc_axi_base +#endif +#define NFC_BUF_SIZE (NFC_REG_BASE + 0xE00) +#define NFC_BUF_ADDR (NFC_REG_BASE + 0xE04) +#define NFC_FLASH_ADDR (NFC_REG_BASE + 0xE06) +#define NFC_FLASH_CMD (NFC_REG_BASE + 0xE08) +#define NFC_CONFIG (NFC_REG_BASE + 0xE0A) +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C) +#define NFC_ECC_STATUS_RESULT_1 (NFC_REG_BASE + 0xE0C) +#define NFC_ECC_STATUS_RESULT_2 (NFC_REG_BASE + 0xE0E) +#define NFC_SPAS (NFC_REG_BASE + 0xE10) +#else +#define NFC_ECC_STATUS_RESULT (NFC_REG_BASE + 0xE0C) +#define NFC_RSLTMAIN_AREA (NFC_REG_BASE + 0xE0E) +#define NFC_RSLTSPARE_AREA (NFC_REG_BASE + 0xE10) +#endif +#define NFC_WRPROT (NFC_REG_BASE + 0xE12) +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE20) +#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE22) +#define NFC_UNLOCKSTART_BLKADDR1 (NFC_REG_BASE + 0xE24) +#define NFC_UNLOCKEND_BLKADDR1 (NFC_REG_BASE + 0xE26) +#define NFC_UNLOCKSTART_BLKADDR2 (NFC_REG_BASE + 0xE28) +#define NFC_UNLOCKEND_BLKADDR2 (NFC_REG_BASE + 0xE2A) +#define NFC_UNLOCKSTART_BLKADDR3 (NFC_REG_BASE + 0xE2C) +#define NFC_UNLOCKEND_BLKADDR3 (NFC_REG_BASE + 0xE2E) +#else +#define NFC_UNLOCKSTART_BLKADDR (NFC_REG_BASE + 0xE14) +#define NFC_UNLOCKEND_BLKADDR (NFC_REG_BASE + 0xE16) +#endif +#define NFC_NF_WRPRST (NFC_REG_BASE + 0xE18) +#define NFC_CONFIG1 (NFC_REG_BASE + 0xE1A) +#define NFC_CONFIG2 (NFC_REG_BASE + 0xE1C) + +/*! + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (u16 *)(nfc_axi_base + 0x000) +#define MAIN_AREA1 (u16 *)(nfc_axi_base + 0x200) + +/*! + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define SPARE_AREA0 (u16 *)(nfc_axi_base + 0x1000) +#define SPARE_LEN 64 +#define SPARE_COUNT 8 +#else +#define SPARE_AREA0 (u16 *)(nfc_axi_base + 0x800) +#define SPARE_LEN 16 +#define SPARE_COUNT 4 +#endif +#define SPARE_SIZE (SPARE_LEN * SPARE_COUNT) + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define REG_NFC_ECC_MODE NFC_CONFIG1 +#define SPAS_SHIFT (0) +#define REG_NFC_SPAS NFC_SPAS +#define SPAS_MASK (0xFF00) + +#define NFC_SET_SPAS(v) \ + raw_write(((raw_read(REG_NFC_SPAS) & SPAS_MASK) | ((v<> 1); \ + } \ +} while (0) +#else +#define NFC_SET_SPAS(v) +#define NFC_SET_ECC_MODE(v) +#define GET_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT); +#define NFC_SET_NFMS(v) (NFMS |= (v)) +#endif + +#define WRITE_NFC_IP_REG(val, reg) \ + raw_write((raw_read(REG_NFC_OPS_STAT) & ~NFC_OPS_STAT), \ + REG_NFC_OPS_STAT) + +#define GET_NFC_ECC_STATUS() raw_read(REG_NFC_ECC_STATUS_RESULT); + +/*! + * Set INT to 0, Set 1 to specific operation bit, rest to 0 in LAUNCH_NFC Register for + * Specific operation + */ +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +/* Bit Definitions */ +#define NFC_OPS_STAT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLCOKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define NFC_ECC_MODE_4 (1<<0) +#define NFC_ECC_MODE_8 (~(1<<0)) +#define NFC_SPAS_16 8 +#define NFC_SPAS_64 32 +#define NFC_SPAS_112 56 +#define NFC_SPAS_128 64 +#define NFC_SPAS_218 109 +#endif +/* NFC Register Mapping */ +#define REG_NFC_OPS_STAT NFC_CONFIG2 +#define REG_NFC_INTRRUPT NFC_CONFIG1 +#define REG_NFC_FLASH_ADDR NFC_FLASH_ADDR +#define REG_NFC_FLASH_CMD NFC_FLASH_CMD +#define REG_NFC_OPS NFC_CONFIG2 +#define REG_NFC_SET_RBA NFC_BUF_ADDR +#define REG_NFC_ECC_EN NFC_CONFIG1 +#define REG_NFC_ECC_STATUS_RESULT NFC_ECC_STATUS_RESULT +#define REG_NFC_CE NFC_CONFIG1 +#define REG_NFC_SP_EN NFC_CONFIG1 +#define REG_NFC_BLS NFC_CONFIG +#define REG_NFC_WPC NFC_WRPROT +#define REG_START_BLKADDR NFC_UNLOCKSTART_BLKADDR +#define REG_END_BLKADDR NFC_UNLOCKEND_BLKADDR +#define REG_NFC_RST NFC_CONFIG1 +#define REG_NFC_ONE_CYCLE NFC_CONFIG1 + +/* NFC V1/V2 Specific MACRO functions definitions */ + +#define raw_write(v, a) __raw_writew(v, a) +#define raw_read(a) __raw_readw(a) + +#define NFC_SET_BLS(val) val + +#define UNLOCK_ADDR(start_addr, end_addr) \ +{ \ + raw_write(start_addr, REG_START_BLKADDR); \ + raw_write(end_addr, REG_END_BLKADDR); \ +} + +#define NFC_SET_NFC_ACTIVE_CS(val) +#define NFC_GET_NFC_ACTIVE_CS() +#define NFC_GET_MAXCHIP_SP() 1 +#define NFC_SET_WPC(val) val + +#define NFC_SET_RBA(val) raw_write(val, REG_NFC_SET_RBA); + +#ifdef CONFIG_ARCH_MXC_HAS_NFC_V2_1 +#define READ_PAGE() send_read_page(0) +#define PROG_PAGE() send_prog_page(0) +#else +#define READ_PAGE() \ +do { \ + send_read_page(0); \ + send_read_page(1); \ + send_read_page(2); \ + send_read_page(3); \ +} while (0) + +#define PROG_PAGE() \ +do { \ + send_prog_page(0); \ + send_prog_page(1); \ + send_prog_page(2); \ + send_prog_page(3); \ +} while (0) +#endif +#define CHECK_NFC_RB 1 + +#endif + +#endif /* __MXC_ND2_H__ */ diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 4a7b86423ee9..3a8216bbf838 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1424,7 +1424,7 @@ static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, * * Internal function. Called with chip held. */ -static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, +int nand_do_read_ops(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { int chipnr, page, realpage, col, bytes, aligned; @@ -1553,6 +1553,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; } +EXPORT_SYMBOL(nand_do_read_ops); /** * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc @@ -2133,7 +2134,7 @@ static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len, * * NAND write with ECC */ -static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, +int nand_do_write_ops(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) { int chipnr, realpage, page, blockmask, column; @@ -2237,6 +2238,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, ops->oobretlen = ops->ooblen; return ret; } +EXPORT_SYMBOL(nand_do_write_ops); /** * panic_nand_write - [MTD Interface] NAND write with ECC @@ -2584,6 +2586,12 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, instr->state = MTD_ERASE_FAILED; instr->fail_addr = ((loff_t)page << chip->page_shift); + + if (chip->bbt) { + int i = (page / pages_per_block) << 1; + chip->bbt[i >> 3] |= 0x03 << (i & 0x6); + mtd->ecc_stats.badblocks++; + } goto erase_exit; } @@ -2649,6 +2657,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, /* Return more or less happy */ return ret; } +EXPORT_SYMBOL_GPL(nand_erase_nand); /** * nand_sync - [MTD Interface] sync @@ -2834,8 +2843,10 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->chipsize = (uint64_t)type->chipsize << 20; - /* Newer devices have all the information in additional id bytes */ - if (!type->pagesize) { + if (!type->pagesize && chip->init_size) { + /* set the pagesize, oobsize, erasesize by the driver*/ + busw = chip->init_size(mtd, chip, id_data); + } else if (!type->pagesize) { int extid; /* The 3rd id byte holds MLC / multichip data */ chip->cellinfo = id_data[2]; diff --git a/drivers/mtd/nand/nand_device_info.c b/drivers/mtd/nand/nand_device_info.c new file mode 100644 index 000000000000..6a23810ebadb --- /dev/null +++ b/drivers/mtd/nand/nand_device_info.c @@ -0,0 +1,2413 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +#include "nand_device_info.h" + +/* + * Type 2 + */ +static struct nand_device_info nand_device_info_table_type_2[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 20, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "NAND01GW3", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 20, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 25, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F1F08", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 20, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG0S3", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "NAND02GW3", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 25, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UF082G2M, HY27UG082G2M, HY27UG082G1M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F2G08", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F2G08U0M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG1S3", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 10, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UH084G2M, HY27UG084G2M, HY27UH084G1M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F4G08", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 25, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 25, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TH58NVG2S3", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 30, + .data_hold_in_ns = 25, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UH088G2M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "NAND08GW3BxANx", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F8G08FABWG", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 30, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 32, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0x48, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + /* TODO: The actual oob size for MT29F16G08ABACA is + 224 bytes. Use oob 218 bytes since MX53 NFC controller + mentions the spare area size must be less or equal 218 + byte if ECC is enabled */ + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F16G08ABACA(2GB)", + }, + {true} +}; + +/* + * Large MLC + */ +static struct nand_device_info nand_device_info_table_large_mlc[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG1D4BFT00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TH58NVG3D4xFT00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 20, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 15, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TH58NVG4D4xFT00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x45, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 35, + .data_hold_in_ns = 15, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 30, + .address_setup_in_ns = 0, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG2D4BFT00", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9G4G08U0M", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 45, + .data_hold_in_ns = 25, + .address_setup_in_ns = 50, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UT084G2M, HY27UU088G5M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x20, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 40, + .data_hold_in_ns = 20, + .address_setup_in_ns = 30, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "NAND04GW3C2AN1E", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 15, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9G8G08U0M, K9HAG08U1M", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 60, + .data_hold_in_ns = 30, + .address_setup_in_ns = 50, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UV08AG5M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "Intel JS29F08G08AAMiB1 and Micron MT29F8G08MAA; " + "Intel JS29F08G08CAMiB1 and Micron MT29F16G08QAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 15, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9LAG08U0M K9HBG08U1M K9GAG08U0M", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "Intel JS29F32G08FAMiB1 and Micron MT29F32G08TAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 20, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F4G08", + }, + { + .end_of_table = false, + .manufacturer_code = 0x89, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "JS29F08G08AAMiB2, JS29F08G08CAMiB2", + }, + { + .end_of_table = false, + .manufacturer_code = 0x89, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "JS29F32G08FAMiB2", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "HY27UW08CGFM", + }, + {true} +}; + +/* + * Type 7 + */ +static struct nand_device_info nand_device_info_table_type_7[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F8G08FABWG", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F4G08AAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xdc, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 512LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 12, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F4G08", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 35, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9K8G08UXM, K9NBG08U5A, K9WAG08U1A", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 12, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9WAG08UXM", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xda, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 256LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F2G08U0A", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xf1, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 128LL*SZ_1M, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 2*SZ_1K + 64, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 12, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9F1F08", + }, + {true} +}; + +/* + * Type 8 + */ +static struct nand_device_info nand_device_info_table_type_8[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9GAG08U0M", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9LBG08U0M (32Gb), K9HCG08U1M (64Gb), K9MDG08U5M (128Gb)", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 20, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 0, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "H27UAG, H27UBG", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 23, + .data_hold_in_ns = 20, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 0, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "H27UCG", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "H27U8G8T2B", + }, + {true} +}; + +/* + * Type 9 + */ +static struct nand_device_info nand_device_info_table_type_9[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG3D1DTG00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TC58NVG4D1DTG00", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 10, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "TH58NVG6D1DTG20", + }, + { + .end_of_table = false, + .manufacturer_code = 0x89, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "JS29F16G08AAMC1, JS29F32G08CAMC1", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F16G08MAA, MT29F32G08QAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F64G08TAA (32Gb), MT29F32G08CBAAA (32Gb) MT29F64G08CFAAA (64Gb)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd9, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "MT29F128G08CJAAA", + }, + { + .end_of_table = false, + .manufacturer_code = 0x89, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "JSF64G08FAMC1", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "K9LBG08U0D", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 8, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9GAG08U0D, K9LBG08U1D, K9HCG08U5D", + }, + {true} +}; + +/* + * Type 10 + */ +static struct nand_device_info nand_device_info_table_type_10[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd3, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 1LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 25, + .data_hold_in_ns = 15, + .address_setup_in_ns = 30, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + "K9NCG08U5M", + }, + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_SLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 64, + .page_total_size_in_bytes = 4*SZ_1K + 128, + .ecc_strength_in_bits = 4, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 15, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = -1, + .tRLOH_in_ns = -1, + .tRHOH_in_ns = -1, + NULL, + }, + {true} +}; + +/* + * Type 11 + */ +static struct nand_device_info nand_device_info_table_type_11[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 8*SZ_1K + 376, + .ecc_strength_in_bits = 14, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 8, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 25, + "TC58NVG5D2ELAM8 (4GB), TH58NVG6D2ELAM8 (8GB)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x98, + .device_code = 0xde, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 8*SZ_1K + 376, + .ecc_strength_in_bits = 14, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 8, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 25, + "TH58NVG7D2ELAM8", + }, + {true} +}; + +/* + * Type 15 + */ +static struct nand_device_info nand_device_info_table_type_15[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 8*SZ_1K + 436, + .ecc_strength_in_bits = 16, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 25, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "K9GBG08U0M (4GB, 1CE); K9LCG08U1M (8GB, 2CE); K9HDG08U5M (16GB, 4CE)", + }, + {true} +}; + +static struct nand_device_info nand_device_info_table_type_16[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0xec, + .device_code = 0xd7, + .is_ddr_ok = true, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 8*SZ_1K + 512, + .ecc_strength_in_bits = 24, + .ecc_size_in_bytes = 1024, + .data_setup_in_ns = 20, + .data_hold_in_ns = 10, + .address_setup_in_ns = 25, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 25, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "K9LCGD88X1M(8GB, 1CE); K9HDGD8X5M(8GB, 2CE); K9PFGD8X7M(16GB, 4CE)", + }, + {true} +}; +/* + * BCH ECC12 + */ +static struct nand_device_info nand_device_info_table_bch_ecc12[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd5, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "H27UAG8T2ATR (2GB, 1CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "H27UBG8T2M (4GB, 1CE), H27UCG8UDM (8GB, 2CE), H27UDG8VEM (16GB, 4CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0xad, + .device_code = 0xde, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "H27UEG8YEM (32GB, 4CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd7, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 16, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F32G08CBAAA (4GB, 1CE), MT29F64G08CFAAA (8GB, 2CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0xd9, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 128, + .page_total_size_in_bytes = 4*SZ_1K + 218, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 10, + .data_hold_in_ns = 10, + .address_setup_in_ns = 15, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 16, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F128G08CJAAA (16GB, 2CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0x48, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 2LL*SZ_1G, + .block_size_in_pages = 256, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F16G08CBABA (2GB, 1CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0x68, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 4LL*SZ_1G, + .block_size_in_pages = 256, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F32G08CBABA (4GB, 1CE); " + "MT29F64G08CEABA (8GB, 2CE); " + "MT29F64G08CFABA (8GB, 2CE)", + }, + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0x88, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL*SZ_1G, + .block_size_in_pages = 256, + .page_total_size_in_bytes = 4*SZ_1K + 224, + .ecc_strength_in_bits = 12, + .ecc_size_in_bytes = 512, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F128G08CJABA (16GB, 2CE); " + "MT29F128G08CKABA (16GB, 2CE); " + "MT29F256G08CUABA (32GB, 4CE)", + }, + {true} +}; + +/* + * BCH ECC24 + */ +static struct nand_device_info nand_device_info_table_bch_ecc24[] __initdata = { + { + .end_of_table = false, + .manufacturer_code = 0x2c, + .device_code = 0x88, + .is_ddr_ok = true, + .cell_technology = NAND_DEVICE_CELL_TECH_MLC, + .chip_size_in_bytes = 8LL * SZ_1G, + .block_size_in_pages = 256, + .page_total_size_in_bytes = 8 * SZ_1K + 448, + .ecc_strength_in_bits = 24, + .ecc_size_in_bytes = 1024, + .data_setup_in_ns = 15, + .data_hold_in_ns = 10, + .address_setup_in_ns = 20, + .gpmi_sample_delay_in_ns = 6, + .tREA_in_ns = 20, + .tRLOH_in_ns = 5, + .tRHOH_in_ns = 15, + "MT29F64G08CBAAA(8GB, 2CE) ", + }, + {true} +}; + +/* + * The following macros make it convenient to extract information from an ID + * byte array. All these macros begin with the prefix "ID_". + * + * Macros of the form: + * + * ID_GET_[_[_]] + * + * extract the given field from an ID byte array. Macros of the form: + * + * ID_[_[_]]_ + * + * contain the value for the given field that has the given meaning. + * + * If the appears, it means this macro represents a view of this + * field that is specific to the given manufacturer. + * + * If the appears, it means this macro represents a view of this + * field that the given manufacturer applies only under specific conditions. + * + * Here is a simple example: + * + * ID_PAGE_SIZE_CODE_2K + * + * This macro has the value of the "Page Size" field that indicates the page + * size is 2K. + * + * A more complicated example: + * + * ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2) + * + * This macro has the value of the "Page Size" field for Samsung parts that + * indicates the page size is 8K. However, this interpretation is only correct + * for devices that return 6 ID bytes. + */ + +/* Byte 1 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_1(id) ((id)[0]) + +#define ID_GET_MFR_CODE(id) ID_GET_BYTE_1(id) + +/* Byte 2 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_2(id) ((id)[1]) + +#define ID_GET_DEVICE_CODE(id) ID_GET_BYTE_2(id) + #define ID_SAMSUNG_DEVICE_CODE_1_GBIT (0xf1) + #define ID_SAMSUNG_DEVICE_CODE_2_GBIT (0xda) + #define ID_HYNIX_DEVICE_CODE_ECC12 (0xd7) + #define ID_HYNIX_DEVICE_CODE_ECC12_ODD (0xd5) + #define ID_HYNIX_DEVICE_CODE_ECC12_LARGE (0xde) + #define ID_MICRON_DEVICE_CODE_ECC12 (0xd7) /* ECC12 */ + #define ID_MICRON_DEVICE_CODE_ECC12_LARGE (0xd9) /* ECC12 8GB/CE */ + #define ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE (0x48) /* L63B 2GB/CE */ + #define ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE (0x68) /* L63B 4GB/CE */ + #define ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE (0x88) /* L63B 8GB/CE */ + #define ID_MICRON_DEVICE_CODE_ECC24_8GB_PER_CE (0x88) /* L63B 8GB/CE */ + +/* Byte 3 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_3(id) ((id)[2]) + +#define ID_GET_DIE_COUNT_CODE(id) ((ID_GET_BYTE_3(id) >> 0) & 0x3) + +#define ID_GET_CELL_TYPE_CODE(id) ((ID_GET_BYTE_3(id) >> 2) & 0x3) + #define ID_CELL_TYPE_CODE_SLC (0x0) /* All others => MLC. */ + +#define ID_GET_SAMSUNG_SIMUL_PROG(id) ((ID_GET_BYTE_3(id) >> 4) & 0x3) + +#define ID_GET_MICRON_SIMUL_PROG(id) ((ID_GET_BYTE_3(id) >> 4) & 0x3) + +#define ID_GET_CACHE_PROGRAM(id) ((ID_GET_BYTE_3(id) >> 7) & 0x1) + +#define ID_ONFI_NAND_BYTE3 (0x04) +/* Byte 4 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_4(id) ((id)[3]) + #define ID_HYNIX_BYTE_4_ECC12_DEVICE (0x25) + +#define ID_GET_PAGE_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 0) & 0x3) + #define ID_PAGE_SIZE_CODE_1K (0x0) + #define ID_PAGE_SIZE_CODE_2K (0x1) + #define ID_PAGE_SIZE_CODE_4K (0x2) + #define ID_PAGE_SIZE_CODE_8K (0x3) + #define ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K (0x2) + +#define ID_GET_OOB_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 2) & 0x1) + +#define ID_GET_BLOCK_SIZE_CODE(id) ((ID_GET_BYTE_4(id) >> 4) & 0x3) + +/* Byte 5 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_5(id) ((id)[4]) + #define ID_MICRON_BYTE_5_ECC12 (0x84) + +#define ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) ((ID_GET_BYTE_5(id) >> 4) & 0x7) + #define ID_SAMSUNG_ECC_LEVEL_CODE_8 (0x03) + #define ID_SAMSUNG_ECC_LEVEL_CODE_24 (0x05) + +#define ID_GET_PLANE_COUNT_CODE(id) ((ID_GET_BYTE_5(id) >> 2) & 0x3) + +/* Byte 6 ------------------------------------------------------------------- */ + +#define ID_GET_BYTE_6(id) ((id)[5]) + #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K (0x54) + #define ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_4K (0x13) + +#define ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) ((ID_GET_BYTE_6(id)>>0) & 0x7) + #define ID_SAMSUNG_DEVICE_VERSION_CODE_40NM (0x01) + +#define ID_GET_TOGGLE_NAND(id) ((ID_GET_BYTE_6(id) >> 7) & 0x1) + +/* -------------------------------------------------------------------------- */ + +void nand_device_print_info(struct nand_device_info *info) +{ + unsigned i; + const char *mfr_name; + const char *cell_technology_name; + uint64_t chip_size; + const char *chip_size_units; + unsigned page_data_size_in_bytes; + unsigned page_oob_size_in_bytes; + + /* Check for nonsense. */ + + if (!info) + return; + + /* Prepare the manufacturer name. */ + + mfr_name = "Unknown"; + + for (i = 0; nand_manuf_ids[i].id; i++) { + if (nand_manuf_ids[i].id == info->manufacturer_code) { + mfr_name = nand_manuf_ids[i].name; + break; + } + } + + /* Prepare the name of the cell technology. */ + + switch (info->cell_technology) { + case NAND_DEVICE_CELL_TECH_SLC: + cell_technology_name = "SLC"; + break; + case NAND_DEVICE_CELL_TECH_MLC: + cell_technology_name = "MLC"; + break; + default: + cell_technology_name = "Unknown"; + break; + } + + /* Prepare the chip size. */ + + if ((info->chip_size_in_bytes >= SZ_1G) && + !(info->chip_size_in_bytes % SZ_1G)) { + chip_size = info->chip_size_in_bytes / ((uint64_t) SZ_1G); + chip_size_units = "GiB"; + } else if ((info->chip_size_in_bytes >= SZ_1M) && + !(info->chip_size_in_bytes % SZ_1M)) { + chip_size = info->chip_size_in_bytes / ((uint64_t) SZ_1M); + chip_size_units = "MiB"; + } else { + chip_size = info->chip_size_in_bytes; + chip_size_units = "B"; + } + + /* Prepare the page geometry. */ + + page_data_size_in_bytes = (1<<(fls(info->page_total_size_in_bytes)-1)); + page_oob_size_in_bytes = info->page_total_size_in_bytes - + page_data_size_in_bytes; + + /* Print the information. */ + + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name, + info->manufacturer_code); + printk(KERN_INFO "Device Code : 0x%02x\n", info->device_code); + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name); + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size, + chip_size_units); + printk(KERN_INFO "Pages per Block : %u\n", + info->block_size_in_pages); + printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes, + page_oob_size_in_bytes); + printk(KERN_INFO "ECC Strength : %u bits\n", + info->ecc_strength_in_bits); + printk(KERN_INFO "ECC Size : %u B\n", info->ecc_size_in_bytes); + printk(KERN_INFO "Data Setup Time : %u ns\n", info->data_setup_in_ns); + printk(KERN_INFO "Data Hold Time : %u ns\n", info->data_hold_in_ns); + printk(KERN_INFO "Address Setup Time: %u ns\n", + info->address_setup_in_ns); + printk(KERN_INFO "GPMI Sample Delay : %u ns\n", + info->gpmi_sample_delay_in_ns); + if (info->tREA_in_ns >= 0) + printk(KERN_INFO "tREA : %u ns\n", + info->tREA_in_ns); + else + printk(KERN_INFO "tREA : Unknown\n"); + if (info->tREA_in_ns >= 0) + printk(KERN_INFO "tRLOH : %u ns\n", + info->tRLOH_in_ns); + else + printk(KERN_INFO "tRLOH : Unknown\n"); + if (info->tREA_in_ns >= 0) + printk(KERN_INFO "tRHOH : %u ns\n", + info->tRHOH_in_ns); + else + printk(KERN_INFO "tRHOH : Unknown\n"); + if (info->description) + printk(KERN_INFO "Description : %s\n", info->description); + else + printk(KERN_INFO "Description : \n"); + +} + +static struct nand_device_info *nand_device_info_search( + struct nand_device_info *table, uint8_t mfr_code, uint8_t device_code) +{ + + for (; !table->end_of_table; table++) { + if (table->manufacturer_code != mfr_code) + continue; + if (table->device_code != device_code) + continue; + return table; + } + + return 0; + +} + +static struct nand_device_info * __init nand_device_info_fn_toshiba(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) { + /* Type 2 */ + return nand_device_info_search(nand_device_info_table_type_2, + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id)); + } + + /* + * Look for 8K page Toshiba MLC devices. + * + * The page size field in byte 4 can't be used because the field was + * redefined in the 8K parts so the value meaning "8K page" is the same + * as the value meaning "4K page" on the 4K page devices. + * + * The only identifiable difference between the 4K and 8K page Toshiba + * devices with a device code of 0xd7 is the undocumented 6th ID byte. + * The 4K device returns a value of 0x13 and the 8K a value of 0x54. + * Toshiba has verified that this is an acceptable method to distinguish + * the two device families. + */ + + if (ID_GET_BYTE_6(id) == ID_TOSHIBA_BYTE_6_PAGE_SIZE_CODE_8K) { + /* Type 11 */ + table = nand_device_info_table_type_11; + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Type 9 */ + table = nand_device_info_table_type_9; + } else { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info * __init nand_device_info_fn_samsung(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an MLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) { + + /* Is this a Samsung 8K Page MLC device with 16 bit ECC? */ + if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) == + ID_SAMSUNG_ECC_LEVEL_CODE_24) && + (ID_GET_PAGE_SIZE_CODE(id) == + ID_SAMSUNG_6_BYTE_PAGE_SIZE_CODE_8K)) { + if (ID_GET_TOGGLE_NAND(id)) + table = nand_device_info_table_type_16; + else + /* Type 15 */ + table = nand_device_info_table_type_15; + } + /* Is this a Samsung 42nm ECC8 device with a 6 byte ID? */ + else if ((ID_GET_SAMSUNG_ECC_LEVEL_CODE(id) == + ID_SAMSUNG_ECC_LEVEL_CODE_8) && + (ID_GET_SAMSUNG_DEVICE_VERSION_CODE(id) == + ID_SAMSUNG_DEVICE_VERSION_CODE_40NM)) { + /* Type 9 */ + table = nand_device_info_table_type_9; + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Type 8 */ + table = nand_device_info_table_type_8; + } else { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } + + } else { + + /* Check the page size first. */ + if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Type 10 */ + table = nand_device_info_table_type_10; + } + /* Check the chip size. */ + else if (ID_GET_DEVICE_CODE(id) == + ID_SAMSUNG_DEVICE_CODE_1_GBIT) { + if (!ID_GET_CACHE_PROGRAM(id)) { + /* + * 128 MiB Samsung chips without cache program + * are Type 7. + * + * The K9F1G08U0B does not support multi-plane + * program, so the if statement below cannot be + * used to identify it. + */ + table = nand_device_info_table_type_7; + + } else { + /* Smaller sizes are Type 2 by default. */ + table = nand_device_info_table_type_2; + } + } else { + /* Check number of simultaneously programmed pages. */ + if (ID_GET_SAMSUNG_SIMUL_PROG(id) && + ID_GET_PLANE_COUNT_CODE(id)) { + /* Type 7 */ + table = nand_device_info_table_type_7; + } else { + /* Type 2 */ + table = nand_device_info_table_type_2; + } + + } + + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info * __init nand_device_info_fn_stmicro(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) + /* Type 2 */ + table = nand_device_info_table_type_2; + else + /* Large MLC */ + table = nand_device_info_table_large_mlc; + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info * __init nand_device_info_fn_hynix(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) { + /* Type 2 */ + return nand_device_info_search(nand_device_info_table_type_2, + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id)); + } + + /* + * Check for ECC12 devices. + * + * We look at the 4th ID byte to distinguish some Hynix ECC12 devices + * from the similar ECC8 part. For example H27UBG8T2M (ECC12) 4th byte + * is 0x25, whereas H27UDG8WFM (ECC8) 4th byte is 0xB6. + */ + + if ((((ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12) || + (ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12_ODD)) && + ID_GET_BYTE_4(id) == ID_HYNIX_BYTE_4_ECC12_DEVICE) || + (ID_GET_DEVICE_CODE(id) == ID_HYNIX_DEVICE_CODE_ECC12_LARGE)) { + /* BCH ECC 12 */ + table = nand_device_info_table_bch_ecc12; + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* + * So far, all other Samsung and Hynix 4K page devices are + * Type 8. + */ + table = nand_device_info_table_type_8; + } else + /* Large MLC */ + table = nand_device_info_table_large_mlc; + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info * __init nand_device_info_fn_micron(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) { + + /* Check number of simultaneously programmed pages. */ + + if (ID_GET_MICRON_SIMUL_PROG(id)) { + /* Type 7 */ + table = nand_device_info_table_type_7; + } else { + /* Zero simultaneously programmed pages means Type 2. */ + table = nand_device_info_table_type_2; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + + } + + if (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC24_8GB_PER_CE + && ID_GET_BYTE_3(id) == ID_ONFI_NAND_BYTE3) { + /* BCH ECC 24 */ + table = nand_device_info_table_bch_ecc24; + } else + /* + * We look at the 5th ID byte to distinguish some Micron ECC12 NANDs + * from the similar ECC8 part. + * + * For example MT29F64G08CFAAA (ECC12) 5th byte is 0x84, whereas + * MT29F64G08TAA (ECC8) 5th byte is 0x78. + * + * We also have a special case for the Micron L63B family + * (256 page/block), which has unique device codes but no ID fields that + * can easily be used to distinguish the family. + */ + + if ((ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12 && + ID_GET_BYTE_5(id) == ID_MICRON_BYTE_5_ECC12) || + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_LARGE) || + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_2GB_PER_CE) || + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_4GB_PER_CE) || + (ID_GET_DEVICE_CODE(id) == ID_MICRON_DEVICE_CODE_ECC12_8GB_PER_CE)) { + /* BCH ECC 12 */ + table = nand_device_info_table_bch_ecc12; + } else if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Toshiba devices with 4K pages are Type 9. */ + table = nand_device_info_table_type_9; + } else { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info * __init nand_device_info_fn_sandisk(const uint8_t id[]) +{ + struct nand_device_info *table; + + if (ID_GET_CELL_TYPE_CODE(id) != ID_CELL_TYPE_CODE_SLC) { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } else { + /* Type 2 */ + table = nand_device_info_table_type_2; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +static struct nand_device_info * __init nand_device_info_fn_intel(const uint8_t id[]) +{ + struct nand_device_info *table; + + /* Check for an SLC device. */ + + if (ID_GET_CELL_TYPE_CODE(id) == ID_CELL_TYPE_CODE_SLC) { + /* Type 2 */ + return nand_device_info_search(nand_device_info_table_type_2, + ID_GET_MFR_CODE(id), ID_GET_DEVICE_CODE(id)); + } + + if (ID_GET_PAGE_SIZE_CODE(id) == ID_PAGE_SIZE_CODE_4K) { + /* Type 9 */ + table = nand_device_info_table_type_9; + } else { + /* Large MLC */ + table = nand_device_info_table_large_mlc; + } + + return nand_device_info_search(table, ID_GET_MFR_CODE(id), + ID_GET_DEVICE_CODE(id)); + +} + +/** + * struct nand_device_type_info - Information about a NAND Flash type. + * + * @name: A human-readable name for this type. + * @table: The device info table for this type. + */ + +struct nand_device_type_info { + struct nand_device_info *table; + const char *name; +}; + +/* + * A table that maps manufacturer IDs to device information tables. + */ + +static struct nand_device_type_info nand_device_type_directory[] __initdata = { + {nand_device_info_table_type_2, "Type 2" }, + {nand_device_info_table_large_mlc, "Large MLC"}, + {nand_device_info_table_type_7, "Type 7" }, + {nand_device_info_table_type_8, "Type 8" }, + {nand_device_info_table_type_9, "Type 9" }, + {nand_device_info_table_type_10, "Type 10" }, + {nand_device_info_table_type_11, "Type 11" }, + {nand_device_info_table_type_15, "Type 15" }, + {nand_device_info_table_type_16, "Type 16" }, + {nand_device_info_table_bch_ecc12, "BCH ECC12"}, + {nand_device_info_table_bch_ecc24, "BCH ECC24"}, + {0, 0}, +}; + +/** + * struct nand_device_mfr_info - Information about a NAND Flash manufacturer. + * + * @id: The value of the first NAND Flash ID byte, which identifies the + * manufacturer. + * @fn: A pointer to a function to use for identifying devices from the + * given manufacturer. + */ + +struct nand_device_mfr_info { + uint8_t id; + struct nand_device_info *(*fn)(const uint8_t id[]); +}; + +/* + * A table that maps manufacturer IDs to device information tables. + */ + +static struct nand_device_mfr_info nand_device_mfr_directory[] __initdata = { + { + .id = NAND_MFR_TOSHIBA, + .fn = nand_device_info_fn_toshiba, + }, + { + .id = NAND_MFR_SAMSUNG, + .fn = nand_device_info_fn_samsung, + }, + { + .id = NAND_MFR_FUJITSU, + .fn = 0, + }, + { + .id = NAND_MFR_NATIONAL, + .fn = 0, + }, + { + .id = NAND_MFR_RENESAS, + .fn = 0, + }, + { + .id = NAND_MFR_STMICRO, + .fn = nand_device_info_fn_stmicro, + }, + { + .id = NAND_MFR_HYNIX, + .fn = nand_device_info_fn_hynix, + }, + { + .id = NAND_MFR_MICRON, + .fn = nand_device_info_fn_micron, + }, + { + .id = NAND_MFR_AMD, + .fn = 0, + }, + { + .id = NAND_MFR_SANDISK, + .fn = nand_device_info_fn_sandisk, + }, + { + .id = NAND_MFR_INTEL, + .fn = nand_device_info_fn_intel, + }, + {0, 0} +}; + +/** + * nand_device_info_test_table - Validate a device info table. + * + * This function runs tests on the given device info table to check that it + * meets the current assumptions. + */ + +static void __init nand_device_info_test_table( + struct nand_device_info *table, const char *name) +{ + unsigned i; + unsigned j; + uint8_t mfr_code; + uint8_t device_code; + + /* Loop over entries in this table. */ + + for (i = 0; !table[i].end_of_table; i++) { + + /* Get discriminating attributes of the current device. */ + + mfr_code = table[i].manufacturer_code; + device_code = table[i].device_code; + + /* Compare with the remaining devices in this table. */ + + for (j = i + 1; !table[j].end_of_table; j++) { + if ((mfr_code == table[j].manufacturer_code) && + (device_code == table[j].device_code)) + goto error; + } + + } + + return; + +error: + + printk(KERN_EMERG + "\n== NAND Flash device info table failed validity check ==\n"); + + printk(KERN_EMERG "\nDevice Info Table: %s\n", name); + printk(KERN_EMERG "\nTable Index %u\n", i); + nand_device_print_info(table + i); + printk(KERN_EMERG "\nTable Index %u\n", j); + nand_device_print_info(table + j); + printk(KERN_EMERG "\n"); + + BUG(); + +} + +/** + * nand_device_info_test_data - Test the NAND Flash device data. + */ + +static void __init nand_device_info_test_data(void) +{ + + unsigned i; + + for (i = 0; nand_device_type_directory[i].name; i++) { + nand_device_info_test_table( + nand_device_type_directory[i].table, + nand_device_type_directory[i].name); + } + +} + +struct nand_device_info * __init nand_device_get_info(const uint8_t id[]) +{ + unsigned i; + uint8_t mfr_id = ID_GET_MFR_CODE(id); + struct nand_device_info *(*fn)(const uint8_t id[]) = 0; + + /* Test the data. */ + + nand_device_info_test_data(); + + /* Look for information about this manufacturer. */ + + for (i = 0; nand_device_mfr_directory[i].id; i++) { + if (nand_device_mfr_directory[i].id == mfr_id) { + fn = nand_device_mfr_directory[i].fn; + break; + } + } + + if (!fn) + return 0; + + /* + * If control arrives here, we found both a table of device information, + * and a function we can use to identify the current device. Attempt to + * identify the device and return the result. + */ + + return fn(id); + +} diff --git a/drivers/mtd/nand/nand_device_info.h b/drivers/mtd/nand/nand_device_info.h new file mode 100644 index 000000000000..f74c975b2fb6 --- /dev/null +++ b/drivers/mtd/nand/nand_device_info.h @@ -0,0 +1,152 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __DRIVERS_NAND_DEVICE_INFO_H +#define __DRIVERS_NAND_DEVICE_INFO_H + + /* + * The number of ID bytes to read from the NAND Flash device and hand over to + * the identification system. + */ + +#define NAND_DEVICE_ID_BYTE_COUNT (6) + + /* + * The number of ID bytes to read from the NAND Flash device and hand over to + * the identification system. + */ + +enum nand_device_cell_technology { + NAND_DEVICE_CELL_TECH_SLC = 0, + NAND_DEVICE_CELL_TECH_MLC = 1, +}; + +/** + * struct nand_device_info - Information about a single NAND Flash device. + * + * This structure contains all the *essential* information about a NAND Flash + * device, derived from the device's data sheet. For each manufacturer, we have + * an array of these structures. + * + * @end_of_table: If true, marks the end of a table of device + * information. + * @manufacturer_code: The manufacturer code (1st ID byte) reported by + * the device. + * @device_code: The device code (2nd ID byte) reported by the + * device. + * @is_ddr_ok: Is this nand an ONFI nand or TOGGLE nand ? + * @cell_technology: The storage cell technology. + * @chip_size_in_bytes: The total size of the storage behind a single + * chip select, in bytes. Notice that this is *not* + * necessarily the total size of the storage in a + * *package*, which may contain several chips. + * @block_size_in_pages: The number of pages in a block. + * @page_total_size_in_bytes: The total size of a page, in bytes, including + * both the data and the OOB. + * @ecc_strength_in_bits: The strength of the ECC called for by the + * manufacturer, in number of correctable bits. + * @ecc_size_in_bytes: The size of the data block over which the + * manufacturer calls for the given ECC algorithm + * and strength. + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the + * maximum of tDS and tWP. A negative value + * indicates this characteristic isn't known. + * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the + * maximum of tDH, tWH and tREH. A negative value + * indicates this characteristic isn't known. + * @address_setup_in_ns: The address setup time, in nanoseconds. Usually + * the maximum of tCLS, tCS and tALS. A negative + * value indicates this characteristic isn't known. + * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative + * value indicates this characteristic isn't known. + * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A + * negative value indicates this characteristic + * isn't known. + */ + +struct nand_device_info { + + /* End of table marker */ + + bool end_of_table; + + /* Manufacturer and Device codes */ + + uint8_t manufacturer_code; + uint8_t device_code; + + /* Does the nand support DDR? (ONFI or TOGGLE) */ + bool is_ddr_ok; + + /* Technology */ + + enum nand_device_cell_technology cell_technology; + + /* Geometry */ + + uint64_t chip_size_in_bytes; + uint32_t block_size_in_pages; + uint16_t page_total_size_in_bytes; + + /* ECC */ + + uint8_t ecc_strength_in_bits; + uint16_t ecc_size_in_bytes; + + /* Timing */ + + int8_t data_setup_in_ns; + int8_t data_hold_in_ns; + int8_t address_setup_in_ns; + int8_t gpmi_sample_delay_in_ns; + int8_t tREA_in_ns; + int8_t tRLOH_in_ns; + int8_t tRHOH_in_ns; + + /* Description */ + + const char *description; + +}; + +/** + * nand_device_get_info - Get info about a device based on ID bytes. + * + * @id_bytes: An array of NAND_DEVICE_ID_BYTE_COUNT ID bytes retrieved from the + * NAND Flash device. + */ + +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]); + +/** + * nand_device_print_info - Prints information about a NAND Flash device. + * + * @info A pointer to a NAND Flash device information structure. + */ + +void nand_device_print_info(struct nand_device_info *info); + +/* + * Check the NAND whether it supports the DDR mode. + * Only the ONFI nand and TOGGLE nand support the DDR now. + */ +static inline bool is_ddr_nand(struct nand_device_info *info) +{ + return info->is_ddr_ok; +} +#endif diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 89907ed99009..241c73b7328a 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -109,6 +109,10 @@ struct nand_flash_dev nand_flash_ids[] = { {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS}, {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, + {"NAND 2GiB 3,3V 8-bit", 0x48, 0, 2048, 0, LP_OPTIONS}, + + /* 32 Gigabit ,only use 2G due to the linux mtd limitation*/ + {"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 2048, 0, LP_OPTIONS}, /* * Renesas AND 1 Gigabit. Those chips do not support extended id and @@ -125,6 +129,7 @@ struct nand_flash_dev nand_flash_ids[] = { BBT_AUTO_REFRESH }, + {"ONFI NAND 3,3V 8-bit", 0x88, 0, 2048, 0, 0 /*LP_OPTIONS*/ }, {NULL,} }; @@ -141,6 +146,8 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_HYNIX, "Hynix"}, {NAND_MFR_MICRON, "Micron"}, {NAND_MFR_AMD, "AMD"}, + {NAND_MFR_SANDISK, "SanDisk"}, + {NAND_MFR_INTEL, "Intel"}, {0x0, "Unknown"} }; diff --git a/drivers/mtd/ubiblock.c b/drivers/mtd/ubiblock.c new file mode 100644 index 000000000000..d71c1f800d09 --- /dev/null +++ b/drivers/mtd/ubiblock.c @@ -0,0 +1,626 @@ +/* + * Direct UBI block device access + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Based on mtdblock by: + * (C) 2000-2003 Nicolas Pitre + * (C) 1999-2003 David Woodhouse + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ubi/ubi.h" +#include "mtdcore.h" + +static LIST_HEAD(ubiblk_devices); +static struct mutex ubiblk_devices_lock; + +/** + * ubiblk_dev - the structure representing translation layer + * + * @m: interface to mtd_blktrans + * @ubi_num: UBI device number + * @ubi_vol: UBI volume ID + * @usecount: reference count + * + * @cache_mutex: protects access to cache_data + * @cache_data: content of the cached LEB + * @cache_offset: offset of cached data on UBI volume, in bytes + * @cache_size: cache size in bytes, usually equal to LEB size + */ +struct ubiblk_dev { + struct mtd_blktrans_dev *m; + + int ubi_num; + int ubi_vol; + int usecount; + struct ubi_volume_desc *ubi; + + struct mutex cache_mutex; + unsigned char *cache_data; + unsigned long cache_offset; + unsigned int cache_size; + + enum { + STATE_EMPTY, + STATE_CLEAN, + STATE_DIRTY + } cache_state; + + struct list_head list; + + struct work_struct unbind; +}; + +static int ubiblock_open(struct mtd_blktrans_dev *mbd); +static int ubiblock_release(struct mtd_blktrans_dev *mbd); +static int ubiblock_flush(struct mtd_blktrans_dev *mbd); +static int ubiblock_readsect(struct mtd_blktrans_dev *mbd, + unsigned long block, char *buf); +static int ubiblock_writesect(struct mtd_blktrans_dev *mbd, + unsigned long block, char *buf); +static int ubiblock_getgeo(struct mtd_blktrans_dev *mbd, + struct hd_geometry *geo); +static void *ubiblk_add(int ubi_num, int ubi_vol_id); +static void *ubiblk_add_locked(int ubi_num, int ubi_vol_id); +static int ubiblk_del(struct ubiblk_dev *u); +static int ubiblk_del_locked(struct ubiblk_dev *u); + +/* + * These two routines are just to satify mtd_blkdev's requirements + */ +static void ubiblock_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd) +{ + return; +} + +static void ubiblock_remove_dev(struct mtd_blktrans_dev *mbd) +{ + return; +} + +static struct mtd_blktrans_ops ubiblock_tr = { + + .name = "ubiblk", + .major = 0, /* assign dynamically */ + .part_bits = 3, /* allow up to 8 parts */ + .blksize = 512, + + .open = ubiblock_open, + .release = ubiblock_release, + .flush = ubiblock_flush, + .readsect = ubiblock_readsect, + .writesect = ubiblock_writesect, + .getgeo = ubiblock_getgeo, + + .add_mtd = ubiblock_add_mtd, + .remove_dev = ubiblock_remove_dev, + .owner = THIS_MODULE, +}; + +static int ubiblock_getgeo(struct mtd_blktrans_dev *bdev, + struct hd_geometry *geo) +{ + return -ENOTTY; +} + +/** + * ubiblk_write_cached_data - flush the cache to the UBI volume + */ +static int ubiblk_write_cached_data(struct ubiblk_dev *u) +{ + int ret; + + if (u->cache_state != STATE_DIRTY) + return 0; + + pr_debug("%s: volume %d:%d, writing at %lx of size %x\n", + __func__, u->ubi_num, u->ubi_vol, + u->cache_offset, u->cache_size); + + ret = ubi_write(u->ubi, u->cache_offset / u->cache_size, + u->cache_data, 0, u->cache_size); + pr_debug("leb_write status %d\n", ret); + + u->cache_state = STATE_EMPTY; + return ret; +} + +/** + * ubiblk_do_cached_write - cached write the data to the UBI volume + * + * @u: ubiblk_dev + * @pos: offset on the block device + * @len: buffer length + * @buf: buffer itself + * + * if buffer contains one or more whole sectors (=LEBs), write them to the + * volume. Otherwise, fill the cache that will be flushed later + */ +static int ubiblk_do_cached_write(struct ubiblk_dev *u, unsigned long pos, + int len, const char *buf) +{ + unsigned int sect_size = u->cache_size, + size, offset; + unsigned long sect_start; + int ret = 0; + int leb; + + pr_debug("%s: volume %d:%d, writing at pos %lx of size %x\n", + __func__, u->ubi_num, u->ubi_vol, pos, len); + + while (len > 0) { + leb = pos / sect_size; + sect_start = leb * sect_size; + offset = pos - sect_start; + size = sect_size - offset; + + if (size > len) + size = len; + + if (size == sect_size) { + /* + * We are covering a whole sector. Thus there is no + * need to bother with the cache while it may still be + * useful for other partial writes. + */ + ret = ubi_leb_change(u->ubi, leb, + buf, size, UBI_UNKNOWN); + if (ret) + goto out; + } else { + /* Partial sector: need to use the cache */ + + if (u->cache_state == STATE_DIRTY && + u->cache_offset != sect_start) { + ret = ubiblk_write_cached_data(u); + if (ret) + goto out; + } + + if (u->cache_state == STATE_EMPTY || + u->cache_offset != sect_start) { + /* fill the cache with the current sector */ + u->cache_state = STATE_EMPTY; + ret = ubi_leb_read(u->ubi, leb, + u->cache_data, 0, u->cache_size, 0); + if (ret) + return ret; + ret = ubi_leb_unmap(u->ubi, leb); + if (ret) + return ret; + ret = ubi_leb_unmap(u->ubi, leb); + if (ret) + return ret; + u->cache_offset = sect_start; + u->cache_state = STATE_CLEAN; + } + + /* write data to our local cache */ + memcpy(u->cache_data + offset, buf, size); + u->cache_state = STATE_DIRTY; + } + + buf += size; + pos += size; + len -= size; + } + +out: + return ret; +} + +/** + * ubiblk_do_cached_read - cached read the data from ubi volume + * + * @u: ubiblk_dev + * @pos: offset on the block device + * @len: buffer length + * @buf: preallocated buffer + * + * Cached LEB will be used if possible; otherwise data will be using + * ubi_leb_read + */ +static int ubiblk_do_cached_read(struct ubiblk_dev *u, unsigned long pos, + int len, char *buf) +{ + unsigned int sect_size = u->cache_size; + int err = 0; + unsigned long sect_start; + unsigned offset, size; + int leb; + + pr_debug("%s: read at 0x%lx, size 0x%x\n", + __func__, pos, len); + + while (len > 0) { + + leb = pos/sect_size; + sect_start = leb*sect_size; + offset = pos - sect_start; + size = sect_size - offset; + + if (size > len) + size = len; + + /* + * Check if the requested data is already cached + * Read the requested amount of data from our internal + * cache if it contains what we want, otherwise we read + * the data directly from flash. + */ + if (u->cache_state != STATE_EMPTY && + u->cache_offset == sect_start) { + pr_debug("%s: cached, returning back from cache\n", + __func__); + memcpy(buf, u->cache_data + offset, size); + err = 0; + } else { + pr_debug("%s: pos = %ld, reading leb = %d\n", + __func__, pos, leb); + err = ubi_leb_read(u->ubi, leb, buf, offset, size, 0); + if (err) + goto out; + } + + buf += size; + pos += size; + len -= size; + } + +out: + return err; +} + +static struct ubiblk_dev *ubiblk_find_by_ptr(struct mtd_blktrans_dev *m) +{ + struct ubiblk_dev *pos; + + mutex_lock(&ubiblk_devices_lock); + list_for_each_entry(pos, &ubiblk_devices, list) + if (pos->m == m) { + mutex_unlock(&ubiblk_devices_lock); + return pos; + } + mutex_unlock(&ubiblk_devices_lock); + BUG(); + return NULL; +} + +/** + * ubiblock_writesect - write the sector + * + * Allocate the cache, if necessary and perform actual write using + * ubiblk_do_cached_write + */ +static int ubiblock_writesect(struct mtd_blktrans_dev *mbd, + unsigned long block, char *buf) +{ + struct ubiblk_dev *u = ubiblk_find_by_ptr(mbd); + + if (unlikely(!u->cache_data)) { + u->cache_data = vmalloc(u->cache_size); + if (!u->cache_data) + return -EAGAIN; + } + return ubiblk_do_cached_write(u, block<<9, 512, buf); +} + +/** + * ubiblk_readsect - read the sector + * + * Allocate the cache, if necessary, and perform actual read using + * ubiblk_do_cached_read + */ +static int ubiblock_readsect(struct mtd_blktrans_dev *mbd, + unsigned long block, char *buf) +{ + struct ubiblk_dev *u = ubiblk_find_by_ptr(mbd); + + if (unlikely(!u->cache_data)) { + u->cache_data = vmalloc(u->cache_size); + if (!u->cache_data) + return -EAGAIN; + } + return ubiblk_do_cached_read(u, block<<9, 512, buf); +} + +static int ubiblk_flush_locked(struct ubiblk_dev *u) +{ + ubiblk_write_cached_data(u); + ubi_sync(u->ubi_num); + return 0; +} + +static int ubiblock_flush(struct mtd_blktrans_dev *mbd) +{ + struct ubiblk_dev *u = ubiblk_find_by_ptr(mbd); + + mutex_lock(&u->cache_mutex); + ubiblk_flush_locked(u); + mutex_unlock(&u->cache_mutex); + return 0; +} + + +static int ubiblock_open(struct mtd_blktrans_dev *mbd) +{ + struct ubiblk_dev *u = ubiblk_find_by_ptr(mbd); + + if (u->usecount == 0) { + u->ubi = ubi_open_volume(u->ubi_num, u->ubi_vol, + UBI_READWRITE); + if (IS_ERR(u->ubi)) + return PTR_ERR(u->ubi); + } + u->usecount++; + return 0; +} + +static int ubiblock_release(struct mtd_blktrans_dev *mbd) +{ + struct ubiblk_dev *u = ubiblk_find_by_ptr(mbd); + + if (--u->usecount == 0) { + mutex_lock(&u->cache_mutex); + ubiblk_flush_locked(u); + vfree(u->cache_data); + u->cache_data = NULL; + mutex_unlock(&u->cache_mutex); + ubi_close_volume(u->ubi); + u->ubi = NULL; + } + return 0; +} + + +/* + * sysfs routines. The ubiblk creates two entries under /sys/block/ubiblkX: + * - volume, R/O, which is read like "ubi0:volume_name" + * - unbind, W/O; when user writes something here, the block device is + * removed + * + * unbind schedules a work item to perform real unbind, because sysfs entry + * handler cannot delete itself :) + */ +ssize_t volume_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gendisk *gd = dev_to_disk(dev); + struct mtd_blktrans_dev *m = gd->private_data; + struct ubiblk_dev *u = ubiblk_find_by_ptr(m); + + return sprintf(buf, "%d:%d\n", u->ubi_num, u->ubi_vol); +} + +static void ubiblk_unbind(struct work_struct *ws) +{ + struct ubiblk_dev *u = container_of(ws, struct ubiblk_dev, unbind); + + ubiblk_del(u); +} + +ssize_t unbind_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct gendisk *gd = dev_to_disk(dev); + struct mtd_blktrans_dev *m = gd->private_data; + struct ubiblk_dev *u = ubiblk_find_by_ptr(m); + + INIT_WORK(&u->unbind, ubiblk_unbind); + schedule_work(&u->unbind); + return count; +} + +DEVICE_ATTR(unbind, 0644, NULL, unbind_store); +DEVICE_ATTR(volume, 0644, volume_show, NULL); + +static int ubiblk_sysfs(struct gendisk *hd, int add) +{ + int r = 0; + + if (add) { + r = device_create_file(disk_to_dev(hd), &dev_attr_unbind); + if (r < 0) + goto out; + r = device_create_file(disk_to_dev(hd), &dev_attr_volume); + if (r < 0) + goto out1; + return 0; + } + + device_remove_file(disk_to_dev(hd), &dev_attr_unbind); +out1: + device_remove_file(disk_to_dev(hd), &dev_attr_volume); +out: + return r; +} + + +/** + * add the FTL by registering it with mtd_blkdevs + */ +static void *ubiblk_add(int ubi_num, int ubi_vol_id) +{ + void *p; + + mutex_lock(&mtd_table_mutex); + p = ubiblk_add_locked(ubi_num, ubi_vol_id); + mutex_unlock(&mtd_table_mutex); + return p; +} + +static void *ubiblk_add_locked(int ubi_num, int ubi_vol_id) +{ + struct ubiblk_dev *u = kzalloc(sizeof(*u), GFP_KERNEL); + struct ubi_volume_info uvi; + struct ubi_volume_desc *ubi; + + if (!u) { + u = ERR_PTR(-ENOMEM); + goto out; + } + u->m = kzalloc(sizeof(struct mtd_blktrans_dev), GFP_KERNEL); + if (!u->m) { + kfree(u); + u = ERR_PTR(-ENOMEM); + goto out; + } + + ubi = ubi_open_volume(ubi_num, ubi_vol_id, UBI_READONLY); + if (IS_ERR(ubi)) { + pr_err("cannot open the volume\n"); + kfree(u->m); + kfree(u); + u = (void *)ubi; + goto out; + } + + ubi_get_volume_info(ubi, &uvi); + + pr_debug("adding volume of size %d (used_size %lld), LEB size %d\n", + uvi.size, uvi.used_bytes, uvi.usable_leb_size); + + u->m->mtd = ubi->vol->ubi->mtd; + u->m->devnum = -1; + u->m->size = uvi.used_bytes >> 9; + u->m->tr = &ubiblock_tr; + + ubi_close_volume(ubi); + + u->ubi_num = ubi_num; + u->ubi_vol = ubi_vol_id; + + mutex_init(&u->cache_mutex); + u->cache_state = STATE_EMPTY; + u->cache_size = uvi.usable_leb_size; + u->cache_data = NULL; + u->usecount = 0; + INIT_LIST_HEAD(&u->list); + + mutex_lock(&ubiblk_devices_lock); + list_add_tail(&u->list, &ubiblk_devices); + mutex_unlock(&ubiblk_devices_lock); + add_mtd_blktrans_dev(u->m); + ubiblk_sysfs(u->m->disk, true); +out: + return u; +} + +static int ubiblk_del(struct ubiblk_dev *u) +{ + int r; + mutex_lock(&mtd_table_mutex); + r = ubiblk_del_locked(u); + mutex_unlock(&mtd_table_mutex); + return r; +} + +static int ubiblk_del_locked(struct ubiblk_dev *u) +{ + if (u->usecount != 0) + return -EBUSY; + ubiblk_sysfs(u->m->disk, false); + del_mtd_blktrans_dev(u->m); + + mutex_lock(&ubiblk_devices_lock); + list_del(&u->list); + mutex_unlock(&ubiblk_devices_lock); + + BUG_ON(u->cache_data != NULL); /* who did not free the cache ?! */ + kfree(u); + return 0; +} + +static struct ubiblk_dev *ubiblk_find(int num, int vol) +{ + struct ubiblk_dev *pos; + + mutex_lock(&ubiblk_devices_lock); + list_for_each_entry(pos, &ubiblk_devices, list) + if (pos->ubi_num == num && pos->ubi_vol == vol) { + mutex_unlock(&ubiblk_devices_lock); + return pos; + } + mutex_unlock(&ubiblk_devices_lock); + return NULL; +} + +static int ubiblock_notification(struct notifier_block *blk, + unsigned long type, void *v) +{ + struct ubi_notification *nt = v; + struct ubiblk_dev *u; + + switch (type) { + case UBI_VOLUME_ADDED: + ubiblk_add(nt->vi.ubi_num, nt->vi.vol_id); + break; + case UBI_VOLUME_REMOVED: + u = ubiblk_find(nt->vi.ubi_num, nt->vi.vol_id); + if (u) + ubiblk_del(u); + break; + case UBI_VOLUME_RENAMED: + case UBI_VOLUME_RESIZED: + break; + } + return NOTIFY_OK; +} + +static struct notifier_block ubiblock_nb = { + .notifier_call = ubiblock_notification, +}; + +static int __init ubiblock_init(void) +{ + int r; + + mutex_init(&ubiblk_devices_lock); + r = register_mtd_blktrans(&ubiblock_tr); + if (r) + goto out; + r = ubi_register_volume_notifier(&ubiblock_nb, 0); + if (r) + goto out_unreg; + return 0; + +out_unreg: + deregister_mtd_blktrans(&ubiblock_tr); +out: + return 0; +} + +static void __exit ubiblock_exit(void) +{ + ubi_unregister_volume_notifier(&ubiblock_nb); + deregister_mtd_blktrans(&ubiblock_tr); +} + +module_init(ubiblock_init); +module_exit(ubiblock_exit); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Caching block device emulation access to UBI devices"); +MODULE_AUTHOR("dmitry pervushin "); diff --git a/drivers/mxc/Kconfig b/drivers/mxc/Kconfig new file mode 100644 index 000000000000..b26c1dc11ad6 --- /dev/null +++ b/drivers/mxc/Kconfig @@ -0,0 +1,40 @@ +# drivers/video/mxc/Kconfig + +if ARCH_MXC + +menu "MXC support drivers" + +config MXC_IPU + bool "Image Processing Unit Driver" + depends on !ARCH_MX21 + depends on !ARCH_MX27 + depends on !ARCH_MX25 + select MXC_IPU_V1 if !ARCH_MX37 && !ARCH_MX5 + select MXC_IPU_V3 if ARCH_MX37 || ARCH_MX5 + select MXC_IPU_V3D if ARCH_MX37 + select MXC_IPU_V3EX if ARCH_MX5 + help + If you plan to use the Image Processing unit, say + Y here. IPU is needed by Framebuffer and V4L2 drivers. + +source "drivers/mxc/ipu/Kconfig" +source "drivers/mxc/ipu3/Kconfig" + +source "drivers/mxc/ssi/Kconfig" +source "drivers/mxc/dam/Kconfig" +source "drivers/mxc/pmic/Kconfig" +source "drivers/mxc/mcu_pmic/Kconfig" +source "drivers/mxc/security/Kconfig" +source "drivers/mxc/hmp4e/Kconfig" +source "drivers/mxc/hw_event/Kconfig" +source "drivers/mxc/vpu/Kconfig" +source "drivers/mxc/asrc/Kconfig" +source "drivers/mxc/bt/Kconfig" +source "drivers/mxc/gps_ioctrl/Kconfig" +source "drivers/mxc/mlb/Kconfig" +source "drivers/mxc/adc/Kconfig" +source "drivers/mxc/amd-gpu/Kconfig" + +endmenu + +endif diff --git a/drivers/mxc/Makefile b/drivers/mxc/Makefile new file mode 100644 index 000000000000..873bd37c9055 --- /dev/null +++ b/drivers/mxc/Makefile @@ -0,0 +1,18 @@ +obj-$(CONFIG_MXC_IPU_V1) += ipu/ +obj-$(CONFIG_MXC_IPU_V3) += ipu3/ +obj-$(CONFIG_MXC_SSI) += ssi/ +obj-$(CONFIG_MXC_DAM) += dam/ + +obj-$(CONFIG_MXC_PMIC_MC9SDZ60) += mcu_pmic/ +obj-$(CONFIG_MXC_PMIC) += pmic/ + +obj-$(CONFIG_MXC_HMP4E) += hmp4e/ +obj-y += security/ +obj-$(CONFIG_MXC_VPU) += vpu/ +obj-$(CONFIG_MXC_HWEVENT) += hw_event/ +obj-$(CONFIG_MXC_ASRC) += asrc/ +obj-$(CONFIG_MXC_BLUETOOTH) += bt/ +obj-$(CONFIG_GPS_IOCTRL) += gps_ioctrl/ +obj-$(CONFIG_MXC_MLB) += mlb/ +obj-$(CONFIG_IMX_ADC) += adc/ +obj-$(CONFIG_MXC_AMD_GPU) += amd-gpu/ diff --git a/drivers/mxc/adc/Kconfig b/drivers/mxc/adc/Kconfig new file mode 100644 index 000000000000..91ad23bc7cbe --- /dev/null +++ b/drivers/mxc/adc/Kconfig @@ -0,0 +1,14 @@ +# +# i.MX ADC devices +# + +menu "i.MX ADC support" + +config IMX_ADC + tristate "i.MX ADC" + depends on ARCH_MXC + default n + help + This selects the Freescale i.MX on-chip ADC driver. + +endmenu diff --git a/drivers/mxc/adc/Makefile b/drivers/mxc/adc/Makefile new file mode 100644 index 000000000000..e21e48ee1185 --- /dev/null +++ b/drivers/mxc/adc/Makefile @@ -0,0 +1,4 @@ +# +# Makefile for i.MX adc devices. +# +obj-$(CONFIG_IMX_ADC) += imx_adc.o diff --git a/drivers/mxc/adc/imx_adc.c b/drivers/mxc/adc/imx_adc.c new file mode 100644 index 000000000000..56538e79e2a0 --- /dev/null +++ b/drivers/mxc/adc/imx_adc.c @@ -0,0 +1,1134 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file adc/imx_adc.c + * @brief This is the main file of i.MX ADC driver. + * + * @ingroup IMX_ADC + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "imx_adc_reg.h" + +static int imx_adc_major; + +/*! + * Number of users waiting in suspendq + */ +static int swait; + +/*! + * To indicate whether any of the adc devices are suspending + */ +static int suspend_flag; + +/*! + * The suspendq is used by blocking application calls + */ +static wait_queue_head_t suspendq; +static wait_queue_head_t tsq; + +static bool imx_adc_ready; +static bool ts_data_ready; +static int tsi_data = TSI_DATA; +static unsigned short ts_data_buf[16]; + +static struct class *imx_adc_class; +static struct imx_adc_data *adc_data; + +static DECLARE_MUTEX(general_convert_mutex); +static DECLARE_MUTEX(ts_convert_mutex); + +unsigned long tsc_base; + +int is_imx_adc_ready(void) +{ + return imx_adc_ready; +} +EXPORT_SYMBOL(is_imx_adc_ready); + +void tsc_clk_enable(void) +{ + unsigned long reg; + + clk_enable(adc_data->adc_clk); + + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_IPG_CLK_EN; + __raw_writel(reg, tsc_base + TGCR); +} + +void tsc_clk_disable(void) +{ + unsigned long reg; + + clk_disable(adc_data->adc_clk); + + reg = __raw_readl(tsc_base + TGCR); + reg &= ~TGCR_IPG_CLK_EN; + __raw_writel(reg, tsc_base + TGCR); +} + +void tsc_self_reset(void) +{ + unsigned long reg; + + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_TSC_RST; + __raw_writel(reg, tsc_base + TGCR); + + while (__raw_readl(tsc_base + TGCR) & TGCR_TSC_RST) + continue; +} + +/* Internal reference */ +void tsc_intref_enable(void) +{ + unsigned long reg; + + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_INTREFEN; + __raw_writel(reg, tsc_base + TGCR); +} + +/* initialize touchscreen */ +void imx_tsc_init(void) +{ + unsigned long reg; + int lastitemid; + + /* Level sense */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_PD_CFG; /* edge sensitive */ + reg |= (0xf << CQCR_FIFOWATERMARK_SHIFT); /* watermark */ + __raw_writel(reg, tsc_base + TCQCR); + + /* Configure 4-wire */ + reg = TSC_4WIRE_PRECHARGE; + reg |= CC_IGS; + __raw_writel(reg, tsc_base + TCC0); + + reg = TSC_4WIRE_TOUCH_DETECT; + reg |= 3 << CC_NOS_SHIFT; /* 4 samples */ + reg |= 32 << CC_SETTLING_TIME_SHIFT; /* it's important! */ + __raw_writel(reg, tsc_base + TCC1); + + reg = TSC_4WIRE_X_MEASUMENT; + reg |= 3 << CC_NOS_SHIFT; /* 4 samples */ + reg |= 16 << CC_SETTLING_TIME_SHIFT; /* settling time */ + __raw_writel(reg, tsc_base + TCC2); + + reg = TSC_4WIRE_Y_MEASUMENT; + reg |= 3 << CC_NOS_SHIFT; /* 4 samples */ + reg |= 16 << CC_SETTLING_TIME_SHIFT; /* settling time */ + __raw_writel(reg, tsc_base + TCC3); + + reg = (TCQ_ITEM_TCC0 << TCQ_ITEM7_SHIFT) | + (TCQ_ITEM_TCC0 << TCQ_ITEM6_SHIFT) | + (TCQ_ITEM_TCC1 << TCQ_ITEM5_SHIFT) | + (TCQ_ITEM_TCC0 << TCQ_ITEM4_SHIFT) | + (TCQ_ITEM_TCC3 << TCQ_ITEM3_SHIFT) | + (TCQ_ITEM_TCC2 << TCQ_ITEM2_SHIFT) | + (TCQ_ITEM_TCC1 << TCQ_ITEM1_SHIFT) | + (TCQ_ITEM_TCC0 << TCQ_ITEM0_SHIFT); + __raw_writel(reg, tsc_base + TCQ_ITEM_7_0); + + lastitemid = 5; + reg = __raw_readl(tsc_base + TCQCR); + reg = (reg & ~CQCR_LAST_ITEM_ID_MASK) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT); + __raw_writel(reg, tsc_base + TCQCR); + + /* Config idle for 4-wire */ + reg = TSC_4WIRE_PRECHARGE; + __raw_writel(reg, tsc_base + TICR); + + reg = TSC_4WIRE_TOUCH_DETECT; + __raw_writel(reg, tsc_base + TICR); + + /* pen down mask */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_PD_MSK; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TCQMR); + reg &= ~TCQMR_PD_IRQ_MSK; + __raw_writel(reg, tsc_base + TCQMR); + + /* Debounce time = dbtime*8 adc clock cycles */ + reg = __raw_readl(tsc_base + TGCR); + reg &= ~TGCR_PDBTIME_MASK; + reg |= TGCR_PDBTIME128 | TGCR_HSYNC_EN; + __raw_writel(reg, tsc_base + TGCR); + + /* pen down enable */ + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_PDB_EN; + __raw_writel(reg, tsc_base + TGCR); + reg |= TGCR_PD_EN; + __raw_writel(reg, tsc_base + TGCR); +} + +static irqreturn_t imx_adc_interrupt(int irq, void *dev_id) +{ + unsigned long reg; + + if (__raw_readl(tsc_base + TGSR) & 0x4) { + /* deep sleep wakeup interrupt */ + /* clear tgsr */ + __raw_writel(0, tsc_base + TGSR); + /* clear deep sleep wakeup irq */ + reg = __raw_readl(tsc_base + TGCR); + reg &= ~TGCR_SLPC; + __raw_writel(reg, tsc_base + TGCR); + /* un-mask pen down and pen down irq */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_PD_MSK; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TCQMR); + reg &= ~TCQMR_PD_IRQ_MSK; + __raw_writel(reg, tsc_base + TCQMR); + } else if ((__raw_readl(tsc_base + TGSR) & 0x1) && + (__raw_readl(tsc_base + TCQSR) & 0x1)) { + + /* mask pen down detect irq */ + reg = __raw_readl(tsc_base + TCQMR); + reg |= TCQMR_PD_IRQ_MSK; + __raw_writel(reg, tsc_base + TCQMR); + + ts_data_ready = 1; + wake_up_interruptible(&tsq); + } + return IRQ_HANDLED; +} + +enum IMX_ADC_STATUS imx_adc_read_general(unsigned short *result) +{ + unsigned long reg; + unsigned int data_num = 0; + + reg = __raw_readl(tsc_base + GCQCR); + reg |= CQCR_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + while (!(__raw_readl(tsc_base + GCQSR) & CQSR_EOQ)) + continue; + reg = __raw_readl(tsc_base + GCQCR); + reg &= ~CQCR_FQS; + __raw_writel(reg, tsc_base + GCQCR); + reg = __raw_readl(tsc_base + GCQSR); + reg |= CQSR_EOQ; + __raw_writel(reg, tsc_base + GCQSR); + + while (!(__raw_readl(tsc_base + GCQSR) & CQSR_EMPT)) { + result[data_num] = __raw_readl(tsc_base + GCQFIFO) >> + GCQFIFO_ADCOUT_SHIFT; + data_num++; + } + return IMX_ADC_SUCCESS; +} + +/*! + * This function will get raw (X,Y) value by converting the voltage + * @param touch_sample Pointer to touch sample + * + * return This funciton returns 0 if successful. + * + * + */ +enum IMX_ADC_STATUS imx_adc_read_ts(struct t_touch_screen *touch_sample, + int wait_tsi) +{ + unsigned long reg; + int data_num = 0; + int detect_sample1, detect_sample2; + + memset(ts_data_buf, 0, sizeof ts_data_buf); + touch_sample->valid_flag = 1; + + if (wait_tsi) { + /* Config idle for 4-wire */ + reg = TSC_4WIRE_TOUCH_DETECT; + __raw_writel(reg, tsc_base + TICR); + + /* Pen interrupt starts new conversion queue */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + reg |= CQCR_QSM_PEN; + __raw_writel(reg, tsc_base + TCQCR); + + /* unmask pen down detect irq */ + reg = __raw_readl(tsc_base + TCQMR); + reg &= ~TCQMR_PD_IRQ_MSK; + __raw_writel(reg, tsc_base + TCQMR); + + wait_event_interruptible(tsq, ts_data_ready); + while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ)) + continue; + + /* stop the conversion */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + __raw_writel(reg, tsc_base + TCQCR); + reg = CQSR_PD | CQSR_EOQ; + __raw_writel(reg, tsc_base + TCQSR); + + /* change configuration for FQS mode */ + tsi_data = TSI_DATA; + reg = (0x1 << CC_YPLLSW_SHIFT) | (0x1 << CC_XNURSW_SHIFT) | + CC_XPULSW; + __raw_writel(reg, tsc_base + TICR); + } else { + /* FQS semaphore */ + down(&ts_convert_mutex); + + reg = (0x1 << CC_YPLLSW_SHIFT) | (0x1 << CC_XNURSW_SHIFT) | + CC_XPULSW; + __raw_writel(reg, tsc_base + TICR); + + /* FQS */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + reg |= CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TCQCR); + reg |= CQCR_FQS; + __raw_writel(reg, tsc_base + TCQCR); + while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EOQ)) + continue; + + /* stop FQS */ + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_FQS; + __raw_writel(reg, tsc_base + TCQCR); + + /* clear status bit */ + reg = __raw_readl(tsc_base + TCQSR); + reg |= CQSR_EOQ; + __raw_writel(reg, tsc_base + TCQSR); + tsi_data = FQS_DATA; + + /* Config idle for 4-wire */ + reg = TSC_4WIRE_PRECHARGE; + __raw_writel(reg, tsc_base + TICR); + + reg = TSC_4WIRE_TOUCH_DETECT; + __raw_writel(reg, tsc_base + TICR); + + } + + while (!(__raw_readl(tsc_base + TCQSR) & CQSR_EMPT)) { + reg = __raw_readl(tsc_base + TCQFIFO); + ts_data_buf[data_num] = reg; + data_num++; + } + + touch_sample->x_position1 = ts_data_buf[4] >> 4; + touch_sample->x_position2 = ts_data_buf[5] >> 4; + touch_sample->x_position3 = ts_data_buf[6] >> 4; + touch_sample->y_position1 = ts_data_buf[9] >> 4; + touch_sample->y_position2 = ts_data_buf[10] >> 4; + touch_sample->y_position3 = ts_data_buf[11] >> 4; + + detect_sample1 = ts_data_buf[0]; + detect_sample2 = ts_data_buf[12]; + + if ((detect_sample1 > 0x6000) || (detect_sample2 > 0x6000)) + touch_sample->valid_flag = 0; + + ts_data_ready = 0; + + if (!(touch_sample->x_position1 || + touch_sample->x_position2 || touch_sample->x_position3)) + touch_sample->contact_resistance = 0; + else + touch_sample->contact_resistance = 1; + + if (tsi_data == FQS_DATA) + up(&ts_convert_mutex); + return IMX_ADC_SUCCESS; +} + +/*! + * This function performs filtering and rejection of excessive noise prone + * sampl. + * + * @param ts_curr Touch screen value + * + * @return This function returns 0 on success, -1 otherwise. + */ +static int imx_adc_filter(struct t_touch_screen *ts_curr) +{ + + unsigned int ydiff1, ydiff2, ydiff3, xdiff1, xdiff2, xdiff3; + unsigned int sample_sumx, sample_sumy; + static unsigned int prev_x[FILTLEN], prev_y[FILTLEN]; + int index = 0; + unsigned int y_curr, x_curr; + static int filt_count; + /* Added a variable filt_type to decide filtering at run-time */ + unsigned int filt_type = 0; + + /* ignore the data converted when pen down and up */ + if ((ts_curr->contact_resistance == 0) || tsi_data == TSI_DATA) { + ts_curr->x_position = 0; + ts_curr->y_position = 0; + filt_count = 0; + return 0; + } + /* ignore the data valid */ + if (ts_curr->valid_flag == 0) + return -1; + + ydiff1 = abs(ts_curr->y_position1 - ts_curr->y_position2); + ydiff2 = abs(ts_curr->y_position2 - ts_curr->y_position3); + ydiff3 = abs(ts_curr->y_position1 - ts_curr->y_position3); + if ((ydiff1 > DELTA_Y_MAX) || + (ydiff2 > DELTA_Y_MAX) || (ydiff3 > DELTA_Y_MAX)) { + pr_debug("imx_adc_filter: Ret pos 1\n"); + return -1; + } + + xdiff1 = abs(ts_curr->x_position1 - ts_curr->x_position2); + xdiff2 = abs(ts_curr->x_position2 - ts_curr->x_position3); + xdiff3 = abs(ts_curr->x_position1 - ts_curr->x_position3); + + if ((xdiff1 > DELTA_X_MAX) || + (xdiff2 > DELTA_X_MAX) || (xdiff3 > DELTA_X_MAX)) { + pr_debug("imx_adc_filter: Ret pos 2\n"); + return -1; + } + /* Compute two closer values among the three available Y readouts */ + + if (ydiff1 < ydiff2) { + if (ydiff1 < ydiff3) { + /* Sample 0 & 1 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position2; + } else { + /* Sample 0 & 2 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position3; + } + } else { + if (ydiff2 < ydiff3) { + /* Sample 1 & 2 closest together */ + sample_sumy = ts_curr->y_position2 + + ts_curr->y_position3; + } else { + /* Sample 0 & 2 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position3; + } + } + + /* + * Compute two closer values among the three available X + * readouts + */ + if (xdiff1 < xdiff2) { + if (xdiff1 < xdiff3) { + /* Sample 0 & 1 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position2; + } else { + /* Sample 0 & 2 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position3; + } + } else { + if (xdiff2 < xdiff3) { + /* Sample 1 & 2 closest together */ + sample_sumx = ts_curr->x_position2 + + ts_curr->x_position3; + } else { + /* Sample 0 & 2 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position3; + } + } + + /* + * Wait FILTER_MIN_DELAY number of samples to restart + * filtering + */ + if (filt_count < FILTER_MIN_DELAY) { + /* + * Current output is the average of the two closer + * values and no filtering is used + */ + y_curr = (sample_sumy / 2); + x_curr = (sample_sumx / 2); + ts_curr->y_position = y_curr; + ts_curr->x_position = x_curr; + filt_count++; + + } else { + if (abs(sample_sumx - (prev_x[0] + prev_x[1])) > + (DELTA_X_MAX * 16)) { + pr_debug("imx_adc_filter: : Ret pos 3\n"); + return -1; + } + if (abs(sample_sumy - (prev_y[0] + prev_y[1])) > + (DELTA_Y_MAX * 16)) { + pr_debug("imx_adc_filter: : Ret pos 4\n"); + return -1; + } + sample_sumy /= 2; + sample_sumx /= 2; + /* Use hard filtering if the sample difference < 10 */ + if ((abs(sample_sumy - prev_y[0]) > 10) || + (abs(sample_sumx - prev_x[0]) > 10)) + filt_type = 1; + + /* + * Current outputs are the average of three previous + * values and the present readout + */ + y_curr = sample_sumy; + for (index = 0; index < FILTLEN; index++) { + if (filt_type == 0) + y_curr = y_curr + (prev_y[index]); + else + y_curr = y_curr + (prev_y[index] / 3); + } + if (filt_type == 0) + y_curr = y_curr >> 2; + else + y_curr = y_curr >> 1; + ts_curr->y_position = y_curr; + + x_curr = sample_sumx; + for (index = 0; index < FILTLEN; index++) { + if (filt_type == 0) + x_curr = x_curr + (prev_x[index]); + else + x_curr = x_curr + (prev_x[index] / 3); + } + if (filt_type == 0) + x_curr = x_curr >> 2; + else + x_curr = x_curr >> 1; + ts_curr->x_position = x_curr; + + } + + /* Update previous X and Y values */ + for (index = (FILTLEN - 1); index > 0; index--) { + prev_x[index] = prev_x[index - 1]; + prev_y[index] = prev_y[index - 1]; + } + + /* + * Current output will be the most recent past for the + * next sample + */ + prev_y[0] = y_curr; + prev_x[0] = x_curr; + + return 0; + +} + +/*! + * This function retrieves the current touch screen (X,Y) coordinates. + * + * @param touch_sample Pointer to touch sample. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_get_touch_sample(struct t_touch_screen + *touch_sample, int wait_tsi) +{ + if (imx_adc_read_ts(touch_sample, wait_tsi)) + return IMX_ADC_ERROR; + if (!imx_adc_filter(touch_sample)) + return IMX_ADC_SUCCESS; + else + return IMX_ADC_ERROR; +} +EXPORT_SYMBOL(imx_adc_get_touch_sample); + +void imx_adc_set_hsync(int on) +{ + unsigned long reg; + if (imx_adc_ready) { + reg = __raw_readl(tsc_base + TGCR); + if (on) + reg |= TGCR_HSYNC_EN; + else + reg &= ~TGCR_HSYNC_EN; + __raw_writel(reg, tsc_base + TGCR); + } +} +EXPORT_SYMBOL(imx_adc_set_hsync); + +/*! + * This is the suspend of power management for the i.MX ADC API. + * It supports SAVE and POWER_DOWN state. + * + * @param pdev the device + * @param state the state + * + * @return This function returns 0 if successful. + */ +static int imx_adc_suspend(struct platform_device *pdev, pm_message_t state) +{ + unsigned long reg; + + /* Config idle for 4-wire */ + reg = TSC_4WIRE_PRECHARGE; + __raw_writel(reg, tsc_base + TICR); + + reg = TSC_4WIRE_TOUCH_DETECT; + __raw_writel(reg, tsc_base + TICR); + + /* enable deep sleep wake up */ + reg = __raw_readl(tsc_base + TGCR); + reg |= TGCR_SLPC; + __raw_writel(reg, tsc_base + TGCR); + + /* mask pen down and pen down irq */ + reg = __raw_readl(tsc_base + TCQCR); + reg |= CQCR_PD_MSK; + __raw_writel(reg, tsc_base + TCQCR); + reg = __raw_readl(tsc_base + TCQMR); + reg |= TCQMR_PD_IRQ_MSK; + __raw_writel(reg, tsc_base + TCQMR); + + /* Set power mode to off */ + reg = __raw_readl(tsc_base + TGCR) & ~TGCR_POWER_MASK; + reg |= TGCR_POWER_OFF; + __raw_writel(reg, tsc_base + TGCR); + + if (device_may_wakeup(&pdev->dev)) { + enable_irq_wake(adc_data->irq); + } else { + suspend_flag = 1; + tsc_clk_disable(); + } + return 0; +}; + +/*! + * This is the resume of power management for the i.MX adc API. + * It supports RESTORE state. + * + * @param pdev the device + * + * @return This function returns 0 if successful. + */ +static int imx_adc_resume(struct platform_device *pdev) +{ + unsigned long reg; + + if (device_may_wakeup(&pdev->dev)) { + disable_irq_wake(adc_data->irq); + } else { + suspend_flag = 0; + tsc_clk_enable(); + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + } + + /* recover power mode */ + reg = __raw_readl(tsc_base + TGCR) & ~TGCR_POWER_MASK; + reg |= TGCR_POWER_SAVE; + __raw_writel(reg, tsc_base + TGCR); + + return 0; +} + +/*! + * This function implements the open method on an i.MX ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int imx_adc_open(struct inode *inode, struct file *file) +{ + while (suspend_flag) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, !suspend_flag)) + return -ERESTARTSYS; + } + pr_debug("imx_adc : imx_adc_open()\n"); + return 0; +} + +/*! + * This function implements the release method on an i.MX ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int imx_adc_free(struct inode *inode, struct file *file) +{ + pr_debug("imx_adc : imx_adc_free()\n"); + return 0; +} + +/*! + * This function initializes all ADC registers with default values. This + * function also registers the interrupt events. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +int imx_adc_init(void) +{ + unsigned long reg; + + pr_debug("imx_adc_init()\n"); + + if (suspend_flag) + return -EBUSY; + + tsc_clk_enable(); + + /* Reset */ + tsc_self_reset(); + + /* Internal reference */ + tsc_intref_enable(); + + /* Set power mode */ + reg = __raw_readl(tsc_base + TGCR) & ~TGCR_POWER_MASK; + reg |= TGCR_POWER_SAVE; + __raw_writel(reg, tsc_base + TGCR); + + imx_tsc_init(); + + return IMX_ADC_SUCCESS; +} +EXPORT_SYMBOL(imx_adc_init); + +/*! + * This function disables the ADC, de-registers the interrupt events. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_deinit(void) +{ + pr_debug("imx_adc_deinit()\n"); + + return IMX_ADC_SUCCESS; +} +EXPORT_SYMBOL(imx_adc_deinit); + +/*! + * This function triggers a conversion and returns one sampling result of one + * channel. + * + * @param channel The channel to be sampled + * @param result The pointer to the conversion result. The memory + * should be allocated by the caller of this function. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_convert(enum t_channel channel, + unsigned short *result) +{ + unsigned long reg; + int lastitemid; + struct t_touch_screen touch_sample; + + switch (channel) { + + case TS_X_POS: + imx_adc_get_touch_sample(&touch_sample, 0); + result[0] = touch_sample.x_position; + + /* if no pen down ,recover the register configuration */ + if (touch_sample.contact_resistance == 0) { + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + reg |= CQCR_QSM_PEN; + __raw_writel(reg, tsc_base + TCQCR); + + reg = __raw_readl(tsc_base + TCQMR); + reg &= ~TCQMR_PD_IRQ_MSK; + __raw_writel(reg, tsc_base + TCQMR); + } + break; + + case TS_Y_POS: + imx_adc_get_touch_sample(&touch_sample, 0); + result[1] = touch_sample.y_position; + + /* if no pen down ,recover the register configuration */ + if (touch_sample.contact_resistance == 0) { + reg = __raw_readl(tsc_base + TCQCR); + reg &= ~CQCR_QSM_MASK; + reg |= CQCR_QSM_PEN; + __raw_writel(reg, tsc_base + TCQCR); + + reg = __raw_readl(tsc_base + TCQMR); + reg &= ~TCQMR_PD_IRQ_MSK; + __raw_writel(reg, tsc_base + TCQMR); + } + break; + + case GER_PURPOSE_ADC0: + down(&general_convert_mutex); + + lastitemid = 0; + reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + reg = TSC_GENERAL_ADC_GCC0; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC0); + + imx_adc_read_general(result); + up(&general_convert_mutex); + break; + + case GER_PURPOSE_ADC1: + down(&general_convert_mutex); + + lastitemid = 0; + reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + reg = TSC_GENERAL_ADC_GCC1; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC0); + + imx_adc_read_general(result); + up(&general_convert_mutex); + break; + + case GER_PURPOSE_ADC2: + down(&general_convert_mutex); + + lastitemid = 0; + reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + reg = TSC_GENERAL_ADC_GCC2; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC0); + + imx_adc_read_general(result); + up(&general_convert_mutex); + break; + + case GER_PURPOSE_MULTICHNNEL: + down(&general_convert_mutex); + + reg = TSC_GENERAL_ADC_GCC0; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC0); + + reg = TSC_GENERAL_ADC_GCC1; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC1); + + reg = TSC_GENERAL_ADC_GCC2; + reg |= (3 << CC_NOS_SHIFT) | (16 << CC_SETTLING_TIME_SHIFT); + __raw_writel(reg, tsc_base + GCC2); + + reg = (GCQ_ITEM_GCC2 << GCQ_ITEM2_SHIFT) | + (GCQ_ITEM_GCC1 << GCQ_ITEM1_SHIFT) | + (GCQ_ITEM_GCC0 << GCQ_ITEM0_SHIFT); + __raw_writel(reg, tsc_base + GCQ_ITEM_7_0); + + lastitemid = 2; + reg = (0xf << CQCR_FIFOWATERMARK_SHIFT) | + (lastitemid << CQCR_LAST_ITEM_ID_SHIFT) | CQCR_QSM_FQS; + __raw_writel(reg, tsc_base + GCQCR); + + imx_adc_read_general(result); + up(&general_convert_mutex); + break; + default: + pr_debug("%s: bad channel number\n", __func__); + return IMX_ADC_ERROR; + } + + return IMX_ADC_SUCCESS; +} +EXPORT_SYMBOL(imx_adc_convert); + +/*! + * This function triggers a conversion and returns sampling results of each + * specified channel. + * + * @param channels This input parameter is bitmap to specify channels + * to be sampled. + * @param result The pointer to array to store sampling results. + * The memory should be allocated by the caller of this + * function. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_convert_multichnnel(enum t_channel channels, + unsigned short *result) +{ + imx_adc_convert(GER_PURPOSE_MULTICHNNEL, result); + return IMX_ADC_SUCCESS; +} +EXPORT_SYMBOL(imx_adc_convert_multichnnel); + +/*! + * This function implements IOCTL controls on an i.MX ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int imx_adc_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct t_adc_convert_param *convert_param; + + if ((_IOC_TYPE(cmd) != 'p') && (_IOC_TYPE(cmd) != 'D')) + return -ENOTTY; + + while (suspend_flag) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, !suspend_flag)) + return -ERESTARTSYS; + } + + switch (cmd) { + case IMX_ADC_INIT: + pr_debug("init adc\n"); + CHECK_ERROR(imx_adc_init()); + break; + + case IMX_ADC_DEINIT: + pr_debug("deinit adc\n"); + CHECK_ERROR(imx_adc_deinit()); + break; + + case IMX_ADC_CONVERT: + convert_param = kmalloc(sizeof(*convert_param), GFP_KERNEL); + if (convert_param == NULL) + return -ENOMEM; + if (copy_from_user(convert_param, + (struct t_adc_convert_param *)arg, + sizeof(*convert_param))) { + kfree(convert_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(imx_adc_convert(convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((struct t_adc_convert_param *)arg, + convert_param, sizeof(*convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + case IMX_ADC_CONVERT_MULTICHANNEL: + convert_param = kmalloc(sizeof(*convert_param), GFP_KERNEL); + if (convert_param == NULL) + return -ENOMEM; + if (copy_from_user(convert_param, + (struct t_adc_convert_param *)arg, + sizeof(*convert_param))) { + kfree(convert_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(imx_adc_convert_multichnnel + (convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((struct t_adc_convert_param *)arg, + convert_param, sizeof(*convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + default: + pr_debug("imx_adc_ioctl: unsupported ioctl command 0x%x\n", + cmd); + return -EINVAL; + } + return 0; +} + +static struct file_operations imx_adc_fops = { + .owner = THIS_MODULE, + .ioctl = imx_adc_ioctl, + .open = imx_adc_open, + .release = imx_adc_free, +}; + +static int imx_adc_module_probe(struct platform_device *pdev) +{ + int ret = 0; + int retval; + struct device *temp_class; + struct resource *res; + void __iomem *base; + + /* ioremap the base address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No TSC base address provided\n"); + goto err_out0; + } + base = ioremap(res->start, res->end - res->start); + if (base == NULL) { + dev_err(&pdev->dev, "failed to rebase TSC base address\n"); + goto err_out0; + } + tsc_base = (unsigned long)base; + + /* create the chrdev */ + imx_adc_major = register_chrdev(0, "imx_adc", &imx_adc_fops); + + if (imx_adc_major < 0) { + dev_err(&pdev->dev, "Unable to get a major for imx_adc\n"); + return imx_adc_major; + } + init_waitqueue_head(&suspendq); + init_waitqueue_head(&tsq); + + imx_adc_class = class_create(THIS_MODULE, "imx_adc"); + if (IS_ERR(imx_adc_class)) { + dev_err(&pdev->dev, "Error creating imx_adc class.\n"); + ret = PTR_ERR(imx_adc_class); + goto err_out1; + } + + temp_class = device_create(imx_adc_class, NULL, + MKDEV(imx_adc_major, 0), NULL, "imx_adc"); + if (IS_ERR(temp_class)) { + dev_err(&pdev->dev, "Error creating imx_adc class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + adc_data = kmalloc(sizeof(struct imx_adc_data), GFP_KERNEL); + if (adc_data == NULL) + return -ENOMEM; + adc_data->irq = platform_get_irq(pdev, 0); + retval = request_irq(adc_data->irq, imx_adc_interrupt, + 0, MOD_NAME, MOD_NAME); + if (retval) { + return retval; + } + adc_data->adc_clk = clk_get(&pdev->dev, "tchscrn_clk"); + + ret = imx_adc_init(); + + if (ret != IMX_ADC_SUCCESS) { + dev_err(&pdev->dev, "Error in imx_adc_init.\n"); + goto err_out4; + } + imx_adc_ready = 1; + + /* By default, devices should wakeup if they can */ + /* So TouchScreen is set as "should wakeup" as it can */ + device_init_wakeup(&pdev->dev, 1); + + pr_info("i.MX ADC at 0x%x irq %d\n", (unsigned int)res->start, + adc_data->irq); + return ret; + +err_out4: + device_destroy(imx_adc_class, MKDEV(imx_adc_major, 0)); +err_out2: + class_destroy(imx_adc_class); +err_out1: + unregister_chrdev(imx_adc_major, "imx_adc"); +err_out0: + return ret; +} + +static int imx_adc_module_remove(struct platform_device *pdev) +{ + imx_adc_ready = 0; + imx_adc_deinit(); + device_destroy(imx_adc_class, MKDEV(imx_adc_major, 0)); + class_destroy(imx_adc_class); + unregister_chrdev(imx_adc_major, "imx_adc"); + free_irq(adc_data->irq, MOD_NAME); + kfree(adc_data); + pr_debug("i.MX ADC successfully removed\n"); + return 0; +} + +static struct platform_driver imx_adc_driver = { + .driver = { + .name = "imx_adc", + }, + .suspend = imx_adc_suspend, + .resume = imx_adc_resume, + .probe = imx_adc_module_probe, + .remove = imx_adc_module_remove, +}; + +/* + * Initialization and Exit + */ +static int __init imx_adc_module_init(void) +{ + pr_debug("i.MX ADC driver loading...\n"); + return platform_driver_register(&imx_adc_driver); +} + +static void __exit imx_adc_module_exit(void) +{ + platform_driver_unregister(&imx_adc_driver); + pr_debug("i.MX ADC driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +module_init(imx_adc_module_init); +module_exit(imx_adc_module_exit); + +MODULE_DESCRIPTION("i.MX ADC device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/adc/imx_adc_reg.h b/drivers/mxc/adc/imx_adc_reg.h new file mode 100644 index 000000000000..71e2d3b21930 --- /dev/null +++ b/drivers/mxc/adc/imx_adc_reg.h @@ -0,0 +1,242 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef __IMX_ADC_H__ +#define __IMX_ADC_H__ + +/* TSC General Config Register */ +#define TGCR 0x000 +#define TGCR_IPG_CLK_EN (1 << 0) +#define TGCR_TSC_RST (1 << 1) +#define TGCR_FUNC_RST (1 << 2) +#define TGCR_SLPC (1 << 4) +#define TGCR_STLC (1 << 5) +#define TGCR_HSYNC_EN (1 << 6) +#define TGCR_HSYNC_POL (1 << 7) +#define TGCR_POWERMODE_SHIFT 8 +#define TGCR_POWER_OFF (0x0 << TGCR_POWERMODE_SHIFT) +#define TGCR_POWER_SAVE (0x1 << TGCR_POWERMODE_SHIFT) +#define TGCR_POWER_ON (0x3 << TGCR_POWERMODE_SHIFT) +#define TGCR_POWER_MASK (0x3 << TGCR_POWERMODE_SHIFT) +#define TGCR_INTREFEN (1 << 10) +#define TGCR_ADCCLKCFG_SHIFT 16 +#define TGCR_PD_EN (1 << 23) +#define TGCR_PDB_EN (1 << 24) +#define TGCR_PDBTIME_SHIFT 25 +#define TGCR_PDBTIME128 (0x3f << TGCR_PDBTIME_SHIFT) +#define TGCR_PDBTIME_MASK (0x7f << TGCR_PDBTIME_SHIFT) + +/* TSC General Status Register */ +#define TGSR 0x004 +#define TCQ_INT (1 << 0) +#define GCQ_INT (1 << 1) +#define SLP_INT (1 << 2) +#define TCQ_DMA (1 << 16) +#define GCQ_DMA (1 << 17) + +/* TSC IDLE Config Register */ +#define TICR 0x008 + +/* TouchScreen Convert Queue FIFO Register */ +#define TCQFIFO 0x400 +/* TouchScreen Convert Queue Control Register */ +#define TCQCR 0x404 +#define CQCR_QSM_SHIFT 0 +#define CQCR_QSM_STOP (0x0 << CQCR_QSM_SHIFT) +#define CQCR_QSM_PEN (0x1 << CQCR_QSM_SHIFT) +#define CQCR_QSM_FQS (0x2 << CQCR_QSM_SHIFT) +#define CQCR_QSM_FQS_PEN (0x3 << CQCR_QSM_SHIFT) +#define CQCR_QSM_MASK (0x3 << CQCR_QSM_SHIFT) +#define CQCR_FQS (1 << 2) +#define CQCR_RPT (1 << 3) +#define CQCR_LAST_ITEM_ID_SHIFT 4 +#define CQCR_LAST_ITEM_ID_MASK (0xf << CQCR_LAST_ITEM_ID_SHIFT) +#define CQCR_FIFOWATERMARK_SHIFT 8 +#define CQCR_FIFOWATERMARK_MASK (0xf << CQCR_FIFOWATERMARK_SHIFT) +#define CQCR_REPEATWAIT_SHIFT 12 +#define CQCR_REPEATWAIT_MASK (0xf << CQCR_REPEATWAIT_SHIFT) +#define CQCR_QRST (1 << 16) +#define CQCR_FRST (1 << 17) +#define CQCR_PD_MSK (1 << 18) +#define CQCR_PD_CFG (1 << 19) + +/* TouchScreen Convert Queue Status Register */ +#define TCQSR 0x408 +#define CQSR_PD (1 << 0) +#define CQSR_EOQ (1 << 1) +#define CQSR_FOR (1 << 4) +#define CQSR_FUR (1 << 5) +#define CQSR_FER (1 << 6) +#define CQSR_EMPT (1 << 13) +#define CQSR_FULL (1 << 14) +#define CQSR_FDRY (1 << 15) + +/* TouchScreen Convert Queue Mask Register */ +#define TCQMR 0x40c +#define TCQMR_PD_IRQ_MSK (1 << 0) +#define TCQMR_EOQ_IRQ_MSK (1 << 1) +#define TCQMR_FOR_IRQ_MSK (1 << 4) +#define TCQMR_FUR_IRQ_MSK (1 << 5) +#define TCQMR_FER_IRQ_MSK (1 << 6) +#define TCQMR_PD_DMA_MSK (1 << 16) +#define TCQMR_EOQ_DMA_MSK (1 << 17) +#define TCQMR_FOR_DMA_MSK (1 << 20) +#define TCQMR_FUR_DMA_MSK (1 << 21) +#define TCQMR_FER_DMA_MSK (1 << 22) +#define TCQMR_FDRY_DMA_MSK (1 << 31) + +/* TouchScreen Convert Queue ITEM 7~0 */ +#define TCQ_ITEM_7_0 0x420 + +/* TouchScreen Convert Queue ITEM 15~8 */ +#define TCQ_ITEM_15_8 0x424 + +#define TCQ_ITEM7_SHIFT 28 +#define TCQ_ITEM6_SHIFT 24 +#define TCQ_ITEM5_SHIFT 20 +#define TCQ_ITEM4_SHIFT 16 +#define TCQ_ITEM3_SHIFT 12 +#define TCQ_ITEM2_SHIFT 8 +#define TCQ_ITEM1_SHIFT 4 +#define TCQ_ITEM0_SHIFT 0 + +#define TCQ_ITEM_TCC0 0x0 +#define TCQ_ITEM_TCC1 0x1 +#define TCQ_ITEM_TCC2 0x2 +#define TCQ_ITEM_TCC3 0x3 +#define TCQ_ITEM_TCC4 0x4 +#define TCQ_ITEM_TCC5 0x5 +#define TCQ_ITEM_TCC6 0x6 +#define TCQ_ITEM_TCC7 0x7 +#define TCQ_ITEM_GCC7 0x8 +#define TCQ_ITEM_GCC6 0x9 +#define TCQ_ITEM_GCC5 0xa +#define TCQ_ITEM_GCC4 0xb +#define TCQ_ITEM_GCC3 0xc +#define TCQ_ITEM_GCC2 0xd +#define TCQ_ITEM_GCC1 0xe +#define TCQ_ITEM_GCC0 0xf + +/* TouchScreen Convert Config 0-7 */ +#define TCC0 0x440 +#define TCC1 0x444 +#define TCC2 0x448 +#define TCC3 0x44c +#define TCC4 0x450 +#define TCC5 0x454 +#define TCC6 0x458 +#define TCC7 0x45c +#define CC_PEN_IACK (1 << 1) +#define CC_SEL_REFN_SHIFT 2 +#define CC_SEL_REFN_YNLR (0x1 << CC_SEL_REFN_SHIFT) +#define CC_SEL_REFN_AGND (0x2 << CC_SEL_REFN_SHIFT) +#define CC_SEL_REFN_MASK (0x3 << CC_SEL_REFN_SHIFT) +#define CC_SELIN_SHIFT 4 +#define CC_SELIN_XPUL (0x0 << CC_SELIN_SHIFT) +#define CC_SELIN_YPLL (0x1 << CC_SELIN_SHIFT) +#define CC_SELIN_XNUR (0x2 << CC_SELIN_SHIFT) +#define CC_SELIN_YNLR (0x3 << CC_SELIN_SHIFT) +#define CC_SELIN_WIPER (0x4 << CC_SELIN_SHIFT) +#define CC_SELIN_INAUX0 (0x5 << CC_SELIN_SHIFT) +#define CC_SELIN_INAUX1 (0x6 << CC_SELIN_SHIFT) +#define CC_SELIN_INAUX2 (0x7 << CC_SELIN_SHIFT) +#define CC_SELIN_MASK (0x7 << CC_SELIN_SHIFT) +#define CC_SELREFP_SHIFT 7 +#define CC_SELREFP_YPLL (0x0 << CC_SELREFP_SHIFT) +#define CC_SELREFP_XPUL (0x1 << CC_SELREFP_SHIFT) +#define CC_SELREFP_EXT (0x2 << CC_SELREFP_SHIFT) +#define CC_SELREFP_INT (0x3 << CC_SELREFP_SHIFT) +#define CC_SELREFP_MASK (0x3 << CC_SELREFP_SHIFT) +#define CC_XPULSW (1 << 9) +#define CC_XNURSW_SHIFT 10 +#define CC_XNURSW_HIGH (0x0 << CC_XNURSW_SHIFT) +#define CC_XNURSW_OFF (0x1 << CC_XNURSW_SHIFT) +#define CC_XNURSW_LOW (0x3 << CC_XNURSW_SHIFT) +#define CC_XNURSW_MASK (0x3 << CC_XNURSW_SHIFT) +#define CC_YPLLSW_SHIFT 12 +#define CC_YPLLSW_MASK (0x3 << CC_YPLLSW_SHIFT) +#define CC_YNLRSW (1 << 14) +#define CC_WIPERSW (1 << 15) +#define CC_NOS_SHIFT 16 +#define CC_YPLLSW_HIGH (0x0 << CC_NOS_SHIFT) +#define CC_YPLLSW_OFF (0x1 << CC_NOS_SHIFT) +#define CC_YPLLSW_LOW (0x3 << CC_NOS_SHIFT) +#define CC_NOS_MASK (0xf << CC_NOS_SHIFT) +#define CC_IGS (1 << 20) +#define CC_SETTLING_TIME_SHIFT 24 +#define CC_SETTLING_TIME_MASK (0xff << CC_SETTLING_TIME_SHIFT) + +#define TSC_4WIRE_PRECHARGE 0x158c +#define TSC_4WIRE_TOUCH_DETECT 0x578e + +#define TSC_4WIRE_X_MEASUMENT 0x1c90 +#define TSC_4WIRE_Y_MEASUMENT 0x4604 + +#define TSC_GENERAL_ADC_GCC0 0x17dc +#define TSC_GENERAL_ADC_GCC1 0x17ec +#define TSC_GENERAL_ADC_GCC2 0x17fc + +/* GeneralADC Convert Queue FIFO Register */ +#define GCQFIFO 0x800 +#define GCQFIFO_ADCOUT_SHIFT 4 +#define GCQFIFO_ADCOUT_MASK (0xfff << GCQFIFO_ADCOUT_SHIFT) +/* GeneralADC Convert Queue Control Register */ +#define GCQCR 0x804 +/* GeneralADC Convert Queue Status Register */ +#define GCQSR 0x808 +/* GeneralADC Convert Queue Mask Register */ +#define GCQMR 0x80c + +/* GeneralADC Convert Queue ITEM 7~0 */ +#define GCQ_ITEM_7_0 0x820 +/* GeneralADC Convert Queue ITEM 15~8 */ +#define GCQ_ITEM_15_8 0x824 + +#define GCQ_ITEM7_SHIFT 28 +#define GCQ_ITEM6_SHIFT 24 +#define GCQ_ITEM5_SHIFT 20 +#define GCQ_ITEM4_SHIFT 16 +#define GCQ_ITEM3_SHIFT 12 +#define GCQ_ITEM2_SHIFT 8 +#define GCQ_ITEM1_SHIFT 4 +#define GCQ_ITEM0_SHIFT 0 + +#define GCQ_ITEM_GCC0 0x0 +#define GCQ_ITEM_GCC1 0x1 +#define GCQ_ITEM_GCC2 0x2 +#define GCQ_ITEM_GCC3 0x3 + +/* GeneralADC Convert Config 0-7 */ +#define GCC0 0x840 +#define GCC1 0x844 +#define GCC2 0x848 +#define GCC3 0x84c +#define GCC4 0x850 +#define GCC5 0x854 +#define GCC6 0x858 +#define GCC7 0x85c + +/* TSC Test Register R/W */ +#define TTR 0xc00 +/* TSC Monitor Register 1, 2 */ +#define MNT1 0xc04 +#define MNT2 0xc04 + +#define DETECT_ITEM_ID_1 1 +#define DETECT_ITEM_ID_2 5 +#define TS_X_ITEM_ID 2 +#define TS_Y_ITEM_ID 3 +#define TSI_DATA 1 +#define FQS_DATA 0 + +#endif /* __IMX_ADC_H__ */ diff --git a/drivers/mxc/amd-gpu/Kconfig b/drivers/mxc/amd-gpu/Kconfig new file mode 100644 index 000000000000..629d8cbbc989 --- /dev/null +++ b/drivers/mxc/amd-gpu/Kconfig @@ -0,0 +1,13 @@ +# +# Bluetooth configuration +# + +menu "MXC GPU support" + +config MXC_AMD_GPU + tristate "MXC GPU support" + depends on ARCH_MX35 || ARCH_MX51 || ARCH_MX53 || ARCH_MX50 + ---help--- + Say Y to get the GPU driver support. + +endmenu diff --git a/drivers/mxc/amd-gpu/Makefile b/drivers/mxc/amd-gpu/Makefile new file mode 100644 index 000000000000..84cf02e5b3a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/Makefile @@ -0,0 +1,31 @@ +EXTRA_CFLAGS := \ + -D_LINUX \ + -I$(obj)/include \ + -I$(obj)/include/api \ + -I$(obj)/include/ucode \ + -I$(obj)/platform/hal/linux \ + -I$(obj)/os/include \ + -I$(obj)/os/kernel/include \ + -I$(obj)/os/user/include + +obj-$(CONFIG_MXC_AMD_GPU) += gpu.o +gpu-objs += common/gsl_cmdstream.o \ + common/gsl_cmdwindow.o \ + common/gsl_context.o \ + common/gsl_debug_pm4.o \ + common/gsl_device.o \ + common/gsl_drawctxt.o \ + common/gsl_driver.o \ + common/gsl_g12.o \ + common/gsl_intrmgr.o \ + common/gsl_memmgr.o \ + common/gsl_mmu.o \ + common/gsl_ringbuffer.o \ + common/gsl_sharedmem.o \ + common/gsl_yamato.o \ + platform/hal/linux/gsl_linux_map.o \ + platform/hal/linux/gsl_kmod.o \ + platform/hal/linux/gsl_hal.o \ + platform/hal/linux/gsl_kmod_cleanup.o \ + platform/hal/linux/misc.o \ + os/kernel/src/linux/kos_lib.o diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdstream.c b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c new file mode 100644 index 000000000000..4f0d107f2f67 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_cmdstream.c @@ -0,0 +1,267 @@ +/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#include "gsl_cmdstream.h" + +#ifdef GSL_LOCKING_FINEGRAIN +#define GSL_CMDSTREAM_MUTEX_CREATE() device->cmdstream_mutex = kos_mutex_create("gsl_cmdstream"); \ + if (!device->cmdstream_mutex) return (GSL_FAILURE); +#define GSL_CMDSTREAM_MUTEX_LOCK() kos_mutex_lock(device->cmdstream_mutex) +#define GSL_CMDSTREAM_MUTEX_UNLOCK() kos_mutex_unlock(device->cmdstream_mutex) +#define GSL_CMDSTREAM_MUTEX_FREE() kos_mutex_free(device->cmdstream_mutex); device->cmdstream_mutex = 0; +#else +#define GSL_CMDSTREAM_MUTEX_CREATE() +#define GSL_CMDSTREAM_MUTEX_LOCK() +#define GSL_CMDSTREAM_MUTEX_UNLOCK() +#define GSL_CMDSTREAM_MUTEX_FREE() +#endif + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_cmdstream_init(gsl_device_t *device) +{ + GSL_CMDSTREAM_MUTEX_CREATE(); + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int +kgsl_cmdstream_close(gsl_device_t *device) +{ + GSL_CMDSTREAM_MUTEX_FREE(); + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +gsl_timestamp_t +kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type) +{ + gsl_timestamp_t timestamp = -1; + gsl_device_t* device = &gsl_driver.device[device_id-1]; + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> gsl_timestamp_t kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id=%d gsl_timestamp_type_t type=%d)\n", device_id, type ); +#if (defined(GSL_BLD_G12) && defined(IRQTHREAD_POLL)) + kos_event_signal(device->irqthread_event); +#endif + if (type == GSL_TIMESTAMP_CONSUMED) + { + // start-of-pipeline timestamp + GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, (unsigned int*)×tamp); + } + else if (type == GSL_TIMESTAMP_RETIRED) + { + // end-of-pipeline timestamp + GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (unsigned int*)×tamp); + } + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_readtimestamp. Return value %d\n", timestamp ); + return (timestamp); +} + +//---------------------------------------------------------------------------- + +KGSL_API gsl_timestamp_t +kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type) +{ + gsl_timestamp_t timestamp = -1; + GSL_API_MUTEX_LOCK(); + timestamp = kgsl_cmdstream_readtimestamp0(device_id, type); + GSL_API_MUTEX_UNLOCK(); + return timestamp; +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status = GSL_FAILURE; + GSL_API_MUTEX_LOCK(); + + kgsl_device_active(device); + + if (device->ftbl.cmdstream_issueibcmds) + { + status = device->ftbl.cmdstream_issueibcmds(device, drawctxt_index, ibaddr, sizedwords, timestamp, flags); + } + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status = GSL_FAILURE; + GSL_API_MUTEX_LOCK(); + if (device->ftbl.device_addtimestamp) + { + status = device->ftbl.device_addtimestamp(device, timestamp); + } + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +KGSL_API +int kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status = GSL_FAILURE; + if (device->ftbl.device_waittimestamp) + { + status = device->ftbl.device_waittimestamp(device, timestamp, timeout); + } + return status; +} + +//---------------------------------------------------------------------------- + +void +kgsl_cmdstream_memqueue_drain(gsl_device_t *device) +{ + gsl_memnode_t *memnode, *nextnode, *freehead; + gsl_timestamp_t timestamp, ts_processed; + gsl_memqueue_t *memqueue = &device->memqueue; + + GSL_CMDSTREAM_MUTEX_LOCK(); + + // check head + if (memqueue->head == NULL) + { + GSL_CMDSTREAM_MUTEX_UNLOCK(); + return; + } + // get current EOP timestamp + ts_processed = kgsl_cmdstream_readtimestamp0(device->id, GSL_TIMESTAMP_RETIRED); + timestamp = memqueue->head->timestamp; + // check head timestamp + if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -GSL_TIMESTAMP_EPSILON))) + { + GSL_CMDSTREAM_MUTEX_UNLOCK(); + return; + } + memnode = memqueue->head; + freehead = memqueue->head; + // get node list to free + for(;;) + { + nextnode = memnode->next; + if (nextnode == NULL) + { + // entire queue drained + memqueue->head = NULL; + memqueue->tail = NULL; + break; + } + timestamp = nextnode->timestamp; + if (!(((ts_processed - timestamp) >= 0) || ((ts_processed - timestamp) < -GSL_TIMESTAMP_EPSILON))) + { + // drained up to a point + memqueue->head = nextnode; + memnode->next = NULL; + break; + } + memnode = nextnode; + } + // free nodes + while (freehead) + { + memnode = freehead; + freehead = memnode->next; + kgsl_sharedmem_free0(&memnode->memdesc, memnode->pid); + kos_free(memnode); + } + + GSL_CMDSTREAM_MUTEX_UNLOCK(); +} + +//---------------------------------------------------------------------------- + +int +kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type) +{ + gsl_memnode_t *memnode; + gsl_device_t *device = &gsl_driver.device[device_id-1]; + gsl_memqueue_t *memqueue; + (void)type; // unref. For now just use EOP timestamp + + GSL_API_MUTEX_LOCK(); + GSL_CMDSTREAM_MUTEX_LOCK(); + + memqueue = &device->memqueue; + + memnode = kos_malloc(sizeof(gsl_memnode_t)); + + if (!memnode) + { + // other solution is to idle and free which given that the upper level driver probably wont check, probably a better idea + GSL_CMDSTREAM_MUTEX_UNLOCK(); + GSL_API_MUTEX_UNLOCK(); + return (GSL_FAILURE); + } + + memnode->timestamp = timestamp; + memnode->pid = GSL_CALLER_PROCESSID_GET(); + memnode->next = NULL; + kos_memcpy(&memnode->memdesc, memdesc, sizeof(gsl_memdesc_t)); + + // add to end of queue + if (memqueue->tail != NULL) + { + memqueue->tail->next = memnode; + memqueue->tail = memnode; + } + else + { + KOS_ASSERT(memqueue->head == NULL); + memqueue->head = memnode; + memqueue->tail = memnode; + } + + GSL_CMDSTREAM_MUTEX_UNLOCK(); + GSL_API_MUTEX_UNLOCK(); + + return (GSL_SUCCESS); +} + +static int kgsl_cmdstream_timestamp_cmp(gsl_timestamp_t ts_new, gsl_timestamp_t ts_old) +{ + gsl_timestamp_t ts_diff = ts_new - ts_old; + return (ts_diff >= 0) || (ts_diff < -GSL_TIMESTAMP_EPSILON); +} + +int kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp) +{ + gsl_timestamp_t ts_processed; + ts_processed = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_RETIRED); + return kgsl_cmdstream_timestamp_cmp(ts_processed, timestamp); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c new file mode 100644 index 000000000000..d19832d8da44 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_cmdwindow.c @@ -0,0 +1,161 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + +#ifdef GSL_BLD_G12 + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_CMDWINDOW_TARGET_MASK 0x000000FF +#define GSL_CMDWINDOW_ADDR_MASK 0x00FFFF00 +#define GSL_CMDWINDOW_TARGET_SHIFT 0 +#define GSL_CMDWINDOW_ADDR_SHIFT 8 + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#ifdef GSL_LOCKING_FINEGRAIN +#define GSL_CMDWINDOW_MUTEX_CREATE() device->cmdwindow_mutex = kos_mutex_create("gsl_cmdwindow"); \ + if (!device->cmdwindow_mutex) return (GSL_FAILURE); +#define GSL_CMDWINDOW_MUTEX_LOCK() kos_mutex_lock(device->cmdwindow_mutex) +#define GSL_CMDWINDOW_MUTEX_UNLOCK() kos_mutex_unlock(device->cmdwindow_mutex) +#define GSL_CMDWINDOW_MUTEX_FREE() kos_mutex_free(device->cmdwindow_mutex); device->cmdwindow_mutex = 0; +#else +#define GSL_CMDWINDOW_MUTEX_CREATE() +#define GSL_CMDWINDOW_MUTEX_LOCK() +#define GSL_CMDWINDOW_MUTEX_UNLOCK() +#define GSL_CMDWINDOW_MUTEX_FREE() +#endif + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_cmdwindow_init(gsl_device_t *device) +{ + GSL_CMDWINDOW_MUTEX_CREATE(); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_cmdwindow_close(gsl_device_t *device) +{ + GSL_CMDWINDOW_MUTEX_FREE(); + + return (GSL_SUCCESS); +} + +#endif // GSL_BLD_G12 + +//---------------------------------------------------------------------------- + +int +kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data) +{ +#ifdef GSL_BLD_G12 + gsl_device_t *device; + unsigned int cmdwinaddr; + unsigned int cmdstream; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_cmdwindow_write( gsl_device_id_t device_id=%d, gsl_cmdwindow_t target=%d, unsigned int addr=0x%08x, unsigned int data=0x%08x)\n", device_id, target, addr, data ); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (target < GSL_CMDWINDOW_MIN || target > GSL_CMDWINDOW_MAX) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid target.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + if ((!(device->flags & GSL_FLAGS_INITIALIZED) && target == GSL_CMDWINDOW_MMU) || + (!(device->flags & GSL_FLAGS_STARTED) && target != GSL_CMDWINDOW_MMU)) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device state to write to selected targer.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // set command stream + if (target == GSL_CMDWINDOW_MMU) + { +#ifdef GSL_NO_MMU + return (GSL_SUCCESS); +#endif + cmdstream = ADDR_VGC_MMUCOMMANDSTREAM; + } + else + { + cmdstream = ADDR_VGC_COMMANDSTREAM; + } + + + // set command window address + cmdwinaddr = ((target << GSL_CMDWINDOW_TARGET_SHIFT) & GSL_CMDWINDOW_TARGET_MASK); + cmdwinaddr |= ((addr << GSL_CMDWINDOW_ADDR_SHIFT) & GSL_CMDWINDOW_ADDR_MASK); + + GSL_CMDWINDOW_MUTEX_LOCK(); + +#ifndef GSL_NO_MMU + // set mmu pagetable + kgsl_mmu_setpagetable(device, GSL_CALLER_PROCESSID_GET()); +#endif + + // write command window address + device->ftbl.device_regwrite(device, (cmdstream)>>2, cmdwinaddr); + + // write data + device->ftbl.device_regwrite(device, (cmdstream)>>2, data); + + GSL_CMDWINDOW_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cmdwindow_write. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +#else + // unreferenced formal parameter + (void) device_id; + (void) target; + (void) addr; + (void) data; + + return (GSL_FAILURE); +#endif // GSL_BLD_G12 +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_cmdwindow_write0(device_id, target, addr, data); + GSL_API_MUTEX_UNLOCK(); + return status; +} diff --git a/drivers/mxc/amd-gpu/common/gsl_context.c b/drivers/mxc/amd-gpu/common/gsl_context.c new file mode 100644 index 000000000000..c999247b3afd --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_context.c @@ -0,0 +1,74 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#include "gsl_context.h" + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +KGSL_API int +kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status; + + GSL_API_MUTEX_LOCK(); + + if (device->ftbl.context_create) + { + status = device->ftbl.context_create(device, type, drawctxt_id, flags); + } + else + { + status = GSL_FAILURE; + } + + GSL_API_MUTEX_UNLOCK(); + + return status; +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id) +{ + gsl_device_t* device = &gsl_driver.device[device_id-1]; + int status; + + GSL_API_MUTEX_LOCK(); + + if (device->ftbl.context_destroy) + { + status = device->ftbl.context_destroy(device, drawctxt_id); + } + else + { + status = GSL_FAILURE; + } + + GSL_API_MUTEX_UNLOCK(); + + return status; +} + +//---------------------------------------------------------------------------- + diff --git a/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c new file mode 100644 index 000000000000..847df8dbe386 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_debug_pm4.c @@ -0,0 +1,1015 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + +#if defined(_WIN32) && defined (GSL_BLD_YAMATO) + +#include +#include +#include + +//#define PM4_DEBUG_USE_MEMBUF + +#ifdef PM4_DEBUG_USE_MEMBUF + +#define MEMBUF_SIZE 100000 +#define BUFFER_END_MARGIN 1000 +char memBuf[MEMBUF_SIZE]; +static int writePtr = 0; +static unsigned int lineNumber = 0; +//#define fprintf(A,...); writePtr += sprintf( memBuf+writePtr, __VA_ARGS__ ); sprintf( memBuf+writePtr, "###" ); if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) { memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); writePtr = 0; } +#define FILE char +#define fopen(X,Y) 0 +#define fclose(X) + +int printString( FILE *_File, const char * _Format, ...) +{ + int ret; + va_list ap; + (void)_File; + + va_start(ap, _Format); + if( writePtr > 0 && memBuf[writePtr-1] == '\n' ) + { + // Add line number if last written character was newline + writePtr += sprintf( memBuf+writePtr, "%d: ", lineNumber++ ); + } + ret = vsprintf(memBuf+writePtr, _Format, ap); + writePtr += ret; + sprintf( memBuf+writePtr, "###" ); + if( writePtr > MEMBUF_SIZE-BUFFER_END_MARGIN ) + { + memset(memBuf+writePtr, '#', MEMBUF_SIZE-writePtr); + writePtr = 0; + } + + va_end(ap); + + return ret; +} + +#else + +int printString( FILE *_File, const char * _Format, ...) +{ + int ret; + va_list ap; + va_start(ap, _Format); + ret = vfprintf(_File, _Format, ap); + va_end(ap); + fflush(_File); + return ret; +} + +#endif + +#ifndef _WIN32_WCE +#define PM4_DUMPFILE "pm4dump.txt" +#else +#define PM4_DUMPFILE "\\Release\\pm4dump.txt" +#endif + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define EXPAND_OPCODE(opcode) ((opcode << 8) | PM4_PKT_MASK) + +#define GetString_uint GetString_int +#define GetString_fixed12_4(val, szValue) GetString_fixed(val, 12, 4, szValue) +#define GetString_signedint15(val, szValue) GetString_signedint(val, 15, szValue) + +// Need a prototype for this function +void WritePM4Packet_Type3(FILE* pFile, unsigned int dwHeader, unsigned int** ppBuffer); + +static int indirectionLevel = 0; + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +void WriteDWORD(FILE* pFile, unsigned int dwValue) +{ + printString(pFile, " 0x%08x", dwValue); +} + +void WriteDWORD2(FILE* pFile, unsigned int dwValue) +{ + printString(pFile, " 0x%08x\n", dwValue); +} + +//---------------------------------------------------------------------------- + +// Generate the GetString_## functions for enumerated types +#define START_ENUMTYPE(__type) \ +void GetString_##__type(unsigned int val, char* szValue) \ +{ \ + switch(val) \ + { + +#define GENERATE_ENUM(__enumname, __val) \ + case __val: \ + kos_strcpy(szValue, #__enumname); \ + break; + +#define END_ENUMTYPE(__type) \ + default: \ + sprintf(szValue, "Unknown: %d", val); \ + break; \ + } \ +} + +#include _YAMATO_GENENUM_H + +//---------------------------------------------------------------------------- + +void +GetString_hex(unsigned int val, char* szValue) +{ + sprintf(szValue, "0x%x", val); +} + +//---------------------------------------------------------------------------- + +void +GetString_float(unsigned int val, char* szValue) +{ + float fval = *((float*) &val); + sprintf(szValue, "%.4f", fval); +} + +//---------------------------------------------------------------------------- + +void +GetString_bool(unsigned int val, char* szValue) +{ + if (val) + { + kos_strcpy(szValue, "TRUE"); + } + else + { + kos_strcpy(szValue, "FALSE"); + } +} + +//---------------------------------------------------------------------------- + +void GetString_int(unsigned int val, char* szValue) +{ + sprintf(szValue, "%d", val); +} + +//---------------------------------------------------------------------------- + +void +GetString_intMinusOne(unsigned int val, char* szValue) +{ + sprintf(szValue, "%d+1", val); +} + +//---------------------------------------------------------------------------- + +void +GetString_signedint(unsigned int val, unsigned int dwNumBits, char* szValue) +{ + int nValue = val; + + if (val & (1<<(dwNumBits-1))) + { + nValue |= 0xffffffff << dwNumBits; + } + + sprintf(szValue, "%d", nValue); +} + +//---------------------------------------------------------------------------- + +void +GetString_fixed(unsigned int val, unsigned int dwNumInt, unsigned int dwNumFrac, char* szValue) +{ + + (void) dwNumInt; // unreferenced formal parameter + + if (val>>dwNumFrac == 0) + { + // Integer part is 0 - just print out the fractional part + sprintf(szValue, "%d/%d", + val&((1<>dwNumFrac, + val&((1<> 16) == 0x4)) + registerAddr = (*pBuffer) & 0xffff; + + // Write unsigned int + WriteDWORD(pFile, *pBuffer); + + // Starting at Ordinal 2 is actual register values + if((dwIndex > 0) && (registerAddr != 0xffffffff)) + { + // Write register string based on address + GetString_Register(registerAddr + 0x2000, *pBuffer, szRegister); + printString(pFile, " // %s\n", szRegister); + registerAddr++; + } + else + { + // Write out newline if we aren't augmenting with register fields + printString(pFile, "\n"); + } + + pBuffer++; + } + } + *ppBuffer = pBuffer; +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpInitParams(unsigned int dwEDRAMBase, unsigned int dwEDRAMSize) +{ + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "InitParams, edrambase=0x%x, edramsize=%d\n", + dwEDRAMBase, dwEDRAMSize); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpSwapBuffers(unsigned int dwAddress, unsigned int dwWidth, + unsigned int dwHeight, unsigned int dwPitch, unsigned int dwAlignedHeight, unsigned int dwBitsPerPixel) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "SwapBuffers, address=0x%08x, width=%d, height=%d, pitch=%d, alignedheight=%d, bpp=%d\n", + dwAddress, dwWidth, dwHeight, dwPitch, dwAlignedHeight, dwBitsPerPixel); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpRegSpace(gsl_device_t *device) +{ + int regsPerLine = 0x20; + unsigned int dwOffset; + unsigned int value; + + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "Start_RegisterSpace\n"); + + for (dwOffset = 0; dwOffset < device->regspace.sizebytes; dwOffset += 4) + { + if (dwOffset % regsPerLine == 0) + { + printString(pFile, " 0x%08x ", dwOffset); + } + + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (dwOffset >> 2), &value); + + printString(pFile, " 0x%08x", value); + + if (((dwOffset + 4) % regsPerLine == 0) && ((dwOffset + 4) < device->regspace.sizebytes)) + { + printString(pFile, "\n"); + } + } + + printString(pFile, "\nEnd_RegisterSpace\n"); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpAllocateMemory(unsigned int dwSize, unsigned int dwFlags, unsigned int dwAddress, + unsigned int dwActualSize) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "AllocateMemory, size=%d, flags=0x%x, address=0x%x, actualSize=%d\n", + dwSize, dwFlags, dwAddress, dwActualSize); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpFreeMemory(unsigned int dwAddress) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "FreeMemory, address=0x%x\n", dwAddress); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + unsigned int dwNumDWORDs; + unsigned int dwIndex; + unsigned int *pDataPtr; + + printString(pFile, "StartWriteMemory, address=0x%x, size=%d\n", dwAddress, dwSize); + + // Now write the data, in dwNumDWORDs + dwNumDWORDs = dwSize >> 2; + + // If there are spillover bytes into the next dword, increment the amount dumped out here. + // The reader needs to take care of not overwriting the nonvalid bytes + if((dwSize % 4) != 0) + dwNumDWORDs++; + + for (dwIndex = 0, pDataPtr = (unsigned int *)pData; dwIndex < dwNumDWORDs; dwIndex++, pDataPtr++) + { + WriteDWORD2(pFile, *pDataPtr); + } + + printString(pFile, "EndWriteMemory\n"); + + fclose(pFile); +} + +void +Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData) +{ + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); +// unsigned int* pDataPtr; + + printString(pFile, "SetMemory, address=0x%x, size=%d, value=0x%x\n", + dwAddress, dwSize, pData); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- +void +Yamato_ConvertIBAddr(unsigned int dwHeader, unsigned int *pBuffer, int gpuToHost) +{ + unsigned int hostaddr; + unsigned int *ibend; + unsigned int *addr; + unsigned int *ib = pBuffer; + pm4_type3 header = *((pm4_type3*) &dwHeader); + + // convert ib1 base address + if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) || + (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD)) + { + if (gpuToHost) + { + // from gpu to host + *ib = kgsl_sharedmem_convertaddr(*ib, 0); + + hostaddr = *ib; + } + else + { + // from host to gpu + hostaddr = *ib; + *ib = kgsl_sharedmem_convertaddr(*ib, 1); + } + + // walk through ib1 and convert any ib2 base address + + ib = (unsigned int *) hostaddr; + ibend = (unsigned int *) (ib + *(++pBuffer)); + + while (ib < ibend) + { + dwHeader = *(ib); + header = *((pm4_type3*) (&dwHeader)); + + switch(dwHeader & PM4_PKT_MASK) + { + case PM4_TYPE0_PKT: + ib += header.count + 2; + break; + + case PM4_TYPE1_PKT: + break; + + case PM4_TYPE2_PKT: + ib++; + break; + + case PM4_TYPE3_PKT: + if((EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER) || + (EXPAND_OPCODE(header.it_opcode) == PM4_PACKET3_INDIRECT_BUFFER_PFD)) + { + addr = ib + 1; + if (gpuToHost) + { + // from gpu to host + *addr = kgsl_sharedmem_convertaddr(*addr, 0); + } + else + { + // from host to gpu + *addr = kgsl_sharedmem_convertaddr(*addr, 1); + } + } + ib += header.count + 2; + break; + } + } + } +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpPM4(unsigned int* pBuffer, unsigned int sizeDWords) +{ + unsigned int *pBufferEnd = pBuffer + sizeDWords; + unsigned int *tmp; + + // Open file + FILE* pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "Start_PM4Buffer\n");//, count=%d\n", sizeDWords); + + // So look at the first unsigned int - should be a header + while(pBuffer < pBufferEnd) + { + unsigned int dwHeader = *(pBuffer++); + + //printString(pFile, " Start_Packet\n"); + switch(dwHeader & PM4_PKT_MASK) + { + case PM4_TYPE0_PKT: + WritePM4Packet_Type0(pFile, dwHeader, &pBuffer); + break; + + case PM4_TYPE1_PKT: + break; + + case PM4_TYPE2_PKT: + WritePM4Packet_Type2(pFile, dwHeader, &pBuffer); + break; + + case PM4_TYPE3_PKT: + indirectionLevel = 0; + tmp = pBuffer; + Yamato_ConvertIBAddr(dwHeader, tmp, 1); + WritePM4Packet_Type3(pFile, dwHeader, &pBuffer); + Yamato_ConvertIBAddr(dwHeader, tmp, 0); + break; + } + //printString(pFile, " End_Packet\n"); + } + + printString(pFile, "End_PM4Buffer\n"); + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value) +{ + FILE *pFile; + + // Build a Type-0 packet that maps to this register write + unsigned int pBuffer[100], *pBuf = &pBuffer[1]; + + // Don't dump CP_RB_WPTR (switch statement may be necessary here for future additions) + if(dwAddress == mmCP_RB_WPTR) + return; + + pFile = fopen(PM4_DUMPFILE, "a"); + + pBuffer[0] = dwAddress; + pBuffer[1] = value; + + printString(pFile, "StartRegisterWrite\n"); + WritePM4Packet_Type0(pFile, pBuffer[0], &pBuf); + printString(pFile, "EndRegisterWrite\n"); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpFbStart(gsl_device_t *device) +{ + FILE *pFile; + + static int firstCall = 0; + + // We only want to call this once + if(firstCall) + return; + + pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "FbStart, value=0x%x\n", device->mmu.mpu_base); + printString(pFile, "FbSize, value=0x%x\n", device->mmu.mpu_range); + + fclose(pFile); + + firstCall = 1; +} + +//---------------------------------------------------------------------------- + +void +Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height) +{ + FILE *pFile; + + pFile = fopen(PM4_DUMPFILE, "a"); + + printString(pFile, "DumpWindow, addr=0x%x, width=0x%x, height=0x%x\n", addr, width, height); + + fclose(pFile); +} + +//---------------------------------------------------------------------------- +#ifdef _DEBUG + +#define ADDRESS_STACK_SIZE 256 +#define GET_PM4_TYPE3_OPCODE(x) ((*(x) >> 8) & 0xFF) +#define IF_REGISTER_IN_RANGE(reg, base, count) \ + offset = (reg) - (base); \ + if(offset >= 0 && offset <= (count) - 2) +#define GET_CP_CONSTANT_DATA(x) (*((x) + offset + 2)) + +static const char format2bpp[] = +{ + 2, // COLORX_4_4_4_4 + 2, // COLORX_1_5_5_5 + 2, // COLORX_5_6_5 + 1, // COLORX_8 + 2, // COLORX_8_8 + 4, // COLORX_8_8_8_8 + 4, // COLORX_S8_8_8_8 + 2, // COLORX_16_FLOAT + 4, // COLORX_16_16_FLOAT + 8, // COLORX_16_16_16_16_FLOAT + 4, // COLORX_32_FLOAT + 8, // COLORX_32_32_FLOAT + 16, // COLORX_32_32_32_32_FLOAT , + 1, // COLORX_2_3_3 + 3, // COLORX_8_8_8 +}; + +static unsigned int kgsl_dumpx_addr_count = 0; //unique command buffer addresses encountered +static int kgsl_dumpx_handle_type3(unsigned int* hostaddr, int count) +{ + // For swap detection we need to find the below declared static values, and detect DI during EDRAM copy + static unsigned int width = 0, height = 0, format = 0, baseaddr = 0, iscopy = 0; + + static unsigned int addr_stack[ADDRESS_STACK_SIZE]; + static unsigned int size_stack[ADDRESS_STACK_SIZE]; + int swap = 0; // have we encountered a swap during recursion (return value) + + switch(GET_PM4_TYPE3_OPCODE(hostaddr)) + { + case PM4_INDIRECT_BUFFER_PFD: + case PM4_INDIRECT_BUFFER: + { + // traverse indirect buffers + unsigned int i; + unsigned int ibaddr = *(hostaddr+1); + unsigned int ibsize = *(hostaddr+2); + + // is this address already in encountered? + for(i = 0; i < kgsl_dumpx_addr_count && addr_stack[i] != ibaddr; i++); + + if(kgsl_dumpx_addr_count == i) + { + // yes it was, store the address so we don't dump this buffer twice + addr_stack[kgsl_dumpx_addr_count] = ibaddr; + // just for sanity checking + size_stack[kgsl_dumpx_addr_count++] = ibsize; + KOS_ASSERT(kgsl_dumpx_addr_count < ADDRESS_STACK_SIZE); + + // recursively follow the indirect link and update swap if indirect buffer had resolve + swap |= kgsl_dumpx_parse_ibs(ibaddr, ibsize); + } + else + { + KOS_ASSERT(size_stack[i] == ibsize); + } + } + break; + + case PM4_SET_CONSTANT: + if((*(hostaddr+1) >> 16) == 0x4) + { + // parse register writes, and figure out framebuffer configuration + + unsigned int regaddr = (*(hostaddr + 1) & 0xFFFF) + 0x2000; //dword address in register space + int offset; // used by the macros + + IF_REGISTER_IN_RANGE(mmPA_SC_WINDOW_SCISSOR_BR, regaddr, count) + { + // found write to PA_SC_WINDOW_SCISSOR_BR, we use this to detect current + // width and height of the framebuffer (TODO: find more reliable way of achieving this) + unsigned int data = GET_CP_CONSTANT_DATA(hostaddr); + width = data & 0xFFFF; + height = data >> 16; + } + + IF_REGISTER_IN_RANGE(mmRB_MODECONTROL, regaddr, count) + { + // found write to RB_MODECONTROL, we use this to find out if next DI is resolve + unsigned int data = GET_CP_CONSTANT_DATA(hostaddr); + iscopy = (data & RB_MODECONTROL__EDRAM_MODE_MASK) == (EDRAM_COPY << RB_MODECONTROL__EDRAM_MODE__SHIFT); + } + + IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_BASE, regaddr, count) + { + // found write to RB_COPY_DEST_BASE, we use this to find out the framebuffer base address + unsigned int data = GET_CP_CONSTANT_DATA(hostaddr); + baseaddr = (data & RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK); + } + + IF_REGISTER_IN_RANGE(mmRB_COPY_DEST_INFO, regaddr, count) + { + // found write to RB_COPY_DEST_INFO, we use this to find out the framebuffer format + unsigned int data = GET_CP_CONSTANT_DATA(hostaddr); + format = (data & RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT; + } + } + break; + + case PM4_DRAW_INDX: + case PM4_DRAW_INDX_2: + { + // DI found + // check if it is resolve + if(iscopy && !swap) + { + // printf("resolve: %ix%i @ 0x%08x, format = 0x%08x\n", width, height, baseaddr, format); + KOS_ASSERT(format < 15); + + // yes it was and we need to update color buffer config because this is the first bin + // dumpx framebuffer base address, and dimensions + KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_AWH, (unsigned int)baseaddr, width, height, " "); + + // find aligned width + width = (width + 31) & ~31; + + //dump bytes-per-pixel and aligned width + KGSL_DEBUG_DUMPX( BB_DUMP_CBUF_FS, format2bpp[format], width, 0, " "); + swap = 1; + } + + } + break; + + default: + break; + } + return swap; +} + +// Traverse IBs and dump them to test vector. Detect swap by inspecting register +// writes, keeping note of the current state, and dump framebuffer config to test vector +int kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords) +{ + static unsigned int level = 0; //recursion level + + int swap = 0; // have we encountered a swap during recursion (return value) + unsigned int *hostaddr; + int dwords_left = sizedwords; //dwords left in the current command buffer + + level++; + + KOS_ASSERT(sizeof(unsigned int *) == sizeof(unsigned int)); + KOS_ASSERT(level <= 2); + hostaddr = (unsigned int *)kgsl_sharedmem_convertaddr(gpuaddr, 0); + + // dump the IB to test vector + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, gpuaddr, (unsigned int)hostaddr, sizedwords*4, "kgsl_dumpx_write_ibs")); + + while(dwords_left) + { + int count = 0; //dword count including packet header + + switch(*hostaddr >> 30) + { + case 0x0: // type-0 + count = (*hostaddr >> 16)+2; + break; + case 0x1: // type-1 + count = 2; + break; + case 0x3: // type-3 + count = ((*hostaddr >> 16) & 0x3fff) + 2; + swap |= kgsl_dumpx_handle_type3(hostaddr, count); + break; // type-3 + default: + KOS_ASSERT(!"unknown packet type"); + } + + // jump to next packet + dwords_left -= count; + hostaddr += count; + KOS_ASSERT(dwords_left >= 0 && "PM4 parsing error"); + } + + level--; + + // if this is the starting level of recursion, we are done. clean-up + if(level == 0) kgsl_dumpx_addr_count = 0; + + return swap; +} +#endif + +#endif // WIN32 + diff --git a/drivers/mxc/amd-gpu/common/gsl_device.c b/drivers/mxc/amd-gpu/common/gsl_device.c new file mode 100644 index 000000000000..6c41d3dd6dcc --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_device.c @@ -0,0 +1,694 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#ifdef _LINUX +#include +#endif + +////////////////////////////////////////////////////////////////////////////// +// inline functions +////////////////////////////////////////////////////////////////////////////// +OSINLINE void +kgsl_device_getfunctable(gsl_deviceid_t device_id, gsl_functable_t *ftbl) +{ + switch (device_id) + { +#ifdef GSL_BLD_YAMATO + case GSL_DEVICE_YAMATO: + kgsl_yamato_getfunctable(ftbl); + break; +#endif // GSL_BLD_YAMATO +#ifdef GSL_BLD_G12 + case GSL_DEVICE_G12: + kgsl_g12_getfunctable(ftbl); + break; +#endif // GSL_BLD_G12 + default: + break; + } +} + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id) +{ + int status = GSL_SUCCESS; + gsl_devconfig_t config; + gsl_hal_t *hal = (gsl_hal_t *)gsl_driver.hal; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_init(gsl_device_t *device=0x%08x, gsl_deviceid_t device_id=%D )\n", device, device_id ); + + if ((GSL_DEVICE_YAMATO == device_id) && !(hal->has_z430)) { + return GSL_FAILURE_NOTSUPPORTED; + } + + if ((GSL_DEVICE_G12 == device_id) && !(hal->has_z160)) { + return GSL_FAILURE_NOTSUPPORTED; + } + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + kos_memset(device, 0, sizeof(gsl_device_t)); + + // if device configuration is present + if (kgsl_hal_getdevconfig(device_id, &config) == GSL_SUCCESS) + { + kgsl_device_getfunctable(device_id, &device->ftbl); + + kos_memcpy(&device->regspace, &config.regspace, sizeof(gsl_memregion_t)); +#ifdef GSL_BLD_YAMATO + kos_memcpy(&device->gmemspace, &config.gmemspace, sizeof(gsl_memregion_t)); +#endif // GSL_BLD_YAMATO + + device->refcnt = 0; + device->id = device_id; + +#ifndef GSL_NO_MMU + device->mmu.config = config.mmu_config; + device->mmu.mpu_base = config.mpu_base; + device->mmu.mpu_range = config.mpu_range; + device->mmu.va_base = config.va_base; + device->mmu.va_range = config.va_range; +#endif + + if (device->ftbl.device_init) + { + status = device->ftbl.device_init(device); + } + else + { + status = GSL_FAILURE_NOTINITIALIZED; + } + + // allocate memory store + status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS, sizeof(gsl_devmemstore_t), &device->memstore); + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + // dumpx needs this to be in EMEM0 aperture + kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET()); + status = kgsl_sharedmem_alloc0(device->id, GSL_MEMFLAGS_ALIGNPAGE, sizeof(gsl_devmemstore_t), &device->memstore); + }); + + if (status != GSL_SUCCESS) + { + kgsl_device_stop(device->id); + return (status); + } + kgsl_sharedmem_set0(&device->memstore, 0, 0, device->memstore.size); + + // init memqueue + device->memqueue.head = NULL; + device->memqueue.tail = NULL; + + // init cmdstream + status = kgsl_cmdstream_init(device); + if (status != GSL_SUCCESS) + { + kgsl_device_stop(device->id); + return (status); + } + +#ifndef _LINUX + // Create timestamp event + device->timestamp_event = kos_event_create(0); + if( !device->timestamp_event ) + { + kgsl_device_stop(device->id); + return (status); + } +#else + // Create timestamp wait queue + init_waitqueue_head(&device->timestamp_waitq); +#endif + + // + // Read the chip ID after the device has been initialized. + // + device->chip_id = kgsl_hal_getchipid(device->id); + } + + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_init. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_close(gsl_device_t *device) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_close(gsl_device_t *device=0x%08x )\n", device ); + + if (!(device->flags & GSL_FLAGS_INITIALIZED)) { + return status; + } + + /* make sure the device is stopped before close + kgsl_device_close is only called for last running caller process + */ + while (device->refcnt > 0) { + GSL_API_MUTEX_UNLOCK(); + kgsl_device_stop(device->id); + GSL_API_MUTEX_LOCK(); + } + + // close cmdstream + status = kgsl_cmdstream_close(device); + if( status != GSL_SUCCESS ) return status; + + if (device->ftbl.device_close) { + status = device->ftbl.device_close(device); + } + + // DumpX allocates memstore from MMU aperture + if ((device->refcnt == 0) && device->memstore.hostptr + && !(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX)) + { + kgsl_sharedmem_free0(&device->memstore, GSL_CALLER_PROCESSID_GET()); + } + +#ifndef _LINUX + // destroy timestamp event + if(device->timestamp_event) + { + kos_event_signal(device->timestamp_event); // wake up waiting threads before destroying the structure + kos_event_destroy( device->timestamp_event ); + device->timestamp_event = 0; + } +#else + wake_up_interruptible_all(&(device->timestamp_waitq)); +#endif + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_close. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_destroy(gsl_device_t *device) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_destroy(gsl_device_t *device=0x%08x )\n", device ); + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (device->ftbl.device_destroy) + { + status = device->ftbl.device_destroy(device); + } + } + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_destroy. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid) +{ + int status = GSL_SUCCESS; + int pindex; + +#ifndef GSL_NO_MMU + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_attachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid ); + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS) + { + device->callerprocess[pindex] = pid; + + status = kgsl_mmu_attachcallback(&device->mmu, pid); + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_attachcallback. Return value: %B\n", status ); + +#else + (void)pid; + (void)device; +#endif + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid) +{ + int status = GSL_SUCCESS; + int pindex; + +#ifndef GSL_NO_MMU + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_device_detachcallback(gsl_device_t *device=0x%08x, unsigned int pid=0x%08x)\n", device, pid ); + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (kgsl_driver_getcallerprocessindex(pid, &pindex) == GSL_SUCCESS) + { + status |= kgsl_mmu_detachcallback(&device->mmu, pid); + + device->callerprocess[pindex] = 0; + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_detachcallback. Return value: %B\n", status ); + +#else + (void)pid; + (void)device; +#endif + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_SUCCESS; + gsl_device_t *device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_getproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes ); + + KOS_ASSERT(value); + +#ifndef _DEBUG + (void) sizebytes; // unreferenced formal parameter +#endif + + switch (type) + { + case GSL_PROP_SHMEM: + { + gsl_shmemprop_t *shem = (gsl_shmemprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_shmemprop_t)); + + shem->numapertures = gsl_driver.shmem.numapertures; + shem->aperture_mask = GSL_APERTURE_MASK; + shem->aperture_shift = GSL_APERTURE_SHIFT; + + break; + } + + case GSL_PROP_SHMEM_APERTURES: + { + int i; + gsl_apertureprop_t *aperture = (gsl_apertureprop_t *) value; + + KOS_ASSERT(sizebytes == (sizeof(gsl_apertureprop_t) * gsl_driver.shmem.numapertures)); + + for (i = 0; i < gsl_driver.shmem.numapertures; i++) + { + if (gsl_driver.shmem.apertures[i].memarena) + { + aperture->gpuaddr = GSL_APERTURE_GETGPUADDR(gsl_driver.shmem, i); + aperture->hostaddr = GSL_APERTURE_GETHOSTADDR(gsl_driver.shmem, i); + } + else + { + aperture->gpuaddr = 0x0; + aperture->hostaddr = 0x0; + } + aperture++; + } + + break; + } + + case GSL_PROP_DEVICE_SHADOW: + { + gsl_shadowprop_t *shadowprop = (gsl_shadowprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_shadowprop_t)); + + kos_memset(shadowprop, 0, sizeof(gsl_shadowprop_t)); + +#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + if (device->memstore.hostptr) + { + shadowprop->hostaddr = (unsigned int) device->memstore.hostptr; + shadowprop->size = device->memstore.size; + shadowprop->flags = GSL_FLAGS_INITIALIZED; + } +#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + + break; + } + + default: + { + if (device->ftbl.device_getproperty) + { + status = device->ftbl.device_getproperty(device, type, value, sizebytes); + } + + break; + } + } + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_getproperty. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_SUCCESS; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_setproperty(gsl_deviceid_t device_id=%D, gsl_property_type_t type=%d, void *value=0x08x, unsigned int sizebytes=%d)\n", device_id, type, value, sizebytes ); + + KOS_ASSERT(value); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (device->ftbl.device_setproperty) + { + status = device->ftbl.device_setproperty(device, type, value, sizebytes); + } + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_setproperty. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + gsl_hal_t *hal = (gsl_hal_t *)gsl_driver.hal; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_start(gsl_deviceid_t device_id=%D, gsl_flags_t flags=%d)\n", device_id, flags ); + + GSL_API_MUTEX_LOCK(); + + if ((GSL_DEVICE_G12 == device_id) && !(hal->has_z160)) { + GSL_API_MUTEX_UNLOCK(); + return GSL_FAILURE_NOTSUPPORTED; + } + + if ((GSL_DEVICE_YAMATO == device_id) && !(hal->has_z430)) { + GSL_API_MUTEX_UNLOCK(); + return GSL_FAILURE_NOTSUPPORTED; + } + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + kgsl_device_active(device); + + if (!(device->flags & GSL_FLAGS_INITIALIZED)) + { + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_ERROR, "ERROR: Trying to start uninitialized device.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + device->refcnt++; + + if (device->flags & GSL_FLAGS_STARTED) + { + GSL_API_MUTEX_UNLOCK(); + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + // start device in safe mode + if (flags & GSL_FLAGS_SAFEMODE) + { + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_INFO, "Running the device in safe mode.\n" ); + device->flags |= GSL_FLAGS_SAFEMODE; + } + + if (device->ftbl.device_start) + { + status = device->ftbl.device_start(device, flags); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_start. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_stop(gsl_deviceid_t device_id) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_stop(gsl_deviceid_t device_id=%D)\n", device_id ); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (device->flags & GSL_FLAGS_STARTED) + { + KOS_ASSERT(device->refcnt); + + device->refcnt--; + + if (device->refcnt == 0) + { + if (device->ftbl.device_stop) + { + status = device->ftbl.device_stop(device); + } + } + else + { + status = GSL_SUCCESS; + } + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_stop. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_idle(gsl_deviceid_t device_id=%D, unsigned int timeout=%d)\n", device_id, timeout ); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + kgsl_device_active(device); + + if (device->ftbl.device_idle) + { + status = device->ftbl.device_idle(device, timeout); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_idle. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_isidle(gsl_deviceid_t device_id) +{ + gsl_timestamp_t retired = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_RETIRED); + gsl_timestamp_t consumed = kgsl_cmdstream_readtimestamp0(device_id, GSL_TIMESTAMP_CONSUMED); + gsl_timestamp_t ts_diff = retired - consumed; + return (ts_diff >= 0) || (ts_diff < -GSL_TIMESTAMP_EPSILON) ? GSL_SUCCESS : GSL_FAILURE; +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + +#ifdef GSL_LOG + if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR ) // Would otherwise flood the log + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_regread(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int *value=0x%08x)\n", device_id, offsetwords, value ); +#endif + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + KOS_ASSERT(value); + KOS_ASSERT(offsetwords < device->regspace.sizebytes); + + if (device->ftbl.device_regread) + { + status = device->ftbl.device_regread(device, offsetwords, value); + } + + GSL_API_MUTEX_UNLOCK(); + +#ifdef GSL_LOG + if( offsetwords != mmRBBM_STATUS && offsetwords != mmCP_RB_RPTR ) + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regread. Return value %B\n", status ); +#endif + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_regwrite(gsl_deviceid_t device_id=%D, unsigned int offsetwords=%R, unsigned int value=0x%08x)\n", device_id, offsetwords, value ); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + KOS_ASSERT(offsetwords < device->regspace.sizebytes); + + if (device->ftbl.device_regwrite) + { + status = device->ftbl.device_regwrite(device, offsetwords, value); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_regwrite. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + gsl_device_t *device; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_waitirq(gsl_deviceid_t device_id=%D, gsl_intrid_t intr_id=%d, unsigned int *count=0x%08x, unsigned int timout=0x%08x)\n", device_id, intr_id, count, timeout); + + GSL_API_MUTEX_LOCK(); + + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (device->ftbl.device_waitirq) + { + status = device->ftbl.device_waitirq(device, intr_id, count, timeout); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_waitirq. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_device_runpending(gsl_device_t *device) +{ + int status = GSL_FAILURE_NOTINITIALIZED; + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_device_runpending(gsl_device_t *device=0x%08x )\n", device ); + + if (device->flags & GSL_FLAGS_INITIALIZED) + { + if (device->ftbl.device_runpending) + { + status = device->ftbl.device_runpending(device); + } + } + + // free any pending freeontimestamps + kgsl_cmdstream_memqueue_drain(device); + + kgsl_log_write( KGSL_LOG_GROUP_DEVICE | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_device_runpending. Return value %B\n", status ); + + return (status); +} + diff --git a/drivers/mxc/amd-gpu/common/gsl_drawctxt.c b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c new file mode 100644 index 000000000000..1e8fa1a4962e --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_drawctxt.c @@ -0,0 +1,1828 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#ifdef _LINUX +#include +#endif + +#ifdef GSL_BLD_YAMATO + +////////////////////////////////////////////////////////////////////////////// +// +// Memory Map for Register, Constant & Instruction Shadow, and Command Buffers (34.5KB) +// +// +---------------------+------------+-------------+---+---------------------+ +// | ALU Constant Shadow | Reg Shadow | C&V Buffers |Tex| Shader Instr Shadow | +// +---------------------+------------+-------------+---+---------------------+ +// ________________________________' '___________________ +// ' ' +// +--------------+-----------+------+-----------+------------------------+ +// | Restore Regs | Save Regs | Quad | Gmem Save | Gmem Restore | unused | +// +--------------+-----------+------+-----------+------------------------+ +// +// 8K - ALU Constant Shadow (8K aligned) +// 4K - H/W Register Shadow (8K aligned) +// 9K - Command and Vertex Buffers +// - Indirect command buffer : Const/Reg restore +// - includes Loop & Bool const shadows +// - Indirect command buffer : Const/Reg save +// - Quad vertices & texture coordinates +// - Indirect command buffer : Gmem save +// - Indirect command buffer : Gmem restore +// - Unused (padding to 8KB boundary) +// <1K - Texture Constant Shadow (768 bytes) (8K aligned) +// 18K - Shader Instruction Shadow +// - 6K vertex (32 byte aligned) +// - 6K pixel (32 byte aligned) +// - 6K shared (32 byte aligned) +// +// Note: Reading constants into a shadow, one at a time using REG_TO_MEM, takes +// 3 DWORDS per DWORD transfered, plus 1 DWORD for the shadow, for a total of +// 16 bytes per constant. If the texture constants were transfered this way, +// the Command & Vertex Buffers section would extend past the 16K boundary. +// By moving the texture constant shadow area to start at 16KB boundary, we +// only require approximately 40 bytes more memory, but are able to use the +// LOAD_CONSTANT_CONTEXT shadowing feature for the textures, speeding up +// context switching. +// +// [Using LOAD_CONSTANT_CONTEXT shadowing feature for the Loop and/or Bool +// constants would require an additional 8KB each, for alignment.] +// +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// Constants +////////////////////////////////////////////////////////////////////////////// + +#define ALU_CONSTANTS 2048 // DWORDS +#define NUM_REGISTERS 1024 // DWORDS +#ifdef DISABLE_SHADOW_WRITES + #define CMD_BUFFER_LEN 9216 // DWORDS +#else + #define CMD_BUFFER_LEN 3072 // DWORDS +#endif +#define TEX_CONSTANTS (32*6) // DWORDS +#define BOOL_CONSTANTS 8 // DWORDS +#define LOOP_CONSTANTS 56 // DWORDS +#define SHADER_INSTRUCT_LOG2 9U // 2^n == SHADER_INSTRUCTIONS + +#if defined(PM4_IM_STORE) +#define SHADER_INSTRUCT (1<drawctxt_mutex = kos_mutex_create("gsl_drawctxt"); \ + if (!device->drawctxt_mutex) {return (GSL_FAILURE);} +#define GSL_CONTEXT_MUTEX_LOCK() kos_mutex_lock(device->drawctxt_mutex) +#define GSL_CONTEXT_MUTEX_UNLOCK() kos_mutex_unlock(device->drawctxt_mutex) +#define GSL_CONTEXT_MUTEX_FREE() kos_mutex_free(device->drawctxt_mutex); device->drawctxt_mutex = 0; +#else +#define GSL_CONTEXT_MUTEX_CREATE() +#define GSL_CONTEXT_MUTEX_LOCK() +#define GSL_CONTEXT_MUTEX_UNLOCK() +#define GSL_CONTEXT_MUTEX_FREE() +#endif + + +////////////////////////////////////////////////////////////////////////////// +// temporary work structure +////////////////////////////////////////////////////////////////////////////// + +typedef struct +{ + unsigned int *start; // Command & Vertex buffer start + unsigned int *cmd; // Next available dword in C&V buffer + + // address of buffers, needed when creating IB1 command buffers. + gpuaddr_t bool_shadow; // Address where bool constants are shadowed + gpuaddr_t loop_shadow; // Address where loop constants are shadowed + +#if defined(PM4_IM_STORE) + gpuaddr_t shader_shared; // Address of shared shader instruction shadow + gpuaddr_t shader_vertex; // Address of vertex shader instruction shadow + gpuaddr_t shader_pixel; // Address of pixel shader instruction shadow +#endif + + gpuaddr_t reg_values[2]; // Addresses in command buffer where separately handled registers are saved + gpuaddr_t chicken_restore;// Address where the TP0_CHICKEN register value is written + gpuaddr_t gmem_base; // Base gpu address of GMEM +} +ctx_t; + +////////////////////////////////////////////////////////////////////////////// +// Helper function to calculate IEEE754 single precision float values without FPU +////////////////////////////////////////////////////////////////////////////// +unsigned int uint2float( unsigned int uintval ) +{ + unsigned int exp = 0; + unsigned int frac = 0; + unsigned int u = uintval; + + // Handle zero separately + if( uintval == 0 ) return 0; + + // Find log2 of u + if(u>=0x10000) { exp+=16; u>>=16; } + if(u>=0x100 ) { exp+=8; u>>=8; } + if(u>=0x10 ) { exp+=4; u>>=4; } + if(u>=0x4 ) { exp+=2; u>>=2; } + if(u>=0x2 ) { exp+=1; u>>=1; } + + // Calculate fraction + frac = ( uintval & ( ~( 1 << exp ) ) ) << ( 23 - exp ); + + // Exp is biased by 127 and shifted 23 bits + exp = ( exp + 127 ) << 23; + + return ( exp | frac ); +} + +////////////////////////////////////////////////////////////////////////////// +// Helper function to divide two unsigned ints and return the result as a floating point value +////////////////////////////////////////////////////////////////////////////// +unsigned int uintdivide(unsigned int a, unsigned int b) +{ +#ifdef _LINUX + uint64_t a_fixed = a << 16; + uint64_t b_fixed = b << 16; +#else + unsigned int a_fixed = a << 16; + unsigned int b_fixed = b << 16; +#endif + // Assume the result is 0.fraction + unsigned int fraction; + unsigned int exp = 126; + + if( b == 0 ) return 0; + +#ifdef _LINUX + a_fixed = a_fixed << 32; + do_div(a_fixed, b_fixed); + fraction = (unsigned int)a_fixed; +#else + fraction = ((unsigned int)((((__int64)a_fixed) << 32) / (__int64)b_fixed)); +#endif + + if( fraction == 0 ) return 0; + + // Normalize + while( !(fraction & (1<<31)) ) + { + fraction <<= 1; + exp--; + } + // Remove hidden bit + fraction <<= 1; + + // Round + if( ( fraction & 0x1ff ) > 256 ) + { + int rounded = 0; + int i = 9; + + // Do the bit addition + while( !rounded ) + { + if( fraction & (1<>= 9; + + return ( ( exp << 23 ) | fraction ); +} + + + +////////////////////////////////////////////////////////////////////////////// +// context save (gmem -> sys) +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// pre-compiled vertex shader program +// +// attribute vec4 P; +// void main(void) +// { +// gl_Position = P; +// } +// +////////////////////////////////////////////////////////////////////////////// + +#define GMEM2SYS_VTX_PGM_LEN 0x12 + +static const unsigned int gmem2sys_vtx_pgm[GMEM2SYS_VTX_PGM_LEN] = { + 0x00011003, 0x00001000, 0xc2000000, + 0x00001004, 0x00001000, 0xc4000000, + 0x00001005, 0x00002000, 0x00000000, + 0x1cb81000, 0x00398a88, 0x00000003, + 0x140f803e, 0x00000000, 0xe2010100, + 0x14000000, 0x00000000, 0xe2000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// pre-compiled fragment shader program +// +// precision highp float; +// uniform vec4 clear_color; +// void main(void) +// { +// gl_FragColor = clear_color; +// } +// +////////////////////////////////////////////////////////////////////////////// + +#define GMEM2SYS_FRAG_PGM_LEN 0x0c + +static const unsigned int gmem2sys_frag_pgm[GMEM2SYS_FRAG_PGM_LEN] = { + 0x00000000, 0x1002c400, 0x10000000, + 0x00001003, 0x00002000, 0x00000000, + 0x140f8000, 0x00000000, 0x22000000, + 0x14000000, 0x00000000, 0xe2000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// context restore (sys -> gmem) +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// pre-compiled vertex shader program +// +// attribute vec4 position; +// attribute vec4 texcoord; +// varying vec4 texcoord0; +// void main() +// { +// gl_Position = position; +// texcoord0 = texcoord; +// } +// +////////////////////////////////////////////////////////////////////////////// + +#define SYS2GMEM_VTX_PGM_LEN 0x18 + +static const unsigned int sys2gmem_vtx_pgm[SYS2GMEM_VTX_PGM_LEN] = { + 0x00052003, 0x00001000, 0xc2000000, 0x00001005, + 0x00001000, 0xc4000000, 0x00001006, 0x10071000, + 0x20000000, 0x18981000, 0x0039ba88, 0x00000003, + 0x12982000, 0x40257b08, 0x00000002, 0x140f803e, + 0x00000000, 0xe2010100, 0x140f8000, 0x00000000, + 0xe2020200, 0x14000000, 0x00000000, 0xe2000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// pre-compiled fragment shader program +// +// precision mediump float; +// uniform sampler2D tex0; +// varying vec4 texcoord0; +// void main() +// { +// gl_FragColor = texture2D(tex0, texcoord0.xy); +// } +// +////////////////////////////////////////////////////////////////////////////// + +#define SYS2GMEM_FRAG_PGM_LEN 0x0f + +static const unsigned int sys2gmem_frag_pgm[SYS2GMEM_FRAG_PGM_LEN] = { + 0x00011002, 0x00001000, 0xc4000000, 0x00001003, + 0x10041000, 0x20000000, 0x10000001, 0x1ffff688, + 0x00000002, 0x140f8000, 0x00000000, 0xe2000000, + 0x14000000, 0x00000000, 0xe2000000 +}; + + +////////////////////////////////////////////////////////////////////////////// +// shader texture constants (sysmem -> gmem) +////////////////////////////////////////////////////////////////////////////// + +#define SYS2GMEM_TEX_CONST_LEN 6 + +static unsigned int sys2gmem_tex_const[SYS2GMEM_TEX_CONST_LEN] = +{ + // Texture, FormatXYZW=Unsigned, ClampXYZ=Wrap/Repeat,RFMode=ZeroClamp-1,Dim=1:2d + 0x00000002, // Pitch = TBD + + // Format=6:8888_WZYX, EndianSwap=0:None, ReqSize=0:256bit, DimHi=0, NearestClamp=1:OGL Mode + 0x00000806, // Address[31:12] = TBD + + // Width, Height, EndianSwap=0:None + 0, // Width & Height = TBD + + // NumFormat=0:RF, DstSelXYZW=XYZW, ExpAdj=0, MagFilt=MinFilt=0:Point, Mip=2:BaseMap + 0 << 1 | 1 << 4 | 2 << 7 | 3 << 10 | 2 << 23, + + // VolMag=VolMin=0:Point, MinMipLvl=0, MaxMipLvl=1, LodBiasH=V=0, Dim3d=0 + 0, + + // BorderColor=0:ABGRBlack, ForceBC=0:diable, TriJuice=0, Aniso=0, Dim=1:2d, MipPacking=0 + 1 << 9 // Mip Address[31:12] = TBD +}; + + +////////////////////////////////////////////////////////////////////////////// +// quad for copying GMEM to context shadow +////////////////////////////////////////////////////////////////////////////// + +#define QUAD_LEN 12 + +static unsigned int gmem_copy_quad[QUAD_LEN] = { + 0x00000000, 0x00000000, 0x3f800000, + 0x00000000, 0x00000000, 0x3f800000, + 0x00000000, 0x00000000, 0x3f800000, + 0x00000000, 0x00000000, 0x3f800000 +}; + +#define TEXCOORD_LEN 8 + +static unsigned int gmem_copy_texcoord[TEXCOORD_LEN] = { + 0x00000000, 0x3f800000, + 0x3f800000, 0x3f800000, + 0x00000000, 0x00000000, + 0x3f800000, 0x00000000 +}; + +#define NUM_COLOR_FORMATS 13 + +static SurfaceFormat surface_format_table[NUM_COLOR_FORMATS] = +{ + FMT_4_4_4_4, // COLORX_4_4_4_4 + FMT_1_5_5_5, // COLORX_1_5_5_5 + FMT_5_6_5, // COLORX_5_6_5 + FMT_8, // COLORX_8 + FMT_8_8, // COLORX_8_8 + FMT_8_8_8_8, // COLORX_8_8_8_8 + FMT_8_8_8_8, // COLORX_S8_8_8_8 + FMT_16_FLOAT, // COLORX_16_FLOAT + FMT_16_16_FLOAT, // COLORX_16_16_FLOAT + FMT_16_16_16_16_FLOAT, // COLORX_16_16_16_16_FLOAT + FMT_32_FLOAT, // COLORX_32_FLOAT + FMT_32_32_FLOAT, // COLORX_32_32_FLOAT + FMT_32_32_32_32_FLOAT, // COLORX_32_32_32_32_FLOAT +}; + +static unsigned int format2bytesperpixel[NUM_COLOR_FORMATS] = +{ + 2, // COLORX_4_4_4_4 + 2, // COLORX_1_5_5_5 + 2, // COLORX_5_6_5 + 1, // COLORX_8 + 2, // COLORX_8_8_8 + 4, // COLORX_8_8_8_8 + 4, // COLORX_S8_8_8_8 + 2, // COLORX_16_FLOAT + 4, // COLORX_16_16_FLOAT + 8, // COLORX_16_16_16_16_FLOAT + 4, // COLORX_32_FLOAT + 8, // COLORX_32_32_FLOAT + 16, // COLORX_32_32_32_32_FLOAT +}; + +////////////////////////////////////////////////////////////////////////////// +// shader linkage info +////////////////////////////////////////////////////////////////////////////// + +#define SHADER_CONST_ADDR (11 * 6 + 3) + + +////////////////////////////////////////////////////////////////////////////// +// gmem command buffer length +////////////////////////////////////////////////////////////////////////////// + +#define PM4_REG(reg) ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg))) + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +static void +config_gmemsize(gmem_shadow_t *shadow, int gmem_size) +{ + int w=64, h=64; // 16KB surface, minimum + + // convert from bytes to 32-bit words + gmem_size = (gmem_size + 3)/4; + + // find the right surface size, close to a square. + while (w * h < gmem_size) + if (w < h) + w *= 2; + else + h *= 2; + + shadow->width = w; + shadow->height = h; + shadow->pitch = w; + shadow->format = COLORX_8_8_8_8; + shadow->size = shadow->pitch * shadow->height * 4; + + shadow->gmem_width = w; + shadow->gmem_height = h; + shadow->gmem_pitch = w; +} + + +////////////////////////////////////////////////////////////////////////////// + +static unsigned int +gpuaddr(unsigned int *cmd, gsl_memdesc_t *memdesc) +{ + return memdesc->gpuaddr + ((char *)cmd - (char *)memdesc->hostptr); +} + + +////////////////////////////////////////////////////////////////////////////// + +static void +create_ib1(gsl_drawctxt_t *drawctxt, unsigned int *cmd, unsigned int *start, unsigned int *end) +{ + cmd[0] = PM4_HDR_INDIRECT_BUFFER_PFD; + cmd[1] = gpuaddr(start, &drawctxt->gpustate); + cmd[2] = end - start; +} + + +////////////////////////////////////////////////////////////////////////////// + +static unsigned int * +program_shader(unsigned int *cmds, int vtxfrag, const unsigned int *shader_pgm, int dwords) +{ + // load the patched vertex shader stream + *cmds++ = pm4_type3_packet(PM4_IM_LOAD_IMMEDIATE, 2 + dwords); + *cmds++ = vtxfrag; // 0=vertex shader, 1=fragment shader + *cmds++ = ( (0 << 16) | dwords ); // instruction start & size (in 32-bit words) + + kos_memcpy(cmds, shader_pgm, dwords<<2); + cmds += dwords; + + return cmds; +} + + +////////////////////////////////////////////////////////////////////////////// + +static unsigned int * +reg_to_mem(unsigned int *cmds, gpuaddr_t dst, gpuaddr_t src, int dwords) +{ + while (dwords-- > 0) + { + *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmds++ = src++; + *cmds++ = dst; + dst += 4; + } + + return cmds; +} + + + +#ifdef DISABLE_SHADOW_WRITES + +static void build_reg_to_mem_range(unsigned int start, unsigned int end, unsigned int** cmd, gsl_drawctxt_t *drawctxt) +{ + unsigned int i = start; + + for(i=start; i<=end; i++) + { + *(*cmd)++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *(*cmd)++ = i | (1<<30); + *(*cmd)++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) + (i-0x2000)*4; + } +} + +#endif + +////////////////////////////////////////////////////////////////////////////// +// chicken restore +////////////////////////////////////////////////////////////////////////////// +static unsigned int* +build_chicken_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int *start = ctx->cmd; + unsigned int *cmds = start; + + *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmds++ = 0; + + *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1); + ctx->chicken_restore = gpuaddr(cmds, &drawctxt->gpustate); + *cmds++ = 0x00000000; + + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->chicken_restore, start, cmds); + + return cmds; +} + + + +////////////////////////////////////////////////////////////////////////////// +// context save +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// save h/w regs, alu constants, texture contants, etc. ... +// requires: bool_shadow_gpuaddr, loop_shadow_gpuaddr +////////////////////////////////////////////////////////////////////////////// + +static void +build_regsave_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int *start = ctx->cmd; + unsigned int *cmd = start; + +#ifdef DISABLE_SHADOW_WRITES + // Write HW registers into shadow + build_reg_to_mem_range(mmRB_SURFACE_INFO, mmRB_DEPTH_INFO, &cmd, drawctxt); + build_reg_to_mem_range(mmCOHER_DEST_BASE_0, mmPA_SC_SCREEN_SCISSOR_BR, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SC_WINDOW_OFFSET, mmPA_SC_WINDOW_SCISSOR_BR, &cmd, drawctxt); + build_reg_to_mem_range(mmVGT_MAX_VTX_INDX, mmRB_FOG_COLOR, &cmd, drawctxt); + build_reg_to_mem_range(mmRB_STENCILREFMASK_BF, mmPA_CL_VPORT_ZOFFSET, &cmd, drawctxt); + build_reg_to_mem_range(mmSQ_PROGRAM_CNTL, mmSQ_WRAPPING_1, &cmd, drawctxt); + build_reg_to_mem_range(mmRB_DEPTHCONTROL, mmRB_MODECONTROL, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SU_POINT_SIZE, mmPA_SC_LINE_STIPPLE, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SC_VIZ_QUERY, mmPA_SC_VIZ_QUERY, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SC_LINE_CNTL, mmSQ_PS_CONST, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SC_AA_MASK, mmPA_SC_AA_MASK, &cmd, drawctxt); + build_reg_to_mem_range(mmVGT_VERTEX_REUSE_BLOCK_CNTL, mmRB_DEPTH_CLEAR, &cmd, drawctxt); + build_reg_to_mem_range(mmRB_SAMPLE_COUNT_CTL, mmRB_COLOR_DEST_MASK, &cmd, drawctxt); + build_reg_to_mem_range(mmPA_SU_POLY_OFFSET_FRONT_SCALE, mmPA_SU_POLY_OFFSET_BACK_OFFSET, &cmd, drawctxt); + + // Copy ALU constants + cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr) & 0xFFFFE000, mmSQ_CONSTANT_0, ALU_CONSTANTS); + + // Copy Tex constants + cmd = reg_to_mem(cmd, (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000, mmSQ_FETCH_0, TEX_CONSTANTS); +#else + // H/w registers are already shadowed; just need to disable shadowing to prevent corruption. + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; + *cmd++ = 4 << 16; // regs, start=0 + *cmd++ = 0x0; // count = 0 + + // ALU constants are already shadowed; just need to disable shadowing to prevent corruption. + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; + *cmd++ = 0 << 16; // ALU, start=0 + *cmd++ = 0x0; // count = 0 + + // Tex constants are already shadowed; just need to disable shadowing to prevent corruption. + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; + *cmd++ = 1 << 16; // Tex, start=0 + *cmd++ = 0x0; // count = 0 +#endif + + + + + // Need to handle some of the registers separately + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmSQ_GPR_MANAGEMENT; + *cmd++ = ctx->reg_values[0]; + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmTP0_CHICKEN; + *cmd++ = ctx->reg_values[1]; + + // Copy Boolean constants + cmd = reg_to_mem(cmd, ctx->bool_shadow, mmSQ_CF_BOOLEANS, BOOL_CONSTANTS); + + // Copy Loop constants + cmd = reg_to_mem(cmd, ctx->loop_shadow, mmSQ_CF_LOOP, LOOP_CONSTANTS); + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->reg_save, start, cmd); + + ctx->cmd = cmd; +} + + +////////////////////////////////////////////////////////////////////////////// +// copy colour, depth, & stencil buffers from graphics memory to system memory +////////////////////////////////////////////////////////////////////////////// + +static unsigned int* +build_gmem2sys_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow) +{ + unsigned int *cmds = shadow->gmem_save_commands; + unsigned int *start = cmds; + + // Store TP0_CHICKEN register + *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmds++ = mmTP0_CHICKEN; + if( ctx ) + *cmds++ = ctx->chicken_restore; + else + cmds++; + + *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmds++ = 0; + + // Set TP0_CHICKEN to zero + *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1); + *cmds++ = 0x00000000; + + // -------------- + // program shader + // -------------- + + // load shader vtx constants ... 5 dwords + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); + *cmds++ = (0x1 << 16) | SHADER_CONST_ADDR; + *cmds++ = 0; + *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; // valid(?) vtx constant flag & addr + *cmds++ = 0x00000030; // limit = 12 dwords + + // Invalidate L2 cache to make sure vertices are updated + *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1); + *cmds++ = 0x1; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); + *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX); + *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX + *cmds++ = 0x0; //mmVGT_MIN_VTX_INDX + *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SC_AA_MASK); + *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK + + + // load the patched vertex shader stream + cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN); + + // Load the patched fragment shader stream + cmds = program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN); + + // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL); + *cmds++ = 0x10010001; + *cmds++ = 0x00000008; + + + // -------------- + // resolve + // -------------- + + // PA_CL_VTE_CNTL + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL); + *cmds++ = 0x00000b00; // disable X/Y/Z transforms, X/Y/Z are premultiplied by W + + // change colour buffer to RGBA8888, MSAA = 1, and matching pitch + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmRB_SURFACE_INFO); + *cmds++ = shadow->gmem_pitch; + + // RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base + if( ctx ) + { + KOS_ASSERT((ctx->gmem_base & 0xFFF) == 0); // gmem base assumed 4K aligned. + *cmds++ = (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base; + } + else + { + unsigned int temp = *cmds; + *cmds++ = (temp & ~RB_COLOR_INFO__COLOR_FORMAT_MASK) | (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT); + } + + // disable Z + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_DEPTHCONTROL); + *cmds++ = 0; + + // set mmPA_SU_SC_MODE_CNTL + // Front_ptype = draw triangles + // Back_ptype = draw triangles + // Provoking vertex = last + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL); + *cmds++ = 0x00080240; + + // set the scissor to the extents of the draw surface + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL); + *cmds++ = (shadow->gmem_offset_y << 16) | shadow->gmem_offset_x; + *cmds++ = (shadow->gmem_height << 16) | shadow->gmem_width; + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL); + *cmds++ = (1U << 31) | (0 << 16) | 0; + *cmds++ = (shadow->height << 16) | shadow->width; + + // load the viewport so that z scale = clear depth and z offset = 0.0f + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE); + *cmds++ = 0xbf800000; // -1.0f + *cmds++ = 0x0; + + // load the COPY state + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 6); + *cmds++ = PM4_REG(mmRB_COPY_CONTROL); + *cmds++ = 0; // RB_COPY_CONTROL + + { + // Calculate the new offset based on the adjusted base + unsigned int bytesperpixel = format2bytesperpixel[shadow->format]; + unsigned int addr = (shadow->gmemshadow.gpuaddr + shadow->offset * bytesperpixel); + unsigned int offset = (addr - (addr & 0xfffff000)) / bytesperpixel; + + *cmds++ = addr & 0xfffff000; // RB_COPY_DEST_BASE + *cmds++ = shadow->pitch >> 5; // RB_COPY_DEST_PITCH + *cmds++ = 0x0003c008 | (shadow->format << RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT); // Endian=none, Linear, Format=RGBA8888,Swap=0,!Dither,MaskWrite:R=G=B=A=1 + + KOS_ASSERT( (offset & 0xfffff000) == 0 ); // Make sure we stay in offsetx field. + *cmds++ = offset; + } + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_MODECONTROL); + *cmds++ = 0x6; // EDRAM copy + + // queue the draw packet + *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2); + *cmds++ = 0; // viz query info. + *cmds++ = 0x00030088; // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, shadow->gmem_save, start, cmds); + + return cmds; +} + + +////////////////////////////////////////////////////////////////////////////// +// context restore +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// copy colour, depth, & stencil buffers from system memory to graphics memory +////////////////////////////////////////////////////////////////////////////// + +static unsigned int* +build_sys2gmem_cmds(gsl_drawctxt_t *drawctxt, ctx_t* ctx, gmem_shadow_t *shadow) +{ + unsigned int *cmds = shadow->gmem_restore_commands; + unsigned int *start = cmds; + + // Store TP0_CHICKEN register + *cmds++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmds++ = mmTP0_CHICKEN; + if( ctx ) + *cmds++ = ctx->chicken_restore; + else + cmds++; + + *cmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmds++ = 0; + + // Set TP0_CHICKEN to zero + *cmds++ = pm4_type0_packet(mmTP0_CHICKEN, 1); + *cmds++ = 0x00000000; + + // ---------------- + // shader constants + // ---------------- + + // vertex buffer constants + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 7); + + *cmds++ = (0x1 << 16) | (9 * 6); + *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; // valid(?) vtx constant flag & addr + *cmds++ = 0x00000030; // limit = 12 dwords + *cmds++ = shadow->quad_texcoords.gpuaddr | 0x3; // valid(?) vtx constant flag & addr + *cmds++ = 0x00000020; // limit = 8 dwords + *cmds++ = 0; + *cmds++ = 0; + + // Invalidate L2 cache to make sure vertices and texture coordinates are updated + *cmds++ = pm4_type0_packet(mmTC_CNTL_STATUS, 1); + *cmds++ = 0x1; + + // load the patched vertex shader stream + cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN); + + // Load the patched fragment shader stream + cmds = program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN); + + // SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmSQ_PROGRAM_CNTL); + *cmds++ = 0x10030002; + *cmds++ = 0x00000008; + + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SC_AA_MASK); + *cmds++ = 0x0000ffff; //mmPA_SC_AA_MASK + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SC_VIZ_QUERY); + *cmds++ = 0x0; //mmPA_SC_VIZ_QUERY + + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_COLORCONTROL); + *cmds++ = 0x00000c20; // RB_COLORCONTROL + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 4); + *cmds++ = PM4_REG(mmVGT_MAX_VTX_INDX); + *cmds++ = 0x00ffffff; //mmVGT_MAX_VTX_INDX + *cmds++ = 0x0; //mmVGT_MIN_VTX_INDX + *cmds++ = 0x00000000; //mmVGT_INDX_OFFSET + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmVGT_VERTEX_REUSE_BLOCK_CNTL); + *cmds++ = 0x00000002; //mmVGT_VERTEX_REUSE_BLOCK_CNTL + *cmds++ = 0x00000002; //mmVGT_OUT_DEALLOC_CNTL + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmSQ_INTERPOLATOR_CNTL); + *cmds++ = 0xffffffff; //mmSQ_INTERPOLATOR_CNTL + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SC_AA_CONFIG); + *cmds++ = 0x00000000; //mmPA_SC_AA_CONFIG + + + // set mmPA_SU_SC_MODE_CNTL + // Front_ptype = draw triangles + // Back_ptype = draw triangles + // Provoking vertex = last + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_SU_SC_MODE_CNTL); + *cmds++ = 0x00080240; + + // texture constants + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1)); + *cmds++ = (0x1 << 16) | (0 * 6); + kos_memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN<<2); + cmds[0] |= (shadow->pitch >> 5) << 22; + cmds[1] |= shadow->gmemshadow.gpuaddr | surface_format_table[shadow->format]; + cmds[2] |= (shadow->width+shadow->offset_x-1) | (shadow->height+shadow->offset_y-1) << 13; + cmds += SYS2GMEM_TEX_CONST_LEN; + + // change colour buffer to RGBA8888, MSAA = 1, and matching pitch + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmRB_SURFACE_INFO); + *cmds++ = shadow->gmem_pitch; // GMEM pitch is equal to context GMEM shadow pitch + + // RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0, Base=gmem_base + if( ctx ) + { + *cmds++ = (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | ctx->gmem_base; + } + else + { + unsigned int temp = *cmds; + *cmds++ = (temp & ~RB_COLOR_INFO__COLOR_FORMAT_MASK) | (shadow->format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT); + } + + // RB_DEPTHCONTROL + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_DEPTHCONTROL); + *cmds++ = 0; // disable Z + + // set the scissor to the extents of the draw surface + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_SC_SCREEN_SCISSOR_TL); + *cmds++ = (0 << 16) | 0; + *cmds++ = (shadow->height << 16) | shadow->width; + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_SC_WINDOW_SCISSOR_TL); + *cmds++ = (1U << 31) | (shadow->gmem_offset_y << 16) | shadow->gmem_offset_x; + *cmds++ = (shadow->gmem_height << 16) | shadow->gmem_width; + + // PA_CL_VTE_CNTL + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmPA_CL_VTE_CNTL); + *cmds++ = 0x00000b00; // disable X/Y/Z transforms, X/Y/Z are premultiplied by W + + // load the viewport so that z scale = clear depth and z offset = 0.0f + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmPA_CL_VPORT_ZSCALE); + *cmds++ = 0xbf800000; + *cmds++ = 0x0; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_COLOR_MASK); + *cmds++ = 0x0000000f; // R = G = B = 1:enabled + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_COLOR_DEST_MASK); + *cmds++ = 0xffffffff; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 3); + *cmds++ = PM4_REG(mmSQ_WRAPPING_0); + *cmds++ = 0x00000000; + *cmds++ = 0x00000000; + + *cmds++ = pm4_type3_packet(PM4_SET_CONSTANT, 2); + *cmds++ = PM4_REG(mmRB_MODECONTROL); + *cmds++ = 0x4; // draw pixels with color and depth/stencil component + + // queue the draw packet + *cmds++ = pm4_type3_packet(PM4_DRAW_INDX, 2); + *cmds++ = 0; // viz query info. + *cmds++ = 0x00030088; // PrimType=RectList, NumIndices=3, SrcSel=AutoIndex + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, shadow->gmem_restore, start, cmds); + + return cmds; +} + + +////////////////////////////////////////////////////////////////////////////// +// restore h/w regs, alu constants, texture constants, etc. ... +////////////////////////////////////////////////////////////////////////////// + +static unsigned * +reg_range(unsigned int *cmd, unsigned int start, unsigned int end) +{ + *cmd++ = PM4_REG(start); // h/w regs, start addr + *cmd++ = end - start + 1; // count + return cmd; +} + + +////////////////////////////////////////////////////////////////////////////// + +static void +build_regrestore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int *start = ctx->cmd; + unsigned int *cmd = start; + + // H/W Registers + cmd++; // deferred pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, ???); +#ifdef DISABLE_SHADOW_WRITES + *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; // Force mismatch +#else + *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; +#endif + + cmd = reg_range(cmd, mmRB_SURFACE_INFO, mmPA_SC_SCREEN_SCISSOR_BR); + cmd = reg_range(cmd, mmPA_SC_WINDOW_OFFSET, mmPA_SC_WINDOW_SCISSOR_BR); + cmd = reg_range(cmd, mmVGT_MAX_VTX_INDX, mmPA_CL_VPORT_ZOFFSET); + cmd = reg_range(cmd, mmSQ_PROGRAM_CNTL, mmSQ_WRAPPING_1); + cmd = reg_range(cmd, mmRB_DEPTHCONTROL, mmRB_MODECONTROL); + cmd = reg_range(cmd, mmPA_SU_POINT_SIZE, mmPA_SC_VIZ_QUERY); + cmd = reg_range(cmd, mmPA_SC_LINE_CNTL, mmRB_COLOR_DEST_MASK); + cmd = reg_range(cmd, mmPA_SU_POLY_OFFSET_FRONT_SCALE, mmPA_SU_POLY_OFFSET_BACK_OFFSET); + + // Now we know how many register blocks we have, we can compute command length + start[0] = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, (cmd-start)-1); +#ifdef DISABLE_SHADOW_WRITES + start[2] |= (0<<24) | (4 << 16); // Disable shadowing. +#else + start[2] |= (1<<24) | (4 << 16); // Enable shadowing for the entire register block. +#endif + + // Need to handle some of the registers separately + *cmd++ = pm4_type0_packet(mmSQ_GPR_MANAGEMENT, 1); + ctx->reg_values[0] = gpuaddr(cmd, &drawctxt->gpustate); + *cmd++ = 0x00040400; + + *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmd++ = 0; + *cmd++ = pm4_type0_packet(mmTP0_CHICKEN, 1); + ctx->reg_values[1] = gpuaddr(cmd, &drawctxt->gpustate); + *cmd++ = 0x00000000; + + // ALU Constants + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; +#ifdef DISABLE_SHADOW_WRITES + *cmd++ = (0<<24) | (0<<16) | 0; // Disable shadowing +#else + *cmd++ = (1<<24) | (0<<16) | 0; +#endif + *cmd++ = ALU_CONSTANTS; + + + // Texture Constants + *cmd++ = pm4_type3_packet(PM4_LOAD_CONSTANT_CONTEXT, 3); + *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; +#ifdef DISABLE_SHADOW_WRITES + *cmd++ = (0<<24) | (1<<16) | 0; // Disable shadowing +#else + *cmd++ = (1<<24) | (1<<16) | 0; +#endif + *cmd++ = TEX_CONSTANTS; + + + // Boolean Constants + *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + BOOL_CONSTANTS); + *cmd++ = (2<<16) | 0; + + // the next BOOL_CONSTANT dwords is the shadow area for boolean constants. + ctx->bool_shadow = gpuaddr(cmd, &drawctxt->gpustate); + cmd += BOOL_CONSTANTS; + + + // Loop Constants + *cmd++ = pm4_type3_packet(PM4_SET_CONSTANT, 1 + LOOP_CONSTANTS); + *cmd++ = (3<<16) | 0; + + // the next LOOP_CONSTANTS dwords is the shadow area for loop constants. + ctx->loop_shadow = gpuaddr(cmd, &drawctxt->gpustate); + cmd += LOOP_CONSTANTS; + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->reg_restore, start, cmd); + + ctx->cmd = cmd; +} + + +////////////////////////////////////////////////////////////////////////////// +// quad for saving/restoring gmem +////////////////////////////////////////////////////////////////////////////// + +static void set_gmem_copy_quad( gmem_shadow_t* shadow ) +{ + unsigned int tex_offset[2]; + + // set vertex buffer values + + gmem_copy_quad[1] = uint2float( shadow->gmem_height + shadow->gmem_offset_y ); + gmem_copy_quad[3] = uint2float( shadow->gmem_width + shadow->gmem_offset_x ); + gmem_copy_quad[4] = uint2float( shadow->gmem_height + shadow->gmem_offset_y ); + gmem_copy_quad[9] = uint2float( shadow->gmem_width + shadow->gmem_offset_x ); + + gmem_copy_quad[0] = uint2float( shadow->gmem_offset_x ); + gmem_copy_quad[6] = uint2float( shadow->gmem_offset_x ); + gmem_copy_quad[7] = uint2float( shadow->gmem_offset_y ); + gmem_copy_quad[10] = uint2float( shadow->gmem_offset_y ); + + tex_offset[0] = uintdivide( shadow->offset_x, (shadow->offset_x+shadow->width) ); + tex_offset[1] = uintdivide( shadow->offset_y, (shadow->offset_y+shadow->height) ); + + gmem_copy_texcoord[0] = gmem_copy_texcoord[4] = tex_offset[0]; + gmem_copy_texcoord[5] = gmem_copy_texcoord[7] = tex_offset[1]; + + // copy quad data to vertex buffer + kos_memcpy(shadow->quad_vertices.hostptr, gmem_copy_quad, QUAD_LEN << 2); + + // copy tex coord data to tex coord buffer + kos_memcpy(shadow->quad_texcoords.hostptr, gmem_copy_texcoord, TEXCOORD_LEN << 2); +} + + +static void +build_quad_vtxbuff(gsl_drawctxt_t *drawctxt, ctx_t *ctx, gmem_shadow_t* shadow) +{ + unsigned int *cmd = ctx->cmd; + + // quad vertex buffer location + shadow->quad_vertices.hostptr = cmd; + shadow->quad_vertices.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate); + cmd += QUAD_LEN; + + // tex coord buffer location (in GPU space) + shadow->quad_texcoords.hostptr = cmd; + shadow->quad_texcoords.gpuaddr = gpuaddr(cmd, &drawctxt->gpustate); + + + cmd += TEXCOORD_LEN; + + set_gmem_copy_quad(shadow); + + + ctx->cmd = cmd; +} + + +////////////////////////////////////////////////////////////////////////////// + +static void +build_shader_save_restore_cmds(gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int *cmd = ctx->cmd; + unsigned int *save, *restore, *fixup; +#if defined(PM4_IM_STORE) + unsigned int *startSizeVtx, *startSizePix, *startSizeShared; +#endif + unsigned int *partition1; + unsigned int *shaderBases, *partition2; + +#if defined(PM4_IM_STORE) + // compute vertex, pixel and shared instruction shadow GPU addresses + ctx->shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET; + ctx->shader_pixel = ctx->shader_vertex + SHADER_SHADOW_SIZE; + ctx->shader_shared = ctx->shader_pixel + SHADER_SHADOW_SIZE; +#endif + + + //------------------------------------------------------------------- + // restore shader partitioning and instructions + //------------------------------------------------------------------- + + restore = cmd; // start address + + // Invalidate Vertex & Pixel instruction code address and sizes + *cmd++ = pm4_type3_packet(PM4_INVALIDATE_STATE, 1); + *cmd++ = 0x00000300; // 0x100 = Vertex, 0x200 = Pixel + + // Restore previous shader vertex & pixel instruction bases. + *cmd++ = pm4_type3_packet(PM4_SET_SHADER_BASES, 1); + shaderBases = cmd++; // TBD #5: shader bases (from fixup) + + // write the shader partition information to a scratch register + *cmd++ = pm4_type0_packet(mmSQ_INST_STORE_MANAGMENT, 1); + partition1 = cmd++; // TBD #4a: partition info (from save) + +#if defined(PM4_IM_STORE) + // load vertex shader instructions from the shadow. + *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); + *cmd++ = ctx->shader_vertex + 0x0; // 0x0 = Vertex + startSizeVtx = cmd++; // TBD #1: start/size (from save) + + // load pixel shader instructions from the shadow. + *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); + *cmd++ = ctx->shader_pixel + 0x1; // 0x1 = Pixel + startSizePix = cmd++; // TBD #2: start/size (from save) + + // load shared shader instructions from the shadow. + *cmd++ = pm4_type3_packet(PM4_IM_LOAD, 2); + *cmd++ = ctx->shader_shared + 0x2; // 0x2 = Shared + startSizeShared = cmd++; // TBD #3: start/size (from save) +#endif + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd); + + + //------------------------------------------------------------------- + // fixup SET_SHADER_BASES data + // + // since self-modifying PM4 code is being used here, a seperate + // command buffer is used for this fixup operation, to ensure the + // commands are not read by the PM4 engine before the data fields + // have been written. + //------------------------------------------------------------------- + + fixup = cmd; // start address + + // write the shader partition information to a scratch register + *cmd++ = pm4_type0_packet(mmSCRATCH_REG2, 1); + partition2 = cmd++; // TBD #4b: partition info (from save) + + // mask off unused bits, then OR with shader instruction memory size + *cmd++ = pm4_type3_packet(PM4_REG_RMW, 3); + *cmd++ = mmSCRATCH_REG2; + *cmd++ = 0x0FFF0FFF; // AND off invalid bits. + *cmd++ = (unsigned int)((SHADER_INSTRUCT_LOG2-5U) << 29); // OR in instruction memory size + + // write the computed value to the SET_SHADER_BASES data field + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmSCRATCH_REG2; + *cmd++ = gpuaddr(shaderBases, &drawctxt->gpustate); // TBD #5: shader bases (to restore) + + // create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd); + + + //------------------------------------------------------------------- + // save shader partitioning and instructions + //------------------------------------------------------------------- + + save = cmd; // start address + + *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmd++ = 0; + + // Fetch the SQ_INST_STORE_MANAGMENT register value, + // Store the value in the data fields of the SET_CONSTANT commands above. + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmSQ_INST_STORE_MANAGMENT; + *cmd++ = gpuaddr(partition1, &drawctxt->gpustate); // TBD #4a: partition info (to restore) + *cmd++ = pm4_type3_packet(PM4_REG_TO_MEM, 2); + *cmd++ = mmSQ_INST_STORE_MANAGMENT; + *cmd++ = gpuaddr(partition2, &drawctxt->gpustate); // TBD #4b: partition info (to fixup) + +#if defined(PM4_IM_STORE) + // Store the vertex shader instructions + *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); + *cmd++ = ctx->shader_vertex + 0x0; // 0x0 = Vertex + *cmd++ = gpuaddr(startSizeVtx, &drawctxt->gpustate); // TBD #1: start/size (to restore) + + // store the pixel shader instructions + *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); + *cmd++ = ctx->shader_pixel + 0x1; // 0x1 = Pixel + *cmd++ = gpuaddr(startSizePix, &drawctxt->gpustate); // TBD #2: start/size (to restore) + + // Store the shared shader instructions + *cmd++ = pm4_type3_packet(PM4_IM_STORE, 2); + *cmd++ = ctx->shader_shared + 0x2; // 0x2 = Shared + *cmd++ = gpuaddr(startSizeShared, &drawctxt->gpustate); // TBD #3: start/size (to restore) +#endif + + *cmd++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *cmd++ = 0; + + + + // Create indirect buffer command for above command sequence + create_ib1(drawctxt, drawctxt->shader_save, save, cmd); + + + ctx->cmd = cmd; +} + + + +////////////////////////////////////////////////////////////////////////////// +// create buffers for saving/restoring registers and constants +////////////////////////////////////////////////////////////////////////////// + +static int +create_gpustate_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + gsl_flags_t flags; + + flags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K); + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_EMEM | GSL_MEMFLAGS_ALIGN8K)); + + // allocate memory to allow HW to save sub-blocks for efficient context save/restore + if (kgsl_sharedmem_alloc0(device->id, flags, CONTEXT_SIZE, &drawctxt->gpustate) != GSL_SUCCESS) + return GSL_FAILURE; + + drawctxt->flags |= CTXT_FLAGS_STATE_SHADOW; + + // Blank out h/w register, constant, and command buffer shadows. + kgsl_sharedmem_set0(&drawctxt->gpustate, 0, 0, CONTEXT_SIZE); + + // set-up command and vertex buffer pointers + ctx->cmd = ctx->start = (unsigned int *) ((char *)drawctxt->gpustate.hostptr + CMD_OFFSET); + + // build indirect command buffers to save & restore regs/constants + build_regrestore_cmds(drawctxt, ctx); + build_regsave_cmds(drawctxt, ctx); + + build_shader_save_restore_cmds(drawctxt, ctx); + + return GSL_SUCCESS; +} + + +////////////////////////////////////////////////////////////////////////////// +// Allocate GMEM shadow buffer +////////////////////////////////////////////////////////////////////////////// +static int +allocate_gmem_shadow_buffer(gsl_device_t *device, gsl_drawctxt_t *drawctxt) +{ + // allocate memory for GMEM shadow + if (kgsl_sharedmem_alloc0(device->id, (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGN8K), + drawctxt->context_gmem_shadow.size, &drawctxt->context_gmem_shadow.gmemshadow) != GSL_SUCCESS) + return GSL_FAILURE; + + // blank out gmem shadow. + kgsl_sharedmem_set0(&drawctxt->context_gmem_shadow.gmemshadow, 0, 0, drawctxt->context_gmem_shadow.size); + + return GSL_SUCCESS; +} + + +////////////////////////////////////////////////////////////////////////////// +// create GMEM save/restore specific stuff +////////////////////////////////////////////////////////////////////////////// + +static int +create_gmem_shadow(gsl_device_t *device, gsl_drawctxt_t *drawctxt, ctx_t *ctx) +{ + unsigned int i; + config_gmemsize(&drawctxt->context_gmem_shadow, device->gmemspace.sizebytes); + ctx->gmem_base = device->gmemspace.gpu_base; + + if( drawctxt->flags & CTXT_FLAGS_GMEM_SHADOW ) + { + if( allocate_gmem_shadow_buffer(device, drawctxt) != GSL_SUCCESS ) + return GSL_FAILURE; + } + else + { + kos_memset( &drawctxt->context_gmem_shadow.gmemshadow, 0, sizeof( gsl_memdesc_t ) ); + } + + // build quad vertex buffer + build_quad_vtxbuff(drawctxt, ctx, &drawctxt->context_gmem_shadow); + + // build TP0_CHICKEN register restore command buffer + ctx->cmd = build_chicken_restore_cmds(drawctxt, ctx); + + // build indirect command buffers to save & restore gmem + drawctxt->context_gmem_shadow.gmem_save_commands = ctx->cmd; + ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow); + drawctxt->context_gmem_shadow.gmem_restore_commands = ctx->cmd; + ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->context_gmem_shadow); + + for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ ) + { + // build quad vertex buffer + build_quad_vtxbuff(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]); + + // build indirect command buffers to save & restore gmem + drawctxt->user_gmem_shadow[i].gmem_save_commands = ctx->cmd; + ctx->cmd = build_gmem2sys_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]); + + drawctxt->user_gmem_shadow[i].gmem_restore_commands = ctx->cmd; + ctx->cmd = build_sys2gmem_cmds(drawctxt, ctx, &drawctxt->user_gmem_shadow[i]); + } + + return GSL_SUCCESS; +} + + +////////////////////////////////////////////////////////////////////////////// +// init draw context +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_drawctxt_init(gsl_device_t *device) +{ + GSL_CONTEXT_MUTEX_CREATE(); + + return (GSL_SUCCESS); +} + + +////////////////////////////////////////////////////////////////////////////// +// close draw context +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_drawctxt_close(gsl_device_t *device) +{ + GSL_CONTEXT_MUTEX_FREE(); + + return (GSL_SUCCESS); +} + + +////////////////////////////////////////////////////////////////////////////// +// create a new drawing context +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags) +{ + gsl_drawctxt_t *drawctxt; + int index; + ctx_t ctx; + + kgsl_device_active(device); + + GSL_CONTEXT_MUTEX_LOCK(); + if (device->drawctxt_count >= GSL_CONTEXT_MAX) + { + GSL_CONTEXT_MUTEX_UNLOCK(); + return (GSL_FAILURE); + } + + // find a free context slot + index = 0; + while (index < GSL_CONTEXT_MAX) + { + if (device->drawctxt[index].flags == CTXT_FLAGS_NOT_IN_USE) + break; + + index++; + } + + if (index >= GSL_CONTEXT_MAX) + { + GSL_CONTEXT_MUTEX_UNLOCK(); + return (GSL_FAILURE); + } + + drawctxt = &device->drawctxt[index]; + + kos_memset( &drawctxt->context_gmem_shadow, 0, sizeof( gmem_shadow_t ) ); + + drawctxt->pid = GSL_CALLER_PROCESSID_GET(); + drawctxt->flags = CTXT_FLAGS_IN_USE; + drawctxt->type = type; + + device->drawctxt_count++; + + // create context shadows, when not running in safe mode + if (!(device->flags & GSL_FLAGS_SAFEMODE)) + { + if (create_gpustate_shadow(device, drawctxt, &ctx) != GSL_SUCCESS) + { + kgsl_drawctxt_destroy(device, index); + GSL_CONTEXT_MUTEX_UNLOCK(); + return (GSL_FAILURE); + } + + // Save the shader instruction memory & GMEM on context switching + drawctxt->flags |= ( CTXT_FLAGS_SHADER_SAVE | CTXT_FLAGS_GMEM_SHADOW ); + + // Clear out user defined GMEM shadow buffer structs + kos_memset( drawctxt->user_gmem_shadow, 0, sizeof(gmem_shadow_t)*GSL_MAX_GMEM_SHADOW_BUFFERS ); + + // create gmem shadow + if (create_gmem_shadow(device, drawctxt, &ctx) != GSL_SUCCESS) + { + kgsl_drawctxt_destroy(device, index); + GSL_CONTEXT_MUTEX_UNLOCK(); + return (GSL_FAILURE); + } + + KOS_ASSERT(ctx.cmd - ctx.start <= CMD_BUFFER_LEN); + } + + *drawctxt_id = index; + + GSL_CONTEXT_MUTEX_UNLOCK(); + return (GSL_SUCCESS); +} + + +////////////////////////////////////////////////////////////////////////////// +// destroy a drawing context +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id) +{ + gsl_drawctxt_t *drawctxt; + + GSL_CONTEXT_MUTEX_LOCK(); + + drawctxt = &device->drawctxt[drawctxt_id]; + + if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE) + { + // deactivate context + if (device->drawctxt_active == drawctxt) + { + // no need to save GMEM or shader, the context is being destroyed. + drawctxt->flags &= ~(CTXT_FLAGS_GMEM_SAVE | CTXT_FLAGS_SHADER_SAVE); + + kgsl_drawctxt_switch(device, GSL_CONTEXT_NONE, 0); + } + + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + + // destroy state shadow, if allocated + if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW) + kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET()); + + + // destroy gmem shadow, if allocated + if (drawctxt->context_gmem_shadow.gmemshadow.size > 0) + { + kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET()); + drawctxt->context_gmem_shadow.gmemshadow.size = 0; + } + + drawctxt->flags = CTXT_FLAGS_NOT_IN_USE; + drawctxt->pid = 0; + + device->drawctxt_count--; + KOS_ASSERT(device->drawctxt_count >= 0); + } + + GSL_CONTEXT_MUTEX_UNLOCK(); + + return (GSL_SUCCESS); +} + +////////////////////////////////////////////////////////////////////////////// +// Binds a user specified buffer as GMEM shadow area +// +// gmem_rect: defines the rectangle that is copied from GMEM. X and Y +// coordinates need to be multiples of 8 after conversion to 32bpp. +// X, Y, width, and height need to be at 32-bit boundary to avoid +// rounding. +// +// shadow_x & shadow_y: Position in GMEM shadow buffer where the contents of +// gmem_rect is copied. Both must be multiples of 8 after +// conversion to 32bpp. They also need to be at 32-bit +// boundary to avoid rounding. +// +// shadow_buffer: Description of the GMEM shadow buffer. BPP needs to be +// 8, 16, 32, 64, or 128. Enabled tells if the buffer is +// used or not (values 0 and 1). All the other buffer +// parameters are ignored when enabled=0. +// +// buffer_id: Two different buffers can be defined. Use buffer IDs 0 and 1. +// +// +////////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id) +{ + gsl_device_t *device = &gsl_driver.device[device_id-1]; + gsl_drawctxt_t *drawctxt = &device->drawctxt[drawctxt_id]; + gmem_shadow_t *shadow = &drawctxt->user_gmem_shadow[buffer_id]; + unsigned int i; + + GSL_API_MUTEX_LOCK(); + GSL_CONTEXT_MUTEX_LOCK(); + + if( !shadow_buffer->enabled ) + { + // Disable shadow + shadow->gmemshadow.size = 0; + } + else + { + // Sanity checks + KOS_ASSERT((gmem_rect->x % 2) == 0); // Needs to be a multiple of 2 + KOS_ASSERT((gmem_rect->y % 2) == 0); // Needs to be a multiple of 2 + KOS_ASSERT((gmem_rect->width % 2) == 0); // Needs to be a multiple of 2 + KOS_ASSERT((gmem_rect->height % 2) == 0); // Needs to be a multiple of 2 + KOS_ASSERT((gmem_rect->pitch % 32) == 0); // Needs to be a multiple of 32 + + KOS_ASSERT((shadow_x % 2) == 0); // Needs to be a multiple of 2 + KOS_ASSERT((shadow_y % 2) == 0); // Needs to be a multiple of 2 + + KOS_ASSERT(shadow_buffer->format >= COLORX_4_4_4_4); + KOS_ASSERT(shadow_buffer->format <= COLORX_32_32_32_32_FLOAT); + KOS_ASSERT((shadow_buffer->pitch % 32) == 0); // Needs to be a multiple of 32 + KOS_ASSERT(buffer_id >= 0); + KOS_ASSERT(buffer_id < GSL_MAX_GMEM_SHADOW_BUFFERS); + + // Set up GMEM shadow regions + kos_memcpy( &shadow->gmemshadow, &shadow_buffer->data, sizeof( gsl_memdesc_t ) ); + shadow->size = shadow->gmemshadow.size; + + shadow->width = shadow_buffer->width; + shadow->height = shadow_buffer->height; + shadow->pitch = shadow_buffer->pitch; + shadow->format = shadow_buffer->format; + + shadow->offset = shadow->pitch * (shadow_y - gmem_rect->y) + shadow_x - gmem_rect->x; + + shadow->offset_x = shadow_x; + shadow->offset_y = shadow_y; + + shadow->gmem_width = gmem_rect->width; + shadow->gmem_height = gmem_rect->height; + shadow->gmem_pitch = gmem_rect->pitch; + + shadow->gmem_offset_x = gmem_rect->x; + shadow->gmem_offset_y = gmem_rect->y; + + // Modify quad vertices + set_gmem_copy_quad(shadow); + + // Modify commands + build_gmem2sys_cmds(drawctxt, NULL, shadow); + build_sys2gmem_cmds(drawctxt, NULL, shadow); + + // Release context GMEM shadow if found + if (drawctxt->context_gmem_shadow.gmemshadow.size > 0) + { + kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET()); + drawctxt->context_gmem_shadow.gmemshadow.size = 0; + } + } + + // Enable GMEM shadowing if we have any of the user buffers enabled + drawctxt->flags &= ~CTXT_FLAGS_GMEM_SHADOW; + for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ ) + { + if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 ) + { + drawctxt->flags |= CTXT_FLAGS_GMEM_SHADOW; + } + } + + GSL_CONTEXT_MUTEX_UNLOCK(); + GSL_API_MUTEX_UNLOCK(); + + return (GSL_SUCCESS); +} + + + +////////////////////////////////////////////////////////////////////////////// +// switch drawing contexts +////////////////////////////////////////////////////////////////////////////// + +void +kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags) +{ + gsl_drawctxt_t *active_ctxt = device->drawctxt_active; + + if (drawctxt != GSL_CONTEXT_NONE) + { + if( flags & GSL_CONTEXT_SAVE_GMEM ) + { + // Set the flag in context so that the save is done when this context is switched out. + drawctxt->flags |= CTXT_FLAGS_GMEM_SAVE; + } + else + { + // Remove GMEM saving flag from the context + drawctxt->flags &= ~CTXT_FLAGS_GMEM_SAVE; + } + } + + // already current? + if (active_ctxt == drawctxt) + { + return; + } + + // save old context, when not running in safe mode + if (active_ctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE)) + { + // save registers and constants. + kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->reg_save, 3, active_ctxt->pid); + + if (active_ctxt->flags & CTXT_FLAGS_SHADER_SAVE) + { + // save shader partitioning and instructions. + kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->shader_save, 3, active_ctxt->pid); + + // fixup shader partitioning parameter for SET_SHADER_BASES. + kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->shader_fixup, 3, active_ctxt->pid); + + active_ctxt->flags |= CTXT_FLAGS_SHADER_RESTORE; + } + + if (active_ctxt->flags & CTXT_FLAGS_GMEM_SHADOW && active_ctxt->flags & CTXT_FLAGS_GMEM_SAVE ) + { + // save gmem. (note: changes shader. shader must already be saved.) + + unsigned int i, numbuffers = 0; + + for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ ) + { + if( active_ctxt->user_gmem_shadow[i].gmemshadow.size > 0 ) + { + kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->user_gmem_shadow[i].gmem_save, 3, active_ctxt->pid); + + // Restore TP0_CHICKEN + kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid); + numbuffers++; + } + } + if( numbuffers == 0 ) + { + // No user defined buffers -> use context default + kgsl_ringbuffer_issuecmds(device, 1, active_ctxt->context_gmem_shadow.gmem_save, 3, active_ctxt->pid); + // Restore TP0_CHICKEN + kgsl_ringbuffer_issuecmds(device, 0, active_ctxt->chicken_restore, 3, active_ctxt->pid); + } + + active_ctxt->flags |= CTXT_FLAGS_GMEM_RESTORE; + } + } + + device->drawctxt_active = drawctxt; + + // restore new context, when not running in safe mode + if (drawctxt != GSL_CONTEXT_NONE && !(device->flags & GSL_FLAGS_SAFEMODE)) + { + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, drawctxt->gpustate.gpuaddr, (unsigned int)drawctxt->gpustate.hostptr, LCC_SHADOW_SIZE + REG_SHADOW_SIZE + CMD_BUFFER_SIZE + TEX_SHADOW_SIZE , "kgsl_drawctxt_switch")); + + // restore gmem. (note: changes shader. shader must not already be restored.) + if (drawctxt->flags & CTXT_FLAGS_GMEM_RESTORE) + { + unsigned int i, numbuffers = 0; + + for( i = 0; i < GSL_MAX_GMEM_SHADOW_BUFFERS; i++ ) + { + if( drawctxt->user_gmem_shadow[i].gmemshadow.size > 0 ) + { + kgsl_ringbuffer_issuecmds(device, 1, drawctxt->user_gmem_shadow[i].gmem_restore, 3, drawctxt->pid); + + // Restore TP0_CHICKEN + kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid); + numbuffers++; + } + } + if( numbuffers == 0 ) + { + // No user defined buffers -> use context default + kgsl_ringbuffer_issuecmds(device, 1, drawctxt->context_gmem_shadow.gmem_restore, 3, drawctxt->pid); + // Restore TP0_CHICKEN + kgsl_ringbuffer_issuecmds(device, 0, drawctxt->chicken_restore, 3, drawctxt->pid); + } + + drawctxt->flags &= ~CTXT_FLAGS_GMEM_RESTORE; + } + + // restore registers and constants. + kgsl_ringbuffer_issuecmds(device, 0, drawctxt->reg_restore, 3, drawctxt->pid); + + // restore shader instructions & partitioning. + if (drawctxt->flags & CTXT_FLAGS_SHADER_RESTORE) + { + kgsl_ringbuffer_issuecmds(device, 0, drawctxt->shader_restore, 3, drawctxt->pid); + } + } +} + + +////////////////////////////////////////////////////////////////////////////// +// destroy all drawing contexts +////////////////////////////////////////////////////////////////////////////// +int +kgsl_drawctxt_destroyall(gsl_device_t *device) +{ + int i; + gsl_drawctxt_t *drawctxt; + + GSL_CONTEXT_MUTEX_LOCK(); + + for (i = 0; i < GSL_CONTEXT_MAX; i++) + { + drawctxt = &device->drawctxt[i]; + + if (drawctxt->flags != CTXT_FLAGS_NOT_IN_USE) + { + // destroy state shadow, if allocated + if (drawctxt->flags & CTXT_FLAGS_STATE_SHADOW) + kgsl_sharedmem_free0(&drawctxt->gpustate, GSL_CALLER_PROCESSID_GET()); + + // destroy gmem shadow, if allocated + if (drawctxt->context_gmem_shadow.gmemshadow.size > 0) + { + kgsl_sharedmem_free0(&drawctxt->context_gmem_shadow.gmemshadow, GSL_CALLER_PROCESSID_GET()); + drawctxt->context_gmem_shadow.gmemshadow.size = 0; + } + + drawctxt->flags = CTXT_FLAGS_NOT_IN_USE; + + device->drawctxt_count--; + KOS_ASSERT(device->drawctxt_count >= 0); + } + } + + GSL_CONTEXT_MUTEX_UNLOCK(); + + return (GSL_SUCCESS); +} + +#endif diff --git a/drivers/mxc/amd-gpu/common/gsl_driver.c b/drivers/mxc/amd-gpu/common/gsl_driver.c new file mode 100644 index 000000000000..b8c5170a1425 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_driver.c @@ -0,0 +1,329 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_PROCESSID_NONE 0x00000000 + +#define GSL_DRVFLAGS_EXTERNAL 0x10000000 +#define GSL_DRVFLAGS_INTERNAL 0x20000000 + + +////////////////////////////////////////////////////////////////////////////// +// globals +////////////////////////////////////////////////////////////////////////////// +#ifndef KGSL_USER_MODE +static gsl_flags_t gsl_driver_initialized = 0; +gsl_driver_t gsl_driver; +#else +extern gsl_flags_t gsl_driver_initialized; +extern gsl_driver_t gsl_driver; +#endif + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_driver_init0(gsl_flags_t flags, gsl_flags_t flags_debug) +{ + int status = GSL_SUCCESS; + + if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0)) + { +#ifdef GSL_LOG + // Uncomment these to enable logging. + //kgsl_log_init(); + //kgsl_log_open_stdout( KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP + // | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID ); + //kgsl_log_open_file( "c:\\kgsl_log.txt", KGSL_LOG_GROUP_ALL | KGSL_LOG_LEVEL_ALL | KGSL_LOG_TIMESTAMP + // | KGSL_LOG_THREAD_ID | KGSL_LOG_PROCESS_ID ); +#endif + kos_memset(&gsl_driver, 0, sizeof(gsl_driver_t)); + + GSL_API_MUTEX_CREATE(); + } + +#ifdef _DEBUG + // set debug flags on every entry, and prior to hal initialization + gsl_driver.flags_debug |= flags_debug; +#else + (void) flags_debug; // unref formal parameter +#endif // _DEBUG + + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + KGSL_DEBUG_DUMPX_OPEN("dumpx.tb", 0); + KGSL_DEBUG_DUMPX( BB_DUMP_ENABLE, 0, 0, 0, " "); + }); + + KGSL_DEBUG_TBDUMP_OPEN("tbdump.txt"); + + if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED0)) + { + GSL_API_MUTEX_LOCK(); + + // init hal + status = kgsl_hal_init(); + + if (status == GSL_SUCCESS) + { + gsl_driver_initialized |= flags; + gsl_driver_initialized |= GSL_FLAGS_INITIALIZED0; + } + + GSL_API_MUTEX_UNLOCK(); + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_driver_close0(gsl_flags_t flags) +{ + int status = GSL_SUCCESS; + + if ((gsl_driver_initialized & GSL_FLAGS_INITIALIZED0) && (gsl_driver_initialized & flags)) + { + GSL_API_MUTEX_LOCK(); + + // close hall + status = kgsl_hal_close(); + + GSL_API_MUTEX_UNLOCK(); + + GSL_API_MUTEX_FREE(); + +#ifdef GSL_LOG + kgsl_log_close(); +#endif + + gsl_driver_initialized &= ~flags; + gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED0; + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + KGSL_DEBUG_DUMPX_CLOSE(); + }); + + KGSL_DEBUG_TBDUMP_CLOSE(); + } + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_init() +{ + // only an external (platform specific device driver) component should call this + + return(kgsl_driver_init0(GSL_DRVFLAGS_EXTERNAL, 0)); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_close() +{ + // only an external (platform specific device driver) component should call this + + return(kgsl_driver_close0(GSL_DRVFLAGS_EXTERNAL)); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_entry(gsl_flags_t flags) +{ + int status = GSL_FAILURE; + int index, i; + unsigned int pid; + + if (kgsl_driver_init0(GSL_DRVFLAGS_INTERNAL, flags) != GSL_SUCCESS) + { + return (GSL_FAILURE); + } + + kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_entry( gsl_flags_t flags=%d )\n", flags ); + + GSL_API_MUTEX_LOCK(); + + pid = GSL_CALLER_PROCESSID_GET(); + + // if caller process has not already opened access + status = kgsl_driver_getcallerprocessindex(pid, &index); + if (status != GSL_SUCCESS) + { + // then, add caller pid to process table + status = kgsl_driver_getcallerprocessindex(GSL_PROCESSID_NONE, &index); + if (status == GSL_SUCCESS) + { + gsl_driver.callerprocess[index] = pid; + gsl_driver.refcnt++; + } + } + + if (status == GSL_SUCCESS) + { + if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED)) + { + // init memory apertures + status = kgsl_sharedmem_init(&gsl_driver.shmem); + if (status == GSL_SUCCESS) + { + // init devices + status = GSL_FAILURE; + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + if (kgsl_device_init(&gsl_driver.device[i], (gsl_deviceid_t)(i + 1)) == GSL_SUCCESS) { + status = GSL_SUCCESS; + } + } + } + + if (status == GSL_SUCCESS) + { + gsl_driver_initialized |= GSL_FLAGS_INITIALIZED; + } + } + + // walk through process attach callbacks + if (status == GSL_SUCCESS) + { + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + status = kgsl_device_attachcallback(&gsl_driver.device[i], pid); + if (status != GSL_SUCCESS) + { + break; + } + } + } + + // if something went wrong + if (status != GSL_SUCCESS) + { + // then, remove caller pid from process table + if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS) + { + gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE; + gsl_driver.refcnt--; + } + } + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_entry. Return value: %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_driver_exit0(unsigned int pid) +{ + int status = GSL_SUCCESS; + int index, i; + + GSL_API_MUTEX_LOCK(); + + if (gsl_driver_initialized & GSL_FLAGS_INITIALIZED) + { + if (kgsl_driver_getcallerprocessindex(pid, &index) == GSL_SUCCESS) + { + // walk through process detach callbacks + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + // Empty the freememqueue of this device + kgsl_cmdstream_memqueue_drain(&gsl_driver.device[i]); + + // Detach callback + status = kgsl_device_detachcallback(&gsl_driver.device[i], pid); + if (status != GSL_SUCCESS) + { + break; + } + } + + // last running caller process + if (gsl_driver.refcnt - 1 == 0) + { + // close devices + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + kgsl_device_close(&gsl_driver.device[i]); + } + + // shutdown memory apertures + kgsl_sharedmem_close(&gsl_driver.shmem); + + gsl_driver_initialized &= ~GSL_FLAGS_INITIALIZED; + } + + // remove caller pid from process table + gsl_driver.callerprocess[index] = GSL_PROCESSID_NONE; + gsl_driver.refcnt--; + } + } + + GSL_API_MUTEX_UNLOCK(); + + if (!(gsl_driver_initialized & GSL_FLAGS_INITIALIZED)) + { + kgsl_driver_close0(GSL_DRVFLAGS_INTERNAL); + } + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_exit(void) +{ + int status; + + kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_driver_exit()\n" ); + + status = kgsl_driver_exit0(GSL_CALLER_PROCESSID_GET()); + + kgsl_log_write( KGSL_LOG_GROUP_DRIVER | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_driver_exit(). Return value: %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_driver_destroy(unsigned int pid) +{ + return (kgsl_driver_exit0(pid)); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_g12.c b/drivers/mxc/amd-gpu/common/gsl_g12.c new file mode 100644 index 000000000000..8286e8e6a6ac --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_g12.c @@ -0,0 +1,1025 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#include "kos_libapi.h" +#include "gsl_cmdstream.h" +#ifdef _LINUX +#include +#endif + +#ifdef CONFIG_ARCH_MX35 +#define V3_SYNC +#endif + +#ifdef GSL_BLD_G12 +#define GSL_IRQ_TIMEOUT 200 + + +//---------------------------------------------------------------------------- + +#define GSL_HAL_NUMCMDBUFFERS 5 +#define GSL_HAL_CMDBUFFERSIZE (1024 + 13) * sizeof(unsigned int) + +#define ALIGN_IN_BYTES( dim, alignment ) ( ( (dim) + (alignment-1) ) & ~(alignment-1) ) + + +#ifdef _Z180 +#define NUMTEXUNITS 4 +#define TEXUNITREGCOUNT 25 +#define VG_REGCOUNT 0x39 +#define GSL_HAL_EDGE0BUFSIZE 0x3E8+64 +#define GSL_HAL_EDGE1BUFSIZE 0x8000+64 +#define GSL_HAL_EDGE2BUFSIZE 0x80020+64 +#define GSL_HAL_EDGE0REG ADDR_VGV1_CBUF +#define GSL_HAL_EDGE1REG ADDR_VGV1_BBUF +#define GSL_HAL_EDGE2REG ADDR_VGV1_EBUF +#else +#define NUMTEXUNITS 2 +#define TEXUNITREGCOUNT 24 +#define VG_REGCOUNT 0x3A +#define L1TILESIZE 64 +#define GSL_HAL_EDGE0BUFSIZE L1TILESIZE*L1TILESIZE*4+64 +#define GSL_HAL_EDGE1BUFSIZE L1TILESIZE*L1TILESIZE*16+64 +#define GSL_HAL_EDGE0REG ADDR_VGV1_CBASE1 +#define GSL_HAL_EDGE1REG ADDR_VGV1_UBASE2 +#endif + +#define PACKETSIZE_BEGIN 3 +#define PACKETSIZE_G2DCOLOR 2 +#define PACKETSIZE_TEXUNIT (TEXUNITREGCOUNT*2) +#define PACKETSIZE_REG (VG_REGCOUNT*2) +#define PACKETSIZE_STATE (PACKETSIZE_TEXUNIT*NUMTEXUNITS + PACKETSIZE_REG + PACKETSIZE_BEGIN + PACKETSIZE_G2DCOLOR) +#define PACKETSIZE_STATESTREAM ALIGN_IN_BYTES((PACKETSIZE_STATE*sizeof(unsigned int)), 32) / sizeof(unsigned int) + +//---------------------------------------------------------------------------- + +typedef struct +{ + unsigned int id; + // unsigned int regs[]; +}gsl_hal_z1xxdrawctx_t; + +typedef struct +{ + unsigned int offs; + unsigned int curr; + unsigned int prevctx; + + gsl_memdesc_t e0; + gsl_memdesc_t e1; + gsl_memdesc_t e2; + unsigned int* cmdbuf[GSL_HAL_NUMCMDBUFFERS]; + gsl_memdesc_t cmdbufdesc[GSL_HAL_NUMCMDBUFFERS]; + gsl_timestamp_t timestamp[GSL_HAL_NUMCMDBUFFERS]; + + unsigned int numcontext; + unsigned int nextUniqueContextID; +}gsl_z1xx_t; + +static gsl_z1xx_t g_z1xx = {0}; + +extern int z160_version; + +//---------------------------------------------------------------------------- + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +static int kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp); +static int kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags); +static int kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags); +static int kgsl_g12_context_destroy(gsl_device_t* device, unsigned int drawctxt_id); +static unsigned int drawctx_id = 0; +static int kgsl_g12_idle(gsl_device_t *device, unsigned int timeout); +#ifndef _LINUX +static void irq_thread(void); +#endif + +//---------------------------------------------------------------------------- + +void +kgsl_g12_intrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_device_t *device = (gsl_device_t *) cookie; + + switch(id) + { + // non-error condition interrupt + case GSL_INTR_G12_G2D: +#ifdef _LINUX + queue_work(device->irq_workq, &(device->irq_work)); + break; +#endif +#ifndef _Z180 + case GSL_INTR_G12_FBC: +#endif //_Z180 + // signal intr completion event + kos_event_signal(device->intr.evnt[id]); + break; + + // error condition interrupt + case GSL_INTR_G12_FIFO: + printk(KERN_ERR "GPU: Z160 FIFO Error\n"); + schedule_work(&device->irq_err_work); + break; + + case GSL_INTR_G12_MH: + // don't do anything. this is handled by the MMU manager + break; + + default: + break; + } +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_isr(gsl_device_t *device) +{ + unsigned int status; +#ifdef _DEBUG + REG_MH_MMU_PAGE_FAULT page_fault = {0}; + REG_MH_AXI_ERROR axi_error = {0}; +#endif // DEBUG + + // determine if G12 is interrupting + device->ftbl.device_regread(device, (ADDR_VGC_IRQSTATUS >> 2), &status); + + if (status) + { + // if G12 MH is interrupting, clear MH block interrupt first, then master G12 MH interrupt + if (status & (1 << VGC_IRQSTATUS_MH_FSHIFT)) + { +#ifdef _DEBUG + // obtain mh error information + device->ftbl.device_regread(device, ADDR_MH_MMU_PAGE_FAULT, (unsigned int *)&page_fault); + device->ftbl.device_regread(device, ADDR_MH_AXI_ERROR, (unsigned int *)&axi_error); +#endif // DEBUG + + kgsl_intr_decode(device, GSL_INTR_BLOCK_G12_MH); + } + + kgsl_intr_decode(device, GSL_INTR_BLOCK_G12); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid) +{ +#ifndef GSL_NO_MMU + REG_MH_MMU_INVALIDATE mh_mmu_invalidate = {0}; + + // unreferenced formal parameter + (void) pid; + + mh_mmu_invalidate.INVALIDATE_ALL = 1; + mh_mmu_invalidate.INVALIDATE_TC = 1; + + device->ftbl.device_regwrite(device, reg_invalidate, *(unsigned int *) &mh_mmu_invalidate); +#else + (void)device; + (void)reg_invalidate; +#endif + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid) +{ + // unreferenced formal parameter + (void) pid; +#ifndef GSL_NO_MMU + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + device->ftbl.device_regwrite(device, reg_ptbase, ptbase); +#else + (void)device; + (void)reg_ptbase; + (void)reg_varange; +#endif + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +#ifdef _LINUX +static void kgsl_g12_updatetimestamp(gsl_device_t *device) +{ + unsigned int count = 0; + device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &count); + count >>= 8; + count &= 255; + device->timestamp += count; +#ifdef V3_SYNC + if (device->current_timestamp > device->timestamp) + { + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 2); + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0); + } +#endif + kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), &device->timestamp, 4, 0); +} + +//---------------------------------------------------------------------------- + +static void kgsl_g12_irqtask(struct work_struct *work) +{ + gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_G12-1]; + kgsl_g12_updatetimestamp(device); + wake_up_interruptible_all(&device->timestamp_waitq); +} + +static void kgsl_g12_irqerr(struct work_struct *work) +{ + gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_G12-1]; + device->ftbl.device_destroy(device); +} +#endif + +//---------------------------------------------------------------------------- + +int +kgsl_g12_init(gsl_device_t *device) +{ + int status = GSL_FAILURE; + + device->flags |= GSL_FLAGS_INITIALIZED; + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100); + + // setup MH arbiter - MH offsets are considered to be dword based, therefore no down shift + device->ftbl.device_regwrite(device, ADDR_MH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_g12_mharb); + + // init interrupt + status = kgsl_intr_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + // enable irq + device->ftbl.device_regwrite(device, (ADDR_VGC_IRQENABLE >> 2), 0x3); + +#ifndef GSL_NO_MMU + // enable master interrupt for G12 MH + kgsl_intr_attach(&device->intr, GSL_INTR_G12_MH, kgsl_g12_intrcallback, (void *) device); + kgsl_intr_enable(&device->intr, GSL_INTR_G12_MH); + + // init mmu + status = kgsl_mmu_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } +#endif + +#ifdef IRQTHREAD_POLL + // Create event to trigger IRQ polling thread + device->irqthread_event = kos_event_create(0); +#endif + + // enable interrupts + kgsl_intr_attach(&device->intr, GSL_INTR_G12_G2D, kgsl_g12_intrcallback, (void *) device); + kgsl_intr_attach(&device->intr, GSL_INTR_G12_FIFO, kgsl_g12_intrcallback, (void *) device); + kgsl_intr_enable(&device->intr, GSL_INTR_G12_G2D); + kgsl_intr_enable(&device->intr, GSL_INTR_G12_FIFO); + +#ifndef _Z180 + kgsl_intr_attach(&device->intr, GSL_INTR_G12_FBC, kgsl_g12_intrcallback, (void *) device); + //kgsl_intr_enable(&device->intr, GSL_INTR_G12_FBC); +#endif //_Z180 + + // create thread for IRQ handling +#if defined(__SYMBIAN32__) + kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) ); +#elif defined(_LINUX) + device->irq_workq = create_singlethread_workqueue("z1xx_workq"); + INIT_WORK(&device->irq_work, kgsl_g12_irqtask); + INIT_WORK(&device->irq_err_work, kgsl_g12_irqerr); +#else + #pragma warning(disable:4152) + device->irq_thread_handle = kos_thread_create( (oshandle_t)irq_thread, &(device->irq_thread) ); +#endif + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_close(gsl_device_t *device) +{ + int status = GSL_FAILURE; + + if (device->refcnt == 0) + { + // wait pending interrupts before shutting down G12 intr thread to + // empty irq counters. Otherwise there's a possibility to have them in + // registers next time systems starts up and this results in a hang. + status = device->ftbl.device_idle(device, 1000); + KOS_ASSERT(status == GSL_SUCCESS); + +#ifndef _LINUX + kos_thread_destroy(device->irq_thread_handle); +#else + destroy_workqueue(device->irq_workq); +#endif + + // shutdown command window + kgsl_cmdwindow_close(device); + +#ifndef GSL_NO_MMU + // shutdown mmu + kgsl_mmu_close(device); +#endif + // disable interrupts + kgsl_intr_detach(&device->intr, GSL_INTR_G12_MH); + kgsl_intr_detach(&device->intr, GSL_INTR_G12_G2D); + kgsl_intr_detach(&device->intr, GSL_INTR_G12_FIFO); +#ifndef _Z180 + kgsl_intr_detach(&device->intr, GSL_INTR_G12_FBC); +#endif //_Z180 + + // shutdown interrupt + kgsl_intr_close(device); + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0); + + device->flags &= ~GSL_FLAGS_INITIALIZED; + +#if defined(__SYMBIAN32__) + while(device->irq_thread) + { + kos_sleep(20); + } +#endif + drawctx_id = 0; + + KOS_ASSERT(g_z1xx.numcontext == 0); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_destroy(gsl_device_t *device) +{ + int i; + unsigned int pid; + +#ifdef _DEBUG + // for now, signal catastrophic failure in a brute force way + KOS_ASSERT(0); +#endif // _DEBUG + + //todo: hard reset core? + + for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++) + { + pid = device->callerprocess[i]; + if (pid) + { + device->ftbl.device_stop(device); + kgsl_driver_destroy(pid); + + // todo: terminate client process? + } + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_start(gsl_device_t *device, gsl_flags_t flags) +{ + int status = GSL_SUCCESS; + + (void) flags; // unreferenced formal parameter + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100); + + // init command window + status = kgsl_cmdwindow_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + KOS_ASSERT(g_z1xx.numcontext == 0); + + device->flags |= GSL_FLAGS_STARTED; + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_stop(gsl_device_t *device) +{ + int status; + + KOS_ASSERT(device->refcnt == 0); + + /* wait for device to idle before setting it's clock off */ + status = device->ftbl.device_idle(device, 1000); + KOS_ASSERT(status == GSL_SUCCESS); + + status = kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0); + device->flags &= ~GSL_FLAGS_STARTED; + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_FAILURE; + // unreferenced formal parameter + (void) sizebytes; + + if (type == GSL_PROP_DEVICE_INFO) + { + gsl_devinfo_t *devinfo = (gsl_devinfo_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t)); + + devinfo->device_id = device->id; + devinfo->chip_id = (gsl_chipid_t)device->chip_id; +#ifndef GSL_NO_MMU + devinfo->mmu_enabled = kgsl_mmu_isenabled(&device->mmu); +#endif + if (z160_version == 1) + devinfo->high_precision = 1; + else + devinfo->high_precision = 0; + + status = GSL_SUCCESS; + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_FAILURE; + + // unreferenced formal parameters + (void) device; + + if (type == GSL_PROP_DEVICE_POWER) + { + gsl_powerprop_t *power = (gsl_powerprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t)); + + if (!(device->flags & GSL_FLAGS_SAFEMODE)) + { + kgsl_hal_setpowerstate(device->id, power->flags, power->value); + } + + status = GSL_SUCCESS; + } + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_idle(gsl_device_t *device, unsigned int timeout) +{ + if ( device->flags & GSL_FLAGS_STARTED ) + { + for ( ; ; ) + { + gsl_timestamp_t retired = kgsl_cmdstream_readtimestamp0( device->id, GSL_TIMESTAMP_RETIRED ); + gsl_timestamp_t ts_diff = retired - device->current_timestamp; + if ( ts_diff >= 0 || ts_diff < -GSL_TIMESTAMP_EPSILON ) + break; + kos_sleep(10); + } + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value) +{ + // G12 MH register values can only be retrieved via dedicated read registers + if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) || + (offsetwords >= ADDR_MH_MMU_CONFIG && offsetwords <= ADDR_MH_MMU_MPU_END)) + { +#ifdef _Z180 + device->ftbl.device_regwrite(device, (ADDR_VGC_MH_READ_ADDR >> 2), offsetwords); + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_VGC_MH_READ_ADDR >> 2), value); +#else + device->ftbl.device_regwrite(device, (ADDR_MMU_READ_ADDR >> 2), offsetwords); + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, (ADDR_MMU_READ_DATA >> 2), value); +#endif + } + else + { + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value) +{ + // G12 MH registers can only be written via the command window + if ((offsetwords >= ADDR_MH_ARBITER_CONFIG && offsetwords <= ADDR_MH_AXI_HALT_CONTROL) || + (offsetwords >= ADDR_MH_MMU_CONFIG && offsetwords <= ADDR_MH_MMU_MPU_END)) + { + kgsl_cmdwindow_write0(device->id, GSL_CMDWINDOW_MMU, offsetwords, value); + } + else + { + GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value); + } + + // idle device when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout) +{ + int status = GSL_FAILURE_NOTSUPPORTED; +#ifdef VG_HDK + (void)timeout; +#endif + +#ifndef _Z180 + if (intr_id == GSL_INTR_G12_G2D || intr_id == GSL_INTR_G12_FBC) +#else + if (intr_id == GSL_INTR_G12_G2D) +#endif //_Z180 + { +#ifndef VG_HDK + if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS) +#endif + { + // wait until intr completion event is received and check that + // the interrupt is still enabled. If event is received, but + // interrupt is not enabled any more, the driver is shutting + // down and event structure is not valid anymore. +#ifndef VG_HDK + if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS && kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS) +#endif + { + unsigned int cntrs; + int i; + kgsl_device_active(device); +#ifndef VG_HDK + kos_event_reset(device->intr.evnt[intr_id]); + device->ftbl.device_regread(device, (ADDR_VGC_IRQ_ACTIVE_CNT >> 2), &cntrs); +#else + device->ftbl.device_regread(device, (0x38 >> 2), &cntrs); +#endif + + for (i = 0; i < GSL_G12_INTR_COUNT; i++) + { + int intrcnt = cntrs >> ((8 * i)) & 255; + + // maximum allowed counter value is 254. if set to 255 then something has gone wrong + if (intrcnt && (intrcnt < 0xFF)) + { + device->intrcnt[i] += intrcnt; + } + } + + *count = device->intrcnt[intr_id - GSL_INTR_G12_MH]; + device->intrcnt[intr_id - GSL_INTR_G12_MH] = 0; + status = GSL_SUCCESS; + } +#ifndef VG_HDK + else + { + status = GSL_FAILURE_TIMEOUT; + } +#endif + } + } + else if(intr_id == GSL_INTR_FOOBAR) + { + if (kgsl_intr_isenabled(&device->intr, GSL_INTR_G12_G2D) == GSL_SUCCESS) + { + kos_event_signal(device->intr.evnt[GSL_INTR_G12_G2D]); + } + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_g12_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout) +{ +#ifndef _LINUX + return kos_event_wait( device->timestamp_event, timeout ); +#else + int status = wait_event_interruptible_timeout(device->timestamp_waitq, + kgsl_cmdstream_check_timestamp(device->id, timestamp), + msecs_to_jiffies(timeout)); + if (status > 0) + return GSL_SUCCESS; + else + return GSL_FAILURE; +#endif +} + +int +kgsl_g12_getfunctable(gsl_functable_t *ftbl) +{ + ftbl->device_init = kgsl_g12_init; + ftbl->device_close = kgsl_g12_close; + ftbl->device_destroy = kgsl_g12_destroy; + ftbl->device_start = kgsl_g12_start; + ftbl->device_stop = kgsl_g12_stop; + ftbl->device_getproperty = kgsl_g12_getproperty; + ftbl->device_setproperty = kgsl_g12_setproperty; + ftbl->device_idle = kgsl_g12_idle; + ftbl->device_regread = kgsl_g12_regread; + ftbl->device_regwrite = kgsl_g12_regwrite; + ftbl->device_waitirq = kgsl_g12_waitirq; + ftbl->device_waittimestamp = kgsl_g12_waittimestamp; + ftbl->device_runpending = NULL; + ftbl->device_addtimestamp = kgsl_g12_addtimestamp; + ftbl->intr_isr = kgsl_g12_isr; + ftbl->mmu_tlbinvalidate = kgsl_g12_tlbinvalidate; + ftbl->mmu_setpagetable = kgsl_g12_setpagetable; + ftbl->cmdstream_issueibcmds = kgsl_g12_issueibcmds; + ftbl->context_create = kgsl_g12_context_create; + ftbl->context_destroy = kgsl_g12_context_destroy; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static void addmarker(gsl_z1xx_t* z1xx) +{ + KOS_ASSERT(z1xx); + { + unsigned int *p = z1xx->cmdbuf[z1xx->curr]; + /* todo: use symbolic values */ + p[z1xx->offs++] = 0x7C000176; + p[z1xx->offs++] = (0x8000|5); + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = 0x7C000176; + p[z1xx->offs++] = 5; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + } +} + +//---------------------------------------------------------------------------- +static void beginpacket(gsl_z1xx_t* z1xx, gpuaddr_t cmd, unsigned int nextcnt) +{ + unsigned int *p = z1xx->cmdbuf[z1xx->curr]; + + p[z1xx->offs++] = 0x7C000176; + p[z1xx->offs++] = 5; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = 0x7C000275; + p[z1xx->offs++] = cmd; + p[z1xx->offs++] = 0x1000|nextcnt; // nextcount + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; + p[z1xx->offs++] = ADDR_VGV3_LAST<<24; +} + +//---------------------------------------------------------------------------- + +static int +kgsl_g12_issueibcmds(gsl_device_t* device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, unsigned int flags) +{ + unsigned int ofs = PACKETSIZE_STATESTREAM*sizeof(unsigned int); + unsigned int cnt = 5; + unsigned int cmd = ibaddr; + unsigned int nextbuf = (g_z1xx.curr+1)%GSL_HAL_NUMCMDBUFFERS; + unsigned int nextaddr = g_z1xx.cmdbufdesc[nextbuf].gpuaddr; + unsigned int nextcnt = 0x9000|5; + gsl_memdesc_t tmp = {0}; + gsl_timestamp_t processed_timestamp; + + (void) flags; + + // read what is the latest timestamp device have processed + GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp); + + /* wait for the next buffer's timestamp to occur */ + while(processed_timestamp < g_z1xx.timestamp[nextbuf]) + { +#ifndef _LINUX + kos_event_wait(device->timestamp_event, 1000); + kos_event_reset(device->timestamp_event); +#else + kgsl_cmdstream_waittimestamp(device->id, g_z1xx.timestamp[nextbuf], 1000); +#endif + GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)&processed_timestamp); + } + + *timestamp = g_z1xx.timestamp[nextbuf] = device->current_timestamp + 1; + + /* context switch */ + if (drawctxt_index != (int)g_z1xx.prevctx) + { + cnt = PACKETSIZE_STATESTREAM; + ofs = 0; + } + g_z1xx.prevctx = drawctxt_index; + + g_z1xx.offs = 10; + beginpacket(&g_z1xx, cmd+ofs, cnt); + + tmp.gpuaddr=ibaddr+(sizedwords*sizeof(unsigned int)); + kgsl_sharedmem_write0(&tmp, 4, &nextaddr, 4, false); + kgsl_sharedmem_write0(&tmp, 8, &nextcnt, 4, false); + + /* sync mem */ + kgsl_sharedmem_write0((const gsl_memdesc_t *)&g_z1xx.cmdbufdesc[g_z1xx.curr], 0, g_z1xx.cmdbuf[g_z1xx.curr], (512 + 13) * sizeof(unsigned int), false); + + g_z1xx.offs = 0; + g_z1xx.curr = nextbuf; + + /* increment mark counter */ +#ifdef V3_SYNC + if (device->timestamp == device->current_timestamp) + { + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, flags); + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0); + } +#else + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, flags); + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0); +#endif + + /* increment consumed timestamp */ + device->current_timestamp++; + kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp), &device->current_timestamp, 4, 0); + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static int +kgsl_g12_context_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags) +{ + int status = 0; + int i; + int cmd; + gsl_flags_t gslflags = (GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_ALIGNPAGE); + + // unreferenced formal parameters + (void) device; + (void) type; + //(void) drawctxt_id; + (void) flags; + + kgsl_device_active(device); + + if (g_z1xx.numcontext==0) + { + g_z1xx.nextUniqueContextID = 0; + /* todo: move this to device create or start. Error checking!! */ + for (i=0;iirqthread_event, GSL_IRQ_TIMEOUT)==GSL_SUCCESS) + { + kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT); +#else + + if( kgsl_g12_waitirq(device, GSL_INTR_G12_G2D, &irq_count, GSL_IRQ_TIMEOUT) == GSL_SUCCESS ) + { +#endif + /* Read a timestamp value */ +#ifdef VG_HDK + timestamp = device->timestamp; +#else + GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, (int *)×tamp); +#endif + /* Increase the timestamp value */ + timestamp += irq_count; + + /* Write the new timestamp value */ + device->timestamp = timestamp; + kgsl_sharedmem_write0(&device->memstore, GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), ×tamp, 4, false); + +#ifdef V3_SYNC + if (device->current_timestamp > device->timestamp) + { + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 2); + kgsl_cmdwindow_write0(2, GSL_CMDWINDOW_2D, ADDR_VGV3_CONTROL, 0); + } +#endif + + /* Notify timestamp event */ +#ifndef _LINUX + kos_event_signal( device->timestamp_event ); +#else + wake_up_interruptible_all(&(device->timestamp_waitq)); +#endif + } + else + { + /* Timeout */ + + + if(!(device->flags&GSL_FLAGS_INITIALIZED)) + { + /* if device is closed -> thread exit */ +#if defined(__SYMBIAN32__) + device->irq_thread = 0; +#endif + return; + } + } + } +} +#endif + +//---------------------------------------------------------------------------- + +static int +kgsl_g12_addtimestamp(gsl_device_t* device, gsl_timestamp_t *timestamp) +{ + device->current_timestamp++; + *timestamp = device->current_timestamp; + + return (GSL_SUCCESS); +} +#endif diff --git a/drivers/mxc/amd-gpu/common/gsl_intrmgr.c b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c new file mode 100644 index 000000000000..2c8b278dfe7a --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_intrmgr.c @@ -0,0 +1,305 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_INTRID_VALIDATE(id) (((id) < 0) || ((id) >= GSL_INTR_COUNT)) + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +static const gsl_intrblock_reg_t * +kgsl_intr_id2block(gsl_intrid_t id) +{ + const gsl_intrblock_reg_t *block; + int i; + + // interrupt id to hw block + for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) + { + block = &gsl_cfg_intrblock_reg[i]; + + if (block->first_id <= id && id <= block->last_id) + { + return (block); + } + } + + return (NULL); +} + +//---------------------------------------------------------------------------- + +void +kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id) +{ + const gsl_intrblock_reg_t *block = &gsl_cfg_intrblock_reg[block_id]; + gsl_intrid_t id; + unsigned int status; + + // read the block's interrupt status bits + device->ftbl.device_regread(device, block->status_reg, &status); + + // mask off any interrupts which are disabled + status &= device->intr.enabled[block->id]; + + // acknowledge the block's interrupts + device->ftbl.device_regwrite(device, block->clear_reg, status); + + // loop through the block's masks, determine which interrupt bits are active, and call callback (or TODO queue DPC) + for (id = block->first_id; id <= block->last_id; id++) + { + if (status & gsl_cfg_intr_mask[id]) + { + device->intr.handler[id].callback(id, device->intr.handler[id].cookie); + } + } +} + +//---------------------------------------------------------------------------- + +KGSL_API void +kgsl_intr_isr() +{ + gsl_deviceid_t device_id; + gsl_device_t *device; + + // loop through the devices, and call device specific isr + for (device_id = (gsl_deviceid_t)(GSL_DEVICE_ANY + 1); device_id <= GSL_DEVICE_MAX; device_id++) + { + device = &gsl_driver.device[device_id-1]; // device_id is 1 based + + if (device->intr.flags & GSL_FLAGS_INITIALIZED) + { + kgsl_device_active(device); + device->ftbl.intr_isr(device); + } + } +} + +//---------------------------------------------------------------------------- + +int kgsl_intr_init(gsl_device_t *device) +{ + if (device->ftbl.intr_isr == NULL) + { + return (GSL_FAILURE_BADPARAM); + } + + if (device->intr.flags & GSL_FLAGS_INITIALIZED) + { + return (GSL_SUCCESS); + } + + device->intr.device = device; + device->intr.flags |= GSL_FLAGS_INITIALIZED; + + // os_interrupt_setcallback(YAMATO_INTR, kgsl_intr_isr); + // os_interrupt_enable(YAMATO_INTR); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int kgsl_intr_close(gsl_device_t *device) +{ + const gsl_intrblock_reg_t *block; + int i, id; + + if (device->intr.flags & GSL_FLAGS_INITIALIZED) + { + // check if there are any enabled interrupts lingering around + for (i = 0; i < GSL_INTR_BLOCK_COUNT; i++) + { + if (device->intr.enabled[i]) + { + block = &gsl_cfg_intrblock_reg[i]; + + // loop through the block's masks, disable interrupts which active + for (id = block->first_id; id <= block->last_id; id++) + { + if (device->intr.enabled[i] & gsl_cfg_intr_mask[id]) + { + kgsl_intr_disable(&device->intr, (gsl_intrid_t)id); + } + } + } + } + + kos_memset(&device->intr, 0, sizeof(gsl_intr_t)); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id) +{ + const gsl_intrblock_reg_t *block; + unsigned int mask; + unsigned int enabled; + + if (GSL_INTRID_VALIDATE(id)) + { + return (GSL_FAILURE_BADPARAM); + } + + if (intr->handler[id].callback == NULL) + { + return (GSL_FAILURE_NOTINITIALIZED); + } + + block = kgsl_intr_id2block(id); + if (block == NULL) + { + return (GSL_FAILURE_SYSTEMERROR); + } + + mask = gsl_cfg_intr_mask[id]; + enabled = intr->enabled[block->id]; + + if (mask && !(enabled & mask)) + { + intr->evnt[id] = kos_event_create(0); + + enabled |= mask; + intr->enabled[block->id] = enabled; + intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id) +{ + const gsl_intrblock_reg_t *block; + unsigned int mask; + unsigned int enabled; + + if (GSL_INTRID_VALIDATE(id)) + { + return (GSL_FAILURE_BADPARAM); + } + + if (intr->handler[id].callback == NULL) + { + return (GSL_FAILURE_NOTINITIALIZED); + } + + block = kgsl_intr_id2block(id); + if (block == NULL) + { + return (GSL_FAILURE_SYSTEMERROR); + } + + mask = gsl_cfg_intr_mask[id]; + enabled = intr->enabled[block->id]; + + if (enabled & mask) + { + enabled &= ~mask; + intr->enabled[block->id] = enabled; + intr->device->ftbl.device_regwrite(intr->device, block->mask_reg, enabled); + + kos_event_signal(intr->evnt[id]); // wake up waiting threads before destroying the event + kos_event_destroy(intr->evnt[id]); + intr->evnt[id] = 0; + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie) +{ + if (GSL_INTRID_VALIDATE(id) || callback == NULL) + { + return (GSL_FAILURE_BADPARAM); + } + + if (intr->handler[id].callback != NULL) + { + if (intr->handler[id].callback == callback && intr->handler[id].cookie == cookie) + { + return (GSL_FAILURE_ALREADYINITIALIZED); + } + else + { + return (GSL_FAILURE_NOMOREAVAILABLE); + } + } + + intr->handler[id].callback = callback; + intr->handler[id].cookie = cookie; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id) +{ + if (GSL_INTRID_VALIDATE(id)) + { + return (GSL_FAILURE_BADPARAM); + } + + if (intr->handler[id].callback == NULL) + { + return (GSL_FAILURE_NOTINITIALIZED); + } + + kgsl_intr_disable(intr, id); + + intr->handler[id].callback = NULL; + intr->handler[id].cookie = NULL; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id) +{ + int status = GSL_FAILURE; + const gsl_intrblock_reg_t *block = kgsl_intr_id2block(id); + + if (block != NULL) + { + // check if interrupt is enabled + if (intr->enabled[block->id] & gsl_cfg_intr_mask[id]) + { + status = GSL_SUCCESS; + } + } + + return (status); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_log.c b/drivers/mxc/amd-gpu/common/gsl_log.c new file mode 100644 index 000000000000..79a14a5f4b21 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_log.c @@ -0,0 +1,591 @@ +/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifdef GSL_LOG + +#define _CRT_SECURE_NO_WARNINGS + +#include +#include +#include +#include "gsl.h" + +#define KGSL_OUTPUT_TYPE_MEMBUF 0 +#define KGSL_OUTPUT_TYPE_STDOUT 1 +#define KGSL_OUTPUT_TYPE_FILE 2 + +#define REG_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break; +#define INTRID_OUTPUT( X ) case X: b += sprintf( b, "%s", #X ); break; + +typedef struct log_output +{ + unsigned char type; + unsigned int flags; + oshandle_t file; + + struct log_output* next; +} log_output_t; + +static log_output_t* outputs = NULL; + +static oshandle_t log_mutex = NULL; +static char buffer[256]; +static char buffer2[256]; +static int log_initialized = 0; + +//---------------------------------------------------------------------------- + +int kgsl_log_init() +{ + log_mutex = kos_mutex_create( "log_mutex" ); + + log_initialized = 1; + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_close() +{ + if( !log_initialized ) return GSL_SUCCESS; + + // Go throught output list and free every node + while( outputs != NULL ) + { + log_output_t* temp = outputs->next; + + switch( outputs->type ) + { + case KGSL_OUTPUT_TYPE_FILE: + kos_fclose( outputs->file ); + break; + } + + kos_free( outputs ); + outputs = temp; + } + + kos_mutex_free( log_mutex ); + + log_initialized = 0; + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_open_stdout( unsigned int log_flags ) +{ + log_output_t* output; + + if( !log_initialized ) return GSL_SUCCESS; + + output = kos_malloc( sizeof( log_output_t ) ); + output->type = KGSL_OUTPUT_TYPE_STDOUT; + output->flags = log_flags; + + // Add to the list + if( outputs == NULL ) + { + // First node in the list. + outputs = output; + output->next = NULL; + } + else + { + // Add to the start of the list + output->next = outputs; + outputs = output; + } + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ) +{ + // TODO + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_open_file( char* filename, unsigned int log_flags ) +{ + log_output_t* output; + + if( !log_initialized ) return GSL_SUCCESS; + + output = kos_malloc( sizeof( log_output_t ) ); + output->type = KGSL_OUTPUT_TYPE_FILE; + output->flags = log_flags; + output->file = kos_fopen( filename, "w" ); + + // Add to the list + if( outputs == NULL ) + { + // First node in the list. + outputs = output; + output->next = NULL; + } + else + { + // Add to the start of the list + output->next = outputs; + outputs = output; + } + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- + +int kgsl_log_flush_membuf( char* filename, int memBufId ) +{ + // TODO + + return GSL_SUCCESS; +} +//---------------------------------------------------------------------------- + +int kgsl_log_write( unsigned int log_flags, char* format, ... ) +{ + char *c = format; + char *b = buffer; + char *p1, *p2; + log_output_t* output; + va_list arguments; + + if( !log_initialized ) return GSL_SUCCESS; + + // Acquire mutex lock as we are using shared buffer for the string parsing + kos_mutex_lock( log_mutex ); + + // Add separator + *(b++) = '|'; *(b++) = ' '; + + va_start( arguments, format ); + + while( 1 ) + { + // Find the first occurence of % + p1 = strchr( c, '%' ); + if( !p1 ) + { + // No more % characters -> copy rest of the string + strcpy( b, c ); + + break; + } + + // Find the second occurence of % and handle the string until that point + p2 = strchr( p1+1, '%' ); + + // If not found, just use the end of the buffer + if( !p2 ) p2 = strchr( p1+1, '\0' ); + + // Break the string to this point + kos_memcpy( buffer2, c, p2-c ); + *(buffer2+(unsigned int)(p2-c)) = '\0'; + + switch( *(p1+1) ) + { + // gsl_memdesc_t + case 'M': + { + gsl_memdesc_t val = va_arg( arguments, gsl_memdesc_t ); + // Handle string before %M + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %M + b += sprintf( b, "[hostptr=0x%08x, gpuaddr=0x%08x]", val.hostptr, val.gpuaddr ); + // Handle string after %M + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + // GSL_SUCCESS/GSL_FAILURE + case 'B': + { + int val = va_arg( arguments, int ); + // Handle string before %B + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %B + if( val == GSL_SUCCESS ) + b += sprintf( b, "%s", "GSL_SUCCESS" ); + else + b += sprintf( b, "%s", "GSL_FAILURE" ); + // Handle string after %B + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + // gsl_deviceid_t + case 'D': + { + gsl_deviceid_t val = va_arg( arguments, gsl_deviceid_t ); + // Handle string before %D + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %D + switch( val ) + { + case GSL_DEVICE_ANY: + b += sprintf( b, "%s", "GSL_DEVICE_ANY" ); + break; + case GSL_DEVICE_YAMATO: + b += sprintf( b, "%s", "GSL_DEVICE_YAMATO" ); + break; + case GSL_DEVICE_G12: + b += sprintf( b, "%s", "GSL_DEVICE_G12" ); + break; + default: + b += sprintf( b, "%s", "UNKNOWN DEVICE" ); + break; + } + // Handle string after %D + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + // gsl_intrid_t + case 'I': + { + unsigned int val = va_arg( arguments, unsigned int ); + // Handle string before %I + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %I + switch( val ) + { + INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_READ_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_MH_AXI_WRITE_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_MH_MMU_PAGE_FAULT ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_SW_INT ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_T0_PACKET_IN_IB ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_OPCODE_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_RESERVED_BIT_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_IB_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_IB2_INT ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_IB1_INT ); + INTRID_OUTPUT( GSL_INTR_YDX_CP_RING_BUFFER ); + INTRID_OUTPUT( GSL_INTR_YDX_RBBM_READ_ERROR ); + INTRID_OUTPUT( GSL_INTR_YDX_RBBM_DISPLAY_UPDATE ); + INTRID_OUTPUT( GSL_INTR_YDX_RBBM_GUI_IDLE ); + INTRID_OUTPUT( GSL_INTR_YDX_SQ_PS_WATCHDOG ); + INTRID_OUTPUT( GSL_INTR_YDX_SQ_VS_WATCHDOG ); + INTRID_OUTPUT( GSL_INTR_G12_MH ); + INTRID_OUTPUT( GSL_INTR_G12_G2D ); + INTRID_OUTPUT( GSL_INTR_G12_FIFO ); +#ifndef _Z180 + INTRID_OUTPUT( GSL_INTR_G12_FBC ); +#endif // _Z180 + INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_READ_ERROR ); + INTRID_OUTPUT( GSL_INTR_G12_MH_AXI_WRITE_ERROR ); + INTRID_OUTPUT( GSL_INTR_G12_MH_MMU_PAGE_FAULT ); + INTRID_OUTPUT( GSL_INTR_COUNT ); + INTRID_OUTPUT( GSL_INTR_FOOBAR ); + + default: + b += sprintf( b, "%s", "UNKNOWN INTERRUPT ID" ); + break; + } + // Handle string after %I + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + // Register offset + case 'R': + { + unsigned int val = va_arg( arguments, unsigned int ); + + // Handle string before %R + kos_memcpy( b, c, p1-c ); + b += (unsigned int)p1-(unsigned int)c; + // Replace %R + switch( val ) + { + REG_OUTPUT( mmPA_CL_VPORT_XSCALE ); REG_OUTPUT( mmPA_CL_VPORT_XOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_YSCALE ); + REG_OUTPUT( mmPA_CL_VPORT_YOFFSET ); REG_OUTPUT( mmPA_CL_VPORT_ZSCALE ); REG_OUTPUT( mmPA_CL_VPORT_ZOFFSET ); + REG_OUTPUT( mmPA_CL_VTE_CNTL ); REG_OUTPUT( mmPA_CL_CLIP_CNTL ); REG_OUTPUT( mmPA_CL_GB_VERT_CLIP_ADJ ); + REG_OUTPUT( mmPA_CL_GB_VERT_DISC_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_CLIP_ADJ ); REG_OUTPUT( mmPA_CL_GB_HORZ_DISC_ADJ ); + REG_OUTPUT( mmPA_CL_ENHANCE ); REG_OUTPUT( mmPA_SC_ENHANCE ); REG_OUTPUT( mmPA_SU_VTX_CNTL ); + REG_OUTPUT( mmPA_SU_POINT_SIZE ); REG_OUTPUT( mmPA_SU_POINT_MINMAX ); REG_OUTPUT( mmPA_SU_LINE_CNTL ); + REG_OUTPUT( mmPA_SU_FACE_DATA ); REG_OUTPUT( mmPA_SU_SC_MODE_CNTL ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_SCALE ); + REG_OUTPUT( mmPA_SU_POLY_OFFSET_FRONT_OFFSET ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_SCALE ); REG_OUTPUT( mmPA_SU_POLY_OFFSET_BACK_OFFSET ); + REG_OUTPUT( mmPA_SU_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_SELECT ); + REG_OUTPUT( mmPA_SU_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER0_HI ); + REG_OUTPUT( mmPA_SU_PERFCOUNTER1_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER1_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER2_LOW ); + REG_OUTPUT( mmPA_SU_PERFCOUNTER2_HI ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_LOW ); REG_OUTPUT( mmPA_SU_PERFCOUNTER3_HI ); + REG_OUTPUT( mmPA_SC_WINDOW_OFFSET ); REG_OUTPUT( mmPA_SC_AA_CONFIG ); REG_OUTPUT( mmPA_SC_AA_MASK ); + REG_OUTPUT( mmPA_SC_LINE_STIPPLE ); REG_OUTPUT( mmPA_SC_LINE_CNTL ); REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_TL ); + REG_OUTPUT( mmPA_SC_WINDOW_SCISSOR_BR ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_TL ); REG_OUTPUT( mmPA_SC_SCREEN_SCISSOR_BR ); + REG_OUTPUT( mmPA_SC_VIZ_QUERY ); REG_OUTPUT( mmPA_SC_VIZ_QUERY_STATUS ); REG_OUTPUT( mmPA_SC_LINE_STIPPLE_STATE ); + REG_OUTPUT( mmPA_SC_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_LOW ); REG_OUTPUT( mmPA_SC_PERFCOUNTER0_HI ); + REG_OUTPUT( mmPA_CL_CNTL_STATUS ); REG_OUTPUT( mmPA_SU_CNTL_STATUS ); REG_OUTPUT( mmPA_SC_CNTL_STATUS ); + REG_OUTPUT( mmPA_SU_DEBUG_CNTL ); REG_OUTPUT( mmPA_SU_DEBUG_DATA ); REG_OUTPUT( mmPA_SC_DEBUG_CNTL ); + REG_OUTPUT( mmPA_SC_DEBUG_DATA ); REG_OUTPUT( mmGFX_COPY_STATE ); REG_OUTPUT( mmVGT_DRAW_INITIATOR ); + REG_OUTPUT( mmVGT_EVENT_INITIATOR ); REG_OUTPUT( mmVGT_DMA_BASE ); REG_OUTPUT( mmVGT_DMA_SIZE ); + REG_OUTPUT( mmVGT_BIN_BASE ); REG_OUTPUT( mmVGT_BIN_SIZE ); REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MIN ); + REG_OUTPUT( mmVGT_CURRENT_BIN_ID_MAX ); REG_OUTPUT( mmVGT_IMMED_DATA ); REG_OUTPUT( mmVGT_MAX_VTX_INDX ); + REG_OUTPUT( mmVGT_MIN_VTX_INDX ); REG_OUTPUT( mmVGT_INDX_OFFSET ); REG_OUTPUT( mmVGT_VERTEX_REUSE_BLOCK_CNTL ); + REG_OUTPUT( mmVGT_OUT_DEALLOC_CNTL ); REG_OUTPUT( mmVGT_MULTI_PRIM_IB_RESET_INDX ); REG_OUTPUT( mmVGT_ENHANCE ); + REG_OUTPUT( mmVGT_VTX_VECT_EJECT_REG ); REG_OUTPUT( mmVGT_LAST_COPY_STATE ); REG_OUTPUT( mmVGT_DEBUG_CNTL ); + REG_OUTPUT( mmVGT_DEBUG_DATA ); REG_OUTPUT( mmVGT_CNTL_STATUS ); REG_OUTPUT( mmVGT_CRC_SQ_DATA ); + REG_OUTPUT( mmVGT_CRC_SQ_CTRL ); REG_OUTPUT( mmVGT_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER1_SELECT ); + REG_OUTPUT( mmVGT_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmVGT_PERFCOUNTER0_LOW ); + REG_OUTPUT( mmVGT_PERFCOUNTER1_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER2_LOW ); REG_OUTPUT( mmVGT_PERFCOUNTER3_LOW ); + REG_OUTPUT( mmVGT_PERFCOUNTER0_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER1_HI ); REG_OUTPUT( mmVGT_PERFCOUNTER2_HI ); + REG_OUTPUT( mmVGT_PERFCOUNTER3_HI ); REG_OUTPUT( mmTC_CNTL_STATUS ); REG_OUTPUT( mmTCR_CHICKEN ); + REG_OUTPUT( mmTCF_CHICKEN ); REG_OUTPUT( mmTCM_CHICKEN ); REG_OUTPUT( mmTCR_PERFCOUNTER0_SELECT ); + REG_OUTPUT( mmTCR_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTCR_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCR_PERFCOUNTER1_HI ); + REG_OUTPUT( mmTCR_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCR_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTP_TC_CLKGATE_CNTL ); + REG_OUTPUT( mmTPC_CNTL_STATUS ); REG_OUTPUT( mmTPC_DEBUG0 ); REG_OUTPUT( mmTPC_DEBUG1 ); + REG_OUTPUT( mmTPC_CHICKEN ); REG_OUTPUT( mmTP0_CNTL_STATUS ); REG_OUTPUT( mmTP0_DEBUG ); + REG_OUTPUT( mmTP0_CHICKEN ); REG_OUTPUT( mmTP0_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER0_HI ); + REG_OUTPUT( mmTP0_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTP0_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmTP0_PERFCOUNTER1_HI ); + REG_OUTPUT( mmTP0_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCM_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCM_PERFCOUNTER1_SELECT ); + REG_OUTPUT( mmTCM_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER1_HI ); REG_OUTPUT( mmTCM_PERFCOUNTER0_LOW ); + REG_OUTPUT( mmTCM_PERFCOUNTER1_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER1_SELECT ); + REG_OUTPUT( mmTCF_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER3_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER4_SELECT ); + REG_OUTPUT( mmTCF_PERFCOUNTER5_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER6_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER7_SELECT ); + REG_OUTPUT( mmTCF_PERFCOUNTER8_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER9_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER10_SELECT ); + REG_OUTPUT( mmTCF_PERFCOUNTER11_SELECT ); REG_OUTPUT( mmTCF_PERFCOUNTER0_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER1_HI ); + REG_OUTPUT( mmTCF_PERFCOUNTER2_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER3_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER4_HI ); + REG_OUTPUT( mmTCF_PERFCOUNTER5_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER6_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER7_HI ); + REG_OUTPUT( mmTCF_PERFCOUNTER8_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER9_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER10_HI ); + REG_OUTPUT( mmTCF_PERFCOUNTER11_HI ); REG_OUTPUT( mmTCF_PERFCOUNTER0_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER1_LOW ); + REG_OUTPUT( mmTCF_PERFCOUNTER2_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER3_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER4_LOW ); + REG_OUTPUT( mmTCF_PERFCOUNTER5_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER6_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER7_LOW ); + REG_OUTPUT( mmTCF_PERFCOUNTER8_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER9_LOW ); REG_OUTPUT( mmTCF_PERFCOUNTER10_LOW ); + REG_OUTPUT( mmTCF_PERFCOUNTER11_LOW ); REG_OUTPUT( mmTCF_DEBUG ); REG_OUTPUT( mmTCA_FIFO_DEBUG ); + REG_OUTPUT( mmTCA_PROBE_DEBUG ); REG_OUTPUT( mmTCA_TPC_DEBUG ); REG_OUTPUT( mmTCB_CORE_DEBUG ); + REG_OUTPUT( mmTCB_TAG0_DEBUG ); REG_OUTPUT( mmTCB_TAG1_DEBUG ); REG_OUTPUT( mmTCB_TAG2_DEBUG ); + REG_OUTPUT( mmTCB_TAG3_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG ); REG_OUTPUT( mmTCB_FETCH_GEN_WALKER_DEBUG ); + REG_OUTPUT( mmTCB_FETCH_GEN_PIPE0_DEBUG ); REG_OUTPUT( mmTCD_INPUT0_DEBUG ); REG_OUTPUT( mmTCD_DEGAMMA_DEBUG ); + REG_OUTPUT( mmTCD_DXTMUX_SCTARB_DEBUG ); REG_OUTPUT( mmTCD_DXTC_ARB_DEBUG ); REG_OUTPUT( mmTCD_STALLS_DEBUG ); + REG_OUTPUT( mmTCO_STALLS_DEBUG ); REG_OUTPUT( mmTCO_QUAD0_DEBUG0 ); REG_OUTPUT( mmTCO_QUAD0_DEBUG1 ); + REG_OUTPUT( mmSQ_GPR_MANAGEMENT ); REG_OUTPUT( mmSQ_FLOW_CONTROL ); REG_OUTPUT( mmSQ_INST_STORE_MANAGMENT ); + REG_OUTPUT( mmSQ_RESOURCE_MANAGMENT ); REG_OUTPUT( mmSQ_EO_RT ); REG_OUTPUT( mmSQ_DEBUG_MISC ); + REG_OUTPUT( mmSQ_ACTIVITY_METER_CNTL ); REG_OUTPUT( mmSQ_ACTIVITY_METER_STATUS ); REG_OUTPUT( mmSQ_INPUT_ARB_PRIORITY ); + REG_OUTPUT( mmSQ_THREAD_ARB_PRIORITY ); REG_OUTPUT( mmSQ_VS_WATCHDOG_TIMER ); REG_OUTPUT( mmSQ_PS_WATCHDOG_TIMER ); + REG_OUTPUT( mmSQ_INT_CNTL ); REG_OUTPUT( mmSQ_INT_STATUS ); REG_OUTPUT( mmSQ_INT_ACK ); + REG_OUTPUT( mmSQ_DEBUG_INPUT_FSM ); REG_OUTPUT( mmSQ_DEBUG_CONST_MGR_FSM ); REG_OUTPUT( mmSQ_DEBUG_TP_FSM ); + REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_0 ); REG_OUTPUT( mmSQ_DEBUG_FSM_ALU_1 ); REG_OUTPUT( mmSQ_DEBUG_EXP_ALLOC ); + REG_OUTPUT( mmSQ_DEBUG_PTR_BUFF ); REG_OUTPUT( mmSQ_DEBUG_GPR_VTX ); REG_OUTPUT( mmSQ_DEBUG_GPR_PIX ); + REG_OUTPUT( mmSQ_DEBUG_TB_STATUS_SEL ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_0 ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_1 ); + REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATUS_REG ); REG_OUTPUT( mmSQ_DEBUG_VTX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_0 ); + REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_0 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_1 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_2 ); + REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATUS_REG_3 ); REG_OUTPUT( mmSQ_DEBUG_PIX_TB_STATE_MEM ); REG_OUTPUT( mmSQ_PERFCOUNTER0_SELECT ); + REG_OUTPUT( mmSQ_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER2_SELECT ); REG_OUTPUT( mmSQ_PERFCOUNTER3_SELECT ); + REG_OUTPUT( mmSQ_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER1_LOW ); + REG_OUTPUT( mmSQ_PERFCOUNTER1_HI ); REG_OUTPUT( mmSQ_PERFCOUNTER2_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER2_HI ); + REG_OUTPUT( mmSQ_PERFCOUNTER3_LOW ); REG_OUTPUT( mmSQ_PERFCOUNTER3_HI ); REG_OUTPUT( mmSX_PERFCOUNTER0_SELECT ); + REG_OUTPUT( mmSX_PERFCOUNTER0_LOW ); REG_OUTPUT( mmSX_PERFCOUNTER0_HI ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_ALU_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_ALU_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_EXEC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_LOOP_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_JMP_CALL_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_CF_ALLOC_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_TFETCH_2 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_0 ); + REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_1 ); REG_OUTPUT( mmSQ_INSTRUCTION_VFETCH_2 ); REG_OUTPUT( mmSQ_CONSTANT_0 ); + REG_OUTPUT( mmSQ_CONSTANT_1 ); REG_OUTPUT( mmSQ_CONSTANT_2 ); REG_OUTPUT( mmSQ_CONSTANT_3 ); + REG_OUTPUT( mmSQ_FETCH_0 ); REG_OUTPUT( mmSQ_FETCH_1 ); REG_OUTPUT( mmSQ_FETCH_2 ); + REG_OUTPUT( mmSQ_FETCH_3 ); REG_OUTPUT( mmSQ_FETCH_4 ); REG_OUTPUT( mmSQ_FETCH_5 ); + REG_OUTPUT( mmSQ_CONSTANT_VFETCH_0 ); REG_OUTPUT( mmSQ_CONSTANT_VFETCH_1 ); REG_OUTPUT( mmSQ_CONSTANT_T2 ); + REG_OUTPUT( mmSQ_CONSTANT_T3 ); REG_OUTPUT( mmSQ_CF_BOOLEANS ); REG_OUTPUT( mmSQ_CF_LOOP ); + REG_OUTPUT( mmSQ_CONSTANT_RT_0 ); REG_OUTPUT( mmSQ_CONSTANT_RT_1 ); REG_OUTPUT( mmSQ_CONSTANT_RT_2 ); + REG_OUTPUT( mmSQ_CONSTANT_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_0 ); REG_OUTPUT( mmSQ_FETCH_RT_1 ); + REG_OUTPUT( mmSQ_FETCH_RT_2 ); REG_OUTPUT( mmSQ_FETCH_RT_3 ); REG_OUTPUT( mmSQ_FETCH_RT_4 ); + REG_OUTPUT( mmSQ_FETCH_RT_5 ); REG_OUTPUT( mmSQ_CF_RT_BOOLEANS ); REG_OUTPUT( mmSQ_CF_RT_LOOP ); + REG_OUTPUT( mmSQ_VS_PROGRAM ); REG_OUTPUT( mmSQ_PS_PROGRAM ); REG_OUTPUT( mmSQ_CF_PROGRAM_SIZE ); + REG_OUTPUT( mmSQ_INTERPOLATOR_CNTL ); REG_OUTPUT( mmSQ_PROGRAM_CNTL ); REG_OUTPUT( mmSQ_WRAPPING_0 ); + REG_OUTPUT( mmSQ_WRAPPING_1 ); REG_OUTPUT( mmSQ_VS_CONST ); REG_OUTPUT( mmSQ_PS_CONST ); + REG_OUTPUT( mmSQ_CONTEXT_MISC ); REG_OUTPUT( mmSQ_CF_RD_BASE ); REG_OUTPUT( mmSQ_DEBUG_MISC_0 ); + REG_OUTPUT( mmSQ_DEBUG_MISC_1 ); REG_OUTPUT( mmMH_ARBITER_CONFIG ); REG_OUTPUT( mmMH_CLNT_AXI_ID_REUSE ); + REG_OUTPUT( mmMH_INTERRUPT_MASK ); REG_OUTPUT( mmMH_INTERRUPT_STATUS ); REG_OUTPUT( mmMH_INTERRUPT_CLEAR ); + REG_OUTPUT( mmMH_AXI_ERROR ); REG_OUTPUT( mmMH_PERFCOUNTER0_SELECT ); REG_OUTPUT( mmMH_PERFCOUNTER1_SELECT ); + REG_OUTPUT( mmMH_PERFCOUNTER0_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER1_CONFIG ); REG_OUTPUT( mmMH_PERFCOUNTER0_LOW ); + REG_OUTPUT( mmMH_PERFCOUNTER1_LOW ); REG_OUTPUT( mmMH_PERFCOUNTER0_HI ); REG_OUTPUT( mmMH_PERFCOUNTER1_HI ); + REG_OUTPUT( mmMH_DEBUG_CTRL ); REG_OUTPUT( mmMH_DEBUG_DATA ); REG_OUTPUT( mmMH_AXI_HALT_CONTROL ); + REG_OUTPUT( mmMH_MMU_CONFIG ); REG_OUTPUT( mmMH_MMU_VA_RANGE ); REG_OUTPUT( mmMH_MMU_PT_BASE ); + REG_OUTPUT( mmMH_MMU_PAGE_FAULT ); REG_OUTPUT( mmMH_MMU_TRAN_ERROR ); REG_OUTPUT( mmMH_MMU_INVALIDATE ); + REG_OUTPUT( mmMH_MMU_MPU_BASE ); REG_OUTPUT( mmMH_MMU_MPU_END ); REG_OUTPUT( mmWAIT_UNTIL ); + REG_OUTPUT( mmRBBM_ISYNC_CNTL ); REG_OUTPUT( mmRBBM_STATUS ); REG_OUTPUT( mmRBBM_DSPLY ); + REG_OUTPUT( mmRBBM_RENDER_LATEST ); REG_OUTPUT( mmRBBM_RTL_RELEASE ); REG_OUTPUT( mmRBBM_PATCH_RELEASE ); + REG_OUTPUT( mmRBBM_AUXILIARY_CONFIG ); REG_OUTPUT( mmRBBM_PERIPHID0 ); REG_OUTPUT( mmRBBM_PERIPHID1 ); + REG_OUTPUT( mmRBBM_PERIPHID2 ); REG_OUTPUT( mmRBBM_PERIPHID3 ); REG_OUTPUT( mmRBBM_CNTL ); + REG_OUTPUT( mmRBBM_SKEW_CNTL ); REG_OUTPUT( mmRBBM_SOFT_RESET ); REG_OUTPUT( mmRBBM_PM_OVERRIDE1 ); + REG_OUTPUT( mmRBBM_PM_OVERRIDE2 ); REG_OUTPUT( mmGC_SYS_IDLE ); REG_OUTPUT( mmNQWAIT_UNTIL ); + REG_OUTPUT( mmRBBM_DEBUG_OUT ); REG_OUTPUT( mmRBBM_DEBUG_CNTL ); REG_OUTPUT( mmRBBM_DEBUG ); + REG_OUTPUT( mmRBBM_READ_ERROR ); REG_OUTPUT( mmRBBM_WAIT_IDLE_CLOCKS ); REG_OUTPUT( mmRBBM_INT_CNTL ); + REG_OUTPUT( mmRBBM_INT_STATUS ); REG_OUTPUT( mmRBBM_INT_ACK ); REG_OUTPUT( mmMASTER_INT_SIGNAL ); + REG_OUTPUT( mmRBBM_PERFCOUNTER1_SELECT ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_LO ); REG_OUTPUT( mmRBBM_PERFCOUNTER1_HI ); + REG_OUTPUT( mmCP_RB_BASE ); REG_OUTPUT( mmCP_RB_CNTL ); REG_OUTPUT( mmCP_RB_RPTR_ADDR ); + REG_OUTPUT( mmCP_RB_RPTR ); REG_OUTPUT( mmCP_RB_RPTR_WR ); REG_OUTPUT( mmCP_RB_WPTR ); + REG_OUTPUT( mmCP_RB_WPTR_DELAY ); REG_OUTPUT( mmCP_RB_WPTR_BASE ); REG_OUTPUT( mmCP_IB1_BASE ); + REG_OUTPUT( mmCP_IB1_BUFSZ ); REG_OUTPUT( mmCP_IB2_BASE ); REG_OUTPUT( mmCP_IB2_BUFSZ ); + REG_OUTPUT( mmCP_ST_BASE ); REG_OUTPUT( mmCP_ST_BUFSZ ); REG_OUTPUT( mmCP_QUEUE_THRESHOLDS ); + REG_OUTPUT( mmCP_MEQ_THRESHOLDS ); REG_OUTPUT( mmCP_CSQ_AVAIL ); REG_OUTPUT( mmCP_STQ_AVAIL ); + REG_OUTPUT( mmCP_MEQ_AVAIL ); REG_OUTPUT( mmCP_CSQ_RB_STAT ); REG_OUTPUT( mmCP_CSQ_IB1_STAT ); + REG_OUTPUT( mmCP_CSQ_IB2_STAT ); REG_OUTPUT( mmCP_NON_PREFETCH_CNTRS ); REG_OUTPUT( mmCP_STQ_ST_STAT ); + REG_OUTPUT( mmCP_MEQ_STAT ); REG_OUTPUT( mmCP_MIU_TAG_STAT ); REG_OUTPUT( mmCP_CMD_INDEX ); + REG_OUTPUT( mmCP_CMD_DATA ); REG_OUTPUT( mmCP_ME_CNTL ); REG_OUTPUT( mmCP_ME_STATUS ); + REG_OUTPUT( mmCP_ME_RAM_WADDR ); REG_OUTPUT( mmCP_ME_RAM_RADDR ); REG_OUTPUT( mmCP_ME_RAM_DATA ); + REG_OUTPUT( mmCP_ME_RDADDR ); REG_OUTPUT( mmCP_DEBUG ); REG_OUTPUT( mmSCRATCH_REG0 ); + REG_OUTPUT( mmSCRATCH_REG1 ); REG_OUTPUT( mmSCRATCH_REG2 ); REG_OUTPUT( mmSCRATCH_REG3 ); + REG_OUTPUT( mmSCRATCH_REG4 ); REG_OUTPUT( mmSCRATCH_REG5 ); REG_OUTPUT( mmSCRATCH_REG6 ); + REG_OUTPUT( mmSCRATCH_REG7 ); + REG_OUTPUT( mmSCRATCH_UMSK ); REG_OUTPUT( mmSCRATCH_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_SRC ); + REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_VS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_VS_EVENT_ADDR_SWM ); + REG_OUTPUT( mmCP_ME_VS_EVENT_DATA_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_SRC ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR ); + REG_OUTPUT( mmCP_ME_PS_EVENT_DATA ); REG_OUTPUT( mmCP_ME_PS_EVENT_ADDR_SWM ); REG_OUTPUT( mmCP_ME_PS_EVENT_DATA_SWM ); + REG_OUTPUT( mmCP_ME_CF_EVENT_SRC ); REG_OUTPUT( mmCP_ME_CF_EVENT_ADDR ); REG_OUTPUT( mmCP_ME_CF_EVENT_DATA ); + REG_OUTPUT( mmCP_ME_NRT_ADDR ); REG_OUTPUT( mmCP_ME_NRT_DATA ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_SRC ); + REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_ADDR ); REG_OUTPUT( mmCP_ME_VS_FETCH_DONE_DATA ); REG_OUTPUT( mmCP_INT_CNTL ); + REG_OUTPUT( mmCP_INT_STATUS ); REG_OUTPUT( mmCP_INT_ACK ); REG_OUTPUT( mmCP_PFP_UCODE_ADDR ); + REG_OUTPUT( mmCP_PFP_UCODE_DATA ); REG_OUTPUT( mmCP_PERFMON_CNTL ); REG_OUTPUT( mmCP_PERFCOUNTER_SELECT ); + REG_OUTPUT( mmCP_PERFCOUNTER_LO ); REG_OUTPUT( mmCP_PERFCOUNTER_HI ); REG_OUTPUT( mmCP_BIN_MASK_LO ); + REG_OUTPUT( mmCP_BIN_MASK_HI ); REG_OUTPUT( mmCP_BIN_SELECT_LO ); REG_OUTPUT( mmCP_BIN_SELECT_HI ); + REG_OUTPUT( mmCP_NV_FLAGS_0 ); REG_OUTPUT( mmCP_NV_FLAGS_1 ); REG_OUTPUT( mmCP_NV_FLAGS_2 ); + REG_OUTPUT( mmCP_NV_FLAGS_3 ); REG_OUTPUT( mmCP_STATE_DEBUG_INDEX ); REG_OUTPUT( mmCP_STATE_DEBUG_DATA ); + REG_OUTPUT( mmCP_PROG_COUNTER ); REG_OUTPUT( mmCP_STAT ); REG_OUTPUT( mmBIOS_0_SCRATCH ); + REG_OUTPUT( mmBIOS_1_SCRATCH ); REG_OUTPUT( mmBIOS_2_SCRATCH ); REG_OUTPUT( mmBIOS_3_SCRATCH ); + REG_OUTPUT( mmBIOS_4_SCRATCH ); REG_OUTPUT( mmBIOS_5_SCRATCH ); REG_OUTPUT( mmBIOS_6_SCRATCH ); + REG_OUTPUT( mmBIOS_7_SCRATCH ); REG_OUTPUT( mmBIOS_8_SCRATCH ); REG_OUTPUT( mmBIOS_9_SCRATCH ); + REG_OUTPUT( mmBIOS_10_SCRATCH ); REG_OUTPUT( mmBIOS_11_SCRATCH ); REG_OUTPUT( mmBIOS_12_SCRATCH ); + REG_OUTPUT( mmBIOS_13_SCRATCH ); REG_OUTPUT( mmBIOS_14_SCRATCH ); REG_OUTPUT( mmBIOS_15_SCRATCH ); + REG_OUTPUT( mmCOHER_SIZE_PM4 ); REG_OUTPUT( mmCOHER_BASE_PM4 ); REG_OUTPUT( mmCOHER_STATUS_PM4 ); + REG_OUTPUT( mmCOHER_SIZE_HOST ); REG_OUTPUT( mmCOHER_BASE_HOST ); REG_OUTPUT( mmCOHER_STATUS_HOST ); + REG_OUTPUT( mmCOHER_DEST_BASE_0 ); REG_OUTPUT( mmCOHER_DEST_BASE_1 ); REG_OUTPUT( mmCOHER_DEST_BASE_2 ); + REG_OUTPUT( mmCOHER_DEST_BASE_3 ); REG_OUTPUT( mmCOHER_DEST_BASE_4 ); REG_OUTPUT( mmCOHER_DEST_BASE_5 ); + REG_OUTPUT( mmCOHER_DEST_BASE_6 ); REG_OUTPUT( mmCOHER_DEST_BASE_7 ); REG_OUTPUT( mmRB_SURFACE_INFO ); + REG_OUTPUT( mmRB_COLOR_INFO ); REG_OUTPUT( mmRB_DEPTH_INFO ); REG_OUTPUT( mmRB_STENCILREFMASK ); + REG_OUTPUT( mmRB_ALPHA_REF ); REG_OUTPUT( mmRB_COLOR_MASK ); REG_OUTPUT( mmRB_BLEND_RED ); + REG_OUTPUT( mmRB_BLEND_GREEN ); REG_OUTPUT( mmRB_BLEND_BLUE ); REG_OUTPUT( mmRB_BLEND_ALPHA ); + REG_OUTPUT( mmRB_FOG_COLOR ); REG_OUTPUT( mmRB_STENCILREFMASK_BF ); REG_OUTPUT( mmRB_DEPTHCONTROL ); + REG_OUTPUT( mmRB_BLENDCONTROL ); REG_OUTPUT( mmRB_COLORCONTROL ); REG_OUTPUT( mmRB_MODECONTROL ); + REG_OUTPUT( mmRB_COLOR_DEST_MASK ); REG_OUTPUT( mmRB_COPY_CONTROL ); REG_OUTPUT( mmRB_COPY_DEST_BASE ); + REG_OUTPUT( mmRB_COPY_DEST_PITCH ); REG_OUTPUT( mmRB_COPY_DEST_INFO ); REG_OUTPUT( mmRB_COPY_DEST_PIXEL_OFFSET ); + REG_OUTPUT( mmRB_DEPTH_CLEAR ); REG_OUTPUT( mmRB_SAMPLE_COUNT_CTL ); REG_OUTPUT( mmRB_SAMPLE_COUNT_ADDR ); + REG_OUTPUT( mmRB_BC_CONTROL ); REG_OUTPUT( mmRB_EDRAM_INFO ); REG_OUTPUT( mmRB_CRC_RD_PORT ); + REG_OUTPUT( mmRB_CRC_CONTROL ); REG_OUTPUT( mmRB_CRC_MASK ); REG_OUTPUT( mmRB_PERFCOUNTER0_SELECT ); + REG_OUTPUT( mmRB_PERFCOUNTER0_LOW ); REG_OUTPUT( mmRB_PERFCOUNTER0_HI ); REG_OUTPUT( mmRB_TOTAL_SAMPLES ); + REG_OUTPUT( mmRB_ZPASS_SAMPLES ); REG_OUTPUT( mmRB_ZFAIL_SAMPLES ); REG_OUTPUT( mmRB_SFAIL_SAMPLES ); + REG_OUTPUT( mmRB_DEBUG_0 ); REG_OUTPUT( mmRB_DEBUG_1 ); REG_OUTPUT( mmRB_DEBUG_2 ); + REG_OUTPUT( mmRB_DEBUG_3 ); REG_OUTPUT( mmRB_DEBUG_4 ); REG_OUTPUT( mmRB_FLAG_CONTROL ); + REG_OUTPUT( mmRB_BC_SPARES ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_ENUMS ); REG_OUTPUT( mmBC_DUMMY_CRAYRB_MOREENUMS ); + + default: + b += sprintf( b, "%s", "UNKNOWN REGISTER OFFSET" ); + break; + } + // Handle string after %R + kos_memcpy( b, p1+2, p2-(p1+2) ); + b += (unsigned int)p2-(unsigned int)(p1+2); + *b = '\0'; + } + break; + + + default: + { + int val = va_arg( arguments, int ); + // Standard format. Use vsprintf. + b += sprintf( b, buffer2, val ); + } + break; + } + + + c = p2; + } + + // Add this string to all outputs + output = outputs; + + while( output != NULL ) + { + // Filter according to the flags + if( ( output->flags & log_flags ) == log_flags ) + { + // Passed the filter. Now commit this message. + switch( output->type ) + { + case KGSL_OUTPUT_TYPE_MEMBUF: + // TODO + break; + + case KGSL_OUTPUT_TYPE_STDOUT: + // Write timestamp if enabled + if( output->flags & KGSL_LOG_TIMESTAMP ) + printf( "[Timestamp: %d] ", kos_timestamp() ); + // Write process id if enabled + if( output->flags & KGSL_LOG_PROCESS_ID ) + printf( "[Process ID: %d] ", kos_process_getid() ); + // Write thread id if enabled + if( output->flags & KGSL_LOG_THREAD_ID ) + printf( "[Thread ID: %d] ", kos_thread_getid() ); + + // Write the message + printf( buffer ); + break; + + case KGSL_OUTPUT_TYPE_FILE: + // Write timestamp if enabled + if( output->flags & KGSL_LOG_TIMESTAMP ) + kos_fprintf( output->file, "[Timestamp: %d] ", kos_timestamp() ); + // Write process id if enabled + if( output->flags & KGSL_LOG_PROCESS_ID ) + kos_fprintf( output->file, "[Process ID: %d] ", kos_process_getid() ); + // Write thread id if enabled + if( output->flags & KGSL_LOG_THREAD_ID ) + kos_fprintf( output->file, "[Thread ID: %d] ", kos_thread_getid() ); + + // Write the message + kos_fprintf( output->file, buffer ); + break; + } + } + + output = output->next; + } + + va_end( arguments ); + + kos_mutex_unlock( log_mutex ); + + return GSL_SUCCESS; +} + +//---------------------------------------------------------------------------- +#endif diff --git a/drivers/mxc/amd-gpu/common/gsl_memmgr.c b/drivers/mxc/amd-gpu/common/gsl_memmgr.c new file mode 100644 index 000000000000..75f250ae59b1 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_memmgr.c @@ -0,0 +1,949 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMARENAPRIV_SIGNATURE_MASK 0x0000FFFF +#define GSL_MEMARENAPRIV_APERTUREID_MASK 0xF0000000 +#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK 0x0F000000 + +#define GSL_MEMARENAPRIV_SIGNATURE_SHIFT 0 +#define GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT 24 +#define GSL_MEMARENAPRIV_APERTUREID_SHIFT 28 + +#define GSL_MEMARENA_INSTANCE_SIGNATURE 0x0000CAFE + +#ifdef GSL_STATS_MEM +#define GSL_MEMARENA_STATS(x) x +#else +#define GSL_MEMARENA_STATS(x) +#endif // GSL_STATS_MEM + + +///////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMARENA_LOCK() kos_mutex_lock(memarena->mutex) +#define GSL_MEMARENA_UNLOCK() kos_mutex_unlock(memarena->mutex) + +#define GSL_MEMARENA_SET_SIGNATURE (memarena->priv |= ((GSL_MEMARENA_INSTANCE_SIGNATURE << GSL_MEMARENAPRIV_SIGNATURE_SHIFT) & GSL_MEMARENAPRIV_SIGNATURE_MASK)) +#define GSL_MEMARENA_SET_MMU_VIRTUALIZED (memarena->priv |= ((mmu_virtualized << GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT) & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK)) +#define GSL_MEMARENA_SET_ID (memarena->priv |= ((aperture_id << GSL_MEMARENAPRIV_APERTUREID_SHIFT) & GSL_MEMARENAPRIV_APERTUREID_MASK)) + +#define GSL_MEMARENA_GET_SIGNATURE ((memarena->priv & GSL_MEMARENAPRIV_SIGNATURE_MASK) >> GSL_MEMARENAPRIV_SIGNATURE_SHIFT) +#define GSL_MEMARENA_IS_MMU_VIRTUALIZED ((memarena->priv & GSL_MEMARENAPRIV_MMUVIRTUALIZED_MASK) >> GSL_MEMARENAPRIV_MMUVIRTUALIZED_SHIFT) +#define GSL_MEMARENA_GET_ID ((memarena->priv & GSL_MEMARENAPRIV_APERTUREID_MASK) >> GSL_MEMARENAPRIV_APERTUREID_SHIFT) + + +////////////////////////////////////////////////////////////////////////////// +// validate +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMARENA_VALIDATE(memarena) \ + KOS_ASSERT(memarena); \ + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) \ + { \ + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, \ + "ERROR: Memarena validation failed.\n" ); \ + return (GSL_FAILURE); \ + } + +////////////////////////////////////////////////////////////////////////////// +// block alignment shift count +////////////////////////////////////////////////////////////////////////////// +OSINLINE unsigned int +gsl_memarena_alignmentshift(gsl_flags_t flags) +{ + int alignshift = ((flags & GSL_MEMFLAGS_ALIGN_MASK) >> GSL_MEMFLAGS_ALIGN_SHIFT); + if (alignshift == 0) + alignshift = 5; // 32 bytes is the minimum alignment boundary + return (alignshift); +} + +////////////////////////////////////////////////////////////////////////////// +// address alignment +////////////////////////////////////////////////////////////////////////////// +OSINLINE unsigned int +gsl_memarena_alignaddr(unsigned int address, int shift) +{ + // + // the value of the returned address is guaranteed to be an even multiple + // of the block alignment shift specified. + // + unsigned int alignedbaseaddr = ((address) >> shift) << shift; + if (alignedbaseaddr < address) + { + alignedbaseaddr += (1 << shift); + } + return (alignedbaseaddr); +} + + +////////////////////////////////////////////////////////////////////////////// +// memory management API +////////////////////////////////////////////////////////////////////////////// + +OSINLINE memblk_t* +kgsl_memarena_getmemblknode(gsl_memarena_t *memarena) +{ +#ifdef GSL_MEMARENA_NODE_POOL_ENABLED + gsl_nodepool_t *nodepool = memarena->nodepool; + memblk_t *memblk = NULL; + int allocnewpool = 1; + int i; + + if (nodepool) + { + // walk through list of existing pools + for ( ; ; ) + { + // if there is a pool with a free memblk node + if (nodepool->priv != (1 << GSL_MEMARENA_NODE_POOL_MAX)-1) + { + // get index of the first free memblk node + for (i = 0; i < GSL_MEMARENA_NODE_POOL_MAX; i++) + { + if (((nodepool->priv >> i) & 0x1) == 0) + { + break; + } + } + + // mark memblk node as used + nodepool->priv |= 1 << i; + + memblk = &nodepool->memblk[i]; + memblk->nodepoolindex = i; + memblk->blkaddr = 0; + memblk->blksize = 0; + + allocnewpool = 0; + + break; + } + else + { + nodepool = nodepool->next; + + if (nodepool == memarena->nodepool) + { + // no free memblk node found + break; + } + } + } + } + + // if no existing pool has a free memblk node + if (allocnewpool) + { + // alloc new pool of memblk nodes + nodepool = ((gsl_nodepool_t *)kos_malloc(sizeof(gsl_nodepool_t))); + if (nodepool) + { + kos_memset(nodepool, 0, sizeof(gsl_nodepool_t)); + + if (memarena->nodepool) + { + nodepool->next = memarena->nodepool->next; + nodepool->prev = memarena->nodepool; + memarena->nodepool->next->prev = nodepool; + memarena->nodepool->next = nodepool; + } + else + { + nodepool->next = nodepool; + nodepool->prev = nodepool; + } + + // reposition pool head + memarena->nodepool = nodepool; + + // mark memblk node as used + nodepool->priv |= 0x1; + + memblk = &nodepool->memblk[0]; + memblk->nodepoolindex = 0; + } + } + + KOS_ASSERT(memblk); + + return (memblk); +#else + // unreferenced formal parameter + (void) memarena; + + return ((memblk_t *)kos_malloc(sizeof(memblk_t))); +#endif // GSL_MEMARENA_NODE_POOL_ENABLED +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_memarena_releasememblknode(gsl_memarena_t *memarena, memblk_t *memblk) +{ +#ifdef GSL_MEMARENA_NODE_POOL_ENABLED + gsl_nodepool_t *nodepool = memarena->nodepool; + + KOS_ASSERT(memblk); + KOS_ASSERT(nodepool); + + // locate pool to which this memblk node belongs + while (((unsigned int) memblk) < ((unsigned int) nodepool) || + ((unsigned int) memblk) > ((unsigned int) nodepool) + sizeof(gsl_nodepool_t)) + { + nodepool = nodepool->prev; + + KOS_ASSERT(nodepool != memarena->nodepool); + } + + // mark memblk node as unused + nodepool->priv &= ~(1 << memblk->nodepoolindex); + + // free pool when all its memblk nodes are unused + if (nodepool->priv == 0) + { + if (nodepool != nodepool->prev) + { + // reposition pool head + if (nodepool == memarena->nodepool) + { + memarena->nodepool = nodepool->prev; + } + + nodepool->prev->next = nodepool->next; + nodepool->next->prev = nodepool->prev; + } + else + { + memarena->nodepool = NULL; + } + + kos_free((void *)nodepool); + } + else + { + // leave pool head in last pool a memblk node was released + memarena->nodepool = nodepool; + } +#else + // unreferenced formal parameter + (void) memarena; + + kos_free((void *)memblk); +#endif // GSL_MEMARENA_NODE_POOL_ENABLED +} + +//---------------------------------------------------------------------------- + +gsl_memarena_t* +kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes) +{ + static int count = 0; + char name[100], id_str[2]; + int len; + gsl_memarena_t *memarena; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> gsl_memarena_t* kgsl_memarena_create(int aperture_id=%d, gpuaddr_t gpubaseaddr=0x%08x, int sizebytes=%d)\n", aperture_id, gpubaseaddr, sizebytes ); + + memarena = (gsl_memarena_t *)kos_malloc(sizeof(gsl_memarena_t)); + + if (!memarena) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, + "ERROR: Memarena allocation failed.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "<-- kgsl_memarena_create. Return value: 0x%08x\n", NULL ); + return (NULL); + } + + kos_memset(memarena, 0, sizeof(gsl_memarena_t)); + + GSL_MEMARENA_SET_SIGNATURE; + GSL_MEMARENA_SET_MMU_VIRTUALIZED; + GSL_MEMARENA_SET_ID; + + // define unique mutex for each memory arena instance + id_str[0] = (char) (count + '0'); + id_str[1] = '\0'; + kos_strcpy(name, "GSL_memory_arena_"); + len = kos_strlen(name); + kos_strcpy(&name[len], id_str); + + memarena->mutex = kos_mutex_create(name); + + // set up the memory arena + memarena->hostbaseaddr = hostbaseaddr; + memarena->gpubaseaddr = gpubaseaddr; + memarena->sizebytes = sizebytes; + + // allocate a memory block in free list which represents all memory in arena + memarena->freelist.head = kgsl_memarena_getmemblknode(memarena); + memarena->freelist.head->blkaddr = 0; + memarena->freelist.head->blksize = memarena->sizebytes; + memarena->freelist.head->next = memarena->freelist.head; + memarena->freelist.head->prev = memarena->freelist.head; + memarena->freelist.allocrover = memarena->freelist.head; + memarena->freelist.freerover = memarena->freelist.head; + + count++; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_create. Return value: 0x%08x\n", memarena ); + + return (memarena); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_destroy(gsl_memarena_t *memarena) +{ + int status = GSL_SUCCESS; + memblk_t *p, *next; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_destroy(gsl_memarena_t *memarena=0x%08x)\n", memarena ); + + GSL_MEMARENA_VALIDATE(memarena); + + GSL_MEMARENA_LOCK(); + +#ifdef _DEBUG + // memory leak check + if (memarena->freelist.head->blksize != memarena->sizebytes) + { + if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM) + { + // external memory leak detected + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, + "ERROR: External memory leak detected.\n" ); + return (GSL_FAILURE); + } + } +#endif // _DEBUG + + p = memarena->freelist.head; + do + { + next = p->next; + kgsl_memarena_releasememblknode(memarena, p); + p = next; + } while (p != memarena->freelist.head); + + GSL_MEMARENA_UNLOCK(); + + if (memarena->mutex) + { + kos_mutex_free(memarena->mutex); + } + + kos_free((void *)memarena); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_destroy. Return value: %B\n", GSL_SUCCESS ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_isvirtualized(gsl_memarena_t *memarena) +{ + // mmu virtualization enabled + return (GSL_MEMARENA_IS_MMU_VIRTUALIZED); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_checkconsistency(gsl_memarena_t *memarena) +{ + memblk_t *p; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_checkconsistency(gsl_memarena_t *memarena=0x%08x)\n", memarena ); + + // go through list of free blocks and make sure there are no detectable errors + + p = memarena->freelist.head; + do + { + if (p->next->blkaddr != memarena->freelist.head->blkaddr) + { + if (p->prev->next->blkaddr != p->blkaddr || + p->next->prev->blkaddr != p->blkaddr || + p->blkaddr + p->blksize >= p->next->blkaddr) + { + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + } + p = p->next; + + } while (p != memarena->freelist.head); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkconsistency. Return value: %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats) +{ +#ifdef GSL_STATS_MEM + KOS_ASSERT(stats); + GSL_MEMARENA_VALIDATE(memarena); + + kos_memcpy(stats, &memarena->stats, sizeof(gsl_memarena_stats_t)); + + return (GSL_SUCCESS); +#else + // unreferenced formal parameters + (void) memarena; + (void) stats; + + return (GSL_FAILURE_NOTSUPPORTED); +#endif // GSL_STATS_MEM +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena, int bytesneeded) +{ + memblk_t *p; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_checkfreeblock(gsl_memarena_t *memarena=0x%08x, int bytesneeded=%d)\n", memarena, bytesneeded ); + + GSL_MEMARENA_VALIDATE(memarena); + + if (bytesneeded < 1) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal number of bytes needed.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_MEMARENA_LOCK(); + + p = memarena->freelist.head; + do + { + if (p->blksize >= (unsigned int)bytesneeded) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + p = p->next; + } while (p != memarena->freelist.head); + + GSL_MEMARENA_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_checkfreeblock. Return value: %B\n", GSL_FAILURE ); + + return (GSL_FAILURE); +} + +//---------------------------------------------------------------------------- + +int +kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc) +{ + int result = GSL_FAILURE_OUTOFMEM; + memblk_t *ptrfree, *ptrlast, *p; + unsigned int blksize; + unsigned int baseaddr, alignedbaseaddr, alignfragment; + int freeblk, alignmentshift; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_alloc(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x, int size=%d, gsl_memdesc_t *memdesc=%M)\n", memarena, flags, size, memdesc ); + + GSL_MEMARENA_VALIDATE(memarena); + + if (size <= 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid size for memory allocation.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // + // go through the list of free blocks. check to find block which can satisfy the alloc request + // + // if no block can satisfy the alloc request this implies that the memory is too fragmented + // and the requestor needs to free up other memory blocks and re-request the allocation + // + // if we do find a block that can satisfy the alloc request then reduce the size of free block + // by blksize and return the address after allocating the memory. if the free block size becomes + // 0 then remove this node from the free list + // + // there would be no node on the free list if all available memory were to be allocated. + // handling an empty list would require executing error checking code in the main branch which + // is not desired. instead, the free list will have at least one node at all times. This node + // could have a block size of zero + // + // we use a next fit allocation mechanism that uses a roving pointer on a circular free block list. + // the pointer is advanced along the chain when searching for a fit. Thus each allocation begins + // looking where the previous one finished. + // + + // when allocating from external memory aperture, round up size of requested block to multiple of page size if needed + if (GSL_MEMARENA_GET_ID == GSL_APERTURE_EMEM) + { + if ((flags & GSL_MEMFLAGS_FORCEPAGESIZE) || GSL_MEMARENA_IS_MMU_VIRTUALIZED) + { + if (size & (GSL_PAGESIZE-1)) + { + size = ((size >> GSL_PAGESIZE_SHIFT) + 1) << GSL_PAGESIZE_SHIFT; + } + } + } + + // determine shift count for alignment requested + alignmentshift = gsl_memarena_alignmentshift(flags); + + // adjust size of requested block to include alignment + blksize = (unsigned int)((size + ((1 << alignmentshift) - 1)) >> alignmentshift) << alignmentshift; + + GSL_MEMARENA_LOCK(); + + // check consistency, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena)); + + ptrfree = memarena->freelist.allocrover; + ptrlast = memarena->freelist.head->prev; + freeblk = 0; + + do + { + // align base address + baseaddr = ptrfree->blkaddr + memarena->gpubaseaddr; + alignedbaseaddr = gsl_memarena_alignaddr(baseaddr, alignmentshift); + + alignfragment = alignedbaseaddr - baseaddr; + + if (ptrfree->blksize >= blksize + alignfragment) + { + result = GSL_SUCCESS; + freeblk = 1; + + memdesc->gpuaddr = alignedbaseaddr; + memdesc->hostptr = kgsl_memarena_gethostptr(memarena, memdesc->gpuaddr); + memdesc->size = blksize; + + if (alignfragment > 0) + { + // insert new node to handle newly created (small) fragment + p = kgsl_memarena_getmemblknode(memarena); + p->blkaddr = ptrfree->blkaddr; + p->blksize = alignfragment; + + p->next = ptrfree; + p->prev = ptrfree->prev; + ptrfree->prev->next = p; + ptrfree->prev = p; + + if (ptrfree == memarena->freelist.head) + { + memarena->freelist.head = p; + } + } + + ptrfree->blkaddr += alignfragment + blksize; + ptrfree->blksize -= alignfragment + blksize; + + memarena->freelist.allocrover = ptrfree; + + if (ptrfree->blksize == 0 && ptrfree != ptrlast) + { + ptrfree->prev->next = ptrfree->next; + ptrfree->next->prev = ptrfree->prev; + if (ptrfree == memarena->freelist.head) + { + memarena->freelist.head = ptrfree->next; + } + if (ptrfree == memarena->freelist.allocrover) + { + memarena->freelist.allocrover = ptrfree->next; + } + if (ptrfree == memarena->freelist.freerover) + { + memarena->freelist.freerover = ptrfree->prev; + } + p = ptrfree; + ptrfree = ptrfree->prev; + kgsl_memarena_releasememblknode(memarena, p); + } + } + + ptrfree = ptrfree->next; + + } while (!freeblk && ptrfree != memarena->freelist.allocrover); + + GSL_MEMARENA_UNLOCK(); + + if (result == GSL_SUCCESS) + { + GSL_MEMARENA_STATS( + { + int i = 0; + while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i)) + { + i++; + } + i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i; + memarena->stats.allocs_pagedistribution[i]++; + }); + + GSL_MEMARENA_STATS(memarena->stats.allocs_success++); + } + else + { + GSL_MEMARENA_STATS(memarena->stats.allocs_fail++); + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_alloc. Return value: %B\n", result ); + + return (result); +} + +//---------------------------------------------------------------------------- + +void +kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc) +{ + // + // request to free a malloc'ed block from the memory arena + // add this block to the free list + // adding a block to the free list requires the following: + // going through the list of free blocks to decide where to add this free block (based on address) + // coalesce free blocks + // + memblk_t *ptrfree, *ptrend, *p; + int mallocfreeblk, clockwise; + unsigned int addrtofree; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> void kgsl_memarena_free(gsl_memarena_t *memarena=0x%08x, gsl_memdesc_t *memdesc=%M)\n", memarena, memdesc ); + + KOS_ASSERT(memarena); + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" ); + return; + } + + // check size of malloc'ed block + if (memdesc->size <= 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Illegal size for the memdesc.\n" ); + KOS_ASSERT(0); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" ); + return; + } + + // check address range + KOS_ASSERT( memarena->gpubaseaddr <= memdesc->gpuaddr); + KOS_ASSERT((memarena->gpubaseaddr + memarena->sizebytes) >= memdesc->gpuaddr + memdesc->size); + + GSL_MEMARENA_LOCK(); + + // check consistency of memory map, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MEMMGR, kgsl_memarena_checkconsistency(memarena)); + + addrtofree = memdesc->gpuaddr - memarena->gpubaseaddr; + mallocfreeblk = 1; + + if (addrtofree < memarena->freelist.head->blkaddr) + { + // add node to head of free list + + if (addrtofree + memdesc->size == memarena->freelist.head->blkaddr) + { + memarena->freelist.head->blkaddr = addrtofree; + memarena->freelist.head->blksize += memdesc->size; + + mallocfreeblk = 0; + } + + ptrfree = memarena->freelist.head->prev; + } + else if (addrtofree >= memarena->freelist.head->prev->blkaddr) + { + // add node to tail of free list + + ptrfree = memarena->freelist.head->prev; + + if (ptrfree->blkaddr + ptrfree->blksize == addrtofree) + { + ptrfree->blksize += memdesc->size; + + mallocfreeblk = 0; + } + } + else + { + // determine range of free list nodes to traverse and orientation in which to traverse them + // keep this code segment unrolled for performance reasons! + if (addrtofree > memarena->freelist.freerover->blkaddr) + { + if (addrtofree - memarena->freelist.freerover->blkaddr < memarena->freelist.head->prev->blkaddr - addrtofree) + { + ptrfree = memarena->freelist.freerover; // rover + ptrend = memarena->freelist.head->prev; // tail + clockwise = 1; + } + else + { + ptrfree = memarena->freelist.head->prev->prev; // tail + ptrend = memarena->freelist.freerover->prev; // rover + clockwise = 0; + } + } + else + { + if (addrtofree - memarena->freelist.head->blkaddr < memarena->freelist.freerover->blkaddr - addrtofree) + { + ptrfree = memarena->freelist.head; // head + ptrend = memarena->freelist.freerover; // rover + clockwise = 1; + } + else + { + ptrfree = memarena->freelist.freerover->prev; // rover + ptrend = memarena->freelist.head->prev; // head + clockwise = 0; + } + } + + // traverse the nodes + do + { + if ((addrtofree >= ptrfree->blkaddr + ptrfree->blksize) && + (addrtofree + memdesc->size <= ptrfree->next->blkaddr)) + { + if (addrtofree == ptrfree->blkaddr + ptrfree->blksize) + { + memblk_t *next; + + ptrfree->blksize += memdesc->size; + next = ptrfree->next; + + if (ptrfree->blkaddr + ptrfree->blksize == next->blkaddr) + { + ptrfree->blksize += next->blksize; + ptrfree->next = next->next; + next->next->prev = ptrfree; + + if (next == memarena->freelist.allocrover) + { + memarena->freelist.allocrover = ptrfree; + } + + kgsl_memarena_releasememblknode(memarena, next); + } + + mallocfreeblk = 0; + } + else if (addrtofree + memdesc->size == ptrfree->next->blkaddr) + { + ptrfree->next->blkaddr = addrtofree; + ptrfree->next->blksize += memdesc->size; + + mallocfreeblk = 0; + } + + break; + } + + if (clockwise) + { + ptrfree = ptrfree->next; + } + else + { + ptrfree = ptrfree->prev; + } + + } while (ptrfree != ptrend); + } + + // this free block could not be coalesced, so create a new free block + // and add it to the free list in the memory arena + if (mallocfreeblk) + { + p = kgsl_memarena_getmemblknode(memarena); + p->blkaddr = addrtofree; + p->blksize = memdesc->size; + + p->next = ptrfree->next; + p->prev = ptrfree; + ptrfree->next->prev = p; + ptrfree->next = p; + + if (p->blkaddr < memarena->freelist.head->blkaddr) + { + memarena->freelist.head = p; + } + + memarena->freelist.freerover = p; + } + else + { + memarena->freelist.freerover = ptrfree; + } + + GSL_MEMARENA_UNLOCK(); + + GSL_MEMARENA_STATS( + { + int i = 0; + while (memdesc->size >> (GSL_PAGESIZE_SHIFT + i)) + { + i++; + } + i = i > (GSL_MEMARENA_PAGE_DIST_MAX-1) ? (GSL_MEMARENA_PAGE_DIST_MAX-1) : i; + memarena->stats.frees_pagedistribution[i]++; + }); + + GSL_MEMARENA_STATS(memarena->stats.frees++); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_free.\n" ); +} + +//---------------------------------------------------------------------------- + +void * +kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr) +{ + // + // get the host mapped address for a hardware device address + // + + void *hostptr = NULL; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> void* kgsl_memarena_gethostptr(gsl_memarena_t *memarena=0x%08x, gpuaddr_t gpuaddr=0x%08x)\n", memarena, gpuaddr ); + + KOS_ASSERT(memarena); + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", NULL ); + return (NULL); + } + + // check address range + KOS_ASSERT(gpuaddr >= memarena->gpubaseaddr); + KOS_ASSERT(gpuaddr < memarena->gpubaseaddr + memarena->sizebytes); + + hostptr = (void *)((gpuaddr - memarena->gpubaseaddr) + memarena->hostbaseaddr); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_gethostptr. Return value: 0x%08x\n", hostptr ); + + return (hostptr); +} + +//---------------------------------------------------------------------------- + +gpuaddr_t +kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr) +{ + // + // get the hardware device address for a host mapped address + // + + gpuaddr_t gpuaddr = 0; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena=0x%08x, void *hostptr=0x%08x)\n", memarena, hostptr ); + + KOS_ASSERT(memarena); + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", 0 ); + return (0); + } + + // check address range + KOS_ASSERT(hostptr >= (void *)memarena->hostbaseaddr); + KOS_ASSERT(hostptr < (void *)(memarena->hostbaseaddr + memarena->sizebytes)); + + gpuaddr = ((unsigned int)hostptr - memarena->hostbaseaddr) + memarena->gpubaseaddr; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getgpuaddr. Return value: 0x%08x\n", gpuaddr ); + + return (gpuaddr); +} + +//---------------------------------------------------------------------------- + +unsigned int +kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags) +{ + memblk_t *ptrfree; + unsigned int blocksize, largestblocksize = 0; + int alignmentshift; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> unsigned int kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena=0x%08x, gsl_flags_t flags=0x%08x)\n", memarena, flags ); + + KOS_ASSERT(memarena); + if (GSL_MEMARENA_GET_SIGNATURE != GSL_MEMARENA_INSTANCE_SIGNATURE) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", 0 ); + return (0); + } + + // determine shift count for alignment requested + alignmentshift = gsl_memarena_alignmentshift(flags); + + GSL_MEMARENA_LOCK(); + + ptrfree = memarena->freelist.head; + + do + { + blocksize = ptrfree->blksize - (ptrfree->blkaddr - ((ptrfree->blkaddr >> alignmentshift) << alignmentshift)); + + if (blocksize > largestblocksize) + { + largestblocksize = blocksize; + } + + ptrfree = ptrfree->next; + + } while (ptrfree != memarena->freelist.head); + + GSL_MEMARENA_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_memarena_getlargestfreeblock. Return value: %d\n", largestblocksize ); + + return (largestblocksize); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_mmu.c b/drivers/mxc/amd-gpu/common/gsl_mmu.c new file mode 100644 index 000000000000..810a058a515d --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_mmu.c @@ -0,0 +1,1084 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// --------- +// pte debug +// --------- + +typedef struct _gsl_pte_debug_t +{ + unsigned int write :1; + unsigned int read :1; + unsigned int reserved :10; + unsigned int phyaddr :20; +} gsl_pte_debug_t; + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_PT_ENTRY_SIZEBYTES 4 +#define GSL_PT_EXTRA_ENTRIES 16 + +#define GSL_PT_PAGE_WRITE 0x00000001 +#define GSL_PT_PAGE_READ 0x00000002 + +#define GSL_PT_PAGE_AP_MASK 0x00000003 +#define GSL_PT_PAGE_ADDR_MASK ~(GSL_PAGESIZE-1) + +#define GSL_MMUFLAGS_TLBFLUSH 0x80000000 + +#define GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS (sizeof(unsigned char) * 8) + + +////////////////////////////////////////////////////////////////////////////// +// constants +////////////////////////////////////////////////////////////////////////////// +const unsigned int GSL_PT_PAGE_AP[4] = {(GSL_PT_PAGE_READ | GSL_PT_PAGE_WRITE), GSL_PT_PAGE_READ, GSL_PT_PAGE_WRITE, 0}; + + +///////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#ifdef GSL_LOCKING_FINEGRAIN +#define GSL_MMU_MUTEX_CREATE() mmu->mutex = kos_mutex_create("gsl_mmu"); \ + if (!mmu->mutex) {return (GSL_FAILURE);} +#define GSL_MMU_LOCK() kos_mutex_lock(mmu->mutex) +#define GSL_MMU_UNLOCK() kos_mutex_unlock(mmu->mutex) +#define GSL_MMU_MUTEX_FREE() kos_mutex_free(mmu->mutex); mmu->mutex = 0; +#else +#define GSL_MMU_MUTEX_CREATE() +#define GSL_MMU_LOCK() +#define GSL_MMU_UNLOCK() +#define GSL_MMU_MUTEX_FREE() +#endif + +#define GSL_PT_ENTRY_GET(va) ((va - pagetable->va_base) >> GSL_PAGESIZE_SHIFT) +#define GSL_PT_VIRT_GET(pte) (pagetable->va_base + (pte * GSL_PAGESIZE)) + +#define GSL_PT_MAP_APDEFAULT GSL_PT_PAGE_AP[0] + +#define GSL_PT_MAP_GET(pte) *((unsigned int *)(((unsigned int)pagetable->base.hostptr) + ((pte) * GSL_PT_ENTRY_SIZEBYTES))) +#define GSL_PT_MAP_GETADDR(pte) (GSL_PT_MAP_GET(pte) & GSL_PT_PAGE_ADDR_MASK) + +#define GSL_PT_MAP_DEBUG(pte) ((gsl_pte_debug_t*) &GSL_PT_MAP_GET(pte)) + +#define GSL_PT_MAP_SETBITS(pte, bits) (GSL_PT_MAP_GET(pte) |= (((unsigned int) bits) & GSL_PT_PAGE_AP_MASK)) +#define GSL_PT_MAP_SETADDR(pte, pageaddr) (GSL_PT_MAP_GET(pte) = (GSL_PT_MAP_GET(pte) & ~GSL_PT_PAGE_ADDR_MASK) | (((unsigned int) pageaddr) & GSL_PT_PAGE_ADDR_MASK)) + +#define GSL_PT_MAP_RESET(pte) (GSL_PT_MAP_GET(pte) = 0) +#define GSL_PT_MAP_RESETBITS(pte, bits) (GSL_PT_MAP_GET(pte) &= ~(((unsigned int) bits) & GSL_PT_PAGE_AP_MASK)) + +#define GSL_MMU_VIRT_TO_PAGE(va) *((unsigned int *)(pagetable->base.gpuaddr + (GSL_PT_ENTRY_GET(va) * GSL_PT_ENTRY_SIZEBYTES))) +#define GSL_MMU_VIRT_TO_PHYS(va) ((GSL_MMU_VIRT_TO_PAGE(va) & GSL_PT_PAGE_ADDR_MASK) + (va & (GSL_PAGESIZE-1))) + +#define GSL_TLBFLUSH_FILTER_GET(superpte) *((unsigned char *)(((unsigned int)mmu->tlbflushfilter.base) + (superpte / GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS))) +#define GSL_TLBFLUSH_FILTER_SETDIRTY(superpte) (GSL_TLBFLUSH_FILTER_GET((superpte)) |= 1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS)) +#define GSL_TLBFLUSH_FILTER_ISDIRTY(superpte) (GSL_TLBFLUSH_FILTER_GET((superpte)) & (1 << (superpte % GSL_TLBFLUSH_FILTER_ENTRY_NUMBITS))) +#define GSL_TLBFLUSH_FILTER_RESET() kos_memset(mmu->tlbflushfilter.base, 0, mmu->tlbflushfilter.size) + + +////////////////////////////////////////////////////////////////////////////// +// process index in pagetable object table +////////////////////////////////////////////////////////////////////////////// +OSINLINE int +kgsl_mmu_getprocessindex(unsigned int pid, int *pindex) +{ + int status = GSL_SUCCESS; +#ifdef GSL_MMU_PAGETABLE_PERPROCESS + if (kgsl_driver_getcallerprocessindex(pid, pindex) != GSL_SUCCESS) + { + status = GSL_FAILURE; + } +#else + (void) pid; // unreferenced formal parameter + *pindex = 0; +#endif // GSL_MMU_PAGETABLE_PERPROCESS + return (status); +} + +////////////////////////////////////////////////////////////////////////////// +// pagetable object for current caller process +////////////////////////////////////////////////////////////////////////////// +OSINLINE gsl_pagetable_t* +kgsl_mmu_getpagetableobject(gsl_mmu_t *mmu, unsigned int pid) +{ + int pindex = 0; + if (kgsl_mmu_getprocessindex(pid, &pindex) == GSL_SUCCESS) + { + return (mmu->pagetable[pindex]); + } + else + { + return (NULL); + } +} + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +void +kgsl_mh_intrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_mmu_t *mmu = (gsl_mmu_t *) cookie; + unsigned int devindex = mmu->device->id-1; // device_id is 1 based + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> void kgsl_mh_ntrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie ); + + // error condition interrupt + if (id == gsl_cfg_mh_intr[devindex].AXI_READ_ERROR || + id == gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR || + id == gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT) + { + printk(KERN_ERR "GPU: AXI Read/Write Error or MMU page fault\n"); + schedule_work(&mmu->device->irq_err_work); + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mh_intrcallback.\n" ); +} + +//---------------------------------------------------------------------------- + +#ifdef _DEBUG +static void +kgsl_mmu_debug(gsl_mmu_t *mmu, gsl_mmu_debug_t *regs) +{ + unsigned int devindex = mmu->device->id-1; // device_id is 1 based + + kos_memset(regs, 0, sizeof(gsl_mmu_debug_t)); + + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].CONFIG, ®s->config); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_BASE, ®s->mpu_base); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].MPU_END, ®s->mpu_end); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].VA_RANGE, ®s->va_range); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE, ®s->pt_base); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].PAGE_FAULT, ®s->page_fault); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, ®s->trans_error); + mmu->device->ftbl.device_regread(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, ®s->invalidate); +} +#endif + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable) +{ + unsigned int pte; + unsigned int data; + gsl_pte_debug_t *pte_debug; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_mmu_checkconsistency(gsl_pagetable_t *pagetable=0x%08x)\n", pagetable ); + + if (pagetable->last_superpte % GSL_PT_SUPER_PTE != 0) + { + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // go through page table and make sure there are no detectable errors + pte = 0; + while (pte < pagetable->max_entries) + { + pte_debug = GSL_PT_MAP_DEBUG(pte); + + if (GSL_PT_MAP_GETADDR(pte) != 0) + { + // pte is in use + + // access first couple bytes of a page + data = *((unsigned int *)GSL_PT_VIRT_GET(pte)); + } + + pte++; + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_checkconsistency. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu, unsigned int pid) +{ + gsl_deviceid_t tmp_id; + gsl_device_t *tmp_device; + int pindex; + gsl_pagetable_t *pagetable; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_destroypagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid ); + + if (kgsl_mmu_getprocessindex(pid, &pindex) != GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS ); + return (GSL_FAILURE); + } + + pagetable = mmu->pagetable[pindex]; + + // if pagetable object exists for current "current device mmu"/"current caller process" combination + if (pagetable) + { + // no more "device mmu"/"caller process" combinations attached to current pagetable object + if (pagetable->refcnt == 0) + { +#ifdef _DEBUG + // memory leak check + if (pagetable->last_superpte != 0 || GSL_PT_MAP_GETADDR(pagetable->last_superpte)) + { + /* many dumpx test cases forcefully exit, and thus trigger this assert. */ + /* Because it is an annoyance for HW guys, it is disabled for dumpx */ + if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX) + { + KOS_ASSERT(0); + return (GSL_FAILURE); + } + } +#endif // _DEBUG + + if (pagetable->base.gpuaddr) + { + kgsl_sharedmem_free0(&pagetable->base, GSL_CALLER_PROCESSID_GET()); + } + + kos_free(pagetable); + + // clear pagetable object reference for all "device mmu"/"current caller process" combinations + for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++) + { + tmp_device = &gsl_driver.device[tmp_id-1]; + + if (tmp_device->mmu.flags & GSL_FLAGS_STARTED) + { + tmp_device->mmu.pagetable[pindex] = NULL; + } + } + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_destroypagetableobject. Return value 0x%08x\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +gsl_pagetable_t* +kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu, unsigned int pid) +{ + // + // create pagetable object for "current device mmu"/"current caller + // process" combination. If none exists, setup a new pagetable object. + // + int status = GSL_SUCCESS; + gsl_pagetable_t *tmp_pagetable = NULL; + gsl_deviceid_t tmp_id; + gsl_device_t *tmp_device; + int pindex; + gsl_flags_t flags; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> gsl_pagetable_t* kgsl_mmu_createpagetableobject(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid ); + + status = kgsl_mmu_getprocessindex(pid, &pindex); + if (status != GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL ); + return (NULL); + } + // if pagetable object does not already exists for "current device mmu"/"current caller process" combination + if (!mmu->pagetable[pindex]) + { + // then, check if pagetable object already exists for any "other device mmu"/"current caller process" combination + for (tmp_id = GSL_DEVICE_ANY + 1; tmp_id <= GSL_DEVICE_MAX; tmp_id++) + { + tmp_device = &gsl_driver.device[tmp_id-1]; + + if (tmp_device->mmu.flags & GSL_FLAGS_STARTED) + { + if (tmp_device->mmu.pagetable[pindex]) + { + tmp_pagetable = tmp_device->mmu.pagetable[pindex]; + break; + } + } + } + + // pagetable object exists + if (tmp_pagetable) + { + KOS_ASSERT(tmp_pagetable->va_base == mmu->va_base); + KOS_ASSERT(tmp_pagetable->va_range == mmu->va_range); + + // set pagetable object reference + mmu->pagetable[pindex] = tmp_pagetable; + } + // create new pagetable object + else + { + mmu->pagetable[pindex] = (void *)kos_malloc(sizeof(gsl_pagetable_t)); + if (!mmu->pagetable[pindex]) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate pagetable object.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", NULL ); + return (NULL); + } + + kos_memset(mmu->pagetable[pindex], 0, sizeof(gsl_pagetable_t)); + + mmu->pagetable[pindex]->pid = pid; + mmu->pagetable[pindex]->refcnt = 0; + mmu->pagetable[pindex]->va_base = mmu->va_base; + mmu->pagetable[pindex]->va_range = mmu->va_range; + mmu->pagetable[pindex]->last_superpte = 0; + mmu->pagetable[pindex]->max_entries = (mmu->va_range >> GSL_PAGESIZE_SHIFT) + GSL_PT_EXTRA_ENTRIES; + + // allocate page table memory + flags = (GSL_MEMFLAGS_ALIGN4K | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST); + status = kgsl_sharedmem_alloc0(mmu->device->id, flags, mmu->pagetable[pindex]->max_entries * GSL_PT_ENTRY_SIZEBYTES, &mmu->pagetable[pindex]->base); + + if (status == GSL_SUCCESS) + { + // reset page table entries + kgsl_sharedmem_set0(&mmu->pagetable[pindex]->base, 0, 0, mmu->pagetable[pindex]->base.size); + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MMU_TBLADDR, mmu->pagetable[pindex]->base.gpuaddr, 0, mmu->pagetable[pindex]->base.size, "kgsl_mmu_init")); + } + else + { + kgsl_mmu_destroypagetableobject(mmu, pid); + } + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_createpagetableobject. Return value 0x%08x\n", mmu->pagetable[pindex] ); + + return (mmu->pagetable[pindex]); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid) +{ + // + // set device mmu to use current caller process's page table + // + int status = GSL_SUCCESS; + unsigned int devindex = device->id-1; // device_id is 1 based + gsl_mmu_t *mmu = &device->mmu; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> gsl_pagetable_t* kgsl_mmu_setpagetable(gsl_device_t *device=0x%08x)\n", device ); + + GSL_MMU_LOCK(); + + if (mmu->flags & GSL_FLAGS_STARTED) + { +#ifdef GSL_MMU_PAGETABLE_PERPROCESS + // page table not current, then setup mmu to use new specified page table + if (mmu->hwpagetable->pid != pid) + { + gsl_pagetable_t *pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if (pagetable) + { + mmu->hwpagetable = pagetable; + + // flag tlb flush + mmu->flags |= GSL_MMUFLAGS_TLBFLUSH; + + status = mmu->device->ftbl.mmu_setpagetable(mmu->device, gsl_cfg_mmu_reg[devindex].PT_BASE, pagetable->base.gpuaddr, pid); + + GSL_MMU_STATS(mmu->stats.pt.switches++); + } + else + { + status = GSL_FAILURE; + } + } +#endif // GSL_MMU_PAGETABLE_PERPROCESS + + // if needed, invalidate device specific tlb + if ((mmu->flags & GSL_MMUFLAGS_TLBFLUSH) && status == GSL_SUCCESS) + { + mmu->flags &= ~GSL_MMUFLAGS_TLBFLUSH; + + GSL_TLBFLUSH_FILTER_RESET(); + + status = mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[devindex].INVALIDATE, pid); + + GSL_MMU_STATS(mmu->stats.tlbflushes++); + } + } + + GSL_MMU_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_setpagetable. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_init(gsl_device_t *device) +{ + // + // intialize device mmu + // + // call this with the global lock held + // + int status; + gsl_flags_t flags; + gsl_pagetable_t *pagetable; + unsigned int devindex = device->id-1; // device_id is 1 based + gsl_mmu_t *mmu = &device->mmu; +#ifdef _DEBUG + gsl_mmu_debug_t regs; +#endif // _DEBUG + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_mmu_init(gsl_device_t *device=0x%08x)\n", device ); + + if (device->ftbl.mmu_tlbinvalidate == NULL || device->ftbl.mmu_setpagetable == NULL || + !(device->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + if (mmu->flags & GSL_FLAGS_INITIALIZED0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_INFO, "MMU already initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + // setup backward reference + mmu->device = device; + + // disable MMU when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + mmu->config = 0x00000000; + } + + // setup MMU and sub-client behavior + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, mmu->config); + + // enable axi interrupts + kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR, kgsl_mh_intrcallback, (void *) mmu); + kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR, kgsl_mh_intrcallback, (void *) mmu); + kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR); + kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR); + + mmu->refcnt = 0; + mmu->flags |= GSL_FLAGS_INITIALIZED0; + + // MMU enabled + if (mmu->config & 0x1) + { + // idle device + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + + // make sure aligned to pagesize + KOS_ASSERT((mmu->mpu_base & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0); + KOS_ASSERT(((mmu->mpu_base + mmu->mpu_range) & ((1 << GSL_PAGESIZE_SHIFT)-1)) == 0); + + // define physical memory range accessible by the core + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_BASE, mmu->mpu_base); + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].MPU_END, mmu->mpu_base + mmu->mpu_range); + + // enable page fault interrupt + kgsl_intr_attach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT, kgsl_mh_intrcallback, (void *) mmu); + kgsl_intr_enable(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT); + + mmu->flags |= GSL_FLAGS_INITIALIZED; + + // sub-client MMU lookups require address translation + if ((mmu->config & ~0x1) > 0) + { + GSL_MMU_MUTEX_CREATE(); + + // make sure virtual address range is a multiple of 64Kb + KOS_ASSERT((mmu->va_range & ((1 << 16)-1)) == 0); + + // setup pagetable object + pagetable = kgsl_mmu_createpagetableobject(mmu, GSL_CALLER_PROCESSID_GET()); + if (!pagetable) + { + kgsl_mmu_close(device); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + mmu->hwpagetable = pagetable; + + // create tlb flush filter to track dirty superPTE's -- one bit per superPTE + mmu->tlbflushfilter.size = (mmu->va_range / (GSL_PAGESIZE * GSL_PT_SUPER_PTE * 8)) + 1; + mmu->tlbflushfilter.base = (unsigned int *)kos_malloc(mmu->tlbflushfilter.size); + if (!mmu->tlbflushfilter.base) + { + kgsl_mmu_close(device); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_TLBFLUSH_FILTER_RESET(); + + // set page table base + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].PT_BASE, mmu->hwpagetable->base.gpuaddr); + + // define virtual address range + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].VA_RANGE, (mmu->hwpagetable->va_base | (mmu->hwpagetable->va_range >> 16))); + + // allocate memory used for completing r/w operations that cannot be mapped by the MMU + flags = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST); + status = kgsl_sharedmem_alloc0(device->id, flags, 32, &mmu->dummyspace); + if (status != GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate dummy space memory.\n" ); + kgsl_mmu_close(device); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", status ); + return (status); + } + + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].TRAN_ERROR, mmu->dummyspace.gpuaddr); + + // call device specific tlb invalidate + device->ftbl.mmu_tlbinvalidate(device, gsl_cfg_mmu_reg[devindex].INVALIDATE, mmu->hwpagetable->pid); + + GSL_MMU_STATS(mmu->stats.tlbflushes++); + + mmu->flags |= GSL_FLAGS_STARTED; + } + } + + KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_debug(&device->mmu, ®s)); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_init. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid) +{ + // + // map physical pages into the gpu page table + // + int status = GSL_SUCCESS; + unsigned int i, phyaddr, ap; + unsigned int pte, ptefirst, ptelast, superpte; + int flushtlb; + gsl_pagetable_t *pagetable; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_mmu_map(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, gsl_scatterlist_t *scatterlist=%M, gsl_flags_t flags=%d, unsigned int pid=%d)\n", + mmu, gpubaseaddr, scatterlist, flags, pid ); + + KOS_ASSERT(scatterlist); + + if (scatterlist->num <= 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: num pages is too small.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // get gpu access permissions + ap = GSL_PT_PAGE_AP[((flags & GSL_MEMFLAGS_GPUAP_MASK) >> GSL_MEMFLAGS_GPUAP_SHIFT)]; + + GSL_MMU_LOCK(); + + pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if (!pagetable) + { + GSL_MMU_UNLOCK(); + return (GSL_FAILURE); + } + + // check consistency, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable)); + + ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr); + ptelast = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (scatterlist->num-1))); + flushtlb = 0; + + if (!GSL_PT_MAP_GETADDR(ptefirst)) + { + // tlb needs to be flushed when the first and last pte are not at superpte boundaries + if ((ptefirst & (GSL_PT_SUPER_PTE-1)) != 0 || ((ptelast+1) & (GSL_PT_SUPER_PTE-1)) != 0) + { + flushtlb = 1; + } + + // create page table entries + for (pte = ptefirst; pte <= ptelast; pte++) + { + if (scatterlist->contiguous) + { + phyaddr = scatterlist->pages[0] + ((pte-ptefirst) * GSL_PAGESIZE); + } + else + { + phyaddr = scatterlist->pages[pte-ptefirst]; + } + + GSL_PT_MAP_SETADDR(pte, phyaddr); + GSL_PT_MAP_SETBITS(pte, ap); + + // tlb needs to be flushed when a dirty superPTE gets backed + if ((pte & (GSL_PT_SUPER_PTE-1)) == 0) + { + if (GSL_TLBFLUSH_FILTER_ISDIRTY(pte / GSL_PT_SUPER_PTE)) + { + flushtlb = 1; + } + } + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte , *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_map")); + } + + if (flushtlb) + { + // every device's tlb needs to be flushed because the current page table is shared among all devices + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + if (gsl_driver.device[i].flags & GSL_FLAGS_INITIALIZED) + { + gsl_driver.device[i].mmu.flags |= GSL_MMUFLAGS_TLBFLUSH; + } + } + } + + // determine new last mapped superPTE + superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1)); + if (superpte > pagetable->last_superpte) + { + pagetable->last_superpte = superpte; + } + + GSL_MMU_STATS(mmu->stats.pt.maps++); + } + else + { + // this should never happen + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" ); + KOS_ASSERT(0); + status = GSL_FAILURE; + } + + GSL_MMU_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_map. Return value %B\n", GSL_SUCCESS ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid) +{ + // + // remove mappings in the specified address range from the gpu page table + // + int status = GSL_SUCCESS; + gsl_pagetable_t *pagetable; + unsigned int numpages; + unsigned int pte, ptefirst, ptelast, superpte; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_mmu_unmap(gsl_mmu_t *mmu=0x%08x, gpuaddr_t gpubaseaddr=0x%08x, int range=%d, unsigned int pid=%d)\n", + mmu, gpubaseaddr, range, pid ); + + if (range <= 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + numpages = (range >> GSL_PAGESIZE_SHIFT); + if (range & (GSL_PAGESIZE-1)) + { + numpages++; + } + + GSL_MMU_LOCK(); + + pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if (!pagetable) + { + GSL_MMU_UNLOCK(); + return (GSL_FAILURE); + } + + // check consistency, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MMU, kgsl_mmu_checkconsistency(pagetable)); + + ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr); + ptelast = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1))); + + if (GSL_PT_MAP_GETADDR(ptefirst)) + { + superpte = ptefirst - (ptefirst & (GSL_PT_SUPER_PTE-1)); + GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE); + + // remove page table entries + for (pte = ptefirst; pte <= ptelast; pte++) + { + GSL_PT_MAP_RESET(pte); + + superpte = pte - (pte & (GSL_PT_SUPER_PTE-1)); + if (pte == superpte) + { + GSL_TLBFLUSH_FILTER_SETDIRTY(superpte / GSL_PT_SUPER_PTE); + } + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_SET_MMUTBL, pte, *(unsigned int*)(((char*)pagetable->base.hostptr) + (pte * GSL_PT_ENTRY_SIZEBYTES)), 0, "kgsl_mmu_unmap, reset superPTE")); + } + + // determine new last mapped superPTE + superpte = ptelast - (ptelast & (GSL_PT_SUPER_PTE-1)); + if (superpte == pagetable->last_superpte && pagetable->last_superpte >= GSL_PT_SUPER_PTE) + { + do + { + pagetable->last_superpte -= GSL_PT_SUPER_PTE; + } while (!GSL_PT_MAP_GETADDR(pagetable->last_superpte) && pagetable->last_superpte >= GSL_PT_SUPER_PTE); + } + + GSL_MMU_STATS(mmu->stats.pt.unmaps++); + } + else + { + // this should never happen + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_FATAL, "FATAL: This should never happen.\n" ); + KOS_ASSERT(0); + status = GSL_FAILURE; + } + + // invalidate tlb, debug only + KGSL_DEBUG(GSL_DBGFLAGS_MMU, mmu->device->ftbl.mmu_tlbinvalidate(mmu->device, gsl_cfg_mmu_reg[mmu->device->id-1].INVALIDATE, pagetable->pid)); + + GSL_MMU_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_unmap. Return value %B\n", GSL_SUCCESS ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid) +{ + // + // obtain scatter list of physical pages for the given gpu address range. + // if all pages are physically contiguous they are coalesced into a single + // scatterlist entry. + // + gsl_pagetable_t *pagetable; + unsigned int numpages; + unsigned int pte, ptefirst, ptelast; + unsigned int contiguous = 1; + + numpages = (range >> GSL_PAGESIZE_SHIFT); + if (range & (GSL_PAGESIZE-1)) + { + numpages++; + } + + if (range <= 0 || scatterlist->num != numpages) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Range is too small.\n" ); + KOS_ASSERT(0); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_getmap. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_MMU_LOCK(); + + pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if (!pagetable) + { + GSL_MMU_UNLOCK(); + return (GSL_FAILURE); + } + + ptefirst = GSL_PT_ENTRY_GET(gpubaseaddr); + ptelast = GSL_PT_ENTRY_GET(gpubaseaddr + (GSL_PAGESIZE * (numpages-1))); + + // determine whether pages are physically contiguous + if (numpages > 1) + { + for (pte = ptefirst; pte <= ptelast-1; pte++) + { + if (GSL_PT_MAP_GETADDR(pte) + GSL_PAGESIZE != GSL_PT_MAP_GETADDR(pte+1)) + { + contiguous = 0; + break; + } + } + } + + if (!contiguous) + { + // populate scatter list + for (pte = ptefirst; pte <= ptelast; pte++) + { + scatterlist->pages[pte-ptefirst] = GSL_PT_MAP_GETADDR(pte); + } + } + else + { + // coalesce physically contiguous pages into a single scatter list entry + scatterlist->pages[0] = GSL_PT_MAP_GETADDR(ptefirst); + } + + GSL_MMU_UNLOCK(); + + scatterlist->contiguous = contiguous; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_close(gsl_device_t *device) +{ + // + // close device mmu + // + // call this with the global lock held + // + gsl_mmu_t *mmu = &device->mmu; + unsigned int devindex = mmu->device->id-1; // device_id is 1 based +#ifdef _DEBUG + int i; +#endif // _DEBUG + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_close(gsl_device_t *device=0x%08x)\n", device ); + + if (mmu->flags & GSL_FLAGS_INITIALIZED0) + { + if (mmu->flags & GSL_FLAGS_STARTED) + { + // terminate pagetable object + kgsl_mmu_destroypagetableobject(mmu, GSL_CALLER_PROCESSID_GET()); + } + + // no more processes attached to current device mmu + if (mmu->refcnt == 0) + { +#ifdef _DEBUG + // check if there are any orphaned pagetable objects lingering around + for (i = 0; i < GSL_MMU_PAGETABLE_MAX; i++) + { + if (mmu->pagetable[i]) + { + /* many dumpx test cases forcefully exit, and thus trigger this assert. */ + /* Because it is an annoyance for HW guys, it is disabled for dumpx */ + if(!gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX) + { + KOS_ASSERT(0); + return (GSL_FAILURE); + } + } + } +#endif // _DEBUG + + // disable mh interrupts + kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_READ_ERROR); + kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].AXI_WRITE_ERROR); + kgsl_intr_detach(&device->intr, gsl_cfg_mh_intr[devindex].MMU_PAGE_FAULT); + + // disable MMU + device->ftbl.device_regwrite(device, gsl_cfg_mmu_reg[devindex].CONFIG, 0x00000000); + + if (mmu->tlbflushfilter.base) + { + kos_free(mmu->tlbflushfilter.base); + } + + if (mmu->dummyspace.gpuaddr) + { + kgsl_sharedmem_free0(&mmu->dummyspace, GSL_CALLER_PROCESSID_GET()); + } + + GSL_MMU_MUTEX_FREE(); + + mmu->flags &= ~GSL_FLAGS_STARTED; + mmu->flags &= ~GSL_FLAGS_INITIALIZED; + mmu->flags &= ~GSL_FLAGS_INITIALIZED0; + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_close. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid) +{ + // + // attach process + // + // call this with the global lock held + // + int status = GSL_SUCCESS; + gsl_pagetable_t *pagetable; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_attachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid ); + + GSL_MMU_LOCK(); + + if (mmu->flags & GSL_FLAGS_INITIALIZED0) + { + // attach to current device mmu + mmu->refcnt++; + + if (mmu->flags & GSL_FLAGS_STARTED) + { + // attach to pagetable object + pagetable = kgsl_mmu_createpagetableobject(mmu, pid); + if(pagetable) + { + pagetable->refcnt++; + } + else + { + status = GSL_FAILURE; + } + } + } + + GSL_MMU_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_attachcallback. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid) +{ + // + // detach process + // + int status = GSL_SUCCESS; + gsl_pagetable_t *pagetable; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_mmu_detachcallback(gsl_mmu_t *mmu=0x%08x, unsigned int pid=0x%08x)\n", mmu, pid ); + + GSL_MMU_LOCK(); + + if (mmu->flags & GSL_FLAGS_INITIALIZED0) + { + // detach from current device mmu + mmu->refcnt--; + + if (mmu->flags & GSL_FLAGS_STARTED) + { + // detach from pagetable object + pagetable = kgsl_mmu_getpagetableobject(mmu, pid); + if(pagetable) + { + pagetable->refcnt--; + } + else + { + status = GSL_FAILURE; + } + } + } + + GSL_MMU_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_mmu_detachcallback. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats) +{ +#ifdef GSL_STATS_MMU + int status = GSL_SUCCESS; + + KOS_ASSERT(stats); + + GSL_MMU_LOCK(); + + if (mmu->flags & GSL_FLAGS_STARTED) + { + kos_memcpy(stats, &mmu->stats, sizeof(gsl_mmustats_t)); + } + else + { + kos_memset(stats, 0, sizeof(gsl_mmustats_t)); + } + + GSL_MMU_UNLOCK(); + + return (status); +#else + // unreferenced formal parameters + (void) mmu; + (void) stats; + + return (GSL_FAILURE_NOTSUPPORTED); +#endif // GSL_STATS_MMU +} + +//---------------------------------------------------------------------------- + +int +kgsl_mmu_bist(gsl_mmu_t *mmu) +{ + // unreferenced formal parameter + (void) mmu; + + return (GSL_SUCCESS); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c new file mode 100644 index 000000000000..76c6c701f126 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_ringbuffer.c @@ -0,0 +1,1169 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#include "gsl_cmdstream.h" + +#ifdef GSL_BLD_YAMATO + +////////////////////////////////////////////////////////////////////////////// +// ucode +////////////////////////////////////////////////////////////////////////////// +#define uint32 unsigned int + +#include "pm4_microcode.inl" +#include "pfp_microcode_nrt.inl" + +#undef uint32 + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_RB_NOP_SIZEDWORDS 2 // default is 2 +#define GSL_RB_PROTECTED_MODE_CONTROL 0x00000000 // protected mode error checking below register address 0x800 + // note: if CP_INTERRUPT packet is used then checking needs + // to change to below register address 0x7C8 + + +////////////////////////////////////////////////////////////////////////////// +// ringbuffer size log2 quadwords equivalent +////////////////////////////////////////////////////////////////////////////// +OSINLINE unsigned int +gsl_ringbuffer_sizelog2quadwords(unsigned int sizedwords) +{ + unsigned int sizelog2quadwords = 0; + int i = sizedwords >> 1; + while (i >>= 1) + { + sizelog2quadwords++; + } + return (sizelog2quadwords); +} + + +////////////////////////////////////////////////////////////////////////////// +// private prototypes +////////////////////////////////////////////////////////////////////////////// +#ifdef _DEBUG +static void kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug); +#endif + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +void +kgsl_cp_intrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_ringbuffer_t *rb = (gsl_ringbuffer_t *) cookie; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> void kgsl_cp_intrcallback(gsl_intrid_t id=%I, void *cookie=0x%08x)\n", id, cookie ); + + switch(id) + { + // error condition interrupt + case GSL_INTR_YDX_CP_T0_PACKET_IN_IB: + case GSL_INTR_YDX_CP_OPCODE_ERROR: + case GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR: + case GSL_INTR_YDX_CP_RESERVED_BIT_ERROR: + case GSL_INTR_YDX_CP_IB_ERROR: + printk(KERN_ERR "GPU: CP Error\n"); + schedule_work(&rb->device->irq_err_work); + break; + + // non-error condition interrupt + case GSL_INTR_YDX_CP_SW_INT: + case GSL_INTR_YDX_CP_IB2_INT: + case GSL_INTR_YDX_CP_IB1_INT: + case GSL_INTR_YDX_CP_RING_BUFFER: + + // signal intr completion event + kos_event_signal(rb->device->intr.evnt[id]); + break; + + default: + + break; + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_cp_intrcallback.\n" ); +} + +//---------------------------------------------------------------------------- + +void +kgsl_ringbuffer_watchdog() +{ + gsl_ringbuffer_t *rb = &(gsl_driver.device[GSL_DEVICE_YAMATO-1]).ringbuffer; // device_id is 1 based + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> void kgsl_ringbuffer_watchdog()\n" ); + + if (rb->flags & GSL_FLAGS_STARTED) + { + GSL_RB_MUTEX_LOCK(); + + GSL_RB_GET_READPTR(rb, &rb->rptr); + + // ringbuffer is currently not empty + if (rb->rptr != rb->wptr) + { + // and a rptr sample was taken during interval n-1 + if (rb->watchdog.flags & GSL_FLAGS_ACTIVE) + { + // and the rptr did not advance between interval n-1 and n + if (rb->rptr == rb->watchdog.rptr_sample) + { + // then the core has hung + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_FATAL, + "ERROR: Watchdog detected core hung.\n" ); + + rb->device->ftbl.device_destroy(rb->device); + return; + } + } + + // save rptr sample for interval n + rb->watchdog.flags |= GSL_FLAGS_ACTIVE; + rb->watchdog.rptr_sample = rb->rptr; + } + else + { + // clear rptr sample for interval n + rb->watchdog.flags &= ~GSL_FLAGS_ACTIVE; + } + + GSL_RB_MUTEX_UNLOCK(); + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_watchdog.\n" ); +} + +//---------------------------------------------------------------------------- + +#ifdef _DEBUG + +OSINLINE void +kgsl_ringbuffer_checkregister(unsigned int reg, int pmodecheck) +{ + if (pmodecheck) + { + // check for register protection mode violation + if (reg <= (GSL_RB_PROTECTED_MODE_CONTROL & 0x3FFF)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register protection mode violation.\n" ); + KOS_ASSERT(0); + } + } + + // range check register offset + if (reg > (gsl_driver.device[GSL_DEVICE_YAMATO-1].regspace.sizebytes >> 2)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Register out of range.\n" ); + KOS_ASSERT(0); + } +} + +//---------------------------------------------------------------------------- + +void +kgsl_ringbuffer_checkpm4type0(unsigned int header, unsigned int** cmds, int pmodeoff) +{ + pm4_type0 pm4header = *((pm4_type0*) &header); + unsigned int reg; + + if (pm4header.one_reg_wr) + { + reg = pm4header.base_index; + } + else + { + reg = pm4header.base_index + pm4header.count; + } + + kgsl_ringbuffer_checkregister(reg, !pmodeoff); + + *cmds += pm4header.count + 1; +} + +//---------------------------------------------------------------------------- + +void +kgsl_ringbuffer_checkpm4type3(unsigned int header, unsigned int** cmds, int indirection, int pmodeoff) +{ + pm4_type3 pm4header = *((pm4_type3*) &header); + unsigned int *ordinal2 = *cmds; + unsigned int *ibcmds, *end; + unsigned int reg, length; + + // check indirect buffer level + if (indirection > 2) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Only two levels of indirection supported.\n" ); + KOS_ASSERT(0); + } + + switch(pm4header.it_opcode) + { + case PM4_INDIRECT_BUFFER: + case PM4_INDIRECT_BUFFER_PFD: + + // determine ib host base and end address + ibcmds = (unsigned int*) kgsl_sharedmem_convertaddr(*ordinal2, 0); + end = ibcmds + *(ordinal2 + 1); + + // walk through the ib + while(ibcmds < end) + { + unsigned int tmpheader = *(ibcmds++); + + switch(tmpheader & PM4_PKT_MASK) + { + case PM4_TYPE0_PKT: + kgsl_ringbuffer_checkpm4type0(tmpheader, &ibcmds, pmodeoff); + break; + + case PM4_TYPE1_PKT: + case PM4_TYPE2_PKT: + break; + + case PM4_TYPE3_PKT: + kgsl_ringbuffer_checkpm4type3(tmpheader, &ibcmds, (indirection + 1), pmodeoff); + break; + } + } + break; + + case PM4_ME_INIT: + + if(indirection != 0) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: ME INIT packet cannot reside in an ib.\n" ); + KOS_ASSERT(0); + } + break; + + case PM4_REG_RMW: + + reg = (*ordinal2) & 0x1FFF; + + kgsl_ringbuffer_checkregister(reg, !pmodeoff); + + break; + + case PM4_SET_CONSTANT: + + if((((*ordinal2) >> 16) & 0xFF) == 0x4) // incremental register update + { + reg = 0x2000 + ((*ordinal2) & 0x3FF); // gfx decode space address starts at 0x2000 + length = pm4header.count - 1; + + kgsl_ringbuffer_checkregister(reg + length, 0); + } + break; + + case PM4_LOAD_CONSTANT_CONTEXT: + + if(((*(ordinal2 + 1) >> 16) & 0xFF) == 0x4) // incremental register update + { + reg = 0x2000 + (*(ordinal2 + 1) & 0x3FF); // gfx decode space address starts at 0x2000 + length = *(ordinal2 + 2); + + kgsl_ringbuffer_checkregister(reg + length, 0); + } + break; + + case PM4_COND_WRITE: + + if(((*ordinal2) & 0x00000100) == 0x0) // write to register + { + reg = *(ordinal2 + 4) & 0x3FFF; + + kgsl_ringbuffer_checkregister(reg, !pmodeoff); + } + break; + } + + *cmds += pm4header.count + 1; +} + +//---------------------------------------------------------------------------- + +void +kgsl_ringbuffer_checkpm4(unsigned int* cmds, unsigned int sizedwords, int pmodeoff) +{ + unsigned int *ringcmds = cmds; + unsigned int *end = cmds + sizedwords; + + while(ringcmds < end) + { + unsigned int header = *(ringcmds++); + + switch(header & PM4_PKT_MASK) + { + case PM4_TYPE0_PKT: + kgsl_ringbuffer_checkpm4type0(header, &ringcmds, pmodeoff); + break; + + case PM4_TYPE1_PKT: + case PM4_TYPE2_PKT: + break; + + case PM4_TYPE3_PKT: + kgsl_ringbuffer_checkpm4type3(header, &ringcmds, 0, pmodeoff); + break; + } + } +} + +#endif // _DEBUG + +//---------------------------------------------------------------------------- + +static void +kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb) +{ + unsigned int value; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static void kgsl_ringbuffer_submit(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + KOS_ASSERT(rb->wptr != 0); + + kgsl_device_active(rb->device); + + GSL_RB_UPDATE_WPTR_POLLING(rb); + + // send the wptr to the hw + rb->device->ftbl.device_regwrite(rb->device, mmCP_RB_WPTR, rb->wptr); + + // force wptr register to be updated + do + { + rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR, &value); + } while (value != rb->wptr); + + rb->flags |= GSL_FLAGS_ACTIVE; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_submit.\n" ); +} + +//---------------------------------------------------------------------------- + +static int +kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb, unsigned int numcmds, int wptr_ahead) +{ + int nopcount; + unsigned int freecmds; + unsigned int *cmds; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static int kgsl_ringbuffer_waitspace(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d, int wptr_ahead=%d)\n", + rb, numcmds, wptr_ahead ); + + + // if wptr ahead, fill the remaining with NOPs + if (wptr_ahead) + { + nopcount = rb->sizedwords - rb->wptr - 1; // -1 for header + + cmds = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr; + GSL_RB_WRITE(cmds, pm4_nop_packet(nopcount)); + rb->wptr++; + + kgsl_ringbuffer_submit(rb); + + rb->wptr = 0; + + GSL_RB_STATS(rb->stats.wraps++); + } + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RBWAIT, GSL_DEVICE_YAMATO, rb->wptr, numcmds, "kgsl_ringbuffer_waitspace")); + + // wait for space in ringbuffer + for( ; ; ) + { + GSL_RB_GET_READPTR(rb, &rb->rptr); + + freecmds = rb->rptr - rb->wptr; + + if ((freecmds == 0) || (freecmds > numcmds)) + { + break; + } + + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static unsigned int * +kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb, unsigned int numcmds) +{ + unsigned int *ptr; + int status = GSL_SUCCESS; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static unsigned int* kgsl_ringbuffer_addcmds(gsl_ringbuffer_t *rb=0x%08x, unsigned int numcmds=%d)\n", + rb, numcmds ); + + KOS_ASSERT(numcmds < rb->sizedwords); + + // update host copy of read pointer when running in safe mode + if (rb->device->flags & GSL_FLAGS_SAFEMODE) + { + GSL_RB_GET_READPTR(rb, &rb->rptr); + } + + // check for available space + if (rb->wptr >= rb->rptr) + { + // wptr ahead or equal to rptr + if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS)) // reserve dwords for nop packet + { + status = kgsl_ringbuffer_waitspace(rb, numcmds, 1); + } + } + else + { + // wptr behind rptr + if ((rb->wptr + numcmds) >= rb->rptr) + { + status = kgsl_ringbuffer_waitspace(rb, numcmds, 0); + } + + // check for remaining space + if ((rb->wptr + numcmds) > (rb->sizedwords - GSL_RB_NOP_SIZEDWORDS)) // reserve dwords for nop packet + { + status = kgsl_ringbuffer_waitspace(rb, numcmds, 1); + } + } + + ptr = (unsigned int *)rb->buffer_desc.hostptr + rb->wptr; + rb->wptr += numcmds; + + if (status == GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", ptr ); + return (ptr); + } + else + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_waitspace. Return value 0x%08x\n", NULL ); + return (NULL); + } +} + +//---------------------------------------------------------------------------- +int +kgsl_ringbuffer_start(gsl_ringbuffer_t *rb) +{ + int status; + cp_rb_cntl_u cp_rb_cntl; + int i; + unsigned int *cmds; + gsl_device_t *device = rb->device; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static int kgsl_ringbuffer_start(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + if (rb->flags & GSL_FLAGS_STARTED) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + // clear memptrs values + kgsl_sharedmem_set0(&rb->memptrs_desc, 0, 0, sizeof(gsl_rbmemptrs_t)); + + // clear ringbuffer + kgsl_sharedmem_set0(&rb->buffer_desc, 0, 0x12341234, (rb->sizedwords << 2)); + + // setup WPTR polling address + device->ftbl.device_regwrite(device, mmCP_RB_WPTR_BASE, (rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_WPTRPOLL_OFFSET)); + + // setup WPTR delay + device->ftbl.device_regwrite(device, mmCP_RB_WPTR_DELAY, 0/*0x70000010*/); + + // setup RB_CNTL + device->ftbl.device_regread(device, mmCP_RB_CNTL, (unsigned int *)&cp_rb_cntl); + + cp_rb_cntl.f.rb_bufsz = gsl_ringbuffer_sizelog2quadwords(rb->sizedwords); // size of ringbuffer + cp_rb_cntl.f.rb_blksz = rb->blksizequadwords; // quadwords to read before updating mem RPTR + cp_rb_cntl.f.rb_poll_en = GSL_RB_CNTL_POLL_EN; // WPTR polling + cp_rb_cntl.f.rb_no_update = GSL_RB_CNTL_NO_UPDATE; // mem RPTR writebacks + + device->ftbl.device_regwrite(device, mmCP_RB_CNTL, cp_rb_cntl.val); + + // setup RB_BASE + device->ftbl.device_regwrite(device, mmCP_RB_BASE, rb->buffer_desc.gpuaddr); + + // setup RPTR_ADDR + device->ftbl.device_regwrite(device, mmCP_RB_RPTR_ADDR, rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_RPTR_OFFSET); + + // explicitly clear all cp interrupts when running in safe mode + if (rb->device->flags & GSL_FLAGS_SAFEMODE) + { + device->ftbl.device_regwrite(device, mmCP_INT_ACK, 0xFFFFFFFF); + } + + // setup scratch/timestamp addr + device->ftbl.device_regwrite(device, mmSCRATCH_ADDR, device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp)); + + // setup scratch/timestamp mask + device->ftbl.device_regwrite(device, mmSCRATCH_UMSK, GSL_RB_MEMPTRS_SCRATCH_MASK); + + // load the CP ucode + device->ftbl.device_regwrite(device, mmCP_DEBUG, 0x02000000); + device->ftbl.device_regwrite(device, mmCP_ME_RAM_WADDR, 0); + + for (i = 0; i < PM4_MICROCODE_SIZE; i++ ) + { + device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][0]); + device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][1]); + device->ftbl.device_regwrite(device, mmCP_ME_RAM_DATA, aPM4_Microcode[i][2]); + } + + // load the prefetch parser ucode + device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_ADDR, 0); + + for ( i = 0; i < PFP_MICROCODE_SIZE_NRT; i++ ) + { + device->ftbl.device_regwrite(device, mmCP_PFP_UCODE_DATA, aPFP_Microcode_nrt[i]); + } + + // queue thresholds ??? + device->ftbl.device_regwrite(device, mmCP_QUEUE_THRESHOLDS, 0x000C0804); + + // reset pointers + rb->rptr = 0; + rb->wptr = 0; + + // init timestamp + rb->timestamp = 0; + GSL_RB_INIT_TIMESTAMP(rb); + + // clear ME_HALT to start micro engine + device->ftbl.device_regwrite(device, mmCP_ME_CNTL, 0); + + // ME_INIT + cmds = kgsl_ringbuffer_addcmds(rb, 19); + + GSL_RB_WRITE(cmds, PM4_HDR_ME_INIT); + GSL_RB_WRITE(cmds, 0x000003ff); // All fields present (bits 9:0) + GSL_RB_WRITE(cmds, 0x00000000); // Disable/Enable Real-Time Stream processing (present but ignored) + GSL_RB_WRITE(cmds, 0x00000000); // Enable (2D to 3D) and (3D to 2D) implicit synchronization (present but ignored) + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_SURFACE_INFO)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_WINDOW_OFFSET)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmVGT_MAX_VTX_INDX)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmSQ_PROGRAM_CNTL)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmRB_DEPTHCONTROL)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POINT_SIZE)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SC_LINE_CNTL)); + GSL_RB_WRITE(cmds, GSL_HAL_SUBBLOCK_OFFSET(mmPA_SU_POLY_OFFSET_FRONT_SCALE)); + GSL_RB_WRITE(cmds, 0x80000180); // Vertex and Pixel Shader Start Addresses in instructions (3 DWORDS per instruction) + GSL_RB_WRITE(cmds, 0x00000001); // Maximum Contexts + GSL_RB_WRITE(cmds, 0x00000000); // Write Confirm Interval and The CP will wait the wait_interval * 16 clocks between polling + GSL_RB_WRITE(cmds, 0x00000000); // NQ and External Memory Swap + GSL_RB_WRITE(cmds, GSL_RB_PROTECTED_MODE_CONTROL); // Protected mode error checking + GSL_RB_WRITE(cmds, 0x00000000); // Disable header dumping and Header dump address + GSL_RB_WRITE(cmds, 0x00000000); // Header dump size + + KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4((unsigned int *)rb->buffer_desc.hostptr, 19, 1)); + KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4((unsigned int *)rb->buffer_desc.hostptr, 19)); + + kgsl_ringbuffer_submit(rb); + + // idle device to validate ME INIT + status = device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + + if (status == GSL_SUCCESS) + { + rb->flags |= GSL_FLAGS_STARTED; + } + + // enable cp interrupts + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_SW_INT, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB_ERROR, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB2_INT, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_IB1_INT, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_cp_intrcallback, (void *) rb); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_SW_INT); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB2_INT); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_IB1_INT); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_start. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb) +{ + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> static int kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + if (rb->flags & GSL_FLAGS_STARTED) + { + // disable cp interrupts + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_SW_INT); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_T0_PACKET_IN_IB); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_OPCODE_ERROR); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RESERVED_BIT_ERROR); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB_ERROR); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB2_INT); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_IB1_INT); + kgsl_intr_detach(&rb->device->intr, GSL_INTR_YDX_CP_RING_BUFFER); + + // ME_HALT + rb->device->ftbl.device_regwrite(rb->device, mmCP_ME_CNTL, 0x10000000); + + rb->flags &= ~GSL_FLAGS_STARTED; + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_stop. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_init(gsl_device_t *device) +{ + int status; + gsl_flags_t flags; + gsl_ringbuffer_t *rb = &device->ringbuffer; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_ringbuffer_init(gsl_device_t *device=0x%08x)\n", device ); + + rb->device = device; + rb->sizedwords = (2 << gsl_cfg_rb_sizelog2quadwords); + rb->blksizequadwords = gsl_cfg_rb_blksizequadwords; + + GSL_RB_MUTEX_CREATE(); + + // allocate memory for ringbuffer, needs to be double octword aligned + // align on page from contiguous physical memory + flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_CONPHYS | GSL_MEMFLAGS_STRICTREQUEST); + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = (GSL_MEMFLAGS_ALIGNPAGE | GSL_MEMFLAGS_STRICTREQUEST)); /* set MMU table for ringbuffer */ + + status = kgsl_sharedmem_alloc0(device->id, flags, (rb->sizedwords << 2), &rb->buffer_desc); + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_SET, (unsigned int)rb->buffer_desc.gpuaddr, (unsigned int)rb->buffer_desc.hostptr, 0, "kgsl_ringbuffer_init")); + + if (status != GSL_SUCCESS) + { + kgsl_ringbuffer_close(rb); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status ); + return (status); + } + + // allocate memory for polling and timestamps + flags = (GSL_MEMFLAGS_ALIGN32 | GSL_MEMFLAGS_CONPHYS); + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, flags = GSL_MEMFLAGS_ALIGN32); + + status = kgsl_sharedmem_alloc0(device->id, flags, sizeof(gsl_rbmemptrs_t), &rb->memptrs_desc); + + if (status != GSL_SUCCESS) + { + kgsl_ringbuffer_close(rb); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status ); + return (status); + } + + // overlay structure on memptrs memory + rb->memptrs = (gsl_rbmemptrs_t *)rb->memptrs_desc.hostptr; + + rb->flags |= GSL_FLAGS_INITIALIZED; + + // validate command stream data when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + gsl_driver.flags_debug |= GSL_DBGFLAGS_PM4CHECK; + } + + // start ringbuffer + status = kgsl_ringbuffer_start(rb); + + if (status != GSL_SUCCESS) + { + kgsl_ringbuffer_close(rb); + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", status ); + return (status); + } + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_init. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_close(gsl_ringbuffer_t *rb) +{ + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_ringbuffer_close(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + GSL_RB_MUTEX_LOCK(); + + // stop ringbuffer + kgsl_ringbuffer_stop(rb); + + // free buffer + if (rb->buffer_desc.hostptr) + { + kgsl_sharedmem_free0(&rb->buffer_desc, GSL_CALLER_PROCESSID_GET()); + } + + // free memory pointers + if (rb->memptrs_desc.hostptr) + { + kgsl_sharedmem_free0(&rb->memptrs_desc, GSL_CALLER_PROCESSID_GET()); + } + + rb->flags &= ~GSL_FLAGS_INITIALIZED; + + GSL_RB_MUTEX_UNLOCK(); + + GSL_RB_MUTEX_FREE(); + + kos_memset(rb, 0, sizeof(gsl_ringbuffer_t)); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_close. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +gsl_timestamp_t +kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmds, int sizedwords, unsigned int pid) +{ + gsl_ringbuffer_t *rb = &device->ringbuffer; + unsigned int pmodesizedwords; + unsigned int *ringcmds; + unsigned int timestamp; + + pmodeoff = 0; + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> gsl_timestamp_t kgsl_ringbuffer_issuecmds(gsl_device_t *device=0x%08x, int pmodeoff=%d, unsigned int *cmds=0x%08x, int sizedwords=%d, unsigned int pid=0x%08x)\n", + device, pmodeoff, cmds, sizedwords, pid ); + + if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED)) + { + return (0); + } + + // set mmu pagetable + kgsl_mmu_setpagetable(device, pid); + + KGSL_DEBUG(GSL_DBGFLAGS_PM4CHECK, kgsl_ringbuffer_checkpm4(cmds, sizedwords, pmodeoff)); + KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPPM4(cmds, sizedwords)); + + // reserve space to temporarily turn off protected mode error checking if needed + pmodesizedwords = pmodeoff ? 8 : 0; + +#if defined GSL_RB_TIMESTAMP_INTERUPT + pmodesizedwords += 2; +#endif + // allocate space in ringbuffer + ringcmds = kgsl_ringbuffer_addcmds(rb, pmodesizedwords + sizedwords + 6); + + if (pmodeoff) + { + // disable protected mode error checking + *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2); + *ringcmds++ = 0x00000080; + *ringcmds++ = 0x00000000; + } + + // copy the cmds to the ringbuffer + kos_memcpy(ringcmds, cmds, (sizedwords << 2)); + + ringcmds += sizedwords; + + if (pmodeoff) + { + *ringcmds++ = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + *ringcmds++ = 0; + + // re-enable protected mode error checking + *ringcmds++ = pm4_type3_packet(PM4_ME_INIT, 2); + *ringcmds++ = 0x00000080; + *ringcmds++ = GSL_RB_PROTECTED_MODE_CONTROL; + } + + // increment timestamp + rb->timestamp++; + timestamp = rb->timestamp; + + // start-of-pipeline and end-of-pipeline timestamps + *ringcmds++ = pm4_type0_packet(mmCP_TIMESTAMP, 1); + *ringcmds++ = rb->timestamp; + *ringcmds++ = pm4_type3_packet(PM4_EVENT_WRITE, 3); + *ringcmds++ = CACHE_FLUSH_TS; + *ringcmds++ = device->memstore.gpuaddr + GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp); + *ringcmds++ = rb->timestamp; + +#if defined GSL_RB_TIMESTAMP_INTERUPT + *ringcmds++ = pm4_type3_packet(PM4_INTERRUPT, 1); + *ringcmds++ = 0x80000000; +#endif + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_MEMWRITE, (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (unsigned int)((char*)ringcmds - ((pmodesizedwords + sizedwords + 6) << 2)), (pmodesizedwords + sizedwords + 6) << 2, "kgsl_ringbuffer_issuecmds")); + + // issue the commands + kgsl_ringbuffer_submit(rb); + + // stats + GSL_RB_STATS(rb->stats.wordstotal += sizedwords); + GSL_RB_STATS(rb->stats.issues++); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issuecmds. Return value %d\n", timestamp ); + + // return timestamp of issued commands + return (timestamp); +} + +//---------------------------------------------------------------------------- +int +kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags) +{ + unsigned int link[3]; + int dumpx_swap; + (void)dumpx_swap; // used only when BB_DUMPX is defined + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> gsl_timestamp_t kgsl_ringbuffer_issueibcmds(gsl_device_t device=%0x%08x, int drawctxt_index=%d, gpuaddr_t ibaddr=0x%08x, int sizedwords=%d, gsl_timestamp_t *timestamp=0x%08x)\n", + device, drawctxt_index, ibaddr, sizedwords, timestamp ); + + if (!(device->ringbuffer.flags & GSL_FLAGS_STARTED)) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + KOS_ASSERT(ibaddr); + KOS_ASSERT(sizedwords); + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, dumpx_swap = kgsl_dumpx_parse_ibs(ibaddr, sizedwords)); + + GSL_RB_MUTEX_LOCK(); + + // context switch if needed + kgsl_drawctxt_switch(device, &device->drawctxt[drawctxt_index], flags); + + link[0] = PM4_HDR_INDIRECT_BUFFER_PFD; + link[1] = ibaddr; + link[2] = sizedwords; + + *timestamp = kgsl_ringbuffer_issuecmds(device, 0, &link[0], 3, GSL_CALLER_PROCESSID_GET()); + + GSL_RB_MUTEX_UNLOCK(); + + // idle device when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + } + else + { + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + // insert wait for idle after every IB1 + // this is conservative but works reliably and is ok even for performance simulations + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + }); + } + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + if(dumpx_swap) + { + KGSL_DEBUG_DUMPX( BB_DUMP_EXPORT_CBUF, 0, 0, 0, "resolve"); + KGSL_DEBUG_DUMPX( BB_DUMP_FLUSH,0,0,0," "); + } + }); + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_issueibcmds. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +#ifdef _DEBUG +static void +kgsl_ringbuffer_debug(gsl_ringbuffer_t *rb, gsl_rb_debug_t *rb_debug) +{ + kos_memset(rb_debug, 0, sizeof(gsl_rb_debug_t)); + + rb_debug->pm4_ucode_rel = PM4_MICROCODE_VERSION; + rb_debug->pfp_ucode_rel = PFP_MICROCODE_VERSION; + + rb->device->ftbl.device_regread(rb->device, mmCP_RB_BASE, (unsigned int *)&rb_debug->cp_rb_base); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_CNTL, (unsigned int *)&rb_debug->cp_rb_cntl); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR_ADDR, (unsigned int *)&rb_debug->cp_rb_rptr_addr); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_RPTR, (unsigned int *)&rb_debug->cp_rb_rptr); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR, (unsigned int *)&rb_debug->cp_rb_wptr); + rb->device->ftbl.device_regread(rb->device, mmCP_RB_WPTR_BASE, (unsigned int *)&rb_debug->cp_rb_wptr_base); + rb->device->ftbl.device_regread(rb->device, mmSCRATCH_UMSK, (unsigned int *)&rb_debug->scratch_umsk); + rb->device->ftbl.device_regread(rb->device, mmSCRATCH_ADDR, (unsigned int *)&rb_debug->scratch_addr); + rb->device->ftbl.device_regread(rb->device, mmCP_ME_CNTL, (unsigned int *)&rb_debug->cp_me_cntl); + rb->device->ftbl.device_regread(rb->device, mmCP_ME_STATUS, (unsigned int *)&rb_debug->cp_me_status); + rb->device->ftbl.device_regread(rb->device, mmCP_DEBUG, (unsigned int *)&rb_debug->cp_debug); + rb->device->ftbl.device_regread(rb->device, mmCP_STAT, (unsigned int *)&rb_debug->cp_stat); + rb->device->ftbl.device_regread(rb->device, mmRBBM_STATUS, (unsigned int *)&rb_debug->rbbm_status); + rb_debug->sop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_CONSUMED); + rb_debug->eop_timestamp = kgsl_cmdstream_readtimestamp(rb->device->id, GSL_TIMESTAMP_RETIRED); +} +#endif + + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats) +{ +#ifdef GSL_STATS_RINGBUFFER + KOS_ASSERT(stats); + + if (!(rb->flags & GSL_FLAGS_STARTED)) + { + return (GSL_FAILURE); + } + + kos_memcpy(stats, &rb->stats, sizeof(gsl_rbstats_t)); + + return (GSL_SUCCESS); +#else + // unreferenced formal parameters + (void) rb; + (void) stats; + + return (GSL_FAILURE_NOTSUPPORTED); +#endif // GSL_STATS_RINGBUFFER +} + +//---------------------------------------------------------------------------- + +int +kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb) +{ + unsigned int *cmds; + unsigned int temp, k, j; + int status; + int i; +#ifdef _DEBUG + gsl_rb_debug_t rb_debug; +#endif + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb=0x%08x)\n", rb ); + + if (!(rb->flags & GSL_FLAGS_STARTED)) + { + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // simple nop submit + cmds = kgsl_ringbuffer_addcmds(rb, 2); + if (!cmds) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_RB_WRITE(cmds, pm4_nop_packet(1)); + GSL_RB_WRITE(cmds, 0xDEADBEEF); + + kgsl_ringbuffer_submit(rb); + + status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT); + + if (status != GSL_SUCCESS) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status ); + return (status); + } + + // simple scratch submit + cmds = kgsl_ringbuffer_addcmds(rb, 2); + if (!cmds) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1)); + GSL_RB_WRITE(cmds, 0xFEEDF00D); + + kgsl_ringbuffer_submit(rb); + + status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT); + + if (status != GSL_SUCCESS) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status ); + return (status); + } + + rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp); + + if (temp != 0xFEEDF00D) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // simple wraps + for (i = 0; i < 256; i+=2) + { + j = ((rb->sizedwords >> 2) - 256) + i; + + cmds = kgsl_ringbuffer_addcmds(rb, j); + if (!cmds) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + k = 0; + + while (k < j) + { + k+=2; + GSL_RB_WRITE(cmds, pm4_type0_packet(mmSCRATCH_REG7, 1)); + GSL_RB_WRITE(cmds, k); + } + + kgsl_ringbuffer_submit(rb); + + status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT); + + if (status != GSL_SUCCESS) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status ); + return (status); + } + + rb->device->ftbl.device_regread(rb->device, mmSCRATCH_REG7, &temp); + + if (temp != k) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + } + + // max size submits, TODO do this at least with regreads + for (i = 0; i < 256; i++) + { + cmds = kgsl_ringbuffer_addcmds(rb, (rb->sizedwords >> 2)); + if (!cmds) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + GSL_RB_WRITE(cmds, pm4_nop_packet((rb->sizedwords >> 2) - 1)); + + kgsl_ringbuffer_submit(rb); + + status = rb->device->ftbl.device_idle(rb->device, GSL_TIMEOUT_DEFAULT); + + if (status != GSL_SUCCESS) + { +#ifdef _DEBUG + kgsl_ringbuffer_debug(rb, &rb_debug); +#endif + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", status ); + return (status); + } + } + + // submit load with randomness + +#ifdef GSL_RB_USE_MEM_TIMESTAMP + // scratch memptr validate +#endif // GSL_RB_USE_MEM_TIMESTAMP + +#ifdef GSL_RB_USE_MEM_RPTR + // rptr memptr validate +#endif // GSL_RB_USE_MEM_RPTR + +#ifdef GSL_RB_USE_WPTR_POLLING + // wptr memptr validate +#endif // GSL_RB_USE_WPTR_POLLING + + kgsl_log_write( KGSL_LOG_GROUP_COMMAND | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_ringbuffer_bist. Return value %d\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +#endif + diff --git a/drivers/mxc/amd-gpu/common/gsl_sharedmem.c b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c new file mode 100644 index 000000000000..51e66f97c52e --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_sharedmem.c @@ -0,0 +1,937 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" + +///////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_SHMEM_APERTURE_MARK(aperture_id) \ + (shmem->priv |= (((aperture_id + 1) << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK)) + +#define GSL_SHMEM_APERTURE_ISMARKED(aperture_id) \ + (((shmem->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT) & (aperture_id + 1)) + +#define GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id) \ + aperture_id = (gsl_apertureid_t)((flags & GSL_MEMFLAGS_APERTURE_MASK) >> GSL_MEMFLAGS_APERTURE_SHIFT); \ + KOS_ASSERT(aperture_id < GSL_APERTURE_MAX); + +#define GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id) \ + channel_id = (gsl_channelid_t)((flags & GSL_MEMFLAGS_CHANNEL_MASK) >> GSL_MEMFLAGS_CHANNEL_SHIFT); \ + KOS_ASSERT(channel_id < GSL_CHANNEL_MAX); + +#define GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index) \ + memdesc->priv = (memdesc->priv & ~GSL_APERTURE_MASK) | ((aperture_index << GSL_APERTURE_SHIFT) & GSL_APERTURE_MASK); + +#define GSL_MEMDESC_DEVICE_SET(memdesc, device_id) \ + memdesc->priv = (memdesc->priv & ~GSL_DEVICEID_MASK) | ((device_id << GSL_DEVICEID_SHIFT) & GSL_DEVICEID_MASK); + +#define GSL_MEMDESC_EXTALLOC_SET(memdesc, flag) \ + memdesc->priv = (memdesc->priv & ~GSL_EXTALLOC_MASK) | ((flag << GSL_EXTALLOC_SHIFT) & GSL_EXTALLOC_MASK); + +#define GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index) \ + KOS_ASSERT(memdesc); \ + aperture_index = ((memdesc->priv & GSL_APERTURE_MASK) >> GSL_APERTURE_SHIFT); \ + KOS_ASSERT(aperture_index < GSL_SHMEM_MAX_APERTURES); + +#define GSL_MEMDESC_DEVICE_GET(memdesc, device_id) \ + KOS_ASSERT(memdesc); \ + device_id = (gsl_deviceid_t)((memdesc->priv & GSL_DEVICEID_MASK) >> GSL_DEVICEID_SHIFT); \ + KOS_ASSERT(device_id <= GSL_DEVICE_MAX); + +#define GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc) \ + ((memdesc->priv & GSL_EXTALLOC_MASK) >> GSL_EXTALLOC_SHIFT) + + +////////////////////////////////////////////////////////////////////////////// +// aperture index in shared memory object +////////////////////////////////////////////////////////////////////////////// +OSINLINE int +kgsl_sharedmem_getapertureindex(gsl_sharedmem_t *shmem, gsl_apertureid_t aperture_id, gsl_channelid_t channel_id) +{ + KOS_ASSERT(shmem->aperturelookup[aperture_id][channel_id] < shmem->numapertures); + + return (shmem->aperturelookup[aperture_id][channel_id]); +} + + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +int +kgsl_sharedmem_init(gsl_sharedmem_t *shmem) +{ + int i; + int status; + gsl_shmemconfig_t config; + int mmu_virtualized; + gsl_apertureid_t aperture_id; + gsl_channelid_t channel_id; + unsigned int hostbaseaddr; + gpuaddr_t gpubaseaddr; + int sizebytes; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_init(gsl_sharedmem_t *shmem=0x%08x)\n", shmem ); + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS ); + return (GSL_SUCCESS); + } + + status = kgsl_hal_getshmemconfig(&config); + if (status != GSL_SUCCESS) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to get sharedmem config.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", status ); + return (status); + } + + shmem->numapertures = config.numapertures; + + for (i = 0; i < shmem->numapertures; i++) + { + aperture_id = config.apertures[i].id; + channel_id = config.apertures[i].channel; + hostbaseaddr = config.apertures[i].hostbase; + gpubaseaddr = config.apertures[i].gpubase; + sizebytes = config.apertures[i].sizebytes; + mmu_virtualized = 0; + + // handle mmu virtualized aperture + if (aperture_id == GSL_APERTURE_MMU) + { + mmu_virtualized = 1; + aperture_id = GSL_APERTURE_EMEM; + } + + // make sure aligned to page size + KOS_ASSERT((gpubaseaddr & ((1 << GSL_PAGESIZE_SHIFT) - 1)) == 0); + + // make a multiple of page size + sizebytes = (sizebytes & ~((1 << GSL_PAGESIZE_SHIFT) - 1)); + + if (sizebytes > 0) + { + shmem->apertures[i].memarena = kgsl_memarena_create(aperture_id, mmu_virtualized, hostbaseaddr, gpubaseaddr, sizebytes); + + if (!shmem->apertures[i].memarena) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Unable to allocate memarena.\n" ); + kgsl_sharedmem_close(shmem); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + shmem->apertures[i].id = aperture_id; + shmem->apertures[i].channel = channel_id; + shmem->apertures[i].numbanks = 1; + + // create aperture lookup table + if (GSL_SHMEM_APERTURE_ISMARKED(aperture_id)) + { + // update "current aperture_id"/"current channel_id" index + shmem->aperturelookup[aperture_id][channel_id] = i; + } + else + { + // initialize "current aperture_id"/"channel_id" indexes + for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++) + { + shmem->aperturelookup[aperture_id][channel_id] = i; + } + + GSL_SHMEM_APERTURE_MARK(aperture_id); + } + } + } + + shmem->flags |= GSL_FLAGS_INITIALIZED; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_init. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_close(gsl_sharedmem_t *shmem) +{ + int i; + int result = GSL_SUCCESS; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_close(gsl_sharedmem_t *shmem=0x%08x)\n", shmem ); + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + for (i = 0; i < shmem->numapertures; i++) + { + if (shmem->apertures[i].memarena) + { + result = kgsl_memarena_destroy(shmem->apertures[i].memarena); + } + } + + kos_memset(shmem, 0, sizeof(gsl_sharedmem_t)); + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_close. Return value %B\n", result ); + + return (result); +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc) +{ + gsl_apertureid_t aperture_id; + gsl_channelid_t channel_id; + gsl_deviceid_t tmp_id; + int aperture_index, org_index; + int result = GSL_FAILURE; + gsl_mmu_t *mmu = NULL; + gsl_sharedmem_t *shmem = &gsl_driver.shmem; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_alloc(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, int sizebytes=%d, gsl_memdesc_t *memdesc=%M)\n", + device_id, flags, sizebytes, memdesc ); + + KOS_ASSERT(sizebytes); + KOS_ASSERT(memdesc); + + GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id); + GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id); + + kos_memset(memdesc, 0, sizeof(gsl_memdesc_t)); + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + // execute pending device action + tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1; + for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++) + { + if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED) + { + kgsl_device_runpending(&gsl_driver.device[tmp_id-1]); + + if (tmp_id == device_id) + { + break; + } + } + } + + // convert any device to an actual existing device + if (device_id == GSL_DEVICE_ANY) + { + for ( ; ; ) + { + device_id++; + + if (device_id <= GSL_DEVICE_MAX) + { + if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED) + { + break; + } + } + else + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + } + } + + KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX); + + // get mmu reference + mmu = &gsl_driver.device[device_id-1].mmu; + + aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id); + + //do not proceed if it is a strict request, the aperture requested is not present, and the MMU is enabled + if (!((flags & GSL_MEMFLAGS_STRICTREQUEST) && aperture_id != shmem->apertures[aperture_index].id && kgsl_mmu_isenabled(mmu))) + { + // do allocation + result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc); + + // if allocation failed + if (result != GSL_SUCCESS) + { + org_index = aperture_index; + + // then failover to other channels within the current aperture + for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++) + { + aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id); + + if (aperture_index != org_index) + { + // do allocation + result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc); + + if (result == GSL_SUCCESS) + { + break; + } + } + } + + // if allocation still has not succeeded, then failover to EMEM/MMU aperture, but + // not if it's a strict request and the MMU is enabled + if (result != GSL_SUCCESS && aperture_id != GSL_APERTURE_EMEM + && !((flags & GSL_MEMFLAGS_STRICTREQUEST) && kgsl_mmu_isenabled(mmu))) + { + aperture_id = GSL_APERTURE_EMEM; + + // try every channel + for (channel_id = GSL_CHANNEL_1; channel_id < GSL_CHANNEL_MAX; channel_id++) + { + aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id); + + if (aperture_index != org_index) + { + // do allocation + result = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, sizebytes, memdesc); + + if (result == GSL_SUCCESS) + { + break; + } + } + } + } + } + } + + if (result == GSL_SUCCESS) + { + GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index); + GSL_MEMDESC_DEVICE_SET(memdesc, device_id); + + if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena)) + { + gsl_scatterlist_t scatterlist; + + scatterlist.contiguous = 0; + scatterlist.num = memdesc->size / GSL_PAGESIZE; + + if (memdesc->size & (GSL_PAGESIZE-1)) + { + scatterlist.num++; + } + + scatterlist.pages = kos_malloc(sizeof(unsigned int) * scatterlist.num); + if (scatterlist.pages) + { + // allocate physical pages + result = kgsl_hal_allocphysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages); + if (result == GSL_SUCCESS) + { + result = kgsl_mmu_map(mmu, memdesc->gpuaddr, &scatterlist, flags, GSL_CALLER_PROCESSID_GET()); + if (result != GSL_SUCCESS) + { + kgsl_hal_freephysical(memdesc->gpuaddr, scatterlist.num, scatterlist.pages); + } + } + + kos_free(scatterlist.pages); + } + else + { + result = GSL_FAILURE; + } + + if (result != GSL_SUCCESS) + { + kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc); + } + } + } + + KGSL_DEBUG_TBDUMP_SETMEM( memdesc->gpuaddr, 0, memdesc->size ); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_alloc. Return value %B\n", result ); + + return (result); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_alloc0(device_id, flags, sizebytes, memdesc); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid) +{ + int status = GSL_SUCCESS; + int aperture_index; + gsl_deviceid_t device_id; + gsl_sharedmem_t *shmem; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "--> int kgsl_sharedmem_free(gsl_memdesc_t *memdesc=%M)\n", memdesc ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + GSL_MEMDESC_DEVICE_GET(memdesc, device_id); + + shmem = &gsl_driver.shmem; + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena)) + { + status |= kgsl_mmu_unmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, pid); + + if (!GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)) + { + status |= kgsl_hal_freephysical(memdesc->gpuaddr, memdesc->size / GSL_PAGESIZE, NULL); + } + } + + kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc); + + // clear descriptor + kos_memset(memdesc, 0, sizeof(gsl_memdesc_t)); + } + else + { + status = GSL_FAILURE; + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_free. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_free(gsl_memdesc_t *memdesc) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET()); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace) +{ + int aperture_index; + gsl_sharedmem_t *shmem; + unsigned int gpuoffsetbytes; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_read(gsl_memdesc_t *memdesc=%M, void *dst=0x%08x, unsigned int offsetbytes=%d, unsigned int sizebytes=%d)\n", + memdesc, dst, offsetbytes, sizebytes ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + + if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE_BADPARAM ); + return (GSL_FAILURE_BADPARAM); + } + + shmem = &gsl_driver.shmem; + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + KOS_ASSERT(dst); + KOS_ASSERT(sizebytes); + + if (memdesc->gpuaddr < shmem->apertures[aperture_index].memarena->gpubaseaddr) + { + return (GSL_FAILURE_BADPARAM); + } + + if (memdesc->gpuaddr + sizebytes > shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes) + { + return (GSL_FAILURE_BADPARAM); + } + + gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes; + + GSL_HAL_MEM_READ(dst, shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, sizebytes, touserspace); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_read. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_read0(memdesc, dst, offsetbytes, sizebytes, touserspace); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace) +{ + int aperture_index; + gsl_sharedmem_t *shmem; + unsigned int gpuoffsetbytes; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_write(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, void *src=0x%08x, unsigned int sizebytes=%d)\n", + memdesc, offsetbytes, src, sizebytes ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + + if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE_BADPARAM ); + return (GSL_FAILURE_BADPARAM); + } + + shmem = &gsl_driver.shmem; + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + KOS_ASSERT(src); + KOS_ASSERT(sizebytes); + KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr); + KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)); + + gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes; + + GSL_HAL_MEM_WRITE(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, src, sizebytes, fromuserspace); + + KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMWRITE((memdesc->gpuaddr + offsetbytes), sizebytes, src)); + + KGSL_DEBUG_TBDUMP_SYNCMEM( (memdesc->gpuaddr + offsetbytes), src, sizebytes ); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_write. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_write0(memdesc, offsetbytes, src, sizebytes, fromuserspace); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes) +{ + int aperture_index; + gsl_sharedmem_t *shmem; + unsigned int gpuoffsetbytes; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_set(gsl_memdesc_t *memdesc=%M, unsigned int offsetbytes=%d, unsigned int value=0x%08x, unsigned int sizebytes=%d)\n", + memdesc, offsetbytes, value, sizebytes ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + + if (GSL_MEMDESC_EXTALLOC_ISMARKED(memdesc)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE_BADPARAM ); + return (GSL_FAILURE_BADPARAM); + } + + shmem = &gsl_driver.shmem; + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + + KOS_ASSERT(sizebytes); + KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr); + KOS_ASSERT((memdesc->gpuaddr + sizebytes) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)); + + gpuoffsetbytes = (memdesc->gpuaddr - shmem->apertures[aperture_index].memarena->gpubaseaddr) + offsetbytes; + + GSL_HAL_MEM_SET(shmem->apertures[aperture_index].memarena->hostbaseaddr, gpuoffsetbytes, value, sizebytes); + + KGSL_DEBUG(GSL_DBGFLAGS_PM4MEM, KGSL_DEBUG_DUMPMEMSET((memdesc->gpuaddr + offsetbytes), sizebytes, value)); + + KGSL_DEBUG_TBDUMP_SETMEM( (memdesc->gpuaddr + offsetbytes), value, sizebytes ); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_set. Return value %B\n", GSL_SUCCESS ); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes) +{ + int status = GSL_SUCCESS; + GSL_API_MUTEX_LOCK(); + status = kgsl_sharedmem_set0(memdesc, offsetbytes, value, sizebytes); + GSL_API_MUTEX_UNLOCK(); + return status; +} + +//---------------------------------------------------------------------------- + +KGSL_API unsigned int +kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags) +{ + gsl_apertureid_t aperture_id; + gsl_channelid_t channel_id; + int aperture_index; + unsigned int result = 0; + gsl_sharedmem_t *shmem; + + // device_id is ignored at this level, it would be used with per-device memarena's + + // unreferenced formal parameter + (void) device_id; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x)\n", + device_id, flags ); + + GSL_MEMFLAGS_APERTURE_GET(flags, aperture_id); + GSL_MEMFLAGS_CHANNEL_GET(flags, channel_id); + + GSL_API_MUTEX_LOCK(); + + shmem = &gsl_driver.shmem; + + if (!(shmem->flags & GSL_FLAGS_INITIALIZED)) + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Shared memory not initialized.\n" ); + GSL_API_MUTEX_UNLOCK(); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", 0 ); + return (0); + } + + aperture_index = kgsl_sharedmem_getapertureindex(shmem, aperture_id, channel_id); + + if (aperture_id == shmem->apertures[aperture_index].id) + { + result = kgsl_memarena_getlargestfreeblock(shmem->apertures[aperture_index].memarena, flags); + } + + GSL_API_MUTEX_UNLOCK(); + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_largestfreeblock. Return value %d\n", result ); + + return (result); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc) +{ + int status = GSL_FAILURE; + gsl_sharedmem_t *shmem = &gsl_driver.shmem; + int aperture_index; + gsl_deviceid_t tmp_id; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_map(gsl_deviceid_t device_id=%D, gsl_flags_t flags=0x%08x, gsl_scatterlist_t scatterlist=%M, gsl_memdesc_t *memdesc=%M)\n", + device_id, flags, memdesc, scatterlist ); + + // execute pending device action + tmp_id = (device_id != GSL_DEVICE_ANY) ? device_id : device_id+1; + for ( ; tmp_id <= GSL_DEVICE_MAX; tmp_id++) + { + if (gsl_driver.device[tmp_id-1].flags & GSL_FLAGS_INITIALIZED) + { + kgsl_device_runpending(&gsl_driver.device[tmp_id-1]); + + if (tmp_id == device_id) + { + break; + } + } + } + + // convert any device to an actual existing device + if (device_id == GSL_DEVICE_ANY) + { + for ( ; ; ) + { + device_id++; + + if (device_id <= GSL_DEVICE_MAX) + { + if (gsl_driver.device[device_id-1].flags & GSL_FLAGS_INITIALIZED) + { + break; + } + } + else + { + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_ERROR, "ERROR: Invalid device.\n" ); + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", GSL_FAILURE ); + return (GSL_FAILURE); + } + } + } + + KOS_ASSERT(device_id > GSL_DEVICE_ANY && device_id <= GSL_DEVICE_MAX); + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + aperture_index = kgsl_sharedmem_getapertureindex(shmem, GSL_APERTURE_EMEM, GSL_CHANNEL_1); + + if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena)) + { + KOS_ASSERT(scatterlist->num); + KOS_ASSERT(scatterlist->pages); + + status = kgsl_memarena_alloc(shmem->apertures[aperture_index].memarena, flags, scatterlist->num *GSL_PAGESIZE, memdesc); + if (status == GSL_SUCCESS) + { + GSL_MEMDESC_APERTURE_SET(memdesc, aperture_index); + GSL_MEMDESC_DEVICE_SET(memdesc, device_id); + + // mark descriptor's memory as externally allocated -- i.e. outside GSL + GSL_MEMDESC_EXTALLOC_SET(memdesc, 1); + + status = kgsl_mmu_map(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, scatterlist, flags, GSL_CALLER_PROCESSID_GET()); + if (status != GSL_SUCCESS) + { + kgsl_memarena_free(shmem->apertures[aperture_index].memarena, memdesc); + } + } + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_map. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc) +{ + return (kgsl_sharedmem_free0(memdesc, GSL_CALLER_PROCESSID_GET())); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist) +{ + int status = GSL_SUCCESS; + int aperture_index; + gsl_deviceid_t device_id; + gsl_sharedmem_t *shmem; + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, + "--> int kgsl_sharedmem_getmap(gsl_memdesc_t *memdesc=%M, gsl_scatterlist_t scatterlist=%M)\n", + memdesc, scatterlist ); + + GSL_MEMDESC_APERTURE_GET(memdesc, aperture_index); + GSL_MEMDESC_DEVICE_GET(memdesc, device_id); + + shmem = &gsl_driver.shmem; + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + KOS_ASSERT(scatterlist->num); + KOS_ASSERT(scatterlist->pages); + KOS_ASSERT(memdesc->gpuaddr >= shmem->apertures[aperture_index].memarena->gpubaseaddr); + KOS_ASSERT((memdesc->gpuaddr + memdesc->size) <= (shmem->apertures[aperture_index].memarena->gpubaseaddr + shmem->apertures[aperture_index].memarena->sizebytes)); + + kos_memset(scatterlist->pages, 0, sizeof(unsigned int) * scatterlist->num); + + if (kgsl_memarena_isvirtualized(shmem->apertures[aperture_index].memarena)) + { + status = kgsl_mmu_getmap(&gsl_driver.device[device_id-1].mmu, memdesc->gpuaddr, memdesc->size, scatterlist, GSL_CALLER_PROCESSID_GET()); + } + else + { + // coalesce physically contiguous pages into a single scatter list entry + scatterlist->pages[0] = memdesc->gpuaddr; + scatterlist->contiguous = 1; + } + } + + kgsl_log_write( KGSL_LOG_GROUP_MEMORY | KGSL_LOG_LEVEL_TRACE, "<-- kgsl_sharedmem_getmap. Return value %B\n", status ); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats) +{ +#ifdef GSL_STATS_MEM + int status = GSL_SUCCESS; + int i; + + KOS_ASSERT(stats); + + if (shmem->flags & GSL_FLAGS_INITIALIZED) + { + for (i = 0; i < shmem->numapertures; i++) + { + if (shmem->apertures[i].memarena) + { + stats->apertures[i].id = shmem->apertures[i].id; + stats->apertures[i].channel = shmem->apertures[i].channel; + + status |= kgsl_memarena_querystats(shmem->apertures[i].memarena, &stats->apertures[i].memarena); + } + } + } + else + { + kos_memset(stats, 0, sizeof(gsl_sharedmem_stats_t)); + } + + return (status); +#else + // unreferenced formal parameters + (void) shmem; + (void) stats; + + return (GSL_FAILURE_NOTSUPPORTED); +#endif // GSL_STATS_MEM +} + +//---------------------------------------------------------------------------- + +unsigned int +kgsl_sharedmem_convertaddr(unsigned int addr, int type) +{ + gsl_sharedmem_t *shmem = &gsl_driver.shmem; + unsigned int cvtaddr = 0; + unsigned int gpubaseaddr, hostbaseaddr, sizebytes; + int i; + + if ((shmem->flags & GSL_FLAGS_INITIALIZED)) + { + for (i = 0; i < shmem->numapertures; i++) + { + hostbaseaddr = shmem->apertures[i].memarena->hostbaseaddr; + gpubaseaddr = shmem->apertures[i].memarena->gpubaseaddr; + sizebytes = shmem->apertures[i].memarena->sizebytes; + + // convert from gpu to host + if (type == 0) + { + if (addr >= gpubaseaddr && addr < (gpubaseaddr + sizebytes)) + { + cvtaddr = hostbaseaddr + (addr - gpubaseaddr); + break; + } + } + // convert from host to gpu + else if (type == 1) + { + if (addr >= hostbaseaddr && addr < (hostbaseaddr + sizebytes)) + { + cvtaddr = gpubaseaddr + (addr - hostbaseaddr); + break; + } + } + } + } + + return (cvtaddr); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation) +{ + int status = GSL_FAILURE; + + /* unreferenced formal parameter */ + (void)memdesc; + (void)offsetbytes; + (void)sizebytes; + (void)operation; + + /* do cache operation */ + + return (status); +} + +//---------------------------------------------------------------------------- + +KGSL_API int +kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr) +{ + int status = GSL_FAILURE; + + memdesc->gpuaddr = (gpuaddr_t)hostptr; /* map physical address with hostptr */ + memdesc->hostptr = hostptr; /* set virtual address also in memdesc */ + + /* unreferenced formal parameter */ + (void)device_id; + + return (status); +} diff --git a/drivers/mxc/amd-gpu/common/gsl_tbdump.c b/drivers/mxc/amd-gpu/common/gsl_tbdump.c new file mode 100644 index 000000000000..e22cf894f7b2 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_tbdump.c @@ -0,0 +1,228 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#ifdef WIN32 +#include +#endif +#include "gsl.h" +#include "gsl_tbdump.h" +#include "kos_libapi.h" + +#ifdef TBDUMP + +typedef struct TBDump_ +{ + void* file; +} TBDump; + + +static TBDump g_tb; +static oshandle_t tbdump_mutex = 0; +#define TBDUMP_MUTEX_LOCK() if( tbdump_mutex ) kos_mutex_lock( tbdump_mutex ) +#define TBDUMP_MUTEX_UNLOCK() if( tbdump_mutex ) kos_mutex_unlock( tbdump_mutex ) + +/* ------------------------------------------------------------------------ */ +/* ------------------------------------------------------------------------ */ +/* ------------------------------------------------------------------------ */ + +static void tbdump_printline(const char* format, ...) +{ + if(g_tb.file) + { + va_list va; + va_start(va, format); + vfprintf((FILE*)g_tb.file, format, va); + va_end(va); + fprintf((FILE*)g_tb.file, "\n"); + } +} + +static void tbdump_printinfo(const char* message ) +{ + tbdump_printline("15 %s", message); +} + +static void tbdump_getmemhex(char* buffer, unsigned int addr, unsigned int sizewords) +{ + unsigned int i = 0; + static const char* hexChars = "0123456789abcdef"; + unsigned char* ptr = (unsigned char*)addr; + + for (i = 0; i < sizewords; i++) + { + buffer[(sizewords - i) * 2 - 1] = hexChars[ptr[i] & 0x0f]; + buffer[(sizewords - i) * 2 - 2] = hexChars[ptr[i] >> 4]; + } + buffer[sizewords * 2] = '\0'; +} + +/* ------------------------------------------------------------------------ */ + +void tbdump_open(char* filename) +{ + if( !tbdump_mutex ) tbdump_mutex = kos_mutex_create( "TBDUMP_MUTEX" ); + + kos_memset( &g_tb, 0, sizeof( g_tb ) ); + + g_tb.file = kos_fopen( filename, "wt" ); + + tbdump_printinfo("reset"); + tbdump_printline("0"); + tbdump_printline("1 00000000 00000eff"); + + /* Enable interrupts */ + tbdump_printline("1 00000000 00000003"); +} + +void tbdump_close() +{ + TBDUMP_MUTEX_LOCK(); + + kos_fclose( g_tb.file ); + g_tb.file = 0; + + TBDUMP_MUTEX_UNLOCK(); + + if( tbdump_mutex ) kos_mutex_free( tbdump_mutex ); +} + +/* ------------------------------------------------------------------------ */ + +void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes) +{ + /* Align starting address and size */ + unsigned int beg = addr; + unsigned int end = addr+sizebytes; + char buffer[65]; + + TBDUMP_MUTEX_LOCK(); + + beg = (beg+15) & ~15; + end &= ~15; + + if( sizebytes <= 16 ) + { + tbdump_getmemhex(buffer, src, 16); + + tbdump_printline("19 %08x %i 1 %s", addr, sizebytes, buffer); + + TBDUMP_MUTEX_UNLOCK(); + return; + } + + /* Handle unaligned start */ + if( beg != addr ) + { + tbdump_getmemhex(buffer, src, 16); + + tbdump_printline("19 %08x %i 1 %s", addr, beg-addr, buffer); + + src += beg-addr; + } + + /* Dump the memory writes */ + while( beg < end ) + { + tbdump_getmemhex(buffer, src, 16); + + tbdump_printline("2 %08x %s", beg, buffer); + + beg += 16; + src += 16; + } + + /* Handle unaligned end */ + if( end != addr+sizebytes ) + { + tbdump_getmemhex(buffer, src, 16); + + tbdump_printline("19 %08x %i 1 %s", end, (addr+sizebytes)-end, buffer); + } + + TBDUMP_MUTEX_UNLOCK(); +} + +/* ------------------------------------------------------------------------ */ + +void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes) +{ + TBDUMP_MUTEX_LOCK(); + + tbdump_printline("19 %08x 4 %i %032x", addr, (sizebytes+3)/4, value ); + + TBDUMP_MUTEX_UNLOCK(); +} + +/* ------------------------------------------------------------------------ */ + +void tbdump_slavewrite(unsigned int addr, unsigned int value) +{ + TBDUMP_MUTEX_LOCK(); + + tbdump_printline("1 %08x %08x", addr, value); + + TBDUMP_MUTEX_UNLOCK(); +} + +/* ------------------------------------------------------------------------ */ + + +KGSL_API int +kgsl_tbdump_waitirq() +{ + if(!g_tb.file) return GSL_FAILURE; + + TBDUMP_MUTEX_LOCK(); + + tbdump_printinfo("wait irq"); + tbdump_printline("10"); + + /* ACK IRQ */ + tbdump_printline("1 00000418 00000003"); + tbdump_printline("18 00000018 00000000 # slave read & assert"); + + TBDUMP_MUTEX_UNLOCK(); + + return GSL_SUCCESS; +} + +/* ------------------------------------------------------------------------ */ + +KGSL_API int +kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height) +{ + static char filename[20]; + static int numframe = 0; + + if(!g_tb.file) return GSL_FAILURE; + + TBDUMP_MUTEX_LOCK(); + #pragma warning(disable:4996) + sprintf( filename, "tbdump_%08d.bmp", numframe++ ); + + tbdump_printline("13 %s %d %08x %d %d %d 0", filename, format, (unsigned int)addr, stride, width, height); + + TBDUMP_MUTEX_UNLOCK(); + + return GSL_SUCCESS; +} + +/* ------------------------------------------------------------------------ */ + +#endif /* TBDUMP */ diff --git a/drivers/mxc/amd-gpu/common/gsl_yamato.c b/drivers/mxc/amd-gpu/common/gsl_yamato.c new file mode 100644 index 000000000000..07c651f57f42 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/gsl_yamato.c @@ -0,0 +1,924 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_hal.h" +#ifdef _LINUX +#include +#include +#endif + +#ifdef GSL_BLD_YAMATO + +#include "gsl_ringbuffer.h" +#include "gsl_drawctxt.h" + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +static int +kgsl_yamato_gmeminit(gsl_device_t *device) +{ + rb_edram_info_u rb_edram_info = {0}; + unsigned int gmem_size; + unsigned int edram_value = 0; + + // make sure edram range is aligned to size + KOS_ASSERT((device->gmemspace.gpu_base & (device->gmemspace.sizebytes - 1)) == 0); + + // get edram_size value equivalent + gmem_size = (device->gmemspace.sizebytes >> 14); + while (gmem_size >>= 1) + { + edram_value++; + } + + rb_edram_info.f.edram_size = edram_value; + rb_edram_info.f.edram_mapping_mode = 0; // EDRAM_MAP_UPPER + rb_edram_info.f.edram_range = (device->gmemspace.gpu_base >> 14); // must be aligned to size + + device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, (unsigned int)rb_edram_info.val); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static int +kgsl_yamato_gmemclose(gsl_device_t *device) +{ + device->ftbl.device_regwrite(device, mmRB_EDRAM_INFO, 0x00000000); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +void +kgsl_yamato_rbbmintrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_device_t *device = (gsl_device_t *) cookie; + + switch(id) + { + // error condition interrupt + case GSL_INTR_YDX_RBBM_READ_ERROR: + printk(KERN_ERR "GPU: Z430 RBBM Read Error\n"); + schedule_work(&device->irq_err_work); + break; + + // non-error condition interrupt + case GSL_INTR_YDX_RBBM_DISPLAY_UPDATE: + case GSL_INTR_YDX_RBBM_GUI_IDLE: + + kos_event_signal(device->intr.evnt[id]); + break; + + default: + + break; + } +} + +//---------------------------------------------------------------------------- + +void +kgsl_yamato_cpintrcallback(gsl_intrid_t id, void *cookie) +{ + gsl_device_t *device = (gsl_device_t *) cookie; + + switch(id) + { + case GSL_INTR_YDX_CP_RING_BUFFER: +#ifndef _LINUX + kos_event_signal(device->timestamp_event); +#else + wake_up_interruptible_all(&(device->timestamp_waitq)); +#endif + break; + default: + break; + } +} +//---------------------------------------------------------------------------- + +void +kgsl_yamato_sqintrcallback(gsl_intrid_t id, void *cookie) +{ + (void) cookie; // unreferenced formal parameter + /*gsl_device_t *device = (gsl_device_t *) cookie;*/ + + switch(id) + { + // error condition interrupt + case GSL_INTR_YDX_SQ_PS_WATCHDOG: + case GSL_INTR_YDX_SQ_VS_WATCHDOG: + + // todo: take appropriate action + + break; + + default: + + break; + } +} + +//---------------------------------------------------------------------------- + +#ifdef _DEBUG + +static int +kgsl_yamato_bist(gsl_device_t *device) +{ + int status = GSL_FAILURE; + unsigned int link[2]; + + if (!(device->flags & GSL_FLAGS_STARTED)) + { + return (GSL_FAILURE); + } + + status = kgsl_ringbuffer_bist(&device->ringbuffer); + if (status != GSL_SUCCESS) + { + return (status); + } + + // interrupt bist + link[0] = pm4_type3_packet(PM4_INTERRUPT, 1); + link[1] = CP_INT_CNTL__RB_INT_MASK; + kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, GSL_CALLER_PROCESSID_GET()); + + status = kgsl_mmu_bist(&device->mmu); + if (status != GSL_SUCCESS) + { + return (status); + } + + return (status); +} +#endif + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_isr(gsl_device_t *device) +{ + unsigned int status; +#ifdef _DEBUG + mh_mmu_page_fault_u page_fault = {0}; + mh_axi_error_u axi_error = {0}; + mh_clnt_axi_id_reuse_u clnt_axi_id_reuse = {0}; + rbbm_read_error_u read_error = {0}; +#endif // DEBUG + + // determine if yamato is interrupting, and if so, which block + device->ftbl.device_regread(device, mmMASTER_INT_SIGNAL, &status); + + if (status & MASTER_INT_SIGNAL__MH_INT_STAT) + { +#ifdef _DEBUG + // obtain mh error information + device->ftbl.device_regread(device, mmMH_MMU_PAGE_FAULT, (unsigned int *)&page_fault); + device->ftbl.device_regread(device, mmMH_AXI_ERROR, (unsigned int *)&axi_error); + device->ftbl.device_regread(device, mmMH_CLNT_AXI_ID_REUSE, (unsigned int *)&clnt_axi_id_reuse); +#endif // DEBUG + + kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_MH); + } + + if (status & MASTER_INT_SIGNAL__CP_INT_STAT) + { + kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_CP); + } + + if (status & MASTER_INT_SIGNAL__RBBM_INT_STAT) + { +#ifdef _DEBUG + // obtain rbbm error information + device->ftbl.device_regread(device, mmRBBM_READ_ERROR, (unsigned int *)&read_error); +#endif // DEBUG + + kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_RBBM); + } + + if (status & MASTER_INT_SIGNAL__SQ_INT_STAT) + { + kgsl_intr_decode(device, GSL_INTR_BLOCK_YDX_SQ); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_tlbinvalidate(gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid) +{ + unsigned int link[2]; + mh_mmu_invalidate_u mh_mmu_invalidate = {0}; + + mh_mmu_invalidate.f.invalidate_all = 1; + mh_mmu_invalidate.f.invalidate_tc = 1; + + // if possible, invalidate via command stream, otherwise via direct register writes + if (device->flags & GSL_FLAGS_STARTED) + { + link[0] = pm4_type0_packet(reg_invalidate, 1); + link[1] = mh_mmu_invalidate.val; + + kgsl_ringbuffer_issuecmds(device, 1, &link[0], 2, pid); + } + else + { + + device->ftbl.device_regwrite(device, reg_invalidate, mh_mmu_invalidate.val); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_setpagetable(gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid) +{ + unsigned int link[25]; + + // if there is an active draw context, set via command stream, + if (device->flags & GSL_FLAGS_STARTED) + { + // wait for graphics pipe to be idle + link[0] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + link[1] = 0x00000000; + + // set page table base + link[2] = pm4_type0_packet(reg_ptbase, 1); + link[3] = ptbase; + + // HW workaround: to resolve MMU page fault interrupts caused by the VGT. It prevents + // the CP PFP from filling the VGT DMA request fifo too early, thereby ensuring that + // the VGT will not fetch vertex/bin data until after the page table base register + // has been updated. + // + // Two null DRAW_INDX_BIN packets are inserted right after the page table base update, + // followed by a wait for idle. The null packets will fill up the VGT DMA request + // fifo and prevent any further vertex/bin updates from occurring until the wait + // has finished. + link[4] = pm4_type3_packet(PM4_SET_CONSTANT, 2); + link[5] = (0x4 << 16) | (mmPA_SU_SC_MODE_CNTL - 0x2000); + link[6] = 0; // disable faceness generation + link[7] = pm4_type3_packet(PM4_SET_BIN_BASE_OFFSET, 1); + link[8] = device->mmu.dummyspace.gpuaddr; + link[9] = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6); + link[10] = 0; // viz query info + link[11] = 0x0003C004; // draw indicator + link[12] = 0; // bin base + link[13] = 3; // bin size + link[14] = device->mmu.dummyspace.gpuaddr; // dma base + link[15] = 6; // dma size + link[16] = pm4_type3_packet(PM4_DRAW_INDX_BIN, 6); + link[17] = 0; // viz query info + link[18] = 0x0003C004; // draw indicator + link[19] = 0; // bin base + link[20] = 3; // bin size + link[21] = device->mmu.dummyspace.gpuaddr; // dma base + link[22] = 6; // dma size + link[23] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + link[24] = 0x00000000; + + kgsl_ringbuffer_issuecmds(device, 1, &link[0], 25, pid); + } + else + { + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + device->ftbl.device_regwrite(device, reg_ptbase, ptbase); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +static void kgsl_yamato_irqerr(struct work_struct *work) +{ + gsl_device_t *device = &gsl_driver.device[GSL_DEVICE_YAMATO-1]; + device->ftbl.device_destroy(device); +} + +int +kgsl_yamato_init(gsl_device_t *device) +{ + int status = GSL_FAILURE; + + device->flags |= GSL_FLAGS_INITIALIZED; + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_ON, 100); + + //We need to make sure all blocks are powered up and clocked before + //issuing a soft reset. The overrides will be turned off (set to 0) + //later in kgsl_yamato_start. + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe); + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff); + + // soft reset + device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0xFFFFFFFF); + kos_sleep(50); + device->ftbl.device_regwrite(device, mmRBBM_SOFT_RESET, 0x00000000); + + // RBBM control + device->ftbl.device_regwrite(device, mmRBBM_CNTL, 0x00004442); + + // setup MH arbiter + device->ftbl.device_regwrite(device, mmMH_ARBITER_CONFIG, *(unsigned int *) &gsl_cfg_yamato_mharb); + + // SQ_*_PROGRAM + device->ftbl.device_regwrite(device, mmSQ_VS_PROGRAM, 0x00000000); + device->ftbl.device_regwrite(device, mmSQ_PS_PROGRAM, 0x00000000); + + // init interrupt + status = kgsl_intr_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + // init mmu + status = kgsl_mmu_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + /* handle error condition */ + INIT_WORK(&device->irq_err_work, kgsl_yamato_irqerr); + + return(status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_close(gsl_device_t *device) +{ + if (device->refcnt == 0) + { + // shutdown mmu + kgsl_mmu_close(device); + + // shutdown interrupt + kgsl_intr_close(device); + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_POWER_OFF, 0); + + device->flags &= ~GSL_FLAGS_INITIALIZED; + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_destroy(gsl_device_t *device) +{ + int i; + unsigned int pid; + +#ifdef _DEBUG + // for now, signal catastrophic failure in a brute force way + KOS_ASSERT(0); +#endif // _DEBUG + + // todo: - hard reset core? + + kgsl_drawctxt_destroyall(device); + + for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++) + { + pid = device->callerprocess[i]; + if (pid) + { + device->ftbl.device_stop(device); + kgsl_driver_destroy(pid); + + // todo: terminate client process? + } + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_start(gsl_device_t *device, gsl_flags_t flags) +{ + int status = GSL_FAILURE; + unsigned int pm1, pm2; + + KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPFBSTART(device)); + + (void) flags; // unreferenced formal parameter + + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_ON, 100); + + // default power management override when running in safe mode + pm1 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0xFFFFFFFE : 0x00000000; + pm2 = (device->flags & GSL_FLAGS_SAFEMODE) ? 0x000000FF : 0x00000000; + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, pm1); + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, pm2); + + // enable rbbm interrupts + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR, kgsl_yamato_rbbmintrcallback, (void *) device); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE, kgsl_yamato_rbbmintrcallback, (void *) device); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE, kgsl_yamato_rbbmintrcallback, (void *) device); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE); +#if defined GSL_RB_TIMESTAMP_INTERUPT + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER, kgsl_yamato_cpintrcallback, (void *) device); + kgsl_intr_enable(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER); +#endif + + //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE); + + // enable sq interrupts + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device); + kgsl_intr_attach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG, kgsl_yamato_sqintrcallback, (void *) device); + //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG); + //kgsl_intr_enable(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG); + + // init gmem + kgsl_yamato_gmeminit(device); + + // init ring buffer + status = kgsl_ringbuffer_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + // init draw context + status = kgsl_drawctxt_init(device); + if (status != GSL_SUCCESS) + { + device->ftbl.device_stop(device); + return (status); + } + + device->flags |= GSL_FLAGS_STARTED; + + KGSL_DEBUG(GSL_DBGFLAGS_BIST, kgsl_yamato_bist(device)); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_stop(gsl_device_t *device) +{ + // HW WORKAROUND: Ringbuffer hangs during next start if it is stopped without any + // commands ever being submitted. To avoid this, submit a dummy wait packet. + unsigned int cmds[2]; + cmds[0] = pm4_type3_packet(PM4_WAIT_FOR_IDLE, 1); + cmds[0] = 0; + kgsl_ringbuffer_issuecmds(device, 0, cmds, 2, GSL_CALLER_PROCESSID_GET()); + + // disable rbbm interrupts + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_READ_ERROR); + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_DISPLAY_UPDATE); + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_RBBM_GUI_IDLE); +#if defined GSL_RB_TIMESTAMP_INTERUPT + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_CP_RING_BUFFER); +#endif + + // disable sq interrupts + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_PS_WATCHDOG); + kgsl_intr_detach(&device->intr, GSL_INTR_YDX_SQ_VS_WATCHDOG); + + kgsl_drawctxt_close(device); + + // shutdown ringbuffer + kgsl_ringbuffer_close(&device->ringbuffer); + + // shutdown gmem + kgsl_yamato_gmemclose(device); + + if(device->refcnt == 0) + { + kgsl_hal_setpowerstate(device->id, GSL_PWRFLAGS_CLK_OFF, 0); + } + + device->flags &= ~GSL_FLAGS_STARTED; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_getproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_FAILURE; + +#ifndef _DEBUG + (void) sizebytes; // unreferenced formal parameter +#endif + + if (type == GSL_PROP_DEVICE_INFO) + { + gsl_devinfo_t *devinfo = (gsl_devinfo_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_devinfo_t)); + + devinfo->device_id = device->id; + devinfo->chip_id = (gsl_chipid_t)device->chip_id; + devinfo->mmu_enabled = kgsl_mmu_isenabled(&device->mmu); + devinfo->gmem_hostbaseaddr = device->gmemspace.mmio_virt_base; + devinfo->gmem_gpubaseaddr = device->gmemspace.gpu_base; + devinfo->gmem_sizebytes = device->gmemspace.sizebytes; + devinfo->high_precision = 0; + + status = GSL_SUCCESS; + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_setproperty(gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes) +{ + int status = GSL_FAILURE; + +#ifndef _DEBUG + (void) sizebytes; // unreferenced formal parameter +#endif + + if (type == GSL_PROP_DEVICE_POWER) + { + gsl_powerprop_t *power = (gsl_powerprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_powerprop_t)); + + if (!(device->flags & GSL_FLAGS_SAFEMODE)) + { + if (power->flags & GSL_PWRFLAGS_OVERRIDE_ON) + { + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0xfffffffe); + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0xffffffff); + } + else if (power->flags & GSL_PWRFLAGS_OVERRIDE_OFF) + { + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE1, 0x00000000); + device->ftbl.device_regwrite(device, mmRBBM_PM_OVERRIDE2, 0x00000000); + } + else + { + kgsl_hal_setpowerstate(device->id, power->flags, power->value); + } + } + + status = GSL_SUCCESS; + } + else if (type == GSL_PROP_DEVICE_DMI) + { + gsl_dmiprop_t *dmi = (gsl_dmiprop_t *) value; + + KOS_ASSERT(sizebytes == sizeof(gsl_dmiprop_t)); + + // + // In order to enable DMI, it must not already be enabled. + // + switch (dmi->flags) + { + case GSL_DMIFLAGS_ENABLE_SINGLE: + case GSL_DMIFLAGS_ENABLE_DOUBLE: + if (!gsl_driver.dmi_state) + { + gsl_driver.dmi_state = OS_TRUE; + gsl_driver.dmi_mode = dmi->flags; + gsl_driver.dmi_frame = -1; + status = GSL_SUCCESS; + } + break; + case GSL_DMIFLAGS_DISABLE: + // + // To disable, we must be enabled. + // + if (gsl_driver.dmi_state) + { + gsl_driver.dmi_state = OS_FALSE; + gsl_driver.dmi_mode = -1; + gsl_driver.dmi_frame = -2; + status = GSL_SUCCESS; + } + break; + case GSL_DMIFLAGS_NEXT_BUFFER: + // + // Going to the next buffer is dependent upon what mod we are in with respect to single, double, or triple buffering. + // DMI must also be enabled. + // + if (gsl_driver.dmi_state) + { + unsigned int cmdbuf[10]; + unsigned int *cmds = &cmdbuf[0]; + int size; + + if (gsl_driver.dmi_frame == -1) + { + size = 8; + + *cmds++ = pm4_type0_packet(mmRBBM_DSPLY, 1); + switch (gsl_driver.dmi_mode) + { + case GSL_DMIFLAGS_ENABLE_SINGLE: + gsl_driver.dmi_max_frame = 1; + *cmds++ = 0x041000410; + break; + case GSL_DMIFLAGS_ENABLE_DOUBLE: + gsl_driver.dmi_max_frame = 2; + *cmds++ = 0x041000510; + break; + case GSL_DMIFLAGS_ENABLE_TRIPLE: + gsl_driver.dmi_max_frame = 3; + *cmds++ = 0x041000610; + break; + } + } + else + { + size = 6; + } + + + // + // Wait for 3D core to be idle and wait for vsync + // + *cmds++ = pm4_type0_packet(mmWAIT_UNTIL, 1); + *cmds++ = 0x00008000; // 3d idle + // *cmds++ = 0x00008008; // 3d idle & vsync + + // + // Update the render latest register. + // + *cmds++ = pm4_type0_packet(mmRBBM_RENDER_LATEST, 1); + switch (gsl_driver.dmi_frame) + { + case 0: + // + // Render frame 0 + // + *cmds++ = 0; + // + // Wait for our max frame # indicator to be de-asserted + // + *cmds++ = pm4_type0_packet(mmWAIT_UNTIL, 1); + *cmds++ = 0x00000008 << gsl_driver.dmi_max_frame; + gsl_driver.dmi_frame = 1; + break; + case -1: + case 1: + // + // Render frame 1 + // + *cmds++ = 1; + *cmds++ = pm4_type0_packet(mmWAIT_UNTIL, 1); + *cmds++ = 0x00000010; // Wait for frame 0 to be deasserted + gsl_driver.dmi_frame = 2; + break; + case 2: + // + // Render frame 2 + // + *cmds++ = 2; + *cmds++ = pm4_type0_packet(mmWAIT_UNTIL, 1); + *cmds++ = 0x00000020; // Wait for frame 1 to be deasserted + gsl_driver.dmi_frame = 0; + break; + } + + // issue the commands + kgsl_ringbuffer_issuecmds(device, 1, &cmdbuf[0], size, GSL_CALLER_PROCESSID_GET()); + + gsl_driver.dmi_frame %= gsl_driver.dmi_max_frame; + status = GSL_SUCCESS; + } + break; + default: + status = GSL_FAILURE; + break; + } + } + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_idle(gsl_device_t *device, unsigned int timeout) +{ + int status = GSL_FAILURE; + gsl_ringbuffer_t *rb = &device->ringbuffer; + rbbm_status_u rbbm_status; + + (void) timeout; // unreferenced formal parameter + + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_REGPOLL, device->id, mmRBBM_STATUS, 0x80000000, "kgsl_yamato_idle")); + + GSL_RB_MUTEX_LOCK(); + + // first, wait until the CP has consumed all the commands in the ring buffer + if (rb->flags & GSL_FLAGS_STARTED) + { + do + { + GSL_RB_GET_READPTR(rb, &rb->rptr); + + } while (rb->rptr != rb->wptr); + } + + // now, wait for the GPU to finish its operations + for ( ; ; ) + { + device->ftbl.device_regread(device, mmRBBM_STATUS, (unsigned int *)&rbbm_status); + + if (!(rbbm_status.val & 0x80000000)) + { + status = GSL_SUCCESS; + break; + } + + } + + GSL_RB_MUTEX_UNLOCK(); + + return (status); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_regread(gsl_device_t *device, unsigned int offsetwords, unsigned int *value) +{ + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, + { + if (!(gsl_driver.flags_debug & GSL_DBGFLAGS_DUMPX_WITHOUT_IFH)) + { + if(offsetwords == mmCP_RB_RPTR || offsetwords == mmCP_RB_WPTR) + { + *value = device->ringbuffer.wptr; + return (GSL_SUCCESS); + } + } + }); + + GSL_HAL_REG_READ(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value); + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_regwrite(gsl_device_t *device, unsigned int offsetwords, unsigned int value) +{ + KGSL_DEBUG(GSL_DBGFLAGS_PM4, KGSL_DEBUG_DUMPREGWRITE(offsetwords, value)); + + GSL_HAL_REG_WRITE(device->id, (unsigned int) device->regspace.mmio_virt_base, offsetwords, value); + + // idle device when running in safe mode + if (device->flags & GSL_FLAGS_SAFEMODE) + { + device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT); + } + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_waitirq(gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout) +{ + int status = GSL_FAILURE_NOTSUPPORTED; + + if (intr_id == GSL_INTR_YDX_CP_IB1_INT || intr_id == GSL_INTR_YDX_CP_IB2_INT || + intr_id == GSL_INTR_YDX_CP_SW_INT || intr_id == GSL_INTR_YDX_RBBM_DISPLAY_UPDATE) + { + if (kgsl_intr_isenabled(&device->intr, intr_id) == GSL_SUCCESS) + { + // wait until intr completion event is received + if (kos_event_wait(device->intr.evnt[intr_id], timeout) == OS_SUCCESS) + { + *count = 1; + status = GSL_SUCCESS; + } + else + { + status = GSL_FAILURE_TIMEOUT; + } + } + } + + return (status); +} + +int kgsl_yamato_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp) +{ + int i; + /* Reason to use a wait loop: + * When bus is busy, for example vpu is working too, the timestamp is + * possiblly not yet refreshed to memory by yamato. For most cases, it + * will hit on first loop cycle. So it don't effect performance. + */ + for (i = 0; i < 10; i++) { + if (kgsl_cmdstream_check_timestamp(device_id, timestamp)) + return 1; + udelay(10); + } + return 0; +} + +int +kgsl_yamato_waittimestamp(gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout) +{ +#if defined GSL_RB_TIMESTAMP_INTERUPT +#ifndef _LINUX + return kos_event_wait( device->timestamp_event, timeout ); +#else + int status = wait_event_interruptible_timeout(device->timestamp_waitq, + kgsl_yamato_check_timestamp(device->id, timestamp), + msecs_to_jiffies(timeout)); + if (status > 0) + return GSL_SUCCESS; + else + return GSL_FAILURE; +#endif +#else + return (GSL_SUCCESS); +#endif +} +//---------------------------------------------------------------------------- + +int +kgsl_yamato_runpending(gsl_device_t *device) +{ + (void) device; + + return (GSL_SUCCESS); +} + +//---------------------------------------------------------------------------- + +int +kgsl_yamato_getfunctable(gsl_functable_t *ftbl) +{ + ftbl->device_init = kgsl_yamato_init; + ftbl->device_close = kgsl_yamato_close; + ftbl->device_destroy = kgsl_yamato_destroy; + ftbl->device_start = kgsl_yamato_start; + ftbl->device_stop = kgsl_yamato_stop; + ftbl->device_getproperty = kgsl_yamato_getproperty; + ftbl->device_setproperty = kgsl_yamato_setproperty; + ftbl->device_idle = kgsl_yamato_idle; + ftbl->device_waittimestamp = kgsl_yamato_waittimestamp; + ftbl->device_regread = kgsl_yamato_regread; + ftbl->device_regwrite = kgsl_yamato_regwrite; + ftbl->device_waitirq = kgsl_yamato_waitirq; + ftbl->device_runpending = kgsl_yamato_runpending; + ftbl->intr_isr = kgsl_yamato_isr; + ftbl->mmu_tlbinvalidate = kgsl_yamato_tlbinvalidate; + ftbl->mmu_setpagetable = kgsl_yamato_setpagetable; + ftbl->cmdstream_issueibcmds = kgsl_ringbuffer_issueibcmds; + ftbl->context_create = kgsl_drawctxt_create; + ftbl->context_destroy = kgsl_drawctxt_destroy; + + return (GSL_SUCCESS); +} + +#endif + diff --git a/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl new file mode 100644 index 000000000000..dfe61295e9ef --- /dev/null +++ b/drivers/mxc/amd-gpu/common/pfp_microcode_nrt.inl @@ -0,0 +1,327 @@ +/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of QUALCOMM Incorporated nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef PFP_MICROCODE_NRT_H +#define PFP_MICROCODE_NRT_H + +#define PFP_MICROCODE_VERSION 308308 + +#define PFP_MICROCODE_SIZE_NRT 288 + +uint32 aPFP_Microcode_nrt[PFP_MICROCODE_SIZE_NRT]={ +0xc60400, +0x7e424b, +0xa00000, +0x7e828b, +0x800001, +0xc60400, +0xcc4003, +0x800000, +0xd60003, +0x800000, +0xc62c00, +0xc80c35, +0x98c000, +0xc80c35, +0x880000, +0xc80c1d, +0x84000b, +0xc60800, +0x98c007, +0xc61000, +0x978003, +0xcc4003, +0xd60004, +0x800000, +0xcd0003, +0x9783e8, +0xc60400, +0x800000, +0xc60400, +0x84000b, +0xc60800, +0x98c00c, +0xc61000, +0xcc4003, +0xc61400, +0xc61800, +0x7d6d40, +0xcd401e, +0x978003, +0xcd801e, +0xd60004, +0x800000, +0xcd0003, +0x800000, +0xd6001f, +0x84000b, +0xc60800, +0x98c007, +0xc60c00, +0xcc4003, +0xcc8003, +0xccc003, +0x800000, +0xd60003, +0x800000, +0xd6001f, +0xc60800, +0x348c08, +0x98c006, +0xc80c1e, +0x98c000, +0xc80c1e, +0x800041, +0xcc8007, +0xcc8008, +0xcc4003, +0x800000, +0xcc8003, +0xc60400, +0x1a9c07, +0xca8821, +0x95c3b9, +0xc8102c, +0x98800a, +0x329418, +0x9a4004, +0xcc6810, +0x042401, +0xd00143, +0xd00162, +0xcd0002, +0x7d514c, +0xcd4003, +0x9b8007, +0x06a801, +0x964003, +0xc28000, +0xcf4003, +0x800001, +0xc60400, +0x800045, +0xc60400, +0x800001, +0xc60400, +0xc60800, +0xc60c00, +0xc8102d, +0x349402, +0x99000b, +0xc8182e, +0xcd4002, +0xcd8002, +0xd001e3, +0xd001c3, +0xccc003, +0xcc801c, +0xcd801d, +0x800001, +0xc60400, +0xd00203, +0x800000, +0xd001c3, +0xc8081f, +0xc60c00, +0xc80c20, +0x988000, +0xc8081f, +0xcc4003, +0xccc003, +0xd60003, +0xccc022, +0xcc001f, +0x800000, +0xcc001f, +0xc81c2f, +0xc60400, +0xc60800, +0xc60c00, +0xc81030, +0x99c000, +0xc81c2f, +0xcc8021, +0xcc4020, +0x990011, +0xc107ff, +0xd00223, +0xd00243, +0x345402, +0x7cb18b, +0x7d95cc, +0xcdc002, +0xccc002, +0xd00263, +0x978005, +0xccc003, +0xc60800, +0x80008a, +0xc60c00, +0x800000, +0xd00283, +0x97836b, +0xc60400, +0xd6001f, +0x800001, +0xc60400, +0xd2000d, +0xcc000d, +0x800000, +0xcc000d, +0xc60800, +0xc60c00, +0xca1433, +0xd022a0, +0xcce000, +0x99435c, +0xcce005, +0x800000, +0x062001, +0xc60800, +0xc60c00, +0xd202c3, +0xcc8003, +0xccc003, +0xcce027, +0x800000, +0x062001, +0xca0831, +0x9883ff, +0xca0831, +0xd6001f, +0x800001, +0xc60400, +0x0a2001, +0x800001, +0xc60400, +0xd20009, +0xd2000a, +0xcc001f, +0x800000, +0xcc001f, +0xd2000b, +0xd2000c, +0xcc001f, +0x800000, +0xcc001f, +0xcc0023, +0xcc4003, +0xce0003, +0x800000, +0xd60003, +0xd00303, +0xcc0024, +0xcc4003, +0x800000, +0xd60003, +0xd00323, +0xcc0025, +0xcc4003, +0x800000, +0xd60003, +0xd00343, +0xcc0026, +0xcc4003, +0x800000, +0xd60003, +0x800000, +0xd6001f, +0x280401, +0xd20001, +0xcc4001, +0xcc4006, +0x8400e7, +0xc40802, +0xc40c02, +0xcc402b, +0x98831f, +0xc63800, +0x8400e7, +0xcf802b, +0x800000, +0xd6001f, +0xcc001f, +0x880000, +0xcc001f, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x000000, +0x0100c8, +0x0200cd, +0x0300d2, +0x050004, +0x1000d7, +0x1700b6, +0x220010, +0x230038, +0x250044, +0x27005e, +0x2d0070, +0x2e007c, +0x4b0009, +0x34001d, +0x36002d, +0x3700a8, +0x3b009b, +0x3f009f, +0x4400d9, +0x4800c3, +0x5000b9, +0x5100be, +0x5500c9, +0x5600ce, +0x5700d3, +0x5d00b0, +0x000006, +0x000006, +0x000006, +0x000006, +0x000006, +0x000006, +}; + +#endif diff --git a/drivers/mxc/amd-gpu/common/pm4_microcode.inl b/drivers/mxc/amd-gpu/common/pm4_microcode.inl new file mode 100644 index 000000000000..03f6f4cd35e4 --- /dev/null +++ b/drivers/mxc/amd-gpu/common/pm4_microcode.inl @@ -0,0 +1,815 @@ +/* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of QUALCOMM Incorporated nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef PM4_MICROCODE_H +#define PM4_MICROCODE_H + +#define PM4_MICROCODE_VERSION 300684 + +#define PM4_MICROCODE_SIZE 768 + + +#ifdef _PRIMLIB_INCLUDE +extern uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]; +#else +uint32 aPM4_Microcode[PM4_MICROCODE_SIZE][3]={ + { 0x00000000, 0xc0200400, 0x000 }, + { 0x00000000, 0x00a0000a, 0x000 }, + { 0x000001f3, 0x00204411, 0x000 }, + { 0x01000000, 0x00204811, 0x000 }, + { 0x00000000, 0x00400000, 0x004 }, + { 0x0000ffff, 0x00284621, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x34e00000, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x0000ffff, 0xc0280a20, 0x000 }, + { 0x00000000, 0x00294582, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x0000ffff, 0xc0284620, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x00600000, 0x2a8 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x000021fc, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404803, 0x021 }, + { 0x00000000, 0x00600000, 0x2a8 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x000021fc, 0x0029462c, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00003fff, 0x002f022f, 0x000 }, + { 0x00000000, 0x0ce00000, 0x000 }, + { 0x0000a1fd, 0x0029462c, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x021 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00001000, 0x00281223, 0x000 }, + { 0x00001000, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ce00000, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x0000000e, 0x00404811, 0x000 }, + { 0x00000394, 0x00204411, 0x000 }, + { 0x00000001, 0xc0404811, 0x000 }, + { 0x00000000, 0x00600000, 0x2a8 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000008, 0xc0210a20, 0x000 }, + { 0x00000000, 0x14e00000, 0x02d }, + { 0x00000007, 0x00404811, 0x000 }, + { 0x00000008, 0x00404811, 0x000 }, + { 0x0000001f, 0x40280a20, 0x000 }, + { 0x0000001b, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x043 }, + { 0x00000002, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x04a }, + { 0x00000003, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x051 }, + { 0x00000004, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x058 }, + { 0x00000014, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x058 }, + { 0x00000015, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x060 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0xc0404802, 0x000 }, + { 0x0000001f, 0x40280a20, 0x000 }, + { 0x0000001b, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x043 }, + { 0x00000002, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x04a }, + { 0x00000000, 0x00400000, 0x051 }, + { 0x0000001f, 0xc0210e20, 0x000 }, + { 0x00000612, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x0000001e, 0xc0210e20, 0x000 }, + { 0x00000600, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x0000001e, 0xc0210e20, 0x000 }, + { 0x00000605, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x0000001f, 0x40280a20, 0x000 }, + { 0x0000001f, 0xc0210e20, 0x000 }, + { 0x0000060a, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x0000001f, 0xc0680a20, 0x2a8 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000000, 0x00404802, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00001fff, 0x40280a20, 0x000 }, + { 0x80000000, 0x40280e20, 0x000 }, + { 0x40000000, 0xc0281220, 0x000 }, + { 0x00040000, 0x00694622, 0x2b2 }, + { 0x00000000, 0x00201410, 0x000 }, + { 0x00000000, 0x002f0223, 0x000 }, + { 0x00000000, 0x0ae00000, 0x06d }, + { 0x00000000, 0xc0401800, 0x070 }, + { 0x00001fff, 0xc0281a20, 0x000 }, + { 0x00040000, 0x00694626, 0x2b2 }, + { 0x00000000, 0x00201810, 0x000 }, + { 0x00000000, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x073 }, + { 0x00000000, 0xc0401c00, 0x076 }, + { 0x00001fff, 0xc0281e20, 0x000 }, + { 0x00040000, 0x00694627, 0x2b2 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x00204402, 0x000 }, + { 0x00000000, 0x002820c5, 0x000 }, + { 0x00000000, 0x004948e8, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x00000010, 0x40210a20, 0x000 }, + { 0x000000ff, 0x00280a22, 0x000 }, + { 0x000007ff, 0x40280e20, 0x000 }, + { 0x00000002, 0x00221e23, 0x000 }, + { 0x00000005, 0xc0211220, 0x000 }, + { 0x00080000, 0x00281224, 0x000 }, + { 0x00000013, 0x00210224, 0x000 }, + { 0x00000000, 0x14c00000, 0x084 }, + { 0xa100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x088 }, + { 0x00000000, 0x0020162d, 0x000 }, + { 0x00004000, 0x00500e23, 0x097 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x08c }, + { 0x00000001, 0x0020162d, 0x000 }, + { 0x00004800, 0x00500e23, 0x097 }, + { 0x00000002, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x090 }, + { 0x00000003, 0x0020162d, 0x000 }, + { 0x00004900, 0x00500e23, 0x097 }, + { 0x00000003, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x094 }, + { 0x00000002, 0x0020162d, 0x000 }, + { 0x00004908, 0x00500e23, 0x097 }, + { 0x00000012, 0x0020162d, 0x000 }, + { 0x00002000, 0x00300e23, 0x000 }, + { 0x00000000, 0x00290d83, 0x000 }, + { 0x9400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002948e5, 0x000 }, + { 0x00000000, 0x00294483, 0x000 }, + { 0x00000000, 0x40201800, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000013, 0x00210224, 0x000 }, + { 0x00000000, 0x14c00000, 0x000 }, + { 0x9400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002948e5, 0x000 }, + { 0x9300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404806, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x0000001f, 0x00211a25, 0x000 }, + { 0x00000000, 0x14e00000, 0x000 }, + { 0x000007ff, 0x00280e25, 0x000 }, + { 0x00000010, 0x00211225, 0x000 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0ae }, + { 0x00000000, 0x00203622, 0x000 }, + { 0x00004000, 0x00504a23, 0x0bd }, + { 0x00000001, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0b2 }, + { 0x00000001, 0x00203622, 0x000 }, + { 0x00004800, 0x00504a23, 0x0bd }, + { 0x00000002, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0b6 }, + { 0x00000003, 0x00203622, 0x000 }, + { 0x00004900, 0x00504a23, 0x0bd }, + { 0x00000003, 0x002f0224, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0ba }, + { 0x00000002, 0x00203622, 0x000 }, + { 0x00004908, 0x00504a23, 0x0bd }, + { 0x00000012, 0x00203622, 0x000 }, + { 0x00000000, 0x00290d83, 0x000 }, + { 0x00002000, 0x00304a23, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, + { 0x00000000, 0x00400000, 0x0a4 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00040578, 0x00604411, 0x2b2 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x00000000, 0xc0201800, 0x000 }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x0cd }, + { 0x00000000, 0xc0201c00, 0x000 }, + { 0x00000000, 0x17000000, 0x000 }, + { 0x00000010, 0x00280a23, 0x000 }, + { 0x00000010, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x0d5 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00040000, 0x00694624, 0x2b2 }, + { 0x00000000, 0x00400000, 0x0d6 }, + { 0x00000000, 0x00600000, 0x135 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000007, 0x00280a23, 0x000 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0dd }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x04e00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000002, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0e2 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x02e00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000003, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0e7 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x0ce00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000004, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0ec }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000005, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0f1 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x06e00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00000006, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x0f6 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x08e00000, 0x0f6 }, + { 0x00000000, 0x00400000, 0x0fd }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x000 }, + { 0x00000008, 0x00210a23, 0x000 }, + { 0x00000000, 0x14e00000, 0x11b }, + { 0x00000000, 0xc0204400, 0x000 }, + { 0x00000000, 0xc0404800, 0x000 }, + { 0x00007f00, 0x00280a21, 0x000 }, + { 0x00004500, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x102 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000000, 0x00404c07, 0x0cd }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x00000000, 0xc0201800, 0x000 }, + { 0x00000000, 0xc0201c00, 0x000 }, + { 0x00000000, 0x17000000, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00040000, 0x00694624, 0x2b2 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x0ce00000, 0x000 }, + { 0x00000000, 0x00404c07, 0x107 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x00000000, 0xc0201400, 0x000 }, + { 0x00000000, 0xc0201800, 0x000 }, + { 0x00000000, 0xc0201c00, 0x000 }, + { 0x00000000, 0x17000000, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00040000, 0x00694624, 0x2b2 }, + { 0x00000000, 0x002820d0, 0x000 }, + { 0x00000000, 0x002f00a8, 0x000 }, + { 0x00000000, 0x06e00000, 0x000 }, + { 0x00000000, 0x00404c07, 0x113 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x0000860e, 0x00204411, 0x000 }, + { 0x00000000, 0xd9004800, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000009, 0x00204811, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0x00404810, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00007fff, 0x00281a22, 0x000 }, + { 0x00040000, 0x00694626, 0x2b2 }, + { 0x00000000, 0x00200c10, 0x000 }, + { 0x00000000, 0xc0201000, 0x000 }, + { 0x80000000, 0x00281a22, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, + { 0x00000000, 0x0ce00000, 0x132 }, + { 0x00000000, 0x00600000, 0x135 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x00300c67, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0x00404803, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0xa400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x000001ea, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0x1ac00000, 0x13b }, + { 0x9e00ffff, 0x00204411, 0x000 }, + { 0xdeadbeef, 0x00204811, 0x000 }, + { 0x00000000, 0x1ae00000, 0x13e }, + { 0xa400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x0080480b, 0x000 }, + { 0x000001f3, 0x00204411, 0x000 }, + { 0xe0000000, 0xc0484a20, 0x000 }, + { 0x00000000, 0xd9000000, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x8c00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000fff, 0x00281223, 0x000 }, + { 0x0000000f, 0x00203624, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00301224, 0x000 }, + { 0x0000000e, 0x00203624, 0x000 }, + { 0x8700ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000001, 0x00331224, 0x000 }, + { 0x8600ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x0000001d, 0x00211223, 0x000 }, + { 0x00000020, 0x00222091, 0x000 }, + { 0x00000003, 0x00381228, 0x000 }, + { 0x8800ffff, 0x00204411, 0x000 }, + { 0x00004fff, 0x00304a24, 0x000 }, + { 0x00000010, 0x00211623, 0x000 }, + { 0x00000fff, 0x00281625, 0x000 }, + { 0x00000fff, 0x00281a23, 0x000 }, + { 0x00000000, 0x00331ca6, 0x000 }, + { 0x8f00ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00000010, 0x00211223, 0x000 }, + { 0x00000fff, 0x00281224, 0x000 }, + { 0x0000000d, 0x00203624, 0x000 }, + { 0x8b00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00301224, 0x000 }, + { 0x0000000c, 0x00203624, 0x000 }, + { 0x8500ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0x00331cc8, 0x000 }, + { 0x9000ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00300000, 0x00493a2e, 0x000 }, + { 0x00000000, 0x00202c11, 0x000 }, + { 0x00000001, 0x00303e2f, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x172 }, + { 0x00000000, 0xd9000000, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x002f0230, 0x000 }, + { 0x00000000, 0x0ae00000, 0x175 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00000009, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x17d }, + { 0x00000000, 0x00600000, 0x2af }, + { 0x00000000, 0x00200c11, 0x000 }, + { 0x00000016, 0x00203623, 0x000 }, + { 0x00000000, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x180 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000001, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x183 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000002, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x18d }, + { 0x00000004, 0xc0203620, 0x000 }, + { 0x00000005, 0xc0203620, 0x000 }, + { 0x00000006, 0xc0203620, 0x000 }, + { 0x00000007, 0xc0203620, 0x000 }, + { 0x00000008, 0xc0203620, 0x000 }, + { 0x00000009, 0xc0203620, 0x000 }, + { 0x0000000a, 0xc0203620, 0x000 }, + { 0x0000000b, 0xc0203620, 0x000 }, + { 0x00000003, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1b5 }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x8c00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000fff, 0x00281223, 0x000 }, + { 0x0000000f, 0x00203624, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00301224, 0x000 }, + { 0x0000000e, 0x00203624, 0x000 }, + { 0x8700ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000001, 0x00331224, 0x000 }, + { 0x8600ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x0000001d, 0x00211223, 0x000 }, + { 0x00000020, 0x00222091, 0x000 }, + { 0x00000003, 0x00381228, 0x000 }, + { 0x8800ffff, 0x00204411, 0x000 }, + { 0x00004fff, 0x00304a24, 0x000 }, + { 0x00000010, 0x00211623, 0x000 }, + { 0x00000fff, 0x00281625, 0x000 }, + { 0x00000fff, 0x00281a23, 0x000 }, + { 0x00000000, 0x00331ca6, 0x000 }, + { 0x8f00ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00000010, 0x00211223, 0x000 }, + { 0x00000fff, 0x00281224, 0x000 }, + { 0x0000000d, 0x00203624, 0x000 }, + { 0x8b00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00301224, 0x000 }, + { 0x0000000c, 0x00203624, 0x000 }, + { 0x8500ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204804, 0x000 }, + { 0x00000000, 0x00331cc8, 0x000 }, + { 0x9000ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00384a27, 0x000 }, + { 0x00300000, 0x00293a2e, 0x000 }, + { 0x00000004, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1bd }, + { 0xa300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x40204800, 0x000 }, + { 0x0000000a, 0xc0220e20, 0x000 }, + { 0x00000011, 0x00203623, 0x000 }, + { 0x000021f4, 0x00204411, 0x000 }, + { 0x0000000a, 0x00614a2c, 0x2af }, + { 0x00000005, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1c0 }, + { 0x00000000, 0xc0200000, 0x000 }, + { 0x00000006, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1c6 }, + { 0x9c00ffff, 0x00204411, 0x000 }, + { 0x0000001f, 0x40214a20, 0x000 }, + { 0x9600ffff, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000007, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1d0 }, + { 0x3fffffff, 0x00283a2e, 0x000 }, + { 0xc0000000, 0x40280e20, 0x000 }, + { 0x00000000, 0x0029386e, 0x000 }, + { 0x18000000, 0x40280e20, 0x000 }, + { 0x00000016, 0x00203623, 0x000 }, + { 0xa400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0xc0202c00, 0x000 }, + { 0x00000000, 0x0020480b, 0x000 }, + { 0x00000008, 0x00210222, 0x000 }, + { 0x00000000, 0x14c00000, 0x1dc }, + { 0x00000000, 0xc0200c00, 0x000 }, + { 0x00000013, 0x00203623, 0x000 }, + { 0x00000015, 0x00203623, 0x000 }, + { 0x00000002, 0x40221220, 0x000 }, + { 0x00000000, 0x00301083, 0x000 }, + { 0x00000014, 0x00203624, 0x000 }, + { 0x00000003, 0xc0210e20, 0x000 }, + { 0x10000000, 0x00280e23, 0x000 }, + { 0xefffffff, 0x00283a2e, 0x000 }, + { 0x00000000, 0x0029386e, 0x000 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x00600000, 0x28c }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x0000001f, 0x00210e22, 0x000 }, + { 0x00000000, 0x14e00000, 0x000 }, + { 0x000003ff, 0x00280e22, 0x000 }, + { 0x00000018, 0x00211222, 0x000 }, + { 0x00000004, 0x00301224, 0x000 }, + { 0x00000000, 0x0020108d, 0x000 }, + { 0x00002000, 0x00291224, 0x000 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00294984, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, + { 0x00000000, 0x00400000, 0x1de }, + { 0x8200ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000000, 0xc0200800, 0x000 }, + { 0x00003fff, 0x40280e20, 0x000 }, + { 0x00000010, 0xc0211220, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x1fb }, + { 0x00000000, 0x2ae00000, 0x205 }, + { 0x20000080, 0x00281e2e, 0x000 }, + { 0x00000080, 0x002f0227, 0x000 }, + { 0x00000000, 0x0ce00000, 0x1f8 }, + { 0x00000000, 0x00401c0c, 0x1f9 }, + { 0x00000010, 0x00201e2d, 0x000 }, + { 0x000021f9, 0x00294627, 0x000 }, + { 0x00000000, 0x00404811, 0x205 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x23a }, + { 0x00000000, 0x28e00000, 0x205 }, + { 0x00800080, 0x00281e2e, 0x000 }, + { 0x00000080, 0x002f0227, 0x000 }, + { 0x00000000, 0x0ce00000, 0x202 }, + { 0x00000000, 0x00401c0c, 0x203 }, + { 0x00000010, 0x00201e2d, 0x000 }, + { 0x000021f9, 0x00294627, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x20c }, + { 0x00000003, 0x00204811, 0x000 }, + { 0x0000000c, 0x0020162d, 0x000 }, + { 0x0000000d, 0x00201a2d, 0x000 }, + { 0xffdfffff, 0x00483a2e, 0x210 }, + { 0x00000004, 0x00204811, 0x000 }, + { 0x0000000e, 0x0020162d, 0x000 }, + { 0x0000000f, 0x00201a2d, 0x000 }, + { 0xffefffff, 0x00283a2e, 0x000 }, + { 0x00000000, 0x00201c10, 0x000 }, + { 0x00000000, 0x002f0067, 0x000 }, + { 0x00000000, 0x04e00000, 0x205 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000006, 0x00204811, 0x000 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204805, 0x000 }, + { 0x8900ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204806, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, + { 0x00000000, 0x00601010, 0x28c }, + { 0x0000000c, 0x00221e24, 0x000 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x22d }, + { 0x20000000, 0x00293a2e, 0x000 }, + { 0x000021f7, 0x0029462c, 0x000 }, + { 0x00000000, 0x002948c7, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000005, 0x00204811, 0x000 }, + { 0x0000000c, 0x00203630, 0x000 }, + { 0x00000007, 0x00204811, 0x000 }, + { 0x0000000d, 0x00203630, 0x000 }, + { 0x9100ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x23000000, 0x000 }, + { 0x8d00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404803, 0x240 }, + { 0x00800000, 0x00293a2e, 0x000 }, + { 0x000021f6, 0x0029462c, 0x000 }, + { 0x00000000, 0x002948c7, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000005, 0x00204811, 0x000 }, + { 0x0000000e, 0x00203630, 0x000 }, + { 0x00000007, 0x00204811, 0x000 }, + { 0x0000000f, 0x00203630, 0x000 }, + { 0x9200ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x25000000, 0x000 }, + { 0x8e00ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404803, 0x240 }, + { 0x8300ffff, 0x00204411, 0x000 }, + { 0x00000003, 0x00381224, 0x000 }, + { 0x00005000, 0x00304a24, 0x000 }, + { 0x8400ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x00000000, 0x21000000, 0x000 }, + { 0x8200ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00404811, 0x000 }, + { 0x00000003, 0x40280a20, 0x000 }, + { 0xffffffe0, 0xc0280e20, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x24a }, + { 0x000021f6, 0x0029122c, 0x000 }, + { 0x00040000, 0x00494624, 0x24c }, + { 0x000021f7, 0x0029122c, 0x000 }, + { 0x00040000, 0x00294624, 0x000 }, + { 0x00000000, 0x00600000, 0x2b2 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x252 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ce00000, 0x252 }, + { 0x00000000, 0x00481630, 0x258 }, + { 0x00000fff, 0x00281630, 0x000 }, + { 0x0000000c, 0x00211a30, 0x000 }, + { 0x00000fff, 0x00281a26, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, + { 0x00000000, 0x0ae00000, 0x258 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00040d02, 0x00604411, 0x2b2 }, + { 0x00000000, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x25d }, + { 0x00000010, 0x00211e30, 0x000 }, + { 0x00000fff, 0x00482630, 0x267 }, + { 0x00000001, 0x002f0222, 0x000 }, + { 0x00000000, 0x0ae00000, 0x261 }, + { 0x00000fff, 0x00281e30, 0x000 }, + { 0x00000200, 0x00402411, 0x267 }, + { 0x00000000, 0x00281e30, 0x000 }, + { 0x00000010, 0x00212630, 0x000 }, + { 0x00000010, 0x00211a30, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, + { 0x00000000, 0x0ae00000, 0x258 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000003, 0x00381625, 0x000 }, + { 0x00000003, 0x00381a26, 0x000 }, + { 0x00000003, 0x00381e27, 0x000 }, + { 0x00000003, 0x00382629, 0x000 }, + { 0x00005000, 0x00302629, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0xc0204800, 0x000 }, + { 0x00000000, 0x00204806, 0x000 }, + { 0x00005000, 0x00302225, 0x000 }, + { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00202810, 0x000 }, + { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00200810, 0x000 }, + { 0x00040000, 0x00694628, 0x2b2 }, + { 0x00000001, 0x00302228, 0x000 }, + { 0x00000000, 0x00201410, 0x000 }, + { 0x0000060d, 0x00204411, 0x000 }, + { 0x00000000, 0x00204803, 0x000 }, + { 0x0000860e, 0x00204411, 0x000 }, + { 0x00000000, 0x0020480a, 0x000 }, + { 0x00000000, 0x00204802, 0x000 }, + { 0x00000000, 0x00204805, 0x000 }, + { 0x00000000, 0x002f0128, 0x000 }, + { 0x00000000, 0x0ae00000, 0x282 }, + { 0x00005000, 0x00302227, 0x000 }, + { 0x0000000c, 0x00300e23, 0x000 }, + { 0x00000003, 0x00331a26, 0x000 }, + { 0x00000000, 0x002f0226, 0x000 }, + { 0x00000000, 0x0ae00000, 0x270 }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x000001f3, 0x00204411, 0x000 }, + { 0x04000000, 0x00204811, 0x000 }, + { 0x00000000, 0x00400000, 0x289 }, + { 0x00000000, 0xc0600000, 0x28c }, + { 0x00000000, 0x00400000, 0x000 }, + { 0x00000000, 0x0ec00000, 0x28e }, + { 0x00000000, 0x00800000, 0x000 }, + { 0x000021f9, 0x0029462c, 0x000 }, + { 0x00000005, 0x00204811, 0x000 }, + { 0x00000000, 0x0020280c, 0x000 }, + { 0x00000011, 0x0020262d, 0x000 }, + { 0x00000000, 0x002f012c, 0x000 }, + { 0x00000000, 0x0ae00000, 0x295 }, + { 0x00000000, 0x00403011, 0x296 }, + { 0x00000400, 0x0030322c, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x0000000a, 0x0021262c, 0x000 }, + { 0x00000000, 0x00210130, 0x000 }, + { 0x00000000, 0x14c00000, 0x29d }, + { 0xa500ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00404811, 0x299 }, + { 0xa500ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x000021f4, 0x0029462c, 0x000 }, + { 0x0000000a, 0x00214a2a, 0x000 }, + { 0xa200ffff, 0x00204411, 0x000 }, + { 0x00000001, 0x00204811, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x00210130, 0x000 }, + { 0xdf7fffff, 0x00283a2e, 0x000 }, + { 0x00000010, 0x0080362a, 0x000 }, + { 0x9700ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x0020480c, 0x000 }, + { 0xa200ffff, 0x00204411, 0x000 }, + { 0x00000000, 0x00204811, 0x000 }, + { 0x8100ffff, 0x00204411, 0x000 }, + { 0x00000002, 0x00204811, 0x000 }, + { 0x00000000, 0x00810130, 0x000 }, + { 0x00000000, 0x00203011, 0x000 }, + { 0x00000010, 0x0080362c, 0x000 }, + { 0x00000000, 0xc0400000, 0x000 }, + { 0x00000000, 0x1ac00000, 0x2b2 }, + { 0x9f00ffff, 0x00204411, 0x000 }, + { 0xdeadbeef, 0x00204811, 0x000 }, + { 0x00000000, 0x1ae00000, 0x2b5 }, + { 0x00000000, 0x00800000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00000000, 0x00000000, 0x000 }, + { 0x00020143, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x01dd0002, 0x000 }, + { 0x006301ee, 0x00280012, 0x000 }, + { 0x00020002, 0x00020026, 0x000 }, + { 0x00020002, 0x01ec0002, 0x000 }, + { 0x00790242, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00200012, 0x00020016, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x011b00c5, 0x00020125, 0x000 }, + { 0x00020141, 0x00020002, 0x000 }, + { 0x00c50002, 0x0143002e, 0x000 }, + { 0x00a2016b, 0x00020145, 0x000 }, + { 0x00020002, 0x01200002, 0x000 }, + { 0x00020002, 0x010f0103, 0x000 }, + { 0x00090002, 0x000e000e, 0x000 }, + { 0x0058003d, 0x00600002, 0x000 }, + { 0x000200c1, 0x0002028a, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x00020002, 0x00020002, 0x000 }, + { 0x000502b1, 0x00020008, 0x000 }, +}; + +#endif +static const uint32 ME_JUMP_TABLE_START = 740; +static const uint32 ME_JUMP_TABLE_END = 768; + +#endif diff --git a/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h new file mode 100644 index 000000000000..7ec10b0c2556 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_displayapi.h @@ -0,0 +1,86 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DISPLAYAPI_H +#define __GSL_DISPLAYAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +////////////////////////////////////////////////////////////////////////////// +// entrypoints +////////////////////////////////////////////////////////////////////////////// +#ifdef __GSLDISPLAY_EXPORTS +#define DISP_API OS_DLLEXPORT +#else +#define DISP_API OS_DLLIMPORT +#endif // __GSLDISPLAY_EXPORTS + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_DISPLAY_PANEL_TOSHIBA_640x480 0 +#define GSL_DISPLAY_PANEL_HITACHI_240x320 1 +#define GSL_DISPLAY_PANEL_DEFAULT GSL_DISPLAY_PANEL_TOSHIBA_640x480 + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// +typedef int gsl_display_id_t; +typedef int gsl_surface_id_t; + +typedef struct _gsl_displaymode_t { + int panel_id; + int width; + int height; + int bpp; + int orientation; + int frequency; +} gsl_displaymode_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +DISP_API gsl_display_id_t gsl_display_open(gsl_devhandle_t devhandle, int panel_id); +DISP_API int gsl_display_close(gsl_display_id_t display_id); +DISP_API int gsl_display_getcount(void); +DISP_API int gsl_display_setmode(gsl_display_id_t display_id, gsl_displaymode_t displaymode); +DISP_API int gsl_display_getmode(gsl_display_id_t display_id, gsl_displaymode_t *displaymode); +DISP_API gsl_surface_id_t gsl_display_setsurface(gsl_display_id_t display_id, void *buffer); +DISP_API int gsl_display_getactivesurface(gsl_display_id_t display_id, void **buffer); +DISP_API int gsl_display_flipsurface(gsl_display_id_t display_id, gsl_surface_id_t surface_id); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __GSL_DISPLAYAPI_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h new file mode 100644 index 000000000000..3c08545c2b68 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_klibapi.h @@ -0,0 +1,136 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_KLIBAPI_H +#define __GSL_KLIBAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "gsl_types.h" +#include "gsl_properties.h" + + +////////////////////////////////////////////////////////////////////////////// +// entrypoints +////////////////////////////////////////////////////////////////////////////// +#ifdef __KGSLLIB_EXPORTS +#define KGSL_API OS_DLLEXPORT +#else +#ifdef __KERNEL_MODE__ +#define KGSL_API extern +#else +#define KGSL_API OS_DLLIMPORT +#endif +#endif // __KGSLLIB_EXPORTS + + +////////////////////////////////////////////////////////////////////////////// +// version control +////////////////////////////////////////////////////////////////////////////// +#define KGSLLIB_NAME "AMD GSL Kernel Library" +#define KGSLLIB_VERSION "0.1" + + +////////////////////////////////////////////////////////////////////////////// +// library API +////////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_driver_init(void); +KGSL_API int kgsl_driver_close(void); +KGSL_API int kgsl_driver_entry(gsl_flags_t flags); +KGSL_API int kgsl_driver_exit(void); +KGSL_API int kgsl_driver_destroy(unsigned int pid); + + +//////////////////////////////////////////////////////////////////////////// +// device API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_device_start(gsl_deviceid_t device_id, gsl_flags_t flags); +KGSL_API int kgsl_device_stop(gsl_deviceid_t device_id); +KGSL_API int kgsl_device_idle(gsl_deviceid_t device_id, unsigned int timeout); +KGSL_API int kgsl_device_isidle(gsl_deviceid_t device_id); +KGSL_API int kgsl_device_getproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes); +KGSL_API int kgsl_device_setproperty(gsl_deviceid_t device_id, gsl_property_type_t type, void *value, unsigned int sizebytes); +KGSL_API int kgsl_device_regread(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int *value); +KGSL_API int kgsl_device_regwrite(gsl_deviceid_t device_id, unsigned int offsetwords, unsigned int value); +KGSL_API int kgsl_device_waitirq(gsl_deviceid_t device_id, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout); + + +//////////////////////////////////////////////////////////////////////////// +// command API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_cmdstream_issueibcmds(gsl_deviceid_t device_id, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags); +KGSL_API gsl_timestamp_t kgsl_cmdstream_readtimestamp(gsl_deviceid_t device_id, gsl_timestamp_type_t type); +KGSL_API int kgsl_cmdstream_freememontimestamp(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type); +KGSL_API int kgsl_cmdstream_waittimestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp, unsigned int timeout); +KGSL_API int kgsl_cmdwindow_write(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data); +KGSL_API int kgsl_add_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t *timestamp); +KGSL_API int kgsl_cmdstream_check_timestamp(gsl_deviceid_t device_id, gsl_timestamp_t timestamp); + +//////////////////////////////////////////////////////////////////////////// +// context API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_context_create(gsl_deviceid_t device_id, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags); +KGSL_API int kgsl_context_destroy(gsl_deviceid_t device_id, unsigned int drawctxt_id); +KGSL_API int kgsl_drawctxt_bind_gmem_shadow(gsl_deviceid_t device_id, unsigned int drawctxt_id, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id); + + +//////////////////////////////////////////////////////////////////////////// +// sharedmem API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_sharedmem_alloc(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc); +KGSL_API int kgsl_sharedmem_free(gsl_memdesc_t *memdesc); +KGSL_API int kgsl_sharedmem_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace); +KGSL_API int kgsl_sharedmem_write(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace); +KGSL_API int kgsl_sharedmem_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes); +KGSL_API unsigned int kgsl_sharedmem_largestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags); +KGSL_API int kgsl_sharedmem_map(gsl_deviceid_t device_id, gsl_flags_t flags, const gsl_scatterlist_t *scatterlist, gsl_memdesc_t *memdesc); +KGSL_API int kgsl_sharedmem_unmap(gsl_memdesc_t *memdesc); +KGSL_API int kgsl_sharedmem_getmap(const gsl_memdesc_t *memdesc, gsl_scatterlist_t *scatterlist); +KGSL_API int kgsl_sharedmem_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation); +KGSL_API int kgsl_sharedmem_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr); + + +//////////////////////////////////////////////////////////////////////////// +// interrupt API +//////////////////////////////////////////////////////////////////////////// +KGSL_API void kgsl_intr_isr(void); + + +//////////////////////////////////////////////////////////////////////////// +// TB dump API +//////////////////////////////////////////////////////////////////////////// +KGSL_API int kgsl_tbdump_waitirq(void); +KGSL_API int kgsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __GSL_KLIBAPI_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_libapi.h b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h new file mode 100644 index 000000000000..3d359e24f572 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_libapi.h @@ -0,0 +1,143 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_LIBAPI_H +#define __GSL_LIBAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "gsl_types.h" + +////////////////////////////////////////////////////////////////////////////// +// entrypoints +////////////////////////////////////////////////////////////////////////////// +#ifdef __GSLLIB_EXPORTS +#define GSL_API OS_DLLEXPORT +#else +#define GSL_API OS_DLLIMPORT +#endif // __GSLLIB_EXPORTS + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSLLIB_NAME "AMD GSL User Library" +#define GSLLIB_VERSION "0.1" + + +////////////////////////////////////////////////////////////////////////////// +// libary API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_library_open(gsl_flags_t flags); +GSL_API int gsl_library_close(void); + + +//////////////////////////////////////////////////////////////////////////// +// device API +//////////////////////////////////////////////////////////////////////////// +GSL_API gsl_devhandle_t gsl_device_open(gsl_deviceid_t device_id, gsl_flags_t flags); +GSL_API int gsl_device_close(gsl_devhandle_t devhandle); +GSL_API int gsl_device_idle(gsl_devhandle_t devhandle, unsigned int timeout); +GSL_API int gsl_device_isidle(gsl_devhandle_t devhandle); +GSL_API int gsl_device_getcount(void); +GSL_API int gsl_device_getinfo(gsl_devhandle_t devhandle, gsl_devinfo_t *devinfo); +GSL_API int gsl_device_setpowerstate(gsl_devhandle_t devhandle, gsl_flags_t flags); +GSL_API int gsl_device_setdmistate(gsl_devhandle_t devhandle, gsl_flags_t flags); +GSL_API int gsl_device_waitirq(gsl_devhandle_t devhandle, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout); +GSL_API int gsl_device_waittimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, unsigned int timeout); +GSL_API int gsl_device_addtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t *timestamp); + +////////////////////////////////////////////////////////////////////////////// +// direct register API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_register_read(gsl_devhandle_t devhandle, unsigned int offsetwords, unsigned int *data); + + +////////////////////////////////////////////////////////////////////////////// +// command API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_cp_issueibcommands(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, gpuaddr_t ibaddr, unsigned int sizewords, gsl_timestamp_t *timestamp, gsl_flags_t flags); +GSL_API gsl_timestamp_t gsl_cp_readtimestamp(gsl_devhandle_t devhandle, gsl_timestamp_type_t type); +GSL_API int gsl_cp_checktimestamp(gsl_devhandle_t devhandle, gsl_timestamp_t timestamp, gsl_timestamp_type_t type); +GSL_API int gsl_cp_freememontimestamp(gsl_devhandle_t devhandle, gsl_memdesc_t *memdesc, gsl_timestamp_t timestamp, gsl_timestamp_type_t type); +GSL_API int gsl_v3_issuecommand(gsl_devhandle_t devhandle, gsl_cmdwindow_t target, unsigned int addr, unsigned int data); + + +////////////////////////////////////////////////////////////////////////////// +// context API +////////////////////////////////////////////////////////////////////////////// +GSL_API gsl_ctxthandle_t gsl_context_create(gsl_devhandle_t devhandle, gsl_context_type_t type, gsl_flags_t flags); +GSL_API int gsl_context_destroy(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle); +GSL_API int gsl_context_bind_gmem_shadow(gsl_devhandle_t devhandle, gsl_ctxthandle_t ctxthandle, const gsl_rect_t* gmem_rect, unsigned int shadow_x, unsigned int shadow_y, const gsl_buffer_desc_t* shadow_buffer, unsigned int buffer_id); + + + +////////////////////////////////////////////////////////////////////////////// +// sharedmem API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_memory_alloc(gsl_deviceid_t device_id, unsigned int sizebytes, gsl_flags_t flags, gsl_memdesc_t *memdesc); +GSL_API int gsl_memory_free(gsl_memdesc_t *memdesc); +GSL_API int gsl_memory_read(const gsl_memdesc_t *memdesc, void *dst, unsigned int sizebytes, unsigned int offsetbytes); +GSL_API int gsl_memory_write(const gsl_memdesc_t *memdesc, void *src, unsigned int sizebytes, unsigned int offsetbytes); +GSL_API int gsl_memory_write_multiple(const gsl_memdesc_t *memdesc, void *src, unsigned int srcstridebytes, unsigned int dststridebytes, unsigned int blocksizebytes, unsigned int numblocks, unsigned int offsetbytes); +GSL_API unsigned int gsl_memory_getlargestfreeblock(gsl_deviceid_t device_id, gsl_flags_t flags); +GSL_API int gsl_memory_set(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes); +GSL_API int gsl_memory_cacheoperation(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int sizebytes, unsigned int operation); +GSL_API int gsl_memory_fromhostpointer(gsl_deviceid_t device_id, gsl_memdesc_t *memdesc, void* hostptr); + +#ifdef _DIRECT_MAPPED +GSL_API unsigned int gsl_sharedmem_gethostaddr(const gsl_memdesc_t *memdesc); +#endif // _DIRECT_MAPPED + +////////////////////////////////////////////////////////////////////////////// +// address translation API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_translate_physaddr(void* virtAddr, unsigned int* physAddr); + + +////////////////////////////////////////////////////////////////////////////// +// TB dump API +////////////////////////////////////////////////////////////////////////////// +GSL_API int gsl_tbdump_waitirq(); +GSL_API int gsl_tbdump_exportbmp(const void* addr, unsigned int format, unsigned int stride, unsigned int width, unsigned int height); + +////////////////////////////////////////////////////////////////////////////// +// OS specific APIs - need to go into their own gsl_libapi_platform.h file +////////////////////////////////////////////////////////////////////////////// +#ifdef WM7 +GSL_API int gsl_kos_wm7_surfobjfromhbitmap(HBITMAP hbitmap, SURFOBJ *surfobj); +#endif // WM7 + + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __GSL_LIBAPI_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h new file mode 100644 index 000000000000..891c7b645ad6 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_pm4types.h @@ -0,0 +1,157 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_PM4TYPES_H +#define __GSL_PM4TYPES_H + + +////////////////////////////////////////////////////////////////////////////// +// packet mask +////////////////////////////////////////////////////////////////////////////// +#define PM4_PKT_MASK 0xc0000000 + + +////////////////////////////////////////////////////////////////////////////// +// packet types +////////////////////////////////////////////////////////////////////////////// +#define PM4_TYPE0_PKT ((unsigned int)0 << 30) +#define PM4_TYPE1_PKT ((unsigned int)1 << 30) +#define PM4_TYPE2_PKT ((unsigned int)2 << 30) +#define PM4_TYPE3_PKT ((unsigned int)3 << 30) + + +////////////////////////////////////////////////////////////////////////////// +// type3 packets +////////////////////////////////////////////////////////////////////////////// +#define PM4_ME_INIT 0x48 // initialize CP's micro-engine + +#define PM4_NOP 0x10 // skip N 32-bit words to get to the next packet + +#define PM4_INDIRECT_BUFFER 0x3f // indirect buffer dispatch. prefetch parser uses this packet type to determine whether to pre-fetch the IB +#define PM4_INDIRECT_BUFFER_PFD 0x37 // indirect buffer dispatch. same as IB, but init is pipelined + +#define PM4_WAIT_FOR_IDLE 0x26 // wait for the IDLE state of the engine +#define PM4_WAIT_REG_MEM 0x3c // wait until a register or memory location is a specific value +#define PM4_WAIT_REG_EQ 0x52 // wait until a register location is equal to a specific value +#define PM4_WAT_REG_GTE 0x53 // wait until a register location is >= a specific value +#define PM4_WAIT_UNTIL_READ 0x5c // wait until a read completes +#define PM4_WAIT_IB_PFD_COMPLETE 0x5d // wait until all base/size writes from an IB_PFD packet have completed + +#define PM4_REG_RMW 0x21 // register read/modify/write +#define PM4_REG_TO_MEM 0x3e // reads register in chip and writes to memory +#define PM4_MEM_WRITE 0x3d // write N 32-bit words to memory +#define PM4_MEM_WRITE_CNTR 0x4f // write CP_PROG_COUNTER value to memory +#define PM4_COND_EXEC 0x44 // conditional execution of a sequence of packets +#define PM4_COND_WRITE 0x45 // conditional write to memory or register + +#define PM4_EVENT_WRITE 0x46 // generate an event that creates a write to memory when completed +#define PM4_EVENT_WRITE_SHD 0x58 // generate a VS|PS_done event +#define PM4_EVENT_WRITE_CFL 0x59 // generate a cache flush done event +#define PM4_EVENT_WRITE_ZPD 0x5b // generate a z_pass done event + +#define PM4_DRAW_INDX 0x22 // initiate fetch of index buffer and draw +#define PM4_DRAW_INDX_2 0x36 // draw using supplied indices in packet +#define PM4_DRAW_INDX_BIN 0x34 // initiate fetch of index buffer and binIDs and draw +#define PM4_DRAW_INDX_2_BIN 0x35 // initiate fetch of bin IDs and draw using supplied indices + +#define PM4_VIZ_QUERY 0x23 // begin/end initiator for viz query extent processing +#define PM4_SET_STATE 0x25 // fetch state sub-blocks and initiate shader code DMAs +#define PM4_SET_CONSTANT 0x2d // load constant into chip and to memory +#define PM4_IM_LOAD 0x27 // load sequencer instruction memory (pointer-based) +#define PM4_IM_LOAD_IMMEDIATE 0x2b // load sequencer instruction memory (code embedded in packet) +#define PM4_LOAD_CONSTANT_CONTEXT 0x2e // load constants from a location in memory +#define PM4_INVALIDATE_STATE 0x3b // selective invalidation of state pointers + +#define PM4_SET_SHADER_BASES 0x4A // dynamically changes shader instruction memory partition +#define PM4_SET_BIN_BASE_OFFSET 0x4B // program an offset that will added to the BIN_BASE value of the 3D_DRAW_INDX_BIN packet +#define PM4_SET_BIN_MASK 0x50 // sets the 64-bit BIN_MASK register in the PFP +#define PM4_SET_BIN_SELECT 0x51 // sets the 64-bit BIN_SELECT register in the PFP + +#define PM4_CONTEXT_UPDATE 0x5e // updates the current context, if needed +#define PM4_INTERRUPT 0x40 // generate interrupt from the command stream + +#define PM4_IM_STORE 0x2c // copy sequencer instruction memory to system memory + + +////////////////////////////////////////////////////////////////////////////// +// packet header building macros +////////////////////////////////////////////////////////////////////////////// +#define pm4_type0_packet(regindx, cnt) (PM4_TYPE0_PKT | (((cnt)-1) << 16) | ((regindx) & 0x7FFF)) +#define pm4_type0_packet_for_sameregister(regindx, cnt) (PM4_TYPE0_PKT | (((cnt)-1) << 16) | ((1 << 15) | ((regindx) & 0x7FFF)) +#define pm4_type1_packet(reg0, reg1) (PM4_TYPE1_PKT | ((reg1) << 12) | (reg0)) +#define pm4_type3_packet(opcode, cnt) (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (((opcode) & 0xFF) << 8)) +#define pm4_predicated_type3_packet(opcode, cnt) (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (((opcode) & 0xFF) << 8) | 0x1)) +#define pm4_nop_packet(cnt) (PM4_TYPE3_PKT | (((cnt)-1) << 16) | (PM4_NOP << 8)) + + +////////////////////////////////////////////////////////////////////////////// +// packet headers +////////////////////////////////////////////////////////////////////////////// +#define PM4_HDR_ME_INIT pm4_type3_packet(PM4_ME_INIT, 18) +#define PM4_HDR_INDIRECT_BUFFER_PFD pm4_type3_packet(PM4_INDIRECT_BUFFER_PFD, 2) +#define PM4_HDR_INDIRECT_BUFFER pm4_type3_packet(PM4_INDIRECT_BUFFER, 2) + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ----------------------- +// pm4 type0 packet header +// ----------------------- +typedef struct __pm4_type0 +{ + unsigned int base_index :15; + unsigned int one_reg_wr :1; + unsigned int count :14; + unsigned int type :2; +} pm4_type0; + +// ----------------------- +// pm4 type2 packet header +// ----------------------- +typedef struct __pm4_type2 +{ + unsigned int reserved :30; + unsigned int type :2; +} pm4_type2; + +// ----------------------- +// pm4 type3 packet header +// ----------------------- +typedef struct __pm4_type3 +{ + unsigned int predicate :1; + unsigned int reserved1 :7; + unsigned int it_opcode :7; + unsigned int reserved2 :1; + unsigned int count :14; + unsigned int type :2; +} pm4_type3; + +#endif // __GSL_PM4TYPES_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_properties.h b/drivers/mxc/amd-gpu/include/api/gsl_properties.h new file mode 100644 index 000000000000..520761fe3490 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_properties.h @@ -0,0 +1,94 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_PROPERTIES_H +#define __GSL_PROPERTIES_H + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// -------------- +// property types +// -------------- +typedef enum _gsl_property_type_t +{ + GSL_PROP_DEVICE_INFO = 0x00000001, + GSL_PROP_DEVICE_SHADOW = 0x00000002, + GSL_PROP_DEVICE_POWER = 0x00000003, + GSL_PROP_SHMEM = 0x00000004, + GSL_PROP_SHMEM_APERTURES = 0x00000005, + GSL_PROP_DEVICE_DMI = 0x00000006 +} gsl_property_type_t; + +// ----------------- +// aperture property +// ----------------- +typedef struct _gsl_apertureprop_t { + unsigned int gpuaddr; + unsigned int hostaddr; +} gsl_apertureprop_t; + +// -------------- +// shmem property +// -------------- +typedef struct _gsl_shmemprop_t { + int numapertures; + unsigned int aperture_mask; + unsigned int aperture_shift; + gsl_apertureprop_t *aperture; +} gsl_shmemprop_t; + +// ----------------------------- +// device shadow memory property +// ----------------------------- +typedef struct _gsl_shadowprop_t { + unsigned int hostaddr; + unsigned int size; + gsl_flags_t flags; +} gsl_shadowprop_t; + +// --------------------- +// device power property +// --------------------- +typedef struct _gsl_powerprop_t { + unsigned int value; + gsl_flags_t flags; +} gsl_powerprop_t; + + +// --------------------- +// device DMI property +// --------------------- +typedef struct _gsl_dmiprop_t { + unsigned int value; + gsl_flags_t flags; +} gsl_dmiprop_t; + +#endif // __GSL_PROPERTIES_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_types.h b/drivers/mxc/amd-gpu/include/api/gsl_types.h new file mode 100644 index 000000000000..99d984966113 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_types.h @@ -0,0 +1,479 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_TYPES_H +#define __GSL_TYPES_H + +#include "stddef.h" + + +////////////////////////////////////////////////////////////////////////////// +// status +////////////////////////////////////////////////////////////////////////////// +#define GSL_SUCCESS OS_SUCCESS +#define GSL_FAILURE OS_FAILURE +#define GSL_FAILURE_SYSTEMERROR OS_FAILURE_SYSTEMERROR +#define GSL_FAILURE_DEVICEERROR OS_FAILURE_DEVICEERROR +#define GSL_FAILURE_OUTOFMEM OS_FAILURE_OUTOFMEM +#define GSL_FAILURE_BADPARAM OS_FAILURE_BADPARAM +#define GSL_FAILURE_OFFSETINVALID OS_FAILURE_OFFSETINVALID +#define GSL_FAILURE_NOTSUPPORTED OS_FAILURE_NOTSUPPORTED +#define GSL_FAILURE_NOMOREAVAILABLE OS_FAILURE_NOMOREAVAILABLE +#define GSL_FAILURE_NOTINITIALIZED OS_FAILURE_NOTINITIALIZED +#define GSL_FAILURE_ALREADYINITIALIZED OS_FAILURE_ALREADYINITIALIZED +#define GSL_FAILURE_TIMEOUT OS_FAILURE_TIMEOUT + + +////////////////////////////////////////////////////////////////////////////// +// memory allocation flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMFLAGS_ANY 0x00000000 // dont care + +#define GSL_MEMFLAGS_CHANNELANY 0x00000000 +#define GSL_MEMFLAGS_CHANNEL1 0x00000000 +#define GSL_MEMFLAGS_CHANNEL2 0x00000001 +#define GSL_MEMFLAGS_CHANNEL3 0x00000002 +#define GSL_MEMFLAGS_CHANNEL4 0x00000003 + +#define GSL_MEMFLAGS_BANKANY 0x00000000 +#define GSL_MEMFLAGS_BANK1 0x00000010 +#define GSL_MEMFLAGS_BANK2 0x00000020 +#define GSL_MEMFLAGS_BANK3 0x00000040 +#define GSL_MEMFLAGS_BANK4 0x00000080 + +#define GSL_MEMFLAGS_DIRANY 0x00000000 +#define GSL_MEMFLAGS_DIRTOP 0x00000100 +#define GSL_MEMFLAGS_DIRBOT 0x00000200 + +#define GSL_MEMFLAGS_APERTUREANY 0x00000000 +#define GSL_MEMFLAGS_EMEM 0x00000000 +#define GSL_MEMFLAGS_CONPHYS 0x00001000 + +#define GSL_MEMFLAGS_ALIGNANY 0x00000000 // minimum alignment is 32 bytes +#define GSL_MEMFLAGS_ALIGN32 0x00000000 +#define GSL_MEMFLAGS_ALIGN64 0x00060000 +#define GSL_MEMFLAGS_ALIGN128 0x00070000 +#define GSL_MEMFLAGS_ALIGN256 0x00080000 +#define GSL_MEMFLAGS_ALIGN512 0x00090000 +#define GSL_MEMFLAGS_ALIGN1K 0x000A0000 +#define GSL_MEMFLAGS_ALIGN2K 0x000B0000 +#define GSL_MEMFLAGS_ALIGN4K 0x000C0000 +#define GSL_MEMFLAGS_ALIGN8K 0x000D0000 +#define GSL_MEMFLAGS_ALIGN16K 0x000E0000 +#define GSL_MEMFLAGS_ALIGN32K 0x000F0000 +#define GSL_MEMFLAGS_ALIGN64K 0x00100000 +#define GSL_MEMFLAGS_ALIGNPAGE GSL_MEMFLAGS_ALIGN4K + +#define GSL_MEMFLAGS_GPUREADWRITE 0x00000000 +#define GSL_MEMFLAGS_GPUREADONLY 0x01000000 +#define GSL_MEMFLAGS_GPUWRITEONLY 0x02000000 +#define GSL_MEMFLAGS_GPUNOACCESS 0x04000000 + +#define GSL_MEMFLAGS_FORCEPAGESIZE 0x40000000 +#define GSL_MEMFLAGS_STRICTREQUEST 0x80000000 // fail the alloc if the flags cannot be honored + +#define GSL_MEMFLAGS_CHANNEL_MASK 0x0000000F +#define GSL_MEMFLAGS_BANK_MASK 0x000000F0 +#define GSL_MEMFLAGS_DIR_MASK 0x00000F00 +#define GSL_MEMFLAGS_APERTURE_MASK 0x0000F000 +#define GSL_MEMFLAGS_ALIGN_MASK 0x00FF0000 +#define GSL_MEMFLAGS_GPUAP_MASK 0x0F000000 + +#define GSL_MEMFLAGS_CHANNEL_SHIFT 0 +#define GSL_MEMFLAGS_BANK_SHIFT 4 +#define GSL_MEMFLAGS_DIR_SHIFT 8 +#define GSL_MEMFLAGS_APERTURE_SHIFT 12 +#define GSL_MEMFLAGS_ALIGN_SHIFT 16 +#define GSL_MEMFLAGS_GPUAP_SHIFT 24 + + +////////////////////////////////////////////////////////////////////////////// +// debug flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_DBGFLAGS_ALL 0xFFFFFFFF +#define GSL_DBGFLAGS_DEVICE 0x00000001 +#define GSL_DBGFLAGS_CTXT 0x00000002 +#define GSL_DBGFLAGS_MEMMGR 0x00000004 +#define GSL_DBGFLAGS_MMU 0x00000008 +#define GSL_DBGFLAGS_POWER 0x00000010 +#define GSL_DBGFLAGS_IRQ 0x00000020 +#define GSL_DBGFLAGS_BIST 0x00000040 +#define GSL_DBGFLAGS_PM4 0x00000080 +#define GSL_DBGFLAGS_PM4MEM 0x00000100 +#define GSL_DBGFLAGS_PM4CHECK 0x00000200 +#define GSL_DBGFLAGS_DUMPX 0x00000400 +#define GSL_DBGFLAGS_DUMPX_WITHOUT_IFH 0x00000800 +#define GSL_DBGFLAGS_IFH 0x00001000 +#define GSL_DBGFLAGS_NULL 0x00002000 + + +////////////////////////////////////////////////////////////////////////////// +// generic flag values +////////////////////////////////////////////////////////////////////////////// +#define GSL_FLAGS_NORMALMODE 0x00000000 +#define GSL_FLAGS_SAFEMODE 0x00000001 +#define GSL_FLAGS_INITIALIZED0 0x00000002 +#define GSL_FLAGS_INITIALIZED 0x00000004 +#define GSL_FLAGS_STARTED 0x00000008 +#define GSL_FLAGS_ACTIVE 0x00000010 +#define GSL_FLAGS_RESERVED0 0x00000020 +#define GSL_FLAGS_RESERVED1 0x00000040 +#define GSL_FLAGS_RESERVED2 0x00000080 + + +////////////////////////////////////////////////////////////////////////////// +// power flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_PWRFLAGS_POWER_OFF 0x00000001 +#define GSL_PWRFLAGS_POWER_ON 0x00000002 +#define GSL_PWRFLAGS_CLK_ON 0x00000004 +#define GSL_PWRFLAGS_CLK_OFF 0x00000008 +#define GSL_PWRFLAGS_OVERRIDE_ON 0x00000010 +#define GSL_PWRFLAGS_OVERRIDE_OFF 0x00000020 + +////////////////////////////////////////////////////////////////////////////// +// DMI flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_DMIFLAGS_ENABLE_SINGLE 0x00000001 // Single buffered DMI +#define GSL_DMIFLAGS_ENABLE_DOUBLE 0x00000002 // Double buffered DMI +#define GSL_DMIFLAGS_ENABLE_TRIPLE 0x00000004 // Triple buffered DMI +#define GSL_DMIFLAGS_DISABLE 0x00000008 +#define GSL_DMIFLAGS_NEXT_BUFFER 0x00000010 + +////////////////////////////////////////////////////////////////////////////// +// cache flags +////////////////////////////////////////////////////////////////////////////// +#define GSL_CACHEFLAGS_CLEAN 0x00000001 /* flush cache */ +#define GSL_CACHEFLAGS_INVALIDATE 0x00000002 /* invalidate cache */ +#define GSL_CACHEFLAGS_WRITECLEAN 0x00000004 /* flush write cache */ + + +////////////////////////////////////////////////////////////////////////////// +// context +////////////////////////////////////////////////////////////////////////////// +#define GSL_CONTEXT_MAX 20 +#define GSL_CONTEXT_NONE 0 +#define GSL_CONTEXT_SAVE_GMEM 1 +#define GSL_CONTEXT_NO_GMEM_ALLOC 2 + + +////////////////////////////////////////////////////////////////////////////// +// other +////////////////////////////////////////////////////////////////////////////// +#define GSL_TIMEOUT_NONE 0 +#define GSL_TIMEOUT_DEFAULT 0xFFFFFFFF + +#define GSL_PAGESIZE 0x1000 +#define GSL_PAGESIZE_SHIFT 12 + +#define GSL_TIMESTAMP_EPSILON 20000 + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// +typedef unsigned int gsl_devhandle_t; +typedef unsigned int gsl_ctxthandle_t; +typedef int gsl_timestamp_t; +typedef unsigned int gsl_flags_t; +typedef unsigned int gpuaddr_t; + +// --------- +// device id +// --------- +typedef enum _gsl_deviceid_t +{ + GSL_DEVICE_ANY = 0, + GSL_DEVICE_YAMATO = 1, + GSL_DEVICE_G12 = 2, + GSL_DEVICE_MAX = 2, + + GSL_DEVICE_FOOBAR = 0x7FFFFFFF +} gsl_deviceid_t; + +// ---------------- +// chip revision id +// ---------------- +// +// coreid:8 majorrev:8 minorrev:8 patch:8 +// +// coreid = 0x00 = YAMATO_DX +// coreid = 0x80 = G12 +// + +#define COREID(x) ((((unsigned int)x & 0xFF) << 24)) +#define MAJORID(x) ((((unsigned int)x & 0xFF) << 16)) +#define MINORID(x) ((((unsigned int)x & 0xFF) << 8)) +#define PATCHID(x) ((((unsigned int)x & 0xFF) << 0)) + +typedef enum _gsl_chipid_t +{ + GSL_CHIPID_YAMATODX_REV13 = (COREID(0x00) | MAJORID(0x01) | MINORID(0x03) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV14 = (COREID(0x00) | MAJORID(0x01) | MINORID(0x04) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV20 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x00) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV21 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV211 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x01) | PATCHID(0x01)), + GSL_CHIPID_YAMATODX_REV22 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x02) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV23 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV231 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x03) | PATCHID(0x01)), + GSL_CHIPID_YAMATODX_REV24 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x04) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV25 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x00)), + GSL_CHIPID_YAMATODX_REV251 = (COREID(0x00) | MAJORID(0x02) | MINORID(0x05) | PATCHID(0x01)), + GSL_CHIPID_G12_REV00 = (int)(COREID(0x80) | MAJORID(0x00) | MINORID(0x00) | PATCHID(0x00)), + GSL_CHIPID_ERROR = (int)0xFFFFFFFF + +} gsl_chipid_t; + +#undef COREID +#undef MAJORID +#undef MINORID +#undef PATCHID + +// ----------- +// device info +// ----------- +typedef struct _gsl_devinfo_t { + + gsl_deviceid_t device_id; // ID of this device + gsl_chipid_t chip_id; + int mmu_enabled; // mmu address translation enabled + unsigned int gmem_gpubaseaddr; + void * gmem_hostbaseaddr; // if gmem_hostbaseaddr is NULL, we would know its not mapped into mmio space + unsigned int gmem_sizebytes; + unsigned int high_precision; /* mx50 z160 has higher gradient/texture precision */ + +} gsl_devinfo_t; + +// ------------------- +// device memory store +// ------------------- +typedef struct _gsl_devmemstore_t { + volatile unsigned int soptimestamp; + unsigned int sbz; + volatile unsigned int eoptimestamp; + unsigned int sbz2; +} gsl_devmemstore_t; + +#define GSL_DEVICE_MEMSTORE_OFFSET(field) offsetof(gsl_devmemstore_t, field) + +// ----------- +// aperture id +// ----------- +typedef enum _gsl_apertureid_t +{ + GSL_APERTURE_EMEM = (GSL_MEMFLAGS_EMEM), + GSL_APERTURE_PHYS = (GSL_MEMFLAGS_CONPHYS >> GSL_MEMFLAGS_APERTURE_SHIFT), + GSL_APERTURE_MMU = (GSL_APERTURE_EMEM | 0x10000000), + GSL_APERTURE_MAX = 2, + + GSL_APERTURE_FOOBAR = 0x7FFFFFFF +} gsl_apertureid_t; + +// ---------- +// channel id +// ---------- +typedef enum _gsl_channelid_t +{ + GSL_CHANNEL_1 = (GSL_MEMFLAGS_CHANNEL1 >> GSL_MEMFLAGS_CHANNEL_SHIFT), + GSL_CHANNEL_2 = (GSL_MEMFLAGS_CHANNEL2 >> GSL_MEMFLAGS_CHANNEL_SHIFT), + GSL_CHANNEL_3 = (GSL_MEMFLAGS_CHANNEL3 >> GSL_MEMFLAGS_CHANNEL_SHIFT), + GSL_CHANNEL_4 = (GSL_MEMFLAGS_CHANNEL4 >> GSL_MEMFLAGS_CHANNEL_SHIFT), + GSL_CHANNEL_MAX = 4, + + GSL_CHANNEL_FOOBAR = 0x7FFFFFFF +} gsl_channelid_t; + +// ---------------------- +// page access permission +// ---------------------- +typedef enum _gsl_ap_t +{ + GSL_AP_NULL = 0x0, + GSL_AP_R = 0x1, + GSL_AP_W = 0x2, + GSL_AP_RW = 0x3, + GSL_AP_X = 0x4, + GSL_AP_RWX = 0x5, + GSL_AP_MAX = 0x6, + + GSL_AP_FOOBAR = 0x7FFFFFFF +} gsl_ap_t; + +// ------------- +// memory region +// ------------- +typedef struct _gsl_memregion_t { + unsigned char *mmio_virt_base; + unsigned int mmio_phys_base; + gpuaddr_t gpu_base; + unsigned int sizebytes; +} gsl_memregion_t; + +// ------------------------ +// shared memory allocation +// ------------------------ +typedef struct _gsl_memdesc_t { + void *hostptr; + gpuaddr_t gpuaddr; + int size; + unsigned int priv; // private + unsigned int priv2; // private + +} gsl_memdesc_t; + +// --------------------------------- +// physical page scatter/gatter list +// --------------------------------- +typedef struct _gsl_scatterlist_t { + int contiguous; // flag whether pages on the list are physically contiguous + unsigned int num; + unsigned int *pages; +} gsl_scatterlist_t; + +// -------------- +// mem free queue +// -------------- +// +// this could be compressed down into the just the memdesc for the node +// +typedef struct _gsl_memnode_t { + gsl_timestamp_t timestamp; + gsl_memdesc_t memdesc; + unsigned int pid; + struct _gsl_memnode_t *next; +} gsl_memnode_t; + +typedef struct _gsl_memqueue_t { + gsl_memnode_t *head; + gsl_memnode_t *tail; +} gsl_memqueue_t; + +// ------------ +// timestamp id +// ------------ +typedef enum _gsl_timestamp_type_t +{ + GSL_TIMESTAMP_CONSUMED = 1, // start-of-pipeline timestamp + GSL_TIMESTAMP_RETIRED = 2, // end-of-pipeline timestamp + GSL_TIMESTAMP_MAX = 2, + + GSL_TIMESTAMP_FOOBAR = 0x7FFFFFFF +} gsl_timestamp_type_t; + +// ------------ +// context type +// ------------ +typedef enum _gsl_context_type_t +{ + GSL_CONTEXT_TYPE_GENERIC = 1, + GSL_CONTEXT_TYPE_OPENGL = 2, + GSL_CONTEXT_TYPE_OPENVG = 3, + + GSL_CONTEXT_TYPE_FOOBAR = 0x7FFFFFFF +} gsl_context_type_t; + +// --------- +// rectangle +// --------- +typedef struct _gsl_rect_t { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int pitch; +} gsl_rect_t; + +// ----------------------- +// pixel buffer descriptor +// ----------------------- +typedef struct _gsl_buffer_desc_t { + gsl_memdesc_t data; + unsigned int width; + unsigned int height; + unsigned int pitch; + unsigned int format; + unsigned int enabled; +} gsl_buffer_desc_t; + +// --------------------- +// command window target +// --------------------- +typedef enum _gsl_cmdwindow_t +{ + GSL_CMDWINDOW_MIN = 0x00000000, + GSL_CMDWINDOW_2D = 0x00000000, + GSL_CMDWINDOW_3D = 0x00000001, // legacy + GSL_CMDWINDOW_MMU = 0x00000002, + GSL_CMDWINDOW_ARBITER = 0x000000FF, + GSL_CMDWINDOW_MAX = 0x000000FF, + + GSL_CMDWINDOW_FOOBAR = 0x7FFFFFFF +} gsl_cmdwindow_t; + +// ------------ +// interrupt id +// ------------ +typedef enum _gsl_intrid_t +{ + GSL_INTR_YDX_MH_AXI_READ_ERROR = 0, + GSL_INTR_YDX_MH_AXI_WRITE_ERROR, + GSL_INTR_YDX_MH_MMU_PAGE_FAULT, + + GSL_INTR_YDX_CP_SW_INT, + GSL_INTR_YDX_CP_T0_PACKET_IN_IB, + GSL_INTR_YDX_CP_OPCODE_ERROR, + GSL_INTR_YDX_CP_PROTECTED_MODE_ERROR, + GSL_INTR_YDX_CP_RESERVED_BIT_ERROR, + GSL_INTR_YDX_CP_IB_ERROR, + GSL_INTR_YDX_CP_IB2_INT, + GSL_INTR_YDX_CP_IB1_INT, + GSL_INTR_YDX_CP_RING_BUFFER, + + GSL_INTR_YDX_RBBM_READ_ERROR, + GSL_INTR_YDX_RBBM_DISPLAY_UPDATE, + GSL_INTR_YDX_RBBM_GUI_IDLE, + + GSL_INTR_YDX_SQ_PS_WATCHDOG, + GSL_INTR_YDX_SQ_VS_WATCHDOG, + + GSL_INTR_G12_MH, + GSL_INTR_G12_G2D, + GSL_INTR_G12_FIFO, +#ifndef _Z180 + GSL_INTR_G12_FBC, +#endif // _Z180 + + GSL_INTR_G12_MH_AXI_READ_ERROR, + GSL_INTR_G12_MH_AXI_WRITE_ERROR, + GSL_INTR_G12_MH_MMU_PAGE_FAULT, + + GSL_INTR_COUNT, + + GSL_INTR_FOOBAR = 0x7FFFFFFF +} gsl_intrid_t; + +#endif // __GSL_TYPES_H diff --git a/drivers/mxc/amd-gpu/include/api/gsl_utils.h b/drivers/mxc/amd-gpu/include/api/gsl_utils.h new file mode 100644 index 000000000000..1078b634173d --- /dev/null +++ b/drivers/mxc/amd-gpu/include/api/gsl_utils.h @@ -0,0 +1,43 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_UTILS_H +#define __GSL_UTILS_H + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_QUADPOW2_TO_SIZEBYTES(quadpow2) (8 << (quadpow2)) +#define GSL_QUADPOW2_TO_SIZEDWORDS(quadpow2) (2 << (quadpow2)) +#define GSL_POW2TEST(size) ((size) && !((size) & ((size) - 1))) +#define GSL_POW2ALIGN_DOWN(addr, alignsize) ((addr) & ~((alignsize) - 1)); +#define GSL_POW2ALIGN_UP(addr, alignsize) (((addr) + ((alignsize) - 1)) & ~((alignsize) - 1)) + + +#endif // __GSL_UTILS_H diff --git a/drivers/mxc/amd-gpu/include/gsl.h b/drivers/mxc/amd-gpu/include/gsl.h new file mode 100644 index 000000000000..07d8e97dcee3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl.h @@ -0,0 +1,79 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_H +#define __GSL_H + +//#define __KGSLLIB_EXPORTS +#define __KERNEL_MODE__ + + +////////////////////////////////////////////////////////////////////////////// +// forward typedefs +////////////////////////////////////////////////////////////////////////////// +//struct _gsl_device_t; +typedef struct _gsl_device_t gsl_device_t; + + +////////////////////////////////////////////////////////////////////////////// +// includes +////////////////////////////////////////////////////////////////////////////// +#include "gsl_buildconfig.h" + +#include "kos_libapi.h" + +#include "gsl_klibapi.h" + +#ifdef GSL_BLD_YAMATO +#include + +#include "gsl_pm4types.h" +#include "gsl_utils.h" +#include "gsl_drawctxt.h" +#include "gsl_ringbuffer.h" +#endif + +#ifdef GSL_BLD_G12 +#include + +#include "gsl_cmdwindow.h" +#endif + +#include "gsl_debug.h" +#include "gsl_mmu.h" +#include "gsl_memmgr.h" +#include "gsl_sharedmem.h" +#include "gsl_intrmgr.h" +#include "gsl_cmdstream.h" +#include "gsl_device.h" +#include "gsl_driver.h" +#include "gsl_log.h" + +#include "gsl_config.h" + +#endif // __GSL_H diff --git a/drivers/mxc/amd-gpu/include/gsl_buildconfig.h b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h new file mode 100644 index 000000000000..4e6be4da7dc4 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_buildconfig.h @@ -0,0 +1,55 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __GSL__BUILDCONFIG_H +#define __GSL__BUILDCONFIG_H + +#define GSL_BLD_YAMATO +#define GSL_BLD_G12 + +#define GSL_LOCKING_COARSEGRAIN + +#define GSL_STATS_MEM +#define GSL_STATS_RINGBUFFER +#define GSL_STATS_MMU + +#define GSL_RB_USE_MEM_RPTR +#define GSL_RB_USE_MEM_TIMESTAMP +#define GSL_RB_TIMESTAMP_INTERUPT +/* #define GSL_RB_USE_WPTR_POLLING */ + +/* #define GSL_MMU_PAGETABLE_PERPROCESS */ + +#define GSL_CALLER_PROCESS_MAX 10 +#define GSL_SHMEM_MAX_APERTURES 3 + +#endif /* __GSL__BUILDCONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdstream.h b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h new file mode 100644 index 000000000000..550d5d0005ab --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_cmdstream.h @@ -0,0 +1,62 @@ +/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_CMDSTREAM_H +#define __GSL_CMDSTREAM_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// + +#ifdef VG_HDK +#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data) +#else +#define GSL_CMDSTREAM_GET_SOP_TIMESTAMP(device, data) kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(soptimestamp), 4, false) +#endif + +#ifdef VG_HDK +#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data) (*((int*)data) = (gsl_driver.device[GSL_DEVICE_G12-1]).timestamp) +#else +#define GSL_CMDSTREAM_GET_EOP_TIMESTAMP(device, data) kgsl_sharedmem_read0(&device->memstore, (data), GSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), 4, false) +#endif + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// +gsl_timestamp_t kgsl_cmdstream_readtimestamp0(gsl_deviceid_t device_id, gsl_timestamp_type_t type); +void kgsl_cmdstream_memqueue_drain(gsl_device_t *device); +int kgsl_cmdstream_init(gsl_device_t *device); +int kgsl_cmdstream_close(gsl_device_t *device); + +#endif // __GSL_CMDSTREAM_H diff --git a/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h new file mode 100644 index 000000000000..0152dd75a631 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_cmdwindow.h @@ -0,0 +1,51 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_CMDWINDOW_H +#define __GSL_CMDWINDOW_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#ifndef _Z180 +#define GSL_G12_INTR_COUNT 4 +#else +#define GSL_G12_INTR_COUNT 3 +#endif + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_cmdwindow_init(gsl_device_t *device); +int kgsl_cmdwindow_close(gsl_device_t *device); +int kgsl_cmdwindow_write0(gsl_deviceid_t device_id, gsl_cmdwindow_t target, unsigned int addr, unsigned int data); + +#endif // __GSL_CMDWINDOW_H diff --git a/drivers/mxc/amd-gpu/include/gsl_config.h b/drivers/mxc/amd-gpu/include/gsl_config.h new file mode 100644 index 000000000000..aa911b4096a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_config.h @@ -0,0 +1,221 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __GSL__CONFIG_H +#define __GSL__CONFIG_H + +/* ------------------------ + * Yamato ringbuffer config + * ------------------------ */ +static const unsigned int gsl_cfg_rb_sizelog2quadwords = GSL_RB_SIZE_32K; +static const unsigned int gsl_cfg_rb_blksizequadwords = GSL_RB_SIZE_16; + +/* ------------------------ + * Yamato MH arbiter config + * ------------------------ */ +static const mh_arbiter_config_t gsl_cfg_yamato_mharb = { + 0x10, /* same_page_limit */ + 0, /* same_page_granularity */ + 1, /* l1_arb_enable */ + 1, /* l1_arb_hold_enable */ + 0, /* l2_arb_control */ + 1, /* page_size */ + 1, /* tc_reorder_enable */ + 1, /* tc_arb_hold_enable */ + 1, /* in_flight_limit_enable */ + 0x8, /* in_flight_limit */ + 1, /* cp_clnt_enable */ + 1, /* vgt_clnt_enable */ + 1, /* tc_clnt_enable */ + 1, /* rb_clnt_enable */ + 1, /* pa_clnt_enable */ +}; + +/* --------------------- + * G12 MH arbiter config + * --------------------- */ +static const REG_MH_ARBITER_CONFIG gsl_cfg_g12_mharb = { + 0x10, /* SAME_PAGE_LIMIT */ + 0, /* SAME_PAGE_GRANULARITY */ + 1, /* L1_ARB_ENABLE */ + 1, /* L1_ARB_HOLD_ENABLE */ + 0, /* L2_ARB_CONTROL */ + 1, /* PAGE_SIZE */ + 1, /* TC_REORDER_ENABLE */ + 1, /* TC_ARB_HOLD_ENABLE */ + 0, /* IN_FLIGHT_LIMIT_ENABLE */ + 0x8, /* IN_FLIGHT_LIMIT */ + 1, /* CP_CLNT_ENABLE */ + 1, /* VGT_CLNT_ENABLE */ + 1, /* TC_CLNT_ENABLE */ + 1, /* RB_CLNT_ENABLE */ + 1, /* PA_CLNT_ENABLE */ +}; + +/* ----------------------------- + * interrupt block register data + * ----------------------------- */ +static const gsl_intrblock_reg_t gsl_cfg_intrblock_reg[GSL_INTR_BLOCK_COUNT] = { + { /* Yamato MH */ + GSL_INTR_BLOCK_YDX_MH, + GSL_INTR_YDX_MH_AXI_READ_ERROR, + GSL_INTR_YDX_MH_MMU_PAGE_FAULT, + mmMH_INTERRUPT_STATUS, + mmMH_INTERRUPT_CLEAR, + mmMH_INTERRUPT_MASK + }, + { /* Yamato CP */ + GSL_INTR_BLOCK_YDX_CP, + GSL_INTR_YDX_CP_SW_INT, + GSL_INTR_YDX_CP_RING_BUFFER, + mmCP_INT_STATUS, + mmCP_INT_ACK, + mmCP_INT_CNTL + }, + { /* Yamato RBBM */ + GSL_INTR_BLOCK_YDX_RBBM, + GSL_INTR_YDX_RBBM_READ_ERROR, + GSL_INTR_YDX_RBBM_GUI_IDLE, + mmRBBM_INT_STATUS, + mmRBBM_INT_ACK, + mmRBBM_INT_CNTL + }, + { /* Yamato SQ */ + GSL_INTR_BLOCK_YDX_SQ, + GSL_INTR_YDX_SQ_PS_WATCHDOG, + GSL_INTR_YDX_SQ_VS_WATCHDOG, + mmSQ_INT_STATUS, + mmSQ_INT_ACK, + mmSQ_INT_CNTL + }, + { /* G12 */ + GSL_INTR_BLOCK_G12, + GSL_INTR_G12_MH, +#ifndef _Z180 + GSL_INTR_G12_FBC, +#else + GSL_INTR_G12_FIFO, +#endif /* _Z180 */ + (ADDR_VGC_IRQSTATUS >> 2), + (ADDR_VGC_IRQSTATUS >> 2), + (ADDR_VGC_IRQENABLE >> 2) + }, + { /* G12 MH */ + GSL_INTR_BLOCK_G12_MH, + GSL_INTR_G12_MH_AXI_READ_ERROR, + GSL_INTR_G12_MH_MMU_PAGE_FAULT, + ADDR_MH_INTERRUPT_STATUS, /* G12 MH offsets are considered to be dword based, therefore no down shift */ + ADDR_MH_INTERRUPT_CLEAR, + ADDR_MH_INTERRUPT_MASK + }, +}; + +/* ----------------------- + * interrupt mask bit data + * ----------------------- */ +static const int gsl_cfg_intr_mask[GSL_INTR_COUNT] = { + MH_INTERRUPT_MASK__AXI_READ_ERROR, + MH_INTERRUPT_MASK__AXI_WRITE_ERROR, + MH_INTERRUPT_MASK__MMU_PAGE_FAULT, + + CP_INT_CNTL__SW_INT_MASK, + CP_INT_CNTL__T0_PACKET_IN_IB_MASK, + CP_INT_CNTL__OPCODE_ERROR_MASK, + CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK, + CP_INT_CNTL__RESERVED_BIT_ERROR_MASK, + CP_INT_CNTL__IB_ERROR_MASK, + CP_INT_CNTL__IB2_INT_MASK, + CP_INT_CNTL__IB1_INT_MASK, + CP_INT_CNTL__RB_INT_MASK, + + RBBM_INT_CNTL__RDERR_INT_MASK, + RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK, + RBBM_INT_CNTL__GUI_IDLE_INT_MASK, + + SQ_INT_CNTL__PS_WATCHDOG_MASK, + SQ_INT_CNTL__VS_WATCHDOG_MASK, + + (1 << VGC_IRQENABLE_MH_FSHIFT), + (1 << VGC_IRQENABLE_G2D_FSHIFT), + (1 << VGC_IRQENABLE_FIFO_FSHIFT), +#ifndef _Z180 + (1 << VGC_IRQENABLE_FBC_FSHIFT), +#endif + (1 << MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT), + (1 << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT), + (1 << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT), +}; + +/* ----------------- + * mmu register data + * ----------------- */ +static const gsl_mmu_reg_t gsl_cfg_mmu_reg[GSL_DEVICE_MAX] = { + { /* Yamato */ + mmMH_MMU_CONFIG, + mmMH_MMU_MPU_BASE, + mmMH_MMU_MPU_END, + mmMH_MMU_VA_RANGE, + mmMH_MMU_PT_BASE, + mmMH_MMU_PAGE_FAULT, + mmMH_MMU_TRAN_ERROR, + mmMH_MMU_INVALIDATE, + }, + { /* G12 - MH offsets are considered to be dword based, therefore no down shift */ + ADDR_MH_MMU_CONFIG, + ADDR_MH_MMU_MPU_BASE, + ADDR_MH_MMU_MPU_END, + ADDR_MH_MMU_VA_RANGE, + ADDR_MH_MMU_PT_BASE, + ADDR_MH_MMU_PAGE_FAULT, + ADDR_MH_MMU_TRAN_ERROR, + ADDR_MH_MMU_INVALIDATE, + }, +}; + +/* ----------------- + * mh interrupt data + * ----------------- */ +static const gsl_mh_intr_t gsl_cfg_mh_intr[GSL_DEVICE_MAX] = +{ + { /* Yamato */ + GSL_INTR_YDX_MH_AXI_READ_ERROR, + GSL_INTR_YDX_MH_AXI_WRITE_ERROR, + GSL_INTR_YDX_MH_MMU_PAGE_FAULT, + }, + { /* G12 */ + GSL_INTR_G12_MH_AXI_READ_ERROR, + GSL_INTR_G12_MH_AXI_WRITE_ERROR, + GSL_INTR_G12_MH_MMU_PAGE_FAULT, + } +}; + +#endif /* __GSL__CONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_context.h b/drivers/mxc/amd-gpu/include/gsl_context.h new file mode 100644 index 000000000000..6e83bdb34036 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_context.h @@ -0,0 +1,45 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_CONTEXT_H +#define __GSL_CONTEXT_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////// +// functions +////////////////////////////////////////////////////////////////////////////// + +#endif // __GSL_CONTEXT_H diff --git a/drivers/mxc/amd-gpu/include/gsl_debug.h b/drivers/mxc/amd-gpu/include/gsl_debug.h new file mode 100644 index 000000000000..1275278f9eae --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_debug.h @@ -0,0 +1,126 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DEBUG_H +#define __GSL_DEBUG_H + +#ifdef BB_DUMPX +#include "dumpx.h" +#endif + +#ifdef TBDUMP +#include "gsl_tbdump.h" +#endif + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#ifdef _DEBUG +#define KGSL_DEBUG(flag, action) if (gsl_driver.flags_debug & flag) {action;} +#ifdef GSL_BLD_YAMATO +#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords) Yamato_DumpPM4((cmds), (sizedwords)) +#define KGSL_DEBUG_DUMPREGWRITE(addr, value) Yamato_DumpRegisterWrite((addr), (value)) +#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data) Yamato_DumpWriteMemory(addr, sizebytes, data) +#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value) Yamato_DumpSetMemory(addr, sizebytes, value) +#define KGSL_DEBUG_DUMPFBSTART(device) Yamato_DumpFbStart(device) +#define KGSL_DEBUG_DUMPREGSPACE(device) Yamato_DumpRegSpace(device) +#define KGSL_DEBUG_DUMPWINDOW(addr, width, height) Yamato_DumpWindow(addr, width, height) +#else +#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords) +#define KGSL_DEBUG_DUMPREGWRITE(addr, value) +#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data) +#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value) +#define KGSL_DEBUG_DUMPFBSTART(device) +#define KGSL_DEBUG_DUMPREGSPACE(device) +#define KGSL_DEBUG_DUMPWINDOW(addr, width, height) +#endif +#ifdef TBDUMP + +#define KGSL_DEBUG_TBDUMP_OPEN(filename) tbdump_open(filename) +#define KGSL_DEBUG_TBDUMP_CLOSE() tbdump_close() +#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes) tbdump_syncmem((unsigned int)addr, (unsigned int)src, sizebytes) +#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes) tbdump_setmem((unsigned int)addr, value, sizebytes) +#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value) tbdump_slavewrite(addr, value) +#define KGSL_DEBUG_TBDUMP_WAITIRQ() tbdump_waitirq() + +#else +#define KGSL_DEBUG_TBDUMP_OPEN(file) +#define KGSL_DEBUG_TBDUMP_CLOSE() +#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes) +#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes) +#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value) +#define KGSL_DEBUG_TBDUMP_WAITIRQ() +#endif +#ifdef BB_DUMPX +#define KGSL_DEBUG_DUMPX_OPEN(filename, param) dumpx_open((filename), (param)) +#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment) dumpx(cmd, (par1), (par2), (par3), (comment)) +#define KGSL_DEBUG_DUMPX_CLOSE() dumpx_close() +#else +#define KGSL_DEBUG_DUMPX_OPEN(filename, param) +#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment) +#define KGSL_DEBUG_DUMPX_CLOSE() +#endif +#else +#define KGSL_DEBUG(flag, action) +#define KGSL_DEBUG_DUMPPM4(cmds, sizedwords) +#define KGSL_DEBUG_DUMPREGWRITE(addr, value) +#define KGSL_DEBUG_DUMPMEMWRITE(addr, sizebytes, data) +#define KGSL_DEBUG_DUMPMEMSET(addr, sizebytes, value) +#define KGSL_DEBUG_DUMPFBSTART(device) +#define KGSL_DEBUG_DUMPREGSPACE(device) +#define KGSL_DEBUG_DUMPWINDOW(addr, width, height) +#define KGSL_DEBUG_DUMPX(cmd, par1, par2, par3, comment) + +#define KGSL_DEBUG_TBDUMP_OPEN(file) +#define KGSL_DEBUG_TBDUMP_CLOSE() +#define KGSL_DEBUG_TBDUMP_SYNCMEM(addr, src, sizebytes) +#define KGSL_DEBUG_TBDUMP_SETMEM(addr, value, sizebytes) +#define KGSL_DEBUG_TBDUMP_SLAVEWRITE(addr, value) +#define KGSL_DEBUG_TBDUMP_WAITIRQ() +#endif // _DEBUG + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +#ifdef GSL_BLD_YAMATO +void Yamato_DumpPM4(unsigned int *cmds, unsigned int sizedwords); +void Yamato_DumpRegisterWrite(unsigned int dwAddress, unsigned int value); +void Yamato_DumpWriteMemory(unsigned int dwAddress, unsigned int dwSize, void* pData); +void Yamato_DumpSetMemory(unsigned int dwAddress, unsigned int dwSize, unsigned int pData); +void Yamato_DumpFbStart(gsl_device_t *device); +void Yamato_DumpRegSpace(gsl_device_t *device); +#ifdef _WIN32 +void Yamato_DumpWindow(unsigned int addr, unsigned int width, unsigned int height); +#endif +#endif +#ifdef _DEBUG +int kgsl_dumpx_parse_ibs(gpuaddr_t gpuaddr, int sizedwords); +#endif //_DEBUG +#endif // __GSL_DRIVER_H diff --git a/drivers/mxc/amd-gpu/include/gsl_device.h b/drivers/mxc/amd-gpu/include/gsl_device.h new file mode 100644 index 000000000000..07c1438994f6 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_device.h @@ -0,0 +1,152 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DEVICE_H +#define __GSL_DEVICE_H + +#ifdef _LINUX +#include +#include +#endif + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// -------------- +// function table +// -------------- +typedef struct _gsl_functable_t { + int (*device_init) (gsl_device_t *device); + int (*device_close) (gsl_device_t *device); + int (*device_destroy) (gsl_device_t *device); + int (*device_start) (gsl_device_t *device, gsl_flags_t flags); + int (*device_stop) (gsl_device_t *device); + int (*device_getproperty) (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes); + int (*device_setproperty) (gsl_device_t *device, gsl_property_type_t type, void *value, unsigned int sizebytes); + int (*device_idle) (gsl_device_t *device, unsigned int timeout); + int (*device_regread) (gsl_device_t *device, unsigned int offsetwords, unsigned int *value); + int (*device_regwrite) (gsl_device_t *device, unsigned int offsetwords, unsigned int value); + int (*device_waitirq) (gsl_device_t *device, gsl_intrid_t intr_id, unsigned int *count, unsigned int timeout); + int (*device_waittimestamp) (gsl_device_t *device, gsl_timestamp_t timestamp, unsigned int timeout); + int (*device_runpending) (gsl_device_t *device); + int (*device_addtimestamp) (gsl_device_t *device_id, gsl_timestamp_t *timestamp); + int (*intr_isr) (gsl_device_t *device); + int (*mmu_tlbinvalidate) (gsl_device_t *device, unsigned int reg_invalidate, unsigned int pid); + int (*mmu_setpagetable) (gsl_device_t *device, unsigned int reg_ptbase, gpuaddr_t ptbase, unsigned int pid); + int (*cmdstream_issueibcmds) (gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags); + int (*context_create) (gsl_device_t *device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags); + int (*context_destroy) (gsl_device_t *device_id, unsigned int drawctxt_id); +} gsl_functable_t; + +// ------------- +// device object +// ------------- +struct _gsl_device_t { + + unsigned int refcnt; + unsigned int callerprocess[GSL_CALLER_PROCESS_MAX]; // caller process table + gsl_functable_t ftbl; + gsl_flags_t flags; + gsl_deviceid_t id; + unsigned int chip_id; + gsl_memregion_t regspace; + gsl_intr_t intr; + gsl_memdesc_t memstore; + gsl_memqueue_t memqueue; // queue of memfrees pending timestamp elapse + +#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + unsigned int memstoreshadow[GSL_CALLER_PROCESS_MAX]; +#endif // GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + +#ifndef GSL_NO_MMU + gsl_mmu_t mmu; +#endif // GSL_NO_MMU + +#ifdef GSL_BLD_YAMATO + gsl_memregion_t gmemspace; + gsl_ringbuffer_t ringbuffer; +#ifdef GSL_LOCKING_FINEGRAIN + oshandle_t drawctxt_mutex; +#endif + unsigned int drawctxt_count; + gsl_drawctxt_t *drawctxt_active; + gsl_drawctxt_t drawctxt[GSL_CONTEXT_MAX]; +#endif // GSL_BLD_YAMATO + +#ifdef GSL_BLD_G12 +#ifdef GSL_LOCKING_FINEGRAIN + oshandle_t cmdwindow_mutex; +#endif + unsigned int intrcnt[GSL_G12_INTR_COUNT]; + gsl_timestamp_t current_timestamp; + gsl_timestamp_t timestamp; +#ifndef _LINUX + unsigned int irq_thread; + oshandle_t irq_thread_handle; +#endif +#ifdef IRQTHREAD_POLL + oshandle_t irqthread_event; +#endif +#endif // GSL_BLD_G12 +#ifdef GSL_LOCKING_FINEGRAIN + oshandle_t cmdstream_mutex; +#endif +#ifndef _LINUX + oshandle_t timestamp_event; +#else + wait_queue_head_t timestamp_waitq; + struct workqueue_struct *irq_workq; + struct work_struct irq_work; + struct work_struct irq_err_work; +#endif + void *autogate; +}; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_device_init(gsl_device_t *device, gsl_deviceid_t device_id); +int kgsl_device_close(gsl_device_t *device); +int kgsl_device_destroy(gsl_device_t *device); +int kgsl_device_attachcallback(gsl_device_t *device, unsigned int pid); +int kgsl_device_detachcallback(gsl_device_t *device, unsigned int pid); +int kgsl_device_runpending(gsl_device_t *device); + +int kgsl_yamato_getfunctable(gsl_functable_t *ftbl); +int kgsl_g12_getfunctable(gsl_functable_t *ftbl); + +int kgsl_clock(gsl_deviceid_t dev, int enable); +int kgsl_device_active(gsl_device_t *dev); +int kgsl_device_clock(gsl_deviceid_t id, int enable); +int kgsl_device_autogate_init(gsl_device_t *dev); +void kgsl_device_autogate_exit(gsl_device_t *dev); + + +#endif // __GSL_DEVICE_H diff --git a/drivers/mxc/amd-gpu/include/gsl_display.h b/drivers/mxc/amd-gpu/include/gsl_display.h new file mode 100644 index 000000000000..82300647b3ef --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_display.h @@ -0,0 +1,62 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DISPLAY_H +#define __GSL_DISPLAY_H + +#define __GSLDISPLAY_EXPORTS + +#include "gsl_libapi.h" +#include "gsl_klibapi.h" // hack to enable direct reg write +#include "gsl_displayapi.h" + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_LIB_MAXDISPLAYS 1 +#define GSL_LIB_MAXSURFACES 3 + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// +typedef struct _gsl_display_t { + int numdisplays; + gsl_displaymode_t mode[GSL_LIB_MAXDISPLAYS]; + gsl_devhandle_t devhandle; +} gsl_display_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int gsl_display_hitachi_240x320_tft_init(int display_id); +int gsl_display_toshiba_640x480_tft_init(int display_id); + +#endif // __GSL_DISPLAY_H diff --git a/drivers/mxc/amd-gpu/include/gsl_drawctxt.h b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h new file mode 100644 index 000000000000..f3bc8c37f4f2 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_drawctxt.h @@ -0,0 +1,118 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DRAWCTXT_H +#define __GSL_DRAWCTXT_H + +////////////////////////////////////////////////////////////////////////////// +// Flags +////////////////////////////////////////////////////////////////////////////// + +#define CTXT_FLAGS_NOT_IN_USE 0x00000000 +#define CTXT_FLAGS_IN_USE 0x00000001 + +#define CTXT_FLAGS_STATE_SHADOW 0x00000010 // state shadow memory allocated + +#define CTXT_FLAGS_GMEM_SHADOW 0x00000100 // gmem shadow memory allocated +#define CTXT_FLAGS_GMEM_SAVE 0x00000200 // gmem must be copied to shadow +#define CTXT_FLAGS_GMEM_RESTORE 0x00000400 // gmem can be restored from shadow + +#define CTXT_FLAGS_SHADER_SAVE 0x00002000 // shader must be copied to shadow +#define CTXT_FLAGS_SHADER_RESTORE 0x00004000 // shader can be restored from shadow + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------ +// draw context +// ------------ + +typedef struct _gmem_shadow_t +{ + gsl_memdesc_t gmemshadow; // Shadow buffer address + + // 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x 256 rows. + // width & height must be a multiples of 32, in case tiled textures are used. + unsigned int size; // Size of surface used to store GMEM + unsigned int width; // Width of surface used to store GMEM + unsigned int height; // Height of surface used to store GMEM + unsigned int pitch; // Pitch of surface used to store GMEM + unsigned int format; // Format of surface used to store GMEM + + int offset; + + unsigned int offset_x; + unsigned int offset_y; + + unsigned int gmem_width; // GMEM width + unsigned int gmem_height; // GMEM height + unsigned int gmem_pitch; // GMEM pitch + + unsigned int gmem_offset_x; + unsigned int gmem_offset_y; + + unsigned int* gmem_save_commands; + unsigned int* gmem_restore_commands; + unsigned int gmem_save[3]; + unsigned int gmem_restore[3]; + + gsl_memdesc_t quad_vertices; + gsl_memdesc_t quad_texcoords; +} gmem_shadow_t; + +#define GSL_MAX_GMEM_SHADOW_BUFFERS 2 + +typedef struct _gsl_drawctxt_t { + unsigned int pid; + gsl_flags_t flags; + gsl_context_type_t type; + gsl_memdesc_t gpustate; + + unsigned int reg_save[3]; + unsigned int reg_restore[3]; + unsigned int shader_save[3]; + unsigned int shader_fixup[3]; + unsigned int shader_restore[3]; + unsigned int chicken_restore[3]; + gmem_shadow_t context_gmem_shadow; // Information of the GMEM shadow that is created in context create + gmem_shadow_t user_gmem_shadow[GSL_MAX_GMEM_SHADOW_BUFFERS]; // User defined GMEM shadow buffers +} gsl_drawctxt_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_drawctxt_init(gsl_device_t *device); +int kgsl_drawctxt_close(gsl_device_t *device); +int kgsl_drawctxt_destroyall(gsl_device_t *device); +void kgsl_drawctxt_switch(gsl_device_t *device, gsl_drawctxt_t *drawctxt, gsl_flags_t flags); +int kgsl_drawctxt_create(gsl_device_t* device, gsl_context_type_t type, unsigned int *drawctxt_id, gsl_flags_t flags); +int kgsl_drawctxt_destroy(gsl_device_t* device, unsigned int drawctxt_id); + +#endif // __GSL_DRAWCTXT_H diff --git a/drivers/mxc/amd-gpu/include/gsl_driver.h b/drivers/mxc/amd-gpu/include/gsl_driver.h new file mode 100644 index 000000000000..9c908ce4696e --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_driver.h @@ -0,0 +1,106 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_DRIVER_H +#define __GSL_DRIVER_H + + +///////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#ifdef GSL_DEDICATED_PROCESS +#define GSL_CALLER_PROCESSID_GET() kos_callerprocess_getid() +#else +#define GSL_CALLER_PROCESSID_GET() kos_process_getid() +#endif // GSL_DEDICATED_PROCESS + +#ifdef GSL_LOCKING_COARSEGRAIN +#define GSL_API_MUTEX_CREATE() gsl_driver.mutex = kos_mutex_create("gsl_global"); \ + if (!gsl_driver.mutex) {return (GSL_FAILURE);} +#define GSL_API_MUTEX_LOCK() kos_mutex_lock(gsl_driver.mutex) +#define GSL_API_MUTEX_UNLOCK() kos_mutex_unlock(gsl_driver.mutex) +#define GSL_API_MUTEX_FREE() kos_mutex_free(gsl_driver.mutex); gsl_driver.mutex = 0; +#else +#define GSL_API_MUTEX_CREATE() +#define GSL_API_MUTEX_LOCK() +#define GSL_API_MUTEX_UNLOCK() +#define GSL_API_MUTEX_FREE() +#endif + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------- +// driver object +// ------------- +typedef struct _gsl_driver_t { + gsl_flags_t flags_debug; + int refcnt; + unsigned int callerprocess[GSL_CALLER_PROCESS_MAX]; // caller process table + oshandle_t mutex; // global API mutex + void *hal; + gsl_sharedmem_t shmem; + gsl_device_t device[GSL_DEVICE_MAX]; + int dmi_state; // OS_TRUE = enabled, OS_FALSE otherwise + gsl_flags_t dmi_mode; // single, double, or triple buffering + int dmi_frame; // set to -1 when DMI is enabled + int dmi_max_frame; // indicates the maximum frame # that we will support + int enable_mmu; +} gsl_driver_t; + + +////////////////////////////////////////////////////////////////////////////// +// external variable declarations +////////////////////////////////////////////////////////////////////////////// +extern gsl_driver_t gsl_driver; + + +////////////////////////////////////////////////////////////////////////////// +// inline functions +////////////////////////////////////////////////////////////////////////////// +OSINLINE int +kgsl_driver_getcallerprocessindex(unsigned int pid, int *index) +{ + int i; + + // obtain index in caller process table + for (i = 0; i < GSL_CALLER_PROCESS_MAX; i++) + { + if (gsl_driver.callerprocess[i] == pid) + { + *index = i; + return (GSL_SUCCESS); + } + } + + return (GSL_FAILURE); +} + +#endif // __GSL_DRIVER_H diff --git a/drivers/mxc/amd-gpu/include/gsl_hal.h b/drivers/mxc/amd-gpu/include/gsl_hal.h new file mode 100644 index 000000000000..fcf9f0891f16 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_hal.h @@ -0,0 +1,151 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_HALAPI_H +#define __GSL_HALAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/* +#include "gsl_buildconfig.h" +#include "kos_libapi.h" +#include "gsl_klibapi.h" +#ifdef GSL_BLD_YAMATO +#include +#endif +#ifdef GSL_BLD_G12 +#include +#endif +#include "gsl_hwaccess.h" +*/ + +#include "gsl.h" +#include "gsl_hwaccess.h" + + +////////////////////////////////////////////////////////////////////////////// +// linkage +////////////////////////////////////////////////////////////////////////////// +#ifdef __KGSLHAL_EXPORTS +#define KGSLHAL_API OS_DLLEXPORT +#else +#define KGSLHAL_API +#endif // __KGSLLIB_EXPORTS + + +////////////////////////////////////////////////////////////////////////////// +// version control +////////////////////////////////////////////////////////////////////////////// +#define KGSLHAL_NAME "AMD GSL Kernel HAL" +#define KGSLHAL_VERSION "0.1" + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define GSL_HAL_REG_READ(device_id, gpubase, offsetwords, value) kgsl_hwaccess_regread(device_id, gpubase, (offsetwords), (value)) +#define GSL_HAL_REG_WRITE(device_id, gpubase, offsetwords, value) kgsl_hwaccess_regwrite(device_id, gpubase, (offsetwords), (value)) + +#define GSL_HAL_MEM_READ(dst, gpubase, gpuoffset, sizebytes, touserspace) kgsl_hwaccess_memread(dst, gpubase, (gpuoffset), (sizebytes), touserspace) +#define GSL_HAL_MEM_WRITE(gpubase, gpuoffset, src, sizebytes, fromuserspace) kgsl_hwaccess_memwrite(gpubase, (gpuoffset), src, (sizebytes), fromuserspace) +#define GSL_HAL_MEM_SET(gpubase, gpuoffset, value, sizebytes) kgsl_hwaccess_memset(gpubase, (gpuoffset), (value), (sizebytes)) + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------- +// device config +// ------------- +typedef struct _gsl_devconfig_t { + + gsl_memregion_t regspace; + + unsigned int mmu_config; + gpuaddr_t mpu_base; + int mpu_range; + gpuaddr_t va_base; + unsigned int va_range; + +#ifdef GSL_BLD_YAMATO + gsl_memregion_t gmemspace; +#endif // GSL_BLD_YAMATO + +} gsl_devconfig_t; + +// ---------------------- +// memory aperture config +// ---------------------- +typedef struct _gsl_apertureconfig_t +{ + gsl_apertureid_t id; + gsl_channelid_t channel; + unsigned int hostbase; + unsigned int gpubase; + unsigned int sizebytes; +} gsl_apertureconfig_t; + +// -------------------- +// shared memory config +// -------------------- +typedef struct _gsl_shmemconfig_t +{ + int numapertures; + gsl_apertureconfig_t apertures[GSL_SHMEM_MAX_APERTURES]; +} gsl_shmemconfig_t; + +typedef struct _gsl_hal_t { + gsl_memregion_t z160_regspace; + gsl_memregion_t z430_regspace; + gsl_memregion_t memchunk; + gsl_memregion_t memspace[GSL_SHMEM_MAX_APERTURES]; + unsigned int has_z160; + unsigned int has_z430; +} gsl_hal_t; + + +////////////////////////////////////////////////////////////////////////////// +// HAL API +////////////////////////////////////////////////////////////////////////////// +KGSLHAL_API int kgsl_hal_init(void); +KGSLHAL_API int kgsl_hal_close(void); +KGSLHAL_API int kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config); +KGSLHAL_API int kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config); +KGSLHAL_API int kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value); +KGSLHAL_API gsl_chipid_t kgsl_hal_getchipid(gsl_deviceid_t device_id); +KGSLHAL_API int kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]); +KGSLHAL_API int kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // __GSL_HALAPI_H diff --git a/drivers/mxc/amd-gpu/include/gsl_halconfig.h b/drivers/mxc/amd-gpu/include/gsl_halconfig.h new file mode 100644 index 000000000000..363474b7a6bb --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_halconfig.h @@ -0,0 +1,49 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#ifndef __GSL_HALCONFIG_H +#define __GSL_HALCONFIG_H + +#define GSL_HAL_GPUBASE_REG_YDX 0x30000000 +#define GSL_HAL_SIZE_REG_YDX 0x00020000 /* 128KB */ + +#define GSL_HAL_SIZE_REG_G12 0x00001000 /* 4KB */ + +#define GSL_HAL_SHMEM_SIZE_EMEM1_MMU 0x01800000 /* 24MB */ +#define GSL_HAL_SHMEM_SIZE_EMEM2_MMU 0x00400000 /* 4MB */ +#define GSL_HAL_SHMEM_SIZE_PHYS_MMU 0x00400000 /* 4MB */ + +#define GSL_HAL_SHMEM_SIZE_EMEM1_NOMMU 0x00A00000 /* 10MB */ +#define GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU 0x00200000 /* 2MB */ +#define GSL_HAL_SHMEM_SIZE_PHYS_NOMMU 0x00100000 /* 1MB */ + +#endif /* __GSL_HALCONFIG_H */ diff --git a/drivers/mxc/amd-gpu/include/gsl_intrmgr.h b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h new file mode 100644 index 000000000000..f46f6d8e6a86 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_intrmgr.h @@ -0,0 +1,104 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_INTRMGR_H +#define __GSL_INTRMGR_H + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------------------------------- +// block which can generate an interrupt +// ------------------------------------- +typedef enum _gsl_intrblock_t +{ + GSL_INTR_BLOCK_YDX_MH = 0, + GSL_INTR_BLOCK_YDX_CP, + GSL_INTR_BLOCK_YDX_RBBM, + GSL_INTR_BLOCK_YDX_SQ, + GSL_INTR_BLOCK_G12, + GSL_INTR_BLOCK_G12_MH, + + GSL_INTR_BLOCK_COUNT, +} gsl_intrblock_t; + +// ------------------------ +// interrupt block register +// ------------------------ +typedef struct _gsl_intrblock_reg_t +{ + gsl_intrblock_t id; + gsl_intrid_t first_id; + gsl_intrid_t last_id; + unsigned int status_reg; + unsigned int clear_reg; + unsigned int mask_reg; +} gsl_intrblock_reg_t; + +// -------- +// callback +// -------- +typedef void (*gsl_intr_callback_t)(gsl_intrid_t id, void *cookie); + +// ----------------- +// interrupt routine +// ----------------- +typedef struct _gsl_intr_handler_t +{ + gsl_intr_callback_t callback; + void * cookie; +} gsl_intr_handler_t; + +// ----------------- +// interrupt manager +// ----------------- +typedef struct _gsl_intr_t +{ + gsl_flags_t flags; + gsl_device_t *device; + unsigned int enabled[GSL_INTR_BLOCK_COUNT]; + gsl_intr_handler_t handler[GSL_INTR_COUNT]; + oshandle_t evnt[GSL_INTR_COUNT]; +} gsl_intr_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_intr_init(gsl_device_t *device); +int kgsl_intr_close(gsl_device_t *device); +int kgsl_intr_attach(gsl_intr_t *intr, gsl_intrid_t id, gsl_intr_callback_t callback, void *cookie); +int kgsl_intr_detach(gsl_intr_t *intr, gsl_intrid_t id); +int kgsl_intr_enable(gsl_intr_t *intr, gsl_intrid_t id); +int kgsl_intr_disable(gsl_intr_t *intr, gsl_intrid_t id); +int kgsl_intr_isenabled(gsl_intr_t *intr, gsl_intrid_t id); +void kgsl_intr_decode(gsl_device_t *device, gsl_intrblock_t block_id); + +#endif // __GSL_INTMGR_H diff --git a/drivers/mxc/amd-gpu/include/gsl_ioctl.h b/drivers/mxc/amd-gpu/include/gsl_ioctl.h new file mode 100644 index 000000000000..6a06f3e0aec4 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_ioctl.h @@ -0,0 +1,243 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _GSL_IOCTL_H +#define _GSL_IOCTL_H + +#include "gsl_types.h" +#include "gsl_properties.h" + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +typedef struct _kgsl_device_start_t { + gsl_deviceid_t device_id; + gsl_flags_t flags; +} kgsl_device_start_t; + +typedef struct _kgsl_device_stop_t { + gsl_deviceid_t device_id; +} kgsl_device_stop_t; + +typedef struct _kgsl_device_idle_t { + gsl_deviceid_t device_id; + unsigned int timeout; +} kgsl_device_idle_t; + +typedef struct _kgsl_device_isidle_t { + gsl_deviceid_t device_id; +} kgsl_device_isidle_t; + +typedef struct _kgsl_device_getproperty_t { + gsl_deviceid_t device_id; + gsl_property_type_t type; + unsigned int *value; + unsigned int sizebytes; +} kgsl_device_getproperty_t; + +typedef struct _kgsl_device_setproperty_t { + gsl_deviceid_t device_id; + gsl_property_type_t type; + void *value; + unsigned int sizebytes; +} kgsl_device_setproperty_t; + +typedef struct _kgsl_device_regread_t { + gsl_deviceid_t device_id; + unsigned int offsetwords; + unsigned int *value; +} kgsl_device_regread_t; + +typedef struct _kgsl_device_regwrite_t { + gsl_deviceid_t device_id; + unsigned int offsetwords; + unsigned int value; +} kgsl_device_regwrite_t; + +typedef struct _kgsl_device_waitirq_t { + gsl_deviceid_t device_id; + gsl_intrid_t intr_id; + unsigned int *count; + unsigned int timeout; +} kgsl_device_waitirq_t; + +typedef struct _kgsl_cmdstream_issueibcmds_t { + gsl_deviceid_t device_id; + int drawctxt_index; + gpuaddr_t ibaddr; + int sizedwords; + gsl_timestamp_t *timestamp; + gsl_flags_t flags; +} kgsl_cmdstream_issueibcmds_t; + +typedef struct _kgsl_cmdstream_readtimestamp_t { + gsl_deviceid_t device_id; + gsl_timestamp_type_t type; + gsl_timestamp_t *timestamp; +} kgsl_cmdstream_readtimestamp_t; + +typedef struct _kgsl_cmdstream_freememontimestamp_t { + gsl_deviceid_t device_id; + gsl_memdesc_t *memdesc; + gsl_timestamp_t timestamp; + gsl_timestamp_type_t type; +} kgsl_cmdstream_freememontimestamp_t; + +typedef struct _kgsl_cmdstream_waittimestamp_t { + gsl_deviceid_t device_id; + gsl_timestamp_t timestamp; + unsigned int timeout; +} kgsl_cmdstream_waittimestamp_t; + +typedef struct _kgsl_cmdwindow_write_t { + gsl_deviceid_t device_id; + gsl_cmdwindow_t target; + unsigned int addr; + unsigned int data; +} kgsl_cmdwindow_write_t; + +typedef struct _kgsl_context_create_t { + gsl_deviceid_t device_id; + gsl_context_type_t type; + unsigned int *drawctxt_id; + gsl_flags_t flags; +} kgsl_context_create_t; + +typedef struct _kgsl_context_destroy_t { + gsl_deviceid_t device_id; + unsigned int drawctxt_id; +} kgsl_context_destroy_t; + +typedef struct _kgsl_drawctxt_bind_gmem_shadow_t { + gsl_deviceid_t device_id; + unsigned int drawctxt_id; + const gsl_rect_t* gmem_rect; + unsigned int shadow_x; + unsigned int shadow_y; + const gsl_buffer_desc_t* shadow_buffer; + unsigned int buffer_id; +} kgsl_drawctxt_bind_gmem_shadow_t; + +typedef struct _kgsl_sharedmem_alloc_t { + gsl_deviceid_t device_id; + gsl_flags_t flags; + int sizebytes; + gsl_memdesc_t *memdesc; +} kgsl_sharedmem_alloc_t; + +typedef struct _kgsl_sharedmem_free_t { + gsl_memdesc_t *memdesc; +} kgsl_sharedmem_free_t; + +typedef struct _kgsl_sharedmem_read_t { + const gsl_memdesc_t *memdesc; + unsigned int *dst; + unsigned int offsetbytes; + unsigned int sizebytes; +} kgsl_sharedmem_read_t; + +typedef struct _kgsl_sharedmem_write_t { + const gsl_memdesc_t *memdesc; + unsigned int offsetbytes; + unsigned int *src; + unsigned int sizebytes; +} kgsl_sharedmem_write_t; + +typedef struct _kgsl_sharedmem_set_t { + const gsl_memdesc_t *memdesc; + unsigned int offsetbytes; + unsigned int value; + unsigned int sizebytes; +} kgsl_sharedmem_set_t; + +typedef struct _kgsl_sharedmem_largestfreeblock_t { + gsl_deviceid_t device_id; + gsl_flags_t flags; + unsigned int *largestfreeblock; +} kgsl_sharedmem_largestfreeblock_t; + +typedef struct _kgsl_sharedmem_cacheoperation_t { + const gsl_memdesc_t *memdesc; + unsigned int offsetbytes; + unsigned int sizebytes; + unsigned int operation; +} kgsl_sharedmem_cacheoperation_t; + +typedef struct _kgsl_sharedmem_fromhostpointer_t { + gsl_deviceid_t device_id; + gsl_memdesc_t *memdesc; + void *hostptr; +} kgsl_sharedmem_fromhostpointer_t; + +typedef struct _kgsl_add_timestamp_t { + gsl_deviceid_t device_id; + gsl_timestamp_t *timestamp; +} kgsl_add_timestamp_t; + +typedef struct _kgsl_device_clock_t { + gsl_deviceid_t device; /* GSL_DEVICE_YAMATO = 1, GSL_DEVICE_G12 = 2 */ + int enable; /* 0: disable, 1: enable */ +} kgsl_device_clock_t; + +////////////////////////////////////////////////////////////////////////////// +// ioctl numbers +////////////////////////////////////////////////////////////////////////////// + +#define GSL_MAGIC 0xF9 +#define IOCTL_KGSL_DEVICE_START _IOW(GSL_MAGIC, 0x20, struct _kgsl_device_start_t) +#define IOCTL_KGSL_DEVICE_STOP _IOW(GSL_MAGIC, 0x21, struct _kgsl_device_stop_t) +#define IOCTL_KGSL_DEVICE_IDLE _IOW(GSL_MAGIC, 0x22, struct _kgsl_device_idle_t) +#define IOCTL_KGSL_DEVICE_ISIDLE _IOR(GSL_MAGIC, 0x23, struct _kgsl_device_isidle_t) +#define IOCTL_KGSL_DEVICE_GETPROPERTY _IOWR(GSL_MAGIC, 0x24, struct _kgsl_device_getproperty_t) +#define IOCTL_KGSL_DEVICE_SETPROPERTY _IOW(GSL_MAGIC, 0x25, struct _kgsl_device_setproperty_t) +#define IOCTL_KGSL_DEVICE_REGREAD _IOWR(GSL_MAGIC, 0x26, struct _kgsl_device_regread_t) +#define IOCTL_KGSL_DEVICE_REGWRITE _IOW(GSL_MAGIC, 0x27, struct _kgsl_device_regwrite_t) +#define IOCTL_KGSL_DEVICE_WAITIRQ _IOWR(GSL_MAGIC, 0x28, struct _kgsl_device_waitirq_t) +#define IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS _IOWR(GSL_MAGIC, 0x29, struct _kgsl_cmdstream_issueibcmds_t) +#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP _IOWR(GSL_MAGIC, 0x2A, struct _kgsl_cmdstream_readtimestamp_t) +#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP _IOW(GSL_MAGIC, 0x2B, struct _kgsl_cmdstream_freememontimestamp_t) +#define IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP _IOW(GSL_MAGIC, 0x2C, struct _kgsl_cmdstream_waittimestamp_t) +#define IOCTL_KGSL_CMDWINDOW_WRITE _IOW(GSL_MAGIC, 0x2D, struct _kgsl_cmdwindow_write_t) +#define IOCTL_KGSL_CONTEXT_CREATE _IOWR(GSL_MAGIC, 0x2E, struct _kgsl_context_create_t) +#define IOCTL_KGSL_CONTEXT_DESTROY _IOW(GSL_MAGIC, 0x2F, struct _kgsl_context_destroy_t) +#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW _IOW(GSL_MAGIC, 0x30, struct _kgsl_drawctxt_bind_gmem_shadow_t) +#define IOCTL_KGSL_SHAREDMEM_ALLOC _IOWR(GSL_MAGIC, 0x31, struct _kgsl_sharedmem_alloc_t) +#define IOCTL_KGSL_SHAREDMEM_FREE _IOW(GSL_MAGIC, 0x32, struct _kgsl_sharedmem_free_t) +#define IOCTL_KGSL_SHAREDMEM_READ _IOWR(GSL_MAGIC, 0x33, struct _kgsl_sharedmem_read_t) +#define IOCTL_KGSL_SHAREDMEM_WRITE _IOW(GSL_MAGIC, 0x34, struct _kgsl_sharedmem_write_t) +#define IOCTL_KGSL_SHAREDMEM_SET _IOW(GSL_MAGIC, 0x35, struct _kgsl_sharedmem_set_t) +#define IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK _IOWR(GSL_MAGIC, 0x36, struct _kgsl_sharedmem_largestfreeblock_t) +#define IOCTL_KGSL_SHAREDMEM_CACHEOPERATION _IOW(GSL_MAGIC, 0x37, struct _kgsl_sharedmem_cacheoperation_t) +#define IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER _IOW(GSL_MAGIC, 0x38, struct _kgsl_sharedmem_fromhostpointer_t) +#define IOCTL_KGSL_ADD_TIMESTAMP _IOWR(GSL_MAGIC, 0x39, struct _kgsl_add_timestamp_t) +#define IOCTL_KGSL_DRIVER_EXIT _IOWR(GSL_MAGIC, 0x3A, NULL) +#define IOCTL_KGSL_DEVICE_CLOCK _IOWR(GSL_MAGIC, 0x60, struct _kgsl_device_clock_t) + + +#endif diff --git a/drivers/mxc/amd-gpu/include/gsl_log.h b/drivers/mxc/amd-gpu/include/gsl_log.h new file mode 100644 index 000000000000..dbb7e4c6ef96 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_log.h @@ -0,0 +1,74 @@ +/* Copyright (c) 2002,2008-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_LOG_H +#define __GSL_LOG_H + +#define KGSL_LOG_GROUP_DRIVER 0x00000001 +#define KGSL_LOG_GROUP_DEVICE 0x00000002 +#define KGSL_LOG_GROUP_COMMAND 0x00000004 +#define KGSL_LOG_GROUP_CONTEXT 0x00000008 +#define KGSL_LOG_GROUP_MEMORY 0x00000010 +#define KGSL_LOG_GROUP_ALL 0x000000ff + +#define KGSL_LOG_LEVEL_ALL 0x0000ff00 +#define KGSL_LOG_LEVEL_TRACE 0x00003f00 +#define KGSL_LOG_LEVEL_DEBUG 0x00001f00 +#define KGSL_LOG_LEVEL_INFO 0x00000f00 +#define KGSL_LOG_LEVEL_WARN 0x00000700 +#define KGSL_LOG_LEVEL_ERROR 0x00000300 +#define KGSL_LOG_LEVEL_FATAL 0x00000100 + +#define KGSL_LOG_TIMESTAMP 0x00010000 +#define KGSL_LOG_THREAD_ID 0x00020000 +#define KGSL_LOG_PROCESS_ID 0x00040000 + +#ifdef GSL_LOG + +int kgsl_log_init(void); +int kgsl_log_close(void); +int kgsl_log_open_stdout( unsigned int log_flags ); +int kgsl_log_write( unsigned int log_flags, char* format, ... ); +int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ); +int kgsl_log_open_file( char* filename, unsigned int log_flags ); +int kgsl_log_flush_membuf( char* filename, int memBufId ); + +#else + +// Empty function definitions +OSINLINE int kgsl_log_init(void) { return GSL_SUCCESS; } +OSINLINE int kgsl_log_close(void) { return GSL_SUCCESS; } +OSINLINE int kgsl_log_open_stdout( unsigned int log_flags ) { (void)log_flags; return GSL_SUCCESS; } +OSINLINE int kgsl_log_write( unsigned int log_flags, char* format, ... ) { (void)log_flags; (void)format; return GSL_SUCCESS; } +OSINLINE int kgsl_log_open_membuf( int* memBufId, unsigned int log_flags ) { (void)memBufId; (void)log_flags; return GSL_SUCCESS; } +OSINLINE int kgsl_log_open_file( char* filename, unsigned int log_flags ) { (void)filename; (void)log_flags; return GSL_SUCCESS; } +OSINLINE int kgsl_log_flush_membuf( char* filename, int memBufId ) { (void) filename; (void) memBufId; return GSL_SUCCESS; } + +#endif + +#endif // __GSL_LOG_H diff --git a/drivers/mxc/amd-gpu/include/gsl_memmgr.h b/drivers/mxc/amd-gpu/include/gsl_memmgr.h new file mode 100644 index 000000000000..ef9ad93ea96e --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_memmgr.h @@ -0,0 +1,122 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_MEMMGR_H +#define __GSL_MEMMGR_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#define GSL_MEMARENA_NODE_POOL_MAX 32 // max is 32 + +#define GSL_MEMARENA_PAGE_DIST_MAX 12 // 4MB + +//#define GSL_MEMARENA_NODE_POOL_ENABLED + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// ------------------ +// memory arena stats +// ------------------ +typedef struct _gsl_memarena_stats_t { + __int64 bytes_read; + __int64 bytes_written; + __int64 allocs_success; + __int64 allocs_fail; + __int64 frees; + __int64 allocs_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX]; // 0=0--(4K-1), 1=4--(8K-1), 2=8--(16K-1),... max-1=(GSL_PAGESIZE<<(max-1))--infinity + __int64 frees_pagedistribution[GSL_MEMARENA_PAGE_DIST_MAX]; +} gsl_memarena_stats_t; + +// ------------ +// memory block +// ------------ +typedef struct _memblk_t { + unsigned int blkaddr; + unsigned int blksize; + struct _memblk_t *next; + struct _memblk_t *prev; + int nodepoolindex; +} memblk_t; + +// ---------------------- +// memory block free list +// ---------------------- +typedef struct _gsl_freelist_t { + memblk_t *head; + memblk_t *allocrover; + memblk_t *freerover; +} gsl_freelist_t; + +// ---------------------- +// memory block node pool +// ---------------------- +typedef struct _gsl_nodepool_t { + unsigned int priv; + memblk_t memblk[GSL_MEMARENA_NODE_POOL_MAX]; + struct _gsl_nodepool_t *next; + struct _gsl_nodepool_t *prev; +} gsl_nodepool_t; + +// ------------------- +// memory arena object +// ------------------- +typedef struct _gsl_memarena_t { + oshandle_t mutex; + unsigned int gpubaseaddr; + unsigned int hostbaseaddr; + unsigned int sizebytes; + gsl_nodepool_t *nodepool; + gsl_freelist_t freelist; + unsigned int priv; + +#ifdef GSL_STATS_MEM + gsl_memarena_stats_t stats; +#endif // GSL_STATS_MEM + +} gsl_memarena_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +gsl_memarena_t* kgsl_memarena_create(int aperture_id, int mmu_virtualized, unsigned int hostbaseaddr, gpuaddr_t gpubaseaddr, int sizebytes); +int kgsl_memarena_destroy(gsl_memarena_t *memarena); +int kgsl_memarena_isvirtualized(gsl_memarena_t *memarena); +int kgsl_memarena_querystats(gsl_memarena_t *memarena, gsl_memarena_stats_t *stats); +int kgsl_memarena_alloc(gsl_memarena_t *memarena, gsl_flags_t flags, int size, gsl_memdesc_t *memdesc); +void kgsl_memarena_free(gsl_memarena_t *memarena, gsl_memdesc_t *memdesc); +void* kgsl_memarena_gethostptr(gsl_memarena_t *memarena, gpuaddr_t gpuaddr); +unsigned int kgsl_memarena_getgpuaddr(gsl_memarena_t *memarena, void *hostptr); +unsigned int kgsl_memarena_getlargestfreeblock(gsl_memarena_t *memarena, gsl_flags_t flags); + +#endif // __GSL_MEMMGR_H diff --git a/drivers/mxc/amd-gpu/include/gsl_mmu.h b/drivers/mxc/amd-gpu/include/gsl_mmu.h new file mode 100644 index 000000000000..ddb2243b58d5 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_mmu.h @@ -0,0 +1,186 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_MMU_H +#define __GSL_MMU_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +#ifdef GSL_STATS_MMU +#define GSL_MMU_STATS(x) x +#else +#define GSL_MMU_STATS(x) +#endif // GSL_STATS_MMU + +#ifdef GSL_MMU_PAGETABLE_PERPROCESS +#define GSL_MMU_PAGETABLE_MAX GSL_CALLER_PROCESS_MAX // all device mmu's share a single page table per process +#else +#define GSL_MMU_PAGETABLE_MAX 1 // all device mmu's share a single global page table +#endif // GSL_MMU_PAGETABLE_PERPROCESS + +#define GSL_PT_SUPER_PTE 8 + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +#ifdef _DEBUG +// --------- +// mmu debug +// --------- +typedef struct _gsl_mmu_debug_t { + unsigned int config; + unsigned int mpu_base; + unsigned int mpu_end; + unsigned int va_range; + unsigned int pt_base; + unsigned int page_fault; + unsigned int trans_error; + unsigned int invalidate; +} gsl_mmu_debug_t; +#endif // _DEBUG + +// ------------ +// mmu register +// ------------ +typedef struct _gsl_mmu_reg_t +{ + unsigned int CONFIG; + unsigned int MPU_BASE; + unsigned int MPU_END; + unsigned int VA_RANGE; + unsigned int PT_BASE; + unsigned int PAGE_FAULT; + unsigned int TRAN_ERROR; + unsigned int INVALIDATE; +} gsl_mmu_reg_t; + +// ------------ +// mh interrupt +// ------------ +typedef struct _gsl_mh_intr_t +{ + gsl_intrid_t AXI_READ_ERROR; + gsl_intrid_t AXI_WRITE_ERROR; + gsl_intrid_t MMU_PAGE_FAULT; +} gsl_mh_intr_t; + +// ---------------- +// page table stats +// ---------------- +typedef struct _gsl_ptstats_t { + __int64 maps; + __int64 unmaps; + __int64 switches; +} gsl_ptstats_t; + +// --------- +// mmu stats +// --------- +typedef struct _gsl_mmustats_t { + gsl_ptstats_t pt; + __int64 tlbflushes; +} gsl_mmustats_t; + +// ----------------- +// page table object +// ----------------- +typedef struct _gsl_pagetable_t { + unsigned int pid; + unsigned int refcnt; + gsl_memdesc_t base; + gpuaddr_t va_base; + unsigned int va_range; + unsigned int last_superpte; + unsigned int max_entries; +} gsl_pagetable_t; + +// ------------------------- +// tlb flush filter object +// ------------------------- +typedef struct _gsl_tlbflushfilter_t { + unsigned int *base; + unsigned int size; +} gsl_tlbflushfilter_t; + +// ---------- +// mmu object +// ---------- +typedef struct _gsl_mmu_t { +#ifdef GSL_LOCKING_FINEGRAIN + oshandle_t mutex; +#endif + unsigned int refcnt; + gsl_flags_t flags; + gsl_device_t *device; + unsigned int config; + gpuaddr_t mpu_base; + int mpu_range; + gpuaddr_t va_base; + unsigned int va_range; + gsl_memdesc_t dummyspace; + gsl_tlbflushfilter_t tlbflushfilter; + gsl_pagetable_t *hwpagetable; // current page table object being used by device mmu + gsl_pagetable_t *pagetable[GSL_MMU_PAGETABLE_MAX]; // page table object table +#ifdef GSL_STATS_MMU + gsl_mmustats_t stats; +#endif // GSL_STATS_MMU +} gsl_mmu_t; + + +////////////////////////////////////////////////////////////////////////////// +// inline functions +////////////////////////////////////////////////////////////////////////////// +OSINLINE int +kgsl_mmu_isenabled(gsl_mmu_t *mmu) +{ + // address translation enabled + int enabled = ((mmu)->flags & GSL_FLAGS_STARTED) ? 1 : 0; + + return (enabled); +} + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_mmu_init(gsl_device_t *device); +int kgsl_mmu_close(gsl_device_t *device); +int kgsl_mmu_attachcallback(gsl_mmu_t *mmu, unsigned int pid); +int kgsl_mmu_detachcallback(gsl_mmu_t *mmu, unsigned int pid); +int kgsl_mmu_setpagetable(gsl_device_t *device, unsigned int pid); +int kgsl_mmu_map(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, const gsl_scatterlist_t *scatterlist, gsl_flags_t flags, unsigned int pid); +int kgsl_mmu_unmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, unsigned int pid); +int kgsl_mmu_getmap(gsl_mmu_t *mmu, gpuaddr_t gpubaseaddr, int range, gsl_scatterlist_t *scatterlist, unsigned int pid); +int kgsl_mmu_querystats(gsl_mmu_t *mmu, gsl_mmustats_t *stats); +int kgsl_mmu_bist(gsl_mmu_t *mmu); + +#endif // __GSL_MMU_H diff --git a/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h new file mode 100644 index 000000000000..57f6297735e2 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_ringbuffer.h @@ -0,0 +1,250 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_RINGBUFFER_H +#define __GSL_RINGBUFFER_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// + +// ringbuffer sizes log2quadword +#define GSL_RB_SIZE_8 0 +#define GSL_RB_SIZE_16 1 +#define GSL_RB_SIZE_32 2 +#define GSL_RB_SIZE_64 3 +#define GSL_RB_SIZE_128 4 +#define GSL_RB_SIZE_256 5 +#define GSL_RB_SIZE_512 6 +#define GSL_RB_SIZE_1K 7 +#define GSL_RB_SIZE_2K 8 +#define GSL_RB_SIZE_4K 9 +#define GSL_RB_SIZE_8K 10 +#define GSL_RB_SIZE_16K 11 +#define GSL_RB_SIZE_32K 12 +#define GSL_RB_SIZE_64K 13 +#define GSL_RB_SIZE_128K 14 +#define GSL_RB_SIZE_256K 15 +#define GSL_RB_SIZE_512K 16 +#define GSL_RB_SIZE_1M 17 +#define GSL_RB_SIZE_2M 18 +#define GSL_RB_SIZE_4M 19 + +// offsets into memptrs +#define GSL_RB_MEMPTRS_RPTR_OFFSET 0 +#define GSL_RB_MEMPTRS_WPTRPOLL_OFFSET (GSL_RB_MEMPTRS_RPTR_OFFSET + sizeof(unsigned int)) + +// dword base address of the GFX decode space +#define GSL_HAL_SUBBLOCK_OFFSET(reg) ((unsigned int)((reg) - (0x2000))) + +// CP timestamp register +#define mmCP_TIMESTAMP mmSCRATCH_REG0 + + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +#ifdef _DEBUG +// ---------------- +// ringbuffer debug +// ---------------- +typedef struct _gsl_rb_debug_t { + unsigned int pm4_ucode_rel; + unsigned int pfp_ucode_rel; + unsigned int cp_rb_base; + cp_rb_cntl_u cp_rb_cntl; + unsigned int cp_rb_rptr_addr; + unsigned int cp_rb_rptr; + unsigned int cp_rb_wptr; + unsigned int cp_rb_wptr_base; + scratch_umsk_u scratch_umsk; + unsigned int scratch_addr; + cp_me_cntl_u cp_me_cntl; + cp_me_status_u cp_me_status; + cp_debug_u cp_debug; + cp_stat_u cp_stat; + rbbm_status_u rbbm_status; + unsigned int sop_timestamp; + unsigned int eop_timestamp; +} gsl_rb_debug_t; +#endif // _DEBUG + +// ------------------- +// ringbuffer watchdog +// ------------------- +typedef struct _gsl_rbwatchdog_t { + gsl_flags_t flags; + unsigned int rptr_sample; +} gsl_rbwatchdog_t; + +// ------------------ +// memory ptr objects +// ------------------ +#ifdef __GNUC__ +#pragma pack(push, 1) +#else +#pragma pack(push) +#pragma pack(1) +#endif +typedef struct _gsl_rbmemptrs_t { + volatile int rptr; + int wptr_poll; +} gsl_rbmemptrs_t; +#pragma pack(pop) + +// ----- +// stats +// ----- +typedef struct _gsl_rbstats_t { + __int64 wraps; + __int64 issues; + __int64 wordstotal; +} gsl_rbstats_t; + + +// ----------------- +// ringbuffer object +// ----------------- +typedef struct _gsl_ringbuffer_t { + + gsl_device_t *device; + gsl_flags_t flags; +#ifdef GSL_LOCKING_FINEGRAIN + oshandle_t mutex; +#endif + gsl_memdesc_t buffer_desc; // allocated memory descriptor + gsl_memdesc_t memptrs_desc; + + gsl_rbmemptrs_t *memptrs; + + unsigned int sizedwords; // ring buffer size dwords + unsigned int blksizequadwords; + + unsigned int wptr; // write pointer offset in dwords from baseaddr + unsigned int rptr; // read pointer offset in dwords from baseaddr + gsl_timestamp_t timestamp; + + + gsl_rbwatchdog_t watchdog; + +#ifdef GSL_STATS_RINGBUFFER + gsl_rbstats_t stats; +#endif // GSL_STATS_RINGBUFFER + +} gsl_ringbuffer_t; + + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// + +#ifdef GSL_LOCKING_FINEGRAIN +#define GSL_RB_MUTEX_CREATE() rb->mutex = kos_mutex_create("gsl_ringbuffer"); \ + if (!rb->mutex) {return (GSL_FAILURE);} +#define GSL_RB_MUTEX_LOCK() kos_mutex_lock(rb->mutex) +#define GSL_RB_MUTEX_UNLOCK() kos_mutex_unlock(rb->mutex) +#define GSL_RB_MUTEX_FREE() kos_mutex_free(rb->mutex); rb->mutex = 0; +#else +#define GSL_RB_MUTEX_CREATE() +#define GSL_RB_MUTEX_LOCK() +#define GSL_RB_MUTEX_UNLOCK() +#define GSL_RB_MUTEX_FREE() +#endif + +// ---------- +// ring write +// ---------- +#define GSL_RB_WRITE(ring, data) \ + KGSL_DEBUG(GSL_DBGFLAGS_DUMPX, KGSL_DEBUG_DUMPX(BB_DUMP_RINGBUF_WRT, (unsigned int)ring, data, 0, "GSL_RB_WRITE")); \ + *(unsigned int *)(ring)++ = (unsigned int)(data); + +// --------- +// timestamp +// --------- +#ifdef GSL_DEVICE_SHADOW_MEMSTORE_TO_USER +#define GSL_RB_USE_MEM_TIMESTAMP +#endif //GSL_DEVICE_SHADOW_MEMSTORE_TO_USER + +#ifdef GSL_RB_USE_MEM_TIMESTAMP +#define GSL_RB_MEMPTRS_SCRATCH_MASK 0x1 // enable timestamp (...scratch0) memory shadowing +#define GSL_RB_INIT_TIMESTAMP(rb) + +#else +#define GSL_RB_MEMPTRS_SCRATCH_MASK 0x0 // disable +#define GSL_RB_INIT_TIMESTAMP(rb) kgsl_device_regwrite((rb)->device->id, mmCP_TIMESTAMP, 0); +#endif // GSL_RB_USE_MEMTIMESTAMP + +// -------- +// mem rptr +// -------- +#ifdef GSL_RB_USE_MEM_RPTR +#define GSL_RB_CNTL_NO_UPDATE 0x0 // enable +#define GSL_RB_GET_READPTR(rb, data) kgsl_sharedmem_read0(&(rb)->memptrs_desc, (data), GSL_RB_MEMPTRS_RPTR_OFFSET, 4, false) +#else +#define GSL_RB_CNTL_NO_UPDATE 0x1 // disable +#define GSL_RB_GET_READPTR(rb, data) (rb)->device->fbtl.device_regread((rb)->device, mmCP_RB_RPTR,(data)) +#endif // GSL_RB_USE_MEMRPTR + +// ------------ +// wptr polling +// ------------ +#ifdef GSL_RB_USE_WPTR_POLLING +#define GSL_RB_CNTL_POLL_EN 0x1 // enable +#define GSL_RB_UPDATE_WPTR_POLLING(rb) (rb)->memptrs->wptr_poll = (rb)->wptr +#else +#define GSL_RB_CNTL_POLL_EN 0x0 // disable +#define GSL_RB_UPDATE_WPTR_POLLING(rb) +#endif // GSL_RB_USE_WPTR_POLLING + +// ----- +// stats +// ----- +#ifdef GSL_STATS_RINGBUFFER +#define GSL_RB_STATS(x) x +#else +#define GSL_RB_STATS(x) +#endif // GSL_STATS_RINGBUFFER + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_ringbuffer_init(gsl_device_t *device); +int kgsl_ringbuffer_close(gsl_ringbuffer_t *rb); +int kgsl_ringbuffer_start(gsl_ringbuffer_t *rb); +int kgsl_ringbuffer_stop(gsl_ringbuffer_t *rb); +gsl_timestamp_t kgsl_ringbuffer_issuecmds(gsl_device_t *device, int pmodeoff, unsigned int *cmdaddr, int sizedwords, unsigned int pid); +int kgsl_ringbuffer_issueibcmds(gsl_device_t *device, int drawctxt_index, gpuaddr_t ibaddr, int sizedwords, gsl_timestamp_t *timestamp, gsl_flags_t flags); +void kgsl_ringbuffer_watchdog(void); + +int kgsl_ringbuffer_querystats(gsl_ringbuffer_t *rb, gsl_rbstats_t *stats); +int kgsl_ringbuffer_bist(gsl_ringbuffer_t *rb); + +#endif // __GSL_RINGBUFFER_H diff --git a/drivers/mxc/amd-gpu/include/gsl_sharedmem.h b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h new file mode 100644 index 000000000000..bb9692cc1e44 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_sharedmem.h @@ -0,0 +1,110 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_SHAREDMEM_H +#define __GSL_SHAREDMEM_H + + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// + +#define GSL_APERTURE_MASK 0x000000FF +#define GSL_DEVICEID_MASK 0x0000FF00 +#define GSL_EXTALLOC_MASK 0x000F0000 + +#define GSL_APERTURE_SHIFT 0 +#define GSL_DEVICEID_SHIFT 8 +#define GSL_EXTALLOC_SHIFT 16 + +#define GSL_APERTURE_GETGPUADDR(shmem, aperture_index) \ + shmem.apertures[aperture_index].memarena->gpubaseaddr; + +#define GSL_APERTURE_GETHOSTADDR(shmem, aperture_index) \ + shmem.apertures[aperture_index].memarena->hostbaseaddr; + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + +// --------------------- +// memory aperture stats +// --------------------- +typedef struct _gsl_aperture_stats_t +{ + gsl_apertureid_t id; + gsl_channelid_t channel; + gsl_memarena_stats_t memarena; +} gsl_aperture_stats_t; + +// ------------------- +// shared memory stats +// ------------------- +typedef struct _gsl_sharedmem_stats_t +{ + gsl_aperture_stats_t apertures[GSL_SHMEM_MAX_APERTURES]; +} gsl_sharedmem_stats_t; + +// --------------- +// memory aperture +// --------------- +typedef struct _gsl_aperture_t +{ + gsl_apertureid_t id; + gsl_channelid_t channel; + int numbanks; + gsl_memarena_t *memarena; +} gsl_aperture_t; + +// -------------------- +// shared memory object +// -------------------- +typedef struct _gsl_sharedmem_t +{ + gsl_flags_t flags; + unsigned int priv; + int numapertures; + gsl_aperture_t apertures[GSL_SHMEM_MAX_APERTURES]; + int aperturelookup[GSL_APERTURE_MAX][GSL_CHANNEL_MAX]; +} gsl_sharedmem_t; + + +////////////////////////////////////////////////////////////////////////////// +// prototypes +////////////////////////////////////////////////////////////////////////////// +int kgsl_sharedmem_init(gsl_sharedmem_t *shmem); +int kgsl_sharedmem_close(gsl_sharedmem_t *shmem); +int kgsl_sharedmem_alloc0(gsl_deviceid_t device_id, gsl_flags_t flags, int sizebytes, gsl_memdesc_t *memdesc); +int kgsl_sharedmem_free0(gsl_memdesc_t *memdesc, unsigned int pid); +int kgsl_sharedmem_read0(const gsl_memdesc_t *memdesc, void *dst, unsigned int offsetbytes, unsigned int sizebytes, unsigned int touserspace); +int kgsl_sharedmem_write0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, void *src, unsigned int sizebytes, unsigned int fromuserspace); +int kgsl_sharedmem_set0(const gsl_memdesc_t *memdesc, unsigned int offsetbytes, unsigned int value, unsigned int sizebytes); +int kgsl_sharedmem_querystats(gsl_sharedmem_t *shmem, gsl_sharedmem_stats_t *stats); +unsigned int kgsl_sharedmem_convertaddr(unsigned int addr, int type); + +#endif // __GSL_SHAREDMEM_H diff --git a/drivers/mxc/amd-gpu/include/gsl_tbdump.h b/drivers/mxc/amd-gpu/include/gsl_tbdump.h new file mode 100644 index 000000000000..53b30a8442e7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/gsl_tbdump.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora Forum nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_TBDUMP_H +#define __GSL_TBDUMP_H + +void tbdump_open(char* filename); +void tbdump_close(); +void tbdump_syncmem(unsigned int addr, unsigned int src, unsigned int sizebytes); +void tbdump_setmem(unsigned int addr, unsigned int value, unsigned int sizebytes); +void tbdump_slavewrite(unsigned int addr, unsigned int value); + +#endif // __GSL_TBDUMP_H diff --git a/drivers/mxc/amd-gpu/include/reg/g12_reg.h b/drivers/mxc/amd-gpu/include/reg/g12_reg.h new file mode 100644 index 000000000000..d12d419822a2 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/g12_reg.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _G12_H +#define _G12_H + +#ifdef _Z180 +#include "vgc/vgregs_z180.h" +#include "vgc/vgenums_z180.h" +#else +#include "vgc/vgregs_z160.h" +#include "vgc/vgenums_z160.h" +#endif + +#endif // _G12_H diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h new file mode 100644 index 000000000000..911c22fbbba6 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h @@ -0,0 +1,291 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REGS_ENUMS_H +#define __REGS_ENUMS_H + +typedef enum _BB_CULL { + BB_CULL_NONE = 0, + BB_CULL_CW = 1, + BB_CULL_CCW = 2, +} BB_CULL; + +typedef enum _BB_TEXTUREADDRESS { + BB_TADDRESS_WRAP = 0, + BB_TADDRESS_CLAMP = 1, + BB_TADDRESS_BORDER = 2, + BB_TADDRESS_MIRROR = 4, + BB_TADDRESS_MIRRORCLAMP = 5, // Not supported on G3x cores + BB_TADDRESS_MIRRORBORDER = 6, // Not supported on G3x cores +} BB_TEXTUREADDRESS; + +typedef enum _BB_TEXTYPE { + BB_TEXTYPE_4444 = 0, + BB_TEXTYPE_1555 = 1, + BB_TEXTYPE_5551 = 2, + BB_TEXTYPE_565 = 3, + BB_TEXTYPE_8888 = 4, + BB_TEXTYPE_8 = 5, + BB_TEXTYPE_88 = 6, + BB_TEXTYPE_4 = 7, + BB_TEXTYPE_44 = 8, + BB_TEXTYPE_UYVY = 9, + BB_TEXTYPE_YUY2 = 10, + BB_TEXTYPE_YVYU = 11, + BB_TEXTYPE_DXT1 = 12, + BB_TEXTYPE_PACKMAN = 13, + BB_TEXTYPE_PACKMAN_ALPHA4 = 14, + BB_TEXTYPE_1F16 = 15, + BB_TEXTYPE_2F16 = 16, + BB_TEXTYPE_4F16 = 17, + BB_TEXTYPE_IPACKMAN_RGB = 18, + BB_TEXTYPE_IPACKMAN_RGBA = 19, +} BB_TEXTYPE; + +typedef enum _BB_CMPFUNC { + BB_CMP_NEVER = 0, + BB_CMP_LESS = 1, + BB_CMP_EQUAL = 2, + BB_CMP_LESSEQUAL = 3, + BB_CMP_GREATER = 4, + BB_CMP_NOTEQUAL = 5, + BB_CMP_GREATEREQUAL = 6, + BB_CMP_ALWAYS = 7, +} BB_CMPFUNC; + +typedef enum _BB_STENCILOP { + BB_STENCILOP_KEEP = 0, + BB_STENCILOP_ZERO = 1, + BB_STENCILOP_REPLACE = 2, + BB_STENCILOP_INCRSAT = 3, + BB_STENCILOP_DECRSAT = 4, + BB_STENCILOP_INVERT = 5, + BB_STENCILOP_INCR = 6, + BB_STENCILOP_DECR = 7, +} BB_STENCILOP; + +typedef enum _BB_PRIMITIVETYPE { + BB_PT_POINTLIST = 0, + BB_PT_LINELIST = 1, + BB_PT_LINESTRIP = 2, + BB_PT_TRIANGLELIST = 3, + BB_PT_TRIANGLESTRIP = 4, + BB_PT_TRIANGLEFAN = 5, +} BB_PRIMITIVETYPE; + +typedef enum _BB_TEXTUREFILTERTYPE { + BB_TEXF_NONE = 0, // filtering disabled (valid for mip filter only) + BB_TEXF_POINT = 1, // nearest + BB_TEXF_LINEAR = 2, // linear interpolation +} BB_TEXTUREFILTERTYPE; + +typedef enum _BB_BUFFER { + BB_BUFFER_PPCODE = 0, // Pixel processor code + BB_BUFFER_UNUSED = 1, // Unused + BB_BUFFER_CBUF = 2, // Color buffer + BB_BUFFER_ZBUF = 3, // Z buffer + BB_BUFFER_AUXBUF0 = 4, // AUX0 buffer + BB_BUFFER_AUXBUF1 = 5, // AUX1 buffer + BB_BUFFER_AUXBUF2 = 6, // AUX2 buffer + BB_BUFFER_AUXBUF3 = 7, // AUX3 buffer +} BB_BUFFER; + +typedef enum _BB_COLORFORMAT { + BB_COLOR_ARGB4444 = 0, + BB_COLOR_ARGB0565 = 1, + BB_COLOR_ARGB1555 = 2, + BB_COLOR_RGBA5551 = 3, + BB_COLOR_ARGB8888 = 4, + BB_COLOR_R16 = 5, + BB_COLOR_RG1616 = 6, + BB_COLOR_ARGB16161616 = 7, + BB_COLOR_D16 = 8, + BB_COLOR_S4D12 = 9, + BB_COLOR_S1D15 = 10, + BB_COLOR_X8D24 = 11, + BB_COLOR_S8D24 = 12, + BB_COLOR_X2D30 = 13, +} BB_COLORFORMAT; + +typedef enum _BB_PP_REGCONFIG { + BB_PP_REGCONFIG_1 = 0, + BB_PP_REGCONFIG_2 = 1, + BB_PP_REGCONFIG_3 = 8, + BB_PP_REGCONFIG_4 = 2, + BB_PP_REGCONFIG_6 = 9, + BB_PP_REGCONFIG_8 = 3, + BB_PP_REGCONFIG_12 = 10, + BB_PP_REGCONFIG_16 = 4, + BB_PP_REGCONFIG_24 = 11, + BB_PP_REGCONFIG_32 = 5, +} BB_PP_REGCONFIG; + +typedef enum _G2D_read_t { + G2D_READ_DST = 0, + G2D_READ_SRC1 = 1, + G2D_READ_SRC2 = 2, + G2D_READ_SRC3 = 3, +} G2D_read_t; + +typedef enum _G2D_format_t { + G2D_1 = 0, // foreground & background + G2D_1BW = 1, // black & white + G2D_4 = 2, + G2D_8 = 3, // alpha + G2D_4444 = 4, + G2D_1555 = 5, + G2D_0565 = 6, + G2D_8888 = 7, + G2D_YUY2 = 8, + G2D_UYVY = 9, + G2D_YVYU = 10, + G2D_4444_RGBA = 11, + G2D_5551_RGBA = 12, + G2D_8888_RGBA = 13, + G2D_A8 = 14, // for alpha texture only +} G2D_format_t; + +typedef enum _G2D_wrap_t { + G2D_WRAP_CLAMP = 0, + G2D_WRAP_REPEAT = 1, + G2D_WRAP_MIRROR = 2, + G2D_WRAP_BORDER = 3, +} G2D_wrap_t; + +typedef enum _G2D_BLEND_OP { + G2D_BLENDOP_ADD = 0, + G2D_BLENDOP_SUB = 1, + G2D_BLENDOP_MIN = 2, + G2D_BLENDOP_MAX = 3, +} G2D_BLEND_OP; + +typedef enum _G2D_GRAD_OP { + G2D_GRADOP_DOT = 0, + G2D_GRADOP_RCP = 1, + G2D_GRADOP_SQRTMUL = 2, + G2D_GRADOP_SQRTADD = 3, +} G2D_GRAD_OP; + +typedef enum _G2D_BLEND_SRC { + G2D_BLENDSRC_ZERO = 0, // One with invert + G2D_BLENDSRC_SOURCE = 1, // Paint with coverage alpha applied + G2D_BLENDSRC_DESTINATION = 2, + G2D_BLENDSRC_IMAGE = 3, // Second texture + G2D_BLENDSRC_TEMP0 = 4, + G2D_BLENDSRC_TEMP1 = 5, + G2D_BLENDSRC_TEMP2 = 6, +} G2D_BLEND_SRC; + +typedef enum _G2D_BLEND_DST { + G2D_BLENDDST_IGNORE = 0, // Ignore destination + G2D_BLENDDST_TEMP0 = 1, + G2D_BLENDDST_TEMP1 = 2, + G2D_BLENDDST_TEMP2 = 3, +} G2D_BLEND_DST; + +typedef enum _G2D_BLEND_CONST { + G2D_BLENDSRC_CONST0 = 0, + G2D_BLENDSRC_CONST1 = 1, + G2D_BLENDSRC_CONST2 = 2, + G2D_BLENDSRC_CONST3 = 3, + G2D_BLENDSRC_CONST4 = 4, + G2D_BLENDSRC_CONST5 = 5, + G2D_BLENDSRC_CONST6 = 6, + G2D_BLENDSRC_CONST7 = 7, +} G2D_BLEND_CONST; + +typedef enum _V3_NEXTCMD { + VGV3_NEXTCMD_CONTINUE = 0, // Continue reading at current address, COUNT gives size of next packet. + VGV3_NEXTCMD_JUMP = 1, // Jump to CALLADDR, COUNT gives size of next packet. + VGV3_NEXTCMD_CALL = 2, // First call a sub-stream at CALLADDR for CALLCOUNT dwords. Then perform a continue. + VGV3_NEXTCMD_CALLV2TRUE = 3, // Not supported. + VGV3_NEXTCMD_CALLV2FALSE = 4, // Not supported. + VGV3_NEXTCMD_ABORT = 5, // Abort reading. This ends the stream. Normally stream can just be paused (or automatically pauses at the end) which avoids any data being lost. +} V3_NEXTCMD; + +typedef enum _V3_FORMAT { + VGV3_FORMAT_S8 = 0, // Signed 8 bit data (4 writes per data dword) => VGV2-float + VGV3_FORMAT_S16 = 1, // Signed 16 bit data (2 writes per data dword) => VGV2-float + VGV3_FORMAT_S32 = 2, // Signed 32 bit data => VGV2-float + VGV3_FORMAT_F32 = 3, // IEEE 32-bit floating point => VGV2-float + VGV3_FORMAT_RAW = 4, // No conversion +} V3_FORMAT; + +typedef enum _V2_ACTION { + VGV2_ACTION_END = 0, // end previous path + VGV2_ACTION_MOVETOOPEN = 1, // end previous path, C1=C4, start new open subpath + VGV2_ACTION_MOVETOCLOSED = 2, // end previous path, C1=C4, start new closed subpath + VGV2_ACTION_LINETO = 3, // line C1,C4 + VGV2_ACTION_CUBICTO = 4, // cubic C1,C2,C3,C4. + VGV2_ACTION_QUADTO = 5, // quadratic C1,C3,C4. + VGV2_ACTION_SCUBICTO = 6, // smooth cubic C1,C4. + VGV2_ACTION_SQUADTO = 7, // smooth quadratic C1,C3,C4. + VGV2_ACTION_VERTEXTO = 8, // half lineto C4=pos, C3=normal. + VGV2_ACTION_VERTEXTOOPEN = 9, // moveto open + half lineto C4=pos, C3=normal. + VGV2_ACTION_VERTEXTOCLOSED = 10, // moveto closed + half lineto C4=pos, C3=normal. + VGV2_ACTION_MOVETOMOVE = 11, // end previous path, C1=C4, move but do not start a subpath + VGV2_ACTION_FLUSH = 15, // end previous path and block following regwrites until all lines sent +} V2_ACTION; + +typedef enum _V2_CAP { + VGV2_CAP_BUTT = 0, // butt caps (straight line overlappin starting point + VGV2_CAP_ROUND = 1, // round caps (smoothness depends on ARCSIN/ARCCOS registers) + VGV2_CAP_SQUARE = 2, // square caps (square centered on starting point) +} V2_CAP; + +typedef enum _V2_JOIN { + VGV2_JOIN_MITER = 0, // miter joins (both sides extended towards intersection. If angle is too small (compared to STMITER register) the miter is converted into a BEVEL. + VGV2_JOIN_ROUND = 1, // round joins (smoothness depends on ARCSIN/ARCCOS registers) + VGV2_JOIN_BEVEL = 2, // bevel joins (ends of both sides are connected with a single line) +} V2_JOIN; + +enum +{ + G2D_GRADREG_X = 0, // also usable as temp + G2D_GRADREG_Y = 1, // also usable as temp + G2D_GRADREG_OUTX = 8, + G2D_GRADREG_OUTY = 9, + G2D_GRADREG_C0 = 16, + G2D_GRADREG_C1 = 17, + G2D_GRADREG_C2 = 18, + G2D_GRADREG_C3 = 19, + G2D_GRADREG_C4 = 20, + G2D_GRADREG_C5 = 21, + G2D_GRADREG_C6 = 22, + G2D_GRADREG_C7 = 23, + G2D_GRADREG_C8 = 24, + G2D_GRADREG_C9 = 25, + G2D_GRADREG_C10 = 26, + G2D_GRADREG_C11 = 27, + G2D_GRADREG_ZERO = 28, + G2D_GRADREG_ONE = 29, + G2D_GRADREG_MINUSONE = 30, +}; + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h new file mode 100644 index 000000000000..1660bc1c12a9 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h @@ -0,0 +1,3775 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REGS_G4X_DRIVER_H +#define __REGS_G4X_DRIVER_H + +#ifndef _LINUX +#include +#else +#ifndef assert +#define assert(expr) +#endif +#endif + +//----------------------------------------------------- +// REGISTER ADDRESSES +//----------------------------------------------------- + +#define ADDR_FBC_BASE 0x84 +#define ADDR_FBC_DATA 0x86 +#define ADDR_FBC_HEIGHT 0x8a +#define ADDR_FBC_START 0x8e +#define ADDR_FBC_STRIDE 0x8c +#define ADDR_FBC_WIDTH 0x88 +#define ADDR_VGC_CLOCKEN 0x508 +#define ADDR_VGC_COMMANDSTREAM 0x0 +#define ADDR_VGC_FIFOFREE 0x7c0 +#define ADDR_VGC_IRQENABLE 0x438 +#define ADDR_VGC_IRQSTATUS 0x418 +#define ADDR_VGC_IRQ_ACTIVE_CNT 0x4e0 +#define ADDR_VGC_MMUCOMMANDSTREAM 0x3fc +#define ADDR_VGC_REVISION 0x400 +#define ADDR_VGC_SYSSTATUS 0x410 +#define ADDR_G2D_ALPHABLEND 0xc +#define ADDR_G2D_BACKGROUND 0xb +#define ADDR_G2D_BASE0 0x0 +#define ADDR_G2D_BASE1 0x2 +#define ADDR_G2D_BASE2 0x4 +#define ADDR_G2D_BASE3 0x6 +#define ADDR_G2D_BLENDERCFG 0x11 +#define ADDR_G2D_BLEND_A0 0x14 +#define ADDR_G2D_BLEND_A1 0x15 +#define ADDR_G2D_BLEND_A2 0x16 +#define ADDR_G2D_BLEND_A3 0x17 +#define ADDR_G2D_BLEND_C0 0x18 +#define ADDR_G2D_BLEND_C1 0x19 +#define ADDR_G2D_BLEND_C2 0x1a +#define ADDR_G2D_BLEND_C3 0x1b +#define ADDR_G2D_BLEND_C4 0x1c +#define ADDR_G2D_BLEND_C5 0x1d +#define ADDR_G2D_BLEND_C6 0x1e +#define ADDR_G2D_BLEND_C7 0x1f +#define ADDR_G2D_CFG0 0x1 +#define ADDR_G2D_CFG1 0x3 +#define ADDR_G2D_CFG2 0x5 +#define ADDR_G2D_CFG3 0x7 +#define ADDR_G2D_COLOR 0xff +#define ADDR_G2D_CONFIG 0xe +#define ADDR_G2D_CONST0 0xb0 +#define ADDR_G2D_CONST1 0xb1 +#define ADDR_G2D_CONST2 0xb2 +#define ADDR_G2D_CONST3 0xb3 +#define ADDR_G2D_CONST4 0xb4 +#define ADDR_G2D_CONST5 0xb5 +#define ADDR_G2D_CONST6 0xb6 +#define ADDR_G2D_CONST7 0xb7 +#define ADDR_G2D_FOREGROUND 0xa +#define ADDR_G2D_GRADIENT 0xd0 +#define ADDR_G2D_IDLE 0xfe +#define ADDR_G2D_INPUT 0xf +#define ADDR_G2D_MASK 0x10 +#define ADDR_G2D_ROP 0xd +#define ADDR_G2D_SCISSORX 0x8 +#define ADDR_G2D_SCISSORY 0x9 +#define ADDR_G2D_SXY 0xf2 +#define ADDR_G2D_SXY2 0xf3 +#define ADDR_G2D_VGSPAN 0xf4 +#define ADDR_G2D_WIDTHHEIGHT 0xf1 +#define ADDR_G2D_XY 0xf0 +#define ADDR_GRADW_BORDERCOLOR 0xd4 +#define ADDR_GRADW_CONST0 0xc0 +#define ADDR_GRADW_CONST1 0xc1 +#define ADDR_GRADW_CONST2 0xc2 +#define ADDR_GRADW_CONST3 0xc3 +#define ADDR_GRADW_CONST4 0xc4 +#define ADDR_GRADW_CONST5 0xc5 +#define ADDR_GRADW_CONST6 0xc6 +#define ADDR_GRADW_CONST7 0xc7 +#define ADDR_GRADW_CONST8 0xc8 +#define ADDR_GRADW_CONST9 0xc9 +#define ADDR_GRADW_CONSTA 0xca +#define ADDR_GRADW_CONSTB 0xcb +#define ADDR_GRADW_INST0 0xe0 +#define ADDR_GRADW_INST1 0xe1 +#define ADDR_GRADW_INST2 0xe2 +#define ADDR_GRADW_INST3 0xe3 +#define ADDR_GRADW_INST4 0xe4 +#define ADDR_GRADW_INST5 0xe5 +#define ADDR_GRADW_INST6 0xe6 +#define ADDR_GRADW_INST7 0xe7 +#define ADDR_GRADW_TEXBASE 0xd3 +#define ADDR_GRADW_TEXCFG 0xd1 +#define ADDR_GRADW_TEXSIZE 0xd2 +#define ADDR_MH_ARBITER_CONFIG 0xa40 +#define ADDR_MH_AXI_ERROR 0xa45 +#define ADDR_MH_AXI_HALT_CONTROL 0xa50 +#define ADDR_MH_CLNT_AXI_ID_REUSE 0xa41 +#define ADDR_MH_DEBUG_CTRL 0xa4e +#define ADDR_MH_DEBUG_DATA 0xa4f +#define ADDR_MH_INTERRUPT_CLEAR 0xa44 +#define ADDR_MH_INTERRUPT_MASK 0xa42 +#define ADDR_MH_INTERRUPT_STATUS 0xa43 +#define ADDR_MH_MMU_CONFIG 0x40 +#define ADDR_MH_MMU_INVALIDATE 0x45 +#define ADDR_MH_MMU_MPU_BASE 0x46 +#define ADDR_MH_MMU_MPU_END 0x47 +#define ADDR_MH_MMU_PAGE_FAULT 0x43 +#define ADDR_MH_MMU_PT_BASE 0x42 +#define ADDR_MH_MMU_TRAN_ERROR 0x44 +#define ADDR_MH_MMU_VA_RANGE 0x41 +#define ADDR_MH_PERFCOUNTER0_CONFIG 0xa47 +#define ADDR_MH_PERFCOUNTER0_HI 0xa49 +#define ADDR_MH_PERFCOUNTER0_LOW 0xa48 +#define ADDR_MH_PERFCOUNTER0_SELECT 0xa46 +#define ADDR_MH_PERFCOUNTER1_CONFIG 0xa4b +#define ADDR_MH_PERFCOUNTER1_HI 0xa4d +#define ADDR_MH_PERFCOUNTER1_LOW 0xa4c +#define ADDR_MH_PERFCOUNTER1_SELECT 0xa4a +#define ADDR_MMU_READ_ADDR 0x510 +#define ADDR_MMU_READ_DATA 0x518 +#define ADDR_VGV1_CBASE1 0x2a +#define ADDR_VGV1_CFG1 0x27 +#define ADDR_VGV1_CFG2 0x28 +#define ADDR_VGV1_DIRTYBASE 0x29 +#define ADDR_VGV1_FILL 0x23 +#define ADDR_VGV1_SCISSORX 0x24 +#define ADDR_VGV1_SCISSORY 0x25 +#define ADDR_VGV1_TILEOFS 0x22 +#define ADDR_VGV1_UBASE2 0x2b +#define ADDR_VGV1_VTX0 0x20 +#define ADDR_VGV1_VTX1 0x21 +#define ADDR_VGV2_ACCURACY 0x60 +#define ADDR_VGV2_ACTION 0x6f +#define ADDR_VGV2_ARCCOS 0x62 +#define ADDR_VGV2_ARCSIN 0x63 +#define ADDR_VGV2_ARCTAN 0x64 +#define ADDR_VGV2_BBOXMAXX 0x5c +#define ADDR_VGV2_BBOXMAXY 0x5d +#define ADDR_VGV2_BBOXMINX 0x5a +#define ADDR_VGV2_BBOXMINY 0x5b +#define ADDR_VGV2_BIAS 0x5f +#define ADDR_VGV2_C1X 0x40 +#define ADDR_VGV2_C1XREL 0x48 +#define ADDR_VGV2_C1Y 0x41 +#define ADDR_VGV2_C1YREL 0x49 +#define ADDR_VGV2_C2X 0x42 +#define ADDR_VGV2_C2XREL 0x4a +#define ADDR_VGV2_C2Y 0x43 +#define ADDR_VGV2_C2YREL 0x4b +#define ADDR_VGV2_C3X 0x44 +#define ADDR_VGV2_C3XREL 0x4c +#define ADDR_VGV2_C3Y 0x45 +#define ADDR_VGV2_C3YREL 0x4d +#define ADDR_VGV2_C4X 0x46 +#define ADDR_VGV2_C4XREL 0x4e +#define ADDR_VGV2_C4Y 0x47 +#define ADDR_VGV2_C4YREL 0x4f +#define ADDR_VGV2_CLIP 0x68 +#define ADDR_VGV2_FIRST 0x40 +#define ADDR_VGV2_LAST 0x6f +#define ADDR_VGV2_MITER 0x66 +#define ADDR_VGV2_MODE 0x6e +#define ADDR_VGV2_RADIUS 0x65 +#define ADDR_VGV2_SCALE 0x5e +#define ADDR_VGV2_THINRADIUS 0x61 +#define ADDR_VGV2_XFSTXX 0x56 +#define ADDR_VGV2_XFSTXY 0x58 +#define ADDR_VGV2_XFSTYX 0x57 +#define ADDR_VGV2_XFSTYY 0x59 +#define ADDR_VGV2_XFXA 0x54 +#define ADDR_VGV2_XFXX 0x50 +#define ADDR_VGV2_XFXY 0x52 +#define ADDR_VGV2_XFYA 0x55 +#define ADDR_VGV2_XFYX 0x51 +#define ADDR_VGV2_XFYY 0x53 +#define ADDR_VGV3_CONTROL 0x70 +#define ADDR_VGV3_FIRST 0x70 +#define ADDR_VGV3_LAST 0x7f +#define ADDR_VGV3_MODE 0x71 +#define ADDR_VGV3_NEXTADDR 0x75 +#define ADDR_VGV3_NEXTCMD 0x76 +#define ADDR_VGV3_VGBYPASS 0x77 +#define ADDR_VGV3_WRITE 0x73 +#define ADDR_VGV3_WRITEADDR 0x72 +#define ADDR_VGV3_WRITEDMI 0x7d +#define ADDR_VGV3_WRITEF32 0x7b +#define ADDR_VGV3_WRITEIFPAUSED 0x74 +#define ADDR_VGV3_WRITERAW 0x7c +#define ADDR_VGV3_WRITES16 0x79 +#define ADDR_VGV3_WRITES32 0x7a +#define ADDR_VGV3_WRITES8 0x78 + +// FBC_BASE +typedef struct _REG_FBC_BASE { + unsigned BASE : 32; +} REG_FBC_BASE; + +// FBC_DATA +typedef struct _REG_FBC_DATA { + unsigned DATA : 32; +} REG_FBC_DATA; + +// FBC_HEIGHT +typedef struct _REG_FBC_HEIGHT { + unsigned HEIGHT : 11; +} REG_FBC_HEIGHT; + +// FBC_START +typedef struct _REG_FBC_START { + unsigned DUMMY : 1; +} REG_FBC_START; + +// FBC_STRIDE +typedef struct _REG_FBC_STRIDE { + unsigned STRIDE : 11; +} REG_FBC_STRIDE; + +// FBC_WIDTH +typedef struct _REG_FBC_WIDTH { + unsigned WIDTH : 11; +} REG_FBC_WIDTH; + +// VGC_CLOCKEN +typedef struct _REG_VGC_CLOCKEN { + unsigned BCACHE : 1; + unsigned G2D_VGL3 : 1; + unsigned VG_L1L2 : 1; + unsigned RESERVED : 3; +} REG_VGC_CLOCKEN; + +// VGC_COMMANDSTREAM +typedef struct _REG_VGC_COMMANDSTREAM { + unsigned DATA : 32; +} REG_VGC_COMMANDSTREAM; + +// VGC_FIFOFREE +typedef struct _REG_VGC_FIFOFREE { + unsigned FREE : 1; +} REG_VGC_FIFOFREE; + +// VGC_IRQENABLE +typedef struct _REG_VGC_IRQENABLE { + unsigned MH : 1; + unsigned G2D : 1; + unsigned FIFO : 1; + unsigned FBC : 1; +} REG_VGC_IRQENABLE; + +// VGC_IRQSTATUS +typedef struct _REG_VGC_IRQSTATUS { + unsigned MH : 1; + unsigned G2D : 1; + unsigned FIFO : 1; + unsigned FBC : 1; +} REG_VGC_IRQSTATUS; + +// VGC_IRQ_ACTIVE_CNT +typedef struct _REG_VGC_IRQ_ACTIVE_CNT { + unsigned MH : 8; + unsigned G2D : 8; + unsigned ERRORS : 8; + unsigned FBC : 8; +} REG_VGC_IRQ_ACTIVE_CNT; + +// VGC_MMUCOMMANDSTREAM +typedef struct _REG_VGC_MMUCOMMANDSTREAM { + unsigned DATA : 32; +} REG_VGC_MMUCOMMANDSTREAM; + +// VGC_REVISION +typedef struct _REG_VGC_REVISION { + unsigned MINOR_REVISION : 4; + unsigned MAJOR_REVISION : 4; +} REG_VGC_REVISION; + +// VGC_SYSSTATUS +typedef struct _REG_VGC_SYSSTATUS { + unsigned RESET : 1; +} REG_VGC_SYSSTATUS; + +// G2D_ALPHABLEND +typedef struct _REG_G2D_ALPHABLEND { + unsigned ALPHA : 8; + unsigned OBS_ENABLE : 1; + unsigned CONSTANT : 1; + unsigned INVERT : 1; + unsigned OPTIMIZE : 1; + unsigned MODULATE : 1; + unsigned INVERTMASK : 1; + unsigned PREMULTIPLYDST : 1; + unsigned MASKTOALPHA : 1; +} REG_G2D_ALPHABLEND; + +// G2D_BACKGROUND +typedef struct _REG_G2D_BACKGROUND { + unsigned COLOR : 32; +} REG_G2D_BACKGROUND; + +// G2D_BASE0 +typedef struct _REG_G2D_BASE0 { + unsigned ADDR : 32; +} REG_G2D_BASE0; + +// G2D_BASE1 +typedef struct _REG_G2D_BASE1 { + unsigned ADDR : 32; +} REG_G2D_BASE1; + +// G2D_BASE2 +typedef struct _REG_G2D_BASE2 { + unsigned ADDR : 32; +} REG_G2D_BASE2; + +// G2D_BASE3 +typedef struct _REG_G2D_BASE3 { + unsigned ADDR : 32; +} REG_G2D_BASE3; + +// G2D_BLENDERCFG +typedef struct _REG_G2D_BLENDERCFG { + unsigned PASSES : 3; + unsigned ALPHAPASSES : 2; + unsigned ENABLE : 1; + unsigned OOALPHA : 1; + unsigned OBS_DIVALPHA : 1; + unsigned NOMASK : 1; +} REG_G2D_BLENDERCFG; + +// G2D_BLEND_A0 +typedef struct _REG_G2D_BLEND_A0 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A0; + +// G2D_BLEND_A1 +typedef struct _REG_G2D_BLEND_A1 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A1; + +// G2D_BLEND_A2 +typedef struct _REG_G2D_BLEND_A2 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A2; + +// G2D_BLEND_A3 +typedef struct _REG_G2D_BLEND_A3 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A3; + +// G2D_BLEND_C0 +typedef struct _REG_G2D_BLEND_C0 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C0; + +// G2D_BLEND_C1 +typedef struct _REG_G2D_BLEND_C1 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C1; + +// G2D_BLEND_C2 +typedef struct _REG_G2D_BLEND_C2 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C2; + +// G2D_BLEND_C3 +typedef struct _REG_G2D_BLEND_C3 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C3; + +// G2D_BLEND_C4 +typedef struct _REG_G2D_BLEND_C4 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C4; + +// G2D_BLEND_C5 +typedef struct _REG_G2D_BLEND_C5 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C5; + +// G2D_BLEND_C6 +typedef struct _REG_G2D_BLEND_C6 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C6; + +// G2D_BLEND_C7 +typedef struct _REG_G2D_BLEND_C7 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C7; + +// G2D_CFG0 +typedef struct _REG_G2D_CFG0 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG0; + +// G2D_CFG1 +typedef struct _REG_G2D_CFG1 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG1; + +// G2D_CFG2 +typedef struct _REG_G2D_CFG2 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG2; + +// G2D_CFG3 +typedef struct _REG_G2D_CFG3 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG3; + +// G2D_COLOR +typedef struct _REG_G2D_COLOR { + unsigned ARGB : 32; +} REG_G2D_COLOR; + +// G2D_CONFIG +typedef struct _REG_G2D_CONFIG { + unsigned DST : 1; + unsigned SRC1 : 1; + unsigned SRC2 : 1; + unsigned SRC3 : 1; + unsigned SRCCK : 1; + unsigned DSTCK : 1; + unsigned ROTATE : 2; + unsigned OBS_GAMMA : 1; + unsigned IGNORECKALPHA : 1; + unsigned DITHER : 1; + unsigned WRITESRGB : 1; + unsigned ARGBMASK : 4; + unsigned ALPHATEX : 1; + unsigned PALMLINES : 1; + unsigned NOLASTPIXEL : 1; + unsigned NOPROTECT : 1; +} REG_G2D_CONFIG; + +// G2D_CONST0 +typedef struct _REG_G2D_CONST0 { + unsigned ARGB : 32; +} REG_G2D_CONST0; + +// G2D_CONST1 +typedef struct _REG_G2D_CONST1 { + unsigned ARGB : 32; +} REG_G2D_CONST1; + +// G2D_CONST2 +typedef struct _REG_G2D_CONST2 { + unsigned ARGB : 32; +} REG_G2D_CONST2; + +// G2D_CONST3 +typedef struct _REG_G2D_CONST3 { + unsigned ARGB : 32; +} REG_G2D_CONST3; + +// G2D_CONST4 +typedef struct _REG_G2D_CONST4 { + unsigned ARGB : 32; +} REG_G2D_CONST4; + +// G2D_CONST5 +typedef struct _REG_G2D_CONST5 { + unsigned ARGB : 32; +} REG_G2D_CONST5; + +// G2D_CONST6 +typedef struct _REG_G2D_CONST6 { + unsigned ARGB : 32; +} REG_G2D_CONST6; + +// G2D_CONST7 +typedef struct _REG_G2D_CONST7 { + unsigned ARGB : 32; +} REG_G2D_CONST7; + +// G2D_FOREGROUND +typedef struct _REG_G2D_FOREGROUND { + unsigned COLOR : 32; +} REG_G2D_FOREGROUND; + +// G2D_GRADIENT +typedef struct _REG_G2D_GRADIENT { + unsigned INSTRUCTIONS : 3; + unsigned INSTRUCTIONS2 : 3; + unsigned ENABLE : 1; + unsigned ENABLE2 : 1; + unsigned SEL : 1; +} REG_G2D_GRADIENT; + +// G2D_IDLE +typedef struct _REG_G2D_IDLE { + unsigned IRQ : 1; + unsigned BCFLUSH : 1; + unsigned V3 : 1; +} REG_G2D_IDLE; + +// G2D_INPUT +typedef struct _REG_G2D_INPUT { + unsigned COLOR : 1; + unsigned SCOORD1 : 1; + unsigned SCOORD2 : 1; + unsigned COPYCOORD : 1; + unsigned VGMODE : 1; + unsigned LINEMODE : 1; +} REG_G2D_INPUT; + +// G2D_MASK +typedef struct _REG_G2D_MASK { + unsigned YMASK : 12; + unsigned XMASK : 12; +} REG_G2D_MASK; + +// G2D_ROP +typedef struct _REG_G2D_ROP { + unsigned ROP : 16; +} REG_G2D_ROP; + +// G2D_SCISSORX +typedef struct _REG_G2D_SCISSORX { + unsigned LEFT : 11; + unsigned RIGHT : 11; +} REG_G2D_SCISSORX; + +// G2D_SCISSORY +typedef struct _REG_G2D_SCISSORY { + unsigned TOP : 11; + unsigned BOTTOM : 11; +} REG_G2D_SCISSORY; + +// G2D_SXY +typedef struct _REG_G2D_SXY { + unsigned Y : 11; + unsigned PAD : 5; + unsigned X : 11; +} REG_G2D_SXY; + +// G2D_SXY2 +typedef struct _REG_G2D_SXY2 { + unsigned Y : 11; + unsigned PAD : 5; + unsigned X : 11; +} REG_G2D_SXY2; + +// G2D_VGSPAN +typedef struct _REG_G2D_VGSPAN { + int WIDTH : 12; + unsigned PAD : 4; + unsigned COVERAGE : 4; +} REG_G2D_VGSPAN; + +// G2D_WIDTHHEIGHT +typedef struct _REG_G2D_WIDTHHEIGHT { + int HEIGHT : 12; + unsigned PAD : 4; + int WIDTH : 12; +} REG_G2D_WIDTHHEIGHT; + +// G2D_XY +typedef struct _REG_G2D_XY { + int Y : 12; + unsigned PAD : 4; + int X : 12; +} REG_G2D_XY; + +// GRADW_BORDERCOLOR +typedef struct _REG_GRADW_BORDERCOLOR { + unsigned COLOR : 32; +} REG_GRADW_BORDERCOLOR; + +// GRADW_CONST0 +typedef struct _REG_GRADW_CONST0 { + unsigned VALUE : 16; +} REG_GRADW_CONST0; + +// GRADW_CONST1 +typedef struct _REG_GRADW_CONST1 { + unsigned VALUE : 16; +} REG_GRADW_CONST1; + +// GRADW_CONST2 +typedef struct _REG_GRADW_CONST2 { + unsigned VALUE : 16; +} REG_GRADW_CONST2; + +// GRADW_CONST3 +typedef struct _REG_GRADW_CONST3 { + unsigned VALUE : 16; +} REG_GRADW_CONST3; + +// GRADW_CONST4 +typedef struct _REG_GRADW_CONST4 { + unsigned VALUE : 16; +} REG_GRADW_CONST4; + +// GRADW_CONST5 +typedef struct _REG_GRADW_CONST5 { + unsigned VALUE : 16; +} REG_GRADW_CONST5; + +// GRADW_CONST6 +typedef struct _REG_GRADW_CONST6 { + unsigned VALUE : 16; +} REG_GRADW_CONST6; + +// GRADW_CONST7 +typedef struct _REG_GRADW_CONST7 { + unsigned VALUE : 16; +} REG_GRADW_CONST7; + +// GRADW_CONST8 +typedef struct _REG_GRADW_CONST8 { + unsigned VALUE : 16; +} REG_GRADW_CONST8; + +// GRADW_CONST9 +typedef struct _REG_GRADW_CONST9 { + unsigned VALUE : 16; +} REG_GRADW_CONST9; + +// GRADW_CONSTA +typedef struct _REG_GRADW_CONSTA { + unsigned VALUE : 16; +} REG_GRADW_CONSTA; + +// GRADW_CONSTB +typedef struct _REG_GRADW_CONSTB { + unsigned VALUE : 16; +} REG_GRADW_CONSTB; + +// GRADW_INST0 +typedef struct _REG_GRADW_INST0 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST0; + +// GRADW_INST1 +typedef struct _REG_GRADW_INST1 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST1; + +// GRADW_INST2 +typedef struct _REG_GRADW_INST2 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST2; + +// GRADW_INST3 +typedef struct _REG_GRADW_INST3 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST3; + +// GRADW_INST4 +typedef struct _REG_GRADW_INST4 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST4; + +// GRADW_INST5 +typedef struct _REG_GRADW_INST5 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST5; + +// GRADW_INST6 +typedef struct _REG_GRADW_INST6 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST6; + +// GRADW_INST7 +typedef struct _REG_GRADW_INST7 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST7; + +// GRADW_TEXBASE +typedef struct _REG_GRADW_TEXBASE { + unsigned ADDR : 32; +} REG_GRADW_TEXBASE; + +// GRADW_TEXCFG +typedef struct _REG_GRADW_TEXCFG { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned WRAPU : 2; + unsigned WRAPV : 2; + unsigned BILIN : 1; + unsigned SRGB : 1; + unsigned PREMULTIPLY : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned TEX2D : 1; + unsigned SWAPBITS : 1; +} REG_GRADW_TEXCFG; + +// GRADW_TEXSIZE +typedef struct _REG_GRADW_TEXSIZE { + unsigned WIDTH : 11; + unsigned HEIGHT : 11; +} REG_GRADW_TEXSIZE; + +// MH_ARBITER_CONFIG +typedef struct _REG_MH_ARBITER_CONFIG { + unsigned SAME_PAGE_LIMIT : 6; + unsigned SAME_PAGE_GRANULARITY : 1; + unsigned L1_ARB_ENABLE : 1; + unsigned L1_ARB_HOLD_ENABLE : 1; + unsigned L2_ARB_CONTROL : 1; + unsigned PAGE_SIZE : 3; + unsigned TC_REORDER_ENABLE : 1; + unsigned TC_ARB_HOLD_ENABLE : 1; + unsigned IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned IN_FLIGHT_LIMIT : 6; + unsigned CP_CLNT_ENABLE : 1; + unsigned VGT_CLNT_ENABLE : 1; + unsigned TC_CLNT_ENABLE : 1; + unsigned RB_CLNT_ENABLE : 1; + unsigned PA_CLNT_ENABLE : 1; +} REG_MH_ARBITER_CONFIG; + +// MH_AXI_ERROR +typedef struct _REG_MH_AXI_ERROR { + unsigned AXI_READ_ID : 3; + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ID : 3; + unsigned AXI_WRITE_ERROR : 1; +} REG_MH_AXI_ERROR; + +// MH_AXI_HALT_CONTROL +typedef struct _REG_MH_AXI_HALT_CONTROL { + unsigned AXI_HALT : 1; +} REG_MH_AXI_HALT_CONTROL; + +// MH_CLNT_AXI_ID_REUSE +typedef struct _REG_MH_CLNT_AXI_ID_REUSE { + unsigned CPW_ID : 3; + unsigned PAD : 1; + unsigned RBW_ID : 3; + unsigned PAD2 : 1; + unsigned MMUR_ID : 3; + unsigned PAD3 : 1; + unsigned PAW_ID : 3; +} REG_MH_CLNT_AXI_ID_REUSE; + +// MH_DEBUG_CTRL +typedef struct _REG_MH_DEBUG_CTRL { + unsigned INDEX : 6; +} REG_MH_DEBUG_CTRL; + +// MH_DEBUG_DATA +typedef struct _REG_MH_DEBUG_DATA { + unsigned DATA : 32; +} REG_MH_DEBUG_DATA; + +// MH_INTERRUPT_CLEAR +typedef struct _REG_MH_INTERRUPT_CLEAR { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_CLEAR; + +// MH_INTERRUPT_MASK +typedef struct _REG_MH_INTERRUPT_MASK { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_MASK; + +// MH_INTERRUPT_STATUS +typedef struct _REG_MH_INTERRUPT_STATUS { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_STATUS; + +// MH_MMU_CONFIG +typedef struct _REG_MH_MMU_CONFIG { + unsigned MMU_ENABLE : 1; + unsigned SPLIT_MODE_ENABLE : 1; + unsigned PAD : 2; + unsigned RB_W_CLNT_BEHAVIOR : 2; + unsigned CP_W_CLNT_BEHAVIOR : 2; + unsigned CP_R0_CLNT_BEHAVIOR : 2; + unsigned CP_R1_CLNT_BEHAVIOR : 2; + unsigned CP_R2_CLNT_BEHAVIOR : 2; + unsigned CP_R3_CLNT_BEHAVIOR : 2; + unsigned CP_R4_CLNT_BEHAVIOR : 2; + unsigned VGT_R0_CLNT_BEHAVIOR : 2; + unsigned VGT_R1_CLNT_BEHAVIOR : 2; + unsigned TC_R_CLNT_BEHAVIOR : 2; + unsigned PA_W_CLNT_BEHAVIOR : 2; +} REG_MH_MMU_CONFIG; + +// MH_MMU_INVALIDATE +typedef struct _REG_MH_MMU_INVALIDATE { + unsigned INVALIDATE_ALL : 1; + unsigned INVALIDATE_TC : 1; +} REG_MH_MMU_INVALIDATE; + +// MH_MMU_MPU_BASE +typedef struct _REG_MH_MMU_MPU_BASE { + unsigned ZERO : 12; + unsigned MPU_BASE : 20; +} REG_MH_MMU_MPU_BASE; + +// MH_MMU_MPU_END +typedef struct _REG_MH_MMU_MPU_END { + unsigned ZERO : 12; + unsigned MPU_END : 20; +} REG_MH_MMU_MPU_END; + +// MH_MMU_PAGE_FAULT +typedef struct _REG_MH_MMU_PAGE_FAULT { + unsigned PAGE_FAULT : 1; + unsigned OP_TYPE : 1; + unsigned CLNT_BEHAVIOR : 2; + unsigned AXI_ID : 3; + unsigned PAD : 1; + unsigned MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned ADDRESS_OUT_OF_RANGE : 1; + unsigned READ_PROTECTION_ERROR : 1; + unsigned WRITE_PROTECTION_ERROR : 1; + unsigned REQ_VA : 20; +} REG_MH_MMU_PAGE_FAULT; + +// MH_MMU_PT_BASE +typedef struct _REG_MH_MMU_PT_BASE { + unsigned ZERO : 12; + unsigned PT_BASE : 20; +} REG_MH_MMU_PT_BASE; + +// MH_MMU_TRAN_ERROR +typedef struct _REG_MH_MMU_TRAN_ERROR { + unsigned ZERO : 5; + unsigned TRAN_ERROR : 27; +} REG_MH_MMU_TRAN_ERROR; + +// MH_MMU_VA_RANGE +typedef struct _REG_MH_MMU_VA_RANGE { + unsigned NUM_64KB_REGIONS : 12; + unsigned VA_BASE : 20; +} REG_MH_MMU_VA_RANGE; + +// MH_PERFCOUNTER0_CONFIG +typedef struct _REG_MH_PERFCOUNTER0_CONFIG { + unsigned N_VALUE : 8; +} REG_MH_PERFCOUNTER0_CONFIG; + +// MH_PERFCOUNTER0_HI +typedef struct _REG_MH_PERFCOUNTER0_HI { + unsigned PERF_COUNTER_HI : 16; +} REG_MH_PERFCOUNTER0_HI; + +// MH_PERFCOUNTER0_LOW +typedef struct _REG_MH_PERFCOUNTER0_LOW { + unsigned PERF_COUNTER_LOW : 32; +} REG_MH_PERFCOUNTER0_LOW; + +// MH_PERFCOUNTER0_SELECT +typedef struct _REG_MH_PERFCOUNTER0_SELECT { + unsigned PERF_SEL : 8; +} REG_MH_PERFCOUNTER0_SELECT; + +// MH_PERFCOUNTER1_CONFIG +typedef struct _REG_MH_PERFCOUNTER1_CONFIG { + unsigned N_VALUE : 8; +} REG_MH_PERFCOUNTER1_CONFIG; + +// MH_PERFCOUNTER1_HI +typedef struct _REG_MH_PERFCOUNTER1_HI { + unsigned PERF_COUNTER_HI : 16; +} REG_MH_PERFCOUNTER1_HI; + +// MH_PERFCOUNTER1_LOW +typedef struct _REG_MH_PERFCOUNTER1_LOW { + unsigned PERF_COUNTER_LOW : 32; +} REG_MH_PERFCOUNTER1_LOW; + +// MH_PERFCOUNTER1_SELECT +typedef struct _REG_MH_PERFCOUNTER1_SELECT { + unsigned PERF_SEL : 8; +} REG_MH_PERFCOUNTER1_SELECT; + +// MMU_READ_ADDR +typedef struct _REG_MMU_READ_ADDR { + unsigned ADDR : 15; +} REG_MMU_READ_ADDR; + +// MMU_READ_DATA +typedef struct _REG_MMU_READ_DATA { + unsigned DATA : 32; +} REG_MMU_READ_DATA; + +// VGV1_CBASE1 +typedef struct _REG_VGV1_CBASE1 { + unsigned ADDR : 32; +} REG_VGV1_CBASE1; + +// VGV1_CFG1 +typedef struct _REG_VGV1_CFG1 { + unsigned WINDRULE : 1; +} REG_VGV1_CFG1; + +// VGV1_CFG2 +typedef struct _REG_VGV1_CFG2 { + unsigned AAMODE : 2; +} REG_VGV1_CFG2; + +// VGV1_DIRTYBASE +typedef struct _REG_VGV1_DIRTYBASE { + unsigned ADDR : 32; +} REG_VGV1_DIRTYBASE; + +// VGV1_FILL +typedef struct _REG_VGV1_FILL { + unsigned INHERIT : 1; +} REG_VGV1_FILL; + +// VGV1_SCISSORX +typedef struct _REG_VGV1_SCISSORX { + unsigned LEFT : 11; + unsigned PAD : 5; + unsigned RIGHT : 11; +} REG_VGV1_SCISSORX; + +// VGV1_SCISSORY +typedef struct _REG_VGV1_SCISSORY { + unsigned TOP : 11; + unsigned PAD : 5; + unsigned BOTTOM : 11; +} REG_VGV1_SCISSORY; + +// VGV1_TILEOFS +typedef struct _REG_VGV1_TILEOFS { + unsigned X : 12; + unsigned Y : 12; + unsigned LEFTMOST : 1; +} REG_VGV1_TILEOFS; + +// VGV1_UBASE2 +typedef struct _REG_VGV1_UBASE2 { + unsigned ADDR : 32; +} REG_VGV1_UBASE2; + +// VGV1_VTX0 +typedef struct _REG_VGV1_VTX0 { + int X : 16; + int Y : 16; +} REG_VGV1_VTX0; + +// VGV1_VTX1 +typedef struct _REG_VGV1_VTX1 { + int X : 16; + int Y : 16; +} REG_VGV1_VTX1; + +// VGV2_ACCURACY +typedef struct _REG_VGV2_ACCURACY { + unsigned F : 24; +} REG_VGV2_ACCURACY; + +// VGV2_ACTION +typedef struct _REG_VGV2_ACTION { + unsigned ACTION : 4; +} REG_VGV2_ACTION; + +// VGV2_ARCCOS +typedef struct _REG_VGV2_ARCCOS { + unsigned F : 24; +} REG_VGV2_ARCCOS; + +// VGV2_ARCSIN +typedef struct _REG_VGV2_ARCSIN { + unsigned F : 24; +} REG_VGV2_ARCSIN; + +// VGV2_ARCTAN +typedef struct _REG_VGV2_ARCTAN { + unsigned F : 24; +} REG_VGV2_ARCTAN; + +// VGV2_BBOXMAXX +typedef struct _REG_VGV2_BBOXMAXX { + unsigned F : 24; +} REG_VGV2_BBOXMAXX; + +// VGV2_BBOXMAXY +typedef struct _REG_VGV2_BBOXMAXY { + unsigned F : 24; +} REG_VGV2_BBOXMAXY; + +// VGV2_BBOXMINX +typedef struct _REG_VGV2_BBOXMINX { + unsigned F : 24; +} REG_VGV2_BBOXMINX; + +// VGV2_BBOXMINY +typedef struct _REG_VGV2_BBOXMINY { + unsigned F : 24; +} REG_VGV2_BBOXMINY; + +// VGV2_BIAS +typedef struct _REG_VGV2_BIAS { + unsigned F : 24; +} REG_VGV2_BIAS; + +// VGV2_C1X +typedef struct _REG_VGV2_C1X { + unsigned F : 24; +} REG_VGV2_C1X; + +// VGV2_C1XREL +typedef struct _REG_VGV2_C1XREL { + unsigned F : 24; +} REG_VGV2_C1XREL; + +// VGV2_C1Y +typedef struct _REG_VGV2_C1Y { + unsigned F : 24; +} REG_VGV2_C1Y; + +// VGV2_C1YREL +typedef struct _REG_VGV2_C1YREL { + unsigned F : 24; +} REG_VGV2_C1YREL; + +// VGV2_C2X +typedef struct _REG_VGV2_C2X { + unsigned F : 24; +} REG_VGV2_C2X; + +// VGV2_C2XREL +typedef struct _REG_VGV2_C2XREL { + unsigned F : 24; +} REG_VGV2_C2XREL; + +// VGV2_C2Y +typedef struct _REG_VGV2_C2Y { + unsigned F : 24; +} REG_VGV2_C2Y; + +// VGV2_C2YREL +typedef struct _REG_VGV2_C2YREL { + unsigned F : 24; +} REG_VGV2_C2YREL; + +// VGV2_C3X +typedef struct _REG_VGV2_C3X { + unsigned F : 24; +} REG_VGV2_C3X; + +// VGV2_C3XREL +typedef struct _REG_VGV2_C3XREL { + unsigned F : 24; +} REG_VGV2_C3XREL; + +// VGV2_C3Y +typedef struct _REG_VGV2_C3Y { + unsigned F : 24; +} REG_VGV2_C3Y; + +// VGV2_C3YREL +typedef struct _REG_VGV2_C3YREL { + unsigned F : 24; +} REG_VGV2_C3YREL; + +// VGV2_C4X +typedef struct _REG_VGV2_C4X { + unsigned F : 24; +} REG_VGV2_C4X; + +// VGV2_C4XREL +typedef struct _REG_VGV2_C4XREL { + unsigned F : 24; +} REG_VGV2_C4XREL; + +// VGV2_C4Y +typedef struct _REG_VGV2_C4Y { + unsigned F : 24; +} REG_VGV2_C4Y; + +// VGV2_C4YREL +typedef struct _REG_VGV2_C4YREL { + unsigned F : 24; +} REG_VGV2_C4YREL; + +// VGV2_CLIP +typedef struct _REG_VGV2_CLIP { + unsigned F : 24; +} REG_VGV2_CLIP; + +// VGV2_FIRST +typedef struct _REG_VGV2_FIRST { + unsigned DUMMY : 1; +} REG_VGV2_FIRST; + +// VGV2_LAST +typedef struct _REG_VGV2_LAST { + unsigned DUMMY : 1; +} REG_VGV2_LAST; + +// VGV2_MITER +typedef struct _REG_VGV2_MITER { + unsigned F : 24; +} REG_VGV2_MITER; + +// VGV2_MODE +typedef struct _REG_VGV2_MODE { + unsigned MAXSPLIT : 4; + unsigned CAP : 2; + unsigned JOIN : 2; + unsigned STROKE : 1; + unsigned STROKESPLIT : 1; + unsigned FULLSPLIT : 1; + unsigned NODOTS : 1; + unsigned OPENFILL : 1; + unsigned DROPLEFT : 1; + unsigned DROPOTHER : 1; + unsigned SYMMETRICJOINS : 1; + unsigned SIMPLESTROKE : 1; + unsigned SIMPLECLIP : 1; + int EXPONENTADD : 6; +} REG_VGV2_MODE; + +// VGV2_RADIUS +typedef struct _REG_VGV2_RADIUS { + unsigned F : 24; +} REG_VGV2_RADIUS; + +// VGV2_SCALE +typedef struct _REG_VGV2_SCALE { + unsigned F : 24; +} REG_VGV2_SCALE; + +// VGV2_THINRADIUS +typedef struct _REG_VGV2_THINRADIUS { + unsigned F : 24; +} REG_VGV2_THINRADIUS; + +// VGV2_XFSTXX +typedef struct _REG_VGV2_XFSTXX { + unsigned F : 24; +} REG_VGV2_XFSTXX; + +// VGV2_XFSTXY +typedef struct _REG_VGV2_XFSTXY { + unsigned F : 24; +} REG_VGV2_XFSTXY; + +// VGV2_XFSTYX +typedef struct _REG_VGV2_XFSTYX { + unsigned F : 24; +} REG_VGV2_XFSTYX; + +// VGV2_XFSTYY +typedef struct _REG_VGV2_XFSTYY { + unsigned F : 24; +} REG_VGV2_XFSTYY; + +// VGV2_XFXA +typedef struct _REG_VGV2_XFXA { + unsigned F : 24; +} REG_VGV2_XFXA; + +// VGV2_XFXX +typedef struct _REG_VGV2_XFXX { + unsigned F : 24; +} REG_VGV2_XFXX; + +// VGV2_XFXY +typedef struct _REG_VGV2_XFXY { + unsigned F : 24; +} REG_VGV2_XFXY; + +// VGV2_XFYA +typedef struct _REG_VGV2_XFYA { + unsigned F : 24; +} REG_VGV2_XFYA; + +// VGV2_XFYX +typedef struct _REG_VGV2_XFYX { + unsigned F : 24; +} REG_VGV2_XFYX; + +// VGV2_XFYY +typedef struct _REG_VGV2_XFYY { + unsigned F : 24; +} REG_VGV2_XFYY; + +// VGV3_CONTROL +typedef struct _REG_VGV3_CONTROL { + unsigned MARKADD : 12; + unsigned DMIWAITCHMASK : 4; + unsigned PAUSE : 1; + unsigned ABORT : 1; + unsigned WRITE : 1; + unsigned BCFLUSH : 1; + unsigned V0SYNC : 1; + unsigned DMIWAITBUF : 3; +} REG_VGV3_CONTROL; + +// VGV3_FIRST +typedef struct _REG_VGV3_FIRST { + unsigned DUMMY : 1; +} REG_VGV3_FIRST; + +// VGV3_LAST +typedef struct _REG_VGV3_LAST { + unsigned DUMMY : 1; +} REG_VGV3_LAST; + +// VGV3_MODE +typedef struct _REG_VGV3_MODE { + unsigned FLIPENDIAN : 1; + unsigned UNUSED : 1; + unsigned WRITEFLUSH : 1; + unsigned DMIPAUSETYPE : 1; + unsigned DMIRESET : 1; +} REG_VGV3_MODE; + +// VGV3_NEXTADDR +typedef struct _REG_VGV3_NEXTADDR { + unsigned CALLADDR : 32; +} REG_VGV3_NEXTADDR; + +// VGV3_NEXTCMD +typedef struct _REG_VGV3_NEXTCMD { + unsigned COUNT : 12; + unsigned NEXTCMD : 3; + unsigned MARK : 1; + unsigned CALLCOUNT : 12; +} REG_VGV3_NEXTCMD; + +// VGV3_VGBYPASS +typedef struct _REG_VGV3_VGBYPASS { + unsigned BYPASS : 1; +} REG_VGV3_VGBYPASS; + +// VGV3_WRITE +typedef struct _REG_VGV3_WRITE { + unsigned VALUE : 32; +} REG_VGV3_WRITE; + +// VGV3_WRITEADDR +typedef struct _REG_VGV3_WRITEADDR { + unsigned ADDR : 32; +} REG_VGV3_WRITEADDR; + +// VGV3_WRITEDMI +typedef struct _REG_VGV3_WRITEDMI { + unsigned CHANMASK : 4; + unsigned BUFFER : 3; +} REG_VGV3_WRITEDMI; + +// VGV3_WRITEF32 +typedef struct _REG_VGV3_WRITEF32 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITEF32; + +// VGV3_WRITEIFPAUSED +typedef struct _REG_VGV3_WRITEIFPAUSED { + unsigned VALUE : 32; +} REG_VGV3_WRITEIFPAUSED; + +// VGV3_WRITERAW +typedef struct _REG_VGV3_WRITERAW { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITERAW; + +// VGV3_WRITES16 +typedef struct _REG_VGV3_WRITES16 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES16; + +// VGV3_WRITES32 +typedef struct _REG_VGV3_WRITES32 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES32; + +// VGV3_WRITES8 +typedef struct _REG_VGV3_WRITES8 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES8; + +// Register address, down shift, AND mask +#define FBC_BASE_BASE_FADDR ADDR_FBC_BASE +#define FBC_BASE_BASE_FSHIFT 0 +#define FBC_BASE_BASE_FMASK 0xffffffff +#define FBC_DATA_DATA_FADDR ADDR_FBC_DATA +#define FBC_DATA_DATA_FSHIFT 0 +#define FBC_DATA_DATA_FMASK 0xffffffff +#define FBC_HEIGHT_HEIGHT_FADDR ADDR_FBC_HEIGHT +#define FBC_HEIGHT_HEIGHT_FSHIFT 0 +#define FBC_HEIGHT_HEIGHT_FMASK 0x7ff +#define FBC_START_DUMMY_FADDR ADDR_FBC_START +#define FBC_START_DUMMY_FSHIFT 0 +#define FBC_START_DUMMY_FMASK 0x1 +#define FBC_STRIDE_STRIDE_FADDR ADDR_FBC_STRIDE +#define FBC_STRIDE_STRIDE_FSHIFT 0 +#define FBC_STRIDE_STRIDE_FMASK 0x7ff +#define FBC_WIDTH_WIDTH_FADDR ADDR_FBC_WIDTH +#define FBC_WIDTH_WIDTH_FSHIFT 0 +#define FBC_WIDTH_WIDTH_FMASK 0x7ff +#define VGC_CLOCKEN_BCACHE_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_BCACHE_FSHIFT 0 +#define VGC_CLOCKEN_BCACHE_FMASK 0x1 +#define VGC_CLOCKEN_G2D_VGL3_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_G2D_VGL3_FSHIFT 1 +#define VGC_CLOCKEN_G2D_VGL3_FMASK 0x1 +#define VGC_CLOCKEN_VG_L1L2_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_VG_L1L2_FSHIFT 2 +#define VGC_CLOCKEN_VG_L1L2_FMASK 0x1 +#define VGC_CLOCKEN_RESERVED_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_RESERVED_FSHIFT 3 +#define VGC_CLOCKEN_RESERVED_FMASK 0x7 +#define VGC_COMMANDSTREAM_DATA_FADDR ADDR_VGC_COMMANDSTREAM +#define VGC_COMMANDSTREAM_DATA_FSHIFT 0 +#define VGC_COMMANDSTREAM_DATA_FMASK 0xffffffff +#define VGC_FIFOFREE_FREE_FADDR ADDR_VGC_FIFOFREE +#define VGC_FIFOFREE_FREE_FSHIFT 0 +#define VGC_FIFOFREE_FREE_FMASK 0x1 +#define VGC_IRQENABLE_MH_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_MH_FSHIFT 0 +#define VGC_IRQENABLE_MH_FMASK 0x1 +#define VGC_IRQENABLE_G2D_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_G2D_FSHIFT 1 +#define VGC_IRQENABLE_G2D_FMASK 0x1 +#define VGC_IRQENABLE_FIFO_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_FIFO_FSHIFT 2 +#define VGC_IRQENABLE_FIFO_FMASK 0x1 +#define VGC_IRQENABLE_FBC_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_FBC_FSHIFT 3 +#define VGC_IRQENABLE_FBC_FMASK 0x1 +#define VGC_IRQSTATUS_MH_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_MH_FSHIFT 0 +#define VGC_IRQSTATUS_MH_FMASK 0x1 +#define VGC_IRQSTATUS_G2D_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_G2D_FSHIFT 1 +#define VGC_IRQSTATUS_G2D_FMASK 0x1 +#define VGC_IRQSTATUS_FIFO_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_FIFO_FSHIFT 2 +#define VGC_IRQSTATUS_FIFO_FMASK 0x1 +#define VGC_IRQSTATUS_FBC_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_FBC_FSHIFT 3 +#define VGC_IRQSTATUS_FBC_FMASK 0x1 +#define VGC_IRQ_ACTIVE_CNT_MH_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_MH_FSHIFT 0 +#define VGC_IRQ_ACTIVE_CNT_MH_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_G2D_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_G2D_FSHIFT 8 +#define VGC_IRQ_ACTIVE_CNT_G2D_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FSHIFT 16 +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_FBC_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_FBC_FSHIFT 24 +#define VGC_IRQ_ACTIVE_CNT_FBC_FMASK 0xff +#define VGC_MMUCOMMANDSTREAM_DATA_FADDR ADDR_VGC_MMUCOMMANDSTREAM +#define VGC_MMUCOMMANDSTREAM_DATA_FSHIFT 0 +#define VGC_MMUCOMMANDSTREAM_DATA_FMASK 0xffffffff +#define VGC_REVISION_MINOR_REVISION_FADDR ADDR_VGC_REVISION +#define VGC_REVISION_MINOR_REVISION_FSHIFT 0 +#define VGC_REVISION_MINOR_REVISION_FMASK 0xf +#define VGC_REVISION_MAJOR_REVISION_FADDR ADDR_VGC_REVISION +#define VGC_REVISION_MAJOR_REVISION_FSHIFT 4 +#define VGC_REVISION_MAJOR_REVISION_FMASK 0xf +#define VGC_SYSSTATUS_RESET_FADDR ADDR_VGC_SYSSTATUS +#define VGC_SYSSTATUS_RESET_FSHIFT 0 +#define VGC_SYSSTATUS_RESET_FMASK 0x1 +#define G2D_ALPHABLEND_ALPHA_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_ALPHA_FSHIFT 0 +#define G2D_ALPHABLEND_ALPHA_FMASK 0xff +#define G2D_ALPHABLEND_OBS_ENABLE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_OBS_ENABLE_FSHIFT 8 +#define G2D_ALPHABLEND_OBS_ENABLE_FMASK 0x1 +#define G2D_ALPHABLEND_CONSTANT_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_CONSTANT_FSHIFT 9 +#define G2D_ALPHABLEND_CONSTANT_FMASK 0x1 +#define G2D_ALPHABLEND_INVERT_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_INVERT_FSHIFT 10 +#define G2D_ALPHABLEND_INVERT_FMASK 0x1 +#define G2D_ALPHABLEND_OPTIMIZE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_OPTIMIZE_FSHIFT 11 +#define G2D_ALPHABLEND_OPTIMIZE_FMASK 0x1 +#define G2D_ALPHABLEND_MODULATE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_MODULATE_FSHIFT 12 +#define G2D_ALPHABLEND_MODULATE_FMASK 0x1 +#define G2D_ALPHABLEND_INVERTMASK_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_INVERTMASK_FSHIFT 13 +#define G2D_ALPHABLEND_INVERTMASK_FMASK 0x1 +#define G2D_ALPHABLEND_PREMULTIPLYDST_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_PREMULTIPLYDST_FSHIFT 14 +#define G2D_ALPHABLEND_PREMULTIPLYDST_FMASK 0x1 +#define G2D_ALPHABLEND_MASKTOALPHA_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_MASKTOALPHA_FSHIFT 15 +#define G2D_ALPHABLEND_MASKTOALPHA_FMASK 0x1 +#define G2D_BACKGROUND_COLOR_FADDR ADDR_G2D_BACKGROUND +#define G2D_BACKGROUND_COLOR_FSHIFT 0 +#define G2D_BACKGROUND_COLOR_FMASK 0xffffffff +#define G2D_BASE0_ADDR_FADDR ADDR_G2D_BASE0 +#define G2D_BASE0_ADDR_FSHIFT 0 +#define G2D_BASE0_ADDR_FMASK 0xffffffff +#define G2D_BASE1_ADDR_FADDR ADDR_G2D_BASE1 +#define G2D_BASE1_ADDR_FSHIFT 0 +#define G2D_BASE1_ADDR_FMASK 0xffffffff +#define G2D_BASE2_ADDR_FADDR ADDR_G2D_BASE2 +#define G2D_BASE2_ADDR_FSHIFT 0 +#define G2D_BASE2_ADDR_FMASK 0xffffffff +#define G2D_BASE3_ADDR_FADDR ADDR_G2D_BASE3 +#define G2D_BASE3_ADDR_FSHIFT 0 +#define G2D_BASE3_ADDR_FMASK 0xffffffff +#define G2D_BLENDERCFG_PASSES_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_PASSES_FSHIFT 0 +#define G2D_BLENDERCFG_PASSES_FMASK 0x7 +#define G2D_BLENDERCFG_ALPHAPASSES_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_ALPHAPASSES_FSHIFT 3 +#define G2D_BLENDERCFG_ALPHAPASSES_FMASK 0x3 +#define G2D_BLENDERCFG_ENABLE_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_ENABLE_FSHIFT 5 +#define G2D_BLENDERCFG_ENABLE_FMASK 0x1 +#define G2D_BLENDERCFG_OOALPHA_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_OOALPHA_FSHIFT 6 +#define G2D_BLENDERCFG_OOALPHA_FMASK 0x1 +#define G2D_BLENDERCFG_OBS_DIVALPHA_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_OBS_DIVALPHA_FSHIFT 7 +#define G2D_BLENDERCFG_OBS_DIVALPHA_FMASK 0x1 +#define G2D_BLENDERCFG_NOMASK_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_NOMASK_FSHIFT 8 +#define G2D_BLENDERCFG_NOMASK_FMASK 0x1 +#define G2D_BLEND_A0_OPERATION_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_OPERATION_FSHIFT 0 +#define G2D_BLEND_A0_OPERATION_FMASK 0x3 +#define G2D_BLEND_A0_DST_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_A_FSHIFT 2 +#define G2D_BLEND_A0_DST_A_FMASK 0x3 +#define G2D_BLEND_A0_DST_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_B_FSHIFT 4 +#define G2D_BLEND_A0_DST_B_FMASK 0x3 +#define G2D_BLEND_A0_DST_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_C_FSHIFT 6 +#define G2D_BLEND_A0_DST_C_FMASK 0x3 +#define G2D_BLEND_A0_AR_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_A_FSHIFT 8 +#define G2D_BLEND_A0_AR_A_FMASK 0x1 +#define G2D_BLEND_A0_AR_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_B_FSHIFT 9 +#define G2D_BLEND_A0_AR_B_FMASK 0x1 +#define G2D_BLEND_A0_AR_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_C_FSHIFT 10 +#define G2D_BLEND_A0_AR_C_FMASK 0x1 +#define G2D_BLEND_A0_AR_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_D_FSHIFT 11 +#define G2D_BLEND_A0_AR_D_FMASK 0x1 +#define G2D_BLEND_A0_INV_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_A_FSHIFT 12 +#define G2D_BLEND_A0_INV_A_FMASK 0x1 +#define G2D_BLEND_A0_INV_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_B_FSHIFT 13 +#define G2D_BLEND_A0_INV_B_FMASK 0x1 +#define G2D_BLEND_A0_INV_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_C_FSHIFT 14 +#define G2D_BLEND_A0_INV_C_FMASK 0x1 +#define G2D_BLEND_A0_INV_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_D_FSHIFT 15 +#define G2D_BLEND_A0_INV_D_FMASK 0x1 +#define G2D_BLEND_A0_SRC_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_A_FSHIFT 16 +#define G2D_BLEND_A0_SRC_A_FMASK 0x7 +#define G2D_BLEND_A0_SRC_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_B_FSHIFT 19 +#define G2D_BLEND_A0_SRC_B_FMASK 0x7 +#define G2D_BLEND_A0_SRC_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_C_FSHIFT 22 +#define G2D_BLEND_A0_SRC_C_FMASK 0x7 +#define G2D_BLEND_A0_SRC_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_D_FSHIFT 25 +#define G2D_BLEND_A0_SRC_D_FMASK 0x7 +#define G2D_BLEND_A0_CONST_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_A_FSHIFT 28 +#define G2D_BLEND_A0_CONST_A_FMASK 0x1 +#define G2D_BLEND_A0_CONST_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_B_FSHIFT 29 +#define G2D_BLEND_A0_CONST_B_FMASK 0x1 +#define G2D_BLEND_A0_CONST_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_C_FSHIFT 30 +#define G2D_BLEND_A0_CONST_C_FMASK 0x1 +#define G2D_BLEND_A0_CONST_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_D_FSHIFT 31 +#define G2D_BLEND_A0_CONST_D_FMASK 0x1 +#define G2D_BLEND_A1_OPERATION_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_OPERATION_FSHIFT 0 +#define G2D_BLEND_A1_OPERATION_FMASK 0x3 +#define G2D_BLEND_A1_DST_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_A_FSHIFT 2 +#define G2D_BLEND_A1_DST_A_FMASK 0x3 +#define G2D_BLEND_A1_DST_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_B_FSHIFT 4 +#define G2D_BLEND_A1_DST_B_FMASK 0x3 +#define G2D_BLEND_A1_DST_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_C_FSHIFT 6 +#define G2D_BLEND_A1_DST_C_FMASK 0x3 +#define G2D_BLEND_A1_AR_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_A_FSHIFT 8 +#define G2D_BLEND_A1_AR_A_FMASK 0x1 +#define G2D_BLEND_A1_AR_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_B_FSHIFT 9 +#define G2D_BLEND_A1_AR_B_FMASK 0x1 +#define G2D_BLEND_A1_AR_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_C_FSHIFT 10 +#define G2D_BLEND_A1_AR_C_FMASK 0x1 +#define G2D_BLEND_A1_AR_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_D_FSHIFT 11 +#define G2D_BLEND_A1_AR_D_FMASK 0x1 +#define G2D_BLEND_A1_INV_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_A_FSHIFT 12 +#define G2D_BLEND_A1_INV_A_FMASK 0x1 +#define G2D_BLEND_A1_INV_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_B_FSHIFT 13 +#define G2D_BLEND_A1_INV_B_FMASK 0x1 +#define G2D_BLEND_A1_INV_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_C_FSHIFT 14 +#define G2D_BLEND_A1_INV_C_FMASK 0x1 +#define G2D_BLEND_A1_INV_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_D_FSHIFT 15 +#define G2D_BLEND_A1_INV_D_FMASK 0x1 +#define G2D_BLEND_A1_SRC_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_A_FSHIFT 16 +#define G2D_BLEND_A1_SRC_A_FMASK 0x7 +#define G2D_BLEND_A1_SRC_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_B_FSHIFT 19 +#define G2D_BLEND_A1_SRC_B_FMASK 0x7 +#define G2D_BLEND_A1_SRC_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_C_FSHIFT 22 +#define G2D_BLEND_A1_SRC_C_FMASK 0x7 +#define G2D_BLEND_A1_SRC_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_D_FSHIFT 25 +#define G2D_BLEND_A1_SRC_D_FMASK 0x7 +#define G2D_BLEND_A1_CONST_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_A_FSHIFT 28 +#define G2D_BLEND_A1_CONST_A_FMASK 0x1 +#define G2D_BLEND_A1_CONST_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_B_FSHIFT 29 +#define G2D_BLEND_A1_CONST_B_FMASK 0x1 +#define G2D_BLEND_A1_CONST_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_C_FSHIFT 30 +#define G2D_BLEND_A1_CONST_C_FMASK 0x1 +#define G2D_BLEND_A1_CONST_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_D_FSHIFT 31 +#define G2D_BLEND_A1_CONST_D_FMASK 0x1 +#define G2D_BLEND_A2_OPERATION_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_OPERATION_FSHIFT 0 +#define G2D_BLEND_A2_OPERATION_FMASK 0x3 +#define G2D_BLEND_A2_DST_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_A_FSHIFT 2 +#define G2D_BLEND_A2_DST_A_FMASK 0x3 +#define G2D_BLEND_A2_DST_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_B_FSHIFT 4 +#define G2D_BLEND_A2_DST_B_FMASK 0x3 +#define G2D_BLEND_A2_DST_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_C_FSHIFT 6 +#define G2D_BLEND_A2_DST_C_FMASK 0x3 +#define G2D_BLEND_A2_AR_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_A_FSHIFT 8 +#define G2D_BLEND_A2_AR_A_FMASK 0x1 +#define G2D_BLEND_A2_AR_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_B_FSHIFT 9 +#define G2D_BLEND_A2_AR_B_FMASK 0x1 +#define G2D_BLEND_A2_AR_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_C_FSHIFT 10 +#define G2D_BLEND_A2_AR_C_FMASK 0x1 +#define G2D_BLEND_A2_AR_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_D_FSHIFT 11 +#define G2D_BLEND_A2_AR_D_FMASK 0x1 +#define G2D_BLEND_A2_INV_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_A_FSHIFT 12 +#define G2D_BLEND_A2_INV_A_FMASK 0x1 +#define G2D_BLEND_A2_INV_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_B_FSHIFT 13 +#define G2D_BLEND_A2_INV_B_FMASK 0x1 +#define G2D_BLEND_A2_INV_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_C_FSHIFT 14 +#define G2D_BLEND_A2_INV_C_FMASK 0x1 +#define G2D_BLEND_A2_INV_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_D_FSHIFT 15 +#define G2D_BLEND_A2_INV_D_FMASK 0x1 +#define G2D_BLEND_A2_SRC_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_A_FSHIFT 16 +#define G2D_BLEND_A2_SRC_A_FMASK 0x7 +#define G2D_BLEND_A2_SRC_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_B_FSHIFT 19 +#define G2D_BLEND_A2_SRC_B_FMASK 0x7 +#define G2D_BLEND_A2_SRC_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_C_FSHIFT 22 +#define G2D_BLEND_A2_SRC_C_FMASK 0x7 +#define G2D_BLEND_A2_SRC_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_D_FSHIFT 25 +#define G2D_BLEND_A2_SRC_D_FMASK 0x7 +#define G2D_BLEND_A2_CONST_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_A_FSHIFT 28 +#define G2D_BLEND_A2_CONST_A_FMASK 0x1 +#define G2D_BLEND_A2_CONST_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_B_FSHIFT 29 +#define G2D_BLEND_A2_CONST_B_FMASK 0x1 +#define G2D_BLEND_A2_CONST_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_C_FSHIFT 30 +#define G2D_BLEND_A2_CONST_C_FMASK 0x1 +#define G2D_BLEND_A2_CONST_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_D_FSHIFT 31 +#define G2D_BLEND_A2_CONST_D_FMASK 0x1 +#define G2D_BLEND_A3_OPERATION_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_OPERATION_FSHIFT 0 +#define G2D_BLEND_A3_OPERATION_FMASK 0x3 +#define G2D_BLEND_A3_DST_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_A_FSHIFT 2 +#define G2D_BLEND_A3_DST_A_FMASK 0x3 +#define G2D_BLEND_A3_DST_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_B_FSHIFT 4 +#define G2D_BLEND_A3_DST_B_FMASK 0x3 +#define G2D_BLEND_A3_DST_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_C_FSHIFT 6 +#define G2D_BLEND_A3_DST_C_FMASK 0x3 +#define G2D_BLEND_A3_AR_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_A_FSHIFT 8 +#define G2D_BLEND_A3_AR_A_FMASK 0x1 +#define G2D_BLEND_A3_AR_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_B_FSHIFT 9 +#define G2D_BLEND_A3_AR_B_FMASK 0x1 +#define G2D_BLEND_A3_AR_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_C_FSHIFT 10 +#define G2D_BLEND_A3_AR_C_FMASK 0x1 +#define G2D_BLEND_A3_AR_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_D_FSHIFT 11 +#define G2D_BLEND_A3_AR_D_FMASK 0x1 +#define G2D_BLEND_A3_INV_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_A_FSHIFT 12 +#define G2D_BLEND_A3_INV_A_FMASK 0x1 +#define G2D_BLEND_A3_INV_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_B_FSHIFT 13 +#define G2D_BLEND_A3_INV_B_FMASK 0x1 +#define G2D_BLEND_A3_INV_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_C_FSHIFT 14 +#define G2D_BLEND_A3_INV_C_FMASK 0x1 +#define G2D_BLEND_A3_INV_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_D_FSHIFT 15 +#define G2D_BLEND_A3_INV_D_FMASK 0x1 +#define G2D_BLEND_A3_SRC_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_A_FSHIFT 16 +#define G2D_BLEND_A3_SRC_A_FMASK 0x7 +#define G2D_BLEND_A3_SRC_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_B_FSHIFT 19 +#define G2D_BLEND_A3_SRC_B_FMASK 0x7 +#define G2D_BLEND_A3_SRC_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_C_FSHIFT 22 +#define G2D_BLEND_A3_SRC_C_FMASK 0x7 +#define G2D_BLEND_A3_SRC_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_D_FSHIFT 25 +#define G2D_BLEND_A3_SRC_D_FMASK 0x7 +#define G2D_BLEND_A3_CONST_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_A_FSHIFT 28 +#define G2D_BLEND_A3_CONST_A_FMASK 0x1 +#define G2D_BLEND_A3_CONST_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_B_FSHIFT 29 +#define G2D_BLEND_A3_CONST_B_FMASK 0x1 +#define G2D_BLEND_A3_CONST_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_C_FSHIFT 30 +#define G2D_BLEND_A3_CONST_C_FMASK 0x1 +#define G2D_BLEND_A3_CONST_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_D_FSHIFT 31 +#define G2D_BLEND_A3_CONST_D_FMASK 0x1 +#define G2D_BLEND_C0_OPERATION_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_OPERATION_FSHIFT 0 +#define G2D_BLEND_C0_OPERATION_FMASK 0x3 +#define G2D_BLEND_C0_DST_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_A_FSHIFT 2 +#define G2D_BLEND_C0_DST_A_FMASK 0x3 +#define G2D_BLEND_C0_DST_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_B_FSHIFT 4 +#define G2D_BLEND_C0_DST_B_FMASK 0x3 +#define G2D_BLEND_C0_DST_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_C_FSHIFT 6 +#define G2D_BLEND_C0_DST_C_FMASK 0x3 +#define G2D_BLEND_C0_AR_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_A_FSHIFT 8 +#define G2D_BLEND_C0_AR_A_FMASK 0x1 +#define G2D_BLEND_C0_AR_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_B_FSHIFT 9 +#define G2D_BLEND_C0_AR_B_FMASK 0x1 +#define G2D_BLEND_C0_AR_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_C_FSHIFT 10 +#define G2D_BLEND_C0_AR_C_FMASK 0x1 +#define G2D_BLEND_C0_AR_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_D_FSHIFT 11 +#define G2D_BLEND_C0_AR_D_FMASK 0x1 +#define G2D_BLEND_C0_INV_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_A_FSHIFT 12 +#define G2D_BLEND_C0_INV_A_FMASK 0x1 +#define G2D_BLEND_C0_INV_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_B_FSHIFT 13 +#define G2D_BLEND_C0_INV_B_FMASK 0x1 +#define G2D_BLEND_C0_INV_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_C_FSHIFT 14 +#define G2D_BLEND_C0_INV_C_FMASK 0x1 +#define G2D_BLEND_C0_INV_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_D_FSHIFT 15 +#define G2D_BLEND_C0_INV_D_FMASK 0x1 +#define G2D_BLEND_C0_SRC_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_A_FSHIFT 16 +#define G2D_BLEND_C0_SRC_A_FMASK 0x7 +#define G2D_BLEND_C0_SRC_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_B_FSHIFT 19 +#define G2D_BLEND_C0_SRC_B_FMASK 0x7 +#define G2D_BLEND_C0_SRC_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_C_FSHIFT 22 +#define G2D_BLEND_C0_SRC_C_FMASK 0x7 +#define G2D_BLEND_C0_SRC_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_D_FSHIFT 25 +#define G2D_BLEND_C0_SRC_D_FMASK 0x7 +#define G2D_BLEND_C0_CONST_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_A_FSHIFT 28 +#define G2D_BLEND_C0_CONST_A_FMASK 0x1 +#define G2D_BLEND_C0_CONST_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_B_FSHIFT 29 +#define G2D_BLEND_C0_CONST_B_FMASK 0x1 +#define G2D_BLEND_C0_CONST_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_C_FSHIFT 30 +#define G2D_BLEND_C0_CONST_C_FMASK 0x1 +#define G2D_BLEND_C0_CONST_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_D_FSHIFT 31 +#define G2D_BLEND_C0_CONST_D_FMASK 0x1 +#define G2D_BLEND_C1_OPERATION_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_OPERATION_FSHIFT 0 +#define G2D_BLEND_C1_OPERATION_FMASK 0x3 +#define G2D_BLEND_C1_DST_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_A_FSHIFT 2 +#define G2D_BLEND_C1_DST_A_FMASK 0x3 +#define G2D_BLEND_C1_DST_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_B_FSHIFT 4 +#define G2D_BLEND_C1_DST_B_FMASK 0x3 +#define G2D_BLEND_C1_DST_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_C_FSHIFT 6 +#define G2D_BLEND_C1_DST_C_FMASK 0x3 +#define G2D_BLEND_C1_AR_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_A_FSHIFT 8 +#define G2D_BLEND_C1_AR_A_FMASK 0x1 +#define G2D_BLEND_C1_AR_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_B_FSHIFT 9 +#define G2D_BLEND_C1_AR_B_FMASK 0x1 +#define G2D_BLEND_C1_AR_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_C_FSHIFT 10 +#define G2D_BLEND_C1_AR_C_FMASK 0x1 +#define G2D_BLEND_C1_AR_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_D_FSHIFT 11 +#define G2D_BLEND_C1_AR_D_FMASK 0x1 +#define G2D_BLEND_C1_INV_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_A_FSHIFT 12 +#define G2D_BLEND_C1_INV_A_FMASK 0x1 +#define G2D_BLEND_C1_INV_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_B_FSHIFT 13 +#define G2D_BLEND_C1_INV_B_FMASK 0x1 +#define G2D_BLEND_C1_INV_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_C_FSHIFT 14 +#define G2D_BLEND_C1_INV_C_FMASK 0x1 +#define G2D_BLEND_C1_INV_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_D_FSHIFT 15 +#define G2D_BLEND_C1_INV_D_FMASK 0x1 +#define G2D_BLEND_C1_SRC_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_A_FSHIFT 16 +#define G2D_BLEND_C1_SRC_A_FMASK 0x7 +#define G2D_BLEND_C1_SRC_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_B_FSHIFT 19 +#define G2D_BLEND_C1_SRC_B_FMASK 0x7 +#define G2D_BLEND_C1_SRC_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_C_FSHIFT 22 +#define G2D_BLEND_C1_SRC_C_FMASK 0x7 +#define G2D_BLEND_C1_SRC_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_D_FSHIFT 25 +#define G2D_BLEND_C1_SRC_D_FMASK 0x7 +#define G2D_BLEND_C1_CONST_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_A_FSHIFT 28 +#define G2D_BLEND_C1_CONST_A_FMASK 0x1 +#define G2D_BLEND_C1_CONST_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_B_FSHIFT 29 +#define G2D_BLEND_C1_CONST_B_FMASK 0x1 +#define G2D_BLEND_C1_CONST_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_C_FSHIFT 30 +#define G2D_BLEND_C1_CONST_C_FMASK 0x1 +#define G2D_BLEND_C1_CONST_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_D_FSHIFT 31 +#define G2D_BLEND_C1_CONST_D_FMASK 0x1 +#define G2D_BLEND_C2_OPERATION_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_OPERATION_FSHIFT 0 +#define G2D_BLEND_C2_OPERATION_FMASK 0x3 +#define G2D_BLEND_C2_DST_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_A_FSHIFT 2 +#define G2D_BLEND_C2_DST_A_FMASK 0x3 +#define G2D_BLEND_C2_DST_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_B_FSHIFT 4 +#define G2D_BLEND_C2_DST_B_FMASK 0x3 +#define G2D_BLEND_C2_DST_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_C_FSHIFT 6 +#define G2D_BLEND_C2_DST_C_FMASK 0x3 +#define G2D_BLEND_C2_AR_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_A_FSHIFT 8 +#define G2D_BLEND_C2_AR_A_FMASK 0x1 +#define G2D_BLEND_C2_AR_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_B_FSHIFT 9 +#define G2D_BLEND_C2_AR_B_FMASK 0x1 +#define G2D_BLEND_C2_AR_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_C_FSHIFT 10 +#define G2D_BLEND_C2_AR_C_FMASK 0x1 +#define G2D_BLEND_C2_AR_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_D_FSHIFT 11 +#define G2D_BLEND_C2_AR_D_FMASK 0x1 +#define G2D_BLEND_C2_INV_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_A_FSHIFT 12 +#define G2D_BLEND_C2_INV_A_FMASK 0x1 +#define G2D_BLEND_C2_INV_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_B_FSHIFT 13 +#define G2D_BLEND_C2_INV_B_FMASK 0x1 +#define G2D_BLEND_C2_INV_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_C_FSHIFT 14 +#define G2D_BLEND_C2_INV_C_FMASK 0x1 +#define G2D_BLEND_C2_INV_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_D_FSHIFT 15 +#define G2D_BLEND_C2_INV_D_FMASK 0x1 +#define G2D_BLEND_C2_SRC_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_A_FSHIFT 16 +#define G2D_BLEND_C2_SRC_A_FMASK 0x7 +#define G2D_BLEND_C2_SRC_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_B_FSHIFT 19 +#define G2D_BLEND_C2_SRC_B_FMASK 0x7 +#define G2D_BLEND_C2_SRC_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_C_FSHIFT 22 +#define G2D_BLEND_C2_SRC_C_FMASK 0x7 +#define G2D_BLEND_C2_SRC_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_D_FSHIFT 25 +#define G2D_BLEND_C2_SRC_D_FMASK 0x7 +#define G2D_BLEND_C2_CONST_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_A_FSHIFT 28 +#define G2D_BLEND_C2_CONST_A_FMASK 0x1 +#define G2D_BLEND_C2_CONST_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_B_FSHIFT 29 +#define G2D_BLEND_C2_CONST_B_FMASK 0x1 +#define G2D_BLEND_C2_CONST_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_C_FSHIFT 30 +#define G2D_BLEND_C2_CONST_C_FMASK 0x1 +#define G2D_BLEND_C2_CONST_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_D_FSHIFT 31 +#define G2D_BLEND_C2_CONST_D_FMASK 0x1 +#define G2D_BLEND_C3_OPERATION_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_OPERATION_FSHIFT 0 +#define G2D_BLEND_C3_OPERATION_FMASK 0x3 +#define G2D_BLEND_C3_DST_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_A_FSHIFT 2 +#define G2D_BLEND_C3_DST_A_FMASK 0x3 +#define G2D_BLEND_C3_DST_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_B_FSHIFT 4 +#define G2D_BLEND_C3_DST_B_FMASK 0x3 +#define G2D_BLEND_C3_DST_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_C_FSHIFT 6 +#define G2D_BLEND_C3_DST_C_FMASK 0x3 +#define G2D_BLEND_C3_AR_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_A_FSHIFT 8 +#define G2D_BLEND_C3_AR_A_FMASK 0x1 +#define G2D_BLEND_C3_AR_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_B_FSHIFT 9 +#define G2D_BLEND_C3_AR_B_FMASK 0x1 +#define G2D_BLEND_C3_AR_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_C_FSHIFT 10 +#define G2D_BLEND_C3_AR_C_FMASK 0x1 +#define G2D_BLEND_C3_AR_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_D_FSHIFT 11 +#define G2D_BLEND_C3_AR_D_FMASK 0x1 +#define G2D_BLEND_C3_INV_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_A_FSHIFT 12 +#define G2D_BLEND_C3_INV_A_FMASK 0x1 +#define G2D_BLEND_C3_INV_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_B_FSHIFT 13 +#define G2D_BLEND_C3_INV_B_FMASK 0x1 +#define G2D_BLEND_C3_INV_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_C_FSHIFT 14 +#define G2D_BLEND_C3_INV_C_FMASK 0x1 +#define G2D_BLEND_C3_INV_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_D_FSHIFT 15 +#define G2D_BLEND_C3_INV_D_FMASK 0x1 +#define G2D_BLEND_C3_SRC_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_A_FSHIFT 16 +#define G2D_BLEND_C3_SRC_A_FMASK 0x7 +#define G2D_BLEND_C3_SRC_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_B_FSHIFT 19 +#define G2D_BLEND_C3_SRC_B_FMASK 0x7 +#define G2D_BLEND_C3_SRC_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_C_FSHIFT 22 +#define G2D_BLEND_C3_SRC_C_FMASK 0x7 +#define G2D_BLEND_C3_SRC_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_D_FSHIFT 25 +#define G2D_BLEND_C3_SRC_D_FMASK 0x7 +#define G2D_BLEND_C3_CONST_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_A_FSHIFT 28 +#define G2D_BLEND_C3_CONST_A_FMASK 0x1 +#define G2D_BLEND_C3_CONST_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_B_FSHIFT 29 +#define G2D_BLEND_C3_CONST_B_FMASK 0x1 +#define G2D_BLEND_C3_CONST_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_C_FSHIFT 30 +#define G2D_BLEND_C3_CONST_C_FMASK 0x1 +#define G2D_BLEND_C3_CONST_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_D_FSHIFT 31 +#define G2D_BLEND_C3_CONST_D_FMASK 0x1 +#define G2D_BLEND_C4_OPERATION_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_OPERATION_FSHIFT 0 +#define G2D_BLEND_C4_OPERATION_FMASK 0x3 +#define G2D_BLEND_C4_DST_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_A_FSHIFT 2 +#define G2D_BLEND_C4_DST_A_FMASK 0x3 +#define G2D_BLEND_C4_DST_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_B_FSHIFT 4 +#define G2D_BLEND_C4_DST_B_FMASK 0x3 +#define G2D_BLEND_C4_DST_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_C_FSHIFT 6 +#define G2D_BLEND_C4_DST_C_FMASK 0x3 +#define G2D_BLEND_C4_AR_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_A_FSHIFT 8 +#define G2D_BLEND_C4_AR_A_FMASK 0x1 +#define G2D_BLEND_C4_AR_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_B_FSHIFT 9 +#define G2D_BLEND_C4_AR_B_FMASK 0x1 +#define G2D_BLEND_C4_AR_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_C_FSHIFT 10 +#define G2D_BLEND_C4_AR_C_FMASK 0x1 +#define G2D_BLEND_C4_AR_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_D_FSHIFT 11 +#define G2D_BLEND_C4_AR_D_FMASK 0x1 +#define G2D_BLEND_C4_INV_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_A_FSHIFT 12 +#define G2D_BLEND_C4_INV_A_FMASK 0x1 +#define G2D_BLEND_C4_INV_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_B_FSHIFT 13 +#define G2D_BLEND_C4_INV_B_FMASK 0x1 +#define G2D_BLEND_C4_INV_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_C_FSHIFT 14 +#define G2D_BLEND_C4_INV_C_FMASK 0x1 +#define G2D_BLEND_C4_INV_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_D_FSHIFT 15 +#define G2D_BLEND_C4_INV_D_FMASK 0x1 +#define G2D_BLEND_C4_SRC_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_A_FSHIFT 16 +#define G2D_BLEND_C4_SRC_A_FMASK 0x7 +#define G2D_BLEND_C4_SRC_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_B_FSHIFT 19 +#define G2D_BLEND_C4_SRC_B_FMASK 0x7 +#define G2D_BLEND_C4_SRC_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_C_FSHIFT 22 +#define G2D_BLEND_C4_SRC_C_FMASK 0x7 +#define G2D_BLEND_C4_SRC_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_D_FSHIFT 25 +#define G2D_BLEND_C4_SRC_D_FMASK 0x7 +#define G2D_BLEND_C4_CONST_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_A_FSHIFT 28 +#define G2D_BLEND_C4_CONST_A_FMASK 0x1 +#define G2D_BLEND_C4_CONST_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_B_FSHIFT 29 +#define G2D_BLEND_C4_CONST_B_FMASK 0x1 +#define G2D_BLEND_C4_CONST_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_C_FSHIFT 30 +#define G2D_BLEND_C4_CONST_C_FMASK 0x1 +#define G2D_BLEND_C4_CONST_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_D_FSHIFT 31 +#define G2D_BLEND_C4_CONST_D_FMASK 0x1 +#define G2D_BLEND_C5_OPERATION_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_OPERATION_FSHIFT 0 +#define G2D_BLEND_C5_OPERATION_FMASK 0x3 +#define G2D_BLEND_C5_DST_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_A_FSHIFT 2 +#define G2D_BLEND_C5_DST_A_FMASK 0x3 +#define G2D_BLEND_C5_DST_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_B_FSHIFT 4 +#define G2D_BLEND_C5_DST_B_FMASK 0x3 +#define G2D_BLEND_C5_DST_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_C_FSHIFT 6 +#define G2D_BLEND_C5_DST_C_FMASK 0x3 +#define G2D_BLEND_C5_AR_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_A_FSHIFT 8 +#define G2D_BLEND_C5_AR_A_FMASK 0x1 +#define G2D_BLEND_C5_AR_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_B_FSHIFT 9 +#define G2D_BLEND_C5_AR_B_FMASK 0x1 +#define G2D_BLEND_C5_AR_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_C_FSHIFT 10 +#define G2D_BLEND_C5_AR_C_FMASK 0x1 +#define G2D_BLEND_C5_AR_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_D_FSHIFT 11 +#define G2D_BLEND_C5_AR_D_FMASK 0x1 +#define G2D_BLEND_C5_INV_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_A_FSHIFT 12 +#define G2D_BLEND_C5_INV_A_FMASK 0x1 +#define G2D_BLEND_C5_INV_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_B_FSHIFT 13 +#define G2D_BLEND_C5_INV_B_FMASK 0x1 +#define G2D_BLEND_C5_INV_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_C_FSHIFT 14 +#define G2D_BLEND_C5_INV_C_FMASK 0x1 +#define G2D_BLEND_C5_INV_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_D_FSHIFT 15 +#define G2D_BLEND_C5_INV_D_FMASK 0x1 +#define G2D_BLEND_C5_SRC_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_A_FSHIFT 16 +#define G2D_BLEND_C5_SRC_A_FMASK 0x7 +#define G2D_BLEND_C5_SRC_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_B_FSHIFT 19 +#define G2D_BLEND_C5_SRC_B_FMASK 0x7 +#define G2D_BLEND_C5_SRC_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_C_FSHIFT 22 +#define G2D_BLEND_C5_SRC_C_FMASK 0x7 +#define G2D_BLEND_C5_SRC_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_D_FSHIFT 25 +#define G2D_BLEND_C5_SRC_D_FMASK 0x7 +#define G2D_BLEND_C5_CONST_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_A_FSHIFT 28 +#define G2D_BLEND_C5_CONST_A_FMASK 0x1 +#define G2D_BLEND_C5_CONST_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_B_FSHIFT 29 +#define G2D_BLEND_C5_CONST_B_FMASK 0x1 +#define G2D_BLEND_C5_CONST_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_C_FSHIFT 30 +#define G2D_BLEND_C5_CONST_C_FMASK 0x1 +#define G2D_BLEND_C5_CONST_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_D_FSHIFT 31 +#define G2D_BLEND_C5_CONST_D_FMASK 0x1 +#define G2D_BLEND_C6_OPERATION_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_OPERATION_FSHIFT 0 +#define G2D_BLEND_C6_OPERATION_FMASK 0x3 +#define G2D_BLEND_C6_DST_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_A_FSHIFT 2 +#define G2D_BLEND_C6_DST_A_FMASK 0x3 +#define G2D_BLEND_C6_DST_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_B_FSHIFT 4 +#define G2D_BLEND_C6_DST_B_FMASK 0x3 +#define G2D_BLEND_C6_DST_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_C_FSHIFT 6 +#define G2D_BLEND_C6_DST_C_FMASK 0x3 +#define G2D_BLEND_C6_AR_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_A_FSHIFT 8 +#define G2D_BLEND_C6_AR_A_FMASK 0x1 +#define G2D_BLEND_C6_AR_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_B_FSHIFT 9 +#define G2D_BLEND_C6_AR_B_FMASK 0x1 +#define G2D_BLEND_C6_AR_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_C_FSHIFT 10 +#define G2D_BLEND_C6_AR_C_FMASK 0x1 +#define G2D_BLEND_C6_AR_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_D_FSHIFT 11 +#define G2D_BLEND_C6_AR_D_FMASK 0x1 +#define G2D_BLEND_C6_INV_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_A_FSHIFT 12 +#define G2D_BLEND_C6_INV_A_FMASK 0x1 +#define G2D_BLEND_C6_INV_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_B_FSHIFT 13 +#define G2D_BLEND_C6_INV_B_FMASK 0x1 +#define G2D_BLEND_C6_INV_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_C_FSHIFT 14 +#define G2D_BLEND_C6_INV_C_FMASK 0x1 +#define G2D_BLEND_C6_INV_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_D_FSHIFT 15 +#define G2D_BLEND_C6_INV_D_FMASK 0x1 +#define G2D_BLEND_C6_SRC_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_A_FSHIFT 16 +#define G2D_BLEND_C6_SRC_A_FMASK 0x7 +#define G2D_BLEND_C6_SRC_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_B_FSHIFT 19 +#define G2D_BLEND_C6_SRC_B_FMASK 0x7 +#define G2D_BLEND_C6_SRC_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_C_FSHIFT 22 +#define G2D_BLEND_C6_SRC_C_FMASK 0x7 +#define G2D_BLEND_C6_SRC_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_D_FSHIFT 25 +#define G2D_BLEND_C6_SRC_D_FMASK 0x7 +#define G2D_BLEND_C6_CONST_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_A_FSHIFT 28 +#define G2D_BLEND_C6_CONST_A_FMASK 0x1 +#define G2D_BLEND_C6_CONST_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_B_FSHIFT 29 +#define G2D_BLEND_C6_CONST_B_FMASK 0x1 +#define G2D_BLEND_C6_CONST_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_C_FSHIFT 30 +#define G2D_BLEND_C6_CONST_C_FMASK 0x1 +#define G2D_BLEND_C6_CONST_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_D_FSHIFT 31 +#define G2D_BLEND_C6_CONST_D_FMASK 0x1 +#define G2D_BLEND_C7_OPERATION_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_OPERATION_FSHIFT 0 +#define G2D_BLEND_C7_OPERATION_FMASK 0x3 +#define G2D_BLEND_C7_DST_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_A_FSHIFT 2 +#define G2D_BLEND_C7_DST_A_FMASK 0x3 +#define G2D_BLEND_C7_DST_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_B_FSHIFT 4 +#define G2D_BLEND_C7_DST_B_FMASK 0x3 +#define G2D_BLEND_C7_DST_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_C_FSHIFT 6 +#define G2D_BLEND_C7_DST_C_FMASK 0x3 +#define G2D_BLEND_C7_AR_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_A_FSHIFT 8 +#define G2D_BLEND_C7_AR_A_FMASK 0x1 +#define G2D_BLEND_C7_AR_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_B_FSHIFT 9 +#define G2D_BLEND_C7_AR_B_FMASK 0x1 +#define G2D_BLEND_C7_AR_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_C_FSHIFT 10 +#define G2D_BLEND_C7_AR_C_FMASK 0x1 +#define G2D_BLEND_C7_AR_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_D_FSHIFT 11 +#define G2D_BLEND_C7_AR_D_FMASK 0x1 +#define G2D_BLEND_C7_INV_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_A_FSHIFT 12 +#define G2D_BLEND_C7_INV_A_FMASK 0x1 +#define G2D_BLEND_C7_INV_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_B_FSHIFT 13 +#define G2D_BLEND_C7_INV_B_FMASK 0x1 +#define G2D_BLEND_C7_INV_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_C_FSHIFT 14 +#define G2D_BLEND_C7_INV_C_FMASK 0x1 +#define G2D_BLEND_C7_INV_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_D_FSHIFT 15 +#define G2D_BLEND_C7_INV_D_FMASK 0x1 +#define G2D_BLEND_C7_SRC_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_A_FSHIFT 16 +#define G2D_BLEND_C7_SRC_A_FMASK 0x7 +#define G2D_BLEND_C7_SRC_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_B_FSHIFT 19 +#define G2D_BLEND_C7_SRC_B_FMASK 0x7 +#define G2D_BLEND_C7_SRC_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_C_FSHIFT 22 +#define G2D_BLEND_C7_SRC_C_FMASK 0x7 +#define G2D_BLEND_C7_SRC_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_D_FSHIFT 25 +#define G2D_BLEND_C7_SRC_D_FMASK 0x7 +#define G2D_BLEND_C7_CONST_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_A_FSHIFT 28 +#define G2D_BLEND_C7_CONST_A_FMASK 0x1 +#define G2D_BLEND_C7_CONST_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_B_FSHIFT 29 +#define G2D_BLEND_C7_CONST_B_FMASK 0x1 +#define G2D_BLEND_C7_CONST_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_C_FSHIFT 30 +#define G2D_BLEND_C7_CONST_C_FMASK 0x1 +#define G2D_BLEND_C7_CONST_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_D_FSHIFT 31 +#define G2D_BLEND_C7_CONST_D_FMASK 0x1 +#define G2D_CFG0_STRIDE_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_STRIDE_FSHIFT 0 +#define G2D_CFG0_STRIDE_FMASK 0xfff +#define G2D_CFG0_FORMAT_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_FORMAT_FSHIFT 12 +#define G2D_CFG0_FORMAT_FMASK 0xf +#define G2D_CFG0_TILED_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_TILED_FSHIFT 16 +#define G2D_CFG0_TILED_FMASK 0x1 +#define G2D_CFG0_SRGB_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SRGB_FSHIFT 17 +#define G2D_CFG0_SRGB_FMASK 0x1 +#define G2D_CFG0_SWAPWORDS_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPWORDS_FSHIFT 18 +#define G2D_CFG0_SWAPWORDS_FMASK 0x1 +#define G2D_CFG0_SWAPBYTES_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPBYTES_FSHIFT 19 +#define G2D_CFG0_SWAPBYTES_FMASK 0x1 +#define G2D_CFG0_SWAPALL_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPALL_FSHIFT 20 +#define G2D_CFG0_SWAPALL_FMASK 0x1 +#define G2D_CFG0_SWAPRB_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPRB_FSHIFT 21 +#define G2D_CFG0_SWAPRB_FMASK 0x1 +#define G2D_CFG0_SWAPBITS_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPBITS_FSHIFT 22 +#define G2D_CFG0_SWAPBITS_FMASK 0x1 +#define G2D_CFG0_STRIDESIGN_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_STRIDESIGN_FSHIFT 23 +#define G2D_CFG0_STRIDESIGN_FMASK 0x1 +#define G2D_CFG1_STRIDE_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_STRIDE_FSHIFT 0 +#define G2D_CFG1_STRIDE_FMASK 0xfff +#define G2D_CFG1_FORMAT_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_FORMAT_FSHIFT 12 +#define G2D_CFG1_FORMAT_FMASK 0xf +#define G2D_CFG1_TILED_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_TILED_FSHIFT 16 +#define G2D_CFG1_TILED_FMASK 0x1 +#define G2D_CFG1_SRGB_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SRGB_FSHIFT 17 +#define G2D_CFG1_SRGB_FMASK 0x1 +#define G2D_CFG1_SWAPWORDS_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPWORDS_FSHIFT 18 +#define G2D_CFG1_SWAPWORDS_FMASK 0x1 +#define G2D_CFG1_SWAPBYTES_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPBYTES_FSHIFT 19 +#define G2D_CFG1_SWAPBYTES_FMASK 0x1 +#define G2D_CFG1_SWAPALL_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPALL_FSHIFT 20 +#define G2D_CFG1_SWAPALL_FMASK 0x1 +#define G2D_CFG1_SWAPRB_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPRB_FSHIFT 21 +#define G2D_CFG1_SWAPRB_FMASK 0x1 +#define G2D_CFG1_SWAPBITS_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPBITS_FSHIFT 22 +#define G2D_CFG1_SWAPBITS_FMASK 0x1 +#define G2D_CFG1_STRIDESIGN_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_STRIDESIGN_FSHIFT 23 +#define G2D_CFG1_STRIDESIGN_FMASK 0x1 +#define G2D_CFG2_STRIDE_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_STRIDE_FSHIFT 0 +#define G2D_CFG2_STRIDE_FMASK 0xfff +#define G2D_CFG2_FORMAT_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_FORMAT_FSHIFT 12 +#define G2D_CFG2_FORMAT_FMASK 0xf +#define G2D_CFG2_TILED_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_TILED_FSHIFT 16 +#define G2D_CFG2_TILED_FMASK 0x1 +#define G2D_CFG2_SRGB_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SRGB_FSHIFT 17 +#define G2D_CFG2_SRGB_FMASK 0x1 +#define G2D_CFG2_SWAPWORDS_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPWORDS_FSHIFT 18 +#define G2D_CFG2_SWAPWORDS_FMASK 0x1 +#define G2D_CFG2_SWAPBYTES_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPBYTES_FSHIFT 19 +#define G2D_CFG2_SWAPBYTES_FMASK 0x1 +#define G2D_CFG2_SWAPALL_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPALL_FSHIFT 20 +#define G2D_CFG2_SWAPALL_FMASK 0x1 +#define G2D_CFG2_SWAPRB_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPRB_FSHIFT 21 +#define G2D_CFG2_SWAPRB_FMASK 0x1 +#define G2D_CFG2_SWAPBITS_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPBITS_FSHIFT 22 +#define G2D_CFG2_SWAPBITS_FMASK 0x1 +#define G2D_CFG2_STRIDESIGN_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_STRIDESIGN_FSHIFT 23 +#define G2D_CFG2_STRIDESIGN_FMASK 0x1 +#define G2D_CFG3_STRIDE_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_STRIDE_FSHIFT 0 +#define G2D_CFG3_STRIDE_FMASK 0xfff +#define G2D_CFG3_FORMAT_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_FORMAT_FSHIFT 12 +#define G2D_CFG3_FORMAT_FMASK 0xf +#define G2D_CFG3_TILED_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_TILED_FSHIFT 16 +#define G2D_CFG3_TILED_FMASK 0x1 +#define G2D_CFG3_SRGB_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SRGB_FSHIFT 17 +#define G2D_CFG3_SRGB_FMASK 0x1 +#define G2D_CFG3_SWAPWORDS_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPWORDS_FSHIFT 18 +#define G2D_CFG3_SWAPWORDS_FMASK 0x1 +#define G2D_CFG3_SWAPBYTES_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPBYTES_FSHIFT 19 +#define G2D_CFG3_SWAPBYTES_FMASK 0x1 +#define G2D_CFG3_SWAPALL_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPALL_FSHIFT 20 +#define G2D_CFG3_SWAPALL_FMASK 0x1 +#define G2D_CFG3_SWAPRB_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPRB_FSHIFT 21 +#define G2D_CFG3_SWAPRB_FMASK 0x1 +#define G2D_CFG3_SWAPBITS_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPBITS_FSHIFT 22 +#define G2D_CFG3_SWAPBITS_FMASK 0x1 +#define G2D_CFG3_STRIDESIGN_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_STRIDESIGN_FSHIFT 23 +#define G2D_CFG3_STRIDESIGN_FMASK 0x1 +#define G2D_COLOR_ARGB_FADDR ADDR_G2D_COLOR +#define G2D_COLOR_ARGB_FSHIFT 0 +#define G2D_COLOR_ARGB_FMASK 0xffffffff +#define G2D_CONFIG_DST_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DST_FSHIFT 0 +#define G2D_CONFIG_DST_FMASK 0x1 +#define G2D_CONFIG_SRC1_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC1_FSHIFT 1 +#define G2D_CONFIG_SRC1_FMASK 0x1 +#define G2D_CONFIG_SRC2_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC2_FSHIFT 2 +#define G2D_CONFIG_SRC2_FMASK 0x1 +#define G2D_CONFIG_SRC3_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC3_FSHIFT 3 +#define G2D_CONFIG_SRC3_FMASK 0x1 +#define G2D_CONFIG_SRCCK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRCCK_FSHIFT 4 +#define G2D_CONFIG_SRCCK_FMASK 0x1 +#define G2D_CONFIG_DSTCK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DSTCK_FSHIFT 5 +#define G2D_CONFIG_DSTCK_FMASK 0x1 +#define G2D_CONFIG_ROTATE_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ROTATE_FSHIFT 6 +#define G2D_CONFIG_ROTATE_FMASK 0x3 +#define G2D_CONFIG_OBS_GAMMA_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_OBS_GAMMA_FSHIFT 8 +#define G2D_CONFIG_OBS_GAMMA_FMASK 0x1 +#define G2D_CONFIG_IGNORECKALPHA_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_IGNORECKALPHA_FSHIFT 9 +#define G2D_CONFIG_IGNORECKALPHA_FMASK 0x1 +#define G2D_CONFIG_DITHER_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DITHER_FSHIFT 10 +#define G2D_CONFIG_DITHER_FMASK 0x1 +#define G2D_CONFIG_WRITESRGB_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_WRITESRGB_FSHIFT 11 +#define G2D_CONFIG_WRITESRGB_FMASK 0x1 +#define G2D_CONFIG_ARGBMASK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ARGBMASK_FSHIFT 12 +#define G2D_CONFIG_ARGBMASK_FMASK 0xf +#define G2D_CONFIG_ALPHATEX_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ALPHATEX_FSHIFT 16 +#define G2D_CONFIG_ALPHATEX_FMASK 0x1 +#define G2D_CONFIG_PALMLINES_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_PALMLINES_FSHIFT 17 +#define G2D_CONFIG_PALMLINES_FMASK 0x1 +#define G2D_CONFIG_NOLASTPIXEL_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_NOLASTPIXEL_FSHIFT 18 +#define G2D_CONFIG_NOLASTPIXEL_FMASK 0x1 +#define G2D_CONFIG_NOPROTECT_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_NOPROTECT_FSHIFT 19 +#define G2D_CONFIG_NOPROTECT_FMASK 0x1 +#define G2D_CONST0_ARGB_FADDR ADDR_G2D_CONST0 +#define G2D_CONST0_ARGB_FSHIFT 0 +#define G2D_CONST0_ARGB_FMASK 0xffffffff +#define G2D_CONST1_ARGB_FADDR ADDR_G2D_CONST1 +#define G2D_CONST1_ARGB_FSHIFT 0 +#define G2D_CONST1_ARGB_FMASK 0xffffffff +#define G2D_CONST2_ARGB_FADDR ADDR_G2D_CONST2 +#define G2D_CONST2_ARGB_FSHIFT 0 +#define G2D_CONST2_ARGB_FMASK 0xffffffff +#define G2D_CONST3_ARGB_FADDR ADDR_G2D_CONST3 +#define G2D_CONST3_ARGB_FSHIFT 0 +#define G2D_CONST3_ARGB_FMASK 0xffffffff +#define G2D_CONST4_ARGB_FADDR ADDR_G2D_CONST4 +#define G2D_CONST4_ARGB_FSHIFT 0 +#define G2D_CONST4_ARGB_FMASK 0xffffffff +#define G2D_CONST5_ARGB_FADDR ADDR_G2D_CONST5 +#define G2D_CONST5_ARGB_FSHIFT 0 +#define G2D_CONST5_ARGB_FMASK 0xffffffff +#define G2D_CONST6_ARGB_FADDR ADDR_G2D_CONST6 +#define G2D_CONST6_ARGB_FSHIFT 0 +#define G2D_CONST6_ARGB_FMASK 0xffffffff +#define G2D_CONST7_ARGB_FADDR ADDR_G2D_CONST7 +#define G2D_CONST7_ARGB_FSHIFT 0 +#define G2D_CONST7_ARGB_FMASK 0xffffffff +#define G2D_FOREGROUND_COLOR_FADDR ADDR_G2D_FOREGROUND +#define G2D_FOREGROUND_COLOR_FSHIFT 0 +#define G2D_FOREGROUND_COLOR_FMASK 0xffffffff +#define G2D_GRADIENT_INSTRUCTIONS_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_INSTRUCTIONS_FSHIFT 0 +#define G2D_GRADIENT_INSTRUCTIONS_FMASK 0x7 +#define G2D_GRADIENT_INSTRUCTIONS2_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_INSTRUCTIONS2_FSHIFT 3 +#define G2D_GRADIENT_INSTRUCTIONS2_FMASK 0x7 +#define G2D_GRADIENT_ENABLE_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_ENABLE_FSHIFT 6 +#define G2D_GRADIENT_ENABLE_FMASK 0x1 +#define G2D_GRADIENT_ENABLE2_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_ENABLE2_FSHIFT 7 +#define G2D_GRADIENT_ENABLE2_FMASK 0x1 +#define G2D_GRADIENT_SEL_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_SEL_FSHIFT 8 +#define G2D_GRADIENT_SEL_FMASK 0x1 +#define G2D_IDLE_IRQ_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_IRQ_FSHIFT 0 +#define G2D_IDLE_IRQ_FMASK 0x1 +#define G2D_IDLE_BCFLUSH_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_BCFLUSH_FSHIFT 1 +#define G2D_IDLE_BCFLUSH_FMASK 0x1 +#define G2D_IDLE_V3_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_V3_FSHIFT 2 +#define G2D_IDLE_V3_FMASK 0x1 +#define G2D_INPUT_COLOR_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_COLOR_FSHIFT 0 +#define G2D_INPUT_COLOR_FMASK 0x1 +#define G2D_INPUT_SCOORD1_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_SCOORD1_FSHIFT 1 +#define G2D_INPUT_SCOORD1_FMASK 0x1 +#define G2D_INPUT_SCOORD2_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_SCOORD2_FSHIFT 2 +#define G2D_INPUT_SCOORD2_FMASK 0x1 +#define G2D_INPUT_COPYCOORD_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_COPYCOORD_FSHIFT 3 +#define G2D_INPUT_COPYCOORD_FMASK 0x1 +#define G2D_INPUT_VGMODE_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_VGMODE_FSHIFT 4 +#define G2D_INPUT_VGMODE_FMASK 0x1 +#define G2D_INPUT_LINEMODE_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_LINEMODE_FSHIFT 5 +#define G2D_INPUT_LINEMODE_FMASK 0x1 +#define G2D_MASK_YMASK_FADDR ADDR_G2D_MASK +#define G2D_MASK_YMASK_FSHIFT 0 +#define G2D_MASK_YMASK_FMASK 0xfff +#define G2D_MASK_XMASK_FADDR ADDR_G2D_MASK +#define G2D_MASK_XMASK_FSHIFT 12 +#define G2D_MASK_XMASK_FMASK 0xfff +#define G2D_ROP_ROP_FADDR ADDR_G2D_ROP +#define G2D_ROP_ROP_FSHIFT 0 +#define G2D_ROP_ROP_FMASK 0xffff +#define G2D_SCISSORX_LEFT_FADDR ADDR_G2D_SCISSORX +#define G2D_SCISSORX_LEFT_FSHIFT 0 +#define G2D_SCISSORX_LEFT_FMASK 0x7ff +#define G2D_SCISSORX_RIGHT_FADDR ADDR_G2D_SCISSORX +#define G2D_SCISSORX_RIGHT_FSHIFT 11 +#define G2D_SCISSORX_RIGHT_FMASK 0x7ff +#define G2D_SCISSORY_TOP_FADDR ADDR_G2D_SCISSORY +#define G2D_SCISSORY_TOP_FSHIFT 0 +#define G2D_SCISSORY_TOP_FMASK 0x7ff +#define G2D_SCISSORY_BOTTOM_FADDR ADDR_G2D_SCISSORY +#define G2D_SCISSORY_BOTTOM_FSHIFT 11 +#define G2D_SCISSORY_BOTTOM_FMASK 0x7ff +#define G2D_SXY_Y_FADDR ADDR_G2D_SXY +#define G2D_SXY_Y_FSHIFT 0 +#define G2D_SXY_Y_FMASK 0x7ff +#define G2D_SXY_PAD_FADDR ADDR_G2D_SXY +#define G2D_SXY_PAD_FSHIFT 11 +#define G2D_SXY_PAD_FMASK 0x1f +#define G2D_SXY_X_FADDR ADDR_G2D_SXY +#define G2D_SXY_X_FSHIFT 16 +#define G2D_SXY_X_FMASK 0x7ff +#define G2D_SXY2_Y_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_Y_FSHIFT 0 +#define G2D_SXY2_Y_FMASK 0x7ff +#define G2D_SXY2_PAD_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_PAD_FSHIFT 11 +#define G2D_SXY2_PAD_FMASK 0x1f +#define G2D_SXY2_X_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_X_FSHIFT 16 +#define G2D_SXY2_X_FMASK 0x7ff +#define G2D_VGSPAN_WIDTH_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_WIDTH_FSHIFT 0 +#define G2D_VGSPAN_WIDTH_FMASK 0xfff +#define G2D_VGSPAN_PAD_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_PAD_FSHIFT 12 +#define G2D_VGSPAN_PAD_FMASK 0xf +#define G2D_VGSPAN_COVERAGE_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_COVERAGE_FSHIFT 16 +#define G2D_VGSPAN_COVERAGE_FMASK 0xf +#define G2D_WIDTHHEIGHT_HEIGHT_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_HEIGHT_FSHIFT 0 +#define G2D_WIDTHHEIGHT_HEIGHT_FMASK 0xfff +#define G2D_WIDTHHEIGHT_PAD_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_PAD_FSHIFT 12 +#define G2D_WIDTHHEIGHT_PAD_FMASK 0xf +#define G2D_WIDTHHEIGHT_WIDTH_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_WIDTH_FSHIFT 16 +#define G2D_WIDTHHEIGHT_WIDTH_FMASK 0xfff +#define G2D_XY_Y_FADDR ADDR_G2D_XY +#define G2D_XY_Y_FSHIFT 0 +#define G2D_XY_Y_FMASK 0xfff +#define G2D_XY_PAD_FADDR ADDR_G2D_XY +#define G2D_XY_PAD_FSHIFT 12 +#define G2D_XY_PAD_FMASK 0xf +#define G2D_XY_X_FADDR ADDR_G2D_XY +#define G2D_XY_X_FSHIFT 16 +#define G2D_XY_X_FMASK 0xfff +#define GRADW_BORDERCOLOR_COLOR_FADDR ADDR_GRADW_BORDERCOLOR +#define GRADW_BORDERCOLOR_COLOR_FSHIFT 0 +#define GRADW_BORDERCOLOR_COLOR_FMASK 0xffffffff +#define GRADW_CONST0_VALUE_FADDR ADDR_GRADW_CONST0 +#define GRADW_CONST0_VALUE_FSHIFT 0 +#define GRADW_CONST0_VALUE_FMASK 0xffff +#define GRADW_CONST1_VALUE_FADDR ADDR_GRADW_CONST1 +#define GRADW_CONST1_VALUE_FSHIFT 0 +#define GRADW_CONST1_VALUE_FMASK 0xffff +#define GRADW_CONST2_VALUE_FADDR ADDR_GRADW_CONST2 +#define GRADW_CONST2_VALUE_FSHIFT 0 +#define GRADW_CONST2_VALUE_FMASK 0xffff +#define GRADW_CONST3_VALUE_FADDR ADDR_GRADW_CONST3 +#define GRADW_CONST3_VALUE_FSHIFT 0 +#define GRADW_CONST3_VALUE_FMASK 0xffff +#define GRADW_CONST4_VALUE_FADDR ADDR_GRADW_CONST4 +#define GRADW_CONST4_VALUE_FSHIFT 0 +#define GRADW_CONST4_VALUE_FMASK 0xffff +#define GRADW_CONST5_VALUE_FADDR ADDR_GRADW_CONST5 +#define GRADW_CONST5_VALUE_FSHIFT 0 +#define GRADW_CONST5_VALUE_FMASK 0xffff +#define GRADW_CONST6_VALUE_FADDR ADDR_GRADW_CONST6 +#define GRADW_CONST6_VALUE_FSHIFT 0 +#define GRADW_CONST6_VALUE_FMASK 0xffff +#define GRADW_CONST7_VALUE_FADDR ADDR_GRADW_CONST7 +#define GRADW_CONST7_VALUE_FSHIFT 0 +#define GRADW_CONST7_VALUE_FMASK 0xffff +#define GRADW_CONST8_VALUE_FADDR ADDR_GRADW_CONST8 +#define GRADW_CONST8_VALUE_FSHIFT 0 +#define GRADW_CONST8_VALUE_FMASK 0xffff +#define GRADW_CONST9_VALUE_FADDR ADDR_GRADW_CONST9 +#define GRADW_CONST9_VALUE_FSHIFT 0 +#define GRADW_CONST9_VALUE_FMASK 0xffff +#define GRADW_CONSTA_VALUE_FADDR ADDR_GRADW_CONSTA +#define GRADW_CONSTA_VALUE_FSHIFT 0 +#define GRADW_CONSTA_VALUE_FMASK 0xffff +#define GRADW_CONSTB_VALUE_FADDR ADDR_GRADW_CONSTB +#define GRADW_CONSTB_VALUE_FSHIFT 0 +#define GRADW_CONSTB_VALUE_FMASK 0xffff +#define GRADW_INST0_SRC_E_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_E_FSHIFT 0 +#define GRADW_INST0_SRC_E_FMASK 0x1f +#define GRADW_INST0_SRC_D_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_D_FSHIFT 5 +#define GRADW_INST0_SRC_D_FMASK 0x1f +#define GRADW_INST0_SRC_C_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_C_FSHIFT 10 +#define GRADW_INST0_SRC_C_FMASK 0x1f +#define GRADW_INST0_SRC_B_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_B_FSHIFT 15 +#define GRADW_INST0_SRC_B_FMASK 0x1f +#define GRADW_INST0_SRC_A_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_A_FSHIFT 20 +#define GRADW_INST0_SRC_A_FMASK 0x1f +#define GRADW_INST0_DST_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_DST_FSHIFT 25 +#define GRADW_INST0_DST_FMASK 0xf +#define GRADW_INST0_OPCODE_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_OPCODE_FSHIFT 29 +#define GRADW_INST0_OPCODE_FMASK 0x3 +#define GRADW_INST1_SRC_E_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_E_FSHIFT 0 +#define GRADW_INST1_SRC_E_FMASK 0x1f +#define GRADW_INST1_SRC_D_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_D_FSHIFT 5 +#define GRADW_INST1_SRC_D_FMASK 0x1f +#define GRADW_INST1_SRC_C_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_C_FSHIFT 10 +#define GRADW_INST1_SRC_C_FMASK 0x1f +#define GRADW_INST1_SRC_B_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_B_FSHIFT 15 +#define GRADW_INST1_SRC_B_FMASK 0x1f +#define GRADW_INST1_SRC_A_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_A_FSHIFT 20 +#define GRADW_INST1_SRC_A_FMASK 0x1f +#define GRADW_INST1_DST_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_DST_FSHIFT 25 +#define GRADW_INST1_DST_FMASK 0xf +#define GRADW_INST1_OPCODE_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_OPCODE_FSHIFT 29 +#define GRADW_INST1_OPCODE_FMASK 0x3 +#define GRADW_INST2_SRC_E_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_E_FSHIFT 0 +#define GRADW_INST2_SRC_E_FMASK 0x1f +#define GRADW_INST2_SRC_D_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_D_FSHIFT 5 +#define GRADW_INST2_SRC_D_FMASK 0x1f +#define GRADW_INST2_SRC_C_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_C_FSHIFT 10 +#define GRADW_INST2_SRC_C_FMASK 0x1f +#define GRADW_INST2_SRC_B_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_B_FSHIFT 15 +#define GRADW_INST2_SRC_B_FMASK 0x1f +#define GRADW_INST2_SRC_A_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_A_FSHIFT 20 +#define GRADW_INST2_SRC_A_FMASK 0x1f +#define GRADW_INST2_DST_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_DST_FSHIFT 25 +#define GRADW_INST2_DST_FMASK 0xf +#define GRADW_INST2_OPCODE_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_OPCODE_FSHIFT 29 +#define GRADW_INST2_OPCODE_FMASK 0x3 +#define GRADW_INST3_SRC_E_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_E_FSHIFT 0 +#define GRADW_INST3_SRC_E_FMASK 0x1f +#define GRADW_INST3_SRC_D_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_D_FSHIFT 5 +#define GRADW_INST3_SRC_D_FMASK 0x1f +#define GRADW_INST3_SRC_C_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_C_FSHIFT 10 +#define GRADW_INST3_SRC_C_FMASK 0x1f +#define GRADW_INST3_SRC_B_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_B_FSHIFT 15 +#define GRADW_INST3_SRC_B_FMASK 0x1f +#define GRADW_INST3_SRC_A_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_A_FSHIFT 20 +#define GRADW_INST3_SRC_A_FMASK 0x1f +#define GRADW_INST3_DST_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_DST_FSHIFT 25 +#define GRADW_INST3_DST_FMASK 0xf +#define GRADW_INST3_OPCODE_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_OPCODE_FSHIFT 29 +#define GRADW_INST3_OPCODE_FMASK 0x3 +#define GRADW_INST4_SRC_E_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_E_FSHIFT 0 +#define GRADW_INST4_SRC_E_FMASK 0x1f +#define GRADW_INST4_SRC_D_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_D_FSHIFT 5 +#define GRADW_INST4_SRC_D_FMASK 0x1f +#define GRADW_INST4_SRC_C_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_C_FSHIFT 10 +#define GRADW_INST4_SRC_C_FMASK 0x1f +#define GRADW_INST4_SRC_B_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_B_FSHIFT 15 +#define GRADW_INST4_SRC_B_FMASK 0x1f +#define GRADW_INST4_SRC_A_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_A_FSHIFT 20 +#define GRADW_INST4_SRC_A_FMASK 0x1f +#define GRADW_INST4_DST_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_DST_FSHIFT 25 +#define GRADW_INST4_DST_FMASK 0xf +#define GRADW_INST4_OPCODE_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_OPCODE_FSHIFT 29 +#define GRADW_INST4_OPCODE_FMASK 0x3 +#define GRADW_INST5_SRC_E_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_E_FSHIFT 0 +#define GRADW_INST5_SRC_E_FMASK 0x1f +#define GRADW_INST5_SRC_D_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_D_FSHIFT 5 +#define GRADW_INST5_SRC_D_FMASK 0x1f +#define GRADW_INST5_SRC_C_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_C_FSHIFT 10 +#define GRADW_INST5_SRC_C_FMASK 0x1f +#define GRADW_INST5_SRC_B_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_B_FSHIFT 15 +#define GRADW_INST5_SRC_B_FMASK 0x1f +#define GRADW_INST5_SRC_A_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_A_FSHIFT 20 +#define GRADW_INST5_SRC_A_FMASK 0x1f +#define GRADW_INST5_DST_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_DST_FSHIFT 25 +#define GRADW_INST5_DST_FMASK 0xf +#define GRADW_INST5_OPCODE_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_OPCODE_FSHIFT 29 +#define GRADW_INST5_OPCODE_FMASK 0x3 +#define GRADW_INST6_SRC_E_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_E_FSHIFT 0 +#define GRADW_INST6_SRC_E_FMASK 0x1f +#define GRADW_INST6_SRC_D_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_D_FSHIFT 5 +#define GRADW_INST6_SRC_D_FMASK 0x1f +#define GRADW_INST6_SRC_C_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_C_FSHIFT 10 +#define GRADW_INST6_SRC_C_FMASK 0x1f +#define GRADW_INST6_SRC_B_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_B_FSHIFT 15 +#define GRADW_INST6_SRC_B_FMASK 0x1f +#define GRADW_INST6_SRC_A_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_A_FSHIFT 20 +#define GRADW_INST6_SRC_A_FMASK 0x1f +#define GRADW_INST6_DST_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_DST_FSHIFT 25 +#define GRADW_INST6_DST_FMASK 0xf +#define GRADW_INST6_OPCODE_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_OPCODE_FSHIFT 29 +#define GRADW_INST6_OPCODE_FMASK 0x3 +#define GRADW_INST7_SRC_E_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_E_FSHIFT 0 +#define GRADW_INST7_SRC_E_FMASK 0x1f +#define GRADW_INST7_SRC_D_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_D_FSHIFT 5 +#define GRADW_INST7_SRC_D_FMASK 0x1f +#define GRADW_INST7_SRC_C_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_C_FSHIFT 10 +#define GRADW_INST7_SRC_C_FMASK 0x1f +#define GRADW_INST7_SRC_B_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_B_FSHIFT 15 +#define GRADW_INST7_SRC_B_FMASK 0x1f +#define GRADW_INST7_SRC_A_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_A_FSHIFT 20 +#define GRADW_INST7_SRC_A_FMASK 0x1f +#define GRADW_INST7_DST_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_DST_FSHIFT 25 +#define GRADW_INST7_DST_FMASK 0xf +#define GRADW_INST7_OPCODE_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_OPCODE_FSHIFT 29 +#define GRADW_INST7_OPCODE_FMASK 0x3 +#define GRADW_TEXBASE_ADDR_FADDR ADDR_GRADW_TEXBASE +#define GRADW_TEXBASE_ADDR_FSHIFT 0 +#define GRADW_TEXBASE_ADDR_FMASK 0xffffffff +#define GRADW_TEXCFG_STRIDE_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_STRIDE_FSHIFT 0 +#define GRADW_TEXCFG_STRIDE_FMASK 0xfff +#define GRADW_TEXCFG_FORMAT_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_FORMAT_FSHIFT 12 +#define GRADW_TEXCFG_FORMAT_FMASK 0xf +#define GRADW_TEXCFG_TILED_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_TILED_FSHIFT 16 +#define GRADW_TEXCFG_TILED_FMASK 0x1 +#define GRADW_TEXCFG_WRAPU_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_WRAPU_FSHIFT 17 +#define GRADW_TEXCFG_WRAPU_FMASK 0x3 +#define GRADW_TEXCFG_WRAPV_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_WRAPV_FSHIFT 19 +#define GRADW_TEXCFG_WRAPV_FMASK 0x3 +#define GRADW_TEXCFG_BILIN_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_BILIN_FSHIFT 21 +#define GRADW_TEXCFG_BILIN_FMASK 0x1 +#define GRADW_TEXCFG_SRGB_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SRGB_FSHIFT 22 +#define GRADW_TEXCFG_SRGB_FMASK 0x1 +#define GRADW_TEXCFG_PREMULTIPLY_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_PREMULTIPLY_FSHIFT 23 +#define GRADW_TEXCFG_PREMULTIPLY_FMASK 0x1 +#define GRADW_TEXCFG_SWAPWORDS_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPWORDS_FSHIFT 24 +#define GRADW_TEXCFG_SWAPWORDS_FMASK 0x1 +#define GRADW_TEXCFG_SWAPBYTES_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPBYTES_FSHIFT 25 +#define GRADW_TEXCFG_SWAPBYTES_FMASK 0x1 +#define GRADW_TEXCFG_SWAPALL_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPALL_FSHIFT 26 +#define GRADW_TEXCFG_SWAPALL_FMASK 0x1 +#define GRADW_TEXCFG_SWAPRB_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPRB_FSHIFT 27 +#define GRADW_TEXCFG_SWAPRB_FMASK 0x1 +#define GRADW_TEXCFG_TEX2D_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_TEX2D_FSHIFT 28 +#define GRADW_TEXCFG_TEX2D_FMASK 0x1 +#define GRADW_TEXCFG_SWAPBITS_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPBITS_FSHIFT 29 +#define GRADW_TEXCFG_SWAPBITS_FMASK 0x1 +#define GRADW_TEXSIZE_WIDTH_FADDR ADDR_GRADW_TEXSIZE +#define GRADW_TEXSIZE_WIDTH_FSHIFT 0 +#define GRADW_TEXSIZE_WIDTH_FMASK 0x7ff +#define GRADW_TEXSIZE_HEIGHT_FADDR ADDR_GRADW_TEXSIZE +#define GRADW_TEXSIZE_HEIGHT_FSHIFT 11 +#define GRADW_TEXSIZE_HEIGHT_FMASK 0x7ff +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FSHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FMASK 0x3f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FSHIFT 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FMASK 0x1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FSHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FSHIFT 8 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FSHIFT 9 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FMASK 0x1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_PAGE_SIZE_FSHIFT 10 +#define MH_ARBITER_CONFIG_PAGE_SIZE_FMASK 0x7 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FSHIFT 13 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FSHIFT 14 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FSHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FSHIFT 16 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FMASK 0x3f +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FSHIFT 22 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FSHIFT 23 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FSHIFT 24 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FSHIFT 25 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FSHIFT 26 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FMASK 0x1 +#define MH_AXI_ERROR_AXI_READ_ID_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_READ_ID_FSHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ID_FMASK 0x7 +#define MH_AXI_ERROR_AXI_READ_ERROR_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_READ_ERROR_FSHIFT 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_FMASK 0x1 +#define MH_AXI_ERROR_AXI_WRITE_ID_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_WRITE_ID_FSHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ID_FMASK 0x7 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FSHIFT 7 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_AXI_HALT_CONTROL_AXI_HALT_FADDR ADDR_MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL_AXI_HALT_FSHIFT 0 +#define MH_AXI_HALT_CONTROL_AXI_HALT_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FSHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD_FSHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_PAD_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FSHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD2_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD2_FSHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_PAD2_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FSHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD3_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD3_FSHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAD3_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FSHIFT 12 +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FMASK 0x7 +#define MH_DEBUG_CTRL_INDEX_FADDR ADDR_MH_DEBUG_CTRL +#define MH_DEBUG_CTRL_INDEX_FSHIFT 0 +#define MH_DEBUG_CTRL_INDEX_FMASK 0x3f +#define MH_DEBUG_DATA_DATA_FADDR ADDR_MH_DEBUG_DATA +#define MH_DEBUG_DATA_DATA_FSHIFT 0 +#define MH_DEBUG_DATA_DATA_FMASK 0xffffffff +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_MMU_CONFIG_MMU_ENABLE_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_MMU_ENABLE_FSHIFT 0 +#define MH_MMU_CONFIG_MMU_ENABLE_FMASK 0x1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FSHIFT 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FMASK 0x1 +#define MH_MMU_CONFIG_PAD_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_PAD_FSHIFT 2 +#define MH_MMU_CONFIG_PAD_FMASK 0x3 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FSHIFT 4 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FSHIFT 6 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FSHIFT 8 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FSHIFT 10 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FSHIFT 12 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FSHIFT 14 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FSHIFT 16 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FSHIFT 18 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FSHIFT 20 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FSHIFT 22 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FSHIFT 24 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FADDR ADDR_MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FSHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FMASK 0x1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FADDR ADDR_MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FSHIFT 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FMASK 0x1 +#define MH_MMU_MPU_BASE_ZERO_FADDR ADDR_MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE_ZERO_FSHIFT 0 +#define MH_MMU_MPU_BASE_ZERO_FMASK 0xfff +#define MH_MMU_MPU_BASE_MPU_BASE_FADDR ADDR_MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE_MPU_BASE_FSHIFT 12 +#define MH_MMU_MPU_BASE_MPU_BASE_FMASK 0xfffff +#define MH_MMU_MPU_END_ZERO_FADDR ADDR_MH_MMU_MPU_END +#define MH_MMU_MPU_END_ZERO_FSHIFT 0 +#define MH_MMU_MPU_END_ZERO_FMASK 0xfff +#define MH_MMU_MPU_END_MPU_END_FADDR ADDR_MH_MMU_MPU_END +#define MH_MMU_MPU_END_MPU_END_FSHIFT 12 +#define MH_MMU_MPU_END_MPU_END_FMASK 0xfffff +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FSHIFT 0 +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_OP_TYPE_FSHIFT 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FSHIFT 2 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_PAGE_FAULT_AXI_ID_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_AXI_ID_FSHIFT 4 +#define MH_MMU_PAGE_FAULT_AXI_ID_FMASK 0x7 +#define MH_MMU_PAGE_FAULT_PAD_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_PAD_FSHIFT 7 +#define MH_MMU_PAGE_FAULT_PAD_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FSHIFT 8 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FSHIFT 9 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FSHIFT 10 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FSHIFT 11 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_REQ_VA_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_REQ_VA_FSHIFT 12 +#define MH_MMU_PAGE_FAULT_REQ_VA_FMASK 0xfffff +#define MH_MMU_PT_BASE_ZERO_FADDR ADDR_MH_MMU_PT_BASE +#define MH_MMU_PT_BASE_ZERO_FSHIFT 0 +#define MH_MMU_PT_BASE_ZERO_FMASK 0xfff +#define MH_MMU_PT_BASE_PT_BASE_FADDR ADDR_MH_MMU_PT_BASE +#define MH_MMU_PT_BASE_PT_BASE_FSHIFT 12 +#define MH_MMU_PT_BASE_PT_BASE_FMASK 0xfffff +#define MH_MMU_TRAN_ERROR_ZERO_FADDR ADDR_MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR_ZERO_FSHIFT 0 +#define MH_MMU_TRAN_ERROR_ZERO_FMASK 0x1f +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FADDR ADDR_MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FSHIFT 5 +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FMASK 0x7ffffff +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FADDR ADDR_MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FSHIFT 0 +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FMASK 0xfff +#define MH_MMU_VA_RANGE_VA_BASE_FADDR ADDR_MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE_VA_BASE_FSHIFT 12 +#define MH_MMU_VA_RANGE_VA_BASE_FMASK 0xfffff +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FSHIFT 0 +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FMASK 0xff +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FSHIFT 0 +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FMASK 0xffff +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FSHIFT 0 +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FSHIFT 0 +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FMASK 0xff +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FSHIFT 0 +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FMASK 0xff +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FSHIFT 0 +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FMASK 0xffff +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FSHIFT 0 +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FSHIFT 0 +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FMASK 0xff +#define MMU_READ_ADDR_ADDR_FADDR ADDR_MMU_READ_ADDR +#define MMU_READ_ADDR_ADDR_FSHIFT 0 +#define MMU_READ_ADDR_ADDR_FMASK 0x7fff +#define MMU_READ_DATA_DATA_FADDR ADDR_MMU_READ_DATA +#define MMU_READ_DATA_DATA_FSHIFT 0 +#define MMU_READ_DATA_DATA_FMASK 0xffffffff +#define VGV1_CBASE1_ADDR_FADDR ADDR_VGV1_CBASE1 +#define VGV1_CBASE1_ADDR_FSHIFT 0 +#define VGV1_CBASE1_ADDR_FMASK 0xffffffff +#define VGV1_CFG1_WINDRULE_FADDR ADDR_VGV1_CFG1 +#define VGV1_CFG1_WINDRULE_FSHIFT 0 +#define VGV1_CFG1_WINDRULE_FMASK 0x1 +#define VGV1_CFG2_AAMODE_FADDR ADDR_VGV1_CFG2 +#define VGV1_CFG2_AAMODE_FSHIFT 0 +#define VGV1_CFG2_AAMODE_FMASK 0x3 +#define VGV1_DIRTYBASE_ADDR_FADDR ADDR_VGV1_DIRTYBASE +#define VGV1_DIRTYBASE_ADDR_FSHIFT 0 +#define VGV1_DIRTYBASE_ADDR_FMASK 0xffffffff +#define VGV1_FILL_INHERIT_FADDR ADDR_VGV1_FILL +#define VGV1_FILL_INHERIT_FSHIFT 0 +#define VGV1_FILL_INHERIT_FMASK 0x1 +#define VGV1_SCISSORX_LEFT_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_LEFT_FSHIFT 0 +#define VGV1_SCISSORX_LEFT_FMASK 0x7ff +#define VGV1_SCISSORX_PAD_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_PAD_FSHIFT 11 +#define VGV1_SCISSORX_PAD_FMASK 0x1f +#define VGV1_SCISSORX_RIGHT_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_RIGHT_FSHIFT 16 +#define VGV1_SCISSORX_RIGHT_FMASK 0x7ff +#define VGV1_SCISSORY_TOP_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_TOP_FSHIFT 0 +#define VGV1_SCISSORY_TOP_FMASK 0x7ff +#define VGV1_SCISSORY_PAD_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_PAD_FSHIFT 11 +#define VGV1_SCISSORY_PAD_FMASK 0x1f +#define VGV1_SCISSORY_BOTTOM_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_BOTTOM_FSHIFT 16 +#define VGV1_SCISSORY_BOTTOM_FMASK 0x7ff +#define VGV1_TILEOFS_X_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_X_FSHIFT 0 +#define VGV1_TILEOFS_X_FMASK 0xfff +#define VGV1_TILEOFS_Y_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_Y_FSHIFT 12 +#define VGV1_TILEOFS_Y_FMASK 0xfff +#define VGV1_TILEOFS_LEFTMOST_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_LEFTMOST_FSHIFT 24 +#define VGV1_TILEOFS_LEFTMOST_FMASK 0x1 +#define VGV1_UBASE2_ADDR_FADDR ADDR_VGV1_UBASE2 +#define VGV1_UBASE2_ADDR_FSHIFT 0 +#define VGV1_UBASE2_ADDR_FMASK 0xffffffff +#define VGV1_VTX0_X_FADDR ADDR_VGV1_VTX0 +#define VGV1_VTX0_X_FSHIFT 0 +#define VGV1_VTX0_X_FMASK 0xffff +#define VGV1_VTX0_Y_FADDR ADDR_VGV1_VTX0 +#define VGV1_VTX0_Y_FSHIFT 16 +#define VGV1_VTX0_Y_FMASK 0xffff +#define VGV1_VTX1_X_FADDR ADDR_VGV1_VTX1 +#define VGV1_VTX1_X_FSHIFT 0 +#define VGV1_VTX1_X_FMASK 0xffff +#define VGV1_VTX1_Y_FADDR ADDR_VGV1_VTX1 +#define VGV1_VTX1_Y_FSHIFT 16 +#define VGV1_VTX1_Y_FMASK 0xffff +#define VGV2_ACCURACY_F_FADDR ADDR_VGV2_ACCURACY +#define VGV2_ACCURACY_F_FSHIFT 0 +#define VGV2_ACCURACY_F_FMASK 0xffffff +#define VGV2_ACTION_ACTION_FADDR ADDR_VGV2_ACTION +#define VGV2_ACTION_ACTION_FSHIFT 0 +#define VGV2_ACTION_ACTION_FMASK 0xf +#define VGV2_ARCCOS_F_FADDR ADDR_VGV2_ARCCOS +#define VGV2_ARCCOS_F_FSHIFT 0 +#define VGV2_ARCCOS_F_FMASK 0xffffff +#define VGV2_ARCSIN_F_FADDR ADDR_VGV2_ARCSIN +#define VGV2_ARCSIN_F_FSHIFT 0 +#define VGV2_ARCSIN_F_FMASK 0xffffff +#define VGV2_ARCTAN_F_FADDR ADDR_VGV2_ARCTAN +#define VGV2_ARCTAN_F_FSHIFT 0 +#define VGV2_ARCTAN_F_FMASK 0xffffff +#define VGV2_BBOXMAXX_F_FADDR ADDR_VGV2_BBOXMAXX +#define VGV2_BBOXMAXX_F_FSHIFT 0 +#define VGV2_BBOXMAXX_F_FMASK 0xffffff +#define VGV2_BBOXMAXY_F_FADDR ADDR_VGV2_BBOXMAXY +#define VGV2_BBOXMAXY_F_FSHIFT 0 +#define VGV2_BBOXMAXY_F_FMASK 0xffffff +#define VGV2_BBOXMINX_F_FADDR ADDR_VGV2_BBOXMINX +#define VGV2_BBOXMINX_F_FSHIFT 0 +#define VGV2_BBOXMINX_F_FMASK 0xffffff +#define VGV2_BBOXMINY_F_FADDR ADDR_VGV2_BBOXMINY +#define VGV2_BBOXMINY_F_FSHIFT 0 +#define VGV2_BBOXMINY_F_FMASK 0xffffff +#define VGV2_BIAS_F_FADDR ADDR_VGV2_BIAS +#define VGV2_BIAS_F_FSHIFT 0 +#define VGV2_BIAS_F_FMASK 0xffffff +#define VGV2_C1X_F_FADDR ADDR_VGV2_C1X +#define VGV2_C1X_F_FSHIFT 0 +#define VGV2_C1X_F_FMASK 0xffffff +#define VGV2_C1XREL_F_FADDR ADDR_VGV2_C1XREL +#define VGV2_C1XREL_F_FSHIFT 0 +#define VGV2_C1XREL_F_FMASK 0xffffff +#define VGV2_C1Y_F_FADDR ADDR_VGV2_C1Y +#define VGV2_C1Y_F_FSHIFT 0 +#define VGV2_C1Y_F_FMASK 0xffffff +#define VGV2_C1YREL_F_FADDR ADDR_VGV2_C1YREL +#define VGV2_C1YREL_F_FSHIFT 0 +#define VGV2_C1YREL_F_FMASK 0xffffff +#define VGV2_C2X_F_FADDR ADDR_VGV2_C2X +#define VGV2_C2X_F_FSHIFT 0 +#define VGV2_C2X_F_FMASK 0xffffff +#define VGV2_C2XREL_F_FADDR ADDR_VGV2_C2XREL +#define VGV2_C2XREL_F_FSHIFT 0 +#define VGV2_C2XREL_F_FMASK 0xffffff +#define VGV2_C2Y_F_FADDR ADDR_VGV2_C2Y +#define VGV2_C2Y_F_FSHIFT 0 +#define VGV2_C2Y_F_FMASK 0xffffff +#define VGV2_C2YREL_F_FADDR ADDR_VGV2_C2YREL +#define VGV2_C2YREL_F_FSHIFT 0 +#define VGV2_C2YREL_F_FMASK 0xffffff +#define VGV2_C3X_F_FADDR ADDR_VGV2_C3X +#define VGV2_C3X_F_FSHIFT 0 +#define VGV2_C3X_F_FMASK 0xffffff +#define VGV2_C3XREL_F_FADDR ADDR_VGV2_C3XREL +#define VGV2_C3XREL_F_FSHIFT 0 +#define VGV2_C3XREL_F_FMASK 0xffffff +#define VGV2_C3Y_F_FADDR ADDR_VGV2_C3Y +#define VGV2_C3Y_F_FSHIFT 0 +#define VGV2_C3Y_F_FMASK 0xffffff +#define VGV2_C3YREL_F_FADDR ADDR_VGV2_C3YREL +#define VGV2_C3YREL_F_FSHIFT 0 +#define VGV2_C3YREL_F_FMASK 0xffffff +#define VGV2_C4X_F_FADDR ADDR_VGV2_C4X +#define VGV2_C4X_F_FSHIFT 0 +#define VGV2_C4X_F_FMASK 0xffffff +#define VGV2_C4XREL_F_FADDR ADDR_VGV2_C4XREL +#define VGV2_C4XREL_F_FSHIFT 0 +#define VGV2_C4XREL_F_FMASK 0xffffff +#define VGV2_C4Y_F_FADDR ADDR_VGV2_C4Y +#define VGV2_C4Y_F_FSHIFT 0 +#define VGV2_C4Y_F_FMASK 0xffffff +#define VGV2_C4YREL_F_FADDR ADDR_VGV2_C4YREL +#define VGV2_C4YREL_F_FSHIFT 0 +#define VGV2_C4YREL_F_FMASK 0xffffff +#define VGV2_CLIP_F_FADDR ADDR_VGV2_CLIP +#define VGV2_CLIP_F_FSHIFT 0 +#define VGV2_CLIP_F_FMASK 0xffffff +#define VGV2_FIRST_DUMMY_FADDR ADDR_VGV2_FIRST +#define VGV2_FIRST_DUMMY_FSHIFT 0 +#define VGV2_FIRST_DUMMY_FMASK 0x1 +#define VGV2_LAST_DUMMY_FADDR ADDR_VGV2_LAST +#define VGV2_LAST_DUMMY_FSHIFT 0 +#define VGV2_LAST_DUMMY_FMASK 0x1 +#define VGV2_MITER_F_FADDR ADDR_VGV2_MITER +#define VGV2_MITER_F_FSHIFT 0 +#define VGV2_MITER_F_FMASK 0xffffff +#define VGV2_MODE_MAXSPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_MAXSPLIT_FSHIFT 0 +#define VGV2_MODE_MAXSPLIT_FMASK 0xf +#define VGV2_MODE_CAP_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_CAP_FSHIFT 4 +#define VGV2_MODE_CAP_FMASK 0x3 +#define VGV2_MODE_JOIN_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_JOIN_FSHIFT 6 +#define VGV2_MODE_JOIN_FMASK 0x3 +#define VGV2_MODE_STROKE_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_STROKE_FSHIFT 8 +#define VGV2_MODE_STROKE_FMASK 0x1 +#define VGV2_MODE_STROKESPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_STROKESPLIT_FSHIFT 9 +#define VGV2_MODE_STROKESPLIT_FMASK 0x1 +#define VGV2_MODE_FULLSPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_FULLSPLIT_FSHIFT 10 +#define VGV2_MODE_FULLSPLIT_FMASK 0x1 +#define VGV2_MODE_NODOTS_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_NODOTS_FSHIFT 11 +#define VGV2_MODE_NODOTS_FMASK 0x1 +#define VGV2_MODE_OPENFILL_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_OPENFILL_FSHIFT 12 +#define VGV2_MODE_OPENFILL_FMASK 0x1 +#define VGV2_MODE_DROPLEFT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_DROPLEFT_FSHIFT 13 +#define VGV2_MODE_DROPLEFT_FMASK 0x1 +#define VGV2_MODE_DROPOTHER_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_DROPOTHER_FSHIFT 14 +#define VGV2_MODE_DROPOTHER_FMASK 0x1 +#define VGV2_MODE_SYMMETRICJOINS_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SYMMETRICJOINS_FSHIFT 15 +#define VGV2_MODE_SYMMETRICJOINS_FMASK 0x1 +#define VGV2_MODE_SIMPLESTROKE_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SIMPLESTROKE_FSHIFT 16 +#define VGV2_MODE_SIMPLESTROKE_FMASK 0x1 +#define VGV2_MODE_SIMPLECLIP_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SIMPLECLIP_FSHIFT 17 +#define VGV2_MODE_SIMPLECLIP_FMASK 0x1 +#define VGV2_MODE_EXPONENTADD_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_EXPONENTADD_FSHIFT 18 +#define VGV2_MODE_EXPONENTADD_FMASK 0x3f +#define VGV2_RADIUS_F_FADDR ADDR_VGV2_RADIUS +#define VGV2_RADIUS_F_FSHIFT 0 +#define VGV2_RADIUS_F_FMASK 0xffffff +#define VGV2_SCALE_F_FADDR ADDR_VGV2_SCALE +#define VGV2_SCALE_F_FSHIFT 0 +#define VGV2_SCALE_F_FMASK 0xffffff +#define VGV2_THINRADIUS_F_FADDR ADDR_VGV2_THINRADIUS +#define VGV2_THINRADIUS_F_FSHIFT 0 +#define VGV2_THINRADIUS_F_FMASK 0xffffff +#define VGV2_XFSTXX_F_FADDR ADDR_VGV2_XFSTXX +#define VGV2_XFSTXX_F_FSHIFT 0 +#define VGV2_XFSTXX_F_FMASK 0xffffff +#define VGV2_XFSTXY_F_FADDR ADDR_VGV2_XFSTXY +#define VGV2_XFSTXY_F_FSHIFT 0 +#define VGV2_XFSTXY_F_FMASK 0xffffff +#define VGV2_XFSTYX_F_FADDR ADDR_VGV2_XFSTYX +#define VGV2_XFSTYX_F_FSHIFT 0 +#define VGV2_XFSTYX_F_FMASK 0xffffff +#define VGV2_XFSTYY_F_FADDR ADDR_VGV2_XFSTYY +#define VGV2_XFSTYY_F_FSHIFT 0 +#define VGV2_XFSTYY_F_FMASK 0xffffff +#define VGV2_XFXA_F_FADDR ADDR_VGV2_XFXA +#define VGV2_XFXA_F_FSHIFT 0 +#define VGV2_XFXA_F_FMASK 0xffffff +#define VGV2_XFXX_F_FADDR ADDR_VGV2_XFXX +#define VGV2_XFXX_F_FSHIFT 0 +#define VGV2_XFXX_F_FMASK 0xffffff +#define VGV2_XFXY_F_FADDR ADDR_VGV2_XFXY +#define VGV2_XFXY_F_FSHIFT 0 +#define VGV2_XFXY_F_FMASK 0xffffff +#define VGV2_XFYA_F_FADDR ADDR_VGV2_XFYA +#define VGV2_XFYA_F_FSHIFT 0 +#define VGV2_XFYA_F_FMASK 0xffffff +#define VGV2_XFYX_F_FADDR ADDR_VGV2_XFYX +#define VGV2_XFYX_F_FSHIFT 0 +#define VGV2_XFYX_F_FMASK 0xffffff +#define VGV2_XFYY_F_FADDR ADDR_VGV2_XFYY +#define VGV2_XFYY_F_FSHIFT 0 +#define VGV2_XFYY_F_FMASK 0xffffff +#define VGV3_CONTROL_MARKADD_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_MARKADD_FSHIFT 0 +#define VGV3_CONTROL_MARKADD_FMASK 0xfff +#define VGV3_CONTROL_DMIWAITCHMASK_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_DMIWAITCHMASK_FSHIFT 12 +#define VGV3_CONTROL_DMIWAITCHMASK_FMASK 0xf +#define VGV3_CONTROL_PAUSE_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_PAUSE_FSHIFT 16 +#define VGV3_CONTROL_PAUSE_FMASK 0x1 +#define VGV3_CONTROL_ABORT_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_ABORT_FSHIFT 17 +#define VGV3_CONTROL_ABORT_FMASK 0x1 +#define VGV3_CONTROL_WRITE_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_WRITE_FSHIFT 18 +#define VGV3_CONTROL_WRITE_FMASK 0x1 +#define VGV3_CONTROL_BCFLUSH_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_BCFLUSH_FSHIFT 19 +#define VGV3_CONTROL_BCFLUSH_FMASK 0x1 +#define VGV3_CONTROL_V0SYNC_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_V0SYNC_FSHIFT 20 +#define VGV3_CONTROL_V0SYNC_FMASK 0x1 +#define VGV3_CONTROL_DMIWAITBUF_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_DMIWAITBUF_FSHIFT 21 +#define VGV3_CONTROL_DMIWAITBUF_FMASK 0x7 +#define VGV3_FIRST_DUMMY_FADDR ADDR_VGV3_FIRST +#define VGV3_FIRST_DUMMY_FSHIFT 0 +#define VGV3_FIRST_DUMMY_FMASK 0x1 +#define VGV3_LAST_DUMMY_FADDR ADDR_VGV3_LAST +#define VGV3_LAST_DUMMY_FSHIFT 0 +#define VGV3_LAST_DUMMY_FMASK 0x1 +#define VGV3_MODE_FLIPENDIAN_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_FLIPENDIAN_FSHIFT 0 +#define VGV3_MODE_FLIPENDIAN_FMASK 0x1 +#define VGV3_MODE_UNUSED_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_UNUSED_FSHIFT 1 +#define VGV3_MODE_UNUSED_FMASK 0x1 +#define VGV3_MODE_WRITEFLUSH_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_WRITEFLUSH_FSHIFT 2 +#define VGV3_MODE_WRITEFLUSH_FMASK 0x1 +#define VGV3_MODE_DMIPAUSETYPE_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_DMIPAUSETYPE_FSHIFT 3 +#define VGV3_MODE_DMIPAUSETYPE_FMASK 0x1 +#define VGV3_MODE_DMIRESET_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_DMIRESET_FSHIFT 4 +#define VGV3_MODE_DMIRESET_FMASK 0x1 +#define VGV3_NEXTADDR_CALLADDR_FADDR ADDR_VGV3_NEXTADDR +#define VGV3_NEXTADDR_CALLADDR_FSHIFT 0 +#define VGV3_NEXTADDR_CALLADDR_FMASK 0xffffffff +#define VGV3_NEXTCMD_COUNT_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_COUNT_FSHIFT 0 +#define VGV3_NEXTCMD_COUNT_FMASK 0xfff +#define VGV3_NEXTCMD_NEXTCMD_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_NEXTCMD_FSHIFT 12 +#define VGV3_NEXTCMD_NEXTCMD_FMASK 0x7 +#define VGV3_NEXTCMD_MARK_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_MARK_FSHIFT 15 +#define VGV3_NEXTCMD_MARK_FMASK 0x1 +#define VGV3_NEXTCMD_CALLCOUNT_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_CALLCOUNT_FSHIFT 16 +#define VGV3_NEXTCMD_CALLCOUNT_FMASK 0xfff +#define VGV3_VGBYPASS_BYPASS_FADDR ADDR_VGV3_VGBYPASS +#define VGV3_VGBYPASS_BYPASS_FSHIFT 0 +#define VGV3_VGBYPASS_BYPASS_FMASK 0x1 +#define VGV3_WRITE_VALUE_FADDR ADDR_VGV3_WRITE +#define VGV3_WRITE_VALUE_FSHIFT 0 +#define VGV3_WRITE_VALUE_FMASK 0xffffffff +#define VGV3_WRITEADDR_ADDR_FADDR ADDR_VGV3_WRITEADDR +#define VGV3_WRITEADDR_ADDR_FSHIFT 0 +#define VGV3_WRITEADDR_ADDR_FMASK 0xffffffff +#define VGV3_WRITEDMI_CHANMASK_FADDR ADDR_VGV3_WRITEDMI +#define VGV3_WRITEDMI_CHANMASK_FSHIFT 0 +#define VGV3_WRITEDMI_CHANMASK_FMASK 0xf +#define VGV3_WRITEDMI_BUFFER_FADDR ADDR_VGV3_WRITEDMI +#define VGV3_WRITEDMI_BUFFER_FSHIFT 4 +#define VGV3_WRITEDMI_BUFFER_FMASK 0x7 +#define VGV3_WRITEF32_ADDR_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_ADDR_FSHIFT 0 +#define VGV3_WRITEF32_ADDR_FMASK 0xff +#define VGV3_WRITEF32_COUNT_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_COUNT_FSHIFT 8 +#define VGV3_WRITEF32_COUNT_FMASK 0xff +#define VGV3_WRITEF32_LOOP_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_LOOP_FSHIFT 16 +#define VGV3_WRITEF32_LOOP_FMASK 0xf +#define VGV3_WRITEF32_ACTION_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_ACTION_FSHIFT 20 +#define VGV3_WRITEF32_ACTION_FMASK 0xf +#define VGV3_WRITEF32_FORMAT_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_FORMAT_FSHIFT 24 +#define VGV3_WRITEF32_FORMAT_FMASK 0x7 +#define VGV3_WRITEIFPAUSED_VALUE_FADDR ADDR_VGV3_WRITEIFPAUSED +#define VGV3_WRITEIFPAUSED_VALUE_FSHIFT 0 +#define VGV3_WRITEIFPAUSED_VALUE_FMASK 0xffffffff +#define VGV3_WRITERAW_ADDR_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_ADDR_FSHIFT 0 +#define VGV3_WRITERAW_ADDR_FMASK 0xff +#define VGV3_WRITERAW_COUNT_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_COUNT_FSHIFT 8 +#define VGV3_WRITERAW_COUNT_FMASK 0xff +#define VGV3_WRITERAW_LOOP_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_LOOP_FSHIFT 16 +#define VGV3_WRITERAW_LOOP_FMASK 0xf +#define VGV3_WRITERAW_ACTION_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_ACTION_FSHIFT 20 +#define VGV3_WRITERAW_ACTION_FMASK 0xf +#define VGV3_WRITERAW_FORMAT_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_FORMAT_FSHIFT 24 +#define VGV3_WRITERAW_FORMAT_FMASK 0x7 +#define VGV3_WRITES16_ADDR_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_ADDR_FSHIFT 0 +#define VGV3_WRITES16_ADDR_FMASK 0xff +#define VGV3_WRITES16_COUNT_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_COUNT_FSHIFT 8 +#define VGV3_WRITES16_COUNT_FMASK 0xff +#define VGV3_WRITES16_LOOP_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_LOOP_FSHIFT 16 +#define VGV3_WRITES16_LOOP_FMASK 0xf +#define VGV3_WRITES16_ACTION_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_ACTION_FSHIFT 20 +#define VGV3_WRITES16_ACTION_FMASK 0xf +#define VGV3_WRITES16_FORMAT_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_FORMAT_FSHIFT 24 +#define VGV3_WRITES16_FORMAT_FMASK 0x7 +#define VGV3_WRITES32_ADDR_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_ADDR_FSHIFT 0 +#define VGV3_WRITES32_ADDR_FMASK 0xff +#define VGV3_WRITES32_COUNT_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_COUNT_FSHIFT 8 +#define VGV3_WRITES32_COUNT_FMASK 0xff +#define VGV3_WRITES32_LOOP_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_LOOP_FSHIFT 16 +#define VGV3_WRITES32_LOOP_FMASK 0xf +#define VGV3_WRITES32_ACTION_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_ACTION_FSHIFT 20 +#define VGV3_WRITES32_ACTION_FMASK 0xf +#define VGV3_WRITES32_FORMAT_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_FORMAT_FSHIFT 24 +#define VGV3_WRITES32_FORMAT_FMASK 0x7 +#define VGV3_WRITES8_ADDR_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_ADDR_FSHIFT 0 +#define VGV3_WRITES8_ADDR_FMASK 0xff +#define VGV3_WRITES8_COUNT_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_COUNT_FSHIFT 8 +#define VGV3_WRITES8_COUNT_FMASK 0xff +#define VGV3_WRITES8_LOOP_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_LOOP_FSHIFT 16 +#define VGV3_WRITES8_LOOP_FMASK 0xf +#define VGV3_WRITES8_ACTION_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_ACTION_FSHIFT 20 +#define VGV3_WRITES8_ACTION_FMASK 0xf +#define VGV3_WRITES8_FORMAT_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_FORMAT_FSHIFT 24 +#define VGV3_WRITES8_FORMAT_FMASK 0x7 +typedef struct { + unsigned RS[256]; + unsigned GRADW[2][40]; +} regstate_t; + +#define GRADW_WINDOW_START 0xc0 +#define GRADW_WINDOW_LEN 0x28 +#define GRADW_WINDOW_NUM 0x2 + +static unsigned __inline __getwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + return (RS->GRADW[win][addr-0xc0] >> + shift) & mask; + } + return ((RS->RS[addr] >> shift) & mask); +} + +static void __inline __setwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & + ~(mask << shift)) | + ((mask & data) << shift); + } + RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift); +} + +static void __inline __setwreg__(regstate_t* RS, unsigned win, unsigned addr, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = data; + } + RS->RS[addr] = data; +} + +static unsigned __inline __getrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask) { + return ((RS->RS[addr] >> shift) & mask); +} + +static void __inline __setrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK); + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & + ~(mask << shift)) | ((mask & data) << shift); + } + RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift); +} + +static void __inline __setreg__(regstate_t* RS, unsigned addr, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK); + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = data; + } + RS->RS[addr] = data; +} + +#define SETWRS(win, id, value) __setwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK, value) +#define GETWRS(win, id) __getwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK) +#define SETWREG(win, reg, data) __setwreg__(&RS, win, reg, data) +#define SETRS(id, value) __setrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK, value) +#define GETRS(id) __getrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK) +#define SETREG(reg, data) __setreg__(&RS, reg, data) +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato.h b/drivers/mxc/amd-gpu/include/reg/yamato.h new file mode 100644 index 000000000000..05cae6c46403 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato.h @@ -0,0 +1,66 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _YAMATO_H +#define _YAMATO_H + +#ifndef qLittleEndian +#define qLittleEndian +#endif + +#if defined(_YDX14) +#if defined(_WIN32) && !defined(__SYMBIAN32__) +#pragma message("YDX 14 header files\r\n") +#endif +#include "yamato/14/yamato_enum.h" +#include "yamato/14/yamato_ipt.h" +#include "yamato/14/yamato_mask.h" +#include "yamato/14/yamato_offset.h" +#include "yamato/14/yamato_registers.h" +#include "yamato/14/yamato_shift.h" +#include "yamato/14/yamato_struct.h" +#include "yamato/14/yamato_typedef.h" +#define _YAMATO_GENENUM_H "reg/yamato/14/yamato_genenum.h" +#define _YAMATO_GENREG_H "reg/yamato/14/yamato_genreg.h" +#else +#if defined(_WIN32) && !defined(__SYMBIAN32__) +#pragma message("YDX 22 header files\r\n") +#endif +#include "yamato/22/yamato_enum.h" +#include "yamato/22/yamato_ipt.h" +#include "yamato/22/yamato_mask.h" +#include "yamato/22/yamato_offset.h" +#include "yamato/22/yamato_registers.h" +#include "yamato/22/yamato_shift.h" +#include "yamato/22/yamato_struct.h" +#include "yamato/22/yamato_typedef.h" +#define _YAMATO_GENENUM_H "reg/yamato/22/yamato_genenum.h" +#define _YAMATO_GENREG_H "reg/yamato/22/yamato_genreg.h" +#endif + +#endif // _YAMATO_H diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h new file mode 100644 index 000000000000..144e9151fd8a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h @@ -0,0 +1,1895 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, + PERF_PAPC_SU_FACENESS_CULL = 102, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +typedef enum VGT_DI_FACENESS_CULL_SELECT { + DI_FACE_CULL_NONE = 0, + DI_FACE_CULL_FETCH = 1, + DI_FACE_BACKFACE_CULL = 2, + DI_FACE_FRONTFACE_CULL = 3 +} VGT_DI_FACENESS_CULL_SELECT; +#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, + FACENESS_FLUSH = 28, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + BIN_PRIM_FACE_CULL = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_PERFCOUNT_VTX_POP_THREAD = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_PERFCOUNT_PIX_POP_THREAD = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, + SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_TOTAL_WRITE_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_TOTAL_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, + ELAPSED_CLK_CYCLES = 164, + CP_W_16B_REQUESTS = 165, + CP_W_32B_REQUESTS = 166, + TC_16B_REQUESTS = 167, + TC_32B_REQUESTS = 168, + PA_REQUESTS = 169, + PA_DATA_BYTES_WRITTEN = 170, + PA_WRITE_CLEAN_RESPONSES = 171, + PA_CYCLES_HELD_OFF = 172, + AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, + AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, + AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, + AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, + AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, + AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, + AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, + AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, + AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h new file mode 100644 index 000000000000..87a454a1e38a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h @@ -0,0 +1,1703 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) + GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + GENERATE_ENUM(DI_FACE_CULL_NONE, 0) + GENERATE_ENUM(DI_FACE_CULL_FETCH, 1) + GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2) + GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3) +END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) + GENERATE_ENUM(FACENESS_FLUSH, 28) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_TOTAL_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) + GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164) + GENERATE_ENUM(CP_W_16B_REQUESTS, 165) + GENERATE_ENUM(CP_W_32B_REQUESTS, 166) + GENERATE_ENUM(TC_16B_REQUESTS, 167) + GENERATE_ENUM(TC_32B_REQUESTS, 168) + GENERATE_ENUM(PA_REQUESTS, 169) + GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170) + GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171) + GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180) + GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h new file mode 100644 index 000000000000..f7efe31bc8a8 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h @@ -0,0 +1,3404 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(PERFCOUNTER_REF, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(W_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(CLIP_DISABLE, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(ECO_SPARE0, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE0, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE3, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(QUANT_MODE, QuantMode) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(PIX_CENTER, PixCenter) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(WIDTH, fixed12_4) + GENERATE_FIELD(HEIGHT, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MAX_SIZE, fixed12_4) + GENERATE_FIELD(MIN_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_FACE_DATA) + GENERATE_FIELD(BASE_ADDR, int) +END_REGISTER(PA_SU_FACE_DATA) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(FACE_WRITE_ENABLE, bool) + GENERATE_FIELD(FACE_KILL_ENABLE, bool) + GENERATE_FIELD(ZERO_AREA_FACENESS, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(CULL_FRONT, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(LINE_PATTERN, hex) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(LAST_PIXEL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(BRES_CNTL, int) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(TL_X, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_Y, int) + GENERATE_FIELD(BR_X, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(TL_X, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_Y, int) + GENERATE_FIELD(BR_X, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_COUNT, int) + GENERATE_FIELD(CURRENT_PTR, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(NUM_INDICES, uint) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(FACENESS_RESET, int) + GENERATE_FIELD(FACENESS_FETCH, int) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(GUARD_BAND, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(COLUMN, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(GUARD_BAND, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(COLUMN, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(DST_STATE_ID, int) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(L2_INVALIDATE, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(SPARE, hex) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TC_BUSY_EXTEND, int) + GENERATE_FIELD(TP_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_INPUT_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(SQ_TP_WAKEUP, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(LOD_CNTL, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(BLEND_PRECISION, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_BUSY, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_INPUT_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(Q_LOD_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(TT_MODE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(tca_rts, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_MH_TC_rtr, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(FW_tpc_rts, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(tp0_full, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(capture_tca_rts, int) + GENERATE_FIELD(captue_state_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(sector_format512, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(access512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(valid_left_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(left_done, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(setquads_to_send, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(quad_sel_left, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(arb_RTR, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc0_arb_rts, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(ipbuf_busy, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(empty, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_pstate, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(dcmp_mux_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(pstate, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_dxt2_4_types, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(n0_stall, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_incoming_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_sg_crd_RTR, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_sector_format, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(TCO_TCB_read_xfc, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(fifo_busy, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_SIZE_VTX, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_DYNAMIC, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_VTX, int) + GENERATE_FIELD(INST_BASE_PIX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_TSTATE_RT, int) + GENERATE_FIELD(EO_CONSTANTS_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_ALUCST_SIZE, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(TIMEBASE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_VS_WATCHDOG_TIMER) + GENERATE_FIELD(TIMEOUT_COUNT, int) + GENERATE_FIELD(ENABLE, int) +END_REGISTER(SQ_VS_WATCHDOG_TIMER) + +START_REGISTER(SQ_PS_WATCHDOG_TIMER) + GENERATE_FIELD(TIMEOUT_COUNT, int) + GENERATE_FIELD(ENABLE, int) +END_REGISTER(SQ_PS_WATCHDOG_TIMER) + +START_REGISTER(SQ_INT_CNTL) + GENERATE_FIELD(VS_WATCHDOG_MASK, int) + GENERATE_FIELD(PS_WATCHDOG_MASK, int) +END_REGISTER(SQ_INT_CNTL) + +START_REGISTER(SQ_INT_STATUS) + GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int) + GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int) +END_REGISTER(SQ_INT_STATUS) + +START_REGISTER(SQ_INT_ACK) + GENERATE_FIELD(VS_WATCHDOG_ACK, int) + GENERATE_FIELD(PS_WATCHDOG_ACK, int) +END_REGISTER(SQ_INT_ACK) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(PC_GPR_SIZE, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_VSR_LD, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(ARB_TR_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(ARB_TR_ALU, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_ALU_0, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(ARB_TR_ALU, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_ALU_0, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(POS_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(VTX_SYNC_CNT, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(END_OF_BUFFER, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_FREE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_TAIL_PTR, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_FREE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_TAIL_PTR, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(BUSY_Q, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(BUSY, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(SCALAR_DST_REL, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier) + GENERATE_FIELD(VECTOR_RESULT, int) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(CONST_0_REL_ABS, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(SRC_C_REG_PTR, int) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(LOOP_ID, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_2, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(OPCODE, TexInstOpcode) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(PRED_SELECT, PredSelect) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_X, DstSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(PRED_CONDITION, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(USE_REG_GRADIENTS, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(SRC_SEL, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(OPCODE, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(PRED_SELECT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_X, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(PRED_CONDITION, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(STRIDE, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(BASE_ADDRESS, hex) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(TYPE, int) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(LIMIT_ADDRESS, hex) + GENERATE_FIELD(ENDIAN_SWAP, int) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_3, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_0, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_STEP, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_COUNT, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_3, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_0, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_STEP, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_COUNT, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(PS_CF_SIZE, int) + GENERATE_FIELD(VS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) + GENERATE_FIELD(PARAM_SHADE, ParamShade) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(GEN_INDEX_VTX, int) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_7, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_0, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_15, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_8, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(TX_CACHE_SEL, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_COUNT, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ON, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_BREAK_ADDR, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_ON_PIX, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(PA_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(PAw_ID, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(MMUr_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(CPw_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(AXI_READ_ERROR, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(MMU_PAGE_FAULT, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_READ_ERROR, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(MMU_PAGE_FAULT, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_READ_ERROR, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_READ_ID, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_AXI_HALT_CONTROL) + GENERATE_FIELD(AXI_HALT, bool) +END_REGISTER(MH_AXI_HALT_CONTROL) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(MMU_ENABLE, bool) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(VA_BASE, int) + GENERATE_FIELD(NUM_64KB_REGIONS, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(REQ_VA, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(PAGE_FAULT, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_TC, int) + GENERATE_FIELD(INVALIDATE_ALL, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_RE_VSYNC, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(GUI_ACTIVE, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(CMDFIFO_AVAIL, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(DMI_CH4_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH4_SW_CNTL, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH3_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH3_SW_CNTL, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID0, int) + GENERATE_FIELD(DMI_CHANNEL_SELECT, int) + GENERATE_FIELD(DMI_CH2_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH2_SW_CNTL, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH1_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH1_SW_CNTL, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID0, int) + GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(DMI_CH4_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH3_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH2_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH1_BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(CUSTOMER_ID, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(PATCH_REVISION, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(DESIGNER0, int) + GENERATE_FIELD(PARTNUMBER1, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(REVISION, int) + GENERATE_FIELD(DESIGNER1, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(CONTINUATION, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) + GENERATE_FIELD(READ_TIMEOUT, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_COUNT, int) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_VGT, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_CP, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG_OUT) + GENERATE_FIELD(DEBUG_BUS_OUT, int) +END_REGISTER(RBBM_DEBUG_OUT) + +START_REGISTER(RBBM_DEBUG_CNTL) + GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int) + GENERATE_FIELD(SW_ENABLE, int) + GENERATE_FIELD(SUB_BLOCK_SEL, int) + GENERATE_FIELD(SUB_BLOCK_ADDR, int) +END_REGISTER(RBBM_DEBUG_CNTL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_RTR, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ERROR, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ADDRESS, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(RDERR_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(RDERR_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(RDERR_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(RBBM_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(SQ_INT_STAT, int) + GENERATE_FIELD(MH_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(RB_BUFSZ, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_ADDR, int) + GENERATE_FIELD(RB_RPTR_SWAP, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) + GENERATE_FIELD(PRE_WRITE_TIMER, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_BASE, int) + GENERATE_FIELD(RB_WPTR_SWAP, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_ST_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_IB1_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(ROQ_END, int) + GENERATE_FIELD(MEQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_IB2, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_RING, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB2_COUNTER, int) + GENERATE_FIELD(IB1_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_WPTR_ST, int) + GENERATE_FIELD(STQ_RPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_WPTR, int) + GENERATE_FIELD(MEQ_RPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(INVALID_RETURN_TAG, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_0_STAT, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_QUEUE_SEL, int) + GENERATE_FIELD(CMD_INDEX, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(PROG_CNT_SIZE, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_STATMUX, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_SWAP, int) + GENERATE_FIELD(SCRATCH_UMSK, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_CNTR, int) + GENERATE_FIELD(VS_DONE_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_ADDR, int) + GENERATE_FIELD(VS_DONE_SWAP, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_CNTR, int) + GENERATE_FIELD(PS_DONE_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_ADDR, int) + GENERATE_FIELD(PS_DONE_SWAP, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_ADDR, int) + GENERATE_FIELD(CF_DONE_SWAP, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_ADDR, int) + GENERATE_FIELD(NRT_WRITE_SWAP, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(RB_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(SW_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(RB_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(SW_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(RB_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(SW_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) + GENERATE_FIELD(PERFMON_STATE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(END_RCVD_15, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_0, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(END_RCVD_31, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_16, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(END_RCVD_47, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_32, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(END_RCVD_63, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_48, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(CP_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_WR_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(STATUS, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(MATCHING_CONTEXTS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(STATUS, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(MATCHING_CONTEXTS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) + GENERATE_FIELD(SURFACE_PITCH, uint) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_BASE, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_BASE, uint) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(RESERVED1, bool) + GENERATE_FIELD(RESERVED0, bool) + GENERATE_FIELD(STENCILWRITEMASK, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILREF, hex) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(RESERVED3, bool) + GENERATE_FIELD(RESERVED2, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_RED, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_BLUE, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_RED, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(RESERVED5, bool) + GENERATE_FIELD(RESERVED4, bool) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILREF_BF, hex) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(STENCIL_ENABLE, bool) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(BLEND_FORCE, bool) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(CLEAR_MASK, uint) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_Y, uint) + GENERATE_FIELD(OFFSET_X, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(RESERVED6, bool) + GENERATE_FIELD(CRC_SYSTEM, bool) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_RANGE, hex) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(Z_TILE_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_VALID, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(RB_BC_SPARES) + GENERATE_FIELD(RESERVED, bool) +END_REGISTER(RB_BC_SPARES) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h new file mode 100644 index 000000000000..c3087908c541 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h @@ -0,0 +1,5906 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR_MASK 0xffffffe0L + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK 0x20000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS 0x20000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK 0x80000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE 0x80000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fposition_MASK 0x00000010L +#define SC_DEBUG_7__fposition 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fposition_MASK 0x00100000L +#define SC_DEBUG_8__fposition 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK 0x00000300L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_BIN_SIZE__FACENESS_FETCH_MASK 0x40000000L +#define VGT_BIN_SIZE__FACENESS_FETCH 0x40000000L +#define VGT_BIN_SIZE__FACENESS_RESET_MASK 0x80000000L +#define VGT_BIN_SIZE__FACENESS_RESET 0x80000000L + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK 0x00000001L +#define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK 0x00000002L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK 0x00000001L +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT 0x00000001L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK 0x00000002L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT 0x00000002L + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK 0x00000001L +#define SQ_INT_ACK__PS_WATCHDOG_ACK 0x00000001L +#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK 0x00000002L +#define SQ_INT_ACK__VS_WATCHDOG_ACK 0x00000002L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK 0x04000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE 0x04000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK 0x00007000L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK 0x00000001L +#define MH_AXI_HALT_CONTROL__AXI_HALT 0x00000001L + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__PA_REQUEST_MASK 0x00000400L +#define MH_DEBUG_REG00__PA_REQUEST 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000800L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00002000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00008000L +#define MH_DEBUG_REG00__WDB_FULL 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BVALID 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x08000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x08000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK 0x10000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA 0x10000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG01__CP_BLEN_q 0x00000040L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00000080L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00000080L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00000100L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00000100L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00000200L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00000200L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG01__TC_SEND_q 0x00000400L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG01__TC_RTR_q 0x00000800L +#define MH_DEBUG_REG01__TC_BLEN_q_MASK 0x00001000L +#define MH_DEBUG_REG01__TC_BLEN_q 0x00001000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00004000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00008000L +#define MH_DEBUG_REG01__TC_MH_written 0x00008000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00010000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00010000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00020000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00020000L +#define MH_DEBUG_REG01__PA_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG01__PA_SEND_q 0x00040000L +#define MH_DEBUG_REG01__PA_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG01__PA_RTR_q 0x00080000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__MH_PA_writeclean_MASK 0x00004000L +#define MH_DEBUG_REG02__MH_PA_writeclean 0x00004000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x00038000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x000c0000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be_MASK 0x000000ffL +#define MH_DEBUG_REG08__RB_MH_be_MASK 0x0000ff00L +#define MH_DEBUG_REG08__PA_MH_be_MASK 0x00ff0000L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG09__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG10__TC_MH_send 0x00000004L +#define MH_DEBUG_REG10__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG11__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG11__TC_MH_send 0x02000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG12__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG12__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG12__TC_MH_written 0x04000000L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG14__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG15__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG15__RB_MH_send 0x00000010L +#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG18__PA_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG18__PA_MH_send 0x00000010L +#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG21__AVALID_q 0x00000001L +#define MH_DEBUG_REG21__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG21__AREADY_q 0x00000002L +#define MH_DEBUG_REG21__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG21__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG21__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG21__ARVALID_q 0x00000100L +#define MH_DEBUG_REG21__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG21__ARREADY_q 0x00000200L +#define MH_DEBUG_REG21__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG21__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG21__RVALID_q 0x00008000L +#define MH_DEBUG_REG21__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG21__RREADY_q 0x00010000L +#define MH_DEBUG_REG21__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG21__RLAST_q 0x00020000L +#define MH_DEBUG_REG21__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG21__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG21__WVALID_q 0x00200000L +#define MH_DEBUG_REG21__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG21__WREADY_q 0x00400000L +#define MH_DEBUG_REG21__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG21__WLAST_q 0x00800000L +#define MH_DEBUG_REG21__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG21__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG21__BVALID_q 0x08000000L +#define MH_DEBUG_REG21__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG21__BREADY_q 0x10000000L +#define MH_DEBUG_REG21__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG22__AVALID_q 0x00000001L +#define MH_DEBUG_REG22__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG22__AREADY_q 0x00000002L +#define MH_DEBUG_REG22__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG22__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG22__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG22__ARVALID_q 0x00000080L +#define MH_DEBUG_REG22__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG22__ARREADY_q 0x00000100L +#define MH_DEBUG_REG22__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG22__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG22__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG22__WVALID_q 0x00002000L +#define MH_DEBUG_REG22__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG22__WREADY_q 0x00004000L +#define MH_DEBUG_REG22__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG22__WLAST_q 0x00008000L +#define MH_DEBUG_REG22__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG22__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG22__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG22__BVALID_q 0x08000000L +#define MH_DEBUG_REG22__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG22__BREADY_q 0x10000000L +#define MH_DEBUG_REG22__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG23__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG24__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG24__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG24__REG_RE 0x00010000L +#define MH_DEBUG_REG24__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG24__REG_WE 0x00020000L +#define MH_DEBUG_REG24__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG24__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy_MASK 0x00000001L +#define MH_DEBUG_REG26__MH_RBBM_busy 0x00000001L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int 0x00000008L +#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK 0x00000010L +#define MH_DEBUG_REG26__GAT_CLK_ENA 0x00000010L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK 0x00000020L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override 0x00000020L +#define MH_DEBUG_REG26__CNT_q_MASK 0x00000fc0L +#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK 0x00001000L +#define MH_DEBUG_REG26__TCD_EMPTY_q 0x00001000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY 0x00002000L +#define MH_DEBUG_REG26__MH_BUSY_d_MASK 0x00004000L +#define MH_DEBUG_REG26__MH_BUSY_d 0x00004000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK 0x00008000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY 0x00008000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC 0x00020000L +#define MH_DEBUG_REG26__CP_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG26__CP_SEND_q 0x00040000L +#define MH_DEBUG_REG26__CP_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG26__CP_RTR_q 0x00080000L +#define MH_DEBUG_REG26__VGT_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG26__VGT_SEND_q 0x00100000L +#define MH_DEBUG_REG26__VGT_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG26__VGT_RTR_q 0x00200000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00800000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00800000L +#define MH_DEBUG_REG26__RB_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG26__RB_SEND_q 0x01000000L +#define MH_DEBUG_REG26__RB_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG26__RB_RTR_q 0x02000000L +#define MH_DEBUG_REG26__PA_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG26__PA_SEND_q 0x04000000L +#define MH_DEBUG_REG26__PA_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG26__PA_RTR_q 0x08000000L +#define MH_DEBUG_REG26__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG26__RDC_VALID 0x10000000L +#define MH_DEBUG_REG26__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG26__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG26__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG26__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG26__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG26__BRC_VALID 0x80000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG27__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG27__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG27__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG27__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG27__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG27__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG27__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG27__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG27__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG27__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG27__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG27__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG27__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG27__PA_SEND_QUAL 0x01000000L +#define MH_DEBUG_REG27__ARB_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG27__ARB_QUAL 0x02000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK 0x20000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ 0x20000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG28__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG28__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG28__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG28__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG28__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG28__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG28__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG28__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG28__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG28__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG28__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG28__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG28__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG28__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG28__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG28__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG28__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK 0x00000038L +#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK 0x000001c0L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK 0x00000200L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d 0x00000200L +#define MH_DEBUG_REG29__ARB_HOLD_MASK 0x00000400L +#define MH_DEBUG_REG29__ARB_HOLD 0x00000400L +#define MH_DEBUG_REG29__ARB_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG29__ARB_RTR_q 0x00000800L +#define MH_DEBUG_REG29__CLNT_REQ_MASK 0x0001f000L +#define MH_DEBUG_REG29__RECENT_d_0_MASK 0x000e0000L +#define MH_DEBUG_REG29__RECENT_d_1_MASK 0x00700000L +#define MH_DEBUG_REG29__RECENT_d_2_MASK 0x03800000L +#define MH_DEBUG_REG29__RECENT_d_3_MASK 0x1c000000L +#define MH_DEBUG_REG29__RECENT_d_4_MASK 0xe0000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG30__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG30__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG30__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG30__TC_MH_written 0x00000800L +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG30__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG30__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG30__WLAST_q 0x00100000L +#define MH_DEBUG_REG30__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG30__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG30__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG30__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG30__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG30__CP_MH_write 0x04000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK 0x10000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL 0x10000000L +#define MH_DEBUG_REG30__ARB_WINNER_MASK 0xe0000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG32__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG32__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG32__TC_MH_send 0x01000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG32__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG32__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG33__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG33__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG33__TC_MH_send 0x01000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG33__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG33__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG39__TC_MH_send 0x00000001L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG39__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG39__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG40__TC_MH_send 0x00000001L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG40__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG40__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG41__TC_MH_send 0x00000001L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG41__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG41__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG42__TC_MH_send 0x00000001L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG42__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG42__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG43__ARB_REG_WE_q 0x00000001L +#define MH_DEBUG_REG43__ARB_WE_MASK 0x00000002L +#define MH_DEBUG_REG43__ARB_WE 0x00000002L +#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG43__ARB_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG43__ARB_RTR_q_MASK 0x00000008L +#define MH_DEBUG_REG43__ARB_RTR_q 0x00000008L +#define MH_DEBUG_REG43__ARB_REG_RTR_MASK 0x00000010L +#define MH_DEBUG_REG43__ARB_REG_RTR 0x00000010L +#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK 0x00000020L +#define MH_DEBUG_REG43__WDAT_BURST_RTR 0x00000020L +#define MH_DEBUG_REG43__MMU_RTR_MASK 0x00000040L +#define MH_DEBUG_REG43__MMU_RTR 0x00000040L +#define MH_DEBUG_REG43__ARB_ID_q_MASK 0x00000380L +#define MH_DEBUG_REG43__ARB_WRITE_q_MASK 0x00000400L +#define MH_DEBUG_REG43__ARB_WRITE_q 0x00000400L +#define MH_DEBUG_REG43__ARB_BLEN_q_MASK 0x00000800L +#define MH_DEBUG_REG43__ARB_BLEN_q 0x00000800L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY 0x00001000L +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK 0x0000e000L +#define MH_DEBUG_REG43__MMU_WE_MASK 0x00010000L +#define MH_DEBUG_REG43__MMU_WE 0x00010000L +#define MH_DEBUG_REG43__ARQ_RTR_MASK 0x00020000L +#define MH_DEBUG_REG43__ARQ_RTR 0x00020000L +#define MH_DEBUG_REG43__MMU_ID_MASK 0x001c0000L +#define MH_DEBUG_REG43__MMU_WRITE_MASK 0x00200000L +#define MH_DEBUG_REG43__MMU_WRITE 0x00200000L +#define MH_DEBUG_REG43__MMU_BLEN_MASK 0x00400000L +#define MH_DEBUG_REG43__MMU_BLEN 0x00400000L +#define MH_DEBUG_REG43__WBURST_IP_q_MASK 0x00800000L +#define MH_DEBUG_REG43__WBURST_IP_q 0x00800000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK 0x01000000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q 0x01000000L +#define MH_DEBUG_REG43__WDB_WE_MASK 0x02000000L +#define MH_DEBUG_REG43__WDB_WE 0x02000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK 0x08000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3 0x08000000L + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG44__ARB_WE 0x00000001L +#define MH_DEBUG_REG44__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG44__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG45__MMU_WE 0x00000001L +#define MH_DEBUG_REG45__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG45__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG46__WDAT_REG_WE_q 0x00000001L +#define MH_DEBUG_REG46__WDB_WE_MASK 0x00000002L +#define MH_DEBUG_REG46__WDB_WE 0x00000002L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK 0x00000008L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4 0x00000008L +#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK 0x00000ff0L +#define MH_DEBUG_REG46__ARB_WLAST_MASK 0x00001000L +#define MH_DEBUG_REG46__ARB_WLAST 0x00001000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY 0x00002000L +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK 0x0007c000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK 0x00080000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q 0x00080000L +#define MH_DEBUG_REG46__WDB_WDC_WID_MASK 0x00700000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK 0xff000000L + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG49__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG49__RVALID_q 0x00008000L +#define MH_DEBUG_REG49__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG49__RREADY_q 0x00010000L +#define MH_DEBUG_REG49__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG49__RLAST_q 0x00020000L +#define MH_DEBUG_REG49__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG49__BVALID_q 0x00040000L +#define MH_DEBUG_REG49__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG49__BREADY_q 0x00080000L + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG50__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG50__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG50__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG50__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG50__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG50__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG50__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG50__RDC_VALID 0x00000020L +#define MH_DEBUG_REG50__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG50__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG50__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG50__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG50__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003L +#define MH_DEBUG_REG52__ARB_WE_MASK 0x00000004L +#define MH_DEBUG_REG52__ARB_WE 0x00000004L +#define MH_DEBUG_REG52__MMU_RTR_MASK 0x00000008L +#define MH_DEBUG_REG52__MMU_RTR 0x00000008L +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0L +#define MH_DEBUG_REG52__ARB_ID_q_MASK 0x1c000000L +#define MH_DEBUG_REG52__ARB_WRITE_q_MASK 0x20000000L +#define MH_DEBUG_REG52__ARB_WRITE_q 0x20000000L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0xc0000000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG53__stage1_valid 0x00000001L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG53__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG53__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG53__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG53__tag_match_q 0x00000008L +#define MH_DEBUG_REG53__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG53__tag_miss_q 0x00000010L +#define MH_DEBUG_REG53__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG53__va_in_range_q 0x00000020L +#define MH_DEBUG_REG53__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG53__MMU_MISS 0x00000040L +#define MH_DEBUG_REG53__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG53__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG53__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG53__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG53__MMU_HIT 0x00000200L +#define MH_DEBUG_REG53__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG53__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG53__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG54__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG54__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG54__MMU_WE 0x00000002L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG54__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG54__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG54__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG54__stage1_valid 0x00000080L +#define MH_DEBUG_REG54__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG54__stage2_valid 0x00000100L +#define MH_DEBUG_REG54__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG54__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG54__tag_match_q 0x00001000L +#define MH_DEBUG_REG54__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG54__tag_miss_q 0x00002000L +#define MH_DEBUG_REG54__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG54__va_in_range_q 0x00004000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG54__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG61__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG61__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG61__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG61__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG61__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG62__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG62__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG62__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG62__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG62__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK 0x03000000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2 0x00000004L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK 0x00000008L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID 0x00000008L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK 0x00000040L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2 0x00000040L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL 0x00000080L +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK 0x00000300L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK 0x00001000L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2 0x00001000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK 0x00002000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL 0x00002000L +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK 0x0000c000L +#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK 0x00030000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK 0x00400000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2 0x00400000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK 0x00800000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL 0x00800000L +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK 0x03000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK 0x10000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2 0x10000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK 0x20000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL 0x20000000L +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK 0xc0000000L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK 0x00000003L +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK 0x00000300L +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK 0x00030000L +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK 0x03000000L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK 0x01000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP 0x01000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK 0x02000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI 0x02000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE 0x20000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE 0x40000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK 0xffffffffL + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK 0x0000003fL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK 0x00000f00L +#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK 0x00001000L +#define RBBM_DEBUG_CNTL__SW_ENABLE 0x00001000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK 0x0f000000L +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK 0xf0000000L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK 0x04000000L +#define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L +#define RB_STENCILREFMASK__RESERVED0_MASK 0x01000000L +#define RB_STENCILREFMASK__RESERVED0 0x01000000L +#define RB_STENCILREFMASK__RESERVED1_MASK 0x02000000L +#define RB_STENCILREFMASK__RESERVED1 0x02000000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L +#define RB_COLOR_MASK__RESERVED2_MASK 0x00000010L +#define RB_COLOR_MASK__RESERVED2 0x00000010L +#define RB_COLOR_MASK__RESERVED3_MASK 0x00000020L +#define RB_COLOR_MASK__RESERVED3 0x00000020L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L +#define RB_STENCILREFMASK_BF__RESERVED4_MASK 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED4 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED5_MASK 0x02000000L +#define RB_STENCILREFMASK_BF__RESERVED5 0x02000000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__CRC_SYSTEM_MASK 0x40000000L +#define RB_BC_CONTROL__CRC_SYSTEM 0x40000000L +#define RB_BC_CONTROL__RESERVED6_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED6 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED_MASK 0xffffffffL + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h new file mode 100644 index 000000000000..ec7c7e126612 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h @@ -0,0 +1,590 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_FACE_DATA 0x0C86 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_VS_WATCHDOG_TIMER 0x0D0A +#define mmSQ_PS_WATCHDOG_TIMER 0x0D0B +#define mmSQ_INT_CNTL 0x0D34 +#define mmSQ_INT_STATUS 0x0D35 +#define mmSQ_INT_ACK 0x0D36 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_AXI_HALT_CONTROL 0x0A50 +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG_OUT 0x03A0 +#define mmRBBM_DEBUG_CNTL 0x03A1 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x0458 +#define mmCP_IB1_BUFSZ 0x0459 +#define mmCP_IB2_BASE 0x045A +#define mmCP_IB2_BUFSZ 0x045B +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x00C0 +#define mmCP_PFP_UCODE_DATA 0x00C1 +#define mmCP_PERFMON_CNTL 0x0444 +#define mmCP_PERFCOUNTER_SELECT 0x0445 +#define mmCP_PERFCOUNTER_LO 0x0446 +#define mmCP_PERFCOUNTER_HI 0x0447 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmRB_BC_SPARES 0x0F2C +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h new file mode 100644 index 000000000000..17379dcfa0e7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h @@ -0,0 +1,223 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h new file mode 100644 index 000000000000..fc6b8b98f849 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h @@ -0,0 +1,14278 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_FACE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int BASE_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 2; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int FACE_WRITE_ENABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACE_WRITE_ENABLE : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int : 2; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fposition : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fposition : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fposition : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fposition : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int : 1; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 1; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int FACENESS_FETCH : 1; + unsigned int FACENESS_RESET : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACENESS_RESET : 1; + unsigned int FACENESS_FETCH : 1; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_MASK : 1; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int PS_WATCHDOG_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_TIMEOUT : 1; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int PS_WATCHDOG_TIMEOUT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_ACK : 1; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int PS_WATCHDOG_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int VECTOR_DST_REL : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SCALAR_DST_REL : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SCALAR_DST_REL : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int VECTOR_DST_REL : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int PAw_ID : 3; + unsigned int : 17; +#else /* !defined(qLittleEndian) */ + unsigned int : 17; + unsigned int PAw_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_HALT_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int AXI_HALT : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int AXI_HALT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int PA_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int AXI_RDY_ENA : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int PA_REQUEST : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BLEN_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BLEN_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_PA_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_PA_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int PA_MH_be : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int PA_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int CP_MH_be : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int PA_MH_send : 1; + unsigned int PA_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_addr_31_5 : 27; + unsigned int PA_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CLNT_REQ : 5; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_4 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_4 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 5; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WINNER : 3; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_REG_WE_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; +#else /* !defined(qLittleEndian) */ + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int : 2; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_NUM_BUFS : 2; +#else /* !defined(qLittleEndian) */ + unsigned int DMI_CH4_NUM_BUFS : 2; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int DMI_CH1_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH1_BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int : 2; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int : 3; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int : 3; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int : 2; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_OUT { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_BUS_OUT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEBUG_BUS_OUT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int SW_ENABLE : 1; + unsigned int : 3; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int GPIO_BYTE_LANE_ENB : 4; +#else /* !defined(qLittleEndian) */ + unsigned int GPIO_BYTE_LANE_ENB : 4; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 3; + unsigned int SW_ENABLE : 1; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int SUB_BLOCK_ADDR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 20; + unsigned int SQ_INT_STAT : 1; + unsigned int : 3; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 3; + unsigned int SQ_INT_STAT : 1; + unsigned int : 20; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int RESERVED0 : 1; + unsigned int RESERVED1 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED1 : 1; + unsigned int RESERVED0 : 1; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int RESERVED2 : 1; + unsigned int RESERVED3 : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int RESERVED3 : 1; + unsigned int RESERVED2 : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int RESERVED4 : 1; + unsigned int RESERVED5 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED5 : 1; + unsigned int RESERVED4 : 1; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int RESERVED6 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED6 : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_SPARES { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h new file mode 100644 index 000000000000..10807b43ea44 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h @@ -0,0 +1,4183 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT 0x00000005 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT 0x0000001d +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT 0x0000001e +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT 0x0000001f + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fposition__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fposition__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT 0x00000008 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT 0x0000001e +#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT 0x0000001f + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT 0x00000000 +#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT 0x00000001 + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT 0x00000000 +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT 0x00000001 + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT 0x00000000 +#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT 0x00000001 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 +#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT 0x0000000b +#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT 0x0000000c + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__PA_REQUEST__SHIFT 0x0000000a +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000e +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001b +#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT 0x0000001c + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x00000007 +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x00000008 +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT 0x0000000c +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x0000000d +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x0000000f +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__PA_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__PA_RTR_q__SHIFT 0x00000013 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000f +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000012 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be__SHIFT 0x00000000 +#define MH_DEBUG_REG08__RB_MH_be__SHIFT 0x00000008 +#define MH_DEBUG_REG08__PA_MH_be__SHIFT 0x00000010 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG10__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG11__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG12__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG15__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG18__PA_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG21__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG21__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG21__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG21__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG21__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG21__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG21__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG21__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG21__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG21__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG21__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG21__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG21__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG21__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG21__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG21__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG22__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG22__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG22__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG22__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG22__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG22__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG22__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG22__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG22__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG22__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG22__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG24__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG24__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG24__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG24__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT 0x00000000 +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT 0x00000001 +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT 0x00000002 +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT 0x00000004 +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT 0x00000005 +#define MH_DEBUG_REG26__CNT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT 0x0000000e +#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT 0x0000000f +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010 +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011 +#define MH_DEBUG_REG26__CP_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG26__CP_RTR_q__SHIFT 0x00000013 +#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000017 +#define MH_DEBUG_REG26__RB_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG26__RB_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG26__PA_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG26__PA_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG26__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG26__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG26__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG27__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG27__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG27__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG27__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG27__ARB_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT 0x0000001d +#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG28__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG28__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG28__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT 0x00000003 +#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT 0x00000006 +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT 0x00000009 +#define MH_DEBUG_REG29__ARB_HOLD__SHIFT 0x0000000a +#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG29__CLNT_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG29__RECENT_d_0__SHIFT 0x00000011 +#define MH_DEBUG_REG29__RECENT_d_1__SHIFT 0x00000014 +#define MH_DEBUG_REG29__RECENT_d_2__SHIFT 0x00000017 +#define MH_DEBUG_REG29__RECENT_d_3__SHIFT 0x0000001a +#define MH_DEBUG_REG29__RECENT_d_4__SHIFT 0x0000001d + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG30__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG30__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG30__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT 0x0000001c +#define MH_DEBUG_REG30__ARB_WINNER__SHIFT 0x0000001d + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG32__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG33__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG43__ARB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT 0x00000003 +#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT 0x00000004 +#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT 0x00000005 +#define MH_DEBUG_REG43__MMU_RTR__SHIFT 0x00000006 +#define MH_DEBUG_REG43__ARB_ID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT 0x0000000a +#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT 0x0000000b +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT 0x0000000d +#define MH_DEBUG_REG43__MMU_WE__SHIFT 0x00000010 +#define MH_DEBUG_REG43__ARQ_RTR__SHIFT 0x00000011 +#define MH_DEBUG_REG43__MMU_ID__SHIFT 0x00000012 +#define MH_DEBUG_REG43__MMU_WRITE__SHIFT 0x00000015 +#define MH_DEBUG_REG43__MMU_BLEN__SHIFT 0x00000016 +#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT 0x00000017 +#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT 0x00000018 +#define MH_DEBUG_REG43__WDB_WE__SHIFT 0x00000019 +#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT 0x0000001a +#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT 0x0000001b + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG44__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG45__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG45__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG46__WDB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT 0x00000003 +#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT 0x00000004 +#define MH_DEBUG_REG46__ARB_WLAST__SHIFT 0x0000000c +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT 0x0000000e +#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT 0x00000013 +#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT 0x00000014 +#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT 0x00000017 +#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT 0x00000018 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG49__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG49__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG49__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG49__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG49__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG50__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG50__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG50__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG50__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT 0x00000000 +#define MH_DEBUG_REG52__ARB_WE__SHIFT 0x00000002 +#define MH_DEBUG_REG52__MMU_RTR__SHIFT 0x00000003 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT 0x00000004 +#define MH_DEBUG_REG52__ARB_ID_q__SHIFT 0x0000001a +#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT 0x0000001d +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x0000001e + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG53__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG53__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG53__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG53__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG53__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG54__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG54__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG54__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG54__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG54__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG54__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG54__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG54__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG61__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG62__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT 0x00000000 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT 0x00000001 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT 0x00000002 +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT 0x00000003 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT 0x00000004 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT 0x00000005 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT 0x00000006 +#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT 0x00000008 +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT 0x0000000a +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT 0x0000000b +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT 0x0000000c +#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT 0x0000000d +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT 0x0000000e +#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT 0x00000010 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT 0x00000014 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT 0x00000015 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT 0x00000016 +#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT 0x00000017 +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT 0x00000018 +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT 0x0000001a +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT 0x0000001b +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT 0x0000001c +#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT 0x0000001d +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT 0x0000001e + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT 0x00000000 +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT 0x00000008 +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT 0x00000010 +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT 0x00000018 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT 0x00000010 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT 0x00000018 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT 0x00000019 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT 0x0000001d +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT 0x0000001e +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT 0x00000000 + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT 0x00000000 +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT 0x00000008 +#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT 0x0000000c +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT 0x00000010 +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT 0x00000018 +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT 0x0000001c + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT 0x0000001a +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 +#define RB_STENCILREFMASK__RESERVED0__SHIFT 0x00000018 +#define RB_STENCILREFMASK__RESERVED1__SHIFT 0x00000019 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 +#define RB_COLOR_MASK__RESERVED2__SHIFT 0x00000004 +#define RB_COLOR_MASK__RESERVED3__SHIFT 0x00000005 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 +#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT 0x00000018 +#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT 0x00000019 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED6__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h new file mode 100644 index 000000000000..d6cc2fe9abdf --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h @@ -0,0 +1,52421 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \ + RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) + +#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \ + ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \ + (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \ + (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \ + (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \ + (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \ + (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \ + (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \ + (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \ + (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \ + (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \ + (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \ + (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \ + (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \ + (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \ + (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \ + (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \ + (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \ + (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \ + (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \ + (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \ + (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \ + (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \ + (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \ + (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \ + (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int : 2; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int : 2; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \ + ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \ + (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \ + (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \ + (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \ + (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \ + (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \ + (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \ + (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int : 2; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int : 3; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int : 3; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int : 2; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG_OUT struct + */ + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff + +#define RBBM_DEBUG_OUT_MASK \ + (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) + +#define RBBM_DEBUG_OUT(debug_bus_out) \ + ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)) + +#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \ + ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \ + rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_out_t f; +} rbbm_debug_out_u; + + +/* + * RBBM_DEBUG_CNTL struct + */ + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00 +#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000 + +#define RBBM_DEBUG_CNTL_MASK \ + (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) + +#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \ + ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \ + (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \ + (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \ + (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \ + (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \ + (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)) + +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int : 3; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + } rbbm_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 3; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + } rbbm_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_cntl_t f; +} rbbm_debug_cntl_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 20; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 3; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 3; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 20; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \ + (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int : 5; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 5; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \ + MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \ + (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \ + (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int : 17; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 17; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_AXI_HALT_CONTROL struct + */ + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001 + +#define MH_AXI_HALT_CONTROL_MASK \ + (MH_AXI_HALT_CONTROL_AXI_HALT_MASK) + +#define MH_AXI_HALT_CONTROL(axi_halt) \ + ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)) + +#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \ + ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \ + mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + unsigned int : 31; + } mh_axi_halt_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int : 31; + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + } mh_axi_halt_control_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_halt_control_t f; +} mh_axi_halt_control_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 13 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00004000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000 +#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_PA_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \ + MH_DEBUG_REG00_AXI_RDY_ENA_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int : 3; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 3; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_PA_RTR_q_SIZE 1 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 11 +#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 17 +#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18 +#define MH_DEBUG_REG01_PA_RTR_q_SHIFT 19 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00000100 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00000200 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG01_TC_BLEN_q_MASK 0x00001000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00010000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00020000 +#define MH_DEBUG_REG01_PA_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG01_PA_RTR_q_MASK 0x00080000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BLEN_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_BLEN_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_PA_SEND_q_MASK | \ + MH_DEBUG_REG01_PA_RTR_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int : 12; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int : 12; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 15 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x00038000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x000c0000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_MH_PA_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 12; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 12; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_CP_MH_be_SIZE 8 +#define MH_DEBUG_REG08_RB_MH_be_SIZE 8 +#define MH_DEBUG_REG08_PA_MH_be_SIZE 8 + +#define MH_DEBUG_REG08_CP_MH_be_SHIFT 0 +#define MH_DEBUG_REG08_RB_MH_be_SHIFT 8 +#define MH_DEBUG_REG08_PA_MH_be_SHIFT 16 + +#define MH_DEBUG_REG08_CP_MH_be_MASK 0x000000ff +#define MH_DEBUG_REG08_RB_MH_be_MASK 0x0000ff00 +#define MH_DEBUG_REG08_PA_MH_be_MASK 0x00ff0000 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_CP_MH_be_MASK | \ + MH_DEBUG_REG08_RB_MH_be_MASK | \ + MH_DEBUG_REG08_PA_MH_be_MASK) + +#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \ + ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \ + (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \ + (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)) + +#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int : 8; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int : 8; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_VGT_MH_send_MASK | \ + MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK | \ + MH_DEBUG_REG10_TC_MH_mask_MASK | \ + MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG11_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_TC_MH_info_MASK | \ + MH_DEBUG_REG11_TC_MH_send_MASK) + +#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG12_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG12_TC_MH_written_MASK) + +#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG14_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG15_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG15_RB_MH_send_MASK | \ + MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG17(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG18_PA_MH_send_SIZE 1 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG18_PA_MH_send_MASK | \ + MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \ + (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \ + (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_PA_MH_data_31_0_MASK) + +#define MH_DEBUG_REG19(pa_mh_data_31_0) \ + ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_PA_MH_data_63_32_MASK) + +#define MH_DEBUG_REG20(pa_mh_data_63_32) \ + ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_AVALID_q_SIZE 1 +#define MH_DEBUG_REG21_AREADY_q_SIZE 1 +#define MH_DEBUG_REG21_AID_q_SIZE 3 +#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG21_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG21_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG21_ARID_q_SIZE 3 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG21_RVALID_q_SIZE 1 +#define MH_DEBUG_REG21_RREADY_q_SIZE 1 +#define MH_DEBUG_REG21_RLAST_q_SIZE 1 +#define MH_DEBUG_REG21_RID_q_SIZE 3 +#define MH_DEBUG_REG21_WVALID_q_SIZE 1 +#define MH_DEBUG_REG21_WREADY_q_SIZE 1 +#define MH_DEBUG_REG21_WLAST_q_SIZE 1 +#define MH_DEBUG_REG21_WID_q_SIZE 3 +#define MH_DEBUG_REG21_BVALID_q_SIZE 1 +#define MH_DEBUG_REG21_BREADY_q_SIZE 1 +#define MH_DEBUG_REG21_BID_q_SIZE 3 + +#define MH_DEBUG_REG21_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG21_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG21_AID_q_SHIFT 2 +#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG21_ARID_q_SHIFT 10 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG21_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG21_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG21_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG21_RID_q_SHIFT 18 +#define MH_DEBUG_REG21_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG21_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG21_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG21_WID_q_SHIFT 24 +#define MH_DEBUG_REG21_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG21_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG21_BID_q_SHIFT 29 + +#define MH_DEBUG_REG21_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG21_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG21_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG21_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG21_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG21_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG21_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG21_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG21_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG21_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG21_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG21_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG21_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG21_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG21_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG21_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG21_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_AVALID_q_MASK | \ + MH_DEBUG_REG21_AREADY_q_MASK | \ + MH_DEBUG_REG21_AID_q_MASK | \ + MH_DEBUG_REG21_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG21_ARVALID_q_MASK | \ + MH_DEBUG_REG21_ARREADY_q_MASK | \ + MH_DEBUG_REG21_ARID_q_MASK | \ + MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG21_RVALID_q_MASK | \ + MH_DEBUG_REG21_RREADY_q_MASK | \ + MH_DEBUG_REG21_RLAST_q_MASK | \ + MH_DEBUG_REG21_RID_q_MASK | \ + MH_DEBUG_REG21_WVALID_q_MASK | \ + MH_DEBUG_REG21_WREADY_q_MASK | \ + MH_DEBUG_REG21_WLAST_q_MASK | \ + MH_DEBUG_REG21_WID_q_MASK | \ + MH_DEBUG_REG21_BVALID_q_MASK | \ + MH_DEBUG_REG21_BREADY_q_MASK | \ + MH_DEBUG_REG21_BID_q_MASK) + +#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)) + +#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT) + +#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_AVALID_q_SIZE 1 +#define MH_DEBUG_REG22_AREADY_q_SIZE 1 +#define MH_DEBUG_REG22_AID_q_SIZE 3 +#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG22_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG22_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG22_ARID_q_SIZE 3 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG22_WVALID_q_SIZE 1 +#define MH_DEBUG_REG22_WREADY_q_SIZE 1 +#define MH_DEBUG_REG22_WLAST_q_SIZE 1 +#define MH_DEBUG_REG22_WID_q_SIZE 3 +#define MH_DEBUG_REG22_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG22_BVALID_q_SIZE 1 +#define MH_DEBUG_REG22_BREADY_q_SIZE 1 +#define MH_DEBUG_REG22_BID_q_SIZE 3 + +#define MH_DEBUG_REG22_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG22_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG22_AID_q_SHIFT 2 +#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG22_ARID_q_SHIFT 9 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG22_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG22_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG22_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG22_WID_q_SHIFT 16 +#define MH_DEBUG_REG22_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG22_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG22_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG22_BID_q_SHIFT 29 + +#define MH_DEBUG_REG22_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG22_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG22_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG22_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG22_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG22_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG22_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG22_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG22_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG22_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG22_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG22_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG22_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG22_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_AVALID_q_MASK | \ + MH_DEBUG_REG22_AREADY_q_MASK | \ + MH_DEBUG_REG22_AID_q_MASK | \ + MH_DEBUG_REG22_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG22_ARVALID_q_MASK | \ + MH_DEBUG_REG22_ARREADY_q_MASK | \ + MH_DEBUG_REG22_ARID_q_MASK | \ + MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG22_WVALID_q_MASK | \ + MH_DEBUG_REG22_WREADY_q_MASK | \ + MH_DEBUG_REG22_WLAST_q_MASK | \ + MH_DEBUG_REG22_WID_q_MASK | \ + MH_DEBUG_REG22_WSTRB_q_MASK | \ + MH_DEBUG_REG22_BVALID_q_MASK | \ + MH_DEBUG_REG22_BREADY_q_MASK | \ + MH_DEBUG_REG22_BID_q_MASK) + +#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)) + +#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT) + +#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG24_REG_A_SIZE 14 +#define MH_DEBUG_REG24_REG_RE_SIZE 1 +#define MH_DEBUG_REG24_REG_WE_SIZE 1 +#define MH_DEBUG_REG24_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG24_REG_A_SHIFT 2 +#define MH_DEBUG_REG24_REG_RE_SHIFT 16 +#define MH_DEBUG_REG24_REG_WE_SHIFT 17 +#define MH_DEBUG_REG24_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG24_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG24_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG24_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG24_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG24_REG_A_MASK | \ + MH_DEBUG_REG24_REG_RE_MASK | \ + MH_DEBUG_REG24_REG_WE_MASK | \ + MH_DEBUG_REG24_BLOCK_RS_MASK) + +#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_REG_WD_SIZE 32 + +#define MH_DEBUG_REG25_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG25_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_REG_WD_MASK) + +#define MH_DEBUG_REG25(reg_wd) \ + ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)) + +#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT) + +#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG26_CNT_q_SIZE 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG26_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 +#define MH_DEBUG_REG26_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_PA_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG26_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG26_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5 +#define MH_DEBUG_REG26_CNT_q_SHIFT 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13 +#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17 +#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18 +#define MH_DEBUG_REG26_CP_RTR_q_SHIFT 19 +#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20 +#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23 +#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24 +#define MH_DEBUG_REG26_RB_RTR_q_SHIFT 25 +#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26 +#define MH_DEBUG_REG26_PA_RTR_q_SHIFT 27 +#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020 +#define MH_DEBUG_REG26_CNT_q_MASK 0x00000fc0 +#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG26_MH_BUSY_d_MASK 0x00004000 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000 +#define MH_DEBUG_REG26_CP_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG26_CP_RTR_q_MASK 0x00080000 +#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG26_VGT_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000 +#define MH_DEBUG_REG26_RB_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG26_RB_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG26_PA_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG26_PA_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG26_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG26_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG26_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG26_CNT_q_MASK | \ + MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG26_MH_BUSY_d_MASK | \ + MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \ + MH_DEBUG_REG26_CP_SEND_q_MASK | \ + MH_DEBUG_REG26_CP_RTR_q_MASK | \ + MH_DEBUG_REG26_VGT_SEND_q_MASK | \ + MH_DEBUG_REG26_VGT_RTR_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_RB_SEND_q_MASK | \ + MH_DEBUG_REG26_RB_RTR_q_MASK | \ + MH_DEBUG_REG26_PA_SEND_q_MASK | \ + MH_DEBUG_REG26_PA_RTR_q_MASK | \ + MH_DEBUG_REG26_RDC_VALID_MASK | \ + MH_DEBUG_REG26_RDC_RLAST_MASK | \ + MH_DEBUG_REG26_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG26_BRC_VALID_MASK) + +#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG27_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG27_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG27_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG27_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG27_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24 +#define MH_DEBUG_REG27_ARB_QUAL_SHIFT 25 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG27_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG27_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG27_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG27_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG27_ARB_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG27_EFF1_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG27_EFF1_WIN_MASK | \ + MH_DEBUG_REG27_KILL_EFF1_MASK | \ + MH_DEBUG_REG27_ARB_HOLD_MASK | \ + MH_DEBUG_REG27_ARB_RTR_q_MASK | \ + MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_ARB_QUAL_MASK | \ + MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG27_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG28_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG28_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG28_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG28_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG28_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG28_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG28_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_EFF1_WINNER_MASK | \ + MH_DEBUG_REG28_ARB_WINNER_MASK | \ + MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_ARB_QUAL_MASK | \ + MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_EFF1_WIN_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_RTR_q_MASK | \ + MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG29_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG29_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_CLNT_REQ_SIZE 5 +#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9 +#define MH_DEBUG_REG29_ARB_HOLD_SHIFT 10 +#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11 +#define MH_DEBUG_REG29_CLNT_REQ_SHIFT 12 +#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17 +#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20 +#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23 +#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26 +#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038 +#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200 +#define MH_DEBUG_REG29_ARB_HOLD_MASK 0x00000400 +#define MH_DEBUG_REG29_ARB_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG29_CLNT_REQ_MASK 0x0001f000 +#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000 +#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000 +#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000 +#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000 +#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG29_ARB_HOLD_MASK | \ + MH_DEBUG_REG29_ARB_RTR_q_MASK | \ + MH_DEBUG_REG29_CLNT_REQ_MASK | \ + MH_DEBUG_REG29_RECENT_d_0_MASK | \ + MH_DEBUG_REG29_RECENT_d_1_MASK | \ + MH_DEBUG_REG29_RECENT_d_2_MASK | \ + MH_DEBUG_REG29_RECENT_d_3_MASK | \ + MH_DEBUG_REG29_RECENT_d_4_MASK) + +#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \ + ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \ + (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \ + (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)) + +#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG30_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG30_WLAST_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG30_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28 +#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG30_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000 +#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG30_TC_MH_written_MASK | \ + MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG30_WLAST_q_MASK | \ + MH_DEBUG_REG30_WBURST_IP_q_MASK | \ + MH_DEBUG_REG30_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_CP_MH_write_MASK | \ + MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_ARB_WINNER_MASK) + +#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG32_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_KILL_EFF1_MASK | \ + MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG32_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG33_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_KILL_EFF1_MASK | \ + MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG33_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_TC_MH_send_MASK | \ + MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_TC_MH_send_MASK | \ + MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_TC_MH_send_MASK | \ + MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_TC_MH_send_MASK | \ + MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_WE_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG43_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG43_MMU_WE_SIZE 1 +#define MH_DEBUG_REG43_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_ID_SIZE 3 +#define MH_DEBUG_REG43_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG43_MMU_BLEN_SIZE 1 +#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_WDB_WE_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG43_ARB_WE_SHIFT 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3 +#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5 +#define MH_DEBUG_REG43_MMU_RTR_SHIFT 6 +#define MH_DEBUG_REG43_ARB_ID_q_SHIFT 7 +#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10 +#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13 +#define MH_DEBUG_REG43_MMU_WE_SHIFT 16 +#define MH_DEBUG_REG43_ARQ_RTR_SHIFT 17 +#define MH_DEBUG_REG43_MMU_ID_SHIFT 18 +#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21 +#define MH_DEBUG_REG43_MMU_BLEN_SHIFT 22 +#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24 +#define MH_DEBUG_REG43_WDB_WE_SHIFT 25 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG43_ARB_WE_MASK 0x00000002 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG43_ARB_RTR_q_MASK 0x00000008 +#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020 +#define MH_DEBUG_REG43_MMU_RTR_MASK 0x00000040 +#define MH_DEBUG_REG43_ARB_ID_q_MASK 0x00000380 +#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400 +#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000 +#define MH_DEBUG_REG43_MMU_WE_MASK 0x00010000 +#define MH_DEBUG_REG43_ARQ_RTR_MASK 0x00020000 +#define MH_DEBUG_REG43_MMU_ID_MASK 0x001c0000 +#define MH_DEBUG_REG43_MMU_WRITE_MASK 0x00200000 +#define MH_DEBUG_REG43_MMU_BLEN_MASK 0x00400000 +#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000 +#define MH_DEBUG_REG43_WDB_WE_MASK 0x02000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000 + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \ + MH_DEBUG_REG43_ARB_WE_MASK | \ + MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \ + MH_DEBUG_REG43_ARB_RTR_q_MASK | \ + MH_DEBUG_REG43_ARB_REG_RTR_MASK | \ + MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \ + MH_DEBUG_REG43_MMU_RTR_MASK | \ + MH_DEBUG_REG43_ARB_ID_q_MASK | \ + MH_DEBUG_REG43_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG43_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG43_MMU_WE_MASK | \ + MH_DEBUG_REG43_ARQ_RTR_MASK | \ + MH_DEBUG_REG43_MMU_ID_MASK | \ + MH_DEBUG_REG43_MMU_WRITE_MASK | \ + MH_DEBUG_REG43_MMU_BLEN_MASK | \ + MH_DEBUG_REG43_WBURST_IP_q_MASK | \ + MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG43_WDB_WE_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) + +#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \ + ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \ + (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \ + (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \ + (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \ + (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \ + (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int : 4; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int : 4; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WE_SIZE 1 +#define MH_DEBUG_REG44_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG44_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG44_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG44_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG44_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG44_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG44_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WE_MASK | \ + MH_DEBUG_REG44_ARB_ID_q_MASK | \ + MH_DEBUG_REG44_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_MMU_WE_SIZE 1 +#define MH_DEBUG_REG45_MMU_ID_SIZE 3 +#define MH_DEBUG_REG45_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG45_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG45_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG45_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG45_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG45_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG45_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_MMU_WE_MASK | \ + MH_DEBUG_REG45_MMU_ID_MASK | \ + MH_DEBUG_REG45_MMU_PAD_MASK) + +#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WE_SIZE 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG46_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG46_WDB_WE_SHIFT 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4 +#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19 +#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG46_WDB_WE_MASK 0x00000002 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008 +#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0 +#define MH_DEBUG_REG46_ARB_WLAST_MASK 0x00001000 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000 +#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000 + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG46_WDB_WE_MASK | \ + MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \ + MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG46_ARB_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \ + (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RVALID_q_SIZE 1 +#define MH_DEBUG_REG49_RREADY_q_SIZE 1 +#define MH_DEBUG_REG49_RLAST_q_SIZE 1 +#define MH_DEBUG_REG49_BVALID_q_SIZE 1 +#define MH_DEBUG_REG49_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG49_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG49_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG49_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG49_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG49_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG49_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG49_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG49_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG49_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG49_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RVALID_q_MASK | \ + MH_DEBUG_REG49_RREADY_q_MASK | \ + MH_DEBUG_REG49_RLAST_q_MASK | \ + MH_DEBUG_REG49_BVALID_q_MASK | \ + MH_DEBUG_REG49_BREADY_q_MASK) + +#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT) + +#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_RID_SIZE 3 +#define MH_DEBUG_REG50_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG50_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG50_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG50_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG50_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG50_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG50_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG50_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG50_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG50_RDC_VALID_MASK | \ + MH_DEBUG_REG50_RDC_RID_MASK | \ + MH_DEBUG_REG50_RDC_RLAST_MASK | \ + MH_DEBUG_REG50_RDC_RRESP_MASK | \ + MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG51(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2 +#define MH_DEBUG_REG52_ARB_WE_SIZE 1 +#define MH_DEBUG_REG52_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22 +#define MH_DEBUG_REG52_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0 +#define MH_DEBUG_REG52_ARB_WE_SHIFT 2 +#define MH_DEBUG_REG52_MMU_RTR_SHIFT 3 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4 +#define MH_DEBUG_REG52_ARB_ID_q_SHIFT 26 +#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003 +#define MH_DEBUG_REG52_ARB_WE_MASK 0x00000004 +#define MH_DEBUG_REG52_MMU_RTR_MASK 0x00000008 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0 +#define MH_DEBUG_REG52_ARB_ID_q_MASK 0x1c000000 +#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \ + MH_DEBUG_REG52_ARB_WE_MASK | \ + MH_DEBUG_REG52_MMU_RTR_MASK | \ + MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \ + MH_DEBUG_REG52_ARB_ID_q_MASK | \ + MH_DEBUG_REG52_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK) + +#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \ + ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \ + (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \ + (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_stage1_valid_SIZE 1 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG53_tag_match_q_SIZE 1 +#define MH_DEBUG_REG53_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG53_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG53_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG53_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG53_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG53_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG53_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG53_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG53_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_stage1_valid_MASK | \ + MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG53_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG53_tag_match_q_MASK | \ + MH_DEBUG_REG53_tag_miss_q_MASK | \ + MH_DEBUG_REG53_va_in_range_q_MASK | \ + MH_DEBUG_REG53_MMU_MISS_MASK | \ + MH_DEBUG_REG53_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG53_MMU_HIT_MASK | \ + MH_DEBUG_REG53_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG54_MMU_WE_SIZE 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG54_stage1_valid_SIZE 1 +#define MH_DEBUG_REG54_stage2_valid_SIZE 1 +#define MH_DEBUG_REG54_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG54_tag_match_q_SIZE 1 +#define MH_DEBUG_REG54_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG54_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG54_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG54_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG54_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG54_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG54_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG54_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG54_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_ARQ_RTR_MASK | \ + MH_DEBUG_REG54_MMU_WE_MASK | \ + MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG54_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG54_stage1_valid_MASK | \ + MH_DEBUG_REG54_stage2_valid_MASK | \ + MH_DEBUG_REG54_client_behavior_q_MASK | \ + MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG54_tag_match_q_MASK | \ + MH_DEBUG_REG54_tag_miss_q_MASK | \ + MH_DEBUG_REG54_va_in_range_q_MASK | \ + MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_MASK) + +#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG55_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG55_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG0_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG1_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG56_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG56_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG2_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG3_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG57_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG57_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG4_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG5_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG58_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG58_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG6_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG7_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG59_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG59_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG8_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG9_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG60_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG60_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG10_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG11_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG61_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG61_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG61_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG61_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG61_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_TAG12_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG61_TAG13_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG62_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG62_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG62_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG62_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG62_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_TAG14_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG62_TAG15_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \ + (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int : 6; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 6; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_FACE_DATA struct + */ + +#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27 + +#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5 + +#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0 + +#define PA_SU_FACE_DATA_MASK \ + (PA_SU_FACE_DATA_BASE_ADDR_MASK) + +#define PA_SU_FACE_DATA(base_addr) \ + ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)) + +#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \ + ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \ + pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int : 5; + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + } pa_su_face_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + unsigned int : 5; + } pa_su_face_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_face_data_t f; +} pa_su_face_data_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \ + PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, zero_area_faceness, face_kill_enable, face_write_enable) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \ + (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \ + (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \ + (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 2; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int : 2; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fposition_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fposition_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fposition_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fposition_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fposition << SC_DEBUG_7_fposition_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fposition(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fposition_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fposition_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fposition_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fposition_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fposition << SC_DEBUG_8_fposition_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fposition(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int : 1; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 1; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 +#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1 +#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30 +#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000 +#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000 + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK | \ + VGT_BIN_SIZE_FACENESS_FETCH_MASK | \ + VGT_BIN_SIZE_FACENESS_RESET_MASK) + +#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \ + (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \ + (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_VS_WATCHDOG_TIMER struct + */ + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_VS_WATCHDOG_TIMER_MASK \ + (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_vs_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_vs_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_watchdog_timer_t f; +} sq_vs_watchdog_timer_u; + + +/* + * SQ_PS_WATCHDOG_TIMER struct + */ + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_PS_WATCHDOG_TIMER_MASK \ + (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_ps_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_ps_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_watchdog_timer_t f; +} sq_ps_watchdog_timer_u; + + +/* + * SQ_INT_CNTL struct + */ + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002 + +#define SQ_INT_CNTL_MASK \ + (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \ + SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) + +#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \ + ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \ + (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)) + +#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int : 30; + } sq_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int : 30; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + } sq_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_cntl_t f; +} sq_int_cntl_u; + + +/* + * SQ_INT_STATUS struct + */ + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002 + +#define SQ_INT_STATUS_MASK \ + (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \ + SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) + +#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \ + ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \ + (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)) + +#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int : 30; + } sq_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int : 30; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + } sq_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_status_t f; +} sq_int_status_u; + + +/* + * SQ_INT_ACK struct + */ + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002 + +#define SQ_INT_ACK_MASK \ + (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \ + SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) + +#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \ + ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \ + (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)) + +#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int : 30; + } sq_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int : 30; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + } sq_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_ack_t f; +} sq_int_ack_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 +#define RB_STENCILREFMASK_RESERVED0_SIZE 1 +#define RB_STENCILREFMASK_RESERVED1_SIZE 1 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 +#define RB_STENCILREFMASK_RESERVED0_SHIFT 24 +#define RB_STENCILREFMASK_RESERVED1_SHIFT 25 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 +#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000 +#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \ + RB_STENCILREFMASK_RESERVED0_MASK | \ + RB_STENCILREFMASK_RESERVED1_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \ + (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \ + (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int : 6; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 6; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 +#define RB_COLOR_MASK_RESERVED2_SIZE 1 +#define RB_COLOR_MASK_RESERVED3_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 +#define RB_COLOR_MASK_RESERVED2_SHIFT 4 +#define RB_COLOR_MASK_RESERVED3_SHIFT 5 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 +#define RB_COLOR_MASK_RESERVED2_MASK 0x00000010 +#define RB_COLOR_MASK_RESERVED3_MASK 0x00000020 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK | \ + RB_COLOR_MASK_RESERVED2_MASK | \ + RB_COLOR_MASK_RESERVED3_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \ + (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \ + (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int : 26; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 26; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1 +#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 +#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24 +#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 +#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000 +#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_RESERVED4_MASK | \ + RB_STENCILREFMASK_BF_RESERVED5_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \ + (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \ + (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int : 6; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 6; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_CRC_SYSTEM_SIZE 1 +#define RB_BC_CONTROL_RESERVED6_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30 +#define RB_BC_CONTROL_RESERVED6_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_CRC_SYSTEM_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED6_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_CRC_SYSTEM_MASK | \ + RB_BC_CONTROL_RESERVED6_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \ + (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * RB_BC_SPARES struct + */ + +#define RB_BC_SPARES_RESERVED_SIZE 32 + +#define RB_BC_SPARES_RESERVED_SHIFT 0 + +#define RB_BC_SPARES_RESERVED_MASK 0xffffffff + +#define RB_BC_SPARES_MASK \ + (RB_BC_SPARES_RESERVED_MASK) + +#define RB_BC_SPARES(reserved) \ + ((reserved << RB_BC_SPARES_RESERVED_SHIFT)) + +#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \ + ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT) + +#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \ + rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_spares_t f; +} rb_bc_spares_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h new file mode 100644 index 000000000000..6968abb48bd7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h @@ -0,0 +1,550 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_FACE_DATA regPA_SU_FACE_DATA; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_VS_WATCHDOG_TIMER regSQ_VS_WATCHDOG_TIMER; +typedef union SQ_PS_WATCHDOG_TIMER regSQ_PS_WATCHDOG_TIMER; +typedef union SQ_INT_CNTL regSQ_INT_CNTL; +typedef union SQ_INT_STATUS regSQ_INT_STATUS; +typedef union SQ_INT_ACK regSQ_INT_ACK; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_AXI_HALT_CONTROL regMH_AXI_HALT_CONTROL; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG_OUT regRBBM_DEBUG_OUT; +typedef union RBBM_DEBUG_CNTL regRBBM_DEBUG_CNTL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union RB_BC_SPARES regRB_BC_SPARES; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h new file mode 100644 index 000000000000..ba259a6c9d5f --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h @@ -0,0 +1,169 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamatoix_h +#define _yamatoix_h + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +// [SUDEBUGIND] : Indirect Registers + +#define ixCLIPPER_DEBUG_REG00 0x0000 +#define ixCLIPPER_DEBUG_REG01 0x0001 +#define ixCLIPPER_DEBUG_REG02 0x0002 +#define ixCLIPPER_DEBUG_REG03 0x0003 +#define ixCLIPPER_DEBUG_REG04 0x0004 +#define ixCLIPPER_DEBUG_REG05 0x0005 +#define ixCLIPPER_DEBUG_REG09 0x0009 +#define ixCLIPPER_DEBUG_REG10 0x000A +#define ixCLIPPER_DEBUG_REG11 0x000B +#define ixCLIPPER_DEBUG_REG12 0x000C +#define ixCLIPPER_DEBUG_REG13 0x000D +#define ixSXIFCCG_DEBUG_REG0 0x0011 +#define ixSXIFCCG_DEBUG_REG1 0x0012 +#define ixSXIFCCG_DEBUG_REG2 0x0013 +#define ixSXIFCCG_DEBUG_REG3 0x0014 +#define ixSETUP_DEBUG_REG0 0x0015 +#define ixSETUP_DEBUG_REG1 0x0016 +#define ixSETUP_DEBUG_REG2 0x0017 +#define ixSETUP_DEBUG_REG3 0x0018 +#define ixSETUP_DEBUG_REG4 0x0019 +#define ixSETUP_DEBUG_REG5 0x001A + +// [SCDEBUGIND] : Indirect Registers + +#define ixSC_DEBUG_0 0x0000 +#define ixSC_DEBUG_1 0x0001 +#define ixSC_DEBUG_2 0x0002 +#define ixSC_DEBUG_3 0x0003 +#define ixSC_DEBUG_4 0x0004 +#define ixSC_DEBUG_5 0x0005 +#define ixSC_DEBUG_6 0x0006 +#define ixSC_DEBUG_7 0x0007 +#define ixSC_DEBUG_8 0x0008 +#define ixSC_DEBUG_9 0x0009 +#define ixSC_DEBUG_10 0x000A +#define ixSC_DEBUG_11 0x000B +#define ixSC_DEBUG_12 0x000C + +// [VGTDEBUGIND] : Indirect Registers + +#define ixVGT_DEBUG_REG0 0x0000 +#define ixVGT_DEBUG_REG1 0x0001 +#define ixVGT_DEBUG_REG3 0x0003 +#define ixVGT_DEBUG_REG6 0x0006 +#define ixVGT_DEBUG_REG7 0x0007 +#define ixVGT_DEBUG_REG8 0x0008 +#define ixVGT_DEBUG_REG9 0x0009 +#define ixVGT_DEBUG_REG10 0x000A +#define ixVGT_DEBUG_REG12 0x000C +#define ixVGT_DEBUG_REG13 0x000D +#define ixVGT_DEBUG_REG14 0x000E +#define ixVGT_DEBUG_REG15 0x000F +#define ixVGT_DEBUG_REG16 0x0010 +#define ixVGT_DEBUG_REG17 0x0011 +#define ixVGT_DEBUG_REG18 0x0012 +#define ixVGT_DEBUG_REG20 0x0014 +#define ixVGT_DEBUG_REG21 0x0015 + +// [MHDEBUGIND] : Indirect Registers + +#define ixMH_DEBUG_REG00 0x0000 +#define ixMH_DEBUG_REG01 0x0001 +#define ixMH_DEBUG_REG02 0x0002 +#define ixMH_DEBUG_REG03 0x0003 +#define ixMH_DEBUG_REG04 0x0004 +#define ixMH_DEBUG_REG05 0x0005 +#define ixMH_DEBUG_REG06 0x0006 +#define ixMH_DEBUG_REG07 0x0007 +#define ixMH_DEBUG_REG08 0x0008 +#define ixMH_DEBUG_REG09 0x0009 +#define ixMH_DEBUG_REG10 0x000A +#define ixMH_DEBUG_REG11 0x000B +#define ixMH_DEBUG_REG12 0x000C +#define ixMH_DEBUG_REG13 0x000D +#define ixMH_DEBUG_REG14 0x000E +#define ixMH_DEBUG_REG15 0x000F +#define ixMH_DEBUG_REG16 0x0010 +#define ixMH_DEBUG_REG17 0x0011 +#define ixMH_DEBUG_REG18 0x0012 +#define ixMH_DEBUG_REG19 0x0013 +#define ixMH_DEBUG_REG20 0x0014 +#define ixMH_DEBUG_REG21 0x0015 +#define ixMH_DEBUG_REG22 0x0016 +#define ixMH_DEBUG_REG23 0x0017 +#define ixMH_DEBUG_REG24 0x0018 +#define ixMH_DEBUG_REG25 0x0019 +#define ixMH_DEBUG_REG26 0x001A +#define ixMH_DEBUG_REG27 0x001B +#define ixMH_DEBUG_REG28 0x001C +#define ixMH_DEBUG_REG29 0x001D +#define ixMH_DEBUG_REG30 0x001E +#define ixMH_DEBUG_REG31 0x001F +#define ixMH_DEBUG_REG32 0x0020 +#define ixMH_DEBUG_REG33 0x0021 +#define ixMH_DEBUG_REG34 0x0022 +#define ixMH_DEBUG_REG35 0x0023 +#define ixMH_DEBUG_REG36 0x0024 +#define ixMH_DEBUG_REG37 0x0025 +#define ixMH_DEBUG_REG38 0x0026 +#define ixMH_DEBUG_REG39 0x0027 +#define ixMH_DEBUG_REG40 0x0028 +#define ixMH_DEBUG_REG41 0x0029 +#define ixMH_DEBUG_REG42 0x002A +#define ixMH_DEBUG_REG43 0x002B +#define ixMH_DEBUG_REG44 0x002C +#define ixMH_DEBUG_REG45 0x002D +#define ixMH_DEBUG_REG46 0x002E +#define ixMH_DEBUG_REG47 0x002F +#define ixMH_DEBUG_REG48 0x0030 +#define ixMH_DEBUG_REG49 0x0031 +#define ixMH_DEBUG_REG50 0x0032 +#define ixMH_DEBUG_REG51 0x0033 +#define ixMH_DEBUG_REG52 0x0034 +#define ixMH_DEBUG_REG53 0x0035 +#define ixMH_DEBUG_REG54 0x0036 +#define ixMH_DEBUG_REG55 0x0037 +#define ixMH_DEBUG_REG56 0x0038 +#define ixMH_DEBUG_REG57 0x0039 +#define ixMH_DEBUG_REG58 0x003A +#define ixMH_DEBUG_REG59 0x003B +#define ixMH_DEBUG_REG60 0x003C +#define ixMH_DEBUG_REG61 0x003D +#define ixMH_DEBUG_REG62 0x003E +#define ixMH_DEBUG_REG63 0x003F + + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // _yamatob_h + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h new file mode 100644 index 000000000000..ab11205f1092 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h @@ -0,0 +1,1867 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + + + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + SPARE33 = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_ALU1_ACTIVE_VTX_SIMD3 = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_ALU1_ACTIVE_PIX_SIMD3 = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_SYNC_ALU_STALL_SIMD3_VTX = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_SYNC_ALU_STALL_SIMD3_PIX = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_CONSTANTS_USED_SIMD3 = 85, + SQ_CONSTANTS_SENT_SP_SIMD3 = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_W_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h new file mode 100644 index 000000000000..f2f4dec63daa --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h @@ -0,0 +1,1674 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(SPARE33, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD3, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD3, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_VTX, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_PIX, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD3, 85) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD3, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_W_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h new file mode 100644 index 000000000000..d44be483e953 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h @@ -0,0 +1,3310 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(PERFCOUNTER_REF, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(CLIP_DISABLE, bool) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(W_NAN_RETAIN, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(PIX_CENTER, PixCenter) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(QUANT_MODE, QuantMode) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(HEIGHT, fixed12_4) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MIN_SIZE, fixed12_4) + GENERATE_FIELD(MAX_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(CULL_FRONT, bool) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(LINE_PATTERN, hex) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(BRES_CNTL, int) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(LAST_PIXEL, bool) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_PTR, int) + GENERATE_FIELD(CURRENT_COUNT, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(NUM_INDICES, uint) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) + GENERATE_FIELD(DST_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(L2_INVALIDATE, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(TC_BUSY, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TP_BUSY_EXTEND, int) + GENERATE_FIELD(TC_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_INPUT_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TPC_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(LOD_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(SQ_TP_WAKEUP, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(BLEND_PRECISION, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_INPUT_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TP_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_LOD_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(TT_MODE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(not_MH_TC_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(tca_rts, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(tp0_full, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_tpc_rts, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(captue_state_rts, int) + GENERATE_FIELD(capture_tca_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(access512, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(sector_format512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(left_done, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(valid_left_q, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(quad_sel_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(setquads_to_send, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(tc0_arb_rts, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(arb_RTR, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ipbuf_busy, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_pstate, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dcmp_mux_send, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_stall, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(n0_dxt2_4_types, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_incoming_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_sg_crd_RTR, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(rl_sg_sector_format, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(busy, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(fifo_busy, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(TCO_TCB_read_xfc, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_DYNAMIC, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_SIZE_VTX, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_PIX, int) + GENERATE_FIELD(INST_BASE_VTX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_CONSTANTS_RT, int) + GENERATE_FIELD(EO_TSTATE_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_ALUCST_SIZE, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(TIMEBASE, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(VC_VSR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_GPR_SIZE, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(EX_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(POS_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(END_OF_BUFFER, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(VTX_SYNC_CNT, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(BUSY_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(BUSY, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(VECTOR_RESULT, int) + GENERATE_FIELD(CST_0_ABS_MOD, Abs_modifier) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(SST_0_ABS_MOD, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(CONST_0_REL_ABS, int) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_C_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_2, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(OPCODE, TexInstOpcode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(DST_SEL_X, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(PRED_SELECT, PredSelect) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(USE_REG_GRADIENTS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(OPCODE, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(SRC_SEL, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(DST_SEL_X, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(PRED_SELECT, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(STRIDE, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(TYPE, int) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(BASE_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(ENDIAN_SWAP, int) + GENERATE_FIELD(LIMIT_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(VS_CF_SIZE, int) + GENERATE_FIELD(PS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(PARAM_SHADE, ParamShade) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(GEN_INDEX_VTX, int) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_0, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_7, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_8, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_15, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(TX_CACHE_SEL, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_ON, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_COUNT, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_ON_PIX, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_BREAK_ADDR, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(CPw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(MMUr_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(AXI_READ_ERROR, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_READ_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(MMU_ENABLE, bool) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(NUM_64KB_REGIONS, int) + GENERATE_FIELD(VA_BASE, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(PAGE_FAULT, int) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(REQ_VA, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_ALL, int) + GENERATE_FIELD(INVALIDATE_TC, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(WAIT_RE_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(CMDFIFO_AVAIL, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(GUI_ACTIVE, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(DISPLAY_ID0_ACTIVE, int) + GENERATE_FIELD(DISPLAY_ID1_ACTIVE, int) + GENERATE_FIELD(DISPLAY_ID2_ACTIVE, int) + GENERATE_FIELD(VSYNC_ACTIVE, int) + GENERATE_FIELD(USE_DISPLAY_ID0, int) + GENERATE_FIELD(USE_DISPLAY_ID1, int) + GENERATE_FIELD(USE_DISPLAY_ID2, int) + GENERATE_FIELD(SW_CNTL, int) + GENERATE_FIELD(NUM_BUFS, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(PATCH_REVISION, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(CUSTOMER_ID, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(PARTNUMBER1, int) + GENERATE_FIELD(DESIGNER0, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(DESIGNER1, int) + GENERATE_FIELD(REVISION, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(CONTINUATION, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(READ_TIMEOUT, int) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) + GENERATE_FIELD(SKEW_COUNT, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_CP, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_VGT, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_RTR, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ADDRESS, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ERROR, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(RDERR_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(RDERR_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(RDERR_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(MH_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(RBBM_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_BUFSZ, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_SWAP, int) + GENERATE_FIELD(RB_RPTR_ADDR, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_TIMER, int) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_SWAP, int) + GENERATE_FIELD(RB_WPTR_BASE, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_IB1_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_ST_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(MEQ_END, int) + GENERATE_FIELD(ROQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_RING, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_IB2, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB1_COUNTER, int) + GENERATE_FIELD(IB2_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_RPTR_ST, int) + GENERATE_FIELD(STQ_WPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_RPTR, int) + GENERATE_FIELD(MEQ_WPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(TAG_0_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(INVALID_RETURN_TAG, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_INDEX, int) + GENERATE_FIELD(CMD_QUEUE_SEL, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(ME_STATMUX, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(PROG_CNT_SIZE, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_UMSK, int) + GENERATE_FIELD(SCRATCH_SWAP, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_SWM, int) + GENERATE_FIELD(VS_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_SWAP, int) + GENERATE_FIELD(VS_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_SWM, int) + GENERATE_FIELD(PS_DONE_CNTR, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_SWAP, int) + GENERATE_FIELD(PS_DONE_ADDR, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_SWAP, int) + GENERATE_FIELD(CF_DONE_ADDR, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_SWAP, int) + GENERATE_FIELD(NRT_WRITE_ADDR, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(SW_INT_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(RB_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(SW_INT_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(RB_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(SW_INT_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(RB_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_STATE, int) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(DISCARD_0, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_15, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(DISCARD_16, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_31, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(DISCARD_32, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_47, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(DISCARD_48, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_63, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(MIU_WR_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(CP_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(SURFACE_PITCH, uint) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_BASE, uint) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) + GENERATE_FIELD(DEPTH_BASE, uint) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(STENCILREF, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILWRITEMASK, hex) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(WRITE_RED, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_RED, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_BLUE, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(STENCILREF_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCIL_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(BLEND_FORCE, bool) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(CLEAR_MASK, uint) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_X, uint) + GENERATE_FIELD(OFFSET_Y, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED9, bool) + GENERATE_FIELD(RESERVED10, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_RANGE, hex) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z_TILE_EMPTY, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ACCUM_VALID, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h new file mode 100644 index 000000000000..0e32e421d0a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _R400IPT_H_ +#define _R400IPT_H_ + +// Hand-generated list from Yamato_PM4_Spec.doc + +#define PM4_PACKET0_NOP 0x00000000 // Empty type-0 packet header +#define PM4_PACKET1_NOP 0x40000000 // Empty type-1 packet header +#define PM4_PACKET2_NOP 0x80000000 // Empty type-2 packet header (reserved) + +#define PM4_COUNT_SHIFT 16 +#define PM4_COUNT_MASK +#define PM4_PACKET_COUNT(__x) ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000) +// Type 3 packet headers + +#define PM4_PACKET3_NOP 0xC0001000 // Do nothing. +#define PM4_PACKET3_IB_PREFETCH_END 0xC0001700 // Internal Packet Used Only by CP +#define PM4_PACKET3_SUBBLK_PREFETCH 0xC0001F00 // Internal Packet Used Only by CP + +#define PM4_PACKET3_INSTR_PREFETCH 0xC0002000 // Internal Packet Used Only by CP +#define PM4_PACKET3_REG_RMW 0xC0002100 // Register Read-Modify-Write New for R400 +#define PM4_PACKET3_DRAW_INDX 0xC0002200 // Initiate fetch of index buffer New for R400 +#define PM4_PACKET3_VIZ_QUERY 0xC0002300 // Begin/End initiator for Viz Query extent processing New for R400 +#define PM4_PACKET3_SET_STATE 0xC0002500 // Fetch State Sub-Blocks and Initiate Shader Code DMAs New for R400 +#define PM4_PACKET3_WAIT_FOR_IDLE 0xC0002600 // Wait for the engine to be idle. +#define PM4_PACKET3_IM_LOAD 0xC0002700 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_IM_LOAD_IMMEDIATE 0xC0002B00 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_SET_CONSTANT 0xC0002D00 // Load Constant Into Chip & Shadow to Memory New for R400 +#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT 0xC0002E00 // Load All Constants from a Location in Memory New for R400 +#define PM4_PACKET3_LOAD_ALU_CONSTANT 0xC0002F00 // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants + +#define PM4_PACKET3_DRAW_INDX_BIN 0xC0003400 // Initiate fetch of index buffer and BIN info used for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2_BIN 0xC0003500 // Draw using supplied indices and initiate fetch of BIN info for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2 0xC0003600 // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt +#define PM4_PACKET3_INDIRECT_BUFFER_PFD 0xC0003700 +#define PM4_PACKET3_INVALIDATE_STATE 0xC0003B00 // Selective Invalidation of State Pointers New for R400 +#define PM4_PACKET3_WAIT_REG_MEM 0xC0003C00 // Wait Until a Register or Memory Location is a Specific Value. New for R400 +#define PM4_PACKET3_MEM_WRITE 0xC0003D00 // Write DWORD to Memory For Synchronization New for R400 +#define PM4_PACKET3_REG_TO_MEM 0xC0003E00 // Reads Register in Chip and Writes to Memory New for R400 +#define PM4_PACKET3_INDIRECT_BUFFER 0xC0003F00 // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer. Supported + +#define PM4_PACKET3_CP_INTERRUPT 0xC0004000 // Generate Interrupt from the Command Stream New for R400 +#define PM4_PACKET3_COND_EXEC 0xC0004400 // Conditional execution of a sequence of packets +#define PM4_PACKET3_COND_WRITE 0xC0004500 // Conditional Write to Memory New for R400 +#define PM4_PACKET3_EVENT_WRITE 0xC0004600 // Generate An Event that Creates a Write to Memory when Completed New for R400 +#define PM4_PACKET3_INSTR_MATCH 0xC0004700 // Internal Packet Used Only by CP +#define PM4_PACKET3_ME_INIT 0xC0004800 // Initialize CP's Micro Engine New for R400 +#define PM4_PACKET3_CONST_PREFETCH 0xC0004900 // Internal packet used only by CP +#define PM4_PACKET3_MEM_WRITE_CNTR 0xC0004F00 + +#define PM4_PACKET3_SET_BIN_MASK 0xC0005000 // Sets the 64-bit BIN_MASK register in the PFP +#define PM4_PACKET3_SET_BIN_SELECT 0xC0005100 // Sets the 64-bit BIN_SELECT register in the PFP +#define PM4_PACKET3_WAIT_REG_EQ 0xC0005200 // Wait until a register location is equal to a specific value +#define PM4_PACKET3_WAIT_REG_GTE 0xC0005300 // Wait until a register location is greater than or equal to a specific value +#define PM4_PACKET3_INCR_UPDT_STATE 0xC0005500 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_CONST 0xC0005600 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_INSTR 0xC0005700 // Internal Packet Used Only by CP +#define PM4_PACKET3_EVENT_WRITE_SHD 0xC0005800 // Generate a VS|PS_Done Event. +#define PM4_PACKET3_EVENT_WRITE_CFL 0xC0005900 // Generate a Cach Flush Done Event +#define PM4_PACKET3_EVENT_WRITE_ZPD 0xC0005B00 // Generate a Cach Flush Done Event +#define PM4_PACKET3_WAIT_UNTIL_READ 0xC0005C00 // Wait Until a Read completes. +#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE 0xC0005D00 // Wait Until all Base/Size writes from an IB_PFD packet have completed. +#define PM4_PACKET3_CONTEXT_UPDATE 0xC0005E00 // Updates the current context if needed. + + /****** New Opcodes For R400 (all decode values are TBD) ******/ + + +#endif // _R400IPT_H_ diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h new file mode 100644 index 000000000000..ad3d829bc94e --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h @@ -0,0 +1,5739 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fpos_MASK 0x00000010L +#define SC_DEBUG_7__fpos 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fpos_MASK 0x00100000L +#define SC_DEBUG_8__fpos 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000400L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00000800L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00001000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00002000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL 0x00004000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00008000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00010000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00020000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00040000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00080000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00100000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00200000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00400000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID 0x00800000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x01000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x04000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BE_q_MASK 0x00003fc0L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00004000L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00004000L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00008000L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00008000L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00010000L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00010000L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00020000L +#define MH_DEBUG_REG01__TC_SEND_q 0x00020000L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG01__TC_RTR_q 0x00040000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00080000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00080000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00100000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00100000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00200000L +#define MH_DEBUG_REG01__TC_MH_written 0x00200000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00400000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00800000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00800000L +#define MH_DEBUG_REG01__RB_BE_q_MASK 0xff000000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x0001c000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x00060000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG08__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG08__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG08__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG08__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG08__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG09__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG09__TC_MH_send 0x00000004L +#define MH_DEBUG_REG09__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG09__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG10__TC_MH_send 0x02000000L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG11__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG11__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG11__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG11__TC_MH_written 0x04000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG12__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG12__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG12__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG14__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG14__RB_MH_send 0x00000010L +#define MH_DEBUG_REG14__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG17__AVALID_q 0x00000001L +#define MH_DEBUG_REG17__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG17__AREADY_q 0x00000002L +#define MH_DEBUG_REG17__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG17__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG17__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG17__ARVALID_q 0x00000100L +#define MH_DEBUG_REG17__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG17__ARREADY_q 0x00000200L +#define MH_DEBUG_REG17__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG17__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG17__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG17__RVALID_q 0x00008000L +#define MH_DEBUG_REG17__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG17__RREADY_q 0x00010000L +#define MH_DEBUG_REG17__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG17__RLAST_q 0x00020000L +#define MH_DEBUG_REG17__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG17__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG17__WVALID_q 0x00200000L +#define MH_DEBUG_REG17__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG17__WREADY_q 0x00400000L +#define MH_DEBUG_REG17__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG17__WLAST_q 0x00800000L +#define MH_DEBUG_REG17__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG17__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG17__BVALID_q 0x08000000L +#define MH_DEBUG_REG17__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG17__BREADY_q 0x10000000L +#define MH_DEBUG_REG17__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG18__AVALID_q 0x00000001L +#define MH_DEBUG_REG18__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG18__AREADY_q 0x00000002L +#define MH_DEBUG_REG18__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG18__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG18__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG18__ARVALID_q 0x00000080L +#define MH_DEBUG_REG18__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG18__ARREADY_q 0x00000100L +#define MH_DEBUG_REG18__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG18__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG18__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG18__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG18__WVALID_q 0x00002000L +#define MH_DEBUG_REG18__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG18__WREADY_q 0x00004000L +#define MH_DEBUG_REG18__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG18__WLAST_q 0x00008000L +#define MH_DEBUG_REG18__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG18__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG18__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG18__BVALID_q 0x08000000L +#define MH_DEBUG_REG18__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG18__BREADY_q 0x10000000L +#define MH_DEBUG_REG18__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG19__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG19__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG19__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG20__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG20__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG20__REG_RE 0x00010000L +#define MH_DEBUG_REG20__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG20__REG_WE 0x00020000L +#define MH_DEBUG_REG20__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG20__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req_MASK 0x00000001L +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req 0x00000001L +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack_MASK 0x00000002L +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack 0x00000002L +#define MH_DEBUG_REG22__MH_RBBM_busy_MASK 0x00000004L +#define MH_DEBUG_REG22__MH_RBBM_busy 0x00000004L +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int 0x00000008L +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int_MASK 0x00000010L +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int 0x00000010L +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int_MASK 0x00000020L +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int 0x00000020L +#define MH_DEBUG_REG22__GAT_CLK_ENA_MASK 0x00000040L +#define MH_DEBUG_REG22__GAT_CLK_ENA 0x00000040L +#define MH_DEBUG_REG22__AXI_RDY_ENA_MASK 0x00000080L +#define MH_DEBUG_REG22__AXI_RDY_ENA 0x00000080L +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override_MASK 0x00000100L +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override 0x00000100L +#define MH_DEBUG_REG22__CNT_q_MASK 0x00007e00L +#define MH_DEBUG_REG22__TCD_EMPTY_q_MASK 0x00008000L +#define MH_DEBUG_REG22__TCD_EMPTY_q 0x00008000L +#define MH_DEBUG_REG22__TC_ROQ_EMPTY_MASK 0x00010000L +#define MH_DEBUG_REG22__TC_ROQ_EMPTY 0x00010000L +#define MH_DEBUG_REG22__MH_BUSY_d_MASK 0x00020000L +#define MH_DEBUG_REG22__MH_BUSY_d 0x00020000L +#define MH_DEBUG_REG22__ANY_CLNT_BUSY_MASK 0x00040000L +#define MH_DEBUG_REG22__ANY_CLNT_BUSY 0x00040000L +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000L +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00080000L +#define MH_DEBUG_REG22__CP_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG22__CP_SEND_q 0x00100000L +#define MH_DEBUG_REG22__CP_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG22__CP_RTR_q 0x00200000L +#define MH_DEBUG_REG22__VGT_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG22__VGT_SEND_q 0x00400000L +#define MH_DEBUG_REG22__VGT_RTR_q_MASK 0x00800000L +#define MH_DEBUG_REG22__VGT_RTR_q 0x00800000L +#define MH_DEBUG_REG22__TC_ROQ_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG22__TC_ROQ_SEND_q 0x01000000L +#define MH_DEBUG_REG22__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG22__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG22__RB_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG22__RB_SEND_q 0x04000000L +#define MH_DEBUG_REG22__RB_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG22__RB_RTR_q 0x08000000L +#define MH_DEBUG_REG22__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG22__RDC_VALID 0x10000000L +#define MH_DEBUG_REG22__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG22__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG22__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG22__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG22__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG22__BRC_VALID 0x80000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG23__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG23__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG23__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG23__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG23__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG23__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG23__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG23__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG23__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG23__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG23__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG23__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG23__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG23__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG23__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG23__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG23__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG23__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG23__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG23__ARB_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG23__ARB_QUAL 0x01000000L +#define MH_DEBUG_REG23__CP_EFF1_REQ_MASK 0x02000000L +#define MH_DEBUG_REG23__CP_EFF1_REQ 0x02000000L +#define MH_DEBUG_REG23__VGT_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG23__VGT_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG23__TC_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG23__TC_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG23__RB_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG23__RB_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK_MASK 0x20000000L +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK 0x20000000L +#define MH_DEBUG_REG23__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG23__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG23__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG23__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG24__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG24__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG24__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG24__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG24__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG24__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG24__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG24__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG24__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG24__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG24__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG24__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG24__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG24__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG24__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG24__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG24__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG24__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG24__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG24__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG24__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG24__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG24__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG24__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG24__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG24__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG24__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG24__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG24__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG24__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG24__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG25__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d_MASK 0x000001c0L +#define MH_DEBUG_REG25__LEAST_RECENT_d_MASK 0x00000e00L +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d_MASK 0x00001000L +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d 0x00001000L +#define MH_DEBUG_REG25__ARB_HOLD_MASK 0x00002000L +#define MH_DEBUG_REG25__ARB_HOLD 0x00002000L +#define MH_DEBUG_REG25__ARB_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG25__ARB_RTR_q 0x00004000L +#define MH_DEBUG_REG25__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG25__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG25__CLNT_REQ_MASK 0x000f0000L +#define MH_DEBUG_REG25__RECENT_d_0_MASK 0x00700000L +#define MH_DEBUG_REG25__RECENT_d_1_MASK 0x03800000L +#define MH_DEBUG_REG25__RECENT_d_2_MASK 0x1c000000L +#define MH_DEBUG_REG25__RECENT_d_3_MASK 0xe0000000L + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG26__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG26__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG26__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG26__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG26__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG26__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG26__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG26__TC_MH_written 0x00000800L +#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG26__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG26__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG26__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG26__WLAST_q 0x00100000L +#define MH_DEBUG_REG26__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG26__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG26__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG26__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG26__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG26__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG26__CP_MH_write 0x04000000L +#define MH_DEBUG_REG26__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG26__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG26__ARB_WINNER_MASK 0x70000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG28__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG28__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG28__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG28__TC_MH_send 0x01000000L +#define MH_DEBUG_REG28__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG28__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG28__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG28__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG28__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG28__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG28__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG28__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG28__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG29__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG29__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG29__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG29__TC_MH_send 0x01000000L +#define MH_DEBUG_REG29__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG29__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG29__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG29__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG29__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG29__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG29__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG29__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG29__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG29__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG31__TC_MH_send 0x00000001L +#define MH_DEBUG_REG31__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG31__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG31__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG31__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG31__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG31__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG31__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG32__TC_MH_send 0x00000001L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG32__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG32__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG32__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG32__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG32__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG33__TC_MH_send 0x00000001L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG33__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG33__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG33__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG33__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG33__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG34__TC_MH_send 0x00000001L +#define MH_DEBUG_REG34__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG34__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG34__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG34__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG34__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG34__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG34__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG39__ARB_WE 0x00000001L +#define MH_DEBUG_REG39__MMU_RTR_MASK 0x00000002L +#define MH_DEBUG_REG39__MMU_RTR 0x00000002L +#define MH_DEBUG_REG39__ARB_ID_q_MASK 0x0000001cL +#define MH_DEBUG_REG39__ARB_WRITE_q_MASK 0x00000020L +#define MH_DEBUG_REG39__ARB_WRITE_q 0x00000020L +#define MH_DEBUG_REG39__ARB_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG39__ARB_BLEN_q 0x00000040L +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY 0x00000080L +#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q_MASK 0x00000700L +#define MH_DEBUG_REG39__MMU_WE_MASK 0x00000800L +#define MH_DEBUG_REG39__MMU_WE 0x00000800L +#define MH_DEBUG_REG39__ARQ_RTR_MASK 0x00001000L +#define MH_DEBUG_REG39__ARQ_RTR 0x00001000L +#define MH_DEBUG_REG39__MMU_ID_MASK 0x0000e000L +#define MH_DEBUG_REG39__MMU_WRITE_MASK 0x00010000L +#define MH_DEBUG_REG39__MMU_WRITE 0x00010000L +#define MH_DEBUG_REG39__MMU_BLEN_MASK 0x00020000L +#define MH_DEBUG_REG39__MMU_BLEN 0x00020000L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG40__ARB_WE 0x00000001L +#define MH_DEBUG_REG40__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG40__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG41__MMU_WE 0x00000001L +#define MH_DEBUG_REG41__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG41__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__WDB_WE_MASK 0x00000001L +#define MH_DEBUG_REG42__WDB_WE 0x00000001L +#define MH_DEBUG_REG42__WDB_RTR_SKID_MASK 0x00000002L +#define MH_DEBUG_REG42__WDB_RTR_SKID 0x00000002L +#define MH_DEBUG_REG42__ARB_WSTRB_q_MASK 0x000003fcL +#define MH_DEBUG_REG42__ARB_WLAST_MASK 0x00000400L +#define MH_DEBUG_REG42__ARB_WLAST 0x00000400L +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY_MASK 0x00000800L +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY 0x00000800L +#define MH_DEBUG_REG42__WDB_FIFO_CNT_q_MASK 0x0001f000L +#define MH_DEBUG_REG42__WDC_WDB_RE_q_MASK 0x00020000L +#define MH_DEBUG_REG42__WDC_WDB_RE_q 0x00020000L +#define MH_DEBUG_REG42__WDB_WDC_WID_MASK 0x001c0000L +#define MH_DEBUG_REG42__WDB_WDC_WLAST_MASK 0x00200000L +#define MH_DEBUG_REG42__WDB_WDC_WLAST 0x00200000L +#define MH_DEBUG_REG42__WDB_WDC_WSTRB_MASK 0x3fc00000L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_WDATA_q_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WDATA_q_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG47__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG47__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG47__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG47__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG47__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG47__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG47__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG47__RVALID_q 0x00008000L +#define MH_DEBUG_REG47__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG47__RREADY_q 0x00010000L +#define MH_DEBUG_REG47__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG47__RLAST_q 0x00020000L +#define MH_DEBUG_REG47__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG47__BVALID_q 0x00040000L +#define MH_DEBUG_REG47__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG47__BREADY_q 0x00080000L + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG48__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG48__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG48__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG48__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG48__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG48__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG48__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG48__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG48__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG48__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG48__RDC_VALID 0x00000020L +#define MH_DEBUG_REG48__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG48__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG48__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG48__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG48__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG48__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG48__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG48__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__RF_MMU_CONFIG_q_MASK 0x00ffffffL +#define MH_DEBUG_REG50__ARB_ID_q_MASK 0x07000000L +#define MH_DEBUG_REG50__ARB_WRITE_q_MASK 0x08000000L +#define MH_DEBUG_REG50__ARB_WRITE_q 0x08000000L +#define MH_DEBUG_REG50__client_behavior_q_MASK 0x30000000L +#define MH_DEBUG_REG50__ARB_WE_MASK 0x40000000L +#define MH_DEBUG_REG50__ARB_WE 0x40000000L +#define MH_DEBUG_REG50__MMU_RTR_MASK 0x80000000L +#define MH_DEBUG_REG50__MMU_RTR 0x80000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG51__stage1_valid 0x00000001L +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG51__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG51__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG51__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG51__tag_match_q 0x00000008L +#define MH_DEBUG_REG51__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG51__tag_miss_q 0x00000010L +#define MH_DEBUG_REG51__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG51__va_in_range_q 0x00000020L +#define MH_DEBUG_REG51__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG51__MMU_MISS 0x00000040L +#define MH_DEBUG_REG51__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG51__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG51__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG51__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG51__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG51__MMU_HIT 0x00000200L +#define MH_DEBUG_REG51__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG51__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG51__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG51__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG51__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG52__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG52__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG52__MMU_WE 0x00000002L +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG52__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG52__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG52__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG52__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG52__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG52__stage1_valid 0x00000080L +#define MH_DEBUG_REG52__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG52__stage2_valid 0x00000100L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG52__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG52__tag_match_q 0x00001000L +#define MH_DEBUG_REG52__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG52__tag_miss_q 0x00002000L +#define MH_DEBUG_REG52__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG52__va_in_range_q 0x00004000L +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG52__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG53__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG53__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG53__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG53__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG53__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG53__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG54__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG54__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG54__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG54__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG54__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG54__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE_MASK 0x00000001L +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE 0x00000001L +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE_MASK 0x00000002L +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE 0x00000002L +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE_MASK 0x00000004L +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE 0x00000004L +#define RBBM_DSPLY__VSYNC_ACTIVE_MASK 0x00000008L +#define RBBM_DSPLY__VSYNC_ACTIVE 0x00000008L +#define RBBM_DSPLY__USE_DISPLAY_ID0_MASK 0x00000010L +#define RBBM_DSPLY__USE_DISPLAY_ID0 0x00000010L +#define RBBM_DSPLY__USE_DISPLAY_ID1_MASK 0x00000020L +#define RBBM_DSPLY__USE_DISPLAY_ID1 0x00000020L +#define RBBM_DSPLY__USE_DISPLAY_ID2_MASK 0x00000040L +#define RBBM_DSPLY__USE_DISPLAY_ID2 0x00000040L +#define RBBM_DSPLY__SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__SW_CNTL 0x00000080L +#define RBBM_DSPLY__NUM_BUFS_MASK 0x00000300L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__BUFFER_ID_MASK 0x00000003L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__RESERVED9_MASK 0x40000000L +#define RB_BC_CONTROL__RESERVED9 0x40000000L +#define RB_BC_CONTROL__RESERVED10_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED10 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h new file mode 100644 index 000000000000..6a229a8e79e2 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h @@ -0,0 +1,581 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x01CC +#define mmCP_IB1_BUFSZ 0x01CD +#define mmCP_IB2_BASE 0x01CE +#define mmCP_IB2_BUFSZ 0x01CF +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x045F +#define mmCP_PFP_UCODE_DATA 0x0460 +#define mmCP_PERFMON_CNTL 0x01F5 +#define mmCP_PERFCOUNTER_SELECT 0x01E6 +#define mmCP_PERFCOUNTER_LO 0x01E7 +#define mmCP_PERFCOUNTER_HI 0x01E8 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h new file mode 100644 index 000000000000..7e293b371bcd --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h @@ -0,0 +1,221 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h new file mode 100644 index 000000000000..b021d446a229 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h @@ -0,0 +1,13962 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fpos : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fpos : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fpos : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fpos : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int : 3; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 3; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int CST_0_ABS_MOD : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SST_0_ABS_MOD : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SST_0_ABS_MOD : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int CST_0_ABS_MOD : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BE_q : 8; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_BE_q : 8; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BE_q : 8; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BE_q : 8; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int CIB_MH_axi_halt_req : 1; + unsigned int MH_CIB_axi_halt_ack : 1; + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_axi_halt_ack : 1; + unsigned int CIB_MH_axi_halt_req : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int ARB_WINNER : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int EFF1_WIN : 1; + unsigned int CLNT_REQ : 4; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 4; + unsigned int EFF1_WIN : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_WINNER : 3; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID : 1; + unsigned int WDB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WDATA_q_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WDATA_q_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WDATA_q_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WDATA_q_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q : 24; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int DISPLAY_ID0_ACTIVE : 1; + unsigned int DISPLAY_ID1_ACTIVE : 1; + unsigned int DISPLAY_ID2_ACTIVE : 1; + unsigned int VSYNC_ACTIVE : 1; + unsigned int USE_DISPLAY_ID0 : 1; + unsigned int USE_DISPLAY_ID1 : 1; + unsigned int USE_DISPLAY_ID2 : 1; + unsigned int SW_CNTL : 1; + unsigned int NUM_BUFS : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int NUM_BUFS : 2; + unsigned int SW_CNTL : 1; + unsigned int USE_DISPLAY_ID2 : 1; + unsigned int USE_DISPLAY_ID1 : 1; + unsigned int USE_DISPLAY_ID0 : 1; + unsigned int VSYNC_ACTIVE : 1; + unsigned int DISPLAY_ID2_ACTIVE : 1; + unsigned int DISPLAY_ID1_ACTIVE : 1; + unsigned int DISPLAY_ID0_ACTIVE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int BUFFER_ID : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int : 15; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int : 15; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 24; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 24; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int : 8; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 8; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int : 8; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 8; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int : 28; +#else /* !defined(qLittleEndian) */ + unsigned int : 28; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int RESERVED9 : 1; + unsigned int RESERVED10 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED10 : 1; + unsigned int RESERVED9 : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h new file mode 100644 index 000000000000..2049d0f7bd14 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h @@ -0,0 +1,4078 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fpos__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fpos__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000a +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000c +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000e +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001a + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BE_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x0000000f +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x00000013 +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x00000014 +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x00000015 +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000017 +#define MH_DEBUG_REG01__RB_BE_q__SHIFT 0x00000018 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000011 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG08__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG08__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG08__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG09__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG09__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG11__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG11__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG12__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG12__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG14__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG17__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG17__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG17__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG17__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG17__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG17__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG17__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG17__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG17__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG17__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG17__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG17__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG17__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG17__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG17__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG17__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG17__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG17__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG18__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG18__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG18__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG18__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG18__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG18__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG18__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG18__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG18__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG18__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG18__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG18__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG18__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG18__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG18__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG19__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG19__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG20__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG20__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG20__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG20__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req__SHIFT 0x00000000 +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack__SHIFT 0x00000001 +#define MH_DEBUG_REG22__MH_RBBM_busy__SHIFT 0x00000002 +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int__SHIFT 0x00000004 +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000005 +#define MH_DEBUG_REG22__GAT_CLK_ENA__SHIFT 0x00000006 +#define MH_DEBUG_REG22__AXI_RDY_ENA__SHIFT 0x00000007 +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override__SHIFT 0x00000008 +#define MH_DEBUG_REG22__CNT_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__TCD_EMPTY_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__TC_ROQ_EMPTY__SHIFT 0x00000010 +#define MH_DEBUG_REG22__MH_BUSY_d__SHIFT 0x00000011 +#define MH_DEBUG_REG22__ANY_CLNT_BUSY__SHIFT 0x00000012 +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000013 +#define MH_DEBUG_REG22__CP_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG22__CP_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG22__VGT_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG22__VGT_RTR_q__SHIFT 0x00000017 +#define MH_DEBUG_REG22__TC_ROQ_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG22__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG22__RB_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG22__RB_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG22__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG22__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG22__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG23__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG23__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG23__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG23__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG23__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG23__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG23__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG23__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG23__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG23__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG23__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG23__ARB_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG23__CP_EFF1_REQ__SHIFT 0x00000019 +#define MH_DEBUG_REG23__VGT_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG23__TC_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG23__RB_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK__SHIFT 0x0000001d +#define MH_DEBUG_REG23__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG23__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG24__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG24__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG24__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG24__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG24__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG24__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG24__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG24__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG24__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG24__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG24__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG24__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG24__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG24__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG24__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG24__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG25__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d__SHIFT 0x00000006 +#define MH_DEBUG_REG25__LEAST_RECENT_d__SHIFT 0x00000009 +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d__SHIFT 0x0000000c +#define MH_DEBUG_REG25__ARB_HOLD__SHIFT 0x0000000d +#define MH_DEBUG_REG25__ARB_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG25__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG25__CLNT_REQ__SHIFT 0x00000010 +#define MH_DEBUG_REG25__RECENT_d_0__SHIFT 0x00000014 +#define MH_DEBUG_REG25__RECENT_d_1__SHIFT 0x00000017 +#define MH_DEBUG_REG25__RECENT_d_2__SHIFT 0x0000001a +#define MH_DEBUG_REG25__RECENT_d_3__SHIFT 0x0000001d + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG26__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG26__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG26__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG26__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG26__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG26__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG26__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG26__ARB_WINNER__SHIFT 0x0000001c + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG28__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG28__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG28__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG28__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG28__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG28__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG29__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG29__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG29__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG29__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG29__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG29__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG29__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG29__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG31__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG31__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG31__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG31__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG32__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG32__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG32__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG33__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG33__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG33__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG34__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG34__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG34__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG34__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG39__MMU_RTR__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ARB_ID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ARB_WRITE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG39__ARB_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q__SHIFT 0x00000008 +#define MH_DEBUG_REG39__MMU_WE__SHIFT 0x0000000b +#define MH_DEBUG_REG39__ARQ_RTR__SHIFT 0x0000000c +#define MH_DEBUG_REG39__MMU_ID__SHIFT 0x0000000d +#define MH_DEBUG_REG39__MMU_WRITE__SHIFT 0x00000010 +#define MH_DEBUG_REG39__MMU_BLEN__SHIFT 0x00000011 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG40__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG41__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG41__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__WDB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG42__WDB_RTR_SKID__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ARB_WSTRB_q__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ARB_WLAST__SHIFT 0x0000000a +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY__SHIFT 0x0000000b +#define MH_DEBUG_REG42__WDB_FIFO_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG42__WDC_WDB_RE_q__SHIFT 0x00000011 +#define MH_DEBUG_REG42__WDB_WDC_WID__SHIFT 0x00000012 +#define MH_DEBUG_REG42__WDB_WDC_WLAST__SHIFT 0x00000015 +#define MH_DEBUG_REG42__WDB_WDC_WSTRB__SHIFT 0x00000016 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_WDATA_q_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WDATA_q_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG47__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG47__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG47__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG47__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG47__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG47__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG47__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG47__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG48__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG48__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG48__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG48__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG48__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG48__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG48__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG48__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG48__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG48__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__RF_MMU_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG50__ARB_ID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG50__ARB_WRITE_q__SHIFT 0x0000001b +#define MH_DEBUG_REG50__client_behavior_q__SHIFT 0x0000001c +#define MH_DEBUG_REG50__ARB_WE__SHIFT 0x0000001e +#define MH_DEBUG_REG50__MMU_RTR__SHIFT 0x0000001f + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG51__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG51__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG51__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG51__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG51__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG51__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG51__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG51__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG51__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG51__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG51__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG52__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG52__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG52__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG52__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG52__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG52__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG52__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG52__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG52__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG53__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG53__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG53__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG53__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG54__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG54__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG54__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG54__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE__SHIFT 0x00000000 +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE__SHIFT 0x00000001 +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE__SHIFT 0x00000002 +#define RBBM_DSPLY__VSYNC_ACTIVE__SHIFT 0x00000003 +#define RBBM_DSPLY__USE_DISPLAY_ID0__SHIFT 0x00000004 +#define RBBM_DSPLY__USE_DISPLAY_ID1__SHIFT 0x00000005 +#define RBBM_DSPLY__USE_DISPLAY_ID2__SHIFT 0x00000006 +#define RBBM_DSPLY__SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__NUM_BUFS__SHIFT 0x00000008 + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__BUFFER_ID__SHIFT 0x00000000 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__RESERVED9__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED10__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h new file mode 100644 index 000000000000..e8402cda4463 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h @@ -0,0 +1,51151 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int : 8; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 8; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int : 8; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 8; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE 1 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE 1 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE 1 +#define RBBM_DSPLY_VSYNC_ACTIVE_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID0_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID1_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID2_SIZE 1 +#define RBBM_DSPLY_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT 0 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT 1 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT 2 +#define RBBM_DSPLY_VSYNC_ACTIVE_SHIFT 3 +#define RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT 4 +#define RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT 5 +#define RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT 6 +#define RBBM_DSPLY_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_NUM_BUFS_SHIFT 8 + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK 0x00000001 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK 0x00000002 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK 0x00000004 +#define RBBM_DSPLY_VSYNC_ACTIVE_MASK 0x00000008 +#define RBBM_DSPLY_USE_DISPLAY_ID0_MASK 0x00000010 +#define RBBM_DSPLY_USE_DISPLAY_ID1_MASK 0x00000020 +#define RBBM_DSPLY_USE_DISPLAY_ID2_MASK 0x00000040 +#define RBBM_DSPLY_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_NUM_BUFS_MASK 0x00000300 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK | \ + RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK | \ + RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK | \ + RBBM_DSPLY_VSYNC_ACTIVE_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID0_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID1_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID2_MASK | \ + RBBM_DSPLY_SW_CNTL_MASK | \ + RBBM_DSPLY_NUM_BUFS_MASK) + +#define RBBM_DSPLY(display_id0_active, display_id1_active, display_id2_active, vsync_active, use_display_id0, use_display_id1, use_display_id2, sw_cntl, num_bufs) \ + ((display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) | \ + (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) | \ + (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) | \ + (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) | \ + (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) | \ + (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) | \ + (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) | \ + (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) | \ + (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_DISPLAY_ID0_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_DISPLAY_ID1_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_DISPLAY_ID2_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_VSYNC_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_VSYNC_ACTIVE_MASK) >> RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID0_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID1_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID2_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) +#define RBBM_DSPLY_GET_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SW_CNTL_MASK) >> RBBM_DSPLY_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_NUM_BUFS_MASK) >> RBBM_DSPLY_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_DISPLAY_ID0_ACTIVE(rbbm_dsply_reg, display_id0_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) | (display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_DISPLAY_ID1_ACTIVE(rbbm_dsply_reg, display_id1_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) | (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_DISPLAY_ID2_ACTIVE(rbbm_dsply_reg, display_id2_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) | (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_VSYNC_ACTIVE(rbbm_dsply_reg, vsync_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_VSYNC_ACTIVE_MASK) | (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID0(rbbm_dsply_reg, use_display_id0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID0_MASK) | (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID1(rbbm_dsply_reg, use_display_id1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID1_MASK) | (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID2(rbbm_dsply_reg, use_display_id2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID2_MASK) | (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) +#define RBBM_DSPLY_SET_SW_CNTL(rbbm_dsply_reg, sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SW_CNTL_MASK) | (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_NUM_BUFS(rbbm_dsply_reg, num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_NUM_BUFS_MASK) | (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int display_id0_active : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE; + unsigned int display_id1_active : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE; + unsigned int display_id2_active : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE; + unsigned int vsync_active : RBBM_DSPLY_VSYNC_ACTIVE_SIZE; + unsigned int use_display_id0 : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE; + unsigned int use_display_id1 : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE; + unsigned int use_display_id2 : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE; + unsigned int sw_cntl : RBBM_DSPLY_SW_CNTL_SIZE; + unsigned int num_bufs : RBBM_DSPLY_NUM_BUFS_SIZE; + unsigned int : 22; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int : 22; + unsigned int num_bufs : RBBM_DSPLY_NUM_BUFS_SIZE; + unsigned int sw_cntl : RBBM_DSPLY_SW_CNTL_SIZE; + unsigned int use_display_id2 : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE; + unsigned int use_display_id1 : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE; + unsigned int use_display_id0 : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE; + unsigned int vsync_active : RBBM_DSPLY_VSYNC_ACTIVE_SIZE; + unsigned int display_id2_active : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE; + unsigned int display_id1_active : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE; + unsigned int display_id0_active : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_BUFFER_ID_SHIFT 0 + +#define RBBM_RENDER_LATEST_BUFFER_ID_MASK 0x00000003 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(buffer_id) \ + ((buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_BUFFER_ID(rbbm_render_latest_reg, buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_BUFFER_ID_MASK) | (buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int buffer_id : RBBM_RENDER_LATEST_BUFFER_ID_SIZE; + unsigned int : 30; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 30; + unsigned int buffer_id : RBBM_RENDER_LATEST_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int : 15; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int : 15; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 24; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 24; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int : 6; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 6; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 21; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 21; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 10 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 12 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 13 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 14 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 16 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 18 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 20 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 22 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 24 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 26 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000400 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00001000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00004000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x04000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int : 5; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 5; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BE_q_SIZE 8 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_RB_BE_q_SIZE 8 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BE_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 14 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 15 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 16 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 17 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 18 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 19 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 20 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 21 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 22 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 23 +#define MH_DEBUG_REG01_RB_BE_q_SHIFT 24 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BE_q_MASK 0x00003fc0 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00004000 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00008000 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00010000 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00020000 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00080000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00100000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00200000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00800000 +#define MH_DEBUG_REG01_RB_BE_q_MASK 0xff000000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BE_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_RB_BE_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_be_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, rb_be_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BE_q_MASK) >> MH_DEBUG_REG01_CP_BE_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_BE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_BE_q_MASK) >> MH_DEBUG_REG01_RB_BE_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BE_q(mh_debug_reg01_reg, cp_be_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BE_q_MASK) | (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_BE_q(mh_debug_reg01_reg, rb_be_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_BE_q_MASK) | (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_be_q : MH_DEBUG_REG01_CP_BE_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_be_q : MH_DEBUG_REG01_RB_BE_q_SIZE; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int rb_be_q : MH_DEBUG_REG01_RB_BE_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_be_q : MH_DEBUG_REG01_CP_BE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 17 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x0001c000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x00060000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 13; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 13; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG08_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG08_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG08_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG08_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG08_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG08_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG08_VGT_MH_send_MASK | \ + MH_DEBUG_REG08_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG08(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG08_GET_ALWAYS_ZERO(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_send(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_send_MASK) >> MH_DEBUG_REG08_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_tagbe(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_ad_31_5(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG08_SET_ALWAYS_ZERO(mh_debug_reg08_reg, always_zero) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_send(mh_debug_reg08_reg, vgt_mh_send) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_tagbe(mh_debug_reg08_reg, vgt_mh_tagbe) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_ad_31_5(mh_debug_reg08_reg, vgt_mh_ad_31_5) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int always_zero : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG08_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG08_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG09_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG09_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG09_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG09_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG09_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_TC_MH_send_MASK | \ + MH_DEBUG_REG09_TC_MH_mask_MASK | \ + MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_send_MASK) >> MH_DEBUG_REG09_TC_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_mask(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_mask_MASK) >> MH_DEBUG_REG09_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_addr_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_send(mh_debug_reg09_reg, tc_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_mask(mh_debug_reg09_reg, tc_mh_mask) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_addr_31_5(mh_debug_reg09_reg, tc_mh_addr_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG09_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG09_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG09_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG09_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG10_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG10_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_TC_MH_info_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK) + +#define MH_DEBUG_REG10(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG10_GET_TC_MH_info(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_info_MASK) >> MH_DEBUG_REG10_TC_MH_info_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG10_SET_TC_MH_info(mh_debug_reg10_reg, tc_mh_info) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_info : MH_DEBUG_REG10_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG10_TC_MH_info_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG11_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG11_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG11_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG11_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG11_TC_MH_written_MASK) + +#define MH_DEBUG_REG11(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG11_GET_MH_TC_mcinfo(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG11_GET_MH_TC_mcinfo_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_written(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_written_MASK) >> MH_DEBUG_REG11_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG11_SET_MH_TC_mcinfo(mh_debug_reg11_reg, mh_tc_mcinfo) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG11_SET_MH_TC_mcinfo_send(mh_debug_reg11_reg, mh_tc_mcinfo_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_written(mh_debug_reg11_reg, tc_mh_written) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG11_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG11_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG12_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG12_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG12_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG12_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG12_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG12_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG12_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG12(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG12_GET_ALWAYS_ZERO(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_SEND(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_MASK(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_ADDR_31_5(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG12_SET_ALWAYS_ZERO(mh_debug_reg12_reg, always_zero) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_SEND(mh_debug_reg12_reg, tc_roq_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_MASK(mh_debug_reg12_reg, tc_roq_mask) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_ADDR_31_5(mh_debug_reg12_reg, tc_roq_addr_31_5) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int always_zero : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG13_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG13(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG13_GET_TC_ROQ_INFO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG13_SET_TC_ROQ_INFO(mh_debug_reg13_reg, tc_roq_info) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_info : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG14_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG14_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG14_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG14_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG14_RB_MH_send_MASK | \ + MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG14(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG14_GET_ALWAYS_ZERO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG14_GET_RB_MH_send(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_send_MASK) >> MH_DEBUG_REG14_RB_MH_send_SHIFT) +#define MH_DEBUG_REG14_GET_RB_MH_addr_31_5(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG14_SET_ALWAYS_ZERO(mh_debug_reg14_reg, always_zero) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG14_SET_RB_MH_send(mh_debug_reg14_reg, rb_mh_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) +#define MH_DEBUG_REG14_SET_RB_MH_addr_31_5(mh_debug_reg14_reg, rb_mh_addr_31_5) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int always_zero : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG14_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG14_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG15_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG15(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG15_GET_RB_MH_data_31_0(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG15_SET_RB_MH_data_31_0(mh_debug_reg15_reg, rb_mh_data_31_0) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_63_32(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_63_32(mh_debug_reg16_reg, rb_mh_data_63_32) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_AVALID_q_SIZE 1 +#define MH_DEBUG_REG17_AREADY_q_SIZE 1 +#define MH_DEBUG_REG17_AID_q_SIZE 3 +#define MH_DEBUG_REG17_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG17_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG17_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG17_ARID_q_SIZE 3 +#define MH_DEBUG_REG17_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG17_RVALID_q_SIZE 1 +#define MH_DEBUG_REG17_RREADY_q_SIZE 1 +#define MH_DEBUG_REG17_RLAST_q_SIZE 1 +#define MH_DEBUG_REG17_RID_q_SIZE 3 +#define MH_DEBUG_REG17_WVALID_q_SIZE 1 +#define MH_DEBUG_REG17_WREADY_q_SIZE 1 +#define MH_DEBUG_REG17_WLAST_q_SIZE 1 +#define MH_DEBUG_REG17_WID_q_SIZE 3 +#define MH_DEBUG_REG17_BVALID_q_SIZE 1 +#define MH_DEBUG_REG17_BREADY_q_SIZE 1 +#define MH_DEBUG_REG17_BID_q_SIZE 3 + +#define MH_DEBUG_REG17_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG17_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG17_AID_q_SHIFT 2 +#define MH_DEBUG_REG17_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG17_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG17_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG17_ARID_q_SHIFT 10 +#define MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG17_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG17_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG17_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG17_RID_q_SHIFT 18 +#define MH_DEBUG_REG17_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG17_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG17_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG17_WID_q_SHIFT 24 +#define MH_DEBUG_REG17_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG17_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG17_BID_q_SHIFT 29 + +#define MH_DEBUG_REG17_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG17_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG17_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG17_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG17_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG17_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG17_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG17_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG17_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG17_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG17_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG17_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG17_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG17_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG17_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG17_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG17_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG17_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG17_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_AVALID_q_MASK | \ + MH_DEBUG_REG17_AREADY_q_MASK | \ + MH_DEBUG_REG17_AID_q_MASK | \ + MH_DEBUG_REG17_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG17_ARVALID_q_MASK | \ + MH_DEBUG_REG17_ARREADY_q_MASK | \ + MH_DEBUG_REG17_ARID_q_MASK | \ + MH_DEBUG_REG17_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG17_RVALID_q_MASK | \ + MH_DEBUG_REG17_RREADY_q_MASK | \ + MH_DEBUG_REG17_RLAST_q_MASK | \ + MH_DEBUG_REG17_RID_q_MASK | \ + MH_DEBUG_REG17_WVALID_q_MASK | \ + MH_DEBUG_REG17_WREADY_q_MASK | \ + MH_DEBUG_REG17_WLAST_q_MASK | \ + MH_DEBUG_REG17_WID_q_MASK | \ + MH_DEBUG_REG17_BVALID_q_MASK | \ + MH_DEBUG_REG17_BREADY_q_MASK | \ + MH_DEBUG_REG17_BID_q_MASK) + +#define MH_DEBUG_REG17(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG17_BID_q_SHIFT)) + +#define MH_DEBUG_REG17_GET_AVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AVALID_q_MASK) >> MH_DEBUG_REG17_AVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_AREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AREADY_q_MASK) >> MH_DEBUG_REG17_AREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_AID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AID_q_MASK) >> MH_DEBUG_REG17_AID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ALEN_q_2_0(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ALEN_q_2_0_MASK) >> MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG17_GET_ARVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARVALID_q_MASK) >> MH_DEBUG_REG17_ARVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARREADY_q_MASK) >> MH_DEBUG_REG17_ARREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARID_q_MASK) >> MH_DEBUG_REG17_ARID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARLEN_q_1_0(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG17_GET_RVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RVALID_q_MASK) >> MH_DEBUG_REG17_RVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_RREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RREADY_q_MASK) >> MH_DEBUG_REG17_RREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_RLAST_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RLAST_q_MASK) >> MH_DEBUG_REG17_RLAST_q_SHIFT) +#define MH_DEBUG_REG17_GET_RID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RID_q_MASK) >> MH_DEBUG_REG17_RID_q_SHIFT) +#define MH_DEBUG_REG17_GET_WVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WVALID_q_MASK) >> MH_DEBUG_REG17_WVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_WREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WREADY_q_MASK) >> MH_DEBUG_REG17_WREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_WLAST_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WLAST_q_MASK) >> MH_DEBUG_REG17_WLAST_q_SHIFT) +#define MH_DEBUG_REG17_GET_WID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WID_q_MASK) >> MH_DEBUG_REG17_WID_q_SHIFT) +#define MH_DEBUG_REG17_GET_BVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BVALID_q_MASK) >> MH_DEBUG_REG17_BVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_BREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BREADY_q_MASK) >> MH_DEBUG_REG17_BREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_BID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BID_q_MASK) >> MH_DEBUG_REG17_BID_q_SHIFT) + +#define MH_DEBUG_REG17_SET_AVALID_q(mh_debug_reg17_reg, avalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_AREADY_q(mh_debug_reg17_reg, aready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_AID_q(mh_debug_reg17_reg, aid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AID_q_MASK) | (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ALEN_q_2_0(mh_debug_reg17_reg, alen_q_2_0) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG17_SET_ARVALID_q(mh_debug_reg17_reg, arvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARREADY_q(mh_debug_reg17_reg, arready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARID_q(mh_debug_reg17_reg, arid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARID_q_MASK) | (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARLEN_q_1_0(mh_debug_reg17_reg, arlen_q_1_0) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG17_SET_RVALID_q(mh_debug_reg17_reg, rvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_RREADY_q(mh_debug_reg17_reg, rready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_RLAST_q(mh_debug_reg17_reg, rlast_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) +#define MH_DEBUG_REG17_SET_RID_q(mh_debug_reg17_reg, rid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RID_q_MASK) | (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) +#define MH_DEBUG_REG17_SET_WVALID_q(mh_debug_reg17_reg, wvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_WREADY_q(mh_debug_reg17_reg, wready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_WLAST_q(mh_debug_reg17_reg, wlast_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) +#define MH_DEBUG_REG17_SET_WID_q(mh_debug_reg17_reg, wid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WID_q_MASK) | (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) +#define MH_DEBUG_REG17_SET_BVALID_q(mh_debug_reg17_reg, bvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_BREADY_q(mh_debug_reg17_reg, bready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_BID_q(mh_debug_reg17_reg, bid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BID_q_MASK) | (bid_q << MH_DEBUG_REG17_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int avalid_q : MH_DEBUG_REG17_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG17_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG17_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG17_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG17_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG17_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG17_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG17_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG17_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG17_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG17_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG17_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG17_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG17_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG17_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG17_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG17_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG17_BID_q_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int bid_q : MH_DEBUG_REG17_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG17_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG17_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG17_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG17_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG17_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG17_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG17_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG17_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG17_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG17_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG17_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG17_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG17_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG17_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG17_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG17_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG17_AVALID_q_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_AVALID_q_SIZE 1 +#define MH_DEBUG_REG18_AREADY_q_SIZE 1 +#define MH_DEBUG_REG18_AID_q_SIZE 3 +#define MH_DEBUG_REG18_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG18_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG18_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG18_ARID_q_SIZE 3 +#define MH_DEBUG_REG18_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG18_WVALID_q_SIZE 1 +#define MH_DEBUG_REG18_WREADY_q_SIZE 1 +#define MH_DEBUG_REG18_WLAST_q_SIZE 1 +#define MH_DEBUG_REG18_WID_q_SIZE 3 +#define MH_DEBUG_REG18_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG18_BVALID_q_SIZE 1 +#define MH_DEBUG_REG18_BREADY_q_SIZE 1 +#define MH_DEBUG_REG18_BID_q_SIZE 3 + +#define MH_DEBUG_REG18_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG18_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG18_AID_q_SHIFT 2 +#define MH_DEBUG_REG18_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG18_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG18_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG18_ARID_q_SHIFT 9 +#define MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG18_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG18_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG18_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG18_WID_q_SHIFT 16 +#define MH_DEBUG_REG18_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG18_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG18_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG18_BID_q_SHIFT 29 + +#define MH_DEBUG_REG18_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG18_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG18_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG18_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG18_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG18_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG18_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG18_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG18_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG18_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG18_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG18_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG18_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG18_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG18_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG18_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_AVALID_q_MASK | \ + MH_DEBUG_REG18_AREADY_q_MASK | \ + MH_DEBUG_REG18_AID_q_MASK | \ + MH_DEBUG_REG18_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG18_ARVALID_q_MASK | \ + MH_DEBUG_REG18_ARREADY_q_MASK | \ + MH_DEBUG_REG18_ARID_q_MASK | \ + MH_DEBUG_REG18_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG18_WVALID_q_MASK | \ + MH_DEBUG_REG18_WREADY_q_MASK | \ + MH_DEBUG_REG18_WLAST_q_MASK | \ + MH_DEBUG_REG18_WID_q_MASK | \ + MH_DEBUG_REG18_WSTRB_q_MASK | \ + MH_DEBUG_REG18_BVALID_q_MASK | \ + MH_DEBUG_REG18_BREADY_q_MASK | \ + MH_DEBUG_REG18_BID_q_MASK) + +#define MH_DEBUG_REG18(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG18_BID_q_SHIFT)) + +#define MH_DEBUG_REG18_GET_AVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AVALID_q_MASK) >> MH_DEBUG_REG18_AVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_AREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AREADY_q_MASK) >> MH_DEBUG_REG18_AREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_AID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AID_q_MASK) >> MH_DEBUG_REG18_AID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ALEN_q_1_0(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALEN_q_1_0_MASK) >> MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG18_GET_ARVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARVALID_q_MASK) >> MH_DEBUG_REG18_ARVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARREADY_q_MASK) >> MH_DEBUG_REG18_ARREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARID_q_MASK) >> MH_DEBUG_REG18_ARID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARLEN_q_1_1(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG18_GET_WVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WVALID_q_MASK) >> MH_DEBUG_REG18_WVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_WREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WREADY_q_MASK) >> MH_DEBUG_REG18_WREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_WLAST_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WLAST_q_MASK) >> MH_DEBUG_REG18_WLAST_q_SHIFT) +#define MH_DEBUG_REG18_GET_WID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WID_q_MASK) >> MH_DEBUG_REG18_WID_q_SHIFT) +#define MH_DEBUG_REG18_GET_WSTRB_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WSTRB_q_MASK) >> MH_DEBUG_REG18_WSTRB_q_SHIFT) +#define MH_DEBUG_REG18_GET_BVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BVALID_q_MASK) >> MH_DEBUG_REG18_BVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_BREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BREADY_q_MASK) >> MH_DEBUG_REG18_BREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_BID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BID_q_MASK) >> MH_DEBUG_REG18_BID_q_SHIFT) + +#define MH_DEBUG_REG18_SET_AVALID_q(mh_debug_reg18_reg, avalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_AREADY_q(mh_debug_reg18_reg, aready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_AID_q(mh_debug_reg18_reg, aid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AID_q_MASK) | (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ALEN_q_1_0(mh_debug_reg18_reg, alen_q_1_0) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG18_SET_ARVALID_q(mh_debug_reg18_reg, arvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARREADY_q(mh_debug_reg18_reg, arready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARID_q(mh_debug_reg18_reg, arid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARID_q_MASK) | (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARLEN_q_1_1(mh_debug_reg18_reg, arlen_q_1_1) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG18_SET_WVALID_q(mh_debug_reg18_reg, wvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_WREADY_q(mh_debug_reg18_reg, wready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_WLAST_q(mh_debug_reg18_reg, wlast_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) +#define MH_DEBUG_REG18_SET_WID_q(mh_debug_reg18_reg, wid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WID_q_MASK) | (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) +#define MH_DEBUG_REG18_SET_WSTRB_q(mh_debug_reg18_reg, wstrb_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) +#define MH_DEBUG_REG18_SET_BVALID_q(mh_debug_reg18_reg, bvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_BREADY_q(mh_debug_reg18_reg, bready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_BID_q(mh_debug_reg18_reg, bid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BID_q_MASK) | (bid_q << MH_DEBUG_REG18_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int avalid_q : MH_DEBUG_REG18_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG18_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG18_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG18_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG18_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG18_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG18_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG18_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG18_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG18_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG18_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG18_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG18_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG18_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG18_BID_q_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int bid_q : MH_DEBUG_REG18_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG18_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG18_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG18_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG18_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG18_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG18_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG18_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG18_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG18_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG18_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG18_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG18_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG18_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG18_AVALID_q_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG19_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG19_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG19_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG19_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG19(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG19_GET_ARC_CTRL_RE_q(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG19_GET_CTRL_ARC_ID(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG19_GET_CTRL_ARC_PAD(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG19_SET_ARC_CTRL_RE_q(mh_debug_reg19_reg, arc_ctrl_re_q) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG19_SET_CTRL_ARC_ID(mh_debug_reg19_reg, ctrl_arc_id) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG19_SET_CTRL_ARC_PAD(mh_debug_reg19_reg, ctrl_arc_pad) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG20_REG_A_SIZE 14 +#define MH_DEBUG_REG20_REG_RE_SIZE 1 +#define MH_DEBUG_REG20_REG_WE_SIZE 1 +#define MH_DEBUG_REG20_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG20_REG_A_SHIFT 2 +#define MH_DEBUG_REG20_REG_RE_SHIFT 16 +#define MH_DEBUG_REG20_REG_WE_SHIFT 17 +#define MH_DEBUG_REG20_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG20_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG20_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG20_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG20_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG20_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG20_REG_A_MASK | \ + MH_DEBUG_REG20_REG_RE_MASK | \ + MH_DEBUG_REG20_REG_WE_MASK | \ + MH_DEBUG_REG20_BLOCK_RS_MASK) + +#define MH_DEBUG_REG20(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG20_GET_ALWAYS_ZERO(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG20_GET_REG_A(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_A_MASK) >> MH_DEBUG_REG20_REG_A_SHIFT) +#define MH_DEBUG_REG20_GET_REG_RE(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_RE_MASK) >> MH_DEBUG_REG20_REG_RE_SHIFT) +#define MH_DEBUG_REG20_GET_REG_WE(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_WE_MASK) >> MH_DEBUG_REG20_REG_WE_SHIFT) +#define MH_DEBUG_REG20_GET_BLOCK_RS(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_BLOCK_RS_MASK) >> MH_DEBUG_REG20_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG20_SET_ALWAYS_ZERO(mh_debug_reg20_reg, always_zero) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG20_SET_REG_A(mh_debug_reg20_reg, reg_a) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_A_MASK) | (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) +#define MH_DEBUG_REG20_SET_REG_RE(mh_debug_reg20_reg, reg_re) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_RE_MASK) | (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) +#define MH_DEBUG_REG20_SET_REG_WE(mh_debug_reg20_reg, reg_we) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_WE_MASK) | (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) +#define MH_DEBUG_REG20_SET_BLOCK_RS(mh_debug_reg20_reg, block_rs) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int always_zero : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG20_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG20_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG20_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG20_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG20_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG20_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG20_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG20_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_REG_WD_SIZE 32 + +#define MH_DEBUG_REG21_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG21_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_REG_WD_MASK) + +#define MH_DEBUG_REG21(reg_wd) \ + ((reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT)) + +#define MH_DEBUG_REG21_GET_REG_WD(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_REG_WD_MASK) >> MH_DEBUG_REG21_REG_WD_SHIFT) + +#define MH_DEBUG_REG21_SET_REG_WD(mh_debug_reg21_reg, reg_wd) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int reg_wd : MH_DEBUG_REG21_REG_WD_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int reg_wd : MH_DEBUG_REG21_REG_WD_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE 1 +#define MH_DEBUG_REG22_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG22_AXI_RDY_ENA_SIZE 1 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG22_CNT_q_SIZE 6 +#define MH_DEBUG_REG22_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG22_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG22_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG22_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG22_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG22_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT 0 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT 1 +#define MH_DEBUG_REG22_MH_RBBM_busy_SHIFT 2 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT 4 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT 5 +#define MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT 6 +#define MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT 7 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT 8 +#define MH_DEBUG_REG22_CNT_q_SHIFT 9 +#define MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT 15 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT 16 +#define MH_DEBUG_REG22_MH_BUSY_d_SHIFT 17 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT 18 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 19 +#define MH_DEBUG_REG22_CP_SEND_q_SHIFT 20 +#define MH_DEBUG_REG22_CP_RTR_q_SHIFT 21 +#define MH_DEBUG_REG22_VGT_SEND_q_SHIFT 22 +#define MH_DEBUG_REG22_VGT_RTR_q_SHIFT 23 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT 24 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG22_RB_SEND_q_SHIFT 26 +#define MH_DEBUG_REG22_RB_RTR_q_SHIFT 27 +#define MH_DEBUG_REG22_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG22_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG22_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG22_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK 0x00000001 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK 0x00000002 +#define MH_DEBUG_REG22_MH_RBBM_busy_MASK 0x00000004 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK 0x00000010 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK 0x00000020 +#define MH_DEBUG_REG22_GAT_CLK_ENA_MASK 0x00000040 +#define MH_DEBUG_REG22_AXI_RDY_ENA_MASK 0x00000080 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK 0x00000100 +#define MH_DEBUG_REG22_CNT_q_MASK 0x00007e00 +#define MH_DEBUG_REG22_TCD_EMPTY_q_MASK 0x00008000 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK 0x00010000 +#define MH_DEBUG_REG22_MH_BUSY_d_MASK 0x00020000 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK 0x00040000 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000 +#define MH_DEBUG_REG22_CP_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG22_CP_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG22_VGT_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG22_VGT_RTR_q_MASK 0x00800000 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG22_RB_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG22_RB_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG22_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG22_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG22_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG22_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK | \ + MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK | \ + MH_DEBUG_REG22_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG22_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG22_AXI_RDY_ENA_MASK | \ + MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG22_CNT_q_MASK | \ + MH_DEBUG_REG22_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG22_MH_BUSY_d_MASK | \ + MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG22_CP_SEND_q_MASK | \ + MH_DEBUG_REG22_CP_RTR_q_MASK | \ + MH_DEBUG_REG22_VGT_SEND_q_MASK | \ + MH_DEBUG_REG22_VGT_RTR_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG22_RB_SEND_q_MASK | \ + MH_DEBUG_REG22_RB_RTR_q_MASK | \ + MH_DEBUG_REG22_RDC_VALID_MASK | \ + MH_DEBUG_REG22_RDC_RLAST_MASK | \ + MH_DEBUG_REG22_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG22_BRC_VALID_MASK) + +#define MH_DEBUG_REG22(cib_mh_axi_halt_req, mh_cib_axi_halt_ack, mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, axi_rdy_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_q, rb_send_q, rb_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) | \ + (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) | \ + (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG22_GET_CIB_MH_axi_halt_req(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) >> MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_axi_halt_ack(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) >> MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) +#define MH_DEBUG_REG22_GET_MH_RBBM_busy(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_RBBM_busy_MASK) >> MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_mh_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_GAT_CLK_ENA(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG22_GET_AXI_RDY_ENA(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) +#define MH_DEBUG_REG22_GET_RBBM_MH_clk_en_override(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG22_GET_CNT_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CNT_q_MASK) >> MH_DEBUG_REG22_CNT_q_SHIFT) +#define MH_DEBUG_REG22_GET_TCD_EMPTY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_EMPTY(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG22_GET_MH_BUSY_d(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_BUSY_d_MASK) >> MH_DEBUG_REG22_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG22_GET_ANY_CLNT_BUSY(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG22_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG22_GET_CP_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CP_SEND_q_MASK) >> MH_DEBUG_REG22_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_CP_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CP_RTR_q_MASK) >> MH_DEBUG_REG22_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_VGT_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_SEND_q_MASK) >> MH_DEBUG_REG22_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_VGT_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_RTR_q_MASK) >> MH_DEBUG_REG22_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_RB_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RB_SEND_q_MASK) >> MH_DEBUG_REG22_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_RB_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RB_RTR_q_MASK) >> MH_DEBUG_REG22_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_RDC_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_VALID_MASK) >> MH_DEBUG_REG22_RDC_VALID_SHIFT) +#define MH_DEBUG_REG22_GET_RDC_RLAST(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_RLAST_MASK) >> MH_DEBUG_REG22_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG22_GET_TLBMISS_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TLBMISS_VALID_MASK) >> MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG22_GET_BRC_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BRC_VALID_MASK) >> MH_DEBUG_REG22_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG22_SET_CIB_MH_axi_halt_req(mh_debug_reg22_reg, cib_mh_axi_halt_req) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) | (cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_axi_halt_ack(mh_debug_reg22_reg, mh_cib_axi_halt_ack) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) | (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) +#define MH_DEBUG_REG22_SET_MH_RBBM_busy(mh_debug_reg22_reg, mh_rbbm_busy) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_mh_clk_en_int(mh_debug_reg22_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg22_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_GAT_CLK_ENA(mh_debug_reg22_reg, gat_clk_ena) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG22_SET_AXI_RDY_ENA(mh_debug_reg22_reg, axi_rdy_ena) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) +#define MH_DEBUG_REG22_SET_RBBM_MH_clk_en_override(mh_debug_reg22_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG22_SET_CNT_q(mh_debug_reg22_reg, cnt_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) +#define MH_DEBUG_REG22_SET_TCD_EMPTY_q(mh_debug_reg22_reg, tcd_empty_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_EMPTY(mh_debug_reg22_reg, tc_roq_empty) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG22_SET_MH_BUSY_d(mh_debug_reg22_reg, mh_busy_d) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG22_SET_ANY_CLNT_BUSY(mh_debug_reg22_reg, any_clnt_busy) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG22_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG22_SET_CP_SEND_q(mh_debug_reg22_reg, cp_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_CP_RTR_q(mh_debug_reg22_reg, cp_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_VGT_SEND_q(mh_debug_reg22_reg, vgt_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_VGT_RTR_q(mh_debug_reg22_reg, vgt_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_SEND_q(mh_debug_reg22_reg, tc_roq_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_RTR_q(mh_debug_reg22_reg, tc_roq_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_RB_SEND_q(mh_debug_reg22_reg, rb_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_RB_RTR_q(mh_debug_reg22_reg, rb_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_RDC_VALID(mh_debug_reg22_reg, rdc_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) +#define MH_DEBUG_REG22_SET_RDC_RLAST(mh_debug_reg22_reg, rdc_rlast) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG22_SET_TLBMISS_VALID(mh_debug_reg22_reg, tlbmiss_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG22_SET_BRC_VALID(mh_debug_reg22_reg, brc_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int cib_mh_axi_halt_req : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE; + unsigned int mh_cib_axi_halt_ack : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG22_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG22_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG22_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG22_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG22_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG22_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG22_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG22_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG22_RB_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG22_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG22_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG22_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG22_BRC_VALID_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int brc_valid : MH_DEBUG_REG22_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG22_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG22_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG22_RDC_VALID_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG22_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG22_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG22_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG22_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG22_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG22_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG22_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG22_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG22_MH_RBBM_busy_SIZE; + unsigned int mh_cib_axi_halt_ack : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE; + unsigned int cib_mh_axi_halt_req : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG23_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG23_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG23_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG23_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG23_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG23_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG23_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG23_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG23_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG23_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG23_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG23_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG23_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG23_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG23_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG23_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG23_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG23_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG23_ARB_QUAL_SHIFT 24 +#define MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT 25 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT 29 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG23_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG23_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG23_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG23_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG23_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG23_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG23_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG23_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG23_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG23_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG23_ARB_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG23_CP_EFF1_REQ_MASK 0x02000000 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG23_TC_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG23_RB_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK 0x20000000 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG23_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG23_EFF1_WINNER_MASK | \ + MH_DEBUG_REG23_ARB_WINNER_MASK | \ + MH_DEBUG_REG23_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG23_EFF1_WIN_MASK | \ + MH_DEBUG_REG23_KILL_EFF1_MASK | \ + MH_DEBUG_REG23_ARB_HOLD_MASK | \ + MH_DEBUG_REG23_ARB_RTR_q_MASK | \ + MH_DEBUG_REG23_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG23_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_ARB_QUAL_MASK | \ + MH_DEBUG_REG23_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG23_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG23_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG23(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, any_same_row_bank, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG23_GET_EFF2_FP_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_EFF2_LRU_WINNER_out(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG23_GET_EFF1_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WINNER_MASK) >> MH_DEBUG_REG23_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_MASK) >> MH_DEBUG_REG23_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_WINNER_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_q_MASK) >> MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG23_GET_EFF1_WIN(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WIN_MASK) >> MH_DEBUG_REG23_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG23_GET_KILL_EFF1(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_KILL_EFF1_MASK) >> MH_DEBUG_REG23_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_HOLD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_HOLD_MASK) >> MH_DEBUG_REG23_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_RTR_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_RTR_q_MASK) >> MH_DEBUG_REG23_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG23_GET_CP_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_VGT_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_TC_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_TC_SEND_EFF1_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_RB_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_QUAL_MASK) >> MH_DEBUG_REG23_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_CP_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_VGT_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_TC_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_RB_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_ANY_SAME_ROW_BANK(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG23_GET_TCD_NEARFULL_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG23_GET_TCHOLD_IP_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG23_SET_EFF2_FP_WINNER(mh_debug_reg23_reg, eff2_fp_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_EFF2_LRU_WINNER_out(mh_debug_reg23_reg, eff2_lru_winner_out) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG23_SET_EFF1_WINNER(mh_debug_reg23_reg, eff1_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_WINNER(mh_debug_reg23_reg, arb_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_WINNER_q(mh_debug_reg23_reg, arb_winner_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG23_SET_EFF1_WIN(mh_debug_reg23_reg, eff1_win) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG23_SET_KILL_EFF1(mh_debug_reg23_reg, kill_eff1) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_HOLD(mh_debug_reg23_reg, arb_hold) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_RTR_q(mh_debug_reg23_reg, arb_rtr_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG23_SET_CP_SEND_QUAL(mh_debug_reg23_reg, cp_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_VGT_SEND_QUAL(mh_debug_reg23_reg, vgt_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_TC_SEND_QUAL(mh_debug_reg23_reg, tc_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_TC_SEND_EFF1_QUAL(mh_debug_reg23_reg, tc_send_eff1_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_RB_SEND_QUAL(mh_debug_reg23_reg, rb_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_QUAL(mh_debug_reg23_reg, arb_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_CP_EFF1_REQ(mh_debug_reg23_reg, cp_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_VGT_EFF1_REQ(mh_debug_reg23_reg, vgt_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_TC_EFF1_REQ(mh_debug_reg23_reg, tc_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_RB_EFF1_REQ(mh_debug_reg23_reg, rb_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_ANY_SAME_ROW_BANK(mh_debug_reg23_reg, any_same_row_bank) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG23_SET_TCD_NEARFULL_q(mh_debug_reg23_reg, tcd_nearfull_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG23_SET_TCHOLD_IP_q(mh_debug_reg23_reg, tchold_ip_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG23_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG23_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG23_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG23_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG23_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG23_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG23_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG23_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int tchold_ip_q : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG23_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG23_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG23_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG23_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG23_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG23_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG23_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG23_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG24_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG24_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG24_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG24_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG24_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG24_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG24_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG24_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG24_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG24_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG24_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG24_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG24_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG24_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG24_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG24_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG24_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG24_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG24_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG24_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG24_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG24_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG24_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG24_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG24_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG24_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG24_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG24_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG24_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_EFF1_WINNER_MASK | \ + MH_DEBUG_REG24_ARB_WINNER_MASK | \ + MH_DEBUG_REG24_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG24_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_ARB_QUAL_MASK | \ + MH_DEBUG_REG24_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_EFF1_WIN_MASK | \ + MH_DEBUG_REG24_KILL_EFF1_MASK | \ + MH_DEBUG_REG24_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG24_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG24_ARB_HOLD_MASK | \ + MH_DEBUG_REG24_ARB_RTR_q_MASK | \ + MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG24(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG24_GET_EFF1_WINNER(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WINNER_MASK) >> MH_DEBUG_REG24_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_WINNER(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_WINNER_MASK) >> MH_DEBUG_REG24_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG24_GET_CP_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_VGT_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_TC_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_TC_SEND_EFF1_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_RB_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_QUAL_MASK) >> MH_DEBUG_REG24_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_CP_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_VGT_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_TC_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_RB_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_EFF1_WIN(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WIN_MASK) >> MH_DEBUG_REG24_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG24_GET_KILL_EFF1(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_KILL_EFF1_MASK) >> MH_DEBUG_REG24_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG24_GET_TCD_NEARFULL_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG24_GET_TC_ARB_HOLD(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_HOLD(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_HOLD_MASK) >> MH_DEBUG_REG24_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_RTR_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_RTR_q_MASK) >> MH_DEBUG_REG24_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG24_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG24_SET_EFF1_WINNER(mh_debug_reg24_reg, eff1_winner) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_WINNER(mh_debug_reg24_reg, arb_winner) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG24_SET_CP_SEND_QUAL(mh_debug_reg24_reg, cp_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_VGT_SEND_QUAL(mh_debug_reg24_reg, vgt_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_TC_SEND_QUAL(mh_debug_reg24_reg, tc_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_TC_SEND_EFF1_QUAL(mh_debug_reg24_reg, tc_send_eff1_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_RB_SEND_QUAL(mh_debug_reg24_reg, rb_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_QUAL(mh_debug_reg24_reg, arb_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_CP_EFF1_REQ(mh_debug_reg24_reg, cp_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_VGT_EFF1_REQ(mh_debug_reg24_reg, vgt_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_TC_EFF1_REQ(mh_debug_reg24_reg, tc_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_RB_EFF1_REQ(mh_debug_reg24_reg, rb_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_EFF1_WIN(mh_debug_reg24_reg, eff1_win) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG24_SET_KILL_EFF1(mh_debug_reg24_reg, kill_eff1) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG24_SET_TCD_NEARFULL_q(mh_debug_reg24_reg, tcd_nearfull_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG24_SET_TC_ARB_HOLD(mh_debug_reg24_reg, tc_arb_hold) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_HOLD(mh_debug_reg24_reg, arb_hold) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_RTR_q(mh_debug_reg24_reg, arb_rtr_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG24_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24_reg, same_page_limit_count_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int eff1_winner : MH_DEBUG_REG24_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG24_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG24_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG24_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG24_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG24_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG24_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG24_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG24_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG24_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG24_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG24_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG24_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG24_EFF1_WINNER_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG25_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG25_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG25_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG25_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG25_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG25_CLNT_REQ_SIZE 4 +#define MH_DEBUG_REG25_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_3_SIZE 3 + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG25_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT 6 +#define MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT 9 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT 12 +#define MH_DEBUG_REG25_ARB_HOLD_SHIFT 13 +#define MH_DEBUG_REG25_ARB_RTR_q_SHIFT 14 +#define MH_DEBUG_REG25_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG25_CLNT_REQ_SHIFT 16 +#define MH_DEBUG_REG25_RECENT_d_0_SHIFT 20 +#define MH_DEBUG_REG25_RECENT_d_1_SHIFT 23 +#define MH_DEBUG_REG25_RECENT_d_2_SHIFT 26 +#define MH_DEBUG_REG25_RECENT_d_3_SHIFT 29 + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG25_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK 0x000001c0 +#define MH_DEBUG_REG25_LEAST_RECENT_d_MASK 0x00000e00 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK 0x00001000 +#define MH_DEBUG_REG25_ARB_HOLD_MASK 0x00002000 +#define MH_DEBUG_REG25_ARB_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG25_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG25_CLNT_REQ_MASK 0x000f0000 +#define MH_DEBUG_REG25_RECENT_d_0_MASK 0x00700000 +#define MH_DEBUG_REG25_RECENT_d_1_MASK 0x03800000 +#define MH_DEBUG_REG25_RECENT_d_2_MASK 0x1c000000 +#define MH_DEBUG_REG25_RECENT_d_3_MASK 0xe0000000 + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG25_ARB_WINNER_MASK | \ + MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG25_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG25_ARB_HOLD_MASK | \ + MH_DEBUG_REG25_ARB_RTR_q_MASK | \ + MH_DEBUG_REG25_EFF1_WIN_MASK | \ + MH_DEBUG_REG25_CLNT_REQ_MASK | \ + MH_DEBUG_REG25_RECENT_d_0_MASK | \ + MH_DEBUG_REG25_RECENT_d_1_MASK | \ + MH_DEBUG_REG25_RECENT_d_2_MASK | \ + MH_DEBUG_REG25_RECENT_d_3_MASK) + +#define MH_DEBUG_REG25(eff2_lru_winner_out, arb_winner, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, eff1_win, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3) \ + ((eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) | \ + (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) | \ + (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT)) + +#define MH_DEBUG_REG25_GET_EFF2_LRU_WINNER_out(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_WINNER(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_WINNER_MASK) >> MH_DEBUG_REG25_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG25_GET_LEAST_RECENT_INDEX_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG25_GET_LEAST_RECENT_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG25_GET_UPDATE_RECENT_STACK_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_HOLD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_HOLD_MASK) >> MH_DEBUG_REG25_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_RTR_q(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_RTR_q_MASK) >> MH_DEBUG_REG25_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG25_GET_EFF1_WIN(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_EFF1_WIN_MASK) >> MH_DEBUG_REG25_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG25_GET_CLNT_REQ(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_CLNT_REQ_MASK) >> MH_DEBUG_REG25_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_0(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_0_MASK) >> MH_DEBUG_REG25_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_1(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_1_MASK) >> MH_DEBUG_REG25_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_2(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_2_MASK) >> MH_DEBUG_REG25_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_3(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_3_MASK) >> MH_DEBUG_REG25_RECENT_d_3_SHIFT) + +#define MH_DEBUG_REG25_SET_EFF2_LRU_WINNER_out(mh_debug_reg25_reg, eff2_lru_winner_out) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_WINNER(mh_debug_reg25_reg, arb_winner) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG25_SET_LEAST_RECENT_INDEX_d(mh_debug_reg25_reg, least_recent_index_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG25_SET_LEAST_RECENT_d(mh_debug_reg25_reg, least_recent_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG25_SET_UPDATE_RECENT_STACK_d(mh_debug_reg25_reg, update_recent_stack_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_HOLD(mh_debug_reg25_reg, arb_hold) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_RTR_q(mh_debug_reg25_reg, arb_rtr_q) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG25_SET_EFF1_WIN(mh_debug_reg25_reg, eff1_win) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG25_SET_CLNT_REQ(mh_debug_reg25_reg, clnt_req) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_0(mh_debug_reg25_reg, recent_d_0) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_1(mh_debug_reg25_reg, recent_d_1) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_2(mh_debug_reg25_reg, recent_d_2) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_3(mh_debug_reg25_reg, recent_d_3) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE; + unsigned int arb_winner : MH_DEBUG_REG25_ARB_WINNER_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG25_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG25_ARB_RTR_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG25_EFF1_WIN_SIZE; + unsigned int clnt_req : MH_DEBUG_REG25_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG25_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG25_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG25_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG25_RECENT_d_3_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int recent_d_3 : MH_DEBUG_REG25_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG25_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG25_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG25_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG25_CLNT_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG25_EFF1_WIN_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG25_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG25_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE; + unsigned int arb_winner : MH_DEBUG_REG25_ARB_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG26_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG26_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG26_WLAST_q_SIZE 1 +#define MH_DEBUG_REG26_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG26_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG26_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG26_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG26_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG26_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG26_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG26_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG26_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG26_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG26_ARB_WINNER_SHIFT 28 + +#define MH_DEBUG_REG26_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG26_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG26_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG26_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG26_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG26_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG26_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG26_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG26_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG26_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG26_ARB_WINNER_MASK 0x70000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG26_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG26_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG26_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_MH_written_MASK | \ + MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG26_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG26_WLAST_q_MASK | \ + MH_DEBUG_REG26_WBURST_IP_q_MASK | \ + MH_DEBUG_REG26_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG26_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG26_CP_MH_write_MASK | \ + MH_DEBUG_REG26_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG26_ARB_WINNER_MASK) + +#define MH_DEBUG_REG26(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG26_GET_TC_ARB_HOLD(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG26_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_NEARFULL_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCHOLD_IP_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCHOLD_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_MH_written(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_MH_written_MASK) >> MH_DEBUG_REG26_TC_MH_written_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_FULLNESS_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_ACTIVE(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG26_GET_WLAST_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WLAST_q_MASK) >> MH_DEBUG_REG26_WLAST_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_IP_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_IP_q_MASK) >> MH_DEBUG_REG26_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_CNT_q_MASK) >> MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_QUAL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_GET_CP_MH_write(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_MH_write_MASK) >> MH_DEBUG_REG26_CP_MH_write_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_QUAL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_GET_ARB_WINNER(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ARB_WINNER_MASK) >> MH_DEBUG_REG26_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG26_SET_TC_ARB_HOLD(mh_debug_reg26_reg, tc_arb_hold) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG26_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_noroq_same_row_bank) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_roq_same_row_bank) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_NEARFULL_q(mh_debug_reg26_reg, tcd_nearfull_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCHOLD_IP_q(mh_debug_reg26_reg, tchold_ip_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCHOLD_CNT_q(mh_debug_reg26_reg, tchold_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_MH_written(mh_debug_reg26_reg, tc_mh_written) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_FULLNESS_CNT_q(mh_debug_reg26_reg, tcd_fullness_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_ACTIVE(mh_debug_reg26_reg, wburst_active) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG26_SET_WLAST_q(mh_debug_reg26_reg, wlast_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_IP_q(mh_debug_reg26_reg, wburst_ip_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_CNT_q(mh_debug_reg26_reg, wburst_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_QUAL(mh_debug_reg26_reg, cp_send_qual) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_SET_CP_MH_write(mh_debug_reg26_reg, cp_mh_write) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_QUAL(mh_debug_reg26_reg, rb_send_qual) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_SET_ARB_WINNER(mh_debug_reg26_reg, arb_winner) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int tc_arb_hold : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG26_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG26_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG26_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG26_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG26_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG26_ARB_WINNER_SIZE; + unsigned int : 1; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int : 1; + unsigned int arb_winner : MH_DEBUG_REG26_ARB_WINNER_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG26_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG26_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG26_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG26_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG26_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG27(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG27_GET_RF_ARBITER_CONFIG_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG27_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG27_SET_RF_ARBITER_CONFIG_q(mh_debug_reg27_reg, rf_arbiter_config_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG27_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG28_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG28_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG28_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG28_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG28_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG28_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG28_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG28_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG28_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG28_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG28_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG28_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG28_TC_MH_send_MASK | \ + MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG28_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG28_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG28(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG28_GET_SAME_ROW_BANK_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG28_GET_ROQ_MARK_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_MARK_q_MASK) >> MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG28_GET_ROQ_VALID_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_VALID_q_MASK) >> MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_MH_send(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_MH_send_MASK) >> MH_DEBUG_REG28_TC_MH_send_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG28_GET_ANY_SAME_ROW_BANK(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_EMPTY(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_FULL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG28_SET_SAME_ROW_BANK_q(mh_debug_reg28_reg, same_row_bank_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG28_SET_ROQ_MARK_q(mh_debug_reg28_reg, roq_mark_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG28_SET_ROQ_VALID_q(mh_debug_reg28_reg, roq_valid_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_MH_send(mh_debug_reg28_reg, tc_mh_send) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_RTR_q(mh_debug_reg28_reg, tc_roq_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG28_SET_ANY_SAME_ROW_BANK(mh_debug_reg28_reg, any_same_row_bank) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_QUAL(mh_debug_reg28_reg, tc_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_EMPTY(mh_debug_reg28_reg, tc_roq_empty) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_FULL(mh_debug_reg28_reg, tc_roq_full) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_row_bank_q : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG28_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG28_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG28_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int tc_roq_full : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG28_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG28_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG28_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG29_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG29_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG29_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG29_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG29_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG29_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG29_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG29_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG29_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG29_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG29_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG29_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG29_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG29_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG29_TC_MH_send_MASK | \ + MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG29_KILL_EFF1_MASK | \ + MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG29_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG29_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG29(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG29_GET_SAME_ROW_BANK_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG29_GET_ROQ_MARK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_MARK_d_MASK) >> MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ROQ_VALID_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_VALID_d_MASK) >> MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG29_GET_TC_MH_send(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_MH_send_MASK) >> MH_DEBUG_REG29_TC_MH_send_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_KILL_EFF1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_KILL_EFF1_MASK) >> MH_DEBUG_REG29_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG29_GET_ANY_SAME_ROW_BANK(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG29_GET_TC_EFF1_QUAL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_EMPTY(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_FULL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG29_SET_SAME_ROW_BANK_q(mh_debug_reg29_reg, same_row_bank_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG29_SET_ROQ_MARK_d(mh_debug_reg29_reg, roq_mark_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ROQ_VALID_d(mh_debug_reg29_reg, roq_valid_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG29_SET_TC_MH_send(mh_debug_reg29_reg, tc_mh_send) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_RTR_q(mh_debug_reg29_reg, tc_roq_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_KILL_EFF1(mh_debug_reg29_reg, kill_eff1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG29_SET_ANY_SAME_ROW_BANK(mh_debug_reg29_reg, any_same_row_bank) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG29_SET_TC_EFF1_QUAL(mh_debug_reg29_reg, tc_eff1_qual) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_EMPTY(mh_debug_reg29_reg, tc_roq_empty) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_FULL(mh_debug_reg29_reg, tc_roq_full) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int same_row_bank_q : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG29_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG29_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG29_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG29_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int tc_roq_full : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG29_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG29_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG29_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG29_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG30(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_WIN(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_REQ(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, same_row_bank_win) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, same_row_bank_req) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, non_same_row_bank_win) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, non_same_row_bank_req) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int same_row_bank_win : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG31_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG31_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG31_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG31_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_TC_MH_send_MASK | \ + MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG31_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG31_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG31_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG31(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG31_GET_TC_MH_send(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_TC_MH_send_MASK) >> MH_DEBUG_REG31_TC_MH_send_SHIFT) +#define MH_DEBUG_REG31_GET_TC_ROQ_RTR_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_MARK_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_VALID_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_SAME_ROW_BANK_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_ADDR_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG31_SET_TC_MH_send(mh_debug_reg31_reg, tc_mh_send) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) +#define MH_DEBUG_REG31_SET_TC_ROQ_RTR_q(mh_debug_reg31_reg, tc_roq_rtr_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_MARK_q_0(mh_debug_reg31_reg, roq_mark_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_VALID_q_0(mh_debug_reg31_reg, roq_valid_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_SAME_ROW_BANK_q_0(mh_debug_reg31_reg, same_row_bank_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_ADDR_0(mh_debug_reg31_reg, roq_addr_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int tc_mh_send : MH_DEBUG_REG31_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int roq_addr_0 : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG31_TC_MH_send_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG32_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG32_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG32_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG32(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_ADDR_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q_1(mh_debug_reg32_reg, roq_mark_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q_1(mh_debug_reg32_reg, roq_valid_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q_1(mh_debug_reg32_reg, same_row_bank_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_ADDR_1(mh_debug_reg32_reg, roq_addr_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int roq_addr_1 : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG33_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG33_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG33_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG33(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_ADDR_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_q_2(mh_debug_reg33_reg, roq_mark_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_q_2(mh_debug_reg33_reg, roq_valid_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q_2(mh_debug_reg33_reg, same_row_bank_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_ADDR_2(mh_debug_reg33_reg, roq_addr_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int roq_addr_2 : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG34_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG34_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG34_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG34_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_TC_MH_send_MASK | \ + MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG34_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG34_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG34_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG34(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG34_GET_TC_MH_send(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_TC_MH_send_MASK) >> MH_DEBUG_REG34_TC_MH_send_SHIFT) +#define MH_DEBUG_REG34_GET_TC_ROQ_RTR_q(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_MARK_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_VALID_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_ADDR_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG34_SET_TC_MH_send(mh_debug_reg34_reg, tc_mh_send) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) +#define MH_DEBUG_REG34_SET_TC_ROQ_RTR_q(mh_debug_reg34_reg, tc_roq_rtr_q) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_MARK_q_3(mh_debug_reg34_reg, roq_mark_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_VALID_q_3(mh_debug_reg34_reg, roq_valid_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_q_3(mh_debug_reg34_reg, same_row_bank_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_ADDR_3(mh_debug_reg34_reg, roq_addr_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int tc_mh_send : MH_DEBUG_REG34_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int roq_addr_3 : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG34_TC_MH_send_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_4(mh_debug_reg35_reg, roq_mark_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_4(mh_debug_reg35_reg, roq_valid_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_4(mh_debug_reg35_reg, same_row_bank_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_4(mh_debug_reg35_reg, roq_addr_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_4 : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_5(mh_debug_reg36_reg, roq_mark_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_5(mh_debug_reg36_reg, roq_valid_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_5(mh_debug_reg36_reg, same_row_bank_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_5(mh_debug_reg36_reg, roq_addr_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_5 : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_6(mh_debug_reg37_reg, roq_mark_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_6(mh_debug_reg37_reg, roq_valid_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_6(mh_debug_reg37_reg, same_row_bank_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_6(mh_debug_reg37_reg, roq_addr_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_6 : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_7(mh_debug_reg38_reg, roq_mark_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_7(mh_debug_reg38_reg, roq_valid_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_7(mh_debug_reg38_reg, same_row_bank_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_7(mh_debug_reg38_reg, roq_addr_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_7 : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_ARB_WE_SIZE 1 +#define MH_DEBUG_REG39_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG39_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG39_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG39_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG39_MMU_WE_SIZE 1 +#define MH_DEBUG_REG39_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG39_MMU_ID_SIZE 3 +#define MH_DEBUG_REG39_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG39_MMU_BLEN_SIZE 1 + +#define MH_DEBUG_REG39_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG39_MMU_RTR_SHIFT 1 +#define MH_DEBUG_REG39_ARB_ID_q_SHIFT 2 +#define MH_DEBUG_REG39_ARB_WRITE_q_SHIFT 5 +#define MH_DEBUG_REG39_ARB_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT 7 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT 8 +#define MH_DEBUG_REG39_MMU_WE_SHIFT 11 +#define MH_DEBUG_REG39_ARQ_RTR_SHIFT 12 +#define MH_DEBUG_REG39_MMU_ID_SHIFT 13 +#define MH_DEBUG_REG39_MMU_WRITE_SHIFT 16 +#define MH_DEBUG_REG39_MMU_BLEN_SHIFT 17 + +#define MH_DEBUG_REG39_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG39_MMU_RTR_MASK 0x00000002 +#define MH_DEBUG_REG39_ARB_ID_q_MASK 0x0000001c +#define MH_DEBUG_REG39_ARB_WRITE_q_MASK 0x00000020 +#define MH_DEBUG_REG39_ARB_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK 0x00000700 +#define MH_DEBUG_REG39_MMU_WE_MASK 0x00000800 +#define MH_DEBUG_REG39_ARQ_RTR_MASK 0x00001000 +#define MH_DEBUG_REG39_MMU_ID_MASK 0x0000e000 +#define MH_DEBUG_REG39_MMU_WRITE_MASK 0x00010000 +#define MH_DEBUG_REG39_MMU_BLEN_MASK 0x00020000 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_ARB_WE_MASK | \ + MH_DEBUG_REG39_MMU_RTR_MASK | \ + MH_DEBUG_REG39_ARB_ID_q_MASK | \ + MH_DEBUG_REG39_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG39_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG39_MMU_WE_MASK | \ + MH_DEBUG_REG39_ARQ_RTR_MASK | \ + MH_DEBUG_REG39_MMU_ID_MASK | \ + MH_DEBUG_REG39_MMU_WRITE_MASK | \ + MH_DEBUG_REG39_MMU_BLEN_MASK) + +#define MH_DEBUG_REG39(arb_we, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen) \ + ((arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT)) + +#define MH_DEBUG_REG39_GET_ARB_WE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WE_MASK) >> MH_DEBUG_REG39_ARB_WE_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_RTR(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_RTR_MASK) >> MH_DEBUG_REG39_MMU_RTR_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_ID_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_ID_q_MASK) >> MH_DEBUG_REG39_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_WRITE_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WRITE_q_MASK) >> MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_BLEN_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_BLEN_q_MASK) >> MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_CTRL_EMPTY(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_FIFO_CNT_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_WE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WE_MASK) >> MH_DEBUG_REG39_MMU_WE_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_RTR(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_RTR_MASK) >> MH_DEBUG_REG39_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_ID(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_ID_MASK) >> MH_DEBUG_REG39_MMU_ID_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_WRITE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WRITE_MASK) >> MH_DEBUG_REG39_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_BLEN(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_BLEN_MASK) >> MH_DEBUG_REG39_MMU_BLEN_SHIFT) + +#define MH_DEBUG_REG39_SET_ARB_WE(mh_debug_reg39_reg, arb_we) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_RTR(mh_debug_reg39_reg, mmu_rtr) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_ID_q(mh_debug_reg39_reg, arb_id_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_WRITE_q(mh_debug_reg39_reg, arb_write_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_BLEN_q(mh_debug_reg39_reg, arb_blen_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_CTRL_EMPTY(mh_debug_reg39_reg, arq_ctrl_empty) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_FIFO_CNT_q(mh_debug_reg39_reg, arq_fifo_cnt_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_WE(mh_debug_reg39_reg, mmu_we) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_RTR(mh_debug_reg39_reg, arq_rtr) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_ID(mh_debug_reg39_reg, mmu_id) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_WRITE(mh_debug_reg39_reg, mmu_write) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_BLEN(mh_debug_reg39_reg, mmu_blen) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int arb_we : MH_DEBUG_REG39_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG39_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG39_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG39_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG39_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG39_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG39_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG39_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG39_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG39_MMU_BLEN_SIZE; + unsigned int : 14; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int : 14; + unsigned int mmu_blen : MH_DEBUG_REG39_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG39_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG39_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG39_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG39_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG39_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG39_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG39_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG39_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG39_ARB_WE_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_ARB_WE_SIZE 1 +#define MH_DEBUG_REG40_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG40_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG40_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG40_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG40_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG40_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG40_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG40_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_ARB_WE_MASK | \ + MH_DEBUG_REG40_ARB_ID_q_MASK | \ + MH_DEBUG_REG40_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG40(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG40_GET_ARB_WE(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_WE_MASK) >> MH_DEBUG_REG40_ARB_WE_SHIFT) +#define MH_DEBUG_REG40_GET_ARB_ID_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_ID_q_MASK) >> MH_DEBUG_REG40_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG40_GET_ARB_VAD_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_VAD_q_MASK) >> MH_DEBUG_REG40_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG40_SET_ARB_WE(mh_debug_reg40_reg, arb_we) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) +#define MH_DEBUG_REG40_SET_ARB_ID_q(mh_debug_reg40_reg, arb_id_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG40_SET_ARB_VAD_q(mh_debug_reg40_reg, arb_vad_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int arb_we : MH_DEBUG_REG40_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG40_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG40_ARB_VAD_q_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int arb_vad_q : MH_DEBUG_REG40_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG40_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG40_ARB_WE_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_MMU_WE_SIZE 1 +#define MH_DEBUG_REG41_MMU_ID_SIZE 3 +#define MH_DEBUG_REG41_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG41_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG41_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG41_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG41_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG41_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG41_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_MMU_WE_MASK | \ + MH_DEBUG_REG41_MMU_ID_MASK | \ + MH_DEBUG_REG41_MMU_PAD_MASK) + +#define MH_DEBUG_REG41(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG41_GET_MMU_WE(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_WE_MASK) >> MH_DEBUG_REG41_MMU_WE_SHIFT) +#define MH_DEBUG_REG41_GET_MMU_ID(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_ID_MASK) >> MH_DEBUG_REG41_MMU_ID_SHIFT) +#define MH_DEBUG_REG41_GET_MMU_PAD(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_PAD_MASK) >> MH_DEBUG_REG41_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG41_SET_MMU_WE(mh_debug_reg41_reg, mmu_we) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) +#define MH_DEBUG_REG41_SET_MMU_ID(mh_debug_reg41_reg, mmu_id) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) +#define MH_DEBUG_REG41_SET_MMU_PAD(mh_debug_reg41_reg, mmu_pad) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int mmu_we : MH_DEBUG_REG41_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG41_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG41_MMU_PAD_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int mmu_pad : MH_DEBUG_REG41_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG41_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG41_MMU_WE_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_WDB_WE_SIZE 1 +#define MH_DEBUG_REG42_WDB_RTR_SKID_SIZE 1 +#define MH_DEBUG_REG42_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG42_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG42_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG42_WDB_WE_SHIFT 0 +#define MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT 1 +#define MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT 2 +#define MH_DEBUG_REG42_ARB_WLAST_SHIFT 10 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT 11 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT 12 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT 17 +#define MH_DEBUG_REG42_WDB_WDC_WID_SHIFT 18 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT 21 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT 22 + +#define MH_DEBUG_REG42_WDB_WE_MASK 0x00000001 +#define MH_DEBUG_REG42_WDB_RTR_SKID_MASK 0x00000002 +#define MH_DEBUG_REG42_ARB_WSTRB_q_MASK 0x000003fc +#define MH_DEBUG_REG42_ARB_WLAST_MASK 0x00000400 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK 0x00000800 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK 0x0001f000 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_MASK 0x00020000 +#define MH_DEBUG_REG42_WDB_WDC_WID_MASK 0x001c0000 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_MASK 0x00200000 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK 0x3fc00000 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_WDB_WE_MASK | \ + MH_DEBUG_REG42_WDB_RTR_SKID_MASK | \ + MH_DEBUG_REG42_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG42_ARB_WLAST_MASK | \ + MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG42_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG42(wdb_we, wdb_rtr_skid, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) | \ + (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG42_GET_WDB_WE(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WE_MASK) >> MH_DEBUG_REG42_WDB_WE_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_RTR_SKID(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_RTR_SKID_MASK) >> MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) +#define MH_DEBUG_REG42_GET_ARB_WSTRB_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG42_GET_ARB_WLAST(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WLAST_MASK) >> MH_DEBUG_REG42_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_CTRL_EMPTY(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_FIFO_CNT_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG42_GET_WDC_WDB_RE_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WID(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WID_MASK) >> MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WLAST(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WSTRB(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG42_SET_WDB_WE(mh_debug_reg42_reg, wdb_we) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_RTR_SKID(mh_debug_reg42_reg, wdb_rtr_skid) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_RTR_SKID_MASK) | (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) +#define MH_DEBUG_REG42_SET_ARB_WSTRB_q(mh_debug_reg42_reg, arb_wstrb_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG42_SET_ARB_WLAST(mh_debug_reg42_reg, arb_wlast) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_CTRL_EMPTY(mh_debug_reg42_reg, wdb_ctrl_empty) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_FIFO_CNT_q(mh_debug_reg42_reg, wdb_fifo_cnt_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG42_SET_WDC_WDB_RE_q(mh_debug_reg42_reg, wdc_wdb_re_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WID(mh_debug_reg42_reg, wdb_wdc_wid) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WLAST(mh_debug_reg42_reg, wdb_wdc_wlast) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WSTRB(mh_debug_reg42_reg, wdb_wdc_wstrb) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int wdb_we : MH_DEBUG_REG42_WDB_WE_SIZE; + unsigned int wdb_rtr_skid : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG42_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG42_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE; + unsigned int : 2; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int : 2; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG42_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG42_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE; + unsigned int wdb_we : MH_DEBUG_REG42_WDB_WE_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE 32 + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT 0 + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) + +#define MH_DEBUG_REG43(arb_wdata_q_31_0) \ + ((arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_WDATA_q_31_0(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) >> MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_WDATA_q_31_0(mh_debug_reg43_reg, arb_wdata_q_31_0) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) | (arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_wdata_q_31_0 : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_wdata_q_31_0 : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE 32 + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT 0 + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) + +#define MH_DEBUG_REG44(arb_wdata_q_63_32) \ + ((arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WDATA_q_63_32(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) >> MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WDATA_q_63_32(mh_debug_reg44_reg, arb_wdata_q_63_32) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) | (arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_wdata_q_63_32 : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_wdata_q_63_32 : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG45(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG45_GET_WDB_WDC_WDATA_31_0(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG45_SET_WDB_WDC_WDATA_31_0(mh_debug_reg45_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG46(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDB_WDC_WDATA_63_32(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG46_SET_WDB_WDC_WDATA_63_32(mh_debug_reg46_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG47_RVALID_q_SIZE 1 +#define MH_DEBUG_REG47_RREADY_q_SIZE 1 +#define MH_DEBUG_REG47_RLAST_q_SIZE 1 +#define MH_DEBUG_REG47_BVALID_q_SIZE 1 +#define MH_DEBUG_REG47_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG47_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG47_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG47_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG47_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG47_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG47_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG47_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG47_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG47_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG47_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG47_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG47_RVALID_q_MASK | \ + MH_DEBUG_REG47_RREADY_q_MASK | \ + MH_DEBUG_REG47_RLAST_q_MASK | \ + MH_DEBUG_REG47_BVALID_q_MASK | \ + MH_DEBUG_REG47_BREADY_q_MASK) + +#define MH_DEBUG_REG47(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG47_GET_CTRL_ARC_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_CTRL_RARC_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_ARQ_CTRL_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_ARQ_CTRL_WRITE(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG47_GET_TLBMISS_CTRL_RTS(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG47_GET_CTRL_TLBMISS_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_INFLT_LIMIT_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG47_GET_INFLT_LIMIT_CNT_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG47_GET_ARC_CTRL_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_RARC_CTRL_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_RVALID_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RVALID_q_MASK) >> MH_DEBUG_REG47_RVALID_q_SHIFT) +#define MH_DEBUG_REG47_GET_RREADY_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RREADY_q_MASK) >> MH_DEBUG_REG47_RREADY_q_SHIFT) +#define MH_DEBUG_REG47_GET_RLAST_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RLAST_q_MASK) >> MH_DEBUG_REG47_RLAST_q_SHIFT) +#define MH_DEBUG_REG47_GET_BVALID_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_BVALID_q_MASK) >> MH_DEBUG_REG47_BVALID_q_SHIFT) +#define MH_DEBUG_REG47_GET_BREADY_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_BREADY_q_MASK) >> MH_DEBUG_REG47_BREADY_q_SHIFT) + +#define MH_DEBUG_REG47_SET_CTRL_ARC_EMPTY(mh_debug_reg47_reg, ctrl_arc_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_CTRL_RARC_EMPTY(mh_debug_reg47_reg, ctrl_rarc_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_ARQ_CTRL_EMPTY(mh_debug_reg47_reg, arq_ctrl_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_ARQ_CTRL_WRITE(mh_debug_reg47_reg, arq_ctrl_write) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG47_SET_TLBMISS_CTRL_RTS(mh_debug_reg47_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG47_SET_CTRL_TLBMISS_RE_q(mh_debug_reg47_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_INFLT_LIMIT_q(mh_debug_reg47_reg, inflt_limit_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG47_SET_INFLT_LIMIT_CNT_q(mh_debug_reg47_reg, inflt_limit_cnt_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG47_SET_ARC_CTRL_RE_q(mh_debug_reg47_reg, arc_ctrl_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_RARC_CTRL_RE_q(mh_debug_reg47_reg, rarc_ctrl_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_RVALID_q(mh_debug_reg47_reg, rvalid_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) +#define MH_DEBUG_REG47_SET_RREADY_q(mh_debug_reg47_reg, rready_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) +#define MH_DEBUG_REG47_SET_RLAST_q(mh_debug_reg47_reg, rlast_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) +#define MH_DEBUG_REG47_SET_BVALID_q(mh_debug_reg47_reg, bvalid_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) +#define MH_DEBUG_REG47_SET_BREADY_q(mh_debug_reg47_reg, bready_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG47_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG47_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG47_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG47_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG47_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG47_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG47_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG47_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG47_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG47_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG48_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG48_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG48_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG48_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG48_RDC_RID_SIZE 3 +#define MH_DEBUG_REG48_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG48_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG48_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG48_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG48_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG48_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG48_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG48_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG48_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG48_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG48_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG48_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG48_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG48_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG48_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG48_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG48_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG48_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG48_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG48_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG48_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG48_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG48_RDC_VALID_MASK | \ + MH_DEBUG_REG48_RDC_RID_MASK | \ + MH_DEBUG_REG48_RDC_RLAST_MASK | \ + MH_DEBUG_REG48_RDC_RRESP_MASK | \ + MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG48_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG48(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG48_GET_MH_CP_grb_send(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CP_grb_send_MASK) >> MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG48_GET_MH_VGT_grb_send(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG48_GET_MH_TC_mcsend(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TC_mcsend_MASK) >> MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG48_GET_MH_TLBMISS_SEND(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_VALID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_VALID_MASK) >> MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_VALID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_VALID_MASK) >> MH_DEBUG_REG48_RDC_VALID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RID_MASK) >> MH_DEBUG_REG48_RDC_RID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RLAST(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RLAST_MASK) >> MH_DEBUG_REG48_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RRESP(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RRESP_MASK) >> MH_DEBUG_REG48_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_CTRL_RTS(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG48_GET_CTRL_TLBMISS_RE_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG48_GET_MMU_ID_REQUEST_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG48_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG48_GET_MMU_ID_RESPONSE(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG48_GET_CNT_HOLD_q1(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG48_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG48_SET_MH_CP_grb_send(mh_debug_reg48_reg, mh_cp_grb_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG48_SET_MH_VGT_grb_send(mh_debug_reg48_reg, mh_vgt_grb_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG48_SET_MH_TC_mcsend(mh_debug_reg48_reg, mh_tc_mcsend) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG48_SET_MH_TLBMISS_SEND(mh_debug_reg48_reg, mh_tlbmiss_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_VALID(mh_debug_reg48_reg, tlbmiss_valid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_VALID(mh_debug_reg48_reg, rdc_valid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RID(mh_debug_reg48_reg, rdc_rid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RLAST(mh_debug_reg48_reg, rdc_rlast) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RRESP(mh_debug_reg48_reg, rdc_rresp) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_CTRL_RTS(mh_debug_reg48_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG48_SET_CTRL_TLBMISS_RE_q(mh_debug_reg48_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG48_SET_MMU_ID_REQUEST_q(mh_debug_reg48_reg, mmu_id_request_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG48_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG48_SET_MMU_ID_RESPONSE(mh_debug_reg48_reg, mmu_id_response) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg48_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG48_SET_CNT_HOLD_q1(mh_debug_reg48_reg, cnt_hold_q1) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG48_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG48_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG48_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG48_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG48_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG48_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG48_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG48_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG48_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG48_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG48_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG48_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG48_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG48_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG48_MH_CP_grb_send_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG49(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG49_GET_RF_MMU_PAGE_FAULT(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG49_SET_RF_MMU_PAGE_FAULT(mh_debug_reg49_reg, rf_mmu_page_fault) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE 24 +#define MH_DEBUG_REG50_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG50_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG50_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG50_ARB_WE_SIZE 1 +#define MH_DEBUG_REG50_MMU_RTR_SIZE 1 + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG50_ARB_ID_q_SHIFT 24 +#define MH_DEBUG_REG50_ARB_WRITE_q_SHIFT 27 +#define MH_DEBUG_REG50_client_behavior_q_SHIFT 28 +#define MH_DEBUG_REG50_ARB_WE_SHIFT 30 +#define MH_DEBUG_REG50_MMU_RTR_SHIFT 31 + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK 0x00ffffff +#define MH_DEBUG_REG50_ARB_ID_q_MASK 0x07000000 +#define MH_DEBUG_REG50_ARB_WRITE_q_MASK 0x08000000 +#define MH_DEBUG_REG50_client_behavior_q_MASK 0x30000000 +#define MH_DEBUG_REG50_ARB_WE_MASK 0x40000000 +#define MH_DEBUG_REG50_MMU_RTR_MASK 0x80000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK | \ + MH_DEBUG_REG50_ARB_ID_q_MASK | \ + MH_DEBUG_REG50_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG50_client_behavior_q_MASK | \ + MH_DEBUG_REG50_ARB_WE_MASK | \ + MH_DEBUG_REG50_MMU_RTR_MASK) + +#define MH_DEBUG_REG50(rf_mmu_config_q, arb_id_q, arb_write_q, client_behavior_q, arb_we, mmu_rtr) \ + ((rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT)) + +#define MH_DEBUG_REG50_GET_RF_MMU_CONFIG_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) >> MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_ID_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_ID_q_MASK) >> MH_DEBUG_REG50_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_WRITE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WRITE_q_MASK) >> MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG50_GET_client_behavior_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_client_behavior_q_MASK) >> MH_DEBUG_REG50_client_behavior_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_WE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WE_MASK) >> MH_DEBUG_REG50_ARB_WE_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_RTR(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_RTR_MASK) >> MH_DEBUG_REG50_MMU_RTR_SHIFT) + +#define MH_DEBUG_REG50_SET_RF_MMU_CONFIG_q(mh_debug_reg50_reg, rf_mmu_config_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) | (rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_ID_q(mh_debug_reg50_reg, arb_id_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_WRITE_q(mh_debug_reg50_reg, arb_write_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG50_SET_client_behavior_q(mh_debug_reg50_reg, client_behavior_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_WE(mh_debug_reg50_reg, arb_we) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_RTR(mh_debug_reg50_reg, mmu_rtr) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int rf_mmu_config_q : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG50_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG50_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG50_client_behavior_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG50_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG50_MMU_RTR_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mmu_rtr : MH_DEBUG_REG50_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG50_ARB_WE_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG50_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG50_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG50_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_stage1_valid_SIZE 1 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG51_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG51_tag_match_q_SIZE 1 +#define MH_DEBUG_REG51_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG51_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG51_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG51_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG51_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG51_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG51_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG51_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG51_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG51_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG51_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG51_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG51_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG51_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG51_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG51_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG51_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG51_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG51_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG51_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG51_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_stage1_valid_MASK | \ + MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG51_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG51_tag_match_q_MASK | \ + MH_DEBUG_REG51_tag_miss_q_MASK | \ + MH_DEBUG_REG51_va_in_range_q_MASK | \ + MH_DEBUG_REG51_MMU_MISS_MASK | \ + MH_DEBUG_REG51_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG51_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG51_MMU_HIT_MASK | \ + MH_DEBUG_REG51_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG51_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG51(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG51_GET_stage1_valid(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_stage1_valid_MASK) >> MH_DEBUG_REG51_stage1_valid_SHIFT) +#define MH_DEBUG_REG51_GET_IGNORE_TAG_MISS_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG51_GET_pa_in_mpu_range(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_pa_in_mpu_range_MASK) >> MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG51_GET_tag_match_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_tag_match_q_MASK) >> MH_DEBUG_REG51_tag_match_q_SHIFT) +#define MH_DEBUG_REG51_GET_tag_miss_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_tag_miss_q_MASK) >> MH_DEBUG_REG51_tag_miss_q_SHIFT) +#define MH_DEBUG_REG51_GET_va_in_range_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_va_in_range_q_MASK) >> MH_DEBUG_REG51_va_in_range_q_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_MISS_MASK) >> MH_DEBUG_REG51_MMU_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_READ_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_MISS_MASK) >> MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_WRITE_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_HIT_MASK) >> MH_DEBUG_REG51_MMU_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_READ_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_HIT_MASK) >> MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_WRITE_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_REQ_VA_OFFSET_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG51_SET_stage1_valid(mh_debug_reg51_reg, stage1_valid) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) +#define MH_DEBUG_REG51_SET_IGNORE_TAG_MISS_q(mh_debug_reg51_reg, ignore_tag_miss_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG51_SET_pa_in_mpu_range(mh_debug_reg51_reg, pa_in_mpu_range) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG51_SET_tag_match_q(mh_debug_reg51_reg, tag_match_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) +#define MH_DEBUG_REG51_SET_tag_miss_q(mh_debug_reg51_reg, tag_miss_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) +#define MH_DEBUG_REG51_SET_va_in_range_q(mh_debug_reg51_reg, va_in_range_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_MISS(mh_debug_reg51_reg, mmu_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_READ_MISS(mh_debug_reg51_reg, mmu_read_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_WRITE_MISS(mh_debug_reg51_reg, mmu_write_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_HIT(mh_debug_reg51_reg, mmu_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_READ_HIT(mh_debug_reg51_reg, mmu_read_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_WRITE_HIT(mh_debug_reg51_reg, mmu_write_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_REQ_VA_OFFSET_q(mh_debug_reg51_reg, req_va_offset_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int stage1_valid : MH_DEBUG_REG51_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG51_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG51_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG51_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG51_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG51_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG51_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG51_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG51_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int req_va_offset_q : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG51_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG51_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG51_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG51_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG51_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG51_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG51_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG51_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG51_stage1_valid_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG52_MMU_WE_SIZE 1 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG52_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG52_stage1_valid_SIZE 1 +#define MH_DEBUG_REG52_stage2_valid_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG52_tag_match_q_SIZE 1 +#define MH_DEBUG_REG52_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG52_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG52_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG52_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG52_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG52_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG52_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG52_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG52_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG52_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG52_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG52_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG52_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG52_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG52_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG52_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG52_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG52_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG52_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG52_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG52_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_ARQ_RTR_MASK | \ + MH_DEBUG_REG52_MMU_WE_MASK | \ + MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG52_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG52_stage1_valid_MASK | \ + MH_DEBUG_REG52_stage2_valid_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK | \ + MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG52_tag_match_q_MASK | \ + MH_DEBUG_REG52_tag_miss_q_MASK | \ + MH_DEBUG_REG52_va_in_range_q_MASK | \ + MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG52_TAG_valid_q_MASK) + +#define MH_DEBUG_REG52(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_ARQ_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARQ_RTR_MASK) >> MH_DEBUG_REG52_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_WE_MASK) >> MH_DEBUG_REG52_MMU_WE_SHIFT) +#define MH_DEBUG_REG52_GET_CTRL_TLBMISS_RE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG52_GET_TLBMISS_CTRL_RTS(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG52_GET_MH_TLBMISS_SEND(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG52_GET_pa_in_mpu_range(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_pa_in_mpu_range_MASK) >> MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG52_GET_stage1_valid(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_stage1_valid_MASK) >> MH_DEBUG_REG52_stage1_valid_SHIFT) +#define MH_DEBUG_REG52_GET_stage2_valid(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_stage2_valid_MASK) >> MH_DEBUG_REG52_stage2_valid_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) +#define MH_DEBUG_REG52_GET_IGNORE_TAG_MISS_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG52_GET_tag_match_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_tag_match_q_MASK) >> MH_DEBUG_REG52_tag_match_q_SHIFT) +#define MH_DEBUG_REG52_GET_tag_miss_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_tag_miss_q_MASK) >> MH_DEBUG_REG52_tag_miss_q_SHIFT) +#define MH_DEBUG_REG52_GET_va_in_range_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_va_in_range_q_MASK) >> MH_DEBUG_REG52_va_in_range_q_SHIFT) +#define MH_DEBUG_REG52_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG52_GET_TAG_valid_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_TAG_valid_q_MASK) >> MH_DEBUG_REG52_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG52_SET_ARQ_RTR(mh_debug_reg52_reg, arq_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_WE(mh_debug_reg52_reg, mmu_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) +#define MH_DEBUG_REG52_SET_CTRL_TLBMISS_RE_q(mh_debug_reg52_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG52_SET_TLBMISS_CTRL_RTS(mh_debug_reg52_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG52_SET_MH_TLBMISS_SEND(mh_debug_reg52_reg, mh_tlbmiss_send) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG52_SET_pa_in_mpu_range(mh_debug_reg52_reg, pa_in_mpu_range) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG52_SET_stage1_valid(mh_debug_reg52_reg, stage1_valid) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) +#define MH_DEBUG_REG52_SET_stage2_valid(mh_debug_reg52_reg, stage2_valid) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) +#define MH_DEBUG_REG52_SET_IGNORE_TAG_MISS_q(mh_debug_reg52_reg, ignore_tag_miss_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG52_SET_tag_match_q(mh_debug_reg52_reg, tag_match_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) +#define MH_DEBUG_REG52_SET_tag_miss_q(mh_debug_reg52_reg, tag_miss_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) +#define MH_DEBUG_REG52_SET_va_in_range_q(mh_debug_reg52_reg, va_in_range_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) +#define MH_DEBUG_REG52_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg52_reg, pte_fetch_complete_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG52_SET_TAG_valid_q(mh_debug_reg52_reg, tag_valid_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int arq_rtr : MH_DEBUG_REG52_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG52_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG52_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG52_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG52_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG52_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG52_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG52_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG52_TAG_valid_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int tag_valid_q : MH_DEBUG_REG52_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG52_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG52_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG52_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG52_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG52_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG52_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG52_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG52_ARQ_RTR_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG53_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG53_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG53_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG53_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG53_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG53_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG53_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG53_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG53_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG53_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG53_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG53_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG53_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_TAG0_VA_MASK | \ + MH_DEBUG_REG53_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG53_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG53_TAG1_VA_MASK | \ + MH_DEBUG_REG53_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG53(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG53_GET_TAG0_VA(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG0_VA_MASK) >> MH_DEBUG_REG53_TAG0_VA_SHIFT) +#define MH_DEBUG_REG53_GET_TAG_valid_q_0(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_0_MASK) >> MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG53_GET_ALWAYS_ZERO(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG53_GET_TAG1_VA(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG1_VA_MASK) >> MH_DEBUG_REG53_TAG1_VA_SHIFT) +#define MH_DEBUG_REG53_GET_TAG_valid_q_1(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_1_MASK) >> MH_DEBUG_REG53_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG53_SET_TAG0_VA(mh_debug_reg53_reg, tag0_va) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) +#define MH_DEBUG_REG53_SET_TAG_valid_q_0(mh_debug_reg53_reg, tag_valid_q_0) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG53_SET_ALWAYS_ZERO(mh_debug_reg53_reg, always_zero) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG53_SET_TAG1_VA(mh_debug_reg53_reg, tag1_va) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) +#define MH_DEBUG_REG53_SET_TAG_valid_q_1(mh_debug_reg53_reg, tag_valid_q_1) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int tag0_va : MH_DEBUG_REG53_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG53_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG53_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG53_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG53_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG53_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG53_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG53_TAG0_VA_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG54_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG54_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG54_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG54_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG54_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG54_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG54_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG54_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG54_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG54_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG54_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG54_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG54_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_TAG2_VA_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG54_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG54_TAG3_VA_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG54(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG54_GET_TAG2_VA(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG2_VA_MASK) >> MH_DEBUG_REG54_TAG2_VA_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q_2(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_2_MASK) >> MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG54_GET_ALWAYS_ZERO(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG54_GET_TAG3_VA(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG3_VA_MASK) >> MH_DEBUG_REG54_TAG3_VA_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q_3(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_3_MASK) >> MH_DEBUG_REG54_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG54_SET_TAG2_VA(mh_debug_reg54_reg, tag2_va) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q_2(mh_debug_reg54_reg, tag_valid_q_2) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG54_SET_ALWAYS_ZERO(mh_debug_reg54_reg, always_zero) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG54_SET_TAG3_VA(mh_debug_reg54_reg, tag3_va) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q_3(mh_debug_reg54_reg, tag_valid_q_3) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag2_va : MH_DEBUG_REG54_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG54_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG54_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG54_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG54_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG54_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG54_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG54_TAG2_VA_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG55_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG55_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG4_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG5_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG55(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG4_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG4_VA_MASK) >> MH_DEBUG_REG55_TAG4_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_4(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_4_MASK) >> MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG5_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG5_VA_MASK) >> MH_DEBUG_REG55_TAG5_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_5(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_5_MASK) >> MH_DEBUG_REG55_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG4_VA(mh_debug_reg55_reg, tag4_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_4(mh_debug_reg55_reg, tag_valid_q_4) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG5_VA(mh_debug_reg55_reg, tag5_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_5(mh_debug_reg55_reg, tag_valid_q_5) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag4_va : MH_DEBUG_REG55_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG55_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG55_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG55_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG55_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG55_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG55_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG55_TAG4_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG56_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG56_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG6_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG7_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG56(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG6_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG6_VA_MASK) >> MH_DEBUG_REG56_TAG6_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_6(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_6_MASK) >> MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG7_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG7_VA_MASK) >> MH_DEBUG_REG56_TAG7_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_7(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_7_MASK) >> MH_DEBUG_REG56_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG6_VA(mh_debug_reg56_reg, tag6_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_6(mh_debug_reg56_reg, tag_valid_q_6) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG7_VA(mh_debug_reg56_reg, tag7_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_7(mh_debug_reg56_reg, tag_valid_q_7) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag6_va : MH_DEBUG_REG56_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG56_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG56_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG56_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG56_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG56_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG56_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG56_TAG6_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG57_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG57_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG8_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG9_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG57(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG8_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG8_VA_MASK) >> MH_DEBUG_REG57_TAG8_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_8(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_8_MASK) >> MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG9_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG9_VA_MASK) >> MH_DEBUG_REG57_TAG9_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_9(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_9_MASK) >> MH_DEBUG_REG57_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG8_VA(mh_debug_reg57_reg, tag8_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_8(mh_debug_reg57_reg, tag_valid_q_8) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG9_VA(mh_debug_reg57_reg, tag9_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_9(mh_debug_reg57_reg, tag_valid_q_9) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag8_va : MH_DEBUG_REG57_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG57_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG57_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG57_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG57_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG57_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG57_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG57_TAG8_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG58_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG58_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG10_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG11_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG58(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG10_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG10_VA_MASK) >> MH_DEBUG_REG58_TAG10_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_10(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_10_MASK) >> MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG11_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG11_VA_MASK) >> MH_DEBUG_REG58_TAG11_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_11(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_11_MASK) >> MH_DEBUG_REG58_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG10_VA(mh_debug_reg58_reg, tag10_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_10(mh_debug_reg58_reg, tag_valid_q_10) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG11_VA(mh_debug_reg58_reg, tag11_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_11(mh_debug_reg58_reg, tag_valid_q_11) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag10_va : MH_DEBUG_REG58_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG58_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG58_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG58_TAG10_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG59_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG59_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG12_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG13_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG59(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG12_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG12_VA_MASK) >> MH_DEBUG_REG59_TAG12_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_12(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_12_MASK) >> MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG13_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG13_VA_MASK) >> MH_DEBUG_REG59_TAG13_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_13(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_13_MASK) >> MH_DEBUG_REG59_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG12_VA(mh_debug_reg59_reg, tag12_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_12(mh_debug_reg59_reg, tag_valid_q_12) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG13_VA(mh_debug_reg59_reg, tag13_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_13(mh_debug_reg59_reg, tag_valid_q_13) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag12_va : MH_DEBUG_REG59_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG59_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG59_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG59_TAG12_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG60_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG60_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG14_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG15_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG60(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG14_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG14_VA_MASK) >> MH_DEBUG_REG60_TAG14_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_14(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_14_MASK) >> MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG15_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG15_VA_MASK) >> MH_DEBUG_REG60_TAG15_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_15(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_15_MASK) >> MH_DEBUG_REG60_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG14_VA(mh_debug_reg60_reg, tag14_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_14(mh_debug_reg60_reg, tag_valid_q_14) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG15_VA(mh_debug_reg60_reg, tag15_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_15(mh_debug_reg60_reg, tag_valid_q_15) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag14_va : MH_DEBUG_REG60_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG60_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG60_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG60_TAG14_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG61(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG61_GET_MH_DBG_DEFAULT(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG61_SET_MH_DBG_DEFAULT(mh_debug_reg61_reg, mh_dbg_default) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int mh_dbg_default : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int mh_dbg_default : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG62(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG62_GET_MH_DBG_DEFAULT(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG62_SET_MH_DBG_DEFAULT(mh_debug_reg62_reg, mh_dbg_default) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int mh_dbg_default : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int mh_dbg_default : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int : 8; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 8; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 5; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int : 5; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fpos_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fpos_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fpos_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fpos_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fpos, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fpos << SC_DEBUG_7_fpos_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fpos(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fpos_MASK) >> SC_DEBUG_7_fpos_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fpos(sc_debug_7_reg, fpos) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fpos_MASK) | (fpos << SC_DEBUG_7_fpos_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fpos : SC_DEBUG_7_fpos_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fpos : SC_DEBUG_7_fpos_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fpos_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fpos_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fpos_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fpos_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fpos, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fpos << SC_DEBUG_8_fpos_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fpos(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fpos_MASK) >> SC_DEBUG_8_fpos_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fpos(sc_debug_8_reg, fpos) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fpos_MASK) | (fpos << SC_DEBUG_8_fpos_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fpos : SC_DEBUG_8_fpos_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fpos : SC_DEBUG_8_fpos_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int : 3; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 3; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK) + +#define VGT_BIN_SIZE(num_words) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 8; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int : 8; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, cst_0_abs_mod, low_precision_16b_fp, scalar_result, sst_0_abs_mod, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_CST_0_ABS_MOD(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SST_0_ABS_MOD(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_CST_0_ABS_MOD(sq_instruction_alu_0_reg, cst_0_abs_mod) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) | (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SST_0_ABS_MOD(sq_instruction_alu_0_reg, sst_0_abs_mod) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) | (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int cst_0_abs_mod : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int sst_0_abs_mod : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int sst_0_abs_mod : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int cst_0_abs_mod : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int : 8; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 8; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int : 28; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 28; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int : 8; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 8; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_RESERVED9_SIZE 1 +#define RB_BC_CONTROL_RESERVED10_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_RESERVED9_SHIFT 30 +#define RB_BC_CONTROL_RESERVED10_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_RESERVED9_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED10_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_RESERVED9_MASK | \ + RB_BC_CONTROL_RESERVED10_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, reserved9, reserved10) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) | \ + (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED9(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED9_MASK) >> RB_BC_CONTROL_RESERVED9_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED10(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED10_MASK) >> RB_BC_CONTROL_RESERVED10_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED9(rb_bc_control_reg, reserved9) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED9_MASK) | (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED10(rb_bc_control_reg, reserved10) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED10_MASK) | (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int reserved9 : RB_BC_CONTROL_RESERVED9_SIZE; + unsigned int reserved10 : RB_BC_CONTROL_RESERVED10_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved10 : RB_BC_CONTROL_RESERVED10_SIZE; + unsigned int reserved9 : RB_BC_CONTROL_RESERVED9_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h new file mode 100644 index 000000000000..1feebebda054 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h @@ -0,0 +1,540 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h new file mode 100644 index 000000000000..15cfbebf2907 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h @@ -0,0 +1,1897 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + + + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, + PERF_PAPC_SU_FACENESS_CULL = 102, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +typedef enum VGT_DI_FACENESS_CULL_SELECT { + DI_FACE_CULL_NONE = 0, + DI_FACE_CULL_FETCH = 1, + DI_FACE_BACKFACE_CULL = 2, + DI_FACE_FRONTFACE_CULL = 3 +} VGT_DI_FACENESS_CULL_SELECT; +#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, + FACENESS_FLUSH = 28, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + BIN_PRIM_FACE_CULL = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_PERFCOUNT_VTX_POP_THREAD = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_PERFCOUNT_PIX_POP_THREAD = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, + SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_TOTAL_WRITE_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_TOTAL_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, + ELAPSED_CLK_CYCLES = 164, + CP_W_16B_REQUESTS = 165, + CP_W_32B_REQUESTS = 166, + TC_16B_REQUESTS = 167, + TC_32B_REQUESTS = 168, + PA_REQUESTS = 169, + PA_DATA_BYTES_WRITTEN = 170, + PA_WRITE_CLEAN_RESPONSES = 171, + PA_CYCLES_HELD_OFF = 172, + AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, + AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, + AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, + AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, + AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, + AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, + AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, + AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, + AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h new file mode 100644 index 000000000000..87a454a1e38a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h @@ -0,0 +1,1703 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) + GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + GENERATE_ENUM(DI_FACE_CULL_NONE, 0) + GENERATE_ENUM(DI_FACE_CULL_FETCH, 1) + GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2) + GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3) +END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) + GENERATE_ENUM(FACENESS_FLUSH, 28) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_TOTAL_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) + GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164) + GENERATE_ENUM(CP_W_16B_REQUESTS, 165) + GENERATE_ENUM(CP_W_32B_REQUESTS, 166) + GENERATE_ENUM(TC_16B_REQUESTS, 167) + GENERATE_ENUM(TC_32B_REQUESTS, 168) + GENERATE_ENUM(PA_REQUESTS, 169) + GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170) + GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171) + GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180) + GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h new file mode 100644 index 000000000000..d04379887b78 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h @@ -0,0 +1,3405 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(PERFCOUNTER_REF, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(CLIP_DISABLE, bool) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(W_NAN_RETAIN, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(PIX_CENTER, PixCenter) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(QUANT_MODE, QuantMode) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(HEIGHT, fixed12_4) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MIN_SIZE, fixed12_4) + GENERATE_FIELD(MAX_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_FACE_DATA) + GENERATE_FIELD(BASE_ADDR, int) +END_REGISTER(PA_SU_FACE_DATA) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(CULL_FRONT, bool) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) + GENERATE_FIELD(CLAMPED_FACENESS, bool) + GENERATE_FIELD(ZERO_AREA_FACENESS, bool) + GENERATE_FIELD(FACE_KILL_ENABLE, bool) + GENERATE_FIELD(FACE_WRITE_ENABLE, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(LINE_PATTERN, hex) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(BRES_CNTL, int) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(LAST_PIXEL, bool) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_PTR, int) + GENERATE_FIELD(CURRENT_COUNT, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(NUM_INDICES, uint) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(FACENESS_FETCH, int) + GENERATE_FIELD(FACENESS_RESET, int) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) + GENERATE_FIELD(DST_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(L2_INVALIDATE, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(TC_BUSY, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TP_BUSY_EXTEND, int) + GENERATE_FIELD(TC_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_INPUT_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TPC_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(LOD_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(SQ_TP_WAKEUP, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(BLEND_PRECISION, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_INPUT_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TP_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_LOD_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(TT_MODE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(not_MH_TC_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(tca_rts, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(tp0_full, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_tpc_rts, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(captue_state_rts, int) + GENERATE_FIELD(capture_tca_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(access512, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(sector_format512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(left_done, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(valid_left_q, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(quad_sel_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(setquads_to_send, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(tc0_arb_rts, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(arb_RTR, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ipbuf_busy, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_pstate, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dcmp_mux_send, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_stall, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(n0_dxt2_4_types, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_incoming_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_sg_crd_RTR, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(rl_sg_sector_format, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(busy, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(fifo_busy, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(TCO_TCB_read_xfc, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_DYNAMIC, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_SIZE_VTX, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_PIX, int) + GENERATE_FIELD(INST_BASE_VTX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_CONSTANTS_RT, int) + GENERATE_FIELD(EO_TSTATE_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_ALUCST_SIZE, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(TIMEBASE, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_VS_WATCHDOG_TIMER) + GENERATE_FIELD(ENABLE, int) + GENERATE_FIELD(TIMEOUT_COUNT, int) +END_REGISTER(SQ_VS_WATCHDOG_TIMER) + +START_REGISTER(SQ_PS_WATCHDOG_TIMER) + GENERATE_FIELD(ENABLE, int) + GENERATE_FIELD(TIMEOUT_COUNT, int) +END_REGISTER(SQ_PS_WATCHDOG_TIMER) + +START_REGISTER(SQ_INT_CNTL) + GENERATE_FIELD(PS_WATCHDOG_MASK, int) + GENERATE_FIELD(VS_WATCHDOG_MASK, int) +END_REGISTER(SQ_INT_CNTL) + +START_REGISTER(SQ_INT_STATUS) + GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int) + GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int) +END_REGISTER(SQ_INT_STATUS) + +START_REGISTER(SQ_INT_ACK) + GENERATE_FIELD(PS_WATCHDOG_ACK, int) + GENERATE_FIELD(VS_WATCHDOG_ACK, int) +END_REGISTER(SQ_INT_ACK) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(VC_VSR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_GPR_SIZE, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(EX_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(POS_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(END_OF_BUFFER, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(VTX_SYNC_CNT, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(BUSY_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(BUSY, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(VECTOR_RESULT, int) + GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(SCALAR_DST_REL, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(CONST_0_REL_ABS, int) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_C_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_2, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(OPCODE, TexInstOpcode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(DST_SEL_X, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(PRED_SELECT, PredSelect) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(USE_REG_GRADIENTS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(OPCODE, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(SRC_SEL, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(DST_SEL_X, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(PRED_SELECT, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(STRIDE, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(TYPE, int) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(BASE_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(ENDIAN_SWAP, int) + GENERATE_FIELD(LIMIT_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(VS_CF_SIZE, int) + GENERATE_FIELD(PS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(PARAM_SHADE, ParamShade) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(GEN_INDEX_VTX, int) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_0, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_7, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_8, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_15, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(TX_CACHE_SEL, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_ON, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_COUNT, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_ON_PIX, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_BREAK_ADDR, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) + GENERATE_FIELD(PA_CLNT_ENABLE, bool) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(CPw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(MMUr_ID, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(PAw_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(AXI_READ_ERROR, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_READ_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_AXI_HALT_CONTROL) + GENERATE_FIELD(AXI_HALT, bool) +END_REGISTER(MH_AXI_HALT_CONTROL) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(MMU_ENABLE, bool) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(NUM_64KB_REGIONS, int) + GENERATE_FIELD(VA_BASE, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(PAGE_FAULT, int) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(REQ_VA, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_ALL, int) + GENERATE_FIELD(INVALIDATE_TC, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(WAIT_RE_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(CMDFIFO_AVAIL, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(GUI_ACTIVE, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int) + GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH1_SW_CNTL, int) + GENERATE_FIELD(DMI_CH1_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH2_SW_CNTL, int) + GENERATE_FIELD(DMI_CH2_NUM_BUFS, int) + GENERATE_FIELD(DMI_CHANNEL_SELECT, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH3_SW_CNTL, int) + GENERATE_FIELD(DMI_CH3_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH4_SW_CNTL, int) + GENERATE_FIELD(DMI_CH4_NUM_BUFS, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(DMI_CH1_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH2_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH3_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH4_BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(PATCH_REVISION, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(CUSTOMER_ID, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(PARTNUMBER1, int) + GENERATE_FIELD(DESIGNER0, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(DESIGNER1, int) + GENERATE_FIELD(REVISION, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(CONTINUATION, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(READ_TIMEOUT, int) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) + GENERATE_FIELD(SKEW_COUNT, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_CP, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_VGT, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG_OUT) + GENERATE_FIELD(DEBUG_BUS_OUT, int) +END_REGISTER(RBBM_DEBUG_OUT) + +START_REGISTER(RBBM_DEBUG_CNTL) + GENERATE_FIELD(SUB_BLOCK_ADDR, int) + GENERATE_FIELD(SUB_BLOCK_SEL, int) + GENERATE_FIELD(SW_ENABLE, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int) + GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int) +END_REGISTER(RBBM_DEBUG_CNTL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_RTR, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ADDRESS, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ERROR, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(RDERR_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(RDERR_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(RDERR_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(MH_INT_STAT, int) + GENERATE_FIELD(SQ_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(RBBM_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_BUFSZ, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_SWAP, int) + GENERATE_FIELD(RB_RPTR_ADDR, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_TIMER, int) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_SWAP, int) + GENERATE_FIELD(RB_WPTR_BASE, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_IB1_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_ST_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(MEQ_END, int) + GENERATE_FIELD(ROQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_RING, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_IB2, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB1_COUNTER, int) + GENERATE_FIELD(IB2_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_RPTR_ST, int) + GENERATE_FIELD(STQ_WPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_RPTR, int) + GENERATE_FIELD(MEQ_WPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(TAG_0_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(INVALID_RETURN_TAG, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_INDEX, int) + GENERATE_FIELD(CMD_QUEUE_SEL, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(ME_STATMUX, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(PROG_CNT_SIZE, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_UMSK, int) + GENERATE_FIELD(SCRATCH_SWAP, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_SWM, int) + GENERATE_FIELD(VS_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_SWAP, int) + GENERATE_FIELD(VS_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_SWM, int) + GENERATE_FIELD(PS_DONE_CNTR, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_SWAP, int) + GENERATE_FIELD(PS_DONE_ADDR, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_SWAP, int) + GENERATE_FIELD(CF_DONE_ADDR, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_SWAP, int) + GENERATE_FIELD(NRT_WRITE_ADDR, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(SW_INT_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(RB_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(SW_INT_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(RB_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(SW_INT_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(RB_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_STATE, int) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(DISCARD_0, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_15, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(DISCARD_16, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_31, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(DISCARD_32, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_47, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(DISCARD_48, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_63, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(MIU_WR_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(CP_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(SURFACE_PITCH, uint) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_BASE, uint) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) + GENERATE_FIELD(DEPTH_BASE, uint) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(STENCILREF, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILWRITEMASK, hex) + GENERATE_FIELD(RESERVED0, bool) + GENERATE_FIELD(RESERVED1, bool) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(WRITE_RED, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) + GENERATE_FIELD(RESERVED2, bool) + GENERATE_FIELD(RESERVED3, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_RED, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_BLUE, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(STENCILREF_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) + GENERATE_FIELD(RESERVED4, bool) + GENERATE_FIELD(RESERVED5, bool) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCIL_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(BLEND_FORCE, bool) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(CLEAR_MASK, uint) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_X, uint) + GENERATE_FIELD(OFFSET_Y, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(CRC_SYSTEM, bool) + GENERATE_FIELD(RESERVED6, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_RANGE, hex) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z_TILE_EMPTY, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ACCUM_VALID, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(RB_BC_SPARES) + GENERATE_FIELD(RESERVED, bool) +END_REGISTER(RB_BC_SPARES) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h new file mode 100644 index 000000000000..0e32e421d0a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _R400IPT_H_ +#define _R400IPT_H_ + +// Hand-generated list from Yamato_PM4_Spec.doc + +#define PM4_PACKET0_NOP 0x00000000 // Empty type-0 packet header +#define PM4_PACKET1_NOP 0x40000000 // Empty type-1 packet header +#define PM4_PACKET2_NOP 0x80000000 // Empty type-2 packet header (reserved) + +#define PM4_COUNT_SHIFT 16 +#define PM4_COUNT_MASK +#define PM4_PACKET_COUNT(__x) ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000) +// Type 3 packet headers + +#define PM4_PACKET3_NOP 0xC0001000 // Do nothing. +#define PM4_PACKET3_IB_PREFETCH_END 0xC0001700 // Internal Packet Used Only by CP +#define PM4_PACKET3_SUBBLK_PREFETCH 0xC0001F00 // Internal Packet Used Only by CP + +#define PM4_PACKET3_INSTR_PREFETCH 0xC0002000 // Internal Packet Used Only by CP +#define PM4_PACKET3_REG_RMW 0xC0002100 // Register Read-Modify-Write New for R400 +#define PM4_PACKET3_DRAW_INDX 0xC0002200 // Initiate fetch of index buffer New for R400 +#define PM4_PACKET3_VIZ_QUERY 0xC0002300 // Begin/End initiator for Viz Query extent processing New for R400 +#define PM4_PACKET3_SET_STATE 0xC0002500 // Fetch State Sub-Blocks and Initiate Shader Code DMAs New for R400 +#define PM4_PACKET3_WAIT_FOR_IDLE 0xC0002600 // Wait for the engine to be idle. +#define PM4_PACKET3_IM_LOAD 0xC0002700 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_IM_LOAD_IMMEDIATE 0xC0002B00 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_SET_CONSTANT 0xC0002D00 // Load Constant Into Chip & Shadow to Memory New for R400 +#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT 0xC0002E00 // Load All Constants from a Location in Memory New for R400 +#define PM4_PACKET3_LOAD_ALU_CONSTANT 0xC0002F00 // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants + +#define PM4_PACKET3_DRAW_INDX_BIN 0xC0003400 // Initiate fetch of index buffer and BIN info used for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2_BIN 0xC0003500 // Draw using supplied indices and initiate fetch of BIN info for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2 0xC0003600 // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt +#define PM4_PACKET3_INDIRECT_BUFFER_PFD 0xC0003700 +#define PM4_PACKET3_INVALIDATE_STATE 0xC0003B00 // Selective Invalidation of State Pointers New for R400 +#define PM4_PACKET3_WAIT_REG_MEM 0xC0003C00 // Wait Until a Register or Memory Location is a Specific Value. New for R400 +#define PM4_PACKET3_MEM_WRITE 0xC0003D00 // Write DWORD to Memory For Synchronization New for R400 +#define PM4_PACKET3_REG_TO_MEM 0xC0003E00 // Reads Register in Chip and Writes to Memory New for R400 +#define PM4_PACKET3_INDIRECT_BUFFER 0xC0003F00 // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer. Supported + +#define PM4_PACKET3_CP_INTERRUPT 0xC0004000 // Generate Interrupt from the Command Stream New for R400 +#define PM4_PACKET3_COND_EXEC 0xC0004400 // Conditional execution of a sequence of packets +#define PM4_PACKET3_COND_WRITE 0xC0004500 // Conditional Write to Memory New for R400 +#define PM4_PACKET3_EVENT_WRITE 0xC0004600 // Generate An Event that Creates a Write to Memory when Completed New for R400 +#define PM4_PACKET3_INSTR_MATCH 0xC0004700 // Internal Packet Used Only by CP +#define PM4_PACKET3_ME_INIT 0xC0004800 // Initialize CP's Micro Engine New for R400 +#define PM4_PACKET3_CONST_PREFETCH 0xC0004900 // Internal packet used only by CP +#define PM4_PACKET3_MEM_WRITE_CNTR 0xC0004F00 + +#define PM4_PACKET3_SET_BIN_MASK 0xC0005000 // Sets the 64-bit BIN_MASK register in the PFP +#define PM4_PACKET3_SET_BIN_SELECT 0xC0005100 // Sets the 64-bit BIN_SELECT register in the PFP +#define PM4_PACKET3_WAIT_REG_EQ 0xC0005200 // Wait until a register location is equal to a specific value +#define PM4_PACKET3_WAIT_REG_GTE 0xC0005300 // Wait until a register location is greater than or equal to a specific value +#define PM4_PACKET3_INCR_UPDT_STATE 0xC0005500 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_CONST 0xC0005600 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_INSTR 0xC0005700 // Internal Packet Used Only by CP +#define PM4_PACKET3_EVENT_WRITE_SHD 0xC0005800 // Generate a VS|PS_Done Event. +#define PM4_PACKET3_EVENT_WRITE_CFL 0xC0005900 // Generate a Cach Flush Done Event +#define PM4_PACKET3_EVENT_WRITE_ZPD 0xC0005B00 // Generate a Cach Flush Done Event +#define PM4_PACKET3_WAIT_UNTIL_READ 0xC0005C00 // Wait Until a Read completes. +#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE 0xC0005D00 // Wait Until all Base/Size writes from an IB_PFD packet have completed. +#define PM4_PACKET3_CONTEXT_UPDATE 0xC0005E00 // Updates the current context if needed. + + /****** New Opcodes For R400 (all decode values are TBD) ******/ + + +#endif // _R400IPT_H_ diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h new file mode 100644 index 000000000000..52ced9af774c --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h @@ -0,0 +1,5908 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR_MASK 0xffffffe0L + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS_MASK 0x10000000L +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS 0x10000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK 0x20000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS 0x20000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK 0x80000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE 0x80000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fposition_MASK 0x00000010L +#define SC_DEBUG_7__fposition 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fposition_MASK 0x00100000L +#define SC_DEBUG_8__fposition 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK 0x00000300L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_BIN_SIZE__FACENESS_FETCH_MASK 0x40000000L +#define VGT_BIN_SIZE__FACENESS_FETCH 0x40000000L +#define VGT_BIN_SIZE__FACENESS_RESET_MASK 0x80000000L +#define VGT_BIN_SIZE__FACENESS_RESET 0x80000000L + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK 0x00000001L +#define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK 0x00000002L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK 0x00000001L +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT 0x00000001L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK 0x00000002L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT 0x00000002L + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK 0x00000001L +#define SQ_INT_ACK__PS_WATCHDOG_ACK 0x00000001L +#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK 0x00000002L +#define SQ_INT_ACK__VS_WATCHDOG_ACK 0x00000002L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK 0x04000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE 0x04000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK 0x00007000L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK 0x00000001L +#define MH_AXI_HALT_CONTROL__AXI_HALT 0x00000001L + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__PA_REQUEST_MASK 0x00000400L +#define MH_DEBUG_REG00__PA_REQUEST 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000800L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00002000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00008000L +#define MH_DEBUG_REG00__WDB_FULL 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BVALID 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x08000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x08000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK 0x10000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA 0x10000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG01__CP_BLEN_q 0x00000040L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00000080L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00000080L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00000100L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00000100L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00000200L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00000200L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG01__TC_SEND_q 0x00000400L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG01__TC_RTR_q 0x00000800L +#define MH_DEBUG_REG01__TC_BLEN_q_MASK 0x00001000L +#define MH_DEBUG_REG01__TC_BLEN_q 0x00001000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00004000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00008000L +#define MH_DEBUG_REG01__TC_MH_written 0x00008000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00010000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00010000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00020000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00020000L +#define MH_DEBUG_REG01__PA_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG01__PA_SEND_q 0x00040000L +#define MH_DEBUG_REG01__PA_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG01__PA_RTR_q 0x00080000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__MH_PA_writeclean_MASK 0x00004000L +#define MH_DEBUG_REG02__MH_PA_writeclean 0x00004000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x00038000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x000c0000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be_MASK 0x000000ffL +#define MH_DEBUG_REG08__RB_MH_be_MASK 0x0000ff00L +#define MH_DEBUG_REG08__PA_MH_be_MASK 0x00ff0000L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG09__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG10__TC_MH_send 0x00000004L +#define MH_DEBUG_REG10__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG11__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG11__TC_MH_send 0x02000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG12__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG12__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG12__TC_MH_written 0x04000000L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG14__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG15__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG15__RB_MH_send 0x00000010L +#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG18__PA_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG18__PA_MH_send 0x00000010L +#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG21__AVALID_q 0x00000001L +#define MH_DEBUG_REG21__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG21__AREADY_q 0x00000002L +#define MH_DEBUG_REG21__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG21__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG21__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG21__ARVALID_q 0x00000100L +#define MH_DEBUG_REG21__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG21__ARREADY_q 0x00000200L +#define MH_DEBUG_REG21__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG21__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG21__RVALID_q 0x00008000L +#define MH_DEBUG_REG21__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG21__RREADY_q 0x00010000L +#define MH_DEBUG_REG21__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG21__RLAST_q 0x00020000L +#define MH_DEBUG_REG21__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG21__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG21__WVALID_q 0x00200000L +#define MH_DEBUG_REG21__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG21__WREADY_q 0x00400000L +#define MH_DEBUG_REG21__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG21__WLAST_q 0x00800000L +#define MH_DEBUG_REG21__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG21__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG21__BVALID_q 0x08000000L +#define MH_DEBUG_REG21__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG21__BREADY_q 0x10000000L +#define MH_DEBUG_REG21__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG22__AVALID_q 0x00000001L +#define MH_DEBUG_REG22__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG22__AREADY_q 0x00000002L +#define MH_DEBUG_REG22__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG22__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG22__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG22__ARVALID_q 0x00000080L +#define MH_DEBUG_REG22__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG22__ARREADY_q 0x00000100L +#define MH_DEBUG_REG22__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG22__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG22__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG22__WVALID_q 0x00002000L +#define MH_DEBUG_REG22__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG22__WREADY_q 0x00004000L +#define MH_DEBUG_REG22__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG22__WLAST_q 0x00008000L +#define MH_DEBUG_REG22__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG22__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG22__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG22__BVALID_q 0x08000000L +#define MH_DEBUG_REG22__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG22__BREADY_q 0x10000000L +#define MH_DEBUG_REG22__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG23__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG24__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG24__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG24__REG_RE 0x00010000L +#define MH_DEBUG_REG24__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG24__REG_WE 0x00020000L +#define MH_DEBUG_REG24__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG24__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy_MASK 0x00000001L +#define MH_DEBUG_REG26__MH_RBBM_busy 0x00000001L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int 0x00000008L +#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK 0x00000010L +#define MH_DEBUG_REG26__GAT_CLK_ENA 0x00000010L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK 0x00000020L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override 0x00000020L +#define MH_DEBUG_REG26__CNT_q_MASK 0x00000fc0L +#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK 0x00001000L +#define MH_DEBUG_REG26__TCD_EMPTY_q 0x00001000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY 0x00002000L +#define MH_DEBUG_REG26__MH_BUSY_d_MASK 0x00004000L +#define MH_DEBUG_REG26__MH_BUSY_d 0x00004000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK 0x00008000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY 0x00008000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC 0x00020000L +#define MH_DEBUG_REG26__CP_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG26__CP_SEND_q 0x00040000L +#define MH_DEBUG_REG26__CP_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG26__CP_RTR_q 0x00080000L +#define MH_DEBUG_REG26__VGT_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG26__VGT_SEND_q 0x00100000L +#define MH_DEBUG_REG26__VGT_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG26__VGT_RTR_q 0x00200000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00800000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00800000L +#define MH_DEBUG_REG26__RB_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG26__RB_SEND_q 0x01000000L +#define MH_DEBUG_REG26__RB_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG26__RB_RTR_q 0x02000000L +#define MH_DEBUG_REG26__PA_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG26__PA_SEND_q 0x04000000L +#define MH_DEBUG_REG26__PA_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG26__PA_RTR_q 0x08000000L +#define MH_DEBUG_REG26__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG26__RDC_VALID 0x10000000L +#define MH_DEBUG_REG26__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG26__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG26__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG26__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG26__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG26__BRC_VALID 0x80000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG27__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG27__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG27__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG27__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG27__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG27__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG27__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG27__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG27__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG27__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG27__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG27__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG27__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG27__PA_SEND_QUAL 0x01000000L +#define MH_DEBUG_REG27__ARB_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG27__ARB_QUAL 0x02000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK 0x20000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ 0x20000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG28__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG28__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG28__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG28__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG28__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG28__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG28__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG28__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG28__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG28__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG28__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG28__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG28__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG28__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG28__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG28__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG28__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK 0x00000038L +#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK 0x000001c0L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK 0x00000200L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d 0x00000200L +#define MH_DEBUG_REG29__ARB_HOLD_MASK 0x00000400L +#define MH_DEBUG_REG29__ARB_HOLD 0x00000400L +#define MH_DEBUG_REG29__ARB_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG29__ARB_RTR_q 0x00000800L +#define MH_DEBUG_REG29__CLNT_REQ_MASK 0x0001f000L +#define MH_DEBUG_REG29__RECENT_d_0_MASK 0x000e0000L +#define MH_DEBUG_REG29__RECENT_d_1_MASK 0x00700000L +#define MH_DEBUG_REG29__RECENT_d_2_MASK 0x03800000L +#define MH_DEBUG_REG29__RECENT_d_3_MASK 0x1c000000L +#define MH_DEBUG_REG29__RECENT_d_4_MASK 0xe0000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG30__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG30__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG30__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG30__TC_MH_written 0x00000800L +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG30__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG30__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG30__WLAST_q 0x00100000L +#define MH_DEBUG_REG30__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG30__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG30__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG30__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG30__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG30__CP_MH_write 0x04000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK 0x10000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL 0x10000000L +#define MH_DEBUG_REG30__ARB_WINNER_MASK 0xe0000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG32__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG32__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG32__TC_MH_send 0x01000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG32__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG32__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG33__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG33__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG33__TC_MH_send 0x01000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG33__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG33__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG39__TC_MH_send 0x00000001L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG39__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG39__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG40__TC_MH_send 0x00000001L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG40__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG40__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG41__TC_MH_send 0x00000001L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG41__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG41__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG42__TC_MH_send 0x00000001L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG42__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG42__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG43__ARB_REG_WE_q 0x00000001L +#define MH_DEBUG_REG43__ARB_WE_MASK 0x00000002L +#define MH_DEBUG_REG43__ARB_WE 0x00000002L +#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG43__ARB_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG43__ARB_RTR_q_MASK 0x00000008L +#define MH_DEBUG_REG43__ARB_RTR_q 0x00000008L +#define MH_DEBUG_REG43__ARB_REG_RTR_MASK 0x00000010L +#define MH_DEBUG_REG43__ARB_REG_RTR 0x00000010L +#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK 0x00000020L +#define MH_DEBUG_REG43__WDAT_BURST_RTR 0x00000020L +#define MH_DEBUG_REG43__MMU_RTR_MASK 0x00000040L +#define MH_DEBUG_REG43__MMU_RTR 0x00000040L +#define MH_DEBUG_REG43__ARB_ID_q_MASK 0x00000380L +#define MH_DEBUG_REG43__ARB_WRITE_q_MASK 0x00000400L +#define MH_DEBUG_REG43__ARB_WRITE_q 0x00000400L +#define MH_DEBUG_REG43__ARB_BLEN_q_MASK 0x00000800L +#define MH_DEBUG_REG43__ARB_BLEN_q 0x00000800L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY 0x00001000L +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK 0x0000e000L +#define MH_DEBUG_REG43__MMU_WE_MASK 0x00010000L +#define MH_DEBUG_REG43__MMU_WE 0x00010000L +#define MH_DEBUG_REG43__ARQ_RTR_MASK 0x00020000L +#define MH_DEBUG_REG43__ARQ_RTR 0x00020000L +#define MH_DEBUG_REG43__MMU_ID_MASK 0x001c0000L +#define MH_DEBUG_REG43__MMU_WRITE_MASK 0x00200000L +#define MH_DEBUG_REG43__MMU_WRITE 0x00200000L +#define MH_DEBUG_REG43__MMU_BLEN_MASK 0x00400000L +#define MH_DEBUG_REG43__MMU_BLEN 0x00400000L +#define MH_DEBUG_REG43__WBURST_IP_q_MASK 0x00800000L +#define MH_DEBUG_REG43__WBURST_IP_q 0x00800000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK 0x01000000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q 0x01000000L +#define MH_DEBUG_REG43__WDB_WE_MASK 0x02000000L +#define MH_DEBUG_REG43__WDB_WE 0x02000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK 0x08000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3 0x08000000L + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG44__ARB_WE 0x00000001L +#define MH_DEBUG_REG44__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG44__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG45__MMU_WE 0x00000001L +#define MH_DEBUG_REG45__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG45__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG46__WDAT_REG_WE_q 0x00000001L +#define MH_DEBUG_REG46__WDB_WE_MASK 0x00000002L +#define MH_DEBUG_REG46__WDB_WE 0x00000002L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK 0x00000008L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4 0x00000008L +#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK 0x00000ff0L +#define MH_DEBUG_REG46__ARB_WLAST_MASK 0x00001000L +#define MH_DEBUG_REG46__ARB_WLAST 0x00001000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY 0x00002000L +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK 0x0007c000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK 0x00080000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q 0x00080000L +#define MH_DEBUG_REG46__WDB_WDC_WID_MASK 0x00700000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK 0xff000000L + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG49__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG49__RVALID_q 0x00008000L +#define MH_DEBUG_REG49__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG49__RREADY_q 0x00010000L +#define MH_DEBUG_REG49__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG49__RLAST_q 0x00020000L +#define MH_DEBUG_REG49__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG49__BVALID_q 0x00040000L +#define MH_DEBUG_REG49__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG49__BREADY_q 0x00080000L + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG50__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG50__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG50__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG50__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG50__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG50__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG50__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG50__RDC_VALID 0x00000020L +#define MH_DEBUG_REG50__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG50__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG50__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG50__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG50__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003L +#define MH_DEBUG_REG52__ARB_WE_MASK 0x00000004L +#define MH_DEBUG_REG52__ARB_WE 0x00000004L +#define MH_DEBUG_REG52__MMU_RTR_MASK 0x00000008L +#define MH_DEBUG_REG52__MMU_RTR 0x00000008L +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0L +#define MH_DEBUG_REG52__ARB_ID_q_MASK 0x1c000000L +#define MH_DEBUG_REG52__ARB_WRITE_q_MASK 0x20000000L +#define MH_DEBUG_REG52__ARB_WRITE_q 0x20000000L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0xc0000000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG53__stage1_valid 0x00000001L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG53__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG53__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG53__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG53__tag_match_q 0x00000008L +#define MH_DEBUG_REG53__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG53__tag_miss_q 0x00000010L +#define MH_DEBUG_REG53__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG53__va_in_range_q 0x00000020L +#define MH_DEBUG_REG53__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG53__MMU_MISS 0x00000040L +#define MH_DEBUG_REG53__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG53__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG53__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG53__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG53__MMU_HIT 0x00000200L +#define MH_DEBUG_REG53__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG53__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG53__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG54__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG54__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG54__MMU_WE 0x00000002L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG54__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG54__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG54__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG54__stage1_valid 0x00000080L +#define MH_DEBUG_REG54__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG54__stage2_valid 0x00000100L +#define MH_DEBUG_REG54__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG54__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG54__tag_match_q 0x00001000L +#define MH_DEBUG_REG54__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG54__tag_miss_q 0x00002000L +#define MH_DEBUG_REG54__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG54__va_in_range_q 0x00004000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG54__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG61__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG61__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG61__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG61__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG61__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG62__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG62__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG62__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG62__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG62__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK 0x03000000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2 0x00000004L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK 0x00000008L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID 0x00000008L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK 0x00000040L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2 0x00000040L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL 0x00000080L +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK 0x00000300L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK 0x00001000L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2 0x00001000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK 0x00002000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL 0x00002000L +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK 0x0000c000L +#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK 0x00030000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK 0x00400000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2 0x00400000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK 0x00800000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL 0x00800000L +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK 0x03000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK 0x10000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2 0x10000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK 0x20000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL 0x20000000L +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK 0xc0000000L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK 0x00000003L +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK 0x00000300L +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK 0x00030000L +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK 0x03000000L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK 0x01000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP 0x01000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK 0x02000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI 0x02000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE 0x20000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE 0x40000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK 0xffffffffL + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK 0x0000003fL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK 0x00000f00L +#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK 0x00001000L +#define RBBM_DEBUG_CNTL__SW_ENABLE 0x00001000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK 0x0f000000L +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK 0xf0000000L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK 0x04000000L +#define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L +#define RB_STENCILREFMASK__RESERVED0_MASK 0x01000000L +#define RB_STENCILREFMASK__RESERVED0 0x01000000L +#define RB_STENCILREFMASK__RESERVED1_MASK 0x02000000L +#define RB_STENCILREFMASK__RESERVED1 0x02000000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L +#define RB_COLOR_MASK__RESERVED2_MASK 0x00000010L +#define RB_COLOR_MASK__RESERVED2 0x00000010L +#define RB_COLOR_MASK__RESERVED3_MASK 0x00000020L +#define RB_COLOR_MASK__RESERVED3 0x00000020L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L +#define RB_STENCILREFMASK_BF__RESERVED4_MASK 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED4 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED5_MASK 0x02000000L +#define RB_STENCILREFMASK_BF__RESERVED5 0x02000000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__CRC_SYSTEM_MASK 0x40000000L +#define RB_BC_CONTROL__CRC_SYSTEM 0x40000000L +#define RB_BC_CONTROL__RESERVED6_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED6 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED_MASK 0xffffffffL + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h new file mode 100644 index 000000000000..83be5f82ed8c --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h @@ -0,0 +1,591 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_FACE_DATA 0x0C86 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_VS_WATCHDOG_TIMER 0x0D0A +#define mmSQ_PS_WATCHDOG_TIMER 0x0D0B +#define mmSQ_INT_CNTL 0x0D34 +#define mmSQ_INT_STATUS 0x0D35 +#define mmSQ_INT_ACK 0x0D36 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_AXI_HALT_CONTROL 0x0A50 +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG_OUT 0x03A0 +#define mmRBBM_DEBUG_CNTL 0x03A1 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x0458 +#define mmCP_IB1_BUFSZ 0x0459 +#define mmCP_IB2_BASE 0x045A +#define mmCP_IB2_BUFSZ 0x045B +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x00C0 +#define mmCP_PFP_UCODE_DATA 0x00C1 +#define mmCP_PERFMON_CNTL 0x0444 +#define mmCP_PERFCOUNTER_SELECT 0x0445 +#define mmCP_PERFCOUNTER_LO 0x0446 +#define mmCP_PERFCOUNTER_HI 0x0447 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmRB_BC_SPARES 0x0F2C +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h new file mode 100644 index 000000000000..17379dcfa0e7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h @@ -0,0 +1,223 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h new file mode 100644 index 000000000000..bcc28f133b08 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h @@ -0,0 +1,14280 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_FACE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int BASE_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 1; + unsigned int CLAMPED_FACENESS : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int FACE_WRITE_ENABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACE_WRITE_ENABLE : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int CLAMPED_FACENESS : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fposition : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fposition : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fposition : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fposition : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int : 1; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 1; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int FACENESS_FETCH : 1; + unsigned int FACENESS_RESET : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACENESS_RESET : 1; + unsigned int FACENESS_FETCH : 1; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_MASK : 1; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int PS_WATCHDOG_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_TIMEOUT : 1; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int PS_WATCHDOG_TIMEOUT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_ACK : 1; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int PS_WATCHDOG_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int VECTOR_DST_REL : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SCALAR_DST_REL : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SCALAR_DST_REL : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int VECTOR_DST_REL : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int PAw_ID : 3; + unsigned int : 17; +#else /* !defined(qLittleEndian) */ + unsigned int : 17; + unsigned int PAw_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_HALT_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int AXI_HALT : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int AXI_HALT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int PA_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int AXI_RDY_ENA : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int PA_REQUEST : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BLEN_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BLEN_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_PA_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_PA_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int PA_MH_be : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int PA_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int CP_MH_be : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int PA_MH_send : 1; + unsigned int PA_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_addr_31_5 : 27; + unsigned int PA_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CLNT_REQ : 5; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_4 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_4 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 5; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WINNER : 3; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_REG_WE_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; +#else /* !defined(qLittleEndian) */ + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int : 2; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_NUM_BUFS : 2; +#else /* !defined(qLittleEndian) */ + unsigned int DMI_CH4_NUM_BUFS : 2; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int DMI_CH1_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH1_BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int : 2; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int : 3; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int : 3; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int : 2; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_OUT { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_BUS_OUT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEBUG_BUS_OUT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int SW_ENABLE : 1; + unsigned int : 3; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int GPIO_BYTE_LANE_ENB : 4; +#else /* !defined(qLittleEndian) */ + unsigned int GPIO_BYTE_LANE_ENB : 4; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 3; + unsigned int SW_ENABLE : 1; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int SUB_BLOCK_ADDR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 20; + unsigned int SQ_INT_STAT : 1; + unsigned int : 3; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 3; + unsigned int SQ_INT_STAT : 1; + unsigned int : 20; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int RESERVED0 : 1; + unsigned int RESERVED1 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED1 : 1; + unsigned int RESERVED0 : 1; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int RESERVED2 : 1; + unsigned int RESERVED3 : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int RESERVED3 : 1; + unsigned int RESERVED2 : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int RESERVED4 : 1; + unsigned int RESERVED5 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED5 : 1; + unsigned int RESERVED4 : 1; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int RESERVED6 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED6 : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_SPARES { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h new file mode 100644 index 000000000000..69677996b133 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h @@ -0,0 +1,4184 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT 0x00000005 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS__SHIFT 0x0000001c +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT 0x0000001d +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT 0x0000001e +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT 0x0000001f + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fposition__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fposition__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT 0x00000008 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT 0x0000001e +#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT 0x0000001f + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT 0x00000000 +#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT 0x00000001 + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT 0x00000000 +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT 0x00000001 + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT 0x00000000 +#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT 0x00000001 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 +#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT 0x0000000b +#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT 0x0000000c + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__PA_REQUEST__SHIFT 0x0000000a +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000e +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001b +#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT 0x0000001c + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x00000007 +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x00000008 +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT 0x0000000c +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x0000000d +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x0000000f +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__PA_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__PA_RTR_q__SHIFT 0x00000013 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000f +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000012 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be__SHIFT 0x00000000 +#define MH_DEBUG_REG08__RB_MH_be__SHIFT 0x00000008 +#define MH_DEBUG_REG08__PA_MH_be__SHIFT 0x00000010 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG10__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG11__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG12__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG15__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG18__PA_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG21__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG21__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG21__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG21__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG21__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG21__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG21__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG21__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG21__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG21__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG21__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG21__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG21__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG21__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG21__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG21__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG22__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG22__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG22__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG22__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG22__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG22__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG22__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG22__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG22__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG22__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG22__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG24__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG24__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG24__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG24__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT 0x00000000 +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT 0x00000001 +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT 0x00000002 +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT 0x00000004 +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT 0x00000005 +#define MH_DEBUG_REG26__CNT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT 0x0000000e +#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT 0x0000000f +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010 +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011 +#define MH_DEBUG_REG26__CP_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG26__CP_RTR_q__SHIFT 0x00000013 +#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000017 +#define MH_DEBUG_REG26__RB_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG26__RB_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG26__PA_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG26__PA_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG26__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG26__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG26__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG27__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG27__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG27__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG27__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG27__ARB_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT 0x0000001d +#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG28__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG28__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG28__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT 0x00000003 +#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT 0x00000006 +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT 0x00000009 +#define MH_DEBUG_REG29__ARB_HOLD__SHIFT 0x0000000a +#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG29__CLNT_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG29__RECENT_d_0__SHIFT 0x00000011 +#define MH_DEBUG_REG29__RECENT_d_1__SHIFT 0x00000014 +#define MH_DEBUG_REG29__RECENT_d_2__SHIFT 0x00000017 +#define MH_DEBUG_REG29__RECENT_d_3__SHIFT 0x0000001a +#define MH_DEBUG_REG29__RECENT_d_4__SHIFT 0x0000001d + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG30__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG30__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG30__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT 0x0000001c +#define MH_DEBUG_REG30__ARB_WINNER__SHIFT 0x0000001d + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG32__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG33__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG43__ARB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT 0x00000003 +#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT 0x00000004 +#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT 0x00000005 +#define MH_DEBUG_REG43__MMU_RTR__SHIFT 0x00000006 +#define MH_DEBUG_REG43__ARB_ID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT 0x0000000a +#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT 0x0000000b +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT 0x0000000d +#define MH_DEBUG_REG43__MMU_WE__SHIFT 0x00000010 +#define MH_DEBUG_REG43__ARQ_RTR__SHIFT 0x00000011 +#define MH_DEBUG_REG43__MMU_ID__SHIFT 0x00000012 +#define MH_DEBUG_REG43__MMU_WRITE__SHIFT 0x00000015 +#define MH_DEBUG_REG43__MMU_BLEN__SHIFT 0x00000016 +#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT 0x00000017 +#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT 0x00000018 +#define MH_DEBUG_REG43__WDB_WE__SHIFT 0x00000019 +#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT 0x0000001a +#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT 0x0000001b + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG44__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG45__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG45__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG46__WDB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT 0x00000003 +#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT 0x00000004 +#define MH_DEBUG_REG46__ARB_WLAST__SHIFT 0x0000000c +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT 0x0000000e +#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT 0x00000013 +#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT 0x00000014 +#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT 0x00000017 +#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT 0x00000018 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG49__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG49__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG49__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG49__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG49__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG50__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG50__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG50__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG50__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT 0x00000000 +#define MH_DEBUG_REG52__ARB_WE__SHIFT 0x00000002 +#define MH_DEBUG_REG52__MMU_RTR__SHIFT 0x00000003 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT 0x00000004 +#define MH_DEBUG_REG52__ARB_ID_q__SHIFT 0x0000001a +#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT 0x0000001d +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x0000001e + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG53__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG53__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG53__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG53__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG53__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG54__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG54__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG54__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG54__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG54__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG54__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG54__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG54__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG61__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG62__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT 0x00000000 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT 0x00000001 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT 0x00000002 +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT 0x00000003 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT 0x00000004 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT 0x00000005 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT 0x00000006 +#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT 0x00000008 +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT 0x0000000a +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT 0x0000000b +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT 0x0000000c +#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT 0x0000000d +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT 0x0000000e +#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT 0x00000010 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT 0x00000014 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT 0x00000015 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT 0x00000016 +#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT 0x00000017 +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT 0x00000018 +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT 0x0000001a +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT 0x0000001b +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT 0x0000001c +#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT 0x0000001d +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT 0x0000001e + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT 0x00000000 +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT 0x00000008 +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT 0x00000010 +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT 0x00000018 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT 0x00000010 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT 0x00000018 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT 0x00000019 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT 0x0000001d +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT 0x0000001e +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT 0x00000000 + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT 0x00000000 +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT 0x00000008 +#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT 0x0000000c +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT 0x00000010 +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT 0x00000018 +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT 0x0000001c + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT 0x0000001a +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 +#define RB_STENCILREFMASK__RESERVED0__SHIFT 0x00000018 +#define RB_STENCILREFMASK__RESERVED1__SHIFT 0x00000019 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 +#define RB_COLOR_MASK__RESERVED2__SHIFT 0x00000004 +#define RB_COLOR_MASK__RESERVED3__SHIFT 0x00000005 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 +#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT 0x00000018 +#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT 0x00000019 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED6__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h new file mode 100644 index 000000000000..21de35591e7d --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h @@ -0,0 +1,52433 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \ + RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) + +#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \ + ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \ + (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \ + (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \ + (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \ + (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \ + (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \ + (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \ + (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \ + (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \ + (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \ + (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \ + (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \ + (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \ + (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \ + (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \ + (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \ + (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \ + (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \ + (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \ + (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \ + (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \ + (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \ + (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \ + (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \ + (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int : 2; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int : 2; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \ + ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \ + (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \ + (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \ + (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \ + (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \ + (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \ + (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \ + (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int : 2; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int : 3; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int : 3; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int : 2; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG_OUT struct + */ + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff + +#define RBBM_DEBUG_OUT_MASK \ + (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) + +#define RBBM_DEBUG_OUT(debug_bus_out) \ + ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)) + +#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \ + ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \ + rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_out_t f; +} rbbm_debug_out_u; + + +/* + * RBBM_DEBUG_CNTL struct + */ + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00 +#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000 + +#define RBBM_DEBUG_CNTL_MASK \ + (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) + +#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \ + ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \ + (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \ + (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \ + (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \ + (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \ + (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)) + +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int : 3; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + } rbbm_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 3; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + } rbbm_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_cntl_t f; +} rbbm_debug_cntl_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 20; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 3; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 3; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 20; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \ + (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int : 5; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 5; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \ + MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \ + (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \ + (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int : 17; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 17; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_AXI_HALT_CONTROL struct + */ + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001 + +#define MH_AXI_HALT_CONTROL_MASK \ + (MH_AXI_HALT_CONTROL_AXI_HALT_MASK) + +#define MH_AXI_HALT_CONTROL(axi_halt) \ + ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)) + +#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \ + ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \ + mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + unsigned int : 31; + } mh_axi_halt_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int : 31; + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + } mh_axi_halt_control_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_halt_control_t f; +} mh_axi_halt_control_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 13 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00004000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000 +#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_PA_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \ + MH_DEBUG_REG00_AXI_RDY_ENA_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int : 3; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 3; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_PA_RTR_q_SIZE 1 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 11 +#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 17 +#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18 +#define MH_DEBUG_REG01_PA_RTR_q_SHIFT 19 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00000100 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00000200 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG01_TC_BLEN_q_MASK 0x00001000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00010000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00020000 +#define MH_DEBUG_REG01_PA_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG01_PA_RTR_q_MASK 0x00080000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BLEN_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_BLEN_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_PA_SEND_q_MASK | \ + MH_DEBUG_REG01_PA_RTR_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int : 12; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int : 12; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 15 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x00038000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x000c0000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_MH_PA_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 12; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 12; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_CP_MH_be_SIZE 8 +#define MH_DEBUG_REG08_RB_MH_be_SIZE 8 +#define MH_DEBUG_REG08_PA_MH_be_SIZE 8 + +#define MH_DEBUG_REG08_CP_MH_be_SHIFT 0 +#define MH_DEBUG_REG08_RB_MH_be_SHIFT 8 +#define MH_DEBUG_REG08_PA_MH_be_SHIFT 16 + +#define MH_DEBUG_REG08_CP_MH_be_MASK 0x000000ff +#define MH_DEBUG_REG08_RB_MH_be_MASK 0x0000ff00 +#define MH_DEBUG_REG08_PA_MH_be_MASK 0x00ff0000 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_CP_MH_be_MASK | \ + MH_DEBUG_REG08_RB_MH_be_MASK | \ + MH_DEBUG_REG08_PA_MH_be_MASK) + +#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \ + ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \ + (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \ + (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)) + +#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int : 8; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int : 8; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_VGT_MH_send_MASK | \ + MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK | \ + MH_DEBUG_REG10_TC_MH_mask_MASK | \ + MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG11_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_TC_MH_info_MASK | \ + MH_DEBUG_REG11_TC_MH_send_MASK) + +#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG12_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG12_TC_MH_written_MASK) + +#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG14_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG15_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG15_RB_MH_send_MASK | \ + MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG17(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG18_PA_MH_send_SIZE 1 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG18_PA_MH_send_MASK | \ + MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \ + (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \ + (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_PA_MH_data_31_0_MASK) + +#define MH_DEBUG_REG19(pa_mh_data_31_0) \ + ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_PA_MH_data_63_32_MASK) + +#define MH_DEBUG_REG20(pa_mh_data_63_32) \ + ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_AVALID_q_SIZE 1 +#define MH_DEBUG_REG21_AREADY_q_SIZE 1 +#define MH_DEBUG_REG21_AID_q_SIZE 3 +#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG21_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG21_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG21_ARID_q_SIZE 3 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG21_RVALID_q_SIZE 1 +#define MH_DEBUG_REG21_RREADY_q_SIZE 1 +#define MH_DEBUG_REG21_RLAST_q_SIZE 1 +#define MH_DEBUG_REG21_RID_q_SIZE 3 +#define MH_DEBUG_REG21_WVALID_q_SIZE 1 +#define MH_DEBUG_REG21_WREADY_q_SIZE 1 +#define MH_DEBUG_REG21_WLAST_q_SIZE 1 +#define MH_DEBUG_REG21_WID_q_SIZE 3 +#define MH_DEBUG_REG21_BVALID_q_SIZE 1 +#define MH_DEBUG_REG21_BREADY_q_SIZE 1 +#define MH_DEBUG_REG21_BID_q_SIZE 3 + +#define MH_DEBUG_REG21_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG21_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG21_AID_q_SHIFT 2 +#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG21_ARID_q_SHIFT 10 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG21_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG21_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG21_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG21_RID_q_SHIFT 18 +#define MH_DEBUG_REG21_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG21_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG21_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG21_WID_q_SHIFT 24 +#define MH_DEBUG_REG21_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG21_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG21_BID_q_SHIFT 29 + +#define MH_DEBUG_REG21_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG21_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG21_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG21_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG21_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG21_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG21_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG21_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG21_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG21_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG21_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG21_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG21_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG21_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG21_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG21_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG21_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_AVALID_q_MASK | \ + MH_DEBUG_REG21_AREADY_q_MASK | \ + MH_DEBUG_REG21_AID_q_MASK | \ + MH_DEBUG_REG21_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG21_ARVALID_q_MASK | \ + MH_DEBUG_REG21_ARREADY_q_MASK | \ + MH_DEBUG_REG21_ARID_q_MASK | \ + MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG21_RVALID_q_MASK | \ + MH_DEBUG_REG21_RREADY_q_MASK | \ + MH_DEBUG_REG21_RLAST_q_MASK | \ + MH_DEBUG_REG21_RID_q_MASK | \ + MH_DEBUG_REG21_WVALID_q_MASK | \ + MH_DEBUG_REG21_WREADY_q_MASK | \ + MH_DEBUG_REG21_WLAST_q_MASK | \ + MH_DEBUG_REG21_WID_q_MASK | \ + MH_DEBUG_REG21_BVALID_q_MASK | \ + MH_DEBUG_REG21_BREADY_q_MASK | \ + MH_DEBUG_REG21_BID_q_MASK) + +#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)) + +#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT) + +#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_AVALID_q_SIZE 1 +#define MH_DEBUG_REG22_AREADY_q_SIZE 1 +#define MH_DEBUG_REG22_AID_q_SIZE 3 +#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG22_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG22_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG22_ARID_q_SIZE 3 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG22_WVALID_q_SIZE 1 +#define MH_DEBUG_REG22_WREADY_q_SIZE 1 +#define MH_DEBUG_REG22_WLAST_q_SIZE 1 +#define MH_DEBUG_REG22_WID_q_SIZE 3 +#define MH_DEBUG_REG22_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG22_BVALID_q_SIZE 1 +#define MH_DEBUG_REG22_BREADY_q_SIZE 1 +#define MH_DEBUG_REG22_BID_q_SIZE 3 + +#define MH_DEBUG_REG22_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG22_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG22_AID_q_SHIFT 2 +#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG22_ARID_q_SHIFT 9 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG22_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG22_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG22_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG22_WID_q_SHIFT 16 +#define MH_DEBUG_REG22_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG22_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG22_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG22_BID_q_SHIFT 29 + +#define MH_DEBUG_REG22_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG22_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG22_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG22_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG22_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG22_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG22_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG22_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG22_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG22_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG22_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG22_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG22_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG22_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_AVALID_q_MASK | \ + MH_DEBUG_REG22_AREADY_q_MASK | \ + MH_DEBUG_REG22_AID_q_MASK | \ + MH_DEBUG_REG22_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG22_ARVALID_q_MASK | \ + MH_DEBUG_REG22_ARREADY_q_MASK | \ + MH_DEBUG_REG22_ARID_q_MASK | \ + MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG22_WVALID_q_MASK | \ + MH_DEBUG_REG22_WREADY_q_MASK | \ + MH_DEBUG_REG22_WLAST_q_MASK | \ + MH_DEBUG_REG22_WID_q_MASK | \ + MH_DEBUG_REG22_WSTRB_q_MASK | \ + MH_DEBUG_REG22_BVALID_q_MASK | \ + MH_DEBUG_REG22_BREADY_q_MASK | \ + MH_DEBUG_REG22_BID_q_MASK) + +#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)) + +#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT) + +#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG24_REG_A_SIZE 14 +#define MH_DEBUG_REG24_REG_RE_SIZE 1 +#define MH_DEBUG_REG24_REG_WE_SIZE 1 +#define MH_DEBUG_REG24_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG24_REG_A_SHIFT 2 +#define MH_DEBUG_REG24_REG_RE_SHIFT 16 +#define MH_DEBUG_REG24_REG_WE_SHIFT 17 +#define MH_DEBUG_REG24_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG24_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG24_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG24_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG24_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG24_REG_A_MASK | \ + MH_DEBUG_REG24_REG_RE_MASK | \ + MH_DEBUG_REG24_REG_WE_MASK | \ + MH_DEBUG_REG24_BLOCK_RS_MASK) + +#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_REG_WD_SIZE 32 + +#define MH_DEBUG_REG25_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG25_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_REG_WD_MASK) + +#define MH_DEBUG_REG25(reg_wd) \ + ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)) + +#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT) + +#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG26_CNT_q_SIZE 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG26_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 +#define MH_DEBUG_REG26_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_PA_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG26_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG26_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5 +#define MH_DEBUG_REG26_CNT_q_SHIFT 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13 +#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17 +#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18 +#define MH_DEBUG_REG26_CP_RTR_q_SHIFT 19 +#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20 +#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23 +#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24 +#define MH_DEBUG_REG26_RB_RTR_q_SHIFT 25 +#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26 +#define MH_DEBUG_REG26_PA_RTR_q_SHIFT 27 +#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020 +#define MH_DEBUG_REG26_CNT_q_MASK 0x00000fc0 +#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG26_MH_BUSY_d_MASK 0x00004000 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000 +#define MH_DEBUG_REG26_CP_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG26_CP_RTR_q_MASK 0x00080000 +#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG26_VGT_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000 +#define MH_DEBUG_REG26_RB_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG26_RB_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG26_PA_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG26_PA_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG26_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG26_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG26_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG26_CNT_q_MASK | \ + MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG26_MH_BUSY_d_MASK | \ + MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \ + MH_DEBUG_REG26_CP_SEND_q_MASK | \ + MH_DEBUG_REG26_CP_RTR_q_MASK | \ + MH_DEBUG_REG26_VGT_SEND_q_MASK | \ + MH_DEBUG_REG26_VGT_RTR_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_RB_SEND_q_MASK | \ + MH_DEBUG_REG26_RB_RTR_q_MASK | \ + MH_DEBUG_REG26_PA_SEND_q_MASK | \ + MH_DEBUG_REG26_PA_RTR_q_MASK | \ + MH_DEBUG_REG26_RDC_VALID_MASK | \ + MH_DEBUG_REG26_RDC_RLAST_MASK | \ + MH_DEBUG_REG26_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG26_BRC_VALID_MASK) + +#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG27_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG27_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG27_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG27_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG27_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24 +#define MH_DEBUG_REG27_ARB_QUAL_SHIFT 25 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG27_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG27_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG27_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG27_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG27_ARB_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG27_EFF1_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG27_EFF1_WIN_MASK | \ + MH_DEBUG_REG27_KILL_EFF1_MASK | \ + MH_DEBUG_REG27_ARB_HOLD_MASK | \ + MH_DEBUG_REG27_ARB_RTR_q_MASK | \ + MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_ARB_QUAL_MASK | \ + MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG27_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG28_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG28_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG28_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG28_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG28_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG28_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG28_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_EFF1_WINNER_MASK | \ + MH_DEBUG_REG28_ARB_WINNER_MASK | \ + MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_ARB_QUAL_MASK | \ + MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_EFF1_WIN_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_RTR_q_MASK | \ + MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG29_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG29_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_CLNT_REQ_SIZE 5 +#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9 +#define MH_DEBUG_REG29_ARB_HOLD_SHIFT 10 +#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11 +#define MH_DEBUG_REG29_CLNT_REQ_SHIFT 12 +#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17 +#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20 +#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23 +#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26 +#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038 +#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200 +#define MH_DEBUG_REG29_ARB_HOLD_MASK 0x00000400 +#define MH_DEBUG_REG29_ARB_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG29_CLNT_REQ_MASK 0x0001f000 +#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000 +#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000 +#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000 +#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000 +#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG29_ARB_HOLD_MASK | \ + MH_DEBUG_REG29_ARB_RTR_q_MASK | \ + MH_DEBUG_REG29_CLNT_REQ_MASK | \ + MH_DEBUG_REG29_RECENT_d_0_MASK | \ + MH_DEBUG_REG29_RECENT_d_1_MASK | \ + MH_DEBUG_REG29_RECENT_d_2_MASK | \ + MH_DEBUG_REG29_RECENT_d_3_MASK | \ + MH_DEBUG_REG29_RECENT_d_4_MASK) + +#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \ + ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \ + (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \ + (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)) + +#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG30_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG30_WLAST_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG30_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28 +#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG30_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000 +#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG30_TC_MH_written_MASK | \ + MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG30_WLAST_q_MASK | \ + MH_DEBUG_REG30_WBURST_IP_q_MASK | \ + MH_DEBUG_REG30_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_CP_MH_write_MASK | \ + MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_ARB_WINNER_MASK) + +#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG32_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_KILL_EFF1_MASK | \ + MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG32_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG33_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_KILL_EFF1_MASK | \ + MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG33_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_TC_MH_send_MASK | \ + MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_TC_MH_send_MASK | \ + MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_TC_MH_send_MASK | \ + MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_TC_MH_send_MASK | \ + MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_WE_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG43_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG43_MMU_WE_SIZE 1 +#define MH_DEBUG_REG43_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_ID_SIZE 3 +#define MH_DEBUG_REG43_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG43_MMU_BLEN_SIZE 1 +#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_WDB_WE_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG43_ARB_WE_SHIFT 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3 +#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5 +#define MH_DEBUG_REG43_MMU_RTR_SHIFT 6 +#define MH_DEBUG_REG43_ARB_ID_q_SHIFT 7 +#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10 +#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13 +#define MH_DEBUG_REG43_MMU_WE_SHIFT 16 +#define MH_DEBUG_REG43_ARQ_RTR_SHIFT 17 +#define MH_DEBUG_REG43_MMU_ID_SHIFT 18 +#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21 +#define MH_DEBUG_REG43_MMU_BLEN_SHIFT 22 +#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24 +#define MH_DEBUG_REG43_WDB_WE_SHIFT 25 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG43_ARB_WE_MASK 0x00000002 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG43_ARB_RTR_q_MASK 0x00000008 +#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020 +#define MH_DEBUG_REG43_MMU_RTR_MASK 0x00000040 +#define MH_DEBUG_REG43_ARB_ID_q_MASK 0x00000380 +#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400 +#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000 +#define MH_DEBUG_REG43_MMU_WE_MASK 0x00010000 +#define MH_DEBUG_REG43_ARQ_RTR_MASK 0x00020000 +#define MH_DEBUG_REG43_MMU_ID_MASK 0x001c0000 +#define MH_DEBUG_REG43_MMU_WRITE_MASK 0x00200000 +#define MH_DEBUG_REG43_MMU_BLEN_MASK 0x00400000 +#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000 +#define MH_DEBUG_REG43_WDB_WE_MASK 0x02000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000 + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \ + MH_DEBUG_REG43_ARB_WE_MASK | \ + MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \ + MH_DEBUG_REG43_ARB_RTR_q_MASK | \ + MH_DEBUG_REG43_ARB_REG_RTR_MASK | \ + MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \ + MH_DEBUG_REG43_MMU_RTR_MASK | \ + MH_DEBUG_REG43_ARB_ID_q_MASK | \ + MH_DEBUG_REG43_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG43_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG43_MMU_WE_MASK | \ + MH_DEBUG_REG43_ARQ_RTR_MASK | \ + MH_DEBUG_REG43_MMU_ID_MASK | \ + MH_DEBUG_REG43_MMU_WRITE_MASK | \ + MH_DEBUG_REG43_MMU_BLEN_MASK | \ + MH_DEBUG_REG43_WBURST_IP_q_MASK | \ + MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG43_WDB_WE_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) + +#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \ + ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \ + (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \ + (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \ + (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \ + (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \ + (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int : 4; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int : 4; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WE_SIZE 1 +#define MH_DEBUG_REG44_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG44_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG44_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG44_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG44_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG44_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG44_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WE_MASK | \ + MH_DEBUG_REG44_ARB_ID_q_MASK | \ + MH_DEBUG_REG44_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_MMU_WE_SIZE 1 +#define MH_DEBUG_REG45_MMU_ID_SIZE 3 +#define MH_DEBUG_REG45_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG45_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG45_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG45_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG45_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG45_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG45_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_MMU_WE_MASK | \ + MH_DEBUG_REG45_MMU_ID_MASK | \ + MH_DEBUG_REG45_MMU_PAD_MASK) + +#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WE_SIZE 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG46_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG46_WDB_WE_SHIFT 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4 +#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19 +#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG46_WDB_WE_MASK 0x00000002 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008 +#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0 +#define MH_DEBUG_REG46_ARB_WLAST_MASK 0x00001000 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000 +#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000 + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG46_WDB_WE_MASK | \ + MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \ + MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG46_ARB_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \ + (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RVALID_q_SIZE 1 +#define MH_DEBUG_REG49_RREADY_q_SIZE 1 +#define MH_DEBUG_REG49_RLAST_q_SIZE 1 +#define MH_DEBUG_REG49_BVALID_q_SIZE 1 +#define MH_DEBUG_REG49_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG49_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG49_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG49_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG49_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG49_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG49_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG49_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG49_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG49_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG49_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RVALID_q_MASK | \ + MH_DEBUG_REG49_RREADY_q_MASK | \ + MH_DEBUG_REG49_RLAST_q_MASK | \ + MH_DEBUG_REG49_BVALID_q_MASK | \ + MH_DEBUG_REG49_BREADY_q_MASK) + +#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT) + +#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_RID_SIZE 3 +#define MH_DEBUG_REG50_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG50_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG50_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG50_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG50_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG50_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG50_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG50_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG50_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG50_RDC_VALID_MASK | \ + MH_DEBUG_REG50_RDC_RID_MASK | \ + MH_DEBUG_REG50_RDC_RLAST_MASK | \ + MH_DEBUG_REG50_RDC_RRESP_MASK | \ + MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG51(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2 +#define MH_DEBUG_REG52_ARB_WE_SIZE 1 +#define MH_DEBUG_REG52_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22 +#define MH_DEBUG_REG52_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0 +#define MH_DEBUG_REG52_ARB_WE_SHIFT 2 +#define MH_DEBUG_REG52_MMU_RTR_SHIFT 3 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4 +#define MH_DEBUG_REG52_ARB_ID_q_SHIFT 26 +#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003 +#define MH_DEBUG_REG52_ARB_WE_MASK 0x00000004 +#define MH_DEBUG_REG52_MMU_RTR_MASK 0x00000008 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0 +#define MH_DEBUG_REG52_ARB_ID_q_MASK 0x1c000000 +#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \ + MH_DEBUG_REG52_ARB_WE_MASK | \ + MH_DEBUG_REG52_MMU_RTR_MASK | \ + MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \ + MH_DEBUG_REG52_ARB_ID_q_MASK | \ + MH_DEBUG_REG52_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK) + +#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \ + ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \ + (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \ + (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_stage1_valid_SIZE 1 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG53_tag_match_q_SIZE 1 +#define MH_DEBUG_REG53_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG53_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG53_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG53_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG53_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG53_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG53_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG53_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG53_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_stage1_valid_MASK | \ + MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG53_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG53_tag_match_q_MASK | \ + MH_DEBUG_REG53_tag_miss_q_MASK | \ + MH_DEBUG_REG53_va_in_range_q_MASK | \ + MH_DEBUG_REG53_MMU_MISS_MASK | \ + MH_DEBUG_REG53_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG53_MMU_HIT_MASK | \ + MH_DEBUG_REG53_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG54_MMU_WE_SIZE 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG54_stage1_valid_SIZE 1 +#define MH_DEBUG_REG54_stage2_valid_SIZE 1 +#define MH_DEBUG_REG54_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG54_tag_match_q_SIZE 1 +#define MH_DEBUG_REG54_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG54_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG54_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG54_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG54_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG54_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG54_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG54_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG54_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_ARQ_RTR_MASK | \ + MH_DEBUG_REG54_MMU_WE_MASK | \ + MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG54_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG54_stage1_valid_MASK | \ + MH_DEBUG_REG54_stage2_valid_MASK | \ + MH_DEBUG_REG54_client_behavior_q_MASK | \ + MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG54_tag_match_q_MASK | \ + MH_DEBUG_REG54_tag_miss_q_MASK | \ + MH_DEBUG_REG54_va_in_range_q_MASK | \ + MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_MASK) + +#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG55_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG55_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG0_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG1_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG56_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG56_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG2_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG3_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG57_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG57_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG4_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG5_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG58_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG58_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG6_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG7_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG59_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG59_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG8_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG9_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG60_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG60_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG10_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG11_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG61_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG61_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG61_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG61_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG61_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_TAG12_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG61_TAG13_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG62_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG62_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG62_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG62_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG62_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_TAG14_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG62_TAG15_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \ + (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int : 6; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 6; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_FACE_DATA struct + */ + +#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27 + +#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5 + +#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0 + +#define PA_SU_FACE_DATA_MASK \ + (PA_SU_FACE_DATA_BASE_ADDR_MASK) + +#define PA_SU_FACE_DATA(base_addr) \ + ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)) + +#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \ + ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \ + pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int : 5; + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + } pa_su_face_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + unsigned int : 5; + } pa_su_face_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_face_data_t f; +} pa_su_face_data_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT 28 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK 0x10000000 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \ + PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, clamped_faceness, zero_area_faceness, face_kill_enable, face_write_enable) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \ + (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) | \ + (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \ + (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \ + (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CLAMPED_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CLAMPED_FACENESS(pa_su_sc_mode_cntl_reg, clamped_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) | (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 1; + unsigned int clamped_faceness : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int clamped_faceness : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fposition_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fposition_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fposition_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fposition_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fposition << SC_DEBUG_7_fposition_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fposition(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fposition_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fposition_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fposition_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fposition_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fposition << SC_DEBUG_8_fposition_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fposition(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int : 1; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 1; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 +#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1 +#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30 +#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000 +#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000 + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK | \ + VGT_BIN_SIZE_FACENESS_FETCH_MASK | \ + VGT_BIN_SIZE_FACENESS_RESET_MASK) + +#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \ + (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \ + (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_VS_WATCHDOG_TIMER struct + */ + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_VS_WATCHDOG_TIMER_MASK \ + (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_vs_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_vs_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_watchdog_timer_t f; +} sq_vs_watchdog_timer_u; + + +/* + * SQ_PS_WATCHDOG_TIMER struct + */ + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_PS_WATCHDOG_TIMER_MASK \ + (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_ps_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_ps_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_watchdog_timer_t f; +} sq_ps_watchdog_timer_u; + + +/* + * SQ_INT_CNTL struct + */ + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002 + +#define SQ_INT_CNTL_MASK \ + (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \ + SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) + +#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \ + ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \ + (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)) + +#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int : 30; + } sq_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int : 30; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + } sq_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_cntl_t f; +} sq_int_cntl_u; + + +/* + * SQ_INT_STATUS struct + */ + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002 + +#define SQ_INT_STATUS_MASK \ + (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \ + SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) + +#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \ + ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \ + (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)) + +#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int : 30; + } sq_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int : 30; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + } sq_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_status_t f; +} sq_int_status_u; + + +/* + * SQ_INT_ACK struct + */ + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002 + +#define SQ_INT_ACK_MASK \ + (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \ + SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) + +#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \ + ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \ + (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)) + +#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int : 30; + } sq_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int : 30; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + } sq_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_ack_t f; +} sq_int_ack_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 +#define RB_STENCILREFMASK_RESERVED0_SIZE 1 +#define RB_STENCILREFMASK_RESERVED1_SIZE 1 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 +#define RB_STENCILREFMASK_RESERVED0_SHIFT 24 +#define RB_STENCILREFMASK_RESERVED1_SHIFT 25 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 +#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000 +#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \ + RB_STENCILREFMASK_RESERVED0_MASK | \ + RB_STENCILREFMASK_RESERVED1_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \ + (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \ + (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int : 6; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 6; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 +#define RB_COLOR_MASK_RESERVED2_SIZE 1 +#define RB_COLOR_MASK_RESERVED3_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 +#define RB_COLOR_MASK_RESERVED2_SHIFT 4 +#define RB_COLOR_MASK_RESERVED3_SHIFT 5 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 +#define RB_COLOR_MASK_RESERVED2_MASK 0x00000010 +#define RB_COLOR_MASK_RESERVED3_MASK 0x00000020 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK | \ + RB_COLOR_MASK_RESERVED2_MASK | \ + RB_COLOR_MASK_RESERVED3_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \ + (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \ + (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int : 26; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 26; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1 +#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 +#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24 +#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 +#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000 +#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_RESERVED4_MASK | \ + RB_STENCILREFMASK_BF_RESERVED5_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \ + (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \ + (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int : 6; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 6; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_CRC_SYSTEM_SIZE 1 +#define RB_BC_CONTROL_RESERVED6_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30 +#define RB_BC_CONTROL_RESERVED6_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_CRC_SYSTEM_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED6_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_CRC_SYSTEM_MASK | \ + RB_BC_CONTROL_RESERVED6_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \ + (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * RB_BC_SPARES struct + */ + +#define RB_BC_SPARES_RESERVED_SIZE 32 + +#define RB_BC_SPARES_RESERVED_SHIFT 0 + +#define RB_BC_SPARES_RESERVED_MASK 0xffffffff + +#define RB_BC_SPARES_MASK \ + (RB_BC_SPARES_RESERVED_MASK) + +#define RB_BC_SPARES(reserved) \ + ((reserved << RB_BC_SPARES_RESERVED_SHIFT)) + +#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \ + ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT) + +#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \ + rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_spares_t f; +} rb_bc_spares_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h new file mode 100644 index 000000000000..6968abb48bd7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h @@ -0,0 +1,550 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_FACE_DATA regPA_SU_FACE_DATA; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_VS_WATCHDOG_TIMER regSQ_VS_WATCHDOG_TIMER; +typedef union SQ_PS_WATCHDOG_TIMER regSQ_PS_WATCHDOG_TIMER; +typedef union SQ_INT_CNTL regSQ_INT_CNTL; +typedef union SQ_INT_STATUS regSQ_INT_STATUS; +typedef union SQ_INT_ACK regSQ_INT_ACK; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_AXI_HALT_CONTROL regMH_AXI_HALT_CONTROL; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG_OUT regRBBM_DEBUG_OUT; +typedef union RBBM_DEBUG_CNTL regRBBM_DEBUG_CNTL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union RB_BC_SPARES regRB_BC_SPARES; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif diff --git a/drivers/mxc/amd-gpu/os/include/os_types.h b/drivers/mxc/amd-gpu/os/include/os_types.h new file mode 100644 index 000000000000..e7ecd90f8952 --- /dev/null +++ b/drivers/mxc/amd-gpu/os/include/os_types.h @@ -0,0 +1,138 @@ + /* Copyright (c) 2008-2010, QUALCOMM Incorporated. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of QUALCOMM Incorporated nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __OSTYPES_H +#define __OSTYPES_H + +////////////////////////////////////////////////////////////////////////////// +// status +////////////////////////////////////////////////////////////////////////////// +#define OS_SUCCESS 0 +#define OS_FAILURE -1 +#define OS_FAILURE_SYSTEMERROR -2 +#define OS_FAILURE_DEVICEERROR -3 +#define OS_FAILURE_OUTOFMEM -4 +#define OS_FAILURE_BADPARAM -5 +#define OS_FAILURE_NOTSUPPORTED -6 +#define OS_FAILURE_NOMOREAVAILABLE -7 +#define OS_FAILURE_NOTINITIALIZED -8 +#define OS_FAILURE_ALREADYINITIALIZED -9 +#define OS_FAILURE_TIMEOUT -10 + + +////////////////////////////////////////////////////////////////////////////// +// inline +////////////////////////////////////////////////////////////////////////////// +#ifndef OSINLINE +#ifdef _LINUX +#define OSINLINE static __inline +#else +#define OSINLINE __inline +#endif +#endif // OSINLINE + + +////////////////////////////////////////////////////////////////////////////// +// values +////////////////////////////////////////////////////////////////////////////// +#define OS_INFINITE 0xFFFFFFFF +#define OS_TLS_OUTOFINDEXES 0xFFFFFFFF +#define OS_TRUE 1 +#define OS_FALSE 0 + +#ifndef NULL +#define NULL (void *)0x0 +#endif // !NULL + +////////////////////////////////////////////////////////////////////////////// +// types +////////////////////////////////////////////////////////////////////////////// + + +// +// oshandle_t +// +typedef void * oshandle_t; +#define OS_HANDLE_NULL (oshandle_t)0x0 + +// +// os_sysinfo_t +// +typedef struct _os_sysinfo_t { + int cpu_mhz; + int cpu_type; + int cpu_version; + int os_type; + int os_version; + int sysmem_size; + int page_size; + int max_path; + int tls_slots; + int endianness; // 0 == little_endian, 1 == big_endian +} os_sysinfo_t; + + +// +// os_stats_t +// +#ifdef _LINUX +typedef long long __int64; +typedef unsigned long long __uint64; +#else +typedef unsigned __int64 __uint64; +#endif + +typedef struct _os_stats_t { + __int64 heap_allocs; + __int64 heap_frees; + __int64 heap_alloc_bytes; + __int64 shared_heap_allocs; + __int64 shared_heap_frees; + __int64 shared_heap_alloc_bytes; + __int64 objects_alloc; + __int64 objects_free; +} os_stats_t; + + +typedef enum { + OS_PROTECTION_GLOBAL, // inter process + OS_PROTECTION_LOCAL, // process local + OS_PROTECTION_NONE, // none +} os_protection_t; + +typedef struct _os_cputimer_t { + int refcount; // Reference count + int enabled; // Counter is enabled + int size; // Number of counters + __int64 start_time; // start time in cpu ticks + __int64 end_time; // end time in cpu ticks + __int64 timer_frequency; // cpu ticks per second + __int64 *counter_array; // number of ticks for each counter +} os_cputimer_t; + +#endif // __OSTYPES_H diff --git a/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h new file mode 100644 index 000000000000..a02c396c22a9 --- /dev/null +++ b/drivers/mxc/amd-gpu/os/kernel/include/kos_libapi.h @@ -0,0 +1,813 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __KOSAPI_H +#define __KOSAPI_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "os_types.h" + + +////////////////////////////////////////////////////////////////////////////// +// entrypoint abstraction +////////////////////////////////////////////////////////////////////////////// + + +#if defined(_WIN32) && !defined (_WIN32_WCE) && !defined(__SYMBIAN32__) +#define KOS_DLLEXPORT __declspec(dllexport) +#define KOS_DLLIMPORT __declspec(dllimport) +#elif defined(_WIN32) && defined (_WIN32_WCE) +#define KOS_DLLEXPORT __declspec(dllexport) +#define KOS_DLLIMPORT +#else +#define KOS_DLLEXPORT extern +#define KOS_DLLIMPORT +#endif // _WIN32 + + +////////////////////////////////////////////////////////////////////////////// +// KOS lib entrypoints +////////////////////////////////////////////////////////////////////////////// +#ifdef __KOSLIB_EXPORTS +#define KOS_API KOS_DLLEXPORT +#else +#define KOS_API KOS_DLLIMPORT +#endif // __KOSLIB_EXPORTS + +////////////////////////////////////////////////////////////////////////////// +// assert API +////////////////////////////////////////////////////////////////////////////// +KOS_API void kos_assert_hook(const char* file, int line, int expression); + +#if defined(DEBUG) || defined(DBG) || defined (_DBG) || defined (_DEBUG) + +#if defined(_WIN32) && !defined(__SYMBIAN32__) || defined(_WIN32_WCE) +#include +#define KOS_ASSERT(expression) assert(expression) +#elif defined(_BREW) +#include +#define KOS_ASSERT(expression) kos_assert_hook(__FILE__, __LINE__, expression) +#elif defined(__SYMBIAN32__) +//#include +//#define KOS_ASSERT(expression) assert(expression) +#define KOS_ASSERT(expression) /**/ +#elif defined(__ARM__) +#define KOS_ASSERT(expression) +#elif defined(_LINUX) +#define KOS_ASSERT(expression) //kos_assert_hook(__FILE__, __LINE__, (int)(expression)) +#endif + +#else + +#define KOS_ASSERT(expression) + +#endif // DEBUG || DBG || _DBG + +#if defined(_WIN32) && defined(_DEBUG) && !defined(_WIN32_WCE) && !defined(__SYMBIAN32__) +#pragma warning ( push, 3 ) +#include +#pragma warning (pop) +#define KOS_MALLOC_DBG(size) _malloc_dbg(size, _NORMAL_BLOCK, __FILE__, __LINE__) +#else +#define KOS_MALLOC_DBG(size) kos_malloc(int size) +#endif // _WIN32 _DEBUG + +#define kos_assert(expression) KOS_ASSERT(expression) +#define kos_malloc_dbg(size) KOS_MALLOC_DBG(size) + +#ifdef UNDER_CE +#define KOS_PAGE_SIZE 0x1000 +#endif + +typedef enum mutexIndex mutexIndex_t; +////////////////////////////////////////////////////////////////////////////// +// Interprocess shared memory initialization +////////////////////////////////////////////////////////////////////////////// +// TODO: still valid? +KOS_API int kos_sharedmem_create(unsigned int map_addr, unsigned int size); +KOS_API int kos_sharedmem_destroy(void); + +////////////////////////////////////////////////////////////////////////////// +// heap API (per process) +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate memory for a kernel side process. + * + * + * \param int size Amount of bytes to be allocated. + * \return Pointer to the reserved memory, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_malloc(int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate memory for a kernel side process. Clears the reserved memory. + * + * + * \param int num Number of elements to allocate. + * \param int size Element size in bytes. + * \return Pointer to the reserved memory, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_calloc(int num, int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Re-allocate an existing memory for a kernel side process. + * Contents of the old block will be copied to the new block + * taking the sizes of both blocks into account. + * + * + * \param void* memblock Pointer to the old memory block. + * \param int size Size of the new block in bytes. + * \return Pointer to the new memory block, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_realloc(void* memblock, int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free a reserved memory block from the kernel side process. + * + * + * \param void* memblock Pointer to the memory block. + *//*-------------------------------------------------------------------*/ +KOS_API void kos_free(void* memblock); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Enable automatic memory leak checking performed at program exit. + * + * + *//*-------------------------------------------------------------------*/ +KOS_API void kos_enable_memoryleakcheck(void); + + +////////////////////////////////////////////////////////////////////////////// +// shared heap API (cross process) +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate memory that can be shared between user and kernel + * side processes. + * + * + * \param int size Amount of bytes to be allocated. + * \return Pointer to the new memory block, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_shared_malloc(int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate memory that can be shared between user and kernel + * side processes. Clears the reserved memory. + * + * + * \param int num Number of elements to allocate. + * \param int size Element size in bytes. + * \return Pointer to the reserved memory, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_shared_calloc(int num, int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Re-allocate an existing user/kernel shared memory block. + * Contents of the old block will be copied to the new block + * taking the sizes of both blocks into account. + * + * + * \param void* ptr Pointer to the old memory block. + * \param int size Size of the new block in bytes. + * \return Pointer to the new memory block, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_shared_realloc(void* ptr, int size); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free a reserved shared memory block. + * + * + * \param void* ptr Pointer to the memory block. + *//*-------------------------------------------------------------------*/ + KOS_API void kos_shared_free(void* ptr); + + +////////////////////////////////////////////////////////////////////////////// +// memory API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Copies the values of num bytes from the location pointed by src + * directly to the memory block pointed by dst. + * + * + * \param void* dst Pointer to the destination memory block. + * \param void* src Pointer to the source memory block. + * \param void* count Amount of bytes to copy. + * \return Returns the dst pointer, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_memcpy(void* dst, const void* src, int count); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Fills the destination memory block with the given value. + * + * + * \param void* dst Pointer to the destination memory block. + * \param int value Value to be written to each destination address. + * \param void* count Number of bytes to be set to the value. + * \return Returns the dst pointer, NULL if any error. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_memset(void* dst, int value, int count); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Compares two memory blocks. + * + * + * \param void* dst Pointer to the destination memory block. + * \param void* src Pointer to the source memory block. + * \param void* count Number of bytes to compare. + * \return Zero if identical, >0 if first nonmatching byte is greater in dst. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_memcmp(void* dst, void* src, int count); + + +////////////////////////////////////////////////////////////////////////////// +// physical memory API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocates a physically contiguous memory block. + * + * + * \param void** virt_addr Pointer where to store the virtual address of the reserved block. + * \param void** phys_addr Pointer where to store the physical address of the reserved block. + * \param int pages Number of pages to reserve (default page size = 4096 bytes). + * \return Zero if ok, othervise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_alloc_physical(void** virt_addr, void** phys_addr, int pages); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free a physically contiguous allocated memory block. + * + * + * \param void* virt_addr Virtual address of the memory block. + * \param int pages Number of pages. + * \return Zero if ok, othervise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_free_physical(void* virt_addr, int pages); + +KOS_API void kos_memoryfence(void); + + +////////////////////////////////////////////////////////////////////////////// +// string API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Perform a string copy. + * + * + * \param void* strdestination Pointer to destination memory. + * \param void* strsource Pointer to the source string. + * \return Zero if ok, othervise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API char* kos_strcpy(char* strdestination, const char* strsource); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Perform a string copy with given length. + * + * + * \param void* destination Pointer to destination memory. + * \param void* source Pointer to the source string. + * \param int length Amount of bytes to copy. + * \return Returns the destination pointer. + *//*-------------------------------------------------------------------*/ +KOS_API char* kos_strncpy(char* destination, const char* source, int length); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Append source string to destination string. + * + * + * \param void* strdestination Pointer to destination string. + * \param void* strsource Pointer to the source string. + * \return Returns the destination pointer. + *//*-------------------------------------------------------------------*/ +KOS_API char* kos_strcat(char* strdestination, const char* strsource); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Compare two strings. + * + * + * \param void* string1 Pointer to first string. + * \param void* string2 Pointer to second string. + * \param void* length Number of bytes to compare. + * \return Zero if identical, >0 if first string is lexically greater <0 if not. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_strcmp(const char* string1, const char* string2); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Compares two strings of given length. + * + * + * \param void* string1 Pointer to first string. + * \param void* string2 Pointer to second string. + * \param void* length Number of bytes to compare. + * \return Zero if identical, >0 if first string is lexically greater <0 if not. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_strncmp(const char* string1, const char* string2, int length); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Calculates the length of a string.. + * + * + * \param void* string Pointer to the string. + * \return Lenght of the string in bytes. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_strlen(const char* string); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Convert an numeric ascii string to integer value. + * + * + * \param void* string Pointer to the string. + * \return Integer value extracted from the string. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_atoi(const char* string); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Convert string to unsigned long integer. + * + * + * \param void* nptr Pointer to the string. + * \param char** endptr If not null, will be set to point to the next character after the number. + * \param int base Base defining the type of the numeric string. + * \return Unsigned integer value extracted from the string. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_strtoul(const char* nptr, char** endptr, int base); + + +////////////////////////////////////////////////////////////////////////////// +// sync API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Create a mutex instance. + * + * + * \param void* name Name string for the new mutex. + * \return Returns a handle to the mutex. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_mutex_create(const char* name); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get a handle to an already existing mutex. + * + * + * \param void* name Name string for the new mutex. + * \return Returns a handle to the mutex. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_mutex_open(const char* name); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free the given mutex. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_free(oshandle_t mutexhandle); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Lock the given mutex. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_lock(oshandle_t mutexhandle); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Try to lock the given mutex, if already locked returns immediately. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_locktry(oshandle_t mutexhandle); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Try to lock the given mutex by waiting for its release. Returns without locking if the + * mutex is already locked and cannot be acquired within the given period. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \param int millisecondstowait Time to wait for the mutex to be available. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_lockwait(oshandle_t mutexhandle, int millisecondstowait); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Unlock the given mutex. + * + * + * \param oshandle_t mutexhandle Handle to the mutex. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_mutex_unlock(oshandle_t mutexhandle); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Increments (increases by one) the value of the specified 32-bit variable as an atomic operation. + * + * + * \param int* ptr Pointer to the value to be incremented. + * \return Returns the new incremented value. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_incr(int* ptr); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Decrements (decreases by one) the value of the specified 32-bit variable as an atomic operation. + * + * + * \param int* ptr Pointer to the value to be decremented. + * \return Returns the new decremented value. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_decr(int* ptr); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Atomic replacement of a value. + * + * + * \param int* ptr Pointer to the value to be replaced. + * \param int value The new value. + * \return Returns the old value. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_xchg(int* ptr, int value); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Perform an atomic compare-and-exchange operation on the specified values. Compares the two specified 32-bit values and exchanges +* with another 32-bit value based on the outcome of the comparison. + * + * + * \param int* ptr Pointer to the value to be replaced. + * \param int value The new value. + * \param int compvalue Value to be compared with. + * \return Returns the initial value of the first given parameter. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_compxchg(int* ptr, int value, int compvalue); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Atomic addition of two 32-bit values. + * + * + * \param int* ptr Pointer to the target value. + * \param int value Value to be added to the target. + * \return Returns the initial value of the target. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interlock_xchgadd(int* ptr, int value); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Create an event semaphore. + * + * + * \param int a_manualReset Selection for performing reset manually (or by the system). + * \return Returns an handle to the created semaphore. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_event_create(int a_manualReset); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Destroy an event semaphore. + * + * + * \param oshandle_t a_event Handle to the semaphore. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_event_destroy(oshandle_t a_event); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Signal an event semaphore. + * + * + * \param oshandle_t a_event Handle to the semaphore. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_event_signal(oshandle_t a_event); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Reset an event semaphore. + * + * + * \param oshandle_t a_event Handle to the semaphore. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_event_reset(oshandle_t a_event); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Wait for an event semaphore to be freed and acquire it. + * + * + * \param oshandle_t a_event Handle to the semaphore. + * \param int a_milliSeconds Time to wait. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_event_wait(oshandle_t a_event, int a_milliSeconds); + + +////////////////////////////////////////////////////////////////////////////// +// interrupt handler API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Enable an interrupt with specified id. + * + * + * \param int interrupt Identification number for the interrupt. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interrupt_enable(int interrupt); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Disable an interrupt with specified id. + * + * + * \param int interrupt Identification number for the interrupt. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interrupt_disable(int interrupt); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Set the callback function for an interrupt. + * + * + * \param int interrupt Identification number for the interrupt. + * \param void* handler Pointer to the callback function. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interrupt_setcallback(int interrupt, void* handler); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Remove a callback function from an interrupt. + * + * + * \param int interrupt Identification number for the interrupt. + * \param void* handler Pointer to the callback function. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_interrupt_clearcallback(int interrupt, void* handler); + + +////////////////////////////////////////////////////////////////////////////// +// thread and process API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Allocate an entry from the thread local storage table. + * + * + * \return Index of the reserved entry. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_tls_alloc(void); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Free an entry from the thread local storage table. + * + * + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_tls_free(unsigned int tlsindex); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Read the value of an entry in the thread local storage table. + * + * + * \param unsigned int tlsindex Index of the entry. + * \return Returns the value of the entry. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_tls_read(unsigned int tlsindex); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Write a value to an entry in the thread local storage table. + * + * + * \param unsigned int tlsindex Index of the entry. + * \param void* tlsvalue Value to be written. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_tls_write(unsigned int tlsindex, void* tlsvalue); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Put the thread to sleep for the given time period. + * + * + * \param unsigned int milliseconds Time in milliseconds. + *//*-------------------------------------------------------------------*/ +KOS_API void kos_sleep(unsigned int milliseconds); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the id of the current process. + * + * + * \return Returns the process id. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_process_getid(void); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the id of the current caller process. + * + * + * \return Returns the caller process id. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_callerprocess_getid(void); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the id of the current thread. + * + * + * \return Returns the thread id. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_thread_getid(void); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Create a new thread. + * + * + * \param oshandle_t a_function Handle to the function to be executed in the thread. + * \param unsigned int* a_threadId Pointer to a value where to store the ID of the new thread. + * \return Returns an handle to the created thread. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_thread_create(oshandle_t a_function, unsigned int* a_threadId); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Destroy the given thread. + * + * + * \param oshandle_t a_task Handle to the thread to be destroyed. + *//*-------------------------------------------------------------------*/ +KOS_API void kos_thread_destroy( oshandle_t a_task ); + +////////////////////////////////////////////////////////////////////////////// +// timing API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the current time as a timestamp. + * + * + * \return Returns the timestamp. + *//*-------------------------------------------------------------------*/ +KOS_API unsigned int kos_timestamp(void); + + +////////////////////////////////////////////////////////////////////////////// +// libary API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Map the given library (not required an all OS'es). + * + * + * \param char* libraryname The name string of the lib. + * \return Returns a handle for the lib. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_lib_map(char* libraryname); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Unmap the given library. + * + * \param oshandle_t libhandle Handle to the lib. + * \return Returns an error code incase of an error. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_lib_unmap(oshandle_t libhandle); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get the address of a lib. + * + * \param oshandle_t libhandle Handle to the lib. + * \return Returns a pointer to the lib. + *//*-------------------------------------------------------------------*/ +KOS_API void* kos_lib_getaddr(oshandle_t libhandle, char* procname); + + +////////////////////////////////////////////////////////////////////////////// +// query API +////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get device system info. + * + * \param os_sysinfo_t* sysinfo Pointer to the destination sysinfo structure. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_get_sysinfo(os_sysinfo_t* sysinfo); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Get system status info. + * + * \param os_stats_t* stats Pointer to the destination stats structure. + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_get_stats(os_stats_t* stats); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block start + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_start(void); +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block end + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_end(void); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block start with argument + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_start_ex( mutexIndex_t a_index ); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block start with argument + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_end_ex( mutexIndex_t a_index ); + +////////////////////////////////////////////////////////////////////////////// +// file API +////////////////////////////////////////////////////////////////////////////// + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Opens a file + * + * \param const char* filename Name of the file to open. + * \param const char* mode Mode used for file opening. See fopen. + * \return Returns file handle or NULL if error. + *//*-------------------------------------------------------------------*/ +KOS_API oshandle_t kos_fopen(const char* filename, const char* mode); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Writes to a file + * + * \param oshandle_t file Handle of the file to write to. + * \param const char* format Format string. See fprintf. + * \return Returns the number of bytes written + *//*-------------------------------------------------------------------*/ +KOS_API int kos_fprintf(oshandle_t file, const char* format, ...); + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Closes a file + * + * \param oshandle_t file Handle of the file to close. + * \return Returns zero if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_fclose(oshandle_t file); + +#ifdef __SYMBIAN32__ +KOS_API void kos_create_dfc(void); +KOS_API void kos_signal_dfc(void); +KOS_API void kos_enter_critical_section(); +KOS_API void kos_leave_critical_section(); +#endif // __SYMBIAN32__ + +#ifdef __cplusplus +} +#endif // __cplusplus +#endif // __KOSAPI_H diff --git a/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c new file mode 100644 index 000000000000..4ead84ffe0dc --- /dev/null +++ b/drivers/mxc/amd-gpu/os/kernel/src/linux/kos_lib.c @@ -0,0 +1,661 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "kos_libapi.h" + +////////////////////////////////////////////////////////////////////////////// +// defines +////////////////////////////////////////////////////////////////////////////// +//#define KOS_STATS_ENABLE + +////////////////////////////////////////////////////////////////////////////// +// macros +////////////////////////////////////////////////////////////////////////////// +#define KOS_MALLOC(s) kmalloc(s, GFP_KERNEL) +#define KOS_CALLOC(num, size) kcalloc(num, size, GFP_KERNEL) +#define KOS_REALLOC(p, s) krealloc(p, s, GFP_KERNEL) +#define KOS_FREE(p) kfree(p); p = 0 +#define KOS_DBGFLAGS_SET(flag) + +////////////////////////////////////////////////////////////////////////////// +// stats +////////////////////////////////////////////////////////////////////////////// +#ifdef KOS_STATS_ENABLE +os_stats_t kos_stats = {0, 0, 0, 0, 0, 0, 0, 0}; +#define KOS_STATS(x) x +#else +#define KOS_STATS(x) +#endif + +////////////////////////////////////////////////////////////////////////////// +// assert API +////////////////////////////////////////////////////////////////////////////// +KOS_API void +kos_assert_hook(const char* file, int line, int expression) +{ + if (expression) + { + return; + } + else + { + printk(KERN_ERR "Assertion failed at %s:%d!\n", file, line); + //BUG(); + } + + // put breakpoint here +} + + +////////////////////////////////////////////////////////////////////////////// +// heap API (per process) +////////////////////////////////////////////////////////////////////////////// +KOS_API void* +kos_malloc(int size) +{ + void* ptr = KOS_MALLOC(size); + + KOS_ASSERT(ptr); + KOS_STATS(kos_stats.heap_allocs++); + KOS_STATS(kos_stats.heap_alloc_bytes += size); + + return (ptr); +} + + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_calloc(int num, int size) +{ + void* ptr = KOS_CALLOC(num, size); + + KOS_ASSERT(ptr); + KOS_STATS(kos_stats.heap_allocs++); + KOS_STATS(kos_stats.heap_alloc_bytes += (size * num)); + + return (ptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_realloc(void* ptr, int size) +{ + void* newptr; + + KOS_ASSERT(ptr); + newptr = KOS_REALLOC(ptr, size); + + KOS_ASSERT(newptr); + + return (newptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_free(void* ptr) +{ + KOS_STATS(kos_stats.heap_frees++); + + KOS_FREE(ptr); +} + + +////////////////////////////////////////////////////////////////////////////// +// shared heap API (cross process) +////////////////////////////////////////////////////////////////////////////// +KOS_API void* +kos_shared_malloc(int size) +{ + void* ptr; + + ptr = NULL; // shared alloc + + KOS_ASSERT(ptr); + KOS_STATS(kos_stats.shared_heap_allocs++); + KOS_STATS(kos_stats.shared_heap_alloc_bytes += size); + + return (ptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_shared_calloc(int num, int size) +{ + void* ptr; + + ptr = NULL; // shared calloc + + KOS_ASSERT(ptr); + KOS_STATS(kos_stats.shared_heap_allocs++); + KOS_STATS(kos_stats.shared_heap_alloc_bytes += (size * num)); + return (ptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_shared_realloc(void* ptr, int size) +{ + void* newptr; + (void) ptr; // unreferenced formal parameter + (void) size; // unreferenced formal parameter + + newptr = NULL; // shared realloc + + KOS_ASSERT(newptr); + + return (newptr); +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_shared_free(void* ptr) +{ + (void) ptr; // unreferenced formal parameter + KOS_ASSERT(0); // not implemented + + KOS_STATS(kos_stats.shared_heap_frees++); + + // shared free +} + +////////////////////////////////////////////////////////////////////////////// +// memory access API +////////////////////////////////////////////////////////////////////////////// +KOS_API void* +kos_memcpy(void* dst, const void* src, int count) +{ + KOS_ASSERT(src); + KOS_ASSERT(dst); + return memcpy(dst, src, count); +} + +//---------------------------------------------------------------------------- + +KOS_API void* +kos_memset(void* dst, int value, int count) +{ + KOS_ASSERT(dst); + return memset(dst, value, count); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_memcmp(void* dst, void* src, int count) +{ + KOS_ASSERT(src); + KOS_ASSERT(dst); + return memcmp(dst, src, count); +} + +////////////////////////////////////////////////////////////////////////////// +// physical memory API +////////////////////////////////////////////////////////////////////////////// +KOS_API int +kos_alloc_physical(void** virt_addr, void** phys_addr, int pages) +{ + *virt_addr = dma_alloc_coherent(NULL, pages*PAGE_SIZE, (dma_addr_t*)*phys_addr, GFP_DMA | GFP_KERNEL); + return *virt_addr ? OS_SUCCESS : OS_FAILURE; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_free_physical(void* virt_addr, int pages) +{ + (void) virt_addr; // unreferenced formal parameter + (void) pages; // unreferenced formal parameter + + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_map_physical(void** virt_addr, void** phys_addr, int pages) +{ + (void) virt_addr; // unreferenced formal parameter + (void) phys_addr; // unreferenced formal parameter + (void) pages; // unreferenced formal parameter + + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_unmap_physical(void* virt_addr, int pages) +{ + (void) virt_addr; // unreferenced formal parameter + (void) pages; // unreferenced formal parameter + + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_memoryfence(void) +{ +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_enable_memoryleakcheck(void) +{ + // perform automatic leak checking at program exit + KOS_DBGFLAGS_SET(_CRTDBG_ALLOC_MEM_DF | _CRTDBG_LEAK_CHECK_DF); +} + +////////////////////////////////////////////////////////////////////////////// +// string API +////////////////////////////////////////////////////////////////////////////// + +KOS_API char* +kos_strcpy(char* strdestination, const char* strsource) +{ + KOS_ASSERT(strdestination); + KOS_ASSERT(strsource); + return strcpy(strdestination, strsource); +} + +//---------------------------------------------------------------------------- + +KOS_API char* +kos_strncpy(char* destination, const char* source, int length) +{ + KOS_ASSERT(destination); + KOS_ASSERT(source); + return strncpy(destination, source, length); +} + +//---------------------------------------------------------------------------- + +KOS_API char* +kos_strcat(char* strdestination, const char* strsource) +{ + KOS_ASSERT(strdestination); + KOS_ASSERT(strsource); + return strcat(strdestination, strsource); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_strcmp(const char* string1, const char* string2) +{ + KOS_ASSERT(string1); + KOS_ASSERT(string2); + return strcmp(string1, string2); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_strncmp(const char* string1, const char* string2, int length) +{ + KOS_ASSERT(string1); + KOS_ASSERT(string2); + return strncmp(string1, string2, length); +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_strlen(const char* string) +{ + KOS_ASSERT(string); + return strlen(string); +} + +////////////////////////////////////////////////////////////////////////////// +// sync API +////////////////////////////////////////////////////////////////////////////// + +KOS_API oshandle_t +kos_mutex_create(const char *name) +{ + struct mutex *mutex = KOS_MALLOC(sizeof(struct mutex)); + if (!mutex) + return 0; + mutex_init(mutex); + return mutex; +} + +//---------------------------------------------------------------------------- + +KOS_API oshandle_t +kos_mutex_open(const char *name) +{ + // not implemented + return 0; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_mutex_free(oshandle_t mutexhandle) +{ + struct mutex *mutex = (struct mutex *)mutexhandle; + if (!mutex) + return OS_FAILURE; + KOS_FREE(mutex); + return OS_SUCCESS; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_mutex_lock(oshandle_t mutexhandle) +{ + struct mutex *mutex = (struct mutex *)mutexhandle; + if (!mutex) + return OS_FAILURE; + if (mutex_lock_interruptible(mutex) == -EINTR) + return OS_FAILURE; + return OS_SUCCESS; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_mutex_locktry(oshandle_t mutexhandle) +{ + struct mutex *mutex = (struct mutex *)mutexhandle; + if (!mutex) + return OS_FAILURE; + if (!mutex_trylock(mutex)) + return OS_FAILURE; + return OS_SUCCESS; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_mutex_unlock(oshandle_t mutexhandle) +{ + struct mutex *mutex = (struct mutex *)mutexhandle; + if (!mutex) + return OS_FAILURE; + KOS_ASSERT(mutex_is_locked(mutex)); + mutex_unlock(mutex); + return OS_SUCCESS; +} + +//---------------------------------------------------------------------------- + +KOS_API unsigned int +kos_process_getid(void) +{ + return current->tgid; +} + +//---------------------------------------------------------------------------- + +/* ------------------------------------------------------------------- *//* + * \brief Creates new event semaphore + * \param uint32 a_manualReset + * When this param is zero, system automatically resets the + * event state to nonsignaled after waiting thread has been + * released + * \return oshandle_t +*//* ------------------------------------------------------------------- */ +KOS_API oshandle_t +kos_event_create(int a_manualReset) +{ + struct completion *comp = KOS_MALLOC(sizeof(struct completion)); + + KOS_ASSERT(comp); + if(!comp) + { + return (oshandle_t)NULL; + } + + init_completion(comp); + + return (oshandle_t)comp; +} + +/* ------------------------------------------------------------------- *//* + * \brief Frees event semaphore + * \param oshandle_t a_event, event semaphore + * \return int +*//* ------------------------------------------------------------------- */ +KOS_API int +kos_event_destroy(oshandle_t a_event) +{ + struct completion *comp = (struct completion *)a_event; + + KOS_ASSERT(comp); +// KOS_ASSERT(completion_done(comp)); + + KOS_FREE(comp); + return (OS_SUCCESS); +} + +/* ------------------------------------------------------------------- *//* + * \brief Signals event semaphore + * \param oshandle_t a_event, event semaphore + * \return int +*//* ------------------------------------------------------------------- */ +KOS_API int +kos_event_signal(oshandle_t a_event) +{ + struct completion *comp = (struct completion *)a_event; + + KOS_ASSERT(comp); + complete_all(comp); // perhaps complete_all? + return (OS_SUCCESS); +} + +/* ------------------------------------------------------------------- *//* + * \brief Resets event semaphore state to nonsignaled + * \param oshandle_t a_event, event semaphore + * \return int +*//* ------------------------------------------------------------------- */ +KOS_API int +kos_event_reset(oshandle_t a_event) +{ + struct completion *comp = (struct completion *)a_event; + + KOS_ASSERT(comp); + INIT_COMPLETION(*comp); + return (OS_SUCCESS); +} + +/* ------------------------------------------------------------------- *//* + * \brief Waits event semaphore to be signaled + * \param oshandle_t a_event, event semaphore + * \return int +*//* ------------------------------------------------------------------- */ +KOS_API int +kos_event_wait(oshandle_t a_event, int a_milliSeconds) +{ + struct completion *comp = (struct completion *)a_event; + + KOS_ASSERT(comp); + if(a_milliSeconds == OS_INFINITE) + { + wait_for_completion_killable(comp); + } + else + { + // should interpret milliseconds really to jiffies? + if(!wait_for_completion_timeout(comp, msecs_to_jiffies(a_milliSeconds))) + { + return (OS_FAILURE); + } + } + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +KOS_API void +kos_sleep(unsigned int milliseconds) +{ + msleep(milliseconds); +} + +////////////////////////////////////////////////////////////////////////////// +// query API +////////////////////////////////////////////////////////////////////////////// + +static int +kos_get_endianness(void) +{ + int value; + char* ptr; + + value = 0x01FFFF00; + + ptr = (char*)&value; + + KOS_ASSERT((*ptr == 0x00) || (*ptr == 0x01)); + + return (int)*ptr; +} + +//---------------------------------------------------------------------------- + +KOS_API int +kos_get_sysinfo(os_sysinfo_t* sysinfo) +{ + KOS_ASSERT(sysinfo); + if (!sysinfo) return (OS_FAILURE); + + sysinfo->cpu_mhz = 0; + sysinfo->cpu_type = 0; + sysinfo->cpu_version = 0; + sysinfo->os_type = 0; + sysinfo->os_version = 0; + sysinfo->sysmem_size = 0; + sysinfo->page_size = 0x1000; + sysinfo->max_path = PATH_MAX; +// sysinfo->tls_slots = TLS_MINIMUM_AVAILABLE - 1; + sysinfo->endianness = kos_get_endianness(); + + return (OS_SUCCESS); +} + +//---------------------------------------------------------------------------- + +#ifdef KOS_STATS_ENABLE +KOS_API int +kos_get_stats(os_stats_t* stats) +{ + kos_memcpy(stats, &kos_stats, sizeof(os_stats_t)); + return (OS_SUCCESS); +} +#else +KOS_API int +kos_get_stats(os_stats_t* stats) +{ + return (OS_FAILURE); +} +#endif // KOS_STATS + +/*-------------------------------------------------------------------*//*! + * \brief Sync block API + * Same mutex needed from different blocks of driver + *//*-------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block start + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ + +static struct mutex* syncblock_mutex = 0; + +KOS_API int kos_syncblock_start(void) +{ + int return_value; + + if(!syncblock_mutex) + { + syncblock_mutex = kos_mutex_create("syncblock"); + } + + if(syncblock_mutex) + { + return_value = kos_mutex_lock(syncblock_mutex); + } + else + { + return_value = -1; + } + + return return_value; +} +/*-------------------------------------------------------------------*//*! + * \external + * \brief Sync block end + * + * \param void + * \return Returns NULL if no error, otherwise an error code. + *//*-------------------------------------------------------------------*/ +KOS_API int kos_syncblock_end(void) +{ + int return_value; + + if(syncblock_mutex) + { + return_value = kos_mutex_unlock(syncblock_mutex); + } + else + { + return_value = -1; + } + + return return_value; +} + +KOS_API oshandle_t kos_thread_create(oshandle_t a_function, unsigned int* a_threadId) +{ + struct task_struct *task = kthread_run(a_function, 0, "kos_thread_%p", a_threadId); + *a_threadId = (unsigned int)task; + return (oshandle_t)task; +} + +KOS_API void kos_thread_destroy( oshandle_t a_task ) +{ + kthread_stop((struct task_struct *)a_task); +} diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c new file mode 100644 index 000000000000..8d452830cc08 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hal.c @@ -0,0 +1,579 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#include "gsl_hal.h" +#include "gsl_halconfig.h" +#include "gsl_linux_map.h" + +#include +#include +#include +#include + +#include +#include +#include +#include + +#define GSL_HAL_MEM1 0 +#define GSL_HAL_MEM2 1 +#define GSL_HAL_MEM3 2 + +/* #define GSL_HAL_DEBUG */ + +extern phys_addr_t gpu_2d_regbase; +extern int gpu_2d_regsize; +extern phys_addr_t gpu_3d_regbase; +extern int gpu_3d_regsize; +extern int gmem_size; +extern phys_addr_t gpu_reserved_mem; +extern int gpu_reserved_mem_size; +extern int gpu_2d_irq, gpu_3d_irq; + + +KGSLHAL_API int +kgsl_hal_allocphysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) +{ + /* allocate physically contiguous memory */ + + int i; + void *va; + + va = gsl_linux_map_alloc(virtaddr, numpages*PAGE_SIZE); + + if (!va) + return GSL_FAILURE_OUTOFMEM; + + for (i = 0; i < numpages; i++) { + scattergatterlist[i] = page_to_phys(vmalloc_to_page(va)); + va += PAGE_SIZE; + } + + return GSL_SUCCESS; +} + +/* --------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_freephysical(unsigned int virtaddr, unsigned int numpages, unsigned int scattergatterlist[]) +{ + /* free physical memory */ + + gsl_linux_map_free(virtaddr); + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_init(void) +{ + gsl_hal_t *hal; + unsigned long totalsize, mem1size; + unsigned int va, pa; + + if (gsl_driver.hal) { + return GSL_FAILURE_ALREADYINITIALIZED; + } + + gsl_driver.hal = (void *)kos_malloc(sizeof(gsl_hal_t)); + + if (!gsl_driver.hal) { + return GSL_FAILURE_OUTOFMEM; + } + + kos_memset(gsl_driver.hal, 0, sizeof(gsl_hal_t)); + + + /* overlay structure on hal memory */ + hal = (gsl_hal_t *) gsl_driver.hal; + + if (gpu_3d_regbase && gpu_3d_regsize && gpu_3d_irq) { + hal->has_z430 = 1; + } else { + hal->has_z430 = 0; + } + + if (gpu_2d_regbase && gpu_2d_regsize && gpu_2d_irq) { + hal->has_z160 = 1; + } else { + hal->has_z160 = 0; + } + + /* there is still some problem to enable mmu currently */ + gsl_driver.enable_mmu = 0; + + /* setup register space */ + if (hal->has_z430) { + hal->z430_regspace.mmio_phys_base = gpu_3d_regbase; + hal->z430_regspace.sizebytes = gpu_3d_regsize; + hal->z430_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z430_regspace.mmio_phys_base, hal->z430_regspace.sizebytes); + + if (hal->z430_regspace.mmio_virt_base == NULL) { + return GSL_FAILURE_SYSTEMERROR; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->z430_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_phys_base); + printk(KERN_INFO "%s: hal->z430_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z430_regspace.mmio_virt_base); + printk(KERN_INFO "%s: hal->z430_regspace.sizebytes = 0x%08x\n", __func__, hal->z430_regspace.sizebytes); +#endif + } + + if (hal->has_z160) { + hal->z160_regspace.mmio_phys_base = gpu_2d_regbase; + hal->z160_regspace.sizebytes = gpu_2d_regsize; + hal->z160_regspace.mmio_virt_base = (unsigned char *)ioremap(hal->z160_regspace.mmio_phys_base, hal->z160_regspace.sizebytes); + + if (hal->z160_regspace.mmio_virt_base == NULL) { + return GSL_FAILURE_SYSTEMERROR; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->z160_regspace.mmio_phys_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_phys_base); + printk(KERN_INFO "%s: hal->z160_regspace.mmio_virt_base = 0x%p\n", __func__, (void *)hal->z160_regspace.mmio_virt_base); + printk(KERN_INFO "%s: hal->z160_regspace.sizebytes = 0x%08x\n", __func__, hal->z160_regspace.sizebytes); +#endif + } + + if (gsl_driver.enable_mmu) { + totalsize = GSL_HAL_SHMEM_SIZE_EMEM2_MMU + GSL_HAL_SHMEM_SIZE_PHYS_MMU; + mem1size = GSL_HAL_SHMEM_SIZE_EMEM1_MMU; + if (gpu_reserved_mem && gpu_reserved_mem_size >= totalsize) { + pa = gpu_reserved_mem; + va = (unsigned int)ioremap(gpu_reserved_mem, totalsize); + } else { + va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); + } + } else { + if (gpu_reserved_mem && gpu_reserved_mem_size >= SZ_8M) { + totalsize = gpu_reserved_mem_size; + pa = gpu_reserved_mem; + va = (unsigned int)ioremap(gpu_reserved_mem, gpu_reserved_mem_size); + } else { + gpu_reserved_mem = 0; + totalsize = GSL_HAL_SHMEM_SIZE_EMEM1_NOMMU + GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU + GSL_HAL_SHMEM_SIZE_PHYS_NOMMU; + va = (unsigned int)dma_alloc_coherent(0, totalsize, (dma_addr_t *)&pa, GFP_DMA | GFP_KERNEL); + } + mem1size = totalsize - (GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU + GSL_HAL_SHMEM_SIZE_PHYS_NOMMU); + } + + if (va) { + kos_memset((void *)va, 0, totalsize); + + hal->memchunk.mmio_virt_base = (void *)va; + hal->memchunk.mmio_phys_base = pa; + hal->memchunk.sizebytes = totalsize; + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memchunk.mmio_phys_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_phys_base); + printk(KERN_INFO "%s: hal->memchunk.mmio_virt_base = 0x%p\n", __func__, (void *)hal->memchunk.mmio_virt_base); + printk(KERN_INFO "%s: hal->memchunk.sizebytes = 0x%08x\n", __func__, hal->memchunk.sizebytes); +#endif + + hal->memspace[GSL_HAL_MEM2].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM2].gpu_base = pa; + if (gsl_driver.enable_mmu) { + hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2_MMU; + va += GSL_HAL_SHMEM_SIZE_EMEM2_MMU; + pa += GSL_HAL_SHMEM_SIZE_EMEM2_MMU; + } else { + hal->memspace[GSL_HAL_MEM2].sizebytes = GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU; + va += GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU; + pa += GSL_HAL_SHMEM_SIZE_EMEM2_NOMMU; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM2].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM2].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM2].sizebytes); +#endif + + hal->memspace[GSL_HAL_MEM3].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM3].gpu_base = pa; + if (gsl_driver.enable_mmu) { + hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS_MMU; + va += GSL_HAL_SHMEM_SIZE_PHYS_MMU; + pa += GSL_HAL_SHMEM_SIZE_PHYS_MMU; + } else { + hal->memspace[GSL_HAL_MEM3].sizebytes = GSL_HAL_SHMEM_SIZE_PHYS_NOMMU; + va += GSL_HAL_SHMEM_SIZE_PHYS_NOMMU; + pa += GSL_HAL_SHMEM_SIZE_PHYS_NOMMU; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM3].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM3].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM3].sizebytes); +#endif + + if (gsl_driver.enable_mmu) { + gsl_linux_map_init(); + hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *)GSL_LINUX_MAP_RANGE_START; + hal->memspace[GSL_HAL_MEM1].gpu_base = GSL_LINUX_MAP_RANGE_START; + hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; + } else { + hal->memspace[GSL_HAL_MEM1].mmio_virt_base = (void *) va; + hal->memspace[GSL_HAL_MEM1].gpu_base = pa; + hal->memspace[GSL_HAL_MEM1].sizebytes = mem1size; + } + +#ifdef GSL_HAL_DEBUG + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].gpu_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].gpu_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].mmio_virt_base = 0x%p\n", __func__, (void *)hal->memspace[GSL_HAL_MEM1].mmio_virt_base); + printk(KERN_INFO "%s: hal->memspace[GSL_HAL_MEM1].sizebytes = 0x%08x\n", __func__, hal->memspace[GSL_HAL_MEM1].sizebytes); +#endif + } else { + kgsl_hal_close(); + return GSL_FAILURE_SYSTEMERROR; + } + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_close(void) +{ + gsl_hal_t *hal; + + if (gsl_driver.hal) { + /* overlay structure on hal memory */ + hal = (gsl_hal_t *) gsl_driver.hal; + + /* unmap registers */ + if (hal->has_z430 && hal->z430_regspace.mmio_virt_base) { + iounmap(hal->z430_regspace.mmio_virt_base); + } + + if (hal->has_z160 && hal->z160_regspace.mmio_virt_base) { + iounmap(hal->z160_regspace.mmio_virt_base); + } + + /* free physical block */ + if (hal->memchunk.mmio_virt_base && gpu_reserved_mem) { + iounmap(hal->memchunk.mmio_virt_base); + } else { + dma_free_coherent(0, hal->memchunk.sizebytes, hal->memchunk.mmio_virt_base, hal->memchunk.mmio_phys_base); + } + + if (gsl_driver.enable_mmu) { + gsl_linux_map_destroy(); + } + + /* release hal struct */ + kos_memset(hal, 0, sizeof(gsl_hal_t)); + kos_free(gsl_driver.hal); + gsl_driver.hal = NULL; + } + + return GSL_SUCCESS; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_getshmemconfig(gsl_shmemconfig_t *config) +{ + int status = GSL_FAILURE_DEVICEERROR; + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + + kos_memset(config, 0, sizeof(gsl_shmemconfig_t)); + + if (hal) { + config->numapertures = GSL_SHMEM_MAX_APERTURES; + + if (gsl_driver.enable_mmu) { + config->apertures[0].id = GSL_APERTURE_MMU; + } else { + config->apertures[0].id = GSL_APERTURE_EMEM; + } + config->apertures[0].channel = GSL_CHANNEL_1; + config->apertures[0].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM1].mmio_virt_base; + config->apertures[0].gpubase = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->apertures[0].sizebytes = hal->memspace[GSL_HAL_MEM1].sizebytes; + + config->apertures[1].id = GSL_APERTURE_EMEM; + config->apertures[1].channel = GSL_CHANNEL_2; + config->apertures[1].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM2].mmio_virt_base; + config->apertures[1].gpubase = hal->memspace[GSL_HAL_MEM2].gpu_base; + config->apertures[1].sizebytes = hal->memspace[GSL_HAL_MEM2].sizebytes; + + config->apertures[2].id = GSL_APERTURE_PHYS; + config->apertures[2].channel = GSL_CHANNEL_1; + config->apertures[2].hostbase = (unsigned int)hal->memspace[GSL_HAL_MEM3].mmio_virt_base; + config->apertures[2].gpubase = hal->memspace[GSL_HAL_MEM3].gpu_base; + config->apertures[2].sizebytes = hal->memspace[GSL_HAL_MEM3].sizebytes; + + status = GSL_SUCCESS; + } + + return status; +} + +/* ---------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_getdevconfig(gsl_deviceid_t device_id, gsl_devconfig_t *config) +{ + int status = GSL_FAILURE_DEVICEERROR; + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + + kos_memset(config, 0, sizeof(gsl_devconfig_t)); + + if (hal) { + switch (device_id) { + case GSL_DEVICE_YAMATO: + { + if (hal->has_z430) { + mh_mmu_config_u mmu_config = {0}; + + config->gmemspace.gpu_base = 0; + config->gmemspace.mmio_virt_base = 0; + config->gmemspace.mmio_phys_base = 0; + if (gmem_size) { + config->gmemspace.sizebytes = gmem_size; + } else { + config->gmemspace.sizebytes = 0; + } + + config->regspace.gpu_base = 0; + config->regspace.mmio_virt_base = (unsigned char *)hal->z430_regspace.mmio_virt_base; + config->regspace.mmio_phys_base = (unsigned int) hal->z430_regspace.mmio_phys_base; + config->regspace.sizebytes = GSL_HAL_SIZE_REG_YDX; + + mmu_config.f.mmu_enable = 1; + + if (gsl_driver.enable_mmu) { + mmu_config.f.split_mode_enable = 0; + mmu_config.f.rb_w_clnt_behavior = 1; + mmu_config.f.cp_w_clnt_behavior = 1; + mmu_config.f.cp_r0_clnt_behavior = 1; + mmu_config.f.cp_r1_clnt_behavior = 1; + mmu_config.f.cp_r2_clnt_behavior = 1; + mmu_config.f.cp_r3_clnt_behavior = 1; + mmu_config.f.cp_r4_clnt_behavior = 1; + mmu_config.f.vgt_r0_clnt_behavior = 1; + mmu_config.f.vgt_r1_clnt_behavior = 1; + mmu_config.f.tc_r_clnt_behavior = 1; + mmu_config.f.pa_w_clnt_behavior = 1; + } + + config->mmu_config = mmu_config.val; + + if (gsl_driver.enable_mmu) { + config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; + } else { + config->va_base = 0x00000000; + config->va_range = 0x00000000; + } + + /* turn off memory protection unit by setting acceptable physical address range to include all pages */ + config->mpu_base = 0x00000000; /* hal->memchunk.mmio_virt_base; */ + config->mpu_range = 0xFFFFF000; /* hal->memchunk.sizebytes; */ + status = GSL_SUCCESS; + } + break; + } + + case GSL_DEVICE_G12: + { + mh_mmu_config_u mmu_config = {0}; + + config->regspace.gpu_base = 0; + config->regspace.mmio_virt_base = (unsigned char *)hal->z160_regspace.mmio_virt_base; + config->regspace.mmio_phys_base = (unsigned int) hal->z160_regspace.mmio_phys_base; + config->regspace.sizebytes = GSL_HAL_SIZE_REG_G12; + + mmu_config.f.mmu_enable = 1; + + if (gsl_driver.enable_mmu) { + config->mmu_config = 0x00555551; + config->va_base = hal->memspace[GSL_HAL_MEM1].gpu_base; + config->va_range = hal->memspace[GSL_HAL_MEM1].sizebytes; + } else { + config->mmu_config = mmu_config.val; + config->va_base = 0x00000000; + config->va_range = 0x00000000; + } + + config->mpu_base = 0x00000000; /* (unsigned int) hal->memchunk.mmio_virt_base; */ + config->mpu_range = 0xFFFFF000; /* hal->memchunk.sizebytes; */ + + status = GSL_SUCCESS; + break; + } + + default: + break; + } + } + + return status; +} + +/*---------------------------------------------------------------------------- + * kgsl_hal_getchipid + * + * The proper platform method, build from RBBM_PERIPHIDx and RBBM_PATCH_RELEASE + *---------------------------------------------------------------------------- + */ +KGSLHAL_API gsl_chipid_t +kgsl_hal_getchipid(gsl_deviceid_t device_id) +{ + gsl_hal_t *hal = (gsl_hal_t *) gsl_driver.hal; + gsl_device_t *device = &gsl_driver.device[device_id-1]; + gsl_chipid_t chipid = 0; + unsigned int coreid, majorid, minorid, patchid, revid; + + if (hal->has_z430 && (device_id == GSL_DEVICE_YAMATO)) { + device->ftbl.device_regread(device, mmRBBM_PERIPHID1, &coreid); + coreid &= 0xF; + + device->ftbl.device_regread(device, mmRBBM_PERIPHID2, &majorid); + majorid = (majorid >> 4) & 0xF; + + device->ftbl.device_regread(device, mmRBBM_PATCH_RELEASE, &revid); + + minorid = ((revid >> 0) & 0xFF); /* this is a 16bit field, but extremely unlikely it would ever get this high */ + + patchid = ((revid >> 16) & 0xFF); + + chipid = ((coreid << 24) | (majorid << 16) | (minorid << 8) | (patchid << 0)); + } + + return chipid; +} + +/* --------------------------------------------------------------------------- */ + +KGSLHAL_API int +kgsl_hal_setpowerstate(gsl_deviceid_t device_id, int state, unsigned int value) +{ + gsl_device_t *device = &gsl_driver.device[device_id-1]; + struct clk *gpu_clk = NULL; + struct clk *garb_clk = NULL; + struct clk *emi_garb_clk = NULL; + + /* unreferenced formal parameters */ + (void) value; + + switch (device_id) { + case GSL_DEVICE_G12: + gpu_clk = clk_get(0, "gpu2d_clk"); + break; + case GSL_DEVICE_YAMATO: + gpu_clk = clk_get(0, "gpu3d_clk"); + garb_clk = clk_get(0, "garb_clk"); + emi_garb_clk = clk_get(0, "emi_garb_clk"); + break; + default: + return GSL_FAILURE_DEVICEERROR; + } + + if (!gpu_clk) { + return GSL_FAILURE_DEVICEERROR; + } + + switch (state) { + case GSL_PWRFLAGS_CLK_ON: + break; + case GSL_PWRFLAGS_POWER_ON: + clk_enable(gpu_clk); + if (garb_clk) { + clk_enable(garb_clk); + } + if (emi_garb_clk) { + clk_enable(emi_garb_clk); + } + kgsl_device_autogate_init(&gsl_driver.device[device_id-1]); + break; + case GSL_PWRFLAGS_CLK_OFF: + break; + case GSL_PWRFLAGS_POWER_OFF: + if (device->ftbl.device_idle(device, GSL_TIMEOUT_DEFAULT) != GSL_SUCCESS) { + return GSL_FAILURE_DEVICEERROR; + } + kgsl_device_autogate_exit(&gsl_driver.device[device_id-1]); + clk_disable(gpu_clk); + if (garb_clk) { + clk_disable(garb_clk); + } + if (emi_garb_clk) { + clk_disable(emi_garb_clk); + } + break; + default: + break; + } + + return GSL_SUCCESS; +} + +KGSLHAL_API int kgsl_clock(gsl_deviceid_t dev, int enable) +{ + struct clk *gpu_clk = NULL; + struct clk *garb_clk = NULL; + struct clk *emi_garb_clk = NULL; + + switch (dev) { + case GSL_DEVICE_G12: + gpu_clk = clk_get(0, "gpu2d_clk"); + break; + case GSL_DEVICE_YAMATO: + gpu_clk = clk_get(0, "gpu3d_clk"); + garb_clk = clk_get(0, "garb_clk"); + emi_garb_clk = clk_get(0, "emi_garb_clk"); + break; + default: + printk(KERN_ERR "GPU device %d is invalid!\n", dev); + return GSL_FAILURE_DEVICEERROR; + } + + if (IS_ERR(gpu_clk)) { + printk(KERN_ERR "%s: GPU clock get failed!\n", __func__); + return GSL_FAILURE_DEVICEERROR; + } + + if (enable) { + clk_enable(gpu_clk); + if (garb_clk) { + clk_enable(garb_clk); + } + if (emi_garb_clk) { + clk_enable(emi_garb_clk); + } + } else { + clk_disable(gpu_clk); + if (garb_clk) { + clk_disable(garb_clk); + } + if (emi_garb_clk) { + clk_disable(emi_garb_clk); + } + } + + return GSL_SUCCESS; +} diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h new file mode 100644 index 000000000000..305b2ee9066d --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_hwaccess.h @@ -0,0 +1,142 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_HWACCESS_LINUX_H +#define __GSL_HWACCESS_LINUX_H + +#ifdef _LINUX +#include "gsl_linux_map.h" +#endif + +#include +#include +#include + +OSINLINE void +kgsl_hwaccess_memread(void *dst, unsigned int gpubase, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace) +{ + if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { + gsl_linux_map_read(dst, gpubase+gpuoffset, sizebytes, touserspace); + } else { + mb(); + dsb(); + if (touserspace) + { + if (copy_to_user(dst, (void *)(gpubase + gpuoffset), sizebytes)) + { + return; + } + } + else + { + kos_memcpy(dst, (void *) (gpubase + gpuoffset), sizebytes); + } + mb(); + dsb(); + } +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_hwaccess_memwrite(unsigned int gpubase, unsigned int gpuoffset, void *src, unsigned int sizebytes, unsigned int fromuserspace) +{ + if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { + gsl_linux_map_write(src, gpubase+gpuoffset, sizebytes, fromuserspace); + } else { + mb(); + dsb(); + if (fromuserspace) + { + if (copy_from_user((void *)(gpubase + gpuoffset), src, sizebytes)) + { + return; + } + } + else + { + kos_memcpy((void *)(gpubase + gpuoffset), src, sizebytes); + } + mb(); + dsb(); + } +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_hwaccess_memset(unsigned int gpubase, unsigned int gpuoffset, unsigned int value, unsigned int sizebytes) +{ + if (gsl_driver.enable_mmu && (gpubase >= GSL_LINUX_MAP_RANGE_START) && (gpubase < GSL_LINUX_MAP_RANGE_END)) { + gsl_linux_map_set(gpuoffset+gpubase, value, sizebytes); + } else { + mb(); + dsb(); + kos_memset((void *)(gpubase + gpuoffset), value, sizebytes); + mb(); + dsb(); + } +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_hwaccess_regread(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int *data) +{ + unsigned int *reg; + + // unreferenced formal parameter + (void) device_id; + + reg = (unsigned int *)(gpubase + (offsetwords << 2)); + + mb(); + dsb(); + *data = __raw_readl(reg); + mb(); + dsb(); +} + +//---------------------------------------------------------------------------- + +OSINLINE void +kgsl_hwaccess_regwrite(gsl_deviceid_t device_id, unsigned int gpubase, unsigned int offsetwords, unsigned int data) +{ + unsigned int *reg; + + // unreferenced formal parameter + (void) device_id; + + reg = (unsigned int *)(gpubase + (offsetwords << 2)); + mb(); + dsb(); + __raw_writel(data, reg); + mb(); + dsb(); +} +#endif // __GSL_HWACCESS_WINCE_MX51_H diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c new file mode 100644 index 000000000000..6b8af4bd2e1b --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod.c @@ -0,0 +1,976 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl_types.h" +#include "gsl.h" +#include "gsl_buildconfig.h" +#include "gsl_halconfig.h" +#include "gsl_ioctl.h" +#include "gsl_kmod_cleanup.h" +#include "gsl_linux_map.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +int gpu_2d_irq, gpu_3d_irq; + +phys_addr_t gpu_2d_regbase; +int gpu_2d_regsize; +phys_addr_t gpu_3d_regbase; +int gpu_3d_regsize; +int gmem_size; +phys_addr_t gpu_reserved_mem; +int gpu_reserved_mem_size; +int z160_version; + +static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr); +static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr); +static int gsl_kmod_ioctl(struct inode *inode, struct file *fd, unsigned int cmd, unsigned long arg); +static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma); +static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf); +static int gsl_kmod_open(struct inode *inode, struct file *fd); +static int gsl_kmod_release(struct inode *inode, struct file *fd); +static irqreturn_t z160_irq_handler(int irq, void *dev_id); +static irqreturn_t z430_irq_handler(int irq, void *dev_id); + +static int gsl_kmod_major; +static struct class *gsl_kmod_class; +DEFINE_MUTEX(gsl_mutex); + +static const struct file_operations gsl_kmod_fops = +{ + .owner = THIS_MODULE, + .read = gsl_kmod_read, + .write = gsl_kmod_write, + .ioctl = gsl_kmod_ioctl, + .mmap = gsl_kmod_mmap, + .open = gsl_kmod_open, + .release = gsl_kmod_release +}; + +static struct vm_operations_struct gsl_kmod_vmops = +{ + .fault = gsl_kmod_fault, +}; + +static ssize_t gsl_kmod_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr) +{ + return 0; +} + +static ssize_t gsl_kmod_write(struct file *fd, const char __user *buf, size_t len, loff_t *ptr) +{ + return 0; +} + +static int gsl_kmod_ioctl(struct inode *inode, struct file *fd, unsigned int cmd, unsigned long arg) +{ + int kgslStatus = GSL_FAILURE; + + switch (cmd) { + case IOCTL_KGSL_DEVICE_START: + { + kgsl_device_start_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_start_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_start(param.device_id, param.flags); + break; + } + case IOCTL_KGSL_DEVICE_STOP: + { + kgsl_device_stop_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_stop_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_stop(param.device_id); + break; + } + case IOCTL_KGSL_DEVICE_IDLE: + { + kgsl_device_idle_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_idle_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_idle(param.device_id, param.timeout); + break; + } + case IOCTL_KGSL_DEVICE_ISIDLE: + { + kgsl_device_isidle_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_isidle_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_isidle(param.device_id); + break; + } + case IOCTL_KGSL_DEVICE_GETPROPERTY: + { + kgsl_device_getproperty_t param; + void *tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_getproperty_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + tmp = kmalloc(param.sizebytes, GFP_KERNEL); + if (!tmp) + { + printk(KERN_ERR "%s:kmalloc error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_getproperty(param.device_id, param.type, tmp, param.sizebytes); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.value, tmp, param.sizebytes)) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + kfree(tmp); + break; + } + } + else + { + printk(KERN_ERR "%s: kgsl_device_getproperty error\n", __func__); + } + kfree(tmp); + break; + } + case IOCTL_KGSL_DEVICE_SETPROPERTY: + { + kgsl_device_setproperty_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_setproperty_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_setproperty(param.device_id, param.type, param.value, param.sizebytes); + if (kgslStatus != GSL_SUCCESS) + { + printk(KERN_ERR "%s: kgsl_device_setproperty error\n", __func__); + } + break; + } + case IOCTL_KGSL_DEVICE_REGREAD: + { + kgsl_device_regread_t param; + unsigned int tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_regread_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_regread(param.device_id, param.offsetwords, &tmp); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.value, &tmp, sizeof(unsigned int))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + } + break; + } + case IOCTL_KGSL_DEVICE_REGWRITE: + { + kgsl_device_regwrite_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_regwrite_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_regwrite(param.device_id, param.offsetwords, param.value); + break; + } + case IOCTL_KGSL_DEVICE_WAITIRQ: + { + kgsl_device_waitirq_t param; + unsigned int count; + + printk(KERN_ERR "IOCTL_KGSL_DEVICE_WAITIRQ obsoleted!\n"); +// kgslStatus = -ENOTTY; break; + + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_waitirq_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_waitirq(param.device_id, param.intr_id, &count, param.timeout); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.count, &count, sizeof(unsigned int))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + } + break; + } + case IOCTL_KGSL_CMDSTREAM_ISSUEIBCMDS: + { + kgsl_cmdstream_issueibcmds_t param; + gsl_timestamp_t tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdstream_issueibcmds_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_cmdstream_issueibcmds(param.device_id, param.drawctxt_index, param.ibaddr, param.sizedwords, &tmp, param.flags); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + } + break; + } + case IOCTL_KGSL_CMDSTREAM_READTIMESTAMP: + { + kgsl_cmdstream_readtimestamp_t param; + gsl_timestamp_t tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdstream_readtimestamp_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + tmp = kgsl_cmdstream_readtimestamp(param.device_id, param.type); + if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = GSL_SUCCESS; + break; + } + case IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP: + { + int err; + kgsl_cmdstream_freememontimestamp_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdstream_freememontimestamp_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + err = del_memblock_from_allocated_list(fd, param.memdesc); + if(err) + { + /* tried to remove a block of memory that is not allocated! + * NOTE that -EINVAL is Linux kernel's error codes! + * the drivers error codes COULD mix up with kernel's. */ + kgslStatus = -EINVAL; + } + else + { + kgslStatus = kgsl_cmdstream_freememontimestamp(param.device_id, + param.memdesc, + param.timestamp, + param.type); + } + break; + } + case IOCTL_KGSL_CMDSTREAM_WAITTIMESTAMP: + { + kgsl_cmdstream_waittimestamp_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdstream_waittimestamp_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_cmdstream_waittimestamp(param.device_id, param.timestamp, param.timeout); + break; + } + case IOCTL_KGSL_CMDWINDOW_WRITE: + { + kgsl_cmdwindow_write_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_cmdwindow_write_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_cmdwindow_write(param.device_id, param.target, param.addr, param.data); + break; + } + case IOCTL_KGSL_CONTEXT_CREATE: + { + kgsl_context_create_t param; + unsigned int tmp; + int tmpStatus; + + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_context_create_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_context_create(param.device_id, param.type, &tmp, param.flags); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.drawctxt_id, &tmp, sizeof(unsigned int))) + { + tmpStatus = kgsl_context_destroy(param.device_id, tmp); + /* is asserting ok? Basicly we should return the error from copy_to_user + * but will the user space interpret it correctly? Will the user space + * always check against GSL_SUCCESS or GSL_FAILURE as they are not the only + * return values. + */ + KOS_ASSERT(tmpStatus == GSL_SUCCESS); + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + else + { + add_device_context_to_array(fd, param.device_id, tmp); + } + } + break; + } + case IOCTL_KGSL_CONTEXT_DESTROY: + { + kgsl_context_destroy_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_context_destroy_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_context_destroy(param.device_id, param.drawctxt_id); + del_device_context_from_array(fd, param.device_id, param.drawctxt_id); + break; + } + case IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW: + { + kgsl_drawctxt_bind_gmem_shadow_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_drawctxt_bind_gmem_shadow_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_drawctxt_bind_gmem_shadow(param.device_id, param.drawctxt_id, param.gmem_rect, param.shadow_x, param.shadow_y, param.shadow_buffer, param.buffer_id); + break; + } + case IOCTL_KGSL_SHAREDMEM_ALLOC: + { + kgsl_sharedmem_alloc_t param; + gsl_memdesc_t tmp; + int tmpStatus; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_alloc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_alloc(param.device_id, param.flags, param.sizebytes, &tmp); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t))) + { + tmpStatus = kgsl_sharedmem_free(&tmp); + KOS_ASSERT(tmpStatus == GSL_SUCCESS); + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + else + { + add_memblock_to_allocated_list(fd, &tmp); + } + } + break; + } + case IOCTL_KGSL_SHAREDMEM_FREE: + { + kgsl_sharedmem_free_t param; + gsl_memdesc_t tmp; + int err; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_free_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&tmp, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + err = del_memblock_from_allocated_list(fd, &tmp); + if(err) + { + printk(KERN_ERR "%s: tried to free memdesc that was not allocated!\n", __func__); + kgslStatus = err; + break; + } + kgslStatus = kgsl_sharedmem_free(&tmp); + if (kgslStatus == GSL_SUCCESS) + { + if (copy_to_user(param.memdesc, &tmp, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + } + break; + } + case IOCTL_KGSL_SHAREDMEM_READ: + { + kgsl_sharedmem_read_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_read_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_read(&memdesc, param.dst, param.offsetbytes, param.sizebytes, true); + if (kgslStatus != GSL_SUCCESS) + { + printk(KERN_ERR "%s: kgsl_sharedmem_read failed\n", __func__); + } + break; + } + case IOCTL_KGSL_SHAREDMEM_WRITE: + { + kgsl_sharedmem_write_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_write_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_write(&memdesc, param.offsetbytes, param.src, param.sizebytes, true); + if (kgslStatus != GSL_SUCCESS) + { + printk(KERN_ERR "%s: kgsl_sharedmem_write failed\n", __func__); + } + + break; + } + case IOCTL_KGSL_SHAREDMEM_SET: + { + kgsl_sharedmem_set_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_set_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_set(&memdesc, param.offsetbytes, param.value, param.sizebytes); + break; + } + case IOCTL_KGSL_SHAREDMEM_LARGESTFREEBLOCK: + { + kgsl_sharedmem_largestfreeblock_t param; + unsigned int largestfreeblock; + + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_largestfreeblock_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + largestfreeblock = kgsl_sharedmem_largestfreeblock(param.device_id, param.flags); + if (copy_to_user(param.largestfreeblock, &largestfreeblock, sizeof(unsigned int))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = GSL_SUCCESS; + break; + } + case IOCTL_KGSL_SHAREDMEM_CACHEOPERATION: + { + kgsl_sharedmem_cacheoperation_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_cacheoperation_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_cacheoperation(&memdesc, param.offsetbytes, param.sizebytes, param.operation); + break; + } + case IOCTL_KGSL_SHAREDMEM_FROMHOSTPOINTER: + { + kgsl_sharedmem_fromhostpointer_t param; + gsl_memdesc_t memdesc; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_sharedmem_fromhostpointer_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + if (copy_from_user(&memdesc, (void __user *)param.memdesc, sizeof(gsl_memdesc_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_sharedmem_fromhostpointer(param.device_id, &memdesc, param.hostptr); + break; + } + case IOCTL_KGSL_ADD_TIMESTAMP: + { + kgsl_add_timestamp_t param; + gsl_timestamp_t tmp; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_add_timestamp_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + tmp = kgsl_add_timestamp(param.device_id, &tmp); + if (copy_to_user(param.timestamp, &tmp, sizeof(gsl_timestamp_t))) + { + printk(KERN_ERR "%s: copy_to_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = GSL_SUCCESS; + break; + } + + case IOCTL_KGSL_DEVICE_CLOCK: + { + kgsl_device_clock_t param; + if (copy_from_user(¶m, (void __user *)arg, sizeof(kgsl_device_clock_t))) + { + printk(KERN_ERR "%s: copy_from_user error\n", __func__); + kgslStatus = GSL_FAILURE; + break; + } + kgslStatus = kgsl_device_clock(param.device, param.enable); + break; + } + default: + kgslStatus = -ENOTTY; + break; + } + + return kgslStatus; +} + +static int gsl_kmod_mmap(struct file *fd, struct vm_area_struct *vma) +{ + int status = 0; + unsigned long start = vma->vm_start; + unsigned long pfn = vma->vm_pgoff; + unsigned long size = vma->vm_end - vma->vm_start; + unsigned long prot = pgprot_writecombine(vma->vm_page_prot); + unsigned long addr = vma->vm_pgoff << PAGE_SHIFT; + void *va = NULL; + + if (gsl_driver.enable_mmu && (addr < GSL_LINUX_MAP_RANGE_END) && (addr >= GSL_LINUX_MAP_RANGE_START)) { + va = gsl_linux_map_find(addr); + while (size > 0) { + if (remap_pfn_range(vma, start, vmalloc_to_pfn(va), PAGE_SIZE, prot)) { + return -EAGAIN; + } + start += PAGE_SIZE; + va += PAGE_SIZE; + size -= PAGE_SIZE; + } + } else { + if (remap_pfn_range(vma, start, pfn, size, prot)) { + status = -EAGAIN; + } + } + + vma->vm_ops = &gsl_kmod_vmops; + + return status; +} + +static int gsl_kmod_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + return VM_FAULT_SIGBUS; +} + +static int gsl_kmod_open(struct inode *inode, struct file *fd) +{ + gsl_flags_t flags = 0; + struct gsl_kmod_per_fd_data *datp; + int err = 0; + + if(mutex_lock_interruptible(&gsl_mutex)) + { + return -EINTR; + } + + if (kgsl_driver_entry(flags) != GSL_SUCCESS) + { + printk(KERN_INFO "%s: kgsl_driver_entry error\n", __func__); + err = -EIO; // TODO: not sure why did it fail? + } + else + { + /* allocate per file descriptor data structure */ + datp = (struct gsl_kmod_per_fd_data *)kzalloc( + sizeof(struct gsl_kmod_per_fd_data), + GFP_KERNEL); + if(datp) + { + init_created_contexts_array(datp->created_contexts_array[0]); + INIT_LIST_HEAD(&datp->allocated_blocks_head); + + fd->private_data = (void *)datp; + } + else + { + err = -ENOMEM; + } + } + + mutex_unlock(&gsl_mutex); + + return err; +} + +static int gsl_kmod_release(struct inode *inode, struct file *fd) +{ + struct gsl_kmod_per_fd_data *datp; + int err = 0; + + if(mutex_lock_interruptible(&gsl_mutex)) + { + return -EINTR; + } + + /* make sure contexts are destroyed */ + del_all_devices_contexts(fd); + + if (kgsl_driver_exit() != GSL_SUCCESS) + { + printk(KERN_INFO "%s: kgsl_driver_exit error\n", __func__); + err = -EIO; // TODO: find better error code + } + else + { + /* release per file descriptor data structure */ + datp = (struct gsl_kmod_per_fd_data *)fd->private_data; + del_all_memblocks_from_allocated_list(fd); + kfree(datp); + fd->private_data = 0; + } + + mutex_unlock(&gsl_mutex); + + return err; +} + +static struct class *gsl_kmod_class; + +static irqreturn_t z160_irq_handler(int irq, void *dev_id) +{ + kgsl_intr_isr(); + return IRQ_HANDLED; +} + +static irqreturn_t z430_irq_handler(int irq, void *dev_id) +{ + kgsl_intr_isr(); + return IRQ_HANDLED; +} + +static int gpu_probe(struct platform_device *pdev) +{ + int i; + struct resource *res; + struct device *dev; + + if (pdev->dev.platform_data) + z160_version = *((int *)(pdev->dev.platform_data)); + else + z160_version = 0; + + for(i = 0; i < 2; i++){ + res = platform_get_resource(pdev, IORESOURCE_IRQ, i); + if (!res) { + if (i == 0) { + printk(KERN_ERR "gpu: unable to get gpu irq\n"); + return -ENODEV; + } else { + break; + } + } + if(strcmp(res->name, "gpu_2d_irq") == 0){ + gpu_2d_irq = res->start; + }else if(strcmp(res->name, "gpu_3d_irq") == 0){ + gpu_3d_irq = res->start; + } + } + + for(i = 0; i < 4; i++){ + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) { + gpu_2d_regbase = 0; + gpu_2d_regsize = 0; + gpu_3d_regbase = 0; + gpu_2d_regsize = 0; + gmem_size = 0; + gpu_reserved_mem = 0; + gpu_reserved_mem_size = 0; + break; + }else{ + if(strcmp(res->name, "gpu_2d_registers") == 0){ + gpu_2d_regbase = res->start; + gpu_2d_regsize = res->end - res->start + 1; + }else if(strcmp(res->name, "gpu_3d_registers") == 0){ + gpu_3d_regbase = res->start; + gpu_3d_regsize = res->end - res->start + 1; + }else if(strcmp(res->name, "gpu_graphics_mem") == 0){ + gmem_size = res->end - res->start + 1; + }else if(strcmp(res->name, "gpu_reserved_mem") == 0){ + gpu_reserved_mem = res->start; + gpu_reserved_mem_size = res->end - res->start + 1; + } + } + } + + if (gpu_3d_irq > 0) + { + if (request_irq(gpu_3d_irq, z430_irq_handler, 0, "ydx", NULL) < 0) { + printk(KERN_ERR "%s: request_irq error\n", __func__); + gpu_3d_irq = 0; + goto request_irq_error; + } + } + + if (gpu_2d_irq > 0) + { + if (request_irq(gpu_2d_irq, z160_irq_handler, 0, "g12", NULL) < 0) { + printk(KERN_ERR "DO NOT use uio_pdrv_genirq kernel module for X acceleration!\n"); + gpu_2d_irq = 0; + } + } + + if (kgsl_driver_init() != GSL_SUCCESS) { + printk(KERN_ERR "%s: kgsl_driver_init error\n", __func__); + goto kgsl_driver_init_error; + } + + gsl_kmod_major = register_chrdev(0, "gsl_kmod", &gsl_kmod_fops); + gsl_kmod_vmops.fault = gsl_kmod_fault; + + if (gsl_kmod_major <= 0) + { + pr_err("%s: register_chrdev error\n", __func__); + goto register_chrdev_error; + } + + gsl_kmod_class = class_create(THIS_MODULE, "gsl_kmod"); + + if (IS_ERR(gsl_kmod_class)) + { + pr_err("%s: class_create error\n", __func__); + goto class_create_error; + } + + #if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)) + dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), "gsl_kmod"); + #else + dev = device_create(gsl_kmod_class, NULL, MKDEV(gsl_kmod_major, 0), NULL,"gsl_kmod"); + #endif + + if (!IS_ERR(dev)) + { + // gsl_kmod_data.device = dev; + return 0; + } + + pr_err("%s: device_create error\n", __func__); + +class_create_error: + class_destroy(gsl_kmod_class); + +register_chrdev_error: + unregister_chrdev(gsl_kmod_major, "gsl_kmod"); + +kgsl_driver_init_error: + kgsl_driver_close(); + if (gpu_2d_irq > 0) { + free_irq(gpu_2d_irq, NULL); + } + if (gpu_3d_irq > 0) { + free_irq(gpu_3d_irq, NULL); + } +request_irq_error: + return 0; // TODO: return proper error code +} + +static int gpu_remove(struct platform_device *pdev) +{ + device_destroy(gsl_kmod_class, MKDEV(gsl_kmod_major, 0)); + class_destroy(gsl_kmod_class); + unregister_chrdev(gsl_kmod_major, "gsl_kmod"); + + if (gpu_3d_irq) + { + free_irq(gpu_3d_irq, NULL); + } + + if (gpu_2d_irq) + { + free_irq(gpu_2d_irq, NULL); + } + + kgsl_driver_close(); + return 0; +} + +#ifdef CONFIG_PM +static int gpu_suspend(struct platform_device *pdev, pm_message_t state) +{ + int i; + gsl_powerprop_t power; + + power.flags = GSL_PWRFLAGS_POWER_OFF; + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + kgsl_device_setproperty( + (gsl_deviceid_t) (i+1), + GSL_PROP_DEVICE_POWER, + &power, + sizeof(gsl_powerprop_t)); + } + + return 0; +} + +static int gpu_resume(struct platform_device *pdev) +{ + int i; + gsl_powerprop_t power; + + power.flags = GSL_PWRFLAGS_POWER_ON; + for (i = 0; i < GSL_DEVICE_MAX; i++) + { + kgsl_device_setproperty( + (gsl_deviceid_t) (i+1), + GSL_PROP_DEVICE_POWER, + &power, + sizeof(gsl_powerprop_t)); + } + + return 0; +} +#else +#define gpu_suspend NULL +#define gpu_resume NULL +#endif /* !CONFIG_PM */ + +/*! Driver definition + */ +static struct platform_driver gpu_driver = { + .driver = { + .name = "mxc_gpu", + }, + .probe = gpu_probe, + .remove = gpu_remove, + .suspend = gpu_suspend, + .resume = gpu_resume, +}; + +static int __init gsl_kmod_init(void) +{ + return platform_driver_register(&gpu_driver); +} + +static void __exit gsl_kmod_exit(void) +{ + platform_driver_unregister(&gpu_driver); +} + +module_init(gsl_kmod_init); +module_exit(gsl_kmod_exit); +MODULE_AUTHOR("Advanced Micro Devices"); +MODULE_DESCRIPTION("AMD graphics core driver for i.MX"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c new file mode 100644 index 000000000000..3685a5756baf --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.c @@ -0,0 +1,269 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "gsl.h" +#include "gsl_kmod_cleanup.h" + +#include +#include + +/* + * Local helper functions to check and convert device/context id's (1 based) + * to index (0 based). + */ +static u32 device_id_to_device_index(gsl_deviceid_t device_id) +{ + KOS_ASSERT((GSL_DEVICE_ANY < device_id) && + (device_id <= GSL_DEVICE_MAX)); + return (u32)(device_id - 1); +} + +/* + * Local helper function to check and get pointer to per file descriptor data + */ +static struct gsl_kmod_per_fd_data *get_fd_private_data(struct file *fd) +{ + struct gsl_kmod_per_fd_data *datp; + + KOS_ASSERT(fd); + datp = (struct gsl_kmod_per_fd_data *)fd->private_data; + KOS_ASSERT(datp); + return datp; +} + +static s8 *find_first_entry_with(s8 *subarray, s8 context_id) +{ + s8 *entry = NULL; + int i; + +//printk(KERN_DEBUG "At %s, ctx_id = %d\n", __func__, context_id); + + KOS_ASSERT(context_id >= EMPTY_ENTRY); + KOS_ASSERT(context_id <= GSL_CONTEXT_MAX); // TODO: check the bound. + + for(i = 0; i < GSL_CONTEXT_MAX; i++) // TODO: check the bound. + { + if(subarray[i] == (s8)context_id) + { + entry = &subarray[i]; + break; + } + } + + return entry; +} + + +/* + * Add a memdesc into a list of allocated memory blocks for this file + * descriptor. The list is build in such a way that it implements FIFO (i.e. + * list). Traces of tiger, tiger_ri and VG11 CTs should be analysed to make + * informed choice. + * + * NOTE! gsl_memdesc_ts are COPIED so user space should NOT change them. + */ +int add_memblock_to_allocated_list(struct file *fd, + gsl_memdesc_t *allocated_block) +{ + int err = 0; + struct gsl_kmod_per_fd_data *datp; + struct gsl_kmod_alloc_list *lisp; + struct list_head *head; + + KOS_ASSERT(allocated_block); + + datp = get_fd_private_data(fd); + + head = &datp->allocated_blocks_head; + KOS_ASSERT(head); + + /* allocate and put new entry in the list of allocated memory descriptors */ + lisp = (struct gsl_kmod_alloc_list *)kzalloc(sizeof(struct gsl_kmod_alloc_list), GFP_KERNEL); + if(lisp) + { + INIT_LIST_HEAD(&lisp->node); + + /* builds FIFO (list_add() would build LIFO) */ + list_add_tail(&lisp->node, head); + memcpy(&lisp->allocated_block, allocated_block, sizeof(gsl_memdesc_t)); + lisp->allocation_number = datp->maximum_number_of_blocks; +// printk(KERN_DEBUG "List entry #%u allocated\n", lisp->allocation_number); + + datp->maximum_number_of_blocks++; + datp->number_of_allocated_blocks++; + + err = 0; + } + else + { + printk(KERN_ERR "%s: Could not allocate new list element\n", __func__); + err = -ENOMEM; + } + + return err; +} + +/* Delete a previously allocated memdesc from a list of allocated memory blocks */ +int del_memblock_from_allocated_list(struct file *fd, + gsl_memdesc_t *freed_block) +{ + struct gsl_kmod_per_fd_data *datp; + struct gsl_kmod_alloc_list *cursor, *next; + struct list_head *head; +// int is_different; + + KOS_ASSERT(freed_block); + + datp = get_fd_private_data(fd); + + head = &datp->allocated_blocks_head; + KOS_ASSERT(head); + + KOS_ASSERT(datp->number_of_allocated_blocks > 0); + + if(!list_empty(head)) + { + list_for_each_entry_safe(cursor, next, head, node) + { + if(cursor->allocated_block.gpuaddr == freed_block->gpuaddr) + { +// is_different = memcmp(&cursor->allocated_block, freed_block, sizeof(gsl_memdesc_t)); +// KOS_ASSERT(!is_different); + + list_del(&cursor->node); +// printk(KERN_DEBUG "List entry #%u freed\n", cursor->allocation_number); + kfree(cursor); + datp->number_of_allocated_blocks--; + return 0; + } + } + } + return -EINVAL; // tried to free entry not existing or from empty list. +} + +/* Delete all previously allocated memdescs from a list */ +int del_all_memblocks_from_allocated_list(struct file *fd) +{ + struct gsl_kmod_per_fd_data *datp; + struct gsl_kmod_alloc_list *cursor, *next; + struct list_head *head; + + datp = get_fd_private_data(fd); + + head = &datp->allocated_blocks_head; + KOS_ASSERT(head); + + if(!list_empty(head)) + { + printk(KERN_INFO "Not all allocated memory blocks were freed. Doing it now.\n"); + list_for_each_entry_safe(cursor, next, head, node) + { + printk(KERN_INFO "Freeing list entry #%u, gpuaddr=%x\n", (u32)cursor->allocation_number, cursor->allocated_block.gpuaddr); + kgsl_sharedmem_free(&cursor->allocated_block); + list_del(&cursor->node); + kfree(cursor); + } + } + + KOS_ASSERT(list_empty(head)); + datp->number_of_allocated_blocks = 0; + + return 0; +} + +void init_created_contexts_array(s8 *array) +{ + memset((void*)array, EMPTY_ENTRY, GSL_DEVICE_MAX * GSL_CONTEXT_MAX); +} + + +void add_device_context_to_array(struct file *fd, + gsl_deviceid_t device_id, + unsigned int context_id) +{ + struct gsl_kmod_per_fd_data *datp; + s8 *entry; + s8 *subarray; + u32 device_index = device_id_to_device_index(device_id); + + datp = get_fd_private_data(fd); + + subarray = datp->created_contexts_array[device_index]; + entry = find_first_entry_with(subarray, EMPTY_ENTRY); + + KOS_ASSERT(entry); + KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) && + (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX)); + KOS_ASSERT(context_id < 127); + *entry = (s8)context_id; +} + +void del_device_context_from_array(struct file *fd, + gsl_deviceid_t device_id, + unsigned int context_id) +{ + struct gsl_kmod_per_fd_data *datp; + u32 device_index = device_id_to_device_index(device_id); + s8 *entry; + s8 *subarray; + + datp = get_fd_private_data(fd); + + KOS_ASSERT(context_id < 127); + subarray = &(datp->created_contexts_array[device_index][0]); + entry = find_first_entry_with(subarray, context_id); + KOS_ASSERT(entry); + KOS_ASSERT((datp->created_contexts_array[device_index] <= entry) && + (entry < datp->created_contexts_array[device_index] + GSL_CONTEXT_MAX)); + *entry = EMPTY_ENTRY; +} + +void del_all_devices_contexts(struct file *fd) +{ + struct gsl_kmod_per_fd_data *datp; + gsl_deviceid_t id; + u32 device_index; + u32 ctx_array_index; + s8 ctx; + int err; + + datp = get_fd_private_data(fd); + + /* device_id is 1 based */ + for(id = GSL_DEVICE_ANY + 1; id <= GSL_DEVICE_MAX; id++) + { + device_index = device_id_to_device_index(id); + for(ctx_array_index = 0; ctx_array_index < GSL_CONTEXT_MAX; ctx_array_index++) + { + ctx = datp->created_contexts_array[device_index][ctx_array_index]; + if(ctx != EMPTY_ENTRY) + { + err = kgsl_context_destroy(id, ctx); + if(err != GSL_SUCCESS) + { + printk(KERN_ERR "%s: could not destroy context %d on device id = %u\n", __func__, ctx, id); + } + else + { + printk(KERN_DEBUG "%s: Destroyed context %d on device id = %u\n", __func__, ctx, id); + } + } + } + } +} + diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h new file mode 100644 index 000000000000..475ee3be2e50 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_kmod_cleanup.h @@ -0,0 +1,90 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_KMOD_CLEANUP_H +#define __GSL_KMOD_CLEANUP_H +#include "gsl_types.h" + +#include +#include +#include +#include + +#if (GSL_CONTEXT_MAX > 127) + #error created_contexts_array supports context numbers only 127 or less. +#endif + +static const s8 EMPTY_ENTRY = -1; + +/* A structure to make list of allocated memory blocks. List per fd. */ +/* should probably be allocated from slab cache to minimise fragmentation */ +struct gsl_kmod_alloc_list +{ + struct list_head node; + gsl_memdesc_t allocated_block; + u32 allocation_number; +}; + +/* A structure to hold abovementioned list of blocks. Contain per fd data. */ +struct gsl_kmod_per_fd_data +{ + struct list_head allocated_blocks_head; // list head + u32 maximum_number_of_blocks; + u32 number_of_allocated_blocks; + s8 created_contexts_array[GSL_DEVICE_MAX][GSL_CONTEXT_MAX]; +}; + + +/* + * prototypes + */ + +/* allocated memory block tracking */ +int add_memblock_to_allocated_list(struct file *fd, + gsl_memdesc_t *allocated_block); + +int del_memblock_from_allocated_list(struct file *fd, + gsl_memdesc_t *freed_block); + +int del_all_memblocks_from_allocated_list(struct file *fd); + +/* created contexts tracking */ +void init_created_contexts_array(s8 *array); + +void add_device_context_to_array(struct file *fd, + gsl_deviceid_t device_id, + unsigned int context_id); + +void del_device_context_from_array(struct file *fd, + gsl_deviceid_t device_id, + unsigned int context_id); + +void del_all_devices_contexts(struct file *fd); + +#endif // __GSL_KMOD_CLEANUP_H + diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c new file mode 100644 index 000000000000..7fee7b814411 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.c @@ -0,0 +1,221 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "gsl_linux_map.h" + +struct gsl_linux_map +{ + struct list_head list; + unsigned int gpu_addr; + void *kernel_virtual_addr; + unsigned int size; +}; + +static LIST_HEAD(gsl_linux_map_list); +static DEFINE_MUTEX(gsl_linux_map_mutex); + +int gsl_linux_map_init() +{ + mutex_lock(&gsl_linux_map_mutex); + INIT_LIST_HEAD(&gsl_linux_map_list); + mutex_unlock(&gsl_linux_map_mutex); + + return 0; +} + +void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size) +{ + struct gsl_linux_map * map; + struct list_head *p; + void *va; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr == gpu_addr){ + mutex_unlock(&gsl_linux_map_mutex); + return map->kernel_virtual_addr; + } + } + + va = __vmalloc(size, GFP_KERNEL, pgprot_noncached(pgprot_kernel)); + if(va == NULL){ + mutex_unlock(&gsl_linux_map_mutex); + return NULL; + } + + map = (struct gsl_linux_map *)kmalloc(sizeof(*map), GFP_KERNEL); + map->gpu_addr = gpu_addr; + map->kernel_virtual_addr = va; + map->size = size; + + INIT_LIST_HEAD(&map->list); + list_add_tail(&map->list, &gsl_linux_map_list); + + mutex_unlock(&gsl_linux_map_mutex); + return va; +} + +void gsl_linux_map_free(unsigned int gpu_addr) +{ + int found = 0; + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr == gpu_addr){ + found = 1; + break; + } + } + + if(found){ + vfree(map->kernel_virtual_addr); + list_del(&map->list); + kfree(map); + } + + mutex_unlock(&gsl_linux_map_mutex); +} + +void *gsl_linux_map_find(unsigned int gpu_addr) +{ + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr == gpu_addr){ + mutex_unlock(&gsl_linux_map_mutex); + return map->kernel_virtual_addr; + } + } + + mutex_unlock(&gsl_linux_map_mutex); + return NULL; +} + +void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace) +{ + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr <= gpuoffset && + (map->gpu_addr + map->size) > gpuoffset){ + void *src = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr); + mutex_unlock(&gsl_linux_map_mutex); + if (touserspace) + { + return (void *)copy_to_user(dst, map->kernel_virtual_addr + gpuoffset - map->gpu_addr, sizebytes); + } + else + { + return memcpy(dst, src, sizebytes); + } + } + } + + mutex_unlock(&gsl_linux_map_mutex); + return NULL; +} + +void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace) +{ + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr <= gpuoffset && + (map->gpu_addr + map->size) > gpuoffset){ + void *dst = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr); + mutex_unlock(&gsl_linux_map_mutex); + if (fromuserspace) + { + return (void *)copy_from_user(map->kernel_virtual_addr + gpuoffset - map->gpu_addr, src, sizebytes); + } + else + { + return memcpy(dst, src, sizebytes); + } + } + } + + mutex_unlock(&gsl_linux_map_mutex); + return NULL; +} + +void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes) +{ + struct gsl_linux_map * map; + struct list_head *p; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each(p, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + if(map->gpu_addr <= gpuoffset && + (map->gpu_addr + map->size) > gpuoffset){ + void *ptr = map->kernel_virtual_addr + (gpuoffset - map->gpu_addr); + mutex_unlock(&gsl_linux_map_mutex); + return memset(ptr, value, sizebytes); + } + } + + mutex_unlock(&gsl_linux_map_mutex); + return NULL; +} + +int gsl_linux_map_destroy() +{ + struct gsl_linux_map * map; + struct list_head *p, *tmp; + + mutex_lock(&gsl_linux_map_mutex); + + list_for_each_safe(p, tmp, &gsl_linux_map_list){ + map = list_entry(p, struct gsl_linux_map, list); + vfree(map->kernel_virtual_addr); + list_del(&map->list); + kfree(map); + } + + INIT_LIST_HEAD(&gsl_linux_map_list); + + mutex_unlock(&gsl_linux_map_mutex); + return 0; +} diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h new file mode 100644 index 000000000000..ebbe94a75e10 --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/gsl_linux_map.h @@ -0,0 +1,46 @@ +/* Copyright (c) 2008-2010, Advanced Micro Devices. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GSL_LINUX_MAP_H__ +#define __GSL_LINUX_MAP_H__ + +#include "gsl_halconfig.h" + +#define GSL_LINUX_MAP_RANGE_START (1024*1024) +#define GSL_LINUX_MAP_RANGE_END (GSL_LINUX_MAP_RANGE_START+GSL_HAL_SHMEM_SIZE_EMEM1_MMU) + +int gsl_linux_map_init(void); +void *gsl_linux_map_alloc(unsigned int gpu_addr, unsigned int size); +void gsl_linux_map_free(unsigned int gpu_addr); +void *gsl_linux_map_find(unsigned int gpu_addr); +void *gsl_linux_map_read(void *dst, unsigned int gpuoffset, unsigned int sizebytes, unsigned int touserspace); +void *gsl_linux_map_write(void *src, unsigned int gpuoffset, unsigned int sizebytes, unsigned int fromuserspace); +void *gsl_linux_map_set(unsigned int gpuoffset, unsigned int value, unsigned int sizebytes); +int gsl_linux_map_destroy(void); + +#endif diff --git a/drivers/mxc/amd-gpu/platform/hal/linux/misc.c b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c new file mode 100644 index 000000000000..877ea332e00f --- /dev/null +++ b/drivers/mxc/amd-gpu/platform/hal/linux/misc.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +#include +#include +#include +#include +#include + +typedef struct _gsl_autogate_t { + struct timer_list timer; + spinlock_t lock; + int active; + int timeout; + gsl_device_t *dev; + struct work_struct dis_task; +} gsl_autogate_t; + +static gsl_autogate_t *g_autogate[2]; +static DECLARE_MUTEX(sem_dev); + +#define KGSL_DEVICE_IDLE_TIMEOUT 5000 /* unit ms */ + +static void clk_disable_task(struct work_struct *work) +{ + gsl_autogate_t *autogate; + autogate = container_of(work, gsl_autogate_t, dis_task); + if (autogate->dev->ftbl.device_idle) + autogate->dev->ftbl.device_idle(autogate->dev, GSL_TIMEOUT_DEFAULT); + kgsl_clock(autogate->dev->id, 0); +} + +static int _kgsl_device_active(gsl_device_t *dev, int all) +{ + unsigned long flags; + int to_active = 0; + gsl_autogate_t *autogate = dev->autogate; + if (!autogate) { + printk(KERN_ERR "%s: autogate has exited!\n", __func__); + return 0; + } +// printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id, autogate->active); + + spin_lock_irqsave(&autogate->lock, flags); + if (in_interrupt()) { + if (!autogate->active) + BUG(); + } else { + to_active = !autogate->active; + autogate->active = 1; + } + mod_timer(&autogate->timer, jiffies + msecs_to_jiffies(autogate->timeout)); + spin_unlock_irqrestore(&autogate->lock, flags); + if (to_active) + kgsl_clock(autogate->dev->id, 1); + if (to_active && all) { + int index; + index = autogate->dev->id == GSL_DEVICE_G12 ? GSL_DEVICE_YAMATO - 1 : + GSL_DEVICE_G12 - 1; + down(&sem_dev); + if (g_autogate[index]) + _kgsl_device_active(g_autogate[index]->dev, 0); + up(&sem_dev); + } + return 0; +} +int kgsl_device_active(gsl_device_t *dev) +{ + return _kgsl_device_active(dev, 1); +} + +static void kgsl_device_inactive(unsigned long data) +{ + gsl_autogate_t *autogate = (gsl_autogate_t *)data; + unsigned long flags; + +// printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, autogate->dev->id, autogate->active); + del_timer(&autogate->timer); + spin_lock_irqsave(&autogate->lock, flags); + WARN(!autogate->active, "GPU Device %d is already inactive\n", autogate->dev->id); + if (autogate->active) { + autogate->active = 0; + schedule_work(&autogate->dis_task); + } + spin_unlock_irqrestore(&autogate->lock, flags); +} + +int kgsl_device_clock(gsl_deviceid_t id, int enable) +{ + int ret = GSL_SUCCESS; + gsl_device_t *device; + + device = &gsl_driver.device[id-1]; // device_id is 1 based + if (device->flags & GSL_FLAGS_INITIALIZED) { + if (enable) + kgsl_device_active(device); + else + kgsl_device_inactive((unsigned long)device); + } else { + printk(KERN_ERR "%s: Dev %d clock is already off!\n", __func__, id); + ret = GSL_FAILURE; + } + + return ret; +} + +int kgsl_device_autogate_init(gsl_device_t *dev) +{ + gsl_autogate_t *autogate; + +// printk(KERN_ERR "%s:%d id %d\n", __func__, __LINE__, dev->id); + autogate = kmalloc(sizeof(gsl_autogate_t), GFP_KERNEL); + if (!autogate) { + printk(KERN_ERR "%s: out of memory!\n", __func__); + return -ENOMEM; + } + down(&sem_dev); + autogate->dev = dev; + autogate->active = 1; + spin_lock_init(&autogate->lock); + autogate->timeout = KGSL_DEVICE_IDLE_TIMEOUT; + init_timer(&autogate->timer); + autogate->timer.expires = jiffies + msecs_to_jiffies(autogate->timeout); + autogate->timer.function = kgsl_device_inactive; + autogate->timer.data = (unsigned long)autogate; + add_timer(&autogate->timer); + INIT_WORK(&autogate->dis_task, clk_disable_task); + dev->autogate = autogate; + g_autogate[dev->id - 1] = autogate; + up(&sem_dev); + return 0; +} + +void kgsl_device_autogate_exit(gsl_device_t *dev) +{ + gsl_autogate_t *autogate = dev->autogate; + +// printk(KERN_ERR "%s:%d id %d active %d\n", __func__, __LINE__, dev->id, autogate->active); + down(&sem_dev); + del_timer_sync(&autogate->timer); + if (!autogate->active) + kgsl_clock(autogate->dev->id, 1); + flush_work(&autogate->dis_task); + g_autogate[dev->id - 1] = NULL; + up(&sem_dev); + kfree(autogate); + dev->autogate = NULL; +} diff --git a/drivers/mxc/asrc/Kconfig b/drivers/mxc/asrc/Kconfig new file mode 100644 index 000000000000..91c657079007 --- /dev/null +++ b/drivers/mxc/asrc/Kconfig @@ -0,0 +1,13 @@ +# +# ASRC configuration +# + +menu "MXC Asynchronous Sample Rate Converter support" + +config MXC_ASRC + tristate "ASRC support" + depends on ARCH_MX35 || ARCH_MX53 + ---help--- + Say Y to get the ASRC service. + +endmenu diff --git a/drivers/mxc/asrc/Makefile b/drivers/mxc/asrc/Makefile new file mode 100644 index 000000000000..7e9aba3abb56 --- /dev/null +++ b/drivers/mxc/asrc/Makefile @@ -0,0 +1,4 @@ +# +# Makefile for the kernel Asynchronous Sample Rate Converter driver +# +obj-$(CONFIG_MXC_ASRC) += mxc_asrc.o diff --git a/drivers/mxc/asrc/mxc_asrc.c b/drivers/mxc/asrc/mxc_asrc.c new file mode 100644 index 000000000000..932e7bbb19c6 --- /dev/null +++ b/drivers/mxc/asrc/mxc_asrc.c @@ -0,0 +1,1728 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_asrc.c + * + * @brief MXC Asynchronous Sample Rate Converter + * + * @ingroup SOUND + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int asrc_major; +static struct class *asrc_class; +#define ASRC_PROC_PATH "driver/asrc" + +#define ASRC_RATIO_DECIMAL_DEPTH 26 + +DEFINE_SPINLOCK(data_lock); +DEFINE_SPINLOCK(input_int_lock); +DEFINE_SPINLOCK(output_int_lock); + +#define AICPA 0 /* Input Clock Divider A Offset */ +#define AICDA 3 /* Input Clock Prescaler A Offset */ +#define AICPB 6 /* Input Clock Divider B Offset */ +#define AICDB 9 /* Input Clock Prescaler B Offset */ +#define AOCPA 12 /* Output Clock Divider A Offset */ +#define AOCDA 15 /* Output Clock Prescaler A Offset */ +#define AOCPB 18 /* Output Clock Divider B Offset */ +#define AOCDB 21 /* Output Clock Prescaler B Offset */ +#define AICPC 0 /* Input Clock Divider C Offset */ +#define AICDC 3 /* Input Clock Prescaler C Offset */ +#define AOCDC 6 /* Output Clock Prescaler C Offset */ +#define AOCPC 9 /* Output Clock Divider C Offset */ + +char *asrc_pair_id[] = { + [0] = "ASRC RX PAIR A", + [1] = "ASRC TX PAIR A", + [2] = "ASRC RX PAIR B", + [3] = "ASRC TX PAIR B", + [4] = "ASRC RX PAIR C", + [5] = "ASRC TX PAIR C", +}; + +enum asrc_status { + ASRC_ASRSTR_AIDEA = 0x01, + ASRC_ASRSTR_AIDEB = 0x02, + ASRC_ASRSTR_AIDEC = 0x04, + ASRC_ASRSTR_AODFA = 0x08, + ASRC_ASRSTR_AODFB = 0x10, + ASRC_ASRSTR_AODFC = 0x20, + ASRC_ASRSTR_AOLE = 0x40, + ASRC_ASRSTR_FPWT = 0x80, + ASRC_ASRSTR_AIDUA = 0x100, + ASRC_ASRSTR_AIDUB = 0x200, + ASRC_ASRSTR_AIDUC = 0x400, + ASRC_ASRSTR_AODOA = 0x800, + ASRC_ASRSTR_AODOB = 0x1000, + ASRC_ASRSTR_AODOC = 0x2000, + ASRC_ASRSTR_AIOLA = 0x4000, + ASRC_ASRSTR_AIOLB = 0x8000, + ASRC_ASRSTR_AIOLC = 0x10000, + ASRC_ASRSTR_AOOLA = 0x20000, + ASRC_ASRSTR_AOOLB = 0x40000, + ASRC_ASRSTR_AOOLC = 0x80000, + ASRC_ASRSTR_ATQOL = 0x100000, + ASRC_ASRSTR_DSLCNT = 0x200000, +}; + +/* Sample rates are aligned with that defined in pcm.h file */ +static const unsigned char asrc_process_table[][8][2] = { + /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */ +/*5512Hz*/ + {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*8kHz*/ + {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*11025Hz*/ + {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*16kHz*/ + {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*22050Hz*/ + {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, +/*32kHz*/ + {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, +/*44.1kHz*/ + {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, +/*48kHz*/ + {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, +/*64kHz*/ + {{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, +/*88.2kHz*/ + {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, +/*96kHz*/ + {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, +/*176kHz*/ + {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, +/*192kHz*/ + {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, +}; + +static const unsigned char asrc_divider_table[] = { +/*5500Hz 8kHz 11025Hz 16kHz 22050kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176400Hz 192kHz*/ + 0x07, 0x15, 0x06, 0x14, 0x05, 0x13, 0x04, 0x04, 0x12, 0x03, 0x03, 0x02, + 0x02, +}; + +static struct asrc_data *g_asrc_data; +static struct proc_dir_entry *proc_asrc; +static unsigned long asrc_vrt_base_addr; +static struct mxc_asrc_platform_data *mxc_asrc_data; + +/* The following tables map the relationship between asrc_inclk/asrc_outclk in + * mxc_asrc.h and the registers of ASRCSR + */ +static unsigned char input_clk_map_v1[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, +}; + +static unsigned char output_clk_map_v1[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, +}; + +static unsigned char input_clk_map_v2[] = { + 0, 1, 2, 3, 4, 5, 0xf, 0xf, 0xf, 8, 9, 0xa, 0xb, 0xc, 0xf, 0xd, +}; + +static unsigned char output_clk_map_v2[] = { + 8, 9, 0xa, 0, 0xc, 0x5, 0xf, 0xf, 0, 1, 2, 0xf, 0xf, 4, 0xf, 0xd, +}; + +static unsigned char *input_clk_map, *output_clk_map; + +static int asrc_set_clock_ratio(enum asrc_pair_index index, + int input_sample_rate, int output_sample_rate) +{ + int i; + int integ = 0; + unsigned long reg_val = 0; + + if (output_sample_rate == 0) + return -1; + while (input_sample_rate >= output_sample_rate) { + input_sample_rate -= output_sample_rate; + integ++; + } + reg_val |= (integ << 26); + + for (i = 1; i <= ASRC_RATIO_DECIMAL_DEPTH; i++) { + if ((input_sample_rate * 2) >= output_sample_rate) { + reg_val |= (1 << (ASRC_RATIO_DECIMAL_DEPTH - i)); + input_sample_rate = + input_sample_rate * 2 - output_sample_rate; + } else + input_sample_rate = input_sample_rate << 1; + + if (input_sample_rate == 0) + break; + } + + __raw_writel(reg_val, + (asrc_vrt_base_addr + ASRC_ASRIDRLA_REG + (index << 3))); + __raw_writel((reg_val >> 24), + (asrc_vrt_base_addr + ASRC_ASRIDRHA_REG + (index << 3))); + return 0; +} + +static int asrc_set_process_configuration(enum asrc_pair_index index, + int input_sample_rate, + int output_sample_rate) +{ + int i = 0, j = 0; + unsigned long reg; + switch (input_sample_rate) { + case 5512: + i = 0; + case 8000: + i = 1; + break; + case 11025: + i = 2; + break; + case 16000: + i = 3; + break; + case 22050: + i = 4; + break; + case 32000: + i = 5; + break; + case 44100: + i = 6; + break; + case 48000: + i = 7; + break; + case 64000: + i = 8; + break; + case 88200: + i = 9; + break; + case 96000: + i = 10; + break; + case 176400: + i = 11; + break; + case 192000: + i = 12; + break; + default: + return -1; + } + + switch (output_sample_rate) { + case 32000: + j = 0; + break; + case 44100: + j = 1; + break; + case 48000: + j = 2; + break; + case 64000: + j = 3; + break; + case 88200: + j = 4; + break; + case 96000: + j = 5; + break; + case 176400: + j = 6; + break; + case 192000: + j = 7; + break; + default: + return -1; + } + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG); + reg &= ~(0x0f << (6 + (index << 2))); + reg |= + ((asrc_process_table[i][j][0] << (6 + (index << 2))) | + (asrc_process_table[i][j][1] << (8 + (index << 2)))); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCFG_REG); + + return 0; +} + +static int asrc_get_asrck_clock_divider(int sample_rate) +{ + int i = 0; + switch (sample_rate) { + case 5500: + i = 0; + break; + case 8000: + i = 1; + break; + case 11025: + i = 2; + break; + case 16000: + i = 3; + break; + case 22050: + i = 4; + break; + case 32000: + i = 5; + break; + case 44100: + i = 6; + break; + case 48000: + i = 7; + break; + case 64000: + i = 8; + break; + case 88200: + i = 9; + break; + case 96000: + i = 10; + break; + case 176400: + i = 11; + break; + case 192000: + i = 12; + break; + default: + return -1; + } + + return asrc_divider_table[i]; +} + +int asrc_req_pair(int chn_num, enum asrc_pair_index *index) +{ + int err = 0; + unsigned long lock_flags; + spin_lock_irqsave(&data_lock, lock_flags); + + if (chn_num > 2) { + if (g_asrc_data->asrc_pair[ASRC_PAIR_C].active + || (chn_num > g_asrc_data->asrc_pair[ASRC_PAIR_C].chn_max)) + err = -EBUSY; + else { + *index = ASRC_PAIR_C; + g_asrc_data->asrc_pair[ASRC_PAIR_C].chn_num = chn_num; + g_asrc_data->asrc_pair[ASRC_PAIR_C].active = 1; + } + } else { + if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active || + (g_asrc_data->asrc_pair[ASRC_PAIR_A].chn_max == 0)) { + if (g_asrc_data->asrc_pair[ASRC_PAIR_B]. + active + || (g_asrc_data->asrc_pair[ASRC_PAIR_B]. + chn_max == 0)) + err = -EBUSY; + else { + *index = ASRC_PAIR_B; + g_asrc_data->asrc_pair[ASRC_PAIR_B].chn_num = 2; + g_asrc_data->asrc_pair[ASRC_PAIR_B].active = 1; + } + } else { + *index = ASRC_PAIR_A; + g_asrc_data->asrc_pair[ASRC_PAIR_A].chn_num = 2; + g_asrc_data->asrc_pair[ASRC_PAIR_A].active = 1; + } + } + spin_unlock_irqrestore(&data_lock, lock_flags); + return err; +} + +EXPORT_SYMBOL(asrc_req_pair); + +void asrc_release_pair(enum asrc_pair_index index) +{ + unsigned long reg; + unsigned long lock_flags; + + spin_lock_irqsave(&data_lock, lock_flags); + g_asrc_data->asrc_pair[index].active = 0; + g_asrc_data->asrc_pair[index].overload_error = 0; + /********Disable PAIR*************/ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg &= ~(1 << (index + 1)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + spin_unlock_irqrestore(&data_lock, lock_flags); +} + +EXPORT_SYMBOL(asrc_release_pair); + +int asrc_config_pair(struct asrc_config *config) +{ + int err = 0; + int reg, tmp, channel_num; + unsigned long lock_flags; + /* Set the channel number */ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + spin_lock_irqsave(&data_lock, lock_flags); + g_asrc_data->asrc_pair[config->pair].chn_num = config->channel_num; + spin_unlock_irqrestore(&data_lock, lock_flags); + reg &= + ~((0xFFFFFFFF >> (32 - mxc_asrc_data->channel_bits)) << + (mxc_asrc_data->channel_bits * config->pair)); + if (mxc_asrc_data->channel_bits > 3) + channel_num = config->channel_num; + else + channel_num = (config->channel_num + 1) / 2; + tmp = channel_num << (mxc_asrc_data->channel_bits * config->pair); + reg |= tmp; + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + + /* Set the clock source */ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCSR_REG); + tmp = ~(0x0f << (config->pair << 2)); + reg &= tmp; + tmp = ~(0x0f << (12 + (config->pair << 2))); + reg &= tmp; + reg |= + ((input_clk_map[config->inclk] << (config->pair << 2)) | (output_clk_map[config-> + outclk] << (12 + + (config-> + pair << + 2)))); + + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCSR_REG); + + /* default setting */ + /* automatic selection for processing mode */ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg |= (1 << (20 + config->pair)); + reg &= ~(1 << (14 + (config->pair << 1))); + + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRRA_REG); + reg &= 0xffbfffff; + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRRA_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg = reg & (~(1 << 23)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + + /* Default Clock Divider Setting */ + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + if (config->pair == ASRC_PAIR_A) { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + reg &= 0xfc0fc0; + /* Input Part */ + if ((config->inclk & 0x0f) == INCLK_SPDIF_RX) + reg |= 7 << AICPA; + else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX) + reg |= 6 << AICPA; + else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { + tmp = + asrc_get_asrck_clock_divider(config-> + input_sample_rate); + reg |= tmp << AICPA; + } else { + if (config->word_width == 16 || config->word_width == 8) + reg |= 5 << AICPA; + else if (config->word_width == 32 + || config->word_width == 24) + reg |= 6 << AICPA; + else + err = -EFAULT; + } + /* Output Part */ + if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX) + reg |= 7 << AOCPA; + else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX) + reg |= 6 << AOCPA; + else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { + tmp = + asrc_get_asrck_clock_divider(config-> + output_sample_rate); + reg |= tmp << AOCPA; + } else { + if (config->word_width == 16 || config->word_width == 8) + reg |= 5 << AOCPA; + else if (config->word_width == 32 + || config->word_width == 24) + reg |= 6 << AOCPA; + else + err = -EFAULT; + } + + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + + } else if (config->pair == ASRC_PAIR_B) { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + reg &= 0x03f03f; + /* Input Part */ + if ((config->inclk & 0x0f) == INCLK_SPDIF_RX) + reg |= 7 << AICPB; + else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX) + reg |= 6 << AICPB; + else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { + tmp = + asrc_get_asrck_clock_divider(config-> + input_sample_rate); + reg |= tmp << AICPB; + } else { + if (config->word_width == 16 || config->word_width == 8) + reg |= 5 << AICPB; + else if (config->word_width == 32 + || config->word_width == 24) + reg |= 6 << AICPB; + else + err = -EFAULT; + } + /* Output Part */ + if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX) + reg |= 7 << AOCPB; + else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX) + reg |= 6 << AOCPB; + else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { + tmp = + asrc_get_asrck_clock_divider(config-> + output_sample_rate); + reg |= tmp << AOCPB; + } else { + if (config->word_width == 16 || config->word_width == 8) + reg |= 5 << AOCPB; + else if (config->word_width == 32 + || config->word_width == 24) + reg |= 6 << AOCPB; + else + err = -EFAULT; + } + + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG); + + } else { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR2_REG); + reg &= 0; + /* Input Part */ + if ((config->inclk & 0x0f) == INCLK_SPDIF_RX) + reg |= 7 << AICPC; + else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX) + reg |= 6 << AICPC; + else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { + tmp = + asrc_get_asrck_clock_divider(config-> + input_sample_rate); + reg |= tmp << AICPC; + } else { + if (config->word_width == 16 || config->word_width == 8) + reg |= 5 << AICPC; + else if (config->word_width == 32 + || config->word_width == 24) + reg |= 6 << AICPC; + else + err = -EFAULT; + } + /* Output Part */ + if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX) + reg |= 7 << AOCPC; + else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX) + reg |= 6 << AOCPC; + else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { + tmp = + asrc_get_asrck_clock_divider(config-> + output_sample_rate); + reg |= tmp << AOCPC; + } else { + if (config->word_width == 16 || config->word_width == 8) + reg |= 5 << AOCPC; + else if (config->word_width == 32 + || config->word_width == 24) + reg |= 6 << AOCPC; + else + err = -EFAULT; + } + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR2_REG); + + } + + /* check whether ideal ratio is a must */ + if ((config->inclk & 0x0f) == INCLK_NONE) { + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg &= ~(1 << (20 + config->pair)); + reg |= (0x03 << (13 + (config->pair << 1))); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + err = asrc_set_clock_ratio(config->pair, + config->input_sample_rate, + config->output_sample_rate); + if (err < 0) + return err; + + err = asrc_set_process_configuration(config->pair, + config->input_sample_rate, + config-> + output_sample_rate); + if (err < 0) + return err; + } else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { + if (config->input_sample_rate == 44100 + || config->input_sample_rate == 88200) { + pr_info + ("ASRC core clock cann't support sample rate %d\n", + config->input_sample_rate); + err = -EFAULT; + } + } else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { + if (config->output_sample_rate == 44100 + || config->output_sample_rate == 88200) { + pr_info + ("ASRC core clock cann't support sample rate %d\n", + config->input_sample_rate); + err = -EFAULT; + } + } + + return err; +} + +EXPORT_SYMBOL(asrc_config_pair); + +void asrc_start_conv(enum asrc_pair_index index) +{ + int reg, reg_1; + unsigned long lock_flags; + int i; + + spin_lock_irqsave(&data_lock, lock_flags); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + if ((reg & 0x0E) == 0) + clk_enable(mxc_asrc_data->asrc_audio_clk); + reg |= (1 << (1 + index)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG); + while (!(reg & (1 << (index + 21)))) + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG); + reg_1 = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG); + + reg = 0; + for (i = 0; i < 20; i++) { + __raw_writel(reg, + asrc_vrt_base_addr + ASRC_ASRDIA_REG + + (index << 3)); + __raw_writel(reg, + asrc_vrt_base_addr + ASRC_ASRDIA_REG + + (index << 3)); + __raw_writel(reg, + asrc_vrt_base_addr + ASRC_ASRDIA_REG + + (index << 3)); + __raw_writel(reg, + asrc_vrt_base_addr + ASRC_ASRDIA_REG + + (index << 3)); + __raw_writel(reg, + asrc_vrt_base_addr + ASRC_ASRDIA_REG + + (index << 3)); + __raw_writel(reg, + asrc_vrt_base_addr + ASRC_ASRDIA_REG + + (index << 3)); + __raw_writel(reg, + asrc_vrt_base_addr + ASRC_ASRDIA_REG + + (index << 3)); + __raw_writel(reg, + asrc_vrt_base_addr + ASRC_ASRDIA_REG + + (index << 3)); + } + + __raw_writel(0x40, asrc_vrt_base_addr + ASRC_ASRIER_REG); + spin_unlock_irqrestore(&data_lock, lock_flags); + return; +} + +EXPORT_SYMBOL(asrc_start_conv); + +void asrc_stop_conv(enum asrc_pair_index index) +{ + int reg; + unsigned long lock_flags; + spin_lock_irqsave(&data_lock, lock_flags); + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); + reg &= ~(1 << (1 + index)); + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + if ((reg & 0x0E) == 0) + clk_disable(mxc_asrc_data->asrc_audio_clk); + spin_unlock_irqrestore(&data_lock, lock_flags); + return; +} + +EXPORT_SYMBOL(asrc_stop_conv); + +/*! + * @brief asrc interrupt handler + */ +static irqreturn_t asrc_isr(int irq, void *dev_id) +{ + unsigned long status; + int reg = 0x40; + + status = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG); + if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active == 1) { + if (status & ASRC_ASRSTR_ATQOL) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_TASK_Q_OVERLOAD; + if (status & ASRC_ASRSTR_AOOLA) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_OUTPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AIOLA) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_INPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AODOA) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_OUTPUT_BUFFER_OVERFLOW; + if (status & ASRC_ASRSTR_AIDUA) + g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= + ASRC_INPUT_BUFFER_UNDERRUN; + } else if (g_asrc_data->asrc_pair[ASRC_PAIR_B].active == 1) { + if (status & ASRC_ASRSTR_ATQOL) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_TASK_Q_OVERLOAD; + if (status & ASRC_ASRSTR_AOOLB) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_OUTPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AIOLB) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_INPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AODOB) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_OUTPUT_BUFFER_OVERFLOW; + if (status & ASRC_ASRSTR_AIDUB) + g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= + ASRC_INPUT_BUFFER_UNDERRUN; + } else if (g_asrc_data->asrc_pair[ASRC_PAIR_C].active == 1) { + if (status & ASRC_ASRSTR_ATQOL) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_TASK_Q_OVERLOAD; + if (status & ASRC_ASRSTR_AOOLC) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_OUTPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AIOLC) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_INPUT_TASK_OVERLOAD; + if (status & ASRC_ASRSTR_AODOC) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_OUTPUT_BUFFER_OVERFLOW; + if (status & ASRC_ASRSTR_AIDUC) + g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= + ASRC_INPUT_BUFFER_UNDERRUN; + } + + /* try to clean the overload error */ + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRSTR_REG); + + return IRQ_HANDLED; +} + +void asrc_get_status(struct asrc_status_flags *flags) +{ + unsigned long lock_flags; + enum asrc_pair_index index; + + spin_lock_irqsave(&data_lock, lock_flags); + index = flags->index; + flags->overload_error = g_asrc_data->asrc_pair[index].overload_error; + + spin_unlock_irqrestore(&data_lock, lock_flags); + return; +} + +EXPORT_SYMBOL(asrc_get_status); + +static int mxc_init_asrc(void) +{ + /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ + __raw_writel(0x0001, asrc_vrt_base_addr + ASRC_ASRCTR_REG); + + /* Enable overflow interrupt */ + __raw_writel(0x00, asrc_vrt_base_addr + ASRC_ASRIER_REG); + + /* Default 6: 2: 2 channel assignment */ + __raw_writel((0x06 << mxc_asrc_data->channel_bits * + 2) | (0x02 << mxc_asrc_data->channel_bits) | 0x02, + asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + + /* Parameter Registers recommended settings */ + __raw_writel(0x7fffff, asrc_vrt_base_addr + ASRC_ASRPM1_REG); + __raw_writel(0x255555, asrc_vrt_base_addr + ASRC_ASRPM2_REG); + __raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM3_REG); + __raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM4_REG); + __raw_writel(0xff7280, asrc_vrt_base_addr + ASRC_ASRPM5_REG); + + __raw_writel(0x001f00, asrc_vrt_base_addr + ASRC_ASRTFR1); + + /* Set the processing clock for 76KHz, 133M */ + __raw_writel(0x30E, asrc_vrt_base_addr + ASRC_ASR76K_REG); + + /* Set the processing clock for 56KHz, 133M */ + __raw_writel(0x0426, asrc_vrt_base_addr + ASRC_ASR56K_REG); + + return 0; +} + +static int asrc_get_output_buffer_size(int input_buffer_size, + int input_sample_rate, + int output_sample_rate) +{ + int i = 0; + int outbuffer_size = 0; + int outsample = output_sample_rate; + while (outsample >= input_sample_rate) { + ++i; + outsample -= input_sample_rate; + } + outbuffer_size = i * input_buffer_size; + i = 1; + while (((input_buffer_size >> i) > 2) && (outsample != 0)) { + if (((outsample << 1) - input_sample_rate) >= 0) { + outsample = (outsample << 1) - input_sample_rate; + outbuffer_size += (input_buffer_size >> i); + } else { + outsample = outsample << 1; + } + i++; + } + outbuffer_size = (outbuffer_size >> 3) << 3; + return outbuffer_size; +} + +static void asrc_input_dma_callback(void *data, int error, unsigned int count) +{ + struct asrc_pair_params *params; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + unsigned long lock_flags; + + params = data; + + spin_lock_irqsave(&input_int_lock, lock_flags); + params->input_queue_empty--; + if (!list_empty(¶ms->input_queue)) { + block = + list_entry(params->input_queue.next, + struct dma_block, queue); + dma_request.src_addr = (dma_addr_t) block->dma_paddr; + dma_request.dst_addr = + (ASRC_BASE_ADDR + ASRC_ASRDIA_REG + (params->index << 3)); + dma_request.num_of_bytes = block->length; + mxc_dma_config(params->input_dma_channel, &dma_request, + 1, MXC_DMA_MODE_WRITE); + list_del(params->input_queue.next); + list_add_tail(&block->queue, ¶ms->input_done_queue); + params->input_queue_empty++; + } + params->input_counter++; + wake_up_interruptible(¶ms->input_wait_queue); + spin_unlock_irqrestore(&input_int_lock, lock_flags); + return; +} + +static void asrc_output_dma_callback(void *data, int error, unsigned int count) +{ + struct asrc_pair_params *params; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + unsigned long lock_flags; + + params = data; + + spin_lock_irqsave(&output_int_lock, lock_flags); + params->output_queue_empty--; + + if (!list_empty(¶ms->output_queue)) { + block = + list_entry(params->output_queue.next, + struct dma_block, queue); + dma_request.src_addr = + (ASRC_BASE_ADDR + ASRC_ASRDOA_REG + (params->index << 3)); + dma_request.dst_addr = (dma_addr_t) block->dma_paddr; + dma_request.num_of_bytes = block->length; + mxc_dma_config(params->output_dma_channel, &dma_request, + 1, MXC_DMA_MODE_READ); + list_del(params->output_queue.next); + list_add_tail(&block->queue, ¶ms->output_done_queue); + params->output_queue_empty++; + } + params->output_counter++; + wake_up_interruptible(¶ms->output_wait_queue); + spin_unlock_irqrestore(&output_int_lock, lock_flags); + return; +} + +static void mxc_free_dma_buf(struct asrc_pair_params *params) +{ + int i; + for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) { + if (params->input_dma[i].dma_vaddr != NULL) { + dma_free_coherent(0, + params->input_buffer_size, + params->input_dma[i]. + dma_vaddr, + params->input_dma[i].dma_paddr); + params->input_dma[i].dma_vaddr = NULL; + } + if (params->output_dma[i].dma_vaddr != NULL) { + dma_free_coherent(0, + params->output_buffer_size, + params->output_dma[i]. + dma_vaddr, + params->output_dma[i].dma_paddr); + params->output_dma[i].dma_vaddr = NULL; + } + } + + return; +} + +static int mxc_allocate_dma_buf(struct asrc_pair_params *params) +{ + int i; + for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) { + params->input_dma[i].dma_vaddr = + dma_alloc_coherent(0, params->input_buffer_size, + ¶ms->input_dma[i].dma_paddr, + GFP_DMA | GFP_KERNEL); + if (params->input_dma[i].dma_vaddr == NULL) { + mxc_free_dma_buf(params); + pr_info("can't allocate buff\n"); + return -ENOBUFS; + } + } + for (i = 0; i < ASRC_DMA_BUFFER_NUM; i++) { + params->output_dma[i].dma_vaddr = + dma_alloc_coherent(0, + params->output_buffer_size, + ¶ms->output_dma[i].dma_paddr, + GFP_DMA | GFP_KERNEL); + if (params->output_dma[i].dma_vaddr == NULL) { + mxc_free_dma_buf(params); + return -ENOBUFS; + } + } + + return 0; +} + +/*! + * asrc interface - ioctl function + * + * @param inode struct inode * + * + * @param file struct file * + * + * @param cmd unsigned int + * + * @param arg unsigned long + * + * @return 0 success, ENODEV for invalid device instance, + * -1 for other errors. + */ +static int asrc_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int err = 0; + struct asrc_pair_params *params; + params = file->private_data; + + if (down_interruptible(¶ms->busy_lock)) + return -EBUSY; + switch (cmd) { + case ASRC_REQ_PAIR: + { + struct asrc_req req; + if (copy_from_user(&req, (void __user *)arg, + sizeof(struct asrc_req))) { + err = -EFAULT; + break; + } + err = asrc_req_pair(req.chn_num, &req.index); + if (err < 0) + break; + params->pair_hold = 1; + params->index = req.index; + if (copy_to_user + ((void __user *)arg, &req, sizeof(struct asrc_req))) + err = -EFAULT; + + break; + } + case ASRC_CONFIG_PAIR: + { + struct asrc_config config; + mxc_dma_device_t rx_id, tx_id; + char *rx_name, *tx_name; + int channel = -1; + if (copy_from_user + (&config, (void __user *)arg, + sizeof(struct asrc_config))) { + err = -EFAULT; + break; + } + err = asrc_config_pair(&config); + if (err < 0) + break; + params->output_buffer_size = + asrc_get_output_buffer_size(config. + dma_buffer_size, + config. + input_sample_rate, + config. + output_sample_rate); + params->input_buffer_size = config.dma_buffer_size; + if (config.buffer_num > ASRC_DMA_BUFFER_NUM) + params->buffer_num = ASRC_DMA_BUFFER_NUM; + else + params->buffer_num = config.buffer_num; + err = mxc_allocate_dma_buf(params); + if (err < 0) + break; + + /* TBD - need to update when new SDMA interface ready */ + if (config.pair == ASRC_PAIR_A) { + rx_id = MXC_DMA_ASRC_A_RX; + tx_id = MXC_DMA_ASRC_A_TX; + rx_name = asrc_pair_id[0]; + tx_name = asrc_pair_id[1]; + } else if (config.pair == ASRC_PAIR_B) { + rx_id = MXC_DMA_ASRC_B_RX; + tx_id = MXC_DMA_ASRC_B_TX; + rx_name = asrc_pair_id[2]; + tx_name = asrc_pair_id[3]; + } else { + rx_id = MXC_DMA_ASRC_C_RX; + tx_id = MXC_DMA_ASRC_C_TX; + rx_name = asrc_pair_id[4]; + tx_name = asrc_pair_id[5]; + } + channel = mxc_dma_request(rx_id, rx_name); + params->input_dma_channel = channel; + err = mxc_dma_callback_set(channel, (mxc_dma_callback_t) + asrc_input_dma_callback, + (void *)params); + channel = mxc_dma_request(tx_id, tx_name); + params->output_dma_channel = channel; + err = mxc_dma_callback_set(channel, (mxc_dma_callback_t) + asrc_output_dma_callback, + (void *)params); + /* TBD - need to update when new SDMA interface ready */ + params->input_queue_empty = 0; + params->output_queue_empty = 0; + INIT_LIST_HEAD(¶ms->input_queue); + INIT_LIST_HEAD(¶ms->input_done_queue); + INIT_LIST_HEAD(¶ms->output_queue); + INIT_LIST_HEAD(¶ms->output_done_queue); + init_waitqueue_head(¶ms->input_wait_queue); + init_waitqueue_head(¶ms->output_wait_queue); + + if (copy_to_user + ((void __user *)arg, &config, + sizeof(struct asrc_config))) + err = -EFAULT; + break; + } + case ASRC_QUERYBUF: + { + struct asrc_querybuf buffer; + if (copy_from_user + (&buffer, (void __user *)arg, + sizeof(struct asrc_querybuf))) { + err = -EFAULT; + break; + } + buffer.input_offset = + (unsigned long)params->input_dma[buffer. + buffer_index]. + dma_paddr; + buffer.input_length = params->input_buffer_size; + buffer.output_offset = + (unsigned long)params->output_dma[buffer. + buffer_index]. + dma_paddr; + buffer.output_length = params->output_buffer_size; + if (copy_to_user + ((void __user *)arg, &buffer, + sizeof(struct asrc_querybuf))) + err = -EFAULT; + break; + } + case ASRC_RELEASE_PAIR: + { + enum asrc_pair_index index; + if (copy_from_user + (&index, (void __user *)arg, + sizeof(enum asrc_pair_index))) { + err = -EFAULT; + break; + } + + mxc_dma_free(params->input_dma_channel); + mxc_dma_free(params->output_dma_channel); + mxc_free_dma_buf(params); + asrc_release_pair(index); + params->pair_hold = 0; + break; + } + case ASRC_Q_INBUF: + { + struct asrc_buffer buf; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + unsigned long lock_flags; + if (copy_from_user + (&buf, (void __user *)arg, + sizeof(struct asrc_buffer))) { + err = -EFAULT; + break; + } + spin_lock_irqsave(&input_int_lock, lock_flags); + params->input_dma[buf.index].index = buf.index; + params->input_dma[buf.index].length = buf.length; + list_add_tail(¶ms->input_dma[buf.index]. + queue, ¶ms->input_queue); + if (params->asrc_active == 0 + || params->input_queue_empty == 0) { + block = + list_entry(params->input_queue.next, + struct dma_block, queue); + dma_request.src_addr = + (dma_addr_t) block->dma_paddr; + dma_request.dst_addr = + (ASRC_BASE_ADDR + ASRC_ASRDIA_REG + + (params->index << 3)); + dma_request.num_of_bytes = block->length; + mxc_dma_config(params-> + input_dma_channel, + &dma_request, 1, + MXC_DMA_MODE_WRITE); + params->input_queue_empty++; + list_del(params->input_queue.next); + list_add_tail(&block->queue, + ¶ms->input_done_queue); + } + + spin_unlock_irqrestore(&input_int_lock, lock_flags); + break; + } + case ASRC_DQ_INBUF:{ + struct asrc_buffer buf; + struct dma_block *block; + unsigned long lock_flags; + if (copy_from_user + (&buf, (void __user *)arg, + sizeof(struct asrc_buffer))) { + err = -EFAULT; + break; + } + /* if ASRC is inactive, nonsense to DQ buffer */ + if (params->asrc_active == 0) { + err = -EFAULT; + buf.buf_valid = ASRC_BUF_NA; + if (copy_to_user + ((void __user *)arg, &buf, + sizeof(struct asrc_buffer))) + err = -EFAULT; + break; + } + + if (!wait_event_interruptible_timeout + (params->input_wait_queue, + params->input_counter != 0, 10 * HZ)) { + pr_info + ("ASRC_DQ_INBUF timeout counter %x\n", + params->input_counter); + err = -ETIME; + break; + } else if (signal_pending(current)) { + pr_info("ASRC_DQ_INBUF interrupt received\n"); + err = -ERESTARTSYS; + break; + } + spin_lock_irqsave(&input_int_lock, lock_flags); + params->input_counter--; + block = + list_entry(params->input_done_queue.next, + struct dma_block, queue); + list_del(params->input_done_queue.next); + spin_unlock_irqrestore(&input_int_lock, lock_flags); + buf.index = block->index; + buf.length = block->length; + buf.buf_valid = ASRC_BUF_AV; + if (copy_to_user + ((void __user *)arg, &buf, + sizeof(struct asrc_buffer))) + err = -EFAULT; + + break; + } + case ASRC_Q_OUTBUF:{ + struct asrc_buffer buf; + struct dma_block *block; + mxc_dma_requestbuf_t dma_request; + unsigned long lock_flags; + if (copy_from_user + (&buf, (void __user *)arg, + sizeof(struct asrc_buffer))) { + err = -EFAULT; + break; + } + spin_lock_irqsave(&output_int_lock, lock_flags); + params->output_dma[buf.index].index = buf.index; + params->output_dma[buf.index].length = buf.length; + list_add_tail(¶ms->output_dma[buf.index]. + queue, ¶ms->output_queue); + if (params->asrc_active == 0 + || params->output_queue_empty == 0) { + block = + list_entry(params->output_queue. + next, struct dma_block, queue); + dma_request.src_addr = + (ASRC_BASE_ADDR + ASRC_ASRDOA_REG + + (params->index << 3)); + dma_request.dst_addr = + (dma_addr_t) block->dma_paddr; + dma_request.num_of_bytes = block->length; + mxc_dma_config(params-> + output_dma_channel, + &dma_request, 1, + MXC_DMA_MODE_READ); + list_del(params->output_queue.next); + list_add_tail(&block->queue, + ¶ms->output_done_queue); + params->output_queue_empty++; + } + + spin_unlock_irqrestore(&output_int_lock, lock_flags); + break; + } + case ASRC_DQ_OUTBUF:{ + struct asrc_buffer buf; + struct dma_block *block; + unsigned long lock_flags; + if (copy_from_user + (&buf, (void __user *)arg, + sizeof(struct asrc_buffer))) { + err = -EFAULT; + break; + } + /* if ASRC is inactive, nonsense to DQ buffer */ + if (params->asrc_active == 0) { + buf.buf_valid = ASRC_BUF_NA; + err = -EFAULT; + if (copy_to_user + ((void __user *)arg, &buf, + sizeof(struct asrc_buffer))) + err = -EFAULT; + break; + } + + if (!wait_event_interruptible_timeout + (params->output_wait_queue, + params->output_counter != 0, 10 * HZ)) { + pr_info + ("ASRC_DQ_OUTBUF timeout counter %x\n", + params->output_counter); + err = -ETIME; + break; + } else if (signal_pending(current)) { + pr_info("ASRC_DQ_INBUF interrupt received\n"); + err = -ERESTARTSYS; + break; + } + spin_lock_irqsave(&output_int_lock, lock_flags); + params->output_counter--; + block = + list_entry(params->output_done_queue.next, + struct dma_block, queue); + list_del(params->output_done_queue.next); + spin_unlock_irqrestore(&output_int_lock, lock_flags); + buf.index = block->index; + buf.length = block->length; + buf.buf_valid = ASRC_BUF_AV; + if (copy_to_user + ((void __user *)arg, &buf, + sizeof(struct asrc_buffer))) + err = -EFAULT; + + break; + } + case ASRC_START_CONV:{ + enum asrc_pair_index index; + unsigned long lock_flags; + if (copy_from_user + (&index, (void __user *)arg, + sizeof(enum asrc_pair_index))) { + err = -EFAULT; + break; + } + + spin_lock_irqsave(&input_int_lock, lock_flags); + if (params->input_queue_empty == 0) { + err = -EFAULT; + pr_info + ("ASRC_START_CONV - no block available\n"); + break; + } + spin_unlock_irqrestore(&input_int_lock, lock_flags); + params->asrc_active = 1; + + asrc_start_conv(index); + mxc_dma_enable(params->input_dma_channel); + mxc_dma_enable(params->output_dma_channel); + break; + } + case ASRC_STOP_CONV:{ + enum asrc_pair_index index; + if (copy_from_user + (&index, (void __user *)arg, + sizeof(enum asrc_pair_index))) { + err = -EFAULT; + break; + } + mxc_dma_disable(params->input_dma_channel); + mxc_dma_disable(params->output_dma_channel); + asrc_stop_conv(index); + params->asrc_active = 0; + break; + } + case ASRC_STATUS:{ + struct asrc_status_flags flags; + if (copy_from_user + (&flags, (void __user *)arg, + sizeof(struct asrc_status_flags))) { + err = -EFAULT; + break; + } + asrc_get_status(&flags); + if (copy_to_user + ((void __user *)arg, &flags, + sizeof(struct asrc_status_flags))) + err = -EFAULT; + break; + } + case ASRC_FLUSH:{ + /* flush input dma buffer */ + unsigned long lock_flags; + mxc_dma_device_t rx_id, tx_id; + char *rx_name, *tx_name; + int channel = -1; + spin_lock_irqsave(&input_int_lock, lock_flags); + while (!list_empty(¶ms->input_queue)) + list_del(params->input_queue.next); + while (!list_empty(¶ms->input_done_queue)) + list_del(params->input_done_queue.next); + params->input_counter = 0; + params->input_queue_empty = 0; + spin_unlock_irqrestore(&input_int_lock, lock_flags); + + /* flush output dma buffer */ + spin_lock_irqsave(&output_int_lock, lock_flags); + while (!list_empty(¶ms->output_queue)) + list_del(params->output_queue.next); + while (!list_empty(¶ms->output_done_queue)) + list_del(params->output_done_queue.next); + params->output_counter = 0; + params->output_queue_empty = 0; + spin_unlock_irqrestore(&output_int_lock, lock_flags); + + /* release DMA and request again */ + mxc_dma_free(params->input_dma_channel); + mxc_dma_free(params->output_dma_channel); + if (params->index == ASRC_PAIR_A) { + rx_id = MXC_DMA_ASRC_A_RX; + tx_id = MXC_DMA_ASRC_A_TX; + rx_name = asrc_pair_id[0]; + tx_name = asrc_pair_id[1]; + } else if (params->index == ASRC_PAIR_B) { + rx_id = MXC_DMA_ASRC_B_RX; + tx_id = MXC_DMA_ASRC_B_TX; + rx_name = asrc_pair_id[2]; + tx_name = asrc_pair_id[3]; + } else { + rx_id = MXC_DMA_ASRC_C_RX; + tx_id = MXC_DMA_ASRC_C_TX; + rx_name = asrc_pair_id[4]; + tx_name = asrc_pair_id[5]; + } + channel = mxc_dma_request(rx_id, rx_name); + params->input_dma_channel = channel; + err = mxc_dma_callback_set(channel, (mxc_dma_callback_t) + asrc_input_dma_callback, + (void *)params); + channel = mxc_dma_request(tx_id, tx_name); + params->output_dma_channel = channel; + err = mxc_dma_callback_set(channel, (mxc_dma_callback_t) + asrc_output_dma_callback, + (void *)params); + + break; + } + default: + break; + } + + up(¶ms->busy_lock); + return err; +} + +/*! + * asrc interface - open function + * + * @param inode structure inode * + * + * @param file structure file * + * + * @return status 0 success, ENODEV invalid device instance, + * ENOBUFS failed to allocate buffer, ERESTARTSYS interrupted by user + */ +static int mxc_asrc_open(struct inode *inode, struct file *file) +{ + int err = 0; + struct asrc_pair_params *pair_params; + if (signal_pending(current)) + return -EINTR; + pair_params = kzalloc(sizeof(struct asrc_pair_params), GFP_KERNEL); + if (pair_params == NULL) { + pr_debug("Failed to allocate pair_params\n"); + err = -ENOBUFS; + } + + init_MUTEX(&pair_params->busy_lock); + file->private_data = pair_params; + return err; +} + +/*! + * asrc interface - close function + * + * @param inode struct inode * + * @param file structure file * + * + * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error + */ +static int mxc_asrc_close(struct inode *inode, struct file *file) +{ + struct asrc_pair_params *pair_params; + pair_params = file->private_data; + if (pair_params->asrc_active == 1) { + mxc_dma_disable(pair_params->input_dma_channel); + mxc_dma_disable(pair_params->output_dma_channel); + asrc_stop_conv(pair_params->index); + wake_up_interruptible(&pair_params->input_wait_queue); + wake_up_interruptible(&pair_params->output_wait_queue); + } + if (pair_params->pair_hold == 1) { + mxc_dma_free(pair_params->input_dma_channel); + mxc_dma_free(pair_params->output_dma_channel); + mxc_free_dma_buf(pair_params); + asrc_release_pair(pair_params->index); + } + kfree(pair_params); + file->private_data = NULL; + return 0; +} + +/*! + * asrc interface - mmap function + * + * @param file structure file * + * + * @param vma structure vm_area_struct * + * + * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error + */ +static int mxc_asrc_mmap(struct file *file, struct vm_area_struct *vma) +{ + unsigned long size; + int res = 0; + size = vma->vm_end - vma->vm_start; + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) + return -ENOBUFS; + + vma->vm_flags &= ~VM_IO; + return res; +} + +static struct file_operations asrc_fops = { + .owner = THIS_MODULE, + .ioctl = asrc_ioctl, + .mmap = mxc_asrc_mmap, + .open = mxc_asrc_open, + .release = mxc_asrc_close, +}; + +static int asrc_read_proc_attr(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + unsigned long reg; + int len = 0; + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + + len += sprintf(page, "ANCA: %d\n", + (int)(reg & + (0xFFFFFFFF >> + (32 - mxc_asrc_data->channel_bits)))); + len += + sprintf(page + len, "ANCB: %d\n", + (int)((reg >> mxc_asrc_data-> + channel_bits) & (0xFFFFFFFF >> (32 - + mxc_asrc_data-> + channel_bits)))); + len += + sprintf(page + len, "ANCC: %d\n", + (int)((reg >> (mxc_asrc_data->channel_bits * 2)) & + (0xFFFFFFFF >> (32 - mxc_asrc_data->channel_bits)))); + + if (off > len) + return 0; + + *eof = (len <= count) ? 1 : 0; + *start = page + off; + + return min(count, len - (int)off); +} + +static int asrc_write_proc_attr(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + char buf[50]; + unsigned long reg; + int na, nb, nc; + int total; + if (count > 48) + return -EINVAL; + if (copy_from_user(buf, buffer, count)) { + pr_debug("Attr proc write, Failed to copy buffer from user\n"); + return -EFAULT; + } + + reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + sscanf(buf, "ANCA: %d\nANCB: %d\nANCC: %d", &na, &nb, &nc); + if (mxc_asrc_data->channel_bits > 3) + total = 10; + else + total = 5; + if ((na + nb + nc) != total) { + pr_info("Wrong ASRCNR settings\n"); + return -EFAULT; + } + reg = na | (nb << mxc_asrc_data-> + channel_bits) | (nc << (mxc_asrc_data->channel_bits * 2)); + + __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCNCR_REG); + + return count; +} + +static void asrc_proc_create(void) +{ + struct proc_dir_entry *proc_attr; + proc_asrc = proc_mkdir(ASRC_PROC_PATH, NULL); + if (proc_asrc) { + proc_attr = create_proc_entry("ChSettings", + S_IFREG | S_IRUGO | + S_IWUSR, proc_asrc); + if (proc_attr) { + proc_attr->read_proc = asrc_read_proc_attr; + proc_attr->write_proc = asrc_write_proc_attr; + proc_attr->size = 48; + proc_attr->uid = proc_attr->gid = 0; + } else { + remove_proc_entry(ASRC_PROC_PATH, NULL); + pr_info("Failed to create proc attribute entry \n"); + } + } else { + pr_info("ASRC: Failed to create proc entry %s\n", + ASRC_PROC_PATH); + } +} + +/*! + * Entry point for the asrc device + * + * @param pdev Pionter to the registered platform device + * @return Error code indicating success or failure + */ +static int mxc_asrc_probe(struct platform_device *pdev) +{ + int err = 0; + struct resource *res; + struct device *temp_class; + int irq; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOENT; + + g_asrc_data = kzalloc(sizeof(struct asrc_data), GFP_KERNEL); + + if (g_asrc_data == NULL) { + pr_info("Failed to allocate g_asrc_data\n"); + return -ENOMEM; + } + + g_asrc_data->asrc_pair[0].chn_max = 2; + g_asrc_data->asrc_pair[1].chn_max = 2; + g_asrc_data->asrc_pair[2].chn_max = 6; + g_asrc_data->asrc_pair[0].overload_error = 0; + g_asrc_data->asrc_pair[1].overload_error = 0; + g_asrc_data->asrc_pair[2].overload_error = 0; + + asrc_major = register_chrdev(asrc_major, "mxc_asrc", &asrc_fops); + if (asrc_major < 0) { + pr_info("Unable to register asrc device\n"); + err = -EBUSY; + goto error; + } + + asrc_class = class_create(THIS_MODULE, "mxc_asrc"); + if (IS_ERR(asrc_class)) { + err = PTR_ERR(asrc_class); + goto err_out_chrdev; + } + + temp_class = device_create(asrc_class, NULL, MKDEV(asrc_major, 0), + NULL, "mxc_asrc"); + if (IS_ERR(temp_class)) { + err = PTR_ERR(temp_class); + goto err_out_class; + } + + asrc_vrt_base_addr = + (unsigned long)ioremap(res->start, res->end - res->start + 1); + + mxc_asrc_data = + (struct mxc_asrc_platform_data *)pdev->dev.platform_data; + clk_enable(mxc_asrc_data->asrc_core_clk); + + switch (mxc_asrc_data->clk_map_ver) { + case 1: + input_clk_map = &input_clk_map_v1[0]; + output_clk_map = &output_clk_map_v1[0]; + break; + case 2: + default: + input_clk_map = &input_clk_map_v2[0]; + output_clk_map = &output_clk_map_v2[0]; + break; + } + irq = platform_get_irq(pdev, 0); + if (request_irq(irq, asrc_isr, 0, "asrc", NULL)) + return -1; + + asrc_proc_create(); + err = mxc_init_asrc(); + if (err < 0) + goto err_out_class; + + goto out; + + err_out_class: + clk_disable(mxc_asrc_data->asrc_core_clk); + device_destroy(asrc_class, MKDEV(asrc_major, 0)); + class_destroy(asrc_class); + err_out_chrdev: + unregister_chrdev(asrc_major, "mxc_asrc"); + error: + kfree(g_asrc_data); + out: + pr_info("mxc_asrc registered\n"); + return err; +} + +/*! + * Exit asrc device + * + * @param pdev Pionter to the registered platform device + * @return Error code indicating success or failure + */ +static int mxc_asrc_remove(struct platform_device *pdev) +{ + int irq = platform_get_irq(pdev, 0); + free_irq(irq, NULL); + kfree(g_asrc_data); + clk_disable(mxc_asrc_data->asrc_core_clk); + mxc_asrc_data = NULL; + iounmap((unsigned long __iomem *)asrc_vrt_base_addr); + remove_proc_entry("ChSettings", proc_asrc); + remove_proc_entry(ASRC_PROC_PATH, NULL); + device_destroy(asrc_class, MKDEV(asrc_major, 0)); + class_destroy(asrc_class); + unregister_chrdev(asrc_major, "mxc_asrc"); + return 0; +} + +/*! mxc asrc driver definition + * + */ +static struct platform_driver mxc_asrc_driver = { + .driver = { + .name = "mxc_asrc", + }, + .probe = mxc_asrc_probe, + .remove = mxc_asrc_remove, +}; + +/*! + * Register asrc driver + * + */ +static __init int asrc_init(void) +{ + int ret; + ret = platform_driver_register(&mxc_asrc_driver); + return ret; +} + +/*! + * Exit and free the asrc data + * + */ static void __exit asrc_exit(void) +{ + platform_driver_unregister(&mxc_asrc_driver); + return; +} + +module_init(asrc_init); +module_exit(asrc_exit); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Asynchronous Sample Rate Converter"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/bt/Kconfig b/drivers/mxc/bt/Kconfig new file mode 100644 index 000000000000..9dbfbe57a14f --- /dev/null +++ b/drivers/mxc/bt/Kconfig @@ -0,0 +1,13 @@ +# +# Bluetooth configuration +# + +menu "MXC Bluetooth support" + +config MXC_BLUETOOTH + tristate "MXC Bluetooth support" + depends on MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS + ---help--- + Say Y to get the third party Bluetooth service. + +endmenu diff --git a/drivers/mxc/bt/Makefile b/drivers/mxc/bt/Makefile new file mode 100644 index 000000000000..91bc4cff380e --- /dev/null +++ b/drivers/mxc/bt/Makefile @@ -0,0 +1,4 @@ +# +# Makefile for the kernel Bluetooth power-on/reset +# +obj-$(CONFIG_MXC_BLUETOOTH) += mxc_bt.o diff --git a/drivers/mxc/bt/mxc_bt.c b/drivers/mxc/bt/mxc_bt.c new file mode 100644 index 000000000000..4ac37d06f2e9 --- /dev/null +++ b/drivers/mxc/bt/mxc_bt.c @@ -0,0 +1,128 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_bt.c + * + * @brief MXC Thirty party Bluetooth + * + */ + +#include +#include +#include +#include +#include +#include + +static struct regulator *bt_vdd; +static struct regulator *bt_vdd_parent; +static struct regulator *bt_vusb; +static struct regulator *bt_vusb_parent; + +/*! + * This function poweron the bluetooth hardware module + * + * @param pdev Pointer to the platform device + * @return 0 on success, -1 otherwise. + */ +static int mxc_bt_probe(struct platform_device *pdev) +{ + struct mxc_bt_platform_data *platform_data; + platform_data = (struct mxc_bt_platform_data *)pdev->dev.platform_data; + if (platform_data->bt_vdd) { + bt_vdd = regulator_get(&pdev->dev, platform_data->bt_vdd); + regulator_enable(bt_vdd); + } + if (platform_data->bt_vdd_parent) { + bt_vdd_parent = + regulator_get(&pdev->dev, platform_data->bt_vdd_parent); + regulator_enable(bt_vdd_parent); + } + if (platform_data->bt_vusb) { + bt_vusb = regulator_get(&pdev->dev, platform_data->bt_vusb); + regulator_enable(bt_vusb); + } + if (platform_data->bt_vusb_parent) { + bt_vusb_parent = + regulator_get(&pdev->dev, platform_data->bt_vusb_parent); + regulator_enable(bt_vusb_parent); + } + + if (platform_data->bt_reset != NULL) + platform_data->bt_reset(); + return 0; + +} + +/*! + * This function poweroff the bluetooth hardware module + * + * @param pdev Pointer to the platform device + * @return 0 on success, -1 otherwise. + */ +static int mxc_bt_remove(struct platform_device *pdev) +{ + struct mxc_bt_platform_data *platform_data; + platform_data = (struct mxc_bt_platform_data *)pdev->dev.platform_data; + if (bt_vdd) { + regulator_disable(bt_vdd); + regulator_put(bt_vdd); + } + if (bt_vdd_parent) { + regulator_disable(bt_vdd_parent); + regulator_put(bt_vdd_parent); + } + if (bt_vusb) { + regulator_disable(bt_vusb); + regulator_put(bt_vusb); + } + if (bt_vusb_parent) { + regulator_disable(bt_vusb_parent); + regulator_put(bt_vusb_parent); + } + return 0; + +} + +static struct platform_driver bluetooth_driver = { + .driver = { + .name = "mxc_bt", + }, + .probe = mxc_bt_probe, + .remove = mxc_bt_remove, +}; + +/*! + * Register bluetooth driver module + * + */ +static __init int bluetooth_init(void) +{ + return platform_driver_register(&bluetooth_driver); +} + +/*! + * Exit and free the bluetooth module + * + */ +static void __exit bluetooth_exit(void) +{ + platform_driver_unregister(&bluetooth_driver); +} + +module_init(bluetooth_init); +module_exit(bluetooth_exit); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Thirty party Bluetooth"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/dam/Kconfig b/drivers/mxc/dam/Kconfig new file mode 100644 index 000000000000..7b4bee92f648 --- /dev/null +++ b/drivers/mxc/dam/Kconfig @@ -0,0 +1,13 @@ +# +# DAM API configuration +# + +menu "MXC Digital Audio Multiplexer support" + +config MXC_DAM + tristate "DAM support" + depends on ARCH_MXC + ---help--- + Say Y to get the Digital Audio Multiplexer services API available on MXC platform. + +endmenu diff --git a/drivers/mxc/dam/Makefile b/drivers/mxc/dam/Makefile new file mode 100644 index 000000000000..b5afdc143dfa --- /dev/null +++ b/drivers/mxc/dam/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the kernel Digital Audio MUX (DAM) device driver. +# + +ifeq ($(CONFIG_ARCH_MX27),y) + obj-$(CONFIG_MXC_DAM) += dam_v1.o +else + obj-$(CONFIG_MXC_DAM) += dam.o +endif diff --git a/drivers/mxc/dam/dam.c b/drivers/mxc/dam/dam.c new file mode 100644 index 000000000000..76ce04e7f171 --- /dev/null +++ b/drivers/mxc/dam/dam.c @@ -0,0 +1,427 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dam.c + * @brief This is the brief documentation for this dam.c file. + * + * This file contains the implementation of the DAM driver main services + * + * @ingroup DAM + */ + +#include +#include +#include +#include +#include +#include "dam.h" + +/*! + * This include to define bool type, false and true definitions. + */ +#include + +#define ModifyRegister32(a, b, c) (c = (((c)&(~(a))) | (b))) + +#define DAM_VIRT_BASE_ADDR IO_ADDRESS(AUDMUX_BASE_ADDR) + +#ifndef _reg_DAM_PTCR1 +#define _reg_DAM_PTCR1 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x00))) +#endif + +#ifndef _reg_DAM_PDCR1 +#define _reg_DAM_PDCR1 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x04))) +#endif + +#ifndef _reg_DAM_PTCR2 +#define _reg_DAM_PTCR2 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x08))) +#endif + +#ifndef _reg_DAM_PDCR2 +#define _reg_DAM_PDCR2 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x0C))) +#endif + +#ifndef _reg_DAM_PTCR3 +#define _reg_DAM_PTCR3 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x10))) +#endif + +#ifndef _reg_DAM_PDCR3 +#define _reg_DAM_PDCR3 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x14))) +#endif + +#ifndef _reg_DAM_PTCR4 +#define _reg_DAM_PTCR4 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x18))) +#endif + +#ifndef _reg_DAM_PDCR4 +#define _reg_DAM_PDCR4 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x1C))) +#endif + +#ifndef _reg_DAM_PTCR5 +#define _reg_DAM_PTCR5 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x20))) +#endif + +#ifndef _reg_DAM_PDCR5 +#define _reg_DAM_PDCR5 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x24))) +#endif + +#ifndef _reg_DAM_PTCR6 +#define _reg_DAM_PTCR6 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x28))) +#endif + +#ifndef _reg_DAM_PDCR6 +#define _reg_DAM_PDCR6 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x2C))) +#endif + +#ifndef _reg_DAM_PTCR7 +#define _reg_DAM_PTCR7 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x30))) +#endif + +#ifndef _reg_DAM_PDCR7 +#define _reg_DAM_PDCR7 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x34))) +#endif + +#ifndef _reg_DAM_CNMCR +#define _reg_DAM_CNMCR (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x38))) +#endif + +#ifndef _reg_DAM_PTCR +#define _reg_DAM_PTCR(a) (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + a*8))) +#endif + +#ifndef _reg_DAM_PDCR +#define _reg_DAM_PDCR(a) (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 4 + a*8))) +#endif + +/*! + * PTCR Registers bit shift definitions + */ +#define dam_synchronous_mode_shift 11 +#define dam_receive_clock_select_shift 12 +#define dam_receive_clock_direction_shift 16 +#define dam_receive_frame_sync_select_shift 17 +#define dam_receive_frame_sync_direction_shift 21 +#define dam_transmit_clock_select_shift 22 +#define dam_transmit_clock_direction_shift 26 +#define dam_transmit_frame_sync_select_shift 27 +#define dam_transmit_frame_sync_direction_shift 31 +#define dam_selection_mask 0xF + +/*! + * HPDCR Register bit shift definitions + */ +#define dam_internal_network_mode_shift 0 +#define dam_mode_shift 8 +#define dam_transmit_receive_switch_shift 12 +#define dam_receive_data_select_shift 13 + +/*! + * HPDCR Register bit masq definitions + */ +#define dam_mode_masq 0x03 +#define dam_internal_network_mode_mask 0xFF + +/*! + * CNMCR Register bit shift definitions + */ +#define dam_ce_bus_port_cntlow_shift 0 +#define dam_ce_bus_port_cnthigh_shift 8 +#define dam_ce_bus_port_clkpol_shift 16 +#define dam_ce_bus_port_fspol_shift 17 +#define dam_ce_bus_port_enable_shift 18 + +#define DAM_NAME "dam" + +EXPORT_SYMBOL(dam_select_mode); +EXPORT_SYMBOL(dam_select_RxClk_direction); +EXPORT_SYMBOL(dam_select_RxClk_source); +EXPORT_SYMBOL(dam_select_RxD_source); +EXPORT_SYMBOL(dam_select_RxFS_direction); +EXPORT_SYMBOL(dam_select_RxFS_source); +EXPORT_SYMBOL(dam_select_TxClk_direction); +EXPORT_SYMBOL(dam_select_TxClk_source); +EXPORT_SYMBOL(dam_select_TxFS_direction); +EXPORT_SYMBOL(dam_select_TxFS_source); +EXPORT_SYMBOL(dam_set_internal_network_mode_mask); +EXPORT_SYMBOL(dam_set_synchronous); +EXPORT_SYMBOL(dam_switch_Tx_Rx); +EXPORT_SYMBOL(dam_reset_register); + +/*! + * This function selects the operation mode of the port. + * + * @param port the DAM port to configure + * @param the_mode the operation mode of the port + * + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_select_mode(dam_port port, dam_mode the_mode) +{ + int result; + result = 0; + + ModifyRegister32(dam_mode_masq << dam_mode_shift, + the_mode << dam_mode_shift, _reg_DAM_PDCR(port)); + + return result; +} + +/*! + * This function controls Receive clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx clock signal direction + */ +void dam_select_RxClk_direction(dam_port port, signal_direction direction) +{ + ModifyRegister32(1 << dam_receive_clock_direction_shift, + direction << dam_receive_clock_direction_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function controls Receive clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_RxClk_source(dam_port p_config, + bool from_RxClk, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << dam_receive_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_receive_clock_select_shift, + _reg_DAM_PTCR(p_config)); +} + +/*! + * This function selects the source port for the RxD data. + * + * @param p_config the DAM port to configure + * @param p_source the source port + */ +void dam_select_RxD_source(dam_port p_config, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << dam_receive_data_select_shift, + p_source << dam_receive_data_select_shift, + _reg_DAM_PDCR(p_config)); +} + +/*! + * This function controls Receive Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx Frame Sync signal direction + */ +void dam_select_RxFS_direction(dam_port port, signal_direction direction) +{ + ModifyRegister32(1 << dam_receive_frame_sync_direction_shift, + direction << dam_receive_frame_sync_direction_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function controls Receive Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_RxFS_source(dam_port p_config, + bool from_RxFS, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << + dam_receive_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_receive_frame_sync_select_shift, + _reg_DAM_PTCR(p_config)); +} + +/*! + * This function controls Transmit clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx clock signal direction + */ +void dam_select_TxClk_direction(dam_port port, signal_direction direction) +{ + ModifyRegister32(1 << dam_transmit_clock_direction_shift, + direction << dam_transmit_clock_direction_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function controls Transmit clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_TxClk_source(dam_port p_config, + bool from_RxClk, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << dam_transmit_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_transmit_clock_select_shift, + _reg_DAM_PTCR(p_config)); +} + +/*! + * This function controls Transmit Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx Frame Sync signal direction + */ +void dam_select_TxFS_direction(dam_port port, signal_direction direction) +{ + ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift, + direction << dam_transmit_frame_sync_direction_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function controls Transmit Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_TxFS_source(dam_port p_config, + bool from_RxFS, dam_port p_source) +{ + ModifyRegister32(dam_selection_mask << + dam_transmit_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_transmit_frame_sync_select_shift, + _reg_DAM_PTCR(p_config)); +} + +/*! + * This function sets a bit mask that selects the port from which of the RxD + * signals are to be ANDed together for internal network mode. + * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1. + * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing. + * + * @param port the DAM port to configure + * @param bit_mask the bit mask + * + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask) +{ + int result; + result = 0; + + ModifyRegister32(dam_internal_network_mode_mask << + dam_internal_network_mode_shift, + bit_mask << dam_internal_network_mode_shift, + _reg_DAM_PDCR(port)); + + return result; +} + +/*! + * This function controls whether or not the port is in synchronous mode. + * When the synchronous mode is selected, the receive and the transmit sections + * use common clock and frame sync signals. + * When the synchronous mode is not selected, separate clock and frame sync + * signals are used for the transmit and the receive sections. + * The defaut value is the synchronous mode selected. + * + * @param port the DAM port to configure + * @param synchronous the state to assign + */ +void dam_set_synchronous(dam_port port, bool synchronous) +{ + ModifyRegister32(1 << dam_synchronous_mode_shift, + synchronous << dam_synchronous_mode_shift, + _reg_DAM_PTCR(port)); +} + +/*! + * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD) + * to (Da-RxD, Db-TxD). + * This default signal configuration is Da-TxD, Db-RxD. + * + * @param port the DAM port to configure + * @param value the switch state + */ +void dam_switch_Tx_Rx(dam_port port, bool value) +{ + ModifyRegister32(1 << dam_transmit_receive_switch_shift, + value << dam_transmit_receive_switch_shift, + _reg_DAM_PDCR(port)); +} + +/*! + * This function resets the two registers of the selected port. + * + * @param port the DAM port to reset + */ +void dam_reset_register(dam_port port) +{ + ModifyRegister32(0xFFFFFFFF, 0x00000000, _reg_DAM_PTCR(port)); + ModifyRegister32(0xFFFFFFFF, 0x00000000, _reg_DAM_PDCR(port)); +} + +/*! + * This function implements the init function of the DAM device. + * This function is called when the module is loaded. + * + * @return This function returns 0. + */ +static int __init dam_init(void) +{ + return 0; +} + +/*! + * This function implements the exit function of the SPI device. + * This function is called when the module is unloaded. + * + */ +static void __exit dam_exit(void) +{ +} + +module_init(dam_init); +module_exit(dam_exit); + +MODULE_DESCRIPTION("DAM char device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/dam/dam.h b/drivers/mxc/dam/dam.h new file mode 100644 index 000000000000..ad49c8e3c5b1 --- /dev/null +++ b/drivers/mxc/dam/dam.h @@ -0,0 +1,258 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @defgroup DAM Digital Audio Multiplexer (AUDMUX) Driver + */ + + /*! + * @file dam.h + * @brief This is the brief documentation for this dam.h file. + * + * This header file contains DAM driver functions prototypes. + * + * @ingroup DAM + */ + +#ifndef __MXC_DAM_H__ +#define __MXC_DAM_H__ + +/*! + * This enumeration describes the Digital Audio Multiplexer mode. + */ +typedef enum { + + /*! + * Normal mode + */ + normal_mode = 0, + + /*! + * Internal network mode + */ + internal_network_mode = 1, + + /*! + * CE bus network mode + */ + CE_bus_network_mode = 2 +} dam_mode; + +/*! + * This enumeration describes the port. + */ +typedef enum { + + /*! + * The port 1 + */ + port_1 = 0, + + /*! + * The port 2 + */ + port_2 = 1, + + /*! + * The port 3 + */ + port_3 = 2, + + /*! + * The port 4 + */ + port_4 = 3, + + /*! + * The port 5 + */ + port_5 = 4, + + /*! + * The port 6 + */ + port_6 = 5, + + /*! + * The port 7 + */ + port_7 = 6 +} dam_port; + +/*! + * This enumeration describes the signal direction. + */ +typedef enum { + + /*! + * Signal In + */ + signal_in = 0, + + /*! + * Signal Out + */ + signal_out = 1 +} signal_direction; + +/*! + * Test purpose definition + */ +#define TEST_DAM 1 + +#ifdef TEST_DAM + +#define DAM_IOCTL 0x55 +#define DAM_CONFIG_SSI1_MC13783 _IOWR(DAM_IOCTL, 1, int) +#define DAM_CONFIG_SSI2_MC13783 _IOWR(DAM_IOCTL, 2, int) +#define DAM_CONFIG_SSI_NETWORK_MODE_MC13783 _IOWR(DAM_IOCTL, 3, int) +#endif + +/*! + * This function selects the operation mode of the port. + * + * @param port the DAM port to configure + * @param the_mode the operation mode of the port + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_select_mode(dam_port port, dam_mode the_mode); + +/*! + * This function controls Receive clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx clock signal direction + */ +void dam_select_RxClk_direction(dam_port port, signal_direction direction); + +/*! + * This function controls Receive clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_RxClk_source(dam_port p_config, bool from_RxClk, + dam_port p_source); + +/*! + * This function selects the source port for the RxD data. + * + * @param p_config the DAM port to configure + * @param p_source the source port + */ +void dam_select_RxD_source(dam_port p_config, dam_port p_source); + +/*! + * This function controls Receive Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx Frame Sync signal direction + */ +void dam_select_RxFS_direction(dam_port port, signal_direction direction); + +/*! + * This function controls Receive Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_RxFS_source(dam_port p_config, bool from_RxFS, + dam_port p_source); + +/*! + * This function controls Transmit clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx clock signal direction + */ +void dam_select_TxClk_direction(dam_port port, signal_direction direction); + +/*! + * This function controls Transmit clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_TxClk_source(dam_port p_config, bool from_RxClk, + dam_port p_source); + +/*! + * This function controls Transmit Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx Frame Sync signal direction + */ +void dam_select_TxFS_direction(dam_port port, signal_direction direction); + +/*! + * This function controls Transmit Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_TxFS_source(dam_port p_config, bool from_RxFS, + dam_port p_source); + +/*! + * This function sets a bit mask that selects the port from which of + * the RxD signals are to be ANDed together for internal network mode. + * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1. + * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing. + * + * @param port the DAM port to configure + * @param bit_mask the bit mask + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask); + +/*! + * This function controls whether or not the port is in synchronous mode. + * When the synchronous mode is selected, the receive and the transmit sections + * use common clock and frame sync signals. + * When the synchronous mode is not selected, separate clock and frame sync + * signals are used for the transmit and the receive sections. + * The defaut value is the synchronous mode selected. + * + * @param port the DAM port to configure + * @param synchronous the state to assign + */ +void dam_set_synchronous(dam_port port, bool synchronous); + +/*! + * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD) to + * (Da-RxD, Db-TxD). + * This default signal configuration is Da-TxD, Db-RxD. + * + * @param port the DAM port to configure + * @param value the switch state + */ +void dam_switch_Tx_Rx(dam_port port, bool value); + +/*! + * This function resets the two registers of the selected port. + * + * @param port the DAM port to reset + */ +void dam_reset_register(dam_port port); + +#endif diff --git a/drivers/mxc/dam/dam_v1.c b/drivers/mxc/dam/dam_v1.c new file mode 100644 index 000000000000..b6c9a6f068e5 --- /dev/null +++ b/drivers/mxc/dam/dam_v1.c @@ -0,0 +1,617 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dam_v1.c + * @brief This is the brief documentation for this dam_v1.c file. + * + * This file contains the implementation of the DAM driver main services + * + * @ingroup DAM + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dam.h" + +/*! + * This include to define bool type, false and true definitions. + */ +#include + +#define DAM_VIRT_BASE_ADDR IO_ADDRESS(AUDMUX_BASE_ADDR) + +#define ModifyRegister32(a, b, c) do {\ + __raw_writel(((__raw_readl(c)) & (~(a))) | (b), (c));\ +} while (0) + +#ifndef _reg_DAM_HPCR1 +#define _reg_DAM_HPCR1 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x00))) +#endif + +#ifndef _reg_DAM_HPCR2 +#define _reg_DAM_HPCR2 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x04))) +#endif + +#ifndef _reg_DAM_HPCR3 +#define _reg_DAM_HPCR3 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x08))) +#endif + +#ifndef _reg_DAM_PPCR1 +#define _reg_DAM_PPCR1 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x10))) +#endif + +#ifndef _reg_DAM_PPCR2 +#define _reg_DAM_PPCR2 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x14))) +#endif + +#ifndef _reg_DAM_PPCR3 +#define _reg_DAM_PPCR3 (*((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x1c))) +#endif + +#ifndef _reg_DAM_HPCR +#define _reg_DAM_HPCR(a) ((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + (a)*4)) +#endif + +#ifndef _reg_DAM_PPCR +#define _reg_DAM_PPCR(a) ((volatile unsigned long *) \ + (DAM_VIRT_BASE_ADDR + 0x0c + (0x04 << (a-3)))) +#endif + +/*! + * HPCR/PPCR Registers bit shift definitions + */ +#define dam_transmit_frame_sync_direction_shift 31 +#define dam_transmit_clock_direction_shift 30 +#define dam_transmit_frame_sync_select_shift 26 +#define dam_transmit_clock_select_shift 26 +#define dam_receive_frame_sync_direction_shift 25 +#define dam_receive_clock_direction_shift 24 +#define dam_receive_clock_select_shift 20 +#define dam_receive_frame_sync_select_shift 20 + +#define dam_receive_data_select_shift 13 +#define dam_synchronous_mode_shift 12 + +#define dam_transmit_receive_switch_shift 10 + +#define dam_mode_shift 8 +#define dam_internal_network_mode_shift 0 + +/*! + * HPCR/PPCR Register bit masq definitions + */ +/*#define dam_selection_mask 0xF*/ +#define dam_fs_selection_mask 0xF +#define dam_clk_selection_mask 0xF +#define dam_dat_selection_mask 0x7 +/*#define dam_mode_masq 0x03*/ +#define dam_internal_network_mode_mask 0xFF + +/*! + * HPCR/PPCR Register reset value definitions + */ +#define dam_hpcr_default_value 0x00001000 +#define dam_ppcr_default_value 0x00001000 + +#define DAM_NAME "dam" +static struct class *mxc_dam_class; + +EXPORT_SYMBOL(dam_select_mode); +EXPORT_SYMBOL(dam_select_RxClk_direction); +EXPORT_SYMBOL(dam_select_RxClk_source); +EXPORT_SYMBOL(dam_select_RxD_source); +EXPORT_SYMBOL(dam_select_RxFS_direction); +EXPORT_SYMBOL(dam_select_RxFS_source); +EXPORT_SYMBOL(dam_select_TxClk_direction); +EXPORT_SYMBOL(dam_select_TxClk_source); +EXPORT_SYMBOL(dam_select_TxFS_direction); +EXPORT_SYMBOL(dam_select_TxFS_source); +EXPORT_SYMBOL(dam_set_internal_network_mode_mask); +EXPORT_SYMBOL(dam_set_synchronous); +EXPORT_SYMBOL(dam_switch_Tx_Rx); +EXPORT_SYMBOL(dam_reset_register); + +/*! + * DAM major + */ +#ifdef TEST_DAM +static int major_dam; + +typedef struct _mxc_cfg { + int reg; + int val; +} mxc_cfg; + +#endif + +/*! + * This function selects the operation mode of the port. + * + * @param port the DAM port to configure + * @param the_mode the operation mode of the port + * + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_select_mode(dam_port port, dam_mode the_mode) +{ + int result; + result = 0; + + if (port >= 3) + the_mode = normal_mode; + ModifyRegister32(1 << dam_mode_shift, + the_mode << dam_mode_shift, _reg_DAM_HPCR(port)); + + return result; +} + +/*! + * This function controls Receive clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx clock signal direction + */ +void dam_select_RxClk_direction(dam_port port, signal_direction direction) +{ + if (port < 3) { + ModifyRegister32(1 << dam_receive_clock_direction_shift, + direction << dam_receive_clock_direction_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_receive_clock_direction_shift, + direction << dam_receive_clock_direction_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function controls Receive clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_RxClk_source(dam_port p_config, + bool from_RxClk, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_clk_selection_mask << + dam_receive_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_receive_clock_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_clk_selection_mask << + dam_receive_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_receive_clock_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function selects the source port for the RxD data. + * + * @param p_config the DAM port to configure + * @param p_source the source port + */ +void dam_select_RxD_source(dam_port p_config, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_dat_selection_mask << + dam_receive_data_select_shift, + p_source << dam_receive_data_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_dat_selection_mask << + dam_receive_data_select_shift, + p_source << dam_receive_data_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function controls Receive Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Rx Frame Sync signal direction + */ +void dam_select_RxFS_direction(dam_port port, signal_direction direction) +{ + if (port < 3) { + ModifyRegister32(1 << dam_receive_frame_sync_direction_shift, + direction << + dam_receive_frame_sync_direction_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_receive_frame_sync_direction_shift, + direction << + dam_receive_frame_sync_direction_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function controls Receive Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_RxFS_source(dam_port p_config, + bool from_RxFS, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_fs_selection_mask << + dam_receive_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_receive_frame_sync_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_fs_selection_mask << + dam_receive_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_receive_frame_sync_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function controls Transmit clock signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx clock signal direction + */ +void dam_select_TxClk_direction(dam_port port, signal_direction direction) +{ + if (port < 3) { + ModifyRegister32(1 << dam_transmit_clock_direction_shift, + direction << + dam_transmit_clock_direction_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_transmit_clock_direction_shift, + direction << + dam_transmit_clock_direction_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function controls Transmit clock signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxClk the signal comes from RxClk or TxClk of + * the source port + * @param p_source the source port + */ +void dam_select_TxClk_source(dam_port p_config, + bool from_RxClk, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_clk_selection_mask << + dam_transmit_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_transmit_clock_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_clk_selection_mask << + dam_transmit_clock_select_shift, + ((from_RxClk << 3) | p_source) << + dam_transmit_clock_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function controls Transmit Frame Sync signal direction for the port. + * + * @param port the DAM port to configure + * @param direction the Tx Frame Sync signal direction + */ +void dam_select_TxFS_direction(dam_port port, signal_direction direction) +{ + if (port < 3) { + ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift, + direction << + dam_transmit_frame_sync_direction_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_transmit_frame_sync_direction_shift, + direction << + dam_transmit_frame_sync_direction_shift, + _reg_DAM_HPCR(port)); + } + return; +} + +/*! + * This function controls Transmit Frame Sync signal source for the port. + * + * @param p_config the DAM port to configure + * @param from_RxFS the signal comes from RxFS or TxFS of + * the source port + * @param p_source the source port + */ +void dam_select_TxFS_source(dam_port p_config, + bool from_RxFS, dam_port p_source) +{ + if (p_config < 3) { + ModifyRegister32(dam_fs_selection_mask << + dam_transmit_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_transmit_frame_sync_select_shift, + _reg_DAM_HPCR(p_config)); + } else { + ModifyRegister32(dam_fs_selection_mask << + dam_transmit_frame_sync_select_shift, + ((from_RxFS << 3) | p_source) << + dam_transmit_frame_sync_select_shift, + _reg_DAM_PPCR(p_config)); + } + return; +} + +/*! + * This function sets a bit mask that selects the port from which of the RxD + * signals are to be ANDed together for internal network mode. + * Bit 6 represents RxD from Port7 and bit0 represents RxD from Port1. + * 1 excludes RxDn from ANDing. 0 includes RxDn for ANDing. + * + * @param port the DAM port to configure + * @param bit_mask the bit mask + * + * @return This function returns the result of the operation + * (0 if successful, -1 otherwise). + */ +int dam_set_internal_network_mode_mask(dam_port port, unsigned char bit_mask) +{ + int result; + result = 0; + + ModifyRegister32(dam_internal_network_mode_mask << + dam_internal_network_mode_shift, + bit_mask << dam_internal_network_mode_shift, + _reg_DAM_HPCR(port)); + return result; +} + +/*! + * This function controls whether or not the port is in synchronous mode. + * When the synchronous mode is selected, the receive and the transmit sections + * use common clock and frame sync signals. + * When the synchronous mode is not selected, separate clock and frame sync + * signals are used for the transmit and the receive sections. + * The defaut value is the synchronous mode selected. + * + * @param port the DAM port to configure + * @param synchronous the state to assign + */ +void dam_set_synchronous(dam_port port, bool synchronous) +{ + if (port < 3) { + ModifyRegister32(1 << dam_synchronous_mode_shift, + synchronous << dam_synchronous_mode_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_synchronous_mode_shift, + synchronous << dam_synchronous_mode_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function swaps the transmit and receive signals from (Da-TxD, Db-RxD) + * to (Da-RxD, Db-TxD). + * This default signal configuration is Da-TxD, Db-RxD. + * + * @param port the DAM port to configure + * @param value the switch state + */ +void dam_switch_Tx_Rx(dam_port port, bool value) +{ + if (port < 3) { + ModifyRegister32(1 << dam_transmit_receive_switch_shift, + value << dam_transmit_receive_switch_shift, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(1 << dam_transmit_receive_switch_shift, + value << dam_transmit_receive_switch_shift, + _reg_DAM_PPCR(port)); + } + return; +} + +/*! + * This function resets the two registers of the selected port. + * + * @param port the DAM port to reset + */ +void dam_reset_register(dam_port port) +{ + if (port < 3) { + ModifyRegister32(0xFFFFFFFF, dam_hpcr_default_value, + _reg_DAM_HPCR(port)); + } else { + ModifyRegister32(0xFFFFFFFF, dam_ppcr_default_value, + _reg_DAM_PPCR(port)); + } + return; +} + +#ifdef TEST_DAM + +/*! + * This function implements IOCTL controls on a DAM device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter :\n + * DAM_CONFIG_SSI1:\n + * data from port 1 to port 4, clock and FS from port 1 (SSI1)\n + * DAM_CONFIG_SSI2:\n + * data from port 2 to port 5, clock and FS from port 2 (SSI2)\n + * DAM_CONFIG_SSI_NETWORK_MODE:\n + * network mode for mix digital with data from port 1 to port4,\n + * data from port 2 to port 4, clock and FS from port 1 (SSI1) + * + * @return This function returns 0 if successful. + */ +static int dam_ioctl(struct inode *inode, + struct file *file, unsigned int cmd, unsigned long arg) +{ + return 0; +} + +/*! + * This function implements the open method on a DAM device. + * + * @param inode pointer on the node + * @param file pointer on the file + * + * @return This function returns 0. + */ +static int dam_open(struct inode *inode, struct file *file) +{ + /* DBG_PRINTK("ssi : dam_open()\n"); */ + return 0; +} + +/*! + * This function implements the release method on a DAM device. + * + * @param inode pointer on the node + * @param file pointer on the file + * + * @return This function returns 0. + */ +static int dam_free(struct inode *inode, struct file *file) +{ + /* DBG_PRINTK("ssi : dam_free()\n"); */ + return 0; +} + +/*! + * This structure defines file operations for a DAM device. + */ +static struct file_operations dam_fops = { + + /*! + * the owner + */ + .owner = THIS_MODULE, + + /*! + * the ioctl operation + */ + .ioctl = dam_ioctl, + + /*! + * the open operation + */ + .open = dam_open, + + /*! + * the release operation + */ + .release = dam_free, +}; + +#endif + +/*! + * This function implements the init function of the DAM device. + * This function is called when the module is loaded. + * + * @return This function returns 0. + */ +static int __init dam_init(void) +{ +#ifdef TEST_DAM + struct device *temp_class; + printk(KERN_DEBUG "dam : dam_init(void) \n"); + + major_dam = register_chrdev(0, DAM_NAME, &dam_fops); + if (major_dam < 0) { + printk(KERN_WARNING "Unable to get a major for dam"); + return major_dam; + } + + mxc_dam_class = class_create(THIS_MODULE, DAM_NAME); + if (IS_ERR(mxc_dam_class)) { + goto err_out; + } + + temp_class = device_create(mxc_dam_class, NULL, + MKDEV(major_dam, 0), NULL, DAM_NAME); + if (IS_ERR(temp_class)) { + goto err_out; + } +#endif + return 0; + + err_out: + printk(KERN_ERR "Error creating dam class device.\n"); + device_destroy(mxc_dam_class, MKDEV(major_dam, 0)); + class_destroy(mxc_dam_class); + unregister_chrdev(major_dam, DAM_NAME); + return -1; +} + +/*! + * This function implements the exit function of the SPI device. + * This function is called when the module is unloaded. + * + */ +static void __exit dam_exit(void) +{ +#ifdef TEST_DAM + device_destroy(mxc_dam_class, MKDEV(major_dam, 0)); + class_destroy(mxc_dam_class); + unregister_chrdev(major_dam, DAM_NAME); + printk(KERN_DEBUG "dam : successfully unloaded\n"); +#endif +} + +module_init(dam_init); +module_exit(dam_exit); + +MODULE_DESCRIPTION("DAM char device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/gps_ioctrl/Kconfig b/drivers/mxc/gps_ioctrl/Kconfig new file mode 100644 index 000000000000..0a85d1636dd7 --- /dev/null +++ b/drivers/mxc/gps_ioctrl/Kconfig @@ -0,0 +1,13 @@ +# +# BROADCOM GPS configuration +# + +menu "Broadcom GPS ioctrl support" + +config GPS_IOCTRL + tristate "GPS ioctrl support" + depends on MACH_MX31_3DS || MACH_MX35_3DS || MACH_MX37_3DS || MACH_MX51_3DS + ---help--- + Say Y to enable Broadcom GPS ioctrl on MXC platform. + +endmenu diff --git a/drivers/mxc/gps_ioctrl/Makefile b/drivers/mxc/gps_ioctrl/Makefile new file mode 100644 index 000000000000..c52d7c9f151c --- /dev/null +++ b/drivers/mxc/gps_ioctrl/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the GPIO device driver module. +# +obj-$(CONFIG_GPS_IOCTRL) += gps_gpiodrv.o +gps_gpiodrv-objs := agpsgpiodev.o diff --git a/drivers/mxc/gps_ioctrl/agpsgpiodev.c b/drivers/mxc/gps_ioctrl/agpsgpiodev.c new file mode 100644 index 000000000000..9b2afef24075 --- /dev/null +++ b/drivers/mxc/gps_ioctrl/agpsgpiodev.c @@ -0,0 +1,332 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file agpsgpiodev.c + * + * @brief Main file for GPIO kernel module. Contains driver entry/exit + * + */ + +#include +#include /* Async notification */ +#include /* for get_user, put_user, access_ok */ +#include /* jiffies */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "agpsgpiodev.h" + +extern void gpio_gps_active(void); +extern void gpio_gps_inactive(void); +extern int gpio_gps_access(int para); + +struct mxc_gps_platform_data *mxc_gps_ioctrl_data; +static int Device_Open; /* Only allow a single user of this device */ +static struct cdev mxc_gps_cdev; +static dev_t agps_gpio_dev; +static struct class *gps_class; +static struct device *gps_class_dev; + +/* Write GPIO from user space */ +static int ioctl_writegpio(int arg) +{ + + /* Bit 0 of arg identifies the GPIO pin to write: + 0 = GPS_RESET_GPIO, 1 = GPS_POWER_GPIO. + Bit 1 of arg identifies the value to write (0 or 1). */ + + /* Bit 2 should be 0 to show this access is write */ + return gpio_gps_access(arg & (~0x4)); +} + +/* Read GPIO from user space */ +static int ioctl_readgpio(int arg) +{ + /* Bit 0 of arg identifies the GPIO pin to read: + 0 = GPS_RESET_GPIO. 1 = GPS_POWER_GPIO + Bit 2 should be 1 to show this access is read */ + return gpio_gps_access(arg | 0x4); +} + +static int device_open(struct inode *inode, struct file *fp) +{ + /* We don't want to talk to two processes at the same time. */ + if (Device_Open) { + printk(KERN_DEBUG "device_open() - Returning EBUSY. \ + Device already open... \n"); + return -EBUSY; + } + Device_Open++; /* BUGBUG : Not protected! */ + try_module_get(THIS_MODULE); + + return 0; +} + +static int device_release(struct inode *inode, struct file *fp) +{ + /* We're now ready for our next caller */ + Device_Open--; + module_put(THIS_MODULE); + + return 0; +} + +static int device_ioctl(struct inode *inode, struct file *fp, + unsigned int cmd, unsigned long arg) +{ + int err = 0; + + /* Extract the type and number bitfields, and don't decode wrong cmds. + Return ENOTTY (inappropriate ioctl) before access_ok() */ + if (_IOC_TYPE(cmd) != MAJOR_NUM) { + printk(KERN_ERR + "device_ioctl() - Error! IOC_TYPE = %d. Expected %d\n", + _IOC_TYPE(cmd), MAJOR_NUM); + return -ENOTTY; + } + if (_IOC_NR(cmd) > IOCTL_MAXNUMBER) { + printk(KERN_ERR + "device_ioctl() - Error!" + "IOC_NR = %d greater than max supported(%d)\n", + _IOC_NR(cmd), IOCTL_MAXNUMBER); + return -ENOTTY; + } + + /* The direction is a bitmask, and VERIFY_WRITE catches R/W transfers. + `Type' is user-oriented, while access_ok is kernel-oriented, so the + concept of "read" and "write" is reversed. I think this is primarily + for good coding practice. You can easily do any kind of R/W access + without these checks and IOCTL code can be implemented "randomly"! */ + if (_IOC_DIR(cmd) & _IOC_READ) + err = + !access_ok(VERIFY_WRITE, (void __user *)arg, + _IOC_SIZE(cmd)); + + else if (_IOC_DIR(cmd) & _IOC_WRITE) + err = + !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); + if (err) { + printk(KERN_ERR + "device_ioctl() - Error! User arg not valid" + "for selected access (R/W/RW). Cmd %d\n", + _IOC_TYPE(cmd)); + return -EFAULT; + } + + /* Note: Read and writing data to user buffer can be done using regular + pointer stuff but we may also use get_user() or put_user() */ + + /* Cmd and arg has been verified... */ + switch (cmd) { + case IOCTL_WRITEGPIO: + return ioctl_writegpio((int)arg); + case IOCTL_READGPIO: + return ioctl_readgpio((int)arg); + default: + printk(KERN_ERR "device_ioctl() - Invalid IOCTL (0x%x)\n", cmd); + return EINVAL; + } + return 0; +} + +struct file_operations Fops = { + .ioctl = device_ioctl, + .open = device_open, + .release = device_release, +}; + +/* Initialize the module - Register the character device */ +int init_chrdev(struct device *dev) +{ + int ret, gps_major; + + ret = alloc_chrdev_region(&agps_gpio_dev, 1, 1, "agps_gpio"); + gps_major = MAJOR(agps_gpio_dev); + if (ret < 0) { + dev_err(dev, "can't get major %d\n", gps_major); + goto err3; + } + + cdev_init(&mxc_gps_cdev, &Fops); + mxc_gps_cdev.owner = THIS_MODULE; + + ret = cdev_add(&mxc_gps_cdev, agps_gpio_dev, 1); + if (ret) { + dev_err(dev, "can't add cdev\n"); + goto err2; + } + + /* create class and device for udev information */ + gps_class = class_create(THIS_MODULE, "gps"); + if (IS_ERR(gps_class)) { + dev_err(dev, "failed to create gps class\n"); + ret = -ENOMEM; + goto err1; + } + + gps_class_dev = device_create(gps_class, NULL, MKDEV(gps_major, 1), NULL, + AGPSGPIO_DEVICE_FILE_NAME); + if (IS_ERR(gps_class_dev)) { + dev_err(dev, "failed to create gps gpio class device\n"); + ret = -ENOMEM; + goto err0; + } + + return 0; +err0: + class_destroy(gps_class); +err1: + cdev_del(&mxc_gps_cdev); +err2: + unregister_chrdev_region(agps_gpio_dev, 1); +err3: + return ret; +} + +/* Cleanup - unregister the appropriate file from /proc. */ +void cleanup_chrdev(void) +{ + /* destroy gps device class */ + device_destroy(gps_class, MKDEV(MAJOR(agps_gpio_dev), 1)); + class_destroy(gps_class); + + /* Unregister the device */ + cdev_del(&mxc_gps_cdev); + unregister_chrdev_region(agps_gpio_dev, 1); +} + +/*! + * This function initializes the driver in terms of memory of the soundcard + * and some basic HW clock settings. + * + * @return 0 on success, -1 otherwise. + */ +static int __init gps_ioctrl_probe(struct platform_device *pdev) +{ + struct regulator *gps_regu; + + mxc_gps_ioctrl_data = + (struct mxc_gps_platform_data *)pdev->dev.platform_data; + + /* open GPS GPO3 1v8 for GL gps support */ + if (mxc_gps_ioctrl_data->core_reg != NULL) { + mxc_gps_ioctrl_data->gps_regu_core = + regulator_get(&(pdev->dev), mxc_gps_ioctrl_data->core_reg); + gps_regu = mxc_gps_ioctrl_data->gps_regu_core; + if (!IS_ERR_VALUE((u32)gps_regu)) { + regulator_set_voltage(gps_regu, 1800000, 1800000); + regulator_enable(gps_regu); + } else { + return -1; + } + } + /* open GPS GPO1 2v8 for GL gps support */ + if (mxc_gps_ioctrl_data->analog_reg != NULL) { + mxc_gps_ioctrl_data->gps_regu_analog = + regulator_get(&(pdev->dev), + mxc_gps_ioctrl_data->analog_reg); + gps_regu = mxc_gps_ioctrl_data->gps_regu_analog; + if (!IS_ERR_VALUE((u32)gps_regu)) { + regulator_set_voltage(gps_regu, 2800000, 2800000); + regulator_enable(gps_regu); + } else { + return -1; + } + } + gpio_gps_active(); + + /* Register character device */ + init_chrdev(&(pdev->dev)); + return 0; +} + +static int gps_ioctrl_remove(struct platform_device *pdev) +{ + struct regulator *gps_regu; + + mxc_gps_ioctrl_data = + (struct mxc_gps_platform_data *)pdev->dev.platform_data; + + /* Character device cleanup.. */ + cleanup_chrdev(); + gpio_gps_inactive(); + + /* close GPS GPO3 1v8 for GL gps */ + gps_regu = mxc_gps_ioctrl_data->gps_regu_core; + if (mxc_gps_ioctrl_data->core_reg != NULL) { + regulator_disable(gps_regu); + regulator_put(gps_regu); + } + /* close GPS GPO1 2v8 for GL gps */ + gps_regu = mxc_gps_ioctrl_data->gps_regu_analog; + if (mxc_gps_ioctrl_data->analog_reg != NULL) { + regulator_disable(gps_regu); + regulator_put(gps_regu); + } + + return 0; +} + +static int gps_ioctrl_suspend(struct platform_device *pdev, pm_message_t state) +{ + /* PowerEn toggle off */ + ioctl_writegpio(0x1); + return 0; +} + +static int gps_ioctrl_resume(struct platform_device *pdev) +{ + /* PowerEn pull up */ + ioctl_writegpio(0x3); + return 0; +} + +static struct platform_driver gps_ioctrl_driver = { + .probe = gps_ioctrl_probe, + .remove = gps_ioctrl_remove, + .suspend = gps_ioctrl_suspend, + .resume = gps_ioctrl_resume, + .driver = { + .name = "gps_ioctrl", + }, +}; + +/*! + * Entry point for GPS ioctrl module. + * + */ +static int __init gps_ioctrl_init(void) +{ + return platform_driver_register(&gps_ioctrl_driver); +} + +/*! + * unloading module. + * + */ +static void __exit gps_ioctrl_exit(void) +{ + platform_driver_unregister(&gps_ioctrl_driver); +} + +module_init(gps_ioctrl_init); +module_exit(gps_ioctrl_exit); +MODULE_DESCRIPTION("GPIO DEVICE DRIVER"); +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/gps_ioctrl/agpsgpiodev.h b/drivers/mxc/gps_ioctrl/agpsgpiodev.h new file mode 100644 index 000000000000..099608785b1b --- /dev/null +++ b/drivers/mxc/gps_ioctrl/agpsgpiodev.h @@ -0,0 +1,46 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file agpsgpiodev.h + * + * @brief head file of Simple character device interface for AGPS kernel module. + * + * @ingroup + */ + +#ifndef AGPSGPIODEV_H +#define AGPSGPIODEV_H + +#include + +#define USE_BLOCKING /* Test driver with blocking calls */ +#undef USE_FASYNC /* Test driver with async notification */ + +/* The major device number. We can't rely on dynamic registration any more + because ioctls need to know it */ +#define MAJOR_NUM 100 + +#define IOCTL_WRITEGPIO _IOWR(MAJOR_NUM, 1, char *) +#define IOCTL_READGPIO _IOR(MAJOR_NUM, 2, char *) +#define IOCTL_MAXNUMBER 2 + +/* The name of the device file */ +#define AGPSGPIO_DEVICE_FILE_NAME "agpsgpio" + +/* Exported prototypes */ +int init_chrdev(struct device *dev); +void cleanup_chrdev(void); +void wakeup(void); + +#endif diff --git a/drivers/mxc/hmp4e/Kconfig b/drivers/mxc/hmp4e/Kconfig new file mode 100644 index 000000000000..fdd7dbc041ba --- /dev/null +++ b/drivers/mxc/hmp4e/Kconfig @@ -0,0 +1,24 @@ +# +# MPEG4 Encoder kernel module configuration +# + +menu "MXC MPEG4 Encoder Kernel module support" + +config MXC_HMP4E + tristate "MPEG4 Encoder support" + depends on ARCH_MXC + depends on !ARCH_MX27 + default y + ---help--- + Say Y to get the MPEG4 Encoder kernel module available on + MXC platform. + +config MXC_HMP4E_DEBUG + bool "MXC MPEG4 Debug messages" + depends on MXC_HMP4E != n + default n + ---help--- + Say Y here if you need the Encoder driver to print debug messages. + This is an option for developers, most people should say N here. + +endmenu diff --git a/drivers/mxc/hmp4e/Makefile b/drivers/mxc/hmp4e/Makefile new file mode 100644 index 000000000000..3f69ec842af7 --- /dev/null +++ b/drivers/mxc/hmp4e/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the MPEG4 Encoder kernel module. + +obj-$(CONFIG_MXC_HMP4E) += mxc_hmp4e.o +CFLAGS_mxc_hmp4e.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS + +ifeq ($(CONFIG_MXC_HMP4E_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif diff --git a/drivers/mxc/hmp4e/mxc_hmp4e.c b/drivers/mxc/hmp4e/mxc_hmp4e.c new file mode 100644 index 000000000000..aebaf445b4de --- /dev/null +++ b/drivers/mxc/hmp4e/mxc_hmp4e.c @@ -0,0 +1,812 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Encoder device driver (kernel module) + * + * Copyright (C) 2005 Hantro Products Oy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include +#include +#include /* __init,__exit directives */ +#include /* remap_page_range / remap_pfn_range */ +#include /* for struct file_operations */ +#include /* standard error codes */ +#include /* for device registeration for PM */ +#include /* for msleep_interruptible */ +#include +#include /* for dma_alloc_consistent */ +#include +#include /* for ioctl __get_user, __put_user */ +#include +#include "mxc_hmp4e.h" /* MPEG4 encoder specific */ + +/* here's all the must remember stuff */ +typedef struct { + ulong buffaddr; + u32 buffsize; + ulong iobaseaddr; + u32 iosize; + volatile u32 *hwregs; + u32 irq; + u16 hwid_offset; + u16 intr_offset; + u16 busy_offset; + u16 type; /* Encoder type, CIF = 0, VGA = 1 */ + u16 clk_gate; + u16 busy_val; + struct fasync_struct *async_queue; +#ifdef CONFIG_PM + s32 suspend_state; + wait_queue_head_t power_queue; +#endif +} hmp4e_t; + +/* and this is our MAJOR; use 0 for dynamic allocation (recommended)*/ +static s32 hmp4e_major; + +static u32 hmp4e_phys; +static struct class *hmp4e_class; +static hmp4e_t hmp4e_data; + +/*! MPEG4 enc clock handle. */ +static struct clk *hmp4e_clk; + +/* + * avoid "enable_irq(x) unbalanced from ..." + * error messages from the kernel, since {ena,dis}able_irq() + * calls are stacked in kernel. + */ +static bool irq_enable; + +ulong base_port = MPEG4_ENC_BASE_ADDR; +u32 irq = MXC_INT_MPEG4_ENCODER; + +module_param(base_port, long, 000); +module_param(irq, int, 000); + +/*! + * These variables store the register values when HMP4E is in suspend mode. + */ +#ifdef CONFIG_PM +u32 io_regs[64]; +#endif + +static s32 hmp4e_map_buffer(struct file *filp, struct vm_area_struct *vma); +static s32 hmp4e_map_hwregs(struct file *filp, struct vm_area_struct *vma); +static void hmp4e_reset(hmp4e_t *dev); +irqreturn_t hmp4e_isr(s32 irq, void *dev_id); + +/*! + * This funtion is called to write h/w register. + * + * @param val value to be written into the register + * @param offset register offset + * + */ +static inline void hmp4e_write(u32 val, u32 offset) +{ + hmp4e_t *dev = &hmp4e_data; + __raw_writel(val, (dev->hwregs + offset)); +} + +/*! + * This funtion is called to read h/w register. + * + * @param offset register offset + * + * @return This function returns the value read from the register. + * + */ +static inline u32 hmp4e_read(u32 offset) +{ + hmp4e_t *dev = &hmp4e_data; + u32 val; + + val = __raw_readl(dev->hwregs + offset); + + return val; +} + +/*! + * The device's mmap method. The VFS has kindly prepared the process's + * vm_area_struct for us, so we examine this to see what was requested. + * + * @param filp pointer to struct file + * @param vma pointer to struct vma_area_struct + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_mmap(struct file *filp, struct vm_area_struct *vma) +{ + s32 result; + ulong offset = vma->vm_pgoff << PAGE_SHIFT; + + pr_debug("hmp4e_mmap: size = %lu off = 0x%08lx\n", + (unsigned long)(vma->vm_end - vma->vm_start), offset); + + if (offset == 0) { + result = hmp4e_map_buffer(filp, vma); + } else if (offset == hmp4e_data.iobaseaddr) { + result = hmp4e_map_hwregs(filp, vma); + } else { + pr_debug("hmp4e: mmap invalid value\n"); + result = -EINVAL; + } + + return result; +} + +/*! + * This funtion is called to handle ioctls. + * + * @param inode pointer to struct inode + * @param filp pointer to struct file + * @param cmd ioctl command + * @param arg user data + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_ioctl(struct inode *inode, struct file *filp, + u32 cmd, ulong arg) +{ + s32 err = 0, retval = 0; + ulong offset = 0; + hmp4e_t *dev = &hmp4e_data; + write_t bwrite; + +#ifdef CONFIG_PM + wait_event_interruptible(hmp4e_data.power_queue, + hmp4e_data.suspend_state == 0); +#endif + + /* + * extract the type and number bitfields, and don't decode + * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() + */ + if (_IOC_TYPE(cmd) != HMP4E_IOC_MAGIC) { + pr_debug("hmp4e: ioctl invalid magic\n"); + return -ENOTTY; + } + + if (_IOC_NR(cmd) > HMP4E_IOC_MAXNR) { + pr_debug("hmp4e: ioctl exceeds max ioctl\n"); + return -ENOTTY; + } + + /* + * the direction is a bitmask, and VERIFY_WRITE catches R/W + * transfers. `Type' is user-oriented, while + * access_ok is kernel-oriented, so the concept of "read" and + * "write" is reversed + */ + if (_IOC_DIR(cmd) & _IOC_READ) { + err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd)); + } else if (_IOC_DIR(cmd) & _IOC_WRITE) { + err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd)); + } + + if (err) { + pr_debug("hmp4e: ioctl invalid direction\n"); + return -EFAULT; + } + + switch (cmd) { + case HMP4E_IOCHARDRESET: + break; + + case HMP4E_IOCGBUFBUSADDRESS: + retval = __put_user((ulong) hmp4e_phys, (u32 *) arg); + break; + + case HMP4E_IOCGBUFSIZE: + retval = __put_user(hmp4e_data.buffsize, (u32 *) arg); + break; + + case HMP4E_IOCSREGWRITE: + if (dev->type != 1) { /* This ioctl only for VGA */ + pr_debug("hmp4e: HMP4E_IOCSREGWRITE invalid\n"); + retval = -EINVAL; + break; + } + + retval = __copy_from_user(&bwrite, (u32 *) arg, + sizeof(write_t)); + + if (bwrite.offset <= hmp4e_data.iosize - 4) { + hmp4e_write(bwrite.data, (bwrite.offset / 4)); + } else { + pr_debug("hmp4e: HMP4E_IOCSREGWRITE failed\n"); + retval = -EFAULT; + } + break; + + case HMP4E_IOCXREGREAD: + if (dev->type != 1) { /* This ioctl only for VGA */ + pr_debug("hmp4e: HMP4E_IOCSREGWRITE invalid\n"); + retval = -EINVAL; + break; + } + + retval = __get_user(offset, (ulong *) arg); + if (offset <= hmp4e_data.iosize - 4) { + __put_user(hmp4e_read((offset / 4)), (ulong *) arg); + } else { + pr_debug("hmp4e: HMP4E_IOCXREGREAD failed\n"); + retval = -EFAULT; + } + break; + + case HMP4E_IOCGHWOFFSET: + __put_user(hmp4e_data.iobaseaddr, (ulong *) arg); + break; + + case HMP4E_IOCGHWIOSIZE: + __put_user(hmp4e_data.iosize, (u32 *) arg); + break; + + case HMP4E_IOC_CLI: + if (irq_enable == true) { + disable_irq(hmp4e_data.irq); + irq_enable = false; + } + break; + + case HMP4E_IOC_STI: + if (irq_enable == false) { + enable_irq(hmp4e_data.irq); + irq_enable = true; + } + break; + + default: + pr_debug("unknown case %x\n", cmd); + } + + return retval; +} + +/*! + * This funtion is called when the device is opened. + * + * @param inode pointer to struct inode + * @param filp pointer to struct file + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_open(struct inode *inode, struct file *filp) +{ + hmp4e_t *dev = &hmp4e_data; + + filp->private_data = (void *)dev; + + if (request_irq(dev->irq, hmp4e_isr, 0, "mxc_hmp4e", dev) != 0) { + pr_debug("hmp4e: request irq failed\n"); + return -EBUSY; + } + + if (irq_enable == false) { + irq_enable = true; + } + clk_enable(hmp4e_clk); + return 0; +} + +static s32 hmp4e_fasync(s32 fd, struct file *filp, s32 mode) +{ + hmp4e_t *dev = (hmp4e_t *) filp->private_data; + return fasync_helper(fd, filp, mode, &dev->async_queue); +} + +/*! + * This funtion is called when the device is closed. + * + * @param inode pointer to struct inode + * @param filp pointer to struct file + * + * @return This function returns 0. + * + */ +static s32 hmp4e_release(struct inode *inode, struct file *filp) +{ + hmp4e_t *dev = (hmp4e_t *) filp->private_data; + + /* this is necessary if user process exited asynchronously */ + if (irq_enable == true) { + disable_irq(dev->irq); + irq_enable = false; + } + + /* reset hardware */ + hmp4e_reset(&hmp4e_data); + + /* free the encoder IRQ */ + free_irq(dev->irq, (void *)dev); + + /* remove this filp from the asynchronusly notified filp's */ + hmp4e_fasync(-1, filp, 0); + clk_disable(hmp4e_clk); + return 0; +} + +/* VFS methods */ +static struct file_operations hmp4e_fops = { + .owner = THIS_MODULE, + .open = hmp4e_open, + .release = hmp4e_release, + .ioctl = hmp4e_ioctl, + .mmap = hmp4e_mmap, + .fasync = hmp4e_fasync, +}; + +/*! + * This funtion allocates physical contigous memory. + * + * @param size size of memory to be allocated + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_alloc(u32 size) +{ + hmp4e_data.buffsize = PAGE_ALIGN(size); + hmp4e_data.buffaddr = + (ulong) dma_alloc_coherent(NULL, hmp4e_data.buffsize, + (dma_addr_t *) &hmp4e_phys, + GFP_DMA | GFP_KERNEL); + + if (hmp4e_data.buffaddr == 0) { + printk(KERN_ERR "hmp4e: couldn't allocate data buffer\n"); + return -ENOMEM; + } + + memset((s8 *) hmp4e_data.buffaddr, 0, hmp4e_data.buffsize); + return 0; +} + +/*! + * This funtion frees the DMAed memory. + */ +static void hmp4e_free(void) +{ + if (hmp4e_data.buffaddr != 0) { + dma_free_coherent(NULL, hmp4e_data.buffsize, + (void *)hmp4e_data.buffaddr, hmp4e_phys); + hmp4e_data.buffaddr = 0; + } +} + +/*! + * This funtion maps the shared buffer in memory. + * + * @param filp pointer to struct file + * @param vma pointer to struct vm_area_struct + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_map_buffer(struct file *filp, struct vm_area_struct *vma) +{ + ulong phys; + ulong start = (u32) vma->vm_start; + ulong size = (u32) (vma->vm_end - vma->vm_start); + + /* if userspace tries to mmap beyond end of our buffer, fail */ + if (size > hmp4e_data.buffsize) { + pr_debug("hmp4e: hmp4e_map_buffer, invalid size\n"); + return -EINVAL; + } + + vma->vm_flags |= VM_RESERVED | VM_IO; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + phys = hmp4e_phys; + + if (remap_pfn_range(vma, start, phys >> PAGE_SHIFT, size, + vma->vm_page_prot)) { + pr_debug("hmp4e: failed mmapping shared buffer\n"); + return -EAGAIN; + } + + return 0; +} + +/*! + * This funtion maps the h/w register space in memory. + * + * @param filp pointer to struct file + * @param vma pointer to struct vm_area_struct + * + * @return This function returns 0 if successful or -ve value on error. + * + */ +static s32 hmp4e_map_hwregs(struct file *filp, struct vm_area_struct *vma) +{ + ulong phys; + ulong start = (unsigned long)vma->vm_start; + ulong size = (unsigned long)(vma->vm_end - vma->vm_start); + + /* if userspace tries to mmap beyond end of our buffer, fail */ + if (size > PAGE_SIZE) { + pr_debug("hmp4e: hmp4e_map_hwregs, invalid size\n"); + return -EINVAL; + } + + vma->vm_flags |= VM_RESERVED | VM_IO; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Remember this won't work for vmalloc()d memory ! */ + phys = hmp4e_data.iobaseaddr; + + if (remap_pfn_range(vma, start, phys >> PAGE_SHIFT, hmp4e_data.iosize, + vma->vm_page_prot)) { + pr_debug("hmp4e: failed mmapping HW registers\n"); + return -EAGAIN; + } + + return 0; +} + +/*! + * This function is the interrupt service routine. + * + * @param irq the irq number + * @param dev_id driver data when ISR was regiatered + * + * @return The return value is IRQ_HANDLED. + * + */ +irqreturn_t hmp4e_isr(s32 irq, void *dev_id) +{ + hmp4e_t *dev = (hmp4e_t *) dev_id; + u32 offset = dev->intr_offset; + + u32 irq_status = hmp4e_read(offset); + + /* clear enc IRQ */ + hmp4e_write(irq_status & (~0x01), offset); + + if (dev->async_queue) + kill_fasync(&dev->async_queue, SIGIO, POLL_IN); + + return IRQ_HANDLED; +} + +/*! + * This function is called to reset the encoder. + * + * @param dev pointer to struct hmp4e_data + * + */ +static void hmp4e_reset(hmp4e_t *dev) +{ + s32 i; + + /* enable HCLK for register reset */ + hmp4e_write(dev->clk_gate, 0); + + /* Reset registers, except ECR0 (0x00) and ID (read-only) */ + for (i = 1; i < (dev->iosize / 4); i += 1) { + if (i == dev->hwid_offset) /* ID is read only */ + continue; + + /* Only for CIF, not used */ + if ((dev->type == 0) && (i == 14)) + continue; + + hmp4e_write(0, i); + } + + /* disable HCLK */ + hmp4e_write(0, 0); + return; +} + +/*! + * This function is called during the driver binding process. This function + * does the hardware initialization. + * + * @param dev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function returns 0 if successful. + */ +static s32 hmp4e_probe(struct platform_device *pdev) +{ + s32 result; + u32 hwid; + struct device *temp_class; + + hmp4e_data.iobaseaddr = base_port; + hmp4e_data.irq = irq; + hmp4e_data.buffaddr = 0; + + /* map hw i/o registers into kernel space */ + hmp4e_data.hwregs = (volatile void *)IO_ADDRESS(hmp4e_data.iobaseaddr); + + hmp4e_clk = clk_get(&pdev->dev, "mpeg4_clk"); + if (IS_ERR(hmp4e_clk)) { + printk(KERN_INFO "hmp4e: Unable to get clock\n"); + return -EIO; + } + + clk_enable(hmp4e_clk); + + /* check hw id for encoder signature */ + hwid = hmp4e_read(7); + if ((hwid & 0xffff) == 0x1882) { /* CIF first */ + hmp4e_data.type = 0; + hmp4e_data.iosize = (16 * 4); + hmp4e_data.hwid_offset = 7; + hmp4e_data.intr_offset = 5; + hmp4e_data.clk_gate = (1 << 1); + hmp4e_data.buffsize = 512000; + hmp4e_data.busy_offset = 0; + hmp4e_data.busy_val = 1; + } else { + hwid = hmp4e_read((0x88 / 4)); + if ((hwid & 0xffff0000) == 0x52510000) { /* VGA */ + hmp4e_data.type = 1; + hmp4e_data.iosize = (35 * 4); + hmp4e_data.hwid_offset = (0x88 / 4); + hmp4e_data.intr_offset = (0x10 / 4); + hmp4e_data.clk_gate = (1 << 12); + hmp4e_data.buffsize = 1048576; + hmp4e_data.busy_offset = (0x10 / 4); + hmp4e_data.busy_val = (1 << 1); + } else { + printk(KERN_INFO "hmp4e: HW ID not found\n"); + goto error1; + } + } + + /* Reset hardware */ + hmp4e_reset(&hmp4e_data); + + /* allocate memory shared with ewl */ + result = hmp4e_alloc(hmp4e_data.buffsize); + if (result < 0) + goto error1; + + result = register_chrdev(hmp4e_major, "hmp4e", &hmp4e_fops); + if (result <= 0) { + pr_debug("hmp4e: unable to get major %d\n", hmp4e_major); + goto error2; + } + + hmp4e_major = result; + + hmp4e_class = class_create(THIS_MODULE, "hmp4e"); + if (IS_ERR(hmp4e_class)) { + pr_debug("Error creating hmp4e class.\n"); + goto error3; + } + + temp_class = device_create(hmp4e_class, NULL, MKDEV(hmp4e_major, 0), NULL, + "hmp4e"); + if (IS_ERR(temp_class)) { + pr_debug("Error creating hmp4e class device.\n"); + goto error4; + } + + platform_set_drvdata(pdev, &hmp4e_data); + +#ifdef CONFIG_PM + hmp4e_data.async_queue = NULL; + hmp4e_data.suspend_state = 0; + init_waitqueue_head(&hmp4e_data.power_queue); +#endif + + printk(KERN_INFO "hmp4e: %s encoder initialized\n", + hmp4e_data.type ? "VGA" : "CIF"); + clk_disable(hmp4e_clk); + return 0; + + error4: + class_destroy(hmp4e_class); + error3: + unregister_chrdev(hmp4e_major, "hmp4e"); + error2: + hmp4e_free(); + error1: + clk_disable(hmp4e_clk); + clk_put(hmp4e_clk); + printk(KERN_INFO "hmp4e: module not inserted\n"); + return -EIO; +} + +/*! + * Dissociates the driver. + * + * @param dev the device structure + * + * @return The function always returns 0. + */ +static s32 hmp4e_remove(struct platform_device *pdev) +{ + device_destroy(hmp4e_class, MKDEV(hmp4e_major, 0)); + class_destroy(hmp4e_class); + unregister_chrdev(hmp4e_major, "hmp4e"); + hmp4e_free(); + clk_disable(hmp4e_clk); + clk_put(hmp4e_clk); + platform_set_drvdata(pdev, NULL); + return 0; +} + +#ifdef CONFIG_PM +/*! + * This is the suspend of power management for the Hantro MPEG4 module + * + * @param dev the device + * @param state the state + * + * @return This function always returns 0. + */ +static s32 hmp4e_suspend(struct platform_device *pdev, pm_message_t state) +{ + s32 i; + hmp4e_t *pdata = &hmp4e_data; + + /* + * how many times msleep_interruptible will be called before + * giving up + */ + s32 timeout = 10; + + pr_debug("hmp4e: Suspend\n"); + hmp4e_data.suspend_state = 1; + + /* check if encoder is currently running */ + while ((hmp4e_read(pdata->busy_offset) & (pdata->busy_val)) && + --timeout) { + pr_debug("hmp4e: encoder is running, going to sleep\n"); + msleep_interruptible((unsigned int)30); + } + + if (!timeout) { + pr_debug("hmp4e: timeout suspending, resetting encoder\n"); + hmp4e_write(hmp4e_read(pdata->busy_offset) & + (~pdata->busy_val), pdata->busy_offset); + } + + /* first read register 0 */ + io_regs[0] = hmp4e_read(0); + + /* then override HCLK to make sure other registers can be read */ + hmp4e_write(pdata->clk_gate, 0); + + /* read other registers */ + for (i = 1; i < (pdata->iosize / 4); i += 1) { + + /* Only for CIF, not used */ + if ((pdata->type == 0) && (i == 14)) + continue; + + io_regs[i] = hmp4e_read(i); + } + + /* restore value of register 0 */ + hmp4e_write(io_regs[0], 0); + + /* stop HCLK */ + hmp4e_write(0, 0); + clk_disable(hmp4e_clk); + return 0; +}; + +/*! + * This is the resume of power management for the Hantro MPEG4 module + * It suports RESTORE state. + * + * @param pdev the platform device + * + * @return This function always returns 0 + */ +static s32 hmp4e_resume(struct platform_device *pdev) +{ + s32 i; + u32 status; + hmp4e_t *pdata = &hmp4e_data; + + pr_debug("hmp4e: Resume\n"); + clk_enable(hmp4e_clk); + + /* override HCLK to make sure registers can be written */ + hmp4e_write(pdata->clk_gate, 0x00); + + for (i = 1; i < (pdata->iosize / 4); i += 1) { + if (i == pdata->hwid_offset) /* Read only */ + continue; + + /* Only for CIF, not used */ + if ((pdata->type == 0) && (i == 14)) + continue; + + hmp4e_write(io_regs[i], i); + } + + /* write register 0 last */ + hmp4e_write(io_regs[0], 0x00); + + /* Clear the suspend flag */ + hmp4e_data.suspend_state = 0; + + /* Unblock the wait queue */ + wake_up_interruptible(&hmp4e_data.power_queue); + + /* Continue operations */ + status = hmp4e_read(pdata->intr_offset); + if (status & 0x1) { + hmp4e_write(status & (~0x01), pdata->intr_offset); + if (hmp4e_data.async_queue) + kill_fasync(&hmp4e_data.async_queue, SIGIO, POLL_IN); + } + + return 0; +}; + +#endif + +static struct platform_driver hmp4e_driver = { + .driver = { + .name = "mxc_hmp4e", + }, + .probe = hmp4e_probe, + .remove = hmp4e_remove, +#ifdef CONFIG_PM + .suspend = hmp4e_suspend, + .resume = hmp4e_resume, +#endif +}; + +static s32 __init hmp4e_init(void) +{ + printk(KERN_INFO "hmp4e: init\n"); + platform_driver_register(&hmp4e_driver); + return 0; +} + +static void __exit hmp4e_cleanup(void) +{ + platform_driver_unregister(&hmp4e_driver); + printk(KERN_INFO "hmp4e: module removed\n"); +} + +module_init(hmp4e_init); +module_exit(hmp4e_cleanup); + +/* module description */ +MODULE_AUTHOR("Hantro Products Oy"); +MODULE_DESCRIPTION("Device driver for Hantro's hardware based MPEG4 encoder"); +MODULE_SUPPORTED_DEVICE("5251/4251 MPEG4 Encoder"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/hmp4e/mxc_hmp4e.h b/drivers/mxc/hmp4e/mxc_hmp4e.h new file mode 100644 index 000000000000..ed882b09e167 --- /dev/null +++ b/drivers/mxc/hmp4e/mxc_hmp4e.h @@ -0,0 +1,70 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Encoder device driver (kernel module headers) + * + * Copyright (C) 2005 Hantro Products Oy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ +#ifndef _HMP4ENC_H_ +#define _HMP4ENC_H_ +#include /* needed for the _IOW etc stuff used later */ + +/* this is for writing data through ioctl to registers*/ +typedef struct { + unsigned long data; + unsigned long offset; +} write_t; + +/* + * Ioctl definitions + */ + +/* Use 'k' as magic number */ +#define HMP4E_IOC_MAGIC 'k' +/* + * S means "Set" through a ptr, + * T means "Tell" directly with the argument value + * G means "Get": reply by setting through a pointer + * Q means "Query": response is on the return value + * X means "eXchange": G and S atomically + * H means "sHift": T and Q atomically + */ +#define HMP4E_IOCGBUFBUSADDRESS _IOR(HMP4E_IOC_MAGIC, 1, unsigned long *) +#define HMP4E_IOCGBUFSIZE _IOR(HMP4E_IOC_MAGIC, 2, unsigned int *) +#define HMP4E_IOCGHWOFFSET _IOR(HMP4E_IOC_MAGIC, 3, unsigned long *) +#define HMP4E_IOCGHWIOSIZE _IOR(HMP4E_IOC_MAGIC, 4, unsigned int *) +#define HMP4E_IOC_CLI _IO(HMP4E_IOC_MAGIC, 5) +#define HMP4E_IOC_STI _IO(HMP4E_IOC_MAGIC, 6) +#define HMP4E_IOCHARDRESET _IO(HMP4E_IOC_MAGIC, 7) +#define HMP4E_IOCSREGWRITE _IOW(HMP4E_IOC_MAGIC, 8, write_t) +#define HMP4E_IOCXREGREAD _IOWR(HMP4E_IOC_MAGIC, 9, unsigned long) + +#define HMP4E_IOC_MAXNR 9 + +#endif /* !_HMP4ENC_H_ */ diff --git a/drivers/mxc/hw_event/Kconfig b/drivers/mxc/hw_event/Kconfig new file mode 100644 index 000000000000..bcf479689501 --- /dev/null +++ b/drivers/mxc/hw_event/Kconfig @@ -0,0 +1,11 @@ +menu "MXC HARDWARE EVENT" + +config MXC_HWEVENT + bool "MXC Hardware Event Handler" + default y + depends on ARCH_MXC + help + If you plan to use the Hardware Event Handler in the MXC, say + Y here. If unsure, select Y. + +endmenu diff --git a/drivers/mxc/hw_event/Makefile b/drivers/mxc/hw_event/Makefile new file mode 100644 index 000000000000..a53fe2b45e04 --- /dev/null +++ b/drivers/mxc/hw_event/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MXC_HWEVENT) += mxc_hw_event.o diff --git a/drivers/mxc/hw_event/mxc_hw_event.c b/drivers/mxc/hw_event/mxc_hw_event.c new file mode 100644 index 000000000000..655e4c821986 --- /dev/null +++ b/drivers/mxc/hw_event/mxc_hw_event.c @@ -0,0 +1,266 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * mxc_hw_event.c + * Collect the hardware events, send to user by netlink + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EVENT_POOL_SIZE 10 + +struct hw_event_elem { + struct mxc_hw_event event; + struct list_head list; +}; + +static struct sock *nl_event_sock; /* netlink socket */ +static struct list_head event_head; +static struct list_head free_head; +static struct hw_event_elem events_pool[EVENT_POOL_SIZE]; /* event pool */ +static DEFINE_SPINLOCK(list_lock); +static DECLARE_WAIT_QUEUE_HEAD(event_wq); +static unsigned int seq; /* send seq */ +static int initialized; +static struct task_struct *hwevent_kthread; + +/*! + * main HW event handler thread + */ +static int hw_event_thread(void *data) +{ + struct sk_buff *skb = NULL; + struct nlmsghdr *nlh = NULL; + unsigned int size; + struct hw_event_elem *event, *n; + LIST_HEAD(tmp_head); + DEFINE_WAIT(wait); + + while (1) { + + prepare_to_wait(&event_wq, &wait, TASK_INTERRUPTIBLE); + /* wait for event coming */ + if (!freezing(current) && !kthread_should_stop() && + list_empty(&event_head)) + schedule(); + finish_wait(&event_wq, &wait); + + try_to_freeze(); + + if (kthread_should_stop()) + break; + + /* fetch event from list */ + spin_lock_irq(&list_lock); + tmp_head = event_head; + tmp_head.prev->next = &tmp_head; + tmp_head.next->prev = &tmp_head; + /* clear the event list head */ + INIT_LIST_HEAD(&event_head); + spin_unlock_irq(&list_lock); + + list_for_each_entry_safe(event, n, &tmp_head, list) { + + size = NLMSG_SPACE(sizeof(struct mxc_hw_event)); + skb = alloc_skb(size, GFP_KERNEL); + if (!skb) { + /* if failed alloc skb, we drop this event */ + printk(KERN_WARNING + "mxc_hw_event: skb_alloc() failed\n"); + goto alloc_failure; + } + + /* put the netlink header struct to skb */ + nlh = + NLMSG_PUT(skb, 0, seq++, NLMSG_DONE, + size - sizeof(*nlh)); + + /* fill the netlink data */ + memcpy((struct mxc_hw_event *)NLMSG_DATA(nlh), + &event->event, sizeof(struct mxc_hw_event)); + + /* free the event node, set to unused */ + spin_lock_irq(&list_lock); + list_move(&event->list, &free_head); + spin_unlock_irq(&list_lock); + + /* send to all process that create this socket */ + NETLINK_CB(skb).pid = 0; /* sender pid */ + NETLINK_CB(skb).dst_group = HW_EVENT_GROUP; + /* broadcast the event */ + netlink_broadcast(nl_event_sock, skb, 0, HW_EVENT_GROUP, + GFP_KERNEL); + + continue; + nlmsg_failure: + printk(KERN_WARNING + "mxc_hw_event: No tailroom for NLMSG in skb\n"); + alloc_failure: + /* free the event node, set to unused */ + spin_lock_irq(&list_lock); + list_del(&event->list); + list_add_tail(&event->list, &free_head); + spin_unlock_irq(&list_lock); + } + } + + return 0; +} + +/*! + * + * @priority the event priority, REALTIME, EMERENCY, NORMAL + * @new_event event id to be send + */ +int hw_event_send(int priority, struct mxc_hw_event *new_event) +{ + unsigned int size; + struct sk_buff *skb = NULL; + struct nlmsghdr *nlh = NULL; + struct mxc_hw_event *event; + struct hw_event_elem *event_elem; + int ret; + unsigned long flag; + struct list_head *list_node; + + if (!initialized) { + pr_info("HW Event module has not been initialized\n"); + return -1; + } + + if (priority == HWE_HIGH_PRIORITY) { + /** + * the most high priority event, + * we send it immediatly. + */ + + size = NLMSG_SPACE(sizeof(struct mxc_hw_event)); + + /* alloc skb */ + if (in_interrupt()) { + skb = alloc_skb(size, GFP_ATOMIC); + } else { + skb = alloc_skb(size, GFP_KERNEL); + } + if (!skb) { + /* if failed alloc skb, we drop this event */ + printk(KERN_WARNING + "hw_event send: skb_alloc() failed\n"); + goto send_later; + } + + /* put the netlink header struct to skb */ + nlh = NLMSG_PUT(skb, 0, seq++, NLMSG_DONE, size - sizeof(*nlh)); + + /* fill the netlink data */ + event = (struct mxc_hw_event *)NLMSG_DATA(nlh); + memcpy(event, new_event, sizeof(struct mxc_hw_event)); + + /* send to all process that create this socket */ + NETLINK_CB(skb).pid = 0; /* sender pid */ + NETLINK_CB(skb).dst_group = HW_EVENT_GROUP; + /* broadcast the event */ + ret = netlink_broadcast(nl_event_sock, skb, 0, HW_EVENT_GROUP, + in_interrupt() ? GFP_ATOMIC : + GFP_KERNEL); + if (ret) { + + nlmsg_failure: + /* send failed */ + kfree_skb(skb); + goto send_later; + } + + return 0; + } + + send_later: + spin_lock_irqsave(&list_lock, flag); + if (list_empty(&free_head)) { + spin_unlock_irqrestore(&list_lock, flag); + /* no more free event node */ + printk(KERN_WARNING "mxc_event send: no more free node\n"); + return -1; + } + + /* get a free node from free list, and added to event list */ + list_node = free_head.next; + /* fill event */ + event_elem = list_entry(list_node, struct hw_event_elem, list); + event_elem->event = *new_event; + list_move(list_node, &event_head); + spin_unlock_irqrestore(&list_lock, flag); + + wake_up(&event_wq); + + return 0; +} + +static int __init mxc_hw_event_init(void) +{ + int i; + + /* initial the list head for event and free */ + INIT_LIST_HEAD(&free_head); + INIT_LIST_HEAD(&event_head); + + /* initial the free list */ + for (i = 0; i < EVENT_POOL_SIZE; i++) + list_add_tail(&events_pool[i].list, &free_head); + + /* create netlink kernel sock */ + nl_event_sock = + netlink_kernel_create(&init_net, NETLINK_USERSOCK, 0, NULL, NULL, + THIS_MODULE); + if (!nl_event_sock) { + printk(KERN_WARNING + "mxc_hw_event: Fail to create netlink socket.\n"); + return 1; + } + + hwevent_kthread = kthread_run(hw_event_thread, NULL, "hwevent"); + if (IS_ERR(hwevent_kthread)) { + printk(KERN_WARNING + "mxc_hw_event: Fail to create hwevent thread.\n"); + return 1; + } + + initialized = 1; + + return 0; +} + +static void __exit mxc_hw_event_exit(void) +{ + kthread_stop(hwevent_kthread); + /* wait for thread completion */ + sock_release(nl_event_sock->sk_socket); +} + +module_init(mxc_hw_event_init); +module_exit(mxc_hw_event_exit); + +EXPORT_SYMBOL(hw_event_send); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/ipu/Kconfig b/drivers/mxc/ipu/Kconfig new file mode 100644 index 000000000000..919cb598c294 --- /dev/null +++ b/drivers/mxc/ipu/Kconfig @@ -0,0 +1,4 @@ +config MXC_IPU_V1 + bool + +source "drivers/mxc/ipu/pf/Kconfig" diff --git a/drivers/mxc/ipu/Makefile b/drivers/mxc/ipu/Makefile new file mode 100644 index 000000000000..4e9f19f9afa5 --- /dev/null +++ b/drivers/mxc/ipu/Makefile @@ -0,0 +1,5 @@ +obj-$(CONFIG_MXC_IPU_V1) = mxc_ipu.o + +mxc_ipu-objs := ipu_common.o ipu_sdc.o ipu_adc.o ipu_ic.o ipu_csi.o ipu_device.o ipu_calc_stripes_sizes.o + +obj-$(CONFIG_MXC_IPU_PF) += pf/ diff --git a/drivers/mxc/ipu/ipu_adc.c b/drivers/mxc/ipu/ipu_adc.c new file mode 100644 index 000000000000..ee3cf916b2f3 --- /dev/null +++ b/drivers/mxc/ipu/ipu_adc.c @@ -0,0 +1,689 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_adc.c + * + * @brief IPU ADC functions + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +/*#define ADC_CHAN1_SA_MASK 0xFF800000 */ + +static void _ipu_set_cmd_data_mappings(display_port_t disp, + uint32_t pixel_fmt, int ifc_width); + +int32_t _ipu_adc_init_channel(ipu_channel_t chan, display_port_t disp, + mcu_mode_t cmd, int16_t x_pos, int16_t y_pos) +{ + uint32_t reg; + uint32_t start_addr, stride; + unsigned long lock_flags; + uint32_t size; + + size = 0; + + switch (disp) { + case DISP0: + reg = __raw_readl(ADC_DISP0_CONF); + stride = reg & ADC_DISP_CONF_SL_MASK; + break; + case DISP1: + reg = __raw_readl(ADC_DISP1_CONF); + stride = reg & ADC_DISP_CONF_SL_MASK; + break; + case DISP2: + reg = __raw_readl(ADC_DISP2_CONF); + stride = reg & ADC_DISP_CONF_SL_MASK; + break; + default: + return -EINVAL; + } + + if (stride == 0) + return -EINVAL; + + stride++; + start_addr = (y_pos * stride) + x_pos; + + spin_lock_irqsave(&ipu_lock, lock_flags); + reg = __raw_readl(ADC_CONF); + + switch (chan) { + case ADC_SYS1: + reg &= ~0x00FF4000; + reg |= + ((uint32_t) size << 21 | (uint32_t) disp << 19 | (uint32_t) + cmd << 16); + + __raw_writel(start_addr, ADC_SYSCHA1_SA); + break; + + case ADC_SYS2: + reg &= ~0xFF008000; + reg |= + ((uint32_t) size << 29 | (uint32_t) disp << 27 | (uint32_t) + cmd << 24); + + __raw_writel(start_addr, ADC_SYSCHA2_SA); + break; + + case CSI_PRP_VF_ADC: + case MEM_PRP_VF_ADC: + reg &= ~0x000000F9; + reg |= + ((uint32_t) size << 5 | (uint32_t) disp << 3 | + ADC_CONF_PRP_EN); + + __raw_writel(start_addr, ADC_PRPCHAN_SA); + break; + + case MEM_PP_ADC: + reg &= ~0x00003F02; + reg |= + ((uint32_t) size << 10 | (uint32_t) disp << 8 | + ADC_CONF_PP_EN); + + __raw_writel(start_addr, ADC_PPCHAN_SA); + break; + default: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -1; + break; + } + __raw_writel(reg, ADC_CONF); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +int32_t _ipu_adc_uninit_channel(ipu_channel_t chan) +{ + uint32_t reg; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + reg = __raw_readl(ADC_CONF); + + switch (chan) { + case ADC_SYS1: + reg &= ~0x00FF4000; + break; + case ADC_SYS2: + reg &= ~0xFF008000; + break; + case CSI_PRP_VF_ADC: + case MEM_PRP_VF_ADC: + reg &= ~0x000000F9; + break; + case MEM_PP_ADC: + reg &= ~0x00003F02; + break; + default: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -1; + break; + } + __raw_writel(reg, ADC_CONF); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +int32_t ipu_adc_write_template(display_port_t disp, uint32_t *pCmd, bool write) +{ + uint32_t ima_addr = 0; + uint32_t row_nu; + int i; + + /* Set IPU_IMA_ADDR (IPU Internal Memory Access Address) */ + /* MEM_NU = 0x0001 (CPM) */ + /* ROW_NU = 2*N ( N is channel number) */ + /* WORD_NU = 0 */ + if (write) { + row_nu = (uint32_t) disp * 2 * ATM_ADDR_RANGE; + } else { + row_nu = ((uint32_t) disp * 2 + 1) * ATM_ADDR_RANGE; + } + + /* form template addr for IPU_IMA_ADDR */ + ima_addr = (0x3 << 16 /*Template memory */ | row_nu << 3); + + __raw_writel(ima_addr, IPU_IMA_ADDR); + + /* write template data for IPU_IMA_DATA */ + for (i = 0; i < TEMPLATE_BUF_SIZE; i++) + /* only DATA field are needed */ + __raw_writel(pCmd[i], IPU_IMA_DATA); + + return 0; +} + +int32_t +ipu_adc_write_cmd(display_port_t disp, cmddata_t type, + uint32_t cmd, const uint32_t *params, uint16_t numParams) +{ + uint16_t i; + int disable_di = 0; + u32 reg; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + reg = __raw_readl(IPU_CONF); + if ((reg & IPU_CONF_DI_EN) == 0) { + disable_di = 1; + reg |= IPU_CONF_DI_EN; + __raw_writel(reg, IPU_CONF); + } + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + __raw_writel((uint32_t) ((type ? 0x0 : 0x1) | disp << 1 | 0x10), + DI_DISP_LLA_CONF); + __raw_writel(cmd, DI_DISP_LLA_DATA); + udelay(3); + + __raw_writel((uint32_t) (0x10 | disp << 1 | 0x11), DI_DISP_LLA_CONF); + for (i = 0; i < numParams; i++) { + __raw_writel(params[i], DI_DISP_LLA_DATA); + udelay(3); + } + + if (disable_di) { + spin_lock_irqsave(&ipu_lock, lock_flags); + reg = __raw_readl(IPU_CONF); + reg &= ~IPU_CONF_DI_EN; + __raw_writel(reg, IPU_CONF); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + } + + return 0; +} + +int32_t ipu_adc_set_update_mode(ipu_channel_t channel, + ipu_adc_update_mode_t mode, + uint32_t refresh_rate, unsigned long addr, + uint32_t *size) +{ + int32_t err = 0; + uint32_t ref_per, reg, src = 0; + unsigned long lock_flags; + uint32_t ipu_freq; + + ipu_freq = clk_get_rate(g_ipu_clk); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPU_FS_DISP_FLOW); + reg &= ~FS_AUTO_REF_PER_MASK; + switch (mode) { + case IPU_ADC_REFRESH_NONE: + src = 0; + break; + case IPU_ADC_AUTO_REFRESH: + if (refresh_rate == 0) { + err = -EINVAL; + goto err0; + } + ref_per = ipu_freq / ((1UL << 17) * refresh_rate); + ref_per--; + reg |= ref_per << FS_AUTO_REF_PER_OFFSET; + + src = FS_SRC_AUTOREF; + break; + case IPU_ADC_AUTO_REFRESH_SNOOP: + if (refresh_rate == 0) { + err = -EINVAL; + goto err0; + } + ref_per = ipu_freq / ((1UL << 17) * refresh_rate); + ref_per--; + reg |= ref_per << FS_AUTO_REF_PER_OFFSET; + + src = FS_SRC_AUTOREF_SNOOP; + break; + case IPU_ADC_SNOOPING: + src = FS_SRC_SNOOP; + break; + } + + switch (channel) { + case ADC_SYS1: + reg &= ~FS_ADC1_SRC_SEL_MASK; + reg |= src << FS_ADC1_SRC_SEL_OFFSET; + break; + case ADC_SYS2: + reg &= ~FS_ADC2_SRC_SEL_MASK; + reg |= src << FS_ADC2_SRC_SEL_OFFSET; + break; + default: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + __raw_writel(reg, IPU_FS_DISP_FLOW); + + /* Setup bus snooping */ + if ((mode == IPU_ADC_AUTO_REFRESH_SNOOP) || (mode == IPU_ADC_SNOOPING)) { + err = mxc_snoop_set_config(0, addr, *size); + if (err > 0) { + *size = err; + err = 0; + } + } else { + mxc_snoop_set_config(0, 0, 0); + } + + err0: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return err; +} + +int32_t ipu_adc_get_snooping_status(uint32_t *statl, uint32_t *stath) +{ + return mxc_snoop_get_status(0, statl, stath); +} + +int32_t ipu_adc_init_panel(display_port_t disp, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint32_t stride, + ipu_adc_sig_cfg_t sig, + display_addressing_t addr, + uint32_t vsync_width, vsync_t mode) +{ + uint32_t temp; + unsigned long lock_flags; + uint32_t ser_conf; + uint32_t disp_conf; + uint32_t adc_disp_conf; + uint32_t adc_disp_vsync; + uint32_t old_pol; + + if ((disp != DISP1) && (disp != DISP2) && + (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL)) { + return -EINVAL; + } +/* adc_disp_conf = ((uint32_t)((((size == 3)||(size == 2))?1:0)<<14) | */ +/* (uint32_t)addr<<12 | (stride-1)); */ + adc_disp_conf = (uint32_t) addr << 12 | (stride - 1); + + _ipu_set_cmd_data_mappings(disp, pixel_fmt, sig.ifc_width); + + spin_lock_irqsave(&ipu_lock, lock_flags); + disp_conf = __raw_readl(DI_DISP_IF_CONF); + old_pol = __raw_readl(DI_DISP_SIG_POL); + adc_disp_vsync = __raw_readl(ADC_DISP_VSYNC); + + switch (disp) { + case DISP0: + __raw_writel(adc_disp_conf, ADC_DISP0_CONF); + __raw_writel((((height - 1) << 16) | (width - 1)), + ADC_DISP0_SS); + + adc_disp_vsync &= ~(ADC_DISP_VSYNC_D0_MODE_MASK | + ADC_DISP_VSYNC_D0_WIDTH_MASK); + adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode; + + old_pol &= ~0x2000003FL; + old_pol |= sig.data_pol | sig.cs_pol << 1 | + sig.addr_pol << 2 | sig.read_pol << 3 | + sig.write_pol << 4 | sig.Vsync_pol << 5 | + sig.burst_pol << 29; + __raw_writel(old_pol, DI_DISP_SIG_POL); + + disp_conf &= ~0x0000001FL; + disp_conf |= (sig.burst_mode << 3) | (sig.ifc_mode << 1) | + DI_CONF_DISP0_EN; + __raw_writel(disp_conf, DI_DISP_IF_CONF); + break; + case DISP1: + __raw_writel(adc_disp_conf, ADC_DISP1_CONF); + __raw_writel((((height - 1) << 16) | (width - 1)), + ADC_DISP12_SS); + + adc_disp_vsync &= ~(ADC_DISP_VSYNC_D12_MODE_MASK | + ADC_DISP_VSYNC_D12_WIDTH_MASK); + adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode; + + old_pol &= ~0x4000FF00L; + old_pol |= (sig.Vsync_pol << 6 | sig.data_pol << 8 | + sig.cs_pol << 9 | sig.addr_pol << 10 | + sig.read_pol << 11 | sig.write_pol << 12 | + sig.clk_pol << 14 | sig.burst_pol << 30); + __raw_writel(old_pol, DI_DISP_SIG_POL); + + disp_conf &= ~0x00003F00L; + if (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL) { + ser_conf = (sig.ifc_width - 1) << + DI_SER_DISPx_CONF_SER_BIT_NUM_OFFSET; + if (sig.ser_preamble_len) { + ser_conf |= DI_SER_DISPx_CONF_PREAMBLE_EN; + ser_conf |= sig.ser_preamble << + DI_SER_DISPx_CONF_PREAMBLE_OFFSET; + ser_conf |= (sig.ser_preamble_len - 1) << + DI_SER_DISPx_CONF_PREAMBLE_LEN_OFFSET; + } + + ser_conf |= + sig.ser_rw_mode << DI_SER_DISPx_CONF_RW_CFG_OFFSET; + + if (sig.burst_mode == IPU_ADC_BURST_SERIAL) + ser_conf |= DI_SER_DISPx_CONF_BURST_MODE_EN; + __raw_writel(ser_conf, DI_SER_DISP1_CONF); + } else { /* parallel interface */ + disp_conf |= (uint32_t) (sig.burst_mode << 12); + } + disp_conf |= (sig.ifc_mode << 9) | DI_CONF_DISP1_EN; + __raw_writel(disp_conf, DI_DISP_IF_CONF); + break; + case DISP2: + __raw_writel(adc_disp_conf, ADC_DISP2_CONF); + __raw_writel((((height - 1) << 16) | (width - 1)), + ADC_DISP12_SS); + + adc_disp_vsync &= ~(ADC_DISP_VSYNC_D12_MODE_MASK | + ADC_DISP_VSYNC_D12_WIDTH_MASK); + adc_disp_vsync |= (vsync_width << 16) | (uint32_t) mode; + + old_pol &= ~0x80FF0000L; + temp = (uint32_t) (sig.data_pol << 16 | sig.cs_pol << 17 | + sig.addr_pol << 18 | sig.read_pol << 19 | + sig.write_pol << 20 | sig.Vsync_pol << 6 | + sig.burst_pol << 31 | sig.clk_pol << 22); + __raw_writel(temp | old_pol, DI_DISP_SIG_POL); + + disp_conf &= ~0x003F0000L; + if (sig.ifc_mode >= IPU_ADC_IFC_MODE_3WIRE_SERIAL) { + ser_conf = (sig.ifc_width - 1) << + DI_SER_DISPx_CONF_SER_BIT_NUM_OFFSET; + if (sig.ser_preamble_len) { + ser_conf |= DI_SER_DISPx_CONF_PREAMBLE_EN; + ser_conf |= sig.ser_preamble << + DI_SER_DISPx_CONF_PREAMBLE_OFFSET; + ser_conf |= (sig.ser_preamble_len - 1) << + DI_SER_DISPx_CONF_PREAMBLE_LEN_OFFSET; + + } + + ser_conf |= + sig.ser_rw_mode << DI_SER_DISPx_CONF_RW_CFG_OFFSET; + + if (sig.burst_mode == IPU_ADC_BURST_SERIAL) + ser_conf |= DI_SER_DISPx_CONF_BURST_MODE_EN; + __raw_writel(ser_conf, DI_SER_DISP2_CONF); + } else { /* parallel interface */ + disp_conf |= (uint32_t) (sig.burst_mode << 20); + } + disp_conf |= (sig.ifc_mode << 17) | DI_CONF_DISP2_EN; + __raw_writel(disp_conf, DI_DISP_IF_CONF); + break; + default: + break; + } + + __raw_writel(adc_disp_vsync, ADC_DISP_VSYNC); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +int32_t ipu_adc_init_ifc_timing(display_port_t disp, bool read, + uint32_t cycle_time, + uint32_t up_time, + uint32_t down_time, + uint32_t read_latch_time, uint32_t pixel_clk) +{ + uint32_t reg; + uint32_t time_conf3 = 0; + uint32_t clk_per; + uint32_t up_per; + uint32_t down_per; + uint32_t read_per; + uint32_t pixclk_per = 0; + uint32_t ipu_freq; + + ipu_freq = clk_get_rate(g_ipu_clk); + + clk_per = (cycle_time * (ipu_freq / 1000L) * 16L) / 1000000L; + up_per = (up_time * (ipu_freq / 1000L) * 4L) / 1000000L; + down_per = (down_time * (ipu_freq / 1000L) * 4L) / 1000000L; + + reg = (clk_per << DISPx_IF_CLK_PER_OFFSET) | + (up_per << DISPx_IF_CLK_UP_OFFSET) | + (down_per << DISPx_IF_CLK_DOWN_OFFSET); + + if (read) { + read_per = + (read_latch_time * (ipu_freq / 1000L) * 4L) / 1000000L; + if (pixel_clk) + pixclk_per = (ipu_freq * 16L) / pixel_clk; + time_conf3 = (read_per << DISPx_IF_CLK_READ_EN_OFFSET) | + (pixclk_per << DISPx_PIX_CLK_PER_OFFSET); + } + + dev_dbg(g_ipu_dev, "DI_DISPx_TIME_CONF_1/2 = 0x%08X\n", reg); + dev_dbg(g_ipu_dev, "DI_DISPx_TIME_CONF_3 = 0x%08X\n", time_conf3); + + switch (disp) { + case DISP0: + if (read) { + __raw_writel(reg, DI_DISP0_TIME_CONF_2); + __raw_writel(time_conf3, DI_DISP0_TIME_CONF_3); + } else { + __raw_writel(reg, DI_DISP0_TIME_CONF_1); + } + break; + case DISP1: + if (read) { + __raw_writel(reg, DI_DISP1_TIME_CONF_2); + __raw_writel(time_conf3, DI_DISP1_TIME_CONF_3); + } else { + __raw_writel(reg, DI_DISP1_TIME_CONF_1); + } + break; + case DISP2: + if (read) { + __raw_writel(reg, DI_DISP2_TIME_CONF_2); + __raw_writel(time_conf3, DI_DISP2_TIME_CONF_3); + } else { + __raw_writel(reg, DI_DISP2_TIME_CONF_1); + } + break; + default: + return -EINVAL; + break; + } + + return 0; +} + +struct ipu_adc_di_map { + uint32_t map_byte1; + uint32_t map_byte2; + uint32_t map_byte3; + uint32_t cycle_cnt; +}; + +static const struct ipu_adc_di_map di_mappings[] = { + [0] = { + /* RGB888, 8-bit bus */ + .map_byte1 = 0x1600AAAA, + .map_byte2 = 0x00E05555, + .map_byte2 = 0x00070000, + .cycle_cnt = 3, + }, + [1] = { + /* RGB666, 8-bit bus */ + .map_byte1 = 0x1C00AAAF, + .map_byte2 = 0x00E0555F, + .map_byte3 = 0x0007000F, + .cycle_cnt = 3, + }, + [2] = { + /* RGB565, 8-bit bus */ + .map_byte1 = 0x008055BF, + .map_byte2 = 0x0142015F, + .map_byte3 = 0x0007003F, + .cycle_cnt = 2, + }, + [3] = { + /* RGB888, 24-bit bus */ + .map_byte1 = 0x0007000F, + .map_byte2 = 0x000F000F, + .map_byte3 = 0x0017000F, + .cycle_cnt = 1, + }, + [4] = { + /* RGB666, 18-bit bus */ + .map_byte1 = 0x0005000F, + .map_byte2 = 0x000B000F, + .map_byte3 = 0x0011000F, + .cycle_cnt = 1, + }, + [5] = { + /* RGB565, 16-bit bus */ + .map_byte1 = 0x0004003F, + .map_byte2 = 0x000A000F, + .map_byte3 = 0x000F003F, + .cycle_cnt = 1, + }, +}; + +/* Private methods */ +static void _ipu_set_cmd_data_mappings(display_port_t disp, + uint32_t pixel_fmt, int ifc_width) +{ + uint32_t reg; + u32 map = 0; + + if (ifc_width == 8) { + switch (pixel_fmt) { + case IPU_PIX_FMT_BGR24: + map = 0; + break; + case IPU_PIX_FMT_RGB666: + map = 1; + break; + case IPU_PIX_FMT_RGB565: + map = 2; + break; + default: + break; + } + } else if (ifc_width >= 16) { + switch (pixel_fmt) { + case IPU_PIX_FMT_BGR24: + map = 3; + break; + case IPU_PIX_FMT_RGB666: + map = 4; + break; + case IPU_PIX_FMT_RGB565: + map = 5; + break; + default: + break; + } + } + + switch (disp) { + case DISP0: + if (ifc_width == 8) { + __raw_writel(0x00070000, DI_DISP0_CB0_MAP); + __raw_writel(0x0000FFFF, DI_DISP0_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP0_CB2_MAP); + } else { + __raw_writel(0x00070000, DI_DISP0_CB0_MAP); + __raw_writel(0x000F0000, DI_DISP0_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP0_CB2_MAP); + } + __raw_writel(di_mappings[map].map_byte1, DI_DISP0_DB0_MAP); + __raw_writel(di_mappings[map].map_byte2, DI_DISP0_DB1_MAP); + __raw_writel(di_mappings[map].map_byte3, DI_DISP0_DB2_MAP); + reg = __raw_readl(DI_DISP_ACC_CC); + reg &= ~DISP0_IF_CLK_CNT_D_MASK; + reg |= (di_mappings[map].cycle_cnt - 1) << + DISP0_IF_CLK_CNT_D_OFFSET; + __raw_writel(reg, DI_DISP_ACC_CC); + break; + case DISP1: + if (ifc_width == 8) { + __raw_writel(0x00070000, DI_DISP1_CB0_MAP); + __raw_writel(0x0000FFFF, DI_DISP1_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP1_CB2_MAP); + } else { + __raw_writel(0x00070000, DI_DISP1_CB0_MAP); + __raw_writel(0x000F0000, DI_DISP1_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP1_CB2_MAP); + } + __raw_writel(di_mappings[map].map_byte1, DI_DISP1_DB0_MAP); + __raw_writel(di_mappings[map].map_byte2, DI_DISP1_DB1_MAP); + __raw_writel(di_mappings[map].map_byte3, DI_DISP1_DB2_MAP); + reg = __raw_readl(DI_DISP_ACC_CC); + reg &= ~DISP1_IF_CLK_CNT_D_MASK; + reg |= (di_mappings[map].cycle_cnt - 1) << + DISP1_IF_CLK_CNT_D_OFFSET; + __raw_writel(reg, DI_DISP_ACC_CC); + break; + case DISP2: + if (ifc_width == 8) { + __raw_writel(0x00070000, DI_DISP2_CB0_MAP); + __raw_writel(0x0000FFFF, DI_DISP2_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP2_CB2_MAP); + } else { + __raw_writel(0x00070000, DI_DISP2_CB0_MAP); + __raw_writel(0x000F0000, DI_DISP2_CB1_MAP); + __raw_writel(0x0000FFFF, DI_DISP2_CB2_MAP); + } + __raw_writel(di_mappings[map].map_byte1, DI_DISP2_DB0_MAP); + __raw_writel(di_mappings[map].map_byte2, DI_DISP2_DB1_MAP); + __raw_writel(di_mappings[map].map_byte3, DI_DISP2_DB2_MAP); + reg = __raw_readl(DI_DISP_ACC_CC); + reg &= ~DISP2_IF_CLK_CNT_D_MASK; + reg |= (di_mappings[map].cycle_cnt - 1) << + DISP2_IF_CLK_CNT_D_OFFSET; + __raw_writel(reg, DI_DISP_ACC_CC); + break; + default: + break; + } +} + +void ipu_disp_direct_write(ipu_channel_t channel, u32 value, u32 offset) +{ + /*TODO*/ +} + +int ipu_init_async_panel(int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig) +{ + /*TODO:uniform interface for ipu async panel init*/ + return -1; +} + +EXPORT_SYMBOL(ipu_adc_write_template); +EXPORT_SYMBOL(ipu_adc_write_cmd); +EXPORT_SYMBOL(ipu_adc_set_update_mode); +EXPORT_SYMBOL(ipu_adc_init_panel); +EXPORT_SYMBOL(ipu_adc_init_ifc_timing); diff --git a/drivers/mxc/ipu/ipu_calc_stripes_sizes.c b/drivers/mxc/ipu/ipu_calc_stripes_sizes.c new file mode 100644 index 000000000000..3a45c0bfc488 --- /dev/null +++ b/drivers/mxc/ipu/ipu_calc_stripes_sizes.c @@ -0,0 +1,374 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_calc_stripes_sizes.c + * + * @brief IPU IC functions + * + * @ingroup IPU + */ + +#include +#include +#include + +#define BPP_32 0 +#define BPP_16 3 +#define BPP_8 5 +#define BPP_24 1 +#define BPP_12 4 +#define BPP_18 2 + +static u64 _do_div(u64 a, u32 b) +{ + u64 div; + div = a; + do_div(div, b); + return div; +} + +static u32 truncate(u32 up, /* 0: down; else: up */ + u64 a, /* must be non-negative */ + u32 b) +{ + u32 d; + u64 div; + div = _do_div(a, b); + d = b * (div >> 32); + if (up && (a > (((u64)d) << 32))) + return d+b; + else + return d; +} + +static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write) +{/* return input_f */ + unsigned int f_calculated = 0; + switch (pfs) { + case IPU_PIX_FMT_YVU422P: + case IPU_PIX_FMT_YUV422P: + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + f_calculated = 16; + break; + + case IPU_PIX_FMT_NV12: + f_calculated = 8; + break; + + default: + f_calculated = 0; + break; + + } + if (!f_calculated) { + switch (bpp) { + case BPP_32: + f_calculated = 2; + break; + + case BPP_16: + f_calculated = 4; + break; + + case BPP_8: + case BPP_24: + f_calculated = 8; + break; + + case BPP_12: + f_calculated = 16; + break; + + case BPP_18: + f_calculated = 32; + break; + + default: + f_calculated = 0; + break; + } + } + return f_calculated; +} + + +static unsigned int m_calc(unsigned int pfs) +{ + unsigned int m_calculated = 0; + switch (pfs) { + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + case IPU_PIX_FMT_YVU422P: + case IPU_PIX_FMT_YUV422P: + case IPU_PIX_FMT_YVU420P: + case IPU_PIX_FMT_NV12: + m_calculated = 8; + break; + + case IPU_PIX_FMT_YUYV: + case IPU_PIX_FMT_UYVY: + m_calculated = 2; + break; + + default: + m_calculated = 1; + break; + + } + return m_calculated; +} + + +/* Stripe parameters calculator */ +/************************************************************************** +Notes: +MSW = the maximal width allowed for a stripe + i.MX31: 720, i.MX35: 800, i.MX37/51/53: 1024 +cirr = the maximal inverse resizing ratio for which overlap in the input + is requested; typically cirr~2 +equal_stripes: + 0: each stripe is allowed to have independent parameters + for maximal image quality + 1: the stripes are requested to have identical parameters + (except the base address), for maximal performance +If performance is the top priority (above image quality) + Avoid overlap, by setting CIRR = 0 + This will also force effectively identical_stripes = 1 + Choose IF & OF that corresponds to the same IOX/SX for both stripes + Choose IFW & OFW such that + IFW/IM, IFW/IF, OFW/OM, OFW/OF are even integers + The function returns an error status: + 0: no error + 1: invalid input parameters -> aborted without result + Valid parameters should satisfy the following conditions + IFW <= OFW, otherwise downsizing is required + - which is not supported yet + 4 <= IFW,OFW, so some interpolation may be needed even without overlap + IM, OM, IF, OF should not vanish + 2*IF <= IFW + so the frame can be split to two equal stripes, even without overlap + 2*(OF+IF/irr_opt) <= OFW + so a valid positive INW exists even for equal stripes + OF <= MSW, otherwise, the left stripe cannot be sufficiently large + MSW < OFW, so splitting to stripes is required + OFW <= 2*MSW, so two stripes are sufficient + (this also implies that 2<=MSW) + 2: OF is not a multiple of OM - not fully-supported yet + Output is produced but OW is not guaranited to be a multiple of OM + 4: OFW reduced to be a multiple of OM + 8: CIRR > 1: truncated to 1 + Overlap is not supported (and not needed) y for upsizing) +**************************************************************************/ +int ipu_calc_stripes_sizes(const unsigned int input_frame_width, + /* input frame width;>1 */ + unsigned int output_frame_width, /* output frame width; >1 */ + const unsigned int maximal_stripe_width, + /* the maximal width allowed for a stripe */ + const unsigned long long cirr, /* see above */ + const unsigned int equal_stripes, /* see above */ + u32 input_pixelformat,/* pixel format after of read channel*/ + u32 output_pixelformat,/* pixel format after of write channel*/ + struct stripe_param *left, + struct stripe_param *right) +{ + const unsigned int irr_frac_bits = 13; + const unsigned long irr_steps = 1 << irr_frac_bits; + const u64 dirr = ((u64)1) << (32 - 2); + /* The maximum relative difference allowed between the irrs */ + const u64 cr = ((u64)4) << 32; + /* The importance ratio between the two terms in the cost function below */ + + unsigned int status; + unsigned int temp; + unsigned int onw_min; + unsigned int inw, onw, inw_best = 0; + /* number of pixels in the left stripe NOT hidden by the right stripe */ + u64 irr_opt; /* the optimal inverse resizing ratio */ + u64 rr_opt; /* the optimal resizing ratio = 1/irr_opt*/ + u64 dinw; /* the misalignment between the stripes */ + /* (measured in units of input columns) */ + u64 difwl, difwr; + /* The number of input columns not reflected in the output */ + /* the resizing ratio used for the right stripe is */ + /* left->irr and right->irr respectively */ + u64 cost, cost_min; + u64 div; /* result of division */ + + unsigned int input_m, input_f, output_m, output_f; /* parameters for upsizing by stripes */ + + status = 0; + + /* M, F calculations */ + /* read back pfs from params */ + + input_f = f_calc(input_pixelformat, 0, NULL); + input_m = 16; + /* BPP should be used in the out_F calc */ + /* Temporarily not used */ + /* out_F = F_calc(idmac->pfs, idmac->bpp, NULL); */ + + output_f = 16; + output_m = m_calc(output_pixelformat); + + + if ((output_frame_width < input_frame_width) || (input_frame_width < 4) + || (output_frame_width < 4)) + return 1; + + irr_opt = _do_div((((u64)(input_frame_width - 1)) << 32), + (output_frame_width - 1)); + rr_opt = _do_div((((u64)(output_frame_width - 1)) << 32), + (input_frame_width - 1)); + + if ((input_m == 0) || (output_m == 0) || (input_f == 0) || (output_f == 0) + || (input_frame_width < (2 * input_f)) + || ((((u64)output_frame_width) << 32) < + (2 * ((((u64)output_f) << 32) + (input_f * rr_opt)))) + || (maximal_stripe_width < output_f) + || (output_frame_width <= maximal_stripe_width) + || ((2 * maximal_stripe_width) < output_frame_width)) + return 1; + + if (output_f % output_m) + status += 2; + + temp = truncate(0, (((u64)output_frame_width) << 32), output_m); + if (temp < output_frame_width) { + output_frame_width = temp; + status += 4; + } + + if (equal_stripes) { + if ((irr_opt > cirr) /* overlap in the input is not requested */ + && ((input_frame_width % (input_m << 1)) == 0) + && ((input_frame_width % (input_f << 1)) == 0) + && ((output_frame_width % (output_m << 1)) == 0) + && ((output_frame_width % (output_f << 1)) == 0)) { + /* without overlap */ + left->input_width = right->input_width = right->input_column = + input_frame_width >> 1; + left->output_width = right->output_width = right->output_column = + output_frame_width >> 1; + left->input_column = right->input_column = 0; + div = _do_div(((((u64)irr_steps) << 32) * + (right->input_width - 1)), (right->output_width - 1)); + left->irr = right->irr = truncate(0, div, 1); + } else { /* with overlap */ + onw = truncate(0, (((u64)output_frame_width) << 32) >> 1, + output_f); + inw = truncate(0, onw * irr_opt, input_f); + /* this is the maximal inw which allows the same resizing ratio */ + /* in both stripes */ + onw = truncate(1, (inw * rr_opt), output_f); + div = _do_div((((u64)(irr_steps * inw)) << + 32), onw); + left->irr = right->irr = truncate(0, div, 1); + left->output_width = right->output_width = + output_frame_width - onw; + /* These are valid assignments for output_width, */ + /* assuming output_f is a multiple of output_m */ + div = (((u64)(left->output_width-1) * (left->irr)) << 32); + div = (((u64)1) << 32) + _do_div(div, irr_steps); + + left->input_width = right->input_width = truncate(1, div, input_m); + + div = _do_div((((u64)((right->output_width - 1) * right->irr)) << + 32), irr_steps); + difwr = (((u64)(input_frame_width - 1 - inw)) << 32) - div; + div = _do_div((difwr + (((u64)input_f) << 32)), 2); + left->input_column = truncate(0, div, input_f); + + + /* This splits the truncated input columns evenly */ + /* between the left and right margins */ + right->input_column = left->input_column + inw; + left->output_column = 0; + right->output_column = onw; + } + } else { /* independent stripes */ + onw_min = output_frame_width - maximal_stripe_width; + /* onw is a multiple of output_f, in the range */ + /* [max(output_f,output_frame_width-maximal_stripe_width),*/ + /*min(output_frame_width-2,maximal_stripe_width)] */ + /* definitely beyond the cost of any valid setting */ + cost_min = (((u64)input_frame_width) << 32) + cr; + onw = truncate(0, ((u64)maximal_stripe_width), output_f); + if (output_frame_width - onw == 1) + onw -= output_f; /* => onw and output_frame_width-1-onw are positive */ + inw = truncate(0, onw * irr_opt, input_f); + /* this is the maximal inw which allows the same resizing ratio */ + /* in both stripes */ + onw = truncate(1, inw * rr_opt, output_f); + do { + div = _do_div((((u64)(irr_steps * inw)) << 32), onw); + left->irr = truncate(0, div, 1); + div = _do_div((((u64)(onw * left->irr)) << 32), + irr_steps); + dinw = (((u64)inw) << 32) - div; + + div = _do_div((((u64)((output_frame_width - 1 - onw) * left->irr)) << + 32), irr_steps); + + difwl = (((u64)(input_frame_width - 1 - inw)) << 32) - div; + + cost = difwl + (((u64)(cr * dinw)) >> 32); + + if (cost < cost_min) { + inw_best = inw; + cost_min = cost; + } + + inw -= input_f; + onw = truncate(1, inw * rr_opt, output_f); + /* This is the minimal onw which allows the same resizing ratio */ + /* in both stripes */ + } while (onw >= onw_min); + + inw = inw_best; + onw = truncate(1, inw * rr_opt, output_f); + div = _do_div((((u64)(irr_steps * inw)) << 32), onw); + left->irr = truncate(0, div, 1); + + left->output_width = onw; + right->output_width = output_frame_width - onw; + /* These are valid assignments for output_width, */ + /* assuming output_f is a multiple of output_m */ + left->input_width = truncate(1, ((u64)(inw + 1)) << 32, input_m); + right->input_width = truncate(1, ((u64)(input_frame_width - inw)) << + 32, input_m); + + div = _do_div((((u64)(irr_steps * (input_frame_width - 1 - inw))) << + 32), (right->output_width - 1)); + right->irr = truncate(0, div, 1); + temp = truncate(0, ((u64)left->irr) * ((((u64)1) << 32) + dirr), 1); + if (temp < right->irr) + right->irr = temp; + div = _do_div(((u64)((right->output_width - 1) * right->irr) << + 32), irr_steps); + difwr = (u64)(input_frame_width - 1 - inw) - div; + + + div = _do_div((difwr + (((u64)input_f) << 32)), 2); + left->input_column = truncate(0, div, input_f); + + /* This splits the truncated input columns evenly */ + /* between the left and right margins */ + right->input_column = left->input_column + inw; + left->output_column = 0; + right->output_column = onw; + } + return status; +} +EXPORT_SYMBOL(ipu_calc_stripes_sizes); diff --git a/drivers/mxc/ipu/ipu_common.c b/drivers/mxc/ipu/ipu_common.c new file mode 100644 index 000000000000..fd4345283180 --- /dev/null +++ b/drivers/mxc/ipu/ipu_common.c @@ -0,0 +1,1970 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_common.c + * + * @brief This file contains the IPU driver common API functions. + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +/* + * This type definition is used to define a node in the GPIO interrupt queue for + * registered interrupts for GPIO pins. Each node contains the GPIO signal number + * associated with the ISR and the actual ISR function pointer. + */ +struct ipu_irq_node { + irqreturn_t(*handler) (int, void *); /*!< the ISR */ + const char *name; /*!< device associated with the interrupt */ + void *dev_id; /*!< some unique information for the ISR */ + __u32 flags; /*!< not used */ +}; + +/* Globals */ +struct clk *g_ipu_clk; +struct clk *g_ipu_csi_clk; +static struct clk *dfm_clk; +int g_ipu_irq[2]; +int g_ipu_hw_rev; +bool g_sec_chan_en[21]; +uint32_t g_channel_init_mask; +DEFINE_SPINLOCK(ipu_lock); +struct device *g_ipu_dev; + +static struct ipu_irq_node ipu_irq_list[IPU_IRQ_COUNT]; +static const char driver_name[] = "mxc_ipu"; + +static uint32_t g_ipu_config; +static uint32_t g_channel_init_mask_backup; +static bool g_csi_used; + +/* Static functions */ +static irqreturn_t ipu_irq_handler(int irq, void *desc); +static void _ipu_pf_init(ipu_channel_params_t *params); +static void _ipu_pf_uninit(void); + +static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) +{ + return ((type == IPU_INPUT_BUFFER) ? ((uint32_t) ch & 0xFF) : + ((type == IPU_OUTPUT_BUFFER) ? (((uint32_t) ch >> 8) & 0xFF) + : (((uint32_t) ch >> 16) & 0xFF))); +}; + +static inline uint32_t DMAParamAddr(uint32_t dma_ch) +{ + return 0x10000 | (dma_ch << 4); +}; + +/*! + * This function is called by the driver framework to initialize the IPU + * hardware. + * + * @param dev The device structure for the IPU passed in by the framework. + * + * @return This function returns 0 on success or negative error code on error + */ +static +int ipu_probe(struct platform_device *pdev) +{ + struct mxc_ipu_config *ipu_conf = pdev->dev.platform_data; + + spin_lock_init(&ipu_lock); + + g_ipu_dev = &pdev->dev; + g_ipu_hw_rev = ipu_conf->rev; + + /* Register IPU interrupts */ + g_ipu_irq[0] = platform_get_irq(pdev, 0); + if (g_ipu_irq[0] < 0) + return -EINVAL; + + if (request_irq(g_ipu_irq[0], ipu_irq_handler, 0, driver_name, 0) != 0) { + dev_err(g_ipu_dev, "request SYNC interrupt failed\n"); + return -EBUSY; + } + /* Some platforms have 2 IPU interrupts */ + g_ipu_irq[1] = platform_get_irq(pdev, 1); + if (g_ipu_irq[1] >= 0) { + if (request_irq + (g_ipu_irq[1], ipu_irq_handler, 0, driver_name, 0) != 0) { + dev_err(g_ipu_dev, "request ERR interrupt failed\n"); + return -EBUSY; + } + } + + /* Enable IPU and CSI clocks */ + /* Get IPU clock freq */ + g_ipu_clk = clk_get(&pdev->dev, "ipu_clk"); + dev_dbg(g_ipu_dev, "ipu_clk = %lu\n", clk_get_rate(g_ipu_clk)); + + g_ipu_csi_clk = clk_get(&pdev->dev, "csi_clk"); + + dfm_clk = clk_get(NULL, "dfm_clk"); + + clk_enable(g_ipu_clk); + + /* resetting the CONF register of the IPU */ + __raw_writel(0x00000000, IPU_CONF); + + __raw_writel(0x00100010L, DI_HSP_CLK_PER); + + /* Set SDC refresh channels as high priority */ + __raw_writel(0x0000C000L, IDMAC_CHA_PRI); + + /* Set to max back to back burst requests */ + __raw_writel(0x00000000L, IDMAC_CONF); + + register_ipu_device(); + + return 0; +} + +/*! + * This function is called to initialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to initalize. + * + * @param params Input parameter containing union of channel initialization + * parameters. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params) +{ + uint32_t ipu_conf; + uint32_t reg; + unsigned long lock_flags; + + dev_dbg(g_ipu_dev, "init channel = %d\n", IPU_CHAN_ID(channel)); + + if ((channel != MEM_SDC_BG) && (channel != MEM_SDC_FG) && + (channel != MEM_ROT_ENC_MEM) && (channel != MEM_ROT_VF_MEM) && + (channel != MEM_ROT_PP_MEM) && (channel != CSI_MEM) + && (params == NULL)) { + return -EINVAL; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + ipu_conf = __raw_readl(IPU_CONF); + if (ipu_conf == 0) { + clk_enable(g_ipu_clk); + } + + if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) { + dev_err(g_ipu_dev, "Warning: channel already initialized %d\n", + IPU_CHAN_ID(channel)); + } + + switch (channel) { + case CSI_PRP_VF_MEM: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW); + + if (params->mem_prp_vf_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_prpvf(params, true); + break; + case CSI_PRP_VF_ADC: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg | (FS_DEST_ADC << FS_PRPVF_DEST_SEL_OFFSET), + IPU_FS_PROC_FLOW); + + _ipu_adc_init_channel(CSI_PRP_VF_ADC, + params->csi_prp_vf_adc.disp, + WriteTemplateNonSeq, + params->csi_prp_vf_adc.out_left, + params->csi_prp_vf_adc.out_top); + + _ipu_ic_init_prpvf(params, true); + break; + case MEM_PRP_VF_MEM: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW); + + if (params->mem_prp_vf_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_prpvf(params, false); + break; + case MEM_ROT_VF_MEM: + _ipu_ic_init_rotate_vf(params); + break; + case CSI_PRP_ENC_MEM: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW); + _ipu_ic_init_prpenc(params, true); + break; + case MEM_PRP_ENC_MEM: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW); + _ipu_ic_init_prpenc(params, false); + break; + case MEM_ROT_ENC_MEM: + _ipu_ic_init_rotate_enc(params); + break; + case MEM_PP_ADC: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg | (FS_DEST_ADC << FS_PP_DEST_SEL_OFFSET), + IPU_FS_PROC_FLOW); + + _ipu_adc_init_channel(MEM_PP_ADC, params->mem_pp_adc.disp, + WriteTemplateNonSeq, + params->mem_pp_adc.out_left, + params->mem_pp_adc.out_top); + + if (params->mem_pp_adc.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_pp(params); + break; + case MEM_PP_MEM: + if (params->mem_pp_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_pp(params); + break; + case MEM_ROT_PP_MEM: + _ipu_ic_init_rotate_pp(params); + break; + case CSI_MEM: + _ipu_ic_init_csi(params); + break; + + case MEM_PF_Y_MEM: + case MEM_PF_U_MEM: + case MEM_PF_V_MEM: + /* Enable PF block */ + _ipu_pf_init(params); + break; + + case MEM_SDC_BG: + break; + case MEM_SDC_FG: + break; + case ADC_SYS1: + _ipu_adc_init_channel(ADC_SYS1, params->adc_sys1.disp, + params->adc_sys1.ch_mode, + params->adc_sys1.out_left, + params->adc_sys1.out_top); + break; + case ADC_SYS2: + _ipu_adc_init_channel(ADC_SYS2, params->adc_sys2.disp, + params->adc_sys2.ch_mode, + params->adc_sys2.out_left, + params->adc_sys2.out_top); + break; + default: + dev_err(g_ipu_dev, "Missing channel initialization\n"); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + + /* Enable IPU sub module */ + g_channel_init_mask |= 1L << IPU_CHAN_ID(channel); + + if (g_channel_init_mask & 0x00000066L) { /*CSI */ + ipu_conf |= IPU_CONF_CSI_EN; + if (cpu_is_mx31() || cpu_is_mx32()) { + g_csi_used = true; + } + } + if (g_channel_init_mask & 0x00001FFFL) { /*IC */ + ipu_conf |= IPU_CONF_IC_EN; + } + if (g_channel_init_mask & 0x00000A10L) { /*ROT */ + ipu_conf |= IPU_CONF_ROT_EN; + } + if (g_channel_init_mask & 0x0001C000L) { /*SDC */ + ipu_conf |= IPU_CONF_SDC_EN | IPU_CONF_DI_EN; + } + if (g_channel_init_mask & 0x00061140L) { /*ADC */ + ipu_conf |= IPU_CONF_ADC_EN | IPU_CONF_DI_EN; + } + if (g_channel_init_mask & 0x00380000L) { /*PF */ + ipu_conf |= IPU_CONF_PF_EN; + } + __raw_writel(ipu_conf, IPU_CONF); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +/*! + * This function is called to uninitialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to uninitalize. + */ +void ipu_uninit_channel(ipu_channel_t channel) +{ + unsigned long lock_flags; + uint32_t reg; + uint32_t dma, mask = 0; + uint32_t ipu_conf; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + dev_err(g_ipu_dev, "Channel already uninitialized %d\n", + IPU_CHAN_ID(channel)); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return; + } + + /* Make sure channel is disabled */ + /* Get input and output dma channels */ + dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + if (dma != IDMA_CHAN_INVALID) + mask |= 1UL << dma; + dma = channel_2_dma(channel, IPU_INPUT_BUFFER); + if (dma != IDMA_CHAN_INVALID) + mask |= 1UL << dma; + /* Get secondary input dma channel */ + if (g_sec_chan_en[IPU_CHAN_ID(channel)]) { + dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER); + if (dma != IDMA_CHAN_INVALID) { + mask |= 1UL << dma; + } + } + if (mask & __raw_readl(IDMAC_CHA_EN)) { + dev_err(g_ipu_dev, + "Channel %d is not disabled, disable first\n", + IPU_CHAN_ID(channel)); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return; + } + + /* Reset the double buffer */ + reg = __raw_readl(IPU_CHA_DB_MODE_SEL); + __raw_writel(reg & ~mask, IPU_CHA_DB_MODE_SEL); + + g_sec_chan_en[IPU_CHAN_ID(channel)] = false; + + switch (channel) { + case CSI_MEM: + _ipu_ic_uninit_csi(); + break; + case CSI_PRP_VF_ADC: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg & ~FS_PRPVF_DEST_SEL_MASK, IPU_FS_PROC_FLOW); + + _ipu_adc_uninit_channel(CSI_PRP_VF_ADC); + + /* Fall thru */ + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + _ipu_ic_uninit_prpvf(); + break; + case MEM_PRP_VF_ADC: + break; + case MEM_ROT_VF_MEM: + _ipu_ic_uninit_rotate_vf(); + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + _ipu_ic_uninit_prpenc(); + break; + case MEM_ROT_ENC_MEM: + _ipu_ic_uninit_rotate_enc(); + break; + case MEM_PP_ADC: + reg = __raw_readl(IPU_FS_PROC_FLOW); + __raw_writel(reg & ~FS_PP_DEST_SEL_MASK, IPU_FS_PROC_FLOW); + + _ipu_adc_uninit_channel(MEM_PP_ADC); + + /* Fall thru */ + case MEM_PP_MEM: + _ipu_ic_uninit_pp(); + break; + case MEM_ROT_PP_MEM: + _ipu_ic_uninit_rotate_pp(); + break; + + case MEM_PF_Y_MEM: + _ipu_pf_uninit(); + break; + case MEM_PF_U_MEM: + case MEM_PF_V_MEM: + break; + + case MEM_SDC_BG: + break; + case MEM_SDC_FG: + break; + case ADC_SYS1: + _ipu_adc_uninit_channel(ADC_SYS1); + break; + case ADC_SYS2: + _ipu_adc_uninit_channel(ADC_SYS2); + break; + case MEM_SDC_MASK: + case CHAN_NONE: + break; + } + + g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel)); + + ipu_conf = __raw_readl(IPU_CONF); + if ((g_channel_init_mask & 0x00000066L) == 0) { /*CSI */ + ipu_conf &= ~IPU_CONF_CSI_EN; + } + if ((g_channel_init_mask & 0x00001FFFL) == 0) { /*IC */ + ipu_conf &= ~IPU_CONF_IC_EN; + } + if ((g_channel_init_mask & 0x00000A10L) == 0) { /*ROT */ + ipu_conf &= ~IPU_CONF_ROT_EN; + } + if ((g_channel_init_mask & 0x0001C000L) == 0) { /*SDC */ + ipu_conf &= ~IPU_CONF_SDC_EN; + } + if ((g_channel_init_mask & 0x00061140L) == 0) { /*ADC */ + ipu_conf &= ~IPU_CONF_ADC_EN; + } + if ((g_channel_init_mask & 0x0007D140L) == 0) { /*DI */ + ipu_conf &= ~IPU_CONF_DI_EN; + } + if ((g_channel_init_mask & 0x00380000L) == 0) { /*PF */ + ipu_conf &= ~IPU_CONF_PF_EN; + } + __raw_writel(ipu_conf, IPU_CONF); + if (ipu_conf == 0) { + clk_disable(g_ipu_clk); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * This function is called to initialize a buffer for logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param pixel_fmt Input parameter for pixel format of buffer. Pixel + * format is a FOURCC ASCII code. + * + * @param width Input parameter for width of buffer in pixels. + * + * @param height Input parameter for height of buffer in pixels. + * + * @param stride Input parameter for stride length of buffer + * in pixels. + * + * @param rot_mode Input parameter for rotation setting of buffer. + * A rotation setting other than \b IPU_ROTATE_VERT_FLIP + * should only be used for input buffers of rotation + * channels. + * + * @param phyaddr_0 Input parameter buffer 0 physical address. + * + * @param phyaddr_1 Input parameter buffer 1 physical address. + * Setting this to a value other than NULL enables + * double buffering mode. + * + * @param u private u offset for additional cropping, + * zero if not used. + * + * @param v private v offset for additional cropping, + * zero if not used. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u, uint32_t v) +{ + uint32_t params[10]; + unsigned long lock_flags; + uint32_t reg; + uint32_t dma_chan; + + dma_chan = channel_2_dma(channel, type); + + if (stride < width * bytes_per_pixel(pixel_fmt)) + stride = width * bytes_per_pixel(pixel_fmt); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + if (stride % 4) { + dev_err(g_ipu_dev, + "Stride must be 32-bit aligned, stride = %d\n", stride); + return -EINVAL; + } + /* IC channels' width must be multiple of 8 pixels */ + if ((dma_chan <= 13) && (width % 8)) { + dev_err(g_ipu_dev, "width must be 8 pixel multiple\n"); + return -EINVAL; + } + /* Build parameter memory data for DMA channel */ + _ipu_ch_param_set_size(params, pixel_fmt, width, height, stride, u, v); + _ipu_ch_param_set_buffer(params, phyaddr_0, phyaddr_1); + _ipu_ch_param_set_rotation(params, rot_mode); + /* Some channels (rotation) have restriction on burst length */ + if ((dma_chan == 10) || (dma_chan == 11) || (dma_chan == 13)) { + _ipu_ch_param_set_burst_size(params, 8); + } else if (dma_chan == 24) { /* PF QP channel */ + _ipu_ch_param_set_burst_size(params, 4); + } else if (dma_chan == 25) { /* PF H264 BS channel */ + _ipu_ch_param_set_burst_size(params, 16); + } else if (((dma_chan == 14) || (dma_chan == 15)) && + pixel_fmt == IPU_PIX_FMT_RGB565) { + _ipu_ch_param_set_burst_size(params, 16); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + _ipu_write_param_mem(DMAParamAddr(dma_chan), params, 10); + + reg = __raw_readl(IPU_CHA_DB_MODE_SEL); + if (phyaddr_1) { + reg |= 1UL << dma_chan; + } else { + reg &= ~(1UL << dma_chan); + } + __raw_writel(reg, IPU_CHA_DB_MODE_SEL); + + /* Reset to buffer 0 */ + __raw_writel(1UL << dma_chan, IPU_CHA_CUR_BUF); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +/*! + * This function is called to update the physical address of a buffer for + * a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param bufNum Input parameter for which buffer number to update. + * 0 or 1 are the only valid values. + * + * @param phyaddr Input parameter buffer physical address. + * + * @return This function returns 0 on success or negative error code on + * fail. This function will fail if the buffer is set to ready. + */ +int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t dma_chan = channel_2_dma(channel, type); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (bufNum == 0) { + reg = __raw_readl(IPU_CHA_BUF0_RDY); + if (reg & (1UL << dma_chan)) { + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EACCES; + } + __raw_writel(DMAParamAddr(dma_chan) + 0x0008UL, IPU_IMA_ADDR); + __raw_writel(phyaddr, IPU_IMA_DATA); + } else { + reg = __raw_readl(IPU_CHA_BUF1_RDY); + if (reg & (1UL << dma_chan)) { + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EACCES; + } + __raw_writel(DMAParamAddr(dma_chan) + 0x0009UL, IPU_IMA_ADDR); + __raw_writel(phyaddr, IPU_IMA_DATA); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + dev_dbg(g_ipu_dev, "IPU: update IDMA ch %d buf %d = 0x%08X\n", + dma_chan, bufNum, phyaddr); + return 0; +} + +/*! + * This function is called to initialize a buffer for logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width Input parameter for width of buffer in pixels. + * + * @param height Input parameter for height of buffer in pixels. + * + * @param stride Input parameter for stride length of buffer + * in pixels. + * + * @param u predefined private u offset for additional cropping, + * zero if not used. + * + * @param v predefined private v offset for additional cropping, + * zero if not used. + * + * @param vertical_offset vertical offset for Y coordinate + * in the existed frame + * + * + * @param horizontal_offset horizontal offset for X coordinate + * in the existed frame + * + * + * @return Returns 0 on success or negative error code on fail + * This function will fail if any buffer is set to ready. + */ + +int32_t ipu_update_channel_offset(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset) +{ + uint32_t reg; + int ret = 0; + unsigned long lock_flags; + uint32_t dma_chan = channel_2_dma(channel, type); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + ret = -EACCES; + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return ret; +} +EXPORT_SYMBOL(ipu_update_channel_offset); + +/*! + * This function is called to set a channel's buffer as ready. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param bufNum Input parameter for which buffer number set to + * ready state. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + uint32_t dma_chan = channel_2_dma(channel, type); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + if (bufNum == 0) { + /*Mark buffer 0 as ready. */ + __raw_writel(1UL << dma_chan, IPU_CHA_BUF0_RDY); + } else { + /*Mark buffer 1 as ready. */ + __raw_writel(1UL << dma_chan, IPU_CHA_BUF1_RDY); + } + return 0; +} + +/*! + * This function check buffer ready for a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to clear. + * + * @param bufNum Input parameter for which buffer number clear + * ready state. + * + */ +int32_t ipu_check_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + uint32_t dma_chan = channel_2_dma(channel, type); + uint32_t reg; + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + if (bufNum == 0) + reg = __raw_readl(IPU_CHA_BUF0_RDY); + else + reg = __raw_readl(IPU_CHA_BUF1_RDY); + + if (reg & (1UL << dma_chan)) + return 1; + else + return 0; +} +EXPORT_SYMBOL(ipu_check_buffer_ready); + +/*! + * This function links 2 channels together for automatic frame + * synchronization. The output of the source channel is linked to the input of + * the destination channel. + * + * @param src_ch Input parameter for the logical channel ID of + * the source channel. + * + * @param dest_ch Input parameter for the logical channel ID of + * the destination channel. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch) +{ + unsigned long lock_flags; + uint32_t out_dma; + uint32_t in_dma; + bool isProc; + uint32_t value; + uint32_t mask; + uint32_t offset; + uint32_t fs_proc_flow; + uint32_t fs_disp_flow; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + fs_proc_flow = __raw_readl(IPU_FS_PROC_FLOW); + fs_disp_flow = __raw_readl(IPU_FS_DISP_FLOW); + + out_dma = (1UL << channel_2_dma(src_ch, IPU_OUTPUT_BUFFER)); + in_dma = (1UL << channel_2_dma(dest_ch, IPU_INPUT_BUFFER)); + + /* PROCESS THE OUTPUT DMA CH */ + switch (out_dma) { + /*VF-> */ + case IDMA_IC_1: + pr_debug("Link VF->"); + isProc = true; + mask = FS_PRPVF_DEST_SEL_MASK; + offset = FS_PRPVF_DEST_SEL_OFFSET; + value = (in_dma == IDMA_IC_11) ? FS_DEST_ROT : /*->VF_ROT */ + (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /* ->ADC1 */ + (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 : /* ->ADC2 */ + (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG : /*->SDC_BG */ + (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG : /*->SDC_FG */ + (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /*->ADC1 */ + /* ->ADCDirect */ + 0; + break; + + /*VF_ROT-> */ + case IDMA_IC_9: + pr_debug("Link VF_ROT->"); + isProc = true; + mask = FS_PRPVF_ROT_DEST_SEL_MASK; + offset = FS_PRPVF_ROT_DEST_SEL_OFFSET; + value = (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /*->ADC1 */ + (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 : /* ->ADC2 */ + (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG : /*->SDC_BG */ + (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG : /*->SDC_FG */ + 0; + break; + + /*ENC-> */ + case IDMA_IC_0: + pr_debug("Link ENC->"); + isProc = true; + mask = 0; + offset = 0; + value = (in_dma == IDMA_IC_10) ? FS_PRPENC_DEST_SEL : /*->ENC_ROT */ + 0; + break; + + /*PP-> */ + case IDMA_IC_2: + pr_debug("Link PP->"); + isProc = true; + mask = FS_PP_DEST_SEL_MASK; + offset = FS_PP_DEST_SEL_OFFSET; + value = (in_dma == IDMA_IC_13) ? FS_DEST_ROT : /*->PP_ROT */ + (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /* ->ADC1 */ + (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 : /* ->ADC2 */ + (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG : /*->SDC_BG */ + (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG : /*->SDC_FG */ + /* ->ADCDirect */ + 0; + break; + + /*PP_ROT-> */ + case IDMA_IC_12: + pr_debug("Link PP_ROT->"); + isProc = true; + mask = FS_PP_ROT_DEST_SEL_MASK; + offset = FS_PP_ROT_DEST_SEL_OFFSET; + value = (in_dma == IDMA_IC_5) ? FS_DEST_ROT : /*->PP */ + (in_dma == IDMA_ADC_SYS1_WR) ? FS_DEST_ADC1 : /* ->ADC1 */ + (in_dma == IDMA_ADC_SYS2_WR) ? FS_DEST_ADC2 : /* ->ADC2 */ + (in_dma == IDMA_SDC_BG) ? FS_DEST_SDC_BG : /*->SDC_BG */ + (in_dma == IDMA_SDC_FG) ? FS_DEST_SDC_FG : /*->SDC_FG */ + 0; + break; + + /*PF-> */ + case IDMA_PF_Y_OUT: + case IDMA_PF_U_OUT: + case IDMA_PF_V_OUT: + pr_debug("Link PF->"); + isProc = true; + mask = FS_PF_DEST_SEL_MASK; + offset = FS_PF_DEST_SEL_OFFSET; + value = (in_dma == IDMA_IC_5) ? FS_PF_DEST_PP : + (in_dma == IDMA_IC_13) ? FS_PF_DEST_ROT : 0; + break; + + /* Invalid Chainings: ENC_ROT-> */ + default: + pr_debug("Link Invalid->"); + value = 0; + break; + + } + + if (value) { + if (isProc) { + fs_proc_flow &= ~mask; + fs_proc_flow |= (value << offset); + } else { + fs_disp_flow &= ~mask; + fs_disp_flow |= (value << offset); + } + } else { + dev_err(g_ipu_dev, "Invalid channel chaining %d -> %d\n", + out_dma, in_dma); + return -EINVAL; + } + + /* PROCESS THE INPUT DMA CH */ + switch (in_dma) { + /* ->VF_ROT */ + case IDMA_IC_11: + pr_debug("VF_ROT\n"); + isProc = true; + mask = 0; + offset = 0; + value = (out_dma == IDMA_IC_1) ? FS_PRPVF_ROT_SRC_SEL : /*VF-> */ + 0; + break; + + /* ->ENC_ROT */ + case IDMA_IC_10: + pr_debug("ENC_ROT\n"); + isProc = true; + mask = 0; + offset = 0; + value = (out_dma == IDMA_IC_0) ? FS_PRPENC_ROT_SRC_SEL : /*ENC-> */ + 0; + break; + + /* ->PP */ + case IDMA_IC_5: + pr_debug("PP\n"); + isProc = true; + mask = FS_PP_SRC_SEL_MASK; + offset = FS_PP_SRC_SEL_OFFSET; + value = (out_dma == IDMA_PF_Y_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_PF_U_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_PF_V_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_IC_12) ? FS_PP_SRC_ROT : /*PP_ROT-> */ + 0; + break; + + /* ->PP_ROT */ + case IDMA_IC_13: + pr_debug("PP_ROT\n"); + isProc = true; + mask = FS_PP_ROT_SRC_SEL_MASK; + offset = FS_PP_ROT_SRC_SEL_OFFSET; + value = (out_dma == IDMA_PF_Y_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_PF_U_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_PF_V_OUT) ? FS_PP_SRC_PF : /*PF-> */ + (out_dma == IDMA_IC_2) ? FS_ROT_SRC_PP : /*PP-> */ + 0; + break; + + /* ->SDC_BG */ + case IDMA_SDC_BG: + pr_debug("SDC_BG\n"); + isProc = false; + mask = FS_SDC_BG_SRC_SEL_MASK; + offset = FS_SDC_BG_SRC_SEL_OFFSET; + value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF : /*VF_ROT-> */ + (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP : /*PP_ROT-> */ + (out_dma == IDMA_IC_1) ? FS_SRC_VF : /*VF-> */ + (out_dma == IDMA_IC_2) ? FS_SRC_PP : /*PP-> */ + 0; + break; + + /* ->SDC_FG */ + case IDMA_SDC_FG: + pr_debug("SDC_FG\n"); + isProc = false; + mask = FS_SDC_FG_SRC_SEL_MASK; + offset = FS_SDC_FG_SRC_SEL_OFFSET; + value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF : /*VF_ROT-> */ + (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP : /*PP_ROT-> */ + (out_dma == IDMA_IC_1) ? FS_SRC_VF : /*VF-> */ + (out_dma == IDMA_IC_2) ? FS_SRC_PP : /*PP-> */ + 0; + break; + + /* ->ADC1 */ + case IDMA_ADC_SYS1_WR: + pr_debug("ADC_SYS1\n"); + isProc = false; + mask = FS_ADC1_SRC_SEL_MASK; + offset = FS_ADC1_SRC_SEL_OFFSET; + value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF : /*VF_ROT-> */ + (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP : /*PP_ROT-> */ + (out_dma == IDMA_IC_1) ? FS_SRC_VF : /*VF-> */ + (out_dma == IDMA_IC_2) ? FS_SRC_PP : /*PP-> */ + 0; + break; + + /* ->ADC2 */ + case IDMA_ADC_SYS2_WR: + pr_debug("ADC_SYS2\n"); + isProc = false; + mask = FS_ADC2_SRC_SEL_MASK; + offset = FS_ADC2_SRC_SEL_OFFSET; + value = (out_dma == IDMA_IC_9) ? FS_SRC_ROT_VF : /*VF_ROT-> */ + (out_dma == IDMA_IC_12) ? FS_SRC_ROT_PP : /*PP_ROT-> */ + (out_dma == IDMA_IC_1) ? FS_SRC_VF : /*VF-> */ + (out_dma == IDMA_IC_2) ? FS_SRC_PP : /*PP-> */ + 0; + break; + + /*Invalid chains: */ + /* ->ENC, ->VF, ->PF, ->VF_COMBINE, ->PP_COMBINE */ + default: + pr_debug("Invalid\n"); + value = 0; + break; + + } + + if (value) { + if (isProc) { + fs_proc_flow &= ~mask; + fs_proc_flow |= (value << offset); + } else { + fs_disp_flow &= ~mask; + fs_disp_flow |= (value << offset); + } + } else { + dev_err(g_ipu_dev, "Invalid channel chaining %d -> %d\n", + out_dma, in_dma); + return -EINVAL; + } + + __raw_writel(fs_proc_flow, IPU_FS_PROC_FLOW); + __raw_writel(fs_disp_flow, IPU_FS_DISP_FLOW); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +/*! + * This function unlinks 2 channels and disables automatic frame + * synchronization. + * + * @param src_ch Input parameter for the logical channel ID of + * the source channel. + * + * @param dest_ch Input parameter for the logical channel ID of + * the destination channel. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch) +{ + unsigned long lock_flags; + uint32_t out_dma; + uint32_t in_dma; + uint32_t fs_proc_flow; + uint32_t fs_disp_flow; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + fs_proc_flow = __raw_readl(IPU_FS_PROC_FLOW); + fs_disp_flow = __raw_readl(IPU_FS_DISP_FLOW); + + out_dma = (1UL << channel_2_dma(src_ch, IPU_OUTPUT_BUFFER)); + in_dma = (1UL << channel_2_dma(dest_ch, IPU_INPUT_BUFFER)); + + /*clear the src_ch's output destination */ + switch (out_dma) { + /*VF-> */ + case IDMA_IC_1: + pr_debug("Unlink VF->"); + fs_proc_flow &= ~FS_PRPVF_DEST_SEL_MASK; + break; + + /*VF_ROT-> */ + case IDMA_IC_9: + pr_debug("Unlink VF_Rot->"); + fs_proc_flow &= ~FS_PRPVF_ROT_DEST_SEL_MASK; + break; + + /*ENC-> */ + case IDMA_IC_0: + pr_debug("Unlink ENC->"); + fs_proc_flow &= ~FS_PRPENC_DEST_SEL; + break; + + /*PP-> */ + case IDMA_IC_2: + pr_debug("Unlink PP->"); + fs_proc_flow &= ~FS_PP_DEST_SEL_MASK; + break; + + /*PP_ROT-> */ + case IDMA_IC_12: + pr_debug("Unlink PP_ROT->"); + fs_proc_flow &= ~FS_PP_ROT_DEST_SEL_MASK; + break; + + /*PF-> */ + case IDMA_PF_Y_OUT: + case IDMA_PF_U_OUT: + case IDMA_PF_V_OUT: + pr_debug("Unlink PF->"); + fs_proc_flow &= ~FS_PF_DEST_SEL_MASK; + break; + + default: /*ENC_ROT-> */ + pr_debug("Unlink Invalid->"); + break; + } + + /*clear the dest_ch's input source */ + switch (in_dma) { + /*->VF_ROT*/ + case IDMA_IC_11: + pr_debug("VF_ROT\n"); + fs_proc_flow &= ~FS_PRPVF_ROT_SRC_SEL; + break; + + /*->Enc_ROT*/ + case IDMA_IC_10: + pr_debug("ENC_ROT\n"); + fs_proc_flow &= ~FS_PRPENC_ROT_SRC_SEL; + break; + + /*->PP*/ + case IDMA_IC_5: + pr_debug("PP\n"); + fs_proc_flow &= ~FS_PP_SRC_SEL_MASK; + break; + + /*->PP_ROT*/ + case IDMA_IC_13: + pr_debug("PP_ROT\n"); + fs_proc_flow &= ~FS_PP_ROT_SRC_SEL_MASK; + break; + + /*->SDC_FG*/ + case IDMA_SDC_FG: + pr_debug("SDC_FG\n"); + fs_disp_flow &= ~FS_SDC_FG_SRC_SEL_MASK; + break; + + /*->SDC_BG*/ + case IDMA_SDC_BG: + pr_debug("SDC_BG\n"); + fs_disp_flow &= ~FS_SDC_BG_SRC_SEL_MASK; + break; + + /*->ADC1*/ + case IDMA_ADC_SYS1_WR: + pr_debug("ADC_SYS1\n"); + fs_disp_flow &= ~FS_ADC1_SRC_SEL_MASK; + break; + + /*->ADC2*/ + case IDMA_ADC_SYS2_WR: + pr_debug("ADC_SYS2\n"); + fs_disp_flow &= ~FS_ADC2_SRC_SEL_MASK; + break; + + default: /*->VF, ->ENC, ->VF_COMBINE, ->PP_COMBINE, ->PF*/ + pr_debug("Invalid\n"); + break; + } + + __raw_writel(fs_proc_flow, IPU_FS_PROC_FLOW); + __raw_writel(fs_disp_flow, IPU_FS_DISP_FLOW); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +/*! + * This function check whether a logical channel was enabled. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 1 while request channel is enabled or + * 0 for not enabled. + */ +int32_t ipu_is_channel_busy(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma; + uint32_t out_dma; + + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_INPUT_BUFFER); + + reg = __raw_readl(IDMAC_CHA_EN); + + if (reg & ((1UL << out_dma) | (1UL << in_dma))) + return 1; + return 0; +} +EXPORT_SYMBOL(ipu_is_channel_busy); + +/*! + * This function enables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_enable_channel(ipu_channel_t channel) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t in_dma; + uint32_t sec_dma; + uint32_t out_dma; + uint32_t chan_mask = 0; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IDMAC_CHA_EN); + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + if (out_dma != IDMA_CHAN_INVALID) + reg |= 1UL << out_dma; + in_dma = channel_2_dma(channel, IPU_INPUT_BUFFER); + if (in_dma != IDMA_CHAN_INVALID) + reg |= 1UL << in_dma; + + /* Get secondary input dma channel */ + if (g_sec_chan_en[IPU_CHAN_ID(channel)]) { + sec_dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER); + if (sec_dma != IDMA_CHAN_INVALID) { + reg |= 1UL << sec_dma; + } + } + + __raw_writel(reg | chan_mask, IDMAC_CHA_EN); + + if (IPU_CHAN_ID(channel) <= IPU_CHAN_ID(MEM_PP_ADC)) { + _ipu_ic_enable_task(channel); + } else if (channel == MEM_SDC_BG) { + dev_dbg(g_ipu_dev, "Initializing SDC BG\n"); + _ipu_sdc_bg_init(NULL); + } else if (channel == MEM_SDC_FG) { + dev_dbg(g_ipu_dev, "Initializing SDC FG\n"); + _ipu_sdc_fg_init(NULL); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} + +/*! + * This function clear buffer ready for a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to clear. + * + * @param bufNum Input parameter for which buffer number clear + * ready state. + * + */ +void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + /*TODO*/ +} +EXPORT_SYMBOL(ipu_clear_buffer_ready); + +uint32_t ipu_get_cur_buffer_idx(ipu_channel_t channel, ipu_buffer_t type) +{ + uint32_t reg, dma_chan; + + dma_chan = channel_2_dma(channel, type); + + reg = __raw_readl(IPU_CHA_CUR_BUF); + if (reg & (1UL << dma_chan)) + return 1; + else + return 0; +} +EXPORT_SYMBOL(ipu_get_cur_buffer_idx); + +/*! + * This function disables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param wait_for_stop Flag to set whether to wait for channel end + * of frame or return immediately. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t sec_dma; + uint32_t in_dma; + uint32_t out_dma; + uint32_t chan_mask = 0; + uint32_t timeout; + uint32_t eof_intr; + uint32_t enabled; + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + if (out_dma != IDMA_CHAN_INVALID) + chan_mask = 1UL << out_dma; + in_dma = channel_2_dma(channel, IPU_INPUT_BUFFER); + if (in_dma != IDMA_CHAN_INVALID) + chan_mask |= 1UL << in_dma; + sec_dma = channel_2_dma(channel, IPU_SEC_INPUT_BUFFER); + if (sec_dma != IDMA_CHAN_INVALID) + chan_mask |= 1UL << sec_dma; + + if (wait_for_stop && channel != MEM_SDC_FG && channel != MEM_SDC_BG) { + timeout = 40; + while ((__raw_readl(IDMAC_CHA_BUSY) & chan_mask) || + (_ipu_channel_status(channel) == TASK_STAT_ACTIVE)) { + timeout--; + msleep(10); + if (timeout == 0) { + printk + (KERN_INFO + "MXC IPU: Warning - timeout waiting for channel to stop,\n" + "\tbuf0_rdy = 0x%08X, buf1_rdy = 0x%08X\n" + "\tbusy = 0x%08X, tstat = 0x%08X\n\tmask = 0x%08X\n", + __raw_readl(IPU_CHA_BUF0_RDY), + __raw_readl(IPU_CHA_BUF1_RDY), + __raw_readl(IDMAC_CHA_BUSY), + __raw_readl(IPU_TASKS_STAT), chan_mask); + break; + } + } + dev_dbg(g_ipu_dev, "timeout = %d * 10ms\n", 40 - timeout); + } + /* SDC BG and FG must be disabled before DMA is disabled */ + if ((channel == MEM_SDC_BG) || (channel == MEM_SDC_FG)) { + + if (channel == MEM_SDC_BG) + eof_intr = IPU_IRQ_SDC_BG_EOF; + else + eof_intr = IPU_IRQ_SDC_FG_EOF; + + /* Wait for any buffer flips to finsh */ + timeout = 4; + while (timeout && + ((__raw_readl(IPU_CHA_BUF0_RDY) & chan_mask) || + (__raw_readl(IPU_CHA_BUF1_RDY) & chan_mask))) { + msleep(10); + timeout--; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + ipu_clear_irq(eof_intr); + if (channel == MEM_SDC_BG) + enabled = _ipu_sdc_bg_uninit(); + else + enabled = _ipu_sdc_fg_uninit(); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + if (enabled && wait_for_stop) { + timeout = 5; + } else { + timeout = 0; + } + while (timeout && !ipu_get_irq_status(eof_intr)) { + msleep(5); + timeout--; + } + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + /* Disable IC task */ + if (IPU_CHAN_ID(channel) <= IPU_CHAN_ID(MEM_PP_ADC)) { + _ipu_ic_disable_task(channel); + } + + /* Disable DMA channel(s) */ + reg = __raw_readl(IDMAC_CHA_EN); + __raw_writel(reg & ~chan_mask, IDMAC_CHA_EN); + + /* Clear DMA related interrupts */ + __raw_writel(chan_mask, IPU_INT_STAT_1); + __raw_writel(chan_mask, IPU_INT_STAT_2); + __raw_writel(chan_mask, IPU_INT_STAT_4); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +int32_t ipu_enable_csi(uint32_t csi) +{ + return 0; +} + + +int32_t ipu_disable_csi(uint32_t csi) +{ + return 0; +} + +static +irqreturn_t ipu_irq_handler(int irq, void *desc) +{ + uint32_t line_base = 0; + uint32_t line; + irqreturn_t result = IRQ_NONE; + uint32_t int_stat; + + int_stat = __raw_readl(IPU_INT_STAT_1); + int_stat &= __raw_readl(IPU_INT_CTRL_1); + __raw_writel(int_stat, IPU_INT_STAT_1); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + line_base = 32; + int_stat = __raw_readl(IPU_INT_STAT_2); + int_stat &= __raw_readl(IPU_INT_CTRL_2); + __raw_writel(int_stat, IPU_INT_STAT_2); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + line_base = 64; + int_stat = __raw_readl(IPU_INT_STAT_3); + int_stat &= __raw_readl(IPU_INT_CTRL_3); + __raw_writel(int_stat, IPU_INT_STAT_3); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + line_base = 96; + int_stat = __raw_readl(IPU_INT_STAT_4); + int_stat &= __raw_readl(IPU_INT_CTRL_4); + __raw_writel(int_stat, IPU_INT_STAT_4); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + line_base = 128; + int_stat = __raw_readl(IPU_INT_STAT_5); + int_stat &= __raw_readl(IPU_INT_CTRL_5); + __raw_writel(int_stat, IPU_INT_STAT_5); + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + line += line_base - 1; + result |= + ipu_irq_list[line].handler(line, ipu_irq_list[line].dev_id); + } + + return result; +} + +/*! + * This function enables the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to enable interrupt for. + * + */ +void ipu_enable_irq(uint32_t irq) +{ + uint32_t reg; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPUIRQ_2_CTRLREG(irq)); + reg |= IPUIRQ_2_MASK(irq); + __raw_writel(reg, IPUIRQ_2_CTRLREG(irq)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * This function disables the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to disable interrupt for. + * + */ +void ipu_disable_irq(uint32_t irq) +{ + uint32_t reg; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPUIRQ_2_CTRLREG(irq)); + reg &= ~IPUIRQ_2_MASK(irq); + __raw_writel(reg, IPUIRQ_2_CTRLREG(irq)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * This function clears the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to clear interrupt for. + * + */ +void ipu_clear_irq(uint32_t irq) +{ + __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); +} + +/*! + * This function returns the current interrupt status for the specified interrupt + * line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @return Returns true if the interrupt is pending/asserted or false if + * the interrupt is not pending. + */ +bool ipu_get_irq_status(uint32_t irq) +{ + uint32_t reg = __raw_readl(IPUIRQ_2_STATREG(irq)); + + if (reg & IPUIRQ_2_MASK(irq)) + return true; + else + return false; +} + +/*! + * This function registers an interrupt handler function for the specified + * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @param handler Input parameter for address of the handler + * function. + * + * @param irq_flags Flags for interrupt mode. Currently not used. + * + * @param devname Input parameter for string name of driver + * registering the handler. + * + * @param dev_id Input parameter for pointer of data to be passed + * to the handler. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int ipu_request_irq(uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id) +{ + unsigned long lock_flags; + + BUG_ON(irq >= IPU_IRQ_COUNT); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (ipu_irq_list[irq].handler != NULL) { + dev_err(g_ipu_dev, + "ipu_request_irq - handler already installed on irq %d\n", + irq); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + + ipu_irq_list[irq].handler = handler; + ipu_irq_list[irq].flags = irq_flags; + ipu_irq_list[irq].dev_id = dev_id; + ipu_irq_list[irq].name = devname; + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + ipu_enable_irq(irq); /* enable the interrupt */ + + return 0; +} + +/*! + * This function unregisters an interrupt handler for the specified interrupt + * line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @param dev_id Input parameter for pointer of data to be passed + * to the handler. This must match value passed to + * ipu_request_irq(). + * + */ +void ipu_free_irq(uint32_t irq, void *dev_id) +{ + ipu_disable_irq(irq); /* disable the interrupt */ + + if (ipu_irq_list[irq].dev_id == dev_id) { + ipu_irq_list[irq].handler = NULL; + } +} + +/*! + * This function sets the post-filter pause row for h.264 mode. + * + * @param pause_row The last row to process before pausing. + * + * @return This function returns 0 on success or negative error code on + * fail. + * + */ +int32_t ipu_pf_set_pause_row(uint32_t pause_row) +{ + int32_t retval = 0; + uint32_t timeout = 5; + unsigned long lock_flags; + uint32_t reg; + + reg = __raw_readl(IPU_TASKS_STAT); + while ((reg & TSTAT_PF_MASK) && ((reg & TSTAT_PF_H264_PAUSE) == 0)) { + timeout--; + msleep(5); + if (timeout == 0) { + dev_err(g_ipu_dev, "PF Timeout - tstat = 0x%08X\n", + __raw_readl(IPU_TASKS_STAT)); + retval = -ETIMEDOUT; + goto err0; + } + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(PF_CONF); + + /* Set the pause row */ + if (pause_row) { + reg &= ~PF_CONF_PAUSE_ROW_MASK; + reg |= PF_CONF_PAUSE_EN | pause_row << PF_CONF_PAUSE_ROW_SHIFT; + } else { + reg &= ~(PF_CONF_PAUSE_EN | PF_CONF_PAUSE_ROW_MASK); + } + __raw_writel(reg, PF_CONF); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + err0: + return retval; +} + +/* Private functions */ +void _ipu_write_param_mem(uint32_t addr, uint32_t *data, uint32_t numWords) +{ + for (; numWords > 0; numWords--) { + dev_dbg(g_ipu_dev, + "write param mem - addr = 0x%08X, data = 0x%08X\n", + addr, *data); + __raw_writel(addr, IPU_IMA_ADDR); + __raw_writel(*data++, IPU_IMA_DATA); + addr++; + if ((addr & 0x7) == 5) { + addr &= ~0x7; /* set to word 0 */ + addr += 8; /* increment to next row */ + } + } +} + +static void _ipu_pf_init(ipu_channel_params_t *params) +{ + uint32_t reg; + + /*Setup the type of filtering required */ + switch (params->mem_pf_mem.operation) { + case PF_MPEG4_DEBLOCK: + case PF_MPEG4_DERING: + case PF_MPEG4_DEBLOCK_DERING: + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = true; + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false; + break; + case PF_H264_DEBLOCK: + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = true; + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = true; + break; + default: + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = false; + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false; + return; + break; + } + reg = params->mem_pf_mem.operation; + __raw_writel(reg, PF_CONF); +} + +static void _ipu_pf_uninit(void) +{ + __raw_writel(0x0L, PF_CONF); + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_Y_MEM)] = false; + g_sec_chan_en[IPU_CHAN_ID(MEM_PF_U_MEM)] = false; +} + +uint32_t _ipu_channel_status(ipu_channel_t channel) +{ + uint32_t stat = 0; + uint32_t task_stat_reg = __raw_readl(IPU_TASKS_STAT); + + switch (channel) { + case CSI_MEM: + stat = + (task_stat_reg & TSTAT_CSI2MEM_MASK) >> + TSTAT_CSI2MEM_OFFSET; + break; + case CSI_PRP_VF_ADC: + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_ADC: + case MEM_PRP_VF_MEM: + stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET; + break; + case MEM_ROT_VF_MEM: + stat = + (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET; + break; + case MEM_ROT_ENC_MEM: + stat = + (task_stat_reg & TSTAT_ENC_ROT_MASK) >> + TSTAT_ENC_ROT_OFFSET; + break; + case MEM_PP_ADC: + case MEM_PP_MEM: + stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET; + break; + case MEM_ROT_PP_MEM: + stat = + (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET; + break; + + case MEM_PF_Y_MEM: + case MEM_PF_U_MEM: + case MEM_PF_V_MEM: + stat = (task_stat_reg & TSTAT_PF_MASK) >> TSTAT_PF_OFFSET; + break; + case MEM_SDC_BG: + break; + case MEM_SDC_FG: + break; + case ADC_SYS1: + stat = + (task_stat_reg & TSTAT_ADCSYS1_MASK) >> + TSTAT_ADCSYS1_OFFSET; + break; + case ADC_SYS2: + stat = + (task_stat_reg & TSTAT_ADCSYS2_MASK) >> + TSTAT_ADCSYS2_OFFSET; + break; + case MEM_SDC_MASK: + default: + stat = TASK_STAT_IDLE; + break; + } + return stat; +} + +uint32_t bytes_per_pixel(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: /*generic data */ + case IPU_PIX_FMT_RGB332: + case IPU_PIX_FMT_YUV420P: + case IPU_PIX_FMT_YUV422P: + return 1; + break; + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_YUYV: + case IPU_PIX_FMT_UYVY: + return 2; + break; + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + return 3; + break; + case IPU_PIX_FMT_GENERIC_32: /*generic data */ + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_ABGR32: + return 4; + break; + default: + return 1; + break; + } + return 0; +} + +void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]) +{ + /* TODO */ +} +EXPORT_SYMBOL(ipu_set_csc_coefficients); + +ipu_color_space_t format_to_colorspace(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_RGB32: + return RGB; + break; + + default: + return YCbCr; + break; + } + return RGB; + +} + +static u32 saved_disp3_time_conf; +static bool in_lpdr_mode; +static struct clk *default_ipu_parent_clk; + +int ipu_lowpwr_display_enable(void) +{ + unsigned long rate, div; + struct clk *parent_clk = g_ipu_clk; + + if (in_lpdr_mode || IS_ERR(dfm_clk)) { + return -EINVAL; + } + + if (g_channel_init_mask != (1L << IPU_CHAN_ID(MEM_SDC_BG))) { + dev_err(g_ipu_dev, "LPDR mode requires only SDC BG active.\n"); + return -EINVAL; + } + + default_ipu_parent_clk = clk_get_parent(g_ipu_clk); + in_lpdr_mode = true; + + /* Calculate current pixel clock rate */ + rate = clk_get_rate(g_ipu_clk) * 16; + saved_disp3_time_conf = __raw_readl(DI_DISP3_TIME_CONF); + div = saved_disp3_time_conf & 0xFFF; + rate /= div; + rate *= 4; /* min hsp clk is 4x pixel clk */ + + /* Initialize DFM clock */ + rate = clk_round_rate(dfm_clk, rate); + clk_set_rate(dfm_clk, rate); + clk_enable(dfm_clk); + + /* Wait for next VSYNC */ + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC), + IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)); + while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)) & + IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC)) == 0) + msleep_interruptible(1); + + /* Set display clock divider to divide by 4 */ + __raw_writel(((0x8) << 22) | 0x40, DI_DISP3_TIME_CONF); + + clk_set_parent(parent_clk, dfm_clk); + + return 0; +} + +int ipu_lowpwr_display_disable(void) +{ + struct clk *parent_clk = g_ipu_clk; + + if (!in_lpdr_mode || IS_ERR(dfm_clk)) { + return -EINVAL; + } + + if (g_channel_init_mask != (1L << IPU_CHAN_ID(MEM_SDC_BG))) { + dev_err(g_ipu_dev, "LPDR mode requires only SDC BG active.\n"); + return -EINVAL; + } + + in_lpdr_mode = false; + + /* Wait for next VSYNC */ + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC), + IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)); + while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_SDC_DISP3_VSYNC)) & + IPUIRQ_2_MASK(IPU_IRQ_SDC_DISP3_VSYNC)) == 0) + msleep_interruptible(1); + + __raw_writel(saved_disp3_time_conf, DI_DISP3_TIME_CONF); + clk_set_parent(parent_clk, default_ipu_parent_clk); + clk_disable(dfm_clk); + + return 0; +} + +static int ipu_suspend(struct platform_device *pdev, pm_message_t state) +{ + if (cpu_is_mx31() || cpu_is_mx32()) { + /* work-around for i.Mx31 SR mode after camera related test */ + if (g_csi_used) { + g_ipu_config = __raw_readl(IPU_CONF); + clk_enable(g_ipu_csi_clk); + __raw_writel(0x51, IPU_CONF); + g_channel_init_mask_backup = g_channel_init_mask; + g_channel_init_mask |= 2; + } + } else if (cpu_is_mx35()) { + g_ipu_config = __raw_readl(IPU_CONF); + /* Disable the clock of display otherwise the backlight cannot + * be close after camera/tvin related test */ + __raw_writel(g_ipu_config & 0xfbf, IPU_CONF); + } + + return 0; +} + +static int ipu_resume(struct platform_device *pdev) +{ + if (cpu_is_mx31() || cpu_is_mx32()) { + /* work-around for i.Mx31 SR mode after camera related test */ + if (g_csi_used) { + __raw_writel(g_ipu_config, IPU_CONF); + clk_disable(g_ipu_csi_clk); + g_channel_init_mask = g_channel_init_mask_backup; + } + } else if (cpu_is_mx35()) { + __raw_writel(g_ipu_config, IPU_CONF); + } + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcipu_driver = { + .driver = { + .name = "mxc_ipu", + }, + .probe = ipu_probe, + .suspend = ipu_suspend, + .resume = ipu_resume, +}; + +int32_t __init ipu_gen_init(void) +{ + int32_t ret; + + ret = platform_driver_register(&mxcipu_driver); + return 0; +} + +subsys_initcall(ipu_gen_init); + +static void __exit ipu_gen_uninit(void) +{ + if (g_ipu_irq[0]) + free_irq(g_ipu_irq[0], 0); + if (g_ipu_irq[1]) + free_irq(g_ipu_irq[1], 0); + + platform_driver_unregister(&mxcipu_driver); +} + +module_exit(ipu_gen_uninit); + +EXPORT_SYMBOL(ipu_init_channel); +EXPORT_SYMBOL(ipu_uninit_channel); +EXPORT_SYMBOL(ipu_init_channel_buffer); +EXPORT_SYMBOL(ipu_unlink_channels); +EXPORT_SYMBOL(ipu_update_channel_buffer); +EXPORT_SYMBOL(ipu_select_buffer); +EXPORT_SYMBOL(ipu_link_channels); +EXPORT_SYMBOL(ipu_enable_channel); +EXPORT_SYMBOL(ipu_disable_channel); +EXPORT_SYMBOL(ipu_enable_csi); +EXPORT_SYMBOL(ipu_disable_csi); +EXPORT_SYMBOL(ipu_enable_irq); +EXPORT_SYMBOL(ipu_disable_irq); +EXPORT_SYMBOL(ipu_clear_irq); +EXPORT_SYMBOL(ipu_get_irq_status); +EXPORT_SYMBOL(ipu_request_irq); +EXPORT_SYMBOL(ipu_free_irq); +EXPORT_SYMBOL(ipu_pf_set_pause_row); +EXPORT_SYMBOL(bytes_per_pixel); diff --git a/drivers/mxc/ipu/ipu_csi.c b/drivers/mxc/ipu/ipu_csi.c new file mode 100644 index 000000000000..6c8dd6f48c24 --- /dev/null +++ b/drivers/mxc/ipu/ipu_csi.c @@ -0,0 +1,238 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_csi.c + * + * @brief IPU CMOS Sensor interface functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" + +static bool gipu_csi_get_mclk_flag; +static int csi_mclk_flag; + +extern void gpio_sensor_suspend(bool flag); + +/*! + * ipu_csi_init_interface + * Sets initial values for the CSI registers. + * The width and height of the sensor and the actual frame size will be + * set to the same values. + * @param width Sensor width + * @param height Sensor height + * @param pixel_fmt pixel format + * @param sig ipu_csi_signal_cfg_t structure + * + * @return 0 for success, -EINVAL for error + */ +int32_t +ipu_csi_init_interface(uint16_t width, uint16_t height, uint32_t pixel_fmt, + ipu_csi_signal_cfg_t sig) +{ + uint32_t data = 0; + + /* Set SENS_DATA_FORMAT bits (8 and 9) + RGB or YUV444 is 0 which is current value in data so not set explicitly + This is also the default value if attempts are made to set it to + something invalid. */ + switch (pixel_fmt) { + case IPU_PIX_FMT_UYVY: + data = CSI_SENS_CONF_DATA_FMT_YUV422; + break; + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR24: + data = CSI_SENS_CONF_DATA_FMT_RGB_YUV444; + break; + case IPU_PIX_FMT_GENERIC: + data = CSI_SENS_CONF_DATA_FMT_BAYER; + break; + default: + return -EINVAL; + } + + /* Set the CSI_SENS_CONF register remaining fields */ + data |= sig.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT | + sig.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT | + sig.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT | + sig.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT | + sig.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT | + sig.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT | + sig.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT | + sig.sens_clksrc << CSI_SENS_CONF_SENS_CLKSRC_SHIFT; + + __raw_writel(data, CSI_SENS_CONF); + + /* Setup frame size */ + __raw_writel(width | height << 16, CSI_SENS_FRM_SIZE); + + __raw_writel(width << 16, CSI_FLASH_STROBE_1); + __raw_writel(height << 16 | 0x22, CSI_FLASH_STROBE_2); + + /* Set CCIR registers */ + if (sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) { + __raw_writel(0x40030, CSI_CCIR_CODE_1); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3); + } else if (sig.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) { + __raw_writel(0xD07DF, CSI_CCIR_CODE_1); + __raw_writel(0x40596, CSI_CCIR_CODE_2); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3); + } + + dev_dbg(g_ipu_dev, "CSI_SENS_CONF = 0x%08X\n", + __raw_readl(CSI_SENS_CONF)); + dev_dbg(g_ipu_dev, "CSI_ACT_FRM_SIZE = 0x%08X\n", + __raw_readl(CSI_ACT_FRM_SIZE)); + + return 0; +} + +/*! + * ipu_csi_flash_strobe + * + * @param flag true to turn on flash strobe + * + * @return 0 for success + */ +void ipu_csi_flash_strobe(bool flag) +{ + if (flag == true) { + __raw_writel(__raw_readl(CSI_FLASH_STROBE_2) | 0x1, + CSI_FLASH_STROBE_2); + } +} + +/*! + * ipu_csi_enable_mclk + * + * @param src enum define which source to control the clk + * CSI_MCLK_VF CSI_MCLK_ENC CSI_MCLK_RAW CSI_MCLK_I2C + * @param flag true to enable mclk, false to disable mclk + * @param wait true to wait 100ms make clock stable, false not wait + * + * @return 0 for success + */ +int32_t ipu_csi_enable_mclk(int src, bool flag, bool wait) +{ + if (flag == true) { + csi_mclk_flag |= src; + } else { + csi_mclk_flag &= ~src; + } + + if (gipu_csi_get_mclk_flag == flag) + return 0; + + if (flag == true) { + clk_enable(g_ipu_csi_clk); + if (wait == true) + msleep(10); + /*printk("enable csi clock from source %d\n", src); */ + gipu_csi_get_mclk_flag = true; + } else if (csi_mclk_flag == 0) { + clk_disable(g_ipu_csi_clk); + /*printk("disable csi clock from source %d\n", src); */ + gipu_csi_get_mclk_flag = flag; + } + + return 0; +} + +/*! + * ipu_csi_read_mclk_flag + * + * @return csi_mclk_flag + */ +int ipu_csi_read_mclk_flag(void) +{ + return csi_mclk_flag; +} + +/*! + * ipu_csi_get_window_size + * + * @param width pointer to window width + * @param height pointer to window height + * @param dummy dummy for IPUv1 to keep the same interface with IPUv3 + * + */ +void ipu_csi_get_window_size(uint32_t *width, uint32_t *height, + uint32_t dummy) +{ + uint32_t reg; + + reg = __raw_readl(CSI_ACT_FRM_SIZE); + *width = (reg & 0xFFFF) + 1; + *height = (reg >> 16 & 0xFFFF) + 1; +} + +/*! + * ipu_csi_set_window_size + * + * @param width window width + * @param height window height + * @param dummy dummy for IPUv1 to keep the same interface with IPUv3 + * + */ +void ipu_csi_set_window_size(uint32_t width, uint32_t height, uint32_t dummy) +{ + __raw_writel((width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE); +} + +/*! + * ipu_csi_set_window_pos + * + * @param left uint32 window x start + * @param top uint32 window y start + * @param dummy dummy for IPUv1 to keep the same interface with IPUv3 + * + */ +void ipu_csi_set_window_pos(uint32_t left, uint32_t top, uint32_t dummy) +{ + uint32_t temp = __raw_readl(CSI_OUT_FRM_CTRL); + temp &= 0xffff0000; + temp = top | (left << 8) | temp; + __raw_writel(temp, CSI_OUT_FRM_CTRL); +} + +/*! + * ipu_csi_get_sensor_protocol + * + * @param csi csi 0 or csi 1 + * + * @return Returns sensor protocol + */ +int32_t ipu_csi_get_sensor_protocol(uint32_t csi) +{ + /* TODO */ +} +EXPORT_SYMBOL(ipu_csi_get_sensor_protocol); + +/* Exported symbols for modules. */ +EXPORT_SYMBOL(ipu_csi_set_window_pos); +EXPORT_SYMBOL(ipu_csi_set_window_size); +EXPORT_SYMBOL(ipu_csi_get_window_size); +EXPORT_SYMBOL(ipu_csi_read_mclk_flag); +EXPORT_SYMBOL(ipu_csi_enable_mclk); +EXPORT_SYMBOL(ipu_csi_flash_strobe); +EXPORT_SYMBOL(ipu_csi_init_interface); diff --git a/drivers/mxc/ipu/ipu_device.c b/drivers/mxc/ipu/ipu_device.c new file mode 100644 index 000000000000..57314f7ebae8 --- /dev/null +++ b/drivers/mxc/ipu/ipu_device.c @@ -0,0 +1,696 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_device.c + * + * @brief This file contains the IPU driver device interface and fops functions. + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +/* Strucutures and variables for exporting MXC IPU as device*/ + +#define MAX_Q_SIZE 10 + +static int mxc_ipu_major; +static struct class *mxc_ipu_class; + +DEFINE_SPINLOCK(queue_lock); +static DECLARE_MUTEX(user_mutex); + +static wait_queue_head_t waitq; +static int pending_events; +int read_ptr; +int write_ptr; + +ipu_event_info events[MAX_Q_SIZE]; + +int register_ipu_device(void); + +/* Static functions */ + +int get_events(ipu_event_info *p) +{ + unsigned long flags; + int ret = 0, i, cnt, found = 0; + spin_lock_irqsave(&queue_lock, flags); + if (pending_events != 0) { + if (write_ptr > read_ptr) + cnt = write_ptr - read_ptr; + else + cnt = MAX_Q_SIZE - read_ptr + write_ptr; + for (i = 0; i < cnt; i++) { + if (p->irq == events[read_ptr].irq) { + *p = events[read_ptr]; + events[read_ptr].irq = 0; + read_ptr++; + if (read_ptr >= MAX_Q_SIZE) + read_ptr = 0; + found = 1; + break; + } + + if (events[read_ptr].irq) { + events[write_ptr] = events[read_ptr]; + events[read_ptr].irq = 0; + write_ptr++; + if (write_ptr >= MAX_Q_SIZE) + write_ptr = 0; + } else + pending_events--; + + read_ptr++; + if (read_ptr >= MAX_Q_SIZE) + read_ptr = 0; + } + if (found) + pending_events--; + else + ret = -1; + } else { + ret = -1; + } + + spin_unlock_irqrestore(&queue_lock, flags); + return ret; +} + +static irqreturn_t mxc_ipu_generic_handler(int irq, void *dev_id) +{ + ipu_event_info e; + + e.irq = irq; + e.dev = dev_id; + events[write_ptr] = e; + write_ptr++; + if (write_ptr >= MAX_Q_SIZE) + write_ptr = 0; + pending_events++; + /* Wakeup any blocking user context */ + wake_up_interruptible(&waitq); + return IRQ_HANDLED; +} + +static int mxc_ipu_open(struct inode *inode, struct file *file) +{ + int ret = 0; + return ret; +} +static int mxc_ipu_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + + switch (cmd) { + + case IPU_INIT_CHANNEL: + { + ipu_channel_parm parm; + if (copy_from_user + (&parm, (ipu_channel_parm *) arg, + sizeof(ipu_channel_parm))) { + return -EFAULT; + } + if (!parm.flag) { + ret = + ipu_init_channel(parm.channel, + &parm.params); + } else { + ret = ipu_init_channel(parm.channel, NULL); + } + } + break; + + case IPU_UNINIT_CHANNEL: + { + ipu_channel_t ch; + int __user *argp = (void __user *)arg; + if (get_user(ch, argp)) + return -EFAULT; + ipu_uninit_channel(ch); + } + break; + + case IPU_INIT_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) { + return -EFAULT; + } + ret = + ipu_init_channel_buffer(parm.channel, parm.type, + parm.pixel_fmt, + parm.width, parm.height, + parm.stride, + parm.rot_mode, + parm.phyaddr_0, + parm.phyaddr_1, + parm.u_offset, + parm.v_offset); + + } + break; + + case IPU_UPDATE_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) { + return -EFAULT; + } + if ((parm.phyaddr_0 != (dma_addr_t) NULL) + && (parm.phyaddr_1 == (dma_addr_t) NULL)) { + ret = + ipu_update_channel_buffer(parm.channel, + parm.type, + parm.bufNum, + parm.phyaddr_0); + } else if ((parm.phyaddr_0 == (dma_addr_t) NULL) + && (parm.phyaddr_1 != (dma_addr_t) NULL)) { + ret = + ipu_update_channel_buffer(parm.channel, + parm.type, + parm.bufNum, + parm.phyaddr_1); + } else { + ret = -1; + } + + } + break; + case IPU_SELECT_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) { + return -EFAULT; + } + ret = + ipu_select_buffer(parm.channel, parm.type, + parm.bufNum); + + } + break; + case IPU_LINK_CHANNELS: + { + ipu_channel_link link; + if (copy_from_user + (&link, (ipu_channel_link *) arg, + sizeof(ipu_channel_link))) { + return -EFAULT; + } + ret = ipu_link_channels(link.src_ch, link.dest_ch); + + } + break; + case IPU_UNLINK_CHANNELS: + { + ipu_channel_link link; + if (copy_from_user + (&link, (ipu_channel_link *) arg, + sizeof(ipu_channel_link))) { + return -EFAULT; + } + ret = ipu_unlink_channels(link.src_ch, link.dest_ch); + + } + break; + case IPU_ENABLE_CHANNEL: + { + ipu_channel_t ch; + int __user *argp = (void __user *)arg; + if (get_user(ch, argp)) + return -EFAULT; + ipu_enable_channel(ch); + } + break; + case IPU_DISABLE_CHANNEL: + { + ipu_channel_info info; + if (copy_from_user + (&info, (ipu_channel_info *) arg, + sizeof(ipu_channel_info))) { + return -EFAULT; + } + ret = ipu_disable_channel(info.channel, info.stop); + } + break; + case IPU_ENABLE_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_enable_irq(irq); + } + break; + case IPU_DISABLE_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_disable_irq(irq); + } + break; + case IPU_CLEAR_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_clear_irq(irq); + } + break; + case IPU_FREE_IRQ: + { + ipu_irq_info info; + if (copy_from_user + (&info, (ipu_irq_info *) arg, + sizeof(ipu_irq_info))) { + return -EFAULT; + } + ipu_free_irq(info.irq, info.dev_id); + } + break; + case IPU_REQUEST_IRQ_STATUS: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ret = ipu_get_irq_status(irq); + } + break; + case IPU_SDC_INIT_PANEL: + { + ipu_sdc_panel_info sinfo; + if (copy_from_user + (&sinfo, (ipu_sdc_panel_info *) arg, + sizeof(ipu_sdc_panel_info))) { + return -EFAULT; + } + ret = + ipu_sdc_init_panel(sinfo.panel, sinfo.pixel_clk, + sinfo.width, sinfo.height, + sinfo.pixel_fmt, + sinfo.hStartWidth, + sinfo.hSyncWidth, + sinfo.hEndWidth, + sinfo.vStartWidth, + sinfo.vSyncWidth, + sinfo.vEndWidth, sinfo.signal); + } + break; + case IPU_SDC_SET_WIN_POS: + { + ipu_sdc_window_pos pos; + if (copy_from_user + (&pos, (ipu_sdc_window_pos *) arg, + sizeof(ipu_sdc_window_pos))) { + return -EFAULT; + } + ret = + ipu_disp_set_window_pos(pos.channel, pos.x_pos, + pos.y_pos); + + } + break; + case IPU_SDC_SET_GLOBAL_ALPHA: + { + ipu_sdc_global_alpha g; + if (copy_from_user + (&g, (ipu_sdc_global_alpha *) arg, + sizeof(ipu_sdc_global_alpha))) { + return -EFAULT; + } + ret = ipu_sdc_set_global_alpha(g.enable, g.alpha); + } + break; + case IPU_SDC_SET_COLOR_KEY: + { + ipu_sdc_color_key c; + if (copy_from_user + (&c, (ipu_sdc_color_key *) arg, + sizeof(ipu_sdc_color_key))) { + return -EFAULT; + } + ret = + ipu_sdc_set_color_key(c.channel, c.enable, + c.colorKey); + } + break; + case IPU_SDC_SET_BRIGHTNESS: + { + uint8_t b; + int __user *argp = (void __user *)arg; + if (get_user(b, argp)) + return -EFAULT; + ret = ipu_sdc_set_brightness(b); + + } + break; + case IPU_REGISTER_GENERIC_ISR: + { + ipu_event_info info; + if (copy_from_user + (&info, (ipu_event_info *) arg, + sizeof(ipu_event_info))) { + return -EFAULT; + } + ret = + ipu_request_irq(info.irq, mxc_ipu_generic_handler, + 0, "video_sink", info.dev); + } + break; + case IPU_GET_EVENT: + /* User will have to allocate event_type structure and pass the pointer in arg */ + { + ipu_event_info info; + int r = -1; + + if (copy_from_user + (&info, (ipu_event_info *) arg, + sizeof(ipu_event_info))) + return -EFAULT; + + r = get_events(&info); + if (r == -1) { + wait_event_interruptible_timeout(waitq, + (pending_events != 0), 2 * HZ); + r = get_events(&info); + } + ret = -1; + if (r == 0) { + if (!copy_to_user((ipu_event_info *) arg, + &info, sizeof(ipu_event_info))) + ret = 0; + } + } + break; + case IPU_ADC_WRITE_TEMPLATE: + { + ipu_adc_template temp; + if (copy_from_user + (&temp, (ipu_adc_template *) arg, sizeof(temp))) { + return -EFAULT; + } + ret = + ipu_adc_write_template(temp.disp, temp.pCmd, + temp.write); + } + break; + case IPU_ADC_UPDATE: + { + ipu_adc_update update; + if (copy_from_user + (&update, (ipu_adc_update *) arg, sizeof(update))) { + return -EFAULT; + } + ret = + ipu_adc_set_update_mode(update.channel, update.mode, + update.refresh_rate, + update.addr, update.size); + } + break; + case IPU_ADC_SNOOP: + { + ipu_adc_snoop snoop; + if (copy_from_user + (&snoop, (ipu_adc_snoop *) arg, sizeof(snoop))) { + return -EFAULT; + } + ret = + ipu_adc_get_snooping_status(snoop.statl, + snoop.stath); + } + break; + case IPU_ADC_CMD: + { + ipu_adc_cmd cmd; + if (copy_from_user + (&cmd, (ipu_adc_cmd *) arg, sizeof(cmd))) { + return -EFAULT; + } + ret = + ipu_adc_write_cmd(cmd.disp, cmd.type, cmd.cmd, + cmd.params, cmd.numParams); + } + break; + case IPU_ADC_INIT_PANEL: + { + ipu_adc_panel panel; + if (copy_from_user + (&panel, (ipu_adc_panel *) arg, sizeof(panel))) { + return -EFAULT; + } + ret = + ipu_adc_init_panel(panel.disp, panel.width, + panel.height, panel.pixel_fmt, + panel.stride, panel.signal, + panel.addr, panel.vsync_width, + panel.mode); + } + break; + case IPU_ADC_IFC_TIMING: + { + ipu_adc_ifc_timing t; + if (copy_from_user + (&t, (ipu_adc_ifc_timing *) arg, sizeof(t))) { + return -EFAULT; + } + ret = + ipu_adc_init_ifc_timing(t.disp, t.read, + t.cycle_time, t.up_time, + t.down_time, + t.read_latch_time, + t.pixel_clk); + } + break; + case IPU_CSI_INIT_INTERFACE: + { + ipu_csi_interface c; + if (copy_from_user + (&c, (ipu_csi_interface *) arg, sizeof(c))) + return -EFAULT; + ret = + ipu_csi_init_interface(c.width, c.height, + c.pixel_fmt, c.signal); + } + break; + case IPU_CSI_ENABLE_MCLK: + { + ipu_csi_mclk m; + if (copy_from_user(&m, (ipu_csi_mclk *) arg, sizeof(m))) + return -EFAULT; + ret = ipu_csi_enable_mclk(m.src, m.flag, m.wait); + } + break; + case IPU_CSI_READ_MCLK_FLAG: + { + ret = ipu_csi_read_mclk_flag(); + } + break; + case IPU_CSI_FLASH_STROBE: + { + bool strobe; + int __user *argp = (void __user *)arg; + if (get_user(strobe, argp)) + return -EFAULT; + ipu_csi_flash_strobe(strobe); + } + break; + case IPU_CSI_GET_WIN_SIZE: + { + ipu_csi_window_size w; + int dummy = 0; + ipu_csi_get_window_size(&w.width, &w.height, dummy); + if (copy_to_user + ((ipu_csi_window_size *) arg, &w, sizeof(w))) + return -EFAULT; + } + break; + case IPU_CSI_SET_WIN_SIZE: + { + ipu_csi_window_size w; + int dummy = 0; + if (copy_from_user + (&w, (ipu_csi_window_size *) arg, sizeof(w))) + return -EFAULT; + ipu_csi_set_window_size(w.width, w.height, dummy); + } + break; + case IPU_CSI_SET_WINDOW: + { + ipu_csi_window p; + int dummy = 0; + if (copy_from_user + (&p, (ipu_csi_window *) arg, sizeof(p))) + return -EFAULT; + ipu_csi_set_window_pos(p.left, p.top, dummy); + } + break; + case IPU_PF_SET_PAUSE_ROW: + { + uint32_t p; + int __user *argp = (void __user *)arg; + if (get_user(p, argp)) + return -EFAULT; + ret = ipu_pf_set_pause_row(p); + } + break; + case IPU_ALOC_MEM: + { + ipu_mem_info info; + if (copy_from_user + (&info, (ipu_mem_info *) arg, + sizeof(ipu_mem_info))) + return -EFAULT; + + info.vaddr = dma_alloc_coherent(0, + PAGE_ALIGN(info.size), + &info.paddr, + GFP_DMA | GFP_KERNEL); + if (info.vaddr == 0) { + printk(KERN_ERR "dma alloc failed!\n"); + return -ENOBUFS; + } + if (copy_to_user((ipu_mem_info *) arg, &info, + sizeof(ipu_mem_info)) > 0) + return -EFAULT; + } + break; + case IPU_FREE_MEM: + { + ipu_mem_info info; + if (copy_from_user + (&info, (ipu_mem_info *) arg, + sizeof(ipu_mem_info))) + return -EFAULT; + + if (info.vaddr != 0) + dma_free_coherent(0, PAGE_ALIGN(info.size), + info.vaddr, info.paddr); + else + return -EFAULT; + } + break; + case IPU_IS_CHAN_BUSY: + { + ipu_channel_t chan; + if (copy_from_user + (&chan, (ipu_channel_t *)arg, + sizeof(ipu_channel_t))) + return -EFAULT; + + if (ipu_is_channel_busy(chan)) + ret = 1; + else + ret = 0; + } + break; + default: + break; + + } + return ret; +} + +static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma) +{ + vma->vm_page_prot = pgprot_writethru(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) { + printk(KERN_ERR + "mmap failed!\n"); + return -ENOBUFS; + } + return 0; +} + +static int mxc_ipu_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static struct file_operations mxc_ipu_fops = { + .owner = THIS_MODULE, + .open = mxc_ipu_open, + .mmap = mxc_ipu_mmap, + .release = mxc_ipu_release, + .ioctl = mxc_ipu_ioctl +}; + +int register_ipu_device() +{ + int ret = 0; + struct device *temp; + mxc_ipu_major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops); + if (mxc_ipu_major < 0) { + printk(KERN_ERR + "Unable to register Mxc Ipu as a char device\n"); + return mxc_ipu_major; + } + + mxc_ipu_class = class_create(THIS_MODULE, "mxc_ipu"); + if (IS_ERR(mxc_ipu_class)) { + printk(KERN_ERR "Unable to create class for Mxc Ipu\n"); + ret = PTR_ERR(mxc_ipu_class); + goto err1; + } + + temp = device_create(mxc_ipu_class, NULL, MKDEV(mxc_ipu_major, 0), NULL, + "mxc_ipu"); + + if (IS_ERR(temp)) { + printk(KERN_ERR "Unable to create class device for Mxc Ipu\n"); + ret = PTR_ERR(temp); + goto err2; + } + spin_lock_init(&queue_lock); + init_waitqueue_head(&waitq); + return ret; + + err2: + class_destroy(mxc_ipu_class); + err1: + unregister_chrdev(mxc_ipu_major, "mxc_ipu"); + return ret; + +} diff --git a/drivers/mxc/ipu/ipu_ic.c b/drivers/mxc/ipu/ipu_ic.c new file mode 100644 index 000000000000..28f002fc2e53 --- /dev/null +++ b/drivers/mxc/ipu/ipu_ic.c @@ -0,0 +1,590 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_ic.c + * + * @brief IPU IC functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +enum { + IC_TASK_VIEWFINDER, + IC_TASK_ENCODER, + IC_TASK_POST_PROCESSOR +}; + +extern int g_ipu_hw_rev; +static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format, + ipu_color_space_t out_format); +static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize, + uint32_t *resizeCoeff, + uint32_t *downsizeCoeff); + +void _ipu_ic_enable_task(ipu_channel_t channel) +{ + uint32_t ic_conf; + + ic_conf = __raw_readl(IC_CONF); + switch (channel) { + case CSI_PRP_VF_ADC: + case MEM_PRP_VF_ADC: + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + ic_conf |= IC_CONF_PRPVF_EN; + break; + case MEM_ROT_VF_MEM: + ic_conf |= IC_CONF_PRPVF_ROT_EN; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + ic_conf |= IC_CONF_PRPENC_EN; + break; + case MEM_ROT_ENC_MEM: + ic_conf |= IC_CONF_PRPENC_ROT_EN; + break; + case MEM_PP_ADC: + case MEM_PP_MEM: + ic_conf |= IC_CONF_PP_EN; + break; + case MEM_ROT_PP_MEM: + ic_conf |= IC_CONF_PP_ROT_EN; + break; + case CSI_MEM: + ic_conf |= IC_CONF_RWS_EN | IC_CONF_PRPENC_EN; + break; + default: + break; + } + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_disable_task(ipu_channel_t channel) +{ + uint32_t ic_conf; + + ic_conf = __raw_readl(IC_CONF); + switch (channel) { + case CSI_PRP_VF_ADC: + case MEM_PRP_VF_ADC: + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_EN; + break; + case MEM_ROT_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_ROT_EN; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + ic_conf &= ~IC_CONF_PRPENC_EN; + break; + case MEM_ROT_ENC_MEM: + ic_conf &= ~IC_CONF_PRPENC_ROT_EN; + break; + case MEM_PP_ADC: + case MEM_PP_MEM: + ic_conf &= ~IC_CONF_PP_EN; + break; + case MEM_ROT_PP_MEM: + ic_conf &= ~IC_CONF_PP_ROT_EN; + break; + case CSI_MEM: + ic_conf &= ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN); + break; + default: + break; + } + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_prp_vf_mem.in_height, + params->mem_prp_vf_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_prp_vf_mem.in_width, + params->mem_prp_vf_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PRP_VF_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + _init_csc(IC_TASK_VIEWFINDER, RGB, out_fmt); + ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->YCBCR CSC */ + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + _init_csc(IC_TASK_VIEWFINDER, YCbCr, RGB); + ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable YCBCR->RGB CSC */ + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_prp_vf_mem.graphics_combine_en) { + ic_conf |= IC_CONF_PRPVF_CMB; + + /* need transparent CSC1 conversion */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB); + ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->RGB CSC */ + + if (params->mem_prp_vf_mem.global_alpha_en) { + ic_conf |= IC_CONF_IC_GLB_LOC_A; + } else { + ic_conf &= ~IC_CONF_IC_GLB_LOC_A; + } + + if (params->mem_prp_vf_mem.key_color_en) { + ic_conf |= IC_CONF_KEY_COLOR_EN; + } else { + ic_conf &= ~IC_CONF_KEY_COLOR_EN; + } + } else { + ic_conf &= ~IC_CONF_PP_CMB; + } + +#ifndef CONFIG_VIRTIO_SUPPORT /* Setting RWS_EN doesn't work in Virtio */ + if (src_is_csi) { + ic_conf &= ~IC_CONF_RWS_EN; + } else { + ic_conf |= IC_CONF_RWS_EN; + } +#endif + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_prpvf(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB | + IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_vf(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_vf(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_PRPVF_ROT_EN; + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_csi(ipu_channel_params_t *params) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_CSI_MEM_WR_EN; + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_uninit_csi(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_prp_enc_mem.in_height, + params->mem_prp_enc_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_prp_enc_mem.in_width, + params->mem_prp_enc_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PRP_ENC_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* TODO: ERROR! */ + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + _init_csc(IC_TASK_ENCODER, YCbCr, RGB); + ic_conf |= IC_CONF_PRPENC_CSC1; /* Enable YCBCR->RGB CSC */ + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (src_is_csi) { + ic_conf &= ~IC_CONF_RWS_EN; + } else { + ic_conf |= IC_CONF_RWS_EN; + } + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_prpenc(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_enc(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_enc(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPENC_ROT_EN); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_pp(ipu_channel_params_t *params) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_pp_mem.in_height, + params->mem_pp_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + _calc_resize_coeffs(params->mem_pp_mem.in_width, + params->mem_pp_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + + __raw_writel(reg, IC_PP_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + _init_csc(IC_TASK_POST_PROCESSOR, RGB, out_fmt); + ic_conf |= IC_CONF_PP_CSC2; /* Enable RGB->YCBCR CSC */ + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + _init_csc(IC_TASK_POST_PROCESSOR, YCbCr, RGB); + ic_conf |= IC_CONF_PP_CSC1; /* Enable YCBCR->RGB CSC */ + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_pp_mem.graphics_combine_en) { + ic_conf |= IC_CONF_PP_CMB; + + /* need transparent CSC1 conversion */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB); + ic_conf |= IC_CONF_PP_CSC1; /* Enable RGB->RGB CSC */ + + if (params->mem_pp_mem.global_alpha_en) { + ic_conf |= IC_CONF_IC_GLB_LOC_A; + } else { + ic_conf &= ~IC_CONF_IC_GLB_LOC_A; + } + + if (params->mem_pp_mem.key_color_en) { + ic_conf |= IC_CONF_KEY_COLOR_EN; + } else { + ic_conf &= ~IC_CONF_KEY_COLOR_EN; + } + } else { + ic_conf &= ~IC_CONF_PP_CMB; + } + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_pp(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 | + IC_CONF_PP_CMB); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_pp(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_pp(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_PP_ROT_EN; + __raw_writel(reg, IC_CONF); +} + +static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format, + ipu_color_space_t out_format) +{ +/* Y = R * .299 + G * .587 + B * .114; + U = R * -.169 + G * -.332 + B * .500 + 128.; + V = R * .500 + G * -.419 + B * -.0813 + 128.;*/ + static const uint32_t rgb2ycbcr_coeff[4][3] = { + {0x004D, 0x0096, 0x001D}, + {0x01D5, 0x01AB, 0x0080}, + {0x0080, 0x0195, 0x01EB}, + {0x0000, 0x0200, 0x0200}, /* A0, A1, A2 */ + }; + + /* transparent RGB->RGB matrix for combining + */ + static const uint32_t rgb2rgb_coeff[4][3] = { + {0x0080, 0x0000, 0x0000}, + {0x0000, 0x0080, 0x0000}, + {0x0000, 0x0000, 0x0080}, + {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */ + }; + +/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); + G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); + B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */ + static const uint32_t ycbcr2rgb_coeff[4][3] = { + {149, 0, 204}, + {149, 462, 408}, + {149, 255, 0}, + {8192 - 446, 266, 8192 - 554}, /* A0, A1, A2 */ + }; + + uint32_t param[2]; + uint32_t address = 0; + + if (g_ipu_hw_rev > 1) { + if (ic_task == IC_TASK_VIEWFINDER) { + address = 0x645 << 3; + } else if (ic_task == IC_TASK_ENCODER) { + address = 0x321 << 3; + } else if (ic_task == IC_TASK_POST_PROCESSOR) { + address = 0x96C << 3; + } else { + BUG(); + } + } else { + if (ic_task == IC_TASK_VIEWFINDER) { + address = 0x5a5 << 3; + } else if (ic_task == IC_TASK_ENCODER) { + address = 0x2d1 << 3; + } else if (ic_task == IC_TASK_POST_PROCESSOR) { + address = 0x87c << 3; + } else { + BUG(); + } + } + + if ((in_format == YCbCr) && (out_format == RGB)) { + /* Init CSC1 (YCbCr->RGB) */ + param[0] = + (ycbcr2rgb_coeff[3][0] << 27) | (ycbcr2rgb_coeff[0][0] << + 18) | + (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2]; + /* scale = 2, sat = 0 */ + param[1] = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32)); + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (ycbcr2rgb_coeff[3][1] << 27) | (ycbcr2rgb_coeff[0][1] << + 18) | + (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0]; + param[1] = (ycbcr2rgb_coeff[3][1] >> 5); + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (ycbcr2rgb_coeff[3][2] << 27) | (ycbcr2rgb_coeff[0][2] << + 18) | + (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1]; + param[1] = (ycbcr2rgb_coeff[3][2] >> 5); + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + } else if ((in_format == RGB) && (out_format == YCbCr)) { + /* Init CSC1 (RGB->YCbCr) */ + param[0] = + (rgb2ycbcr_coeff[3][0] << 27) | (rgb2ycbcr_coeff[0][0] << + 18) | + (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2]; + /* scale = 1, sat = 0 */ + param[1] = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8); + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (rgb2ycbcr_coeff[3][1] << 27) | (rgb2ycbcr_coeff[0][1] << + 18) | + (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0]; + param[1] = (rgb2ycbcr_coeff[3][1] >> 5); + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (rgb2ycbcr_coeff[3][2] << 27) | (rgb2ycbcr_coeff[0][2] << + 18) | + (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1]; + param[1] = (rgb2ycbcr_coeff[3][2] >> 5); + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + } else if ((in_format == RGB) && (out_format == RGB)) { + /* Init CSC1 */ + param[0] = + (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) | + (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2]; + /* scale = 2, sat = 0 */ + param[1] = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8); + + _ipu_write_param_mem(address, param, 2); + + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) | + (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0]; + param[1] = (rgb2rgb_coeff[3][1] >> 5); + + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + + param[0] = + (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) | + (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1]; + param[1] = (rgb2rgb_coeff[3][2] >> 5); + + address += 1L << 3; + _ipu_write_param_mem(address, param, 2); + + dev_dbg(g_ipu_dev, + "addr 0x%04X: word0 = 0x%08X, word1 = 0x%08X\n", + address, param[0], param[1]); + } else { + dev_err(g_ipu_dev, "Unsupported color space conversion\n"); + } +} + +static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize, + uint32_t *resizeCoeff, + uint32_t *downsizeCoeff) +{ + uint32_t tempSize; + uint32_t tempDownsize; + + /* Cannot downsize more than 8:1 */ + if ((outSize << 3) < inSize) { + return false; + } + /* compute downsizing coefficient */ + tempDownsize = 0; + tempSize = inSize; + while ((tempSize >= outSize * 2) && (tempDownsize < 2)) { + tempSize >>= 1; + tempDownsize++; + } + *downsizeCoeff = tempDownsize; + + /* compute resizing coefficient using the following equation: + resizeCoeff = M*(SI -1)/(SO - 1) + where M = 2^13, SI - input size, SO - output size */ + *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1); + if (*resizeCoeff >= 16384L) { + dev_err(g_ipu_dev, "Warning! Overflow on resize coeff.\n"); + *resizeCoeff = 0x3FFF; + } + + dev_dbg(g_ipu_dev, "resizing from %u -> %u pixels, " + "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize, + *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0, + ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff); + + return true; +} diff --git a/drivers/mxc/ipu/ipu_param_mem.h b/drivers/mxc/ipu/ipu_param_mem.h new file mode 100644 index 000000000000..4f2d5cba6e42 --- /dev/null +++ b/drivers/mxc/ipu/ipu_param_mem.h @@ -0,0 +1,176 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_IPU_PARAM_MEM_H__ +#define __INCLUDE_IPU_PARAM_MEM_H__ + +#include + +static __inline void _ipu_ch_param_set_size(uint32_t *params, + uint32_t pixel_fmt, uint16_t width, + uint16_t height, uint16_t stride, + uint32_t u, uint32_t v) +{ + uint32_t u_offset = 0; + uint32_t v_offset = 0; + memset(params, 0, 40); + + params[3] = + (uint32_t) ((width - 1) << 12) | ((uint32_t) (height - 1) << 24); + params[4] = (uint32_t) (height - 1) >> 8; + params[7] = (uint32_t) (stride - 1) << 3; + + switch (pixel_fmt) { + case IPU_PIX_FMT_GENERIC: + /*Represents 8-bit Generic data */ + params[7] |= 3 | (7UL << (81 - 64)) | (31L << (89 - 64)); /* BPP & PFS */ + params[8] = 2; /* SAT = use 32-bit access */ + break; + case IPU_PIX_FMT_GENERIC_32: + /*Represents 32-bit Generic data */ + params[7] |= (7UL << (81 - 64)) | (7L << (89 - 64)); /* BPP & PFS */ + params[8] = 2; /* SAT = use 32-bit access */ + break; + case IPU_PIX_FMT_RGB565: + params[7] |= 2L | (4UL << (81 - 64)) | (7L << (89 - 64)); /* BPP & PFS */ + params[8] = 2 | /* SAT = 32-bit access */ + (0UL << (99 - 96)) | /* Red bit offset */ + (5UL << (104 - 96)) | /* Green bit offset */ + (11UL << (109 - 96)) | /* Blue bit offset */ + (16UL << (114 - 96)) | /* Alpha bit offset */ + (4UL << (119 - 96)) | /* Red bit width - 1 */ + (5UL << (122 - 96)) | /* Green bit width - 1 */ + (4UL << (125 - 96)); /* Blue bit width - 1 */ + break; + case IPU_PIX_FMT_BGR24: /* 24 BPP & RGB PFS */ + params[7] |= 1 | (4UL << (81 - 64)) | (7L << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (8UL << (104 - 96)) | /* Green bit offset */ + (16UL << (109 - 96)) | /* Blue bit offset */ + (24UL << (114 - 96)) | /* Alpha bit offset */ + (7UL << (119 - 96)) | /* Red bit width - 1 */ + (7UL << (122 - 96)) | /* Green bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Blue bit width - 1 */ + break; + case IPU_PIX_FMT_RGB24: /* 24 BPP & RGB PFS */ + params[7] |= 1 | (4UL << (81 - 64)) | (7L << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (16UL << (99 - 96)) | /* Red bit offset */ + (8UL << (104 - 96)) | /* Green bit offset */ + (0UL << (109 - 96)) | /* Blue bit offset */ + (24UL << (114 - 96)) | /* Alpha bit offset */ + (7UL << (119 - 96)) | /* Red bit width - 1 */ + (7UL << (122 - 96)) | /* Green bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Blue bit width - 1 */ + break; + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_BGR32: + /* BPP & pixel fmt */ + params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (8UL << (99 - 96)) | /* Red bit offset */ + (16UL << (104 - 96)) | /* Green bit offset */ + (24UL << (109 - 96)) | /* Blue bit offset */ + (0UL << (114 - 96)) | /* Alpha bit offset */ + (7UL << (119 - 96)) | /* Red bit width - 1 */ + (7UL << (122 - 96)) | /* Green bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Blue bit width - 1 */ + params[9] = 7; /* Alpha bit width - 1 */ + break; + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_RGB32: + /* BPP & pixel fmt */ + params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (24UL << (99 - 96)) | /* Red bit offset */ + (16UL << (104 - 96)) | /* Green bit offset */ + (8UL << (109 - 96)) | /* Blue bit offset */ + (0UL << (114 - 96)) | /* Alpha bit offset */ + (7UL << (119 - 96)) | /* Red bit width - 1 */ + (7UL << (122 - 96)) | /* Green bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Blue bit width - 1 */ + params[9] = 7; /* Alpha bit width - 1 */ + break; + case IPU_PIX_FMT_ABGR32: + /* BPP & pixel fmt */ + params[7] |= 0 | (4UL << (81 - 64)) | (7 << (89 - 64)); + params[8] = 2 | /* SAT = 32-bit access */ + (0UL << (99 - 96)) | /* Alpha bit offset */ + (8UL << (104 - 96)) | /* Blue bit offset */ + (16UL << (109 - 96)) | /* Green bit offset */ + (24UL << (114 - 96)) | /* Red bit offset */ + (7UL << (119 - 96)) | /* Alpha bit width - 1 */ + (7UL << (122 - 96)) | /* Blue bit width - 1 */ + (uint32_t) (7UL << (125 - 96)); /* Green bit width - 1 */ + params[9] = 7; /* Red bit width - 1 */ + break; + case IPU_PIX_FMT_UYVY: + /* BPP & pixel format */ + params[7] |= 2 | (6UL << 17) | (7 << (89 - 64)); + params[8] = 2; /* SAT = 32-bit access */ + break; + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + /* BPP & pixel format */ + params[7] |= 3 | (3UL << 17) | (7 << (89 - 64)); + params[8] = 2; /* SAT = 32-bit access */ + u_offset = (u == 0) ? stride * height : u; + v_offset = (v == 0) ? u_offset + u_offset / 4 : v; + break; + case IPU_PIX_FMT_YVU422P: + /* BPP & pixel format */ + params[7] |= 3 | (2UL << 17) | (7 << (89 - 64)); + params[8] = 2; /* SAT = 32-bit access */ + v_offset = (v == 0) ? stride * height : v; + u_offset = (u == 0) ? v_offset + v_offset / 2 : u; + break; + case IPU_PIX_FMT_YUV422P: + /* BPP & pixel format */ + params[7] |= 3 | (2UL << 17) | (7 << (89 - 64)); + params[8] = 2; /* SAT = 32-bit access */ + u_offset = (u == 0) ? stride * height : u; + v_offset = (v == 0) ? u_offset + u_offset / 2 : v; + break; + default: + dev_err(g_ipu_dev, "mxc ipu: unimplemented pixel format\n"); + break; + } + + params[1] = (1UL << (46 - 32)) | (u_offset << (53 - 32)); + params[2] = u_offset >> (64 - 53); + params[2] |= v_offset << (79 - 64); + params[3] |= v_offset >> (96 - 79); +} + +static __inline void _ipu_ch_param_set_burst_size(uint32_t *params, + uint16_t burst_pixels) +{ + params[7] &= ~(0x3FL << (89 - 64)); + params[7] |= (uint32_t) (burst_pixels - 1) << (89 - 64); +}; + +static __inline void _ipu_ch_param_set_buffer(uint32_t *params, + dma_addr_t buf0, dma_addr_t buf1) +{ + params[5] = buf0; + params[6] = buf1; +}; + +static __inline void _ipu_ch_param_set_rotation(uint32_t *params, + ipu_rotate_mode_t rot) +{ + params[7] |= (uint32_t) rot << (84 - 64); +}; + +void _ipu_write_param_mem(uint32_t addr, uint32_t *data, uint32_t numWords); + +#endif diff --git a/drivers/mxc/ipu/ipu_prv.h b/drivers/mxc/ipu/ipu_prv.h new file mode 100644 index 000000000000..03450de968e6 --- /dev/null +++ b/drivers/mxc/ipu/ipu_prv.h @@ -0,0 +1,59 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_IPU_PRV_H__ +#define __INCLUDE_IPU_PRV_H__ + +#include +#include +#include +#include +#include + +/* Globals */ +extern struct device *g_ipu_dev; +extern spinlock_t ipu_lock; +extern struct clk *g_ipu_clk; +extern struct clk *g_ipu_csi_clk; + +int register_ipu_device(void); +ipu_color_space_t format_to_colorspace(uint32_t fmt); + +uint32_t _ipu_channel_status(ipu_channel_t channel); + +void _ipu_sdc_fg_init(ipu_channel_params_t *params); +uint32_t _ipu_sdc_fg_uninit(void); +void _ipu_sdc_bg_init(ipu_channel_params_t *params); +uint32_t _ipu_sdc_bg_uninit(void); + +void _ipu_ic_enable_task(ipu_channel_t channel); +void _ipu_ic_disable_task(ipu_channel_t channel); +void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi); +void _ipu_ic_uninit_prpvf(void); +void _ipu_ic_init_rotate_vf(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_vf(void); +void _ipu_ic_init_csi(ipu_channel_params_t *params); +void _ipu_ic_uninit_csi(void); +void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi); +void _ipu_ic_uninit_prpenc(void); +void _ipu_ic_init_rotate_enc(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_enc(void); +void _ipu_ic_init_pp(ipu_channel_params_t *params); +void _ipu_ic_uninit_pp(void); +void _ipu_ic_init_rotate_pp(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_pp(void); + +int32_t _ipu_adc_init_channel(ipu_channel_t chan, display_port_t disp, + mcu_mode_t cmd, int16_t x_pos, int16_t y_pos); +int32_t _ipu_adc_uninit_channel(ipu_channel_t chan); + +#endif /* __INCLUDE_IPU_PRV_H__ */ diff --git a/drivers/mxc/ipu/ipu_regs.h b/drivers/mxc/ipu/ipu_regs.h new file mode 100644 index 000000000000..d78df52a9785 --- /dev/null +++ b/drivers/mxc/ipu/ipu_regs.h @@ -0,0 +1,396 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_regs.h + * + * @brief IPU Register definitions + * + * @ingroup IPU + */ +#ifndef __IPU_REGS_INCLUDED__ +#define __IPU_REGS_INCLUDED__ + +#define IPU_REG_BASE IO_ADDRESS(IPU_CTRL_BASE_ADDR) + +/* Register addresses */ +/* IPU Common registers */ +#define IPU_CONF (IPU_REG_BASE + 0x0000) +#define IPU_CHA_BUF0_RDY (IPU_REG_BASE + 0x0004) +#define IPU_CHA_BUF1_RDY (IPU_REG_BASE + 0x0008) +#define IPU_CHA_DB_MODE_SEL (IPU_REG_BASE + 0x000C) +#define IPU_CHA_CUR_BUF (IPU_REG_BASE + 0x0010) +#define IPU_FS_PROC_FLOW (IPU_REG_BASE + 0x0014) +#define IPU_FS_DISP_FLOW (IPU_REG_BASE + 0x0018) +#define IPU_TASKS_STAT (IPU_REG_BASE + 0x001C) +#define IPU_IMA_ADDR (IPU_REG_BASE + 0x0020) +#define IPU_IMA_DATA (IPU_REG_BASE + 0x0024) +#define IPU_INT_CTRL_1 (IPU_REG_BASE + 0x0028) +#define IPU_INT_CTRL_2 (IPU_REG_BASE + 0x002C) +#define IPU_INT_CTRL_3 (IPU_REG_BASE + 0x0030) +#define IPU_INT_CTRL_4 (IPU_REG_BASE + 0x0034) +#define IPU_INT_CTRL_5 (IPU_REG_BASE + 0x0038) +#define IPU_INT_STAT_1 (IPU_REG_BASE + 0x003C) +#define IPU_INT_STAT_2 (IPU_REG_BASE + 0x0040) +#define IPU_INT_STAT_3 (IPU_REG_BASE + 0x0044) +#define IPU_INT_STAT_4 (IPU_REG_BASE + 0x0048) +#define IPU_INT_STAT_5 (IPU_REG_BASE + 0x004C) +#define IPU_BRK_CTRL_1 (IPU_REG_BASE + 0x0050) +#define IPU_BRK_CTRL_2 (IPU_REG_BASE + 0x0054) +#define IPU_BRK_STAT (IPU_REG_BASE + 0x0058) +#define IPU_DIAGB_CTRL (IPU_REG_BASE + 0x005C) +/* CMOS Sensor Interface Registers */ +#define CSI_SENS_CONF (IPU_REG_BASE + 0x0060) +#define CSI_SENS_FRM_SIZE (IPU_REG_BASE + 0x0064) +#define CSI_ACT_FRM_SIZE (IPU_REG_BASE + 0x0068) +#define CSI_OUT_FRM_CTRL (IPU_REG_BASE + 0x006C) +#define CSI_TST_CTRL (IPU_REG_BASE + 0x0070) +#define CSI_CCIR_CODE_1 (IPU_REG_BASE + 0x0074) +#define CSI_CCIR_CODE_2 (IPU_REG_BASE + 0x0078) +#define CSI_CCIR_CODE_3 (IPU_REG_BASE + 0x007C) +#define CSI_FLASH_STROBE_1 (IPU_REG_BASE + 0x0080) +#define CSI_FLASH_STROBE_2 (IPU_REG_BASE + 0x0084) +/* Image Converter Registers */ +#define IC_CONF (IPU_REG_BASE + 0x0088) +#define IC_PRP_ENC_RSC (IPU_REG_BASE + 0x008C) +#define IC_PRP_VF_RSC (IPU_REG_BASE + 0x0090) +#define IC_PP_RSC (IPU_REG_BASE + 0x0094) +#define IC_CMBP_1 (IPU_REG_BASE + 0x0098) +#define IC_CMBP_2 (IPU_REG_BASE + 0x009C) +#define PF_CONF (IPU_REG_BASE + 0x00A0) +#define IDMAC_CONF (IPU_REG_BASE + 0x00A4) +#define IDMAC_CHA_EN (IPU_REG_BASE + 0x00A8) +#define IDMAC_CHA_PRI (IPU_REG_BASE + 0x00AC) +#define IDMAC_CHA_BUSY (IPU_REG_BASE + 0x00B0) +/* SDC Registers */ +#define SDC_COM_CONF (IPU_REG_BASE + 0x00B4) +#define SDC_GW_CTRL (IPU_REG_BASE + 0x00B8) +#define SDC_FG_POS (IPU_REG_BASE + 0x00BC) +#define SDC_BG_POS (IPU_REG_BASE + 0x00C0) +#define SDC_CUR_POS (IPU_REG_BASE + 0x00C4) +#define SDC_PWM_CTRL (IPU_REG_BASE + 0x00C8) +#define SDC_CUR_MAP (IPU_REG_BASE + 0x00CC) +#define SDC_HOR_CONF (IPU_REG_BASE + 0x00D0) +#define SDC_VER_CONF (IPU_REG_BASE + 0x00D4) +#define SDC_SHARP_CONF_1 (IPU_REG_BASE + 0x00D8) +#define SDC_SHARP_CONF_2 (IPU_REG_BASE + 0x00DC) +/* ADC Registers */ +#define ADC_CONF (IPU_REG_BASE + 0x00E0) +#define ADC_SYSCHA1_SA (IPU_REG_BASE + 0x00E4) +#define ADC_SYSCHA2_SA (IPU_REG_BASE + 0x00E8) +#define ADC_PRPCHAN_SA (IPU_REG_BASE + 0x00EC) +#define ADC_PPCHAN_SA (IPU_REG_BASE + 0x00F0) +#define ADC_DISP0_CONF (IPU_REG_BASE + 0x00F4) +#define ADC_DISP0_RD_AP (IPU_REG_BASE + 0x00F8) +#define ADC_DISP0_RDM (IPU_REG_BASE + 0x00FC) +#define ADC_DISP0_SS (IPU_REG_BASE + 0x0100) +#define ADC_DISP1_CONF (IPU_REG_BASE + 0x0104) +#define ADC_DISP1_RD_AP (IPU_REG_BASE + 0x0108) +#define ADC_DISP1_RDM (IPU_REG_BASE + 0x010C) +#define ADC_DISP12_SS (IPU_REG_BASE + 0x0110) +#define ADC_DISP2_CONF (IPU_REG_BASE + 0x0114) +#define ADC_DISP2_RD_AP (IPU_REG_BASE + 0x0118) +#define ADC_DISP2_RDM (IPU_REG_BASE + 0x011C) +#define ADC_DISP_VSYNC (IPU_REG_BASE + 0x0120) +/* Display Interface re(sters */ +#define DI_DISP_IF_CONF (IPU_REG_BASE + 0x0124) +#define DI_DISP_SIG_POL (IPU_REG_BASE + 0x0128) +#define DI_SER_DISP1_CONF (IPU_REG_BASE + 0x012C) +#define DI_SER_DISP2_CONF (IPU_REG_BASE + 0x0130) +#define DI_HSP_CLK_PER (IPU_REG_BASE + 0x0134) +#define DI_DISP0_TIME_CONF_1 (IPU_REG_BASE + 0x0138) +#define DI_DISP0_TIME_CONF_2 (IPU_REG_BASE + 0x013C) +#define DI_DISP0_TIME_CONF_3 (IPU_REG_BASE + 0x0140) +#define DI_DISP1_TIME_CONF_1 (IPU_REG_BASE + 0x0144) +#define DI_DISP1_TIME_CONF_2 (IPU_REG_BASE + 0x0148) +#define DI_DISP1_TIME_CONF_3 (IPU_REG_BASE + 0x014C) +#define DI_DISP2_TIME_CONF_1 (IPU_REG_BASE + 0x0150) +#define DI_DISP2_TIME_CONF_2 (IPU_REG_BASE + 0x0154) +#define DI_DISP2_TIME_CONF_3 (IPU_REG_BASE + 0x0158) +#define DI_DISP3_TIME_CONF (IPU_REG_BASE + 0x015C) +#define DI_DISP0_DB0_MAP (IPU_REG_BASE + 0x0160) +#define DI_DISP0_DB1_MAP (IPU_REG_BASE + 0x0164) +#define DI_DISP0_DB2_MAP (IPU_REG_BASE + 0x0168) +#define DI_DISP0_CB0_MAP (IPU_REG_BASE + 0x016C) +#define DI_DISP0_CB1_MAP (IPU_REG_BASE + 0x0170) +#define DI_DISP0_CB2_MAP (IPU_REG_BASE + 0x0174) +#define DI_DISP1_DB0_MAP (IPU_REG_BASE + 0x0178) +#define DI_DISP1_DB1_MAP (IPU_REG_BASE + 0x017C) +#define DI_DISP1_DB2_MAP (IPU_REG_BASE + 0x0180) +#define DI_DISP1_CB0_MAP (IPU_REG_BASE + 0x0184) +#define DI_DISP1_CB1_MAP (IPU_REG_BASE + 0x0188) +#define DI_DISP1_CB2_MAP (IPU_REG_BASE + 0x018C) +#define DI_DISP2_DB0_MAP (IPU_REG_BASE + 0x0190) +#define DI_DISP2_DB1_MAP (IPU_REG_BASE + 0x0194) +#define DI_DISP2_DB2_MAP (IPU_REG_BASE + 0x0198) +#define DI_DISP2_CB0_MAP (IPU_REG_BASE + 0x019C) +#define DI_DISP2_CB1_MAP (IPU_REG_BASE + 0x01A0) +#define DI_DISP2_CB2_MAP (IPU_REG_BASE + 0x01A4) +#define DI_DISP3_B0_MAP (IPU_REG_BASE + 0x01A8) +#define DI_DISP3_B1_MAP (IPU_REG_BASE + 0x01AC) +#define DI_DISP3_B2_MAP (IPU_REG_BASE + 0x01B0) +#define DI_DISP_ACC_CC (IPU_REG_BASE + 0x01B4) +#define DI_DISP_LLA_CONF (IPU_REG_BASE + 0x01B8) +#define DI_DISP_LLA_DATA (IPU_REG_BASE + 0x01BC) + +#define IPUIRQ_2_STATREG(int) (IPU_INT_STAT_1 + 4*(int>>5)) +#define IPUIRQ_2_CTRLREG(int) (IPU_INT_CTRL_1 + 4*(int>>5)) +#define IPUIRQ_2_MASK(int) (1UL << (int & 0x1F)) + +enum { + IPU_CONF_CSI_EN = 0x00000001, + IPU_CONF_IC_EN = 0x00000002, + IPU_CONF_ROT_EN = 0x00000004, + IPU_CONF_PF_EN = 0x00000008, + IPU_CONF_SDC_EN = 0x00000010, + IPU_CONF_ADC_EN = 0x00000020, + IPU_CONF_DI_EN = 0x00000040, + IPU_CONF_DU_EN = 0x00000080, + IPU_CONF_PXL_ENDIAN = 0x00000100, + + FS_PRPVF_ROT_SRC_SEL = 0x00000040, + FS_PRPENC_ROT_SRC_SEL = 0x00000020, + FS_PRPENC_DEST_SEL = 0x00000010, + FS_PP_SRC_SEL_MASK = 0x00000300, + FS_PP_SRC_SEL_OFFSET = 8, + FS_PP_ROT_SRC_SEL_MASK = 0x00000C00, + FS_PP_ROT_SRC_SEL_OFFSET = 10, + FS_PF_DEST_SEL_MASK = 0x00003000, + FS_PF_DEST_SEL_OFFSET = 12, + FS_PRPVF_DEST_SEL_MASK = 0x00070000, + FS_PRPVF_DEST_SEL_OFFSET = 16, + FS_PRPVF_ROT_DEST_SEL_MASK = 0x00700000, + FS_PRPVF_ROT_DEST_SEL_OFFSET = 20, + FS_PP_DEST_SEL_MASK = 0x07000000, + FS_PP_DEST_SEL_OFFSET = 24, + FS_PP_ROT_DEST_SEL_MASK = 0x70000000, + FS_PP_ROT_DEST_SEL_OFFSET = 28, + FS_VF_IN_VALID = 0x00000002, + FS_ENC_IN_VALID = 0x00000001, + + FS_SDC_BG_SRC_SEL_MASK = 0x00000007, + FS_SDC_BG_SRC_SEL_OFFSET = 0, + FS_SDC_FG_SRC_SEL_MASK = 0x00000070, + FS_SDC_FG_SRC_SEL_OFFSET = 4, + FS_ADC1_SRC_SEL_MASK = 0x00000700, + FS_ADC1_SRC_SEL_OFFSET = 8, + FS_ADC2_SRC_SEL_MASK = 0x00007000, + FS_ADC2_SRC_SEL_OFFSET = 12, + FS_AUTO_REF_PER_MASK = 0x03FF0000, + FS_AUTO_REF_PER_OFFSET = 16, + + FS_DEST_ARM = 0, + FS_DEST_ROT = 1, + FS_DEST_PP = 1, + FS_DEST_ADC1 = 2, + FS_DEST_ADC2 = 3, + FS_DEST_SDC_BG = 4, + FS_DEST_SDC_FG = 5, + FS_DEST_ADC = 6, + + FS_SRC_ARM = 0, + FS_PP_SRC_PF = 1, + FS_PP_SRC_ROT = 2, + + FS_ROT_SRC_PP = 1, + FS_ROT_SRC_PF = 2, + + FS_PF_DEST_PP = 1, + FS_PF_DEST_ROT = 2, + + FS_SRC_ROT_VF = 1, + FS_SRC_ROT_PP = 2, + FS_SRC_VF = 3, + FS_SRC_PP = 4, + FS_SRC_SNOOP = 5, + FS_SRC_AUTOREF = 6, + FS_SRC_AUTOREF_SNOOP = 7, + + TSTAT_PF_H264_PAUSE = 0x00000001, + TSTAT_CSI2MEM_MASK = 0x0000000C, + TSTAT_CSI2MEM_OFFSET = 2, + TSTAT_VF_MASK = 0x00000600, + TSTAT_VF_OFFSET = 9, + TSTAT_VF_ROT_MASK = 0x000C0000, + TSTAT_VF_ROT_OFFSET = 18, + TSTAT_ENC_MASK = 0x00000180, + TSTAT_ENC_OFFSET = 7, + TSTAT_ENC_ROT_MASK = 0x00030000, + TSTAT_ENC_ROT_OFFSET = 16, + TSTAT_PP_MASK = 0x00001800, + TSTAT_PP_OFFSET = 11, + TSTAT_PP_ROT_MASK = 0x00300000, + TSTAT_PP_ROT_OFFSET = 20, + TSTAT_PF_MASK = 0x00C00000, + TSTAT_PF_OFFSET = 22, + TSTAT_ADCSYS1_MASK = 0x03000000, + TSTAT_ADCSYS1_OFFSET = 24, + TSTAT_ADCSYS2_MASK = 0x0C000000, + TSTAT_ADCSYS2_OFFSET = 26, + + TASK_STAT_IDLE = 0, + TASK_STAT_ACTIVE = 1, + TASK_STAT_WAIT4READY = 2, + + /* Register bits */ + SDC_COM_TFT_COLOR = 0x00000001UL, + SDC_COM_FG_EN = 0x00000010UL, + SDC_COM_GWSEL = 0x00000020UL, + SDC_COM_GLB_A = 0x00000040UL, + SDC_COM_KEY_COLOR_G = 0x00000080UL, + SDC_COM_BG_EN = 0x00000200UL, + SDC_COM_SHARP = 0x00001000UL, + + SDC_V_SYNC_WIDTH_L = 0x00000001UL, + + ADC_CONF_PRP_EN = 0x00000001L, + ADC_CONF_PP_EN = 0x00000002L, + ADC_CONF_MCU_EN = 0x00000004L, + + ADC_DISP_CONF_SL_MASK = 0x00000FFFL, + ADC_DISP_CONF_TYPE_MASK = 0x00003000L, + ADC_DISP_CONF_TYPE_XY = 0x00002000L, + + ADC_DISP_VSYNC_D0_MODE_MASK = 0x00000003L, + ADC_DISP_VSYNC_D0_WIDTH_MASK = 0x003F0000L, + ADC_DISP_VSYNC_D12_MODE_MASK = 0x0000000CL, + ADC_DISP_VSYNC_D12_WIDTH_MASK = 0x3F000000L, + + /* Image Converter Register bits */ + IC_CONF_PRPENC_EN = 0x00000001, + IC_CONF_PRPENC_CSC1 = 0x00000002, + IC_CONF_PRPENC_ROT_EN = 0x00000004, + IC_CONF_PRPVF_EN = 0x00000100, + IC_CONF_PRPVF_CSC1 = 0x00000200, + IC_CONF_PRPVF_CSC2 = 0x00000400, + IC_CONF_PRPVF_CMB = 0x00000800, + IC_CONF_PRPVF_ROT_EN = 0x00001000, + IC_CONF_PP_EN = 0x00010000, + IC_CONF_PP_CSC1 = 0x00020000, + IC_CONF_PP_CSC2 = 0x00040000, + IC_CONF_PP_CMB = 0x00080000, + IC_CONF_PP_ROT_EN = 0x00100000, + IC_CONF_IC_GLB_LOC_A = 0x10000000, + IC_CONF_KEY_COLOR_EN = 0x20000000, + IC_CONF_RWS_EN = 0x40000000, + IC_CONF_CSI_MEM_WR_EN = 0x80000000, + + IDMA_CHAN_INVALID = 0x000000FF, + IDMA_IC_0 = 0x00000001, + IDMA_IC_1 = 0x00000002, + IDMA_IC_2 = 0x00000004, + IDMA_IC_3 = 0x00000008, + IDMA_IC_4 = 0x00000010, + IDMA_IC_5 = 0x00000020, + IDMA_IC_6 = 0x00000040, + IDMA_IC_7 = 0x00000080, + IDMA_IC_8 = 0x00000100, + IDMA_IC_9 = 0x00000200, + IDMA_IC_10 = 0x00000400, + IDMA_IC_11 = 0x00000800, + IDMA_IC_12 = 0x00001000, + IDMA_IC_13 = 0x00002000, + IDMA_SDC_BG = 0x00004000, + IDMA_SDC_FG = 0x00008000, + IDMA_SDC_MASK = 0x00010000, + IDMA_SDC_PARTIAL = 0x00020000, + IDMA_ADC_SYS1_WR = 0x00040000, + IDMA_ADC_SYS2_WR = 0x00080000, + IDMA_ADC_SYS1_CMD = 0x00100000, + IDMA_ADC_SYS2_CMD = 0x00200000, + IDMA_ADC_SYS1_RD = 0x00400000, + IDMA_ADC_SYS2_RD = 0x00800000, + IDMA_PF_QP = 0x01000000, + IDMA_PF_BSP = 0x02000000, + IDMA_PF_Y_IN = 0x04000000, + IDMA_PF_U_IN = 0x08000000, + IDMA_PF_V_IN = 0x10000000, + IDMA_PF_Y_OUT = 0x20000000, + IDMA_PF_U_OUT = 0x40000000, + IDMA_PF_V_OUT = 0x80000000, + + CSI_SENS_CONF_DATA_FMT_SHIFT = 8, + CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0x00000000L, + CSI_SENS_CONF_DATA_FMT_YUV422 = 0x00000200L, + CSI_SENS_CONF_DATA_FMT_BAYER = 0x00000300L, + + CSI_SENS_CONF_VSYNC_POL_SHIFT = 0, + CSI_SENS_CONF_HSYNC_POL_SHIFT = 1, + CSI_SENS_CONF_DATA_POL_SHIFT = 2, + CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3, + CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4, + CSI_SENS_CONF_SENS_CLKSRC_SHIFT = 7, + CSI_SENS_CONF_DATA_WIDTH_SHIFT = 10, + CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15, + CSI_SENS_CONF_DIVRATIO_SHIFT = 16, + + PF_CONF_TYPE_MASK = 0x00000007, + PF_CONF_TYPE_SHIFT = 0, + PF_CONF_PAUSE_EN = 0x00000010, + PF_CONF_RESET = 0x00008000, + PF_CONF_PAUSE_ROW_MASK = 0x00FF0000, + PF_CONF_PAUSE_ROW_SHIFT = 16, + + /* DI_DISP_SIG_POL bits */ + DI_D3_VSYNC_POL_SHIFT = 28, + DI_D3_HSYNC_POL_SHIFT = 27, + DI_D3_DRDY_SHARP_POL_SHIFT = 26, + DI_D3_CLK_POL_SHIFT = 25, + DI_D3_DATA_POL_SHIFT = 24, + + /* DI_DISP_IF_CONF bits */ + DI_D3_CLK_IDLE_SHIFT = 26, + DI_D3_CLK_SEL_SHIFT = 25, + DI_D3_DATAMSK_SHIFT = 24, + + DISPx_IF_CLK_DOWN_OFFSET = 22, + DISPx_IF_CLK_UP_OFFSET = 12, + DISPx_IF_CLK_PER_OFFSET = 0, + DISPx_IF_CLK_READ_EN_OFFSET = 16, + DISPx_PIX_CLK_PER_OFFSET = 0, + + DI_CONF_DISP0_EN = 0x00000001L, + DI_CONF_DISP0_IF_MODE_OFFSET = 1, + DI_CONF_DISP0_BURST_MODE_OFFSET = 3, + DI_CONF_DISP1_EN = 0x00000100L, + DI_CONF_DISP1_IF_MODE_OFFSET = 9, + DI_CONF_DISP1_BURST_MODE_OFFSET = 12, + DI_CONF_DISP2_EN = 0x00010000L, + DI_CONF_DISP2_IF_MODE_OFFSET = 17, + DI_CONF_DISP2_BURST_MODE_OFFSET = 20, + + DI_SER_DISPx_CONF_SER_BIT_NUM_OFFSET = 16, + DI_SER_DISPx_CONF_PREAMBLE_OFFSET = 8, + DI_SER_DISPx_CONF_PREAMBLE_LEN_OFFSET = 4, + DI_SER_DISPx_CONF_RW_CFG_OFFSET = 1, + DI_SER_DISPx_CONF_BURST_MODE_EN = 0x01000000L, + DI_SER_DISPx_CONF_PREAMBLE_EN = 0x00000001L, + + /* DI_DISP_ACC_CC */ + DISP0_IF_CLK_CNT_D_MASK = 0x00000003L, + DISP0_IF_CLK_CNT_D_OFFSET = 0, + DISP0_IF_CLK_CNT_C_MASK = 0x0000000CL, + DISP0_IF_CLK_CNT_C_OFFSET = 2, + DISP1_IF_CLK_CNT_D_MASK = 0x00000030L, + DISP1_IF_CLK_CNT_D_OFFSET = 4, + DISP1_IF_CLK_CNT_C_MASK = 0x000000C0L, + DISP1_IF_CLK_CNT_C_OFFSET = 6, + DISP2_IF_CLK_CNT_D_MASK = 0x00000300L, + DISP2_IF_CLK_CNT_D_OFFSET = 8, + DISP2_IF_CLK_CNT_C_MASK = 0x00000C00L, + DISP2_IF_CLK_CNT_C_OFFSET = 10, + DISP3_IF_CLK_CNT_MASK = 0x00003000L, + DISP3_IF_CLK_CNT_OFFSET = 12, +}; + +#endif diff --git a/drivers/mxc/ipu/ipu_sdc.c b/drivers/mxc/ipu/ipu_sdc.c new file mode 100644 index 000000000000..946d793e30de --- /dev/null +++ b/drivers/mxc/ipu/ipu_sdc.c @@ -0,0 +1,357 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_sdc.c + * + * @brief IPU SDC submodule API functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +static uint32_t g_h_start_width; +static uint32_t g_v_start_width; + +static const uint32_t di_mappings[] = { + 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */ + 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */ + 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */ + 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */ +}; + +/*! + * This function is called to initialize a synchronous LCD panel. + * + * @param panel The type of panel. + * + * @param pixel_clk Desired pixel clock frequency in Hz. + * + * @param pixel_fmt Input parameter for pixel format of buffer. Pixel + * format is a FOURCC ASCII code. + * + * @param width The width of panel in pixels. + * + * @param height The height of panel in pixels. + * + * @param hStartWidth The number of pixel clocks between the HSYNC + * signal pulse and the start of valid data. + * + * @param hSyncWidth The width of the HSYNC signal in units of pixel + * clocks. + * + * @param hEndWidth The number of pixel clocks between the end of + * valid data and the HSYNC signal for next line. + * + * @param vStartWidth The number of lines between the VSYNC + * signal pulse and the start of valid data. + * + * @param vSyncWidth The width of the VSYNC signal in units of lines + * + * @param vEndWidth The number of lines between the end of valid + * data and the VSYNC signal for next frame. + * + * @param sig Bitfield of signal polarities for LCD interface. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_sdc_init_panel(ipu_panel_t panel, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + ipu_di_signal_cfg_t sig) +{ + unsigned long lock_flags; + uint32_t reg; + uint32_t old_conf; + uint32_t div; + + dev_dbg(g_ipu_dev, "panel size = %d x %d\n", width, height); + + if ((v_sync_width == 0) || (h_sync_width == 0)) + return EINVAL; + + /* Init panel size and blanking periods */ + reg = + ((uint32_t) (h_sync_width - 1) << 26) | + ((uint32_t) (width + h_sync_width + h_start_width + h_end_width - 1) + << 16); + __raw_writel(reg, SDC_HOR_CONF); + + reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | + ((uint32_t) + (height + v_sync_width + v_start_width + v_end_width - 1) << 16); + __raw_writel(reg, SDC_VER_CONF); + + g_h_start_width = h_start_width + h_sync_width; + g_v_start_width = v_start_width + v_sync_width; + + switch (panel) { + case IPU_PANEL_SHARP_TFT: + __raw_writel(0x00FD0102L, SDC_SHARP_CONF_1); + __raw_writel(0x00F500F4L, SDC_SHARP_CONF_2); + __raw_writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); + break; + case IPU_PANEL_TFT: + __raw_writel(SDC_COM_TFT_COLOR, SDC_COM_CONF); + break; + default: + return EINVAL; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + /* Init clocking */ + + /* Calculate divider */ + /* fractional part is 4 bits so simply multiple by 2^4 to get fractional part */ + dev_dbg(g_ipu_dev, "pixel clk = %d\n", pixel_clk); + div = (clk_get_rate(g_ipu_clk) * 16) / pixel_clk; + if (div < 0x40) { /* Divider less than 4 */ + dev_dbg(g_ipu_dev, + "InitPanel() - Pixel clock divider less than 1\n"); + div = 0x40; + } + /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less fraction bits */ + /* Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing debug */ + /* DISP3_IF_CLK_UP_WR is 0 */ + __raw_writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); + + /* DI settings */ + old_conf = __raw_readl(DI_DISP_IF_CONF) & 0x78FFFFFF; + old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT | + sig.clksel_en << DI_D3_CLK_SEL_SHIFT | + sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT; + __raw_writel(old_conf, DI_DISP_IF_CONF); + + old_conf = __raw_readl(DI_DISP_SIG_POL) & 0xE0FFFFFF; + old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT | + sig.clk_pol << DI_D3_CLK_POL_SHIFT | + sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT | + sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT | + sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT; + __raw_writel(old_conf, DI_DISP_SIG_POL); + + switch (pixel_fmt) { + case IPU_PIX_FMT_RGB24: + __raw_writel(di_mappings[0], DI_DISP3_B0_MAP); + __raw_writel(di_mappings[1], DI_DISP3_B1_MAP); + __raw_writel(di_mappings[2], DI_DISP3_B2_MAP); + __raw_writel(__raw_readl(DI_DISP_ACC_CC) | + ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC); + break; + case IPU_PIX_FMT_RGB666: + __raw_writel(di_mappings[4], DI_DISP3_B0_MAP); + __raw_writel(di_mappings[5], DI_DISP3_B1_MAP); + __raw_writel(di_mappings[6], DI_DISP3_B2_MAP); + __raw_writel(__raw_readl(DI_DISP_ACC_CC) | + ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC); + break; + case IPU_PIX_FMT_BGR666: + __raw_writel(di_mappings[8], DI_DISP3_B0_MAP); + __raw_writel(di_mappings[9], DI_DISP3_B1_MAP); + __raw_writel(di_mappings[10], DI_DISP3_B2_MAP); + __raw_writel(__raw_readl(DI_DISP_ACC_CC) | + ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC); + break; + default: + __raw_writel(di_mappings[12], DI_DISP3_B0_MAP); + __raw_writel(di_mappings[13], DI_DISP3_B1_MAP); + __raw_writel(di_mappings[14], DI_DISP3_B2_MAP); + __raw_writel(__raw_readl(DI_DISP_ACC_CC) | + ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC); + break; + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + dev_dbg(g_ipu_dev, "DI_DISP_IF_CONF = 0x%08X\n", + __raw_readl(DI_DISP_IF_CONF)); + dev_dbg(g_ipu_dev, "DI_DISP_SIG_POL = 0x%08X\n", + __raw_readl(DI_DISP_SIG_POL)); + dev_dbg(g_ipu_dev, "DI_DISP3_TIME_CONF = 0x%08X\n", + __raw_readl(DI_DISP3_TIME_CONF)); + + return 0; +} + +/*! + * This function sets the foreground and background plane global alpha blending + * modes. + * + * @param enable Boolean to enable or disable global alpha + * blending. If disabled, per pixel blending is used. + * + * @param alpha Global alpha value. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_sdc_set_global_alpha(bool enable, uint8_t alpha) +{ + uint32_t reg; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (enable) { + reg = __raw_readl(SDC_GW_CTRL) & 0x00FFFFFFL; + __raw_writel(reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); + + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg | SDC_COM_GLB_A, SDC_COM_CONF); + } else { + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg & ~SDC_COM_GLB_A, SDC_COM_CONF); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +/*! + * This function sets the transparent color key for SDC graphic plane. + * + * @param channel Input parameter for the logical channel ID. + * + * @param enable Boolean to enable or disable color key + * + * @param colorKey 24-bit RGB color to use as transparent color key. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_sdc_set_color_key(ipu_channel_t channel, bool enable, + uint32_t color_key) +{ + uint32_t reg, sdc_conf; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + sdc_conf = __raw_readl(SDC_COM_CONF); + if (channel == MEM_SDC_BG) { + sdc_conf &= ~SDC_COM_GWSEL; + } else { + sdc_conf |= SDC_COM_GWSEL; + } + + if (enable) { + reg = __raw_readl(SDC_GW_CTRL) & 0xFF000000L; + __raw_writel(reg | (color_key & 0x00FFFFFFL), SDC_GW_CTRL); + + sdc_conf |= SDC_COM_KEY_COLOR_G; + } else { + sdc_conf &= ~SDC_COM_KEY_COLOR_G; + } + __raw_writel(sdc_conf, SDC_COM_CONF); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} + +int32_t ipu_sdc_set_brightness(uint8_t value) +{ + __raw_writel(0x03000000UL | value << 16, SDC_PWM_CTRL); + return 0; +} + +/*! + * This function sets the window position of the foreground or background plane. + * modes. + * + * @param channel Input parameter for the logical channel ID. + * + * @param x_pos The X coordinate position to place window at. + * The position is relative to the top left corner. + * + * @param y_pos The Y coordinate position to place window at. + * The position is relative to the top left corner. + * + * @return This function returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_window_pos(ipu_channel_t channel, int16_t x_pos, + int16_t y_pos) +{ + x_pos += g_h_start_width; + y_pos += g_v_start_width; + + if (channel == MEM_SDC_BG) { + __raw_writel((x_pos << 16) | y_pos, SDC_BG_POS); + } else if (channel == MEM_SDC_FG) { + __raw_writel((x_pos << 16) | y_pos, SDC_FG_POS); + } else { + return EINVAL; + } + return 0; +} + +void _ipu_sdc_fg_init(ipu_channel_params_t *params) +{ + uint32_t reg; + (void)params; + + /* Enable FG channel */ + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg | SDC_COM_FG_EN | SDC_COM_BG_EN, SDC_COM_CONF); +} + +uint32_t _ipu_sdc_fg_uninit(void) +{ + uint32_t reg; + + /* Disable FG channel */ + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg & ~SDC_COM_FG_EN, SDC_COM_CONF); + + return reg & SDC_COM_FG_EN; +} + +void _ipu_sdc_bg_init(ipu_channel_params_t *params) +{ + uint32_t reg; + (void)params; + + /* Enable FG channel */ + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg | SDC_COM_BG_EN, SDC_COM_CONF); +} + +uint32_t _ipu_sdc_bg_uninit(void) +{ + uint32_t reg; + + /* Disable BG channel */ + reg = __raw_readl(SDC_COM_CONF); + __raw_writel(reg & ~SDC_COM_BG_EN, SDC_COM_CONF); + + return reg & SDC_COM_BG_EN; +} + +/* Exported symbols for modules. */ +EXPORT_SYMBOL(ipu_sdc_init_panel); +EXPORT_SYMBOL(ipu_sdc_set_global_alpha); +EXPORT_SYMBOL(ipu_sdc_set_color_key); +EXPORT_SYMBOL(ipu_sdc_set_brightness); +EXPORT_SYMBOL(ipu_disp_set_window_pos); diff --git a/drivers/mxc/ipu/pf/Kconfig b/drivers/mxc/ipu/pf/Kconfig new file mode 100644 index 000000000000..fa5a777cf727 --- /dev/null +++ b/drivers/mxc/ipu/pf/Kconfig @@ -0,0 +1,7 @@ +config MXC_IPU_PF + tristate "MXC MPEG4/H.264 Post Filter Driver" + depends on MXC_IPU_V1 + default y + help + Driver for MPEG4 dering and deblock and H.264 deblock + using MXC IPU h/w diff --git a/drivers/mxc/ipu/pf/Makefile b/drivers/mxc/ipu/pf/Makefile new file mode 100644 index 000000000000..641adf4be4bd --- /dev/null +++ b/drivers/mxc/ipu/pf/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MXC_IPU_PF) += mxc_pf.o diff --git a/drivers/mxc/ipu/pf/mxc_pf.c b/drivers/mxc/ipu/pf/mxc_pf.c new file mode 100644 index 000000000000..e098e0d20510 --- /dev/null +++ b/drivers/mxc/ipu/pf/mxc_pf.c @@ -0,0 +1,991 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_pf.c + * + * @brief MXC IPU MPEG4/H.264 Post-filtering driver + * + * User-level API for IPU Hardware MPEG4/H.264 Post-filtering. + * + * @ingroup MXC_PF + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mxc_pf_data { + pf_operation_t mode; + u32 pf_enabled; + u32 width; + u32 height; + u32 stride; + uint32_t qp_size; + dma_addr_t qp_paddr; + void *qp_vaddr; + pf_buf buf[PF_MAX_BUFFER_CNT]; + void *buf_vaddr[PF_MAX_BUFFER_CNT]; + wait_queue_head_t pf_wait; + volatile int done_mask; + volatile int wait_mask; + volatile int busy_flag; + struct semaphore busy_lock; +}; + +static struct mxc_pf_data pf_data; +static u8 open_count; +static struct class *mxc_pf_class; + +/* + * Function definitions + */ + +static irqreturn_t mxc_pf_irq_handler(int irq, void *dev_id) +{ + struct mxc_pf_data *pf = dev_id; + + if (irq == IPU_IRQ_PF_Y_OUT_EOF) { + pf->done_mask |= PF_WAIT_Y; + } else if (irq == IPU_IRQ_PF_U_OUT_EOF) { + pf->done_mask |= PF_WAIT_U; + } else if (irq == IPU_IRQ_PF_V_OUT_EOF) { + pf->done_mask |= PF_WAIT_V; + } else { + return IRQ_NONE; + } + + if (pf->wait_mask && ((pf->done_mask & pf->wait_mask) == pf->wait_mask)) { + wake_up_interruptible(&pf->pf_wait); + } + return IRQ_HANDLED; +} + +/*! + * This function handles PF_IOCTL_INIT calls. It initializes the PF channels, + * interrupt handlers, and channel buffers. + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_init(pf_init_params *pf_init) +{ + int err; + ipu_channel_params_t params; + u32 w; + u32 stride; + u32 h; + u32 qp_size = 0; + u32 qp_stride; + + if ((pf_init->pf_mode > 4) || (pf_init->width > 1024) || + (pf_init->height > 1024) || (pf_init->stride < pf_init->width)) { + return -EINVAL; + } + + pf_data.mode = pf_init->pf_mode; + w = pf_data.width = pf_init->width; + h = pf_data.height = pf_init->height; + stride = pf_data.stride = pf_init->stride; + pf_data.qp_size = pf_init->qp_size; + + memset(¶ms, 0, sizeof(params)); + params.mem_pf_mem.operation = pf_data.mode; + err = ipu_init_channel(MEM_PF_Y_MEM, ¶ms); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error initializing channel\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error initializing Y input buffer\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error initializing Y output buffer\n"); + goto err0; + } + + w = w / 2; + h = h / 2; + stride = stride / 2; + + if (pf_data.mode != PF_MPEG4_DERING) { + err = ipu_init_channel_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing U input buffer\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing U output buffer\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing V input buffer\n"); + goto err0; + } + + err = ipu_init_channel_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, stride, + IPU_ROTATE_NONE, 0, 0, 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing V output buffer\n"); + goto err0; + } + } + + /*Setup Channel QF and BSC Params */ + if (pf_data.mode == PF_H264_DEBLOCK) { + w = ((pf_data.width + 15) / 16); + h = (pf_data.height + 15) / 16; + qp_stride = w; + qp_size = 4 * qp_stride * h; + pr_debug("H264 QP width = %d, height = %d\n", w, h); + err = ipu_init_channel_buffer(MEM_PF_Y_MEM, + IPU_SEC_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC_32, w, h, + qp_stride, IPU_ROTATE_NONE, 0, 0, + 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing H264 QP buffer\n"); + goto err0; + } +/* w = (pf_data.width + 3) / 4; */ + w *= 4; + h *= 4; + qp_stride = w; + err = ipu_init_channel_buffer(MEM_PF_U_MEM, + IPU_SEC_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, + qp_stride, IPU_ROTATE_NONE, 0, 0, + 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing H264 BSB buffer\n"); + goto err0; + } + qp_size += qp_stride * h; + } else { /* MPEG4 mode */ + + w = (pf_data.width + 15) / 16; + h = (pf_data.height + 15) / 16; + qp_stride = (w + 3) & ~0x3UL; + pr_debug("MPEG4 QP width = %d, height = %d, stride = %d\n", + w, h, qp_stride); + err = ipu_init_channel_buffer(MEM_PF_Y_MEM, + IPU_SEC_INPUT_BUFFER, + IPU_PIX_FMT_GENERIC, w, h, + qp_stride, IPU_ROTATE_NONE, 0, 0, + 0, 0); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error initializing MPEG4 QP buffer\n"); + goto err0; + } + qp_size = qp_stride * h; + } + + /* Support 2 QP buffers */ + qp_size *= 2; + + if (pf_data.qp_size > qp_size) + qp_size = pf_data.qp_size; + else + pf_data.qp_size = qp_size; + + pf_data.qp_vaddr = dma_alloc_coherent(NULL, pf_data.qp_size, + &pf_data.qp_paddr, + GFP_KERNEL | GFP_DMA); + if (!pf_data.qp_vaddr) + return -ENOMEM; + + pf_init->qp_paddr = pf_data.qp_paddr; + pf_init->qp_size = pf_data.qp_size; + + return 0; + + err0: + return err; +} + +/*! + * This function handles PF_IOCTL_UNINIT calls. It uninitializes the PF + * channels and interrupt handlers. + * + * @return This function returns 0 on success or negative error code + * on error. + */ +static int mxc_pf_uninit(void) +{ + pf_data.pf_enabled = 0; + ipu_disable_irq(IPU_IRQ_PF_Y_OUT_EOF); + ipu_disable_irq(IPU_IRQ_PF_U_OUT_EOF); + ipu_disable_irq(IPU_IRQ_PF_V_OUT_EOF); + + ipu_disable_channel(MEM_PF_Y_MEM, true); + ipu_disable_channel(MEM_PF_U_MEM, true); + ipu_disable_channel(MEM_PF_V_MEM, true); + ipu_uninit_channel(MEM_PF_Y_MEM); + ipu_uninit_channel(MEM_PF_U_MEM); + ipu_uninit_channel(MEM_PF_V_MEM); + + if (pf_data.qp_vaddr) { + dma_free_coherent(NULL, pf_data.qp_size, pf_data.qp_vaddr, + pf_data.qp_paddr); + pf_data.qp_vaddr = NULL; + } + + return 0; +} + +/*! + * This function handles PF_IOCTL_REQBUFS calls. It initializes the PF channels + * and channel buffers. + * + * @param reqbufs Input/Output Structure containing buffer mode, + * type, offset, and size. The offset and size of + * the buffer are returned for PF_MEMORY_MMAP mode. + * + * @return This function returns 0 on success or negative error code + * on error. + */ +static int mxc_pf_reqbufs(pf_reqbufs_params *reqbufs) +{ + int err; + uint32_t buf_size; + int i; + int alloc_cnt = 0; + pf_buf *buf = pf_data.buf; + if (reqbufs->count > PF_MAX_BUFFER_CNT) { + reqbufs->count = PF_MAX_BUFFER_CNT; + } + /* Deallocate mmapped buffers */ + if (reqbufs->count == 0) { + for (i = 0; i < PF_MAX_BUFFER_CNT; i++) { + if (buf[i].index != -1) { + dma_free_coherent(NULL, buf[i].size, + pf_data.buf_vaddr[i], + buf[i].offset); + pf_data.buf_vaddr[i] = NULL; + buf[i].index = -1; + buf[i].size = 0; + } + } + return 0; + } + + buf_size = (pf_data.stride * pf_data.height * 3) / 2; + if (reqbufs->req_size > buf_size) { + buf_size = reqbufs->req_size; + pr_debug("using requested buffer size of %d\n", buf_size); + } else { + reqbufs->req_size = buf_size; + pr_debug("using default buffer size of %d\n", buf_size); + } + + for (i = 0; alloc_cnt < reqbufs->count; i++) { + buf[i].index = i; + buf[i].size = buf_size; + pf_data.buf_vaddr[i] = dma_alloc_coherent(NULL, buf[i].size, + &buf[i].offset, + GFP_KERNEL | GFP_DMA); + if (!pf_data.buf_vaddr[i] || !buf[i].offset) { + printk(KERN_ERR + "mxc_pf: unable to allocate IPU buffers.\n"); + err = -ENOMEM; + goto err0; + } + pr_debug("Allocated buffer %d at paddr 0x%08X, vaddr %p\n", + i, buf[i].offset, pf_data.buf_vaddr[i]); + + alloc_cnt++; + } + + return 0; + err0: + for (i = 0; i < alloc_cnt; i++) { + dma_free_coherent(NULL, buf[i].size, pf_data.buf_vaddr[i], + buf[i].offset); + pf_data.buf_vaddr[i] = NULL; + buf[i].index = -1; + buf[i].size = 0; + } + return err; +} + +/*! + * This function handles PF_IOCTL_START calls. It sets the PF channel buffers + * addresses and starts the channels + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_start(pf_buf *in, pf_buf *out, int qp_buf) +{ + int err; + dma_addr_t y_in_paddr; + dma_addr_t u_in_paddr; + dma_addr_t v_in_paddr; + dma_addr_t p1_in_paddr; + dma_addr_t p2_in_paddr; + dma_addr_t y_out_paddr; + dma_addr_t u_out_paddr; + dma_addr_t v_out_paddr; + + /* H.264 requires output buffer equal to input */ + if (pf_data.mode == PF_H264_DEBLOCK) + out = in; + + y_in_paddr = in->offset + in->y_offset; + if (in->u_offset) + u_in_paddr = in->offset + in->u_offset; + else + u_in_paddr = y_in_paddr + (pf_data.stride * pf_data.height); + if (in->v_offset) + v_in_paddr = in->offset + in->v_offset; + else + v_in_paddr = u_in_paddr + (pf_data.stride * pf_data.height) / 4; + p1_in_paddr = pf_data.qp_paddr; + if (qp_buf) + p1_in_paddr += pf_data.qp_size / 2; + + if (pf_data.mode == PF_H264_DEBLOCK) { + p2_in_paddr = p1_in_paddr + + ((pf_data.width + 15) / 16) * + ((pf_data.height + 15) / 16) * 4; + } else { + p2_in_paddr = 0; + } + + pr_debug("y_in_paddr = 0x%08X\nu_in_paddr = 0x%08X\n" + "v_in_paddr = 0x%08X\n" + "qp_paddr = 0x%08X\nbsb_paddr = 0x%08X\n", + y_in_paddr, u_in_paddr, v_in_paddr, p1_in_paddr, p2_in_paddr); + + y_out_paddr = out->offset + out->y_offset; + if (out->u_offset) + u_out_paddr = out->offset + out->u_offset; + else + u_out_paddr = y_out_paddr + (pf_data.stride * pf_data.height); + if (out->v_offset) + v_out_paddr = out->offset + out->v_offset; + else + v_out_paddr = + u_out_paddr + (pf_data.stride * pf_data.height) / 4; + + pr_debug("y_out_paddr = 0x%08X\nu_out_paddr = 0x%08X\n" + "v_out_paddr = 0x%08X\n", + y_out_paddr, u_out_paddr, v_out_paddr); + + pf_data.done_mask = 0; + + ipu_enable_irq(IPU_IRQ_PF_Y_OUT_EOF); + if (pf_data.mode != PF_MPEG4_DERING) { + ipu_enable_irq(IPU_IRQ_PF_U_OUT_EOF); + ipu_enable_irq(IPU_IRQ_PF_V_OUT_EOF); + } + + err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER, 0, + y_in_paddr); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error setting Y input buffer\n"); + goto err0; + } + + err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER, 0, + y_out_paddr); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error setting Y output buffer\n"); + goto err0; + } + + if (pf_data.mode != PF_MPEG4_DERING) { + err = + ipu_update_channel_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER, 0, + u_in_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting U input buffer\n"); + goto err0; + } + + err = + ipu_update_channel_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER, + 0, u_out_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting U output buffer\n"); + goto err0; + } + + err = + ipu_update_channel_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER, 0, + v_in_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting V input buffer\n"); + goto err0; + } + + err = + ipu_update_channel_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER, + 0, v_out_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting V output buffer\n"); + goto err0; + } + } + + err = ipu_update_channel_buffer(MEM_PF_Y_MEM, IPU_SEC_INPUT_BUFFER, 0, + p1_in_paddr); + if (err < 0) { + printk(KERN_ERR "mxc_pf: error setting QP buffer\n"); + goto err0; + } + + if (pf_data.mode == PF_H264_DEBLOCK) { + + err = ipu_update_channel_buffer(MEM_PF_U_MEM, + IPU_SEC_INPUT_BUFFER, 0, + p2_in_paddr); + if (err < 0) { + printk(KERN_ERR + "mxc_pf: error setting H264 BSB buffer\n"); + goto err0; + } + ipu_select_buffer(MEM_PF_U_MEM, IPU_SEC_INPUT_BUFFER, 0); + } + + ipu_select_buffer(MEM_PF_Y_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_Y_MEM, IPU_SEC_INPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_Y_MEM, IPU_INPUT_BUFFER, 0); + if (pf_data.mode != PF_MPEG4_DERING) { + ipu_select_buffer(MEM_PF_U_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_V_MEM, IPU_OUTPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_U_MEM, IPU_INPUT_BUFFER, 0); + ipu_select_buffer(MEM_PF_V_MEM, IPU_INPUT_BUFFER, 0); + } + + if (!pf_data.pf_enabled) { + pf_data.pf_enabled = 1; + if (pf_data.mode != PF_MPEG4_DERING) { + ipu_enable_channel(MEM_PF_V_MEM); + ipu_enable_channel(MEM_PF_U_MEM); + } + ipu_enable_channel(MEM_PF_Y_MEM); + } + + return 0; + err0: + return err; +} + +/*! + * Post Filter driver open function. This function implements the Linux + * file_operations.open() API function. + * + * @param inode struct inode * + * + * @param filp struct file * + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_open(struct inode *inode, struct file *filp) +{ + int i; + + if (open_count) { + return -EBUSY; + } + + open_count++; + + memset(&pf_data, 0, sizeof(pf_data)); + for (i = 0; i < PF_MAX_BUFFER_CNT; i++) { + pf_data.buf[i].index = -1; + } + init_waitqueue_head(&pf_data.pf_wait); + init_MUTEX(&pf_data.busy_lock); + + pf_data.busy_flag = 1; + + ipu_request_irq(IPU_IRQ_PF_Y_OUT_EOF, mxc_pf_irq_handler, + 0, "mxc_ipu_pf", &pf_data); + + ipu_request_irq(IPU_IRQ_PF_U_OUT_EOF, mxc_pf_irq_handler, + 0, "mxc_ipu_pf", &pf_data); + + ipu_request_irq(IPU_IRQ_PF_V_OUT_EOF, mxc_pf_irq_handler, + 0, "mxc_ipu_pf", &pf_data); + + ipu_disable_irq(IPU_IRQ_PF_Y_OUT_EOF); + ipu_disable_irq(IPU_IRQ_PF_U_OUT_EOF); + ipu_disable_irq(IPU_IRQ_PF_V_OUT_EOF); + + return 0; +} + +/*! + * Post Filter driver release function. This function implements the Linux + * file_operations.release() API function. + * + * @param inode struct inode * + * + * @param filp struct file * + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_release(struct inode *inode, struct file *filp) +{ + pf_reqbufs_params req_buf; + + if (open_count) { + mxc_pf_uninit(); + + /* Free any allocated buffers */ + req_buf.count = 0; + mxc_pf_reqbufs(&req_buf); + + ipu_free_irq(IPU_IRQ_PF_V_OUT_EOF, &pf_data); + ipu_free_irq(IPU_IRQ_PF_U_OUT_EOF, &pf_data); + ipu_free_irq(IPU_IRQ_PF_Y_OUT_EOF, &pf_data); + open_count--; + } + return 0; +} + +/*! + * Post Filter driver ioctl function. This function implements the Linux + * file_operations.ioctl() API function. + * + * @param inode struct inode * + * + * @param filp struct file * + * + * @param cmd IOCTL command to handle + * + * @param arg Pointer to arguments for IOCTL + * + * @return This function returns 0 on success or negative error code on + * error. + */ +static int mxc_pf_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + int retval = 0; + + switch (cmd) { + case PF_IOCTL_INIT: + { + pf_init_params pf_init; + + pr_debug("PF_IOCTL_INIT\n"); + if (copy_from_user(&pf_init, (void *)arg, + _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + retval = mxc_pf_init(&pf_init); + if (retval < 0) + break; + pf_init.qp_paddr = pf_data.qp_paddr; + pf_init.qp_size = pf_data.qp_size; + + /* Return size of memory allocated */ + if (copy_to_user((void *)arg, &pf_init, _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + pf_data.busy_flag = 0; + break; + } + case PF_IOCTL_UNINIT: + pr_debug("PF_IOCTL_UNINIT\n"); + retval = mxc_pf_uninit(); + break; + case PF_IOCTL_REQBUFS: + { + pf_reqbufs_params reqbufs; + pr_debug("PF_IOCTL_REQBUFS\n"); + + if (copy_from_user + (&reqbufs, (void *)arg, _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + retval = mxc_pf_reqbufs(&reqbufs); + + /* Return size of memory allocated */ + if (copy_to_user((void *)arg, &reqbufs, _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + break; + } + case PF_IOCTL_QUERYBUF: + { + pf_buf buf; + pr_debug("PF_IOCTL_QUERYBUF\n"); + + if (copy_from_user(&buf, (void *)arg, _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + if ((buf.index < 0) || + (buf.index >= PF_MAX_BUFFER_CNT) || + (pf_data.buf[buf.index].index != buf.index)) { + retval = -EINVAL; + break; + } + /* Return size of memory allocated */ + if (copy_to_user((void *)arg, &pf_data.buf[buf.index], + _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + break; + } + case PF_IOCTL_START: + { + int index; + pf_start_params start_params; + pr_debug("PF_IOCTL_START\n"); + + if (pf_data.busy_flag) { + retval = -EBUSY; + break; + } + + if (copy_from_user(&start_params, (void *)arg, + _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + if (start_params.h264_pause_row >= + ((pf_data.height + 15) / 16)) { + retval = -EINVAL; + break; + } + + pf_data.busy_flag = 1; + + index = start_params.in.index; + if ((index >= 0) && (index < PF_MAX_BUFFER_CNT)) { + if (pf_data.buf[index].offset != + start_params.in.offset) { + retval = -EINVAL; + break; + } + } + + index = start_params.out.index; + if ((index >= 0) && (index < PF_MAX_BUFFER_CNT)) { + if (pf_data.buf[index].offset != + start_params.out.offset) { + retval = -EINVAL; + break; + } + } + + ipu_pf_set_pause_row(start_params.h264_pause_row); + + retval = mxc_pf_start(&start_params.in, &start_params.out, + start_params.qp_buf); + /*Update y, u, v buffers in DMA Channels */ + if ((retval < 0) + break; + + pr_debug("PF_IOCTL_START - processing started\n"); + + if (!start_params.wait) { + break; + } + + pr_debug("PF_IOCTL_START - waiting for completion\n"); + + pf_data.wait_mask = PF_WAIT_ALL; + /* Fall thru to wait */ + } + case PF_IOCTL_WAIT: + { + if (!pf_data.wait_mask) + pf_data.wait_mask = (u32) arg; + + if (pf_data.mode == PF_MPEG4_DERING) + pf_data.wait_mask &= PF_WAIT_Y; + + if (!pf_data.wait_mask) { + retval = -EINVAL; + break; + } + + if (!wait_event_interruptible_timeout(pf_data.pf_wait, + ((pf_data. + done_mask & + pf_data. + wait_mask) == + pf_data. + wait_mask), + 1 * HZ)) { + pr_debug + ("PF_IOCTL_WAIT: timeout, done_mask = %d\n", + pf_data.done_mask); + retval = -ETIME; + break; + } else if (signal_pending(current)) { + pr_debug("PF_IOCTL_WAIT: interrupt received\n"); + retval = -ERESTARTSYS; + break; + } + pf_data.busy_flag = 0; + pf_data.wait_mask = 0; + + pr_debug("PF_IOCTL_WAIT - finished\n"); + break; + } + case PF_IOCTL_RESUME: + { + int pause_row; + pr_debug("PF_IOCTL_RESUME\n"); + + if (pf_data.busy_flag == 0) { + retval = -EFAULT; + break; + } + + if (copy_from_user(&pause_row, (void *)arg, + _IOC_SIZE(cmd))) { + retval = -EFAULT; + break; + } + + if (pause_row >= ((pf_data.height + 15) / 16)) { + retval = -EINVAL; + break; + } + + ipu_pf_set_pause_row(pause_row); + break; + } + + default: + printk(KERN_ERR "ipu_pf_ioctl not supported ioctl\n"); + retval = -1; + } + + if (retval < 0) + pr_debug("return = %d\n", retval); + return retval; +} + +/*! + * Post Filter driver mmap function. This function implements the Linux + * file_operations.mmap() API function for mapping driver buffers to user space. + * + * @param file struct file * + * + * @param vma structure vm_area_struct * + * + * @return 0 Success, EINTR busy lock error, + * ENOBUFS remap_page error. + */ +static int mxc_pf_mmap(struct file *file, struct vm_area_struct *vma) +{ + unsigned long size = vma->vm_end - vma->vm_start; + int res = 0; + + pr_debug("pgoff=0x%lx, start=0x%lx, end=0x%lx\n", + vma->vm_pgoff, vma->vm_start, vma->vm_end); + + /* make this _really_ smp-safe */ + if (down_interruptible(&pf_data.busy_lock)) + return -EINTR; + + /* make buffers write-thru cacheable */ + vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) & + ~L_PTE_BUFFERABLE); + + if (remap_pfn_range(vma, vma->vm_start, + vma->vm_pgoff, size, vma->vm_page_prot)) { + printk(KERN_ERR "mxc_pf: remap_pfn_range failed\n"); + res = -ENOBUFS; + goto mmap_exit; + } + + vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ + + mmap_exit: + up(&pf_data.busy_lock); + return res; +} + +/*! + * Post Filter driver fsync function. This function implements the Linux + * file_operations.fsync() API function. + * + * The user must call fsync() before reading an output buffer. This + * call flushes the L1 and L2 caches + * + * @param filp structure file * + * + * @param dentry struct dentry * + * + * @param datasync unused + * + * @return status POLLIN | POLLRDNORM + */ +int mxc_pf_fsync(struct file *filp, struct dentry *dentry, int datasync) +{ + flush_cache_all(); + outer_flush_all(); + return 0; +} + +/*! + * Post Filter driver poll function. This function implements the Linux + * file_operations.poll() API function. + * + * @param file structure file * + * + * @param wait structure poll_table * + * + * @return status POLLIN | POLLRDNORM + */ +static unsigned int mxc_pf_poll(struct file *file, poll_table * wait) +{ + wait_queue_head_t *queue = NULL; + int res = POLLIN | POLLRDNORM; + + if (down_interruptible(&pf_data.busy_lock)) + return -EINTR; + + queue = &pf_data.pf_wait; + poll_wait(file, queue, wait); + + up(&pf_data.busy_lock); + + return res; +} + +/*! + * File operation structure functions pointers. + */ +static struct file_operations mxc_pf_fops = { + .owner = THIS_MODULE, + .open = mxc_pf_open, + .release = mxc_pf_release, + .ioctl = mxc_pf_ioctl, + .poll = mxc_pf_poll, + .mmap = mxc_pf_mmap, + .fsync = mxc_pf_fsync, +}; + +static int mxc_pf_major; + +/*! + * Post Filter driver module initialization function. + */ +int mxc_pf_dev_init(void) +{ + int ret = 0; + struct device *temp_class; + + mxc_pf_major = register_chrdev(0, "mxc_ipu_pf", &mxc_pf_fops); + + if (mxc_pf_major < 0) { + printk(KERN_INFO "Unable to get a major for mxc_ipu_pf"); + return mxc_pf_major; + } + + mxc_pf_class = class_create(THIS_MODULE, "mxc_ipu_pf"); + if (IS_ERR(mxc_pf_class)) { + printk(KERN_ERR "Error creating mxc_ipu_pf class.\n"); + ret = PTR_ERR(mxc_pf_class); + goto err_out1; + } + + temp_class = device_create(mxc_pf_class, NULL, MKDEV(mxc_pf_major, 0), NULL, + "mxc_ipu_pf"); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "Error creating mxc_ipu_pf class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + printk(KERN_INFO "IPU Post-filter loading\n"); + + return 0; + + err_out2: + class_destroy(mxc_pf_class); + err_out1: + unregister_chrdev(mxc_pf_major, "mxc_ipu_pf"); + return ret; +} + +/*! + * Post Filter driver module exit function. + */ +static void mxc_pf_exit(void) +{ + if (mxc_pf_major > 0) { + device_destroy(mxc_pf_class, MKDEV(mxc_pf_major, 0)); + class_destroy(mxc_pf_class); + unregister_chrdev(mxc_pf_major, "mxc_ipu_pf"); + } +} + +module_init(mxc_pf_dev_init); +module_exit(mxc_pf_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC MPEG4/H.264 Postfilter Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/ipu3/Kconfig b/drivers/mxc/ipu3/Kconfig new file mode 100644 index 000000000000..0ae0ffa9e19d --- /dev/null +++ b/drivers/mxc/ipu3/Kconfig @@ -0,0 +1,5 @@ +config MXC_IPU_V3 + bool + +config MXC_IPU_V3D + bool diff --git a/drivers/mxc/ipu3/Makefile b/drivers/mxc/ipu3/Makefile new file mode 100644 index 000000000000..aa3e7b1bb501 --- /dev/null +++ b/drivers/mxc/ipu3/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_MXC_IPU_V3) = mxc_ipu.o + +mxc_ipu-objs := ipu_common.o ipu_ic.o ipu_disp.o ipu_capture.o ipu_device.o ipu_calc_stripes_sizes.o + diff --git a/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c new file mode 100644 index 000000000000..5e6a9e2f48be --- /dev/null +++ b/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c @@ -0,0 +1,374 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_calc_stripes_sizes.c + * + * @brief IPU IC functions + * + * @ingroup IPU + */ + +#include +#include +#include + +#define BPP_32 0 +#define BPP_16 3 +#define BPP_8 5 +#define BPP_24 1 +#define BPP_12 4 +#define BPP_18 2 + +static u64 _do_div(u64 a, u32 b) +{ + u64 div; + div = a; + do_div(div, b); + return div; +} + +static u32 truncate(u32 up, /* 0: down; else: up */ + u64 a, /* must be non-negative */ + u32 b) +{ + u32 d; + u64 div; + div = _do_div(a, b); + d = b * (div >> 32); + if (up && (a > (((u64)d) << 32))) + return d+b; + else + return d; +} + +static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write) +{/* return input_f */ + unsigned int f_calculated = 0; + switch (pfs) { + case IPU_PIX_FMT_YVU422P: + case IPU_PIX_FMT_YUV422P: + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + f_calculated = 16; + break; + + case IPU_PIX_FMT_NV12: + f_calculated = 8; + break; + + default: + f_calculated = 0; + break; + + } + if (!f_calculated) { + switch (bpp) { + case BPP_32: + f_calculated = 2; + break; + + case BPP_16: + f_calculated = 4; + break; + + case BPP_8: + case BPP_24: + f_calculated = 8; + break; + + case BPP_12: + f_calculated = 16; + break; + + case BPP_18: + f_calculated = 32; + break; + + default: + f_calculated = 0; + break; + } + } + return f_calculated; +} + + +static unsigned int m_calc(unsigned int pfs) +{ + unsigned int m_calculated = 0; + switch (pfs) { + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + case IPU_PIX_FMT_YVU422P: + case IPU_PIX_FMT_YUV422P: + case IPU_PIX_FMT_YVU420P: + case IPU_PIX_FMT_NV12: + m_calculated = 8; + break; + + case IPU_PIX_FMT_YUYV: + case IPU_PIX_FMT_UYVY: + m_calculated = 2; + break; + + default: + m_calculated = 1; + break; + + } + return m_calculated; +} + + +/* Stripe parameters calculator */ +/************************************************************************** +Notes: +MSW = the maximal width allowed for a stripe + i.MX31: 720, i.MX35: 800, i.MX37/51/53: 1024 +cirr = the maximal inverse resizing ratio for which overlap in the input + is requested; typically cirr~2 +equal_stripes: + 0: each stripe is allowed to have independent parameters + for maximal image quality + 1: the stripes are requested to have identical parameters + (except the base address), for maximal performance +If performance is the top priority (above image quality) + Avoid overlap, by setting CIRR = 0 + This will also force effectively identical_stripes = 1 + Choose IF & OF that corresponds to the same IOX/SX for both stripes + Choose IFW & OFW such that + IFW/IM, IFW/IF, OFW/OM, OFW/OF are even integers + The function returns an error status: + 0: no error + 1: invalid input parameters -> aborted without result + Valid parameters should satisfy the following conditions + IFW <= OFW, otherwise downsizing is required + - which is not supported yet + 4 <= IFW,OFW, so some interpolation may be needed even without overlap + IM, OM, IF, OF should not vanish + 2*IF <= IFW + so the frame can be split to two equal stripes, even without overlap + 2*(OF+IF/irr_opt) <= OFW + so a valid positive INW exists even for equal stripes + OF <= MSW, otherwise, the left stripe cannot be sufficiently large + MSW < OFW, so splitting to stripes is required + OFW <= 2*MSW, so two stripes are sufficient + (this also implies that 2<=MSW) + 2: OF is not a multiple of OM - not fully-supported yet + Output is produced but OW is not guaranited to be a multiple of OM + 4: OFW reduced to be a multiple of OM + 8: CIRR > 1: truncated to 1 + Overlap is not supported (and not needed) y for upsizing) +**************************************************************************/ +int ipu_calc_stripes_sizes(const unsigned int input_frame_width, + /* input frame width;>1 */ + unsigned int output_frame_width, /* output frame width; >1 */ + const unsigned int maximal_stripe_width, + /* the maximal width allowed for a stripe */ + const unsigned long long cirr, /* see above */ + const unsigned int equal_stripes, /* see above */ + u32 input_pixelformat,/* pixel format after of read channel*/ + u32 output_pixelformat,/* pixel format after of write channel*/ + struct stripe_param *left, + struct stripe_param *right) +{ + const unsigned int irr_frac_bits = 13; + const unsigned long irr_steps = 1 << irr_frac_bits; + const u64 dirr = ((u64)1) << (32 - 2); + /* The maximum relative difference allowed between the irrs */ + const u64 cr = ((u64)4) << 32; + /* The importance ratio between the two terms in the cost function below */ + + unsigned int status; + unsigned int temp; + unsigned int onw_min; + unsigned int inw, onw, inw_best = 0; + /* number of pixels in the left stripe NOT hidden by the right stripe */ + u64 irr_opt; /* the optimal inverse resizing ratio */ + u64 rr_opt; /* the optimal resizing ratio = 1/irr_opt*/ + u64 dinw; /* the misalignment between the stripes */ + /* (measured in units of input columns) */ + u64 difwl, difwr; + /* The number of input columns not reflected in the output */ + /* the resizing ratio used for the right stripe is */ + /* left->irr and right->irr respectively */ + u64 cost, cost_min; + u64 div; /* result of division */ + + unsigned int input_m, input_f, output_m, output_f; /* parameters for upsizing by stripes */ + + status = 0; + + /* M, F calculations */ + /* read back pfs from params */ + + input_f = f_calc(input_pixelformat, 0, NULL); + input_m = 16; + /* BPP should be used in the out_F calc */ + /* Temporarily not used */ + /* out_F = F_calc(idmac->pfs, idmac->bpp, NULL); */ + + output_f = 16; + output_m = m_calc(output_pixelformat); + + + if ((input_frame_width < 4) || (output_frame_width < 4)) + return 1; + + irr_opt = _do_div((((u64)(input_frame_width - 1)) << 32), + (output_frame_width - 1)); + rr_opt = _do_div((((u64)(output_frame_width - 1)) << 32), + (input_frame_width - 1)); + + if ((input_m == 0) || (output_m == 0) || (input_f == 0) || (output_f == 0) + || (input_frame_width < (2 * input_f)) + || ((((u64)output_frame_width) << 32) < + (2 * ((((u64)output_f) << 32) + (input_f * rr_opt)))) + || (maximal_stripe_width < output_f) + || (output_frame_width <= maximal_stripe_width) + || ((2 * maximal_stripe_width) < output_frame_width)) + return 1; + + if (output_f % output_m) + status += 2; + + temp = truncate(0, (((u64)output_frame_width) << 32), output_m); + if (temp < output_frame_width) { + output_frame_width = temp; + status += 4; + } + + if (equal_stripes) { + if ((irr_opt > cirr) /* overlap in the input is not requested */ + && ((input_frame_width % (input_m << 1)) == 0) + && ((input_frame_width % (input_f << 1)) == 0) + && ((output_frame_width % (output_m << 1)) == 0) + && ((output_frame_width % (output_f << 1)) == 0)) { + /* without overlap */ + left->input_width = right->input_width = right->input_column = + input_frame_width >> 1; + left->output_width = right->output_width = right->output_column = + output_frame_width >> 1; + left->input_column = 0; + left->output_column = 0; + div = _do_div(((((u64)irr_steps) << 32) * + (right->input_width - 1)), (right->output_width - 1)); + left->irr = right->irr = truncate(0, div, 1); + } else { /* with overlap */ + onw = truncate(0, (((u64)output_frame_width - 1) << 32) >> 1, + output_f); + inw = truncate(0, onw * irr_opt, input_f); + /* this is the maximal inw which allows the same resizing ratio */ + /* in both stripes */ + onw = truncate(1, (inw * rr_opt), output_f); + div = _do_div((((u64)(irr_steps * inw)) << + 32), onw); + left->irr = right->irr = truncate(0, div, 1); + left->output_width = right->output_width = + output_frame_width - onw; + /* These are valid assignments for output_width, */ + /* assuming output_f is a multiple of output_m */ + div = (((u64)(left->output_width-1) * (left->irr)) << 32); + div = (((u64)1) << 32) + _do_div(div, irr_steps); + + left->input_width = right->input_width = truncate(1, div, input_m); + + div = _do_div((((u64)((right->output_width - 1) * right->irr)) << + 32), irr_steps); + difwr = (((u64)(input_frame_width - 1 - inw)) << 32) - div; + div = _do_div((difwr + (((u64)input_f) << 32)), 2); + left->input_column = truncate(0, div, input_f); + + + /* This splits the truncated input columns evenly */ + /* between the left and right margins */ + right->input_column = left->input_column + inw; + left->output_column = 0; + right->output_column = onw; + } + } else { /* independent stripes */ + onw_min = output_frame_width - maximal_stripe_width; + /* onw is a multiple of output_f, in the range */ + /* [max(output_f,output_frame_width-maximal_stripe_width),*/ + /*min(output_frame_width-2,maximal_stripe_width)] */ + /* definitely beyond the cost of any valid setting */ + cost_min = (((u64)input_frame_width) << 32) + cr; + onw = truncate(0, ((u64)maximal_stripe_width), output_f); + if (output_frame_width - onw == 1) + onw -= output_f; /* => onw and output_frame_width-1-onw are positive */ + inw = truncate(0, onw * irr_opt, input_f); + /* this is the maximal inw which allows the same resizing ratio */ + /* in both stripes */ + onw = truncate(1, inw * rr_opt, output_f); + do { + div = _do_div((((u64)(irr_steps * inw)) << 32), onw); + left->irr = truncate(0, div, 1); + div = _do_div((((u64)(onw * left->irr)) << 32), + irr_steps); + dinw = (((u64)inw) << 32) - div; + + div = _do_div((((u64)((output_frame_width - 1 - onw) * left->irr)) << + 32), irr_steps); + + difwl = (((u64)(input_frame_width - 1 - inw)) << 32) - div; + + cost = difwl + (((u64)(cr * dinw)) >> 32); + + if (cost < cost_min) { + inw_best = inw; + cost_min = cost; + } + + inw -= input_f; + onw = truncate(1, inw * rr_opt, output_f); + /* This is the minimal onw which allows the same resizing ratio */ + /* in both stripes */ + } while (onw >= onw_min); + + inw = inw_best; + onw = truncate(1, inw * rr_opt, output_f); + div = _do_div((((u64)(irr_steps * inw)) << 32), onw); + left->irr = truncate(0, div, 1); + + left->output_width = onw; + right->output_width = output_frame_width - onw; + /* These are valid assignments for output_width, */ + /* assuming output_f is a multiple of output_m */ + left->input_width = truncate(1, ((u64)(inw + 1)) << 32, input_m); + right->input_width = truncate(1, ((u64)(input_frame_width - inw)) << + 32, input_m); + + div = _do_div((((u64)(irr_steps * (input_frame_width - 1 - inw))) << + 32), (right->output_width - 1)); + right->irr = truncate(0, div, 1); + temp = truncate(0, ((u64)left->irr) * ((((u64)1) << 32) + dirr), 1); + if (temp < right->irr) + right->irr = temp; + div = _do_div(((u64)((right->output_width - 1) * right->irr) << + 32), irr_steps); + difwr = (u64)(input_frame_width - 1 - inw) - div; + + + div = _do_div((difwr + (((u64)input_f) << 32)), 2); + left->input_column = truncate(0, div, input_f); + + /* This splits the truncated input columns evenly */ + /* between the left and right margins */ + right->input_column = left->input_column + inw; + left->output_column = 0; + right->output_column = onw; + } + return status; +} +EXPORT_SYMBOL(ipu_calc_stripes_sizes); diff --git a/drivers/mxc/ipu3/ipu_capture.c b/drivers/mxc/ipu3/ipu_capture.c new file mode 100644 index 000000000000..700b32b7e883 --- /dev/null +++ b/drivers/mxc/ipu3/ipu_capture.c @@ -0,0 +1,851 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_capture.c + * + * @brief IPU capture dase functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" + +/*! + * ipu_csi_init_interface + * Sets initial values for the CSI registers. + * The width and height of the sensor and the actual frame size will be + * set to the same values. + * @param width Sensor width + * @param height Sensor height + * @param pixel_fmt pixel format + * @param cfg_param ipu_csi_signal_cfg_t structure + * @param csi csi 0 or csi 1 + * + * @return 0 for success, -EINVAL for error + */ +int32_t +ipu_csi_init_interface(uint16_t width, uint16_t height, uint32_t pixel_fmt, + ipu_csi_signal_cfg_t cfg_param) +{ + uint32_t data = 0; + uint32_t csi = cfg_param.csi; + unsigned long lock_flags; + + /* Set SENS_DATA_FORMAT bits (8, 9 and 10) + RGB or YUV444 is 0 which is current value in data so not set + explicitly + This is also the default value if attempts are made to set it to + something invalid. */ + switch (pixel_fmt) { + case IPU_PIX_FMT_YUYV: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV; + break; + case IPU_PIX_FMT_UYVY: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY; + break; + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR24: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444; + break; + case IPU_PIX_FMT_GENERIC: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER; + break; + case IPU_PIX_FMT_RGB565: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565; + break; + case IPU_PIX_FMT_RGB555: + cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555; + break; + default: + return -EINVAL; + } + + /* Set the CSI_SENS_CONF register remaining fields */ + data |= cfg_param.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT | + cfg_param.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT | + cfg_param.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT | + cfg_param.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT | + cfg_param.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT | + cfg_param.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT | + cfg_param.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT | + cfg_param.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT | + cfg_param.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT | + cfg_param.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT | + cfg_param.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + __raw_writel(data, CSI_SENS_CONF(csi)); + + /* Setup sensor frame size */ + __raw_writel((width - 1) | (height - 1) << 16, CSI_SENS_FRM_SIZE(csi)); + + /* Set CCIR registers */ + if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) { + __raw_writel(0x40030, CSI_CCIR_CODE_1(csi)); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi)); + } else if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) { + if (width == 720 && height == 625) { + /* PAL case */ + /* + * Field0BlankEnd = 0x6, Field0BlankStart = 0x2, + * Field0ActiveEnd = 0x4, Field0ActiveStart = 0 + */ + __raw_writel(0x40596, CSI_CCIR_CODE_1(csi)); + /* + * Field1BlankEnd = 0x7, Field1BlankStart = 0x3, + * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1 + */ + __raw_writel(0xD07DF, CSI_CCIR_CODE_2(csi)); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi)); + } else if (width == 720 && height == 525) { + /* NTSC case */ + /* + * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, + * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 + */ + __raw_writel(0xD07DF, CSI_CCIR_CODE_1(csi)); + /* + * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, + * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 + */ + __raw_writel(0x40596, CSI_CCIR_CODE_2(csi)); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi)); + } else { + spin_unlock_irqrestore(&ipu_lock, lock_flags); + dev_err(g_ipu_dev, "Unsupported CCIR656 interlaced " + "video mode\n"); + return -EINVAL; + } + _ipu_csi_ccir_err_detection_enable(csi); + } else if ((cfg_param.clk_mode == + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR) || + (cfg_param.clk_mode == + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR) || + (cfg_param.clk_mode == + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR) || + (cfg_param.clk_mode == + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR)) { + __raw_writel(0x40030, CSI_CCIR_CODE_1(csi)); + __raw_writel(0xFF0000, CSI_CCIR_CODE_3(csi)); + _ipu_csi_ccir_err_detection_enable(csi); + } else if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_GATED_CLK) || + (cfg_param.clk_mode == IPU_CSI_CLK_MODE_NONGATED_CLK)) { + _ipu_csi_ccir_err_detection_disable(csi); + } + + dev_dbg(g_ipu_dev, "CSI_SENS_CONF = 0x%08X\n", + __raw_readl(CSI_SENS_CONF(csi))); + dev_dbg(g_ipu_dev, "CSI_ACT_FRM_SIZE = 0x%08X\n", + __raw_readl(CSI_ACT_FRM_SIZE(csi))); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_csi_init_interface); + +/*! + * ipu_csi_get_sensor_protocol + * + * @param csi csi 0 or csi 1 + * + * @return Returns sensor protocol + */ +int32_t ipu_csi_get_sensor_protocol(uint32_t csi) +{ + return (__raw_readl(CSI_SENS_CONF(csi)) & + CSI_SENS_CONF_SENS_PRTCL_MASK) >> + CSI_SENS_CONF_SENS_PRTCL_SHIFT; +} +EXPORT_SYMBOL(ipu_csi_get_sensor_protocol); + +/*! + * _ipu_csi_mclk_set + * + * @param pixel_clk desired pixel clock frequency in Hz + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_mclk_set(uint32_t pixel_clk, uint32_t csi) +{ + uint32_t temp; + uint32_t div_ratio; + + div_ratio = (clk_get_rate(g_ipu_clk) / pixel_clk) - 1; + + if (div_ratio > 0xFF || div_ratio < 0) { + dev_dbg(g_ipu_dev, "The value of pixel_clk extends normal range\n"); + return -EINVAL; + } + + temp = __raw_readl(CSI_SENS_CONF(csi)); + temp &= ~CSI_SENS_CONF_DIVRATIO_MASK; + __raw_writel(temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT), + CSI_SENS_CONF(csi)); + + return 0; +} + +/*! + * ipu_csi_enable_mclk + * + * @param csi csi 0 or csi 1 + * @param flag true to enable mclk, false to disable mclk + * @param wait true to wait 100ms make clock stable, false not wait + * + * @return Returns 0 on success + */ +int ipu_csi_enable_mclk(int csi, bool flag, bool wait) +{ + if (flag) { + clk_enable(g_csi_clk[csi]); + if (wait == true) + msleep(10); + } else { + clk_disable(g_csi_clk[csi]); + } + + return 0; +} +EXPORT_SYMBOL(ipu_csi_enable_mclk); + +/*! + * ipu_csi_get_window_size + * + * @param width pointer to window width + * @param height pointer to window height + * @param csi csi 0 or csi 1 + */ +void ipu_csi_get_window_size(uint32_t *width, uint32_t *height, uint32_t csi) +{ + uint32_t reg; + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(CSI_ACT_FRM_SIZE(csi)); + *width = (reg & 0xFFFF) + 1; + *height = (reg >> 16 & 0xFFFF) + 1; + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_csi_get_window_size); + +/*! + * ipu_csi_set_window_size + * + * @param width window width + * @param height window height + * @param csi csi 0 or csi 1 + */ +void ipu_csi_set_window_size(uint32_t width, uint32_t height, uint32_t csi) +{ + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + __raw_writel((width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_csi_set_window_size); + +/*! + * ipu_csi_set_window_pos + * + * @param left uint32 window x start + * @param top uint32 window y start + * @param csi csi 0 or csi 1 + */ +void ipu_csi_set_window_pos(uint32_t left, uint32_t top, uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp &= ~(CSI_HSC_MASK | CSI_VSC_MASK); + temp |= ((top << CSI_VSC_SHIFT) | (left << CSI_HSC_SHIFT)); + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_csi_set_window_pos); + +/*! + * _ipu_csi_horizontal_downsize_enable + * Enable horizontal downsizing(decimation) by 2. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_horizontal_downsize_enable(uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp |= CSI_HORI_DOWNSIZE_EN; + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_csi_horizontal_downsize_disable + * Disable horizontal downsizing(decimation) by 2. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_horizontal_downsize_disable(uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp &= ~CSI_HORI_DOWNSIZE_EN; + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_csi_vertical_downsize_enable + * Enable vertical downsizing(decimation) by 2. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_vertical_downsize_enable(uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp |= CSI_VERT_DOWNSIZE_EN; + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_csi_vertical_downsize_disable + * Disable vertical downsizing(decimation) by 2. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_vertical_downsize_disable(uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_OUT_FRM_CTRL(csi)); + temp &= ~CSI_VERT_DOWNSIZE_EN; + __raw_writel(temp, CSI_OUT_FRM_CTRL(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * ipu_csi_set_test_generator + * + * @param active 1 for active and 0 for inactive + * @param r_value red value for the generated pattern of even pixel + * @param g_value green value for the generated pattern of even + * pixel + * @param b_value blue value for the generated pattern of even pixel + * @param pixel_clk desired pixel clock frequency in Hz + * @param csi csi 0 or csi 1 + */ +void ipu_csi_set_test_generator(bool active, uint32_t r_value, + uint32_t g_value, uint32_t b_value, uint32_t pix_clk, uint32_t csi) +{ + uint32_t temp; + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_TST_CTRL(csi)); + + if (active == false) { + temp &= ~CSI_TEST_GEN_MODE_EN; + __raw_writel(temp, CSI_TST_CTRL(csi)); + } else { + /* Set sensb_mclk div_ratio*/ + _ipu_csi_mclk_set(pix_clk, csi); + + temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK | + CSI_TEST_GEN_B_MASK); + temp |= CSI_TEST_GEN_MODE_EN; + temp |= (r_value << CSI_TEST_GEN_R_SHIFT) | + (g_value << CSI_TEST_GEN_G_SHIFT) | + (b_value << CSI_TEST_GEN_B_SHIFT); + __raw_writel(temp, CSI_TST_CTRL(csi)); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_csi_set_test_generator); + +/*! + * _ipu_csi_ccir_err_detection_en + * Enable error detection and correction for + * CCIR interlaced mode with protection bit. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_ccir_err_detection_enable(uint32_t csi) +{ + uint32_t temp; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + temp = __raw_readl(CSI_CCIR_CODE_1(csi)); + temp |= CSI_CCIR_ERR_DET_EN; + __raw_writel(temp, CSI_CCIR_CODE_1(csi)); +} + +/*! + * _ipu_csi_ccir_err_detection_disable + * Disable error detection and correction for + * CCIR interlaced mode with protection bit. + * + * @param csi csi 0 or csi 1 + */ +void _ipu_csi_ccir_err_detection_disable(uint32_t csi) +{ + uint32_t temp; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + temp = __raw_readl(CSI_CCIR_CODE_1(csi)); + temp &= ~CSI_CCIR_ERR_DET_EN; + __raw_writel(temp, CSI_CCIR_CODE_1(csi)); +} + +/*! + * _ipu_csi_set_mipi_di + * + * @param num MIPI data identifier 0-3 handled by CSI + * @param di_val data identifier value + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_set_mipi_di(uint32_t num, uint32_t di_val, uint32_t csi) +{ + uint32_t temp; + int retval = 0; + unsigned long lock_flags; + + if (di_val > 0xFFL) { + retval = -EINVAL; + goto err; + } + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_MIPI_DI(csi)); + + switch (num) { + case IPU_CSI_MIPI_DI0: + temp &= ~CSI_MIPI_DI0_MASK; + temp |= (di_val << CSI_MIPI_DI0_SHIFT); + __raw_writel(temp, CSI_MIPI_DI(csi)); + break; + case IPU_CSI_MIPI_DI1: + temp &= ~CSI_MIPI_DI1_MASK; + temp |= (di_val << CSI_MIPI_DI1_SHIFT); + __raw_writel(temp, CSI_MIPI_DI(csi)); + break; + case IPU_CSI_MIPI_DI2: + temp &= ~CSI_MIPI_DI2_MASK; + temp |= (di_val << CSI_MIPI_DI2_SHIFT); + __raw_writel(temp, CSI_MIPI_DI(csi)); + break; + case IPU_CSI_MIPI_DI3: + temp &= ~CSI_MIPI_DI3_MASK; + temp |= (di_val << CSI_MIPI_DI3_SHIFT); + __raw_writel(temp, CSI_MIPI_DI(csi)); + break; + default: + retval = -EINVAL; + goto err; + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +err: + return retval; +} + +/*! + * _ipu_csi_set_skip_isp + * + * @param skip select frames to be skipped and set the + * correspond bits to 1 + * @param max_ratio number of frames in a skipping set and the + * maximum value of max_ratio is 5 + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_set_skip_isp(uint32_t skip, uint32_t max_ratio, uint32_t csi) +{ + uint32_t temp; + int retval = 0; + unsigned long lock_flags; + + if (max_ratio > 5) { + retval = -EINVAL; + goto err; + } + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_SKIP(csi)); + temp &= ~(CSI_MAX_RATIO_SKIP_ISP_MASK | CSI_SKIP_ISP_MASK); + temp |= (max_ratio << CSI_MAX_RATIO_SKIP_ISP_SHIFT) | + (skip << CSI_SKIP_ISP_SHIFT); + __raw_writel(temp, CSI_SKIP(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +err: + return retval; +} + +/*! + * _ipu_csi_set_skip_smfc + * + * @param skip select frames to be skipped and set the + * correspond bits to 1 + * @param max_ratio number of frames in a skipping set and the + * maximum value of max_ratio is 5 + * @param id csi to smfc skipping id + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_set_skip_smfc(uint32_t skip, uint32_t max_ratio, + uint32_t id, uint32_t csi) +{ + uint32_t temp; + int retval = 0; + unsigned long lock_flags; + + if (max_ratio > 5 || id > 3) { + retval = -EINVAL; + goto err; + } + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(CSI_SKIP(csi)); + temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK | + CSI_SKIP_SMFC_MASK); + temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) | + (id << CSI_ID_2_SKIP_SHIFT) | + (skip << CSI_SKIP_SMFC_SHIFT); + __raw_writel(temp, CSI_SKIP(csi)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +err: + return retval; +} + +/*! + * _ipu_smfc_init + * Map CSI frames to IDMAC channels. + * + * @param channel IDMAC channel 0-3 + * @param mipi_id mipi id number 0-3 + * @param csi csi0 or csi1 + */ +void _ipu_smfc_init(ipu_channel_t channel, uint32_t mipi_id, uint32_t csi) +{ + uint32_t temp; + + temp = __raw_readl(SMFC_MAP); + + switch (channel) { + case CSI_MEM0: + temp &= ~SMFC_MAP_CH0_MASK; + temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH0_SHIFT; + break; + case CSI_MEM1: + temp &= ~SMFC_MAP_CH1_MASK; + temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH1_SHIFT; + break; + case CSI_MEM2: + temp &= ~SMFC_MAP_CH2_MASK; + temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH2_SHIFT; + break; + case CSI_MEM3: + temp &= ~SMFC_MAP_CH3_MASK; + temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH3_SHIFT; + break; + default: + return; + } + + __raw_writel(temp, SMFC_MAP); +} + +/*! + * _ipu_smfc_set_wmc + * Caution: The number of required channels, the enabled channels + * and the FIFO size per channel are configured restrictedly. + * + * @param channel IDMAC channel 0-3 + * @param set set 1 or clear 0 + * @param level water mark level when FIFO is on the + * relative size + */ +void _ipu_smfc_set_wmc(ipu_channel_t channel, bool set, uint32_t level) +{ + uint32_t temp; + unsigned long lock_flags; + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(SMFC_WMC); + + switch (channel) { + case CSI_MEM0: + if (set == true) { + temp &= ~SMFC_WM0_SET_MASK; + temp |= level << SMFC_WM0_SET_SHIFT; + } else { + temp &= ~SMFC_WM0_CLR_MASK; + temp |= level << SMFC_WM0_CLR_SHIFT; + } + break; + case CSI_MEM1: + if (set == true) { + temp &= ~SMFC_WM1_SET_MASK; + temp |= level << SMFC_WM1_SET_SHIFT; + } else { + temp &= ~SMFC_WM1_CLR_MASK; + temp |= level << SMFC_WM1_CLR_SHIFT; + } + break; + case CSI_MEM2: + if (set == true) { + temp &= ~SMFC_WM2_SET_MASK; + temp |= level << SMFC_WM2_SET_SHIFT; + } else { + temp &= ~SMFC_WM2_CLR_MASK; + temp |= level << SMFC_WM2_CLR_SHIFT; + } + break; + case CSI_MEM3: + if (set == true) { + temp &= ~SMFC_WM3_SET_MASK; + temp |= level << SMFC_WM3_SET_SHIFT; + } else { + temp &= ~SMFC_WM3_CLR_MASK; + temp |= level << SMFC_WM3_CLR_SHIFT; + } + break; + default: + return; + } + + __raw_writel(temp, SMFC_WMC); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_smfc_set_burst_size + * + * @param channel IDMAC channel 0-3 + * @param bs burst size of IDMAC channel, + * the value programmed here shoud be BURST_SIZE-1 + */ +void _ipu_smfc_set_burst_size(ipu_channel_t channel, uint32_t bs) +{ + uint32_t temp; + unsigned long lock_flags; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + temp = __raw_readl(SMFC_BS); + + switch (channel) { + case CSI_MEM0: + temp &= ~SMFC_BS0_MASK; + temp |= bs << SMFC_BS0_SHIFT; + break; + case CSI_MEM1: + temp &= ~SMFC_BS1_MASK; + temp |= bs << SMFC_BS1_SHIFT; + break; + case CSI_MEM2: + temp &= ~SMFC_BS2_MASK; + temp |= bs << SMFC_BS2_SHIFT; + break; + case CSI_MEM3: + temp &= ~SMFC_BS3_MASK; + temp |= bs << SMFC_BS3_SHIFT; + break; + default: + return; + } + + __raw_writel(temp, SMFC_BS); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} + +/*! + * _ipu_csi_init + * + * @param channel IDMAC channel + * @param csi csi 0 or csi 1 + * + * @return Returns 0 on success or negative error code on fail + */ +int _ipu_csi_init(ipu_channel_t channel, uint32_t csi) +{ + uint32_t csi_sens_conf, csi_dest; + int retval = 0; + + switch (channel) { + case CSI_MEM0: + case CSI_MEM1: + case CSI_MEM2: + case CSI_MEM3: + csi_dest = CSI_DATA_DEST_IDMAC; + break; + case CSI_PRP_ENC_MEM: + case CSI_PRP_VF_MEM: + csi_dest = CSI_DATA_DEST_IC; + break; + default: + retval = -EINVAL; + goto err; + } + + csi_sens_conf = __raw_readl(CSI_SENS_CONF(csi)); + csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK; + __raw_writel(csi_sens_conf | (csi_dest << + CSI_SENS_CONF_DATA_DEST_SHIFT), CSI_SENS_CONF(csi)); +err: + return retval; +} diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c new file mode 100644 index 000000000000..1bacec010f77 --- /dev/null +++ b/drivers/mxc/ipu3/ipu_common.c @@ -0,0 +1,2644 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_common.c + * + * @brief This file contains the IPU driver common API functions. + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +struct ipu_irq_node { + irqreturn_t(*handler) (int, void *); /*!< the ISR */ + const char *name; /*!< device associated with the interrupt */ + void *dev_id; /*!< some unique information for the ISR */ + __u32 flags; /*!< not used */ +}; + +/* Globals */ +struct clk *g_ipu_clk; +bool g_ipu_clk_enabled; +struct clk *g_di_clk[2]; +struct clk *g_pixel_clk[2]; +struct clk *g_csi_clk[2]; +unsigned char g_dc_di_assignment[10]; +ipu_channel_t g_ipu_csi_channel[2]; +int g_ipu_irq[2]; +int g_ipu_hw_rev; +bool g_sec_chan_en[24]; +bool g_thrd_chan_en[24]; +bool g_chan_is_interlaced[52]; +uint32_t g_channel_init_mask; +uint32_t g_channel_enable_mask; +DEFINE_SPINLOCK(ipu_lock); +struct device *g_ipu_dev; + +static struct ipu_irq_node ipu_irq_list[IPU_IRQ_COUNT]; +static const char driver_name[] = "mxc_ipu"; + +static int ipu_dc_use_count; +static int ipu_dp_use_count; +static int ipu_dmfc_use_count; +static int ipu_smfc_use_count; +static int ipu_ic_use_count; +static int ipu_rot_use_count; +static int ipu_vdi_use_count; +static int ipu_di_use_count[2]; +static int ipu_csi_use_count[2]; +/* Set to the follow using IC direct channel, default non */ +static ipu_channel_t using_ic_dirct_ch; + +/* for power gating */ +static uint32_t ipu_conf_reg; +static uint32_t ic_conf_reg; +static uint32_t ipu_cha_db_mode_reg[4]; +static uint32_t ipu_cha_cur_buf_reg[4]; +static uint32_t idma_enable_reg[2]; +static uint32_t buf_ready_reg[8]; + +u32 *ipu_cm_reg; +u32 *ipu_idmac_reg; +u32 *ipu_dp_reg; +u32 *ipu_ic_reg; +u32 *ipu_dc_reg; +u32 *ipu_dc_tmpl_reg; +u32 *ipu_dmfc_reg; +u32 *ipu_di_reg[2]; +u32 *ipu_smfc_reg; +u32 *ipu_csi_reg[2]; +u32 *ipu_cpmem_base; +u32 *ipu_tpmem_base; +u32 *ipu_disp_base[2]; +u32 *ipu_vdi_reg; + +/* Static functions */ +static irqreturn_t ipu_irq_handler(int irq, void *desc); + +static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) +{ + return ((uint32_t) ch >> (6 * type)) & 0x3F; +}; + +static inline int _ipu_is_ic_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) && (dma_chan != 18)); +} + +static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan) +{ + return (dma_chan == 14 || dma_chan == 15); +} + +/* Either DP BG or DP FG can be graphic window */ +static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan) +{ + return (dma_chan == 23 || dma_chan == 27); +} + +static inline int _ipu_is_irt_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 45) && (dma_chan <= 50)); +} + +static inline int _ipu_is_dmfc_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 23) && (dma_chan <= 29)); +} + +static inline int _ipu_is_smfc_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 0) && (dma_chan <= 3)); +} + +#define idma_is_valid(ch) (ch != NO_DMA) +#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0) +#define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma)) + +static unsigned long _ipu_pixel_clk_get_rate(struct clk *clk) +{ + u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); + if (div == 0) + return 0; + return (clk_get_rate(clk->parent) * 16) / div; +} + +static unsigned long _ipu_pixel_clk_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div, div1; + u32 parent_rate = clk_get_rate(clk->parent) * 16; + /* + * Calculate divider + * Fractional part is 4 bits, + * so simply multiply by 2^4 to get fractional part. + */ + div = parent_rate / rate; + + if (div < 0x10) /* Min DI disp clock divider is 1 */ + div = 0x10; + if (div & ~0xFEF) + div &= 0xFF8; + else { + div1 = div & 0xFE0; + if ((parent_rate / div1 - parent_rate / div) < rate / 4) + div = div1; + else + div &= 0xFF8; + } + return parent_rate / div; +} + +static int _ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 div = (clk_get_rate(clk->parent) * 16) / rate; + + __raw_writel(div, DI_BS_CLKGEN0(clk->id)); + + /* Setup pixel clock timing */ + /* FIXME: needs to be more flexible */ + /* Down time is half of period */ + __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); + + return 0; +} + +static int _ipu_pixel_clk_enable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + + start_dvfs_per(); + + return 0; +} + +static void _ipu_pixel_clk_disable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + + start_dvfs_per(); +} + +static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) +{ + u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); + + if (parent == g_ipu_clk) + di_gen &= ~DI_GEN_DI_CLK_EXT; + else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id]) + di_gen |= DI_GEN_DI_CLK_EXT; + else + return -EINVAL; + + __raw_writel(di_gen, DI_GENERAL(clk->id)); + return 0; +} + +static struct clk pixel_clk[] = { + { + .id = 0, + .get_rate = _ipu_pixel_clk_get_rate, + .set_rate = _ipu_pixel_clk_set_rate, + .round_rate = _ipu_pixel_clk_round_rate, + .set_parent = _ipu_pixel_clk_set_parent, + .enable = _ipu_pixel_clk_enable, + .disable = _ipu_pixel_clk_disable, + }, + { + .id = 1, + .get_rate = _ipu_pixel_clk_get_rate, + .set_rate = _ipu_pixel_clk_set_rate, + .round_rate = _ipu_pixel_clk_round_rate, + .set_parent = _ipu_pixel_clk_set_parent, + .enable = _ipu_pixel_clk_enable, + .disable = _ipu_pixel_clk_disable, + }, +}; + +/*! + * This function is called by the driver framework to initialize the IPU + * hardware. + * + * @param dev The device structure for the IPU passed in by the + * driver framework. + * + * @return Returns 0 on success or negative error code on error + */ +static int ipu_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mxc_ipu_config *plat_data = pdev->dev.platform_data; + unsigned long ipu_base; + + spin_lock_init(&ipu_lock); + + g_ipu_hw_rev = plat_data->rev; + + g_ipu_dev = &pdev->dev; + + /* Register IPU interrupts */ + g_ipu_irq[0] = platform_get_irq(pdev, 0); + if (g_ipu_irq[0] < 0) + return -EINVAL; + + if (request_irq(g_ipu_irq[0], ipu_irq_handler, 0, pdev->name, 0) != 0) { + dev_err(g_ipu_dev, "request SYNC interrupt failed\n"); + return -EBUSY; + } + /* Some platforms have 2 IPU interrupts */ + g_ipu_irq[1] = platform_get_irq(pdev, 1); + if (g_ipu_irq[1] >= 0) { + if (request_irq + (g_ipu_irq[1], ipu_irq_handler, 0, pdev->name, 0) != 0) { + dev_err(g_ipu_dev, "request ERR interrupt failed\n"); + return -EBUSY; + } + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) + return -ENODEV; + + ipu_base = res->start; + if (g_ipu_hw_rev == 3) /* IPUv3M */ + ipu_base += IPUV3M_REG_BASE; + else /* IPUv3D, v3E, v3EX */ + ipu_base += IPU_REG_BASE; + + ipu_cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE); + ipu_ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE); + ipu_idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE); + /* DP Registers are accessed thru the SRM */ + ipu_dp_reg = ioremap(ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE); + ipu_dc_reg = ioremap(ipu_base + IPU_DC_REG_BASE, PAGE_SIZE); + ipu_dmfc_reg = ioremap(ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE); + ipu_di_reg[0] = ioremap(ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE); + ipu_di_reg[1] = ioremap(ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE); + ipu_smfc_reg = ioremap(ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE); + ipu_csi_reg[0] = ioremap(ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE); + ipu_csi_reg[1] = ioremap(ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE); + ipu_cpmem_base = ioremap(ipu_base + IPU_CPMEM_REG_BASE, PAGE_SIZE); + ipu_tpmem_base = ioremap(ipu_base + IPU_TPM_REG_BASE, SZ_64K); + ipu_dc_tmpl_reg = ioremap(ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K); + ipu_disp_base[1] = ioremap(ipu_base + IPU_DISP1_BASE, SZ_4K); + ipu_vdi_reg = ioremap(ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE); + + dev_dbg(g_ipu_dev, "IPU VDI Regs = %p\n", ipu_vdi_reg); + dev_dbg(g_ipu_dev, "IPU CM Regs = %p\n", ipu_cm_reg); + dev_dbg(g_ipu_dev, "IPU IC Regs = %p\n", ipu_ic_reg); + dev_dbg(g_ipu_dev, "IPU IDMAC Regs = %p\n", ipu_idmac_reg); + dev_dbg(g_ipu_dev, "IPU DP Regs = %p\n", ipu_dp_reg); + dev_dbg(g_ipu_dev, "IPU DC Regs = %p\n", ipu_dc_reg); + dev_dbg(g_ipu_dev, "IPU DMFC Regs = %p\n", ipu_dmfc_reg); + dev_dbg(g_ipu_dev, "IPU DI0 Regs = %p\n", ipu_di_reg[0]); + dev_dbg(g_ipu_dev, "IPU DI1 Regs = %p\n", ipu_di_reg[1]); + dev_dbg(g_ipu_dev, "IPU SMFC Regs = %p\n", ipu_smfc_reg); + dev_dbg(g_ipu_dev, "IPU CSI0 Regs = %p\n", ipu_csi_reg[0]); + dev_dbg(g_ipu_dev, "IPU CSI1 Regs = %p\n", ipu_csi_reg[1]); + dev_dbg(g_ipu_dev, "IPU CPMem = %p\n", ipu_cpmem_base); + dev_dbg(g_ipu_dev, "IPU TPMem = %p\n", ipu_tpmem_base); + dev_dbg(g_ipu_dev, "IPU DC Template Mem = %p\n", ipu_dc_tmpl_reg); + dev_dbg(g_ipu_dev, "IPU Display Region 1 Mem = %p\n", ipu_disp_base[1]); + + g_pixel_clk[0] = &pixel_clk[0]; + g_pixel_clk[1] = &pixel_clk[1]; + + /* Enable IPU and CSI clocks */ + /* Get IPU clock freq */ + g_ipu_clk = clk_get(&pdev->dev, "ipu_clk"); + dev_dbg(g_ipu_dev, "ipu_clk = %lu\n", clk_get_rate(g_ipu_clk)); + + if (plat_data->reset) + plat_data->reset(); + + clk_set_parent(g_pixel_clk[0], g_ipu_clk); + clk_set_parent(g_pixel_clk[1], g_ipu_clk); + clk_enable(g_ipu_clk); + + g_di_clk[0] = plat_data->di_clk[0]; + g_di_clk[1] = plat_data->di_clk[1]; + + g_csi_clk[0] = plat_data->csi_clk[0]; + g_csi_clk[1] = plat_data->csi_clk[1]; + + __raw_writel(0x807FFFFF, IPU_MEM_RST); + while (__raw_readl(IPU_MEM_RST) & 0x80000000) + ; + + _ipu_init_dc_mappings(); + + /* Enable error interrupts by default */ + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10)); + + /* DMFC Init */ + _ipu_dmfc_init(DMFC_NORMAL, 1); + + /* Set sync refresh channels and CSI->mem channel as high priority */ + __raw_writel(0x18800001L, IDMAC_CHA_PRI(0)); + + /* Set MCU_T to divide MCU access window into 2 */ + __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); + + clk_disable(g_ipu_clk); + + register_ipu_device(); + + return 0; +} + +int ipu_remove(struct platform_device *pdev) +{ + if (g_ipu_irq[0]) + free_irq(g_ipu_irq[0], 0); + if (g_ipu_irq[1]) + free_irq(g_ipu_irq[1], 0); + + clk_put(g_ipu_clk); + + iounmap(ipu_cm_reg); + iounmap(ipu_ic_reg); + iounmap(ipu_idmac_reg); + iounmap(ipu_dc_reg); + iounmap(ipu_dp_reg); + iounmap(ipu_dmfc_reg); + iounmap(ipu_di_reg[0]); + iounmap(ipu_di_reg[1]); + iounmap(ipu_smfc_reg); + iounmap(ipu_csi_reg[0]); + iounmap(ipu_csi_reg[1]); + iounmap(ipu_cpmem_base); + iounmap(ipu_tpmem_base); + iounmap(ipu_dc_tmpl_reg); + iounmap(ipu_disp_base[1]); + iounmap(ipu_vdi_reg); + + return 0; +} + +void ipu_dump_registers(void) +{ + printk(KERN_DEBUG "IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF)); + printk(KERN_DEBUG "IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF)); + printk(KERN_DEBUG "IDMAC_CHA_EN1 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_EN(0))); + printk(KERN_DEBUG "IDMAC_CHA_EN2 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_EN(32))); + printk(KERN_DEBUG "IDMAC_CHA_PRI1 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_PRI(0))); + printk(KERN_DEBUG "IDMAC_CHA_PRI2 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_PRI(32))); + printk(KERN_DEBUG "IDMAC_BAND_EN1 = \t0x%08X\n", + __raw_readl(IDMAC_BAND_EN(0))); + printk(KERN_DEBUG "IDMAC_BAND_EN2 = \t0x%08X\n", + __raw_readl(IDMAC_BAND_EN(32))); + printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", + __raw_readl(IPU_CHA_DB_MODE_SEL(0))); + printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", + __raw_readl(IPU_CHA_DB_MODE_SEL(32))); + printk(KERN_DEBUG "DMFC_WR_CHAN = \t0x%08X\n", + __raw_readl(DMFC_WR_CHAN)); + printk(KERN_DEBUG "DMFC_WR_CHAN_DEF = \t0x%08X\n", + __raw_readl(DMFC_WR_CHAN_DEF)); + printk(KERN_DEBUG "DMFC_DP_CHAN = \t0x%08X\n", + __raw_readl(DMFC_DP_CHAN)); + printk(KERN_DEBUG "DMFC_DP_CHAN_DEF = \t0x%08X\n", + __raw_readl(DMFC_DP_CHAN_DEF)); + printk(KERN_DEBUG "DMFC_IC_CTRL = \t0x%08X\n", + __raw_readl(DMFC_IC_CTRL)); + printk(KERN_DEBUG "IPU_FS_PROC_FLOW1 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW1)); + printk(KERN_DEBUG "IPU_FS_PROC_FLOW2 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW2)); + printk(KERN_DEBUG "IPU_FS_PROC_FLOW3 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW3)); + printk(KERN_DEBUG "IPU_FS_DISP_FLOW1 = \t0x%08X\n", + __raw_readl(IPU_FS_DISP_FLOW1)); +} + +/*! + * This function is called to initialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to init. + * + * @param params Input parameter containing union of channel + * initialization parameters. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params) +{ + int ret = 0; + uint32_t ipu_conf; + uint32_t reg; + unsigned long lock_flags; + + dev_dbg(g_ipu_dev, "init channel = %d\n", IPU_CHAN_ID(channel)); + + /* re-enable error interrupts every time a channel is initialized */ + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9)); + __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10)); + + if (g_ipu_clk_enabled == false) { + stop_dvfs_per(); + g_ipu_clk_enabled = true; + clk_enable(g_ipu_clk); + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) { + dev_err(g_ipu_dev, "Warning: channel already initialized %d\n", + IPU_CHAN_ID(channel)); + } + + ipu_conf = __raw_readl(IPU_CONF); + + switch (channel) { + case CSI_MEM0: + case CSI_MEM1: + case CSI_MEM2: + case CSI_MEM3: + if (params->csi_mem.csi > 1) { + ret = -EINVAL; + goto err; + } + + if (params->csi_mem.interlaced) + g_chan_is_interlaced[channel_2_dma(channel, + IPU_OUTPUT_BUFFER)] = true; + else + g_chan_is_interlaced[channel_2_dma(channel, + IPU_OUTPUT_BUFFER)] = false; + + ipu_smfc_use_count++; + g_ipu_csi_channel[params->csi_mem.csi] = channel; + + /*SMFC setting*/ + if (params->csi_mem.mipi_en) { + ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_mem.csi)); + _ipu_smfc_init(channel, params->csi_mem.mipi_id, + params->csi_mem.csi); + } else { + ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_mem.csi)); + _ipu_smfc_init(channel, 0, params->csi_mem.csi); + } + + /*CSI data (include compander) dest*/ + _ipu_csi_init(channel, params->csi_mem.csi); + break; + case CSI_PRP_ENC_MEM: + if (params->csi_prp_enc_mem.csi > 1) { + ret = -EINVAL; + goto err; + } + if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) { + ret = -EINVAL; + goto err; + } + using_ic_dirct_ch = CSI_PRP_ENC_MEM; + + ipu_ic_use_count++; + g_ipu_csi_channel[params->csi_prp_enc_mem.csi] = channel; + + /*Without SMFC, CSI only support parallel data source*/ + ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_prp_enc_mem.csi)); + + /*CSI0/1 feed into IC*/ + ipu_conf &= ~IPU_CONF_IC_INPUT; + if (params->csi_prp_enc_mem.csi) + ipu_conf |= IPU_CONF_CSI_SEL; + else + ipu_conf &= ~IPU_CONF_CSI_SEL; + + /*PRP skip buffer in memory, only valid when RWS_EN is true*/ + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1); + + /*CSI data (include compander) dest*/ + _ipu_csi_init(channel, params->csi_prp_enc_mem.csi); + _ipu_ic_init_prpenc(params, true); + break; + case CSI_PRP_VF_MEM: + if (params->csi_prp_vf_mem.csi > 1) { + ret = -EINVAL; + goto err; + } + if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) { + ret = -EINVAL; + goto err; + } + using_ic_dirct_ch = CSI_PRP_VF_MEM; + + ipu_ic_use_count++; + g_ipu_csi_channel[params->csi_prp_vf_mem.csi] = channel; + + /*Without SMFC, CSI only support parallel data source*/ + ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET + + params->csi_prp_vf_mem.csi)); + + /*CSI0/1 feed into IC*/ + ipu_conf &= ~IPU_CONF_IC_INPUT; + if (params->csi_prp_vf_mem.csi) + ipu_conf |= IPU_CONF_CSI_SEL; + else + ipu_conf &= ~IPU_CONF_CSI_SEL; + + /*PRP skip buffer in memory, only valid when RWS_EN is true*/ + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1); + + /*CSI data (include compander) dest*/ + _ipu_csi_init(channel, params->csi_prp_vf_mem.csi); + _ipu_ic_init_prpvf(params, true); + break; + case MEM_PRP_VF_MEM: + ipu_ic_use_count++; + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1); + + if (params->mem_prp_vf_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + if (params->mem_prp_vf_mem.alpha_chan_en) + g_thrd_chan_en[IPU_CHAN_ID(channel)] = true; + + _ipu_ic_init_prpvf(params, false); + break; + case MEM_VDI_PRP_VF_MEM: + if ((using_ic_dirct_ch == CSI_PRP_VF_MEM) || + (using_ic_dirct_ch == CSI_PRP_ENC_MEM)) { + ret = -EINVAL; + goto err; + } + using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM; + ipu_ic_use_count++; + ipu_vdi_use_count++; + reg = __raw_readl(IPU_FS_PROC_FLOW1); + reg &= ~FS_VDI_SRC_SEL_MASK; + __raw_writel(reg , IPU_FS_PROC_FLOW1); + + if (params->mem_prp_vf_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + _ipu_ic_init_prpvf(params, false); + _ipu_vdi_init(channel, params); + break; + case MEM_VDI_PRP_VF_MEM_P: + _ipu_vdi_init(channel, params); + break; + case MEM_VDI_PRP_VF_MEM_N: + _ipu_vdi_init(channel, params); + break; + case MEM_ROT_VF_MEM: + ipu_ic_use_count++; + ipu_rot_use_count++; + _ipu_ic_init_rotate_vf(params); + break; + case MEM_PRP_ENC_MEM: + ipu_ic_use_count++; + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1); + _ipu_ic_init_prpenc(params, false); + break; + case MEM_ROT_ENC_MEM: + ipu_ic_use_count++; + ipu_rot_use_count++; + _ipu_ic_init_rotate_enc(params); + break; + case MEM_PP_MEM: + if (params->mem_pp_mem.graphics_combine_en) + g_sec_chan_en[IPU_CHAN_ID(channel)] = true; + if (params->mem_pp_mem.alpha_chan_en) + g_thrd_chan_en[IPU_CHAN_ID(channel)] = true; + _ipu_ic_init_pp(params); + ipu_ic_use_count++; + break; + case MEM_ROT_PP_MEM: + _ipu_ic_init_rotate_pp(params); + ipu_ic_use_count++; + ipu_rot_use_count++; + break; + case MEM_DC_SYNC: + if (params->mem_dc_sync.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[1] = params->mem_dc_sync.di; + _ipu_dc_init(1, params->mem_dc_sync.di, + params->mem_dc_sync.interlaced, + params->mem_dc_sync.out_pixel_fmt); + ipu_di_use_count[params->mem_dc_sync.di]++; + ipu_dc_use_count++; + ipu_dmfc_use_count++; + break; + case MEM_BG_SYNC: + if (params->mem_dp_bg_sync.di > 1) { + ret = -EINVAL; + goto err; + } + + if (params->mem_dp_bg_sync.alpha_chan_en) + g_thrd_chan_en[IPU_CHAN_ID(channel)] = true; + + g_dc_di_assignment[5] = params->mem_dp_bg_sync.di; + _ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt, + params->mem_dp_bg_sync.out_pixel_fmt); + _ipu_dc_init(5, params->mem_dp_bg_sync.di, + params->mem_dp_bg_sync.interlaced, + params->mem_dp_bg_sync.out_pixel_fmt); + ipu_di_use_count[params->mem_dp_bg_sync.di]++; + ipu_dc_use_count++; + ipu_dp_use_count++; + ipu_dmfc_use_count++; + break; + case MEM_FG_SYNC: + _ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt, + params->mem_dp_fg_sync.out_pixel_fmt); + + if (params->mem_dp_fg_sync.alpha_chan_en) + g_thrd_chan_en[IPU_CHAN_ID(channel)] = true; + + ipu_dc_use_count++; + ipu_dp_use_count++; + ipu_dmfc_use_count++; + break; + case DIRECT_ASYNC0: + if (params->direct_async.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[8] = params->direct_async.di; + _ipu_dc_init(8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC); + ipu_di_use_count[params->direct_async.di]++; + ipu_dc_use_count++; + break; + case DIRECT_ASYNC1: + if (params->direct_async.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[9] = params->direct_async.di; + _ipu_dc_init(9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC); + ipu_di_use_count[params->direct_async.di]++; + ipu_dc_use_count++; + break; + default: + dev_err(g_ipu_dev, "Missing channel initialization\n"); + break; + } + + /* Enable IPU sub module */ + g_channel_init_mask |= 1L << IPU_CHAN_ID(channel); + + __raw_writel(ipu_conf, IPU_CONF); + +err: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return ret; +} +EXPORT_SYMBOL(ipu_init_channel); + +/*! + * This function is called to uninitialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to uninit. + */ +void ipu_uninit_channel(ipu_channel_t channel) +{ + unsigned long lock_flags; + uint32_t reg; + uint32_t in_dma, out_dma = 0; + uint32_t ipu_conf; + + if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + dev_err(g_ipu_dev, "Channel already uninitialized %d\n", + IPU_CHAN_ID(channel)); + return; + } + + /* Make sure channel is disabled */ + /* Get input and output dma channels */ + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + + if (idma_is_set(IDMAC_CHA_EN, in_dma) || + idma_is_set(IDMAC_CHA_EN, out_dma)) { + dev_err(g_ipu_dev, + "Channel %d is not disabled, disable first\n", + IPU_CHAN_ID(channel)); + return; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + ipu_conf = __raw_readl(IPU_CONF); + + /* Reset the double buffer */ + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma)); + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma)); + __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma)); + + if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) { + g_sec_chan_en[IPU_CHAN_ID(channel)] = false; + g_thrd_chan_en[IPU_CHAN_ID(channel)] = false; + } + + switch (channel) { + case CSI_MEM0: + case CSI_MEM1: + case CSI_MEM2: + case CSI_MEM3: + ipu_smfc_use_count--; + if (g_ipu_csi_channel[0] == channel) { + g_ipu_csi_channel[0] = CHAN_NONE; + } else if (g_ipu_csi_channel[1] == channel) { + g_ipu_csi_channel[1] = CHAN_NONE; + } + break; + case CSI_PRP_ENC_MEM: + ipu_ic_use_count--; + if (using_ic_dirct_ch == CSI_PRP_ENC_MEM) + using_ic_dirct_ch = 0; + _ipu_ic_uninit_prpenc(); + if (g_ipu_csi_channel[0] == channel) { + g_ipu_csi_channel[0] = CHAN_NONE; + } else if (g_ipu_csi_channel[1] == channel) { + g_ipu_csi_channel[1] = CHAN_NONE; + } + break; + case CSI_PRP_VF_MEM: + ipu_ic_use_count--; + if (using_ic_dirct_ch == CSI_PRP_VF_MEM) + using_ic_dirct_ch = 0; + _ipu_ic_uninit_prpvf(); + if (g_ipu_csi_channel[0] == channel) { + g_ipu_csi_channel[0] = CHAN_NONE; + } else if (g_ipu_csi_channel[1] == channel) { + g_ipu_csi_channel[1] = CHAN_NONE; + } + break; + case MEM_PRP_VF_MEM: + ipu_ic_use_count--; + _ipu_ic_uninit_prpvf(); + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1); + break; + case MEM_VDI_PRP_VF_MEM: + ipu_ic_use_count--; + ipu_vdi_use_count--; + if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) + using_ic_dirct_ch = 0; + _ipu_ic_uninit_prpvf(); + _ipu_vdi_uninit(); + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1); + break; + case MEM_VDI_PRP_VF_MEM_P: + case MEM_VDI_PRP_VF_MEM_N: + break; + case MEM_ROT_VF_MEM: + ipu_rot_use_count--; + ipu_ic_use_count--; + _ipu_ic_uninit_rotate_vf(); + break; + case MEM_PRP_ENC_MEM: + ipu_ic_use_count--; + _ipu_ic_uninit_prpenc(); + reg = __raw_readl(IPU_FS_PROC_FLOW1); + __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1); + break; + case MEM_ROT_ENC_MEM: + ipu_rot_use_count--; + ipu_ic_use_count--; + _ipu_ic_uninit_rotate_enc(); + break; + case MEM_PP_MEM: + ipu_ic_use_count--; + _ipu_ic_uninit_pp(); + break; + case MEM_ROT_PP_MEM: + ipu_rot_use_count--; + ipu_ic_use_count--; + _ipu_ic_uninit_rotate_pp(); + break; + case MEM_DC_SYNC: + _ipu_dc_uninit(1); + ipu_di_use_count[g_dc_di_assignment[1]]--; + ipu_dc_use_count--; + ipu_dmfc_use_count--; + break; + case MEM_BG_SYNC: + _ipu_dp_uninit(channel); + _ipu_dc_uninit(5); + ipu_di_use_count[g_dc_di_assignment[5]]--; + ipu_dc_use_count--; + ipu_dp_use_count--; + ipu_dmfc_use_count--; + break; + case MEM_FG_SYNC: + _ipu_dp_uninit(channel); + ipu_dc_use_count--; + ipu_dp_use_count--; + ipu_dmfc_use_count--; + break; + case DIRECT_ASYNC0: + _ipu_dc_uninit(8); + ipu_di_use_count[g_dc_di_assignment[8]]--; + ipu_dc_use_count--; + break; + case DIRECT_ASYNC1: + _ipu_dc_uninit(9); + ipu_di_use_count[g_dc_di_assignment[9]]--; + ipu_dc_use_count--; + break; + default: + break; + } + + g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel)); + + if (ipu_ic_use_count == 0) + ipu_conf &= ~IPU_CONF_IC_EN; + if (ipu_vdi_use_count == 0) { + ipu_conf &= ~IPU_CONF_ISP_EN; + ipu_conf &= ~IPU_CONF_VDI_EN; + ipu_conf &= ~IPU_CONF_IC_INPUT; + } + if (ipu_rot_use_count == 0) + ipu_conf &= ~IPU_CONF_ROT_EN; + if (ipu_dc_use_count == 0) + ipu_conf &= ~IPU_CONF_DC_EN; + if (ipu_dp_use_count == 0) + ipu_conf &= ~IPU_CONF_DP_EN; + if (ipu_dmfc_use_count == 0) + ipu_conf &= ~IPU_CONF_DMFC_EN; + if (ipu_di_use_count[0] == 0) { + ipu_conf &= ~IPU_CONF_DI0_EN; + } + if (ipu_di_use_count[1] == 0) { + ipu_conf &= ~IPU_CONF_DI1_EN; + } + if (ipu_smfc_use_count == 0) + ipu_conf &= ~IPU_CONF_SMFC_EN; + + __raw_writel(ipu_conf, IPU_CONF); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + if (ipu_conf == 0) { + clk_disable(g_ipu_clk); + g_ipu_clk_enabled = false; + } + + WARN_ON(ipu_ic_use_count < 0); + WARN_ON(ipu_vdi_use_count < 0); + WARN_ON(ipu_rot_use_count < 0); + WARN_ON(ipu_dc_use_count < 0); + WARN_ON(ipu_dp_use_count < 0); + WARN_ON(ipu_dmfc_use_count < 0); + WARN_ON(ipu_smfc_use_count < 0); +} +EXPORT_SYMBOL(ipu_uninit_channel); + +/*! + * This function is called to initialize a buffer for logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width Input parameter for width of buffer in pixels. + * + * @param height Input parameter for height of buffer in pixels. + * + * @param stride Input parameter for stride length of buffer + * in pixels. + * + * @param rot_mode Input parameter for rotation setting of buffer. + * A rotation setting other than + * IPU_ROTATE_VERT_FLIP + * should only be used for input buffers of + * rotation channels. + * + * @param phyaddr_0 Input parameter buffer 0 physical address. + * + * @param phyaddr_1 Input parameter buffer 1 physical address. + * Setting this to a value other than NULL enables + * double buffering mode. + * + * @param u private u offset for additional cropping, + * zero if not used. + * + * @param v private v offset for additional cropping, + * zero if not used. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u, uint32_t v) +{ + unsigned long lock_flags; + uint32_t reg; + uint32_t dma_chan; + uint32_t burst_size; + + dma_chan = channel_2_dma(channel, type); + if (!idma_is_valid(dma_chan)) + return -EINVAL; + + if (stride < width * bytes_per_pixel(pixel_fmt)) + stride = width * bytes_per_pixel(pixel_fmt); + + if (stride % 4) { + dev_err(g_ipu_dev, + "Stride not 32-bit aligned, stride = %d\n", stride); + return -EINVAL; + } + /* IC & IRT channels' width must be multiple of 8 pixels */ + if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) + && (width % 8)) { + dev_err(g_ipu_dev, "Width must be 8 pixel multiple\n"); + return -EINVAL; + } + + /* Build parameter memory data for DMA channel */ + _ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0, + phyaddr_0, phyaddr_1); + + /* Set correlative channel parameter of local alpha channel */ + if ((_ipu_is_ic_graphic_chan(dma_chan) || + _ipu_is_dp_graphic_chan(dma_chan)) && + (g_thrd_chan_en[IPU_CHAN_ID(channel)] == true)) { + _ipu_ch_param_set_alpha_use_separate_channel(dma_chan, true); + _ipu_ch_param_set_alpha_buffer_memory(dma_chan); + _ipu_ch_param_set_alpha_condition_read(dma_chan); + /* fix alpha width as 8 and burst size as 16*/ + _ipu_ch_params_set_alpha_width(dma_chan, 8); + _ipu_ch_param_set_burst_size(dma_chan, 16); + } else if (_ipu_is_ic_graphic_chan(dma_chan) && + ipu_pixel_format_has_alpha(pixel_fmt)) + _ipu_ch_param_set_alpha_use_separate_channel(dma_chan, false); + + if (rot_mode) + _ipu_ch_param_set_rotation(dma_chan, rot_mode); + + /* IC and ROT channels have restriction of 8 or 16 pix burst length */ + if (_ipu_is_ic_chan(dma_chan)) { + if ((width % 16) == 0) + _ipu_ch_param_set_burst_size(dma_chan, 16); + else + _ipu_ch_param_set_burst_size(dma_chan, 8); + } else if (_ipu_is_irt_chan(dma_chan)) { + _ipu_ch_param_set_burst_size(dma_chan, 8); + _ipu_ch_param_set_block_mode(dma_chan); + } else if (_ipu_is_dmfc_chan(dma_chan)) { + u32 dmfc_dp_chan, dmfc_wr_chan; + /* + * non-interleaving format need enlarge burst size + * to work-around black flash issue. + */ + if (((dma_chan == 23) || (dma_chan == 27) || (dma_chan == 28)) + && ((pixel_fmt == IPU_PIX_FMT_YUV420P) || + (pixel_fmt == IPU_PIX_FMT_YUV420P2) || + (pixel_fmt == IPU_PIX_FMT_YVU422P) || + (pixel_fmt == IPU_PIX_FMT_YUV422P) || + (pixel_fmt == IPU_PIX_FMT_NV12))) { + if (dma_chan == 23) { + dmfc_dp_chan = __raw_readl(DMFC_DP_CHAN); + dmfc_dp_chan &= ~(0xc0); + dmfc_dp_chan |= 0x40; + __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); + } else if (dma_chan == 27) { + dmfc_dp_chan = __raw_readl(DMFC_DP_CHAN); + dmfc_dp_chan &= ~(0xc000); + dmfc_dp_chan |= 0x4000; + __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); + } else if (dma_chan == 28) { + dmfc_wr_chan = __raw_readl(DMFC_WR_CHAN); + dmfc_wr_chan &= ~(0xc0); + dmfc_wr_chan |= 0x40; + __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); + } + _ipu_ch_param_set_burst_size(dma_chan, 64); + } else { + if (dma_chan == 23) { + dmfc_dp_chan = __raw_readl(DMFC_DP_CHAN); + dmfc_dp_chan &= ~(0xc0); + dmfc_dp_chan |= 0x80; + __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); + } else if (dma_chan == 27) { + dmfc_dp_chan = __raw_readl(DMFC_DP_CHAN); + dmfc_dp_chan &= ~(0xc000); + dmfc_dp_chan |= 0x8000; + __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); + } else { + dmfc_wr_chan = __raw_readl(DMFC_WR_CHAN); + dmfc_wr_chan &= ~(0xc0); + dmfc_wr_chan |= 0x80; + __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); + } + } + spin_lock_irqsave(&ipu_lock, lock_flags); + _ipu_dmfc_set_wait4eot(dma_chan, width); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + } + + if (_ipu_disp_chan_is_interlaced(channel) || + g_chan_is_interlaced[dma_chan]) + _ipu_ch_param_set_interlaced_scan(dma_chan); + + if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) { + burst_size = _ipu_ch_param_get_burst_size(dma_chan); + _ipu_ic_idma_init(dma_chan, width, height, burst_size, + rot_mode); + } else if (_ipu_is_smfc_chan(dma_chan)) { + burst_size = _ipu_ch_param_get_burst_size(dma_chan); + if ((pixel_fmt == IPU_PIX_FMT_GENERIC) && + ((_ipu_ch_param_get_bpp(dma_chan) == 5) || + (_ipu_ch_param_get_bpp(dma_chan) == 3))) + burst_size = burst_size >> 4; + else + burst_size = burst_size >> 2; + _ipu_smfc_set_burst_size(channel, burst_size-1); + } + + if (idma_is_set(IDMAC_CHA_PRI, dma_chan) && !cpu_is_mx53()) + _ipu_ch_param_set_high_priority(dma_chan); + + _ipu_ch_param_dump(dma_chan); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan)); + if (phyaddr_1) + reg |= idma_mask(dma_chan); + else + reg &= ~idma_mask(dma_chan); + __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan)); + + /* Reset to buffer 0 */ + __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_init_channel_buffer); + +/*! + * This function is called to update the physical address of a buffer for + * a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param bufNum Input parameter for buffer number to update. + * 0 or 1 are the only valid values. + * + * @param phyaddr Input parameter buffer physical address. + * + * @return This function returns 0 on success or negative error code on + * fail. This function will fail if the buffer is set to ready. + */ +int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr) +{ + uint32_t reg; + int ret = 0; + unsigned long lock_flags; + uint32_t dma_chan = channel_2_dma(channel, type); + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (bufNum == 0) + reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan)); + else + reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan)); + + if ((reg & idma_mask(dma_chan)) == 0) + _ipu_ch_param_set_buffer(dma_chan, bufNum, phyaddr); + else + ret = -EACCES; + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return ret; +} +EXPORT_SYMBOL(ipu_update_channel_buffer); + + +/*! + * This function is called to initialize a buffer for logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width Input parameter for width of buffer in pixels. + * + * @param height Input parameter for height of buffer in pixels. + * + * @param stride Input parameter for stride length of buffer + * in pixels. + * + * @param u predefined private u offset for additional cropping, + * zero if not used. + * + * @param v predefined private v offset for additional cropping, + * zero if not used. + * + * @param vertical_offset vertical offset for Y coordinate + * in the existed frame + * + * + * @param horizontal_offset horizontal offset for X coordinate + * in the existed frame + * + * + * @return Returns 0 on success or negative error code on fail + * This function will fail if any buffer is set to ready. + */ + +int32_t ipu_update_channel_offset(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset) +{ + int ret = 0; + unsigned long lock_flags; + uint32_t dma_chan = channel_2_dma(channel, type); + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if ((__raw_readl(IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) || + (__raw_readl(IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan))) + ret = -EACCES; + else + _ipu_ch_offset_update(dma_chan, pixel_fmt, width, height, stride, + u, v, 0, vertical_offset, horizontal_offset); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return ret; +} +EXPORT_SYMBOL(ipu_update_channel_offset); + + +/*! + * This function is called to set a channel's buffer as ready. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param bufNum Input parameter for which buffer number set to + * ready state. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + uint32_t dma_chan = channel_2_dma(channel, type); + uint32_t reg; + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + if (bufNum == 0) { + /*Mark buffer 0 as ready. */ + reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan)); + __raw_writel(idma_mask(dma_chan) | reg, + IPU_CHA_BUF0_RDY(dma_chan)); + } else { + /*Mark buffer 1 as ready. */ + reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan)); + __raw_writel(idma_mask(dma_chan) | reg, + IPU_CHA_BUF1_RDY(dma_chan)); + } + return 0; +} +EXPORT_SYMBOL(ipu_select_buffer); + +/*! + * This function is called to set a channel's buffer as ready. + * + * @param bufNum Input parameter for which buffer number set to + * ready state. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_select_multi_vdi_buffer(uint32_t bufNum) +{ + + uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER); + uint32_t mask_bit = + idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))| + idma_mask(dma_chan)| + idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER)); + uint32_t reg; + + if (bufNum == 0) { + /*Mark buffer 0 as ready. */ + reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan)); + __raw_writel(mask_bit | reg, IPU_CHA_BUF0_RDY(dma_chan)); + } else { + /*Mark buffer 1 as ready. */ + reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan)); + __raw_writel(mask_bit | reg, IPU_CHA_BUF1_RDY(dma_chan)); + } + return 0; +} +EXPORT_SYMBOL(ipu_select_multi_vdi_buffer); + +#define NA -1 +static int proc_dest_sel[] = { + 0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16, + 0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 }; +static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA, + NA, NA, NA, NA, NA, 1, 2, 3, 4, 7, 8, NA, 8, NA }; +static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA, + NA, NA, NA, NA, NA, 1, NA, 2, NA, 3, 4, 4, 4, 4 }; + + +/*! + * This function links 2 channels together for automatic frame + * synchronization. The output of the source channel is linked to the input of + * the destination channel. + * + * @param src_ch Input parameter for the logical channel ID of + * the source channel. + * + * @param dest_ch Input parameter for the logical channel ID of + * the destination channel. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch) +{ + int retval = 0; + unsigned long lock_flags; + uint32_t fs_proc_flow1; + uint32_t fs_proc_flow2; + uint32_t fs_proc_flow3; + uint32_t fs_disp_flow1; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1); + fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2); + fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3); + fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1); + + switch (src_ch) { + case CSI_MEM0: + fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK; + fs_proc_flow3 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_SMFC0_DEST_SEL_OFFSET; + break; + case CSI_MEM1: + fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK; + fs_proc_flow3 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_SMFC1_DEST_SEL_OFFSET; + break; + case CSI_MEM2: + fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK; + fs_proc_flow3 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_SMFC2_DEST_SEL_OFFSET; + break; + case CSI_MEM3: + fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK; + fs_proc_flow3 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_SMFC3_DEST_SEL_OFFSET; + break; + case CSI_PRP_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPENC_DEST_SEL_OFFSET; + break; + case CSI_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPVF_DEST_SEL_OFFSET; + break; + case MEM_PP_MEM: + fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PP_DEST_SEL_OFFSET; + break; + case MEM_ROT_PP_MEM: + fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PP_ROT_DEST_SEL_OFFSET; + break; + case MEM_PRP_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPENC_DEST_SEL_OFFSET; + break; + case MEM_ROT_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPENC_ROT_DEST_SEL_OFFSET; + break; + case MEM_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPVF_DEST_SEL_OFFSET; + break; + case MEM_VDI_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPVF_DEST_SEL_OFFSET; + break; + case MEM_ROT_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK; + fs_proc_flow2 |= + proc_dest_sel[IPU_CHAN_ID(dest_ch)] << + FS_PRPVF_ROT_DEST_SEL_OFFSET; + break; + default: + retval = -EINVAL; + goto err; + } + + switch (dest_ch) { + case MEM_PP_MEM: + fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PP_SRC_SEL_OFFSET; + break; + case MEM_ROT_PP_MEM: + fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << + FS_PP_ROT_SRC_SEL_OFFSET; + break; + case MEM_PRP_ENC_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET; + break; + case MEM_ROT_ENC_MEM: + fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << + FS_PRPENC_ROT_SRC_SEL_OFFSET; + break; + case MEM_PRP_VF_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET; + break; + case MEM_VDI_PRP_VF_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET; + break; + case MEM_ROT_VF_MEM: + fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= + proc_src_sel[IPU_CHAN_ID(src_ch)] << + FS_PRPVF_ROT_SRC_SEL_OFFSET; + break; + case MEM_DC_SYNC: + fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET; + break; + case MEM_BG_SYNC: + fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << + FS_DP_SYNC0_SRC_SEL_OFFSET; + break; + case MEM_FG_SYNC: + fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << + FS_DP_SYNC1_SRC_SEL_OFFSET; + break; + case MEM_DC_ASYNC: + fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET; + break; + case MEM_BG_ASYNC0: + fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << + FS_DP_ASYNC0_SRC_SEL_OFFSET; + break; + case MEM_FG_ASYNC0: + fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK; + fs_disp_flow1 |= + disp_src_sel[IPU_CHAN_ID(src_ch)] << + FS_DP_ASYNC1_SRC_SEL_OFFSET; + break; + default: + retval = -EINVAL; + goto err; + } + + __raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1); + __raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2); + __raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3); + __raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1); + +err: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return retval; +} +EXPORT_SYMBOL(ipu_link_channels); + +/*! + * This function unlinks 2 channels and disables automatic frame + * synchronization. + * + * @param src_ch Input parameter for the logical channel ID of + * the source channel. + * + * @param dest_ch Input parameter for the logical channel ID of + * the destination channel. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch) +{ + int retval = 0; + unsigned long lock_flags; + uint32_t fs_proc_flow1; + uint32_t fs_proc_flow2; + uint32_t fs_proc_flow3; + uint32_t fs_disp_flow1; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1); + fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2); + fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3); + fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1); + + switch (src_ch) { + case CSI_MEM0: + fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK; + break; + case CSI_MEM1: + fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK; + break; + case CSI_MEM2: + fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK; + break; + case CSI_MEM3: + fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK; + break; + case CSI_PRP_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + break; + case CSI_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + break; + case MEM_PP_MEM: + fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK; + break; + case MEM_ROT_PP_MEM: + fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK; + break; + case MEM_PRP_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + break; + case MEM_ROT_ENC_MEM: + fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK; + break; + case MEM_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + break; + case MEM_VDI_PRP_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + break; + case MEM_ROT_VF_MEM: + fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK; + break; + default: + retval = -EINVAL; + goto err; + } + + switch (dest_ch) { + case MEM_PP_MEM: + fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK; + break; + case MEM_ROT_PP_MEM: + fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK; + break; + case MEM_PRP_ENC_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + break; + case MEM_ROT_ENC_MEM: + fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK; + break; + case MEM_PRP_VF_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + break; + case MEM_VDI_PRP_VF_MEM: + fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK; + break; + case MEM_ROT_VF_MEM: + fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK; + break; + case MEM_DC_SYNC: + fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK; + break; + case MEM_BG_SYNC: + fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK; + break; + case MEM_FG_SYNC: + fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK; + break; + case MEM_DC_ASYNC: + fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK; + break; + case MEM_BG_ASYNC0: + fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK; + break; + case MEM_FG_ASYNC0: + fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK; + break; + default: + retval = -EINVAL; + goto err; + } + + __raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1); + __raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2); + __raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3); + __raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1); + +err: + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return retval; +} +EXPORT_SYMBOL(ipu_unlink_channels); + +/*! + * This function check whether a logical channel was enabled. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 1 while request channel is enabled or + * 0 for not enabled. + */ +int32_t ipu_is_channel_busy(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma; + uint32_t out_dma; + + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + if (reg & idma_mask(in_dma)) + return 1; + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + if (reg & idma_mask(out_dma)) + return 1; + return 0; +} +EXPORT_SYMBOL(ipu_is_channel_busy); + +/*! + * This function enables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_enable_channel(ipu_channel_t channel) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t ipu_conf; + uint32_t in_dma; + uint32_t out_dma; + uint32_t sec_dma; + uint32_t thrd_dma; + + if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) { + dev_err(g_ipu_dev, "Warning: channel already enabled %d\n", + IPU_CHAN_ID(channel)); + } + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + ipu_conf = __raw_readl(IPU_CONF); + if (ipu_di_use_count[0] > 0) { + ipu_conf |= IPU_CONF_DI0_EN; + } + if (ipu_di_use_count[1] > 0) { + ipu_conf |= IPU_CONF_DI1_EN; + } + if (ipu_dp_use_count > 0) + ipu_conf |= IPU_CONF_DP_EN; + if (ipu_dc_use_count > 0) + ipu_conf |= IPU_CONF_DC_EN; + if (ipu_dmfc_use_count > 0) + ipu_conf |= IPU_CONF_DMFC_EN; + if (ipu_ic_use_count > 0) + ipu_conf |= IPU_CONF_IC_EN; + if (ipu_vdi_use_count > 0) { + ipu_conf |= IPU_CONF_ISP_EN; + ipu_conf |= IPU_CONF_VDI_EN; + ipu_conf |= IPU_CONF_IC_INPUT; + } + if (ipu_rot_use_count > 0) + ipu_conf |= IPU_CONF_ROT_EN; + if (ipu_smfc_use_count > 0) + ipu_conf |= IPU_CONF_SMFC_EN; + __raw_writel(ipu_conf, IPU_CONF); + + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); + } + if (idma_is_valid(out_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); + } + + if ((g_sec_chan_en[IPU_CHAN_ID(channel)]) && + ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) || + (channel == MEM_VDI_PRP_VF_MEM))) { + sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER); + reg = __raw_readl(IDMAC_CHA_EN(sec_dma)); + __raw_writel(reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma)); + } + if ((g_thrd_chan_en[IPU_CHAN_ID(channel)]) && + ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) { + thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER); + reg = __raw_readl(IDMAC_CHA_EN(thrd_dma)); + __raw_writel(reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma)); + + sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER); + reg = __raw_readl(IDMAC_SEP_ALPHA); + __raw_writel(reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA); + } else if ((g_thrd_chan_en[IPU_CHAN_ID(channel)]) && + ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) { + thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER); + reg = __raw_readl(IDMAC_CHA_EN(thrd_dma)); + __raw_writel(reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma)); + reg = __raw_readl(IDMAC_SEP_ALPHA); + __raw_writel(reg | idma_mask(in_dma), IDMAC_SEP_ALPHA); + } + + if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) || + (channel == MEM_FG_SYNC)) { + reg = __raw_readl(IDMAC_WM_EN(in_dma)); + __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma)); + + _ipu_dp_dc_enable(channel); + } + + if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) || + _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma)) + _ipu_ic_enable_task(channel); + + g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_enable_channel); + +/*! + * This function check buffer ready for a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to clear. + * + * @param bufNum Input parameter for which buffer number clear + * ready state. + * + */ +int32_t ipu_check_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + uint32_t dma_chan = channel_2_dma(channel, type); + uint32_t reg; + + if (dma_chan == IDMA_CHAN_INVALID) + return -EINVAL; + + if (bufNum == 0) + reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan)); + else + reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan)); + + if (reg & idma_mask(dma_chan)) + return 1; + else + return 0; +} +EXPORT_SYMBOL(ipu_check_buffer_ready); + +/*! + * This function clear buffer ready for a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to clear. + * + * @param bufNum Input parameter for which buffer number clear + * ready state. + * + */ +void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + unsigned long lock_flags; + uint32_t dma_ch = channel_2_dma(channel, type); + + if (!idma_is_valid(dma_ch)) + return; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */ + if (bufNum == 0) { + if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) { + __raw_writel(idma_mask(dma_ch), + IPU_CHA_BUF0_RDY(dma_ch)); + } + } else { + if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) { + __raw_writel(idma_mask(dma_ch), + IPU_CHA_BUF1_RDY(dma_ch)); + } + } + __raw_writel(0x0, IPU_GPR); /* write one to set */ + spin_unlock_irqrestore(&ipu_lock, lock_flags); +} +EXPORT_SYMBOL(ipu_clear_buffer_ready); + +static irqreturn_t disable_chan_irq_handler(int irq, void *dev_id) +{ + struct completion *comp = dev_id; + + complete(comp); + return IRQ_HANDLED; +} + +/*! + * This function disables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param wait_for_stop Flag to set whether to wait for channel end + * of frame or return immediately. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop) +{ + uint32_t reg; + unsigned long lock_flags; + uint32_t in_dma; + uint32_t out_dma; + uint32_t sec_dma = NO_DMA; + uint32_t thrd_dma = NO_DMA; + + if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + dev_err(g_ipu_dev, "Channel already disabled %d\n", + IPU_CHAN_ID(channel)); + return 0; + } + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if ((idma_is_valid(in_dma) && + !idma_is_set(IDMAC_CHA_EN, in_dma)) + && (idma_is_valid(out_dma) && + !idma_is_set(IDMAC_CHA_EN, out_dma))) + return -EINVAL; + + if (g_sec_chan_en[IPU_CHAN_ID(channel)]) + sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER); + if (g_thrd_chan_en[IPU_CHAN_ID(channel)]) { + sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER); + thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER); + } + + if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) || + (channel == MEM_DC_SYNC)) { + if (channel == MEM_FG_SYNC) + ipu_disp_set_window_pos(channel, 0, 0); + + _ipu_dp_dc_disable(channel, false); + + /* + * wait for BG channel EOF then disable FG-IDMAC, + * it avoid FG NFB4EOF error. + */ + if (channel == MEM_FG_SYNC) { + int timeout = 50; + + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF), + IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)); + while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) & + IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) { + msleep(10); + timeout -= 10; + if (timeout <= 0) { + dev_err(g_ipu_dev, "warning: wait for bg sync eof timeout\n"); + break; + } + } + } + } else if (wait_for_stop) { + while (idma_is_set(IDMAC_CHA_BUSY, in_dma) || + idma_is_set(IDMAC_CHA_BUSY, out_dma) || + (g_sec_chan_en[IPU_CHAN_ID(channel)] && + idma_is_set(IDMAC_CHA_BUSY, sec_dma)) || + (g_thrd_chan_en[IPU_CHAN_ID(channel)] && + idma_is_set(IDMAC_CHA_BUSY, thrd_dma))) { + uint32_t ret, irq = 0xffffffff; + DECLARE_COMPLETION_ONSTACK(disable_comp); + + if (idma_is_set(IDMAC_CHA_BUSY, out_dma)) + irq = out_dma; + if (g_sec_chan_en[IPU_CHAN_ID(channel)] && + idma_is_set(IDMAC_CHA_BUSY, sec_dma)) + irq = sec_dma; + if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && + idma_is_set(IDMAC_CHA_BUSY, thrd_dma)) + irq = thrd_dma; + if (idma_is_set(IDMAC_CHA_BUSY, in_dma)) + irq = in_dma; + + if (irq == 0xffffffff) { + dev_err(g_ipu_dev, "warning: no channel busy, break\n"); + break; + } + ret = ipu_request_irq(irq, disable_chan_irq_handler, 0, NULL, &disable_comp); + if (ret < 0) { + dev_err(g_ipu_dev, "irq %d in use\n", irq); + break; + } else { + ret = wait_for_completion_timeout(&disable_comp, msecs_to_jiffies(200)); + ipu_free_irq(irq, &disable_comp); + if (ret == 0) { + ipu_dump_registers(); + dev_err(g_ipu_dev, "warning: disable ipu dma channel %d during its busy state\n", irq); + break; + } + } + } + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) || + (channel == MEM_DC_SYNC)) { + reg = __raw_readl(IDMAC_WM_EN(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma)); + } + + /* Disable IC task */ + if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) || + _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma)) + _ipu_ic_disable_task(channel); + + /* Disable DMA channel(s) */ + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); + __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma)); + } + if (idma_is_valid(out_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); + __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma)); + } + if (g_sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(sec_dma)); + __raw_writel(reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma)); + __raw_writel(idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma)); + } + if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(thrd_dma)); + __raw_writel(reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma)); + if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) { + reg = __raw_readl(IDMAC_SEP_ALPHA); + __raw_writel(reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA); + } else { + reg = __raw_readl(IDMAC_SEP_ALPHA); + __raw_writel(reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA); + } + __raw_writel(idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma)); + } + + g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel)); + + /* Set channel buffers NOT to be ready */ + if (idma_is_valid(in_dma)) { + ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0); + ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1); + } + if (idma_is_valid(out_dma)) { + ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0); + ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1); + } + if (g_sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) { + ipu_clear_buffer_ready(channel, IPU_GRAPH_IN_BUFFER, 0); + ipu_clear_buffer_ready(channel, IPU_GRAPH_IN_BUFFER, 1); + } + if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) { + ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 0); + ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 1); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_disable_channel); + +/*! + * This function enables CSI. + * + * @param csi csi num 0 or 1 + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_enable_csi(uint32_t csi) +{ + uint32_t reg; + unsigned long lock_flags; + + if (csi > 1) { + dev_err(g_ipu_dev, "Wrong csi num_%d\n", csi); + return -EINVAL; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + ipu_csi_use_count[csi]++; + + if (ipu_csi_use_count[csi] == 1) { + reg = __raw_readl(IPU_CONF); + if (csi == 0) + __raw_writel(reg | IPU_CONF_CSI0_EN, IPU_CONF); + else + __raw_writel(reg | IPU_CONF_CSI1_EN, IPU_CONF); + } + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} +EXPORT_SYMBOL(ipu_enable_csi); + +/*! + * This function disables CSI. + * + * @param csi csi num 0 or 1 + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_disable_csi(uint32_t csi) +{ + uint32_t reg; + unsigned long lock_flags; + + if (csi > 1) { + dev_err(g_ipu_dev, "Wrong csi num_%d\n", csi); + return -EINVAL; + } + + spin_lock_irqsave(&ipu_lock, lock_flags); + ipu_csi_use_count[csi]--; + + if (ipu_csi_use_count[csi] == 0) { + reg = __raw_readl(IPU_CONF); + if (csi == 0) + __raw_writel(reg & ~IPU_CONF_CSI0_EN, IPU_CONF); + else + __raw_writel(reg & ~IPU_CONF_CSI1_EN, IPU_CONF); + } + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} +EXPORT_SYMBOL(ipu_disable_csi); + +static irqreturn_t ipu_irq_handler(int irq, void *desc) +{ + int i; + uint32_t line; + irqreturn_t result = IRQ_NONE; + uint32_t int_stat; + const int err_reg[] = { 5, 6, 9, 10, 0 }; + const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 }; + + for (i = 0;; i++) { + if (err_reg[i] == 0) + break; + int_stat = __raw_readl(IPU_INT_STAT(err_reg[i])); + int_stat &= __raw_readl(IPU_INT_CTRL(err_reg[i])); + if (int_stat) { + __raw_writel(int_stat, IPU_INT_STAT(err_reg[i])); + dev_err(g_ipu_dev, + "IPU Error - IPU_INT_STAT_%d = 0x%08X\n", + err_reg[i], int_stat); + /* Disable interrupts so we only get error once */ + int_stat = + __raw_readl(IPU_INT_CTRL(err_reg[i])) & ~int_stat; + __raw_writel(int_stat, IPU_INT_CTRL(err_reg[i])); + } + } + + for (i = 0;; i++) { + if (int_reg[i] == 0) + break; + int_stat = __raw_readl(IPU_INT_STAT(int_reg[i])); + int_stat &= __raw_readl(IPU_INT_CTRL(int_reg[i])); + __raw_writel(int_stat, IPU_INT_STAT(int_reg[i])); + while ((line = ffs(int_stat)) != 0) { + line--; + int_stat &= ~(1UL << line); + line += (int_reg[i] - 1) * 32; + result |= + ipu_irq_list[line].handler(line, + ipu_irq_list[line]. + dev_id); + } + } + + return result; +} + +/*! + * This function enables the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to enable interrupt for. + * + */ +void ipu_enable_irq(uint32_t irq) +{ + uint32_t reg; + unsigned long lock_flags; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPUIRQ_2_CTRLREG(irq)); + reg |= IPUIRQ_2_MASK(irq); + __raw_writel(reg, IPUIRQ_2_CTRLREG(irq)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); +} +EXPORT_SYMBOL(ipu_enable_irq); + +/*! + * This function disables the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to disable interrupt for. + * + */ +void ipu_disable_irq(uint32_t irq) +{ + uint32_t reg; + unsigned long lock_flags; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IPUIRQ_2_CTRLREG(irq)); + reg &= ~IPUIRQ_2_MASK(irq); + __raw_writel(reg, IPUIRQ_2_CTRLREG(irq)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); +} +EXPORT_SYMBOL(ipu_disable_irq); + +/*! + * This function clears the interrupt for the specified interrupt line. + * The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to clear interrupt for. + * + */ +void ipu_clear_irq(uint32_t irq) +{ + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); + + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); +} +EXPORT_SYMBOL(ipu_clear_irq); + +/*! + * This function returns the current interrupt status for the specified + * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @return Returns true if the interrupt is pending/asserted or false if + * the interrupt is not pending. + */ +bool ipu_get_irq_status(uint32_t irq) +{ + uint32_t reg; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + reg = __raw_readl(IPUIRQ_2_STATREG(irq)); + + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + if (reg & IPUIRQ_2_MASK(irq)) + return true; + else + return false; +} +EXPORT_SYMBOL(ipu_get_irq_status); + +/*! + * This function registers an interrupt handler function for the specified + * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @param handler Input parameter for address of the handler + * function. + * + * @param irq_flags Flags for interrupt mode. Currently not used. + * + * @param devname Input parameter for string name of driver + * registering the handler. + * + * @param dev_id Input parameter for pointer of data to be + * passed to the handler. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int ipu_request_irq(uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id) +{ + unsigned long lock_flags; + + BUG_ON(irq >= IPU_IRQ_COUNT); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (ipu_irq_list[irq].handler != NULL) { + dev_err(g_ipu_dev, + "handler already installed on irq %d\n", irq); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + + ipu_irq_list[irq].handler = handler; + ipu_irq_list[irq].flags = irq_flags; + ipu_irq_list[irq].dev_id = dev_id; + ipu_irq_list[irq].name = devname; + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + ipu_enable_irq(irq); /* enable the interrupt */ + + return 0; +} +EXPORT_SYMBOL(ipu_request_irq); + +/*! + * This function unregisters an interrupt handler for the specified interrupt + * line. The interrupt lines are defined in \b ipu_irq_line enum. + * + * @param irq Interrupt line to get status for. + * + * @param dev_id Input parameter for pointer of data to be passed + * to the handler. This must match value passed to + * ipu_request_irq(). + * + */ +void ipu_free_irq(uint32_t irq, void *dev_id) +{ + ipu_disable_irq(irq); /* disable the interrupt */ + + if (ipu_irq_list[irq].dev_id == dev_id) + ipu_irq_list[irq].handler = NULL; +} +EXPORT_SYMBOL(ipu_free_irq); + +uint32_t ipu_get_cur_buffer_idx(ipu_channel_t channel, ipu_buffer_t type) +{ + uint32_t reg, dma_chan; + + dma_chan = channel_2_dma(channel, type); + if (!idma_is_valid(dma_chan)) + return -EINVAL; + + reg = __raw_readl(IPU_CHA_CUR_BUF(dma_chan/32)); + if (reg & idma_mask(dma_chan)) + return 1; + else + return 0; +} +EXPORT_SYMBOL(ipu_get_cur_buffer_idx); + +uint32_t _ipu_channel_status(ipu_channel_t channel) +{ + uint32_t stat = 0; + uint32_t task_stat_reg = __raw_readl(IPU_PROC_TASK_STAT); + + switch (channel) { + case MEM_PRP_VF_MEM: + stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET; + break; + case MEM_VDI_PRP_VF_MEM: + stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET; + break; + case MEM_ROT_VF_MEM: + stat = + (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET; + break; + case MEM_PRP_ENC_MEM: + stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET; + break; + case MEM_ROT_ENC_MEM: + stat = + (task_stat_reg & TSTAT_ENC_ROT_MASK) >> + TSTAT_ENC_ROT_OFFSET; + break; + case MEM_PP_MEM: + stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET; + break; + case MEM_ROT_PP_MEM: + stat = + (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET; + break; + + default: + stat = TASK_STAT_IDLE; + break; + } + return stat; +} + +int32_t ipu_swap_channel(ipu_channel_t from_ch, ipu_channel_t to_ch) +{ + uint32_t reg; + unsigned long lock_flags; + + int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER); + int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER); + + /* enable target channel */ + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IDMAC_CHA_EN(to_dma)); + __raw_writel(reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma)); + + g_channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + /* switch dp dc */ + _ipu_dp_dc_disable(from_ch, true); + + /* disable source channel */ + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(IDMAC_CHA_EN(from_dma)); + __raw_writel(reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma)); + __raw_writel(idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma)); + + g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch)); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_swap_channel); + +uint32_t bytes_per_pixel(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: /*generic data */ + case IPU_PIX_FMT_RGB332: + case IPU_PIX_FMT_YUV420P: + case IPU_PIX_FMT_YUV422P: + return 1; + break; + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_YUYV: + case IPU_PIX_FMT_UYVY: + return 2; + break; + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + return 3; + break; + case IPU_PIX_FMT_GENERIC_32: /*generic data */ + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_ABGR32: + return 4; + break; + default: + return 1; + break; + } + return 0; +} +EXPORT_SYMBOL(bytes_per_pixel); + +ipu_color_space_t format_to_colorspace(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_RGB666: + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_GBR24: + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_ABGR32: + case IPU_PIX_FMT_LVDS666: + case IPU_PIX_FMT_LVDS888: + return RGB; + break; + + default: + return YCbCr; + break; + } + return RGB; +} + +bool ipu_pixel_format_has_alpha(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_ABGR32: + return true; + break; + default: + return false; + break; + } + return false; +} + +void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]) +{ + _ipu_dp_set_csc_coefficients(channel, param); +} +EXPORT_SYMBOL(ipu_set_csc_coefficients); + +static int ipu_suspend(struct platform_device *pdev, pm_message_t state) +{ + if (g_ipu_clk_enabled) { + /* save and disable enabled channels*/ + idma_enable_reg[0] = __raw_readl(IDMAC_CHA_EN(0)); + idma_enable_reg[1] = __raw_readl(IDMAC_CHA_EN(32)); + while ((__raw_readl(IDMAC_CHA_BUSY(0)) & idma_enable_reg[0]) + || (__raw_readl(IDMAC_CHA_BUSY(32)) & + idma_enable_reg[1])) { + /* disable channel not busy already */ + uint32_t chan_should_disable, timeout = 1000, time = 0; + + chan_should_disable = + __raw_readl(IDMAC_CHA_BUSY(0)) + ^ idma_enable_reg[0]; + __raw_writel((~chan_should_disable) & + idma_enable_reg[0], IDMAC_CHA_EN(0)); + chan_should_disable = + __raw_readl(IDMAC_CHA_BUSY(1)) + ^ idma_enable_reg[1]; + __raw_writel((~chan_should_disable) & + idma_enable_reg[1], IDMAC_CHA_EN(32)); + msleep(2); + time += 2; + if (time >= timeout) + return -1; + } + __raw_writel(0, IDMAC_CHA_EN(0)); + __raw_writel(0, IDMAC_CHA_EN(32)); + + /* save double buffer select regs */ + ipu_cha_db_mode_reg[0] = __raw_readl(IPU_CHA_DB_MODE_SEL(0)); + ipu_cha_db_mode_reg[1] = __raw_readl(IPU_CHA_DB_MODE_SEL(32)); + ipu_cha_db_mode_reg[2] = + __raw_readl(IPU_ALT_CHA_DB_MODE_SEL(0)); + ipu_cha_db_mode_reg[3] = + __raw_readl(IPU_ALT_CHA_DB_MODE_SEL(32)); + + /* save current buffer regs */ + ipu_cha_cur_buf_reg[0] = __raw_readl(IPU_CHA_CUR_BUF(0)); + ipu_cha_cur_buf_reg[1] = __raw_readl(IPU_CHA_CUR_BUF(32)); + ipu_cha_cur_buf_reg[2] = __raw_readl(IPU_ALT_CUR_BUF0); + ipu_cha_cur_buf_reg[3] = __raw_readl(IPU_ALT_CUR_BUF1); + + /* save sub-modules status and disable all */ + ic_conf_reg = __raw_readl(IC_CONF); + __raw_writel(0, IC_CONF); + ipu_conf_reg = __raw_readl(IPU_CONF); + __raw_writel(0, IPU_CONF); + + /* save buf ready regs */ + buf_ready_reg[0] = __raw_readl(IPU_CHA_BUF0_RDY(0)); + buf_ready_reg[1] = __raw_readl(IPU_CHA_BUF0_RDY(32)); + buf_ready_reg[2] = __raw_readl(IPU_CHA_BUF1_RDY(0)); + buf_ready_reg[3] = __raw_readl(IPU_CHA_BUF1_RDY(32)); + buf_ready_reg[4] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(0)); + buf_ready_reg[5] = __raw_readl(IPU_ALT_CHA_BUF0_RDY(32)); + buf_ready_reg[6] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(0)); + buf_ready_reg[7] = __raw_readl(IPU_ALT_CHA_BUF1_RDY(32)); + } + + mxc_pg_enable(pdev); + + return 0; +} + +static int ipu_resume(struct platform_device *pdev) +{ + mxc_pg_disable(pdev); + + if (g_ipu_clk_enabled) { + + /* restore buf ready regs */ + __raw_writel(buf_ready_reg[0], IPU_CHA_BUF0_RDY(0)); + __raw_writel(buf_ready_reg[1], IPU_CHA_BUF0_RDY(32)); + __raw_writel(buf_ready_reg[2], IPU_CHA_BUF1_RDY(0)); + __raw_writel(buf_ready_reg[3], IPU_CHA_BUF1_RDY(32)); + __raw_writel(buf_ready_reg[4], IPU_ALT_CHA_BUF0_RDY(0)); + __raw_writel(buf_ready_reg[5], IPU_ALT_CHA_BUF0_RDY(32)); + __raw_writel(buf_ready_reg[6], IPU_ALT_CHA_BUF1_RDY(0)); + __raw_writel(buf_ready_reg[7], IPU_ALT_CHA_BUF1_RDY(32)); + + /* re-enable sub-modules*/ + __raw_writel(ipu_conf_reg, IPU_CONF); + __raw_writel(ic_conf_reg, IC_CONF); + + /* restore double buffer select regs */ + __raw_writel(ipu_cha_db_mode_reg[0], IPU_CHA_DB_MODE_SEL(0)); + __raw_writel(ipu_cha_db_mode_reg[1], IPU_CHA_DB_MODE_SEL(32)); + __raw_writel(ipu_cha_db_mode_reg[2], + IPU_ALT_CHA_DB_MODE_SEL(0)); + __raw_writel(ipu_cha_db_mode_reg[3], + IPU_ALT_CHA_DB_MODE_SEL(32)); + + /* restore current buffer select regs */ + __raw_writel(~(ipu_cha_cur_buf_reg[0]), IPU_CHA_CUR_BUF(0)); + __raw_writel(~(ipu_cha_cur_buf_reg[1]), IPU_CHA_CUR_BUF(32)); + __raw_writel(~(ipu_cha_cur_buf_reg[2]), IPU_ALT_CUR_BUF0); + __raw_writel(~(ipu_cha_cur_buf_reg[3]), IPU_ALT_CUR_BUF1); + + /* restart idma channel*/ + __raw_writel(idma_enable_reg[0], IDMAC_CHA_EN(0)); + __raw_writel(idma_enable_reg[1], IDMAC_CHA_EN(32)); + } else { + clk_enable(g_ipu_clk); + _ipu_dmfc_init(dmfc_type_setup, 1); + _ipu_init_dc_mappings(); + + /* Set sync refresh channels as high priority */ + __raw_writel(0x18800000L, IDMAC_CHA_PRI(0)); + clk_disable(g_ipu_clk); + } + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcipu_driver = { + .driver = { + .name = "mxc_ipu", + }, + .probe = ipu_probe, + .remove = ipu_remove, + .suspend = ipu_suspend, + .resume = ipu_resume, +}; + +int32_t __init ipu_gen_init(void) +{ + int32_t ret; + + ret = platform_driver_register(&mxcipu_driver); + return 0; +} + +subsys_initcall(ipu_gen_init); + +static void __exit ipu_gen_uninit(void) +{ + platform_driver_unregister(&mxcipu_driver); +} + +module_exit(ipu_gen_uninit); diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c new file mode 100644 index 000000000000..c7c032d85d52 --- /dev/null +++ b/drivers/mxc/ipu3/ipu_device.c @@ -0,0 +1,510 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_device.c + * + * @brief This file contains the IPUv3 driver device interface and fops functions. + * + * @ingroup IPU + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +/* Strucutures and variables for exporting MXC IPU as device*/ + +static int mxc_ipu_major; +static struct class *mxc_ipu_class; + +DEFINE_SPINLOCK(event_lock); + +struct ipu_dev_irq_info { + wait_queue_head_t waitq; + int irq_pending; +} irq_info[480]; + +int register_ipu_device(void); + +/* Static functions */ + +int get_events(ipu_event_info *p) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&event_lock, flags); + if (irq_info[p->irq].irq_pending > 0) + irq_info[p->irq].irq_pending--; + else + ret = -1; + spin_unlock_irqrestore(&event_lock, flags); + + return ret; +} + +static irqreturn_t mxc_ipu_generic_handler(int irq, void *dev_id) +{ + irq_info[irq].irq_pending++; + + /* Wakeup any blocking user context */ + wake_up_interruptible(&(irq_info[irq].waitq)); + return IRQ_HANDLED; +} + +static int mxc_ipu_open(struct inode *inode, struct file *file) +{ + int ret = 0; + return ret; +} +static int mxc_ipu_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + + switch (cmd) { + case IPU_INIT_CHANNEL: + { + ipu_channel_parm parm; + + if (copy_from_user + (&parm, (ipu_channel_parm *) arg, + sizeof(ipu_channel_parm))) + return -EFAULT; + + if (!parm.flag) { + ret = + ipu_init_channel(parm.channel, + &parm.params); + } else { + ret = ipu_init_channel(parm.channel, NULL); + } + } + break; + case IPU_UNINIT_CHANNEL: + { + ipu_channel_t ch; + int __user *argp = (void __user *)arg; + if (get_user(ch, argp)) + return -EFAULT; + ipu_uninit_channel(ch); + } + break; + case IPU_INIT_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) + return -EFAULT; + + ret = + ipu_init_channel_buffer( + parm.channel, parm.type, + parm.pixel_fmt, + parm.width, parm.height, + parm.stride, + parm.rot_mode, + parm.phyaddr_0, + parm.phyaddr_1, + parm.u_offset, + parm.v_offset); + + } + break; + case IPU_UPDATE_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) + return -EFAULT; + + if ((parm.phyaddr_0 != (dma_addr_t) NULL) + && (parm.phyaddr_1 == (dma_addr_t) NULL)) { + ret = + ipu_update_channel_buffer( + parm.channel, + parm.type, + parm.bufNum, + parm.phyaddr_0); + } else if ((parm.phyaddr_0 == (dma_addr_t) NULL) + && (parm.phyaddr_1 != (dma_addr_t) NULL)) { + ret = + ipu_update_channel_buffer( + parm.channel, + parm.type, + parm.bufNum, + parm.phyaddr_1); + } else { + ret = -1; + } + + } + break; + case IPU_SELECT_CHANNEL_BUFFER: + { + ipu_channel_buf_parm parm; + if (copy_from_user + (&parm, (ipu_channel_buf_parm *) arg, + sizeof(ipu_channel_buf_parm))) + return -EFAULT; + + ret = + ipu_select_buffer(parm.channel, + parm.type, parm.bufNum); + + } + break; + case IPU_SELECT_MULTI_VDI_BUFFER: + { + uint32_t parm; + if (copy_from_user + (&parm, (uint32_t *) arg, + sizeof(uint32_t))) + return -EFAULT; + + ret = ipu_select_multi_vdi_buffer(parm); + } + break; + case IPU_LINK_CHANNELS: + { + ipu_channel_link link; + if (copy_from_user + (&link, (ipu_channel_link *) arg, + sizeof(ipu_channel_link))) + return -EFAULT; + + ret = ipu_link_channels(link.src_ch, + link.dest_ch); + + } + break; + case IPU_UNLINK_CHANNELS: + { + ipu_channel_link link; + if (copy_from_user + (&link, (ipu_channel_link *) arg, + sizeof(ipu_channel_link))) + return -EFAULT; + + ret = ipu_unlink_channels(link.src_ch, + link.dest_ch); + + } + break; + case IPU_ENABLE_CHANNEL: + { + ipu_channel_t ch; + int __user *argp = (void __user *)arg; + if (get_user(ch, argp)) + return -EFAULT; + ipu_enable_channel(ch); + } + break; + case IPU_DISABLE_CHANNEL: + { + ipu_channel_info info; + if (copy_from_user + (&info, (ipu_channel_info *) arg, + sizeof(ipu_channel_info))) + return -EFAULT; + + ret = ipu_disable_channel(info.channel, + info.stop); + } + break; + case IPU_ENABLE_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_enable_irq(irq); + } + break; + case IPU_DISABLE_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_disable_irq(irq); + } + break; + case IPU_CLEAR_IRQ: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ipu_clear_irq(irq); + } + break; + case IPU_FREE_IRQ: + { + ipu_irq_info info; + + if (copy_from_user + (&info, (ipu_irq_info *) arg, + sizeof(ipu_irq_info))) + return -EFAULT; + + ipu_free_irq(info.irq, info.dev_id); + irq_info[info.irq].irq_pending = 0; + } + break; + case IPU_REQUEST_IRQ_STATUS: + { + uint32_t irq; + int __user *argp = (void __user *)arg; + if (get_user(irq, argp)) + return -EFAULT; + ret = ipu_get_irq_status(irq); + } + break; + case IPU_REGISTER_GENERIC_ISR: + { + ipu_event_info info; + if (copy_from_user + (&info, (ipu_event_info *) arg, + sizeof(ipu_event_info))) + return -EFAULT; + + ret = + ipu_request_irq(info.irq, + mxc_ipu_generic_handler, + 0, "video_sink", info.dev); + if (ret == 0) + init_waitqueue_head(&(irq_info[info.irq].waitq)); + } + break; + case IPU_GET_EVENT: + /* User will have to allocate event_type + structure and pass the pointer in arg */ + { + ipu_event_info info; + int r = -1; + + if (copy_from_user + (&info, (ipu_event_info *) arg, + sizeof(ipu_event_info))) + return -EFAULT; + + r = get_events(&info); + if (r == -1) { + if ((file->f_flags & O_NONBLOCK) && + (irq_info[info.irq].irq_pending == 0)) + return -EAGAIN; + wait_event_interruptible_timeout(irq_info[info.irq].waitq, + (irq_info[info.irq].irq_pending != 0), 2 * HZ); + r = get_events(&info); + } + ret = -1; + if (r == 0) { + if (!copy_to_user((ipu_event_info *) arg, + &info, sizeof(ipu_event_info))) + ret = 0; + } + } + break; + case IPU_ALOC_MEM: + { + ipu_mem_info info; + if (copy_from_user + (&info, (ipu_mem_info *) arg, + sizeof(ipu_mem_info))) + return -EFAULT; + + info.vaddr = dma_alloc_coherent(0, + PAGE_ALIGN(info.size), + &info.paddr, + GFP_DMA | GFP_KERNEL); + if (info.vaddr == 0) { + printk(KERN_ERR "dma alloc failed!\n"); + return -ENOBUFS; + } + if (copy_to_user((ipu_mem_info *) arg, &info, + sizeof(ipu_mem_info)) > 0) + return -EFAULT; + } + break; + case IPU_FREE_MEM: + { + ipu_mem_info info; + if (copy_from_user + (&info, (ipu_mem_info *) arg, + sizeof(ipu_mem_info))) + return -EFAULT; + + if (info.vaddr) + dma_free_coherent(0, PAGE_ALIGN(info.size), + info.vaddr, info.paddr); + else + return -EFAULT; + } + break; + case IPU_IS_CHAN_BUSY: + { + ipu_channel_t chan; + if (copy_from_user + (&chan, (ipu_channel_t *)arg, + sizeof(ipu_channel_t))) + return -EFAULT; + + if (ipu_is_channel_busy(chan)) + ret = 1; + else + ret = 0; + } + break; + case IPU_CALC_STRIPES_SIZE: + { + ipu_stripe_parm stripe_parm; + + if (copy_from_user (&stripe_parm, (ipu_stripe_parm *)arg, + sizeof(ipu_stripe_parm))) + return -EFAULT; + ipu_calc_stripes_sizes(stripe_parm.input_width, + stripe_parm.output_width, + stripe_parm.maximal_stripe_width, + stripe_parm.cirr, + stripe_parm.equal_stripes, + stripe_parm.input_pixelformat, + stripe_parm.output_pixelformat, + &stripe_parm.left, + &stripe_parm.right); + if (copy_to_user((ipu_stripe_parm *) arg, &stripe_parm, + sizeof(ipu_stripe_parm)) > 0) + return -EFAULT; + } + break; + case IPU_UPDATE_BUF_OFFSET: + { + ipu_buf_offset_parm offset_parm; + + if (copy_from_user (&offset_parm, (ipu_buf_offset_parm *)arg, + sizeof(ipu_buf_offset_parm))) + return -EFAULT; + ret = ipu_update_channel_offset(offset_parm.channel, + offset_parm.type, + offset_parm.pixel_fmt, + offset_parm.width, + offset_parm.height, + offset_parm.stride, + offset_parm.u_offset, + offset_parm.v_offset, + offset_parm.vertical_offset, + offset_parm.horizontal_offset); + } + break; + case IPU_CSC_UPDATE: + { + int param[5][3]; + ipu_csc_update csc; + if (copy_from_user(&csc, (void *) arg, + sizeof(ipu_csc_update))) + return -EFAULT; + if (copy_from_user(¶m[0][0], (void *) csc.param, + sizeof(param))) + return -EFAULT; + ipu_set_csc_coefficients(csc.channel, param); + } + break; + default: + break; + } + return ret; +} + +static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma) +{ + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) { + printk(KERN_ERR + "mmap failed!\n"); + return -ENOBUFS; + } + return 0; +} + +static int mxc_ipu_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static struct file_operations mxc_ipu_fops = { + .owner = THIS_MODULE, + .open = mxc_ipu_open, + .mmap = mxc_ipu_mmap, + .release = mxc_ipu_release, + .ioctl = mxc_ipu_ioctl, +}; + +int register_ipu_device() +{ + int ret = 0; + struct device *temp; + mxc_ipu_major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops); + if (mxc_ipu_major < 0) { + printk(KERN_ERR + "Unable to register Mxc Ipu as a char device\n"); + return mxc_ipu_major; + } + + mxc_ipu_class = class_create(THIS_MODULE, "mxc_ipu"); + if (IS_ERR(mxc_ipu_class)) { + printk(KERN_ERR "Unable to create class for Mxc Ipu\n"); + ret = PTR_ERR(mxc_ipu_class); + goto err1; + } + + temp = device_create(mxc_ipu_class, NULL, MKDEV(mxc_ipu_major, 0), + NULL, "mxc_ipu"); + + if (IS_ERR(temp)) { + printk(KERN_ERR "Unable to create class device for Mxc Ipu\n"); + ret = PTR_ERR(temp); + goto err2; + } + spin_lock_init(&event_lock); + + return ret; + +err2: + class_destroy(mxc_ipu_class); +err1: + unregister_chrdev(mxc_ipu_major, "mxc_ipu"); + return ret; + +} diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c new file mode 100644 index 000000000000..e845bdaf3485 --- /dev/null +++ b/drivers/mxc/ipu3/ipu_disp.c @@ -0,0 +1,1884 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ipu_disp.c + * + * @brief IPU display submodule API functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +enum csc_type_t { + RGB2YUV = 0, + YUV2RGB, + RGB2RGB, + YUV2YUV, + CSC_NONE, + CSC_NUM +}; + +struct dp_csc_param_t { + int mode; + void *coeff; +}; + +#define SYNC_WAVE 0 +#define ASYNC_SER_WAVE 6 + +/* DC display ID assignments */ +#define DC_DISP_ID_SYNC(di) (di) +#define DC_DISP_ID_SERIAL 2 +#define DC_DISP_ID_ASYNC 3 + +int dmfc_type_setup; +static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; + +void _ipu_dmfc_init(int dmfc_type, int first) +{ + u32 dmfc_wr_chan, dmfc_dp_chan; + + if (first) { + if (dmfc_type_setup > dmfc_type) + dmfc_type = dmfc_type_setup; + else + dmfc_type_setup = dmfc_type; + + /* disable DMFC-IC channel*/ + __raw_writel(0x2, DMFC_IC_CTRL); + } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) { + printk(KERN_DEBUG "DMFC high resolution has set, will not change\n"); + return; + } else + dmfc_type_setup = dmfc_type; + + if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) { + /* 1 - segment 0~3; + * 5B - segement 4, 5; + * 5F - segement 6, 7; + * 1C, 2C and 6B, 6F unused; + */ + printk(KERN_INFO "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000088; + dmfc_dp_chan = 0x00009694; + dmfc_size_28 = 256*4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128*4; + dmfc_size_23 = 128*4; + } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) { + /* 1 - segment 0, 1; + * 5B - segement 2~5; + * 5F - segement 6,7; + * 1C, 2C and 6B, 6F unused; + */ + printk(KERN_INFO "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000090; + dmfc_dp_chan = 0x0000968a; + dmfc_size_28 = 128*4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128*4; + dmfc_size_23 = 256*4; + } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) { + /* 5B - segement 0~3; + * 5F - segement 4~7; + * 1, 1C, 2C and 6B, 6F unused; + */ + printk(KERN_INFO "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n"); + dmfc_wr_chan = 0x00000000; + dmfc_dp_chan = 0x00008c88; + dmfc_size_28 = 0; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 256*4; + dmfc_size_23 = 256*4; + } else { + /* 1 - segment 0, 1; + * 5B - segement 4, 5; + * 5F - segement 6, 7; + * 1C, 2C and 6B, 6F unused; + */ + printk(KERN_INFO "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000090; + dmfc_dp_chan = 0x00009694; + dmfc_size_28 = 128*4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128*4; + dmfc_size_23 = 128*4; + } + __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); + __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF); + __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); + /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */ + __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF); +} + +static int __init dmfc_setup(char *options) +{ + get_option(&options, &dmfc_type_setup); + if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP) + dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP; + return 1; +} +__setup("dmfc=", dmfc_setup); + +void _ipu_dmfc_set_wait4eot(int dma_chan, int width) +{ + u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); + + if (width >= HIGH_RESOLUTION_WIDTH) { + if (dma_chan == 23) + _ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0); + else if (dma_chan == 28) + _ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0); + } + + if (dma_chan == 23) { /*5B*/ + if (dmfc_size_23/width > 3) + dmfc_gen1 |= 1UL << 20; + else + dmfc_gen1 &= ~(1UL << 20); + } else if (dma_chan == 24) { /*6B*/ + if (dmfc_size_24/width > 1) + dmfc_gen1 |= 1UL << 22; + else + dmfc_gen1 &= ~(1UL << 22); + } else if (dma_chan == 27) { /*5F*/ + if (dmfc_size_27/width > 2) + dmfc_gen1 |= 1UL << 21; + else + dmfc_gen1 &= ~(1UL << 21); + } else if (dma_chan == 28) { /*1*/ + if (dmfc_size_28/width > 2) + dmfc_gen1 |= 1UL << 16; + else + dmfc_gen1 &= ~(1UL << 16); + } else if (dma_chan == 29) { /*6F*/ + if (dmfc_size_29/width > 1) + dmfc_gen1 |= 1UL << 23; + else + dmfc_gen1 &= ~(1UL << 23); + } + + __raw_writel(dmfc_gen1, DMFC_GENERAL1); +} + +static void _ipu_di_data_wave_config(int di, + int wave_gen, + int access_size, int component_size) +{ + u32 reg; + reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | + (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); + __raw_writel(reg, DI_DW_GEN(di, wave_gen)); +} + +static void _ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set, + int up, int down) +{ + u32 reg; + + reg = __raw_readl(DI_DW_GEN(di, wave_gen)); + reg &= ~(0x3 << (di_pin * 2)); + reg |= set << (di_pin * 2); + __raw_writel(reg, DI_DW_GEN(di, wave_gen)); + + __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set)); +} + +static void _ipu_di_sync_config(int di, int wave_gen, + int run_count, int run_src, + int offset_count, int offset_src, + int repeat_count, int cnt_clr_src, + int cnt_polarity_gen_en, + int cnt_polarity_clr_src, + int cnt_polarity_trigger_src, + int cnt_up, int cnt_down) +{ + u32 reg; + + if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) || + (cnt_up >= 0x400) || (cnt_down >= 0x400)) { + dev_err(g_ipu_dev, "DI%d counters out of range.\n", di); + return; + } + + reg = (run_count << 19) | (++run_src << 16) | + (offset_count << 3) | ++offset_src; + __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); + reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) | + (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9); + reg |= (cnt_down << 16) | cnt_up; + if (repeat_count == 0) { + /* Enable auto reload */ + reg |= 0x10000000; + } + __raw_writel(reg, DI_SW_GEN1(di, wave_gen)); + reg = __raw_readl(DI_STP_REP(di, wave_gen)); + reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1))); + reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1)); + __raw_writel(reg, DI_STP_REP(di, wave_gen)); +} + +static void _ipu_dc_map_link(int current_map, + int base_map_0, int buf_num_0, + int base_map_1, int buf_num_1, + int base_map_2, int buf_num_2) +{ + int ptr_0 = base_map_0 * 3 + buf_num_0; + int ptr_1 = base_map_1 * 3 + buf_num_1; + int ptr_2 = base_map_2 * 3 + buf_num_2; + int ptr; + u32 reg; + ptr = (ptr_2 << 10) + (ptr_1 << 5) + ptr_0; + + reg = __raw_readl(DC_MAP_CONF_PTR(current_map)); + reg &= ~(0x1F << ((16 * (current_map & 0x1)))); + reg |= ptr << ((16 * (current_map & 0x1))); + __raw_writel(reg, DC_MAP_CONF_PTR(current_map)); +} + +static void _ipu_dc_map_config(int map, int byte_num, int offset, int mask) +{ + int ptr = map * 3 + byte_num; + u32 reg; + + reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); + reg &= ~(0xFFFF << (16 * (ptr & 0x1))); + reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); + __raw_writel(reg, DC_MAP_CONF_VAL(ptr)); + + reg = __raw_readl(DC_MAP_CONF_PTR(map)); + reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num))); + reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); + __raw_writel(reg, DC_MAP_CONF_PTR(map)); +} + +static void _ipu_dc_map_clear(int map) +{ + u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); + __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))), + DC_MAP_CONF_PTR(map)); +} + +static void _ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map, + int wave, int glue, int sync, int stop) +{ + u32 reg; + + if (opcode == WRG) { + reg = sync; + reg |= (glue << 4); + reg |= (++wave << 11); + reg |= ((operand & 0x1FFFF) << 15); + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2); + + reg = (operand >> 17); + reg |= opcode << 7; + reg |= (stop << 9); + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1); + } else { + reg = sync; + reg |= (glue << 4); + reg |= (++wave << 11); + reg |= (++map << 15); + reg |= (operand << 20) & 0xFFF00000; + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2); + + reg = (operand >> 12); + reg |= opcode << 4; + reg |= (stop << 9); + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1); + } +} + +static void _ipu_dc_link_event(int chan, int event, int addr, int priority) +{ + u32 reg; + u32 address_shift; + if (event < DC_EVEN_UGDE0) { + reg = __raw_readl(DC_RL_CH(chan, event)); + reg &= ~(0xFFFF << (16 * (event & 0x1))); + reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); + __raw_writel(reg, DC_RL_CH(chan, event)); + } else { + reg = __raw_readl(DC_UGDE_0((event - DC_EVEN_UGDE0) / 2)); + if ((event - DC_EVEN_UGDE0) & 0x1) { + reg &= ~(0x2FF << 16); + reg |= (addr << 16); + reg |= priority ? (2 << 24) : 0x0; + } else { + reg &= ~0xFC00FFFF; + if (priority) + chan = (chan >> 1) + + ((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3)); + else + chan = 0x7; + address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8; + reg |= (addr << address_shift) | (priority << 3) | chan; + } + __raw_writel(reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2)); + } +} + +/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250; + U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.; + V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;*/ +static const int rgb2ycbcr_coeff[5][3] = { + {0x4D, 0x96, 0x1D}, + {-0x2B, -0x55, 0x80}, + {0x80, -0x6B, -0x15}, + {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */ + {0x2, 0x2, 0x2}, /* S0, S1, S2 */ +}; + +/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); + G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); + B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */ +static const int ycbcr2rgb_coeff[5][3] = { + {0x095, 0x000, 0x0CC}, + {0x095, 0x3CE, 0x398}, + {0x095, 0x0FF, 0x000}, + {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */ + {0x1, 0x1, 0x1}, /*S0,S1,S2 */ +}; + +#define mask_a(a) ((u32)(a) & 0x3FF) +#define mask_b(b) ((u32)(b) & 0x3FFF) + +/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */ +static int _rgb_to_yuv(int n, int red, int green, int blue) +{ + int c; + c = red * rgb2ycbcr_coeff[n][0]; + c += green * rgb2ycbcr_coeff[n][1]; + c += blue * rgb2ycbcr_coeff[n][2]; + c /= 16; + c += rgb2ycbcr_coeff[3][n] * 4; + c += 8; + c /= 16; + if (c < 0) + c = 0; + if (c > 255) + c = 255; + return c; +} + +/* + * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE + * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE + */ +static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = { +{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} }, +{{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} }, +{{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }, +{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, +{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} } +}; + +static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE; +static int color_key_4rgb = 1; + +void __ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param, + bool srm_mode_update) +{ + u32 reg; + const int (*coeff)[5][3]; + + if (dp_csc_param.mode >= 0) { + reg = __raw_readl(DP_COM_CONF(dp)); + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + reg |= dp_csc_param.mode; + __raw_writel(reg, DP_COM_CONF(dp)); + } + + coeff = dp_csc_param.coeff; + + if (coeff) { + __raw_writel(mask_a((*coeff)[0][0]) | + (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp)); + __raw_writel(mask_a((*coeff)[0][2]) | + (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp)); + __raw_writel(mask_a((*coeff)[1][1]) | + (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp)); + __raw_writel(mask_a((*coeff)[2][0]) | + (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp)); + __raw_writel(mask_a((*coeff)[2][2]) | + (mask_b((*coeff)[3][0]) << 16) | + ((*coeff)[4][0] << 30), DP_CSC_0(dp)); + __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) | + (mask_b((*coeff)[3][2]) << 16) | + ((*coeff)[4][2] << 30), DP_CSC_1(dp)); + } + + if (srm_mode_update) { + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + } +} + +int _ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, + uint32_t out_pixel_fmt) +{ + int in_fmt, out_fmt; + int dp; + int partial = false; + uint32_t reg; + + if (channel == MEM_FG_SYNC) { + dp = DP_SYNC; + partial = true; + } else if (channel == MEM_BG_SYNC) { + dp = DP_SYNC; + partial = false; + } else if (channel == MEM_BG_ASYNC0) { + dp = DP_ASYNC0; + partial = false; + } else { + return -EINVAL; + } + + in_fmt = format_to_colorspace(in_pixel_fmt); + out_fmt = format_to_colorspace(out_pixel_fmt); + + if (partial) { + if (in_fmt == RGB) { + if (out_fmt == RGB) + fg_csc_type = RGB2RGB; + else + fg_csc_type = RGB2YUV; + } else { + if (out_fmt == RGB) + fg_csc_type = YUV2RGB; + else + fg_csc_type = YUV2YUV; + } + } else { + if (in_fmt == RGB) { + if (out_fmt == RGB) + bg_csc_type = RGB2RGB; + else + bg_csc_type = RGB2YUV; + } else { + if (out_fmt == RGB) + bg_csc_type = YUV2RGB; + else + bg_csc_type = YUV2YUV; + } + } + + /* Transform color key from rgb to yuv if CSC is enabled */ + reg = __raw_readl(DP_COM_CONF(dp)); + if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) && + (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) { + int red, green, blue; + int y, u, v; + uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL; + + dev_dbg(g_ipu_dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key); + + red = (color_key >> 16) & 0xFF; + green = (color_key >> 8) & 0xFF; + blue = color_key & 0xFF; + + y = _rgb_to_yuv(0, red, green, blue); + u = _rgb_to_yuv(1, red, green, blue); + v = _rgb_to_yuv(2, red, green, blue); + color_key = (y << 16) | (u << 8) | v; + + reg = __raw_readl(DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L; + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(dp)); + color_key_4rgb = 0; + + dev_dbg(g_ipu_dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key); + } + + __ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], true); + + return 0; +} + +void _ipu_dp_uninit(ipu_channel_t channel) +{ + int dp; + int partial = false; + + if (channel == MEM_FG_SYNC) { + dp = DP_SYNC; + partial = true; + } else if (channel == MEM_BG_SYNC) { + dp = DP_SYNC; + partial = false; + } else if (channel == MEM_BG_ASYNC0) { + dp = DP_ASYNC0; + partial = false; + } else { + return; + } + + if (partial) + fg_csc_type = CSC_NONE; + else + bg_csc_type = CSC_NONE; + + __ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], false); +} + +void _ipu_dc_init(int dc_chan, int di, bool interlaced, uint32_t pixel_fmt) +{ + u32 reg = 0; + + if ((dc_chan == 1) || (dc_chan == 5)) { + if (interlaced) { + _ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3); + _ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1); + } else { + if (di) { + _ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3); + _ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 4, 1); + if ((pixel_fmt == IPU_PIX_FMT_YUYV) || + (pixel_fmt == IPU_PIX_FMT_UYVY) || + (pixel_fmt == IPU_PIX_FMT_YVYU) || + (pixel_fmt == IPU_PIX_FMT_VYUY)) { + _ipu_dc_link_event(dc_chan, DC_ODD_UGDE1, 9, 5); + _ipu_dc_link_event(dc_chan, DC_EVEN_UGDE1, 8, 5); + } + } else { + _ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3); + _ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 7, 1); + if ((pixel_fmt == IPU_PIX_FMT_YUYV) || + (pixel_fmt == IPU_PIX_FMT_UYVY) || + (pixel_fmt == IPU_PIX_FMT_YVYU) || + (pixel_fmt == IPU_PIX_FMT_VYUY)) { + _ipu_dc_link_event(dc_chan, DC_ODD_UGDE0, 10, 5); + _ipu_dc_link_event(dc_chan, DC_EVEN_UGDE0, 11, 5); + } + } + } + _ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); + + reg = 0x2; + reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; + reg |= di << 2; + if (interlaced) + reg |= DC_WR_CH_CONF_FIELD_MODE; + } else if ((dc_chan == 8) || (dc_chan == 9)) { + /* async channels */ + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1); + + reg = 0x3; + reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; + } + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan)); + + __raw_writel(0x00000084, DC_GEN); +} + +void _ipu_dc_uninit(int dc_chan) +{ + if ((dc_chan == 1) || (dc_chan == 5)) { + _ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); + _ipu_dc_link_event(dc_chan, DC_ODD_UGDE0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVEN_UGDE0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_ODD_UGDE1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVEN_UGDE1, 0, 0); + } else if ((dc_chan == 8) || (dc_chan == 9)) { + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0); + _ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0); + } +} + +int _ipu_disp_chan_is_interlaced(ipu_channel_t channel) +{ + if (channel == MEM_DC_SYNC) + return !!(__raw_readl(DC_WR_CH_CONF_1) & + DC_WR_CH_CONF_FIELD_MODE); + else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC)) + return !!(__raw_readl(DC_WR_CH_CONF_5) & + DC_WR_CH_CONF_FIELD_MODE); + return 0; +} + +void _ipu_dp_dc_enable(ipu_channel_t channel) +{ + int di; + uint32_t reg; + uint32_t dc_chan; + int irq = 0; + + if (channel == MEM_FG_SYNC) + irq = IPU_IRQ_DP_SF_END; + else if (channel == MEM_DC_SYNC) + dc_chan = 1; + else if (channel == MEM_BG_SYNC) + dc_chan = 5; + else + return; + + if (channel == MEM_FG_SYNC) { + /* Enable FG channel */ + reg = __raw_readl(DP_COM_CONF(DP_SYNC)); + __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC)); + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + return; + } + + di = g_dc_di_assignment[dc_chan]; + + /* Make sure other DC sync channel is not assigned same DI */ + reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); + if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) { + reg &= ~DC_WR_CH_CONF_PROG_DI_ID; + reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID; + __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); + } + + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + clk_enable(g_pixel_clk[di]); +} + +static bool dc_swap; + +static irqreturn_t dc_irq_handler(int irq, void *dev_id) +{ + struct completion *comp = dev_id; + uint32_t reg; + uint32_t dc_chan; + + if (irq == IPU_IRQ_DC_FC_1) + dc_chan = 1; + else + dc_chan = 5; + + if (!dc_swap) { + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + reg = __raw_readl(IPU_DISP_GEN); + if (g_dc_di_assignment[dc_chan]) + reg &= ~DI1_COUNTER_RELEASE; + else + reg &= ~DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); + } + + complete(comp); + return IRQ_HANDLED; +} + +void _ipu_dp_dc_disable(ipu_channel_t channel, bool swap) +{ + int ret; + unsigned long lock_flags; + uint32_t reg; + uint32_t csc; + uint32_t dc_chan; + int irq = 0; + int timeout = 50; + DECLARE_COMPLETION_ONSTACK(dc_comp); + + dc_swap = swap; + + if (channel == MEM_DC_SYNC) { + dc_chan = 1; + irq = IPU_IRQ_DC_FC_1; + } else if (channel == MEM_BG_SYNC) { + dc_chan = 5; + irq = IPU_IRQ_DP_SF_END; + } else if (channel == MEM_FG_SYNC) { + /* Disable FG channel */ + dc_chan = 5; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(DP_COM_CONF(DP_SYNC)); + csc = reg & DP_COM_CONF_CSC_DEF_MASK; + if (csc == DP_COM_CONF_CSC_DEF_FG) + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + + reg &= ~DP_COM_CONF_FG_EN; + __raw_writel(reg, DP_COM_CONF(DP_SYNC)); + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END), + IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)); + while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) & + IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) { + msleep(2); + timeout -= 2; + if (timeout <= 0) + break; + } + return; + } else { + return; + } + + if (!dc_swap) + __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_VSYNC_PRE_0 + + g_dc_di_assignment[dc_chan]), + IPUIRQ_2_STATREG(IPU_IRQ_VSYNC_PRE_0 + + g_dc_di_assignment[dc_chan])); + ipu_clear_irq(irq); + ret = ipu_request_irq(irq, dc_irq_handler, 0, NULL, &dc_comp); + if (ret < 0) { + dev_err(g_ipu_dev, "DC irq %d in use\n", irq); + return; + } + ret = wait_for_completion_timeout(&dc_comp, msecs_to_jiffies(50)); + + dev_dbg(g_ipu_dev, "DC stop timeout - %d * 10ms\n", 5 - ret); + ipu_free_irq(irq, &dc_comp); + + if (dc_swap) { + spin_lock_irqsave(&ipu_lock, lock_flags); + /* Swap DC channel 1 and 5 settings, and disable old dc chan */ + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); + reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; + reg ^= DC_WR_CH_CONF_PROG_DI_ID; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + } else { + /* Clock is already off because it must be done quickly, but + we need to fix the ref count */ + clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]); + + if (__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_VSYNC_PRE_0 + + g_dc_di_assignment[dc_chan])) & + IPUIRQ_2_MASK(IPU_IRQ_VSYNC_PRE_0 + + g_dc_di_assignment[dc_chan])) + dev_dbg(g_ipu_dev, + "VSyncPre occurred before DI%d disable\n", + g_dc_di_assignment[dc_chan]); + } +} + +void _ipu_init_dc_mappings(void) +{ + /* IPU_PIX_FMT_RGB24 */ + _ipu_dc_map_clear(0); + _ipu_dc_map_config(0, 0, 7, 0xFF); + _ipu_dc_map_config(0, 1, 15, 0xFF); + _ipu_dc_map_config(0, 2, 23, 0xFF); + + /* IPU_PIX_FMT_RGB666 */ + _ipu_dc_map_clear(1); + _ipu_dc_map_config(1, 0, 5, 0xFC); + _ipu_dc_map_config(1, 1, 11, 0xFC); + _ipu_dc_map_config(1, 2, 17, 0xFC); + + /* IPU_PIX_FMT_YUV444 */ + _ipu_dc_map_clear(2); + _ipu_dc_map_config(2, 0, 15, 0xFF); + _ipu_dc_map_config(2, 1, 23, 0xFF); + _ipu_dc_map_config(2, 2, 7, 0xFF); + + /* IPU_PIX_FMT_RGB565 */ + _ipu_dc_map_clear(3); + _ipu_dc_map_config(3, 0, 4, 0xF8); + _ipu_dc_map_config(3, 1, 10, 0xFC); + _ipu_dc_map_config(3, 2, 15, 0xF8); + + /* IPU_PIX_FMT_LVDS666 */ + _ipu_dc_map_clear(4); + _ipu_dc_map_config(4, 0, 5, 0xFC); + _ipu_dc_map_config(4, 1, 13, 0xFC); + _ipu_dc_map_config(4, 2, 21, 0xFC); + + /* IPU_PIX_FMT_VYUY 16bit width */ + _ipu_dc_map_clear(5); + _ipu_dc_map_config(5, 0, 7, 0xFF); + _ipu_dc_map_config(5, 1, 0, 0x0); + _ipu_dc_map_config(5, 2, 15, 0xFF); + _ipu_dc_map_clear(6); + _ipu_dc_map_config(6, 0, 0, 0x0); + _ipu_dc_map_config(6, 1, 7, 0xFF); + _ipu_dc_map_config(6, 2, 15, 0xFF); + + /* IPU_PIX_FMT_UYUV 16bit width */ + _ipu_dc_map_clear(7); + _ipu_dc_map_link(7, 6, 0, 6, 1, 6, 2); + _ipu_dc_map_clear(8); + _ipu_dc_map_link(8, 5, 0, 5, 1, 5, 2); + + /* IPU_PIX_FMT_YUYV 16bit width */ + _ipu_dc_map_clear(9); + _ipu_dc_map_link(9, 5, 2, 5, 1, 5, 0); + _ipu_dc_map_clear(10); + _ipu_dc_map_link(10, 5, 1, 5, 2, 5, 0); + + /* IPU_PIX_FMT_YVYU 16bit width */ + _ipu_dc_map_clear(11); + _ipu_dc_map_link(11, 5, 1, 5, 2, 5, 0); + _ipu_dc_map_clear(12); + _ipu_dc_map_link(12, 5, 2, 5, 1, 5, 0); + + /* IPU_PIX_FMT_GBR24 */ + _ipu_dc_map_clear(13); + _ipu_dc_map_link(13, 0, 2, 0, 0, 0, 1); +} + +int _ipu_pixfmt_to_map(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: + case IPU_PIX_FMT_RGB24: + return 0; + case IPU_PIX_FMT_RGB666: + return 1; + case IPU_PIX_FMT_YUV444: + return 2; + case IPU_PIX_FMT_RGB565: + return 3; + case IPU_PIX_FMT_LVDS666: + return 4; + case IPU_PIX_FMT_VYUY: + return 6; + case IPU_PIX_FMT_UYVY: + return 8; + case IPU_PIX_FMT_YUYV: + return 10; + case IPU_PIX_FMT_YVYU: + return 12; + case IPU_PIX_FMT_GBR24: + return 13; + } + + return -1; +} + +/*! + * This function sets the colorspace for of dp. + * modes. + * + * @param channel Input parameter for the logical channel ID. + * + * @param param If it's not NULL, update the csc table + * with this parameter. + * + * @return N/A + */ +void _ipu_dp_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]) +{ + int dp; + struct dp_csc_param_t dp_csc_param; + + if (channel == MEM_FG_SYNC) + dp = DP_SYNC; + else if (channel == MEM_BG_SYNC) + dp = DP_SYNC; + else if (channel == MEM_BG_ASYNC0) + dp = DP_ASYNC0; + else + return; + + dp_csc_param.mode = -1; + dp_csc_param.coeff = param; + __ipu_dp_csc_setup(dp, dp_csc_param, true); +} + +/*! + * This function is called to adapt synchronous LCD panel to IPU restriction. + * + */ +void adapt_panel_to_ipu_restricitions(uint16_t *v_start_width, + uint16_t *v_sync_width, + uint16_t *v_end_width) +{ + if (*v_end_width < 2) { + uint16_t diff = 2 - *v_end_width; + if (*v_start_width >= diff) { + *v_end_width = 2; + *v_start_width = *v_start_width - diff; + } else if (*v_sync_width > diff) { + *v_end_width = 2; + *v_sync_width = *v_sync_width - diff; + } else + dev_err(g_ipu_dev, "WARNING: try to adapt timming, but failed\n"); + dev_err(g_ipu_dev, "WARNING: adapt panel end blank lines\n"); + } +} + +/*! + * This function is called to initialize a synchronous LCD panel. + * + * @param disp The DI the panel is attached to. + * + * @param pixel_clk Desired pixel clock frequency in Hz. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width The width of panel in pixels. + * + * @param height The height of panel in pixels. + * + * @param hStartWidth The number of pixel clocks between the HSYNC + * signal pulse and the start of valid data. + * + * @param hSyncWidth The width of the HSYNC signal in units of pixel + * clocks. + * + * @param hEndWidth The number of pixel clocks between the end of + * valid data and the HSYNC signal for next line. + * + * @param vStartWidth The number of lines between the VSYNC + * signal pulse and the start of valid data. + * + * @param vSyncWidth The width of the VSYNC signal in units of lines + * + * @param vEndWidth The number of lines between the end of valid + * data and the VSYNC signal for next frame. + * + * @param sig Bitfield of signal polarities for LCD interface. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig) +{ + unsigned long lock_flags; + uint32_t field0_offset = 0; + uint32_t field1_offset; + uint32_t reg; + uint32_t di_gen, vsync_cnt; + uint32_t div, rounded_pixel_clk; + uint32_t h_total, v_total; + int map; + int ipu_freq_scaling_enabled = 0; + struct clk *di_parent; + + dev_dbg(g_ipu_dev, "panel size = %d x %d\n", width, height); + + if ((v_sync_width == 0) || (h_sync_width == 0)) + return EINVAL; + + adapt_panel_to_ipu_restricitions(&v_start_width, &v_sync_width, &v_end_width); + h_total = width + h_sync_width + h_start_width + h_end_width; + v_total = height + v_sync_width + v_start_width + v_end_width; + + /* Init clocking */ + dev_dbg(g_ipu_dev, "pixel clk = %d\n", pixel_clk); + + /*clear DI*/ + __raw_writel((1 << 21), DI_GENERAL(disp)); + + di_parent = clk_get_parent(g_di_clk[disp]); + if (clk_get(NULL, "tve_clk") == di_parent || + clk_get(NULL, "ldb_di0_clk") == di_parent || + clk_get(NULL, "ldb_di1_clk") == di_parent) { + /* if di clk parent is tve/ldb, then keep it;*/ + dev_dbg(g_ipu_dev, "use special clk parent\n"); + clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]); + } else { + /* try ipu clk first*/ + dev_dbg(g_ipu_dev, "try ipu internal clk\n"); + clk_set_parent(g_pixel_clk[disp], g_ipu_clk); + rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); + /* + * we will only use 1/2 fraction for ipu clk, + * so if the clk rate is not fit, try ext clk. + */ + if (!sig.int_clk && + ((rounded_pixel_clk >= pixel_clk + pixel_clk/16) || + (rounded_pixel_clk <= pixel_clk - pixel_clk/16))) { + dev_dbg(g_ipu_dev, "try ipu ext di clk\n"); + rounded_pixel_clk = pixel_clk * 2; + while (rounded_pixel_clk < 150000000) + rounded_pixel_clk += pixel_clk * 2; + clk_set_rate(di_parent, rounded_pixel_clk); + rounded_pixel_clk = + clk_round_rate(g_di_clk[disp], pixel_clk); + clk_set_rate(g_di_clk[disp], rounded_pixel_clk); + clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]); + } + } + rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); + clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); + msleep(5); + /* Get integer portion of divider */ + div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / rounded_pixel_clk; + + ipu_freq_scaling_enabled = dvfs_per_pixel_clk_limit(); + + if (ipu_freq_scaling_enabled) { + /* Enable for a divide by 2 clock change. */ + reg = __raw_readl(IPU_PM); + reg &= ~(0x7f << 7); + reg |= 0x20 << 7; + reg &= ~(0x7f << 23); + reg |= 0x20 << 23; + __raw_writel(reg, IPU_PM); + } + spin_lock_irqsave(&ipu_lock, lock_flags); + + _ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); + _ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); + + map = _ipu_pixfmt_to_map(pixel_fmt); + if (map < 0) { + dev_dbg(g_ipu_dev, "IPU_DISP: No MAP\n"); + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return -EINVAL; + } + + di_gen = __raw_readl(DI_GENERAL(disp)); + + if (sig.interlaced) { + if (g_ipu_hw_rev >= 2) { + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config( + disp, /* display */ + 1, /* counter */ + h_total/2 - 1, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Field 1 VSYNC waveform */ + _ipu_di_sync_config( + disp, /* display */ + 2, /* counter */ + h_total - 1, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 2*div /* COUNT DOWN */ + ); + + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config( + disp, /* display */ + 3, /* counter */ + v_total*2 - 1, /* run count */ + DI_SYNC_INT_HSYNC, /* run_resolution */ + 1, /* offset */ + DI_SYNC_INT_HSYNC, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 2*div /* COUNT DOWN */ + ); + + /* Active Field ? */ + _ipu_di_sync_config( + disp, /* display */ + 4, /* counter */ + v_total/2 - 1, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + v_start_width, /* offset */ + DI_SYNC_HSYNC, /* offset resolution */ + 2, /* repeat count */ + DI_SYNC_VSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Active Line */ + _ipu_di_sync_config( + disp, /* display */ + 5, /* counter */ + 0, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + height/2, /* repeat count */ + 4, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Field 0 VSYNC waveform */ + _ipu_di_sync_config( + disp, /* display */ + 6, /* counter */ + v_total - 1, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* DC VSYNC waveform */ + vsync_cnt = 7; + _ipu_di_sync_config( + disp, /* display */ + 7, /* counter */ + v_total/2 - 1, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 9, /* offset */ + DI_SYNC_HSYNC, /* offset resolution */ + 2, /* repeat count */ + DI_SYNC_VSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* active pixel waveform */ + _ipu_di_sync_config( + disp, /* display */ + 8, /* counter */ + 0, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + h_start_width, /* offset */ + DI_SYNC_CLK, /* offset resolution */ + width, /* repeat count */ + 5, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Second VSYNC */ + _ipu_di_sync_config( + disp, /* display */ + 9, /* counter */ + v_total - 1, /* run count */ + DI_SYNC_INT_HSYNC, /* run_resolution */ + v_total/2, /* offset */ + DI_SYNC_INT_HSYNC, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_HSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 2*div /* COUNT DOWN */ + ); + + /* set gentime select and tag sel */ + reg = __raw_readl(DI_SW_GEN1(disp, 9)); + reg &= 0x1FFFFFFF; + reg |= (3-1)<<29 | 0x00008000; + __raw_writel(reg, DI_SW_GEN1(disp, 9)); + + __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp)); + + /* set y_sel = 1 */ + di_gen |= 0x10000000; + di_gen |= DI_GEN_POLARITY_5; + di_gen |= DI_GEN_POLARITY_8; + } else { + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + field1_offset = v_sync_width + v_start_width + height / 2 + + v_end_width; + if (sig.odd_field_first) { + field0_offset = field1_offset - 1; + field1_offset = 0; + } + v_total += v_start_width + v_end_width; + + /* Field 1 VSYNC waveform */ + _ipu_di_sync_config(disp, 2, v_total - 1, 1, + field0_offset, + field0_offset ? 1 : DI_SYNC_NONE, + 0, DI_SYNC_NONE, 0, + DI_SYNC_NONE, DI_SYNC_NONE, 0, 4); + + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config(disp, 3, h_total - 1, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, + DI_SYNC_NONE, DI_SYNC_NONE, 0, 4); + + /* Active Field ? */ + _ipu_di_sync_config(disp, 4, + field0_offset ? + field0_offset : field1_offset - 2, + 1, v_start_width + v_sync_width, 1, 2, 2, + 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); + + /* Active Line */ + _ipu_di_sync_config(disp, 5, 0, 1, + 0, DI_SYNC_NONE, + height / 2, 4, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + /* Field 0 VSYNC waveform */ + _ipu_di_sync_config(disp, 6, v_total - 1, 1, + 0, DI_SYNC_NONE, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + /* DC VSYNC waveform */ + vsync_cnt = 7; + _ipu_di_sync_config(disp, 7, 0, 1, + field1_offset, + field1_offset ? 1 : DI_SYNC_NONE, + 1, 2, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); + + /* active pixel waveform */ + _ipu_di_sync_config(disp, 8, 0, DI_SYNC_CLK, + h_sync_width + h_start_width, DI_SYNC_CLK, + width, 5, 0, DI_SYNC_NONE, DI_SYNC_NONE, + 0, 0); + + /* ??? */ + _ipu_di_sync_config(disp, 9, v_total - 1, 2, + 0, DI_SYNC_NONE, + 0, DI_SYNC_NONE, 6, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + reg = __raw_readl(DI_SW_GEN1(disp, 9)); + reg |= 0x8000; + __raw_writel(reg, DI_SW_GEN1(disp, 9)); + + __raw_writel(v_sync_width + v_start_width + + v_end_width + height / 2 - 1, DI_SCR_CONF(disp)); + } + + /* Init template microcode */ + _ipu_dc_write_tmpl(0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1); + + if (sig.Hsync_pol) + di_gen |= DI_GEN_POLARITY_3; + if (sig.Vsync_pol) + di_gen |= DI_GEN_POLARITY_2; + } else { + /* Setup internal HSYNC waveform */ + _ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + /* Setup external (delayed) HSYNC waveform */ + _ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1, + DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_CLK, 0, h_sync_width * 2); + /* Setup VSYNC waveform */ + vsync_cnt = DI_SYNC_VSYNC; + _ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1, + DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0, + DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_INT_HSYNC, 0, v_sync_width * 2); + __raw_writel(v_total - 1, DI_SCR_CONF(disp)); + + /* Setup active data waveform to sync with DC */ + _ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC, + v_sync_width + v_start_width, DI_SYNC_HSYNC, height, + DI_SYNC_VSYNC, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + _ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK, + h_sync_width + h_start_width, DI_SYNC_CLK, + width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, + 0); + + /* set VGA delayed hsync/vsync no matter VGA enabled */ + if (disp) { + /* couter 7 for VGA delay HSYNC */ + _ipu_di_sync_config(disp, 7, + h_total - 1, DI_SYNC_CLK, + 18, DI_SYNC_CLK, + 0, DI_SYNC_NONE, + 1, DI_SYNC_NONE, DI_SYNC_CLK, + 0, h_sync_width * 2); + + /* couter 8 for VGA delay VSYNC */ + _ipu_di_sync_config(disp, 8, + v_total - 1, DI_SYNC_INT_HSYNC, + 1, DI_SYNC_INT_HSYNC, + 0, DI_SYNC_NONE, + 1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC, + 0, v_sync_width * 2); + } + + /* reset all unused counters */ + __raw_writel(0, DI_SW_GEN0(disp, 6)); + __raw_writel(0, DI_SW_GEN1(disp, 6)); + if (!disp) { + __raw_writel(0, DI_SW_GEN0(disp, 7)); + __raw_writel(0, DI_SW_GEN1(disp, 7)); + __raw_writel(0, DI_STP_REP(disp, 7)); + __raw_writel(0, DI_SW_GEN0(disp, 8)); + __raw_writel(0, DI_SW_GEN1(disp, 8)); + __raw_writel(0, DI_STP_REP(disp, 8)); + } + __raw_writel(0, DI_SW_GEN0(disp, 9)); + __raw_writel(0, DI_SW_GEN1(disp, 9)); + __raw_writel(0, DI_STP_REP(disp, 9)); + + reg = __raw_readl(DI_STP_REP(disp, 6)); + reg &= 0x0000FFFF; + __raw_writel(reg, DI_STP_REP(disp, 6)); + + if (ipu_freq_scaling_enabled) { + h_total = ((width + h_start_width + + h_sync_width) / 2) - 2; + _ipu_di_sync_config(disp, 6, 1, 0, + 2, DI_SYNC_CLK, + h_total, + DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + } + + /* Init template microcode */ + if (disp) { + if ((pixel_fmt == IPU_PIX_FMT_YUYV) || + (pixel_fmt == IPU_PIX_FMT_UYVY) || + (pixel_fmt == IPU_PIX_FMT_YVYU) || + (pixel_fmt == IPU_PIX_FMT_VYUY)) { + _ipu_dc_write_tmpl(8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1); + _ipu_dc_write_tmpl(9, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); + /* configure user events according to DISP NUM */ + __raw_writel((width - 1), DC_UGDE_3(disp)); + } + _ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1); + _ipu_dc_write_tmpl(3, WRG, 0, map, SYNC_WAVE, 4, 5, 1); + _ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); + } else { + if ((pixel_fmt == IPU_PIX_FMT_YUYV) || + (pixel_fmt == IPU_PIX_FMT_UYVY) || + (pixel_fmt == IPU_PIX_FMT_YVYU) || + (pixel_fmt == IPU_PIX_FMT_VYUY)) { + _ipu_dc_write_tmpl(10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1); + _ipu_dc_write_tmpl(11, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); + /* configure user events according to DISP NUM */ + __raw_writel(width - 1, DC_UGDE_3(disp)); + } + _ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1); + _ipu_dc_write_tmpl(6, WRG, 0, map, SYNC_WAVE, 4, 5, 1); + _ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); + } + + if (sig.Hsync_pol) { + di_gen |= DI_GEN_POLARITY_2; + if (disp) + di_gen |= DI_GEN_POLARITY_7; + } + if (sig.Vsync_pol) { + di_gen |= DI_GEN_POLARITY_3; + if (disp) + di_gen |= DI_GEN_POLARITY_8; + } + + if (ipu_freq_scaling_enabled) + /* Set the clock to stop at counter 6. */ + di_gen |= 0x6000000; + } + /* changinc DISP_CLK polarity: it can be wrong for some applications */ + if ((pixel_fmt == IPU_PIX_FMT_YUYV) || + (pixel_fmt == IPU_PIX_FMT_UYVY) || + (pixel_fmt == IPU_PIX_FMT_YVYU) || + (pixel_fmt == IPU_PIX_FMT_VYUY)) + di_gen |= 0x00020000; + + if (!sig.clk_pol) + di_gen |= DI_GEN_POLARITY_DISP_CLK; + + __raw_writel(di_gen, DI_GENERAL(disp)); + + if (!ipu_freq_scaling_enabled) + __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | + 0x00000002, DI_SYNC_AS_GEN(disp)); + else { + if (sig.interlaced) + __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | + 0x00000002, DI_SYNC_AS_GEN(disp)); + else + __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET), + DI_SYNC_AS_GEN(disp)); + } + + reg = __raw_readl(DI_POL(disp)); + reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); + if (sig.enable_pol) + reg |= DI_POL_DRDY_POLARITY_15; + if (sig.data_pol) + reg |= DI_POL_DRDY_DATA_POLARITY; + __raw_writel(reg, DI_POL(disp)); + + __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp))); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + + return 0; +} +EXPORT_SYMBOL(ipu_init_sync_panel); + + +int ipu_init_async_panel(int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig) +{ + unsigned long lock_flags; + int map; + u32 ser_conf = 0; + u32 div; + u32 di_clk = clk_get_rate(g_ipu_clk); + + /* round up cycle_time, then calcalate the divider using scaled math */ + cycle_time += (1000000000UL / di_clk) - 1; + div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL); + + map = _ipu_pixfmt_to_map(pixel_fmt); + if (map < 0) + return -EINVAL; + + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (type == IPU_PANEL_SERIAL) { + __raw_writel((div << 24) | ((sig.ifc_width - 1) << 4), + DI_DW_GEN(disp, ASYNC_SER_WAVE)); + + _ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_CS, + 0, 0, (div * 2) + 1); + _ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK, + 1, div, div * 2); + _ipu_di_data_pin_config(disp, ASYNC_SER_WAVE, DI_PIN_SER_RS, + 2, 0, 0); + + _ipu_dc_write_tmpl(0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0, 1); + + /* Configure DC for serial panel */ + __raw_writel(0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL)); + + if (sig.clk_pol) + ser_conf |= DI_SER_CONF_SERIAL_CLK_POL; + if (sig.data_pol) + ser_conf |= DI_SER_CONF_SERIAL_DATA_POL; + if (sig.rs_pol) + ser_conf |= DI_SER_CONF_SERIAL_RS_POL; + if (sig.cs_pol) + ser_conf |= DI_SER_CONF_SERIAL_CS_POL; + __raw_writel(ser_conf, DI_SER_CONF(disp)); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + return 0; +} +EXPORT_SYMBOL(ipu_init_async_panel); + +/*! + * This function sets the foreground and background plane global alpha blending + * modes. This function also sets the DP graphic plane according to the + * parameter of IPUv3 DP channel. + * + * @param channel IPUv3 DP channel + * + * @param enable Boolean to enable or disable global alpha + * blending. If disabled, local blending is used. + * + * @param alpha Global alpha value. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, bool enable, + uint8_t alpha) +{ + uint32_t reg; + uint32_t flow; + unsigned long lock_flags; + bool bg_chan; + + if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 || + channel == MEM_BG_ASYNC1) + bg_chan = true; + else + bg_chan = false; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + spin_lock_irqsave(&ipu_lock, lock_flags); + + if (bg_chan) { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow)); + } else { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow)); + } + + if (enable) { + reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL; + __raw_writel(reg | ((uint32_t) alpha << 24), + DP_GRAPH_WIND_CTRL(flow)); + + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow)); + } else { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow)); + } + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} +EXPORT_SYMBOL(ipu_disp_set_global_alpha); + +/*! + * This function sets the transparent color key for SDC graphic plane. + * + * @param channel Input parameter for the logical channel ID. + * + * @param enable Boolean to enable or disable color key + * + * @param colorKey 24-bit RGB color for transparent color key. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_color_key(ipu_channel_t channel, bool enable, + uint32_t color_key) +{ + uint32_t reg, flow; + int y, u, v; + int red, green, blue; + unsigned long lock_flags; + + if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + color_key_4rgb = 1; + /* Transform color key from rgb to yuv if CSC is enabled */ + if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) { + + dev_dbg(g_ipu_dev, "color key 0x%x need change to yuv fmt\n", color_key); + + red = (color_key >> 16) & 0xFF; + green = (color_key >> 8) & 0xFF; + blue = color_key & 0xFF; + + y = _rgb_to_yuv(0, red, green, blue); + u = _rgb_to_yuv(1, red, green, blue); + v = _rgb_to_yuv(2, red, green, blue); + color_key = (y << 16) | (u << 8) | v; + + color_key_4rgb = 0; + + dev_dbg(g_ipu_dev, "color key change to yuv fmt 0x%x\n", color_key); + } + + if (enable) { + reg = __raw_readl(DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L; + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL(flow)); + + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow)); + } else { + reg = __raw_readl(DP_COM_CONF(flow)); + __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow)); + } + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} +EXPORT_SYMBOL(ipu_disp_set_color_key); + +/*! + * This function sets the gamma correction for DP output. + * + * @param channel Input parameter for the logical channel ID. + * + * @param enable Boolean to enable or disable gamma correction. + * + * @param constk Gamma piecewise linear approximation constk coeff. + * + * @param slopek Gamma piecewise linear approximation slopek coeff. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_gamma_correction(ipu_channel_t channel, bool enable, int constk[], int slopek[]) +{ + uint32_t reg, flow, i; + unsigned long lock_flags; + + if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + spin_lock_irqsave(&ipu_lock, lock_flags); + + for (i = 0; i < 8; i++) + __raw_writel((constk[2*i] & 0x1ff) | ((constk[2*i+1] & 0x1ff) << 16), DP_GAMMA_C(flow, i)); + for (i = 0; i < 4; i++) + __raw_writel((slopek[4*i] & 0xff) | ((slopek[4*i+1] & 0xff) << 8) | + ((slopek[4*i+2] & 0xff) << 16) | ((slopek[4*i+3] & 0xff) << 24), DP_GAMMA_S(flow, i)); + + reg = __raw_readl(DP_COM_CONF(flow)); + if (enable) { + if ((bg_csc_type == RGB2YUV) || (bg_csc_type == YUV2YUV)) + reg |= DP_COM_CONF_GAMMA_YUV_EN; + else + reg &= ~DP_COM_CONF_GAMMA_YUV_EN; + __raw_writel(reg | DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow)); + } else + __raw_writel(reg & ~DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow)); + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} +EXPORT_SYMBOL(ipu_disp_set_gamma_correction); + +/*! + * This function sets the window position of the foreground or background plane. + * modes. + * + * @param channel Input parameter for the logical channel ID. + * + * @param x_pos The X coordinate position to place window at. + * The position is relative to the top left corner. + * + * @param y_pos The Y coordinate position to place window at. + * The position is relative to the top left corner. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_window_pos(ipu_channel_t channel, int16_t x_pos, + int16_t y_pos) +{ + u32 reg; + unsigned long lock_flags; + uint32_t flow = 0; + uint32_t dp_srm_shift; + + if (channel == MEM_FG_SYNC) { + flow = DP_SYNC; + dp_srm_shift = 3; + } else if (channel == MEM_FG_ASYNC0) { + flow = DP_ASYNC0; + dp_srm_shift = 5; + } else if (channel == MEM_FG_ASYNC1) { + flow = DP_ASYNC1; + dp_srm_shift = 7; + } else + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + spin_lock_irqsave(&ipu_lock, lock_flags); + + __raw_writel((x_pos << 16) | y_pos, DP_FG_POS(flow)); + + if (ipu_is_channel_busy(channel)) { + /* controled by FSU if channel enabled */ + reg = __raw_readl(IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift)); + reg |= (0x1 << dp_srm_shift); + __raw_writel(reg, IPU_SRM_PRI2); + } else { + /* disable auto swap, controled by MCU if channel disabled */ + reg = __raw_readl(IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift)); + __raw_writel(reg, IPU_SRM_PRI2); + } + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} +EXPORT_SYMBOL(ipu_disp_set_window_pos); + +int32_t ipu_disp_get_window_pos(ipu_channel_t channel, int16_t *x_pos, + int16_t *y_pos) +{ + u32 reg; + unsigned long lock_flags; + uint32_t flow = 0; + + if (channel == MEM_FG_SYNC) + flow = DP_SYNC; + else if (channel == MEM_FG_ASYNC0) + flow = DP_ASYNC0; + else if (channel == MEM_FG_ASYNC1) + flow = DP_ASYNC1; + else + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + spin_lock_irqsave(&ipu_lock, lock_flags); + + reg = __raw_readl(DP_FG_POS(flow)); + + *x_pos = (reg >> 16) & 0x7FF; + *y_pos = reg & 0x7FF; + + spin_unlock_irqrestore(&ipu_lock, lock_flags); + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} +EXPORT_SYMBOL(ipu_disp_get_window_pos); + +void ipu_disp_direct_write(ipu_channel_t channel, u32 value, u32 offset) +{ + if (channel == DIRECT_ASYNC0) + __raw_writel(value, ipu_disp_base[0] + offset); + else if (channel == DIRECT_ASYNC1) + __raw_writel(value, ipu_disp_base[1] + offset); +} +EXPORT_SYMBOL(ipu_disp_direct_write); + +void ipu_reset_disp_panel(void) +{ + uint32_t tmp; + + tmp = __raw_readl(DI_GENERAL(1)); + __raw_writel(tmp | 0x08, DI_GENERAL(1)); + msleep(10); /* tRES >= 100us */ + tmp = __raw_readl(DI_GENERAL(1)); + __raw_writel(tmp & ~0x08, DI_GENERAL(1)); + msleep(60); + + return; +} +EXPORT_SYMBOL(ipu_reset_disp_panel); diff --git a/drivers/mxc/ipu3/ipu_ic.c b/drivers/mxc/ipu3/ipu_ic.c new file mode 100644 index 000000000000..80369f67c297 --- /dev/null +++ b/drivers/mxc/ipu3/ipu_ic.c @@ -0,0 +1,833 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_ic.c + * + * @brief IPU IC functions + * + * @ingroup IPU + */ +#include +#include +#include +#include +#include +#include +#include + +#include "ipu_prv.h" +#include "ipu_regs.h" +#include "ipu_param_mem.h" + +enum { + IC_TASK_VIEWFINDER, + IC_TASK_ENCODER, + IC_TASK_POST_PROCESSOR +}; + +static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format, + ipu_color_space_t out_format, int csc_index); +static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize, + uint32_t *resizeCoeff, + uint32_t *downsizeCoeff); + +void _ipu_vdi_set_top_field_man(bool top_field_0) +{ + uint32_t reg; + + reg = __raw_readl(VDI_C); + if (top_field_0) + reg &= ~VDI_C_TOP_FIELD_MAN_1; + else + reg |= VDI_C_TOP_FIELD_MAN_1; + __raw_writel(reg, VDI_C); +} + +void _ipu_vdi_set_motion(ipu_motion_sel motion_sel) +{ + uint32_t reg; + + reg = __raw_readl(VDI_C); + reg &= ~(VDI_C_MOT_SEL_FULL | VDI_C_MOT_SEL_MED | VDI_C_MOT_SEL_LOW); + if (motion_sel == HIGH_MOTION) + reg |= VDI_C_MOT_SEL_FULL; + else if (motion_sel == MED_MOTION) + reg |= VDI_C_MOT_SEL_MED; + else + reg |= VDI_C_MOT_SEL_LOW; + + __raw_writel(reg, VDI_C); +} + +void ic_dump_register(void) +{ + printk(KERN_DEBUG "IC_CONF = \t0x%08X\n", __raw_readl(IC_CONF)); + printk(KERN_DEBUG "IC_PRP_ENC_RSC = \t0x%08X\n", + __raw_readl(IC_PRP_ENC_RSC)); + printk(KERN_DEBUG "IC_PRP_VF_RSC = \t0x%08X\n", + __raw_readl(IC_PRP_VF_RSC)); + printk(KERN_DEBUG "IC_PP_RSC = \t0x%08X\n", __raw_readl(IC_PP_RSC)); + printk(KERN_DEBUG "IC_IDMAC_1 = \t0x%08X\n", __raw_readl(IC_IDMAC_1)); + printk(KERN_DEBUG "IC_IDMAC_2 = \t0x%08X\n", __raw_readl(IC_IDMAC_2)); + printk(KERN_DEBUG "IC_IDMAC_3 = \t0x%08X\n", __raw_readl(IC_IDMAC_3)); +} + +void _ipu_ic_enable_task(ipu_channel_t channel) +{ + uint32_t ic_conf; + + ic_conf = __raw_readl(IC_CONF); + switch (channel) { + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + ic_conf |= IC_CONF_PRPVF_EN; + break; + case MEM_VDI_PRP_VF_MEM: + ic_conf |= IC_CONF_PRPVF_EN; + break; + case MEM_ROT_VF_MEM: + ic_conf |= IC_CONF_PRPVF_ROT_EN; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + ic_conf |= IC_CONF_PRPENC_EN; + break; + case MEM_ROT_ENC_MEM: + ic_conf |= IC_CONF_PRPENC_ROT_EN; + break; + case MEM_PP_MEM: + ic_conf |= IC_CONF_PP_EN; + break; + case MEM_ROT_PP_MEM: + ic_conf |= IC_CONF_PP_ROT_EN; + break; + default: + break; + } + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_disable_task(ipu_channel_t channel) +{ + uint32_t ic_conf; + + ic_conf = __raw_readl(IC_CONF); + switch (channel) { + case CSI_PRP_VF_MEM: + case MEM_PRP_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_EN; + break; + case MEM_VDI_PRP_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_EN; + break; + case MEM_ROT_VF_MEM: + ic_conf &= ~IC_CONF_PRPVF_ROT_EN; + break; + case CSI_PRP_ENC_MEM: + case MEM_PRP_ENC_MEM: + ic_conf &= ~IC_CONF_PRPENC_EN; + break; + case MEM_ROT_ENC_MEM: + ic_conf &= ~IC_CONF_PRPENC_ROT_EN; + break; + case MEM_PP_MEM: + ic_conf &= ~IC_CONF_PP_EN; + break; + case MEM_ROT_PP_MEM: + ic_conf &= ~IC_CONF_PP_ROT_EN; + break; + default: + break; + } + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_vdi_init(ipu_channel_t channel, ipu_channel_params_t *params) +{ + uint32_t reg; + uint32_t pixel_fmt; + + reg = ((params->mem_prp_vf_mem.in_height-1) << 16) | + (params->mem_prp_vf_mem.in_width-1); + __raw_writel(reg, VDI_FSIZE); + + /* Full motion, only vertical filter is used + Burst size is 4 accesses */ + if (params->mem_prp_vf_mem.in_pixel_fmt == + IPU_PIX_FMT_UYVY || + params->mem_prp_vf_mem.in_pixel_fmt == + IPU_PIX_FMT_YUYV) + pixel_fmt = VDI_C_CH_422; + else + pixel_fmt = VDI_C_CH_420; + + reg = __raw_readl(VDI_C); + reg |= pixel_fmt; + switch (channel) { + case MEM_VDI_PRP_VF_MEM: + reg |= VDI_C_BURST_SIZE2_4; + break; + case MEM_VDI_PRP_VF_MEM_P: + reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_SET_1 | VDI_C_VWM1_CLR_2; + break; + case MEM_VDI_PRP_VF_MEM_N: + reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_SET_1 | VDI_C_VWM3_CLR_2; + break; + default: + break; + } + __raw_writel(reg, VDI_C); + + if (params->mem_prp_vf_mem.field_fmt == V4L2_FIELD_INTERLACED_TB) + _ipu_vdi_set_top_field_man(false); + else if (params->mem_prp_vf_mem.field_fmt == V4L2_FIELD_INTERLACED_BT) + _ipu_vdi_set_top_field_man(true); + + _ipu_vdi_set_motion(params->mem_prp_vf_mem.motion_sel); + + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_RWS_EN; + __raw_writel(reg, IC_CONF); +} + +void _ipu_vdi_uninit(void) +{ + __raw_writel(0, VDI_FSIZE); + __raw_writel(0, VDI_C); +} + +void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_prp_vf_mem.in_height, + params->mem_prp_vf_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + /* Upadeted for IC split case */ + if (!(params->mem_prp_vf_mem.outh_resize_ratio)) { + _calc_resize_coeffs(params->mem_prp_vf_mem.in_width, + params->mem_prp_vf_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + } else + reg |= params->mem_prp_vf_mem.outh_resize_ratio; + + __raw_writel(reg, IC_PRP_VF_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* Enable RGB->YCBCR CSC1 */ + _init_csc(IC_TASK_VIEWFINDER, RGB, out_fmt, 1); + ic_conf |= IC_CONF_PRPVF_CSC1; + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + /* Enable YCBCR->RGB CSC1 */ + _init_csc(IC_TASK_VIEWFINDER, YCbCr, RGB, 1); + ic_conf |= IC_CONF_PRPVF_CSC1; + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_prp_vf_mem.graphics_combine_en) { + ic_conf |= IC_CONF_PRPVF_CMB; + + if (!(ic_conf & IC_CONF_PRPVF_CSC1)) { + /* need transparent CSC1 conversion */ + _init_csc(IC_TASK_VIEWFINDER, RGB, RGB, 1); + ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->RGB CSC */ + } + in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_g_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* Enable RGB->YCBCR CSC2 */ + _init_csc(IC_TASK_VIEWFINDER, RGB, out_fmt, 2); + ic_conf |= IC_CONF_PRPVF_CSC2; + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + /* Enable YCBCR->RGB CSC2 */ + _init_csc(IC_TASK_VIEWFINDER, YCbCr, RGB, 2); + ic_conf |= IC_CONF_PRPVF_CSC2; + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_prp_vf_mem.global_alpha_en) { + ic_conf |= IC_CONF_IC_GLB_LOC_A; + reg = __raw_readl(IC_CMBP_1); + reg &= ~(0xff); + reg |= params->mem_prp_vf_mem.alpha; + __raw_writel(reg, IC_CMBP_1); + } else + ic_conf &= ~IC_CONF_IC_GLB_LOC_A; + + if (params->mem_prp_vf_mem.key_color_en) { + ic_conf |= IC_CONF_KEY_COLOR_EN; + __raw_writel(params->mem_prp_vf_mem.key_color, + IC_CMBP_2); + } else + ic_conf &= ~IC_CONF_KEY_COLOR_EN; + } else { + ic_conf &= ~IC_CONF_PRPVF_CMB; + } + + if (src_is_csi) + ic_conf &= ~IC_CONF_RWS_EN; + else + ic_conf |= IC_CONF_RWS_EN; + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_prpvf(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB | + IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_vf(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_vf(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_PRPVF_ROT_EN; + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + _calc_resize_coeffs(params->mem_prp_enc_mem.in_height, + params->mem_prp_enc_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + + /* Setup horizontal resizing */ + /* Upadeted for IC split case */ + if (!(params->mem_prp_enc_mem.outh_resize_ratio)) { + _calc_resize_coeffs(params->mem_prp_enc_mem.in_width, + params->mem_prp_enc_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + } else + reg |= params->mem_prp_enc_mem.outh_resize_ratio; + + __raw_writel(reg, IC_PRP_ENC_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* Enable RGB->YCBCR CSC1 */ + _init_csc(IC_TASK_ENCODER, RGB, out_fmt, 1); + ic_conf |= IC_CONF_PRPENC_CSC1; + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + /* Enable YCBCR->RGB CSC1 */ + _init_csc(IC_TASK_ENCODER, YCbCr, RGB, 1); + ic_conf |= IC_CONF_PRPENC_CSC1; + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (src_is_csi) + ic_conf &= ~IC_CONF_RWS_EN; + else + ic_conf |= IC_CONF_RWS_EN; + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_prpenc(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_enc(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_enc(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PRPENC_ROT_EN); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_pp(ipu_channel_params_t *params) +{ + uint32_t reg, ic_conf; + uint32_t downsizeCoeff, resizeCoeff; + ipu_color_space_t in_fmt, out_fmt; + + /* Setup vertical resizing */ + if (!(params->mem_pp_mem.outv_resize_ratio)) { + _calc_resize_coeffs(params->mem_pp_mem.in_height, + params->mem_pp_mem.out_height, + &resizeCoeff, &downsizeCoeff); + reg = (downsizeCoeff << 30) | (resizeCoeff << 16); + } else { + reg = (params->mem_pp_mem.outv_resize_ratio) << 16; + } + + /* Setup horizontal resizing */ + /* Upadeted for IC split case */ + if (!(params->mem_pp_mem.outh_resize_ratio)) { + _calc_resize_coeffs(params->mem_pp_mem.in_width, + params->mem_pp_mem.out_width, + &resizeCoeff, &downsizeCoeff); + reg |= (downsizeCoeff << 14) | resizeCoeff; + } else { + reg |= params->mem_pp_mem.outh_resize_ratio; + } + + __raw_writel(reg, IC_PP_RSC); + + ic_conf = __raw_readl(IC_CONF); + + /* Setup color space conversion */ + in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* Enable RGB->YCBCR CSC1 */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, out_fmt, 1); + ic_conf |= IC_CONF_PP_CSC1; + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + /* Enable YCBCR->RGB CSC1 */ + _init_csc(IC_TASK_POST_PROCESSOR, YCbCr, RGB, 1); + ic_conf |= IC_CONF_PP_CSC1; + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_pp_mem.graphics_combine_en) { + ic_conf |= IC_CONF_PP_CMB; + + if (!(ic_conf & IC_CONF_PP_CSC1)) { + /* need transparent CSC1 conversion */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, RGB, 1); + ic_conf |= IC_CONF_PP_CSC1; /* Enable RGB->RGB CSC */ + } + + in_fmt = format_to_colorspace(params->mem_pp_mem.in_g_pixel_fmt); + out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt); + if (in_fmt == RGB) { + if ((out_fmt == YCbCr) || (out_fmt == YUV)) { + /* Enable RGB->YCBCR CSC2 */ + _init_csc(IC_TASK_POST_PROCESSOR, RGB, out_fmt, 2); + ic_conf |= IC_CONF_PP_CSC2; + } + } + if ((in_fmt == YCbCr) || (in_fmt == YUV)) { + if (out_fmt == RGB) { + /* Enable YCBCR->RGB CSC2 */ + _init_csc(IC_TASK_POST_PROCESSOR, YCbCr, RGB, 2); + ic_conf |= IC_CONF_PP_CSC2; + } else { + /* TODO: Support YUV<->YCbCr conversion? */ + } + } + + if (params->mem_pp_mem.global_alpha_en) { + ic_conf |= IC_CONF_IC_GLB_LOC_A; + reg = __raw_readl(IC_CMBP_1); + reg &= ~(0xff00); + reg |= (params->mem_pp_mem.alpha << 8); + __raw_writel(reg, IC_CMBP_1); + } else + ic_conf &= ~IC_CONF_IC_GLB_LOC_A; + + if (params->mem_pp_mem.key_color_en) { + ic_conf |= IC_CONF_KEY_COLOR_EN; + __raw_writel(params->mem_pp_mem.key_color, + IC_CMBP_2); + } else + ic_conf &= ~IC_CONF_KEY_COLOR_EN; + } else { + ic_conf &= ~IC_CONF_PP_CMB; + } + + __raw_writel(ic_conf, IC_CONF); +} + +void _ipu_ic_uninit_pp(void) +{ + uint32_t reg; + + reg = __raw_readl(IC_CONF); + reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 | + IC_CONF_PP_CMB); + __raw_writel(reg, IC_CONF); +} + +void _ipu_ic_init_rotate_pp(ipu_channel_params_t *params) +{ +} + +void _ipu_ic_uninit_rotate_pp(void) +{ + uint32_t reg; + reg = __raw_readl(IC_CONF); + reg &= ~IC_CONF_PP_ROT_EN; + __raw_writel(reg, IC_CONF); +} + +int _ipu_ic_idma_init(int dma_chan, uint16_t width, uint16_t height, + int burst_size, ipu_rotate_mode_t rot) +{ + u32 ic_idmac_1, ic_idmac_2, ic_idmac_3; + u32 temp_rot = bitrev8(rot) >> 5; + bool need_hor_flip = false; + + if ((burst_size != 8) && (burst_size != 16)) { + dev_dbg(g_ipu_dev, "Illegal burst length for IC\n"); + return -EINVAL; + } + + width--; + height--; + + if (temp_rot & 0x2) /* Need horizontal flip */ + need_hor_flip = true; + + ic_idmac_1 = __raw_readl(IC_IDMAC_1); + ic_idmac_2 = __raw_readl(IC_IDMAC_2); + ic_idmac_3 = __raw_readl(IC_IDMAC_3); + if (dma_chan == 22) { /* PP output - CB2 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16; + + if (need_hor_flip) + ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS; + else + ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS; + + ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK; + ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET; + + ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK; + ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET; + + } else if (dma_chan == 11) { /* PP Input - CB5 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16; + } else if (dma_chan == 47) { /* PP Rot input */ + ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK; + ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET; + } + + if (dma_chan == 12) { /* PRP Input - CB6 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16; + } + + if (dma_chan == 20) { /* PRP ENC output - CB0 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16; + + if (need_hor_flip) + ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS; + else + ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS; + + ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK; + ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET; + + ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK; + ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET; + + } else if (dma_chan == 45) { /* PRP ENC Rot input */ + ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK; + ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET; + } + + if (dma_chan == 21) { /* PRP VF output - CB1 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16; + + if (need_hor_flip) + ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS; + else + ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS; + + ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK; + ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET; + + ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK; + ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET; + + } else if (dma_chan == 46) { /* PRP VF Rot input */ + ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK; + ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET; + } + + if (dma_chan == 14) { /* PRP VF graphics combining input - CB3 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16; + } else if (dma_chan == 15) { /* PP graphics combining input - CB4 */ + if (burst_size == 16) + ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16; + else + ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16; + } + + __raw_writel(ic_idmac_1, IC_IDMAC_1); + __raw_writel(ic_idmac_2, IC_IDMAC_2); + __raw_writel(ic_idmac_3, IC_IDMAC_3); + + return 0; +} + +static void _init_csc(uint8_t ic_task, ipu_color_space_t in_format, + ipu_color_space_t out_format, int csc_index) +{ + +/* Y = R * .299 + G * .587 + B * .114; + U = R * -.169 + G * -.332 + B * .500 + 128.; + V = R * .500 + G * -.419 + B * -.0813 + 128.;*/ + static const uint32_t rgb2ycbcr_coeff[4][3] = { + {0x004D, 0x0096, 0x001D}, + {0x01D5, 0x01AB, 0x0080}, + {0x0080, 0x0195, 0x01EB}, + {0x0000, 0x0200, 0x0200}, /* A0, A1, A2 */ + }; + + /* transparent RGB->RGB matrix for combining + */ + static const uint32_t rgb2rgb_coeff[4][3] = { + {0x0080, 0x0000, 0x0000}, + {0x0000, 0x0080, 0x0000}, + {0x0000, 0x0000, 0x0080}, + {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */ + }; + +/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); + G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); + B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */ + static const uint32_t ycbcr2rgb_coeff[4][3] = { + {149, 0, 204}, + {149, 462, 408}, + {149, 255, 0}, + {8192 - 446, 266, 8192 - 554}, /* A0, A1, A2 */ + }; + + uint32_t param; + uint32_t *base = NULL; + + if (ic_task == IC_TASK_ENCODER) { + base = ipu_tpmem_base + 0x2008 / 4; + } else if (ic_task == IC_TASK_VIEWFINDER) { + if (csc_index == 1) + base = ipu_tpmem_base + 0x4028 / 4; + else + base = ipu_tpmem_base + 0x4040 / 4; + } else if (ic_task == IC_TASK_POST_PROCESSOR) { + if (csc_index == 1) + base = ipu_tpmem_base + 0x6060 / 4; + else + base = ipu_tpmem_base + 0x6078 / 4; + } else { + BUG(); + } + + if ((in_format == YCbCr) && (out_format == RGB)) { + /* Init CSC (YCbCr->RGB) */ + param = (ycbcr2rgb_coeff[3][0] << 27) | + (ycbcr2rgb_coeff[0][0] << 18) | + (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2]; + __raw_writel(param, base++); + /* scale = 2, sat = 0 */ + param = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32)); + __raw_writel(param, base++); + + param = (ycbcr2rgb_coeff[3][1] << 27) | + (ycbcr2rgb_coeff[0][1] << 18) | + (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0]; + __raw_writel(param, base++); + param = (ycbcr2rgb_coeff[3][1] >> 5); + __raw_writel(param, base++); + + param = (ycbcr2rgb_coeff[3][2] << 27) | + (ycbcr2rgb_coeff[0][2] << 18) | + (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1]; + __raw_writel(param, base++); + param = (ycbcr2rgb_coeff[3][2] >> 5); + __raw_writel(param, base++); + } else if ((in_format == RGB) && (out_format == YCbCr)) { + /* Init CSC (RGB->YCbCr) */ + param = (rgb2ycbcr_coeff[3][0] << 27) | + (rgb2ycbcr_coeff[0][0] << 18) | + (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2]; + __raw_writel(param, base++); + /* scale = 1, sat = 0 */ + param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8); + __raw_writel(param, base++); + + param = (rgb2ycbcr_coeff[3][1] << 27) | + (rgb2ycbcr_coeff[0][1] << 18) | + (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0]; + __raw_writel(param, base++); + param = (rgb2ycbcr_coeff[3][1] >> 5); + __raw_writel(param, base++); + + param = (rgb2ycbcr_coeff[3][2] << 27) | + (rgb2ycbcr_coeff[0][2] << 18) | + (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1]; + __raw_writel(param, base++); + param = (rgb2ycbcr_coeff[3][2] >> 5); + __raw_writel(param, base++); + } else if ((in_format == RGB) && (out_format == RGB)) { + /* Init CSC */ + param = + (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) | + (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2]; + __raw_writel(param, base++); + /* scale = 2, sat = 0 */ + param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8); + __raw_writel(param, base++); + + param = + (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) | + (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0]; + __raw_writel(param, base++); + param = (rgb2rgb_coeff[3][1] >> 5); + __raw_writel(param, base++); + + param = + (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) | + (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1]; + __raw_writel(param, base++); + param = (rgb2rgb_coeff[3][2] >> 5); + __raw_writel(param, base++); + } else { + dev_err(g_ipu_dev, "Unsupported color space conversion\n"); + } +} + +static bool _calc_resize_coeffs(uint32_t inSize, uint32_t outSize, + uint32_t *resizeCoeff, + uint32_t *downsizeCoeff) +{ + uint32_t tempSize; + uint32_t tempDownsize; + + /* Input size cannot be more than 4096 */ + /* Output size cannot be more than 1024 */ + if ((inSize > 4096) || (outSize > 1024)) + return false; + + /* Cannot downsize more than 8:1 */ + if ((outSize << 3) < inSize) + return false; + + /* Compute downsizing coefficient */ + /* Output of downsizing unit cannot be more than 1024 */ + tempDownsize = 0; + tempSize = inSize; + while (((tempSize > 1024) || (tempSize >= outSize * 2)) && + (tempDownsize < 2)) { + tempSize >>= 1; + tempDownsize++; + } + *downsizeCoeff = tempDownsize; + + /* compute resizing coefficient using the following equation: + resizeCoeff = M*(SI -1)/(SO - 1) + where M = 2^13, SI - input size, SO - output size */ + *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1); + if (*resizeCoeff >= 16384L) { + dev_err(g_ipu_dev, "Warning! Overflow on resize coeff.\n"); + *resizeCoeff = 0x3FFF; + } + + dev_dbg(g_ipu_dev, "resizing from %u -> %u pixels, " + "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize, + *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0, + ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff); + + return true; +} + +void _ipu_vdi_toggle_top_field_man() +{ + uint32_t reg; + uint32_t mask_reg; + + reg = __raw_readl(VDI_C); + mask_reg = reg & VDI_C_TOP_FIELD_MAN_1; + if (mask_reg == VDI_C_TOP_FIELD_MAN_1) + reg &= ~VDI_C_TOP_FIELD_MAN_1; + else + reg |= VDI_C_TOP_FIELD_MAN_1; + + __raw_writel(reg, VDI_C); +} + diff --git a/drivers/mxc/ipu3/ipu_param_mem.h b/drivers/mxc/ipu3/ipu_param_mem.h new file mode 100644 index 000000000000..81b001ed947b --- /dev/null +++ b/drivers/mxc/ipu3/ipu_param_mem.h @@ -0,0 +1,570 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_IPU_PARAM_MEM_H__ +#define __INCLUDE_IPU_PARAM_MEM_H__ + +#include +#include + +extern u32 *ipu_cpmem_base; + +struct ipu_ch_param_word { + uint32_t data[5]; + uint32_t res[3]; +}; + +struct ipu_ch_param { + struct ipu_ch_param_word word[2]; +}; + +#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch)) + +#define _param_word(base, w) \ + (((struct ipu_ch_param *)(base))->word[(w)].data) + +#define ipu_ch_param_set_field(base, w, bit, size, v) { \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + _param_word(base, w)[i] |= (v) << off; \ + if (((bit)+(size)-1)/32 > i) { \ + _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \ + } \ +} + +#define ipu_ch_param_mod_field(base, w, bit, size, v) { \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + u32 mask = (1UL << size) - 1; \ + u32 temp = _param_word(base, w)[i]; \ + temp &= ~(mask << off); \ + _param_word(base, w)[i] = temp | (v) << off; \ + if (((bit)+(size)-1)/32 > i) { \ + temp = _param_word(base, w)[i + 1]; \ + temp &= ~(mask >> (32 - off)); \ + _param_word(base, w)[i + 1] = \ + temp | ((v) >> (off ? (32 - off) : 0)); \ + } \ +} + +#define ipu_ch_param_read_field(base, w, bit, size) ({ \ + u32 temp2; \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + u32 mask = (1UL << size) - 1; \ + u32 temp1 = _param_word(base, w)[i]; \ + temp1 = mask & (temp1 >> off); \ + if (((bit)+(size)-1)/32 > i) { \ + temp2 = _param_word(base, w)[i + 1]; \ + temp2 &= mask >> (off ? (32 - off) : 0); \ + temp1 |= temp2 << (off ? (32 - off) : 0); \ + } \ + temp1; \ +}) + +static inline void _ipu_ch_params_set_packing(struct ipu_ch_param *p, + int red_width, int red_offset, + int green_width, int green_offset, + int blue_width, int blue_offset, + int alpha_width, int alpha_offset) +{ + /* Setup red width and offset */ + ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1); + ipu_ch_param_set_field(p, 1, 128, 5, red_offset); + /* Setup green width and offset */ + ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1); + ipu_ch_param_set_field(p, 1, 133, 5, green_offset); + /* Setup blue width and offset */ + ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1); + ipu_ch_param_set_field(p, 1, 138, 5, blue_offset); + /* Setup alpha width and offset */ + ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1); + ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset); +} + +static inline void _ipu_ch_param_dump(int ch) +{ + struct ipu_ch_param *p = ipu_ch_param_addr(ch); + pr_debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch, + p->word[0].data[0], p->word[0].data[1], p->word[0].data[2], + p->word[0].data[3], p->word[0].data[4]); + pr_debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch, + p->word[1].data[0], p->word[1].data[1], p->word[1].data[2], + p->word[1].data[3], p->word[1].data[4]); + pr_debug("PFS 0x%x, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4)); + pr_debug("BPP 0x%x, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3)); + pr_debug("NPB 0x%x\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7)); + + pr_debug("FW %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13)); + pr_debug("FH %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12)); + pr_debug("Stride %d\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14)); + + pr_debug("Width0 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3)); + pr_debug("Width1 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3)); + pr_debug("Width2 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3)); + pr_debug("Width3 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3)); + pr_debug("Offset0 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5)); + pr_debug("Offset1 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5)); + pr_debug("Offset2 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5)); + pr_debug("Offset3 %d\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5)); +} + +static inline void _ipu_ch_param_init(int ch, + uint32_t pixel_fmt, uint32_t width, + uint32_t height, uint32_t stride, + uint32_t u, uint32_t v, + uint32_t uv_stride, dma_addr_t addr0, + dma_addr_t addr1) +{ + uint32_t u_offset = 0; + uint32_t v_offset = 0; + struct ipu_ch_param params; + + memset(¶ms, 0, sizeof(params)); + + ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1); + + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1); + ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1); + } else { + ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1); + ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1); + } + + /* EBA is 8-byte aligned */ + ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3); + ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3); + if (addr0%8) + dev_warn(g_ipu_dev, + "IDMAC%d's EBA0 is not 8-byte aligned\n", ch); + if (addr1%8) + dev_warn(g_ipu_dev, + "IDMAC%d's EBA1 is not 8-byte aligned\n", ch); + + switch (pixel_fmt) { + case IPU_PIX_FMT_GENERIC: + /*Represents 8-bit Generic data */ + ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */ + + break; + case IPU_PIX_FMT_GENERIC_32: + /*Represents 32-bit Generic data */ + break; + case IPU_PIX_FMT_RGB565: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16); + break; + case IPU_PIX_FMT_BGR24: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); + break; + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_YUV444: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24); + break; + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_BGR32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0); + break; + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_RGB32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0); + break; + case IPU_PIX_FMT_ABGR32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + _ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); + break; + case IPU_PIX_FMT_UYVY: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */ + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + } else { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + } + break; + case IPU_PIX_FMT_YUYV: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */ + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + } else { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + } + break; + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = stride * height; + v_offset = u_offset + (uv_stride * height / 2); + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + uv_stride = uv_stride*2; + } else { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + } + break; + case IPU_PIX_FMT_YVU422P: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + v_offset = (v == 0) ? stride * height : v; + u_offset = (u == 0) ? v_offset + v_offset / 2 : u; + break; + case IPU_PIX_FMT_YUV422P: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = (u == 0) ? stride * height : u; + v_offset = (v == 0) ? u_offset + u_offset / 2 : v; + break; + case IPU_PIX_FMT_NV12: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */ + uv_stride = stride; + u_offset = (u == 0) ? stride * height : u; + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + uv_stride = uv_stride*2; + } else { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + } + break; + default: + dev_err(g_ipu_dev, "mxc ipu: unimplemented pixel format\n"); + break; + } + /*set burst size to 16*/ + + + if (uv_stride) + ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1); + + /* Get the uv offset from user when need cropping */ + if (u || v) { + u_offset = u; + v_offset = v; + } + + /* UBO and VBO are 22-bit and 8-byte aligned */ + if (u_offset/8 > 0x3fffff) + dev_warn(g_ipu_dev, + "IDMAC%d's U offset exceeds IPU limitation\n", ch); + if (v_offset/8 > 0x3fffff) + dev_warn(g_ipu_dev, + "IDMAC%d's V offset exceeds IPU limitation\n", ch); + if (u_offset%8) + dev_warn(g_ipu_dev, + "IDMAC%d's U offset is not 8-byte aligned\n", ch); + if (v_offset%8) + dev_warn(g_ipu_dev, + "IDMAC%d's V offset is not 8-byte aligned\n", ch); + + ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8); + ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8); + + pr_debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch)); + memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params)); +}; + +static inline void _ipu_ch_param_set_burst_size(uint32_t ch, + uint16_t burst_pixels) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 78, 7, + burst_pixels - 1); +}; + +static inline int _ipu_ch_param_get_burst_size(uint32_t ch) +{ + return ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7) + 1; +}; + +static inline int _ipu_ch_param_get_bpp(uint32_t ch) +{ + return ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3); +}; + +static inline void _ipu_ch_param_set_buffer(uint32_t ch, int bufNum, + dma_addr_t phyaddr) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29, + phyaddr / 8); +}; + +static inline void _ipu_ch_param_set_rotation(uint32_t ch, + ipu_rotate_mode_t rot) +{ + u32 temp_rot = bitrev8(rot) >> 5; + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 119, 3, temp_rot); +}; + +static inline void _ipu_ch_param_set_block_mode(uint32_t ch) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 117, 2, 1); +}; + +static inline void _ipu_ch_param_set_alpha_use_separate_channel(uint32_t ch, + bool option) +{ + if (option) { + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 89, 1, 1); + } else { + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 89, 1, 0); + } +}; + +static inline void _ipu_ch_param_set_alpha_condition_read(uint32_t ch) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 149, 1, 1); +}; + +static inline void _ipu_ch_param_set_alpha_buffer_memory(uint32_t ch) +{ + int alp_mem_idx; + + switch (ch) { + case 14: /* PRP graphic */ + alp_mem_idx = 0; + break; + case 15: /* PP graphic */ + alp_mem_idx = 1; + break; + case 23: /* DP BG SYNC graphic */ + alp_mem_idx = 4; + break; + case 27: /* DP FG SYNC graphic */ + alp_mem_idx = 2; + break; + default: + dev_err(g_ipu_dev, "unsupported correlative channel of local " + "alpha channel\n"); + return; + } + + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 90, 3, alp_mem_idx); +}; + +static inline void _ipu_ch_param_set_interlaced_scan(uint32_t ch) +{ + u32 stride; + ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 113, 1, 1); + stride = ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14) + 1; + /* ILO is 20-bit and 8-byte aligned */ + if (stride/8 > 0xfffff) + dev_warn(g_ipu_dev, + "IDMAC%d's ILO exceeds IPU limitation\n", ch); + if (stride%8) + dev_warn(g_ipu_dev, + "IDMAC%d's ILO is not 8-byte aligned\n", ch); + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 58, 20, stride / 8); + stride *= 2; + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1); +}; + +static inline void _ipu_ch_param_set_high_priority(uint32_t ch) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1); +}; + +/* IDMAC U/V offset changing support */ +/* U and V input is not affected, */ +/* the update is done by new calculation according to */ +/* vertical_offset and horizontal_offset */ +static inline void _ipu_ch_offset_update(int ch, + uint32_t pixel_fmt, + uint32_t width, + uint32_t height, + uint32_t stride, + uint32_t u, + uint32_t v, + uint32_t uv_stride, + uint32_t vertical_offset, + uint32_t horizontal_offset) +{ + uint32_t u_offset = 0; + uint32_t v_offset = 0; + uint32_t u_fix = 0; + uint32_t v_fix = 0; + + switch (pixel_fmt) { + case IPU_PIX_FMT_GENERIC: + case IPU_PIX_FMT_GENERIC_32: + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_YUV444: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_ABGR32: + case IPU_PIX_FMT_UYVY: + case IPU_PIX_FMT_YUYV: + break; + + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = stride * (height - vertical_offset - 1) + + (stride - horizontal_offset) + + (uv_stride * vertical_offset / 2) + + horizontal_offset / 2; + v_offset = u_offset + (uv_stride * height / 2); + u_fix = u ? (u + (uv_stride * vertical_offset / 2) + + (horizontal_offset / 2) - + (stride * vertical_offset) - (horizontal_offset)) : + u_offset; + v_fix = v ? (v + (uv_stride * vertical_offset / 2) + + (horizontal_offset / 2) - + (stride * vertical_offset) - (horizontal_offset)) : + v_offset; + + break; + case IPU_PIX_FMT_YVU422P: + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + v_offset = stride * (height - vertical_offset - 1) + + (stride - horizontal_offset) + + (uv_stride * vertical_offset) + + horizontal_offset / 2; + u_offset = v_offset + uv_stride * height; + u_fix = u ? (u + (uv_stride * vertical_offset) + + horizontal_offset / 2 - + (stride * vertical_offset) - (horizontal_offset)) : + u_offset; + v_fix = v ? (v + (uv_stride * vertical_offset) + + horizontal_offset / 2 - + (stride * vertical_offset) - (horizontal_offset)) : + v_offset; + break; + case IPU_PIX_FMT_YUV422P: + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = stride * (height - vertical_offset - 1) + + (stride - horizontal_offset) + + (uv_stride * vertical_offset) + + horizontal_offset / 2; + v_offset = u_offset + uv_stride * height; + u_fix = u ? (u + (uv_stride * vertical_offset) + + horizontal_offset / 2 - + (stride * vertical_offset) - (horizontal_offset)) : + u_offset; + v_fix = v ? (v + (uv_stride * vertical_offset) + + horizontal_offset / 2 - + (stride * vertical_offset) - (horizontal_offset)) : + v_offset; + break; + + case IPU_PIX_FMT_NV12: + uv_stride = stride; + u_offset = stride * (height - vertical_offset - 1) + + (stride - horizontal_offset) + + (uv_stride * vertical_offset / 2) + + horizontal_offset; + u_fix = u ? (u + (uv_stride * vertical_offset / 2) + + horizontal_offset - + (stride * vertical_offset) - (horizontal_offset)) : + u_offset; + + break; + default: + dev_err(g_ipu_dev, "mxc ipu: unimplemented pixel format\n"); + break; + } + + + + if (u_fix > u_offset) + u_offset = u_fix; + + if (v_fix > v_offset) + v_offset = v_fix; + + /* UBO and VBO are 22-bit and 8-byte aligned */ + if (u_offset/8 > 0x3fffff) + dev_warn(g_ipu_dev, + "IDMAC%d's U offset exceeds IPU limitation\n", ch); + if (v_offset/8 > 0x3fffff) + dev_warn(g_ipu_dev, + "IDMAC%d's V offset exceeds IPU limitation\n", ch); + if (u_offset%8) + dev_warn(g_ipu_dev, + "IDMAC%d's U offset is not 8-byte aligned\n", ch); + if (v_offset%8) + dev_warn(g_ipu_dev, + "IDMAC%d's V offset is not 8-byte aligned\n", ch); + + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8); + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8); + +}; + +static inline void _ipu_ch_params_set_alpha_width(uint32_t ch, int alpha_width) +{ + ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 125, 3, alpha_width - 1); +}; + +#endif diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h new file mode 100644 index 000000000000..d9c429652012 --- /dev/null +++ b/drivers/mxc/ipu3/ipu_prv.h @@ -0,0 +1,102 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __INCLUDE_IPU_PRV_H__ +#define __INCLUDE_IPU_PRV_H__ + +#include +#include +#include +#include +#include + +/* Globals */ +extern struct device *g_ipu_dev; +extern spinlock_t ipu_lock; +extern bool g_ipu_clk_enabled; +extern struct clk *g_ipu_clk; +extern struct clk *g_di_clk[2]; +extern struct clk *g_pixel_clk[2]; +extern struct clk *g_csi_clk[2]; +extern unsigned char g_dc_di_assignment[]; +extern int g_ipu_hw_rev; +extern int dmfc_type_setup; + +#define IDMA_CHAN_INVALID 0xFF +#define HIGH_RESOLUTION_WIDTH 1024 + +struct ipu_channel { + u8 video_in_dma; + u8 alpha_in_dma; + u8 graph_in_dma; + u8 out_dma; +}; + +enum ipu_dmfc_type { + DMFC_NORMAL = 0, + DMFC_HIGH_RESOLUTION_DC, + DMFC_HIGH_RESOLUTION_DP, + DMFC_HIGH_RESOLUTION_ONLY_DP, +}; + +int register_ipu_device(void); +ipu_color_space_t format_to_colorspace(uint32_t fmt); +bool ipu_pixel_format_has_alpha(uint32_t fmt); + +void ipu_dump_registers(void); + +uint32_t _ipu_channel_status(ipu_channel_t channel); + +void _ipu_init_dc_mappings(void); +int _ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, + uint32_t out_pixel_fmt); +void _ipu_dp_uninit(ipu_channel_t channel); +void _ipu_dc_init(int dc_chan, int di, bool interlaced, uint32_t pixel_fmt); +void _ipu_dc_uninit(int dc_chan); +void _ipu_dp_dc_enable(ipu_channel_t channel); +void _ipu_dp_dc_disable(ipu_channel_t channel, bool swap); +void _ipu_dmfc_init(int dmfc_type, int first); +void _ipu_dmfc_set_wait4eot(int dma_chan, int width); +int _ipu_disp_chan_is_interlaced(ipu_channel_t channel); + +void _ipu_ic_enable_task(ipu_channel_t channel); +void _ipu_ic_disable_task(ipu_channel_t channel); +void _ipu_ic_init_prpvf(ipu_channel_params_t *params, bool src_is_csi); +void _ipu_vdi_init(ipu_channel_t channel, ipu_channel_params_t *params); +void _ipu_vdi_uninit(void); +void _ipu_ic_uninit_prpvf(void); +void _ipu_ic_init_rotate_vf(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_vf(void); +void _ipu_ic_init_csi(ipu_channel_params_t *params); +void _ipu_ic_uninit_csi(void); +void _ipu_ic_init_prpenc(ipu_channel_params_t *params, bool src_is_csi); +void _ipu_ic_uninit_prpenc(void); +void _ipu_ic_init_rotate_enc(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_enc(void); +void _ipu_ic_init_pp(ipu_channel_params_t *params); +void _ipu_ic_uninit_pp(void); +void _ipu_ic_init_rotate_pp(ipu_channel_params_t *params); +void _ipu_ic_uninit_rotate_pp(void); +int _ipu_ic_idma_init(int dma_chan, uint16_t width, uint16_t height, + int burst_size, ipu_rotate_mode_t rot); +void _ipu_vdi_toggle_top_field_man(void); +int _ipu_csi_init(ipu_channel_t channel, uint32_t csi); +void ipu_csi_set_test_generator(bool active, uint32_t r_value, + uint32_t g_value, uint32_t b_value, + uint32_t pix_clk, uint32_t csi); +void _ipu_csi_ccir_err_detection_enable(uint32_t csi); +void _ipu_csi_ccir_err_detection_disable(uint32_t csi); +void _ipu_smfc_init(ipu_channel_t channel, uint32_t mipi_id, uint32_t csi); +void _ipu_smfc_set_burst_size(ipu_channel_t channel, uint32_t bs); +void _ipu_dp_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]); + +#endif /* __INCLUDE_IPU_PRV_H__ */ diff --git a/drivers/mxc/ipu3/ipu_regs.h b/drivers/mxc/ipu3/ipu_regs.h new file mode 100644 index 000000000000..002bb96b9f66 --- /dev/null +++ b/drivers/mxc/ipu3/ipu_regs.h @@ -0,0 +1,669 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * @file ipu_regs.h + * + * @brief IPU Register definitions + * + * @ingroup IPU + */ +#ifndef __IPU_REGS_INCLUDED__ +#define __IPU_REGS_INCLUDED__ + +#define IPU_DISP0_BASE 0x00000000 +#define IPU_MCU_T_DEFAULT 8 +#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) +#define IPU_REG_BASE 0x1E000000 +#define IPUV3M_REG_BASE 0x06000000 + +#define IPU_CM_REG_BASE 0x00000000 +#define IPU_IDMAC_REG_BASE 0x00008000 +#define IPU_ISP_REG_BASE 0x00010000 +#define IPU_DP_REG_BASE 0x00018000 +#define IPU_IC_REG_BASE 0x00020000 +#define IPU_IRT_REG_BASE 0x00028000 +#define IPU_CSI0_REG_BASE 0x00030000 +#define IPU_CSI1_REG_BASE 0x00038000 +#define IPU_DI0_REG_BASE 0x00040000 +#define IPU_DI1_REG_BASE 0x00048000 +#define IPU_SMFC_REG_BASE 0x00050000 +#define IPU_DC_REG_BASE 0x00058000 +#define IPU_DMFC_REG_BASE 0x00060000 +#define IPU_VDI_REG_BASE 0x00068000 +#define IPU_CPMEM_REG_BASE 0x01000000 +#define IPU_LUT_REG_BASE 0x01020000 +#define IPU_SRM_REG_BASE 0x01040000 +#define IPU_TPM_REG_BASE 0x01060000 +#define IPU_DC_TMPL_REG_BASE 0x01080000 +#define IPU_ISP_TBPR_REG_BASE 0x010C0000 + + +extern u32 *ipu_cm_reg; +extern u32 *ipu_idmac_reg; +extern u32 *ipu_dp_reg; +extern u32 *ipu_ic_reg; +extern u32 *ipu_dc_reg; +extern u32 *ipu_dc_tmpl_reg; +extern u32 *ipu_dmfc_reg; +extern u32 *ipu_di_reg[]; +extern u32 *ipu_smfc_reg; +extern u32 *ipu_csi_reg[]; +extern u32 *ipu_tpmem_base; +extern u32 *ipu_disp_base[]; +extern u32 *ipu_vdi_reg; + +/* Register addresses */ +/* IPU Common registers */ +#define IPU_CONF (ipu_cm_reg) + +#define IPU_SRM_PRI1 (ipu_cm_reg + 0x00A0/4) +#define IPU_SRM_PRI2 (ipu_cm_reg + 0x00A4/4) +#define IPU_FS_PROC_FLOW1 (ipu_cm_reg + 0x00A8/4) +#define IPU_FS_PROC_FLOW2 (ipu_cm_reg + 0x00AC/4) +#define IPU_FS_PROC_FLOW3 (ipu_cm_reg + 0x00B0/4) +#define IPU_FS_DISP_FLOW1 (ipu_cm_reg + 0x00B4/4) +#define IPU_FS_DISP_FLOW2 (ipu_cm_reg + 0x00B8/4) +#define IPU_SKIP (ipu_cm_reg + 0x00BC/4) +#define IPU_DISP_ALT_CONF (ipu_cm_reg + 0x00C0/4) +#define IPU_DISP_GEN (ipu_cm_reg + 0x00C4/4) +#define IPU_DISP_ALT1 (ipu_cm_reg + 0x00C8/4) +#define IPU_DISP_ALT2 (ipu_cm_reg + 0x00CC/4) +#define IPU_DISP_ALT3 (ipu_cm_reg + 0x00D0/4) +#define IPU_DISP_ALT4 (ipu_cm_reg + 0x00D4/4) +#define IPU_SNOOP (ipu_cm_reg + 0x00D8/4) +#define IPU_MEM_RST (ipu_cm_reg + 0x00DC/4) +#define IPU_PM (ipu_cm_reg + 0x00E0/4) +#define IPU_GPR (ipu_cm_reg + 0x00E4/4) +#define IPU_CHA_DB_MODE_SEL(ch) (ipu_cm_reg + 0x0150/4 + (ch / 32)) +#define IPU_ALT_CHA_DB_MODE_SEL(ch) (ipu_cm_reg + 0x0168/4 + (ch / 32)) +#define IPU_CHA_CUR_BUF(ch) ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x023C/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0124/4 + (ch / 32)); }) +#define IPU_ALT_CUR_BUF0 ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0244/4) : \ + (ipu_cm_reg + 0x012C/4); }) +#define IPU_ALT_CUR_BUF1 ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0248/4) : \ + (ipu_cm_reg + 0x0130/4); }) +#define IPU_SRM_STAT ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x024C/4) : \ + (ipu_cm_reg + 0x0134/4); }) +#define IPU_PROC_TASK_STAT ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0250/4) : \ + (ipu_cm_reg + 0x0138/4); }) +#define IPU_DISP_TASK_STAT ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0254/4) : \ + (ipu_cm_reg + 0x013C/4); }) +#define IPU_CHA_BUF0_RDY(ch) ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0268/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0140/4 + (ch / 32)); }) +#define IPU_CHA_BUF1_RDY(ch) ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0270/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0148/4 + (ch / 32)); }) +#define IPU_ALT_CHA_BUF0_RDY(ch) ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0278/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0158/4 + (ch / 32)); }) +#define IPU_ALT_CHA_BUF1_RDY(ch) ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0280/4 + (ch / 32)) : \ + (ipu_cm_reg + 0x0160/4 + (ch / 32)); }) + +#define IPU_INT_CTRL(n) (ipu_cm_reg + 0x003C/4 + ((n) - 1)) +#define IPU_INT_CTRL_IRQ(irq) IPU_INT_CTRL(((irq) / 32)) +#define IPU_INT_STAT_IRQ(irq) IPU_INT_STAT(((irq) / 32)) +#define IPU_INT_STAT(n) ({g_ipu_hw_rev >= 2 ? \ + (ipu_cm_reg + 0x0200/4 + ((n) - 1)) : \ + (ipu_cm_reg + 0x00E8/4 + ((n) - 1)); }) + +#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32)) +#define IPUIRQ_2_CTRLREG(irq) (IPU_INT_CTRL(1) + ((irq) / 32)) +#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F)) + +#define VDI_FSIZE (ipu_vdi_reg) +#define VDI_C (ipu_vdi_reg + 0x0004/4) + +/* CMOS Sensor Interface Registers */ +#define CSI_SENS_CONF(csi) (ipu_csi_reg[csi]) +#define CSI_SENS_FRM_SIZE(csi) (ipu_csi_reg[csi] + 0x0004/4) +#define CSI_ACT_FRM_SIZE(csi) (ipu_csi_reg[csi] + 0x0008/4) +#define CSI_OUT_FRM_CTRL(csi) (ipu_csi_reg[csi] + 0x000C/4) +#define CSI_TST_CTRL(csi) (ipu_csi_reg[csi] + 0x0010/4) +#define CSI_CCIR_CODE_1(csi) (ipu_csi_reg[csi] + 0x0014/4) +#define CSI_CCIR_CODE_2(csi) (ipu_csi_reg[csi] + 0x0018/4) +#define CSI_CCIR_CODE_3(csi) (ipu_csi_reg[csi] + 0x001C/4) +#define CSI_MIPI_DI(csi) (ipu_csi_reg[csi] + 0x0020/4) +#define CSI_SKIP(csi) (ipu_csi_reg[csi] + 0x0024/4) +#define CSI_CPD_CTRL(csi) (ipu_csi_reg[csi] + 0x0028/4) +#define CSI_CPD_RC(csi, n) (ipu_csi_reg[csi] + 0x002C/4 + n) +#define CSI_CPD_RS(csi, n) (ipu_csi_reg[csi] + 0x004C/4 + n) +#define CSI_CPD_GRC(csi, n) (ipu_csi_reg[csi] + 0x005C/4 + n) +#define CSI_CPD_GRS(csi, n) (ipu_csi_reg[csi] + 0x007C/4 + n) +#define CSI_CPD_GBC(csi, n) (ipu_csi_reg[csi] + 0x008C/4 + n) +#define CSI_CPD_GBS(csi, n) (ipu_csi_reg[csi] + 0x00AC/4 + n) +#define CSI_CPD_BC(csi, n) (ipu_csi_reg[csi] + 0x00BC/4 + n) +#define CSI_CPD_BS(csi, n) (ipu_csi_reg[csi] + 0x00DC/4 + n) +#define CSI_CPD_OFFSET1(csi) (ipu_csi_reg[csi] + 0x00EC/4) +#define CSI_CPD_OFFSET2(csi) (ipu_csi_reg[csi] + 0x00F0/4) + +/*SMFC Registers */ +#define SMFC_MAP (ipu_smfc_reg) +#define SMFC_WMC (ipu_smfc_reg + 0x0004/4) +#define SMFC_BS (ipu_smfc_reg + 0x0008/4) + +/* Image Converter Registers */ +#define IC_CONF (ipu_ic_reg) +#define IC_PRP_ENC_RSC (ipu_ic_reg + 0x0004/4) +#define IC_PRP_VF_RSC (ipu_ic_reg + 0x0008/4) +#define IC_PP_RSC (ipu_ic_reg + 0x000C/4) +#define IC_CMBP_1 (ipu_ic_reg + 0x0010/4) +#define IC_CMBP_2 (ipu_ic_reg + 0x0014/4) +#define IC_IDMAC_1 (ipu_ic_reg + 0x0018/4) +#define IC_IDMAC_2 (ipu_ic_reg + 0x001C/4) +#define IC_IDMAC_3 (ipu_ic_reg + 0x0020/4) +#define IC_IDMAC_4 (ipu_ic_reg + 0x0024/4) + +#define IDMAC_CONF (ipu_idmac_reg + 0x0000) +#define IDMAC_CHA_EN(ch) (ipu_idmac_reg + 0x0004/4 + (ch/32)) +#define IDMAC_SEP_ALPHA (ipu_idmac_reg + 0x000C/4) +#define IDMAC_ALT_SEP_ALPHA (ipu_idmac_reg + 0x0010/4) +#define IDMAC_CHA_PRI(ch) (ipu_idmac_reg + 0x0014/4 + (ch/32)) +#define IDMAC_WM_EN(ch) (ipu_idmac_reg + 0x001C/4 + (ch/32)) +#define IDMAC_CH_LOCK_EN_1 ({g_ipu_hw_rev >= 2 ? \ + (ipu_idmac_reg + 0x0024/4) : 0; }) +#define IDMAC_CH_LOCK_EN_2 ({g_ipu_hw_rev >= 2 ? \ + (ipu_idmac_reg + 0x0028/4) : \ + (ipu_idmac_reg + 0x0024/4); }) +#define IDMAC_SUB_ADDR_0 ({g_ipu_hw_rev >= 2 ? \ + (ipu_idmac_reg + 0x002C/4) : \ + (ipu_idmac_reg + 0x0028/4); }) +#define IDMAC_SUB_ADDR_1 ({g_ipu_hw_rev >= 2 ? \ + (ipu_idmac_reg + 0x0030/4) : \ + (ipu_idmac_reg + 0x002C/4); }) +#define IDMAC_SUB_ADDR_2 ({g_ipu_hw_rev >= 2 ? \ + (ipu_idmac_reg + 0x0034/4) : \ + (ipu_idmac_reg + 0x0030/4); }) +#define IDMAC_BAND_EN(ch) ({g_ipu_hw_rev >= 2 ? \ + (ipu_idmac_reg + 0x0040/4 + (ch/32)) : \ + (ipu_idmac_reg + 0x0034/4 + (ch/32)); }) +#define IDMAC_CHA_BUSY(ch) ({g_ipu_hw_rev >= 2 ? \ + (ipu_idmac_reg + 0x0100/4 + (ch/32)) : \ + (ipu_idmac_reg + 0x0040/4 + (ch/32)); }) + +#define DI_GENERAL(di) (ipu_di_reg[di]) +#define DI_BS_CLKGEN0(di) (ipu_di_reg[di] + 0x0004/4) +#define DI_BS_CLKGEN1(di) (ipu_di_reg[di] + 0x0008/4) + +#define DI_SW_GEN0(di, gen) (ipu_di_reg[di] + 0x000C/4 + (gen - 1)) +#define DI_SW_GEN1(di, gen) (ipu_di_reg[di] + 0x0030/4 + (gen - 1)) +#define DI_STP_REP(di, gen) (ipu_di_reg[di] + 0x0148/4 + (gen - 1)/2) +#define DI_SYNC_AS_GEN(di) (ipu_di_reg[di] + 0x0054/4) +#define DI_DW_GEN(di, gen) (ipu_di_reg[di] + 0x0058/4 + gen) +#define DI_DW_SET(di, gen, set) (ipu_di_reg[di] + 0x0088/4 + gen + 0xC*set) +#define DI_SER_CONF(di) (ipu_di_reg[di] + 0x015C/4) +#define DI_SSC(di) (ipu_di_reg[di] + 0x0160/4) +#define DI_POL(di) (ipu_di_reg[di] + 0x0164/4) +#define DI_AW0(di) (ipu_di_reg[di] + 0x0168/4) +#define DI_AW1(di) (ipu_di_reg[di] + 0x016C/4) +#define DI_SCR_CONF(di) (ipu_di_reg[di] + 0x0170/4) +#define DI_STAT(di) (ipu_di_reg[di] + 0x0174/4) + +#define DMFC_RD_CHAN (ipu_dmfc_reg) +#define DMFC_WR_CHAN (ipu_dmfc_reg + 0x0004/4) +#define DMFC_WR_CHAN_DEF (ipu_dmfc_reg + 0x0008/4) +#define DMFC_DP_CHAN (ipu_dmfc_reg + 0x000C/4) +#define DMFC_DP_CHAN_DEF (ipu_dmfc_reg + 0x0010/4) +#define DMFC_GENERAL1 (ipu_dmfc_reg + 0x0014/4) +#define DMFC_GENERAL2 (ipu_dmfc_reg + 0x0018/4) +#define DMFC_IC_CTRL (ipu_dmfc_reg + 0x001C/4) +#define DMFC_STAT (ipu_dmfc_reg + 0x0020/4) + +#define DC_MAP_CONF_PTR(n) (ipu_dc_reg + 0x0108/4 + n/2) +#define DC_MAP_CONF_VAL(n) (ipu_dc_reg + 0x0144/4 + n/2) + +#define _RL_CH_2_OFFSET(ch) ((ch == 0) ? 8 : ( \ + (ch == 1) ? 0x24 : ( \ + (ch == 2) ? 0x40 : ( \ + (ch == 5) ? 0x64 : ( \ + (ch == 6) ? 0x80 : ( \ + (ch == 8) ? 0x9C : ( \ + (ch == 9) ? 0xBC : (-1)))))))) +#define DC_RL_CH(ch, evt) (ipu_dc_reg + _RL_CH_2_OFFSET(ch)/4 + evt/2) + +#define DC_EVT_NF 0 +#define DC_EVT_NL 1 +#define DC_EVT_EOF 2 +#define DC_EVT_NFIELD 3 +#define DC_EVT_EOL 4 +#define DC_EVT_EOFIELD 5 +#define DC_EVT_NEW_ADDR 6 +#define DC_EVT_NEW_CHAN 7 +#define DC_EVT_NEW_DATA 8 + +#define DC_EVT_NEW_ADDR_W_0 0 +#define DC_EVT_NEW_ADDR_W_1 1 +#define DC_EVT_NEW_CHAN_W_0 2 +#define DC_EVT_NEW_CHAN_W_1 3 +#define DC_EVT_NEW_DATA_W_0 4 +#define DC_EVT_NEW_DATA_W_1 5 +#define DC_EVT_NEW_ADDR_R_0 6 +#define DC_EVT_NEW_ADDR_R_1 7 +#define DC_EVT_NEW_CHAN_R_0 8 +#define DC_EVT_NEW_CHAN_R_1 9 +#define DC_EVT_NEW_DATA_R_0 10 +#define DC_EVT_NEW_DATA_R_1 11 +#define DC_EVEN_UGDE0 12 +#define DC_ODD_UGDE0 13 +#define DC_EVEN_UGDE1 14 +#define DC_ODD_UGDE1 15 +#define DC_EVEN_UGDE2 16 +#define DC_ODD_UGDE2 17 +#define DC_EVEN_UGDE3 18 +#define DC_ODD_UGDE3 19 + +#define dc_ch_offset(ch) \ +({ \ + const u8 _offset[] = { \ + 0, 0x1C, 0x38, 0x54, 0x58, 0x5C, 0x78, 0, 0x94, 0xB4}; \ + _offset[ch]; \ +}) +#define DC_WR_CH_CONF(ch) (ipu_dc_reg + dc_ch_offset(ch)/4) +#define DC_WR_CH_ADDR(ch) (ipu_dc_reg + dc_ch_offset(ch)/4 + 4/4) + +#define DC_WR_CH_CONF_1 (ipu_dc_reg + 0x001C/4) +#define DC_WR_CH_ADDR_1 (ipu_dc_reg + 0x0020/4) +#define DC_WR_CH_CONF_5 (ipu_dc_reg + 0x005C/4) +#define DC_WR_CH_ADDR_5 (ipu_dc_reg + 0x0060/4) +#define DC_GEN (ipu_dc_reg + 0x00D4/4) +#define DC_DISP_CONF1(disp) (ipu_dc_reg + 0x00D8/4 + disp) +#define DC_DISP_CONF2(disp) (ipu_dc_reg + 0x00E8/4 + disp) +#define DC_STAT (ipu_dc_reg + 0x01C8/4) +#define DC_UGDE_0(evt) (ipu_dc_reg + 0x0174/4 + evt*4) +#define DC_UGDE_1(evt) (ipu_dc_reg + 0x0178/4 + evt*4) +#define DC_UGDE_2(evt) (ipu_dc_reg + 0x017C/4 + evt*4) +#define DC_UGDE_3(evt) (ipu_dc_reg + 0x0180/4 + evt*4) + +#define DP_SYNC 0 +#define DP_ASYNC0 0x60 +#define DP_ASYNC1 0xBC +#define DP_COM_CONF(flow) (ipu_dp_reg + flow/4) +#define DP_GRAPH_WIND_CTRL(flow) (ipu_dp_reg + 0x0004/4 + flow/4) +#define DP_FG_POS(flow) (ipu_dp_reg + 0x0008/4 + flow/4) +#define DP_GAMMA_C(flow, i) (ipu_dp_reg + 0x0014/4 + flow/4 + i) +#define DP_GAMMA_S(flow, i) (ipu_dp_reg + 0x0034/4 + flow/4 + i) +#define DP_CSC_A_0(flow) (ipu_dp_reg + 0x0044/4 + flow/4) +#define DP_CSC_A_1(flow) (ipu_dp_reg + 0x0048/4 + flow/4) +#define DP_CSC_A_2(flow) (ipu_dp_reg + 0x004C/4 + flow/4) +#define DP_CSC_A_3(flow) (ipu_dp_reg + 0x0050/4 + flow/4) +#define DP_CSC_0(flow) (ipu_dp_reg + 0x0054/4 + flow/4) +#define DP_CSC_1(flow) (ipu_dp_reg + 0x0058/4 + flow/4) + +enum { + IPU_CONF_CSI0_EN = 0x00000001, + IPU_CONF_CSI1_EN = 0x00000002, + IPU_CONF_IC_EN = 0x00000004, + IPU_CONF_ROT_EN = 0x00000008, + IPU_CONF_ISP_EN = 0x00000010, + IPU_CONF_DP_EN = 0x00000020, + IPU_CONF_DI0_EN = 0x00000040, + IPU_CONF_DI1_EN = 0x00000080, + IPU_CONF_DMFC_EN = 0x00000400, + IPU_CONF_SMFC_EN = 0x00000100, + IPU_CONF_DC_EN = 0x00000200, + IPU_CONF_VDI_EN = 0x00001000, + IPU_CONF_IDMAC_DIS = 0x00400000, + IPU_CONF_IC_DMFC_SEL = 0x02000000, + IPU_CONF_IC_DMFC_SYNC = 0x04000000, + IPU_CONF_VDI_DMFC_SYNC = 0x08000000, + IPU_CONF_CSI0_DATA_SOURCE = 0x10000000, + IPU_CONF_CSI0_DATA_SOURCE_OFFSET = 28, + IPU_CONF_CSI1_DATA_SOURCE = 0x20000000, + IPU_CONF_IC_INPUT = 0x40000000, + IPU_CONF_CSI_SEL = 0x80000000, + + DI0_COUNTER_RELEASE = 0x01000000, + DI1_COUNTER_RELEASE = 0x02000000, + + FS_PRPVF_ROT_SRC_SEL_MASK = 0x00000F00, + FS_PRPVF_ROT_SRC_SEL_OFFSET = 8, + FS_PRPENC_ROT_SRC_SEL_MASK = 0x0000000F, + FS_PRPENC_ROT_SRC_SEL_OFFSET = 0, + FS_PP_ROT_SRC_SEL_MASK = 0x000F0000, + FS_PP_ROT_SRC_SEL_OFFSET = 16, + FS_PP_SRC_SEL_MASK = 0x0000F000, + FS_PP_SRC_SEL_OFFSET = 12, + FS_PRP_SRC_SEL_MASK = 0x0F000000, + FS_PRP_SRC_SEL_OFFSET = 24, + FS_VF_IN_VALID = 0x80000000, + FS_ENC_IN_VALID = 0x40000000, + FS_VDI_SRC_SEL_MASK = 0x30000000, + FS_VDI_SRC_SEL_OFFSET = 28, + + + FS_PRPENC_DEST_SEL_MASK = 0x0000000F, + FS_PRPENC_DEST_SEL_OFFSET = 0, + FS_PRPVF_DEST_SEL_MASK = 0x000000F0, + FS_PRPVF_DEST_SEL_OFFSET = 4, + FS_PRPVF_ROT_DEST_SEL_MASK = 0x00000F00, + FS_PRPVF_ROT_DEST_SEL_OFFSET = 8, + FS_PP_DEST_SEL_MASK = 0x0000F000, + FS_PP_DEST_SEL_OFFSET = 12, + FS_PP_ROT_DEST_SEL_MASK = 0x000F0000, + FS_PP_ROT_DEST_SEL_OFFSET = 16, + FS_PRPENC_ROT_DEST_SEL_MASK = 0x00F00000, + FS_PRPENC_ROT_DEST_SEL_OFFSET = 20, + + FS_SMFC0_DEST_SEL_MASK = 0x0000000F, + FS_SMFC0_DEST_SEL_OFFSET = 0, + FS_SMFC1_DEST_SEL_MASK = 0x00000070, + FS_SMFC1_DEST_SEL_OFFSET = 4, + FS_SMFC2_DEST_SEL_MASK = 0x00000780, + FS_SMFC2_DEST_SEL_OFFSET = 7, + FS_SMFC3_DEST_SEL_MASK = 0x00003800, + FS_SMFC3_DEST_SEL_OFFSET = 11, + + FS_DC1_SRC_SEL_MASK = 0x00F00000, + FS_DC1_SRC_SEL_OFFSET = 20, + FS_DC2_SRC_SEL_MASK = 0x000F0000, + FS_DC2_SRC_SEL_OFFSET = 16, + FS_DP_SYNC0_SRC_SEL_MASK = 0x0000000F, + FS_DP_SYNC0_SRC_SEL_OFFSET = 0, + FS_DP_SYNC1_SRC_SEL_MASK = 0x000000F0, + FS_DP_SYNC1_SRC_SEL_OFFSET = 4, + FS_DP_ASYNC0_SRC_SEL_MASK = 0x00000F00, + FS_DP_ASYNC0_SRC_SEL_OFFSET = 8, + FS_DP_ASYNC1_SRC_SEL_MASK = 0x0000F000, + FS_DP_ASYNC1_SRC_SEL_OFFSET = 12, + + FS_AUTO_REF_PER_MASK = 0, + FS_AUTO_REF_PER_OFFSET = 16, + + TSTAT_VF_MASK = 0x0000000C, + TSTAT_VF_OFFSET = 2, + TSTAT_VF_ROT_MASK = 0x00000300, + TSTAT_VF_ROT_OFFSET = 8, + TSTAT_ENC_MASK = 0x00000003, + TSTAT_ENC_OFFSET = 0, + TSTAT_ENC_ROT_MASK = 0x000000C0, + TSTAT_ENC_ROT_OFFSET = 6, + TSTAT_PP_MASK = 0x00000030, + TSTAT_PP_OFFSET = 4, + TSTAT_PP_ROT_MASK = 0x00000C00, + TSTAT_PP_ROT_OFFSET = 10, + + TASK_STAT_IDLE = 0, + TASK_STAT_ACTIVE = 1, + TASK_STAT_WAIT4READY = 2, + + /* Image Converter Register bits */ + IC_CONF_PRPENC_EN = 0x00000001, + IC_CONF_PRPENC_CSC1 = 0x00000002, + IC_CONF_PRPENC_ROT_EN = 0x00000004, + IC_CONF_PRPVF_EN = 0x00000100, + IC_CONF_PRPVF_CSC1 = 0x00000200, + IC_CONF_PRPVF_CSC2 = 0x00000400, + IC_CONF_PRPVF_CMB = 0x00000800, + IC_CONF_PRPVF_ROT_EN = 0x00001000, + IC_CONF_PP_EN = 0x00010000, + IC_CONF_PP_CSC1 = 0x00020000, + IC_CONF_PP_CSC2 = 0x00040000, + IC_CONF_PP_CMB = 0x00080000, + IC_CONF_PP_ROT_EN = 0x00100000, + IC_CONF_IC_GLB_LOC_A = 0x10000000, + IC_CONF_KEY_COLOR_EN = 0x20000000, + IC_CONF_RWS_EN = 0x40000000, + IC_CONF_CSI_MEM_WR_EN = 0x80000000, + + IC_IDMAC_1_CB0_BURST_16 = 0x00000001, + IC_IDMAC_1_CB1_BURST_16 = 0x00000002, + IC_IDMAC_1_CB2_BURST_16 = 0x00000004, + IC_IDMAC_1_CB3_BURST_16 = 0x00000008, + IC_IDMAC_1_CB4_BURST_16 = 0x00000010, + IC_IDMAC_1_CB5_BURST_16 = 0x00000020, + IC_IDMAC_1_CB6_BURST_16 = 0x00000040, + IC_IDMAC_1_CB7_BURST_16 = 0x00000080, + IC_IDMAC_1_PRPENC_ROT_MASK = 0x00003800, + IC_IDMAC_1_PRPENC_ROT_OFFSET = 11, + IC_IDMAC_1_PRPVF_ROT_MASK = 0x0001C000, + IC_IDMAC_1_PRPVF_ROT_OFFSET = 14, + IC_IDMAC_1_PP_ROT_MASK = 0x000E0000, + IC_IDMAC_1_PP_ROT_OFFSET = 17, + IC_IDMAC_1_PP_FLIP_RS = 0x00400000, + IC_IDMAC_1_PRPVF_FLIP_RS = 0x00200000, + IC_IDMAC_1_PRPENC_FLIP_RS = 0x00100000, + + IC_IDMAC_2_PRPENC_HEIGHT_MASK = 0x000003FF, + IC_IDMAC_2_PRPENC_HEIGHT_OFFSET = 0, + IC_IDMAC_2_PRPVF_HEIGHT_MASK = 0x000FFC00, + IC_IDMAC_2_PRPVF_HEIGHT_OFFSET = 10, + IC_IDMAC_2_PP_HEIGHT_MASK = 0x3FF00000, + IC_IDMAC_2_PP_HEIGHT_OFFSET = 20, + + IC_IDMAC_3_PRPENC_WIDTH_MASK = 0x000003FF, + IC_IDMAC_3_PRPENC_WIDTH_OFFSET = 0, + IC_IDMAC_3_PRPVF_WIDTH_MASK = 0x000FFC00, + IC_IDMAC_3_PRPVF_WIDTH_OFFSET = 10, + IC_IDMAC_3_PP_WIDTH_MASK = 0x3FF00000, + IC_IDMAC_3_PP_WIDTH_OFFSET = 20, + + CSI_SENS_CONF_DATA_FMT_SHIFT = 8, + CSI_SENS_CONF_DATA_FMT_MASK = 0x00000700, + CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0L, + CSI_SENS_CONF_DATA_FMT_YUV422_YUYV = 1L, + CSI_SENS_CONF_DATA_FMT_YUV422_UYVY = 2L, + CSI_SENS_CONF_DATA_FMT_BAYER = 3L, + CSI_SENS_CONF_DATA_FMT_RGB565 = 4L, + CSI_SENS_CONF_DATA_FMT_RGB555 = 5L, + CSI_SENS_CONF_DATA_FMT_RGB444 = 6L, + CSI_SENS_CONF_DATA_FMT_JPEG = 7L, + + CSI_SENS_CONF_VSYNC_POL_SHIFT = 0, + CSI_SENS_CONF_HSYNC_POL_SHIFT = 1, + CSI_SENS_CONF_DATA_POL_SHIFT = 2, + CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3, + CSI_SENS_CONF_SENS_PRTCL_MASK = 0x00000070L, + CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4, + CSI_SENS_CONF_PACK_TIGHT_SHIFT = 7, + CSI_SENS_CONF_DATA_WIDTH_SHIFT = 11, + CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15, + CSI_SENS_CONF_DIVRATIO_SHIFT = 16, + + CSI_SENS_CONF_DIVRATIO_MASK = 0x00FF0000L, + CSI_SENS_CONF_DATA_DEST_SHIFT = 24, + CSI_SENS_CONF_DATA_DEST_MASK = 0x07000000L, + CSI_SENS_CONF_JPEG8_EN_SHIFT = 27, + CSI_SENS_CONF_JPEG_EN_SHIFT = 28, + CSI_SENS_CONF_FORCE_EOF_SHIFT = 29, + CSI_SENS_CONF_DATA_EN_POL_SHIFT = 31, + + CSI_DATA_DEST_ISP = 1L, + CSI_DATA_DEST_IC = 2L, + CSI_DATA_DEST_IDMAC = 4L, + + CSI_CCIR_ERR_DET_EN = 0x01000000L, + CSI_HORI_DOWNSIZE_EN = 0x80000000L, + CSI_VERT_DOWNSIZE_EN = 0x40000000L, + CSI_TEST_GEN_MODE_EN = 0x01000000L, + + CSI_HSC_MASK = 0x1FFF0000, + CSI_HSC_SHIFT = 16, + CSI_VSC_MASK = 0x00000FFF, + CSI_VSC_SHIFT = 0, + + CSI_TEST_GEN_R_MASK = 0x000000FFL, + CSI_TEST_GEN_R_SHIFT = 0, + CSI_TEST_GEN_G_MASK = 0x0000FF00L, + CSI_TEST_GEN_G_SHIFT = 8, + CSI_TEST_GEN_B_MASK = 0x00FF0000L, + CSI_TEST_GEN_B_SHIFT = 16, + + CSI_MIPI_DI0_MASK = 0x000000FFL, + CSI_MIPI_DI0_SHIFT = 0, + CSI_MIPI_DI1_MASK = 0x0000FF00L, + CSI_MIPI_DI1_SHIFT = 8, + CSI_MIPI_DI2_MASK = 0x00FF0000L, + CSI_MIPI_DI2_SHIFT = 16, + CSI_MIPI_DI3_MASK = 0xFF000000L, + CSI_MIPI_DI3_SHIFT = 24, + + CSI_MAX_RATIO_SKIP_ISP_MASK = 0x00070000L, + CSI_MAX_RATIO_SKIP_ISP_SHIFT = 16, + CSI_SKIP_ISP_MASK = 0x00F80000L, + CSI_SKIP_ISP_SHIFT = 19, + CSI_MAX_RATIO_SKIP_SMFC_MASK = 0x00000007L, + CSI_MAX_RATIO_SKIP_SMFC_SHIFT = 0, + CSI_SKIP_SMFC_MASK = 0x000000F8L, + CSI_SKIP_SMFC_SHIFT = 3, + CSI_ID_2_SKIP_MASK = 0x00000300L, + CSI_ID_2_SKIP_SHIFT = 8, + + CSI_COLOR_FIRST_ROW_MASK = 0x00000002L, + CSI_COLOR_FIRST_COMP_MASK = 0x00000001L, + + SMFC_MAP_CH0_MASK = 0x00000007L, + SMFC_MAP_CH0_SHIFT = 0, + SMFC_MAP_CH1_MASK = 0x00000038L, + SMFC_MAP_CH1_SHIFT = 3, + SMFC_MAP_CH2_MASK = 0x000001C0L, + SMFC_MAP_CH2_SHIFT = 6, + SMFC_MAP_CH3_MASK = 0x00000E00L, + SMFC_MAP_CH3_SHIFT = 9, + + SMFC_WM0_SET_MASK = 0x00000007L, + SMFC_WM0_SET_SHIFT = 0, + SMFC_WM1_SET_MASK = 0x000001C0L, + SMFC_WM1_SET_SHIFT = 6, + SMFC_WM2_SET_MASK = 0x00070000L, + SMFC_WM2_SET_SHIFT = 16, + SMFC_WM3_SET_MASK = 0x01C00000L, + SMFC_WM3_SET_SHIFT = 22, + + SMFC_WM0_CLR_MASK = 0x00000038L, + SMFC_WM0_CLR_SHIFT = 3, + SMFC_WM1_CLR_MASK = 0x00000E00L, + SMFC_WM1_CLR_SHIFT = 9, + SMFC_WM2_CLR_MASK = 0x00380000L, + SMFC_WM2_CLR_SHIFT = 19, + SMFC_WM3_CLR_MASK = 0x0E000000L, + SMFC_WM3_CLR_SHIFT = 25, + + SMFC_BS0_MASK = 0x0000000FL, + SMFC_BS0_SHIFT = 0, + SMFC_BS1_MASK = 0x000000F0L, + SMFC_BS1_SHIFT = 4, + SMFC_BS2_MASK = 0x00000F00L, + SMFC_BS2_SHIFT = 8, + SMFC_BS3_MASK = 0x0000F000L, + SMFC_BS3_SHIFT = 12, + + PF_CONF_TYPE_MASK = 0x00000007, + PF_CONF_TYPE_SHIFT = 0, + PF_CONF_PAUSE_EN = 0x00000010, + PF_CONF_RESET = 0x00008000, + PF_CONF_PAUSE_ROW_MASK = 0x00FF0000, + PF_CONF_PAUSE_ROW_SHIFT = 16, + + DI_DW_GEN_ACCESS_SIZE_OFFSET = 24, + DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16, + + DI_GEN_DI_CLK_EXT = 0x100000, + DI_GEN_POLARITY_DISP_CLK = 0x00020000, + DI_GEN_POLARITY_1 = 0x00000001, + DI_GEN_POLARITY_2 = 0x00000002, + DI_GEN_POLARITY_3 = 0x00000004, + DI_GEN_POLARITY_4 = 0x00000008, + DI_GEN_POLARITY_5 = 0x00000010, + DI_GEN_POLARITY_6 = 0x00000020, + DI_GEN_POLARITY_7 = 0x00000040, + DI_GEN_POLARITY_8 = 0x00000080, + + DI_POL_DRDY_DATA_POLARITY = 0x00000080, + DI_POL_DRDY_POLARITY_15 = 0x00000010, + + DI_VSYNC_SEL_OFFSET = 13, + + DC_WR_CH_CONF_FIELD_MODE = 0x00000200, + DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5, + DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0, + DC_WR_CH_CONF_PROG_DI_ID = 0x00000004, + DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3, + DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018, + + DC_UGDE_0_ODD_EN = 0x02000000, + DC_UGDE_0_ID_CODED_MASK = 0x00000007, + DC_UGDE_0_ID_CODED_OFFSET = 0, + DC_UGDE_0_EV_PRIORITY_MASK = 0x00000078, + DC_UGDE_0_EV_PRIORITY_OFFSET = 3, + + DP_COM_CONF_FG_EN = 0x00000001, + DP_COM_CONF_GWSEL = 0x00000002, + DP_COM_CONF_GWAM = 0x00000004, + DP_COM_CONF_GWCKE = 0x00000008, + DP_COM_CONF_CSC_DEF_MASK = 0x00000300, + DP_COM_CONF_CSC_DEF_OFFSET = 8, + DP_COM_CONF_CSC_DEF_FG = 0x00000300, + DP_COM_CONF_CSC_DEF_BG = 0x00000200, + DP_COM_CONF_CSC_DEF_BOTH = 0x00000100, + DP_COM_CONF_GAMMA_EN = 0x00001000, + DP_COM_CONF_GAMMA_YUV_EN = 0x00002000, + + DI_SER_CONF_LLA_SER_ACCESS = 0x00000020, + DI_SER_CONF_SERIAL_CLK_POL = 0x00000010, + DI_SER_CONF_SERIAL_DATA_POL = 0x00000008, + DI_SER_CONF_SERIAL_RS_POL = 0x00000004, + DI_SER_CONF_SERIAL_CS_POL = 0x00000002, + DI_SER_CONF_WAIT4SERIAL = 0x00000001, + + VDI_C_CH_420 = 0x00000000, + VDI_C_CH_422 = 0x00000002, + VDI_C_MOT_SEL_FULL = 0x00000008, + VDI_C_MOT_SEL_LOW = 0x00000004, + VDI_C_MOT_SEL_MED = 0x00000000, + VDI_C_BURST_SIZE1_4 = 0x00000030, + VDI_C_BURST_SIZE2_4 = 0x00000300, + VDI_C_BURST_SIZE3_4 = 0x00003000, + VDI_C_VWM1_SET_1 = 0x00000000, + VDI_C_VWM1_CLR_2 = 0x00080000, + VDI_C_VWM3_SET_1 = 0x00000000, + VDI_C_VWM3_CLR_2 = 0x02000000, + VDI_C_TOP_FIELD_MAN_1 = 0x40000000, + VDI_C_TOP_FIELD_AUTO_1 = 0x80000000, +}; + +enum di_pins { + DI_PIN11 = 0, + DI_PIN12 = 1, + DI_PIN13 = 2, + DI_PIN14 = 3, + DI_PIN15 = 4, + DI_PIN16 = 5, + DI_PIN17 = 6, + DI_PIN_CS = 7, + + DI_PIN_SER_CLK = 0, + DI_PIN_SER_RS = 1, +}; + +enum di_sync_wave { + DI_SYNC_NONE = -1, + DI_SYNC_CLK = 0, + DI_SYNC_INT_HSYNC = 1, + DI_SYNC_HSYNC = 2, + DI_SYNC_VSYNC = 3, + DI_SYNC_DE = 5, +}; + +/* DC template opcodes */ +#define WROD(lf) (0x18 | (lf << 1)) +#define WRG (0x01) + +#endif diff --git a/drivers/mxc/mcu_pmic/Kconfig b/drivers/mxc/mcu_pmic/Kconfig new file mode 100644 index 000000000000..cb6815e92d86 --- /dev/null +++ b/drivers/mxc/mcu_pmic/Kconfig @@ -0,0 +1,17 @@ +# +# PMIC Modules configuration +# + +config MXC_PMIC_MC9S08DZ60 + tristate "MC9S08DZ60 PMIC" + depends on ARCH_MXC && I2C + ---help--- + This is the MXC MC9S08DZ60(MCU) PMIC support. + +config MXC_MC9SDZ60_RTC + tristate "MC9SDZ60 Real Time Clock (RTC) support" + depends on MXC_PMIC_MC9SDZ60 + ---help--- + This is the MC9SDZ60 RTC module driver. This module provides kernel API + for RTC part of MC9SDZ60. + If you want MC9SDZ60 RTC support, you should say Y here diff --git a/drivers/mxc/mcu_pmic/Makefile b/drivers/mxc/mcu_pmic/Makefile new file mode 100644 index 000000000000..96aae94d5290 --- /dev/null +++ b/drivers/mxc/mcu_pmic/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the mc9sdz60 pmic drivers. +# + +obj-$(CONFIG_MXC_PMIC_MC9SDZ60) += pmic_mc9sdz60_mod.o +pmic_mc9sdz60_mod-objs := mcu_pmic_core.o max8660.o mc9s08dz60.o mcu_pmic_gpio.o diff --git a/drivers/mxc/mcu_pmic/max8660.c b/drivers/mxc/mcu_pmic/max8660.c new file mode 100644 index 000000000000..17fe22958ca9 --- /dev/null +++ b/drivers/mxc/mcu_pmic/max8660.c @@ -0,0 +1,154 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file max8660.c + * @brief Driver for max8660 + * + * @ingroup pmic + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mcu_pmic_core.h" +#include "max8660.h" + +/* I2C bus id and device address of mcu */ +#define I2C1_BUS 0 +#define MAX8660_I2C_ADDR 0x68 + +static struct i2c_client *max8660_i2c_client; + + /* reg names for max8660 + REG_MAX8660_OUTPUT_ENABLE_1, + REG_MAX8660_OUTPUT_ENABLE_2, + REG_MAX8660_VOLT__CHANGE_1, + REG_MAX8660_V3_TARGET_VOLT_1, + REG_MAX8660_V3_TARGET_VOLT_2, + REG_MAX8660_V4_TARGET_VOLT_1, + REG_MAX8660_V4_TARGET_VOLT_2, + REG_MAX8660_V5_TARGET_VOLT_1, + REG_MAX8660_V5_TARGET_VOLT_2, + REG_MAX8660_V6V7_TARGET_VOLT, + REG_MAX8660_FORCE_PWM + */ + + /* save down the reg values for the device is write only */ +static u8 max8660_reg_value_table[] = { + 0x0, 0x0, 0x0, 0x17, 0x17, 0x1F, 0x1F, 0x04, 0x04, 0x0, 0x0 +}; +static int max8660_dev_present; + +int is_max8660_present(void) +{ + return max8660_dev_present; +} + +int max8660_get_buffered_reg_val(int reg_name, u8 *value) +{ + if (!max8660_dev_present) + return -1; + /* outof range */ + if (reg_name < REG_MAX8660_OUTPUT_ENABLE_1 + || reg_name > REG_MAX8660_FORCE_PWM) + return -1; + *value = + max8660_reg_value_table[reg_name - REG_MAX8660_OUTPUT_ENABLE_1]; + return 0; +} +int max8660_save_buffered_reg_val(int reg_name, u8 value) +{ + + /* outof range */ + if (reg_name < REG_MAX8660_OUTPUT_ENABLE_1 + || reg_name > REG_MAX8660_FORCE_PWM) + return -1; + max8660_reg_value_table[reg_name - REG_MAX8660_OUTPUT_ENABLE_1] = value; + return 0; +} + +int max8660_write_reg(u8 reg, u8 value) +{ + if (max8660_dev_present && (i2c_smbus_write_byte_data( + max8660_i2c_client, reg, value) >= 0)) + return 0; + return -1; +} + +/*! + * max8660 I2C attach function + * + * @param adapter struct i2c_client * + * @return 0 for max8660 successfully detected + */ +static int max8660_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int retval; + max8660_i2c_client = client; + retval = i2c_smbus_write_byte_data(max8660_i2c_client, + MAX8660_OUTPUT_ENABLE_1, 0); + if (retval == 0) { + max8660_dev_present = 1; + pr_info("max8660 probed !\n"); + } else { + max8660_dev_present = 0; + pr_info("max8660 not detected!\n"); + } + return retval; +} + +/*! + * max8660 I2C detach function + * + * @param client struct i2c_client * + * @return 0 + */ +static int max8660_remove(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id max8660_id[] = { + { "max8660", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, max8660_id); + +static struct i2c_driver max8660_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "max8660",}, + .probe = max8660_probe, + .remove = max8660_remove, + .id_table = max8660_id, +}; + +/* called by pmic core when init*/ +int max8660_init(void) +{ + int err; + err = i2c_add_driver(&max8660_i2c_driver); + return err; +} +void max8660_exit(void) +{ + i2c_del_driver(&max8660_i2c_driver); +} diff --git a/drivers/mxc/mcu_pmic/max8660.h b/drivers/mxc/mcu_pmic/max8660.h new file mode 100644 index 000000000000..370ca5f66a28 --- /dev/null +++ b/drivers/mxc/mcu_pmic/max8660.h @@ -0,0 +1,49 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file max8660.h + * @brief Driver for max8660 + * + * @ingroup pmic + */ +#ifndef _MAX8660_H_ +#define _MAX8660_H_ + +#ifdef __KERNEL__ + +#define MAX8660_OUTPUT_ENABLE_1 0x10 +#define MAX8660_OUTPUT_ENABLE_2 0x12 +#define MAX8660_VOLT_CHANGE_CONTROL 0x20 +#define MAX8660_V3_TARGET_VOLT_1 0x23 +#define MAX8660_V3_TARGET_VOLT_2 0x24 +#define MAX8660_V4_TARGET_VOLT_1 0x29 +#define MAX8660_V4_TARGET_VOLT_2 0x2A +#define MAX8660_V5_TARGET_VOLT_1 0x32 +#define MAX8660_V5_TARGET_VOLT_2 0x33 +#define MAX8660_V6V7_TARGET_VOLT 0x39 +#define MAX8660_FORCE_PWM 0x80 + +int is_max8660_present(void); +int max8660_write_reg(u8 reg, u8 value); +int max8660_save_buffered_reg_val(int reg_name, u8 value); +int max8660_get_buffered_reg_val(int reg_name, u8 *value); +int max8660_init(void); +void max8660_exit(void); + +extern int reg_max8660_probe(void); +extern int reg_max8660_remove(void); + +#endif /* __KERNEL__ */ + +#endif /* _MAX8660_H_ */ diff --git a/drivers/mxc/mcu_pmic/mc9s08dz60.c b/drivers/mxc/mcu_pmic/mc9s08dz60.c new file mode 100644 index 000000000000..c51ffcd5ba7d --- /dev/null +++ b/drivers/mxc/mcu_pmic/mc9s08dz60.c @@ -0,0 +1,197 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file mc9s08dz60.c + * @brief Driver for MC9sdz60 + * + * @ingroup pmic + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "mc9s08dz60.h" + +/* I2C bus id and device address of mcu */ +#define I2C1_BUS 0 +#define MC9S08DZ60_I2C_ADDR 0xD2 /* 7bits I2C address */ +static struct i2c_client *mc9s08dz60_i2c_client; + +int mc9s08dz60_read_reg(u8 reg, u8 *value) +{ + *value = (u8) i2c_smbus_read_byte_data(mc9s08dz60_i2c_client, reg); + return 0; +} + +int mc9s08dz60_write_reg(u8 reg, u8 value) +{ + if (i2c_smbus_write_byte_data(mc9s08dz60_i2c_client, reg, value) < 0) + return -1; + return 0; +} + +static ssize_t mc9s08dz60_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int i; + u8 value; + int offset = 7; + + for (i = 0; i < 7; i++) { + mc9s08dz60_read_reg(i, &value); + pr_info("reg%02x: %02x\t", i, value); + mc9s08dz60_read_reg(i + offset, &value); + pr_info("reg%02x: %02x\t", i + offset, value); + mc9s08dz60_read_reg(i + offset * 2, &value); + pr_info("reg%02x: %02x\t", i + offset * 2, value); + mc9s08dz60_read_reg(i + offset * 3, &value); + pr_info("reg%02x: %02x\t", i + offset * 3, value); + mc9s08dz60_read_reg(i + offset * 4, &value); + pr_info("reg%02x: %02x\t", i + offset * 4, value); + mc9s08dz60_read_reg(i + offset * 5, &value); + pr_info("reg%02x: %02x\n", i + offset * 5, value); + } + + return 0; +} + +static ssize_t mc9s08dz60_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int ret; + unsigned long reg, new_value; + u8 value; + char *p; + + strict_strtoul(buf, 16, ®); + + p = NULL; + p = memchr(buf, ' ', count); + + if (p == NULL) { + mc9s08dz60_read_reg(reg, &value); + pr_info("reg%02lu: %06x\n", reg, value); + return count; + } + + p += 1; + + strict_strtoul(p, 16, &new_value); + value = new_value; + + ret = mc9s08dz60_write_reg((u8)reg, value); + if (ret == 0) + pr_info("write reg%02lx: %06x\n", reg, value); + else + pr_info("register update failed\n"); + + return count; +} + +static struct device_attribute mc9s08dz60_dev_attr = { + .attr = { + .name = "mc9s08dz60_ctl", + .mode = S_IRUSR | S_IWUSR, + }, + .show = mc9s08dz60_show, + .store = mc9s08dz60_store, +}; + + +/*! + * mc9s08dz60 I2C attach function + * + * @param adapter struct i2c_adapter * + * @return 0 + */ +static int mc9s08dz60_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct mc9s08dz60 *mc9s08dz60 = NULL; + struct mc9s08dz60_platform_data *plat_data = client->dev.platform_data; + pr_info("mc9s08dz60 probing .... \n"); + + mc9s08dz60 = kzalloc(sizeof(struct mc9s08dz60), GFP_KERNEL); + if (mc9s08dz60 == NULL) + return -ENOMEM; + + i2c_set_clientdata(client, mc9s08dz60); + mc9s08dz60->dev = &client->dev; + mc9s08dz60->i2c_client = client; + + if (plat_data && plat_data->init) { + ret = plat_data->init(mc9s08dz60); + if (ret != 0) + return -1; + } + + ret = device_create_file(&client->dev, &mc9s08dz60_dev_attr); + if (ret) + dev_err(&client->dev, "create device file failed!\n"); + + + mc9s08dz60_i2c_client = client; + + return 0; +} + +/*! + * mc9s08dz60 I2C detach function + * + * @param client struct i2c_client * + * @return 0 + */ +static int mc9s08dz60_remove(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id mc9s08dz60_id[] = { + { "mc9s08dz60", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, mc9s08dz60_id); + +static struct i2c_driver mc9s08dz60_i2c_driver = { + .driver = {.owner = THIS_MODULE, + .name = "mc9s08dz60", + }, + .probe = mc9s08dz60_probe, + .remove = mc9s08dz60_remove, + .id_table = mc9s08dz60_id, +}; + +#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos)) +#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos)) + +int mc9s08dz60_init(void) +{ + int err; + err = i2c_add_driver(&mc9s08dz60_i2c_driver); + return err; +} +void mc9s08dz60_exit(void) +{ + i2c_del_driver(&mc9s08dz60_i2c_driver); +} diff --git a/drivers/mxc/mcu_pmic/mc9s08dz60.h b/drivers/mxc/mcu_pmic/mc9s08dz60.h new file mode 100644 index 000000000000..382d905cd3d1 --- /dev/null +++ b/drivers/mxc/mcu_pmic/mc9s08dz60.h @@ -0,0 +1,73 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc9s08dz60.h + * @brief Driver for mc9s08dz60 + * + * @ingroup pmic + */ +#ifndef _MC9SDZ60_H_ +#define _MC9SDZ60_H_ + +#define MCU_VERSION 0x00 +/*#define Reserved 0x01*/ +#define MCU_SECS 0x02 +#define MCU_MINS 0x03 +#define MCU_HRS 0x04 +#define MCU_DAY 0x05 +#define MCU_DATE 0x06 +#define MCU_MONTH 0x07 +#define MCU_YEAR 0x08 + +#define MCU_ALARM_SECS 0x09 +#define MCU_ALARM_MINS 0x0A +#define MCU_ALARM_HRS 0x0B +/* #define Reserved 0x0C*/ +/* #define Reserved 0x0D*/ +#define MCU_TS_CONTROL 0x0E +#define MCU_X_LOW 0x0F +#define MCU_Y_LOW 0x10 +#define MCU_XY_HIGH 0x11 +#define MCU_X_LEFT_LOW 0x12 +#define MCU_X_LEFT_HIGH 0x13 +#define MCU_X_RIGHT 0x14 +#define MCU_Y_TOP_LOW 0x15 +#define MCU_Y_TOP_HIGH 0x16 +#define MCU_Y_BOTTOM 0x17 +/* #define Reserved 0x18*/ +/* #define Reserved 0x19*/ +#define MCU_RESET_1 0x1A +#define MCU_RESET_2 0x1B +#define MCU_POWER_CTL 0x1C +#define MCU_DELAY_CONFIG 0x1D +/* #define Reserved 0x1E */ +/* #define Reserved 0x1F */ +#define MCU_GPIO_1 0x20 +#define MCU_GPIO_2 0x21 +#define MCU_KPD_1 0x22 +#define MCU_KPD_2 0x23 +#define MCU_KPD_CONTROL 0x24 +#define MCU_INT_ENABLE_1 0x25 +#define MCU_INT_ENABLE_2 0x26 +#define MCU_INT_FLAG_1 0x27 +#define MCU_INT_FLAG_2 0x28 +#define MCU_DES_FLAG 0x29 +int mc9s08dz60_read_reg(u8 reg, u8 *value); +int mc9s08dz60_write_reg(u8 reg, u8 value); +int mc9s08dz60_init(void); +void mc9s08dz60_exit(void); + +extern int reg_mc9s08dz60_probe(void); +extern int reg_mc9s08dz60_remove(void); + +#endif /* _MC9SDZ60_H_ */ diff --git a/drivers/mxc/mcu_pmic/mcu_pmic_core.c b/drivers/mxc/mcu_pmic/mcu_pmic_core.c new file mode 100644 index 000000000000..47c16d1659ca --- /dev/null +++ b/drivers/mxc/mcu_pmic/mcu_pmic_core.c @@ -0,0 +1,226 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc9s08dz60/mcu_pmic_core.c + * @brief This is the main file of mc9s08dz60 Power Control driver. + * + * @ingroup PMIC_POWER + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mcu_pmic_core.h" +#include "mc9s08dz60.h" +#include "max8660.h" + +/* bitfield macros for mcu pmic*/ +#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos)) +#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos)) + + +/* map reg names (enum pmic_reg in pmic_external.h) to real addr*/ +const static u8 mcu_pmic_reg_addr_table[] = { + MCU_VERSION, + MCU_SECS, + MCU_MINS, + MCU_HRS, + MCU_DAY, + MCU_DATE, + MCU_MONTH, + MCU_YEAR, + MCU_ALARM_SECS, + MCU_ALARM_MINS, + MCU_ALARM_HRS, + MCU_TS_CONTROL, + MCU_X_LOW, + MCU_Y_LOW, + MCU_XY_HIGH, + MCU_X_LEFT_LOW, + MCU_X_LEFT_HIGH, + MCU_X_RIGHT, + MCU_Y_TOP_LOW, + MCU_Y_TOP_HIGH, + MCU_Y_BOTTOM, + MCU_RESET_1, + MCU_RESET_2, + MCU_POWER_CTL, + MCU_DELAY_CONFIG, + MCU_GPIO_1, + MCU_GPIO_2, + MCU_KPD_1, + MCU_KPD_2, + MCU_KPD_CONTROL, + MCU_INT_ENABLE_1, + MCU_INT_ENABLE_2, + MCU_INT_FLAG_1, + MCU_INT_FLAG_2, + MCU_DES_FLAG, + MAX8660_OUTPUT_ENABLE_1, + MAX8660_OUTPUT_ENABLE_2, + MAX8660_VOLT_CHANGE_CONTROL, + MAX8660_V3_TARGET_VOLT_1, + MAX8660_V3_TARGET_VOLT_2, + MAX8660_V4_TARGET_VOLT_1, + MAX8660_V4_TARGET_VOLT_2, + MAX8660_V5_TARGET_VOLT_1, + MAX8660_V5_TARGET_VOLT_2, + MAX8660_V6V7_TARGET_VOLT, + MAX8660_FORCE_PWM +}; + +static int mcu_pmic_read(int reg_num, unsigned int *reg_val) +{ + int ret; + u8 value = 0; + /* mcu ops */ + if (reg_num >= REG_MCU_VERSION && reg_num <= REG_MCU_DES_FLAG) + ret = mc9s08dz60_read_reg(mcu_pmic_reg_addr_table[reg_num], + &value); + else if (reg_num >= REG_MAX8660_OUTPUT_ENABLE_1 + && reg_num <= REG_MAX8660_FORCE_PWM) + ret = max8660_get_buffered_reg_val(reg_num, &value); + else + return -1; + + if (ret < 0) + return -1; + *reg_val = value; + + return 0; +} + +static int mcu_pmic_write(int reg_num, const unsigned int reg_val) +{ + int ret; + u8 value = reg_val; + /* mcu ops */ + if (reg_num >= REG_MCU_VERSION && reg_num <= REG_MCU_DES_FLAG) { + + ret = + mc9s08dz60_write_reg( + mcu_pmic_reg_addr_table[reg_num], value); + if (ret < 0) + return -1; + } else if (reg_num >= REG_MAX8660_OUTPUT_ENABLE_1 + && reg_num <= REG_MAX8660_FORCE_PWM) { + ret = + max8660_write_reg(mcu_pmic_reg_addr_table[reg_num], value); + + if (ret < 0) + return -1; + + ret = max8660_save_buffered_reg_val(reg_num, value); + } else + return -1; + + return 0; +} + +int mcu_pmic_read_reg(int reg, unsigned int *reg_value, + unsigned int reg_mask) +{ + int ret = 0; + unsigned int temp = 0; + + ret = mcu_pmic_read(reg, &temp); + if (ret != 0) + return -1; + *reg_value = (temp & reg_mask); + + pr_debug("Read REG[ %d ] = 0x%x\n", reg, *reg_value); + + return ret; +} + + +int mcu_pmic_write_reg(int reg, unsigned int reg_value, + unsigned int reg_mask) +{ + int ret = 0; + unsigned int temp = 0; + + ret = mcu_pmic_read(reg, &temp); + if (ret != 0) + return -1; + temp = (temp & (~reg_mask)) | reg_value; + + ret = mcu_pmic_write(reg, temp); + if (ret != 0) + return -1; + + pr_debug("Write REG[ %d ] = 0x%x\n", reg, reg_value); + + return ret; +} + +/*! + * make max8660 - mc9s08dz60 enter low-power mode + */ +static void pmic_power_off(void) +{ + mcu_pmic_write_reg(REG_MCU_POWER_CTL, 0x10, 0x10); +} + +static int __init mcu_pmic_init(void) +{ + int err; + + /* init chips */ + err = max8660_init(); + if (err) + goto fail1; + + err = mc9s08dz60_init(); + if (err) + goto fail1; + + if (is_max8660_present()) { + pr_info("max8660 is present \n"); + pm_power_off = pmic_power_off; + } else + pr_debug("max8660 is not present\n"); + pr_info("mcu_pmic_init completed!\n"); + return 0; + +fail1: + pr_err("mcu_pmic_init failed!\n"); + return err; +} + +static void __exit mcu_pmic_exit(void) +{ + reg_max8660_remove(); + mc9s08dz60_exit(); + max8660_exit(); +} + +subsys_initcall_sync(mcu_pmic_init); +module_exit(mcu_pmic_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("mcu pmic driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/mcu_pmic/mcu_pmic_core.h b/drivers/mxc/mcu_pmic/mcu_pmic_core.h new file mode 100644 index 000000000000..969e84ff5df3 --- /dev/null +++ b/drivers/mxc/mcu_pmic/mcu_pmic_core.h @@ -0,0 +1,43 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mcu_pmic_core.h + * @brief Driver for max8660 + * + * @ingroup pmic + */ +#ifndef _MCU_PMIC_CORE_H_ +#define _MCU_PMIC_CORE_H_ + +#include + +#define MAX8660_REG_START (REG_MCU_DES_FLAG + 1) +enum { + + /* reg names for max8660 */ + REG_MAX8660_OUTPUT_ENABLE_1 = MAX8660_REG_START, + REG_MAX8660_OUTPUT_ENABLE_2, + REG_MAX8660_VOLT_CHANGE_CONTROL_1, + REG_MAX8660_V3_TARGET_VOLT_1, + REG_MAX8660_V3_TARGET_VOLT_2, + REG_MAX8660_V4_TARGET_VOLT_1, + REG_MAX8660_V4_TARGET_VOLT_2, + REG_MAX8660_V5_TARGET_VOLT_1, + REG_MAX8660_V5_TARGET_VOLT_2, + REG_MAX8660_V6V7_TARGET_VOLT, + REG_MAX8660_FORCE_PWM +}; + + +#endif /* _MCU_PMIC_CORE_H_ */ diff --git a/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c b/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c new file mode 100644 index 000000000000..417dabe35386 --- /dev/null +++ b/drivers/mxc/mcu_pmic/mcu_pmic_gpio.c @@ -0,0 +1,131 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc9s08dz60/mcu_pmic_gpio.c + * @brief This is the main file of mc9s08dz60 Power Control driver. + * + * @ingroup PMIC_POWER + */ + +/* + * Includes + */ +#include +#include +#include +#include + +#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos)) +#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos)) + +int pmic_gpio_set_bit_val(int reg, unsigned int bit, + unsigned int val) +{ + int reg_name; + u8 reg_mask = 0; + + if (bit > 7) + return -1; + + switch (reg) { + case MCU_GPIO_REG_RESET_1: + reg_name = REG_MCU_RESET_1; + break; + case MCU_GPIO_REG_RESET_2: + reg_name = REG_MCU_RESET_2; + break; + case MCU_GPIO_REG_POWER_CONTROL: + reg_name = REG_MCU_POWER_CTL; + break; + case MCU_GPIO_REG_GPIO_CONTROL_1: + reg_name = REG_MCU_GPIO_1; + break; + case MCU_GPIO_REG_GPIO_CONTROL_2: + reg_name = REG_MCU_GPIO_2; + break; + default: + return -1; + } + + SET_BIT_IN_BYTE(reg_mask, bit); + if (0 == val) + CHECK_ERROR(mcu_pmic_write_reg(reg_name, 0, reg_mask)); + else + CHECK_ERROR(mcu_pmic_write_reg(reg_name, reg_mask, reg_mask)); + + return 0; +} +EXPORT_SYMBOL(pmic_gpio_set_bit_val); + +int pmic_gpio_get_bit_val(int reg, unsigned int bit, + unsigned int *val) +{ + int reg_name; + unsigned int reg_read_val; + u8 reg_mask = 0; + + if (bit > 7) + return -1; + + switch (reg) { + case MCU_GPIO_REG_RESET_1: + reg_name = REG_MCU_RESET_1; + break; + case MCU_GPIO_REG_RESET_2: + reg_name = REG_MCU_RESET_2; + break; + case MCU_GPIO_REG_POWER_CONTROL: + reg_name = REG_MCU_POWER_CTL; + break; + case MCU_GPIO_REG_GPIO_CONTROL_1: + reg_name = REG_MCU_GPIO_1; + break; + case MCU_GPIO_REG_GPIO_CONTROL_2: + reg_name = REG_MCU_GPIO_2; + break; + default: + return -1; + } + + SET_BIT_IN_BYTE(reg_mask, bit); + CHECK_ERROR(mcu_pmic_read_reg(reg_name, ®_read_val, reg_mask)); + if (0 == reg_read_val) + *val = 0; + else + *val = 1; + + return 0; +} +EXPORT_SYMBOL(pmic_gpio_get_bit_val); + +int pmic_gpio_get_designation_bit_val(unsigned int bit, + unsigned int *val) +{ + unsigned int reg_read_val; + u8 reg_mask = 0; + + if (bit > 7) + return -1; + + SET_BIT_IN_BYTE(reg_mask, bit); + CHECK_ERROR( + mcu_pmic_read_reg(REG_MCU_DES_FLAG, ®_read_val, reg_mask)); + if (0 == reg_read_val) + *val = 0; + else + *val = 1; + + return 0; +} +EXPORT_SYMBOL(pmic_gpio_get_designation_bit_val); diff --git a/drivers/mxc/mlb/Kconfig b/drivers/mxc/mlb/Kconfig new file mode 100644 index 000000000000..7e3b16c2ddae --- /dev/null +++ b/drivers/mxc/mlb/Kconfig @@ -0,0 +1,13 @@ +# +# MLB configuration +# + +menu "MXC Media Local Bus Driver" + +config MXC_MLB + tristate "MLB support" + depends on ARCH_MX35 || ARCH_MX53 + ---help--- + Say Y to get the MLB support. + +endmenu diff --git a/drivers/mxc/mlb/Makefile b/drivers/mxc/mlb/Makefile new file mode 100644 index 000000000000..60662eb1c031 --- /dev/null +++ b/drivers/mxc/mlb/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the kernel MLB driver +# + +obj-$(CONFIG_MXC_MLB) += mxc_mlb.o diff --git a/drivers/mxc/mlb/mxc_mlb.c b/drivers/mxc/mlb/mxc_mlb.c new file mode 100644 index 000000000000..48c160a77922 --- /dev/null +++ b/drivers/mxc/mlb/mxc_mlb.c @@ -0,0 +1,1060 @@ +/* + * linux/drivers/mxc/mlb/mxc_mlb.c + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * MLB module memory map registers define + */ +#define MLB_REG_DCCR 0x0 +#define MLB_REG_SSCR 0x4 +#define MLB_REG_SDCR 0x8 +#define MLB_REG_SMCR 0xC +#define MLB_REG_VCCR 0x1C +#define MLB_REG_SBCR 0x20 +#define MLB_REG_ABCR 0x24 +#define MLB_REG_CBCR 0x28 +#define MLB_REG_IBCR 0x2C +#define MLB_REG_CICR 0x30 +#define MLB_REG_CECRn 0x40 +#define MLB_REG_CSCRn 0x44 +#define MLB_REG_CCBCRn 0x48 +#define MLB_REG_CNBCRn 0x4C +#define MLB_REG_LCBCRn 0x280 + +#define MLB_DCCR_FS_OFFSET 28 +#define MLB_DCCR_EN (1 << 31) +#define MLB_DCCR_LBM_OFFSET 30 +#define MLB_DCCR_RESET (1 << 23) +#define MLB_CECR_CE (1 << 31) +#define MLB_CECR_TR (1 << 30) +#define MLB_CECR_CT_OFFSET 28 +#define MLB_CECR_MBS (1 << 19) +#define MLB_CSCR_CBPE (1 << 0) +#define MLB_CSCR_CBDB (1 << 1) +#define MLB_CSCR_CBD (1 << 2) +#define MLB_CSCR_CBS (1 << 3) +#define MLB_CSCR_BE (1 << 4) +#define MLB_CSCR_ABE (1 << 5) +#define MLB_CSCR_LFS (1 << 6) +#define MLB_CSCR_PBPE (1 << 8) +#define MLB_CSCR_PBDB (1 << 9) +#define MLB_CSCR_PBD (1 << 10) +#define MLB_CSCR_PBS (1 << 11) +#define MLB_CSCR_RDY (1 << 16) +#define MLB_CSCR_BM (1 << 31) +#define MLB_CSCR_BF (1 << 30) +#define MLB_SSCR_SDML (1 << 5) + +#define MLB_CONTROL_TX_CHANN (0 << 4) +#define MLB_CONTROL_RX_CHANN (1 << 4) +#define MLB_ASYNC_TX_CHANN (2 << 4) +#define MLB_ASYNC_RX_CHANN (3 << 4) + +#define MLB_MINOR_DEVICES 2 +#define MLB_CONTROL_DEV_NAME "ctrl" +#define MLB_ASYNC_DEV_NAME "async" + +#define TX_CHANNEL 0 +#define RX_CHANNEL 1 +#define TX_CHANNEL_BUF_SIZE 1024 +#define RX_CHANNEL_BUF_SIZE (2*1024) +/* max package data size */ +#define ASYNC_PACKET_SIZE 1024 +#define CTRL_PACKET_SIZE 64 +#define RX_RING_NODES 10 + +#define MLB_IRAM_SIZE (MLB_MINOR_DEVICES * (TX_CHANNEL_BUF_SIZE + RX_CHANNEL_BUF_SIZE)) +#define _get_txchan(dev) mlb_devinfo[dev].channels[TX_CHANNEL] +#define _get_rxchan(dev) mlb_devinfo[dev].channels[RX_CHANNEL] + +enum { + MLB_CTYPE_SYNC, + MLB_CTYPE_ISOC, + MLB_CTYPE_ASYNC, + MLB_CTYPE_CTRL, +}; + +/*! + * Rx ring buffer + */ +struct mlb_rx_ringnode { + int size; + char *data; +}; + +struct mlb_channel_info { + + /* channel offset in memmap */ + const unsigned int reg_offset; + /* channel address */ + int address; + /*! + * channel buffer start address + * for Rx, buf_head pointer to a loop ring buffer + */ + unsigned long buf_head; + /* physical buffer head address */ + unsigned long phy_head; + /* channel buffer size */ + unsigned int buf_size; + /* channel buffer current ptr */ + unsigned long buf_ptr; + /* buffer spin lock */ + rwlock_t buf_lock; +}; + +struct mlb_dev_info { + + /* device node name */ + const char dev_name[20]; + /* channel type */ + const unsigned int channel_type; + /* channel info for tx/rx */ + struct mlb_channel_info channels[2]; + /* rx ring buffer */ + struct mlb_rx_ringnode rx_bufs[RX_RING_NODES]; + /* rx ring buffer read/write ptr */ + unsigned int rdpos, wtpos; + /* exception event */ + unsigned long ex_event; + /* channel started up or not */ + atomic_t on; + /* device open count */ + atomic_t opencnt; + /* wait queue head for channel */ + wait_queue_head_t rd_wq; + wait_queue_head_t wt_wq; + /* spinlock for event access */ + spinlock_t event_lock; +}; + +static struct mlb_dev_info mlb_devinfo[MLB_MINOR_DEVICES] = { + { + .dev_name = MLB_CONTROL_DEV_NAME, + .channel_type = MLB_CTYPE_CTRL, + .channels = { + [0] = { + .reg_offset = MLB_CONTROL_TX_CHANN, + .buf_size = TX_CHANNEL_BUF_SIZE, + .buf_lock = + __RW_LOCK_UNLOCKED(mlb_devinfo[0].channels[0]. + buf_lock), + }, + [1] = { + .reg_offset = MLB_CONTROL_RX_CHANN, + .buf_size = RX_CHANNEL_BUF_SIZE, + .buf_lock = + __RW_LOCK_UNLOCKED(mlb_devinfo[0].channels[1]. + buf_lock), + }, + }, + .on = ATOMIC_INIT(0), + .opencnt = ATOMIC_INIT(0), + .rd_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[0].rd_wq), + .wt_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[0].wt_wq), + .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[0].event_lock), + }, + { + .dev_name = MLB_ASYNC_DEV_NAME, + .channel_type = MLB_CTYPE_ASYNC, + .channels = { + [0] = { + .reg_offset = MLB_ASYNC_TX_CHANN, + .buf_size = TX_CHANNEL_BUF_SIZE, + .buf_lock = + __RW_LOCK_UNLOCKED(mlb_devinfo[1].channels[0]. + buf_lock), + }, + [1] = { + .reg_offset = MLB_ASYNC_RX_CHANN, + .buf_size = RX_CHANNEL_BUF_SIZE, + .buf_lock = + __RW_LOCK_UNLOCKED(mlb_devinfo[1].channels[1]. + buf_lock), + }, + }, + .on = ATOMIC_INIT(0), + .opencnt = ATOMIC_INIT(0), + .rd_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[1].rd_wq), + .wt_wq = __WAIT_QUEUE_HEAD_INITIALIZER(mlb_devinfo[1].wt_wq), + .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[1].event_lock), + }, +}; + +static struct regulator *reg_nvcc; /* NVCC_MLB regulator */ +static struct clk *mlb_clk; +static struct cdev mxc_mlb_dev; /* chareset device */ +static dev_t dev; +static struct class *mlb_class; /* device class */ +static struct device *class_dev; +static unsigned long mlb_base; /* mlb module base address */ +static unsigned int irq; +static unsigned long iram_base; +static __iomem void *iram_addr; + +/*! + * Initial the MLB module device + */ +static void mlb_dev_init(void) +{ + unsigned long dccr_val; + unsigned long phyaddr; + + /* reset the MLB module */ + __raw_writel(MLB_DCCR_RESET, mlb_base + MLB_REG_DCCR); + while (__raw_readl(mlb_base + MLB_REG_DCCR) + & MLB_DCCR_RESET) + ; + + /*! + * Enable MLB device, disable loopback mode, + * set default fps to 512, set mlb device address to 0 + */ + dccr_val = MLB_DCCR_EN; + __raw_writel(dccr_val, mlb_base + MLB_REG_DCCR); + + /* disable all the system interrupt */ + __raw_writel(0x5F, mlb_base + MLB_REG_SMCR); + + /* write async, control tx/rx base address */ + phyaddr = _get_txchan(0).phy_head >> 16; + __raw_writel(phyaddr << 16 | phyaddr, mlb_base + MLB_REG_CBCR); + phyaddr = _get_txchan(1).phy_head >> 16; + __raw_writel(phyaddr << 16 | phyaddr, mlb_base + MLB_REG_ABCR); + +} + +static void mlb_dev_exit(void) +{ + __raw_writel(0, mlb_base + MLB_REG_DCCR); +} + +/*! + * MLB receive start function + * + * load phy_head to next buf register to start next rx + * here use single-packet buffer, set start=end + */ +static void mlb_start_rx(int cdev_id) +{ + struct mlb_channel_info *chinfo = &_get_rxchan(cdev_id); + unsigned long next; + + next = chinfo->phy_head & 0xFFFC; + /* load next buf */ + __raw_writel((next << 16) | next, mlb_base + + MLB_REG_CNBCRn + chinfo->reg_offset); + /* set ready bit to start next rx */ + __raw_writel(MLB_CSCR_RDY, mlb_base + MLB_REG_CSCRn + + chinfo->reg_offset); +} + +/*! + * MLB transmit start function + * make sure aquiring the rw buf_lock, when calling this + */ +static void mlb_start_tx(int cdev_id) +{ + struct mlb_channel_info *chinfo = &_get_txchan(cdev_id); + unsigned long begin, end; + + begin = chinfo->phy_head; + end = (chinfo->phy_head + chinfo->buf_ptr - chinfo->buf_head) & 0xFFFC; + /* load next buf */ + __raw_writel((begin << 16) | end, mlb_base + + MLB_REG_CNBCRn + chinfo->reg_offset); + /* set ready bit to start next tx */ + __raw_writel(MLB_CSCR_RDY, mlb_base + MLB_REG_CSCRn + + chinfo->reg_offset); +} + +/*! + * Enable the MLB channel + */ +static void mlb_channel_enable(int chan_dev_id, int on) +{ + unsigned long tx_regval = 0, rx_regval = 0; + /*! + * setup the direction, enable, channel type, + * mode select, channel address and mask buf start + */ + if (on) { + unsigned int ctype = mlb_devinfo[chan_dev_id].channel_type; + tx_regval = MLB_CECR_CE | MLB_CECR_TR | MLB_CECR_MBS | + (ctype << MLB_CECR_CT_OFFSET) | + _get_txchan(chan_dev_id).address; + rx_regval = MLB_CECR_CE | MLB_CECR_MBS | + (ctype << MLB_CECR_CT_OFFSET) | + _get_rxchan(chan_dev_id).address; + + atomic_set(&mlb_devinfo[chan_dev_id].on, 1); + } else { + atomic_set(&mlb_devinfo[chan_dev_id].on, 0); + } + + /* update the rx/tx channel entry config */ + __raw_writel(tx_regval, mlb_base + MLB_REG_CECRn + + _get_txchan(chan_dev_id).reg_offset); + __raw_writel(rx_regval, mlb_base + MLB_REG_CECRn + + _get_rxchan(chan_dev_id).reg_offset); + + if (on) + mlb_start_rx(chan_dev_id); +} + +/*! + * MLB interrupt handler + */ +void mlb_tx_isr(int minor, unsigned int cis) +{ + struct mlb_channel_info *chinfo = &_get_txchan(minor); + + if (cis & MLB_CSCR_CBD) { + /* buffer done, reset the buf_ptr */ + write_lock(&chinfo->buf_lock); + chinfo->buf_ptr = chinfo->buf_head; + write_unlock(&chinfo->buf_lock); + /* wake up the writer */ + wake_up_interruptible(&mlb_devinfo[minor].wt_wq); + } +} + +void mlb_rx_isr(int minor, unsigned int cis) +{ + struct mlb_channel_info *chinfo = &_get_rxchan(minor); + unsigned long end; + unsigned int len; + + if (cis & MLB_CSCR_CBD) { + + int wpos, rpos; + + rpos = mlb_devinfo[minor].rdpos; + wpos = mlb_devinfo[minor].wtpos; + + /* buffer done, get current buffer ptr */ + end = + __raw_readl(mlb_base + MLB_REG_CCBCRn + chinfo->reg_offset); + end >>= 16; /* end here is phy */ + len = end - (chinfo->phy_head & 0xFFFC); + + /*! + * copy packet from IRAM buf to ring buf. + * if the wpos++ == rpos, drop this packet + */ + if (((wpos + 1) % RX_RING_NODES) != rpos) { + +#ifdef DEBUG + if (mlb_devinfo[minor].channel_type == MLB_CTYPE_CTRL) { + if (len > CTRL_PACKET_SIZE) + pr_debug + ("mxc_mlb: ctrl packet" + "overflow\n"); + } else { + if (len > ASYNC_PACKET_SIZE) + pr_debug + ("mxc_mlb: async packet" + "overflow\n"); + } +#endif + memcpy(mlb_devinfo[minor].rx_bufs[wpos].data, + (const void *)chinfo->buf_head, len); + mlb_devinfo[minor].rx_bufs[wpos].size = len; + + /* update the ring wpos */ + mlb_devinfo[minor].wtpos = (wpos + 1) % RX_RING_NODES; + + /* wake up the reader */ + wake_up_interruptible(&mlb_devinfo[minor].rd_wq); + + pr_debug("recv package, len:%d, rdpos: %d, wtpos: %d\n", + len, rpos, mlb_devinfo[minor].wtpos); + } else { + pr_debug + ("drop package, due to no space, (%d,%d)\n", + rpos, mlb_devinfo[minor].wtpos); + } + + /* start next rx */ + mlb_start_rx(minor); + } +} + +static irqreturn_t mlb_isr(int irq, void *dev_id) +{ + unsigned long int_status, sscr, tx_cis, rx_cis; + struct mlb_dev_info *pdev; + int minor; + + sscr = __raw_readl(mlb_base + MLB_REG_SSCR); + pr_debug("mxc_mlb: system interrupt:%lx\n", sscr); + __raw_writel(0x7F, mlb_base + MLB_REG_SSCR); + + int_status = __raw_readl(mlb_base + MLB_REG_CICR) & 0xFFFF; + pr_debug("mxc_mlb: channel interrupt ids: %lx\n", int_status); + + for (minor = 0; minor < MLB_MINOR_DEVICES; minor++) { + + pdev = &mlb_devinfo[minor]; + tx_cis = rx_cis = 0; + + /* get tx channel interrupt status */ + if (int_status & (1 << (_get_txchan(minor).reg_offset >> 4))) + tx_cis = __raw_readl(mlb_base + MLB_REG_CSCRn + + _get_txchan(minor).reg_offset); + /* get rx channel interrupt status */ + if (int_status & (1 << (_get_rxchan(minor).reg_offset >> 4))) + rx_cis = __raw_readl(mlb_base + MLB_REG_CSCRn + + _get_rxchan(minor).reg_offset); + + if (!tx_cis && !rx_cis) + continue; + + pr_debug("tx/rx int status: 0x%08lx/0x%08lx\n", tx_cis, rx_cis); + /* fill exception event */ + spin_lock(&pdev->event_lock); + pdev->ex_event |= tx_cis & 0x303; + pdev->ex_event |= (rx_cis & 0x303) << 16; + spin_unlock(&pdev->event_lock); + + /* clear the interrupt status */ + __raw_writel(tx_cis & 0xFFFF, mlb_base + MLB_REG_CSCRn + + _get_txchan(minor).reg_offset); + __raw_writel(rx_cis & 0xFFFF, mlb_base + MLB_REG_CSCRn + + _get_rxchan(minor).reg_offset); + + /* handel tx channel */ + if (tx_cis) + mlb_tx_isr(minor, tx_cis); + /* handle rx channel */ + if (rx_cis) + mlb_rx_isr(minor, rx_cis); + + } + + return IRQ_HANDLED; +} + +static int mxc_mlb_open(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + + if (minor < 0 || minor >= MLB_MINOR_DEVICES) + return -ENODEV; + + /* open for each channel device */ + if (atomic_cmpxchg(&mlb_devinfo[minor].opencnt, 0, 1) != 0) + return -EBUSY; + + /* reset the buffer read/write ptr */ + _get_txchan(minor).buf_ptr = _get_txchan(minor).buf_head; + _get_rxchan(minor).buf_ptr = _get_rxchan(minor).buf_head; + mlb_devinfo[minor].rdpos = mlb_devinfo[minor].wtpos = 0; + mlb_devinfo[minor].ex_event = 0; + + return 0; +} + +static int mxc_mlb_release(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + + /* clear channel settings and info */ + mlb_channel_enable(minor, 0); + + /* decrease the open count */ + atomic_set(&mlb_devinfo[minor].opencnt, 0); + + return 0; +} + +static int mxc_mlb_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) +{ + void __user *argp = (void __user *)arg; + unsigned long flags, event; + int minor; + + minor = MINOR(inode->i_rdev); + + switch (cmd) { + + case MLB_CHAN_SETADDR: + { + unsigned int caddr; + /* get channel address from user space */ + if (copy_from_user(&caddr, argp, sizeof(caddr))) { + pr_err("mxc_mlb: copy from user failed\n"); + return -EFAULT; + } + _get_txchan(minor).address = (caddr >> 16) & 0xFFFF; + _get_rxchan(minor).address = caddr & 0xFFFF; + break; + } + + case MLB_CHAN_STARTUP: + if (atomic_read(&mlb_devinfo[minor].on)) { + pr_debug("mxc_mlb: channel areadly startup\n"); + break; + } + mlb_channel_enable(minor, 1); + break; + case MLB_CHAN_SHUTDOWN: + if (atomic_read(&mlb_devinfo[minor].on) == 0) { + pr_debug("mxc_mlb: channel areadly shutdown\n"); + break; + } + mlb_channel_enable(minor, 0); + break; + case MLB_CHAN_GETEVENT: + /* get and clear the ex_event */ + spin_lock_irqsave(&mlb_devinfo[minor].event_lock, flags); + event = mlb_devinfo[minor].ex_event; + mlb_devinfo[minor].ex_event = 0; + spin_unlock_irqrestore(&mlb_devinfo[minor].event_lock, flags); + + if (event) { + if (copy_to_user(argp, &event, sizeof(event))) { + pr_err("mxc_mlb: copy to user failed\n"); + return -EFAULT; + } + } else { + pr_debug("mxc_mlb: no exception event now\n"); + return -EAGAIN; + } + break; + case MLB_SET_FPS: + { + unsigned int fps; + unsigned long dccr_val; + + /* get fps from user space */ + if (copy_from_user(&fps, argp, sizeof(fps))) { + pr_err("mxc_mlb: copy from user failed\n"); + return -EFAULT; + } + + /* check fps value */ + if (fps != 256 && fps != 512 && fps != 1024) { + pr_debug("mxc_mlb: invalid fps argument\n"); + return -EINVAL; + } + + dccr_val = __raw_readl(mlb_base + MLB_REG_DCCR); + dccr_val &= ~(0x3 << MLB_DCCR_FS_OFFSET); + dccr_val |= (fps >> 9) << MLB_DCCR_FS_OFFSET; + __raw_writel(dccr_val, mlb_base + MLB_REG_DCCR); + break; + } + + case MLB_GET_VER: + { + unsigned long version; + + /* get MLB device module version */ + version = __raw_readl(mlb_base + MLB_REG_VCCR); + + if (copy_to_user(argp, &version, sizeof(version))) { + pr_err("mxc_mlb: copy to user failed\n"); + return -EFAULT; + } + break; + } + + case MLB_SET_DEVADDR: + { + unsigned long dccr_val; + unsigned char devaddr; + + /* get MLB device address from user space */ + if (copy_from_user + (&devaddr, argp, sizeof(unsigned char))) { + pr_err("mxc_mlb: copy from user failed\n"); + return -EFAULT; + } + + dccr_val = __raw_readl(mlb_base + MLB_REG_DCCR); + dccr_val &= ~0xFF; + dccr_val |= devaddr; + __raw_writel(dccr_val, mlb_base + MLB_REG_DCCR); + + break; + } + default: + pr_info("mxc_mlb: Invalid ioctl command\n"); + return -EINVAL; + } + + return 0; +} + +/*! + * MLB read routine + * + * Read the current received data from queued buffer, + * and free this buffer for hw to fill ingress data. + */ +static ssize_t mxc_mlb_read(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos) +{ + int minor, ret; + int size, rdpos; + struct mlb_rx_ringnode *rxbuf; + + minor = MINOR(filp->f_dentry->d_inode->i_rdev); + + rdpos = mlb_devinfo[minor].rdpos; + rxbuf = mlb_devinfo[minor].rx_bufs; + + /* check the current rx buffer is available or not */ + if (rdpos == mlb_devinfo[minor].wtpos) { + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + /* if !O_NONBLOCK, we wait for recv packet */ + ret = wait_event_interruptible(mlb_devinfo[minor].rd_wq, + (mlb_devinfo[minor].wtpos != + rdpos)); + if (ret < 0) + return ret; + } + + size = rxbuf[rdpos].size; + if (size > count) { + /* the user buffer is too small */ + pr_warning + ("mxc_mlb: received data size is bigger than count\n"); + return -EINVAL; + } + + /* copy rx buffer data to user buffer */ + if (copy_to_user(buf, rxbuf[rdpos].data, size)) { + pr_err("mxc_mlb: copy from user failed\n"); + return -EFAULT; + } + + /* update the read ptr */ + mlb_devinfo[minor].rdpos = (rdpos + 1) % RX_RING_NODES; + + *f_pos = 0; + + return size; +} + +/*! + * MLB write routine + * + * Copy the user data to tx channel buffer, + * and prepare the channel current/next buffer ptr. + */ +static ssize_t mxc_mlb_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos) +{ + int minor; + unsigned long flags; + DEFINE_WAIT(__wait); + int ret; + + minor = MINOR(filp->f_dentry->d_inode->i_rdev); + + if (count > _get_txchan(minor).buf_size) { + /* too many data to write */ + pr_warning("mxc_mlb: overflow write data\n"); + return -EFBIG; + } + + *f_pos = 0; + + /* check the current tx buffer is used or not */ + write_lock_irqsave(&_get_txchan(minor).buf_lock, flags); + if (_get_txchan(minor).buf_ptr != _get_txchan(minor).buf_head) { + write_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags); + + /* there's already some datas being transmit now */ + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + + /* if !O_NONBLOCK, we wait for transmit finish */ + for (;;) { + prepare_to_wait(&mlb_devinfo[minor].wt_wq, + &__wait, TASK_INTERRUPTIBLE); + + write_lock_irqsave(&_get_txchan(minor).buf_lock, flags); + if (_get_txchan(minor).buf_ptr == + _get_txchan(minor).buf_head) + break; + + write_unlock_irqrestore(&_get_txchan(minor).buf_lock, + flags); + if (!signal_pending(current)) { + schedule(); + continue; + } + return -ERESTARTSYS; + } + finish_wait(&mlb_devinfo[minor].wt_wq, &__wait); + } + + /* copy user buffer to tx buffer */ + if (copy_from_user((void *)_get_txchan(minor).buf_ptr, buf, count)) { + pr_err("mxc_mlb: copy from user failed\n"); + ret = -EFAULT; + goto out; + } + _get_txchan(minor).buf_ptr += count; + + /* set current/next buffer start/end */ + mlb_start_tx(minor); + + ret = count; + +out: + write_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags); + return ret; +} + +static unsigned int mxc_mlb_poll(struct file *filp, + struct poll_table_struct *wait) +{ + int minor; + unsigned int ret = 0; + unsigned long flags; + + minor = MINOR(filp->f_dentry->d_inode->i_rdev); + + poll_wait(filp, &mlb_devinfo[minor].rd_wq, wait); + poll_wait(filp, &mlb_devinfo[minor].wt_wq, wait); + + /* check the tx buffer is avaiable or not */ + read_lock_irqsave(&_get_txchan(minor).buf_lock, flags); + if (_get_txchan(minor).buf_ptr == _get_txchan(minor).buf_head) + ret |= POLLOUT | POLLWRNORM; + read_unlock_irqrestore(&_get_txchan(minor).buf_lock, flags); + + /* check the rx buffer filled or not */ + if (mlb_devinfo[minor].rdpos != mlb_devinfo[minor].wtpos) + ret |= POLLIN | POLLRDNORM; + + /* check the exception event */ + if (mlb_devinfo[minor].ex_event) + ret |= POLLIN | POLLRDNORM; + + return ret; +} + +/*! + * char dev file operations structure + */ +static struct file_operations mxc_mlb_fops = { + + .owner = THIS_MODULE, + .open = mxc_mlb_open, + .release = mxc_mlb_release, + .ioctl = mxc_mlb_ioctl, + .poll = mxc_mlb_poll, + .read = mxc_mlb_read, + .write = mxc_mlb_write, +}; + +/*! + * This function is called whenever the MLB device is detected. + */ +static int __devinit mxc_mlb_probe(struct platform_device *pdev) +{ + int ret, mlb_major, i, j; + struct mxc_mlb_platform_data *plat_data; + struct resource *res; + void __iomem *base, *bufaddr; + unsigned long phyaddr; + + /* malloc the Rx ring buffer firstly */ + for (i = 0; i < MLB_MINOR_DEVICES; i++) { + char *buf; + int bufsize; + + if (mlb_devinfo[i].channel_type == MLB_CTYPE_ASYNC) + bufsize = ASYNC_PACKET_SIZE; + else + bufsize = CTRL_PACKET_SIZE; + + buf = kmalloc(bufsize * RX_RING_NODES, GFP_KERNEL); + if (buf == NULL) { + ret = -ENOMEM; + dev_err(&pdev->dev, "can not alloc rx buffers\n"); + goto err4; + } + for (j = 0; j < RX_RING_NODES; j++) { + mlb_devinfo[i].rx_bufs[j].data = buf; + buf += bufsize; + } + } + + /** + * Register MLB lld as two character devices + * One for Packet date channel, the other for control data channel + */ + ret = alloc_chrdev_region(&dev, 0, MLB_MINOR_DEVICES, "mxc_mlb"); + mlb_major = MAJOR(dev); + + if (ret < 0) { + dev_err(&pdev->dev, "can't get major %d\n", mlb_major); + goto err3; + } + + cdev_init(&mxc_mlb_dev, &mxc_mlb_fops); + mxc_mlb_dev.owner = THIS_MODULE; + + ret = cdev_add(&mxc_mlb_dev, dev, MLB_MINOR_DEVICES); + if (ret) { + dev_err(&pdev->dev, "can't add cdev\n"); + goto err2; + } + + /* create class and device for udev information */ + mlb_class = class_create(THIS_MODULE, "mlb"); + if (IS_ERR(mlb_class)) { + dev_err(&pdev->dev, "failed to create mlb class\n"); + ret = -ENOMEM; + goto err2; + } + + for (i = 0; i < MLB_MINOR_DEVICES; i++) { + + class_dev = device_create(mlb_class, NULL, MKDEV(mlb_major, i), + NULL, mlb_devinfo[i].dev_name); + if (IS_ERR(class_dev)) { + dev_err(&pdev->dev, "failed to create mlb %s" + " class device\n", mlb_devinfo[i].dev_name); + ret = -ENOMEM; + goto err1; + } + } + + /* get irq line */ + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No mlb irq line provided\n"); + goto err1; + } + + irq = res->start; + /* request irq */ + if (request_irq(irq, mlb_isr, 0, "mlb", NULL)) { + dev_err(&pdev->dev, "failed to request irq\n"); + ret = -EBUSY; + goto err1; + } + + /* ioremap from phy mlb to kernel space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No mlb base address provided\n"); + goto err0; + } + + base = ioremap(res->start, res->end - res->start); + dev_dbg(&pdev->dev, "mapped mlb base address: 0x%08x\n", + (unsigned int)base); + + if (base == NULL) { + dev_err(&pdev->dev, "failed to do ioremap with mlb base\n"); + goto err0; + } + mlb_base = (unsigned long)base; + + /*! + * get rx/tx buffer address from platform data + * make sure the buf_address is 4bytes aligned + * + * ------------------- <-- plat_data->buf_address + * | minor 0 tx buf | + * ----------------- + * | minor 0 rx buf | + * ----------------- + * | .... | + * ----------------- + * | minor n tx buf | + * ----------------- + * | minor n rx buf | + * ------------------- + */ + + plat_data = (struct mxc_mlb_platform_data *)pdev->dev.platform_data; + + bufaddr = iram_addr = iram_alloc(MLB_IRAM_SIZE, &iram_base); + phyaddr = iram_base; + + for (i = 0; i < MLB_MINOR_DEVICES; i++) { + /* set the virtual and physical buf head address */ + _get_txchan(i).buf_head = bufaddr; + _get_txchan(i).phy_head = phyaddr; + + bufaddr += TX_CHANNEL_BUF_SIZE; + phyaddr += TX_CHANNEL_BUF_SIZE; + + _get_rxchan(i).buf_head = (unsigned long)bufaddr; + _get_rxchan(i).phy_head = phyaddr; + + bufaddr += RX_CHANNEL_BUF_SIZE; + phyaddr += RX_CHANNEL_BUF_SIZE; + + dev_dbg(&pdev->dev, "phy_head: tx(%lx), rx(%lx)\n", + _get_txchan(i).phy_head, _get_rxchan(i).phy_head); + dev_dbg(&pdev->dev, "buf_head: tx(%lx), rx(%lx)\n", + _get_txchan(i).buf_head, _get_rxchan(i).buf_head); + } + + /* enable GPIO */ + gpio_mlb_active(); + + if (plat_data->reg_nvcc) { + /* power on MLB */ + reg_nvcc = regulator_get(&pdev->dev, plat_data->reg_nvcc); + if (!IS_ERR(reg_nvcc)) { + /* set MAX LDO6 for NVCC to 2.5V */ + regulator_set_voltage(reg_nvcc, 2500000, 2500000); + regulator_enable(reg_nvcc); + } + } + + /* enable clock */ + mlb_clk = clk_get(&pdev->dev, plat_data->mlb_clk); + clk_enable(mlb_clk); + + /* initial MLB module */ + mlb_dev_init(); + + return 0; + +err0: + free_irq(irq, NULL); +err1: + for (--i; i >= 0; i--) + device_destroy(mlb_class, MKDEV(mlb_major, i)); + + class_destroy(mlb_class); +err2: + cdev_del(&mxc_mlb_dev); +err3: + unregister_chrdev_region(dev, MLB_MINOR_DEVICES); +err4: + for (i = 0; i < MLB_MINOR_DEVICES; i++) + kfree(mlb_devinfo[i].rx_bufs[0].data); + + return ret; +} + +static int __devexit mxc_mlb_remove(struct platform_device *pdev) +{ + int i; + + mlb_dev_exit(); + + /* disable mlb clock */ + clk_disable(mlb_clk); + clk_put(mlb_clk); + + /* disable mlb power */ + regulator_disable(reg_nvcc); + regulator_put(reg_nvcc); + + /* inactive GPIO */ + gpio_mlb_inactive(); + + iram_free(iram_base, MLB_IRAM_SIZE); + + /* iounmap */ + iounmap((void *)mlb_base); + + free_irq(irq, NULL); + + /* destroy mlb device class */ + for (i = MLB_MINOR_DEVICES - 1; i >= 0; i--) + device_destroy(mlb_class, MKDEV(MAJOR(dev), i)); + class_destroy(mlb_class); + + /* Unregister the two MLB devices */ + cdev_del(&mxc_mlb_dev); + unregister_chrdev_region(dev, MLB_MINOR_DEVICES); + + for (i = 0; i < MLB_MINOR_DEVICES; i++) + kfree(mlb_devinfo[i].rx_bufs[0].data); + + return 0; +} + +#ifdef CONFIG_PM +static int mxc_mlb_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int mxc_mlb_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define mxc_mlb_suspend NULL +#define mxc_mlb_resume NULL +#endif + +/*! + * platform driver structure for MLB + */ +static struct platform_driver mxc_mlb_driver = { + .driver = { + .name = "mxc_mlb"}, + .probe = mxc_mlb_probe, + .remove = __devexit_p(mxc_mlb_remove), + .suspend = mxc_mlb_suspend, + .resume = mxc_mlb_resume, +}; + +static int __init mxc_mlb_init(void) +{ + return platform_driver_register(&mxc_mlb_driver); +} + +static void __exit mxc_mlb_exit(void) +{ + platform_driver_unregister(&mxc_mlb_driver); +} + +module_init(mxc_mlb_init); +module_exit(mxc_mlb_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MLB low level driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/Kconfig b/drivers/mxc/pmic/Kconfig new file mode 100644 index 000000000000..4ee91110fc03 --- /dev/null +++ b/drivers/mxc/pmic/Kconfig @@ -0,0 +1,64 @@ +# +# PMIC device driver configuration +# + +menu "MXC PMIC support" + +config MXC_PMIC + boolean + +config MXC_PMIC_MC13783 + tristate "MC13783 PMIC" + depends on ARCH_MXC && SPI + select MXC_PMIC + ---help--- + This is the MXC MC13783(PMIC) support. It include + ADC, Audio, Battery, Connectivity, Light, Power and RTC. + +config MXC_PMIC_MC13892 + tristate "MC13892 PMIC" + depends on ARCH_MXC && (I2C || SPI) + select MXC_PMIC + ---help--- + This is the MXC MC13892(PMIC) support. It include + ADC, Battery, Connectivity, Light, Power and RTC. + +config MXC_PMIC_I2C + bool "Support PMIC I2C Interface" + depends on MXC_PMIC_MC13892 && I2C + +config MXC_PMIC_SPI + bool "Support PMIC SPI Interface" + depends on (MXC_PMIC_MC13892 || MXC_PMIC_MC13783) && SPI + +config MXC_PMIC_MC34704 + tristate "MC34704 PMIC" + depends on ARCH_MXC && I2C + select MXC_PMIC + ---help--- + This is the MXC MC34704 PMIC support. + +config MXC_PMIC_MC9SDZ60 + tristate "MC9sDZ60 PMIC" + depends on ARCH_MXC && I2C + select MXC_PMIC + ---help--- + This is the MXC MC9sDZ60(MCU) PMIC support. + +config MXC_PMIC_CHARDEV + tristate "MXC PMIC device interface" + depends on MXC_PMIC + help + Say Y here to use "pmic" device files, found in the /dev directory + on the system. They make it possible to have user-space programs + use or controll PMIC. Mainly its useful for notifying PMIC events + to user-space programs. + +comment "MXC PMIC Client Drivers" + depends on MXC_PMIC + +source "drivers/mxc/pmic/mc13783/Kconfig" + +source "drivers/mxc/pmic/mc13892/Kconfig" + +endmenu diff --git a/drivers/mxc/pmic/Makefile b/drivers/mxc/pmic/Makefile new file mode 100644 index 000000000000..385c07e8509f --- /dev/null +++ b/drivers/mxc/pmic/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the MXC PMIC drivers. +# + +obj-y += core/ +obj-$(CONFIG_MXC_PMIC_MC13783) += mc13783/ +obj-$(CONFIG_MXC_PMIC_MC13892) += mc13892/ diff --git a/drivers/mxc/pmic/core/Makefile b/drivers/mxc/pmic/core/Makefile new file mode 100644 index 000000000000..bb42231e3aa8 --- /dev/null +++ b/drivers/mxc/pmic/core/Makefile @@ -0,0 +1,21 @@ +# +# Makefile for the PMIC core drivers. +# +obj-$(CONFIG_MXC_PMIC_MC13783) += pmic_mc13783_mod.o +pmic_mc13783_mod-objs := pmic_external.o pmic_event.o pmic_common.o pmic_core_spi.o mc13783.o + +obj-$(CONFIG_MXC_PMIC_MC13892) += pmic_mc13892_mod.o +pmic_mc13892_mod-objs := pmic_external.o pmic_event.o pmic_common.o mc13892.o + +ifneq ($(CONFIG_MXC_PMIC_SPI),) +pmic_mc13892_mod-objs += pmic_core_spi.o +endif + +ifneq ($(CONFIG_MXC_PMIC_I2C),) +pmic_mc13892_mod-objs += pmic_core_i2c.o +endif + +obj-$(CONFIG_MXC_PMIC_MC34704) += pmic_mc34704_mod.o +pmic_mc34704_mod-objs := pmic_external.o pmic_event.o mc34704.o + +obj-$(CONFIG_MXC_PMIC_CHARDEV) += pmic-dev.o diff --git a/drivers/mxc/pmic/core/mc13783.c b/drivers/mxc/pmic/core/mc13783.c new file mode 100644 index 000000000000..812de6e146aa --- /dev/null +++ b/drivers/mxc/pmic/core/mc13783.c @@ -0,0 +1,380 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic/core/mc13783.c + * @brief This file contains MC13783 specific PMIC code. This implementaion + * may differ for each PMIC chip. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "pmic.h" + +/* + * Defines + */ +#define EVENT_MASK_0 0x697fdf +#define EVENT_MASK_1 0x3efffb +#define MXC_PMIC_FRAME_MASK 0x00FFFFFF +#define MXC_PMIC_MAX_REG_NUM 0x3F +#define MXC_PMIC_REG_NUM_SHIFT 0x19 +#define MXC_PMIC_WRITE_BIT_SHIFT 31 + +static unsigned int events_enabled0; +static unsigned int events_enabled1; +struct mxc_pmic pmic_drv_data; + +/*! + * This function is called to read a register on PMIC. + * + * @param reg_num number of the pmic register to be read + * @param reg_val return value of register + * + * @return Returns 0 on success -1 on failure. + */ +int pmic_read(unsigned int reg_num, unsigned int *reg_val) +{ + unsigned int frame = 0; + int ret = 0; + + if (reg_num > MXC_PMIC_MAX_REG_NUM) + return PMIC_ERROR; + + frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT; + + ret = spi_rw(pmic_drv_data.spi, (u8 *) &frame, 1); + + *reg_val = frame & MXC_PMIC_FRAME_MASK; + + return ret; +} + +/*! + * This function is called to write a value to the register on PMIC. + * + * @param reg_num number of the pmic register to be written + * @param reg_val value to be written + * + * @return Returns 0 on success -1 on failure. + */ +int pmic_write(int reg_num, const unsigned int reg_val) +{ + unsigned int frame = 0; + int ret = 0; + + if (reg_num > MXC_PMIC_MAX_REG_NUM) + return PMIC_ERROR; + + frame |= (1 << MXC_PMIC_WRITE_BIT_SHIFT); + + frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT; + + frame |= reg_val & MXC_PMIC_FRAME_MASK; + + ret = spi_rw(pmic_drv_data.spi, (u8 *) &frame, 1); + + return ret; +} + +void *pmic_alloc_data(struct device *dev) +{ + struct mc13783 *mc13783; + + mc13783 = kzalloc(sizeof(struct mc13783), GFP_KERNEL); + if (mc13783 == NULL) + return NULL; + + mc13783->dev = dev; + + return (void *)mc13783; +} + +/*! + * This function initializes the SPI device parameters for this PMIC. + * + * @param spi the SPI slave device(PMIC) + * + * @return None + */ +int pmic_spi_setup(struct spi_device *spi) +{ + /* Setup the SPI slave i.e.PMIC */ + pmic_drv_data.spi = spi; + + spi->mode = SPI_MODE_2 | SPI_CS_HIGH; + spi->bits_per_word = 32; + + return spi_setup(spi); +} + +/*! + * This function initializes the PMIC registers. + * + * @return None + */ +int pmic_init_registers(void) +{ + CHECK_ERROR(pmic_write(REG_INTERRUPT_MASK_0, MXC_PMIC_FRAME_MASK)); + CHECK_ERROR(pmic_write(REG_INTERRUPT_MASK_1, MXC_PMIC_FRAME_MASK)); + CHECK_ERROR(pmic_write(REG_INTERRUPT_STATUS_0, MXC_PMIC_FRAME_MASK)); + CHECK_ERROR(pmic_write(REG_INTERRUPT_STATUS_1, MXC_PMIC_FRAME_MASK)); + return PMIC_SUCCESS; +} + +/*! + * This function returns the PMIC version in system. + * + * @param ver pointer to the pmic_version_t structure + * + * @return This function returns PMIC version. + */ +void pmic_get_revision(pmic_version_t *ver) +{ + int rev_id = 0; + int rev1 = 0; + int rev2 = 0; + int finid = 0; + int icid = 0; + + ver->id = PMIC_MC13783; + pmic_read(REG_REVISION, &rev_id); + + rev1 = (rev_id & 0x018) >> 3; + rev2 = (rev_id & 0x007); + icid = (rev_id & 0x01C0) >> 6; + finid = (rev_id & 0x01E00) >> 9; + + /* Ver 0.2 is actually 3.2a. Report as 3.2 */ + if ((rev1 == 0) && (rev2 == 2)) { + rev1 = 3; + } + + if (rev1 == 0 || icid != 2) { + ver->revision = -1; + printk(KERN_NOTICE + "mc13783: Not detected.\tAccess failed\t!!!\n"); + } else { + ver->revision = ((rev1 * 10) + rev2); + printk(KERN_INFO "mc13783 Rev %d.%d FinVer %x detected\n", rev1, + rev2, finid); + } + + return; + +} + +/*! + * This function reads the interrupt status registers of PMIC + * and determine the current active events. + * + * @param active_events array pointer to be used to return active + * event numbers. + * + * @return This function returns PMIC version. + */ +unsigned int pmic_get_active_events(unsigned int *active_events) +{ + unsigned int count = 0; + unsigned int status0, status1; + int bit_set; + + pmic_read(REG_INTERRUPT_STATUS_0, &status0); + pmic_read(REG_INTERRUPT_STATUS_1, &status1); + pmic_write(REG_INTERRUPT_STATUS_0, status0); + pmic_write(REG_INTERRUPT_STATUS_1, status1); + status0 &= events_enabled0; + status1 &= events_enabled1; + + while (status0) { + bit_set = ffs(status0) - 1; + *(active_events + count) = bit_set; + count++; + status0 ^= (1 << bit_set); + } + while (status1) { + bit_set = ffs(status1) - 1; + *(active_events + count) = bit_set + 24; + count++; + status1 ^= (1 << bit_set); + } + + return count; +} + +/*! + * This function unsets a bit in mask register of pmic to unmask an event IT. + * + * @param event the event to be unmasked + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +int pmic_event_unmask(type_event event) +{ + unsigned int event_mask = 0; + unsigned int mask_reg = 0; + unsigned int event_bit = 0; + int ret; + + if (event < EVENT_E1HZI) { + mask_reg = REG_INTERRUPT_MASK_0; + event_mask = EVENT_MASK_0; + event_bit = (1 << event); + events_enabled0 |= event_bit; + } else { + event -= 24; + mask_reg = REG_INTERRUPT_MASK_1; + event_mask = EVENT_MASK_1; + event_bit = (1 << event); + events_enabled1 |= event_bit; + } + + if ((event_bit & event_mask) == 0) { + pr_debug("Error: unmasking a reserved/unused event\n"); + return PMIC_ERROR; + } + + ret = pmic_write_reg(mask_reg, 0, event_bit); + + pr_debug("Enable Event : %d\n", event); + + return ret; +} + +/*! + * This function sets a bit in mask register of pmic to disable an event IT. + * + * @param event the event to be masked + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +int pmic_event_mask(type_event event) +{ + unsigned int event_mask = 0; + unsigned int mask_reg = 0; + unsigned int event_bit = 0; + int ret; + + if (event < EVENT_E1HZI) { + mask_reg = REG_INTERRUPT_MASK_0; + event_mask = EVENT_MASK_0; + event_bit = (1 << event); + events_enabled0 &= ~event_bit; + } else { + event -= 24; + mask_reg = REG_INTERRUPT_MASK_1; + event_mask = EVENT_MASK_1; + event_bit = (1 << event); + events_enabled1 &= ~event_bit; + } + + if ((event_bit & event_mask) == 0) { + pr_debug("Error: masking a reserved/unused event\n"); + return PMIC_ERROR; + } + + ret = pmic_write_reg(mask_reg, event_bit, event_bit); + + pr_debug("Disable Event : %d\n", event); + + return ret; +} + +/*! + * This function is called to read all sensor bits of PMIC. + * + * @param sensor Sensor to be checked. + * + * @return This function returns true if the sensor bit is high; + * or returns false if the sensor bit is low. + */ +bool pmic_check_sensor(t_sensor sensor) +{ + unsigned int reg_val = 0; + + CHECK_ERROR(pmic_read_reg + (REG_INTERRUPT_SENSE_0, ®_val, PMIC_ALL_BITS)); + + if ((1 << sensor) & reg_val) + return true; + else + return false; +} + +/*! + * This function checks one sensor of PMIC. + * + * @param sensor_bits structure of all sensor bits. + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ + +PMIC_STATUS pmic_get_sensors(t_sensor_bits *sensor_bits) +{ + int sense_0 = 0; + int sense_1 = 0; + + memset(sensor_bits, 0, sizeof(t_sensor_bits)); + + pmic_read_reg(REG_INTERRUPT_SENSE_0, &sense_0, 0xffffff); + pmic_read_reg(REG_INTERRUPT_SENSE_1, &sense_1, 0xffffff); + + sensor_bits->sense_chgdets = (sense_0 & (1 << 6)) ? true : false; + sensor_bits->sense_chgovs = (sense_0 & (1 << 7)) ? true : false; + sensor_bits->sense_chgrevs = (sense_0 & (1 << 8)) ? true : false; + sensor_bits->sense_chgshorts = (sense_0 & (1 << 9)) ? true : false; + sensor_bits->sense_cccvs = (sense_0 & (1 << 10)) ? true : false; + sensor_bits->sense_chgcurrs = (sense_0 & (1 << 11)) ? true : false; + sensor_bits->sense_bpons = (sense_0 & (1 << 12)) ? true : false; + sensor_bits->sense_lobatls = (sense_0 & (1 << 13)) ? true : false; + sensor_bits->sense_lobaths = (sense_0 & (1 << 14)) ? true : false; + sensor_bits->sense_usb4v4s = (sense_0 & (1 << 16)) ? true : false; + sensor_bits->sense_usb2v0s = (sense_0 & (1 << 17)) ? true : false; + sensor_bits->sense_usb0v8s = (sense_0 & (1 << 18)) ? true : false; + sensor_bits->sense_id_floats = (sense_0 & (1 << 19)) ? true : false; + sensor_bits->sense_id_gnds = (sense_0 & (1 << 20)) ? true : false; + sensor_bits->sense_se1s = (sense_0 & (1 << 21)) ? true : false; + sensor_bits->sense_ckdets = (sense_0 & (1 << 22)) ? true : false; + + sensor_bits->sense_onofd1s = (sense_1 & (1 << 3)) ? true : false; + sensor_bits->sense_onofd2s = (sense_1 & (1 << 4)) ? true : false; + sensor_bits->sense_onofd3s = (sense_1 & (1 << 5)) ? true : false; + sensor_bits->sense_pwrrdys = (sense_1 & (1 << 11)) ? true : false; + sensor_bits->sense_thwarnhs = (sense_1 & (1 << 12)) ? true : false; + sensor_bits->sense_thwarnls = (sense_1 & (1 << 13)) ? true : false; + sensor_bits->sense_clks = (sense_1 & (1 << 14)) ? true : false; + sensor_bits->sense_mc2bs = (sense_1 & (1 << 17)) ? true : false; + sensor_bits->sense_hsdets = (sense_1 & (1 << 18)) ? true : false; + sensor_bits->sense_hsls = (sense_1 & (1 << 19)) ? true : false; + sensor_bits->sense_alspths = (sense_1 & (1 << 20)) ? true : false; + sensor_bits->sense_ahsshorts = (sense_1 & (1 << 21)) ? true : false; + return PMIC_SUCCESS; +} + +EXPORT_SYMBOL(pmic_check_sensor); +EXPORT_SYMBOL(pmic_get_sensors); diff --git a/drivers/mxc/pmic/core/mc13892.c b/drivers/mxc/pmic/core/mc13892.c new file mode 100644 index 000000000000..a2cbb1645901 --- /dev/null +++ b/drivers/mxc/pmic/core/mc13892.c @@ -0,0 +1,335 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic/core/mc13892.c + * @brief This file contains MC13892 specific PMIC code. This implementaion + * may differ for each PMIC chip. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "pmic.h" + +/* + * Defines + */ +#define MC13892_I2C_RETRY_TIMES 10 +#define MXC_PMIC_FRAME_MASK 0x00FFFFFF +#define MXC_PMIC_MAX_REG_NUM 0x3F +#define MXC_PMIC_REG_NUM_SHIFT 0x19 +#define MXC_PMIC_WRITE_BIT_SHIFT 31 + +static unsigned int events_enabled0; +static unsigned int events_enabled1; +static struct mxc_pmic pmic_drv_data; +#ifndef CONFIG_MXC_PMIC_I2C +struct i2c_client *mc13892_client; +#endif + +int pmic_i2c_24bit_read(struct i2c_client *client, unsigned int reg_num, + unsigned int *value) +{ + unsigned char buf[3]; + int ret; + int i; + + memset(buf, 0, 3); + for (i = 0; i < MC13892_I2C_RETRY_TIMES; i++) { + ret = i2c_smbus_read_i2c_block_data(client, reg_num, 3, buf); + if (ret == 3) + break; + msleep(1); + } + + if (ret == 3) { + *value = buf[0] << 16 | buf[1] << 8 | buf[2]; + return ret; + } else { + pr_err("24bit read error, ret = %d\n", ret); + return -1; /* return -1 on failure */ + } +} + +int pmic_i2c_24bit_write(struct i2c_client *client, + unsigned int reg_num, unsigned int reg_val) +{ + char buf[3]; + int ret; + int i; + + buf[0] = (reg_val >> 16) & 0xff; + buf[1] = (reg_val >> 8) & 0xff; + buf[2] = (reg_val) & 0xff; + + for (i = 0; i < MC13892_I2C_RETRY_TIMES; i++) { + ret = i2c_smbus_write_i2c_block_data(client, reg_num, 3, buf); + if (ret == 0) + break; + msleep(1); + } + if (i == MC13892_I2C_RETRY_TIMES) + pr_err("24bit write error, ret = %d\n", ret); + + return ret; +} + +int pmic_read(int reg_num, unsigned int *reg_val) +{ + unsigned int frame = 0; + int ret = 0; + + if (pmic_drv_data.spi != NULL) { + if (reg_num > MXC_PMIC_MAX_REG_NUM) + return PMIC_ERROR; + + frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT; + + ret = spi_rw(pmic_drv_data.spi, (u8 *) &frame, 1); + + *reg_val = frame & MXC_PMIC_FRAME_MASK; + } else { + if (mc13892_client == NULL) + return PMIC_ERROR; + + if (pmic_i2c_24bit_read(mc13892_client, reg_num, reg_val) == -1) + return PMIC_ERROR; + } + + return PMIC_SUCCESS; +} + +int pmic_write(int reg_num, const unsigned int reg_val) +{ + unsigned int frame = 0; + int ret = 0; + + if (pmic_drv_data.spi != NULL) { + if (reg_num > MXC_PMIC_MAX_REG_NUM) + return PMIC_ERROR; + + frame |= (1 << MXC_PMIC_WRITE_BIT_SHIFT); + + frame |= reg_num << MXC_PMIC_REG_NUM_SHIFT; + + frame |= reg_val & MXC_PMIC_FRAME_MASK; + + ret = spi_rw(pmic_drv_data.spi, (u8 *) &frame, 1); + + return ret; + } else { + if (mc13892_client == NULL) + return PMIC_ERROR; + + return pmic_i2c_24bit_write(mc13892_client, reg_num, reg_val); + } +} + +void *pmic_alloc_data(struct device *dev) +{ + struct mc13892 *mc13892; + + mc13892 = kzalloc(sizeof(struct mc13892), GFP_KERNEL); + if (mc13892 == NULL) + return NULL; + + mc13892->dev = dev; + + return (void *)mc13892; +} + +/*! + * This function initializes the SPI device parameters for this PMIC. + * + * @param spi the SPI slave device(PMIC) + * + * @return None + */ +int pmic_spi_setup(struct spi_device *spi) +{ + /* Setup the SPI slave i.e.PMIC */ + pmic_drv_data.spi = spi; + + spi->mode = SPI_MODE_0 | SPI_CS_HIGH; + spi->bits_per_word = 32; + + return spi_setup(spi); +} + +int pmic_init_registers(void) +{ + CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF)); + CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF)); + CHECK_ERROR(pmic_write(REG_INT_STATUS0, 0xFFFFFF)); + CHECK_ERROR(pmic_write(REG_INT_STATUS1, 0xFFFFFF)); + /* disable auto charge */ + if (machine_is_mx51_3ds()) + CHECK_ERROR(pmic_write(REG_CHARGE, 0xB40003)); + + pm_power_off = mc13892_power_off; + + return PMIC_SUCCESS; +} + +unsigned int pmic_get_active_events(unsigned int *active_events) +{ + unsigned int count = 0; + unsigned int status0, status1; + int bit_set; + + pmic_read(REG_INT_STATUS0, &status0); + pmic_read(REG_INT_STATUS1, &status1); + pmic_write(REG_INT_STATUS0, status0); + pmic_write(REG_INT_STATUS1, status1); + status0 &= events_enabled0; + status1 &= events_enabled1; + + while (status0) { + bit_set = ffs(status0) - 1; + *(active_events + count) = bit_set; + count++; + status0 ^= (1 << bit_set); + } + while (status1) { + bit_set = ffs(status1) - 1; + *(active_events + count) = bit_set + 24; + count++; + status1 ^= (1 << bit_set); + } + + return count; +} + +#define EVENT_MASK_0 0x387fff +#define EVENT_MASK_1 0x1177ef + +int pmic_event_unmask(type_event event) +{ + unsigned int event_mask = 0; + unsigned int mask_reg = 0; + unsigned int event_bit = 0; + int ret; + + if (event < EVENT_1HZI) { + mask_reg = REG_INT_MASK0; + event_mask = EVENT_MASK_0; + event_bit = (1 << event); + events_enabled0 |= event_bit; + } else { + event -= 24; + mask_reg = REG_INT_MASK1; + event_mask = EVENT_MASK_1; + event_bit = (1 << event); + events_enabled1 |= event_bit; + } + + if ((event_bit & event_mask) == 0) { + pr_debug("Error: unmasking a reserved/unused event\n"); + return PMIC_ERROR; + } + + ret = pmic_write_reg(mask_reg, 0, event_bit); + + pr_debug("Enable Event : %d\n", event); + + return ret; +} + +int pmic_event_mask(type_event event) +{ + unsigned int event_mask = 0; + unsigned int mask_reg = 0; + unsigned int event_bit = 0; + int ret; + + if (event < EVENT_1HZI) { + mask_reg = REG_INT_MASK0; + event_mask = EVENT_MASK_0; + event_bit = (1 << event); + events_enabled0 &= ~event_bit; + } else { + event -= 24; + mask_reg = REG_INT_MASK1; + event_mask = EVENT_MASK_1; + event_bit = (1 << event); + events_enabled1 &= ~event_bit; + } + + if ((event_bit & event_mask) == 0) { + pr_debug("Error: masking a reserved/unused event\n"); + return PMIC_ERROR; + } + + ret = pmic_write_reg(mask_reg, event_bit, event_bit); + + pr_debug("Disable Event : %d\n", event); + + return ret; +} + +/*! + * This function returns the PMIC version in system. + * + * @param ver pointer to the pmic_version_t structure + * + * @return This function returns PMIC version. + */ +void pmic_get_revision(pmic_version_t *ver) +{ + int rev_id = 0; + int rev1 = 0; + int rev2 = 0; + int finid = 0; + int icid = 0; + + ver->id = PMIC_MC13892; + pmic_read(REG_IDENTIFICATION, &rev_id); + + rev1 = (rev_id & 0x018) >> 3; + rev2 = (rev_id & 0x007); + icid = (rev_id & 0x01C0) >> 6; + finid = (rev_id & 0x01E00) >> 9; + + ver->revision = ((rev1 * 10) + rev2); + printk(KERN_INFO "mc13892 Rev %d.%d FinVer %x detected\n", rev1, + rev2, finid); +} + +void mc13892_power_off(void) +{ + unsigned int value; + + pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff); + + value |= 0x000008; + + pmic_write_reg(REG_POWER_CTL0, value, 0xffffff); +} diff --git a/drivers/mxc/pmic/core/mc34704.c b/drivers/mxc/pmic/core/mc34704.c new file mode 100644 index 000000000000..e70a45134c6a --- /dev/null +++ b/drivers/mxc/pmic/core/mc34704.c @@ -0,0 +1,329 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic/core/mc34704.c + * @brief This file contains MC34704 specific PMIC code. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pmic.h" + +/* + * Globals + */ +static pmic_version_t mxc_pmic_version = { + .id = PMIC_MC34704, + .revision = 0, +}; +static unsigned int events_enabled; +unsigned int active_events[MAX_ACTIVE_EVENTS]; +struct i2c_client *mc34704_client; +static void pmic_trigger_poll(void); + +#define MAX_MC34704_REG 0x59 +static unsigned int mc34704_reg_readonly[MAX_MC34704_REG / 32 + 1] = { + (1 << 0x03) || (1 << 0x05) || (1 << 0x07) || (1 << 0x09) || + (1 << 0x0B) || (1 << 0x0E) || (1 << 0x11) || (1 << 0x14) || + (1 << 0x17) || (1 << 0x18), + 0, +}; +static unsigned int mc34704_reg_written[MAX_MC34704_REG / 32 + 1]; +static unsigned char mc34704_shadow_regs[MAX_MC34704_REG - 1]; +#define IS_READONLY(r) ((1 << ((r) % 32)) & mc34704_reg_readonly[(r) / 32]) +#define WAS_WRITTEN(r) ((1 << ((r) % 32)) & mc34704_reg_written[(r) / 32]) +#define MARK_WRITTEN(r) do { \ + mc34704_reg_written[(r) / 32] |= (1 << ((r) % 32)); \ +} while (0) + +int pmic_read(int reg_nr, unsigned int *reg_val) +{ + int c; + + /* + * Use the shadow register if we've written to it + */ + if (WAS_WRITTEN(reg_nr)) { + *reg_val = mc34704_shadow_regs[reg_nr]; + return PMIC_SUCCESS; + } + + /* + * Otherwise, actually read the real register. + * Write-only registers will read as zero. + */ + c = i2c_smbus_read_byte_data(mc34704_client, reg_nr); + if (c == -1) { + pr_debug("mc34704: error reading register 0x%02x\n", reg_nr); + return PMIC_ERROR; + } else { + *reg_val = c; + return PMIC_SUCCESS; + } +} + +int pmic_write(int reg_nr, const unsigned int reg_val) +{ + int ret; + + ret = i2c_smbus_write_byte_data(mc34704_client, reg_nr, reg_val); + if (ret == -1) { + return PMIC_ERROR; + } else { + /* + * Update our software copy of the register since you + * can't read what you wrote. + */ + if (!IS_READONLY(reg_nr)) { + mc34704_shadow_regs[reg_nr] = reg_val; + MARK_WRITTEN(reg_nr); + } + return PMIC_SUCCESS; + } +} + +unsigned int pmic_get_active_events(unsigned int *active_events) +{ + unsigned int count = 0; + unsigned int faults; + int bit_set; + + /* Check for any relevant PMIC faults */ + pmic_read(REG_MC34704_FAULTS, &faults); + faults &= events_enabled; + + /* + * Mask all active events, because there is no way to acknowledge + * or dismiss them in the PMIC -- they're sticky. + */ + events_enabled &= ~faults; + + /* Account for all unmasked faults */ + while (faults) { + bit_set = ffs(faults) - 1; + *(active_events + count) = bit_set; + count++; + faults ^= (1 << bit_set); + } + return count; +} + +int pmic_event_unmask(type_event event) +{ + unsigned int event_bit = 0; + unsigned int prior_events = events_enabled; + + event_bit = (1 << event); + events_enabled |= event_bit; + + pr_debug("Enable Event : %d\n", event); + + /* start the polling task as needed */ + if (events_enabled && prior_events == 0) + pmic_trigger_poll(); + + return 0; +} + +int pmic_event_mask(type_event event) +{ + unsigned int event_bit = 0; + + event_bit = (1 << event); + events_enabled &= ~event_bit; + + pr_debug("Disable Event : %d\n", event); + + return 0; +} + +/*! + * PMIC event polling task. This task is called periodically to poll + * for possible MC34704 events (No interrupt supplied by the hardware). + */ +static void pmic_event_task(struct work_struct *work); +DECLARE_DELAYED_WORK(pmic_ws, pmic_event_task); + +static void pmic_trigger_poll(void) +{ + schedule_delayed_work(&pmic_ws, HZ / 10); +} + +static void pmic_event_task(struct work_struct *work) +{ + unsigned int count = 0; + int i; + + count = pmic_get_active_events(active_events); + pr_debug("active events number %d\n", count); + + /* call handlers for all active events */ + for (i = 0; i < count; i++) + pmic_event_callback(active_events[i]); + + /* re-trigger this task, but only if somebody is watching */ + if (events_enabled) + pmic_trigger_poll(); + + return; +} + +pmic_version_t pmic_get_version(void) +{ + return mxc_pmic_version; +} +EXPORT_SYMBOL(pmic_get_version); + +int __devinit pmic_init_registers(void) +{ + /* + * Set some registers to what they should be, + * if for no other reason than to initialize our + * software register copies. + */ + CHECK_ERROR(pmic_write(REG_MC34704_GENERAL2, 0x09)); + CHECK_ERROR(pmic_write(REG_MC34704_VGSET1, 0)); + CHECK_ERROR(pmic_write(REG_MC34704_REG2SET1, 0)); + CHECK_ERROR(pmic_write(REG_MC34704_REG3SET1, 0)); + CHECK_ERROR(pmic_write(REG_MC34704_REG4SET1, 0)); + CHECK_ERROR(pmic_write(REG_MC34704_REG5SET1, 0)); + + return PMIC_SUCCESS; +} + +static int __devinit is_chip_onboard(struct i2c_client *client) +{ + int val; + + /* + * This PMIC has no version or ID register, so just see + * if it ACK's and returns 0 on some write-only register as + * evidence of its presence. + */ + val = i2c_smbus_read_byte_data(client, REG_MC34704_GENERAL2); + if (val != 0) + return -1; + + return 0; +} + +static int __devinit pmic_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct mc34704 *mc34704; + struct mc34704_platform_data *plat_data = client->dev.platform_data; + + if (!plat_data || !plat_data->init) + return -ENODEV; + + ret = is_chip_onboard(client); + + if (ret == -1) + return -ENODEV; + + mc34704 = kzalloc(sizeof(struct mc34704), GFP_KERNEL); + if (mc34704 == NULL) + return -ENOMEM; + + i2c_set_clientdata(client, mc34704); + mc34704->dev = &client->dev; + mc34704->i2c_client = client; + + mc34704_client = client; + + /* Initialize the PMIC event handling */ + pmic_event_list_init(); + + /* Initialize PMI registers */ + if (pmic_init_registers() != PMIC_SUCCESS) + return PMIC_ERROR; + + ret = plat_data->init(mc34704); + if (ret != 0) + return PMIC_ERROR; + + dev_info(&client->dev, "Loaded\n"); + + return PMIC_SUCCESS; +} + +static int pmic_remove(struct i2c_client *client) +{ + return 0; +} + +static int pmic_suspend(struct i2c_client *client, pm_message_t state) +{ + return 0; +} + +static int pmic_resume(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id mc34704_id[] = { + {"mc34704", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mc34704_id); + +static struct i2c_driver pmic_driver = { + .driver = { + .name = "mc34704", + .bus = NULL, + }, + .probe = pmic_probe, + .remove = pmic_remove, + .suspend = pmic_suspend, + .resume = pmic_resume, + .id_table = mc34704_id, +}; + +static int __init pmic_init(void) +{ + return i2c_add_driver(&pmic_driver); +} + +static void __exit pmic_exit(void) +{ + i2c_del_driver(&pmic_driver); +} + +/* + * Module entry points + */ +subsys_initcall_sync(pmic_init); +module_exit(pmic_exit); + +MODULE_DESCRIPTION("MC34704 PMIC driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/core/pmic-dev.c b/drivers/mxc/pmic/core/pmic-dev.c new file mode 100644 index 000000000000..7c457db47b4d --- /dev/null +++ b/drivers/mxc/pmic/core/pmic-dev.c @@ -0,0 +1,316 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All rights reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic-dev.c + * @brief This provides /dev interface to the user program. They make it + * possible to have user-space programs use or control PMIC. Mainly its + * useful for notifying PMIC events to user-space programs. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PMIC_NAME "pmic" +#define CIRC_BUF_MAX 16 + +static int pmic_major; +static struct class *pmic_class; +static struct fasync_struct *pmic_dev_queue; + +static DECLARE_MUTEX(event_mutex); +static struct circ_buf pmic_events; + +static void callbackfn(void *event) +{ + printk(KERN_INFO "\n\n DETECTED PMIC EVENT : %d\n\n", + (unsigned int)event); +} + +static void user_notify_callback(void *event) +{ + down(&event_mutex); + if (CIRC_SPACE(pmic_events.head, pmic_events.tail, CIRC_BUF_MAX)) { + pmic_events.buf[pmic_events.head] = (int)event; + pmic_events.head = (pmic_events.head + 1) & (CIRC_BUF_MAX - 1); + } else { + pr_info("Failed to notify event to the user\n"); + } + up(&event_mutex); + + kill_fasync(&pmic_dev_queue, SIGIO, POLL_IN); +} + +/*! + * This function implements IOCTL controls on a PMIC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_dev_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + register_info reg_info; + pmic_event_callback_t event_sub; + type_event event = EVENT_NB; + int ret = 0; + + if (_IOC_TYPE(cmd) != 'P') + return -ENOTTY; + + switch (cmd) { + case PMIC_READ_REG: + if (copy_from_user(®_info, (register_info *) arg, + sizeof(register_info))) { + return -EFAULT; + } + ret = + pmic_read_reg(reg_info.reg, &(reg_info.reg_value), + 0x00ffffff); + pr_debug("read reg %d %x\n", reg_info.reg, reg_info.reg_value); + if (copy_to_user((register_info *) arg, ®_info, + sizeof(register_info))) { + return -EFAULT; + } + break; + + case PMIC_WRITE_REG: + if (copy_from_user(®_info, (register_info *) arg, + sizeof(register_info))) { + return -EFAULT; + } + ret = + pmic_write_reg(reg_info.reg, reg_info.reg_value, + 0x00ffffff); + pr_debug("write reg %d %x\n", reg_info.reg, reg_info.reg_value); + if (copy_to_user((register_info *) arg, ®_info, + sizeof(register_info))) { + return -EFAULT; + } + break; + + case PMIC_SUBSCRIBE: + if (get_user(event, (int __user *)arg)) { + return -EFAULT; + } + event_sub.func = callbackfn; + event_sub.param = (void *)event; + ret = pmic_event_subscribe(event, event_sub); + pr_debug("subscribe done\n"); + break; + + case PMIC_UNSUBSCRIBE: + if (get_user(event, (int __user *)arg)) { + return -EFAULT; + } + event_sub.func = callbackfn; + event_sub.param = (void *)event; + ret = pmic_event_unsubscribe(event, event_sub); + pr_debug("unsubscribe done\n"); + break; + + case PMIC_NOTIFY_USER: + if (get_user(event, (int __user *)arg)) { + return -EFAULT; + } + event_sub.func = user_notify_callback; + event_sub.param = (void *)event; + ret = pmic_event_subscribe(event, event_sub); + break; + + case PMIC_GET_NOTIFY: + down(&event_mutex); + if (CIRC_CNT(pmic_events.head, pmic_events.tail, CIRC_BUF_MAX)) { + event = (int)pmic_events.buf[pmic_events.tail]; + pmic_events.tail = (pmic_events.tail + 1) & (CIRC_BUF_MAX - 1); + } else { + pr_info("No valid notified event\n"); + } + up(&event_mutex); + + if (put_user(event, (int __user *)arg)) { + return -EFAULT; + } + break; + + default: + printk(KERN_ERR "%d unsupported ioctl command\n", (int)cmd); + return -EINVAL; + } + + return ret; +} + +/*! + * This function implements the open method on a PMIC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_dev_open(struct inode *inode, struct file *file) +{ + pr_debug("open\n"); + return PMIC_SUCCESS; +} + +/*! + * This function implements the release method on a PMIC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * + * @return This function returns 0. + */ +static int pmic_dev_free(struct inode *inode, struct file *file) +{ + pr_debug("free\n"); + return PMIC_SUCCESS; +} + +static int pmic_dev_fasync(int fd, struct file *filp, int mode) +{ + return fasync_helper(fd, filp, mode, &pmic_dev_queue); +} + +/*! + * This structure defines file operations for a PMIC device. + */ +static struct file_operations pmic_fops = { + /*! + * the owner + */ + .owner = THIS_MODULE, + /*! + * the ioctl operation + */ + .ioctl = pmic_dev_ioctl, + /*! + * the open operation + */ + .open = pmic_dev_open, + /*! + * the release operation + */ + .release = pmic_dev_free, + /*! + * the release operation + */ + .fasync = pmic_dev_fasync, +}; + +/*! + * This function implements the init function of the PMIC char device. + * This function is called when the module is loaded. It registers + * the character device for PMIC to be used by user-space programs. + * + * @return This function returns 0. + */ +static int __init pmic_dev_init(void) +{ + int ret = 0; + struct device *pmic_device; + pmic_version_t pmic_ver; + + pmic_ver = pmic_get_version(); + if (pmic_ver.revision < 0) { + printk(KERN_ERR "No PMIC device found\n"); + return -ENODEV; + } + + pmic_major = register_chrdev(0, PMIC_NAME, &pmic_fops); + if (pmic_major < 0) { + printk(KERN_ERR "unable to get a major for pmic\n"); + return pmic_major; + } + + pmic_class = class_create(THIS_MODULE, PMIC_NAME); + if (IS_ERR(pmic_class)) { + printk(KERN_ERR "Error creating pmic class.\n"); + ret = PMIC_ERROR; + goto err; + } + + pmic_device = device_create(pmic_class, NULL, MKDEV(pmic_major, 0), NULL, + PMIC_NAME); + if (IS_ERR(pmic_device)) { + printk(KERN_ERR "Error creating pmic class device.\n"); + ret = PMIC_ERROR; + goto err1; + } + + pmic_events.buf = kmalloc(CIRC_BUF_MAX * sizeof(char), GFP_KERNEL); + if (NULL == pmic_events.buf) { + ret = -ENOMEM; + goto err2; + } + pmic_events.head = pmic_events.tail = 0; + + printk(KERN_INFO "PMIC Character device: successfully loaded\n"); + return ret; + err2: + device_destroy(pmic_class, MKDEV(pmic_major, 0)); + err1: + class_destroy(pmic_class); + err: + unregister_chrdev(pmic_major, PMIC_NAME); + return ret; + +} + +/*! + * This function implements the exit function of the PMIC character device. + * This function is called when the module is unloaded. It unregisters + * the PMIC character device. + * + */ +static void __exit pmic_dev_exit(void) +{ + device_destroy(pmic_class, MKDEV(pmic_major, 0)); + class_destroy(pmic_class); + + unregister_chrdev(pmic_major, PMIC_NAME); + + printk(KERN_INFO "PMIC Character device: successfully unloaded\n"); +} + +/* + * Module entry points + */ + +module_init(pmic_dev_init); +module_exit(pmic_dev_exit); + +MODULE_DESCRIPTION("PMIC Protocol /dev entries driver"); +MODULE_AUTHOR("FreeScale"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/core/pmic.h b/drivers/mxc/pmic/core/pmic.h new file mode 100644 index 000000000000..d4ba34786888 --- /dev/null +++ b/drivers/mxc/pmic/core/pmic.h @@ -0,0 +1,138 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __PMIC_H__ +#define __PMIC_H__ + + /*! + * @file pmic.h + * @brief This file contains prototypes of all the functions to be + * defined for each PMIC chip. The implementation of these may differ + * from PMIC chip to PMIC chip. + * + * @ingroup PMIC_CORE + */ + +#include + +#define MAX_ACTIVE_EVENTS 10 + +/*! + * This structure is a way for the PMIC core driver to define their own + * \b spi_device structure. This structure includes the core \b spi_device + * structure that is provided by Linux SPI Framework/driver as an + * element and may contain other elements that are required by core driver. + */ +struct mxc_pmic { + /*! + * Master side proxy for an SPI slave device(PMIC) + */ + struct spi_device *spi; +}; + +/*! + * This function is called to transfer data to PMIC on SPI. + * + * @param spi the SPI slave device(PMIC) + * @param buf the pointer to the data buffer + * @param len the length of the data to be transferred + * + * @return Returns 0 on success -1 on failure. + */ +static inline int spi_rw(struct spi_device *spi, u8 * buf, size_t len) +{ + struct spi_transfer t = { + .tx_buf = (const void *)buf, + .rx_buf = buf, + .len = len, + .cs_change = 0, + .delay_usecs = 0, + }; + struct spi_message m; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + if (spi_sync(spi, &m) != 0 || m.status != 0) + return PMIC_ERROR; + return len - m.actual_length; +} + +/*! + * This function returns the PMIC version in system. + * + * @param ver pointer to the pmic_version_t structure + * + * @return This function returns PMIC version. + */ +void pmic_get_revision(pmic_version_t *ver); + +/*! + * This function initializes the SPI device parameters for this PMIC. + * + * @param spi the SPI slave device(PMIC) + * + * @return None + */ +int pmic_spi_setup(struct spi_device *spi); + +/*! + * This function initializes the PMIC registers. + * + * @return None + */ +int pmic_init_registers(void); + +/*! + * This function reads the interrupt status registers of PMIC + * and determine the current active events. + * + * @param active_events array pointer to be used to return active + * event numbers. + * + * @return This function returns PMIC version. + */ +unsigned int pmic_get_active_events(unsigned int *active_events); + +/*! + * This function sets a bit in mask register of pmic to disable an event IT. + * + * @param event the event to be masked + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +int pmic_event_mask(type_event event); + +/*! + * This function unsets a bit in mask register of pmic to unmask an event IT. + * + * @param event the event to be unmasked + * + * @return This function returns PMIC_SUCCESS on SUCCESS, error on FAILURE. + */ +int pmic_event_unmask(type_event event); + +#ifdef CONFIG_MXC_PMIC_FIXARB +extern PMIC_STATUS pmic_fix_arbitration(struct spi_device *spi); +#else +static inline PMIC_STATUS pmic_fix_arbitration(struct spi_device *spi) +{ + return PMIC_SUCCESS; +} +#endif + +void *pmic_alloc_data(struct device *dev); + +int pmic_start_event_thread(int irq_num); + +void pmic_stop_event_thread(void); + +#endif /* __PMIC_H__ */ diff --git a/drivers/mxc/pmic/core/pmic_common.c b/drivers/mxc/pmic/core/pmic_common.c new file mode 100644 index 000000000000..7e53121f12b8 --- /dev/null +++ b/drivers/mxc/pmic/core/pmic_common.c @@ -0,0 +1,131 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_common.c + * @brief This is the common file for the PMIC Core/Protocol driver. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "pmic.h" + +/* + * Global variables + */ +pmic_version_t mxc_pmic_version; +unsigned int active_events[MAX_ACTIVE_EVENTS]; + + +static struct completion event_completion; +static struct task_struct *tstask; + +static int pmic_event_thread_func(void *v) +{ + unsigned int loop; + unsigned int count = 0; + unsigned int irq = (int)v; + + while (1) { + wait_for_completion_interruptible( + &event_completion); + if (kthread_should_stop()) + break; + + count = pmic_get_active_events( + active_events); + pr_debug("active events number %d\n", count); + + do { + for (loop = 0; loop < count; loop++) + pmic_event_callback(active_events[loop]); + + count = pmic_get_active_events(active_events); + + } while (count != 0); + enable_irq(irq); + } + + return 0; +} + +int pmic_start_event_thread(int irq_num) +{ + int ret = 0; + + if (tstask) + return ret; + + init_completion(&event_completion); + + tstask = kthread_run(pmic_event_thread_func, + (void *)irq_num, "pmic-event-thread"); + ret = IS_ERR(tstask) ? -1 : 0; + if (IS_ERR(tstask)) + tstask = NULL; + return ret; +} + +void pmic_stop_event_thread(void) +{ + if (tstask) { + complete(&event_completion); + kthread_stop(tstask); + } +} + +/*! + * This function is called when pmic interrupt occurs on the processor. + * It is the interrupt handler for the pmic module. + * + * @param irq the irq number + * @param dev_id the pointer on the device + * + * @return The function returns IRQ_HANDLED when handled. + */ +irqreturn_t pmic_irq_handler(int irq, void *dev_id) +{ + disable_irq_nosync(irq); + complete(&event_completion); + + return IRQ_HANDLED; +} + +/*! + * This function is used to determine the PMIC type and its revision. + * + * @return Returns the PMIC type and its revision. + */ + +pmic_version_t pmic_get_version(void) +{ + return mxc_pmic_version; +} +EXPORT_SYMBOL(pmic_get_version); diff --git a/drivers/mxc/pmic/core/pmic_core_i2c.c b/drivers/mxc/pmic/core/pmic_core_i2c.c new file mode 100644 index 000000000000..8dfec5ad4976 --- /dev/null +++ b/drivers/mxc/pmic/core/pmic_core_i2c.c @@ -0,0 +1,348 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_core_i2c.c + * @brief This is the main file for the PMIC Core/Protocol driver. i2c + * should be providing the interface between the PMIC and the MCU. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pmic.h" + +#define MC13892_GENERATION_ID_LSH 6 +#define MC13892_IC_ID_LSH 13 + +#define MC13892_GENERATION_ID_WID 3 +#define MC13892_IC_ID_WID 6 + +#define MC13892_GEN_ID_VALUE 0x7 +#define MC13892_IC_ID_VALUE 1 + +/* + * Global variables + */ +struct i2c_client *mc13892_client; + +extern pmic_version_t mxc_pmic_version; +extern irqreturn_t pmic_irq_handler(int irq, void *dev_id); +/* + * Platform device structure for PMIC client drivers + */ +static struct platform_device adc_ldm = { + .name = "pmic_adc", + .id = 1, +}; +static struct platform_device battery_ldm = { + .name = "pmic_battery", + .id = 1, +}; +static struct platform_device power_ldm = { + .name = "pmic_power", + .id = 1, +}; +static struct platform_device rtc_ldm = { + .name = "pmic_rtc", + .id = 1, +}; +static struct platform_device light_ldm = { + .name = "pmic_light", + .id = 1, +}; +static struct platform_device rleds_ldm = { + .name = "pmic_leds", + .id = 'r', +}; +static struct platform_device gleds_ldm = { + .name = "pmic_leds", + .id = 'g', +}; +static struct platform_device bleds_ldm = { + .name = "pmic_leds", + .id = 'b', +}; + +static void pmic_pdev_register(struct device *dev) +{ + platform_device_register(&adc_ldm); + + if (!cpu_is_mx53()) + platform_device_register(&battery_ldm); + + platform_device_register(&rtc_ldm); + platform_device_register(&power_ldm); + platform_device_register(&light_ldm); + platform_device_register(&rleds_ldm); + platform_device_register(&gleds_ldm); + platform_device_register(&bleds_ldm); +} + +/*! + * This function unregisters platform device structures for + * PMIC client drivers. + */ +static void pmic_pdev_unregister(void) +{ + platform_device_unregister(&adc_ldm); + platform_device_unregister(&battery_ldm); + platform_device_unregister(&rtc_ldm); + platform_device_unregister(&power_ldm); + platform_device_unregister(&light_ldm); +} + +static int __devinit is_chip_onboard(struct i2c_client *client) +{ + unsigned int ret = 0; + + /*bind the right device to the driver */ + if (pmic_i2c_24bit_read(client, REG_IDENTIFICATION, &ret) == -1) + return -1; + + if (MC13892_GEN_ID_VALUE != BITFEXT(ret, MC13892_GENERATION_ID)) { + /*compare the address value */ + dev_err(&client->dev, + "read generation ID 0x%x is not equal to 0x%x!\n", + BITFEXT(ret, MC13892_GENERATION_ID), + MC13892_GEN_ID_VALUE); + return -1; + } + + return 0; +} + +static ssize_t mc13892_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i, value; + int offset = (REG_TEST4 + 1) / 4; + + for (i = 0; i < offset; i++) { + pmic_read(i, &value); + pr_info("reg%02d: %06x\t\t", i, value); + pmic_read(i + offset, &value); + pr_info("reg%02d: %06x\t\t", i + offset, value); + pmic_read(i + offset * 2, &value); + pr_info("reg%02d: %06x\t\t", i + offset * 2, value); + pmic_read(i + offset * 3, &value); + pr_info("reg%02d: %06x\n", i + offset * 3, value); + } + + return 0; +} + +static ssize_t mc13892_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int reg, value, ret; + char *p; + + reg = simple_strtoul(buf, NULL, 10); + + p = NULL; + p = memchr(buf, ' ', count); + + if (p == NULL) { + pmic_read(reg, &value); + pr_debug("reg%02d: %06x\n", reg, value); + return count; + } + + p += 1; + + value = simple_strtoul(p, NULL, 16); + + ret = pmic_write(reg, value); + if (ret == 0) + pr_debug("write reg%02d: %06x\n", reg, value); + else + pr_debug("register update failed\n"); + + return count; +} + +static struct device_attribute mc13892_dev_attr = { + .attr = { + .name = "mc13892_ctl", + .mode = S_IRUSR | S_IWUSR, + }, + .show = mc13892_show, + .store = mc13892_store, +}; + +static int __devinit pmic_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + int pmic_irq; + struct mc13892 *mc13892; + struct mc13892_platform_data *plat_data = client->dev.platform_data; + + ret = is_chip_onboard(client); + if (ret == -1) + return -ENODEV; + + mc13892 = kzalloc(sizeof(struct mc13892), GFP_KERNEL); + if (mc13892 == NULL) + return -ENOMEM; + + i2c_set_clientdata(client, mc13892); + mc13892->dev = &client->dev; + mc13892->i2c_client = client; + + /* so far, we got matched chip on board */ + + mc13892_client = client; + + /* Initialize the PMIC event handling */ + pmic_event_list_init(); + + /* Initialize GPIO for PMIC Interrupt */ + gpio_pmic_active(); + + /* Get the PMIC Version */ + pmic_get_revision(&mxc_pmic_version); + if (mxc_pmic_version.revision < 0) { + dev_err((struct device *)client, + "PMIC not detected!!! Access Failed\n"); + return -ENODEV; + } else { + dev_dbg((struct device *)client, + "Detected pmic core IC version number is %d\n", + mxc_pmic_version.revision); + } + + /* Initialize the PMIC parameters */ + ret = pmic_init_registers(); + if (ret != PMIC_SUCCESS) + return PMIC_ERROR; + + pmic_irq = (int)(client->irq); + if (pmic_irq == 0) + return PMIC_ERROR; + + ret = pmic_start_event_thread(pmic_irq); + if (ret) { + pr_err("mc13892 pmic driver init: \ + fail to start event thread\n"); + return PMIC_ERROR; + } + + /* Set and install PMIC IRQ handler */ + + set_irq_type(pmic_irq, IRQF_TRIGGER_HIGH); + + ret = + request_irq(pmic_irq, pmic_irq_handler, 0, "PMIC_IRQ", + 0); + + if (ret) { + dev_err(&client->dev, "request irq %d error!\n", pmic_irq); + return ret; + } + enable_irq_wake(pmic_irq); + + if (plat_data && plat_data->init) { + ret = plat_data->init(mc13892); + if (ret != 0) + return PMIC_ERROR; + } + + ret = device_create_file(&client->dev, &mc13892_dev_attr); + if (ret) + dev_err(&client->dev, "create device file failed!\n"); + + pmic_pdev_register(&client->dev); + + dev_info(&client->dev, "Loaded\n"); + + return PMIC_SUCCESS; +} + +static int pmic_remove(struct i2c_client *client) +{ + int pmic_irq = (int)(client->irq); + + pmic_stop_event_thread(); + free_irq(pmic_irq, 0); + pmic_pdev_unregister(); + return 0; +} + +static int pmic_suspend(struct i2c_client *client, pm_message_t state) +{ + return 0; +} + +static int pmic_resume(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id mc13892_id[] = { + {"mc13892", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, mc13892_id); + +static struct i2c_driver pmic_driver = { + .driver = { + .name = "mc13892", + .bus = NULL, + }, + .probe = pmic_probe, + .remove = pmic_remove, + .suspend = pmic_suspend, + .resume = pmic_resume, + .id_table = mc13892_id, +}; + +static int __init pmic_init(void) +{ + return i2c_add_driver(&pmic_driver); +} + +static void __exit pmic_exit(void) +{ + i2c_del_driver(&pmic_driver); +} + +/* + * Module entry points + */ +subsys_initcall_sync(pmic_init); +module_exit(pmic_exit); + +MODULE_DESCRIPTION("Core/Protocol driver for PMIC"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/core/pmic_core_spi.c b/drivers/mxc/pmic/core/pmic_core_spi.c new file mode 100644 index 000000000000..5461dbe3f0f0 --- /dev/null +++ b/drivers/mxc/pmic/core/pmic_core_spi.c @@ -0,0 +1,303 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_core_spi.c + * @brief This is the main file for the PMIC Core/Protocol driver. SPI + * should be providing the interface between the PMIC and the MCU. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "pmic.h" + +/* + * Static functions + */ +static void pmic_pdev_register(void); +static void pmic_pdev_unregister(void); + +/* + * Platform device structure for PMIC client drivers + */ +static struct platform_device adc_ldm = { + .name = "pmic_adc", + .id = 1, +}; +static struct platform_device battery_ldm = { + .name = "pmic_battery", + .id = 1, +}; +static struct platform_device power_ldm = { + .name = "pmic_power", + .id = 1, +}; +static struct platform_device rtc_ldm = { + .name = "pmic_rtc", + .id = 1, +}; +static struct platform_device light_ldm = { + .name = "pmic_light", + .id = 1, +}; +static struct platform_device rleds_ldm = { + .name = "pmic_leds", + .id = 'r', +}; +static struct platform_device gleds_ldm = { + .name = "pmic_leds", + .id = 'g', +}; +static struct platform_device bleds_ldm = { + .name = "pmic_leds", + .id = 'b', +}; + +/* + * External functions + */ +extern void pmic_event_list_init(void); +extern void pmic_event_callback(type_event event); +extern void gpio_pmic_active(void); +extern irqreturn_t pmic_irq_handler(int irq, void *dev_id); +extern pmic_version_t mxc_pmic_version; + +/*! + * This function registers platform device structures for + * PMIC client drivers. + */ +static void pmic_pdev_register(void) +{ + platform_device_register(&adc_ldm); + platform_device_register(&battery_ldm); + platform_device_register(&rtc_ldm); + platform_device_register(&power_ldm); + platform_device_register(&light_ldm); + platform_device_register(&rleds_ldm); + platform_device_register(&gleds_ldm); + platform_device_register(&bleds_ldm); +} + +/*! + * This function unregisters platform device structures for + * PMIC client drivers. + */ +static void pmic_pdev_unregister(void) +{ + platform_device_unregister(&adc_ldm); + platform_device_unregister(&battery_ldm); + platform_device_unregister(&rtc_ldm); + platform_device_unregister(&power_ldm); + platform_device_unregister(&light_ldm); +} + +/*! + * This function puts the SPI slave device in low-power mode/state. + * + * @param spi the SPI slave device + * @param message the power state to enter + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int pmic_suspend(struct spi_device *spi, pm_message_t message) +{ + return PMIC_SUCCESS; +} + +/*! + * This function brings the SPI slave device back from low-power mode/state. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int pmic_resume(struct spi_device *spi) +{ + return PMIC_SUCCESS; +} + +static struct spi_driver pmic_driver; + +/*! + * This function is called whenever the SPI slave device is detected. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit pmic_probe(struct spi_device *spi) +{ + int ret = 0; + struct pmic_platform_data *plat_data = spi->dev.platform_data; + + /* Initialize the PMIC parameters */ + ret = pmic_spi_setup(spi); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + + /* Initialize the PMIC event handling */ + pmic_event_list_init(); + + /* Initialize GPIO for PMIC Interrupt */ + gpio_pmic_active(); + + /* Get the PMIC Version */ + pmic_get_revision(&mxc_pmic_version); + if (mxc_pmic_version.revision < 0) { + dev_err((struct device *)spi, + "PMIC not detected!!! Access Failed\n"); + return -ENODEV; + } else { + dev_dbg((struct device *)spi, + "Detected pmic core IC version number is %d\n", + mxc_pmic_version.revision); + } + + spi_set_drvdata(spi, pmic_alloc_data(&(spi->dev))); + + /* Initialize the PMIC parameters */ + ret = pmic_init_registers(); + if (ret != PMIC_SUCCESS) { + kfree(spi_get_drvdata(spi)); + spi_set_drvdata(spi, NULL); + return PMIC_ERROR; + } + + ret = pmic_start_event_thread(spi->irq); + if (ret) { + pr_err("mc13892 pmic driver init: \ + fail to start event thread\n"); + kfree(spi_get_drvdata(spi)); + spi_set_drvdata(spi, NULL); + return PMIC_ERROR; + } + + /* Set and install PMIC IRQ handler */ + set_irq_type(spi->irq, IRQF_TRIGGER_HIGH); + ret = request_irq(spi->irq, pmic_irq_handler, 0, "PMIC_IRQ", 0); + if (ret) { + kfree(spi_get_drvdata(spi)); + spi_set_drvdata(spi, NULL); + dev_err((struct device *)spi, "gpio1: irq%d error.", spi->irq); + return ret; + } + + enable_irq_wake(spi->irq); + + if (plat_data && plat_data->init) { + ret = plat_data->init(spi_get_drvdata(spi)); + if (ret != 0) { + kfree(spi_get_drvdata(spi)); + spi_set_drvdata(spi, NULL); + return PMIC_ERROR; + } + } + + power_ldm.dev.platform_data = spi->dev.platform_data; + + pmic_pdev_register(); + + printk(KERN_INFO "Device %s probed\n", dev_name(&spi->dev)); + + return PMIC_SUCCESS; +} + +/*! + * This function is called whenever the SPI slave device is removed. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devexit pmic_remove(struct spi_device *spi) +{ + pmic_stop_event_thread(); + free_irq(spi->irq, 0); + + pmic_pdev_unregister(); + + printk(KERN_INFO "Device %s removed\n", dev_name(&spi->dev)); + + return PMIC_SUCCESS; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct spi_driver pmic_driver = { + .driver = { + .name = "pmic_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = pmic_probe, + .remove = __devexit_p(pmic_remove), + .suspend = pmic_suspend, + .resume = pmic_resume, +}; + +/* + * Initialization and Exit + */ + +/*! + * This function implements the init function of the PMIC device. + * This function is called when the module is loaded. It registers + * the PMIC Protocol driver. + * + * @return This function returns 0. + */ +static int __init pmic_init(void) +{ + return spi_register_driver(&pmic_driver); +} + +/*! + * This function implements the exit function of the PMIC device. + * This function is called when the module is unloaded. It unregisters + * the PMIC Protocol driver. + * + */ +static void __exit pmic_exit(void) +{ + pr_debug("Unregistering the PMIC Protocol Driver\n"); + spi_unregister_driver(&pmic_driver); +} + +/* + * Module entry points + */ +subsys_initcall_sync(pmic_init); +module_exit(pmic_exit); + +MODULE_DESCRIPTION("Core/Protocol driver for PMIC"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/core/pmic_event.c b/drivers/mxc/pmic/core/pmic_event.c new file mode 100644 index 000000000000..c8ffc63a4973 --- /dev/null +++ b/drivers/mxc/pmic/core/pmic_event.c @@ -0,0 +1,236 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_event.c + * @brief This file manage all event of PMIC component. + * + * It contains event subscription, unsubscription and callback + * launch methods implemeted. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pmic.h" + +/*! + * This structure is used to keep a list of subscribed + * callbacks for an event. + */ +typedef struct { + /*! + * Keeps a list of subscribed clients to an event. + */ + struct list_head list; + + /*! + * Callback function with parameter, called when event occurs + */ + pmic_event_callback_t callback; +} pmic_event_callback_list_t; + +/* Create a mutex to be used to prevent concurrent access to the event list */ +static DEFINE_MUTEX(event_mutex); + +/* This is a pointer to the event handler array. It defines the currently + * active set of events and user-defined callback functions. + */ +static struct list_head pmic_events[PMIC_MAX_EVENTS]; + +/*! + * This function initializes event list for PMIC event handling. + * + */ +void pmic_event_list_init(void) +{ + int i; + + for (i = 0; i < PMIC_MAX_EVENTS; i++) { + INIT_LIST_HEAD(&pmic_events[i]); + } + + mutex_init(&event_mutex); + return; +} + +/*! + * This function is used to subscribe on an event. + * + * @param event the event number to be subscribed + * @param callback the callback funtion to be subscribed + * + * @return This function returns 0 on SUCCESS, error on FAILURE. + */ +PMIC_STATUS pmic_event_subscribe(type_event event, + pmic_event_callback_t callback) +{ + pmic_event_callback_list_t *new = NULL; + + pr_debug("Event:%d Subscribe\n", event); + + /* Check whether the event & callback are valid? */ + if (event >= PMIC_MAX_EVENTS) { + pr_debug("Invalid Event:%d\n", event); + return -EINVAL; + } + if (NULL == callback.func) { + pr_debug("Null or Invalid Callback\n"); + return -EINVAL; + } + + /* Create a new linked list entry */ + new = kmalloc(sizeof(pmic_event_callback_list_t), GFP_KERNEL); + if (NULL == new) { + return -ENOMEM; + } + /* Initialize the list node fields */ + new->callback.func = callback.func; + new->callback.param = callback.param; + INIT_LIST_HEAD(&new->list); + + /* Obtain the lock to access the list */ + if (mutex_lock_interruptible(&event_mutex)) { + kfree(new); + return PMIC_SYSTEM_ERROR_EINTR; + } + + /* Unmask the requested event */ + if (list_empty(&pmic_events[event])) { + if (pmic_event_unmask(event) != PMIC_SUCCESS) { + kfree(new); + mutex_unlock(&event_mutex); + return PMIC_ERROR; + } + } + + /* Add this entry to the event list */ + list_add_tail(&new->list, &pmic_events[event]); + + /* Release the lock */ + mutex_unlock(&event_mutex); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to unsubscribe on an event. + * + * @param event the event number to be unsubscribed + * @param callback the callback funtion to be unsubscribed + * + * @return This function returns 0 on SUCCESS, error on FAILURE. + */ +PMIC_STATUS pmic_event_unsubscribe(type_event event, + pmic_event_callback_t callback) +{ + struct list_head *p; + struct list_head *n; + pmic_event_callback_list_t *temp = NULL; + int ret = PMIC_EVENT_NOT_SUBSCRIBED; + + pr_debug("Event:%d Unsubscribe\n", event); + + /* Check whether the event & callback are valid? */ + if (event >= PMIC_MAX_EVENTS) { + pr_debug("Invalid Event:%d\n", event); + return -EINVAL; + } + + if (NULL == callback.func) { + pr_debug("Null or Invalid Callback\n"); + return -EINVAL; + } + + /* Obtain the lock to access the list */ + if (mutex_lock_interruptible(&event_mutex)) { + return PMIC_SYSTEM_ERROR_EINTR; + } + + /* Find the entry in the list */ + list_for_each_safe(p, n, &pmic_events[event]) { + temp = list_entry(p, pmic_event_callback_list_t, list); + if (temp->callback.func == callback.func + && temp->callback.param == callback.param) { + /* Remove the entry from the list */ + list_del(p); + kfree(temp); + ret = PMIC_SUCCESS; + break; + } + } + + /* Unmask the requested event */ + if (list_empty(&pmic_events[event])) { + if (pmic_event_mask(event) != PMIC_SUCCESS) { + ret = PMIC_UNSUBSCRIBE_ERROR; + } + } + + /* Release the lock */ + mutex_unlock(&event_mutex); + + return ret; +} + +/*! + * This function calls all callback of a specific event. + * + * @param event the active event number + * + * @return None + */ +void pmic_event_callback(type_event event) +{ + struct list_head *p; + pmic_event_callback_list_t *temp = NULL; + + /* Obtain the lock to access the list */ + if (mutex_lock_interruptible(&event_mutex)) { + return; + } + + if (list_empty(&pmic_events[event])) { + pr_debug("PMIC Event:%d detected. No callback subscribed\n", + event); + mutex_unlock(&event_mutex); + return; + } + + list_for_each(p, &pmic_events[event]) { + temp = list_entry(p, pmic_event_callback_list_t, list); + temp->callback.func(temp->callback.param); + } + + /* Release the lock */ + mutex_unlock(&event_mutex); + + return; + +} + +EXPORT_SYMBOL(pmic_event_subscribe); +EXPORT_SYMBOL(pmic_event_unsubscribe); diff --git a/drivers/mxc/pmic/core/pmic_external.c b/drivers/mxc/pmic/core/pmic_external.c new file mode 100644 index 000000000000..02318ed959bb --- /dev/null +++ b/drivers/mxc/pmic/core/pmic_external.c @@ -0,0 +1,100 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file pmic_external.c + * @brief This file contains all external functions of PMIC drivers. + * + * @ingroup PMIC_CORE + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include + +#include +#include + +/* + * External Functions + */ +extern int pmic_read(int reg_num, unsigned int *reg_val); +extern int pmic_write(int reg_num, const unsigned int reg_val); + +/*! + * This function is called by PMIC clients to read a register on PMIC. + * + * @param reg number of register + * @param reg_value return value of register + * @param reg_mask Bitmap mask indicating which bits to modify + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_read_reg(int reg, unsigned int *reg_value, + unsigned int reg_mask) +{ + int ret = 0; + unsigned int temp = 0; + + ret = pmic_read(reg, &temp); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + *reg_value = (temp & reg_mask); + + pr_debug("Read REG[ %d ] = 0x%x\n", reg, *reg_value); + + return ret; +} + +/*! + * This function is called by PMIC clients to write a register on PMIC. + * + * @param reg number of register + * @param reg_value New value of register + * @param reg_mask Bitmap mask indicating which bits to modify + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_write_reg(int reg, unsigned int reg_value, + unsigned int reg_mask) +{ + int ret = 0; + unsigned int temp = 0; + + ret = pmic_read(reg, &temp); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + temp = (temp & (~reg_mask)) | reg_value; +#ifdef CONFIG_MXC_PMIC_MC13783 + if (reg == REG_POWER_MISCELLANEOUS) + temp &= 0xFFFE7FFF; +#endif + ret = pmic_write(reg, temp); + if (ret != PMIC_SUCCESS) { + return PMIC_ERROR; + } + + pr_debug("Write REG[ %d ] = 0x%x\n", reg, reg_value); + + return ret; +} + +EXPORT_SYMBOL(pmic_read_reg); +EXPORT_SYMBOL(pmic_write_reg); diff --git a/drivers/mxc/pmic/mc13783/Kconfig b/drivers/mxc/pmic/mc13783/Kconfig new file mode 100644 index 000000000000..02496c624e2e --- /dev/null +++ b/drivers/mxc/pmic/mc13783/Kconfig @@ -0,0 +1,55 @@ +# +# PMIC Modules configuration +# + +config MXC_MC13783_ADC + tristate "MC13783 ADC support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 ADC module driver. This module provides kernel API + for the ADC system of MC13783. + It controls also the touch screen interface. + If you want MC13783 ADC support, you should say Y here + +config MXC_MC13783_AUDIO + tristate "MC13783 Audio support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 audio module driver. This module provides kernel API + for audio part of MC13783. + If you want MC13783 audio support, you should say Y here +config MXC_MC13783_RTC + tristate "MC13783 Real Time Clock (RTC) support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 RTC module driver. This module provides kernel API + for RTC part of MC13783. + If you want MC13783 RTC support, you should say Y here +config MXC_MC13783_LIGHT + tristate "MC13783 Light and Backlight support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 Light module driver. This module provides kernel API + for led and backlight control part of MC13783. + If you want MC13783 Light support, you should say Y here +config MXC_MC13783_BATTERY + tristate "MC13783 Battery API support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 battery module driver. This module provides kernel API + for battery control part of MC13783. + If you want MC13783 battery support, you should say Y here +config MXC_MC13783_CONNECTIVITY + tristate "MC13783 Connectivity API support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 connectivity module driver. This module provides kernel API + for USB/RS232 connectivity control part of MC13783. + If you want MC13783 connectivity support, you should say Y here +config MXC_MC13783_POWER + tristate "MC13783 Power API support" + depends on MXC_PMIC_MC13783 + ---help--- + This is the MC13783 power and supplies module driver. This module provides kernel API + for power and regulator control part of MC13783. + If you want MC13783 power support, you should say Y here diff --git a/drivers/mxc/pmic/mc13783/Makefile b/drivers/mxc/pmic/mc13783/Makefile new file mode 100644 index 000000000000..7bbba23f5ab9 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the mc13783 pmic drivers. +# + +obj-$(CONFIG_MXC_MC13783_ADC) += pmic_adc-mod.o +obj-$(CONFIG_MXC_MC13783_AUDIO) += pmic_audio-mod.o +obj-$(CONFIG_MXC_MC13783_RTC) += pmic_rtc-mod.o +obj-$(CONFIG_MXC_MC13783_LIGHT) += pmic_light-mod.o +obj-$(CONFIG_MXC_MC13783_BATTERY) += pmic_battery-mod.o +obj-$(CONFIG_MXC_MC13783_CONNECTIVITY) += pmic_convity-mod.o +obj-$(CONFIG_MXC_MC13783_POWER) += pmic_power-mod.o +pmic_adc-mod-objs := pmic_adc.o +pmic_audio-mod-objs := pmic_audio.o +pmic_rtc-mod-objs := pmic_rtc.o +pmic_light-mod-objs := pmic_light.o +pmic_battery-mod-objs := pmic_battery.o +pmic_convity-mod-objs := pmic_convity.o +pmic_power-mod-objs := pmic_power.o diff --git a/drivers/mxc/pmic/mc13783/pmic_adc.c b/drivers/mxc/pmic/mc13783/pmic_adc.c new file mode 100644 index 000000000000..482d0ee08e39 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_adc.c @@ -0,0 +1,1541 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_adc.c + * @brief This is the main file of PMIC(mc13783) ADC driver. + * + * @ingroup PMIC_ADC + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core/pmic.h" +#include "pmic_adc_defs.h" + +#define NB_ADC_REG 5 + +static int pmic_adc_major; + +/* internal function */ +static void callback_tsi(void *); +static void callback_adcdone(void *); +static void callback_adcbisdone(void *); +static void callback_adc_comp_high(void *); + +/*! + * Number of users waiting in suspendq + */ +static int swait; + +/*! + * To indicate whether any of the adc devices are suspending + */ +static int suspend_flag; + +/*! + * The suspendq is used by blocking application calls + */ +static wait_queue_head_t suspendq; + +static struct class *pmic_adc_class; + +/* + * ADC mc13783 API + */ +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_adc_init); +EXPORT_SYMBOL(pmic_adc_deinit); +EXPORT_SYMBOL(pmic_adc_convert); +EXPORT_SYMBOL(pmic_adc_convert_8x); +EXPORT_SYMBOL(pmic_adc_convert_multichnnel); +EXPORT_SYMBOL(pmic_adc_set_touch_mode); +EXPORT_SYMBOL(pmic_adc_get_touch_mode); +EXPORT_SYMBOL(pmic_adc_get_touch_sample); +EXPORT_SYMBOL(pmic_adc_get_battery_current); +EXPORT_SYMBOL(pmic_adc_active_comparator); +EXPORT_SYMBOL(pmic_adc_deactive_comparator); + +static DECLARE_COMPLETION(adcdone_it); +static DECLARE_COMPLETION(adcbisdone_it); +static DECLARE_COMPLETION(adc_tsi); +static pmic_event_callback_t tsi_event; +static pmic_event_callback_t event_adc; +static pmic_event_callback_t event_adc_bis; +static pmic_event_callback_t adc_comp_h; +static bool data_ready_adc_1; +static bool data_ready_adc_2; +static bool adc_ts; +static bool wait_ts; +static bool monitor_en; +static bool monitor_adc; +static t_check_mode wcomp_mode; +static DECLARE_MUTEX(convert_mutex); + +void (*monitoring_cb) (void); /*call back to be called when event is detected. */ + +static DECLARE_WAIT_QUEUE_HEAD(queue_adc_busy); +static t_adc_state adc_dev[2]; + +static unsigned channel_num[] = { + 0, + 1, + 3, + 4, + 2, + 12, + 13, + 14, + 15, + -1, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 7, + 6, + -1, + -1, + -1, + -1, + 5, + 7 +}; + +static bool pmic_adc_ready; + +int is_pmic_adc_ready() +{ + return pmic_adc_ready; +} +EXPORT_SYMBOL(is_pmic_adc_ready); + + +/*! + * This is the suspend of power management for the mc13783 ADC API. + * It supports SAVE and POWER_DOWN state. + * + * @param pdev the device + * @param state the state + * + * @return This function returns 0 if successful. + */ +static int pmic_adc_suspend(struct platform_device *pdev, pm_message_t state) +{ + unsigned int reg_value = 0; + suspend_flag = 1; + CHECK_ERROR(pmic_write_reg(REG_ADC_0, DEF_ADC_0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_2, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_3, DEF_ADC_3, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_4, reg_value, PMIC_ALL_BITS)); + + return 0; +}; + +/*! + * This is the resume of power management for the mc13783 adc API. + * It supports RESTORE state. + * + * @param pdev the device + * + * @return This function returns 0 if successful. + */ +static int pmic_adc_resume(struct platform_device *pdev) +{ + /* nothing for mc13783 adc */ + unsigned int adc_0_reg, adc_1_reg; + suspend_flag = 0; + + /* let interrupt of TSI again */ + adc_0_reg = ADC_WAIT_TSI_0; + CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg, PMIC_ALL_BITS)); + adc_1_reg = ADC_WAIT_TSI_1 | (ADC_BIS * adc_ts); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, PMIC_ALL_BITS)); + + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +}; + +/* + * Call back functions + */ + +/*! + * This is the callback function called on TSI mc13783 event, used in synchronous call. + */ +static void callback_tsi(void *unused) +{ + pr_debug("*** TSI IT mc13783 PMIC_ADC_GET_TOUCH_SAMPLE ***\n"); + if (wait_ts) { + complete(&adc_tsi); + pmic_event_mask(EVENT_TSI); + } +} + +/*! + * This is the callback function called on ADCDone mc13783 event. + */ +static void callback_adcdone(void *unused) +{ + if (data_ready_adc_1) { + complete(&adcdone_it); + } +} + +/*! + * This is the callback function called on ADCDone mc13783 event. + */ +static void callback_adcbisdone(void *unused) +{ + pr_debug("* adcdone bis it callback *\n"); + if (data_ready_adc_2) { + complete(&adcbisdone_it); + } +} + +/*! + * This is the callback function called on mc13783 event. + */ +static void callback_adc_comp_high(void *unused) +{ + pr_debug("* adc comp it high *\n"); + if (wcomp_mode == CHECK_HIGH || wcomp_mode == CHECK_LOW_OR_HIGH) { + /* launch callback */ + if (monitoring_cb != NULL) { + monitoring_cb(); + } + } +} + +/*! + * This function performs filtering and rejection of excessive noise prone + * samples. + * + * @param ts_curr Touch screen value + * + * @return This function returns 0 on success, -1 otherwise. + */ +static int pmic_adc_filter(t_touch_screen *ts_curr) +{ + unsigned int ydiff1, ydiff2, ydiff3, xdiff1, xdiff2, xdiff3; + unsigned int sample_sumx, sample_sumy; + static unsigned int prev_x[FILTLEN], prev_y[FILTLEN]; + int index = 0; + unsigned int y_curr, x_curr; + static int filt_count; + /* Added a variable filt_type to decide filtering at run-time */ + unsigned int filt_type = 0; + + if (ts_curr->contact_resistance == 0) { + ts_curr->x_position = 0; + ts_curr->y_position = 0; + filt_count = 0; + return 0; + } + + ydiff1 = abs(ts_curr->y_position1 - ts_curr->y_position2); + ydiff2 = abs(ts_curr->y_position2 - ts_curr->y_position3); + ydiff3 = abs(ts_curr->y_position1 - ts_curr->y_position3); + if ((ydiff1 > DELTA_Y_MAX) || + (ydiff2 > DELTA_Y_MAX) || (ydiff3 > DELTA_Y_MAX)) { + pr_debug("pmic_adc_filter: Ret pos 1\n"); + return -1; + } + + xdiff1 = abs(ts_curr->x_position1 - ts_curr->x_position2); + xdiff2 = abs(ts_curr->x_position2 - ts_curr->x_position3); + xdiff3 = abs(ts_curr->x_position1 - ts_curr->x_position3); + + if ((xdiff1 > DELTA_X_MAX) || + (xdiff2 > DELTA_X_MAX) || (xdiff3 > DELTA_X_MAX)) { + pr_debug("mc13783_adc_filter: Ret pos 2\n"); + return -1; + } + /* Compute two closer values among the three available Y readouts */ + + if (ydiff1 < ydiff2) { + if (ydiff1 < ydiff3) { + /* Sample 0 & 1 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position2; + } else { + /* Sample 0 & 2 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position3; + } + } else { + if (ydiff2 < ydiff3) { + /* Sample 1 & 2 closest together */ + sample_sumy = ts_curr->y_position2 + + ts_curr->y_position3; + } else { + /* Sample 0 & 2 closest together */ + sample_sumy = ts_curr->y_position1 + + ts_curr->y_position3; + } + } + + /* + * Compute two closer values among the three available X + * readouts + */ + if (xdiff1 < xdiff2) { + if (xdiff1 < xdiff3) { + /* Sample 0 & 1 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position2; + } else { + /* Sample 0 & 2 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position3; + } + } else { + if (xdiff2 < xdiff3) { + /* Sample 1 & 2 closest together */ + sample_sumx = ts_curr->x_position2 + + ts_curr->x_position3; + } else { + /* Sample 0 & 2 closest together */ + sample_sumx = ts_curr->x_position1 + + ts_curr->x_position3; + } + } + /* + * Wait FILTER_MIN_DELAY number of samples to restart + * filtering + */ + if (filt_count < FILTER_MIN_DELAY) { + /* + * Current output is the average of the two closer + * values and no filtering is used + */ + y_curr = (sample_sumy / 2); + x_curr = (sample_sumx / 2); + ts_curr->y_position = y_curr; + ts_curr->x_position = x_curr; + filt_count++; + } else { + if (abs(sample_sumx - (prev_x[0] + prev_x[1])) > + (DELTA_X_MAX * 16)) { + pr_debug("pmic_adc_filter: : Ret pos 3\n"); + return -1; + } + if (abs(sample_sumy - (prev_y[0] + prev_y[1])) > + (DELTA_Y_MAX * 16)) { + return -1; + } + sample_sumy /= 2; + sample_sumx /= 2; + /* Use hard filtering if the sample difference < 10 */ + if ((abs(sample_sumy - prev_y[0]) > 10) || + (abs(sample_sumx - prev_x[0]) > 10)) { + filt_type = 1; + } + + /* + * Current outputs are the average of three previous + * values and the present readout + */ + y_curr = sample_sumy; + for (index = 0; index < FILTLEN; index++) { + if (filt_type == 0) { + y_curr = y_curr + (prev_y[index]); + } else { + y_curr = y_curr + (prev_y[index] / 3); + } + } + if (filt_type == 0) { + y_curr = y_curr >> 2; + } else { + y_curr = y_curr >> 1; + } + ts_curr->y_position = y_curr; + + x_curr = sample_sumx; + for (index = 0; index < FILTLEN; index++) { + if (filt_type == 0) { + x_curr = x_curr + (prev_x[index]); + } else { + x_curr = x_curr + (prev_x[index] / 3); + } + } + if (filt_type == 0) { + x_curr = x_curr >> 2; + } else { + x_curr = x_curr >> 1; + } + ts_curr->x_position = x_curr; + + } + + /* Update previous X and Y values */ + for (index = (FILTLEN - 1); index > 0; index--) { + prev_x[index] = prev_x[index - 1]; + prev_y[index] = prev_y[index - 1]; + } + + /* + * Current output will be the most recent past for the + * next sample + */ + prev_y[0] = y_curr; + prev_x[0] = x_curr; + + return 0; +} + +/*! + * This function implements the open method on a MC13783 ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_adc_open(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + pr_debug("mc13783_adc : mc13783_adc_open()\n"); + return 0; +} + +/*! + * This function implements the release method on a MC13783 ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_adc_free(struct inode *inode, struct file *file) +{ + pr_debug("mc13783_adc : mc13783_adc_free()\n"); + return 0; +} + +/*! + * This function initializes all ADC registers with default values. This + * function also registers the interrupt events. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +int pmic_adc_init(void) +{ + unsigned int reg_value = 0, i = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + for (i = 0; i < ADC_NB_AVAILABLE; i++) { + adc_dev[i] = ADC_FREE; + } + CHECK_ERROR(pmic_write_reg(REG_ADC_0, DEF_ADC_0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_2, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_3, DEF_ADC_3, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_4, reg_value, PMIC_ALL_BITS)); + reg_value = 0x001000; + CHECK_ERROR(pmic_write_reg(REG_ARBITRATION_PERIPHERAL_AUDIO, reg_value, + 0xFFFFFF)); + + data_ready_adc_1 = false; + data_ready_adc_2 = false; + adc_ts = false; + wait_ts = false; + monitor_en = false; + monitor_adc = false; + wcomp_mode = CHECK_LOW; + monitoring_cb = NULL; + /* sub to ADCDone IT */ + event_adc.param = NULL; + event_adc.func = callback_adcdone; + CHECK_ERROR(pmic_event_subscribe(EVENT_ADCDONEI, event_adc)); + + /* sub to ADCDoneBis IT */ + event_adc_bis.param = NULL; + event_adc_bis.func = callback_adcbisdone; + CHECK_ERROR(pmic_event_subscribe(EVENT_ADCBISDONEI, event_adc_bis)); + + /* sub to Touch Screen IT */ + tsi_event.param = NULL; + tsi_event.func = callback_tsi; + CHECK_ERROR(pmic_event_subscribe(EVENT_TSI, tsi_event)); + + /* ADC reading above high limit */ + adc_comp_h.param = NULL; + adc_comp_h.func = callback_adc_comp_high; + CHECK_ERROR(pmic_event_subscribe(EVENT_WHIGHI, adc_comp_h)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables the ADC, de-registers the interrupt events. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_deinit(void) +{ + CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCDONEI, event_adc)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCBISDONEI, event_adc_bis)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_TSI, tsi_event)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_WHIGHI, adc_comp_h)); + + return PMIC_SUCCESS; +} + +/*! + * This function initializes adc_param structure. + * + * @param adc_param Structure to be initialized. + * + * @return This function returns 0 if successful. + */ +int mc13783_adc_init_param(t_adc_param *adc_param) +{ + int i = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + adc_param->delay = 0; + adc_param->conv_delay = false; + adc_param->single_channel = false; + adc_param->group = false; + adc_param->channel_0 = BATTERY_VOLTAGE; + adc_param->channel_1 = BATTERY_VOLTAGE; + adc_param->read_mode = 0; + adc_param->wait_tsi = 0; + adc_param->chrgraw_devide_5 = true; + adc_param->read_ts = false; + adc_param->ts_value.x_position = 0; + adc_param->ts_value.y_position = 0; + adc_param->ts_value.contact_resistance = 0; + for (i = 0; i <= MAX_CHANNEL; i++) { + adc_param->value[i] = 0; + } + return 0; +} + +/*! + * This function starts the convert. + * + * @param adc_param contains all adc configuration and return value. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS mc13783_adc_convert(t_adc_param *adc_param) +{ + bool use_bis = false; + unsigned int adc_0_reg = 0, adc_1_reg = 0, reg_1 = 0, result_reg = + 0, i = 0; + unsigned int result = 0, temp = 0; + pmic_version_t mc13783_ver; + pr_debug("mc13783 ADC - mc13783_adc_convert ....\n"); + if (suspend_flag == 1) { + return -EBUSY; + } + + if (adc_param->wait_tsi) { + /* we need to set ADCEN 1 for TSI interrupt on mc13783 1.x */ + /* configure adc to wait tsi interrupt */ + INIT_COMPLETION(adc_tsi); + pr_debug("mc13783 ADC - pmic_write_reg ....\n"); + /*for ts don't use bis */ + adc_0_reg = 0x001c00 | (ADC_BIS * 0); + pmic_event_unmask(EVENT_TSI); + CHECK_ERROR(pmic_write_reg + (REG_ADC_0, adc_0_reg, PMIC_ALL_BITS)); + /*for ts don't use bis */ + adc_1_reg = 0x200001 | (ADC_BIS * 0); + CHECK_ERROR(pmic_write_reg + (REG_ADC_1, adc_1_reg, PMIC_ALL_BITS)); + pr_debug("wait tsi ....\n"); + wait_ts = true; + wait_for_completion_interruptible(&adc_tsi); + wait_ts = false; + } + if (adc_param->read_ts == false) + down(&convert_mutex); + use_bis = mc13783_adc_request(adc_param->read_ts); + if (use_bis < 0) { + pr_debug("process has received a signal and got interrupted\n"); + return -EINTR; + } + + /* CONFIGURE ADC REG 0 */ + adc_0_reg = 0; + adc_1_reg = 0; + if (adc_param->read_ts == false) { + adc_0_reg = adc_param->read_mode & 0x00003F; + /* add auto inc */ + adc_0_reg |= ADC_INC; + if (use_bis) { + /* add adc bis */ + adc_0_reg |= ADC_BIS; + } + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + if (adc_param->chrgraw_devide_5) { + adc_0_reg |= ADC_CHRGRAW_D5; + } + } + if (adc_param->single_channel) { + adc_1_reg |= ADC_SGL_CH; + } + + if (adc_param->conv_delay) { + adc_1_reg |= ADC_ATO; + } + + if (adc_param->group) { + adc_1_reg |= ADC_ADSEL; + } + + if (adc_param->single_channel) { + adc_1_reg |= ADC_SGL_CH; + } + + adc_1_reg |= (adc_param->channel_0 << ADC_CH_0_POS) & + ADC_CH_0_MASK; + adc_1_reg |= (adc_param->channel_1 << ADC_CH_1_POS) & + ADC_CH_1_MASK; + } else { + adc_0_reg = 0x003c00 | (ADC_BIS * use_bis) | ADC_INC; + } + pr_debug("Write Reg %i = %x\n", REG_ADC_0, adc_0_reg); + /*Change has been made here */ + CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg, + ADC_INC | ADC_BIS | ADC_CHRGRAW_D5 | + 0xfff00ff)); + /* CONFIGURE ADC REG 1 */ + if (adc_param->read_ts == false) { + adc_1_reg |= ADC_NO_ADTRIG; + adc_1_reg |= ADC_EN; + adc_1_reg |= (adc_param->delay << ADC_DELAY_POS) & + ADC_DELAY_MASK; + if (use_bis) { + adc_1_reg |= ADC_BIS; + } + } else { + /* configure and start convert to read x and y position */ + /* configure to read 2 value in channel selection 1 & 2 */ + adc_1_reg = 0x100409 | (ADC_BIS * use_bis) | ADC_NO_ADTRIG; + } + reg_1 = adc_1_reg; + if (use_bis == 0) { + data_ready_adc_1 = false; + adc_1_reg |= ASC_ADC; + data_ready_adc_1 = true; + pr_debug("Write Reg %i = %x\n", REG_ADC_1, adc_1_reg); + INIT_COMPLETION(adcdone_it); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, + ADC_SGL_CH | ADC_ATO | ADC_ADSEL + | ADC_CH_0_MASK | ADC_CH_1_MASK | + ADC_NO_ADTRIG | ADC_EN | + ADC_DELAY_MASK | ASC_ADC | ADC_BIS)); + pr_debug("wait adc done \n"); + wait_for_completion_interruptible(&adcdone_it); + data_ready_adc_1 = false; + } else { + data_ready_adc_2 = false; + adc_1_reg |= ASC_ADC; + data_ready_adc_2 = true; + INIT_COMPLETION(adcbisdone_it); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, 0xFFFFFF)); + temp = 0x800000; + CHECK_ERROR(pmic_write_reg(REG_ADC_3, temp, 0xFFFFFF)); + temp = 0x001000; + pmic_write_reg(REG_ARBITRATION_PERIPHERAL_AUDIO, temp, + 0xFFFFFF); + pr_debug("wait adc done bis\n"); + wait_for_completion_interruptible(&adcbisdone_it); + data_ready_adc_2 = false; + } + /* read result and store in adc_param */ + result = 0; + if (use_bis == 0) { + result_reg = REG_ADC_2; + } else { + result_reg = REG_ADC_4; + } + CHECK_ERROR(pmic_write_reg(REG_ADC_1, 4 << ADC_CH_1_POS, + ADC_CH_0_MASK | ADC_CH_1_MASK)); + + for (i = 0; i <= 3; i++) { + CHECK_ERROR(pmic_read_reg(result_reg, &result, PMIC_ALL_BITS)); + pr_debug("result %i = %x\n", result_reg, result); + adc_param->value[i] = ((result & ADD1_RESULT_MASK) >> 2); + adc_param->value[i + 4] = ((result & ADD2_RESULT_MASK) >> 14); + } + if (adc_param->read_ts) { + adc_param->ts_value.x_position = adc_param->value[2]; + adc_param->ts_value.x_position1 = adc_param->value[0]; + adc_param->ts_value.x_position2 = adc_param->value[1]; + adc_param->ts_value.x_position3 = adc_param->value[2]; + adc_param->ts_value.y_position1 = adc_param->value[3]; + adc_param->ts_value.y_position2 = adc_param->value[4]; + adc_param->ts_value.y_position3 = adc_param->value[5]; + adc_param->ts_value.y_position = adc_param->value[5]; + adc_param->ts_value.contact_resistance = adc_param->value[6]; + + } + + /*if (adc_param->read_ts) { + adc_param->ts_value.x_position = adc_param->value[2]; + adc_param->ts_value.y_position = adc_param->value[5]; + adc_param->ts_value.contact_resistance = adc_param->value[6]; + } */ + mc13783_adc_release(use_bis); + if (adc_param->read_ts == false) + up(&convert_mutex); + + return PMIC_SUCCESS; +} + +/*! + * This function select the required read_mode for a specific channel. + * + * @param channel The channel to be sampled + * + * @return This function returns the requires read_mode + */ +t_reading_mode mc13783_set_read_mode(t_channel channel) +{ + t_reading_mode read_mode = 0; + + switch (channel) { + case LICELL: + read_mode = M_LITHIUM_CELL; + break; + case CHARGE_CURRENT: + read_mode = M_CHARGE_CURRENT; + break; + case BATTERY_CURRENT: + read_mode = M_BATTERY_CURRENT; + break; + case THERMISTOR: + read_mode = M_THERMISTOR; + break; + case DIE_TEMP: + read_mode = M_DIE_TEMPERATURE; + break; + case USB_ID: + read_mode = M_UID; + break; + default: + read_mode = 0; + } + + return read_mode; +} + +/*! + * This function triggers a conversion and returns one sampling result of one + * channel. + * + * @param channel The channel to be sampled + * @param result The pointer to the conversion result. The memory + * should be allocated by the caller of this function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_convert(t_channel channel, unsigned short *result) +{ + t_adc_param adc_param; + PMIC_STATUS ret; + + if (suspend_flag == 1) { + return -EBUSY; + } + + channel = channel_num[channel]; + if (channel == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + mc13783_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert\n"); + adc_param.read_ts = false; + adc_param.read_mode = mc13783_set_read_mode(channel); + + adc_param.single_channel = true; + /* Find the group */ + if ((channel >= 0) && (channel <= 7)) { + adc_param.channel_0 = channel; + adc_param.group = false; + } else if ((channel >= 8) && (channel <= 15)) { + adc_param.channel_0 = channel & 0x07; + adc_param.group = true; + } else { + return PMIC_PARAMETER_ERROR; + } + ret = mc13783_adc_convert(&adc_param); + *result = adc_param.value[0]; + return ret; +} + +/*! + * This function triggers a conversion and returns eight sampling results of + * one channel. + * + * @param channel The channel to be sampled + * @param result The pointer to array to store eight sampling results. + * The memory should be allocated by the caller of this + * function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_convert_8x(t_channel channel, unsigned short *result) +{ + t_adc_param adc_param; + int i; + PMIC_STATUS ret; + if (suspend_flag == 1) { + return -EBUSY; + } + + channel = channel_num[channel]; + + if (channel == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + mc13783_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert_8x\n"); + adc_param.read_ts = false; + adc_param.single_channel = true; + adc_param.read_mode = mc13783_set_read_mode(channel); + if ((channel >= 0) && (channel <= 7)) { + adc_param.channel_0 = channel; + adc_param.channel_1 = channel; + adc_param.group = false; + } else if ((channel >= 8) && (channel <= 15)) { + adc_param.channel_0 = channel & 0x07; + adc_param.channel_1 = channel & 0x07; + adc_param.group = true; + } else { + return PMIC_PARAMETER_ERROR; + } + + ret = mc13783_adc_convert(&adc_param); + for (i = 0; i <= 7; i++) { + result[i] = adc_param.value[i]; + } + return ret; +} + +/*! + * This function triggers a conversion and returns sampling results of each + * specified channel. + * + * @param channels This input parameter is bitmap to specify channels + * to be sampled. + * @param result The pointer to array to store sampling results. + * The memory should be allocated by the caller of this + * function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_convert_multichnnel(t_channel channels, + unsigned short *result) +{ + t_adc_param adc_param; + int i; + PMIC_STATUS ret; + if (suspend_flag == 1) { + return -EBUSY; + } + mc13783_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert_multichnnel\n"); + + channels = channel_num[channels]; + + if (channels == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + + adc_param.read_ts = false; + adc_param.single_channel = false; + if ((channels >= 0) && (channels <= 7)) { + adc_param.channel_0 = channels; + adc_param.channel_1 = ((channels + 4) % 4) + 4; + adc_param.group = false; + } else if ((channels >= 8) && (channels <= 15)) { + channels = channels & 0x07; + adc_param.channel_0 = channels; + adc_param.channel_1 = ((channels + 4) % 4) + 4; + adc_param.group = true; + } else { + return PMIC_PARAMETER_ERROR; + } + adc_param.read_mode = 0x00003f; + adc_param.read_ts = false; + ret = mc13783_adc_convert(&adc_param); + + for (i = 0; i <= 7; i++) { + result[i] = adc_param.value[i]; + } + return ret; +} + +/*! + * This function sets touch screen operation mode. + * + * @param touch_mode Touch screen operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_set_touch_mode(t_touch_mode touch_mode) +{ + if (suspend_flag == 1) { + return -EBUSY; + } + CHECK_ERROR(pmic_write_reg(REG_ADC_0, + BITFVAL(MC13783_ADC0_TS_M, touch_mode), + BITFMASK(MC13783_ADC0_TS_M))); + return PMIC_SUCCESS; +} + +/*! + * This function retrieves the current touch screen operation mode. + * + * @param touch_mode Pointer to the retrieved touch screen operation + * mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_touch_mode(t_touch_mode *touch_mode) +{ + unsigned int value; + if (suspend_flag == 1) { + return -EBUSY; + } + CHECK_ERROR(pmic_read_reg(REG_ADC_0, &value, PMIC_ALL_BITS)); + + *touch_mode = BITFEXT(value, MC13783_ADC0_TS_M); + + return PMIC_SUCCESS; +} + +/*! + * This function retrieves the current touch screen (X,Y) coordinates. + * + * @param touch_sample Pointer to touch sample. + * @param wait indicates whether this call must block or not. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_touch_sample(t_touch_screen *touch_sample, int wait) +{ + if (mc13783_adc_read_ts(touch_sample, wait) != 0) + return PMIC_ERROR; + if (0 == pmic_adc_filter(touch_sample)) + return PMIC_SUCCESS; + else + return PMIC_ERROR; +} + +/*! + * This function read the touch screen value. + * + * @param ts_value return value of touch screen + * @param wait_tsi if true, this function is synchronous (wait in TSI event). + * + * @return This function returns 0. + */ +PMIC_STATUS mc13783_adc_read_ts(t_touch_screen *ts_value, int wait_tsi) +{ + t_adc_param param; + pr_debug("mc13783_adc : mc13783_adc_read_ts\n"); + if (suspend_flag == 1) { + return -EBUSY; + } + if (wait_ts) { + pr_debug("mc13783_adc : error TS busy \n"); + return PMIC_ERROR; + } + mc13783_adc_init_param(¶m); + param.wait_tsi = wait_tsi; + param.read_ts = true; + if (mc13783_adc_convert(¶m) != 0) + return PMIC_ERROR; + /* check if x-y is ok */ + if ((param.ts_value.x_position1 < TS_X_MAX) && + (param.ts_value.x_position1 >= TS_X_MIN) && + (param.ts_value.y_position1 < TS_Y_MAX) && + (param.ts_value.y_position1 >= TS_Y_MIN) && + (param.ts_value.x_position2 < TS_X_MAX) && + (param.ts_value.x_position2 >= TS_X_MIN) && + (param.ts_value.y_position2 < TS_Y_MAX) && + (param.ts_value.y_position2 >= TS_Y_MIN) && + (param.ts_value.x_position3 < TS_X_MAX) && + (param.ts_value.x_position3 >= TS_X_MIN) && + (param.ts_value.y_position3 < TS_Y_MAX) && + (param.ts_value.y_position3 >= TS_Y_MIN)) { + ts_value->x_position = param.ts_value.x_position; + ts_value->x_position1 = param.ts_value.x_position1; + ts_value->x_position2 = param.ts_value.x_position2; + ts_value->x_position3 = param.ts_value.x_position3; + ts_value->y_position = param.ts_value.y_position; + ts_value->y_position1 = param.ts_value.y_position1; + ts_value->y_position2 = param.ts_value.y_position2; + ts_value->y_position3 = param.ts_value.y_position3; + ts_value->contact_resistance = + param.ts_value.contact_resistance + 1; + + } else { + ts_value->x_position = 0; + ts_value->y_position = 0; + ts_value->contact_resistance = 0; + + } + return PMIC_SUCCESS; +} + +/*! + * This function starts a Battery Current mode conversion. + * + * @param mode Conversion mode. + * @param result Battery Current measurement result. + * if \a mode = ADC_8CHAN_1X, the result is \n + * result[0] = (BATTP - BATT_I) \n + * if \a mode = ADC_1CHAN_8X, the result is \n + * result[0] = BATTP \n + * result[1] = BATT_I \n + * result[2] = BATTP \n + * result[3] = BATT_I \n + * result[4] = BATTP \n + * result[5] = BATT_I \n + * result[6] = BATTP \n + * result[7] = BATT_I + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_battery_current(t_conversion_mode mode, + unsigned short *result) +{ + PMIC_STATUS ret; + t_channel channel; + if (suspend_flag == 1) { + return -EBUSY; + } + channel = BATTERY_CURRENT; + if (mode == ADC_8CHAN_1X) { + ret = pmic_adc_convert(channel, result); + } else { + ret = pmic_adc_convert_8x(channel, result); + } + return ret; +} + +/*! + * This function request a ADC. + * + * @return This function returns index of ADC to be used (0 or 1) if successful. + * return -1 if error. + */ +int mc13783_adc_request(bool read_ts) +{ + int adc_index = -1; + if (read_ts != 0) { + /*for ts we use bis=0 */ + if (adc_dev[0] == ADC_USED) + return -1; + /*no wait here */ + adc_dev[0] = ADC_USED; + adc_index = 0; + } else { + /*for other adc use bis = 1 */ + if (adc_dev[1] == ADC_USED) { + return -1; + /*no wait here */ + } + adc_dev[1] = ADC_USED; + adc_index = 1; + } + pr_debug("mc13783_adc : request ADC %d\n", adc_index); + return adc_index; +} + +/*! + * This function release an ADC. + * + * @param adc_index index of ADC to be released. + * + * @return This function returns 0 if successful. + */ +int mc13783_adc_release(int adc_index) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + + pr_debug("mc13783_adc : release ADC %d\n", adc_index); + if ((adc_dev[adc_index] == ADC_MONITORING) || + (adc_dev[adc_index] == ADC_USED)) { + adc_dev[adc_index] = ADC_FREE; + wake_up(&queue_adc_busy); + return 0; + } + return -1; +} + +/*! + * This function initializes monitoring structure. + * + * @param monitor Structure to be initialized. + * + * @return This function returns 0 if successful. + */ +int mc13783_adc_init_monitor_param(t_monitoring_param *monitor) +{ + pr_debug("mc13783_adc : init monitor\n"); + monitor->delay = 0; + monitor->conv_delay = false; + monitor->channel = BATTERY_VOLTAGE; + monitor->read_mode = 0; + monitor->comp_low = 0; + monitor->comp_high = 0; + monitor->group = 0; + monitor->check_mode = CHECK_LOW_OR_HIGH; + monitor->callback = NULL; + return 0; +} + +/*! + * This function actives the comparator. When comparator is active and ADC + * is enabled, the 8th converted value will be digitally compared against the + * window defined by WLOW and WHIGH registers. + * + * @param low Comparison window low threshold (WLOW). + * @param high Comparison window high threshold (WHIGH). + * @param channel The channel to be sampled + * @param callback Callback function to be called when the converted + * value is beyond the comparison window. The callback + * function will pass a parameter of type + * \b t_comp_expection to indicate the reason of + * comparator exception. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_active_comparator(unsigned char low, + unsigned char high, + t_channel channel, + t_comparator_cb callback) +{ + bool use_bis = false; + unsigned int adc_0_reg = 0, adc_1_reg = 0, adc_3_reg = 0; + t_monitoring_param monitoring; + + if (suspend_flag == 1) { + return -EBUSY; + } + if (monitor_en) { + pr_debug("mc13783_adc : monitoring already configured\n"); + return PMIC_ERROR; + } + monitor_en = true; + mc13783_adc_init_monitor_param(&monitoring); + monitoring.comp_low = low; + monitoring.comp_high = high; + monitoring.channel = channel; + monitoring.callback = (void *)callback; + + use_bis = mc13783_adc_request(false); + if (use_bis < 0) { + pr_debug("mc13783_adc : request error\n"); + return PMIC_ERROR; + } + monitor_adc = use_bis; + + adc_0_reg = 0; + + /* TO DO ADOUT CONFIGURE */ + adc_0_reg = monitoring.read_mode & ADC_MODE_MASK; + if (use_bis) { + /* add adc bis */ + adc_0_reg |= ADC_BIS; + } + adc_0_reg |= ADC_WCOMP; + + /* CONFIGURE ADC REG 1 */ + adc_1_reg = 0; + adc_1_reg |= ADC_EN; + if (monitoring.conv_delay) { + adc_1_reg |= ADC_ATO; + } + if (monitoring.group) { + adc_1_reg |= ADC_ADSEL; + } + adc_1_reg |= (monitoring.channel << ADC_CH_0_POS) & ADC_CH_0_MASK; + adc_1_reg |= (monitoring.delay << ADC_DELAY_POS) & ADC_DELAY_MASK; + if (use_bis) { + adc_1_reg |= ADC_BIS; + } + + adc_3_reg |= (monitoring.comp_high << ADC_WCOMP_H_POS) & + ADC_WCOMP_H_MASK; + adc_3_reg |= (monitoring.comp_low << ADC_WCOMP_L_POS) & + ADC_WCOMP_L_MASK; + if (use_bis) { + adc_3_reg |= ADC_BIS; + } + + wcomp_mode = monitoring.check_mode; + /* call back to be called when event is detected. */ + monitoring_cb = monitoring.callback; + + CHECK_ERROR(pmic_write_reg(REG_ADC_0, adc_0_reg, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, adc_1_reg, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_3, adc_3_reg, PMIC_ALL_BITS)); + return PMIC_SUCCESS; +} + +/*! + * This function deactivates the comparator. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_deactive_comparator(void) +{ + unsigned int reg_value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + if (!monitor_en) { + pr_debug("mc13783_adc : adc monitoring free\n"); + return PMIC_ERROR; + } + + if (monitor_en) { + reg_value = ADC_BIS; + } + + /* clear all reg value */ + CHECK_ERROR(pmic_write_reg(REG_ADC_0, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_1, reg_value, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC_3, reg_value, PMIC_ALL_BITS)); + + reg_value = 0; + + if (monitor_adc) { + CHECK_ERROR(pmic_write_reg + (REG_ADC_4, reg_value, PMIC_ALL_BITS)); + } else { + CHECK_ERROR(pmic_write_reg + (REG_ADC_2, reg_value, PMIC_ALL_BITS)); + } + + mc13783_adc_release(monitor_adc); + monitor_en = false; + return PMIC_SUCCESS; +} + +/*! + * This function implements IOCTL controls on a MC13783 ADC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_adc_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + t_adc_convert_param *convert_param; + t_touch_mode touch_mode; + t_touch_screen touch_sample; + unsigned short b_current; + t_adc_comp_param *comp_param; + if ((_IOC_TYPE(cmd) != 'p') && (_IOC_TYPE(cmd) != 'D')) + return -ENOTTY; + + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + + convert_param = kmalloc(sizeof(t_adc_convert_param), GFP_KERNEL); + comp_param = kmalloc(sizeof(t_adc_comp_param), GFP_KERNEL); + switch (cmd) { + case PMIC_ADC_INIT: + pr_debug("init adc\n"); + CHECK_ERROR(pmic_adc_init()); + break; + + case PMIC_ADC_DEINIT: + pr_debug("deinit adc\n"); + CHECK_ERROR(pmic_adc_deinit()); + break; + + case PMIC_ADC_CONVERT: + if (convert_param == NULL) + return -ENOMEM; + + if (copy_from_user(convert_param, (t_adc_convert_param *) arg, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_adc_convert(convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((t_adc_convert_param *) arg, convert_param, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + case PMIC_ADC_CONVERT_8X: + if (convert_param == NULL) + return -ENOMEM; + + if (copy_from_user(convert_param, (t_adc_convert_param *) arg, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_adc_convert_8x(convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((t_adc_convert_param *) arg, convert_param, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + case PMIC_ADC_CONVERT_MULTICHANNEL: + if (convert_param == NULL) + return -ENOMEM; + + if (copy_from_user(convert_param, (t_adc_convert_param *) arg, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_adc_convert_multichnnel + (convert_param->channel, + convert_param->result), + (kfree(convert_param))); + + if (copy_to_user((t_adc_convert_param *) arg, convert_param, + sizeof(t_adc_convert_param))) { + kfree(convert_param); + return -EFAULT; + } + kfree(convert_param); + break; + + case PMIC_ADC_SET_TOUCH_MODE: + CHECK_ERROR(pmic_adc_set_touch_mode((t_touch_mode) arg)); + break; + + case PMIC_ADC_GET_TOUCH_MODE: + CHECK_ERROR(pmic_adc_get_touch_mode(&touch_mode)); + if (copy_to_user((t_touch_mode *) arg, &touch_mode, + sizeof(t_touch_mode))) { + return -EFAULT; + } + break; + + case PMIC_ADC_GET_TOUCH_SAMPLE: + pr_debug("pmic_adc_ioctl: " "PMIC_ADC_GET_TOUCH_SAMPLE\n"); + CHECK_ERROR(pmic_adc_get_touch_sample(&touch_sample, 1)); + if (copy_to_user((t_touch_screen *) arg, &touch_sample, + sizeof(t_touch_screen))) { + return -EFAULT; + } + break; + + case PMIC_ADC_GET_BATTERY_CURRENT: + CHECK_ERROR(pmic_adc_get_battery_current(ADC_8CHAN_1X, + &b_current)); + if (copy_to_user((unsigned short *)arg, &b_current, + sizeof(unsigned short))) { + + return -EFAULT; + } + break; + + case PMIC_ADC_ACTIVATE_COMPARATOR: + if (comp_param == NULL) + return -ENOMEM; + + if (copy_from_user(comp_param, (t_adc_comp_param *) arg, + sizeof(t_adc_comp_param))) { + kfree(comp_param); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_adc_active_comparator(comp_param->wlow, + comp_param->whigh, + comp_param-> + channel, + comp_param-> + callback), + (kfree(comp_param))); + break; + + case PMIC_ADC_DEACTIVE_COMPARATOR: + CHECK_ERROR(pmic_adc_deactive_comparator()); + break; + + default: + pr_debug("pmic_adc_ioctl: unsupported ioctl command 0x%x\n", + cmd); + return -EINVAL; + } + return 0; +} + +static struct file_operations mc13783_adc_fops = { + .owner = THIS_MODULE, + .ioctl = pmic_adc_ioctl, + .open = pmic_adc_open, + .release = pmic_adc_free, +}; + +static int pmic_adc_module_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *temp_class; + + pmic_adc_major = register_chrdev(0, "pmic_adc", &mc13783_adc_fops); + + if (pmic_adc_major < 0) { + pr_debug(KERN_ERR "Unable to get a major for pmic_adc\n"); + return pmic_adc_major; + } + init_waitqueue_head(&suspendq); + + pmic_adc_class = class_create(THIS_MODULE, "pmic_adc"); + if (IS_ERR(pmic_adc_class)) { + pr_debug(KERN_ERR "Error creating pmic_adc class.\n"); + ret = PTR_ERR(pmic_adc_class); + goto err_out1; + } + + temp_class = device_create(pmic_adc_class, NULL, + MKDEV(pmic_adc_major, 0), NULL, "pmic_adc"); + if (IS_ERR(temp_class)) { + pr_debug(KERN_ERR "Error creating pmic_adc class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + ret = pmic_adc_init(); + if (ret != PMIC_SUCCESS) { + pr_debug(KERN_ERR "Error in pmic_adc_init.\n"); + goto err_out4; + } + + pmic_adc_ready = 1; + pr_debug(KERN_INFO "PMIC ADC successfully probed\n"); + return ret; + + err_out4: + device_destroy(pmic_adc_class, MKDEV(pmic_adc_major, 0)); + err_out2: + class_destroy(pmic_adc_class); + err_out1: + unregister_chrdev(pmic_adc_major, "pmic_adc"); + return ret; +} + +static int pmic_adc_module_remove(struct platform_device *pdev) +{ + pmic_adc_ready = 0; + pmic_adc_deinit(); + device_destroy(pmic_adc_class, MKDEV(pmic_adc_major, 0)); + class_destroy(pmic_adc_class); + unregister_chrdev(pmic_adc_major, "pmic_adc"); + pr_debug(KERN_INFO "PMIC ADC successfully removed\n"); + return 0; +} + +static struct platform_driver pmic_adc_driver_ldm = { + .driver = { + .name = "pmic_adc", + }, + .suspend = pmic_adc_suspend, + .resume = pmic_adc_resume, + .probe = pmic_adc_module_probe, + .remove = pmic_adc_module_remove, +}; + +/* + * Initialization and Exit + */ +static int __init pmic_adc_module_init(void) +{ + pr_debug("PMIC ADC driver loading...\n"); + return platform_driver_register(&pmic_adc_driver_ldm); +} + +static void __exit pmic_adc_module_exit(void) +{ + platform_driver_unregister(&pmic_adc_driver_ldm); + pr_debug("PMIC ADC driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +module_init(pmic_adc_module_init); +module_exit(pmic_adc_module_exit); + +MODULE_DESCRIPTION("PMIC ADC device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13783/pmic_adc_defs.h b/drivers/mxc/pmic/mc13783/pmic_adc_defs.h new file mode 100644 index 000000000000..fbde842bad94 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_adc_defs.h @@ -0,0 +1,321 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_adc_defs.h + * @brief This header contains all defines for PMIC(mc13783) ADC driver. + * + * @ingroup PMIC_ADC + */ + +#ifndef __MC13783_ADC__DEFS_H__ +#define __MC13783_ADC__DEFS_H__ + +#define MC13783_ADC_DEVICE "/dev/mc13783_adc" + +#define DEF_ADC_0 0x008000 +#define DEF_ADC_3 0x000080 + +#define ADC_NB_AVAILABLE 2 + +#define MAX_CHANNEL 7 + +/* + * Maximun allowed variation in the three X/Y co-ordinates acquired from + * touch-screen + */ +#define DELTA_Y_MAX 50 +#define DELTA_X_MAX 50 + +/* Upon clearing the filter, this is the delay in restarting the filter */ +#define FILTER_MIN_DELAY 4 + +/* Length of X and Y Touch screen filters */ +#define FILTLEN 3 + +#define TS_X_MAX 1000 +#define TS_Y_MAX 1000 + +#define TS_X_MIN 80 +#define TS_Y_MIN 80 + +#define MC13783_ADC0_TS_M_LSH 14 +#define MC13783_ADC0_TS_M_WID 3 +/* + * ADC 0 + */ +#define ADC_WAIT_TSI_0 0x001C00 + +/* + * ADC 1 + */ + +#define ADC_EN 0x000001 +#define ADC_SGL_CH 0x000002 +#define ADC_ADSEL 0x000008 +#define ADC_CH_0_POS 5 +#define ADC_CH_0_MASK 0x0000E0 +#define ADC_CH_1_POS 8 +#define ADC_CH_1_MASK 0x000700 +#define ADC_DELAY_POS 11 +#define ADC_DELAY_MASK 0x07F800 +#define ADC_ATO 0x080000 +#define ASC_ADC 0x100000 +#define ADC_WAIT_TSI_1 0x300001 +#define ADC_CHRGRAW_D5 0x008000 + +/* + * ADC 2 - 4 + */ +#define ADD1_RESULT_MASK 0x00000FFC +#define ADD2_RESULT_MASK 0x00FFC000 +#define ADC_TS_MASK 0x00FFCFFC + +/* + * ADC 3 + */ +#define ADC_INC 0x030000 +#define ADC_BIS 0x800000 + +/* + * ADC 3 + */ +#define ADC_NO_ADTRIG 0x200000 +#define ADC_WCOMP 0x040000 +#define ADC_WCOMP_H_POS 0 +#define ADC_WCOMP_L_POS 9 +#define ADC_WCOMP_H_MASK 0x00003F +#define ADC_WCOMP_L_MASK 0x007E00 + +#define ADC_MODE_MASK 0x00003F + +/* + * Interrupt Status 0 + */ +#define ADC_INT_BISDONEI 0x02 + +/*! + * Define state mode of ADC. + */ +typedef enum adc_state { + /*! + * Free. + */ + ADC_FREE, + /*! + * Used. + */ + ADC_USED, + /*! + * Monitoring + */ + ADC_MONITORING, +} t_adc_state; + +/*! + * This enumeration, is used to configure the mode of ADC. + */ +typedef enum reading_mode { + /*! + * Enables lithium cell reading + */ + M_LITHIUM_CELL = 0x000001, + /*! + * Enables charge current reading + */ + M_CHARGE_CURRENT = 0x000002, + /*! + * Enables battery current reading + */ + M_BATTERY_CURRENT = 0x000004, + /*! + * Enables thermistor reading + */ + M_THERMISTOR = 0x000008, + /*! + * Enables die temperature reading + */ + M_DIE_TEMPERATURE = 0x000010, + /*! + * Enables UID reading + */ + M_UID = 0x000020, +} t_reading_mode; + +/*! + * This enumeration, is used to configure the monitoring mode. + */ +typedef enum check_mode { + /*! + * Comparator low level + */ + CHECK_LOW, + /*! + * Comparator high level + */ + CHECK_HIGH, + /*! + * Comparator low or high level + */ + CHECK_LOW_OR_HIGH, +} t_check_mode; + +/*! + * This structure is used to configure and report adc value. + */ +typedef struct { + /*! + * Delay before first conversion + */ + unsigned int delay; + /*! + * sets the ATX bit for delay on all conversion + */ + bool conv_delay; + /*! + * Sets the single channel mode + */ + bool single_channel; + /*! + * Selects the set of inputs + */ + bool group; + /*! + * Channel selection 1 + */ + t_channel channel_0; + /*! + * Channel selection 2 + */ + t_channel channel_1; + /*! + * Used to configure ADC mode with t_reading_mode + */ + t_reading_mode read_mode; + /*! + * Sets the Touch screen mode + */ + bool read_ts; + /*! + * Wait TSI event before touch screen reading + */ + bool wait_tsi; + /*! + * Sets CHRGRAW scaling to divide by 5 + * Only supported on 2.0 and higher + */ + bool chrgraw_devide_5; + /*! + * Return ADC values + */ + unsigned int value[8]; + /*! + * Return touch screen values + */ + t_touch_screen ts_value; +} t_adc_param; + +/*! + * This structure is used to configure the monitoring mode of ADC. + */ +typedef struct { + /*! + * Delay before first conversion + */ + unsigned int delay; + /*! + * sets the ATX bit for delay on all conversion + */ + bool conv_delay; + /*! + * Channel selection 1 + */ + t_channel channel; + /*! + * Selects the set of inputs + */ + bool group; + /*! + * Used to configure ADC mode with t_reading_mode + */ + unsigned int read_mode; + /*! + * Comparator low level in WCOMP mode + */ + unsigned int comp_low; + /*! + * Comparator high level in WCOMP mode + */ + unsigned int comp_high; + /*! + * Sets type of monitoring (low, high or both) + */ + t_check_mode check_mode; + /*! + * Callback to be launched when event is detected + */ + void (*callback) (void); +} t_monitoring_param; + +/*! + * This function performs filtering and rejection of excessive noise prone + * samples. + * + * @param ts_curr Touch screen value + * + * @return This function returns 0 on success, -1 otherwise. + */ +static int pmic_adc_filter(t_touch_screen *ts_curr); + +/*! + * This function request a ADC. + * + * @return This function returns index of ADC to be used (0 or 1) if successful. + * return -1 if error. + */ +int mc13783_adc_request(bool read_ts); + +/*! + * This function is used to update buffer of touch screen value in read mode. + */ +void update_buffer(void); + +/*! + * This function release an ADC. + * + * @param adc_index index of ADC to be released. + * + * @return This function returns 0 if successful. + */ +int mc13783_adc_release(int adc_index); + +/*! + * This function select the required read_mode for a specific channel. + * + * @param channel The channel to be sampled + * + * @return This function returns the requires read_mode + */ +t_reading_mode mc13783_set_read_mode(t_channel channel); + +/*! + * This function read the touch screen value. + * + * @param touch_sample return value of touch screen + * @param wait_tsi if true, this function is synchronous (wait in TSI event). + * + * @return This function returns 0. + */ +PMIC_STATUS mc13783_adc_read_ts(t_touch_screen *touch_sample, int wait_tsi); + +#endif /* __MC13783_ADC__DEFS_H__ */ diff --git a/drivers/mxc/pmic/mc13783/pmic_audio.c b/drivers/mxc/pmic/mc13783/pmic_audio.c new file mode 100644 index 000000000000..acdde44b738f --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_audio.c @@ -0,0 +1,5873 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_audio.c + * @brief Implementation of the PMIC(mc13783) Audio driver APIs. + * + * The PMIC Audio driver and this API were developed to support the + * audio playback, recording, and mixing capabilities of the power + * management ICs that are available from Freescale Semiconductor, Inc. + * + * The following operating modes are supported: + * + * @verbatim + Operating Mode mc13783 + ---------------------------- ------- + Stereo DAC Playback Yes + Stereo DAC Input Mixing Yes + Voice CODEC Playback Yes + Voice CODEC Input Mixing Yes + Voice CODEC Mono Recording Yes + Voice CODEC Stereo Recording Yes + Microphone Bias Control Yes + Output Amplifier Control Yes + Output Mixing Control Yes + Input Amplifier Control Yes + Master/Slave Mode Select Yes + Anti Pop Bias Circuit Control Yes + @endverbatim + * + * Note that the Voice CODEC may also be referred to as the Telephone + * CODEC in the PMIC DTS documentation. Also note that, while the power + * management ICs do provide similar audio capabilities, each PMIC may + * support additional configuration settings and features. Therefore, it + * is highly recommended that the appropriate power management IC DTS + * documents be used in conjunction with this API interface. + * + * @ingroup PMIC_AUDIO + */ + +#include +#include /* For tasklet interface. */ +#include /* For kernel module interface. */ +#include +#include /* For spinlock interface. */ +#include /* For PMIC ADC driver interface. */ +#include +#include /* For PMIC Audio driver interface. */ + +/* + * mc13783 PMIC Audio API + */ + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(MIN_STDAC_SAMPLING_RATE_HZ); +EXPORT_SYMBOL(MAX_STDAC_SAMPLING_RATE_HZ); +EXPORT_SYMBOL(pmic_audio_open); +EXPORT_SYMBOL(pmic_audio_close); +EXPORT_SYMBOL(pmic_audio_set_protocol); +EXPORT_SYMBOL(pmic_audio_get_protocol); +EXPORT_SYMBOL(pmic_audio_enable); +EXPORT_SYMBOL(pmic_audio_disable); +EXPORT_SYMBOL(pmic_audio_reset); +EXPORT_SYMBOL(pmic_audio_reset_all); +EXPORT_SYMBOL(pmic_audio_set_callback); +EXPORT_SYMBOL(pmic_audio_clear_callback); +EXPORT_SYMBOL(pmic_audio_get_callback); +EXPORT_SYMBOL(pmic_audio_antipop_enable); +EXPORT_SYMBOL(pmic_audio_antipop_disable); +EXPORT_SYMBOL(pmic_audio_digital_filter_reset); +EXPORT_SYMBOL(pmic_audio_vcodec_set_clock); +EXPORT_SYMBOL(pmic_audio_vcodec_get_clock); +EXPORT_SYMBOL(pmic_audio_vcodec_set_rxtx_timeslot); +EXPORT_SYMBOL(pmic_audio_vcodec_get_rxtx_timeslot); +EXPORT_SYMBOL(pmic_audio_vcodec_set_secondary_txslot); +EXPORT_SYMBOL(pmic_audio_vcodec_get_secondary_txslot); +EXPORT_SYMBOL(pmic_audio_vcodec_set_config); +EXPORT_SYMBOL(pmic_audio_vcodec_clear_config); +EXPORT_SYMBOL(pmic_audio_vcodec_get_config); +EXPORT_SYMBOL(pmic_audio_vcodec_enable_bypass); +EXPORT_SYMBOL(pmic_audio_vcodec_disable_bypass); +EXPORT_SYMBOL(pmic_audio_stdac_set_clock); +EXPORT_SYMBOL(pmic_audio_stdac_get_clock); +EXPORT_SYMBOL(pmic_audio_stdac_set_rxtx_timeslot); +EXPORT_SYMBOL(pmic_audio_stdac_get_rxtx_timeslot); +EXPORT_SYMBOL(pmic_audio_stdac_set_config); +EXPORT_SYMBOL(pmic_audio_stdac_clear_config); +EXPORT_SYMBOL(pmic_audio_stdac_get_config); +EXPORT_SYMBOL(pmic_audio_input_set_config); +EXPORT_SYMBOL(pmic_audio_input_clear_config); +EXPORT_SYMBOL(pmic_audio_input_get_config); +EXPORT_SYMBOL(pmic_audio_vcodec_set_mic); +EXPORT_SYMBOL(pmic_audio_vcodec_get_mic); +EXPORT_SYMBOL(pmic_audio_vcodec_set_mic_on_off); +EXPORT_SYMBOL(pmic_audio_vcodec_get_mic_on_off); +EXPORT_SYMBOL(pmic_audio_vcodec_set_record_gain); +EXPORT_SYMBOL(pmic_audio_vcodec_get_record_gain); +EXPORT_SYMBOL(pmic_audio_vcodec_enable_micbias); +EXPORT_SYMBOL(pmic_audio_vcodec_disable_micbias); +EXPORT_SYMBOL(pmic_audio_vcodec_enable_mixer); +EXPORT_SYMBOL(pmic_audio_vcodec_disable_mixer); +EXPORT_SYMBOL(pmic_audio_stdac_enable_mixer); +EXPORT_SYMBOL(pmic_audio_stdac_disable_mixer); +EXPORT_SYMBOL(pmic_audio_output_set_port); +EXPORT_SYMBOL(pmic_audio_output_get_port); +EXPORT_SYMBOL(pmic_audio_output_clear_port); +EXPORT_SYMBOL(pmic_audio_output_set_stereo_in_gain); +EXPORT_SYMBOL(pmic_audio_output_get_stereo_in_gain); +EXPORT_SYMBOL(pmic_audio_output_set_pgaGain); +EXPORT_SYMBOL(pmic_audio_output_get_pgaGain); +EXPORT_SYMBOL(pmic_audio_output_enable_mixer); +EXPORT_SYMBOL(pmic_audio_output_disable_mixer); +EXPORT_SYMBOL(pmic_audio_output_set_balance); +EXPORT_SYMBOL(pmic_audio_output_get_balance); +EXPORT_SYMBOL(pmic_audio_output_enable_mono_adder); +EXPORT_SYMBOL(pmic_audio_output_disable_mono_adder); +EXPORT_SYMBOL(pmic_audio_output_set_mono_adder_gain); +EXPORT_SYMBOL(pmic_audio_output_get_mono_adder_gain); +EXPORT_SYMBOL(pmic_audio_output_set_config); +EXPORT_SYMBOL(pmic_audio_output_clear_config); +EXPORT_SYMBOL(pmic_audio_output_get_config); +EXPORT_SYMBOL(pmic_audio_output_enable_phantom_ground); +EXPORT_SYMBOL(pmic_audio_output_disable_phantom_ground); +EXPORT_SYMBOL(pmic_audio_set_autodetect); +#ifdef DEBUG_AUDIO +EXPORT_SYMBOL(pmic_audio_dump_registers); +#endif /* DEBUG_AUDIO */ +/*! + * Define the minimum sampling rate (in Hz) that is supported by the + * Stereo DAC. + */ +const unsigned MIN_STDAC_SAMPLING_RATE_HZ = 8000; + +/*! + * Define the maximum sampling rate (in Hz) that is supported by the + * Stereo DAC. + */ +const unsigned MAX_STDAC_SAMPLING_RATE_HZ = 96000; + +/*! @def SET_BITS + * Set a register field to a given value. + */ +#define SET_BITS(reg, field, value) (((value) << reg.field.offset) & \ + reg.field.mask) +/*! @def GET_BITS + * Get the current value of a given register field. + */ +#define GET_BITS(reg, field, value) (((value) & reg.field.mask) >> \ + reg.field.offset) + +/*! + * @brief Define the possible states for a device handle. + * + * This enumeration is used to track the current state of each device handle. + */ +typedef enum { + HANDLE_FREE, /*!< Handle is available for use. */ + HANDLE_IN_USE /*!< Handle is currently in use. */ +} HANDLE_STATE; + +/*! + * @brief Identifies the hardware interrupt source. + * + * This enumeration identifies which of the possible hardware interrupt + * sources actually caused the current interrupt handler to be called. + */ +typedef enum { + CORE_EVENT_MC2BI, /*!< Microphone Bias 2 detect. */ + CORE_EVENT_HSDETI, /*!< Detect Headset attach */ + CORE_EVENT_HSLI, /*!< Detect Stereo Headset */ + CORE_EVENT_ALSPTHI, /*!< Detect Thermal shutdown of ALSP */ + CORE_EVENT_AHSSHORTI /*!< Detect Short circuit on AHS outputs */ +} PMIC_CORE_EVENT; + +/*! + * @brief This structure is used to track the state of a microphone input. + */ +typedef struct { + PMIC_AUDIO_INPUT_PORT mic; /*!< Microphone input port. */ + PMIC_AUDIO_INPUT_MIC_STATE micOnOff; /*!< Microphone On/Off state. */ + PMIC_AUDIO_MIC_AMP_MODE ampMode; /*!< Input amplifier mode. */ + PMIC_AUDIO_MIC_GAIN gain; /*!< Input amplifier gain level. */ +} PMIC_MICROPHONE_STATE; + +/*! + * @brief Tracks whether a headset is currently attached or not. + */ +typedef enum { + NO_HEADSET, /*!< No headset currently attached. */ + HEADSET_ON /*!< Headset has been attached. */ +} HEADSET_STATUS; + +/*! + * @brief mc13783 only enum that indicates the path to output taken + * by the voice codec output + */ +typedef enum { + VCODEC_DIRECT_OUT, /*!< Vcodec signal out direct */ + VCODEC_MIXER_OUT /*!< Output via the mixer */ +} PMIC_AUDIO_VCODEC_OUTPUT_PATH; + +/*! + * @brief This structure is used to define a specific hardware register field. + * + * All hardware register fields are defined using an offset to the LSB + * and a mask. The offset is used to right shift a register value before + * applying the mask to actually obtain the value of the field. + */ +typedef struct { + const unsigned char offset; /*!< Offset of LSB of register field. */ + const unsigned int mask; /*!< Mask value used to isolate register field. */ +} REGFIELD; + +/*! + * @brief This structure lists all fields of the AUD_CODEC hardware register. + */ +typedef struct { + REGFIELD CDCSSISEL; /*!< codec SSI bus select */ + REGFIELD CDCCLKSEL; /*!< Codec clock input select */ + REGFIELD CDCSM; /*!< Codec slave / master select */ + REGFIELD CDCBCLINV; /*!< Codec bitclock inversion */ + REGFIELD CDCFSINV; /*!< Codec framesync inversion */ + REGFIELD CDCFS; /*!< Bus protocol selection - 2 bits */ + REGFIELD CDCCLK; /*!< Codec clock setting - 3 bits */ + REGFIELD CDCFS8K16K; /*!< Codec framesync select */ + REGFIELD CDCEN; /*!< Codec enable */ + REGFIELD CDCCLKEN; /*!< Codec clocking enable */ + REGFIELD CDCTS; /*!< Codec SSI tristate */ + REGFIELD CDCDITH; /*!< Codec dithering */ + REGFIELD CDCRESET; /*!< Codec filter reset */ + REGFIELD CDCBYP; /*!< Codec bypass */ + REGFIELD CDCALM; /*!< Codec analog loopback */ + REGFIELD CDCDLM; /*!< Codec digital loopback */ + REGFIELD AUDIHPF; /*!< Transmit high pass filter enable */ + REGFIELD AUDOHPF; /*!< Receive high pass filter enable */ +} REGISTER_AUD_CODEC; + +/*! + * @brief This variable is used to access the AUD_CODEC hardware register. + * + * This variable defines how to access all of the fields within the + * AUD_CODEC hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_AUD_CODEC regAUD_CODEC = { + {0, 0x000001}, /* CDCSSISEL */ + {1, 0x000002}, /* CDCCLKSEL */ + {2, 0x000004}, /* CDCSM */ + {3, 0x000008}, /* CDCBCLINV */ + {4, 0x000010}, /* CDCFSINV */ + {5, 0x000060}, /* CDCFS */ + {7, 0x000380}, /* CDCCLK */ + {10, 0x000400}, /* CDCFS8K16K */ + {11, 0x000800}, /* CDCEN */ + {12, 0x001000}, /* CDCCLKEN */ + {13, 0x002000}, /* CDCTS */ + {14, 0x004000}, /* CDCDITH */ + {15, 0x008000}, /* CDCRESET */ + {16, 0x010000}, /* CDCBYP */ + {17, 0x020000}, /* CDCALM */ + {18, 0x040000}, /* CDCDLM */ + {19, 0x080000}, /* AUDIHPF */ + {20, 0x100000} /* AUDOHPF */ + /* Unused */ + /* Unused */ + /* Unused */ + +}; + +/*! + * @brief This structure lists all fields of the ST_DAC hardware register. + */ + /* VVV */ +typedef struct { + REGFIELD STDCSSISEL; /*!< Stereo DAC SSI bus select */ + REGFIELD STDCCLKSEL; /*!< Stereo DAC clock input select */ + REGFIELD STDCSM; /*!< Stereo DAC slave / master select */ + REGFIELD STDCBCLINV; /*!< Stereo DAC bitclock inversion */ + REGFIELD STDCFSINV; /*!< Stereo DAC framesync inversion */ + REGFIELD STDCFS; /*!< Bus protocol selection - 2 bits */ + REGFIELD STDCCLK; /*!< Stereo DAC clock setting - 3 bits */ + REGFIELD STDCFSDLYB; /*!< Stereo DAC framesync delay bar */ + REGFIELD STDCEN; /*!< Stereo DAC enable */ + REGFIELD STDCCLKEN; /*!< Stereo DAC clocking enable */ + REGFIELD STDCRESET; /*!< Stereo DAC filter reset */ + REGFIELD SPDIF; /*!< Stereo DAC SSI SPDIF mode. Mode no longer available. */ + REGFIELD SR; /*!< Stereo DAC sample rate - 4 bits */ +} REGISTER_ST_DAC; + +/*! + * @brief This variable is used to access the ST_DAC hardware register. + * + * This variable defines how to access all of the fields within the + * ST_DAC hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_ST_DAC regST_DAC = { + {0, 0x000001}, /* STDCSSISEL */ + {1, 0x000002}, /* STDCCLKSEL */ + {2, 0x000004}, /* STDCSM */ + {3, 0x000008}, /* STDCBCLINV */ + {4, 0x000010}, /* STDCFSINV */ + {5, 0x000060}, /* STDCFS */ + {7, 0x000380}, /* STDCCLK */ + {10, 0x000400}, /* STDCFSDLYB */ + {11, 0x000800}, /* STDCEN */ + {12, 0x001000}, /* STDCCLKEN */ + {15, 0x008000}, /* STDCRESET */ + {16, 0x010000}, /* SPDIF */ + {17, 0x1E0000} /* SR */ +}; + +/*! + * @brief This structure lists all of the fields in the SSI_NETWORK hardware register. + */ +typedef struct { + REGFIELD CDCTXRXSLOT; /*!< Codec timeslot assignment - 2 bits */ + REGFIELD CDCTXSECSLOT; /*!< Codec secondary transmit timeslot - 2 bits */ + REGFIELD CDCRXSECSLOT; /*!< Codec secondary receive timeslot - 2 bits */ + REGFIELD CDCRXSECGAIN; /*!< Codec secondary receive channel gain setting - 2 bits */ + REGFIELD CDCSUMGAIN; /*!< Codec summed receive signal gain setting */ + REGFIELD CDCFSDLY; /*!< Codec framesync delay */ + REGFIELD STDCSLOTS; /*!< Stereo DAC number of timeslots select - 2 bits */ + REGFIELD STDCRXSLOT; /*!< Stereo DAC timeslot assignment - 2 bits */ + REGFIELD STDCRXSECSLOT; /*!< Stereo DAC secondary receive timeslot - 2 bits */ + REGFIELD STDCRXSECGAIN; /*!< Stereo DAC secondary receive channel gain setting - 2 bits */ + REGFIELD STDCSUMGAIN; /*!< Stereo DAC summed receive signal gain setting */ +} REGISTER_SSI_NETWORK; + +/*! + * @brief This variable is used to access the SSI_NETWORK hardware register. + * + * This variable defines how to access all of the fields within the + * SSI_NETWORK hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_SSI_NETWORK regSSI_NETWORK = { + {2, 0x00000c}, /* CDCTXRXSLOT */ + {4, 0x000030}, /* CDCTXSECSLOT */ + {6, 0x0000c0}, /* CDCRXSECSLOT */ + {8, 0x000300}, /* CDCRXSECGAIN */ + {10, 0x000400}, /* CDCSUMGAIN */ + {11, 0x000800}, /* CDCFSDLY */ + {12, 0x003000}, /* STDCSLOTS */ + {14, 0x00c000}, /* STDCRXSLOT */ + {16, 0x030000}, /* STDCRXSECSLOT */ + {18, 0x0c0000}, /* STDCRXSECGAIN */ + {20, 0x100000} /* STDCSUMGAIN */ +}; + +/*! + * @brief This structure lists all fields of the AUDIO_TX hardware register. + * + * + */ +typedef struct { + REGFIELD MC1BEN; /*!< Microphone bias 1 enable */ + REGFIELD MC2BEN; /*!< Microphone bias 2 enable */ + REGFIELD MC2BDETDBNC; /*!< Microphone bias detect debounce setting */ + REGFIELD MC2BDETEN; /*!< Microphone bias 2 detect enable */ + REGFIELD AMC1REN; /*!< Amplifier Amc1R enable */ + REGFIELD AMC1RITOV; /*!< Amplifier Amc1R current to voltage mode enable */ + REGFIELD AMC1LEN; /*!< Amplifier Amc1L enable */ + REGFIELD AMC1LITOV; /*!< Amplifier Amc1L current to voltage mode enable */ + REGFIELD AMC2EN; /*!< Amplifier Amc2 enable */ + REGFIELD AMC2ITOV; /*!< Amplifier Amc2 current to voltage mode enable */ + REGFIELD ATXINEN; /*!< Amplifier Atxin enable */ + REGFIELD ATXOUTEN; /*!< Reserved for output TXOUT enable, currently not used */ + REGFIELD RXINREC; /*!< RXINR/RXINL to voice CODEC ADC routing enable */ + REGFIELD PGATXR; /*!< Transmit gain setting right - 5 bits */ + REGFIELD PGATXL; /*!< Transmit gain setting left - 5 bits */ +} REGISTER_AUDIO_TX; + +/*! + * @brief This variable is used to access the AUDIO_TX hardware register. + * + * This variable defines how to access all of the fields within the + * AUDIO_TX hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_AUDIO_TX regAUDIO_TX = { + {0, 0x000001}, /* MC1BEN */ + {1, 0x000002}, /* MC2BEN */ + {2, 0x000004}, /* MC2BDETDBNC */ + {3, 0x000008}, /* MC2BDETEN */ + {5, 0x000020}, /* AMC1REN */ + {6, 0x000040}, /* AMC1RITOV */ + {7, 0x000080}, /* AMC1LEN */ + {8, 0x000100}, /* AMC1LITOV */ + {9, 0x000200}, /* AMC2EN */ + {10, 0x000400}, /* AMC2ITOV */ + {11, 0x000800}, /* ATXINEN */ + {12, 0x001000}, /* ATXOUTEN */ + {13, 0x002000}, /* RXINREC */ + {14, 0x07c000}, /* PGATXR */ + {19, 0xf80000} /* PGATXL */ +}; + +/*! + * @brief This structure lists all fields of the AUDIO_RX_0 hardware register. + */ +typedef struct { + REGFIELD VAUDIOON; /*!< Forces VAUDIO in active on mode */ + REGFIELD BIASEN; /*!< Audio bias enable */ + REGFIELD BIASSPEED; /*!< Turn on ramp speed of the audio bias */ + REGFIELD ASPEN; /*!< Amplifier Asp enable */ + REGFIELD ASPSEL; /*!< Asp input selector */ + REGFIELD ALSPEN; /*!< Amplifier Alsp enable */ + REGFIELD ALSPREF; /*!< Bias Alsp at common audio reference */ + REGFIELD ALSPSEL; /*!< Alsp input selector */ + REGFIELD LSPLEN; /*!< Output LSPL enable */ + REGFIELD AHSREN; /*!< Amplifier AhsR enable */ + REGFIELD AHSLEN; /*!< Amplifier AhsL enable */ + REGFIELD AHSSEL; /*!< Ahsr and Ahsl input selector */ + REGFIELD HSPGDIS; /*!< Phantom ground disable */ + REGFIELD HSDETEN; /*!< Headset detect enable */ + REGFIELD HSDETAUTOB; /*!< Amplifier state determined by headset detect */ + REGFIELD ARXOUTREN; /*!< Output RXOUTR enable */ + REGFIELD ARXOUTLEN; /*!< Output RXOUTL enable */ + REGFIELD ARXOUTSEL; /*!< Arxout input selector */ + REGFIELD CDCOUTEN; /*!< Output CDCOUT enable */ + REGFIELD HSLDETEN; /*!< Headset left channel detect enable */ + REGFIELD ADDCDC; /*!< Adder channel codec selection */ + REGFIELD ADDSTDC; /*!< Adder channel stereo DAC selection */ + REGFIELD ADDRXIN; /*!< Adder channel line in selection */ +} REGISTER_AUDIO_RX_0; + +/*! + * @brief This variable is used to access the AUDIO_RX_0 hardware register. + * + * This variable defines how to access all of the fields within the + * AUDIO_RX_0 hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_AUDIO_RX_0 regAUDIO_RX_0 = { + {0, 0x000001}, /* VAUDIOON */ + {1, 0x000002}, /* BIASEN */ + {2, 0x000004}, /* BIASSPEED */ + {3, 0x000008}, /* ASPEN */ + {4, 0x000010}, /* ASPSEL */ + {5, 0x000020}, /* ALSPEN */ + {6, 0x000040}, /* ALSPREF */ + {7, 0x000080}, /* ALSPSEL */ + {8, 0x000100}, /* LSPLEN */ + {9, 0x000200}, /* AHSREN */ + {10, 0x000400}, /* AHSLEN */ + {11, 0x000800}, /* AHSSEL */ + {12, 0x001000}, /* HSPGDIS */ + {13, 0x002000}, /* HSDETEN */ + {14, 0x004000}, /* HSDETAUTOB */ + {15, 0x008000}, /* ARXOUTREN */ + {16, 0x010000}, /* ARXOUTLEN */ + {17, 0x020000}, /* ARXOUTSEL */ + {18, 0x040000}, /* CDCOUTEN */ + {19, 0x080000}, /* HSLDETEN */ + {21, 0x200000}, /* ADDCDC */ + {22, 0x400000}, /* ADDSTDC */ + {23, 0x800000} /* ADDRXIN */ +}; + +/*! + * @brief This structure lists all fields of the AUDIO_RX_1 hardware register. + */ +typedef struct { + REGFIELD PGARXEN; /*!< Codec receive PGA enable */ + REGFIELD PGARX; /*!< Codec receive gain setting - 4 bits */ + REGFIELD PGASTEN; /*!< Stereo DAC PGA enable */ + REGFIELD PGAST; /*!< Stereo DAC gain setting - 4 bits */ + REGFIELD ARXINEN; /*!< Amplifier Arx enable */ + REGFIELD ARXIN; /*!< Amplifier Arx additional gain setting */ + REGFIELD PGARXIN; /*!< PGArxin gain setting - 4 bits */ + REGFIELD MONO; /*!< Mono adder setting - 2 bits */ + REGFIELD BAL; /*!< Balance control - 3 bits */ + REGFIELD BALLR; /*!< Left / right balance */ +} REGISTER_AUDIO_RX_1; + +/*! + * @brief This variable is used to access the AUDIO_RX_1 hardware register. + * + * This variable defines how to access all of the fields within the + * AUDIO_RX_1 hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const REGISTER_AUDIO_RX_1 regAUDIO_RX_1 = { + {0, 0x000001}, /* PGARXEN */ + {1, 0x00001e}, /* PGARX */ + {5, 0x000020}, /* PGASTEN */ + {6, 0x0003c0}, /* PGAST */ + {10, 0x000400}, /* ARXINEN */ + {11, 0x000800}, /* ARXIN */ + {12, 0x00f000}, /* PGARXIN */ + {16, 0x030000}, /* MONO */ + {18, 0x1c0000}, /* BAL */ + {21, 0x200000} /* BALLR */ +}; + +/*! Define a mask to access the entire hardware register. */ +static const unsigned int REG_FULLMASK = 0xffffff; + +/*! Reset value for the AUD_CODEC register. */ +static const unsigned int RESET_AUD_CODEC = 0x180027; + +/*! Reset value for the ST_DAC register. + * + * Note that we avoid resetting any of the arbitration bits. + */ +static const unsigned int RESET_ST_DAC = 0x0E0004; + +/*! Reset value for the SSI_NETWORK register. */ +static const unsigned int RESET_SSI_NETWORK = 0x013060; + +/*! Reset value for the AUDIO_TX register. + * + * Note that we avoid resetting any of the arbitration bits. + */ +static const unsigned int RESET_AUDIO_TX = 0x420000; + +/*! Reset value for the AUDIO_RX_0 register. */ +static const unsigned int RESET_AUDIO_RX_0 = 0x001000; + +/*! Reset value for the AUDIO_RX_1 register. */ +static const unsigned int RESET_AUDIO_RX_1 = 0x00D35A; + +/*! Reset mask for the SSI network Vcodec part. first 12 bits + * 0 - 11 */ +static const unsigned int REG_SSI_VCODEC_MASK = 0x000fff; + +/*! Reset mask for the SSI network STDAC part. last 12 bits + * 12 - 24 */ +static const unsigned int REG_SSI_STDAC_MASK = 0xfff000; + +/*! Constant NULL value for initializing/reseting the audio handles. */ +static const PMIC_AUDIO_HANDLE AUDIO_HANDLE_NULL = (PMIC_AUDIO_HANDLE) NULL; + +/*! + * @brief This structure maintains the current state of the Stereo DAC. + */ +typedef struct { + PMIC_AUDIO_HANDLE handle; /*!< Handle used to access + the Stereo DAC. */ + HANDLE_STATE handleState; /*!< Current handle state. */ + PMIC_AUDIO_DATA_BUS busID; /*!< Data bus used to access + the Stereo DAC. */ + bool protocol_set; + PMIC_AUDIO_BUS_PROTOCOL protocol; /*!< Data bus protocol. */ + PMIC_AUDIO_BUS_MODE masterSlave; /*!< Master/Slave mode + select. */ + PMIC_AUDIO_NUMSLOTS numSlots; /*!< Number of timeslots + used. */ + PMIC_AUDIO_CALLBACK callback; /*!< Event notification + callback function + pointer. */ + PMIC_AUDIO_EVENTS eventMask; /*!< Event notification mask. */ + PMIC_AUDIO_CLOCK_IN_SOURCE clockIn; /*!< Stereo DAC clock input + source select. */ + PMIC_AUDIO_STDAC_SAMPLING_RATE samplingRate; /*!< Stereo DAC sampling rate + select. */ + PMIC_AUDIO_STDAC_CLOCK_IN_FREQ clockFreq; /*!< Stereo DAC clock input + frequency. */ + PMIC_AUDIO_CLOCK_INVERT invert; /*!< Stereo DAC clock signal + invert select. */ + PMIC_AUDIO_STDAC_TIMESLOTS timeslot; /*!< Stereo DAC data + timeslots select. */ + PMIC_AUDIO_STDAC_CONFIG config; /*!< Stereo DAC configuration + options. */ +} PMIC_AUDIO_STDAC_STATE; + +/*! + * @brief This variable maintains the current state of the Stereo DAC. + * + * This variable tracks the current state of the Stereo DAC audio hardware + * along with any information that is required by the device driver to + * manage the hardware (e.g., callback functions and event notification + * masks). + * + * The initial values represent the reset/power on state of the Stereo DAC. + */ +static PMIC_AUDIO_STDAC_STATE stDAC = { + (PMIC_AUDIO_HANDLE) NULL, /* handle */ + HANDLE_FREE, /* handleState */ + AUDIO_DATA_BUS_1, /* busID */ + false, + NORMAL_MSB_JUSTIFIED_MODE, /* protocol */ + BUS_MASTER_MODE, /* masterSlave */ + USE_2_TIMESLOTS, /* numSlots */ + (PMIC_AUDIO_CALLBACK) NULL, /* callback */ + (PMIC_AUDIO_EVENTS) NULL, /* eventMask */ + CLOCK_IN_CLIA, /* clockIn */ + STDAC_RATE_44_1_KHZ, /* samplingRate */ + STDAC_CLI_13MHZ, /* clockFreq */ + NO_INVERT, /* invert */ + USE_TS0_TS1, /* timeslot */ + (PMIC_AUDIO_STDAC_CONFIG) 0 /* config */ +}; + +/*! + * @brief This structure maintains the current state of the Voice CODEC. + */ +typedef struct { + PMIC_AUDIO_HANDLE handle; /*!< Handle used to access + the Voice CODEC. */ + HANDLE_STATE handleState; /*!< Current handle state. */ + PMIC_AUDIO_DATA_BUS busID; /*!< Data bus used to access + the Voice CODEC. */ + bool protocol_set; + PMIC_AUDIO_BUS_PROTOCOL protocol; /*!< Data bus protocol. */ + PMIC_AUDIO_BUS_MODE masterSlave; /*!< Master/Slave mode + select. */ + PMIC_AUDIO_NUMSLOTS numSlots; /*!< Number of timeslots + used. */ + PMIC_AUDIO_CALLBACK callback; /*!< Event notification + callback function + pointer. */ + PMIC_AUDIO_EVENTS eventMask; /*!< Event notification + mask. */ + PMIC_AUDIO_CLOCK_IN_SOURCE clockIn; /*!< Voice CODEC clock input + source select. */ + PMIC_AUDIO_VCODEC_SAMPLING_RATE samplingRate; /*!< Voice CODEC sampling + rate select. */ + PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ clockFreq; /*!< Voice CODEC clock input + frequency. */ + PMIC_AUDIO_CLOCK_INVERT invert; /*!< Voice CODEC clock + signal invert select. */ + PMIC_AUDIO_VCODEC_TIMESLOT timeslot; /*!< Voice CODEC data + timeslot select. */ + PMIC_AUDIO_VCODEC_TIMESLOT secondaryTXtimeslot; + + PMIC_AUDIO_VCODEC_CONFIG config; /*!< Voice CODEC + configuration + options. */ + PMIC_MICROPHONE_STATE leftChannelMic; /*!< Left channel + microphone + configuration. */ + PMIC_MICROPHONE_STATE rightChannelMic; /*!< Right channel + microphone + configuration. */ +} PMIC_AUDIO_VCODEC_STATE; + +/*! + * @brief This variable maintains the current state of the Voice CODEC. + * + * This variable tracks the current state of the Voice CODEC audio hardware + * along with any information that is required by the device driver to + * manage the hardware (e.g., callback functions and event notification + * masks). + * + * The initial values represent the reset/power on state of the Voice CODEC. + */ +static PMIC_AUDIO_VCODEC_STATE vCodec = { + (PMIC_AUDIO_HANDLE) NULL, /* handle */ + HANDLE_FREE, /* handleState */ + AUDIO_DATA_BUS_2, /* busID */ + false, + NETWORK_MODE, /* protocol */ + BUS_SLAVE_MODE, /* masterSlave */ + USE_4_TIMESLOTS, /* numSlots */ + (PMIC_AUDIO_CALLBACK) NULL, /* callback */ + (PMIC_AUDIO_EVENTS) NULL, /* eventMask */ + CLOCK_IN_CLIB, /* clockIn */ + VCODEC_RATE_8_KHZ, /* samplingRate */ + VCODEC_CLI_13MHZ, /* clockFreq */ + NO_INVERT, /* invert */ + USE_TS0, /* timeslot pri */ + USE_TS2, /* timeslot sec TX */ + INPUT_HIGHPASS_FILTER | OUTPUT_HIGHPASS_FILTER, /* config */ + /* leftChannelMic */ + {NO_MIC, /* mic */ + MICROPHONE_OFF, /* micOnOff */ + AMP_OFF, /* ampMode */ + MIC_GAIN_0DB /* gain */ + }, + /* rightChannelMic */ + {NO_MIC, /* mic */ + MICROPHONE_OFF, /* micOnOff */ + AMP_OFF, /* ampMode */ + MIC_GAIN_0DB /* gain */ + } +}; + +/*! + * @brief This maintains the current state of the External Stereo Input. + */ +typedef struct { + PMIC_AUDIO_HANDLE handle; /*!< Handle used to access the + External Stereo Inputs. */ + HANDLE_STATE handleState; /*!< Current handle state. */ + PMIC_AUDIO_CALLBACK callback; /*!< Event notification callback + function pointer. */ + PMIC_AUDIO_EVENTS eventMask; /*!< Event notification mask. */ + PMIC_AUDIO_STEREO_IN_GAIN inputGain; /*!< External Stereo Input + amplifier gain level. */ +} PMIC_AUDIO_EXT_STEREO_IN_STATE; + +/*! + * @brief This maintains the current state of the External Stereo Input. + * + * This variable tracks the current state of the External Stereo Input audio + * hardware along with any information that is required by the device driver + * to manage the hardware (e.g., callback functions and event notification + * masks). + * + * The initial values represent the reset/power on state of the External + * Stereo Input. + */ +static PMIC_AUDIO_EXT_STEREO_IN_STATE extStereoIn = { + (PMIC_AUDIO_HANDLE) NULL, /* handle */ + HANDLE_FREE, /* handleState */ + (PMIC_AUDIO_CALLBACK) NULL, /* callback */ + (PMIC_AUDIO_EVENTS) NULL, /* eventMask */ + STEREO_IN_GAIN_0DB /* inputGain */ +}; + +/*! + * @brief This maintains the current state of the callback & Eventmask. + */ +typedef struct { + PMIC_AUDIO_CALLBACK callback; /*!< Event notification callback + function pointer. */ + PMIC_AUDIO_EVENTS eventMask; /*!< Event notification mask. */ +} PMIC_AUDIO_EVENT_STATE; + +static PMIC_AUDIO_EVENT_STATE event_state = { + (PMIC_AUDIO_CALLBACK) NULL, /*Callback */ + (PMIC_AUDIO_EVENTS) NULL, /* EventMask */ + +}; + +/*! + * @brief This maintains the current state of the Audio Output Section. + */ +typedef struct { + PMIC_AUDIO_OUTPUT_PORT outputPort; /*!< Current audio + output port. */ + PMIC_AUDIO_OUTPUT_PGA_GAIN vCodecoutputPGAGain; /*!< Output PGA gain + level codec */ + PMIC_AUDIO_OUTPUT_PGA_GAIN stDacoutputPGAGain; /*!< Output PGA gain + level stDAC */ + PMIC_AUDIO_OUTPUT_PGA_GAIN extStereooutputPGAGain; /*!< Output PGA gain + level stereo ext */ + PMIC_AUDIO_OUTPUT_BALANCE_GAIN balanceLeftGain; /*!< Left channel + balance gain + level. */ + PMIC_AUDIO_OUTPUT_BALANCE_GAIN balanceRightGain; /*!< Right channel + balance gain + level. */ + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN monoAdderGain; /*!< Mono adder gain + level. */ + PMIC_AUDIO_OUTPUT_CONFIG config; /*!< Audio output + section config + options. */ + PMIC_AUDIO_VCODEC_OUTPUT_PATH vCodecOut; + +} PMIC_AUDIO_AUDIO_OUTPUT_STATE; + +/*! + * @brief This variable maintains the current state of the Audio Output Section. + * + * This variable tracks the current state of the Audio Output Section. + * + * The initial values represent the reset/power on state of the Audio + * Output Section. + */ +static PMIC_AUDIO_AUDIO_OUTPUT_STATE audioOutput = { + (PMIC_AUDIO_OUTPUT_PORT) NULL, /* outputPort */ + OUTPGA_GAIN_0DB, /* outputPGAGain */ + OUTPGA_GAIN_0DB, /* outputPGAGain */ + OUTPGA_GAIN_0DB, /* outputPGAGain */ + BAL_GAIN_0DB, /* balanceLeftGain */ + BAL_GAIN_0DB, /* balanceRightGain */ + MONOADD_GAIN_0DB, /* monoAdderGain */ + (PMIC_AUDIO_OUTPUT_CONFIG) 0, /* config */ + VCODEC_DIRECT_OUT +}; + +/*! The current headset status. */ +static HEADSET_STATUS headsetState = NO_HEADSET; + +/* Removed PTT variable */ +/*! Define a 1 ms wait interval that is needed to ensure that certain + * hardware operations are successfully completed. + */ +static const unsigned long delay_1ms = (HZ / 1000); + +/*! + * @brief This spinlock is used to provide mutual exclusion. + * + * Create a spinlock that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * that were defined above. Mutually exclusive access is required to + * ensure that the audio data structures are consistent at all times + * when possibly accessed by multiple threads of execution (for example, + * while simultaneously handling a user request and an interrupt event). + * + * We need to use a spinlock whenever we do need to provide mutual + * exclusion while possibly executing in a hardware interrupt context. + * Spinlocks should be held for the minimum time that is necessary + * because hardware interrupts are disabled while a spinlock is held. + * + */ +static DEFINE_SPINLOCK(lock); + +/*! + * @brief This mutex is used to provide mutual exclusion. + * + * Create a mutex that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * that were defined above. Mutually exclusive access is required to + * ensure that the audio data structures are consistent at all times + * when possibly accessed by multiple threads of execution. + * + * Note that we use a mutex instead of the spinlock whenever disabling + * interrupts while in the critical section is not required. This helps + * to minimize kernel interrupt handling latency. + */ +static DECLARE_MUTEX(mutex); + +/*! + * @brief Global variable to track currently active interrupt events. + * + * This global variable is used to keep track of all of the currently + * active interrupt events for the audio driver. Note that access to this + * variable may occur while within an interrupt context and, therefore, + * must be guarded by using a spinlock. + */ +/* static PMIC_CORE_EVENT eventID = 0; */ + +/* Prototypes for all static audio driver functions. */ +/* +static PMIC_STATUS pmic_audio_mic_boost_enable(void); +static PMIC_STATUS pmic_audio_mic_boost_disable(void);*/ +static PMIC_STATUS pmic_audio_close_handle(const PMIC_AUDIO_HANDLE handle); +static PMIC_STATUS pmic_audio_reset_device(const PMIC_AUDIO_HANDLE handle); + +static PMIC_STATUS pmic_audio_deregister(void *callback, + PMIC_AUDIO_EVENTS * const eventMask); + +/************************************************************************* + * Audio device access APIs. + ************************************************************************* + */ + +/*! + * @name General Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Audio + * hardware. + */ +/*@{*/ + +PMIC_STATUS pmic_audio_set_autodetect(int val) +{ + PMIC_STATUS status; + unsigned int reg_mask = 0, reg_write = 0; + reg_mask = SET_BITS(regAUDIO_RX_0, VAUDIOON, 1); + status = pmic_write_reg(REG_AUDIO_RX_0, reg_mask, reg_mask); + if (status != PMIC_SUCCESS) + return status; + reg_mask = 0; + if (val == 1) { + reg_write = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + } else { + reg_write = 0; + } + reg_mask = + SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | SET_BITS(regAUDIO_RX_0, + HSDETAUTOB, 1); + status = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + + return status; +} + +/*! + * @brief Request exclusive access to the PMIC Audio hardware. + * + * Attempt to open and gain exclusive access to a key PMIC audio hardware + * component (e.g., the Stereo DAC or the Voice CODEC). Depending upon the + * type of audio operation that is desired and the nature of the audio data + * stream, the Stereo DAC and/or the Voice CODEC will be a required hardware + * component and needs to be acquired by calling this function. + * + * If the open request is successful, then a numeric handle is returned + * and this handle must be used in all subsequent function calls to complete + * the configuration of either the Stereo DAC or the Voice CODEC and along + * with any other associated audio hardware components that will be needed. + * + * The same handle must also be used in the close call when use of the PMIC + * audio hardware is no longer required. + * + * The open request will fail if the requested audio hardware component has + * already been acquired by a previous open call but not yet closed. + * + * @param handle Device handle to be used for subsequent PMIC + * audio API calls. + * @param device The required PMIC audio hardware component. + * + * @retval PMIC_SUCCESS If the open request was successful + * @retval PMIC_PARAMETER_ERROR If the handle argument is NULL. + * @retval PMIC_ERROR If the audio hardware component is + * unavailable. + */ +PMIC_STATUS pmic_audio_open(PMIC_AUDIO_HANDLE * const handle, + const PMIC_AUDIO_SOURCE device) +{ + PMIC_STATUS rc = PMIC_ERROR; + + if (handle == (PMIC_AUDIO_HANDLE *) NULL) { + /* Do not dereference a NULL pointer. */ + return PMIC_PARAMETER_ERROR; + } + + /* We only need to acquire a mutex here because the interrupt handler + * never modifies the device handle or device handle state. Therefore, + * we don't need to worry about conflicts with the interrupt handler + * or the need to execute in an interrupt context. + * + * But we do need a critical section here to avoid problems in case + * multiple calls to pmic_audio_open() are made since we can only allow + * one of them to succeed. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* Check the current device handle state and acquire the handle if + * it is available. + */ + + if ((device == STEREO_DAC) && (stDAC.handleState == HANDLE_FREE)) { + stDAC.handle = (PMIC_AUDIO_HANDLE) (&stDAC); + stDAC.handleState = HANDLE_IN_USE; + *handle = stDAC.handle; + rc = PMIC_SUCCESS; + } else if ((device == VOICE_CODEC) + && (vCodec.handleState == HANDLE_FREE)) { + vCodec.handle = (PMIC_AUDIO_HANDLE) (&vCodec); + vCodec.handleState = HANDLE_IN_USE; + *handle = vCodec.handle; + rc = PMIC_SUCCESS; + } else if ((device == EXTERNAL_STEREO_IN) && + (extStereoIn.handleState == HANDLE_FREE)) { + extStereoIn.handle = (PMIC_AUDIO_HANDLE) (&extStereoIn); + extStereoIn.handleState = HANDLE_IN_USE; + *handle = extStereoIn.handle; + rc = PMIC_SUCCESS; + } else { + *handle = AUDIO_HANDLE_NULL; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Terminate further access to the PMIC audio hardware. + * + * Terminate further access to the PMIC audio hardware that was previously + * acquired by calling pmic_audio_open(). This now allows another thread to + * successfully call pmic_audio_open() to gain access. + * + * Note that we will shutdown/reset the Voice CODEC or Stereo DAC as well as + * any associated audio input/output components that are no longer required. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the close request was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_close(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* We need a critical section here to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* We can now call pmic_audio_close_handle() to actually do the work. */ + rc = pmic_audio_close_handle(handle); + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Configure the data bus protocol to be used. + * + * Provide the parameters needed to properly configure the audio data bus + * protocol so that data can be read/written to either the Stereo DAC or + * the Voice CODEC. + * + * @param handle Device handle from pmic_audio_open() call. + * @param busID Select data bus to be used. + * @param protocol Select the data bus protocol. + * @param masterSlave Select the data bus timing mode. + * @param numSlots Define the number of timeslots (only if in + * master mode). + * + * @retval PMIC_SUCCESS If the protocol was successful configured. + * @retval PMIC_PARAMETER_ERROR If the handle or the protocol parameters + * are invalid. + */ +PMIC_STATUS pmic_audio_set_protocol(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_DATA_BUS busID, + const PMIC_AUDIO_BUS_PROTOCOL protocol, + const PMIC_AUDIO_BUS_MODE masterSlave, + const PMIC_AUDIO_NUMSLOTS numSlots) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int ST_DAC_MASK = SET_BITS(regST_DAC, STDCSSISEL, 1) | + SET_BITS(regST_DAC, STDCFS, 3) | SET_BITS(regST_DAC, STDCSM, 1); + + unsigned int reg_mask; + /*unsigned int VCODEC_MASK = SET_BITS(regAUD_CODEC, CDCSSISEL, 1) | + SET_BITS(regAUD_CODEC, CDCFS, 3) | SET_BITS(regAUD_CODEC, CDCSM, 1); */ + + unsigned int SSI_NW_MASK = SET_BITS(regSSI_NETWORK, STDCSLOTS, 1); + unsigned int reg_value = 0; + unsigned int ssi_nw_value = 0; + + /* Enter a critical section so that we can ensure only one + * state change request is completed at a time. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (handle == (PMIC_AUDIO_HANDLE) NULL) { + rc = PMIC_PARAMETER_ERROR; + } else { + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + if ((stDAC.handleState == HANDLE_IN_USE) && + (stDAC.busID == busID) && (stDAC.protocol_set)) { + pr_debug("The requested bus already in USE\n"); + rc = PMIC_PARAMETER_ERROR; + } else if ((masterSlave == BUS_MASTER_MODE) + && (numSlots != USE_4_TIMESLOTS)) { + pr_debug + ("mc13783 supports only 4 slots in Master mode\n"); + rc = PMIC_NOT_SUPPORTED; + } else if ((masterSlave == BUS_SLAVE_MODE) + && (numSlots != USE_4_TIMESLOTS)) { + pr_debug + ("Driver currently supports only 4 slots in Slave mode\n"); + rc = PMIC_NOT_SUPPORTED; + } else if (!((protocol == NETWORK_MODE) || + (protocol == I2S_MODE))) { + pr_debug + ("mc13783 Voice codec works only in Network and I2S modes\n"); + rc = PMIC_NOT_SUPPORTED; + } else { + pr_debug + ("Proceeding to configure Voice Codec\n"); + if (busID == AUDIO_DATA_BUS_1) { + reg_value = + SET_BITS(regAUD_CODEC, CDCSSISEL, + 0); + } else { + reg_value = + SET_BITS(regAUD_CODEC, CDCSSISEL, + 1); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCSSISEL, 1); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + if (masterSlave == BUS_MASTER_MODE) { + reg_value = + SET_BITS(regAUD_CODEC, CDCSM, 0); + } else { + reg_value = + SET_BITS(regAUD_CODEC, CDCSM, 1); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCSM, 1); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + if (protocol == NETWORK_MODE) { + reg_value = + SET_BITS(regAUD_CODEC, CDCFS, 1); + } else { /* protocol == I2S, other options have been already eliminated */ + reg_value = + SET_BITS(regAUD_CODEC, CDCFS, 2); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCFS, 3); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + ssi_nw_value = + SET_BITS(regSSI_NETWORK, CDCFSDLY, 1); + /*if (pmic_write_reg + (REG_AUDIO_CODEC, reg_value, + VCODEC_MASK) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { */ + vCodec.busID = busID; + vCodec.protocol = protocol; + vCodec.masterSlave = masterSlave; + vCodec.numSlots = numSlots; + vCodec.protocol_set = true; + + pr_debug + ("mc13783 Voice codec successfully configured\n"); + rc = PMIC_SUCCESS; + } + + } else if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + if ((vCodec.handleState == HANDLE_IN_USE) && + (vCodec.busID == busID) && (vCodec.protocol_set)) { + pr_debug("The requested bus already in USE\n"); + rc = PMIC_PARAMETER_ERROR; + } else if (((protocol == NORMAL_MSB_JUSTIFIED_MODE) || + (protocol == I2S_MODE)) + && (numSlots != USE_2_TIMESLOTS)) { + pr_debug + ("STDAC uses only 2 slots in Normal and I2S modes\n"); + rc = PMIC_PARAMETER_ERROR; + } else if ((protocol == NETWORK_MODE) && + !((numSlots == USE_2_TIMESLOTS) || + (numSlots == USE_4_TIMESLOTS) || + (numSlots == USE_8_TIMESLOTS))) { + pr_debug + ("STDAC uses only 2,4 or 8 slots in Network mode\n"); + rc = PMIC_PARAMETER_ERROR; + } else if (protocol == SPD_IF_MODE) { + pr_debug + ("STDAC driver currently does not support SPD IF mode\n"); + rc = PMIC_NOT_SUPPORTED; + } else { + pr_debug + ("Proceeding to configure Stereo DAC\n"); + if (busID == AUDIO_DATA_BUS_1) { + reg_value = + SET_BITS(regST_DAC, STDCSSISEL, 0); + } else { + reg_value = + SET_BITS(regST_DAC, STDCSSISEL, 1); + } + if (masterSlave == BUS_MASTER_MODE) { + reg_value |= + SET_BITS(regST_DAC, STDCSM, 0); + } else { + reg_value |= + SET_BITS(regST_DAC, STDCSM, 1); + } + if (protocol == NETWORK_MODE) { + reg_value |= + SET_BITS(regST_DAC, STDCFS, 1); + } else if (protocol == + NORMAL_MSB_JUSTIFIED_MODE) { + reg_value |= + SET_BITS(regST_DAC, STDCFS, 0); + } else { /* I2S mode as the other option has already been eliminated */ + reg_value |= + SET_BITS(regST_DAC, STDCFS, 2); + } + + if (pmic_write_reg + (REG_AUDIO_STEREO_DAC, + reg_value, ST_DAC_MASK) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + if (numSlots == USE_2_TIMESLOTS) { + reg_value = + SET_BITS(regSSI_NETWORK, + STDCSLOTS, 3); + } else if (numSlots == USE_4_TIMESLOTS) { + reg_value = + SET_BITS(regSSI_NETWORK, + STDCSLOTS, 2); + } else { /* Use 8 timeslots - L , R and 6 other */ + reg_value = + SET_BITS(regSSI_NETWORK, + STDCSLOTS, 1); + } + if (pmic_write_reg + (REG_AUDIO_SSI_NETWORK, + reg_value, + SSI_NW_MASK) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + stDAC.busID = busID; + stDAC.protocol = protocol; + stDAC.protocol_set = true; + stDAC.masterSlave = masterSlave; + stDAC.numSlots = numSlots; + pr_debug + ("mc13783 Stereo DAC successfully configured\n"); + rc = PMIC_SUCCESS; + } + } + + } + } else { + rc = PMIC_PARAMETER_ERROR; + /* Handle can only be Voice Codec or Stereo DAC */ + pr_debug("Handles only STDAC and VCODEC\n"); + } + + } + /* Exit critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Retrieve the current data bus protocol configuration. + * + * Retrieve the parameters that define the current audio data bus protocol. + * + * @param handle Device handle from pmic_audio_open() call. + * @param busID The data bus being used. + * @param protocol The data bus protocol being used. + * @param masterSlave The data bus timing mode being used. + * @param numSlots The number of timeslots being used (if in + * master mode). + * + * @retval PMIC_SUCCESS If the protocol was successful retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_get_protocol(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_DATA_BUS * const busID, + PMIC_AUDIO_BUS_PROTOCOL * const protocol, + PMIC_AUDIO_BUS_MODE * const masterSlave, + PMIC_AUDIO_NUMSLOTS * const numSlots) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + if ((busID != (PMIC_AUDIO_DATA_BUS *) NULL) && + (protocol != (PMIC_AUDIO_BUS_PROTOCOL *) NULL) && + (masterSlave != (PMIC_AUDIO_BUS_MODE *) NULL) && + (numSlots != (PMIC_AUDIO_NUMSLOTS *) NULL)) { + /* Enter a critical section so that we return a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + *busID = stDAC.busID; + *protocol = stDAC.protocol; + *masterSlave = stDAC.masterSlave; + *numSlots = stDAC.numSlots; + rc = PMIC_SUCCESS; + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + *busID = vCodec.busID; + *protocol = vCodec.protocol; + *masterSlave = vCodec.masterSlave; + *numSlots = vCodec.numSlots; + rc = PMIC_SUCCESS; + } + + /* Exit critical section. */ + up(&mutex); + } + + return rc; +} + +/*! + * @brief Enable the Stereo DAC or the Voice CODEC. + * + * Explicitly enable the Stereo DAC or the Voice CODEC to begin audio + * playback or recording as required. This should only be done after + * successfully configuring all of the associated audio components (e.g., + * microphones, amplifiers, etc.). + * + * Note that the timed delays used in this function are necessary to + * ensure reliable operation of the Voice CODEC and Stereo DAC. The + * Stereo DAC seems to be particularly sensitive and it has been observed + * to fail to generate the required master mode clock signals if it is + * not allowed enough time to initialize properly. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the device was successful enabled. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the device could not be enabled. + */ +PMIC_STATUS pmic_audio_enable(const PMIC_AUDIO_HANDLE handle) +{ + const unsigned int AUDIO_BIAS_ENABLE = SET_BITS(regAUDIO_RX_0, + VAUDIOON, 1); + const unsigned int STDAC_ENABLE = SET_BITS(regST_DAC, STDCEN, 1); + const unsigned int VCODEC_ENABLE = SET_BITS(regAUD_CODEC, CDCEN, 1); + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + pmic_write_reg(REG_AUDIO_RX_0, AUDIO_BIAS_ENABLE, + AUDIO_BIAS_ENABLE); + reg_mask = + SET_BITS(regAUDIO_RX_0, HSDETEN, + 1) | SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + reg_write = + SET_BITS(regAUDIO_RX_0, HSDETEN, + 1) | SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + if (rc == PMIC_SUCCESS) + pr_debug("pmic_audio_enable\n"); + /* We can enable the Stereo DAC. */ + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, + STDAC_ENABLE, STDAC_ENABLE); + /*pmic_read_reg(REG_AUDIO_STEREO_DAC, ®_value); */ + if (rc != PMIC_SUCCESS) { + pr_debug("Failed to enable the Stereo DAC\n"); + rc = PMIC_ERROR; + } + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE)) { + /* Must first set the audio bias bit to power up the audio circuits. */ + pmic_write_reg(REG_AUDIO_RX_0, AUDIO_BIAS_ENABLE, + AUDIO_BIAS_ENABLE); + reg_mask = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + reg_write = SET_BITS(regAUDIO_RX_0, HSDETEN, 1) | + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + + /* Then we can enable the Voice CODEC. */ + rc = pmic_write_reg(REG_AUDIO_CODEC, VCODEC_ENABLE, + VCODEC_ENABLE); + + /* pmic_read_reg(REG_AUDIO_CODEC, ®_value); */ + if (rc != PMIC_SUCCESS) { + pr_debug("Failed to enable the Voice codec\n"); + rc = PMIC_ERROR; + } + } + /* Exit critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Disable the Stereo DAC or the Voice CODEC. + * + * Explicitly disable the Stereo DAC or the Voice CODEC to end audio + * playback or recording as required. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the device was successful disabled. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the device could not be disabled. + */ +PMIC_STATUS pmic_audio_disable(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int STDAC_DISABLE = SET_BITS(regST_DAC, STDCEN, 1); + const unsigned int VCODEC_DISABLE = SET_BITS(regAUD_CODEC, CDCEN, 1); + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, 0, STDAC_DISABLE); + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_CODEC, 0, VCODEC_DISABLE); + } + if (rc == PMIC_SUCCESS) { + pr_debug("Disabled successfully\n"); + } + /* Exit critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Reset the selected audio hardware control registers to their + * power on state. + * + * This resets all of the audio hardware control registers currently + * associated with the device handle back to their power on states. For + * example, if the handle is associated with the Stereo DAC and a + * specific output port and output amplifiers, then this function will + * reset all of those components to their initial power on state. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +PMIC_STATUS pmic_audio_reset(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + rc = pmic_audio_reset_device(handle); + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Reset all audio hardware control registers to their power on state. + * + * This resets all of the audio hardware control registers back to their + * power on states. Use this function with care since it also invalidates + * (i.e., automatically closes) all currently opened device handles. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +PMIC_STATUS pmic_audio_reset_all(void) +{ + PMIC_STATUS rc = PMIC_SUCCESS; + unsigned int audio_ssi_reset = 0; + unsigned int audio_rx1_reset = 0; + /* We need a critical section here to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* First close all opened device handles, also deregisters callbacks. */ + pmic_audio_close_handle(stDAC.handle); + pmic_audio_close_handle(vCodec.handle); + pmic_audio_close_handle(extStereoIn.handle); + + if (pmic_write_reg(REG_AUDIO_RX_1, RESET_AUDIO_RX_1, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + audio_rx1_reset = 1; + } + if (pmic_write_reg(REG_AUDIO_SSI_NETWORK, RESET_SSI_NETWORK, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + audio_ssi_reset = 1; + } + if (pmic_write_reg + (REG_AUDIO_STEREO_DAC, RESET_ST_DAC, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + /* Also reset the driver state information to match. Note that we + * keep the device handle and event callback settings unchanged + * since these don't affect the actual hardware and we rely on + * the user to explicitly close the handle or deregister callbacks + */ + if (audio_ssi_reset) { + /* better to check if SSI is also reset as some fields are represennted in SSI reg */ + stDAC.busID = AUDIO_DATA_BUS_1; + stDAC.protocol = NORMAL_MSB_JUSTIFIED_MODE; + stDAC.masterSlave = BUS_MASTER_MODE; + stDAC.protocol_set = false; + stDAC.numSlots = USE_2_TIMESLOTS; + stDAC.clockIn = CLOCK_IN_CLIA; + stDAC.samplingRate = STDAC_RATE_44_1_KHZ; + stDAC.clockFreq = STDAC_CLI_13MHZ; + stDAC.invert = NO_INVERT; + stDAC.timeslot = USE_TS0_TS1; + stDAC.config = (PMIC_AUDIO_STDAC_CONFIG) 0; + } + } + + if (pmic_write_reg(REG_AUDIO_CODEC, RESET_AUD_CODEC, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + /* Also reset the driver state information to match. Note that we + * keep the device handle and event callback settings unchanged + * since these don't affect the actual hardware and we rely on + * the user to explicitly close the handle or deregister callbacks + */ + if (audio_ssi_reset) { + vCodec.busID = AUDIO_DATA_BUS_2; + vCodec.protocol = NETWORK_MODE; + vCodec.masterSlave = BUS_SLAVE_MODE; + vCodec.protocol_set = false; + vCodec.numSlots = USE_4_TIMESLOTS; + vCodec.clockIn = CLOCK_IN_CLIB; + vCodec.samplingRate = VCODEC_RATE_8_KHZ; + vCodec.clockFreq = VCODEC_CLI_13MHZ; + vCodec.invert = NO_INVERT; + vCodec.timeslot = USE_TS0; + vCodec.config = + INPUT_HIGHPASS_FILTER | OUTPUT_HIGHPASS_FILTER; + } + } + + if (pmic_write_reg(REG_AUDIO_RX_0, RESET_AUDIO_RX_0, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + /* Also reset the driver state information to match. */ + audioOutput.outputPort = (PMIC_AUDIO_OUTPUT_PORT) NULL; + audioOutput.vCodecoutputPGAGain = OUTPGA_GAIN_0DB; + audioOutput.stDacoutputPGAGain = OUTPGA_GAIN_0DB; + audioOutput.extStereooutputPGAGain = OUTPGA_GAIN_0DB; + audioOutput.balanceLeftGain = BAL_GAIN_0DB; + audioOutput.balanceRightGain = BAL_GAIN_0DB; + audioOutput.monoAdderGain = MONOADD_GAIN_0DB; + audioOutput.config = (PMIC_AUDIO_OUTPUT_CONFIG) 0; + audioOutput.vCodecOut = VCODEC_DIRECT_OUT; + } + + if (pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX, + PMIC_ALL_BITS) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + /* Also reset the driver state information to match. Note that we + * reset the vCodec fields since all of the input/recording + * devices are only connected to the Voice CODEC and are managed + * as part of the Voice CODEC state. + */ + if (audio_rx1_reset) { + vCodec.leftChannelMic.mic = NO_MIC; + vCodec.leftChannelMic.micOnOff = MICROPHONE_OFF; + vCodec.leftChannelMic.ampMode = CURRENT_TO_VOLTAGE; + vCodec.leftChannelMic.gain = MIC_GAIN_0DB; + vCodec.rightChannelMic.mic = NO_MIC; + vCodec.rightChannelMic.micOnOff = MICROPHONE_OFF; + vCodec.rightChannelMic.ampMode = AMP_OFF; + vCodec.rightChannelMic.gain = MIC_GAIN_0DB; + } + } + /* Finally, also reset any global state variables. */ + headsetState = NO_HEADSET; + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Set the Audio callback function. + * + * Register a callback function that will be used to signal PMIC audio + * events. For example, the OSS audio driver should register a callback + * function in order to be notified of headset connect/disconnect events. + * + * @param func A pointer to the callback function. + * @param eventMask A mask selecting events to be notified. + * @param hs_state To know the headset state. + * + * + * + * @retval PMIC_SUCCESS If the callback was successfully + * registered. + * @retval PMIC_PARAMETER_ERROR If the handle or the eventMask is invalid. + */ +PMIC_STATUS pmic_audio_set_callback(void *func, + const PMIC_AUDIO_EVENTS eventMask, + PMIC_HS_STATE *hs_state) +{ + unsigned long flags; + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + pmic_event_callback_t eventNotify; + + /* We need to start a critical section here to ensure a consistent state + * in case simultaneous calls to pmic_audio_set_callback() are made. In + * that case, we must serialize the calls to ensure that the "callback" + * and "eventMask" state variables are always consistent. + * + * Note that we don't actually need to acquire the spinlock until later + * when we are finally ready to update the "callback" and "eventMask" + * state variables which are shared with the interrupt handler. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + rc = PMIC_ERROR; + /* Register for PMIC events from the core protocol driver. */ + if (eventMask & MICROPHONE_DETECTED) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_MC2BI); + rc = pmic_event_subscribe(EVENT_MC2BI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_HSDETI " + "failed\n", __FILE__); + goto End; + } + } + + if (eventMask & HEADSET_DETECTED) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_HSDETI); + rc = pmic_event_subscribe(EVENT_HSDETI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_HSDETI " + "failed\n", __FILE__); + goto Cleanup_HDT; + } + + } + if (eventMask & HEADSET_STEREO) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_HSLI); + rc = pmic_event_subscribe(EVENT_HSLI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_HSLI " + "failed\n", __FILE__); + goto Cleanup_HST; + } + } + if (eventMask & HEADSET_THERMAL_SHUTDOWN) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_ALSPTHI); + rc = pmic_event_subscribe(EVENT_ALSPTHI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_ALSPTHI " + "failed\n", __FILE__); + goto Cleanup_TSD; + } + pr_debug("Registered for EVENT_ALSPTHI\n"); + } + if (eventMask & HEADSET_SHORT_CIRCUIT) { + /* We need to register for the A1 amplifier interrupt. */ + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI); + rc = pmic_event_subscribe(EVENT_AHSSHORTI, eventNotify); + + if (rc != PMIC_SUCCESS) { + pr_debug + ("%s: pmic_event_subscribe() for EVENT_AHSSHORTI " + "failed\n", __FILE__); + goto Cleanup_HShort; + } + pr_debug("Registered for EVENT_AHSSHORTI\n"); + } + + /* We also need the spinlock here to avoid possible problems + * with the interrupt handler when we update the + * "callback" and "eventMask" state variables. + */ + spin_lock_irqsave(&lock, flags); + + /* Successfully registered for all events. */ + event_state.callback = func; + event_state.eventMask = eventMask; + + /* The spinlock is no longer needed now that we've finished + * updating the "callback" and "eventMask" state variables. + */ + spin_unlock_irqrestore(&lock, flags); + + goto End; + + /* This section unregisters any already registered events if we should + * encounter an error partway through the registration process. Note + * that we don't check the return status here since it is already set + * to PMIC_ERROR before we get here. + */ + Cleanup_HShort: + + if (eventMask & HEADSET_SHORT_CIRCUIT) { + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI); + pmic_event_unsubscribe(EVENT_AHSSHORTI, eventNotify); + } + + Cleanup_TSD: + + if (eventMask & HEADSET_THERMAL_SHUTDOWN) { + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_ALSPTHI); + pmic_event_unsubscribe(EVENT_ALSPTHI, eventNotify); + } + + Cleanup_HST: + + if (eventMask & HEADSET_STEREO) { + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_HSLI); + pmic_event_unsubscribe(EVENT_HSLI, eventNotify); + } + + Cleanup_HDT: + + if (eventMask & HEADSET_DETECTED) { + eventNotify.func = func; + eventNotify.param = (void *)(CORE_EVENT_HSDETI); + pmic_event_unsubscribe(EVENT_HSDETI, eventNotify); + } + + End: + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Deregisters the existing audio callback function. + * + * Deregister the callback function that was previously registered by calling + * pmic_audio_set_callback(). + * + * + * @retval PMIC_SUCCESS If the callback was successfully + * deregistered. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_clear_callback(void) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* We need a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (event_state.callback != (PMIC_AUDIO_CALLBACK) NULL) { + rc = pmic_audio_deregister(&(event_state.callback), + &(event_state.eventMask)); + } + + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Get the current audio callback function settings. + * + * Get the current callback function and event mask. + * + * @param func The current callback function. + * @param eventMask The current event selection mask. + * + * @retval PMIC_SUCCESS If the callback information was + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +PMIC_STATUS pmic_audio_get_callback(PMIC_AUDIO_CALLBACK * const func, + PMIC_AUDIO_EVENTS * const eventMask) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* We only need to acquire the mutex here because we will not be updating + * anything that may affect the interrupt handler. We just need to ensure + * that the callback fields are not changed while we are in the critical + * section by calling either pmic_audio_set_callback() or + * pmic_audio_clear_callback(). + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((func != (PMIC_AUDIO_CALLBACK *) NULL) && + (eventMask != (PMIC_AUDIO_EVENTS *) NULL)) { + + *func = event_state.callback; + *eventMask = event_state.eventMask; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Enable the anti-pop circuitry to avoid extra noise when inserting + * or removing a external device (e.g., a headset). + * + * Enable the use of the built-in anti-pop circuitry to prevent noise from + * being generated when an external audio device is inserted or removed + * from an audio plug. A slow ramp speed may be needed to avoid extra noise. + * + * @param rampSpeed The desired anti-pop circuitry ramp speed. + * + * @retval PMIC_SUCCESS If the anti-pop circuitry was successfully + * enabled. + * @retval PMIC_ERROR If the anti-pop circuitry could not be + * enabled. + */ +PMIC_STATUS pmic_audio_antipop_enable(const PMIC_AUDIO_ANTI_POP_RAMP_SPEED + rampSpeed) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, BIASEN, 1) | + SET_BITS(regAUDIO_RX_0, BIASSPEED, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + /* + * Antipop is enabled by enabling the BIAS (BIASEN) and setting the + * BIASSPEED . + * BIASEN is just to make sure that BIAS is enabled + */ + reg_value = SET_BITS(regAUDIO_RX_0, BIASEN, 1) + | SET_BITS(regAUDIO_RX_0, BIASSPEED, 0) | SET_BITS(regAUDIO_RX_0, + HSLDETEN, 1); + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_value, reg_mask); + return rc; +} + +/*! + * @brief Disable the anti-pop circuitry. + * + * Disable the use of the built-in anti-pop circuitry to prevent noise from + * being generated when an external audio device is inserted or removed + * from an audio plug. + * + * @retval PMIC_SUCCESS If the anti-pop circuitry was successfully + * disabled. + * @retval PMIC_ERROR If the anti-pop circuitry could not be + * disabled. + */ +PMIC_STATUS pmic_audio_antipop_disable(void) +{ + PMIC_STATUS rc = PMIC_ERROR; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, BIASSPEED, 1) | + SET_BITS(regAUDIO_RX_0, BIASEN, 1); + const unsigned int reg_write = SET_BITS(regAUDIO_RX_0, BIASSPEED, 1) | + SET_BITS(regAUDIO_RX_0, BIASEN, 0); + + /* No critical section required here since we are not updating any + * global data. + */ + + /* + * Antipop is disabled by setting BIASSPEED = 0. BIASEN bit remains set + * as only antipop needs to be disabled + */ + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + + return rc; +} + +/*! + * @brief Performs a reset of the Voice CODEC/Stereo DAC digital filter. + * + * The digital filter should be reset whenever the clock or sampling rate + * configuration has been changed. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the digital filter was successfully + * reset. + * @retval PMIC_ERROR If the digital filter could not be reset. + */ +PMIC_STATUS pmic_audio_digital_filter_reset(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regST_DAC, STDCRESET, 1); + if (pmic_write_reg(REG_AUDIO_STEREO_DAC, reg_mask, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("STDAC filter reset\n"); + } + + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUD_CODEC, CDCRESET, 1); + if (pmic_write_reg(REG_AUDIO_CODEC, reg_mask, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("CODEC filter reset\n"); + } + } + return rc; +} + +/*! + * @brief Get the most recent PTT button voltage reading. + * + * This feature is not supported by mc13783 + * @param level PTT button level. + * + * @retval PMIC_SUCCESS If the most recent PTT button voltage was + * returned. + * @retval PMIC_PARAMETER_ERROR If a NULL pointer argument was given. + */ +PMIC_STATUS pmic_audio_get_ptt_button_level(unsigned int *const level) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +#ifdef DEBUG_AUDIO + +/*! + * @brief Provide a hexadecimal dump of all PMIC audio registers (DEBUG only) + * + * This function is intended strictly for debugging purposes only and will + * print the current values of the following PMIC registers: + * + * - AUD_CODEC + * - ST_DAC + * - AUDIO_RX_0 + * - AUDIO_RX_1 + * - AUDIO_TX + * - AUDIO_SSI_NW + * + * The register fields will not be decoded. + * + * Note that we don't dump any of the arbitration bits because we cannot + * access the true arbitration bit settings when reading the registers + * from the secondary SPI bus. + * + * Also note that we must not call this function with interrupts disabled, + * for example, while holding a spinlock, because calls to pmic_read_reg() + * eventually end up in the SPI driver which will want to perform a + * schedule() operation. If schedule() is called with interrupts disabled, + * then you will see messages like the following: + * + * BUG: scheduling while atomic: ... + * + */ +void pmic_audio_dump_registers(void) +{ + unsigned int reg_value = 0; + + /* Dump the AUD_CODEC (Voice CODEC) register. */ + if (pmic_read_reg(REG_AUDIO_CODEC, ®_value, REG_FULLMASK) + == PMIC_SUCCESS) { + pr_debug("Audio Codec = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read audio codec\n"); + } + + /* Dump the ST DAC (Stereo DAC) register. */ + if (pmic_read_reg + (REG_AUDIO_STEREO_DAC, ®_value, REG_FULLMASK) == PMIC_SUCCESS) { + pr_debug("Stereo DAC = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read Stereo DAC\n"); + } + + /* Dump the SSI NW register. */ + if (pmic_read_reg + (REG_AUDIO_SSI_NETWORK, ®_value, REG_FULLMASK) == PMIC_SUCCESS) { + pr_debug("SSI Network = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read SSI network\n"); + } + + /* Dump the Audio RX 0 register. */ + if (pmic_read_reg(REG_AUDIO_RX_0, ®_value, REG_FULLMASK) + == PMIC_SUCCESS) { + pr_debug("Audio RX 0 = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read audio RX 0\n"); + } + + /* Dump the Audio RX 1 register. */ + if (pmic_read_reg(REG_AUDIO_RX_1, ®_value, REG_FULLMASK) + == PMIC_SUCCESS) { + pr_debug("Audio RX 1 = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read audio RX 1\n"); + } + /* Dump the Audio TX register. */ + if (pmic_read_reg(REG_AUDIO_TX, ®_value, REG_FULLMASK) == + PMIC_SUCCESS) { + pr_debug("Audio Tx = 0x%x\n", reg_value); + } else { + pr_debug("Failed to read audio TX\n"); + } + +} + +#endif /* DEBUG_AUDIO */ + +/*@}*/ + +/************************************************************************* + * General Voice CODEC configuration. + ************************************************************************* + */ + +/*! + * @name General Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice + * CODEC hardware. + */ +/*@{*/ + +/*! + * @brief Set the Voice CODEC clock source and operating characteristics. + * + * Define the Voice CODEC clock source and operating characteristics. This + * must be done before the Voice CODEC is enabled. + * + * + * + * @param handle Device handle from pmic_audio_open() call. + * @param clockIn Select the clock signal source. + * @param clockFreq Select the clock signal frequency. + * @param samplingRate Select the audio data sampling rate. + * @param invert Enable inversion of the frame sync and/or + * bit clock inputs. + * + * @retval PMIC_SUCCESS If the Voice CODEC clock settings were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or clock configuration was + * invalid. + * @retval PMIC_ERROR If the Voice CODEC clock configuration + * could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_clock(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_CLOCK_IN_SOURCE + clockIn, + const PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ + clockFreq, + const PMIC_AUDIO_VCODEC_SAMPLING_RATE + samplingRate, + const PMIC_AUDIO_CLOCK_INVERT invert) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* Validate all of the calling parameters. */ + if (handle == (PMIC_AUDIO_HANDLE) NULL) { + rc = PMIC_PARAMETER_ERROR; + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + if ((clockIn != CLOCK_IN_CLIA) && (clockIn != CLOCK_IN_CLIB)) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((clockFreq >= VCODEC_CLI_13MHZ) + && (clockFreq <= VCODEC_CLI_33_6MHZ))) { + rc = PMIC_PARAMETER_ERROR; + } else if ((samplingRate != VCODEC_RATE_8_KHZ) + && (samplingRate != VCODEC_RATE_16_KHZ)) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((invert >= NO_INVERT) + && (invert <= INVERT_FRAMESYNC))) { + rc = PMIC_PARAMETER_ERROR; + } else { + /*reg_mask = SET_BITS(regAUD_CODEC, CDCCLK, 7) | + SET_BITS(regAUD_CODEC, CDCCLKSEL, 1) | + SET_BITS(regAUD_CODEC, CDCFS8K16K, 1) | + SET_BITS(regAUD_CODEC, CDCBCLINV, 1) | + SET_BITS(regAUD_CODEC, CDCFSINV, 1); */ + if (clockIn == CLOCK_IN_CLIA) { + reg_value = + SET_BITS(regAUD_CODEC, CDCCLKSEL, 0); + } else { + reg_value = + SET_BITS(regAUD_CODEC, CDCCLKSEL, 1); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCCLKSEL, 1); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + reg_value = 0; + if (clockFreq == VCODEC_CLI_13MHZ) { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 0); + } else if (clockFreq == VCODEC_CLI_15_36MHZ) { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 1); + } else if (clockFreq == VCODEC_CLI_16_8MHZ) { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 2); + } else if (clockFreq == VCODEC_CLI_26MHZ) { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 4); + } else { + reg_value |= SET_BITS(regAUD_CODEC, CDCCLK, 7); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCCLK, 7); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + + reg_value = 0; + reg_mask = 0; + + if (samplingRate == VCODEC_RATE_8_KHZ) { + reg_value |= + SET_BITS(regAUD_CODEC, CDCFS8K16K, 0); + } else { + reg_value |= + SET_BITS(regAUD_CODEC, CDCFS8K16K, 1); + } + reg_mask = SET_BITS(regAUD_CODEC, CDCFS8K16K, 1); + if (PMIC_SUCCESS != + pmic_write_reg(REG_AUDIO_CODEC, + reg_value, reg_mask)) + return PMIC_ERROR; + reg_value = 0; + reg_mask = + SET_BITS(regAUD_CODEC, CDCBCLINV, + 1) | SET_BITS(regAUD_CODEC, CDCFSINV, 1); + + if (invert & INVERT_BITCLOCK) { + reg_value |= + SET_BITS(regAUD_CODEC, CDCBCLINV, 1); + } + if (invert & INVERT_FRAMESYNC) { + reg_value |= + SET_BITS(regAUD_CODEC, CDCFSINV, 1); + } + if (invert & NO_INVERT) { + reg_value |= + SET_BITS(regAUD_CODEC, CDCBCLINV, 0); + reg_value |= + SET_BITS(regAUD_CODEC, CDCFSINV, 0); + } + if (pmic_write_reg + (REG_AUDIO_CODEC, reg_value, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("CODEC clock set\n"); + vCodec.clockIn = clockIn; + vCodec.clockFreq = clockFreq; + vCodec.samplingRate = samplingRate; + vCodec.invert = invert; + } + + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the Voice CODEC clock source and operating characteristics. + * + * Get the current Voice CODEC clock source and operating characteristics. + * + * @param handle Device handle from pmic_audio_open() call. + * @param clockIn The clock signal source. + * @param clockFreq The clock signal frequency. + * @param samplingRate The audio data sampling rate. + * @param invert Inversion of the frame sync and/or + * bit clock inputs is enabled/disabled. + * + * @retval PMIC_SUCCESS If the Voice CODEC clock settings were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle invalid. + * @retval PMIC_ERROR If the Voice CODEC clock configuration + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_clock(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_CLOCK_IN_SOURCE * + const clockIn, + PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ * + const clockFreq, + PMIC_AUDIO_VCODEC_SAMPLING_RATE * + const samplingRate, + PMIC_AUDIO_CLOCK_INVERT * const invert) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure that we return a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (clockIn != (PMIC_AUDIO_CLOCK_IN_SOURCE *) NULL) && + (clockFreq != (PMIC_AUDIO_VCODEC_CLOCK_IN_FREQ *) NULL) && + (samplingRate != (PMIC_AUDIO_VCODEC_SAMPLING_RATE *) NULL) && + (invert != (PMIC_AUDIO_CLOCK_INVERT *) NULL)) { + *clockIn = vCodec.clockIn; + *clockFreq = vCodec.clockFreq; + *samplingRate = vCodec.samplingRate; + *invert = vCodec.invert; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the Voice CODEC primary audio channel timeslot. + * + * Set the Voice CODEC primary audio channel timeslot. This function must be + * used if the default timeslot for the primary audio channel is to be changed. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot Select the primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC primary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC primary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_TIMESLOT + timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + const unsigned int reg_mask = SET_BITS(regSSI_NETWORK, CDCTXRXSLOT, 3); + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + ((timeslot == USE_TS0) || (timeslot == USE_TS1) || + (timeslot == USE_TS2) || (timeslot == USE_TS3))) { + reg_write = SET_BITS(regSSI_NETWORK, CDCTXRXSLOT, timeslot); + + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + vCodec.timeslot = timeslot; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current Voice CODEC primary audio channel timeslot. + * + * Get the current Voice CODEC primary audio channel timeslot. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot The primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC primary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC primary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_VCODEC_TIMESLOT * + const timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (timeslot != (PMIC_AUDIO_VCODEC_TIMESLOT *) NULL)) { + *timeslot = vCodec.timeslot; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the Voice CODEC secondary recording audio channel timeslot. + * + * Set the Voice CODEC secondary audio channel timeslot. This function must be + * used if the default timeslot for the secondary audio channel is to be + * changed. The secondary audio channel timeslot is used to transmit the audio + * data that was recorded by the Voice CODEC from the secondary audio input + * channel. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot Select the secondary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC secondary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC secondary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_vcodec_set_secondary_txslot(const PMIC_AUDIO_HANDLE + handle, + const + PMIC_AUDIO_VCODEC_TIMESLOT + timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = SET_BITS(regSSI_NETWORK, CDCTXSECSLOT, 3); + unsigned int reg_write = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + /* How to handle primary slot and secondary slot being the same */ + if ((timeslot >= USE_TS0) && (timeslot <= USE_TS3) + && (timeslot != vCodec.timeslot)) { + reg_write = + SET_BITS(regSSI_NETWORK, CDCTXSECSLOT, timeslot); + + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + vCodec.secondaryTXtimeslot = timeslot; + } + } + + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the Voice CODEC secondary recording audio channel timeslot. + * + * Get the Voice CODEC secondary audio channel timeslot. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot The secondary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Voice CODEC secondary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC secondary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_secondary_txslot(const PMIC_AUDIO_HANDLE + handle, + PMIC_AUDIO_VCODEC_TIMESLOT * + const timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (timeslot != (PMIC_AUDIO_VCODEC_TIMESLOT *) NULL)) { + rc = PMIC_SUCCESS; + *timeslot = vCodec.secondaryTXtimeslot; + } + + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Set/Enable the Voice CODEC options. + * + * Set or enable various Voice CODEC options. The available options include + * the use of dithering, highpass digital filters, and loopback modes. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The Voice CODEC options to enable. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or Voice CODEC options + * were invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * successfully set/enabled. + */ +PMIC_STATUS pmic_audio_vcodec_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_CONFIG config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (config & DITHERING) { + reg_write = SET_BITS(regAUD_CODEC, CDCDITH, 0); + reg_mask = SET_BITS(regAUD_CODEC, CDCDITH, 1); + } + + if (config & INPUT_HIGHPASS_FILTER) { + reg_write |= SET_BITS(regAUD_CODEC, AUDIHPF, 1); + reg_mask |= SET_BITS(regAUD_CODEC, AUDIHPF, 1); + } + + if (config & OUTPUT_HIGHPASS_FILTER) { + reg_write |= SET_BITS(regAUD_CODEC, AUDOHPF, 1); + reg_mask |= SET_BITS(regAUD_CODEC, AUDOHPF, 1); + } + + if (config & DIGITAL_LOOPBACK) { + reg_write |= SET_BITS(regAUD_CODEC, CDCDLM, 1); + reg_mask |= SET_BITS(regAUD_CODEC, CDCDLM, 1); + } + + if (config & ANALOG_LOOPBACK) { + reg_write |= SET_BITS(regAUD_CODEC, CDCALM, 1); + reg_mask |= SET_BITS(regAUD_CODEC, CDCALM, 1); + } + + if (config & VCODEC_MASTER_CLOCK_OUTPUTS) { + reg_write |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1) | + SET_BITS(regAUD_CODEC, CDCTS, 0); + reg_mask |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1) | + SET_BITS(regAUD_CODEC, CDCTS, 1); + + } + + if (config & TRISTATE_TS) { + reg_write |= SET_BITS(regAUD_CODEC, CDCTS, 1); + reg_mask |= SET_BITS(regAUD_CODEC, CDCTS, 1); + } + + if (reg_mask == 0) { + /* We should not reach this point without having to configure + * anything so we flag it as an error. + */ + rc = PMIC_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_CODEC, + reg_write, reg_mask); + } + + if (rc == PMIC_SUCCESS) { + vCodec.config |= config; + } + } + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Clear/Disable the Voice CODEC options. + * + * Clear or disable various Voice CODEC options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The Voice CODEC options to be cleared/disabled. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the Voice CODEC options + * were invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * cleared/disabled. + */ +PMIC_STATUS pmic_audio_vcodec_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_CONFIG + config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (config & DITHERING) { + reg_mask = SET_BITS(regAUD_CODEC, CDCDITH, 1); + reg_write = SET_BITS(regAUD_CODEC, CDCDITH, 1); + } + + if (config & INPUT_HIGHPASS_FILTER) { + reg_mask |= SET_BITS(regAUD_CODEC, AUDIHPF, 1); + } + + if (config & OUTPUT_HIGHPASS_FILTER) { + reg_mask |= SET_BITS(regAUD_CODEC, AUDOHPF, 1); + } + + if (config & DIGITAL_LOOPBACK) { + reg_mask |= SET_BITS(regAUD_CODEC, CDCDLM, 1); + } + + if (config & ANALOG_LOOPBACK) { + reg_mask |= SET_BITS(regAUD_CODEC, CDCALM, 1); + } + + if (config & VCODEC_MASTER_CLOCK_OUTPUTS) { + reg_mask |= SET_BITS(regAUD_CODEC, CDCCLKEN, 1); + } + + if (config & TRISTATE_TS) { + reg_mask |= SET_BITS(regAUD_CODEC, CDCTS, 1); + } + + if (reg_mask == 0) { + /* We should not reach this point without having to configure + * anything so we flag it as an error. + */ + rc = PMIC_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_CODEC, + reg_write, reg_mask); + } + + if (rc == PMIC_SUCCESS) { + vCodec.config |= config; + } + + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current Voice CODEC options. + * + * Get the current Voice CODEC options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The current set of Voice CODEC options. + * + * @retval PMIC_SUCCESS If the Voice CODEC options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC options could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_VCODEC_CONFIG * + const config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (config != (PMIC_AUDIO_VCODEC_CONFIG *) NULL)) { + *config = vCodec.config; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Enable the Voice CODEC bypass audio pathway. + * + * Enables the Voice CODEC bypass pathway for audio data. This allows direct + * output of the voltages on the TX data bus line to the output amplifiers + * (bypassing the digital-to-analog converters within the Voice CODEC). + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC bypass was successfully + * enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC bypass could not be + * enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_bypass(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_write = SET_BITS(regAUD_CODEC, CDCBYP, 1); + const unsigned int reg_mask = SET_BITS(regAUD_CODEC, CDCBYP, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_CODEC, reg_write, reg_mask); + } + + return rc; +} + +/*! + * @brief Disable the Voice CODEC bypass audio pathway. + * + * Disables the Voice CODEC bypass pathway for audio data. This means that + * the TX data bus line will deliver digital data to the digital-to-analog + * converters within the Voice CODEC. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC bypass was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC bypass could not be + * disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_bypass(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_write = 0; + const unsigned int reg_mask = SET_BITS(regAUD_CODEC, CDCBYP, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_CODEC, reg_write, reg_mask); + } + + return rc; +} + +/*@}*/ + +/************************************************************************* + * General Stereo DAC configuration. + ************************************************************************* + */ + +/*! + * @name General Stereo DAC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Stereo + * DAC hardware. + */ +/*@{*/ + +/*! + * @brief Set the Stereo DAC clock source and operating characteristics. + * + * Define the Stereo DAC clock source and operating characteristics. This + * must be done before the Stereo DAC is enabled. + * + * + * @param handle Device handle from pmic_audio_open() call. + * @param clockIn Select the clock signal source. + * @param clockFreq Select the clock signal frequency. + * @param samplingRate Select the audio data sampling rate. + * @param invert Enable inversion of the frame sync and/or + * bit clock inputs. + * + * @retval PMIC_SUCCESS If the Stereo DAC clock settings were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or clock configuration was + * invalid. + * @retval PMIC_ERROR If the Stereo DAC clock configuration + * could not be set. + */ +PMIC_STATUS pmic_audio_stdac_set_clock(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_CLOCK_IN_SOURCE clockIn, + const PMIC_AUDIO_STDAC_CLOCK_IN_FREQ + clockFreq, + const PMIC_AUDIO_STDAC_SAMPLING_RATE + samplingRate, + const PMIC_AUDIO_CLOCK_INVERT invert) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + /* Validate all of the calling parameters. */ + if (handle == (PMIC_AUDIO_HANDLE) NULL) { + rc = PMIC_PARAMETER_ERROR; + } else if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + if ((clockIn != CLOCK_IN_CLIA) && (clockIn != CLOCK_IN_CLIB)) { + rc = PMIC_PARAMETER_ERROR; + } else if ((stDAC.masterSlave == BUS_MASTER_MODE) + && !((clockFreq >= STDAC_CLI_3_36864MHZ) + && (clockFreq <= STDAC_CLI_33_6MHZ))) { + rc = PMIC_PARAMETER_ERROR; + } else if ((stDAC.masterSlave == BUS_SLAVE_MODE) + && !((clockFreq >= STDAC_MCLK_PLL_DISABLED) + && (clockFreq <= STDAC_BCLK_IN_PLL))) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((samplingRate >= STDAC_RATE_8_KHZ) + && (samplingRate <= STDAC_RATE_96_KHZ))) { + rc = PMIC_PARAMETER_ERROR; + } + /* + else if(!((invert >= NO_INVERT) && (invert <= INVERT_FRAMESYNC))) + { + rc = PMIC_PARAMETER_ERROR; + } */ + else { + reg_mask = SET_BITS(regST_DAC, STDCCLK, 7) | + SET_BITS(regST_DAC, STDCCLKSEL, 1) | + SET_BITS(regST_DAC, SR, 15) | + SET_BITS(regST_DAC, STDCBCLINV, 1) | + SET_BITS(regST_DAC, STDCFSINV, 1); + if (clockIn == CLOCK_IN_CLIA) { + reg_value = SET_BITS(regST_DAC, STDCCLKSEL, 0); + } else { + reg_value = SET_BITS(regST_DAC, STDCCLKSEL, 1); + } + /* How to take care of sample rates in SLAVE mode */ + if ((clockFreq == STDAC_CLI_3_36864MHZ) + || ((clockFreq == STDAC_FSYNC_IN_PLL))) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 6); + } else if ((clockFreq == STDAC_CLI_12MHZ) + || (clockFreq == STDAC_MCLK_PLL_DISABLED)) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 5); + } else if (clockFreq == STDAC_CLI_13MHZ) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 0); + } else if (clockFreq == STDAC_CLI_15_36MHZ) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 1); + } else if (clockFreq == STDAC_CLI_16_8MHZ) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 2); + } else if (clockFreq == STDAC_CLI_26MHZ) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 4); + } else if ((clockFreq == STDAC_CLI_33_6MHZ) + || (clockFreq == STDAC_BCLK_IN_PLL)) { + reg_value |= SET_BITS(regST_DAC, STDCCLK, 7); + } + + reg_value |= SET_BITS(regST_DAC, SR, samplingRate); + + if (invert & INVERT_BITCLOCK) { + reg_value |= SET_BITS(regST_DAC, STDCBCLINV, 1); + } + if (invert & INVERT_FRAMESYNC) { + reg_value |= SET_BITS(regST_DAC, STDCFSINV, 1); + } + if (invert & NO_INVERT) { + reg_value |= SET_BITS(regST_DAC, STDCBCLINV, 0); + reg_value |= SET_BITS(regST_DAC, STDCFSINV, 0); + } + if (pmic_write_reg + (REG_AUDIO_STEREO_DAC, reg_value, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("STDAC clock set\n"); + rc = PMIC_SUCCESS; + stDAC.clockIn = clockIn; + stDAC.clockFreq = clockFreq; + stDAC.samplingRate = samplingRate; + stDAC.invert = invert; + } + + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the Stereo DAC clock source and operating characteristics. + * + * Get the current Stereo DAC clock source and operating characteristics. + * + * @param handle Device handle from pmic_audio_open() call. + * @param clockIn The clock signal source. + * @param clockFreq The clock signal frequency. + * @param samplingRate The audio data sampling rate. + * @param invert Inversion of the frame sync and/or + * bit clock inputs is enabled/disabled. + * + * @retval PMIC_SUCCESS If the Stereo DAC clock settings were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle invalid. + * @retval PMIC_ERROR If the Stereo DAC clock configuration + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_clock(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_CLOCK_IN_SOURCE * + const clockIn, + PMIC_AUDIO_STDAC_SAMPLING_RATE * + const samplingRate, + PMIC_AUDIO_STDAC_CLOCK_IN_FREQ * + const clockFreq, + PMIC_AUDIO_CLOCK_INVERT * const invert) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE) && + (clockIn != (PMIC_AUDIO_CLOCK_IN_SOURCE *) NULL) && + (samplingRate != (PMIC_AUDIO_STDAC_SAMPLING_RATE *) NULL) && + (clockFreq != (PMIC_AUDIO_STDAC_CLOCK_IN_FREQ *) NULL) && + (invert != (PMIC_AUDIO_CLOCK_INVERT *) NULL)) { + *clockIn = stDAC.clockIn; + *samplingRate = stDAC.samplingRate; + *clockFreq = stDAC.clockFreq; + *invert = stDAC.invert; + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the Stereo DAC primary audio channel timeslot. + * + * Set the Stereo DAC primary audio channel timeslot. This function must be + * used if the default timeslot for the primary audio channel is to be changed. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot Select the primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Stereo DAC primary audio channel + * timeslot was successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio channel timeslot + * was invalid. + * @retval PMIC_ERROR If the Stereo DAC primary audio channel + * timeslot could not be set. + */ +PMIC_STATUS pmic_audio_stdac_set_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_TIMESLOTS + timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = SET_BITS(regSSI_NETWORK, STDCRXSLOT, 3); + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + if ((timeslot == USE_TS0_TS1) || (timeslot == USE_TS2_TS3) + || (timeslot == USE_TS4_TS5) || (timeslot == USE_TS6_TS7)) { + if (pmic_write_reg + (REG_AUDIO_SSI_NETWORK, timeslot, + reg_mask) != PMIC_SUCCESS) { + rc = PMIC_ERROR; + } else { + pr_debug("STDAC primary timeslot set\n"); + stDAC.timeslot = timeslot; + rc = PMIC_SUCCESS; + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current Stereo DAC primary audio channel timeslot. + * + * Get the current Stereo DAC primary audio channel timeslot. + * + * @param handle Device handle from pmic_audio_open() call. + * @param timeslot The primary audio channel timeslot. + * + * @retval PMIC_SUCCESS If the Stereo DAC primary audio channel + * timeslot was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC primary audio channel + * timeslot could not be retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_rxtx_timeslot(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STDAC_TIMESLOTS * + const timeslot) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE) && + (timeslot != (PMIC_AUDIO_STDAC_TIMESLOTS *) NULL)) { + *timeslot = stDAC.timeslot; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set/Enable the Stereo DAC options. + * + * Set or enable various Stereo DAC options. The available options include + * resetting the digital filter and enabling the bus master clock outputs. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The Stereo DAC options to enable. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or Stereo DAC options + * were invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * successfully set/enabled. + */ +PMIC_STATUS pmic_audio_stdac_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_CONFIG config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + if (config & STDAC_MASTER_CLOCK_OUTPUTS) { + reg_write |= SET_BITS(regST_DAC, STDCCLKEN, 1); + reg_mask |= SET_BITS(regST_DAC, STDCCLKEN, 1); + } + + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + stDAC.config |= config; + pr_debug("STDAC config set\n"); + + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Clear/Disable the Stereo DAC options. + * + * Clear or disable various Stereo DAC options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The Stereo DAC options to be cleared/disabled. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the Stereo DAC options + * were invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * cleared/disabled. + */ +PMIC_STATUS pmic_audio_stdac_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_CONFIG config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + + if (config & STDAC_MASTER_CLOCK_OUTPUTS) { + reg_mask |= SET_BITS(regST_DAC, STDCCLKEN, 1); + } + + if (reg_mask != 0) { + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + stDAC.config &= ~config; + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current Stereo DAC options. + * + * Get the current Stereo DAC options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The current set of Stereo DAC options. + * + * @retval PMIC_SUCCESS If the Stereo DAC options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC options could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_stdac_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STDAC_CONFIG * const config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE) && + (config != (PMIC_AUDIO_STDAC_CONFIG *) NULL)) { + *config = stDAC.config; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio input section configuration. + ************************************************************************* + */ + +/*! + * @name Audio Input Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC audio + * input hardware. + */ +/*@{*/ + +/*! + * @brief Set/Enable the audio input section options. + * + * Set or enable various audio input section options. The only available + * option right now is to enable the automatic disabling of the microphone + * input amplifiers when a microphone/headset is inserted or removed. + * NOT SUPPORTED BY MC13783 + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The audio input section options to enable. + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully configured. + * @retval PMIC_PARAMETER_ERROR If the handle or audio input section + * options were invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be successfully set/enabled. + */ +PMIC_STATUS pmic_audio_input_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_CONFIG config) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +/*! + * @brief Clear/Disable the audio input section options. + * + * Clear or disable various audio input section options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The audio input section options to be + * cleared/disabled. + * NOT SUPPORTED BY MC13783 + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully cleared/disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or the audio input section + * options were invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be cleared/disabled. + */ +PMIC_STATUS pmic_audio_input_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_CONFIG config) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; + +} + +/*! + * @brief Get the current audio input section options. + * + * Get the current audio input section options. + * + * @param[in] handle Device handle from pmic_audio_open() call. + * @param[out] config The current set of audio input section options. + * NOT SUPPORTED BY MC13783 + * + * @retval PMIC_SUCCESS If the audio input section options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the audio input section options could + * not be retrieved. + */ +PMIC_STATUS pmic_audio_input_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_CONFIG * const config) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio recording using the Voice CODEC. + ************************************************************************* + */ + +/*! + * @name Audio Recording Using the Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice CODEC + * to perform audio recording. + */ +/*@{*/ + +/*! + * @brief Select the microphone inputs to be used for Voice CODEC recording. + * + * Select left (mc13783-only) and right microphone inputs for Voice CODEC + * recording. It is possible to disable or not use a particular microphone + * input channel by specifying NO_MIC as a parameter. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannel Select the left microphone input channel. + * @param rightChannel Select the right microphone input channel. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input ports + * were invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be successfully enabled. + */ +PMIC_STATUS pmic_audio_vcodec_set_mic(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_PORT leftChannel, + const PMIC_AUDIO_INPUT_PORT rightChannel) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (!((leftChannel == NO_MIC) || (leftChannel == MIC1_LEFT))) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((rightChannel == NO_MIC) + || (rightChannel == MIC1_RIGHT_MIC_MONO) + || (rightChannel == TXIN_EXT) + || (rightChannel == MIC2_AUX))) { + rc = PMIC_PARAMETER_ERROR; + } else { + if (leftChannel == NO_MIC) { + } else { /* Left channel MIC enable */ + reg_mask = SET_BITS(regAUDIO_TX, AMC1LEN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 1); + reg_write = SET_BITS(regAUDIO_TX, AMC1LEN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 0); + } + /*For right channel enable one and clear the other two as well as RXINREC */ + if (rightChannel == NO_MIC) { + } else if (rightChannel == MIC1_RIGHT_MIC_MONO) { + reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 1) | + SET_BITS(regAUDIO_TX, AMC2EN, 1) | + SET_BITS(regAUDIO_TX, ATXINEN, 1); + reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 0) | + SET_BITS(regAUDIO_TX, AMC2EN, 0) | + SET_BITS(regAUDIO_TX, ATXINEN, 0); + } else if (rightChannel == MIC2_AUX) { + reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 1) | + SET_BITS(regAUDIO_TX, AMC2EN, 1) | + SET_BITS(regAUDIO_TX, ATXINEN, 1); + reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 0) | + SET_BITS(regAUDIO_TX, RXINREC, 0) | + SET_BITS(regAUDIO_TX, AMC2EN, 1) | + SET_BITS(regAUDIO_TX, ATXINEN, 0); + } else { /* TX line in */ + reg_mask |= SET_BITS(regAUDIO_TX, AMC1REN, 1) | + SET_BITS(regAUDIO_TX, RXINREC, 1) | + SET_BITS(regAUDIO_TX, AMC2EN, 1) | + SET_BITS(regAUDIO_TX, ATXINEN, 1); + reg_write |= SET_BITS(regAUDIO_TX, AMC1REN, 0) | + SET_BITS(regAUDIO_TX, RXINREC, 0) | + SET_BITS(regAUDIO_TX, AMC2EN, 0) | + SET_BITS(regAUDIO_TX, ATXINEN, 1); + } + + if (reg_mask == 0) { + rc = PMIC_PARAMETER_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_TX, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug + ("MIC inputs configured successfully\n"); + vCodec.leftChannelMic.mic = leftChannel; + vCodec.rightChannelMic.mic = + rightChannel; + + } + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current microphone inputs being used for Voice CODEC + * recording. + * + * Get the left (mc13783-only) and right microphone inputs currently being + * used for Voice CODEC recording. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannel The left microphone input channel. + * @param rightChannel The right microphone input channel. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_mic(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_PORT * const leftChannel, + PMIC_AUDIO_INPUT_PORT * + const rightChannel) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (leftChannel != (PMIC_AUDIO_INPUT_PORT *) NULL) && + (rightChannel != (PMIC_AUDIO_INPUT_PORT *) NULL)) { + *leftChannel = vCodec.leftChannelMic.mic; + *rightChannel = vCodec.rightChannelMic.mic; + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + return rc; +} + +/*! + * @brief Enable/disable the microphone input. + * + * This function enables/disables the current microphone input channel. The + * input amplifier is automatically turned off when the microphone input is + * disabled. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannel The left microphone input channel state. + * @param rightChannel the right microphone input channel state. + * + * @retval PMIC_SUCCESS If the microphone input channels were + * successfully reconfigured. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input states + * were invalid. + * @retval PMIC_ERROR If the microphone input channels could + * not be reconfigured. + */ +PMIC_STATUS pmic_audio_vcodec_set_mic_on_off(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_INPUT_MIC_STATE + leftChannel, + const PMIC_AUDIO_INPUT_MIC_STATE + rightChannel) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + unsigned int curr_left = 0; + unsigned int curr_right = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + curr_left = vCodec.leftChannelMic.mic; + curr_right = vCodec.rightChannelMic.mic; + if ((curr_left == NO_MIC) && (curr_right == NO_MIC)) { + rc = PMIC_PARAMETER_ERROR; + } else { + if (curr_left == MIC1_LEFT) { + if ((leftChannel == MICROPHONE_ON) && + (vCodec.leftChannelMic.micOnOff == + MICROPHONE_OFF)) { + /* Enable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1LEN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1LEN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, 0); + + } else if ((leftChannel == MICROPHONE_OFF) && + (vCodec.leftChannelMic.micOnOff == + MICROPHONE_ON)) { + /* Disable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1LEN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1LEN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, 0); + + } else { + /* Both are in same state . Nothing to be done */ + } + + } + if (curr_right == MIC1_RIGHT_MIC_MONO) { + if ((rightChannel == MICROPHONE_ON) && + (vCodec.leftChannelMic.micOnOff == + MICROPHONE_OFF)) { + /* Enable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else if ((rightChannel == MICROPHONE_OFF) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_ON)) { + /* Disable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else { + /* Both are in same state . Nothing to be done */ + } + } else if (curr_right == MIC2_AUX) { + if ((rightChannel == MICROPHONE_ON) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_OFF)) { + /* Enable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else if ((rightChannel == MICROPHONE_OFF) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_ON)) { + /* Disable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else { + /* Both are in same state . Nothing to be done */ + } + } else if (curr_right == TXIN_EXT) { + if ((rightChannel == MICROPHONE_ON) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_OFF)) { + /* Enable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + } else if ((rightChannel == MICROPHONE_OFF) + && (vCodec.leftChannelMic.micOnOff == + MICROPHONE_ON)) { + /* Disable the microphone */ + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1REN, + 1) | SET_BITS(regAUDIO_TX, + RXINREC, + 1) | + SET_BITS(regAUDIO_TX, AMC2EN, + 1) | SET_BITS(regAUDIO_TX, + ATXINEN, 1); + reg_write |= + SET_BITS(regAUDIO_TX, AMC1REN, + 0) | SET_BITS(regAUDIO_TX, + RXINREC, + 0) | + SET_BITS(regAUDIO_TX, AMC2EN, + 0) | SET_BITS(regAUDIO_TX, + ATXINEN, 0); + } else { + /* Both are in same state . Nothing to be done */ + } + } + if (reg_mask == 0) { + } else { + rc = pmic_write_reg(REG_AUDIO_TX, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug + ("MIC states configured successfully\n"); + vCodec.leftChannelMic.micOnOff = + leftChannel; + vCodec.rightChannelMic.micOnOff = + rightChannel; + } + } + } + + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Return the current state of the microphone inputs. + * + * This function returns the current state (on/off) of the microphone + * input channels. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannel The current left microphone input channel + * state. + * @param rightChannel the current right microphone input channel + * state. + * + * @retval PMIC_SUCCESS If the microphone input channel states + * were successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input channel states + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_mic_on_off(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_INPUT_MIC_STATE * + const leftChannel, + PMIC_AUDIO_INPUT_MIC_STATE * + const rightChannel) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (leftChannel != (PMIC_AUDIO_INPUT_MIC_STATE *) NULL) && + (rightChannel != (PMIC_AUDIO_INPUT_MIC_STATE *) NULL)) { + *leftChannel = vCodec.leftChannelMic.micOnOff; + *rightChannel = vCodec.rightChannelMic.micOnOff; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the microphone input amplifier mode and gain level. + * + * This function sets the current microphone input amplifier operating mode + * and gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannelMode The left microphone input amplifier mode. + * @param leftChannelGain The left microphone input amplifier gain level. + * @param rightChannelMode The right microphone input amplifier mode. + * @param rightChannelGain The right microphone input amplifier gain + * level. + * + * @retval PMIC_SUCCESS If the microphone input amplifiers were + * successfully reconfigured. + * @retval PMIC_PARAMETER_ERROR If the handle or microphone input amplifier + * modes or gain levels were invalid. + * @retval PMIC_ERROR If the microphone input amplifiers could + * not be reconfigured. + */ +PMIC_STATUS pmic_audio_vcodec_set_record_gain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_AMP_MODE + leftChannelMode, + const PMIC_AUDIO_MIC_GAIN + leftChannelGain, + const PMIC_AUDIO_MIC_AMP_MODE + rightChannelMode, + const PMIC_AUDIO_MIC_GAIN + rightChannelGain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (!(((leftChannelGain >= MIC_GAIN_MINUS_8DB) + && (leftChannelGain <= MIC_GAIN_PLUS_23DB)) + && ((rightChannelGain >= MIC_GAIN_MINUS_8DB) + && (rightChannelGain <= MIC_GAIN_PLUS_23DB)))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("VCODEC set record gain - wrong gain value\n"); + } else if (((leftChannelMode != AMP_OFF) + && (leftChannelMode != VOLTAGE_TO_VOLTAGE) + && (leftChannelMode != CURRENT_TO_VOLTAGE)) + || ((rightChannelMode != VOLTAGE_TO_VOLTAGE) + && (rightChannelMode != CURRENT_TO_VOLTAGE) + && (rightChannelMode != AMP_OFF))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("VCODEC set record gain - wrong amp mode\n"); + } else { + if (vCodec.leftChannelMic.mic == MIC1_LEFT) { + reg_mask = SET_BITS(regAUDIO_TX, AMC1LITOV, 1) | + SET_BITS(regAUDIO_TX, PGATXL, 31); + if (leftChannelMode == VOLTAGE_TO_VOLTAGE) { + reg_write = + SET_BITS(regAUDIO_TX, AMC1LITOV, 0); + } else { + reg_write = + SET_BITS(regAUDIO_TX, AMC1LITOV, 1); + } + reg_write |= + SET_BITS(regAUDIO_TX, PGATXL, + leftChannelGain); + } + if (vCodec.rightChannelMic.mic == MIC1_RIGHT_MIC_MONO) { + reg_mask |= + SET_BITS(regAUDIO_TX, AMC1RITOV, + 1) | SET_BITS(regAUDIO_TX, PGATXR, + 31); + if (rightChannelMode == VOLTAGE_TO_VOLTAGE) { + reg_write |= + SET_BITS(regAUDIO_TX, AMC1RITOV, 0); + } else { + reg_write |= + SET_BITS(regAUDIO_TX, AMC1RITOV, 1); + } + reg_write |= + SET_BITS(regAUDIO_TX, PGATXR, + rightChannelGain); + } else if (vCodec.rightChannelMic.mic == MIC2_AUX) { + reg_mask |= SET_BITS(regAUDIO_TX, AMC2ITOV, 1); + reg_mask |= SET_BITS(regAUDIO_TX, PGATXR, 31); + if (rightChannelMode == VOLTAGE_TO_VOLTAGE) { + reg_write |= + SET_BITS(regAUDIO_TX, AMC2ITOV, 0); + } else { + reg_write |= + SET_BITS(regAUDIO_TX, AMC2ITOV, 1); + } + reg_write |= + SET_BITS(regAUDIO_TX, PGATXR, + rightChannelGain); + } else if (vCodec.rightChannelMic.mic == TXIN_EXT) { + reg_mask |= SET_BITS(regAUDIO_TX, PGATXR, 31); + /* No current to voltage option for TX IN amplifier */ + reg_write |= + SET_BITS(regAUDIO_TX, PGATXR, + rightChannelGain); + } + + if (reg_mask == 0) { + } else { + rc = pmic_write_reg(REG_AUDIO_TX, + reg_write, reg_mask); + reg_write = + SET_BITS(regAUDIO_TX, PGATXL, + leftChannelGain); + reg_mask = SET_BITS(regAUDIO_TX, PGATXL, 31); + rc = pmic_write_reg(REG_AUDIO_TX, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("MIC amp mode and gain set\n"); + vCodec.leftChannelMic.ampMode = + leftChannelMode; + vCodec.leftChannelMic.gain = + leftChannelGain; + vCodec.rightChannelMic.ampMode = + rightChannelMode; + vCodec.rightChannelMic.gain = + rightChannelGain; + + } + } + } + } + + /* Exit critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current microphone input amplifier mode and gain level. + * + * This function gets the current microphone input amplifier operating mode + * and gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftChannelMode The left microphone input amplifier mode. + * @param leftChannelGain The left microphone input amplifier gain level. + * @param rightChannelMode The right microphone input amplifier mode. + * @param rightChannelGain The right microphone input amplifier gain + * level. + * + * @retval PMIC_SUCCESS If the microphone input amplifier modes + * and gain levels were successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the microphone input amplifier modes + * and gain levels could not be retrieved. + */ +PMIC_STATUS pmic_audio_vcodec_get_record_gain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_MIC_AMP_MODE * + const leftChannelMode, + PMIC_AUDIO_MIC_GAIN * + const leftChannelGain, + PMIC_AUDIO_MIC_AMP_MODE * + const rightChannelMode, + PMIC_AUDIO_MIC_GAIN * + const rightChannelGain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE) && + (leftChannelMode != (PMIC_AUDIO_MIC_AMP_MODE *) NULL) && + (leftChannelGain != (PMIC_AUDIO_MIC_GAIN *) NULL) && + (rightChannelMode != (PMIC_AUDIO_MIC_AMP_MODE *) NULL) && + (rightChannelGain != (PMIC_AUDIO_MIC_GAIN *) NULL)) { + *leftChannelMode = vCodec.leftChannelMic.ampMode; + *leftChannelGain = vCodec.leftChannelMic.gain; + *rightChannelMode = vCodec.rightChannelMic.ampMode; + *rightChannelGain = vCodec.rightChannelMic.gain; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Enable a microphone bias circuit. + * + * This function enables one of the available microphone bias circuits. + * + * @param handle Device handle from pmic_audio_open() call. + * @param biasCircuit The microphone bias circuit to be enabled. + * + * @retval PMIC_SUCCESS If the microphone bias circuit was + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or selected microphone bias + * circuit was invalid. + * @retval PMIC_ERROR If the microphone bias circuit could not + * be enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_micbias(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_BIAS + biasCircuit) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (biasCircuit & MIC_BIAS1) { + reg_write = SET_BITS(regAUDIO_TX, MC1BEN, 1); + reg_mask = SET_BITS(regAUDIO_TX, MC1BEN, 1); + } + if (biasCircuit & MIC_BIAS2) { + reg_write |= SET_BITS(regAUDIO_TX, MC2BEN, 1); + reg_mask |= SET_BITS(regAUDIO_TX, MC2BEN, 1); + } + if (reg_mask != 0) { + rc = pmic_write_reg(REG_AUDIO_TX, reg_write, reg_mask); + } + } + + return rc; +} + +/*! + * @brief Disable a microphone bias circuit. + * + * This function disables one of the available microphone bias circuits. + * + * @param handle Device handle from pmic_audio_open() call. + * @param biasCircuit The microphone bias circuit to be disabled. + * + * @retval PMIC_SUCCESS If the microphone bias circuit was + * successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or selected microphone bias + * circuit was invalid. + * @retval PMIC_ERROR If the microphone bias circuit could not + * be disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_micbias(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MIC_BIAS + biasCircuit) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (biasCircuit & MIC_BIAS1) { + reg_mask = SET_BITS(regAUDIO_TX, MC1BEN, 1); + } + + if (biasCircuit & MIC_BIAS2) { + reg_mask |= SET_BITS(regAUDIO_TX, MC2BEN, 1); + } + + if (reg_mask != 0) { + rc = pmic_write_reg(REG_AUDIO_TX, reg_write, reg_mask); + } + } + + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio Playback Using the Voice CODEC. + ************************************************************************* + */ + +/*! + * @name Audio Playback Using the Voice CODEC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Voice CODEC + * to perform audio playback. + */ +/*@{*/ + +/*! + * @brief Configure and enable the Voice CODEC mixer. + * + * This function configures and enables the Voice CODEC mixer. + * + * @param handle Device handle from pmic_audio_open() call. + * @param rxSecondaryTimeslot The timeslot used for the secondary audio + * channel. + * @param gainIn The secondary audio channel gain level. + * @param gainOut The mixer output gain level. + * + * @retval PMIC_SUCCESS If the Voice CODEC mixer was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mixer configuration + * was invalid. + * @retval PMIC_ERROR If the Voice CODEC mixer could not be + * reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_vcodec_enable_mixer(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_VCODEC_TIMESLOT + rxSecondaryTimeslot, + const PMIC_AUDIO_VCODEC_MIX_IN_GAIN + gainIn, + const PMIC_AUDIO_VCODEC_MIX_OUT_GAIN + gainOut) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + if (!((rxSecondaryTimeslot >= USE_TS0) + && (rxSecondaryTimeslot <= USE_TS3))) { + pr_debug + ("VCODEC enable mixer - wrong sec rx timeslot\n"); + } else if (!((gainIn >= VCODEC_NO_MIX) + && (gainIn <= VCODEC_MIX_IN_MINUS_12DB))) { + pr_debug("VCODEC enable mixer - wrong mix in gain\n"); + + } else if (!((gainOut >= VCODEC_MIX_OUT_0DB) + && (gainOut <= VCODEC_MIX_OUT_MINUS_6DB))) { + pr_debug("VCODEC enable mixer - wrong mix out gain\n"); + } else { + + reg_mask = SET_BITS(regSSI_NETWORK, CDCRXSECSLOT, 3) | + SET_BITS(regSSI_NETWORK, CDCRXSECGAIN, 3) | + SET_BITS(regSSI_NETWORK, CDCSUMGAIN, 1); + reg_write = + SET_BITS(regSSI_NETWORK, CDCRXSECSLOT, + rxSecondaryTimeslot) | + SET_BITS(regSSI_NETWORK, CDCRXSECGAIN, + gainIn) | SET_BITS(regSSI_NETWORK, + CDCSUMGAIN, gainOut); + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + reg_write, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("Vcodec mixer enabled\n"); + } + } + } + + return rc; +} + +/*! + * @brief Disable the Voice CODEC mixer. + * + * This function disables the Voice CODEC mixer. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Voice CODEC mixer was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Voice CODEC mixer could not be + * disabled. + */ +PMIC_STATUS pmic_audio_vcodec_disable_mixer(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask; + + if ((handle == vCodec.handle) && (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regSSI_NETWORK, CDCRXSECGAIN, 1); + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + VCODEC_NO_MIX, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Vcodec mixer disabled\n"); + } + + } + + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio Playback Using the Stereo DAC. + ************************************************************************* + */ + +/*! + * @name Audio Playback Using the Stereo DAC Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC Stereo DAC + * to perform audio playback. + */ +/*@{*/ + +/*! + * @brief Configure and enable the Stereo DAC mixer. + * + * This function configures and enables the Stereo DAC mixer. + * + * @param handle Device handle from pmic_audio_open() call. + * @param rxSecondaryTimeslot The timeslot used for the secondary audio + * channel. + * @param gainIn The secondary audio channel gain level. + * @param gainOut The mixer output gain level. + * + * @retval PMIC_SUCCESS If the Stereo DAC mixer was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mixer configuration + * was invalid. + * @retval PMIC_ERROR If the Stereo DAC mixer could not be + * reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_stdac_enable_mixer(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STDAC_TIMESLOTS + rxSecondaryTimeslot, + const PMIC_AUDIO_STDAC_MIX_IN_GAIN + gainIn, + const PMIC_AUDIO_STDAC_MIX_OUT_GAIN + gainOut) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + if (!((rxSecondaryTimeslot >= USE_TS0_TS1) + && (rxSecondaryTimeslot <= USE_TS6_TS7))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("STDAC enable mixer - wrong sec timeslot\n"); + } else if (!((gainIn >= STDAC_NO_MIX) + && (gainIn <= STDAC_MIX_IN_MINUS_12DB))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("STDAC enable mixer - wrong mix in gain\n"); + } else if (!((gainOut >= STDAC_MIX_OUT_0DB) + && (gainOut <= STDAC_MIX_OUT_MINUS_6DB))) { + rc = PMIC_PARAMETER_ERROR; + pr_debug("STDAC enable mixer - wrong mix out gain\n"); + } else { + + reg_mask = SET_BITS(regSSI_NETWORK, STDCRXSECSLOT, 3) | + SET_BITS(regSSI_NETWORK, STDCRXSECGAIN, 3) | + SET_BITS(regSSI_NETWORK, STDCSUMGAIN, 1); + reg_write = + SET_BITS(regSSI_NETWORK, STDCRXSECSLOT, + rxSecondaryTimeslot) | + SET_BITS(regSSI_NETWORK, STDCRXSECGAIN, + gainIn) | SET_BITS(regSSI_NETWORK, + STDCSUMGAIN, gainOut); + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + reg_write, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("STDAC mixer enabled\n"); + } + } + + } + + return rc; +} + +/*! + * @brief Disable the Stereo DAC mixer. + * + * This function disables the Stereo DAC mixer. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the Stereo DAC mixer was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the Stereo DAC mixer could not be + * disabled. + */ +PMIC_STATUS pmic_audio_stdac_disable_mixer(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_write = 0; + const unsigned int reg_mask = + SET_BITS(regSSI_NETWORK, STDCRXSECGAIN, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, reg_write, reg_mask); + } + + return rc; +} + +/*@}*/ + +/************************************************************************* + * Audio Output Control + ************************************************************************* + */ + +/*! + * @name Audio Output Section Setup and Configuration APIs + * Functions for general setup and configuration of the PMIC audio output + * section to support playback. + */ +/*@{*/ + +/*! + * @brief Select the audio output ports. + * + * This function selects the audio output ports to be used. This also enables + * the appropriate output amplifiers. + * + * @param handle Device handle from pmic_audio_open() call. + * @param port The audio output ports to be used. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * acquired. + * @retval PMIC_PARAMETER_ERROR If the handle or output ports were + * invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * acquired. + */ +PMIC_STATUS pmic_audio_output_set_port(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PORT port) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((port == MONO_ALERT) || (port == MONO_EXTOUT)) { + rc = PMIC_NOT_SUPPORTED; + } else { + if (((handle == stDAC.handle) + && (stDAC.handleState == HANDLE_IN_USE)) + || ((handle == extStereoIn.handle) + && (extStereoIn.handleState == HANDLE_IN_USE)) + || ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE) + && (audioOutput.vCodecOut == VCODEC_MIXER_OUT))) { + /* Stereo signal and MIXER source needs to be routed to the port + / Avoid Codec direct out */ + + if (port & MONO_SPEAKER) { + reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1) | + SET_BITS(regAUDIO_RX_0, ASPSEL, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 1) | + SET_BITS(regAUDIO_RX_0, ASPSEL, 1); + } + if (port & MONO_LOUDSPEAKER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) | + SET_BITS(regAUDIO_RX_0, ALSPREF, 1) | + SET_BITS(regAUDIO_RX_0, ALSPSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ALSPEN, + 1) | SET_BITS(regAUDIO_RX_0, + ALSPREF, + 1) | + SET_BITS(regAUDIO_RX_0, ALSPSEL, 1); + } + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1) | + SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, AHSLEN, + 1) | SET_BITS(regAUDIO_RX_0, + AHSSEL, 1); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1) | + SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, AHSREN, + 1) | SET_BITS(regAUDIO_RX_0, + AHSSEL, 1); + } + if (port & STEREO_OUT_LEFT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + } + if (port & STEREO_OUT_RIGHT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + } + if (port & STEREO_LEFT_LOW_POWER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1); + + reg_write |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1); + } + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE) + && (audioOutput.vCodecOut == VCODEC_DIRECT_OUT)) { + if (port & MONO_SPEAKER) { + reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1) | + SET_BITS(regAUDIO_RX_0, ASPSEL, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 1) | + SET_BITS(regAUDIO_RX_0, ASPSEL, 0); + } + if (port & MONO_LOUDSPEAKER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) | + SET_BITS(regAUDIO_RX_0, ALSPREF, 1) | + SET_BITS(regAUDIO_RX_0, ALSPSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ALSPEN, + 1) | SET_BITS(regAUDIO_RX_0, + ALSPREF, + 1) | + SET_BITS(regAUDIO_RX_0, ALSPSEL, 0); + } + + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1) | + SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, AHSLEN, + 1) | SET_BITS(regAUDIO_RX_0, + AHSSEL, 0); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1) | + SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, AHSREN, + 1) | SET_BITS(regAUDIO_RX_0, + AHSSEL, 0); + } + if (port & STEREO_OUT_LEFT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 0); + } + if (port & STEREO_OUT_RIGHT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, + 1) | SET_BITS(regAUDIO_RX_0, + ARXOUTSEL, 0); + } + if (port & MONO_CDCOUT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1); + + reg_write |= + SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1); + } + } + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("output ports enabled\n"); + audioOutput.outputPort = port; + + } + } + } + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Deselect/disable the audio output ports. + * + * This function disables the audio output ports that were previously enabled + * by calling pmic_audio_output_set_port(). + * + * @param handle Device handle from pmic_audio_open() call. + * @param port The audio output ports to be disabled. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle or output ports were + * invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * disabled. + */ +PMIC_STATUS pmic_audio_output_clear_port(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PORT port) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((port == MONO_ALERT) || (port == MONO_EXTOUT)) { + rc = PMIC_NOT_SUPPORTED; + } else { + if (((handle == stDAC.handle) + && (stDAC.handleState == HANDLE_IN_USE)) + || ((handle == extStereoIn.handle) + && (extStereoIn.handleState == HANDLE_IN_USE)) + || ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE) + && (audioOutput.vCodecOut == VCODEC_MIXER_OUT))) { + /* Stereo signal and MIXER source needs to be routed to the port / + Avoid Codec direct out */ + if (port & MONO_SPEAKER) { + reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 0); + } + if (port & MONO_LOUDSPEAKER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) | + SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + + reg_write |= + SET_BITS(regAUDIO_RX_0, ALSPEN, + 0) | SET_BITS(regAUDIO_RX_0, + ALSPREF, 0); + + } + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0); + } + if (port & STEREO_OUT_LEFT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 0); + } + if (port & STEREO_OUT_RIGHT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, 0); + } + if (port & STEREO_LEFT_LOW_POWER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, LSPLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, LSPLEN, 0); + } + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE) + && (audioOutput.vCodecOut == VCODEC_DIRECT_OUT)) { + if (port & MONO_SPEAKER) { + reg_mask = SET_BITS(regAUDIO_RX_0, ASPEN, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ASPEN, 0); + } + if (port & MONO_LOUDSPEAKER) { + reg_mask |= SET_BITS(regAUDIO_RX_0, ALSPEN, 1) | + SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ALSPEN, + 0) | SET_BITS(regAUDIO_RX_0, + ALSPREF, 0); + } + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0); + } + if (port & STEREO_OUT_LEFT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTLEN, 0); + } + if (port & STEREO_OUT_RIGHT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, ARXOUTREN, 0); + } + if (port & MONO_CDCOUT) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, CDCOUTEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, CDCOUTEN, 0); + } + } +#ifdef CONFIG_HEADSET_DETECT_ENABLE + + if (port & STEREO_HEADSET_LEFT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 0); + } + if (port & STEREO_HEADSET_RIGHT) { + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 0); + } +#endif + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("output ports disabled\n"); + audioOutput.outputPort &= ~port; + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current audio output ports. + * + * This function retrieves the audio output ports that are currently being + * used. + * + * @param handle Device handle from pmic_audio_open() call. + * @param port The audio output ports currently being used. + * + * @retval PMIC_SUCCESS If the audio output ports were successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the audio output ports could not be + * retrieved. + */ +PMIC_STATUS pmic_audio_output_get_port(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_PORT * const port) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) && + (port != (PMIC_AUDIO_OUTPUT_PORT *) NULL)) { + *port = audioOutput.outputPort; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the gain level for the external stereo inputs. + * + * This function sets the gain levels for the external stereo inputs. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The external stereo input gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the gain level could not be set. + */ +PMIC_STATUS pmic_audio_output_set_stereo_in_gain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_STEREO_IN_GAIN + gain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1) | + SET_BITS(regAUDIO_RX_1, ARXIN, 1); + unsigned int reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + /* The ARX amplifier for stereo is also enabled over here */ + + if ((gain == STEREO_IN_GAIN_0DB) || (gain == STEREO_IN_GAIN_PLUS_18DB)) { + if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + + if (gain == STEREO_IN_GAIN_0DB) { + reg_write |= SET_BITS(regAUDIO_RX_1, ARXIN, 1); + } else { + reg_write |= SET_BITS(regAUDIO_RX_1, ARXIN, 0); + } + + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Ext stereo gain set\n"); + extStereoIn.inputGain = gain; + + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + } + + return rc; +} + +/*! + * @brief Get the current gain level for the external stereo inputs. + * + * This function retrieves the current gain levels for the external stereo + * inputs. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The current external stereo input gain + * level. + * + * @retval PMIC_SUCCESS If the gain level was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the gain level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_stereo_in_gain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_STEREO_IN_GAIN * + const gain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE) && + (gain != (PMIC_AUDIO_STEREO_IN_GAIN *) NULL)) { + *gain = extStereoIn.inputGain; + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Set the output PGA gain level. + * + * This function sets the audio output PGA gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The output PGA gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the gain level could not be set. + */ +PMIC_STATUS pmic_audio_output_set_pgaGain(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_PGA_GAIN gain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = 0; + unsigned int reg_gain; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (!((gain >= OUTPGA_GAIN_MINUS_33DB) + && (gain <= OUTPGA_GAIN_PLUS_6DB))) { + rc = PMIC_NOT_SUPPORTED; + pr_debug("output set PGA gain - wrong gain value\n"); + } else { + reg_gain = gain + 2; + if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, ARXIN, 15) | + SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXIN, reg_gain) | + SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGARX, 15); + reg_write = SET_BITS(regAUDIO_RX_1, PGARX, reg_gain); + } else if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGAST, 15); + reg_write = SET_BITS(regAUDIO_RX_1, PGAST, reg_gain); + } + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Output PGA gains set\n"); + + if (handle == stDAC.handle) { + audioOutput.stDacoutputPGAGain = gain; + } else if (handle == vCodec.handle) { + audioOutput.vCodecoutputPGAGain = gain; + } else { + audioOutput.extStereooutputPGAGain = + gain; + } + } else { + pr_debug + ("Error writing PGA gains to register\n"); + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the output PGA gain level. + * + * This function retrieves the current audio output PGA gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The current output PGA gain level. + * + * @retval PMIC_SUCCESS If the gain level was successfully + * retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the gain level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_pgaGain(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_PGA_GAIN * + const gain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (gain != (PMIC_AUDIO_OUTPUT_PGA_GAIN *) NULL) { + if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + *gain = audioOutput.extStereooutputPGAGain; + rc = PMIC_SUCCESS; + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + *gain = audioOutput.vCodecoutputPGAGain; + rc = PMIC_SUCCESS; + } else if ((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) { + *gain = audioOutput.stDacoutputPGAGain; + rc = PMIC_SUCCESS; + } else { + rc = PMIC_PARAMETER_ERROR; + } + } else { + rc = PMIC_PARAMETER_ERROR; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Enable the output mixer. + * + * This function enables the output mixer for the audio stream that + * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or + * the external stereo inputs). + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mixer was successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mixer could not be enabled. + */ +PMIC_STATUS pmic_audio_output_enable_mixer(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + unsigned int reg_mask_mix = 0; + unsigned int reg_write_mix = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if (((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE))) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGASTEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, PGASTEN, 1); + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1); + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGARXEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, PGARXEN, 1); + audioOutput.vCodecOut = VCODEC_MIXER_OUT; + + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1); + } else if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + } + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write_mix, reg_mask_mix); + if (rc == PMIC_SUCCESS) { + pr_debug("Output PGA mixers enabled\n"); + rc = PMIC_SUCCESS; + } + + } else { + pr_debug("Error writing mixer enable to register\n"); + } + + } + + return rc; +} + +/*! + * @brief Disable the output mixer. + * + * This function disables the output mixer for the audio stream that + * corresponds to the current handle (i.e., the Voice CODEC, Stereo DAC, or + * the external stereo inputs). + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mixer was successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mixer could not be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_mixer(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + + unsigned int reg_mask_mix = 0; + unsigned int reg_write_mix = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + if (((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE))) { + /*reg_mask = SET_BITS(regAUDIO_RX_1, PGASTEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, PGASTEN, 0); */ + + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDSTDC, 0); + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + reg_mask = SET_BITS(regAUDIO_RX_1, PGARXEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, PGARXEN, 0); + audioOutput.vCodecOut = VCODEC_DIRECT_OUT; + + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDCDC, 0); + } else if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + /*reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 0); */ + + reg_mask_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + reg_write_mix = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + } + + if (reg_mask == 0) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write_mix, reg_mask_mix); + if (rc == PMIC_SUCCESS) { + pr_debug("Output PGA mixers disabled\n"); + } + } + } + return rc; +} + +/*! + * @brief Configure and enable the output balance amplifiers. + * + * This function configures and enables the output balance amplifiers. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftGain The desired left channel gain level. + * @param rightGain The desired right channel gain level. + * + * @retval PMIC_SUCCESS If the output balance amplifiers were + * successfully configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or gain levels were invalid. + * @retval PMIC_ERROR If the output balance amplifiers could not + * be reconfigured or enabled. + */ +PMIC_STATUS pmic_audio_output_set_balance(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_BALANCE_GAIN + leftGain, + const PMIC_AUDIO_OUTPUT_BALANCE_GAIN + rightGain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + unsigned int reg_mask_ch = 0; + unsigned int reg_write_ch = 0; + + /* No critical section required here since we are not updating any + * global data. + */ + + if (!((leftGain >= BAL_GAIN_MINUS_21DB) && (leftGain <= BAL_GAIN_0DB))) { + rc = PMIC_PARAMETER_ERROR; + } else if (!((rightGain >= BAL_GAIN_MINUS_21DB) + && (rightGain <= BAL_GAIN_0DB))) { + rc = PMIC_PARAMETER_ERROR; + } else { + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + /* In mc13783 only one channel can be attenuated wrt the other. + * It is not possible to specify attenuation for both + * This function will return an error if both channels + * are required to be attenuated + * The BALLR bit is set/reset depending on whether leftGain + * or rightGain is specified*/ + if ((rightGain == BAL_GAIN_0DB) + && (leftGain == BAL_GAIN_0DB)) { + /* Nothing to be done */ + } else if ((rightGain != BAL_GAIN_0DB) + && (leftGain == BAL_GAIN_0DB)) { + /* Attenuate right channel */ + reg_mask = SET_BITS(regAUDIO_RX_1, BAL, 7); + reg_mask_ch = SET_BITS(regAUDIO_RX_1, BALLR, 1); + reg_write = + SET_BITS(regAUDIO_RX_1, BAL, + (BAL_GAIN_0DB - rightGain)); + /* The enum and the register values are reversed in order .. */ + reg_write_ch = + SET_BITS(regAUDIO_RX_1, BALLR, 0); + /* BALLR = 0 selects right channel for atten */ + } else if ((rightGain == BAL_GAIN_0DB) + && (leftGain != BAL_GAIN_0DB)) { + /* Attenuate left channel */ + + reg_mask = SET_BITS(regAUDIO_RX_1, BAL, 7); + reg_mask_ch = SET_BITS(regAUDIO_RX_1, BALLR, 1); + reg_write = + SET_BITS(regAUDIO_RX_1, BAL, + (BAL_GAIN_0DB - leftGain)); + reg_write_ch = + SET_BITS(regAUDIO_RX_1, BALLR, 1); + /* BALLR = 1 selects left channel for atten */ + } else { + rc = PMIC_PARAMETER_ERROR; + } + + if ((reg_mask == 0) || (reg_mask_ch == 0)) { + + } else { + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write_ch, reg_mask_ch); + + if (rc == PMIC_SUCCESS) { + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write, + reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug + ("Output balance attenuation set\n"); + audioOutput.balanceLeftGain = + leftGain; + audioOutput.balanceRightGain = + rightGain; + } + } + } + } + } + return rc; +} + +/*! + * @brief Get the current output balance amplifier gain levels. + * + * This function retrieves the current output balance amplifier gain levels. + * + * @param handle Device handle from pmic_audio_open() call. + * @param leftGain The current left channel gain level. + * @param rightGain The current right channel gain level. + * + * @retval PMIC_SUCCESS If the output balance amplifier gain levels + * were successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the output balance amplifier gain levels + * could be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_balance(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_BALANCE_GAIN * + const leftGain, + PMIC_AUDIO_OUTPUT_BALANCE_GAIN * + const rightGain) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) && + ((leftGain != (PMIC_AUDIO_OUTPUT_BALANCE_GAIN *) NULL) && + (rightGain != (PMIC_AUDIO_OUTPUT_BALANCE_GAIN *) NULL))) { + *leftGain = audioOutput.balanceLeftGain; + *rightGain = audioOutput.balanceRightGain; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Configure and enable the output mono adder. + * + * This function configures and enables the output mono adder. + * + * @param handle Device handle from pmic_audio_open() call. + * @param mode The desired mono adder operating mode. + * + * @retval PMIC_SUCCESS If the mono adder was successfully + * configured and enabled. + * @retval PMIC_PARAMETER_ERROR If the handle or mono adder mode was + * invalid. + * @retval PMIC_ERROR If the mono adder could not be reconfigured + * or enabled. + */ +PMIC_STATUS pmic_audio_output_enable_mono_adder(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_MONO_ADDER_MODE + mode) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_write = 0; + unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, MONO, 3); + + /* No critical section required here since we are not updating any + * global data. + */ + + if ((mode >= MONO_ADDER_OFF) && (mode <= STEREO_OPPOSITE_PHASE)) { + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + if (mode == MONO_ADDER_OFF) { + reg_write = SET_BITS(regAUDIO_RX_1, MONO, 0); + } else if (mode == MONO_ADD_LEFT_RIGHT) { + reg_write = SET_BITS(regAUDIO_RX_1, MONO, 2); + } else if (mode == MONO_ADD_OPPOSITE_PHASE) { + reg_write = SET_BITS(regAUDIO_RX_1, MONO, 3); + } else { /* stereo opposite */ + + reg_write = SET_BITS(regAUDIO_RX_1, MONO, 1); + } + + rc = pmic_write_reg(REG_AUDIO_RX_1, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Output mono adder mode set\n"); + + } + + } else { + rc = PMIC_PARAMETER_ERROR; + } + } else { + rc = PMIC_PARAMETER_ERROR; + } + return rc; +} + +/*! + * @brief Disable the output mono adder. + * + * This function disables the output mono adder. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the mono adder was successfully + * disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mono adder could not be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_mono_adder(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_write = 0; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_1, MONO, 3); + + /* No critical section required here since we are not updating any + * global data. + */ + + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask); + } + + return rc; +} + +/*! + * @brief Configure the mono adder output gain level. + * + * This function configures the mono adder output amplifier gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The desired output gain level. + * + * @retval PMIC_SUCCESS If the mono adder output amplifier gain + * level was successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or gain level was invalid. + * @retval PMIC_ERROR If the mono adder output amplifier gain + * level could not be reconfigured. + */ +PMIC_STATUS pmic_audio_output_set_mono_adder_gain(const PMIC_AUDIO_HANDLE + handle, + const + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + gain) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +/*! + * @brief Get the current mono adder output gain level. + * + * This function retrieves the current mono adder output amplifier gain level. + * + * @param handle Device handle from pmic_audio_open() call. + * @param gain The current output gain level. + * + * @retval PMIC_SUCCESS If the mono adder output amplifier gain + * level was successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the mono adder output amplifier gain + * level could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_mono_adder_gain(const PMIC_AUDIO_HANDLE + handle, + PMIC_AUDIO_MONO_ADDER_OUTPUT_GAIN + * const gain) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + return rc; +} + +/*! + * @brief Set various audio output section options. + * + * This function sets one or more audio output section configuration + * options. The currently supported options include whether to disable + * the non-inverting mono speaker output, enabling the loudspeaker common + * bias circuit, enabling detection of headset insertion/removal, and + * whether to automatically disable the headset amplifiers when a headset + * insertion/removal has been detected. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The desired audio output section + * configuration options to be set. + * + * @retval PMIC_SUCCESS If the desired configuration options were + * all successfully set. + * @retval PMIC_PARAMETER_ERROR If the handle or configuration options + * were invalid. + * @retval PMIC_ERROR If the desired configuration options + * could not be set. + */ +PMIC_STATUS pmic_audio_output_set_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_CONFIG config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + if (config & MONO_SPEAKER_INVERT_OUT_ONLY) { + /* If this is one of the parameters */ + rc = PMIC_NOT_SUPPORTED; + } else { + if (config & MONO_LOUDSPEAKER_COMMON_BIAS) { + reg_mask = SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + } + if (config & HEADSET_DETECT_ENABLE) { + reg_mask |= SET_BITS(regAUDIO_RX_0, HSDETEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, HSDETEN, 1); + } + if (config & STEREO_HEADSET_AMP_AUTO_DISABLE) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + } + + if (reg_mask == 0) { + rc = PMIC_PARAMETER_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Output config set\n"); + audioOutput.config |= config; + + } + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Clear various audio output section options. + * + * This function clears one or more audio output section configuration + * options. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The desired audio output section + * configuration options to be cleared. + * + * @retval PMIC_SUCCESS If the desired configuration options were + * all successfully cleared. + * @retval PMIC_PARAMETER_ERROR If the handle or configuration options + * were invalid. + * @retval PMIC_ERROR If the desired configuration options + * could not be cleared. + */ +PMIC_STATUS pmic_audio_output_clear_config(const PMIC_AUDIO_HANDLE handle, + const PMIC_AUDIO_OUTPUT_CONFIG + config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + /*unsigned int reg_write_RX = 0; + unsigned int reg_mask_RX = 0; + unsigned int reg_write_TX = 0; + unsigned int reg_mask_TX = 0; */ + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) { + if (config & MONO_SPEAKER_INVERT_OUT_ONLY) { + /* If this is one of the parameters */ + rc = PMIC_NOT_SUPPORTED; + } else { + if (config & MONO_LOUDSPEAKER_COMMON_BIAS) { + reg_mask = SET_BITS(regAUDIO_RX_0, ALSPREF, 1); + reg_write = SET_BITS(regAUDIO_RX_0, ALSPREF, 0); + } + + if (config & HEADSET_DETECT_ENABLE) { + reg_mask |= SET_BITS(regAUDIO_RX_0, HSDETEN, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, HSDETEN, 0); + } + + if (config & STEREO_HEADSET_AMP_AUTO_DISABLE) { + reg_mask |= + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 1); + reg_write |= + SET_BITS(regAUDIO_RX_0, HSDETAUTOB, 0); + } + + if (reg_mask == 0) { + rc = PMIC_PARAMETER_ERROR; + } else { + rc = pmic_write_reg(REG_AUDIO_RX_0, + reg_write, reg_mask); + + if (rc == PMIC_SUCCESS) { + pr_debug("Output config cleared\n"); + audioOutput.config &= ~config; + + } + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Get the current audio output section options. + * + * This function retrieves the current audio output section configuration + * option settings. + * + * @param handle Device handle from pmic_audio_open() call. + * @param config The current audio output section + * configuration option settings. + * + * @retval PMIC_SUCCESS If the current configuration options were + * successfully retrieved. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the current configuration options + * could not be retrieved. + */ +PMIC_STATUS pmic_audio_output_get_config(const PMIC_AUDIO_HANDLE handle, + PMIC_AUDIO_OUTPUT_CONFIG * + const config) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Use a critical section to ensure a consistent hardware state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((((handle == stDAC.handle) && + (stDAC.handleState == HANDLE_IN_USE)) || + ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) || + ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE))) && + (config != (PMIC_AUDIO_OUTPUT_CONFIG *) NULL)) { + *config = audioOutput.config; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * @brief Enable the phantom ground circuit that is used to help identify + * the type of headset that has been inserted. + * + * This function enables the phantom ground circuit that is used to help + * identify the type of headset (e.g., stereo or mono) that has been inserted. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the phantom ground circuit was + * successfully enabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the phantom ground circuit could not + * be enabled. + */ +PMIC_STATUS pmic_audio_output_enable_phantom_ground() +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, HSPGDIS, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + rc = pmic_write_reg(REG_AUDIO_RX_0, 0, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("Phantom ground enabled\n"); + + } + return rc; +} + +/*! + * @brief Disable the phantom ground circuit that is used to help identify + * the type of headset that has been inserted. + * + * This function disables the phantom ground circuit that is used to help + * identify the type of headset (e.g., stereo or mono) that has been inserted. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the phantom ground circuit was + * successfully disabled. + * @retval PMIC_PARAMETER_ERROR If the handle was invalid. + * @retval PMIC_ERROR If the phantom ground circuit could not + * be disabled. + */ +PMIC_STATUS pmic_audio_output_disable_phantom_ground() +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + const unsigned int reg_mask = SET_BITS(regAUDIO_RX_0, HSPGDIS, 1); + + /* No critical section required here since we are not updating any + * global data. + */ + + rc = pmic_write_reg(REG_AUDIO_RX_0, 1, reg_mask); + if (rc == PMIC_SUCCESS) { + pr_debug("Phantom ground disabled\n"); + + } + return rc; +} + +/*@}*/ + +/************************************************************************** + * Static functions. + ************************************************************************** + */ + +/*! + * @name Audio Driver Internal Support Functions + * These non-exported internal functions are used to support the functionality + * of the exported audio APIs. + */ +/*@{*/ + +/*! + * @brief Enables the 5.6V boost for the microphone bias 2 circuit. + * + * This function enables the switching regulator SW3 and configures it to + * provide the 5.6V boost that is required for driving the microphone bias 2 + * circuit when using a 5-pole jack configuration (which is the case for the + * Sphinx board). + * + * @retval PMIC_SUCCESS The 5.6V boost was successfully enabled. + * @retval PMIC_ERROR Failed to enable the 5.6V boost. + */ +/* +static PMIC_STATUS pmic_audio_mic_boost_enable(void) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + + return rc; +} +*/ +/*! + * @brief Disables the 5.6V boost for the microphone bias 2 circuit. + * + * This function disables the switching regulator SW3 to turn off the 5.6V + * boost for the microphone bias 2 circuit. + * + * @retval PMIC_SUCCESS The 5.6V boost was successfully disabled. + * @retval PMIC_ERROR Failed to disable the 5.6V boost. + */ +/* +static PMIC_STATUS pmic_audio_mic_boost_disable(void) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + + return rc; +} +*/ + +/*! + * @brief Free a device handle previously acquired by calling pmic_audio_open(). + * + * Terminate further access to the PMIC audio hardware that was previously + * acquired by calling pmic_audio_open(). This now allows another thread to + * successfully call pmic_audio_open() to gain access. + * + * Note that we will shutdown/reset the Voice CODEC or Stereo DAC as well as + * any associated audio input/output components that are no longer required. + * + * Also note that this function should only be called with the mutex already + * acquired. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the close request was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + */ +static PMIC_STATUS pmic_audio_close_handle(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + + /* Match up the handle to the audio device and then close it. */ + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + /* Also shutdown the Stereo DAC hardware. The simplest way to + * do this is to simply call pmic_audio_reset_device() which will + * restore the ST_DAC register to it's initial power-on state. + * + * This will also shutdown the audio output section if no one + * else is still using it. + */ + rc = pmic_audio_reset_device(stDAC.handle); + + if (rc == PMIC_SUCCESS) { + stDAC.handle = AUDIO_HANDLE_NULL; + stDAC.handleState = HANDLE_FREE; + } + } else if ((handle == vCodec.handle) && + (vCodec.handleState == HANDLE_IN_USE)) { + /* Also shutdown the Voice CODEC and audio input hardware. The + * simplest way to do this is to simply call pmic_audio_reset_device() + * which will restore the AUD_CODEC register to it's initial + * power-on state. + * + * This will also shutdown the audio output section if no one + * else is still using it. + */ + rc = pmic_audio_reset_device(vCodec.handle); + if (rc == PMIC_SUCCESS) { + vCodec.handle = AUDIO_HANDLE_NULL; + vCodec.handleState = HANDLE_FREE; + } + } else if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + + /* Call pmic_audio_reset_device() here to shutdown the audio output + * section if no one else is still using it. + */ + rc = pmic_audio_reset_device(extStereoIn.handle); + + if (rc == PMIC_SUCCESS) { + extStereoIn.handle = AUDIO_HANDLE_NULL; + extStereoIn.handleState = HANDLE_FREE; + } + } + + return rc; +} + +/*! + * @brief Reset the selected audio hardware control registers to their + * power on state. + * + * This resets all of the audio hardware control registers currently + * associated with the device handle back to their power on states. For + * example, if the handle is associated with the Stereo DAC and a + * specific output port and output amplifiers, then this function will + * reset all of those components to their initial power on state. + * + * This function can only be called if the mutex has already been acquired. + * + * @param handle Device handle from pmic_audio_open() call. + * + * @retval PMIC_SUCCESS If the reset operation was successful. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_ERROR If the reset was unsuccessful. + */ +static PMIC_STATUS pmic_audio_reset_device(const PMIC_AUDIO_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + unsigned int reg_mask = 0; + + if ((handle == stDAC.handle) && (stDAC.handleState == HANDLE_IN_USE)) { + /* Also shutdown the audio output section if nobody else is using it. + if ((vCodec.handleState == HANDLE_FREE) && + (extStereoIn.handleState == HANDLE_FREE)) + { + pmic_write_reg(REG_RX_AUD_AMPS, RESET_RX_AUD_AMPS, + REG_FULLMASK); + } */ + + rc = pmic_write_reg(REG_AUDIO_STEREO_DAC, + RESET_ST_DAC, REG_FULLMASK); + + if (rc == PMIC_SUCCESS) { + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + RESET_SSI_NETWORK, + REG_SSI_STDAC_MASK); + if (rc == PMIC_SUCCESS) { + /* Also reset the driver state information to match. Note that we + * keep the device handle and event callback settings unchanged + * since these don't affect the actual hardware and we rely on + * the user to explicitly close the handle or deregister callbacks + */ + stDAC.busID = AUDIO_DATA_BUS_1; + stDAC.protocol = NORMAL_MSB_JUSTIFIED_MODE; + stDAC.protocol_set = false; + stDAC.masterSlave = BUS_MASTER_MODE; + stDAC.numSlots = USE_2_TIMESLOTS; + stDAC.clockIn = CLOCK_IN_CLIA; + stDAC.samplingRate = STDAC_RATE_44_1_KHZ; + stDAC.clockFreq = STDAC_CLI_13MHZ; + stDAC.invert = NO_INVERT; + stDAC.timeslot = USE_TS0_TS1; + stDAC.config = (PMIC_AUDIO_STDAC_CONFIG) 0; + + } + } + } else if ((handle == vCodec.handle) + && (vCodec.handleState == HANDLE_IN_USE)) { + /* Disable the audio input section when disabling the Voice CODEC. */ + pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX, REG_FULLMASK); + + rc = pmic_write_reg(REG_AUDIO_CODEC, + RESET_AUD_CODEC, REG_FULLMASK); + + if (rc == PMIC_SUCCESS) { + rc = pmic_write_reg(REG_AUDIO_SSI_NETWORK, + RESET_SSI_NETWORK, + REG_SSI_VCODEC_MASK); + if (rc == PMIC_SUCCESS) { + + /* Also reset the driver state information to match. Note that we + * keep the device handle and event callback settings unchanged + * since these don't affect the actual hardware and we rely on + * the user to explicitly close the handle or deregister callbacks + */ + vCodec.busID = AUDIO_DATA_BUS_2; + vCodec.protocol = NETWORK_MODE; + vCodec.protocol_set = false; + vCodec.masterSlave = BUS_SLAVE_MODE; + vCodec.numSlots = USE_4_TIMESLOTS; + vCodec.clockIn = CLOCK_IN_CLIB; + vCodec.samplingRate = VCODEC_RATE_8_KHZ; + vCodec.clockFreq = VCODEC_CLI_13MHZ; + vCodec.invert = NO_INVERT; + vCodec.timeslot = USE_TS0; + vCodec.config = + INPUT_HIGHPASS_FILTER | + OUTPUT_HIGHPASS_FILTER; + + } + } + + } else if ((handle == extStereoIn.handle) && + (extStereoIn.handleState == HANDLE_IN_USE)) { + /* Disable the Ext stereo Amplifier and disable it as analog mixer input */ + reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + pmic_write_reg(REG_AUDIO_RX_1, 0, reg_mask); + + reg_mask = SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + pmic_write_reg(REG_AUDIO_RX_0, 0, reg_mask); + + /* We don't need to reset any other registers for this case. */ + rc = PMIC_SUCCESS; + } + + return rc; +} + +/*! + * @brief Deregister the callback function and event mask currently associated + * with an audio device handle. + * + * This function deregisters any existing callback function and event mask for + * the given audio device handle. This is done by either calling the + * pmic_audio_clear_callback() API or by closing the device handle. + * + * Note that this function should only be called with the mutex already + * acquired. We will also acquire the spinlock here to prevent possible + * race conditions with the interrupt handler. + * + * @param[in] callback The current event callback function pointer. + * @param[in] eventMask The current audio event mask. + * + * @retval PMIC_SUCCESS If the callback function and event mask + * were both successfully deregistered. + * @retval PMIC_ERROR If either the callback function or the + * event mask was not successfully + * deregistered. + */ + +static PMIC_STATUS pmic_audio_deregister(void *callback, + PMIC_AUDIO_EVENTS * const eventMask) +{ + unsigned long flags; + pmic_event_callback_t eventNotify; + PMIC_STATUS rc = PMIC_SUCCESS; + + /* Deregister each of the PMIC events that we had previously + * registered for by calling pmic_event_subscribe(). + */ + if (*eventMask & (HEADSET_DETECTED)) { + /* We need to deregister for the A1 amplifier interrupt. */ + eventNotify.func = callback; + eventNotify.param = (void *)(CORE_EVENT_HSDETI); + if (pmic_event_unsubscribe(EVENT_HSDETI, eventNotify) == + PMIC_SUCCESS) { + *eventMask &= ~(HEADSET_DETECTED); + pr_debug("Deregistered for EVENT_HSDETI\n"); + } else { + rc = PMIC_ERROR; + } + } + + if (*eventMask & (HEADSET_STEREO)) { + /* We need to deregister for the A1 amplifier interrupt. */ + eventNotify.func = callback; + eventNotify.param = (void *)(CORE_EVENT_HSLI); + if (pmic_event_unsubscribe(EVENT_HSLI, eventNotify) == + PMIC_SUCCESS) { + *eventMask &= ~(HEADSET_STEREO); + pr_debug("Deregistered for EVENT_HSLI\n"); + } else { + rc = PMIC_ERROR; + } + } + if (*eventMask & (HEADSET_THERMAL_SHUTDOWN)) { + /* We need to deregister for the A1 amplifier interrupt. */ + eventNotify.func = callback; + eventNotify.param = (void *)(CORE_EVENT_ALSPTHI); + if (pmic_event_unsubscribe(EVENT_ALSPTHI, eventNotify) == + PMIC_SUCCESS) { + *eventMask &= ~(HEADSET_THERMAL_SHUTDOWN); + pr_debug("Deregistered for EVENT_ALSPTHI\n"); + } else { + rc = PMIC_ERROR; + } + } + if (*eventMask & (HEADSET_SHORT_CIRCUIT)) { + /* We need to deregister for the A1 amplifier interrupt. */ + eventNotify.func = callback; + eventNotify.param = (void *)(CORE_EVENT_AHSSHORTI); + if (pmic_event_unsubscribe(EVENT_AHSSHORTI, eventNotify) == + PMIC_SUCCESS) { + *eventMask &= ~(HEADSET_SHORT_CIRCUIT); + pr_debug("Deregistered for EVENT_AHSSHORTI\n"); + } else { + rc = PMIC_ERROR; + } + } + + if (rc == PMIC_SUCCESS) { + /* We need to grab the spinlock here to create a critical section to + * avoid any possible race conditions with the interrupt handler + */ + spin_lock_irqsave(&lock, flags); + + /* Restore the initial reset values for the callback function + * and event mask parameters. This should be NULL and zero, + * respectively. + */ + callback = NULL; + *eventMask = 0; + + /* Exit the critical section. */ + spin_unlock_irqrestore(&lock, flags); + } + + return rc; +} + +/*! + * @brief enable/disable fm output. + * + * @param[in] enable true to enable false to disable + */ +PMIC_STATUS pmic_audio_fm_output_enable(bool enable) +{ + unsigned int reg_mask = 0; + unsigned int reg_write = 0; + PMIC_STATUS rc = PMIC_PARAMETER_ERROR; + if (enable) { + pmic_audio_antipop_enable(ANTI_POP_RAMP_FAST); + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSLEN, 1); + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSREN, 1); + + reg_mask |= SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, AHSSEL, 1); + + reg_mask |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + + reg_mask |= SET_BITS(regAUDIO_RX_0, HSPGDIS, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, HSPGDIS, 0); + } else { + reg_mask |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 1); + reg_write |= SET_BITS(regAUDIO_RX_0, ADDRXIN, 0); + } + rc = pmic_write_reg(REG_AUDIO_RX_0, reg_write, reg_mask); + if (rc != PMIC_SUCCESS) + return rc; + if (enable) { + reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + } else { + reg_mask = SET_BITS(regAUDIO_RX_1, ARXINEN, 1); + reg_write = SET_BITS(regAUDIO_RX_1, ARXINEN, 0); + } + rc = pmic_write_reg(REG_AUDIO_RX_1, reg_write, reg_mask); + return rc; +} + +/*@}*/ + +/************************************************************************** + * Module initialization and termination functions. + * + * Note that if this code is compiled into the kernel, then the + * module_init() function will be called within the device_initcall() + * group. + ************************************************************************** + */ + +/*! + * @name Audio Driver Loading/Unloading Functions + * These non-exported internal functions are used to support the audio + * device driver initialization and de-initialization operations. + */ +/*@{*/ + +/*! + * @brief This is the audio device driver initialization function. + * + * This function is called by the kernel when this device driver is first + * loaded. + */ +static int __init mc13783_pmic_audio_init(void) +{ + printk(KERN_INFO "PMIC Audio driver loading...\n"); + + return 0; +} + +/*! + * @brief This is the audio device driver de-initialization function. + * + * This function is called by the kernel when this device driver is about + * to be unloaded. + */ +static void __exit mc13783_pmic_audio_exit(void) +{ + printk(KERN_INFO "PMIC Audio driver unloading...\n"); + + /* Close all device handles that are still open. This will also + * deregister any callbacks that may still be active. + */ + if (stDAC.handleState == HANDLE_IN_USE) { + pmic_audio_close(stDAC.handle); + } + if (vCodec.handleState == HANDLE_IN_USE) { + pmic_audio_close(vCodec.handle); + } + if (extStereoIn.handleState == HANDLE_IN_USE) { + pmic_audio_close(extStereoIn.handle); + } + + /* Explicitly reset all of the audio registers so that there is no + * possibility of leaving the audio hardware in a state + * where it can cause problems if there is no device driver loaded. + */ + pmic_write_reg(REG_AUDIO_STEREO_DAC, RESET_ST_DAC, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_CODEC, RESET_AUD_CODEC, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_TX, RESET_AUDIO_TX, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_SSI_NETWORK, RESET_SSI_NETWORK, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_RX_0, RESET_AUDIO_RX_0, REG_FULLMASK); + pmic_write_reg(REG_AUDIO_RX_1, RESET_AUDIO_RX_1, REG_FULLMASK); +} + +/*@}*/ + +/* + * Module entry points and description information. + */ + +module_init(mc13783_pmic_audio_init); +module_exit(mc13783_pmic_audio_exit); + +MODULE_DESCRIPTION("PMIC - mc13783 ADC driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13783/pmic_battery.c b/drivers/mxc/pmic/mc13783/pmic_battery.c new file mode 100644 index 000000000000..f721218e8fb1 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_battery.c @@ -0,0 +1,1220 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_battery.c + * @brief This is the main file of PMIC(mc13783) Battery driver. + * + * @ingroup PMIC_BATTERY + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "pmic_battery_defs.h" + +#include +#ifdef CONFIG_MXC_HWEVENT +#include +#endif + +static int pmic_battery_major; + +/*! + * Number of users waiting in suspendq + */ +static int swait; + +/*! + * To indicate whether any of the battery devices are suspending + */ +static int suspend_flag; + +/*! + * The suspendq is used to block application calls + */ +static wait_queue_head_t suspendq; + +static struct class *pmic_battery_class; + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_batt_enable_charger); +EXPORT_SYMBOL(pmic_batt_disable_charger); +EXPORT_SYMBOL(pmic_batt_set_charger); +EXPORT_SYMBOL(pmic_batt_get_charger_setting); +EXPORT_SYMBOL(pmic_batt_get_charge_current); +EXPORT_SYMBOL(pmic_batt_enable_eol); +EXPORT_SYMBOL(pmic_batt_bp_enable_eol); +EXPORT_SYMBOL(pmic_batt_disable_eol); +EXPORT_SYMBOL(pmic_batt_set_out_control); +EXPORT_SYMBOL(pmic_batt_set_threshold); +EXPORT_SYMBOL(pmic_batt_led_control); +EXPORT_SYMBOL(pmic_batt_set_reverse_supply); +EXPORT_SYMBOL(pmic_batt_set_unregulated); +EXPORT_SYMBOL(pmic_batt_set_5k_pull); +EXPORT_SYMBOL(pmic_batt_event_subscribe); +EXPORT_SYMBOL(pmic_batt_event_unsubscribe); + +static DECLARE_MUTEX(count_mutex); /* open count mutex */ +static int open_count; /* open count for device file */ + +/*! + * Callback function for events, we want on MGN board + */ +static void callback_chg_detect(void) +{ +#ifdef CONFIG_MXC_HWEVENT + t_sensor_bits sensor; + struct mxc_hw_event event = { HWE_BAT_CHARGER_PLUG, 0 }; + + pr_debug("In callback_chg_detect\n"); + + /* get sensor values */ + pmic_get_sensors(&sensor); + + pr_debug("Callback, charger detect:%d\n", sensor.sense_chgdets); + + if (sensor.sense_chgdets) + event.args = 1; + else + event.args = 0; + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static void callback_low_battery(void) +{ +#ifdef CONFIG_MXC_HWEVENT + struct mxc_hw_event event = { HWE_BAT_BATTERY_LOW, 0 }; + + pr_debug("In callback_low_battery\n"); + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static void callback_power_fail(void) +{ +#ifdef CONFIG_MXC_HWEVENT + struct mxc_hw_event event = { HWE_BAT_POWER_FAILED, 0 }; + + pr_debug("In callback_power_fail\n"); + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static void callback_chg_overvoltage(void) +{ +#ifdef CONFIG_MXC_HWEVENT + struct mxc_hw_event event = { HWE_BAT_CHARGER_OVERVOLTAGE, 0 }; + + pr_debug("In callback_chg_overvoltage\n"); + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static void callback_chg_full(void) +{ +#ifdef CONFIG_MXC_HWEVENT + t_sensor_bits sensor; + struct mxc_hw_event event = { HWE_BAT_CHARGER_FULL, 0 }; + + pr_debug("In callback_chg_full\n"); + + /* disable charge function */ + pmic_batt_disable_charger(BATT_MAIN_CHGR); + + /* get charger sensor */ + pmic_get_sensors(&sensor); + + /* if did not detect the charger */ + if (sensor.sense_chgdets) + return; + /* send hardware event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +/*! + * This is the suspend of power management for the pmic battery API. + * It suports SAVE and POWER_DOWN state. + * + * @param pdev the device + * @param state the state + * + * @return This function returns 0 if successful. + */ +static int pmic_battery_suspend(struct platform_device *pdev, + pm_message_t state) +{ + unsigned int reg_value = 0; + + suspend_flag = 1; + CHECK_ERROR(pmic_write_reg(REG_CHARGER, reg_value, PMIC_ALL_BITS)); + + return 0; +}; + +/*! + * This is the resume of power management for the pmic battery API. + * It suports RESTORE state. + * + * @param pdev the device + * + * @return This function returns 0 if successful. + */ +static int pmic_battery_resume(struct platform_device *pdev) +{ + suspend_flag = 0; + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +}; + +/*! + * This function is used to start charging a battery. For different charger, + * different voltage and current range are supported. \n + * + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Charging voltage. + * @param c_current Charging current. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_enable_charger(t_batt_charger chgr, + unsigned char c_voltage, + unsigned char c_current) +{ + unsigned int val, mask, reg; + + val = 0; + mask = 0; + reg = 0; + + if (suspend_flag == 1) + return PMIC_ERROR; + + switch (chgr) { + case BATT_MAIN_CHGR: + val = BITFVAL(MC13783_BATT_DAC_DAC, c_current) | + BITFVAL(MC13783_BATT_DAC_V_DAC, c_voltage); + mask = BITFMASK(MC13783_BATT_DAC_DAC) | + BITFMASK(MC13783_BATT_DAC_V_DAC); + reg = REG_CHARGER; + break; + + case BATT_CELL_CHGR: + val = BITFVAL(MC13783_BATT_DAC_V_COIN, c_voltage) | + BITFVAL(MC13783_BATT_DAC_COIN_CH_EN, + MC13783_BATT_DAC_COIN_CH_EN_ENABLED); + mask = BITFMASK(MC13783_BATT_DAC_V_COIN) | + BITFMASK(MC13783_BATT_DAC_COIN_CH_EN); + reg = REG_POWER_CONTROL_0; + break; + + case BATT_TRCKLE_CHGR: + val = BITFVAL(MC13783_BATT_DAC_TRCKLE, c_current); + mask = BITFMASK(MC13783_BATT_DAC_TRCKLE); + reg = REG_CHARGER; + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function turns off a charger. + * + * @param chgr Charger as defined in \b t_batt_charger. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_disable_charger(t_batt_charger chgr) +{ + unsigned int val, mask, reg; + + val = 0; + mask = 0; + reg = 0; + + if (suspend_flag == 1) + return PMIC_ERROR; + switch (chgr) { + case BATT_MAIN_CHGR: + val = BITFVAL(MC13783_BATT_DAC_DAC, 0) | + BITFVAL(MC13783_BATT_DAC_V_DAC, 0); + mask = BITFMASK(MC13783_BATT_DAC_DAC) | + BITFMASK(MC13783_BATT_DAC_V_DAC); + reg = REG_CHARGER; + break; + + case BATT_CELL_CHGR: + val = BITFVAL(MC13783_BATT_DAC_COIN_CH_EN, + MC13783_BATT_DAC_COIN_CH_EN_DISABLED); + mask = BITFMASK(MC13783_BATT_DAC_COIN_CH_EN); + reg = REG_POWER_CONTROL_0; + break; + + case BATT_TRCKLE_CHGR: + val = BITFVAL(MC13783_BATT_DAC_TRCKLE, 0); + mask = BITFMASK(MC13783_BATT_DAC_TRCKLE); + reg = REG_CHARGER; + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to change the charger setting. + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Charging voltage. + * @param c_current Charging current. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_charger(t_batt_charger chgr, + unsigned char c_voltage, + unsigned char c_current) +{ + unsigned int val, mask, reg; + + val = 0; + mask = 0; + reg = 0; + + if (suspend_flag == 1) + return PMIC_ERROR; + + switch (chgr) { + case BATT_MAIN_CHGR: + val = BITFVAL(MC13783_BATT_DAC_DAC, c_current) | + BITFVAL(MC13783_BATT_DAC_V_DAC, c_voltage); + mask = BITFMASK(MC13783_BATT_DAC_DAC) | + BITFMASK(MC13783_BATT_DAC_V_DAC); + reg = REG_CHARGER; + break; + + case BATT_CELL_CHGR: + val = BITFVAL(MC13783_BATT_DAC_V_COIN, c_voltage); + mask = BITFMASK(MC13783_BATT_DAC_V_COIN); + reg = REG_POWER_CONTROL_0; + break; + + case BATT_TRCKLE_CHGR: + val = BITFVAL(MC13783_BATT_DAC_TRCKLE, c_current); + mask = BITFMASK(MC13783_BATT_DAC_TRCKLE); + reg = REG_CHARGER; + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, val, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function is used to retrive the charger setting. + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Output parameter for charging voltage setting. + * @param c_current Output parameter for charging current setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_charger_setting(t_batt_charger chgr, + unsigned char *c_voltage, + unsigned char *c_current) +{ + unsigned int val, reg; + + reg = 0; + + if (suspend_flag == 1) + return PMIC_ERROR; + + switch (chgr) { + case BATT_MAIN_CHGR: + case BATT_TRCKLE_CHGR: + reg = REG_CHARGER; + break; + case BATT_CELL_CHGR: + reg = REG_POWER_CONTROL_0; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, &val, PMIC_ALL_BITS)); + + switch (chgr) { + case BATT_MAIN_CHGR: + *c_voltage = BITFEXT(val, MC13783_BATT_DAC_V_DAC);; + *c_current = BITFEXT(val, MC13783_BATT_DAC_DAC); + break; + + case BATT_CELL_CHGR: + *c_voltage = BITFEXT(val, MC13783_BATT_DAC_V_COIN); + *c_current = 0; + break; + + case BATT_TRCKLE_CHGR: + *c_voltage = 0; + *c_current = BITFEXT(val, MC13783_BATT_DAC_TRCKLE); + break; + + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery voltage. + * + * @param b_voltage Output parameter for voltage setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_batt_voltage(unsigned short *b_voltage) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + channel = BATTERY_VOLTAGE; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *b_voltage = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery current. + * + * @param b_current Output parameter for current setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_batt_current(unsigned short *b_current) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + + channel = BATTERY_CURRENT; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *b_current = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery temperature. + * + * @param b_temper Output parameter for temperature setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_batt_temperature(unsigned short *b_temper) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + + channel = GEN_PURPOSE_AD5; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *b_temper = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery charging voltage. + * + * @param c_voltage Output parameter for charging voltage setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_charge_voltage(unsigned short *c_voltage) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + + channel = CHARGE_VOLTAGE; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *c_voltage = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function is retrives the main battery charging current. + * + * @param c_current Output parameter for charging current setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_charge_current(unsigned short *c_current) +{ + t_channel channel; + unsigned short result[8]; + + if (suspend_flag == 1) + return PMIC_ERROR; + + channel = CHARGE_CURRENT; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *c_current = result[0]; + + return PMIC_SUCCESS; +} + +/*! + * This function enables End-of-Life comparator. Not supported on + * mc13783. Use pmic_batt_bp_enable_eol function. + * + * @param threshold End-of-Life threshold. + * + * @return This function returns PMIC_UNSUPPORTED + */ +PMIC_STATUS pmic_batt_enable_eol(unsigned char threshold) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function enables End-of-Life comparator. + * + * @param typical Falling Edge Threshold threshold. + * @verbatim + BPDET UVDET LOBATL + ____ _____ ___________ + 0 2.6 UVDET + 0.2 + 1 2.6 UVDET + 0.3 + 2 2.6 UVDET + 0.4 + 3 2.6 UVDET + 0.5 + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_bp_enable_eol(t_bp_threshold typical) +{ + unsigned int val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_EOL_CMP_EN, + MC13783_BATT_DAC_EOL_CMP_EN_ENABLE) | + BITFVAL(MC13783_BATT_DAC_EOL_SEL, typical); + mask = BITFMASK(MC13783_BATT_DAC_EOL_CMP_EN) | + BITFMASK(MC13783_BATT_DAC_EOL_SEL); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables End-of-Life comparator. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_disable_eol(void) +{ + unsigned int val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_EOL_CMP_EN, + MC13783_BATT_DAC_EOL_CMP_EN_DISABLE); + mask = BITFMASK(MC13783_BATT_DAC_EOL_CMP_EN); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets the output controls. + * It sets the FETOVRD and FETCTRL bits of mc13783 + * + * @param control type of control. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_set_out_control(t_control control) +{ + unsigned int val, mask; + if (suspend_flag == 1) + return PMIC_ERROR; + + switch (control) { + case CONTROL_HARDWARE: + val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 0) | + BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 0); + mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | + BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); + break; + case CONTROL_BPFET_LOW: + val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 1) | + BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 0); + mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | + BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); + break; + case CONTROL_BPFET_HIGH: + val = BITFVAL(MC13783_BATT_DAC_FETOVRD_EN, 1) | + BITFVAL(MC13783_BATT_DAC_FETCTRL_EN, 1); + mask = BITFMASK(MC13783_BATT_DAC_FETOVRD_EN) | + BITFMASK(MC13783_BATT_DAC_FETCTRL_EN); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function sets over voltage threshold. + * + * @param threshold value of over voltage threshold. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_set_threshold(int threshold) +{ + unsigned int val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + if (threshold > BAT_THRESHOLD_MAX) + return PMIC_PARAMETER_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_OVCTRL, threshold); + mask = BITFMASK(MC13783_BATT_DAC_OVCTRL); + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function controls charge LED. + * + * @param on If on is ture, LED will be turned on, + * or otherwise, LED will be turned off. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_led_control(bool on) +{ + unsigned val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_LED_EN, on); + mask = BITFMASK(MC13783_BATT_DAC_LED_EN); + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets reverse supply mode. + * + * @param enable If enable is ture, reverse supply mode is enable, + * or otherwise, reverse supply mode is disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_reverse_supply(bool enable) +{ + unsigned val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_REVERSE_SUPPLY, enable); + mask = BITFMASK(MC13783_BATT_DAC_REVERSE_SUPPLY); + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets unregulatored charging mode on main battery. + * + * @param enable If enable is ture, unregulated charging mode is + * enable, or otherwise, disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_unregulated(bool enable) +{ + unsigned val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_UNREGULATED, enable); + mask = BITFMASK(MC13783_BATT_DAC_UNREGULATED); + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets a 5K pull down at CHRGRAW. + * To be used in the dual path charging configuration. + * + * @param enable If enable is true, 5k pull down is + * enable, or otherwise, disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_5k_pull(bool enable) +{ + unsigned val, mask; + + if (suspend_flag == 1) + return PMIC_ERROR; + + val = BITFVAL(MC13783_BATT_DAC_5K, enable); + mask = BITFMASK(MC13783_BATT_DAC_5K); + + CHECK_ERROR(pmic_write_reg(REG_CHARGER, val, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to un/subscribe on battery event IT. + * + * @param event type of event. + * @param callback event callback function. + * @param sub define if Un/subscribe event. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS mc13783_battery_event(t_batt_event event, void *callback, bool sub) +{ + pmic_event_callback_t bat_callback; + type_event bat_event; + + bat_callback.func = callback; + bat_callback.param = NULL; + switch (event) { + case BAT_IT_CHG_DET: + bat_event = EVENT_CHGDETI; + break; + case BAT_IT_CHG_OVERVOLT: + bat_event = EVENT_CHGOVI; + break; + case BAT_IT_CHG_REVERSE: + bat_event = EVENT_CHGREVI; + break; + case BAT_IT_CHG_SHORT_CIRCUIT: + bat_event = EVENT_CHGSHORTI; + break; + case BAT_IT_CCCV: + bat_event = EVENT_CCCVI; + break; + case BAT_IT_BELOW_THRESHOLD: + bat_event = EVENT_CHRGCURRI; + break; + default: + return PMIC_PARAMETER_ERROR; + } + if (sub == true) { + CHECK_ERROR(pmic_event_subscribe(bat_event, bat_callback)); + } else { + CHECK_ERROR(pmic_event_unsubscribe(bat_event, bat_callback)); + } + return 0; +} + +/*! + * This function is used to subscribe on battery event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_event_subscribe(t_batt_event event, void *callback) +{ + if (suspend_flag == 1) + return PMIC_ERROR; + + return mc13783_battery_event(event, callback, true); +} + +/*! + * This function is used to un subscribe on battery event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_event_unsubscribe(t_batt_event event, void *callback) +{ + if (suspend_flag == 1) + return PMIC_ERROR; + + return mc13783_battery_event(event, callback, false); +} + +/*! + * This function implements IOCTL controls on a PMIC Battery device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_battery_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + t_charger_setting *chgr_setting = NULL; + unsigned short c_current; + unsigned int bc_info; + t_eol_setting *eol_setting; + + if (_IOC_TYPE(cmd) != 'p') + return -ENOTTY; + + chgr_setting = kmalloc(sizeof(t_charger_setting), GFP_KERNEL); + eol_setting = kmalloc(sizeof(t_eol_setting), GFP_KERNEL); + switch (cmd) { + case PMIC_BATT_CHARGER_CONTROL: + if (chgr_setting == NULL) + return -ENOMEM; + + if (copy_from_user(chgr_setting, (t_charger_setting *) arg, + sizeof(t_charger_setting))) { + kfree(chgr_setting); + return -EFAULT; + } + + if (chgr_setting->on != false) { + CHECK_ERROR_KFREE(pmic_batt_enable_charger + (chgr_setting->chgr, + chgr_setting->c_voltage, + chgr_setting->c_current), + (kfree(chgr_setting))); + } else { + CHECK_ERROR(pmic_batt_disable_charger + (chgr_setting->chgr)); + } + + kfree(chgr_setting); + break; + + case PMIC_BATT_SET_CHARGER: + if (chgr_setting == NULL) + return -ENOMEM; + + if (copy_from_user(chgr_setting, (t_charger_setting *) arg, + sizeof(t_charger_setting))) { + kfree(chgr_setting); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_batt_set_charger(chgr_setting->chgr, + chgr_setting->c_voltage, + chgr_setting-> + c_current), + (kfree(chgr_setting))); + + kfree(chgr_setting); + break; + + case PMIC_BATT_GET_CHARGER: + if (chgr_setting == NULL) + return -ENOMEM; + + if (copy_from_user(chgr_setting, (t_charger_setting *) arg, + sizeof(t_charger_setting))) { + kfree(chgr_setting); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_batt_get_charger_setting + (chgr_setting->chgr, &chgr_setting->c_voltage, + &chgr_setting->c_current), + (kfree(chgr_setting))); + if (copy_to_user + ((t_charger_setting *) arg, chgr_setting, + sizeof(t_charger_setting))) { + return -EFAULT; + } + + kfree(chgr_setting); + break; + + case PMIC_BATT_GET_CHARGER_SENSOR: + { + t_sensor_bits sensor; + pmic_get_sensors(&sensor); + if (copy_to_user + ((unsigned int *)arg, &sensor.sense_chgdets, + sizeof(unsigned int))) + return -EFAULT; + + break; + } + case PMIC_BATT_GET_BATTERY_VOLTAGE: + CHECK_ERROR(pmic_batt_get_batt_voltage(&c_current)); + bc_info = (unsigned int)c_current * 2300 / 1023 + 2400; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + + break; + + case PMIC_BATT_GET_BATTERY_CURRENT: + CHECK_ERROR(pmic_batt_get_batt_current(&c_current)); + bc_info = (unsigned int)c_current * 5750 / 1023; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + break; + + case PMIC_BATT_GET_BATTERY_TEMPERATURE: + CHECK_ERROR(pmic_batt_get_batt_temperature(&c_current)); + bc_info = (unsigned int)c_current; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + + break; + + case PMIC_BATT_GET_CHARGER_VOLTAGE: + CHECK_ERROR(pmic_batt_get_charge_voltage(&c_current)); + bc_info = (unsigned int)c_current * 23000 / 1023; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + + break; + + case PMIC_BATT_GET_CHARGER_CURRENT: + CHECK_ERROR(pmic_batt_get_charge_current(&c_current)); + bc_info = (unsigned int)c_current * 5750 / 1023; + if (copy_to_user((unsigned int *)arg, &bc_info, + sizeof(unsigned int))) + return -EFAULT; + + break; + + case PMIC_BATT_EOL_CONTROL: + if (eol_setting == NULL) + return -ENOMEM; + + if (copy_from_user(eol_setting, (t_eol_setting *) arg, + sizeof(t_eol_setting))) { + kfree(eol_setting); + return -EFAULT; + } + + if (eol_setting->enable != false) { + CHECK_ERROR_KFREE(pmic_batt_bp_enable_eol + (eol_setting->typical), + (kfree(chgr_setting))); + } else { + CHECK_ERROR_KFREE(pmic_batt_disable_eol(), + (kfree(chgr_setting))); + } + + kfree(eol_setting); + break; + + case PMIC_BATT_SET_OUT_CONTROL: + CHECK_ERROR(pmic_batt_set_out_control((t_control) arg)); + break; + + case PMIC_BATT_SET_THRESHOLD: + CHECK_ERROR(pmic_batt_set_threshold((int)arg)); + break; + + case PMIC_BATT_LED_CONTROL: + CHECK_ERROR(pmic_batt_led_control((bool) arg)); + break; + + case PMIC_BATT_REV_SUPP_CONTROL: + CHECK_ERROR(pmic_batt_set_reverse_supply((bool) arg)); + break; + + case PMIC_BATT_UNREG_CONTROL: + CHECK_ERROR(pmic_batt_set_unregulated((bool) arg)); + break; + + default: + return -EINVAL; + } + return 0; +} + +/*! + * This function implements the open method on a Pmic battery device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_battery_open(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + + /* check open count, if open firstly, register callbacks */ + down(&count_mutex); + if (open_count++ > 0) { + up(&count_mutex); + return 0; + } + + pr_debug("Subscribe the callbacks\n"); + /* register battery event callback */ + if (pmic_batt_event_subscribe(BAT_IT_CHG_DET, callback_chg_detect)) { + pr_debug("Failed to subscribe the charger detect callback\n"); + goto event_err1; + } + if (pmic_power_event_sub(PWR_IT_LOBATLI, callback_power_fail)) { + pr_debug("Failed to subscribe the power failed callback\n"); + goto event_err2; + } + if (pmic_power_event_sub(PWR_IT_LOBATHI, callback_low_battery)) { + pr_debug("Failed to subscribe the low battery callback\n"); + goto event_err3; + } + if (pmic_batt_event_subscribe + (BAT_IT_CHG_OVERVOLT, callback_chg_overvoltage)) { + pr_debug("Failed to subscribe the low battery callback\n"); + goto event_err4; + } + if (pmic_batt_event_subscribe + (BAT_IT_BELOW_THRESHOLD, callback_chg_full)) { + pr_debug("Failed to subscribe the charge full callback\n"); + goto event_err5; + } + + up(&count_mutex); + + return 0; + + /* un-subscribe the event callbacks */ +event_err5: + pmic_batt_event_unsubscribe(BAT_IT_CHG_OVERVOLT, + callback_chg_overvoltage); +event_err4: + pmic_power_event_unsub(PWR_IT_LOBATHI, callback_low_battery); +event_err3: + pmic_power_event_unsub(PWR_IT_LOBATLI, callback_power_fail); +event_err2: + pmic_batt_event_unsubscribe(BAT_IT_CHG_DET, callback_chg_detect); +event_err1: + + open_count--; + up(&count_mutex); + + return -EFAULT; + +} + +/*! + * This function implements the release method on a Pmic battery device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_battery_release(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + + /* check open count, if open firstly, register callbacks */ + down(&count_mutex); + if (--open_count == 0) { + /* unregister these event callback */ + pr_debug("Unsubscribe the callbacks\n"); + pmic_batt_event_unsubscribe(BAT_IT_BELOW_THRESHOLD, + callback_chg_full); + pmic_batt_event_unsubscribe(BAT_IT_CHG_OVERVOLT, + callback_chg_overvoltage); + pmic_power_event_unsub(PWR_IT_LOBATHI, callback_low_battery); + pmic_power_event_unsub(PWR_IT_LOBATLI, callback_power_fail); + pmic_batt_event_unsubscribe(BAT_IT_CHG_DET, + callback_chg_detect); + } + up(&count_mutex); + + return 0; +} + +static struct file_operations pmic_battery_fops = { + .owner = THIS_MODULE, + .ioctl = pmic_battery_ioctl, + .open = pmic_battery_open, + .release = pmic_battery_release, +}; + +static int pmic_battery_remove(struct platform_device *pdev) +{ + device_destroy(pmic_battery_class, MKDEV(pmic_battery_major, 0)); + class_destroy(pmic_battery_class); + unregister_chrdev(pmic_battery_major, PMIC_BATTERY_STRING); + return 0; +} + +static int pmic_battery_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *temp_class; + + pmic_battery_major = register_chrdev(0, PMIC_BATTERY_STRING, + &pmic_battery_fops); + + if (pmic_battery_major < 0) { + printk(KERN_ERR "Unable to get a major for pmic_battery\n"); + return pmic_battery_major; + } + init_waitqueue_head(&suspendq); + + pmic_battery_class = class_create(THIS_MODULE, PMIC_BATTERY_STRING); + if (IS_ERR(pmic_battery_class)) { + printk(KERN_ERR "Error creating PMIC battery class.\n"); + ret = PTR_ERR(pmic_battery_class); + goto err_out1; + } + + temp_class = device_create(pmic_battery_class, NULL, + MKDEV(pmic_battery_major, 0), NULL, + PMIC_BATTERY_STRING); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "Error creating PMIC battery class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + pmic_batt_led_control(true); + pmic_batt_set_5k_pull(true); + + printk(KERN_INFO "PMIC Battery successfully probed\n"); + + return ret; + + err_out2: + class_destroy(pmic_battery_class); + err_out1: + unregister_chrdev(pmic_battery_major, PMIC_BATTERY_STRING); + return ret; +} + +static struct platform_driver pmic_battery_driver_ldm = { + .driver = { + .name = "pmic_battery", + .bus = &platform_bus_type, + }, + .suspend = pmic_battery_suspend, + .resume = pmic_battery_resume, + .probe = pmic_battery_probe, + .remove = pmic_battery_remove, +}; + +/* + * Init and Exit + */ + +static int __init pmic_battery_init(void) +{ + pr_debug("PMIC Battery driver loading...\n"); + return platform_driver_register(&pmic_battery_driver_ldm); +} + +static void __exit pmic_battery_exit(void) +{ + platform_driver_unregister(&pmic_battery_driver_ldm); + pr_debug("PMIC Battery driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +module_init(pmic_battery_init); +module_exit(pmic_battery_exit); + +MODULE_DESCRIPTION("pmic_battery driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13783/pmic_battery_defs.h b/drivers/mxc/pmic/mc13783/pmic_battery_defs.h new file mode 100644 index 000000000000..29704de301d1 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_battery_defs.h @@ -0,0 +1,81 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_battery_defs.h + * @brief This is the internal header for PMIC(mc13783) Battery driver. + * + * @ingroup PMIC_BATTERY + */ + +#ifndef __PMIC_BATTERY_DEFS_H__ +#define __PMIC_BATTERY_DEFS_H__ + +#define PMIC_BATTERY_STRING "pmic_battery" + +/* REG_CHARGE */ +#define MC13783_BATT_DAC_V_DAC_LSH 0 +#define MC13783_BATT_DAC_V_DAC_WID 3 +#define MC13783_BATT_DAC_DAC_LSH 3 +#define MC13783_BATT_DAC_DAC_WID 4 +#define MC13783_BATT_DAC_TRCKLE_LSH 7 +#define MC13783_BATT_DAC_TRCKLE_WID 3 +#define MC13783_BATT_DAC_FETOVRD_EN_LSH 10 +#define MC13783_BATT_DAC_FETOVRD_EN_WID 1 +#define MC13783_BATT_DAC_FETCTRL_EN_LSH 11 +#define MC13783_BATT_DAC_FETCTRL_EN_WID 1 +#define MC13783_BATT_DAC_REVERSE_SUPPLY_LSH 13 +#define MC13783_BATT_DAC_REVERSE_SUPPLY_WID 1 +#define MC13783_BATT_DAC_OVCTRL_LSH 15 +#define MC13783_BATT_DAC_OVCTRL_WID 2 +#define MC13783_BATT_DAC_UNREGULATED_LSH 17 +#define MC13783_BATT_DAC_UNREGULATED_WID 1 +#define MC13783_BATT_DAC_LED_EN_LSH 18 +#define MC13783_BATT_DAC_LED_EN_WID 1 +#define MC13783_BATT_DAC_5K_LSH 19 +#define MC13783_BATT_DAC_5K_WID 1 + +#define BITS_OUT_VOLTAGE 0 +#define LONG_OUT_VOLTAGE 3 +#define BITS_CURRENT_MAIN 3 +#define LONG_CURRENT_MAIN 4 +#define BITS_CURRENT_TRICKLE 7 +#define LONG_CURRENT_TRICKLE 3 +#define BIT_FETOVRD 10 +#define BIT_FETCTRL 11 +#define BIT_RVRSMODE 13 +#define BITS_OVERVOLTAGE 15 +#define LONG_OVERVOLTAGE 2 +#define BIT_UNREGULATED 17 +#define BIT_CHRG_LED 18 +#define BIT_CHRGRAWPDEN 19 + +/* REG_POWXER_CONTROL_0 */ +#define MC13783_BATT_DAC_V_COIN_LSH 20 +#define MC13783_BATT_DAC_V_COIN_WID 3 +#define MC13783_BATT_DAC_COIN_CH_EN_LSH 23 +#define MC13783_BATT_DAC_COIN_CH_EN_WID 1 +#define MC13783_BATT_DAC_COIN_CH_EN_ENABLED 1 +#define MC13783_BATT_DAC_COIN_CH_EN_DISABLED 0 +#define MC13783_BATT_DAC_EOL_CMP_EN_LSH 18 +#define MC13783_BATT_DAC_EOL_CMP_EN_WID 1 +#define MC13783_BATT_DAC_EOL_CMP_EN_ENABLE 1 +#define MC13783_BATT_DAC_EOL_CMP_EN_DISABLE 0 +#define MC13783_BATT_DAC_EOL_SEL_LSH 16 +#define MC13783_BATT_DAC_EOL_SEL_WID 2 + +#define DEF_VALUE 0 + +#define BAT_THRESHOLD_MAX 3 + +#endif /* __PMIC_BATTERY_DEFS_H__ */ diff --git a/drivers/mxc/pmic/mc13783/pmic_convity.c b/drivers/mxc/pmic/mc13783/pmic_convity.c new file mode 100644 index 000000000000..9d89f493a8f2 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_convity.c @@ -0,0 +1,2468 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_convity.c + * @brief Implementation of the PMIC Connectivity driver APIs. + * + * The PMIC connectivity device driver and this API were developed to support + * the external connectivity capabilities of several power management ICs that + * are available from Freescale Semiconductor, Inc. + * + * The following operating modes, in terms of external connectivity, are + * supported: + * + * @verbatim + Operating Mode mc13783 + --------------- ------- + USB (incl. OTG) Yes + RS-232 Yes + CEA-936 Yes + + @endverbatim + * + * @ingroup PMIC_CONNECTIVITY + */ + +#include /* For tasklet interface. */ +#include /* For kernel module interface. */ +#include /* For spinlock interface. */ +#include /* For PMIC ADC driver interface. */ +#include +#include /* For PMIC Connectivity driver interface. */ + +/* + * mc13783 Connectivity API + */ +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_convity_open); +EXPORT_SYMBOL(pmic_convity_close); +EXPORT_SYMBOL(pmic_convity_set_mode); +EXPORT_SYMBOL(pmic_convity_get_mode); +EXPORT_SYMBOL(pmic_convity_reset); +EXPORT_SYMBOL(pmic_convity_set_callback); +EXPORT_SYMBOL(pmic_convity_clear_callback); +EXPORT_SYMBOL(pmic_convity_get_callback); +EXPORT_SYMBOL(pmic_convity_usb_set_speed); +EXPORT_SYMBOL(pmic_convity_usb_get_speed); +EXPORT_SYMBOL(pmic_convity_usb_set_power_source); +EXPORT_SYMBOL(pmic_convity_usb_get_power_source); +EXPORT_SYMBOL(pmic_convity_usb_set_xcvr); +EXPORT_SYMBOL(pmic_convity_usb_get_xcvr); +EXPORT_SYMBOL(pmic_convity_usb_otg_set_dlp_duration); +EXPORT_SYMBOL(pmic_convity_usb_otg_get_dlp_duration); +EXPORT_SYMBOL(pmic_convity_usb_otg_set_config); +EXPORT_SYMBOL(pmic_convity_usb_otg_clear_config); +EXPORT_SYMBOL(pmic_convity_usb_otg_get_config); +EXPORT_SYMBOL(pmic_convity_set_output); +EXPORT_SYMBOL(pmic_convity_rs232_set_config); +EXPORT_SYMBOL(pmic_convity_rs232_get_config); +EXPORT_SYMBOL(pmic_convity_cea936_exit_signal); + +/*! @def SET_BITS + * Set a register field to a given value. + */ + +#define SET_BITS(reg, field, value) (((value) << reg.field.offset) & \ + reg.field.mask) + +/*! @def GET_BITS + * Get the current value of a given register field. + */ +#define GET_BITS(reg, value) (((value) & reg.mask) >> \ + reg.offset) + +/*! + * @brief Define the possible states for a device handle. + * + * This enumeration is used to track the current state of each device handle. + */ +typedef enum { + HANDLE_FREE, /*!< Handle is available for use. */ + HANDLE_IN_USE /*!< Handle is currently in use. */ +} HANDLE_STATE; + +/* + * This structure is used to define a specific hardware register field. + * + * All hardware register fields are defined using an offset to the LSB + * and a mask. The offset is used to right shift a register value before + * applying the mask to actually obtain the value of the field. + */ +typedef struct { + const unsigned char offset; /* Offset of LSB of register field. */ + const unsigned int mask; /* Mask value used to isolate register field. */ +} REGFIELD; + +/*! + * @brief This structure is used to identify the fields in the USBCNTRL_REG_0 hardware register. + * + * This structure lists all of the fields within the USBCNTRL_REG_0 hardware + * register. + */ +typedef struct { + REGFIELD FSENB; /*!< USB Full Speed Enable */ + REGFIELD USB_SUSPEND; /*!< USB Suspend Mode Enable */ + REGFIELD USB_PU; /*!< USB Pullup Enable */ + REGFIELD UDP_PD; /*!< USB Data Plus Pulldown Enable */ + REGFIELD UDM_PD; /*!< USB 150K UDP Pullup Enable */ + REGFIELD DP150K_PU; /*!< USB Pullup/Pulldown Override Enable */ + REGFIELD VBUSPDENB; /*!< USB VBUS Pulldown NMOS Switch Enable */ + REGFIELD CURRENT_LIMIT; /*!< USB Regulator Current Limit Setting-3 bits */ + REGFIELD DLP_SRP; /*!< USB Data Line Pulsing Timer Enable */ + REGFIELD SE0_CONN; /*!< USB Pullup Connect When SE0 Detected */ + REGFIELD USBXCVREN; /*!< USB Transceiver Enabled When INTERFACE_MODE[2:0]=000 and RESETB=high */ + REGFIELD PULLOVR; /*!< 1K5 Pullup and UDP/UDM Pulldown Disable When UTXENB=Low */ + REGFIELD INTERFACE_MODE; /*!< Connectivity Interface Mode Select-3 Bits */ + REGFIELD DATSE0; /*!< USB Single or Differential Mode Select */ + REGFIELD BIDIR; /*!< USB Unidirectional/Bidirectional Transmission */ + REGFIELD USBCNTRL; /*!< USB Mode of Operation controlled By USBEN/SPI Pin */ + REGFIELD IDPD; /*!< USB UID Pulldown Enable */ + REGFIELD IDPULSE; /*!< USB Pulse to Gnd on UID Line Generated */ + REGFIELD IDPUCNTRL; /*!< USB UID Pin pulled high By 5ua Curr Source */ + REGFIELD DMPULSE; /*!< USB Positive pulse on the UDM Line Generated */ +} USBCNTRL_REG_0; + +/*! + * @brief This variable is used to access the USBCNTRL_REG_0 hardware register. + * + * This variable defines how to access all of the fields within the + * USBCNTRL_REG_0 hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const USBCNTRL_REG_0 regUSB0 = { + {0, 0x000001}, /*!< FSENB */ + {1, 0x000002}, /*!< USB_SUSPEND */ + {2, 0x000004}, /*!< USB_PU */ + {3, 0x000008}, /*!< UDP_PD */ + {4, 0x000010}, /*!< UDM_PD */ + {5, 0x000020}, /*!< DP150K_PU */ + {6, 0x000040}, /*!< VBUSPDENB */ + {7, 0x000380}, /*!< CURRENT_LIMIT */ + {10, 0x000400}, /*!< DLP_SRP */ + {11, 0x000800}, /*!< SE0_CONN */ + {12, 0x001000}, /*!< USBXCVREN */ + {13, 0x002000}, /*!< PULLOVR */ + {14, 0x01c000}, /*!< INTERFACE_MODE */ + {17, 0x020000}, /*!< DATSE0 */ + {18, 0x040000}, /*!< BIDIR */ + {19, 0x080000}, /*!< USBCNTRL */ + {20, 0x100000}, /*!< IDPD */ + {21, 0x200000}, /*!< IDPULSE */ + {22, 0x400000}, /*!< IDPUCNTRL */ + {23, 0x800000} /*!< DMPULSE */ + +}; + +/*! + * @brief This structure is used to identify the fields in the USBCNTRL_REG_1 hardware register. + * + * This structure lists all of the fields within the USBCNTRL_REG_1 hardware + * register. + */ +typedef struct { + REGFIELD VUSBIN; /*!< Controls The Input Source For VUSB */ + REGFIELD VUSB; /*!< VUSB Output Voltage Select-High=3.3V Low=2.775V */ + REGFIELD VUSBEN; /*!< VUSB Output Enable- */ + REGFIELD VBUSEN; /*!< VBUS Output Enable- */ + REGFIELD RSPOL; /*!< Low=RS232 TX on UDM, RX on UDP + High= RS232 TX on UDP, RX on UDM */ + REGFIELD RSTRI; /*!< TX Forced To Tristate in RS232 Mode Only */ + REGFIELD ID100kPU; /*!< 100k UID Pullup Enabled */ +} USBCNTRL_REG_1; + +/*! + * @brief This variable is used to access the USBCNTRL_REG_1 hardware register. + * + * This variable defines how to access all of the fields within the + * USBCNTRL_REG_1 hardware register. The initial values consist of the offset + * and mask values needed to access each of the register fields. + */ +static const USBCNTRL_REG_1 regUSB1 = { + {0, 0x000003}, /*!< VUSBIN-2 Bits */ + {2, 0x000004}, /*!< VUSB */ + {3, 0x000008}, /*!< VUSBEN */ + /*{4, 0x000010} *//*!< Reserved */ + {5, 0x000020}, /*!< VBUSEN */ + {6, 0x000040}, /*!< RSPOL */ + {7, 0x000080}, /*!< RSTRI */ + {8, 0x000100} /*!< ID100kPU */ + /*!< 9-23 Unused */ +}; + +/*! Define a mask to access the entire hardware register. */ +static const unsigned int REG_FULLMASK = 0xffffff; + +/*! Define the mc13783 USBCNTRL_REG_0 register power on reset state. */ +static const unsigned int RESET_USBCNTRL_REG_0 = 0x080060; + +/*! Define the mc13783 USBCNTRL_REG_1 register power on reset state. */ +static const unsigned int RESET_USBCNTRL_REG_1 = 0x000006; + +static pmic_event_callback_t eventNotify; + +/*! + * @brief This structure is used to maintain the current device driver state. + * + * This structure maintains the current state of the connectivity driver. This + * includes both the PMIC hardware state as well as the device handle and + * callback states. + */ + +typedef struct { + PMIC_CONVITY_HANDLE handle; /*!< Device handle. */ + HANDLE_STATE handle_state; /*!< Device handle + state. */ + PMIC_CONVITY_MODE mode; /*!< Device mode. */ + PMIC_CONVITY_CALLBACK callback; /*!< Event callback function pointer. */ + PMIC_CONVITY_EVENTS eventMask; /*!< Event mask. */ + PMIC_CONVITY_USB_SPEED usbSpeed; /*!< USB connection + speed. */ + PMIC_CONVITY_USB_MODE usbMode; /*!< USB connection + mode. */ + PMIC_CONVITY_USB_POWER_IN usbPowerIn; /*!< USB transceiver + power source. */ + PMIC_CONVITY_USB_POWER_OUT usbPowerOut; /*!< USB transceiver + power output + level. */ + PMIC_CONVITY_USB_TRANSCEIVER_MODE usbXcvrMode; /*!< USB transceiver + mode. */ + unsigned int usbDlpDuration; /*!< USB Data Line + Pulsing duration. */ + PMIC_CONVITY_USB_OTG_CONFIG usbOtgCfg; /*!< USB OTG + configuration + options. */ + PMIC_CONVITY_RS232_INTERNAL rs232CfgInternal; /*!< RS-232 internal + connections. */ + PMIC_CONVITY_RS232_EXTERNAL rs232CfgExternal; /*!< RS-232 external + connections. */ +} pmic_convity_state_struct; + +/*! + * @brief This structure is used to maintain the current device driver state. + * + * This structure maintains the current state of the driver in USB mode. This + * includes both the PMIC hardware state as well as the device handle and + * callback states. + */ + +typedef struct { + PMIC_CONVITY_HANDLE handle; /*!< Device handle. */ + HANDLE_STATE handle_state; /*!< Device handle + state. */ + PMIC_CONVITY_MODE mode; /*!< Device mode. */ + PMIC_CONVITY_CALLBACK callback; /*!< Event callback function pointer. */ + PMIC_CONVITY_EVENTS eventMask; /*!< Event mask. */ + PMIC_CONVITY_USB_SPEED usbSpeed; /*!< USB connection + speed. */ + PMIC_CONVITY_USB_MODE usbMode; /*!< USB connection + mode. */ + PMIC_CONVITY_USB_POWER_IN usbPowerIn; /*!< USB transceiver + power source. */ + PMIC_CONVITY_USB_POWER_OUT usbPowerOut; /*!< USB transceiver + power output + level. */ + PMIC_CONVITY_USB_TRANSCEIVER_MODE usbXcvrMode; /*!< USB transceiver + mode. */ + unsigned int usbDlpDuration; /*!< USB Data Line + Pulsing duration. */ + PMIC_CONVITY_USB_OTG_CONFIG usbOtgCfg; /*!< USB OTG + configuration + options. */ +} pmic_convity_usb_state; + +/*! + * @brief This structure is used to maintain the current device driver state. + * + * This structure maintains the current state of the driver in RS_232 mode. This + * includes both the PMIC hardware state as well as the device handle and + * callback states. + */ + +typedef struct { + PMIC_CONVITY_HANDLE handle; /*!< Device handle. */ + HANDLE_STATE handle_state; /*!< Device handle + state. */ + PMIC_CONVITY_MODE mode; /*!< Device mode. */ + PMIC_CONVITY_CALLBACK callback; /*!< Event callback function pointer. */ + PMIC_CONVITY_EVENTS eventMask; /*!< Event mask. */ + PMIC_CONVITY_RS232_INTERNAL rs232CfgInternal; /*!< RS-232 internal + connections. */ + PMIC_CONVITY_RS232_EXTERNAL rs232CfgExternal; /*!< RS-232 external + connections. */ +} pmic_convity_rs232_state; + +/*! + * @brief This structure is used to maintain the current device driver state. + * + * This structure maintains the current state of the driver in cea-936 mode. This + * includes both the PMIC hardware state as well as the device handle and + * callback states. + */ + +typedef struct { + PMIC_CONVITY_HANDLE handle; /*!< Device handle. */ + HANDLE_STATE handle_state; /*!< Device handle + state. */ + PMIC_CONVITY_MODE mode; /*!< Device mode. */ + PMIC_CONVITY_CALLBACK callback; /*!< Event callback function pointer. */ + PMIC_CONVITY_EVENTS eventMask; /*!< Event mask. */ + +} pmic_convity_cea936_state; + +/*! + * @brief Identifies the hardware interrupt source. + * + * This enumeration identifies which of the possible hardware interrupt + * sources actually caused the current interrupt handler to be called. + */ +typedef enum { + CORE_EVENT_4V4 = 1, /*!< Detected USB 4.4 V event. */ + CORE_EVENT_2V0 = 2, /*!< Detected USB 2.0 V event. */ + CORE_EVENT_0V8 = 4, /*!< Detected USB 0.8 V event. */ + CORE_EVENT_ABDET = 8 /*!< Detected USB mini A-B connector event. */ +} PMIC_CORE_EVENT; + +/*! + * @brief This structure defines the reset/power on state for the Connectivity driver. + */ +static const pmic_convity_state_struct reset = { + 0, + HANDLE_FREE, + USB, + NULL, + 0, + USB_FULL_SPEED, + USB_PERIPHERAL, + USB_POWER_INTERNAL, + USB_POWER_3V3, + USB_TRANSCEIVER_OFF, + 0, + USB_PULL_OVERRIDE | USB_VBUS_CURRENT_LIMIT_HIGH, + RS232_TX_USE0VM_RX_UDATVP, + RS232_TX_UDM_RX_UDP +}; + +/*! + * @brief This structure maintains the current state of the Connectivity driver. + * + * The initial values must be identical to the reset state defined by the + * #reset variable. + */ +static pmic_convity_usb_state usb = { + 0, + HANDLE_FREE, + USB, + NULL, + 0, + USB_FULL_SPEED, + USB_PERIPHERAL, + USB_POWER_INTERNAL, + USB_POWER_3V3, + USB_TRANSCEIVER_OFF, + 0, + USB_PULL_OVERRIDE | USB_VBUS_CURRENT_LIMIT_HIGH, +}; + +/*! + * @brief This structure maintains the current state of the Connectivity driver. + * + * The initial values must be identical to the reset state defined by the + * #reset variable. + */ +static pmic_convity_rs232_state rs_232 = { + 0, + HANDLE_FREE, + RS232_1, + NULL, + 0, + RS232_TX_USE0VM_RX_UDATVP, + RS232_TX_UDM_RX_UDP +}; + +/*! + * @brief This structure maintains the current state of the Connectivity driver. + * + * The initial values must be identical to the reset state defined by the + * #reset variable. + */ +static pmic_convity_cea936_state cea_936 = { + 0, + HANDLE_FREE, + CEA936_MONO, + NULL, + 0, +}; + +/*! + * @brief This spinlock is used to provide mutual exclusion. + * + * Create a spinlock that can be used to provide mutually exclusive + * read/write access to the globally accessible "convity" data structure + * that was defined above. Mutually exclusive access is required to + * ensure that the convity data structure is consistent at all times + * when possibly accessed by multiple threads of execution (for example, + * while simultaneously handling a user request and an interrupt event). + * + * We need to use a spinlock sometimes because we need to provide mutual + * exclusion while handling a hardware interrupt. + */ +static DEFINE_SPINLOCK(lock); + +/*! + * @brief This mutex is used to provide mutual exclusion. + * + * Create a mutex that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * that were defined above. Mutually exclusive access is required to + * ensure that the Connectivity data structures are consistent at all + * times when possibly accessed by multiple threads of execution. + * + * Note that we use a mutex instead of the spinlock whenever disabling + * interrupts while in the critical section is not required. This helps + * to minimize kernel interrupt handling latency. + */ +static DECLARE_MUTEX(mutex); + +/* Prototype for the connectivity driver tasklet function. */ +static void pmic_convity_tasklet(struct work_struct *work); + +/*! + * @brief Tasklet handler for the connectivity driver. + * + * Declare a tasklet that will do most of the processing for all of the + * connectivity-related interrupt events (USB4.4VI, USB2.0VI, USB0.8VI, + * and AB_DETI). Note that we cannot do all of the required processing + * within the interrupt handler itself because we may need to call the + * ADC driver to measure voltages as well as calling any user-registered + * callback functions. + */ +DECLARE_WORK(convityTasklet, pmic_convity_tasklet); + +/*! + * @brief Global variable to track currently active interrupt events. + * + * This global variable is used to keep track of all of the currently + * active interrupt events for the connectivity driver. Note that access + * to this variable may occur while within an interrupt context and, + * therefore, must be guarded by using a spinlock. + */ +static PMIC_CORE_EVENT eventID; + +/* Prototypes for all static connectivity driver functions. */ +static PMIC_STATUS pmic_convity_set_mode_internal(const PMIC_CONVITY_MODE mode); +static PMIC_STATUS pmic_convity_deregister_all(void); +static void pmic_convity_event_handler(void *param); + +/************************************************************************** + * General setup and configuration functions. + ************************************************************************** + */ + +/*! + * @name General Setup and Configuration Connectivity APIs + * Functions for setting up and configuring the connectivity hardware. + */ +/*@{*/ + +/*! + * Attempt to open and gain exclusive access to the PMIC connectivity + * hardware. An initial operating mode must also be specified. + * + * If the open request is successful, then a numeric handle is returned + * and this handle must be used in all subsequent function calls. The + * same handle must also be used in the pmic_convity_close() call when use + * of the PMIC connectivity hardware is no longer required. + * + * @param handle device handle from open() call + * @param mode initial connectivity operating mode + * + * @return PMIC_SUCCESS if the open request was successful + */ +PMIC_STATUS pmic_convity_open(PMIC_CONVITY_HANDLE * const handle, + const PMIC_CONVITY_MODE mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + if (handle == (PMIC_CONVITY_HANDLE *) NULL) { + /* Do not dereference a NULL pointer. */ + return PMIC_ERROR; + } + + /* We only need to acquire a mutex here because the interrupt handler + * never modifies the device handle or device handle state. Therefore, + * we don't need to worry about conflicts with the interrupt handler + * or the need to execute in an interrupt context. + * + * But we do need a critical section here to avoid problems in case + * multiple calls to pmic_convity_open() are made since we can only + * allow one of them to succeed. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* Check the current device handle state and acquire the handle if + * it is available. + */ + if ((usb.handle_state != HANDLE_FREE) + && (rs_232.handle_state != HANDLE_FREE) + && (cea_936.handle_state != HANDLE_FREE)) { + + /* Cannot open the PMIC connectivity hardware at this time or an invalid + * mode was requested. + */ + *handle = reset.handle; + } else { + + if (mode == USB) { + usb.handle = (PMIC_CONVITY_HANDLE) (&usb); + usb.handle_state = HANDLE_IN_USE; + } else if ((mode == RS232_1) || (mode == RS232_2)) { + rs_232.handle = (PMIC_CONVITY_HANDLE) (&rs_232); + rs_232.handle_state = HANDLE_IN_USE; + } else if ((mode == CEA936_STEREO) || (mode == CEA936_MONO) + || (mode == CEA936_TEST_LEFT) + || (mode == CEA936_TEST_RIGHT)) { + cea_936.handle = (PMIC_CONVITY_HANDLE) (&cea_936); + cea_936.handle_state = HANDLE_IN_USE; + + } + /* Let's begin by acquiring the connectivity device handle. */ + /* Then we can try to set the desired operating mode. */ + rc = pmic_convity_set_mode_internal(mode); + + if (rc == PMIC_SUCCESS) { + /* Successfully set the desired operating mode, now return the + * handle to the caller. + */ + if (mode == USB) { + *handle = usb.handle; + } else if ((mode == RS232_1) || (mode == RS232_2)) { + *handle = rs_232.handle; + } else if ((mode == CEA936_STEREO) + || (mode == CEA936_MONO) + || (mode == CEA936_TEST_LEFT) + || (mode == CEA936_TEST_RIGHT)) { + *handle = cea_936.handle; + } + } else { + /* Failed to set the desired mode, return the handle to an unused + * state. + */ + if (mode == USB) { + usb.handle = reset.handle; + usb.handle_state = reset.handle_state; + } else if ((mode == RS232_1) || (mode == RS232_2)) { + rs_232.handle = reset.handle; + rs_232.handle_state = reset.handle_state; + } else if ((mode == CEA936_STEREO) + || (mode == CEA936_MONO) + || (mode == CEA936_TEST_LEFT) + || (mode == CEA936_TEST_RIGHT)) { + cea_936.handle = reset.handle; + cea_936.handle_state = reset.handle_state; + } + + *handle = reset.handle; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Terminate further access to the PMIC connectivity hardware. Also allows + * another process to call pmic_convity_open() to gain access. + * + * @param handle device handle from open() call + * + * @return PMIC_SUCCESS if the close request was successful + */ +PMIC_STATUS pmic_convity_close(const PMIC_CONVITY_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Begin a critical section here to avoid the possibility of race + * conditions if multiple threads happen to call this function and + * pmic_convity_open() at the same time. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + /* Confirm that the device handle matches the one assigned in the + * pmic_convity_open() call and then close the connection. + */ + if (((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232.handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) { + rc = PMIC_SUCCESS; + + /* Deregister for all existing callbacks if necessary and make sure + * that the event handling settings are consistent following the + * close operation. + */ + if ((usb.callback != reset.callback) + || (rs_232.callback != reset.callback) + || (cea_936.callback != reset.callback)) { + /* Deregister the existing callback function and all registered + * events before we completely close the handle. + */ + rc = pmic_convity_deregister_all(); + if (rc == PMIC_SUCCESS) { + + } else if (usb.eventMask != reset.eventMask) { + /* Having a non-zero eventMask without a callback function being + * defined should never occur but let's just make sure here that + * we keep things consistent. + */ + usb.eventMask = reset.eventMask; + /* Mark the connectivity device handle as being closed. */ + usb.handle = reset.handle; + usb.handle_state = reset.handle_state; + + } else if (rs_232.eventMask != reset.eventMask) { + + rs_232.eventMask = reset.eventMask; + /* Mark the connectivity device handle as being closed. */ + rs_232.handle = reset.handle; + rs_232.handle_state = reset.handle_state; + + } else if (cea_936.eventMask != reset.eventMask) { + cea_936.eventMask = reset.eventMask; + /* Mark the connectivity device handle as being closed. */ + cea_936.handle = reset.handle; + cea_936.handle_state = reset.handle_state; + + } + + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Change the current operating mode of the PMIC connectivity hardware. + * The available connectivity operating modes is hardware dependent and + * consists of one or more of the following: USB (including USB On-the-Go), + * RS-232, and CEA-936. Requesting an operating mode that is not supported + * by the PMIC hardware will return PMIC_NOT_SUPPORTED. + * + * @param handle device handle from + open() call + * @param mode desired operating mode + * + * @return PMIC_SUCCESS if the requested mode was successfully set + */ +PMIC_STATUS pmic_convity_set_mode(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_MODE mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232.handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) { + rc = pmic_convity_set_mode_internal(mode); + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the current operating mode for the PMIC connectivity hardware. + * + * @param handle device handle from open() call + * @param mode the current PMIC connectivity operating mode + * + * @return PMIC_SUCCESS if the requested mode was successfully set + */ +PMIC_STATUS pmic_convity_get_mode(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_MODE * const mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232. + handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) + && (mode != (PMIC_CONVITY_MODE *) NULL)) { + + *mode = usb.mode; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Restore all registers to the initial power-on/reset state. + * + * @param handle device handle from open() call + * + * @return PMIC_SUCCESS if the reset was successful + */ +PMIC_STATUS pmic_convity_reset(const PMIC_CONVITY_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + if (((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232.handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) { + + /* Reset the PMIC Connectivity register to it's power on state. */ + rc = pmic_write_reg(REG_USB, RESET_USBCNTRL_REG_0, + REG_FULLMASK); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + RESET_USBCNTRL_REG_1, REG_FULLMASK); + + if (rc == PMIC_SUCCESS) { + /* Also reset the device driver state data structure. */ + + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Register a callback function that will be used to signal PMIC connectivity + * events. For example, the USB subsystem should register a callback function + * in order to be notified of device connect/disconnect events. Note, however, + * that non-USB events may also be signalled depending upon the PMIC hardware + * capabilities. Therefore, the callback function must be able to properly + * handle all of the possible events if support for non-USB peripherals is + * also to be included. + * + * @param handle device handle from open() call + * @param func a pointer to the callback function + * @param eventMask a mask selecting events to be notified + * + * @return PMIC_SUCCESS if the callback was successful registered + */ +PMIC_STATUS pmic_convity_set_callback(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_CALLBACK func, + const PMIC_CONVITY_EVENTS eventMask) +{ + unsigned long flags; + PMIC_STATUS rc = PMIC_ERROR; + + /* We need to start a critical section here to ensure a consistent state + * in case simultaneous calls to pmic_convity_set_callback() are made. In + * that case, we must serialize the calls to ensure that the "callback" + * and "eventMask" state variables are always consistent. + * + * Note that we don't actually need to acquire the spinlock until later + * when we are finally ready to update the "callback" and "eventMask" + * state variables which are shared with the interrupt handler. + */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + + /* Return an error if either the callback function or event mask + * is not properly defined. + * + * It is also considered an error if a callback function has already + * been defined. If you wish to register for a new set of events, + * then you must first call pmic_convity_clear_callback() to + * deregister the existing callback function and list of events + * before trying to register a new callback function. + */ + if ((func == NULL) || (eventMask == 0) + || (usb.callback != NULL)) { + rc = PMIC_ERROR; + + /* Register for PMIC events from the core protocol driver. */ + } else { + + if ((eventMask & USB_DETECT_4V4_RISE) || + (eventMask & USB_DETECT_4V4_FALL)) { + /* We need to register for the 4.4V interrupt. + EVENT_USBI or EVENT_USB_44VI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_4V4); + rc = pmic_event_subscribe(EVENT_USBI, + eventNotify); + + if (rc != PMIC_SUCCESS) { + return rc; + } + } + + if ((eventMask & USB_DETECT_2V0_RISE) || + (eventMask & USB_DETECT_2V0_FALL)) { + /* We need to register for the 2.0V interrupt. + EVENT_USB_20VI or EVENT_USBI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_2V0); + rc = pmic_event_subscribe(EVENT_USBI, + eventNotify); + + if (rc != PMIC_SUCCESS) { + goto Cleanup_4V4; + } + } + + if ((eventMask & USB_DETECT_0V8_RISE) || + (eventMask & USB_DETECT_0V8_FALL)) { + /* We need to register for the 0.8V interrupt. + EVENT_USB_08VI or EVENT_USBI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_0V8); + rc = pmic_event_subscribe(EVENT_USBI, + eventNotify); + + if (rc != PMIC_SUCCESS) { + goto Cleanup_2V0; + } + } + + if ((eventMask & USB_DETECT_MINI_A) || + (eventMask & USB_DETECT_MINI_B) + || (eventMask & USB_DETECT_NON_USB_ACCESSORY) + || (eventMask & USB_DETECT_FACTORY_MODE)) { + /* We need to register for the AB_DET interrupt. + EVENT_AB_DETI or EVENT_IDI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_ABDET); + rc = pmic_event_subscribe(EVENT_IDI, + eventNotify); + + if (rc != PMIC_SUCCESS) { + goto Cleanup_0V8; + } + } + + /* Use a critical section to maintain a consistent state. */ + spin_lock_irqsave(&lock, flags); + + /* Successfully registered for all events. */ + usb.callback = func; + usb.eventMask = eventMask; + spin_unlock_irqrestore(&lock, flags); + + goto End; + + /* This section unregisters any already registered events if we should + * encounter an error partway through the registration process. Note + * that we don't check the return status here since it is already set + * to PMIC_ERROR before we get here. + */ + Cleanup_0V8: + + if ((eventMask & USB_DETECT_0V8_RISE) || + (eventMask & USB_DETECT_0V8_FALL)) { + /* EVENT_USB_08VI or EVENT_USBI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_0V8); + pmic_event_unsubscribe(EVENT_USBI, eventNotify); + goto End; + } + + Cleanup_2V0: + + if ((eventMask & USB_DETECT_2V0_RISE) || + (eventMask & USB_DETECT_2V0_FALL)) { + /* EVENT_USB_20VI or EVENT_USBI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_2V0); + pmic_event_unsubscribe(EVENT_USBI, eventNotify); + goto End; + } + + Cleanup_4V4: + + if ((eventMask & USB_DETECT_4V4_RISE) || + (eventMask & USB_DETECT_4V4_FALL)) { + /* EVENT_USB_44VI or EVENT_USBI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_4V4); + pmic_event_unsubscribe(EVENT_USBI, eventNotify); + } + } + /* Exit the critical section. */ + + } + End:up(&mutex); + return rc; + +} + +/*! + * Clears the current callback function. If this function returns successfully + * then all future Connectivity events will only be handled by the default + * handler within the Connectivity driver. + * + * @param handle device handle from open() call + * + * @return PMIC_SUCCESS if the callback was successful cleared + */ +PMIC_STATUS pmic_convity_clear_callback(const PMIC_CONVITY_HANDLE handle) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + if (((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232.handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) { + + rc = pmic_convity_deregister_all(); + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the current callback function and event mask. + * + * @param handle device handle from open() call + * @param func the current callback function + * @param eventMask the current event selection mask + * + * @return PMIC_SUCCESS if the callback information was successful + * retrieved + */ +PMIC_STATUS pmic_convity_get_callback(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_CALLBACK * const func, + PMIC_CONVITY_EVENTS * const eventMask) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + if ((((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) || ((handle == rs_232.handle) + && (rs_232. + handle_state == + HANDLE_IN_USE)) + || ((handle == cea_936.handle) + && (cea_936.handle_state == HANDLE_IN_USE))) + && (func != (PMIC_CONVITY_CALLBACK *) NULL) + && (eventMask != (PMIC_CONVITY_EVENTS *) NULL)) { + *func = usb.callback; + *eventMask = usb.eventMask; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + + up(&mutex); + + return rc; +} + +/*@*/ + +/************************************************************************** + * USB-specific configuration and setup functions. + ************************************************************************** + */ + +/*! + * @name USB and USB-OTG Connectivity APIs + * Functions for controlling USB and USB-OTG connectivity. + */ +/*@{*/ + +/*! + * Set the USB transceiver speed. + * + * @param handle device handle from open() call + * @param speed the desired USB transceiver speed + * + * @return PMIC_SUCCESS if the transceiver speed was successfully set + */ +PMIC_STATUS pmic_convity_usb_set_speed(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_SPEED speed) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = SET_BITS(regUSB0, FSENB, 1); + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if (handle == (rs_232.handle || cea_936.handle)) { + return PMIC_PARAMETER_ERROR; + } else { + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE)) { + /* Validate the function parameters and if they are valid, then + * configure the pull-up and pull-down resistors as required for + * the desired operating mode. + */ + if ((speed == USB_HIGH_SPEED)) { + /* + * The USB transceiver also does not support the high speed mode + * (which is also optional under the USB OTG specification). + */ + rc = PMIC_NOT_SUPPORTED; + } else if ((speed != USB_LOW_SPEED) + && (speed != USB_FULL_SPEED)) { + /* Final validity check on the speed parameter. */ + rc = PMIC_ERROR;; + } else { + /* First configure the D+ and D- pull-up/pull-down resistors as + * per the USB OTG specification. + */ + if (speed == USB_FULL_SPEED) { + /* Activate pull-up on D+ and pull-down on D-. */ + reg_value = + SET_BITS(regUSB0, UDM_PD, 1); + } else if (speed == USB_LOW_SPEED) { + /* Activate pull-up on D+ and pull-down on D-. */ + reg_value = SET_BITS(regUSB0, FSENB, 1); + } + + /* Now set the desired USB transceiver speed. Note that + * USB_FULL_SPEED simply requires FSENB=0 (which it + * already is). + */ + + rc = pmic_write_reg(REG_USB, reg_value, + reg_mask); + + if (rc == PMIC_SUCCESS) { + usb.usbSpeed = speed; + } + } + } + } + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the USB transceiver speed. + * + * @param handle device handle from open() call + * @param speed the current USB transceiver speed + * @param mode the current USB transceiver mode + * + * @return PMIC_SUCCESS if the transceiver speed was successfully + * obtained + */ +PMIC_STATUS pmic_convity_usb_get_speed(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_SPEED * const speed, + PMIC_CONVITY_USB_MODE * const mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE) && + (speed != (PMIC_CONVITY_USB_SPEED *) NULL) && + (mode != (PMIC_CONVITY_USB_MODE *) NULL)) { + *speed = usb.usbSpeed; + *mode = usb.usbMode; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * This function enables/disables VUSB and VBUS output. + * This API configures the VUSBEN and VBUSEN bits of USB register + * + * @param handle device handle from open() call + * @param out_type true, for VBUS + * false, for VUSB + * @param out if true, output is enabled + * if false, output is disabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_convity_set_output(const PMIC_CONVITY_HANDLE handle, + bool out_type, bool out) +{ + + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + + if ((out_type == 0) && (out == 1)) { + + reg_value = SET_BITS(regUSB1, VUSBEN, 1); + reg_mask = SET_BITS(regUSB1, VUSBEN, 1); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } else if (out_type == 0 && out == 0) { + reg_mask = SET_BITS(regUSB1, VBUSEN, 1); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } else if (out_type == 1 && out == 1) { + + reg_value = SET_BITS(regUSB1, VBUSEN, 1); + reg_mask = SET_BITS(regUSB1, VBUSEN, 1); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } + + else if (out_type == 1 && out == 0) { + + reg_mask = SET_BITS(regUSB1, VBUSEN, 1); + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } + + /*else { + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value, reg_mask); + } */ + } + + up(&mutex); + + return rc; +} + +/*! + * Set the USB transceiver's power supply configuration. + * + * @param handle device handle from open() call + * @param pwrin USB transceiver regulator input power source + * @param pwrout USB transceiver regulator output power level + * + * @return PMIC_SUCCESS if the USB transceiver's power supply + * configuration was successfully set + */ +PMIC_STATUS pmic_convity_usb_set_power_source(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_POWER_IN + pwrin, + const PMIC_CONVITY_USB_POWER_OUT + pwrout) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + + if (pwrin == USB_POWER_INTERNAL_BOOST) { + reg_value |= SET_BITS(regUSB1, VUSBIN, 0); + reg_mask = SET_BITS(regUSB1, VUSBIN, 1); + } else if (pwrin == USB_POWER_VBUS) { + reg_value |= SET_BITS(regUSB1, VUSBIN, 1); + reg_mask = SET_BITS(regUSB1, VUSBIN, 1); + } + + else if (pwrin == USB_POWER_INTERNAL) { + reg_value |= SET_BITS(regUSB1, VUSBIN, 2); + reg_mask = SET_BITS(regUSB1, VUSBIN, 1); + } + + if (pwrout == USB_POWER_3V3) { + reg_value |= SET_BITS(regUSB1, VUSB, 1); + reg_mask |= SET_BITS(regUSB1, VUSB, 1); + } + + else if (pwrout == USB_POWER_2V775) { + reg_value |= SET_BITS(regUSB1, VUSB, 0); + reg_mask |= SET_BITS(regUSB1, VUSB, 1); + } + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, reg_value, reg_mask); + + if (rc == PMIC_SUCCESS) { + usb.usbPowerIn = pwrin; + usb.usbPowerOut = pwrout; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the USB transceiver's current power supply configuration. + * + * @param handle device handle from open() call + * @param pwrin USB transceiver regulator input power source + * @param pwrout USB transceiver regulator output power level + * + * @return PMIC_SUCCESS if the USB transceiver's power supply + * configuration was successfully retrieved + */ +PMIC_STATUS pmic_convity_usb_get_power_source(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_POWER_IN * + const pwrin, + PMIC_CONVITY_USB_POWER_OUT * + const pwrout) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE) && + (pwrin != (PMIC_CONVITY_USB_POWER_IN *) NULL) && + (pwrout != (PMIC_CONVITY_USB_POWER_OUT *) NULL)) { + *pwrin = usb.usbPowerIn; + *pwrout = usb.usbPowerOut; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Set the USB transceiver's operating mode. + * + * @param handle device handle from open() call + * @param mode desired operating mode + * + * @return PMIC_SUCCESS if the USB transceiver's operating mode + * was successfully configured + */ +PMIC_STATUS pmic_convity_usb_set_xcvr(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_TRANSCEIVER_MODE + mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + + if (mode == USB_TRANSCEIVER_OFF) { + reg_value = SET_BITS(regUSB0, USBXCVREN, 0); + reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1); + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + } + + if (mode == USB_SINGLE_ENDED_UNIDIR) { + reg_value |= + SET_BITS(regUSB0, DATSE0, 1) | SET_BITS(regUSB0, + BIDIR, 0); + reg_mask |= + SET_BITS(regUSB0, USB_SUSPEND, + 1) | SET_BITS(regUSB0, DATSE0, + 1) | SET_BITS(regUSB0, BIDIR, + 1); + } else if (mode == USB_SINGLE_ENDED_BIDIR) { + reg_value |= + SET_BITS(regUSB0, DATSE0, 1) | SET_BITS(regUSB0, + BIDIR, 1); + reg_mask |= + SET_BITS(regUSB0, USB_SUSPEND, + 1) | SET_BITS(regUSB0, DATSE0, + 1) | SET_BITS(regUSB0, BIDIR, + 1); + } else if (mode == USB_DIFFERENTIAL_UNIDIR) { + reg_value |= + SET_BITS(regUSB0, DATSE0, 0) | SET_BITS(regUSB0, + BIDIR, 0); + reg_mask |= + SET_BITS(regUSB0, USB_SUSPEND, + 1) | SET_BITS(regUSB0, DATSE0, + 1) | SET_BITS(regUSB0, BIDIR, + 1); + } else if (mode == USB_DIFFERENTIAL_BIDIR) { + reg_value |= + SET_BITS(regUSB0, DATSE0, 0) | SET_BITS(regUSB0, + BIDIR, 1); + reg_mask |= + SET_BITS(regUSB0, USB_SUSPEND, + 1) | SET_BITS(regUSB0, DATSE0, + 1) | SET_BITS(regUSB0, BIDIR, + 1); + } + + if (mode == USB_SUSPEND_ON) { + reg_value |= SET_BITS(regUSB0, USB_SUSPEND, 1); + reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1); + } else if (mode == USB_SUSPEND_OFF) { + reg_value |= SET_BITS(regUSB0, USB_SUSPEND, 0); + reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1); + } + + if (mode == USB_OTG_SRP_DLP_START) { + reg_value |= SET_BITS(regUSB0, USB_PU, 0); + reg_mask |= SET_BITS(regUSB0, USB_SUSPEND, 1); + } else if (mode == USB_OTG_SRP_DLP_STOP) { + reg_value &= SET_BITS(regUSB0, USB_PU, 1); + reg_mask |= SET_BITS(regUSB0, USB_PU, 1); + } + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + if (rc == PMIC_SUCCESS) { + usb.usbXcvrMode = mode; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the USB transceiver's current operating mode. + * + * @param handle device handle from open() call + * @param mode current operating mode + * + * @return PMIC_SUCCESS if the USB transceiver's operating mode + * was successfully retrieved + */ +PMIC_STATUS pmic_convity_usb_get_xcvr(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_TRANSCEIVER_MODE * + const mode) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE) && + (mode != (PMIC_CONVITY_USB_TRANSCEIVER_MODE *) NULL)) { + *mode = usb.usbXcvrMode; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Set the Data Line Pulse duration (in milliseconds) for the USB OTG + * Session Request Protocol. + * + * For mc13783, this feature is not supported.So return PMIC_NOT_SUPPORTED + * + * @param handle device handle from open() call + * @param duration the data line pulse duration (ms) + * + * @return PMIC_SUCCESS if the pulse duration was successfully set + */ +PMIC_STATUS pmic_convity_usb_otg_set_dlp_duration(const PMIC_CONVITY_HANDLE + handle, + const unsigned int duration) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + + /* The setting of the dlp duration is not supported by the mc13783 PMIC hardware. */ + + /* No critical section is required. */ + + if ((handle != usb.handle) + || (usb.handle_state != HANDLE_IN_USE)) { + /* Must return error indication for invalid handle parameter to be + * consistent with other APIs. + */ + rc = PMIC_ERROR; + } + + return rc; +} + +/*! + * Get the current Data Line Pulse duration (in milliseconds) for the USB + * OTG Session Request Protocol. + * + * @param handle device handle from open() call + * @param duration the data line pulse duration (ms) + * + * @return PMIC_SUCCESS if the pulse duration was successfully obtained + */ +PMIC_STATUS pmic_convity_usb_otg_get_dlp_duration(const PMIC_CONVITY_HANDLE + handle, + unsigned int *const duration) +{ + PMIC_STATUS rc = PMIC_NOT_SUPPORTED; + + /* The setting of dlp duration is not supported by the mc13783 PMIC hardware. */ + + /* No critical section is required. */ + + if ((handle != usb.handle) + || (usb.handle_state != HANDLE_IN_USE)) { + /* Must return error indication for invalid handle parameter to be + * consistent with other APIs. + */ + rc = PMIC_ERROR; + } + + return rc; +} + +/*! + * Set the USB On-The-Go (OTG) configuration. + * + * @param handle device handle from open() call + * @param cfg desired USB OTG configuration + * + * @return PMIC_SUCCESS if the OTG configuration was successfully set + */ +PMIC_STATUS pmic_convity_usb_otg_set_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_OTG_CONFIG + cfg) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + if (cfg & USB_OTG_SE0CONN) { + reg_value = SET_BITS(regUSB0, SE0_CONN, 1); + reg_mask = SET_BITS(regUSB0, SE0_CONN, 1); + } + if (cfg & USBXCVREN) { + reg_value |= SET_BITS(regUSB0, USBXCVREN, 1); + reg_mask |= SET_BITS(regUSB0, USBXCVREN, 1); + } + + if (cfg & USB_OTG_DLP_SRP) { + reg_value |= SET_BITS(regUSB0, DLP_SRP, 1); + reg_mask |= SET_BITS(regUSB0, DLP_SRP, 1); + } + + if (cfg & USB_PULL_OVERRIDE) { + reg_value |= SET_BITS(regUSB0, PULLOVR, 1); + reg_mask |= SET_BITS(regUSB0, PULLOVR, 1); + } + + if (cfg & USB_PU) { + reg_value |= SET_BITS(regUSB0, USB_PU, 1); + reg_mask |= SET_BITS(regUSB0, USB_PU, 1); + } + + if (cfg & USB_UDM_PD) { + reg_value |= SET_BITS(regUSB0, UDM_PD, 1); + reg_mask |= SET_BITS(regUSB0, UDM_PD, 1); + } + + if (cfg & USB_UDP_PD) { + reg_value |= SET_BITS(regUSB0, UDP_PD, 1); + reg_mask |= SET_BITS(regUSB0, UDP_PD, 1); + } + + if (cfg & USB_DP150K_PU) { + reg_value |= SET_BITS(regUSB0, DP150K_PU, 1); + reg_mask |= SET_BITS(regUSB0, DP150K_PU, 1); + } + + if (cfg & USB_USBCNTRL) { + reg_value |= SET_BITS(regUSB0, USBCNTRL, 1); + reg_mask |= SET_BITS(regUSB0, USBCNTRL, 1); + } + + if (cfg & USB_VBUS_CURRENT_LIMIT_HIGH) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 0); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 1); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 2); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 3); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 4); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 5); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 6); + } + if (cfg & USB_VBUS_CURRENT_LIMIT_LOW) { + reg_value |= SET_BITS(regUSB0, CURRENT_LIMIT, 7); + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 7); + } + + if (cfg & USB_VBUS_PULLDOWN) { + reg_value |= SET_BITS(regUSB0, VBUSPDENB, 1); + reg_mask |= SET_BITS(regUSB0, VBUSPDENB, 1); + } + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + if (rc == PMIC_SUCCESS) { + if ((cfg & USB_VBUS_CURRENT_LIMIT_HIGH) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS)) { + /* Make sure that the VBUS current limit state is + * correctly set to either USB_VBUS_CURRENT_LIMIT_HIGH + * or USB_VBUS_CURRENT_LIMIT_LOW but never both at the + * same time. + * + * We guarantee this by first clearing both of the + * status bits and then resetting the correct one. + */ + usb.usbOtgCfg &= + ~(USB_VBUS_CURRENT_LIMIT_HIGH | + USB_VBUS_CURRENT_LIMIT_LOW | + USB_VBUS_CURRENT_LIMIT_LOW_10MS | + USB_VBUS_CURRENT_LIMIT_LOW_20MS | + USB_VBUS_CURRENT_LIMIT_LOW_30MS | + USB_VBUS_CURRENT_LIMIT_LOW_40MS | + USB_VBUS_CURRENT_LIMIT_LOW_50MS | + USB_VBUS_CURRENT_LIMIT_LOW_60MS); + } + + usb.usbOtgCfg |= cfg; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Clears the USB On-The-Go (OTG) configuration. Multiple configuration settings + * may be OR'd together in a single call. However, selecting conflicting + * settings (e.g., multiple VBUS current limits) will result in undefined + * behavior. + * + * @param handle Device handle from open() call. + * @param cfg USB OTG configuration settings to be cleared. + * + * @retval PMIC_SUCCESS If the OTG configuration was successfully + * cleared. + * @retval PMIC_PARAMETER_ERROR If the handle is invalid. + * @retval PMIC_NOT_SUPPORTED If the desired USB OTG configuration is + * not supported by the PMIC hardware. + */ +PMIC_STATUS pmic_convity_usb_otg_clear_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_USB_OTG_CONFIG + cfg) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = 0; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && (usb.handle_state == HANDLE_IN_USE)) { + /* if ((cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) || + (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS)) + { + rc = PMIC_NOT_SUPPORTED; + } */ + + if (cfg & USB_OTG_SE0CONN) { + reg_mask = SET_BITS(regUSB0, SE0_CONN, 1); + } + + if (cfg & USB_OTG_DLP_SRP) { + reg_mask |= SET_BITS(regUSB0, DLP_SRP, 1); + } + + if (cfg & USB_DP150K_PU) { + reg_mask |= SET_BITS(regUSB0, DP150K_PU, 1); + } + + if (cfg & USB_PULL_OVERRIDE) { + reg_mask |= SET_BITS(regUSB0, PULLOVR, 1); + } + + if (cfg & USB_PU) { + + reg_mask |= SET_BITS(regUSB0, USB_PU, 1); + } + + if (cfg & USB_UDM_PD) { + + reg_mask |= SET_BITS(regUSB0, UDM_PD, 1); + } + + if (cfg & USB_UDP_PD) { + + reg_mask |= SET_BITS(regUSB0, UDP_PD, 1); + } + + if (cfg & USB_USBCNTRL) { + reg_mask |= SET_BITS(regUSB0, USBCNTRL, 1); + } + + if (cfg & USB_VBUS_CURRENT_LIMIT_HIGH) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 0); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_10MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 1); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_20MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 2); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_30MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 3); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_40MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 4); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_50MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 5); + } else if (cfg & USB_VBUS_CURRENT_LIMIT_LOW_60MS) { + reg_mask |= SET_BITS(regUSB0, CURRENT_LIMIT, 6); + } + + if (cfg & USB_VBUS_PULLDOWN) { + reg_mask |= SET_BITS(regUSB0, VBUSPDENB, 1); + } + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + if (rc == PMIC_SUCCESS) { + usb.usbOtgCfg &= ~cfg; + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the current USB On-The-Go (OTG) configuration. + * + * @param handle device handle from open() call + * @param cfg the current USB OTG configuration + * + * @return PMIC_SUCCESS if the OTG configuration was successfully + * retrieved + */ +PMIC_STATUS pmic_convity_usb_otg_get_config(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_USB_OTG_CONFIG * + const cfg) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == usb.handle) && + (usb.handle_state == HANDLE_IN_USE) && + (cfg != (PMIC_CONVITY_USB_OTG_CONFIG *) NULL)) { + *cfg = usb.usbOtgCfg; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*@}*/ + +/************************************************************************** + * RS-232-specific configuration and setup functions. + ************************************************************************** + */ + +/*! + * @name RS-232 Serial Connectivity APIs + * Functions for controlling RS-232 serial connectivity. + */ +/*@{*/ + +/*! + * Set the connectivity interface to the selected RS-232 operating + * configuration. Note that the RS-232 operating mode will be automatically + * overridden if the USB_EN is asserted at any time (e.g., when a USB device + * is attached). However, we will also automatically return to the RS-232 + * mode once the USB device is detached. + * + * @param handle device handle from open() call + * @param cfgInternal RS-232 transceiver internal connections + * @param cfgExternal RS-232 transceiver external connections + * + * @return PMIC_SUCCESS if the requested mode was set + */ +PMIC_STATUS pmic_convity_rs232_set_config(const PMIC_CONVITY_HANDLE handle, + const PMIC_CONVITY_RS232_INTERNAL + cfgInternal, + const PMIC_CONVITY_RS232_EXTERNAL + cfgExternal) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value0 = 0, reg_value1 = 0; + unsigned int reg_mask = SET_BITS(regUSB1, RSPOL, 1); + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == rs_232.handle) && (rs_232.handle_state == HANDLE_IN_USE)) { + rc = PMIC_SUCCESS; + + /* Validate the calling parameters. */ + /*if ((cfgInternal != RS232_TX_USE0VM_RX_UDATVP) && + (cfgInternal != RS232_TX_RX_INTERNAL_DEFAULT) && (cfgInternal != RS232_TX_UDATVP_RX_URXVM)) + { + + rc = PMIC_NOT_SUPPORTED; + } */ + if (cfgInternal == RS232_TX_USE0VM_RX_UDATVP) { + + reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 1); + + } else if (cfgInternal == RS232_TX_RX_INTERNAL_DEFAULT) { + + reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 1); + reg_mask |= SET_BITS(regUSB1, RSPOL, 1); + + } else if (cfgInternal == RS232_TX_UDATVP_RX_URXVM) { + + reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 2); + reg_value1 |= SET_BITS(regUSB1, RSPOL, 1); + + } else if ((cfgExternal == RS232_TX_UDM_RX_UDP) || + (cfgExternal == RS232_TX_RX_EXTERNAL_DEFAULT)) { + /* Configure for TX on D+ and RX on D-. */ + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 1); + reg_value1 |= SET_BITS(regUSB1, RSPOL, 0); + } else if (cfgExternal != RS232_TX_UDM_RX_UDP) { + /* Any other RS-232 configuration is an error. */ + rc = PMIC_ERROR; + } + + if (rc == PMIC_SUCCESS) { + /* Configure for TX on D- and RX on D+. */ + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask); + + rc = pmic_write_reg(REG_CHARGE_USB_SPARE, + reg_value1, reg_mask); + + if (rc == PMIC_SUCCESS) { + rs_232.rs232CfgInternal = cfgInternal; + rs_232.rs232CfgExternal = cfgExternal; + } + } + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*! + * Get the connectivity interface's current RS-232 operating configuration. + * + * @param handle device handle from open() call + * @param cfgInternal RS-232 transceiver internal connections + * @param cfgExternal RS-232 transceiver external connections + * + * @return PMIC_SUCCESS if the requested mode was retrieved + */ +PMIC_STATUS pmic_convity_rs232_get_config(const PMIC_CONVITY_HANDLE handle, + PMIC_CONVITY_RS232_INTERNAL * + const cfgInternal, + PMIC_CONVITY_RS232_EXTERNAL * + const cfgExternal) +{ + PMIC_STATUS rc = PMIC_ERROR; + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle == rs_232.handle) && + (rs_232.handle_state == HANDLE_IN_USE) && + (cfgInternal != (PMIC_CONVITY_RS232_INTERNAL *) NULL) && + (cfgExternal != (PMIC_CONVITY_RS232_EXTERNAL *) NULL)) { + *cfgInternal = rs_232.rs232CfgInternal; + *cfgExternal = rs_232.rs232CfgExternal; + + rc = PMIC_SUCCESS; + } + + /* Exit the critical section. */ + up(&mutex); + + return rc; +} + +/*@}*/ + +/************************************************************************** + * CEA-936-specific configuration and setup functions. + ************************************************************************** + */ + +/*! + * @name CEA-936 Connectivity APIs + * Functions for controlling CEA-936 connectivity. + */ +/*@{*/ + +/*! + * Signal the attached device to exit the current CEA-936 operating mode. + * Returns an error if the current operating mode is not CEA-936. + * + * @param handle device handle from open() call + * @param signal type of exit signal to be sent + * + * @return PMIC_SUCCESS if exit signal was sent + */ +PMIC_STATUS pmic_convity_cea936_exit_signal(const PMIC_CONVITY_HANDLE handle, + const + PMIC_CONVITY_CEA936_EXIT_SIGNAL + signal) +{ + PMIC_STATUS rc = PMIC_ERROR; + unsigned int reg_value = 0; + unsigned int reg_mask = + SET_BITS(regUSB0, IDPD, 1) | SET_BITS(regUSB0, IDPULSE, 1); + + /* Use a critical section to maintain a consistent state. */ + if (down_interruptible(&mutex)) + return PMIC_SYSTEM_ERROR_EINTR; + + if ((handle != cea_936.handle) + || (cea_936.handle_state != HANDLE_IN_USE)) { + /* Must return error indication for invalid handle parameter to be + * consistent with other APIs. + */ + rc = PMIC_ERROR; + } else if (signal == CEA936_UID_PULLDOWN_6MS) { + reg_value = + SET_BITS(regUSB0, IDPULSE, 0) | SET_BITS(regUSB0, IDPD, 0); + } else if (signal == CEA936_UID_PULLDOWN_6MS) { + reg_value = SET_BITS(regUSB0, IDPULSE, 1); + } else if (signal == CEA936_UID_PULLDOWN) { + reg_value = SET_BITS(regUSB0, IDPD, 1); + } else if (signal == CEA936_UDMPULSE) { + reg_value = SET_BITS(regUSB0, DMPULSE, 1); + } + + rc = pmic_write_reg(REG_USB, reg_value, reg_mask); + + up(&mutex); + + return rc; +} + +/*@}*/ + +/************************************************************************** + * Static functions. + ************************************************************************** + */ + +/*! + * @name Connectivity Driver Internal Support Functions + * These non-exported internal functions are used to support the functionality + * of the exported connectivity APIs. + */ +/*@{*/ + +/*! + * This internal helper function sets the desired operating mode (either USB + * OTG or RS-232). It must be called with the mutex already acquired. + * + * @param mode the desired operating mode (USB or RS232) + * + * @return PMIC_SUCCESS if the desired operating mode was set + * @return PMIC_NOT_SUPPORTED if the desired operating mode is invalid + */ +static PMIC_STATUS pmic_convity_set_mode_internal(const PMIC_CONVITY_MODE mode) +{ + unsigned int reg_value0 = 0, reg_value1 = 0; + unsigned int reg_mask0 = 0, reg_mask1 = 0; + + PMIC_STATUS rc = PMIC_SUCCESS; + + switch (mode) { + case USB: + /* For the USB mode, we start by tri-stating the USB bus (by + * setting VBUSEN = 0) until a device is connected (i.e., + * until we receive a 4.4V rising edge event). All pull-up + * and pull-down resistors are also disabled until a USB + * device is actually connected and we have determined which + * device is the host and the desired USB bus speed. + * + * Also tri-state the RS-232 buffers (by setting RSTRI = 1). + * This prevents the hardware from automatically returning to + * the RS-232 mode when the USB device is detached. + */ + + reg_value0 = SET_BITS(regUSB0, INTERFACE_MODE, 0); + reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7); + + /*reg_value1 = SET_BITS(regUSB1, RSTRI, 1); */ + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + /* if (rc == PMIC_SUCCESS) { + CHECK_ERROR(pmic_write_reg + (REG_CHARGE_USB_SPARE, + reg_value1, reg_mask1)); + } */ + + break; + + case RS232_1: + /* For the RS-232 mode, we tri-state the USB bus (by setting + * VBUSEN = 0) and enable the RS-232 transceiver (by setting + * RS232ENB = 0). + * + * Note that even in the RS-232 mode, if a USB device is + * plugged in, we will receive a 4.4V rising edge event which + * will automatically disable the RS-232 transceiver and + * tri-state the RS-232 buffers. This allows us to temporarily + * switch over to USB mode while the USB device is attached. + * The RS-232 transceiver and buffers will be automatically + * re-enabled when the USB device is detached. + */ + + /* Explicitly disconnect all of the USB pull-down resistors + * and the VUSB power regulator here just to be safe. + * + * But we do connect the internal pull-up resistor on USB_D+ + * to avoid having an extra load on the USB_D+ line when in + * RS-232 mode. + */ + + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 1) | + SET_BITS(regUSB0, VBUSPDENB, 1) | + SET_BITS(regUSB0, USB_PU, 1); + reg_mask0 = + SET_BITS(regUSB0, INTERFACE_MODE, 7) | SET_BITS(regUSB0, + VBUSPDENB, + 1) | + SET_BITS(regUSB0, USB_PU, 1); + + reg_value1 = SET_BITS(regUSB1, RSPOL, 0); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + + if (rc == PMIC_SUCCESS) { + CHECK_ERROR(pmic_write_reg + (REG_CHARGE_USB_SPARE, + reg_value1, reg_mask1)); + } + break; + + case RS232_2: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 2) | + SET_BITS(regUSB0, VBUSPDENB, 1) | + SET_BITS(regUSB0, USB_PU, 1); + reg_mask0 = + SET_BITS(regUSB0, INTERFACE_MODE, 7) | SET_BITS(regUSB0, + VBUSPDENB, + 1) | + SET_BITS(regUSB0, USB_PU, 1); + + reg_value1 = SET_BITS(regUSB1, RSPOL, 1); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + + if (rc == PMIC_SUCCESS) { + CHECK_ERROR(pmic_write_reg + (REG_CHARGE_USB_SPARE, + reg_value1, reg_mask1)); + } + break; + + case CEA936_MONO: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 4); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + break; + + case CEA936_STEREO: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 5); + reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + break; + + case CEA936_TEST_RIGHT: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 6); + reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + break; + + case CEA936_TEST_LEFT: + reg_value0 |= SET_BITS(regUSB0, INTERFACE_MODE, 7); + reg_mask0 = SET_BITS(regUSB0, INTERFACE_MODE, 7); + + rc = pmic_write_reg(REG_USB, reg_value0, reg_mask0); + break; + + default: + rc = PMIC_NOT_SUPPORTED; + } + + if (rc == PMIC_SUCCESS) { + if (mode == USB) { + usb.mode = mode; + } else if ((mode == RS232_1) || (mode == RS232_1)) { + rs_232.mode = mode; + } else if ((mode == CEA936_MONO) || (mode == CEA936_STEREO) || + (mode == CEA936_TEST_RIGHT) + || (mode == CEA936_TEST_LEFT)) { + cea_936.mode = mode; + } + } + + return rc; +} + +/*! + * This internal helper function deregisters all of the currently registered + * callback events. It must be called with the mutual exclusion spinlock + * already acquired. + * + * We've defined the event and callback deregistration code here as a separate + * function because it can be called by either the pmic_convity_close() or the + * pmic_convity_clear_callback() APIs. We also wanted to avoid any possible + * issues with having the same thread calling spin_lock_irq() twice. + * + * Note that the mutex must have already been acquired. We will also acquire + * the spinlock here to avoid any possible race conditions with the interrupt + * handler. + * + * @return PMIC_SUCCESS if all of the callback events were cleared + */ +static PMIC_STATUS pmic_convity_deregister_all(void) +{ + unsigned long flags; + PMIC_STATUS rc = PMIC_SUCCESS; + + /* Deregister each of the PMIC events that we had previously + * registered for by using pmic_event_subscribe(). + */ + + if ((usb.eventMask & USB_DETECT_MINI_A) || + (usb.eventMask & USB_DETECT_MINI_B) || + (usb.eventMask & USB_DETECT_NON_USB_ACCESSORY) || + (usb.eventMask & USB_DETECT_FACTORY_MODE)) { + /* EVENT_AB_DETI or EVENT_IDI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_ABDET); + + if (pmic_event_unsubscribe(EVENT_IDI, eventNotify) == + PMIC_SUCCESS) { + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + + spin_lock_irqsave(&lock, flags); + + usb.eventMask &= ~(USB_DETECT_MINI_A | + USB_DETECT_MINI_B | + USB_DETECT_NON_USB_ACCESSORY | + USB_DETECT_FACTORY_MODE); + + spin_unlock_irqrestore(&lock, flags); + } else { + pr_debug + ("%s: pmic_event_unsubscribe() for EVENT_AB_DETI failed\n", + __FILE__); + rc = PMIC_ERROR; + } + } + + else if ((usb.eventMask & USB_DETECT_0V8_RISE) || + (usb.eventMask & USB_DETECT_0V8_FALL)) { + /* EVENT_USB_08VI or EVENT_USBI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_0V8); + if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) == + PMIC_SUCCESS) { + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + spin_lock_irqsave(&lock, flags); + + usb.eventMask &= ~(USB_DETECT_0V8_RISE | + USB_DETECT_0V8_FALL); + + spin_unlock_irqrestore(&lock, flags); + } else { + pr_debug + ("%s: pmic_event_unsubscribe() for EVENT_USB_08VI failed\n", + __FILE__); + rc = PMIC_ERROR; + } + + } + + else if ((usb.eventMask & USB_DETECT_2V0_RISE) || + (usb.eventMask & USB_DETECT_2V0_FALL)) { + /* EVENT_USB_20VI or EVENT_USBI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_2V0); + if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) == + PMIC_SUCCESS) { + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + spin_lock_irqsave(&lock, flags); + + usb.eventMask &= ~(USB_DETECT_2V0_RISE | + USB_DETECT_2V0_FALL); + + spin_unlock_irqrestore(&lock, flags); + } else { + pr_debug + ("%s: pmic_event_unsubscribe() for EVENT_USB_20VI failed\n", + __FILE__); + rc = PMIC_ERROR; + } + } + + else if ((usb.eventMask & USB_DETECT_4V4_RISE) || + (usb.eventMask & USB_DETECT_4V4_FALL)) { + + /* EVENT_USB_44VI or EVENT_USBI */ + eventNotify.func = pmic_convity_event_handler; + eventNotify.param = (void *)(CORE_EVENT_4V4); + + if (pmic_event_unsubscribe(EVENT_USBI, eventNotify) == + PMIC_SUCCESS) { + + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + spin_lock_irqsave(&lock, flags); + + usb.eventMask &= ~(USB_DETECT_4V4_RISE | + USB_DETECT_4V4_FALL); + + spin_unlock_irqrestore(&lock, flags); + } else { + pr_debug + ("%s: pmic_event_unsubscribe() for EVENT_USB_44VI failed\n", + __FILE__); + rc = PMIC_ERROR; + } + } + + if (rc == PMIC_SUCCESS) { + /* Also acquire the spinlock here to avoid any possible race + * conditions with the interrupt handler. + */ + spin_lock_irqsave(&lock, flags); + + /* Restore the initial reset values for the callback function + * and event mask parameters. This should be NULL and zero, + * respectively. + * + * Note that we wait until the end here to fully reset everything + * just in case some of the pmic_event_unsubscribe() calls above + * failed for some reason (which normally shouldn't happen). + */ + usb.callback = reset.callback; + usb.eventMask = reset.eventMask; + + spin_unlock_irqrestore(&lock, flags); + } + return rc; +} + +/*! + * This is the default event handler for all connectivity-related events + * and hardware interrupts. + * + * @param param event ID + */ +static void pmic_convity_event_handler(void *param) +{ + unsigned long flags; + + /* Update the global list of active interrupt events. */ + spin_lock_irqsave(&lock, flags); + eventID |= (PMIC_CORE_EVENT) (param); + spin_unlock_irqrestore(&lock, flags); + + /* Schedule the tasklet to be run as soon as it is convenient to do so. */ + schedule_work(&convityTasklet); +} + +/*! + * @brief This is the connectivity driver tasklet that handles interrupt events. + * + * This function is scheduled by the connectivity driver interrupt handler + * pmic_convity_event_handler() to complete the processing of all of the + * connectivity-related interrupt events. + * + * Since this tasklet runs with interrupts enabled, we can safely call + * the ADC driver, if necessary, to properly detect the type of USB connection + * that is being made and to call any user-registered callback functions. + * + * @param arg The parameter that was provided above in + * the DECLARE_TASKLET() macro (unused). + */ +static void pmic_convity_tasklet(struct work_struct *work) +{ + + PMIC_CONVITY_EVENTS activeEvents = 0; + unsigned long flags = 0; + + /* Check the interrupt sense bits to determine exactly what + * event just occurred. + */ + if (eventID & CORE_EVENT_4V4) { + spin_lock_irqsave(&lock, flags); + eventID &= ~CORE_EVENT_4V4; + spin_unlock_irqrestore(&lock, flags); + + activeEvents |= pmic_check_sensor(SENSE_USB4V4S) ? + USB_DETECT_4V4_RISE : USB_DETECT_4V4_FALL; + + if (activeEvents & ~usb.eventMask) { + /* The default handler for 4.4 V rising/falling edge detection + * is to simply ignore the event. + */ + ; + } + } + if (eventID & CORE_EVENT_2V0) { + spin_lock_irqsave(&lock, flags); + eventID &= ~CORE_EVENT_2V0; + spin_unlock_irqrestore(&lock, flags); + + activeEvents |= pmic_check_sensor(SENSE_USB2V0S) ? + USB_DETECT_2V0_RISE : USB_DETECT_2V0_FALL; + if (activeEvents & ~usb.eventMask) { + /* The default handler for 2.0 V rising/falling edge detection + * is to simply ignore the event. + */ + ; + } + } + if (eventID & CORE_EVENT_0V8) { + spin_lock_irqsave(&lock, flags); + eventID &= ~CORE_EVENT_0V8; + spin_unlock_irqrestore(&lock, flags); + + activeEvents |= pmic_check_sensor(SENSE_USB0V8S) ? + USB_DETECT_0V8_RISE : USB_DETECT_0V8_FALL; + + if (activeEvents & ~usb.eventMask) { + /* The default handler for 0.8 V rising/falling edge detection + * is to simply ignore the event. + */ + ; + } + } + if (eventID & CORE_EVENT_ABDET) { + spin_lock_irqsave(&lock, flags); + eventID &= ~CORE_EVENT_ABDET; + spin_unlock_irqrestore(&lock, flags); + + activeEvents |= pmic_check_sensor(SENSE_ID_GNDS) ? + USB_DETECT_MINI_A : 0; + + activeEvents |= pmic_check_sensor(SENSE_ID_FLOATS) ? + USB_DETECT_MINI_B : 0; + } + + /* Begin a critical section here so that we don't register/deregister + * for events or open/close the connectivity driver while the existing + * event handler (if it is currently defined) is in the middle of handling + * the current event. + */ + spin_lock_irqsave(&lock, flags); + + /* Finally, call the user-defined callback function if required. */ + if ((usb.handle_state == HANDLE_IN_USE) && + (usb.callback != NULL) && (activeEvents & usb.eventMask)) { + (*usb.callback) (activeEvents); + } + + spin_unlock_irqrestore(&lock, flags); +} + +/*@}*/ + +/************************************************************************** + * Module initialization and termination functions. + * + * Note that if this code is compiled into the kernel, then the + * module_init() function will be called within the device_initcall() + * group. + ************************************************************************** + */ + +/*! + * @name Connectivity Driver Loading/Unloading Functions + * These non-exported internal functions are used to support the connectivity + * device driver initialization and de-initialization operations. + */ +/*@{*/ + +/*! + * @brief This is the connectivity device driver initialization function. + * + * This function is called by the kernel when this device driver is first + * loaded. + */ +static int __init mc13783_pmic_convity_init(void) +{ + printk(KERN_INFO "PMIC Connectivity driver loading..\n"); + + return 0; +} + +/*! + * @brief This is the Connectivity device driver de-initialization function. + * + * This function is called by the kernel when this device driver is about + * to be unloaded. + */ +static void __exit mc13783_pmic_convity_exit(void) +{ + printk(KERN_INFO "PMIC Connectivity driver unloading\n"); + + /* Close the device handle if it is still open. This will also + * deregister any callbacks that may still be active. + */ + if (usb.handle_state == HANDLE_IN_USE) { + pmic_convity_close(usb.handle); + } else if (usb.handle_state == HANDLE_IN_USE) { + pmic_convity_close(rs_232.handle); + } else if (usb.handle_state == HANDLE_IN_USE) { + pmic_convity_close(cea_936.handle); + } + + /* Reset the PMIC Connectivity register to it's power on state. + * We should do this when unloading the module so that we don't + * leave the hardware in a state which could cause problems when + * no device driver is loaded. + */ + pmic_write_reg(REG_USB, RESET_USBCNTRL_REG_0, REG_FULLMASK); + pmic_write_reg(REG_CHARGE_USB_SPARE, RESET_USBCNTRL_REG_1, + REG_FULLMASK); + /* Note that there is no need to reset the "convity" device driver + * state structure to the reset state since we are in the final + * stage of unloading the device driver. The device driver state + * structure will be automatically and properly reinitialized if + * this device driver is reloaded. + */ +} + +/*@}*/ + +/* + * Module entry points and description information. + */ + +module_init(mc13783_pmic_convity_init); +module_exit(mc13783_pmic_convity_exit); + +MODULE_DESCRIPTION("mc13783 Connectivity device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13783/pmic_light.c b/drivers/mxc/pmic/mc13783/pmic_light.c new file mode 100644 index 000000000000..46c13aab2a78 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_light.c @@ -0,0 +1,2764 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_light.c + * @brief This is the main file of PMIC(mc13783) Light and Backlight driver. + * + * @ingroup PMIC_LIGHT + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include "pmic_light_defs.h" + +#define NB_LIGHT_REG 6 + +static int pmic_light_major; + +/*! + * Number of users waiting in suspendq + */ +static int swait; + +/*! + * To indicate whether any of the light devices are suspending + */ +static int suspend_flag; + +/*! + * The suspendq is used to block application calls + */ +static wait_queue_head_t suspendq; + +static struct class *pmic_light_class; + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_bklit_tcled_master_enable); +EXPORT_SYMBOL(pmic_bklit_tcled_master_disable); +EXPORT_SYMBOL(pmic_bklit_master_enable); +EXPORT_SYMBOL(pmic_bklit_master_disable); +EXPORT_SYMBOL(pmic_bklit_set_current); +EXPORT_SYMBOL(pmic_bklit_get_current); +EXPORT_SYMBOL(pmic_bklit_set_dutycycle); +EXPORT_SYMBOL(pmic_bklit_get_dutycycle); +EXPORT_SYMBOL(pmic_bklit_set_cycle_time); +EXPORT_SYMBOL(pmic_bklit_get_cycle_time); +EXPORT_SYMBOL(pmic_bklit_set_mode); +EXPORT_SYMBOL(pmic_bklit_get_mode); +EXPORT_SYMBOL(pmic_bklit_rampup); +EXPORT_SYMBOL(pmic_bklit_off_rampup); +EXPORT_SYMBOL(pmic_bklit_rampdown); +EXPORT_SYMBOL(pmic_bklit_off_rampdown); +EXPORT_SYMBOL(pmic_bklit_enable_edge_slow); +EXPORT_SYMBOL(pmic_bklit_disable_edge_slow); +EXPORT_SYMBOL(pmic_bklit_get_edge_slow); +EXPORT_SYMBOL(pmic_bklit_set_strobemode); +EXPORT_SYMBOL(pmic_tcled_enable); +EXPORT_SYMBOL(pmic_tcled_disable); +EXPORT_SYMBOL(pmic_tcled_get_mode); +EXPORT_SYMBOL(pmic_tcled_ind_set_current); +EXPORT_SYMBOL(pmic_tcled_ind_get_current); +EXPORT_SYMBOL(pmic_tcled_ind_set_blink_pattern); +EXPORT_SYMBOL(pmic_tcled_ind_get_blink_pattern); +EXPORT_SYMBOL(pmic_tcled_fun_set_current); +EXPORT_SYMBOL(pmic_tcled_fun_get_current); +EXPORT_SYMBOL(pmic_tcled_fun_set_cycletime); +EXPORT_SYMBOL(pmic_tcled_fun_get_cycletime); +EXPORT_SYMBOL(pmic_tcled_fun_set_dutycycle); +EXPORT_SYMBOL(pmic_tcled_fun_get_dutycycle); +EXPORT_SYMBOL(pmic_tcled_fun_blendedramps); +EXPORT_SYMBOL(pmic_tcled_fun_sawramps); +EXPORT_SYMBOL(pmic_tcled_fun_blendedbowtie); +EXPORT_SYMBOL(pmic_tcled_fun_chasinglightspattern); +EXPORT_SYMBOL(pmic_tcled_fun_strobe); +EXPORT_SYMBOL(pmic_tcled_fun_rampup); +EXPORT_SYMBOL(pmic_tcled_get_fun_rampup); +EXPORT_SYMBOL(pmic_tcled_fun_rampdown); +EXPORT_SYMBOL(pmic_tcled_get_fun_rampdown); +EXPORT_SYMBOL(pmic_tcled_fun_triode_on); +EXPORT_SYMBOL(pmic_tcled_fun_triode_off); +EXPORT_SYMBOL(pmic_tcled_enable_edge_slow); +EXPORT_SYMBOL(pmic_tcled_disable_edge_slow); +EXPORT_SYMBOL(pmic_tcled_enable_half_current); +EXPORT_SYMBOL(pmic_tcled_disable_half_current); +EXPORT_SYMBOL(pmic_tcled_enable_audio_modulation); +EXPORT_SYMBOL(pmic_tcled_disable_audio_modulation); +EXPORT_SYMBOL(pmic_bklit_set_boost_mode); +EXPORT_SYMBOL(pmic_bklit_get_boost_mode); +EXPORT_SYMBOL(pmic_bklit_config_boost_mode); +EXPORT_SYMBOL(pmic_bklit_gets_boost_mode); + +/*! + * This is the suspend of power management for the pmic light API. + * It suports SAVE and POWER_DOWN state. + * + * @param pdev the device + * @param state the state + * + * @return This function returns 0 if successful. + */ +static int pmic_light_suspend(struct platform_device *dev, pm_message_t state) +{ + suspend_flag = 1; + /* switch off all leds and backlights */ + CHECK_ERROR(pmic_light_init_reg()); + + return 0; +}; + +/*! + * This is the resume of power management for the pmic light API. + * It suports RESTORE state. + * + * @param dev the device + * + * @return This function returns 0 if successful. + */ +static int pmic_light_resume(struct platform_device *pdev) +{ + suspend_flag = 0; + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +}; + +/*! + * This function enables backlight & tcled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_tcled_master_enable(void) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + reg_value = BITFVAL(BIT_LEDEN, 1); + mask = BITFMASK(BIT_LEDEN); + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables backlight & tcled. + * + * @return This function returns PMIC_SUCCESS if successful + */ +PMIC_STATUS pmic_bklit_tcled_master_disable(void) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + reg_value = BITFVAL(BIT_LEDEN, 0); + mask = BITFMASK(BIT_LEDEN); + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables backlight. Not supported on mc13783 + * Use pmic_bklit_tcled_master_enable. + * + * @return This function returns PMIC_NOT_SUPPORTED + */ +PMIC_STATUS pmic_bklit_master_enable(void) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function disables backlight. Not supported on mc13783 + * Use pmic_bklit_tcled_master_enable. + * + * @return This function returns PMIC_NOT_SUPPORTED + */ +PMIC_STATUS pmic_bklit_master_disable(void) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function sets backlight current level. + * + * @param channel Backlight channel + * @param level Backlight current level, as the following table. + * @verbatim + * level main & aux keyboard + * ------ ----------- -------- + * 0 0 mA 0 mA + * 1 3 mA 12 mA + * 2 6 mA 24 mA + * 3 9 mA 36 mA + * 4 12 mA 48 mA + * 5 15 mA 60 mA + * 6 18 mA 72 mA + * 7 21 mA 84 mA + * @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_current(t_bklit_channel channel, unsigned char level) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + value = BITFVAL(BIT_CL_MAIN, level); + mask = BITFMASK(BIT_CL_MAIN); + break; + case BACKLIGHT_LED2: + value = BITFVAL(BIT_CL_AUX, level); + mask = BITFMASK(BIT_CL_AUX); + break; + case BACKLIGHT_LED3: + value = BITFVAL(BIT_CL_KEY, level); + mask = BITFMASK(BIT_CL_KEY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(LREG_2, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives backlight current level. + * The channels are not individually adjustable, hence + * the channel parameter is ignored. + * + * @param channel Backlight channel (Ignored because the + * channels are not individually adjustable) + * @param level Pointer to store backlight current level result. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_current(t_bklit_channel channel, + unsigned char *level) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_CL_MAIN); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_CL_AUX); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_CL_KEY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_2, ®_value, mask)); + + switch (channel) { + case BACKLIGHT_LED1: + *level = BITFEXT(reg_value, BIT_CL_MAIN); + break; + case BACKLIGHT_LED2: + *level = BITFEXT(reg_value, BIT_CL_AUX); + break; + case BACKLIGHT_LED3: + *level = BITFEXT(reg_value, BIT_CL_KEY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a backlight channel duty cycle. + * LED perceived brightness for each zone may be individually set by setting + * duty cycle. The default setting is for 0% duty cycle; this keeps all zone + * drivers turned off even after the master enable command. Each LED current + * sink can be turned on and adjusted for brightness with an independent 4 bit + * word for a duty cycle ranging from 0% to 100% in approximately 6.7% steps. + * + * @param channel Backlight channel. + * @param dc Backlight duty cycle, as the following table. + * @verbatim + * dc Duty Cycle (% On-time over Cycle Time) + * ------ --------------------------------------- + * 0 0% + * 1 6.7% + * 2 13.3% + * 3 20% + * 4 26.7% + * 5 33.3% + * 6 40% + * 7 46.7% + * 8 53.3% + * 9 60% + * 10 66.7% + * 11 73.3% + * 12 80% + * 13 86.7% + * 14 93.3% + * 15 100% + * @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_dutycycle(t_bklit_channel channel, unsigned char dc) +{ + unsigned int reg_value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (dc > 15) { + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_2, ®_value, PMIC_ALL_BITS)); + + switch (channel) { + case BACKLIGHT_LED1: + reg_value = reg_value & (~MASK_DUTY_CYCLE); + reg_value = reg_value | (dc << BIT_DUTY_CYCLE); + break; + case BACKLIGHT_LED2: + reg_value = reg_value & (~(MASK_DUTY_CYCLE << INDEX_AUX)); + reg_value = reg_value | (dc << (BIT_DUTY_CYCLE + INDEX_AUX)); + break; + case BACKLIGHT_LED3: + reg_value = reg_value & (~(MASK_DUTY_CYCLE << INDEX_KYD)); + reg_value = reg_value | (dc << (BIT_DUTY_CYCLE + INDEX_KYD)); + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(LREG_2, reg_value, PMIC_ALL_BITS)); + return PMIC_SUCCESS; + +} + +/*! + * This function retrives a backlight channel duty cycle. + * + * @param channel Backlight channel. + * @param dc Pointer to backlight duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_dutycycle(t_bklit_channel channel, unsigned char *dc) +{ + unsigned int reg_value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + CHECK_ERROR(pmic_read_reg(LREG_2, ®_value, PMIC_ALL_BITS)); + + switch (channel) { + case BACKLIGHT_LED1: + *dc = (int)((reg_value & (MASK_DUTY_CYCLE)) + >> BIT_DUTY_CYCLE); + + break; + case BACKLIGHT_LED2: + *dc = (int)((reg_value & (MASK_DUTY_CYCLE << INDEX_AUX)) + >> (BIT_DUTY_CYCLE + INDEX_AUX)); + break; + case BACKLIGHT_LED3: + *dc = (int)((reg_value & (MASK_DUTY_CYCLE << + INDEX_KYD)) >> (BIT_DUTY_CYCLE + + INDEX_KYD)); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a backlight channel cycle time. + * Cycle Time is defined as the period of a complete cycle of + * Time_on + Time_off. The default Cycle Time is set to 0.01 seconds such that + * the 100 Hz on-off cycling is averaged out by the eye to eliminate + * flickering. Additionally, the Cycle Time can be programmed to intentionally + * extend the period of on-off cycles for a visual pulsating or blinking effect. + * + * @param period Backlight cycle time, as the following table. + * @verbatim + * period Cycle Time + * -------- ------------ + * 0 0.01 seconds + * 1 0.1 seconds + * 2 0.5 seconds + * 3 2 seconds + * @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_cycle_time(unsigned char period) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + if (period > 3) { + return PMIC_PARAMETER_ERROR; + } + mask = BITFMASK(BIT_PERIOD); + value = BITFVAL(BIT_PERIOD, period); + CHECK_ERROR(pmic_write_reg(LREG_2, value, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function retrives a backlight channel cycle time setting. + * + * @param period Pointer to save backlight cycle time setting result. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_cycle_time(unsigned char *period) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_PERIOD); + CHECK_ERROR(pmic_read_reg(LREG_2, &value, mask)); + *period = BITFEXT(value, BIT_PERIOD); + return PMIC_SUCCESS; +} + +/*! + * This function sets backlight operation mode. There are two modes of + * operations: current control and triode mode. + * The Duty Cycle/Cycle Time control is retained in Triode Mode. Audio + * coupling is not available in Triode Mode. + * + * @param channel Backlight channel. + * @param mode Backlight operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_mode(t_bklit_channel channel, t_bklit_mode mode) +{ + unsigned int reg_value = 0; + unsigned int clear_val = 0; + unsigned int triode_val = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + CHECK_ERROR(pmic_read_reg(LREG_0, ®_value, PMIC_ALL_BITS)); + + switch (channel) { + case BACKLIGHT_LED1: + clear_val = ~(MASK_TRIODE_MAIN_BL); + triode_val = MASK_TRIODE_MAIN_BL; + break; + case BACKLIGHT_LED2: + clear_val = ~(MASK_TRIODE_MAIN_BL << INDEX_AUXILIARY); + triode_val = (MASK_TRIODE_MAIN_BL << INDEX_AUXILIARY); + break; + case BACKLIGHT_LED3: + clear_val = ~(MASK_TRIODE_MAIN_BL << INDEX_KEYPAD); + triode_val = (MASK_TRIODE_MAIN_BL << INDEX_KEYPAD); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + reg_value = (reg_value & clear_val); + + if (mode == BACKLIGHT_TRIODE_MODE) { + reg_value = (reg_value | triode_val); + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, PMIC_ALL_BITS)); + return PMIC_SUCCESS; +} + +/*! + * This function gets backlight operation mode. There are two modes of + * operations: current control and triode mode. + * The Duty Cycle/Cycle Time control is retained in Triode Mode. Audio + * coupling is not available in Triode Mode. + * + * @param channel Backlight channel. + * @param mode Backlight operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_mode(t_bklit_channel channel, t_bklit_mode *mode) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_TRIODE_MAIN_BL); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_TRIODE_AUX_BL); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_TRIODE_KEY_BL); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_0, ®_value, mask)); + + switch (channel) { + case BACKLIGHT_LED1: + *mode = BITFEXT(reg_value, BIT_TRIODE_MAIN_BL); + break; + case BACKLIGHT_LED2: + *mode = BITFEXT(reg_value, BIT_TRIODE_AUX_BL); + break; + case BACKLIGHT_LED3: + *mode = BITFEXT(reg_value, BIT_TRIODE_KEY_BL); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function starts backlight brightness ramp up function; ramp time is + * fixed at 0.5 seconds. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_rampup(t_bklit_channel channel) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_UP_MAIN_BL); + reg_value = BITFVAL(BIT_UP_MAIN_BL, 1); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_UP_AUX_BL); + reg_value = BITFVAL(BIT_UP_AUX_BL, 1); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_UP_KEY_BL); + reg_value = BITFVAL(BIT_UP_KEY_BL, 1); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function stops backlight brightness ramp up function; + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_off_rampup(t_bklit_channel channel) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_UP_MAIN_BL); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_UP_AUX_BL); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_UP_KEY_BL); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function starts backlight brightness ramp down function; ramp time is + * fixed at 0.5 seconds. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_rampdown(t_bklit_channel channel) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_DOWN_MAIN_BL); + reg_value = BITFVAL(BIT_DOWN_MAIN_BL, 1); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_DOWN_AUX_BL); + reg_value = BITFVAL(BIT_DOWN_AUX_BL, 1); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_DOWN_KEY_BL); + reg_value = BITFVAL(BIT_DOWN_KEY_BL, 1); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function stops backlight brightness ramp down function. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_off_rampdown(t_bklit_channel channel) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (channel) { + case BACKLIGHT_LED1: + mask = BITFMASK(BIT_DOWN_MAIN_BL); + break; + case BACKLIGHT_LED2: + mask = BITFMASK(BIT_DOWN_AUX_BL); + break; + case BACKLIGHT_LED3: + mask = BITFMASK(BIT_DOWN_KEY_BL); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, reg_value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables backlight analog edge slowing mode. Analog Edge + * Slowing slows down the transient edges to reduce the chance of coupling LED + * modulation activity into other circuits. Rise and fall times will be targeted + * for approximately 50usec. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_enable_edge_slow(void) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_SLEWLIMBL); + value = BITFVAL(BIT_SLEWLIMBL, 1); + CHECK_ERROR(pmic_write_reg(LREG_2, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables backlight analog edge slowing mode. The backlight + * drivers will default to an <93>Instant On<94> mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_disable_edge_slow(void) +{ + unsigned int mask; + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_SLEWLIMBL); + CHECK_ERROR(pmic_write_reg(LREG_2, 0, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets backlight analog edge slowing mode. DThe backlight + * + * @param edge Edge slowing mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_edge_slow(bool *edge) +{ + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_SLEWLIMBL); + CHECK_ERROR(pmic_read_reg(LREG_2, &value, mask)); + *edge = (bool) BITFEXT(value, BIT_SLEWLIMBL); + + return PMIC_SUCCESS; +} + +/*! + * This function sets backlight Strobe Light Pulsing mode. + * + * @param channel Backlight channel. + * @param mode Strobe Light Pulsing mode. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_bklit_set_strobemode(t_bklit_channel channel, + t_bklit_strobe_mode mode) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function enables tri-color LED. + * + * @param mode Tri-color LED operation mode. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_enable(t_tcled_mode mode, t_funlight_bank bank) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (mode) { + case TCLED_FUN_MODE: + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + value = MASK_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + value = MASK_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + value = MASK_BK3_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + break; + case TCLED_IND_MODE: + mask = MASK_BK1_FL | MASK_BK2_FL | MASK_BK3_FL; + break; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables tri-color LED. + * + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + * + */ +PMIC_STATUS pmic_tcled_disable(t_funlight_bank bank) +{ + unsigned int mask = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, 0, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives tri-color LED operation mode. + * + * @param mode Pointer to Tri-color LED operation mode. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_mode(t_tcled_mode *mode, t_funlight_bank bank) +{ + unsigned int val; + unsigned int mask; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_0, &val, mask)); + + if (val) { + *mode = TCLED_FUN_MODE; + } else { + *mode = TCLED_IND_MODE; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a tri-color LED channel current level in indicator mode. + * + * @param channel Tri-color LED channel. + * @param level Current level. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_set_current(t_ind_channel channel, + t_tcled_cur_level level, + t_funlight_bank bank) +{ + unsigned int reg_conf = 0; + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (level > TCLED_CUR_LEVEL_4) { + return PMIC_PARAMETER_ERROR; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_IND_RED: + value = BITFVAL(BITS_CL_RED, level); + mask = BITFMASK(BITS_CL_RED); + break; + case TCLED_IND_GREEN: + value = BITFVAL(BITS_CL_GREEN, level); + mask = BITFMASK(BITS_CL_GREEN); + break; + case TCLED_IND_BLUE: + value = BITFVAL(BITS_CL_BLUE, level); + mask = BITFMASK(BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives a tri-color LED channel current level + * in indicator mode. + * + * @param channel Tri-color LED channel. + * @param level Pointer to current level. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_get_current(t_ind_channel channel, + t_tcled_cur_level *level, + t_funlight_bank bank) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_IND_RED: + mask = BITFMASK(BITS_CL_RED); + break; + case TCLED_IND_GREEN: + mask = BITFMASK(BITS_CL_GREEN); + break; + case TCLED_IND_BLUE: + mask = BITFMASK(BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + switch (channel) { + case TCLED_IND_RED: + *level = BITFEXT(value, BITS_CL_RED); + break; + case TCLED_IND_GREEN: + *level = BITFEXT(value, BITS_CL_GREEN); + break; + case TCLED_IND_BLUE: + *level = BITFEXT(value, BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a tri-color LED channel blinking pattern in indication + * mode. + * + * @param channel Tri-color LED channel. + * @param pattern Blinking pattern. + * @param skip If true, skip a cycle after each cycle. + * @param bank Selected tri-color bank + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_set_blink_pattern(t_ind_channel channel, + t_tcled_ind_blink_pattern pattern, + bool skip, t_funlight_bank bank) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (skip == true) { + return PMIC_NOT_SUPPORTED; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_IND_RED: + value = BITFVAL(BITS_DC_RED, pattern); + mask = BITFMASK(BITS_DC_RED); + break; + case TCLED_IND_GREEN: + value = BITFVAL(BITS_DC_GREEN, pattern); + mask = BITFMASK(BITS_DC_GREEN); + break; + case TCLED_IND_BLUE: + value = BITFVAL(BITS_DC_BLUE, pattern); + mask = BITFMASK(BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives a tri-color LED channel blinking pattern in + * indication mode. + * + * @param channel Tri-color LED channel. + * @param pattern Pointer to Blinking pattern. + * @param skip Pointer to a boolean varible indicating if skip + * @param bank Selected tri-color bank + * a cycle after each cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_get_blink_pattern(t_ind_channel channel, + t_tcled_ind_blink_pattern * + pattern, bool *skip, + t_funlight_bank bank) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_IND_RED: + mask = BITFMASK(BITS_DC_RED); + break; + case TCLED_IND_GREEN: + mask = BITFMASK(BITS_DC_GREEN); + break; + case TCLED_IND_BLUE: + mask = BITFMASK(BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + switch (channel) { + case TCLED_IND_RED: + *pattern = BITFEXT(value, BITS_DC_RED); + break; + case TCLED_IND_GREEN: + *pattern = BITFEXT(value, BITS_DC_GREEN); + break; + case TCLED_IND_BLUE: + *pattern = BITFEXT(value, BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets a tri-color LED channel current level in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param level Current level. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_current(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_cur_level level) +{ + unsigned int reg_conf = 0; + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (level > TCLED_CUR_LEVEL_4) { + return PMIC_PARAMETER_ERROR; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + value = BITFVAL(BITS_CL_RED, level); + mask = BITFMASK(BITS_CL_RED); + break; + case TCLED_FUN_CHANNEL2: + value = BITFVAL(BITS_CL_GREEN, level); + mask = BITFMASK(BITS_CL_GREEN); + break; + case TCLED_FUN_CHANNEL3: + value = BITFVAL(BITS_CL_BLUE, level); + mask = BITFMASK(BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives a tri-color LED channel current level + * in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param level Pointer to current level. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_current(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_cur_level *level) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = BITFMASK(BITS_CL_RED); + break; + case TCLED_FUN_CHANNEL2: + mask = BITFMASK(BITS_CL_GREEN); + break; + case TCLED_FUN_CHANNEL3: + mask = BITFMASK(BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + switch (channel) { + case TCLED_FUN_CHANNEL1: + *level = BITFEXT(value, BITS_CL_RED); + break; + case TCLED_FUN_CHANNEL2: + *level = BITFEXT(value, BITS_CL_GREEN); + break; + case TCLED_FUN_CHANNEL3: + *level = BITFEXT(value, BITS_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets tri-color LED cycle time. + * + * @param bank Tri-color LED bank + * @param ct Cycle time. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_cycletime(t_funlight_bank bank, + t_tcled_fun_cycle_time ct) +{ + unsigned int reg_conf = 0; + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (ct > TC_CYCLE_TIME_4) { + return PMIC_PARAMETER_ERROR; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + value = BITFVAL(BIT_PERIOD, ct); + mask = BITFMASK(BIT_PERIOD); + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function retrives tri-color LED cycle time in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param ct Pointer to cycle time. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_cycletime(t_funlight_bank bank, + t_tcled_fun_cycle_time *ct) +{ + unsigned int reg_conf = 0; + unsigned int mask; + unsigned int value; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (*ct > TC_CYCLE_TIME_4) { + return PMIC_PARAMETER_ERROR; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BIT_PERIOD); + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + *ct = BITFVAL(BIT_PERIOD, value); + + return PMIC_SUCCESS; +} + +/*! + * This function sets a tri-color LED channel duty cycle in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param dc Duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_dutycycle(t_funlight_bank bank, + t_funlight_channel channel, + unsigned char dc) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + value = BITFVAL(BITS_DC_RED, dc); + mask = BITFMASK(BITS_DC_RED); + break; + case TCLED_FUN_CHANNEL2: + value = BITFVAL(BITS_DC_GREEN, dc); + mask = BITFMASK(BITS_DC_GREEN); + break; + case TCLED_FUN_CHANNEL3: + value = BITFVAL(BITS_DC_BLUE, dc); + mask = BITFMASK(BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg_conf, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives a tri-color LED channel duty cycle in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param dc Pointer to duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_dutycycle(t_funlight_bank bank, + t_funlight_channel channel, + unsigned char *dc) +{ + unsigned int reg_conf = 0; + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + reg_conf = LREG_3; + break; + case TCLED_FUN_BANK2: + reg_conf = LREG_4; + break; + case TCLED_FUN_BANK3: + reg_conf = LREG_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = BITFMASK(BITS_DC_RED); + break; + case TCLED_FUN_CHANNEL2: + mask = BITFMASK(BITS_DC_GREEN); + break; + case TCLED_FUN_CHANNEL3: + mask = BITFMASK(BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg_conf, &value, mask)); + + switch (channel) { + case TCLED_FUN_CHANNEL1: + *dc = BITFEXT(value, BITS_DC_RED); + break; + case TCLED_FUN_CHANNEL2: + *dc = BITFEXT(value, BITS_DC_GREEN); + break; + case TCLED_FUN_CHANNEL3: + *dc = BITFEXT(value, BITS_DC_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Blended Ramp fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_blendedramps(t_funlight_bank bank, + t_tcled_fun_speed speed) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (speed) { + case TC_OFF: + value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF); + break; + case TC_SLOW: + value = BITFVAL(BITS_FUN_LIGHT, BLENDED_RAMPS_SLOW); + break; + case TC_FAST: + value = BITFVAL(BITS_FUN_LIGHT, BLENDED_RAMPS_FAST); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BITS_FUN_LIGHT); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Saw Ramp fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_sawramps(t_funlight_bank bank, + t_tcled_fun_speed speed) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (speed) { + case TC_OFF: + value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF); + break; + case TC_SLOW: + value = BITFVAL(BITS_FUN_LIGHT, SAW_RAMPS_SLOW); + break; + case TC_FAST: + value = BITFVAL(BITS_FUN_LIGHT, SAW_RAMPS_FAST); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BITS_FUN_LIGHT); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Blended Bowtie fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_blendedbowtie(t_funlight_bank bank, + t_tcled_fun_speed speed) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (speed) { + case TC_OFF: + value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF); + break; + case TC_SLOW: + value = BITFVAL(BITS_FUN_LIGHT, BLENDED_INVERSE_RAMPS_SLOW); + break; + case TC_FAST: + value = BITFVAL(BITS_FUN_LIGHT, BLENDED_INVERSE_RAMPS_FAST); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BITS_FUN_LIGHT); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Chasing Lights fun light pattern. + * + * @param bank Tri-color LED bank + * @param pattern Chasing light pattern mode. + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_chasinglightspattern(t_funlight_bank bank, + t_chaselight_pattern pattern, + t_tcled_fun_speed speed) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + if (pattern > BGR) { + return PMIC_PARAMETER_ERROR; + } + + switch (speed) { + case TC_OFF: + value = BITFVAL(BITS_FUN_LIGHT, FUN_LIGHTS_OFF); + break; + case TC_SLOW: + if (pattern == PMIC_RGB) { + value = + BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_RGB_SLOW); + } else { + value = + BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_BGR_SLOW); + } + break; + case TC_FAST: + if (pattern == PMIC_RGB) { + value = + BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_RGB_FAST); + } else { + value = + BITFVAL(BITS_FUN_LIGHT, CHASING_LIGHTS_BGR_FAST); + } + break; + default: + return PMIC_PARAMETER_ERROR; + } + + mask = BITFMASK(BITS_FUN_LIGHT); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Strobe Mode fun light pattern. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_strobe(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_fun_strobe_speed speed) +{ + /* not supported on mc13783 */ + + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function initiates Tri-color LED brightness Ramp Up function; Ramp time + * is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampup Ramp-up configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_rampup(t_funlight_bank bank, + t_funlight_channel channel, bool rampup) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = LEDR1RAMPUP; + value = LEDR1RAMPUP; + break; + case TCLED_FUN_BANK2: + mask = LEDR2RAMPUP; + value = LEDR2RAMPUP; + break; + case TCLED_FUN_BANK3: + mask = LEDR3RAMPUP; + value = LEDR3RAMPUP; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = mask; + value = value; + break; + case TCLED_FUN_CHANNEL2: + mask = mask * 2; + value = value * 2; + break; + case TCLED_FUN_CHANNEL3: + mask = mask * 4; + value = value * 4; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (!rampup) { + value = 0; + } + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets Tri-color LED brightness Ramp Up function; Ramp time + * is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampup Ramp-up configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_fun_rampup(t_funlight_bank bank, + t_funlight_channel channel, bool *rampup) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = LEDR1RAMPUP; + break; + case TCLED_FUN_BANK2: + mask = LEDR2RAMPUP; + break; + case TCLED_FUN_BANK3: + mask = LEDR3RAMPUP; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = mask; + break; + case TCLED_FUN_CHANNEL2: + mask = mask * 2; + break; + case TCLED_FUN_CHANNEL3: + mask = mask * 4; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_1, &value, mask)); + if (value) { + *rampup = true; + } else { + *rampup = false; + } + + return PMIC_SUCCESS; +} + +/*! + * This function initiates Tri-color LED brightness Ramp Down function; Ramp + * time is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampdown Ramp-down configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_rampdown(t_funlight_bank bank, + t_funlight_channel channel, bool rampdown) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = LEDR1RAMPDOWN; + value = LEDR1RAMPDOWN; + break; + case TCLED_FUN_BANK2: + mask = LEDR2RAMPDOWN; + value = LEDR2RAMPDOWN; + break; + case TCLED_FUN_BANK3: + mask = LEDR3RAMPDOWN; + value = LEDR3RAMPDOWN; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = mask; + value = value; + break; + case TCLED_FUN_CHANNEL2: + mask = mask * 2; + value = value * 2; + break; + case TCLED_FUN_CHANNEL3: + mask = mask * 4; + value = value * 4; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (!rampdown) { + value = 0; + } + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + return PMIC_SUCCESS; +} + +/*! + * This function initiates Tri-color LED brightness Ramp Down function; Ramp + * time is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampdown Ramp-down configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_fun_rampdown(t_funlight_bank bank, + t_funlight_channel channel, + bool *rampdown) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = LEDR1RAMPDOWN; + break; + case TCLED_FUN_BANK2: + mask = LEDR2RAMPDOWN; + break; + case TCLED_FUN_BANK3: + mask = LEDR3RAMPDOWN; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + switch (channel) { + case TCLED_FUN_CHANNEL1: + mask = mask; + break; + case TCLED_FUN_CHANNEL2: + mask = mask * 2; + break; + case TCLED_FUN_CHANNEL3: + mask = mask * 4; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(LREG_1, &value, mask)); + if (value) { + *rampdown = true; + } else { + *rampdown = false; + } + return PMIC_SUCCESS; +} + +/*! + * This function enables a Tri-color channel triode mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_triode_on(t_funlight_bank bank, + t_funlight_channel channel) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + value = ENABLE_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + value = ENABLE_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + value = ENABLE_BK2_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables a Tri-color LED channel triode mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_triode_off(t_funlight_bank bank, + t_funlight_channel channel) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + switch (bank) { + case TCLED_FUN_BANK1: + mask = MASK_BK1_FL; + break; + case TCLED_FUN_BANK2: + mask = MASK_BK2_FL; + break; + case TCLED_FUN_BANK3: + mask = MASK_BK3_FL; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables Tri-color LED edge slowing. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_enable_edge_slow(void) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_SLEWLIMTC, 1); + mask = BITFMASK(BIT_SLEWLIMTC); + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables Tri-color LED edge slowing. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_disable_edge_slow(void) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_SLEWLIMTC, 0); + mask = BITFMASK(BIT_SLEWLIMTC); + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables Tri-color LED half current mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_enable_half_current(void) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_TC1HALF, 1); + mask = BITFMASK(BIT_TC1HALF); + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function disables Tri-color LED half current mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_disable_half_current(void) +{ + unsigned int mask = 0; + unsigned int value = 0; + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_TC1HALF, 0); + mask = BITFMASK(BIT_TC1HALF); + + CHECK_ERROR(pmic_write_reg(LREG_1, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function enables backlight or Tri-color LED audio modulation. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_enable_audio_modulation(t_led_channel channel, + t_aud_path path, + t_aud_gain gain, bool lpf_bypass) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function disables backlight or Tri-color LED audio modulation. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_disable_audio_modulation(void) +{ + return PMIC_NOT_SUPPORTED; +} + +/*! + * This function enables the boost mode. + * Only on mc13783 2.0 or higher + * + * @param en_dis Enable or disable the boost mode + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_set_boost_mode(bool en_dis) +{ + + pmic_version_t mc13783_ver; + unsigned int mask; + unsigned int value; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + + if (suspend_flag == 1) { + return -EBUSY; + } + + value = BITFVAL(BIT_BOOSTEN, en_dis); + mask = BITFMASK(BIT_BOOSTEN); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets the boost mode. + * Only on mc13783 2.0 or higher + * + * @param en_dis Enable or disable the boost mode + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_get_boost_mode(bool *en_dis) +{ + pmic_version_t mc13783_ver; + unsigned int mask; + unsigned int value; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + + if (suspend_flag == 1) { + return -EBUSY; + } + mask = BITFMASK(BIT_BOOSTEN); + CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask)); + *en_dis = BITFEXT(value, BIT_BOOSTEN); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function sets boost mode configuration + * Only on mc13783 2.0 or higher + * + * @param abms Define adaptive boost mode selection + * @param abr Define adaptive boost reference + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_config_boost_mode(unsigned int abms, unsigned int abr) +{ + unsigned int conf_boost = 0; + unsigned int mask; + unsigned int value; + pmic_version_t mc13783_ver; + + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + if (suspend_flag == 1) { + return -EBUSY; + } + + if (abms > MAX_BOOST_ABMS) { + return PMIC_PARAMETER_ERROR; + } + + if (abr > MAX_BOOST_ABR) { + return PMIC_PARAMETER_ERROR; + } + + conf_boost = abms | (abr << 3); + + value = BITFVAL(BITS_BOOST, conf_boost); + mask = BITFMASK(BITS_BOOST); + CHECK_ERROR(pmic_write_reg(LREG_0, value, mask)); + + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets boost mode configuration + * Only on mc13783 2.0 or higher + * + * @param abms Define adaptive boost mode selection + * @param abr Define adaptive boost reference + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_gets_boost_mode(unsigned int *abms, unsigned int *abr) +{ + unsigned int mask; + unsigned int value; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + if (suspend_flag == 1) { + return -EBUSY; + } + + mask = BITFMASK(BITS_BOOST_ABMS); + CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask)); + *abms = BITFEXT(value, BITS_BOOST_ABMS); + + mask = BITFMASK(BITS_BOOST_ABR); + CHECK_ERROR(pmic_read_reg(LREG_0, &value, mask)); + *abr = BITFEXT(value, BITS_BOOST_ABR); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function implements IOCTL controls on a PMIC Light device. + * + + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_light_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + t_bklit_setting_param *bklit_setting = NULL; + t_tcled_enable_param *tcled_setting; + t_fun_param *fun_param; + t_tcled_ind_param *tcled_ind; + + if (_IOC_TYPE(cmd) != 'p') + return -ENOTTY; + + bklit_setting = kmalloc(sizeof(t_bklit_setting_param), GFP_KERNEL); + tcled_setting = kmalloc(sizeof(t_tcled_enable_param), GFP_KERNEL); + fun_param = kmalloc(sizeof(t_fun_param), GFP_KERNEL); + tcled_ind = kmalloc(sizeof(t_tcled_ind_param), GFP_KERNEL); + switch (cmd) { + case PMIC_BKLIT_TCLED_ENABLE: + pmic_bklit_tcled_master_enable(); + break; + + case PMIC_BKLIT_TCLED_DISABLE: + pmic_bklit_tcled_master_disable(); + break; + + case PMIC_BKLIT_ENABLE: + pmic_bklit_master_enable(); + break; + + case PMIC_BKLIT_DISABLE: + pmic_bklit_master_disable(); + break; + + case PMIC_SET_BKLIT: + if (bklit_setting == NULL) + return -ENOMEM; + + if (copy_from_user(bklit_setting, (t_bklit_setting_param *) arg, + sizeof(t_bklit_setting_param))) { + kfree(bklit_setting); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_bklit_set_mode(bklit_setting->channel, + bklit_setting->mode), + (kfree(bklit_setting))); + + CHECK_ERROR_KFREE(pmic_bklit_set_current(bklit_setting->channel, + bklit_setting-> + current_level), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_set_dutycycle + (bklit_setting->channel, + bklit_setting->duty_cycle), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_set_cycle_time + (bklit_setting->cycle_time), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_set_boost_mode + (bklit_setting->en_dis), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_config_boost_mode + (bklit_setting->abms, bklit_setting->abr), + (kfree(bklit_setting))); + if (bklit_setting->edge_slow != false) { + CHECK_ERROR_KFREE(pmic_bklit_enable_edge_slow(), + (kfree(bklit_setting))); + } else { + CHECK_ERROR_KFREE(pmic_bklit_disable_edge_slow(), + (kfree(bklit_setting))); + } + + kfree(bklit_setting); + break; + + case PMIC_GET_BKLIT: + if (bklit_setting == NULL) + return -ENOMEM; + + if (copy_from_user(bklit_setting, (t_bklit_setting_param *) arg, + sizeof(t_bklit_setting_param))) { + kfree(bklit_setting); + return -EFAULT; + } + + CHECK_ERROR_KFREE(pmic_bklit_get_current(bklit_setting->channel, + &bklit_setting-> + current_level), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_get_cycle_time + (&bklit_setting->cycle_time), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_get_dutycycle + (bklit_setting->channel, + &bklit_setting->duty_cycle), + (kfree(bklit_setting))); + bklit_setting->strobe = BACKLIGHT_STROBE_NONE; + CHECK_ERROR_KFREE(pmic_bklit_get_mode(bklit_setting->channel, + &bklit_setting->mode), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_get_edge_slow + (&bklit_setting->edge_slow), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_get_boost_mode + (&bklit_setting->en_dis), + (kfree(bklit_setting))); + CHECK_ERROR_KFREE(pmic_bklit_gets_boost_mode + (&bklit_setting->abms, &bklit_setting->abr), + (kfree(bklit_setting))); + + if (copy_to_user((t_bklit_setting_param *) arg, bklit_setting, + sizeof(t_bklit_setting_param))) { + kfree(bklit_setting); + return -EFAULT; + } + kfree(bklit_setting); + break; + + case PMIC_RAMPUP_BKLIT: + CHECK_ERROR(pmic_bklit_rampup((t_bklit_channel) arg)); + break; + + case PMIC_RAMPDOWN_BKLIT: + CHECK_ERROR(pmic_bklit_rampdown((t_bklit_channel) arg)); + break; + + case PMIC_OFF_RAMPUP_BKLIT: + CHECK_ERROR(pmic_bklit_off_rampup((t_bklit_channel) arg)); + break; + + case PMIC_OFF_RAMPDOWN_BKLIT: + CHECK_ERROR(pmic_bklit_off_rampdown((t_bklit_channel) arg)); + break; + + case PMIC_TCLED_ENABLE: + if (tcled_setting == NULL) + return -ENOMEM; + + if (copy_from_user(tcled_setting, (t_tcled_enable_param *) arg, + sizeof(t_tcled_enable_param))) { + kfree(tcled_setting); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_tcled_enable(tcled_setting->mode, + tcled_setting->bank), + (kfree(bklit_setting))); + break; + + case PMIC_TCLED_DISABLE: + CHECK_ERROR(pmic_tcled_disable((t_funlight_bank) arg)); + break; + + case PMIC_TCLED_PATTERN: + if (fun_param == NULL) + return -ENOMEM; + + if (copy_from_user(fun_param, + (t_fun_param *) arg, sizeof(t_fun_param))) { + kfree(fun_param); + return -EFAULT; + } + + switch (fun_param->pattern) { + case BLENDED_RAMPS_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_blendedramps + (fun_param->bank, TC_SLOW), + (kfree(fun_param))); + break; + + case BLENDED_RAMPS_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_blendedramps + (fun_param->bank, TC_FAST), + (kfree(fun_param))); + break; + + case SAW_RAMPS_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_sawramps + (fun_param->bank, TC_SLOW), + (kfree(fun_param))); + break; + + case SAW_RAMPS_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_sawramps + (fun_param->bank, TC_FAST), + (kfree(fun_param))); + break; + + case BLENDED_BOWTIE_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_blendedbowtie + (fun_param->bank, TC_SLOW), + (kfree(fun_param))); + break; + + case BLENDED_BOWTIE_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_blendedbowtie + (fun_param->bank, TC_FAST), + (kfree(fun_param))); + break; + + case STROBE_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_strobe + (fun_param->bank, fun_param->channel, + TC_STROBE_SLOW), (kfree(fun_param))); + break; + + case STROBE_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_strobe + (fun_param->bank, + fun_param->channel, TC_STROBE_SLOW), + (kfree(fun_param))); + break; + + case CHASING_LIGHT_RGB_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern + (fun_param->bank, PMIC_RGB, TC_SLOW), + (kfree(fun_param))); + break; + + case CHASING_LIGHT_RGB_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern + (fun_param->bank, PMIC_RGB, TC_FAST), + (kfree(fun_param))); + break; + + case CHASING_LIGHT_BGR_SLOW: + CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern + (fun_param->bank, BGR, TC_SLOW), + (kfree(fun_param))); + break; + + case CHASING_LIGHT_BGR_FAST: + CHECK_ERROR_KFREE(pmic_tcled_fun_chasinglightspattern + (fun_param->bank, BGR, TC_FAST), + (kfree(fun_param))); + break; + } + + kfree(fun_param); + break; + + case PMIC_SET_TCLED: + if (tcled_ind == NULL) + return -ENOMEM; + + if (copy_from_user(tcled_ind, (t_tcled_ind_param *) arg, + sizeof(t_tcled_ind_param))) { + kfree(tcled_ind); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_tcled_ind_set_current(tcled_ind->channel, + tcled_ind->level, + tcled_ind->bank), + (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_ind_set_blink_pattern + (tcled_ind->channel, tcled_ind->pattern, + tcled_ind->skip, tcled_ind->bank), + (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_fun_rampup + (tcled_ind->bank, tcled_ind->channel, + tcled_ind->rampup), (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_fun_rampdown + (tcled_ind->bank, tcled_ind->channel, + tcled_ind->rampdown), (kfree(tcled_ind))); + if (tcled_ind->half_current) { + CHECK_ERROR_KFREE(pmic_tcled_enable_half_current(), + (kfree(tcled_ind))); + } else { + CHECK_ERROR_KFREE(pmic_tcled_disable_half_current(), + (kfree(tcled_ind))); + } + + kfree(tcled_ind); + break; + + case PMIC_GET_TCLED: + if (tcled_ind == NULL) + return -ENOMEM; + + if (copy_from_user(tcled_ind, (t_tcled_ind_param *) arg, + sizeof(t_tcled_ind_param))) { + kfree(tcled_ind); + return -EFAULT; + } + CHECK_ERROR_KFREE(pmic_tcled_ind_get_current(tcled_ind->channel, + &tcled_ind->level, + tcled_ind->bank), + (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_ind_get_blink_pattern + (tcled_ind->channel, &tcled_ind->pattern, + &tcled_ind->skip, tcled_ind->bank), + (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_get_fun_rampup + (tcled_ind->bank, tcled_ind->channel, + &tcled_ind->rampup), (kfree(tcled_ind))); + CHECK_ERROR_KFREE(pmic_tcled_get_fun_rampdown + (tcled_ind->bank, tcled_ind->channel, + &tcled_ind->rampdown), (kfree(tcled_ind))); + if (copy_to_user + ((t_tcled_ind_param *) arg, tcled_ind, + sizeof(t_tcled_ind_param))) { + return -EFAULT; + } + kfree(tcled_ind); + + break; + + default: + return -EINVAL; + } + return 0; +} + +/*! + * This function initialize Light registers of mc13783 with 0. + * + * @return This function returns 0 if successful. + */ +int pmic_light_init_reg(void) +{ + CHECK_ERROR(pmic_write_reg(LREG_0, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_1, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_2, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_3, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_4, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(LREG_5, 0, PMIC_ALL_BITS)); + return 0; +} + +/*! + * This function implements the open method on a mc13783 light device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_light_open(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + return 0; +} + +/*! + * This function implements the release method on a mc13783 light device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_light_release(struct inode *inode, struct file *file) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + return 0; +} + +static struct file_operations pmic_light_fops = { + .owner = THIS_MODULE, + .ioctl = pmic_light_ioctl, + .open = pmic_light_open, + .release = pmic_light_release, +}; + +static int pmic_light_remove(struct platform_device *pdev) +{ + device_destroy(pmic_light_class, MKDEV(pmic_light_major, 0)); + class_destroy(pmic_light_class); + unregister_chrdev(pmic_light_major, "pmic_light"); + return 0; +} + +static int pmic_light_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *temp_class; + + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) { + return -ERESTARTSYS; + } + } + pmic_light_major = register_chrdev(0, "pmic_light", &pmic_light_fops); + + if (pmic_light_major < 0) { + printk(KERN_ERR "Unable to get a major for pmic_light\n"); + return pmic_light_major; + } + init_waitqueue_head(&suspendq); + + pmic_light_class = class_create(THIS_MODULE, "pmic_light"); + if (IS_ERR(pmic_light_class)) { + printk(KERN_ERR "Error creating pmic_light class.\n"); + ret = PTR_ERR(pmic_light_class); + goto err_out1; + } + + temp_class = device_create(pmic_light_class, NULL, + MKDEV(pmic_light_major, 0), NULL, + "pmic_light"); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "Error creating pmic_light class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + ret = pmic_light_init_reg(); + if (ret != PMIC_SUCCESS) { + goto err_out3; + } + + printk(KERN_INFO "PMIC Light successfully loaded\n"); + return ret; + + err_out3: + device_destroy(pmic_light_class, MKDEV(pmic_light_major, 0)); + err_out2: + class_destroy(pmic_light_class); + err_out1: + unregister_chrdev(pmic_light_major, "pmic_light"); + return ret; +} + +static struct platform_driver pmic_light_driver_ldm = { + .driver = { + .name = "pmic_light", + }, + .suspend = pmic_light_suspend, + .resume = pmic_light_resume, + .probe = pmic_light_probe, + .remove = pmic_light_remove, +}; + +/* + * Initialization and Exit + */ + +static int __init pmic_light_init(void) +{ + pr_debug("PMIC Light driver loading...\n"); + return platform_driver_register(&pmic_light_driver_ldm); +} +static void __exit pmic_light_exit(void) +{ + platform_driver_unregister(&pmic_light_driver_ldm); + pr_debug("PMIC Light driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +subsys_initcall(pmic_light_init); +module_exit(pmic_light_exit); + +MODULE_DESCRIPTION("PMIC_LIGHT"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13783/pmic_light_defs.h b/drivers/mxc/pmic/mc13783/pmic_light_defs.h new file mode 100644 index 000000000000..34602015a34d --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_light_defs.h @@ -0,0 +1,144 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_light_defs.h + * @brief This is the internal header PMIC(mc13783) Light and Backlight driver. + * + * @ingroup PMIC_LIGHT + */ + +#ifndef __MC13783_LIGHT_DEFS_H__ +#define __MC13783_LIGHT_DEFS_H__ + +#define LREG_0 REG_LED_CONTROL_0 +#define LREG_1 REG_LED_CONTROL_1 +#define LREG_2 REG_LED_CONTROL_2 +#define LREG_3 REG_LED_CONTROL_3 +#define LREG_4 REG_LED_CONTROL_4 +#define LREG_5 REG_LED_CONTROL_5 + +/* REG_LED_CONTROL_0 */ + +#define BIT_LEDEN_LSH 0 +#define BIT_LEDEN_WID 1 +#define MASK_TRIODE_MAIN_BL 0x080 +#define INDEX_AUXILIARY 1 +#define INDEX_KEYPAD 2 +#define BITS_FUN_LIGHT_LSH 17 +#define BITS_FUN_LIGHT_WID 4 +#define MASK_FUN_LIGHT 0x1E0000 +#define MASK_BK1_FL 0x200000 +#define ENABLE_BK1_FL 0x200000 +#define MASK_BK2_FL 0x400000 +#define ENABLE_BK2_FL 0x400000 +#define MASK_BK3_FL 0x800000 +#define ENABLE_BK3_FL 0x800000 +#define BIT_UP_MAIN_BL_LSH 1 +#define BIT_UP_MAIN_BL_WID 1 +#define BIT_UP_AUX_BL_LSH 2 +#define BIT_UP_AUX_BL_WID 1 +#define BIT_UP_KEY_BL_LSH 3 +#define BIT_UP_KEY_BL_WID 1 +#define BIT_DOWN_MAIN_BL_LSH 4 +#define BIT_DOWN_MAIN_BL_WID 1 +#define BIT_DOWN_AUX_BL_LSH 5 +#define BIT_DOWN_AUX_BL_WID 1 +#define BIT_DOWN_KEY_BL_LSH 6 +#define BIT_DOWN_KEY_BL_WID 1 +#define BIT_TRIODE_MAIN_BL_LSH 7 +#define BIT_TRIODE_MAIN_BL_WID 1 +#define BIT_TRIODE_AUX_BL_LSH 8 +#define BIT_TRIODE_AUX_BL_WID 1 +#define BIT_TRIODE_KEY_BL_LSH 9 +#define BIT_TRIODE_KEY_BL_WID 1 + +#define BIT_BOOSTEN_LSH 10 +#define BIT_BOOSTEN_WID 1 +#define BITS_BOOST_LSH 11 +#define BITS_BOOST_WID 5 +#define BITS_BOOST_ABMS_LSH 11 +#define BITS_BOOST_ABMS_WID 3 +#define BITS_BOOST_ABR_LSH 14 +#define BITS_BOOST_ABR_WID 2 + +#define MAX_BOOST_ABMS 7 +#define MAX_BOOST_ABR 3 + +/* REG_LED_CONTROL_1 */ + +#define BIT_SLEWLIMTC_LSH 23 +#define BIT_SLEWLIMTC_WID 1 +#define BIT_TC1HALF_LSH 18 +#define BIT_TC1HALF_WID 1 +#define LEDR1RAMPUP 0x000001 +#define LEDR2RAMPUP 0x000040 +#define LEDR3RAMPUP 0x001000 +#define LEDR1RAMPDOWN 0x000008 +#define LEDR2RAMPDOWN 0x000200 +#define LEDR3RAMPDOWN 0x008000 + +/* REG_LED_CONTROL_2 */ + +#define BIT_SLEWLIMBL_LSH 23 +#define BIT_SLEWLIMBL_WID 1 +#define BIT_DUTY_CYCLE 9 +#define MASK_DUTY_CYCLE 0x001E00 +#define INDEX_AUX 4 +#define INDEX_KYD 8 +#define BIT_CL_MAIN_LSH 0 +#define BIT_CL_MAIN_WID 3 +#define BIT_CL_AUX_LSH 3 +#define BIT_CL_AUX_WID 3 +#define BIT_CL_KEY_LSH 6 +#define BIT_CL_KEY_WID 3 + +/* REG_LED_CONTROL_3 4 5 */ +#define BITS_CL_RED_LSH 0 +#define BITS_CL_RED_WID 2 +#define BITS_CL_GREEN_LSH 2 +#define BITS_CL_GREEN_WID 2 +#define BITS_CL_BLUE_LSH 4 +#define BITS_CL_BLUE_WID 2 +#define BITS_DC_RED_LSH 6 +#define BITS_DC_RED_WID 5 +#define BITS_DC_GREEN_LSH 11 +#define BITS_DC_GREEN_WID 5 +#define BITS_DC_BLUE_LSH 16 +#define BITS_DC_BLUE_WID 5 +#define BIT_PERIOD_LSH 21 +#define BIT_PERIOD_WID 2 + +#define DUTY_CYCLE_MAX 31 + +/* Fun light pattern */ +#define BLENDED_RAMPS_SLOW 0 +#define BLENDED_RAMPS_FAST 1 +#define SAW_RAMPS_SLOW 2 +#define SAW_RAMPS_FAST 3 +#define BLENDED_INVERSE_RAMPS_SLOW 4 +#define BLENDED_INVERSE_RAMPS_FAST 5 +#define CHASING_LIGHTS_RGB_SLOW 6 +#define CHASING_LIGHTS_RGB_FAST 7 +#define CHASING_LIGHTS_BGR_SLOW 8 +#define CHASING_LIGHTS_BGR_FAST 9 +#define FUN_LIGHTS_OFF 15 + +/*! + * This function initialize Light registers of mc13783 with 0. + * + * @return This function returns 0 if successful. + */ +int pmic_light_init_reg(void); + +#endif /* __MC13783_LIGHT_DEFS_H__ */ diff --git a/drivers/mxc/pmic/mc13783/pmic_power.c b/drivers/mxc/pmic/mc13783/pmic_power.c new file mode 100644 index 000000000000..c67fe773703d --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_power.c @@ -0,0 +1,3146 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_power.c + * @brief This is the main file of PMIC(mc13783) Power driver. + * + * @ingroup PMIC_POWER + */ + +/* + * Includes + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pmic_power_defs.h" + +#ifdef CONFIG_MXC_HWEVENT +#include +#endif + +#include + +#define MC13783_REGCTRL_GPOx_MASK 0x18000 + +static bool VBKUP1_EN; +static bool VBKUP2_EN; + +/* + * Power Pmic API + */ + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_power_off); +EXPORT_SYMBOL(pmic_power_set_pc_config); +EXPORT_SYMBOL(pmic_power_get_pc_config); +EXPORT_SYMBOL(pmic_power_regulator_on); +EXPORT_SYMBOL(pmic_power_regulator_off); +EXPORT_SYMBOL(pmic_power_regulator_set_voltage); +EXPORT_SYMBOL(pmic_power_regulator_get_voltage); +EXPORT_SYMBOL(pmic_power_regulator_set_config); +EXPORT_SYMBOL(pmic_power_regulator_get_config); +EXPORT_SYMBOL(pmic_power_vbkup2_auto_en); +EXPORT_SYMBOL(pmic_power_get_vbkup2_auto_state); +EXPORT_SYMBOL(pmic_power_bat_det_en); +EXPORT_SYMBOL(pmic_power_get_bat_det_state); +EXPORT_SYMBOL(pmic_power_vib_pin_en); +EXPORT_SYMBOL(pmic_power_gets_vib_pin_state); +EXPORT_SYMBOL(pmic_power_get_power_mode_sense); +EXPORT_SYMBOL(pmic_power_set_regen_assig); +EXPORT_SYMBOL(pmic_power_get_regen_assig); +EXPORT_SYMBOL(pmic_power_set_regen_inv); +EXPORT_SYMBOL(pmic_power_get_regen_inv); +EXPORT_SYMBOL(pmic_power_esim_v_en); +EXPORT_SYMBOL(pmic_power_gets_esim_v_state); +EXPORT_SYMBOL(pmic_power_set_auto_reset_en); +EXPORT_SYMBOL(pmic_power_get_auto_reset_en); +EXPORT_SYMBOL(pmic_power_set_conf_button); +EXPORT_SYMBOL(pmic_power_get_conf_button); +EXPORT_SYMBOL(pmic_power_event_sub); +EXPORT_SYMBOL(pmic_power_event_unsub); + +/*! + * This function is called to put the power in a low power state. + * Switching off the platform cannot be decided by + * the power module. It has to be handled by the + * client application. + * + * @param pdev the device structure used to give information on which power + * device (0 through 3 channels) to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int pmic_power_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +}; + +/*! + * This function is called to resume the power from a low power state. + * + * @param pdev the device structure used to give information on which power + * device (0 through 3 channels) to suspend + * + * @return The function always returns 0. + */ +static int pmic_power_resume(struct platform_device *pdev) +{ + return 0; +}; + +/*! + * This function sets user power off in power control register and thus powers + * off the phone. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +void pmic_power_off(void) +{ + unsigned int mask, value; + + mask = BITFMASK(MC13783_PWRCTRL_USER_OFF_SPI); + value = BITFVAL(MC13783_PWRCTRL_USER_OFF_SPI, + MC13783_PWRCTRL_USER_OFF_SPI_ENABLE); + + pmic_write_reg(REG_POWER_CONTROL_0, value, mask); +} + +/*! + * This function sets the power control configuration. + * + * @param pc_config power control configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_set_pc_config(t_pc_config *pc_config) +{ + unsigned int pwrctrl_val_reg0 = 0; + unsigned int pwrctrl_val_reg1 = 0; + unsigned int pwrctrl_mask_reg0 = 0; + unsigned int pwrctrl_mask_reg1 = 0; + + if (pc_config == NULL) { + return PMIC_PARAMETER_ERROR; + } + + if (pc_config->pc_enable != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PCEN, + MC13783_PWRCTRL_PCEN_ENABLE); + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PCT, + pc_config->pc_timer); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PCEN, + MC13783_PWRCTRL_PCEN_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_PCEN); + pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_PCT); + + if (pc_config->pc_count_enable != false) { + + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT_EN, + MC13783_PWRCTRL_PC_COUNT_EN_ENABLE); + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT, + pc_config->pc_count); + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_PC_MAX_CNT, + pc_config->pc_max_count); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_PC_COUNT_EN, + MC13783_PWRCTRL_PC_COUNT_EN_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_PC_COUNT_EN); + pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_PC_MAX_CNT) | + BITFMASK(MC13783_PWRCTRL_PC_COUNT); + + if (pc_config->warm_enable != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN, + MC13783_PWRCTRL_WARM_EN_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN, + MC13783_PWRCTRL_WARM_EN_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_WARM_EN); + + if (pc_config->user_off_pc != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_USER_OFF_PC, + MC13783_PWRCTRL_USER_OFF_PC_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_WARM_EN, + MC13783_PWRCTRL_USER_OFF_PC_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_USER_OFF_PC); + + if (pc_config->clk_32k_user_off != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_USER_OFF, + MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_USER_OFF, + MC13783_PWRCTRL_32OUT_USER_OFF_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_32OUT_USER_OFF); + + if (pc_config->clk_32k_enable != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_EN, + MC13783_PWRCTRL_32OUT_EN_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_32OUT_EN, + MC13783_PWRCTRL_32OUT_EN_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_32OUT_EN); + + if (pc_config->en_vbkup1 != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_EN, + MC13783_PWRCTRL_VBKUP_ENABLE); + VBKUP1_EN = true; + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_EN, + MC13783_PWRCTRL_VBKUP_DISABLE); + VBKUP1_EN = false; + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1_EN); + + if (pc_config->en_vbkup2 != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_EN, + MC13783_PWRCTRL_VBKUP_ENABLE); + VBKUP2_EN = true; + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_EN, + MC13783_PWRCTRL_VBKUP_DISABLE); + VBKUP2_EN = false; + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP2_EN); + + if (pc_config->auto_en_vbkup1 != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_AUTO_EN, + MC13783_PWRCTRL_VBKUP_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1_AUTO_EN, + MC13783_PWRCTRL_VBKUP_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1_AUTO_EN); + + if (pc_config->auto_en_vbkup2 != false) { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_AUTO_EN, + MC13783_PWRCTRL_VBKUP_ENABLE); + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2_AUTO_EN, + MC13783_PWRCTRL_VBKUP_DISABLE); + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP2_AUTO_EN); + + if (VBKUP1_EN != false) { + if (pc_config->vhold_voltage > 3 + || pc_config->vhold_voltage < 0) { + return PMIC_PARAMETER_ERROR; + } else { + + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP1, + pc_config->vhold_voltage); + } + } + if (VBKUP2_EN != false) { + if (pc_config->vhold_voltage > 3 + || pc_config->vhold_voltage < 0) { + return PMIC_PARAMETER_ERROR; + } else { + pwrctrl_val_reg0 |= BITFVAL(MC13783_PWRCTRL_VBKUP2, + pc_config->vhold_voltage2); + } + } + pwrctrl_mask_reg0 |= BITFMASK(MC13783_PWRCTRL_VBKUP1) | + BITFMASK(MC13783_PWRCTRL_VBKUP2); + + if (pc_config->mem_allon != false) { + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_ALLON, + MC13783_PWRCTRL_MEM_ALLON_ENABLE); + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_TMR, + pc_config->mem_timer); + } else { + pwrctrl_val_reg1 |= BITFVAL(MC13783_PWRCTRL_MEM_ALLON, + MC13783_PWRCTRL_MEM_ALLON_DISABLE); + } + pwrctrl_mask_reg1 |= BITFMASK(MC13783_PWRCTRL_MEM_ALLON) | + BITFMASK(MC13783_PWRCTRL_MEM_TMR); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, + pwrctrl_val_reg0, pwrctrl_mask_reg0)); + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_1, + pwrctrl_val_reg1, pwrctrl_mask_reg1)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives the power control configuration. + * + * @param pc_config pointer to power control configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_pc_config(t_pc_config *pc_config) +{ + unsigned int pwrctrl_val_reg0 = 0; + unsigned int pwrctrl_val_reg1 = 0; + + if (pc_config == NULL) { + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0, + &pwrctrl_val_reg0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_1, + &pwrctrl_val_reg1, PMIC_ALL_BITS)); + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_PCEN) + == MC13783_PWRCTRL_PCEN_ENABLE) { + pc_config->pc_enable = true; + pc_config->pc_timer = BITFEXT(pwrctrl_val_reg1, + MC13783_PWRCTRL_PCT); + + } else { + pc_config->pc_enable = false; + pc_config->pc_timer = 0; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_PC_COUNT_EN) + == MC13783_PWRCTRL_PCEN_ENABLE) { + pc_config->pc_count_enable = true; + pc_config->pc_count = BITFEXT(pwrctrl_val_reg1, + MC13783_PWRCTRL_PC_COUNT); + pc_config->pc_max_count = BITFEXT(pwrctrl_val_reg1, + MC13783_PWRCTRL_PC_MAX_CNT); + } else { + pc_config->pc_count_enable = false; + pc_config->pc_count = 0; + pc_config->pc_max_count = 0; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_WARM_EN) + == MC13783_PWRCTRL_WARM_EN_ENABLE) { + pc_config->warm_enable = true; + } else { + pc_config->warm_enable = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_USER_OFF_PC) + == MC13783_PWRCTRL_USER_OFF_PC_ENABLE) { + pc_config->user_off_pc = true; + } else { + pc_config->user_off_pc = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_32OUT_USER_OFF) + == MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE) { + pc_config->clk_32k_user_off = true; + } else { + pc_config->clk_32k_user_off = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_32OUT_EN) + == MC13783_PWRCTRL_32OUT_EN_ENABLE) { + pc_config->clk_32k_enable = true; + } else { + pc_config->clk_32k_enable = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP1_AUTO_EN) + == MC13783_PWRCTRL_VBKUP_ENABLE) { + pc_config->auto_en_vbkup1 = true; + } else { + pc_config->auto_en_vbkup1 = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP2_AUTO_EN) + == MC13783_PWRCTRL_VBKUP_ENABLE) { + pc_config->auto_en_vbkup2 = true; + } else { + pc_config->auto_en_vbkup2 = false; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP1_EN) + == MC13783_PWRCTRL_VBKUP_ENABLE) { + pc_config->en_vbkup1 = true; + pc_config->vhold_voltage = BITFEXT(pwrctrl_val_reg0, + MC13783_PWRCTRL_VBKUP1); + } else { + pc_config->en_vbkup1 = false; + pc_config->vhold_voltage = 0; + } + + if (BITFEXT(pwrctrl_val_reg0, MC13783_PWRCTRL_VBKUP2_EN) + == MC13783_PWRCTRL_VBKUP_ENABLE) { + pc_config->en_vbkup2 = true; + pc_config->vhold_voltage2 = BITFEXT(pwrctrl_val_reg0, + MC13783_PWRCTRL_VBKUP2); + } else { + pc_config->en_vbkup2 = false; + pc_config->vhold_voltage2 = 0; + } + + if (BITFEXT(pwrctrl_val_reg1, MC13783_PWRCTRL_MEM_ALLON) == + MC13783_PWRCTRL_MEM_ALLON_ENABLE) { + pc_config->mem_allon = true; + pc_config->mem_timer = BITFEXT(pwrctrl_val_reg1, + MC13783_PWRCTRL_MEM_TMR); + } else { + pc_config->mem_allon = false; + pc_config->mem_timer = 0; + } + + return PMIC_SUCCESS; +} + +/*! + * This function turns on a regulator. + * + * @param regulator The regulator to be truned on. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_on(t_pmic_regulator regulator) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_PLL: + reg_val = BITFVAL(MC13783_SWCTRL_PLL_EN, + MC13783_SWCTRL_PLL_EN_ENABLE); + reg_mask = BITFMASK(MC13783_SWCTRL_PLL_EN); + reg = REG_SWITCHERS_4; + break; + case SW_SW3: + reg_val = BITFVAL(MC13783_SWCTRL_SW3_EN, + MC13783_SWCTRL_SW3_EN_ENABLE); + reg_mask = BITFMASK(MC13783_SWCTRL_SW3_EN); + reg = REG_SWITCHERS_5; + break; + case REGU_VAUDIO: + reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_EN, + MC13783_REGCTRL_VAUDIO_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOHI: + reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_EN, + MC13783_REGCTRL_VIOHI_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOLO: + reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_EN, + MC13783_REGCTRL_VIOLO_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VDIG_EN, + MC13783_REGCTRL_VDIG_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VGEN: + reg_val = BITFVAL(MC13783_REGCTRL_VGEN_EN, + MC13783_REGCTRL_VGEN_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_EN, + MC13783_REGCTRL_VRFDIG_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFREF: + reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_EN, + MC13783_REGCTRL_VRFREF_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFCP: + reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_EN, + MC13783_REGCTRL_VRFCP_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VSIM: + reg_val = BITFVAL(MC13783_REGCTRL_VSIM_EN, + MC13783_REGCTRL_VSIM_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VESIM: + reg_val = BITFVAL(MC13783_REGCTRL_VESIM_EN, + MC13783_REGCTRL_VESIM_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VCAM: + reg_val = BITFVAL(MC13783_REGCTRL_VCAM_EN, + MC13783_REGCTRL_VCAM_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRFBG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_EN, + MC13783_REGCTRL_VRFBG_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VVIB: + reg_val = BITFVAL(MC13783_REGCTRL_VVIB_EN, + MC13783_REGCTRL_VVIB_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VVIB_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF1: + reg_val = BITFVAL(MC13783_REGCTRL_VRF1_EN, + MC13783_REGCTRL_VRF1_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF2: + reg_val = BITFVAL(MC13783_REGCTRL_VRF2_EN, + MC13783_REGCTRL_VRF2_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC1: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_EN, + MC13783_REGCTRL_VMMC1_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC2: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_EN, + MC13783_REGCTRL_VMMC2_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_GPO1: + reg_val = BITFVAL(MC13783_REGCTRL_GPO1_EN, + MC13783_REGCTRL_GPO1_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO1_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO2: + reg_val = BITFVAL(MC13783_REGCTRL_GPO2_EN, + MC13783_REGCTRL_GPO2_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO2_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO3: + reg_val = BITFVAL(MC13783_REGCTRL_GPO3_EN, + MC13783_REGCTRL_GPO3_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO3_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO4: + reg_val = BITFVAL(MC13783_REGCTRL_GPO4_EN, + MC13783_REGCTRL_GPO4_EN_ENABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO4_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function turns off a regulator. + * + * @param regulator The regulator to be truned off. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_off(t_pmic_regulator regulator) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_PLL: + reg_val = BITFVAL(MC13783_SWCTRL_PLL_EN, + MC13783_SWCTRL_PLL_EN_DISABLE); + reg_mask = BITFMASK(MC13783_SWCTRL_PLL_EN); + reg = REG_SWITCHERS_4; + break; + case SW_SW3: + reg_val = BITFVAL(MC13783_SWCTRL_SW3_EN, + MC13783_SWCTRL_SW3_EN_DISABLE); + reg_mask = BITFMASK(MC13783_SWCTRL_SW3_EN); + reg = REG_SWITCHERS_5; + break; + case REGU_VAUDIO: + reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_EN, + MC13783_REGCTRL_VAUDIO_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOHI: + reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_EN, + MC13783_REGCTRL_VIOHI_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOLO: + reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_EN, + MC13783_REGCTRL_VIOLO_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VDIG_EN, + MC13783_REGCTRL_VDIG_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VGEN: + reg_val = BITFVAL(MC13783_REGCTRL_VGEN_EN, + MC13783_REGCTRL_VGEN_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_EN, + MC13783_REGCTRL_VRFDIG_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFREF: + reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_EN, + MC13783_REGCTRL_VRFREF_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFCP: + reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_EN, + MC13783_REGCTRL_VRFCP_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_EN); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VSIM: + reg_val = BITFVAL(MC13783_REGCTRL_VSIM_EN, + MC13783_REGCTRL_VSIM_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VESIM: + reg_val = BITFVAL(MC13783_REGCTRL_VESIM_EN, + MC13783_REGCTRL_VESIM_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VCAM: + reg_val = BITFVAL(MC13783_REGCTRL_VCAM_EN, + MC13783_REGCTRL_VCAM_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRFBG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_EN, + MC13783_REGCTRL_VRFBG_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VVIB: + reg_val = BITFVAL(MC13783_REGCTRL_VVIB_EN, + MC13783_REGCTRL_VVIB_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VVIB_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF1: + reg_val = BITFVAL(MC13783_REGCTRL_VRF1_EN, + MC13783_REGCTRL_VRF1_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF2: + reg_val = BITFVAL(MC13783_REGCTRL_VRF2_EN, + MC13783_REGCTRL_VRF2_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC1: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_EN, + MC13783_REGCTRL_VMMC1_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC2: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_EN, + MC13783_REGCTRL_VMMC2_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_EN); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_GPO1: + reg_val = BITFVAL(MC13783_REGCTRL_GPO1_EN, + MC13783_REGCTRL_GPO1_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO1_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO2: + reg_val = BITFVAL(MC13783_REGCTRL_GPO2_EN, + MC13783_REGCTRL_GPO2_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO2_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO3: + reg_val = BITFVAL(MC13783_REGCTRL_GPO3_EN, + MC13783_REGCTRL_GPO3_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO3_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + case REGU_GPO4: + reg_val = BITFVAL(MC13783_REGCTRL_GPO4_EN, + MC13783_REGCTRL_GPO4_EN_DISABLE); + reg_mask = BITFMASK(MC13783_REGCTRL_GPO4_EN); + reg = REG_POWER_MISCELLANEOUS; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function sets the regulator output voltage. + * + * @param regulator The regulator to be configured. + * @param voltage The regulator output voltage. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_voltage(t_pmic_regulator regulator, + t_regulator_voltage voltage) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + if ((voltage.sw1a < SW1A_0_9V) || (voltage.sw1a > SW1A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1A, voltage.sw1a); + reg_mask = BITFMASK(MC13783_SWSET_SW1A); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + if ((voltage.sw1b < SW1B_0_9V) || (voltage.sw1b > SW1B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1B, voltage.sw1b); + reg_mask = BITFMASK(MC13783_SWSET_SW1B); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + if ((voltage.sw2a < SW2A_0_9V) || (voltage.sw2a > SW2A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2A, voltage.sw1a); + reg_mask = BITFMASK(MC13783_SWSET_SW2A); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + if ((voltage.sw2b < SW2B_0_9V) || (voltage.sw2b > SW2B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2B, voltage.sw2b); + reg_mask = BITFMASK(MC13783_SWSET_SW1A); + reg = REG_SWITCHERS_3; + break; + case SW_SW3: + if (voltage.sw3 != SW3_5V) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW3, voltage.sw3); + reg_mask = BITFMASK(MC13783_SWSET_SW3); + reg = REG_SWITCHERS_5; + break; + case REGU_VIOLO: + if ((voltage.violo < VIOLO_1_2V) || + (voltage.violo > VIOLO_1_8V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VIOLO, voltage.violo); + reg_mask = BITFMASK(MC13783_REGSET_VIOLO); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VDIG: + if ((voltage.vdig < VDIG_1_2V) || (voltage.vdig > VDIG_1_8V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VDIG, voltage.vdig); + reg_mask = BITFMASK(MC13783_REGSET_VDIG); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VGEN: + if ((voltage.vgen < VGEN_1_2V) || (voltage.vgen > VGEN_2_4V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VGEN, voltage.vgen); + reg_mask = BITFMASK(MC13783_REGSET_VGEN); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VRFDIG: + if ((voltage.vrfdig < VRFDIG_1_2V) || + (voltage.vrfdig > VRFDIG_1_875V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRFDIG, voltage.vrfdig); + reg_mask = BITFMASK(MC13783_REGSET_VRFDIG); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VRFREF: + if ((voltage.vrfref < VRFREF_2_475V) || + (voltage.vrfref > VRFREF_2_775V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRFREF, voltage.vrfref); + reg_mask = BITFMASK(MC13783_REGSET_VRFREF); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VRFCP: + if ((voltage.vrfcp < VRFCP_2_7V) || + (voltage.vrfcp > VRFCP_2_775V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRFCP, voltage.vrfcp); + reg_mask = BITFMASK(MC13783_REGSET_VRFCP); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VSIM: + if ((voltage.vsim < VSIM_1_8V) || (voltage.vsim > VSIM_2_9V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VSIM, voltage.vsim); + reg_mask = BITFMASK(MC13783_REGSET_VSIM); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VESIM: + if ((voltage.vesim < VESIM_1_8V) || + (voltage.vesim > VESIM_2_9V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VESIM, voltage.vesim); + reg_mask = BITFMASK(MC13783_REGSET_VESIM); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VCAM: + if ((voltage.vcam < VCAM_1_5V) || (voltage.vcam > VCAM_3V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VCAM, voltage.vcam); + reg_mask = BITFMASK(MC13783_REGSET_VCAM); + reg = REG_REGULATOR_SETTING_0; + break; + case REGU_VVIB: + if ((voltage.vvib < VVIB_1_3V) || (voltage.vvib > VVIB_3V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VVIB, voltage.vvib); + reg_mask = BITFMASK(MC13783_REGSET_VVIB); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VRF1: + if ((voltage.vrf1 < VRF1_1_5V) || (voltage.vrf1 > VRF1_2_775V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRF1, voltage.vrf1); + reg_mask = BITFMASK(MC13783_REGSET_VRF1); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VRF2: + if ((voltage.vrf2 < VRF2_1_5V) || (voltage.vrf2 > VRF2_2_775V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VRF2, voltage.vrf2); + reg_mask = BITFMASK(MC13783_REGSET_VRF2); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VMMC1: + if ((voltage.vmmc1 < VMMC1_1_6V) || (voltage.vmmc1 > VMMC1_3V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VMMC1, voltage.vmmc1); + reg_mask = BITFMASK(MC13783_REGSET_VMMC1); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VMMC2: + if ((voltage.vmmc2 < VMMC2_1_6V) || (voltage.vmmc2 > VMMC2_3V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGSET_VMMC2, voltage.vmmc2); + reg_mask = BITFMASK(MC13783_REGSET_VMMC2); + reg = REG_REGULATOR_SETTING_1; + break; + case REGU_VAUDIO: + case REGU_VIOHI: + case REGU_VRFBG: + case REGU_GPO1: + case REGU_GPO2: + case REGU_GPO3: + case REGU_GPO4: + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function retrives the regulator output voltage. + * + * @param regulator The regulator to be truned off. + * @param voltage Pointer to regulator output voltage. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_voltage(t_pmic_regulator regulator, + t_regulator_voltage *voltage) +{ + unsigned int reg_val = 0; + + if (regulator == SW_SW1A) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_0, + ®_val, PMIC_ALL_BITS)); + } else if (regulator == SW_SW1B) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_1, + ®_val, PMIC_ALL_BITS)); + } else if (regulator == SW_SW2A) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_2, + ®_val, PMIC_ALL_BITS)); + } else if (regulator == SW_SW2B) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_3, + ®_val, PMIC_ALL_BITS)); + } else if (regulator == SW_SW3) { + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_5, + ®_val, PMIC_ALL_BITS)); + } else if ((regulator == REGU_VIOLO) || (regulator == REGU_VDIG) || + (regulator == REGU_VGEN) || + (regulator == REGU_VRFDIG) || + (regulator == REGU_VRFREF) || + (regulator == REGU_VRFCP) || + (regulator == REGU_VSIM) || + (regulator == REGU_VESIM) || (regulator == REGU_VCAM)) { + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®_val, PMIC_ALL_BITS)); + } else if ((regulator == REGU_VVIB) || (regulator == REGU_VRF1) || + (regulator == REGU_VRF2) || + (regulator == REGU_VMMC1) || (regulator == REGU_VMMC2)) { + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1, + ®_val, PMIC_ALL_BITS)); + } + + switch (regulator) { + case SW_SW1A: + voltage->sw1a = BITFEXT(reg_val, MC13783_SWSET_SW1A); + break; + case SW_SW1B: + voltage->sw1b = BITFEXT(reg_val, MC13783_SWSET_SW1B); + break; + case SW_SW2A: + voltage->sw2a = BITFEXT(reg_val, MC13783_SWSET_SW2A); + break; + case SW_SW2B: + voltage->sw2b = BITFEXT(reg_val, MC13783_SWSET_SW2B); + break; + case SW_SW3: + voltage->sw3 = BITFEXT(reg_val, MC13783_SWSET_SW3); + break; + case REGU_VIOLO: + voltage->violo = BITFEXT(reg_val, MC13783_REGSET_VIOLO); + break; + case REGU_VDIG: + voltage->vdig = BITFEXT(reg_val, MC13783_REGSET_VDIG); + break; + case REGU_VGEN: + voltage->vgen = BITFEXT(reg_val, MC13783_REGSET_VGEN); + break; + case REGU_VRFDIG: + voltage->vrfdig = BITFEXT(reg_val, MC13783_REGSET_VRFDIG); + break; + case REGU_VRFREF: + voltage->vrfref = BITFEXT(reg_val, MC13783_REGSET_VRFREF); + break; + case REGU_VRFCP: + voltage->vrfcp = BITFEXT(reg_val, MC13783_REGSET_VRFCP); + break; + case REGU_VSIM: + voltage->vsim = BITFEXT(reg_val, MC13783_REGSET_VSIM); + break; + case REGU_VESIM: + voltage->vesim = BITFEXT(reg_val, MC13783_REGSET_VESIM); + break; + case REGU_VCAM: + voltage->vcam = BITFEXT(reg_val, MC13783_REGSET_VCAM); + break; + case REGU_VVIB: + voltage->vvib = BITFEXT(reg_val, MC13783_REGSET_VVIB); + break; + case REGU_VRF1: + voltage->vrf1 = BITFEXT(reg_val, MC13783_REGSET_VRF1); + break; + case REGU_VRF2: + voltage->vrf2 = BITFEXT(reg_val, MC13783_REGSET_VRF2); + break; + case REGU_VMMC1: + voltage->vmmc1 = BITFEXT(reg_val, MC13783_REGSET_VMMC1); + break; + case REGU_VMMC2: + voltage->vmmc2 = BITFEXT(reg_val, MC13783_REGSET_VMMC2); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the DVS voltage + * + * @param regulator The regulator to be configured. + * @param dvs The switch Dynamic Voltage Scaling + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_dvs(t_pmic_regulator regulator, + t_regulator_voltage dvs) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + if ((dvs.sw1a < SW1A_0_9V) || (dvs.sw1a > SW1A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1A_DVS, dvs.sw1a); + reg_mask = BITFMASK(MC13783_SWSET_SW1A_DVS); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + if ((dvs.sw1b < SW1B_0_9V) || (dvs.sw1b > SW1B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1B_DVS, dvs.sw1b); + reg_mask = BITFMASK(MC13783_SWSET_SW1B_DVS); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + if ((dvs.sw2a < SW2A_0_9V) || (dvs.sw2a > SW2A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2A_DVS, dvs.sw2a); + reg_mask = BITFMASK(MC13783_SWSET_SW2A_DVS); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + if ((dvs.sw2b < SW2B_0_9V) || (dvs.sw2b > SW2B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2B_DVS, dvs.sw2b); + reg_mask = BITFMASK(MC13783_SWSET_SW2B_DVS); + reg = REG_SWITCHERS_3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the DVS voltage + * + * @param regulator The regulator to be handled. + * @param dvs The switch Dynamic Voltage Scaling + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_dvs(t_pmic_regulator regulator, + t_regulator_voltage *dvs) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWSET_SW1A_DVS); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWSET_SW1B_DVS); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWSET_SW2A_DVS); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWSET_SW2B_DVS); + reg = REG_SWITCHERS_3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *dvs = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW1A_DVS); + break; + case SW_SW1B: + *dvs = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW1B_DVS); + break; + case SW_SW2A: + *dvs = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW2A_DVS); + break; + case SW_SW2B: + *dvs = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW2B_DVS); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the standiby voltage + * + * @param regulator The regulator to be configured. + * @param stby The switch standby voltage + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_stby(t_pmic_regulator regulator, + t_regulator_voltage stby) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + if ((stby.sw1a < SW1A_0_9V) || (stby.sw1a > SW1A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1A_STDBY, stby.sw1a); + reg_mask = BITFMASK(MC13783_SWSET_SW1A_STDBY); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + if ((stby.sw1b < SW1B_0_9V) || (stby.sw1b > SW1B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW1B_STDBY, stby.sw1b); + reg_mask = BITFMASK(MC13783_SWSET_SW1B_STDBY); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + if ((stby.sw2a < SW2A_0_9V) || (stby.sw2a > SW2A_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2A_STDBY, stby.sw2a); + reg_mask = BITFMASK(MC13783_SWSET_SW2A_STDBY); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + if ((stby.sw2b < SW2B_0_9V) || (stby.sw2b > SW2B_2_2V)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWSET_SW2B_STDBY, stby.sw2b); + reg_mask = BITFMASK(MC13783_SWSET_SW2B_STDBY); + reg = REG_SWITCHERS_3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the standiby voltage + * + * @param regulator The regulator to be handled. + * @param stby The switch standby voltage + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_stby(t_pmic_regulator regulator, + t_regulator_voltage *stby) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWSET_SW1A_STDBY); + reg = REG_SWITCHERS_0; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWSET_SW1B_STDBY); + reg = REG_SWITCHERS_1; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWSET_SW2A_STDBY); + reg = REG_SWITCHERS_2; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWSET_SW2B_STDBY); + reg = REG_SWITCHERS_3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *stby = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW1A_STDBY); + break; + case SW_SW1B: + *stby = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW1B_STDBY); + break; + case SW_SW2A: + *stby = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW2A_STDBY); + break; + case SW_SW2B: + *stby = (t_regulator_voltage) BITFEXT(reg_val, + MC13783_SWSET_SW2B_STDBY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the switchers mode. + * + * @param regulator The regulator to be configured. + * @param mode The switcher mode + * @param stby Switch between main and standby. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_mode(t_pmic_regulator regulator, + t_regulator_sw_mode mode, bool stby) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + unsigned int l_mode; + + if (mode == SYNC_RECT) { + l_mode = MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN; + } else if (mode == NO_PULSE_SKIP) { + l_mode = MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN; + } else if (mode == PULSE_SKIP) { + l_mode = MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN; + } else if (mode == LOW_POWER) { + l_mode = MC13783_SWCTRL_SW_MODE_LOW_POWER_EN; + } else { + return PMIC_PARAMETER_ERROR; + } + + switch (regulator) { + case SW_SW1A: + if (stby) { + reg_val = + BITFVAL(MC13783_SWCTRL_SW1A_STBY_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_STBY_MODE); + } else { + reg_val = BITFVAL(MC13783_SWCTRL_SW1A_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_MODE); + } + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + if (stby) { + reg_val = + BITFVAL(MC13783_SWCTRL_SW1B_STBY_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_STBY_MODE); + } else { + reg_val = BITFVAL(MC13783_SWCTRL_SW1B_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_MODE); + } + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + if (stby) { + reg_val = + BITFVAL(MC13783_SWCTRL_SW2A_STBY_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_STBY_MODE); + } else { + reg_val = BITFVAL(MC13783_SWCTRL_SW2A_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_MODE); + } + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + if (stby) { + reg_val = + BITFVAL(MC13783_SWCTRL_SW2B_STBY_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_STBY_MODE); + } else { + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_MODE, l_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_MODE); + } + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the switchers mode. + * + * @param regulator The regulator to be handled. + * @param mode The switcher mode. + * @param stby Switch between main and standby. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_mode(t_pmic_regulator regulator, + t_regulator_sw_mode *mode, bool stby) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg = 0; + unsigned int l_mode = 0; + + switch (regulator) { + case SW_SW1A: + if (stby) { + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_STBY_MODE); + } else { + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_MODE); + } + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + if (stby) { + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_STBY_MODE); + } else { + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_MODE); + } + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + if (stby) { + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_STBY_MODE); + } else { + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_MODE); + } + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + if (stby) { + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_STBY_MODE); + } else { + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_MODE); + } + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + if (stby) { + l_mode = + BITFEXT(reg_val, MC13783_SWCTRL_SW1A_STBY_MODE); + } else { + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_MODE); + } + break; + case SW_SW1B: + if (stby) { + l_mode = + BITFEXT(reg_val, MC13783_SWCTRL_SW1B_STBY_MODE); + } else { + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_MODE); + } + break; + case SW_SW2A: + if (stby) { + l_mode = + BITFEXT(reg_val, MC13783_SWCTRL_SW2A_STBY_MODE); + } else { + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_MODE); + } + break; + case SW_SW2B: + if (stby) { + l_mode = + BITFEXT(reg_val, MC13783_SWCTRL_SW2B_STBY_MODE); + } else { + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_MODE); + } + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (l_mode == MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN) { + *mode = SYNC_RECT; + } else if (l_mode == MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN) { + *mode = NO_PULSE_SKIP; + } else if (l_mode == MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN) { + *mode = PULSE_SKIP; + } else if (l_mode == MC13783_SWCTRL_SW_MODE_LOW_POWER_EN) { + *mode = LOW_POWER; + } else { + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the switch dvs speed + * + * @param regulator The regulator to be configured. + * @param speed The dvs speed. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_dvs_speed(t_pmic_regulator regulator, + t_switcher_dvs_speed speed) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + if (speed > 3 || speed < 0) { + return PMIC_PARAMETER_ERROR; + } + + switch (regulator) { + case SW_SW1A: + reg_val = BITFVAL(MC13783_SWCTRL_SW1A_DVS_SPEED, speed); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_DVS_SPEED); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_DVS_SPEED, speed); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_DVS_SPEED); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_val = BITFVAL(MC13783_SWCTRL_SW2A_DVS_SPEED, speed); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_DVS_SPEED); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_DVS_SPEED, speed); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_DVS_SPEED); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the switch dvs speed + * + * @param regulator The regulator to be handled. + * @param speed The dvs speed. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_dvs_speed(t_pmic_regulator regulator, + t_switcher_dvs_speed *speed) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_DVS_SPEED); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_DVS_SPEED); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_DVS_SPEED); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_DVS_SPEED); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *speed = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_DVS_SPEED); + break; + case SW_SW1B: + *speed = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_DVS_SPEED); + break; + case SW_SW2A: + *speed = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_DVS_SPEED); + break; + case SW_SW2B: + *speed = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_DVS_SPEED); + break; + default: + break; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the switch panic mode + * + * @param regulator The regulator to be configured. + * @param panic_mode Enable or disable panic mode + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_panic_mode(t_pmic_regulator regulator, + bool panic_mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_val = BITFVAL(MC13783_SWCTRL_SW1A_PANIC_MODE, panic_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_PANIC_MODE); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_PANIC_MODE, panic_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_PANIC_MODE); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_val = BITFVAL(MC13783_SWCTRL_SW2A_PANIC_MODE, panic_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_PANIC_MODE); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_PANIC_MODE, panic_mode); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_PANIC_MODE); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the switch panic mode + * + * @param regulator The regulator to be handled + * @param panic_mode Enable or disable panic mode + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_panic_mode(t_pmic_regulator regulator, + bool *panic_mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_PANIC_MODE); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_PANIC_MODE); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_PANIC_MODE); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_PANIC_MODE); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_PANIC_MODE); + break; + case SW_SW1B: + *panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW1B_PANIC_MODE); + break; + case SW_SW2A: + *panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_PANIC_MODE); + break; + case SW_SW2B: + *panic_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_PANIC_MODE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the switch softstart mode + * + * @param regulator The regulator to be configured. + * @param softstart Enable or disable softstart. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_softstart(t_pmic_regulator regulator, + bool softstart) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_val = BITFVAL(MC13783_SWCTRL_SW1A_SOFTSTART, softstart); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_SOFTSTART); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_SOFTSTART, softstart); + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_SOFTSTART); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_val = BITFVAL(MC13783_SWCTRL_SW2A_SOFTSTART, softstart); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_SOFTSTART); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_val = BITFVAL(MC13783_SWCTRL_SW2B_SOFTSTART, softstart); + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_SOFTSTART); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the switch softstart mode + * + * @param regulator The regulator to be handled + * @param softstart Enable or disable softstart. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_softstart(t_pmic_regulator regulator, + bool *softstart) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + + switch (regulator) { + case SW_SW1A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1A_SOFTSTART); + reg = REG_SWITCHERS_4; + break; + case SW_SW1B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW1B_SOFTSTART); + reg = REG_SWITCHERS_4; + break; + case SW_SW2A: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2A_SOFTSTART); + reg = REG_SWITCHERS_5; + break; + case SW_SW2B: + reg_mask = BITFMASK(MC13783_SWCTRL_SW2B_SOFTSTART); + reg = REG_SWITCHERS_5; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW1A: + *softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW1A_SOFTSTART); + break; + case SW_SW1B: + *softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_SOFTSTART); + break; + case SW_SW2A: + *softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2A_SOFTSTART); + break; + case SW_SW2B: + *softstart = BITFEXT(reg_val, MC13783_SWCTRL_SW2B_SOFTSTART); + break; + default: + break; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the PLL multiplication factor + * + * @param regulator The regulator to be configured. + * @param factor The multiplication factor. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_set_factor(t_pmic_regulator regulator, + t_switcher_factor factor) +{ + unsigned int reg_val = 0, reg_mask = 0; + + if (regulator != SW_PLL) { + return PMIC_PARAMETER_ERROR; + } + if (factor < FACTOR_28 || factor > FACTOR_35) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_SWCTRL_PLL_FACTOR, factor); + reg_mask = BITFMASK(MC13783_SWCTRL_PLL_FACTOR); + + CHECK_ERROR(pmic_write_reg(REG_SWITCHERS_4, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the PLL multiplication factor + * + * @param regulator The regulator to be handled + * @param factor The multiplication factor. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_switcher_get_factor(t_pmic_regulator regulator, + t_switcher_factor *factor) +{ + unsigned int reg_val = 0, reg_mask = 0; + + if (regulator != SW_PLL) { + return PMIC_PARAMETER_ERROR; + } + reg_mask = BITFMASK(MC13783_SWCTRL_PLL_FACTOR); + + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_4, ®_val, reg_mask)); + + *factor = BITFEXT(reg_val, MC13783_SWCTRL_PLL_FACTOR); + + return PMIC_SUCCESS; +} + +/*! + * This function enables or disables low power mode. + * + * @param regulator The regulator to be configured. + * @param lp_mode Select nominal or low power mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_lp_mode(t_pmic_regulator regulator, + t_regulator_lp_mode lp_mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + unsigned int l_mode, l_stby; + + if (lp_mode == LOW_POWER_DISABLED) { + l_mode = MC13783_REGTRL_LP_MODE_DISABLE; + l_stby = MC13783_REGTRL_STBY_MODE_DISABLE; + } else if (lp_mode == LOW_POWER_CTRL_BY_PIN) { + l_mode = MC13783_REGTRL_LP_MODE_DISABLE; + l_stby = MC13783_REGTRL_STBY_MODE_ENABLE; + } else if (lp_mode == LOW_POWER_EN) { + l_mode = MC13783_REGTRL_LP_MODE_ENABLE; + l_stby = MC13783_REGTRL_STBY_MODE_DISABLE; + } else if (lp_mode == LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN) { + l_mode = MC13783_REGTRL_LP_MODE_ENABLE; + l_stby = MC13783_REGTRL_STBY_MODE_ENABLE; + } else { + return PMIC_PARAMETER_ERROR; + } + + switch (regulator) { + case SW_SW3: + reg_val = BITFVAL(MC13783_SWCTRL_SW3_MODE, l_mode) | + BITFVAL(MC13783_SWCTRL_SW3_STBY, l_stby); + reg_mask = BITFMASK(MC13783_SWCTRL_SW3_MODE) | + BITFMASK(MC13783_SWCTRL_SW3_STBY); + reg = REG_SWITCHERS_5; + break; + case REGU_VAUDIO: + reg_val = BITFVAL(MC13783_REGCTRL_VAUDIO_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VAUDIO_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_MODE) | + BITFMASK(MC13783_REGCTRL_VAUDIO_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOHI: + reg_val = BITFVAL(MC13783_REGCTRL_VIOHI_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VIOHI_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_MODE) | + BITFMASK(MC13783_REGCTRL_VIOHI_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOLO: + reg_val = BITFVAL(MC13783_REGCTRL_VIOLO_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VIOLO_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_MODE) | + BITFMASK(MC13783_REGCTRL_VIOLO_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VDIG_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VDIG_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_MODE) | + BITFMASK(MC13783_REGCTRL_VDIG_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VGEN: + reg_val = BITFVAL(MC13783_REGCTRL_VGEN_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VGEN_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_MODE) | + BITFMASK(MC13783_REGCTRL_VGEN_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFDIG: + reg_val = BITFVAL(MC13783_REGCTRL_VRFDIG_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRFDIG_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_MODE) | + BITFMASK(MC13783_REGCTRL_VRFDIG_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFREF: + reg_val = BITFVAL(MC13783_REGCTRL_VRFREF_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRFREF_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_MODE) | + BITFMASK(MC13783_REGCTRL_VRFREF_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFCP: + reg_val = BITFVAL(MC13783_REGCTRL_VRFCP_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRFCP_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_MODE) | + BITFMASK(MC13783_REGCTRL_VRFCP_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VSIM: + reg_val = BITFVAL(MC13783_REGCTRL_VSIM_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VSIM_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_MODE) | + BITFMASK(MC13783_REGCTRL_VSIM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VESIM: + reg_val = BITFVAL(MC13783_REGCTRL_VESIM_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VESIM_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_MODE) | + BITFMASK(MC13783_REGCTRL_VESIM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VCAM: + reg_val = BITFVAL(MC13783_REGCTRL_VCAM_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VCAM_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_MODE) | + BITFMASK(MC13783_REGCTRL_VCAM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRFBG: + if ((lp_mode == LOW_POWER) || + (lp_mode == LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN)) { + return PMIC_PARAMETER_ERROR; + } + reg_val = BITFVAL(MC13783_REGCTRL_VRFBG_STBY, l_mode); + reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF1: + reg_val = BITFVAL(MC13783_REGCTRL_VRF1_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRF1_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_MODE) | + BITFMASK(MC13783_REGCTRL_VRF1_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF2: + reg_val = BITFVAL(MC13783_REGCTRL_VRF2_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VRF2_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_MODE) | + BITFMASK(MC13783_REGCTRL_VRF2_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC1: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC1_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VMMC1_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_MODE) | + BITFMASK(MC13783_REGCTRL_VMMC1_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC2: + reg_val = BITFVAL(MC13783_REGCTRL_VMMC2_MODE, l_mode) | + BITFVAL(MC13783_REGCTRL_VMMC2_STBY, l_stby); + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_MODE) | + BITFMASK(MC13783_REGCTRL_VMMC2_STBY); + reg = REG_REGULATOR_MODE_1; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(reg, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets low power mode. + * + * @param regulator The regulator to be handled + * @param lp_mode Select nominal or low power mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_lp_mode(t_pmic_regulator regulator, + t_regulator_lp_mode *lp_mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int reg; + unsigned int l_mode, l_stby; + + switch (regulator) { + case SW_SW3: + reg_mask = BITFMASK(MC13783_SWCTRL_SW3_MODE) | + BITFMASK(MC13783_SWCTRL_SW3_STBY); + reg = REG_SWITCHERS_5; + break; + case REGU_VAUDIO: + reg_mask = BITFMASK(MC13783_REGCTRL_VAUDIO_MODE) | + BITFMASK(MC13783_REGCTRL_VAUDIO_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOHI: + reg_mask = BITFMASK(MC13783_REGCTRL_VIOHI_MODE) | + BITFMASK(MC13783_REGCTRL_VIOHI_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VIOLO: + reg_mask = BITFMASK(MC13783_REGCTRL_VIOLO_MODE) | + BITFMASK(MC13783_REGCTRL_VIOLO_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VDIG: + reg_mask = BITFMASK(MC13783_REGCTRL_VDIG_MODE) | + BITFMASK(MC13783_REGCTRL_VDIG_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VGEN: + reg_mask = BITFMASK(MC13783_REGCTRL_VGEN_MODE) | + BITFMASK(MC13783_REGCTRL_VGEN_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFDIG: + reg_mask = BITFMASK(MC13783_REGCTRL_VRFDIG_MODE) | + BITFMASK(MC13783_REGCTRL_VRFDIG_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFREF: + reg_mask = BITFMASK(MC13783_REGCTRL_VRFREF_MODE) | + BITFMASK(MC13783_REGCTRL_VRFREF_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VRFCP: + reg_mask = BITFMASK(MC13783_REGCTRL_VRFCP_MODE) | + BITFMASK(MC13783_REGCTRL_VRFCP_STBY); + reg = REG_REGULATOR_MODE_0; + break; + case REGU_VSIM: + reg_mask = BITFMASK(MC13783_REGCTRL_VSIM_MODE) | + BITFMASK(MC13783_REGCTRL_VSIM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VESIM: + reg_mask = BITFMASK(MC13783_REGCTRL_VESIM_MODE) | + BITFMASK(MC13783_REGCTRL_VESIM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VCAM: + reg_mask = BITFMASK(MC13783_REGCTRL_VCAM_MODE) | + BITFMASK(MC13783_REGCTRL_VCAM_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRFBG: + reg_mask = BITFMASK(MC13783_REGCTRL_VRFBG_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF1: + reg_mask = BITFMASK(MC13783_REGCTRL_VRF1_MODE) | + BITFMASK(MC13783_REGCTRL_VRF1_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VRF2: + reg_mask = BITFMASK(MC13783_REGCTRL_VRF2_MODE) | + BITFMASK(MC13783_REGCTRL_VRF2_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC1: + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC1_MODE) | + BITFMASK(MC13783_REGCTRL_VMMC1_STBY); + reg = REG_REGULATOR_MODE_1; + break; + case REGU_VMMC2: + reg_mask = BITFMASK(MC13783_REGCTRL_VMMC2_MODE) | + BITFMASK(MC13783_REGCTRL_VMMC2_STBY); + reg = REG_REGULATOR_MODE_1; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_val, reg_mask)); + + switch (regulator) { + case SW_SW3: + l_mode = BITFEXT(reg_val, MC13783_SWCTRL_SW3_MODE); + l_stby = BITFEXT(reg_val, MC13783_SWCTRL_SW3_STBY); + break; + case REGU_VAUDIO: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VAUDIO_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VAUDIO_STBY); + break; + case REGU_VIOHI: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VIOHI_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VIOHI_STBY); + break; + case REGU_VIOLO: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VIOLO_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VIOLO_STBY); + break; + case REGU_VDIG: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VDIG_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VDIG_STBY); + break; + case REGU_VGEN: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VGEN_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VGEN_STBY); + break; + case REGU_VRFDIG: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFDIG_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFDIG_STBY); + break; + case REGU_VRFREF: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFREF_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFREF_STBY); + break; + case REGU_VRFCP: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRFCP_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFCP_STBY); + break; + case REGU_VSIM: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VSIM_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VSIM_STBY); + break; + case REGU_VESIM: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VESIM_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VESIM_STBY); + break; + case REGU_VCAM: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VCAM_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VCAM_STBY); + break; + case REGU_VRFBG: + l_mode = MC13783_REGTRL_LP_MODE_DISABLE; + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRFBG_STBY); + break; + case REGU_VRF1: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRF1_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRF1_STBY); + break; + case REGU_VRF2: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VRF2_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VRF2_STBY); + break; + case REGU_VMMC1: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VMMC1_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VMMC1_STBY); + break; + case REGU_VMMC2: + l_mode = BITFEXT(reg_val, MC13783_REGCTRL_VMMC2_MODE); + l_stby = BITFEXT(reg_val, MC13783_REGCTRL_VMMC2_STBY); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if ((l_mode == MC13783_REGTRL_LP_MODE_DISABLE) && + (l_stby == MC13783_REGTRL_STBY_MODE_DISABLE)) { + *lp_mode = LOW_POWER_DISABLED; + } else if ((l_mode == MC13783_REGTRL_LP_MODE_DISABLE) && + (l_stby == MC13783_REGTRL_STBY_MODE_ENABLE)) { + *lp_mode = LOW_POWER_CTRL_BY_PIN; + } else if ((l_mode == MC13783_REGTRL_LP_MODE_ENABLE) && + (l_stby == MC13783_REGTRL_STBY_MODE_DISABLE)) { + *lp_mode = LOW_POWER_EN; + } else { + *lp_mode = LOW_POWER_AND_LOW_POWER_CTRL_BY_PIN; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the regulator configuration. + * + * @param regulator The regulator to be configured. + * @param config The regulator output configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_set_config(t_pmic_regulator regulator, + t_regulator_config *config) +{ + if (config == NULL) { + return PMIC_ERROR; + } + + switch (regulator) { + case SW_SW1A: + case SW_SW1B: + case SW_SW2A: + case SW_SW2B: + CHECK_ERROR(pmic_power_regulator_set_voltage + (regulator, config->voltage)); + CHECK_ERROR(pmic_power_switcher_set_dvs + (regulator, config->voltage_lvs)); + CHECK_ERROR(pmic_power_switcher_set_stby + (regulator, config->voltage_stby)); + CHECK_ERROR(pmic_power_switcher_set_mode + (regulator, config->mode, false)); + CHECK_ERROR(pmic_power_switcher_set_mode + (regulator, config->stby_mode, true)); + CHECK_ERROR(pmic_power_switcher_set_dvs_speed + (regulator, config->dvs_speed)); + CHECK_ERROR(pmic_power_switcher_set_panic_mode + (regulator, config->panic_mode)); + CHECK_ERROR(pmic_power_switcher_set_softstart + (regulator, config->softstart)); + break; + case SW_PLL: + CHECK_ERROR(pmic_power_switcher_set_factor + (regulator, config->factor)); + break; + case SW_SW3: + case REGU_VIOLO: + case REGU_VDIG: + case REGU_VGEN: + case REGU_VRFDIG: + case REGU_VRFREF: + case REGU_VRFCP: + case REGU_VSIM: + case REGU_VESIM: + case REGU_VCAM: + case REGU_VRF1: + case REGU_VRF2: + case REGU_VMMC1: + case REGU_VMMC2: + CHECK_ERROR(pmic_power_regulator_set_voltage + (regulator, config->voltage)); + CHECK_ERROR(pmic_power_regulator_set_lp_mode + (regulator, config->lp_mode)); + break; + case REGU_VVIB: + CHECK_ERROR(pmic_power_regulator_set_voltage + (regulator, config->voltage)); + break; + case REGU_VAUDIO: + case REGU_VIOHI: + case REGU_VRFBG: + CHECK_ERROR(pmic_power_regulator_set_lp_mode + (regulator, config->lp_mode)); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function retrives the regulator output configuration. + * + * @param regulator The regulator to be truned off. + * @param config Pointer to regulator configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_regulator_get_config(t_pmic_regulator regulator, + t_regulator_config *config) +{ + if (config == NULL) { + return PMIC_ERROR; + } + + switch (regulator) { + case SW_SW1A: + case SW_SW1B: + case SW_SW2A: + case SW_SW2B: + CHECK_ERROR(pmic_power_regulator_get_voltage + (regulator, &config->voltage)); + CHECK_ERROR(pmic_power_switcher_get_dvs + (regulator, &config->voltage_lvs)); + CHECK_ERROR(pmic_power_switcher_get_stby + (regulator, &config->voltage_stby)); + CHECK_ERROR(pmic_power_switcher_get_mode + (regulator, &config->mode, false)); + CHECK_ERROR(pmic_power_switcher_get_mode + (regulator, &config->stby_mode, true)); + CHECK_ERROR(pmic_power_switcher_get_dvs_speed + (regulator, &config->dvs_speed)); + CHECK_ERROR(pmic_power_switcher_get_panic_mode + (regulator, &config->panic_mode)); + CHECK_ERROR(pmic_power_switcher_get_softstart + (regulator, &config->softstart)); + break; + case SW_PLL: + CHECK_ERROR(pmic_power_switcher_get_factor + (regulator, &config->factor)); + break; + case SW_SW3: + case REGU_VIOLO: + case REGU_VDIG: + case REGU_VGEN: + case REGU_VRFDIG: + case REGU_VRFREF: + case REGU_VRFCP: + case REGU_VSIM: + case REGU_VESIM: + case REGU_VCAM: + case REGU_VRF1: + case REGU_VRF2: + case REGU_VMMC1: + case REGU_VMMC2: + CHECK_ERROR(pmic_power_regulator_get_voltage + (regulator, &config->voltage)); + CHECK_ERROR(pmic_power_regulator_get_lp_mode + (regulator, &config->lp_mode)); + break; + case REGU_VVIB: + CHECK_ERROR(pmic_power_regulator_get_voltage + (regulator, &config->voltage)); + break; + case REGU_VAUDIO: + case REGU_VIOHI: + case REGU_VRFBG: + CHECK_ERROR(pmic_power_regulator_get_lp_mode + (regulator, &config->lp_mode)); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + return PMIC_SUCCESS; +} + +/*! + * This function enables automatically VBKUP2 in the memory hold modes. + * Only on mc13783 2.0 or higher + * + * @param en if true, enable VBKUP2AUTOMH + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_vbkup2_auto_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_val = BITFVAL(MC13783_REGCTRL_VBKUP2AUTOMH, en); + reg_mask = BITFMASK(MC13783_REGCTRL_VBKUP2AUTOMH); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, + reg_val, reg_mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets state of automatically VBKUP2. + * Only on mc13783 2.0 or higher + * + * @param en if true, VBKUP2AUTOMH is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_vbkup2_auto_state(bool *en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_mask = BITFMASK(MC13783_REGCTRL_VBKUP2AUTOMH); + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0, + ®_val, reg_mask)); + *en = BITFEXT(reg_val, MC13783_REGCTRL_VBKUP2AUTOMH); + + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function enables battery detect function. + * Only on mc13783 2.0 or higher + * + * @param en if true, enable BATTDETEN + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_bat_det_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_val = BITFVAL(MC13783_REGCTRL_BATTDETEN, en); + reg_mask = BITFMASK(MC13783_REGCTRL_BATTDETEN); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_0, + reg_val, reg_mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets state of battery detect function. + * Only on mc13783 2.0 or higher + * + * @param en if true, BATTDETEN is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_bat_det_state(bool *en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_mask = BITFMASK(MC13783_REGCTRL_BATTDETEN); + + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_0, + ®_val, reg_mask)); + *en = BITFEXT(reg_val, MC13783_REGCTRL_BATTDETEN); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function enables control of VVIB by VIBEN pin. + * Only on mc13783 2.0 or higher + * + * @param en if true, enable VIBPINCTRL + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_vib_pin_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_val = BITFVAL(MC13783_REGCTRL_VIBPINCTRL, en); + reg_mask = BITFMASK(MC13783_REGCTRL_VIBPINCTRL); + + CHECK_ERROR(pmic_write_reg(REG_POWER_MISCELLANEOUS, + reg_val, reg_mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets state of control of VVIB by VIBEN pin. + * Only on mc13783 2.0 or higher + * @param en if true, VIBPINCTRL is enabled + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_gets_vib_pin_state(bool *en) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_mask = BITFMASK(MC13783_REGCTRL_VIBPINCTRL); + CHECK_ERROR(pmic_read_reg(REG_POWER_MISCELLANEOUS, + ®_val, reg_mask)); + *en = BITFEXT(reg_val, MC13783_REGCTRL_VIBPINCTRL); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function returns power up sense value + * + * @param p_up_sense value of power up sense + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_power_get_power_mode_sense(struct t_p_up_sense *p_up_sense) +{ + unsigned int reg_value = 0; + CHECK_ERROR(pmic_read_reg(REG_POWER_UP_MODE_SENSE, + ®_value, PMIC_ALL_BITS)); + p_up_sense->state_ictest = (STATE_ICTEST_MASK & reg_value); + p_up_sense->state_clksel = ((STATE_CLKSEL_MASK & reg_value) + >> STATE_CLKSEL_BIT); + p_up_sense->state_pums1 = ((STATE_PUMS1_MASK & reg_value) + >> STATE_PUMS1_BITS); + p_up_sense->state_pums2 = ((STATE_PUMS2_MASK & reg_value) + >> STATE_PUMS2_BITS); + p_up_sense->state_pums3 = ((STATE_PUMS3_MASK & reg_value) + >> STATE_PUMS3_BITS); + p_up_sense->state_chrgmode0 = ((STATE_CHRGM1_MASK & reg_value) + >> STATE_CHRGM1_BITS); + p_up_sense->state_chrgmode1 = ((STATE_CHRGM2_MASK & reg_value) + >> STATE_CHRGM2_BITS); + p_up_sense->state_umod = ((STATE_UMOD_MASK & reg_value) + >> STATE_UMOD_BITS); + p_up_sense->state_usben = ((STATE_USBEN_MASK & reg_value) + >> STATE_USBEN_BIT); + p_up_sense->state_sw_1a1b_joined = ((STATE_SW1A_J_B_MASK & reg_value) + >> STATE_SW1A_J_B_BIT); + p_up_sense->state_sw_2a2b_joined = ((STATE_SW2A_J_B_MASK & reg_value) + >> STATE_SW2A_J_B_BIT); + return PMIC_SUCCESS; +} + +/*! + * This function configures the Regen assignment for all regulator + * + * @param regulator type of regulator + * @param en_dis if true, the regulator is enabled by regen. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_regen_assig(t_pmic_regulator regulator, bool en_dis) +{ + unsigned int reg_val = 0, reg_mask = 0; + + switch (regulator) { + case REGU_VAUDIO: + reg_val = BITFVAL(MC13783_REGGEN_VAUDIO, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VAUDIO); + break; + case REGU_VIOHI: + reg_val = BITFVAL(MC13783_REGGEN_VIOHI, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VIOHI); + break; + case REGU_VIOLO: + reg_val = BITFVAL(MC13783_REGGEN_VIOLO, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VIOLO); + break; + case REGU_VDIG: + reg_val = BITFVAL(MC13783_REGGEN_VDIG, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VDIG); + break; + case REGU_VGEN: + reg_val = BITFVAL(MC13783_REGGEN_VGEN, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VGEN); + break; + case REGU_VRFDIG: + reg_val = BITFVAL(MC13783_REGGEN_VRFDIG, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRFDIG); + break; + case REGU_VRFREF: + reg_val = BITFVAL(MC13783_REGGEN_VRFREF, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRFREF); + break; + case REGU_VRFCP: + reg_val = BITFVAL(MC13783_REGGEN_VRFCP, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRFCP); + break; + case REGU_VCAM: + reg_val = BITFVAL(MC13783_REGGEN_VCAM, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VCAM); + break; + case REGU_VRFBG: + reg_val = BITFVAL(MC13783_REGGEN_VRFBG, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRFBG); + break; + case REGU_VRF1: + reg_val = BITFVAL(MC13783_REGGEN_VRF1, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRF1); + break; + case REGU_VRF2: + reg_val = BITFVAL(MC13783_REGGEN_VRF2, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VRF2); + break; + case REGU_VMMC1: + reg_val = BITFVAL(MC13783_REGGEN_VMMC1, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VMMC1); + break; + case REGU_VMMC2: + reg_val = BITFVAL(MC13783_REGGEN_VMMC2, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_VMMC2); + break; + case REGU_GPO1: + reg_val = BITFVAL(MC13783_REGGEN_GPO1, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_GPO1); + break; + case REGU_GPO2: + reg_val = BITFVAL(MC13783_REGGEN_GPO2, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_GPO2); + break; + case REGU_GPO3: + reg_val = BITFVAL(MC13783_REGGEN_GPO3, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_GPO3); + break; + case REGU_GPO4: + reg_val = BITFVAL(MC13783_REGGEN_GPO4, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_GPO4); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets the Regen assignment for all regulator + * + * @param regulator type of regulator + * @param en_dis return value, if true : + * the regulator is enabled by regen. + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_regen_assig(t_pmic_regulator regulator, + bool *en_dis) +{ + unsigned int reg_val = 0, reg_mask = 0; + + switch (regulator) { + case REGU_VAUDIO: + reg_mask = BITFMASK(MC13783_REGGEN_VAUDIO); + break; + case REGU_VIOHI: + reg_mask = BITFMASK(MC13783_REGGEN_VIOHI); + break; + case REGU_VIOLO: + reg_mask = BITFMASK(MC13783_REGGEN_VIOLO); + break; + case REGU_VDIG: + reg_mask = BITFMASK(MC13783_REGGEN_VDIG); + break; + case REGU_VGEN: + reg_mask = BITFMASK(MC13783_REGGEN_VGEN); + break; + case REGU_VRFDIG: + reg_mask = BITFMASK(MC13783_REGGEN_VRFDIG); + break; + case REGU_VRFREF: + reg_mask = BITFMASK(MC13783_REGGEN_VRFREF); + break; + case REGU_VRFCP: + reg_mask = BITFMASK(MC13783_REGGEN_VRFCP); + break; + case REGU_VCAM: + reg_mask = BITFMASK(MC13783_REGGEN_VCAM); + break; + case REGU_VRFBG: + reg_mask = BITFMASK(MC13783_REGGEN_VRFBG); + break; + case REGU_VRF1: + reg_mask = BITFMASK(MC13783_REGGEN_VRF1); + break; + case REGU_VRF2: + reg_mask = BITFMASK(MC13783_REGGEN_VRF2); + break; + case REGU_VMMC1: + reg_mask = BITFMASK(MC13783_REGGEN_VMMC1); + break; + case REGU_VMMC2: + reg_mask = BITFMASK(MC13783_REGGEN_VMMC2); + break; + case REGU_GPO1: + reg_mask = BITFMASK(MC13783_REGGEN_GPO1); + break; + case REGU_GPO2: + reg_mask = BITFMASK(MC13783_REGGEN_GPO2); + break; + case REGU_GPO3: + reg_mask = BITFMASK(MC13783_REGGEN_GPO3); + break; + case REGU_GPO4: + reg_mask = BITFMASK(MC13783_REGGEN_GPO4); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT, ®_val, reg_mask)); + + switch (regulator) { + case REGU_VAUDIO: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VAUDIO); + break; + case REGU_VIOHI: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VIOHI); + break; + case REGU_VIOLO: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VIOLO); + break; + case REGU_VDIG: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VDIG); + break; + case REGU_VGEN: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VGEN); + break; + case REGU_VRFDIG: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFDIG); + break; + case REGU_VRFREF: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFREF); + break; + case REGU_VRFCP: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFCP); + break; + case REGU_VCAM: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VCAM); + break; + case REGU_VRFBG: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRFBG); + break; + case REGU_VRF1: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRF1); + break; + case REGU_VRF2: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VRF2); + break; + case REGU_VMMC1: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VMMC1); + break; + case REGU_VMMC2: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_VMMC2); + break; + case REGU_GPO1: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO1); + break; + case REGU_GPO2: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO2); + break; + case REGU_GPO3: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO3); + break; + case REGU_GPO4: + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_GPO4); + break; + default: + break; + } + + return PMIC_SUCCESS; +} + +/*! + * This function sets the Regen polarity. + * + * @param en_dis If true regen is inverted. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_regen_inv(bool en_dis) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_val = BITFVAL(MC13783_REGGEN_INV, en_dis); + reg_mask = BITFMASK(MC13783_REGGEN_INV); + + CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT, reg_val, reg_mask)); + return PMIC_SUCCESS; +} + +/*! + * This function gets the Regen polarity. + * + * @param en_dis If true regen is inverted. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_regen_inv(bool *en_dis) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_mask = BITFMASK(MC13783_REGGEN_INV); + CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT, ®_val, reg_mask)); + *en_dis = BITFEXT(reg_val, MC13783_REGGEN_INV); + return PMIC_SUCCESS; +} + +/*! + * This function enables esim control voltage. + * Only on mc13783 2.0 or higher + * + * @param vesim if true, enable VESIMESIMEN + * @param vmmc1 if true, enable VMMC1ESIMEN + * @param vmmc2 if true, enable VMMC2ESIMEN + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_esim_v_en(bool vesim, bool vmmc1, bool vmmc2) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_val = BITFVAL(MC13783_REGGEN_VESIMESIM, vesim) | + BITFVAL(MC13783_REGGEN_VMMC1ESIM, vesim) | + BITFVAL(MC13783_REGGEN_VMMC2ESIM, vesim); + reg_mask = BITFMASK(MC13783_REGGEN_VESIMESIM) | + BITFMASK(MC13783_REGGEN_VMMC1ESIM) | + BITFMASK(MC13783_REGGEN_VMMC2ESIM); + CHECK_ERROR(pmic_write_reg(REG_REGEN_ASSIGNMENT, + reg_val, reg_mask)); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function gets esim control voltage values. + * Only on mc13783 2.0 or higher + * + * @param vesim if true, enable VESIMESIMEN + * @param vmmc1 if true, enable VMMC1ESIMEN + * @param vmmc2 if true, enable VMMC2ESIMEN + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_gets_esim_v_state(bool *vesim, bool *vmmc1, + bool *vmmc2) +{ + unsigned int reg_val = 0, reg_mask = 0; + pmic_version_t mc13783_ver; + mc13783_ver = pmic_get_version(); + if (mc13783_ver.revision >= 20) { + reg_mask = BITFMASK(MC13783_REGGEN_VESIMESIM) | + BITFMASK(MC13783_REGGEN_VMMC1ESIM) | + BITFMASK(MC13783_REGGEN_VMMC2ESIM); + CHECK_ERROR(pmic_read_reg(REG_REGEN_ASSIGNMENT, + ®_val, reg_mask)); + *vesim = BITFEXT(reg_val, MC13783_REGGEN_VESIMESIM); + *vmmc1 = BITFEXT(reg_val, MC13783_REGGEN_VMMC1ESIM); + *vmmc2 = BITFEXT(reg_val, MC13783_REGGEN_VMMC2ESIM); + return PMIC_SUCCESS; + } else { + return PMIC_NOT_SUPPORTED; + } +} + +/*! + * This function enables auto reset after a system reset. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_auto_reset_en(bool en) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_val = BITFVAL(MC13783_AUTO_RESTART, en); + reg_mask = BITFMASK(MC13783_AUTO_RESTART); + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_2, reg_val, reg_mask)); + return PMIC_SUCCESS; +} + +/*! + * This function gets auto reset configuration. + * + * @param en if true, the auto reset is enabled + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_auto_reset_en(bool *en) +{ + unsigned int reg_val = 0, reg_mask = 0; + + reg_mask = BITFMASK(MC13783_AUTO_RESTART); + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_2, ®_val, reg_mask)); + *en = BITFEXT(reg_val, MC13783_AUTO_RESTART); + return PMIC_SUCCESS; +} + +/*! + * This function configures a system reset on a button. + * + * @param bt type of button. + * @param sys_rst if true, enable the system reset on this button + * @param deb_time sets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_set_conf_button(t_button bt, bool sys_rst, int deb_time) +{ + int max_val = 0; + unsigned int reg_val = 0, reg_mask = 0; + + max_val = (1 << MC13783_DEB_BT_ON1B_WID) - 1; + if (deb_time > max_val) { + return PMIC_PARAMETER_ERROR; + } + + switch (bt) { + case BT_ON1B: + reg_val = BITFVAL(MC13783_EN_BT_ON1B, sys_rst) | + BITFVAL(MC13783_DEB_BT_ON1B, deb_time); + reg_mask = BITFMASK(MC13783_EN_BT_ON1B) | + BITFMASK(MC13783_DEB_BT_ON1B); + break; + case BT_ON2B: + reg_val = BITFVAL(MC13783_EN_BT_ON2B, sys_rst) | + BITFVAL(MC13783_DEB_BT_ON2B, deb_time); + reg_mask = BITFMASK(MC13783_EN_BT_ON2B) | + BITFMASK(MC13783_DEB_BT_ON2B); + break; + case BT_ON3B: + reg_val = BITFVAL(MC13783_EN_BT_ON3B, sys_rst) | + BITFVAL(MC13783_DEB_BT_ON3B, deb_time); + reg_mask = BITFMASK(MC13783_EN_BT_ON3B) | + BITFMASK(MC13783_DEB_BT_ON3B); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_POWER_CONTROL_2, reg_val, reg_mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function gets configuration of a button. + * + * @param bt type of button. + * @param sys_rst if true, the system reset is enabled on this button + * @param deb_time gets the debounce time on this button pin + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_get_conf_button(t_button bt, + bool *sys_rst, int *deb_time) +{ + unsigned int reg_val = 0, reg_mask = 0; + + switch (bt) { + case BT_ON1B: + reg_mask = BITFMASK(MC13783_EN_BT_ON1B) | + BITFMASK(MC13783_DEB_BT_ON1B); + break; + case BT_ON2B: + reg_mask = BITFMASK(MC13783_EN_BT_ON2B) | + BITFMASK(MC13783_DEB_BT_ON2B); + break; + case BT_ON3B: + reg_mask = BITFMASK(MC13783_EN_BT_ON3B) | + BITFMASK(MC13783_DEB_BT_ON3B); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(REG_POWER_CONTROL_2, ®_val, reg_mask)); + + switch (bt) { + case BT_ON1B: + *sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON1B); + *deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON1B); + break; + case BT_ON2B: + *sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON2B); + *deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON2B); + break; + case BT_ON3B: + *sys_rst = BITFEXT(reg_val, MC13783_EN_BT_ON3B); + *deb_time = BITFEXT(reg_val, MC13783_DEB_BT_ON3B); + break; + default: + return PMIC_PARAMETER_ERROR; + } + return PMIC_SUCCESS; +} + +/*! + * This function is used to un/subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * @param sub define if Un/subscribe event. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event(t_pwr_int event, void *callback, bool sub) +{ + pmic_event_callback_t power_callback; + type_event power_event; + + power_callback.func = callback; + power_callback.param = NULL; + switch (event) { + case PWR_IT_BPONI: + power_event = EVENT_BPONI; + break; + case PWR_IT_LOBATLI: + power_event = EVENT_LOBATLI; + break; + case PWR_IT_LOBATHI: + power_event = EVENT_LOBATHI; + break; + case PWR_IT_ONOFD1I: + power_event = EVENT_ONOFD1I; + break; + case PWR_IT_ONOFD2I: + power_event = EVENT_ONOFD2I; + break; + case PWR_IT_ONOFD3I: + power_event = EVENT_ONOFD3I; + break; + case PWR_IT_SYSRSTI: + power_event = EVENT_SYSRSTI; + break; + case PWR_IT_PWRRDYI: + power_event = EVENT_PWRRDYI; + break; + case PWR_IT_PCI: + power_event = EVENT_PCI; + break; + case PWR_IT_WARMI: + power_event = EVENT_WARMI; + break; + default: + return PMIC_PARAMETER_ERROR; + } + if (sub == true) { + CHECK_ERROR(pmic_event_subscribe(power_event, power_callback)); + } else { + CHECK_ERROR(pmic_event_unsubscribe + (power_event, power_callback)); + } + return PMIC_SUCCESS; +} + +/*! + * This function is used to subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_sub(t_pwr_int event, void *callback) +{ + return pmic_power_event(event, callback, true); +} + +/*! + * This function is used to un subscribe on power event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_power_event_unsub(t_pwr_int event, void *callback) +{ + return pmic_power_event(event, callback, false); +} + +void pmic_power_key_callback(void) +{ +#ifdef CONFIG_MXC_HWEVENT + /*read the power key is pressed or up */ + t_sensor_bits sense; + struct mxc_hw_event event = { HWE_POWER_KEY, 0 }; + + pmic_get_sensors(&sense); + if (sense.sense_onofd1s) { + pr_debug("PMIC Power key up\n"); + event.args = PWRK_UNPRESS; + } else { + pr_debug("PMIC Power key pressed\n"); + event.args = PWRK_PRESS; + } + /* send hw event */ + hw_event_send(HWE_DEF_PRIORITY, &event); +#endif +} + +static irqreturn_t power_key_int(int irq, void *dev_id) +{ + pr_info(KERN_INFO "on-off key pressed\n"); + + return 0; +} + +extern void gpio_power_key_active(void); + +/* + * Init and Exit + */ + +static int pmic_power_probe(struct platform_device *pdev) +{ + int irq, ret; + struct pmic_platform_data *ppd; + + /* configure on/off button */ + gpio_power_key_active(); + + ppd = pdev->dev.platform_data; + if (ppd) + irq = ppd->power_key_irq; + else + goto done; + + if (irq == 0) { + pr_info(KERN_INFO "PMIC Power has no platform data\n"); + goto done; + } + set_irq_type(irq, IRQF_TRIGGER_RISING); + + ret = request_irq(irq, power_key_int, 0, "power_key", 0); + if (ret) + pr_info(KERN_ERR "register on-off key interrupt failed\n"); + + set_irq_wake(irq, 1); + + done: + pr_info(KERN_INFO "PMIC Power successfully probed\n"); + return 0; +} + +static struct platform_driver pmic_power_driver_ldm = { + .driver = { + .name = "pmic_power", + }, + .suspend = pmic_power_suspend, + .resume = pmic_power_resume, + .probe = pmic_power_probe, + .remove = NULL, +}; + +static int __init pmic_power_init(void) +{ + pr_debug("PMIC Power driver loading..\n"); + pmic_power_event_sub(PWR_IT_ONOFD1I, pmic_power_key_callback); + /* set power off hook to mc13783 power off */ + pm_power_off = pmic_power_off; + return platform_driver_register(&pmic_power_driver_ldm); +} +static void __exit pmic_power_exit(void) +{ + pmic_power_event_unsub(PWR_IT_ONOFD1I, pmic_power_key_callback); + platform_driver_unregister(&pmic_power_driver_ldm); + pr_debug("PMIC Power driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +subsys_initcall_sync(pmic_power_init); +module_exit(pmic_power_exit); + +MODULE_DESCRIPTION("pmic_power driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13783/pmic_power_defs.h b/drivers/mxc/pmic/mc13783/pmic_power_defs.h new file mode 100644 index 000000000000..6777f56321e5 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_power_defs.h @@ -0,0 +1,509 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_power_defs.h + * @brief This is the internal header define of PMIC(mc13783) Power driver. + * + * @ingroup PMIC_POWER + */ + +/* + * Includes + */ + +#ifndef __MC13783_POWER_DEFS_H__ +#define __MC13783_POWER_DEFS_H__ + +/* + * Power Up Mode Sense bits + */ + +#define STATE_ICTEST_MASK 0x000001 + +#define STATE_CLKSEL_BIT 1 +#define STATE_CLKSEL_MASK 0x000002 + +#define STATE_PUMS1_BITS 2 +#define STATE_PUMS1_MASK 0x00000C + +#define STATE_PUMS2_BITS 4 +#define STATE_PUMS2_MASK 0x000030 + +#define STATE_PUMS3_BITS 6 +#define STATE_PUMS3_MASK 0x0000C0 + +#define STATE_CHRGM1_BITS 8 +#define STATE_CHRGM1_MASK 0x000300 + +#define STATE_CHRGM2_BITS 10 +#define STATE_CHRGM2_MASK 0x000C00 + +#define STATE_UMOD_BITS 12 +#define STATE_UMOD_MASK 0x003000 + +#define STATE_USBEN_BIT 14 +#define STATE_USBEN_MASK 0x004000 + +#define STATE_SW1A_J_B_BIT 15 +#define STATE_SW1A_J_B_MASK 0x008000 + +#define STATE_SW2A_J_B_BIT 16 +#define STATE_SW2A_J_B_MASK 0x010000 + +#define PC_COUNT_MAX 3 +#define PC_COUNT_MIN 0 +/* + * Reg Regen + */ +#define MC13783_REGGEN_VAUDIO_LSH 0 +#define MC13783_REGGEN_VAUDIO_WID 1 +#define MC13783_REGGEN_VIOHI_LSH 1 +#define MC13783_REGGEN_VIOHI_WID 1 +#define MC13783_REGGEN_VIOLO_LSH 2 +#define MC13783_REGGEN_VIOLO_WID 1 +#define MC13783_REGGEN_VDIG_LSH 3 +#define MC13783_REGGEN_VDIG_WID 1 +#define MC13783_REGGEN_VGEN_LSH 4 +#define MC13783_REGGEN_VGEN_WID 1 +#define MC13783_REGGEN_VRFDIG_LSH 5 +#define MC13783_REGGEN_VRFDIG_WID 1 +#define MC13783_REGGEN_VRFREF_LSH 6 +#define MC13783_REGGEN_VRFREF_WID 1 +#define MC13783_REGGEN_VRFCP_LSH 7 +#define MC13783_REGGEN_VRFCP_WID 1 +#define MC13783_REGGEN_VCAM_LSH 8 +#define MC13783_REGGEN_VCAM_WID 1 +#define MC13783_REGGEN_VRFBG_LSH 9 +#define MC13783_REGGEN_VRFBG_WID 1 +#define MC13783_REGGEN_VRF1_LSH 10 +#define MC13783_REGGEN_VRF1_WID 1 +#define MC13783_REGGEN_VRF2_LSH 11 +#define MC13783_REGGEN_VRF2_WID 1 +#define MC13783_REGGEN_VMMC1_LSH 12 +#define MC13783_REGGEN_VMMC1_WID 1 +#define MC13783_REGGEN_VMMC2_LSH 13 +#define MC13783_REGGEN_VMMC2_WID 1 +#define MC13783_REGGEN_GPO1_LSH 16 +#define MC13783_REGGEN_GPO1_WID 1 +#define MC13783_REGGEN_GPO2_LSH 17 +#define MC13783_REGGEN_GPO2_WID 1 +#define MC13783_REGGEN_GPO3_LSH 18 +#define MC13783_REGGEN_GPO3_WID 1 +#define MC13783_REGGEN_GPO4_LSH 19 +#define MC13783_REGGEN_GPO4_WID 1 +#define MC13783_REGGEN_INV_LSH 20 +#define MC13783_REGGEN_INV_WID 1 +#define MC13783_REGGEN_VESIMESIM_LSH 21 +#define MC13783_REGGEN_VESIMESIM_WID 1 +#define MC13783_REGGEN_VMMC1ESIM_LSH 22 +#define MC13783_REGGEN_VMMC1ESIM_WID 1 +#define MC13783_REGGEN_VMMC2ESIM_LSH 23 +#define MC13783_REGGEN_VMMC2ESIM_WID 1 + +/* + * Reg Power Control 0 + */ +#define MC13783_PWRCTRL_PCEN_LSH 0 +#define MC13783_PWRCTRL_PCEN_WID 1 +#define MC13783_PWRCTRL_PCEN_ENABLE 1 +#define MC13783_PWRCTRL_PCEN_DISABLE 0 +#define MC13783_PWRCTRL_PC_COUNT_EN_LSH 1 +#define MC13783_PWRCTRL_PC_COUNT_EN_WID 1 +#define MC13783_PWRCTRL_PC_COUNT_EN_ENABLE 1 +#define MC13783_PWRCTRL_PC_COUNT_EN_DISABLE 0 +#define MC13783_PWRCTRL_WARM_EN_LSH 2 +#define MC13783_PWRCTRL_WARM_EN_WID 1 +#define MC13783_PWRCTRL_WARM_EN_ENABLE 1 +#define MC13783_PWRCTRL_WARM_EN_DISABLE 0 +#define MC13783_PWRCTRL_USER_OFF_SPI_LSH 3 +#define MC13783_PWRCTRL_USER_OFF_SPI_WID 1 +#define MC13783_PWRCTRL_USER_OFF_SPI_ENABLE 1 +#define MC13783_PWRCTRL_USER_OFF_PC_LSH 4 +#define MC13783_PWRCTRL_USER_OFF_PC_WID 1 +#define MC13783_PWRCTRL_USER_OFF_PC_ENABLE 1 +#define MC13783_PWRCTRL_USER_OFF_PC_DISABLE 0 +#define MC13783_PWRCTRL_32OUT_USER_OFF_LSH 5 +#define MC13783_PWRCTRL_32OUT_USER_OFF_WID 1 +#define MC13783_PWRCTRL_32OUT_USER_OFF_ENABLE 1 +#define MC13783_PWRCTRL_32OUT_USER_OFF_DISABLE 0 +#define MC13783_PWRCTRL_32OUT_EN_LSH 6 +#define MC13783_PWRCTRL_32OUT_EN_WID 1 +#define MC13783_PWRCTRL_32OUT_EN_ENABLE 1 +#define MC13783_PWRCTRL_32OUT_EN_DISABLE 0 +#define MC13783_REGCTRL_VBKUP2AUTOMH_LSH 7 +#define MC13783_REGCTRL_VBKUP2AUTOMH_WID 1 +#define MC13783_PWRCTRL_VBKUP1_EN_LSH 8 +#define MC13783_PWRCTRL_VBKUP1_EN_WID 1 +#define MC13783_PWRCTRL_VBKUP_ENABLE 1 +#define MC13783_PWRCTRL_VBKUP_DISABLE 0 +#define MC13783_PWRCTRL_VBKUP1_AUTO_EN_LSH 9 +#define MC13783_PWRCTRL_VBKUP1_AUTO_EN_WID 1 +#define MC13783_PWRCTRL_VBKUP1_LSH 10 +#define MC13783_PWRCTRL_VBKUP1_WID 2 +#define MC13783_PWRCTRL_VBKUP2_EN_LSH 12 +#define MC13783_PWRCTRL_VBKUP2_EN_WID 1 +#define MC13783_PWRCTRL_VBKUP2_AUTO_EN_LSH 13 +#define MC13783_PWRCTRL_VBKUP2_AUTO_EN_WID 1 +#define MC13783_PWRCTRL_VBKUP2_LSH 14 +#define MC13783_PWRCTRL_VBKUP2_WID 2 +#define MC13783_REGCTRL_BATTDETEN_LSH 19 +#define MC13783_REGCTRL_BATTDETEN_WID 1 + +/* + * Reg Power Control 1 + */ +#define MC13783_PWRCTRL_PCT_LSH 0 +#define MC13783_PWRCTRL_PCT_WID 8 +#define MC13783_PWRCTRL_PC_COUNT_LSH 8 +#define MC13783_PWRCTRL_PC_COUNT_WID 4 +#define MC13783_PWRCTRL_PC_MAX_CNT_LSH 12 +#define MC13783_PWRCTRL_PC_MAX_CNT_WID 4 +#define MC13783_PWRCTRL_MEM_TMR_LSH 16 +#define MC13783_PWRCTRL_MEM_TMR_WID 4 +#define MC13783_PWRCTRL_MEM_ALLON_LSH 20 +#define MC13783_PWRCTRL_MEM_ALLON_WID 1 +#define MC13783_PWRCTRL_MEM_ALLON_ENABLE 1 +#define MC13783_PWRCTRL_MEM_ALLON_DISABLE 0 + +/* + * Reg Power Control 2 + */ +#define MC13783_AUTO_RESTART_LSH 0 +#define MC13783_AUTO_RESTART_WID 1 +#define MC13783_EN_BT_ON1B_LSH 1 +#define MC13783_EN_BT_ON1B_WID 1 +#define MC13783_EN_BT_ON2B_LSH 2 +#define MC13783_EN_BT_ON2B_WID 1 +#define MC13783_EN_BT_ON3B_LSH 3 +#define MC13783_EN_BT_ON3B_WID 1 +#define MC13783_DEB_BT_ON1B_LSH 4 +#define MC13783_DEB_BT_ON1B_WID 2 +#define MC13783_DEB_BT_ON2B_LSH 6 +#define MC13783_DEB_BT_ON2B_WID 2 +#define MC13783_DEB_BT_ON3B_LSH 8 +#define MC13783_DEB_BT_ON3B_WID 2 + +/* + * Reg Regulator Mode 0 + */ +#define MC13783_REGCTRL_VAUDIO_EN_LSH 0 +#define MC13783_REGCTRL_VAUDIO_EN_WID 1 +#define MC13783_REGCTRL_VAUDIO_EN_ENABLE 1 +#define MC13783_REGCTRL_VAUDIO_EN_DISABLE 0 +#define MC13783_REGCTRL_VAUDIO_STBY_LSH 1 +#define MC13783_REGCTRL_VAUDIO_STBY_WID 1 +#define MC13783_REGCTRL_VAUDIO_MODE_LSH 2 +#define MC13783_REGCTRL_VAUDIO_MODE_WID 1 +#define MC13783_REGCTRL_VIOHI_EN_LSH 3 +#define MC13783_REGCTRL_VIOHI_EN_WID 1 +#define MC13783_REGCTRL_VIOHI_EN_ENABLE 1 +#define MC13783_REGCTRL_VIOHI_EN_DISABLE 0 +#define MC13783_REGCTRL_VIOHI_STBY_LSH 4 +#define MC13783_REGCTRL_VIOHI_STBY_WID 1 +#define MC13783_REGCTRL_VIOHI_MODE_LSH 5 +#define MC13783_REGCTRL_VIOHI_MODE_WID 1 +#define MC13783_REGCTRL_VIOLO_EN_LSH 6 +#define MC13783_REGCTRL_VIOLO_EN_WID 1 +#define MC13783_REGCTRL_VIOLO_EN_ENABLE 1 +#define MC13783_REGCTRL_VIOLO_EN_DISABLE 0 +#define MC13783_REGCTRL_VIOLO_STBY_LSH 7 +#define MC13783_REGCTRL_VIOLO_STBY_WID 1 +#define MC13783_REGCTRL_VIOLO_MODE_LSH 8 +#define MC13783_REGCTRL_VIOLO_MODE_WID 1 +#define MC13783_REGCTRL_VDIG_EN_LSH 9 +#define MC13783_REGCTRL_VDIG_EN_WID 1 +#define MC13783_REGCTRL_VDIG_EN_ENABLE 1 +#define MC13783_REGCTRL_VDIG_EN_DISABLE 0 +#define MC13783_REGCTRL_VDIG_STBY_LSH 10 +#define MC13783_REGCTRL_VDIG_STBY_WID 1 +#define MC13783_REGCTRL_VDIG_MODE_LSH 11 +#define MC13783_REGCTRL_VDIG_MODE_WID 1 +#define MC13783_REGCTRL_VGEN_EN_LSH 12 +#define MC13783_REGCTRL_VGEN_EN_WID 1 +#define MC13783_REGCTRL_VGEN_EN_ENABLE 1 +#define MC13783_REGCTRL_VGEN_EN_DISABLE 0 +#define MC13783_REGCTRL_VGEN_STBY_LSH 13 +#define MC13783_REGCTRL_VGEN_STBY_WID 1 +#define MC13783_REGCTRL_VGEN_MODE_LSH 14 +#define MC13783_REGCTRL_VGEN_MODE_WID 1 +#define MC13783_REGCTRL_VRFDIG_EN_LSH 15 +#define MC13783_REGCTRL_VRFDIG_EN_WID 1 +#define MC13783_REGCTRL_VRFDIG_EN_ENABLE 1 +#define MC13783_REGCTRL_VRFDIG_EN_DISABLE 0 +#define MC13783_REGCTRL_VRFDIG_STBY_LSH 16 +#define MC13783_REGCTRL_VRFDIG_STBY_WID 1 +#define MC13783_REGCTRL_VRFDIG_MODE_LSH 17 +#define MC13783_REGCTRL_VRFDIG_MODE_WID 1 +#define MC13783_REGCTRL_VRFREF_EN_LSH 18 +#define MC13783_REGCTRL_VRFREF_EN_WID 1 +#define MC13783_REGCTRL_VRFREF_EN_ENABLE 1 +#define MC13783_REGCTRL_VRFREF_EN_DISABLE 0 +#define MC13783_REGCTRL_VRFREF_STBY_LSH 19 +#define MC13783_REGCTRL_VRFREF_STBY_WID 1 +#define MC13783_REGCTRL_VRFREF_MODE_LSH 20 +#define MC13783_REGCTRL_VRFREF_MODE_WID 1 +#define MC13783_REGCTRL_VRFCP_EN_LSH 21 +#define MC13783_REGCTRL_VRFCP_EN_WID 1 +#define MC13783_REGCTRL_VRFCP_EN_ENABLE 1 +#define MC13783_REGCTRL_VRFCP_EN_DISABLE 0 +#define MC13783_REGCTRL_VRFCP_STBY_LSH 22 +#define MC13783_REGCTRL_VRFCP_STBY_WID 1 +#define MC13783_REGCTRL_VRFCP_MODE_LSH 23 +#define MC13783_REGCTRL_VRFCP_MODE_WID 1 + +/* + * Reg Regulator Mode 1 + */ +#define MC13783_REGCTRL_VSIM_EN_LSH 0 +#define MC13783_REGCTRL_VSIM_EN_WID 1 +#define MC13783_REGCTRL_VSIM_EN_ENABLE 1 +#define MC13783_REGCTRL_VSIM_EN_DISABLE 0 +#define MC13783_REGCTRL_VSIM_STBY_LSH 1 +#define MC13783_REGCTRL_VSIM_STBY_WID 1 +#define MC13783_REGCTRL_VSIM_MODE_LSH 2 +#define MC13783_REGCTRL_VSIM_MODE_WID 1 +#define MC13783_REGCTRL_VESIM_EN_LSH 3 +#define MC13783_REGCTRL_VESIM_EN_WID 1 +#define MC13783_REGCTRL_VESIM_EN_ENABLE 1 +#define MC13783_REGCTRL_VESIM_EN_DISABLE 0 +#define MC13783_REGCTRL_VESIM_STBY_LSH 4 +#define MC13783_REGCTRL_VESIM_STBY_WID 1 +#define MC13783_REGCTRL_VESIM_MODE_LSH 5 +#define MC13783_REGCTRL_VESIM_MODE_WID 1 +#define MC13783_REGCTRL_VCAM_EN_LSH 6 +#define MC13783_REGCTRL_VCAM_EN_WID 1 +#define MC13783_REGCTRL_VCAM_EN_ENABLE 1 +#define MC13783_REGCTRL_VCAM_EN_DISABLE 0 +#define MC13783_REGCTRL_VCAM_STBY_LSH 7 +#define MC13783_REGCTRL_VCAM_STBY_WID 1 +#define MC13783_REGCTRL_VCAM_MODE_LSH 8 +#define MC13783_REGCTRL_VCAM_MODE_WID 1 +#define MC13783_REGCTRL_VRFBG_EN_LSH 9 +#define MC13783_REGCTRL_VRFBG_EN_WID 1 +#define MC13783_REGCTRL_VRFBG_EN_ENABLE 1 +#define MC13783_REGCTRL_VRFBG_EN_DISABLE 0 +#define MC13783_REGCTRL_VRFBG_STBY_LSH 10 +#define MC13783_REGCTRL_VRFBG_STBY_WID 1 +#define MC13783_REGCTRL_VVIB_EN_LSH 11 +#define MC13783_REGCTRL_VVIB_EN_WID 1 +#define MC13783_REGCTRL_VVIB_EN_ENABLE 1 +#define MC13783_REGCTRL_VVIB_EN_DISABLE 0 +#define MC13783_REGCTRL_VRF1_EN_LSH 12 +#define MC13783_REGCTRL_VRF1_EN_WID 1 +#define MC13783_REGCTRL_VRF1_EN_ENABLE 1 +#define MC13783_REGCTRL_VRF1_EN_DISABLE 0 +#define MC13783_REGCTRL_VRF1_STBY_LSH 13 +#define MC13783_REGCTRL_VRF1_STBY_WID 1 +#define MC13783_REGCTRL_VRF1_MODE_LSH 14 +#define MC13783_REGCTRL_VRF1_MODE_WID 1 +#define MC13783_REGCTRL_VRF2_EN_LSH 15 +#define MC13783_REGCTRL_VRF2_EN_WID 1 +#define MC13783_REGCTRL_VRF2_EN_ENABLE 1 +#define MC13783_REGCTRL_VRF2_EN_DISABLE 0 +#define MC13783_REGCTRL_VRF2_STBY_LSH 16 +#define MC13783_REGCTRL_VRF2_STBY_WID 1 +#define MC13783_REGCTRL_VRF2_MODE_LSH 17 +#define MC13783_REGCTRL_VRF2_MODE_WID 1 +#define MC13783_REGCTRL_VMMC1_EN_LSH 18 +#define MC13783_REGCTRL_VMMC1_EN_WID 1 +#define MC13783_REGCTRL_VMMC1_EN_ENABLE 1 +#define MC13783_REGCTRL_VMMC1_EN_DISABLE 0 +#define MC13783_REGCTRL_VMMC1_STBY_LSH 19 +#define MC13783_REGCTRL_VMMC1_STBY_WID 1 +#define MC13783_REGCTRL_VMMC1_MODE_LSH 20 +#define MC13783_REGCTRL_VMMC1_MODE_WID 1 +#define MC13783_REGCTRL_VMMC2_EN_LSH 21 +#define MC13783_REGCTRL_VMMC2_EN_WID 1 +#define MC13783_REGCTRL_VMMC2_EN_ENABLE 1 +#define MC13783_REGCTRL_VMMC2_EN_DISABLE 0 +#define MC13783_REGCTRL_VMMC2_STBY_LSH 22 +#define MC13783_REGCTRL_VMMC2_STBY_WID 1 +#define MC13783_REGCTRL_VMMC2_MODE_LSH 23 +#define MC13783_REGCTRL_VMMC2_MODE_WID 1 + +/* + * Reg Regulator Misc. + */ +#define MC13783_REGCTRL_GPO1_EN_LSH 6 +#define MC13783_REGCTRL_GPO1_EN_WID 1 +#define MC13783_REGCTRL_GPO1_EN_ENABLE 1 +#define MC13783_REGCTRL_GPO1_EN_DISABLE 0 +#define MC13783_REGCTRL_GPO2_EN_LSH 8 +#define MC13783_REGCTRL_GPO2_EN_WID 1 +#define MC13783_REGCTRL_GPO2_EN_ENABLE 1 +#define MC13783_REGCTRL_GPO2_EN_DISABLE 0 +#define MC13783_REGCTRL_GPO3_EN_LSH 10 +#define MC13783_REGCTRL_GPO3_EN_WID 1 +#define MC13783_REGCTRL_GPO3_EN_ENABLE 1 +#define MC13783_REGCTRL_GPO3_EN_DISABLE 0 +#define MC13783_REGCTRL_GPO4_EN_LSH 12 +#define MC13783_REGCTRL_GPO4_EN_WID 1 +#define MC13783_REGCTRL_GPO4_EN_ENABLE 1 +#define MC13783_REGCTRL_GPO4_EN_DISABLE 0 +#define MC13783_REGCTRL_VIBPINCTRL_LSH 14 +#define MC13783_REGCTRL_VIBPINCTRL_WID 1 + +/* + * Reg Regulator Setting 0 + */ +#define MC13783_REGSET_VIOLO_LSH 2 +#define MC13783_REGSET_VIOLO_WID 2 +#define MC13783_REGSET_VDIG_LSH 4 +#define MC13783_REGSET_VDIG_WID 2 +#define MC13783_REGSET_VGEN_LSH 6 +#define MC13783_REGSET_VGEN_WID 3 +#define MC13783_REGSET_VRFDIG_LSH 9 +#define MC13783_REGSET_VRFDIG_WID 2 +#define MC13783_REGSET_VRFREF_LSH 11 +#define MC13783_REGSET_VRFREF_WID 2 +#define MC13783_REGSET_VRFCP_LSH 13 +#define MC13783_REGSET_VRFCP_WID 1 +#define MC13783_REGSET_VSIM_LSH 14 +#define MC13783_REGSET_VSIM_WID 1 +#define MC13783_REGSET_VESIM_LSH 15 +#define MC13783_REGSET_VESIM_WID 1 +#define MC13783_REGSET_VCAM_LSH 16 +#define MC13783_REGSET_VCAM_WID 3 + +/* + * Reg Regulator Setting 1 + */ +#define MC13783_REGSET_VVIB_LSH 0 +#define MC13783_REGSET_VVIB_WID 2 +#define MC13783_REGSET_VRF1_LSH 2 +#define MC13783_REGSET_VRF1_WID 2 +#define MC13783_REGSET_VRF2_LSH 4 +#define MC13783_REGSET_VRF2_WID 2 +#define MC13783_REGSET_VMMC1_LSH 6 +#define MC13783_REGSET_VMMC1_WID 3 +#define MC13783_REGSET_VMMC2_LSH 9 +#define MC13783_REGSET_VMMC2_WID 3 + +/* + * Reg Switcher 0 + */ +#define MC13783_SWSET_SW1A_LSH 0 +#define MC13783_SWSET_SW1A_WID 6 +#define MC13783_SWSET_SW1A_DVS_LSH 6 +#define MC13783_SWSET_SW1A_DVS_WID 6 +#define MC13783_SWSET_SW1A_STDBY_LSH 12 +#define MC13783_SWSET_SW1A_STDBY_WID 6 + +/* + * Reg Switcher 1 + */ +#define MC13783_SWSET_SW1B_LSH 0 +#define MC13783_SWSET_SW1B_WID 6 +#define MC13783_SWSET_SW1B_DVS_LSH 6 +#define MC13783_SWSET_SW1B_DVS_WID 6 +#define MC13783_SWSET_SW1B_STDBY_LSH 12 +#define MC13783_SWSET_SW1B_STDBY_WID 6 + +/* + * Reg Switcher 2 + */ +#define MC13783_SWSET_SW2A_LSH 0 +#define MC13783_SWSET_SW2A_WID 6 +#define MC13783_SWSET_SW2A_DVS_LSH 6 +#define MC13783_SWSET_SW2A_DVS_WID 6 +#define MC13783_SWSET_SW2A_STDBY_LSH 12 +#define MC13783_SWSET_SW2A_STDBY_WID 6 + +/* + * Reg Switcher 3 + */ +#define MC13783_SWSET_SW2B_LSH 0 +#define MC13783_SWSET_SW2B_WID 6 +#define MC13783_SWSET_SW2B_DVS_LSH 6 +#define MC13783_SWSET_SW2B_DVS_WID 6 +#define MC13783_SWSET_SW2B_STDBY_LSH 12 +#define MC13783_SWSET_SW2B_STDBY_WID 6 + +/* + * Reg Switcher 4 + */ +#define MC13783_SWCTRL_SW1A_MODE_LSH 0 +#define MC13783_SWCTRL_SW1A_MODE_WID 2 +#define MC13783_SWCTRL_SW1A_STBY_MODE_LSH 2 +#define MC13783_SWCTRL_SW1A_STBY_MODE_WID 2 +#define MC13783_SWCTRL_SW1A_DVS_SPEED_LSH 6 +#define MC13783_SWCTRL_SW1A_DVS_SPEED_WID 2 +#define MC13783_SWCTRL_SW1A_PANIC_MODE_LSH 8 +#define MC13783_SWCTRL_SW1A_PANIC_MODE_WID 1 +#define MC13783_SWCTRL_SW1A_SOFTSTART_LSH 9 +#define MC13783_SWCTRL_SW1A_SOFTSTART_WID 1 +#define MC13783_SWCTRL_SW1B_MODE_LSH 10 +#define MC13783_SWCTRL_SW1B_MODE_WID 2 +#define MC13783_SWCTRL_SW1B_STBY_MODE_LSH 12 +#define MC13783_SWCTRL_SW1B_STBY_MODE_WID 2 +#define MC13783_SWCTRL_SW1B_DVS_SPEED_LSH 14 +#define MC13783_SWCTRL_SW1B_DVS_SPEED_WID 2 +#define MC13783_SWCTRL_SW1B_PANIC_MODE_LSH 16 +#define MC13783_SWCTRL_SW1B_PANIC_MODE_WID 1 +#define MC13783_SWCTRL_SW1B_SOFTSTART_LSH 17 +#define MC13783_SWCTRL_SW1B_SOFTSTART_WID 1 +#define MC13783_SWCTRL_PLL_EN_LSH 18 +#define MC13783_SWCTRL_PLL_EN_WID 1 +#define MC13783_SWCTRL_PLL_EN_ENABLE 1 +#define MC13783_SWCTRL_PLL_EN_DISABLE 0 +#define MC13783_SWCTRL_PLL_FACTOR_LSH 19 +#define MC13783_SWCTRL_PLL_FACTOR_WID 3 + +/* + * Reg Switcher 5 + */ +#define MC13783_SWCTRL_SW2A_MODE_LSH 0 +#define MC13783_SWCTRL_SW2A_MODE_WID 2 +#define MC13783_SWCTRL_SW2A_STBY_MODE_LSH 2 +#define MC13783_SWCTRL_SW2A_STBY_MODE_WID 2 +#define MC13783_SWCTRL_SW2A_DVS_SPEED_LSH 6 +#define MC13783_SWCTRL_SW2A_DVS_SPEED_WID 2 +#define MC13783_SWCTRL_SW2A_PANIC_MODE_LSH 8 +#define MC13783_SWCTRL_SW2A_PANIC_MODE_WID 1 +#define MC13783_SWCTRL_SW2A_SOFTSTART_LSH 9 +#define MC13783_SWCTRL_SW2A_SOFTSTART_WID 1 +#define MC13783_SWCTRL_SW2B_MODE_LSH 10 +#define MC13783_SWCTRL_SW2B_MODE_WID 2 +#define MC13783_SWCTRL_SW2B_STBY_MODE_LSH 12 +#define MC13783_SWCTRL_SW2B_STBY_MODE_WID 2 +#define MC13783_SWCTRL_SW2B_DVS_SPEED_LSH 14 +#define MC13783_SWCTRL_SW2B_DVS_SPEED_WID 2 +#define MC13783_SWCTRL_SW2B_PANIC_MODE_LSH 16 +#define MC13783_SWCTRL_SW2B_PANIC_MODE_WID 1 +#define MC13783_SWCTRL_SW2B_SOFTSTART_LSH 17 +#define MC13783_SWCTRL_SW2B_SOFTSTART_WID 1 +#define MC13783_SWSET_SW3_LSH 18 +#define MC13783_SWSET_SW3_WID 2 +#define MC13783_SWCTRL_SW3_EN_LSH 20 +#define MC13783_SWCTRL_SW3_EN_WID 2 +#define MC13783_SWCTRL_SW3_EN_ENABLE 1 +#define MC13783_SWCTRL_SW3_EN_DISABLE 0 +#define MC13783_SWCTRL_SW3_STBY_LSH 21 +#define MC13783_SWCTRL_SW3_STBY_WID 1 +#define MC13783_SWCTRL_SW3_MODE_LSH 22 +#define MC13783_SWCTRL_SW3_MODE_WID 1 + +/* + * Switcher configuration + */ +#define MC13783_SWCTRL_SW_MODE_SYNC_RECT_EN 0 +#define MC13783_SWCTRL_SW_MODE_PULSE_NO_SKIP_EN 1 +#define MC13783_SWCTRL_SW_MODE_PULSE_SKIP_EN 2 +#define MC13783_SWCTRL_SW_MODE_LOW_POWER_EN 3 +#define MC13783_REGTRL_LP_MODE_ENABLE 1 +#define MC13783_REGTRL_LP_MODE_DISABLE 0 +#define MC13783_REGTRL_STBY_MODE_ENABLE 1 +#define MC13783_REGTRL_STBY_MODE_DISABLE 0 + +#endif /* __MC13783_POWER_DEFS_H__ */ diff --git a/drivers/mxc/pmic/mc13783/pmic_rtc.c b/drivers/mxc/pmic/mc13783/pmic_rtc.c new file mode 100644 index 000000000000..b55c21b4c4f0 --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_rtc.c @@ -0,0 +1,544 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13783/pmic_rtc.c + * @brief This is the main file of PMIC(mc13783) RTC driver. + * + * @ingroup PMIC_RTC + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include + +#include "pmic_rtc_defs.h" + +#define PMIC_LOAD_ERROR_MSG \ +"PMIC card was not correctly detected. Stop loading PMIC RTC driver\n" + +/* + * Global variables + */ +static int pmic_rtc_major; +static void callback_alarm_asynchronous(void *); +static void callback_alarm_synchronous(void *); +static unsigned int pmic_rtc_poll(struct file *file, poll_table * wait); +static DECLARE_WAIT_QUEUE_HEAD(queue_alarm); +static DECLARE_WAIT_QUEUE_HEAD(pmic_rtc_wait); +static pmic_event_callback_t alarm_callback; +static pmic_event_callback_t rtc_callback; +static bool pmic_rtc_done; +static struct class *pmic_rtc_class; + +static DECLARE_MUTEX(mutex); + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_rtc_set_time); +EXPORT_SYMBOL(pmic_rtc_get_time); +EXPORT_SYMBOL(pmic_rtc_set_time_alarm); +EXPORT_SYMBOL(pmic_rtc_get_time_alarm); +EXPORT_SYMBOL(pmic_rtc_wait_alarm); +EXPORT_SYMBOL(pmic_rtc_event_sub); +EXPORT_SYMBOL(pmic_rtc_event_unsub); + +/* + * Real Time Clock Pmic API + */ + +/*! + * This is the callback function called on TSI Pmic event, used in asynchronous + * call. + */ +static void callback_alarm_asynchronous(void *unused) +{ + pmic_rtc_done = true; +} + +/*! + * This is the callback function is used in test code for (un)sub. + */ +static void callback_test_sub(void) +{ + printk(KERN_INFO "*****************************************\n"); + printk(KERN_INFO "***** PMIC RTC 'Alarm IT CallBack' ******\n"); + printk(KERN_INFO "*****************************************\n"); +} + +/*! + * This is the callback function called on TSI Pmic event, used in synchronous + * call. + */ +static void callback_alarm_synchronous(void *unused) +{ + printk(KERN_INFO "*** Alarm IT Pmic ***\n"); + wake_up(&queue_alarm); +} + +/*! + * This function wait the Alarm event + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_wait_alarm(void) +{ + DEFINE_WAIT(wait); + alarm_callback.func = callback_alarm_synchronous; + alarm_callback.param = NULL; + CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, alarm_callback)); + prepare_to_wait(&queue_alarm, &wait, TASK_UNINTERRUPTIBLE); + schedule(); + finish_wait(&queue_alarm, &wait); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_TODAI, alarm_callback)); + return PMIC_SUCCESS; +} + +/*! + * This function set the real time clock of PMIC + * + * @param pmic_time value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_set_time(struct timeval *pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + tod_reg_val = pmic_time->tv_sec % 86400; + day_reg_val = pmic_time->tv_sec / 86400; + + mask = BITFMASK(MC13783_RTCTIME_TIME); + value = BITFVAL(MC13783_RTCTIME_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask)); + + mask = BITFMASK(MC13783_RTCDAY_DAY); + value = BITFVAL(MC13783_RTCDAY_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask)); + + return PMIC_SUCCESS; +} + +/*! + * This function get the real time clock of PMIC + * + * @param pmic_time return value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_get_time(struct timeval *pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + mask = BITFMASK(MC13783_RTCTIME_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_TIME, &value, mask)); + tod_reg_val = BITFEXT(value, MC13783_RTCTIME_TIME); + + mask = BITFMASK(MC13783_RTCDAY_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val = BITFEXT(value, MC13783_RTCDAY_DAY); + + pmic_time->tv_sec = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * + 86400)); + return PMIC_SUCCESS; +} + +/*! + * This function set the real time clock alarm of PMIC + * + * @param pmic_time value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_set_time_alarm(struct timeval *pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + if (down_interruptible(&mutex) < 0) + return ret; + + tod_reg_val = pmic_time->tv_sec % 86400; + day_reg_val = pmic_time->tv_sec / 86400; + + mask = BITFMASK(MC13783_RTCALARM_TIME); + value = BITFVAL(MC13783_RTCALARM_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask)); + + mask = BITFMASK(MC13783_RTCALARM_DAY); + value = BITFVAL(MC13783_RTCALARM_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask)); + up(&mutex); + return PMIC_SUCCESS; +} + +/*! + * This function get the real time clock alarm of PMIC + * + * @param pmic_time return value of date and time + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_get_time_alarm(struct timeval *pmic_time) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + + mask = BITFMASK(MC13783_RTCALARM_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_ALARM, &value, mask)); + tod_reg_val = BITFEXT(value, MC13783_RTCALARM_TIME); + + mask = BITFMASK(MC13783_RTCALARM_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY_ALARM, &value, mask)); + day_reg_val = BITFEXT(value, MC13783_RTCALARM_DAY); + + pmic_time->tv_sec = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * + 86400)); + + return PMIC_SUCCESS; +} + +/*! + * This function is used to un/subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * @param sub define if Un/subscribe event. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_event(t_rtc_int event, void *callback, bool sub) +{ + type_event rtc_event; + if (callback == NULL) { + return PMIC_ERROR; + } else { + rtc_callback.func = callback; + rtc_callback.param = NULL; + } + switch (event) { + case RTC_IT_ALARM: + rtc_event = EVENT_TODAI; + break; + case RTC_IT_1HZ: + rtc_event = EVENT_E1HZI; + break; + case RTC_IT_RST: + rtc_event = EVENT_RTCRSTI; + break; + default: + return PMIC_PARAMETER_ERROR; + } + if (sub == true) { + CHECK_ERROR(pmic_event_subscribe(rtc_event, rtc_callback)); + } else { + CHECK_ERROR(pmic_event_unsubscribe(rtc_event, rtc_callback)); + } + return PMIC_SUCCESS; +} + +/*! + * This function is used to subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_event_sub(t_rtc_int event, void *callback) +{ + CHECK_ERROR(pmic_rtc_event(event, callback, true)); + return PMIC_SUCCESS; +} + +/*! + * This function is used to un subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_rtc_event_unsub(t_rtc_int event, void *callback) +{ + CHECK_ERROR(pmic_rtc_event(event, callback, false)); + return PMIC_SUCCESS; +} + +/* Called without the kernel lock - fine */ +static unsigned int pmic_rtc_poll(struct file *file, poll_table * wait) +{ + /*poll_wait(file, &pmic_rtc_wait, wait); */ + + if (pmic_rtc_done) + return POLLIN | POLLRDNORM; + return 0; +} + +/*! + * This function implements IOCTL controls on a PMIC RTC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @param cmd the command + * @param arg the parameter + * @return This function returns 0 if successful. + */ +static int pmic_rtc_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + struct timeval *pmic_time = NULL; + + if (_IOC_TYPE(cmd) != 'p') + return -ENOTTY; + + if (arg) { + pmic_time = kmalloc(sizeof(struct timeval), GFP_KERNEL); + if (pmic_time == NULL) + return -ENOMEM; + + /* if (copy_from_user(pmic_time, (struct timeval *)arg, + sizeof(struct timeval))) { + return -EFAULT; + } */ + } + + switch (cmd) { + case PMIC_RTC_SET_TIME: + if (copy_from_user(pmic_time, (struct timeval *)arg, + sizeof(struct timeval))) { + return -EFAULT; + } + pr_debug("SET RTC\n"); + CHECK_ERROR(pmic_rtc_set_time(pmic_time)); + break; + case PMIC_RTC_GET_TIME: + if (copy_to_user((struct timeval *)arg, pmic_time, + sizeof(struct timeval))) { + return -EFAULT; + } + pr_debug("GET RTC\n"); + CHECK_ERROR(pmic_rtc_get_time(pmic_time)); + break; + case PMIC_RTC_SET_ALARM: + if (copy_from_user(pmic_time, (struct timeval *)arg, + sizeof(struct timeval))) { + return -EFAULT; + } + pr_debug("SET RTC ALARM\n"); + CHECK_ERROR(pmic_rtc_set_time_alarm(pmic_time)); + break; + case PMIC_RTC_GET_ALARM: + if (copy_to_user((struct timeval *)arg, pmic_time, + sizeof(struct timeval))) { + return -EFAULT; + } + pr_debug("GET RTC ALARM\n"); + CHECK_ERROR(pmic_rtc_get_time_alarm(pmic_time)); + break; + case PMIC_RTC_WAIT_ALARM: + printk(KERN_INFO "WAIT ALARM...\n"); + CHECK_ERROR(pmic_rtc_event_sub(RTC_IT_ALARM, + callback_test_sub)); + CHECK_ERROR(pmic_rtc_wait_alarm()); + printk(KERN_INFO "ALARM DONE\n"); + CHECK_ERROR(pmic_rtc_event_unsub(RTC_IT_ALARM, + callback_test_sub)); + break; + case PMIC_RTC_ALARM_REGISTER: + printk(KERN_INFO "PMIC RTC ALARM REGISTER\n"); + alarm_callback.func = callback_alarm_asynchronous; + alarm_callback.param = NULL; + CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, alarm_callback)); + break; + case PMIC_RTC_ALARM_UNREGISTER: + printk(KERN_INFO "PMIC RTC ALARM UNREGISTER\n"); + alarm_callback.func = callback_alarm_asynchronous; + alarm_callback.param = NULL; + CHECK_ERROR(pmic_event_unsubscribe + (EVENT_TODAI, alarm_callback)); + pmic_rtc_done = false; + break; + default: + pr_debug("%d unsupported ioctl command\n", (int)cmd); + return -EINVAL; + } + + if (arg) { + if (copy_to_user((struct timeval *)arg, pmic_time, + sizeof(struct timeval))) { + return -EFAULT; + } + kfree(pmic_time); + } + + return 0; +} + +/*! + * This function implements the open method on a PMIC RTC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_rtc_open(struct inode *inode, struct file *file) +{ + return 0; +} + +/*! + * This function implements the release method on a PMIC RTC device. + * + * @param inode pointer on the node + * @param file pointer on the file + * @return This function returns 0. + */ +static int pmic_rtc_release(struct inode *inode, struct file *file) +{ + return 0; +} + +/*! + * This function is called to put the RTC in a low power state. + * There is no need for power handlers for the RTC device. + * The RTC cannot be suspended. + * + * @param pdev the device structure used to give information on which RTC + * device (0 through 3 channels) to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int pmic_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +/*! + * This function is called to resume the RTC from a low power state. + * + * @param pdev the device structure used to give information on which RTC + * device (0 through 3 channels) to suspend + * + * @return The function always returns 0. + */ +static int pmic_rtc_resume(struct platform_device *pdev) +{ + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ + +static struct file_operations pmic_rtc_fops = { + .owner = THIS_MODULE, + .ioctl = pmic_rtc_ioctl, + .poll = pmic_rtc_poll, + .open = pmic_rtc_open, + .release = pmic_rtc_release, +}; + +static int pmic_rtc_remove(struct platform_device *pdev) +{ + device_destroy(pmic_rtc_class, MKDEV(pmic_rtc_major, 0)); + class_destroy(pmic_rtc_class); + unregister_chrdev(pmic_rtc_major, "pmic_rtc"); + return 0; +} + +static int pmic_rtc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *temp_class; + + pmic_rtc_major = register_chrdev(0, "pmic_rtc", &pmic_rtc_fops); + if (pmic_rtc_major < 0) { + printk(KERN_ERR "Unable to get a major for pmic_rtc\n"); + return pmic_rtc_major; + } + + pmic_rtc_class = class_create(THIS_MODULE, "pmic_rtc"); + if (IS_ERR(pmic_rtc_class)) { + printk(KERN_ERR "Error creating pmic rtc class.\n"); + ret = PTR_ERR(pmic_rtc_class); + goto err_out1; + } + + temp_class = device_create(pmic_rtc_class, NULL, + MKDEV(pmic_rtc_major, 0), NULL, + "pmic_rtc"); + if (IS_ERR(temp_class)) { + printk(KERN_ERR "Error creating pmic rtc class device.\n"); + ret = PTR_ERR(temp_class); + goto err_out2; + } + + printk(KERN_INFO "PMIC RTC successfully probed\n"); + return ret; + + err_out2: + class_destroy(pmic_rtc_class); + err_out1: + unregister_chrdev(pmic_rtc_major, "pmic_rtc"); + return ret; +} + +static struct platform_driver pmic_rtc_driver_ldm = { + .driver = { + .name = "pmic_rtc", + .owner = THIS_MODULE, + }, + .suspend = pmic_rtc_suspend, + .resume = pmic_rtc_resume, + .probe = pmic_rtc_probe, + .remove = pmic_rtc_remove, +}; + +static int __init pmic_rtc_init(void) +{ + pr_debug("PMIC RTC driver loading...\n"); + return platform_driver_register(&pmic_rtc_driver_ldm); +} +static void __exit pmic_rtc_exit(void) +{ + platform_driver_unregister(&pmic_rtc_driver_ldm); + pr_debug("PMIC RTC driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +subsys_initcall(pmic_rtc_init); +module_exit(pmic_rtc_exit); + +MODULE_DESCRIPTION("Pmic_rtc driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h b/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h new file mode 100644 index 000000000000..e20596a932ed --- /dev/null +++ b/drivers/mxc/pmic/mc13783/pmic_rtc_defs.h @@ -0,0 +1,47 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MC13783_RTC_DEFS_H__ +#define __MC13783_RTC_DEFS_H__ + +/*! + * @file mc13783/pmic_rtc_defs.h + * @brief This is the internal header of PMIC(mc13783) RTC driver. + * + * @ingroup PMIC_RTC + */ + +/* + * RTC Time + */ +#define MC13783_RTCTIME_TIME_LSH 0 +#define MC13783_RTCTIME_TIME_WID 17 + +/* + * RTC Alarm + */ +#define MC13783_RTCALARM_TIME_LSH 0 +#define MC13783_RTCALARM_TIME_WID 17 + +/* + * RTC Day + */ +#define MC13783_RTCDAY_DAY_LSH 0 +#define MC13783_RTCDAY_DAY_WID 15 + +/* + * RTC Day alarm + */ +#define MC13783_RTCALARM_DAY_LSH 0 +#define MC13783_RTCALARM_DAY_WID 15 + +#endif /* __MC13783_RTC_DEFS_H__ */ diff --git a/drivers/mxc/pmic/mc13892/Kconfig b/drivers/mxc/pmic/mc13892/Kconfig new file mode 100644 index 000000000000..930e06ab2282 --- /dev/null +++ b/drivers/mxc/pmic/mc13892/Kconfig @@ -0,0 +1,48 @@ +# +# PMIC Modules configuration +# + +config MXC_MC13892_ADC + tristate "MC13892 ADC support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 ADC module driver. This module provides kernel API + for the ADC system of MC13892. + It controls also the touch screen interface. + If you want MC13892 ADC support, you should say Y here + +config MXC_MC13892_RTC + tristate "MC13892 Real Time Clock (RTC) support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 RTC module driver. This module provides kernel API + for RTC part of MC13892. + If you want MC13892 RTC support, you should say Y here +config MXC_MC13892_LIGHT + tristate "MC13892 Light and Backlight support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 Light module driver. This module provides kernel API + for led and backlight control part of MC13892. + If you want MC13892 Light support, you should say Y here +config MXC_MC13892_BATTERY + tristate "MC13892 Battery API support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 battery module driver. This module provides kernel API + for battery control part of MC13892. + If you want MC13892 battery support, you should say Y here +config MXC_MC13892_CONNECTIVITY + tristate "MC13892 Connectivity API support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 connectivity module driver. This module provides kernel API + for USB/RS232 connectivity control part of MC13892. + If you want MC13892 connectivity support, you should say Y here +config MXC_MC13892_POWER + tristate "MC13892 Power API support" + depends on MXC_PMIC_MC13892 + ---help--- + This is the MC13892 power and supplies module driver. This module provides kernel API + for power and regulator control part of MC13892. + If you want MC13892 power support, you should say Y here diff --git a/drivers/mxc/pmic/mc13892/Makefile b/drivers/mxc/pmic/mc13892/Makefile new file mode 100644 index 000000000000..0ed2b7eb4c11 --- /dev/null +++ b/drivers/mxc/pmic/mc13892/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the mc13783 pmic drivers. +# + +obj-$(CONFIG_MXC_MC13892_ADC) += pmic_adc.o +#obj-$(CONFIG_MXC_MC13892_RTC) += pmic_rtc.o +obj-$(CONFIG_MXC_MC13892_LIGHT) += pmic_light.o +obj-$(CONFIG_MXC_MC13892_BATTERY) += pmic_battery.o +#obj-$(CONFIG_MXC_MC13892_CONNECTIVITY) += pmic_convity.o +#obj-$(CONFIG_MXC_MC13892_POWER) += pmic_power.o diff --git a/drivers/mxc/pmic/mc13892/pmic_adc.c b/drivers/mxc/pmic/mc13892/pmic_adc.c new file mode 100644 index 000000000000..c0f0f069b902 --- /dev/null +++ b/drivers/mxc/pmic/mc13892/pmic_adc.c @@ -0,0 +1,1073 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../core/pmic.h" + +#define DEF_ADC_0 0x008000 +#define DEF_ADC_3 0x0001c0 + +#define ADC_NB_AVAILABLE 2 + +#define MAX_CHANNEL 7 + +#define MC13892_ADC0_TS_M_LSH 14 +#define MC13892_ADC0_TS_M_WID 3 + +/* + * Maximun allowed variation in the three X/Y co-ordinates acquired from + * touch-screen + */ +#define DELTA_Y_MAX 50 +#define DELTA_X_MAX 50 + +/* + * ADC 0 + */ +#define ADC_CHRGICON 0x000002 +#define ADC_WAIT_TSI_0 0x001400 + +#define ADC_INC 0x030000 +#define ADC_BIS 0x800000 +#define ADC_CHRGRAW_D5 0x008000 + +/* + * ADC 1 + */ + +#define ADC_EN 0x000001 +#define ADC_SGL_CH 0x000002 +#define ADC_ADCCAL 0x000004 +#define ADC_ADSEL 0x000008 +#define ADC_TRIGMASK 0x000010 +#define ADC_CH_0_POS 5 +#define ADC_CH_0_MASK 0x0000E0 +#define ADC_CH_1_POS 8 +#define ADC_CH_1_MASK 0x000700 +#define ADC_DELAY_POS 11 +#define ADC_DELAY_MASK 0x07F800 +#define ADC_ATO 0x080000 +#define ASC_ADC 0x100000 +#define ADC_WAIT_TSI_1 0x200001 +#define ADC_NO_ADTRIG 0x200000 + +/* + * ADC 2 - 4 + */ +#define ADD1_RESULT_MASK 0x00000FFC +#define ADD2_RESULT_MASK 0x00FFC000 +#define ADC_TS_MASK 0x00FFCFFC + +#define ADC_WCOMP 0x040000 +#define ADC_WCOMP_H_POS 0 +#define ADC_WCOMP_L_POS 9 +#define ADC_WCOMP_H_MASK 0x00003F +#define ADC_WCOMP_L_MASK 0x007E00 + +#define ADC_MODE_MASK 0x00003F + +#define ADC_INT_BISDONEI 0x02 +#define ADC_TSMODE_MASK 0x007000 + +typedef enum adc_state { + ADC_FREE, + ADC_USED, + ADC_MONITORING, +} t_adc_state; + +typedef enum reading_mode { + /*! + * Enables lithium cell reading + */ + M_LITHIUM_CELL = 0x000001, + /*! + * Enables charge current reading + */ + M_CHARGE_CURRENT = 0x000002, + /*! + * Enables battery current reading + */ + M_BATTERY_CURRENT = 0x000004, +} t_reading_mode; + +typedef struct { + /*! + * Delay before first conversion + */ + unsigned int delay; + /*! + * sets the ATX bit for delay on all conversion + */ + bool conv_delay; + /*! + * Sets the single channel mode + */ + bool single_channel; + /*! + * Channel selection 1 + */ + t_channel channel_0; + /*! + * Channel selection 2 + */ + t_channel channel_1; + /*! + * Used to configure ADC mode with t_reading_mode + */ + t_reading_mode read_mode; + /*! + * Sets the Touch screen mode + */ + bool read_ts; + /*! + * Wait TSI event before touch screen reading + */ + bool wait_tsi; + /*! + * Sets CHRGRAW scaling to divide by 5 + * Only supported on 2.0 and higher + */ + bool chrgraw_devide_5; + /*! + * Return ADC values + */ + unsigned int value[8]; + /*! + * Return touch screen values + */ + t_touch_screen ts_value; +} t_adc_param; + +static int pmic_adc_filter(t_touch_screen *ts_curr); +int mc13892_adc_request(bool read_ts); +int mc13892_adc_release(int adc_index); +t_reading_mode mc13892_set_read_mode(t_channel channel); +PMIC_STATUS mc13892_adc_read_ts(t_touch_screen *touch_sample, int wait_tsi); + +/* internal function */ +static void callback_tsi(void *); +static void callback_adcdone(void *); +static void callback_adcbisdone(void *); + +static int swait; + +static int suspend_flag; + +static wait_queue_head_t suspendq; + +/* EXPORTED FUNCTIONS */ +EXPORT_SYMBOL(pmic_adc_init); +EXPORT_SYMBOL(pmic_adc_deinit); +EXPORT_SYMBOL(pmic_adc_convert); +EXPORT_SYMBOL(pmic_adc_convert_8x); +EXPORT_SYMBOL(pmic_adc_set_touch_mode); +EXPORT_SYMBOL(pmic_adc_get_touch_mode); +EXPORT_SYMBOL(pmic_adc_get_touch_sample); + +static DECLARE_COMPLETION(adcdone_it); +static DECLARE_COMPLETION(adcbisdone_it); +static DECLARE_COMPLETION(adc_tsi); +static pmic_event_callback_t tsi_event; +static pmic_event_callback_t event_adc; +static pmic_event_callback_t event_adc_bis; +static bool data_ready_adc_1; +static bool data_ready_adc_2; +static bool adc_ts; +static bool wait_ts; +static bool monitor_en; +static bool monitor_adc; +static DECLARE_MUTEX(convert_mutex); + +static DECLARE_WAIT_QUEUE_HEAD(queue_adc_busy); +static t_adc_state adc_dev[2]; + +static unsigned channel_num[] = { + 0, + 1, + 3, + 4, + 2, + 0, + 1, + 3, + 4, + -1, + 5, + 6, + 7, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1 +}; + +static bool pmic_adc_ready; + +int is_pmic_adc_ready() +{ + return pmic_adc_ready; +} +EXPORT_SYMBOL(is_pmic_adc_ready); + + +static int pmic_adc_suspend(struct platform_device *pdev, pm_message_t state) +{ + suspend_flag = 1; + CHECK_ERROR(pmic_write_reg(REG_ADC0, DEF_ADC_0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC1, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC2, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC3, DEF_ADC_3, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC4, 0, PMIC_ALL_BITS)); + + return 0; +}; + +static int pmic_adc_resume(struct platform_device *pdev) +{ + /* nothing for mc13892 adc */ + unsigned int adc_0_reg, adc_1_reg, reg_mask; + suspend_flag = 0; + + /* let interrupt of TSI again */ + adc_0_reg = ADC_WAIT_TSI_0; + reg_mask = ADC_WAIT_TSI_0; + CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, reg_mask)); + adc_1_reg = ADC_WAIT_TSI_1 | (ADC_BIS * adc_ts); + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, PMIC_ALL_BITS)); + + while (swait > 0) { + swait--; + wake_up_interruptible(&suspendq); + } + + return 0; +}; + +static void callback_tsi(void *unused) +{ + pr_debug("*** TSI IT mc13892 PMIC_ADC_GET_TOUCH_SAMPLE ***\n"); + if (wait_ts) { + complete(&adc_tsi); + pmic_event_mask(EVENT_TSI); + } +} + +static void callback_adcdone(void *unused) +{ + if (data_ready_adc_1) + complete(&adcdone_it); +} + +static void callback_adcbisdone(void *unused) +{ + pr_debug("* adcdone bis it callback *\n"); + if (data_ready_adc_2) + complete(&adcbisdone_it); +} + +static int pmic_adc_filter(t_touch_screen *ts_curr) +{ + unsigned int ydiff, xdiff; + unsigned int sample_sumx, sample_sumy; + + if (ts_curr->contact_resistance == 0) { + ts_curr->x_position = 0; + ts_curr->y_position = 0; + return 0; + } + + ydiff = abs(ts_curr->y_position1 - ts_curr->y_position2); + if (ydiff > DELTA_Y_MAX) { + pr_debug("pmic_adc_filter: Ret pos y\n"); + return -1; + } + + xdiff = abs(ts_curr->x_position1 - ts_curr->x_position2); + if (xdiff > DELTA_X_MAX) { + pr_debug("mc13892_adc_filter: Ret pos x\n"); + return -1; + } + + sample_sumx = ts_curr->x_position1 + ts_curr->x_position2; + sample_sumy = ts_curr->y_position1 + ts_curr->y_position2; + + ts_curr->y_position = sample_sumy / 2; + ts_curr->x_position = sample_sumx / 2; + + return 0; +} + +int pmic_adc_init(void) +{ + unsigned int reg_value = 0, i = 0; + + if (suspend_flag == 1) + return -EBUSY; + + for (i = 0; i < ADC_NB_AVAILABLE; i++) + adc_dev[i] = ADC_FREE; + + CHECK_ERROR(pmic_write_reg(REG_ADC0, DEF_ADC_0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC1, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC2, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC3, DEF_ADC_3, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_ADC4, 0, PMIC_ALL_BITS)); + reg_value = 0x001000; + + data_ready_adc_1 = false; + data_ready_adc_2 = false; + adc_ts = false; + wait_ts = false; + monitor_en = false; + monitor_adc = false; + + /* sub to ADCDone IT */ + event_adc.param = NULL; + event_adc.func = callback_adcdone; + CHECK_ERROR(pmic_event_subscribe(EVENT_ADCDONEI, event_adc)); + + /* sub to ADCDoneBis IT */ + event_adc_bis.param = NULL; + event_adc_bis.func = callback_adcbisdone; + CHECK_ERROR(pmic_event_subscribe(EVENT_ADCBISDONEI, event_adc_bis)); + + /* sub to Touch Screen IT */ + tsi_event.param = NULL; + tsi_event.func = callback_tsi; + CHECK_ERROR(pmic_event_subscribe(EVENT_TSI, tsi_event)); + + return PMIC_SUCCESS; +} + +PMIC_STATUS pmic_adc_deinit(void) +{ + CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCDONEI, event_adc)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_ADCBISDONEI, event_adc_bis)); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_TSI, tsi_event)); + + return PMIC_SUCCESS; +} + +int mc13892_adc_init_param(t_adc_param *adc_param) +{ + int i = 0; + + if (suspend_flag == 1) + return -EBUSY; + + adc_param->delay = 0; + adc_param->conv_delay = false; + adc_param->single_channel = false; + adc_param->channel_0 = BATTERY_VOLTAGE; + adc_param->channel_1 = BATTERY_VOLTAGE; + adc_param->read_mode = 0; + adc_param->wait_tsi = 0; + adc_param->chrgraw_devide_5 = true; + adc_param->read_ts = false; + adc_param->ts_value.x_position = 0; + adc_param->ts_value.y_position = 0; + adc_param->ts_value.contact_resistance = 0; + for (i = 0; i <= MAX_CHANNEL; i++) + adc_param->value[i] = 0; + + return 0; +} + +PMIC_STATUS mc13892_adc_convert(t_adc_param *adc_param) +{ + bool use_bis = false; + unsigned int adc_0_reg = 0, adc_1_reg = 0, result_reg = 0, i = 0; + unsigned int result = 0, temp = 0; + pmic_version_t mc13892_ver; + int ret; + + pr_debug("mc13892 ADC - mc13892_adc_convert ....\n"); + if (suspend_flag == 1) + return -EBUSY; + + if (adc_param->wait_tsi) { + /* configure adc to wait tsi interrupt */ + INIT_COMPLETION(adc_tsi); + + /*for ts don't use bis */ + /*put ts in interrupt mode */ + /* still kep reference? */ + adc_0_reg = 0x001400 | (ADC_BIS * 0); + pmic_event_unmask(EVENT_TSI); + CHECK_ERROR(pmic_write_reg(REG_ADC0, adc_0_reg, PMIC_ALL_BITS)); + /*for ts don't use bis */ + adc_1_reg = 0x200001 | (ADC_BIS * 0); + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, PMIC_ALL_BITS)); + pr_debug("wait tsi ....\n"); + wait_ts = true; + wait_for_completion_interruptible(&adc_tsi); + wait_ts = false; + } + down(&convert_mutex); + use_bis = mc13892_adc_request(adc_param->read_ts); + if (use_bis < 0) { + pr_debug("process has received a signal and got interrupted\n"); + ret = -EINTR; + goto out_up_convert_mutex; + } + + /* CONFIGURE ADC REG 0 */ + adc_0_reg = 0; + adc_1_reg = 0; + if (adc_param->read_ts == false) { + adc_0_reg = adc_param->read_mode & 0x00003F; + /* add auto inc */ + adc_0_reg |= ADC_INC; + if (use_bis) { + /* add adc bis */ + adc_0_reg |= ADC_BIS; + } + mc13892_ver = pmic_get_version(); + if (mc13892_ver.revision >= 20) + if (adc_param->chrgraw_devide_5) + adc_0_reg |= ADC_CHRGRAW_D5; + + if (adc_param->single_channel) + adc_1_reg |= ADC_SGL_CH; + + if (adc_param->conv_delay) + adc_1_reg |= ADC_ATO; + + if (adc_param->single_channel) + adc_1_reg |= ADC_SGL_CH; + + adc_1_reg |= (adc_param->channel_0 << ADC_CH_0_POS) & + ADC_CH_0_MASK; + adc_1_reg |= (adc_param->channel_1 << ADC_CH_1_POS) & + ADC_CH_1_MASK; + } else { + adc_0_reg = 0x002400 | (ADC_BIS * use_bis) | ADC_INC; + } + + if (adc_param->channel_0 == channel_num[CHARGE_CURRENT]) + adc_0_reg |= ADC_CHRGICON; + + /*Change has been made here */ + ret = pmic_write_reg(REG_ADC0, adc_0_reg, + ADC_INC | ADC_BIS | ADC_CHRGRAW_D5 | 0xfff00ff); + if (ret != PMIC_SUCCESS) { + pr_debug("pmic_write_reg"); + goto out_mc13892_adc_release; + } + + /* CONFIGURE ADC REG 1 */ + if (adc_param->read_ts == false) { + adc_1_reg |= ADC_NO_ADTRIG; + adc_1_reg |= ADC_EN; + adc_1_reg |= (adc_param->delay << ADC_DELAY_POS) & + ADC_DELAY_MASK; + if (use_bis) + adc_1_reg |= ADC_BIS; + } else { + /* configure and start convert to read x and y position */ + /* configure to read 2 value in channel selection 1 & 2 */ + adc_1_reg = 0x100409 | (ADC_BIS * use_bis) | ADC_NO_ADTRIG; + /* set ATOx = 5, it could be better for ts ADC */ + adc_1_reg |= 0x002800; + } + + if (adc_param->channel_0 == channel_num[CHARGE_CURRENT]) { + adc_param->channel_1 = channel_num[CHARGE_CURRENT]; + adc_1_reg &= ~(ADC_CH_0_MASK | ADC_CH_1_MASK | ADC_NO_ADTRIG | + ADC_TRIGMASK | ADC_EN | ADC_SGL_CH | ADC_ADCCAL); + adc_1_reg |= ((adc_param->channel_0 << ADC_CH_0_POS) | + (adc_param->channel_1 << ADC_CH_1_POS)); + adc_1_reg |= (ADC_EN | ADC_SGL_CH | ADC_ADCCAL); + + if (use_bis == 0) { + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, + 0xFFFFFF)); + } else { + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, + 0xFFFFFF)); + temp = 0x800000; + CHECK_ERROR(pmic_write_reg(REG_ADC3, temp, 0xFFFFFF)); + } + + adc_1_reg &= ~(ADC_NO_ADTRIG | ASC_ADC | ADC_ADCCAL); + adc_1_reg |= (ADC_NO_ADTRIG | ASC_ADC); + if (use_bis == 0) { + data_ready_adc_1 = true; + INIT_COMPLETION(adcdone_it); + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, + 0xFFFFFF)); + pr_debug("wait adc done\n"); + wait_for_completion_interruptible(&adcdone_it); + data_ready_adc_1 = false; + } else { + data_ready_adc_2 = true; + INIT_COMPLETION(adcbisdone_it); + CHECK_ERROR(pmic_write_reg(REG_ADC1, adc_1_reg, + 0xFFFFFF)); + temp = 0x800000; + CHECK_ERROR(pmic_write_reg(REG_ADC3, temp, 0xFFFFFF)); + pr_debug("wait adc done bis\n"); + wait_for_completion_interruptible(&adcbisdone_it); + data_ready_adc_2 = false; + } + } else { + if (use_bis == 0) { + data_ready_adc_1 = false; + adc_1_reg |= ASC_ADC; + data_ready_adc_1 = true; + pr_debug("Write Reg %i = %x\n", REG_ADC1, adc_1_reg); + INIT_COMPLETION(adcdone_it); + ret = pmic_write_reg(REG_ADC1, adc_1_reg, + ADC_SGL_CH | ADC_ATO | + ADC_ADSEL | ADC_CH_0_MASK | + ADC_CH_1_MASK | + ADC_NO_ADTRIG | ADC_EN | + ADC_DELAY_MASK | ASC_ADC | + ADC_BIS); + if (ret != PMIC_SUCCESS) { + pr_debug("pmic_write_reg"); + goto out_mc13892_adc_release; + } + + pr_debug("wait adc done\n"); + wait_for_completion_interruptible(&adcdone_it); + data_ready_adc_1 = false; + } else { + data_ready_adc_2 = false; + adc_1_reg |= ASC_ADC; + data_ready_adc_2 = true; + INIT_COMPLETION(adcbisdone_it); + ret = pmic_write_reg(REG_ADC1, adc_1_reg, 0xFFFFFF); + if (ret != PMIC_SUCCESS) { + pr_debug("pmic_write_reg"); + goto out_mc13892_adc_release; + } + + temp = 0x800000; + ret = pmic_write_reg(REG_ADC3, temp, 0xFFFFFF); + if (ret != PMIC_SUCCESS) { + pr_info("pmic_write_reg"); + goto out_mc13892_adc_release; + } + + pr_debug("wait adc done bis\n"); + wait_for_completion_interruptible(&adcbisdone_it); + data_ready_adc_2 = false; + } + } + + /* read result and store in adc_param */ + result = 0; + if (use_bis == 0) + result_reg = REG_ADC2; + else + result_reg = REG_ADC4; + + ret = pmic_write_reg(REG_ADC1, 4 << ADC_CH_1_POS, + ADC_CH_0_MASK | ADC_CH_1_MASK); + if (ret != PMIC_SUCCESS) { + pr_debug("pmic_write_reg"); + goto out_mc13892_adc_release; + } + + for (i = 0; i <= 3; i++) { + ret = pmic_read_reg(result_reg, &result, PMIC_ALL_BITS); + if (ret != PMIC_SUCCESS) { + pr_debug("pmic_write_reg"); + goto out_mc13892_adc_release; + } + + adc_param->value[i] = ((result & ADD1_RESULT_MASK) >> 2); + adc_param->value[i + 4] = ((result & ADD2_RESULT_MASK) >> 14); + pr_debug("value[%d] = %d, value[%d] = %d\n", + i, adc_param->value[i], + i + 4, adc_param->value[i + 4]); + } + if (adc_param->read_ts) { + adc_param->ts_value.x_position = adc_param->value[0]; + adc_param->ts_value.x_position1 = adc_param->value[0]; + adc_param->ts_value.x_position2 = adc_param->value[1]; + adc_param->ts_value.y_position = adc_param->value[3]; + adc_param->ts_value.y_position1 = adc_param->value[3]; + adc_param->ts_value.y_position2 = adc_param->value[4]; + adc_param->ts_value.contact_resistance = adc_param->value[6]; + ret = pmic_write_reg(REG_ADC0, 0x0, ADC_TSMODE_MASK); + if (ret != PMIC_SUCCESS) { + pr_debug("pmic_write_reg"); + goto out_mc13892_adc_release; + } + } + + /*if (adc_param->read_ts) { + adc_param->ts_value.x_position = adc_param->value[2]; + adc_param->ts_value.y_position = adc_param->value[5]; + adc_param->ts_value.contact_resistance = adc_param->value[6]; + } */ + ret = PMIC_SUCCESS; +out_mc13892_adc_release: + mc13892_adc_release(use_bis); +out_up_convert_mutex: + up(&convert_mutex); + + return ret; +} + +t_reading_mode mc13892_set_read_mode(t_channel channel) +{ + t_reading_mode read_mode = 0; + + switch (channel) { + case CHARGE_CURRENT: + read_mode = M_CHARGE_CURRENT; + break; + case BATTERY_CURRENT: + read_mode = M_BATTERY_CURRENT; + break; + default: + read_mode = 0; + } + + return read_mode; +} + +PMIC_STATUS pmic_adc_convert(t_channel channel, unsigned short *result) +{ + t_adc_param adc_param; + PMIC_STATUS ret; + unsigned int i; + + if (suspend_flag == 1) + return -EBUSY; + + channel = channel_num[channel]; + if (channel == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + mc13892_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert\n"); + adc_param.read_ts = false; + adc_param.single_channel = true; + adc_param.read_mode = mc13892_set_read_mode(channel); + + /* Find the group */ + if (channel <= 7) + adc_param.channel_0 = channel; + else + return PMIC_PARAMETER_ERROR; + + ret = mc13892_adc_convert(&adc_param); + for (i = 0; i <= 7; i++) + result[i] = adc_param.value[i]; + + return ret; +} + +PMIC_STATUS pmic_adc_convert_8x(t_channel channel, unsigned short *result) +{ + t_adc_param adc_param; + int i; + PMIC_STATUS ret; + if (suspend_flag == 1) + return -EBUSY; + + channel = channel_num[channel]; + + if (channel == -1) { + pr_debug("Wrong channel ID\n"); + return PMIC_PARAMETER_ERROR; + } + mc13892_adc_init_param(&adc_param); + pr_debug("pmic_adc_convert_8x\n"); + adc_param.read_ts = false; + adc_param.single_channel = true; + adc_param.read_mode = mc13892_set_read_mode(channel); + + if (channel <= 7) { + adc_param.channel_0 = channel; + adc_param.channel_1 = channel; + } else + return PMIC_PARAMETER_ERROR; + + ret = mc13892_adc_convert(&adc_param); + for (i = 0; i <= 7; i++) + result[i] = adc_param.value[i]; + + return ret; +} + +PMIC_STATUS pmic_adc_set_touch_mode(t_touch_mode touch_mode) +{ + if (suspend_flag == 1) + return -EBUSY; + + CHECK_ERROR(pmic_write_reg(REG_ADC0, + BITFVAL(MC13892_ADC0_TS_M, touch_mode), + BITFMASK(MC13892_ADC0_TS_M))); + return PMIC_SUCCESS; +} + +PMIC_STATUS pmic_adc_get_touch_mode(t_touch_mode *touch_mode) +{ + unsigned int value; + if (suspend_flag == 1) + return -EBUSY; + + CHECK_ERROR(pmic_read_reg(REG_ADC0, &value, PMIC_ALL_BITS)); + + *touch_mode = BITFEXT(value, MC13892_ADC0_TS_M); + + return PMIC_SUCCESS; +} + +PMIC_STATUS pmic_adc_get_touch_sample(t_touch_screen *touch_sample, int wait) +{ + if (mc13892_adc_read_ts(touch_sample, wait) != 0) + return PMIC_ERROR; + if (0 == pmic_adc_filter(touch_sample)) + return PMIC_SUCCESS; + else + return PMIC_ERROR; +} + +PMIC_STATUS mc13892_adc_read_ts(t_touch_screen *ts_value, int wait_tsi) +{ + t_adc_param param; + pr_debug("mc13892_adc : mc13892_adc_read_ts\n"); + if (suspend_flag == 1) + return -EBUSY; + + if (wait_ts) { + pr_debug("mc13892_adc : error TS busy \n"); + return PMIC_ERROR; + } + mc13892_adc_init_param(¶m); + param.wait_tsi = wait_tsi; + param.read_ts = true; + if (mc13892_adc_convert(¶m) != 0) + return PMIC_ERROR; + /* check if x-y is ok */ + if (param.ts_value.contact_resistance < 1000) { + ts_value->x_position = param.ts_value.x_position; + ts_value->x_position1 = param.ts_value.x_position1; + ts_value->x_position2 = param.ts_value.x_position2; + + ts_value->y_position = param.ts_value.y_position; + ts_value->y_position1 = param.ts_value.y_position1; + ts_value->y_position2 = param.ts_value.y_position2; + + ts_value->contact_resistance = + param.ts_value.contact_resistance + 1; + + } else { + ts_value->x_position = 0; + ts_value->y_position = 0; + ts_value->contact_resistance = 0; + + } + return PMIC_SUCCESS; +} + +int mc13892_adc_request(bool read_ts) +{ + int adc_index = -1; + if (read_ts != 0) { + /*for ts we use bis=0 */ + if (adc_dev[0] == ADC_USED) + return -1; + /*no wait here */ + adc_dev[0] = ADC_USED; + adc_index = 0; + } else { + /*for other adc use bis = 1 */ + if (adc_dev[1] == ADC_USED) { + return -1; + /*no wait here */ + } + adc_dev[1] = ADC_USED; + adc_index = 1; + } + pr_debug("mc13892_adc : request ADC %d\n", adc_index); + return adc_index; +} + +int mc13892_adc_release(int adc_index) +{ + while (suspend_flag == 1) { + swait++; + /* Block if the device is suspended */ + if (wait_event_interruptible(suspendq, (suspend_flag == 0))) + return -ERESTARTSYS; + } + + pr_debug("mc13892_adc : release ADC %d\n", adc_index); + if ((adc_dev[adc_index] == ADC_MONITORING) || + (adc_dev[adc_index] == ADC_USED)) { + adc_dev[adc_index] = ADC_FREE; + wake_up(&queue_adc_busy); + return 0; + } + return -1; +} + +#ifdef DEBUG +static t_adc_param adc_param_db; + +static ssize_t adc_info(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int *value = adc_param_db.value; + + pr_debug("adc_info\n"); + + pr_debug("ch0\t\t%d\n", adc_param_db.channel_0); + pr_debug("ch1\t\t%d\n", adc_param_db.channel_1); + pr_debug("d5\t\t%d\n", adc_param_db.chrgraw_devide_5); + pr_debug("conv delay\t%d\n", adc_param_db.conv_delay); + pr_debug("delay\t\t%d\n", adc_param_db.delay); + pr_debug("read mode\t%d\n", adc_param_db.read_mode); + pr_debug("read ts\t\t%d\n", adc_param_db.read_ts); + pr_debug("single ch\t%d\n", adc_param_db.single_channel); + pr_debug("wait ts int\t%d\n", adc_param_db.wait_tsi); + pr_debug("value0-3:\t%d\t%d\t%d\t%d\n", value[0], value[1], + value[2], value[3]); + pr_debug("value4-7:\t%d\t%d\t%d\t%d\n", value[4], value[5], + value[6], value[7]); + + return 0; +} + +enum { + ADC_SET_CH0 = 0, + ADC_SET_CH1, + ADC_SET_DV5, + ADC_SET_CON_DELAY, + ADC_SET_DELAY, + ADC_SET_RM, + ADC_SET_RT, + ADC_SET_S_CH, + ADC_SET_WAIT_TS, + ADC_INIT_P, + ADC_START, + ADC_TS, + ADC_TS_READ, + ADC_TS_CAL, + ADC_CMD_MAX +}; + +static const char *const adc_cmd[ADC_CMD_MAX] = { + [ADC_SET_CH0] = "ch0", + [ADC_SET_CH1] = "ch1", + [ADC_SET_DV5] = "dv5", + [ADC_SET_CON_DELAY] = "cd", + [ADC_SET_DELAY] = "dl", + [ADC_SET_RM] = "rm", + [ADC_SET_RT] = "rt", + [ADC_SET_S_CH] = "sch", + [ADC_SET_WAIT_TS] = "wt", + [ADC_INIT_P] = "init", + [ADC_START] = "start", + [ADC_TS] = "touch", + [ADC_TS_READ] = "touchr", + [ADC_TS_CAL] = "cal" +}; + +static int cmd(unsigned int index, int value) +{ + t_touch_screen ts; + + switch (index) { + case ADC_SET_CH0: + adc_param_db.channel_0 = value; + break; + case ADC_SET_CH1: + adc_param_db.channel_1 = value; + break; + case ADC_SET_DV5: + adc_param_db.chrgraw_devide_5 = value; + break; + case ADC_SET_CON_DELAY: + adc_param_db.conv_delay = value; + break; + case ADC_SET_RM: + adc_param_db.read_mode = value; + break; + case ADC_SET_RT: + adc_param_db.read_ts = value; + break; + case ADC_SET_S_CH: + adc_param_db.single_channel = value; + break; + case ADC_SET_WAIT_TS: + adc_param_db.wait_tsi = value; + break; + case ADC_INIT_P: + mc13892_adc_init_param(&adc_param_db); + break; + case ADC_START: + mc13892_adc_convert(&adc_param_db); + break; + case ADC_TS: + pmic_adc_get_touch_sample(&ts, 1); + pr_debug("x = %d\n", ts.x_position); + pr_debug("y = %d\n", ts.y_position); + pr_debug("p = %d\n", ts.contact_resistance); + break; + case ADC_TS_READ: + pmic_adc_get_touch_sample(&ts, 0); + pr_debug("x = %d\n", ts.x_position); + pr_debug("y = %d\n", ts.y_position); + pr_debug("p = %d\n", ts.contact_resistance); + break; + case ADC_TS_CAL: + break; + default: + pr_debug("error command\n"); + break; + } + return 0; +} + +static ssize_t adc_ctl(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int state = 0; + const char *const *s; + char *p, *q; + int error; + int len, value = 0; + + pr_debug("adc_ctl\n"); + + q = NULL; + q = memchr(buf, ' ', count); + + if (q != NULL) { + len = q - buf; + q += 1; + value = simple_strtoul(q, NULL, 10); + } else { + p = memchr(buf, '\n', count); + len = p ? p - buf : count; + } + + for (s = &adc_cmd[state]; state < ADC_CMD_MAX; s++, state++) { + if (*s && !strncmp(buf, *s, len)) + break; + } + if (state < ADC_CMD_MAX && *s) + error = cmd(state, value); + else + error = -EINVAL; + + return count; +} + +#else +static ssize_t adc_info(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return 0; +} + +static ssize_t adc_ctl(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + return count; +} + +#endif + +static DEVICE_ATTR(adc, 0644, adc_info, adc_ctl); + +static int pmic_adc_module_probe(struct platform_device *pdev) +{ + int ret = 0; + + pr_debug("PMIC ADC start probe\n"); + ret = device_create_file(&(pdev->dev), &dev_attr_adc); + if (ret) { + pr_debug("Can't create device file!\n"); + return -ENODEV; + } + + init_waitqueue_head(&suspendq); + + ret = pmic_adc_init(); + if (ret != PMIC_SUCCESS) { + pr_debug("Error in pmic_adc_init.\n"); + goto rm_dev_file; + } + + pmic_adc_ready = 1; + pr_debug("PMIC ADC successfully probed\n"); + return 0; + +rm_dev_file: + device_remove_file(&(pdev->dev), &dev_attr_adc); + return ret; +} + +static int pmic_adc_module_remove(struct platform_device *pdev) +{ + pmic_adc_deinit(); + pmic_adc_ready = 0; + pr_debug("PMIC ADC successfully removed\n"); + return 0; +} + +static struct platform_driver pmic_adc_driver_ldm = { + .driver = { + .name = "pmic_adc", + }, + .suspend = pmic_adc_suspend, + .resume = pmic_adc_resume, + .probe = pmic_adc_module_probe, + .remove = pmic_adc_module_remove, +}; + +static int __init pmic_adc_module_init(void) +{ + pr_debug("PMIC ADC driver loading...\n"); + return platform_driver_register(&pmic_adc_driver_ldm); +} + +static void __exit pmic_adc_module_exit(void) +{ + platform_driver_unregister(&pmic_adc_driver_ldm); + pr_debug("PMIC ADC driver successfully unloaded\n"); +} + +module_init(pmic_adc_module_init); +module_exit(pmic_adc_module_exit); + +MODULE_DESCRIPTION("PMIC ADC device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13892/pmic_battery.c b/drivers/mxc/pmic/mc13892/pmic_battery.c new file mode 100644 index 000000000000..246bd2731ee4 --- /dev/null +++ b/drivers/mxc/pmic/mc13892/pmic_battery.c @@ -0,0 +1,797 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * Includes + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BIT_CHG_VOL_LSH 0 +#define BIT_CHG_VOL_WID 3 + +#define BIT_CHG_CURR_LSH 3 +#define BIT_CHG_CURR_WID 4 + +#define BIT_CHG_PLIM_LSH 15 +#define BIT_CHG_PLIM_WID 2 + +#define BIT_CHG_DETS_LSH 6 +#define BIT_CHG_DETS_WID 1 +#define BIT_CHG_CURRS_LSH 11 +#define BIT_CHG_CURRS_WID 1 + +#define TRICKLE_CHG_EN_LSH 7 +#define LOW_POWER_BOOT_ACK_LSH 8 +#define BAT_TH_CHECK_DIS_LSH 9 +#define BATTFET_CTL_EN_LSH 10 +#define BATTFET_CTL_LSH 11 +#define REV_MOD_EN_LSH 13 +#define PLIM_DIS_LSH 17 +#define CHG_LED_EN_LSH 18 +#define RESTART_CHG_STAT_LSH 20 +#define AUTO_CHG_DIS_LSH 21 +#define CYCLING_DIS_LSH 22 +#define VI_PROGRAM_EN_LSH 23 + +#define TRICKLE_CHG_EN_WID 1 +#define LOW_POWER_BOOT_ACK_WID 1 +#define BAT_TH_CHECK_DIS_WID 1 +#define BATTFET_CTL_EN_WID 1 +#define BATTFET_CTL_WID 1 +#define REV_MOD_EN_WID 1 +#define PLIM_DIS_WID 1 +#define CHG_LED_EN_WID 1 +#define RESTART_CHG_STAT_WID 1 +#define AUTO_CHG_DIS_WID 1 +#define CYCLING_DIS_WID 1 +#define VI_PROGRAM_EN_WID 1 + +#define ACC_STARTCC_LSH 0 +#define ACC_STARTCC_WID 1 +#define ACC_RSTCC_LSH 1 +#define ACC_RSTCC_WID 1 +#define ACC_CCFAULT_LSH 7 +#define ACC_CCFAULT_WID 7 +#define ACC_CCOUT_LSH 8 +#define ACC_CCOUT_WID 16 +#define ACC1_ONEC_LSH 0 +#define ACC1_ONEC_WID 15 + +#define ACC_CALIBRATION 0x17 +#define ACC_START_COUNTER 0x07 +#define ACC_STOP_COUNTER 0x2 +#define ACC_CONTROL_BIT_MASK 0x1f +#define ACC_ONEC_VALUE 2621 +#define ACC_COULOMB_PER_LSB 1 +#define ACC_CALIBRATION_DURATION_MSECS 20 + +#define BAT_VOLTAGE_UNIT_UV 4692 +#define BAT_CURRENT_UNIT_UA 5870 +#define CHG_VOLTAGE_UINT_UV 23474 +#define CHG_MIN_CURRENT_UA 3500 + +#define COULOMB_TO_UAH(c) (10000 * c / 36) + +enum chg_setting { + TRICKLE_CHG_EN, + LOW_POWER_BOOT_ACK, + BAT_TH_CHECK_DIS, + BATTFET_CTL_EN, + BATTFET_CTL, + REV_MOD_EN, + PLIM_DIS, + CHG_LED_EN, + RESTART_CHG_STAT, + AUTO_CHG_DIS, + CYCLING_DIS, + VI_PROGRAM_EN +}; + +/* Flag used to indicate if Charger workaround is active. */ +int chg_wa_is_active; +/* Flag used to indicate if Charger workaround timer is on. */ +int chg_wa_timer; +int disable_chg_timer; +struct workqueue_struct *chg_wq; +struct delayed_work chg_work; + +static int pmic_set_chg_current(unsigned short curr) +{ + unsigned int mask; + unsigned int value; + + value = BITFVAL(BIT_CHG_CURR, curr); + mask = BITFMASK(BIT_CHG_CURR); + CHECK_ERROR(pmic_write_reg(REG_CHARGE, value, mask)); + + return 0; +} + +static int pmic_set_chg_misc(enum chg_setting type, unsigned short flag) +{ + + unsigned int reg_value = 0; + unsigned int mask = 0; + + switch (type) { + case TRICKLE_CHG_EN: + reg_value = BITFVAL(TRICKLE_CHG_EN, flag); + mask = BITFMASK(TRICKLE_CHG_EN); + break; + case LOW_POWER_BOOT_ACK: + reg_value = BITFVAL(LOW_POWER_BOOT_ACK, flag); + mask = BITFMASK(LOW_POWER_BOOT_ACK); + break; + case BAT_TH_CHECK_DIS: + reg_value = BITFVAL(BAT_TH_CHECK_DIS, flag); + mask = BITFMASK(BAT_TH_CHECK_DIS); + break; + case BATTFET_CTL_EN: + reg_value = BITFVAL(BATTFET_CTL_EN, flag); + mask = BITFMASK(BATTFET_CTL_EN); + break; + case BATTFET_CTL: + reg_value = BITFVAL(BATTFET_CTL, flag); + mask = BITFMASK(BATTFET_CTL); + break; + case REV_MOD_EN: + reg_value = BITFVAL(REV_MOD_EN, flag); + mask = BITFMASK(REV_MOD_EN); + break; + case PLIM_DIS: + reg_value = BITFVAL(PLIM_DIS, flag); + mask = BITFMASK(PLIM_DIS); + break; + case CHG_LED_EN: + reg_value = BITFVAL(CHG_LED_EN, flag); + mask = BITFMASK(CHG_LED_EN); + break; + case RESTART_CHG_STAT: + reg_value = BITFVAL(RESTART_CHG_STAT, flag); + mask = BITFMASK(RESTART_CHG_STAT); + break; + case AUTO_CHG_DIS: + reg_value = BITFVAL(AUTO_CHG_DIS, flag); + mask = BITFMASK(AUTO_CHG_DIS); + break; + case CYCLING_DIS: + reg_value = BITFVAL(CYCLING_DIS, flag); + mask = BITFMASK(CYCLING_DIS); + break; + case VI_PROGRAM_EN: + reg_value = BITFVAL(VI_PROGRAM_EN, flag); + mask = BITFMASK(VI_PROGRAM_EN); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_write_reg(REG_CHARGE, reg_value, mask)); + + return 0; +} + +static int pmic_get_batt_voltage(unsigned short *voltage) +{ + t_channel channel; + unsigned short result[8]; + + channel = BATTERY_VOLTAGE; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *voltage = result[0]; + + return 0; +} + +static int pmic_get_batt_current(unsigned short *curr) +{ + t_channel channel; + unsigned short result[8]; + + channel = BATTERY_CURRENT; + CHECK_ERROR(pmic_adc_convert(channel, result)); + *curr = result[0]; + + return 0; +} + +static int coulomb_counter_calibration; +static unsigned int coulomb_counter_start_time_msecs; + +static int pmic_start_coulomb_counter(void) +{ + /* set scaler */ + CHECK_ERROR(pmic_write_reg(REG_ACC1, + ACC_COULOMB_PER_LSB * ACC_ONEC_VALUE, BITFMASK(ACC1_ONEC))); + + CHECK_ERROR(pmic_write_reg( + REG_ACC0, ACC_START_COUNTER, ACC_CONTROL_BIT_MASK)); + coulomb_counter_start_time_msecs = jiffies_to_msecs(jiffies); + pr_debug("coulomb counter start time %u\n", + coulomb_counter_start_time_msecs); + return 0; +} + +static int pmic_stop_coulomb_counter(void) +{ + CHECK_ERROR(pmic_write_reg( + REG_ACC0, ACC_STOP_COUNTER, ACC_CONTROL_BIT_MASK)); + return 0; +} + +static int pmic_calibrate_coulomb_counter(void) +{ + int ret; + unsigned int value; + + /* set scaler */ + CHECK_ERROR(pmic_write_reg(REG_ACC1, + 0x1, BITFMASK(ACC1_ONEC))); + + CHECK_ERROR(pmic_write_reg( + REG_ACC0, ACC_CALIBRATION, ACC_CONTROL_BIT_MASK)); + msleep(ACC_CALIBRATION_DURATION_MSECS); + + ret = pmic_read_reg(REG_ACC0, &value, BITFMASK(ACC_CCOUT)); + if (ret != 0) + return -1; + value = BITFEXT(value, ACC_CCOUT); + pr_debug("calibrate value = %x\n", value); + coulomb_counter_calibration = (int)((s16)((u16) value)); + pr_debug("coulomb_counter_calibration = %d\n", + coulomb_counter_calibration); + + return 0; + +} + +static int pmic_get_charger_coulomb(int *coulomb) +{ + int ret; + unsigned int value; + int calibration; + unsigned int time_diff_msec; + + ret = pmic_read_reg(REG_ACC0, &value, BITFMASK(ACC_CCOUT)); + if (ret != 0) + return -1; + value = BITFEXT(value, ACC_CCOUT); + pr_debug("counter value = %x\n", value); + *coulomb = ((s16)((u16)value)) * ACC_COULOMB_PER_LSB; + + if (abs(*coulomb) >= ACC_COULOMB_PER_LSB) { + /* calibrate */ + time_diff_msec = jiffies_to_msecs(jiffies); + time_diff_msec = + (time_diff_msec > coulomb_counter_start_time_msecs) ? + (time_diff_msec - coulomb_counter_start_time_msecs) : + (0xffffffff - coulomb_counter_start_time_msecs + + time_diff_msec); + calibration = coulomb_counter_calibration * (int)time_diff_msec + / (ACC_ONEC_VALUE * ACC_CALIBRATION_DURATION_MSECS); + *coulomb -= calibration; + } + + return 0; +} + +static int pmic_restart_charging(void) +{ + pmic_set_chg_misc(BAT_TH_CHECK_DIS, 1); + pmic_set_chg_misc(AUTO_CHG_DIS, 0); + pmic_set_chg_misc(VI_PROGRAM_EN, 1); + pmic_set_chg_current(0x8); + pmic_set_chg_misc(RESTART_CHG_STAT, 1); + pmic_set_chg_misc(PLIM_DIS, 3); + return 0; +} + +struct mc13892_dev_info { + struct device *dev; + + unsigned short voltage_raw; + int voltage_uV; + unsigned short current_raw; + int current_uA; + int battery_status; + int full_counter; + int charger_online; + int charger_voltage_uV; + int accum_current_uAh; + + struct power_supply bat; + struct power_supply charger; + + struct workqueue_struct *monitor_wqueue; + struct delayed_work monitor_work; +}; + +#define mc13892_SENSER 25 +#define to_mc13892_dev_info(x) container_of((x), struct mc13892_dev_info, \ + bat); + +static enum power_supply_property mc13892_battery_props[] = { + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_CHARGE_NOW, + POWER_SUPPLY_PROP_STATUS, +}; + +static enum power_supply_property mc13892_charger_props[] = { + POWER_SUPPLY_PROP_ONLINE, +}; + +static int pmic_get_chg_value(unsigned int *value) +{ + t_channel channel; + unsigned short result[8], max1 = 0, min1 = 0, max2 = 0, min2 = 0, i; + unsigned int average = 0, average1 = 0, average2 = 0; + + channel = CHARGE_CURRENT; + CHECK_ERROR(pmic_adc_convert(channel, result)); + + + for (i = 0; i < 8; i++) { + if ((result[i] & 0x200) != 0) { + result[i] = 0x400 - result[i]; + average2 += result[i]; + if ((max2 == 0) || (max2 < result[i])) + max2 = result[i]; + if ((min2 == 0) || (min2 > result[i])) + min2 = result[i]; + } else { + average1 += result[i]; + if ((max1 == 0) || (max1 < result[i])) + max1 = result[i]; + if ((min1 == 0) || (min1 > result[i])) + min1 = result[i]; + } + } + + if (max1 != 0) { + average1 -= max1; + if (max2 != 0) + average2 -= max2; + else + average1 -= min1; + } else + average2 -= max2 + min2; + + if (average1 >= average2) { + average = (average1 - average2) / 6; + *value = average; + } else { + average = (average2 - average1) / 6; + *value = ((~average) + 1) & 0x3FF; + } + + return 0; +} + +static void chg_thread(struct work_struct *work) +{ + int ret; + unsigned int value = 0; + int dets; + + if (disable_chg_timer) { + disable_chg_timer = 0; + pmic_set_chg_current(0x8); + queue_delayed_work(chg_wq, &chg_work, 100); + chg_wa_timer = 1; + return; + } + + ret = pmic_read_reg(REG_INT_SENSE0, &value, BITFMASK(BIT_CHG_DETS)); + + if (ret == 0) { + dets = BITFEXT(value, BIT_CHG_DETS); + pr_debug("dets=%d\n", dets); + + if (dets == 1) { + pmic_get_chg_value(&value); + pr_debug("average value=%d\n", value); + if ((value <= 3) | ((value & 0x200) != 0)) { + pr_debug("%s: Disable the charger\n", __func__); + pmic_set_chg_current(0); + disable_chg_timer = 1; + } + + queue_delayed_work(chg_wq, &chg_work, 100); + chg_wa_timer = 1; + } + } +} + +static int mc13892_charger_update_status(struct mc13892_dev_info *di) +{ + int ret; + unsigned int value; + int online; + + ret = pmic_read_reg(REG_INT_SENSE0, &value, BITFMASK(BIT_CHG_DETS)); + + if (ret == 0) { + online = BITFEXT(value, BIT_CHG_DETS); + if (online != di->charger_online) { + di->charger_online = online; + dev_info(di->charger.dev, "charger status: %s\n", + online ? "online" : "offline"); + power_supply_changed(&di->charger); + + cancel_delayed_work(&di->monitor_work); + queue_delayed_work(di->monitor_wqueue, + &di->monitor_work, HZ / 10); + if (online) { + pmic_start_coulomb_counter(); + pmic_restart_charging(); + queue_delayed_work(chg_wq, &chg_work, 100); + chg_wa_timer = 1; + } else { + cancel_delayed_work(&chg_work); + chg_wa_timer = 0; + pmic_stop_coulomb_counter(); + } + } + } + + return ret; +} + +static int mc13892_charger_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct mc13892_dev_info *di = + container_of((psy), struct mc13892_dev_info, charger); + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + val->intval = di->charger_online; + return 0; + default: + break; + } + return -EINVAL; +} + +static int mc13892_battery_read_status(struct mc13892_dev_info *di) +{ + int retval; + int coulomb; + retval = pmic_get_batt_voltage(&(di->voltage_raw)); + if (retval == 0) + di->voltage_uV = di->voltage_raw * BAT_VOLTAGE_UNIT_UV; + + retval = pmic_get_batt_current(&(di->current_raw)); + if (retval == 0) { + if (di->current_raw & 0x200) + di->current_uA = + (0x1FF - (di->current_raw & 0x1FF)) * + BAT_CURRENT_UNIT_UA * (-1); + else + di->current_uA = + (di->current_raw & 0x1FF) * BAT_CURRENT_UNIT_UA; + } + retval = pmic_get_charger_coulomb(&coulomb); + if (retval == 0) + di->accum_current_uAh = COULOMB_TO_UAH(coulomb); + + return retval; +} + +static void mc13892_battery_update_status(struct mc13892_dev_info *di) +{ + unsigned int value; + int retval; + int old_battery_status = di->battery_status; + + if (di->battery_status == POWER_SUPPLY_STATUS_UNKNOWN) + di->full_counter = 0; + + if (di->charger_online) { + retval = pmic_read_reg(REG_INT_SENSE0, + &value, BITFMASK(BIT_CHG_CURRS)); + + if (retval == 0) { + value = BITFEXT(value, BIT_CHG_CURRS); + if (value) + di->battery_status = + POWER_SUPPLY_STATUS_CHARGING; + else + di->battery_status = + POWER_SUPPLY_STATUS_NOT_CHARGING; + } + + if (di->battery_status == POWER_SUPPLY_STATUS_NOT_CHARGING) + di->full_counter++; + else + di->full_counter = 0; + } else { + di->battery_status = POWER_SUPPLY_STATUS_DISCHARGING; + di->full_counter = 0; + } + + dev_dbg(di->bat.dev, "bat status: %d\n", + di->battery_status); + + if (old_battery_status != POWER_SUPPLY_STATUS_UNKNOWN && + di->battery_status != old_battery_status) + power_supply_changed(&di->bat); +} + +static void mc13892_battery_work(struct work_struct *work) +{ + struct mc13892_dev_info *di = container_of(work, + struct mc13892_dev_info, + monitor_work.work); + const int interval = HZ * 60; + + dev_dbg(di->dev, "%s\n", __func__); + + mc13892_battery_update_status(di); + queue_delayed_work(di->monitor_wqueue, &di->monitor_work, interval); +} + +static void charger_online_event_callback(void *para) +{ + struct mc13892_dev_info *di = (struct mc13892_dev_info *) para; + pr_info("\n\n DETECTED charger plug/unplug event\n"); + mc13892_charger_update_status(di); +} + + +static int mc13892_battery_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct mc13892_dev_info *di = to_mc13892_dev_info(psy); + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (di->battery_status == POWER_SUPPLY_STATUS_UNKNOWN) { + mc13892_charger_update_status(di); + mc13892_battery_update_status(di); + } + val->intval = di->battery_status; + return 0; + default: + break; + } + + mc13892_battery_read_status(di); + + switch (psp) { + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + val->intval = di->voltage_uV; + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + val->intval = di->current_uA; + break; + case POWER_SUPPLY_PROP_CHARGE_NOW: + val->intval = di->accum_current_uAh; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: + val->intval = 3800000; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: + val->intval = 3300000; + break; + default: + return -EINVAL; + } + + return 0; +} + +static ssize_t chg_wa_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (chg_wa_is_active & chg_wa_timer) + return sprintf(buf, "Charger LED workaround timer is on\n"); + else + return sprintf(buf, "Charger LED workaround timer is off\n"); +} + +static ssize_t chg_wa_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + if (strstr(buf, "1") != NULL) { + if (chg_wa_is_active) { + if (chg_wa_timer) + printk(KERN_INFO "Charger timer is already on\n"); + else { + queue_delayed_work(chg_wq, &chg_work, 100); + chg_wa_timer = 1; + printk(KERN_INFO "Turned on the timer\n"); + } + } + } else if (strstr(buf, "0") != NULL) { + if (chg_wa_is_active) { + if (chg_wa_timer) { + cancel_delayed_work(&chg_work); + chg_wa_timer = 0; + printk(KERN_INFO "Turned off charger timer\n"); + } else { + printk(KERN_INFO "The Charger workaround timer is off\n"); + } + } + } + + return size; +} + +static DEVICE_ATTR(enable, 0644, chg_wa_enable_show, chg_wa_enable_store); + +static int pmic_battery_remove(struct platform_device *pdev) +{ + pmic_event_callback_t bat_event_callback; + struct mc13892_dev_info *di = platform_get_drvdata(pdev); + + bat_event_callback.func = charger_online_event_callback; + bat_event_callback.param = (void *) di; + pmic_event_unsubscribe(EVENT_CHGDETI, bat_event_callback); + + cancel_rearming_delayed_workqueue(di->monitor_wqueue, + &di->monitor_work); + cancel_rearming_delayed_workqueue(chg_wq, + &chg_work); + destroy_workqueue(di->monitor_wqueue); + destroy_workqueue(chg_wq); + chg_wa_timer = 0; + chg_wa_is_active = 0; + disable_chg_timer = 0; + power_supply_unregister(&di->bat); + power_supply_unregister(&di->charger); + + kfree(di); + + return 0; +} + +static int pmic_battery_probe(struct platform_device *pdev) +{ + int retval = 0; + struct mc13892_dev_info *di; + pmic_event_callback_t bat_event_callback; + pmic_version_t pmic_version; + + /* Only apply battery driver for MC13892 V2.0 due to ENGR108085 */ + pmic_version = pmic_get_version(); + if (pmic_version.revision < 20) { + pr_debug("Battery driver is only applied for MC13892 V2.0\n"); + return -1; + } + if (machine_is_mx50_arm2()) { + pr_debug("mc13892 charger is not used for this platform\n"); + return -1; + } + + di = kzalloc(sizeof(*di), GFP_KERNEL); + if (!di) { + retval = -ENOMEM; + goto di_alloc_failed; + } + + platform_set_drvdata(pdev, di); + + di->charger.name = "mc13892_charger"; + di->charger.type = POWER_SUPPLY_TYPE_MAINS; + di->charger.properties = mc13892_charger_props; + di->charger.num_properties = ARRAY_SIZE(mc13892_charger_props); + di->charger.get_property = mc13892_charger_get_property; + retval = power_supply_register(&pdev->dev, &di->charger); + if (retval) { + dev_err(di->dev, "failed to register charger\n"); + goto charger_failed; + } + + INIT_DELAYED_WORK(&chg_work, chg_thread); + chg_wq = create_singlethread_workqueue("mxc_chg"); + if (!chg_wq) { + retval = -ESRCH; + goto workqueue_failed; + } + + INIT_DELAYED_WORK(&di->monitor_work, mc13892_battery_work); + di->monitor_wqueue = create_singlethread_workqueue(dev_name(&pdev->dev)); + if (!di->monitor_wqueue) { + retval = -ESRCH; + goto workqueue_failed; + } + queue_delayed_work(di->monitor_wqueue, &di->monitor_work, HZ * 10); + + di->dev = &pdev->dev; + di->bat.name = "mc13892_bat"; + di->bat.type = POWER_SUPPLY_TYPE_BATTERY; + di->bat.properties = mc13892_battery_props; + di->bat.num_properties = ARRAY_SIZE(mc13892_battery_props); + di->bat.get_property = mc13892_battery_get_property; + di->bat.use_for_apm = 1; + + di->battery_status = POWER_SUPPLY_STATUS_UNKNOWN; + + retval = power_supply_register(&pdev->dev, &di->bat); + if (retval) { + dev_err(di->dev, "failed to register battery\n"); + goto batt_failed; + } + + bat_event_callback.func = charger_online_event_callback; + bat_event_callback.param = (void *) di; + pmic_event_subscribe(EVENT_CHGDETI, bat_event_callback); + retval = sysfs_create_file(&pdev->dev.kobj, &dev_attr_enable.attr); + + if (retval) { + printk(KERN_ERR + "Battery: Unable to register sysdev entry for Battery"); + goto workqueue_failed; + } + chg_wa_is_active = 1; + chg_wa_timer = 0; + disable_chg_timer = 0; + + pmic_stop_coulomb_counter(); + pmic_calibrate_coulomb_counter(); + goto success; + +workqueue_failed: + power_supply_unregister(&di->charger); +charger_failed: + power_supply_unregister(&di->bat); +batt_failed: + kfree(di); +di_alloc_failed: +success: + dev_dbg(di->dev, "%s battery probed!\n", __func__); + return retval; + + + return 0; +} + +static struct platform_driver pmic_battery_driver_ldm = { + .driver = { + .name = "pmic_battery", + .bus = &platform_bus_type, + }, + .probe = pmic_battery_probe, + .remove = pmic_battery_remove, +}; + +static int __init pmic_battery_init(void) +{ + pr_debug("PMIC Battery driver loading...\n"); + return platform_driver_register(&pmic_battery_driver_ldm); +} + +static void __exit pmic_battery_exit(void) +{ + platform_driver_unregister(&pmic_battery_driver_ldm); + pr_debug("PMIC Battery driver successfully unloaded\n"); +} + +module_init(pmic_battery_init); +module_exit(pmic_battery_exit); + +MODULE_DESCRIPTION("pmic_battery driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/pmic/mc13892/pmic_light.c b/drivers/mxc/pmic/mc13892/pmic_light.c new file mode 100644 index 000000000000..caaa98d7d7d9 --- /dev/null +++ b/drivers/mxc/pmic/mc13892/pmic_light.c @@ -0,0 +1,685 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mc13892/pmic_light.c + * @brief This is the main file of PMIC(mc13783) Light and Backlight driver. + * + * @ingroup PMIC_LIGHT + */ + +/* + * Includes + */ +#define DEBUG +#include +#include +#include +#include +#include + +#define BIT_CL_MAIN_LSH 9 +#define BIT_CL_AUX_LSH 21 +#define BIT_CL_KEY_LSH 9 +#define BIT_CL_RED_LSH 9 +#define BIT_CL_GREEN_LSH 21 +#define BIT_CL_BLUE_LSH 9 + +#define BIT_CL_MAIN_WID 3 +#define BIT_CL_AUX_WID 3 +#define BIT_CL_KEY_WID 3 +#define BIT_CL_RED_WID 3 +#define BIT_CL_GREEN_WID 3 +#define BIT_CL_BLUE_WID 3 + +#define BIT_DC_MAIN_LSH 3 +#define BIT_DC_AUX_LSH 15 +#define BIT_DC_KEY_LSH 3 +#define BIT_DC_RED_LSH 3 +#define BIT_DC_GREEN_LSH 15 +#define BIT_DC_BLUE_LSH 3 + +#define BIT_DC_MAIN_WID 6 +#define BIT_DC_AUX_WID 6 +#define BIT_DC_KEY_WID 6 +#define BIT_DC_RED_WID 6 +#define BIT_DC_GREEN_WID 6 +#define BIT_DC_BLUE_WID 6 + +#define BIT_RP_MAIN_LSH 2 +#define BIT_RP_AUX_LSH 14 +#define BIT_RP_KEY_LSH 2 +#define BIT_RP_RED_LSH 2 +#define BIT_RP_GREEN_LSH 14 +#define BIT_RP_BLUE_LSH 2 + +#define BIT_RP_MAIN_WID 1 +#define BIT_RP_AUX_WID 1 +#define BIT_RP_KEY_WID 1 +#define BIT_RP_RED_WID 1 +#define BIT_RP_GREEN_WID 1 +#define BIT_RP_BLUE_WID 1 + +#define BIT_HC_MAIN_LSH 1 +#define BIT_HC_AUX_LSH 13 +#define BIT_HC_KEY_LSH 1 + +#define BIT_HC_MAIN_WID 1 +#define BIT_HC_AUX_WID 1 +#define BIT_HC_KEY_WID 1 + +#define BIT_BP_RED_LSH 0 +#define BIT_BP_GREEN_LSH 12 +#define BIT_BP_BLUE_LSH 0 + +#define BIT_BP_RED_WID 2 +#define BIT_BP_GREEN_WID 2 +#define BIT_BP_BLUE_WID 2 + +int pmic_light_init_reg(void) +{ + CHECK_ERROR(pmic_write_reg(REG_LED_CTL0, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_LED_CTL1, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_LED_CTL2, 0, PMIC_ALL_BITS)); + CHECK_ERROR(pmic_write_reg(REG_LED_CTL3, 0, PMIC_ALL_BITS)); + + return 0; +} + +static int pmic_light_suspend(struct platform_device *dev, pm_message_t state) +{ + return 0; +}; + +static int pmic_light_resume(struct platform_device *pdev) +{ + return 0; +}; + +PMIC_STATUS mc13892_bklit_set_hi_current(enum lit_channel channel, int mode) +{ + unsigned int mask; + unsigned int value; + int reg; + + switch (channel) { + case LIT_MAIN: + value = BITFVAL(BIT_HC_MAIN, mode); + mask = BITFMASK(BIT_HC_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + value = BITFVAL(BIT_HC_AUX, mode); + mask = BITFMASK(BIT_HC_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + value = BITFVAL(BIT_HC_KEY, mode); + mask = BITFMASK(BIT_HC_KEY); + reg = REG_LED_CTL1; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_hi_current(enum lit_channel channel, int *mode) +{ + unsigned int mask; + int reg; + + switch (channel) { + case LIT_MAIN: + mask = BITFMASK(BIT_HC_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + mask = BITFMASK(BIT_HC_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + mask = BITFMASK(BIT_HC_KEY); + reg = REG_LED_CTL1; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, mode, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_set_current(enum lit_channel channel, + unsigned char level) +{ + unsigned int mask; + unsigned int value; + int reg; + + if (level > LIT_CURR_HI_42) + return PMIC_PARAMETER_ERROR; + else if (level >= LIT_CURR_HI_0) { + CHECK_ERROR(mc13892_bklit_set_hi_current(channel, 1)); + level -= LIT_CURR_HI_0; + } + + switch (channel) { + case LIT_MAIN: + value = BITFVAL(BIT_CL_MAIN, level); + mask = BITFMASK(BIT_CL_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + value = BITFVAL(BIT_CL_AUX, level); + mask = BITFMASK(BIT_CL_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + value = BITFVAL(BIT_CL_KEY, level); + mask = BITFMASK(BIT_CL_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + value = BITFVAL(BIT_CL_RED, level); + mask = BITFMASK(BIT_CL_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + value = BITFVAL(BIT_CL_GREEN, level); + mask = BITFMASK(BIT_CL_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + value = BITFVAL(BIT_CL_BLUE, level); + mask = BITFMASK(BIT_CL_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_current(enum lit_channel channel, + unsigned char *level) +{ + unsigned int reg_value = 0; + unsigned int mask = 0; + int reg, mode; + + CHECK_ERROR(mc13892_bklit_get_hi_current(channel, &mode)); + + switch (channel) { + case LIT_MAIN: + mask = BITFMASK(BIT_CL_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + mask = BITFMASK(BIT_CL_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + mask = BITFMASK(BIT_CL_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + mask = BITFMASK(BIT_CL_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + mask = BITFMASK(BIT_CL_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + mask = BITFMASK(BIT_CL_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_value, mask)); + + switch (channel) { + case LIT_MAIN: + *level = BITFEXT(reg_value, BIT_CL_MAIN); + break; + case LIT_AUX: + *level = BITFEXT(reg_value, BIT_CL_AUX); + break; + case LIT_KEY: + *level = BITFEXT(reg_value, BIT_CL_KEY); + break; + case LIT_RED: + *level = BITFEXT(reg_value, BIT_CL_RED); + break; + case LIT_GREEN: + *level = BITFEXT(reg_value, BIT_CL_GREEN); + break; + case LIT_BLUE: + *level = BITFEXT(reg_value, BIT_CL_BLUE); + break; + default: + return PMIC_PARAMETER_ERROR; + } + + if (mode == 1) + *level += LIT_CURR_HI_0; + + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_set_dutycycle(enum lit_channel channel, + unsigned char dc) +{ + unsigned int mask; + unsigned int value; + int reg; + + switch (channel) { + case LIT_MAIN: + value = BITFVAL(BIT_DC_MAIN, dc); + mask = BITFMASK(BIT_DC_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + value = BITFVAL(BIT_DC_AUX, dc); + mask = BITFMASK(BIT_DC_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + value = BITFVAL(BIT_DC_KEY, dc); + mask = BITFMASK(BIT_DC_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + value = BITFVAL(BIT_DC_RED, dc); + mask = BITFMASK(BIT_DC_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + value = BITFVAL(BIT_DC_GREEN, dc); + mask = BITFMASK(BIT_DC_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + value = BITFVAL(BIT_DC_BLUE, dc); + mask = BITFMASK(BIT_DC_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_dutycycle(enum lit_channel channel, + unsigned char *dc) +{ + unsigned int mask; + int reg; + unsigned int reg_value = 0; + + switch (channel) { + case LIT_MAIN: + mask = BITFMASK(BIT_DC_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + mask = BITFMASK(BIT_DC_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + mask = BITFMASK(BIT_DC_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + mask = BITFMASK(BIT_DC_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + mask = BITFMASK(BIT_DC_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + mask = BITFMASK(BIT_DC_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, ®_value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_set_ramp(enum lit_channel channel, int flag) +{ + unsigned int mask; + unsigned int value; + int reg; + + switch (channel) { + case LIT_MAIN: + value = BITFVAL(BIT_RP_MAIN, flag); + mask = BITFMASK(BIT_RP_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + value = BITFVAL(BIT_RP_AUX, flag); + mask = BITFMASK(BIT_RP_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + value = BITFVAL(BIT_RP_KEY, flag); + mask = BITFMASK(BIT_RP_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + value = BITFVAL(BIT_RP_RED, flag); + mask = BITFMASK(BIT_RP_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + value = BITFVAL(BIT_RP_GREEN, flag); + mask = BITFMASK(BIT_RP_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + value = BITFVAL(BIT_RP_BLUE, flag); + mask = BITFMASK(BIT_RP_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_ramp(enum lit_channel channel, int *flag) +{ + unsigned int mask; + int reg; + + switch (channel) { + case LIT_MAIN: + mask = BITFMASK(BIT_RP_MAIN); + reg = REG_LED_CTL0; + break; + case LIT_AUX: + mask = BITFMASK(BIT_RP_AUX); + reg = REG_LED_CTL0; + break; + case LIT_KEY: + mask = BITFMASK(BIT_RP_KEY); + reg = REG_LED_CTL1; + break; + case LIT_RED: + mask = BITFMASK(BIT_RP_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + mask = BITFMASK(BIT_RP_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + mask = BITFMASK(BIT_RP_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, flag, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_set_blink_p(enum lit_channel channel, int period) +{ + unsigned int mask; + unsigned int value; + int reg; + + switch (channel) { + case LIT_RED: + value = BITFVAL(BIT_BP_RED, period); + mask = BITFMASK(BIT_BP_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + value = BITFVAL(BIT_BP_GREEN, period); + mask = BITFMASK(BIT_BP_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + value = BITFVAL(BIT_BP_BLUE, period); + mask = BITFMASK(BIT_BP_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + CHECK_ERROR(pmic_write_reg(reg, value, mask)); + return PMIC_SUCCESS; +} + +PMIC_STATUS mc13892_bklit_get_blink_p(enum lit_channel channel, int *period) +{ + unsigned int mask; + int reg; + + switch (channel) { + case LIT_RED: + mask = BITFMASK(BIT_BP_RED); + reg = REG_LED_CTL2; + break; + case LIT_GREEN: + mask = BITFMASK(BIT_BP_GREEN); + reg = REG_LED_CTL2; + break; + case LIT_BLUE: + mask = BITFMASK(BIT_BP_BLUE); + reg = REG_LED_CTL3; + break; + default: + return PMIC_PARAMETER_ERROR; + } + + CHECK_ERROR(pmic_read_reg(reg, period, mask)); + return PMIC_SUCCESS; +} + +EXPORT_SYMBOL(mc13892_bklit_set_current); +EXPORT_SYMBOL(mc13892_bklit_get_current); +EXPORT_SYMBOL(mc13892_bklit_set_dutycycle); +EXPORT_SYMBOL(mc13892_bklit_get_dutycycle); +EXPORT_SYMBOL(mc13892_bklit_set_ramp); +EXPORT_SYMBOL(mc13892_bklit_get_ramp); +EXPORT_SYMBOL(mc13892_bklit_set_blink_p); +EXPORT_SYMBOL(mc13892_bklit_get_blink_p); + +static int pmic_light_remove(struct platform_device *pdev) +{ + return 0; +} + +#ifdef DEBUG +static ssize_t lit_info(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return 0; +} + +enum { + SET_CURR = 0, + SET_DC, + SET_RAMP, + SET_BP, + SET_CH, + LIT_CMD_MAX +}; + +static const char *const lit_cmd[LIT_CMD_MAX] = { + [SET_CURR] = "cur", + [SET_DC] = "dc", + [SET_RAMP] = "ra", + [SET_BP] = "bp", + [SET_CH] = "ch" +}; + +static int cmd(unsigned int index, int value) +{ + static int ch = LIT_MAIN; + int ret = 0; + + switch (index) { + case SET_CH: + ch = value; + break; + case SET_CURR: + pr_debug("set %d cur %d\n", ch, value); + ret = mc13892_bklit_set_current(ch, value); + break; + case SET_DC: + pr_debug("set %d dc %d\n", ch, value); + ret = mc13892_bklit_set_dutycycle(ch, value); + break; + case SET_RAMP: + pr_debug("set %d ramp %d\n", ch, value); + ret = mc13892_bklit_set_ramp(ch, value); + break; + case SET_BP: + pr_debug("set %d bp %d\n", ch, value); + ret = mc13892_bklit_set_blink_p(ch, value); + break; + default: + pr_debug("error command\n"); + break; + } + + if (ret == PMIC_SUCCESS) + pr_debug("command exec successfully!\n"); + + return 0; +} + +static ssize_t lit_ctl(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int state = 0; + const char *const *s; + char *p, *q; + int error; + int len, value = 0; + + pr_debug("lit_ctl\n"); + + q = NULL; + q = memchr(buf, ' ', count); + + if (q != NULL) { + len = q - buf; + q += 1; + value = simple_strtoul(q, NULL, 10); + } else { + p = memchr(buf, '\n', count); + len = p ? p - buf : count; + } + + for (s = &lit_cmd[state]; state < LIT_CMD_MAX; s++, state++) { + if (*s && !strncmp(buf, *s, len)) + break; + } + if (state < LIT_CMD_MAX && *s) + error = cmd(state, value); + else + error = -EINVAL; + + return count; +} + +#else +static ssize_t lit_info(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return 0; +} + +static ssize_t lit_ctl(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + return count; +} + +#endif + +static DEVICE_ATTR(lit, 0644, lit_info, lit_ctl); + +static int pmic_light_probe(struct platform_device *pdev) +{ + int ret = 0; + + pr_debug("PMIC ADC start probe\n"); + ret = device_create_file(&(pdev->dev), &dev_attr_lit); + if (ret) { + pr_debug("Can't create device file!\n"); + return -ENODEV; + } + + pmic_light_init_reg(); + + pr_debug("PMIC Light successfully loaded\n"); + return 0; +} + +static struct platform_driver pmic_light_driver_ldm = { + .driver = { + .name = "pmic_light", + }, + .suspend = pmic_light_suspend, + .resume = pmic_light_resume, + .probe = pmic_light_probe, + .remove = pmic_light_remove, +}; + +/* + * Initialization and Exit + */ + +static int __init pmic_light_init(void) +{ + pr_debug("PMIC Light driver loading...\n"); + return platform_driver_register(&pmic_light_driver_ldm); +} +static void __exit pmic_light_exit(void) +{ + platform_driver_unregister(&pmic_light_driver_ldm); + pr_debug("PMIC Light driver successfully unloaded\n"); +} + +/* + * Module entry points + */ + +subsys_initcall(pmic_light_init); +module_exit(pmic_light_exit); + +MODULE_DESCRIPTION("PMIC_LIGHT"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/security/Kconfig b/drivers/mxc/security/Kconfig new file mode 100644 index 000000000000..875848b2c69c --- /dev/null +++ b/drivers/mxc/security/Kconfig @@ -0,0 +1,64 @@ +menu "MXC Security Drivers" + +config MXC_SECURITY_SCC + tristate "MXC SCC Driver" + default n + ---help--- + This module contains the core API's for accessing the SCC module. + If you are unsure about this, say N here. + +config MXC_SECURITY_SCC2 + tristate "MXC SCC2 Driver" + depends on ARCH_MX37 || ARCH_MX5 + default n + ---help--- + This module contains the core API's for accessing the SCC2 module. + If you are unsure about this, say N here. + +config SCC_DEBUG + bool "MXC SCC Module debugging" + depends on MXC_SECURITY_SCC || MXC_SECURITY_SCC2 + ---help--- + This is an option for use by developers; most people should + say N here. This enables SCC module debugging. + +config MXC_SECURITY_RNG + tristate "MXC RNG Driver" + depends on ARCH_MXC + depends on !ARCH_MXC91321 + depends on !ARCH_MX27 + default n + select MXC_SECURITY_CORE + ---help--- + This module contains the core API's for accessing the RNG module. + If you are unsure about this, say N here. + +config MXC_RNG_TEST_DRIVER + bool "MXC RNG debug register" + depends on MXC_SECURITY_RNG + default n + ---help--- + This option enables the RNG kcore driver to provide peek-poke facility + into the RNG device registers. Enable this, only for development and + testing purposes. +config MXC_RNG_DEBUG + bool "MXC RNG Module Dubugging" + depends on MXC_SECURITY_RNG + default n + ---help--- + This is an option for use by developers; most people should + say N here. This enables RNG module debugging. + +config MXC_DRYICE + tristate "MXC DryIce Driver" + depends on ARCH_MX25 + default n + ---help--- + This module contains the core API's for accessing the DryIce module. + If you are unsure about this, say N here. + +if (ARCH_MX37 || ARCH_MX5 || ARCH_MX27) +source "drivers/mxc/security/sahara2/Kconfig" +endif + +endmenu diff --git a/drivers/mxc/security/Makefile b/drivers/mxc/security/Makefile new file mode 100644 index 000000000000..f643a09a423d --- /dev/null +++ b/drivers/mxc/security/Makefile @@ -0,0 +1,11 @@ +# Makefile for the Linux MXC Security API +ifeq ($( SCC_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif +EXTRA_CFLAGS += -DMXC -DLINUX_KERNEL + +obj-$(CONFIG_MXC_SECURITY_SCC2) += scc2_driver.o +obj-$(CONFIG_MXC_SECURITY_SCC) += mxc_scc.o +obj-$(CONFIG_MXC_SECURITY_RNG) += rng/ +obj-$(CONFIG_MXC_SAHARA) += sahara2/ +obj-$(CONFIG_MXC_DRYICE) += dryice.o diff --git a/drivers/mxc/security/dryice-regs.h b/drivers/mxc/security/dryice-regs.h new file mode 100644 index 000000000000..2da10585965a --- /dev/null +++ b/drivers/mxc/security/dryice-regs.h @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#ifndef __DRYICE_REGS_H__ +#define __DRYICE_REGS_H__ + +/*********************************************************************** + * DryIce Register Definitions + ***********************************************************************/ + +/* DryIce Time Counter MSB Reg */ +#define DTCMR 0x00 + +/* DryIce Time Counter LSB Reg */ +#define DTCLR 0x04 + +/* DryIce Clock Alarm MSB Reg */ +#define DCAMR 0x08 + +/* DryIce Clock Alarm LSB Reg */ +#define DCALR 0x0c + +/* DryIce Control Reg */ +#define DCR 0x10 +#define DCR_TDCHL (1 << 30) /* Tamper Detect Config Hard Lock */ +#define DCR_TDCSL (1 << 29) /* Tamper Detect COnfig Soft Lock */ +#define DCR_KSHL (1 << 28) /* Key Select Hard Lock */ +#define DCR_KSSL (1 << 27) /* Key Select Soft Lock */ +#define DCR_RKHL (1 << 26) /* Random Key Hard Lock */ +#define DCR_RKSL (1 << 25) /* Random Key Soft Lock */ +#define DCR_PKRHL (1 << 24) /* Programmed Key Read Hard Lock */ +#define DCR_PKRSL (1 << 23) /* Programmed Key Read Soft Lock */ +#define DCR_PKWHL (1 << 22) /* Programmed Key Write Hard Lock */ +#define DCR_PKWSL (1 << 21) /* Programmed Key Write Soft Lock */ +#define DCR_MCHL (1 << 20) /* Monotonic Counter Hard Lock */ +#define DCR_MCSL (1 << 19) /* Monotonic Counter Soft Lock */ +#define DCR_TCHL (1 << 18) /* Time Counter Hard Lock */ +#define DCR_TCSL (1 << 17) /* Time Counter Soft Lock */ +#define DCR_FSHL (1 << 16) /* Failure State Hard Lock */ +#define DCR_NSA (1 << 15) /* Non-Secure Access */ +#define DCR_OSCB (1 << 14) /* Oscillator Bypass */ +#define DCR_APE (1 << 4) /* Alarm Pin Enable */ +#define DCR_TCE (1 << 3) /* Time Counter Enable */ +#define DCR_MCE (1 << 2) /* Monotonic Counter Enable */ +#define DCR_SWR (1 << 0) /* Software Reset (w/o) */ + +/* DryIce Status Reg */ +#define DSR 0x14 +#define DSR_WTD (1 << 23) /* Wire-mesh Tampering Detected */ +#define DSR_ETBD (1 << 22) /* External Tampering B Detected */ +#define DSR_ETAD (1 << 21) /* External Tampering A Detected */ +#define DSR_EBD (1 << 20) /* External Boot Detected */ +#define DSR_SAD (1 << 19) /* Security Alarm Detected */ +#define DSR_TTD (1 << 18) /* Temperature Tampering Detected */ +#define DSR_CTD (1 << 17) /* Clock Tampering Detected */ +#define DSR_VTD (1 << 16) /* Voltage Tampering Detected */ +#define DSR_KBF (1 << 11) /* Key Busy Flag */ +#define DSR_WBF (1 << 10) /* Write Busy Flag */ +#define DSR_WNF (1 << 9) /* Write Next Flag */ +#define DSR_WCF (1 << 8) /* Write Complete Flag */ +#define DSR_WEF (1 << 7) /* Write Error Flag */ +#define DSR_RKE (1 << 6) /* Random Key Error */ +#define DSR_RKV (1 << 5) /* Random Key Valid */ +#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ +#define DSR_MCO (1 << 3) /* Monotonic Counter Overflow */ +#define DSR_TCO (1 << 2) /* Time Counter Overflow */ +#define DSR_NVF (1 << 1) /* Non-Valid Flag */ +#define DSR_SVF (1 << 0) /* Security Violation Flag */ + +#define DSR_TAMPER_BITS (DSR_WTD | DSR_ETBD | DSR_ETAD | DSR_EBD | DSR_SAD | \ + DSR_TTD | DSR_CTD | DSR_VTD | DSR_MCO | DSR_TCO) + +/* ensure that external tamper defs match register bits */ +#if DSR_WTD != DI_TAMPER_EVENT_WTD +#error "Mismatch between DSR_WTD and DI_TAMPER_EVENT_WTD" +#endif +#if DSR_ETBD != DI_TAMPER_EVENT_ETBD +#error "Mismatch between DSR_ETBD and DI_TAMPER_EVENT_ETBD" +#endif +#if DSR_ETAD != DI_TAMPER_EVENT_ETAD +#error "Mismatch between DSR_ETAD and DI_TAMPER_EVENT_ETAD" +#endif +#if DSR_EBD != DI_TAMPER_EVENT_EBD +#error "Mismatch between DSR_EBD and DI_TAMPER_EVENT_EBD" +#endif +#if DSR_SAD != DI_TAMPER_EVENT_SAD +#error "Mismatch between DSR_SAD and DI_TAMPER_EVENT_SAD" +#endif +#if DSR_TTD != DI_TAMPER_EVENT_TTD +#error "Mismatch between DSR_TTD and DI_TAMPER_EVENT_TTD" +#endif +#if DSR_CTD != DI_TAMPER_EVENT_CTD +#error "Mismatch between DSR_CTD and DI_TAMPER_EVENT_CTD" +#endif +#if DSR_VTD != DI_TAMPER_EVENT_VTD +#error "Mismatch between DSR_VTD and DI_TAMPER_EVENT_VTD" +#endif +#if DSR_MCO != DI_TAMPER_EVENT_MCO +#error "Mismatch between DSR_MCO and DI_TAMPER_EVENT_MCO" +#endif +#if DSR_TCO != DI_TAMPER_EVENT_TCO +#error "Mismatch between DSR_TCO and DI_TAMPER_EVENT_TCO" +#endif + +/* DryIce Interrupt Enable Reg */ +#define DIER 0x18 +#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ +#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ +#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ +#define DIER_RKIE (1 << 5) /* Random Key Interrupt Enable */ +#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ +#define DIER_MOIE (1 << 3) /* Monotonic Overflow Interrupt En */ +#define DIER_TOIE (1 << 2) /* Time Overflow Interrupt Enable */ +#define DIER_SVIE (1 << 0) /* Security Violation Interrupt En */ + +/* DryIce Monotonic Counter Reg */ +#define DMCR 0x1c + +/* DryIce Key Select Reg */ +#define DKSR 0x20 +#define DKSR_IIM_KEY 0x0 +#define DKSR_PROG_KEY 0x4 +#define DKSR_RAND_KEY 0x5 +#define DKSR_PROG_XOR_IIM_KEY 0x6 +#define DKSR_RAND_XOR_IIM_KEY 0x7 + +/* DryIce Key Control Reg */ +#define DKCR 0x24 +#define DKCR_LRK (1 << 0) /* Load Random Key */ + +/* DryIce Tamper Configuration Reg */ +#define DTCR 0x28 +#define DTCR_ETGFB_SHIFT 27 /* Ext Tamper Glitch Filter B */ +#define DTCR_ETGFB_MASK 0xf8000000 +#define DTCR_ETGFA_SHIFT 22 /* Ext Tamper Glitch Filter A */ +#define DTCR_ETGFA_MASK 0x07c00000 +#define DTCR_WTGF_SHIFT 17 /* Wire-mesh Tamper Glitch Filter */ +#define DTCR_WTGF_MASK 0x003e0000 +#define DTCR_WGFE (1 << 16) /* Wire-mesh Glitch Filter Enable */ +#define DTCR_SAOE (1 << 15) /* Security Alarm Output Enable */ +#define DTCR_MOE (1 << 9) /* Monotonic Overflow Enable */ +#define DTCR_TOE (1 << 8) /* Time Overflow Enable */ +#define DTCR_WTE (1 << 7) /* Wire-mesh Tampering Enable */ +#define DTCR_ETBE (1 << 6) /* External Tampering B Enable */ +#define DTCR_ETAE (1 << 5) /* External Tampering A Enable */ +#define DTCR_EBE (1 << 4) /* External Boot Enable */ +#define DTCR_SAIE (1 << 3) /* Security Alarm Input Enable */ +#define DTCR_TTE (1 << 2) /* Temperature Tamper Enable */ +#define DTCR_CTE (1 << 1) /* Clock Tamper Enable */ +#define DTCR_VTE (1 << 0) /* Voltage Tamper Enable */ + +/* DryIce Analog Configuration Reg */ +#define DACR 0x2c +#define DACR_VRC_SHIFT 6 /* Voltage Reference Configuration */ +#define DACR_VRC_MASK 0x000001c0 +#define DACR_HTDC_SHIFT 3 /* High Temperature Detect Configuration */ +#define DACR_HTDC_MASK 0x00000038 +#define DACR_LTDC_SHIFT 0 /* Low Temperature Detect Configuration */ +#define DACR_LTDC_MASK 0x00000007 + +/* DryIce General Purpose Reg */ +#define DGPR 0x3c + +/* DryIce Programmed Key0-7 Regs */ +#define DPKR0 0x40 +#define DPKR1 0x44 +#define DPKR2 0x48 +#define DPKR3 0x4c +#define DPKR4 0x50 +#define DPKR5 0x54 +#define DPKR6 0x58 +#define DPKR7 0x5c + +/* DryIce Random Key0-7 Regs */ +#define DRKR0 0x60 +#define DRKR1 0x64 +#define DRKR2 0x68 +#define DRKR3 0x6c +#define DRKR4 0x70 +#define DRKR5 0x74 +#define DRKR6 0x78 +#define DRKR7 0x7c + +#define DI_ADDRESS_RANGE (DRKR7 + 4) + +/* + * this doesn't really belong here but the + * portability layer doesn't include it + */ +#ifdef LINUX_KERNEL +#define EXTERN_SYMBOL(symbol) EXPORT_SYMBOL(symbol) +#else +#define EXTERN_SYMBOL(symbol) do {} while (0) +#endif + +#endif /* __DRYICE_REGS_H__ */ diff --git a/drivers/mxc/security/dryice.c b/drivers/mxc/security/dryice.c new file mode 100644 index 000000000000..7d0d45b71d83 --- /dev/null +++ b/drivers/mxc/security/dryice.c @@ -0,0 +1,1123 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#undef DI_DEBUG /* enable debug messages */ +#undef DI_DEBUG_REGIO /* show register read/write */ +#undef DI_TESTING /* include test code */ + +#ifdef DI_DEBUG +#define di_debug(fmt, arg...) os_printk(KERN_INFO fmt, ##arg) +#else +#define di_debug(fmt, arg...) do {} while (0) +#endif + +#define di_info(fmt, arg...) os_printk(KERN_INFO fmt, ##arg) +#define di_warn(fmt, arg...) os_printk(KERN_WARNING fmt, ##arg) + +#include "sahara2/include/portable_os.h" +#include "dryice.h" +#include "dryice-regs.h" + +/* mask of the lock-related function flags */ +#define DI_FUNC_LOCK_FLAGS (DI_FUNC_FLAG_READ_LOCK | \ + DI_FUNC_FLAG_WRITE_LOCK | \ + DI_FUNC_FLAG_HARD_LOCK) + +/* + * dryice hardware states + */ +enum di_states { + DI_STATE_VALID = 0, + DI_STATE_NON_VALID, + DI_STATE_FAILURE, +}; + +/* + * todo list actions + */ +enum todo_actions { + TODO_ACT_WRITE_VAL, + TODO_ACT_WRITE_PTR, + TODO_ACT_WRITE_PTR32, + TODO_ACT_ASSIGN, + TODO_ACT_WAIT_RKG, +}; + +/* + * todo list status + */ +enum todo_status { + TODO_ST_LOADING, + TODO_ST_READY, + TODO_ST_PEND_WCF, + TODO_ST_PEND_RKG, + TODO_ST_DONE, +}; + +OS_DEV_INIT_DCL(dryice_init) +OS_DEV_SHUTDOWN_DCL(dryice_exit) +OS_DEV_ISR_DCL(dryice_norm_irq) +OS_WAIT_OBJECT(done_queue); +OS_WAIT_OBJECT(exit_queue); + +struct dryice_data { + int busy; /* enforce exclusive access */ + os_lock_t busy_lock; + int exit_flag; /* don't start new operations */ + + uint32_t baseaddr; /* physical base address */ + void *ioaddr; /* virtual base address */ + + /* interrupt handling */ + struct irq_struct { + os_interrupt_id_t irq; + int set; + } irq_norm, irq_sec; + + struct clk *clk; /* clock control */ + + int key_programmed; /* key has been programmed */ + int key_selected; /* key has been selected */ + + /* callback function and cookie */ + void (*cb_func)(di_return_t rc, unsigned long cookie); + unsigned long cb_cookie; +} *di = NULL; + +#define TODO_LIST_LEN 12 +static struct { + struct td { + enum todo_actions action; + uint32_t src; + uint32_t dst; + int num; + } list[TODO_LIST_LEN]; + int cur; /* current todo pointer */ + int num; /* number of todo's on the list */ + int async; /* non-zero if list is async */ + int status; /* current status of the list */ + di_return_t rc; /* return code generated by the list */ +} todo; + +/* + * dryice register read/write functions + */ +#ifdef DI_DEBUG_REGIO +static uint32_t di_read(int reg) +{ + uint32_t val = os_read32(di->ioaddr + (reg)); + di_info("di_read(0x%02x) = 0x%08x\n", reg, val); + + return val; +} + +static void di_write(uint32_t val, int reg) +{ + di_info("dryice_write_reg(0x%08x, 0x%02x)\n", val, reg); + os_write32(di->ioaddr + (reg), val); +} +#else +#define di_read(reg) os_read32(di->ioaddr + (reg)) +#define di_write(val, reg) os_write32(di->ioaddr + (reg), val); +#endif + +/* + * set the dryice busy flag atomically, allowing + * for case where the driver is trying to exit. + */ +static int di_busy_set(void) +{ + os_lock_context_t context; + int rc = 0; + + os_lock_save_context(di->busy_lock, context); + if (di->exit_flag || di->busy) + rc = 1; + else + di->busy = 1; + os_unlock_restore_context(di->busy_lock, context); + + return rc; +} + +/* + * clear the dryice busy flag + */ +static inline void di_busy_clear(void) +{ + /* don't acquire the lock because the race is benign */ + di->busy = 0; + + if (di->exit_flag) + os_wake_sleepers(exit_queue); +} + +/* + * return the current state of dryice + * (valid, non-valid, or failure) + */ +static enum di_states di_state(void) +{ + enum di_states state = DI_STATE_VALID; + uint32_t dsr = di_read(DSR); + + if (dsr & DSR_NVF) + state = DI_STATE_NON_VALID; + else if (dsr & DSR_SVF) + state = DI_STATE_FAILURE; + + return state; +} + +#define DI_WRITE_LOOP_CNT 0x1000 +/* + * the write-error flag is something that shouldn't get set + * during normal operation. if it's set something is terribly + * wrong. the best we can do is try to clear the bit and hope + * that dryice will recover. this situation is similar to an + * unexpected bus fault in terms of severity. + */ +static void try_to_clear_wef(void) +{ + int cnt; + + while (1) { + di_write(DSR_WEF, DSR); + for (cnt = 0; cnt < DI_WRITE_LOOP_CNT; cnt++) { + if ((di_read(DSR) & DSR_WEF) == 0) + break; + } + di_warn("WARNING: DryIce cannot clear DSR_WEF " + "(Write Error Flag)!\n"); + } +} + +/* + * write a dryice register and loop, waiting for it + * to complete. use only during driver initialization. + * returns 0 on success or 1 on write failure. + */ +static int di_write_loop(uint32_t val, int reg) +{ + int rc = 0; + int cnt; + + di_debug("FUNC: %s\n", __func__); + di_write(val, reg); + + for (cnt = 0; cnt < DI_WRITE_LOOP_CNT; cnt++) { + uint32_t dsr = di_read(DSR); + if (dsr & DSR_WEF) { + try_to_clear_wef(); + rc = 1; + } + if (dsr & DSR_WCF) + break; + } + di_debug("wait_write_loop looped %d times\n", cnt); + if (cnt == DI_WRITE_LOOP_CNT) + rc = 1; + + if (rc) + di_warn("DryIce wait_write_done: WRITE ERROR!\n"); + return rc; +} + +/* + * initialize the todo list. must be called + * before adding items to the list. + */ +static void todo_init(int async_flag) +{ + di_debug("FUNC: %s\n", __func__); + todo.cur = 0; + todo.num = 0; + todo.async = async_flag; + todo.rc = 0; + todo.status = TODO_ST_LOADING; +} + +/* + * perform the current action on the todo list + */ +#define TC todo.list[todo.cur] +void todo_cur(void) +{ + di_debug("FUNC: %s[%d]\n", __func__, todo.cur); + switch (TC.action) { + case TODO_ACT_WRITE_VAL: + di_debug(" TODO_ACT_WRITE_VAL\n"); + /* enable the write-completion interrupt */ + todo.status = TODO_ST_PEND_WCF; + di_write(di_read(DIER) | DIER_WCIE, DIER); + + di_write(TC.src, TC.dst); + break; + + case TODO_ACT_WRITE_PTR32: + di_debug(" TODO_ACT_WRITE_PTR32\n"); + /* enable the write-completion interrupt */ + todo.status = TODO_ST_PEND_WCF; + di_write(di_read(DIER) | DIER_WCIE, DIER); + + di_write(*(uint32_t *)TC.src, TC.dst); + break; + + case TODO_ACT_WRITE_PTR: + { + uint8_t *p = (uint8_t *)TC.src; + uint32_t val = 0; + int num = TC.num; + + di_debug(" TODO_ACT_WRITE_PTR\n"); + while (num--) + val = (val << 8) | *p++; + + /* enable the write-completion interrupt */ + todo.status = TODO_ST_PEND_WCF; + di_write(di_read(DIER) | DIER_WCIE, DIER); + + di_write(val, TC.dst); + } + break; + + case TODO_ACT_ASSIGN: + di_debug(" TODO_ACT_ASSIGN\n"); + switch (TC.num) { + case 1: + *(uint8_t *)TC.dst = TC.src; + break; + case 2: + *(uint16_t *)TC.dst = TC.src; + break; + case 4: + *(uint32_t *)TC.dst = TC.src; + break; + default: + di_warn("Unexpected size in TODO_ACT_ASSIGN\n"); + break; + } + break; + + case TODO_ACT_WAIT_RKG: + di_debug(" TODO_ACT_WAIT_RKG\n"); + /* enable the random-key interrupt */ + todo.status = TODO_ST_PEND_RKG; + di_write(di_read(DIER) | DIER_RKIE, DIER); + break; + + default: + di_debug(" TODO_ACT_NOOP\n"); + break; + } +} + +/* + * called when done with the todo list. + * if async, it does the callback. + * if blocking, it wakes up the caller. + */ +static void todo_done(di_return_t rc) +{ + todo.rc = rc; + todo.status = TODO_ST_DONE; + if (todo.async) { + di_busy_clear(); + if (di->cb_func) + di->cb_func(rc, di->cb_cookie); + } else + os_wake_sleepers(done_queue); +} + +/* + * performs the actions sequentially from the todo list + * until it encounters an item that isn't ready. + */ +static void todo_run(void) +{ + di_debug("FUNC: %s\n", __func__); + while (todo.status == TODO_ST_READY) { + if (todo.cur == todo.num) { + todo_done(0); + break; + } + todo_cur(); + if (todo.status != TODO_ST_READY) + break; + todo.cur++; + } +} + +/* + * kick off the todo list by making it ready + */ +static void todo_start(void) +{ + di_debug("FUNC: %s\n", __func__); + todo.status = TODO_ST_READY; + todo_run(); +} + +/* + * blocking callers sleep here until the todo list is done + */ +static int todo_wait_done(void) +{ + di_debug("FUNC: %s\n", __func__); + os_sleep(done_queue, todo.status == TODO_ST_DONE, 0); + + return todo.rc; +} + +/* + * add a dryice register write to the todo list. + * the value to be written is supplied. + */ +#define todo_write_val(val, reg) \ + todo_add(TODO_ACT_WRITE_VAL, val, reg, 0) + +/* + * add a dryice register write to the todo list. + * "size" bytes pointed to by addr will be written. + */ +#define todo_write_ptr(addr, reg, size) \ + todo_add(TODO_ACT_WRITE_PTR, (uint32_t)addr, reg, size) + +/* + * add a dryice register write to the todo list. + * the word pointed to by addr will be written. + */ +#define todo_write_ptr32(addr, reg) \ + todo_add(TODO_ACT_WRITE_PTR32, (uint32_t)addr, reg, 0) + +/* + * add a dryice memory write to the todo list. + * object can only have a size of 1, 2, or 4 bytes. + */ +#define todo_assign(var, val) \ + todo_add(TODO_ACT_ASSIGN, val, (uint32_t)&(var), sizeof(var)) + +#define todo_wait_rkg() \ + todo_add(TODO_ACT_WAIT_RKG, 0, 0, 0) + +static void todo_add(int action, uint32_t src, uint32_t dst, int num) +{ + struct td *p = &todo.list[todo.num]; + + di_debug("FUNC: %s\n", __func__); + if (todo.num == TODO_LIST_LEN) { + di_warn("WARNING: DryIce todo-list overflow!\n"); + return; + } + p->action = action; + p->src = src; + p->dst = dst; + p->num = num; + todo.num++; +} + +#if defined(DI_DEBUG) || defined(DI_TESTING) +/* + * print out the contents of the dryice status register + * with all the bits decoded + */ +static void show_dsr(const char *heading) +{ + uint32_t dsr = di_read(DSR); + + di_info("%s\n", heading); + if (dsr & DSR_TAMPER_BITS) { + if (dsr & DSR_WTD) + di_info("Wire-mesh Tampering Detected\n"); + if (dsr & DSR_ETBD) + di_info("External Tampering B Detected\n"); + if (dsr & DSR_ETAD) + di_info("External Tampering A Detected\n"); + if (dsr & DSR_EBD) + di_info("External Boot Detected\n"); + if (dsr & DSR_SAD) + di_info("Security Alarm Detected\n"); + if (dsr & DSR_TTD) + di_info("Temperature Tampering Detected\n"); + if (dsr & DSR_CTD) + di_info("Clock Tampering Detected\n"); + if (dsr & DSR_VTD) + di_info("Voltage Tampering Detected\n"); + if (dsr & DSR_MCO) + di_info("Monotonic Counter Overflow\n"); + if (dsr & DSR_TCO) + di_info("Time Counter Overflow\n"); + } else + di_info("No Tamper Events Detected\n"); + + di_info("%d Key Busy Flag\n", !!(dsr & DSR_KBF)); + di_info("%d Write Busy Flag\n", !!(dsr & DSR_WBF)); + di_info("%d Write Next Flag\n", !!(dsr & DSR_WNF)); + di_info("%d Write Complete Flag\n", !!(dsr & DSR_WCF)); + di_info("%d Write Error Flag\n", !!(dsr & DSR_WEF)); + di_info("%d Random Key Error\n", !!(dsr & DSR_RKE)); + di_info("%d Random Key Valid\n", !!(dsr & DSR_RKV)); + di_info("%d Clock Alarm Flag\n", !!(dsr & DSR_CAF)); + di_info("%d Non-Valid Flag\n", !!(dsr & DSR_NVF)); + di_info("%d Security Violation Flag\n", !!(dsr & DSR_SVF)); +} + +/* + * print out a key in hex + */ +static void print_key(const char *tag, uint8_t *key, int bits) +{ + int bytes = (bits + 7) / 8; + + di_info("%s", tag); + while (bytes--) + os_printk("%02x", *key++); + os_printk("\n"); +} +#endif /* defined(DI_DEBUG) || defined(DI_TESTING) */ + +/* + * dryice normal interrupt service routine + */ +OS_DEV_ISR(dryice_norm_irq) +{ + /* save dryice status register */ + uint32_t dsr = di_read(DSR); + + if (dsr & DSR_WCF) { + /* disable the write-completion interrupt */ + di_write(di_read(DIER) & ~DIER_WCIE, DIER); + + if (todo.status == TODO_ST_PEND_WCF) { + if (dsr & DSR_WEF) { + try_to_clear_wef(); + todo_done(DI_ERR_WRITE); + } else { + todo.cur++; + todo.status = TODO_ST_READY; + todo_run(); + } + } + } else if (dsr & (DSR_RKV | DSR_RKE)) { + /* disable the random-key-gen interrupt */ + di_write(di_read(DIER) & ~DIER_RKIE, DIER); + + if (todo.status == TODO_ST_PEND_RKG) { + if (dsr & DSR_RKE) + todo_done(DI_ERR_FAIL); + else { + todo.cur++; + todo.status = TODO_ST_READY; + todo_run(); + } + } + } + + os_dev_isr_return(1); +} + +/* write loop with error handling -- for init only */ +#define di_write_loop_goto(val, reg, rc, label) \ + do {if (di_write_loop(val, reg)) \ + {rc = OS_ERROR_FAIL_S; goto label; } } while (0) + +/* + * dryice driver initialization + */ +OS_DEV_INIT(dryice_init) +{ + di_return_t rc = 0; + + di_info("MXC DryIce driver\n"); + + /* allocate memory */ + di = os_alloc_memory(sizeof(*di), GFP_KERNEL); + if (di == NULL) { + rc = OS_ERROR_NO_MEMORY_S; + goto err_alloc; + } + memset(di, 0, sizeof(*di)); + di->baseaddr = DRYICE_BASE_ADDR; + di->irq_norm.irq = MXC_INT_DRYICE_NORM; + di->irq_sec.irq = MXC_INT_DRYICE_SEC; + + /* map i/o registers */ + di->ioaddr = os_map_device(di->baseaddr, DI_ADDRESS_RANGE); + if (di->ioaddr == NULL) { + rc = OS_ERROR_FAIL_S; + goto err_iomap; + } + + /* allocate locks */ + di->busy_lock = os_lock_alloc_init(); + if (di->busy_lock == NULL) { + rc = OS_ERROR_NO_MEMORY_S; + goto err_locks; + } + + /* enable clocks (is there a portable way to do this?) */ + di->clk = clk_get(NULL, "dryice_clk"); + clk_enable(di->clk); + + /* register for interrupts */ + /* os_register_interrupt() dosen't support an option to make the + interrupt as shared. Replaced it with request_irq().*/ + rc = request_irq(di->irq_norm.irq, dryice_norm_irq, IRQF_SHARED, + "dry_ice", di); + if (rc) + goto err_irqs; + else + di->irq_norm.set = 1; + + /* + * DRYICE HARDWARE INIT + */ + +#ifdef DI_DEBUG + show_dsr("DSR Pre-Initialization State"); +#endif + + if (di_state() == DI_STATE_NON_VALID) { + uint32_t dsr = di_read(DSR); + + di_debug("initializing from non-valid state\n"); + + /* clear security violation flag */ + if (dsr & DSR_SVF) + di_write_loop_goto(DSR_SVF, DSR, rc, err_write); + + /* clear tamper detect flags */ + if (dsr & DSR_TAMPER_BITS) + di_write_loop_goto(DSR_TAMPER_BITS, DSR, rc, err_write); + + /* initialize timers */ + di_write_loop_goto(0, DTCLR, rc, err_write); + di_write_loop_goto(0, DTCMR, rc, err_write); + di_write_loop_goto(0, DMCR, rc, err_write); + + /* clear non-valid flag */ + di_write_loop_goto(DSR_NVF, DSR, rc, err_write); + } + + /* set tamper events we are interested in watching */ + di_write_loop_goto(DTCR_WTE | DTCR_ETBE | DTCR_ETAE, DTCR, rc, + err_write); +#ifdef DI_DEBUG + show_dsr("DSR Post-Initialization State"); +#endif + os_dev_init_return(OS_ERROR_OK_S); + +err_write: + /* unregister interrupts */ + if (di->irq_norm.set) + os_deregister_interrupt(di->irq_norm.irq); + if (di->irq_sec.set) + os_deregister_interrupt(di->irq_sec.irq); + + /* turn off clocks (is there a portable way to do this?) */ + clk_disable(di->clk); + clk_put(di->clk); + +err_irqs: + /* unallocate locks */ + os_lock_deallocate(di->busy_lock); + +err_locks: + /* unmap i/o registers */ + os_unmap_device(di->ioaddr, DI_ADDRESS_RANGE); + +err_iomap: + /* free the dryice struct */ + os_free_memory(di); + +err_alloc: + os_dev_init_return(rc); +} + +/* + * dryice driver exit routine + */ +OS_DEV_SHUTDOWN(dryice_exit) +{ + /* don't allow new operations */ + di->exit_flag = 1; + + /* wait for the current operation to complete */ + os_sleep(exit_queue, di->busy == 0, 0); + + /* unregister interrupts */ + if (di->irq_norm.set) + os_deregister_interrupt(di->irq_norm.irq); + if (di->irq_sec.set) + os_deregister_interrupt(di->irq_sec.irq); + + /* turn off clocks (is there a portable way to do this?) */ + clk_disable(di->clk); + clk_put(di->clk); + + /* unallocate locks */ + os_lock_deallocate(di->busy_lock); + + /* unmap i/o registers */ + os_unmap_device(di->ioaddr, DI_ADDRESS_RANGE); + + /* free the dryice struct */ + os_free_memory(di); + + os_dev_shutdown_return(OS_ERROR_OK_S); +} + +di_return_t dryice_set_programmed_key(const void *key_data, int key_bits, + int flags) +{ + uint32_t dcr; + int key_bytes, reg; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (key_data == NULL) { + rc = DI_ERR_INVAL; + goto err; + } + if (key_bits < 0 || key_bits > MAX_KEY_LEN || key_bits % 8) { + rc = DI_ERR_INVAL; + goto err; + } + if (flags & DI_FUNC_FLAG_WORD_KEY) { + if (key_bits % 32 || (uint32_t)key_data & 0x3) { + rc = DI_ERR_INVAL; + goto err; + } + } + if (di->key_programmed) { + rc = DI_ERR_INUSE; + goto err; + } + if (di_state() == DI_STATE_FAILURE) { + rc = DI_ERR_STATE; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_PKWHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_PKWSL) { + rc = DI_ERR_SLOCK; + goto err; + } + key_bytes = key_bits / 8; + + todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0); + + /* accomodate busses that can only do 32-bit transfers */ + if (flags & DI_FUNC_FLAG_WORD_KEY) { + uint32_t *keyp = (void *)key_data; + + for (reg = 0; reg < MAX_KEY_WORDS; reg++) { + if (reg < MAX_KEY_WORDS - key_bytes / 4) + todo_write_val(0, DPKR7 - reg * 4); + else { + todo_write_ptr32(keyp, DPKR7 - reg * 4); + keyp++; + } + } + } else { + uint8_t *keyp = (void *)key_data; + + for (reg = 0; reg < MAX_KEY_WORDS; reg++) { + int size = key_bytes - (MAX_KEY_WORDS - reg - 1) * 4; + if (size <= 0) + todo_write_val(0, DPKR7 - reg * 4); + else { + if (size > 4) + size = 4; + todo_write_ptr(keyp, DPKR7 - reg * 4, size); + keyp += size; + } + } + } + todo_assign(di->key_programmed, 1); + + if (flags & DI_FUNC_LOCK_FLAGS) { + dcr = di_read(DCR); + if (flags & DI_FUNC_FLAG_READ_LOCK) { + if (flags & DI_FUNC_FLAG_HARD_LOCK) + dcr |= DCR_PKRHL; + else + dcr |= DCR_PKRSL; + } + if (flags & DI_FUNC_FLAG_WRITE_LOCK) { + if (flags & DI_FUNC_FLAG_HARD_LOCK) + dcr |= DCR_PKWHL; + else + dcr |= DCR_PKWSL; + } + todo_write_val(dcr, DCR); + } + todo_start(); + + if (flags & DI_FUNC_FLAG_ASYNC) + return 0; + + rc = todo_wait_done(); +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_set_programmed_key); + +di_return_t dryice_get_programmed_key(uint8_t *key_data, int key_bits) +{ + int reg, byte, key_bytes; + uint32_t dcr, dpkr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (key_data == NULL) { + rc = DI_ERR_INVAL; + goto err; + } + if (key_bits < 0 || key_bits > MAX_KEY_LEN || key_bits % 8) { + rc = DI_ERR_INVAL; + goto err; + } + #if 0 + if (!di->key_programmed) { + rc = DI_ERR_UNSET; + goto err; + } + #endif + if (di_state() == DI_STATE_FAILURE) { + rc = DI_ERR_STATE; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_PKRHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_PKRSL) { + rc = DI_ERR_SLOCK; + goto err; + } + key_bytes = key_bits / 8; + + /* read key */ + for (reg = 0; reg < MAX_KEY_WORDS; reg++) { + if (reg < (MAX_KEY_BYTES - key_bytes) / 4) + continue; + dpkr = di_read(DPKR7 - reg * 4); + + for (byte = 0; byte < 4; byte++) { + if (reg * 4 + byte >= MAX_KEY_BYTES - key_bytes) { + int shift = 24 - byte * 8; + *key_data++ = (dpkr >> shift) & 0xff; + } + } + dpkr = 0; /* cleared for security */ + } +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_get_programmed_key); + +di_return_t dryice_release_programmed_key(void) +{ + uint32_t dcr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (!di->key_programmed) { + rc = DI_ERR_UNSET; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_PKWHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_PKWSL) { + rc = DI_ERR_SLOCK; + goto err; + } + di->key_programmed = 0; + +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_release_programmed_key); + +di_return_t dryice_set_random_key(int flags) +{ + uint32_t dcr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (di_state() == DI_STATE_FAILURE) { + rc = DI_ERR_STATE; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_RKHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_RKSL) { + rc = DI_ERR_SLOCK; + goto err; + } + todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0); + + /* clear Random Key Error bit, if set */ + if (di_read(DSR) & DSR_RKE) + todo_write_val(DSR_RKE, DCR); + + /* load random key */ + todo_write_val(DKCR_LRK, DKCR); + + /* wait for RKV (valid) or RKE (error) */ + todo_wait_rkg(); + + if (flags & DI_FUNC_LOCK_FLAGS) { + dcr = di_read(DCR); + if (flags & DI_FUNC_FLAG_WRITE_LOCK) { + if (flags & DI_FUNC_FLAG_HARD_LOCK) + dcr |= DCR_RKHL; + else + dcr |= DCR_RKSL; + } + todo_write_val(dcr, DCR); + } + todo_start(); + + if (flags & DI_FUNC_FLAG_ASYNC) + return 0; + + rc = todo_wait_done(); +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_set_random_key); + +di_return_t dryice_select_key(di_key_t key, int flags) +{ + uint32_t dcr, dksr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + switch (key) { + case DI_KEY_FK: + dksr = DKSR_IIM_KEY; + break; + case DI_KEY_PK: + dksr = DKSR_PROG_KEY; + break; + case DI_KEY_RK: + dksr = DKSR_RAND_KEY; + break; + case DI_KEY_FPK: + dksr = DKSR_PROG_XOR_IIM_KEY; + break; + case DI_KEY_FRK: + dksr = DKSR_RAND_XOR_IIM_KEY; + break; + default: + rc = DI_ERR_INVAL; + goto err; + } + if (di->key_selected) { + rc = DI_ERR_INUSE; + goto err; + } + if (di_state() != DI_STATE_VALID) { + rc = DI_ERR_STATE; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_KSHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_KSSL) { + rc = DI_ERR_SLOCK; + goto err; + } + todo_init((flags & DI_FUNC_FLAG_ASYNC) != 0); + + /* select key */ + todo_write_val(dksr, DKSR); + + todo_assign(di->key_selected, 1); + + if (flags & DI_FUNC_LOCK_FLAGS) { + dcr = di_read(DCR); + if (flags & DI_FUNC_FLAG_WRITE_LOCK) { + if (flags & DI_FUNC_FLAG_HARD_LOCK) + dcr |= DCR_KSHL; + else + dcr |= DCR_KSSL; + } + todo_write_val(dcr, DCR); + } + todo_start(); + + if (flags & DI_FUNC_FLAG_ASYNC) + return 0; + + rc = todo_wait_done(); +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_select_key); + +di_return_t dryice_check_key(di_key_t *key) +{ + uint32_t dksr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (key == NULL) { + rc = DI_ERR_INVAL; + goto err; + } + + dksr = di_read(DKSR); + + if (di_state() != DI_STATE_VALID) { + dksr = DKSR_IIM_KEY; + rc = DI_ERR_STATE; + } else if (dksr == DI_KEY_RK || dksr == DI_KEY_FRK) { + if (!(di_read(DSR) & DSR_RKV)) { + dksr = DKSR_IIM_KEY; + rc = DI_ERR_UNSET; + } + } + switch (dksr) { + case DKSR_IIM_KEY: + *key = DI_KEY_FK; + break; + case DKSR_PROG_KEY: + *key = DI_KEY_PK; + break; + case DKSR_RAND_KEY: + *key = DI_KEY_RK; + break; + case DKSR_PROG_XOR_IIM_KEY: + *key = DI_KEY_FPK; + break; + case DKSR_RAND_XOR_IIM_KEY: + *key = DI_KEY_FRK; + break; + } +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_check_key); + +di_return_t dryice_release_key_selection(void) +{ + uint32_t dcr; + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (!di->key_selected) { + rc = DI_ERR_UNSET; + goto err; + } + dcr = di_read(DCR); + if (dcr & DCR_KSHL) { + rc = DI_ERR_HLOCK; + goto err; + } + if (dcr & DCR_KSSL) { + rc = DI_ERR_SLOCK; + goto err; + } + di->key_selected = 0; + +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_release_key_selection); + +di_return_t dryice_get_tamper_event(uint32_t *events, uint32_t *timestamp, + int flags) +{ + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + if (di_state() == DI_STATE_VALID) { + rc = DI_ERR_STATE; + goto err; + } + if (events == NULL) { + rc = DI_ERR_INVAL; + goto err; + } + *events = di_read(DSR) & DSR_TAMPER_BITS; + if (timestamp) { + if (di_state() == DI_STATE_NON_VALID) + *timestamp = di_read(DTCMR); + else + *timestamp = 0; + } +err: + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_get_tamper_event); + +di_return_t dryice_register_callback(void (*func)(di_return_t, + unsigned long cookie), + unsigned long cookie) +{ + di_return_t rc = 0; + + if (di_busy_set()) + return DI_ERR_BUSY; + + di->cb_func = func; + di->cb_cookie = cookie; + + di_busy_clear(); + return rc; +} +EXTERN_SYMBOL(dryice_register_callback); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("DryIce"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/security/dryice.h b/drivers/mxc/security/dryice.h new file mode 100644 index 000000000000..127e0bcd5d1b --- /dev/null +++ b/drivers/mxc/security/dryice.h @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#ifndef __DRYICE_H__ +#define __DRYICE_H__ + + +/*! + * @file dryice.h + * @brief Definition of DryIce API. + */ + +/*! @page dryice_api DryIce API + * + * Definition of the DryIce API. + * + * The DryIce API implements a software interface to the DryIce hardware + * block. Methods are provided to store, retrieve, generate, and manage + * cryptographic keys and to monitor security tamper events. + * + * See @ref dryice_api for the DryIce API. + */ + +/*! + * This defines the SCC key length (in bits) + */ +#define SCC_KEY_LEN 168 + +/*! + * This defines the maximum key length (in bits) + */ +#define MAX_KEY_LEN 256 +#define MAX_KEY_BYTES ((MAX_KEY_LEN) / 8) +#define MAX_KEY_WORDS ((MAX_KEY_LEN) / 32) + +/*! + * @name DryIce Function Flags + */ +/*@{*/ +#define DI_FUNC_FLAG_ASYNC 0x01 /*!< do not block */ +#define DI_FUNC_FLAG_READ_LOCK 0x02 /*!< set read lock for this resource */ +#define DI_FUNC_FLAG_WRITE_LOCK 0x04 /*!< set write lock for resource */ +#define DI_FUNC_FLAG_HARD_LOCK 0x08 /*!< locks will be hard (default soft) */ +#define DI_FUNC_FLAG_WORD_KEY 0x10 /*!< key provided as 32-bit words */ +/*@}*/ + +/*! + * @name DryIce Tamper Events + */ +/*@{*/ +#define DI_TAMPER_EVENT_WTD (1 << 23) /*!< wire-mesh tampering det */ +#define DI_TAMPER_EVENT_ETBD (1 << 22) /*!< ext tampering det: input B */ +#define DI_TAMPER_EVENT_ETAD (1 << 21) /*!< ext tampering det: input A */ +#define DI_TAMPER_EVENT_EBD (1 << 20) /*!< external boot detected */ +#define DI_TAMPER_EVENT_SAD (1 << 19) /*!< security alarm detected */ +#define DI_TAMPER_EVENT_TTD (1 << 18) /*!< temperature tampering det */ +#define DI_TAMPER_EVENT_CTD (1 << 17) /*!< clock tampering det */ +#define DI_TAMPER_EVENT_VTD (1 << 16) /*!< voltage tampering det */ +#define DI_TAMPER_EVENT_MCO (1 << 3) /*!< monotonic counter overflow */ +#define DI_TAMPER_EVENT_TCO (1 << 2) /*!< time counter overflow */ +/*@}*/ + +/*! + * DryIce Key Sources + */ +typedef enum di_key { + DI_KEY_FK, /*!< the fused (IIM) key */ + DI_KEY_PK, /*!< the programmed key */ + DI_KEY_RK, /*!< the random key */ + DI_KEY_FPK, /*!< the programmed key XORed with the fused key */ + DI_KEY_FRK, /*!< the random key XORed with the fused key */ +} di_key_t; + +/*! + * DryIce Error Codes + */ +typedef enum dryice_return { + DI_SUCCESS = 0, /*!< operation was successful */ + DI_ERR_BUSY, /*!< device or resource busy */ + DI_ERR_STATE, /*!< dryice is in incompatible state */ + DI_ERR_INUSE, /*!< resource is already in use */ + DI_ERR_UNSET, /*!< resource has not been initialized */ + DI_ERR_WRITE, /*!< error occurred during register write */ + DI_ERR_INVAL, /*!< invalid argument */ + DI_ERR_FAIL, /*!< operation failed */ + DI_ERR_HLOCK, /*!< resource is hard locked */ + DI_ERR_SLOCK, /*!< resource is soft locked */ + DI_ERR_NOMEM, /*!< out of memory */ +} di_return_t; + +/*! + * These functions define the DryIce API. + */ + +/*! + * Write a given key to the Programmed Key registers in DryIce, and + * optionally lock the Programmed Key against either reading or further + * writing. The value is held until a call to the release_programmed_key + * interface is made, or until the appropriate HW reset if the write-lock + * flags are used. Unused key bits will be zeroed. + * + * @param[in] key_data A pointer to the key data to be programmed, with + * the most significant byte or word first. This + * will be interpreted as a byte pointer unless the + * WORD_KEY flag is set, in which case it will be + * treated as a word pointer and the key data will be + * read a word at a time, starting with the MSW. + * When called asynchronously, the data pointed to by + * key_data must persist until the operation completes. + * + * @param[in] key_bits The number of bits in the key to be stored. + * This must be a multiple of 8 and within the + * range of 0 and MAX_KEY_LEN. + * + * @param[in] flags This is a bit-wise OR of the flags to be passed + * to the function. Flags can include: + * ASYNC, READ_LOCK, WRITE_LOCK, HARD_LOCK, and + * WORD_KEY. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, INVAL + * on invalid arguments, INUSE if key has already been + * programmed, STATE if DryIce is in the wrong state, + * HLOCK or SLOCK if the key registers are locked for + * writing, and WRITE if a write error occurs + * (See #di_return_t). + */ +extern di_return_t dryice_set_programmed_key(const void *key_data, int key_bits, + int flags); + +/*! + * Read the Programmed Key registers and write the contents into a buffer. + * + * @param[out] key_data A byte pointer to where the key data will be written, + * with the most significant byte being written first. + * + * @param[in] key_bits The number of bits of the key to be retrieved. + * This must be a multiple of 8 and within the + * range of 0 and MAX_KEY_LEN. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, INVAL + * on invalid arguments, UNSET if key has not been + * programmed, STATE if DryIce is in the wrong state, + * and HLOCK or SLOCK if the key registers are locked for + * reading (See #di_return_t). + */ +extern di_return_t dryice_get_programmed_key(uint8_t *key_data, int key_bits); + +/*! + * Allow the set_programmed_key interface to be used to write a new + * Programmed Key to DryIce. Note that this interface does not overwrite + * the value in the Programmed Key registers. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, + * UNSET if the key has not been previously set, and + * HLOCK or SLOCK if the key registers are locked for + * writing (See #di_return_t). + */ +extern di_return_t dryice_release_programmed_key(void); + +/*! + * Generate and load a new Random Key in DryIce, and optionally lock the + * Random Key against further change. + * + * @param[in] flags This is a bit-wise OR of the flags to be passed + * to the function. Flags can include: + * ASYNC, READ_LOCK, WRITE_LOCK, and HARD_LOCK. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, STATE + * if DryIce is in the wrong state, FAIL if the key gen + * failed, HLOCK or SLOCK if the key registers are + * locked, and WRITE if a write error occurs + * (See #di_return_t). + */ +extern di_return_t dryice_set_random_key(int flags); + +/*! + * Set the key selection in DryIce to determine the key used by an + * encryption module such as SCC. The selection is held until a call to the + * Release Selected Key interface is made, or until the appropriate HW + * reset if the LOCK flags are used. + * + * @param[in] key The source of the key to be used by the SCC + * (See #di_key_t). + * + * @param[in] flags This is a bit-wise OR of the flags to be passed + * to the function. Flags can include: + * ASYNC, WRITE_LOCK, and HARD_LOCK. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, INVAL + * on invalid arguments, INUSE if a selection has already + * been made, STATE if DryIce is in the wrong state, + * HLOCK or SLOCK if the selection register is locked, + * and WRITE if a write error occurs + */ +extern di_return_t dryice_select_key(di_key_t key, int flags); + +/*! + * Check which key will be used in the SCC. This is needed because in some + * DryIce states, the Key Select Register is overridden by a default value + * (the Fused/IIM key). + * + * @param[out] key The source of the key that is currently selected for + * use by the SCC. This may be different from the key + * specified by the dryice_select_key function + * (See #di_key_t). This value is set even if an error + * code (except for BUSY) is returned. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, STATE if + * DryIce is in the wrong state, INVAL on invalid + * arguments, or UNSET if no key has been selected + * (See #di_return_t). + */ +extern di_return_t dryice_check_key(di_key_t *key); + +/*! + * Allow the dryice_select_key interface to be used to set a new key selection + * in DryIce. Note that this interface does not overwrite the value in DryIce. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, UNSET + * if the no selection has been made previously, and + * HLOCK or SLOCK if the selection register is locked + * (See #di_return_t). + */ +extern di_return_t dryice_release_key_selection(void); + +/*! + * Returns tamper-detection status bits. Also an optional timestamp when + * DryIce is in the Non-valid state. If DryIce is not in Failure or Non-valid + * state, this interface returns a failure code. + * + * @param[out] events This is a bit-wise OR of the following events: + * WTD (Wire Mesh), ETBD (External Tamper B), + * ETAD (External Tamper A), EBD (External Boot), + * SAD (Security Alarm), TTD (Temperature Tamper), + * CTD (Clock Tamper), VTD (Voltage Tamper), + * MCO (Monolithic Counter Overflow), and + * TCO (Time Counter Overflow). + * + * @param[out] timestamp This is the value of the time counter in seconds + * when the tamper occurred. A timestamp will not be + * returned if a NULL pointer is specified. If DryIce + * is not in the Non-valid state the time cannot be + * read, so a timestamp of 0 will be returned. + * + * @param[in] flags This is a bit-wise OR of the flags to be passed + * to the function. Flags is ignored currently by + * this function. + * + * @return Returns SUCCESS (0), BUSY if DryIce is busy, and + * INVAL on invalid arguments (See #di_return_t). + */ +extern di_return_t +dryice_get_tamper_event(uint32_t *events, uint32_t *timestamp, int flags); + +/*! + * Provide a callback function to be called upon the completion of DryIce calls + * that are executed asynchronously. + * + * @param[in] func This is a pointer to a function of type: + * void callback(di_return_t rc, unsigned long cookie) + * The return code of the async function is passed + * back in "rc" along with the cookie provided when + * registering the callback. + * + * @param[in] cookie This is an "opaque" cookie of type unsigned long that + * is returned on subsequent callbacks. It may be of any + * value. + * + * @return Returns SUCCESS (0), or BUSY if DryIce is busy + * (See #di_return_t). + */ +extern di_return_t dryice_register_callback(void (*func)(di_return_t rc, + unsigned long cookie), + unsigned long cookie); + +#endif /* __DRYICE_H__ */ diff --git a/drivers/mxc/security/mxc_scc.c b/drivers/mxc/security/mxc_scc.c new file mode 100644 index 000000000000..20d54bfb5362 --- /dev/null +++ b/drivers/mxc/security/mxc_scc.c @@ -0,0 +1,2386 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_scc.c + * + * This is the driver code for the Security Controller (SCC). It has no device + * driver interface, so no user programs may access it. Its interaction with + * the Linux kernel is from calls to #scc_init() when the driver is loaded, and + * #scc_cleanup() should the driver be unloaded. The driver uses locking and + * (task-sleep/task-wakeup) functions of the kernel. It also registers itself + * to handle the interrupt line(s) from the SCC. + * + * Other drivers in the kernel may use the remaining API functions to get at + * the services of the SCC. The main service provided is the Secure Memory, + * which allows encoding and decoding of secrets with a per-chip secret key. + * + * The SCC is single-threaded, and so is this module. When the scc_crypt() + * routine is called, it will lock out other accesses to the function. If + * another task is already in the module, the subsequent caller will spin on a + * lock waiting for the other access to finish. + * + * Note that long crypto operations could cause a task to spin for a while, + * preventing other kernel work (other than interrupt processing) to get done. + * + * The external (kernel module) interface is through the following functions: + * @li scc_get_configuration() + * @li scc_crypt() + * @li scc_zeroize_memories() + * @li scc_monitor_security_failure() + * @li scc_stop_monitoring_security_failure() + * @li scc_set_sw_alarm() + * @li scc_read_register() + * @li scc_write_register() + * + * All other functions are internal to the driver. + * + * @ingroup MXCSCC +*/ +#include "sahara2/include/fsl_platform.h" +#include "sahara2/include/portable_os.h" +#include "mxc_scc_internals.h" + +#include + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + +#include +#include +#include + +#else +#include +#include +#include + +#endif + +/*! + * This is the set of errors which signal that access to the SCM RAM has + * failed or will fail. + */ +#define SCM_ACCESS_ERRORS \ + (SCM_ERR_USER_ACCESS | SCM_ERR_ILLEGAL_ADDRESS | \ + SCM_ERR_ILLEGAL_MASTER | SCM_ERR_CACHEABLE_ACCESS | \ + SCM_ERR_UNALIGNED_ACCESS | SCM_ERR_BYTE_ACCESS | \ + SCM_ERR_INTERNAL_ERROR | SCM_ERR_SMN_BLOCKING_ACCESS | \ + SCM_ERR_CIPHERING | SCM_ERR_ZEROIZING | SCM_ERR_BUSY) +/****************************************************************************** + * + * Global / Static Variables + * + *****************************************************************************/ + +/*! + * This is type void* so that a) it cannot directly be dereferenced, + * and b) pointer arithmetic on it will function in a 'normal way' for + * the offsets in scc_defines.h + * + * scc_base is the location in the iomap where the SCC's registers + * (and memory) start. + * + * The referenced data is declared volatile so that the compiler will + * not make any assumptions about the value of registers in the SCC, + * and thus will always reload the register into CPU memory before + * using it (i.e. wherever it is referenced in the driver). + * + * This value should only be referenced by the #SCC_READ_REGISTER and + * #SCC_WRITE_REGISTER macros and their ilk. All dereferences must be + * 32 bits wide. + */ +static volatile void *scc_base; + +/*! Array to hold function pointers registered by + #scc_monitor_security_failure() and processed by + #scc_perform_callbacks() */ +static void (*scc_callbacks[SCC_CALLBACK_SIZE]) (void); + +/*! Structure returned by #scc_get_configuration() */ +static scc_config_t scc_configuration = { + .driver_major_version = SCC_DRIVER_MAJOR_VERSION_1, + .driver_minor_version = SCC_DRIVER_MINOR_VERSION_8, + .scm_version = -1, + .smn_version = -1, + .block_size_bytes = -1, + .black_ram_size_blocks = -1, + .red_ram_size_blocks = -1 +}; + +/*! Key Control Information. Integrity is controlled by use of + #scc_crypto_lock. */ +static struct scc_key_slot scc_key_info[SCC_KEY_SLOTS]; + +/*! Internal flag to know whether SCC is in Failed state (and thus many + * registers are unavailable). Once it goes failed, it never leaves it. */ +static volatile enum scc_status scc_availability = SCC_STATUS_INITIAL; + +/*! Flag to say whether interrupt handler has been registered for + * SMN interrupt */ +static int smn_irq_set = 0; + +/*! Flag to say whether interrupt handler has been registered for + * SCM interrupt */ +static int scm_irq_set = 0; + +/*! This lock protects the #scc_callbacks list as well as the @c + * callbacks_performed flag in #scc_perform_callbacks. Since the data this + * protects may be read or written from either interrupt or base level, all + * operations should use the irqsave/irqrestore or similar to make sure that + * interrupts are inhibited when locking from base level. + */ +static spinlock_t scc_callbacks_lock = SPIN_LOCK_UNLOCKED; + +/*! + * Ownership of this lock prevents conflicts on the crypto operation in the SCC + * and the integrity of the #scc_key_info. + */ +static spinlock_t scc_crypto_lock = SPIN_LOCK_UNLOCKED; + +/*! Calculated once for quick reference to size of the unreserved space in one + * RAM in SCM. + */ +static uint32_t scc_memory_size_bytes; + +/*! Calculated once for quick reference to size of SCM address space */ +static uint32_t scm_highest_memory_address; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)) +#ifndef SCC_CLOCK_NOT_GATED +/*! Pointer to SCC's clock information. Initialized during scc_init(). */ +static struct clk *scc_clk = NULL; +#endif +#endif + +/*! The lookup table for an 8-bit value. Calculated once + * by #scc_init_ccitt_crc(). + */ +static uint16_t scc_crc_lookup_table[256]; + +/*! Fixed padding for appending to plaintext to fill out a block */ +static uint8_t scc_block_padding[8] = + { SCC_DRIVER_PAD_CHAR, 0, 0, 0, 0, 0, 0, 0 }; + +/****************************************************************************** + * + * Function Implementations - Externally Accessible + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn scc_init() */ +/*****************************************************************************/ +/*! + * Initialize the driver at boot time or module load time. + * + * Register with the kernel as the interrupt handler for the SCC interrupt + * line(s). + * + * Map the SCC's register space into the driver's memory space. + * + * Query the SCC for its configuration and status. Save the configuration in + * #scc_configuration and save the status in #scc_availability. Called by the + * kernel. + * + * Do any locking/wait queue initialization which may be necessary. + * + * The availability fuse may be checked, depending on platform. + */ +static int scc_init(void) +{ + uint32_t smn_status; + int i; + int return_value = -EIO; /* assume error */ + if (scc_availability == SCC_STATUS_INITIAL) { + + /* Set this until we get an initial reading */ + scc_availability = SCC_STATUS_CHECKING; + + /* Initialize the constant for the CRC function */ + scc_init_ccitt_crc(); + + /* initialize the callback table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + scc_callbacks[i] = 0; + } + + /* Initialize key slots */ + for (i = 0; i < SCC_KEY_SLOTS; i++) { + scc_key_info[i].offset = i * SCC_KEY_SLOT_SIZE; + scc_key_info[i].status = 0; /* unassigned */ + } + + /* Enable the SCC clock on platforms where it is gated */ +#ifndef SCC_CLOCK_NOT_GATED + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + mxc_clks_enable(SCC_CLK); +#else + + scc_clk = clk_get(NULL, "scc_clk"); + if (scc_clk != ERR_PTR(ENOENT)) { + clk_enable(scc_clk); + } +#endif /* LINUX_VERSION_CODE */ + +#endif /* SCC_CLOCK_NOT_GATED */ + /* See whether there is an SCC available */ + if (0 && !SCC_ENABLED()) { + os_printk(KERN_ERR + "SCC: Fuse for SCC is set to disabled. Exiting.\n"); + } else { + /* Map the SCC (SCM and SMN) memory on the internal bus into + kernel address space */ + scc_base = (void *)IO_ADDRESS(SCC_BASE); + + /* If that worked, we can try to use the SCC */ + if (scc_base == NULL) { + os_printk(KERN_ERR + "SCC: Register mapping failed. Exiting.\n"); + } else { + /* Get SCM into 'clean' condition w/interrupts cleared & + disabled */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | + SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + + /* Clear error status register (any write will do it) */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0); + + /* + * There is an SCC. Determine its current state. Side effect + * is to populate scc_config and scc_availability + */ + smn_status = scc_grab_config_values(); + + /* Try to set up interrupt handler(s) */ + if (scc_availability == SCC_STATUS_OK) { + if (setup_interrupt_handling() != 0) { + unsigned condition; + /*! + * The error could be only that the SCM interrupt was + * not set up. This interrupt is always masked, so + * that is not an issue. + * + * The SMN's interrupt may be shared on that line, it + * may be separate, or it may not be wired. Do what + * is necessary to check its status. + * + * Although the driver is coded for possibility of not + * having SMN interrupt, the fact that there is one + * means it should be available and used. + */ +#ifdef USE_SMN_INTERRUPT + condition = !smn_irq_set; /* Separate. Check SMN binding */ +#elif !defined(NO_SMN_INTERRUPT) + condition = !scm_irq_set; /* Shared. Check SCM binding */ +#else + condition = FALSE; /* SMN not wired at all. Ignore. */ +#endif + /* setup was not able to set up SMN interrupt */ + scc_availability = + SCC_STATUS_UNIMPLEMENTED; + } /* interrupt handling returned non-zero */ + } /* availability is OK */ + if (scc_availability == SCC_STATUS_OK) { + /* Get SMN into 'clean' condition w/interrupts cleared & + enabled */ + SCC_WRITE_REGISTER(SMN_COMMAND, + SMN_COMMAND_CLEAR_INTERRUPT + | + SMN_COMMAND_ENABLE_INTERRUPT); + } + /* availability is still OK */ + } /* if scc_base != NULL */ + + } /* if SCC_ENABLED() */ + + /* + * If status is SCC_STATUS_UNIMPLEMENTED or is still + * SCC_STATUS_CHECKING, could be leaving here with the driver partially + * initialized. In either case, cleanup (which will mark the SCC as + * UNIMPLEMENTED). + */ + if (scc_availability == SCC_STATUS_CHECKING || + scc_availability == SCC_STATUS_UNIMPLEMENTED) { + scc_cleanup(); + } else { + return_value = 0; /* All is well */ + } + } + /* ! STATUS_INITIAL */ + pr_debug("SCC: Driver Status is %s\n", + (scc_availability == SCC_STATUS_INITIAL) ? "INITIAL" : + (scc_availability == SCC_STATUS_CHECKING) ? "CHECKING" : + (scc_availability == + SCC_STATUS_UNIMPLEMENTED) ? "UNIMPLEMENTED" + : (scc_availability == + SCC_STATUS_OK) ? "OK" : (scc_availability == + SCC_STATUS_FAILED) ? "FAILED" : + "UNKNOWN"); + + return return_value; +} /* scc_init */ + +/*****************************************************************************/ +/* fn scc_cleanup() */ +/*****************************************************************************/ +/*! + * Perform cleanup before driver/module is unloaded by setting the machine + * state close to what it was when the driver was loaded. This function is + * called when the kernel is shutting down or when this driver is being + * unloaded. + * + * A driver like this should probably never be unloaded, especially if there + * are other module relying upon the callback feature for monitoring the SCC + * status. + * + * In any case, cleanup the callback table (by clearing out all of the + * pointers). Deregister the interrupt handler(s). Unmap SCC registers. + * + */ +static void scc_cleanup(void) +{ + int i; + + /* Mark the driver / SCC as unusable. */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; + + /* Clear out callback table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + scc_callbacks[i] = 0; + } + + /* If SCC has been mapped in, clean it up and unmap it */ + if (scc_base) { + /* For the SCM, disable interrupts, zeroize RAMs. Interrupt + * status will appear because zeroize will complete. */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_MASK_INTERRUPTS | + SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY); + + /* For the SMN, clear and disable interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_CLEAR_INTERRUPT); + + /* remove virtual mapping */ + iounmap((void *)scc_base); + } + + /* Now that interrupts cannot occur, disassociate driver from the interrupt + * lines. + */ + + /* Deregister SCM interrupt handler */ + if (scm_irq_set) { + os_deregister_interrupt(INT_SCC_SCM); + } + + /* Deregister SMN interrupt handler */ + if (smn_irq_set) { +#ifdef USE_SMN_INTERRUPT + os_deregister_interrupt(INT_SCC_SMN); +#endif + } + pr_debug("SCC driver cleaned up.\n"); + +} /* scc_cleanup */ + +/*****************************************************************************/ +/* fn scc_get_configuration() */ +/*****************************************************************************/ +scc_config_t *scc_get_configuration(void) +{ + /* + * If some other driver calls scc before the kernel does, make sure that + * this driver's initialization is performed. + */ + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /*! + * If there is no SCC, yet the driver exists, the value -1 will be in + * the #scc_config_t fields for other than the driver versions. + */ + return &scc_configuration; +} /* scc_get_configuration */ + +/*****************************************************************************/ +/* fn scc_zeroize_memories() */ +/*****************************************************************************/ +scc_return_t scc_zeroize_memories(void) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + if (scc_availability == SCC_STATUS_OK) { + unsigned long irq_flags; /* for IRQ save/restore */ + + /* Lock access to crypto memory of the SCC */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + /* Start the Zeroize by setting a bit in the SCM_INTERRUPT_CTRL + * register */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_MASK_INTERRUPTS + | SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY); + + scc_wait_completion(); + + /* Get any error info */ + status = SCC_READ_REGISTER(SCM_ERROR_STATUS); + + /* unlock the SCC */ + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + if (!(status & SCM_ERR_ZEROIZE_FAILED)) { + return_status = SCC_RET_OK; + } else { + pr_debug + ("SCC: Zeroize failed. SCM Error Status is 0x%08x\n", + status); + } + + /* Clear out any status. */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + + /* and any error status */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0); + } + + return return_status; +} /* scc_zeroize_memories */ + +/*****************************************************************************/ +/* fn scc_crypt() */ +/*****************************************************************************/ +scc_return_t +scc_crypt(unsigned long count_in_bytes, const uint8_t * data_in, + const uint8_t * init_vector, + scc_enc_dec_t direction, scc_crypto_mode_t crypto_mode, + scc_verify_t check_mode, uint8_t * data_out, + unsigned long *count_out_bytes) + +{ + scc_return_t return_code = SCC_RET_FAIL; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + (void)scc_update_state(); /* in case no interrupt line from SMN */ + + /* make initial error checks */ + if (scc_availability != SCC_STATUS_OK + || count_in_bytes == 0 + || data_in == 0 + || data_out == 0 + || (crypto_mode != SCC_CBC_MODE && crypto_mode != SCC_ECB_MODE) + || (crypto_mode == SCC_CBC_MODE && init_vector == NULL) + || (direction != SCC_ENCRYPT && direction != SCC_DECRYPT) + || (check_mode == SCC_VERIFY_MODE_NONE && + count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0) + || (direction == SCC_DECRYPT && + count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0) + || (check_mode != SCC_VERIFY_MODE_NONE && + check_mode != SCC_VERIFY_MODE_CCITT_CRC)) { + pr_debug + ("SCC: scc_crypt() count_in_bytes_ok = %d; data_in_ok = %d;" + " data_out_ok = %d; iv_ok = %d\n", !(count_in_bytes == 0), + !(data_in == 0), !(data_out == 0), + !(crypto_mode == SCC_CBC_MODE && init_vector == NULL)); + pr_debug("SCC: scc_crypt() mode_ok=%d; direction_ok=%d;" + " size_ok=%d, check_mode_ok=%d\n", + !(crypto_mode != SCC_CBC_MODE + && crypto_mode != SCC_ECB_MODE), + !(direction != SCC_ENCRYPT + && direction != SCC_DECRYPT), + !((check_mode == SCC_VERIFY_MODE_NONE + && count_in_bytes % SCC_BLOCK_SIZE_BYTES() != 0) + || (direction == SCC_DECRYPT + && count_in_bytes % SCC_BLOCK_SIZE_BYTES() != + 0)), !(check_mode != SCC_VERIFY_MODE_NONE + && check_mode != + SCC_VERIFY_MODE_CCITT_CRC)); + pr_debug("SCC: scc_crypt() detected bad argument\n"); + } else { + /* Start settings for write to SCM_CONTROL register */ + uint32_t scc_control = SCM_CONTROL_START_CIPHER; + unsigned long irq_flags; /* for IRQ save/restore */ + + /* Lock access to crypto memory of the SCC */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + /* Special needs for CBC Mode */ + if (crypto_mode == SCC_CBC_MODE) { + scc_control |= SCM_CBC_MODE; /* change default of ECB */ + /* Put in Initial Context. Vector registers are contiguous */ + copy_to_scc(init_vector, SCM_INIT_VECTOR_0, + SCC_BLOCK_SIZE_BYTES(), NULL); + } + + /* Fill the RED_START register */ + SCC_WRITE_REGISTER(SCM_RED_START, + SCM_NON_RESERVED_OFFSET / + SCC_BLOCK_SIZE_BYTES()); + + /* Fill the BLACK_START register */ + SCC_WRITE_REGISTER(SCM_BLACK_START, + SCM_NON_RESERVED_OFFSET / + SCC_BLOCK_SIZE_BYTES()); + + if (direction == SCC_ENCRYPT) { + /* Check for sufficient space in data_out */ + if (check_mode == SCC_VERIFY_MODE_NONE) { + if (*count_out_bytes < count_in_bytes) { + return_code = + SCC_RET_INSUFFICIENT_SPACE; + } + } else { /* SCC_VERIFY_MODE_CCITT_CRC */ + /* Calculate extra bytes needed for crc (2) and block + padding */ + int padding_needed = + CRC_SIZE_BYTES + SCC_BLOCK_SIZE_BYTES() - + ((count_in_bytes + CRC_SIZE_BYTES) + % SCC_BLOCK_SIZE_BYTES()); + + /* Verify space is available */ + if (*count_out_bytes < + count_in_bytes + padding_needed) { + return_code = + SCC_RET_INSUFFICIENT_SPACE; + } + } + /* If did not detect space error, do the encryption */ + if (return_code != SCC_RET_INSUFFICIENT_SPACE) { + return_code = + scc_encrypt(count_in_bytes, data_in, + scc_control, data_out, + check_mode == + SCC_VERIFY_MODE_CCITT_CRC, + count_out_bytes); + } + + } + /* direction == SCC_ENCRYPT */ + else { /* SCC_DECRYPT */ + /* Check for sufficient space in data_out */ + if (check_mode == SCC_VERIFY_MODE_NONE) { + if (*count_out_bytes < count_in_bytes) { + return_code = + SCC_RET_INSUFFICIENT_SPACE; + } + } else { /* SCC_VERIFY_MODE_CCITT_CRC */ + /* Do initial check. Assume last block (of padding) and CRC + * will get stripped. After decipher is done and padding is + * removed, will know exact value. + */ + int possible_size = + (int)count_in_bytes - CRC_SIZE_BYTES - + SCC_BLOCK_SIZE_BYTES(); + if ((int)*count_out_bytes < possible_size) { + pr_debug + ("SCC: insufficient decrypt space %ld/%d.\n", + *count_out_bytes, possible_size); + return_code = + SCC_RET_INSUFFICIENT_SPACE; + } + } + + /* If did not detect space error, do the decryption */ + if (return_code != SCC_RET_INSUFFICIENT_SPACE) { + return_code = + scc_decrypt(count_in_bytes, data_in, + scc_control, data_out, + check_mode == + SCC_VERIFY_MODE_CCITT_CRC, + count_out_bytes); + } + + } /* SCC_DECRYPT */ + + /* unlock the SCC */ + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + } /* else no initial error */ + + return return_code; +} /* scc_crypt */ + +/*****************************************************************************/ +/* fn scc_set_sw_alarm() */ +/*****************************************************************************/ +void scc_set_sw_alarm(void) +{ + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Update scc_availability based on current SMN status. This might + * perform callbacks. + */ + (void)scc_update_state(); + + /* if everything is OK, make it fail */ + if (scc_availability == SCC_STATUS_OK) { + + /* sound the alarm (and disable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_SET_SOFTWARE_ALARM); + + scc_availability = SCC_STATUS_FAILED; /* Remember what we've done */ + + /* In case SMN interrupt is not available, tell the world */ + scc_perform_callbacks(); + } + + return; +} /* scc_set_sw_alarm */ + +/*****************************************************************************/ +/* fn scc_monitor_security_failure() */ +/*****************************************************************************/ +scc_return_t scc_monitor_security_failure(void callback_func(void)) +{ + int i; + unsigned long irq_flags; /* for IRQ save/restore */ + scc_return_t return_status = SCC_RET_TOO_MANY_FUNCTIONS; + int function_stored = FALSE; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Acquire lock of callbacks table. Could be spin_lock_irq() if this + * routine were just called from base (not interrupt) level + */ + spin_lock_irqsave(&scc_callbacks_lock, irq_flags); + + /* Search through table looking for empty slot */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + if (scc_callbacks[i] == callback_func) { + if (function_stored) { + /* Saved duplicate earlier. Clear this later one. */ + scc_callbacks[i] = NULL; + } + /* Exactly one copy is now stored */ + return_status = SCC_RET_OK; + break; + } else if (scc_callbacks[i] == NULL && !function_stored) { + /* Found open slot. Save it and remember */ + scc_callbacks[i] = callback_func; + return_status = SCC_RET_OK; + function_stored = TRUE; + } + } + + /* Free the lock */ + spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags); + + return return_status; +} /* scc_monitor_security_failure */ + +/*****************************************************************************/ +/* fn scc_stop_monitoring_security_failure() */ +/*****************************************************************************/ +void scc_stop_monitoring_security_failure(void callback_func(void)) +{ + unsigned long irq_flags; /* for IRQ save/restore */ + int i; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Acquire lock of callbacks table. Could be spin_lock_irq() if this + * routine were just called from base (not interrupt) level + */ + spin_lock_irqsave(&scc_callbacks_lock, irq_flags); + + /* Search every entry of the table for this function */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + if (scc_callbacks[i] == callback_func) { + scc_callbacks[i] = NULL; /* found instance - clear it out */ + break; + } + } + + /* Free the lock */ + spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags); + + return; +} /* scc_stop_monitoring_security_failure */ + +/*****************************************************************************/ +/* fn scc_read_register() */ +/*****************************************************************************/ +scc_return_t scc_read_register(int register_offset, uint32_t * value) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t smn_status; + uint32_t scm_status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* First layer of protection -- completely unaccessible SCC */ + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + + /* Second layer -- that offset is valid */ + if (register_offset != SMN_BITBANK_DECREMENT && /* write only! */ + check_register_offset(register_offset) == SCC_RET_OK) { + + /* Get current status / update local state */ + smn_status = scc_update_state(); + scm_status = SCC_READ_REGISTER(SCM_STATUS); + + /* + * Third layer - verify that the register being requested is + * available in the current state of the SCC. + */ + if ((return_status = + check_register_accessible(register_offset, + smn_status, + scm_status)) == + SCC_RET_OK) { + *value = SCC_READ_REGISTER(register_offset); + } + } + } + + return return_status; +} /* scc_read_register */ + +/*****************************************************************************/ +/* fn scc_write_register() */ +/*****************************************************************************/ +scc_return_t scc_write_register(int register_offset, uint32_t value) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t smn_status; + uint32_t scm_status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* First layer of protection -- completely unaccessible SCC */ + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + + /* Second layer -- that offset is valid */ + if (!(register_offset == SCM_STATUS || /* These registers are */ + register_offset == SCM_CONFIGURATION || /* Read Only */ + register_offset == SMN_BIT_COUNT || + register_offset == SMN_TIMER) && + check_register_offset(register_offset) == SCC_RET_OK) { + + /* Get current status / update local state */ + smn_status = scc_update_state(); + scm_status = SCC_READ_REGISTER(SCM_STATUS); + + /* + * Third layer - verify that the register being requested is + * available in the current state of the SCC. + */ + if (check_register_accessible + (register_offset, smn_status, scm_status) == 0) { + SCC_WRITE_REGISTER(register_offset, value); + return_status = SCC_RET_OK; + } + } + } + + return return_status; +} /* scc_write_register() */ + +/****************************************************************************** + * + * Function Implementations - Internal + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn scc_irq() */ +/*****************************************************************************/ +/*! + * This is the interrupt handler for the SCC. + * + * This function checks the SMN Status register to see whether it + * generated the interrupt, then it checks the SCM Status register to + * see whether it needs attention. + * + * If an SMN Interrupt is active, then the SCC state set to failure, and + * #scc_perform_callbacks() is invoked to notify any interested parties. + * + * The SCM Interrupt should be masked, as this driver uses polling to determine + * when the SCM has completed a crypto or zeroing operation. Therefore, if the + * interrupt is active, the driver will just clear the interrupt and (re)mask. + * + */ +OS_DEV_ISR(scc_irq) +{ + uint32_t smn_status; + uint32_t scm_status; + int handled = 0; /* assume interrupt isn't from SMN */ +#if defined(USE_SMN_INTERRUPT) + int smn_irq = INT_SCC_SMN; /* SMN interrupt is on a line by itself */ +#elif defined (NO_SMN_INTERRUPT) + int smn_irq = -1; /* not wired to CPU at all */ +#else + int smn_irq = INT_SCC_SCM; /* SMN interrupt shares a line with SCM */ +#endif + + /* Update current state... This will perform callbacks... */ + smn_status = scc_update_state(); + + /* SMN is on its own interrupt line. Verify the IRQ was triggered + * before clearing the interrupt and marking it handled. */ + if ((os_dev_get_irq() == smn_irq) && + (smn_status & SMN_STATUS_SMN_STATUS_IRQ)) { + SCC_WRITE_REGISTER(SMN_COMMAND, SMN_COMMAND_CLEAR_INTERRUPT); + handled++; /* tell kernel that interrupt was handled */ + } + + /* Check on the health of the SCM */ + scm_status = SCC_READ_REGISTER(SCM_STATUS); + + /* The driver masks interrupts, so this should never happen. */ + if (os_dev_get_irq() == INT_SCC_SCM) { + /* but if it does, try to prevent it in the future */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + handled++; + } + + /* Any non-zero value of handled lets kernel know we got something */ + return IRQ_RETVAL(handled); +} + +/*****************************************************************************/ +/* fn scc_perform_callbacks() */ +/*****************************************************************************/ +/*! Perform callbacks registered by #scc_monitor_security_failure(). + * + * Make sure callbacks only happen once... Since there may be some reason why + * the interrupt isn't generated, this routine could be called from base(task) + * level. + * + * One at a time, go through #scc_callbacks[] and call any non-null pointers. + */ +static void scc_perform_callbacks(void) +{ + static int callbacks_performed = 0; + unsigned long irq_flags; /* for IRQ save/restore */ + int i; + + /* Acquire lock of callbacks table and callbacks_performed flag */ + spin_lock_irqsave(&scc_callbacks_lock, irq_flags); + + if (!callbacks_performed) { + callbacks_performed = 1; + + /* Loop over all of the entries in the table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + /* If not null, ... */ + if (scc_callbacks[i]) { + scc_callbacks[i] (); /* invoke the callback routine */ + } + } + } + + spin_unlock_irqrestore(&scc_callbacks_lock, irq_flags); + + return; +} + +/*****************************************************************************/ +/* fn copy_to_scc() */ +/*****************************************************************************/ +/*! + * Move data from possibly unaligned source and realign for SCC, possibly + * while calculating CRC. + * + * Multiple calls can be made to this routine (without intervening calls to + * #copy_from_scc(), as long as the sum total of bytes copied is a multiple of + * four (SCC native word size). + * + * @param[in] from Location in memory + * @param[out] to Location in SCC + * @param[in] count_bytes Number of bytes to copy + * @param[in,out] crc Pointer to CRC. Initial value must be + * #CRC_CCITT_START if this is the start of + * message. Output is the resulting (maybe + * partial) CRC. If NULL, no crc is calculated. + * + * @return Zero - success. Non-zero - SCM status bits defining failure. + */ +static uint32_t +copy_to_scc(const uint8_t * from, uint32_t to, unsigned long count_bytes, + uint16_t * crc) +{ + int i; + uint32_t scm_word; + uint16_t current_crc = 0; /* local copy for fast access */ + uint32_t status; + + pr_debug("SCC: copying %ld bytes to 0x%0x.\n", count_bytes, to); + + status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS; + if (status != 0) { + pr_debug + ("SCC copy_to_scc(): Error status detected (before copy):" + " %08x\n", status); + /* clear out errors left behind by somebody else */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status); + } + + if (crc) { + current_crc = *crc; + } + + /* Initialize value being built for SCM. If we are starting 'clean', + * set it to zero. Otherwise pick up partial value which had been saved + * earlier. */ + if (SCC_BYTE_OFFSET(to) == 0) { + scm_word = 0; + } else { + scm_word = SCC_READ_REGISTER(SCC_WORD_PTR(to)); /* recover */ + } + + /* Now build up SCM words and write them out when each is full */ + for (i = 0; i < count_bytes; i++) { + uint8_t byte = *from++; /* value from plaintext */ + +#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE) + scm_word = (scm_word << 8) | byte; /* add byte to SCM word */ +#else + scm_word = (byte << 24) | (scm_word >> 8); +#endif + /* now calculate CCITT CRC */ + if (crc) { + CALC_CRC(byte, current_crc); + } + + to++; /* bump location in SCM */ + + /* check for full word */ + if (SCC_BYTE_OFFSET(to) == 0) { + SCC_WRITE_REGISTER((uint32_t) (to - 4), scm_word); /* write it out */ + } + } + + /* If at partial word after previous loop, save it in SCM memory for + next time. */ + if (SCC_BYTE_OFFSET(to) != 0) { + SCC_WRITE_REGISTER(SCC_WORD_PTR(to), scm_word); /* save */ + } + + /* Copy CRC back */ + if (crc) { + *crc = current_crc; + } + + status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS; + if (status != 0) { + pr_debug("SCC copy_to_scc(): Error status detected: %08x\n", + status); + /* Clear any/all bits. */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status); + } + return status; +} + +/*****************************************************************************/ +/* fn copy_from_scc() */ +/*****************************************************************************/ +/*! + * Move data from aligned 32-bit source and place in (possibly unaligned) + * target, and maybe calculate CRC at the same time. + * + * Multiple calls can be made to this routine (without intervening calls to + * #copy_to_scc(), as long as the sum total of bytes copied is be a multiple + * of four. + * + * @param[in] from Location in SCC + * @param[out] to Location in memory + * @param[in] count_bytes Number of bytes to copy + * @param[in,out] crc Pointer to CRC. Initial value must be + * #CRC_CCITT_START if this is the start of + * message. Output is the resulting (maybe + * partial) CRC. If NULL, crc is not calculated. + * + * @return Zero - success. Non-zero - SCM status bits defining failure. + */ +static uint32_t +copy_from_scc(const uint32_t from, uint8_t * to, unsigned long count_bytes, + uint16_t * crc) +{ + uint32_t running_from = from; + uint32_t scm_word; + uint16_t current_crc = 0; /* local copy for fast access */ + uint32_t status; + pr_debug("SCC: copying %ld bytes from 0x%x.\n", count_bytes, from); + status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS; + if (status != 0) { + pr_debug + ("SCC copy_from_scc(): Error status detected (before copy):" + " %08x\n", status); + /* clear out errors left behind by somebody else */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status); + } + + if (crc) { + current_crc = *crc; + } + + /* Read word which is sitting in SCM memory. Ignore byte offset */ + scm_word = SCC_READ_REGISTER(SCC_WORD_PTR(running_from)); + + /* If necessary, move the 'first' byte into place */ + if (SCC_BYTE_OFFSET(running_from) != 0) { +#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE) + scm_word <<= 8 * SCC_BYTE_OFFSET(running_from); +#else + scm_word >>= 8 * SCC_BYTE_OFFSET(running_from); +#endif + } + + /* Now build up SCM words and write them out when each is full */ + while (count_bytes--) { + uint8_t byte; /* value from plaintext */ + +#if defined(__BIG_ENDIAN) || defined(FSL_HAVE_DRYICE) + byte = (scm_word & 0xff000000) >> 24; /* pull byte out of SCM word */ + scm_word <<= 8; /* shift over to remove the just-pulled byte */ +#else + byte = (scm_word & 0xff); + scm_word >>= 8; /* shift over to remove the just-pulled byte */ +#endif + *to++ = byte; /* send byte to memory */ + + /* now calculate CRC */ + if (crc) { + CALC_CRC(byte, current_crc); + } + + running_from++; + /* check for empty word */ + if (count_bytes && SCC_BYTE_OFFSET(running_from) == 0) { + /* read one in */ + scm_word = SCC_READ_REGISTER((uint32_t) running_from); + } + } + + if (crc) { + *crc = current_crc; + } + + status = SCC_READ_REGISTER(SCM_ERROR_STATUS) & SCM_ACCESS_ERRORS; + if (status != 0) { + pr_debug("SCC copy_from_scc(): Error status detected: %08x\n", + status); + /* Clear any/all bits. */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, status); + } + + return status; +} + +/*****************************************************************************/ +/* fn scc_strip_padding() */ +/*****************************************************************************/ +/*! + * Remove padding from plaintext. Search backwards for #SCC_DRIVER_PAD_CHAR, + * verifying that each byte passed over is zero (0). Maximum number of bytes + * to examine is 8. + * + * @param[in] from Pointer to byte after end of message + * @param[out] count_bytes_stripped Number of padding bytes removed by this + * function. + * + * @return #SCC_RET_OK if all goes, well, #SCC_RET_FAIL if padding was + * not present. +*/ +static scc_return_t +scc_strip_padding(uint8_t * from, unsigned *count_bytes_stripped) +{ + int i = SCC_BLOCK_SIZE_BYTES(); + scc_return_t return_code = SCC_RET_VERIFICATION_FAILED; + + /* + * Search backwards looking for the magic marker. If it isn't found, + * make sure that a 0 byte is there in its place. Stop after the maximum + * amount of padding (8 bytes) has been searched); + */ + while (i-- > 0) { + if (*--from == SCC_DRIVER_PAD_CHAR) { + *count_bytes_stripped = SCC_BLOCK_SIZE_BYTES() - i; + return_code = SCC_RET_OK; + break; + } else if (*from != 0) { /* if not marker, check for 0 */ + pr_debug("SCC: Found non-zero interim pad: 0x%x\n", + *from); + break; + } + } + + return return_code; +} + +/*****************************************************************************/ +/* fn scc_update_state() */ +/*****************************************************************************/ +/*! + * Make certain SCC is still running. + * + * Side effect is to update #scc_availability and, if the state goes to failed, + * run #scc_perform_callbacks(). + * + * (If #SCC_BRINGUP is defined, bring SCC to secure state if it is found to be + * in health check state) + * + * @return Current value of #SMN_STATUS register. + */ +static uint32_t scc_update_state(void) +{ + uint32_t smn_status_register = SMN_STATE_FAIL; + int smn_state; + + /* if FAIL or UNIMPLEMENTED, don't bother */ + if (scc_availability == SCC_STATUS_CHECKING || + scc_availability == SCC_STATUS_OK) { + + smn_status_register = SCC_READ_REGISTER(SMN_STATUS); + smn_state = smn_status_register & SMN_STATUS_STATE_MASK; + +#ifdef SCC_BRINGUP + /* If in Health Check while booting, try to 'bringup' to Secure mode */ + if (scc_availability == SCC_STATUS_CHECKING && + smn_state == SMN_STATE_HEALTH_CHECK) { + /* Code up a simple algorithm for the ASC */ + SCC_WRITE_REGISTER(SMN_SEQUENCE_START, 0xaaaa); + SCC_WRITE_REGISTER(SMN_SEQUENCE_END, 0x5555); + SCC_WRITE_REGISTER(SMN_SEQUENCE_CHECK, 0x5555); + /* State should be SECURE now */ + smn_status_register = SCC_READ_REGISTER(SMN_STATUS); + smn_state = smn_status_register & SMN_STATUS_STATE_MASK; + } +#endif + + /* + * State should be SECURE or NON_SECURE for operation of the part. If + * FAIL, mark failed (i.e. limited access to registers). Any other + * state, mark unimplemented, as the SCC is unuseable. + */ + if (smn_state == SMN_STATE_SECURE + || smn_state == SMN_STATE_NON_SECURE) { + /* Healthy */ + scc_availability = SCC_STATUS_OK; + } else if (smn_state == SMN_STATE_FAIL) { + scc_availability = SCC_STATUS_FAILED; /* uh oh - unhealthy */ + scc_perform_callbacks(); + os_printk(KERN_ERR "SCC: SCC went into FAILED mode\n"); + } else { + /* START, ZEROIZE RAM, HEALTH CHECK, or unknown */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; /* unuseable */ + os_printk(KERN_ERR "SCC: SCC declared UNIMPLEMENTED\n"); + } + } + /* if availability is initial or ok */ + return smn_status_register; +} + +/*****************************************************************************/ +/* fn scc_init_ccitt_crc() */ +/*****************************************************************************/ +/*! + * Populate the partial CRC lookup table. + * + * @return none + * + */ +static void scc_init_ccitt_crc(void) +{ + int dividend; /* index for lookup table */ + uint16_t remainder; /* partial value for a given dividend */ + int bit; /* index into bits of a byte */ + + /* + * Compute the remainder of each possible dividend. + */ + for (dividend = 0; dividend < 256; ++dividend) { + /* + * Start with the dividend followed by zeros. + */ + remainder = dividend << (8); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) { + /* + * Try to divide the current data bit. + */ + if (remainder & 0x8000) { + remainder = (remainder << 1) ^ CRC_POLYNOMIAL; + } else { + remainder = (remainder << 1); + } + } + + /* + * Store the result into the table. + */ + scc_crc_lookup_table[dividend] = remainder; + } + +} /* scc_init_ccitt_crc() */ + +/*****************************************************************************/ +/* fn grab_config_values() */ +/*****************************************************************************/ +/*! + * grab_config_values() will read the SCM Configuration and SMN Status + * registers and store away version and size information for later use. + * + * @return The current value of the SMN Status register. + */ +static uint32_t scc_grab_config_values(void) +{ + uint32_t config_register; + uint32_t smn_status_register = SMN_STATE_FAIL; + + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + /* access the SCC - these are 'safe' registers */ + config_register = SCC_READ_REGISTER(SCM_CONFIGURATION); + pr_debug("SCC Driver: SCM config is 0x%08x\n", config_register); + + /* Get SMN status and update scc_availability */ + smn_status_register = scc_update_state(); + pr_debug("SCC Driver: SMN status is 0x%08x\n", + smn_status_register); + + /* save sizes and versions information for later use */ + scc_configuration.block_size_bytes = (config_register & + SCM_CFG_BLOCK_SIZE_MASK) + >> SCM_CFG_BLOCK_SIZE_SHIFT; + + scc_configuration.red_ram_size_blocks = (config_register & + SCM_CFG_RED_SIZE_MASK) + >> SCM_CFG_RED_SIZE_SHIFT; + + scc_configuration.black_ram_size_blocks = (config_register & + SCM_CFG_BLACK_SIZE_MASK) + >> SCM_CFG_BLACK_SIZE_SHIFT; + + scc_configuration.scm_version = (config_register + & SCM_CFG_VERSION_ID_MASK) + >> SCM_CFG_VERSION_ID_SHIFT; + + scc_configuration.smn_version = (smn_status_register & + SMN_STATUS_VERSION_ID_MASK) + >> SMN_STATUS_VERSION_ID_SHIFT; + + if (scc_configuration.scm_version != SCM_VERSION_1) { + scc_availability = SCC_STATUS_UNIMPLEMENTED; /* Unknown version */ + } + + scc_memory_size_bytes = (SCC_BLOCK_SIZE_BYTES() * + scc_configuration. + black_ram_size_blocks) + - SCM_NON_RESERVED_OFFSET; + + /* This last is for driver consumption only */ + scm_highest_memory_address = SCM_BLACK_MEMORY + + (SCC_BLOCK_SIZE_BYTES() * + scc_configuration.black_ram_size_blocks); + } + + return smn_status_register; +} /* grab_config_values */ + +/*****************************************************************************/ +/* fn setup_interrupt_handling() */ +/*****************************************************************************/ +/*! + * Register the SCM and SMN interrupt handlers. + * + * Called from #scc_init() + * + * @return 0 on success + */ +static int setup_interrupt_handling(void) +{ + int smn_error_code = -1; + int scm_error_code = -1; + + /* Disnable SCM interrupts */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + +#ifdef USE_SMN_INTERRUPT + /* Install interrupt service routine for SMN. */ + smn_error_code = os_register_interrupt(SCC_DRIVER_NAME, + INT_SCC_SMN, scc_irq); + if (smn_error_code != 0) { + os_printk + ("SCC Driver: Error installing SMN Interrupt Handler: %d\n", + smn_error_code); + } else { + smn_irq_set = 1; /* remember this for cleanup */ + /* Enable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND, + SMN_COMMAND_CLEAR_INTERRUPT | + SMN_COMMAND_ENABLE_INTERRUPT); + } +#else + smn_error_code = 0; /* no problems... will handle later */ +#endif + + /* + * Install interrupt service routine for SCM (or both together). + */ + scm_error_code = os_register_interrupt(SCC_DRIVER_NAME, + INT_SCC_SCM, scc_irq); + if (scm_error_code != 0) { +#ifndef MXC + os_printk + ("SCC Driver: Error installing SCM Interrupt Handler: %d\n", + scm_error_code); +#else + os_printk + ("SCC Driver: Error installing SCC Interrupt Handler: %d\n", + scm_error_code); +#endif + } else { + scm_irq_set = 1; /* remember this for cleanup */ +#if defined(USE_SMN_INTERRUPT) && !defined(NO_SMN_INTERRUPT) + /* Enable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND, + SMN_COMMAND_CLEAR_INTERRUPT | + SMN_COMMAND_ENABLE_INTERRUPT); +#endif + } + + /* Return an error if one was encountered */ + return scm_error_code ? scm_error_code : smn_error_code; +} /* setup_interrupt_handling */ + +/*****************************************************************************/ +/* fn scc_do_crypto() */ +/*****************************************************************************/ +/*! Have the SCM perform the crypto function. + * + * Set up length register, and the store @c scm_control into control register + * to kick off the operation. Wait for completion, gather status, clear + * interrupt / status. + * + * @param byte_count number of bytes to perform in this operation + * @param scm_control Bit values to be set in @c SCM_CONTROL register + * + * @return 0 on success, value of #SCM_ERROR_STATUS on failure + */ +static uint32_t scc_do_crypto(int byte_count, uint32_t scm_control) +{ + int block_count = byte_count / SCC_BLOCK_SIZE_BYTES(); + uint32_t crypto_status; + + /* clear any outstanding flags */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + + /* In length register, 0 means 1, etc. */ + SCC_WRITE_REGISTER(SCM_LENGTH, block_count - 1); + + /* set modes and kick off the operation */ + SCC_WRITE_REGISTER(SCM_CONTROL, scm_control); + + scc_wait_completion(); + + /* Mask for done and error bits */ + crypto_status = SCC_READ_REGISTER(SCM_STATUS) + & (SCM_STATUS_CIPHERING_DONE + | SCM_STATUS_LENGTH_ERROR | SCM_STATUS_INTERNAL_ERROR); + + /* Only done bit should be on */ + if (crypto_status != SCM_STATUS_CIPHERING_DONE) { + /* Replace with error status instead */ + crypto_status = SCC_READ_REGISTER(SCM_ERROR_STATUS); + pr_debug("SCM Failure: 0x%x\n", crypto_status); + if (crypto_status == 0) { + /* That came up 0. Turn on arbitrary bit to signal error. */ + crypto_status = SCM_ERR_INTERNAL_ERROR; + } + } else { + crypto_status = 0; + } + + pr_debug("SCC: Done waiting.\n"); + + /* Clear out any status. */ + SCC_WRITE_REGISTER(SCM_INTERRUPT_CTRL, + SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT + | SCM_INTERRUPT_CTRL_MASK_INTERRUPTS); + + /* And clear any error status */ + SCC_WRITE_REGISTER(SCM_ERROR_STATUS, 0); + + return crypto_status; +} + +/*****************************************************************************/ +/* fn scc_encrypt() */ +/*****************************************************************************/ +/*! + * Perform an encryption on the input. If @c verify_crc is true, a CRC must be + * calculated on the plaintext, and appended, with padding, before computing + * the ciphertext. + * + * @param[in] count_in_bytes Count of bytes of plaintext + * @param[in] data_in Pointer to the plaintext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing ciphertext + * @param[in] add_crc Flag for computing CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + */ +static scc_return_t +scc_encrypt(uint32_t count_in_bytes, const uint8_t * data_in, + uint32_t scm_control, + uint8_t * data_out, int add_crc, unsigned long *count_out_bytes) + +{ + scc_return_t return_code = SCC_RET_FAIL; /* initialised for failure */ + uint32_t input_bytes_left = count_in_bytes; /* local copy */ + uint32_t output_bytes_copied = 0; /* running total */ + uint32_t bytes_to_process; /* multi-purpose byte counter */ + uint16_t crc = CRC_CCITT_START; /* running CRC value */ + crc_t *crc_ptr = NULL; /* Reset if CRC required */ + /* byte address into SCM RAM */ + uint32_t scm_location = SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET; + /* free RED RAM */ + uint32_t scm_bytes_remaining = scc_memory_size_bytes; + /* CRC+padding holder */ + uint8_t padding_buffer[PADDING_BUFFER_MAX_BYTES]; + unsigned padding_byte_count = 0; /* Reset if padding required */ + uint32_t scm_error_status = 0; /* No known SCM error initially */ + uint32_t i; /* Counter for clear data loop */ + uint32_t dirty_bytes; /* Number of bytes of memory used + temporarily during encryption, + which need to be wiped after + completion of the operation. */ + + /* Set location of CRC and prepare padding bytes if required */ + if (add_crc != 0) { + crc_ptr = &crc; + padding_byte_count = SCC_BLOCK_SIZE_BYTES() + - (count_in_bytes + + CRC_SIZE_BYTES) % SCC_BLOCK_SIZE_BYTES(); + memcpy(padding_buffer + CRC_SIZE_BYTES, scc_block_padding, + padding_byte_count); + } + + /* Process remaining input or padding data */ + while (input_bytes_left > 0) { + + /* Determine how much work to do this pass */ + bytes_to_process = (input_bytes_left > scm_bytes_remaining) ? + scm_bytes_remaining : input_bytes_left; + + /* Copy plaintext into SCM RAM, calculating CRC if required */ + copy_to_scc(data_in, scm_location, bytes_to_process, crc_ptr); + + /* Adjust pointers & counters */ + input_bytes_left -= bytes_to_process; + data_in += bytes_to_process; + scm_location += bytes_to_process; + scm_bytes_remaining -= bytes_to_process; + + /* Add CRC and padding after the last byte is copied if required */ + if ((input_bytes_left == 0) && (crc_ptr != NULL)) { + + /* Copy CRC into padding buffer MSB first */ + padding_buffer[0] = (crc >> 8) & 0xFF; + padding_buffer[1] = crc & 0xFF; + + /* Reset pointers and counter */ + data_in = padding_buffer; + input_bytes_left = CRC_SIZE_BYTES + padding_byte_count; + crc_ptr = NULL; /* CRC no longer required */ + + /* Go round loop again to copy CRC and padding to SCM */ + continue; + } + + /* if no input and crc_ptr */ + /* Now have block-sized plaintext in SCM to encrypt */ + /* Encrypt plaintext; exit loop on error */ + bytes_to_process = scm_location - + (SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET); + + if (output_bytes_copied + bytes_to_process > *count_out_bytes) { + return_code = SCC_RET_INSUFFICIENT_SPACE; + scm_error_status = -1; /* error signal */ + pr_debug + ("SCC: too many ciphertext bytes for space available\n"); + break; + } + pr_debug("SCC: Starting encryption. %x for %d bytes (%p/%p)\n", + scm_control, bytes_to_process, + (void *)SCC_READ_REGISTER(SCM_RED_START), + (void *)SCC_READ_REGISTER(SCM_BLACK_START)); + scm_error_status = scc_do_crypto(bytes_to_process, scm_control); + if (scm_error_status != 0) { + break; + } + + /* Copy out ciphertext */ + copy_from_scc(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET, + data_out, bytes_to_process, NULL); + + /* Adjust pointers and counters for next loop */ + output_bytes_copied += bytes_to_process; + data_out += bytes_to_process; + scm_location = SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET; + scm_bytes_remaining = scc_memory_size_bytes; + + } /* input_bytes_left > 0 */ + /* Clear all red and black memory used during ephemeral encryption */ + dirty_bytes = (count_in_bytes > scc_memory_size_bytes) ? + scc_memory_size_bytes : count_in_bytes; + + for (i = 0; i < dirty_bytes; i += 4) { + SCC_WRITE_REGISTER(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET + i, + 0); + SCC_WRITE_REGISTER(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET + + i, 0); + } + + /* If no SCM error, set OK status and save ouput byte count */ + if (scm_error_status == 0) { + return_code = SCC_RET_OK; + *count_out_bytes = output_bytes_copied; + } + + return return_code; +} /* scc_encrypt */ + +/*****************************************************************************/ +/* fn scc_decrypt() */ +/*****************************************************************************/ +/*! + * Perform a decryption on the input. If @c verify_crc is true, the last block + * (maybe the two last blocks) is special - it should contain a CRC and + * padding. These must be stripped and verified. + * + * @param[in] count_in_bytes Count of bytes of ciphertext + * @param[in] data_in Pointer to the ciphertext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing plaintext + * @param[in] verify_crc Flag for running CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + + */ +static scc_return_t +scc_decrypt(uint32_t count_in_bytes, const uint8_t * data_in, + uint32_t scm_control, + uint8_t * data_out, int verify_crc, unsigned long *count_out_bytes) +{ + scc_return_t return_code = SCC_RET_FAIL; + uint32_t bytes_left = count_in_bytes; /* local copy */ + uint32_t bytes_copied = 0; /* running total of bytes going to user */ + uint32_t bytes_to_copy = 0; /* Number in this encryption 'chunk' */ + uint16_t crc = CRC_CCITT_START; /* running CRC value */ + /* next target for ctext */ + uint32_t scm_location = SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET; + unsigned padding_byte_count; /* number of bytes of padding stripped */ + uint8_t last_two_blocks[2 * SCC_BLOCK_SIZE_BYTES()]; /* temp */ + uint32_t scm_error_status = 0; /* register value */ + uint32_t i; /* Counter for clear data loop */ + uint32_t dirty_bytes; /* Number of bytes of memory used + temporarily during decryption, + which need to be wiped after + completion of the operation. */ + + scm_control |= SCM_DECRYPT_MODE; + + if (verify_crc) { + /* Save last two blocks (if there are at least two) of ciphertext for + special treatment. */ + bytes_left -= SCC_BLOCK_SIZE_BYTES(); + if (bytes_left >= SCC_BLOCK_SIZE_BYTES()) { + bytes_left -= SCC_BLOCK_SIZE_BYTES(); + } + } + + /* Copy ciphertext into SCM BLACK memory */ + while (bytes_left && scm_error_status == 0) { + + /* Determine how much work to do this pass */ + if (bytes_left > (scc_memory_size_bytes)) { + bytes_to_copy = scc_memory_size_bytes; + } else { + bytes_to_copy = bytes_left; + } + + if (bytes_copied + bytes_to_copy > *count_out_bytes) { + scm_error_status = -1; + break; + } + copy_to_scc(data_in, scm_location, bytes_to_copy, NULL); + data_in += bytes_to_copy; /* move pointer */ + + pr_debug("SCC: Starting decryption of %d bytes.\n", + bytes_to_copy); + + /* Do the work, wait for completion */ + scm_error_status = scc_do_crypto(bytes_to_copy, scm_control); + + copy_from_scc(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET, + data_out, bytes_to_copy, &crc); + bytes_copied += bytes_to_copy; + data_out += bytes_to_copy; + scm_location = SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET; + + /* Do housekeeping */ + bytes_left -= bytes_to_copy; + + } /* while bytes_left */ + + /* At this point, either the process is finished, or this is verify mode */ + + if (scm_error_status == 0) { + if (!verify_crc) { + *count_out_bytes = bytes_copied; + return_code = SCC_RET_OK; + } else { + /* Verify mode. There are one or two blocks of unprocessed + * ciphertext sitting at data_in. They need to be moved to the + * SCM, decrypted, searched to remove padding, then the plaintext + * copied back to the user (while calculating CRC, of course). + */ + + /* Calculate ciphertext still left */ + bytes_to_copy = count_in_bytes - bytes_copied; + + copy_to_scc(data_in, scm_location, bytes_to_copy, NULL); + data_in += bytes_to_copy; /* move pointer */ + + pr_debug("SCC: Finishing decryption (%d bytes).\n", + bytes_to_copy); + + /* Do the work, wait for completion */ + scm_error_status = + scc_do_crypto(bytes_to_copy, scm_control); + + if (scm_error_status == 0) { + /* Copy decrypted data back from SCM RED memory */ + copy_from_scc(SCM_RED_MEMORY + + SCM_NON_RESERVED_OFFSET, + last_two_blocks, bytes_to_copy, + NULL); + + /* (Plaintext) + crc + padding should be in temp buffer */ + if (scc_strip_padding + (last_two_blocks + bytes_to_copy, + &padding_byte_count) == SCC_RET_OK) { + bytes_to_copy -= + padding_byte_count + CRC_SIZE_BYTES; + + /* verify enough space in user buffer */ + if (bytes_copied + bytes_to_copy <= + *count_out_bytes) { + int i = 0; + + /* Move out last plaintext and calc CRC */ + while (i < bytes_to_copy) { + CALC_CRC(last_two_blocks + [i], crc); + *data_out++ = + last_two_blocks + [i++]; + bytes_copied++; + } + + /* Verify the CRC by running over itself */ + CALC_CRC(last_two_blocks + [bytes_to_copy], crc); + CALC_CRC(last_two_blocks + [bytes_to_copy + 1], + crc); + if (crc == 0) { + /* Just fine ! */ + *count_out_bytes = + bytes_copied; + return_code = + SCC_RET_OK; + } else { + return_code = + SCC_RET_VERIFICATION_FAILED; + pr_debug + ("SCC: CRC values are %04x, %02x%02x\n", + crc, + last_two_blocks + [bytes_to_copy], + last_two_blocks + [bytes_to_copy + + 1]); + } + } /* if space available */ + } /* if scc_strip_padding... */ + else { + /* bad padding means bad verification */ + return_code = + SCC_RET_VERIFICATION_FAILED; + } + } + /* scm_error_status == 0 */ + } /* verify_crc */ + } + + /* scm_error_status == 0 */ + /* Clear all red and black memory used during ephemeral decryption */ + dirty_bytes = (count_in_bytes > scc_memory_size_bytes) ? + scc_memory_size_bytes : count_in_bytes; + + for (i = 0; i < dirty_bytes; i += 4) { + SCC_WRITE_REGISTER(SCM_RED_MEMORY + SCM_NON_RESERVED_OFFSET + i, + 0); + SCC_WRITE_REGISTER(SCM_BLACK_MEMORY + SCM_NON_RESERVED_OFFSET + + i, 0); + } + return return_code; +} /* scc_decrypt */ + +/*****************************************************************************/ +/* fn scc_alloc_slot() */ +/*****************************************************************************/ +/*! + * Allocate a key slot to fit the requested size. + * + * @param value_size_bytes Size of the key or other secure data + * @param owner_id Value to tie owner to slot + * @param[out] slot Handle to access or deallocate slot + * + * @return SCC_RET_OK on success, SCC_RET_INSUFFICIENT_SPACE if not slots of + * requested size are available. + */ +scc_return_t +scc_alloc_slot(uint32_t value_size_bytes, uint64_t owner_id, uint32_t * slot) +{ + scc_return_t status = SCC_RET_FAIL; + unsigned long irq_flags; + + if (scc_availability != SCC_STATUS_OK) { + goto out; + } + /* ACQUIRE LOCK to prevent others from using SCC crypto */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + pr_debug("SCC: Allocating %d-byte slot for 0x%Lx\n", + value_size_bytes, owner_id); + + if ((value_size_bytes != 0) && (value_size_bytes <= SCC_MAX_KEY_SIZE)) { + int i; + + for (i = 0; i < SCC_KEY_SLOTS; i++) { + if (scc_key_info[i].status == 0) { + scc_key_info[i].owner_id = owner_id; + scc_key_info[i].length = value_size_bytes; + scc_key_info[i].status = 1; /* assigned! */ + *slot = i; + status = SCC_RET_OK; + break; /* exit 'for' loop */ + } + } + + if (status != SCC_RET_OK) { + status = SCC_RET_INSUFFICIENT_SPACE; + } else { + pr_debug("SCC: Allocated slot %d (0x%Lx)\n", i, + owner_id); + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + out: + return status; +} + +/*****************************************************************************/ +/* fn verify_slot_access() */ +/*****************************************************************************/ +inline static scc_return_t +verify_slot_access(uint64_t owner_id, uint32_t slot, uint32_t access_len) +{ + scc_return_t status = SCC_RET_FAIL; + if (scc_availability != SCC_STATUS_OK) { + goto out; + } + + if ((slot < SCC_KEY_SLOTS) && scc_key_info[slot].status + && (scc_key_info[slot].owner_id == owner_id) + && (access_len <= SCC_KEY_SLOT_SIZE)) { + status = SCC_RET_OK; + pr_debug("SCC: Verify on slot %d succeeded\n", slot); + } else { + if (slot >= SCC_KEY_SLOTS) { + pr_debug("SCC: Verify on bad slot (%d) failed\n", slot); + } else if (scc_key_info[slot].status) { + pr_debug("SCC: Verify on slot %d failed (%Lx) \n", slot, + owner_id); + } else { + pr_debug + ("SCC: Verify on slot %d failed: not allocated\n", + slot); + } + } + + out: + return status; +} + +scc_return_t +scc_verify_slot_access(uint64_t owner_id, uint32_t slot, uint32_t access_len) +{ + return verify_slot_access(owner_id, slot, access_len); +} + +/*****************************************************************************/ +/* fn scc_dealloc_slot() */ +/*****************************************************************************/ +scc_return_t scc_dealloc_slot(uint64_t owner_id, uint32_t slot) +{ + scc_return_t status; + unsigned long irq_flags; + int i; + + /* ACQUIRE LOCK to prevent others from using SCC crypto */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, 0); + + if (status == SCC_RET_OK) { + scc_key_info[slot].owner_id = 0; + scc_key_info[slot].status = 0; /* unassign */ + + /* clear old info */ + for (i = 0; i < SCC_KEY_SLOT_SIZE; i += 4) { + SCC_WRITE_REGISTER(SCM_RED_MEMORY + + scc_key_info[slot].offset + i, 0); + SCC_WRITE_REGISTER(SCM_BLACK_MEMORY + + scc_key_info[slot].offset + i, 0); + } + pr_debug("SCC: Deallocated slot %d\n", slot); + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} + +/*****************************************************************************/ +/* fn scc_load_slot() */ +/*****************************************************************************/ +/*! + * Load a value into a slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param key_data Data to load into the slot + * @param key_length Length, in bytes, of @c key_data to copy to SCC. + * + * @return SCC_RET_OK on success. SCC_RET_FAIL will be returned if slot + * specified cannot be accessed for any reason, or SCC_RET_INSUFFICIENT_SPACE + * if @c key_length exceeds the size of the slot. + */ +scc_return_t +scc_load_slot(uint64_t owner_id, uint32_t slot, const uint8_t * key_data, + uint32_t key_length) +{ + scc_return_t status; + unsigned long irq_flags; + + /* ACQUIRE LOCK to prevent others from using SCC crypto */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, key_length); + if ((status == SCC_RET_OK) && (key_data != NULL)) { + status = SCC_RET_FAIL; /* reset expectations */ + + if (key_length > SCC_KEY_SLOT_SIZE) { + pr_debug + ("SCC: scc_load_slot() rejecting key of %d bytes.\n", + key_length); + status = SCC_RET_INSUFFICIENT_SPACE; + } else { + if (copy_to_scc(key_data, + SCM_RED_MEMORY + + scc_key_info[slot].offset, key_length, + NULL)) { + pr_debug("SCC: RED copy_to_scc() failed for" + " scc_load_slot()\n"); + } else { + if ((key_length % 4) != 0) { + uint32_t zeros = 0; + + /* zero-pad to get remainder bytes in correct place */ + copy_to_scc((uint8_t *) & zeros, + SCM_RED_MEMORY + + + scc_key_info[slot].offset + + key_length, + 4 - (key_length % 4), NULL); + } + status = SCC_RET_OK; + } + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} /* scc_load_slot */ + +scc_return_t +scc_read_slot(uint64_t owner_id, uint32_t slot, uint32_t key_length, + uint8_t * key_data) +{ + scc_return_t status; + unsigned long irq_flags; + + /* ACQUIRE LOCK to prevent others from using SCC crypto */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, key_length); + if ((status == SCC_RET_OK) && (key_data != NULL)) { + status = SCC_RET_FAIL; /* reset expectations */ + + if (key_length > SCC_KEY_SLOT_SIZE) { + pr_debug + ("SCC: scc_read_slot() rejecting key of %d bytes.\n", + key_length); + status = SCC_RET_INSUFFICIENT_SPACE; + } else { + if (copy_from_scc + (SCM_RED_MEMORY + scc_key_info[slot].offset, + key_data, key_length, NULL)) { + pr_debug("SCC: RED copy_from_scc() failed for" + " scc_read_slot()\n"); + } else { + status = SCC_RET_OK; + } + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} /* scc_read_slot */ + +/*****************************************************************************/ +/* fn scc_encrypt_slot() */ +/*****************************************************************************/ +/*! + * Encrypt the key data stored in a slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param length Length, in bytes, of @c black_data + * @param black_data Location to store result of encrypting RED data in slot + * + * @return SCC_RET_OK on success, SCC_RET_FAIL if slot specified cannot be + * accessed for any reason. + */ +scc_return_t scc_encrypt_slot(uint64_t owner_id, uint32_t slot, + uint32_t length, uint8_t * black_data) +{ + unsigned long irq_flags; + scc_return_t status; + uint32_t crypto_status; + uint32_t slot_offset = + scc_key_info[slot].offset / SCC_BLOCK_SIZE_BYTES(); + + /* ACQUIRE LOCK to prevent others from using crypto or releasing slot */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, length); + if (status == SCC_RET_OK) { + SCC_WRITE_REGISTER(SCM_BLACK_START, slot_offset); + SCC_WRITE_REGISTER(SCM_RED_START, slot_offset); + + /* Use OwnerID as CBC IV to tie Owner to data */ + SCC_WRITE_REGISTER(SCM_INIT_VECTOR_0, *(uint32_t *) & owner_id); + SCC_WRITE_REGISTER(SCM_INIT_VECTOR_1, + *(((uint32_t *) & owner_id) + 1)); + + /* Set modes and kick off the encryption */ + crypto_status = scc_do_crypto(length, + SCM_CONTROL_START_CIPHER | + SCM_CBC_MODE); + + if (crypto_status != 0) { + pr_debug("SCM encrypt red crypto failure: 0x%x\n", + crypto_status); + } else { + + /* Give blob back to caller */ + if (!copy_from_scc + (SCM_BLACK_MEMORY + scc_key_info[slot].offset, + black_data, length, NULL)) { + status = SCC_RET_OK; + pr_debug("SCC: Encrypted slot %d\n", slot); + } + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} + +/*****************************************************************************/ +/* fn scc_decrypt_slot() */ +/*****************************************************************************/ +/*! + * Decrypt some black data and leave result in the slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param length Length, in bytes, of @c black_data + * @param black_data Location of data to dencrypt and store in slot + * + * @return SCC_RET_OK on success, SCC_RET_FAIL if slot specified cannot be + * accessed for any reason. + */ +scc_return_t scc_decrypt_slot(uint64_t owner_id, uint32_t slot, + uint32_t length, const uint8_t * black_data) +{ + unsigned long irq_flags; + scc_return_t status; + uint32_t crypto_status; + uint32_t slot_offset = + scc_key_info[slot].offset / SCC_BLOCK_SIZE_BYTES(); + + /* ACQUIRE LOCK to prevent others from using crypto or releasing slot */ + spin_lock_irqsave(&scc_crypto_lock, irq_flags); + + status = verify_slot_access(owner_id, slot, length); + if (status == SCC_RET_OK) { + status = SCC_RET_FAIL; /* reset expectations */ + + /* Place black key in to BLACK RAM and set up the SCC */ + copy_to_scc(black_data, + SCM_BLACK_MEMORY + scc_key_info[slot].offset, + length, NULL); + + SCC_WRITE_REGISTER(SCM_BLACK_START, slot_offset); + SCC_WRITE_REGISTER(SCM_RED_START, slot_offset); + + /* Use OwnerID as CBC IV to tie Owner to data */ + SCC_WRITE_REGISTER(SCM_INIT_VECTOR_0, *(uint32_t *) & owner_id); + SCC_WRITE_REGISTER(SCM_INIT_VECTOR_1, + *(((uint32_t *) & owner_id) + 1)); + + /* Set modes and kick off the decryption */ + crypto_status = scc_do_crypto(length, + SCM_CONTROL_START_CIPHER + | SCM_CBC_MODE | + SCM_DECRYPT_MODE); + + if (crypto_status != 0) { + pr_debug("SCM decrypt black crypto failure: 0x%x\n", + crypto_status); + } else { + status = SCC_RET_OK; + } + } + + spin_unlock_irqrestore(&scc_crypto_lock, irq_flags); + + return status; +} + +/*****************************************************************************/ +/* fn scc_get_slot_info() */ +/*****************************************************************************/ +/*! + * Determine address and value length for a give slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param address Location to store kernel address of slot data + * @param value_size_bytes Location to store allocated length of data in slot. + * May be NULL if value is not needed by caller. + * @param slot_size_bytes Location to store max length data in slot + * May be NULL if value is not needed by caller. + * + * @return SCC_RET_OK or error indication + */ +scc_return_t +scc_get_slot_info(uint64_t owner_id, uint32_t slot, uint32_t * address, + uint32_t * value_size_bytes, uint32_t * slot_size_bytes) +{ + scc_return_t status = verify_slot_access(owner_id, slot, 0); + + if (status == SCC_RET_OK) { + *address = + SCC_BASE + SCM_RED_MEMORY + scc_key_info[slot].offset; + if (value_size_bytes != NULL) { + *value_size_bytes = scc_key_info[slot].length; + } + if (slot_size_bytes != NULL) { + *slot_size_bytes = SCC_KEY_SLOT_SIZE; + } + } + + return status; +} + +/*****************************************************************************/ +/* fn scc_wait_completion() */ +/*****************************************************************************/ +/*! + * Poll looking for end-of-cipher indication. Only used + * if @c SCC_SCM_SLEEP is not defined. + * + * @internal + * + * On a Tahiti, crypto under 230 or so bytes is done after the first loop, all + * the way up to five sets of spins for 1024 bytes. (8- and 16-byte functions + * are done when we first look. Zeroizing takes one pass around. + */ +static void scc_wait_completion(void) +{ + int i = 0; + + /* check for completion by polling */ + while (!is_cipher_done() && (i++ < SCC_CIPHER_MAX_POLL_COUNT)) { + udelay(10); + } + pr_debug("SCC: Polled DONE %d times\n", i); +} /* scc_wait_completion() */ + +/*****************************************************************************/ +/* fn is_cipher_done() */ +/*****************************************************************************/ +/*! + * This function returns non-zero if SCM Status register indicates + * that a cipher has terminated or some other interrupt-generating + * condition has occurred. + */ +static int is_cipher_done(void) +{ + register uint32_t scm_status; + register int cipher_done; + + scm_status = SCC_READ_REGISTER(SCM_STATUS); + + /* + * Done when 'SCM is currently performing a function' bits are zero + */ + cipher_done = !(scm_status & (SCM_STATUS_ZEROIZING | + SCM_STATUS_CIPHERING)); + + return cipher_done; +} /* is_cipher_done() */ + +/*****************************************************************************/ +/* fn offset_within_smn() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SMN register set. + * + * @param[in] register_offset register offset of SMN. + * + * @return 1 if true, 0 if false (not within SMN) + */ +static inline int offset_within_smn(uint32_t register_offset) +{ + return register_offset >= SMN_STATUS && register_offset <= SMN_TIMER; +} + +/*****************************************************************************/ +/* fn offset_within_scm() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SCM register set. + * + * @param[in] register_offset Register offset of SCM + * + * @return 1 if true, 0 if false (not within SCM) + */ +static inline int offset_within_scm(uint32_t register_offset) +{ + return (register_offset >= SCM_RED_START) + && (register_offset < scm_highest_memory_address); + /* Although this would cause trouble for zeroize testing, this change would + * close a security whole which currently allows any kernel program to access + * any location in RED RAM. Perhaps enforce in non-SCC_DEBUG compiles? + && (register_offset <= SCM_INIT_VECTOR_1); */ +} + +/*****************************************************************************/ +/* fn check_register_accessible() */ +/*****************************************************************************/ +/*! + * Given the current SCM and SMN status, verify that access to the requested + * register should be OK. + * + * @param[in] register_offset register offset within SCC + * @param[in] smn_status recent value from #SMN_STATUS + * @param[in] scm_status recent value from #SCM_STATUS + * + * @return #SCC_RET_OK if ok, #SCC_RET_FAIL if not + */ +static scc_return_t +check_register_accessible(uint32_t register_offset, uint32_t smn_status, + uint32_t scm_status) +{ + int error_code = SCC_RET_FAIL; + + /* Verify that the register offset passed in is not among the verboten set + * if the SMN is in Fail mode. + */ + if (offset_within_smn(register_offset)) { + if ((smn_status & SMN_STATUS_STATE_MASK) == SMN_STATE_FAIL) { + if (!((register_offset == SMN_STATUS) || + (register_offset == SMN_COMMAND) || + (register_offset == SMN_DEBUG_DETECT_STAT))) { + pr_debug + ("SCC Driver: Note: Security State is in FAIL state.\n"); + } /* register not a safe one */ + else { + /* SMN is in FAIL, but register is a safe one */ + error_code = SCC_RET_OK; + } + } /* State is FAIL */ + else { + /* State is not fail. All registers accessible. */ + error_code = SCC_RET_OK; + } + } + /* offset within SMN */ + /* Not SCM register. Check for SCM busy. */ + else if (offset_within_scm(register_offset)) { + /* This is the 'cannot access' condition in the SCM */ + if ((scm_status & SCM_STATUS_BUSY) + /* these are always available - rest fail on busy */ + && !((register_offset == SCM_STATUS) || + (register_offset == SCM_ERROR_STATUS) || + (register_offset == SCM_INTERRUPT_CTRL) || + (register_offset == SCM_CONFIGURATION))) { + pr_debug + ("SCC Driver: Note: Secure Memory is in BUSY state.\n"); + } /* status is busy & register inaccessible */ + else { + error_code = SCC_RET_OK; + } + } + /* offset within SCM */ + return error_code; + +} /* check_register_accessible() */ + +/*****************************************************************************/ +/* fn check_register_offset() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SCC register set. + * + * @param[in] register_offset register offset of SMN. + * + * #SCC_RET_OK if ok, #SCC_RET_FAIL if not + */ +static scc_return_t check_register_offset(uint32_t register_offset) +{ + int return_value = SCC_RET_FAIL; + + /* Is it valid word offset ? */ + if (SCC_BYTE_OFFSET(register_offset) == 0) { + /* Yes. Is register within SCM? */ + if (offset_within_scm(register_offset)) { + return_value = SCC_RET_OK; /* yes, all ok */ + } + /* Not in SCM. Now look within the SMN */ + else if (offset_within_smn(register_offset)) { + return_value = SCC_RET_OK; /* yes, all ok */ + } + } + + return return_value; +} + +#ifdef SCC_REGISTER_DEBUG + +/*****************************************************************************/ +/* fn dbg_scc_read_register() */ +/*****************************************************************************/ +/*! + * Noisily read a 32-bit value to an SCC register. + * @param offset The address of the register to read. + * + * @return The register value + * */ +static uint32_t dbg_scc_read_register(uint32_t offset) +{ + uint32_t value; + + value = readl(scc_base + offset); + +#ifndef SCC_RAM_DEBUG /* print no RAM references */ + if ((offset < SCM_RED_MEMORY) || (offset >= scm_highest_memory_address)) { +#endif + pr_debug("SCC RD: 0x%4x : 0x%08x\n", offset, value); +#ifndef SCC_RAM_DEBUG + } +#endif + + return value; +} + +/*****************************************************************************/ +/* fn dbg_scc_write_register() */ +/*****************************************************************************/ +/* + * Noisily read a 32-bit value to an SCC register. + * @param offset The address of the register to written. + * + * @param value The new register value + */ +static void dbg_scc_write_register(uint32_t offset, uint32_t value) +{ + +#ifndef SCC_RAM_DEBUG /* print no RAM references */ + if ((offset < SCM_RED_MEMORY) || (offset >= scm_highest_memory_address)) { +#endif + pr_debug("SCC WR: 0x%4x : 0x%08x\n", offset, value); +#ifndef SCC_RAM_DEBUG + } +#endif + + (void)writel(value, scc_base + offset); +} + +#endif /* SCC_REGISTER_DEBUG */ diff --git a/drivers/mxc/security/mxc_scc_internals.h b/drivers/mxc/security/mxc_scc_internals.h new file mode 100644 index 000000000000..fddb0da9a4a5 --- /dev/null +++ b/drivers/mxc/security/mxc_scc_internals.h @@ -0,0 +1,498 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_SCC_INTERNALS_H__ +#define __MXC_SCC_INTERNALS_H__ + +/*! + * @file mxc_scc_internals.h + * + * @brief This is intended to be the file which contains most or all of the code or + * changes need to port the driver. It also includes other definitions needed + * by the driver. + * + * This header file should only ever be included by scc_driver.c + * + * Compile-time flags minimally needed: + * + * @li Some sort of platform flag. + * @li Some start-of-SCC consideration, such as SCC_BASE_ADDR + * + * Some changes which could be made when porting this driver: + * #SCC_SPIN_COUNT + * + * @ingroup MXCSCC + */ +#if 0 +#include /* Current version Linux kernel */ +#include /* Basic support for loadable modules, + printk */ +#include /* module_init, module_exit */ +#include /* General kernel system calls */ +#include /* for interrupt.h */ +#include +#include /* IRQ / interrupt definitions */ +#include /* ioremap() */ +#endif +#include + +/* Get handle on certain per-platform symbols */ +#ifdef TAHITI +#include + +/* + * Mark the SCC as always there... as Tahiti is not officially supported by + * driver. Porting opportunity. + */ +#define SCC_ENABLED() (1) + +#elif defined(MXC) + +#include +#include + +#ifdef SCC_FUSE + +/* + * This macro is used to determine whether the SCC is enabled/available + * on the platform. This macro may need to be ported. + */ +#define SCC_ENABLED() ((SCC_FUSE & MXC_IIMHWV1_SCC_DISABLE) == 0) + +#else + +#define SCC_ENABLED() (1) + +#endif + +#else /* neither TAHITI nor MXC */ + +#error Do not understand target architecture + +#endif /* TAHITI */ + +/* Temporarily define compile-time flags to make Doxygen happy. */ +#ifdef DOXYGEN_HACK +/*! @addtogroup scccompileflags */ +/*! @{ */ + +/*! @def NO_SMN_INTERRUPT + * The SMN interrupt is not wired to the CPU at all. + */ +#define NO_SMN_INTERRUPT + +/*! + * Register an interrupt handler for the SMN as well as + * the SCM. In some implementations, the SMN is not connected at all (see + * #NO_SMN_INTERRUPT), and in others, it is on the same interrupt line as the + * SCM. When defining this flag, the SMN interrupt should be on a separate + * line from the SCM interrupt. + */ + +#define USE_SMN_INTERRUPT + +/*! + * Turn on generation of run-time operational, debug, and error messages + */ +#define SCC_DEBUG + +/*! + * Turn on generation of run-time logging of access to the SCM and SMN + * registers. + */ +#define SCC_REGISTER_DEBUG + +/*! + * Turn on generation of run-time logging of access to the SCM Red and + * Black memories. Will only work if #SCC_REGISTER_DEBUG is also defined. + */ +#define SCC_RAM_DEBUG + +/*! + * If the driver finds the SCC in HEALTH_CHECK state, go ahead and + * run a quick ASC to bring it to SECURE state. + */ +#define SCC_BRINGUP + +/*! + * Expected to come from platform header files or compile command line. + * This symbol must be the address of the SCC + */ +#define SCC_BASE + +/*! + * This must be the interrupt line number of the SCM interrupt. + */ +#define INT_SCM + +/*! + * if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of + * the SMN interrupt. + */ +#define INT_SMN + +/*! + * Define the number of Stored Keys which the SCC driver will make available. + * Value shall be from 0 to 20. Default is zero (0). + */ +#define SCC_KEY_SLOTS + +/*! + * Make sure that this flag is defined if compiling for a Little-Endian + * platform. Linux Kernel builds provide this flag. + */ +#define __LITTLE_ENDIAN + +/*! + * Make sure that this flag is defined if compiling for a Big-Endian platform. + * Linux Kernel builds provide this flag. + */ +#define __BIG_ENDIAN + +/*! + * Read a 32-bit register value from a 'peripheral'. Standard Linux/Unix + * macro. + * + * @param offset Bus address of register to be read + * + * @return The value of the register + */ +#define readl(offset) + +/*! + * Write a 32-bit value to a register in a 'peripheral'. Standard Linux/Unix + * macro. + * + * @param value The 32-bit value to store + * @param offset Bus address of register to be written + * + * return (none) + */ +#define writel(value,offset) + + /*! @} *//* end group scccompileflags */ + +#endif /* DOXYGEN_HACK */ + +/*! + * Define the number of Stored Keys which the SCC driver will make available. + * Value shall be from 0 to 20. Default is zero (0). + */ +#define SCC_KEY_SLOTS 20 + +#ifndef SCC_KEY_SLOTS +#define SCC_KEY_SLOTS 0 + +#else + +#if (SCC_KEY_SLOTS < 0) || (SCC_KEY_SLOTS > 20) +#error Bad value for SCC_KEY_SLOTS +#endif + +/*! + * Maximum length of key/secret value which can be stored in SCC. + */ +#define SCC_MAX_KEY_SIZE 32 + +/*! + * This is the size, in bytes, of each key slot, and therefore the maximum size + * of the wrapped key. + */ +#define SCC_KEY_SLOT_SIZE 32 + +/*! + * This is the offset into each RAM of the base of the area which is + * not used for Stored Keys. + */ +#define SCM_NON_RESERVED_OFFSET (SCC_KEY_SLOTS * SCC_KEY_SLOT_SIZE) + +#endif + +/* These come for free with Linux, but may need to be set in a port. */ +#ifndef __BIG_ENDIAN +#ifndef __LITTLE_ENDIAN +#error One of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined +#endif +#else +#ifdef __LITTLE_ENDIAN +#error Exactly one of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined +#endif +#endif + +#ifndef SCC_CALLBACK_SIZE +/*! The number of function pointers which can be stored in #scc_callbacks. + * Defaults to 4, can be overridden with compile-line argument. + */ +#define SCC_CALLBACK_SIZE 4 +#endif + +/*! Initial CRC value for CCITT-CRC calculation. */ +#define CRC_CCITT_START 0xFFFF + +#ifdef TAHITI + +/*! + * The SCC_BASE has to be SMN_BASE_ADDR on TAHITI, as the banks of + * registers are swapped in place. + */ +#define SCC_BASE SMN_BASE_ADDR + +/*! The interrupt number for the SCC (SCM only!) on Tahiti */ +#define INT_SCC_SCM 62 + +/*! Tahiti does not have the SMN interrupt wired to the CPU. */ +#define NO_SMN_INTERRUPT + +#endif /* TAHITI */ + +/*! Number of times to spin between polling of SCC while waiting for cipher + * or zeroizing function to complete. See also #SCC_CIPHER_MAX_POLL_COUNT. */ +#define SCC_SPIN_COUNT 1000 + +/*! Number of times to polling SCC while waiting for cipher + * or zeroizing function to complete. See also #SCC_SPIN_COUNT. */ +#define SCC_CIPHER_MAX_POLL_COUNT 100 + +/*! + * @def SCC_READ_REGISTER + * Read a 32-bit value from an SCC register. Macro which depends upon + * #scc_base. Linux readl()/writel() macros operate on 32-bit quantities, as + * do SCC register reads/writes. + * + * @param offset Register offset within SCC. + * + * @return The value from the SCC's register. + */ +#ifndef SCC_REGISTER_DEBUG +#define SCC_READ_REGISTER(offset) __raw_readl(scc_base+(offset)) +#else +#define SCC_READ_REGISTER(offset) dbg_scc_read_register(offset) +#endif + +/*! + * Write a 32-bit value to an SCC register. Macro depends upon #scc_base. + * Linux readl()/writel() macros operate on 32-bit quantities, as do SCC + * register reads/writes. + * + * @param offset Register offset within SCC. + * @param value 32-bit value to store into the register + * + * @return (void) + */ +#ifndef SCC_REGISTER_DEBUG +#define SCC_WRITE_REGISTER(offset,value) (void)__raw_writel(value, scc_base+(offset)) +#else +#define SCC_WRITE_REGISTER(offset,value) dbg_scc_write_register(offset, value) +#endif + +/*! + * Calculates the byte offset into a word + * @param bp The byte (char*) pointer + * @return The offset (0, 1, 2, or 3) + */ +#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t)) + +/*! + * Converts (by rounding down) a byte pointer into a word pointer + * @param bp The byte (char*) pointer + * @return The word (uint32_t) as though it were an aligned (uint32_t*) + */ +#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1)) + +/*! + * Determine number of bytes in an SCC block + * + * @return Bytes / block + */ +#define SCC_BLOCK_SIZE_BYTES() scc_configuration.block_size_bytes + +/*! + * Maximum number of additional bytes which may be added in CRC+padding mode. + */ +#define PADDING_BUFFER_MAX_BYTES (CRC_SIZE_BYTES + sizeof(scc_block_padding)) + +/*! + * Shorthand (clearer, anyway) for number of bytes in a CRC. + */ +#define CRC_SIZE_BYTES (sizeof(crc_t)) + +/*! + * The polynomial used in CCITT-CRC calculation + */ +#define CRC_POLYNOMIAL 0x1021 + +/*! + * Calculate CRC on one byte of data + * + * @param[in,out] running_crc A value of type crc_t where CRC is kept. This + * must be an rvalue and an lvalue. + * @param[in] byte_value The byte (uint8_t, char) to be put in the CRC + * + * @return none + */ +#define CALC_CRC(byte_value,running_crc) { \ + uint8_t data; \ + data = (0xff&(byte_value)) ^ (running_crc >> 8); \ + running_crc = scc_crc_lookup_table[data] ^ (running_crc << 8); \ +} + +/*! Value of 'beginning of padding' marker in driver-provided padding */ +#define SCC_DRIVER_PAD_CHAR 0x80 + +/*! Name of the driver. Used (on Linux, anyway) when registering interrupts */ +#define SCC_DRIVER_NAME "scc" + +/* Port -- these symbols are defined in Linux 2.6 and later. They are defined + * here for backwards compatibility because this started life as a 2.4 + * driver, and as a guide to portation to other platforms. + */ + +#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + +#define irqreturn_t void /* Return type of an interrupt handler */ + +#define IRQ_HANDLED /* Would be '1' for handled -- as in return IRQ_HANDLED; */ + +#define IRQ_NONE /* would be '0' for not handled -- as in return IRQ_NONE; */ + +#define IRQ_RETVAL(x) /* Return x==0 (not handled) or non-zero (handled) */ + +#endif /* LINUX earlier than 2.5 */ + +/* These are nice to have around */ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif + +/*! Provide a typedef for the CRC which can be used in encrypt/decrypt */ +typedef uint16_t crc_t; + +/*! Gives high-level view of state of the SCC */ +enum scc_status { + SCC_STATUS_INITIAL, /*!< State of driver before ever checking */ + SCC_STATUS_CHECKING, /*!< Transient state while driver loading */ + SCC_STATUS_UNIMPLEMENTED, /*!< SCC is non-existent or unuseable */ + SCC_STATUS_OK, /*!< SCC is in Secure or Default state */ + SCC_STATUS_FAILED /*!< In Failed state */ +}; + +/*! + * Information about a key slot. + */ +struct scc_key_slot { + uint64_t owner_id; /*!< Access control value. */ + uint32_t length; /*!< Length of value in slot. */ + uint32_t offset; /*!< Offset of value from start of each RAM. */ + uint32_t status; /*!< 0 = unassigned, 1 = assigned. */ +}; + +/* Forward-declare a number routines which are not part of user api */ +static int scc_init(void); +static void scc_cleanup(void); + +/* Forward defines of internal functions */ +OS_DEV_ISR(scc_irq); +/*! Perform callbacks registered by #scc_monitor_security_failure(). + * + * Make sure callbacks only happen once... Since there may be some reason why + * the interrupt isn't generated, this routine could be called from base(task) + * level. + * + * One at a time, go through #scc_callbacks[] and call any non-null pointers. + */ +static void scc_perform_callbacks(void); +static uint32_t copy_to_scc(const uint8_t * from, uint32_t to, + unsigned long count_bytes, uint16_t * crc); +static uint32_t copy_from_scc(const uint32_t from, uint8_t * to, + unsigned long count_bytes, uint16_t * crc); +static scc_return_t scc_strip_padding(uint8_t * from, + unsigned *count_bytes_stripped); +static uint32_t scc_update_state(void); +static void scc_init_ccitt_crc(void); +static uint32_t scc_grab_config_values(void); +static int setup_interrupt_handling(void); +/*! + * Perform an encryption on the input. If @c verify_crc is true, a CRC must be + * calculated on the plaintext, and appended, with padding, before computing + * the ciphertext. + * + * @param[in] count_in_bytes Count of bytes of plaintext + * @param[in] data_in Pointer to the plaintext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing ciphertext + * @param[in] add_crc Flag for computing CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + */ +static scc_return_t scc_encrypt(uint32_t count_in_bytes, + const uint8_t * data_in, + uint32_t scm_control, uint8_t * data_out, + int add_crc, unsigned long *count_out_bytes); + +/*! + * Perform a decryption on the input. If @c verify_crc is true, the last block + * (maybe the two last blocks) is special - it should contain a CRC and + * padding. These must be stripped and verified. + * + * @param[in] count_in_bytes Count of bytes of ciphertext + * @param[in] data_in Pointer to the ciphertext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing plaintext + * @param[in] verify_crc Flag for running CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + + */ +static scc_return_t scc_decrypt(uint32_t count_in_bytes, + const uint8_t * data_in, + uint32_t scm_control, uint8_t * data_out, + int verify_crc, unsigned long *count_out_bytes); + +static void scc_wait_completion(void); +static int is_cipher_done(void); +static scc_return_t check_register_accessible(uint32_t offset, + uint32_t smn_status, + uint32_t scm_status); +static scc_return_t check_register_offset(uint32_t offset); + +#ifdef SCC_REGISTER_DEBUG +static uint32_t dbg_scc_read_register(uint32_t offset); +static void dbg_scc_write_register(uint32_t offset, uint32_t value); +#endif + +/* For Linux kernel, export the API functions to other kernel modules */ +EXPORT_SYMBOL(scc_get_configuration); +EXPORT_SYMBOL(scc_zeroize_memories); +EXPORT_SYMBOL(scc_crypt); +EXPORT_SYMBOL(scc_set_sw_alarm); +EXPORT_SYMBOL(scc_monitor_security_failure); +EXPORT_SYMBOL(scc_stop_monitoring_security_failure); +EXPORT_SYMBOL(scc_read_register); +EXPORT_SYMBOL(scc_write_register); +EXPORT_SYMBOL(scc_alloc_slot); +EXPORT_SYMBOL(scc_dealloc_slot); +EXPORT_SYMBOL(scc_load_slot); +EXPORT_SYMBOL(scc_encrypt_slot); +EXPORT_SYMBOL(scc_decrypt_slot); +EXPORT_SYMBOL(scc_get_slot_info); + +/* Tell Linux where to invoke driver at boot/module load time */ +module_init(scc_init); +/* Tell Linux where to invoke driver on module unload */ +module_exit(scc_cleanup); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Device Driver for SCC (SMN/SCM)"); + +#endif /* __MXC_SCC_INTERNALS_H__ */ diff --git a/drivers/mxc/security/rng/Makefile b/drivers/mxc/security/rng/Makefile new file mode 100644 index 000000000000..7d3332e2e675 --- /dev/null +++ b/drivers/mxc/security/rng/Makefile @@ -0,0 +1,35 @@ +# Makefile for the Linux RNG Driver +# +# This makefile works within a kernel driver tree + + # Makefile for rng_driver + + +# Possible configurable paramters +CFG_RNG += -DRNGA_MAX_REQUEST_SIZE=32 + +#DBG_RNGA = -DRNGA_DEBUG +#DBG_RNGA += -DRNGA_REGISTER_DEBUG +#DBG_RNGA += -DRNGA_ENTROPY_DEBUG + +EXTRA_CFLAGS = -DLINUX_KERNEL $(CFG_RNG) $(DBG_RNG) + + +ifeq ($(CONFIG_MXC_RNG_TEST_DRIVER),y) +EXTRA_CFLAGS += -DRNG_REGISTER_PEEK_POKE +endif +ifeq ($(CONFIG_RNG_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif + + +EXTRA_CFLAGS += -Idrivers/mxc/security/rng/include -Idrivers/mxc/security/sahara2/include + +obj-$(CONFIG_MXC_SECURITY_RNG) += shw.o +#shw-objs := shw_driver.o shw_memory_mapper.o ../sahara2/fsl_shw_keystore.o +shw-objs := shw_driver.o shw_memory_mapper.o ../sahara2/fsl_shw_keystore.o \ + fsl_shw_sym.o fsl_shw_wrap.o shw_dryice.o des_key.o \ + shw_hash.o shw_hmac.o + +obj-$(CONFIG_MXC_SECURITY_RNG) += rng.o +rng-objs := rng_driver.o diff --git a/drivers/mxc/security/rng/des_key.c b/drivers/mxc/security/rng/des_key.c new file mode 100644 index 000000000000..14ac2b3cdd5e --- /dev/null +++ b/drivers/mxc/security/rng/des_key.c @@ -0,0 +1,385 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file des_key.c + * + * This file implements the function #fsl_shw_permute1_bytes(). + * + * The code was lifted from crypto++ v5.5.2, which is public domain code. The + * code to handle words instead of bytes was extensively modified from the byte + * version and then converted to handle one to three keys at once. + * + */ + +#include "shw_driver.h" +#ifdef DIAG_SECURITY_FUNC +#include "apihelp.h" +#endif + +#ifndef __KERNEL__ +#include +#include /* or whichever is proper for target arch */ +#endif + +#ifdef DEBUG +#undef DEBUG /* TEMPORARY */ +#endif + +#if defined(DEBUG) || defined(SELF_TEST) +static void DUMP_BYTES(const char *label, const uint8_t * data, int len) +{ + int i; + + printf("%s: ", label); + for (i = 0; i < len; i++) { + printf("%02X", data[i]); + if ((i % 8 == 0) && (i != 0)) { + printf("_"); /* key separator */ + } + } + printf("\n"); +} + +static void DUMP_WORDS(const char *label, const uint32_t * data, int len) +{ + int i, j; + + printf("%s: ", label); + /* Dump the words in reverse order, so that they are intelligible */ + for (i = len - 1; i >= 0; i--) { + for (j = 3; j >= 0; j--) { + uint32_t word = data[i]; + printf("%02X", (word >> ((j * 8)) & 0xff)); + if ((i != 0) && ((((i) * 4 + 5 + j) % 7) == 5)) + printf("_"); /* key separator */ + } + printf("|"); /* word separator */ + } + printf("\n"); +} +#else +#define DUMP_BYTES(label, data,len) +#define DUMP_WORDS(label, data,len) +#endif + +/*! + * permuted choice table (key) + * + * Note that this table has had one subtracted from each element so that the + * code doesn't have to do it. + */ +static const uint8_t pc1[] = { + 56, 48, 40, 32, 24, 16, 8, + 0, 57, 49, 41, 33, 25, 17, + 9, 1, 58, 50, 42, 34, 26, + 18, 10, 2, 59, 51, 43, 35, + 62, 54, 46, 38, 30, 22, 14, + 6, 61, 53, 45, 37, 29, 21, + 13, 5, 60, 52, 44, 36, 28, + 20, 12, 4, 27, 19, 11, 3, +}; + +/*! bit 0 is left-most in byte */ +static const int bytebit[] = { + 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 +}; + +/*! + * Convert a 3-key 3DES key into the first-permutation 168-bit version. + * + * This is the format of the input key: + * + * @verbatim + BIT: |191 128|127 64|63 0| + BYTE: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | + KEY: | 0 | 1 | 2 | + @endverbatim + * + * This is the format of the output key: + * + * @verbatim + BIT: |167 112|111 56|55 0| + BYTE: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | + KEY: | 1 | 2 | 3 | + @endverbatim + * + * @param[in] key bytes of 3DES key + * @param[out] permuted_key 21 bytes of permuted key + * @param[in] key_count How many DES keys (2 or 3) + */ +void fsl_shw_permute1_bytes(const uint8_t * key, uint8_t * permuted_key, + int key_count) +{ + int i; + int j; + int l; + int m; + + DUMP_BYTES("Input key", key, 8 * key_count); + + /* For each individual sub-key */ + for (i = 0; i < 3; i++) { + DUMP_BYTES("(key)", key, 8); + memset(permuted_key, 0, 7); + /* For each bit of key */ + for (j = 0; j < 56; j++) { /* convert pc1 to bits of key */ + l = pc1[j]; /* integer bit location */ + m = l & 07; /* find bit */ + permuted_key[j >> 3] |= (((key[l >> 3] & /* find which key byte l is in */ + bytebit[m]) /* and which bit of that byte */ + ? 0x80 : 0) >> (j % 8)); /* and store 1-bit result */ + } + switch (i) { + case 0: + if (key_count != 1) + key += 8; /* move on to second key */ + break; + case 1: + if (key_count == 2) + key -= 8; /* go back to first key */ + else if (key_count == 3) + key += 8; /* move on to third key */ + break; + default: + break; + } + permuted_key += 7; + } + DUMP_BYTES("Output key (bytes)", permuted_key - 21, 21); +} + +#ifdef SELF_TEST +const uint8_t key1_in[] = { + /* FE01FE01FE01FE01_01FE01FE01FE01FE_FEFE0101FEFE0101 */ + 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, + 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, + 0xFE, 0xFE, 0x01, 0x01, 0xFE, 0xFE, 0x01, 0x01 +}; + +const uint32_t key1_word_in[] = { + 0xFE01FE01, 0xFE01FE01, + 0x01FE01FE, 0x01FE01FE, + 0xFEFE0101, 0xFEFE0101 +}; + +uint8_t exp_key1_out[] = { + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33 +}; + +uint32_t exp_word_key1_out[] = { + 0x33333333, 0xAA333333, 0xAAAAAAAA, 0x5555AAAA, + 0x55555555, 0x00000055, +}; + +const uint8_t key2_in[] = { + 0xEF, 0x10, 0xBB, 0xA4, 0x23, 0x49, 0x42, 0x58, + 0x01, 0x28, 0x01, 0x4A, 0x10, 0xE4, 0x03, 0x59, + 0xFE, 0x84, 0x30, 0x29, 0x8E, 0xF1, 0x10, 0x5A +}; + +const uint32_t key2_word_in[] = { + 0xEF10BBA4, 0x23494258, + 0x0128014A, 0x10E40359, + 0xFE843029, 0x8EF1105A +}; + +uint8_t exp_key2_out[] = { + 0x0D, 0xE1, 0x1D, 0x85, 0x50, 0x9A, 0x56, 0x20, + 0xA8, 0x22, 0x94, 0x82, 0x08, 0xA0, 0x33, 0xA1, + 0x2D, 0xE9, 0x11, 0x39, 0x95 +}; + +uint32_t exp_word_key2_out[] = { + 0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8, + 0xE11D8550, 0x0000000D +}; + +const uint8_t key3_in[] = { + 0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C, + 0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69, + 0xB3, 0x7C, 0x98, 0xD8, 0xC9, 0x35, 0x57, 0x19 +}; + +const uint32_t key3_word_in[] = { + 0xEF10BBA4, 0x23494258, + 0x0128014A, 0x10E40359, + 0xFE843029, 0x8EF1105A +}; + +uint8_t exp_key3_out[] = { + 0x02, 0x3E, 0x93, 0xA7, 0x9F, 0x18, 0xF1, 0x11, + 0xC6, 0x96, 0x00, 0x62, 0xA8, 0x96, 0x02, 0x3E, + 0x93, 0xA7, 0x9F, 0x18, 0xF1 +}; + +uint32_t exp_word_key3_out[] = { + 0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8, + 0xE11D8550, 0x0000000D +}; + +const uint8_t key4_in[] = { + 0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C, + 0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69, +}; + +const uint32_t key4_word_in[] = { + 0xEF10BBA4, 0x23494258, + 0x0128014A, 0x10E40359, + 0xFE843029, 0x8EF1105A +}; + +const uint8_t key5_in[] = { + 0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C, + 0x89, 0x77, 0x73, 0x0C, 0xA0, 0x05, 0x41, 0x69, + 0x3F, 0xE9, 0x49, 0x4B, 0x67, 0x57, 0x07, 0x3C, +}; + +uint8_t exp_key4_out[] = { + 0x0D, 0xE1, 0x1D, 0x85, 0x50, 0x9A, 0x56, 0x20, + 0xA8, 0x22, 0x94, 0x82, 0x08, 0xA0, 0x33, 0xA1, + 0x2D, 0xE9, 0x11, 0x39, 0x95 +}; + +uint32_t exp_word_key4_out[] = { + 0xE9113995, 0xA033A12D, 0x22948208, 0x9A5620A8, + 0xE11D8550, 0x0000000D +}; + +const uint8_t key6_in[] = { + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 +}; + +uint8_t exp_key6_out[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +uint32_t exp_word_key6_out[] = { + 0x00000000, 0x0000000, 0x0000000, 0x00000000, + 0x00000000, 0x0000000 +}; + +const uint8_t key7_in[] = { + /* 01FE01FE01FE01FE_FE01FE01FE01FE01_0101FEFE0101FEFE */ + /* 0101FEFE0101FEFE_FE01FE01FE01FE01_01FE01FE01FE01FE */ + 0x01, 0x01, 0xFE, 0xFE, 0x01, 0x01, 0xFE, 0xFE, + 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, + 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, +}; + +uint8_t exp_key7_out[] = { + 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x55, + 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa +}; + +uint32_t exp_word_key7_out[] = { + 0xcccccccc, 0x55cccccc, 0x55555555, 0xaaaa5555, + 0xaaaaaaaa, 0x000000aa +}; + +int run_test(const uint8_t * key_in, + const int key_count, + const uint32_t * key_word_in, + const uint8_t * exp_bytes_key_out, + const uint32_t * exp_word_key_out) +{ + uint8_t key_out[22]; + uint32_t word_key_out[6]; + int failed = 0; + + memset(key_out, 0x42, 22); + fsl_shw_permute1_bytes(key_in, key_out, key_count); + if (memcmp(key_out, exp_bytes_key_out, 21) != 0) { + printf("bytes_to_bytes: ERROR: \n"); + DUMP_BYTES("key_in", key_in, 8 * key_count); + DUMP_BYTES("key_out", key_out, 21); + DUMP_BYTES("exp_out", exp_bytes_key_out, 21); + failed |= 1; + } else if (key_out[21] != 0x42) { + printf("bytes_to_bytes: ERROR: Buffer overflow 0x%02x\n", + (int)key_out[21]); + } else { + printf("bytes_to_bytes: OK\n"); + } +#if 0 + memset(word_key_out, 0x42, 21); + fsl_shw_permute1_bytes_to_words(key_in, word_key_out, key_count); + if (memcmp(word_key_out, exp_word_key_out, 21) != 0) { + printf("bytes_to_words: ERROR: \n"); + DUMP_BYTES("key_in", key_in, 8 * key_count); + DUMP_WORDS("key_out", word_key_out, 6); + DUMP_WORDS("exp_out", exp_word_key_out, 6); + failed |= 1; + } else { + printf("bytes_to_words: OK\n"); + } + + if (key_word_in != NULL) { + memset(word_key_out, 0x42, 21); + fsl_shw_permute1_words_to_words(key_word_in, word_key_out); + if (memcmp(word_key_out, exp_word_key_out, 21) != 0) { + printf("words_to_words: ERROR: \n"); + DUMP_BYTES("key_in", key_in, 24); + DUMP_WORDS("key_out", word_key_out, 6); + DUMP_WORDS("exp_out", exp_word_key_out, 6); + failed |= 1; + } else { + printf("words_to_words: OK\n"); + } + } +#endif + + return failed; +} /* end fn run_test */ + +int main() +{ + int failed = 0; + + printf("key1\n"); + failed |= + run_test(key1_in, 3, key1_word_in, exp_key1_out, exp_word_key1_out); + printf("\nkey2\n"); + failed |= + run_test(key2_in, 3, key2_word_in, exp_key2_out, exp_word_key2_out); + printf("\nkey3\n"); + failed |= run_test(key3_in, 3, NULL, exp_key3_out, exp_word_key3_out); + printf("\nkey4\n"); + failed |= run_test(key4_in, 2, NULL, exp_key4_out, exp_word_key4_out); + printf("\nkey5\n"); + failed |= run_test(key5_in, 3, NULL, exp_key4_out, exp_word_key4_out); + printf("\nkey6 - 3\n"); + failed |= run_test(key6_in, 3, NULL, exp_key6_out, exp_word_key6_out); + printf("\nkey6 - 2\n"); + failed |= run_test(key6_in, 2, NULL, exp_key6_out, exp_word_key6_out); + printf("\nkey6 - 1\n"); + failed |= run_test(key6_in, 1, NULL, exp_key6_out, exp_word_key6_out); + printf("\nkey7\n"); + failed |= run_test(key7_in, 3, NULL, exp_key7_out, exp_word_key7_out); + printf("\n"); + + if (failed != 0) { + printf("TEST FAILED\n"); + } + return failed; +} + +#endif /* SELF_TEST */ diff --git a/drivers/mxc/security/rng/fsl_shw_hash.c b/drivers/mxc/security/rng/fsl_shw_hash.c new file mode 100644 index 000000000000..56b2dcc34035 --- /dev/null +++ b/drivers/mxc/security/rng/fsl_shw_hash.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file fsl_shw_hash.c + * + * This file implements Cryptographic Hashing functions of the FSL SHW API + * for Sahara. This does not include HMAC. + */ + +#include "shw_driver.h" + +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */ +/*! + * Hash a stream of data with a cryptographic hash algorithm. + * + * The flags in the @a hash_ctx control the operation of this function. + * + * Hashing functions work on 64 octets of message at a time. Therefore, when + * any partial hashing of a long message is performed, the message @a length of + * each segment must be a multiple of 64. When ready to + * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value. + * + * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a + * one-shot complete hash, including padding, will be performed. The @a length + * may be any value. + * + * The first octets of a data stream can be hashed by setting the + * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags. The @a length must be + * a multiple of 64. + * + * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by + * #FSL_HASH_FLAGS_SAVE. The two in combination will allow a (multiple-of-64 + * octets) 'middle sequence' of the data stream to be hashed with the + * beginning. The @a length must again be a multiple of 64. + * + * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously + * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and + * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the + * stream. The @a length may be any value. + * + * If the user program wants to do the padding for the hash, it can leave off + * the #FSL_HASH_FLAGS_FINALIZE flag. The @a length must then be a multiple of + * 64 octets. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] hash_ctx Hashing algorithm and state of the cipher. + * @param msg Pointer to the data to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result If not null, pointer to where to store the hash + * digest. + * @param result_len Number of octets to store in @a result. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)hash_ctx; + (void)msg; + (void)length; + (void)result; + (void)result_len; + + return ret; +} diff --git a/drivers/mxc/security/rng/fsl_shw_hmac.c b/drivers/mxc/security/rng/fsl_shw_hmac.c new file mode 100644 index 000000000000..23a2fb3d3292 --- /dev/null +++ b/drivers/mxc/security/rng/fsl_shw_hmac.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file fsl_shw_hmac.c + * + * This file implements Hashed Message Authentication Code functions of the FSL + * SHW API. + */ + +#include "shw_driver.h" + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */ +/*! + * Get the precompute information + * + * + * @param user_ctx + * @param key_info + * @param hmac_ctx + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx) +{ + fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)hmac_ctx; + + return status; +} + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */ +/*! + * Get the hmac + * + * + * @param user_ctx Info for acquiring memory + * @param key_info + * @param hmac_ctx + * @param msg + * @param length + * @param result + * @param result_len + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)hmac_ctx; + (void)msg; + (void)length; + (void)result; + (void)result_len; + + return status; +} diff --git a/drivers/mxc/security/rng/fsl_shw_rand.c b/drivers/mxc/security/rng/fsl_shw_rand.c new file mode 100644 index 000000000000..7ba49d8d470f --- /dev/null +++ b/drivers/mxc/security/rng/fsl_shw_rand.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file fsl_shw_rand.c + * + * This file implements Random Number Generation functions of the FSL SHW API + * in USER MODE for talking to a standalone RNGA/RNGC device driver. + * + * It contains the fsl_shw_get_random() and fsl_shw_add_entropy() functions. + * + * These routines will build a request block and pass it to the SHW driver. + */ + +#include +#include +#include +#include +#include +#include + +#ifdef FSL_DEBUG +#include +#include +#include +#endif /* FSL_DEBUG */ + +#include "shw_driver.h" + +extern fsl_shw_return_t validate_uco(fsl_shw_uco_t * uco); + +#if defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC) + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* perform a sanity check / update uco */ + ret = validate_uco(user_ctx); + if (ret == FSL_RETURN_OK_S) { + struct get_random_req *req = malloc(sizeof(*req)); + + if (req == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + } else { + + init_req(&req->hdr, user_ctx); + req->size = length; + req->random = data; + + ret = + send_req(SHW_USER_REQ_GET_RANDOM, &req->hdr, + user_ctx); + } + } + + return ret; +} + +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* perform a sanity check on the uco */ + ret = validate_uco(user_ctx); + if (ret == FSL_RETURN_OK_S) { + struct add_entropy_req *req = malloc(sizeof(*req)); + + if (req == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + } else { + init_req(&req->hdr, user_ctx); + req->size = length; + req->entropy = data; + + ret = + send_req(SHW_USER_REQ_ADD_ENTROPY, &req->hdr, + user_ctx); + } + } + + return ret; +} + +#else /* no H/W RNG block */ + +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + + (void)user_ctx; + (void)length; + (void)data; + + return FSL_RETURN_ERROR_S; +} + +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + + (void)user_ctx; + (void)length; + (void)data; + + return FSL_RETURN_ERROR_S; +} +#endif diff --git a/drivers/mxc/security/rng/fsl_shw_sym.c b/drivers/mxc/security/rng/fsl_shw_sym.c new file mode 100644 index 000000000000..bcd8a0efcced --- /dev/null +++ b/drivers/mxc/security/rng/fsl_shw_sym.c @@ -0,0 +1,317 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/*! + * @file fsl_shw_sym.c + * + * This file implements the Symmetric Cipher functions of the FSL SHW API. Its + * features are limited to what can be done with the combination of SCC and + * DryIce. + */ +#include "fsl_platform.h" +#include "shw_driver.h" + +#if defined(__KERNEL__) && defined(FSL_HAVE_DRYICE) + +#include "../dryice.h" +#include +#ifdef DIAG_SECURITY_FUNC +#include "apihelp.h" +#endif + +#include + +#define SYM_DECRYPT 0 +#define SYM_ENCRYPT 1 + +extern fsl_shw_return_t shw_convert_pf_key(fsl_shw_pf_key_t shw_pf_key, + di_key_t * di_keyp); + +/*! 'Initial' IV for presence of FSL_SYM_CTX_LOAD flag */ +static uint8_t zeros[8] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/*! + * Common function for encryption and decryption + * + * This is for a device with DryIce. + * + * A key must either refer to a 'pure' HW key, or, if PRG or PRG_IIM, + * established, then that key will be programmed. Then, the HW_key in the + * object will be selected. After this setup, the ciphering will be performed + * by calling the SCC driver.. + * + * The function 'releases' the reservations before it completes. + */ +fsl_shw_return_t do_symmetric(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + int encrypt, + uint32_t length, + const uint8_t * in, uint8_t * out) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + int key_selected = 0; + uint8_t *iv = NULL; + unsigned long count_out = length; + di_key_t di_key = DI_KEY_PK; /* default for user key */ + di_key_t di_key_orig; /* currently selected key */ + di_key_t selected_key = -1; + di_return_t di_code; + scc_return_t scc_code; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* No software keys allowed */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + ret = FSL_RETURN_BAD_FLAG_S; + } + + /* The only algorithm the SCC supports */ + if (key_info->algorithm != FSL_KEY_ALG_TDES) { + ret = FSL_RETURN_BAD_ALGORITHM_S; + goto out; + } + + /* Validate key length */ + if ((key_info->key_length != 16) + && (key_info->key_length != 21) + && (key_info->key_length != 24)) { + ret = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } + + /* Validate data is multiple of DES/TDES block */ + if ((length & 7) != 0) { + ret = FSL_RETURN_BAD_DATA_LENGTH_S; + goto out; + } + + /* Do some setup according to where the key lives */ + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + if ((key_info->pf_key != FSL_SHW_PF_KEY_PRG) + && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG)) { + ret = FSL_RETURN_ERROR_S; + } + } else if (key_info->flags & FSL_SKO_KEY_PRESENT) { + ret = FSL_RETURN_BAD_FLAG_S; + } else if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) { + /* + * No key present or established, just refer to HW + * as programmed. + */ + } else { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Now make proper selection */ + ret = shw_convert_pf_key(key_info->pf_key, &di_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Determine the current DI key selection */ + di_code = dryice_check_key(&di_key_orig); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not save current DI key state: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + + /* If the requested DI key is already selected, don't re-select it. */ + if (di_key != di_key_orig) { + di_code = dryice_select_key(di_key, 0); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Error from select_key: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_INTERNAL_ERROR_S; + goto out; + } + } + key_selected = 1; + + /* Verify that we are using the key we want */ + di_code = dryice_check_key(&selected_key); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Error from check_key: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_INTERNAL_ERROR_S; + goto out; + } + + if (di_key != selected_key) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Wrong key in use: %d instead of %d\n\n", + selected_key, di_key); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + + if (sym_ctx->mode == FSL_SYM_MODE_CBC) { + if ((sym_ctx->flags & FSL_SYM_CTX_LOAD) + && !(sym_ctx->flags & FSL_SYM_CTX_INIT)) { + iv = sym_ctx->context; + } else if ((sym_ctx->flags & FSL_SYM_CTX_INIT) + && !(sym_ctx->flags & FSL_SYM_CTX_LOAD)) { + iv = zeros; + } else { + /* Exactly one must be set! */ + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + } + + /* Now run the data through the SCC */ + scc_code = scc_crypt(length, in, iv, + encrypt ? SCC_ENCRYPT : SCC_DECRYPT, + (sym_ctx->mode == FSL_SYM_MODE_ECB) + ? SCC_ECB_MODE : SCC_CBC_MODE, + SCC_VERIFY_MODE_NONE, out, &count_out); + if (scc_code != SCC_RET_OK) { + ret = FSL_RETURN_INTERNAL_ERROR_S; +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("scc_code from scc_crypt() is %d\n", scc_code); +#endif + goto out; + } + + if ((sym_ctx->mode == FSL_SYM_MODE_CBC) + && (sym_ctx->flags & FSL_SYM_CTX_SAVE)) { + /* Save the context for the caller */ + if (encrypt) { + /* Last ciphertext block ... */ + memcpy(sym_ctx->context, out + length - 8, 8); + } else { + /* Last ciphertext block ... */ + memcpy(sym_ctx->context, in + length - 8, 8); + } + } + + ret = FSL_RETURN_OK_S; + + out: + if (key_selected) { + (void)dryice_release_key_selection(); + } + + return ret; +} + +EXPORT_SYMBOL(fsl_shw_symmetric_encrypt); +/*! + * Compute symmetric encryption + * + * + * @param user_ctx + * @param key_info + * @param sym_ctx + * @param length + * @param pt + * @param ct + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, uint8_t * ct) +{ + fsl_shw_return_t ret; + + ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_ENCRYPT, + length, pt, ct); + + return ret; +} + +EXPORT_SYMBOL(fsl_shw_symmetric_decrypt); +/*! + * Compute symmetric decryption + * + * + * @param user_ctx + * @param key_info + * @param sym_ctx + * @param length + * @param pt + * @param ct + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, uint8_t * pt) +{ + fsl_shw_return_t ret; + + ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_DECRYPT, + length, ct, pt); + + return ret; +} + +#else /* __KERNEL__ && DRYICE */ + +fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, uint8_t * ct) +{ + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)sym_ctx; + (void)length; + (void)pt; + (void)ct; + + return FSL_RETURN_ERROR_S; +} + +fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, uint8_t * pt) +{ + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)sym_ctx; + (void)length; + (void)ct; + (void)pt; + + return FSL_RETURN_ERROR_S; +} + +#endif /* __KERNEL__ and DRYICE */ diff --git a/drivers/mxc/security/rng/fsl_shw_wrap.c b/drivers/mxc/security/rng/fsl_shw_wrap.c new file mode 100644 index 000000000000..c7d6947296af --- /dev/null +++ b/drivers/mxc/security/rng/fsl_shw_wrap.c @@ -0,0 +1,1301 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_wrap.c + * + * This file implements Key-Wrap (Black Key) and Key Establishment functions of + * the FSL SHW API for the SHW (non-SAHARA) driver. + * + * This is the Black Key information: + * + *
    + *
  • Ownerid is an 8-byte, user-supplied, value to keep KEY + * confidential.
    • + *
  • KEY is a 1-32 byte value which starts in SCC RED RAM before + * wrapping, and ends up there on unwrap. Length is limited because of + * size of SCC1 RAM.
    • + *
  • KEY' is the encrypted KEY
    • + *
  • LEN is a 1-byte (for now) byte-length of KEY
    • + *
  • ALG is a 1-byte value for the algorithm which which the key is + * associated. Values are defined by the FSL SHW API
    • + *
  • FLAGS is a 1-byte value contain information like "this key is for + * software" (TBD)
    • + *
  • Ownerid, LEN, and ALG come from the user's "key_info" object, as does + * the slot number where KEY already is/will be.
    • + *
  • T is a Nonce
    • + *
  • T' is the encrypted T
    • + *
  • KEK is a Key-Encryption Key for the user's Key
    • + *
  • ICV is the "Integrity Check Value" for the wrapped key
    • + *
  • Black Key is the string of bytes returned as the wrapped key
    • + *
  • Wrap Key is the user's choice for encrypting the nonce. One of + * the Fused Key, the Random Key, or the XOR of the two. + *
+ + + + + + + + + + + + + + + + + + +
BLACK_KEY =ICV | T' | LEN | ALG | + FLAGS | KEY'
 
To Wrap
T = RND()16 +
KEK=HASHsha256(T | + Ownerid)16
KEY'= + TDEScbc-enc(Key=KEK, Data=KEY, IV=Ownerid)
ICV=HMACsha256 + (Key=T, Data=Ownerid | LEN | ALG | FLAGS | KEY')16
T'=TDESecb-enc + (Key=Wrap_Key, IV=Ownerid, Data=T)
 
To Unwrap
T=TDESecb-dec + (Key=Wrap_Key, IV=Ownerid, Data=T')
ICV=HMACsha256 + (Key=T, Data=Ownerid | LEN | ALG | FLAGS | KEY')16
KEK=HASHsha256 + (T | Ownerid)16
KEY=TDEScbc-dec + (Key=KEK, Data=KEY', IV=Ownerid)
+ + * This code supports two types of keys: Software Keys and keys destined for + * (or residing in) the DryIce Programmed Key Register. + * + * Software Keys go to / from the keystore. + * + * PK keys go to / from the DryIce Programmed Key Register. + * + * This code only works on a platform with DryIce. "software" keys go into + * the keystore. "Program" keys go to the DryIce Programmed Key Register. + * As far as this code is concerned, the size of that register is 21 bytes, + * the size of a 3DES key with parity stripped. + * + * The maximum key size supported for wrapped/unwrapped keys depends upon + * LENGTH_LENGTH. Currently, it is one byte, so the maximum key size is + * 255 bytes. However, key objects cannot currently hold a key of this + * length, so a smaller key size is the max. + */ + +#include "fsl_platform.h" + +/* This code only works in kernel mode */ + +#include "shw_driver.h" +#ifdef DIAG_SECURITY_FUNC +#include "apihelp.h" +#endif + +#if defined(__KERNEL__) && defined(FSL_HAVE_DRYICE) + +#include "../dryice.h" +#include + +#include "portable_os.h" +#include "fsl_shw_keystore.h" + +#include + +#include "shw_hmac.h" +#include "shw_hash.h" + +#define ICV_LENGTH 16 +#define T_LENGTH 16 +#define KEK_LENGTH 21 +#define LENGTH_LENGTH 1 +#define ALGORITHM_LENGTH 1 +#define FLAGS_LENGTH 1 + +/* ICV | T' | LEN | ALG | FLAGS | KEY' */ +#define ICV_OFFSET 0 +#define T_PRIME_OFFSET (ICV_OFFSET + ICV_LENGTH) +#define LENGTH_OFFSET (T_PRIME_OFFSET + T_LENGTH) +#define ALGORITHM_OFFSET (LENGTH_OFFSET + LENGTH_LENGTH) +#define FLAGS_OFFSET (ALGORITHM_OFFSET + ALGORITHM_LENGTH) +#define KEY_PRIME_OFFSET (FLAGS_OFFSET + FLAGS_LENGTH) + +#define FLAGS_SW_KEY 0x01 + +#define LENGTH_PATCH 8 +#define LENGTH_PATCH_MASK (LENGTH_PATCH - 1) + +/*! rounded up from 168 bits to the next word size */ +#define HW_KEY_LEN_WORDS_BITS 192 + +/*! + * Round a key length up to the TDES block size + * + * @param len Length of key, in bytes + * + * @return Length rounded up, if necessary + */ +#define ROUND_LENGTH(len) \ +({ \ + uint32_t orig_len = len; \ + uint32_t new_len; \ + \ + if ((orig_len & LENGTH_PATCH_MASK) != 0) { \ + new_len = (orig_len + LENGTH_PATCH \ + - (orig_len & LENGTH_PATCH_MASK)); \ + } \ + else { \ + new_len = orig_len; \ + } \ + \ + new_len; \ +}) + +/* This is the system keystore object */ +extern fsl_shw_kso_t system_keystore; + +#ifdef DIAG_SECURITY_FUNC +static void dump(const char *name, const uint8_t * data, unsigned int len) +{ + os_printk("%s: ", name); + while (len > 0) { + os_printk("%02x ", (unsigned)*data++); + len--; + } + os_printk("\n"); +} +#endif + +/* + * For testing of the algorithm implementation,, the DO_REPEATABLE_WRAP flag + * causes the T_block to go into the T field during a wrap operation. This + * will make the black key value repeatable (for a given SCC secret key, or + * always if the default key is in use). + * + * Normally, a random sequence is used. + */ +#ifdef DO_REPEATABLE_WRAP +/*! + * Block of zeroes which is maximum Symmetric block size, used for + * initializing context register, etc. + */ +static uint8_t T_block[16] = { + 0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42, + 0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42 +}; +#endif + +EXPORT_SYMBOL(fsl_shw_establish_key); +EXPORT_SYMBOL(fsl_shw_read_key); +EXPORT_SYMBOL(fsl_shw_extract_key); +EXPORT_SYMBOL(fsl_shw_release_key); + +extern fsl_shw_return_t alloc_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info); + +extern fsl_shw_return_t load_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + const uint8_t * key); + +extern fsl_shw_return_t dealloc_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info); + +/*! + * Initalialize SKO and SCCO used for T <==> T' cipher operation + * + * @param wrap_key Which wrapping key user wants + * @param key_info Key object for selecting wrap key + * @param wrap_ctx Sym Context object for doing the cipher op + */ +static inline void init_wrap_key(fsl_shw_pf_key_t wrap_key, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * wrap_ctx) +{ + fsl_shw_sko_init_pf_key(key_info, FSL_KEY_ALG_TDES, wrap_key); + fsl_shw_scco_init(wrap_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_ECB); +} + +/*! + * Insert descriptors to calculate ICV = HMAC(key=T, data=LEN|ALG|KEY') + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param T Location of nonce (length is T_LENGTH bytes) + * @param userid Location of userid/ownerid + * @param userid_len Length, in bytes of @c userid + * @param black_key Beginning of Black Key region + * @param key_length Number of bytes of key' there are in @c black_key + * @param[out] hmac Location to store ICV. Will be tagged "USES" so + * sf routines will not try to free it. + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t calc_icv(const uint8_t * T, + const uint8_t * userid, + unsigned int userid_len, + const uint8_t * black_key, + uint32_t key_length, uint8_t * hmac) +{ + fsl_shw_return_t code; + shw_hmac_state_t hmac_state; + + /* Load up T as key for the HMAC */ + code = shw_hmac_init(&hmac_state, T, T_LENGTH); + if (code != FSL_RETURN_OK_S) { + goto out; + } + + /* Previous step loaded key; Now set up to hash the data */ + + /* Input - start with ownerid */ + code = shw_hmac_update(&hmac_state, userid, userid_len); + if (code != FSL_RETURN_OK_S) { + goto out; + } + + /* Still input - Append black-key fields len, alg, key' */ + code = shw_hmac_update(&hmac_state, + (void *)black_key + LENGTH_OFFSET, + (LENGTH_LENGTH + + ALGORITHM_LENGTH + + FLAGS_LENGTH + key_length)); + if (code != FSL_RETURN_OK_S) { + goto out; + } + + /* Output - computed ICV/HMAC */ + code = shw_hmac_final(&hmac_state, hmac, ICV_LENGTH); + if (code != FSL_RETURN_OK_S) { + goto out; + } + + out: + + return code; +} /* calc_icv */ + +/*! + * Compute and return the KEK (Key Encryption Key) from the inputs + * + * @param userid The user's 'secret' for the key + * @param userid_len Length, in bytes of @c userid + * @param T The nonce + * @param[out] kek Location to store the computed KEK. It will + * be 21 bytes long. + * + * @return the usual error code + */ +static fsl_shw_return_t calc_kek(const uint8_t * userid, + unsigned int userid_len, + const uint8_t * T, uint8_t * kek) +{ + fsl_shw_return_t code = FSL_RETURN_INTERNAL_ERROR_S; + shw_hash_state_t hash_state; + + code = shw_hash_init(&hash_state, FSL_HASH_ALG_SHA256); + if (code != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Hash init failed: %s\n", fsl_error_string(code)); +#endif + goto out; + } + + code = shw_hash_update(&hash_state, T, T_LENGTH); + if (code != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Hash for T failed: %s\n", + fsl_error_string(code)); +#endif + goto out; + } + + code = shw_hash_update(&hash_state, userid, userid_len); + if (code != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Hash for userid failed: %s\n", + fsl_error_string(code)); +#endif + goto out; + } + + code = shw_hash_final(&hash_state, kek, KEK_LENGTH); + if (code != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not extract kek: %s\n", + fsl_error_string(code)); +#endif + goto out; + } + +#if KEK_LENGTH != 21 + { + uint8_t permuted_kek[21]; + + fsl_shw_permute1_bytes(kek, permuted_kek, KEK_LENGTH / 8); + memcpy(kek, permuted_kek, 21); + memset(permuted_kek, 0, sizeof(permuted_kek)); + } +#endif + +#ifdef DIAG_SECURITY_FUNC + dump("kek", kek, 21); +#endif + + out: + + return code; +} /* end fn calc_kek */ + +/*! + * Validate user's wrap key selection + * + * @param wrap_key The user's desired wrapping key + */ +static fsl_shw_return_t check_wrap_key(fsl_shw_pf_key_t wrap_key) +{ + /* unable to use desired key */ + fsl_shw_return_t ret = FSL_RETURN_NO_RESOURCE_S; + + if ((wrap_key != FSL_SHW_PF_KEY_IIM) && + (wrap_key != FSL_SHW_PF_KEY_RND) && + (wrap_key != FSL_SHW_PF_KEY_IIM_RND)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Invalid wrap_key in key wrap/unwrap attempt"); +#endif + goto out; + } + ret = FSL_RETURN_OK_S; + + out: + return ret; +} /* end fn check_wrap_key */ + +/*! + * Perform unwrapping of a black key into a RED slot + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be unwrapped... key length, slot info, etc. + * @param black_key Encrypted key + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t unwrap(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + const uint8_t * black_key) +{ + fsl_shw_return_t ret; + uint8_t hmac[ICV_LENGTH]; + uint8_t T[T_LENGTH]; + uint8_t kek[KEK_LENGTH + 20]; + int key_length = black_key[LENGTH_OFFSET]; + int rounded_key_length = ROUND_LENGTH(key_length); + uint8_t key[rounded_key_length]; + fsl_shw_sko_t t_key_info; + fsl_shw_scco_t t_key_ctx; + fsl_shw_sko_t kek_key_info; + fsl_shw_scco_t kek_ctx; + int unwrapping_sw_key = key_info->flags & FSL_SKO_KEY_SW_KEY; + int pk_needs_restoration = 0; /* bool */ + unsigned original_key_length = key_info->key_length; + int pk_was_held = 0; + uint8_t current_pk[21]; + di_return_t di_code; + + ret = check_wrap_key(user_ctx->wrap_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (black_key == NULL) { + ret = FSL_RETURN_ERROR_S; + goto out; + } +#ifdef DIAG_SECURITY_FUNC + dump("black", black_key, KEY_PRIME_OFFSET + key_length); +#endif + /* Validate SW flags to prevent misuse */ + if ((key_info->flags & FSL_SKO_KEY_SW_KEY) + && !(black_key[FLAGS_OFFSET] & FLAGS_SW_KEY)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Compute T = 3des-dec-ecb(wrap_key, T') */ + init_wrap_key(user_ctx->wrap_key, &t_key_info, &t_key_ctx); + ret = fsl_shw_symmetric_decrypt(user_ctx, &t_key_info, &t_key_ctx, + T_LENGTH, + black_key + T_PRIME_OFFSET, T); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Recovery of nonce (T) failed"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + /* Compute ICV = HMAC(T, ownerid | len | alg | flags | key' */ + ret = calc_icv(T, (uint8_t *) & key_info->userid, + sizeof(key_info->userid), + black_key, original_key_length, hmac); + + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Calculation of ICV failed"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Validating MAC of wrapped key"); +#endif + + /* Check computed ICV against value in Black Key */ + if (memcmp(black_key + ICV_OFFSET, hmac, ICV_LENGTH) != 0) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Computed ICV fails validation\n"); +#endif + ret = FSL_RETURN_AUTH_FAILED_S; + goto out; + } + + /* Compute KEK = SHA256(T | ownerid). */ + ret = calc_kek((uint8_t *) & key_info->userid, sizeof(key_info->userid), + T, kek); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (unwrapping_sw_key) { + di_code = dryice_get_programmed_key(current_pk, 8 * 21); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not save current PK: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + } + + /* + * "Establish" the KEK in the PK. If the PK was held and unwrapping a + * software key, then release it and try again, but remember that we need + * to leave it 'held' if we are unwrapping a software key. + * + * If the PK is held while we are unwrapping a key for the PK, then + * the user didn't call release, so gets an error. + */ + di_code = dryice_set_programmed_key(kek, 8 * 21, 0); + if ((di_code == DI_ERR_INUSE) && unwrapping_sw_key) { + /* Temporarily reprogram the PK out from under the user */ + pk_was_held = 1; + dryice_release_programmed_key(); + di_code = dryice_set_programmed_key(kek, 8 * 21, 0); + } + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not program KEK: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + + if (unwrapping_sw_key) { + pk_needs_restoration = 1; + } + dryice_release_programmed_key(); /* Because of previous 'set' */ + + /* Compute KEY = TDES-decrypt(KEK, KEY') */ + fsl_shw_sko_init_pf_key(&kek_key_info, FSL_KEY_ALG_TDES, + FSL_SHW_PF_KEY_PRG); + fsl_shw_sko_set_key_length(&kek_key_info, KEK_LENGTH); + + fsl_shw_scco_init(&kek_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_CBC); + fsl_shw_scco_set_flags(&kek_ctx, FSL_SYM_CTX_LOAD); + fsl_shw_scco_set_context(&kek_ctx, (uint8_t *) & key_info->userid); +#ifdef DIAG_SECURITY_FUNC + dump("KEY'", black_key + KEY_PRIME_OFFSET, rounded_key_length); +#endif + ret = fsl_shw_symmetric_decrypt(user_ctx, &kek_key_info, &kek_ctx, + rounded_key_length, + black_key + KEY_PRIME_OFFSET, key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } +#ifdef DIAG_SECURITY_FUNC + dump("KEY", key, original_key_length); +#endif + /* Now either put key into PK or into a slot */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + ret = load_slot(user_ctx, key_info, key); + } else { + /* + * Since we have just unwrapped a program key, it had + * to have been wrapped as a program key, so it must + * be 168 bytes long and permuted ... + */ + ret = dryice_set_programmed_key(key, 8 * key_length, 0); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + } + + out: + key_info->key_length = original_key_length; + + if (pk_needs_restoration) { + di_code = dryice_set_programmed_key(current_pk, 8 * 21, 0); + } + + if (!pk_was_held) { + dryice_release_programmed_key(); + } + + /* Erase tracks of confidential data */ + memset(T, 0, T_LENGTH); + memset(key, 0, rounded_key_length); + memset(current_pk, 0, sizeof(current_pk)); + memset(&t_key_info, 0, sizeof(t_key_info)); + memset(&t_key_ctx, 0, sizeof(t_key_ctx)); + memset(&kek_key_info, 0, sizeof(kek_key_info)); + memset(&kek_ctx, 0, sizeof(kek_ctx)); + memset(kek, 0, KEK_LENGTH); + + return ret; +} /* unwrap */ + +/*! + * Perform wrapping of a black key from a RED slot (or the PK register) + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be wrapped... key length, slot info, etc. + * @param black_key Place to store encrypted key + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t wrap(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * black_key) +{ + fsl_shw_return_t ret = FSL_RETURN_OK_S; + fsl_shw_sko_t t_key_info; /* for holding T */ + fsl_shw_scco_t t_key_ctx; + fsl_shw_sko_t kek_key_info; + fsl_shw_scco_t kek_ctx; + unsigned original_key_length = key_info->key_length; + unsigned rounded_key_length; + uint8_t T[T_LENGTH]; + uint8_t kek[KEK_LENGTH + 20]; + uint8_t *red_key = 0; + int red_key_malloced = 0; /* bool */ + int pk_was_held = 0; /* bool */ + uint8_t saved_pk[21]; + uint8_t pk_needs_restoration; /* bool */ + di_return_t di_code; + + ret = check_wrap_key(user_ctx->wrap_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (black_key == NULL) { + ret = FSL_RETURN_ERROR_S; + goto out; + } + + if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) { + if ((key_info->pf_key != FSL_SHW_PF_KEY_PRG) + && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG)) { + ret = FSL_RETURN_ERROR_S; + goto out; + } + } else { + if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) { + ret = FSL_RETURN_BAD_FLAG_S; /* not established! */ + goto out; + } + } + + black_key[ALGORITHM_OFFSET] = key_info->algorithm; + +#ifndef DO_REPEATABLE_WRAP + /* Compute T = RND() */ + ret = fsl_shw_get_random(user_ctx, T_LENGTH, T); + if (ret != FSL_RETURN_OK_S) { + goto out; + } +#else + memcpy(T, T_block, T_LENGTH); +#endif + + /* Compute KEK = SHA256(T | ownerid). */ + ret = calc_kek((uint8_t *) & key_info->userid, sizeof(key_info->userid), + T, kek); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Calculation of KEK failed\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + rounded_key_length = ROUND_LENGTH(original_key_length); + + di_code = dryice_get_programmed_key(saved_pk, 8 * 21); + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not save current PK: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + + /* + * Load KEK into DI PKR. Note that we are NOT permuting it before loading, + * so we are using it as though it is a 168-bit key ready for the SCC. + */ + di_code = dryice_set_programmed_key(kek, 8 * 21, 0); + if (di_code == DI_ERR_INUSE) { + /* Temporarily reprogram the PK out from under the user */ + pk_was_held = 1; + dryice_release_programmed_key(); + di_code = dryice_set_programmed_key(kek, 8 * 21, 0); + } + if (di_code != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("Could not program KEK: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + pk_needs_restoration = 1; + dryice_release_programmed_key(); + + /* Find red key */ + if (key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY) { + black_key[LENGTH_OFFSET] = 21; + rounded_key_length = 24; + + red_key = saved_pk; + } else { + black_key[LENGTH_OFFSET] = key_info->key_length; + + red_key = os_alloc_memory(key_info->key_length, 0); + if (red_key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + red_key_malloced = 1; + + ret = fsl_shw_read_key(user_ctx, key_info, red_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + } + +#ifdef DIAG_SECURITY_FUNC + dump("KEY", red_key, black_key[LENGTH_OFFSET]); +#endif + /* Compute KEY' = TDES-encrypt(KEK, KEY) */ + fsl_shw_sko_init_pf_key(&kek_key_info, FSL_KEY_ALG_TDES, + FSL_SHW_PF_KEY_PRG); + fsl_shw_sko_set_key_length(&kek_key_info, KEK_LENGTH); + + fsl_shw_scco_init(&kek_ctx, FSL_KEY_ALG_TDES, FSL_SYM_MODE_CBC); + fsl_shw_scco_set_flags(&kek_ctx, FSL_SYM_CTX_LOAD); + fsl_shw_scco_set_context(&kek_ctx, (uint8_t *) & key_info->userid); + ret = fsl_shw_symmetric_encrypt(user_ctx, &kek_key_info, &kek_ctx, + rounded_key_length, + red_key, black_key + KEY_PRIME_OFFSET); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Encryption of KEY failed\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + /* Set up flags info */ + black_key[FLAGS_OFFSET] = 0; + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + black_key[FLAGS_OFFSET] |= FLAGS_SW_KEY; + } +#ifdef DIAG_SECURITY_FUNC + dump("KEY'", black_key + KEY_PRIME_OFFSET, rounded_key_length); +#endif + /* Compute and store ICV into Black Key */ + ret = calc_icv(T, + (uint8_t *) & key_info->userid, + sizeof(key_info->userid), + black_key, original_key_length, black_key + ICV_OFFSET); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Calculation of ICV failed\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + /* Compute T' = 3des-enc-ecb(wrap_key, T); Result goes to Black Key */ + init_wrap_key(user_ctx->wrap_key, &t_key_info, &t_key_ctx); + ret = fsl_shw_symmetric_encrypt(user_ctx, &t_key_info, &t_key_ctx, + T_LENGTH, + T, black_key + T_PRIME_OFFSET); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Encryption of nonce failed"); +#endif + goto out; + } +#ifdef DIAG_SECURITY_FUNC + dump("black", black_key, KEY_PRIME_OFFSET + black_key[LENGTH_OFFSET]); +#endif + + out: + if (pk_needs_restoration) { + dryice_set_programmed_key(saved_pk, 8 * 21, 0); + } + + if (!pk_was_held) { + dryice_release_programmed_key(); + } + + if (red_key_malloced) { + memset(red_key, 0, key_info->key_length); + os_free_memory(red_key); + } + + key_info->key_length = original_key_length; + + /* Erase tracks of confidential data */ + memset(T, 0, T_LENGTH); + memset(&t_key_info, 0, sizeof(t_key_info)); + memset(&t_key_ctx, 0, sizeof(t_key_ctx)); + memset(&kek_key_info, 0, sizeof(kek_key_info)); + memset(&kek_ctx, 0, sizeof(kek_ctx)); + memset(kek, 0, sizeof(kek)); + memset(saved_pk, 0, sizeof(saved_pk)); + + return ret; +} /* wrap */ + +static fsl_shw_return_t create(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + unsigned key_length = key_info->key_length; + di_return_t di_code; + + if (!(key_info->flags & FSL_SKO_KEY_SW_KEY)) { + /* Must be creating key for PK */ + if ((key_info->algorithm != FSL_KEY_ALG_TDES) || + ((key_info->key_length != 16) + && (key_info->key_length != 21) /* permuted 168-bit key */ + &&(key_info->key_length != 24))) { + ret = FSL_RETURN_ERROR_S; + goto out; + } + + key_length = 21; /* 168-bit PK */ + } + + /* operational block */ + { + uint8_t key_value[key_length]; + +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creating random key\n"); +#endif + ret = fsl_shw_get_random(user_ctx, key_length, key_value); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("get_random for CREATE KEY failed\n"); +#endif + goto out; + } + + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + ret = load_slot(user_ctx, key_info, key_value); + } else { + di_code = + dryice_set_programmed_key(key_value, 8 * key_length, + 0); + if (di_code != 0) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("di set_pk failed: %s\n", + di_error_string(di_code)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + ret = FSL_RETURN_OK_S; + } + memset(key_value, 0, key_length); + } /* end operational block */ + +#ifdef DIAG_SECURITY_FUNC + if (ret != FSL_RETURN_OK_S) { + LOG_DIAG("Loading random key failed"); + } +#endif + + out: + + return ret; +} /* end fn create */ + +static fsl_shw_return_t accept(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, const uint8_t * key) +{ + uint8_t permuted_key[21]; + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + if (key == NULL) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("ACCEPT: Red Key is NULL"); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } +#ifdef DIAG_SECURITY_FUNC + dump("red", key, key_info->key_length); +#endif + /* Only SW keys go into the keystore */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + + /* Copy in safe number of bytes of Red key */ + ret = load_slot(user_ctx, key_info, key); + } else { /* not SW key */ + di_return_t di_ret; + + /* Only 3DES PGM key types can be established */ + if (((key_info->pf_key != FSL_SHW_PF_KEY_PRG) + && (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG)) + || (key_info->algorithm != FSL_KEY_ALG_TDES)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS + ("ACCEPT: Failed trying to establish non-PRG" + " or invalid 3DES Key: iim%d, iim_prg%d, alg%d\n", + (key_info->pf_key != FSL_SHW_PF_KEY_PRG), + (key_info->pf_key != FSL_SHW_PF_KEY_IIM_PRG), + (key_info->algorithm != FSL_KEY_ALG_TDES)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + if ((key_info->key_length != 16) + && (key_info->key_length != 21) + && (key_info->key_length != 24)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("ACCEPT: Failed trying to establish" + " invalid 3DES Key: len=%d (%d)\n", + key_info->key_length, + ((key_info->key_length != 16) + && (key_info->key_length != 21) + && (key_info->key_length != 24))); +#endif + ret = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } + + /* Convert key into 168-bit value and put it into PK */ + if (key_info->key_length != 21) { + fsl_shw_permute1_bytes(key, permuted_key, + key_info->key_length / 8); + di_ret = + dryice_set_programmed_key(permuted_key, 168, 0); + } else { + /* Already permuted ! */ + di_ret = dryice_set_programmed_key(key, 168, 0); + } + if (di_ret != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS + ("ACCEPT: DryIce error setting Program Key: %s", + di_error_string(di_ret)); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + } + + ret = FSL_RETURN_OK_S; + + out: + memset(permuted_key, 0, 21); + + return ret; +} /* end fn accept */ + +/*! + * Place a key into a protected location for use only by cryptographic + * algorithms. + * + * This only needs to be used to a) unwrap a key, or b) set up a key which + * could be wrapped by calling #fsl_shw_extract_key() at some later time). + * + * The protected key will not be available for use until this operation + * successfully completes. + * + * @bug This whole discussion needs review. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be established. In the create case, the key + * length must be set. + * @param establish_type How @a key will be interpreted to establish a + * key for use. + * @param key If @a establish_type is #FSL_KEY_WRAP_UNWRAP, + * this is the location of a wrapped key. If + * @a establish_type is #FSL_KEY_WRAP_CREATE, this + * parameter can be @a NULL. If @a establish_type + * is #FSL_KEY_WRAP_ACCEPT, this is the location + * of a plaintext key. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + unsigned original_key_length = key_info->key_length; + unsigned rounded_key_length; + unsigned slot_allocated = 0; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("%s: Non-blocking call not supported\n", + __FUNCTION__); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* + HW keys are always 'established', but otherwise do not allow user + * to establish over the top of an established key. + */ + if ((key_info->flags & FSL_SKO_KEY_ESTABLISHED) + && !(key_info->flags & FSL_SKO_KEY_SELECT_PF_KEY)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("%s: Key already established\n", __FUNCTION__); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* @bug VALIDATE KEY flags here -- SW or PRG/IIM_PRG */ + + /* Write operations into SCC memory require word-multiple number of + * bytes. For ACCEPT and CREATE functions, the key length may need + * to be rounded up. Calculate. */ + if (LENGTH_PATCH && (original_key_length & LENGTH_PATCH_MASK) != 0) { + rounded_key_length = original_key_length + LENGTH_PATCH + - (original_key_length & LENGTH_PATCH_MASK); + } else { + rounded_key_length = original_key_length; + } + + /* SW keys need a place to live */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + ret = alloc_slot(user_ctx, key_info); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Slot allocation failed\n"); +#endif + goto out; + } + slot_allocated = 1; + } + + switch (establish_type) { + case FSL_KEY_WRAP_CREATE: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creating random key\n"); +#endif + ret = create(user_ctx, key_info); + break; + + case FSL_KEY_WRAP_ACCEPT: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Accepting plaintext key\n"); +#endif + ret = accept(user_ctx, key_info, key); + break; + + case FSL_KEY_WRAP_UNWRAP: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Unwrapping wrapped key\n"); +#endif + ret = unwrap(user_ctx, key_info, key); + break; + + default: + ret = FSL_RETURN_BAD_FLAG_S; + break; + } /* switch */ + + out: + if (ret != FSL_RETURN_OK_S) { + if (slot_allocated) { + (void)dealloc_slot(user_ctx, key_info); + } + key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED; + } else { + key_info->flags |= FSL_SKO_KEY_ESTABLISHED; + } + + return ret; +} /* end fn fsl_shw_establish_key */ + +/*! + * Wrap a key and retrieve the wrapped value. + * + * A wrapped key is a key that has been cryptographically obscured. It is + * only able to be used with #fsl_shw_establish_key(). + * + * This function will also release a software key (see #fsl_shw_release_key()) + * so it must be re-established before reuse. This is not true of PGM keys. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * @param[out] covered_key The location to store the 48-octet wrapped key. + * (This size is based upon the maximum key size + * of 32 octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Wrapping a key\n"); +#endif + + if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("%s: Key not established\n", __FUNCTION__); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + /* Verify that a SW key info really belongs to a SW key */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + /* ret = FSL_RETURN_BAD_FLAG_S; + goto out;*/ + } + + ret = wrap(user_ctx, key_info, covered_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + /* Need to deallocate on successful extraction */ + (void)dealloc_slot(user_ctx, key_info); + /* Mark key not available in the flags */ + key_info->flags &= + ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT); + memset(key_info->key, 0, sizeof(key_info->key)); + } + + out: + return ret; +} /* end fn fsl_shw_extract_key */ + +/*! + * De-establish a key so that it can no longer be accessed. + * + * The key will need to be re-established before it can again be used. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Not in blocking mode\n"); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Releasing a key\n"); +#endif + + if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Key not established\n"); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + (void)dealloc_slot(user_ctx, key_info); + /* Turn off 'established' flag */ +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("dealloc_slot() called\n"); +#endif + key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED; + ret = FSL_RETURN_OK_S; + goto out; + } + + if ((key_info->pf_key == FSL_SHW_PF_KEY_PRG) + || (key_info->pf_key == FSL_SHW_PF_KEY_IIM_PRG)) { + di_return_t di_ret; + + di_ret = dryice_release_programmed_key(); + if (di_ret != DI_SUCCESS) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS + ("dryice_release_programmed_key() failed: %d\n", + di_ret); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + } else { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Neither SW nor HW key\n"); +#endif + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + ret = FSL_RETURN_OK_S; + + out: + return ret; +} /* end fn fsl_shw_release_key */ + +fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * key) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + + /* Only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + printk("Reading a key\n"); +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Reading a key"); +#endif + if (key_info->flags & FSL_SKO_KEY_PRESENT) { + memcpy(key_info->key, key, key_info->key_length); + ret = FSL_RETURN_OK_S; + } else if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + printk("key established\n"); + if (key_info->keystore == NULL) { + printk("keystore is null\n"); + /* First verify that the key access is valid */ + ret = + system_keystore.slot_verify_access(system_keystore. + user_data, + key_info->userid, + key_info-> + handle); + + printk("key in system keystore\n"); + + /* Key is in system keystore */ + ret = keystore_slot_read(&system_keystore, + key_info->userid, + key_info->handle, + key_info->key_length, key); + } else { + printk("key goes in user keystore.\n"); + /* Key goes in user keystore */ + ret = keystore_slot_read(key_info->keystore, + key_info->userid, + key_info->handle, + key_info->key_length, key); + } + } + + out: + return ret; +} /* end fn fsl_shw_read_key */ + +#else /* __KERNEL__ && DRYICE */ + +/* User mode -- these functions are unsupported */ + +fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key) +{ + (void)user_ctx; + (void)key_info; + (void)establish_type; + (void)key; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key) +{ + (void)user_ctx; + (void)key_info; + (void)covered_key; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + (void)user_ctx; + (void)key_info; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * key) +{ + (void)user_ctx; + (void)key_info; + (void)key; + + return FSL_RETURN_NO_RESOURCE_S; +} + +#endif /* __KERNEL__ && DRYICE */ diff --git a/drivers/mxc/security/rng/include/rng_driver.h b/drivers/mxc/security/rng/include/rng_driver.h new file mode 100644 index 000000000000..e760a14f2ded --- /dev/null +++ b/drivers/mxc/security/rng/include/rng_driver.h @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef RNG_DRIVER_H +#define RNG_DRIVER_H + +#include "shw_driver.h" + +/* This is a Linux flag meaning 'compiling kernel code'... */ +#ifndef __KERNEL__ +#include +#include +#include +#else +#include "../../sahara2/include/portable_os.h" +#endif + +#include "../../sahara2/include/fsl_platform.h" + +/*! @file rng_driver.h + * + * @brief Header file to use the RNG driver. + * + * @ingroup RNG + */ + +#if defined(FSL_HAVE_RNGA) + +#include "rng_rnga.h" + +#elif defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC) + +#include "rng_rngc.h" + +#else /* neither RNGA, RNGB, nor RNGC */ + +#error NO_RNG_TYPE_IDENTIFIED + +#endif + +/***************************************************************************** + * Enumerations + *****************************************************************************/ + +/*! Values from Version ID register */ +enum rng_type { + /*! Type RNGA. */ + RNG_TYPE_RNGA = 0, + /*! Type RNGB. */ + RNG_TYPE_RNGB = 1, + /*! Type RNGC */ + RNG_TYPE_RNGC = 2 +}; + +/*! + * Return values (error codes) for kernel register interface functions + */ +typedef enum rng_return { + RNG_RET_OK = 0, /*!< Function succeeded */ + RNG_RET_FAIL /*!< Non-specific failure */ +} rng_return_t; + +/***************************************************************************** + * Data Structures + *****************************************************************************/ +/*! + * An entry in the RNG Work Queue. Based upon standard SHW queue entry. + * + * This entry also gets saved (for non-blocking requests) in the user's result + * pool. When the user picks up the request, the final processing (copy from + * data_local to data_user) will get made if status was good. + */ +typedef struct rng_work_entry { + struct shw_queue_entry_t hdr; /*!< Standards SHW queue info. */ + uint32_t length; /*!< Number of bytes still needed to satisfy request. */ + uint32_t *data_local; /*!< Where data from RNG FIFO gets placed. */ + uint8_t *data_user; /*!< Ultimate target of data. */ + unsigned completed; /*!< Non-zero if job is done. */ +} rng_work_entry_t; + +/***************************************************************************** + * Function Prototypes + *****************************************************************************/ + +#ifdef RNG_REGISTER_PEEK_POKE +/*! + * Read value from an RNG register. + * The offset will be checked for validity as well as whether it is + * accessible at the time of the call. + * + * This routine cannot be used to read the RNG's Output FIFO if the RNG is in + * High Assurance mode. + * + * @param[in] register_offset The (byte) offset within the RNG block + * of the register to be queried. See + * RNG(A, C) registers for meanings. + * @param[out] value Pointer to where value from the register + * should be placed. + * + * @return See #rng_return_t. + */ +/* REQ-FSLSHW-PINTFC-API-LLF-001 */ +extern rng_return_t rng_read_register(uint32_t register_offset, + uint32_t * value); + +/*! + * Write a new value into an RNG register. + * + * The offset will be checked for validity as well as whether it is + * accessible at the time of the call. + * + * @param[in] register_offset The (byte) offset within the RNG block + * of the register to be modified. See + * RNG(A, C) registers for meanings. + * @param[in] value The value to store into the register. + * + * @return See #rng_return_t. + */ +/* REQ-FSLSHW-PINTFC-API-LLF-002 */ +extern rng_return_t rng_write_register(uint32_t register_offset, + uint32_t value); +#endif /* RNG_REGISTER_PEEK_POKE */ + +#endif /* RNG_DRIVER_H */ diff --git a/drivers/mxc/security/rng/include/rng_internals.h b/drivers/mxc/security/rng/include/rng_internals.h new file mode 100644 index 000000000000..9f754a77e766 --- /dev/null +++ b/drivers/mxc/security/rng/include/rng_internals.h @@ -0,0 +1,680 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef RNG_INTERNALS_H +#define RNG_INTERNALS_H + +/*! @file rng_internals.h + * + * This file contains definitions which are internal to the RNG driver. + * + * This header file should only ever be needed by rng_driver.c + * + * Compile-time flags minimally needed: + * + * @li Some sort of platform flag. (FSL_HAVE_RNGA or FSL_HAVE_RNGC) + * + * @ingroup RNG + */ + +#include "portable_os.h" +#include "shw_driver.h" +#include "rng_driver.h" + +/*! @defgroup rngcompileflags RNG Compile Flags + * + * These are flags which are used to configure the RNG driver at compilation + * time. + * + * Most of them default to good values for normal operation, but some + * (#INT_RNG and #RNG_BASE_ADDR) need to be provided. + * + * The terms 'defined' and 'undefined' refer to whether a @c \#define (or -D on + * a compile command) has defined a given preprocessor symbol. If a given + * symbol is defined, then @c \#ifdef \ will succeed. Some symbols + * described below default to not having a definition, i.e. they are undefined. + * + */ + +/*! @addtogroup rngcompileflags */ +/*! @{ */ + +/*! + * This is the maximum number of times the driver will loop waiting for the + * RNG hardware to say that it has generated random data. It prevents the + * driver from stalling forever should there be a hardware problem. + * + * Default value is 100. It should be revisited as CPU clocks speed up. + */ +#ifndef RNG_MAX_TRIES +#define RNG_MAX_TRIES 100 +#endif + +/* Temporarily define compile-time flags to make Doxygen happy and allow them + to get into the documentation. */ +#ifdef DOXYGEN_HACK + +/*! + * This symbol is the base address of the RNG in the CPU memory map. It may + * come from some included header file, or it may come from the compile command + * line. This symbol has no default, and the driver will not compile without + * it. + */ +#define RNG_BASE_ADDR +#undef RNG_BASE_ADDR + +/*! + * This symbol is the Interrupt Number of the RNG in the CPU. It may come + * from some included header file, or it may come from the compile command + * line. This symbol has no default, and the driver will not compile without + * it. + */ +#define INT_RNG +#undef INT_RNG + +/*! + * Defining this symbol will allow other kernel programs to call the + * #rng_read_register() and #rng_write_register() functions. If this symbol is + * not defined, those functions will not be present in the driver. + */ +#define RNG_REGISTER_PEEK_POKE +#undef RNG_REGISTER_PEEK_POKE + +/*! + * Turn on compilation of run-time operational, debug, and error messages. + * + * This flag is undefined by default. + */ +/* REQ-FSLSHW-DEBUG-001 */ + +/*! + * Turn on compilation of run-time logging of access to the RNG registers, + * except for the RNG's Output FIFO register. See #RNG_ENTROPY_DEBUG. + * + * This flag is undefined by default + */ +#define RNG_REGISTER_DEBUG +#undef RNG_REGISTER_DEBUG + +/*! + * Turn on compilation of run-time logging of reading of the RNG's Output FIFO + * register. This flag does nothing if #RNG_REGISTER_DEBUG is not defined. + * + * This flag is undefined by default + */ +#define RNG_ENTROPY_DEBUG +#undef RNG_ENTROPY_DEBUG + +/*! + * If this flag is defined, the driver will not attempt to put the RNG into + * High Assurance mode. + + * If it is undefined, the driver will attempt to put the RNG into High + * Assurance mode. If RNG fails to go into High Assurance mode, the driver + * will fail to initialize. + + * In either case, if the RNG is already in this mode, the driver will operate + * normally. + * + * This flag is undefined by default. + */ +#define RNG_NO_FORCE_HIGH_ASSURANCE +#undef RNG_NO_FORCE_HIGH_ASSURANCE + +/*! + * If this flag is defined, the driver will put the RNG into low power mode + * every opportunity. + * + * This flag is undefined by default. + */ +#define RNG_USE_LOW_POWER_MODE +#undef RNG_USE_LOW_POWER_MODE + +/*! @} */ +#endif /* end DOXYGEN_HACK */ + +/*! + * If this flag is defined, the driver will not attempt to put the RNG into + * High Assurance mode. + + * If it is undefined, the driver will attempt to put the RNG into High + * Assurance mode. If RNG fails to go into High Assurance mode, the driver + * will fail to initialize. + + * In either case, if the RNG is already in this mode, the driver will operate + * normally. + * + */ +#define RNG_NO_FORCE_HIGH_ASSURANCE + +/*! + * Read a 32-bit value from an RNG register. This macro depends upon + * #rng_base. The os_read32() macro operates on 32-bit quantities, as do + * all RNG register reads. + * + * @param offset Register byte offset within RNG. + * + * @return The value from the RNG's register. + */ +#ifndef RNG_REGISTER_DEBUG +#define RNG_READ_REGISTER(offset) os_read32(rng_base+(offset)) +#else +#define RNG_READ_REGISTER(offset) dbg_rng_read_register(offset) +#endif + +/*! + * Write a 32-bit value to an RNG register. This macro depends upon + * #rng_base. The os_write32() macro operates on 32-bit quantities, as do + * all RNG register writes. + * + * @param offset Register byte offset within RNG. + * @param value 32-bit value to store into the register + * + * @return (void) + */ +#ifndef RNG_REGISTER_DEBUG +#define RNG_WRITE_REGISTER(offset,value) \ + (void)os_write32(rng_base+(offset), value) +#else +#define RNG_WRITE_REGISTER(offset,value) dbg_rng_write_register(offset,value) +#endif + +#ifndef RNG_DRIVER_NAME +/*! @addtogroup rngcompileflags */ +/*! @{ */ +/*! Name the driver will use to register itself to the kernel as the driver. */ +#define RNG_DRIVER_NAME "rng" +/*! @} */ +#endif + +/*! + * Calculate number of words needed to hold the given number of bytes. + * + * @param byte_count Number of bytes + * + * @return Number of words + */ +#define BYTES_TO_WORDS(byte_count) \ + (((byte_count)+sizeof(uint32_t)-1)/sizeof(uint32_t)) + +/*! Gives high-level view of state of the RNG */ +typedef enum rng_status { + RNG_STATUS_INITIAL, /*!< Driver status before ever starting. */ + RNG_STATUS_CHECKING, /*!< During driver initialization. */ + RNG_STATUS_UNIMPLEMENTED, /*!< Hardware is non-existent / unreachable. */ + RNG_STATUS_OK, /*!< Hardware is In Secure or Default state. */ + RNG_STATUS_FAILED /*!< Hardware is In Failed state / other fatal + problem. Driver is still able to read/write + some registers, but cannot get Random + data. */ +} rng_status_t; + +static shw_queue_t rng_work_queue; + +/***************************************************************************** + * + * Function Declarations + * + *****************************************************************************/ + +/* kernel interface functions */ +OS_DEV_INIT_DCL(rng_init); +OS_DEV_TASK_DCL(rng_entropy_task); +OS_DEV_SHUTDOWN_DCL(rng_shutdown); +OS_DEV_ISR_DCL(rng_irq); + +#define RNG_ADD_QUEUE_ENTRY(pool, entry) \ + SHW_ADD_QUEUE_ENTRY(pool, (shw_queue_entry_t*)entry) + +#define RNG_REMOVE_QUEUE_ENTRY(pool, entry) \ + SHW_REMOVE_QUEUE_ENTRY(pool, (shw_queue_entry_t*)entry) +#define RNG_GET_WORK_ENTRY() \ + (rng_work_entry_t*)SHW_POP_FIRST_ENTRY(&rng_work_queue) + +/*! + * Add an work item to a work list. Item will be marked incomplete. + * + * @param work Work entry to place at tail of list. + * + * @return none + */ +inline static void RNG_ADD_WORK_ENTRY(rng_work_entry_t * work) +{ + work->completed = FALSE; + + SHW_ADD_QUEUE_ENTRY(&rng_work_queue, (shw_queue_entry_t *) work); + + os_dev_schedule_task(rng_entropy_task); +} + +/*! + * For #rng_check_register_accessible(), check read permission on given + * register. + */ +#define RNG_CHECK_READ 0 + +/*! + * For #rng_check_register_accessible(), check write permission on given + * register. + */ +#define RNG_CHECK_WRITE 1 + +/* Define different helper symbols based on RNG type */ +#ifdef FSL_HAVE_RNGA + +/****************************************************************************** + * + * RNGA support + * + *****************************************************************************/ + +/*! Interrupt number for driver. */ +#if defined(MXC_INT_RNG) +/* Most modern definition */ +#define INT_RNG MXC_INT_RNG +#elif defined(MXC_INT_RNGA) +#define INT_RNG MXC_INT_RNGA +#else +#define INT_RNG INT_RNGA +#endif + +/*! Base (bus?) address of RNG component. */ +#define RNG_BASE_ADDR RNGA_BASE_ADDR + +/*! Read and return the status register. */ +#define RNG_GET_STATUS() \ + RNG_READ_REGISTER(RNGA_STATUS) +/*! Configure RNG for Auto seeding */ +#define RNG_AUTO_SEED() +/* Put RNG for Seed Generation */ +#define RNG_SEED_GEN() +/*! + * Return RNG Type value. Should be RNG_TYPE_RNGA, RNG_TYPE_RNGB, + * or RNG_TYPE_RNGC. + */ +#define RNG_GET_RNG_TYPE() \ + ((RNG_READ_REGISTER(RNGA_CONTROL) & RNGA_CONTROL_RNG_TYPE_MASK) \ + >> RNGA_CONTROL_RNG_TYPE_SHIFT) + +/*! + * Verify Type value of RNG. + * + * Returns true of OK, false if not. + */ +#define RNG_VERIFY_TYPE(type) \ + ((type) == RNG_TYPE_RNGA) + +/*! Returns non-zero if RNG device is reporting an error. */ +#define RNG_HAS_ERROR() \ + (RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_ERROR_INTERRUPT) +/*! Returns non-zero if Bad Key is selected */ +#define RNG_HAS_BAD_KEY() 0 +/*! Return non-zero if Self Test Done */ +#define RNG_SELF_TEST_DONE() 0 +/*! Returns non-zero if RNG ring oscillators have failed. */ +#define RNG_OSCILLATOR_FAILED() \ + (RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OSCILLATOR_DEAD) + +/*! Returns maximum number of 32-bit words in the RNG's output fifo. */ +#define RNG_GET_FIFO_SIZE() \ + ((RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OUTPUT_FIFO_SIZE_MASK) \ + >> RNGA_STATUS_OUTPUT_FIFO_SIZE_SHIFT) + +/*! Returns number of 32-bit words currently in the RNG's output fifo. */ +#define RNG_GET_WORDS_IN_FIFO() \ + ((RNG_READ_REGISTER(RNGA_STATUS) & RNGA_STATUS_OUTPUT_FIFO_LEVEL_MASK) \ + >> RNGA_STATUS_OUTPUT_FIFO_LEVEL_SHIFT) +/* Configuring RNG for Self Test */ +#define RNG_SELF_TEST() +/*! Get a random value from the RNG's output FIFO. */ +#define RNG_READ_FIFO() \ + RNG_READ_REGISTER(RNGA_OUTPUT_FIFO) + +/*! Put entropy into the RNG's algorithm. + * @param value 32-bit value to add to RNG's entropy. + **/ +#define RNG_ADD_ENTROPY(value) \ + RNG_WRITE_REGISTER(RNGA_ENTROPY, (value)) +/*! Return non-zero in case of Error during Self Test */ +#define RNG_CHECK_SELF_ERR() 0 +/*! Return non-zero in case of Error during Seed Generation */ +#define RNG_CHECK_SEED_ERR() 0 +/*! Get the RNG started at generating output. */ +#define RNG_GO() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_GO); \ +} +/*! To clear all Error Bits in Error Status Register */ +#define RNG_CLEAR_ERR() +/*! Put RNG into High Assurance mode */ +#define RNG_SET_HIGH_ASSURANCE() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_HIGH_ASSURANCE); \ +} + +/*! Return non-zero if the RNG is in High Assurance mode. */ +#define RNG_GET_HIGH_ASSURANCE() \ + (RNG_READ_REGISTER(RNGA_CONTROL) & RNGA_CONTROL_HIGH_ASSURANCE) + +/*! Clear all status, error and otherwise. */ +#define RNG_CLEAR_ALL_STATUS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_CLEAR_INTERRUPT); \ +} +/* Return non-zero if RESEED Required */ +#define RNG_RESEED() 1 + +/*! Return non-zero if Seeding is done */ +#define RNG_SEED_DONE() 1 + +/*! Return non-zero if everything seems OK with the RNG. */ +#define RNG_WORKING() \ + ((RNG_READ_REGISTER(RNGA_STATUS) \ + & (RNGA_STATUS_SLEEP | RNGA_STATUS_SECURITY_VIOLATION \ + | RNGA_STATUS_ERROR_INTERRUPT | RNGA_STATUS_FIFO_UNDERFLOW \ + | RNGA_STATUS_LAST_READ_STATUS )) == 0) + +/*! Put the RNG into sleep (low-power) mode. */ +#define RNG_SLEEP() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_SLEEP); \ +} + +/*! Wake the RNG from sleep (low-power) mode. */ +#define RNG_WAKE() \ +{ \ + uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control & ~RNGA_CONTROL_SLEEP); \ +} + +/*! Mask interrupts so that the driver/OS will not see them. */ +#define RNG_MASK_ALL_INTERRUPTS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control | RNGA_CONTROL_MASK_INTERRUPTS); \ +} + +/*! Unmask interrupts so that the driver/OS will see them. */ +#define RNG_UNMASK_ALL_INTERRUPTS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGA_CONTROL); \ + RNG_WRITE_REGISTER(RNGA_CONTROL, control & ~RNGA_CONTROL_MASK_INTERRUPTS);\ +} + +/*! + * @def RNG_PUT_RNG_TO_SLEEP() + * + * If compiled with #RNG_USE_LOW_POWER_MODE, this routine will put the RNG + * to sleep (low power mode). + * + * @return none + */ +/*! + * @def RNG_WAKE_RNG_FROM_SLEEP() + * + * If compiled with #RNG_USE_LOW_POWER_MODE, this routine will wake the RNG + * from sleep (low power mode). + * + * @return none + */ +#ifdef RNG_USE_LOW_POWER_MODE + +#define RNG_PUT_RNG_TO_SLEEP() \ + RNG_SLEEP() + +#define RNG_WAKE_FROM_SLEEP() \ + RNG_WAKE() 1 + +#else /* not low power mode */ + +#define RNG_PUT_RNG_TO_SLEEP() + +#define RNG_WAKE_FROM_SLEEP() + +#endif /* Use low-power mode */ + +#else /* FSL_HAVE_RNGB or FSL_HAVE_RNGC */ + +/****************************************************************************** + * + * RNGB and RNGC support + * + *****************************************************************************/ +/* + * The operational interfaces for RNGB and RNGC are almost identical, so + * the defines for RNGC work fine for both. There are minor differences + * which will be treated within this conditional block. + */ + +/*! Interrupt number for driver. */ +#if defined(MXC_INT_RNG) +/* Most modern definition */ +#define INT_RNG MXC_INT_RNG +#elif defined(MXC_INT_RNGC) +#define INT_RNG MXC_INT_RNGC +#elif defined(MXC_INT_RNGB) +#define INT_RNG MXC_INT_RNGB +#elif defined(INT_RNGC) +#define INT_RNG INT_RNGC +#else +#error NO_INTERRUPT_DEFINED +#endif + +/*! Base address of RNG component. */ +#ifdef FSL_HAVE_RNGB +#define RNG_BASE_ADDR RNGB_BASE_ADDR +#else +#define RNG_BASE_ADDR RNGC_BASE_ADDR +#endif + +/*! Read and return the status register. */ +#define RNG_GET_STATUS() \ + RNG_READ_REGISTER(RNGC_ERROR) + +/*! + * Return RNG Type value. Should be RNG_TYPE_RNGA or RNG_TYPE_RNGC. + */ +#define RNG_GET_RNG_TYPE() \ + ((RNG_READ_REGISTER(RNGC_VERSION_ID) & RNGC_VERID_RNG_TYPE_MASK) \ + >> RNGC_VERID_RNG_TYPE_SHIFT) + +/*! + * Verify Type value of RNG. + * + * Returns true of OK, false if not. + */ +#ifdef FSL_HAVE_RNGB +#define RNG_VERIFY_TYPE(type) \ + ((type) == RNG_TYPE_RNGB) +#else /* RNGC */ +#define RNG_VERIFY_TYPE(type) \ + ((type) == RNG_TYPE_RNGC) +#endif + +/*! Returns non-zero if RNG device is reporting an error. */ +#define RNG_HAS_ERROR() \ + (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_ERROR) +/*! Returns non-zero if Bad Key is selected */ +#define RNG_HAS_BAD_KEY() \ + (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_BAD_KEY) +/*! Returns non-zero if RNG ring oscillators have failed. */ +#define RNG_OSCILLATOR_FAILED() \ + (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_OSC_ERR) + +/*! Returns maximum number of 32-bit words in the RNG's output fifo. */ +#define RNG_GET_FIFO_SIZE() \ + ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_FIFO_SIZE_MASK) \ + >> RNGC_STATUS_FIFO_SIZE_SHIFT) + +/*! Returns number of 32-bit words currently in the RNG's output fifo. */ +#define RNG_GET_WORDS_IN_FIFO() \ + ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_FIFO_LEVEL_MASK) \ + >> RNGC_STATUS_FIFO_LEVEL_SHIFT) + +/*! Get a random value from the RNG's output FIFO. */ +#define RNG_READ_FIFO() \ + RNG_READ_REGISTER(RNGC_FIFO) + +/*! Put entropy into the RNG's algorithm. + * @param value 32-bit value to add to RNG's entropy. + **/ +#ifdef FSL_HAVE_RNGB +#define RNG_ADD_ENTROPY(value) \ + RNG_WRITE_REGISTER(RNGB_ENTROPY, value) +#else /* RNGC does not have Entropy register */ +#define RNG_ADD_ENTROPY(value) +#endif +/*! Wake the RNG from sleep (low-power) mode. */ +#define RNG_WAKE() 1 +/*! Get the RNG started at generating output. */ +#define RNG_GO() +/*! Put RNG into High Assurance mode. */ +#define RNG_SET_HIGH_ASSURANCE() +/*! Returns non-zero in case of Error during Self Test */ +#define RNG_CHECK_SELF_ERR() \ + (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_ST_ERR) +/*! Return non-zero in case of Error during Seed Generation */ +#define RNG_CHECK_SEED_ERR() \ + (RNG_READ_REGISTER(RNGC_ERROR) & RNGC_ERROR_STATUS_STAT_ERR) + +/*! Configure RNG for Self Test */ +#define RNG_SELF_TEST() \ +{ \ + register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND); \ + RNG_WRITE_REGISTER(RNGC_COMMAND, command \ + | RNGC_COMMAND_SELF_TEST); \ +} +/*! Clearing the Error bits in Error Status Register */ +#define RNG_CLEAR_ERR() \ +{ \ + register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND); \ + RNG_WRITE_REGISTER(RNGC_COMMAND, command \ + | RNGC_COMMAND_CLEAR_ERROR); \ +} + +/*! Return non-zero if Self Test Done */ +#define RNG_SELF_TEST_DONE() \ + (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_ST_DONE) +/* Put RNG for SEED Generation */ +#define RNG_SEED_GEN() \ +{ \ + register uint32_t command = RNG_READ_REGISTER(RNGC_COMMAND); \ + RNG_WRITE_REGISTER(RNGC_COMMAND, command \ + | RNGC_COMMAND_SEED); \ +} +/* Return non-zero if RESEED Required */ +#define RNG_RESEED() \ + (RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_RESEED) + +/*! Return non-zero if the RNG is in High Assurance mode. */ +#define RNG_GET_HIGH_ASSURANCE() (RNG_READ_REGISTER(RNGC_STATUS) & \ + RNGC_STATUS_SEC_STATE) + +/*! Clear all status, error and otherwise. */ +#define RNG_CLEAR_ALL_STATUS() \ + RNG_WRITE_REGISTER(RNGC_COMMAND, \ + RNGC_COMMAND_CLEAR_INTERRUPT \ + | RNGC_COMMAND_CLEAR_ERROR) + +/*! Return non-zero if everything seems OK with the RNG. */ +#define RNG_WORKING() \ + ((RNG_READ_REGISTER(RNGC_ERROR) \ + & (RNGC_ERROR_STATUS_STAT_ERR | RNGC_ERROR_STATUS_RAND_ERR \ + | RNGC_ERROR_STATUS_FIFO_ERR | RNGC_ERROR_STATUS_ST_ERR | \ + RNGC_ERROR_STATUS_OSC_ERR | RNGC_ERROR_STATUS_LFSR_ERR )) == 0) +/*! Return Non zero if SEEDING is DONE */ +#define RNG_SEED_DONE() \ + ((RNG_READ_REGISTER(RNGC_STATUS) & RNGC_STATUS_SEED_DONE) != 0) + +/*! Put the RNG into sleep (low-power) mode. */ +#define RNG_SLEEP() + +/*! Wake the RNG from sleep (low-power) mode. */ + +/*! Mask interrupts so that the driver/OS will not see them. */ +#define RNG_MASK_ALL_INTERRUPTS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL); \ + RNG_WRITE_REGISTER(RNGC_CONTROL, control \ + | RNGC_CONTROL_MASK_DONE \ + | RNGC_CONTROL_MASK_ERROR); \ +} +/*! Configuring RNGC for self Test. */ + +#define RNG_AUTO_SEED() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL); \ + RNG_WRITE_REGISTER(RNGC_CONTROL, control \ + | RNGC_CONTROL_AUTO_SEED); \ +} + +/*! Unmask interrupts so that the driver/OS will see them. */ +#define RNG_UNMASK_ALL_INTERRUPTS() \ +{ \ + register uint32_t control = RNG_READ_REGISTER(RNGC_CONTROL); \ + RNG_WRITE_REGISTER(RNGC_CONTROL, \ + control & ~(RNGC_CONTROL_MASK_DONE|RNGC_CONTROL_MASK_ERROR)); \ +} + +/*! Put RNG to sleep if appropriate. */ +#define RNG_PUT_RNG_TO_SLEEP() + +/*! Wake RNG from sleep if necessary. */ +#define RNG_WAKE_FROM_SLEEP() + +#endif /* RNG TYPE */ + +/* internal functions */ +static os_error_code rng_map_RNG_memory(void); +static os_error_code rng_setup_interrupt_handling(void); +#ifdef RNG_REGISTER_PEEK_POKE +inline static int rng_check_register_offset(uint32_t offset); +inline static int rng_check_register_accessible(uint32_t offset, + int access_write); +#endif /* DEBUG_RNG_REGISTERS */ +static fsl_shw_return_t rng_drain_fifo(uint32_t * random_p, int count_words); +static os_error_code rng_grab_config_values(void); +static void rng_cleanup(void); + +#ifdef FSL_HAVE_RNGA +static void rng_sec_failure(void); +#endif + +#ifdef RNG_REGISTER_DEBUG +static uint32_t dbg_rng_read_register(uint32_t offset); +static void dbg_rng_write_register(uint32_t offset, uint32_t value); +#endif + +#if defined(LINUX_VERSION_CODE) + +EXPORT_SYMBOL(fsl_shw_add_entropy); +EXPORT_SYMBOL(fsl_shw_get_random); + +#ifdef RNG_REGISTER_PEEK_POKE +/* For Linux kernel, export the API functions to other kernel modules */ +EXPORT_SYMBOL(rng_read_register); +EXPORT_SYMBOL(rng_write_register); +#endif /* DEBUG_RNG_REGISTERS */ + + + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("Device Driver for RNG"); + +#endif /* LINUX_VERSION_CODE */ + +#endif /* RNG_INTERNALS_H */ diff --git a/drivers/mxc/security/rng/include/rng_rnga.h b/drivers/mxc/security/rng/include/rng_rnga.h new file mode 100644 index 000000000000..a3a86b961506 --- /dev/null +++ b/drivers/mxc/security/rng/include/rng_rnga.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef RNG_RNGA_H +#define RNG_RNGA_H + +/*! @defgroup rngaregs RNGA Registers + * @ingroup RNG + * These are the definitions for the RNG registers and their offsets + * within the RNG. They are used in the @c register_offset parameter of + * #rng_read_register() and #rng_write_register(). + */ +/*! @addtogroup rngaregs */ +/*! @{ */ + +/*! Control Register. See @ref rngacontrolreg. */ +#define RNGA_CONTROL 0x00 +/*! Status Register. See @ref rngastatusreg. */ +#define RNGA_STATUS 0x04 +/*! Register for adding to the Entropy of the RNG */ +#define RNGA_ENTROPY 0x08 +/*! Register containing latest 32 bits of random value */ +#define RNGA_OUTPUT_FIFO 0x0c +/*! Mode Register. Non-secure mode access only. See @ref rngmodereg. */ +#define RNGA_MODE 0x10 +/*! Verification Control Register. Non-secure mode access only. See + * @ref rngvfctlreg. */ +#define RNGA_VERIFICATION_CONTROL 0x14 +/*! Oscillator Control Counter Register. Non-secure mode access only. + * See @ref rngosccntctlreg. */ +#define RNGA_OSCILLATOR_CONTROL_COUNTER 0x18 +/*! Oscillator 1 Counter Register. Non-secure mode access only. See + * @ref rngosccntreg. */ +#define RNGA_OSCILLATOR1_COUNTER 0x1c +/*! Oscillator 2 Counter Register. Non-secure mode access only. See + * @ref rngosccntreg. */ +#define RNGA_OSCILLATOR2_COUNTER 0x20 +/*! Oscillator Counter Status Register. Non-secure mode access only. See + * @ref rngosccntstatreg. */ +#define RNGA_OSCILLATOR_COUNTER_STATUS 0x24 +/*! @} */ + +/*! Total address space of the RNGA, in bytes */ +#define RNG_ADDRESS_RANGE 0x28 + +/*! @defgroup rngacontrolreg RNGA Control Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngacontrolreg */ +/*! @{ */ +/*! These bits are unimplemented or reserved */ +#define RNGA_CONTROL_ZEROS_MASK 0x0fffffe0 +/*! 'RNG type' - should be 0 for RNGA */ +#define RNGA_CONTROL_RNG_TYPE_MASK 0xf0000000 +/*! Number of bits to shift the type to get it to LSB */ +#define RNGA_CONTROL_RNG_TYPE_SHIFT 28 +/*! Put RNG to sleep */ +#define RNGA_CONTROL_SLEEP 0x00000010 +/*! Clear interrupt & status */ +#define RNGA_CONTROL_CLEAR_INTERRUPT 0x00000008 +/*! Mask interrupt generation */ +#define RNGA_CONTROL_MASK_INTERRUPTS 0x00000004 +/*! Enter into Secure Mode. Notify SCC of security violation should FIFO + * underflow occur. */ +#define RNGA_CONTROL_HIGH_ASSURANCE 0x00000002 +/*! Load data into FIFO */ +#define RNGA_CONTROL_GO 0x00000001 +/*! @} */ + +/*! @defgroup rngastatusreg RNGA Status Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngastatusreg */ +/*! @{ */ +/*! RNG Oscillator not working */ +#define RNGA_STATUS_OSCILLATOR_DEAD 0x80000000 +/*! These bits are undefined or reserved */ +#define RNGA_STATUS_ZEROS1_MASK 0x7f000000 +/*! How big FIFO is, in bytes */ +#define RNGA_STATUS_OUTPUT_FIFO_SIZE_MASK 0x00ff0000 +/*! How many bits right to shift fifo size to make it LSB */ +#define RNGA_STATUS_OUTPUT_FIFO_SIZE_SHIFT 16 +/*! How many bytes are currently in the FIFO */ +#define RNGA_STATUS_OUTPUT_FIFO_LEVEL_MASK 0x0000ff00 +/*! How many bits right to shift fifo level to make it LSB */ +#define RNGA_STATUS_OUTPUT_FIFO_LEVEL_SHIFT 8 +/*! These bits are undefined or reserved. */ +#define RNGA_STATUS_ZEROS2_MASK 0x000000e0 +/*! RNG is sleeping. */ +#define RNGA_STATUS_SLEEP 0x00000010 +/*! Error detected. */ +#define RNGA_STATUS_ERROR_INTERRUPT 0x00000008 +/*! FIFO was empty on some read since last status read. */ +#define RNGA_STATUS_FIFO_UNDERFLOW 0x00000004 +/*! FIFO was empty on most recent read. */ +#define RNGA_STATUS_LAST_READ_STATUS 0x00000002 +/*! Security violation occurred. Will only happen in High Assurance mode. */ +#define RNGA_STATUS_SECURITY_VIOLATION 0x00000001 +/*! @} */ + +/*! @defgroup rngmodereg RNG Mode Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngmodereg */ +/*! @{ */ +/*! These bits are undefined or reserved */ +#define RNGA_MODE_ZEROS_MASK 0xfffffffc +/*! RNG is in / put RNG in Oscillator Frequency Test Mode. */ +#define RNGA_MODE_OSCILLATOR_FREQ_TEST 0x00000002 +/*! Put RNG in verification mode / RNG is in verification mode. */ +#define RNGA_MODE_VERIFICATION 0x00000001 +/*! @} */ + +/*! @defgroup rngvfctlreg RNG Verification Control Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngvfctlreg */ +/*! @{ */ +/*! These bits are undefined or reserved. */ +#define RNGA_VFCTL_ZEROS_MASK 0xfffffff8 +/*! Reset the shift registers. */ +#define RNGA_VFCTL_RESET_SHIFT_REGISTERS 0x00000004 +/*! Drive shift registers from system clock. */ +#define RNGA_VFCTL_FORCE_SYSTEM_CLOCK 0x00000002 +/*! Turn off shift register clocks. */ +#define RNGA_VFCTL_SHIFT_CLOCK_OFF 0x00000001 +/*! @} */ + +/*! + * @defgroup rngosccntctlreg RNG Oscillator Counter Control Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngosccntctlreg */ +/*! @{ */ +/*! These bits are undefined or reserved. */ +#define RNGA_OSCCR_ZEROS_MASK 0xfffc0000 +/*! Bits containing clock cycle counter */ +#define RNGA_OSCCR_CLOCK_CYCLES_MASK 0x0003ffff +/*! Bits to shift right RNG_OSCCR_CLOCK_CYCLES_MASK */ +#define RNGA_OSCCR_CLOCK_CYCLES_SHIFT 0 +/*! @} */ + +/*! + * @defgroup rngosccntreg RNG Oscillator (1 and 2) Counter Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngosccntreg */ +/*! @{ */ +/*! These bits are undefined or reserved. */ +#define RNGA_COUNTER_ZEROS_MASK 0xfff00000 +/*! Bits containing number of clock pulses received from the oscillator. */ +#define RNGA_COUNTER_PULSES_MASK 0x000fffff +/*! Bits right to shift RNG_COUNTER_PULSES_MASK to make it LSB. */ +#define RNGA_COUNTER_PULSES_SHIFT 0 +/*! @} */ + +/*! + * @defgroup rngosccntstatreg RNG Oscillator Counter Status Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngosccntstatreg */ +/*! @{ */ +/*! These bits are undefined or reserved. */ +#define RNGA_COUNTER_STATUS_ZEROS_MASK 0xfffffffc +/*! Oscillator 2 has toggled 0x400 times */ +#define RNGA_COUNTER_STATUS_OSCILLATOR2 0x00000002 +/*! Oscillator 1 has toggled 0x400 times */ +#define RNGA_COUNTER_STATUS_OSCILLATOR1 0x00000001 +/*! @} */ + +#endif /* RNG_RNGA_H */ diff --git a/drivers/mxc/security/rng/include/rng_rngc.h b/drivers/mxc/security/rng/include/rng_rngc.h new file mode 100644 index 000000000000..d7b7f127f74c --- /dev/null +++ b/drivers/mxc/security/rng/include/rng_rngc.h @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file rng_rngc.h + * + * Definition of the registers for the RNGB and RNGC. The names start with + * RNGC where they are in common or relate only to the RNGC; the RNGB-only + * definitions begin with RNGB. + * + */ + +#ifndef RNG_RNGC_H +#define RNG_RNGC_H + +#define RNGC_VERSION_MAJOR3 3 + +/*! @defgroup rngcregs RNGB/RNGC Registers + * These are the definitions for the RNG registers and their offsets + * within the RNG. They are used in the @c register_offset parameter of + * #rng_read_register() and #rng_write_register(). + * + * @ingroup RNG + */ +/*! @addtogroup rngcregs */ +/*! @{ */ + +/*! RNGC Version ID Register R/W */ +#define RNGC_VERSION_ID 0x0000 +/*! RNGC Command Register R/W */ +#define RNGC_COMMAND 0x0004 +/*! RNGC Control Register R/W */ +#define RNGC_CONTROL 0x0008 +/*! RNGC Status Register R */ +#define RNGC_STATUS 0x000C +/*! RNGC Error Status Register R */ +#define RNGC_ERROR 0x0010 +/*! RNGC FIFO Register W */ +#define RNGC_FIFO 0x0014 +/*! Undefined */ +#define RNGC_UNDEF_18 0x0018 +/*! RNGB Entropy Register W */ +#define RNGB_ENTROPY 0x0018 +/*! Undefined */ +#define RNGC_UNDEF_1C 0x001C +/*! RNGC Verification Control Register1 R/W */ +#define RNGC_VERIFICATION_CONTROL 0x0020 +/*! Undefined */ +#define RNGC_UNDEF_24 0x0024 +/*! RNGB XKEY Data Register R */ +#define RNGB_XKEY 0x0024 +/*! RNGC Oscillator Counter Control Register1 R/W */ +#define RNGC_OSC_COUNTER_CONTROL 0x0028 +/*! RNGC Oscillator Counter Register1 R */ +#define RNGC_OSC_COUNTER 0x002C +/*! RNGC Oscillator Counter Status Register1 R */ +#define RNGC_OSC_COUNTER_STATUS 0x0030 +/*! @} */ + +/*! @defgroup rngcveridreg RNGB/RNGC Version ID Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngcveridreg */ +/*! @{ */ +/*! These bits are unimplemented or reserved */ +#define RNGC_VERID_ZEROS_MASK 0x0f000000 +/*! Mask for RNG TYPE */ +#define RNGC_VERID_RNG_TYPE_MASK 0xf0000000 +/*! Shift to make RNG TYPE be LSB */ +#define RNGC_VERID_RNG_TYPE_SHIFT 28 +/*! Mask for RNG Chip Version */ +#define RNGC_VERID_CHIP_VERSION_MASK 0x00ff0000 +/*! Shift to make RNG Chip version be LSB */ +#define RNGC_VERID_CHIP_VERSION_SHIFT 16 +/*! Mask for RNG Major Version */ +#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00 +/*! Shift to make RNG Major version be LSB */ +#define RNGC_VERID_VERSION_MAJOR_SHIFT 8 +/*! Mask for RNG Minor Version */ +#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff +/*! Shift to make RNG Minor version be LSB */ +#define RNGC_VERID_VERSION_MINOR_SHIFT 0 +/*! @} */ + +/*! @defgroup rngccommandreg RNGB/RNGC Command Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngccommandreg */ +/*! @{ */ +/*! These bits are unimplemented or reserved. */ +#define RNGC_COMMAND_ZEROS_MASK 0xffffff8c +/*! Perform a software reset of the RNGC. */ +#define RNGC_COMMAND_SOFTWARE_RESET 0x00000040 +/*! Clear error from Error Status register (and interrupt). */ +#define RNGC_COMMAND_CLEAR_ERROR 0x00000020 +/*! Clear interrupt & status. */ +#define RNGC_COMMAND_CLEAR_INTERRUPT 0x00000010 +/*! Start RNGC seed generation. */ +#define RNGC_COMMAND_SEED 0x00000002 +/*! Perform a self test of (and reset) the RNGC. */ +#define RNGC_COMMAND_SELF_TEST 0x00000001 +/*! @} */ + +/*! @defgroup rngccontrolreg RNGB/RNGC Control Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngccontrolreg */ +/*! @{ */ +/*! These bits are unimplemented or reserved */ +#define RNGC_CONTROL_ZEROS_MASK 0xfffffc8c +/*! Allow access to verification registers. */ +#define RNGC_CONTROL_CTL_ACC 0x00000200 +/*! Put RNGC into deterministic verifcation mode. */ +#define RNGC_CONTROL_VERIF_MODE 0x00000100 +/*! Prevent RNGC from generating interrupts caused by errors. */ +#define RNGC_CONTROL_MASK_ERROR 0x00000040 + +/*! + * Prevent RNGB/RNGC from generating interrupts after Seed Done or Self Test + * Mode completion. + */ +#define RNGC_CONTROL_MASK_DONE 0x00000020 +/*! Allow RNGC to generate a new seed whenever it is needed. */ +#define RNGC_CONTROL_AUTO_SEED 0x00000010 +/*! Set FIFO Underflow Response.*/ +#define RNGC_CONTROL_FIFO_UFLOW_MASK 0x00000003 +/*! Shift value to make FIFO Underflow Response be LSB. */ +#define RNGC_CONTROL_FIFO_UFLOW_SHIFT 0 + +/*! @} */ + +/*! @{ */ +/*! FIFO Underflow should cause ... */ +#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR 0 +/*! FIFO Underflow should cause ... */ +#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_ERROR2 1 +/*! FIFO Underflow should cause ... */ +#define RNGC_CONTROL_FIFO_UFLOW_BUS_XFR 2 +/*! FIFO Underflow should cause ... */ +#define RNGC_CONTROL_FIFO_UFLOW_ZEROS_INTR 3 +/*! @} */ + +/*! @defgroup rngcstatusreg RNGB/RNGC Status Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngcstatusreg */ +/*! @{ */ +/*! Unused or MBZ. */ +#define RNGC_STATUS_ZEROS_MASK 0x003e0080 +/*! + * Statistical tests pass-fail. Individual bits on indicate failure of a + * particular test. + */ +#define RNGC_STATUS_STAT_TEST_PF_MASK 0xff000000 +/*! Mask to get Statistical PF to be LSB. */ +#define RNGC_STATUS_STAT_TEST_PF_SHIFT 24 +/*! + * Self tests pass-fail. Individual bits on indicate failure of a + * particular test. + */ +#define RNGC_STATUS_ST_PF_MASK 0x00c00000 +/*! Shift value to get Self Test PF field to be LSB. */ +#define RNGC_STATUS_ST_PF_SHIFT 22 +/* TRNG Self test pass-fail */ +#define RNGC_STATUS_ST_PF_TRNG 0x00800000 +/* PRNG Self test pass-fail */ +#define RNGC_STATUS_ST_PF_PRNG 0x00400000 +/*! Error detected in RNGC. See Error Status register. */ +#define RNGC_STATUS_ERROR 0x00010000 +/*! Size of the internal FIFO in 32-bit words. */ +#define RNGC_STATUS_FIFO_SIZE_MASK 0x0000f000 +/*! Shift value to get FIFO Size to be LSB. */ +#define RNGC_STATUS_FIFO_SIZE_SHIFT 12 +/*! The level (available data) of the internal FIFO in 32-bit words. */ +#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00 +/*! Shift value to get FIFO Level to be LSB. */ +#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8 +/*! A new seed is ready for use. */ +#define RNGC_STATUS_NEXT_SEED_DONE 0x00000040 +/*! The first seed has been generated. */ +#define RNGC_STATUS_SEED_DONE 0x00000020 +/*! Self Test has been completed. */ +#define RNGC_STATUS_ST_DONE 0x00000010 +/*! Reseed is necessary. */ +#define RNGC_STATUS_RESEED 0x00000008 +/*! RNGC is sleeping. */ +#define RNGC_STATUS_SLEEP 0x00000004 +/*! RNGC is currently generating numbers, seeding, generating next seed, or + performing a self test. */ +#define RNGC_STATUS_BUSY 0x00000002 +/*! RNGC is in secure state. */ +#define RNGC_STATUS_SEC_STATE 0x00000001 + +/*! @} */ + +/*! @defgroup rngcerrstatusreg RNGB/RNGC Error Status Register Definitions + * @ingroup RNG + */ +/*! @addtogroup rngcerrstatusreg */ +/*! @{ */ +/*! Unused or MBZ. */ +#define RNGC_ERROR_STATUS_ZEROS_MASK 0xffffff80 +/*! Bad Key Error Status */ +#define RNGC_ERROR_STATUS_BAD_KEY 0x00000040 +/*! Random Compare Error. Previous number matched the current number. */ +#define RNGC_ERROR_STATUS_RAND_ERR 0x00000020 +/*! FIFO Underflow. FIFO was read while empty. */ +#define RNGC_ERROR_STATUS_FIFO_ERR 0x00000010 +/*! Statistic Error Statistic Test failed for the last seed. */ +#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008 +/*! Self-test error. Some self test has failed. */ +#define RNGC_ERROR_STATUS_ST_ERR 0x00000004 +/*! + * Oscillator Error. The oscillator may be broken. Clear by hard or soft + * reset. + */ +#define RNGC_ERROR_STATUS_OSC_ERR 0x00000002 +/*! LFSR Error. Clear by hard or soft reset. */ +#define RNGC_ERROR_STATUS_LFSR_ERR 0x00000001 + +/*! @} */ + +/*! Total address space of the RNGB/RNGC registers, in bytes */ +#define RNG_ADDRESS_RANGE 0x34 + +#endif /* RNG_RNGC_H */ diff --git a/drivers/mxc/security/rng/include/shw_driver.h b/drivers/mxc/security/rng/include/shw_driver.h new file mode 100644 index 000000000000..d529b4fe6e6b --- /dev/null +++ b/drivers/mxc/security/rng/include/shw_driver.h @@ -0,0 +1,2971 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef SHW_DRIVER_H +#define SHW_DRIVER_H + +/* This is a Linux flag meaning 'compiling kernel code'... */ +#ifndef __KERNEL__ +#include +#include +#include +#include +#include +#else +#include "../../sahara2/include/portable_os.h" +#endif /* __KERNEL__ */ + +#include "../../sahara2/include/fsl_platform.h" + +/*! @file shw_driver.h + * + * @brief Header file to use the SHW driver. + * + * The SHW driver is used in two modes: By a user, from the FSL SHW API in user + * space, which goes through /dev/fsl_shw to make open(), ioctl(), and close() + * calls; and by other kernel modules/drivers, which use the FSL SHW API, parts + * of which are supported directly by the SHW driver. + * + * Testing is performed by using the apitest and kernel api test routines + * developed for the Sahara2 driver. + */ +/*#define DIAG_SECURITY_FUNC*/ +/*! Perform a security function. */ +#define SHW_IOCTL_REQUEST 21 + +/* This definition may need a new name, and needs to go somewhere which + * can determine platform, kernel vs. user, os, etc. + */ +#define copy_bytes(out, in, len) memcpy(out, in, len) + + +/*! + * This is part of the IOCTL request type passed between kernel and user space. + * It is added to #SHW_IOCTL_REQUEST to generate the actual value. + */ +typedef enum shw_user_request_t { + SHW_USER_REQ_REGISTER_USER, /*!< Initialize user-kernel discussion. */ + SHW_USER_REQ_DEREGISTER_USER, /*!< Terminate user-kernel discussion. */ + SHW_USER_REQ_GET_RESULTS, /*!< Get information on outstanding + results. */ + SHW_USER_REQ_GET_CAPABILITIES, /*!< Get information on hardware support. */ + SHW_USER_REQ_GET_RANDOM, /*!< Get random data from RNG. */ + SHW_USER_REQ_ADD_ENTROPY, /*!< Add entropy to hardware RNG. */ + SHW_USER_REQ_DROP_PERMS, /*!< Diminish the permissions of a block of + secure memory */ + SHW_USER_REQ_SSTATUS, /*!< Check the status of a block of secure + memory */ + SHW_USER_REQ_SFREE, /*!< Free a block of secure memory */ + SHW_USER_REQ_SCC_ENCRYPT, /*!< Encrypt a region of user-owned secure + memory */ + SHW_USER_REQ_SCC_DECRYPT, /*!< Decrypt a region of user-owned secure + memory */ +} shw_user_request_t; + + +/*! + * @typedef scc_partition_status_t + */ +/** Partition status information. */ +typedef enum fsl_shw_partition_status_t { + FSL_PART_S_UNUSABLE, /*!< Partition not implemented */ + FSL_PART_S_UNAVAILABLE, /*!< Partition owned by other host */ + FSL_PART_S_AVAILABLE, /*!< Partition available */ + FSL_PART_S_ALLOCATED, /*!< Partition owned by host but not engaged + */ + FSL_PART_S_ENGAGED, /*!< Partition owned by host and engaged */ +} fsl_shw_partition_status_t; + + +/* + * Structure passed during user ioctl() calls to manage secure partitions. + */ +typedef struct scc_partition_info_t { + uint32_t user_base; /*!< Userspace pointer to base of partition */ + uint32_t permissions; /*!< Permissions to give the partition (only + used in call to _DROP_PERMS) */ + fsl_shw_partition_status_t status; /*!< Status of the partition */ +} scc_partition_info_t; + + +/****************************************************************************** + * Enumerations + *****************************************************************************/ +/*! + * Flags for the state of the User Context Object (#fsl_shw_uco_t). + */ +typedef enum fsl_shw_user_ctx_flags_t +{ + /*! + * API will block the caller until operation completes. The result will be + * available in the return code. If this is not set, user will have to get + * results using #fsl_shw_get_results(). + */ + FSL_UCO_BLOCKING_MODE = 0x01, + /*! + * User wants callback (at the function specified with + * #fsl_shw_uco_set_callback()) when the operation completes. This flag is + * valid only if #FSL_UCO_BLOCKING_MODE is not set. + */ + FSL_UCO_CALLBACK_MODE = 0x02, + /*! Do not free descriptor chain after driver (adaptor) finishes */ + FSL_UCO_SAVE_DESC_CHAIN = 0x04, + /*! + * User has made at least one request with callbacks requested, so API is + * ready to handle others. + */ + FSL_UCO_CALLBACK_SETUP_COMPLETE = 0x08, + /*! + * (virtual) pointer to descriptor chain is completely linked with physical + * (DMA) addresses, ready for the hardware. This flag should not be used + * by FSL SHW API programs. + */ + FSL_UCO_CHAIN_PREPHYSICALIZED = 0x10, + /*! + * The user has changed the context but the changes have not been copied to + * the kernel driver. + */ + FSL_UCO_CONTEXT_CHANGED = 0x20, + /*! Internal Use. This context belongs to a user-mode API user. */ + FSL_UCO_USERMODE_USER = 0x40, +} fsl_shw_user_ctx_flags_t; + + +/*! + * Return code for FSL_SHW library. + * + * These codes may be returned from a function call. In non-blocking mode, + * they will appear as the status in a Result Object. + */ +/* REQ-FSLSHW-ERR-001 */ +typedef enum fsl_shw_return_t +{ + /*! + * No error. As a function return code in Non-blocking mode, this may + * simply mean that the operation was accepted for eventual execution. + */ + FSL_RETURN_OK_S = 0, + /*! Failure for non-specific reason. */ + FSL_RETURN_ERROR_S, + /*! + * Operation failed because some resource was not able to be allocated. + */ + FSL_RETURN_NO_RESOURCE_S, + /*! Crypto algorithm unrecognized or improper. */ + FSL_RETURN_BAD_ALGORITHM_S, + /*! Crypto mode unrecognized or improper. */ + FSL_RETURN_BAD_MODE_S, + /*! Flag setting unrecognized or inconsistent. */ + FSL_RETURN_BAD_FLAG_S, + /*! Improper or unsupported key length for algorithm. */ + FSL_RETURN_BAD_KEY_LENGTH_S, + /*! Improper parity in a (DES, TDES) key. */ + FSL_RETURN_BAD_KEY_PARITY_S, + /*! + * Improper or unsupported data length for algorithm or internal buffer. + */ + FSL_RETURN_BAD_DATA_LENGTH_S, + /*! Authentication / Integrity Check code check failed. */ + FSL_RETURN_AUTH_FAILED_S, + /*! A memory error occurred. */ + FSL_RETURN_MEMORY_ERROR_S, + /*! An error internal to the hardware occurred. */ + FSL_RETURN_INTERNAL_ERROR_S, + /*! ECC detected Point at Infinity */ + FSL_RETURN_POINT_AT_INFINITY_S, + /*! ECC detected No Point at Infinity */ + FSL_RETURN_POINT_NOT_AT_INFINITY_S, + /*! GCD is One */ + FSL_RETURN_GCD_IS_ONE_S, + /*! GCD is not One */ + FSL_RETURN_GCD_IS_NOT_ONE_S, + /*! Candidate is Prime */ + FSL_RETURN_PRIME_S, + /*! Candidate is not Prime */ + FSL_RETURN_NOT_PRIME_S, + /*! N register loaded improperly with even value */ + FSL_RETURN_EVEN_MODULUS_ERROR_S, + /*! Divisor is zero. */ + FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S, + /*! Bad Exponent or Scalar value for Point Multiply */ + FSL_RETURN_BAD_EXPONENT_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_OSCILLATOR_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_STATISTICS_ERROR_S, +} fsl_shw_return_t; + + +/*! + * Algorithm Identifier. + * + * Selection of algorithm will determine how large the block size of the + * algorithm is. Context size is the same length unless otherwise specified. + * Selection of algorithm also affects the allowable key length. + */ +typedef enum fsl_shw_key_alg_t +{ + /*! + * Key will be used to perform an HMAC. Key size is 1 to 64 octets. Block + * size is 64 octets. + */ + FSL_KEY_ALG_HMAC, + /*! + * Advanced Encryption Standard (Rijndael). Block size is 16 octets. Key + * size is 16 octets. (The single choice of key size is a Sahara platform + * limitation.) + */ + FSL_KEY_ALG_AES, + /*! + * Data Encryption Standard. Block size is 8 octets. Key size is 8 + * octets. + */ + FSL_KEY_ALG_DES, + /*! + * 2- or 3-key Triple DES. Block size is 8 octets. Key size is 16 octets + * for 2-key Triple DES, and 24 octets for 3-key. + */ + FSL_KEY_ALG_TDES, + /*! + * ARC4. No block size. Context size is 259 octets. Allowed key size is + * 1-16 octets. (The choices for key size are a Sahara platform + * limitation.) + */ + FSL_KEY_ALG_ARC4, +} fsl_shw_key_alg_t; + + +/*! + * Mode selector for Symmetric Ciphers. + * + * The selection of mode determines how a cryptographic algorithm will be + * used to process the plaintext or ciphertext. + * + * For all modes which are run block-by-block (that is, all but + * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text + * length which is multiple of the block size. Except for #FSL_SYM_MODE_CTR, + * these block-by-block algorithms must also be passed a total number of octets + * which is a multiple of the block size. + * + * In modes which require that the total number of octets of data be a multiple + * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user + * has a total number of octets which are not a multiple of the block size, the + * user must perform any necessary padding to get to the correct data length. + */ +typedef enum fsl_shw_sym_mode_t +{ + /*! + * Stream. There is no associated block size. Any request to process data + * may be of any length. This mode is only for ARC4 operations, and is + * also the only mode used for ARC4. + */ + FSL_SYM_MODE_STREAM, + + /*! + * Electronic Codebook. Each block of data is encrypted/decrypted. The + * length of the data stream must be a multiple of the block size. This + * mode may be used for DES, 3DES, and AES. The block size is determined + * by the algorithm. + */ + FSL_SYM_MODE_ECB, + /*! + * Cipher-Block Chaining. Each block of data is encrypted/decrypted and + * then "chained" with the previous block by an XOR function. Requires + * context to start the XOR (previous block). This mode may be used for + * DES, 3DES, and AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CBC, + /*! + * Counter. The counter is encrypted, then XORed with a block of data. + * The counter is then incremented (using modulus arithmetic) for the next + * block. The final operation may be non-multiple of block size. This mode + * may be used for AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CTR, +} fsl_shw_sym_mode_t; + + +/*! + * Algorithm selector for Cryptographic Hash functions. + * + * Selection of algorithm determines how large the context and digest will be. + * Context is the same size as the digest (resulting hash), unless otherwise + * specified. + */ +typedef enum fsl_shw_hash_alg_t +{ + FSL_HASH_ALG_MD5, /*!< MD5 algorithm. Digest is 16 octets. */ + FSL_HASH_ALG_SHA1, /*!< SHA-1 (aka SHA or SHA-160) algorithm. + Digest is 20 octets. */ + FSL_HASH_ALG_SHA224, /*!< SHA-224 algorithm. Digest is 28 octets, + though context is 32 octets. */ + FSL_HASH_ALG_SHA256 /*!< SHA-256 algorithm. Digest is 32 + octets. */ +} fsl_shw_hash_alg_t; + + +/*! + * The type of Authentication-Cipher function which will be performed. + */ +typedef enum fsl_shw_acc_mode_t +{ + /*! + * CBC-MAC for Counter. Requires context and modulus. Final operation may + * be non-multiple of block size. This mode may be used for AES. + */ + FSL_ACC_MODE_CCM, + /*! + * SSL mode. Not supported. Combines HMAC and encrypt (or decrypt). + * Needs one key object for encryption, another for the HMAC. The usual + * hashing and symmetric encryption algorithms are supported. + */ + FSL_ACC_MODE_SSL +} fsl_shw_acc_mode_t; + + +/* REQ-FSLSHW-PINTFC-COA-HCO-001 */ +/*! + * Flags which control a Hash operation. + */ +typedef enum fsl_shw_hash_ctx_flags_t +{ + FSL_HASH_FLAGS_INIT = 0x01, /*!< Context is empty. Hash is started + from scratch, with a message-processed + count of zero. */ + FSL_HASH_FLAGS_SAVE = 0x02, /*!< Retrieve context from hardware after + hashing. If used with the + #FSL_HASH_FLAGS_FINALIZE flag, the final + digest value will be saved in the + object. */ + FSL_HASH_FLAGS_LOAD = 0x04, /*!< Place context into hardware before + hashing. */ + FSL_HASH_FLAGS_FINALIZE = 0x08, /*!< PAD message and perform final digest + operation. If user message is + pre-padded, this flag should not be + used. */ +} fsl_shw_hash_ctx_flags_t; + + +/*! + * Flags which control an HMAC operation. + * + * These may be combined by ORing them together. See #fsl_shw_hmco_set_flags() + * and #fsl_shw_hmco_clear_flags(). + */ +typedef enum fsl_shw_hmac_ctx_flags_t +{ + FSL_HMAC_FLAGS_INIT = 1, /**< Message context is empty. HMAC is + started from scratch (with key) or from + precompute of inner hash, depending on + whether + #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is + set. */ + FSL_HMAC_FLAGS_SAVE = 2, /**< Retrieve ongoing context from hardware + after hashing. If used with the + #FSL_HMAC_FLAGS_FINALIZE flag, the final + digest value (HMAC) will be saved in the + object. */ + FSL_HMAC_FLAGS_LOAD = 4, /**< Place ongoing context into hardware + before hashing. */ + FSL_HMAC_FLAGS_FINALIZE = 8, /**< PAD message and perform final HMAC + operations of inner and outer hashes. */ + FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16 /**< This means that the context + contains precomputed inner and outer + hash values. */ +} fsl_shw_hmac_ctx_flags_t; + + +/** + * Flags to control use of the #fsl_shw_scco_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags() + */ +typedef enum fsl_shw_sym_ctx_flags_t +{ + /** + * Context is empty. In ARC4, this means that the S-Box needs to be + * generated from the key. In #FSL_SYM_MODE_CBC mode, this allows an IV of + * zero to be specified. In #FSL_SYM_MODE_CTR mode, it means that an + * initial CTR value of zero is desired. + */ + FSL_SYM_CTX_INIT = 1, + /** + * Load context from object into hardware before running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_LOAD = 2, + /** + * Save context from hardware into object after running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_SAVE = 4, + /** + * Context (SBox) is to be unwrapped and wrapped on each use. + * This flag is unsupported. + * */ + FSL_SYM_CTX_PROTECT = 8, +} fsl_shw_sym_ctx_flags_t; + + +/** + * Flags which describe the state of the #fsl_shw_sko_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags() + */ +typedef enum fsl_shw_key_flags_t +{ + FSL_SKO_KEY_IGNORE_PARITY = 1, /*!< If algorithm is DES or 3DES, do not + validate the key parity bits. */ + FSL_SKO_KEY_PRESENT = 2, /*!< Clear key is present in the object. */ + FSL_SKO_KEY_ESTABLISHED = 4, /*!< Key has been established for use. This + feature is not available for all + platforms, nor for all algorithms and + modes.*/ + FSL_SKO_USE_SECRET_KEY = 8, /*!< Use device-unique key. Not always + available. */ + FSL_SKO_KEY_SW_KEY = 16, /*!< Clear key can be provided to the user */ + FSL_SKO_KEY_SELECT_PF_KEY = 32, /*!< Internal flag to show that this key + references one of the hardware keys, and + its value is in pf_key. */ +} fsl_shw_key_flags_t; + + +/** + * Type of value which is associated with an established key. + */ +typedef uint64_t key_userid_t; + + +/** + * Flags which describe the state of the #fsl_shw_acco_t. + * + * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used + * together, provide for a one-shot operation. + */ +typedef enum fsl_shw_auth_ctx_flags_t +{ + FSL_ACCO_CTX_INIT = 1, /**< Initialize Context(s) */ + FSL_ACCO_CTX_LOAD = 2, /**< Load intermediate context(s). + This flag is unsupported. */ + FSL_ACCO_CTX_SAVE = 4, /**< Save intermediate context(s). + This flag is unsupported. */ + FSL_ACCO_CTX_FINALIZE = 8, /**< Create MAC during this operation. */ + FSL_ACCO_NIST_CCM = 0x10, /**< Formatting of CCM input data is + performed by calls to + #fsl_shw_ccm_nist_format_ctr_and_iv() and + #fsl_shw_ccm_nist_update_ctr_and_iv(). */ +} fsl_shw_auth_ctx_flags_t; + + +/** + * The operation which controls the behavior of #fsl_shw_establish_key(). + * + * These values are passed to #fsl_shw_establish_key(). + */ +typedef enum fsl_shw_key_wrap_t +{ + FSL_KEY_WRAP_CREATE, /**< Generate a key from random values. */ + FSL_KEY_WRAP_ACCEPT, /**< Use the provided clear key. */ + FSL_KEY_WRAP_UNWRAP /**< Unwrap a previously wrapped key. */ +} fsl_shw_key_wrap_t; + + +/** + * Modulus Selector for CTR modes. + * + * The incrementing of the Counter value may be modified by a modulus. If no + * modulus is needed or desired for AES, use #FSL_CTR_MOD_128. + */ +typedef enum fsl_shw_ctr_mod_t +{ + FSL_CTR_MOD_8, /**< Run counter with modulus of 2^8. */ + FSL_CTR_MOD_16, /**< Run counter with modulus of 2^16. */ + FSL_CTR_MOD_24, /**< Run counter with modulus of 2^24. */ + FSL_CTR_MOD_32, /**< Run counter with modulus of 2^32. */ + FSL_CTR_MOD_40, /**< Run counter with modulus of 2^40. */ + FSL_CTR_MOD_48, /**< Run counter with modulus of 2^48. */ + FSL_CTR_MOD_56, /**< Run counter with modulus of 2^56. */ + FSL_CTR_MOD_64, /**< Run counter with modulus of 2^64. */ + FSL_CTR_MOD_72, /**< Run counter with modulus of 2^72. */ + FSL_CTR_MOD_80, /**< Run counter with modulus of 2^80. */ + FSL_CTR_MOD_88, /**< Run counter with modulus of 2^88. */ + FSL_CTR_MOD_96, /**< Run counter with modulus of 2^96. */ + FSL_CTR_MOD_104, /**< Run counter with modulus of 2^104. */ + FSL_CTR_MOD_112, /**< Run counter with modulus of 2^112. */ + FSL_CTR_MOD_120, /**< Run counter with modulus of 2^120. */ + FSL_CTR_MOD_128 /**< Run counter with modulus of 2^128. */ +} fsl_shw_ctr_mod_t; + + +/** + * A work type associated with a work/result queue request. + */ +typedef enum shw_work_type_t +{ + SHW_WORK_GET_RANDOM = 1, /**< fsl_shw_get_random() request. */ + SHW_WORK_ADD_RANDOM, /**< fsl_shw_add_entropy() request. */ +} shw_work_type_t; + + +/** + * Permissions flags for Secure Partitions + */ +typedef enum fsl_shw_permission_t +{ +/** SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */ + FSL_PERM_NO_ZEROIZE = 0x80000000, +/** SCM Access Permission: Enforce trusted key read in */ + FSL_PERM_TRUSTED_KEY_READ = 0x40000000, +/** SCM Access Permission: Ignore Supervisor/User mode in permission determination */ + FSL_PERM_HD_S = 0x00000800, +/** SCM Access Permission: Allow Read Access to Host Domain */ + FSL_PERM_HD_R = 0x00000400, +/** SCM Access Permission: Allow Write Access to Host Domain */ + FSL_PERM_HD_W = 0x00000200, +/** SCM Access Permission: Allow Execute Access to Host Domain */ + FSL_PERM_HD_X = 0x00000100, +/** SCM Access Permission: Allow Read Access to Trusted Host Domain */ + FSL_PERM_TH_R = 0x00000040, +/** SCM Access Permission: Allow Write Access to Trusted Host Domain */ + FSL_PERM_TH_W = 0x00000020, +/** SCM Access Permission: Allow Read Access to Other/World Domain */ + FSL_PERM_OT_R = 0x00000004, +/** SCM Access Permission: Allow Write Access to Other/World Domain */ + FSL_PERM_OT_W = 0x00000002, +/** SCM Access Permission: Allow Execute Access to Other/World Domain */ + FSL_PERM_OT_X = 0x00000001, +} fsl_shw_permission_t; + +/*! + * Select the cypher mode to use for partition cover/uncover operations. + * + * They currently map directly to the values used in the SCC2 driver, but this + * is not guarinteed behavior. + */ +typedef enum fsl_shw_cypher_mode_t +{ + FSL_SHW_CYPHER_MODE_ECB = 1, /*!< ECB mode */ + FSL_SHW_CYPHER_MODE_CBC = 2, /*!< CBC mode */ +} fsl_shw_cypher_mode_t; + +/*! + * Which platform key should be presented for cryptographic use. + */ +typedef enum fsl_shw_pf_key_t { + FSL_SHW_PF_KEY_IIM, /*!< Present fused IIM key */ + FSL_SHW_PF_KEY_PRG, /*!< Present Program key */ + FSL_SHW_PF_KEY_IIM_PRG, /*!< Present IIM ^ Program key */ + FSL_SHW_PF_KEY_IIM_RND, /*!< Present Random key */ + FSL_SHW_PF_KEY_RND, /*!< Present IIM ^ Random key */ +} fsl_shw_pf_key_t; + +/*! + * The various security tamper events + */ +typedef enum fsl_shw_tamper_t { + FSL_SHW_TAMPER_NONE, /*!< No error detected */ + FSL_SHW_TAMPER_WTD, /*!< wire-mesh tampering det */ + FSL_SHW_TAMPER_ETBD, /*!< ext tampering det: input B */ + FSL_SHW_TAMPER_ETAD, /*!< ext tampering det: input A */ + FSL_SHW_TAMPER_EBD, /*!< external boot detected */ + FSL_SHW_TAMPER_SAD, /*!< security alarm detected */ + FSL_SHW_TAMPER_TTD, /*!< temperature tampering det */ + FSL_SHW_TAMPER_CTD, /*!< clock tampering det */ + FSL_SHW_TAMPER_VTD, /*!< voltage tampering det */ + FSL_SHW_TAMPER_MCO, /*!< monotonic counter overflow */ + FSL_SHW_TAMPER_TCO, /*!< time counter overflow */ +} fsl_shw_tamper_t; + +/* + * Structure passed during user ioctl() calls to manage data stored in secure + * partitions. + */ + +typedef struct scc_region_t { + uint32_t partition_base; /*!< Base address of partition */ + uint32_t offset; /*!< Byte offset into partition */ + uint32_t length; /*!< Number of bytes in request */ + uint8_t *black_data; /*!< Address of cipher text */ + uint64_t owner_id; /*!< user's secret */ + fsl_shw_cypher_mode_t cypher_mode; /*!< ECB or CBC */ + uint32_t IV[4]; /*!< IV for CBC mode */ +} scc_region_t; + +/****************************************************************************** + * Data Structures + *****************************************************************************/ + +/** + * Initialization Object + */ +typedef struct fsl_sho_ibo +{ +} fsl_sho_ibo_t; + + +/** + * Common Entry structure for work queues, results queues. + */ +typedef struct shw_queue_entry_t { + struct shw_queue_entry_t* next; /**< Next entry in queue. */ + struct fsl_shw_uco_t* user_ctx; /**< Associated user context. */ + uint32_t flags; /**< User context flags at time of request. */ + void (*callback)(struct fsl_shw_uco_t* uco); /**< Any callback request. */ + uint32_t user_ref; /**< User's reference for this request. */ + fsl_shw_return_t code; /**< FSL SHW result of this operation. */ + uint32_t detail1; /**< Any extra error info. */ + uint32_t detail2; /**< More any extra error info. */ + void* user_mode_req; /**< Pointer into user space. */ + uint32_t (*postprocess)(struct shw_queue_entry_t* q); /**< (internal) + function to call + when this operation + completes. + */ +} shw_queue_entry_t; + + +/** + * A queue. Fields must be initialized to NULL before use. + */ +typedef struct shw_queue_t +{ + struct shw_queue_entry_t* head; /**< First entry in queue. */ + struct shw_queue_entry_t* tail; /**< Last entry. */ +} shw_queue_t; + + +/** + * Secure Partition information + */ +typedef struct fsl_shw_spo_t +{ + uint32_t user_base; + void* kernel_base; + struct fsl_shw_spo_t* next; +} fsl_shw_spo_t; + + +/* REQ-FSLSHW-PINTFC-COA-UCO-001 */ +/** + * User Context Object + */ +typedef struct fsl_shw_uco_t +{ + int openfd; /**< user-mode file descriptor */ + uint32_t user_ref; /**< User's reference */ + void (*callback)(struct fsl_shw_uco_t* uco); /**< User's callback fn */ + uint32_t flags; /**< from fsl_shw_user_ctx_flags_t */ + unsigned pool_size; /**< maximum size of user result pool */ +#ifdef __KERNEL__ + shw_queue_t result_pool; /**< where non-blocking results go */ + os_process_handle_t process; /**< remember for signalling User mode */ + fsl_shw_spo_t* partition; /**< chain of secure partitions owned by + the user */ +#endif + struct fsl_shw_uco_t* next; /**< To allow user-mode chaining of contexts, + for signalling and in kernel, to link user + contexts. */ + fsl_shw_pf_key_t wrap_key; /*!< What key for ciphering T */ +} fsl_shw_uco_t; + + +/* REQ-FSLSHW-PINTFC-API-GEN-006 ?? */ +/** + * Result object + */ +typedef struct fsl_shw_result_t +{ + uint32_t user_ref; /**< User's reference at time of request. */ + fsl_shw_return_t code; /**< Return code from request. */ + uint32_t detail1; /**< Extra error info. Unused in SHW driver. */ + uint32_t detail2; /**< Extra error info. Unused in SHW driver. */ + void* user_req; /**< Pointer to original user request. */ +} fsl_shw_result_t; + + +/** + * Keystore Object + */ +typedef struct fsl_shw_kso_t +{ +#ifdef __KERNEL__ + os_lock_t lock; /**< Pointer to lock that controls access to + the keystore. */ +#endif + void* user_data; /**< Pointer to user structure that handles + the internals of the keystore. */ + fsl_shw_return_t (*data_init) (fsl_shw_uco_t* user_ctx, + void** user_data); + void (*data_cleanup) (fsl_shw_uco_t* user_ctx, + void** user_data); + fsl_shw_return_t (*slot_verify_access)(void* user_data, uint64_t owner_id, + uint32_t slot); + fsl_shw_return_t (*slot_alloc) (void* user_data, uint32_t size_bytes, + uint64_t owner_id, uint32_t* slot); + fsl_shw_return_t (*slot_dealloc) (void* user_data, + uint64_t owner_id, uint32_t slot); + void* (*slot_get_address) (void* user_data, uint32_t slot); + uint32_t (*slot_get_base) (void* user_data, uint32_t slot); + uint32_t (*slot_get_offset) (void* user_data, uint32_t slot); + uint32_t (*slot_get_slot_size) (void* user_data, uint32_t slot); +} fsl_shw_kso_t; + + +/* REQ-FSLSHW-PINTFC-COA-SKO-001 */ +/** + * Secret Key Context Object + */ +typedef struct fsl_shw_sko_t +{ + uint32_t flags; /**< Flags from #fsl_shw_sym_ctx_flags_t. */ + fsl_shw_key_alg_t algorithm; /**< Algorithm for this key. */ + key_userid_t userid; /**< User's identifying value for Black key. */ + uint32_t handle; /**< Reference in SCC driver for Red key. */ + uint16_t key_length; /**< Length of stored key, in bytes. */ + uint8_t key[64]; /**< Bytes of stored key. */ + struct fsl_shw_kso_t* keystore; /**< If present, key is in keystore */ + fsl_shw_pf_key_t pf_key; /*!< What key to select for use when this key + is doing ciphering. If FSL_SHW_PF_KEY_PRG + or FSL_SHW_PF_KEY_PRG_IIM is the value, then + a 'present' or 'established' key will be + programed into the PK. */ +} fsl_shw_sko_t; + + +/* REQ-FSLSHW-PINTFC-COA-CO-001 */ +/** + * Platform Capability Object + * + * Pointer to this structure is returned by fsl_shw_get_capabilities() and + * queried with the various fsl_shw_pco_() functions. + */ +typedef struct fsl_shw_pco_t +{ + int api_major; /**< Major version number for API. */ + int api_minor; /**< Minor version number for API. */ + int driver_major; /**< Major version of some driver. */ + int driver_minor; /**< Minor version of some driver. */ + unsigned sym_algorithm_count; /**< Number of sym_algorithms. */ + fsl_shw_key_alg_t* sym_algorithms; /**< Pointer to array. */ + unsigned sym_mode_count; /**< Number of sym_modes. */ + fsl_shw_sym_mode_t* sym_modes; /**< Pointer to array. */ + unsigned hash_algorithm_count; /**< Number of hash_algorithms. */ + fsl_shw_hash_alg_t* hash_algorithms; /**< Pointer to array */ + uint8_t sym_support[5][4]; /**< indexed by key alg then mode */ + + int scc_driver_major; + int scc_driver_minor; + int scm_version; /**< Version from SCM Configuration register */ + int smn_version; /**< Version from SMN Status register */ + int block_size_bytes; /**< Number of bytes per block of RAM; also + block size of the crypto algorithm. */ + union { + struct scc_info { + int black_ram_size_blocks; /**< Number of blocks of Black RAM */ + int red_ram_size_blocks; /**< Number of blocks of Red RAM */ + } scc_info; + struct scc2_info { + int partition_size_bytes; /**< Number of bytes in each partition */ + int partition_count; /**< Number of partitions on this platform */ + } scc2_info; + } u; +} fsl_shw_pco_t; + + +/* REQ-FSLSHW-PINTFC-COA-HCO-001 */ +/** + * Hash Context Object + */ +typedef struct fsl_shw_hco_t /* fsl_shw_hash_context_object */ +{ + fsl_shw_hash_alg_t algorithm; /**< Algorithm for this context. */ + uint32_t flags; /**< Flags from + #fsl_shw_hash_ctx_flags_t. */ + uint8_t digest_length; /**< hash result length in bytes */ + uint8_t context_length; /**< Context length in bytes */ + uint8_t context_register_length; /**< in bytes */ + uint32_t context[9]; /**< largest digest + msg size */ +} fsl_shw_hco_t; + + +/* REQ-FSLSHW-PINTFC-COA-HCO-001 */ +/** + * HMAC Context Object + */ +typedef struct fsl_shw_hmco_t /* fsl_shw_hmac_context_object */ +{ + fsl_shw_hash_alg_t algorithm; /**< Hash algorithm for the HMAC. */ + uint32_t flags; /**< Flags from + #fsl_shw_hmac_ctx_flags_t. */ + uint8_t digest_length; /**< in bytes */ + uint8_t context_length; /**< in bytes */ + uint8_t context_register_length; /**< in bytes */ + uint32_t ongoing_context[9]; /**< largest digest + msg + size */ + uint32_t inner_precompute[9]; /**< largest digest + msg + size */ + uint32_t outer_precompute[9]; /**< largest digest + msg + size */ +} fsl_shw_hmco_t; + + +/* REQ-FSLSHW-PINTFC-COA-SCCO-001 */ +/** + * Symmetric Crypto Context Object Context Object + */ +typedef struct fsl_shw_scco_t +{ + uint32_t flags; /**< Flags from #fsl_shw_sym_ctx_flags_t. */ + unsigned block_size_bytes; /**< Both block and ctx size */ + fsl_shw_sym_mode_t mode; /**< Symmetric mode for this context. */ + /* Could put modulus plus 16-octet context in union with arc4 + sbox+ptrs... */ + fsl_shw_ctr_mod_t modulus_exp; /**< Exponent value for CTR modulus */ + uint8_t context[8]; /**< Stored context. Large enough + for 3DES. */ +} fsl_shw_scco_t; + + +/** + * Authenticate-Cipher Context Object + + * An object for controlling the function of, and holding information about, + * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and + * #fsl_shw_auth_decrypt(). + */ +typedef struct fsl_shw_acco_t +{ + uint32_t flags; /**< See #fsl_shw_auth_ctx_flags_t for + meanings */ + fsl_shw_acc_mode_t mode; /**< CCM only */ + uint8_t mac_length; /**< User's value for length */ + unsigned q_length; /**< NIST parameter - */ + fsl_shw_scco_t cipher_ctx_info; /**< For running + encrypt/decrypt. */ + union { + fsl_shw_scco_t CCM_ctx_info; /**< For running the CBC in + AES-CCM. */ + fsl_shw_hco_t hash_ctx_info; /**< For running the hash */ + } auth_info; /**< "auth" info struct */ + uint8_t unencrypted_mac[16]; /**< max block size... */ +} fsl_shw_acco_t; + + +/** + * Common header in request structures between User-mode API and SHW driver. + */ +struct shw_req_header { + uint32_t flags; /**< Flags - from user-mode context. */ + uint32_t user_ref; /**< Reference - from user-mode context. */ + fsl_shw_return_t code; /**< Result code for operation. */ +}; + +/** + * Used by user-mode API to retrieve completed non-blocking results in + * SHW_USER_REQ_GET_RESULTS ioctl(). + */ +struct results_req { + struct shw_req_header hdr; /**< Boilerplate. */ + unsigned requested; /**< number of results requested, */ + unsigned actual; /**< number of results obtained. */ + fsl_shw_result_t *results; /**< pointer to memory to hold results. */ +}; + + +/** + * Used by user-mode API to retrieve hardware capabilities in + * SHW_USER_REQ_GET_CAPABILITIES ioctl(). + */ +struct capabilities_req { + struct shw_req_header hdr; /**< Boilerplate. */ + unsigned size; /**< Size, in bytes, capabilities. */ + fsl_shw_pco_t* capabilities; /**< Place to copy out the info. */ +}; + + +/** + * Used by user-mode API to get a random number + */ +struct get_random_req { + struct shw_req_header hdr; /**< Boilerplate. */ + unsigned size; /**< Size, in bytes, of random. */ + uint8_t* random; /**< Place to copy out the random number. */ +}; + + +/** + * Used by API to add entropy to a random number generator + */ +struct add_entropy_req { + struct shw_req_header hdr; /**< Boilerplate. */ + unsigned size; /**< Size, in bytes, of entropy. */ + uint8_t* entropy; /**< Location of the entropy to be added. */ +}; + + +/****************************************************************************** + * External variables + *****************************************************************************/ +#ifdef __KERNEL__ +extern os_lock_t shw_queue_lock; + +extern fsl_shw_uco_t* user_list; +#endif + + +/****************************************************************************** + * Access Macros for Objects + *****************************************************************************/ +/** + * Get FSL SHW API version + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the API is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the API is to be stored. + */ +#define fsl_shw_pco_get_version(pcobject, pcmajor, pcminor) \ +do { \ + *(pcmajor) = (pcobject)->api_major; \ + *(pcminor) = (pcobject)->api_minor; \ +} while (0) + + +/** + * Get underlying driver version. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the driver is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the driver is to be stored. + */ +#define fsl_shw_pco_get_driver_version(pcobject, pcmajor, pcminor) \ +do { \ + *(pcmajor) = (pcobject)->driver_major; \ + *(pcminor) = (pcobject)->driver_minor; \ +} while (0) + + +/** + * Get list of symmetric algorithms supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcalgorithms A pointer to where to store the location of + * the list of algorithms. + * @param[out] pcacount A pointer to where to store the number of + * algorithms in the list at @a algorithms. + */ +#define fsl_shw_pco_get_sym_algorithms(pcobject, pcalgorithms, pcacount) \ +do { \ + *(pcalgorithms) = (pcobject)->sym_algorithms; \ + *(pcacount) = (pcobject)->sym_algorithm_count; \ +} while (0) + + +/** + * Get list of symmetric modes supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] gsmodes A pointer to where to store the location of + * the list of modes. + * @param[out] gsacount A pointer to where to store the number of + * algorithms in the list at @a modes. + */ +#define fsl_shw_pco_get_sym_modes(pcobject, gsmodes, gsacount) \ +do { \ + *(gsmodes) = (pcobject)->sym_modes; \ + *(gsacount) = (pcobject)->sym_mode_count; \ +} while (0) + + +/** + * Get list of hash algorithms supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] gsalgorithms A pointer which will be set to the list of + * algorithms. + * @param[out] gsacount The number of algorithms in the list at @a + * algorithms. + */ +#define fsl_shw_pco_get_hash_algorithms(pcobject, gsalgorithms, gsacount) \ +do { \ + *(gsalgorithms) = (pcobject)->hash_algorithms; \ + *(gsacount) = (pcobject)->hash_algorithm_count; \ +} while (0) + + +/** + * Determine whether the combination of a given symmetric algorithm and a given + * mode is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param pcalg A Symmetric Cipher algorithm. + * @param pcmode A Symmetric Cipher mode. + * + * @return 0 if combination is not supported, non-zero if supported. + */ +#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__) +#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode) \ + ((pcobject)->sym_support[pcalg][pcmode]) +#else +#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode) \ + 0 +#endif + +/** + * Determine whether a given Encryption-Authentication mode is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param pcmode The Authentication mode. + * + * @return 0 if mode is not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_auth_supported(pcobject, pcmode) \ + 0 + + +/** + * Determine whether Black Keys (key establishment / wrapping) is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return 0 if wrapping is not supported, non-zero if supported. + */ +#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__) +#define fsl_shw_pco_check_black_key_supported(pcobject) \ + 1 +#else +#define fsl_shw_pco_check_black_key_supported(pcobject) \ + 0 + +#endif + +/*! + * Determine whether Programmed Key features are available + * + * @param pcobject The Platform Capabilities Object to query. + * + * @return 1 if Programmed Key features are available, otherwise zero. + */ +#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__) +#define fsl_shw_pco_check_pk_supported(pcobject) \ + 1 +#else +#define fsl_shw_pco_check_pk_supported(pcobject) \ + 0 +#endif + +/*! + * Determine whether Software Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Software key features are available, otherwise zero. + */ +#if defined(FSL_HAVE_DRYICE) && defined(__KERNEL__) +#define fsl_shw_pco_check_sw_keys_supported(pcobject) \ + 1 +#else +#define fsl_shw_pco_check_sw_keys_supported(pcobject) \ + 0 +#endif + +/*! + * Get FSL SHW SCC driver version + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the SCC driver is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the SCC driver is to be stored. + */ +#define fsl_shw_pco_get_scc_driver_version(pcobject, pcmajor, pcminor) \ +{ \ + *(pcmajor) = (pcobject)->scc_driver_major; \ + *(pcminor) = (pcobject)->scc_driver_minor; \ +} + + +/** + * Get SCM hardware version + * + * @param pcobject The Platform Capababilities Object to query. + * @return The SCM hardware version + */ +#define fsl_shw_pco_get_scm_version(pcobject) \ + ((pcobject)->scm_version) + + +/** + * Get SMN hardware version + * + * @param pcobject The Platform Capababilities Object to query. + * @return The SMN hardware version + */ +#define fsl_shw_pco_get_smn_version(pcobject) \ + ((pcobject)->smn_version) + + +/** + * Get the size of an SCM block, in bytes + * + * @param pcobject The Platform Capababilities Object to query. + * @return The size of an SCM block, in bytes. + */ +#define fsl_shw_pco_get_scm_block_size(pcobject) \ + ((pcobject)->block_size_bytes) + + +/** + * Get size of Black and Red RAM memory + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] black_size A pointer to where the size of the Black RAM, in + * blocks, is to be placed. + * @param[out] red_size A pointer to where the size of the Red RAM, in + * blocks, is to be placed. + */ +#define fsl_shw_pco_get_smn_size(pcobject, black_size, red_size) \ +{ \ + if ((pcobject)->scm_version == 1) { \ + *(black_size) = (pcobject)->u.scc_info.black_ram_size_blocks; \ + *(red_size) = (pcobject)->u.scc_info.red_ram_size_blocks; \ + } else { \ + *(black_size) = 0; \ + *(red_size) = 0; \ + } \ +} + + +/** + * Determine whether Secure Partitions are supported + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return 0 if secure partitions are not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_spo_supported(pcobject) \ + ((pcobject)->scm_version == 2) + + +/** + * Get the size of a Secure Partitions + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return Partition size, in bytes. 0 if Secure Partitions not supported. + */ +#define fsl_shw_pco_get_spo_size_bytes(pcobject) \ + (((pcobject)->scm_version == 2) ? \ + ((pcobject)->u.scc2_info.partition_size_bytes) : 0 ) \ + + +/** + * Get the number of Secure Partitions on this platform + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return Number of partitions. 0 if Secure Paritions not supported. Note + * that this returns the total number of partitions, not all may be + * available to the user. + */ +#define fsl_shw_pco_get_spo_count(pcobject) \ + (((pcobject)->scm_version == 2) ? \ + ((pcobject)->u.scc2_info.partition_count) : 0 ) \ + + +/*! + * Initialize a Secret Key Object. + * + * This function must be called before performing any other operation with + * the Object. + * + * @param skobject The Secret Key Object to be initialized. + * @param skalgorithm DES, AES, etc. + * + */ +#define fsl_shw_sko_init(skobject,skalgorithm) \ +{ \ + fsl_shw_sko_t* skop = skobject; \ + \ + skop->algorithm = skalgorithm; \ + skop->flags = 0; \ + skop->keystore = NULL; \ + skop->pf_key = FSL_SHW_PF_KEY_PRG; \ +} + +/*! + * Initialize a Secret Key Object to use a Platform Key register. + * + * This function must be called before performing any other operation with + * the Object. + * + * @param skobject The Secret Key Object to be initialized. + * @param skalgorithm DES, AES, etc. + * @param skhwkey one of the fsl_shw_pf_key_t values. + * + */ +#define fsl_shw_sko_init_pf_key(skobject,skalgorithm,skhwkey) \ +{ \ + fsl_shw_sko_t* skop = skobject; \ + fsl_shw_key_alg_t alg = skalgorithm; \ + fsl_shw_pf_key_t key = skhwkey; \ + \ + skop->algorithm = alg; \ + if (alg == FSL_KEY_ALG_TDES) { \ + skop->key_length = 21; \ + } \ + skop->keystore = NULL; \ + skop->flags = FSL_SKO_KEY_SELECT_PF_KEY; \ + skop->pf_key = key; \ + if ((key == FSL_SHW_PF_KEY_IIM) || (key == FSL_SHW_PF_KEY_PRG) \ + || (key == FSL_SHW_PF_KEY_IIM_PRG) \ + || (key == FSL_SHW_PF_KEY_IIM_RND) \ + || (key == FSL_SHW_PF_KEY_RND)) { \ + skop->flags |= FSL_SKO_KEY_ESTABLISHED; \ + } \ +} + +/*! + * Store a cleartext key in the key object. + * + * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag and + * resetting the #FSL_SKO_KEY_ESTABLISHED flag. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skkey A pointer to the beginning of the key. + * @param skkeylen The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +#define fsl_shw_sko_set_key(skobject, skkey, skkeylen) \ +{ \ + (skobject)->key_length = skkeylen; \ + copy_bytes((skobject)->key, skkey, skkeylen); \ + (skobject)->flags |= FSL_SKO_KEY_PRESENT; \ + (skobject)->flags &= ~FSL_SKO_KEY_ESTABLISHED; \ +} + +/** + * Set a size for the key. + * + * This function would normally be used when the user wants the key to be + * generated from a random source. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skkeylen The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +#define fsl_shw_sko_set_key_length(skobject, skkeylen) \ + (skobject)->key_length = skkeylen; + + +/** + * Set the User ID associated with the key. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skuserid The User ID to identify authorized users of the key. + */ +#define fsl_shw_sko_set_user_id(skobject, skuserid) \ + (skobject)->userid = (skuserid) + +/** + * Establish a user Keystore to hold the key. + */ +#define fsl_shw_sko_set_keystore(skobject, user_keystore) \ + (skobject)->keystore = (user_keystore) + + + +/** + * Set the establish key handle into a key object. + * + * The @a userid field will be used to validate the access to the unwrapped + * key. This feature is not available for all platforms, nor for all + * algorithms and modes. + * + * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT flag + * will be cleared). + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skuserid The User ID to verify this user is an authorized user of + * the key. + * @param skhandle A @a handle from #fsl_shw_sko_get_established_info. + */ +#define fsl_shw_sko_set_established_info(skobject, skuserid, skhandle) \ +{ \ + (skobject)->userid = (skuserid); \ + (skobject)->handle = (skhandle); \ + (skobject)->flags |= FSL_SKO_KEY_ESTABLISHED; \ + (skobject)->flags &= \ + ~(FSL_SKO_KEY_PRESENT); \ +} + + +/** + * Retrieve the established-key handle from a key object. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skhandle The location to store the @a handle of the unwrapped + * key. + */ +#define fsl_shw_sko_get_established_info(skobject, skhandle) \ + *(skhandle) = (skobject)->handle + + +/** + * Extract the algorithm from a key object. + * + * @param skobject The Key Object to be queried. + * @param[out] skalgorithm A pointer to the location to store the algorithm. + */ +#define fsl_shw_sko_get_algorithm(skobject, skalgorithm) \ + *(skalgorithm) = (skobject)->algorithm + + +/** + * Retrieve the cleartext key from a key object that is stored in a user + * keystore. + * + * @param skobject The Key Object to be queried. + * @param[out] skkey A pointer to the location to store the key. NULL + * if the key is not stored in a user keystore. + */ +#define fsl_shw_sko_get_key(skobject, skkey) \ +{ \ + fsl_shw_kso_t* keystore = (skobject)->keystore; \ + if (keystore != NULL) { \ + *(skkey) = keystore->slot_get_address(keystore->user_data, \ + (skobject)->handle); \ + } else { \ + *(skkey) = NULL; \ + } \ +} + + +/*! + * Determine the size of a wrapped key based upon the cleartext key's length. + * + * This function can be used to calculate the number of octets that + * #fsl_shw_extract_key() will write into the location at @a covered_key. + * + * If zero is returned at @a length, this means that the key length in + * @a key_info is not supported. + * + * @param wkeyinfo Information about a key to be wrapped. + * @param wkeylen Location to store the length of a wrapped + * version of the key in @a key_info. + */ +#define fsl_shw_sko_calculate_wrapped_size(wkeyinfo, wkeylen) \ +{ \ + register fsl_shw_sko_t* kp = wkeyinfo; \ + register uint32_t kl = kp->key_length; \ + int key_blocks; \ + int base_size = 35; /* ICV + T' + ALG + LEN + FLAGS */ \ + \ + if (kp->flags & FSL_SKO_KEY_SELECT_PF_KEY) { \ + kl = 21; /* 168-bit 3DES key */ \ + } \ + key_blocks = (kl + 7) / 8; \ + /* Round length up to 3DES block size for CBC mode */ \ + *(wkeylen) = base_size + 8 * key_blocks; \ +} + +/*! + * Set some flags in the key object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skflags (One or more) ORed members of #fsl_shw_key_flags_t which + * are to be set. + */ +#define fsl_shw_sko_set_flags(skobject, skflags) \ + (skobject)->flags |= (skflags) + + +/** + * Clear some flags in the key object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skflags (One or more) ORed members of #fsl_shw_key_flags_t + * which are to be reset. + */ +#define fsl_shw_sko_clear_flags(skobject, skflags) \ + (skobject)->flags &= ~(skflags) + +/** + * Initialize a User Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the User Context Object to initial values, and set the size + * of the results pool. The mode will be set to a default of + * #FSL_UCO_BLOCKING_MODE. + * + * When using non-blocking operations, this sets the maximum number of + * operations which can be outstanding. This number includes the counts of + * operations waiting to start, operation(s) being performed, and results which + * have not been retrieved. + * + * Changes to this value are ignored once user registration has completed. It + * should be set to 1 if only blocking operations will ever be performed. + * + * @param ucontext The User Context object to operate on. + * @param usize The maximum number of operations which can be + * outstanding. + */ +#ifdef __KERNEL__ + +#define fsl_shw_uco_init(ucontext, usize) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->pool_size = usize; \ + (uco)->flags = FSL_UCO_BLOCKING_MODE | FSL_UCO_CONTEXT_CHANGED; \ + (uco)->openfd = -1; \ + (uco)->callback = NULL; \ + (uco)->partition = NULL; \ + (uco)->wrap_key = FSL_SHW_PF_KEY_IIM; \ +} while (0) + +#else /* __KERNEL__ */ + +#define fsl_shw_uco_init(ucontext, usize) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->pool_size = usize; \ + (uco)->flags = FSL_UCO_BLOCKING_MODE | FSL_UCO_CONTEXT_CHANGED; \ + (uco)->openfd = -1; \ + (uco)->callback = NULL; \ + (uco)->wrap_key = FSL_SHW_PF_KEY_IIM; \ +} while (0) + +#endif /* __KERNEL__ */ + + +/** + * Set the User Reference for the User Context. + * + * @param ucontext The User Context object to operate on. + * @param uref A value which will be passed back with a result. + */ +#define fsl_shw_uco_set_reference(ucontext, uref) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->user_ref = uref; \ + (uco)->flags |= FSL_UCO_CONTEXT_CHANGED; \ +} while (0) + + +/** + * Set the User Reference for the User Context. + * + * @param ucontext The User Context object to operate on. + * @param ucallback The function the API will invoke when an operation + * completes. + */ +#define fsl_shw_uco_set_callback(ucontext, ucallback) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->callback = ucallback; \ + (uco)->flags |= FSL_UCO_CONTEXT_CHANGED; \ +} while (0) + +/** + * Set flags in the User Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param ucontext The User Context object to operate on. + * @param uflags ORed values from #fsl_shw_user_ctx_flags_t. + */ +#define fsl_shw_uco_set_flags(ucontext, uflags) \ + (ucontext)->flags |= (uflags) | FSL_UCO_CONTEXT_CHANGED + + +/** + * Clear flags in the User Context. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param ucontext The User Context object to operate on. + * @param uflags ORed values from #fsl_shw_user_ctx_flags_t. + */ +#define fsl_shw_uco_clear_flags(ucontext, uflags) \ +do { \ + fsl_shw_uco_t* uco = ucontext; \ + \ + (uco)->flags &= ~(uflags); \ + (uco)->flags |= FSL_UCO_CONTEXT_CHANGED; \ +} while (0) + + +/** + * Retrieve the reference value from a Result Object. + * + * @param robject The result object to query. + * + * @return The reference associated with the request. + */ +#define fsl_shw_ro_get_reference(robject) \ + (robject)->user_ref + + +/** + * Retrieve the status code from a Result Object. + * + * @param robject The result object to query. + * + * @return The status of the request. + */ +#define fsl_shw_ro_get_status(robject) \ + (robject)->code + + + +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-004 */ +/** + * Initialize a Hash Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the hash + * context object. + * + * @param hcobject The hash context to operate upon. + * @param hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +#define fsl_shw_hco_init(hcobject, hcalgorithm) \ +do { \ + (hcobject)->algorithm = hcalgorithm; \ + (hcobject)->flags = 0; \ + switch (hcalgorithm) { \ + case FSL_HASH_ALG_MD5: \ + (hcobject)->digest_length = 16; \ + (hcobject)->context_length = 16; \ + (hcobject)->context_register_length = 24; \ + break; \ + case FSL_HASH_ALG_SHA1: \ + (hcobject)->digest_length = 20; \ + (hcobject)->context_length = 20; \ + (hcobject)->context_register_length = 24; \ + break; \ + case FSL_HASH_ALG_SHA224: \ + (hcobject)->digest_length = 28; \ + (hcobject)->context_length = 32; \ + (hcobject)->context_register_length = 36; \ + break; \ + case FSL_HASH_ALG_SHA256: \ + (hcobject)->digest_length = 32; \ + (hcobject)->context_length = 32; \ + (hcobject)->context_register_length = 36; \ + break; \ + default: \ + /* error ! */ \ + (hcobject)->digest_length = 1; \ + (hcobject)->context_length = 1; \ + (hcobject)->context_register_length = 1; \ + break; \ + } \ +} while (0) + + +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-001 */ +/** + * Get the current hash value and message length from the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hcobject The hash context to query. + * @param[out] hccontext Pointer to the location of @a length octets where to + * store a copy of the current value of the digest. + * @param hcclength Number of octets of hash value to copy. + * @param[out] hcmsglen Pointer to the location to store the number of octets + * already hashed. + */ +#define fsl_shw_hco_get_digest(hcobject, hccontext, hcclength, hcmsglen) \ +do { \ + memcpy(hccontext, (hcobject)->context, hcclength); \ + if ((hcobject)->algorithm == FSL_HASH_ALG_SHA224 \ + || (hcobject)->algorithm == FSL_HASH_ALG_SHA256) { \ + *(hcmsglen) = (hcobject)->context[8]; \ + } else { \ + *(hcmsglen) = (hcobject)->context[5]; \ + } \ +} while (0) + + +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-002 */ +/** + * Get the hash algorithm from the hash context object. + * + * @param hcobject The hash context to query. + * @param[out] hcalgorithm Pointer to where the algorithm is to be stored. + */ +#define fsl_shw_hco_get_info(hcobject, hcalgorithm) \ +do { \ + *(hcalgorithm) = (hcobject)->algorithm; \ +} while (0) + + +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-003 */ +/* REQ-FSL-SHW-PINTFC-API-BASIC-HASH-004 */ +/** + * Set the current hash value and message length in the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hcobject The hash context to operate upon. + * @param hccontext Pointer to buffer of appropriate length to copy into + * the hash context object. + * @param hcmsglen The number of octets of the message which have + * already been hashed. + * + */ +#define fsl_shw_hco_set_digest(hcobject, hccontext, hcmsglen) \ +do { \ + memcpy((hcobject)->context, hccontext, (hcobject)->context_length); \ + if (((hcobject)->algorithm == FSL_HASH_ALG_SHA224) \ + || ((hcobject)->algorithm == FSL_HASH_ALG_SHA256)) { \ + (hcobject)->context[8] = hcmsglen; \ + } else { \ + (hcobject)->context[5] = hcmsglen; \ + } \ +} while (0) + + +/** + * Set flags in a Hash Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The hash context to be operated on. + * @param hcflags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +#define fsl_shw_hco_set_flags(hcobject, hcflags) \ + (hcobject)->flags |= (hcflags) + + +/** + * Clear flags in a Hash Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The hash context to be operated on. + * @param hcflags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +#define fsl_shw_hco_clear_flags(hcobject, hcflags) \ + (hcobject)->flags &= ~(hcflags) + + +/** + * Initialize an HMAC Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the HMAC + * context object. + * + * @param hcobject The HMAC context to operate upon. + * @param hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +#define fsl_shw_hmco_init(hcobject, hcalgorithm) \ + fsl_shw_hco_init(hcobject, hcalgorithm) + + +/** + * Set flags in an HMAC Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The HMAC context to be operated on. + * @param hcflags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +#define fsl_shw_hmco_set_flags(hcobject, hcflags) \ + (hcobject)->flags |= (hcflags) + + +/** + * Clear flags in an HMAC Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The HMAC context to be operated on. + * @param hcflags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +#define fsl_shw_hmco_clear_flags(hcobject, hcflags) \ + (hcobject)->flags &= ~(hcflags) + + +/** + * Initialize a Symmetric Cipher Context Object. + * + * This function must be called before performing any other operation with the + * Object. This will set the @a mode and @a algorithm and initialize the + * Object. + * + * @param scobject The context object to operate on. + * @param scalg The cipher algorithm this context will be used with. + * @param scmode #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc. + * + */ +#define fsl_shw_scco_init(scobject, scalg, scmode) \ +do { \ + register uint32_t bsb; /* block-size bytes */ \ + \ + switch (scalg) { \ + case FSL_KEY_ALG_AES: \ + bsb = 16; \ + break; \ + case FSL_KEY_ALG_DES: \ + /* fall through */ \ + case FSL_KEY_ALG_TDES: \ + bsb = 8; \ + break; \ + case FSL_KEY_ALG_ARC4: \ + bsb = 259; \ + break; \ + case FSL_KEY_ALG_HMAC: \ + bsb = 1; /* meaningless */ \ + break; \ + default: \ + bsb = 00; \ + } \ + (scobject)->block_size_bytes = bsb; \ + (scobject)->mode = scmode; \ + (scobject)->flags = 0; \ +} while (0) + + +/** + * Set the flags for a Symmetric Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param scobject The context object to operate on. + * @param scflags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +#define fsl_shw_scco_set_flags(scobject, scflags) \ + (scobject)->flags |= (scflags) + + +/** + * Clear some flags in a Symmetric Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param scobject The context object to operate on. + * @param scflags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +#define fsl_shw_scco_clear_flags(scobject, scflags) \ + (scobject)->flags &= ~(scflags) + + +/** + * Set the Context (IV) for a Symmetric Cipher Context. + * + * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the + * context (the S-Box and pointers) for ARC4. The full context size will + * be copied. + * + * @param scobject The context object to operate on. + * @param sccontext A pointer to the buffer which contains the context. + * + */ +#define fsl_shw_scco_set_context(scobject, sccontext) \ + memcpy((scobject)->context, sccontext, \ + (scobject)->block_size_bytes) + + +/** + * Get the Context for a Symmetric Cipher Context. + * + * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to + * retrieve context (the S-Box and pointers) for ARC4. The full context + * will be copied. + * + * @param scobject The context object to operate on. + * @param[out] sccontext Pointer to location where context will be stored. + */ +#define fsl_shw_scco_get_context(scobject, sccontext) \ + memcpy(sccontext, (scobject)->context, (scobject)->block_size_bytes) + + +/** + * Set the Counter Value for a Symmetric Cipher Context. + * + * This will set the Counter Value for CTR mode. + * + * @param scobject The context object to operate on. + * @param sccounter The starting counter value. The number of octets. + * copied will be the block size for the algorithm. + * @param scmodulus The modulus for controlling the incrementing of the + * counter. + * + */ +#define fsl_shw_scco_set_counter_info(scobject, sccounter, scmodulus) \ +do { \ + if ((sccounter) != NULL) { \ + memcpy((scobject)->context, sccounter, \ + (scobject)->block_size_bytes); \ + } \ + (scobject)->modulus_exp = scmodulus; \ +} while (0) + + +/** + * Get the Counter Value for a Symmetric Cipher Context. + * + * This will retrieve the Counter Value is for CTR mode. + * + * @param scobject The context object to query. + * @param[out] sccounter Pointer to location to store the current counter + * value. The number of octets copied will be the + * block size for the algorithm. + * @param[out] scmodulus Pointer to location to store the modulus. + * + */ +#define fsl_shw_scco_get_counter_info(scobject, sccounter, scmodulus) \ +do { \ + if ((sccounter) != NULL) { \ + memcpy(sccounter, (scobject)->context, \ + (scobject)->block_size_bytes); \ + } \ + if ((scmodulus) != NULL) { \ + *(scmodulus) = (scobject)->modulus_exp; \ + } \ +} while (0) + + +/** + * Initialize a Authentication-Cipher Context. + * + * @param acobject Pointer to object to operate on. + * @param acmode The mode for this object (only #FSL_ACC_MODE_CCM + * supported). + */ +#define fsl_shw_acco_init(acobject, acmode) \ +do { \ + (acobject)->flags = 0; \ + (acobject)->mode = (acmode); \ +} while (0) + + +/** + * Set the flags for a Authentication-Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param acobject Pointer to object to operate on. + * @param acflags The flags to set (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +#define fsl_shw_acco_set_flags(acobject, acflags) \ + (acobject)->flags |= (acflags) + + +/** + * Clear some flags in a Authentication-Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param acobject Pointer to object to operate on. + * @param acflags The flags to reset (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +#define fsl_shw_acco_clear_flags(acobject, acflags) \ + (acobject)->flags &= ~(acflags) + + +/** + * Set up the Authentication-Cipher Object for CCM mode. + * + * This will set the @a auth_object for CCM mode and save the @a ctr, + * and @a mac_length. This function can be called instead of + * #fsl_shw_acco_init(). + * + * The paramater @a ctr is Counter Block 0, (counter value 0), which is for the + * MAC. + * + * @param acobject Pointer to object to operate on. + * @param acalg Cipher algorithm. Only AES is supported. + * @param accounter The initial counter value. + * @param acmaclen The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_acco_set_ccm(acobject, acalg, accounter, acmaclen) \ + do { \ + (acobject)->flags = 0; \ + (acobject)->mode = FSL_ACC_MODE_CCM; \ + (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16; \ + (acobject)->cipher_ctx_info.block_size_bytes = 16; \ + (acobject)->mac_length = acmaclen; \ + fsl_shw_scco_set_counter_info(&(acobject)->cipher_ctx_info, accounter, \ + FSL_CTR_MOD_128); \ +} while (0) + + +/** + * Format the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will also set the IV and CTR values per Appendix A of NIST + * Special Publication 800-38C (May 2004). It will also perform the + * #fsl_shw_acco_set_ccm() operation with information derived from this set of + * parameters. + * + * Note this function assumes the algorithm is AES. It initializes the + * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the + * flags to be #FSL_ACCO_NIST_CCM. + * + * @param acobject Pointer to object to operate on. + * @param act The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + * @param acad Number of octets of Associated Data (may be zero). + * @param acq A value for the size of the length of @a q field. Valid + * values are 1-8. + * @param acN The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param acQ The value of Q (size of the payload in octets). + * + */ +#define fsl_shw_ccm_nist_format_ctr_and_iv(acobject, act, acad, acq, acN, acQ)\ + do { \ + uint64_t Q = acQ; \ + uint8_t bflag = ((acad)?0x40:0) | ((((act)-2)/2)<<3) | ((acq)-1); \ + unsigned i; \ + uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15; \ + (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16; \ + (acobject)->cipher_ctx_info.block_size_bytes = 16; \ + (acobject)->mode = FSL_ACC_MODE_CCM; \ + (acobject)->flags = FSL_ACCO_NIST_CCM; \ + \ + /* Store away the MAC length (after calculating actual value */ \ + (acobject)->mac_length = (act); \ + /* Set Flag field in Block 0 */ \ + *((acobject)->auth_info.CCM_ctx_info.context) = bflag; \ + /* Set Nonce field in Block 0 */ \ + memcpy((acobject)->auth_info.CCM_ctx_info.context+1, acN, \ + 15-(acq)); \ + /* Set Flag field in ctr */ \ + *((acobject)->cipher_ctx_info.context) = (acq)-1; \ + /* Update the Q (payload length) field of Block0 */ \ + (acobject)->q_length = acq; \ + for (i = 0; i < (acq); i++) { \ + *qptr-- = Q & 0xFF; \ + Q >>= 8; \ + } \ + /* Set the Nonce field of the ctr */ \ + memcpy((acobject)->cipher_ctx_info.context+1, acN, 15-(acq)); \ + /* Clear the block counter field of the ctr */ \ + memset((acobject)->cipher_ctx_info.context+16-(acq), 0, (acq)+1); \ + } while (0) + + +/** + * Update the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will set the IV and CTR values per Appendix A of NIST Special + * Publication 800-38C (May 2004). + * + * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has + * previously been called on the @a auth_object. + * + * @param acobject Pointer to object to operate on. + * @param acN The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param acQ The value of Q (size of the payload in octets). + * + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_ccm_nist_update_ctr_and_iv(acobject, acN, acQ) \ + do { \ + uint64_t Q = acQ; \ + unsigned i; \ + uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15; \ + \ + /* Update the Nonce field field of Block0 */ \ + memcpy((acobject)->auth_info.CCM_ctx_info.context+1, acN, \ + 15 - (acobject)->q_length); \ + /* Update the Q (payload length) field of Block0 */ \ + for (i = 0; i < (acobject)->q_length; i++) { \ + *qptr-- = Q & 0xFF; \ + Q >>= 8; \ + } \ + /* Update the Nonce field of the ctr */ \ + memcpy((acobject)->cipher_ctx_info.context+1, acN, \ + 15 - (acobject)->q_length); \ + } while (0) + + +/****************************************************************************** + * Library functions + *****************************************************************************/ +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-GEN-003 */ +/** + * Determine the hardware security capabilities of this platform. + * + * Though a user context object is passed into this function, it will always + * act in a non-blocking manner. + * + * @param user_ctx The user context which will be used for the query. + * + * @return A pointer to the capabilities object. + */ +extern fsl_shw_pco_t* fsl_shw_get_capabilities(fsl_shw_uco_t* user_ctx); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-GEN-004 */ +/** + * Create an association between the the user and the provider of the API. + * + * @param user_ctx The user context which will be used for this association. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t* user_ctx); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-GEN-005 */ +/** + * Destroy the association between the the user and the provider of the API. + * + * @param user_ctx The user context which is no longer needed. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t* user_ctx); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-GEN-006 */ +/** + * Retrieve results from earlier operations. + * + * @param user_ctx The user's context. + * @param result_size The number of array elements of @a results. + * @param[in,out] results Pointer to first of the (array of) locations to + * store results. + * @param[out] result_count Pointer to store the number of results which + * were returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t* user_ctx, + unsigned result_size, + fsl_shw_result_t results[], + unsigned* result_count); + +/** + * Place a key into a protected location for use only by cryptographic + * algorithms. + * + * This only needs to be used to a) unwrap a key, or b) set up a key which + * could be wrapped with a later call to #fsl_shw_extract_key(). Normal + * cleartext keys can simply be placed into #fsl_shw_sko_t key objects with + * #fsl_shw_sko_set_key() and used directly. + * + * The maximum key size supported for wrapped/unwrapped keys is 32 octets. + * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC + * key based on SHA-256.) The key size is determined by the @a key_info. The + * expected length of @a key can be determined by + * #fsl_shw_sko_calculate_wrapped_size() + * + * The protected key will not be available for use until this operation + * successfully completes. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be established. In the create case, the key + * length must be set. + * @param establish_type How @a key will be interpreted to establish a + * key for use. + * @param key If @a establish_type is #FSL_KEY_WRAP_UNWRAP, + * this is the location of a wrapped key. If + * @a establish_type is #FSL_KEY_WRAP_CREATE, this + * parameter can be @a NULL. If @a establish_type + * is #FSL_KEY_WRAP_ACCEPT, this is the location + * of a plaintext key. + */ +extern fsl_shw_return_t fsl_shw_establish_key( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t* key); + + +/** + * Wrap a key and retrieve the wrapped value. + * + * A wrapped key is a key that has been cryptographically obscured. It is + * only able to be used with #fsl_shw_establish_key(). + * + * This function will also release the key (see #fsl_shw_release_key()) so + * that it must be re-established before reuse. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * @param[out] covered_key The location to store the wrapped key. + * (This size is based upon the maximum key size + * of 32 octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + uint8_t* covered_key); + +/*! + * Read the key value from a key object. + * + * Only a key marked as a software key (#FSL_SKO_KEY_SW_KEY) can be read with + * this call. It has no effect on the status of the key store. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The referenced key. + * @param[out] key The location to store the key value. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * key); + +/** + * De-establish a key so that it can no longer be accessed. + * + * The key will need to be re-established before it can again be used. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_release_key( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info); + + +/* + * In userspace, partition assignments will be tracked using the user context. + * In kernel mode, partition assignments are based on address only. + */ + +/** + * Allocate a block of secure memory + * + * @param user_ctx User context + * @param size Memory size (octets). Note: currently only + * supports only single-partition sized blocks. + * @param UMID User Mode ID to use when registering the + * partition. + * @param permissions Permissions to initialize the partition with. + * Can be made by ORing flags from the + * #fsl_shw_permission_t. + * + * @return Address of the allocated memory. NULL if the + * call was not successful. + */ +extern void *fsl_shw_smalloc(fsl_shw_uco_t* user_ctx, + uint32_t size, + const uint8_t* UMID, + uint32_t permissions); + + +/** + * Free a block of secure memory that was allocated with #fsl_shw_smalloc + * + * @param user_ctx User context + * @param address Address of the block of secure memory to be + * released. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_sfree( + fsl_shw_uco_t* user_ctx, + void* address); + + +/** + * Check the status of a block of a secure memory that was allocated with + * #fsl_shw_smalloc + * + * @param user_ctx User context + * @param address Address of the block of secure memory to be + * released. + * @param status Status of the partition, of type + * #fsl_partition_status_t + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t* user_ctx, + void* address, + fsl_shw_partition_status_t* status); + + +/** + * Diminish the permissions of a block of secure memory. Note that permissions + * can only be revoked. + * + * @param user_ctx User context + * @param address Base address of the secure memory to work with + * @param permissions Permissions to initialize the partition with. + * Can be made by ORing flags from the + * #fsl_shw_permission_t. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_diminish_perms( + fsl_shw_uco_t* user_ctx, + void* address, + uint32_t permissions); + +extern fsl_shw_return_t do_scc_engage_partition( + fsl_shw_uco_t* user_ctx, + void* address, + const uint8_t* UMID, + uint32_t permissions); + +extern fsl_shw_return_t do_system_keystore_slot_alloc( + fsl_shw_uco_t* user_ctx, + uint32_t key_lenth, + uint64_t ownerid, + uint32_t *slot); + +extern fsl_shw_return_t do_system_keystore_slot_dealloc( + fsl_shw_uco_t* user_ctx, + uint64_t ownerid, + uint32_t slot); + +extern fsl_shw_return_t do_system_keystore_slot_load( + fsl_shw_uco_t* user_ctx, + uint64_t ownerid, + uint32_t slot, + const uint8_t *key, + uint32_t key_length); + +extern fsl_shw_return_t do_system_keystore_slot_encrypt( + fsl_shw_uco_t* user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t* black_data); + +extern fsl_shw_return_t do_system_keystore_slot_decrypt( + fsl_shw_uco_t* user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t* black_data); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-SKO */ +/* REQ-FSL-SHW-PINTFC-COA-SCCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-SYM-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +/** + * Encrypt a stream of data with a symmetric-key algorithm. + * + * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the + * flags of the @a sym_ctx object will control part of the operation of this + * function. The #FSL_SYM_CTX_INIT flag means that there is no context info in + * the object. The #FSL_SYM_CTX_LOAD means to use information in the + * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag + * means to update the object's context information after the operation has + * been performed. + * + * All of the data for an operation can be run through at once using the + * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using + * a @a length for the whole of the data. + * + * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function + * would "pick up" where the previous call left off, allowing the user to + * perform the larger function in smaller steps. + * + * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always + * be a multiple of the block size for the algorithm being used. For proper + * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the + * block size until the last operation on the total octet stream. + * + * Some users of ARC4 may want to compute the context (S-Box and pointers) from + * the key before any data is available. This may be done by running this + * function with a @a length of zero, with the init & save flags flags on in + * the @a sym_ctx. Subsequent operations would then run as normal with the + * load and save flags. Note that they key object is still required. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info Key and algorithm being used for this operation. + * @param[in,out] sym_ctx Info on cipher mode, state of the cipher. + * @param length Length, in octets, of the pt (and ct). + * @param pt pointer to plaintext to be encrypted. + * @param[out] ct pointer to where to store the resulting ciphertext. + * + * @return A return code of type #fsl_shw_return_t. + * + */ +extern fsl_shw_return_t fsl_shw_symmetric_encrypt( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_scco_t* sym_ctx, + uint32_t length, + const uint8_t* pt, + uint8_t* ct); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-SKO */ +/* REQ-FSL-SHW-PINTFC-COA-SCCO */ +/* PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +/** + * Decrypt a stream of data with a symmetric-key algorithm. + * + * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the + * flags of the @a sym_ctx object will control part of the operation of this + * function. The #FSL_SYM_CTX_INIT flag means that there is no context info in + * the object. The #FSL_SYM_CTX_LOAD means to use information in the + * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag + * means to update the object's context information after the operation has + * been performed. + * + * All of the data for an operation can be run through at once using the + * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using + * a @a length for the whole of the data. + * + * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function + * would "pick up" where the previous call left off, allowing the user to + * perform the larger function in smaller steps. + * + * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always + * be a multiple of the block size for the algorithm being used. For proper + * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the + * block size until the last operation on the total octet stream. + * + * Some users of ARC4 may want to compute the context (S-Box and pointers) from + * the key before any data is available. This may be done by running this + * function with a @a length of zero, with the #FSL_SYM_CTX_INIT & + * #FSL_SYM_CTX_SAVE flags on in the @a sym_ctx. Subsequent operations would + * then run as normal with the load & save flags. Note that they key object is + * still required. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The key and algorithm being used in this operation. + * @param[in,out] sym_ctx Info on cipher mode, state of the cipher. + * @param length Length, in octets, of the ct (and pt). + * @param ct pointer to ciphertext to be decrypted. + * @param[out] pt pointer to where to store the resulting plaintext. + * + * @return A return code of type #fsl_shw_return_t + * + */ +extern fsl_shw_return_t fsl_shw_symmetric_decrypt( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_scco_t* sym_ctx, + uint32_t length, + const uint8_t* ct, + uint8_t* pt); + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-HCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-HASH-005 */ +/** + * Hash a stream of data with a cryptographic hash algorithm. + * + * The flags in the @a hash_ctx control the operation of this function. + * + * Hashing functions work on 64 octets of message at a time. Therefore, when + * any partial hashing of a long message is performed, the message @a length of + * each segment must be a multiple of 64. When ready to + * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value. + * + * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a + * one-shot complete hash, including padding, will be performed. The @a length + * may be any value. + * + * The first octets of a data stream can be hashed by setting the + * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags. The @a length must be + * a multiple of 64. + * + * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by + * #FSL_HASH_FLAGS_SAVE. The two in combination will allow a (multiple-of-64 + * octets) 'middle sequence' of the data stream to be hashed with the + * beginning. The @a length must again be a multiple of 64. + * + * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously + * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and + * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the + * stream. The @a length may be any value. + * + * If the user program wants to do the padding for the hash, it can leave off + * the #FSL_HASH_FLAGS_FINALIZE flag. The @a length must then be a multiple of + * 64 octets. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] hash_ctx Hashing algorithm and state of the cipher. + * @param msg Pointer to the data to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result If not null, pointer to where to store the hash + * digest. + * @param result_len Number of octets to store in @a result. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hash( + fsl_shw_uco_t* user_ctx, + fsl_shw_hco_t* hash_ctx, + const uint8_t* msg, + uint32_t length, + uint8_t* result, + uint32_t result_len); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-API-BASIC-HMAC-001 */ +/** + * Precompute the Key hashes for an HMAC operation. + * + * This function may be used to calculate the inner and outer precomputes, + * which are the hash contexts resulting from hashing the XORed key for the + * 'inner hash' and the 'outer hash', respectively, of the HMAC function. + * + * After execution of this function, the @a hmac_ctx will contain the + * precomputed inner and outer contexts, so that they may be used by + * #fsl_shw_hmac(). The flags of @a hmac_ctx will be updated with + * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT to mark their presence. In addtion, the + * #FSL_HMAC_FLAGS_INIT flag will be set. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The key being used in this operation. Key must be + * 1 to 64 octets long. + * @param[in,out] hmac_ctx The context which controls, by its flags and + * algorithm, the operation of this function. + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hmac_precompute( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_hmco_t* hmac_ctx); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-HMAC-002 */ +/** + * Continue, finalize, or one-shot an HMAC operation. + * + * There are a number of ways to use this function. The flags in the + * @a hmac_ctx object will determine what operations occur. + * + * If #FSL_HMAC_FLAGS_INIT is set, then the hash will be started either from + * the @a key_info, or from the precomputed inner hash value in the + * @a hmac_ctx, depending on the value of #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT. + * + * If, instead, #FSL_HMAC_FLAGS_LOAD is set, then the hash will be continued + * from the ongoing inner hash computation in the @a hmac_ctx. + * + * If #FSL_HMAC_FLAGS_FINALIZE are set, then the @a msg will be padded, hashed, + * the outer hash will be performed, and the @a result will be generated. + * + * If the #FSL_HMAC_FLAGS_SAVE flag is set, then the (ongoing or final) digest + * value will be stored in the ongoing inner hash computation field of the @a + * hmac_ctx. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info If #FSL_HMAC_FLAGS_INIT is set in the @a hmac_ctx, + * this is the key being used in this operation, and the + * IPAD. If #FSL_HMAC_FLAGS_INIT is set in the @a + * hmac_ctx and @a key_info is NULL, then + * #fsl_shw_hmac_precompute() has been used to populate + * the @a inner_precompute and @a outer_precompute + * contexts. If #FSL_HMAC_FLAGS_INIT is not set, this + * parameter is ignored. + + * @param[in,out] hmac_ctx The context which controls, by its flags and + * algorithm, the operation of this function. + * @param msg Pointer to the message to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result Pointer, of @a result_len octets, to where to + * store the HMAC. + * @param result_len Length of @a result buffer. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hmac( + fsl_shw_uco_t* user_ctx, + fsl_shw_sko_t* key_info, + fsl_shw_hmco_t* hmac_ctx, + const uint8_t* msg, + uint32_t length, + uint8_t* result, + uint32_t result_len); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-002 */ +/** + * Get random data. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length The number of octets of @a data being requested. + * @param[out] data A pointer to a location of @a length octets to where + * random data will be returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_get_random( + fsl_shw_uco_t* user_ctx, + uint32_t length, + uint8_t* data); + + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-003 */ +/** + * Add entropy to random number generator. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length Number of bytes at @a data. + * @param data Entropy to add to random number generator. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_add_entropy( + fsl_shw_uco_t* user_ctx, + uint32_t length, + uint8_t* data); + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-SKO */ +/** + * Perform Generation-Encryption by doing a Cipher and a Hash. + * + * Generate the authentication value @a auth_value as well as encrypt the @a + * payload into @a ct (the ciphertext). This is a one-shot function, so all of + * the @a auth_data and the total message @a payload must passed in one call. + * This also means that the flags in the @a auth_ctx must be #FSL_ACCO_CTX_INIT + * and #FSL_ACCO_CTX_FINALIZE. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param auth_ctx Controlling object for Authenticate-decrypt. + * @param cipher_key_info The key being used for the cipher part of this + * operation. In CCM mode, this key is used for + * both parts. + * @param auth_key_info The key being used for the authentication part + * of this operation. In CCM mode, this key is + * ignored and may be NULL. + * @param auth_data_length Length, in octets, of @a auth_data. + * @param auth_data Data to be authenticated but not encrypted. + * @param payload_length Length, in octets, of @a payload. + * @param payload Pointer to the plaintext to be encrypted. + * @param[out] ct Pointer to the where the encrypted @a payload + * will be stored. Must be @a payload_length + * octets long. + * @param[out] auth_value Pointer to where the generated authentication + * field will be stored. Must be as many octets as + * indicated by MAC length in the @a function_ctx. + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_gen_encrypt( + fsl_shw_uco_t* user_ctx, + fsl_shw_acco_t* auth_ctx, + fsl_shw_sko_t* cipher_key_info, + fsl_shw_sko_t* auth_key_info, + uint32_t auth_data_length, + const uint8_t* auth_data, + uint32_t payload_length, + const uint8_t* payload, + uint8_t* ct, + uint8_t* auth_value); + +/* REQ-FSL-SHW-PINTFC-COA-UCO */ +/* REQ-FSL-SHW-PINTFC-COA-SKO */ +/** + * Perform Authentication-Decryption in Cipher + Hash. + * + * This function will perform a one-shot decryption of a data stream as well as + * authenticate the authentication value. This is a one-shot function, so all + * of the @a auth_data and the total message @a payload must passed in one + * call. This also means that the flags in the @a auth_ctx must be + * #FSL_ACCO_CTX_INIT and #FSL_ACCO_CTX_FINALIZE. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param auth_ctx Controlling object for Authenticate-decrypt. + * @param cipher_key_info The key being used for the cipher part of this + * operation. In CCM mode, this key is used for + * both parts. + * @param auth_key_info The key being used for the authentication part + * of this operation. In CCM mode, this key is + * ignored and may be NULL. + * @param auth_data_length Length, in octets, of @a auth_data. + * @param auth_data Data to be authenticated but not decrypted. + * @param payload_length Length, in octets, of @a ct and @a pt. + * @param ct Pointer to the encrypted input stream. + * @param auth_value The (encrypted) authentication value which will + * be authenticated. This is the same data as the + * (output) @a auth_value argument to + * #fsl_shw_gen_encrypt(). + * @param[out] payload Pointer to where the plaintext resulting from + * the decryption will be stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_auth_decrypt( + fsl_shw_uco_t* user_ctx, + fsl_shw_acco_t* auth_ctx, + fsl_shw_sko_t* cipher_key_info, + fsl_shw_sko_t* auth_key_info, + uint32_t auth_data_length, + const uint8_t* auth_data, + uint32_t payload_length, + const uint8_t* ct, + const uint8_t* auth_value, + uint8_t* payload); + +/*! + * Cause the hardware to create a new random key for secure memory use. + * + * Have the hardware use the secure hardware random number generator to load a + * new secret key into the hardware random key register. It will not be made + * active without a call to #fsl_shw_select_pf_key(). + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * + * @return A return code of type #fsl_shw_return_t. + */ +#ifdef __KERNEL__ + +extern fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx); + +#else + +#define fsl_shw_gen_random_pf_key(user_ctx) FSL_RETURN_NO_RESOURCE_S + +#endif /* __KERNEL__ */ + +/*! + * Retrieve the detected tamper event. + * + * Note that if more than one event was detected, this routine will only ever + * return one of them. + * + * @param[in] user_ctx A user context from #fsl_shw_register_user(). + * @param[out] tamperp Location to store the tamper information. + * @param[out] timestampp Locate to store timestamp from hardwhare when + * an event was detected. + * + * + * @return A return code of type #fsl_shw_return_t (for instance, if the platform + * is not in a fail state. + */ +#ifdef __KERNEL__ + +extern fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx, + fsl_shw_tamper_t * tamperp, + uint64_t * timestampp); +#else + +#define fsl_shw_read_tamper_event(user_ctx,tamperp,timestampp) \ + FSL_RETURN_NO_RESOURCE_S + +#endif /* __KERNEL__ */ + +/***************************************************************************** + * + * Functions internal to SHW driver. + * +*****************************************************************************/ + +fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t* user_ctx, + void* partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t* black_data, + uint32_t* IV, fsl_shw_cypher_mode_t cypher_mode); + +fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t* user_ctx, + void* partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t* black_data, + uint32_t* IV, fsl_shw_cypher_mode_t cypher_mode); + + +/***************************************************************************** + * + * Functions available to other SHW-family drivers. + * +*****************************************************************************/ + +#ifdef __KERNEL__ +/** + * Add an entry to a work/result queue. + * + * @param pool Pointer to list structure + * @param entry Entry to place at tail of list + * + * @return void + */ +inline static void SHW_ADD_QUEUE_ENTRY(shw_queue_t* pool, + shw_queue_entry_t* entry) +{ + os_lock_context_t lock_context; + + entry->next = NULL; + os_lock_save_context(shw_queue_lock, lock_context); + + if (pool->tail != NULL) { + pool->tail->next = entry; + } else { + /* Queue was empty, so this is also the head. */ + pool->head = entry; + } + pool->tail = entry; + + os_unlock_restore_context(shw_queue_lock, lock_context); + + return; + + +} + + +/** + * Get first entry on the queue and remove it from the queue. + * + * @return Pointer to first entry, or NULL if none. + */ +inline static shw_queue_entry_t* SHW_POP_FIRST_ENTRY(shw_queue_t* queue) +{ + shw_queue_entry_t* entry; + os_lock_context_t lock_context; + + os_lock_save_context(shw_queue_lock, lock_context); + + entry = queue->head; + + if (entry != NULL) { + queue->head = entry->next; + entry->next = NULL; + /* If this was only entry, clear the tail. */ + if (queue->tail == entry) { + queue->tail = NULL; + } + } + + os_unlock_restore_context(shw_queue_lock, lock_context); + + return entry; +} + + + +/** + * Remove an entry from the list. + * + * If the entry not on the queue, no error will be returned. + * + * @param pool Pointer to work queue + * @param entry Entry to remove from queue + * + * @return void + * + */ +inline static void SHW_QUEUE_REMOVE_ENTRY(shw_queue_t* pool, + shw_queue_entry_t* entry) +{ + os_lock_context_t lock_context; + + os_lock_save_context(shw_queue_lock, lock_context); + + /* Check for quick case.*/ + if (pool->head == entry) { + pool->head = entry->next; + entry->next = NULL; + if (pool->tail == entry) { + pool->tail = NULL; + } + } else { + register shw_queue_entry_t* prev = pool->head; + + /* We know it is not the head, so start looking at entry after head. */ + while (prev->next) { + if (prev->next != entry) { + prev = prev->next; /* Try another */ + continue; + } else { + /* Unlink from chain. */ + prev->next = entry->next; + entry->next = NULL; + /* If last in chain, update tail. */ + if (pool->tail == entry) { + pool->tail = prev; + } + break; + } + } /* while */ + } + + os_unlock_restore_context(shw_queue_lock, lock_context); + + return; +} +#endif /* __KERNEL__ */ + + +/***************************************************************************** + * + * Functions available to User-Mode API functions + * + ****************************************************************************/ +#ifndef __KERNEL__ + + + /** + * Sanity checks the user context object fields to ensure that they make some + * sense before passing the uco as a parameter. + * + * @brief Verify the user context object + * + * @param uco user context object + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t validate_uco(fsl_shw_uco_t *uco); + + +/** + * Initialize a request block to go to the driver. + * + * @param hdr Pointer to request block header + * @param user_ctx Pointer to user's context + * + * @return void + */ +inline static void init_req(struct shw_req_header* hdr, + fsl_shw_uco_t* user_ctx) +{ + hdr->flags = user_ctx->flags; + hdr->user_ref = user_ctx->user_ref; + hdr->code = FSL_RETURN_ERROR_S; + + return; +} + + +/** + * Send a request block off to the driver. + * + * If this is a non-blocking request, then req will be freed. + * + * @param type The type of request being sent + * @param req Pointer to the request block + * @param ctx Pointer to user's context + * + * @return code from driver if ioctl() succeeded, otherwise + * FSL_RETURN_INTERNAL_ERROR_S. + */ +inline static fsl_shw_return_t send_req(shw_user_request_t type, + struct shw_req_header* req, + fsl_shw_uco_t* ctx) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + unsigned blocking = ctx->flags & FSL_UCO_BLOCKING_MODE; + int code; + + code = ioctl(ctx->openfd, SHW_IOCTL_REQUEST + type, req); + + if (code == 0) { + if (blocking) { + ret = req->code; + } else { + ret = FSL_RETURN_OK_S; + } + } else { +#ifdef FSL_DEBUG + fprintf(stderr, "SHW: send_req failed with (%d), %s\n", errno, + strerror(errno)); +#endif + } + + if (blocking) { + free(req); + } + + return ret; +} + + +#endif /* no __KERNEL__ */ + +#if defined(FSL_HAVE_DRYICE) +/* Some kernel functions */ +void fsl_shw_permute1_bytes(const uint8_t * key, uint8_t * permuted_key, + int key_count); +void fsl_shw_permute1_bytes_to_words(const uint8_t * key, + uint32_t * permuted_key, int key_count); + +#define PFKEY_TO_STR(key_in) \ +({ \ + di_key_t key = key_in; \ + \ + ((key == DI_KEY_FK) ? "IIM" : \ + ((key == DI_KEY_PK) ? "PRG" : \ + ((key == DI_KEY_RK) ? "RND" : \ + ((key == DI_KEY_FPK) ? "IIM_PRG" : \ + ((key == DI_KEY_FRK) ? "IIM_RND" : "unk"))))); \ +}) + +#ifdef DIAG_SECURITY_FUNC +extern const char *di_error_string(int code); +#endif + +#endif /* HAVE DRYICE */ + +#endif /* SHW_DRIVER_H */ diff --git a/drivers/mxc/security/rng/include/shw_hash.h b/drivers/mxc/security/rng/include/shw_hash.h new file mode 100644 index 000000000000..8026c7ecb3fd --- /dev/null +++ b/drivers/mxc/security/rng/include/shw_hash.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file shw_hash.h + * + * This file contains definitions for use of the (internal) SHW hash + * software computation. It defines the usual three steps: + * + * - #shw_hash_init() + * - #shw_hash_update() + * - #shw_hash_final() + * + * The only other item of note to callers is #SHW_HASH_LEN, which is the number + * of bytes calculated for the hash. + */ + +#ifndef SHW_HASH_H +#define SHW_HASH_H + +/*! Define which gives the number of bytes available in an hash result */ +#define SHW_HASH_LEN 32 + +/* Define which matches block length in bytes of the underlying hash */ +#define SHW_HASH_BLOCK_LEN 64 + +/* "Internal" define which matches SHA-256 state size (32-bit words) */ +#define SHW_HASH_STATE_WORDS 8 + +/* "Internal" define which matches word length in blocks of the underlying + hash. */ +#define SHW_HASH_BLOCK_WORD_SIZE 16 + +#define SHW_HASH_STATE_SIZE 32 + +/*! + * State for a SHA-1/SHA-2 Hash + * + * (Note to maintainers: state needs to be updated to uint64_t to handle + * SHA-384/SHA-512)... And bit_count to uint128_t (heh). + */ +typedef struct shw_hash_state { + unsigned int partial_count_bytes; /*!< Number of bytes of message sitting + * in @c partial_block */ + uint8_t partial_block[SHW_HASH_BLOCK_LEN]; /*!< Data waiting to be processed as a block */ + uint32_t state[SHW_HASH_STATE_WORDS]; /*!< Current hash state variables */ + uint64_t bit_count; /*!< Number of bits sent through the update function */ +} shw_hash_state_t; + +/*! + * Initialize the hash state structure + * + * @param state Address of hash state structure. + * @param algorithm Which hash algorithm to use (must be FSL_HASH_ALG_SHA256) + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hash_init(shw_hash_state_t * state, + fsl_shw_hash_alg_t algorithm); + +/*! + * Put data into the hash calculation + * + * @param state Address of hash state structure. + * @param msg Address of the message data for the hash. + * @param msg_len Number of bytes of @c msg. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hash_update(shw_hash_state_t * state, + const uint8_t * msg, unsigned int msg_len); + +/*! + * Calculate the final hash value + * + * @param state Address of hash state structure. + * @param hash Address of location to store the hash. + * @param hash_len Number of bytes of @c hash to be stored. + * + * @return FSL_RETURN_OK_S if all went well, FSL_RETURN_BAD_DATA_LENGTH_S if + * hash_len is too long, otherwise an error code. + */ +fsl_shw_return_t shw_hash_final(shw_hash_state_t * state, + uint8_t * hash, unsigned int hash_len); + +#endif /* SHW_HASH_H */ diff --git a/drivers/mxc/security/rng/include/shw_hmac.h b/drivers/mxc/security/rng/include/shw_hmac.h new file mode 100644 index 000000000000..f73a78f5b02d --- /dev/null +++ b/drivers/mxc/security/rng/include/shw_hmac.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file shw_hmac.h + * + * This file contains definitions for use of the (internal) SHW HMAC + * software computation. It defines the usual three steps: + * + * - #shw_hmac_init() + * - #shw_hmac_update() + * - #shw_hmac_final() + * + * The only other item of note to callers is #SHW_HASH_LEN, which is the number + * of bytes calculated for the HMAC. + */ + +#ifndef SHW_HMAC_H +#define SHW_HMAC_H + +#include "shw_hash.h" + +/*! + * State for an HMAC + * + * Note to callers: This structure contains key material and should be kept in + * a secure location, such as internal RAM. + */ +typedef struct shw_hmac_state { + shw_hash_state_t inner_hash; /*!< Current state of inner hash */ + shw_hash_state_t outer_hash; /*!< Current state of outer hash */ +} shw_hmac_state_t; + +/*! + * Initialize the HMAC state structure with the HMAC key + * + * @param state Address of HMAC state structure. + * @param key Address of the key to be used for the HMAC. + * @param key_len Number of bytes of @c key. This must not be greater than + * the block size of the underlying hash (#SHW_HASH_BLOCK_LEN). + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_init(shw_hmac_state_t * state, + const uint8_t * key, unsigned int key_len); + +/*! + * Put data into the HMAC calculation + * + * @param state Address of HMAC state structure. + * @param msg Address of the message data for the HMAC. + * @param msg_len Number of bytes of @c msg. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_update(shw_hmac_state_t * state, + const uint8_t * msg, unsigned int msg_len); + +/*! + * Calculate the final HMAC + * + * @param state Address of HMAC state structure. + * @param hmac Address of location to store the HMAC. + * @param hmac_len Number of bytes of @c mac to be stored. Probably best if + * this value is no greater than #SHW_HASH_LEN. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_final(shw_hmac_state_t * state, + uint8_t * hmac, unsigned int hmac_len); + +#endif /* SHW_HMAC_H */ diff --git a/drivers/mxc/security/rng/include/shw_internals.h b/drivers/mxc/security/rng/include/shw_internals.h new file mode 100644 index 000000000000..1bf3b1a86374 --- /dev/null +++ b/drivers/mxc/security/rng/include/shw_internals.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef SHW_INTERNALS_H +#define SHW_INTERNALS_H + +/*! @file shw_internals.h + * + * This file contains definitions which are internal to the SHW driver. + * + * This header file should only ever be included by shw_driver.c + * + * Compile-time flags minimally needed: + * + * @li Some sort of platform flag. + * + */ + +#include "portable_os.h" +#include "shw_driver.h" + +/*! @defgroup shwcompileflags SHW Compile Flags + * + * These are flags which are used to configure the SHW driver at compilation + * time. + * + * The terms 'defined' and 'undefined' refer to whether a @c \#define (or -D on + * a compile command) has defined a given preprocessor symbol. If a given + * symbol is defined, then @c \#ifdef \ will succeed. Some symbols + * described below default to not having a definition, i.e. they are undefined. + * + */ + +/*! @addtogroup shwcompileflags */ +/*! @{ */ +#ifndef SHW_MAJOR_NODE +/*! + * This should be configured in a Makefile/compile command line. It is the + * value the driver will use to register itself as a device driver for a + * /dev/node file. Zero means allow (Linux) to assign a value. Any positive + * number will be attempted as the registration value, to allow for + * coordination with the creation/existence of a /dev/fsl_shw (for instance) + * file in the filesystem. + */ +#define SHW_MAJOR_NODE 0 +#endif + +/* Temporarily define compile-time flags to make Doxygen happy and allow them + to get into the documentation. */ +#ifdef DOXYGEN_HACK + +/*! + * Turn on compilation of run-time operational, debug, and error messages. + * + * This flag is undefined by default. + */ +/* REQ-FSLSHW-DEBUG-001 */ +#define SHW_DEBUG +#undef SHW_DEBUG + +/*! @} */ +#endif /* end DOXYGEN_HACK */ + +#ifndef SHW_DRIVER_NAME +/*! @addtogroup shwcompileflags */ +/*! @{ */ +/*! Name the driver will use to register itself to the kernel as the driver for + * the #shw_major_node and interrupt handling. */ +#define SHW_DRIVER_NAME "fsl_shw" +/*! @} */ +#endif +/*#define SHW_DEBUG*/ + +/*! + * Add a user context onto the list of registered users. + * + * Place it at the head of the #user_list queue. + * + * @param ctx A pointer to a user context + * + * @return void + */ +inline static void SHW_ADD_USER(fsl_shw_uco_t * ctx) +{ + os_lock_context_t lock_context; + + os_lock_save_context(shw_queue_lock, lock_context); + ctx->next = user_list; + user_list = ctx; + os_unlock_restore_context(shw_queue_lock, lock_context); + +} + +/*! + * Remove a user context from the list of registered users. + * + * @param ctx A pointer to a user context + * + * @return void + * + */ +inline static void SHW_REMOVE_USER(fsl_shw_uco_t * ctx) +{ + fsl_shw_uco_t *prev_ctx = user_list; + os_lock_context_t lock_context; + + os_lock_save_context(shw_queue_lock, lock_context); + + if (prev_ctx == ctx) { + /* Found at head, so just set new head */ + user_list = ctx->next; + } else { + for (; (prev_ctx != NULL); prev_ctx = prev_ctx->next) { + if (prev_ctx->next == ctx) { + prev_ctx->next = ctx->next; + break; + } + } + } + os_unlock_restore_context(shw_queue_lock, lock_context); +} + +static void shw_user_callback(fsl_shw_uco_t * uco); + +/* internal functions */ +static os_error_code shw_setup_user_driver_interaction(void); +static void shw_cleanup(void); + +static os_error_code init_uco(fsl_shw_uco_t * user_ctx, void *user_mode_uco); +static os_error_code get_capabilities(fsl_shw_uco_t * user_ctx, + void *user_mode_pco_request); +static os_error_code get_results(fsl_shw_uco_t * user_ctx, + void *user_mode_result_req); +static os_error_code get_random(fsl_shw_uco_t * user_ctx, + void *user_mode_get_random_req); +static os_error_code add_entropy(fsl_shw_uco_t * user_ctx, + void *user_mode_add_entropy_req); + +void* wire_user_memory(void* address, uint32_t length, void** page_ctx); +void unwire_user_memory(void** page_ctx); +os_error_code map_user_memory(struct vm_area_struct* vma, + uint32_t physical_addr, uint32_t size); +os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size); + +#if defined(LINUX_VERSION_CODE) + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("Device Driver for FSL SHW API"); + +#endif /* LINUX_VERSION_CODE */ + +#endif /* SHW_INTERNALS_H */ diff --git a/drivers/mxc/security/rng/rng_driver.c b/drivers/mxc/security/rng/rng_driver.c new file mode 100644 index 000000000000..51eda5ccbe61 --- /dev/null +++ b/drivers/mxc/security/rng/rng_driver.c @@ -0,0 +1,1150 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! @file rng_driver.c + * + * This is the driver code for the hardware Random Number Generator (RNG). + * + * It provides the following functions to callers: + * fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t* user_ctx, + * uint32_t length, + * uint8_t* data); + * + * fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t* user_ctx, + * uint32_t length, + * uint8_t* data); + * + * The life of the driver starts at boot (or module load) time, with a call by + * the kernel to #rng_init(). As part of initialization, a background task + * running #rng_entropy_task() will be created. + * + * The life of the driver ends when the kernel is shutting down (or the driver + * is being unloaded). At this time, #rng_shutdown() is called. No function + * will ever be called after that point. In the case that the driver is + * reloaded, a new copy of the driver, with fresh global values, etc., is + * loaded, and there will be a new call to #rng_init(). + * + * A call to fsl_shw_get_random() gets converted into a work entry which is + * queued and handed off to a background task for fulfilment. This provides + * for a single thread of control for reading the RNG's FIFO register, which + * might otherwise underflow if not carefully managed. + * + * A call to fsl_shw_add_entropy() will cause the additional entropy to + * be passed directly into the hardware. + * + * In a debug configuration, it provides the following kernel functions: + * rng_return_t rng_read_register(uint32_t byte_offset, uint32_t* valuep); + * rng_return_t rng_write_register(uint32_t byte_offset, uint32_t value); + * @ingroup RNG + */ + +#include "portable_os.h" +#include "fsl_shw.h" +#include "rng_internals.h" + +#ifdef FSL_HAVE_SCC2 +#include +#else +#include +#endif + +#if defined(RNG_DEBUG) || defined(RNG_ENTROPY_DEBUG) || \ + defined(RNG_REGISTER_DEBUG) + +#include + +#else + +#define LOG_KDIAG_ARGS(fmt, ...) +#define LOG_KDIAG(diag) + +#endif + +/* These are often handy */ +#ifndef FALSE +/*! Non-true value for arguments, return values. */ +#define FALSE 0 +#endif +#ifndef TRUE +/*! True value for arguments, return values. */ +#define TRUE 1 +#endif + +/****************************************************************************** + * + * Global / Static Variables + * + *****************************************************************************/ + +/*! + * This is type void* so that a) it cannot directly be dereferenced, and b) + * pointer arithmetic on it will function for the byte offsets in rng_rnga.h + * and rng_rngc.h + * + * rng_base is the location in the iomap where the RNG's registers + * (and memory) start. + * + * The referenced data is declared volatile so that the compiler will + * not make any assumptions about the value of registers in the RNG, + * and thus will always reload the register into CPU memory before + * using it (i.e. wherever it is referenced in the driver). + * + * This value should only be referenced by the #RNG_READ_REGISTER and + * #RNG_WRITE_REGISTER macros and their ilk. All dereferences must be + * 32 bits wide. + */ +static volatile void *rng_base; + +/*! + * Flag to say whether interrupt handler has been registered for RNG + * interrupt */ +static int rng_irq_set = FALSE; + +/*! + * Size of the RNG's OUTPUT_FIFO, in words. Retrieved with + * #RNG_GET_FIFO_SIZE() during driver initialization. + */ +static int rng_output_fifo_size; + +/*! Major number for device driver. */ +static int rng_major; + +/*! Registration handle for registering driver with OS. */ +os_driver_reg_t rng_reg_handle; + +/*! + * Internal flag to know whether RNG is in Failed state (and thus many + * registers are unavailable). If the value ever goes to #RNG_STATUS_FAILED, + * it will never change. + */ +static volatile rng_status_t rng_availability = RNG_STATUS_INITIAL; + +/*! + * Global lock for the RNG driver. Mainly used for entries on the RNG work + * queue. + */ +static os_lock_t rng_queue_lock = NULL; + +/*! + * Queue for the RNG task to process. + */ +static shw_queue_t rng_work_queue; + +/*! + * Flag to say whether task initialization succeeded. + */ +static unsigned task_started = FALSE; +/*! + * Waiting queue for RNG SELF TESTING + */ +static DECLARE_COMPLETION(rng_self_testing); +static DECLARE_COMPLETION(rng_seed_done); +/*! + * Object for blocking-mode callers of RNG driver to sleep. + */ +OS_WAIT_OBJECT(rng_wait_queue); + +/****************************************************************************** + * + * Function Implementations - Externally Accessible + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn rng_init() */ +/*****************************************************************************/ +/*! + * Initialize the driver. + * + * Set up the driver to have access to RNG device registers and verify that + * it appears to be a proper working device. + * + * Set up interrupt handling. Assure RNG is ready to go and (possibly) set it + * into High Assurance mode. Create a background task to run + * #rng_entropy_task(). Set up up a callback with the SCC driver should the + * security alarm go off. Tell the kernel that the driver is here. + * + * This routine is called during kernel init or module load (insmod). + * + * The function will fail in one of two ways: Returning OK to the caller so + * that kernel startup / driver initialization completes, or returning an + * error. In the success case, the function could set the rng_avaailability to + * RNG_STATUS_FAILED so that only minimal support (e.g. register peek / poke) + * is available in the driver. + * + * @return a call to os_dev_init_return() + */ +OS_DEV_INIT(rng_init) +{ + struct clk *clk; + os_error_code return_code = OS_ERROR_FAIL_S; + rng_availability = RNG_STATUS_CHECKING; + +#if !defined(FSL_HAVE_RNGA) + INIT_COMPLETION(rng_self_testing); + INIT_COMPLETION(rng_seed_done); +#endif + rng_work_queue.head = NULL; + rng_work_queue.tail = NULL; + + clk = clk_get(NULL, "rng_clk"); + + // Check that the clock was found + if (IS_ERR(clk)) { + LOG_KDIAG("RNG: Failed to find rng_clock."); + return_code = OS_ERROR_FAIL_S; + goto check_err; + } + + clk_enable(clk); + + os_printk(KERN_INFO "RNG Driver: Loading\n"); + + return_code = rng_map_RNG_memory(); + if (return_code != OS_ERROR_OK_S) { + rng_availability = RNG_STATUS_UNIMPLEMENTED; + LOG_KDIAG_ARGS("RNG: Driver failed to map RNG registers. %d", + return_code); + goto check_err; + } + LOG_KDIAG_ARGS("RNG Driver: rng_base is 0x%08x", (uint32_t) rng_base); + /*Check SCC keys are fused */ + if (RNG_HAS_ERROR()) { + if (RNG_HAS_BAD_KEY()) { +#ifdef RNG_DEBUG +#if !defined(FSL_HAVE_RNGA) + LOG_KDIAG("ERROR: BAD KEYS SELECTED"); + { + uint32_t rngc_status = + RNG_READ_REGISTER(RNGC_STATUS); + uint32_t rngc_error = + RNG_READ_REGISTER(RNGC_ERROR); + LOG_KDIAG_ARGS + ("status register: %08x, error status: %08x", + rngc_status, rngc_error); + } +#endif +#endif + rng_availability = RNG_STATUS_FAILED; + return_code = OS_ERROR_FAIL_S; + goto check_err; + } + } + + /* Check RNG configuration and status */ + return_code = rng_grab_config_values(); + if (return_code != OS_ERROR_OK_S) { + rng_availability = RNG_STATUS_UNIMPLEMENTED; + goto check_err; + } + + /* Masking All Interrupts */ + /* They are unmasked later in rng_setup_interrupt_handling() */ + RNG_MASK_ALL_INTERRUPTS(); + + RNG_WAKE(); + + /* Determine status of RNG */ + if (RNG_OSCILLATOR_FAILED()) { + LOG_KDIAG("RNG Driver: RNG Oscillator is dead"); + rng_availability = RNG_STATUS_FAILED; + goto check_err; + } + + /* Oscillator not dead. Setup interrupt code and start the RNG. */ + if ((return_code = rng_setup_interrupt_handling()) == OS_ERROR_OK_S) { +#if defined(FSL_HAVE_RNGA) + scc_return_t scc_code; +#endif + + RNG_GO(); + + /* Self Testing For RNG */ + do { + RNG_CLEAR_ERR(); + + /* wait for Clearing Erring finished */ + msleep(1); + + RNG_UNMASK_ALL_INTERRUPTS(); + RNG_SELF_TEST(); +#if !defined(FSL_HAVE_RNGA) + wait_for_completion(&rng_self_testing); +#endif + } while (RNG_CHECK_SELF_ERR()); + + RNG_CLEAR_ALL_STATUS(); + /* checking for RNG SEED done */ + do { + RNG_CLEAR_ERR(); + RNG_SEED_GEN(); +#if !defined(FSL_HAVE_RNGA) + wait_for_completion(&rng_seed_done); +#endif + } while (RNG_CHECK_SEED_ERR()); +#ifndef RNG_NO_FORCE_HIGH_ASSURANCE + RNG_SET_HIGH_ASSURANCE(); +#endif + if (RNG_GET_HIGH_ASSURANCE()) { + LOG_KDIAG("RNG Driver: RNG is in High Assurance mode"); + } else { +#ifndef RNG_NO_FORCE_HIGH_ASSURANCE + LOG_KDIAG + ("RNG Driver: RNG could not be put in High Assurance mode"); + rng_availability = RNG_STATUS_FAILED; + goto check_err; +#endif /* RNG_NO_FORCE_HIGH_ASSURANCE */ + } + + /* Check that RNG is OK */ + if (!RNG_WORKING()) { + LOG_KDIAG_ARGS + ("RNG determined to be inoperable. Status %08x", + RNG_GET_STATUS()); + /* Couldn't wake it up or other problem */ + rng_availability = RNG_STATUS_FAILED; + goto check_err; + } + + rng_queue_lock = os_lock_alloc_init(); + if (rng_queue_lock == NULL) { + LOG_KDIAG("RNG: lock initialization failed"); + rng_availability = RNG_STATUS_FAILED; + goto check_err; + } + + return_code = os_create_task(rng_entropy_task); + if (return_code != OS_ERROR_OK_S) { + LOG_KDIAG("RNG: task initialization failed"); + rng_availability = RNG_STATUS_FAILED; + goto check_err; + } else { + task_started = TRUE; + } +#ifdef FSL_HAVE_RNGA + scc_code = scc_monitor_security_failure(rng_sec_failure); + if (scc_code != SCC_RET_OK) { + LOG_KDIAG_ARGS("Failed to register SCC callback: %d", + scc_code); +#ifndef RNG_NO_FORCE_HIGH_ASSURANCE + return_code = OS_ERROR_FAIL_S; + goto check_err; +#endif + } +#endif /* FSL_HAVE_RNGA */ + return_code = os_driver_init_registration(rng_reg_handle); + if (return_code != OS_ERROR_OK_S) { + goto check_err; + } + /* add power suspend here */ + /* add power resume here */ + return_code = + os_driver_complete_registration(rng_reg_handle, + rng_major, RNG_DRIVER_NAME); + } + /* RNG is working */ + + check_err: + + /* If FIFO underflow or other error occurred during drain, this will fail, + * as system will have been put into fail mode by SCC. */ + if ((return_code == OS_ERROR_OK_S) + && (rng_availability == RNG_STATUS_CHECKING)) { + RNG_PUT_RNG_TO_SLEEP(); + rng_availability = RNG_STATUS_OK; /* RNG & driver are ready */ + } else if (return_code != OS_ERROR_OK_S) { + os_printk(KERN_ALERT "Driver initialization failed. %d", + return_code); + rng_cleanup(); + } + + os_dev_init_return(return_code); + +} /* rng_init */ + +/*****************************************************************************/ +/* fn rng_shutdown() */ +/*****************************************************************************/ +/*! + * Prepare driver for exit. + * + * This is called during @c rmmod when the driver is unloading. + * Try to undo whatever was done during #rng_init(), to make the machine be + * in the same state, if possible. + * + * Calls rng_cleanup() to do all work, and then unmap device's register space. + */ +OS_DEV_SHUTDOWN(rng_shutdown) +{ + LOG_KDIAG("shutdown called"); + + rng_cleanup(); + + os_driver_remove_registration(rng_reg_handle); + if (rng_base != NULL) { + /* release the virtual memory map to the RNG */ + os_unmap_device((void *)rng_base, RNG_ADDRESS_RANGE); + rng_base = NULL; + } + + os_dev_shutdown_return(OS_ERROR_OK_S); +} /* rng_shutdown */ + +/*****************************************************************************/ +/* fn rng_cleanup() */ +/*****************************************************************************/ +/*! + * Undo everything done by rng_init() and place driver in fail mode. + * + * Deregister from SCC, stop tasklet, shutdown the RNG. Leave the register + * map in place in case other drivers call rng_read/write_register() + * + * @return void + */ +static void rng_cleanup(void) +{ + struct clk *clk; + +#ifdef FSL_HAVE_RNGA + scc_stop_monitoring_security_failure(rng_sec_failure); +#endif + + clk = clk_get(NULL, "rng_clk"); + clk_disable(clk); + if (task_started) { + os_dev_stop_task(rng_entropy_task); + } + + if (rng_base != NULL) { + /* mask off RNG interrupts */ + RNG_MASK_ALL_INTERRUPTS(); + RNG_SLEEP(); + + if (rng_irq_set) { + /* unmap the interrupts from the IRQ lines */ + os_deregister_interrupt(INT_RNG); + rng_irq_set = FALSE; + } + LOG_KDIAG("Leaving rng driver status as failed"); + rng_availability = RNG_STATUS_FAILED; + } else { + LOG_KDIAG("Leaving rng driver status as unimplemented"); + rng_availability = RNG_STATUS_UNIMPLEMENTED; + } + LOG_KDIAG("Cleaned up"); +} /* rng_cleanup */ + +/*! + * Post-process routine for fsl_shw_get_random(). + * + * This function will copy the random data generated by the background task + * into the user's buffer and then free the local buffer. + * + * @param gen_entry The work request. + * + * @return 0 = meaning work completed, pass back result. + */ +static uint32_t finish_random(shw_queue_entry_t * gen_entry) +{ + rng_work_entry_t *work = (rng_work_entry_t *) gen_entry; + + if (work->hdr.flags & FSL_UCO_USERMODE_USER) { + os_copy_to_user(work->data_user, work->data_local, + work->length); + } else { + memcpy(work->data_user, work->data_local, work->length); + } + + os_free_memory(work->data_local); + work->data_local = NULL; + + return 0; /* means completed. */ +} + +/* REQ-FSLSHW-PINTFC-API-BASIC-RNG-002 */ +/*****************************************************************************/ +/* fn fsl_shw_get_random() */ +/*****************************************************************************/ +/*! + * Get random data. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length The number of octets of @a data being requested. + * @param data A pointer to a location of @a length octets to where + * random data will be returned. + * + * @return FSL_RETURN_NO_RESOURCE_S A return code of type #fsl_shw_return_t. + * FSL_RETURN_OK_S + */ +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, uint32_t length, + uint8_t * data) +{ + fsl_shw_return_t return_code = FSL_RETURN_NO_RESOURCE_S; + /* Boost up length to cover any 'missing' bytes at end of a word */ + uint32_t *buf = os_alloc_memory(length + 3, 0); + volatile rng_work_entry_t *work = os_alloc_memory(sizeof(*work), 0); + + if ((rng_availability != RNG_STATUS_OK) || (buf == NULL) + || (work == NULL)) { + if (rng_availability != RNG_STATUS_OK) { + LOG_KDIAG_ARGS("rng not available: %d\n", + rng_availability); + } else { + LOG_KDIAG_ARGS + ("Resource allocation failure: %d or %d bytes", + length, sizeof(*work)); + } + /* Cannot perform function. Clean up and clear out. */ + if (buf != NULL) { + os_free_memory(buf); + } + if (work != NULL) { + os_free_memory((void *)work); + } + } else { + unsigned blocking = user_ctx->flags & FSL_UCO_BLOCKING_MODE; + + work->hdr.user_ctx = user_ctx; + work->hdr.flags = user_ctx->flags; + work->hdr.callback = user_ctx->callback; + work->hdr.user_ref = user_ctx->user_ref; + work->hdr.postprocess = finish_random; + work->length = length; + work->data_local = buf; + work->data_user = data; + + RNG_ADD_WORK_ENTRY((rng_work_entry_t *) work); + + if (blocking) { + os_sleep(rng_wait_queue, work->completed != FALSE, + FALSE); + finish_random((shw_queue_entry_t *) work); + return_code = work->hdr.code; + os_free_memory((void *)work); + } else { + return_code = FSL_RETURN_OK_S; + } + } + + return return_code; +} /* fsl_shw_get_entropy */ + +/*****************************************************************************/ +/* fn fsl_shw_add_entropy() */ +/*****************************************************************************/ +/*! + * Add entropy to random number generator. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length Number of bytes at @a data. + * @param data Entropy to add to random number generator. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, uint32_t length, + uint8_t * data) +{ + fsl_shw_return_t return_code = FSL_RETURN_NO_RESOURCE_S; +#if defined(FSL_HAVE_RNGC) + /* No Entropy Register in RNGC */ + return_code = FSL_RETURN_OK_S; +#else + uint32_t *local_data = NULL; + if (rng_availability == RNG_STATUS_OK) { + /* make 32-bit aligned place to hold data */ + local_data = os_alloc_memory(length + 3, 0); + if (local_data == NULL) { + return_code = FSL_RETURN_NO_RESOURCE_S; + } else { + memcpy(local_data, data, length); + + /* Copy one word at a time to hardware */ + while (TRUE) { + register uint32_t *ptr = local_data; + + RNG_ADD_ENTROPY(*ptr++); + if (length <= 4) { + break; + } + length -= 4; + } + return_code = FSL_RETURN_OK_S; + os_free_memory(local_data); + } /* else local_data not NULL */ + + } +#endif + /* rng_availability is OK */ + return return_code; +} /* fsl_shw_add_entropy */ + +#ifdef RNG_REGISTER_PEEK_POKE +/*****************************************************************************/ +/* fn rng_read_register() */ +/*****************************************************************************/ +/* + * Debug routines to allow reading of RNG registers. + * + * This routine is only for accesses by other than this driver. + * + * @param register_offset The byte offset of the register to be read. + * @param value Pointer to store the value of the register. + * + * @return RNG_RET_OK or an error return. + */ +rng_return_t rng_read_register(uint32_t register_offset, uint32_t * value) +{ + rng_return_t return_code = RNG_RET_FAIL; + + if ((rng_availability == RNG_STATUS_OK) + || (rng_availability == RNG_STATUS_FAILED)) { + if ((rng_check_register_offset(register_offset) + && rng_check_register_accessible(register_offset, + RNG_CHECK_READ))) { + /* The guards let the check through */ + *value = RNG_READ_REGISTER(register_offset); + return_code = RNG_RET_OK; + } + } + + return return_code; +} /* rng_read_register */ + +/*****************************************************************************/ +/* fn rng_write_register() */ +/*****************************************************************************/ +/* + * Debug routines to allow writing of RNG registers. + * + * This routine is only for accesses by other than this driver. + * + * @param register_offset The byte offset of the register to be written. + * @param value Value to store in the register. + * + * @return RNG_RET_OK or an error return. + */ +rng_return_t rng_write_register(uint32_t register_offset, uint32_t value) +{ + rng_return_t return_code = RNG_RET_FAIL; + + if ((rng_availability == RNG_STATUS_OK) + || (rng_availability == RNG_STATUS_FAILED)) { + if ((rng_check_register_offset(register_offset) + && rng_check_register_accessible(register_offset, + RNG_CHECK_WRITE))) { + RNG_WRITE_REGISTER(register_offset, value); + return_code = RNG_RET_OK; + } + } + + return return_code; +} /* rng_write_register */ +#endif /* RNG_REGISTER_PEEK_POKE */ + +/****************************************************************************** + * + * Function Implementations - Internal + * + *****************************************************************************/ + +#ifdef RNG_REGISTER_PEEK_POKE +/*****************************************************************************/ +/* fn check_register_offset() */ +/*****************************************************************************/ +/*! + * Verify that the @c offset is appropriate for the RNG's register set. + * + * @param[in] offset The (byte) offset within the RNG block + * of the register to be accessed. See + * RNG(A, C) register definitions for meanings. + * + * This routine is only for checking accesses by other than this driver. + * + * @return 0 if register offset out of bounds, 1 if ok to use + */ +inline int rng_check_register_offset(uint32_t offset) +{ + int return_code = FALSE; /* invalid */ + + /* Make sure offset isn't too high and also that it is aligned to + * aa 32-bit offset (multiple of four). + */ + if ((offset < RNG_ADDRESS_RANGE) && (offset % sizeof(uint32_t) == 0)) { + return_code = TRUE; /* OK */ + } else { + pr_debug("RNG: Denied access to offset %8x\n", offset); + } + + return return_code; + +} /* rng_check_register */ + +/*****************************************************************************/ +/* fn check_register_accessible() */ +/*****************************************************************************/ +/*! + * Make sure that register access is legal. + * + * Verify that, if in secure mode, only safe registers are used. + * For any register access, make sure that read-only registers are not written + * and that write-only registers are not read. This check also disallows any + * access to the RNG's Output FIFO, to prevent other drivers from draining the + * FIFO and causing an underflow condition. + * + * This routine is only for checking accesses by other than this driver. + * + * @param offset The (byte) offset within the RNG block + * of the register to be accessed. See + * @ref rngregs for meanings. + * @param access_write 0 for read, anything else for write + * + * @return 0 if invalid, 1 if OK. + */ +static int rng_check_register_accessible(uint32_t offset, int access_write) +{ + int return_code = FALSE; /* invalid */ + uint32_t secure = RNG_GET_HIGH_ASSURANCE(); + + /* First check for RNG in Secure Mode -- most registers inaccessible. + * Also disallowing access to RNG_OUTPUT_FIFO except by the driver. + */ + if (! +#ifdef FSL_HAVE_RNGA + (secure && + ((offset == RNGA_OUTPUT_FIFO) || + (offset == RNGA_MODE) || + (offset == RNGA_VERIFICATION_CONTROL) || + (offset == RNGA_OSCILLATOR_CONTROL_COUNTER) || + (offset == RNGA_OSCILLATOR1_COUNTER) || + (offset == RNGA_OSCILLATOR2_COUNTER) || + (offset == RNGA_OSCILLATOR_COUNTER_STATUS))) +#else /* RNGB or RNGC */ + (secure && + ((offset == RNGC_FIFO) || + (offset == RNGC_VERIFICATION_CONTROL) || + (offset == RNGC_OSC_COUNTER_CONTROL) || + (offset == RNGC_OSC_COUNTER) || + (offset == RNGC_OSC_COUNTER_STATUS))) +#endif + ) { + + /* Passed that test. Either not in high assurance, and/or are + checking register that is always available. Now check + R/W permissions. */ + if (access_write == RNG_CHECK_READ) { /* read request */ + /* Only the entropy register is write-only */ +#ifdef FSL_HAVE_RNGC + /* No registers are write-only */ + return_code = TRUE; +#else /* else RNGA or RNGB */ +#ifdef FSL_HAVE_RNGA + if (1) { +#else + if (!(offset == RNGB_ENTROPY)) { +#endif + return_code = TRUE; /* Let all others be read */ + } else { + pr_debug + ("RNG: Offset %04x denied read access\n", + offset); + } +#endif /* RNGA or RNGB */ + } /* read */ + else { /* access_write means write */ + /* Check against list of non-writable registers */ + if (! +#ifdef FSL_HAVE_RNGA + ((offset == RNGA_STATUS) || + (offset == RNGA_OUTPUT_FIFO) || + (offset == RNGA_OSCILLATOR1_COUNTER) || + (offset == RNGA_OSCILLATOR2_COUNTER) || + (offset == RNGA_OSCILLATOR_COUNTER_STATUS)) +#else /* FSL_HAVE_RNGB or FSL_HAVE_RNGC */ + ((offset == RNGC_STATUS) || + (offset == RNGC_FIFO) || + (offset == RNGC_OSC_COUNTER) || + (offset == RNGC_OSC_COUNTER_STATUS)) +#endif + ) { + return_code = TRUE; /* can be written */ + } else { + LOG_KDIAG_ARGS + ("Offset %04x denied write access", offset); + } + } /* write */ + } /* not high assurance and inaccessible register... */ + else { + LOG_KDIAG_ARGS("Offset %04x denied high-assurance access", + offset); + } + + return return_code; +} /* rng_check_register_accessible */ +#endif /* RNG_REGISTER_PEEK_POKE */ + +/*****************************************************************************/ +/* fn rng_irq() */ +/*****************************************************************************/ +/*! + * This is the interrupt handler for the RNG. It is only ever invoked if the + * RNG detects a FIFO Underflow error. + * + * If the error is a Security Violation, this routine will + * set the #rng_availability to #RNG_STATUS_FAILED, as the entropy pool may + * have been corrupted. The RNG will also be placed into low power mode. The + * SCC will have noticed the problem as well. + * + * The other possibility, if the RNG is not in High Assurance mode, would be + * simply a FIFO Underflow. No special action, other than to + * clear the interrupt, is taken. + */ +OS_DEV_ISR(rng_irq) +{ + int handled = FALSE; /* assume interrupt isn't from RNG */ + + LOG_KDIAG("rng irq!"); + + if (RNG_SEED_DONE()) { + complete(&rng_seed_done); + RNG_CLEAR_ALL_STATUS(); + handled = TRUE; + } + + if (RNG_SELF_TEST_DONE()) { + complete(&rng_self_testing); + RNG_CLEAR_ALL_STATUS(); + handled = TRUE; + } + /* Look to see whether RNG needs attention */ + if (RNG_HAS_ERROR()) { + if (RNG_GET_HIGH_ASSURANCE()) { + RNG_SLEEP(); + rng_availability = RNG_STATUS_FAILED; + RNG_MASK_ALL_INTERRUPTS(); + } + handled = TRUE; + /* Clear the interrupt */ + RNG_CLEAR_ALL_STATUS(); + + } + os_dev_isr_return(handled); +} /* rng_irq */ + +/*****************************************************************************/ +/* fn map_RNG_memory() */ +/*****************************************************************************/ +/*! + * Place the RNG's memory into kernel virtual space. + * + * @return OS_ERROR_OK_S on success, os_error_code on failure + */ +static os_error_code rng_map_RNG_memory(void) +{ + os_error_code error_code = OS_ERROR_FAIL_S; + + rng_base = os_map_device(RNG_BASE_ADDR, RNG_ADDRESS_RANGE); + if (rng_base == NULL) { + /* failure ! */ + LOG_KDIAG("RNG Driver: ioremap failed."); + } else { + error_code = OS_ERROR_OK_S; + } + + return error_code; +} /* rng_map_RNG_memory */ + +/*****************************************************************************/ +/* fn rng_setup_interrupt_handling() */ +/*****************************************************************************/ +/*! + * Register #rng_irq() as the interrupt handler for #INT_RNG. + * + * @return OS_ERROR_OK_S on success, os_error_code on failure + */ +static os_error_code rng_setup_interrupt_handling(void) +{ + os_error_code error_code; + + /* + * Install interrupt service routine for the RNG. Ignore the + * assigned IRQ number. + */ + error_code = os_register_interrupt(RNG_DRIVER_NAME, INT_RNG, + OS_DEV_ISR_REF(rng_irq)); + if (error_code != OS_ERROR_OK_S) { + LOG_KDIAG("RNG Driver: Error installing Interrupt Handler"); + } else { + rng_irq_set = TRUE; + RNG_UNMASK_ALL_INTERRUPTS(); + } + + return error_code; +} /* rng_setup_interrupt_handling */ + +/*****************************************************************************/ +/* fn rng_grab_config_values() */ +/*****************************************************************************/ +/*! + * Read configuration information from the RNG. + * + * Sets #rng_output_fifo_size. + * + * @return A error code indicating whether the part is the expected one. + */ +static os_error_code rng_grab_config_values(void) +{ + enum rng_type type; + os_error_code ret = OS_ERROR_FAIL_S; + + /* Go for type, versions... */ + type = RNG_GET_RNG_TYPE(); + + /* Make sure type is the one this code has been compiled for. */ + if (RNG_VERIFY_TYPE(type)) { + rng_output_fifo_size = RNG_GET_FIFO_SIZE(); + if (rng_output_fifo_size != 0) { + ret = OS_ERROR_OK_S; + } + } + if (ret != OS_ERROR_OK_S) { + LOG_KDIAG_ARGS + ("Unknown or unexpected RNG type %d (FIFO size %d)." + " Failing driver initialization", type, + rng_output_fifo_size); + } + + return ret; +} + + /* rng_grab_config_values */ + +/*****************************************************************************/ +/* fn rng_drain_fifo() */ +/*****************************************************************************/ +/*! + * This function copies words from the RNG FIFO into the caller's buffer. + * + * + * @param random_p Location to copy random data + * @param count_words Number of words to copy + * + * @return An error code. + */ +static fsl_shw_return_t rng_drain_fifo(uint32_t * random_p, int count_words) +{ + + int words_in_rng; /* Number of words available now in RNG */ + fsl_shw_return_t code = FSL_RETURN_ERROR_S; + int sequential_count = 0; /* times through big while w/empty FIFO */ + int fifo_empty_count = 0; /* number of times FIFO was empty */ + int max_sequential = 0; /* max times 0 seen in a row */ +#if !defined(FSL_HAVE_RNGA) + int count_for_reseed = 0; + INIT_COMPLETION(rng_seed_done); +#endif +#if !defined(FSL_HAVE_RNGA) + if (RNG_RESEED()) { + do { + LOG_KDIAG("Reseeding RNG"); + + RNG_CLEAR_ERR(); + RNG_SEED_GEN(); + wait_for_completion(&rng_seed_done); + if (count_for_reseed == 3) { + os_printk(KERN_ALERT + "Device was not able to enter RESEED Mode\n"); + code = FSL_RETURN_INTERNAL_ERROR_S; + } + count_for_reseed++; + } while (RNG_CHECK_SEED_ERR()); + } +#endif + /* Copy all of them in. Stop if pool fills. */ + while ((rng_availability == RNG_STATUS_OK) && (count_words > 0)) { + /* Ask RNG how many words currently in FIFO */ + words_in_rng = RNG_GET_WORDS_IN_FIFO(); + if (words_in_rng == 0) { + ++sequential_count; + fifo_empty_count++; + if (sequential_count > max_sequential) { + max_sequential = sequential_count; + } + if (sequential_count >= RNG_MAX_TRIES) { + LOG_KDIAG_ARGS("FIFO staying empty (%d)", + words_in_rng); + code = FSL_RETURN_NO_RESOURCE_S; + break; + } + } else { + /* Found at least one word */ + sequential_count = 0; + /* Now adjust: words_in_rng = MAX(count_words, words_in_rng) */ + words_in_rng = (count_words < words_in_rng) + ? count_words : words_in_rng; + } /* else found words */ + +#ifdef RNG_FORCE_FIFO_UNDERFLOW + /* + * For unit test, force occasional extraction of more words than + * available. This should cause FIFO Underflow, and IRQ invocation. + */ + words_in_rng = count_words; +#endif + + /* Copy out all available & neeeded data */ + while (words_in_rng-- > 0) { + *random_p++ = RNG_READ_FIFO(); + count_words--; + } + } /* while words still needed */ + + if (count_words == 0) { + code = FSL_RETURN_OK_S; + } + if (fifo_empty_count != 0) { + LOG_KDIAG_ARGS("FIFO empty %d times, max loop count %d", + fifo_empty_count, max_sequential); + } + + return code; +} /* rng_drain_fifo */ + +/*****************************************************************************/ +/* fn rng_entropy_task() */ +/*****************************************************************************/ +/*! + * This is the background task of the driver. It is scheduled by + * RNG_ADD_WORK_ENTRY(). + * + * This will process each entry on the #rng_work_queue. Blocking requests will + * cause sleepers to be awoken. Non-blocking requests will be placed on the + * results queue, and if appropriate, the callback function will be invoked. + */ +OS_DEV_TASK(rng_entropy_task) +{ + rng_work_entry_t *work; + + os_dev_task_begin(); + +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG("entropy task starting"); +#endif + + while ((work = RNG_GET_WORK_ENTRY()) != NULL) { +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG_ARGS("found %d bytes of work at %p (%p)", + work->length, work, work->data_local); +#endif + work->hdr.code = rng_drain_fifo(work->data_local, + BYTES_TO_WORDS(work->length)); + work->completed = TRUE; + + if (work->hdr.flags & FSL_UCO_BLOCKING_MODE) { +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG("Waking queued processes"); +#endif + os_wake_sleepers(rng_wait_queue); + } else { + os_lock_context_t lock_context; + + os_lock_save_context(rng_queue_lock, lock_context); + RNG_ADD_QUEUE_ENTRY(&work->hdr.user_ctx->result_pool, + work); + os_unlock_restore_context(rng_queue_lock, lock_context); + + if (work->hdr.flags & FSL_UCO_CALLBACK_MODE) { + if (work->hdr.callback != NULL) { + work->hdr.callback(work->hdr.user_ctx); + } else { +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG_ARGS + ("Callback ptr for %p is NULL", + work); +#endif + } + } + } + } /* while */ + +#ifdef RNG_ENTROPY_DEBUG + LOG_KDIAG("entropy task ending"); +#endif + + os_dev_task_return(OS_ERROR_OK_S); +} /* rng_entropy_task */ + +#ifdef FSL_HAVE_RNGA +/*****************************************************************************/ +/* fn rng_sec_failure() */ +/*****************************************************************************/ +/*! + * Function to handle "Security Alarm" indication from SCC. + * + * This function is registered with the Security Monitor ans the callback + * function for the RNG driver. Upon alarm, it will shut down the driver so + * that no more random data can be retrieved. + * + * @return void + */ +static void rng_sec_failure(void) +{ + os_printk(KERN_ALERT "RNG Driver: Security Failure Alarm received.\n"); + + rng_cleanup(); + + return; +} +#endif + +#ifdef RNG_REGISTER_DEBUG +/*****************************************************************************/ +/* fn dbg_rng_read_register() */ +/*****************************************************************************/ +/*! + * Noisily read a 32-bit value to an RNG register. + * @param offset The address of the register to read. + * + * @return The register value + * */ +static uint32_t dbg_rng_read_register(uint32_t offset) +{ + uint32_t value; + + value = os_read32(rng_base + offset); +#ifndef RNG_ENTROPY_DEBUG + if (offset != RNG_OUTPUT_FIFO) { +#endif + pr_debug("RNG RD: 0x%4x : 0x%08x\n", offset, value); +#ifndef RNG_ENTROPY_DEBUG + } +#endif + return value; +} + +/*****************************************************************************/ +/* fn dbg_rng_write_register() */ +/*****************************************************************************/ +/*! + * Noisily write a 32-bit value to an RNG register. + * @param offset The address of the register to written. + * + * @param value The new register value + */ +static void dbg_rng_write_register(uint32_t offset, uint32_t value) +{ + LOG_KDIAG_ARGS("WR: 0x%4x : 0x%08x", offset, value); + os_write32(value, rng_base + offset); + return; +} + +#endif /* RNG_REGISTER_DEBUG */ diff --git a/drivers/mxc/security/rng/shw_driver.c b/drivers/mxc/security/rng/shw_driver.c new file mode 100644 index 000000000000..a6e80a0d4eb0 --- /dev/null +++ b/drivers/mxc/security/rng/shw_driver.c @@ -0,0 +1,2335 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! @file shw_driver.c + * + * This is the user-mode driver code for the FSL Security Hardware (SHW) API. + * as well as the 'common' FSL SHW API code for kernel API users. + * + * Its interaction with the Linux kernel is from calls to shw_init() when the + * driver is loaded, and shw_shutdown() should the driver be unloaded. + * + * The User API (driver interface) is handled by the following functions: + * @li shw_open() - handles open() system call on FSL SHW device + * @li shw_release() - handles close() system call on FSL SHW device + * @li shw_ioctl() - handles ioctl() system call on FSL SHW device + * + * The driver also provides the following functions for kernel users of the FSL + * SHW API: + * @li fsl_shw_register_user() + * @li fsl_shw_deregister_user() + * @li fsl_shw_get_capabilities() + * @li fsl_shw_get_results() + * + * All other functions are internal to the driver. + * + * The life of the driver starts at boot (or module load) time, with a call by + * the kernel to shw_init(). + * + * The life of the driver ends when the kernel is shutting down (or the driver + * is being unloaded). At this time, shw_shutdown() is called. No function + * will ever be called after that point. + * + * In the case that the driver is reloaded, a new copy of the driver, with + * fresh global values, etc., is loaded, and there will be a new call to + * shw_init(). + * + * In user mode, the user's fsl_shw_register_user() call causes an open() event + * on the driver followed by a ioctl() with the registration information. Any + * subsequent API calls by the user are handled through the ioctl() function + * and shuffled off to the appropriate routine (or driver) for service. The + * fsl_shw_deregister_user() call by the user results in a close() function + * call on the driver. + * + * In kernel mode, the driver provides the functions fsl_shw_register_user(), + * fsl_shw_deregister_user(), fsl_shw_get_capabilities(), and + * fsl_shw_get_results(). Other parts of the API are provided by other + * drivers, if available, to support the cryptographic functions. + */ + +#include "portable_os.h" +#include "fsl_shw.h" +#include "fsl_shw_keystore.h" + +#include "shw_internals.h" + +#ifdef FSL_HAVE_SCC2 +#include +#else +#include +#endif + +#ifdef SHW_DEBUG +#include +#endif + +/****************************************************************************** + * + * Function Declarations + * + *****************************************************************************/ + +/* kernel interface functions */ +OS_DEV_INIT_DCL(shw_init); +OS_DEV_SHUTDOWN_DCL(shw_shutdown); +OS_DEV_IOCTL_DCL(shw_ioctl); +OS_DEV_MMAP_DCL(shw_mmap); + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_smalloc); +EXPORT_SYMBOL(fsl_shw_sfree); +EXPORT_SYMBOL(fsl_shw_sstatus); +EXPORT_SYMBOL(fsl_shw_diminish_perms); +EXPORT_SYMBOL(do_scc_encrypt_region); +EXPORT_SYMBOL(do_scc_decrypt_region); + +EXPORT_SYMBOL(do_system_keystore_slot_alloc); +EXPORT_SYMBOL(do_system_keystore_slot_dealloc); +EXPORT_SYMBOL(do_system_keystore_slot_load); +EXPORT_SYMBOL(do_system_keystore_slot_encrypt); +EXPORT_SYMBOL(do_system_keystore_slot_decrypt); +#endif + +static os_error_code +shw_handle_scc_sfree(fsl_shw_uco_t * user_ctx, uint32_t info); + +static os_error_code +shw_handle_scc_sstatus(fsl_shw_uco_t * user_ctx, uint32_t info); + +static os_error_code +shw_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx, uint32_t info); + +static os_error_code +shw_handle_scc_encrypt(fsl_shw_uco_t * user_ctx, uint32_t info); + +static os_error_code +shw_handle_scc_decrypt(fsl_shw_uco_t * user_ctx, uint32_t info); + +#ifdef FSL_HAVE_SCC2 +static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base, + void *kernel_base); +static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base); +void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base); + +#endif /* FSL_HAVE_SCC2 */ + +/****************************************************************************** + * + * Global / Static Variables + * + *****************************************************************************/ + +/*! + * Major node (user/device interaction value) of this driver. + */ +static int shw_major_node = SHW_MAJOR_NODE; + +/*! + * Flag to know whether the driver has been associated with its user device + * node (e.g. /dev/shw). + */ +static int shw_device_registered = 0; + +/*! + * OS-dependent handle used for registering user interface of a driver. + */ +static os_driver_reg_t reg_handle; + +/*! + * Linked List of registered users of the API + */ +fsl_shw_uco_t *user_list; + +/*! + * This is the lock for all user request pools. H/W component drivers may also + * use it for their own work queues. + */ +os_lock_t shw_queue_lock = NULL; + +/* This is the system keystore object */ +fsl_shw_kso_t system_keystore; + +#ifndef FSL_HAVE_SAHARA +/*! Empty list of supported symmetric algorithms. */ +static fsl_shw_key_alg_t pf_syms[] = { +}; + +/*! Empty list of supported symmetric modes. */ +static fsl_shw_sym_mode_t pf_modes[] = { +}; + +/*! Empty list of supported hash algorithms. */ +static fsl_shw_hash_alg_t pf_hashes[] = { +}; +#endif /* no Sahara */ + +/*! This matches SHW capabilities... */ +static fsl_shw_pco_t cap = { + 1, 3, /* api version number - major & minor */ + 2, 3, /* driver version number - major & minor */ + sizeof(pf_syms) / sizeof(fsl_shw_key_alg_t), /* key alg count */ + pf_syms, /* key alg list ptr */ + sizeof(pf_modes) / sizeof(fsl_shw_sym_mode_t), /* sym mode count */ + pf_modes, /* modes list ptr */ + sizeof(pf_hashes) / sizeof(fsl_shw_hash_alg_t), /* hash alg count */ + pf_hashes, /* hash list ptr */ + /* + * The following table must be set to handle all values of key algorithm + * and sym mode, and be in the correct order.. + */ + { /* Stream, ECB, CBC, CTR */ + {0, 0, 0, 0} + , /* HMAC */ + {0, 0, 0, 0} + , /* AES */ + {0, 0, 0, 0} + , /* DES */ +#ifdef FSL_HAVE_DRYICE + {0, 1, 1, 0} + , /* 3DES - ECB and CBC */ +#else + {0, 0, 0, 0} + , /* 3DES */ +#endif + {0, 0, 0, 0} /* ARC4 */ + } + , + 0, 0, /* SCC driver version */ + 0, 0, 0, /* SCC version/capabilities */ + {{0, 0} + } + , /* (filled in during OS_INIT) */ +}; + +/* These are often handy */ +#ifndef FALSE +/*! Not true. Guaranteed to be zero. */ +#define FALSE 0 +#endif +#ifndef TRUE +/*! True. Guaranteed to be non-zero. */ +#define TRUE 1 +#endif + +/****************************************************************************** + * + * Function Implementations - Externally Accessible + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn shw_init() */ +/*****************************************************************************/ +/*! + * Initialize the driver. + * + * This routine is called during kernel init or module load (insmod). + * + * @return OS_ERROR_OK_S on success, errno on failure + */ +OS_DEV_INIT(shw_init) +{ + os_error_code error_code = OS_ERROR_NO_MEMORY_S; /* assume failure */ + scc_config_t *shw_capabilities; + +#ifdef SHW_DEBUG + LOG_KDIAG("SHW Driver: Loading"); +#endif + + user_list = NULL; + shw_queue_lock = os_lock_alloc_init(); + + if (shw_queue_lock != NULL) { + error_code = shw_setup_user_driver_interaction(); + if (error_code != OS_ERROR_OK_S) { +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("SHW Driver: Failed to setup user i/f: %d", + error_code); +#endif + } + } + + /* queue_lock not NULL */ + /* Fill in the SCC portion of the capabilities object */ + shw_capabilities = scc_get_configuration(); + cap.scc_driver_major = shw_capabilities->driver_major_version; + cap.scc_driver_minor = shw_capabilities->driver_minor_version; + cap.scm_version = shw_capabilities->scm_version; + cap.smn_version = shw_capabilities->smn_version; + cap.block_size_bytes = shw_capabilities->block_size_bytes; + +#ifdef FSL_HAVE_SCC + cap.u.scc_info.black_ram_size_blocks = + shw_capabilities->black_ram_size_blocks; + cap.u.scc_info.red_ram_size_blocks = + shw_capabilities->red_ram_size_blocks; +#elif defined(FSL_HAVE_SCC2) + cap.u.scc2_info.partition_size_bytes = + shw_capabilities->partition_size_bytes; + cap.u.scc2_info.partition_count = shw_capabilities->partition_count; +#endif + +#if defined(FSL_HAVE_SCC2) || defined(FSL_HAVE_DRYICE) + if (error_code == OS_ERROR_OK_S) { + /* set up the system keystore, using the default keystore handler */ + fsl_shw_init_keystore_default(&system_keystore); + + if (fsl_shw_establish_keystore(NULL, &system_keystore) + == FSL_RETURN_OK_S) { + error_code = OS_ERROR_OK_S; + } else { + error_code = OS_ERROR_FAIL_S; + } + + if (error_code != OS_ERROR_OK_S) { +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("Registering the system keystore failed with error" + " code: %d\n", error_code); +#endif + } + } +#endif /* FSL_HAVE_SCC2 */ + + if (error_code != OS_ERROR_OK_S) { +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: Driver initialization failed. %d", + error_code); +#endif + shw_cleanup(); + } else { +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: Driver initialization complete."); +#endif + } + + os_dev_init_return(error_code); +} /* shw_init */ + +/*****************************************************************************/ +/* fn shw_shutdown() */ +/*****************************************************************************/ +/*! + * Prepare driver for exit. + * + * This is called during @c rmmod when the driver is unloading or when the + * kernel is shutting down. + * + * Calls shw_cleanup() to do all work to undo anything that happened during + * initialization or while driver was running. + */ +OS_DEV_SHUTDOWN(shw_shutdown) +{ + +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: shutdown called"); +#endif + shw_cleanup(); + + os_dev_shutdown_return(OS_ERROR_OK_S); +} /* shw_shutdown */ + +/*****************************************************************************/ +/* fn shw_cleanup() */ +/*****************************************************************************/ +/*! + * Prepare driver for shutdown. + * + * Remove the driver registration. + * + */ +static void shw_cleanup(void) +{ + if (shw_device_registered) { + + /* Turn off the all association with OS */ + os_driver_remove_registration(reg_handle); + shw_device_registered = 0; + } + + if (shw_queue_lock != NULL) { + os_lock_deallocate(shw_queue_lock); + } +#ifdef SHW_DEBUG + LOG_KDIAG("SHW Driver: Cleaned up"); +#endif +} /* shw_cleanup */ + +/*****************************************************************************/ +/* fn shw_open() */ +/*****************************************************************************/ +/*! + * Handle @c open() call from user. + * + * @return OS_ERROR_OK_S on success (always!) + */ +OS_DEV_OPEN(shw_open) +{ + os_error_code status = OS_ERROR_OK_S; + + os_dev_set_user_private(NULL); /* Make sure */ + + os_dev_open_return(status); +} /* shw_open */ + +/*****************************************************************************/ +/* fn shw_ioctl() */ +/*****************************************************************************/ +/*! + * Process an ioctl() request from user-mode API. + * + * This code determines which of the API requests the user has made and then + * sends the request off to the appropriate function. + * + * @return ioctl_return() + */ +OS_DEV_IOCTL(shw_ioctl) +{ + os_error_code code = OS_ERROR_FAIL_S; + + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: IOCTL %d received", os_dev_get_ioctl_op()); +#endif + switch (os_dev_get_ioctl_op()) { + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_REGISTER_USER: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: register_user ioctl received"); +#endif + { + fsl_shw_uco_t *user_ctx = + os_alloc_memory(sizeof(*user_ctx), 0); + + if (user_ctx == NULL) { + code = OS_ERROR_NO_MEMORY_S; + } else { + code = + init_uco(user_ctx, + (fsl_shw_uco_t *) + os_dev_get_ioctl_arg()); + if (code == OS_ERROR_OK_S) { + os_dev_set_user_private(user_ctx); + } else { + os_free_memory(user_ctx); + } + } + } + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_DEREGISTER_USER: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: deregister_user ioctl received"); +#endif + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + SHW_REMOVE_USER(user_ctx); + } + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_RESULTS: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: get_results ioctl received"); +#endif + code = get_results(user_ctx, + (struct results_req *) + os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_CAPABILITIES: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: get_capabilities ioctl received"); +#endif + code = get_capabilities(user_ctx, + (fsl_shw_pco_t *) + os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_GET_RANDOM: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: get_random ioctl received"); +#endif + code = get_random(user_ctx, + (struct get_random_req *) + os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_ADD_ENTROPY: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: add_entropy ioctl received"); +#endif + code = add_entropy(user_ctx, + (struct add_entropy_req *) + os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_DROP_PERMS: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: drop permissions ioctl received"); +#endif + code = + shw_handle_scc_drop_perms(user_ctx, os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_SSTATUS: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: sstatus ioctl received"); +#endif + code = shw_handle_scc_sstatus(user_ctx, os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_SFREE: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: sfree ioctl received"); +#endif + code = shw_handle_scc_sfree(user_ctx, os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_SCC_ENCRYPT: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: scc encrypt ioctl received"); +#endif + code = shw_handle_scc_encrypt(user_ctx, os_dev_get_ioctl_arg()); + break; + + case SHW_IOCTL_REQUEST + SHW_USER_REQ_SCC_DECRYPT: +#ifdef SHW_DEBUG + LOG_KDIAG("SHW: scc decrypt ioctl received"); +#endif + code = shw_handle_scc_decrypt(user_ctx, os_dev_get_ioctl_arg()); + break; + + default: +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: Unexpected ioctl %d", + os_dev_get_ioctl_op()); +#endif + break; + } + + os_dev_ioctl_return(code); +} + +#ifdef FSL_HAVE_SCC2 + +/*****************************************************************************/ +/* fn get_user_smid() */ +/*****************************************************************************/ +uint32_t get_user_smid(void *proc) +{ + /* + * A real implementation would have some way to handle signed applications + * which wouild be assigned distinct SMIDs. For the reference + * implementation, we show where this would be determined (here), but + * always provide a fixed answer, thus not separating users at all. + */ + + return 0x42eaae42; +} + +/* user_base: userspace base address of the partition + * kernel_base: kernel mode base address of the partition + */ +static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base, + void *kernel_base) +{ + fsl_shw_spo_t *partition_info; + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + if (user_ctx == NULL) { + goto out; + } + + partition_info = os_alloc_memory(sizeof(fsl_shw_spo_t), GFP_KERNEL); + + if (partition_info == NULL) { + goto out; + } + + /* stuff the partition info, then put it at the front of the chain */ + partition_info->user_base = user_base; + partition_info->kernel_base = kernel_base; + partition_info->next = user_ctx->partition; + + user_ctx->partition = (struct fsl_shw_spo_t *)partition_info; + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("partition with user_base=%p, kernel_base=%p registered.", + (void *)user_base, kernel_base); +#endif + + ret = FSL_RETURN_OK_S; + + out: + + return ret; +} + +/* if the partition is in the users list, remove it */ +static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base) +{ + fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition; + fsl_shw_spo_t *last = (fsl_shw_spo_t *) user_ctx->partition; + + while (curr != NULL) { + if (curr->user_base == user_base) { + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("deregister_user_partition: partition with " + "user_base=%p, kernel_base=%p deregistered.\n", + (void *)curr->user_base, curr->kernel_base); +#endif + + if (last == curr) { + user_ctx->partition = curr->next; + os_free_memory(curr); + return FSL_RETURN_OK_S; + } else { + last->next = curr->next; + os_free_memory(curr); + return FSL_RETURN_OK_S; + } + } + last = curr; + curr = (fsl_shw_spo_t *) curr->next; + } + + return FSL_RETURN_ERROR_S; +} + +/* Find the kernel-mode address of the partition. + * This can then be passed to the SCC functions. + */ +void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base) +{ + /* search through the partition chain to find one that matches the user base + * address. + */ + fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition; + + while (curr != NULL) { + if (curr->user_base == user_base) { + return curr->kernel_base; + } + curr = (fsl_shw_spo_t *) curr->next; + } + return NULL; +} + +#endif /* FSL_HAVE_SCC2 */ + +/*! +******************************************************************************* +* This function implements the smalloc() function for userspace programs, by +* making a call to the SCC2 mmap() function that acquires a region of secure +* memory on behalf of the user, and then maps it into the users memory space. +* Currently, the only memory size supported is that of a single SCC2 partition. +* Requests for other sized memory regions will fail. +*/ +OS_DEV_MMAP(shw_mmap) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; + +#ifdef FSL_HAVE_SCC2 + { + scc_return_t scc_ret; + fsl_shw_return_t fsl_ret; + uint32_t partition_registered = FALSE; + + uint32_t user_base; + void *partition_base; + uint32_t smid; + scc_config_t *scc_configuration; + + int part_no = -1; + uint32_t part_phys; + + fsl_shw_uco_t *user_ctx = + (fsl_shw_uco_t *) os_dev_get_user_private(); + + /* Make sure that the user context is valid */ + if (user_ctx == NULL) { + user_ctx = + os_alloc_memory(sizeof(*user_ctx), GFP_KERNEL); + + if (user_ctx == NULL) { + status = OS_ERROR_NO_MEMORY_S; + goto out; + } + fsl_shw_register_user(user_ctx); + os_dev_set_user_private(user_ctx); + } + + /* Determine the size of a secure partition */ + scc_configuration = scc_get_configuration(); + + /* Check that the memory size requested is equal to the partition + * size, and that the requested destination is on a page boundary. + */ + if (((os_mmap_user_base() % PAGE_SIZE) != 0) || + (os_mmap_memory_size() != + scc_configuration->partition_size_bytes)) { + status = OS_ERROR_BAD_ARG_S; + goto out; + } + + /* Retrieve the SMID associated with the user */ + smid = get_user_smid(user_ctx->process); + + /* Attempt to allocate a secure partition */ + scc_ret = + scc_allocate_partition(smid, &part_no, &partition_base, + &part_phys); + if (scc_ret != SCC_RET_OK) { + pr_debug + ("SCC mmap() request failed to allocate partition;" + " error %d\n", status); + status = OS_ERROR_FAIL_S; + goto out; + } + + pr_debug("scc_mmap() acquired partition %d at %08x\n", + part_no, part_phys); + + /* Record partition info in the user context */ + user_base = os_mmap_user_base(); + fsl_ret = + register_user_partition(user_ctx, user_base, + partition_base); + + if (fsl_ret != FSL_RETURN_OK_S) { + pr_debug + ("SCC mmap() request failed to register partition with user" + " context, error: %d\n", fsl_ret); + status = OS_ERROR_FAIL_S; + } + + partition_registered = TRUE; + + status = map_user_memory(os_mmap_memory_ctx(), part_phys, + os_mmap_memory_size()); + +#ifdef SHW_DEBUG + if (status == OS_ERROR_OK_S) { + LOG_KDIAG_ARGS + ("Partition allocated: user_base=%p, partition_base=%p.", + (void *)user_base, partition_base); + } +#endif + + out: + /* If there is an error it has to be handled here */ + if (status != OS_ERROR_OK_S) { + /* if the partition was registered with the user, unregister it. */ + if (partition_registered == TRUE) { + deregister_user_partition(user_ctx, user_base); + } + + /* if the partition was allocated, deallocate it */ + if (partition_base != NULL) { + scc_release_partition(partition_base); + } + } + } +#endif /* FSL_HAVE_SCC2 */ + + return status; +} + +/*****************************************************************************/ +/* fn shw_release() */ +/*****************************************************************************/ +/*! + * Handle @c close() call from user. + * This is a Linux device driver interface routine. + * + * @return OS_ERROR_OK_S on success (always!) + */ +OS_DEV_CLOSE(shw_release) +{ + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + os_error_code code = OS_ERROR_OK_S; + + if (user_ctx != NULL) { + + fsl_shw_deregister_user(user_ctx); + os_free_memory(user_ctx); + os_dev_set_user_private(NULL); + + } + + os_dev_close_return(code); +} /* shw_release */ + +/*****************************************************************************/ +/* fn shw_user_callback() */ +/*****************************************************************************/ +/*! + * FSL SHW User callback function. + * + * This function is set in the kernel version of the user context as the + * callback function when the user mode user wants a callback. Its job is to + * inform the user process that results (may) be available. It does this by + * sending a SIGUSR2 signal which is then caught by the user-mode FSL SHW + * library. + * + * @param user_ctx Kernel version of uco associated with the request. + * + * @return void + */ +static void shw_user_callback(fsl_shw_uco_t * user_ctx) +{ +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: Signalling callback user process for context %p\n", + user_ctx); +#endif + os_send_signal(user_ctx->process, SIGUSR2); +} + +/*****************************************************************************/ +/* fn setup_user_driver_interaction() */ +/*****************************************************************************/ +/*! + * Register the driver with the kernel as the driver for shw_major_node. Note + * that this value may be zero, in which case the major number will be assigned + * by the OS. shw_major_node is never modified. + * + * The open(), ioctl(), and close() handles for the driver ned to be registered + * with the kernel. Upon success, shw_device_registered will be true; + * + * @return OS_ERROR_OK_S on success, or an os err code + */ +static os_error_code shw_setup_user_driver_interaction(void) +{ + os_error_code error_code; + + os_driver_init_registration(reg_handle); + os_driver_add_registration(reg_handle, OS_FN_OPEN, + OS_DEV_OPEN_REF(shw_open)); + os_driver_add_registration(reg_handle, OS_FN_IOCTL, + OS_DEV_IOCTL_REF(shw_ioctl)); + os_driver_add_registration(reg_handle, OS_FN_CLOSE, + OS_DEV_CLOSE_REF(shw_release)); + os_driver_add_registration(reg_handle, OS_FN_MMAP, + OS_DEV_MMAP_REF(shw_mmap)); + error_code = os_driver_complete_registration(reg_handle, shw_major_node, + SHW_DRIVER_NAME); + + if (error_code != OS_ERROR_OK_S) { + /* failure ! */ +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW Driver: register device driver failed: %d", + error_code); +#endif + } else { /* success */ + shw_device_registered = TRUE; +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW Driver: Major node is %d\n", + os_driver_get_major(reg_handle)); +#endif + } + + return error_code; +} /* shw_setup_user_driver_interaction */ + +/******************************************************************/ +/* User Mode Support */ +/******************************************************************/ + +/*! + * Initialze kernel User Context Object from User-space version. + * + * Copy user UCO into kernel UCO, set flags and fields for operation + * within kernel space. Add user to driver's list of users. + * + * @param user_ctx Pointer to kernel space UCO + * @param user_mode_uco User pointer to user space version + * + * @return os_error_code + */ +static os_error_code init_uco(fsl_shw_uco_t * user_ctx, void *user_mode_uco) +{ + os_error_code code; + + code = os_copy_from_user(user_ctx, user_mode_uco, sizeof(*user_ctx)); + if (code == OS_ERROR_OK_S) { + user_ctx->flags |= FSL_UCO_USERMODE_USER; + user_ctx->result_pool.head = NULL; + user_ctx->result_pool.tail = NULL; + user_ctx->process = os_get_process_handle(); + user_ctx->callback = shw_user_callback; + SHW_ADD_USER(user_ctx); + } +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: init uco returning %d (flags %x)", + code, user_ctx->flags); +#endif + + return code; +} + +/*! + * Copy array from kernel to user space. + * + * This routine will check bounds before trying to copy, and return failure + * on bounds violation or error during the copy. + * + * @param userloc Location in userloc to place data. If NULL, the function + * will do nothing (except return NULL). + * @param userend Address beyond allowed copy region at @c userloc. + * @param data_start Location of data to be copied + * @param element_size sizeof() an element + * @param element_count Number of elements of size element_size to copy. + * @return New value of userloc, or NULL if there was an error. + */ +inline static void *copy_array(void *userloc, void *userend, void *data_start, + unsigned element_size, unsigned element_count) +{ + unsigned byte_count = element_size * element_count; + + if ((userloc == NULL) || (userend == NULL) + || ((userloc + byte_count) >= userend) || + (copy_to_user(userloc, data_start, byte_count) != OS_ERROR_OK_S)) { + userloc = NULL; + } else { + userloc += byte_count; + } + + return userloc; +} + +/*! + * Send an FSL SHW API return code up into the user-space request structure. + * + * @param user_header User address of request block / request header + * @param result_code The FSL SHW API code to be placed at header.code + * + * @return an os_error_code + * + * NOTE: This function assumes that the shw_req_header is at the beginning of + * each request structure. + */ +inline static os_error_code copy_fsl_code(void *user_header, + fsl_shw_return_t result_code) +{ + return os_copy_to_user(user_header + + offsetof(struct shw_req_header, code), + &result_code, sizeof(result_code)); +} + +static os_error_code shw_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + scc_return_t scc_ret; + scc_partition_info_t partition_info; + void *kernel_base; + + status = + os_copy_from_user(&partition_info, (void *)info, + sizeof(partition_info)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("_scc_drop_perms(): failed to find partition\n"); +#endif + goto out; + } + + /* call scc driver to perform the drop */ + scc_ret = scc_diminish_permissions(kernel_base, + partition_info.permissions); + if (scc_ret == SCC_RET_OK) { + status = OS_ERROR_OK_S; + } else { + status = OS_ERROR_FAIL_S; + } + + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code shw_handle_scc_sstatus(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + scc_partition_info_t partition_info; + void *kernel_base; + + status = os_copy_from_user(&partition_info, + (void *)info, sizeof(partition_info)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("Failed to find partition\n"); +#endif + goto out; + } + + /* Call the SCC driver to ask about the partition status */ + partition_info.status = scc_partition_status(kernel_base); + + /* and copy the structure out */ + status = os_copy_to_user((void *)info, + &partition_info, sizeof(partition_info)); + + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code shw_handle_scc_sfree(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + { + scc_partition_info_t partition_info; + void *kernel_base; + int ret; + + status = os_copy_from_user(&partition_info, + (void *)info, + sizeof(partition_info)); + + /* check that the copy was successful */ + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = + lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("failed to find partition\n"); +#endif /*SHW_DEBUG */ + goto out; + } + + /* Unmap the memory region (see sys_munmap in mmap.c) */ + ret = unmap_user_memory(partition_info.user_base, 8192); + + /* If the memory was successfully released */ + if (ret == OS_ERROR_OK_S) { + + /* release the partition */ + scc_release_partition(kernel_base); + + /* and remove it from the users context */ + deregister_user_partition(user_ctx, + partition_info.user_base); + + status = OS_ERROR_OK_S; + + } else { +#ifdef SHW_DEBUG + LOG_KDIAG("do_munmap not successful!"); +#endif + } + + } + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code shw_handle_scc_encrypt(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_FAIL_S; +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_return_t retval; + scc_region_t region_info; + void *page_ctx = NULL; + void *black_addr = NULL; + void *partition_base = NULL; + scc_config_t *scc_configuration; + + status = + os_copy_from_user(®ion_info, (void *)info, + sizeof(region_info)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + partition_base = lookup_user_partition(user_ctx, + region_info. + partition_base); + + if (partition_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("failed to find secure partition\n"); +#endif + goto out; + } + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (region_info.offset + region_info.length > + scc_configuration->partition_size_bytes) { + status = OS_ERROR_FAIL_S; + goto out; + } + + /* wire down black_data */ + black_addr = wire_user_memory(region_info.black_data, + region_info.length, &page_ctx); + + if (black_addr == NULL) { + status = OS_ERROR_FAIL_S; + goto out; + } + + retval = + do_scc_encrypt_region(NULL, partition_base, + region_info.offset, + region_info.length, black_addr, + region_info.IV, + region_info.cypher_mode); + + if (retval == FSL_RETURN_OK_S) { + status = OS_ERROR_OK_S; + } else { + status = OS_ERROR_FAIL_S; + } + + /* release black data */ + unwire_user_memory(&page_ctx); + } + out: + +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code shw_handle_scc_decrypt(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_FAIL_S; +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_return_t retval; + scc_region_t region_info; + void *page_ctx = NULL; + void *black_addr; + void *partition_base; + scc_config_t *scc_configuration; + + status = + os_copy_from_user(®ion_info, (void *)info, + sizeof(region_info)); + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("partition_base: %p, offset: %i, length: %i, black data: %p", + (void *)region_info.partition_base, region_info.offset, + region_info.length, (void *)region_info.black_data); +#endif + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + partition_base = lookup_user_partition(user_ctx, + region_info. + partition_base); + + if (partition_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef SHW_DEBUG + LOG_KDIAG("failed to find partition\n"); +#endif + goto out; + } + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (region_info.offset + region_info.length > + scc_configuration->partition_size_bytes) { + status = OS_ERROR_FAIL_S; + goto out; + } + + /* wire down black_data */ + black_addr = wire_user_memory(region_info.black_data, + region_info.length, &page_ctx); + + if (black_addr == NULL) { + status = OS_ERROR_FAIL_S; + goto out; + } + + retval = + do_scc_decrypt_region(NULL, partition_base, + region_info.offset, + region_info.length, black_addr, + region_info.IV, + region_info.cypher_mode); + + if (retval == FSL_RETURN_OK_S) { + status = OS_ERROR_OK_S; + } else { + status = OS_ERROR_FAIL_S; + } + + /* release black data */ + unwire_user_memory(&page_ctx); + } + out: + +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx, + uint32_t key_length, + uint64_t ownerid, + uint32_t * slot) +{ + (void)user_ctx; + return keystore_slot_alloc(&system_keystore, key_length, ownerid, slot); +} + +fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot) +{ + (void)user_ctx; + return keystore_slot_dealloc(&system_keystore, ownerid, slot); +} + +fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + const uint8_t * key, + uint32_t key_length) +{ + (void)user_ctx; + return keystore_slot_load(&system_keystore, ownerid, slot, + (void *)key, key_length); +} + +fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t * black_data) +{ + (void)user_ctx; + return keystore_slot_encrypt(NULL, &system_keystore, ownerid, + slot, key_length, black_data); +} + +fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * black_data) +{ + (void)user_ctx; + return keystore_slot_decrypt(NULL, &system_keystore, ownerid, + slot, key_length, black_data); +} + +fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t * key_data) +{ + (void)user_ctx; + + return keystore_slot_read(&system_keystore, ownerid, + slot, key_length, key_data); +} + +/*! + * Handle user-mode Get Capabilities request + * + * Right now, this function can only have a failure if the user has failed to + * provide a pointer to a location in user space with enough room to hold the + * fsl_shw_pco_t structure and any associated data. It will treat this failure + * as an ioctl failure and return an ioctl error code, instead of treating it + * as an API failure. + * + * @param user_ctx The kernel version of user's context + * @param user_mode_pco_request Pointer to user-space request + * + * @return an os_error_code + */ +static os_error_code get_capabilities(fsl_shw_uco_t * user_ctx, + void *user_mode_pco_request) +{ + os_error_code code; + struct capabilities_req req; + fsl_shw_pco_t local_cap; + + memcpy(&local_cap, &cap, sizeof(cap)); + /* Initialize pointers to out-of-struct arrays */ + local_cap.sym_algorithms = NULL; + local_cap.sym_modes = NULL; + local_cap.sym_modes = NULL; + + code = os_copy_from_user(&req, user_mode_pco_request, sizeof(req)); + if (code == OS_ERROR_OK_S) { + void *endcap; + void *user_bounds; +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHE: Received get_cap request: 0x%p/%u/0x%x", + req.capabilities, req.size, + sizeof(fsl_shw_pco_t)); +#endif + endcap = req.capabilities + 1; /* point to end of structure */ + user_bounds = (void *)req.capabilities + req.size; /* end of area */ + + /* First verify that request is big enough for the main structure */ + if (endcap >= user_bounds) { + endcap = NULL; /* No! */ + } + + /* Copy any Symmetric Algorithm suppport */ + if (cap.sym_algorithm_count != 0) { + local_cap.sym_algorithms = endcap; + endcap = + copy_array(endcap, user_bounds, cap.sym_algorithms, + sizeof(fsl_shw_key_alg_t), + cap.sym_algorithm_count); + } + + /* Copy any Symmetric Modes suppport */ + if (cap.sym_mode_count != 0) { + local_cap.sym_modes = endcap; + endcap = copy_array(endcap, user_bounds, cap.sym_modes, + sizeof(fsl_shw_sym_mode_t), + cap.sym_mode_count); + } + + /* Copy any Hash Algorithm suppport */ + if (cap.hash_algorithm_count != 0) { + local_cap.hash_algorithms = endcap; + endcap = + copy_array(endcap, user_bounds, cap.hash_algorithms, + sizeof(fsl_shw_hash_alg_t), + cap.hash_algorithm_count); + } + + /* Now copy up the (possibly modified) main structure */ + if (endcap != NULL) { + code = + os_copy_to_user(req.capabilities, &local_cap, + sizeof(cap)); + } + + if (endcap == NULL) { + code = OS_ERROR_BAD_ADDRESS_S; + } + + /* And return the FSL SHW code in the request structure. */ + if (code == OS_ERROR_OK_S) { + code = + copy_fsl_code(user_mode_pco_request, + FSL_RETURN_OK_S); + } + } + + /* code may already be set to an error. This is another error case. */ + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: get capabilities returning %d", code); +#endif + + return code; +} + +/*! + * Handle user-mode Get Results request + * + * Get arguments from user space into kernel space, then call + * fsl_shw_get_results, and then copy its return code and any results from + * kernel space back to user space. + * + * @param user_ctx The kernel version of user's context + * @param user_mode_results_req Pointer to user-space request + * + * @return an os_error_code + */ +static os_error_code get_results(fsl_shw_uco_t * user_ctx, + void *user_mode_results_req) +{ + os_error_code code; + struct results_req req; + fsl_shw_result_t *results = NULL; + int loop; + + code = os_copy_from_user(&req, user_mode_results_req, sizeof(req)); + loop = 0; + + if (code == OS_ERROR_OK_S) { + results = os_alloc_memory(req.requested * sizeof(*results), 0); + if (results == NULL) { + code = OS_ERROR_NO_MEMORY_S; + } + } + + if (code == OS_ERROR_OK_S) { + fsl_shw_return_t err = + fsl_shw_get_results(user_ctx, req.requested, + results, &req.actual); + + /* Send API return code up to user. */ + code = copy_fsl_code(user_mode_results_req, err); + + if ((code == OS_ERROR_OK_S) && (err == FSL_RETURN_OK_S)) { + /* Now copy up the result count */ + code = os_copy_to_user(user_mode_results_req + + offsetof(struct results_req, + actual), &req.actual, + sizeof(req.actual)); + if ((code == OS_ERROR_OK_S) && (req.actual != 0)) { + /* now copy up the results... */ + code = os_copy_to_user(req.results, results, + req.actual * + sizeof(*results)); + } + } + } + + if (results != NULL) { + os_free_memory(results); + } + + return code; +} + +/*! + * Process header of user-mode request. + * + * Mark header as User Mode request. Update UCO's flags and reference fields + * with current versions from the header. + * + * @param user_ctx Pointer to kernel version of UCO. + * @param hdr Pointer to common part of user request. + * + * @return void + */ +inline static void process_hdr(fsl_shw_uco_t * user_ctx, + struct shw_req_header *hdr) +{ + hdr->flags |= FSL_UCO_USERMODE_USER; + user_ctx->flags = hdr->flags; + user_ctx->user_ref = hdr->user_ref; + + return; +} + +/*! + * Handle user-mode Get Random request + * + * @param user_ctx The kernel version of user's context + * @param user_mode_get_random_req Pointer to user-space request + * + * @return an os_error_code + */ +static os_error_code get_random(fsl_shw_uco_t * user_ctx, + void *user_mode_get_random_req) +{ + os_error_code code; + struct get_random_req req; + + code = os_copy_from_user(&req, user_mode_get_random_req, sizeof(req)); + if (code == OS_ERROR_OK_S) { + process_hdr(user_ctx, &req.hdr); +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("SHW: get_random() for %d bytes in %sblocking mode", + req.size, + (req.hdr.flags & FSL_UCO_BLOCKING_MODE) ? "" : "non-"); +#endif + req.hdr.code = + fsl_shw_get_random(user_ctx, req.size, req.random); + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("SHW: get_random() returning %d", req.hdr.code); +#endif + + /* Copy FSL function status back to user */ + code = copy_fsl_code(user_mode_get_random_req, req.hdr.code); + } + + return code; +} + +/*! + * Handle user-mode Add Entropy request + * + * @param user_ctx Pointer to the kernel version of user's context + * @param user_mode_add_entropy_req Address of user-space request + * + * @return an os_error_code + */ +static os_error_code add_entropy(fsl_shw_uco_t * user_ctx, + void *user_mode_add_entropy_req) +{ + os_error_code code; + struct add_entropy_req req; + uint8_t *local_buffer = NULL; + + code = os_copy_from_user(&req, user_mode_add_entropy_req, sizeof(req)); + if (code == OS_ERROR_OK_S) { + local_buffer = os_alloc_memory(req.size, 0); /* for random */ + if (local_buffer != NULL) { + code = + os_copy_from_user(local_buffer, req.entropy, + req.size); + } + if (code == OS_ERROR_OK_S) { + req.hdr.code = fsl_shw_add_entropy(user_ctx, req.size, + local_buffer); + + code = + copy_fsl_code(user_mode_add_entropy_req, + req.hdr.code); + } + } + + if (local_buffer != NULL) { + os_free_memory(local_buffer); + } + + return code; +} + +/******************************************************************/ +/* End User Mode Support */ +/******************************************************************/ + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_register_user); +#endif +/* REQ-S2LRD-PINTFC-API-GEN-004 */ +/* + * Handle user registration. + * + * @param user_ctx The user context for the registration. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_return_t code = FSL_RETURN_INTERNAL_ERROR_S; + + if ((user_ctx->flags & FSL_UCO_BLOCKING_MODE) && + (user_ctx->flags & FSL_UCO_CALLBACK_MODE)) { + code = FSL_RETURN_BAD_FLAG_S; + goto error_exit; + } else if (user_ctx->pool_size == 0) { + code = FSL_RETURN_NO_RESOURCE_S; + goto error_exit; + } else { + user_ctx->result_pool.head = NULL; + user_ctx->result_pool.tail = NULL; + SHW_ADD_USER(user_ctx); + code = FSL_RETURN_OK_S; + } + + error_exit: + return code; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_deregister_user); +#endif +/* REQ-S2LRD-PINTFC-API-GEN-005 */ +/*! + * Destroy the association between the the user and the provider of the API. + * + * @param user_ctx The user context which is no longer needed. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx) +{ + shw_queue_entry_t *finished_request; + fsl_shw_return_t ret = FSL_RETURN_OK_S; + + /* Clean up what we find in result pool. */ + do { + os_lock_context_t lock_context; + os_lock_save_context(shw_queue_lock, lock_context); + finished_request = user_ctx->result_pool.head; + + if (finished_request != NULL) { + SHW_QUEUE_REMOVE_ENTRY(&user_ctx->result_pool, + finished_request); + os_unlock_restore_context(shw_queue_lock, lock_context); + os_free_memory(finished_request); + } else { + os_unlock_restore_context(shw_queue_lock, lock_context); + } + } while (finished_request != NULL); + +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_spo_t *partition; + struct mm_struct *mm = current->mm; + + while ((user_ctx->partition != NULL) + && (ret == FSL_RETURN_OK_S)) { + + partition = user_ctx->partition; + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS + ("Found an abandoned secure partition at %p, releasing", + partition); +#endif + + /* It appears that current->mm is not valid if this is called from a + * close routine (perhaps only if the program raised an exception that + * caused it to close?) If that is the case, then still free the + * partition, but do not remove it from the memory space (dangerous?) + */ + + if (mm == NULL) { +#ifdef SHW_DEBUG + LOG_KDIAG + ("Warning: no mm structure found, not unmapping " + "partition from user memory\n"); +#endif + } else { + /* Unmap the memory region (see sys_munmap in mmap.c) */ + /* Note that this assumes a single memory partition */ + unmap_user_memory(partition->user_base, 8192); + } + + /* If the memory was successfully released */ + if (ret == OS_ERROR_OK_S) { + /* release the partition */ + scc_release_partition(partition->kernel_base); + + /* and remove it from the users context */ + deregister_user_partition(user_ctx, + partition->user_base); + + ret = FSL_RETURN_OK_S; + } else { + ret = FSL_RETURN_ERROR_S; + + goto out; + } + } + } + out: +#endif /* FSL_HAVE_SCC2 */ + + SHW_REMOVE_USER(user_ctx); + + return ret; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_get_results); +#endif +/* REQ-S2LRD-PINTFC-API-GEN-006 */ +fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx, + unsigned result_size, + fsl_shw_result_t results[], + unsigned *result_count) +{ + shw_queue_entry_t *finished_request; + unsigned loop = 0; + + do { + os_lock_context_t lock_context; + + /* Protect state of user's result pool until we have retrieved and + * remove the first entry, or determined that the pool is empty. */ + os_lock_save_context(shw_queue_lock, lock_context); + finished_request = user_ctx->result_pool.head; + + if (finished_request != NULL) { + uint32_t code = 0; + + SHW_QUEUE_REMOVE_ENTRY(&user_ctx->result_pool, + finished_request); + os_unlock_restore_context(shw_queue_lock, lock_context); + + results[loop].user_ref = finished_request->user_ref; + results[loop].code = finished_request->code; + results[loop].detail1 = 0; + results[loop].detail2 = 0; + results[loop].user_req = + finished_request->user_mode_req; + if (finished_request->postprocess != NULL) { + code = + finished_request-> + postprocess(finished_request); + } + + results[loop].code = finished_request->code; + os_free_memory(finished_request); + if (code == 0) { + loop++; + } + } else { /* finished_request is NULL */ + /* pool is empty */ + os_unlock_restore_context(shw_queue_lock, lock_context); + } + + } while ((loop < result_size) && (finished_request != NULL)); + + *result_count = loop; + + return FSL_RETURN_OK_S; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_get_capabilities); +#endif +fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx) +{ + + /* Unused */ + (void)user_ctx; + + return ∩ +} + +#if !(defined(FSL_HAVE_SAHARA) || defined(FSL_HAVE_RNGA) \ + || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC)) + +#if defined(LINUX_VERSION_CODE) +EXPORT_SYMBOL(fsl_shw_get_random); +#endif +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + + /* Unused */ + (void)user_ctx; + (void)length; + (void)data; + + return FSL_RETURN_ERROR_S; +} + +#if defined(LINUX_VERSION_CODE) +EXPORT_SYMBOL(fsl_shw_add_entropy); +#endif +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + + /* Unused */ + (void)user_ctx; + (void)length; + (void)data; + + return FSL_RETURN_ERROR_S; +} +#endif + +#if !defined(FSL_HAVE_DRYICE) && !defined(FSL_HAVE_SAHARA2) +#if 0 +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_symmetric_decrypt); +#endif +fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, uint8_t * pt) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)sym_ctx; + (void)length; + (void)ct; + (void)pt; + + return FSL_RETURN_ERROR_S; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_symmetric_encrypt); +#endif +fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, uint8_t * ct) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)sym_ctx; + (void)length; + (void)pt; + (void)ct; + + return FSL_RETURN_ERROR_S; +} + +/* DryIce support provided in separate file */ + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_establish_key); +#endif +fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)establish_type; + (void)key; + + return FSL_RETURN_ERROR_S; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_extract_key); +#endif +fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)covered_key; + + return FSL_RETURN_ERROR_S; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_release_key); +#endif +fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + + /* Unused */ + (void)user_ctx; + (void)key_info; + + return FSL_RETURN_ERROR_S; +} +#endif +#endif /* SAHARA or DRYICE */ + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_hash); +#endif +#if !defined(FSL_HAVE_SAHARA) +fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)hash_ctx; + (void)msg; + (void)length; + (void)result; + (void)result_len; + + return ret; +} +#endif + +#ifndef FSL_HAVE_SAHARA +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_hmac_precompute); +#endif + +fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx) +{ + fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)hmac_ctx; + + return status; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_hmac); +#endif + +fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)key_info; + (void)hmac_ctx; + (void)msg; + (void)length; + (void)result; + (void)result_len; + + return status; +} +#endif + +/*! + * Call the proper function to encrypt a region of encrypted secure memory + * + * @brief + * + * @param user_ctx User context of the partition owner (NULL in kernel) + * @param partition_base Base address (physical) of the partition + * @param offset_bytes Offset from base address of the data to be encrypted + * @param byte_count Length of the message (bytes) + * @param black_data Pointer to where the encrypted data is stored + * @param IV IV to use for encryption + * @param cypher_mode Cyphering mode to use, specified by type + * #fsl_shw_cypher_mode_t + * + * @return status + */ +fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode) +{ + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; +#ifdef FSL_HAVE_SCC2 + + scc_return_t scc_ret; + +#ifdef SHW_DEBUG + uint32_t *owner_32 = (uint32_t *) & (owner_id); + + LOG_KDIAG_ARGS + ("partition base: %p, offset: %i, count: %i, black data: %p\n", + partition_base, offset_bytes, byte_count, (void *)black_data); + + LOG_KDIAG_ARGS("Owner ID: %08x%08x\n", owner_32[1], owner_32[0]); +#endif /* SHW_DEBUG */ + (void)user_ctx; + + os_cache_flush_range(black_data, byte_count); + + scc_ret = + scc_encrypt_region((uint32_t) partition_base, offset_bytes, + byte_count, __virt_to_phys(black_data), IV, + cypher_mode); + + if (scc_ret == SCC_RET_OK) { + retval = FSL_RETURN_OK_S; + } else { + retval = FSL_RETURN_ERROR_S; + } + + /* The SCC2 DMA engine should have written to the black ram, so we need to + * invalidate that region of memory. Note that the red ram is not an + * because it is mapped with the cache disabled. + */ + os_cache_inv_range(black_data, byte_count); + +#endif /* FSL_HAVE_SCC2 */ + return retval; +} + +/*! + * Call the proper function to decrypt a region of encrypted secure memory + * + * @brief + * + * @param user_ctx User context of the partition owner (NULL in kernel) + * @param partition_base Base address (physical) of the partition + * @param offset_bytes Offset from base address that the decrypted data + * shall be placed + * @param byte_count Length of the message (bytes) + * @param black_data Pointer to where the encrypted data is stored + * @param IV IV to use for decryption + * @param cypher_mode Cyphering mode to use, specified by type + * #fsl_shw_cypher_mode_t + * + * @return status + */ +fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode) +{ + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + +#ifdef FSL_HAVE_SCC2 + + scc_return_t scc_ret; + +#ifdef SHW_DEBUG + uint32_t *owner_32 = (uint32_t *) & (owner_id); + + LOG_KDIAG_ARGS + ("partition base: %p, offset: %i, count: %i, black data: %p\n", + partition_base, offset_bytes, byte_count, (void *)black_data); + + LOG_KDIAG_ARGS("Owner ID: %08x%08x\n", owner_32[1], owner_32[0]); +#endif /* SHW_DEBUG */ + + (void)user_ctx; + + /* The SCC2 DMA engine will be reading from the black ram, so we need to + * make sure that the data is pushed out of the cache. Note that the red + * ram is not an issue because it is mapped with the cache disabled. + */ + os_cache_flush_range(black_data, byte_count); + + scc_ret = + scc_decrypt_region((uint32_t) partition_base, offset_bytes, + byte_count, + (uint8_t *) __virt_to_phys(black_data), IV, + cypher_mode); + + if (scc_ret == SCC_RET_OK) { + retval = FSL_RETURN_OK_S; + } else { + retval = FSL_RETURN_ERROR_S; + } + +#endif /* FSL_HAVE_SCC2 */ + + return retval; +} + +void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx, + uint32_t size, const uint8_t * UMID, uint32_t permissions) +{ +#ifdef FSL_HAVE_SCC2 + int part_no; + void *part_base; + uint32_t part_phys; + scc_config_t *scc_configuration; + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (size != scc_configuration->partition_size_bytes) { + return NULL; + } + + /* attempt to grab a partition. */ + if (scc_allocate_partition(0, &part_no, &part_base, &part_phys) + != SCC_RET_OK) { + return NULL; + } +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("Partition_base: %p, partition_base_phys: %p\n", + part_base, (void *)part_phys); +#endif + + if (scc_engage_partition(part_base, UMID, permissions) + != SCC_RET_OK) { + /* Engagement failed, so the partition needs to be de-allocated */ + +#ifdef SHW_DEBUG + LOG_KDIAG_ARGS("Failed to engage partition %p, de-allocating", + part_base); +#endif + scc_release_partition(part_base); + + return NULL; + } + + return part_base; + +#else /* FSL_HAVE_SCC2 */ + + (void)user_ctx; + (void)size; + (void)UMID; + (void)permissions; + return NULL; + +#endif /* FSL_HAVE_SCC2 */ +} + +/* Release a block of secure memory */ +fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address) +{ + (void)user_ctx; + +#ifdef FSL_HAVE_SCC2 + if (scc_release_partition(address) == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } +#endif + + return FSL_RETURN_ERROR_S; +} + +/* Check the status of a block of secure memory */ +fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx, + void *address, + fsl_shw_partition_status_t * part_status) +{ + (void)user_ctx; + +#ifdef FSL_HAVE_SCC2 + *part_status = scc_partition_status(address); + + return FSL_RETURN_OK_S; +#endif + + return FSL_RETURN_ERROR_S; +} + +/* Diminish permissions on some secure memory */ +fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx, + void *address, uint32_t permissions) +{ + + (void)user_ctx; /* unused parameter warning */ + +#ifdef FSL_HAVE_SCC2 + if (scc_diminish_permissions(address, permissions) == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } +#endif + return FSL_RETURN_ERROR_S; +} + +#ifndef FSL_HAVE_SAHARA +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_gen_encrypt); +#endif + +fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value) +{ + volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)auth_ctx; + (void)cipher_key_info; + (void)auth_key_info; /* save compilation warning */ + (void)auth_data_length; + (void)auth_data; + (void)payload_length; + (void)payload; + (void)ct; + (void)auth_value; + + return status; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_auth_decrypt); +#endif +/*! + * @brief Authenticate and decrypt a (CCM) stream. + * + * @param user_ctx The user's context + * @param auth_ctx Info on this Auth operation + * @param cipher_key_info Key to encrypt payload + * @param auth_key_info (unused - same key in CCM) + * @param auth_data_length Length in bytes of @a auth_data + * @param auth_data Any auth-only data + * @param payload_length Length in bytes of @a payload + * @param ct The encrypted data + * @param auth_value The authentication code to validate + * @param[out] payload The location to store decrypted data + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * ct, + const uint8_t * auth_value, + uint8_t * payload) +{ + volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + /* Unused */ + (void)user_ctx; + (void)auth_ctx; + (void)cipher_key_info; + (void)auth_key_info; /* save compilation warning */ + (void)auth_data_length; + (void)auth_data; + (void)payload_length; + (void)ct; + (void)auth_value; + (void)payload; + + return status; +} + +#endif /* no SAHARA */ + +#ifndef FSL_HAVE_DRYICE + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_gen_random_pf_key); +#endif +/*! + * Cause the hardware to create a new random key for secure memory use. + * + * Have the hardware use the secure hardware random number generator to load a + * new secret key into the hardware random key register. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx) +{ + volatile fsl_shw_return_t status = FSL_RETURN_ERROR_S; + + return status; +} + +#endif /* not have DRYICE */ + +fsl_shw_return_t alloc_slot(fsl_shw_uco_t * user_ctx, fsl_shw_sko_t * key_info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_alloc(user_ctx, + key_info->key_length, + key_info->userid, + &(key_info->handle)); +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("key length: %i, handle: %i", + key_info->key_length, key_info->handle); +#endif + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_alloc(key_info->keystore, + key_info->key_length, + key_info->userid, + &(key_info->handle)); + } + + return ret; +} /* end fn alloc_slot */ + +fsl_shw_return_t load_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, const uint8_t * key) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_load(user_ctx, + key_info->userid, + key_info->handle, key, + key_info->key_length); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_load(key_info->keystore, + key_info->userid, + key_info->handle, key, + key_info->key_length); + } + + return ret; +} /* end fn load_slot */ + +fsl_shw_return_t dealloc_slot(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + key_info->handle); + } else { + /* Key goes in user keystore */ + keystore_slot_dealloc(key_info->keystore, + key_info->userid, key_info->handle); + } + + key_info->flags &= ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT); + + return ret; +} /* end fn slot_dealloc */ diff --git a/drivers/mxc/security/rng/shw_dryice.c b/drivers/mxc/security/rng/shw_dryice.c new file mode 100644 index 000000000000..bcf1794f7351 --- /dev/null +++ b/drivers/mxc/security/rng/shw_dryice.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "shw_driver.h" +#include "../dryice.h" + +#include + +#ifdef FSL_HAVE_DRYICE + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_gen_random_pf_key); +#endif +/*! + * Cause the hardware to create a new random key for secure memory use. + * + * Have the hardware use the secure hardware random number generator to load a + * new secret key into the hardware random key register. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + di_return_t di_ret; + + /* For now, only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + di_ret = dryice_set_random_key(0); + if (di_ret != DI_SUCCESS) { + printk("dryice_set_random_key returned %d\n", di_ret); + goto out; + } + + ret = FSL_RETURN_OK_S; + + out: + return ret; +} + +#ifdef LINUX_VERSION_CODE +EXPORT_SYMBOL(fsl_shw_read_tamper_event); +#endif +fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx, + fsl_shw_tamper_t * tamperp, + uint64_t * timestampp) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + di_return_t di_ret; + uint32_t di_events = 0; + uint32_t di_time_stamp; + + /* Only blocking mode calls are supported */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + di_ret = dryice_get_tamper_event(&di_events, &di_time_stamp, 0); + if ((di_ret != DI_SUCCESS) && (di_ret != DI_ERR_STATE)) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("dryice_get_tamper_event returned %s\n", + di_error_string(di_ret)); +#endif + goto out; + } + + /* Pass time back to caller */ + *timestampp = (uint64_t) di_time_stamp; + + if (di_events & DI_TAMPER_EVENT_WTD) { + *tamperp = FSL_SHW_TAMPER_WTD; + } else if (di_events & DI_TAMPER_EVENT_ETBD) { + *tamperp = FSL_SHW_TAMPER_ETBD; + } else if (di_events & DI_TAMPER_EVENT_ETAD) { + *tamperp = FSL_SHW_TAMPER_ETAD; + } else if (di_events & DI_TAMPER_EVENT_EBD) { + *tamperp = FSL_SHW_TAMPER_EBD; + } else if (di_events & DI_TAMPER_EVENT_SAD) { + *tamperp = FSL_SHW_TAMPER_SAD; + } else if (di_events & DI_TAMPER_EVENT_TTD) { + *tamperp = FSL_SHW_TAMPER_TTD; + } else if (di_events & DI_TAMPER_EVENT_CTD) { + *tamperp = FSL_SHW_TAMPER_CTD; + } else if (di_events & DI_TAMPER_EVENT_VTD) { + *tamperp = FSL_SHW_TAMPER_VTD; + } else if (di_events & DI_TAMPER_EVENT_MCO) { + *tamperp = FSL_SHW_TAMPER_MCO; + } else if (di_events & DI_TAMPER_EVENT_TCO) { + *tamperp = FSL_SHW_TAMPER_TCO; + } else if (di_events != 0) { + /* Apparentliy a tamper type not known to this driver was detected */ + goto out; + } else { + *tamperp = FSL_SHW_TAMPER_NONE; + } + + ret = FSL_RETURN_OK_S; + + out: + return ret; +} /* end fn fsl_shw_read_tamper_event */ +#endif +/*! + * Convert an SHW HW key reference into a DI driver key reference + * + * @param shw_pf_key An SHW HW key value + * @param di_keyp Location to store the equivalent DI driver key + * + * @return FSL_RETURN_OK_S, or error if key is unknown or cannot translate. + */ +fsl_shw_return_t shw_convert_pf_key(fsl_shw_pf_key_t shw_pf_key, + di_key_t * di_keyp) +{ + fsl_shw_return_t ret = FSL_RETURN_BAD_FLAG_S; + + switch (shw_pf_key) { + case FSL_SHW_PF_KEY_IIM: + *di_keyp = DI_KEY_FK; + break; + case FSL_SHW_PF_KEY_RND: + *di_keyp = DI_KEY_RK; + break; + case FSL_SHW_PF_KEY_IIM_RND: + *di_keyp = DI_KEY_FRK; + break; + case FSL_SHW_PF_KEY_PRG: + *di_keyp = DI_KEY_PK; + break; + case FSL_SHW_PF_KEY_IIM_PRG: + *di_keyp = DI_KEY_FPK; + break; + default: + goto out; + } + + ret = FSL_RETURN_OK_S; + + out: + return ret; +} + +#ifdef DIAG_SECURITY_FUNC +const char *di_error_string(int code) +{ + char *str = "unknown"; + + switch (code) { + case DI_SUCCESS: + str = "operation was successful"; + break; + case DI_ERR_BUSY: + str = "device or resource busy"; + break; + case DI_ERR_STATE: + str = "dryice is in incompatible state"; + break; + case DI_ERR_INUSE: + str = "resource is already in use"; + break; + case DI_ERR_UNSET: + str = "resource has not been initialized"; + break; + case DI_ERR_WRITE: + str = "error occurred during register write"; + break; + case DI_ERR_INVAL: + str = "invalid argument"; + break; + case DI_ERR_FAIL: + str = "operation failed"; + break; + case DI_ERR_HLOCK: + str = "resource is hard locked"; + break; + case DI_ERR_SLOCK: + str = "resource is soft locked"; + break; + case DI_ERR_NOMEM: + str = "out of memory"; + break; + default: + break; + } + + return str; +} +#endif /* HAVE DRYICE */ diff --git a/drivers/mxc/security/rng/shw_hash.c b/drivers/mxc/security/rng/shw_hash.c new file mode 100644 index 000000000000..3aac05235bfa --- /dev/null +++ b/drivers/mxc/security/rng/shw_hash.c @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file shw_hash.c + * + * This file contains implementations for use of the (internal) SHW hash + * software computation. It defines the usual three steps: + * + * - #shw_hash_init() + * - #shw_hash_update() + * - #shw_hash_final() + * + * In support of the above functions, it also contains these functions: + * - #sha256_init() + * - #sha256_process_block() + * + * + * These functions depend upon the Linux Endian functions __be32_to_cpu(), + * __cpu_to_be32() to convert a 4-byte big-endian array to an integer and + * vice-versa. For those without Linux, it should be pretty obvious what they + * do. + * + * The #shw_hash_update() and #shw_hash_final() functions are generic enough to + * support SHA-1/SHA-224/SHA-256, as needed. Some extra tweaking would be + * necessary to get them to support SHA-384/SHA-512. + * + */ + +#include "shw_driver.h" +#include "shw_hash.h" + +#ifndef __KERNEL__ +#include +#include /* or whichever is proper for target arch */ +#define printk printf +#endif + +/*! + * Rotate a value right by a number of bits. + * + * @param x Word of data which needs rotating + * @param y Number of bits to rotate + * + * @return The new value + */ +inline uint32_t rotr32fixed(uint32_t x, unsigned int y) +{ + return (uint32_t) ((x >> y) | (x << (32 - y))); +} + +#define blk0(i) (W[i] = data[i]) +// Referencing parameters so many times is really poor practice. Do not imitate these macros +#define blk2(i) (W[i & 15] += s1(W[(i - 2) & 15]) + W[(i - 7) & 15] + s0(W[(i - 15) & 15])) + +#define Ch(x,y,z) (z ^ (x & (y ^ z))) +#define Maj(x,y,z) ((x & y) | (z & (x | y))) + +#define a(i) T[(0 - i) & 7] +#define b(i) T[(1 - i) & 7] +#define c(i) T[(2 - i) & 7] +#define d(i) T[(3 - i) & 7] +#define e(i) T[(4 - i) & 7] +#define f(i) T[(5 - i) & 7] +#define g(i) T[(6 - i) & 7] +#define h(i) T[(7 - i) & 7] + +// This is a bad way to write a multi-statement macro... and referencing 'i' so many +// times is really poor practice. Do not imitate. +#define R(i) h(i) += S1( e(i)) + Ch(e(i), f(i), g(i)) + K[i + j] +(j ? blk2(i) : blk0(i));\ + d(i) += h(i);h(i) += S0(a(i)) + Maj(a(i), b(i), c(i)) + +// for SHA256 +#define S0(x) (rotr32fixed(x, 2) ^ rotr32fixed(x, 13) ^ rotr32fixed(x, 22)) +#define S1(x) (rotr32fixed(x, 6) ^ rotr32fixed(x, 11) ^ rotr32fixed(x, 25)) +#define s0(x) (rotr32fixed(x, 7) ^ rotr32fixed(x, 18) ^ (x >> 3)) +#define s1(x) (rotr32fixed(x, 17) ^ rotr32fixed(x, 19) ^ (x >> 10)) + +/*! + * Initialize the Hash State + * + * Constructs the SHA256 hash engine. + * Specification: + * State Size = 32 bytes + * Block Size = 64 bytes + * Digest Size = 32 bytes + * + * @param state Address of hash state structure + * + */ +void sha256_init(shw_hash_state_t * state) +{ + state->bit_count = 0; + state->partial_count_bytes = 0; + + state->state[0] = 0x6a09e667; + state->state[1] = 0xbb67ae85; + state->state[2] = 0x3c6ef372; + state->state[3] = 0xa54ff53a; + state->state[4] = 0x510e527f; + state->state[5] = 0x9b05688c; + state->state[6] = 0x1f83d9ab; + state->state[7] = 0x5be0cd19; +} + +const uint32_t K[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, + 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, + 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, + 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, + 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, + 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, + 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, + 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, + 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, + 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, + 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, + 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, + 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, + 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 +}; + +/*! + * Hash a block of data into the SHA-256 hash state. + * + * This function hash the block of data in the @c partial_block + * element of the state structure into the state variables of the + * state structure. + * + * @param state Address of hash state structure + * + */ +static void sha256_process_block(shw_hash_state_t * state) +{ + uint32_t W[16]; + uint32_t T[8]; + uint32_t stack_buffer[SHW_HASH_BLOCK_WORD_SIZE]; + uint32_t *data = &stack_buffer[0]; + uint8_t *input = state->partial_block; + unsigned int i; + unsigned int j; + + /* Copy byte-oriented input block into word-oriented registers */ + for (i = 0; i < SHW_HASH_BLOCK_LEN / sizeof(uint32_t); + i++, input += sizeof(uint32_t)) { + stack_buffer[i] = __be32_to_cpu(*(uint32_t *) input); + } + + /* Copy context->state[] to working vars */ + memcpy(T, state->state, sizeof(T)); + + /* 64 operations, partially loop unrolled */ + for (j = 0; j < SHW_HASH_BLOCK_LEN; j += 16) { + R(0); + R(1); + R(2); + R(3); + R(4); + R(5); + R(6); + R(7); + R(8); + R(9); + R(10); + R(11); + R(12); + R(13); + R(14); + R(15); + } + /* Add the working vars back into context.state[] */ + state->state[0] += a(0); + state->state[1] += b(0); + state->state[2] += c(0); + state->state[3] += d(0); + state->state[4] += e(0); + state->state[5] += f(0); + state->state[6] += g(0); + state->state[7] += h(0); + + /* Wipe variables */ + memset(W, 0, sizeof(W)); + memset(T, 0, sizeof(T)); +} + +/*! + * Initialize the hash state structure + * + * @param state Address of hash state structure. + * @param alg Which hash algorithm to use (must be FSL_HASH_ALG_SHA1) + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hash_init(shw_hash_state_t * state, fsl_shw_hash_alg_t alg) +{ + if (alg != FSL_HASH_ALG_SHA256) { + return FSL_RETURN_BAD_ALGORITHM_S; + } + + sha256_init(state); + + return FSL_RETURN_OK_S; +} + +/*! + * Add input bytes to the hash + * + * The bytes are added to the partial_block element of the hash state, and as + * the partial block is filled, it is processed by sha1_process_block(). This + * function also updates the bit_count element of the hash state. + * + * @param state Address of hash state structure + * @param input Address of bytes to add to the hash + * @param input_len Numbef of bytes at @c input + * + */ +fsl_shw_return_t shw_hash_update(shw_hash_state_t * state, + const uint8_t * input, unsigned int input_len) +{ + unsigned int bytes_needed; /* Needed to fill a block */ + unsigned int bytes_to_copy; /* to copy into the block */ + + /* Account for new data */ + state->bit_count += 8 * input_len; + + /* + * Process input bytes into the ongoing block; process the block when it + * gets full. + */ + while (input_len > 0) { + bytes_needed = SHW_HASH_BLOCK_LEN - state->partial_count_bytes; + bytes_to_copy = ((input_len < bytes_needed) ? + input_len : bytes_needed); + + /* Add in the bytes and do the accounting */ + memcpy(state->partial_block + state->partial_count_bytes, + input, bytes_to_copy); + input += bytes_to_copy; + input_len -= bytes_to_copy; + state->partial_count_bytes += bytes_to_copy; + + /* Run a full block through the transform */ + if (state->partial_count_bytes == SHW_HASH_BLOCK_LEN) { + sha256_process_block(state); + state->partial_count_bytes = 0; + } + } + + return FSL_RETURN_OK_S; +} /* end fn shw_hash_update */ + +/*! + * Finalize the hash + * + * Performs the finalize operation on the previous input data & returns the + * resulting digest. The finalize operation performs the appropriate padding + * up to the block size. + * + * @param state Address of hash state structure + * @param result Location to store the hash result + * @param result_len Number of bytes of @c result to be stored. + * + * @return FSL_RETURN_OK_S if all went well, FSL_RETURN_BAD_DATA_LENGTH_S if + * hash_len is too long, otherwise an error code. + */ +fsl_shw_return_t shw_hash_final(shw_hash_state_t * state, uint8_t * result, + unsigned int result_len) +{ + static const uint8_t pad[SHW_HASH_BLOCK_LEN * 2] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }; + + uint8_t data[sizeof(state->bit_count)]; + uint32_t pad_length; + uint64_t bit_count = state->bit_count; + uint8_t hash[SHW_HASH_LEN]; + int i; + + if (result_len > SHW_HASH_LEN) { + return FSL_RETURN_BAD_DATA_LENGTH_S; + } + + /* Save the length before padding. */ + for (i = sizeof(state->bit_count) - 1; i >= 0; i--) { + data[i] = bit_count & 0xFF; + bit_count >>= 8; + } + pad_length = ((state->partial_count_bytes < 56) ? + (56 - state->partial_count_bytes) : + (120 - state->partial_count_bytes)); + + /* Pad to 56 bytes mod 64 (BLOCK_SIZE). */ + shw_hash_update(state, pad, pad_length); + + /* + * Append the length. This should trigger transform of the final block. + */ + shw_hash_update(state, data, sizeof(state->bit_count)); + + /* Copy the result into a byte array */ + for (i = 0; i < SHW_HASH_STATE_WORDS; i++) { + *(uint32_t *) (hash + 4 * i) = __cpu_to_be32(state->state[i]); + } + + /* And copy the result out to caller */ + memcpy(result, hash, result_len); + + return FSL_RETURN_OK_S; +} /* end fn shw_hash_final */ diff --git a/drivers/mxc/security/rng/shw_hmac.c b/drivers/mxc/security/rng/shw_hmac.c new file mode 100644 index 000000000000..57c086405a49 --- /dev/null +++ b/drivers/mxc/security/rng/shw_hmac.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file shw_hmac.c + * + * This file contains implementations for use of the (internal) SHW HMAC + * software computation. It defines the usual three steps: + * + * - #shw_hmac_init() + * - #shw_hmac_update() + * - #shw_hmac_final() + * + * + */ + +#include "shw_driver.h" +#include "shw_hmac.h" + +#ifndef __KERNEL__ +#include +#include /* or whichever is proper for target arch */ +#define printk printf +#endif + +/*! XOR value for HMAC inner key */ +#define INNER_HASH_CONSTANT 0x36 + +/*! XOR value for HMAC outer key */ +#define OUTER_HASH_CONSTANT 0x5C + +/*! + * Initialize the HMAC state structure with the HMAC key + * + * @param state Address of HMAC state structure + * @param key Address of the key to be used for the HMAC. + * @param key_len Number of bytes of @c key. + * + * Convert the key into its equivalent inner and outer hash state objects. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_init(shw_hmac_state_t * state, + const uint8_t * key, unsigned int key_len) +{ + fsl_shw_return_t code = FSL_RETURN_ERROR_S; + uint8_t first_block[SHW_HASH_BLOCK_LEN]; + unsigned int i; + + /* Don't bother handling the pre-hash. */ + if (key_len > SHW_HASH_BLOCK_LEN) { + code = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } + + /* Prepare inner hash */ + for (i = 0; i < SHW_HASH_BLOCK_LEN; i++) { + if (i < key_len) { + first_block[i] = key[i] ^ INNER_HASH_CONSTANT; + } else { + first_block[i] = INNER_HASH_CONSTANT; + } + } + code = shw_hash_init(&state->inner_hash, FSL_HASH_ALG_SHA256); + if (code != FSL_RETURN_OK_S) { + goto out; + } + shw_hash_update(&state->inner_hash, first_block, SHW_HASH_BLOCK_LEN); + + /* Prepare outer hash */ + for (i = 0; i < SHW_HASH_BLOCK_LEN; i++) { + if (i < key_len) { + first_block[i] = key[i] ^ OUTER_HASH_CONSTANT; + } else { + first_block[i] = OUTER_HASH_CONSTANT; + } + } + code = shw_hash_init(&state->outer_hash, FSL_HASH_ALG_SHA256); + if (code != FSL_RETURN_OK_S) { + goto out; + } + shw_hash_update(&state->outer_hash, first_block, SHW_HASH_BLOCK_LEN); + + /* Wipe evidence of key */ + memset(first_block, 0, SHW_HASH_BLOCK_LEN); + + out: + return code; +} + +/*! + * Put data into the HMAC calculation + * + * Send the msg data inner inner hash's update function. + * + * @param state Address of HMAC state structure. + * @param msg Address of the message data for the HMAC. + * @param msg_len Number of bytes of @c msg. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_update(shw_hmac_state_t * state, + const uint8_t * msg, unsigned int msg_len) +{ + shw_hash_update(&state->inner_hash, msg, msg_len); + + return FSL_RETURN_OK_S; +} + +/*! + * Calculate the final HMAC + * + * @param state Address of HMAC state structure. + * @param hmac Address of location to store the HMAC. + * @param hmac_len Number of bytes of @c mac to be stored. Probably best if + * this value is no greater than #SHW_HASH_LEN. + * + * This function finalizes the internal hash, and uses that result as + * data for the outer hash. As many bytes of that result are passed + * to the user as desired. + * + * @return FSL_RETURN_OK_S if all went well, otherwise an error code. + */ +fsl_shw_return_t shw_hmac_final(shw_hmac_state_t * state, + uint8_t * hmac, unsigned int hmac_len) +{ + uint8_t hash_result[SHW_HASH_LEN]; + + shw_hash_final(&state->inner_hash, hash_result, sizeof(hash_result)); + shw_hash_update(&state->outer_hash, hash_result, SHW_HASH_LEN); + + shw_hash_final(&state->outer_hash, hmac, hmac_len); + + return FSL_RETURN_OK_S; +} diff --git a/drivers/mxc/security/rng/shw_memory_mapper.c b/drivers/mxc/security/rng/shw_memory_mapper.c new file mode 100644 index 000000000000..d7b82576a6cd --- /dev/null +++ b/drivers/mxc/security/rng/shw_memory_mapper.c @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + + +/** + * Memory management functions, from Sahara Crypto API + * + * This is a subset of the memory management functions from the Sahara Crypto + * API, and is intended to support user secure partitions. + */ + +#include "portable_os.h" +#include "fsl_shw.h" + +#include +#include +#include + +#ifdef SHW_DEBUG +#include +#endif + +/* Page context structure. Used by wire_user_memory and unwire_user_memory */ +typedef struct page_ctx_t { + uint32_t count; + struct page **local_pages; +} page_ctx_t; + +/** +******************************************************************************* +* Map and wire down a region of user memory. +* +* +* @param address Userspace address of the memory to wire +* @param length Length of the memory region to wire +* @param page_ctx Page context, to be passed to unwire_user_memory +* +* @return (if successful) Kernel virtual address of the wired pages +*/ +void* wire_user_memory(void* address, uint32_t length, void **page_ctx) +{ + void* kernel_black_addr = NULL; + int result = -1; + int page_index = 0; + page_ctx_t *page_context; + int nr_pages = 0; + unsigned long start_page; + fsl_shw_return_t status; + + /* Determine the number of pages being used for this link */ + nr_pages = (((unsigned long)(address) & ~PAGE_MASK) + + length + ~PAGE_MASK) >> PAGE_SHIFT; + + start_page = (unsigned long)(address) & PAGE_MASK; + + /* Allocate some memory to keep track of the wired user pages, so that + * they can be deallocated later. The block of memory will contain both + * the structure and the array of pages. + */ + page_context = kmalloc(sizeof(page_ctx_t) + + nr_pages * sizeof(struct page *), GFP_KERNEL); + + if (page_context == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; /* no memory! */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("kmalloc() failed."); +#endif + return NULL; + } + + /* Set the page pointer to point to the allocated region of memory */ + page_context->local_pages = (void*)page_context + sizeof(page_ctx_t); + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("page_context at: %p, local_pages at: %p", + (void *)page_context, + (void *)(page_context->local_pages)); +#endif + + /* Wire down the pages from user space */ + down_read(¤t->mm->mmap_sem); + result = get_user_pages(current, current->mm, + start_page, nr_pages, + WRITE, 0 /* noforce */, + (page_context->local_pages), NULL); + up_read(¤t->mm->mmap_sem); + + if (result < nr_pages) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("get_user_pages() failed."); +#endif + if (result > 0) { + for (page_index = 0; page_index < result; page_index++) + page_cache_release((page_context->local_pages[page_index])); + + kfree(page_context); + } + return NULL; + } + + kernel_black_addr = page_address(page_context->local_pages[0]) + + ((unsigned long)address & ~PAGE_MASK); + + page_context->count = nr_pages; + *page_ctx = page_context; + + return kernel_black_addr; +} + + +/** +******************************************************************************* +* Release and unmap a region of user memory. +* +* @param page_ctx Page context from wire_user_memory +*/ +void unwire_user_memory(void** page_ctx) +{ + int page_index = 0; + struct page_ctx_t *page_context = *page_ctx; + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("page_context at: %p, first page at:%p, count: %i", + (void *)page_context, + (void *)(page_context->local_pages), + page_context->count); +#endif + + if ((page_context != NULL) && (page_context->local_pages != NULL)) { + for (page_index = 0; page_index < page_context->count; page_index++) + page_cache_release(page_context->local_pages[page_index]); + + kfree(page_context); + *page_ctx = NULL; + } +} + + +/** +******************************************************************************* +* Map some physical memory into a users memory space +* +* @param vma Memory structure to map to +* @param physical_addr Physical address of the memory to be mapped in +* @param size Size of the memory to map (bytes) +* +* @return +*/ +os_error_code +map_user_memory(struct vm_area_struct *vma, uint32_t physical_addr, uint32_t size) +{ + os_error_code retval; + + /* Map the acquired partition into the user's memory space */ + vma->vm_end = vma->vm_start + size; + + /* set cache policy to uncached so that each write of the UMID and + * permissions get directly to the SCC2 in order to engage it + * properly. Once the permissions have been written, it may be + * useful to provide a service for the user to request a different + * cache policy + */ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Make sure that the user cannot fork() a child which will inherit + * this mapping, as it creates a security hole. Likewise, do not + * allow the user to 'expand' his mapping beyond this partition. + */ + vma->vm_flags |= VM_IO | VM_RESERVED | VM_DONTCOPY | VM_DONTEXPAND; + + retval = remap_pfn_range(vma, + vma->vm_start, + __phys_to_pfn(physical_addr), + size, + vma->vm_page_prot); + + return retval; +} + + +/** +******************************************************************************* +* Remove some memory from a user's memory space +* +* @param user_addr Userspace address of the memory to be unmapped +* @param size Size of the memory to map (bytes) +* +* @return +*/ +os_error_code +unmap_user_memory(uint32_t user_addr, uint32_t size) +{ + os_error_code retval; + struct mm_struct *mm = current->mm; + + /* Unmap the memory region (see sys_munmap in mmap.c) */ + down_write(&mm->mmap_sem); + retval = do_munmap(mm, (unsigned long)user_addr, size); + up_write(&mm->mmap_sem); + + return retval; +} diff --git a/drivers/mxc/security/sahara2/Kconfig b/drivers/mxc/security/sahara2/Kconfig new file mode 100644 index 000000000000..ab4e6fdc2cfc --- /dev/null +++ b/drivers/mxc/security/sahara2/Kconfig @@ -0,0 +1,35 @@ +menu "SAHARA2 Security Hardware Support" + +config MXC_SAHARA + tristate "Security Hardware Support (FSL SHW)" + ---help--- + Provides driver and kernel mode API for using cryptographic + accelerators. + +config MXC_SAHARA_USER_MODE + tristate "User Mode API for FSL SHW" + depends on MXC_SAHARA + ---help--- + Provides kernel driver for User Mode API. + +config MXC_SAHARA_POLL_MODE + bool "Force driver to POLL for hardware completion." + depends on MXC_SAHARA + default n + ---help--- + When this flag is yes, the driver will not use interrupts to + determine when the hardware has completed a task, but instead + will hold onto the CPU and continually poll the hardware until + it completes. + +config MXC_SAHARA_POLL_MODE_TIMEOUT + hex "Poll loop timeout" + depends on MXC_SAHARA_POLL_MODE + default "0xFFFFFFFF" + help + To avoid infinite polling, a timeout is provided. Should the + timeout be reached, a fault is reported, indicating there must + be something wrong with SAHARA, and SAHARA is reset. The loop + will exit after the given number of iterations. + +endmenu diff --git a/drivers/mxc/security/sahara2/Makefile b/drivers/mxc/security/sahara2/Makefile new file mode 100644 index 000000000000..b515709be29b --- /dev/null +++ b/drivers/mxc/security/sahara2/Makefile @@ -0,0 +1,47 @@ +# Makefile for the Linux Sahara2 driver +# +# This makefile works within a kernel driver tree + +# Need to augment this to support optionally building user-mode support +API_SOURCES = fsl_shw_sym.c fsl_shw_user.c fsl_shw_hash.c fsl_shw_auth.c \ + fsl_shw_hmac.c fsl_shw_rand.c sf_util.c km_adaptor.c fsl_shw_keystore.c \ + fsl_shw_wrap.c \ + + +SOURCES = sah_driver_interface.c sah_hardware_interface.c \ + sah_interrupt_handler.c sah_queue.c sah_queue_manager.c \ + sah_status_manager.c sah_memory_mapper.c + + +# Turn on for mostly full debugging +# DIAGS = -DDIAG_DRV_STATUS -DDIAG_DRV_QUEUE -DDIAG_DRV_INTERRUPT -DDIAG_DRV_IF +# DIAGS += -DDIAG_DURING_INTERRUPT + +# Turn on for lint-type checking +#EXTRA_CFLAGS = -Wall -W -Wstrict-prototypes -Wmissing-prototypes +EXTRA_CFLAGS += -DLINUX_KERNEL $(DIAGS) + + +ifeq ($(CONFIG_MXC_SAHARA_POLL_MODE),y) +EXTRA_CFLAGS += -DSAHARA_POLL_MODE +EXTRA_CFLAGS += -DSAHARA_POLL_MODE_TIMEOUT=$(CONFIG_SAHARA_POLL_MODE_TIMEOUT) +endif + +ifeq ($(CONFIG_MXC_SAHARA_USER_MODE),y) +EXTRA_CFLAGS += -DSAHARA_USER_MODE +SOURCES += +endif + +ifeq ($(CONFIG_PM),y) +EXTRA_CFLAGS += -DSAHARA_POWER_MANAGMENT +endif + +EXTRA_CFLAGS += -Idrivers/mxc/security/sahara2/include + +# handle buggy BSP -- uncomment if these are undefined during build +#EXTRA_CFLAGS += -DSAHARA_BASE_ADDR=HAC_BASE_ADDR -DINT_SAHARA=INT_HAC_RTIC + + +obj-$(CONFIG_MXC_SAHARA) += sahara.o + +sahara-objs := $(SOURCES:.c=.o) $(API_SOURCES:.c=.o) diff --git a/drivers/mxc/security/sahara2/fsl_shw_auth.c b/drivers/mxc/security/sahara2/fsl_shw_auth.c new file mode 100644 index 000000000000..161feac8e52b --- /dev/null +++ b/drivers/mxc/security/sahara2/fsl_shw_auth.c @@ -0,0 +1,706 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file fsl_shw_auth.c + * + * This file contains the routines which do the combined encrypt+authentication + * functions. For now, only AES-CCM is supported. + */ + +#include "sahara.h" +#include "adaptor.h" +#include "sf_util.h" + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_gen_encrypt); +EXPORT_SYMBOL(fsl_shw_auth_decrypt); +#endif + + +/*! Size of buffer to repetively sink useless CBC output */ +#define CBC_BUF_LEN 4096 + +/*! + * Compute the size, in bytes, of the encoded auth length + * + * @param l The actual associated data length + * + * @return The encoded length + */ +#define COMPUTE_NIST_AUTH_LEN_SIZE(l) \ +({ \ + unsigned val; \ + uint32_t len = l; \ + if (len == 0) { \ + val = 0; \ + } else if (len < 65280) { \ + val = 2; \ + } else { /* cannot handle >= 2^32 */ \ + val = 6; \ + } \ + val; \ +}) + +/*! + * Store the encoded Auth Length into the Auth Data + * + * @param l The actual Auth Length + * @param p Location to store encoding (must be uint8_t*) + * + * @return void + */ +#define STORE_NIST_AUTH_LEN(l, p) \ +{ \ + register uint32_t L = l; \ + if ((uint32_t)(l) < 65280) { \ + (p)[1] = L & 0xff; \ + L >>= 8; \ + (p)[0] = L & 0xff; \ + } else { /* cannot handle >= 2^32 */ \ + int i; \ + for (i = 5; i > 1; i--) { \ + (p)[i] = L & 0xff; \ + L >>= 8; \ + } \ + (p)[1] = 0xfe; /* Markers */ \ + (p)[0] = 0xff; \ + } \ +} + +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN) \ + || defined (USE_S2_CCM_ENCRYPT_CHAIN) +/*! Buffer to repetively sink useless CBC output */ +static uint8_t cbc_buffer[CBC_BUF_LEN]; +#endif + +/*! + * Place to store useless output (while bumping CTR0 to CTR1, for instance. + * Must be maximum Symmetric block size + */ +static uint8_t garbage_output[16]; + +/*! + * Block of zeroes which is maximum Symmetric block size, used for + * initializing context register, etc. + */ +static uint8_t block_zeros[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/*! + * Append a descriptor chain which will compute CBC over the + * formatted associated data blocks. + * + * @param[in,out] link1 Where to append the new link + * @param[in,out] data_len Location of current/updated auth-only data length + * @param user_ctx Info for acquiring memory + * @param auth_ctx Location of block0 value + * @param auth_data Unformatted associated data + * @param auth_data_length Length in octets of @a auth_data + * @param[in,out] temp_buf Location of in-process data. + * + * @return A return code of type #fsl_shw_return_t. + */ +static inline fsl_shw_return_t process_assoc_from_nist_params(sah_Link ** link1, + uint32_t * + data_len, + fsl_shw_uco_t * + user_ctx, + fsl_shw_acco_t * + auth_ctx, + const uint8_t * + auth_data, + uint32_t + auth_data_length, + uint8_t ** + temp_buf) +{ + fsl_shw_return_t status; + uint32_t auth_size_length = + COMPUTE_NIST_AUTH_LEN_SIZE(auth_data_length); + uint32_t auth_pad_length = + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes - + (auth_data_length + + auth_size_length) % + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes; + + if (auth_pad_length == + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes) { + auth_pad_length = 0; + } + + /* Put in Block0 */ + status = sah_Create_Link(user_ctx->mem_util, link1, + auth_ctx->auth_info.CCM_ctx_info.context, + auth_ctx->auth_info.CCM_ctx_info. + block_size_bytes, SAH_USES_LINK_DATA); + + if (auth_data_length != 0) { + if (status == FSL_RETURN_OK_S) { + /* Add on length preamble to auth data */ + STORE_NIST_AUTH_LEN(auth_data_length, *temp_buf); + status = sah_Append_Link(user_ctx->mem_util, *link1, + *temp_buf, auth_size_length, + SAH_OWNS_LINK_DATA); + *temp_buf += auth_size_length; /* 2, 6, or 10 bytes */ + } + + if (status == FSL_RETURN_OK_S) { + /* Add in auth data */ + status = sah_Append_Link(user_ctx->mem_util, *link1, + (uint8_t *) auth_data, + auth_data_length, + SAH_USES_LINK_DATA); + } + + if ((status == FSL_RETURN_OK_S) && (auth_pad_length > 0)) { + status = sah_Append_Link(user_ctx->mem_util, *link1, + block_zeros, auth_pad_length, + SAH_USES_LINK_DATA); + } + } + /* ... if auth_data_length != 0 */ + *data_len = auth_ctx->auth_info.CCM_ctx_info.block_size_bytes + + auth_data_length + auth_size_length + auth_pad_length; + + return status; +} /* end fn process_assoc_from_nist_params */ + +/*! + * Add a Descriptor which will process with CBC the NIST preamble data + * + * @param desc_chain Current chain + * @param user_ctx User's context + * @param auth_ctx Inf + * @pararm encrypt 0 => decrypt, non-zero => encrypt + * @param auth_data Additional auth data for this call + * @param auth_data_length Length in bytes of @a auth_data + * + * @return A return code of type #fsl_shw_return_t. + */ +static inline fsl_shw_return_t add_assoc_preamble(sah_Head_Desc ** desc_chain, + fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + int encrypt, + const uint8_t * auth_data, + uint32_t auth_data_length) +{ + uint8_t *temp_buf; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + fsl_shw_return_t status = FSL_RETURN_OK_S; + uint32_t cbc_data_length = 0; + /* Assume AES */ + uint32_t header = SAH_HDR_SKHA_ENC_DEC; + uint32_t temp_buf_flag; + unsigned chain_s2 = 1; + +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN) + if (!encrypt) { + chain_s2 = 0; + } +#endif +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN) + if (encrypt) { + chain_s2 = 0; + } +#endif + /* Grab a block big enough for multiple uses so that only one allocate + * request needs to be made. + */ + temp_buf = + user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref, + 3 * + auth_ctx->auth_info.CCM_ctx_info. + block_size_bytes); + + if (temp_buf == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + + if (auth_ctx->flags & FSL_ACCO_NIST_CCM) { + status = process_assoc_from_nist_params(&link1, + &cbc_data_length, + user_ctx, + auth_ctx, + auth_data, + auth_data_length, + &temp_buf); + if (status != FSL_RETURN_OK_S) { + goto out; + } + /* temp_buf has been referenced (and incremented). Only 'own' it + * once, at its first value. Since the nist routine called above + * bumps it... + */ + temp_buf_flag = SAH_USES_LINK_DATA; + } else { /* if NIST */ + status = sah_Create_Link(user_ctx->mem_util, &link1, + (uint8_t *) auth_data, + auth_data_length, SAH_USES_LINK_DATA); + if (status != FSL_RETURN_OK_S) { + goto out; + } + /* for next/first use of temp_buf */ + temp_buf_flag = SAH_OWNS_LINK_DATA; + cbc_data_length = auth_data_length; + } /* else not NIST */ + +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_ENCRYPT_CHAIN) \ + || defined (USE_S2_CCM_DECRYPT_CHAIN) + + if (!chain_s2) { + header = SAH_HDR_SKHA_CBC_ICV + ^ sah_insert_skha_mode_cbc ^ sah_insert_skha_aux0 + ^ sah_insert_skha_encrypt; + } else { + /* + * Auth data links have been created. Now create link for the + * useless output of the CBC calculation. + */ + status = sah_Create_Link(user_ctx->mem_util, &link2, + temp_buf, + auth_ctx->auth_info.CCM_ctx_info. + block_size_bytes, + temp_buf_flag | SAH_OUTPUT_LINK); + if (status != FSL_RETURN_OK_S) { + goto out; + } + + temp_buf += auth_ctx->auth_info.CCM_ctx_info.block_size_bytes; + + cbc_data_length -= + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes; + if (cbc_data_length != 0) { + while ((status == FSL_RETURN_OK_S) + && (cbc_data_length != 0)) { + uint32_t linklen = + (cbc_data_length > + CBC_BUF_LEN) ? CBC_BUF_LEN : + cbc_data_length; + + status = + sah_Append_Link(user_ctx->mem_util, link2, + cbc_buffer, linklen, + SAH_USES_LINK_DATA | + SAH_OUTPUT_LINK); + if (status != FSL_RETURN_OK_S) { + goto out; + } + cbc_data_length -= linklen; + } + } + } +#else + header = SAH_HDR_SKHA_CBC_ICV + ^ sah_insert_skha_mode_cbc ^ sah_insert_skha_aux0 + ^ sah_insert_skha_encrypt; +#endif + /* Crank through auth data */ + status = sah_Append_Desc(user_ctx->mem_util, desc_chain, + header, link1, link2); + + out: + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(user_ctx->mem_util, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(user_ctx->mem_util, link2); + } + } + + (void)encrypt; + return status; +} /* add_assoc_preamble() */ + +#if SUPPORT_SSL +/*! + * Generate an SSL value + * + * @param user_ctx Info for acquiring memory + * @param auth_ctx Info for CTR0, size of MAC + * @param cipher_key_info + * @param auth_key_info + * @param auth_data_length + * @param auth_data + * @param payload_length + * @param payload + * @param ct + * @param auth_value + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t do_ssl_gen(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value) +{ + SAH_SF_DCLS; + uint8_t *ptr1 = NULL; + + /* Assume one-shot init-finalize... no precomputes */ + header = SAH_HDR_MDHA_SET_MODE_MD_KEY ^ + sah_insert_mdha_algorithm[auth_ctx->auth_info.hash_ctx_info. + algorithm] ^ sah_insert_mdha_init ^ + sah_insert_mdha_ssl ^ sah_insert_mdha_pdata ^ + sah_insert_mdha_mac_full; + + /* set up hmac */ + DESC_IN_KEY(header, 0, NULL, auth_key_info); + + /* This is wrong -- need to find 16 extra bytes of data from + * somewhere */ + DESC_IN_OUT(SAH_HDR_MDHA_HASH, payload_length, payload, 1, auth_value); + + /* set up encrypt */ + header = SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_mode[auth_ctx->cipher_ctx_info.mode] + ^ sah_insert_skha_encrypt + ^ sah_insert_skha_algorithm[cipher_key_info->algorithm]; + + /* Honor 'no key parity checking' for DES and TDES */ + if ((cipher_key_info->flags & FSL_SKO_KEY_IGNORE_PARITY) && + ((cipher_key_info->algorithm == FSL_KEY_ALG_DES) || + (cipher_key_info->algorithm == FSL_KEY_ALG_TDES))) { + header ^= sah_insert_skha_no_key_parity; + } + + if (auth_ctx->cipher_ctx_info.mode == FSL_SYM_MODE_CTR) { + header ^= + sah_insert_skha_modulus[auth_ctx->cipher_ctx_info. + modulus_exp]; + } + + if ((auth_ctx->cipher_ctx_info.mode == FSL_SYM_MODE_ECB) + || (auth_ctx->cipher_ctx_info.flags & FSL_SYM_CTX_INIT)) { + ptr1 = block_zeros; + } else { + ptr1 = auth_ctx->cipher_ctx_info.context; + } + + DESC_IN_KEY(header, auth_ctx->cipher_ctx_info.block_size_bytes, ptr1, + cipher_key_info); + + /* This is wrong -- need to find 16 extra bytes of data from + * somewhere... + */ + if (payload_length != 0) { + DESC_IN_OUT(SAH_HDR_SKHA_ENC_DEC, + payload_length, payload, payload_length, ct); + } + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + /* Eliminate compiler warnings until full implementation... */ + (void)auth_data; + (void)auth_data_length; + + return ret; +} /* do_ssl_gen() */ +#endif + +/*! + * @brief Generate a (CCM) auth code and encrypt the payload. + * + * This is a very complicated function. Seven (or eight) descriptors are + * required to perform a CCM calculation. + * + * First: Load CTR0 and key. + * + * Second: Run an octet of data through to bump to CTR1. (This could be + * done in software, but software will have to bump and later decrement - + * or copy and bump. + * + * Third: (in Virtio) Load a descriptor with data of zeros for CBC IV. + * + * Fourth: Run any (optional) "additional data" through the CBC-mode + * portion of the algorithm. + * + * Fifth: Run the payload through in CCM mode. + * + * Sixth: Extract the unencrypted MAC. + * + * Seventh: Load CTR0. + * + * Eighth: Encrypt the MAC. + * + * @param user_ctx The user's context + * @param auth_ctx Info on this Auth operation + * @param cipher_key_info Key to encrypt payload + * @param auth_key_info (unused - same key in CCM) + * @param auth_data_length Length in bytes of @a auth_data + * @param auth_data Any auth-only data + * @param payload_length Length in bytes of @a payload + * @param payload The data to encrypt + * @param[out] ct The location to store encrypted data + * @param[out] auth_value The location to store authentication code + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + if (auth_ctx->mode == FSL_ACC_MODE_SSL) { +#if SUPPORT_SSL + ret = do_ssl_gen(user_ctx, auth_ctx, cipher_key_info, + auth_key_info, auth_data_length, auth_data, + payload_length, payload, ct, auth_value); +#else + ret = FSL_RETURN_BAD_MODE_S; +#endif + goto out; + } + + if (auth_ctx->mode != FSL_ACC_MODE_CCM) { + ret = FSL_RETURN_BAD_MODE_S; + goto out; + } + + /* Only support INIT and FINALIZE flags right now. */ + if ((auth_ctx->flags & (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_LOAD | + FSL_ACCO_CTX_SAVE | FSL_ACCO_CTX_FINALIZE)) + != (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_FINALIZE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Load CTR0 and Key */ + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_mode_ctr + ^ sah_insert_skha_modulus_128 ^ sah_insert_skha_encrypt); + DESC_IN_KEY(header, + auth_ctx->cipher_ctx_info.block_size_bytes, + auth_ctx->cipher_ctx_info.context, cipher_key_info); + + /* Encrypt dummy data to bump to CTR1 */ + header = SAH_HDR_SKHA_ENC_DEC; + DESC_IN_OUT(header, auth_ctx->mac_length, garbage_output, + auth_ctx->mac_length, garbage_output); + +#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_ENCRYPT_CHAIN) +#ifndef NO_ZERO_IV_LOAD + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_encrypt ^ sah_insert_skha_mode_cbc); + DESC_IN_IN(header, + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes, + block_zeros, 0, NULL); +#endif +#endif + + ret = add_assoc_preamble(&desc_chain, user_ctx, + auth_ctx, 1, auth_data, auth_data_length); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Process the payload */ + header = (SAH_HDR_SKHA_SET_MODE_ENC_DEC + ^ sah_insert_skha_mode_ccm + ^ sah_insert_skha_modulus_128 ^ sah_insert_skha_encrypt); +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN) + header ^= sah_insert_skha_aux0; +#endif + if (payload_length != 0) { + DESC_IN_OUT(header, payload_length, payload, payload_length, + ct); + } else { + DESC_IN_OUT(header, 0, NULL, 0, NULL); + } /* if payload_length */ + +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_ENCRYPT_CHAIN) + /* Pull out the CBC-MAC value. */ + DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV, 0, NULL, + auth_ctx->mac_length, auth_value); +#else + /* Pull out the unencrypted CBC-MAC value. */ + DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV, + 0, NULL, auth_ctx->mac_length, auth_ctx->unencrypted_mac); + + /* Now load CTR0 in, and encrypt the MAC */ + header = SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_encrypt + ^ sah_insert_skha_mode_ctr ^ sah_insert_skha_modulus_128; + DESC_IN_IN(header, + auth_ctx->cipher_ctx_info.block_size_bytes, + auth_ctx->cipher_ctx_info.context, 0, NULL); + + header = SAH_HDR_SKHA_ENC_DEC; /* Desc. #4 SKHA Enc/Dec */ + DESC_IN_OUT(header, + auth_ctx->mac_length, auth_ctx->unencrypted_mac, + auth_ctx->mac_length, auth_value); +#endif + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + (void)auth_key_info; + return ret; +} /* fsl_shw_gen_encrypt() */ + +/*! + * @brief Authenticate and decrypt a (CCM) stream. + * + * @param user_ctx The user's context + * @param auth_ctx Info on this Auth operation + * @param cipher_key_info Key to encrypt payload + * @param auth_key_info (unused - same key in CCM) + * @param auth_data_length Length in bytes of @a auth_data + * @param auth_data Any auth-only data + * @param payload_length Length in bytes of @a payload + * @param ct The encrypted data + * @param auth_value The authentication code to validate + * @param[out] payload The location to store decrypted data + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * ct, + const uint8_t * auth_value, + uint8_t * payload) +{ + SAH_SF_DCLS; +#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_DECRYPT_CHAIN) + uint8_t *calced_auth = NULL; + unsigned blocking = user_ctx->flags & FSL_UCO_BLOCKING_MODE; +#endif + + SAH_SF_USER_CHECK(); + + /* Only support CCM */ + if (auth_ctx->mode != FSL_ACC_MODE_CCM) { + ret = FSL_RETURN_BAD_MODE_S; + goto out; + } + /* Only support INIT and FINALIZE flags right now. */ + if ((auth_ctx->flags & (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_LOAD | + FSL_ACCO_CTX_SAVE | FSL_ACCO_CTX_FINALIZE)) + != (FSL_ACCO_CTX_INIT | FSL_ACCO_CTX_FINALIZE)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Load CTR0 and Key */ + header = SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_mode_ctr ^ sah_insert_skha_modulus_128; +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN) + header ^= sah_insert_skha_aux0; +#endif + DESC_IN_KEY(header, + auth_ctx->cipher_ctx_info.block_size_bytes, + auth_ctx->cipher_ctx_info.context, cipher_key_info); + + /* Decrypt the MAC which the user passed in */ + header = SAH_HDR_SKHA_ENC_DEC; + DESC_IN_OUT(header, + auth_ctx->mac_length, auth_value, + auth_ctx->mac_length, auth_ctx->unencrypted_mac); + +#if defined(FSL_HAVE_SAHARA2) || defined(USE_S2_CCM_DECRYPT_CHAIN) +#ifndef NO_ZERO_IV_LOAD + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_encrypt ^ sah_insert_skha_mode_cbc); + DESC_IN_IN(header, + auth_ctx->auth_info.CCM_ctx_info.block_size_bytes, + block_zeros, 0, NULL); +#endif +#endif + + ret = add_assoc_preamble(&desc_chain, user_ctx, + auth_ctx, 0, auth_data, auth_data_length); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Process the payload */ + header = (SAH_HDR_SKHA_SET_MODE_ENC_DEC + ^ sah_insert_skha_mode_ccm ^ sah_insert_skha_modulus_128); +#if defined (FSL_HAVE_SAHARA4) && !defined (USE_S2_CCM_DECRYPT_CHAIN) + header ^= sah_insert_skha_aux0; +#endif + if (payload_length != 0) { + DESC_IN_OUT(header, payload_length, ct, payload_length, + payload); + } else { + DESC_IN_OUT(header, 0, NULL, 0, NULL); + } + +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN) + /* Now pull CBC context (unencrypted MAC) out for comparison. */ + /* Need to allocate a place for it, to handle non-blocking mode + * when this stack frame will disappear! + */ + calced_auth = DESC_TEMP_ALLOC(auth_ctx->mac_length); + header = SAH_HDR_SKHA_READ_CONTEXT_IV; + DESC_OUT_OUT(header, 0, NULL, auth_ctx->mac_length, calced_auth); + if (!blocking) { + /* get_results will need this for comparison */ + desc_chain->out1_ptr = calced_auth; + desc_chain->out2_ptr = auth_ctx->unencrypted_mac; + desc_chain->out_len = auth_ctx->mac_length; + } +#endif + + SAH_SF_EXECUTE(); + +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN) + if (blocking && (ret == FSL_RETURN_OK_S)) { + unsigned i; + /* Validate the auth code */ + for (i = 0; i < auth_ctx->mac_length; i++) { + if (calced_auth[i] != auth_ctx->unencrypted_mac[i]) { + ret = FSL_RETURN_AUTH_FAILED_S; + break; + } + } + } +#endif + + out: + SAH_SF_DESC_CLEAN(); +#if defined (FSL_HAVE_SAHARA2) || defined (USE_S2_CCM_DECRYPT_CHAIN) + DESC_TEMP_FREE(calced_auth); +#endif + + (void)auth_key_info; + return ret; +} /* fsl_shw_gen_decrypt() */ diff --git a/drivers/mxc/security/sahara2/fsl_shw_hash.c b/drivers/mxc/security/sahara2/fsl_shw_hash.c new file mode 100644 index 000000000000..7d4db53480f6 --- /dev/null +++ b/drivers/mxc/security/sahara2/fsl_shw_hash.c @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_hash.c + * + * This file implements Cryptographic Hashing functions of the FSL SHW API + * for Sahara. This does not include HMAC. + */ + +#include "sahara.h" +#include "sf_util.h" + +#ifdef LINUX_KERNEL +EXPORT_SYMBOL(fsl_shw_hash); +#endif + +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */ +/*! + * Hash a stream of data with a cryptographic hash algorithm. + * + * The flags in the @a hash_ctx control the operation of this function. + * + * Hashing functions work on 64 octets of message at a time. Therefore, when + * any partial hashing of a long message is performed, the message @a length of + * each segment must be a multiple of 64. When ready to + * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value. + * + * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a + * one-shot complete hash, including padding, will be performed. The @a length + * may be any value. + * + * The first octets of a data stream can be hashed by setting the + * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags. The @a length must be + * a multiple of 64. + * + * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by + * #FSL_HASH_FLAGS_SAVE. The two in combination will allow a (multiple-of-64 + * octets) 'middle sequence' of the data stream to be hashed with the + * beginning. The @a length must again be a multiple of 64. + * + * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously + * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and + * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the + * stream. The @a length may be any value. + * + * If the user program wants to do the padding for the hash, it can leave off + * the #FSL_HASH_FLAGS_FINALIZE flag. The @a length must then be a multiple of + * 64 octets. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] hash_ctx Hashing algorithm and state of the cipher. + * @param msg Pointer to the data to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result If not null, pointer to where to store the hash + * digest. + * @param result_len Number of octets to store in @a result. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + SAH_SF_DCLS; + unsigned ctx_flags = (hash_ctx->flags & (FSL_HASH_FLAGS_INIT + | FSL_HASH_FLAGS_LOAD + | FSL_HASH_FLAGS_SAVE + | FSL_HASH_FLAGS_FINALIZE)); + + SAH_SF_USER_CHECK(); + + /* Reset expectations if user gets overly zealous. */ + if (result_len > hash_ctx->digest_length) { + result_len = hash_ctx->digest_length; + } + + /* Validate hash ctx flags. + * Need INIT or LOAD but not both. + * Need SAVE or digest ptr (both is ok). + */ + if (((ctx_flags & (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD)) + == (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD)) + || ((ctx_flags & (FSL_HASH_FLAGS_INIT | FSL_HASH_FLAGS_LOAD)) == 0) + || (!(ctx_flags & FSL_HASH_FLAGS_SAVE) && (result == NULL))) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + if (ctx_flags & FSL_HASH_FLAGS_INIT) { + sah_Oct_Str out_ptr; + unsigned out_len; + + /* Create desc to perform the initial hashing operation */ + /* Desc. #8 w/INIT and algorithm */ + header = SAH_HDR_MDHA_SET_MODE_HASH + ^ sah_insert_mdha_init + ^ sah_insert_mdha_algorithm[hash_ctx->algorithm]; + + /* If user wants one-shot, set padding operation. */ + if (ctx_flags & FSL_HASH_FLAGS_FINALIZE) { + header ^= sah_insert_mdha_pdata; + } + + /* Determine where Digest will go - hash_ctx or result */ + if (ctx_flags & FSL_HASH_FLAGS_SAVE) { + out_ptr = (sah_Oct_Str) hash_ctx->context; + out_len = hash_ctx->context_register_length; + } else { + out_ptr = result; + out_len = (result_len > hash_ctx->digest_length) + ? hash_ctx->digest_length : result_len; + } + + DESC_IN_OUT(header, length, (sah_Oct_Str) msg, out_len, + out_ptr); + } else { /* not doing hash INIT */ + void *out_ptr; + unsigned out_len; + + /* + * Build two descriptors -- one to load in context/set mode, the + * other to compute & retrieve hash/context value. + * + * First up - Desc. #6 to load context. + */ + /* Desc. #8 w/algorithm */ + header = SAH_HDR_MDHA_SET_MODE_MD_KEY + ^ sah_insert_mdha_algorithm[hash_ctx->algorithm]; + + if (ctx_flags & FSL_HASH_FLAGS_FINALIZE) { + header ^= sah_insert_mdha_pdata; + } + + /* Message Digest (in) */ + DESC_IN_IN(header, + hash_ctx->context_register_length, + (sah_Oct_Str) hash_ctx->context, 0, NULL); + + if (ctx_flags & FSL_HASH_FLAGS_SAVE) { + out_ptr = hash_ctx->context; + out_len = hash_ctx->context_register_length; + } else { + out_ptr = result; + out_len = result_len; + } + + /* Second -- run data through and retrieve ctx regs */ + /* Desc. #10 - no mode register with this. */ + header = SAH_HDR_MDHA_HASH; + DESC_IN_OUT(header, length, (sah_Oct_Str) msg, out_len, + out_ptr); + } /* else not INIT */ + + /* Now that execution is rejoined, we can append another descriptor + to extract the digest/context a second time, into the result. */ + if ((ctx_flags & FSL_HASH_FLAGS_SAVE) + && (result != NULL) && (result_len != 0)) { + + header = SAH_HDR_MDHA_STORE_DIGEST; + + /* Message Digest (out) */ + DESC_IN_OUT(header, 0, NULL, + (result_len > hash_ctx->digest_length) + ? hash_ctx->digest_length : result_len, result); + } + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} /* fsl_shw_hash() */ diff --git a/drivers/mxc/security/sahara2/fsl_shw_hmac.c b/drivers/mxc/security/sahara2/fsl_shw_hmac.c new file mode 100644 index 000000000000..21f4314054d6 --- /dev/null +++ b/drivers/mxc/security/sahara2/fsl_shw_hmac.c @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_hmac.c + * + * This file implements Hashed Message Authentication Code functions of the FSL + * SHW API for Sahara. + */ + +#include "sahara.h" +#include "sf_util.h" + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_hmac_precompute); +EXPORT_SYMBOL(fsl_shw_hmac); +#endif + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */ +/*! + * Get the precompute information + * + * + * @param user_ctx + * @param key_info + * @param hmac_ctx + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + if ((key_info->algorithm != FSL_KEY_ALG_HMAC) || + (key_info->key_length > 64)) { + return FSL_RETURN_BAD_ALGORITHM_S; + } else if (key_info->key_length == 0) { + return FSL_RETURN_BAD_KEY_LENGTH_S; + } + + /* Set up to start the Inner Calculation */ + /* Desc. #8 w/IPAD, & INIT */ + header = SAH_HDR_MDHA_SET_MODE_HASH + ^ sah_insert_mdha_ipad + ^ sah_insert_mdha_init + ^ sah_insert_mdha_algorithm[hmac_ctx->algorithm]; + + DESC_KEY_OUT(header, key_info, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->inner_precompute); + + /* Set up for starting Outer calculation */ + /* exchange IPAD bit for OPAD bit */ + header ^= (sah_insert_mdha_ipad ^ sah_insert_mdha_opad); + + /* Theoretically, we can leave this link out and use the key which is + * already in the register... however, if we do, the resulting opad + * hash does not have the correct value when using the model. */ + DESC_KEY_OUT(header, key_info, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->outer_precompute); + + SAH_SF_EXECUTE(); + if (ret == FSL_RETURN_OK_S) { + /* flag that precomputes have been entered in this hco + * assume it'll first be used for initilizing */ + hmac_ctx->flags |= (FSL_HMAC_FLAGS_INIT | + FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT); + } + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */ +/*! + * Get the hmac + * + * + * @param user_ctx Info for acquiring memory + * @param key_info + * @param hmac_ctx + * @param msg + * @param length + * @param result + * @param result_len + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + /* check flag consistency */ + /* Note that Final, Init, and Save are an illegal combination when a key + * is being used. Because of the logic flow of this routine, that is + * taken care of without being explict */ + if ( + /* nothing to work on */ + (((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) == 0) && + ((hmac_ctx->flags & FSL_HMAC_FLAGS_LOAD) == 0)) || + /* can't do both */ + ((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) && + (hmac_ctx->flags & FSL_HMAC_FLAGS_LOAD)) || + /* must be some output */ + (((hmac_ctx->flags & FSL_HMAC_FLAGS_SAVE) == 0) && + ((hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) == 0))) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* build descriptor #6 */ + + /* start building descriptor header */ + header = SAH_HDR_MDHA_SET_MODE_MD_KEY ^ + sah_insert_mdha_algorithm[hmac_ctx->algorithm] ^ + sah_insert_mdha_init; + + /* if this is to finalize the digest, mark to pad last block */ + if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) { + header ^= sah_insert_mdha_pdata; + } + + /* Check if this is a one shot */ + if ((hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) && + (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE)) { + + header ^= sah_insert_mdha_hmac; + + /* See if this uses Precomputes */ + if (hmac_ctx->flags & FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT) { + DESC_IN_IN(header, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->inner_precompute, + hmac_ctx->context_length, + (uint8_t *) hmac_ctx->outer_precompute); + } else { /* Precomputes not requested, try using Key */ + if (key_info->key != NULL) { + /* first, validate the key fields and related flag */ + if ((key_info->key_length == 0) + || (key_info->key_length > 64)) { + ret = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } else { + if (key_info->algorithm != + FSL_KEY_ALG_HMAC) { + ret = + FSL_RETURN_BAD_ALGORITHM_S; + goto out; + } + } + + /* finish building descriptor header (Key specific) */ + header ^= sah_insert_mdha_mac_full; + DESC_IN_KEY(header, 0, NULL, key_info); + } else { /* not using Key or Precomputes, so die */ + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + } + } else { /* it's not a one shot, must be multi-step */ + /* this the last chunk? */ + if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) { + header ^= sah_insert_mdha_hmac; + DESC_IN_IN(header, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->ongoing_context, + hmac_ctx->context_length, + (uint8_t *) hmac_ctx->outer_precompute); + } else { /* not last chunk */ + uint8_t *ptr1; + + if (hmac_ctx->flags & FSL_HMAC_FLAGS_INIT) { + /* must be using precomputes, cannot 'chunk' message + * starting with a key */ + if (hmac_ctx-> + flags & FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT) + { + ptr1 = + (uint8_t *) hmac_ctx-> + inner_precompute; + } else { + ret = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + } else { + ptr1 = (uint8_t *) hmac_ctx->ongoing_context; + } + + if (ret != FSL_RETURN_OK_S) { + goto out; + } + DESC_IN_IN(header, + hmac_ctx->context_register_length, ptr1, + 0, NULL); + } + } /* multi-step */ + + /* build descriptor #10 & maybe 11 */ + header = SAH_HDR_MDHA_HASH; + + if (hmac_ctx->flags & FSL_HMAC_FLAGS_FINALIZE) { + /* check that the results parameters seem reasonable */ + if ((result_len != 0) && (result != NULL)) { + if (result_len > hmac_ctx->context_register_length) { + result_len = hmac_ctx->context_register_length; + } + + /* message in / digest out (descriptor #10) */ + DESC_IN_OUT(header, length, msg, result_len, result); + + /* see if descriptor #11 needs to be built */ + if (hmac_ctx->flags & FSL_HMAC_FLAGS_SAVE) { + header = SAH_HDR_MDHA_STORE_DIGEST; + /* nothing in / context out */ + DESC_IN_IN(header, 0, NULL, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx-> + ongoing_context); + } + } else { + /* something wrong with result or its length */ + ret = FSL_RETURN_BAD_DATA_LENGTH_S; + } + } else { /* finalize not set, so store in ongoing context field */ + if ((length % 64) == 0) { /* this will change for 384/512 support */ + /* message in / context out */ + DESC_IN_OUT(header, length, msg, + hmac_ctx->context_register_length, + (uint8_t *) hmac_ctx->ongoing_context); + } else { + /* not final data, and not multiple of block length */ + ret = FSL_RETURN_BAD_DATA_LENGTH_S; + } + } + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} /* fsl_shw_hmac() */ diff --git a/drivers/mxc/security/sahara2/fsl_shw_keystore.c b/drivers/mxc/security/sahara2/fsl_shw_keystore.c new file mode 100644 index 000000000000..b45cda6dde01 --- /dev/null +++ b/drivers/mxc/security/sahara2/fsl_shw_keystore.c @@ -0,0 +1,837 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** + * @file fsl_shw_keystore.c + * + * File which implements a default keystore policy, for use as the system + * keystore. + */ +#include "fsl_platform.h" +#include "fsl_shw.h" +#include "fsl_shw_keystore.h" + +#if defined(DIAG_DRV_IF) +#include +#endif + +#if !defined(FSL_HAVE_SCC2) && defined(__KERNEL__) +#include +#endif + +/* Define a semaphore to protect the keystore data */ +#ifdef __KERNEL__ +#define LOCK_INCLUDES os_lock_context_t context +#define ACQUIRE_LOCK os_lock_save_context(keystore->lock, context) +#define RELEASE_LOCK os_unlock_restore_context(keystore->lock, context); +#else +#define LOCK_INCLUDES +#define ACQUIRE_LOCK +#define RELEASE_LOCK +#endif /* __KERNEL__ */ + +/*! + * Calculates the byte offset into a word + * @param bp The byte (char*) pointer + * @return The offset (0, 1, 2, or 3) + */ +#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t)) + +/*! + * Converts (by rounding down) a byte pointer into a word pointer + * @param bp The byte (char*) pointer + * @return The word (uint32_t) as though it were an aligned (uint32_t*) + */ +#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1)) + +/* Depending on the architecture, these functions should be defined + * differently. On Platforms with SCC2, the functions use the secure + * partition interface and should be available in both user and kernel space. + * On platforms with SCC, they use the SCC keystore interface. This is only + * available in kernel mode, so they should be stubbed out in user mode. + */ +#if defined(FSL_HAVE_SCC2) || (defined(FSL_HAVE_SCC) && defined(__KERNEL__)) +EXPORT_SYMBOL(fsl_shw_init_keystore); +void fsl_shw_init_keystore( + fsl_shw_kso_t *keystore, + fsl_shw_return_t(*data_init) (fsl_shw_uco_t *user_ctx, + void **user_data), + void (*data_cleanup) (fsl_shw_uco_t *user_ctx, + void **user_data), + fsl_shw_return_t(*slot_alloc) (void *user_data, + uint32_t size, + uint64_t owner_id, + uint32_t *slot), + fsl_shw_return_t(*slot_dealloc) (void *user_data, + uint64_t + owner_id, + uint32_t slot), + fsl_shw_return_t(*slot_verify_access) (void + *user_data, + uint64_t + owner_id, + uint32_t + slot), + void *(*slot_get_address) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_base) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_offset) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_slot_size) (void *user_data, + uint32_t handle)) +{ + keystore->data_init = data_init; + keystore->data_cleanup = data_cleanup; + keystore->slot_alloc = slot_alloc; + keystore->slot_dealloc = slot_dealloc; + keystore->slot_verify_access = slot_verify_access; + keystore->slot_get_address = slot_get_address; + keystore->slot_get_base = slot_get_base; + keystore->slot_get_offset = slot_get_offset; + keystore->slot_get_slot_size = slot_get_slot_size; +} + +EXPORT_SYMBOL(fsl_shw_init_keystore_default); +void fsl_shw_init_keystore_default(fsl_shw_kso_t *keystore) +{ + keystore->data_init = shw_kso_init_data; + keystore->data_cleanup = shw_kso_cleanup_data; + keystore->slot_alloc = shw_slot_alloc; + keystore->slot_dealloc = shw_slot_dealloc; + keystore->slot_verify_access = shw_slot_verify_access; + keystore->slot_get_address = shw_slot_get_address; + keystore->slot_get_base = shw_slot_get_base; + keystore->slot_get_offset = shw_slot_get_offset; + keystore->slot_get_slot_size = shw_slot_get_slot_size; +} + +/*! + * Do any keystore specific initializations + */ +EXPORT_SYMBOL(fsl_shw_establish_keystore); +fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t *user_ctx, + fsl_shw_kso_t *keystore) +{ + if (keystore->data_init == NULL) { + return FSL_RETURN_ERROR_S; + } + + /* Call the data_init function for any user setup */ + return keystore->data_init(user_ctx, &(keystore->user_data)); +} + +EXPORT_SYMBOL(fsl_shw_release_keystore); +void fsl_shw_release_keystore(fsl_shw_uco_t *user_ctx, + fsl_shw_kso_t *keystore) +{ + + /* Call the data_cleanup function for any keystore cleanup. + * NOTE: The keystore doesn't have any way of telling which keys are using + * it, so it is up to the user program to manage their key objects + * correctly. + */ + if ((keystore != NULL) && (keystore->data_cleanup != NULL)) { + keystore->data_cleanup(user_ctx, &(keystore->user_data)); + } + return; +} + +fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t *keystore, uint32_t size, + uint64_t owner_id, uint32_t *slot) +{ + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + +#ifdef DIAG_DRV_IF + LOG_DIAG("In keystore_slot_alloc."); + +#endif + ACQUIRE_LOCK; + if ((keystore->slot_alloc == NULL) || (keystore->user_data == NULL)) { + goto out; + } + +#ifdef DIAG_DRV_IF + LOG_DIAG_ARGS("key length: %i, handle: %i\n", size, *slot); + +#endif +retval = keystore->slot_alloc(keystore->user_data, size, owner_id, slot); +out:RELEASE_LOCK; + return retval; +} + +fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot) +{ + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + ACQUIRE_LOCK; + if ((keystore->slot_alloc == NULL) || (keystore->user_data == NULL)) { + goto out; + } + retval = + keystore->slot_dealloc(keystore->user_data, owner_id, slot); +out:RELEASE_LOCK; + return retval; +} + +fsl_shw_return_t +keystore_slot_load(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + const uint8_t * key_data, uint32_t key_length) +{ + +#ifdef FSL_HAVE_SCC2 + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + uint32_t slot_size; + uint32_t i; + uint8_t * slot_location; + ACQUIRE_LOCK; + if ((keystore->slot_verify_access == NULL) || + (keystore->user_data == NULL)) + goto out; + if (keystore-> + slot_verify_access(keystore->user_data, owner_id, + slot) !=FSL_RETURN_OK_S) { + retval = FSL_RETURN_AUTH_FAILED_S; + goto out; + } + slot_size = keystore->slot_get_slot_size(keystore->user_data, slot); + if (key_length > slot_size) { + retval = FSL_RETURN_BAD_DATA_LENGTH_S; + goto out; + } + slot_location = keystore->slot_get_address(keystore->user_data, slot); + for (i = 0; i < key_length; i++) { + slot_location[i] = key_data[i]; + } + retval = FSL_RETURN_OK_S; +out:RELEASE_LOCK; + return retval; + +#else /* FSL_HAVE_SCC2 */ + fsl_shw_return_t retval; + scc_return_t scc_ret; + scc_ret = + scc_load_slot(owner_id, slot, (uint8_t *) key_data, key_length); + switch (scc_ret) { + case SCC_RET_OK: + retval = FSL_RETURN_OK_S; + break; + case SCC_RET_VERIFICATION_FAILED: + retval = FSL_RETURN_AUTH_FAILED_S; + break; + case SCC_RET_INSUFFICIENT_SPACE: + retval = FSL_RETURN_BAD_DATA_LENGTH_S; + break; + default: + retval = FSL_RETURN_ERROR_S; + } + return retval; + +#endif /* FSL_HAVE_SCC2 */ +} + +fsl_shw_return_t +keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + uint32_t key_length, uint8_t * key_data) +{ +#ifdef FSL_HAVE_SCC2 + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + uint8_t *slot_addr; + uint32_t slot_size; + + slot_addr = keystore->slot_get_address(keystore->user_data, slot); + slot_size = keystore->slot_get_slot_size(keystore->user_data, slot); + + if (key_length > slot_size) { + retval = FSL_RETURN_BAD_KEY_LENGTH_S; + goto out; + } + + memcpy(key_data, slot_addr, key_length); + retval = FSL_RETURN_OK_S; + + out: + return retval; + +#else /* Have SCC2 */ + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + scc_return_t scc_ret; + printk("keystore SCC \n"); + + scc_ret = + scc_read_slot(owner_id, slot, key_length, (uint8_t *) key_data); + printk("keystore SCC Ret value: %d \n", scc_ret); + switch (scc_ret) { + case SCC_RET_OK: + retval = FSL_RETURN_OK_S; + break; + case SCC_RET_VERIFICATION_FAILED: + retval = FSL_RETURN_AUTH_FAILED_S; + break; + case SCC_RET_INSUFFICIENT_SPACE: + retval = FSL_RETURN_BAD_DATA_LENGTH_S; + break; + default: + retval = FSL_RETURN_ERROR_S; + } + + return retval; + +#endif /* FSL_HAVE_SCC2 */ +}/* end fn keystore_slot_read */ + +fsl_shw_return_t +keystore_slot_encrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot, uint32_t length, + uint8_t *destination) +{ + +#ifdef FSL_HAVE_SCC2 + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + uint32_t slot_length; + uint32_t IV[4]; + uint32_t * iv_ptr = (uint32_t *) & (owner_id); + + /* Build the IV */ + IV[0] = iv_ptr[0]; + IV[1] = iv_ptr[1]; + IV[2] = 0; + IV[3] = 0; + ACQUIRE_LOCK; + + /* Ensure that the data will fit in the key slot */ + slot_length = + keystore->slot_get_slot_size(keystore->user_data, slot); + if (length > slot_length) { + goto out; + } + + /* Call scc encrypt function to encrypt the data. */ + retval = do_scc_encrypt_region(user_ctx, + (void *)keystore-> + slot_get_base(keystore->user_data, + slot), + keystore->slot_get_offset(keystore-> + user_data, + slot), + length, destination, IV, + FSL_SHW_CYPHER_MODE_CBC); + goto out; +out:RELEASE_LOCK; + return retval; + +#else + scc_return_t retval; + retval = scc_encrypt_slot(owner_id, slot, length, destination); + if (retval == SCC_RET_OK) + return FSL_RETURN_OK_S; + return FSL_RETURN_ERROR_S; + +#endif /* FSL_HAVE_SCC2 */ +} + +fsl_shw_return_t +keystore_slot_decrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot, uint32_t length, + const uint8_t *source) +{ + +#ifdef FSL_HAVE_SCC2 + LOCK_INCLUDES; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + uint32_t slot_length; + uint32_t IV[4]; + uint32_t *iv_ptr = (uint32_t *) & (owner_id); + + /* Build the IV */ + IV[0] = iv_ptr[0]; + IV[1] = iv_ptr[1]; + IV[2] = 0; + IV[3] = 0; + ACQUIRE_LOCK; + + /* Call scc decrypt function to decrypt the data. */ + + /* Ensure that the data will fit in the key slot */ + slot_length = + keystore->slot_get_slot_size(keystore->user_data, slot); + if (length > slot_length) + goto out; + + /* Call scc decrypt function to encrypt the data. */ + retval = do_scc_decrypt_region(user_ctx, + (void *)keystore-> + slot_get_base(keystore->user_data, + slot), + keystore->slot_get_offset(keystore-> + user_data, + slot), + length, source, IV, + FSL_SHW_CYPHER_MODE_CBC); + goto out; +out:RELEASE_LOCK; + return retval; + +#else + scc_return_t retval; + retval = scc_decrypt_slot(owner_id, slot, length, source); + if (retval == SCC_RET_OK) + return FSL_RETURN_OK_S; + return FSL_RETURN_ERROR_S; + +#endif /* FSL_HAVE_SCC2 */ +} + +#else /* SCC in userspace */ +void fsl_shw_init_keystore( + fsl_shw_kso_t *keystore, + fsl_shw_return_t(*data_init) (fsl_shw_uco_t *user_ctx, + void **user_data), + void (*data_cleanup) (fsl_shw_uco_t *user_ctx, + void **user_data), + fsl_shw_return_t(*slot_alloc) (void *user_data, + uint32_t size, + uint64_t owner_id, + uint32_t *slot), + fsl_shw_return_t(*slot_dealloc) (void *user_data, + uint64_t + owner_id, + uint32_t slot), + fsl_shw_return_t(*slot_verify_access) (void + *user_data, + uint64_t + owner_id, + uint32_t + slot), + void *(*slot_get_address) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_base) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_offset) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_slot_size) (void *user_data, + uint32_t handle)) +{ + (void)keystore; + (void)data_init; + (void)data_cleanup; + (void)slot_alloc; + (void)slot_dealloc; + (void)slot_verify_access; + (void)slot_get_address; + (void)slot_get_base; + (void)slot_get_offset; + (void)slot_get_slot_size; +} + +void fsl_shw_init_keystore_default(fsl_shw_kso_t * keystore) +{ + (void)keystore; +} +fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t *user_ctx, + fsl_shw_kso_t *keystore) +{ + (void)user_ctx; + (void)keystore; + return FSL_RETURN_NO_RESOURCE_S; +} +void fsl_shw_release_keystore(fsl_shw_uco_t *user_ctx, + fsl_shw_kso_t *keystore) +{ + (void)user_ctx; + (void)keystore; + return; +} + +fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t *keystore, uint32_t size, + uint64_t owner_id, uint32_t *slot) +{ + (void)keystore; + (void)size; + (void)owner_id; + (void)slot; + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot) +{ + (void)keystore; + (void)owner_id; + (void)slot; + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t +keystore_slot_load(fsl_shw_kso_t *keystore, uint64_t owner_id, uint32_t slot, + const uint8_t *key_data, uint32_t key_length) +{ + (void)keystore; + (void)owner_id; + (void)slot; + (void)key_data; + (void)key_length; + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t +keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + uint32_t key_length, uint8_t * key_data) +{ + (void)keystore; + (void)owner_id; + (void)slot; + (void)key_length; + (void)key_data; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t +keystore_slot_decrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot, uint32_t length, + const uint8_t *source) +{ + (void)user_ctx; + (void)keystore; + (void)owner_id; + (void)slot; + (void)length; + (void)source; + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t +keystore_slot_encrypt(fsl_shw_uco_t *user_ctx, fsl_shw_kso_t *keystore, + uint64_t owner_id, uint32_t slot, uint32_t length, + uint8_t *destination) +{ + (void)user_ctx; + (void)keystore; + (void)owner_id; + (void)slot; + (void)length; + (void)destination; + return FSL_RETURN_NO_RESOURCE_S; +} + + +#endif /* FSL_HAVE_SCC2 */ + +/***** Default keystore implementation **************************************/ + +#ifdef FSL_HAVE_SCC2 + fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t *user_ctx, + void **user_data) +{ + int retval = FSL_RETURN_ERROR_S; + keystore_data_t *keystore_data = NULL; + fsl_shw_pco_t *capabilities = fsl_shw_get_capabilities(user_ctx); + uint32_t partition_size; + uint32_t slot_count; + uint32_t keystore_data_size; + uint8_t UMID[16] = { + 0x42, 0, 0, 0, 0x43, 0, 0, 0, 0x19, 0, 0, 0, 0x59, 0, 0, 0}; + uint32_t permissions = + FSL_PERM_TH_R | FSL_PERM_TH_W | FSL_PERM_HD_R | FSL_PERM_HD_W | + FSL_PERM_HD_X; + + /* Look up the size of a partition to see how big to make the keystore */ + partition_size = fsl_shw_pco_get_spo_size_bytes(capabilities); + + /* Calculate the required size of the keystore data structure, based on the + * number of keys that can fit in the partition. + */ + slot_count = partition_size / KEYSTORE_SLOT_SIZE; + keystore_data_size = + sizeof(keystore_data_t) + + slot_count * sizeof(keystore_data_slot_info_t); + +#ifdef __KERNEL__ + keystore_data = os_alloc_memory(keystore_data_size, GFP_KERNEL); + +#else + keystore_data = malloc(keystore_data_size); + +#endif + if (keystore_data == NULL) { + retval = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + + /* Clear the memory (effectively clear all key assignments) */ + memset(keystore_data, 0, keystore_data_size); + + /* Place the slot information structure directly after the keystore data + * structure. + */ + keystore_data->slot = + (keystore_data_slot_info_t *) (keystore_data + 1); + keystore_data->slot_count = slot_count; + + /* Retrieve a secure partition to put the keystore in. */ + keystore_data->base_address = + fsl_shw_smalloc(user_ctx, partition_size, UMID, permissions); + if (keystore_data->base_address == NULL) { + retval = FSL_RETURN_NO_RESOURCE_S; + goto out; + } + *user_data = keystore_data; + retval = FSL_RETURN_OK_S; +out:if (retval != FSL_RETURN_OK_S) { + if (keystore_data != NULL) { + if (keystore_data->base_address != NULL) + fsl_shw_sfree(NULL, + keystore_data->base_address); + +#ifdef __KERNEL__ + os_free_memory(keystore_data); + +#else + free(keystore_data); + +#endif + } + } + return retval; +} +void shw_kso_cleanup_data(fsl_shw_uco_t *user_ctx, void **user_data) +{ + if (user_data != NULL) { + keystore_data_t * keystore_data = + (keystore_data_t *) (*user_data); + fsl_shw_sfree(user_ctx, keystore_data->base_address); + +#ifdef __KERNEL__ + os_free_memory(*user_data); + +#else + free(*user_data); + +#endif + } + return; +} + +fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id, + uint32_t slot) +{ + keystore_data_t * data = user_data; + if (data->slot[slot].owner == owner_id) { + return FSL_RETURN_OK_S; + } else { + +#ifdef DIAG_DRV_IF + LOG_DIAG_ARGS("Access to slot %i fails.\n", slot); + +#endif + return FSL_RETURN_AUTH_FAILED_S; + } +} + +fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size, + uint64_t owner_id, uint32_t *slot) +{ + keystore_data_t *data = user_data; + uint32_t i; + if (size > KEYSTORE_SLOT_SIZE) + return FSL_RETURN_BAD_KEY_LENGTH_S; + for (i = 0; i < data->slot_count; i++) { + if (data->slot[i].allocated == 0) { + data->slot[i].allocated = 1; + data->slot[i].owner = owner_id; + (*slot) = i; + +#ifdef DIAG_DRV_IF + LOG_DIAG_ARGS("Keystore: allocated slot %i. Slot " + "address: %p\n", + (*slot), + data->base_address + + (*slot) * KEYSTORE_SLOT_SIZE); + +#endif + return FSL_RETURN_OK_S; + } + } + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t shw_slot_dealloc(void *user_data, uint64_t owner_id, + uint32_t slot) +{ + keystore_data_t * data = user_data; + (void)owner_id; + (void)slot; + if (slot >= data->slot_count) + return FSL_RETURN_ERROR_S; + if (data->slot[slot].allocated == 1) { + /* Forcibly remove the data from the keystore */ + memset(shw_slot_get_address(user_data, slot), 0, + KEYSTORE_SLOT_SIZE); + data->slot[slot].allocated = 0; + return FSL_RETURN_OK_S; + } + return FSL_RETURN_ERROR_S; +} + +void *shw_slot_get_address(void *user_data, uint32_t slot) +{ + keystore_data_t * data = user_data; + if (slot >= data->slot_count) + return NULL; + return data->base_address + slot * KEYSTORE_SLOT_SIZE; +} + +uint32_t shw_slot_get_base(void *user_data, uint32_t slot) +{ + keystore_data_t * data = user_data; + + /* There could potentially be more than one secure partition object + * associated with this keystore. For now, there is just one. + */ + (void)slot; + return (uint32_t) (data->base_address); +} + +uint32_t shw_slot_get_offset(void *user_data, uint32_t slot) +{ + keystore_data_t *data = user_data; + if (slot >= data->slot_count) + return FSL_RETURN_ERROR_S; + return (slot * KEYSTORE_SLOT_SIZE); +} + +uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot) +{ + (void)user_data; + (void)slot; + + /* All slots are the same size in the default implementation */ + return KEYSTORE_SLOT_SIZE; +} + +#else /* FSL_HAVE_SCC2 */ + +#ifdef __KERNEL__ + fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t *user_ctx, + void **user_data) +{ + + /* The SCC does its own initialization. All that needs to be done here is + * make sure an SCC exists. + */ + *user_data = (void *)0xFEEDFEED; + return FSL_RETURN_OK_S; +} +void shw_kso_cleanup_data(fsl_shw_uco_t *user_ctx, void **user_data) +{ + + /* The SCC does its own cleanup. */ + *user_data = NULL; + return; +} + +fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id, + uint32_t slot) +{ + + /* Zero is used for the size because the newer interface does bounds + * checking later. + */ + scc_return_t retval; + retval = scc_verify_slot_access(owner_id, slot, 0); + if (retval == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } + return FSL_RETURN_AUTH_FAILED_S; +} + +fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size, + uint64_t owner_id, uint32_t *slot) +{ + scc_return_t retval; + +#ifdef DIAG_DRV_IF + LOG_DIAG_ARGS("key length: %i, handle: %i\n", size, *slot); + +#endif + retval = scc_alloc_slot(size, owner_id, slot); + if (retval == SCC_RET_OK) + return FSL_RETURN_OK_S; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t shw_slot_dealloc(void *user_data, uint64_t owner_id, + uint32_t slot) +{ + scc_return_t retval; + retval = scc_dealloc_slot(owner_id, slot); + if (retval == SCC_RET_OK) + return FSL_RETURN_OK_S; + + return FSL_RETURN_ERROR_S; +} +void *shw_slot_get_address(void *user_data, uint32_t slot) +{ + uint64_t owner_id = *((uint64_t *) user_data); + uint32_t address; + uint32_t value_size_bytes; + uint32_t slot_size_bytes; + scc_return_t scc_ret; + scc_ret = + scc_get_slot_info(owner_id, slot, &address, &value_size_bytes, + &slot_size_bytes); + if (scc_ret == SCC_RET_OK) { + return (void *)address; + } + return NULL; +} + +uint32_t shw_slot_get_base(void *user_data, uint32_t slot) +{ + return 0; +} + +uint32_t shw_slot_get_offset(void *user_data, uint32_t slot) +{ + return 0; +} + + +/* Return the size of the key slot, in octets */ +uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot) +{ + uint64_t owner_id = *((uint64_t *) user_data); + uint32_t address; + uint32_t value_size_bytes; + uint32_t slot_size_bytes; + scc_return_t scc_ret; + scc_ret = + scc_get_slot_info(owner_id, slot, &address, &value_size_bytes, + &slot_size_bytes); + if (scc_ret == SCC_RET_OK) + return slot_size_bytes; + return 0; +} + + +#endif /* __KERNEL__ */ + +#endif /* FSL_HAVE_SCC2 */ + +/*****************************************************************************/ diff --git a/drivers/mxc/security/sahara2/fsl_shw_rand.c b/drivers/mxc/security/sahara2/fsl_shw_rand.c new file mode 100644 index 000000000000..69999c3272f3 --- /dev/null +++ b/drivers/mxc/security/sahara2/fsl_shw_rand.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_rand.c + * + * This file implements Random Number Generation functions of the FSL SHW API + * for Sahara. + */ + +#include "sahara.h" +#include "sf_util.h" + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_get_random); +#endif + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +/*! + * Get a random number + * + * + * @param user_ctx + * @param length + * @param data + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + SAH_SF_DCLS; + + /* perform a sanity check on the uco */ + ret = sah_validate_uco(user_ctx); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + header = SAH_HDR_RNG_GENERATE; /* Desc. #18 */ + DESC_OUT_OUT(header, length, data, 0, NULL); + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_add_entropy); +#endif + +/*! + * Add entropy to a random number generator + + * @param user_ctx + * @param length + * @param data + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data) +{ + SAH_SF_DCLS; + + /* perform a sanity check on the uco */ + ret = sah_validate_uco(user_ctx); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + header = SAH_HDR_RNG_GENERATE; /* Desc. #18 */ + + /* create descriptor #18. Generate random data */ + DESC_IN_IN(header, 0, NULL, length, data) + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} diff --git a/drivers/mxc/security/sahara2/fsl_shw_sym.c b/drivers/mxc/security/sahara2/fsl_shw_sym.c new file mode 100644 index 000000000000..133b92dad3c1 --- /dev/null +++ b/drivers/mxc/security/sahara2/fsl_shw_sym.c @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_sym.c + * + * This file implements Symmetric Cipher functions of the FSL SHW API for + * Sahara. This does not include CCM. + */ + +#include "sahara.h" +#include "fsl_platform.h" + +#include "sf_util.h" +#include "adaptor.h" + +#ifdef LINUX_KERNEL +EXPORT_SYMBOL(fsl_shw_symmetric_encrypt); +EXPORT_SYMBOL(fsl_shw_symmetric_decrypt); +#endif + +#if defined(NEED_CTR_WORKAROUND) +/* CTR mode needs block-multiple data in/out */ +#define LENGTH_PATCH (sym_ctx->block_size_bytes) +#define LENGTH_PATCH_MASK (sym_ctx->block_size_bytes-1) +#else +#define LENGTH_PATCH 0 +#define LENGTH_PATCH_MASK 0 /* du not use! */ +#endif + +/*! + * Block of zeroes which is maximum Symmetric block size, used for + * initializing context register, etc. + */ +static uint32_t block_zeros[4] = { + 0, 0, 0, 0 +}; + +typedef enum cipher_direction { + SYM_DECRYPT, + SYM_ENCRYPT +} cipher_direction_t; + +/*! + * Create and run the chain for a symmetric-key operation. + * + * @param user_ctx Who the user is + * @param key_info What key is to be used + * @param sym_ctx Info details about algorithm + * @param encrypt 0 = decrypt, non-zero = encrypt + * @param length Number of octets at @a in and @a out + * @param in Pointer to input data + * @param out Location to store output data + * + * @return The status of handing chain to driver, + * or an earlier argument/flag or allocation + * error. + */ +static fsl_shw_return_t do_symmetric(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + cipher_direction_t encrypt, + uint32_t length, + const uint8_t * in, uint8_t * out) +{ + SAH_SF_DCLS; + uint8_t *sink = NULL; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + sah_Oct_Str ptr1; + uint32_t size1 = sym_ctx->block_size_bytes; + + SAH_SF_USER_CHECK(); + + /* Two different sets of chains, depending on algorithm */ + if (key_info->algorithm == FSL_KEY_ALG_ARC4) { + if (sym_ctx->flags & FSL_SYM_CTX_INIT) { + /* Desc. #35 w/ARC4 - start from key */ + header = SAH_HDR_ARC4_SET_MODE_KEY + ^ sah_insert_skha_algorithm_arc4; + + DESC_IN_KEY(header, 0, NULL, key_info); + } else { /* load SBox */ + /* Desc. #33 w/ARC4 and NO PERMUTE */ + header = SAH_HDR_ARC4_SET_MODE_SBOX + ^ sah_insert_skha_no_permute + ^ sah_insert_skha_algorithm_arc4; + DESC_IN_IN(header, 256, sym_ctx->context, + 3, sym_ctx->context + 256); + } /* load SBox */ + + /* Add in-out data descriptor to process the data */ + if (length != 0) { + DESC_IN_OUT(SAH_HDR_SKHA_ENC_DEC, length, in, length, + out); + } + + /* Operation is done ... save what came out? */ + if (sym_ctx->flags & FSL_SYM_CTX_SAVE) { + /* Desc. #34 - Read SBox, pointers */ + header = SAH_HDR_ARC4_READ_SBOX; + DESC_OUT_OUT(header, 256, sym_ctx->context, + 3, sym_ctx->context + 256); + } + } else { /* not ARC4 */ + /* Doing 1- or 2- descriptor chain. */ + /* Desc. #1 and algorithm and mode */ + header = SAH_HDR_SKHA_SET_MODE_IV_KEY + ^ sah_insert_skha_mode[sym_ctx->mode] + ^ sah_insert_skha_algorithm[key_info->algorithm]; + + /* Honor 'no key parity checking' for DES and TDES */ + if ((key_info->flags & FSL_SKO_KEY_IGNORE_PARITY) && + ((key_info->algorithm == FSL_KEY_ALG_DES) || + (key_info->algorithm == FSL_KEY_ALG_TDES))) { + header ^= sah_insert_skha_no_key_parity; + } + + /* Header by default is decrypting, so... */ + if (encrypt == SYM_ENCRYPT) { + header ^= sah_insert_skha_encrypt; + } + + if (sym_ctx->mode == FSL_SYM_MODE_CTR) { + header ^= sah_insert_skha_modulus[sym_ctx->modulus_exp]; + } + + if (sym_ctx->mode == FSL_SYM_MODE_ECB) { + ptr1 = NULL; + size1 = 0; + } else if (sym_ctx->flags & FSL_SYM_CTX_INIT) { + ptr1 = (uint8_t *) block_zeros; + } else { + ptr1 = sym_ctx->context; + } + + DESC_IN_KEY(header, sym_ctx->block_size_bytes, ptr1, key_info); + + /* Add in-out data descriptor */ + if (length != 0) { + header = SAH_HDR_SKHA_ENC_DEC; + if (LENGTH_PATCH && (sym_ctx->mode == FSL_SYM_MODE_CTR) + && ((length & LENGTH_PATCH_MASK) != 0)) { + sink = DESC_TEMP_ALLOC(LENGTH_PATCH); + ret = + sah_Create_Link(user_ctx->mem_util, &link1, + (uint8_t *) in, length, + SAH_USES_LINK_DATA); + ret = + sah_Append_Link(user_ctx->mem_util, link1, + (uint8_t *) sink, + LENGTH_PATCH - + (length & + LENGTH_PATCH_MASK), + SAH_USES_LINK_DATA); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + ret = + sah_Create_Link(user_ctx->mem_util, &link2, + out, length, + SAH_USES_LINK_DATA | + SAH_OUTPUT_LINK); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + ret = sah_Append_Link(user_ctx->mem_util, link2, + sink, + LENGTH_PATCH - + (length & + LENGTH_PATCH_MASK), + SAH_USES_LINK_DATA); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + ret = + sah_Append_Desc(user_ctx->mem_util, + &desc_chain, header, link1, + link2); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + link1 = link2 = NULL; + } else { + DESC_IN_OUT(header, length, in, length, out); + } + } + + /* Unload any desired context */ + if (sym_ctx->flags & FSL_SYM_CTX_SAVE) { + DESC_OUT_OUT(SAH_HDR_SKHA_READ_CONTEXT_IV, 0, NULL, + sym_ctx->block_size_bytes, + sym_ctx->context); + } + + } /* not ARC4 */ + + SAH_SF_EXECUTE(); + + out: + SAH_SF_DESC_CLEAN(); + DESC_TEMP_FREE(sink); + if (LENGTH_PATCH) { + sah_Destroy_Link(user_ctx->mem_util, link1); + sah_Destroy_Link(user_ctx->mem_util, link2); + } + + return ret; +} + +/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ + +/*! + * Compute symmetric encryption + * + * + * @param user_ctx + * @param key_info + * @param sym_ctx + * @param length + * @param pt + * @param ct + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, uint8_t * ct) +{ + fsl_shw_return_t ret; + + ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_ENCRYPT, + length, pt, ct); + + return ret; +} + +/* PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ + +/*! + * Compute symmetric decryption + * + * + * @param user_ctx + * @param key_info + * @param sym_ctx + * @param length + * @param pt + * @param ct + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, uint8_t * pt) +{ + fsl_shw_return_t ret; + + ret = do_symmetric(user_ctx, key_info, sym_ctx, SYM_DECRYPT, + length, ct, pt); + + return ret; +} diff --git a/drivers/mxc/security/sahara2/fsl_shw_user.c b/drivers/mxc/security/sahara2/fsl_shw_user.c new file mode 100644 index 000000000000..e53b29cfd404 --- /dev/null +++ b/drivers/mxc/security/sahara2/fsl_shw_user.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_user.c + * + * This file implements user and platform capabilities functions of the FSL SHW + * API for Sahara + */ +#include "sahara.h" +#include +#include + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_get_capabilities); +EXPORT_SYMBOL(fsl_shw_register_user); +EXPORT_SYMBOL(fsl_shw_deregister_user); +EXPORT_SYMBOL(fsl_shw_get_results); +#endif /* __KERNEL__ */ + +struct cap_t { + unsigned populated; + union { + uint32_t buffer[sizeof(fsl_shw_pco_t)]; + fsl_shw_pco_t pco; + }; +}; + +static struct cap_t cap = { + 0, + {} +}; + +/* REQ-S2LRD-PINTFC-API-GEN-003 */ +/*! + * Determine the hardware security capabilities of this platform. + * + * Though a user context object is passed into this function, it will always + * act in a non-blocking manner. + * + * @param user_ctx The user context which will be used for the query. + * + * @return A pointer to the capabilities object. + */ +fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_pco_t *retval = NULL; + + if (cap.populated) { + retval = &cap.pco; + } else { + if (get_capabilities(user_ctx, &cap.pco) == FSL_RETURN_OK_S) { + cap.populated = 1; + retval = &cap.pco; + } + } + return retval; +} + +/* REQ-S2LRD-PINTFC-API-GEN-004 */ + +/*! + * Create an association between the the user and the provider of the API. + * + * @param user_ctx The user context which will be used for this association. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx) +{ + return sah_register(user_ctx); +} + +/* REQ-S2LRD-PINTFC-API-GEN-005 */ + +/*! + * Destroy the association between the the user and the provider of the API. + * + * @param user_ctx The user context which is no longer needed. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx) +{ + return sah_deregister(user_ctx); +} + +/* REQ-S2LRD-PINTFC-API-GEN-006 */ + +/*! + * Retrieve results from earlier operations. + * + * @param user_ctx The user's context. + * @param result_size The number of array elements of @a results. + * @param[in,out] results Pointer to first of the (array of) locations to + * store results. + * @param[out] result_count Pointer to store the number of results which + * were returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx, + unsigned result_size, + fsl_shw_result_t results[], + unsigned *result_count) +{ + fsl_shw_return_t status; + + /* perform a sanity check on the uco */ + status = sah_validate_uco(user_ctx); + + /* if uco appears ok, build structure and pass to get results */ + if (status == FSL_RETURN_OK_S) { + sah_results arg; + + /* if requested is zero, it's done before it started */ + if (result_size > 0) { + arg.requested = result_size; + arg.actual = result_count; + arg.results = results; + /* get the results */ + status = sah_get_results(&arg, user_ctx); + } + } + + return status; +} diff --git a/drivers/mxc/security/sahara2/fsl_shw_wrap.c b/drivers/mxc/security/sahara2/fsl_shw_wrap.c new file mode 100644 index 000000000000..9f2e28c7b84d --- /dev/null +++ b/drivers/mxc/security/sahara2/fsl_shw_wrap.c @@ -0,0 +1,967 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_shw_wrap.c + * + * This file implements Key-Wrap (Black Key) functions of the FSL SHW API for + * Sahara. + * + * - Ownerid is an 8-byte, user-supplied, value to keep KEY confidential. + * - KEY is a 1-32 byte value which starts in SCC RED RAM before + * wrapping, and ends up there on unwrap. Length is limited because of + * size of SCC1 RAM. + * - KEY' is the encrypted KEY + * - LEN is a 1-byte (for now) byte-length of KEY + * - ALG is a 1-byte value for the algorithm which which the key is + * associated. Values are defined by the FSL SHW API + * - Ownerid, LEN, and ALG come from the user's "key_info" object, as does the + * slot number where KEY already is/will be. + * - T is a Nonce + * - T' is the encrypted T + * - KEK is a Key-Encryption Key for the user's Key + * - ICV is the "Integrity Check Value" for the wrapped key + * - Black Key is the string of bytes returned as the wrapped key + + + + + + + + + + + + + + + + + + +
BLACK_KEY =ICV | T' | LEN | ALG | + KEY'
 
To Wrap
T = RND()16 +
KEK=HASHsha256(T | + Ownerid)16
KEY'= + AESctr-enc(Key=KEK, CTR=0, Data=KEY)
ICV=HMACsha256 + (Key=T, Data=Ownerid | LEN | ALG | KEY')16
T'=TDEScbc-enc + (Key=SLID, IV=Ownerid, Data=T)
 
To Unwrap
T=TDESecb-dec + (Key=SLID, IV=Ownerid, Data=T')
ICV=HMACsha256 + (Key=T, Data=Ownerid | LEN | ALG | KEY')16
KEK=HASHsha256 + (T | Ownerid)16
KEY=AESctr-dec + (Key=KEK, CTR=0, Data=KEY')
+ + */ + +#include "sahara.h" +#include "fsl_platform.h" +#include "fsl_shw_keystore.h" + +#include "sf_util.h" +#include "adaptor.h" + +#if defined(DIAG_SECURITY_FUNC) +#include +#endif + +#if defined(NEED_CTR_WORKAROUND) +/* CTR mode needs block-multiple data in/out */ +#define LENGTH_PATCH 16 +#define LENGTH_PATCH_MASK 0xF +#else +#define LENGTH_PATCH 4 +#define LENGTH_PATCH_MASK 3 +#endif + +#if LENGTH_PATCH +#define ROUND_LENGTH(len) \ +({ \ + uint32_t orig_len = len; \ + uint32_t new_len; \ + \ + if ((orig_len & LENGTH_PATCH_MASK) != 0) { \ + new_len = (orig_len + LENGTH_PATCH \ + - (orig_len & LENGTH_PATCH_MASK)); \ + } \ + else { \ + new_len = orig_len; \ + } \ + new_len; \ +}) +#else +#define ROUND_LENGTH(len) (len) +#endif + +#ifdef __KERNEL__ +EXPORT_SYMBOL(fsl_shw_establish_key); +EXPORT_SYMBOL(fsl_shw_extract_key); +EXPORT_SYMBOL(fsl_shw_release_key); +EXPORT_SYMBOL(fsl_shw_read_key); +#endif + +#define ICV_LENGTH 16 +#define T_LENGTH 16 +#define KEK_LENGTH 16 +#define LENGTH_LENGTH 1 +#define ALGORITHM_LENGTH 1 +#define FLAGS_LENGTH 1 + +/* ICV | T' | LEN | ALG | KEY' */ +#define ICV_OFFSET 0 +#define T_PRIME_OFFSET (ICV_OFFSET + ICV_LENGTH) +#define LENGTH_OFFSET (T_PRIME_OFFSET + T_LENGTH) +#define ALGORITHM_OFFSET (LENGTH_OFFSET + LENGTH_LENGTH) +#define FLAGS_OFFSET (ALGORITHM_OFFSET + ALGORITHM_LENGTH) +#define KEY_PRIME_OFFSET (FLAGS_OFFSET + FLAGS_LENGTH) +#define FLAGS_SW_KEY 0x01 + +/* + * For testing of the algorithm implementation,, the DO_REPEATABLE_WRAP flag + * causes the T_block to go into the T field during a wrap operation. This + * will make the black key value repeatable (for a given SCC secret key, or + * always if the default key is in use). + * + * Normally, a random sequence is used. + */ +#ifdef DO_REPEATABLE_WRAP +/*! + * Block of zeroes which is maximum Symmetric block size, used for + * initializing context register, etc. + */ +static uint8_t T_block_[16] = { + 0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42, + 0x42, 0, 0, 0x42, 0x42, 0, 0, 0x42 +}; +#endif + +/*! + * Insert descriptors to calculate ICV = HMAC(key=T, data=LEN|ALG|KEY') + * + * @param user_ctx User's context for this operation + * @param desc_chain Descriptor chain to append to + * @param t_key_info T's key object + * @param black_key Beginning of Black Key region + * @param key_length Number of bytes of key' there are in @c black_key + * @param[out] hmac Location to store ICV. Will be tagged "USES" so + * sf routines will not try to free it. + * + * @return A return code of type #fsl_shw_return_t. + */ +static inline fsl_shw_return_t create_icv_calc(fsl_shw_uco_t * user_ctx, + sah_Head_Desc ** desc_chain, + fsl_shw_sko_t * t_key_info, + const uint8_t * black_key, + uint32_t key_length, + uint8_t * hmac) +{ + fsl_shw_return_t sah_code; + uint32_t header; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + /* Load up T as key for the HMAC */ + header = (SAH_HDR_MDHA_SET_MODE_MD_KEY /* #6 */ + ^ sah_insert_mdha_algorithm_sha256 + ^ sah_insert_mdha_init ^ sah_insert_mdha_hmac ^ + sah_insert_mdha_pdata ^ sah_insert_mdha_mac_full); + sah_code = sah_add_in_key_desc(header, NULL, 0, t_key_info, /* Reference T in RED */ + user_ctx->mem_util, desc_chain); + if (sah_code != FSL_RETURN_OK_S) { + goto out; + } + + /* Previous step loaded key; Now set up to hash the data */ + header = SAH_HDR_MDHA_HASH; /* #10 */ + + /* Input - start with ownerid */ + sah_code = sah_Create_Link(user_ctx->mem_util, &link1, + (void *)&t_key_info->userid, + sizeof(t_key_info->userid), + SAH_USES_LINK_DATA); + if (sah_code != FSL_RETURN_OK_S) { + goto out; + } + + /* Still input - Append black-key fields len, alg, key' */ + sah_code = sah_Append_Link(user_ctx->mem_util, link1, + (void *)black_key + LENGTH_OFFSET, + (LENGTH_LENGTH + + ALGORITHM_LENGTH + + key_length), SAH_USES_LINK_DATA); + + if (sah_code != FSL_RETURN_OK_S) { + goto out; + } + /* Output - computed ICV/HMAC */ + sah_code = sah_Create_Link(user_ctx->mem_util, &link2, + hmac, ICV_LENGTH, + SAH_USES_LINK_DATA | SAH_OUTPUT_LINK); + if (sah_code != FSL_RETURN_OK_S) { + goto out; + } + + sah_code = sah_Append_Desc(user_ctx->mem_util, desc_chain, + header, link1, link2); + + out: + if (sah_code != FSL_RETURN_OK_S) { + (void)sah_Destroy_Link(user_ctx->mem_util, link1); + (void)sah_Destroy_Link(user_ctx->mem_util, link2); + } + + return sah_code; +} /* create_icv_calc */ + +/*! + * Perform unwrapping of a black key into a RED slot + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be unwrapped... key length, slot info, etc. + * @param black_key Encrypted key + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t unwrap(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + const uint8_t * black_key) +{ + SAH_SF_DCLS; + uint8_t *hmac = NULL; + fsl_shw_sko_t t_key_info; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + unsigned i; + unsigned rounded_key_length; + unsigned original_key_length = key_info->key_length; + + hmac = DESC_TEMP_ALLOC(ICV_LENGTH); + + /* Set up key_info for "T" - use same slot as eventual key */ + fsl_shw_sko_init(&t_key_info, FSL_KEY_ALG_AES); + t_key_info.userid = key_info->userid; + t_key_info.handle = key_info->handle; + t_key_info.flags = key_info->flags; + t_key_info.key_length = T_LENGTH; + t_key_info.keystore = key_info->keystore; + + /* Validate SW flags to prevent misuse */ + if ((key_info->flags & FSL_SKO_KEY_SW_KEY) + && !(black_key[FLAGS_OFFSET] & FLAGS_SW_KEY)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + /* Compute T = SLID_decrypt(T'); leave in RED slot */ + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_decrypt(user_ctx, + key_info->userid, + t_key_info.handle, + T_LENGTH, + black_key + T_PRIME_OFFSET); + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_decrypt(user_ctx, + key_info->keystore, + key_info->userid, + t_key_info.handle, + T_LENGTH, + black_key + T_PRIME_OFFSET); + } + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Compute ICV = HMAC(T, ownerid | len | alg | key' */ + ret = create_icv_calc(user_ctx, &desc_chain, &t_key_info, + black_key, original_key_length, hmac); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creation of sah_Key_Link failed due to bad key" + " flag!\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Validating MAC of wrapped key"); +#endif + SAH_SF_EXECUTE(); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + SAH_SF_DESC_CLEAN(); + + /* Check computed ICV against value in Black Key */ + for (i = 0; i < ICV_LENGTH; i++) { + if (black_key[ICV_OFFSET + i] != hmac[i]) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS("computed ICV fails at offset %i\n", i); + + { + char buff[300]; + int a; + for (a = 0; a < ICV_LENGTH; a++) + sprintf(&(buff[a * 2]), "%02x", + black_key[ICV_OFFSET + a]); + buff[a * 2 + 1] = 0; + LOG_DIAG_ARGS("black key: %s", buff); + + for (a = 0; a < ICV_LENGTH; a++) + sprintf(&(buff[a * 2]), "%02x", + hmac[a]); + buff[a * 2 + 1] = 0; + LOG_DIAG_ARGS("hmac: %s", buff); + } +#endif + ret = FSL_RETURN_AUTH_FAILED_S; + goto out; + } + } + + /* This is no longer needed. */ + DESC_TEMP_FREE(hmac); + + /* Compute KEK = SHA256(T | ownerid). Rewrite slot with value */ + header = (SAH_HDR_MDHA_SET_MODE_HASH /* #8 */ + ^ sah_insert_mdha_init + ^ sah_insert_mdha_algorithm_sha256 ^ sah_insert_mdha_pdata); + + /* Input - Start with T */ + ret = sah_Create_Key_Link(user_ctx->mem_util, &link1, &t_key_info); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Still input - append ownerid */ + ret = sah_Append_Link(user_ctx->mem_util, link1, + (void *)&key_info->userid, + sizeof(key_info->userid), SAH_USES_LINK_DATA); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Output - KEK goes into RED slot */ + ret = sah_Create_Key_Link(user_ctx->mem_util, &link2, &t_key_info); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Put the Hash calculation into the chain. */ + ret = sah_Append_Desc(user_ctx->mem_util, &desc_chain, + header, link1, link2); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Compute KEY = AES-decrypt(KEK, KEY') */ + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY /* #1 */ + ^ sah_insert_skha_mode_ctr + ^ sah_insert_skha_algorithm_aes + ^ sah_insert_skha_modulus_128); + /* Load KEK in as the key to use */ + DESC_IN_KEY(header, 0, NULL, &t_key_info); + + rounded_key_length = ROUND_LENGTH(original_key_length); + key_info->key_length = rounded_key_length; + + /* Now set up for computation. Result in RED */ + header = SAH_HDR_SKHA_ENC_DEC; /* #4 */ + DESC_IN_KEY(header, rounded_key_length, black_key + KEY_PRIME_OFFSET, + key_info); + + /* Perform the operation */ +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Decrypting key with KEK"); +#endif + SAH_SF_EXECUTE(); + + out: + key_info->key_length = original_key_length; + SAH_SF_DESC_CLEAN(); + + DESC_TEMP_FREE(hmac); + + /* Erase tracks */ + t_key_info.userid = 0xdeadbeef; + t_key_info.handle = 0xdeadbeef; + + return ret; +} /* unwrap */ + +/*! + * Perform wrapping of a black key from a RED slot + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be wrapped... key length, slot info, etc. + * @param black_key Place to store encrypted key + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t wrap(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * black_key) +{ + SAH_SF_DCLS; + unsigned slots_allocated = 0; /* boolean */ + fsl_shw_sko_t T_key_info; /* for holding T */ + fsl_shw_sko_t KEK_key_info; /* for holding KEK */ + unsigned original_key_length = key_info->key_length; + unsigned rounded_key_length; + sah_Link *link1; + sah_Link *link2; + + black_key[LENGTH_OFFSET] = key_info->key_length; + black_key[ALGORITHM_OFFSET] = key_info->algorithm; + + memcpy(&T_key_info, key_info, sizeof(T_key_info)); + fsl_shw_sko_set_key_length(&T_key_info, T_LENGTH); + T_key_info.algorithm = FSL_KEY_ALG_HMAC; + + memcpy(&KEK_key_info, &T_key_info, sizeof(KEK_key_info)); + KEK_key_info.algorithm = FSL_KEY_ALG_AES; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_alloc(user_ctx, + T_LENGTH, key_info->userid, + &T_key_info.handle); + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_alloc(key_info->keystore, + T_LENGTH, + key_info->userid, &T_key_info.handle); + } + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_alloc(user_ctx, + KEK_LENGTH, key_info->userid, + &KEK_key_info.handle); + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_alloc(key_info->keystore, + KEK_LENGTH, key_info->userid, + &KEK_key_info.handle); + } + + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("do_scc_slot_alloc() failed"); +#endif + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + (void)do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, T_key_info.handle); + + } else { + /* Key goes in user keystore */ + (void)keystore_slot_dealloc(key_info->keystore, + key_info->userid, T_key_info.handle); + } + } else { + slots_allocated = 1; + } + + /* Set up to compute everything except T' ... */ +#ifndef DO_REPEATABLE_WRAP + /* Compute T = RND() */ + header = SAH_HDR_RNG_GENERATE; /* Desc. #18 */ + DESC_KEY_OUT(header, &T_key_info, 0, NULL); +#else + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_load(user_ctx, + T_key_info.userid, + T_key_info.handle, T_block, + T_key_info.key_length); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_load(key_info->keystore, + T_key_info.userid, + T_key_info.handle, + T_block, T_key_info.key_length); + } + + if (ret != FSL_RETURN_OK_S) { + goto out; + } +#endif + + /* Compute KEK = SHA256(T | Ownerid) */ + header = (SAH_HDR_MDHA_SET_MODE_HASH /* #8 */ + ^ sah_insert_mdha_init + ^ sah_insert_mdha_algorithm[FSL_HASH_ALG_SHA256] + ^ sah_insert_mdha_pdata); + /* Input - Start with T */ + ret = sah_Create_Key_Link(user_ctx->mem_util, &link1, &T_key_info); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + /* Still input - append ownerid */ + ret = sah_Append_Link(user_ctx->mem_util, link1, + (void *)&key_info->userid, + sizeof(key_info->userid), SAH_USES_LINK_DATA); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + /* Output - KEK goes into RED slot */ + ret = sah_Create_Key_Link(user_ctx->mem_util, &link2, &KEK_key_info); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + /* Put the Hash calculation into the chain. */ + ret = sah_Append_Desc(user_ctx->mem_util, &desc_chain, + header, link1, link2); + if (ret != FSL_RETURN_OK_S) { + goto out; + } +#if defined(NEED_CTR_WORKAROUND) + rounded_key_length = ROUND_LENGTH(original_key_length); + key_info->key_length = rounded_key_length; +#else + rounded_key_length = original_key_length; +#endif + /* Compute KEY' = AES-encrypt(KEK, KEY) */ + header = (SAH_HDR_SKHA_SET_MODE_IV_KEY /* #1 */ + ^ sah_insert_skha_mode[FSL_SYM_MODE_CTR] + ^ sah_insert_skha_algorithm[FSL_KEY_ALG_AES] + ^ sah_insert_skha_modulus[FSL_CTR_MOD_128]); + /* Set up KEK as key to use */ + DESC_IN_KEY(header, 0, NULL, &KEK_key_info); + header = SAH_HDR_SKHA_ENC_DEC; + DESC_KEY_OUT(header, key_info, + key_info->key_length, black_key + KEY_PRIME_OFFSET); + + /* Set up flags info */ + black_key[FLAGS_OFFSET] = 0; + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + black_key[FLAGS_OFFSET] |= FLAGS_SW_KEY; + } + + /* Compute and store ICV into Black Key */ + ret = create_icv_calc(user_ctx, &desc_chain, &T_key_info, + black_key, original_key_length, + black_key + ICV_OFFSET); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creation of sah_Key_Link failed due to bad key" + " flag!\n"); +#endif /*DIAG_SECURITY_FUNC */ + goto out; + } + + /* Now get Sahara to do the work. */ +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Encrypting key with KEK"); +#endif + SAH_SF_EXECUTE(); + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("sah_Descriptor_Chain_Execute() failed"); +#endif + goto out; + } + + /* Compute T' = SLID_encrypt(T); Result goes to Black Key */ + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_encrypt(user_ctx, + T_key_info.userid, T_key_info.handle, + T_LENGTH, black_key + T_PRIME_OFFSET); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_encrypt(user_ctx, + key_info->keystore, + T_key_info.userid, + T_key_info.handle, + T_LENGTH, + black_key + T_PRIME_OFFSET); + } + + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("do_scc_slot_encrypt() failed"); +#endif + goto out; + } + + out: + key_info->key_length = original_key_length; + + SAH_SF_DESC_CLEAN(); + if (slots_allocated) { + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + (void)do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + T_key_info. + handle); + (void)do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + KEK_key_info. + handle); + } else { + /* Key goes in user keystore */ + (void)keystore_slot_dealloc(key_info->keystore, + key_info->userid, + T_key_info.handle); + (void)keystore_slot_dealloc(key_info->keystore, + key_info->userid, + KEK_key_info.handle); + } + } + + return ret; +} /* wrap */ + +/*! + * Place a key into a protected location for use only by cryptographic + * algorithms. + * + * This only needs to be used to a) unwrap a key, or b) set up a key which + * could be wrapped with a later call to #fsl_shw_extract_key(). Normal + * cleartext keys can simply be placed into #fsl_shw_sko_t key objects with + * #fsl_shw_sko_set_key() and used directly. + * + * The maximum key size supported for wrapped/unwrapped keys is 32 octets. + * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC + * key based on SHA-256.) The key size is determined by the @a key_info. The + * expected length of @a key can be determined by + * #fsl_shw_sko_calculate_wrapped_size() + * + * The protected key will not be available for use until this operation + * successfully completes. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be established. In the create case, the key + * length must be set. + * @param establish_type How @a key will be interpreted to establish a + * key for use. + * @param key If @a establish_type is #FSL_KEY_WRAP_UNWRAP, + * this is the location of a wrapped key. If + * @a establish_type is #FSL_KEY_WRAP_CREATE, this + * parameter can be @a NULL. If @a establish_type + * is #FSL_KEY_WRAP_ACCEPT, this is the location + * of a plaintext key. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key) +{ + SAH_SF_DCLS; + unsigned original_key_length = key_info->key_length; + unsigned rounded_key_length; + unsigned slot_allocated = 0; + uint32_t old_flags; + + header = SAH_HDR_RNG_GENERATE; /* Desc. #18 for rand */ + + /* TODO: THIS STILL NEEDS TO BE REFACTORED */ + + /* Write operations into SCC memory require word-multiple number of + * bytes. For ACCEPT and CREATE functions, the key length may need + * to be rounded up. Calculate. */ + if (LENGTH_PATCH && (original_key_length & LENGTH_PATCH_MASK) != 0) { + rounded_key_length = original_key_length + LENGTH_PATCH + - (original_key_length & LENGTH_PATCH_MASK); + } else { + rounded_key_length = original_key_length; + } + + SAH_SF_USER_CHECK(); + + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { +#ifdef DIAG_SECURITY_FUNC + ret = FSL_RETURN_BAD_FLAG_S; + LOG_DIAG("Key already established\n"); +#endif + } + + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_alloc(user_ctx, + key_info->key_length, + key_info->userid, + &(key_info->handle)); +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG_ARGS + ("key length: %i, handle: %i, rounded key length: %i", + key_info->key_length, key_info->handle, + rounded_key_length); +#endif + + } else { + /* Key goes in user keystore */ + ret = keystore_slot_alloc(key_info->keystore, + key_info->key_length, + key_info->userid, + &(key_info->handle)); + } + if (ret != FSL_RETURN_OK_S) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Slot allocation failed\n"); +#endif + goto out; + } + slot_allocated = 1; + + key_info->flags |= FSL_SKO_KEY_ESTABLISHED; + switch (establish_type) { + case FSL_KEY_WRAP_CREATE: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creating random key\n"); +#endif + /* Use safe version of key length */ + key_info->key_length = rounded_key_length; + /* Generate descriptor to put random value into */ + DESC_KEY_OUT(header, key_info, 0, NULL); + /* Restore actual, desired key length */ + key_info->key_length = original_key_length; + + old_flags = user_ctx->flags; + /* Now put random value into key */ + SAH_SF_EXECUTE(); + /* Restore user's old flag value */ + user_ctx->flags = old_flags; +#ifdef DIAG_SECURITY_FUNC + if (ret == FSL_RETURN_OK_S) { + LOG_DIAG("ret is ok"); + } else { + LOG_DIAG("ret is not ok"); + } +#endif + break; + + case FSL_KEY_WRAP_ACCEPT: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Accepting plaintext key\n"); +#endif + if (key == NULL) { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("ACCEPT: Red Key is NULL"); +#endif + ret = FSL_RETURN_ERROR_S; + goto out; + } + /* Copy in safe number of bytes of Red key */ + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_load(user_ctx, + key_info->userid, + key_info->handle, key, + rounded_key_length); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_load(key_info->keystore, + key_info->userid, + key_info->handle, key, + key_info->key_length); + } + break; + + case FSL_KEY_WRAP_UNWRAP: +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Unwrapping wrapped key\n"); +#endif + /* For now, disallow non-blocking calls. */ + if (!(user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { + ret = FSL_RETURN_BAD_FLAG_S; + } else if (key == NULL) { + ret = FSL_RETURN_ERROR_S; + } else { + ret = unwrap(user_ctx, key_info, key); + } + break; + + default: + ret = FSL_RETURN_BAD_FLAG_S; + break; + } /* switch */ + + out: + if (slot_allocated && (ret != FSL_RETURN_OK_S)) { + fsl_shw_return_t scc_err; + + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + scc_err = do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + key_info->handle); + } else { + /* Key goes in user keystore */ + scc_err = keystore_slot_dealloc(key_info->keystore, + key_info->userid, key_info->handle); + } + + key_info->flags &= ~FSL_SKO_KEY_ESTABLISHED; + } + + SAH_SF_DESC_CLEAN(); + + return ret; +} /* fsl_shw_establish_key() */ + +/*! + * Wrap a key and retrieve the wrapped value. + * + * A wrapped key is a key that has been cryptographically obscured. It is + * only able to be used with #fsl_shw_establish_key(). + * + * This function will also release the key (see #fsl_shw_release_key()) so + * that it must be re-established before reuse. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * @param[out] covered_key The location to store the 48-octet wrapped key. + * (This size is based upon the maximum key size + * of 32 octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + /* For now, only blocking mode calls are supported */ + if (user_ctx->flags & FSL_UCO_BLOCKING_MODE) { + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + ret = wrap(user_ctx, key_info, covered_key); + if (ret != FSL_RETURN_OK_S) { + goto out; + } + + /* Verify that a SW key info really belongs to a SW key */ + if (key_info->flags & FSL_SKO_KEY_SW_KEY) { + /* ret = FSL_RETURN_BAD_FLAG_S; + goto out;*/ + } + + /* Need to deallocate on successful extraction */ + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + ret = do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, key_info->handle); + } else { + /* Key goes in user keystore */ + ret = keystore_slot_dealloc(key_info->keystore, + key_info->userid, key_info->handle); + } + /* Mark key not available in the flags */ + key_info->flags &= + ~(FSL_SKO_KEY_ESTABLISHED | FSL_SKO_KEY_PRESENT); + } + } + +out: + SAH_SF_DESC_CLEAN(); + + return ret; +} + +/*! + * De-establish a key so that it can no longer be accessed. + * + * The key will need to be re-established before it can again be used. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + if (key_info->keystore == NULL) { + /* Key goes in system keystore */ + do_system_keystore_slot_dealloc(user_ctx, + key_info->userid, + key_info->handle); + } else { + /* Key goes in user keystore */ + keystore_slot_dealloc(key_info->keystore, + key_info->userid, + key_info->handle); + } + key_info->flags &= ~(FSL_SKO_KEY_ESTABLISHED | + FSL_SKO_KEY_PRESENT); + } + +out: + SAH_SF_DESC_CLEAN(); + + return ret; +} + +fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, uint8_t * key) +{ + SAH_SF_DCLS; + + SAH_SF_USER_CHECK(); + + if (!(key_info->flags & FSL_SKO_KEY_ESTABLISHED) + || !(key_info->flags & FSL_SKO_KEY_SW_KEY)) { + ret = FSL_RETURN_BAD_FLAG_S; + goto out; + } + + if (key_info->keystore == NULL) { + /* Key lives in system keystore */ + ret = do_system_keystore_slot_read(user_ctx, + key_info->userid, + key_info->handle, + key_info->key_length, key); + } else { + /* Key lives in user keystore */ + ret = keystore_slot_read(key_info->keystore, + key_info->userid, + key_info->handle, + key_info->key_length, key); + } + + out: + SAH_SF_DESC_CLEAN(); + + return ret; +} diff --git a/drivers/mxc/security/sahara2/include/adaptor.h b/drivers/mxc/security/sahara2/include/adaptor.h new file mode 100644 index 000000000000..4c2d2bd7b688 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/adaptor.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file adaptor.h +* +* @brief The Adaptor component provides an interface to the device +* driver. +* +* Intended to be used by the FSL SHW API, this can also be called directly +*/ + +#ifndef ADAPTOR_H +#define ADAPTOR_H + +#include + +/*! + * Structure passed during user ioctl() call to submit request. + */ +typedef struct sah_dar { + sah_Desc *desc_addr; /*!< head of descriptor chain */ + uint32_t uco_flags; /*!< copy of fsl_shw_uco flags field */ + uint32_t uco_user_ref; /*!< copy of fsl_shw_uco user_ref */ + uint32_t result; /*!< result of descriptor chain request */ + struct sah_dar *next; /*!< for driver use */ +} sah_dar_t; + +/*! + * Structure passed during user ioctl() call to Register a user + */ +typedef struct sah_register { + uint32_t pool_size; /*!< max number of outstanding requests possible */ + uint32_t result; /*!< result of registration request */ +} sah_register_t; + +/*! + * Structure passed during ioctl() call to request SCC operation + */ +typedef struct scc_data { + uint32_t length; /*!< length of data */ + uint8_t *in; /*!< input data */ + uint8_t *out; /*!< output data */ + unsigned direction; /*!< encrypt or decrypt */ + fsl_shw_sym_mode_t crypto_mode; /*!< CBC or EBC */ + uint8_t *init_vector; /*!< initialization vector or NULL */ +} scc_data_t; + +/*! + * Structure passed during user ioctl() calls to manage stored keys and + * stored-key slots. + */ +typedef struct scc_slot_t { + uint64_t ownerid; /*!< Owner's id to check/set permissions */ + uint32_t key_length; /*!< Length of key */ + uint32_t slot; /*!< Slot to operation on, or returned slot + number. */ + uint8_t *key; /*!< User-memory pointer to key value */ + fsl_shw_return_t code; /*!< API return code from operation */ +} scc_slot_t; + +/* + * Structure passed during user ioctl() calls to manage data stored in secure + * partitions. + */ +typedef struct scc_region_t { + uint32_t partition_base; /*!< User virtual address of the + partition base. */ + uint32_t offset; /*!< Offset from the start of the + partition where the cleartext data + is located. */ + uint32_t length; /*!< Length of the region to be + operated on */ + uint8_t *black_data; /*!< User virtual address of any black + (encrypted) data. */ + fsl_shw_cypher_mode_t cypher_mode; /*!< Cypher mode to use in an encryt/ + decrypt operation. */ + uint32_t IV[4]; /*!< Intialization vector to use in an + encrypt/decrypt operation. */ + fsl_shw_return_t code; /*!< API return code from operation */ +} scc_region_t; + +/* + * Structure passed during user ioctl() calls to manage secure partitions. + */ +typedef struct scc_partition_info_t { + uint32_t user_base; /**< Userspace pointer to base of partition */ + uint32_t permissions; /**< Permissions to give the partition (only + used in call to _DROP_PERMS) */ + fsl_shw_partition_status_t status; /*!< Status of the partition */ +} scc_partition_info_t; + +fsl_shw_return_t adaptor_Exec_Descriptor_Chain(sah_Head_Desc * dar, + fsl_shw_uco_t * uco); +fsl_shw_return_t sah_get_results(sah_results * arg, fsl_shw_uco_t * uco); +fsl_shw_return_t sah_register(fsl_shw_uco_t * user_ctx); +fsl_shw_return_t sah_deregister(fsl_shw_uco_t * user_ctx); +fsl_shw_return_t get_capabilities(fsl_shw_uco_t * user_ctx, + fsl_shw_pco_t *capabilities); + +#endif /* ADAPTOR_H */ + +/* End of adaptor.h */ diff --git a/drivers/mxc/security/sahara2/include/diagnostic.h b/drivers/mxc/security/sahara2/include/diagnostic.h new file mode 100644 index 000000000000..94db9bfe3a8a --- /dev/null +++ b/drivers/mxc/security/sahara2/include/diagnostic.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file diagnostic.h +* +* @brief Macros for outputting kernel and user space diagnostics. +*/ + +#ifndef DIAGNOSTIC_H +#define DIAGNOSTIC_H + +#ifndef __KERNEL__ /* linux flag */ +#include +#endif +#include "fsl_platform.h" + +#if defined(FSL_HAVE_SAHARA2) || defined(FSL_HAVE_SAHARA4) +#define DEV_NAME "sahara" +#elif defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) || \ + defined(FSL_HAVE_RNGC) +#define DEV_NAME "shw" +#endif + +/*! +******************************************************************** +* @brief This macro logs diagnostic messages to stderr. +* +* @param diag String that must be logged, char *. +* +* @return void +* +*/ +//#if defined DIAG_SECURITY_FUNC || defined DIAG_ADAPTOR +#define LOG_DIAG(diag) \ +({ \ + const char* fname = strrchr(__FILE__, '/'); \ + \ + sah_Log_Diag(fname ? fname+1 : __FILE__, __LINE__, diag); \ +}) + +#ifdef __KERNEL__ + +#define LOG_DIAG_ARGS(fmt, ...) \ +({ \ + const char* fname = strrchr(__FILE__, '/'); \ + os_printk(KERN_ALERT "%s:%i: " fmt "\n", \ + fname ? fname+1 : __FILE__, \ + __LINE__, \ + __VA_ARGS__); \ +}) + +#else + +#define LOG_DIAG_ARGS(fmt, ...) \ +({ \ + const char* fname = strrchr(__FILE__, '/'); \ + printf("%s:%i: " fmt "\n", \ + fname ? fname+1 : __FILE__, \ + __LINE__, \ + __VA_ARGS__); \ +}) + +#ifndef __KERNEL__ +void sah_Log_Diag(char *source_name, int source_line, char *diag); +#endif +#endif /* if define DIAG_SECURITY_FUNC ... */ + +#ifdef __KERNEL__ +/*! +******************************************************************** +* @brief This macro logs kernel diagnostic messages to the kernel +* log. +* +* @param diag String that must be logged, char *. +* +* @return As for printf() +*/ +#if 0 +#if defined(DIAG_DRV_IF) || defined(DIAG_DRV_QUEUE) || \ + defined(DIAG_DRV_STATUS) || defined(DIAG_DRV_INTERRUPT) || \ + defined(DIAG_MEM) || defined(DIAG_SECURITY_FUNC) || defined(DIAG_ADAPTOR) +#endif +#endif + +#define LOG_KDIAG_ARGS(fmt, ...) \ +({ \ + os_printk (KERN_ALERT "%s (%s:%i): " fmt "\n", \ + DEV_NAME, strrchr(__FILE__, '/')+1, __LINE__, __VA_ARGS__); \ +}) + +#define LOG_KDIAG(diag) \ + os_printk (KERN_ALERT "%s (%s:%i): %s\n", \ + DEV_NAME, strrchr(__FILE__, '/')+1, __LINE__, diag); + +#define sah_Log_Diag(n, l, d) \ + os_printk(KERN_ALERT "%s:%i: %s\n", n, l, d) + +#else /* not KERNEL */ + +#define sah_Log_Diag(n, l, d) \ + printf("%s:%i: %s\n", n, l, d) + +#endif /* __KERNEL__ */ + +#endif /* DIAGNOSTIC_H */ diff --git a/drivers/mxc/security/sahara2/include/fsl_platform.h b/drivers/mxc/security/sahara2/include/fsl_platform.h new file mode 100644 index 000000000000..b55bd6cd9a5e --- /dev/null +++ b/drivers/mxc/security/sahara2/include/fsl_platform.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file fsl_platform.h + * + * Header file to isolate code which might be platform-dependent + */ + +#ifndef FSL_PLATFORM_H +#define FSL_PLATFORM_H + +#ifdef __KERNEL__ +#include "portable_os.h" +#endif + +#if defined(FSL_PLATFORM_OTHER) + +/* Have Makefile or other method of setting FSL_HAVE_* flags */ + +#elif defined(CONFIG_ARCH_MX3) /* i.MX31 */ + +#define FSL_HAVE_SCC +#define FSL_HAVE_RTIC +#define FSL_HAVE_RNGA + +#elif defined(CONFIG_ARCH_MX21) + +#define FSL_HAVE_HAC +#define FSL_HAVE_RNGA +#define FSL_HAVE_SCC + +#elif defined(CONFIG_ARCH_MX25) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGB +#define FSL_HAVE_RTIC3 +#define FSL_HAVE_DRYICE + +#elif defined(CONFIG_ARCH_MX27) + +#define FSL_HAVE_SAHARA2 +#define SUBMIT_MULTIPLE_DARS +#define FSL_HAVE_RTIC +#define FSL_HAVE_SCC +#define ALLOW_LLO_DESCRIPTORS + +#elif defined(CONFIG_ARCH_MX35) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGC +#define FSL_HAVE_RTIC + +#elif defined(CONFIG_ARCH_MX37) + +#define FSL_HAVE_SCC2 +#define FSL_HAVE_RNGC +#define FSL_HAVE_RTIC2 +#define FSL_HAVE_SRTC + +#elif defined(CONFIG_ARCH_MX5) + +#define FSL_HAVE_SCC2 +#define FSL_HAVE_SAHARA4 +#define FSL_HAVE_RTIC3 +#define FSL_HAVE_SRTC +#define NO_RESEED_WORKAROUND +#define NEED_CTR_WORKAROUND +#define USE_S2_CCM_ENCRYPT_CHAIN +#define USE_S2_CCM_DECRYPT_CHAIN +#define ALLOW_LLO_DESCRIPTORS + +#elif defined(CONFIG_ARCH_MXC91131) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGC +#define FSL_HAVE_HAC + +#elif defined(CONFIG_ARCH_MXC91221) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGC +#define FSL_HAVE_RTIC2 + +#elif defined(CONFIG_ARCH_MXC91231) + +#define FSL_HAVE_SAHARA2 +#define FSL_HAVE_RTIC +#define FSL_HAVE_SCC +#define NO_OUTPUT_1K_CROSSING + +#elif defined(CONFIG_ARCH_MXC91311) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGC + +#elif defined(CONFIG_ARCH_MXC91314) + +#define FSL_HAVE_SCC +#define FSL_HAVE_SAHAR4 +#define FSL_HAVE_RTIC3 +#define NO_RESEED_WORKAROUND +#define NEED_CTR_WORKAROUND +#define USE_S2_CCM_ENCRYPT_CHAIN +#define USE_S2_CCM_DECRYPT_CHAIN +#define ALLOW_LLO_DESCRIPTORS + +#elif defined(CONFIG_ARCH_MXC91321) + +#define FSL_HAVE_SAHARA2 +#define FSL_HAVE_RTIC +#define FSL_HAVE_SCC +#define SCC_CLOCK_NOT_GATED +#define NO_OUTPUT_1K_CROSSING + +#elif defined(CONFIG_ARCH_MXC92323) + +#define FSL_HAVE_SCC2 +#define FSL_HAVE_SAHARA4 +#define FSL_HAVE_PKHA +#define FSL_HAVE_RTIC2 +#define NO_1K_CROSSING +#define NO_RESEED_WORKAROUND +#define NEED_CTR_WORKAROUND +#define USE_S2_CCM_ENCRYPT_CHAIN +#define USE_S2_CCM_DECRYPT_CHAIN +#define ALLOW_LLO_DESCRIPTORS + + +#elif defined(CONFIG_ARCH_MXC91331) + +#define FSL_HAVE_SCC +#define FSL_HAVE_RNGA +#define FSL_HAVE_HAC +#define FSL_HAVE_RTIC + +#elif defined(CONFIG_8548) + +#define FSL_HAVE_SEC2x + +#elif defined(CONFIG_MPC8374) + +#define FSL_HAVE_SEC3x + +#else + +#error UNKNOWN_PLATFORM + +#endif /* platform checks */ + +#endif /* FSL_PLATFORM_H */ diff --git a/drivers/mxc/security/sahara2/include/fsl_shw.h b/drivers/mxc/security/sahara2/include/fsl_shw.h new file mode 100644 index 000000000000..a52d420c721e --- /dev/null +++ b/drivers/mxc/security/sahara2/include/fsl_shw.h @@ -0,0 +1,2515 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * NOTE TO MAINTAINERS: Although this header file is *the* header file to be + * #include'd by FSL SHW programs, it does not itself make any definitions for + * the API. Instead, it uses the fsl_platform.h file and / or compiler + * environment variables to determine which actual driver header file to + * include. This allows different implementations to contain different + * implementations of the various objects, macros, etc., or even to change + * which functions are macros and which are not. + */ + +/*! + * @file fsl_shw.h + * + * @brief Definition of the Freescale Security Hardware API. + * + * See @ref index for an overview of the API. + */ + +/*! + * @if USE_MAINPAGE + * @mainpage Common API for Freescale Security Hardware (FSL SHW API) + * @endif + * + * @section intro_sec Introduction + * + * This is the interface definition for the Freescale Security Hardware API + * (FSL SHW API) for User Mode and Kernel Mode to access Freescale Security + * Hardware components for cryptographic acceleration. The API is intended to + * provide cross-platform access to security hardware components of Freescale. + * + * This documentation has not been approved, and should not be taken to + * mean anything definite about future direction. + * + * Some example code is provided to give some idea of usage of this API. + * + * Note: This first version has been defined around the capabilities of the + * Sahara2 cryptographic accelerator, and may be expanded in the future to + * provide support for other platforms. The Platform Capabilities Object is + * intended as a way to allow programs to adapt to different platforms. + * + * The i.MX25 is an example of a platform without a SAHARA but yet has + * capabilities supported by this API. These include #fsl_shw_get_random() and + * #fsl_shw_add_entropy(), and the use of Triple-DES (TDEA) cipher algorithm + * (with no checking of key parity supported) in ECB and CBC modes with @ref + * sym_sec. See also the @ref di_sec for information on key handling, and @ref + * td_sec for detection of Tamper Events. Only the random functions are + * available from user space on this platform. + * + * @section usr_ctx The User Context + * + * The User Context Object (#fsl_shw_uco_t) controls the interaction between + * the user program and the API. It is initialized as part of user + * registration (#fsl_shw_register_user()), and is part of every interaction + * thereafter. + * + * @section pf_sec Platform Capabilities + * + * Since this API is not tied to one specific type of hardware or even one + * given version of a given type of hardware, the platform capabilities object + * could be used by a portable program to make choices about using software + * instead of hardware for certain operations. + * + * See the #fsl_shw_pco_t, returned by #fsl_shw_get_capabilities(). + * + * @ref pcoops are provided to query its contents. + * + * + * @section sym_sec Symmetric-Key Encryption and Decryption + * + * Symmetric-Key encryption support is provided for the block cipher algorithms + * AES, DES, and Triple DES. Modes supported are #FSL_SYM_MODE_ECB, + * #FSL_SYM_MODE_CBC, and #FSL_SYM_MODE_CTR, though not necessarily all modes + * for all algorithms. There is also support for the stream cipher algorithm + * commonly known as ARC4. + * + * Encryption and decryption are performed by using the functions + * #fsl_shw_symmetric_encrypt() and #fsl_shw_symmetric_decrypt(), respectively. + * There are two objects which provide information about the operation of these + * functions. They are the #fsl_shw_sko_t, to provide key and algorithm + * information; and the #fsl_shw_scco_t, to provide (and store) initial context + * or counter value information. + * + * CCM is not supported by these functions. For information CCM support, see + * @ref cmb_sec. + * + * + * @section hash_sec Cryptographic Hashing + * + * Hashing is performed by fsl_shw_hash(). Control of the function is through + * flags in the #fsl_shw_hco_t. The algorithms which are + * supported are listed in #fsl_shw_hash_alg_t. + * + * The hashing function works on octet streams. If a user application needs to + * hash a bitstream, it will need to do its own padding of the last block. + * + * + * @section hmac_sec Hashed Message Authentication Codes + * + * An HMAC is a method of combining a hash and a key so that a message cannot + * be faked by a third party. + * + * The #fsl_shw_hmac() can be used by itself for one-shot or multi-step + * operations, or in combination with #fsl_shw_hmac_precompute() to provide the + * ability to compute and save the beginning hashes from a key one time, and + * then use #fsl_shw_hmac() to calculate an HMAC on each message as it is + * processed. + * + * The maximum key length which is directly supported by this API is 64 octets. + * If a longer key size is needed for HMAC, the user will have to hash the key + * and present the digest value as the key to be used by the HMAC functions. + * + * + * @section rnd_sec Random Numbers + * + * Support is available for acquiring random values from a + * cryptographically-strong random number generator. See + * #fsl_shw_get_random(). The function #fsl_shw_add_entropy() may be used to + * add entropy to the random number generator. + * + * + * @section cmb_sec Combined Cipher and Authentication + * + * Some schemes require that messages be encrypted and that they also have an + * authentication code associated with the message. The function + * #fsl_shw_gen_encrypt() will generate the authentication code and encrypt the + * message. + * + * Upon receipt of such a message, the message must be decrypted and the + * authentication code validated. The function + * #fsl_shw_auth_decrypt() will perform these steps. + * + * Only AES-CCM is supported. + * + * + * @section wrap_sec Wrapped Keys + * + * On platforms with a Secure Memory, the function #fsl_shw_establish_key() can + * be used to place a key into the System Keystore. This key then can be used + * directly by the cryptographic hardware. It later then be wrapped + * (cryptographically obscured) by #fsl_shw_extract_key() and stored for later + * use. If a software key (#FSL_SKO_KEY_SW_KEY) was established, then its + * value can be retrieved with a call to #fsl_shw_read_key(). + * + * The wrapping and unwrapping functions provide security against unauthorized + * use and detection of tampering. + * + * The functions can also be used with a User Keystore. + * + * @section smalloc_sec Secure Memory Allocation + * + * On platforms with multiple partitions of Secure Memory, the function + * #fsl_shw_smalloc() can be used to acquire a partition for private use. The + * function #fsl_shw_diminish_perms() can then be used to revoke specific + * permissions on the partition, and #fsl_shw_sfree() can be used to release the + * partition. + * + * @section keystore_sec User Keystore + * + * User Keystore functionality is defined in fsl_shw_keystore.h. See @ref + * user_keystore for details. This is not supported on platforms without SCC2. + * + * @section di_sec Hardware key-select extensions - DryIce + * + * Some platforms have a component called DryIce which allows the software to + * control which key will be used by the secure memory encryption hardware. + * The choices are the secret per-chip Fused (IIM) Key, an unknown, hardware- + * generated Random Key, a software-written Programmed Key, or the IIM Key in + * combination with one of the others. #fsl_shw_pco_check_pk_supported() can + * be used to determine whether this feature is available on the platform. + * The rest of this section will explain the symmetric ciphering and key + * operations which are available on such a platform. + * + * The function #fsl_shw_sko_init_pf_key() will set up a Secret Key Object to + * refer to one of the system's platform keys. All keys which reference a + * platform key must use this initialization function, including a user- + * provided key value. Keys which are intended for software encryption must + * use #fsl_shw_sko_init(). + * + * To change the setting of the Programmed Key of the DryIce module, + * #fsl_shw_establish_key() must be called with a platform key object of type + * #FSL_SHW_PF_KEY_PRG or #FSL_SHW_PF_KEY_IIM_PRG. The key will be go + * into the PK register of DryIce and not to the keystore. Any symmetric + * operation which references either #FSL_SHW_PF_KEY_PRG or + * #FSL_SHW_PF_KEY_IIM_PRG will use the current PK value (possibly modified by + * the secret fused IIM key). Before the Flatform Key can be changed, a call to + * #fsl_shw_release_key() or #fsl_shw_extract_key() must be made. Neither + * function will change the value in the PK registers, and further ciphering + * can take place. + * + * When #fsl_shw_establish_key() is called to change the PK value, a plaintext + * key can be passed in with the #FSL_KEY_WRAP_ACCEPT argument or a previously + * wrapped key can be passed in with the #FSL_KEY_WRAP_UNWRAP argument. If + * #FSL_KEY_WRAP_CREATE is passed in, then a random value will be loaded into + * the PK register. The PK value can be wrapped by a call to + * #fsl_shw_extract_key() for later use with the #FSL_KEY_WRAP_UNWRAP argument. + * + * As an alternative to using only the fused key for @ref wrap_sec, + * #fsl_shw_uco_set_wrap_key() can be used to select either the random key or + * the random key with the fused key as the key which will be used to protect + * the one-time value used to wrap the key. This allows for these + * wrapped keys to be dependent upon and therefore unrecoverable after a tamper + * event causes the erasure of the DryIce Random Key register. + * + * The software can request that the hardware generate a (new) Random Key for + * DryIce by calling #fsl_shw_gen_random_pf_key(). + * + * + * @section td_sec Device Tamper-Detection + * + * Some platforms have a component which can detect certain types of tampering + * with the hardware. #fsl_shw_read_tamper_event() API will allow the + * retrieval of the type of event which caused a tamper-detection failure. + * + */ + +/*! @defgroup glossary Glossary + * + * @li @b AES - Advanced Encryption Standard - An NIST-created block cipher + * originally knowns as Rijndael. + * @li @b ARC4 - ARCFOUR - An S-Box-based OFB mode stream cipher. + * @li @b CBC - Cipher-Block Chaining - Each encrypted block is XORed with the + * result of the previous block's encryption. + * @li @b CCM - A way of combining CBC and CTR to perform cipher and + * authentication. + * @li @b ciphertext - @a plaintext which has been encrypted in some fashion. + * @li @b context - Information on the state of a cryptographic operation, + * excluding any key. This could include IV, Counter Value, or SBox. + * @li @b CTR - A mode where a counter value is encrypted and then XORed with + * the data. After each block, the counter value is incremented. + * @li @b DES - Data Encryption Standard - An 8-octet-block cipher. + * @li @b ECB - Electronic Codebook - A straight encryption/decryption of the + * data. + * @li @b hash - A cryptographically strong one-way function performed on data. + * @li @b HMAC - Hashed Message Authentication Code - A key-dependent one-way + * hash result, used to verify authenticity of a message. The equation + * for an HMAC is hash((K + A) || hash((K + B) || msg)), where K is the + * key, A is the constant for the outer hash, B is the constant for the + * inner hash, and hash is the hashing function (MD5, SHA256, etc). + * @li @b IPAD - In an HMAC operation, the context generated by XORing the key + * with a constant and then hashing that value as the first block of the + * inner hash. + * @li @b IV - An "Initial Vector" or @a context for modes like CBC. + * @li @b MAC - A Message Authentication Code. HMAC, hashing, and CCM all + * produce a MAC. + * @li @b mode - A way of using a cryptographic algorithm. See ECB, CBC, etc. + * @li @b MD5 - Message Digest 5 - A one-way hash function. + * @li @b plaintext - Data which has not been encrypted, or has been decrypted + * from @a ciphertext. + * @li @b OPAD - In an HMAC operation, the context generated by XORing the key + * with a constant and then hashing that value as the first block of the + * outer hash. + * @li @b SHA - Secure Hash Algorithm - A one-way hash function. + * @li @b TDES - AKA @b 3DES - Triple Data Encryption Standard - A method of + * using two or three keys and DES to perform three operations (encrypt + * decrypt encrypt) to create a new algorithm. + * @li @b XOR - Exclusive-OR. A Boolean arithmetic function. + * @li @b Wrapped value - A (key) which has been encrypted into an opaque datum + * which cannot be unwrapped (decrypted) for use except by an authorized + * user. Once created, the key is never visible, but may be used for + * other cryptographic operations. + */ + +#ifndef FSL_SHW_H +#define FSL_SHW_H + +/* Set FSL_HAVE_* flags */ + +#include "fsl_platform.h" + +#ifndef API_DOC + +#if defined(FSL_HAVE_SAHARA2) || defined(FSL_HAVE_SAHARA4) + +#include "sahara.h" + +#else + +#if defined(FSL_HAVE_RNGA) || defined(FSL_HAVE_RNGB) || defined(FSL_HAVE_RNGC) + +#include "rng_driver.h" + +#else + +#error FSL_SHW_API_platform_not_recognized + +#endif + +#endif /* HAVE SAHARA */ + +#else /* API_DOC */ + +#include /* for uint32_t, etc. */ +#include /* Mainly for definition of NULL !! */ + +/* These groups will appear in the order in which they are defined. */ + +/*! + * @defgroup strgrp Objects + * + * These objects are used to pass information into and out of the API. Through + * flags and other settings, they control the behavior of the @ref opfuns. + * + * They are manipulated and queried by use of the various access functions. + * There are different sets defined for each object. See @ref objman. + */ + +/*! + * @defgroup consgrp Enumerations and other Constants + * + * This collection of symbols comprise the values which can be passed into + * various functions to control how the API will work. + */ + +/*! @defgroup opfuns Operational Functions + * + * These functions request that the underlying hardware perform cryptographic + * operations. They are the heart of the API. + */ + +/****** Organization the Object Operations under one group ! **********/ +/*! @defgroup objman Object-Manipulation Operations + * + */ +/*! @addtogroup objman + @{ */ +/*! + * @defgroup pcoops Platform Context Object Operations + * + * The Platform Context object is "read-only", so only query operations are + * provided for it. It is returned by the #fsl_shw_get_capabilities() + * function. + */ + +/*! @defgroup ucoops User Context Operations + * + * These operations should be the only access to the #fsl_shw_uco_t + * type/struct, as the internal members of the object are subject to change. + * The #fsl_shw_uco_init() function must be called before any other use of the + * object. + */ + +/*! + * @defgroup rops Result Object Operations + * + * As the Result Object contains the result of one of the @ref opfuns. The + * manipulations provided are query-only. No initialization is needed for this + * object. + */ + +/*! + * @defgroup skoops Secret Key Object Operations + * + * These operations should be the only access to the #fsl_shw_sko_t + * type/struct, as the internal members of that object are subject to change. + */ + +/*! + * @defgroup ksoops Keystore Object Operations + * + * These operations should be the only access to the #fsl_shw_kso_t + * type/struct, as the internal members of that object are subject to change. + */ + +/*! + * @defgroup hcops Hash Context Object Operations + * + * These operations should be the only access to the #fsl_shw_hco_t + * type/struct, as the internal members of that object are subject to change. + */ + +/*! + * @defgroup hmcops HMAC Context Object Operations + * + * These operations should be the only access to the #fsl_shw_hmco_t + * type/struct, as the internal members of that object are subject to change. + */ + +/*! + * @defgroup sccops Symmetric Cipher Context Operations + * + * These operations should be the only access to the #fsl_shw_scco_t + * type/struct, as the internal members of that object are subject to change + */ + +/*! @defgroup accoops Authentication-Cipher Context Object Operations + * + * These functions operate on a #fsl_shw_acco_t. Their purpose is to set + * flags, fields, etc., in order to control the operation of + * #fsl_shw_gen_encrypt() and #fsl_shw_auth_decrypt(). + */ + + /* @} *//************ END GROUPING of Object Manipulations *****************/ + +/*! @defgroup miscfuns Miscellaneous Functions + * + * These functions are neither @ref opfuns nor @ref objman. Their behavior + * does not depend upon the flags in the #fsl_shw_uco_t, yet they may involve + * more interaction with the library and the kernel than simply querying an + * object. + */ + +/****************************************************************************** + * Enumerations + *****************************************************************************/ +/*! @addtogroup consgrp + @{ */ + +/*! + * Flags for the state of the User Context Object (#fsl_shw_uco_t). + * + * These flags describe how the @ref opfuns will operate. + */ +typedef enum fsl_shw_user_ctx_flags_t { + /*! + * API will block the caller until operation completes. The result will be + * available in the return code. If this is not set, user will have to get + * results using #fsl_shw_get_results(). + */ + FSL_UCO_BLOCKING_MODE, + /*! + * User wants callback (at the function specified with + * #fsl_shw_uco_set_callback()) when the operation completes. This flag is + * valid only if #FSL_UCO_BLOCKING_MODE is not set. + */ + FSL_UCO_CALLBACK_MODE, + /*! Do not free descriptor chain after driver (adaptor) finishes */ + FSL_UCO_SAVE_DESC_CHAIN, + /*! + * User has made at least one request with callbacks requested, so API is + * ready to handle others. + */ + FSL_UCO_CALLBACK_SETUP_COMPLETE, + /*! + * (virtual) pointer to descriptor chain is completely linked with physical + * (DMA) addresses, ready for the hardware. This flag should not be used + * by FSL SHW API programs. + */ + FSL_UCO_CHAIN_PREPHYSICALIZED, + /*! + * The user has changed the context but the changes have not been copied to + * the kernel driver. + */ + FSL_UCO_CONTEXT_CHANGED, + /*! Internal Use. This context belongs to a user-mode API user. */ + FSL_UCO_USERMODE_USER, +} fsl_shw_user_ctx_flags_t; + +/*! + * Return code for FSL_SHW library. + * + * These codes may be returned from a function call. In non-blocking mode, + * they will appear as the status in a Result Object. + */ +typedef enum fsl_shw_return_t { + /*! + * No error. As a function return code in Non-blocking mode, this may + * simply mean that the operation was accepted for eventual execution. + */ + FSL_RETURN_OK_S = 0, + /*! Failure for non-specific reason. */ + FSL_RETURN_ERROR_S, + /*! + * Operation failed because some resource was not able to be allocated. + */ + FSL_RETURN_NO_RESOURCE_S, + /*! Crypto algorithm unrecognized or improper. */ + FSL_RETURN_BAD_ALGORITHM_S, + /*! Crypto mode unrecognized or improper. */ + FSL_RETURN_BAD_MODE_S, + /*! Flag setting unrecognized or inconsistent. */ + FSL_RETURN_BAD_FLAG_S, + /*! Improper or unsupported key length for algorithm. */ + FSL_RETURN_BAD_KEY_LENGTH_S, + /*! Improper parity in a (DES, TDES) key. */ + FSL_RETURN_BAD_KEY_PARITY_S, + /*! + * Improper or unsupported data length for algorithm or internal buffer. + */ + FSL_RETURN_BAD_DATA_LENGTH_S, + /*! Authentication / Integrity Check code check failed. */ + FSL_RETURN_AUTH_FAILED_S, + /*! A memory error occurred. */ + FSL_RETURN_MEMORY_ERROR_S, + /*! An error internal to the hardware occurred. */ + FSL_RETURN_INTERNAL_ERROR_S, + /*! ECC detected Point at Infinity */ + FSL_RETURN_POINT_AT_INFINITY_S, + /*! ECC detected No Point at Infinity */ + FSL_RETURN_POINT_NOT_AT_INFINITY_S, + /*! GCD is One */ + FSL_RETURN_GCD_IS_ONE_S, + /*! GCD is not One */ + FSL_RETURN_GCD_IS_NOT_ONE_S, + /*! Candidate is Prime */ + FSL_RETURN_PRIME_S, + /*! Candidate is not Prime */ + FSL_RETURN_NOT_PRIME_S, + /*! N register loaded improperly with even value */ + FSL_RETURN_EVEN_MODULUS_ERROR_S, + /*! Divisor is zero. */ + FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S, + /*! Bad Exponent or Scalar value for Point Multiply */ + FSL_RETURN_BAD_EXPONENT_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_OSCILLATOR_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_STATISTICS_ERROR_S, +} fsl_shw_return_t; + +/*! + * Algorithm Identifier. + * + * Selection of algorithm will determine how large the block size of the + * algorithm is. Context size is the same length unless otherwise specified. + * Selection of algorithm also affects the allowable key length. + */ +typedef enum fsl_shw_key_alg_t { + FSL_KEY_ALG_HMAC, /*!< Key will be used to perform an HMAC. Key + size is 1 to 64 octets. Block size is 64 + octets. */ + FSL_KEY_ALG_AES, /*!< Advanced Encryption Standard (Rijndael). + Block size is 16 octets. Key size is 16 + octets. (The single choice of key size is a + Sahara platform limitation.) */ + FSL_KEY_ALG_DES, /*!< Data Encryption Standard. Block size is + 8 octets. Key size is 8 octets. */ + FSL_KEY_ALG_TDES, /*!< 2- or 3-key Triple DES. Block size is 8 + octets. Key size is 16 octets for 2-key + Triple DES, and 24 octets for 3-key. */ + FSL_KEY_ALG_ARC4 /*!< ARC4. No block size. Context size is 259 + octets. Allowed key size is 1-16 octets. + (The choices for key size are a Sahara + platform limitation.) */ +} fsl_shw_key_alg_t; + +/*! + * Mode selector for Symmetric Ciphers. + * + * The selection of mode determines how a cryptographic algorithm will be + * used to process the plaintext or ciphertext. + * + * For all modes which are run block-by-block (that is, all but + * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text + * length which is multiple of the block size. Except for #FSL_SYM_MODE_CTR, + * these block-by-block algorithms must also be passed a total number of octets + * which is a multiple of the block size. + * + * In modes which require that the total number of octets of data be a multiple + * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user + * has a total number of octets which are not a multiple of the block size, the + * user must perform any necessary padding to get to the correct data length. + */ +typedef enum fsl_shw_sym_mode_t { + /*! + * Stream. There is no associated block size. Any request to process data + * may be of any length. This mode is only for ARC4 operations, and is + * also the only mode used for ARC4. + */ + FSL_SYM_MODE_STREAM, + + /*! + * Electronic Codebook. Each block of data is encrypted/decrypted. The + * length of the data stream must be a multiple of the block size. This + * mode may be used for DES, 3DES, and AES. The block size is determined + * by the algorithm. + */ + FSL_SYM_MODE_ECB, + /*! + * Cipher-Block Chaining. Each block of data is encrypted/decrypted and + * then "chained" with the previous block by an XOR function. Requires + * context to start the XOR (previous block). This mode may be used for + * DES, 3DES, and AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CBC, + /*! + * Counter. The counter is encrypted, then XORed with a block of data. + * The counter is then incremented (using modulus arithmetic) for the next + * block. The final operation may be non-multiple of block size. This mode + * may be used for AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CTR, +} fsl_shw_sym_mode_t; + +/*! + * Algorithm selector for Cryptographic Hash functions. + * + * Selection of algorithm determines how large the context and digest will be. + * Context is the same size as the digest (resulting hash), unless otherwise + * specified. + */ +typedef enum fsl_shw_hash_alg_t { + FSL_HASH_ALG_MD5, /*!< MD5 algorithm. Digest is 16 octets. */ + FSL_HASH_ALG_SHA1, /*!< SHA-1 (aka SHA or SHA-160) algorithm. + Digest is 20 octets. */ + FSL_HASH_ALG_SHA224, /*!< SHA-224 algorithm. Digest is 28 octets, + though context is 32 octets. */ + FSL_HASH_ALG_SHA256 /*!< SHA-256 algorithm. Digest is 32 + octets. */ +} fsl_shw_hash_alg_t; + +/*! + * The type of Authentication-Cipher function which will be performed. + */ +typedef enum fsl_shw_acc_mode_t { + /*! + * CBC-MAC for Counter. Requires context and modulus. Final operation may + * be non-multiple of block size. This mode may be used for AES. + */ + FSL_ACC_MODE_CCM, + /*! + * SSL mode. Not supported. Combines HMAC and encrypt (or decrypt). + * Needs one key object for encryption, another for the HMAC. The usual + * hashing and symmetric encryption algorithms are supported. + */ + FSL_ACC_MODE_SSL, +} fsl_shw_acc_mode_t; + +/*! + * The operation which controls the behavior of #fsl_shw_establish_key(). + * + * These values are passed to #fsl_shw_establish_key(). + */ +typedef enum fsl_shw_key_wrap_t { + FSL_KEY_WRAP_CREATE, /*!< Generate a key from random values. */ + FSL_KEY_WRAP_ACCEPT, /*!< Use the provided clear key. */ + FSL_KEY_WRAP_UNWRAP /*!< Unwrap a previously wrapped key. */ +} fsl_shw_key_wrap_t; + +/* REQ-S2LRD-PINTFC-COA-HCO-001 */ +/*! + * Flags which control a Hash operation. + * + * These may be combined by ORing them together. See #fsl_shw_hco_set_flags() + * and #fsl_shw_hco_clear_flags(). + */ +typedef enum fsl_shw_hash_ctx_flags_t { + FSL_HASH_FLAGS_INIT = 1, /*!< Context is empty. Hash is started + from scratch, with a message-processed + count of zero. */ + FSL_HASH_FLAGS_SAVE = 2, /*!< Retrieve context from hardware after + hashing. If used with the + #FSL_HASH_FLAGS_FINALIZE flag, the final + digest value will be saved in the + object. */ + FSL_HASH_FLAGS_LOAD = 4, /*!< Place context into hardware before + hashing. */ + FSL_HASH_FLAGS_FINALIZE = 8, /*!< PAD message and perform final digest + operation. If user message is + pre-padded, this flag should not be + used. */ +} fsl_shw_hash_ctx_flags_t; + +/*! + * Flags which control an HMAC operation. + * + * These may be combined by ORing them together. See #fsl_shw_hmco_set_flags() + * and #fsl_shw_hmco_clear_flags(). + */ +typedef enum fsl_shw_hmac_ctx_flags_t { + FSL_HMAC_FLAGS_INIT = 1, /*!< Message context is empty. HMAC is + started from scratch (with key) or from + precompute of inner hash, depending on + whether + #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is + set. */ + FSL_HMAC_FLAGS_SAVE = 2, /*!< Retrieve ongoing context from hardware + after hashing. If used with the + #FSL_HMAC_FLAGS_FINALIZE flag, the final + digest value (HMAC) will be saved in the + object. */ + FSL_HMAC_FLAGS_LOAD = 4, /*!< Place ongoing context into hardware + before hashing. */ + FSL_HMAC_FLAGS_FINALIZE = 8, /*!< PAD message and perform final HMAC + operations of inner and outer hashes. */ + FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16 /*!< This means that the context + contains precomputed inner and outer + hash values. */ +} fsl_shw_hmac_ctx_flags_t; + +/*! + * Flags to control use of the #fsl_shw_scco_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags() + */ +typedef enum fsl_shw_sym_ctx_flags_t { + /*! + * Context is empty. In ARC4, this means that the S-Box needs to be + * generated from the key. In #FSL_SYM_MODE_CBC mode, this allows an IV of + * zero to be specified. In #FSL_SYM_MODE_CTR mode, it means that an + * initial CTR value of zero is desired. + */ + FSL_SYM_CTX_INIT = 1, + /*! + * Load context from object into hardware before running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_LOAD = 2, + /*! + * Save context from hardware into object after running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_SAVE = 4, + /*! + * Context (SBox) is to be unwrapped and wrapped on each use. + * This flag is unsupported. + * */ + FSL_SYM_CTX_PROTECT = 8, +} fsl_shw_sym_ctx_flags_t; + +/*! + * Flags which describe the state of the #fsl_shw_sko_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags() + */ +typedef enum fsl_shw_key_flags_t { + FSL_SKO_KEY_IGNORE_PARITY = 1, /*!< If algorithm is DES or 3DES, do not + validate the key parity bits. */ + FSL_SKO_KEY_PRESENT = 2, /*!< Clear key is present in the object. */ + FSL_SKO_KEY_ESTABLISHED = 4, /*!< Key has been established for use. This + feature is not available for all + platforms, nor for all algorithms and + modes. */ + FSL_SKO_KEY_SW_KEY = 8, /*!< This key is for software use, and can + be copied out of a keystore by its owner. + The default is that they key is available + only for hardware (or security driver) + use. */ +} fsl_shw_key_flags_t; + +/*! + * Type of value which is associated with an established key. + */ +typedef uint64_t key_userid_t; + +/*! + * Flags which describe the state of the #fsl_shw_acco_t. + * + * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used + * together, provide for a one-shot operation. + */ +typedef enum fsl_shw_auth_ctx_flags_t { + FSL_ACCO_CTX_INIT = 1, /*!< Initialize Context(s) */ + FSL_ACCO_CTX_LOAD = 2, /*!< Load intermediate context(s). + This flag is unsupported. */ + FSL_ACCO_CTX_SAVE = 4, /*!< Save intermediate context(s). + This flag is unsupported. */ + FSL_ACCO_CTX_FINALIZE = 8, /*!< Create MAC during this operation. */ + FSL_ACCO_NIST_CCM = 16, /*!< Formatting of CCM input data is + performed by calls to + #fsl_shw_ccm_nist_format_ctr_and_iv() and + #fsl_shw_ccm_nist_update_ctr_and_iv(). */ +} fsl_shw_auth_ctx_flags_t; + +/*! + * Modulus Selector for CTR modes. + * + * The incrementing of the Counter value may be modified by a modulus. If no + * modulus is needed or desired for AES, use #FSL_CTR_MOD_128. + */ +typedef enum fsl_shw_ctr_mod_t { + FSL_CTR_MOD_8, /*!< Run counter with modulus of 2^8. */ + FSL_CTR_MOD_16, /*!< Run counter with modulus of 2^16. */ + FSL_CTR_MOD_24, /*!< Run counter with modulus of 2^24. */ + FSL_CTR_MOD_32, /*!< Run counter with modulus of 2^32. */ + FSL_CTR_MOD_40, /*!< Run counter with modulus of 2^40. */ + FSL_CTR_MOD_48, /*!< Run counter with modulus of 2^48. */ + FSL_CTR_MOD_56, /*!< Run counter with modulus of 2^56. */ + FSL_CTR_MOD_64, /*!< Run counter with modulus of 2^64. */ + FSL_CTR_MOD_72, /*!< Run counter with modulus of 2^72. */ + FSL_CTR_MOD_80, /*!< Run counter with modulus of 2^80. */ + FSL_CTR_MOD_88, /*!< Run counter with modulus of 2^88. */ + FSL_CTR_MOD_96, /*!< Run counter with modulus of 2^96. */ + FSL_CTR_MOD_104, /*!< Run counter with modulus of 2^104. */ + FSL_CTR_MOD_112, /*!< Run counter with modulus of 2^112. */ + FSL_CTR_MOD_120, /*!< Run counter with modulus of 2^120. */ + FSL_CTR_MOD_128 /*!< Run counter with modulus of 2^128. */ +} fsl_shw_ctr_mod_t; + +/*! + * Permissions flags for Secure Partitions + * + * They currently map directly to the SCC2 hardware values, but this is not + * guarinteed behavior. + */ +typedef enum fsl_shw_permission_t { +/*! SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */ + FSL_PERM_NO_ZEROIZE, +/*! SCM Access Permission: Enforce trusted key read in */ + FSL_PERM_TRUSTED_KEY_READ, +/*! SCM Access Permission: Ignore Supervisor/User mode in permission determination */ + FSL_PERM_HD_S, +/*! SCM Access Permission: Allow Read Access to Host Domain */ + FSL_PERM_HD_R, +/*! SCM Access Permission: Allow Write Access to Host Domain */ + FSL_PERM_HD_W, +/*! SCM Access Permission: Allow Execute Access to Host Domain */ + FSL_PERM_HD_X, +/*! SCM Access Permission: Allow Read Access to Trusted Host Domain */ + FSL_PERM_TH_R, +/*! SCM Access Permission: Allow Write Access to Trusted Host Domain */ + FSL_PERM_TH_W, +/*! SCM Access Permission: Allow Read Access to Other/World Domain */ + FSL_PERM_OT_R, +/*! SCM Access Permission: Allow Write Access to Other/World Domain */ + FSL_PERM_OT_W, +/*! SCM Access Permission: Allow Execute Access to Other/World Domain */ + FSL_PERM_OT_X, +} fsl_shw_permission_t; + +/*! + * Select the cypher mode to use for partition cover/uncover operations. + * + * They currently map directly to the values used in the SCC2 driver, but this + * is not guarinteed behavior. + */ +typedef enum fsl_shw_cypher_mode_t { + FSL_SHW_CYPHER_MODE_ECB, /*!< ECB mode */ + FSL_SHW_CYPHER_MODE_CBC, /*!< CBC mode */ +} fsl_shw_cypher_mode_t; + +/*! + * Which platform key should be presented for cryptographic use. + */ +typedef enum fsl_shw_pf_key_t { + FSL_SHW_PF_KEY_IIM, /*!< Present fused IIM key */ + FSL_SHW_PF_KEY_PRG, /*!< Present Program key */ + FSL_SHW_PF_KEY_IIM_PRG, /*!< Present IIM ^ Program key */ + FSL_SHW_PF_KEY_IIM_RND, /*!< Present Random key */ + FSL_SHW_PF_KEY_RND, /*!< Present IIM ^ Random key */ +} fsl_shw_pf_key_t; + +/*! + * The various security tamper events + */ +typedef enum fsl_shw_tamper_t { + FSL_SHW_TAMPER_NONE, /*!< No error detected */ + FSL_SHW_TAMPER_WTD, /*!< wire-mesh tampering det */ + FSL_SHW_TAMPER_ETBD, /*!< ext tampering det: input B */ + FSL_SHW_TAMPER_ETAD, /*!< ext tampering det: input A */ + FSL_SHW_TAMPER_EBD, /*!< external boot detected */ + FSL_SHW_TAMPER_SAD, /*!< security alarm detected */ + FSL_SHW_TAMPER_TTD, /*!< temperature tampering det */ + FSL_SHW_TAMPER_CTD, /*!< clock tampering det */ + FSL_SHW_TAMPER_VTD, /*!< voltage tampering det */ + FSL_SHW_TAMPER_MCO, /*!< monotonic counter overflow */ + FSL_SHW_TAMPER_TCO, /*!< time counter overflow */ +} fsl_shw_tamper_t; + +/*! @} *//* consgrp */ + +/****************************************************************************** + * Data Structures + *****************************************************************************/ +/*! @addtogroup strgrp + @{ */ + +/* REQ-S2LRD-PINTFC-COA-IBO-001 */ +/*! + * Application Initialization Object + * + * This object, the operations on it, and its interaction with the driver are + * TBD. + */ +typedef struct fsl_sho_ibo_t { +} fsl_sho_ibo_t; + +/* REQ-S2LRD-PINTFC-COA-UCO-001 */ +/*! + * User Context Object + * + * This object must be initialized by a call to #fsl_shw_uco_init(). It must + * then be passed to #fsl_shw_register_user() before it can be used in any + * calls besides those in @ref ucoops. + * + * It contains the user's configuration for the API, for instance whether an + * operation should block, or instead should call back the user upon completion + * of the operation. + * + * See @ref ucoops for further information. + */ +typedef struct fsl_shw_uco_t { /* fsl_shw_user_context_object */ +} fsl_shw_uco_t; + +/* REQ-S2LRD-PINTFC-API-GEN-006 ?? */ +/*! + * Result Object + * + * This object will contain success and failure information about a specific + * cryptographic request which has been made. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref rops. + */ +typedef struct fsl_shw_result_t { /* fsl_shw_result */ +} fsl_shw_result_t; + +/*! + * Keystore Object + * + * This object holds the context of a user keystore, including the functions + * that define the interface and pointers to where the key data is stored. The + * user must supply a set of functions to handle keystore management, including + * slot allocation, deallocation, etc. A default keystore manager is provided + * as part of the API. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref ksoops. + */ +typedef struct fsl_shw_kso_t { /* fsl_shw_keystore_object */ +} fsl_shw_kso_t; + +/* REQ-S2LRD-PINTFC-COA-SKO-001 */ +/*! + * Secret Key Object + * + * This object contains a key for a cryptographic operation, and information + * about its current state, its intended usage, etc. It may instead contain + * information about a protected key, or an indication to use a platform- + * specific secret key. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref skoops. + */ +typedef struct fsl_shw_sko_t { /* fsl_shw_secret_key_object */ +} fsl_shw_sko_t; + +/* REQ-S2LRD-PINTFC-COA-CO-001 */ +/*! + * Platform Capabilities Object + * + * This object will contain information about the cryptographic features of the + * platform which the program is running on. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. + * + * See @ref pcoops. + */ +typedef struct fsl_shw_pco_t { /* fsl_shw_platform_capabilities_object */ +} fsl_shw_pco_t; + +/* REQ-S2LRD-PINTFC-COA-HCO-001 */ +/*! + * Hash Context Object + * + * This object contains information to control hashing functions. + + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref hcops. + */ +typedef struct fsl_shw_hco_t { /* fsl_shw_hash_context_object */ +} fsl_shw_hco_t; + +/*! + * HMAC Context Object + * + * This object contains information to control HMAC functions. + + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref hmcops. + */ +typedef struct fsl_shw_hmco_t { /* fsl_shw_hmac_context_object */ +} fsl_shw_hmco_t; + +/* REQ-S2LRD-PINTFC-COA-SCCO-001 */ +/*! + * Symmetric Cipher Context Object + * + * This object contains information to control Symmetric Ciphering encrypt and + * decrypt functions in #FSL_SYM_MODE_STREAM (ARC4), #FSL_SYM_MODE_ECB, + * #FSL_SYM_MODE_CBC, and #FSL_SYM_MODE_CTR modes and the + * #fsl_shw_symmetric_encrypt() and #fsl_shw_symmetric_decrypt() functions. + * CCM mode is controlled with the #fsl_shw_acco_t object. + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref sccops. + */ +typedef struct fsl_shw_scco_t { /* fsl_shw_symmetric_cipher_context_object */ +} fsl_shw_scco_t; + +/*! + * Authenticate-Cipher Context Object + + * An object for controlling the function of, and holding information about, + * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and + * #fsl_shw_auth_decrypt(). + * + * No direct access to its members should be made by programs. Instead, the + * object should be manipulated using the provided functions. See @ref + * accoops. + */ +typedef struct fsl_shw_acco_t { /* fsl_shw_authenticate_cipher_context_object */ +} fsl_shw_acco_t; + /*! @} *//* strgrp */ + +/****************************************************************************** + * Access Macros for Objects + *****************************************************************************/ +/*! @addtogroup pcoops + @{ */ + +/*! + * Get FSL SHW API version + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] major A pointer to where the major version + * of the API is to be stored. + * @param[out] minor A pointer to where the minor version + * of the API is to be stored. + */ +void fsl_shw_pco_get_version(const fsl_shw_pco_t * pc_info, + uint32_t * major, uint32_t * minor); + +/*! + * Get underlying driver version. + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] major A pointer to where the major version + * of the driver is to be stored. + * @param[out] minor A pointer to where the minor version + * of the driver is to be stored. + */ +void fsl_shw_pco_get_driver_version(const fsl_shw_pco_t * pc_info, + uint32_t * major, uint32_t * minor); + +/*! + * Get list of symmetric algorithms supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] algorithms A pointer to where to store the location of + * the list of algorithms. + * @param[out] algorithm_count A pointer to where to store the number of + * algorithms in the list at @a algorithms. + */ +void fsl_shw_pco_get_sym_algorithms(const fsl_shw_pco_t * pc_info, + fsl_shw_key_alg_t * algorithms[], + uint8_t * algorithm_count); + +/*! + * Get list of symmetric modes supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] modes A pointer to where to store the location of + * the list of modes. + * @param[out] mode_count A pointer to where to store the number of + * algorithms in the list at @a modes. + */ +void fsl_shw_pco_get_sym_modes(const fsl_shw_pco_t * pc_info, + fsl_shw_sym_mode_t * modes[], + uint8_t * mode_count); + +/*! + * Get list of hash algorithms supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] algorithms A pointer which will be set to the list of + * algorithms. + * @param[out] algorithm_count The number of algorithms in the list at @a + * algorithms. + */ +void fsl_shw_pco_get_hash_algorithms(const fsl_shw_pco_t * pc_info, + fsl_shw_hash_alg_t * algorithms[], + uint8_t * algorithm_count); + +/*! + * Determine whether the combination of a given symmetric algorithm and a given + * mode is supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param algorithm A Symmetric Cipher algorithm. + * @param mode A Symmetric Cipher mode. + * + * @return 0 if combination is not supported, non-zero if supported. + */ +int fsl_shw_pco_check_sym_supported(const fsl_shw_pco_t * pc_info, + fsl_shw_key_alg_t algorithm, + fsl_shw_sym_mode_t mode); + +/*! + * Determine whether a given Encryption-Authentication mode is supported. + * + * @param pc_info The Platform Capabilities Object to query. + * @param mode The Authentication mode. + * + * @return 0 if mode is not supported, non-zero if supported. + */ +int fsl_shw_pco_check_auth_supported(const fsl_shw_pco_t * pc_info, + fsl_shw_acc_mode_t mode); + +/*! + * Determine whether Black Keys (key establishment / wrapping) is supported. + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 0 if wrapping is not supported, non-zero if supported. + */ +int fsl_shw_pco_check_black_key_supported(const fsl_shw_pco_t * pc_info); + +/*! + * Get FSL SHW SCC driver version + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] major A pointer to where the major version + * of the SCC driver is to be stored. + * @param[out] minor A pointer to where the minor version + * of the SCC driver is to be stored. + */ +void fsl_shw_pco_get_scc_driver_version(const fsl_shw_pco_t * pc_info, + uint32_t * major, uint32_t * minor); + +/*! + * Get SCM hardware version + * + * @param pc_info The Platform Capabilities Object to query. + * @return The SCM hardware version + */ +uint32_t fsl_shw_pco_get_scm_version(const fsl_shw_pco_t * pc_info); + +/*! + * Get SMN hardware version + * + * @param pc_info The Platform Capabilities Object to query. + * @return The SMN hardware version + */ +uint32_t fsl_shw_pco_get_smn_version(const fsl_shw_pco_t * pc_info); + +/*! + * Get the size of an SCM block, in bytes + * + * @param pc_info The Platform Capabilities Object to query. + * @return The size of an SCM block, in bytes. + */ +uint32_t fsl_shw_pco_get_scm_block_size(const fsl_shw_pco_t * pc_info); + +/*! + * Get size of Black and Red RAM memory + * + * @param pc_info The Platform Capabilities Object to query. + * @param[out] black_size A pointer to where the size of the Black RAM, in + * blocks, is to be placed. + * @param[out] red_size A pointer to where the size of the Red RAM, in + * blocks, is to be placed. + */ +void fsl_shw_pco_get_smn_size(const fsl_shw_pco_t * pc_info, + uint32_t * black_size, uint32_t * red_size); + +/*! + * Determine whether Secure Partitions are supported + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 0 if secure partitions are not supported, non-zero if supported. + */ +int fsl_shw_pco_check_spo_supported(const fsl_shw_pco_t * pc_info); + +/*! + * Get the size of a Secure Partitions + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return Partition size, in bytes. 0 if Secure Partitions not supported. + */ +uint32_t fsl_shw_pco_get_spo_size_bytes(const fsl_shw_pco_t * pc_info); + +/*! + * Get the number of Secure Partitions on this platform + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return Number of partitions. 0 if Secure Partitions not supported. Note + * that this returns the total number of partitions, though + * not all may be available to the user. + */ +uint32_t fsl_shw_pco_get_spo_count(const fsl_shw_pco_t * pc_info); + +/*! + * Determine whether Platform Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Programmed Key features are available, otherwise zero. + */ +int fsl_shw_pco_check_pk_supported(const fsl_shw_pco_t * pc_info); + +/*! + * Determine whether Software Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Software key features are available, otherwise zero. + */ +int fsl_shw_pco_check_sw_keys_supported(const fsl_shw_pco_t * pc_info); + +/*! @} *//* pcoops */ + +/*! @addtogroup ucoops + @{ */ + +/*! + * Initialize a User Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the User Context Object to initial values, and set the size + * of the results pool. The mode will be set to a default of + * #FSL_UCO_BLOCKING_MODE. + * + * When using non-blocking operations, this sets the maximum number of + * operations which can be outstanding. This number includes the counts of + * operations waiting to start, operation(s) being performed, and results which + * have not been retrieved. + * + * Changes to this value are ignored once user registration has completed. It + * should be set to 1 if only blocking operations will ever be performed. + * + * @param user_ctx The User Context object to operate on. + * @param pool_size The maximum number of operations which can be + * outstanding. + */ +void fsl_shw_uco_init(fsl_shw_uco_t * user_ctx, uint16_t pool_size); + +/*! + * Set the User Reference for the User Context. + * + * @param user_ctx The User Context object to operate on. + * @param reference A value which will be passed back with a result. + */ +void fsl_shw_uco_set_reference(fsl_shw_uco_t * user_ctx, uint32_t reference); + +/*! + * Set the callback routine for the User Context. + * + * Note that the callback routine may be called when no results are available, + * and possibly even when no requests are outstanding. + * + * + * @param user_ctx The User Context object to operate on. + * @param callback_fn The function the API will invoke when an operation + * completes. + */ +void fsl_shw_uco_set_callback(fsl_shw_uco_t * user_ctx, + void (*callback_fn) (fsl_shw_uco_t * uco)); + +/*! + * Set flags in the User Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param user_ctx The User Context object to operate on. + * @param flags ORed values from #fsl_shw_user_ctx_flags_t. + */ +void fsl_shw_uco_set_flags(fsl_shw_uco_t * user_ctx, uint32_t flags); + +/*! + * Clear flags in the User Context. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param user_ctx The User Context object to operate on. + * @param flags ORed values from #fsl_shw_user_ctx_flags_t. + */ +void fsl_shw_uco_clear_flags(fsl_shw_uco_t * user_ctx, uint32_t flags); + +/*! + * Select a key for the key-wrap key for key wrapping/unwrapping + * + * Without a call to this function, default is FSL_SHW_PF_KEY_IIM. The wrap + * key is used to encrypt and decrypt the per-key random secret which is used + * to calculate the key which will encrypt/decrypt the user's key. + * + * @param user_ctx The User Context object to operate on. + * @param pf_key Which key to use. Valid choices are + * #FSL_SHW_PF_KEY_IIM, #FSL_SHW_PF_KEY_RND, and + * #FSL_SHW_PF_KEY_IIM_RND. + */ +void fsl_shw_uco_set_wrap_key(fsl_shw_uco_t * user_ctx, + fsl_shw_pf_key_t pf_key); + + /*! @} *//* ucoops */ + +/*! @addtogroup rops + @{ */ + +/*! + * Retrieve the status code from a Result Object. + * + * @param result The result object to query. + * + * @return The status of the request. + */ +fsl_shw_return_t fsl_shw_ro_get_status(fsl_shw_result_t * result); + +/*! + * Retrieve the reference value from a Result Object. + * + * @param result The result object to query. + * + * @return The reference associated with the request. + */ +uint32_t fsl_shw_ro_get_reference(fsl_shw_result_t * result); + + /* @} *//* rops */ + +/*! @addtogroup skoops + @{ */ + +/*! + * Initialize a Secret Key Object. + * + * This function or #fsl_shw_sko_init_pf_key() must be called before performing + * any other operation with the Object. + * + * @param key_info The Secret Key Object to be initialized. + * @param algorithm DES, AES, etc. + * + */ +void fsl_shw_sko_init(fsl_shw_sko_t * key_info, fsl_shw_key_alg_t algorithm); + +/*! + * Initialize a Secret Key Object to use a Platform Key register. + * + * This function or #fsl_shw_sko_init() must be called before performing any + * other operation with the Object. #fsl_shw_sko_set_key() does not work on + * a key object initialized in this way. + * + * If this function is used to initialize the key object, but no key is + * established with the key object, then the object will refer strictly to the + * key value specified by the @c pf_key selection. + * + * If the pf key is #FSL_SHW_PF_KEY_PRG or #FSL_SHW_PF_KEY_IIM_PRG, then the + * key object may be used with #fsl_shw_establish_key() to change the Program + * Key value. When the pf key is neither #FSL_SHW_PF_KEY_PRG nor + * #FSL_SHW_PF_KEY_IIM_PRG, it is an error to call #fsl_shw_establish_key(). + * + * @param key_info The Secret Key Object to be initialized. + * @param algorithm DES, AES, etc. + * @param pf_key Which platform key is referenced. + */ +void fsl_shw_sko_init_pf_key(fsl_shw_sko_t * key_info, + fsl_shw_key_alg_t algorithm, + fsl_shw_pf_key_t pf_key); + +/*! + * Store a cleartext key in the key object. + * + * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag. It should + * not be used if there is a key established with the key object. If there is, + * a call to #fsl_shw_release_key() should be made first. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param key A pointer to the beginning of the key. + * @param key_length The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +void fsl_shw_sko_set_key(fsl_shw_sko_t * key_object, + const uint8_t * key, uint16_t key_length); + +/*! + * Set a size for the key. + * + * This function would normally be used when the user wants the key to be + * generated from a random source. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param key_length The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +void fsl_shw_sko_set_key_length(fsl_shw_sko_t * key_object, + uint16_t key_length); + +/*! + * Set the User ID associated with the key. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param userid The User ID to identify authorized users of the key. + */ +void fsl_shw_sko_set_user_id(fsl_shw_sko_t * key_object, key_userid_t userid); + +/*! + * Set the keystore that the key will be stored in. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param keystore The keystore to place the key in. This is a variable of + * type #fsl_shw_kso_t. + */ +void fsl_shw_sko_set_keystore(fsl_shw_sko_t * key_object, + fsl_shw_kso_t * keystore); + +/*! + * Set the establish key handle into a key object. + * + * The @a userid field will be used to validate the access to the unwrapped + * key. This feature is not available for all platforms, nor for all + * algorithms and modes. + * + * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT + * flag will be cleared). + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param userid The User ID to verify this user is an authorized user of + * the key. + * @param handle A @a handle from #fsl_shw_sko_get_established_info. + */ +void fsl_shw_sko_set_established_info(fsl_shw_sko_t * key_object, + key_userid_t userid, uint32_t handle); + +/*! + * Extract the algorithm from a key object. + * + * @param key_info The Key Object to be queried. + * @param[out] algorithm A pointer to the location to store the algorithm. + */ +void fsl_shw_sko_get_algorithm(const fsl_shw_sko_t * key_info, + fsl_shw_key_alg_t * algorithm); + +/*! + * Retrieve the cleartext key from a key object that is stored in a user + * keystore. + * + * @param skobject The Key Object to be queried. + * @param[out] skkey A pointer to the location to store the key. NULL + * if the key is not stored in a user keystore. + */ +void fsl_shw_sko_get_key(const fsl_shw_sko_t * skobject, void *skkey); + +/*! + * Retrieve the established-key handle from a key object. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param handle The location to store the @a handle of the unwrapped + * key. + */ +void fsl_shw_sko_get_established_info(fsl_shw_sko_t * key_object, + uint32_t * handle); + +/*! + * Determine the size of a wrapped key based upon the cleartext key's length. + * + * This function can be used to calculate the number of octets that + * #fsl_shw_extract_key() will write into the location at @a covered_key. + * + * If zero is returned at @a length, this means that the key length in + * @a key_info is not supported. + * + * @param key_info Information about a key to be wrapped. + * @param length Location to store the length of a wrapped + * version of the key in @a key_info. + */ +void fsl_shw_sko_calculate_wrapped_size(const fsl_shw_sko_t * key_info, + uint32_t * length); + +/*! + * Set some flags in the key object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param flags (One or more) ORed members of #fsl_shw_key_flags_t which + * are to be set. + */ +void fsl_shw_sko_set_flags(fsl_shw_sko_t * key_object, uint32_t flags); + +/*! + * Clear some flags in the key object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param key_object A variable of type #fsl_shw_sko_t. + * @param flags (One or more) ORed members of #fsl_shw_key_flags_t which + * are to be reset. + */ +void fsl_shw_sko_clear_flags(fsl_shw_sko_t * key_object, uint32_t flags); + + /*! @} *//* end skoops */ + +/*****************************************************************************/ + +/*! @addtogroup hcops + @{ */ + +/*****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-004 - partially */ +/*! + * Initialize a Hash Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the hash + * context object. + * + * @param hash_ctx The hash context to operate upon. + * @param algorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +void fsl_shw_hco_init(fsl_shw_hco_t * hash_ctx, fsl_shw_hash_alg_t algorithm); + +/*****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-001 */ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-002 */ +/*! + * Get the current hash value and message length from the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hash_ctx The hash context to query. + * @param[out] digest Pointer to the location of @a length octets where to + * store a copy of the current value of the digest. + * @param length Number of octets of hash value to copy. + * @param[out] msg_length Pointer to the location to store the number of octets + * already hashed. + */ +void fsl_shw_hco_get_digest(const fsl_shw_hco_t * hash_ctx, uint8_t * digest, + uint8_t length, uint32_t * msg_length); + +/*****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-002 - partially */ +/*! + * Get the hash algorithm from the hash context object. + * + * @param hash_ctx The hash context to query. + * @param[out] algorithm Pointer to where the algorithm is to be stored. + */ +void fsl_shw_hco_get_info(const fsl_shw_hco_t * hash_ctx, + fsl_shw_hash_alg_t * algorithm); + +/*****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-003 */ +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-004 */ +/*! + * Set the current hash value and message length in the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hash_ctx The hash context to operate upon. + * @param context Pointer to buffer of appropriate length to copy into + * the hash context object. + * @param msg_length The number of octets of the message which have + * already been hashed. + * + */ +void fsl_shw_hco_set_digest(fsl_shw_hco_t * hash_ctx, const uint8_t * context, + uint32_t msg_length); + +/*! + * Set flags in a Hash Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hash_ctx The hash context to be operated on. + * @param flags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +void fsl_shw_hco_set_flags(fsl_shw_hco_t * hash_ctx, uint32_t flags); + +/*! + * Clear flags in a Hash Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hash_ctx The hash context to be operated on. + * @param flags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +void fsl_shw_hco_clear_flags(fsl_shw_hco_t * hash_ctx, uint32_t flags); + + /*! @} *//* end hcops */ + +/*****************************************************************************/ + +/*! @addtogroup hmcops + @{ */ + +/*! + * Initialize an HMAC Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the HMAC + * context object. + * + * @param hmac_ctx The HMAC context to operate upon. + * @param algorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +void fsl_shw_hmco_init(fsl_shw_hmco_t * hmac_ctx, fsl_shw_hash_alg_t algorithm); + +/*! + * Set flags in an HMAC Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hmac_ctx The HMAC context to be operated on. + * @param flags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +void fsl_shw_hmco_set_flags(fsl_shw_hmco_t * hmac_ctx, uint32_t flags); + +/*! + * Clear flags in an HMAC Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hmac_ctx The HMAC context to be operated on. + * @param flags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +void fsl_shw_hmco_clear_flags(fsl_shw_hmco_t * hmac_ctx, uint32_t flags); + +/*! @} */ + +/*****************************************************************************/ + +/*! @addtogroup sccops + @{ */ + +/*! + * Initialize a Symmetric Cipher Context Object. + * + * This function must be called before performing any other operation with the + * Object. This will set the @a mode and @a algorithm and initialize the + * Object. + * + * @param sym_ctx The context object to operate on. + * @param algorithm The cipher algorithm this context will be used with. + * @param mode #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc. + * + */ +void fsl_shw_scco_init(fsl_shw_scco_t * sym_ctx, + fsl_shw_key_alg_t algorithm, fsl_shw_sym_mode_t mode); + +/*! + * Set the flags for a Symmetric Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param sym_ctx The context object to operate on. + * @param flags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +void fsl_shw_scco_set_flags(fsl_shw_scco_t * sym_ctx, uint32_t flags); + +/*! + * Clear some flags in a Symmetric Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param sym_ctx The context object to operate on. + * @param flags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +void fsl_shw_scco_clear_flags(fsl_shw_scco_t * sym_ctx, uint32_t flags); + +/*! + * Set the Context (IV) for a Symmetric Cipher Context. + * + * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the + * context (the S-Box and pointers) for ARC4. The full context size will + * be copied. + * + * @param sym_ctx The context object to operate on. + * @param context A pointer to the buffer which contains the context. + * + */ +void fsl_shw_scco_set_context(fsl_shw_scco_t * sym_ctx, uint8_t * context); + +/*! + * Get the Context for a Symmetric Cipher Context. + * + * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to + * retrieve context (the S-Box and pointers) for ARC4. The full context + * will be copied. + * + * @param sym_ctx The context object to operate on. + * @param[out] context Pointer to location where context will be stored. + */ +void fsl_shw_scco_get_context(const fsl_shw_scco_t * sym_ctx, + uint8_t * context); + +/*! + * Set the Counter Value for a Symmetric Cipher Context. + * + * This will set the Counter Value for CTR mode. + * + * @param sym_ctx The context object to operate on. + * @param counter The starting counter value. The number of octets. + * copied will be the block size for the algorithm. + * @param modulus The modulus for controlling the incrementing of the counter. + * + */ +void fsl_shw_scco_set_counter_info(fsl_shw_scco_t * sym_ctx, + const uint8_t * counter, + fsl_shw_ctr_mod_t modulus); + +/*! + * Get the Counter Value for a Symmetric Cipher Context. + * + * This will retrieve the Counter Value is for CTR mode. + * + * @param sym_ctx The context object to query. + * @param[out] counter Pointer to location to store the current counter + * value. The number of octets copied will be the + * block size for the algorithm. + * @param[out] modulus Pointer to location to store the modulus. + * + */ +void fsl_shw_scco_get_counter_info(const fsl_shw_scco_t * sym_ctx, + uint8_t * counter, + fsl_shw_ctr_mod_t * modulus); + + /*! @} *//* end sccops */ + +/*****************************************************************************/ + +/*! @addtogroup accoops + @{ */ + +/*! + * Initialize a Authentication-Cipher Context. + * + * @param auth_object Pointer to object to operate on. + * @param mode The mode for this object (only #FSL_ACC_MODE_CCM + * supported). + */ +void fsl_shw_acco_init(fsl_shw_acco_t * auth_object, fsl_shw_acc_mode_t mode); + +/*! + * Set the flags for a Authentication-Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param auth_object Pointer to object to operate on. + * @param flags The flags to set (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +void fsl_shw_acco_set_flags(fsl_shw_acco_t * auth_object, uint32_t flags); + +/*! + * Clear some flags in a Authentication-Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param auth_object Pointer to object to operate on. + * @param flags The flags to reset (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +void fsl_shw_acco_clear_flags(fsl_shw_acco_t * auth_object, uint32_t flags); + +/*! + * Set up the Authentication-Cipher Object for CCM mode. + * + * This will set the @a auth_object for CCM mode and save the @a ctr, + * and @a mac_length. This function can be called instead of + * #fsl_shw_acco_init(). + * + * The parameter @a ctr is Counter Block 0, (counter value 0), which is for the + * MAC. + * + * @param auth_object Pointer to object to operate on. + * @param algorithm Cipher algorithm. Only AES is supported. + * @param ctr The initial counter value. + * @param mac_length The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + */ +void fsl_shw_acco_set_ccm(fsl_shw_acco_t * auth_object, + fsl_shw_key_alg_t algorithm, + const uint8_t * ctr, uint8_t mac_length); + +/*! + * Format the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will also set the IV and CTR values per Appendix A of NIST + * Special Publication 800-38C (May 2004). It will also perform the + * #fsl_shw_acco_set_ccm() operation with information derived from this set of + * parameters. + * + * Note this function assumes the algorithm is AES. It initializes the + * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the + * flags to be #FSL_ACCO_NIST_CCM. + * + * @param auth_object Pointer to object to operate on. + * @param t_length The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + * @param ad_length Number of octets of Associated Data (may be zero). + * @param q_length A value for the size of the length of @a q field. Valid + * values are 1-8. + * @param n The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param q The value of Q (size of the payload in octets). + * + */ +void fsl_shw_ccm_nist_format_ctr_and_iv(fsl_shw_acco_t * auth_object, + uint8_t t_length, + uint32_t ad_length, + uint8_t q_length, + const uint8_t * n, uint32_t q); + +/*! + * Update the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will set the IV and CTR values per Appendix A of NIST Special + * Publication 800-38C (May 2004). + * + * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has + * previously been called on the @a auth_object. + * + * @param auth_object Pointer to object to operate on. + * @param n The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param q The value of Q (size of the payload in octets). + * + */ +void fsl_shw_ccm_nist_update_ctr_and_iv(fsl_shw_acco_t * auth_object, + const uint8_t * n, uint32_t q); + + /* @} *//* accoops */ + +/****************************************************************************** + * Library functions + *****************************************************************************/ + +/*! @addtogroup miscfuns + @{ */ + +/* REQ-S2LRD-PINTFC-API-GEN-003 */ +/*! + * Determine the hardware security capabilities of this platform. + * + * Though a user context object is passed into this function, it will always + * act in a non-blocking manner. + * + * @param user_ctx The user context which will be used for the query. + * + * @return A pointer to the capabilities object. + */ +extern fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-004 */ +/*! + * Create an association between the user and the provider of the API. + * + * @param user_ctx The user context which will be used for this association. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-005 */ +/*! + * Destroy the association between the user and the provider of the API. + * + * @param user_ctx The user context which is no longer needed. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-006 */ +/*! + * Retrieve results from earlier operations. + * + * @param user_ctx The user's context. + * @param result_size The number of array elements of @a results. + * @param[in,out] results Pointer to first of the (array of) locations to + * store results. + * @param[out] result_count Pointer to store the number of results which + * were returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx, + uint16_t result_size, + fsl_shw_result_t results[], + uint16_t * result_count); + +/*! + * Allocate a block of secure memory + * + * @param user_ctx User context + * @param size Memory size (octets). Note: currently only + * supports only single-partition sized blocks. + * @param UMID User Mode ID to use when registering the + * partition. + * @param permissions Permissions to initialize the partition with. + * Can be made by ORing flags from the + * #fsl_shw_permission_t. + * + * @return Address of the allocated memory. NULL if the + * call was not successful. + */ +extern void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx, + uint32_t size, + const uint8_t * UMID, uint32_t permissions); + +/*! + * Free a block of secure memory that was allocated with #fsl_shw_smalloc + * + * @param user_ctx User context + * @param address Address of the block of secure memory to be + * released. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address); + +/*! + * Diminish the permissions of a block of secure memory. Note that permissions + * can only be revoked. + * + * @param user_ctx User context + * @param address Base address of the secure memory to work with + * @param permissions Permissions to initialize the partition with. + * Can be made by ORing flags from the + * #fsl_shw_permission_t. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx, + void *address, + uint32_t permissions); + +/*! + * @brief Encrypt a region of secure memory using the hardware secret key + * + * @param user_ctx User context + * @param partition_base Base address of the partition + * @param offset_bytes Offset of data from the partition base + * @param byte_count Length of the data to encrypt + * @param black_data Location to store the encrypted data + * @param IV IV to use for the encryption routine + * @param cypher_mode Cyphering mode to use, specified by type + * #fsl_shw_cypher_mode_t + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode); + +/*! + * @brief Decrypt a region of secure memory using the hardware secret key + * + * @param user_ctx User context + * @param partition_base Base address of the partition + * @param offset_bytes Offset of data from the partition base + * @param byte_count Length of the data to encrypt + * @param black_data Location to store the encrypted data + * @param IV IV to use for the encryption routine + * @param cypher_mode Cyphering mode to use, specified by type + * #fsl_shw_cypher_mode_t + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode); + + /*! @} *//* miscfuns */ + +/*! @addtogroup opfuns + @{ */ + +/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +/*! + * Encrypt a stream of data with a symmetric-key algorithm. + * + * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the + * flags of the @a sym_ctx object will control part of the operation of this + * function. The #FSL_SYM_CTX_INIT flag means that there is no context info in + * the object. The #FSL_SYM_CTX_LOAD means to use information in the + * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag + * means to update the object's context information after the operation has + * been performed. + * + * All of the data for an operation can be run through at once using the + * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using + * a @a length for the whole of the data. + * + * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function + * would "pick up" where the previous call left off, allowing the user to + * perform the larger function in smaller steps. + * + * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always + * be a multiple of the block size for the algorithm being used. For proper + * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the + * block size until the last operation on the total octet stream. + * + * Some users of ARC4 may want to compute the context (S-Box and pointers) from + * the key before any data is available. This may be done by running this + * function with a @a length of zero, with the init & save flags flags on in + * the @a sym_ctx. Subsequent operations would then run as normal with the + * load and save flags. Note that they key object is still required. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info Key and algorithm being used for this operation. + * @param[in,out] sym_ctx Info on cipher mode, state of the cipher. + * @param length Length, in octets, of the pt (and ct). + * @param pt pointer to plaintext to be encrypted. + * @param[out] ct pointer to where to store the resulting ciphertext. + * + * @return A return code of type #fsl_shw_return_t. + * + */ +extern fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, + uint8_t * ct); + +/* PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +/*! + * Decrypt a stream of data with a symmetric-key algorithm. + * + * In ARC4, and also in #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_CTR modes, the + * flags of the @a sym_ctx object will control part of the operation of this + * function. The #FSL_SYM_CTX_INIT flag means that there is no context info in + * the object. The #FSL_SYM_CTX_LOAD means to use information in the + * @a sym_ctx at the start of the operation, and the #FSL_SYM_CTX_SAVE flag + * means to update the object's context information after the operation has + * been performed. + * + * All of the data for an operation can be run through at once using the + * #FSL_SYM_CTX_INIT or #FSL_SYM_CTX_LOAD flags, as appropriate, and then using + * a @a length for the whole of the data. + * + * If a #FSL_SYM_CTX_SAVE flag were added, an additional call to the function + * would "pick up" where the previous call left off, allowing the user to + * perform the larger function in smaller steps. + * + * In #FSL_SYM_MODE_CBC and #FSL_SYM_MODE_ECB modes, the @a length must always + * be a multiple of the block size for the algorithm being used. For proper + * operation in #FSL_SYM_MODE_CTR mode, the @a length must be a multiple of the + * block size until the last operation on the total octet stream. + * + * Some users of ARC4 may want to compute the context (S-Box and pointers) from + * the key before any data is available. This may be done by running this + * function with a @a length of zero, with the #FSL_SYM_CTX_INIT & + * #FSL_SYM_CTX_SAVE flags on in the @a sym_ctx. Subsequent operations would + * then run as normal with the load & save flags. Note that they key object is + * still required. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The key and algorithm being used in this operation. + * @param[in,out] sym_ctx Info on cipher mode, state of the cipher. + * @param length Length, in octets, of the ct (and pt). + * @param ct pointer to ciphertext to be decrypted. + * @param[out] pt pointer to where to store the resulting plaintext. + * + * @return A return code of type #fsl_shw_return_t + * + */ +extern fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, + uint8_t * pt); + +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */ +/*! + * Hash a stream of data with a cryptographic hash algorithm. + * + * The flags in the @a hash_ctx control the operation of this function. + * + * Hashing functions work on 64 octets of message at a time. Therefore, when + * any partial hashing of a long message is performed, the message @a length of + * each segment must be a multiple of 64. When ready to + * #FSL_HASH_FLAGS_FINALIZE the hash, the @a length may be any value. + * + * With the #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_FINALIZE flags on, a + * one-shot complete hash, including padding, will be performed. The @a length + * may be any value. + * + * The first octets of a data stream can be hashed by setting the + * #FSL_HASH_FLAGS_INIT and #FSL_HASH_FLAGS_SAVE flags. The @a length must be + * a multiple of 64. + * + * The flag #FSL_HASH_FLAGS_LOAD is used to load a context previously saved by + * #FSL_HASH_FLAGS_SAVE. The two in combination will allow a (multiple-of-64 + * octets) 'middle sequence' of the data stream to be hashed with the + * beginning. The @a length must again be a multiple of 64. + * + * Since the flag #FSL_HASH_FLAGS_LOAD is used to load a context previously + * saved by #FSL_HASH_FLAGS_SAVE, the #FSL_HASH_FLAGS_LOAD and + * #FSL_HASH_FLAGS_FINALIZE flags, used together, can be used to finish the + * stream. The @a length may be any value. + * + * If the user program wants to do the padding for the hash, it can leave off + * the #FSL_HASH_FLAGS_FINALIZE flag. The @a length must then be a multiple of + * 64 octets. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] hash_ctx Hashing algorithm and state of the cipher. + * @param msg Pointer to the data to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result If not null, pointer to where to store the hash + * digest. + * @param result_len Number of octets to store in @a result. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len); + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */ +/*! + * Precompute the Key hashes for an HMAC operation. + * + * This function may be used to calculate the inner and outer precomputes, + * which are the hash contexts resulting from hashing the XORed key for the + * 'inner hash' and the 'outer hash', respectively, of the HMAC function. + * + * After execution of this function, the @a hmac_ctx will contain the + * precomputed inner and outer contexts, so that they may be used by + * #fsl_shw_hmac(). The flags of @a hmac_ctx will be updated with + * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT to mark their presence. In addition, the + * #FSL_HMAC_FLAGS_INIT flag will be set. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The key being used in this operation. Key must be + * 1 to 64 octets long. + * @param[in,out] hmac_ctx The context which controls, by its flags and + * algorithm, the operation of this function. + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx); + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */ +/*! + * Continue, finalize, or one-shot an HMAC operation. + * + * There are a number of ways to use this function. The flags in the + * @a hmac_ctx object will determine what operations occur. + * + * If #FSL_HMAC_FLAGS_INIT is set, then the hash will be started either from + * the @a key_info, or from the precomputed inner hash value in the + * @a hmac_ctx, depending on the value of #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT. + * + * If, instead, #FSL_HMAC_FLAGS_LOAD is set, then the hash will be continued + * from the ongoing inner hash computation in the @a hmac_ctx. + * + * If #FSL_HMAC_FLAGS_FINALIZE are set, then the @a msg will be padded, hashed, + * the outer hash will be performed, and the @a result will be generated. + * + * If the #FSL_HMAC_FLAGS_SAVE flag is set, then the (ongoing or final) digest + * value will be stored in the ongoing inner hash computation field of the @a + * hmac_ctx. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info If #FSL_HMAC_FLAGS_INIT is set in the @a hmac_ctx, + * this is the key being used in this operation, and the + * IPAD. If #FSL_HMAC_FLAGS_INIT is set in the @a + * hmac_ctx and @a key_info is NULL, then + * #fsl_shw_hmac_precompute() has been used to populate + * the @a inner_precompute and @a outer_precompute + * contexts. If #FSL_HMAC_FLAGS_INIT is not set, this + * parameter is ignored. + + * @param[in,out] hmac_ctx The context which controls, by its flags and + * algorithm, the operation of this function. + * @param msg Pointer to the message to be hashed. + * @param length Length, in octets, of the @a msg. + * @param[out] result Pointer, of @a result_len octets, to where to + * store the HMAC. + * @param result_len Length of @a result buffer. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len); + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +/*! + * Get random data. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length The number of octets of @a data being requested. + * @param[out] data A pointer to a location of @a length octets to where + * random data will be returned. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data); + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +/*! + * Add entropy to random number generator. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param length Number of bytes at @a data. + * @param data Entropy to add to random number generator. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data); + +/*! + * Perform Generation-Encryption by doing a Cipher and a Hash. + * + * Generate the authentication value @a auth_value as well as encrypt the @a + * payload into @a ct (the ciphertext). This is a one-shot function, so all of + * the @a auth_data and the total message @a payload must passed in one call. + * This also means that the flags in the @a auth_ctx must be #FSL_ACCO_CTX_INIT + * and #FSL_ACCO_CTX_FINALIZE. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param auth_ctx Controlling object for Authenticate-decrypt. + * @param cipher_key_info The key being used for the cipher part of this + * operation. In CCM mode, this key is used for + * both parts. + * @param auth_key_info The key being used for the authentication part + * of this operation. In CCM mode, this key is + * ignored and may be NULL. + * @param auth_data_length Length, in octets, of @a auth_data. + * @param auth_data Data to be authenticated but not encrypted. + * @param payload_length Length, in octets, of @a payload. + * @param payload Pointer to the plaintext to be encrypted. + * @param[out] ct Pointer to the where the encrypted @a payload + * will be stored. Must be @a payload_length + * octets long. + * @param[out] auth_value Pointer to where the generated authentication + * field will be stored. Must be as many octets as + * indicated by MAC length in the @a function_ctx. + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value); + +/*! + * Perform Authentication-Decryption in Cipher + Hash. + * + * This function will perform a one-shot decryption of a data stream as well as + * authenticate the authentication value. This is a one-shot function, so all + * of the @a auth_data and the total message @a payload must passed in one + * call. This also means that the flags in the @a auth_ctx must be + * #FSL_ACCO_CTX_INIT and #FSL_ACCO_CTX_FINALIZE. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param auth_ctx Controlling object for Authenticate-decrypt. + * @param cipher_key_info The key being used for the cipher part of this + * operation. In CCM mode, this key is used for + * both parts. + * @param auth_key_info The key being used for the authentication part + * of this operation. In CCM mode, this key is + * ignored and may be NULL. + * @param auth_data_length Length, in octets, of @a auth_data. + * @param auth_data Data to be authenticated but not decrypted. + * @param payload_length Length, in octets, of @a ct and @a pt. + * @param ct Pointer to the encrypted input stream. + * @param auth_value The (encrypted) authentication value which will + * be authenticated. This is the same data as the + * (output) @a auth_value argument to + * #fsl_shw_gen_encrypt(). + * @param[out] payload Pointer to where the plaintext resulting from + * the decryption will be stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * ct, + const uint8_t * auth_value, + uint8_t * payload); + +/*! + * Establish the key in a protected location, which can be the system keystore, + * user keystore, or (on platforms that support it) as a Platform Key. + * + * By default, keys initialized with #fsl_shw_sko_init() will be placed into + * the system keystore. The user can cause the key to be established in a + * user keystore by first calling #fsl_shw_sko_set_keystore() on the key. + * Normally, keys in the system keystore can only be used for hardware + * encrypt or decrypt operations, however if the #FSL_SKO_KEY_SW_KEY flag is + * applied using #fsl_shw_sko_set_flags(), the key will be established as a + * software key, which can then be read out using #fsl_shw_read_key(). + * + * Keys initialized with #fsl_shw_sko_init_pf_key() are established as a + * Platform Key. Their use is covered in @ref di_sec. + * + * This function only needs to be used when unwrapping a key, setting up a key + * which could be wrapped with a later call to #fsl_shw_extract_key(), or + * setting up a key as a Platform Key. Normal cleartext keys can simply be + * placed into #fsl_shw_sko_t key objects with #fsl_shw_sko_set_key() and used + * directly. + * + * The maximum key size supported for wrapped/unwrapped keys is 32 octets. + * (This is the maximum reasonable key length on Sahara - 32 octets for an HMAC + * key based on SHA-256.) The key size is determined by the @a key_info. The + * expected length of @a key can be determined by + * #fsl_shw_sko_calculate_wrapped_size() + * + * The protected key will not be available for use until this operation + * successfully completes. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param[in,out] key_info The information about the key to be which will + * be established. In the create case, the key + * length must be set. + * @param establish_type How @a key will be interpreted to establish a + * key for use. + * @param key If @a establish_type is #FSL_KEY_WRAP_UNWRAP, + * this is the location of a wrapped key. If + * @a establish_type is #FSL_KEY_WRAP_CREATE, this + * parameter can be @a NULL. If @a establish_type + * is #FSL_KEY_WRAP_ACCEPT, this is the location + * of a plaintext key. + */ +extern fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key); + +/*! + * Read the key value from a key object. + * + * Only a key marked as a software key (#FSL_SKO_KEY_SW_KEY) can be read with + * this call. It has no effect on the status of the key store. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The referenced key. + * @param[out] key The location to store the key value. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * key); + +/*! + * Wrap a key and retrieve the wrapped value. + * + * A wrapped key is a key that has been cryptographically obscured. It is + * only able to be used with keys that have been established by + * #fsl_shw_establish_key(). + * + * For keys established in the system or user keystore, this function will + * also release the key (see #fsl_shw_release_key()) so that it must be re- + * established before reuse. This function will not release keys that are + * established as a Platform Key, so a call to #fsl_shw_release_key() is + * necessary to release those keys. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * @param[out] covered_key The location to store the wrapped key. + * (This size is based upon the maximum key size + * of 32 octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key); + +/*! + * De-establish a key so that it can no longer be accessed. + * + * The key will need to be re-established before it can again be used. + * + * This feature is not available for all platforms, nor for all algorithms and + * modes. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * @param key_info The information about the key to be deleted. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info); + +/*! + * Cause the hardware to create a new random key for use by the secure memory + * encryption hardware. + * + * Have the hardware use the secure hardware random number generator to load a + * new secret key into the system's Random Key register. + * + * @param user_ctx A user context from #fsl_shw_register_user(). + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * user_ctx); + +/*! + * Retrieve the detected tamper event. + * + * Note that if more than one event was detected, this routine will only ever + * return one of them. + * + * @param[in] user_ctx A user context from #fsl_shw_register_user(). + * @param[out] tamperp Location to store the tamper information. + * @param[out] timestampp Locate to store timestamp from hardwhare when + * an event was detected. + * + * + * @return A return code of type #fsl_shw_return_t (for instance, if the platform + * is not in a fail state. + */ +extern fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * user_ctx, + fsl_shw_tamper_t * tamperp, + uint64_t * timestampp); + +/*! @} *//* opfuns */ + +/* Insert example code into the API documentation. */ + +/*! + * @example apitest.c + */ + +/*! + * @example sym.c + */ + +/*! + * @example rand.c + */ + +/*! + * @example hash.c + */ + +/*! + * @example hmac1.c + */ + +/*! + * @example hmac2.c + */ + +/*! + * @example gen_encrypt.c + */ + +/*! + * @example auth_decrypt.c + */ + +/*! + * @example wrapped_key.c + */ + +/*! + * @example smalloc.c + */ + +/*! + * @example user_keystore.c + */ + +/*! + * @example dryice.c + */ + +#endif /* API_DOC */ + +#endif /* FSL_SHW_H */ diff --git a/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h b/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h new file mode 100644 index 000000000000..4af6b782af6b --- /dev/null +++ b/drivers/mxc/security/sahara2/include/fsl_shw_keystore.h @@ -0,0 +1,475 @@ +/* + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#ifndef FSL_SHW_KEYSTORE_H +#define FSL_SHW_KEYSTORE_H + +/*! + * @file fsl_shw_keystore.h + * + * @brief Definition of the User Keystore API. + * + */ + +/*! \page user_keystore User Keystore API + * + * Definition of the User Keystore API. + * + * On platforms with multiple partitions of Secure Memory, the Keystore Object + * (#fsl_shw_kso_t) is provided to allow users to manage a private keystore for + * use in software cryptographic routines. The user can define a custom set of + * methods for managing their keystore, or use a default keystore handler. The + * keystore is established by #fsl_shw_establish_keystore(), and released by + * #fsl_shw_release_keystore(). The intent of this design is to make the + * keystore implementation as flexible as possible. + * + * See @ref keystore_api for the generic keystore API, and @ref + * default_keystore for the default keystore implementation. + * + */ + +/*! + * @defgroup keystore_api User Keystore API + * + * Keystore API + * + * These functions define the generic keystore API, which can be used in + * conjunction with a keystore implementation backend to support a user + * keystore. + */ + +/*! + * @defgroup default_keystore Default Keystore Implementation + * + * Default Keystore Implementation + * + * These functions define the default keystore implementation, which is used + * for the system keystore and for user keystores initialized by + * #fsl_shw_init_keystore_default(). They can be used as-is or as a reference + * for creating a custom keystore handler. It uses an entire Secure Memory + * partition, divided in to equal slots of length #KEYSTORE_SLOT_SIZE. These + * functions are not intended to be used directly- all user interaction with + * the keystore should be through the @ref keystore_api and the Wrapped Key + * interface. + * + * The current implementation is designed to work with both SCC and SCC2. + * Differences between the two versions are noted below. + */ + +/*! @addtogroup keystore_api + @{ */ + +#ifndef KEYSTORE_SLOT_SIZE +/*! Size of each key slot, in octets. This sets an upper bound on the size + * of a key that can placed in the keystore. + */ +#define KEYSTORE_SLOT_SIZE 32 +#endif + +/*! + * Initialize a Keystore Object. + * + * This function must be called before performing any other operation with the + * Object. It allows the user to associate a custom keystore interface by + * specifying the correct set of functions that will be used to perform actions + * on the keystore object. To use the default keystore handler, the function + * #fsl_shw_init_keystore_default() can be used instead. + * + * @param keystore The Keystore object to operate on. + * @param data_init Keystore initialization function. This function is + * responsible for initializing the keystore. A + * user-defined object can be assigned to the user_data + * pointer, and will be passed to any function acting on + * that keystore. It is called during + * #fsl_shw_establish_keystore(). + * @param data_cleanup Keystore cleanup function. This function cleans up + * any data structures associated with the keyboard. It + * is called by #fsl_shw_release_keystore(). + * @param slot_alloc Slot allocation function. This function allocates a + * key slot, potentially based on size and owner id. It + * is called by #fsl_shw_establish_key(). + * @param slot_dealloc Slot deallocation function. + * @param slot_verify_access Function to verify that a given Owner ID + * credential matches the given slot. + * @param slot_get_address For SCC2: Get the virtual address (kernel or + * userspace) of the data stored in the slot. + * For SCC: Get the physical address of the data + * stored in the slot. + * @param slot_get_base For SCC2: Get the (virtual) base address of the + * partition that the slot is located on. + * For SCC: Not implemented. + * @param slot_get_offset For SCC2: Get the offset from the start of the + * partition that the slot data is located at (in + * octets) + * For SCC: Not implemented. + * @param slot_get_slot_size Get the size of the key slot, in octets. + */ +extern void fsl_shw_init_keystore(fsl_shw_kso_t * keystore, + fsl_shw_return_t(*data_init) (fsl_shw_uco_t * + user_ctx, + void + **user_data), + void (*data_cleanup) (fsl_shw_uco_t * + user_ctx, + void **user_data), + fsl_shw_return_t(*slot_alloc) (void + *user_data, + uint32_t size, + uint64_t + owner_id, + uint32_t * + slot), + fsl_shw_return_t(*slot_dealloc) (void + *user_data, + uint64_t + owner_id, + uint32_t + slot), + fsl_shw_return_t(*slot_verify_access) (void + *user_data, + uint64_t + owner_id, + uint32_t + slot), + void *(*slot_get_address) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_base) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_offset) (void *user_data, + uint32_t handle), + uint32_t(*slot_get_slot_size) (void + *user_data, + uint32_t + handle)); + +/*! + * Initialize a Keystore Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the user keystore object up to use the default keystore + * handler. If a custom keystore handler is desired, the function + * #fsl_shw_init_keystore() can be used instead. + * + * @param keystore The Keystore object to operate on. + */ +extern void fsl_shw_init_keystore_default(fsl_shw_kso_t * keystore); + +/*! + * Establish a Keystore Object. + * + * This function establishes a keystore object that has been set up by a call + * to #fsl_shw_init_keystore(). It is a wrapper for the user-defined + * data_init() function, which is specified during keystore initialization. + * + * @param user_ctx The user context that this keystore should be attached + * to + * @param keystore The Keystore object to operate on. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t fsl_shw_establish_keystore(fsl_shw_uco_t * user_ctx, + fsl_shw_kso_t * keystore); + +/*! + * Release a Keystore Object. + * + * This function releases an established keystore object. It is a wrapper for + * the user-defined data_cleanup() function, which is specified during keystore + * initialization. + * + * @param user_ctx The user context that this keystore should be attached + * to. + * @param keystore The Keystore object to operate on. + */ +extern void fsl_shw_release_keystore(fsl_shw_uco_t * user_ctx, + fsl_shw_kso_t * keystore); + +/*! + * Allocate a slot in the Keystore. + * + * This function attempts to allocate a slot to hold a key in the keystore. It + * is called by #fsl_shw_establish_key() when establishing a Secure Key Object, + * if the key has been flagged to be stored in a user keystore by the + * #fsl_shw_sko_set_keystore() function. It is a wrapper for the + * implementation-specific function slot_alloc(). + * + * @param keystore The Keystore object to operate on. + * @param[in] size Size of the key to be stored (octets). + * @param[in] owner_id ID of the key owner. + * @param[out] slot If successful, assigned slot ID + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t keystore_slot_alloc(fsl_shw_kso_t * keystore, + uint32_t size, + uint64_t owner_id, uint32_t * slot); + +/*! + * Deallocate a slot in the Keystore. + * + * This function attempts to allocate a slot to hold a key in the keystore. + * It is called by #fsl_shw_extract_key() and #fsl_shw_release_key() when the + * key that it contains is to be released. It is a wrapper for the + * implmentation-specific function slot_dealloc(). + + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot If successful, assigned slot ID. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t keystore_slot_dealloc(fsl_shw_kso_t * keystore, + uint64_t owner_id, uint32_t slot); + +/*! + * Load cleartext key data into a key slot + * + * This function loads a key slot with cleartext data. + * + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot If successful, assigned slot ID. + * @param[in] key_data Pointer to the location of the cleartext key data. + * @param[in] key_length Length of the key data (octets). + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +keystore_slot_load(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + const uint8_t * key_data, uint32_t key_length); + +/*! + * Read cleartext key data from a key slot + * + * This function returns the key in a key slot. + * + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot ID of slot where key resides. + * @param[in] key_length Length of the key data (octets). + * @param[out] key_data Pointer to the location of the cleartext key data. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +keystore_slot_read(fsl_shw_kso_t * keystore, uint64_t owner_id, uint32_t slot, + uint32_t key_length, uint8_t * key_data); + +/*! + * Encrypt a keyslot + * + * This function encrypts a key using the hardware secret key. + * + * @param user_ctx User context + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot Slot ID of the key to encrypt. + * @param[in] length Length of the key + * @param[out] destination Pointer to the location where the encrypted data + * is to be stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +keystore_slot_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_kso_t * keystore, uint64_t owner_id, + uint32_t slot, uint32_t length, uint8_t * destination); + +/*! + * Decrypt a keyslot + * + * This function decrypts a key using the hardware secret key. + * + * @param user_ctx User context + * @param keystore The Keystore object to operate on. + * @param[in] owner_id ID of the key owner. + * @param[in] slot Slot ID of the key to encrypt. + * @param[in] length Length of the key + * @param[in] source Pointer to the location where the encrypted data + * is stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +extern fsl_shw_return_t +keystore_slot_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_kso_t * keystore, uint64_t owner_id, + uint32_t slot, uint32_t length, const uint8_t * source); + +/* @} */ + +/*! @addtogroup default_keystore + @{ */ + +/*! + * Data structure to hold per-slot information + */ +typedef struct keystore_data_slot_info_t { + uint8_t allocated; /*!< Track slot assignments */ + uint64_t owner; /*!< Owner IDs */ + uint32_t key_length; /*!< Size of the key */ +} keystore_data_slot_info_t; + +/*! + * Data structure to hold keystore information. + */ +typedef struct keystore_data_t { + void *base_address; /*!< Base of the Secure Partition */ + uint32_t slot_count; /*!< Number of slots in the keystore */ + struct keystore_data_slot_info_t *slot; /*!< Per-slot information */ +} keystore_data_t; + +/*! + * Default keystore initialization routine. + * + * This function acquires a Secure Partition Object to store the keystore, + * divides it into slots of length #KEYSTORE_SLOT_SIZE, and builds a data + * structure to hold key information. + * + * @param user_ctx User context + * @param[out] user_data Pointer to the location where the keystore data + * structure is to be stored. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t shw_kso_init_data(fsl_shw_uco_t * user_ctx, void **user_data); + +/*! + * Default keystore cleanup routine. + * + * This function releases the Secure Partition Object and the memory holding + * the keystore data structure, that obtained by the shw_kso_init_data + * function. + * + * @param user_ctx User context + * @param[in,out] user_data Pointer to the location where the keystore data + * structure is stored. + */ +void shw_kso_cleanup_data(fsl_shw_uco_t * user_ctx, void **user_data); + +/*! + * Default keystore slot access verification + * + * This function compares the supplied Owner ID to the registered owner of + * the key slot, to see if the supplied ID is correct. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] owner_id Owner ID supplied as a credential. + * @param[in] slot Requested slot + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t shw_slot_verify_access(void *user_data, uint64_t owner_id, + uint32_t slot); + +/*! + * Default keystore slot allocation + * + * This function first checks that the requested size is equal to or less than + * the maximum keystore slot size. If so, it searches the keystore for a free + * key slot, and if found, marks it as used and returns a slot reference to the + * user. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] size Size of the key data that will be stored in this slot + * (octets) + * @param[in] owner_id Owner ID supplied as a credential. + * @param[out] slot Requested slot + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t shw_slot_alloc(void *user_data, uint32_t size, + uint64_t owner_id, uint32_t * slot); + +/*! + * Default keystore slot deallocation + * + * This function releases the given key slot in the keystore, making it + * available to store a new key. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] owner_id Owner ID supplied as a credential. + * @param[in] slot Requested slot + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t shw_slot_dealloc(void *user_data, + uint64_t owner_id, uint32_t slot); + +/*! + * Default keystore slot address lookup + * + * This function calculates the address where the key data is stored. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] slot Requested slot + * + * @return SCC2: Virtual address (kernel or userspace) of the key data. + * SCC: Physical address of the key data. + */ +void *shw_slot_get_address(void *user_data, uint32_t slot); + +/*! + * Default keystore slot base address lookup + * + * This function calculates the base address of the Secure Partition on which + * the key data is located. For the reference design, only one Secure + * Partition is used per Keystore, however in general, any number may be used. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] slot Requested slot + * + * @return SCC2: Secure Partition virtual (kernel or userspace) base address. + * SCC: Secure Partition physical base address. + */ +uint32_t shw_slot_get_base(void *user_data, uint32_t slot); + +/*! + * Default keystore slot offset lookup + * + * This function calculates the offset from the base of the Secure Partition + * where the key data is located. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] slot Requested slot + * + * @return SCC2: Key data offset (octets) + * SCC: Not implemented + */ +uint32_t shw_slot_get_offset(void *user_data, uint32_t slot); + +/*! + * Default keystore slot offset lookup + * + * This function returns the size of the given key slot. In the reference + * implementation, all key slots are of the same size, however in general, + * the keystore slot sizes can be made variable. + * + * @param[in] user_data Pointer to the location where the keystore data + * structure stored. + * @param[in] slot Requested slot + * + * @return SCC2: Keystore slot size. + * SCC: Not implemented + */ +uint32_t shw_slot_get_slot_size(void *user_data, uint32_t slot); + +/* @} */ + +#endif /* FSL_SHW_KEYSTORE_H */ diff --git a/drivers/mxc/security/sahara2/include/linux_port.h b/drivers/mxc/security/sahara2/include/linux_port.h new file mode 100644 index 000000000000..bd65c55c4f7b --- /dev/null +++ b/drivers/mxc/security/sahara2/include/linux_port.h @@ -0,0 +1,1806 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file linux_port.h + * + * OS_PORT ported to Linux (2.6.9+ for now) + * + */ + + /*! + * @if USE_MAINPAGE + * @mainpage ==Linux version of== Generic OS API for STC Drivers + * @endif + * + * @section intro_sec Introduction + * + * This API / kernel programming environment blah blah. + * + * See @ref dkops "Driver-to-Kernel Operations" as a good place to start. + */ + +#ifndef LINUX_PORT_H +#define LINUX_PORT_H + +#define PORTABLE_OS_VERSION 101 + +/* Linux Kernel Includes */ +#include /* Current version Linux kernel */ + +#if defined(CONFIG_MODVERSIONS) && ! defined(MODVERSIONS) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +#include +#endif +#define MODVERSIONS +#endif +/*! + * __NO_VERSION__ defined due to Kernel module possibly spanning multiple + * files. + */ +#define __NO_VERSION__ + +#include /* Basic support for loadable modules, + printk */ +#include /* module_init, module_exit */ +#include /* General kernel system calls */ +#include /* for interrupt.h */ +#include /* for inode */ +#include +#include +#include +#include +#include /* kmalloc */ + +#include + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +#include /* used in dynamic power management */ +#else +#include /* used in dynamic power management */ +#endif + +#include +#include + +#include /* clock en/disable for DPM */ + +#include +#include + +#include /* copy_to_user(), copy_from_user() */ +#include /* ioremap() */ +#include +#include + +#include + +#ifndef TRUE +/*! Useful symbol for unsigned values used as flags. */ +#define TRUE 1 +#endif + +#ifndef FALSE +/*! Useful symbol for unsigned values used as flags. */ +#define FALSE 0 +#endif + +/* These symbols are defined in Linux 2.6 and later. Include here for minimal + * support of 2.4 kernel. + **/ +#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +/*! + * Symbol defined somewhere in 2.5/2.6. It is the return signature of an ISR. + */ +#define irqreturn_t void +/*! Possible return value of 'modern' ISR routine. */ +#define IRQ_HANDLED +/*! Method of generating value of 'modern' ISR routine. */ +#define IRQ_RETVAL(x) +#endif + +/*! + * Type used for registering and deregistering interrupts. + */ +typedef int os_interrupt_id_t; + +/*! + * Type used as handle for a process + * + * See #os_get_process_handle() and #os_send_signal(). + */ +/* + * The following should be defined this way, but it gets compiler errors + * on the current tool chain. + * + * typedef task_t *os_process_handle_t; + */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +typedef task_t *os_process_handle_t; +#else +typedef struct task_struct *os_process_handle_t; +#endif + +/*! + * Generic return code for functions which need such a thing. + * + * No knowledge should be assumed of the value of any of these symbols except + * that @c OS_ERROR_OK_S is guaranteed to be zero. + */ +typedef enum { + OS_ERROR_OK_S = 0, /*!< Success */ + OS_ERROR_FAIL_S = -EIO, /*!< Generic driver failure */ + OS_ERROR_NO_MEMORY_S = -ENOMEM, /*!< Failure to acquire/use memory */ + OS_ERROR_BAD_ADDRESS_S = -EFAULT, /*!< Bad address */ + OS_ERROR_BAD_ARG_S = -EINVAL, /*!< Bad input argument */ +} os_error_code; + +/*! + * Handle to a lock. + */ +#ifdef CONFIG_PREEMPT_RT +typedef raw_spinlock_t *os_lock_t; +#else +typedef spinlock_t *os_lock_t; +#endif + +/*! + * Context while locking. + */ +typedef unsigned long os_lock_context_t; + +/*! + * Declare a wait object for sleeping/waking processes. + */ +#define OS_WAIT_OBJECT(name) \ + DECLARE_WAIT_QUEUE_HEAD(name##_qh) + +/*! + * Driver registration handle + * + * Used with #os_driver_init_registration(), #os_driver_add_registration(), + * and #os_driver_complete_registration(). + */ +typedef struct { + unsigned reg_complete; /*!< TRUE if next inits succeeded. */ + dev_t dev; /*!< dev_t for register_chrdev() */ + struct file_operations fops; /*!< struct for register_chrdev() */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) + struct class_simple *cs; /*!< results of class_simple_create() */ +#else + struct class *cs; /*!< results of class_create() */ +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) + struct class_device *cd; /*!< Result of class_device_create() */ +#else + struct device *cd; /*!< Result of device_create() */ +#endif + unsigned power_complete; /*!< TRUE if next inits succeeded */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + struct device_driver dd; /*!< struct for register_driver() */ +#else + struct platform_driver dd; /*!< struct for register_driver() */ +#endif + struct platform_device pd; /*!< struct for platform_register_device() */ +} os_driver_reg_t; + +/* + * Function types which can be associated with driver entry points. + * + * Note that init and shutdown are absent. + */ +/*! @{ */ +/*! Keyword for registering open() operation handler. */ +#define OS_FN_OPEN open +/*! Keyword for registering close() operation handler. */ +#define OS_FN_CLOSE release +/*! Keyword for registering read() operation handler. */ +#define OS_FN_READ read +/*! Keyword for registering write() operation handler. */ +#define OS_FN_WRITE write +/*! Keyword for registering ioctl() operation handler. */ +#define OS_FN_IOCTL ioctl +/*! Keyword for registering mmap() operation handler. */ +#define OS_FN_MMAP mmap +/*! @} */ + +/*! + * Function signature for the portable interrupt handler + * + * While it would be nice to know which interrupt is being serviced, the + * Least Common Denominator rule says that no arguments get passed in. + * + * @return Zero if not handled, non-zero if handled. + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +typedef int (*os_interrupt_handler_t) (int, void *, struct pt_regs *); +#else +typedef int (*os_interrupt_handler_t) (int, void *); +#endif + +/*! + * @defgroup dkops Driver-to-Kernel Operations + * + * These are the operations which drivers should call to get the OS to perform + * services. + */ + +/*! @addtogroup dkops */ +/*! @{ */ + +/*! + * Register an interrupt handler. + * + * @param driver_name The name of the driver + * @param interrupt_id The interrupt line to monitor (type + * #os_interrupt_id_t) + * @param function The function to be called to handle an interrupt + * + * @return #os_error_code + */ +#define os_register_interrupt(driver_name, interrupt_id, function) \ + request_irq(interrupt_id, function, 0, driver_name, NULL) + +/*! + * Deregister an interrupt handler. + * + * @param interrupt_id The interrupt line to stop monitoring + * + * @return #os_error_code + */ +#define os_deregister_interrupt(interrupt_id) \ + free_irq(interrupt_id, NULL) + +/*! + * INTERNAL implementation of os_driver_init_registration() + * + * @return An os error code. + */ +inline static int os_drv_do_init_reg(os_driver_reg_t * handle) +{ + memset(handle, 0, sizeof(*handle)); + handle->fops.owner = THIS_MODULE; + handle->power_complete = FALSE; + handle->reg_complete = FALSE; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + handle->dd.name = NULL; +#else + handle->dd.driver.name = NULL; +#endif + + return OS_ERROR_OK_S; +} + +/*! + * Initialize driver registration. + * + * If the driver handles open(), close(), ioctl(), read(), write(), or mmap() + * calls, then it needs to register their location with the kernel so that they + * get associated with the device. + * + * @param handle The handle object to be used with this registration. The + * object must live (be in memory somewhere) at least until + * os_driver_remove_registration() is called. + * + * @return A handle for further driver registration, or NULL if failed. + */ +#define os_driver_init_registration(handle) \ + os_drv_do_init_reg(&handle) + +/*! + * Add a function registration to driver registration. + * + * @param handle A handle initialized by #os_driver_init_registration(). + * @param name Which function is being supported. + * @param function The result of a call to a @c _REF version of one of the + * driver function signature macros + * @return void + */ +#define os_driver_add_registration(handle, name, function) \ + do {handle.fops.name = (void*)(function); } while (0) + +/*! + * Record 'power suspend' function for the device. + * + * @param handle A handle initialized by #os_driver_init_registration(). + * @param function Name of function to call on power suspend request + * + * Status: Provisional + * + * @return void + */ +#define os_driver_register_power_suspend(handle, function) \ + handle.dd.suspend = function + +/*! + * Record 'power resume' function for the device. + * + * @param handle A handle initialized by #os_driver_init_registration(). + * @param function Name of function to call on power resume request + * + * Status: Provisional + * + * @return void + */ +#define os_driver_register_resume(handle, function) \ + handle.dd.resume = function + +/*! + * INTERNAL function of the Linux port of the OS API. Implements the + * os_driver_complete_registration() function. + * + * @param handle The handle used with #os_driver_init_registration(). + * @param major The major device number to be associated with the driver. + * If this value is zero, a major number may be assigned. + * See #os_driver_get_major() to determine final value. + * #os_driver_remove_registration(). + * @param driver_name The driver name. Can be used as part of 'device node' + * name on platforms which support such a feature. + * + * @return An error code + */ +inline static int os_drv_do_reg(os_driver_reg_t * handle, + unsigned major, char *driver_name) +{ + os_error_code code = OS_ERROR_NO_MEMORY_S; + char *name = kmalloc(strlen(driver_name) + 1, 0); + + if (name != NULL) { + memcpy(name, driver_name, strlen(driver_name) + 1); + code = OS_ERROR_OK_S; /* OK so far */ + /* If any chardev/POSIX routines were added, then do chrdev part */ + if (handle->fops.open || handle->fops.release + || handle->fops.read || handle->fops.write + || handle->fops.ioctl || handle->fops.mmap) { + + printk("ioctl pointer: %p. mmap pointer: %p\n", + handle->fops.ioctl, handle->fops.mmap); + + /* this method is depricated, see: + * http://lwn.net/Articles/126808/ + */ + code = + register_chrdev(major, driver_name, &handle->fops); + + /* instead something like this: */ +#if 0 + handle->dev = MKDEV(major, 0); + code = + register_chrdev_region(handle->dev, 1, driver_name); + if (code < 0) { + code = OS_ERROR_FAIL_S; + } else { + cdev_init(&handle->cdev, &handle->fops); + code = cdev_add(&handle->cdev, major, 1); + } +#endif + + if (code < 0) { + code = OS_ERROR_FAIL_S; + } else { + if (code != 0) { + /* Zero was passed in for major; code is actual value */ + handle->dev = MKDEV(code, 0); + } else { + handle->dev = MKDEV(major, 0); + } + code = OS_ERROR_OK_S; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) + handle->cs = + class_simple_create(THIS_MODULE, + driver_name); + if (IS_ERR(handle->cs)) { + code = (os_error_code) handle->cs; + handle->cs = NULL; + } else { + handle->cd = + class_simple_device_add(handle->cs, + handle->dev, + NULL, + driver_name); + if (IS_ERR(handle->cd)) { + class_simple_device_remove + (handle->dev); + unregister_chrdev(MAJOR + (handle->dev), + driver_name); + code = + (os_error_code) handle->cs; + handle->cs = NULL; + } else { + handle->reg_complete = TRUE; + } + } +#else + handle->cs = + class_create(THIS_MODULE, driver_name); + if (IS_ERR(handle->cs)) { + code = (os_error_code) handle->cs; + handle->cs = NULL; + } else { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) + handle->cd = + class_device_create(handle->cs, + NULL, + handle->dev, + NULL, + driver_name); +#else + handle->cd = + device_create(handle->cs, NULL, + handle->dev, NULL, + driver_name); +#endif + if (IS_ERR(handle->cd)) { + class_destroy(handle->cs); + unregister_chrdev(MAJOR + (handle->dev), + driver_name); + code = + (os_error_code) handle->cs; + handle->cs = NULL; + } else { + handle->reg_complete = TRUE; + } + } +#endif + } + } + /* ... fops routine registered */ + /* Handle power management fns through separate interface */ + if ((code == OS_ERROR_OK_S) && + (handle->dd.suspend || handle->dd.resume)) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + handle->dd.name = name; + handle->dd.bus = &platform_bus_type; + code = driver_register(&handle->dd); +#else + handle->dd.driver.name = name; + handle->dd.driver.bus = &platform_bus_type; + code = driver_register(&handle->dd.driver); +#endif + if (code == OS_ERROR_OK_S) { + handle->pd.name = name; + handle->pd.id = 0; + code = platform_device_register(&handle->pd); + if (code != OS_ERROR_OK_S) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + driver_unregister(&handle->dd); +#else + driver_unregister(&handle->dd.driver); +#endif + } else { + handle->power_complete = TRUE; + } + } + } /* ... suspend or resume */ + } /* name != NULL */ + return code; +} + +/*! + * Finalize the driver registration with the kernel. + * + * Upon return from this call, the driver may begin receiving calls at the + * defined entry points. + * + * @param handle The handle used with #os_driver_init_registration(). + * @param major The major device number to be associated with the driver. + * If this value is zero, a major number may be assigned. + * See #os_driver_get_major() to determine final value. + * #os_driver_remove_registration(). + * @param driver_name The driver name. Can be used as part of 'device node' + * name on platforms which support such a feature. + * + * @return An error code + */ +#define os_driver_complete_registration(handle, major, driver_name) \ + os_drv_do_reg(&handle, major, driver_name) + +/*! + * Get driver Major Number from handle after a successful registration. + * + * @param handle A handle which has completed registration. + * + * @return The major number (if any) associated with the handle. + */ +#define os_driver_get_major(handle) \ + (handle.reg_complete ? MAJOR(handle.dev) : -1) + +/*! + * INTERNAL implemention of os_driver_remove_registration. + * + * @param handle A handle initialized by #os_driver_init_registration(). + * + * @return An error code. + */ +inline static int os_drv_rmv_reg(os_driver_reg_t * handle) +{ + if (handle->reg_complete) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) + if (handle->cd != NULL) { + class_simple_device_remove(handle->dev); + handle->cd = NULL; + } + if (handle->cs != NULL) { + class_simple_destroy(handle->cs); + handle->cs = NULL; + } + unregister_chrdev(MAJOR(handle->dev), handle->dd.name); +#else + if (handle->cd != NULL) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) + class_device_destroy(handle->cs, handle->dev); +#else + device_destroy(handle->cs, handle->dev); +#endif + handle->cd = NULL; + } + if (handle->cs != NULL) { + class_destroy(handle->cs); + handle->cs = NULL; + } + unregister_chrdev(MAJOR(handle->dev), handle->dd.driver.name); +#endif + handle->reg_complete = FALSE; + } + if (handle->power_complete) { + platform_device_unregister(&handle->pd); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + driver_unregister(&handle->dd); +#else + driver_unregister(&handle->dd.driver); +#endif + handle->power_complete = FALSE; + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + if (handle->dd.name != NULL) { + kfree(handle->dd.name); + handle->dd.name = NULL; + } +#else + if (handle->dd.driver.name != NULL) { + kfree(handle->dd.driver.name); + handle->dd.driver.name = NULL; + } +#endif + return OS_ERROR_OK_S; +} + +/*! + * Remove the driver's registration with the kernel. + * + * Upon return from this call, the driver not receive any more calls at the + * defined entry points (other than ISR and shutdown). + * + * @param handle A handle initialized by #os_driver_init_registration(). + * + * @return An error code. + */ +#define os_driver_remove_registration(handle) \ + os_drv_rmv_reg(&handle) + +/*! + * Register a driver with the Linux Device Model. + * + * @param driver_information The device_driver structure information + * + * @return An error code. + * + * Status: denigrated in favor of #os_driver_complete_registration() + */ +#define os_register_to_driver(driver_information) \ + driver_register(driver_information) + +/*! + * Unregister a driver from the Linux Device Model + * + * this routine unregisters from the Linux Device Model + * + * @param driver_information The device_driver structure information + * + * @return An error code. + * + * Status: Denigrated. See #os_register_to_driver(). + */ +#define os_unregister_from_driver(driver_information) \ + driver_unregister(driver_information) + +/*! + * register a device to a driver + * + * this routine registers a drivers devices to the Linux Device Model + * + * @param device_information The platform_device structure information + * + * @return An error code. + * + * Status: denigrated in favor of #os_driver_complete_registration() + */ +#define os_register_a_device(device_information) \ + platform_device_register(device_information) + +/*! + * unregister a device from a driver + * + * this routine unregisters a drivers devices from the Linux Device Model + * + * @param device_information The platform_device structure information + * + * @return An error code. + * + * Status: Denigrated. See #os_register_a_device(). + */ +#define os_unregister_a_device(device_information) \ + platform_device_unregister(device_information) + +/*! + * Print a message to console / into log file. After the @c msg argument a + * number of printf-style arguments may be added. Types should be limited to + * printf string, char, octal, decimal, and hexadecimal types. (This excludes + * pointers, and floating point). + * + * @param msg The main text of the message to be logged + * @param s The printf-style arguments which go with msg, if any + * + * @return (void) + */ +#define os_printk(...) \ + (void) printk(__VA_ARGS__) + +/*! + * Prepare a task to execute the given function. This should only be done once + * per function,, during the driver's initialization routine. + * + * @param task_fn Name of the OS_DEV_TASK() function to be created. + * + * @return an OS ERROR code. + */ +#define os_create_task(function_name) \ + OS_ERROR_OK_S + +/*! + * Schedule execution of a task. + * + * @param function_name The function associated with the task. + * + * @return (void) + */ +#define os_dev_schedule_task(function_name) \ + tasklet_schedule(&(function_name ## let)) + +/*! + * Make sure that task is no longer running and will no longer run. + * + * This function will not return until both are true. This is useful when + * shutting down a driver. + */ +#define os_dev_stop_task(function_name) \ +do { \ + tasklet_disable(&(function_name ## let)); \ + tasklet_kill(&(function_name ## let)); \ +} while (0) + +/*! + * Allocate some kernel memory + * + * @param amount Number of 8-bit bytes to allocate + * @param flags Some indication of purpose of memory (needs definition) + * + * @return Pointer to allocated memory, or NULL if failed. + */ +#define os_alloc_memory(amount, flags) \ + (void*)kmalloc(amount, flags) + +/*! + * Free some kernel memory + * + * @param location The beginning of the region to be freed. + * + * Do some OSes have separate free() functions which should be + * distinguished by passing in @c flags here, too? Don't some also require the + * size of the buffer being freed? + */ +#define os_free_memory(location) \ + kfree(location) + +/*! + * Allocate cache-coherent memory + * + * @param amount Number of bytes to allocate + * @param[out] dma_addrp Location to store physical address of allocated + * memory. + * @param flags Some indication of purpose of memory (needs + * definition). + * + * @return (virtual space) pointer to allocated memory, or NULL if failed. + * + */ +#define os_alloc_coherent(amount, dma_addrp, flags) \ + (void*)dma_alloc_coherent(NULL, amount, dma_addrp, flags) + +/*! + * Free cache-coherent memory + * + * @param size Number of bytes which were allocated. + * @param virt_addr Virtual(kernel) address of memory.to be freed, as + * returned by #os_alloc_coherent(). + * @param dma_addr Physical address of memory.to be freed, as returned + * by #os_alloc_coherent(). + * + * @return void + * + */ +#define os_free_coherent(size, virt_addr, dma_addr) \ + dma_free_coherent(NULL, size, virt_addr, dma_addr + +/*! + * Map an I/O space into kernel memory space + * + * @param start The starting address of the (physical / io space) region + * @param range_bytes The number of bytes to map + * + * @return A pointer to the mapped area, or NULL on failure + */ +#define os_map_device(start, range_bytes) \ + (void*)ioremap_nocache((start), range_bytes) + +/*! + * Unmap an I/O space from kernel memory space + * + * @param start The starting address of the (virtual) region + * @param range_bytes The number of bytes to unmap + * + * @return None + */ +#define os_unmap_device(start, range_bytes) \ + iounmap((void*)(start)) + +/*! + * Copy data from Kernel space to User space + * + * @param to The target location in user memory + * @param from The source location in kernel memory + * @param size The number of bytes to be copied + * + * @return #os_error_code + */ +#define os_copy_to_user(to, from, size) \ + ((copy_to_user(to, from, size) == 0) ? 0 : OS_ERROR_BAD_ADDRESS_S) + +/*! + * Copy data from User space to Kernel space + * + * @param to The target location in kernel memory + * @param from The source location in user memory + * @param size The number of bytes to be copied + * + * @return #os_error_code + */ +#define os_copy_from_user(to, from, size) \ + ((copy_from_user(to, from, size) == 0) ? 0 : OS_ERROR_BAD_ADDRESS_S) + +/*! + * Read a 8-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +#define os_read8(register_address) \ + __raw_readb(register_address) + +/*! + * Write a 8-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +#define os_write8(register_address, value) \ + __raw_writeb(value, register_address) + +/*! + * Read a 16-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +#define os_read16(register_address) \ + __raw_readw(register_address) + +/*! + * Write a 16-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +#define os_write16(register_address, value) \ + __raw_writew(value, (uint32_t*)(register_address)) + +/*! + * Read a 32-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +#define os_read32(register_address) \ + __raw_readl((uint32_t*)(register_address)) + +/*! + * Write a 32-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +#define os_write32(register_address, value) \ + __raw_writel(value, register_address) + +/*! + * Read a 64-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +#define os_read64(register_address) \ + ERROR_UNIMPLEMENTED + +/*! + * Write a 64-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +#define os_write64(register_address, value) \ + ERROR_UNIMPLEMENTED + +/*! + * Delay some number of microseconds + * + * Note that this is a busy-loop, not a suspension of the task/process. + * + * @param msecs The number of microseconds to delay + * + * @return void + */ +#define os_mdelay mdelay + +/*! + * Calculate virtual address from physical address + * + * @param pa Physical address + * + * @return virtual address + * + * @note this assumes that addresses are 32 bits wide + */ +#define os_va __va + +/*! + * Calculate physical address from virtual address + * + * + * @param va Virtual address + * + * @return physical address + * + * @note this assumes that addresses are 32 bits wide + */ +#define os_pa __pa + +#ifdef CONFIG_PREEMPT_RT +/*! + * Allocate and initialize a lock, returning a lock handle. + * + * The lock state will be initialized to 'unlocked'. + * + * @return A lock handle, or NULL if an error occurred. + */ +inline static os_lock_t os_lock_alloc_init(void) +{ + raw_spinlock_t *lockp; + lockp = (raw_spinlock_t *) kmalloc(sizeof(raw_spinlock_t), 0); + if (lockp) { + _raw_spin_lock_init(lockp); + } else { + printk("OS: lock init failed\n"); + } + + return lockp; +} +#else +/*! + * Allocate and initialize a lock, returning a lock handle. + * + * The lock state will be initialized to 'unlocked'. + * + * @return A lock handle, or NULL if an error occurred. + */ +inline static os_lock_t os_lock_alloc_init(void) +{ + spinlock_t *lockp; + lockp = (spinlock_t *) kmalloc(sizeof(spinlock_t), 0); + if (lockp) { + spin_lock_init(lockp); + } else { + printk("OS: lock init failed\n"); + } + + return lockp; +} +#endif /* CONFIG_PREEMPT_RT */ + +/*! + * Acquire a lock. + * + * This function should only be called from an interrupt service routine. + * + * @param lock_handle A handle to the lock to acquire. + * + * @return void + */ +#define os_lock(lock_handle) \ + spin_lock(lock_handle) + +/*! + * Unlock a lock. Lock must have been acquired by #os_lock(). + * + * @param lock_handle A handle to the lock to unlock. + * + * @return void + */ +#define os_unlock(lock_handle) \ + spin_unlock(lock_handle) + +/*! + * Acquire a lock in non-ISR context + * + * This function will spin until the lock is available. + * + * @param lock_handle A handle of the lock to acquire. + * @param context Place to save the before-lock context + * + * @return void + */ +#define os_lock_save_context(lock_handle, context) \ + spin_lock_irqsave(lock_handle, context) + +/*! + * Release a lock in non-ISR context + * + * @param lock_handle A handle of the lock to release. + * @param context Place where before-lock context was saved. + * + * @return void + */ +#define os_unlock_restore_context(lock_handle, context) \ + spin_unlock_irqrestore(lock_handle, context) + +/*! + * Deallocate a lock handle. + * + * @param lock_handle An #os_lock_t that has been allocated. + * + * @return void + */ +#define os_lock_deallocate(lock_handle) \ + kfree(lock_handle) + +/*! + * Determine process handle + * + * The process handle of the current user is returned. + * + * @return A handle on the current process. + */ +#define os_get_process_handle() \ + current + +/*! + * Send a signal to a process + * + * @param proc A handle to the target process. + * @param sig The POSIX signal to send to that process. + */ +#define os_send_signal(proc, sig) \ + send_sig(sig, proc, 0); + +/*! + * Get some random bytes + * + * @param buf The location to store the random data. + * @param count The number of bytes to store. + * + * @return void + */ +#define os_get_random_bytes(buf, count) \ + get_random_bytes(buf, count) + +/*! + * Go to sleep on an object. + * + * @param object The object on which to sleep + * @param condition An expression to check for sleep completion. Must be + * coded so that it can be referenced more than once inside + * macro, i.e., no ++ or other modifying expressions. + * @param atomic Non-zero if sleep must not return until condition. + * + * @return error code -- OK or sleep interrupted?? + */ +#define os_sleep(object, condition, atomic) \ +({ \ + DEFINE_WAIT(_waitentry_); \ + os_error_code code = OS_ERROR_OK_S; \ + \ + while (!(condition)) { \ + prepare_to_wait(&(object##_qh), &_waitentry_, \ + atomic ? 0 : TASK_INTERRUPTIBLE); \ + if (!(condition)) { \ + schedule(); \ + } \ + \ + finish_wait(&(object##_qh), &_waitentry_); \ + \ + if (!atomic && signal_pending(current)) { \ + code = OS_ERROR_FAIL_S; /* NEED SOMETHING BETTER */ \ + break; \ + } \ + }; \ + \ + code; \ +}) + +/*! + * Wake up whatever is sleeping on sleep object + * + * @param object The object on which things might be sleeping + * + * @return none + */ +#define os_wake_sleepers(object) \ + wake_up_interruptible(&(object##_qh)); + + /*! @} *//* dkops */ + +/****************************************************************************** + * Function signature-generating macros + *****************************************************************************/ + +/*! + * @defgroup drsigs Driver Signatures + * + * These macros will define the entry point signatures for interrupt handlers; + * driver initialization and shutdown; device open/close; etc. + * + * There are two versions of each macro for a given Driver Entry Point. The + * first version is used to define a function and its implementation in the + * driver.c file, e.g. #OS_DEV_INIT(). + * + * The second form is used whenever a forward declaration (prototype) is + * needed. It has the letters @c _DCL appended to the name of the defintion + * function, and takes only the first two arguments (driver_name and + * function_name). These are not otherwise mentioned in this documenation. + * + * There is a third form used when a reference to a function is required, for + * instance when passing the routine as a pointer to a function. It has the + * letters @c _REF appended to it, and takes only the first two arguments + * (driver_name and function_name). These functions are not otherwise + * mentioned in this documentation. + * + * (Note that these two extra forms are required because of the + * possibility/likelihood of having a 'wrapper function' which invokes the + * generic function with expected arguments. An alternative would be to have a + * generic function which isn't able to get at any arguments directly, but + * would be equipped with macros which could get at information passed in. + * + * Example: + * + * (in a header file) + * @code + * OS_DEV_INIT_DCL(widget, widget_init); + * @endcode + * + * (in an implementation file) + * @code + * OS_DEV_INIT(widget, widget_init) + * { + * os_dev_init_return(TRUE); + * } + * @endcode + * + */ + +/*! @addtogroup drsigs */ +/*! @{ */ + +/*! + * Define a function which will handle device initialization + * + * This is tne driver initialization routine. This is normally where the + * part would be initialized; queues, locks, interrupts handlers defined; + * long-term dynamic memory allocated for driver use; etc. + * + * @param function_name The name of the portable initialization function. + * + * @return A call to #os_dev_init_return() + * + */ +#define OS_DEV_INIT(function_name) \ +module_init(function_name); \ +static int __init function_name (void) + +/*! Make declaration for driver init function. + * @param function_name foo + */ +#define OS_DEV_INIT_DCL(function_name) \ +static int __init function_name (void); + +/*! + * Generate a function reference to the driver's init function. + * @param function_name Name of the OS_DEV_INIT() function. + * + * @return A function pointer. + */ +#define OS_DEV_INIT_REF(function_name) \ +function_name + +/*! + * Define a function which will handle device shutdown + * + * This is the inverse of the #OS_DEV_INIT() routine. + * + * @param function_name The name of the portable driver shutdown routine. + * + * @return A call to #os_dev_shutdown_return() + * + */ +#define OS_DEV_SHUTDOWN(function_name) \ +module_exit(function_name); \ +static void function_name(void) + +/*! + * Generate a function reference to the driver's shutdown function. + * @param function_name Name of the OS_DEV_HUSTDOWN() function. + * + * @return A function pointer. + */ +#define OS_DEV_SHUTDOWN_DCL(function_name) \ +static void function_name(void); + +/*! + * Generate a reference to driver's shutdown function + * @param function_name Name of the OS_DEV_HUSTDOWN() function. +*/ + +#define OS_DEV_SHUTDOWN_REF(function_name) \ +function_name + +/*! + * Define a function which will open the device for a user. + * + * @param function_name The name of the driver open() function + * + * @return A call to #os_dev_open_return() + */ +#define OS_DEV_OPEN(function_name) \ +static int function_name(struct inode* inode_p_, struct file* file_p_) + +/*! + * Declare prototype for an open() function. + * + * @param function_name The name of the OS_DEV_OPEN() function. + */ +#define OS_DEV_OPEN_DCL(function_name) \ +OS_DEV_OPEN(function_name); + +/*! + * Generate a function reference to the driver's open() function. + * @param function_name Name of the OS_DEV_OPEN() function. + * + * @return A function pointer. + */ +#define OS_DEV_OPEN_REF(function_name) \ +function_name + +/*! + * Define a function which will handle a user's ioctl() request + * + * @param function_name The name of the driver ioctl() function + * + * @return A call to #os_dev_ioctl_return() + */ +#define OS_DEV_IOCTL(function_name) \ +static int function_name(struct inode* inode_p_, struct file* file_p_, \ + unsigned int cmd_, unsigned long data_) + +/*! Boo. */ +#define OS_DEV_IOCTL_DCL(function_name) \ +OS_DEV_IOCTL(function_name); + +/*! + * Generate a function reference to the driver's ioctl() function. + * @param function_name Name of the OS_DEV_IOCTL() function. + * + * @return A function pointer. + */ +#define OS_DEV_IOCTL_REF(function_name) \ +function_name + +/*! + * Define a function which will handle a user's mmap() request + * + * @param function_name The name of the driver mmap() function + * + * @return A call to #os_dev_ioctl_return() + */ +#define OS_DEV_MMAP(function_name) \ +int function_name(struct file* file_p_, struct vm_area_struct* vma_) + +#define OS_DEV_MMAP_DCL(function_name) \ +OS_DEV_MMAP(function_name); + +#define OS_DEV_MMAP_REF(function_name) \ +function_name + +/* Retrieve the context to the memory structure that is to be MMAPed */ +#define os_mmap_memory_ctx() (vma_) + +/* Determine the size of the requested MMAP region*/ +#define os_mmap_memory_size() (vma_->vm_end - vma_->vm_start) + +/* Determine the base address of the requested MMAP region*/ +#define os_mmap_user_base() (vma_->vm_start) + +/*! + * Declare prototype for an read() function. + * + * @param function_name The name of the driver read function. + */ +#define OS_DEV_READ_DCL(function_name) \ +OS_DEV_READ(function_name); + +/*! + * Generate a function reference to the driver's read() routine + * @param function_name Name of the OS_DEV_READ() function. + * + * @return A function pointer. + */ +#define OS_DEV_READ_REF(function_name) \ +function_name + +/*! + * Define a function which will handle a user's write() request + * + * @param function_name The name of the driver write() function + * + * @return A call to #os_dev_write_return() + */ +#define OS_DEV_WRITE(function_name) \ +static ssize_t function_name(struct file* file_p_, char* user_buffer_, \ + size_t count_bytes_, loff_t* file_position_) + +/*! + * Declare prototype for an write() function. + * + * @param function_name The name of the driver write function. + */ +#define OS_DEV_WRITE_DCL(function_name) \ +OS_DEV_WRITE(function_name); + +/*! + * Generate a function reference to the driver's write() routine + * @param function_name Name of the OS_DEV_WRITE() function. + * + * @return A function pointer. + */ +#define OS_DEV_WRITE_REF(function_name) \ +function_name + +/*! + * Define a function which will close the device - opposite of OS_DEV_OPEN() + * + * @param function_name The name of the driver close() function + * + * @return A call to #os_dev_close_return() + */ +#define OS_DEV_CLOSE(function_name) \ +static int function_name(struct inode* inode_p_, struct file* file_p_) + +/*! + * Declare prototype for an close() function + * + * @param function_name The name of the driver close() function. + */ +#define OS_DEV_CLOSE_DCL(function_name) \ +OS_DEV_CLOSE(function_name); + +/*! + * Generate a function reference to the driver's close function. + * @param function_name Name of the OS_DEV_CLOSE() function. + * + * @return A function pointer. + */ +#define OS_DEV_CLOSE_REF(function_name) \ +function_name + +/*! + * Define a function which will handle an interrupt + * + * No arguments are available to the generic function. It must not invoke any + * OS functions which are illegal in a ISR. It gets no parameters, and must + * have a call to #os_dev_isr_return() instead of any/all return statements. + * + * Example: + * @code + * OS_DEV_ISR(widget) + * { + * os_dev_isr_return(1); + * } + * @endcode + * + * @param function_name The name of the driver ISR function + * + * @return A call to #os_dev_isr_return() + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +#define OS_DEV_ISR(function_name) \ +static irqreturn_t function_name(int N1_, void* N2_, struct pt_regs* N3_) +#else +#define OS_DEV_ISR(function_name) \ +static irqreturn_t function_name(int N1_, void* N2_) +#endif + +/*! + * Declare prototype for an ISR function. + * + * @param function_name The name of the driver ISR function. + */ +#define OS_DEV_ISR_DCL(function_name) \ +OS_DEV_ISR(function_name); + +/*! + * Generate a function reference to the driver's interrupt service routine + * @param function_name Name of the OS_DEV_ISR() function. + * + * @return A function pointer. + */ +#define OS_DEV_ISR_REF(function_name) \ +function_name + +/*! + * Define a function which will operate as a background task / bottom half. + * + * Tasklet stuff isn't strictly limited to 'Device drivers', but leave it + * this namespace anyway. + * + * @param function_name The name of this background task function + * + * @return A call to #os_dev_task_return() + */ +#define OS_DEV_TASK(function_name) \ +static void function_name(unsigned long data_) + +/*! + * Declare prototype for a background task / bottom half function + * + * @param function_name The name of this background task function + */ +#define OS_DEV_TASK_DCL(function_name) \ +OS_DEV_TASK(function_name); \ +DECLARE_TASKLET(function_name ## let, function_name, 0); + +/*! + * Generate a reference to an #OS_DEV_TASK() function + * + * @param function_name The name of the task being referenced. + */ +#define OS_DEV_TASK_REF(function_name) \ + (function_name ## let) + + /*! @} *//* drsigs */ + +/***************************************************************************** + * Functions/Macros for returning values from Driver Signature routines + *****************************************************************************/ + +/*! + * Return from the #OS_DEV_INIT() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_init_return(code) \ + return code + +/*! + * Return from the #OS_DEV_SHUTDOWN() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_shutdown_return(code) \ + return + +/*! + * Return from the #OS_DEV_ISR() function + * + * The function should verify that it really was supposed to be called, + * and that its device needed attention, in order to properly set the + * return code. + * + * @param code non-zero if interrupt handled, zero otherwise. + * + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) +#define os_dev_isr_return(code) \ +do { \ + /* Unused warnings */ \ + (void)N1_; \ + (void)N2_; \ + (void)N3_; \ + \ + return IRQ_RETVAL(code); \ +} while (0) +#else +#define os_dev_isr_return(code) \ +do { \ + /* Unused warnings */ \ + (void)N1_; \ + (void)N2_; \ + \ + return IRQ_RETVAL(code); \ +} while (0) +#endif + +/*! + * Return from the #OS_DEV_OPEN() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_open_return(code) \ +do { \ + int retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)inode_p_; \ + (void)file_p_; \ + \ + return retcode; \ +} while (0) + +/*! + * Return from the #OS_DEV_IOCTL() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_ioctl_return(code) \ +do { \ + int retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)inode_p_; \ + (void)file_p_; \ + (void)cmd_; \ + (void)data_; \ + \ + return retcode; \ +} while (0) + +/*! + * Return from the #OS_DEV_READ() function + * + * @param code Number of bytes read, or an error code to report failure. + * + */ +#define os_dev_read_return(code) \ +do { \ + ssize_t retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)file_p_; \ + (void)user_buffer_; \ + (void)count_bytes_; \ + (void)file_position_; \ + \ + return retcode; \ +} while (0) + +/*! + * Return from the #OS_DEV_WRITE() function + * + * @param code Number of bytes written, or an error code to report failure. + * + */ +#define os_dev_write_return(code) \ +do { \ + ssize_t retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)file_p_; \ + (void)user_buffer_; \ + (void)count_bytes_; \ + (void)file_position_; \ + \ + return retcode; \ +} while (0) + +/*! + * Return from the #OS_DEV_CLOSE() function + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_close_return(code) \ +do { \ + ssize_t retcode = code; \ + \ + /* get rid of 'unused parameter' warnings */ \ + (void)inode_p_; \ + (void)file_p_; \ + \ + return retcode; \ +} while (0) + +/*! + * Start the #OS_DEV_TASK() function + * + * In some implementations, this could be turned into a label for + * the os_dev_task_return() call. + * + * @return none + */ +#define os_dev_task_begin() + +/*! + * Return from the #OS_DEV_TASK() function + * + * In some implementations, this could be turned into a sleep followed + * by a jump back to the os_dev_task_begin() call. + * + * @param code An error code to report success or failure. + * + */ +#define os_dev_task_return(code) \ +do { \ + /* Unused warnings */ \ + (void)data_; \ + \ + return; \ +} while (0) + +/***************************************************************************** + * Functions/Macros for accessing arguments from Driver Signature routines + *****************************************************************************/ + +/*! @defgroup drsigargs Functions for Getting Arguments in Signature functions + * + */ +/* @addtogroup @drsigargs */ +/*! @{ */ +/*! + * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and + * #OS_DEV_WRITE() routines to check whether user is requesting read + * (permission) + */ +#define os_dev_is_flag_read() \ + (file_p_->f_mode & FMODE_READ) + +/*! + * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and + * #OS_DEV_WRITE() routines to check whether user is requesting write + * (permission) + */ +#define os_dev_is_flag_write() \ + (file_p_->f_mode & FMODE_WRITE) + +/*! + * Used in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and + * #OS_DEV_WRITE() routines to check whether user is requesting non-blocking + * I/O. + */ +#define os_dev_is_flag_nonblock() \ + (file_p_->f_flags & (O_NONBLOCK | O_NDELAY)) + +/*! + * Used in #OS_DEV_OPEN() and #OS_DEV_CLOSE() to determine major device being + * accessed. + */ +#define os_dev_get_major() \ + (imajor(inode_p_)) + +/*! + * Used in #OS_DEV_OPEN() and #OS_DEV_CLOSE() to determine minor device being + * accessed. + */ +#define os_dev_get_minor() \ + (iminor(inode_p_)) + +/*! + * Used in #OS_DEV_IOCTL() to determine which operation the user wants + * performed. + * + * @return Value of the operation. + */ +#define os_dev_get_ioctl_op() \ + (cmd_) + +/*! + * Used in #OS_DEV_IOCTL() to return the associated argument for the desired + * operation. + * + * @return A value which can be cast to a struct pointer or used as + * int/long. + */ +#define os_dev_get_ioctl_arg() \ + (data_) + +/*! + * Used in OS_DEV_READ() and OS_DEV_WRITE() routines to access the requested + * byte count. + * + * @return (unsigned) a count of bytes + */ +#define os_dev_get_count() \ + ((unsigned)count_bytes_) + +/*! + * Used in OS_DEV_READ() and OS_DEV_WRITE() routines to return the pointer + * byte count. + * + * @return char* pointer to user buffer + */ +#define os_dev_get_user_buffer() \ + ((void*)user_buffer_) + +/*! + * Used in OS_DEV_READ(), OS_DEV_WRITE(), and OS_DEV_IOCTL() routines to + * get the POSIX flags field for the associated open file). + * + * @return The flags associated with the file. + */ +#define os_dev_get_file_flags() \ + (file_p_->f_flags) + +/*! + * Set the driver's private structure associated with this file/open. + * + * Generally used during #OS_DEV_OPEN(). See #os_dev_get_user_private(). + * + * @param struct_p The driver data structure to associate with this user. + */ +#define os_dev_set_user_private(struct_p) \ + file_p_->private_data = (void*)(struct_p) + +/*! + * Get the driver's private structure associated with this file. + * + * May be used during #OS_DEV_OPEN(), #OS_DEV_READ(), #OS_DEV_WRITE(), + * #OS_DEV_IOCTL(), and #OS_DEV_CLOSE(). See #os_dev_set_user_private(). + * + * @return The driver data structure to associate with this user. + */ +#define os_dev_get_user_private() \ + ((void*)file_p_->private_data) + +/*! + * Get the IRQ associated with this call to the #OS_DEV_ISR() function. + * + * @return The IRQ (integer) interrupt number. + */ +#define os_dev_get_irq() \ + N1_ + + /*! @} *//* drsigargs */ + +/*! + * @defgroup cacheops Cache Operations + * + * These functions are for synchronizing processor cache with RAM. + */ +/*! @addtogroup cacheops */ +/*! @{ */ + +/*! + * Flush and invalidate all cache lines. + */ +#if 0 +#define os_flush_cache_all() \ + flush_cache_all() +#else +/* Call ARM fn directly, in case L2cache=on3 not set */ +#define os_flush_cache_all() \ + v6_flush_kern_cache_all_L2() + +/*! + * ARM-routine to flush all cache. Defined here, because it exists in no + * easy-access header file. ARM-11 with L210 cache only! + */ +extern void v6_flush_kern_cache_all_L2(void); +#endif + +/* + * These macros are using part of the Linux DMA API. They rely on the + * map function to do nothing more than the equivalent clean/inv/flush + * operation at the time of the mapping, and do nothing at an unmapping + * call, which the Sahara driver code will never invoke. + */ + +/*! + * Clean a range of addresses from the cache. That is, write updates back + * to (RAM, next layer). + * + * @param start Starting virtual address + * @param len Number of bytes to flush + * + * @return void + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +#define os_cache_clean_range(start,len) \ + dma_map_single(NULL, (void*)start, len, DMA_TO_DEVICE) +#else +#define os_cache_clean_range(start,len) \ +{ \ + void *s = (void*)start; \ + void *e = s + len; \ + dmac_map_area(s, len, DMA_TO_DEVICE); \ + outer_clean_range(__pa(s), __pa(e)); \ +} +#endif + +/*! + * Invalidate a range of addresses in the cache + * + * @param start Starting virtual address + * @param len Number of bytes to flush + * + * @return void + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +#define os_cache_inv_range(start,len) \ + dma_map_single(NULL, (void*)start, len, DMA_FROM_DEVICE) +#else +#define os_cache_inv_range(start,len) \ +{ \ + void *s = (void*)start; \ + void *e = s + len; \ + dmac_unmap_area(s, len, DMA_FROM_DEVICE); \ + outer_inv_range(__pa(s), __pa(e)); \ +} +#endif + +/*! + * Flush a range of addresses from the cache. That is, perform clean + * and invalidate + * + * @param start Starting virtual address + * @param len Number of bytes to flush + * + * @return void + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) +#define os_cache_flush_range(start,len) \ + dma_map_single(NULL, (void*)start, len, DMA_BIDIRECTIONAL) +#else +#define os_cache_flush_range(start,len) \ +{ \ + void *s = (void*)start; \ + void *e = s + len; \ + dmac_flush_range(s, e); \ + outer_flush_range(__pa(s), __pa(e)); \ +} +#endif + + /*! @} *//* cacheops */ + +#endif /* LINUX_PORT_H */ diff --git a/drivers/mxc/security/sahara2/include/platform_abstractions.h b/drivers/mxc/security/sahara2/include/platform_abstractions.h new file mode 100644 index 000000000000..5fc87ccc5161 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/platform_abstractions.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @file platform_abstractions.h + */ diff --git a/drivers/mxc/security/sahara2/include/portable_os.h b/drivers/mxc/security/sahara2/include/portable_os.h new file mode 100644 index 000000000000..445acd5d420c --- /dev/null +++ b/drivers/mxc/security/sahara2/include/portable_os.h @@ -0,0 +1,1453 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef PORTABLE_OS_H +#define PORTABLE_OS_H + +/***************************************************************************/ + +/* + * Add support for your target OS by checking appropriate flags and then + * including the appropriate file. Don't forget to document the conditions + * in the later documentation section at the beginning of the + * DOXYGEN_PORTABLE_OS_DOC. + */ + +#if defined(LINUX_KERNEL) + +#include "linux_port.h" + +#elif defined(PORTABLE_OS) + +#include "check_portability.h" + +#else + +#error Target OS unsupported or unspecified + +#endif + + +/***************************************************************************/ + +/*! + * @file portable_os.h + * + * This file should be included by portable driver code in order to gain access + * to the OS-specific header files. It is the only OS-related header file that + * the writer of a portable driver should need. + * + * This file also contains the documentation for the common API. + * + * Begin reading the documentation for this file at the @ref index "main page". + * + */ + +/*! + * @if USE_MAINPAGE + * @mainpage Generic OS API for STC Drivers + * @endif + * + * @section intro_sec Introduction + * + * This defines the API / kernel programming environment for portable drivers. + * + * This API is broken up into several functional areas. It greatly limits the + * choices of a device-driver author, but at the same time should allow for + * greater portability of the resulting code. + * + * Each kernel-to-driver function (initialization function, interrupt service + * routine, etc.) has a 'portable signature' which must be used, and a specific + * function which must be called to generate the return statement. There is + * one exception, a background task or "bottom half" routine, which instead has + * a specific structure which must be followed. These signatures and function + * definitions are found in @ref drsigs. + * + * None of these kernel-to-driver functions seem to get any arguments passed to + * them. Instead, there are @ref drsigargs which allow one of these functions + * to get at fairly generic parts of its calling arguments, if there are any. + * + * Almost every driver will have some need to call the operating system + * @ref dkops is the list of services which are available to the driver. + * + * + * @subsection warn_sec Warning + * + * The specifics of the types, values of the various enumerations + * (unless specifically stated, like = 0), etc., are only here for illustrative + * purposes. No attempts should be made to make use of any specific knowledge + * gleaned from this documentation. These types are only meant to be passed in + * and out of the API, and their contents are to be handled only by the + * provided OS-specific functions. + * + * Also, note that the function may be provided as macros in some + * implementations, or vice versa. + * + * + * @section dev_sec Writing a Portable Driver + * + * First off, writing a portable driver means calling no function in an OS + * except what is available through this header file. + * + * Secondly, all OS-called functions in your driver must be invoked and + * referenced through the signature routines. + * + * Thirdly, there might be some rules which you can get away with ignoring or + * violating on one OS, yet will cause your code not to be portable to a + * different OS. + * + * + * @section limit_sec Limitations + * + * This API is not expected to handle every type of driver which may be found + * in an operating system. For example, it will not be able to handle the + * usual design for something like a UART driver, where there are multiple + * logical devices to access, because the design usually calls for some sort of + * indication to the #OS_DEV_TASK() function or OS_DEV_ISR() to indicate which + * channel is to be serviced by that instance of the task/function. This sort + * of argument is missing in this API for functions like os_dev_schedule_task() and + * os_register_interrupt(). + * + * + * @section port_guide Porting Guidelines + * + * This section is intended for a developer who needs to port the header file + * to an operating system which is not yet supported. + * + * This interface allows for a lot of flexibility when it comes to porting to + * an operating systems device driver interface. There are three main areas to + * examine: The use of Driver Routine Signatures, the use of Driver Argument + * Access functions, the Calls to Kernel Functions, and Data Types. + * + * + * @subsection port_sig Porting Driver Routine Signatures + * + * The three macros for each function (e.g. #OS_DEV_INIT(), #OS_DEV_INIT_DCL(), + * and #OS_DEV_INIT_REF()) allow the flexibility of having a 'wrapper' function + * with the OS-required signature, which would then call the user's function + * with some different signature. + * + * The first form would lay down the wrapper function, followed by the + * signature for the user function. The second form would lay down just the + * signatures for both functions, and the last function would reference the + * wrapper function, since that is the interface function called by the OS. + * + * Note that the driver author has no visibility at all to the signature of the + * routines. The author can access arguments only through a limited set of + * functions, and must return via another function. + * + * The Return Functions allow a lot of flexibility in converting the return + * value, or not returning a value at all. These will likely be implemented as + * macros. + * + * + * @subsection port_arg Porting Driver Argument Access Functions + * + * The signatures defined by the guide will usually be replaced with macro + * definitions. + * + * + * @subsection port_dki Porting Calls to Kernel Functions + * + * The signatures defined by the guide may be replaced with macro definitions, + * if that makes more sense. + * + * Implementors are free to ignore arguments which are not applicable to their + * OS. + * + * @subsection port_datatypes Porting Data Types + * + * + */ + +/*************************************************************************** + * Compile flags + **************************************************************************/ + +/* + * This compile flag should only be turned on when running doxygen to generate + * the API documentation. + */ +#ifdef DOXYGEN_PORTABLE_OS_DOC + +/*! + * @todo module_init()/module_cleanup() for Linux need to be added to OS + * abstractions. Also need EXPORT_SYMBOL() equivalent?? + * + */ + +/* Drop OS differentation documentation here */ + +/*! + * \#define this flag to build your driver as a Linux driver + */ +#define LINUX + +/* end OS differentation documentation */ + +/*! + * Symbol to give version number of the implementation file. Earliest + * definition is in version 1.1, with value 101 (to mean version 1.1) + */ +#define PORTABLE_OS_VERSION 101 + +/* + * NOTICE: The following definitions (the rest of the file) are not meant ever + * to be compiled. Instead, they are the documentation for the portable OS + * API, to be used by driver writers. + * + * Each individual OS port will define each of these types, functions, or + * macros as appropriate to the target OS. This is why they are under the + * DOXYGEN_PORTABLE_OS_DOC flag. + */ + +/*************************************************************************** + * Type definitions + **************************************************************************/ + +/*! + * Type used for registering and deregistering interrupts. + * + * This is typically an interrupt channel number. + */ +typedef int os_interrupt_id_t; + +/*! + * Type used as handle for a process + * + * See #os_get_process_handle() and #os_send_signal(). + */ +typedef int os_process_handle_t; + +/*! + * Generic return code for functions which need such a thing. + * + * No knowledge should be assumed of the value of any of these symbols except + * that @c OS_ERROR_OK_S is guaranteed to be zero. + * + * @todo Any other named values? What about (-EAGAIN? -ERESTARTSYS? Are they + * too Linux/Unix-specific read()/write() return values) ? + */ +typedef enum { + OS_ERROR_OK_S = 0, /*!< Success */ + OS_ERROR_FAIL_S, /*!< Generic driver failure */ + OS_ERROR_NO_MEMORY_S, /*!< Failure to acquire/use memory */ + OS_ERROR_BAD_ADDRESS_S, /*!< Bad address */ + OS_ERROR_BAD_ARG_S /*!< Bad input argument */ +} os_error_code; + +/*! + * Handle to a lock. + */ +typedef int *os_lock_t; + +/*! + * Context while locking. + */ +typedef int os_lock_context_t; + +/*! + * An object which can be slept on and later used to wake any/all sleepers. + */ +typedef int os_sleep_object_t; + +/*! + * Driver registration handle + */ +typedef void *os_driver_reg_t; + +/*! + * Function signature for an #OS_DEV_INIT() function. + * + * @return A call to os_dev_init_return() function. + */ +typedef void (*os_init_function_t) (void); + +/*! + * Function signature for an #OS_DEV_SHUTDOWN() function. + * + * @return A call to os_dev_shutdown_return() function. + */ +typedef void (*os_shutdown_function_t) (void); + +/*! + * Function signature for a user-driver function. + * + * @return A call to the appropriate os_dev_xxx_return() function. + */ +typedef void (*os_user_function_t) (void); + +/*! + * Function signature for the portable interrupt handler + * + * While it would be nice to know which interrupt is being serviced, the + * Least Common Denominator rule says that no arguments get passed in. + * + * @return A call to #os_dev_isr_return() + */ +typedef void (*os_interrupt_handler_t) (void); + +/*! + * Function signature for a task function + * + * Many task function definitions get some sort of generic argument so that the + * same function can run across many (queues, channels, ...) as separate task + * instances. This has been left out of this API. + * + * This function must be structured as documented by #OS_DEV_TASK(). + * + */ +typedef void (*os_task_fn_t) (void); + +/*! + * Function types which can be associated with driver entry points. These are + * used in os_driver_add_registration(). + * + * Note that init and shutdown are absent. + */ +typedef enum { + OS_FN_OPEN, /*!< open() operation handler. */ + OS_FN_CLOSE, /*!< close() operation handler. */ + OS_FN_READ, /*!< read() operation handler. */ + OS_FN_WRITE, /*!< write() operation handler. */ + OS_FN_IOCTL, /*!< ioctl() operation handler. */ + OS_FN_MMAP /*!< mmap() operation handler. */ +} os_driver_fn_t; + +/*************************************************************************** + * Driver-to-Kernel Operations + **************************************************************************/ + +/*! + * @defgroup dkops Driver-to-Kernel Operations + * + * These are the operations which drivers should call to get the OS to perform + * services. + */ + +/*! @addtogroup dkops */ +/*! @{ */ + +/*! + * Register an interrupt handler. + * + * @param driver_name The name of the driver + * @param interrupt_id The interrupt line to monitor (type + * #os_interrupt_id_t) + * @param function The function to be called to handle an interrupt + * + * @return #os_error_code + */ +os_error_code os_register_interrupt(char *driver_name, + os_interrupt_id_t interrupt_id, + os_interrupt_handler_t function); + +/*! + * Deregister an interrupt handler. + * + * @param interrupt_id The interrupt line to stop monitoring + * + * @return #os_error_code + */ +os_error_code os_deregister_interrupt(os_interrupt_id_t interrupt_id); + +/*! + * Initialize driver registration. + * + * If the driver handles open(), close(), ioctl(), read(), write(), or mmap() + * calls, then it needs to register their location with the kernel so that they + * get associated with the device. + * + * @param handle The handle object to be used with this registration. The + * object must live (be in memory somewhere) at least until + * os_driver_remove_registration() is called. + * + * @return An os error code. + */ +os_error_code os_driver_init_registration(os_driver_reg_t handle); + +/*! + * Add a function registration to driver registration. + * + * @param handle The handle used with #os_driver_init_registration(). + * @param name Which function is being supported. + * @param function The result of a call to a @c _REF version of one of the + * driver function signature macros + * driver function signature macros + * @return void + */ +void os_driver_add_registration(os_driver_reg_t handle, os_driver_fn_t name, + void *function); + +/*! + * Finalize the driver registration with the kernel. + * + * Upon return from this call, the driver may begin receiving calls at the + * defined entry points. + * + * @param handle The handle used with #os_driver_init_registration(). + * @param major The major device number to be associated with the driver. + * If this value is zero, a major number may be assigned. + * See #os_driver_get_major() to determine final value. + * #os_driver_remove_registration(). + * @param driver_name The driver name. Can be used as part of 'device node' + * name on platforms which support such a feature. + * + * @return An error code + */ +os_error_code os_driver_complete_registration(os_driver_reg_t handle, + int major, char *driver_name); + +/*! + * Get driver Major Number from handle after a successful registration. + * + * @param handle A handle which has completed registration. + * + * @return The major number (if any) associated with the handle. + */ +uint32_t os_driver_get_major(os_driver_reg_t handle); + +/*! + * Remove the driver's registration with the kernel. + * + * Upon return from this call, the driver not receive any more calls at the + * defined entry points (other than ISR and shutdown). + * + * @param major The major device number to be associated with the driver. + * @param driver_name The driver name + * + * @return An error code. + */ +os_error_code os_driver_remove_registration(int major, char *driver_name); + +/*! + * Print a message to console / into log file. After the @c msg argument a + * number of printf-style arguments may be added. Types should be limited to + * printf string, char, octal, decimal, and hexadecimal types. (This excludes + * pointers, and floating point). + * + * @param msg The message to print to console / system log + * + * @return (void) + */ +void os_printk(char *msg, ...); + +/*! + * Allocate some kernel memory + * + * @param amount Number of 8-bit bytes to allocate + * @param flags Some indication of purpose of memory (needs definition) + * + * @return Pointer to allocated memory, or NULL if failed. + */ +void *os_alloc_memory(unsigned amount, int flags); + +/*! + * Free some kernel memory + * + * @param location The beginning of the region to be freed. + * + * Do some OSes have separate free() functions which should be + * distinguished by passing in @c flags here, too? Don't some also require the + * size of the buffer being freed? Perhaps separate routines for each + * alloc/free pair (DMAable, etc.)? + */ +void os_free_memory(void *location); + +/*! + * Allocate cache-coherent memory + * + * @param amount Number of bytes to allocate + * @param[out] dma_addrp Location to store physical address of allocated + * memory. + * @param flags Some indication of purpose of memory (needs + * definition). + * + * @return (virtual space) pointer to allocated memory, or NULL if failed. + * + */ +void *os_alloc_coherent(unsigned amount, uint32_t * dma_addrp, int flags); + +/*! + * Free cache-coherent memory + * + * @param size Number of bytes which were allocated. + * @param[out] virt_addr Virtual(kernel) address of memory.to be freed, as + * returned by #os_alloc_coherent(). + * @param[out] dma_addr Physical address of memory.to be freed, as returned + * by #os_alloc_coherent(). + * + * @return void + * + */ +void os_free_coherent(unsigned size, void *virt_addr, uint32_t dma_addr); + +/*! + * Map an I/O space into kernel memory space + * + * @param start The starting address of the (physical / io space) region + * @param range_bytes The number of bytes to map + * + * @return A pointer to the mapped area, or NULL on failure + */ +void *os_map_device(uint32_t start, unsigned range_bytes); + +/*! + * Unmap an I/O space from kernel memory space + * + * @param start The starting address of the (virtual) region + * @param range_bytes The number of bytes to unmap + * + * @return None + */ +void os_unmap_device(void *start, unsigned range_bytes); + +/*! + * Copy data from Kernel space to User space + * + * @param to The target location in user memory + * @param from The source location in kernel memory + * @param size The number of bytes to be copied + * + * @return #os_error_code + */ +os_error_code os_copy_to_user(void *to, void *from, unsigned size); + +/*! + * Copy data from User space to Kernel space + * + * @param to The target location in kernel memory + * @param from The source location in user memory + * @param size The number of bytes to be copied + * + * @return #os_error_code + */ +os_error_code os_copy_from_user(void *to, void *from, unsigned size); + +/*! + * Read an 8-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +uint8_t os_read8(uint8_t * register_address); + +/*! + * Write an 8-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +void os_write8(uint8_t * register_address, uint8_t value); + +/*! + * Read a 16-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +uint16_t os_read16(uint16_t * register_address); + +/*! + * Write a 16-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +void os_write16(uint16_t * register_address, uint16_t value); + +/*! + * Read a 32-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +uint32_t os_read32(uint32_t * register_address); + +/*! + * Write a 32-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +void os_write32(uint32_t * register_address, uint32_t value); + +/*! + * Read a 64-bit device register + * + * @param register_address The (bus) address of the register to write to + * @return The value in the register + */ +uint64_t os_read64(uint64_t * register_address); + +/*! + * Write a 64-bit device register + * + * @param register_address The (bus) address of the register to write to + * @param value The value to write into the register + */ +void os_write64(uint64_t * register_address, uint64_t value); + +/*! + * Prepare a task to execute the given function. This should only be done once + * per task, during the driver's initialization routine. + * + * @param task_fn Name of the OS_DEV_TASK() function to be created. + * + * @return an OS ERROR code. + */ +os_error os_create_task(os_task_fn_t * task_fn); + +/*! + * Run the task associated with an #OS_DEV_TASK() function + * + * The task will begin execution sometime after or during this call. + * + * @param task_fn Name of the OS_DEV_TASK() function to be scheduled. + * + * @return void + */ +void os_dev_schedule_task(os_task_fn_t * task_fn); + +/*! + * Make sure that task is no longer running and will no longer run. + * + * This function will not return until both are true. This is useful when + * shutting down a driver. + * + * @param task_fn Name of the OS_DEV_TASK() funciton to be stopped. + * + */ +void os_stop_task(os_task_fn_t * task_fn); + +/*! + * Delay some number of microseconds + * + * Note that this is a busy-loop, not a suspension of the task/process. + * + * @param msecs The number of microseconds to delay + * + * @return void + */ +void os_mdelay(unsigned long msecs); + +/*! + * Calculate virtual address from physical address + * + * @param pa Physical address + * + * @return virtual address + * + * @note this assumes that addresses are 32 bits wide + */ +void *os_va(uint32_t pa); + +/*! + * Calculate physical address from virtual address + * + * + * @param va Virtual address + * + * @return physical address + * + * @note this assumes that addresses are 32 bits wide + */ +uint32_t os_pa(void *va); + +/*! + * Allocate and initialize a lock, returning a lock handle. + * + * The lock state will be initialized to 'unlocked'. + * + * @return A lock handle, or NULL if an error occurred. + */ +os_lock_t os_lock_alloc_init(void); + +/*! + * Acquire a lock. + * + * This function should only be called from an interrupt service routine. + * + * @param lock_handle A handle to the lock to acquire. + * + * @return void + */ +void os_lock(os_lock_t lock_handle); + +/*! + * Unlock a lock. Lock must have been acquired by #os_lock(). + * + * @param lock_handle A handle to the lock to unlock. + * + * @return void + */ +void os_unlock(os_lock_t lock_handle); + +/*! + * Acquire a lock in non-ISR context + * + * This function will spin until the lock is available. + * + * @param lock_handle A handle of the lock to acquire. + * @param context Place to save the before-lock context + * + * @return void + */ +void os_lock_save_context(os_lock_t lock_handle, os_lock_context_t context); + +/*! + * Release a lock in non-ISR context + * + * @param lock_handle A handle of the lock to release. + * @param context Place where before-lock context was saved. + * + * @return void + */ +void os_unlock_restore_context(os_lock_t lock_handle, + os_lock_context_t context); + +/*! + * Deallocate a lock handle. + * + * @param lock_handle An #os_lock_t that has been allocated. + * + * @return void + */ +void os_lock_deallocate(os_lock_t lock_handle); + +/*! + * Determine process handle + * + * The process handle of the current user is returned. + * + * @return A handle on the current process. + */ +os_process_handle_t os_get_process_handle(); + +/*! + * Send a signal to a process + * + * @param proc A handle to the target process. + * @param sig The POSIX signal to send to that process. + */ +void os_send_signal(os_process_handle_t proc, int sig); + +/*! + * Get some random bytes + * + * @param buf The location to store the random data. + * @param count The number of bytes to store. + * + * @return void + */ +void os_get_random_bytes(void *buf, unsigned count); + +/*! + * Go to sleep on an object. + * + * Example: code = os_sleep(my_queue, available_count == 0, 0); + * + * @param object The object on which to sleep + * @param condition An expression to check for sleep completion. Must be + * coded so that it can be referenced more than once inside + * macro, i.e., no ++ or other modifying expressions. + * @param atomic Non-zero if sleep must not return until condition. + * + * @return error code -- OK or sleep interrupted?? + */ +os_error_code os_sleep(os_sleep_object_t object, unsigned condition, + unsigned atomic); + +/*! + * Wake up whatever is sleeping on sleep object + * + * @param object The object on which things might be sleeping + * + * @return none + */ +void os_wake_sleepers(os_sleep_object_t object); + + /*! @} *//* dkops */ + +/***************************************************************************** + * Function-signature-generating macros + *****************************************************************************/ + +/*! + * @defgroup drsigs Driver Function Signatures + * + * These macros will define the entry point signatures for interrupt handlers; + * driver initialization and shutdown; device open/close; etc. They are to be + * used whenever the Kernel will call into the Driver. They are not + * appropriate for driver calls to other routines in the driver. + * + * There are three versions of each macro for a given Driver Entry Point. The + * first version is used to define a function and its implementation in the + * driver.c file, e.g. #OS_DEV_INIT(). + * + * The second form is used whenever a forward declaration (prototype) is + * needed. It has the letters @c _DCL appended to the name of the definition + * function. These are not otherwise mentioned in this documenation. + * + * There is a third form used when a reference to a function is required, for + * instance when passing the routine as a pointer to a function. It has the + * letters @c _REF appended to the name of the definition function + * (e.g. DEV_IOCTL_REF). + * + * Note that these two extra forms are required because of the possibility of + * having an invisible 'wrapper function' created by the os-specific header + * file which would need to be invoked by the operating system, and which in + * turn would invoke the generic function. + * + * Example: + * + * (in a header file) + * @code + * OS_DEV_INIT_DCL(widget_init); + * OS_DEV_ISR_DCL(widget_isr); + * @endcode + * + * (in an implementation file) + * @code + * OS_DEV_INIT(widget, widget_init) + * { + * + * os_register_interrupt("widget", WIDGET_IRQ, OS_DEV_ISR_REF(widget_isr)); + * + * os_dev_init_return(OS_RETURN_NO_ERROR_S); + * } + * + * OS_DEV_ISR(widget_isr) + * { + * os_dev_isr_return(TRUE); + * } + * @endcode + */ + +/*! @addtogroup drsigs */ +/*! @{ */ + +/*! + * Define a function which will handle device initialization + * + * This is tne driver initialization routine. This is normally where the + * part would be initialized; queues, locks, interrupts handlers defined; + * long-term dynamic memory allocated for driver use; etc. + * + * @param function_name The name of the portable initialization function. + * + * @return A call to #os_dev_init_return() + * + */ +#define OS_DEV_INIT(function_name) + +/*! + * Define a function which will handle device shutdown + * + * This is the reverse of the #OS_DEV_INIT() routine. + * + * @param function_name The name of the portable driver shutdown routine. + * + * @return A call to #os_dev_shutdown_return() + */ +#define OS_DEV_SHUTDOWN(function_name) + +/*! + * Define a function which will open the device for a user. + * + * @param function_name The name of the driver open() function + * + * @return A call to #os_dev_open_return() + */ +#define OS_DEV_OPEN(function_name) + +/*! + * Define a function which will handle a user's ioctl() request + * + * @param function_name The name of the driver ioctl() function + * + * @return A call to #os_dev_ioctl_return() + */ +#define OS_DEV_IOCTL(function_name) + +/*! + * Define a function which will handle a user's read() request + * + * @param function_name The name of the driver read() function + * + * @return A call to #os_dev_read_return() + */ +#define OS_DEV_READ(function_name) + +/*! + * Define a function which will handle a user's write() request + * + * @param function_name The name of the driver write() function + * + * @return A call to #os_dev_write_return() + */ +#define OS_DEV_WRITE(function_name) + +/*! + * Define a function which will handle a user's mmap() request + * + * The mmap() function requests the driver to map some memory into user space. + * + * @todo Determine what support functions are needed for mmap() handling. + * + * @param function_name The name of the driver mmap() function + * + * @return A call to #os_dev_mmap_return() + */ +#define OS_DEV_MMAP(function_name) + +/*! + * Define a function which will close the device - opposite of OS_DEV_OPEN() + * + * @param function_name The name of the driver close() function + * + * @return A call to #os_dev_close_return() + */ +#define OS_DEV_CLOSE(function_name) + +/*! + * Define a function which will handle an interrupt + * + * No arguments are available to the generic function. It must not invoke any + * OS functions which are illegal in a ISR. It gets no parameters, and must + * have a call to #os_dev_isr_return() instead of any/all return statements. + * + * Example: + * @code + * OS_DEV_ISR(widget, widget_isr, WIDGET_IRQ_NUMBER) + * { + * os_dev_isr_return(1); + * } + * @endcode + * + * @param function_name The name of the driver ISR function + * + * @return A call to #os_dev_isr_return() + */ +#define OS_DEV_ISR(function_name) + +/*! + * Define a function which will operate as a background task / bottom half. + * + * The function implementation must be structured in the following manner: + * @code + * OS_DEV_TASK(widget_task) + * { + * OS_DEV_TASK_SETUP(widget_task); + * + * while OS_DEV_TASK_CONDITION(widget_task) } + * + * }; + * } + * @endcode + * + * @todo In some systems the OS_DEV_TASK_CONDITION() will be an action which + * will cause the task to sleep on some event triggered by os_run_task(). In + * others, the macro will reference a variable laid down by + * OS_DEV_TASK_SETUP() to make sure that the loop is only performed once. + * + * @param function_name The name of this background task function + */ +#define OS_DEV_TASK(function_name) + + /*! @} *//* drsigs */ + +/*! @defgroup dclsigs Routines to declare Driver Signature routines + * + * These macros drop prototypes suitable for forward-declaration of + * @ref drsigs "function signatures". + */ + +/*! @addtogroup dclsigs */ +/*! @{ */ + +/*! + * Declare prototype for the device initialization function + * + * @param function_name The name of the portable initialization function. + */ +#define OS_DEV_INIT_DCL(function_name) + +/*! + * Declare prototype for the device shutdown function + * + * @param function_name The name of the portable driver shutdown routine. + * + * @return A call to #os_dev_shutdown_return() + */ +#define OS_DEV_SHUTDOWN_DCL(function_name) + +/*! + * Declare prototype for the open() function. + * + * @param function_name The name of the driver open() function + * + * @return A call to #os_dev_open_return() + */ +#define OS_DEV_OPEN_DCL(function_name) + +/*! + * Declare prototype for the user's ioctl() request function + * + * @param function_name The name of the driver ioctl() function + * + * @return A call to #os_dev_ioctl_return() + */ +#define OS_DEV_IOCTL_DCL(function_name) + +/*! + * Declare prototype for the function a user's read() request + * + * @param function_name The name of the driver read() function + */ +#define OS_DEV_READ_DCL(function_name) + +/*! + * Declare prototype for the user's write() request function + * + * @param function_name The name of the driver write() function + */ +#define OS_DEV_WRITE_DCL(function_name) + +/*! + * Declare prototype for the user's mmap() request function + * + * @param function_name The name of the driver mmap() function + */ +#define OS_DEV_MMAP_DCL(function_name) + +/*! + * Declare prototype for the close function + * + * @param function_name The name of the driver close() function + * + * @return A call to #os_dev_close_return() + */ +#define OS_DEV_CLOSE_DCL(function_name) + +/*! + * Declare prototype for the interrupt handling function + * + * @param function_name The name of the driver ISR function + */ +#define OS_DEV_ISR_DCL(function_name) + +/*! + * Declare prototype for a background task / bottom half function + * + * @param function_name The name of this background task function + */ +#define OS_DEV_TASK_DCL(function_name) + + /*! @} *//* dclsigs */ + +/***************************************************************************** + * Functions for Returning Values from Driver Signature routines + *****************************************************************************/ + +/*! + * @defgroup retfns Functions to Return Values from Driver Signature routines + */ + +/*! @addtogroup retfns */ +/*! @{ */ + +/*! + * Return from the #OS_DEV_INIT() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_init_return(os_error_code code); + +/*! + * Return from the #OS_DEV_SHUTDOWN() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_shutdown_return(os_error_code code); + +/*! + * Return from the #OS_DEV_ISR() function + * + * The function should verify that it really was supposed to be called, + * and that its device needed attention, in order to properly set the + * return code. + * + * @param code non-zero if interrupt handled, zero otherwise. + * + */ +void os_dev_isr_return(int code); + +/*! + * Return from the #OS_DEV_OPEN() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_open_return(os_error_code code); + +/*! + * Return from the #OS_DEV_IOCTL() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_ioctl_return(os_error_code code); + +/*! + * Return from the #OS_DEV_READ() function + * + * @param code Number of bytes read, or an error code to report failure. + * + */ +void os_dev_read_return(os_error_code code); + +/*! + * Return from the #OS_DEV_WRITE() function + * + * @param code Number of bytes written, or an error code to report failure. + * + */ +void os_dev_write_return(os_error_code code); + +/*! + * Return from the #OS_DEV_MMAP() function + * + * @param code Number of bytes written, or an error code to report failure. + * + */ +void os_dev_mmap_return(os_error_code code); + +/*! + * Return from the #OS_DEV_CLOSE() function + * + * @param code An error code to report success or failure. + * + */ +void os_dev_close_return(os_error_code code); + +/*! + * Start the #OS_DEV_TASK() function + * + * In some implementations, this could be turned into a label for + * the os_dev_task_return() call. + * + * For a more portable interface, should this take the sleep object as an + * argument??? + * + * @return none + */ +void os_dev_task_begin(void); + +/*! + * Return from the #OS_DEV_TASK() function + * + * In some implementations, this could be turned into a sleep followed + * by a jump back to the os_dev_task_begin() call. + * + * @param code An error code to report success or failure. + * + */ +void os_dev_task_return(os_error_code code); + + /*! @} *//* retfns */ + +/***************************************************************************** + * Functions/Macros for accessing arguments from Driver Signature routines + *****************************************************************************/ + +/*! @defgroup drsigargs Functions for Getting Arguments in Signature functions + * + */ +/* @addtogroup @drsigargs */ +/*! @{ */ + +/*! + * Check whether user is requesting read (permission) on the file/device. + * Usable in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() + * and #OS_DEV_WRITE() routines. + */ +int os_dev_is_flag_read(void); + +/*! + * Check whether user is requesting write (permission) on the file/device. + * Usable in #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() + * and #OS_DEV_WRITE() routines. + */ +int os_dev_is_flag_write(void); + +/*! + * Check whether user is requesting non-blocking I/O. Usable in + * #OS_DEV_OPEN(), #OS_DEV_CLOSE(), #OS_DEV_IOCTL(), #OS_DEV_READ() and + * #OS_DEV_WRITE() routines. + * + * @todo Specify required behavior when nonblock is requested and (sufficient?) + * data are not available to fulfill the request. + * + */ +int os_dev_is_flag_nonblock(void); + +/*! + * Determine which major device is being accessed. Usable in #OS_DEV_OPEN() + * and #OS_DEV_CLOSE(). + */ +int os_dev_get_major(void); + +/*! + * Determine which minor device is being accessed. Usable in #OS_DEV_OPEN() + * and #OS_DEV_CLOSE(). + */ +int os_dev_get_minor(void); + +/*! + * Determine which operation the user wants performed. Usable in + * #OS_DEV_IOCTL(). + * + * @return Value of the operation. + * + * @todo Define some generic way to define the individual operations. + */ +unsigned os_dev_get_ioctl_op(void); + +/*! + * Retrieve the associated argument for the desired operation. Usable in + * #OS_DEV_IOCTL(). + * + * @return A value which can be cast to a struct pointer or used as + * int/long. + */ +os_dev_ioctl_arg_t os_dev_get_ioctl_arg(void); + +/*! + * Determine the requested byte count. This should be the size of buffer at + * #os_dev_get_user_buffer(). Usable in OS_DEV_READ() and OS_DEV_WRITE() + * routines. + * + * @return A count of bytes + */ +unsigned os_dev_get_count(void); + +/*! + * Get the pointer to the user's data buffer. Usable in OS_DEV_READ(), + * OS_DEV_WRITE(), and OS_DEV_MMAP() routines. + * + * @return Pointer to user buffer (in user space). See #os_copy_to_user() + * and #os_copy_from_user(). + */ +void *os_dev_get_user_buffer(void); + +/*! + * Get the POSIX flags field for the associated open file. Usable in + * OS_DEV_READ(), OS_DEV_WRITE(), and OS_DEV_IOCTL() routines. + * + * @return The flags associated with the file. + */ +unsigned os_dev_get_file_flags(void); + +/*! + * Set the driver's private structure associated with this file/open. + * + * Generally used during #OS_DEV_OPEN(). May also be used during + * #OS_DEV_READ(), #OS_DEV_WRITE(), #OS_DEV_IOCTL(), #OS_DEV_MMAP(), and + * #OS_DEV_CLOSE(). See also #os_dev_get_user_private(). + * + * @param struct_p The driver data structure to associate with this user. + */ +void os_dev_set_user_private(void *struct_p); + +/*! + * Get the driver's private structure associated with this file. + * + * May be used during #OS_DEV_OPEN(), #OS_DEV_READ(), #OS_DEV_WRITE(), + * #OS_DEV_IOCTL(), #OS_DEV_MMAP(), and #OS_DEV_CLOSE(). See + * also #os_dev_set_user_private(). + * + * @return The driver data structure to associate with this user. + */ +void *os_dev_get_user_private(void); + +/*! + * Get the IRQ associated with this call to the #OS_DEV_ISR() function. + * + * @return The IRQ (integer) interrupt number. + */ +int os_dev_get_irq(void); + + /*! @} *//* drsigargs */ + +/***************************************************************************** + * Functions for Generating References to Driver Routines + *****************************************************************************/ + +/*! + * @defgroup drref Functions for Generating References to Driver Routines + * + * These functions will most likely be implemented as macros. They are a + * necessary part of the portable API to guarantee portability. The @c symbol + * type in here is the same symbol passed to the associated + * signature-generating macro. + * + * These macros must be used whenever referring to a + * @ref drsigs "driver signature function", for instance when storing or + * passing a pointer to the function. + */ + +/*! @addtogroup drref */ +/*! @{ */ + +/*! + * Generate a reference to an #OS_DEV_INIT() function + * + * @param function_name The name of the init function being referenced. + * + * @return A reference to the function + */ +os_init_function_t OS_DEV_INIT_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_SHUTDOWN() function + * + * @param function_name The name of the shutdown function being referenced. + * + * @return A reference to the function + */ +os_shutdown_function_t OS_DEV_SHUTDOWN_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_OPEN() function + * + * @param function_name The name of the open function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_OPEN_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_CLOSE() function + * + * @param function_name The name of the close function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_CLOSE_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_READ() function + * + * @param function_name The name of the read function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_READ_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_WRITE() function + * + * @param function_name The name of the write function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_WRITE_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_IOCTL() function + * + * @param function_name The name of the ioctl function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_IOCTL_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_MMAP() function + * + * @param function_name The name of the mmap function being referenced. + * + * @return A reference to the function + */ +os_user_function_t OS_DEV_MMAP_REF(symbol function_name); + +/*! + * Generate a reference to an #OS_DEV_ISR() function + * + * @param function_name The name of the isr being referenced. + * + * @return a reference to the function + */ +os_interrupt_handler_t OS_DEV_ISR_REF(symbol function_name); + + /*! @} *//* drref */ + +/*! + * Flush and invalidate all cache lines. + */ +void os_flush_cache_all(void); + +/*! + * Flush a range of addresses from the cache + * + * @param start Starting virtual address + * @param len Number of bytes to flush + */ +void os_cache_flush_range(void *start, uint32_t len); + +/*! + * Invalidate a range of addresses in the cache + * + * @param start Starting virtual address + * @param len Number of bytes to flush + */ +void os_cache_inv_range(void *start, uint32_t len); + +/*! + * Clean a range of addresses from the cache + * + * @param start Starting virtual address + * @param len Number of bytes to flush + */ +void os_cache_clean_range(void *start, uint32_t len); + +/*! + * @example widget.h + */ + +/*! + * @example widget.c + */ + +/*! + * @example rng_driver.h + */ + +/*! + * @example rng_driver.c + */ + +/*! + * @example shw_driver.h + */ + +/*! + * @example shw_driver.c + */ + +#endif /* DOXYGEN_PORTABLE_OS_DOC */ + +#endif /* PORTABLE_OS_H */ diff --git a/drivers/mxc/security/sahara2/include/sah_driver_common.h b/drivers/mxc/security/sahara2/include/sah_driver_common.h new file mode 100644 index 000000000000..bcdc053bf0c3 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sah_driver_common.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_driver_common.h +* +* @brief Provides types and defined values for use in the Driver Interface. +* +*/ + +#ifndef SAH_DRIVER_COMMON_H +#define SAH_DRIVER_COMMON_H + +#include "fsl_platform.h" +#include +#include + +/** This specifies the permissions for the device file. It is equivalent to + * chmod 666. + */ +#define SAHARA_DEVICE_MODE S_IFCHR | S_IRUGO | S_IWUGO + +/** +* The status of entries in the Queue. +* +******************************************************************************/ +typedef enum +{ + /** This state indicates that the entry is in the queue and awaits + * execution on SAHARA. */ + SAH_STATE_PENDING, + /** This state indicates that the entry has been written to the SAHARA + * DAR. */ + SAH_STATE_ON_SAHARA, + /** This state indicates that the entry is off of SAHARA, and is awaiting + post-processing. */ + SAH_STATE_OFF_SAHARA, + /** This state indicates that the entry is successfully executed on SAHARA, + and it is finished with post-processing. */ + SAH_STATE_COMPLETE, + /** This state indicates that the entry caused an error or fault on SAHARA, + * and it is finished with post-processing. */ + SAH_STATE_FAILED, + /** This state indicates that the entry was reset via the Reset IO + * Control, and it is finished with post-processing. */ + SAH_STATE_RESET, + /** This state indicates that the entry was signalled from user-space and + * either in the DAR, IDAR or has finished executing pending Bottom Half + * processing. */ + SAH_STATE_IGNORE, + /** This state indicates that the entry was signalled from user-space and + * has been processed by the bottom half. */ + SAH_STATE_IGNORED +} sah_Queue_Status; + +/* any of these conditions being true indicates the descriptor's processing + * is complete */ +#define SAH_DESC_PROCESSED(status) \ + (((status) == SAH_STATE_COMPLETE) || \ + ((status) == SAH_STATE_FAILED ) || \ + ((status) == SAH_STATE_RESET )) + +extern os_lock_t desc_queue_lock; + +extern uint32_t dar_count; +extern uint32_t interrupt_count; +extern uint32_t done1done2_count; +extern uint32_t done1busy2_count; +extern uint32_t done1_count; + +#ifdef FSL_HAVE_SCC2 +extern void *lookup_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base); +#endif + +int sah_get_results_pointers(fsl_shw_uco_t* user_ctx, uint32_t arg); +fsl_shw_return_t sah_get_results_from_pool(volatile fsl_shw_uco_t* user_ctx, + sah_results *arg); +fsl_shw_return_t sah_handle_registration(fsl_shw_uco_t *user_cts); +fsl_shw_return_t sah_handle_deregistration(fsl_shw_uco_t *user_cts); + +int sah_Queue_Manager_Count_Entries(int ignore_state, sah_Queue_Status state); +unsigned long sah_Handle_Poll(sah_Head_Desc *entry); + +#ifdef DIAG_DRV_IF +/****************************************************************************** +* Descriptor and Link dumping functions. +******************************************************************************/ +void sah_Dump_Chain(const sah_Desc *chain, dma_addr_t addr); +#endif /* DIAG_DRV_IF */ + +#endif /* SAH_DRIVER_COMMON_H */ diff --git a/drivers/mxc/security/sahara2/include/sah_hardware_interface.h b/drivers/mxc/security/sahara2/include/sah_hardware_interface.h new file mode 100644 index 000000000000..f507a835a504 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sah_hardware_interface.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_hardware_interface.h +* +* @brief Provides an interface to the SAHARA hardware registers. +* +*/ + +#ifndef SAH_HARDWARE_INTERFACE_H +#define SAH_HARDWARE_INTERFACE_H + +#include +#include + +/* These values can be used with sah_HW_Write_Control(). */ +#ifdef SAHARA1 +/** Define platform as Little-Endian */ +#define CTRL_LITTLE_END 0x00000002 +/** Bit to cause endian change in transfers */ +#define CTRL_INT_EN 0x00000004 +/** Set High Assurance mode */ +#define CTRL_HA 0x00000008 +#else +/** Bit to cause byte swapping in (data?) transfers */ +#define CTRL_BYTE_SWAP 0x00000001 +/** Bit to cause halfword swapping in (data?) transfers */ +#define CTRL_HALFWORD_SWAP 0x00000002 +/** Bit to cause endian change in (data?) transfers */ +#define CTRL_INT_EN 0x00000010 +/** Set High Assurance mode */ +#define CTRL_HA 0x00000020 +/** Disable High Assurance */ +#define CTRL_HA_DISABLE 0x00000040 +/** Reseed the RNG CHA */ +#define CTRL_RNG_RESEED 0x00000080 +#endif + + +/* These values can be used with sah_HW_Write_Command(). */ +/** Reset the Sahara */ +#define CMD_RESET 0x00000001 +/** Set Sahara into Batch mode. */ +#define CMD_BATCH 0x00010000 +/** Clear the Sahara interrupt */ +#define CMD_CLR_INT_BIT 0x00000100 +/** Clear the Sahara error */ +#define CMD_CLR_ERROR_BIT 0x00000200 + + +/** error status register contains error */ +#define STATUS_ERROR 0x00000010 + +/** Op status register contains op status */ +#define OP_STATUS 0x00000020 + + +/* High Level functions */ +int sah_HW_Reset(void); +fsl_shw_return_t sah_HW_Set_HA(void); +sah_Execute_Status sah_Wait_On_Sahara(void); + +/* Low Level functions */ +uint32_t sah_HW_Read_Version(void); +uint32_t sah_HW_Read_Control(void); +uint32_t sah_HW_Read_Status(void); +uint32_t sah_HW_Read_Error_Status(void); +uint32_t sah_HW_Read_Op_Status(void); +uint32_t sah_HW_Read_DAR(void); +uint32_t sah_HW_Read_CDAR(void); +uint32_t sah_HW_Read_IDAR(void); +uint32_t sah_HW_Read_Fault_Address(void); +uint32_t sah_HW_Read_MM_Status(void); +uint32_t sah_HW_Read_Config(void); +void sah_HW_Write_Command(uint32_t command); +void sah_HW_Write_Control(uint32_t control); +void sah_HW_Write_DAR(uint32_t pointer); +void sah_HW_Write_Config(uint32_t configuration); + +#if defined DIAG_DRV_IF || defined(DO_DBG) + +void sah_Dump_Words(const char *prefix, const unsigned *data, dma_addr_t addr, + unsigned length); +#endif + +#endif /* SAH_HARDWARE_INTERFACE_H */ + +/* End of sah_hardware_interface.c */ diff --git a/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h b/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h new file mode 100644 index 000000000000..fc4d77475f85 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sah_interrupt_handler.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_interrupt_handler.h +* +* @brief Provides a hardware interrupt handling mechanism for device driver. +* +*/ +/****************************************************************************** +* +* CAUTION: +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 30/07/03 MW Initial Creation +******************************************************************* +*/ + +#ifndef SAH_INTERRUPT_HANDLER_H +#define SAH_INTERRUPT_HANDLER_H + +#include + +/****************************************************************************** +* External function declarations +******************************************************************************/ +int sah_Intr_Init (wait_queue_head_t *wait_queue); +void sah_Intr_Release (void); + +#endif /* SAH_INTERRUPT_HANDLER_H */ diff --git a/drivers/mxc/security/sahara2/include/sah_kernel.h b/drivers/mxc/security/sahara2/include/sah_kernel.h new file mode 100644 index 000000000000..e39a61e64430 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sah_kernel.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* +* @file sah_kernel.h +* +* @brief Provides definitions for items that user-space and kernel-space share. +*/ +/****************************************************************************** +* +* This file needs to be PORTED to a non-Linux platform +*/ + +#ifndef SAH_KERNEL_H +#define SAH_KERNEL_H + +#if defined(__KERNEL__) + +#if defined(CONFIG_ARCH_MXC91321) || defined(CONFIG_ARCH_MXC91231) \ + || defined(CONFIG_ARCH_MX27) || defined(CONFIG_ARCH_MXC92323) +#include +#define SAHA_BASE_ADDR SAHARA_BASE_ADDR +#define SAHARA_IRQ MXC_INT_SAHARA +#elif defined(CONFIG_ARCH_MX5) +#include +#define SAHA_BASE_ADDR SAHARA_BASE_ADDR +#define SAHARA_IRQ MXC_INT_SAHARA_H0 +#else +#include +#endif + +#endif /* KERNEL */ + +/* IO Controls */ +/* The magic number 'k' is reserved for the SPARC architecture. (See /Documentation/ioctl-number.txt. + * + * Note: Numbers 8-13 were used in a previous version of the API and should + * be avoided. + */ +#define SAH_IOC_MAGIC 'k' +#define SAHARA_HWRESET _IO(SAH_IOC_MAGIC, 0) +#define SAHARA_SET_HA _IO(SAH_IOC_MAGIC, 1) +#define SAHARA_CHK_TEST_MODE _IOR(SAH_IOC_MAGIC,2, int) +#define SAHARA_DAR _IO(SAH_IOC_MAGIC, 3) +#define SAHARA_GET_RESULTS _IO(SAH_IOC_MAGIC, 4) +#define SAHARA_REGISTER _IO(SAH_IOC_MAGIC, 5) +#define SAHARA_DEREGISTER _IO(SAH_IOC_MAGIC, 6) +/* 7 */ +/* 8 */ +/* 9 */ +/* 10 */ +/* 11 */ +/* 12 */ +/* 13 */ + +#define SAHARA_SCC_DROP_PERMS _IOWR(SAH_IOC_MAGIC, 14, scc_partition_info_t) +#define SAHARA_SCC_SFREE _IOWR(SAH_IOC_MAGIC, 15, scc_partition_info_t) + +#define SAHARA_SK_ALLOC _IOWR(SAH_IOC_MAGIC, 16, scc_slot_t) +#define SAHARA_SK_DEALLOC _IOWR(SAH_IOC_MAGIC, 17, scc_slot_t) +#define SAHARA_SK_LOAD _IOWR(SAH_IOC_MAGIC, 18, scc_slot_t) +#define SAHARA_SK_UNLOAD _IOWR(SAH_IOC_MAGIC, 19, scc_slot_t) +#define SAHARA_SK_SLOT_ENC _IOWR(SAH_IOC_MAGIC, 20, scc_slot_t) +#define SAHARA_SK_SLOT_DEC _IOWR(SAH_IOC_MAGIC, 21, scc_slot_t) + +#define SAHARA_SCC_ENCRYPT _IOWR(SAH_IOC_MAGIC, 22, scc_region_t) +#define SAHARA_SCC_DECRYPT _IOWR(SAH_IOC_MAGIC, 23, scc_region_t) +#define SAHARA_GET_CAPS _IOWR(SAH_IOC_MAGIC, 24, fsl_shw_pco_t) + +#define SAHARA_SCC_SSTATUS _IOWR(SAH_IOC_MAGIC, 25, scc_partition_info_t) + +#define SAHARA_SK_READ _IOWR(SAH_IOC_MAGIC, 29, scc_slot_t) + +/*! This is the name that will appear in /proc/interrupts */ +#define SAHARA_NAME "SAHARA" + +/*! + * SAHARA IRQ number. See page 9-239 of TLICS - Motorola Semiconductors H.K. + * TAHITI-Lite IC Specification, Rev 1.1, Feb 2003. + * + * TAHITI has two blocks of 32 interrupts. The SAHARA IRQ is number 27 + * in the second block. This means that the SAHARA IRQ is 27 + 32 = 59. + */ +#ifndef SAHARA_IRQ +#define SAHARA_IRQ (27+32) +#endif + +/*! + * Device file definition. The #ifndef is here to support the unit test code + * by allowing it to specify a different test device. + */ +#ifndef SAHARA_DEVICE_SHORT +#define SAHARA_DEVICE_SHORT "sahara" +#endif + +#ifndef SAHARA_DEVICE +#define SAHARA_DEVICE "/dev/"SAHARA_DEVICE_SHORT +#endif + +#endif /* SAH_KERNEL_H */ + +/* End of sah_kernel.h */ diff --git a/drivers/mxc/security/sahara2/include/sah_memory_mapper.h b/drivers/mxc/security/sahara2/include/sah_memory_mapper.h new file mode 100644 index 000000000000..ddf4a59af540 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sah_memory_mapper.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_memory_mapper.h +* +* @brief Re-creates SAHARA data structures in Kernel memory such that they are +* suitable for DMA. +* +*/ + +#ifndef SAH_MEMORY_MAPPER_H +#define SAH_MEMORY_MAPPER_H + +#include +#include + + +/****************************************************************************** +* External function declarations +******************************************************************************/ +sah_Head_Desc *sah_Copy_Descriptors(fsl_shw_uco_t * user_ctx, + sah_Head_Desc * desc); + +sah_Link *sah_Copy_Links(fsl_shw_uco_t * user_ctx, sah_Link * ptr); + +sah_Head_Desc *sah_Physicalise_Descriptors(sah_Head_Desc * desc); + +sah_Link *sah_Physicalise_Links (sah_Link *ptr); + +sah_Head_Desc *sah_DePhysicalise_Descriptors (sah_Head_Desc *desc); + +sah_Link *sah_DePhysicalise_Links (sah_Link *ptr); + +sah_Link *sah_Make_Links(fsl_shw_uco_t * user_ctx, + sah_Link * ptr, sah_Link ** tail); + + +void sah_Destroy_Descriptors (sah_Head_Desc *desc); + +void sah_Destroy_Links (sah_Link *link); + +void sah_Free_Chained_Descriptors (sah_Head_Desc *desc); + +void sah_Free_Chained_Links (sah_Link *link); + +int sah_Init_Mem_Map (void); + +void sah_Stop_Mem_Map (void); + +int sah_Block_Add_Page (int big); + +sah_Desc *sah_Alloc_Descriptor (void); +sah_Head_Desc *sah_Alloc_Head_Descriptor (void); +void sah_Free_Descriptor (sah_Desc *desc); +void sah_Free_Head_Descriptor (sah_Head_Desc *desc); +sah_Link *sah_Alloc_Link (void); +void sah_Free_Link (sah_Link *link); + +void *wire_user_memory(void *address, uint32_t length, void **page_ctx); +void unwire_user_memory(void **page_ctx); + +os_error_code map_user_memory(struct vm_area_struct *vma, + uint32_t physical_addr, uint32_t size); +os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size); + +#endif /* SAH_MEMORY_MAPPER_H */ + +/* End of sah_memory_mapper.h */ diff --git a/drivers/mxc/security/sahara2/include/sah_queue_manager.h b/drivers/mxc/security/sahara2/include/sah_queue_manager.h new file mode 100644 index 000000000000..895006f7ab91 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sah_queue_manager.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_queue_manager.h +* +* @brief This file definitions for the Queue Manager. + +* The Queue Manager manages additions and removal from the queue and updates +* the status of queue entries. It also calls sah_HW_* functions to interact +* with the hardware. +* +*/ + +#ifndef SAH_QUEUE_MANAGER_H +#define SAH_QUEUE_MANAGER_H + +#include +#include + + +/************************* +* Queue Manager Functions +*************************/ +fsl_shw_return_t sah_Queue_Manager_Init(void); +void sah_Queue_Manager_Close(void); +void sah_Queue_Manager_Reset_Entries(void); +void sah_Queue_Manager_Append_Entry(sah_Head_Desc *entry); +void sah_Queue_Manager_Remove_Entry(sah_Head_Desc *entry); + + +/************************* +* Queue Functions +*************************/ +sah_Queue *sah_Queue_Construct(void); +void sah_Queue_Destroy(sah_Queue *this); +void sah_Queue_Append_Entry(sah_Queue *this, sah_Head_Desc *entry); +void sah_Queue_Remove_Entry(sah_Queue *this); +void sah_Queue_Remove_Any_Entry(sah_Queue *this, sah_Head_Desc *entry); +void sah_postprocess_queue(unsigned long reset_flag); + + +/************************* +* Misc Releated Functions +*************************/ + +int sah_blocking_mode(struct sah_Head_Desc *entry); +fsl_shw_return_t sah_convert_error_status(uint32_t error_status); + + +#endif /* SAH_QUEUE_MANAGER_H */ + +/* End of sah_queue_manager.h */ diff --git a/drivers/mxc/security/sahara2/include/sah_status_manager.h b/drivers/mxc/security/sahara2/include/sah_status_manager.h new file mode 100644 index 000000000000..63660b53c94f --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sah_status_manager.h @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sah_status_manager.h +* +* @brief SAHARA Status Manager Types and Function Prototypes +* +* @author Stuart Holloway (SH) +* +*/ + +#ifndef STATUS_MANAGER_H +#define STATUS_MANAGER_H +#include "sah_driver_common.h" +#include "sahara.h" + + +/****************************************************************************** +* User defined data types +******************************************************************************/ +/** +****************************************************************************** +* sah_Execute_Status +* Types read from SAHARA Status Register, with additional state for Op Status +******************************************************************************/ +typedef enum sah_Execute_Status +{ + /** Sahara is Idle. */ + SAH_EXEC_IDLE = 0, + /** SAHARA is busy performing a resest or processing a decriptor chain. */ + SAH_EXEC_BUSY = 1, + /** An error occurred while SAHARA executed the first descriptor. */ + SAH_EXEC_ERROR1 = 2, + /** SAHARA has failed internally. */ + SAH_EXEC_FAULT = 3, + /** SAHARA has finished processing a descriptor chain and is idle. */ + SAH_EXEC_DONE1 = 4, + /** SAHARA has finished processing a descriptor chain, and is processing a + * second chain. */ + SAH_EXEC_DONE1_BUSY2 = 5, + /** SAHARA has finished processing a descriptor chain, but has generated an + * error while processing a second descriptor chain. */ + SAH_EXEC_DONE1_ERROR2 = 6, + /** SAHARA has finished two descriptors. */ + SAH_EXEC_DONE1_DONE2 = 7, + /** SAHARA has stopped, and first descriptor has Op Status, not Err */ + SAH_EXEC_OPSTAT1 = 0x20, +} sah_Execute_Status; + +/** + * When this bit is on in a #sah_Execute_Status, it means that DONE1 is true. + */ +#define SAH_EXEC_DONE1_BIT 4 + +/** + * Bits which make up the Sahara State + */ +#define SAH_EXEC_STATE_MASK 0x00000007 + +/** +******************************************************************************* +* sah_Execute_Error +* Types read from SAHARA Error Status Register +******************************************************************************/ +typedef enum sah_Execute_Error +{ + /** No Error */ + SAH_ERR_NONE = 0, + /** Header is not valid. */ + SAH_ERR_HEADER = 1, + /** Descriptor length is not correct. */ + SAH_ERR_DESC_LENGTH = 2, + /** Length or pointer field is zero while the other is non-zero. */ + SAH_ERR_DESC_POINTER = 3, + /** Length of the link is not a multiple of 4 and is not the last link */ + SAH_ERR_LINK_LENGTH = 4, + /** The data pointer in a link is zero */ + SAH_ERR_LINK_POINTER = 5, + /** Input Buffer reported an overflow */ + SAH_ERR_INPUT_BUFFER = 6, + /** Output Buffer reported an underflow */ + SAH_ERR_OUTPUT_BUFFER = 7, + /** Incorrect data in output buffer after CHA's has signalled 'done'. */ + SAH_ERR_OUTPUT_BUFFER_STARVATION = 8, + /** Internal Hardware Failure. */ + SAH_ERR_INTERNAL_STATE = 9, + /** Current Descriptor was not legal, but cause is unknown. */ + SAH_ERR_GENERAL_DESCRIPTOR = 10, + /** Reserved pointer fields have been set to 1. */ + SAH_ERR_RESERVED_FIELDS = 11, + /** Descriptor address error */ + SAH_ERR_DESCRIPTOR_ADDRESS = 12, + /** Link address error */ + SAH_ERR_LINK_ADDRESS = 13, + /** Processing error in CHA module */ + SAH_ERR_CHA = 14, + /** Processing error during DMA */ + SAH_ERR_DMA = 15 +} sah_Execute_Error; + + +/** +******************************************************************************* +* sah_CHA_Error_Source +* Types read from SAHARA Error Status Register for CHA Error Source +* +******************************************************************************/ +typedef enum sah_CHA_Error_Source +{ + /** No Error indicated in Source CHA Error. */ + SAH_CHA_NO_ERROR = 0, + /** Error in SKHA module. */ + SAH_CHA_SKHA_ERROR = 1, + /** Error in MDHA module. */ + SAH_CHA_MDHA_ERROR = 2, + /** Error in RNG module. */ + SAH_CHA_RNG_ERROR = 3, + /** Error in PKHA module. */ + SAH_CHA_PKHA_ERROR = 4, +} sah_CHA_Error_Source; + +/** +****************************************************************************** +* sah_CHA_Error_Status +* Types read from SAHARA Error Status Register for CHA Error Status +* +******************************************************************************/ +typedef enum sah_CHA_Error_Status +{ + /** No CHA error detected */ + SAH_CHA_NO_ERR = 0x000, + /** Non-empty input buffer when complete. */ + SAH_CHA_IP_BUF = 0x001, + /** Illegal Address Error. */ + SAH_CHA_ADD_ERR = 0x002, + /** Illegal Mode Error. */ + SAH_CHA_MODE_ERR = 0x004, + /** Illegal Data Size Error. */ + SAH_CHA_DATA_SIZE_ERR = 0x008, + /** Illegal Key Size Error. */ + SAH_CHA_KEY_SIZE_ERR = 0x010, + /** Mode/Context/Key written during processing. */ + SAH_CHA_PROC_ERR = 0x020, + /** Context Read During Processing. */ + SAH_CHA_CTX_READ_ERR = 0x040, + /** Internal Hardware Error. */ + SAH_CHA_INTERNAL_HW_ERR = 0x080, + /** Input Buffer not enabled or underflow. */ + SAH_CHA_IP_BUFF_ERR = 0x100, + /** Output Buffer not enabled or overflow. */ + SAH_CHA_OP_BUFF_ERR = 0x200, + /** DES key parity error (SKHA) */ + SAH_CHA_DES_KEY_ERR = 0x400, + /** Reserved error code. */ + SAH_CHA_RES = 0x800 +} sah_CHA_Error_Status; + +/** +***************************************************************************** +* sah_DMA_Error_Status +* Types read from SAHARA Error Status Register for DMA Error Status +******************************************************************************/ +typedef enum sah_DMA_Error_Status +{ + /** No DMA Error Code. */ + SAH_DMA_NO_ERR = 0, + /** AHB terminated a bus cycle with an error. */ + SAH_DMA_AHB_ERR = 2, + /** Internal IP bus cycle was terminated with an error termination. */ + SAH_DMA_IP_ERR = 4, + /** Parity error detected on DMA command. */ + SAH_DMA_PARITY_ERR = 6, + /** DMA was requested to cross a 256 byte internal address boundary. */ + SAH_DMA_BOUNDRY_ERR = 8, + /** DMA controller is busy */ + SAH_DMA_BUSY_ERR = 10, + /** Memory Bounds Error */ + SAH_DMA_RESERVED_ERR = 12, + /** Internal DMA hardware error detected */ + SAH_DMA_INT_ERR = 14 +} sah_DMA_Error_Status; + +/** +***************************************************************************** +* sah_DMA_Error_Size +* Types read from SAHARA Error Status Register for DMA Error Size +* +******************************************************************************/ +typedef enum sah_DMA_Error_Size +{ + /** Error during Byte transfer. */ + SAH_DMA_SIZE_BYTE = 0, + /** Error during Half-word transfer. */ + SAH_DMA_SIZE_HALF_WORD = 1, + /** Error during Word transfer. */ + SAH_DMA_SIZE_WORD = 2, + /** Reserved DMA word size. */ + SAH_DMA_SIZE_RES = 3 +} sah_DMA_Error_Size; + + + + +extern bool sah_dpm_flag; + +/************************* +* Status Manager Functions +*************************/ + +unsigned long sah_Handle_Interrupt(sah_Execute_Status hw_status); +sah_Head_Desc *sah_Find_With_State (sah_Queue_Status status); +int sah_dpm_init(void); +void sah_dpm_close(void); +void sah_Queue_Manager_Prime (sah_Head_Desc *entry); + + +#endif /* STATUS_MANAGER_H */ diff --git a/drivers/mxc/security/sahara2/include/sahara.h b/drivers/mxc/security/sahara2/include/sahara.h new file mode 100644 index 000000000000..c66c125bc129 --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sahara.h @@ -0,0 +1,2265 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sahara.h + * + * File which implements the FSL_SHW API when used on Sahara + */ +/*! + * @if USE_MAINPAGE + * @mainpage Sahara2 implemtation of FSL Security Hardware API + * @endif + * + */ + +#define _DIAG_DRV_IF +#define _DIAG_SECURITY_FUNC +#define _DIAG_ADAPTOR + +#ifndef SAHARA2_API_H +#define SAHARA2_API_H + +#ifdef DIAG_SECURITY_FUNC +#include +#endif /* DIAG_SECURITY_FUNC */ + +/* This is a Linux flag... ? */ +#ifndef __KERNEL__ +#include +#include +#include +#else +#include "portable_os.h" +#endif + +/* This definition may need a new name, and needs to go somewhere which + * can determine platform, kernel vs. user, os, etc. + */ +#define copy_bytes(out, in, len) memcpy(out, in, len) + +/* Does this belong here? */ +#ifndef SAHARA_DEVICE +#define SAHARA_DEVICE "/dev/sahara" +#endif + +/*! +******************************************************************************* +* @defgroup lnkflags Link Flags +* +* @brief Flags to show information about link data and link segments +* +******************************************************************************/ +/*! @addtogroup lnkflags + * @{ + */ + +/*! +******************************************************************************* +* This flag indicates that the data in a link is owned by the security +* function component and this memory will be freed by the security function +* component. To be used as part of the flag field of the sah_Link structure. +******************************************************************************/ +#define SAH_OWNS_LINK_DATA 0x01 + +/*! +******************************************************************************* +* The data in a link is not owned by the security function component and +* therefore it will not attempt to free this memory. To be used as part of the +* flag field of the sah_Link structure. +******************************************************************************/ +#define SAH_USES_LINK_DATA 0x02 + +/*! +******************************************************************************* +* The data in this link will change when the descriptor gets executed. +******************************************************************************/ +#define SAH_OUTPUT_LINK 0x04 + +/*! +******************************************************************************* +* The ptr and length in this link are really 'established key' info. They +* are to be converted to ptr/length before putting on request queue. +******************************************************************************/ +#define SAH_KEY_IS_HIDDEN 0x08 + +/*! +******************************************************************************* +* The link structure has been appended to the previous one by the driver. It +* needs to be removed before leaving the driver (and returning to API). +******************************************************************************/ +#define SAH_REWORKED_LINK 0x10 + +/*! +******************************************************************************* +* The length and data fields of this link contain the slot and user id +* used to access the SCC stored key +******************************************************************************/ +#define SAH_STORED_KEY_INFO 0x20 + +/*! +******************************************************************************* +* The Data field points to a physical address, and does not need to be +* processed by the driver. Honored only in Kernel API. +******************************************************************************/ +#define SAH_PREPHYS_DATA 0x40 + +/*! +******************************************************************************* +* The link was inserted during the Physicalise procedure. It is tagged so +* it can be removed during DePhysicalise, thereby returning to the caller an +* intact chain. +******************************************************************************/ +#define SAH_LINK_INSERTED_LINK 0x80 + +/*! +******************************************************************************* +* The Data field points to the location of the key, which is in a secure +* partition held by the user. The memory address needs to be converted to +* kernel space manually, by looking through the partitions that the user holds. +******************************************************************************/ +#define SAH_IN_USER_KEYSTORE 0x100 + +/*! +******************************************************************************* +* sah_Link_Flags +* +* Type to be used for flags associated with a Link in security function. +* These flags are used internally by the security function component only. +* +* Values defined at @ref lnkflags +* +* @brief typedef for flags field of sah_Link +******************************************************************************/ +typedef uint32_t sah_Link_Flags; + +/* +******************************************************************************* +* Security Parameters Related Structures +* +* All of structures associated with API parameters +* +******************************************************************************/ + +/* +******************************************************************************* +* Common Types +* +* All of structures used across several classes of crytography +******************************************************************************/ + +/*! +******************************************************************************* +* @brief Indefinite precision integer used for security operations on SAHARA +* accelerator. The data will always be in little Endian format. +******************************************************************************/ +typedef uint8_t *sah_Int; + +/*! +******************************************************************************* +* @brief Byte array used for block cipher and hash digest/MAC operations on +* SAHARA accelerator. The Endian format will be as specified by the function +* using the sah_Oct_Str. +******************************************************************************/ +typedef uint8_t *sah_Oct_Str; + +/*! + * A queue of descriptor heads -- used to hold requests waiting for user to + * pick up the results. */ +typedef struct sah_Queue { + int count; /*!< # entries in queue */ + struct sah_Head_Desc *head; /*!< first entry in queue */ + struct sah_Head_Desc *tail; /*!< last entry in queue */ +} sah_Queue; + +/****************************************************************************** + * Enumerations + *****************************************************************************/ +/*! + * Flags for the state of the User Context Object (#fsl_shw_uco_t). + */ +typedef enum fsl_shw_user_ctx_flags_t { + /*! + * API will block the caller until operation completes. The result will be + * available in the return code. If this is not set, user will have to get + * results using #fsl_shw_get_results(). + */ + FSL_UCO_BLOCKING_MODE = 0x01, + /*! + * User wants callback (at the function specified with + * #fsl_shw_uco_set_callback()) when the operation completes. This flag is + * valid only if #FSL_UCO_BLOCKING_MODE is not set. + */ + FSL_UCO_CALLBACK_MODE = 0x02, + /*! Do not free descriptor chain after driver (adaptor) finishes */ + FSL_UCO_SAVE_DESC_CHAIN = 0x04, + /*! + * User has made at least one request with callbacks requested, so API is + * ready to handle others. + */ + FSL_UCO_CALLBACK_SETUP_COMPLETE = 0x08, + /*! + * (virtual) pointer to descriptor chain is completely linked with physical + * (DMA) addresses, ready for the hardware. This flag should not be used + * by FSL SHW API programs. + */ + FSL_UCO_CHAIN_PREPHYSICALIZED = 0x10, + /*! + * The user has changed the context but the changes have not been copied to + * the kernel driver. + */ + FSL_UCO_CONTEXT_CHANGED = 0x20, + /*! Internal Use. This context belongs to a user-mode API user. */ + FSL_UCO_USERMODE_USER = 0x40, +} fsl_shw_user_ctx_flags_t; + +/*! + * Return code for FSL_SHW library. + * + * These codes may be returned from a function call. In non-blocking mode, + * they will appear as the status in a Result Object. + */ +typedef enum fsl_shw_return_t { + /*! + * No error. As a function return code in Non-blocking mode, this may + * simply mean that the operation was accepted for eventual execution. + */ + FSL_RETURN_OK_S = 0, + /*! Failure for non-specific reason. */ + FSL_RETURN_ERROR_S, + /*! + * Operation failed because some resource was not able to be allocated. + */ + FSL_RETURN_NO_RESOURCE_S, + /*! Crypto algorithm unrecognized or improper. */ + FSL_RETURN_BAD_ALGORITHM_S, + /*! Crypto mode unrecognized or improper. */ + FSL_RETURN_BAD_MODE_S, + /*! Flag setting unrecognized or inconsistent. */ + FSL_RETURN_BAD_FLAG_S, + /*! Improper or unsupported key length for algorithm. */ + FSL_RETURN_BAD_KEY_LENGTH_S, + /*! Improper parity in a (DES, TDES) key. */ + FSL_RETURN_BAD_KEY_PARITY_S, + /*! + * Improper or unsupported data length for algorithm or internal buffer. + */ + FSL_RETURN_BAD_DATA_LENGTH_S, + /*! Authentication / Integrity Check code check failed. */ + FSL_RETURN_AUTH_FAILED_S, + /*! A memory error occurred. */ + FSL_RETURN_MEMORY_ERROR_S, + /*! An error internal to the hardware occurred. */ + FSL_RETURN_INTERNAL_ERROR_S, + /*! ECC detected Point at Infinity */ + FSL_RETURN_POINT_AT_INFINITY_S, + /*! ECC detected No Point at Infinity */ + FSL_RETURN_POINT_NOT_AT_INFINITY_S, + /*! GCD is One */ + FSL_RETURN_GCD_IS_ONE_S, + /*! GCD is not One */ + FSL_RETURN_GCD_IS_NOT_ONE_S, + /*! Candidate is Prime */ + FSL_RETURN_PRIME_S, + /*! Candidate is not Prime */ + FSL_RETURN_NOT_PRIME_S, + /*! N register loaded improperly with even value */ + FSL_RETURN_EVEN_MODULUS_ERROR_S, + /*! Divisor is zero. */ + FSL_RETURN_DIVIDE_BY_ZERO_ERROR_S, + /*! Bad Exponent or Scalar value for Point Multiply */ + FSL_RETURN_BAD_EXPONENT_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_OSCILLATOR_ERROR_S, + /*! RNG hardware problem. */ + FSL_RETURN_STATISTICS_ERROR_S, +} fsl_shw_return_t; + +/*! + * Algorithm Identifier. + * + * Selection of algorithm will determine how large the block size of the + * algorithm is. Context size is the same length unless otherwise specified. + * Selection of algorithm also affects the allowable key length. + */ +typedef enum fsl_shw_key_alg_t { + /*! + * Key will be used to perform an HMAC. Key size is 1 to 64 octets. Block + * size is 64 octets. + */ + FSL_KEY_ALG_HMAC, + /*! + * Advanced Encryption Standard (Rijndael). Block size is 16 octets. Key + * size is 16 octets. (The single choice of key size is a Sahara platform + * limitation.) + */ + FSL_KEY_ALG_AES, + /*! + * Data Encryption Standard. Block size is 8 octets. Key size is 8 + * octets. + */ + FSL_KEY_ALG_DES, + /*! + * 2- or 3-key Triple DES. Block size is 8 octets. Key size is 16 octets + * for 2-key Triple DES, and 24 octets for 3-key. + */ + FSL_KEY_ALG_TDES, + /*! + * ARC4. No block size. Context size is 259 octets. Allowed key size is + * 1-16 octets. (The choices for key size are a Sahara platform + * limitation.) + */ + FSL_KEY_ALG_ARC4, + /*! + * Private key of a public-private key-pair. Max is 512 bits... + */ + FSL_KEY_PK_PRIVATE, +} fsl_shw_key_alg_t; + +/*! + * Mode selector for Symmetric Ciphers. + * + * The selection of mode determines how a cryptographic algorithm will be + * used to process the plaintext or ciphertext. + * + * For all modes which are run block-by-block (that is, all but + * #FSL_SYM_MODE_STREAM), any partial operations must be performed on a text + * length which is multiple of the block size. Except for #FSL_SYM_MODE_CTR, + * these block-by-block algorithms must also be passed a total number of octets + * which is a multiple of the block size. + * + * In modes which require that the total number of octets of data be a multiple + * of the block size (#FSL_SYM_MODE_ECB and #FSL_SYM_MODE_CBC), and the user + * has a total number of octets which are not a multiple of the block size, the + * user must perform any necessary padding to get to the correct data length. + */ +typedef enum fsl_shw_sym_mode_t { + /*! + * Stream. There is no associated block size. Any request to process data + * may be of any length. This mode is only for ARC4 operations, and is + * also the only mode used for ARC4. + */ + FSL_SYM_MODE_STREAM, + + /*! + * Electronic Codebook. Each block of data is encrypted/decrypted. The + * length of the data stream must be a multiple of the block size. This + * mode may be used for DES, 3DES, and AES. The block size is determined + * by the algorithm. + */ + FSL_SYM_MODE_ECB, + /*! + * Cipher-Block Chaining. Each block of data is encrypted/decrypted and + * then "chained" with the previous block by an XOR function. Requires + * context to start the XOR (previous block). This mode may be used for + * DES, 3DES, and AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CBC, + /*! + * Counter. The counter is encrypted, then XORed with a block of data. + * The counter is then incremented (using modulus arithmetic) for the next + * block. The final operation may be non-multiple of block size. This mode + * may be used for AES. The block size is determined by the algorithm. + */ + FSL_SYM_MODE_CTR, +} fsl_shw_sym_mode_t; + +/*! + * Algorithm selector for Cryptographic Hash functions. + * + * Selection of algorithm determines how large the context and digest will be. + * Context is the same size as the digest (resulting hash), unless otherwise + * specified. + */ +typedef enum fsl_shw_hash_alg_t { + /*! MD5 algorithm. Digest is 16 octets. */ + FSL_HASH_ALG_MD5, + /*! SHA-1 (aka SHA or SHA-160) algorithm. Digest is 20 octets. */ + FSL_HASH_ALG_SHA1, + /*! + * SHA-224 algorithm. Digest is 28 octets, though context is 32 octets. + */ + FSL_HASH_ALG_SHA224, + /*! SHA-256 algorithm. Digest is 32 octets. */ + FSL_HASH_ALG_SHA256 +} fsl_shw_hash_alg_t; + +/*! + * The type of Authentication-Cipher function which will be performed. + */ +typedef enum fsl_shw_acc_mode_t { + /*! + * CBC-MAC for Counter. Requires context and modulus. Final operation may + * be non-multiple of block size. This mode may be used for AES. + */ + FSL_ACC_MODE_CCM, + /*! + * SSL mode. Not supported. Combines HMAC and encrypt (or decrypt). + * Needs one key object for encryption, another for the HMAC. The usual + * hashing and symmetric encryption algorithms are supported. + */ + FSL_ACC_MODE_SSL, +} fsl_shw_acc_mode_t; + +/* REQ-S2LRD-PINTFC-COA-HCO-001 */ +/*! + * Flags which control a Hash operation. + */ +typedef enum fsl_shw_hash_ctx_flags_t { + /*! + * Context is empty. Hash is started from scratch, with a + * message-processed count of zero. + */ + FSL_HASH_FLAGS_INIT = 0x01, + /*! + * Retrieve context from hardware after hashing. If used with the + * #FSL_HASH_FLAGS_FINALIZE flag, the final digest value will be saved in + * the object. + */ + FSL_HASH_FLAGS_SAVE = 0x02, + /*! Place context into hardware before hashing. */ + FSL_HASH_FLAGS_LOAD = 0x04, + /*! + * PAD message and perform final digest operation. If user message is + * pre-padded, this flag should not be used. + */ + FSL_HASH_FLAGS_FINALIZE = 0x08, +} fsl_shw_hash_ctx_flags_t; + +/*! + * Flags which control an HMAC operation. + * + * These may be combined by ORing them together. See #fsl_shw_hmco_set_flags() + * and #fsl_shw_hmco_clear_flags(). + */ +typedef enum fsl_shw_hmac_ctx_flags_t { + /*! + * Message context is empty. HMAC is started from scratch (with key) or + * from precompute of inner hash, depending on whether + * #FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT is set. + */ + FSL_HMAC_FLAGS_INIT = 1, + /*! + * Retrieve ongoing context from hardware after hashing. If used with the + * #FSL_HMAC_FLAGS_FINALIZE flag, the final digest value (HMAC) will be + * saved in the object. + */ + FSL_HMAC_FLAGS_SAVE = 2, + /*! Place ongoing context into hardware before hashing. */ + FSL_HMAC_FLAGS_LOAD = 4, + /*! + * PAD message and perform final HMAC operations of inner and outer + * hashes. + */ + FSL_HMAC_FLAGS_FINALIZE = 8, + /*! + * This means that the context contains precomputed inner and outer hash + * values. + */ + FSL_HMAC_FLAGS_PRECOMPUTES_PRESENT = 16, +} fsl_shw_hmac_ctx_flags_t; + +/*! + * Flags to control use of the #fsl_shw_scco_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_scco_set_flags() and #fsl_shw_scco_clear_flags() + */ +typedef enum fsl_shw_sym_ctx_flags_t { + /*! + * Context is empty. In ARC4, this means that the S-Box needs to be + * generated from the key. In #FSL_SYM_MODE_CBC mode, this allows an IV of + * zero to be specified. In #FSL_SYM_MODE_CTR mode, it means that an + * initial CTR value of zero is desired. + */ + FSL_SYM_CTX_INIT = 1, + /*! + * Load context from object into hardware before running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_LOAD = 2, + /*! + * Save context from hardware into object after running cipher. In + * #FSL_SYM_MODE_CTR mode, this would refer to the Counter Value. + */ + FSL_SYM_CTX_SAVE = 4, + /*! + * Context (SBox) is to be unwrapped and wrapped on each use. + * This flag is unsupported. + * */ + FSL_SYM_CTX_PROTECT = 8, +} fsl_shw_sym_ctx_flags_t; + +/*! + * Flags which describe the state of the #fsl_shw_sko_t. + * + * These may be ORed together to get the desired effect. + * See #fsl_shw_sko_set_flags() and #fsl_shw_sko_clear_flags() + */ +typedef enum fsl_shw_key_flags_t { + /*! If algorithm is DES or 3DES, do not validate the key parity bits. */ + FSL_SKO_KEY_IGNORE_PARITY = 1, + /*! Clear key is present in the object. */ + FSL_SKO_KEY_PRESENT = 2, + /*! + * Key has been established for use. This feature is not available for all + * platforms, nor for all algorithms and modes. + */ + FSL_SKO_KEY_ESTABLISHED = 4, + /*! + * Key intended for user (software) use; can be read cleartext from the + * keystore. + */ + FSL_SKO_KEY_SW_KEY = 8, +} fsl_shw_key_flags_t; + +/*! + * Type of value which is associated with an established key. + */ +typedef uint64_t key_userid_t; + +/*! + * Flags which describe the state of the #fsl_shw_acco_t. + * + * The @a FSL_ACCO_CTX_INIT and @a FSL_ACCO_CTX_FINALIZE flags, when used + * together, provide for a one-shot operation. + */ +typedef enum fsl_shw_auth_ctx_flags_t { + /*! Initialize Context(s) */ + FSL_ACCO_CTX_INIT = 1, + /*! Load intermediate context(s). This flag is unsupported. */ + FSL_ACCO_CTX_LOAD = 2, + /*! Save intermediate context(s). This flag is unsupported. */ + FSL_ACCO_CTX_SAVE = 4, + /*! Create MAC during this operation. */ + FSL_ACCO_CTX_FINALIZE = 8, + /*! + * Formatting of CCM input data is performed by calls to + * #fsl_shw_ccm_nist_format_ctr_and_iv() and + * #fsl_shw_ccm_nist_update_ctr_and_iv(). + */ + FSL_ACCO_NIST_CCM = 0x10, +} fsl_shw_auth_ctx_flags_t; + +/*! + * The operation which controls the behavior of #fsl_shw_establish_key(). + * + * These values are passed to #fsl_shw_establish_key(). + */ +typedef enum fsl_shw_key_wrap_t { + /*! Generate a key from random values. */ + FSL_KEY_WRAP_CREATE, + /*! Use the provided clear key. */ + FSL_KEY_WRAP_ACCEPT, + /*! Unwrap a previously wrapped key. */ + FSL_KEY_WRAP_UNWRAP +} fsl_shw_key_wrap_t; + +/*! + * Modulus Selector for CTR modes. + * + * The incrementing of the Counter value may be modified by a modulus. If no + * modulus is needed or desired for AES, use #FSL_CTR_MOD_128. + */ +typedef enum fsl_shw_ctr_mod_t { + FSL_CTR_MOD_8, /*!< Run counter with modulus of 2^8. */ + FSL_CTR_MOD_16, /*!< Run counter with modulus of 2^16. */ + FSL_CTR_MOD_24, /*!< Run counter with modulus of 2^24. */ + FSL_CTR_MOD_32, /*!< Run counter with modulus of 2^32. */ + FSL_CTR_MOD_40, /*!< Run counter with modulus of 2^40. */ + FSL_CTR_MOD_48, /*!< Run counter with modulus of 2^48. */ + FSL_CTR_MOD_56, /*!< Run counter with modulus of 2^56. */ + FSL_CTR_MOD_64, /*!< Run counter with modulus of 2^64. */ + FSL_CTR_MOD_72, /*!< Run counter with modulus of 2^72. */ + FSL_CTR_MOD_80, /*!< Run counter with modulus of 2^80. */ + FSL_CTR_MOD_88, /*!< Run counter with modulus of 2^88. */ + FSL_CTR_MOD_96, /*!< Run counter with modulus of 2^96. */ + FSL_CTR_MOD_104, /*!< Run counter with modulus of 2^104. */ + FSL_CTR_MOD_112, /*!< Run counter with modulus of 2^112. */ + FSL_CTR_MOD_120, /*!< Run counter with modulus of 2^120. */ + FSL_CTR_MOD_128 /*!< Run counter with modulus of 2^128. */ +} fsl_shw_ctr_mod_t; + +/*! + * Permissions flags for Secure Partitions + */ +typedef enum fsl_shw_permission_t { +/*! SCM Access Permission: Do not zeroize/deallocate partition on SMN Fail state */ + FSL_PERM_NO_ZEROIZE = 0x80000000, +/*! SCM Access Permission: Enforce trusted key read in */ + FSL_PERM_TRUSTED_KEY_READ = 0x40000000, +/*! SCM Access Permission: Ignore Supervisor/User mode in permission determination */ + FSL_PERM_HD_S = 0x00000800, +/*! SCM Access Permission: Allow Read Access to Host Domain */ + FSL_PERM_HD_R = 0x00000400, +/*! SCM Access Permission: Allow Write Access to Host Domain */ + FSL_PERM_HD_W = 0x00000200, +/*! SCM Access Permission: Allow Execute Access to Host Domain */ + FSL_PERM_HD_X = 0x00000100, +/*! SCM Access Permission: Allow Read Access to Trusted Host Domain */ + FSL_PERM_TH_R = 0x00000040, +/*! SCM Access Permission: Allow Write Access to Trusted Host Domain */ + FSL_PERM_TH_W = 0x00000020, +/*! SCM Access Permission: Allow Read Access to Other/World Domain */ + FSL_PERM_OT_R = 0x00000004, +/*! SCM Access Permission: Allow Write Access to Other/World Domain */ + FSL_PERM_OT_W = 0x00000002, +/*! SCM Access Permission: Allow Execute Access to Other/World Domain */ + FSL_PERM_OT_X = 0x00000001, +} fsl_shw_permission_t; + +typedef enum fsl_shw_cypher_mode_t { + FSL_SHW_CYPHER_MODE_ECB = 1, /*!< ECB mode */ + FSL_SHW_CYPHER_MODE_CBC = 2, /*!< CBC mode */ +} fsl_shw_cypher_mode_t; + +typedef enum fsl_shw_pf_key_t { + FSL_SHW_PF_KEY_IIM, /*!< Present fused IIM key */ + FSL_SHW_PF_KEY_PRG, /*!< Present Program key */ + FSL_SHW_PF_KEY_IIM_PRG, /*!< Present IIM ^ Program key */ + FSL_SHW_PF_KEY_IIM_RND, /*!< Present Random key */ + FSL_SHW_PF_KEY_RND, /*!< Present IIM ^ Random key */ +} fsl_shw_pf_key_t; + +typedef enum fsl_shw_tamper_t { + FSL_SHW_TAMPER_NONE, /*!< No error detected */ + FSL_SHW_TAMPER_WTD, /*!< wire-mesh tampering det */ + FSL_SHW_TAMPER_ETBD, /*!< ext tampering det: input B */ + FSL_SHW_TAMPER_ETAD, /*!< ext tampering det: input A */ + FSL_SHW_TAMPER_EBD, /*!< external boot detected */ + FSL_SHW_TAMPER_SAD, /*!< security alarm detected */ + FSL_SHW_TAMPER_TTD, /*!< temperature tampering det */ + FSL_SHW_TAMPER_CTD, /*!< clock tampering det */ + FSL_SHW_TAMPER_VTD, /*!< voltage tampering det */ + FSL_SHW_TAMPER_MCO, /*!< monotonic counter overflow */ + FSL_SHW_TAMPER_TCO, /*!< time counter overflow */ +} fsl_shw_tamper_t; + +/****************************************************************************** + * Data Structures + *****************************************************************************/ + +/*! + * + * @brief Structure type for descriptors + * + * The first five fields are passed to the hardware. + * + *****************************************************************************/ +#ifndef USE_NEW_PTRS /* Experimental */ + +typedef struct sah_Desc { + uint32_t header; /*!< descriptor header value */ + uint32_t len1; /*!< number of data bytes in 'ptr1' buffer */ + void *ptr1; /*!< pointer to first sah_Link structure */ + uint32_t len2; /*!< number of data bytes in 'ptr2' buffer */ + void *ptr2; /*!< pointer to second sah_Link structure */ + struct sah_Desc *next; /*!< pointer to next descriptor */ +#ifdef __KERNEL__ /* This needs a better test */ + /* These two must be last. See sah_Copy_Descriptors */ + struct sah_Desc *virt_addr; /*!< Virtual (kernel) address of this + descriptor. */ + dma_addr_t dma_addr; /*!< Physical (bus) address of this + descriptor. */ + void *original_ptr1; /*!< user's pointer to ptr1 */ + void *original_ptr2; /*!< user's pointer to ptr2 */ + struct sah_Desc *original_next; /*!< user's pointer to next */ +#endif +} sah_Desc; + +#else + +typedef struct sah_Desc { + uint32_t header; /*!< descriptor header value */ + uint32_t len1; /*!< number of data bytes in 'ptr1' buffer */ + uint32_t hw_ptr1; /*!< pointer to first sah_Link structure */ + uint32_t len2; /*!< number of data bytes in 'ptr2' buffer */ + uint32_t hw_ptr2; /*!< pointer to second sah_Link structure */ + uint32_t hw_next; /*!< pointer to next descriptor */ + struct sah_Link *ptr1; /*!< (virtual) pointer to first sah_Link structure */ + struct sah_Link *ptr2; /*!< (virtual) pointer to first sah_Link structure */ + struct sah_Desc *next; /*!< (virtual) pointer to next descriptor */ +#ifdef __KERNEL__ /* This needs a better test */ + /* These two must be last. See sah_Copy_Descriptors */ + struct sah_Desc *virt_addr; /*!< Virtual (kernel) address of this + descriptor. */ + dma_addr_t dma_addr; /*!< Physical (bus) address of this + descriptor. */ +#endif +} sah_Desc; + +#endif + +/*! +******************************************************************************* +* @brief The first descriptor in a chain +******************************************************************************/ +typedef struct sah_Head_Desc { + sah_Desc desc; /*!< whole struct - must be first */ + struct fsl_shw_uco_t *user_info; /*!< where result pool lives */ + uint32_t user_ref; /*!< at time of request */ + uint32_t uco_flags; /*!< at time of request */ + uint32_t status; /*!< Status of queue entry */ + uint32_t error_status; /*!< If error, register from Sahara */ + uint32_t fault_address; /*!< If error, register from Sahara */ + uint32_t op_status; /*!< If error, register from Sahara */ + fsl_shw_return_t result; /*!< Result of running descriptor */ + struct sah_Head_Desc *next; /*!< Next in queue */ + struct sah_Head_Desc *prev; /*!< previous in queue */ + struct sah_Head_Desc *user_desc; /*!< For API async get_results */ + void *out1_ptr; /*!< For async post-processing */ + void *out2_ptr; /*!< For async post-processing */ + uint32_t out_len; /*!< For async post-processing */ +} sah_Head_Desc; + +/*! + * @brief Structure type for links + * + * The first three fields are used by hardware. + *****************************************************************************/ +#ifndef USE_NEW_PTRS + +typedef struct sah_Link { + size_t len; /*!< len of 'data' buffer in bytes */ + uint8_t *data; /*!< buffer to store data */ + struct sah_Link *next; /*!< pointer to the next sah_Link storing + * data */ + sah_Link_Flags flags; /*!< indicates the component that created the + * data buffer. Security Function internal + * information */ + key_userid_t ownerid; /*!< Auth code for established key */ + uint32_t slot; /*!< Location of the the established key */ +#ifdef __KERNEL__ /* This needs a better test */ + /* These two elements must be last. See sah_Copy_Links() */ + struct sah_Link *virt_addr; + dma_addr_t dma_addr; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) + struct page *vm_info; +#endif + uint8_t *original_data; /*!< user's version of data pointer */ + struct sah_Link *original_next; /*!< user's version of next pointer */ +#ifdef SAH_COPY_DATA + uint8_t *copy_data; /*!< Virtual address of acquired buffer */ +#endif +#endif /* kernel-only */ +} sah_Link; + +#else + +typedef struct sah_Link { + /*! len of 'data' buffer in bytes */ + size_t len; + /*! buffer to store data */ + uint32_t hw_data; + /*! Physical address */ + uint32_t hw_next; + /*! + * indicates the component that created the data buffer. Security Function + * internal information + */ + sah_Link_Flags flags; + /*! (virtual) pointer to data */ + uint8_t *data; + /*! (virtual) pointer to the next sah_Link storing data */ + struct sah_Link *next; + /*! Auth code for established key */ + key_userid_t ownerid; + /*! Location of the the established key */ + uint32_t slot; +#ifdef __KERNEL__ /* This needs a better test */ + /* These two elements must be last. See sah_Copy_Links() */ + struct sah_Link *virt_addr; + dma_addr_t dma_addr; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) + struct page *vm_info; +#endif +#endif /* kernel-only */ +} sah_Link; + +#endif + +/*! + * Initialization Object + */ +typedef struct fsl_sho_ibo_t { +} fsl_sho_ibo_t; + +/* Imported from Sahara1 driver -- is it needed forever? */ +/*! +******************************************************************************* +* FIELDS +* +* void * ref - parameter to be passed into the memory function calls +* +* void * (*malloc)(void *ref, size_t n) - pointer to user's malloc function +* +* void (*free)(void *ref, void *ptr) - pointer to user's free function +* +* void * (*memcpy)(void *ref, void *dest, const void *src, size_t n) - +* pointer to user's memcpy function +* +* void * (*memset)(void *ref, void *ptr, int ch, size_t n) - pointer to +* user's memset function +* +* @brief Structure for API memory utilities +******************************************************************************/ +typedef struct sah_Mem_Util { + /*! Who knows. Vestigial. */ + void *mu_ref; + /*! Acquire buffer of size n bytes */ + void *(*mu_malloc) (void *ref, size_t n); + /*! Acquire a sah_Head_Desc */ + sah_Head_Desc *(*mu_alloc_head_desc) (void *ref); + /* Acquire a sah_Desc */ + sah_Desc *(*mu_alloc_desc) (void *ref); + /* Acquire a sah_Link */ + sah_Link *(*mu_alloc_link) (void *ref); + /*! Free buffer at ptr */ + void (*mu_free) (void *ref, void *ptr); + /*! Free sah_Head_Desc at ptr */ + void (*mu_free_head_desc) (void *ref, sah_Head_Desc * ptr); + /*! Free sah_Desc at ptr */ + void (*mu_free_desc) (void *ref, sah_Desc * ptr); + /*! Free sah_Link at ptr */ + void (*mu_free_link) (void *ref, sah_Link * ptr); + /*! Funciton which will copy n bytes from src to dest */ + void *(*mu_memcpy) (void *ref, void *dest, const void *src, size_t n); + /*! Set all n bytes of ptr to ch */ + void *(*mu_memset) (void *ref, void *ptr, int ch, size_t n); +} sah_Mem_Util; + +/*! + * Secure Partition information + * + * This holds the context to a single secure partition owned by the user. It + * is only available in the kernel version of the User Context Object. + */ +typedef struct fsl_shw_spo_t { + uint32_t user_base; /*!< Base address (user virtual) */ + void *kernel_base; /*!< Base address (kernel virtual) */ + struct fsl_shw_spo_t *next; /*!< Pointer to the next partition + owned by the user. NULL if this + is the last partition. */ +} fsl_shw_spo_t; + +/* REQ-S2LRD-PINTFC-COA-UCO-001 */ +/*! + * User Context Object + */ +typedef struct fsl_shw_uco_t { + int sahara_openfd; /*!< this should be kernel-only?? */ + sah_Mem_Util *mem_util; /*!< Memory utility fns */ + uint32_t user_ref; /*!< User's reference */ + void (*callback) (struct fsl_shw_uco_t * uco); /*!< User's callback fn */ + uint32_t flags; /*!< from fsl_shw_user_ctx_flags_t */ + unsigned pool_size; /*!< maximum size of user pool */ +#ifdef __KERNEL__ + sah_Queue result_pool; /*!< where non-blocking results go */ + os_process_handle_t process; /*!< remember for signalling User mode */ + fsl_shw_spo_t *partition; /*!< chain of secure partitions owned by + the user */ +#else + struct fsl_shw_uco_t *next; /*!< To allow user-mode chaining of contexts, + for signalling. */ +#endif +} fsl_shw_uco_t; + +/* REQ-S2LRD-PINTFC-API-GEN-006 ?? */ +/*! + * Result object + */ +typedef struct fsl_shw_result_t { + uint32_t user_ref; + fsl_shw_return_t code; + uint32_t detail1; + uint32_t detail2; + sah_Head_Desc *user_desc; +} fsl_shw_result_t; + +/*! + * Keystore Object + */ +typedef struct fsl_shw_kso_t { +#ifdef __KERNEL__ + os_lock_t lock; /*!< Pointer to lock that controls access to + the keystore. */ +#endif + void *user_data; /*!< Pointer to user structure that handles + the internals of the keystore. */ + fsl_shw_return_t(*data_init) (fsl_shw_uco_t * user_ctx, + void **user_data); + void (*data_cleanup) (fsl_shw_uco_t * user_ctx, void **user_data); + fsl_shw_return_t(*slot_verify_access) (void *user_data, + uint64_t owner_id, + uint32_t slot); + fsl_shw_return_t(*slot_alloc) (void *user_data, uint32_t size_bytes, + uint64_t owner_id, uint32_t * slot); + fsl_shw_return_t(*slot_dealloc) (void *user_data, uint64_t owner_id, + uint32_t slot); + void *(*slot_get_address) (void *user_data, uint32_t slot); + uint32_t(*slot_get_base) (void *user_data, uint32_t slot); + uint32_t(*slot_get_offset) (void *user_data, uint32_t slot); + uint32_t(*slot_get_slot_size) (void *user_data, uint32_t slot); +} fsl_shw_kso_t; + +/* REQ-S2LRD-PINTFC-COA-SKO-001 */ +/*! + * Secret Key Context Object + */ +typedef struct fsl_shw_sko_t { + uint32_t flags; + fsl_shw_key_alg_t algorithm; + key_userid_t userid; + uint32_t handle; + uint16_t key_length; + uint8_t key[64]; + struct fsl_shw_kso_t *keystore; /*!< If present, key is in keystore */ +} fsl_shw_sko_t; + +/* REQ-S2LRD-PINTFC-COA-CO-001 */ +/*! + * @brief Platform Capability Object + */ +typedef struct fsl_shw_pco_t { /* Consider turning these constants into symbols */ + int api_major; + int api_minor; + int driver_major; + int driver_minor; + fsl_shw_key_alg_t sym_algorithms[4]; + fsl_shw_sym_mode_t sym_modes[4]; + fsl_shw_hash_alg_t hash_algorithms[4]; + uint8_t sym_support[5][4]; /* indexed by key alg then mode */ + + int scc_driver_major; + int scc_driver_minor; + int scm_version; /*!< Version from SCM Configuration register */ + int smn_version; /*!< Version from SMN Status register */ + int block_size_bytes; /*!< Number of bytes per block of RAM; also + block size of the crypto algorithm. */ + union { + struct { + int black_ram_size_blocks; /*!< Number of blocks of Black RAM */ + int red_ram_size_blocks; /*!< Number of blocks of Red RAM */ + } scc_info; + struct { + int partition_size_bytes; /*!< Number of bytes in each partition */ + int partition_count; /*!< Number of partitions on this platform */ + } scc2_info; + }; +} fsl_shw_pco_t; + +/* REQ-S2LRD-PINTFC-COA-HCO-001 */ +/*! + * Hash Context Object + */ +typedef struct fsl_shw_hco_t { /* fsl_shw_hash_context_object */ + fsl_shw_hash_alg_t algorithm; + uint32_t flags; + uint8_t digest_length; /* in bytes */ + uint8_t context_length; /* in bytes */ + uint8_t context_register_length; /* in bytes */ + uint32_t context[9]; /* largest digest + msg size */ +} fsl_shw_hco_t; + +/*! + * HMAC Context Object + */ +typedef struct fsl_shw_hmco_t { /* fsl_shw_hmac_context_object */ + fsl_shw_hash_alg_t algorithm; + uint32_t flags; + uint8_t digest_length; /*!< in bytes */ + uint8_t context_length; /*!< in bytes */ + uint8_t context_register_length; /*!< in bytes */ + uint32_t ongoing_context[9]; /*!< largest digest + msg + size */ + uint32_t inner_precompute[9]; /*!< largest digest + msg + size */ + uint32_t outer_precompute[9]; /*!< largest digest + msg + size */ +} fsl_shw_hmco_t; + +/* REQ-S2LRD-PINTFC-COA-SCCO-001 */ +/*! + * Symmetric Crypto Context Object Context Object + */ +typedef struct fsl_shw_scco_t { + uint32_t flags; + unsigned block_size_bytes; /* double duty block&ctx size */ + fsl_shw_sym_mode_t mode; + /* Could put modulus plus 16-octet context in union with arc4 + sbox+ptrs... */ + fsl_shw_ctr_mod_t modulus_exp; + uint8_t context[259]; +} fsl_shw_scco_t; + +/*! + * Authenticate-Cipher Context Object + + * An object for controlling the function of, and holding information about, + * data for the authenticate-cipher functions, #fsl_shw_gen_encrypt() and + * #fsl_shw_auth_decrypt(). + */ +typedef struct fsl_shw_acco_t { + uint32_t flags; /*!< See #fsl_shw_auth_ctx_flags_t for + meanings */ + fsl_shw_acc_mode_t mode; /*!< CCM only */ + uint8_t mac_length; /*!< User's value for length */ + unsigned q_length; /*!< NIST parameter - */ + fsl_shw_scco_t cipher_ctx_info; /*!< For running + encrypt/decrypt. */ + union { + fsl_shw_scco_t CCM_ctx_info; /*!< For running the CBC in + AES-CCM. */ + fsl_shw_hco_t hash_ctx_info; /*!< For running the hash */ + } auth_info; /*!< "auth" info struct */ + uint8_t unencrypted_mac[16]; /*!< max block size... */ +} fsl_shw_acco_t; + +/*! + * Used by Sahara API to retrieve completed non-blocking results. + */ +typedef struct sah_results { + unsigned requested; /*!< number of results requested */ + unsigned *actual; /*!< number of results obtained */ + fsl_shw_result_t *results; /*!< pointer to memory to hold results */ +} sah_results; + +/*! + * @typedef scc_partition_status_t + */ +/*! Partition status information. */ +typedef enum fsl_shw_partition_status_t { + FSL_PART_S_UNUSABLE, /*!< Partition not implemented */ + FSL_PART_S_UNAVAILABLE, /*!< Partition owned by other host */ + FSL_PART_S_AVAILABLE, /*!< Partition available */ + FSL_PART_S_ALLOCATED, /*!< Partition owned by host but not engaged + */ + FSL_PART_S_ENGAGED, /*!< Partition owned by host and engaged */ +} fsl_shw_partition_status_t; + +/****************************************************************************** + * Access Macros for Objects + *****************************************************************************/ +/*! + * Get FSL SHW API version + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the API is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the API is to be stored. + */ +#define fsl_shw_pco_get_version(pcobject, pcmajor, pcminor) \ +{ \ + *(pcmajor) = (pcobject)->api_major; \ + *(pcminor) = (pcobject)->api_minor; \ +} + +/*! + * Get underlying driver version. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the driver is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the driver is to be stored. + */ +#define fsl_shw_pco_get_driver_version(pcobject, pcmajor, pcminor) \ +{ \ + *(pcmajor) = (pcobject)->driver_major; \ + *(pcminor) = (pcobject)->driver_minor; \ +} + +/*! + * Get list of symmetric algorithms supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] pcalgorithms A pointer to where to store the location of + * the list of algorithms. + * @param[out] pcacount A pointer to where to store the number of + * algorithms in the list at @a algorithms. + */ +#define fsl_shw_pco_get_sym_algorithms(pcobject, pcalgorithms, pcacount) \ +{ \ + *(pcalgorithms) = (pcobject)->sym_algorithms; \ + *(pcacount) = sizeof((pcobject)->sym_algorithms)/4; \ +} + +/*! + * Get list of symmetric modes supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] gsmodes A pointer to where to store the location of + * the list of modes. + * @param[out] gsacount A pointer to where to store the number of + * algorithms in the list at @a modes. + */ +#define fsl_shw_pco_get_sym_modes(pcobject, gsmodes, gsacount) \ +{ \ + *(gsmodes) = (pcobject)->sym_modes; \ + *(gsacount) = sizeof((pcobject)->sym_modes)/4; \ +} + +/*! + * Get list of hash algorithms supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param[out] gsalgorithms A pointer which will be set to the list of + * algorithms. + * @param[out] gsacount The number of algorithms in the list at @a + * algorithms. + */ +#define fsl_shw_pco_get_hash_algorithms(pcobject, gsalgorithms, gsacount) \ +{ \ + *(gsalgorithms) = (pcobject)->hash_algorithms; \ + *(gsacount) = sizeof((pcobject)->hash_algorithms)/4; \ +} + +/*! + * Determine whether the combination of a given symmetric algorithm and a given + * mode is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param pcalg A Symmetric Cipher algorithm. + * @param pcmode A Symmetric Cipher mode. + * + * @return 0 if combination is not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_sym_supported(pcobject, pcalg, pcmode) \ + ((pcobject)->sym_support[pcalg][pcmode]) + +/*! + * Determine whether a given Encryption-Authentication mode is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * @param pcmode The Authentication mode. + * + * @return 0 if mode is not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_auth_supported(pcobject, pcmode) \ + ((pcmode == FSL_ACC_MODE_CCM) ? 1 : 0) + +/*! + * Determine whether Black Keys (key establishment / wrapping) is supported. + * + * @param pcobject The Platform Capababilities Object to query. + * + * @return 0 if wrapping is not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_black_key_supported(pcobject) \ + 1 + +/*! + * Determine whether Programmed Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Programmed Key features are available, otherwise zero. + */ +#define fsl_shw_pco_check_pk_supported(pcobject) \ + 0 + +/*! + * Determine whether Software Key features are available + * + * @param pc_info The Platform Capabilities Object to query. + * + * @return 1 if Software key features are available, otherwise zero. + */ +#define fsl_shw_pco_check_sw_keys_supported(pcobject) \ + 0 + +/*! + * Get FSL SHW SCC driver version + * + * @param pcobject The Platform Capabilities Object to query. + * @param[out] pcmajor A pointer to where the major version + * of the SCC driver is to be stored. + * @param[out] pcminor A pointer to where the minor version + * of the SCC driver is to be stored. + */ +#define fsl_shw_pco_get_scc_driver_version(pcobject, pcmajor, pcminor) \ +{ \ + *(pcmajor) = (pcobject)->scc_driver_major; \ + *(pcminor) = (pcobject)->scc_driver_minor; \ +} + +/*! + * Get SCM hardware version + * + * @param pcobject The Platform Capabilities Object to query. + * @return The SCM hardware version + */ +#define fsl_shw_pco_get_scm_version(pcobject) \ + ((pcobject)->scm_version) + +/*! + * Get SMN hardware version + * + * @param pcobject The Platform Capabilities Object to query. + * @return The SMN hardware version + */ +#define fsl_shw_pco_get_smn_version(pcobject) \ + ((pcobject)->smn_version) + +/*! + * Get the size of an SCM block, in bytes + * + * @param pcobject The Platform Capabilities Object to query. + * @return The size of an SCM block, in bytes. + */ +#define fsl_shw_pco_get_scm_block_size(pcobject) \ + ((pcobject)->block_size_bytes) + +/*! + * Get size of Black and Red RAM memory + * + * @param pcobject The Platform Capabilities Object to query. + * @param[out] black_size A pointer to where the size of the Black RAM, in + * blocks, is to be placed. + * @param[out] red_size A pointer to where the size of the Red RAM, in + * blocks, is to be placed. + */ +#define fsl_shw_pco_get_smn_size(pcobject, black_size, red_size) \ +{ \ + if ((pcobject)->scm_version == 1) { \ + *(black_size) = (pcobject)->scc_info.black_ram_size_blocks; \ + *(red_size) = (pcobject)->scc_info.red_ram_size_blocks; \ + } else { \ + *(black_size) = 0; \ + *(red_size) = 0; \ + } \ +} + +/*! + * Determine whether Secure Partitions are supported + * + * @param pcobject The Platform Capabilities Object to query. + * + * @return 0 if secure partitions are not supported, non-zero if supported. + */ +#define fsl_shw_pco_check_spo_supported(pcobject) \ + ((pcobject)->scm_version == 2) + +/*! + * Get the size of a Secure Partitions + * + * @param pcobject The Platform Capabilities Object to query. + * + * @return Partition size, in bytes. 0 if Secure Partitions not supported. + */ +#define fsl_shw_pco_get_spo_size_bytes(pcobject) \ + (((pcobject)->scm_version == 2) ? \ + ((pcobject)->scc2_info.partition_size_bytes) : 0 ) + +/*! + * Get the number of Secure Partitions on this platform + * + * @param pcobject The Platform Capabilities Object to query. + * + * @return Number of partitions. 0 if Secure Paritions not supported. Note + * that this returns the total number of partitions, not all may be + * available to the user. + */ +#define fsl_shw_pco_get_spo_count(pcobject) \ + (((pcobject)->scm_version == 2) ? \ + ((pcobject)->scc2_info.partition_count) : 0 ) + +/*! + * Initialize a User Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the User Context Object to initial values, and set the size + * of the results pool. The mode will be set to a default of + * #FSL_UCO_BLOCKING_MODE. + * + * When using non-blocking operations, this sets the maximum number of + * operations which can be outstanding. This number includes the counts of + * operations waiting to start, operation(s) being performed, and results which + * have not been retrieved. + * + * Changes to this value are ignored once user registration has completed. It + * should be set to 1 if only blocking operations will ever be performed. + * + * @param ucontext The User Context object to operate on. + * @param usize The maximum number of operations which can be + * outstanding. + */ +#ifdef __KERNEL__ +#define fsl_shw_uco_init(ucontext, usize) \ +{ \ + (ucontext)->pool_size = usize; \ + (ucontext)->flags = FSL_UCO_BLOCKING_MODE; \ + (ucontext)->sahara_openfd = -1; \ + (ucontext)->mem_util = NULL; \ + (ucontext)->partition = NULL; \ + (ucontext)->callback = NULL; \ +} +#else +#define fsl_shw_uco_init(ucontext, usize) \ +{ \ + (ucontext)->pool_size = usize; \ + (ucontext)->flags = FSL_UCO_BLOCKING_MODE; \ + (ucontext)->sahara_openfd = -1; \ + (ucontext)->mem_util = NULL; \ + (ucontext)->callback = NULL; \ +} +#endif + +/*! + * Set the User Reference for the User Context. + * + * @param ucontext The User Context object to operate on. + * @param uref A value which will be passed back with a result. + */ +#define fsl_shw_uco_set_reference(ucontext, uref) \ + (ucontext)->user_ref = uref + +/*! + * Set the User Reference for the User Context. + * + * @param ucontext The User Context object to operate on. + * @param ucallback The function the API will invoke when an operation + * completes. + */ +#define fsl_shw_uco_set_callback(ucontext, ucallback) \ + (ucontext)->callback = ucallback + +/*! + * Set flags in the User Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param ucontext The User Context object to operate on. + * @param uflags ORed values from #fsl_shw_user_ctx_flags_t. + */ +#define fsl_shw_uco_set_flags(ucontext, uflags) \ + (ucontext)->flags |= (uflags) + +/*! + * Clear flags in the User Context. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param ucontext The User Context object to operate on. + * @param uflags ORed values from #fsl_shw_user_ctx_flags_t. + */ +#define fsl_shw_uco_clear_flags(ucontext, uflags) \ + (ucontext)->flags &= ~(uflags) + +/*! + * Retrieve the reference value from a Result Object. + * + * @param robject The result object to query. + * + * @return The reference associated with the request. + */ +#define fsl_shw_ro_get_reference(robject) \ + (robject)->user_ref + +/*! + * Retrieve the status code from a Result Object. + * + * @param robject The result object to query. + * + * @return The status of the request. + */ +#define fsl_shw_ro_get_status(robject) \ + (robject)->code + +/*! + * Initialize a Secret Key Object. + * + * This function must be called before performing any other operation with + * the Object. + * + * @param skobject The Secret Key Object to be initialized. + * @param skalgorithm DES, AES, etc. + * + */ +#define fsl_shw_sko_init(skobject,skalgorithm) \ +{ \ + (skobject)->algorithm = skalgorithm; \ + (skobject)->flags = 0; \ + (skobject)->keystore = NULL; \ +} + +/*! + * Initialize a Secret Key Object to use a Platform Key register. + * + * This function must be called before performing any other operation with + * the Object. INVALID on this platform. + * + * @param skobject The Secret Key Object to be initialized. + * @param skalgorithm DES, AES, etc. + * @param skhwkey one of the fsl_shw_pf_key_t values. + * + */ +#define fsl_shw_sko_init_pf_key(skobject,skalgorithm,skhwkey) \ +{ \ + (skobject)->algorithm = -1; \ + (skobject)->flags = -1; \ + (skobject)->keystore = NULL; \ +} + +/*! + * Store a cleartext key in the key object. + * + * This has the side effect of setting the #FSL_SKO_KEY_PRESENT flag and + * resetting the #FSL_SKO_KEY_ESTABLISHED flag. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skkey A pointer to the beginning of the key. + * @param skkeylen The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +#define fsl_shw_sko_set_key(skobject, skkey, skkeylen) \ +{ \ + (skobject)->key_length = skkeylen; \ + copy_bytes((skobject)->key, skkey, skkeylen); \ + (skobject)->flags |= FSL_SKO_KEY_PRESENT; \ + (skobject)->flags &= ~FSL_SKO_KEY_ESTABLISHED; \ +} + +/*! + * Set a size for the key. + * + * This function would normally be used when the user wants the key to be + * generated from a random source. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skkeylen The length, in octets, of the key. The value should be + * appropriate to the key size supported by the algorithm. + * 64 octets is the absolute maximum value allowed for this + * call. + */ +#define fsl_shw_sko_set_key_length(skobject, skkeylen) \ + (skobject)->key_length = skkeylen; + +/*! + * Set the User ID associated with the key. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skuserid The User ID to identify authorized users of the key. + */ +#define fsl_shw_sko_set_user_id(skobject, skuserid) \ + (skobject)->userid = (skuserid) + +/*! + * Establish a user Keystore to hold the key. + */ +#define fsl_shw_sko_set_keystore(skobject, user_keystore) \ + (skobject)->keystore = (user_keystore) + +/*! + * Set the establish key handle into a key object. + * + * The @a userid field will be used to validate the access to the unwrapped + * key. This feature is not available for all platforms, nor for all + * algorithms and modes. + * + * The #FSL_SKO_KEY_ESTABLISHED will be set (and the #FSL_SKO_KEY_PRESENT flag + * will be cleared). + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skuserid The User ID to verify this user is an authorized user of + * the key. + * @param skhandle A @a handle from #fsl_shw_sko_get_established_info. + */ +#define fsl_shw_sko_set_established_info(skobject, skuserid, skhandle) \ +{ \ + (skobject)->userid = (skuserid); \ + (skobject)->handle = (skhandle); \ + (skobject)->flags |= FSL_SKO_KEY_ESTABLISHED; \ + (skobject)->flags &= \ + ~(FSL_SKO_KEY_PRESENT); \ +} + +/*! + * Retrieve the established-key handle from a key object. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skhandle The location to store the @a handle of the unwrapped + * key. + */ +#define fsl_shw_sko_get_established_info(skobject, skhandle) \ + *(skhandle) = (skobject)->handle + +/*! + * Extract the algorithm from a key object. + * + * @param skobject The Key Object to be queried. + * @param[out] skalgorithm A pointer to the location to store the algorithm. + */ +#define fsl_shw_sko_get_algorithm(skobject, skalgorithm) \ + *(skalgorithm) = (skobject)->algorithm + +/*! + * Retrieve the cleartext key from a key object that is stored in a user + * keystore. + * + * @param skobject The Key Object to be queried. + * @param[out] skkey A pointer to the location to store the key. NULL + * if the key is not stored in a user keystore. + */ +#define fsl_shw_sko_get_key(skobject, skkey) \ +{ \ + fsl_shw_kso_t* keystore = (skobject)->keystore; \ + if (keystore != NULL) { \ + *(skkey) = keystore->slot_get_address(keystore->user_data, \ + (skobject)->handle); \ + } else { \ + *(skkey) = NULL; \ + } \ +} + +/*! + * Determine the size of a wrapped key based upon the cleartext key's length. + * + * This function can be used to calculate the number of octets that + * #fsl_shw_extract_key() will write into the location at @a covered_key. + * + * If zero is returned at @a length, this means that the key length in + * @a key_info is not supported. + * + * @param wkeyinfo Information about a key to be wrapped. + * @param wkeylen Location to store the length of a wrapped + * version of the key in @a key_info. + */ +#define fsl_shw_sko_calculate_wrapped_size(wkeyinfo, wkeylen) \ +{ \ + register fsl_shw_sko_t* kp = wkeyinfo; \ + register uint32_t kl = kp->key_length; \ + int key_blocks = (kl + 15) / 16; \ + int base_size = 35; /* ICV + T' + ALG + LEN + FLAGS */ \ + \ + *(wkeylen) = base_size + 16 * key_blocks; \ +} + +/*! + * Set some flags in the key object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skflags (One or more) ORed members of #fsl_shw_key_flags_t which + * are to be set. + */ +#define fsl_shw_sko_set_flags(skobject, skflags) \ + (skobject)->flags |= (skflags) + +/*! + * Clear some flags in the key object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param skobject A variable of type #fsl_shw_sko_t. + * @param skflags (One or more) ORed members of #fsl_shw_key_flags_t + * which are to be reset. + */ +#define fsl_shw_sko_clear_flags(skobject, skflags) \ + (skobject)->flags &= ~(skflags) + +/*! + * Initialize a Hash Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the hash + * context object. + * + * @param hcobject The hash context to operate upon. + * @param hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +#define fsl_shw_hco_init(hcobject, hcalgorithm) \ +{ \ + (hcobject)->algorithm = hcalgorithm; \ + (hcobject)->flags = 0; \ + switch (hcalgorithm) { \ + case FSL_HASH_ALG_MD5: \ + (hcobject)->digest_length = 16; \ + (hcobject)->context_length = 16; \ + (hcobject)->context_register_length = 24; \ + break; \ + case FSL_HASH_ALG_SHA1: \ + (hcobject)->digest_length = 20; \ + (hcobject)->context_length = 20; \ + (hcobject)->context_register_length = 24; \ + break; \ + case FSL_HASH_ALG_SHA224: \ + (hcobject)->digest_length = 28; \ + (hcobject)->context_length = 32; \ + (hcobject)->context_register_length = 36; \ + break; \ + case FSL_HASH_ALG_SHA256: \ + (hcobject)->digest_length = 32; \ + (hcobject)->context_length = 32; \ + (hcobject)->context_register_length = 36; \ + break; \ + default: \ + /* error ! */ \ + (hcobject)->digest_length = 1; \ + (hcobject)->context_length = 1; \ + (hcobject)->context_register_length = 1; \ + break; \ + } \ +} + +/*! + * Get the current hash value and message length from the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hcobject The hash context to query. + * @param[out] hccontext Pointer to the location of @a length octets where to + * store a copy of the current value of the digest. + * @param hcclength Number of octets of hash value to copy. + * @param[out] hcmsglen Pointer to the location to store the number of octets + * already hashed. + */ +#define fsl_shw_hco_get_digest(hcobject, hccontext, hcclength, hcmsglen) \ +{ \ + copy_bytes(hccontext, (hcobject)->context, hcclength); \ + if ((hcobject)->algorithm == FSL_HASH_ALG_SHA224 \ + || (hcobject)->algorithm == FSL_HASH_ALG_SHA256) { \ + *(hcmsglen) = (hcobject)->context[8]; \ + } else { \ + *(hcmsglen) = (hcobject)->context[5]; \ + } \ +} + +/*! + * Get the hash algorithm from the hash context object. + * + * @param hcobject The hash context to query. + * @param[out] hcalgorithm Pointer to where the algorithm is to be stored. + */ +#define fsl_shw_hco_get_info(hcobject, hcalgorithm) \ +{ \ + *(hcalgorithm) = (hcobject)->algorithm; \ +} + +/*! + * Set the current hash value and message length in the hash context object. + * + * The algorithm must have already been specified. See #fsl_shw_hco_init(). + * + * @param hcobject The hash context to operate upon. + * @param hccontext Pointer to buffer of appropriate length to copy into + * the hash context object. + * @param hcmsglen The number of octets of the message which have + * already been hashed. + * + */ +#define fsl_shw_hco_set_digest(hcobject, hccontext, hcmsglen) \ +{ \ + copy_bytes((hcobject)->context, hccontext, (hcobject)->context_length); \ + if (((hcobject)->algorithm == FSL_HASH_ALG_SHA224) \ + || ((hcobject)->algorithm == FSL_HASH_ALG_SHA256)) { \ + (hcobject)->context[8] = hcmsglen; \ + } else { \ + (hcobject)->context[5] = hcmsglen; \ + } \ +} + +/*! + * Set flags in a Hash Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The hash context to be operated on. + * @param hcflags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +#define fsl_shw_hco_set_flags(hcobject, hcflags) \ + (hcobject)->flags |= (hcflags) + +/*! + * Clear flags in a Hash Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The hash context to be operated on. + * @param hcflags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hash_ctx_flags_t. + */ +#define fsl_shw_hco_clear_flags(hcobject, hcflags) \ + (hcobject)->flags &= ~(hcflags) + +/*! + * Initialize an HMAC Context Object. + * + * This function must be called before performing any other operation with the + * Object. It sets the current message length and hash algorithm in the HMAC + * context object. + * + * @param hcobject The HMAC context to operate upon. + * @param hcalgorithm The hash algorithm to be used (#FSL_HASH_ALG_MD5, + * #FSL_HASH_ALG_SHA256, etc). + * + */ +#define fsl_shw_hmco_init(hcobject, hcalgorithm) \ + fsl_shw_hco_init(hcobject, hcalgorithm) + +/*! + * Set flags in an HMAC Context Object. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The HMAC context to be operated on. + * @param hcflags The flags to be set in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +#define fsl_shw_hmco_set_flags(hcobject, hcflags) \ + (hcobject)->flags |= (hcflags) + +/*! + * Clear flags in an HMAC Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param hcobject The HMAC context to be operated on. + * @param hcflags The flags to be reset in the context. These can be ORed + * members of #fsl_shw_hmac_ctx_flags_t. + */ +#define fsl_shw_hmco_clear_flags(hcobject, hcflags) \ + (hcobject)->flags &= ~(hcflags) + +/*! + * Initialize a Symmetric Cipher Context Object. + * + * This function must be called before performing any other operation with the + * Object. This will set the @a mode and @a algorithm and initialize the + * Object. + * + * @param scobject The context object to operate on. + * @param scalg The cipher algorithm this context will be used with. + * @param scmode #FSL_SYM_MODE_CBC, #FSL_SYM_MODE_ECB, etc. + * + */ +#define fsl_shw_scco_init(scobject, scalg, scmode) \ +{ \ + register uint32_t bsb; /* block-size bytes */ \ + \ + switch (scalg) { \ + case FSL_KEY_ALG_AES: \ + bsb = 16; \ + break; \ + case FSL_KEY_ALG_DES: \ + /* fall through */ \ + case FSL_KEY_ALG_TDES: \ + bsb = 8; \ + break; \ + case FSL_KEY_ALG_ARC4: \ + bsb = 259; \ + break; \ + case FSL_KEY_ALG_HMAC: \ + bsb = 1; /* meaningless */ \ + break; \ + default: \ + bsb = 00; \ + } \ + (scobject)->block_size_bytes = bsb; \ + (scobject)->mode = scmode; \ + (scobject)->flags = 0; \ +} + +/*! + * Set the flags for a Symmetric Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param scobject The context object to operate on. + * @param scflags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +#define fsl_shw_scco_set_flags(scobject, scflags) \ + (scobject)->flags |= (scflags) + +/*! + * Clear some flags in a Symmetric Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param scobject The context object to operate on. + * @param scflags The flags to reset (one or more values from + * #fsl_shw_sym_ctx_flags_t ORed together). + * + */ +#define fsl_shw_scco_clear_flags(scobject, scflags) \ + (scobject)->flags &= ~(scflags) + +/*! + * Set the Context (IV) for a Symmetric Cipher Context. + * + * This is to set the context/IV for #FSL_SYM_MODE_CBC mode, or to set the + * context (the S-Box and pointers) for ARC4. The full context size will + * be copied. + * + * @param scobject The context object to operate on. + * @param sccontext A pointer to the buffer which contains the context. + * + */ +#define fsl_shw_scco_set_context(scobject, sccontext) \ + copy_bytes((scobject)->context, sccontext, \ + (scobject)->block_size_bytes) + +/*! + * Get the Context for a Symmetric Cipher Context. + * + * This is to retrieve the context/IV for #FSL_SYM_MODE_CBC mode, or to + * retrieve context (the S-Box and pointers) for ARC4. The full context + * will be copied. + * + * @param scobject The context object to operate on. + * @param[out] sccontext Pointer to location where context will be stored. + */ +#define fsl_shw_scco_get_context(scobject, sccontext) \ + copy_bytes(sccontext, (scobject)->context, (scobject)->block_size_bytes) + +/*! + * Set the Counter Value for a Symmetric Cipher Context. + * + * This will set the Counter Value for CTR mode. + * + * @param scobject The context object to operate on. + * @param sccounter The starting counter value. The number of octets. + * copied will be the block size for the algorithm. + * @param scmodulus The modulus for controlling the incrementing of the + * counter. + * + */ +#define fsl_shw_scco_set_counter_info(scobject, sccounter, scmodulus) \ + { \ + if ((sccounter) != NULL) { \ + copy_bytes((scobject)->context, sccounter, \ + (scobject)->block_size_bytes); \ + } \ + (scobject)->modulus_exp = scmodulus; \ + } + +/*! + * Get the Counter Value for a Symmetric Cipher Context. + * + * This will retrieve the Counter Value is for CTR mode. + * + * @param scobject The context object to query. + * @param[out] sccounter Pointer to location to store the current counter + * value. The number of octets copied will be the + * block size for the algorithm. + * @param[out] scmodulus Pointer to location to store the modulus. + * + */ +#define fsl_shw_scco_get_counter_info(scobject, sccounter, scmodulus) \ + { \ + if ((sccounter) != NULL) { \ + copy_bytes(sccounter, (scobject)->context, \ + (scobject)->block_size_bytes); \ + } \ + if ((scmodulus) != NULL) { \ + *(scmodulus) = (scobject)->modulus_exp; \ + } \ + } + +/*! + * Initialize a Authentication-Cipher Context. + * + * @param acobject Pointer to object to operate on. + * @param acmode The mode for this object (only #FSL_ACC_MODE_CCM + * supported). + */ +#define fsl_shw_acco_init(acobject, acmode) \ + { \ + (acobject)->flags = 0; \ + (acobject)->mode = (acmode); \ + } + +/*! + * Set the flags for a Authentication-Cipher Context. + * + * Turns on the flags specified in @a flags. Other flags are untouched. + * + * @param acobject Pointer to object to operate on. + * @param acflags The flags to set (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +#define fsl_shw_acco_set_flags(acobject, acflags) \ + (acobject)->flags |= (acflags) + +/*! + * Clear some flags in a Authentication-Cipher Context Object. + * + * Turns off the flags specified in @a flags. Other flags are untouched. + * + * @param acobject Pointer to object to operate on. + * @param acflags The flags to reset (one or more from + * #fsl_shw_auth_ctx_flags_t ORed together). + * + */ +#define fsl_shw_acco_clear_flags(acobject, acflags) \ + (acobject)->flags &= ~(acflags) + +/*! + * Set up the Authentication-Cipher Object for CCM mode. + * + * This will set the @a auth_object for CCM mode and save the @a ctr, + * and @a mac_length. This function can be called instead of + * #fsl_shw_acco_init(). + * + * The paramater @a ctr is Counter Block 0, (counter value 0), which is for the + * MAC. + * + * @param acobject Pointer to object to operate on. + * @param acalg Cipher algorithm. Only AES is supported. + * @param accounter The initial counter value. + * @param acmaclen The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_acco_set_ccm(acobject, acalg, accounter, acmaclen) \ +{ \ + (acobject)->flags = 0; \ + (acobject)->mode = FSL_ACC_MODE_CCM; \ + (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16; \ + (acobject)->cipher_ctx_info.block_size_bytes = 16; \ + (acobject)->mac_length = acmaclen; \ + fsl_shw_scco_set_counter_info(&(acobject)->cipher_ctx_info, accounter, \ + FSL_CTR_MOD_128); \ +} + +/*! + * Format the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will also set the IV and CTR values per Appendix A of NIST + * Special Publication 800-38C (May 2004). It will also perform the + * #fsl_shw_acco_set_ccm() operation with information derived from this set of + * parameters. + * + * Note this function assumes the algorithm is AES. It initializes the + * @a auth_object by setting the mode to #FSL_ACC_MODE_CCM and setting the + * flags to be #FSL_ACCO_NIST_CCM. + * + * @param acobject Pointer to object to operate on. + * @param act The number of octets used for the MAC. Valid values are + * 4, 6, 8, 10, 12, 14, and 16. + * @param acad Number of octets of Associated Data (may be zero). + * @param acq A value for the size of the length of @a q field. Valid + * values are 1-8. + * @param acN The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param acQ The value of Q (size of the payload in octets). + * + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_ccm_nist_format_ctr_and_iv(acobject, act, acad, acq, acN, acQ)\ + { \ + uint64_t Q = acQ; \ + uint8_t bflag = ((acad)?0x40:0) | ((((act)-2)/2)<<3) | ((acq)-1); \ + unsigned i; \ + uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15; \ + (acobject)->auth_info.CCM_ctx_info.block_size_bytes = 16; \ + (acobject)->cipher_ctx_info.block_size_bytes = 16; \ + (acobject)->mode = FSL_ACC_MODE_CCM; \ + (acobject)->flags = FSL_ACCO_NIST_CCM; \ + \ + /* Store away the MAC length (after calculating actual value */ \ + (acobject)->mac_length = (act); \ + /* Set Flag field in Block 0 */ \ + *((acobject)->auth_info.CCM_ctx_info.context) = bflag; \ + /* Set Nonce field in Block 0 */ \ + copy_bytes((acobject)->auth_info.CCM_ctx_info.context+1, acN, \ + 15-(acq)); \ + /* Set Flag field in ctr */ \ + *((acobject)->cipher_ctx_info.context) = (acq)-1; \ + /* Update the Q (payload length) field of Block0 */ \ + (acobject)->q_length = acq; \ + for (i = 0; i < (acq); i++) { \ + *qptr-- = Q & 0xFF; \ + Q >>= 8; \ + } \ + /* Set the Nonce field of the ctr */ \ + copy_bytes((acobject)->cipher_ctx_info.context+1, acN, 15-(acq)); \ + /* Clear the block counter field of the ctr */ \ + memset((acobject)->cipher_ctx_info.context+16-(acq), 0, (acq)+1); \ + } + +/*! + * Update the First Block (IV) & Initial Counter Value per NIST CCM. + * + * This function will set the IV and CTR values per Appendix A of NIST Special + * Publication 800-38C (May 2004). + * + * Note this function assumes that #fsl_shw_ccm_nist_format_ctr_and_iv() has + * previously been called on the @a auth_object. + * + * @param acobject Pointer to object to operate on. + * @param acN The Nonce (packet number or other changing value). Must + * be (15 - @a q_length) octets long. + * @param acQ The value of Q (size of the payload in octets). + * + */ +/* Do we need to stash the +1 value of the CTR somewhere? */ +#define fsl_shw_ccm_nist_update_ctr_and_iv(acobject, acN, acQ) \ + { \ + uint64_t Q = acQ; \ + unsigned i; \ + uint8_t* qptr = (acobject)->auth_info.CCM_ctx_info.context + 15; \ + \ + /* Update the Nonce field field of Block0 */ \ + copy_bytes((acobject)->auth_info.CCM_ctx_info.context+1, acN, \ + 15 - (acobject)->q_length); \ + /* Update the Q (payload length) field of Block0 */ \ + for (i = 0; i < (acobject)->q_length; i++) { \ + *qptr-- = Q & 0xFF; \ + Q >>= 8; \ + } \ + /* Update the Nonce field of the ctr */ \ + copy_bytes((acobject)->cipher_ctx_info.context+1, acN, \ + 15 - (acobject)->q_length); \ + } + +/****************************************************************************** + * Library functions + *****************************************************************************/ +/* REQ-S2LRD-PINTFC-API-GEN-003 */ +extern fsl_shw_pco_t *fsl_shw_get_capabilities(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-004 */ +extern fsl_shw_return_t fsl_shw_register_user(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-005 */ +extern fsl_shw_return_t fsl_shw_deregister_user(fsl_shw_uco_t * user_ctx); + +/* REQ-S2LRD-PINTFC-API-GEN-006 */ +extern fsl_shw_return_t fsl_shw_get_results(fsl_shw_uco_t * user_ctx, + unsigned result_size, + fsl_shw_result_t results[], + unsigned *result_count); + +extern fsl_shw_return_t fsl_shw_establish_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_key_wrap_t establish_type, + const uint8_t * key); + +extern fsl_shw_return_t fsl_shw_extract_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * covered_key); + +extern fsl_shw_return_t fsl_shw_release_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info); + +extern void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx, + uint32_t size, + const uint8_t * UMID, uint32_t permissions); + +extern fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address); + +extern fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx, + void *address, + fsl_shw_partition_status_t * status); + +extern fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx, + void *address, + uint32_t permissions); + +extern fsl_shw_return_t do_scc_engage_partition(fsl_shw_uco_t * user_ctx, + void *address, + const uint8_t * UMID, + uint32_t permissions); + +extern fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx, + uint32_t key_lenth, + uint64_t ownerid, + uint32_t * slot); + +extern fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t * + user_ctx, + uint64_t ownerid, + uint32_t slot); + +extern fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + const uint8_t * key, + uint32_t key_length); + +extern fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * key); + +extern fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t * + user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t * black_data); + +extern fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t * + user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * + black_data); + +extern fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode); + +extern fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode); + +extern fsl_shw_return_t +system_keystore_get_slot_info(uint64_t owner_id, uint32_t slot, + uint32_t * address, uint32_t * slot_size_bytes); + +/* REQ-S2LRD-PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +extern fsl_shw_return_t fsl_shw_symmetric_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * pt, + uint8_t * ct); + +/* PINTFC-API-BASIC-SYM-002 */ +/* PINTFC-API-BASIC-SYM-ARC4-001 */ +/* PINTFC-API-BASIC-SYM-ARC4-002 */ +extern fsl_shw_return_t fsl_shw_symmetric_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_scco_t * sym_ctx, + uint32_t length, + const uint8_t * ct, + uint8_t * pt); + +/* REQ-S2LRD-PINTFC-API-BASIC-HASH-005 */ +extern fsl_shw_return_t fsl_shw_hash(fsl_shw_uco_t * user_ctx, + fsl_shw_hco_t * hash_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len); + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-001 */ +extern fsl_shw_return_t fsl_shw_hmac_precompute(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx); + +/* REQ-S2LRD-PINTFC-API-BASIC-HMAC-002 */ +extern fsl_shw_return_t fsl_shw_hmac(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + fsl_shw_hmco_t * hmac_ctx, + const uint8_t * msg, + uint32_t length, + uint8_t * result, uint32_t result_len); + +/* REQ-S2LRD-PINTFC-API-BASIC-RNG-002 */ +extern fsl_shw_return_t fsl_shw_get_random(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data); + +extern fsl_shw_return_t fsl_shw_add_entropy(fsl_shw_uco_t * user_ctx, + uint32_t length, uint8_t * data); + +extern fsl_shw_return_t fsl_shw_gen_encrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * payload, + uint8_t * ct, uint8_t * auth_value); + +extern fsl_shw_return_t fsl_shw_auth_decrypt(fsl_shw_uco_t * user_ctx, + fsl_shw_acco_t * auth_ctx, + fsl_shw_sko_t * cipher_key_info, + fsl_shw_sko_t * auth_key_info, + uint32_t auth_data_length, + const uint8_t * auth_data, + uint32_t payload_length, + const uint8_t * ct, + const uint8_t * auth_value, + uint8_t * payload); + +extern fsl_shw_return_t fsl_shw_read_key(fsl_shw_uco_t * user_ctx, + fsl_shw_sko_t * key_info, + uint8_t * key); + +static inline fsl_shw_return_t fsl_shw_gen_random_pf_key(fsl_shw_uco_t * + user_ctx) +{ + (void)user_ctx; + + return FSL_RETURN_NO_RESOURCE_S; +} + +static inline fsl_shw_return_t fsl_shw_read_tamper_event(fsl_shw_uco_t * + user_ctx, + fsl_shw_tamper_t * + tamperp, + uint64_t * timestampp) +{ + (void)user_ctx; + (void)tamperp; + (void)timestampp; + + return FSL_RETURN_NO_RESOURCE_S; +} + +fsl_shw_return_t sah_Append_Desc(const sah_Mem_Util * mu, + sah_Head_Desc ** desc_head, + const uint32_t header, + sah_Link * link1, sah_Link * link2); + +/* Utility Function leftover from sahara1 API */ +void sah_Descriptor_Chain_Destroy(const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/* Utility Function leftover from sahara1 API */ +fsl_shw_return_t sah_Descriptor_Chain_Execute(sah_Head_Desc * desc_chain, + fsl_shw_uco_t * user_ctx); + +fsl_shw_return_t sah_Append_Link(const sah_Mem_Util * mu, + sah_Link * link, + uint8_t * p, + const size_t length, + const sah_Link_Flags flags); + +fsl_shw_return_t sah_Create_Link(const sah_Mem_Util * mu, + sah_Link ** link, + uint8_t * p, + const size_t length, + const sah_Link_Flags flags); + +fsl_shw_return_t sah_Create_Key_Link(const sah_Mem_Util * mu, + sah_Link ** link, + fsl_shw_sko_t * key_info); + +void sah_Destroy_Link(const sah_Mem_Util * mu, sah_Link * link); + +void sah_Postprocess_Results(fsl_shw_uco_t * user_ctx, + sah_results * result_info); + +#endif /* SAHARA2_API_H */ diff --git a/drivers/mxc/security/sahara2/include/sahara2_kernel.h b/drivers/mxc/security/sahara2/include/sahara2_kernel.h new file mode 100644 index 000000000000..bd2fae8e684a --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sahara2_kernel.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#define DRIVER_NAME sahara2 + +#define SAHARA_MAJOR_NODE 78 + +#include "portable_os.h" + +#include "platform_abstractions.h" + +/* Forward-declare prototypes using signature macros */ + +OS_DEV_ISR_DCL(sahara2_isr); + +OS_DEV_INIT_DCL(sahara2_init); + +OS_DEV_SHUTDOWN_DCL(sahara2_shutdown); + +OS_DEV_OPEN_DCL(sahara2_open); + +OS_DEV_CLOSE_DCL(sahara2_release); + +OS_DEV_IOCTL_DCL(sahara2_ioctl); + +struct sahara2_kernel_user { + void *command_ring[32]; +}; + +struct sahara2_sym_arg { + char *key; + unsigned key_len; +}; + +/*! These need to be added to Linux / OS abstractions */ +/* +module_init(OS_DEV_INIT_REF(sahara2_init)); +module_cleanup(OS_DEV_SHUTDOWN_REF(sahara2_shutdown)); +*/ diff --git a/drivers/mxc/security/sahara2/include/sf_util.h b/drivers/mxc/security/sahara2/include/sf_util.h new file mode 100644 index 000000000000..f64c3f7c393c --- /dev/null +++ b/drivers/mxc/security/sahara2/include/sf_util.h @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sf_util.h +* +* @brief Header for Sahara Descriptor-chain building Functions +*/ +#ifndef SF_UTIL_H +#define SF_UTIL_H + +#include +#include + +/*! Header value for Sahara Descriptor 1 */ +#define SAH_HDR_SKHA_SET_MODE_IV_KEY 0x10880000 +/*! Header value for Sahara Descriptor 2 */ +#define SAH_HDR_SKHA_SET_MODE_ENC_DEC 0x108D0000 +/*! Header value for Sahara Descriptor 4 */ +#define SAH_HDR_SKHA_ENC_DEC 0x90850000 +/*! Header value for Sahara Descriptor 5 */ +#define SAH_HDR_SKHA_READ_CONTEXT_IV 0x10820000 +/*! Header value for Sahara Descriptor 6 */ +#define SAH_HDR_MDHA_SET_MODE_MD_KEY 0x20880000 +/*! Header value for Sahara Descriptor 8 */ +#define SAH_HDR_MDHA_SET_MODE_HASH 0x208D0000 +/*! Header value for Sahara Descriptor 10 */ +#define SAH_HDR_MDHA_HASH 0xA0850000 +/*! Header value for Sahara Descriptor 11 */ +#define SAH_HDR_MDHA_STORE_DIGEST 0x20820000 +/*! Header value for Sahara Descriptor 18 */ +#define SAH_HDR_RNG_GENERATE 0x308C0000 +/*! Header value for Sahara Descriptor 19 */ +#define SAH_HDR_PKHA_LD_N_E 0xC0800000 +/*! Header value for Sahara Descriptor 20 */ +#define SAH_HDR_PKHA_LD_A_EX_ST_B 0x408D0000 +/*! Header value for Sahara Descriptor 21 */ +#define SAH_HDR_PKHA_LD_N_EX_ST_B 0x408E0000 +/*! Header value for Sahara Descriptor 22 */ +#define SAH_HDR_PKHA_LD_A_B 0xC0830000 +/*! Header value for Sahara Descriptor 23 */ +#define SAH_HDR_PKHA_LD_A0_A1 0x40840000 +/*! Header value for Sahara Descriptor 24 */ +#define SAH_HDR_PKHA_LD_A2_A3 0xC0850000 +/*! Header value for Sahara Descriptor 25 */ +#define SAH_HDR_PKHA_LD_B0_B1 0xC0860000 +/*! Header value for Sahara Descriptor 26 */ +#define SAH_HDR_PKHA_LD_B2_B3 0x40870000 +/*! Header value for Sahara Descriptor 27 */ +#define SAH_HDR_PKHA_ST_A_B 0x40820000 +/*! Header value for Sahara Descriptor 28 */ +#define SAH_HDR_PKHA_ST_A0_A1 0x40880000 +/*! Header value for Sahara Descriptor 29 */ +#define SAH_HDR_PKHA_ST_A2_A3 0xC0890000 +/*! Header value for Sahara Descriptor 30 */ +#define SAH_HDR_PKHA_ST_B0_B1 0xC08A0000 +/*! Header value for Sahara Descriptor 31 */ +#define SAH_HDR_PKHA_ST_B2_B3 0x408B0000 +/*! Header value for Sahara Descriptor 32 */ +#define SAH_HDR_PKHA_EX_ST_B1 0xC08C0000 +/*! Header value for Sahara Descriptor 33 */ +#define SAH_HDR_ARC4_SET_MODE_SBOX 0x90890000 +/*! Header value for Sahara Descriptor 34 */ +#define SAH_HDR_ARC4_READ_SBOX 0x90860000 +/*! Header value for Sahara Descriptor 35 */ +#define SAH_HDR_ARC4_SET_MODE_KEY 0x90830000 +/*! Header value for Sahara Descriptor 36 */ +#define SAH_HDR_PKHA_LD_A3_B0 0x40810000 +/*! Header value for Sahara Descriptor 37 */ +#define SAH_HDR_PKHA_ST_B1_B2 0xC08F0000 +/*! Header value for Sahara Descriptor 38 */ +#define SAH_HDR_SKHA_CBC_ICV 0x10840000 +/*! Header value for Sahara Descriptor 39 */ +#define SAH_HDR_MDHA_ICV_CHECK 0xA08A0000 + +/*! Header bit indicating "Link-List optimization" */ +#define SAH_HDR_LLO 0x01000000 + +#define SAH_SF_DCLS \ + fsl_shw_return_t ret; \ + unsigned sf_executed = 0; \ + sah_Head_Desc* desc_chain = NULL; \ + uint32_t header + +#define SAH_SF_USER_CHECK() \ +do { \ + ret = sah_validate_uco(user_ctx); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} while (0) + +#define SAH_SF_EXECUTE() \ +do { \ + sf_executed = 1; \ + ret = sah_Descriptor_Chain_Execute(desc_chain, user_ctx); \ +} while (0) + +#define SAH_SF_DESC_CLEAN() \ +do { \ + if (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE)) { \ + sah_Descriptor_Chain_Destroy(user_ctx->mem_util, &desc_chain); \ + } \ + (void) header; \ +} while (0) + +/*! Add Descriptor with two inputs */ +#define DESC_IN_IN(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_two_in_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with two vectors */ +#define DESC_D_D(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_two_d_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with input and a key */ +#define DESC_IN_KEY(hdr, len1, ptr1, key2) \ +{ \ + ret = sah_add_in_key_desc(hdr, ptr1, len1, key2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with input and an output */ +#define DESC_IN_OUT(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_in_out_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with input and a key output */ +#define DESC_IN_KEYOUT(hdr, len1, ptr1, key2) \ +{ \ + ret = sah_add_in_keyout_desc(hdr, ptr1, len1, key2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with a key and an output */ +#define DESC_KEY_OUT(hdr, key1, len2, ptr2) \ +{ \ + ret = sah_add_key_out_desc(hdr, key1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with two outputs */ +#define DESC_OUT_OUT(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_two_out_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +/*! Add Descriptor with output then input pointers */ +#define DESC_OUT_IN(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_out_in_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} + +#ifdef SAH_SF_DEBUG +/*! Add Descriptor with two outputs */ +#define DBG_DESC(hdr, len1, ptr1, len2, ptr2) \ +{ \ + ret = sah_add_two_out_desc(hdr, ptr1, len1, ptr2, len2, \ + user_ctx->mem_util, &desc_chain); \ + if (ret != FSL_RETURN_OK_S) { \ + goto out; \ + } \ +} +#else +#define DBG_DESC(hdr, len1, ptr1, len2, ptr2) +#endif + +#ifdef __KERNEL__ +#define DESC_DBG_ON ({console_loglevel = 8;}) +#define DESC_DBG_OFF ({console_loglevel = 7;}) +#else +#define DESC_DBG_ON system("echo 8 > /proc/sys/kernel/printk") +#define DESC_DBG_OFF system("echo 7 > /proc/sys/kernel/printk") +#endif + +#define DESC_TEMP_ALLOC(size) \ +({ \ + uint8_t* ptr; \ + ptr = user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref, \ + size); \ + if (ptr == NULL) { \ + ret = FSL_RETURN_NO_RESOURCE_S; \ + goto out; \ + } \ + \ + ptr; \ +}) + +#define DESC_TEMP_FREE(ptr) \ +({ \ + if ((ptr != NULL) && \ + (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE))) { \ + user_ctx->mem_util-> \ + mu_free(user_ctx->mem_util->mu_ref, ptr); \ + ptr = NULL; \ + } \ +}) + +/* Temporary implementation. This needs to be in internal/secure RAM */ +#define DESC_TEMP_SECURE_ALLOC(size) \ +({ \ + uint8_t* ptr; \ + ptr = user_ctx->mem_util->mu_malloc(user_ctx->mem_util->mu_ref, \ + size); \ + if (ptr == NULL) { \ + ret = FSL_RETURN_NO_RESOURCE_S; \ + goto out; \ + } \ + \ + ptr; \ +}) + +#define DESC_TEMP_SECURE_FREE(ptr, size) \ +({ \ + if ((ptr != NULL) && \ + (!sf_executed || (user_ctx->flags & FSL_UCO_BLOCKING_MODE))) { \ + user_ctx->mem_util->mu_memset(user_ctx->mem_util->mu_ref, \ + ptr, 0, size); \ + \ + user_ctx->mem_util-> \ + mu_free(user_ctx->mem_util->mu_ref, ptr); \ + ptr = NULL; \ + } \ +}) + +extern const uint32_t sah_insert_mdha_algorithm[]; + +/*! @defgroup mdhaflags MDHA Mode Register Values + * + * These are bit fields and combinations of bit fields for setting the Mode + * Register portion of a Sahara Descriptor Header field. + * + * The parity bit has been set to ensure that these values have even parity, + * therefore using an Exclusive-OR operation against an existing header will + * preserve its parity. + * + * @addtogroup mdhaflags + @{ + */ +#define sah_insert_mdha_icv_check 0x80001000 +#define sah_insert_mdha_ssl 0x80000400 +#define sah_insert_mdha_mac_full 0x80000200 +#define sah_insert_mdha_opad 0x80000080 +#define sah_insert_mdha_ipad 0x80000040 +#define sah_insert_mdha_init 0x80000020 +#define sah_insert_mdha_hmac 0x80000008 +#define sah_insert_mdha_pdata 0x80000004 +#define sah_insert_mdha_algorithm_sha224 0x00000003 +#define sah_insert_mdha_algorithm_sha256 0x80000002 +#define sah_insert_mdha_algorithm_md5 0x80000001 +#define sah_insert_mdha_algorithm_sha1 0x00000000 +/*! @} */ + +extern const uint32_t sah_insert_skha_algorithm[]; +extern const uint32_t sah_insert_skha_mode[]; +extern const uint32_t sah_insert_skha_modulus[]; + +/*! @defgroup skhaflags SKHA Mode Register Values + * + * These are bit fields and combinations of bit fields for setting the Mode + * Register portion of a Sahara Descriptor Header field. + * + * The parity bit has been set to ensure that these values have even parity, + * therefore using an Exclusive-OR operation against an existing header will + * preserve its parity. + * + * @addtogroup skhaflags + @{ + */ +/*! */ +#define sah_insert_skha_modulus_128 0x00001e00 +#define sah_insert_skha_no_key_parity 0x80000100 +#define sah_insert_skha_ctr_last_block 0x80000020 +#define sah_insert_skha_suppress_cbc 0x80000020 +#define sah_insert_skha_no_permute 0x80000020 +#define sah_insert_skha_algorithm_arc4 0x00000003 +#define sah_insert_skha_algorithm_tdes 0x80000002 +#define sah_insert_skha_algorithm_des 0x80000001 +#define sah_insert_skha_algorithm_aes 0x00000000 +#define sah_insert_skha_aux0 0x80000020 +#define sah_insert_skha_mode_ctr 0x00000018 +#define sah_insert_skha_mode_ccm 0x80000010 +#define sah_insert_skha_mode_cbc 0x80000008 +#define sah_insert_skha_mode_ecb 0x00000000 +#define sah_insert_skha_encrypt 0x80000004 +#define sah_insert_skha_decrypt 0x00000000 +/*! @} */ + +/*! @defgroup rngflags RNG Mode Register Values + * + */ +/*! */ +#define sah_insert_rng_gen_seed 0x80000001 + +/*! @} */ + +/*! @defgroup pkhaflags PKHA Mode Register Values + * + */ +/*! */ +#define sah_insert_pkha_soft_err_false 0x80000200 +#define sah_insert_pkha_soft_err_true 0x80000100 + +#define sah_insert_pkha_rtn_clr_mem 0x80000001 +#define sah_insert_pkha_rtn_clr_eram 0x80000002 +#define sah_insert_pkha_rtn_mod_exp 0x00000003 +#define sah_insert_pkha_rtn_mod_r2modn 0x80000004 +#define sah_insert_pkha_rtn_mod_rrmodp 0x00000005 +#define sah_insert_pkha_rtn_ec_fp_aff_ptmul 0x00000006 +#define sah_insert_pkha_rtn_ec_f2m_aff_ptmul 0x80000007 +#define sah_insert_pkha_rtn_ec_fp_proj_ptmul 0x80000008 +#define sah_insert_pkha_rtn_ec_f2m_proj_ptmul 0x00000009 +#define sah_insert_pkha_rtn_ec_fp_add 0x0000000A +#define sah_insert_pkha_rtn_ec_fp_double 0x8000000B +#define sah_insert_pkha_rtn_ec_f2m_add 0x0000000C +#define sah_insert_pkha_rtn_ec_f2m_double 0x8000000D +#define sah_insert_pkha_rtn_f2m_r2modn 0x8000000E +#define sah_insert_pkha_rtn_f2m_inv 0x0000000F +#define sah_insert_pkha_rtn_mod_inv 0x80000010 +#define sah_insert_pkha_rtn_rsa_sstep 0x00000011 +#define sah_insert_pkha_rtn_mod_emodn 0x00000012 +#define sah_insert_pkha_rtn_f2m_emodn 0x80000013 +#define sah_insert_pkha_rtn_ec_fp_ptmul 0x00000014 +#define sah_insert_pkha_rtn_ec_f2m_ptmul 0x80000015 +#define sah_insert_pkha_rtn_f2m_gcd 0x80000016 +#define sah_insert_pkha_rtn_mod_gcd 0x00000017 +#define sah_insert_pkha_rtn_f2m_dbl_aff 0x00000018 +#define sah_insert_pkha_rtn_fp_dbl_aff 0x80000019 +#define sah_insert_pkha_rtn_f2m_add_aff 0x8000001A +#define sah_insert_pkha_rtn_fp_add_aff 0x0000001B +#define sah_insert_pkha_rtn_f2m_exp 0x8000001C +#define sah_insert_pkha_rtn_mod_exp_teq 0x0000001D +#define sah_insert_pkha_rtn_rsa_sstep_teq 0x0000001E +#define sah_insert_pkha_rtn_f2m_multn 0x8000001F +#define sah_insert_pkha_rtn_mod_multn 0x80000020 +#define sah_insert_pkha_rtn_mod_add 0x00000021 +#define sah_insert_pkha_rtn_mod_sub 0x00000022 +#define sah_insert_pkha_rtn_mod_mult1_mont 0x80000023 +#define sah_insert_pkha_rtn_mod_mult2_deconv 0x00000024 +#define sah_insert_pkha_rtn_f2m_add 0x80000025 +#define sah_insert_pkha_rtn_f2m_mult1_mont 0x80000026 +#define sah_insert_pkha_rtn_f2m_mult2_deconv 0x00000027 +#define sah_insert_pkha_rtn_miller_rabin 0x00000028 +#define sah_insert_pkha_rtn_mod_amodn 0x00000029 +#define sah_insert_pkha_rtn_f2m_amodn 0x8000002A +/*! @} */ + +/*! Add a descriptor with two input pointers */ +fsl_shw_return_t sah_add_two_in_desc(uint32_t header, + const uint8_t * in1, + uint32_t in1_length, + const uint8_t * in2, + uint32_t in2_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with two 'data' pointers */ +fsl_shw_return_t sah_add_two_d_desc(uint32_t header, + const uint8_t * in1, + uint32_t in1_length, + const uint8_t * in2, + uint32_t in2_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with an input and key pointer */ +fsl_shw_return_t sah_add_in_key_desc(uint32_t header, + const uint8_t * in1, + uint32_t in1_length, + fsl_shw_sko_t * key_info, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with two key pointers */ +fsl_shw_return_t sah_add_key_key_desc(uint32_t header, + fsl_shw_sko_t * key_info1, + fsl_shw_sko_t * key_info2, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with two output pointers */ +fsl_shw_return_t sah_add_two_out_desc(uint32_t header, + uint8_t * out1, + uint32_t out1_length, + uint8_t * out2, + uint32_t out2_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with an input and output pointer */ +fsl_shw_return_t sah_add_in_out_desc(uint32_t header, + const uint8_t * in, uint32_t in_length, + uint8_t * out, uint32_t out_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with an input and key output pointer */ +fsl_shw_return_t sah_add_in_keyout_desc(uint32_t header, + const uint8_t * in, uint32_t in_length, + fsl_shw_sko_t * key_info, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with a key and an output pointer */ +fsl_shw_return_t sah_add_key_out_desc(uint32_t header, + const fsl_shw_sko_t * key_info, + uint8_t * out, uint32_t out_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Add a descriptor with an output and input pointer */ +fsl_shw_return_t sah_add_out_in_desc(uint32_t header, + uint8_t * out, uint32_t out_length, + const uint8_t * in, uint32_t in_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain); + +/*! Verify that supplied User Context Object is valid */ +fsl_shw_return_t sah_validate_uco(fsl_shw_uco_t * uco); + +#endif /* SF_UTIL_H */ + +/* End of sf_util.h */ diff --git a/drivers/mxc/security/sahara2/km_adaptor.c b/drivers/mxc/security/sahara2/km_adaptor.c new file mode 100644 index 000000000000..f2b7d564256d --- /dev/null +++ b/drivers/mxc/security/sahara2/km_adaptor.c @@ -0,0 +1,849 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file km_adaptor.c +* +* @brief The Adaptor component provides an interface to the +* driver for a kernel user. +*/ + +#include +#include +#include +#include +#include +#ifdef FSL_HAVE_SCC +#include +#elif defined (FSL_HAVE_SCC2) +#include +#endif + + +EXPORT_SYMBOL(adaptor_Exec_Descriptor_Chain); +EXPORT_SYMBOL(sah_register); +EXPORT_SYMBOL(sah_deregister); +EXPORT_SYMBOL(sah_get_results); +EXPORT_SYMBOL(fsl_shw_smalloc); +EXPORT_SYMBOL(fsl_shw_sfree); +EXPORT_SYMBOL(fsl_shw_sstatus); +EXPORT_SYMBOL(fsl_shw_diminish_perms); +EXPORT_SYMBOL(do_scc_encrypt_region); +EXPORT_SYMBOL(do_scc_decrypt_region); +EXPORT_SYMBOL(do_system_keystore_slot_alloc); +EXPORT_SYMBOL(do_system_keystore_slot_dealloc); +EXPORT_SYMBOL(do_system_keystore_slot_load); +EXPORT_SYMBOL(do_system_keystore_slot_read); +EXPORT_SYMBOL(do_system_keystore_slot_encrypt); +EXPORT_SYMBOL(do_system_keystore_slot_decrypt); + + +#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DIAG_ADAPTOR) +#include +#endif + +#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DIAG_ADAPTOR) +#define MAX_DUMP 16 + +#define DIAG_MSG_SIZE 300 +static char Diag_msg[DIAG_MSG_SIZE]; +#endif + +/* This is the wait queue to this mode of driver */ +DECLARE_WAIT_QUEUE_HEAD(Wait_queue_km); + +/*! This matches Sahara2 capabilities... */ +fsl_shw_pco_t sahara2_capabilities = { + 1, 3, /* api version number - major & minor */ + 1, 6, /* driver version number - major & minor */ + { + FSL_KEY_ALG_AES, + FSL_KEY_ALG_DES, + FSL_KEY_ALG_TDES, + FSL_KEY_ALG_ARC4}, + { + FSL_SYM_MODE_STREAM, + FSL_SYM_MODE_ECB, + FSL_SYM_MODE_CBC, + FSL_SYM_MODE_CTR}, + { + FSL_HASH_ALG_MD5, + FSL_HASH_ALG_SHA1, + FSL_HASH_ALG_SHA224, + FSL_HASH_ALG_SHA256}, + /* + * The following table must be set to handle all values of key algorithm + * and sym mode, and be in the correct order.. + */ + { /* Stream, ECB, CBC, CTR */ + {0, 0, 0, 0}, /* HMAC */ + {0, 1, 1, 1}, /* AES */ + {0, 1, 1, 0}, /* DES */ + {0, 1, 1, 0}, /* 3DES */ + {1, 0, 0, 0} /* ARC4 */ + }, + 0, 0, + 0, 0, 0, + {{0, 0}} +}; + +#ifdef DIAG_ADAPTOR +void km_Dump_Chain(const sah_Desc * chain); + +void km_Dump_Region(const char *prefix, const unsigned char *data, + unsigned length); + +static void km_Dump_Link(const char *prefix, const sah_Link * link); + +void km_Dump_Words(const char *prefix, const unsigned *data, unsigned length); +#endif + +/**** Memory routines ****/ + +static void *my_malloc(void *ref, size_t n) +{ + register void *mem; + +#ifndef DIAG_MEM_ERRORS + mem = os_alloc_memory(n, GFP_KERNEL); + +#else + { + uint32_t rand; + /* are we feeling lucky ? */ + os_get_random_bytes(&rand, sizeof(rand)); + if ((rand % DIAG_MEM_CONST) == 0) { + mem = 0; + } else { + mem = os_alloc_memory(n, GFP_ATOMIC); + } + } +#endif /* DIAG_MEM_ERRORS */ + +#ifdef DIAG_MEM + sprintf(Diag_msg, "API kmalloc: %p for %d\n", mem, n); + LOG_KDIAG(Diag_msg); +#endif + ref = 0; /* unused param warning */ + return mem; +} + +static sah_Head_Desc *my_alloc_head_desc(void *ref) +{ + register sah_Head_Desc *ptr; + +#ifndef DIAG_MEM_ERRORS + ptr = sah_Alloc_Head_Descriptor(); + +#else + { + uint32_t rand; + /* are we feeling lucky ? */ + os_get_random_bytes(&rand, sizeof(rand)); + if ((rand % DIAG_MEM_CONST) == 0) { + ptr = 0; + } else { + ptr = sah_Alloc_Head_Descriptor(); + } + } +#endif + ref = 0; + return ptr; +} + +static sah_Desc *my_alloc_desc(void *ref) +{ + register sah_Desc *ptr; + +#ifndef DIAG_MEM_ERRORS + ptr = sah_Alloc_Descriptor(); + +#else + { + uint32_t rand; + /* are we feeling lucky ? */ + os_get_random_bytes(&rand, sizeof(rand)); + if ((rand % DIAG_MEM_CONST) == 0) { + ptr = 0; + } else { + ptr = sah_Alloc_Descriptor(); + } + } +#endif + ref = 0; + return ptr; +} + +static sah_Link *my_alloc_link(void *ref) +{ + register sah_Link *ptr; + +#ifndef DIAG_MEM_ERRORS + ptr = sah_Alloc_Link(); + +#else + { + uint32_t rand; + /* are we feeling lucky ? */ + os_get_random_bytes(&rand, sizeof(rand)); + if ((rand % DIAG_MEM_CONST) == 0) { + ptr = 0; + } else { + ptr = sah_Alloc_Link(); + } + } +#endif + ref = 0; + return ptr; +} + +static void my_free(void *ref, void *ptr) +{ + ref = 0; /* unused param warning */ +#ifdef DIAG_MEM + sprintf(Diag_msg, "API kfree: %p\n", ptr); + LOG_KDIAG(Diag_msg); +#endif + os_free_memory(ptr); +} + +static void my_free_head_desc(void *ref, sah_Head_Desc * ptr) +{ + sah_Free_Head_Descriptor(ptr); +} + +static void my_free_desc(void *ref, sah_Desc * ptr) +{ + sah_Free_Descriptor(ptr); +} + +static void my_free_link(void *ref, sah_Link * ptr) +{ + sah_Free_Link(ptr); +} + +static void *my_memcpy(void *ref, void *dest, const void *src, size_t n) +{ + ref = 0; /* unused param warning */ + return memcpy(dest, src, n); +} + +static void *my_memset(void *ref, void *ptr, int ch, size_t n) +{ + ref = 0; /* unused param warning */ + return memset(ptr, ch, n); +} + +/*! Standard memory manipulation routines for kernel API. */ +static sah_Mem_Util std_kernelmode_mem_util = { + .mu_ref = 0, + .mu_malloc = my_malloc, + .mu_alloc_head_desc = my_alloc_head_desc, + .mu_alloc_desc = my_alloc_desc, + .mu_alloc_link = my_alloc_link, + .mu_free = my_free, + .mu_free_head_desc = my_free_head_desc, + .mu_free_desc = my_free_desc, + .mu_free_link = my_free_link, + .mu_memcpy = my_memcpy, + .mu_memset = my_memset +}; + +fsl_shw_return_t get_capabilities(fsl_shw_uco_t * user_ctx, + fsl_shw_pco_t * capabilities) +{ + scc_config_t *scc_capabilities; + + /* Fill in the Sahara2 capabilities. */ + memcpy(capabilities, &sahara2_capabilities, sizeof(fsl_shw_pco_t)); + + /* Fill in the SCC portion of the capabilities object */ + scc_capabilities = scc_get_configuration(); + capabilities->scc_driver_major = scc_capabilities->driver_major_version; + capabilities->scc_driver_minor = scc_capabilities->driver_minor_version; + capabilities->scm_version = scc_capabilities->scm_version; + capabilities->smn_version = scc_capabilities->smn_version; + capabilities->block_size_bytes = scc_capabilities->block_size_bytes; + +#ifdef FSL_HAVE_SCC + capabilities->scc_info.black_ram_size_blocks = + scc_capabilities->black_ram_size_blocks; + capabilities->scc_info.red_ram_size_blocks = + scc_capabilities->red_ram_size_blocks; +#elif defined(FSL_HAVE_SCC2) + capabilities->scc2_info.partition_size_bytes = + scc_capabilities->partition_size_bytes; + capabilities->scc2_info.partition_count = + scc_capabilities->partition_count; +#endif + + return FSL_RETURN_OK_S; +} + +/*! + * Sends a request to register this user + * + * @brief Sends a request to register this user + * + * @param[in,out] user_ctx part of the structure contains input parameters and + * part is filled in by the driver + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_register(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_return_t status; + + /* this field is used in user mode to indicate a file open has occured. + * it is used here, in kernel mode, to indicate that the uco is registered + */ + user_ctx->sahara_openfd = 0; /* set to 'registered' */ + user_ctx->mem_util = &std_kernelmode_mem_util; + + /* check that uco is valid */ + status = sah_validate_uco(user_ctx); + + /* If life is good, register this user */ + if (status == FSL_RETURN_OK_S) { + status = sah_handle_registration(user_ctx); + } + + if (status != FSL_RETURN_OK_S) { + user_ctx->sahara_openfd = -1; /* set to 'not registered' */ + } + + return status; +} + +/*! + * Sends a request to deregister this user + * + * @brief Sends a request to deregister this user + * + * @param[in,out] user_ctx Info on user being deregistered. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_deregister(fsl_shw_uco_t * user_ctx) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + + if (user_ctx->sahara_openfd == 0) { + status = sah_handle_deregistration(user_ctx); + user_ctx->sahara_openfd = -1; /* set to 'no registered */ + } + + return status; +} + +/*! + * Sends a request to get results for this user + * + * @brief Sends a request to get results for this user + * + * @param[in,out] arg Pointer to structure to collect results + * @param uco User's context + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_get_results(sah_results * arg, fsl_shw_uco_t * uco) +{ + fsl_shw_return_t code = sah_get_results_from_pool(uco, arg); + + if ((code == FSL_RETURN_OK_S) && (arg->actual != 0)) { + sah_Postprocess_Results(uco, arg); + } + + return code; +} + +/*! + * This function writes the Descriptor Chain to the kernel driver. + * + * @brief Writes the Descriptor Chain to the kernel driver. + * + * @param dar A pointer to a Descriptor Chain of type sah_Head_Desc + * @param uco The user context object + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t adaptor_Exec_Descriptor_Chain(sah_Head_Desc * dar, + fsl_shw_uco_t * uco) +{ + sah_Head_Desc *kernel_space_desc = NULL; + fsl_shw_return_t code = FSL_RETURN_OK_S; + int os_error_code = 0; + unsigned blocking_mode = dar->uco_flags & FSL_UCO_BLOCKING_MODE; + +#ifdef DIAG_ADAPTOR + km_Dump_Chain(&dar->desc); +#endif + + dar->user_info = uco; + dar->user_desc = dar; + + /* This code has been shamelessly copied from sah_driver_interface.c */ + /* It needs to be moved somewhere common ... */ + kernel_space_desc = sah_Physicalise_Descriptors(dar); + + if (kernel_space_desc == NULL) { + /* We may have failed due to a -EFAULT as well, but we will return + * -ENOMEM since either way it is a memory related failure. */ + code = FSL_RETURN_NO_RESOURCE_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Physicalise_Descriptors() failed\n"); +#endif + } else { + if (blocking_mode) { +#ifdef SAHARA_POLL_MODE + os_error_code = sah_Handle_Poll(dar); +#else + os_error_code = sah_blocking_mode(dar); +#endif + if (os_error_code != 0) { + code = FSL_RETURN_ERROR_S; + } else { /* status of actual operation */ + code = dar->result; + } + } else { +#ifdef SAHARA_POLL_MODE + sah_Handle_Poll(dar); +#else + /* just put someting in the DAR */ + sah_Queue_Manager_Append_Entry(dar); +#endif /* SAHARA_POLL_MODE */ + } + } + + return code; +} + + +/* System keystore context, defined in sah_driver_interface.c */ +extern fsl_shw_kso_t system_keystore; + +fsl_shw_return_t do_system_keystore_slot_alloc(fsl_shw_uco_t * user_ctx, + uint32_t key_length, + uint64_t ownerid, + uint32_t * slot) +{ + (void)user_ctx; + return keystore_slot_alloc(&system_keystore, key_length, ownerid, slot); +} + +fsl_shw_return_t do_system_keystore_slot_dealloc(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot) +{ + (void)user_ctx; + return keystore_slot_dealloc(&system_keystore, ownerid, slot); +} + +fsl_shw_return_t do_system_keystore_slot_load(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + const uint8_t * key, + uint32_t key_length) +{ + (void)user_ctx; + return keystore_slot_load(&system_keystore, ownerid, slot, + (void *)key, key_length); +} + +fsl_shw_return_t do_system_keystore_slot_read(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * key) +{ + (void)user_ctx; + return keystore_slot_read(&system_keystore, ownerid, slot, + key_length, (void *)key); +} + +fsl_shw_return_t do_system_keystore_slot_encrypt(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + uint8_t * black_data) +{ + (void)user_ctx; + return keystore_slot_encrypt(NULL, &system_keystore, ownerid, + slot, key_length, black_data); +} + +fsl_shw_return_t do_system_keystore_slot_decrypt(fsl_shw_uco_t * user_ctx, + uint64_t ownerid, + uint32_t slot, + uint32_t key_length, + const uint8_t * black_data) +{ + (void)user_ctx; + return keystore_slot_decrypt(NULL, &system_keystore, ownerid, + slot, key_length, black_data); +} + +void *fsl_shw_smalloc(fsl_shw_uco_t * user_ctx, + uint32_t size, const uint8_t * UMID, uint32_t permissions) +{ +#ifdef FSL_HAVE_SCC2 + int part_no; + void *part_base; + uint32_t part_phys; + scc_config_t *scc_configuration; + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (size != scc_configuration->partition_size_bytes) { + return NULL; + } + + /* Attempt to grab a partition. */ + if (scc_allocate_partition(0, &part_no, &part_base, &part_phys) + != SCC_RET_OK) { + return NULL; + } + printk(KERN_ALERT "In fsh_shw_smalloc (km): partition_base:%p " + "partition_base_phys: %p\n", part_base, (void *)part_phys); + + /* these bits should be in a separate function */ + printk(KERN_ALERT "writing UMID and MAP to secure the partition\n"); + + scc_engage_partition(part_base, UMID, permissions); + + (void)user_ctx; /* unused param warning */ + + return part_base; +#else /* FSL_HAVE_SCC2 */ + (void)user_ctx; + (void)size; + (void)UMID; + (void)permissions; + return NULL; +#endif /* FSL_HAVE_SCC2 */ + +} + +fsl_shw_return_t fsl_shw_sfree(fsl_shw_uco_t * user_ctx, void *address) +{ + (void)user_ctx; + +#ifdef FSL_HAVE_SCC2 + if (scc_release_partition(address) == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } +#endif + + return FSL_RETURN_ERROR_S; +} + +fsl_shw_return_t fsl_shw_sstatus(fsl_shw_uco_t * user_ctx, + void *address, + fsl_shw_partition_status_t * status) +{ + (void)user_ctx; + +#ifdef FSL_HAVE_SCC2 + *status = scc_partition_status(address); + return FSL_RETURN_OK_S; +#endif + + return FSL_RETURN_ERROR_S; +} + +/* Diminish permissions on some secure memory */ +fsl_shw_return_t fsl_shw_diminish_perms(fsl_shw_uco_t * user_ctx, + void *address, uint32_t permissions) +{ + + (void)user_ctx; /* unused parameter warning */ + +#ifdef FSL_HAVE_SCC2 + if (scc_diminish_permissions(address, permissions) == SCC_RET_OK) { + return FSL_RETURN_OK_S; + } +#endif + return FSL_RETURN_ERROR_S; +} + +/* + * partition_base - physical address of the partition + * offset - offset, in blocks, of the data from the start of the partition + * length - length, in bytes, of the data to be encrypted (multiple of 4) + * black_data - virtual address that the encrypted data should be stored at + * Note that this virtual address must be translatable using the __virt_to_phys + * macro; ie, it can't be a specially mapped address. To do encryption with those + * addresses, use the scc_encrypt_region function directly. This is to make + * this function compatible with the user mode declaration, which does not know + * the physical addresses of the data it is using. + */ +fsl_shw_return_t +do_scc_encrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode) +{ + scc_return_t scc_ret; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + +#ifdef FSL_HAVE_SCC2 + +#ifdef DIAG_ADAPTOR + uint32_t *owner_32 = (uint32_t *) & (owner_id); + + LOG_KDIAG_ARGS + ("partition base: %p, offset: %i, count: %i, black data: %p\n", + partition_base, offset_bytes, byte_count, (void *)black_data); +#endif + (void)user_ctx; + + os_cache_flush_range(black_data, byte_count); + + scc_ret = + scc_encrypt_region((uint32_t) partition_base, offset_bytes, + byte_count, __virt_to_phys(black_data), IV, + cypher_mode); + + if (scc_ret == SCC_RET_OK) { + retval = FSL_RETURN_OK_S; + } else { + retval = FSL_RETURN_ERROR_S; + } + + /* The SCC2 DMA engine should have written to the black ram, so we need to + * invalidate that region of memory. Note that the red ram is not an + * because it is mapped with the cache disabled. + */ + os_cache_inv_range(black_data, byte_count); + +#else + (void)scc_ret; +#endif /* FSL_HAVE_SCC2 */ + + return retval; +} + +/*! + * Call the proper function to decrypt a region of encrypted secure memory + * + * @brief + * + * @param user_ctx User context of the partition owner (NULL in kernel) + * @param partition_base Base address (physical) of the partition + * @param offset_bytes Offset from base address that the decrypted data + * shall be placed + * @param byte_count Length of the message (bytes) + * @param black_data Pointer to where the encrypted data is stored + * @param owner_id + * + * @return status + */ + +fsl_shw_return_t +do_scc_decrypt_region(fsl_shw_uco_t * user_ctx, + void *partition_base, uint32_t offset_bytes, + uint32_t byte_count, const uint8_t * black_data, + uint32_t * IV, fsl_shw_cypher_mode_t cypher_mode) +{ + scc_return_t scc_ret; + fsl_shw_return_t retval = FSL_RETURN_ERROR_S; + +#ifdef FSL_HAVE_SCC2 + +#ifdef DIAG_ADAPTOR + uint32_t *owner_32 = (uint32_t *) & (owner_id); + + LOG_KDIAG_ARGS + ("partition base: %p, offset: %i, count: %i, black data: %p\n", + partition_base, offset_bytes, byte_count, (void *)black_data); +#endif + + (void)user_ctx; + + /* The SCC2 DMA engine will be reading from the black ram, so we need to + * make sure that the data is pushed out of the cache. Note that the red + * ram is not an issue because it is mapped with the cache disabled. + */ + os_cache_flush_range(black_data, byte_count); + + scc_ret = + scc_decrypt_region((uint32_t) partition_base, offset_bytes, + byte_count, + (uint8_t *) __virt_to_phys(black_data), IV, + cypher_mode); + + if (scc_ret == SCC_RET_OK) { + retval = FSL_RETURN_OK_S; + } else { + retval = FSL_RETURN_ERROR_S; + } + +#else + (void)scc_ret; +#endif /* FSL_HAVE_SCC2 */ + + return retval; +} + +#ifdef DIAG_ADAPTOR +/*! + * Dump chain of descriptors to the log. + * + * @brief Dump descriptor chain + * + * @param chain Kernel virtual address of start of chain of descriptors + * + * @return void + */ +void km_Dump_Chain(const sah_Desc * chain) +{ + while (chain != NULL) { + km_Dump_Words("Desc", (unsigned *)chain, + 6 /*sizeof(*chain)/sizeof(unsigned) */ ); + /* place this definition elsewhere */ + if (chain->ptr1) { + if (chain->header & SAH_HDR_LLO) { + km_Dump_Region(" Data1", chain->ptr1, + chain->len1); + } else { + km_Dump_Link(" Link1", chain->ptr1); + } + } + if (chain->ptr2) { + if (chain->header & SAH_HDR_LLO) { + km_Dump_Region(" Data2", chain->ptr2, + chain->len2); + } else { + km_Dump_Link(" Link2", chain->ptr2); + } + } + + chain = chain->next; + } +} + +/*! + * Dump chain of links to the log. + * + * @brief Dump chain of links + * + * @param prefix Text to put in front of dumped data + * @param link Kernel virtual address of start of chain of links + * + * @return void + */ +static void km_Dump_Link(const char *prefix, const sah_Link * link) +{ + while (link != NULL) { + km_Dump_Words(prefix, (unsigned *)link, + 3 /* # words in h/w link */ ); + if (link->flags & SAH_STORED_KEY_INFO) { +#ifdef CAN_DUMP_SCC_DATA + uint32_t len; +#endif + +#ifdef CAN_DUMP_SCC_DATA + { + char buf[50]; + + scc_get_slot_info(link->ownerid, link->slot, (uint32_t *) & link->data, /* RED key address */ + &len); /* key length */ + sprintf(buf, " SCC slot %d: ", link->slot); + km_Dump_Words(buf, + (void *)IO_ADDRESS((uint32_t) + link->data), + link->len / 4); + } +#else + sprintf(Diag_msg, " SCC slot %d", link->slot); + LOG_KDIAG(Diag_msg); +#endif + } else if (link->data != NULL) { + km_Dump_Region(" Data", link->data, link->len); + } + + link = link->next; + } +} + +/*! + * Dump given region of data to the log. + * + * @brief Dump data + * + * @param prefix Text to put in front of dumped data + * @param data Kernel virtual address of start of region to dump + * @param length Amount of data to dump + * + * @return void +*/ +void km_Dump_Region(const char *prefix, const unsigned char *data, + unsigned length) +{ + unsigned count; + char *output; + unsigned data_len; + + sprintf(Diag_msg, "%s (%08X,%u):", prefix, (uint32_t) data, length); + + /* Restrict amount of data to dump */ + if (length > MAX_DUMP) { + data_len = MAX_DUMP; + } else { + data_len = length; + } + + /* We've already printed some text in output buffer, skip over it */ + output = Diag_msg + strlen(Diag_msg); + + for (count = 0; count < data_len; count++) { + if (count % 4 == 0) { + *output++ = ' '; + } + sprintf(output, "%02X", *data++); + output += 2; + } + + LOG_KDIAG(Diag_msg); +} + +/*! + * Dump given wors of data to the log. + * + * @brief Dump data + * + * @param prefix Text to put in front of dumped data + * @param data Kernel virtual address of start of region to dump + * @param word_count Amount of data to dump + * + * @return void +*/ +void km_Dump_Words(const char *prefix, const unsigned *data, + unsigned word_count) +{ + char *output; + + sprintf(Diag_msg, "%s (%08X,%uw): ", prefix, (uint32_t) data, + word_count); + + /* We've already printed some text in output buffer, skip over it */ + output = Diag_msg + strlen(Diag_msg); + + while (word_count--) { + sprintf(output, "%08X ", *data++); + output += 9; + } + + LOG_KDIAG(Diag_msg); +} +#endif diff --git a/drivers/mxc/security/sahara2/sah_driver_interface.c b/drivers/mxc/security/sahara2/sah_driver_interface.c new file mode 100644 index 000000000000..cf01c5f8bfe0 --- /dev/null +++ b/drivers/mxc/security/sahara2/sah_driver_interface.c @@ -0,0 +1,2185 @@ +/* + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_driver_interface.c +* +* @brief Provides a Linux Kernel Module interface to the SAHARA h/w device. +* +*/ + +/* SAHARA Includes */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef FSL_HAVE_SCC +#include +#else +#include +#endif + +#ifdef DIAG_DRV_IF +#include +#endif + +#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) +#include +#else +#include +#endif + +#ifdef PERF_TEST +#define interruptible_sleep_on(x) sah_Handle_Interrupt() +#endif + +#define TEST_MODE_OFF 1 +#define TEST_MODE_ON 2 + +/*! Version register on first deployments */ +#define SAHARA_VERSION2 2 +/*! Version register on MX27 */ +#define SAHARA_VERSION3 3 +/*! Version register on MXC92323 */ +#define SAHARA_VERSION4 4 + +/****************************************************************************** +* Module function declarations +******************************************************************************/ + +OS_DEV_INIT_DCL(sah_init); +OS_DEV_SHUTDOWN_DCL(sah_cleanup); +OS_DEV_OPEN_DCL(sah_open); +OS_DEV_CLOSE_DCL(sah_release); +OS_DEV_IOCTL_DCL(sah_ioctl); +OS_DEV_MMAP_DCL(sah_mmap); + +static os_error_code sah_handle_get_capabilities(fsl_shw_uco_t* user_ctx, + uint32_t info); + +static void sah_user_callback(fsl_shw_uco_t * user_ctx); +static os_error_code sah_handle_scc_sfree(fsl_shw_uco_t* user_ctx, + uint32_t info); +static os_error_code sah_handle_scc_sstatus(fsl_shw_uco_t* user_ctx, + uint32_t info); +static os_error_code sah_handle_scc_drop_perms(fsl_shw_uco_t* user_ctx, + uint32_t info); +static os_error_code sah_handle_scc_encrypt(fsl_shw_uco_t* user_ctx, + uint32_t info); +static os_error_code sah_handle_scc_decrypt(fsl_shw_uco_t* user_ctx, + uint32_t info); + +#ifdef FSL_HAVE_SCC2 +static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base, + void *kernel_base); +static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base); +#endif + +static os_error_code sah_handle_sk_slot_alloc(uint32_t info); +static os_error_code sah_handle_sk_slot_dealloc(uint32_t info); +static os_error_code sah_handle_sk_slot_load(uint32_t info); +static os_error_code sah_handle_sk_slot_read(uint32_t info); +static os_error_code sah_handle_sk_slot_decrypt(uint32_t info); +static os_error_code sah_handle_sk_slot_encrypt(uint32_t info); + +/*! Boolean flag for whether interrupt handler needs to be released on exit */ +static unsigned interrupt_registered; + +static int handle_sah_ioctl_dar(fsl_shw_uco_t * filp, uint32_t user_space_desc); + +#if !defined(CONFIG_DEVFS_FS) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +static int sah_read_procfs(char *buf, + char **start, + off_t offset, int count, int *eof, void *data); + +static int sah_write_procfs(struct file *file, const char __user * buffer, + unsigned long count, void *data); +#endif + +#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) + +/* This is a handle to the sahara DEVFS entry. */ +static devfs_handle_t Sahara_devfs_handle; + +#else + +/* Major number assigned to our device driver */ +static int Major; + +/* This is a handle to the sahara PROCFS entry */ +static struct proc_dir_entry *Sahara_procfs_handle; + +#endif + +uint32_t sah_hw_version; +extern void *sah_virt_base; + +/* This is the wait queue to this driver. Linux declaration. */ +DECLARE_WAIT_QUEUE_HEAD(Wait_queue); + +/* This is a global variable that is used to track how many times the device + * has been opened simultaneously. */ +#ifdef DIAG_DRV_IF +static int Device_in_use = 0; +#endif + +/* This is the system keystore object */ +fsl_shw_kso_t system_keystore; + +/*! + * OS-dependent handle used for registering user interface of a driver. + */ +static os_driver_reg_t reg_handle; + +#ifdef DIAG_DRV_IF +/* This is for sprintf() to use when constructing output. */ +#define DIAG_MSG_SIZE 1024 +static char Diag_msg[DIAG_MSG_SIZE]; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18)) +/** Pointer to Sahara clock information. Initialized during os_dev_init(). */ +static struct clk *sah_clk; +#endif + +/*! +******************************************************************************* +* This function gets called when the module is inserted (insmod) into the +* running kernel. +* +* @brief SAHARA device initialisation function. +* +* @return 0 on success +* @return -EBUSY if the device or proc file entry cannot be created. +* @return OS_ERROR_NO_MEMORY_S if kernel memory could not be allocated. +* @return OS_ERROR_FAIL_S if initialisation of proc entry failed +*/ +OS_DEV_INIT(sah_init) +{ + /* Status variable */ + int os_error_code = 0; + uint32_t sah_phys_base = SAHARA_BASE_ADDR; + + + interrupt_registered = 0; + + /* Enable the SAHARA Clocks */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA : Enabling the IPG and AHB clocks\n") +#endif /*DIAG_DRV_IF */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + mxc_clks_enable(SAHARA2_CLK); +#else + { + sah_clk = clk_get(NULL, "sahara_clk"); + if (IS_ERR(sah_clk)) + os_error_code = PTR_ERR(sah_clk); + else + clk_enable(sah_clk); + } +#endif + + if (cpu_is_mx53()) + sah_phys_base -= 0x20000000; + + sah_virt_base = (void *)ioremap(sah_phys_base, SZ_16K); + if (sah_virt_base == NULL) { + os_printk(KERN_ERR + "SAHARA: Register mapping failed\n"); + os_error_code = OS_ERROR_FAIL_S; + } + + if (os_error_code == OS_ERROR_OK_S) { + sah_hw_version = sah_HW_Read_Version(); + os_printk("Sahara HW Version is 0x%08x\n", sah_hw_version); + + /* verify code and hardware are version compatible */ + if ((sah_hw_version != SAHARA_VERSION2) + && (sah_hw_version != SAHARA_VERSION3)) { + if (((sah_hw_version >> 8) & 0xff) != SAHARA_VERSION4) { + os_printk + ("Sahara HW Version was not expected value.\n"); + os_error_code = OS_ERROR_FAIL_S; + } + } + } + + if (os_error_code == OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Calling sah_Init_Mem_Map to initialise " + "memory subsystem."); +#endif + /* Do any memory-routine initialization */ + os_error_code = sah_Init_Mem_Map(); + } + + if (os_error_code == OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Calling sah_HW_Reset() to Initialise the Hardware."); +#endif + /* Initialise the hardware */ + os_error_code = sah_HW_Reset(); + if (os_error_code != OS_ERROR_OK_S) { + os_printk + ("sah_HW_Reset() failed to Initialise the Hardware.\n"); + } + + } + + if (os_error_code == OS_ERROR_OK_S) { +#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) + /* Register the DEVFS entry */ + Sahara_devfs_handle = devfs_register(NULL, + SAHARA_DEVICE_SHORT, + DEVFS_FL_AUTO_DEVNUM, + 0, 0, + SAHARA_DEVICE_MODE, + &Fops, NULL); + if (Sahara_devfs_handle == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("Registering the DEVFS character device failed."); +#endif /* DIAG_DRV_IF */ + os_error_code = -EBUSY; + } +#else /* CONFIG_DEVFS_FS */ + /* Create the PROCFS entry. This is used to report the assigned device + * major number back to user-space. */ +#if 1 + Sahara_procfs_handle = create_proc_entry(SAHARA_DEVICE_SHORT, 0700, /* default mode */ + NULL); /* parent dir */ + if (Sahara_procfs_handle == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Registering the PROCFS interface failed."); +#endif /* DIAG_DRV_IF */ + os_error_code = OS_ERROR_FAIL_S; + } else { + Sahara_procfs_handle->nlink = 1; + Sahara_procfs_handle->data = 0; + Sahara_procfs_handle->read_proc = sah_read_procfs; + Sahara_procfs_handle->write_proc = sah_write_procfs; + } +#endif /* #if 1 */ + } + + if (os_error_code == OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("Calling sah_Queue_Manager_Init() to Initialise the Queue " + "Manager."); +#endif + /* Initialise the Queue Manager */ + if (sah_Queue_Manager_Init() != FSL_RETURN_OK_S) { + os_error_code = -ENOMEM; + } + } +#ifndef SAHARA_POLL_MODE + if (os_error_code == OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Calling sah_Intr_Init() to Initialise the Interrupt " + "Handler."); +#endif + /* Initialise the Interrupt Handler */ + os_error_code = sah_Intr_Init(&Wait_queue); + if (os_error_code == OS_ERROR_OK_S) { + interrupt_registered = 1; + } + } +#endif /* ifndef SAHARA_POLL_MODE */ + +#ifdef SAHARA_POWER_MANAGEMENT + if (os_error_code == OS_ERROR_OK_S) { + /* set up dynamic power management (dmp) */ + os_error_code = sah_dpm_init(); + } +#endif + + if (os_error_code == OS_ERROR_OK_S) { + os_driver_init_registration(reg_handle); + os_driver_add_registration(reg_handle, OS_FN_OPEN, + OS_DEV_OPEN_REF(sah_open)); + os_driver_add_registration(reg_handle, OS_FN_IOCTL, + OS_DEV_IOCTL_REF(sah_ioctl)); + os_driver_add_registration(reg_handle, OS_FN_CLOSE, + OS_DEV_CLOSE_REF(sah_release)); + os_driver_add_registration(reg_handle, OS_FN_MMAP, + OS_DEV_MMAP_REF(sah_mmap)); + + os_error_code = + os_driver_complete_registration(reg_handle, Major, + "sahara"); + + if (os_error_code < OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Registering the regular " + "character device failed with error code: %d\n", + os_error_code); + LOG_KDIAG(Diag_msg); +#endif + } + } +#endif /* CONFIG_DEVFS_FS */ + + if (os_error_code == OS_ERROR_OK_S) { + /* set up the system keystore, using the default keystore handler */ + fsl_shw_init_keystore_default(&system_keystore); + + if (fsl_shw_establish_keystore(NULL, &system_keystore) + == FSL_RETURN_OK_S) { + os_error_code = OS_ERROR_OK_S; + } else { + os_error_code = OS_ERROR_FAIL_S; + } + + if (os_error_code != OS_ERROR_OK_S) { +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Registering the system keystore " + "failed with error code: %d\n", os_error_code); + LOG_KDIAG(Diag_msg); +#endif + } + } + + if (os_error_code != OS_ERROR_OK_S) { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) + cleanup_module(); +#else + sah_cleanup(); +#endif + } +#ifdef DIAG_DRV_IF + else { + LOG_KDIAG_ARGS("Sahara major node is %d\n", Major); + } +#endif + +/* Disabling the Clock after the driver has been registered fine. + This is done to save power when Sahara is not in use.*/ +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA : Disabling the clocks\n") +#endif /* DIAG_DRV_IF */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_disable(SAHARA2_CLK); +#else + { + if (IS_ERR(sah_clk)) + os_error_code = PTR_ERR(sah_clk); + else + clk_disable(sah_clk); + } +#endif + + os_dev_init_return(os_error_code); +} + +/*! +******************************************************************************* +* This function gets called when the module is removed (rmmod) from the running +* kernel. +* +* @brief SAHARA device clean-up function. +* +* @return void +*/ +OS_DEV_SHUTDOWN(sah_cleanup) +{ + int ret_val = 0; + + printk(KERN_ALERT "Sahara going into cleanup\n"); + + /* clear out the system keystore */ + fsl_shw_release_keystore(NULL, &system_keystore); + + /* Unregister the device */ +#if defined(CONFIG_DEVFS_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) + devfs_unregister(Sahara_devfs_handle); +#else + + if (Sahara_procfs_handle != NULL) { + remove_proc_entry(SAHARA_DEVICE_SHORT, NULL); + } + + if (Major >= 0) { + ret_val = os_driver_remove_registration(reg_handle); + } +#ifdef DIAG_DRV_IF + if (ret_val < 0) { + snprintf(Diag_msg, DIAG_MSG_SIZE, "Error while attempting to " + "unregister the device: %d\n", ret_val); + LOG_KDIAG(Diag_msg); + } +#endif + +#endif /* CONFIG_DEVFS_FS */ + sah_Queue_Manager_Close(); + +#ifndef SAHARA_POLL_MODE + if (interrupt_registered) { + sah_Intr_Release(); + interrupt_registered = 0; + } +#endif + sah_Stop_Mem_Map(); +#ifdef SAHARA_POWER_MANAGEMENT + sah_dpm_close(); +#endif + +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA : Disabling the clocks\n") +#endif /* DIAG_DRV_IF */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + mxc_clks_disable(SAHARA2_CLK); +#else + { + if (IS_ERR(sah_clk)) + ret_val = PTR_ERR(sah_clk); + else + clk_disable(sah_clk); + clk_put(sah_clk); + } +#endif + + os_dev_shutdown_return(ret_val); +} + +/*! +******************************************************************************* +* This function simply increments the module usage count. +* +* @brief SAHARA device open function. +* +* @param inode Part of the kernel prototype. +* @param file Part of the kernel prototype. +* +* @return 0 - Always returns 0 since any number of calls to this function are +* allowed. +* +*/ +OS_DEV_OPEN(sah_open) +{ + +#if defined(LINUX_VERSION) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10)) + MOD_INC_USE_COUNT; +#endif + +#ifdef DIAG_DRV_IF + Device_in_use++; + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Incrementing module use count to: %d ", Device_in_use); + LOG_KDIAG(Diag_msg); +#endif + + os_dev_set_user_private(NULL); + + /* Return 0 to indicate success */ + os_dev_open_return(0); +} + +/*! +******************************************************************************* +* This function simply decrements the module usage count. +* +* @brief SAHARA device release function. +* +* @param inode Part of the kernel prototype. +* @param file Part of the kernel prototype. +* +* @return 0 - Always returns 0 since this function does not fail. +*/ +OS_DEV_CLOSE(sah_release) +{ + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + +#if defined(LINUX_VERSION) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10)) + MOD_DEC_USE_COUNT; +#endif + +#ifdef DIAG_DRV_IF + Device_in_use--; + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Decrementing module use count to: %d ", Device_in_use); + LOG_KDIAG(Diag_msg); +#endif + + if (user_ctx != NULL) { + sah_handle_deregistration(user_ctx); + os_free_memory(user_ctx); + os_dev_set_user_private(NULL); + } + + /* Return 0 to indicate success */ + os_dev_close_return(OS_ERROR_OK_S); +} + +/*! +******************************************************************************* +* This function provides the IO Controls for the SAHARA driver. Three IO +* Controls are supported: +* +* SAHARA_HWRESET and +* SAHARA_SET_HA +* SAHARA_CHK_TEST_MODE +* +* @brief SAHARA device IO Control function. +* +* @param inode Part of the kernel prototype. +* @param filp Part of the kernel prototype. +* @param cmd Part of the kernel prototype. +* @param arg Part of the kernel prototype. +* +* @return 0 on success +* @return -EBUSY if the HA bit could not be set due to busy hardware. +* @return -ENOTTY if an unsupported IOCTL was attempted on the device. +* @return -EFAULT if put_user() fails +*/ +OS_DEV_IOCTL(sah_ioctl) +{ + int status = 0; + int test_mode; + + switch (os_dev_get_ioctl_op()) { + case SAHARA_HWRESET: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_HWRESET IOCTL."); +#endif + /* We need to reset the hardware. */ + sah_HW_Reset(); + + /* Mark all the entries in the Queue Manager's queue with state + * SAH_STATE_RESET. + */ + sah_Queue_Manager_Reset_Entries(); + + /* Wake up all sleeping write() calls. */ + wake_up_interruptible(&Wait_queue); + break; +#ifdef SAHARA_HA_ENABLED + case SAHARA_SET_HA: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SET_HA IOCTL."); +#endif /* DIAG_DRV_IF */ + if (sah_HW_Set_HA() == ERR_INTERNAL) { + status = -EBUSY; + } + break; +#endif /* SAHARA_HA_ENABLED */ + + case SAHARA_CHK_TEST_MODE: + /* load test_mode */ + test_mode = TEST_MODE_OFF; +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_CHECK_TEST_MODE IOCTL."); + test_mode = TEST_MODE_ON; +#endif /* DIAG_DRV_IF */ +#if defined(KERNEL_TEST) || defined(PERF_TEST) + test_mode = TEST_MODE_ON; +#endif /* KERNEL_TEST || PERF_TEST */ + /* copy test_mode back to user space. put_user() is Linux fn */ + /* compiler warning `register': no problem found so ignored */ + status = put_user(test_mode, (int *)os_dev_get_ioctl_arg()); + break; + + case SAHARA_DAR: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_DAR IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + if (user_ctx != NULL) { + status = + handle_sah_ioctl_dar(user_ctx, + os_dev_get_ioctl_arg + ()); + } else { + status = OS_ERROR_FAIL_S; + } + + } + break; + + case SAHARA_GET_RESULTS: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_GET_RESULTS IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + if (user_ctx != NULL) { + status = + sah_get_results_pointers(user_ctx, + os_dev_get_ioctl_arg + ()); + } else { + status = OS_ERROR_FAIL_S; + } + } + break; + + case SAHARA_REGISTER: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_REGISTER IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + if (user_ctx != NULL) { + status = OS_ERROR_FAIL_S; /* already registered */ + } else { + user_ctx = + os_alloc_memory(sizeof(fsl_shw_uco_t), + GFP_KERNEL); + if (user_ctx == NULL) { + status = OS_ERROR_NO_MEMORY_S; + } else { + /* Copy UCO from user, but only as big as the common UCO */ + if (os_copy_from_user(user_ctx, + (void *) + os_dev_get_ioctl_arg + (), + offsetof + (fsl_shw_uco_t, + result_pool))) { + status = OS_ERROR_FAIL_S; + } else { + os_dev_set_user_private + (user_ctx); + status = + sah_handle_registration + (user_ctx); + } + } + } + } + break; + + /* This ioctl cmd should disappear in favor of a close() routine. */ + case SAHARA_DEREGISTER: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_DEREGISTER IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + if (user_ctx == NULL) { + status = OS_ERROR_FAIL_S; + } else { + status = sah_handle_deregistration(user_ctx); + os_free_memory(user_ctx); + os_dev_set_user_private(NULL); + } + } + break; + case SAHARA_SCC_DROP_PERMS: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_DROP_PERMS IOCTL."); +#endif /* DIAG_DRV_IF */ + { + /* drop permissions on the specified partition */ + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_drop_perms(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SCC_SFREE: + /* Unmap the specified partition from the users space, and then + * free it for use by someone else. + */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_SFREE IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_sfree(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SCC_SSTATUS: + /* Unmap the specified partition from the users space, and then + * free it for use by someone else. + */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_SSTATUS IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_sstatus(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SCC_ENCRYPT: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_ENCRYPT IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_encrypt(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SCC_DECRYPT: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SCC_DECRYPT IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_scc_decrypt(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + case SAHARA_SK_ALLOC: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_ALLOC IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_alloc(os_dev_get_ioctl_arg()); + break; + + case SAHARA_SK_DEALLOC: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_DEALLOC IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_dealloc(os_dev_get_ioctl_arg()); + break; + + case SAHARA_SK_LOAD: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_LOAD IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_load(os_dev_get_ioctl_arg()); + break; + case SAHARA_SK_READ: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_READ IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_read(os_dev_get_ioctl_arg()); + break; + + case SAHARA_SK_SLOT_DEC: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_SLOT_DECRYPT IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_decrypt(os_dev_get_ioctl_arg()); + break; + + case SAHARA_SK_SLOT_ENC: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_SK_SLOT_ENCRYPT IOCTL."); +#endif /* DIAG_DRV_IF */ + status = sah_handle_sk_slot_encrypt(os_dev_get_ioctl_arg()); + break; + case SAHARA_GET_CAPS: +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA_GET_CAPS IOCTL."); +#endif /* DIAG_DRV_IF */ + { + fsl_shw_uco_t *user_ctx = os_dev_get_user_private(); + + status = + sah_handle_get_capabilities(user_ctx, + os_dev_get_ioctl_arg()); + } + break; + + default: +#ifdef DIAG_DRV_IF + LOG_KDIAG("Unknown SAHARA IOCTL."); +#endif /* DIAG_DRV_IF */ + status = OS_ERROR_FAIL_S; + } + + os_dev_ioctl_return(status); +} + +/* Fill in the user's capabilities structure */ +static os_error_code sah_handle_get_capabilities(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_FAIL_S; + fsl_shw_pco_t capabilities; + + status = os_copy_from_user(&capabilities, (void *)info, + sizeof(fsl_shw_pco_t)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + if (get_capabilities(user_ctx, &capabilities) == FSL_RETURN_OK_S) { + status = os_copy_to_user((void *)info, &capabilities, + sizeof(fsl_shw_pco_t)); + } + + out: + return status; +} + +#ifdef FSL_HAVE_SCC2 + +/* Find the kernel-mode address of the partition. + * This can then be passed to the SCC functions. + */ +void *lookup_user_partition(fsl_shw_uco_t * user_ctx, uint32_t user_base) +{ + /* search through the partition chain to find one that matches the user base + * address. + */ + fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition; + + while (curr != NULL) { + if (curr->user_base == user_base) { + return curr->kernel_base; + } + curr = (fsl_shw_spo_t *) curr->next; + } + return NULL; +} + +/* user_base: userspace base address of the partition + * kernel_base: kernel mode base address of the partition + */ +static fsl_shw_return_t register_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base, + void *kernel_base) +{ + fsl_shw_spo_t *partition_info; + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + if (user_ctx == NULL) { + goto out; + } + + partition_info = os_alloc_memory(sizeof(fsl_shw_spo_t), GFP_KERNEL); + + if (partition_info == NULL) { + goto out; + } + + /* stuff the partition info, then put it at the front of the chain */ + partition_info->user_base = user_base; + partition_info->kernel_base = kernel_base; + partition_info->next = user_ctx->partition; + + user_ctx->partition = (struct fsl_shw_spo_t *)partition_info; + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("partition with user_base=%p, kernel_base=%p registered.", + (void *)user_base, kernel_base); +#endif + + ret = FSL_RETURN_OK_S; + + out: + + return ret; +} + +/* if the partition is in the users list, remove it */ +static fsl_shw_return_t deregister_user_partition(fsl_shw_uco_t * user_ctx, + uint32_t user_base) +{ + fsl_shw_spo_t *curr = (fsl_shw_spo_t *) user_ctx->partition; + fsl_shw_spo_t *last = (fsl_shw_spo_t *) user_ctx->partition; + + while (curr != NULL) { + if (curr->user_base == user_base) { + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("deregister_user_partition: partition with " + "user_base=%p, kernel_base=%p deregistered.\n", + (void *)curr->user_base, curr->kernel_base); +#endif + + if (last == curr) { + user_ctx->partition = curr->next; + os_free_memory(curr); + return FSL_RETURN_OK_S; + } else { + last->next = curr->next; + os_free_memory(curr); + return FSL_RETURN_OK_S; + } + } + last = curr; + curr = (fsl_shw_spo_t *) curr->next; + } + + return FSL_RETURN_ERROR_S; +} + +#endif /* FSL_HAVE_SCC2 */ + +static os_error_code sah_handle_scc_drop_perms(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + scc_return_t scc_ret; + scc_partition_info_t partition_info; + void *kernel_base; + + status = + os_copy_from_user(&partition_info, (void *)info, + sizeof(partition_info)); + + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("_scc_drop_perms(): failed to find partition\n"); +#endif + goto out; + } + + /* call scc driver to perform the drop */ + scc_ret = scc_diminish_permissions(kernel_base, + partition_info.permissions); + if (scc_ret == SCC_RET_OK) { + status = OS_ERROR_OK_S; + } else { + status = OS_ERROR_FAIL_S; + } + + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code sah_handle_scc_sfree(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + { + scc_partition_info_t partition_info; + void *kernel_base; + int ret; + + status = + os_copy_from_user(&partition_info, (void *)info, + sizeof(partition_info)); + + /* check that the copy was successful */ + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = + lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("failed to find partition\n"); +#endif /*DIAG_DRV_IF */ + goto out; + } + + /* Unmap the memory region (see sys_munmap in mmap.c) */ + ret = unmap_user_memory(partition_info.user_base, 8192); + + /* If the memory was successfully released */ + if (ret == OS_ERROR_OK_S) { + + /* release the partition */ + scc_release_partition(kernel_base); + + /* and remove it from the users context */ + deregister_user_partition(user_ctx, + partition_info.user_base); + + status = OS_ERROR_OK_S; + } + } + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code sah_handle_scc_sstatus(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; +#ifdef FSL_HAVE_SCC2 + { + scc_partition_info_t partition_info; + void *kernel_base; + + status = + os_copy_from_user(&partition_info, (void *)info, + sizeof(partition_info)); + + /* check that the copy was successful */ + if (status != OS_ERROR_OK_S) { + goto out; + } + + /* validate that the user owns this partition, and look up its handle */ + kernel_base = + lookup_user_partition(user_ctx, partition_info.user_base); + + if (kernel_base == NULL) { + status = OS_ERROR_FAIL_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("failed to find partition\n"); +#endif /*DIAG_DRV_IF */ + goto out; + } + + partition_info.status = scc_partition_status(kernel_base); + + status = + os_copy_to_user((void *)info, &partition_info, + sizeof(partition_info)); + } + out: +#endif /* FSL_HAVE_SCC2 */ + return status; +} + +static os_error_code sah_handle_scc_encrypt(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code os_err = OS_ERROR_FAIL_S; +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_return_t retval; + scc_region_t region_info; + void *page_ctx = NULL; + void *black_addr = NULL; + void *partition_base = NULL; + scc_config_t *scc_configuration; + + os_err = + os_copy_from_user(®ion_info, (void *)info, + sizeof(region_info)); + + if (os_err != OS_ERROR_OK_S) { + goto out; + } +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("partition_base: %p, offset: %i, length: %i, black data: %p", + (void *)region_info.partition_base, region_info.offset, + region_info.length, (void *)region_info.black_data); +#endif + + /* validate that the user owns this partition, and look up its handle */ + partition_base = lookup_user_partition(user_ctx, + region_info. + partition_base); + + if (partition_base == NULL) { + retval = FSL_RETURN_ERROR_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("failed to find secure partition\n"); +#endif + goto out; + } + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (region_info.offset + region_info.length > + scc_configuration->partition_size_bytes) { + retval = FSL_RETURN_ERROR_S; + goto out; + } + + /* wire down black data */ + black_addr = wire_user_memory(region_info.black_data, + region_info.length, &page_ctx); + + if (black_addr == NULL) { + retval = FSL_RETURN_ERROR_S; + goto out; + } + + retval = + do_scc_encrypt_region(NULL, partition_base, + region_info.offset, + region_info.length, black_addr, + region_info.IV, + region_info.cypher_mode); + + /* release black data */ + unwire_user_memory(&page_ctx); + + out: + if (os_err == OS_ERROR_OK_S) { + /* Return error code */ + region_info.code = retval; + os_err = + os_copy_to_user((void *)info, ®ion_info, + sizeof(region_info)); + } + } + +#endif + return os_err; +} + +static os_error_code sah_handle_scc_decrypt(fsl_shw_uco_t * user_ctx, + uint32_t info) +{ + os_error_code os_err = OS_ERROR_FAIL_S; +#ifdef FSL_HAVE_SCC2 + { + fsl_shw_return_t retval; + scc_region_t region_info; + void *page_ctx = NULL; + void *black_addr; + void *partition_base; + scc_config_t *scc_configuration; + + os_err = + os_copy_from_user(®ion_info, (void *)info, + sizeof(region_info)); + + if (os_err != OS_ERROR_OK_S) { + goto out; + } +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("partition_base: %p, offset: %i, length: %i, black data: %p", + (void *)region_info.partition_base, region_info.offset, + region_info.length, (void *)region_info.black_data); +#endif + + /* validate that the user owns this partition, and look up its handle */ + partition_base = lookup_user_partition(user_ctx, + region_info. + partition_base); + + if (partition_base == NULL) { + retval = FSL_RETURN_ERROR_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("failed to find partition\n"); +#endif + goto out; + } + + /* Check that the memory size requested is correct */ + scc_configuration = scc_get_configuration(); + if (region_info.offset + region_info.length > + scc_configuration->partition_size_bytes) { + retval = FSL_RETURN_ERROR_S; + goto out; + } + + /* wire down black data */ + black_addr = wire_user_memory(region_info.black_data, + region_info.length, &page_ctx); + + if (black_addr == NULL) { + retval = FSL_RETURN_ERROR_S; + goto out; + } + + retval = + do_scc_decrypt_region(NULL, partition_base, + region_info.offset, + region_info.length, black_addr, + region_info.IV, + region_info.cypher_mode); + + /* release black data */ + unwire_user_memory(&page_ctx); + + out: + if (os_err == OS_ERROR_OK_S) { + /* Return error code */ + region_info.code = retval; + os_err = + os_copy_to_user((void *)info, ®ion_info, + sizeof(region_info)); + } + } + +#endif /* FSL_HAVE_SCC2 */ + return os_err; +} + +/*****************************************************************************/ +/* fn get_user_smid() */ +/*****************************************************************************/ +uint32_t get_user_smid(void *proc) +{ + /* + * A real implementation would have some way to handle signed applications + * which wouild be assigned distinct SMIDs. For the reference + * implementation, we show where this would be determined (here), but + * always provide a fixed answer, thus not separating users at all. + */ + + return 0x42eaae42; +} + +/*! +******************************************************************************* +* This function implements the smalloc() function for userspace programs, by +* making a call to the SCC2 mmap() function that acquires a region of secure +* memory on behalf of the user, and then maps it into the users memory space. +* Currently, the only memory size supported is that of a single SCC2 partition. +* Requests for other sized memory regions will fail. +*/ +OS_DEV_MMAP(sah_mmap) +{ + os_error_code status = OS_ERROR_NO_MEMORY_S; + +#ifdef FSL_HAVE_SCC2 + { + scc_return_t scc_ret; + fsl_shw_return_t fsl_ret; + uint32_t partition_registered = FALSE; + + uint32_t user_base; + void *partition_base; + uint32_t smid; + scc_config_t *scc_configuration; + + int part_no = -1; + uint32_t part_phys; + + fsl_shw_uco_t *user_ctx = + (fsl_shw_uco_t *) os_dev_get_user_private(); + + /* Make sure that the user context is valid */ + if (user_ctx == NULL) { + user_ctx = + os_alloc_memory(sizeof(*user_ctx), GFP_KERNEL); + + if (user_ctx == NULL) { + status = OS_ERROR_NO_MEMORY_S; + goto out; + } + + sah_handle_registration(user_ctx); + os_dev_set_user_private(user_ctx); + } + + /* Determine the size of a secure partition */ + scc_configuration = scc_get_configuration(); + + /* Check that the memory size requested is equal to the partition + * size, and that the requested destination is on a page boundary. + */ + if (((os_mmap_user_base() % PAGE_SIZE) != 0) || + (os_mmap_memory_size() != + scc_configuration->partition_size_bytes)) { + status = OS_ERROR_BAD_ARG_S; + goto out; + } + + /* Retrieve the SMID associated with the user */ + smid = get_user_smid(user_ctx->process); + + /* Attempt to allocate a secure partition */ + scc_ret = + scc_allocate_partition(smid, &part_no, &partition_base, + &part_phys); + if (scc_ret != SCC_RET_OK) { + pr_debug + ("SCC mmap() request failed to allocate partition;" + " error %d\n", status); + status = OS_ERROR_FAIL_S; + goto out; + } + + pr_debug("scc_mmap() acquired partition %d at %08x\n", + part_no, part_phys); + + /* Record partition info in the user context */ + user_base = os_mmap_user_base(); + fsl_ret = + register_user_partition(user_ctx, user_base, + partition_base); + + if (fsl_ret != FSL_RETURN_OK_S) { + pr_debug + ("SCC mmap() request failed to register partition with user" + " context, error: %d\n", fsl_ret); + status = OS_ERROR_FAIL_S; + } + + partition_registered = TRUE; + + status = map_user_memory(os_mmap_memory_ctx(), part_phys, + os_mmap_memory_size()); + +#ifdef SHW_DEBUG + if (status == OS_ERROR_OK_S) { + LOG_KDIAG_ARGS + ("Partition allocated: user_base=%p, partition_base=%p.", + (void *)user_base, partition_base); + } +#endif + + out: + /* If there is an error it has to be handled here */ + if (status != OS_ERROR_OK_S) { + /* if the partition was registered with the user, unregister it. */ + if (partition_registered == TRUE) { + deregister_user_partition(user_ctx, user_base); + } + + /* if the partition was allocated, deallocate it */ + if (partition_base != NULL) { + scc_release_partition(partition_base); + } + } + } +#endif /* FSL_HAVE_SCC2 */ + + return status; +} + +/* Find the physical address of a key stored in the system keystore */ +fsl_shw_return_t +system_keystore_get_slot_info(uint64_t owner_id, uint32_t slot, + uint32_t * address, uint32_t * slot_size_bytes) +{ + fsl_shw_return_t retval; + void *kernel_address; + + /* First verify that the key access is valid */ + retval = system_keystore.slot_verify_access(system_keystore.user_data, + owner_id, slot); + + if (retval != FSL_RETURN_OK_S) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("verification failed"); +#endif + return retval; + } + + if (address != NULL) { +#ifdef FSL_HAVE_SCC2 + kernel_address = + system_keystore.slot_get_address(system_keystore.user_data, + slot); + (*address) = scc_virt_to_phys(kernel_address); +#else + kernel_address = + system_keystore.slot_get_address((void *)&owner_id, slot); + (*address) = (uint32_t) kernel_address; +#endif + } + + if (slot_size_bytes != NULL) { +#ifdef FSL_HAVE_SCC2 + *slot_size_bytes = + system_keystore.slot_get_slot_size(system_keystore. + user_data, slot); +#else + *slot_size_bytes = + system_keystore.slot_get_slot_size((void *)&owner_id, slot); +#endif + } + + return retval; +} + +static os_error_code sah_handle_sk_slot_alloc(uint32_t info) +{ + scc_slot_t slot_info; + os_error_code os_err; + scc_return_t scc_ret; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + if (os_err == OS_ERROR_OK_S) { + scc_ret = keystore_slot_alloc(&system_keystore, + slot_info.key_length, + slot_info.ownerid, + &slot_info.slot); + if (scc_ret == SCC_RET_OK) { + slot_info.code = FSL_RETURN_OK_S; + } else if (scc_ret == SCC_RET_INSUFFICIENT_SPACE) { + slot_info.code = FSL_RETURN_NO_RESOURCE_S; + } else { + slot_info.code = FSL_RETURN_ERROR_S; + } + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("key length: %i, handle: %i\n", + slot_info.key_length, slot_info.slot); +#endif + + /* Return error code and slot info */ + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + + if (os_err != OS_ERROR_OK_S) { + (void)keystore_slot_dealloc(&system_keystore, + slot_info.ownerid, + slot_info.slot); + } + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_dealloc(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; + os_error_code os_err; + scc_return_t scc_ret; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + scc_ret = keystore_slot_dealloc(&system_keystore, + slot_info.ownerid, + slot_info.slot); + + if (scc_ret == SCC_RET_OK) { + ret = FSL_RETURN_OK_S; + } else { + ret = FSL_RETURN_ERROR_S; + } + slot_info.code = ret; + + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_load(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; + os_error_code os_err; + uint8_t *key = NULL; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + /* Allow slop in alloc in case we are rounding up to word multiple */ + key = os_alloc_memory(slot_info.key_length + 3, GFP_KERNEL); + if (key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + os_err = OS_ERROR_NO_MEMORY_S; + } else { + os_err = os_copy_from_user(key, slot_info.key, + slot_info.key_length); + } + } + + if (os_err == OS_ERROR_OK_S) { + unsigned key_length = slot_info.key_length; + + /* Round up if necessary, as SCC call wants a multiple of 32-bit + * values for the full object being loaded. */ + if ((key_length & 3) != 0) { + key_length += 4 - (key_length & 3); + } + ret = keystore_slot_load(&system_keystore, + slot_info.ownerid, slot_info.slot, key, + key_length); + + slot_info.code = ret; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + } + + if (key != NULL) { + memset(key, 0, slot_info.key_length); + os_free_memory(key); + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_read(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; + os_error_code os_err; + uint8_t *key = NULL; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + + /* This operation is not allowed for user keys */ + slot_info.code = FSL_RETURN_NO_RESOURCE_S; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + + return os_err; + } + + if (os_err == OS_ERROR_OK_S) { + /* Allow slop in alloc in case we are rounding up to word multiple */ + key = os_alloc_memory(slot_info.key_length + 3, GFP_KERNEL); + if (key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + os_err = OS_ERROR_NO_MEMORY_S; + } + } + + if (os_err == OS_ERROR_OK_S) { + unsigned key_length = slot_info.key_length; + + /* @bug Do some PERMISSIONS checking - make sure this is SW key */ + + /* Round up if necessary, as SCC call wants a multiple of 32-bit + * values for the full object being loaded. */ + if ((key_length & 3) != 0) { + key_length += 4 - (key_length & 3); + } + ret = keystore_slot_read(&system_keystore, + slot_info.ownerid, slot_info.slot, + key_length, key); + + /* @bug do some error checking */ + + /* Send key back to user */ + os_err = os_copy_to_user(slot_info.key, key, + slot_info.key_length); + + slot_info.code = ret; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + } + + if (key != NULL) { + memset(key, 0, slot_info.key_length); + os_free_memory(key); + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_encrypt(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; + os_error_code os_err; + scc_return_t scc_ret; + uint8_t *key = NULL; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + key = os_alloc_memory(slot_info.key_length, GFP_KERNEL); + if (key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + } + } + + if (key != NULL) { + + scc_ret = keystore_slot_encrypt(NULL, &system_keystore, + slot_info.ownerid, + slot_info.slot, + slot_info.key_length, key); + + if (scc_ret != SCC_RET_OK) { + ret = FSL_RETURN_ERROR_S; + } else { + os_err = + os_copy_to_user(slot_info.key, key, + slot_info.key_length); + if (os_err != OS_ERROR_OK_S) { + ret = FSL_RETURN_INTERNAL_ERROR_S; + } else { + ret = FSL_RETURN_OK_S; + } + } + + slot_info.code = ret; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + + memset(key, 0, slot_info.key_length); + os_free_memory(key); + } + + return os_err; +} + +static os_error_code sah_handle_sk_slot_decrypt(uint32_t info) +{ + fsl_shw_return_t ret = FSL_RETURN_INTERNAL_ERROR_S; + scc_slot_t slot_info; /*!< decrypt request fields */ + os_error_code os_err; + scc_return_t scc_ret; + uint8_t *key = NULL; + + os_err = os_copy_from_user(&slot_info, (void *)info, sizeof(slot_info)); + + if (os_err == OS_ERROR_OK_S) { + key = os_alloc_memory(slot_info.key_length, GFP_KERNEL); + if (key == NULL) { + ret = FSL_RETURN_NO_RESOURCE_S; + os_err = OS_ERROR_OK_S; + } else { + os_err = os_copy_from_user(key, slot_info.key, + slot_info.key_length); + } + } + + if (os_err == OS_ERROR_OK_S) { + scc_ret = keystore_slot_decrypt(NULL, &system_keystore, + slot_info.ownerid, + slot_info.slot, + slot_info.key_length, key); + if (scc_ret == SCC_RET_OK) { + ret = FSL_RETURN_OK_S; + } else { + ret = FSL_RETURN_ERROR_S; + } + + slot_info.code = ret; + os_err = + os_copy_to_user((void *)info, &slot_info, + sizeof(slot_info)); + } + + if (key != NULL) { + memset(key, 0, slot_info.key_length); + os_free_memory(key); + } + + return os_err; +} + +/*! + * Register a user + * + * @brief Register a user + * + * @param user_ctx information about this user + * + * @return status code + */ +fsl_shw_return_t sah_handle_registration(fsl_shw_uco_t * user_ctx) +{ + /* Initialize the user's result pool (like sah_Queue_Construct() */ + user_ctx->result_pool.head = NULL; + user_ctx->result_pool.tail = NULL; + user_ctx->result_pool.count = 0; + + /* initialize the user's partition chain */ + user_ctx->partition = NULL; + + return FSL_RETURN_OK_S; +} + +/*! + * Deregister a user + * + * @brief Deregister a user + * + * @param user_ctx information about this user + * + * @return status code + */ +fsl_shw_return_t sah_handle_deregistration(fsl_shw_uco_t * user_ctx) +{ + /* NOTE: + * This will release any secure partitions that are held by the user. + * Encryption keys that were placed in the system keystore by the user + * should not be removed here, because they might have been shared with + * another process. The user must be careful to release any that are no + * longer in use. + */ + fsl_shw_return_t ret = FSL_RETURN_OK_S; + +#ifdef FSL_HAVE_SCC2 + fsl_shw_spo_t *partition; + struct mm_struct *mm = current->mm; + + while ((user_ctx->partition != NULL) && (ret == FSL_RETURN_OK_S)) { + + partition = user_ctx->partition; + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("Found an abandoned secure partition at %p, releasing", + partition); +#endif + + /* It appears that current->mm is not valid if this is called from a + * close routine (perhaps only if the program raised an exception that + * caused it to close?) If that is the case, then still free the + * partition, but do not remove it from the memory space (dangerous?) + */ + + if (mm == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("Warning: no mm structure found, not unmapping " + "partition from user memory\n"); +#endif + } else { + /* Unmap the memory region (see sys_munmap in mmap.c) */ + /* Note that this assumes a single memory partition */ + unmap_user_memory(partition->user_base, 8192); + } + + /* If the memory was successfully released */ + if (ret == OS_ERROR_OK_S) { + /* release the partition */ + scc_release_partition(partition->kernel_base); + + /* and remove it from the users context */ + deregister_user_partition(user_ctx, + partition->user_base); + + ret = FSL_RETURN_OK_S; + } else { + ret = FSL_RETURN_ERROR_S; + + goto out; + } + } + out: +#endif /* FSL_HAVE_SCC2 */ + + return ret; +} + +/*! + * Sets up memory to extract results from results pool + * + * @brief Sets up memory to extract results from results pool + * + * @param user_ctx information about this user + * @param[in,out] arg contains input parameters and fields that the driver + * fills in + * + * @return os error code or 0 on success + */ +int sah_get_results_pointers(fsl_shw_uco_t * user_ctx, uint32_t arg) +{ + sah_results results_arg; /* kernel mode usable version of 'arg' */ + fsl_shw_result_t *user_results; /* user mode address of results */ + unsigned *user_actual; /* user mode address of actual number of results */ + unsigned actual; /* local memory of actual number of results */ + int ret_val = OS_ERROR_FAIL_S; + sah_Head_Desc *finished_request; + unsigned int loop; + + /* copy structure from user to kernel space */ + if (!os_copy_from_user(&results_arg, (void *)arg, sizeof(sah_results))) { + /* save user space pointers */ + user_actual = results_arg.actual; /* where count goes */ + user_results = results_arg.results; /* where results goe */ + + /* Set pointer for actual value to temporary kernel memory location */ + results_arg.actual = &actual; + + /* Allocate kernel memory to hold temporary copy of the results */ + results_arg.results = + os_alloc_memory(sizeof(fsl_shw_result_t) * + results_arg.requested, GFP_KERNEL); + + /* if memory allocated, continue */ + if (results_arg.results == NULL) { + ret_val = OS_ERROR_NO_MEMORY_S; + } else { + fsl_shw_return_t get_status; + + /* get the results */ + get_status = + sah_get_results_from_pool(user_ctx, &results_arg); + + /* free the copy of the user space descriptor chain */ + for (loop = 0; loop < actual; ++loop) { + /* get sah_Head_Desc from results and put user address into + * the return structure */ + finished_request = + results_arg.results[loop].user_desc; + results_arg.results[loop].user_desc = + finished_request->user_desc; + /* return the descriptor chain memory to the block free pool */ + sah_Free_Chained_Descriptors(finished_request); + } + + /* if no errors, copy results and then the actual number of results + * back to user space + */ + if (get_status == FSL_RETURN_OK_S) { + if (os_copy_to_user + (user_results, results_arg.results, + actual * sizeof(fsl_shw_result_t)) + || os_copy_to_user(user_actual, &actual, + sizeof(user_actual))) { + ret_val = OS_ERROR_FAIL_S; + } else { + ret_val = 0; /* no error */ + } + } + /* free the allocated memory */ + os_free_memory(results_arg.results); + } + } + + return ret_val; +} + +/*! + * Extracts results from results pool + * + * @brief Extract results from results pool + * + * @param user_ctx information about this user + * @param[in,out] arg contains input parameters and fields that the + * driver fills in + * + * @return status code + */ +fsl_shw_return_t sah_get_results_from_pool(volatile fsl_shw_uco_t * user_ctx, + sah_results * arg) +{ + sah_Head_Desc *finished_request; + unsigned int loop = 0; + os_lock_context_t int_flags; + + /* Get the number of results requested, up to total number of results + * available + */ + do { + /* Protect state of user's result pool until we have retrieved and + * remove the first entry, or determined that the pool is empty. */ + os_lock_save_context(desc_queue_lock, int_flags); + finished_request = user_ctx->result_pool.head; + + if (finished_request != NULL) { + sah_Queue_Remove_Entry((sah_Queue *) & user_ctx-> + result_pool); + os_unlock_restore_context(desc_queue_lock, int_flags); + + /* Prepare to free. */ + (void)sah_DePhysicalise_Descriptors(finished_request); + + arg->results[loop].user_ref = + finished_request->user_ref; + arg->results[loop].code = finished_request->result; + arg->results[loop].detail1 = + finished_request->fault_address; + arg->results[loop].detail2 = 0; + arg->results[loop].user_desc = finished_request; + + loop++; + } else { /* finished_request is NULL */ + /* pool is empty */ + os_unlock_restore_context(desc_queue_lock, int_flags); + } + + } while ((loop < arg->requested) && (finished_request != NULL)); + + /* record number of results actually obtained */ + *arg->actual = loop; + + return FSL_RETURN_OK_S; +} + +/*! + * Converts descriptor chain to kernel space (from user space) and submits + * chain to Sahara for processing + * + * @brief Submits converted descriptor chain to sahara + * + * @param user_ctx Pointer to Kernel version of user's ctx + * @param user_space_desc user space address of descriptor chain that is + * in user space + * + * @return OS status code + */ +static int handle_sah_ioctl_dar(fsl_shw_uco_t * user_ctx, + uint32_t user_space_desc) +{ + int os_error_code = OS_ERROR_FAIL_S; + sah_Head_Desc *desc_chain_head; /* chain in kernel - virtual address */ + + /* This will re-create the linked list so that the SAHARA hardware can + * DMA on it. + */ + desc_chain_head = sah_Copy_Descriptors(user_ctx, + (sah_Head_Desc *) + user_space_desc); + + if (desc_chain_head == NULL) { + /* We may have failed due to a -EFAULT as well, but we will return + * OS_ERROR_NO_MEMORY_S since either way it is a memory related + * failure. + */ + os_error_code = OS_ERROR_NO_MEMORY_S; + } else { + fsl_shw_return_t stat; + + desc_chain_head->user_info = user_ctx; + desc_chain_head->user_desc = (sah_Head_Desc *) user_space_desc; + + if (desc_chain_head->uco_flags & FSL_UCO_BLOCKING_MODE) { +#ifdef SAHARA_POLL_MODE + sah_Handle_Poll(desc_chain_head); +#else + sah_blocking_mode(desc_chain_head); +#endif + stat = desc_chain_head->result; + /* return the descriptor chain memory to the block free pool */ + sah_Free_Chained_Descriptors(desc_chain_head); + /* Tell user how the call turned out */ + + /* Copy 'result' back up to the result member. + * + * The dereference of the different member will cause correct the + * arithmetic to occur on the user-space address because of the + * missing dma/bus locations in the user mode version of the + * sah_Desc structure. */ + os_error_code = + os_copy_to_user((void *)(user_space_desc + + offsetof(sah_Head_Desc, + uco_flags)), + &stat, sizeof(fsl_shw_return_t)); + + } else { /* not blocking mode - queue and forget */ + + if (desc_chain_head->uco_flags & FSL_UCO_CALLBACK_MODE) { + user_ctx->process = os_get_process_handle(); + user_ctx->callback = sah_user_callback; + } +#ifdef SAHARA_POLL_MODE + /* will put results in result pool */ + sah_Handle_Poll(desc_chain_head); +#else + /* just put someting in the DAR */ + sah_Queue_Manager_Append_Entry(desc_chain_head); +#endif + /* assume all went well */ + os_error_code = OS_ERROR_OK_S; + } + } + + return os_error_code; +} + +static void sah_user_callback(fsl_shw_uco_t * user_ctx) +{ + os_send_signal(user_ctx->process, SIGUSR2); +} + +/*! + * This function is called when a thread attempts to read from the /proc/sahara + * file. Upon read, statistics and information about the state of the driver + * are returned in nthe supplied buffer. + * + * @brief SAHARA PROCFS read function. + * + * @param buf Anything written to this buffer will be returned to the + * user-space process that is reading from this proc entry. + * @param start Part of the kernel prototype. + * @param offset Part of the kernel prototype. + * @param count The size of the buf argument. + * @param eof An integer which is set to one to tell the user-space + * process that there is no more data to read. + * @param data Part of the kernel prototype. + * + * @return The number of bytes written to the proc entry. + */ +#if !defined(CONFIG_DEVFS_FS) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) +static int sah_read_procfs(char *buf, + char **start, + off_t offset, int count, int *eof, void *data) +{ + int output_bytes = 0; + int in_queue_count = 0; + os_lock_context_t lock_context; + + os_lock_save_context(desc_queue_lock, lock_context); + in_queue_count = sah_Queue_Manager_Count_Entries(TRUE, 0); + os_unlock_restore_context(desc_queue_lock, lock_context); + output_bytes += snprintf(buf, count - output_bytes, "queued: %d\n", + in_queue_count); + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "Descriptors: %d, " + "Interrupts %d (%d Done1Done2, %d Done1Busy2, " + " %d Done1)\n", + dar_count, interrupt_count, done1done2_count, + done1busy2_count, done1_count); + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "Control: %08x\n", sah_HW_Read_Control()); +#if !defined(FSL_HAVE_SAHARA4) || defined(SAHARA4_NO_USE_SQUIB) + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "IDAR: %08x; CDAR: %08x\n", + sah_HW_Read_IDAR(), sah_HW_Read_CDAR()); +#endif +#ifdef DIAG_DRV_STATUS + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "Status: %08x; Error Status: %08x; Op Status: %08x\n", + sah_HW_Read_Status(), + sah_HW_Read_Error_Status(), + sah_HW_Read_Op_Status()); +#endif +#ifdef FSL_HAVE_SAHARA4 + output_bytes += snprintf(buf + output_bytes, count - output_bytes, + "MMStat: %08x; Config: %08x\n", + sah_HW_Read_MM_Status(), sah_HW_Read_Config()); +#endif + + /* Signal the end of the file */ + *eof = 1; + + /* To get rid of the unused parameter warnings */ + (void)start; + (void)data; + (void)offset; + + return output_bytes; +} + +static int sah_write_procfs(struct file *file, const char __user * buffer, + unsigned long count, void *data) +{ + + /* Any write to this file will reset all counts. */ + dar_count = interrupt_count = done1done2_count = + done1busy2_count = done1_count = 0; + + (void)file; + (void)buffer; + (void)data; + + return count; +} + +#endif + +#ifndef SAHARA_POLL_MODE +/*! + * Block user call until processing is complete. + * + * @param entry The user's request. + * + * @return An OS error code, or 0 if no error + */ +int sah_blocking_mode(sah_Head_Desc * entry) +{ + int os_error_code = 0; + sah_Queue_Status status; + + /* queue entry, put something in the DAR, if nothing is there currently */ + sah_Queue_Manager_Append_Entry(entry); + + /* get this descriptor chain's current status */ + status = ((volatile sah_Head_Desc *)entry)->status; + + while (!SAH_DESC_PROCESSED(status)) { + extern sah_Queue *main_queue; + + DEFINE_WAIT(sahara_wait); /* create a wait queue entry. Linux */ + + /* enter the wait queue entry into the queue */ + prepare_to_wait(&Wait_queue, &sahara_wait, TASK_INTERRUPTIBLE); + + /* check if this entry has been processed */ + status = ((volatile sah_Head_Desc *)entry)->status; + + if (!SAH_DESC_PROCESSED(status)) { + /* go to sleep - Linux */ + schedule(); + } + + /* un-queue the 'prepare to wait' queue? - Linux */ + finish_wait(&Wait_queue, &sahara_wait); + + /* signal belongs to this thread? */ + if (signal_pending(current)) { /* Linux */ + os_lock_context_t lock_flags; + + /* don't allow access during this check and operation */ + os_lock_save_context(desc_queue_lock, lock_flags); + status = ((volatile sah_Head_Desc *)entry)->status; + if (status == SAH_STATE_PENDING) { + sah_Queue_Remove_Any_Entry(main_queue, entry); + entry->result = FSL_RETURN_INTERNAL_ERROR_S; + ((volatile sah_Head_Desc *)entry)->status = + SAH_STATE_FAILED; + } + os_unlock_restore_context(desc_queue_lock, lock_flags); + } + + status = ((volatile sah_Head_Desc *)entry)->status; + } /* while ... */ + + /* Do this so that caller can free */ + (void)sah_DePhysicalise_Descriptors(entry); + + return os_error_code; +} + +/*! + * If interrupt does not return in a reasonable time, time out, trigger + * interrupt, and continue with process + * + * @param data ignored + */ +void sahara_timeout_handler(unsigned long data) +{ + /* Sahara has not issuing an interrupt, so timed out */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("Sahara HW did not respond. Resetting.\n"); +#endif + /* assume hardware needs resetting */ + sah_Handle_Interrupt(SAH_EXEC_FAULT); + /* wake up sleeping thread to try again */ + wake_up_interruptible(&Wait_queue); +} + +#endif /* ifndef SAHARA_POLL_MODE */ + +/* End of sah_driver_interface.c */ diff --git a/drivers/mxc/security/sahara2/sah_hardware_interface.c b/drivers/mxc/security/sahara2/sah_hardware_interface.c new file mode 100644 index 000000000000..ff3cb987dc7f --- /dev/null +++ b/drivers/mxc/security/sahara2/sah_hardware_interface.c @@ -0,0 +1,808 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sah_hardware_interface.c + * + * @brief Provides an interface to the SAHARA hardware registers. + * + */ + +/* SAHARA Includes */ +#include +#include +#include +#include + +#if defined DIAG_DRV_IF || defined(DO_DBG) +#include +#ifndef LOG_KDIAG +#define LOG_KDIAG(x) os_printk("%s\n", x) +#endif + +static void sah_Dump_Link(const char *prefix, const sah_Link * link, + dma_addr_t addr); + +/* This is for sprintf() to use when constructing output. */ +#define DIAG_MSG_SIZE 1024 +/* was 200 */ +#define MAX_DUMP 200 +static char Diag_msg[DIAG_MSG_SIZE]; + +#endif /* DIAG_DRV_IF */ + +/*! + * Number of descriptors sent to Sahara. This value should only be updated + * with the main queue lock held. + */ +uint32_t dar_count; + +/* sahara virtual base address */ +void *sah_virt_base; + +/*! The "link-list optimize" bit in the Header of a Descriptor */ +#define SAH_HDR_LLO 0x01000000 + +#define SAHARA_VERSION_REGISTER_OFFSET 0x000 +#define SAHARA_DAR_REGISTER_OFFSET 0x004 +#define SAHARA_CONTROL_REGISTER_OFFSET 0x008 +#define SAHARA_COMMAND_REGISTER_OFFSET 0x00C +#define SAHARA_STATUS_REGISTER_OFFSET 0x010 +#define SAHARA_ESTATUS_REGISTER_OFFSET 0x014 +#define SAHARA_FLT_ADD_REGISTER_OFFSET 0x018 +#define SAHARA_CDAR_REGISTER_OFFSET 0x01C +#define SAHARA_IDAR_REGISTER_OFFSET 0x020 +#define SAHARA_OSTATUS_REGISTER_OFFSET 0x028 +#define SAHARA_CONFIG_REGISTER_OFFSET 0x02C +#define SAHARA_MM_STAT_REGISTER_OFFSET 0x030 + + +/* Local Functions */ +#if defined DIAG_DRV_IF || defined DO_DBG +void sah_Dump_Region(const char *prefix, const unsigned char *data, + dma_addr_t addr, unsigned length); + +#endif /* DIAG_DRV_IF */ + +/* time out value when polling SAHARA status register for completion */ +static uint32_t sah_poll_timeout = 0xFFFFFFFF; + +/*! + * Polls Sahara to determine when its current operation is complete + * + * @return last value found in Sahara's status register + */ +sah_Execute_Status sah_Wait_On_Sahara() +{ + uint32_t count = 0; /* ensure we don't get stuck in the loop forever */ + sah_Execute_Status status; /* Sahara's status register */ + uint32_t stat_reg; + + pr_debug("Entered sah_Wait_On_Sahara\n"); + + do { + /* get current status register from Sahara */ + stat_reg = sah_HW_Read_Status(); + status = stat_reg & SAH_EXEC_STATE_MASK; + + /* timeout if SAHARA takes too long to complete */ + if (++count == sah_poll_timeout) { + status = SAH_EXEC_FAULT; + printk("sah_Wait_On_Sahara timed out\n"); + } + + /* stay in loop as long as Sahara is still busy */ + } while ((status == SAH_EXEC_BUSY) || (status == SAH_EXEC_DONE1_BUSY2)); + + if (status == SAH_EXEC_ERROR1) { + if (stat_reg & OP_STATUS) { + status = SAH_EXEC_OPSTAT1; + } + } + + return status; +} /* sah_Wait_on_Sahara() */ + +/*! + * This function resets the SAHARA hardware. The following operations are + * performed: + * 1. Resets SAHARA. + * 2. Requests BATCH mode. + * 3. Enables interrupts. + * 4. Requests Little Endian mode. + * + * @brief SAHARA hardware reset function. + * + * @return void + */ +int sah_HW_Reset(void) +{ + sah_Execute_Status sah_state; + int status; /* this is the value to return to the calling routine */ + uint32_t saha_control = 0; + +#ifndef USE_3WORD_BURST +#ifdef FSL_HAVE_SAHARA2 + saha_control |= (8 << 16); /* Allow 8-word burst */ +#endif +#else +/***************** HARDWARE BUG WORK AROUND ******************/ +/* A burst size of > 4 can cause Sahara DMA to issue invalid AHB transactions + * when crossing 1KB boundaries. By limiting the 'burst size' to 3, these + * invalid transactions will not be generated, but Sahara will still transfer + * data more efficiently than if the burst size were set to 1. + */ + saha_control |= (3 << 16); /* Limit DMA burst size. For versions 2/3 */ +#endif /* USE_3WORD_BURST */ + +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Address of sah_virt_base = 0x%08x\n", + sah_virt_base); + LOG_KDIAG(Diag_msg); + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Sahara Status register before reset: %08x", + sah_HW_Read_Status()); + LOG_KDIAG(Diag_msg); +#endif + + /* Write the Reset & BATCH mode command to the SAHARA Command register. */ + sah_HW_Write_Command(CMD_BATCH | CMD_RESET); +#ifdef SAHARA4_NO_USE_SQUIB + { + uint32_t cfg = sah_HW_Read_Config(); + cfg &= ~0x10000; + sah_HW_Write_Config(cfg); + } +#endif + + sah_poll_timeout = 0x0FFFFFFF; + sah_state = sah_Wait_On_Sahara(); +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Sahara Status register after reset: %08x", + sah_HW_Read_Status()); + LOG_KDIAG(Diag_msg); +#endif + /* on reset completion, check that Sahara is in the idle state */ + status = (sah_state == SAH_EXEC_IDLE) ? 0 : OS_ERROR_FAIL_S; + + /* Set initial value out of reset */ + sah_HW_Write_Control(saha_control); + +#ifndef NO_RESEED_WORKAROUND +/***************** HARDWARE BUG WORK AROUND ******************/ +/* In order to set the 'auto reseed' bit, must first acquire a random value. */ + /* + * to solve a hardware bug, a random number must be generated before + * the 'RNG Auto Reseed' bit can be set. So this generates a random + * number that is thrown away. + * + * Note that the interrupt bit has not been set at this point so + * the result can be polled. + */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("Create and submit Random Number Descriptor"); +#endif + + if (status == OS_ERROR_OK_S) { + /* place to put random number */ + volatile uint32_t *random_data_ptr; + sah_Head_Desc *random_desc; + dma_addr_t desc_dma; + dma_addr_t rand_dma; + const int rnd_cnt = 3; /* how many random 32-bit values to get */ + + /* Get space for data -- assume at least 32-bit aligned! */ + random_data_ptr = os_alloc_memory(rnd_cnt * sizeof(uint32_t), + GFP_ATOMIC); + + random_desc = sah_Alloc_Head_Descriptor(); + + if ((random_data_ptr == NULL) || (random_desc == NULL)) { + status = OS_ERROR_FAIL_S; + } else { + int i; + + /* Clear out values */ + for (i = 0; i < rnd_cnt; i++) { + random_data_ptr[i] = 0; + } + + rand_dma = os_pa(random_data_ptr); + + random_desc->desc.header = 0xB18C0000; /* LLO get random number */ + random_desc->desc.len1 = + rnd_cnt * sizeof(*random_data_ptr); + random_desc->desc.ptr1 = (void *)rand_dma; + random_desc->desc.original_ptr1 = + (void *)random_data_ptr; + + random_desc->desc.len2 = 0; /* not used */ + random_desc->desc.ptr2 = 0; /* not used */ + + random_desc->desc.next = 0; /* chain terminates here */ + random_desc->desc.original_next = 0; /* chain terminates here */ + + desc_dma = random_desc->desc.dma_addr; + + /* Force in-cache data out to RAM */ + os_cache_clean_range(random_data_ptr, + rnd_cnt * + sizeof(*random_data_ptr)); + + /* pass descriptor to Sahara */ + sah_HW_Write_DAR(desc_dma); + + /* + * Wait for RNG to complete (interrupts are disabled at this point + * due to sahara being reset previously) then check for error + */ + sah_state = sah_Wait_On_Sahara(); + /* Force CPU to ignore in-cache and reload from RAM */ + os_cache_inv_range(random_data_ptr, + rnd_cnt * sizeof(*random_data_ptr)); + + /* if it didn't move to done state, an error occured */ + if ( +#ifndef SUBMIT_MULTIPLE_DARS + (sah_state != SAH_EXEC_IDLE) && +#endif + (sah_state != SAH_EXEC_DONE1) + ) { + status = OS_ERROR_FAIL_S; + os_printk + ("(sahara) Failure: state is %08x; random_data is" + " %08x\n", sah_state, *random_data_ptr); + os_printk + ("(sahara) CDAR: %08x, IDAR: %08x, FADR: %08x," + " ESTAT: %08x\n", sah_HW_Read_CDAR(), + sah_HW_Read_IDAR(), + sah_HW_Read_Fault_Address(), + sah_HW_Read_Error_Status()); + } else { + int i; + int seen_rand = 0; + + for (i = 0; i < rnd_cnt; i++) { + if (*random_data_ptr != 0) { + seen_rand = 1; + break; + } + } + if (!seen_rand) { + status = OS_ERROR_FAIL_S; + os_printk + ("(sahara) Error: Random number is zero!\n"); + } + } + } + + if (random_data_ptr) { + os_free_memory((void *)random_data_ptr); + } + if (random_desc) { + sah_Free_Head_Descriptor(random_desc); + } + } +/***************** END HARDWARE BUG WORK AROUND ******************/ +#endif + + if (status == 0) { +#ifdef FSL_HAVE_SAHARA2 + saha_control |= CTRL_RNG_RESEED; +#endif + +#ifndef SAHARA_POLL_MODE + saha_control |= CTRL_INT_EN; /* enable interrupts */ +#else + sah_poll_timeout = SAHARA_POLL_MODE_TIMEOUT; +#endif + +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Setting up Sahara's Control Register: %08x\n", + saha_control); + LOG_KDIAG(Diag_msg); +#endif + + /* Rewrite the setup to the SAHARA Control register */ + sah_HW_Write_Control(saha_control); +#ifdef DIAG_DRV_IF + snprintf(Diag_msg, DIAG_MSG_SIZE, + "Sahara Status register after control write: %08x", + sah_HW_Read_Status()); + LOG_KDIAG(Diag_msg); +#endif + +#ifdef FSL_HAVE_SAHARA4 + { + uint32_t cfg = sah_HW_Read_Config(); + sah_HW_Write_Config(cfg | 0x100); /* Add RNG auto-reseed */ + } +#endif + } else { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Reset failed\n"); +#endif + } + + return status; +} /* sah_HW_Reset() */ + +/*! + * This function enables High Assurance mode. + * + * @brief SAHARA hardware enable High Assurance mode. + * + * @return FSL_RETURN_OK_S - if HA was set successfully + * @return FSL_RETURN_INTERNAL_ERROR_S - if HA was not set due to SAHARA + * being busy. + */ +fsl_shw_return_t sah_HW_Set_HA(void) +{ + /* This is the value to write to the register */ + uint32_t value; + + /* Read from the control register. */ + value = sah_HW_Read_Control(); + + /* Set the HA bit */ + value |= CTRL_HA; + + /* Write to the control register. */ + sah_HW_Write_Control(value); + + /* Read from the control register. */ + value = sah_HW_Read_Control(); + + return (value & CTRL_HA) ? FSL_RETURN_OK_S : + FSL_RETURN_INTERNAL_ERROR_S; +} + +/*! + * This function reads the SAHARA hardware Version Register. + * + * @brief Read SAHARA hardware Version Register. + * + * @return uint32_t Register value. + */ +uint32_t sah_HW_Read_Version(void) +{ + return os_read32(sah_virt_base + SAHARA_VERSION_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Control Register. + * + * @brief Read SAHARA hardware Control Register. + * + * @return uint32_t Register value. + */ +uint32_t sah_HW_Read_Control(void) +{ + return os_read32(sah_virt_base + SAHARA_CONTROL_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Status Register. + * + * @brief Read SAHARA hardware Status Register. + * + * @return uint32_t Register value. + */ +uint32_t sah_HW_Read_Status(void) +{ + return os_read32(sah_virt_base + SAHARA_STATUS_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Error Status Register. + * + * @brief Read SAHARA hardware Error Status Register. + * + * @return uint32_t Error Status value. + */ +uint32_t sah_HW_Read_Error_Status(void) +{ + return os_read32(sah_virt_base + SAHARA_ESTATUS_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Op Status Register. + * + * @brief Read SAHARA hardware Op Status Register. + * + * @return uint32_t Op Status value. + */ +uint32_t sah_HW_Read_Op_Status(void) +{ + return os_read32(sah_virt_base + SAHARA_OSTATUS_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Descriptor Address Register. + * + * @brief Read SAHARA hardware DAR Register. + * + * @return uint32_t DAR value. + */ +uint32_t sah_HW_Read_DAR(void) +{ + return os_read32(sah_virt_base + SAHARA_DAR_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Current Descriptor Address Register. + * + * @brief Read SAHARA hardware CDAR Register. + * + * @return uint32_t CDAR value. + */ +uint32_t sah_HW_Read_CDAR(void) +{ + return os_read32(sah_virt_base + SAHARA_CDAR_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Initial Descriptor Address Register. + * + * @brief Read SAHARA hardware IDAR Register. + * + * @return uint32_t IDAR value. + */ +uint32_t sah_HW_Read_IDAR(void) +{ + return os_read32(sah_virt_base + SAHARA_IDAR_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Fault Address Register. + * + * @brief Read SAHARA Fault Address Register. + * + * @return uint32_t Fault Address value. + */ +uint32_t sah_HW_Read_Fault_Address(void) +{ + return os_read32(sah_virt_base + SAHARA_FLT_ADD_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Multiple Master Status Register. + * + * @brief Read SAHARA hardware MM Stat Register. + * + * @return uint32_t MM Stat value. + */ +uint32_t sah_HW_Read_MM_Status(void) +{ + return os_read32(sah_virt_base + SAHARA_MM_STAT_REGISTER_OFFSET); +} + +/*! + * This function reads the SAHARA hardware Configuration Register. + * + * @brief Read SAHARA Configuration Register. + * + * @return uint32_t Configuration value. + */ +uint32_t sah_HW_Read_Config(void) +{ + return os_read32(sah_virt_base + SAHARA_CONFIG_REGISTER_OFFSET); +} + +/*! + * This function writes a command to the SAHARA hardware Command Register. + * + * @brief Write to SAHARA hardware Command Register. + * + * @param command An unsigned 32bit command value. + * + * @return void + */ +void sah_HW_Write_Command(uint32_t command) +{ + os_write32(sah_virt_base + SAHARA_COMMAND_REGISTER_OFFSET, command); +} + +/*! + * This function writes a control value to the SAHARA hardware Control + * Register. + * + * @brief Write to SAHARA hardware Control Register. + * + * @param control An unsigned 32bit control value. + * + * @return void + */ +void sah_HW_Write_Control(uint32_t control) +{ + os_write32(sah_virt_base + SAHARA_CONTROL_REGISTER_OFFSET, control); +} + +/*! + * This function writes a configuration value to the SAHARA hardware Configuration + * Register. + * + * @brief Write to SAHARA hardware Configuration Register. + * + * @param configuration An unsigned 32bit configuration value. + * + * @return void + */ +void sah_HW_Write_Config(uint32_t configuration) +{ + os_write32(sah_virt_base + SAHARA_CONFIG_REGISTER_OFFSET, + configuration); +} + +/*! + * This function writes a descriptor address to the SAHARA Descriptor Address + * Register. + * + * @brief Write to SAHARA Descriptor Address Register. + * + * @param pointer An unsigned 32bit descriptor address value. + * + * @return void + */ +void sah_HW_Write_DAR(uint32_t pointer) +{ + os_write32(sah_virt_base + SAHARA_DAR_REGISTER_OFFSET, pointer); + dar_count++; +} + +#if defined DIAG_DRV_IF || defined DO_DBG + +static char *interpret_header(uint32_t header) +{ + unsigned desc_type = ((header >> 24) & 0x70) | ((header >> 16) & 0xF); + + switch (desc_type) { + case 0x12: + return "5/SKHA_ST_CTX"; + case 0x13: + return "35/SKHA_LD_MODE_KEY"; + case 0x14: + return "38/SKHA_LD_MODE_IN_CPHR_ST_CTX"; + case 0x15: + return "4/SKHA_IN_CPHR_OUT"; + case 0x16: + return "34/SKHA_ST_SBOX"; + case 0x18: + return "1/SKHA_LD_MODE_IV_KEY"; + case 0x19: + return "33/SKHA_ST_SBOX"; + case 0x1D: + return "2/SKHA_LD_MODE_IN_CPHR_OUT"; + case 0x22: + return "11/MDHA_ST_MD"; + case 0x25: + return "10/MDHA_HASH_ST_MD"; + case 0x28: + return "6/MDHA_LD_MODE_MD_KEY"; + case 0x2A: + return "39/MDHA_ICV"; + case 0x2D: + return "8/MDHA_LD_MODE_HASH_ST_MD"; + case 0x3C: + return "18/RNG_GEN"; + case 0x40: + return "19/PKHA_LD_N_E"; + case 0x41: + return "36/PKHA_LD_A3_B0"; + case 0x42: + return "27/PKHA_ST_A_B"; + case 0x43: + return "22/PKHA_LD_A_B"; + case 0x44: + return "23/PKHA_LD_A0_A1"; + case 0x45: + return "24/PKHA_LD_A2_A3"; + case 0x46: + return "25/PKHA_LD_B0_B1"; + case 0x47: + return "26/PKHA_LD_B2_B3"; + case 0x48: + return "28/PKHA_ST_A0_A1"; + case 0x49: + return "29/PKHA_ST_A2_A3"; + case 0x4A: + return "30/PKHA_ST_B0_B1"; + case 0x4B: + return "31/PKHA_ST_B2_B3"; + case 0x4C: + return "32/PKHA_EX_ST_B1"; + case 0x4D: + return "20/PKHA_LD_A_EX_ST_B"; + case 0x4E: + return "21/PKHA_LD_N_EX_ST_B"; + case 0x4F: + return "37/PKHA_ST_B1_B2"; + default: + return "??/UNKNOWN"; + } +} /* cvt_desc_name() */ + +/*! + * Dump chain of descriptors to the log. + * + * @brief Dump descriptor chain + * + * @param chain Kernel virtual address of start of chain of descriptors + * + * @return void + */ +void sah_Dump_Chain(const sah_Desc * chain, dma_addr_t addr) +{ + int desc_no = 1; + + pr_debug("Chain for Sahara\n"); + + while (chain != NULL) { + char desc_name[50]; + + sprintf(desc_name, "Desc %02d (%s)\n" KERN_DEBUG "Desc ", + desc_no++, interpret_header(chain->header)); + + sah_Dump_Words(desc_name, (unsigned *)chain, addr, + 6 /* #words in h/w link */ ); + if (chain->original_ptr1) { + if (chain->header & SAH_HDR_LLO) { + sah_Dump_Region(" Data1", + (unsigned char *)chain-> + original_ptr1, + (dma_addr_t) chain->ptr1, + chain->len1); + } else { + sah_Dump_Link(" Link1", chain->original_ptr1, + (dma_addr_t) chain->ptr1); + } + } + if (chain->ptr2) { + if (chain->header & SAH_HDR_LLO) { + sah_Dump_Region(" Data2", + (unsigned char *)chain-> + original_ptr2, + (dma_addr_t) chain->ptr2, + chain->len2); + } else { + sah_Dump_Link(" Link2", chain->original_ptr2, + (dma_addr_t) chain->ptr2); + } + } + + addr = (dma_addr_t) chain->next; + chain = (chain->next) ? (chain->original_next) : NULL; + } +} + +/*! + * Dump chain of links to the log. + * + * @brief Dump chain of links + * + * @param prefix Text to put in front of dumped data + * @param link Kernel virtual address of start of chain of links + * + * @return void + */ +static void sah_Dump_Link(const char *prefix, const sah_Link * link, + dma_addr_t addr) +{ +#ifdef DUMP_SCC_DATA + extern uint8_t *sahara_partition_base; + extern dma_addr_t sahara_partition_phys; +#endif + + while (link != NULL) { + sah_Dump_Words(prefix, (unsigned *)link, addr, + 3 /* # words in h/w link */ ); + if (link->flags & SAH_STORED_KEY_INFO) { +#ifdef SAH_DUMP_DATA +#ifdef DUMP_SCC_DATA + sah_Dump_Region(" Data", + (uint8_t *) link->data - + (uint8_t *) sahara_partition_phys + + sahara_partition_base, + (dma_addr_t) link->data, link->len); +#else + pr_debug(" Key Slot %d\n", link->slot); +#endif +#endif + } else { +#ifdef SAH_DUMP_DATA + sah_Dump_Region(" Data", link->original_data, + (dma_addr_t) link->data, link->len); +#endif + } + addr = (dma_addr_t) link->next; + link = link->original_next; + } +} + +/*! + * Dump given region of data to the log. + * + * @brief Dump data + * + * @param prefix Text to put in front of dumped data + * @param data Kernel virtual address of start of region to dump + * @param length Amount of data to dump + * + * @return void + */ +void sah_Dump_Region(const char *prefix, const unsigned char *data, + dma_addr_t addr, unsigned length) +{ + unsigned count; + char *output; + unsigned data_len; + + sprintf(Diag_msg, "%s (%08X,%u):", prefix, addr, length); + + /* Restrict amount of data to dump */ + if (length > MAX_DUMP) { + data_len = MAX_DUMP; + } else { + data_len = length; + } + + /* We've already printed some text in output buffer, skip over it */ + output = Diag_msg + strlen(Diag_msg); + + for (count = 0; count < data_len; count++) { + if ((count % 4) == 0) { + *output++ = ' '; + } + sprintf(output, "%02X", *data++); + output += 2; + } + + pr_debug("%s\n", Diag_msg); +} + +/*! + * Dump given word of data to the log. + * + * @brief Dump data + * + * @param prefix Text to put in front of dumped data + * @param data Kernel virtual address of start of region to dump + * @param word_count Amount of data to dump + * + * @return void + */ +void sah_Dump_Words(const char *prefix, const unsigned *data, dma_addr_t addr, + unsigned word_count) +{ + char *output; + + sprintf(Diag_msg, "%s (%08X,%uw): ", prefix, addr, word_count); + + /* We've already printed some text in output buffer, skip over it */ + output = Diag_msg + strlen(Diag_msg); + + while (word_count--) { + sprintf(output, "%08X ", *data++); + output += 9; + } + + pr_debug("%s\n", Diag_msg); + +} + +#endif /* DIAG_DRV_IF */ + +/* End of sah_hardware_interface.c */ diff --git a/drivers/mxc/security/sahara2/sah_interrupt_handler.c b/drivers/mxc/security/sahara2/sah_interrupt_handler.c new file mode 100644 index 000000000000..959c3d8cf7bb --- /dev/null +++ b/drivers/mxc/security/sahara2/sah_interrupt_handler.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_interrupt_handler.c +* +* @brief Provides a hardware interrupt handling mechanism for device driver. +* +* This file needs to be ported for a non-Linux OS. +* +* It gets a call at #sah_Intr_Init() during initialization. +* +* #sah_Intr_Top_Half() is intended to be the Interrupt Service Routine. It +* calls a portable function in another file to process the Sahara status. +* +* #sah_Intr_Bottom_Half() is a 'background' task scheduled by the top half to +* take care of the expensive tasks of the interrupt processing. +* +* The driver shutdown code calls #sah_Intr_Release(). +* +*/ + +#include + +/* SAHARA Includes */ +#include +#include +#include +#include +#include + +/*Enable this flag for debugging*/ +#if 0 +#define DIAG_DRV_INTERRUPT +#endif + +#ifdef DIAG_DRV_INTERRUPT +#include +#endif + +/*! + * Number of interrupts received. This value should only be updated during + * interrupt processing. + */ +uint32_t interrupt_count; + +#ifndef SAHARA_POLL_MODE + +#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#define irqreturn_t void +#define IRQ_HANDLED +#define IRQ_RETVAL(x) +#endif + +/* Internal Prototypes */ +static irqreturn_t sah_Intr_Top_Half(int irq, void *dev_id); + +#ifdef KERNEL_TEST +extern void (*SAHARA_INT_PTR) (int, void *); +#endif + +unsigned long reset_flag; +static void sah_Intr_Bottom_Half(unsigned long reset_flag); + +/* This is the Bottom Half Task, (reset flag set to false) */ +DECLARE_TASKLET(BH_task, sah_Intr_Bottom_Half, (unsigned long)&reset_flag); + +/*! This is set by the Initialisation function */ +wait_queue_head_t *int_queue = NULL; + +/*! +******************************************************************************* +* This function registers the Top Half of the interrupt handler with the Kernel +* and the SAHARA IRQ number. +* +* @brief SAHARA Interrupt Handler Initialisation +* +* @param wait_queue Pointer to the wait queue used by driver interface +* +* @return int A return of Zero indicates successful initialisation. +*/ +/****************************************************************************** +* +* CAUTION: NONE +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 30/07/2003 MW Initial Creation +******************************************************************************/ +int sah_Intr_Init(wait_queue_head_t * wait_queue) +{ + +#ifdef DIAG_DRV_INTERRUPT + char err_string[200]; +#endif + + int result; + +#ifdef KERNEL_TEST + SAHARA_INT_PTR = sah_Intr_Top_Half; +#endif + + /* Set queue used by the interrupt handler to match the driver interface */ + int_queue = wait_queue; + + /* Request use of the Interrupt line. */ + result = request_irq(SAHARA_IRQ, + sah_Intr_Top_Half, 0, SAHARA_NAME, NULL); + +#ifdef DIAG_DRV_INTERRUPT + if (result != 0) { + sprintf(err_string, "Cannot use SAHARA interrupt line %d. " + "request_irq() return code is %i.", SAHARA_IRQ, result); + LOG_KDIAG(err_string); + } else { + sprintf(err_string, + "SAHARA driver registered for interrupt %d. ", + SAHARA_IRQ); + LOG_KDIAG(err_string); + } +#endif + + return result; +} + +/*! +******************************************************************************* +* This function releases the Top Half of the interrupt handler. The driver will +* not receive any more interrupts after calling this functions. +* +* @brief SAHARA Interrupt Handler Release +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: NONE +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 30/07/2003 MW Initial Creation +******************************************************************************/ +void sah_Intr_Release(void) +{ + /* Release the Interrupt. */ + free_irq(SAHARA_IRQ, NULL); +} + +/*! +******************************************************************************* +* This function is the Top Half of the interrupt handler. It updates the +* status of any finished descriptor chains and then tries to add any pending +* requests into the hardware. It then queues the bottom half to complete +* operations on the finished chains. +* +* @brief SAHARA Interrupt Handler Top Half +* +* @param irq Part of the kernel prototype. +* @param dev_id Part of the kernel prototype. +* +* @return An IRQ_RETVAL() -- non-zero to that function means 'handled' +*/ +static irqreturn_t sah_Intr_Top_Half(int irq, void *dev_id) +{ +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + LOG_KDIAG("Top half of Sahara's interrupt handler called."); +#endif + + interrupt_count++; + reset_flag = sah_Handle_Interrupt(sah_HW_Read_Status()); + + /* Schedule the Bottom Half of the Interrupt. */ + tasklet_schedule(&BH_task); + + /* To get rid of the unused parameter warnings. */ + irq = 0; + dev_id = NULL; + return IRQ_RETVAL(1); +} + +/*! +******************************************************************************* +* This function is the Bottom Half of the interrupt handler. It calls +* #sah_postprocess_queue() to complete the processing of the Descriptor Chains +* which were finished by the hardware. +* +* @brief SAHARA Interrupt Handler Bottom Half +* +* @param data Part of the kernel prototype. +* +* @return void +*/ +static void sah_Intr_Bottom_Half(unsigned long reset_flag) +{ +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + LOG_KDIAG("Bottom half of Sahara's interrupt handler called."); +#endif + sah_postprocess_queue(*(unsigned long *)reset_flag); + + return; +} + +/* end of sah_interrupt_handler.c */ +#endif /* ifndef SAHARA_POLL_MODE */ diff --git a/drivers/mxc/security/sahara2/sah_memory_mapper.c b/drivers/mxc/security/sahara2/sah_memory_mapper.c new file mode 100644 index 000000000000..2e3b80b14873 --- /dev/null +++ b/drivers/mxc/security/sahara2/sah_memory_mapper.c @@ -0,0 +1,2356 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_memory_mapper.c +* +* @brief Re-creates SAHARA data structures in Kernel memory such that they are +* suitable for DMA. Provides support for kernel API. +* +* This file needs to be ported. +* +* The memory mapper gets a call at #sah_Init_Mem_Map() during driver +* initialization. +* +* The routine #sah_Copy_Descriptors() is used to bring descriptor chains from +* user memory down to kernel memory, relink using physical addresses, and make +* sure that all user data will be accessible by the Sahara DMA. +* #sah_Destroy_Descriptors() does the inverse. +* +* The #sah_Alloc_Block(), #sah_Free_Block(), and #sah_Block_Add_Page() routines +* implement a cache of free blocks used when allocating descriptors and links +* within the kernel. +* +* The memory mapper gets a call at #sah_Stop_Mem_Map() during driver shutdown. +* +*/ + +#include +#include +#include +#include +#ifdef FSL_HAVE_SCC2 +#include +#else +#include +#endif + +#if defined(DIAG_DRV_IF) || defined(DIAG_MEM) || defined(DO_DBG) +#include +#include +#endif + +#include /* get_user_pages() */ +#include +#include + +#include +#include + +#if defined(DIAG_MEM) || defined(DIAG_DRV_IF) +#define DIAG_MSG_SIZE 1024 +static char Diag_msg[DIAG_MSG_SIZE]; +#endif + +#ifdef LINUX_VERSION_CODE +#define FLUSH_SPECIFIC_DATA_ONLY +#else +#define SELF_MANAGED_POOL +#endif + +#if defined(LINUX_VERSION_CODE) +EXPORT_SYMBOL(sah_Alloc_Link); +EXPORT_SYMBOL(sah_Free_Link); +EXPORT_SYMBOL(sah_Alloc_Descriptor); +EXPORT_SYMBOL(sah_Free_Descriptor); +EXPORT_SYMBOL(sah_Alloc_Head_Descriptor); +EXPORT_SYMBOL(sah_Free_Head_Descriptor); +EXPORT_SYMBOL(sah_Physicalise_Descriptors); +EXPORT_SYMBOL(sah_DePhysicalise_Descriptors); +#endif + +/* Determine if L2 cache support should be built in. */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)) +#ifdef CONFIG_OUTER_CACHE +#define HAS_L2_CACHE +#endif +#else +#ifdef CONFIG_CPU_CACHE_L210 +#define HAS_L2_CACHE +#endif +#endif + +/* Number of bytes the hardware uses out of sah_Link and sah_*Desc structs */ +#define SAH_HW_LINK_LEN 1 +#define SAH_HW_DESC_LEN 24 + +/* Macros for Descriptors */ +#define SAH_LLO_BIT 0x01000000 +#define sah_Desc_Get_LLO(desc) (desc->header & SAH_LLO_BIT) +#define sah_Desc_Set_Header(desc, h) (desc->header = (h)) + +#define sah_Desc_Get_Next(desc) (desc->next) +#define sah_Desc_Set_Next(desc, n) (desc->next = (n)) + +#define sah_Desc_Get_Ptr1(desc) (desc->ptr1) +#define sah_Desc_Get_Ptr2(desc) (desc->ptr2) +#define sah_Desc_Set_Ptr1(desc,p1) (desc->ptr1 = (p1)) +#define sah_Desc_Set_Ptr2(desc,p2) (desc->ptr2 = (p2)) + +#define sah_Desc_Get_Len1(desc) (desc->len1) +#define sah_Desc_Get_Len2(desc) (desc->len2) +#define sah_Desc_Set_Len1(desc,l1) (desc->len1 = (l1)) +#define sah_Desc_Set_Len2(desc,l2) (desc->len2 = (l2)) + +/* Macros for Links */ +#define sah_Link_Get_Next(link) (link->next) +#define sah_Link_Set_Next(link, n) (link->next = (n)) + +#define sah_Link_Get_Data(link) (link->data) +#define sah_Link_Set_Data(link,d) (link->data = (d)) + +#define sah_Link_Get_Len(link) (link->len) +#define sah_Link_Set_Len(link, l) (link->len = (l)) + +#define sah_Link_Get_Flags(link) (link->flags) + +/* Memory block defines */ +/* Warning! This assumes that kernel version of sah_Link + * is larger than kernel version of sah_Desc. + */ +#define MEM_BLOCK_SIZE sizeof(sah_Link) + +/*! Structure for link/descriptor memory blocks in internal pool */ +typedef struct mem_block { + uint8_t data[MEM_BLOCK_SIZE]; /*!< the actual buffer area */ + struct mem_block *next; /*!< next block when in free chain */ + dma_addr_t dma_addr; /*!< physical address of @a data */ +} Mem_Block; + +#define MEM_BLOCK_ENTRIES (PAGE_SIZE / sizeof(Mem_Block)) + +#define MEM_BIG_BLOCK_SIZE sizeof(sah_Head_Desc) + +/*! Structure for head descriptor memory blocks in internal pool */ +typedef struct mem_big_block { + uint8_t data[MEM_BIG_BLOCK_SIZE]; /*!< the actual buffer area */ + struct mem_big_block *next; /*!< next block when in free chain */ + uint32_t dma_addr; /*!< physical address of @a data */ +} Mem_Big_Block; + +#define MEM_BIG_BLOCK_ENTRIES (PAGE_SIZE / sizeof(Mem_Big_Block)) + +/* Shared variables */ + +/*! + * Lock to protect the memory chain composed of #block_free_head and + * #block_free_tail. + */ +static os_lock_t mem_lock; + +#ifndef SELF_MANAGED_POOL +static struct dma_pool *big_dma_pool = NULL; +static struct dma_pool *small_dma_pool = NULL; +#endif + +#ifdef SELF_MANAGED_POOL +/*! + * Memory block free pool - pointer to first block. Chain is protected by + * #mem_lock. + */ +static Mem_Block *block_free_head = NULL; +/*! + * Memory block free pool - pointer to last block. Chain is protected by + * #mem_lock. + */ +static Mem_Block *block_free_tail = NULL; +/*! + * Memory block free pool - pointer to first block. Chain is protected by + * #mem_lock. + */ +static Mem_Big_Block *big_block_free_head = NULL; +/*! + * Memory block free pool - pointer to last block. Chain is protected by + * #mem_lock. +a */ +static Mem_Big_Block *big_block_free_tail = NULL; +#endif /* SELF_MANAGED_POOL */ + +static Mem_Block *sah_Alloc_Block(void); +static void sah_Free_Block(Mem_Block * block); +static Mem_Big_Block *sah_Alloc_Big_Block(void); +static void sah_Free_Big_Block(Mem_Big_Block * block); +#ifdef SELF_MANAGED_POOL +static void sah_Append_Block(Mem_Block * block); +static void sah_Append_Big_Block(Mem_Big_Block * block); +#endif /* SELF_MANAGED_POOL */ + +/* Page context structure. Used by wire_user_memory and unwire_user_memory */ +typedef struct page_ctx_t { + uint32_t count; + struct page **local_pages; +} page_ctx_t; + +/*! +******************************************************************************* +* Map and wire down a region of user memory. +* +* +* @param address Userspace address of the memory to wire +* @param length Length of the memory region to wire +* @param page_ctx Page context, to be passed to unwire_user_memory +* +* @return (if successful) Kernel virtual address of the wired pages +*/ +void *wire_user_memory(void *address, uint32_t length, void **page_ctx) +{ + void *kernel_black_addr = NULL; + int result = -1; + int page_index = 0; + page_ctx_t *page_context; + int nr_pages = 0; + unsigned long start_page; + fsl_shw_return_t status; + + /* Determine the number of pages being used for this link */ + nr_pages = (((unsigned long)(address) & ~PAGE_MASK) + + length + ~PAGE_MASK) >> PAGE_SHIFT; + + start_page = (unsigned long)(address) & PAGE_MASK; + + /* Allocate some memory to keep track of the wired user pages, so that + * they can be deallocated later. The block of memory will contain both + * the structure and the array of pages. + */ + page_context = kmalloc(sizeof(page_ctx_t) + + nr_pages * sizeof(struct page *), GFP_KERNEL); + + if (page_context == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; /* no memory! */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("kmalloc() failed."); +#endif + return NULL; + } + + /* Set the page pointer to point to the allocated region of memory */ + page_context->local_pages = (void *)page_context + sizeof(page_ctx_t); + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("page_context at: %p, local_pages at: %p", + (void *)page_context, + (void *)(page_context->local_pages)); +#endif + + /* Wire down the pages from user space */ + down_read(¤t->mm->mmap_sem); + result = get_user_pages(current, current->mm, + start_page, nr_pages, WRITE, 0 /* noforce */ , + (page_context->local_pages), NULL); + up_read(¤t->mm->mmap_sem); + + if (result < nr_pages) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("get_user_pages() failed."); +#endif + if (result > 0) { + for (page_index = 0; page_index < result; page_index++) { + page_cache_release((page_context-> + local_pages[page_index])); + } + + kfree(page_context); + } + return NULL; + } + + kernel_black_addr = page_address(page_context->local_pages[0]) + + ((unsigned long)address & ~PAGE_MASK); + + page_context->count = nr_pages; + *page_ctx = page_context; + + return kernel_black_addr; +} + +/*! +******************************************************************************* +* Release and unmap a region of user memory. +* +* @param page_ctx Page context from wire_user_memory +*/ +void unwire_user_memory(void **page_ctx) +{ + int page_index = 0; + struct page_ctx_t *page_context = *page_ctx; + +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS("page_context at: %p, first page at:%p, count: %i", + (void *)page_context, + (void *)(page_context->local_pages), + page_context->count); +#endif + + if ((page_context != NULL) && (page_context->local_pages != NULL)) { + for (page_index = 0; page_index < page_context->count; + page_index++) { + page_cache_release(page_context-> + local_pages[page_index]); + } + + kfree(page_context); + *page_ctx = NULL; + } +} + +/*! +******************************************************************************* +* Map some physical memory into a users memory space +* +* @param vma Memory structure to map to +* @param physical_addr Physical address of the memory to be mapped in +* @param size Size of the memory to map (bytes) +* +* @return +*/ +os_error_code +map_user_memory(struct vm_area_struct *vma, uint32_t physical_addr, + uint32_t size) +{ + os_error_code retval; + + /* Map the acquired partition into the user's memory space */ + vma->vm_end = vma->vm_start + size; + + /* set cache policy to uncached so that each write of the UMID and + * permissions get directly to the SCC2 in order to engage it + * properly. Once the permissions have been written, it may be + * useful to provide a service for the user to request a different + * cache policy + */ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Make sure that the user cannot fork() a child which will inherit + * this mapping, as it creates a security hole. Likewise, do not + * allow the user to 'expand' his mapping beyond this partition. + */ + vma->vm_flags |= VM_IO | VM_RESERVED | VM_DONTCOPY | VM_DONTEXPAND; + + retval = remap_pfn_range(vma, + vma->vm_start, + __phys_to_pfn(physical_addr), + size, vma->vm_page_prot); + + return retval; +} + +/*! +******************************************************************************* +* Remove some memory from a user's memory space +* +* @param user_addr Userspace address of the memory to be unmapped +* @param size Size of the memory to map (bytes) +* +* @return +*/ +os_error_code unmap_user_memory(uint32_t user_addr, uint32_t size) +{ + os_error_code retval; + struct mm_struct *mm = current->mm; + + /* Unmap the memory region (see sys_munmap in mmap.c) */ + down_write(&mm->mmap_sem); + retval = do_munmap(mm, (unsigned long)user_addr, size); + up_write(&mm->mmap_sem); + + return retval; +} + +/*! +******************************************************************************* +* Free descriptor back to free pool +* +* @brief Free descriptor +* +* @param desc A descriptor allocated with sah_Alloc_Descriptor(). +* +* @return none +* +*/ +void sah_Free_Descriptor(sah_Desc * desc) +{ + memset(desc, 0x45, sizeof(*desc)); + sah_Free_Block((Mem_Block *) desc); +} + +/*! +******************************************************************************* +* Free Head descriptor back to free pool +* +* @brief Free Head descriptor +* +* @param desc A Head descriptor allocated with sah_Alloc_Head_Descriptor(). +* +* @return none +* +*/ +void sah_Free_Head_Descriptor(sah_Head_Desc * desc) +{ + memset(desc, 0x43, sizeof(*desc)); + sah_Free_Big_Block((Mem_Big_Block *) desc); +} + +/*! +******************************************************************************* +* Free link back to free pool +* +* @brief Free link +* +* @param link A link allocated with sah_Alloc_Link(). +* +* @return none +* +*/ +void sah_Free_Link(sah_Link * link) +{ + memset(link, 0x41, sizeof(*link)); + sah_Free_Block((Mem_Block *) link); +} + +/*! +******************************************************************************* +* This function runs through a descriptor chain pointed to by a user-space +* address. It duplicates each descriptor in Kernel space memory and calls +* sah_Copy_Links() to handle any links attached to the descriptors. This +* function cleans-up everything that it created in the case of a failure. +* +* @brief Kernel Descriptor Chain Copier +* +* @param fsl_shw_uco_t The user context to act under +* @param user_head_desc A Head Descriptor pointer from user-space. +* +* @return sah_Head_Desc * - A virtual address of the first descriptor in the +* chain. +* @return NULL - If there was some error. +* +*/ +sah_Head_Desc *sah_Copy_Descriptors(fsl_shw_uco_t * user_ctx, + sah_Head_Desc * user_head_desc) +{ + sah_Desc *curr_desc = NULL; + sah_Desc *prev_desc = NULL; + sah_Desc *next_desc = NULL; + sah_Head_Desc *head_desc = NULL; + sah_Desc *user_desc = NULL; + unsigned long result; + + /* Internal status variable to be used in this function */ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Head_Desc *ret_val = NULL; + + /* This will be set to True when we have finished processing our + * descriptor chain. + */ + int drv_if_done = FALSE; + int is_this_the_head = TRUE; + + do { + /* Allocate memory for this descriptor */ + if (is_this_the_head) { + head_desc = + (sah_Head_Desc *) sah_Alloc_Head_Descriptor(); + +#ifdef DIAG_MEM + sprintf(Diag_msg, + "Alloc_Head_Descriptor returned %p\n", + head_desc); + LOG_KDIAG(Diag_msg); +#endif + if (head_desc == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("sah_Alloc_Head_Descriptor() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_NO_RESOURCE_S; + } else { + void *virt_addr = head_desc->desc.virt_addr; + dma_addr_t dma_addr = head_desc->desc.dma_addr; + + /* Copy the head descriptor from user-space */ + /* Instead of copying the whole structure, + * unneeded bits at the end are left off. + * The user space version is missing virt/dma addrs, which + * means that the copy will be off for flags... */ + result = copy_from_user(head_desc, + user_head_desc, + (sizeof(*head_desc) - + sizeof(head_desc->desc. + dma_addr) - + sizeof(head_desc->desc. + virt_addr) - + sizeof(head_desc->desc. + original_ptr1) - +/* sizeof(head_desc->desc.original_ptr2) - + sizeof(head_desc->status) - + sizeof(head_desc->error_status) - + sizeof(head_desc->fault_address) - + sizeof(head_desc->current_dar) - + sizeof(head_desc->result) - + sizeof(head_desc->next) - + sizeof(head_desc->prev) - + sizeof(head_desc->user_desc) - +*/ sizeof(head_desc->out1_ptr) - + sizeof(head_desc-> + out2_ptr) - + sizeof(head_desc-> + out_len))); + /* there really isn't a 'next' descriptor at this point, so + * set that pointer to NULL, but remember it for if/when there + * is a next */ + next_desc = head_desc->desc.next; + head_desc->desc.next = NULL; + + if (result != 0) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("copy_from_user() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; + /* when destroying the descriptor, skip these links. + * They've not been copied down, so don't exist */ + head_desc->desc.ptr1 = NULL; + head_desc->desc.ptr2 = NULL; + + } else { + /* The kernel DESC has five more words than user DESC, so + * the missing values are in the middle of the HEAD DESC, + * causing values after the missing ones to be at different + * offsets in kernel and user space. + * + * Patch up the problem by moving field two spots. + * This assumes sizeof(pointer) == sizeof(uint32_t). + * Note that 'user_info' is not needed, so not copied. + */ + head_desc->user_ref = + (uint32_t) head_desc->desc.dma_addr; + head_desc->uco_flags = + (uint32_t) head_desc->desc. + original_ptr1; +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS( + "User flags: %x; User Reference: %x", + head_desc->uco_flags, + head_desc->user_ref); +#endif + /* These values were destroyed by the copy. */ + head_desc->desc.virt_addr = virt_addr; + head_desc->desc.dma_addr = dma_addr; + + /* ensure that the save descriptor chain bit is not set. + * the copy of the user space descriptor chain should + * always be deleted */ + head_desc->uco_flags &= + ~FSL_UCO_SAVE_DESC_CHAIN; + + curr_desc = (sah_Desc *) head_desc; + is_this_the_head = FALSE; + } + } + } else { /* not head */ + curr_desc = sah_Alloc_Descriptor(); +#ifdef DIAG_MEM + LOG_KDIAG_ARGS("Alloc_Descriptor returned %p\n", + curr_desc); +#endif + if (curr_desc == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Alloc_Descriptor() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_NO_RESOURCE_S; + } else { + /* need to update the previous descriptors' next field to + * pointer to the current descriptor. */ + prev_desc->original_next = curr_desc; + prev_desc->next = + (sah_Desc *) curr_desc->dma_addr; + + /* Copy the current descriptor from user-space */ + /* The virtual address and DMA address part of the sah_Desc + * struct are not copied to user space */ + result = copy_from_user(curr_desc, user_desc, (sizeof(sah_Desc) - sizeof(dma_addr_t) - /* dma_addr */ + sizeof(uint32_t) - /* virt_addr */ + sizeof(void *) - /* original_ptr1 */ + sizeof(void *) - /* original_ptr2 */ + sizeof(sah_Desc **))); /* original_next */ + /* there really isn't a 'next' descriptor at this point, so + * set that pointer to NULL, but remember it for if/when there + * is a next */ + next_desc = curr_desc->next; + curr_desc->next = NULL; + curr_desc->original_next = NULL; + + if (result != 0) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("copy_from_user() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; + /* when destroying the descriptor chain, skip these links. + * They've not been copied down, so don't exist */ + curr_desc->ptr1 = NULL; + curr_desc->ptr2 = NULL; + } + } + } /* end if (is_this_the_head) */ + + if (status == FSL_RETURN_OK_S) { + if (!(curr_desc->header & SAH_LLO_BIT)) { + /* One or both pointer fields being NULL is a valid + * configuration. */ + if (curr_desc->ptr1 == NULL) { + curr_desc->original_ptr1 = NULL; + } else { + /* pointer fields point to sah_Link structures */ + curr_desc->original_ptr1 = + sah_Copy_Links(user_ctx, curr_desc->ptr1); + if (curr_desc->original_ptr1 == NULL) { + /* This descriptor and any links created successfully + * are cleaned-up at the bottom of this function. */ + drv_if_done = TRUE; + status = + FSL_RETURN_INTERNAL_ERROR_S; + /* mark that link 2 doesn't exist */ + curr_desc->ptr2 = NULL; +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("sah_Copy_Links() failed."); +#endif + } else { + curr_desc->ptr1 = (void *) + ((sah_Link *) curr_desc-> + original_ptr1)->dma_addr; + } + } + + if (status == FSL_RETURN_OK_S) { + if (curr_desc->ptr2 == NULL) { + curr_desc->original_ptr2 = NULL; + } else { + /* pointer fields point to sah_Link structures */ + curr_desc->original_ptr2 = + sah_Copy_Links(user_ctx, curr_desc->ptr2); + if (curr_desc->original_ptr2 == + NULL) { + /* This descriptor and any links created + * successfully are cleaned-up at the bottom of + * this function. */ + drv_if_done = TRUE; + status = + FSL_RETURN_INTERNAL_ERROR_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("sah_Copy_Links() failed."); +#endif + } else { + curr_desc->ptr2 = + (void + *)(((sah_Link *) + curr_desc-> + original_ptr2) + ->dma_addr); + } + } + } + } else { + /* Pointer fields point directly to user buffers. We don't + * support this mode. + */ +#ifdef DIAG_DRV_IF + LOG_KDIAG + ("The LLO bit in the Descriptor Header field was " + "set. This an invalid configuration."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; + } + } + + if (status == FSL_RETURN_OK_S) { + user_desc = next_desc; + prev_desc = curr_desc; + if (user_desc == NULL) { + /* We have reached the end our our descriptor chain */ + drv_if_done = TRUE; + } + } + + } while (drv_if_done == FALSE); + + if (status != FSL_RETURN_OK_S) { + /* Clean-up if failed */ + if (head_desc != NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("Error! Calling destroy descriptors!\n"); +#endif + sah_Destroy_Descriptors(head_desc); + } + ret_val = NULL; + } else { + /* Flush the caches */ +#ifndef FLUSH_SPECIFIC_DATA_ONLY + os_flush_cache_all(); +#endif + + /* Success. Return the DMA'able head descriptor. */ + ret_val = head_desc; + + } + + return ret_val; +} /* sah_Copy_Descriptors() */ + +/*! +******************************************************************************* +* This function runs through a sah_Link chain pointed to by a kernel-space +* address. It computes the physical address for each pointer, and converts +* the chain to use these physical addresses. +* +****** +* This function needs to return some indication that the chain could not be +* converted. It also needs to back out any conversion already taken place on +* this chain of links. +* +* Then, of course, sah_Physicalise_Descriptors() will need to recognize that +* an error occured, and then be able to back out any physicalization of the +* chain which had taken place up to that point! +****** +* +* @brief Convert kernel Link chain +* +* @param first_link A sah_Link pointer from kernel space; must not be +* NULL, so error case can be distinguished. +* +* @return sah_Link * A dma'able address of the first descriptor in the +* chain. +* @return NULL If Link chain could not be physicalised, i.e. ERROR +* +*/ +sah_Link *sah_Physicalise_Links(sah_Link * first_link) +{ + sah_Link *link = first_link; + + while (link != NULL) { +#ifdef DO_DBG + sah_Dump_Words("Link", (unsigned *)link, link->dma_addr, 3); +#endif + link->vm_info = NULL; + + /* need to retrieve stored key? */ + if (link->flags & SAH_STORED_KEY_INFO) { + uint32_t max_len = 0; /* max slot length */ + fsl_shw_return_t ret_status; + + /* get length and physical address of stored key */ + ret_status = system_keystore_get_slot_info(link->ownerid, link->slot, (uint32_t *) & link->data, /* RED key address */ + &max_len); + if ((ret_status != FSL_RETURN_OK_S) || (link->len > max_len)) { + /* trying to illegally/incorrectly access a key. Cause the + * error status register to show a Link Length Error by + * putting a zero in the links length. */ + link->len = 0; /* Cause error. Somebody is up to no good. */ + } + } else if (link->flags & SAH_IN_USER_KEYSTORE) { + +#ifdef FSL_HAVE_SCC2 + /* The data field points to the virtual address of the key. Convert + * this to a physical address by modifying the address based + * on where the secure memory was mapped to the kernel. Note: In + * kernel mode, no attempt is made to track or control who owns what + * memory partition. + */ + link->data = (uint8_t *) scc_virt_to_phys(link->data); + + /* Do bounds checking to ensure that the user is not overstepping + * the bounds of their partition. This is a simple implementation + * that assumes the user only owns one partition. It only checks + * to see if the address of the last byte of data steps over a + * page boundary. + */ + +#ifdef DO_DBG + LOG_KDIAG_ARGS("start page: %08x, end page: %08x" + "first addr: %p, last addr: %p, len; %i", + ((uint32_t) (link->data) >> PAGE_SHIFT), + (((uint32_t) link->data + + link->len) >> PAGE_SHIFT), link->data, + link->data + link->len, link->len); +#endif + + if ((((uint32_t) link->data + + link->len) >> PAGE_SHIFT) != + ((uint32_t) link->data >> PAGE_SHIFT)) { + link->len = 0; /* Cause error. Somebody is up to no good. */ + } +#else /* FSL_HAVE_SCC2 */ + + /* User keystores are not valid on non-SCC2 platforms */ + link->len = 0; /* Cause error. Somebody is up to no good. */ + +#endif /* FSL_HAVE_SCC2 */ + + } else { + if (!(link->flags & SAH_PREPHYS_DATA)) { + link->original_data = link->data; + + /* All pointers are virtual right now */ + link->data = (void *)os_pa(link->data); +#ifdef DO_DBG + os_printk("%sput: %p (%d)\n", + (link-> + flags & SAH_OUTPUT_LINK) ? "out" : + "in", link->data, link->len); +#endif + + if (link->flags & SAH_OUTPUT_LINK) { + /* clean and invalidate */ + os_cache_flush_range(link-> + original_data, + link->len); + } else { + os_cache_clean_range(link->original_data, + link->len); + } + } /* not prephys */ + } /* else not key reference */ + +#if defined(NO_OUTPUT_1K_CROSSING) || defined(NO_1K_CROSSING) + if ( +#ifdef NO_OUTPUT_1K_CROSSING + /* Insert extra link if 1k boundary on output pointer + * crossed not at an 8-word boundary */ + (link->flags & SAH_OUTPUT_LINK) && + (((uint32_t) link->data % 32) != 0) && +#endif + ((((uint32_t) link->data & 1023) + link->len) > + 1024)) { + uint32_t full_length = link->len; + sah_Link *new_link = sah_Alloc_Link(); + link->len = 1024 - ((uint32_t) link->data % 1024); + new_link->len = full_length - link->len; + new_link->data = link->data + link->len; + new_link->original_data = + link->original_data + link->len; + new_link->flags = link->flags & ~(SAH_OWNS_LINK_DATA); + new_link->flags |= SAH_LINK_INSERTED_LINK; + new_link->next = link->next; + + link->next = (sah_Link *) new_link->dma_addr; + link->original_next = new_link; + link = new_link; + } +#endif /* ALLOW_OUTPUT_1K_CROSSING */ + + link->original_next = link->next; + if (link->next != NULL) { + link->next = (sah_Link *) link->next->dma_addr; + } +#ifdef DO_DBG + sah_Dump_Words("Link", link, link->dma_addr, 3); +#endif + + link = link->original_next; + } + + return (sah_Link *) first_link->dma_addr; +} /* sah_Physicalise_Links */ + +/*! + * Run through descriptors and links created by KM-API and set the + * dma addresses and 'do not free' flags. + * + * @param first_desc KERNEL VIRTUAL address of first descriptor in chain. + * + * Warning! This ONLY works without LLO flags in headers!!! + * + * @return Virtual address of @a first_desc. + * @return NULL if Descriptor Chain could not be physicalised + */ +sah_Head_Desc *sah_Physicalise_Descriptors(sah_Head_Desc * first_desc) +{ + sah_Desc *desc = &first_desc->desc; + + if (!(first_desc->uco_flags & FSL_UCO_CHAIN_PREPHYSICALIZED)) { + while (desc != NULL) { + sah_Desc *next_desc; + +#ifdef DO_DBG + + sah_Dump_Words("Desc", (unsigned *)desc, desc->dma_addr, 6); +#endif + + desc->original_ptr1 = desc->ptr1; + if (desc->ptr1 != NULL) { + if ((desc->ptr1 = + sah_Physicalise_Links(desc->ptr1)) == + NULL) { + /* Clean up ... */ + sah_DePhysicalise_Descriptors + (first_desc); + first_desc = NULL; + break; + } + } + desc->original_ptr2 = desc->ptr2; + if (desc->ptr2 != NULL) { + if ((desc->ptr2 = + sah_Physicalise_Links(desc->ptr2)) == + NULL) { + /* Clean up ... */ + sah_DePhysicalise_Descriptors + (first_desc); + first_desc = NULL; + break; + } + } + + desc->original_next = desc->next; + next_desc = desc->next; /* save for bottom of while loop */ + if (desc->next != NULL) { + desc->next = (sah_Desc *) desc->next->dma_addr; + } + + desc = next_desc; + } + } + /* not prephysicalized */ +#ifdef DO_DBG + os_printk("Physicalise finished\n"); +#endif + + return first_desc; +} /* sah_Physicalise_Descriptors() */ + +/*! +******************************************************************************* +* This function runs through a sah_Link chain pointed to by a physical address. +* It computes the virtual address for each pointer +* +* @brief Convert physical Link chain +* +* @param first_link A kernel address of a sah_Link +* +* @return sah_Link * A kernal address for the link chain of @c first_link +* @return NULL If there was some error. +* +* @post All links will be chained together by original virtual addresses, +* data pointers will point to virtual addresses. Appropriate cache +* lines will be flushed, memory unwired, etc. +*/ +sah_Link *sah_DePhysicalise_Links(sah_Link * first_link) +{ + sah_Link *link = first_link; + sah_Link *prev_link = NULL; + + /* Loop on virtual link pointer */ + while (link != NULL) { + +#ifdef DO_DBG + sah_Dump_Words("Link", (unsigned *)link, link->dma_addr, 3); +#endif + + /* if this references stored keys, don't want to dephysicalize them */ + if (!(link->flags & SAH_STORED_KEY_INFO) + && !(link->flags & SAH_PREPHYS_DATA) + && !(link->flags & SAH_IN_USER_KEYSTORE)) { + + /* */ + if (link->flags & SAH_OUTPUT_LINK) { + os_cache_inv_range(link->original_data, + link->len); + } + + /* determine if there is a page in user space associated with this + * link */ + if (link->vm_info != NULL) { + /* check that this isn't reserved and contains output */ + if (!PageReserved(link->vm_info) && + (link->flags & SAH_OUTPUT_LINK)) { + + /* Mark to force page eventually to backing store */ + SetPageDirty(link->vm_info); + } + + /* Untie this page from physical memory */ + page_cache_release(link->vm_info); + } else { + /* kernel-mode data */ +#ifdef DO_DBG + os_printk("%sput: %p (%d)\n", + (link-> + flags & SAH_OUTPUT_LINK) ? "out" : + "in", link->original_data, link->len); +#endif + } + link->data = link->original_data; + } +#ifndef ALLOW_OUTPUT_1K_CROSSING + if (link->flags & SAH_LINK_INSERTED_LINK) { + /* Reconsolidate data by merging this link with previous */ + prev_link->len += link->len; + prev_link->next = link->next; + prev_link->original_next = link->original_next; + sah_Free_Link(link); + link = prev_link; + + } +#endif + + if (link->next != NULL) { + link->next = link->original_next; + } + prev_link = link; + link = link->next; + } + + return first_link; +} /* sah_DePhysicalise_Links() */ + +/*! + * Run through descriptors and links that have been Physicalised + * (sah_Physicalise_Descriptors function) and set the dma addresses back + * to KM virtual addresses + * + * @param first_desc Kernel virtual address of first descriptor in chain. + * + * Warning! This ONLY works without LLO flags in headers!!! + */ +sah_Head_Desc *sah_DePhysicalise_Descriptors(sah_Head_Desc * first_desc) +{ + sah_Desc *desc = &first_desc->desc; + + if (!(first_desc->uco_flags & FSL_UCO_CHAIN_PREPHYSICALIZED)) { + while (desc != NULL) { +#ifdef DO_DBG + sah_Dump_Words("Desc", (unsigned *)desc, desc->dma_addr, 6); +#endif + + if (desc->ptr1 != NULL) { + desc->ptr1 = + sah_DePhysicalise_Links(desc-> + original_ptr1); + } + if (desc->ptr2 != NULL) { + desc->ptr2 = + sah_DePhysicalise_Links(desc-> + original_ptr2); + } + if (desc->next != NULL) { + desc->next = desc->original_next; + } + desc = desc->next; + } + } + /* not prephysicalized */ + return first_desc; +} /* sah_DePhysicalise_Descriptors() */ + +/*! +******************************************************************************* +* This walks through a SAHARA descriptor chain and free()'s everything +* that is not NULL. Finally it also unmaps all of the physical memory and +* frees the kiobuf_list Queue. +* +* @brief Kernel Descriptor Chain Destructor +* +* @param head_desc A Descriptor pointer from kernel-space. +* +* @return void +* +*/ +void sah_Free_Chained_Descriptors(sah_Head_Desc * head_desc) +{ + sah_Desc *desc = NULL; + sah_Desc *next_desc = NULL; + int this_is_head = 1; + + desc = &head_desc->desc; + + while (desc != NULL) { + + sah_Free_Chained_Links(desc->ptr1); + sah_Free_Chained_Links(desc->ptr2); + + /* Get a bus pointer to the next Descriptor */ + next_desc = desc->next; + + /* Zero the header and Length fields for security reasons. */ + desc->header = 0; + desc->len1 = 0; + desc->len2 = 0; + + if (this_is_head) { + sah_Free_Head_Descriptor(head_desc); + this_is_head = 0; +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Head_Descriptor: %p\n", + head_desc); + LOG_KDIAG(Diag_msg); +#endif + } else { + /* free this descriptor */ + sah_Free_Descriptor(desc); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Descriptor: %p\n", desc); + LOG_KDIAG(Diag_msg); +#endif + } + + /* Look at the next Descriptor */ + desc = next_desc; + } +} /* sah_Free_Chained_Descriptors() */ + +/*! +******************************************************************************* +* This walks through a SAHARA link chain and frees everything that is +* not NULL, excluding user-space buffers. +* +* @brief Kernel Link Chain Destructor +* +* @param link A Link pointer from kernel-space. This is in bus address +* space. +* +* @return void +* +*/ +void sah_Free_Chained_Links(sah_Link * link) +{ + sah_Link *next_link = NULL; + + while (link != NULL) { + /* Get a bus pointer to the next Link */ + next_link = link->next; + + /* Zero some fields for security reasons. */ + link->data = NULL; + link->len = 0; + link->ownerid = 0; + + /* Free this Link */ +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Link: %p(->%p)\n", link, link->next); + LOG_KDIAG(Diag_msg); +#endif + sah_Free_Link(link); + + /* Move on to the next Link */ + link = next_link; + } +} + +/*! +******************************************************************************* +* This function runs through a link chain pointed to by a user-space +* address. It makes a temporary kernel-space copy of each link in the +* chain and calls sah_Make_Links() to create a set of kernel-side links +* to replace it. +* +* @brief Kernel Link Chain Copier +* +* @param ptr A link pointer from user-space. +* +* @return sah_Link * - The virtual address of the first link in the +* chain. +* @return NULL - If there was some error. +*/ +sah_Link *sah_Copy_Links(fsl_shw_uco_t * user_ctx, sah_Link * ptr) +{ + sah_Link *head_link = NULL; + sah_Link *new_head_link = NULL; + sah_Link *new_tail_link = NULL; + sah_Link *prev_tail_link = NULL; + sah_Link *user_link = ptr; + sah_Link link_copy; + int link_data_length = 0; + + /* Internal status variable to be used in this function */ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *ret_val = NULL; + + /* This will be set to True when we have finished processing our + * link chain. */ + int drv_if_done = FALSE; + int is_this_the_head = TRUE; + int result; + + /* transfer all links, on this link chain, from user space */ + while (drv_if_done == FALSE) { + /* Copy the current link from user-space. The virtual address, DMA + * address, and vm_info fields of the sah_Link struct are not part + * of the user-space structure. They must be the last elements and + * should not be copied. */ + result = copy_from_user(&link_copy, + user_link, (sizeof(sah_Link) - +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) + sizeof(struct page *) - /* vm_info */ +#endif + sizeof(dma_addr_t) - /* dma_addr */ + sizeof(uint32_t) - /* virt_addr */ + sizeof(uint8_t *) - /* original_data */ + sizeof(sah_Link *))); /* original_next */ + + if (result != 0) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("copy_from_user() failed."); +#endif + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; + } + + if (status == FSL_RETURN_OK_S) { + /* This will create new links which can be used to replace tmp_link + * in the chain. This will return a new head and tail link. */ + link_data_length = link_data_length + link_copy.len; + new_head_link = + sah_Make_Links(user_ctx, &link_copy, &new_tail_link); + + if (new_head_link == NULL) { + /* If we ran out of memory or a user pointer was invalid */ + drv_if_done = TRUE; + status = FSL_RETURN_INTERNAL_ERROR_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Make_Links() failed."); +#endif + } else { + if (is_this_the_head == TRUE) { + /* Keep a reference to the head link */ + head_link = new_head_link; + is_this_the_head = FALSE; + } else { + /* Need to update the previous links' next field to point + * to the current link. */ + prev_tail_link->next = + (void *)new_head_link->dma_addr; + prev_tail_link->original_next = + new_head_link; + } + } + } + + if (status == FSL_RETURN_OK_S) { + /* Get to the next link in the chain. */ + user_link = link_copy.next; + prev_tail_link = new_tail_link; + + /* Check if the end of the link chain was reached (TRUE) or if + * there is another linked to this one (FALSE) */ + drv_if_done = (user_link == NULL) ? TRUE : FALSE; + } + } /* end while */ + + if (status != FSL_RETURN_OK_S) { + ret_val = NULL; + /* There could be clean-up to do here because we may have made some + * successful iterations through the while loop and as a result, the + * links created by sah_Make_Links() need to be destroyed. + */ + if (head_link != NULL) { + /* Failed somewhere in the while loop and need to clean-up. */ + sah_Destroy_Links(head_link); + } + } else { + /* Success. Return the head link. */ + ret_val = head_link; + } + + return ret_val; +} /* sah_Copy_Links() */ + +/*! +******************************************************************************* +* This function takes an input link pointed to by a user-space address +* and returns a chain of links that span the physical pages pointed +* to by the input link. +* +* @brief Kernel Link Chain Constructor +* +* @param ptr A link pointer from user-space. +* @param tail The address of a link pointer. This is used to return +* the tail link created by this function. +* +* @return sah_Link * - A virtual address of the first link in the +* chain. +* @return NULL - If there was some error. +* +*/ +sah_Link *sah_Make_Links(fsl_shw_uco_t * user_ctx, + sah_Link * ptr, sah_Link ** tail) +{ + int result = -1; + int page_index = 0; + fsl_shw_return_t status = FSL_RETURN_OK_S; + int is_this_the_head = TRUE; + void *buffer_start = NULL; + sah_Link *link = NULL; + sah_Link *prev_link = NULL; + sah_Link *head_link = NULL; + sah_Link *ret_val = NULL; + int buffer_length = 0; + struct page **local_pages = NULL; + int nr_pages = 0; + int write = (sah_Link_Get_Flags(ptr) & SAH_OUTPUT_LINK) ? WRITE : READ; + dma_addr_t phys_addr; + + /* need to retrieve stored key? */ + if (ptr->flags & SAH_STORED_KEY_INFO) { + fsl_shw_return_t ret_status; + + /* allocate space for this link */ + link = sah_Alloc_Link(); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link, + (void *)link->dma_addr); + LOG_KDIAG(Diag_msg); +#endif + + if (link == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Alloc_Link() failed!"); +#endif + return link; + } else { + uint32_t max_len = 0; /* max slot length */ + + /* get length and physical address of stored key */ + ret_status = system_keystore_get_slot_info(ptr->ownerid, ptr->slot, (uint32_t *) & link->data, /* RED key address */ + &max_len); +#ifdef DIAG_DRV_IF + LOG_KDIAG_ARGS + ("ret_status==SCC_RET_OK? %s. slot: %i. data: %p" + ". len: %i, key length: %i", + (ret_status == FSL_RETURN_OK_S ? "yes" : "no"), + ptr->slot, link->data, max_len, ptr->len); +#endif + + if ((ret_status == FSL_RETURN_OK_S) && (ptr->len <= max_len)) { + /* finish populating the link */ + link->len = ptr->len; + link->flags = ptr->flags & ~SAH_PREPHYS_DATA; + *tail = link; + } else { +#ifdef DIAG_DRV_IF + if (ret_status == FSL_RETURN_OK_S) { + LOG_KDIAG + ("SCC sah_Link key slot reference is too long"); + } else { + LOG_KDIAG + ("SCC sah_Link slot slot reference is invalid"); + } +#endif + sah_Free_Link(link); + status = FSL_RETURN_INTERNAL_ERROR_S; + return NULL; + } + return link; + } + } else if (ptr->flags & SAH_IN_USER_KEYSTORE) { + +#ifdef FSL_HAVE_SCC2 + + void *kernel_base; + + /* allocate space for this link */ + link = sah_Alloc_Link(); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link, + (void *)link->dma_addr); + LOG_KDIAG(Diag_msg); +#endif /* DIAG_MEM */ + + if (link == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Alloc_Link() failed!"); +#endif + return link; + } else { + /* link->data points to the virtual address of the key data, however + * this memory does not need to be locked down. + */ + kernel_base = lookup_user_partition(user_ctx, + (uint32_t) ptr-> + data & PAGE_MASK); + + link->data = (uint8_t *) scc_virt_to_phys(kernel_base + + ((unsigned + long)ptr-> + data & + ~PAGE_MASK)); + + /* Do bounds checking to ensure that the user is not overstepping + * the bounds of their partition. This is a simple implementation + * that assumes the user only owns one partition. It only checks + * to see if the address of the last byte of data steps over a + * page boundary. + */ + if ((kernel_base != NULL) && + ((((uint32_t) link->data + + link->len) >> PAGE_SHIFT) == + ((uint32_t) link->data >> PAGE_SHIFT))) { + /* finish populating the link */ + link->len = ptr->len; + link->flags = ptr->flags & ~SAH_PREPHYS_DATA; + *tail = link; + } else { +#ifdef DIAG_DRV_IF + if (kernel_base != NULL) { + LOG_KDIAG + ("SCC sah_Link key slot reference is too long"); + } else { + LOG_KDIAG + ("SCC sah_Link slot slot reference is invalid"); + } +#endif + sah_Free_Link(link); + status = FSL_RETURN_INTERNAL_ERROR_S; + return NULL; + } + return link; + } + +#else /* FSL_HAVE_SCC2 */ + + return NULL; + +#endif /* FSL_HAVE_SCC2 */ + } + + if (ptr->data == NULL) { + /* The user buffer must not be NULL because map_user_kiobuf() cannot + * handle NULL pointer input. + */ + status = FSL_RETURN_BAD_DATA_LENGTH_S; +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Link data pointer is NULL."); +#endif + } + + if (status == FSL_RETURN_OK_S) { + unsigned long start_page = (unsigned long)ptr->data & PAGE_MASK; + + /* determine number of pages being used for this link */ + nr_pages = (((unsigned long)(ptr->data) & ~PAGE_MASK) + + ptr->len + ~PAGE_MASK) >> PAGE_SHIFT; + + /* ptr contains all the 'user space' information, add the pages + * to it also just so everything is in one place */ + local_pages = + kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); + + if (local_pages == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; /* no memory! */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("kmalloc() failed."); +#endif + } else { + /* get the actual pages being used in 'user space' */ + + down_read(¤t->mm->mmap_sem); + result = get_user_pages(current, current->mm, + start_page, nr_pages, + write, 0 /* noforce */ , + local_pages, NULL); + up_read(¤t->mm->mmap_sem); + + if (result < nr_pages) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("get_user_pages() failed."); +#endif + if (result > 0) { + for (page_index = 0; + page_index < result; + page_index++) { + page_cache_release(local_pages + [page_index]); + } + } + status = FSL_RETURN_INTERNAL_ERROR_S; + } + } + } + + /* Now we can walk through the list of pages in the buffer */ + if (status == FSL_RETURN_OK_S) { + +#if defined(FLUSH_SPECIFIC_DATA_ONLY) && !defined(HAS_L2_CACHE) + /* + * Now that pages are wired, clear user data from cache lines. When + * there is just an L1 cache, clean based on user virtual for ARM. + */ + if (write == WRITE) { + os_cache_flush_range(ptr->data, ptr->len); + } else { + os_cache_clean_range(ptr->data, ptr->len); + } +#endif + + for (page_index = 0; page_index < nr_pages; page_index++) { + /* Allocate a new link structure */ + link = sah_Alloc_Link(); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Alloc_Link returned %p/%p\n", link, + (void *)link->dma_addr); + LOG_KDIAG(Diag_msg); +#endif + if (link == NULL) { +#ifdef DIAG_DRV_IF + LOG_KDIAG("sah_Alloc_Link() failed."); +#endif + status = FSL_RETURN_NO_RESOURCE_S; + + /* need to free the rest of the pages. Destroy_Links will take + * care of the ones already assigned to a link */ + for (; page_index < nr_pages; page_index++) { + page_cache_release(local_pages + [page_index]); + } + break; /* exit 'for page_index' loop */ + } + + if (status == FSL_RETURN_OK_S) { + if (is_this_the_head == TRUE) { + /* keep a reference to the head link */ + head_link = link; + /* remember that we have seen the head link */ + is_this_the_head = FALSE; + } else { + /* If this is not the head link then set the previous + * link's next pointer to point to this link */ + prev_link->original_next = link; + prev_link->next = + (sah_Link *) link->dma_addr; + } + + buffer_start = + page_address(local_pages[page_index]); + + phys_addr = + page_to_phys(local_pages[page_index]); + + if (page_index == 0) { + /* If this is the first page, there might be an + * offset. We need to increment the address by this offset + * so we don't just get the start of the page. + */ + buffer_start += + (unsigned long) + sah_Link_Get_Data(ptr) + & ~PAGE_MASK; + phys_addr += + (unsigned long) + sah_Link_Get_Data(ptr) + & ~PAGE_MASK; + buffer_length = PAGE_SIZE + - + ((unsigned long) + sah_Link_Get_Data(ptr) + & ~PAGE_MASK); + } else { + buffer_length = PAGE_SIZE; + } + + if (page_index == nr_pages - 1) { + /* if this is the last page, we need to adjust + * the buffer_length to account for the last page being + * partially used. + */ + buffer_length -= + nr_pages * PAGE_SIZE - + sah_Link_Get_Len(ptr) - + ((unsigned long) + sah_Link_Get_Data(ptr) & + ~PAGE_MASK); + } +#if defined(FLUSH_SPECIFIC_DATA_ONLY) && defined(HAS_L2_CACHE) + /* + * When there is an L2 cache, clean based on kernel + * virtual.. + */ + if (write == WRITE) { + os_cache_flush_range(buffer_start, + buffer_length); + } else { + os_cache_clean_range(buffer_start, + buffer_length); + } +#endif + + /* Fill in link information */ + link->len = buffer_length; +#if !defined(HAS_L2_CACHE) + /* use original virtual */ + link->original_data = ptr->data; +#else + /* use kernel virtual */ + link->original_data = buffer_start; +#endif + link->data = (void *)phys_addr; + link->flags = ptr->flags & ~SAH_PREPHYS_DATA; + link->vm_info = local_pages[page_index]; + prev_link = link; + +#if defined(NO_OUTPUT_1K_CROSSING) || defined(NO_1K_CROSSING) + if ( +#ifdef NO_OUTPUT_1K_CROSSING + /* Insert extra link if 1k boundary on output pointer + * crossed not at an 8-word boundary */ + (link->flags & SAH_OUTPUT_LINK) && + (((uint32_t) buffer_start % 32) != 0) + && +#endif + ((((uint32_t) buffer_start & 1023) + + buffer_length) > 1024)) { + + /* Shorten current link to 1k boundary */ + link->len = + 1024 - + ((uint32_t) buffer_start % 1024); + + /* Get new link to follow it */ + link = sah_Alloc_Link(); + prev_link->len = + 1024 - + ((uint32_t) buffer_start % 1024); + prev_link->original_next = link; + prev_link->next = + (sah_Link *) link->dma_addr; + buffer_length -= prev_link->len; + buffer_start += prev_link->len; + +#if !defined(HAS_L2_CACHE) + /* use original virtual */ + link->original_data = ptr->data; +#else + /* use kernel virtual */ + link->original_data = buffer_start; +#endif + link->data = (void *)phys_addr; + link->vm_info = prev_link->vm_info; + prev_link->vm_info = NULL; /* delay release */ + link->flags = ptr->flags; + link->len = buffer_length; + prev_link = link; + } /* while link would cross 1K boundary */ +#endif /* 1K_CROSSING */ + } + } /* for each page */ + } + + if (local_pages != NULL) { + kfree(local_pages); + } + + if (status != FSL_RETURN_OK_S) { + /* De-allocated any links created, this routine first looks if + * head_link is NULL */ + sah_Destroy_Links(head_link); + + /* Clean-up of the KIOBUF will occur in the * sah_Copy_Descriptors() + * function. + * Clean-up of the Queue entry must occur in the function called + * sah_Copy_Descriptors(). + */ + } else { + + /* Success. Return the head link. */ + ret_val = head_link; + link->original_next = NULL; + /* return the tail link as well */ + *tail = link; + } + + return ret_val; +} /* sah_Make_Links() */ + +/*! +******************************************************************************* +* This walks through a SAHARA descriptor chain and frees everything +* that is not NULL. Finally it also unmaps all of the physical memory and +* frees the kiobuf_list Queue. +* +* @brief Kernel Descriptor Chain Destructor +* +* @param desc A Descriptor pointer from kernel-space. This should be +* in bus address space. +* +* @return void +* +*/ +void sah_Destroy_Descriptors(sah_Head_Desc * head_desc) +{ + sah_Desc *this_desc = (sah_Desc *) head_desc; + sah_Desc *next_desc = NULL; + int this_is_head = 1; + + /* + * Flush the D-cache. This flush is here because the hardware has finished + * processing this descriptor and probably has changed the contents of + * some linked user buffers as a result. This flush will enable + * user-space applications to see the correct data rather than the + * out-of-date cached version. + */ +#ifndef FLUSH_SPECIFIC_DATA_ONLY + os_flush_cache_all(); +#endif + + head_desc = (sah_Head_Desc *) this_desc->virt_addr; + + while (this_desc != NULL) { + if (this_desc->ptr1 != NULL) { + sah_Destroy_Links(this_desc->original_ptr1 + ? this_desc-> + original_ptr1 : this_desc->ptr1); + } + if (this_desc->ptr2 != NULL) { + sah_Destroy_Links(this_desc->original_ptr2 + ? this_desc-> + original_ptr2 : this_desc->ptr2); + } + + /* Get a bus pointer to the next Descriptor */ + next_desc = (this_desc->original_next + ? this_desc->original_next : this_desc->next); + + /* Zero the header and Length fields for security reasons. */ + this_desc->header = 0; + this_desc->len1 = 0; + this_desc->len2 = 0; + + if (this_is_head) { + sah_Free_Head_Descriptor(head_desc); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Head_Descriptor: %p\n", + head_desc); + LOG_KDIAG(Diag_msg); +#endif + this_is_head = 0; + } else { + /* free this descriptor */ + sah_Free_Descriptor(this_desc); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Descriptor: %p\n", this_desc); + LOG_KDIAG(Diag_msg); +#endif + } + + /* Set up for next round. */ + this_desc = (sah_Desc *) next_desc; + } +} + +/*! +******************************************************************************* +* This walks through a SAHARA link chain and frees everything that is +* not NULL excluding user-space buffers. +* +* @brief Kernel Link Chain Destructor +* +* @param link A Link pointer from kernel-space. +* +* @return void +* +*/ +void sah_Destroy_Links(sah_Link * link) +{ + sah_Link *this_link = link; + sah_Link *next_link = NULL; + + while (this_link != NULL) { + + /* if this link indicates an associated page, process it */ + if (this_link->vm_info != NULL) { + /* since this function is only called from the routine that + * creates a kernel copy of the user space descriptor chain, + * there are no pages to dirty. All that is needed is to release + * the page from cache */ + page_cache_release(this_link->vm_info); + } + + /* Get a bus pointer to the next Link */ + next_link = (this_link->original_next + ? this_link->original_next : this_link->next); + + /* Zero the Pointer and Length fields for security reasons. */ + this_link->data = NULL; + this_link->len = 0; + + /* Free this Link */ + sah_Free_Link(this_link); +#ifdef DIAG_MEM + sprintf(Diag_msg, "Free_Link: %p\n", this_link); + LOG_KDIAG(Diag_msg); +#endif + + /* Look at the next Link */ + this_link = next_link; + } +} + +/*! +******************************************************************************* +* @brief Initialize memory manager/mapper. +* +* In 2.4, this function also allocates a kiovec to be used when mapping user +* data to kernel space +* +* @return 0 for success, OS error code on failure +* +*/ +int sah_Init_Mem_Map(void) +{ + int ret = OS_ERROR_FAIL_S; + + mem_lock = os_lock_alloc_init(); + + /* + * If one of these fails, change the calculation in the #define earlier in + * the file to be the other one. + */ + if (sizeof(sah_Link) > MEM_BLOCK_SIZE) { + os_printk("Sahara Driver: sah_Link structure is too large\n"); + } else if (sizeof(sah_Desc) > MEM_BLOCK_SIZE) { + os_printk("Sahara Driver: sah_Desc structure is too large\n"); + } else { + ret = OS_ERROR_OK_S; + } + +#ifndef SELF_MANAGED_POOL + + big_dma_pool = dma_pool_create("sah_big_blocks", NULL, + sizeof(Mem_Big_Block), sizeof(uint32_t), + PAGE_SIZE); + small_dma_pool = dma_pool_create("sah_small_blocks", NULL, + sizeof(Mem_Block), sizeof(uint32_t), + PAGE_SIZE); +#else + +#endif + return ret; +} + +/*! +******************************************************************************* +* @brief Clean up memory manager/mapper. +* +* In 2.4, this function also frees the kiovec used when mapping user data to +* kernel space. +* +* @return none +* +*/ +void sah_Stop_Mem_Map(void) +{ + os_lock_deallocate(mem_lock); + +#ifndef SELF_MANAGED_POOL + if (big_dma_pool != NULL) { + dma_pool_destroy(big_dma_pool); + } + if (small_dma_pool != NULL) { + dma_pool_destroy(small_dma_pool); + } +#endif +} + +/*! +******************************************************************************* +* Allocate Head descriptor from free pool. +* +* @brief Allocate Head descriptor +* +* @return sah_Head_Desc Free descriptor, NULL if no free descriptors available. +* +*/ +sah_Head_Desc *sah_Alloc_Head_Descriptor(void) +{ + Mem_Big_Block *block; + sah_Head_Desc *desc; + + block = sah_Alloc_Big_Block(); + if (block != NULL) { + /* initialize everything */ + desc = (sah_Head_Desc *) block->data; + + desc->desc.virt_addr = (sah_Desc *) desc; + desc->desc.dma_addr = block->dma_addr; + desc->desc.original_ptr1 = NULL; + desc->desc.original_ptr2 = NULL; + desc->desc.original_next = NULL; + + desc->desc.ptr1 = NULL; + desc->desc.ptr2 = NULL; + desc->desc.next = NULL; + } else { + desc = NULL; + } + + return desc; +} + +/*! +******************************************************************************* +* Allocate descriptor from free pool. +* +* @brief Allocate descriptor +* +* @return sah_Desc Free descriptor, NULL if no free descriptors available. +* +*/ +sah_Desc *sah_Alloc_Descriptor(void) +{ + Mem_Block *block; + sah_Desc *desc; + + block = sah_Alloc_Block(); + if (block != NULL) { + /* initialize everything */ + desc = (sah_Desc *) block->data; + + desc->virt_addr = desc; + desc->dma_addr = block->dma_addr; + desc->original_ptr1 = NULL; + desc->original_ptr2 = NULL; + desc->original_next = NULL; + + desc->ptr1 = NULL; + desc->ptr2 = NULL; + desc->next = NULL; + } else { + desc = NULL; + } + + return (desc); +} + +/*! +******************************************************************************* +* Allocate link from free pool. +* +* @brief Allocate link +* +* @return sah_Link Free link, NULL if no free links available. +* +*/ +sah_Link *sah_Alloc_Link(void) +{ + Mem_Block *block; + sah_Link *link; + + block = sah_Alloc_Block(); + if (block != NULL) { + /* initialize everything */ + link = (sah_Link *) block->data; + + link->virt_addr = link; + link->original_next = NULL; + link->original_data = NULL; + /* information found in allocated block */ + link->dma_addr = block->dma_addr; + + /* Sahara link fields */ + link->len = 0; + link->data = NULL; + link->next = NULL; + + /* driver required fields */ + link->flags = 0; + link->vm_info = NULL; + } else { + link = NULL; + } + + return link; +} + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Add a new page to end of block free pool. This will allocate one page and +* fill the pool with entries, appending to the end. +* +* @brief Add page of blocks to block free pool. +* +* @pre This function must be called with the #mem_lock held. +* +* @param big 0 - make blocks big enough for sah_Desc +* non-zero - make blocks big enough for sah_Head_Desc +* +* @return int TRUE if blocks added succeesfully, FALSE otherwise +* +*/ +int sah_Block_Add_Page(int big) +{ + void *page; + int success; + dma_addr_t dma_addr; + unsigned block_index; + uint32_t dma_offset; + unsigned block_entries = + big ? MEM_BIG_BLOCK_ENTRIES : MEM_BLOCK_ENTRIES; + unsigned block_size = big ? sizeof(Mem_Big_Block) : sizeof(Mem_Block); + void *block; + + /* Allocate page of memory */ +#ifndef USE_COHERENT_MEMORY + page = os_alloc_memory(PAGE_SIZE, GFP_ATOMIC | __GFP_DMA); + dma_addr = os_pa(page); +#else + page = os_alloc_coherent(PAGE_SIZE, &dma_addr, GFP_ATOMIC); +#endif + if (page != NULL) { + /* + * Find the difference between the virtual address and the DMA + * address of the page. This is used later to determine the DMA + * address of each individual block. + */ + dma_offset = page - (void *)dma_addr; + + /* Split page into blocks and add to free pool */ + block = page; + for (block_index = 0; block_index < block_entries; + block_index++) { + if (big) { + register Mem_Big_Block *blockp = block; + blockp->dma_addr = + (uint32_t) (block - dma_offset); + sah_Append_Big_Block(blockp); + } else { + register Mem_Block *blockp = block; + blockp->dma_addr = + (uint32_t) (block - dma_offset); + /* sah_Append_Block must be protected with spin locks. This is + * done in sah_Alloc_Block(), which calls + * sah_Block_Add_Page() */ + sah_Append_Block(blockp); + } + block += block_size; + } + success = TRUE; +#ifdef DIAG_MEM + LOG_KDIAG("Succeeded in allocating new page"); +#endif + } else { + success = FALSE; +#ifdef DIAG_MEM + LOG_KDIAG("Failed in allocating new page"); +#endif + } + + return success; +} +#endif /* SELF_MANAGED_POOL */ + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Allocate block from free pool. A block is large enough to fit either a link +* or descriptor. +* +* @brief Allocate memory block +* +* @return Mem_Block Free block, NULL if no free blocks available. +* +*/ +static Mem_Big_Block *sah_Alloc_Big_Block(void) +{ + Mem_Big_Block *block; + os_lock_context_t lock_flags; + + os_lock_save_context(mem_lock, lock_flags); + + /* If the pool is empty, try to allocate more entries */ + if (big_block_free_head == NULL) { + (void)sah_Block_Add_Page(1); + } + + /* Check that the pool now has some free entries */ + if (big_block_free_head != NULL) { + /* Return the head of the free pool */ + block = big_block_free_head; + + big_block_free_head = big_block_free_head->next; + if (big_block_free_head == NULL) { + /* Allocated last entry in pool */ + big_block_free_tail = NULL; + } + } else { + block = NULL; + } + os_unlock_restore_context(mem_lock, lock_flags); + + return block; +} +#else +/*! +******************************************************************************* +* Allocate block from free pool. A block is large enough to fit either a link +* or descriptor. +* +* @brief Allocate memory block +* +* @return Mem_Block Free block, NULL if no free blocks available. +* +*/ +static Mem_Big_Block *sah_Alloc_Big_Block(void) +{ + dma_addr_t dma_addr; + Mem_Big_Block *block = + dma_pool_alloc(big_dma_pool, GFP_ATOMIC, &dma_addr); + + if (block == NULL) { + } else { + block->dma_addr = dma_addr; + } + + return block; +} +#endif + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Allocate block from free pool. A block is large enough to fit either a link +* or descriptor. +* +* @brief Allocate memory block +* +* @return Mem_Block Free block, NULL if no free blocks available. +* +*/ +/****************************************************************************** +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 31/10/2003 RWK PR52734 - Implement functions to allocate +* descriptors and links. Replace +* consistent_alloc() calls. Initial creation. +* +******************************************************************************/ +static Mem_Block *sah_Alloc_Block(void) +{ + Mem_Block *block; + os_lock_context_t lock_flags; + + os_lock_save_context(mem_lock, lock_flags); + + /* If the pool is empty, try to allocate more entries */ + if (block_free_head == NULL) { + (void)sah_Block_Add_Page(0); + } + + /* Check that the pool now has some free entries */ + if (block_free_head != NULL) { + /* Return the head of the free pool */ + block = block_free_head; + + block_free_head = block_free_head->next; + if (block_free_head == NULL) { + /* Allocated last entry in pool */ + block_free_tail = NULL; + } + } else { + block = NULL; + } + os_unlock_restore_context(mem_lock, lock_flags); + + return block; +} +#else +/*! +******************************************************************************* +* Allocate block from free pool. A block is large enough to fit either a link +* or descriptor. +* +* @brief Allocate memory block +* +* @return Mem_Block Free block, NULL if no free blocks available. +* +*/ +/****************************************************************************** +* +* MODIFICATION HISTORY: +* +* Date Person Change +* 31/10/2003 RWK PR52734 - Implement functions to allocate +* descriptors and links. Replace +* consistent_alloc() calls. Initial creation. +* +******************************************************************************/ +static Mem_Block *sah_Alloc_Block(void) +{ + + dma_addr_t dma_addr; + Mem_Block *block = + dma_pool_alloc(small_dma_pool, GFP_ATOMIC, &dma_addr); + + if (block == NULL) { + } else { + block->dma_addr = dma_addr; + } + + return block; +} +#endif + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Free memory block back to free pool +* +* @brief Free memory block +* +* @param block A block allocated with sah_Alloc_Block(). +* +* @return none +* +*/ +static void sah_Free_Block(Mem_Block * block) +{ + os_lock_context_t lock_flags; + + os_lock_save_context(mem_lock, lock_flags); + sah_Append_Block(block); + os_unlock_restore_context(mem_lock, lock_flags); +} +#else +/*! +******************************************************************************* +* Free memory block back to free pool +* +* @brief Free memory block +* +* @param block A block allocated with sah_Alloc_Block(). +* +* @return none +* +*/ +static void sah_Free_Block(Mem_Block * block) +{ + dma_pool_free(small_dma_pool, block, block->dma_addr); +} +#endif + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Free memory block back to free pool +* +* @brief Free memory block +* +* @param block A block allocated with sah_Alloc_Block(). +* +* @return none +* +*/ +static void sah_Free_Big_Block(Mem_Big_Block * block) +{ + os_lock_context_t lock_flags; + + os_lock_save_context(mem_lock, lock_flags); + sah_Append_Big_Block(block); + os_unlock_restore_context(mem_lock, lock_flags); +} +#else +/*! +******************************************************************************* +* Free memory block back to free pool +* +* @brief Free memory block +* +* @param block A block allocated with sah_Alloc_Block(). +* +* @return none +* +*/ +static void sah_Free_Big_Block(Mem_Big_Block * block) +{ + dma_pool_free(big_dma_pool, block, block->dma_addr); +} +#endif + +#ifdef SELF_MANAGED_POOL +/*! +******************************************************************************* +* Append memory block to end of free pool. +* +* @param block A block entry +* +* @return none +* +* @pre This function must be called with the #mem_lock held. +* +* @brief Append memory block to free pool +*/ +static void sah_Append_Big_Block(Mem_Big_Block * block) +{ + + /* Initialise block */ + block->next = NULL; + + /* Remember that block may be the first in the pool */ + if (big_block_free_tail != NULL) { + big_block_free_tail->next = block; + } else { + /* Pool is empty */ + big_block_free_head = block; + } + + big_block_free_tail = block; +} + +/*! +******************************************************************************* +* Append memory block to end of free pool. +* +* @brief Append memory block to free pool +* +* @param block A block entry +* +* @return none +* +* @pre #mem_lock must be held +* +*/ +static void sah_Append_Block(Mem_Block * block) +{ + + /* Initialise block */ + block->next = NULL; + + /* Remember that block may be the first in the pool */ + if (block_free_tail != NULL) { + block_free_tail->next = block; + } else { + /* Pool is empty */ + block_free_head = block; + } + + block_free_tail = block; +} +#endif /* SELF_MANAGED_POOL */ + +/* End of sah_memory_mapper.c */ diff --git a/drivers/mxc/security/sahara2/sah_queue.c b/drivers/mxc/security/sahara2/sah_queue.c new file mode 100644 index 000000000000..317a60b92b6b --- /dev/null +++ b/drivers/mxc/security/sahara2/sah_queue.c @@ -0,0 +1,249 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_queue.c +* +* @brief This file provides a FIFO Queue implementation. +* +*/ +/****************************************************************************** +* +* CAUTION: +******************************************************************* +*/ + +/* SAHARA Includes */ +#include +#ifdef DIAG_DRV_QUEUE +#include +#endif + +/****************************************************************************** +* Queue Functions +******************************************************************************/ + +/*! +******************************************************************************* +* This function constructs a new sah_Queue. +* +* @brief sah_Queue Constructor +* +* @return A pointer to a newly allocated sah_Queue. +* @return NULL if allocation of memory failed. +*/ +/****************************************************************************** +* +* CAUTION: This function may sleep in low-memory situations, as it uses +* kmalloc ( ..., GFP_KERNEL). +******************************************************************************/ +sah_Queue *sah_Queue_Construct(void) +{ + sah_Queue *q = (sah_Queue *) os_alloc_memory(sizeof(sah_Queue), + GFP_KERNEL); + + if (q != NULL) { + /* Initialise the queue to an empty state. */ + q->head = NULL; + q->tail = NULL; + q->count = 0; + } +#ifdef DIAG_DRV_QUEUE + else { + LOG_KDIAG("kmalloc() failed."); + } +#endif + + return q; +} + +/*! +******************************************************************************* +* This function destroys a sah_Queue. +* +* @brief sah_Queue Destructor +* +* @param q A pointer to a sah_Queue. +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: This function does not free any queue entries. +* +******************************************************************************/ +void sah_Queue_Destroy(sah_Queue * q) +{ +#ifdef DIAG_DRV_QUEUE + if (q == NULL) { + LOG_KDIAG("Trying to kfree() a NULL pointer."); + } else { + if (q->count != 0) { + LOG_KDIAG + ("Trying to destroy a queue that is not empty."); + } + } +#endif + + if (q != NULL) { + os_free_memory(q); + q = NULL; + } +} + +/*! +******************************************************************************* +* This function appends a sah_Head_Desc to the tail of a sah_Queue. +* +* @brief Appends a sah_Head_Desc to a sah_Queue. +* +* @param q A pointer to a sah_Queue to append to. +* @param entry A pointer to a sah_Head_Desc to append. +* +* @pre The #desc_queue_lock must be held before calling this function. +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: NONE +******************************************************************************/ +void sah_Queue_Append_Entry(sah_Queue * q, sah_Head_Desc * entry) +{ + sah_Head_Desc *tail_entry = NULL; + + if ((q == NULL) || (entry == NULL)) { +#ifdef DIAG_DRV_QUEUE + LOG_KDIAG("Null pointer input."); +#endif + return; + } + + if (q->count == 0) { + /* The queue is empty */ + q->head = entry; + q->tail = entry; + entry->next = NULL; + entry->prev = NULL; + } else { + /* The queue is not empty */ + tail_entry = q->tail; + tail_entry->next = entry; + entry->next = NULL; + entry->prev = tail_entry; + q->tail = entry; + } + q->count++; +} + +/*! +******************************************************************************* +* This function a removes a sah_Head_Desc from the head of a sah_Queue. +* +* @brief Removes a sah_Head_Desc from a the head of a sah_Queue. +* +* @param q A pointer to a sah_Queue to remove from. +* +* @pre The #desc_queue_lock must be held before calling this function. +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: This does not kfree() the entry. +******************************************************************************/ +void sah_Queue_Remove_Entry(sah_Queue * q) +{ + sah_Queue_Remove_Any_Entry(q, q->head); +} + +/*! +******************************************************************************* +* This function a removes a sah_Head_Desc from anywhere in a sah_Queue. +* +* @brief Removes a sah_Head_Desc from anywhere in a sah_Queue. +* +* @param qq A pointer to a sah_Queue to remove from. +* @param entry A pointer to a sah_Head_Desc to remove. +* +* @pre The #desc_queue_lock must be held before calling this function. +* +* @return void +*/ +/****************************************************************************** +* +* CAUTION: This does not kfree() the entry. Does not check to see if the entry +* actually belongs to the queue. +******************************************************************************/ +void sah_Queue_Remove_Any_Entry(sah_Queue * q, sah_Head_Desc * entry) +{ + sah_Head_Desc *prev_entry = NULL; + sah_Head_Desc *next_entry = NULL; + + if ((q == NULL) || (entry == NULL)) { +#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT + LOG_KDIAG("Null pointer input."); +#endif + return; + } + + if (q->count == 1) { + /* If q is the only entry in the queue. */ + q->tail = NULL; + q->head = NULL; + q->count = 0; + } else if (q->count > 1) { + /* There are 2 or more entries in the queue. */ + +#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT + if ((entry->next == NULL) && (entry->prev == NULL)) { + LOG_KDIAG + ("Queue is not empty yet both next and prev pointers" + " are NULL"); + } +#endif + + if (entry->next == NULL) { + /* If this is the end of the queue */ + prev_entry = entry->prev; + prev_entry->next = NULL; + q->tail = prev_entry; + } else if (entry->prev == NULL) { + /* If this is the head of the queue */ + next_entry = entry->next; + next_entry->prev = NULL; + q->head = next_entry; + } else { + /* If this is somewhere in the middle of the queue */ + prev_entry = entry->prev; + next_entry = entry->next; + prev_entry->next = next_entry; + next_entry->prev = prev_entry; + } + q->count--; + } + /* + * Otherwise we are removing an entry from an empty queue. + * Don't do anything in the product code + */ +#if defined DIAG_DRV_QUEUE && defined DIAG_DURING_INTERRUPT + else { + LOG_KDIAG("Trying to remove an entry from an empty queue."); + } +#endif + + entry->next = NULL; + entry->prev = NULL; +} + +/* End of sah_queue.c */ diff --git a/drivers/mxc/security/sahara2/sah_queue_manager.c b/drivers/mxc/security/sahara2/sah_queue_manager.c new file mode 100644 index 000000000000..78de3543cd23 --- /dev/null +++ b/drivers/mxc/security/sahara2/sah_queue_manager.c @@ -0,0 +1,1076 @@ +/* + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file sah_queue_manager.c + * + * @brief This file provides a Queue Manager implementation. + * + * The Queue Manager manages additions and removal from the queue and updates + * the status of queue entries. It also calls sah_HW_* functions to interract + * with the hardware. +*/ + +#include "portable_os.h" + +/* SAHARA Includes */ +#include +#include +#include +#include +#if defined(DIAG_DRV_QUEUE) || defined(DIAG_DRV_STATUS) +#include +#endif +#include + +#ifdef DIAG_DRV_STATUS + +#define FSL_INVALID_RETURN 13 +#define MAX_RETURN_STRING_LEN 22 +#endif + +/* Defines for parsing value from Error Status register */ +#define SAH_STATUS_MASK 0x07 +#define SAH_ERROR_MASK 0x0F +#define SAH_CHA_ERR_SOURCE_MASK 0x07 +#define SAH_CHA_ERR_STATUS_MASK 0x0FFF +#define SAH_DMA_ERR_STATUS_MASK 0x0F +#define SAH_DMA_ERR_SIZE_MASK 0x03 +#define SAH_DMA_ERR_DIR_MASK 0x01 + +#define SHA_ERROR_STATUS_CONTINUE 0xFFFFFFFF +#define SHA_CHA_ERROR_STATUS_DONE 0xFFFFFFFF + +/* this maps the error status register's error source 4 bit field to the API + * return values. A 0xFFFFFFFF indicates additional fields must be checked to + * determine an appropriate return value */ +static sah_Execute_Error sah_Execute_Error_Array[] = { + FSL_RETURN_ERROR_S, /* SAH_ERR_NONE */ + FSL_RETURN_BAD_FLAG_S, /* SAH_ERR_HEADER */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_DESC_LENGTH */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_DESC_POINTER */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_LINK_LENGTH */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_LINK_POINTER */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_ERR_INPUT_BUFFER */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_ERR_OUTPUT_BUFFER */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_ERR_OUTPUT_BUFFER_STARVATION */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_ERR_INTERNAL_STATE */ + FSL_RETURN_ERROR_S, /* SAH_ERR_GENERAL_DESCRIPTOR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_ERR_RESERVED_FIELDS */ + FSL_RETURN_MEMORY_ERROR_S, /* SAH_ERR_DESCRIPTOR_ADDRESS */ + FSL_RETURN_MEMORY_ERROR_S, /* SAH_ERR_LINK_ADDRESS */ + SHA_ERROR_STATUS_CONTINUE, /* SAH_ERR_CHA */ + SHA_ERROR_STATUS_CONTINUE /* SAH_ERR_DMA */ +}; + +static sah_DMA_Error_Status sah_DMA_Error_Status_Array[] = { + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_NO_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_AHB_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_IP_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_PARITY_ERR */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_DMA_BOUNDRY_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_BUSY_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_DMA_RESERVED_ERR */ + FSL_RETURN_INTERNAL_ERROR_S /* SAH_DMA_INT_ERR */ +}; + +static sah_CHA_Error_Status sah_CHA_Error_Status_Array[] = { + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_CHA_NO_ERR */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_CHA_IP_BUF */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_CHA_ADD_ERR */ + FSL_RETURN_BAD_MODE_S, /* SAH_CHA_MODE_ERR */ + FSL_RETURN_BAD_DATA_LENGTH_S, /* SAH_CHA_DATA_SIZE_ERR */ + FSL_RETURN_BAD_KEY_LENGTH_S, /* SAH_CHA_KEY_SIZE_ERR */ + FSL_RETURN_BAD_MODE_S, /* SAH_CHA_PROC_ERR */ + FSL_RETURN_ERROR_S, /* SAH_CHA_CTX_READ_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_CHA_INTERNAL_HW_ERR */ + FSL_RETURN_MEMORY_ERROR_S, /* SAH_CHA_IP_BUFF_ERR */ + FSL_RETURN_MEMORY_ERROR_S, /* SAH_CHA_OP_BUFF_ERR */ + FSL_RETURN_BAD_KEY_PARITY_S, /* SAH_CHA_DES_KEY_ERR */ + FSL_RETURN_INTERNAL_ERROR_S, /* SAH_CHA_RES */ +}; + +#ifdef DIAG_DRV_STATUS + +char sah_return_text[FSL_INVALID_RETURN][MAX_RETURN_STRING_LEN] = { + "No error", /* FSL_RETURN_OK_S */ + "Error", /* FSL_RETURN_ERROR_S */ + "No resource", /* FSL_RETURN_NO_RESOURCE_S */ + "Bad algorithm", /* FSL_RETURN_BAD_ALGORITHM_S */ + "Bad mode", /* FSL_RETURN_BAD_MODE_S */ + "Bad flag", /* FSL_RETURN_BAD_FLAG_S */ + "Bad key length", /* FSL_RETURN_BAD_KEY_LENGTH_S */ + "Bad key parity", /* FSL_RETURN_BAD_KEY_PARITY_S */ + "Bad data length", /* FSL_RETURN_BAD_DATA_LENGTH_S */ + "Authentication failed", /* FSL_RETURN_AUTH_FAILED_S */ + "Memory error", /* FSL_RETURN_MEMORY_ERROR_S */ + "Internal error", /* FSL_RETURN_INTERNAL_ERROR_S */ + "unknown value", /* default */ +}; + +#endif /* DIAG_DRV_STATUS */ + +/*! + * This lock must be held while performing any queuing or unqueuing functions, + * including reading the first pointer on the queue. It also protects reading + * and writing the Sahara DAR register. It must be held during a read-write + * operation on the DAR so that the 'test-and-set' is atomic. + */ +os_lock_t desc_queue_lock; + +/*! This is the main queue for the driver. This is shared between all threads + * and is not protected by mutexes since the kernel is non-preemptable. */ +sah_Queue *main_queue = NULL; + +/* Internal Prototypes */ +sah_Head_Desc *sah_Find_With_State(sah_Queue_Status state); + +#ifdef DIAG_DRV_STATUS +void sah_Log_Error(uint32_t descriptor, uint32_t error, uint32_t fault_address); +#endif + +extern wait_queue_head_t *int_queue; + +/*! + * This function initialises the Queue Manager + * + * @brief Initialise the Queue Manager + * + * @return FSL_RETURN_OK_S on success; FSL_RETURN_MEMORY_ERROR_S if not + */ +fsl_shw_return_t sah_Queue_Manager_Init(void) +{ + fsl_shw_return_t ret_val = FSL_RETURN_OK_S; + + desc_queue_lock = os_lock_alloc_init(); + + if (main_queue == NULL) { + /* Construct the main queue. */ + main_queue = sah_Queue_Construct(); + + if (main_queue == NULL) { + ret_val = FSL_RETURN_MEMORY_ERROR_S; + } + } else { +#ifdef DIAG_DRV_QUEUE + LOG_KDIAG + ("Trying to initialise the queue manager more than once."); +#endif + } + + return ret_val; +} + +/*! + * This function closes the Queue Manager + * + * @brief Close the Queue Manager + * + * @return void + */ +void sah_Queue_Manager_Close(void) +{ +#ifdef DIAG_DRV_QUEUE + if (main_queue && main_queue->count != 0) { + LOG_KDIAG + ("Trying to close the main queue when it is not empty."); + } +#endif + + if (main_queue) { + /* There is no error checking here because there is no way to handle + it. */ + sah_Queue_Destroy(main_queue); + main_queue = NULL; + } +} + +/*! + * Count the number of entries on the Queue Manager's queue + * + * @param ignore_state If non-zero, the @a state parameter is ignored. + * If zero, only entries matching @a state are counted. + * @param state State of entry to match for counting. + * + * @return Number of entries which matched criteria + */ +int sah_Queue_Manager_Count_Entries(int ignore_state, sah_Queue_Status state) +{ + int count = 0; + sah_Head_Desc *current_entry; + + /* Start at the head */ + current_entry = main_queue->head; + while (current_entry != NULL) { + if (ignore_state || (current_entry->status == state)) { + count++; + } + /* Jump to the next entry. */ + current_entry = current_entry->next; + } + + return count; +} + +/*! + * This function removes an entry from the Queue Manager's queue. The entry to + * be removed can be anywhere in the queue. + * + * @brief Remove an entry from the Queue Manager's queue. + * + * @param entry A pointer to a sah_Head_Desc to remove from the Queue + * Manager's queue. + * + * @pre The #desc_queue_lock must be held before calling this function. + * + * @return void + */ +void sah_Queue_Manager_Remove_Entry(sah_Head_Desc * entry) +{ + if (entry == NULL) { +#ifdef DIAG_DRV_QUEUE + LOG_KDIAG("NULL pointer input."); +#endif + } else { + sah_Queue_Remove_Any_Entry(main_queue, entry); + } +} + +/*! + * This function appends an entry to the Queue Managers queue. It primes SAHARA + * if this entry is the first PENDING entry in the Queue Manager's Queue. + * + * @brief Appends an entry to the Queue Manager's queue. + * + * @param entry A pointer to a sah_Head_Desc to append to the Queue + * Manager's queue. + * + * @pre The #desc_queue_lock may not may be held when calling this function. + * + * @return void + */ +void sah_Queue_Manager_Append_Entry(sah_Head_Desc * entry) +{ + sah_Head_Desc *current_entry; + os_lock_context_t int_flags; + +#ifdef DIAG_DRV_QUEUE + if (entry == NULL) { + LOG_KDIAG("NULL pointer input."); + } +#endif + entry->status = SAH_STATE_PENDING; + os_lock_save_context(desc_queue_lock, int_flags); + sah_Queue_Append_Entry(main_queue, entry); + + /* Prime SAHARA if the operation that was just appended is the only PENDING + * operation in the queue. + */ + current_entry = sah_Find_With_State(SAH_STATE_PENDING); + if (current_entry != NULL) { + if (current_entry == entry) { + sah_Queue_Manager_Prime(entry); + } + } + + os_unlock_restore_context(desc_queue_lock, int_flags); +} + +/*! + * This function marks all entries in the Queue Manager's queue with state + * SAH_STATE_RESET. + * + * @brief Mark all entries with state SAH_STATE_RESET + * + * @return void + * + * @note This feature needs re-visiting + */ +void sah_Queue_Manager_Reset_Entries(void) +{ + sah_Head_Desc *current_entry = NULL; + + /* Start at the head */ + current_entry = main_queue->head; + + while (current_entry != NULL) { + /* Set the state. */ + current_entry->status = SAH_STATE_RESET; + /* Jump to the next entry. */ + current_entry = current_entry->next; + } +} + +/*! + * This function primes SAHARA for the first time or after the queue becomes + * empty. Queue lock must have been set by the caller of this routine. + * + * @brief Prime SAHARA. + * + * @param entry A pointer to a sah_Head_Desc to Prime SAHARA with. + * + * @return void + */ +void sah_Queue_Manager_Prime(sah_Head_Desc * entry) +{ +#ifdef DIAG_DRV_QUEUE + LOG_KDIAG("Priming SAHARA"); + if (entry == NULL) { + LOG_KDIAG("Trying to prime SAHARA with a NULL entry pointer."); + } +#endif + +#ifndef SUBMIT_MULTIPLE_DARS + /* BUG FIX: state machine can transition from Done1 Busy2 directly + * to Idle. To fix that problem, only one DAR is being allowed on + * SAHARA at a time */ + if (sah_Find_With_State(SAH_STATE_ON_SAHARA) != NULL) { + return; + } +#endif + +#ifdef SAHARA_POWER_MANAGEMENT + /* check that dynamic power management is not asserted */ + if (!sah_dpm_flag) { +#endif + + /* Enable the SAHARA Clocks */ +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA : Enabling the IPG and AHB clocks\n") +#endif /*DIAG_DRV_IF */ + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_enable(SAHARA2_CLK); +#else + { + struct clk *clk = clk_get(NULL, "sahara_clk"); + if (!IS_ERR(clk)) + clk_enable(clk); + clk_put(clk); + } +#endif + + /* Make sure nothing is in the DAR */ + if (sah_HW_Read_DAR() == 0) { +#if defined(DIAG_DRV_IF) + sah_Dump_Chain(&entry->desc, entry->desc.dma_addr); +#endif /* DIAG_DRV_IF */ + + sah_HW_Write_DAR((entry->desc.dma_addr)); + entry->status = SAH_STATE_ON_SAHARA; + } +#ifdef DIAG_DRV_QUEUE + else { + LOG_KDIAG("DAR should be empty when Priming SAHARA"); + } +#endif +#ifdef SAHARA_POWER_MANAGEMENT + } +#endif +} + +#ifndef SAHARA_POLL_MODE + +/*! + * Reset SAHARA, then load the next descriptor on it, if one exists + */ +void sah_reset_sahara_request(void) +{ + sah_Head_Desc *desc; + os_lock_context_t lock_flags; + +#ifdef DIAG_DRV_STATUS + LOG_KDIAG("Sahara required reset from tasklet, replace chip"); +#endif + sah_HW_Reset(); + + /* Now stick in a waiting request */ + os_lock_save_context(desc_queue_lock, lock_flags); + if ((desc = sah_Find_With_State(SAH_STATE_PENDING))) { + sah_Queue_Manager_Prime(desc); + } + os_unlock_restore_context(desc_queue_lock, lock_flags); +} + +/*! + * Post-process a descriptor chain after the hardware has finished with it. + * + * The status of the descriptor could also be checked. (for FATAL or IGNORED). + * + * @param desc_head The finished chain + * @param error A boolean to mark whether hardware reported error + * + * @pre The #desc_queue_lock may not be held when calling this function. + */ +void sah_process_finished_request(sah_Head_Desc * desc_head, unsigned error) +{ + os_lock_context_t lock_flags; + + if (!error) { + desc_head->result = FSL_RETURN_OK_S; + } else if (desc_head->error_status == -1) { + /* Disaster! Sahara has faulted */ + desc_head->result = FSL_RETURN_ERROR_S; + } else { + /* translate from SAHARA error status to fsl_shw return values */ + desc_head->result = + sah_convert_error_status(desc_head->error_status); +#ifdef DIAG_DRV_STATUS + sah_Log_Error(desc_head->desc.dma_addr, desc_head->error_status, + desc_head->fault_address); +#endif + } + + /* Show that the request has been processd */ + desc_head->status = error ? SAH_STATE_FAILED : SAH_STATE_COMPLETE; + + if (desc_head->uco_flags & FSL_UCO_BLOCKING_MODE) { + + /* Wake up all processes on Sahara queue */ + wake_up_interruptible(int_queue); + + } else { + os_lock_save_context(desc_queue_lock, lock_flags); + sah_Queue_Append_Entry(&desc_head->user_info->result_pool, + desc_head); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + /* perform callback */ + if (desc_head->uco_flags & FSL_UCO_CALLBACK_MODE) { + desc_head->user_info->callback(desc_head->user_info); + } + } +} /* sah_process_finished_request */ + +/*! Called from bottom half. + * + * @pre The #desc_queue_lock may not be held when calling this function. + */ +void sah_postprocess_queue(unsigned long reset_flag) +{ + + sah_Head_Desc *first_entry; + os_lock_context_t lock_flags; + + /* Disabling Sahara Clock only if the hardware is in idle state and + the DAR queue is empty.*/ + os_lock_save_context(desc_queue_lock, lock_flags); + first_entry = sah_Find_With_State(SAH_STATE_ON_SAHARA); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + if ((first_entry == NULL) && (sah_HW_Read_Status() == SAH_EXEC_IDLE)) { + +#ifdef DIAG_DRV_IF + LOG_KDIAG("SAHARA : Disabling the clocks\n") +#endif /* DIAG_DRV_IF */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_disable(SAHARA2_CLK); +#else + { + struct clk *clk = clk_get(NULL, "sahara_clk"); + if (!IS_ERR(clk)) + clk_disable(clk); + clk_put(clk); + } +#endif + + } + + + /* if SAHARA needs to be reset, do it here. This starts a descriptor chain + * if one is ready also */ + if (reset_flag) { + sah_reset_sahara_request(); + } + + /* now handle the descriptor chain(s) that has/have completed */ + do { + + os_lock_save_context(desc_queue_lock, lock_flags); + + first_entry = main_queue->head; + if ((first_entry != NULL) && + (first_entry->status == SAH_STATE_OFF_SAHARA)) { + sah_Queue_Remove_Entry(main_queue); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + sah_process_finished_request(first_entry, + (first_entry-> + error_status != 0)); + } else { + os_unlock_restore_context(desc_queue_lock, lock_flags); + break; + } + } while (1); + + return; +} + +#endif /* ifndef SAHARA_POLL_MODE */ + +/*! + * This is a helper function for Queue Manager. This function finds the first + * entry in the Queue Manager's queue whose state matches the given input + * state. This function starts at the head of the queue and works towards the + * tail. If a matching entry was found, the address of the entry is returned. + * + * @brief Handle the IDLE state. + * + * @param state A sah_Queue_Status value. + * + * @pre The #desc_queue_lock must be held before calling this function. + * + * @return A pointer to a sah_Head_Desc that matches the given state. + * @return NULL otherwise. + */ +sah_Head_Desc *sah_Find_With_State(sah_Queue_Status state) +{ + sah_Head_Desc *current_entry = NULL; + sah_Head_Desc *ret_val = NULL; + int done_looping = FALSE; + + /* Start at the head */ + current_entry = main_queue->head; + + while ((current_entry != NULL) && (done_looping == FALSE)) { + if (current_entry->status == state) { + done_looping = TRUE; + ret_val = current_entry; + } + /* Jump to the next entry. */ + current_entry = current_entry->next; + } + + return ret_val; +} /* sah_postprocess_queue */ + +/*! + * Process the value from the Sahara error status register and convert it into + * an FSL SHW API error code. + * + * Warning, this routine must only be called if an error exists. + * + * @param error_status The value from the error status register. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_convert_error_status(uint32_t error_status) +{ + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; /* catchall */ + uint8_t error_source; + uint8_t DMA_error_status; + uint8_t DMA_error_size; + + /* get the error source from the error status register */ + error_source = error_status & SAH_ERROR_MASK; + + /* array size is maximum allowed by mask, so no boundary checking is + * needed here */ + ret = sah_Execute_Error_Array[error_source]; + + /* is this one that needs additional fields checked to determine the + * error condition? */ + if (ret == SHA_ERROR_STATUS_CONTINUE) { + /* check the DMA fields */ + if (error_source == SAH_ERR_DMA) { + /* get the DMA transfer error size. If this indicates that no + * error was detected, something is seriously wrong */ + DMA_error_size = + (error_status >> 9) & SAH_DMA_ERR_SIZE_MASK; + if (DMA_error_size == SAH_DMA_NO_ERR) { + ret = FSL_RETURN_INTERNAL_ERROR_S; + } else { + /* get DMA error status */ + DMA_error_status = (error_status >> 12) & + SAH_DMA_ERR_STATUS_MASK; + + /* the DMA error bits cover all the even numbers. By dividing + * by 2 it can be used as an index into the error array */ + ret = + sah_DMA_Error_Status_Array[DMA_error_status + >> 1]; + } + } else { /* not SAH_ERR_DMA, so must be SAH_ERR_CHA */ + uint16_t CHA_error_status; + uint8_t CHA_error_source; + + /* get CHA Error Source. If this indicates that no error was + * detected, something is seriously wrong */ + CHA_error_source = + (error_status >> 28) & SAH_CHA_ERR_SOURCE_MASK; + if (CHA_error_source == SAH_CHA_NO_ERROR) { + ret = FSL_RETURN_INTERNAL_ERROR_S; + } else { + uint32_t mask = 1; + uint32_t count = 0; + + /* get CHA Error Status */ + CHA_error_status = (error_status >> 16) & + SAH_CHA_ERR_STATUS_MASK; + + /* If more than one bit is set (which shouldn't happen), only + * the first will be captured */ + if (CHA_error_status != 0) { + count = 1; + while (CHA_error_status != mask) { + ++count; + mask <<= 1; + } + } + + ret = sah_CHA_Error_Status_Array[count]; + } + } + } + + return ret; +} + +fsl_shw_return_t sah_convert_op_status(uint32_t op_status) +{ + unsigned op_source = (op_status >> 28) & 0x7; + unsigned op_detail = op_status & 0x3f; + fsl_shw_return_t ret = FSL_RETURN_ERROR_S; + + switch (op_source) { + case 1: /* SKHA */ + /* Can't this have "ICV" error from CCM ?? */ + break; + case 2: /* MDHA */ + if (op_detail == 1) { + ret = FSL_RETURN_AUTH_FAILED_S; + } + break; + case 3: /* RNGA */ + /* Self-test and Compare errors... what to do? */ + break; + case 4: /* PKHA */ + switch (op_detail) { + case 0x01: + ret = FSL_RETURN_PRIME_S; + break; + case 0x02: + ret = FSL_RETURN_NOT_PRIME_S; + break; + case 0x04: + ret = FSL_RETURN_POINT_AT_INFINITY_S; + break; + case 0x08: + ret = FSL_RETURN_POINT_NOT_AT_INFINITY_S; + break; + case 0x10: + ret = FSL_RETURN_GCD_IS_ONE_S; + break; + case 0x20: + ret = FSL_RETURN_GCD_IS_NOT_ONE_S; + break; + default: + break; + } + break; + default: + break; + } + return ret; +} + +#ifdef DIAG_DRV_STATUS + +/*! + * This function logs the diagnostic information for the given error and + * descriptor address. Only used for diagnostic purposes. + * + * @brief (debug only) Log a description of hardware-detected error. + * + * @param descriptor The descriptor address that caused the error + * @param error The SAHARA error code + * @param fault_address Value from the Fault address register + * + * @return void + */ +void sah_Log_Error(uint32_t descriptor, uint32_t error, uint32_t fault_address) +{ + char *source_text; /* verbose error source from register */ + char *address; /* string buffer for descriptor address */ + char *error_log; /* the complete logging message */ + char *cha_log = NULL; /* string buffer for descriptor address */ + char *dma_log = NULL; /* string buffer for descriptor address */ + + uint16_t cha_error = 0; + uint16_t dma_error = 0; + + uint8_t error_source; + sah_Execute_Error return_code; + + /* log error code and descriptor address */ + error_source = error & SAH_ERROR_MASK; + return_code = sah_Execute_Error_Array[error_source]; + + source_text = os_alloc_memory(64, GFP_KERNEL); + + switch (error_source) { + case SAH_ERR_HEADER: + sprintf(source_text, "%s", "Header is not valid"); + break; + + case SAH_ERR_DESC_LENGTH: + sprintf(source_text, "%s", + "Descriptor length not equal to sum of link lengths"); + break; + + case SAH_ERR_DESC_POINTER: + sprintf(source_text, "%s", "Length or pointer " + "field is zero while the other is non-zero"); + break; + + case SAH_ERR_LINK_LENGTH: + /* note that the Sahara Block Guide 2.7 has an invalid explaination + * of this. It only happens when a link length is zero */ + sprintf(source_text, "%s", "A data length is a link is zero"); + break; + + case SAH_ERR_LINK_POINTER: + sprintf(source_text, "%s", + "The data pointer in a link is zero"); + break; + + case SAH_ERR_INPUT_BUFFER: + sprintf(source_text, "%s", "Input Buffer reported an overflow"); + break; + + case SAH_ERR_OUTPUT_BUFFER: + sprintf(source_text, "%s", + "Output Buffer reported an underflow"); + break; + + case SAH_ERR_OUTPUT_BUFFER_STARVATION: + sprintf(source_text, "%s", "Incorrect data in output " + "buffer after CHA has signalled 'done'"); + break; + + case SAH_ERR_INTERNAL_STATE: + sprintf(source_text, "%s", "Internal Hardware Failure"); + break; + + case SAH_ERR_GENERAL_DESCRIPTOR: + sprintf(source_text, "%s", + "Current Descriptor was not legal, but cause is unknown"); + break; + + case SAH_ERR_RESERVED_FIELDS: + sprintf(source_text, "%s", + "Reserved pointer field is non-zero"); + break; + + case SAH_ERR_DESCRIPTOR_ADDRESS: + sprintf(source_text, "%s", + "Descriptor address not word aligned"); + break; + + case SAH_ERR_LINK_ADDRESS: + sprintf(source_text, "%s", "Link address not word aligned"); + break; + + case SAH_ERR_CHA: + sprintf(source_text, "%s", "CHA Error"); + { + char *cha_module = os_alloc_memory(5, GFP_KERNEL); + char *cha_text = os_alloc_memory(45, GFP_KERNEL); + + cha_error = (error >> 28) & SAH_CHA_ERR_SOURCE_MASK; + + switch (cha_error) { + case SAH_CHA_SKHA_ERROR: + sprintf(cha_module, "%s", "SKHA"); + break; + + case SAH_CHA_MDHA_ERROR: + sprintf(cha_module, "%s", "MDHA"); + break; + + case SAH_CHA_RNG_ERROR: + sprintf(cha_module, "%s", "RNG "); + break; + + case SAH_CHA_PKHA_ERROR: + sprintf(cha_module, "%s", "PKHA"); + break; + + case SAH_CHA_NO_ERROR: + /* can't happen */ + /* no break */ + default: + sprintf(cha_module, "%s", "????"); + break; + } + + cha_error = (error >> 16) & SAH_CHA_ERR_STATUS_MASK; + + /* Log CHA Error Status */ + switch (cha_error) { + case SAH_CHA_IP_BUF: + sprintf(cha_text, "%s", + "Non-empty input buffer when done"); + break; + + case SAH_CHA_ADD_ERR: + sprintf(cha_text, "%s", "Illegal address"); + break; + + case SAH_CHA_MODE_ERR: + sprintf(cha_text, "%s", "Illegal mode"); + break; + + case SAH_CHA_DATA_SIZE_ERR: + sprintf(cha_text, "%s", "Illegal data size"); + break; + + case SAH_CHA_KEY_SIZE_ERR: + sprintf(cha_text, "%s", "Illegal key size"); + break; + + case SAH_CHA_PROC_ERR: + sprintf(cha_text, "%s", + "Mode/Context/Key written during processing"); + break; + + case SAH_CHA_CTX_READ_ERR: + sprintf(cha_text, "%s", + "Context read during processing"); + break; + + case SAH_CHA_INTERNAL_HW_ERR: + sprintf(cha_text, "%s", "Internal hardware"); + break; + + case SAH_CHA_IP_BUFF_ERR: + sprintf(cha_text, "%s", + "Input buffer not enabled or underflow"); + break; + + case SAH_CHA_OP_BUFF_ERR: + sprintf(cha_text, "%s", + "Output buffer not enabled or overflow"); + break; + + case SAH_CHA_DES_KEY_ERR: + sprintf(cha_text, "%s", "DES key parity error"); + break; + + case SAH_CHA_RES: + sprintf(cha_text, "%s", "Reserved"); + break; + + case SAH_CHA_NO_ERR: + /* can't happen */ + /* no break */ + default: + sprintf(cha_text, "%s", "Unknown error"); + break; + } + + cha_log = os_alloc_memory(90, GFP_KERNEL); + sprintf(cha_log, + " Module %s encountered the error: %s.", + cha_module, cha_text); + + os_free_memory(cha_module); + os_free_memory(cha_text); + + { + uint32_t mask = 1; + uint32_t count = 0; + + if (cha_error != 0) { + count = 1; + while (cha_error != mask) { + ++count; + mask <<= 1; + } + } + + return_code = sah_CHA_Error_Status_Array[count]; + } + cha_error = 1; + } + break; + + case SAH_ERR_DMA: + sprintf(source_text, "%s", "DMA Error"); + { + char *dma_direction = os_alloc_memory(6, GFP_KERNEL); + char *dma_size = os_alloc_memory(14, GFP_KERNEL); + char *dma_text = os_alloc_memory(250, GFP_KERNEL); + + if ((dma_direction == NULL) || (dma_size == NULL) || + (dma_text == NULL)) { + LOG_KDIAG + ("No memory allocated for DMA debug messages\n"); + } + + /* log DMA error direction */ + sprintf(dma_direction, "%s", + (((error >> 8) & SAH_DMA_ERR_DIR_MASK) == 1) ? + "read" : "write"); + + /* log the size of the DMA transfer error */ + dma_error = (error >> 9) & SAH_DMA_ERR_SIZE_MASK; + switch (dma_error) { + case SAH_DMA_SIZE_BYTE: + sprintf(dma_size, "%s", "byte"); + break; + + case SAH_DMA_SIZE_HALF_WORD: + sprintf(dma_size, "%s", "half-word"); + break; + + case SAH_DMA_SIZE_WORD: + sprintf(dma_size, "%s", "word"); + break; + + case SAH_DMA_SIZE_RES: + sprintf(dma_size, "%s", "reserved size"); + break; + + default: + sprintf(dma_size, "%s", "unknown size"); + break; + } + + /* log DMA error status */ + dma_error = (error >> 12) & SAH_DMA_ERR_STATUS_MASK; + switch (dma_error) { + case SAH_DMA_NO_ERR: + sprintf(dma_text, "%s", "No DMA Error Code"); + break; + + case SAH_DMA_AHB_ERR: + sprintf(dma_text, "%s", + "AHB terminated a bus cycle with an error"); + break; + + case SAH_DMA_IP_ERR: + sprintf(dma_text, "%s", + "Internal IP bus cycle was terminated with an " + "error termination. This would likely be " + "caused by a descriptor length being too " + "large, and thus accessing an illegal " + "internal address. Verify the length field " + "of the current descriptor"); + break; + + case SAH_DMA_PARITY_ERR: + sprintf(dma_text, "%s", + "Parity error detected on DMA command from " + "Descriptor Decoder. Cause is likely to be " + "internal hardware fault"); + break; + + case SAH_DMA_BOUNDRY_ERR: + sprintf(dma_text, "%s", + "DMA was requested to cross a 256 byte " + "internal address boundary. Cause is likely a " + "descriptor length being too large, thus " + "accessing two different internal hardware " + "blocks"); + break; + + case SAH_DMA_BUSY_ERR: + sprintf(dma_text, "%s", + "Descriptor Decoder has made a DMA request " + "while the DMA controller is busy. Cause is " + "likely due to hardware fault"); + break; + + case SAH_DMA_RESERVED_ERR: + sprintf(dma_text, "%s", "Reserved"); + break; + + case SAH_DMA_INT_ERR: + sprintf(dma_text, "%s", + "Internal DMA hardware error detected. The " + "DMA controller has detected an internal " + "condition which should never occur"); + break; + + default: + sprintf(dma_text, "%s", + "Unknown DMA Error Status Code"); + break; + } + + return_code = + sah_DMA_Error_Status_Array[dma_error >> 1]; + dma_error = 1; + + dma_log = os_alloc_memory(320, GFP_KERNEL); + sprintf(dma_log, + " Occurred during a %s operation of a %s transfer: %s.", + dma_direction, dma_size, dma_text); + + os_free_memory(dma_direction); + os_free_memory(dma_size); + os_free_memory(dma_text); + } + break; + + case SAH_ERR_NONE: + default: + sprintf(source_text, "%s", "Unknown Error Code"); + break; + } + + address = os_alloc_memory(35, GFP_KERNEL); + + /* convert error & descriptor address to strings */ + if (dma_error) { + sprintf(address, "Fault address is 0x%08x", fault_address); + } else { + sprintf(address, "Descriptor bus address is 0x%08x", + descriptor); + } + + if (return_code > FSL_INVALID_RETURN) { + return_code = FSL_INVALID_RETURN; + } + + error_log = os_alloc_memory(250, GFP_KERNEL); + + /* construct final log message */ + sprintf(error_log, "Error source = 0x%08x. Return = %s. %s. %s.", + error, sah_return_text[return_code], address, source_text); + + os_free_memory(source_text); + os_free_memory(address); + + /* log standard messages */ + LOG_KDIAG(error_log); + os_free_memory(error_log); + + /* add additional information if available */ + if (cha_error) { + LOG_KDIAG(cha_log); + os_free_memory(cha_log); + } + + if (dma_error) { + LOG_KDIAG(dma_log); + os_free_memory(dma_log); + } + + return; +} /* sah_Log_Error */ + +#endif /* DIAG_DRV_STATUS */ + +/* End of sah_queue_manager.c */ diff --git a/drivers/mxc/security/sahara2/sah_status_manager.c b/drivers/mxc/security/sahara2/sah_status_manager.c new file mode 100644 index 000000000000..f881b47591c2 --- /dev/null +++ b/drivers/mxc/security/sahara2/sah_status_manager.c @@ -0,0 +1,714 @@ +/* + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! +* @file sah_status_manager.c +* +* @brief Status Manager Function +* +* This file contains the function which processes the Sahara status register +* during an interrupt. +* +* This file does not need porting. +*/ + +#include "portable_os.h" + +#include +#include +#include +#include +#include + +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) +#include +#endif + +/*! Compile-time flag to count various interrupt types. */ +#define DIAG_INT_COUNT + +/*! + * Number of interrupts processed with Done1Done2 status. Updates to this + * value should only be done in interrupt processing. + */ +uint32_t done1_count; + +/*! + * Number of interrupts processed with Done1Busy2 status. Updates to this + * value should only be done in interrupt processing. + */ +uint32_t done1busy2_count; + +/*! + * Number of interrupts processed with Done1Done2 status. Updates to this + * value should only be done in interrupt processing. + */ +uint32_t done1done2_count; + +/*! + * the dynameic power management flag is false when power management is not + * asserted and true when dpm is. + */ +#ifdef SAHARA_POWER_MANAGEMENT +bool sah_dpm_flag = FALSE; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static int sah_dpm_suspend(struct device *dev, uint32_t state, uint32_t level); +static int sah_dpm_resume(struct device *dev, uint32_t level); +#else +static int sah_dpm_suspend(struct platform_device *dev, pm_message_t state); +static int sah_dpm_resume(struct platform_device *dev); +#endif +#endif + +#ifndef SAHARA_POLL_MODE +/*! +******************************************************************************* +* This functionx processes the status register of the Sahara, updates the state +* of the finished queue entry, and then tries to find more work for Sahara to +* do. +* +* @brief The bulk of the interrupt handling code. +* +* @param hw_status The status register of Sahara at time of interrupt. +* The Clear interrupt bit is already handled by this +* register read prior to entry into this function. +* @return void +*/ +unsigned long sah_Handle_Interrupt(sah_Execute_Status hw_status) +{ + unsigned long reset_flag = 0; /* assume no SAHARA reset needed */ + os_lock_context_t lock_flags; + sah_Head_Desc *current_entry; + + /* HW status at time of interrupt */ + sah_Execute_Status state = hw_status & SAH_EXEC_STATE_MASK; + + do { + uint32_t dar; + +#ifdef DIAG_INT_COUNT + if (state == SAH_EXEC_DONE1) { + done1_count++; + } else if (state == SAH_EXEC_DONE1_BUSY2) { + done1busy2_count++; + } else if (state == SAH_EXEC_DONE1_DONE2) { + done1done2_count++; + } +#endif + + /* if the first entry on sahara has completed... */ + if ((state & SAH_EXEC_DONE1_BIT) || + (state == SAH_EXEC_ERROR1)) { + /* lock queue while searching */ + os_lock_save_context(desc_queue_lock, lock_flags); + current_entry = + sah_Find_With_State(SAH_STATE_ON_SAHARA); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + /* an active descriptor was not found */ + if (current_entry == NULL) { + /* change state to avoid an infinite loop (possible if + * state is SAH_EXEC_DONE1_BUSY2 first time into loop) */ + hw_status = SAH_EXEC_IDLE; +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + LOG_KDIAG + ("Interrupt received with nothing on queue."); +#endif + } else { + /* SAHARA has completed its work on this descriptor chain */ + current_entry->status = SAH_STATE_OFF_SAHARA; + + if (state == SAH_EXEC_ERROR1) { + if (hw_status & STATUS_ERROR) { + /* Gather extra diagnostic information */ + current_entry->fault_address = + sah_HW_Read_Fault_Address(); + /* Read this last - it clears the error */ + current_entry->error_status = + sah_HW_Read_Error_Status(); + current_entry->op_status = 0; +#ifdef FSL_HAVE_SAHARA4 + } else { + current_entry->op_status = + sah_HW_Read_Op_Status(); + current_entry->error_status = 0; +#endif + } + + } else { + /* indicate that no errors were found with descriptor + * chain 1 */ + current_entry->error_status = 0; + current_entry->op_status = 0; + + /* is there a second, successfully, completed descriptor + * chain? (done1/error2 processing is handled later) */ + if (state == SAH_EXEC_DONE1_DONE2) { + os_lock_save_context + (desc_queue_lock, + lock_flags); + current_entry = + sah_Find_With_State + (SAH_STATE_ON_SAHARA); + os_unlock_restore_context + (desc_queue_lock, + lock_flags); + + if (current_entry == NULL) { +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + LOG_KDIAG + ("Done1_Done2 Interrupt received with " + "one entry on queue."); +#endif + } else { + /* indicate no errors in descriptor chain 2 */ + current_entry-> + error_status = 0; + current_entry->status = + SAH_STATE_OFF_SAHARA; + } + } + } + } + +#ifdef SAHARA_POWER_MANAGEMENT + /* check dynamic power management is not asserted */ + if (!sah_dpm_flag) { +#endif + do { + /* protect DAR and main_queue */ + os_lock_save_context(desc_queue_lock, + lock_flags); + dar = sah_HW_Read_DAR(); + /* check if SAHARA has space for another descriptor. SAHARA + * only accepts up to the DAR queue size number of DAR + * entries, after that 'dar' will not be zero until the + * pending interrupt is serviced */ + if (dar == 0) { + current_entry = + sah_Find_With_State + (SAH_STATE_PENDING); + if (current_entry != NULL) { +#ifndef SUBMIT_MULTIPLE_DARS + /* BUG FIX: state machine can transition from Done1 + * Busy2 directly to Idle. To fix that problem, + * only one DAR is being allowed on SAHARA at a + * time. If a high level interrupt has happened, + * there could * be an active descriptor chain */ + if (sah_Find_With_State + (SAH_STATE_ON_SAHARA) + == NULL) { +#endif +#if defined(DIAG_DRV_IF) && defined(DIAG_DURING_INTERRUPT) + sah_Dump_Chain + (¤t_entry-> + desc, + current_entry-> + desc. + dma_addr); +#endif /* DIAG_DRV_IF */ + sah_HW_Write_DAR + (current_entry-> + desc. + dma_addr); + current_entry-> + status = + SAH_STATE_ON_SAHARA; +#ifndef SUBMIT_MULTIPLE_DARS + } + current_entry = NULL; /* exit loop */ +#endif + } + } + os_unlock_restore_context + (desc_queue_lock, lock_flags); + } while ((dar == 0) && (current_entry != NULL)); +#ifdef SAHARA_POWER_MANAGEMENT + } /* sah_device_power_manager */ +#endif + } else { + if (state == SAH_EXEC_FAULT) { + sah_Head_Desc *previous_entry; /* point to chain 1 */ + /* Address of request when fault occured */ + uint32_t bad_dar = sah_HW_Read_IDAR(); + + reset_flag = 1; /* SAHARA needs to be reset */ + + /* get first of possible two descriptor chain that was + * on SAHARA */ + os_lock_save_context(desc_queue_lock, + lock_flags); + previous_entry = + sah_Find_With_State(SAH_STATE_ON_SAHARA); + os_unlock_restore_context(desc_queue_lock, + lock_flags); + + /* if it exists, continue processing the fault */ + if (previous_entry) { + /* assume this chain didn't complete correctly */ + previous_entry->error_status = -1; + previous_entry->status = + SAH_STATE_OFF_SAHARA; + + /* get the second descriptor chain */ + os_lock_save_context(desc_queue_lock, + lock_flags); + current_entry = + sah_Find_With_State + (SAH_STATE_ON_SAHARA); + os_unlock_restore_context + (desc_queue_lock, lock_flags); + + /* if it exists, continue processing both chains */ + if (current_entry) { + /* assume this chain didn't complete correctly */ + current_entry->error_status = + -1; + current_entry->status = + SAH_STATE_OFF_SAHARA; + + /* now see if either can be identified as the one + * in progress when the fault occured */ + if (current_entry->desc. + dma_addr == bad_dar) { + /* the second descriptor chain was active when the + * fault occured, so the first descriptor chain + * was successfull */ + previous_entry-> + error_status = 0; + } else { + if (previous_entry-> + desc.dma_addr == + bad_dar) { + /* if the first chain was in progress when the + * fault occured, the second has not yet been + * touched, so reset it to PENDING */ + current_entry-> + status = + SAH_STATE_PENDING; + } + } + } + } +#if defined(DIAG_DRV_INTERRUPT) && defined(DIAG_DURING_INTERRUPT) + } else { + /* shouldn't ever get here */ + if (state == SAH_EXEC_BUSY) { + LOG_KDIAG + ("Got Sahara interrupt in Busy state"); + } else { + if (state == SAH_EXEC_IDLE) { + LOG_KDIAG + ("Got Sahara interrupt in Idle state"); + } else { + LOG_KDIAG + ("Got Sahara interrupt in unknown state"); + } + } +#endif + } + } + + /* haven't handled the done1/error2 (the error 2 part), so setup to + * do that now. Otherwise, exit loop */ + state = (state == SAH_EXEC_DONE1_ERROR2) ? + SAH_EXEC_ERROR1 : SAH_EXEC_IDLE; + + /* Keep going while further status is available. */ + } while (state == SAH_EXEC_ERROR1); + + return reset_flag; +} + +#endif /* ifndef SAHARA_POLL_MODE */ + +#ifdef SAHARA_POLL_MODE +/*! +******************************************************************************* +* Submits descriptor chain to SAHARA, polls on SAHARA for completion, process +* results, and dephysicalizes chain +* +* @brief Handle poll mode. +* +* @param entry Virtual address of a physicalized chain +* +* @return 0 this function is always successful +*/ + +unsigned long sah_Handle_Poll(sah_Head_Desc * entry) +{ + sah_Execute_Status hw_status; /* Sahara's status register */ + os_lock_context_t lock_flags; + + /* lock SARAHA */ + os_lock_save_context(desc_queue_lock, lock_flags); + +#ifdef SAHARA_POWER_MANAGEMENT + /* check if the dynamic power management is asserted */ + if (sah_dpm_flag) { + /* return that request failed to be processed */ + entry->result = FSL_RETURN_ERROR_S; + entry->fault_address = 0xBAD; + entry->op_status= 0xBAD; + entry->error_status = 0xBAD; + } else { +#endif /* SAHARA_POWER_MANAGEMENT */ + +#if defined(DIAG_DRV_IF) + sah_Dump_Chain(&entry->desc, entry->desc.dma_addr); +#endif /* DIAG_DRV_IF */ + /* Nothing can be in the dar if we got the lock */ + sah_HW_Write_DAR((uint32_t) (entry->desc.dma_addr)); + + /* Wait for SAHARA to finish with this entry */ + hw_status = sah_Wait_On_Sahara(); + + /* if entry completed successfully, mark it as such */ + /**** HARDWARE ERROR WORK AROUND (hw_status == SAH_EXEC_IDLE) *****/ + if ( +#ifndef SUBMIT_MULTIPLE_DARS + (hw_status == SAH_EXEC_IDLE) || (hw_status == SAH_EXEC_DONE1_BUSY2) || /* should not happen */ +#endif + (hw_status == SAH_EXEC_DONE1) + ) { + entry->error_status = 0; + entry->result = FSL_RETURN_OK_S; + } else { + /* SAHARA is reporting an error with entry */ + if (hw_status == SAH_EXEC_ERROR1) { + /* Gather extra diagnostic information */ + entry->fault_address = + sah_HW_Read_Fault_Address(); + /* Read this register last - it clears the error */ + entry->error_status = + sah_HW_Read_Error_Status(); + entry->op_status = 0; + /* translate from SAHARA error status to fsl_shw return values */ + entry->result = + sah_convert_error_status(entry-> + error_status); +#ifdef DIAG_DRV_STATUS + sah_Log_Error(entry->op_status, + entry->error_status, + entry->fault_address); +#endif + } else if (hw_status == SAH_EXEC_OPSTAT1) { + entry->op_status = sah_HW_Read_Op_Status(); + entry->error_status = 0; + entry->result = + sah_convert_op_status(op_status); + } else { + /* SAHARA entered FAULT state (or something bazaar has + * happened) */ + pr_debug + ("Sahara: hw_status = 0x%x; Stat: 0x%08x; IDAR: 0x%08x; " + "CDAR: 0x%08x; FltAdr: 0x%08x; Estat: 0x%08x\n", + hw_status, sah_HW_Read_Status(), + sah_HW_Read_IDAR(), sah_HW_Read_CDAR(), + sah_HW_Read_Fault_Address(), + sah_HW_Read_Error_Status()); +#ifdef DIAG_DRV_IF + { + int old_level = console_loglevel; + console_loglevel = 8; + sah_Dump_Chain(&(entry->desc), + entry->desc.dma_addr); + console_loglevel = old_level; + } +#endif + + entry->error_status = -1; + entry->result = FSL_RETURN_ERROR_S; + sah_HW_Reset(); + } + } +#ifdef SAHARA_POWER_MANAGEMENT + } +#endif + + if (!(entry->uco_flags & FSL_UCO_BLOCKING_MODE)) { + /* put it in results pool to allow get_results to work */ + sah_Queue_Append_Entry(&entry->user_info->result_pool, entry); + if (entry->uco_flags & FSL_UCO_CALLBACK_MODE) { + /* invoke callback */ + entry->user_info->callback(entry->user_info); + } + } else { + /* convert the descriptor link back to virtual memory, mark dirty pages + * if they are from user mode, and release the page cache for user + * pages + */ + entry = sah_DePhysicalise_Descriptors(entry); + } + + os_unlock_restore_context(desc_queue_lock, lock_flags); + + return 0; +} + +#endif /* SAHARA_POLL_MODE */ + +/****************************************************************************** +* The following is the implementation of the Dynamic Power Management +* functionality. +******************************************************************************/ +#ifdef SAHARA_POWER_MANAGEMENT + +static bool sah_dpm_init_flag; + +/* dynamic power management information for the sahara driver */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static struct device_driver sah_dpm_driver = { + .name = "sahara_", + .bus = &platform_bus_type, +#else +static struct platform_driver sah_dpm_driver = { + .driver.name = "sahara_", + .driver.bus = &platform_bus_type, +#endif + .suspend = sah_dpm_suspend, + .resume = sah_dpm_resume +}; + +/* dynamic power management information for the sahara HW device */ +static struct platform_device sah_dpm_device = { + .name = "sahara_", + .id = 1, +}; + +/*! +******************************************************************************* +* Initilaizes the dynamic power managment functionality +* +* @brief Initialization of the Dynamic Power Management functionality +* +* @return 0 = success; failed otherwise +*/ +int sah_dpm_init() +{ + int status; + + /* dpm is not asserted */ + sah_dpm_flag = FALSE; + + /* register the driver to the kernel */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + status = os_register_to_driver(&sah_dpm_driver); +#else + status = os_register_to_driver(&sah_dpm_driver.driver); +#endif + + if (status == 0) { + /* register a single sahara chip */ + /*status = platform_device_register(&sah_dpm_device); */ + status = os_register_a_device(&sah_dpm_device); + + /* if something went awry, unregister the driver */ + if (status != 0) { + /*driver_unregister(&sah_dpm_driver); */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + os_unregister_from_driver(&sah_dpm_driver); +#else + os_unregister_from_driver(&sah_dpm_driver.driver); +#endif + sah_dpm_init_flag = FALSE; + } else { + /* if everything went okay, flag that life is good */ + sah_dpm_init_flag = TRUE; + } + } + + /* let the kernel know how it went */ + return status; + +} + +/*! +******************************************************************************* +* Unregister the dynamic power managment functionality +* +* @brief Unregister the Dynamic Power Management functionality +* +*/ +void sah_dpm_close() +{ + /* if dynamic power management was initilaized, kill it */ + if (sah_dpm_init_flag == TRUE) { + /*driver_unregister(&sah_dpm_driver); */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + os_unregister_from_driver(&sah_dpm_driver); +#else + os_unregister_from_driver(&sah_dpm_driver.driver); +#endif + /*platform_device_register(&sah_dpm_device); */ + os_unregister_a_device(&sah_dpm_device); + } +} + +/*! +******************************************************************************* +* Callback routine defined by the Linux Device Model / Dynamic Power management +* extension. It sets a global flag to disallow the driver to enter queued items +* into Sahara's DAR. +* +* It allows the current active descriptor chains to complete before it returns +* +* @brief Suspends the driver +* +* @param dev contains device information +* @param state contains state information +* @param level level of shutdown +* +* @return 0 = success; failed otherwise +*/ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static int sah_dpm_suspend(struct device *dev, uint32_t state, uint32_t level) +#else +static int sah_dpm_suspend(struct platform_device *dev, pm_message_t state) +#endif +{ + sah_Head_Desc *entry = NULL; + os_lock_context_t lock_flags; + int error_code = 0; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + switch (level) { + case SUSPEND_DISABLE: + /* Assert dynamic power management. This stops the driver from + * entering queued requests to Sahara */ + sah_dpm_flag = TRUE; + break; + + case SUSPEND_SAVE_STATE: + break; + + case SUSPEND_POWER_DOWN: + /* hopefully between the DISABLE call and this one, the outstanding + * work Sahara was doing complete. this checks (and waits) for + * those entries that were already active on Sahara to complete */ + /* lock queue while searching */ + os_lock_save_context(desc_queue_lock, lock_flags); + do { + entry = sah_Find_With_State(SAH_STATE_ON_SAHARA); + } while (entry != NULL); + os_unlock_restore_context(desc_queue_lock, lock_flags); + + /* now we kill the clock so the control circuitry isn't sucking + * any power */ + mxc_clks_disable(SAHARA2_CLK); + break; + } +#else + /* Assert dynamic power management. This stops the driver from + * entering queued requests to Sahara */ + sah_dpm_flag = TRUE; + + /* Now wait for any outstanding work Sahara was doing to complete. + * this checks (and waits) for + * those entries that were already active on Sahara to complete */ + do { + /* lock queue while searching */ + os_lock_save_context(desc_queue_lock, lock_flags); + entry = sah_Find_With_State(SAH_STATE_ON_SAHARA); + os_unlock_restore_context(desc_queue_lock, lock_flags); + } while (entry != NULL); + + /* now we kill the clock so the control circuitry isn't sucking + * any power */ + { + struct clk *clk = clk_get(NULL, "sahara_clk"); + if (IS_ERR(clk)) + error_code = PTR_ERR(clk); + else + clk_disable(clk); + } +#endif + + return error_code; +} + +/*! +******************************************************************************* +* Callback routine defined by the Linux Device Model / Dynamic Power management +* extension. It cleears a global flag to allow the driver to enter queued items +* into Sahara's DAR. +* +* It primes the mechanism to start depleting the queue +* +* @brief Resumes the driver +* +* @param dev contains device information +* @param level level of resumption +* +* @return 0 = success; failed otherwise +*/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +static int sah_dpm_resume(struct device *dev, uint32_t level) +#else +static int sah_dpm_resume(struct platform_device *dev) +#endif +{ + sah_Head_Desc *entry = NULL; + os_lock_context_t lock_flags; + int error_code = 0; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) + switch (level) { + case RESUME_POWER_ON: + /* enable Sahara's clock */ + mxc_clks_enable(SAHARA2_CLK); + break; + + case RESUME_RESTORE_STATE: + break; + + case RESUME_ENABLE: + /* Disable dynamic power managment. This allows the driver to put + * entries into Sahara's DAR */ + sah_dpm_flag = FALSE; + + /* find a pending entry to prime the pump */ + os_lock_save_context(desc_queue_lock, lock_flags); + entry = sah_Find_With_State(SAH_STATE_PENDING); + if (entry != NULL) { + sah_Queue_Manager_Prime(entry); + } + os_unlock_restore_context(desc_queue_lock, lock_flags); + break; + } +#else + { + /* enable Sahara's clock */ + struct clk *clk = clk_get(NULL, "sahara_clk"); + + if (IS_ERR(clk)) + error_code = PTR_ERR(clk); + else + clk_disable(clk); + } + sah_dpm_flag = FALSE; + + /* find a pending entry to prime the pump */ + os_lock_save_context(desc_queue_lock, lock_flags); + entry = sah_Find_With_State(SAH_STATE_PENDING); + if (entry != NULL) { + sah_Queue_Manager_Prime(entry); + } + os_unlock_restore_context(desc_queue_lock, lock_flags); +#endif + return error_code; +} + +#endif /* SAHARA_POWER_MANAGEMENT */ diff --git a/drivers/mxc/security/sahara2/sf_util.c b/drivers/mxc/security/sahara2/sf_util.c new file mode 100644 index 000000000000..12cc0161f4d4 --- /dev/null +++ b/drivers/mxc/security/sahara2/sf_util.c @@ -0,0 +1,1390 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/** +* @file sf_util.c +* +* @brief Security Functions component API - Utility functions +* +* These are the 'Sahara api' functions which are used by the higher-level +* FSL SHW API to build and then execute descriptor chains. +*/ + + +#include "sf_util.h" +#include + +#ifdef DIAG_SECURITY_FUNC +#include +#endif /*DIAG_SECURITY_FUNC*/ + + +#ifdef __KERNEL__ +EXPORT_SYMBOL(sah_Append_Desc); +EXPORT_SYMBOL(sah_Append_Link); +EXPORT_SYMBOL(sah_Create_Link); +EXPORT_SYMBOL(sah_Create_Key_Link); +EXPORT_SYMBOL(sah_Destroy_Link); +EXPORT_SYMBOL(sah_Descriptor_Chain_Execute); +EXPORT_SYMBOL(sah_insert_mdha_algorithm); +EXPORT_SYMBOL(sah_insert_skha_algorithm); +EXPORT_SYMBOL(sah_insert_skha_mode); +EXPORT_SYMBOL(sah_insert_skha_modulus); +EXPORT_SYMBOL(sah_Descriptor_Chain_Destroy); +EXPORT_SYMBOL(sah_add_two_in_desc); +EXPORT_SYMBOL(sah_add_in_key_desc); +EXPORT_SYMBOL(sah_add_two_out_desc); +EXPORT_SYMBOL(sah_add_in_out_desc); +EXPORT_SYMBOL(sah_add_key_out_desc); +#endif + +#ifdef DEBUG_REWORK +#ifndef __KERNEL__ +#include +#define os_printk printf +#endif +#endif + +/** + * Convert fsl_shw_hash_alg_t to mdha mode bits. + * + * Index must be maintained in order of fsl_shw_hash_alg_t enumeration!!! + */ +const uint32_t sah_insert_mdha_algorithm[] = +{ + [FSL_HASH_ALG_MD5] = sah_insert_mdha_algorithm_md5, + [FSL_HASH_ALG_SHA1] = sah_insert_mdha_algorithm_sha1, + [FSL_HASH_ALG_SHA224] = sah_insert_mdha_algorithm_sha224, + [FSL_HASH_ALG_SHA256] = sah_insert_mdha_algorithm_sha256, +}; + +/** + * Header bits for Algorithm field of SKHA header + * + * Index value must be kept in sync with fsl_shw_key_alg_t + */ +const uint32_t sah_insert_skha_algorithm[] = +{ + [FSL_KEY_ALG_HMAC] = 0x00000040, + [FSL_KEY_ALG_AES] = sah_insert_skha_algorithm_aes, + [FSL_KEY_ALG_DES] = sah_insert_skha_algorithm_des, + [FSL_KEY_ALG_TDES] = sah_insert_skha_algorithm_tdes, + [FSL_KEY_ALG_ARC4] = sah_insert_skha_algorithm_arc4, +}; + + +/** + * Header bits for MODE field of SKHA header + * + * Index value must be kept in sync with fsl_shw_sym_mod_t + */ +const uint32_t sah_insert_skha_mode[] = +{ + [FSL_SYM_MODE_STREAM] = sah_insert_skha_mode_ecb, + [FSL_SYM_MODE_ECB] = sah_insert_skha_mode_ecb, + [FSL_SYM_MODE_CBC] = sah_insert_skha_mode_cbc, + [FSL_SYM_MODE_CTR] = sah_insert_skha_mode_ctr, +}; + + +/** + * Header bits to set CTR modulus size. These have parity + * included to allow XOR insertion of values. + * + * @note Must be kept in sync with fsl_shw_ctr_mod_t + */ +const uint32_t sah_insert_skha_modulus[] = +{ + [FSL_CTR_MOD_8] = 0x00000000, /**< 2**8 */ + [FSL_CTR_MOD_16] = 0x80000200, /**< 2**16 */ + [FSL_CTR_MOD_24] = 0x80000400, /**< 2**24 */ + [FSL_CTR_MOD_32] = 0x00000600, /**< 2**32 */ + [FSL_CTR_MOD_40] = 0x80000800, /**< 2**40 */ + [FSL_CTR_MOD_48] = 0x00000a00, /**< 2**48 */ + [FSL_CTR_MOD_56] = 0x00000c00, /**< 2**56 */ + [FSL_CTR_MOD_64] = 0x80000e00, /**< 2**64 */ + [FSL_CTR_MOD_72] = 0x80001000, /**< 2**72 */ + [FSL_CTR_MOD_80] = 0x00001200, /**< 2**80 */ + [FSL_CTR_MOD_88] = 0x00001400, /**< 2**88 */ + [FSL_CTR_MOD_96] = 0x80001600, /**< 2**96 */ + [FSL_CTR_MOD_104] = 0x00001800, /**< 2**104 */ + [FSL_CTR_MOD_112] = 0x80001a00, /**< 2**112 */ + [FSL_CTR_MOD_120] = 0x80001c00, /**< 2**120 */ + [FSL_CTR_MOD_128] = 0x00001e00 /**< 2**128 */ +}; + + +/****************************************************************************** +* Internal function declarations +******************************************************************************/ +static fsl_shw_return_t sah_Create_Desc( + const sah_Mem_Util *mu, + sah_Desc ** desc, + int head, + uint32_t header, + sah_Link * link1, + sah_Link * link2); + + +/** + * Create a descriptor chain using the the header and links passed in as + * parameters. The newly created descriptor will be added to the end of + * the descriptor chain passed. + * + * If @a desc_head points to a NULL value, then a sah_Head_Desc will be created + * as the first descriptor. Otherwise a sah_Desc will be created and appended. + * + * @pre + * + * - None + * + * @post + * + * - A descriptor has been created from the header, link1 and link2. + * + * - The newly created descriptor has been appended to the end of + * desc_head, or its location stored into the location pointed to by + * @a desc_head. + * + * - On allocation failure, @a link1 and @a link2 will be destroyed., and + * @a desc_head will be untouched. + * + * @brief Create and append descriptor chain, inserting header and links + * pointing to link1 and link2 + * + * @param mu Memory functions + * @param header Value of descriptor header to be added + * @param desc_head Pointer to head of descriptor chain to append new desc + * @param link1 Pointer to sah_Link 1 (or NULL) + * @param link2 Pointer to sah_Link 2 (or NULL) + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_Append_Desc( + const sah_Mem_Util *mu, + sah_Head_Desc **desc_head, + const uint32_t header, + sah_Link *link1, + sah_Link *link2) +{ + fsl_shw_return_t status; + sah_Desc *desc; + sah_Desc *desc_ptr; + + + status = sah_Create_Desc(mu, (sah_Desc**)&desc, (*desc_head == NULL), + header, link1, link2); + /* append newly created descriptor to end of current chain */ + if (status == FSL_RETURN_OK_S) { + if (*desc_head == NULL) { + (*desc_head) = (sah_Head_Desc*)desc; + (*desc_head)->out1_ptr = NULL; + (*desc_head)->out2_ptr = NULL; + + } else { + desc_ptr = (sah_Desc*)*desc_head; + while (desc_ptr->next != NULL) { + desc_ptr = desc_ptr->next; + } + desc_ptr->next = desc; + } + } + + return status; +} + + +/** + * Releases the memory allocated by the Security Function library for + * descriptors, links and any internally allocated memory referenced in the + * given chain. Note that memory allocated by user applications is not + * released. + * + * @post The @a desc_head pointer will be set to NULL to prevent further use. + * + * @brief Destroy a descriptor chain and free memory of associated links + * + * @param mu Memory functions + * @param desc_head Pointer to head of descriptor chain to be freed + * + * @return none + */ +void sah_Descriptor_Chain_Destroy ( + const sah_Mem_Util *mu, + sah_Head_Desc **desc_head) +{ + sah_Desc *desc_ptr = &(*desc_head)->desc; + sah_Head_Desc *desc_head_ptr = (sah_Head_Desc *)desc_ptr; + + while (desc_ptr != NULL) { + register sah_Desc *next_desc_ptr; + + if (desc_ptr->ptr1 != NULL) { + sah_Destroy_Link(mu, desc_ptr->ptr1); + } + if (desc_ptr->ptr2 != NULL) { + sah_Destroy_Link(mu, desc_ptr->ptr2); + } + + next_desc_ptr = desc_ptr->next; + + /* Be sure to free head descriptor as such */ + if (desc_ptr == (sah_Desc*)desc_head_ptr) { + mu->mu_free_head_desc(mu->mu_ref, desc_head_ptr); + } else { + mu->mu_free_desc(mu->mu_ref, desc_ptr); + } + + desc_ptr = next_desc_ptr; + } + + *desc_head = NULL; +} + + +#ifndef NO_INPUT_WORKAROUND +/** + * Reworks the link chain + * + * @brief Reworks the link chain + * + * @param mu Memory functions + * @param link Pointer to head of link chain to be reworked + * + * @return none + */ +static fsl_shw_return_t sah_rework_link_chain( + const sah_Mem_Util *mu, + sah_Link* link) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + int found_potential_problem = 0; + uint32_t total_data = 0; +#ifdef DEBUG_REWORK + sah_Link* first_link = link; +#endif + + if ((link->flags & SAH_OUTPUT_LINK)) { + return status; + } + + while (link != NULL) { + total_data += link->len; + + /* Only non-key Input Links are affected by the DMA flush-to-FIFO + * problem */ + + /* If have seen problem and at end of chain... */ + if (found_potential_problem && (link->next == NULL) && + (total_data > 16)) { + /* insert new 1-byte link */ + sah_Link* new_tail_link = mu->mu_alloc_link(mu->mu_ref); + if (new_tail_link == NULL) { + status = FSL_RETURN_NO_RESOURCE_S; + } else { +#ifdef DEBUG_REWORK + sah_Link* dump_link = first_link; + while (dump_link != NULL) { + uint32_t i; + unsigned bytes_to_dump = (dump_link->len > 32) ? + 32 : dump_link->len; + os_printk("(rework)Link %p: %p/%u/%p\n", dump_link, + dump_link->data, dump_link->len, + dump_link->next); + if (!(dump_link->flags & SAH_STORED_KEY_INFO)) { + os_printk("(rework)Data %p: ", dump_link->data); + for (i = 0; i < bytes_to_dump; i++) { + os_printk("%02X ", dump_link->data[i]); + } + os_printk("\n"); + } + else { + os_printk("rework)Data %p: Red key data\n", dump_link); + } + dump_link = dump_link->next; + } +#endif + link->len--; + link->next = new_tail_link; + new_tail_link->len = 1; + new_tail_link->data = link->data+link->len; + new_tail_link->flags = link->flags & ~(SAH_OWNS_LINK_DATA); + new_tail_link->next = NULL; + link = new_tail_link; +#ifdef DEBUG_REWORK + os_printk("(rework)New link chain:\n"); + dump_link = first_link; + while (dump_link != NULL) { + uint32_t i; + unsigned bytes_to_dump = (dump_link->len > 32) ? + 32 : dump_link->len; + + os_printk("Link %p: %p/%u/%p\n", dump_link, + dump_link->data, dump_link->len, + dump_link->next); + if (!(dump_link->flags & SAH_STORED_KEY_INFO)) { + os_printk("Data %p: ", dump_link->data); + for (i = 0; i < bytes_to_dump; i++) { + os_printk("%02X ", dump_link->data[i]); + } + os_printk("\n"); + } + else { + os_printk("Data %p: Red key data\n", dump_link); + } + dump_link = dump_link->next; + } +#endif + } + } else if ((link->len % 4) || ((uint32_t)link->data % 4)) { + found_potential_problem = 1; + } + + link = link->next; + } + + return status; +} + + +/** + * Rework links to avoid H/W bug + * + * @param head Beginning of descriptor chain + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t sah_rework_links( + const sah_Mem_Util *mu, + sah_Head_Desc *head) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Desc* desc = &head->desc; + + while ((status == FSL_RETURN_OK_S) && (desc != NULL)) { + if (desc->header & SAH_HDR_LLO) { + status = FSL_RETURN_ERROR_S; + break; + } + if (desc->ptr1 != NULL) { + status = sah_rework_link_chain(mu, desc->ptr1); + } + if ((status == FSL_RETURN_OK_S) && (desc->ptr2 != NULL)) { + status = sah_rework_link_chain(mu, desc->ptr2); + } + desc = desc->next; + } + + return status; +} +#endif /* NO_INPUT_WORKAROUND */ + + +/** + * Send a descriptor chain to the SAHARA driver for processing. + * + * Note that SAHARA will read the input data from and write the output data + * directly to the locations indicated during construction of the chain. + * + * @pre + * + * - None + * + * @post + * + * - @a head will have been executed on SAHARA + * - @a head Will be freed unless a SAVE flag is set + * + * @brief Execute a descriptor chain + * + * @param head Pointer to head of descriptor chain to be executed + * @param user_ctx The user context on which to execute the descriptor chain. + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_Descriptor_Chain_Execute( + sah_Head_Desc *head, + fsl_shw_uco_t *user_ctx) +{ + fsl_shw_return_t status; + + /* Check for null pointer or non-multiple-of-four value */ + if ((head == NULL) || ((uint32_t)head & 0x3)) { + status = FSL_RETURN_ERROR_S; + goto out; + } + +#ifndef NO_INPUT_WORKAROUND + status = sah_rework_links(user_ctx->mem_util, head); + if (status != FSL_RETURN_OK_S) { + goto out; + } +#endif + + /* complete the information in the descriptor chain head node */ + head->user_ref = user_ctx->user_ref; + head->uco_flags = user_ctx->flags; + head->next = NULL; /* driver will use this to link chain heads */ + + status = adaptor_Exec_Descriptor_Chain(head, user_ctx); + +#ifdef DIAG_SECURITY_FUNC + if (status == FSL_RETURN_OK_S) + LOG_DIAG("after exec desc chain: status is ok\n"); + else + LOG_DIAG("after exec desc chain: status is not ok\n"); +#endif + + out: + return status; +} + + +/** + * Create Link + * + * @brief Allocate Memory for Link structure and populate using input + * parameters + * + * @post On allocation failure, @a p will be freed if #SAH_OWNS_LINK_DATA is + * p set in @a flags. + + * @param mu Memory functions + * @param link Pointer to link to be created + * @param p Pointer to data to use in link + * @param length Length of buffer 'p' in bytes + * @param flags Indicates whether memory has been allocated by the calling + * function or the security function + * + * @return FSL_RETURN_OK_S or FSL_RETURN_NO_RESOURCE_S + */ +fsl_shw_return_t sah_Create_Link( + const sah_Mem_Util *mu, + sah_Link **link, + uint8_t *p, + const size_t length, + const sah_Link_Flags flags) +{ + +#ifdef DIAG_SECURITY_FUNC + + char diag[50]; +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S; + + + *link = mu->mu_alloc_link(mu->mu_ref); + + /* populate link if memory allocation successful */ + if (*link != NULL) { + (*link)->len = length; + (*link)->data = p; + (*link)->next = NULL; + (*link)->flags = flags; + status = FSL_RETURN_OK_S; + +#ifdef DIAG_SECURITY_FUNC + + LOG_DIAG("Created Link"); + LOG_DIAG("------------"); + sprintf(diag," address = 0x%x", (int) *link); + LOG_DIAG(diag); + sprintf(diag," link->len = %d",(*link)->len); + LOG_DIAG(diag); + sprintf(diag," link->data = 0x%x",(int) (*link)->data); + LOG_DIAG(diag); + sprintf(diag," link->flags = 0x%x",(*link)->flags); + LOG_DIAG(diag); + LOG_DIAG(" link->next = NULL"); +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + + } else { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Allocation of memory for sah_Link failed!\n"); +#endif /*DIAG_SECURITY_FUNC*/ + + /* Free memory previously allocated by the security function layer for + link data. Note that the memory being pointed to will be zeroed before + being freed, for security reasons. */ + if (flags & SAH_OWNS_LINK_DATA) { + mu->mu_memset(mu->mu_ref, p, 0x00, length); + mu->mu_free(mu->mu_ref, p); + } + } + + return status; +} + + +/** + * Create Key Link + * + * @brief Allocate Memory for Link structure and populate using key info + * object + * + * @param mu Memory functions + * @param link Pointer to store address of link to be created + * @param key_info Pointer to Key Info object to be referenced + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_Create_Key_Link( + const sah_Mem_Util *mu, + sah_Link **link, + fsl_shw_sko_t *key_info) +{ +#ifdef DIAG_SECURITY_FUNC_UGLY + char diag[50]; +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S; + sah_Link_Flags flags = 0; + + + *link = mu->mu_alloc_link(mu->mu_ref); + + /* populate link if memory allocation successful */ + if (*link != NULL) { + (*link)->len = key_info->key_length; + + if (key_info->flags & FSL_SKO_KEY_PRESENT) { + (*link)->data = key_info->key; + status = FSL_RETURN_OK_S; + } else { + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + + if (key_info->keystore == NULL) { + /* System Keystore */ + (*link)->slot = key_info->handle; + (*link)->ownerid = key_info->userid; + (*link)->data = 0; + flags |= SAH_STORED_KEY_INFO; + status = FSL_RETURN_OK_S; + } else { +#ifdef FSL_HAVE_SCC2 + /* User Keystore */ + fsl_shw_kso_t *keystore = key_info->keystore; + /* Note: the key data is stored here, but the address has to + * be converted to a partition and offset in the kernel. + * This will be calculated in kernel space, based on the + * list of partitions held by the users context. + */ + (*link)->data = + keystore->slot_get_address(keystore->user_data, + key_info->handle); + + flags |= SAH_IN_USER_KEYSTORE; + status = FSL_RETURN_OK_S; +#else + /* User keystores only supported in SCC2 */ + status = FSL_RETURN_BAD_FLAG_S; +#endif /* FSL_HAVE_SCC2 */ + + } + } else { + /* the flag is bad. Should never get here */ + status = FSL_RETURN_BAD_FLAG_S; + } + } + + (*link)->next = NULL; + (*link)->flags = flags; + +#ifdef DIAG_SECURITY_FUNC_UGLY + if (status == FSL_RETURN_OK_S) { + LOG_DIAG("Created Link"); + LOG_DIAG("------------"); + sprintf(diag," address = 0x%x", (int) *link); + LOG_DIAG(diag); + sprintf(diag," link->len = %d", (*link)->len); + LOG_DIAG(diag); + if (key_info->flags & FSL_SKO_KEY_ESTABLISHED) { + sprintf(diag," link->slot = 0x%x", (*link)->slot); + LOG_DIAG(diag); + } else { + sprintf(diag," link->data = 0x%x", (int)(*link)->data); + LOG_DIAG(diag); + } + sprintf(diag," link->flags = 0x%x", (*link)->flags); + LOG_DIAG(diag); + LOG_DIAG(" link->next = NULL"); + } +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + + if (status == FSL_RETURN_BAD_FLAG_S) { + mu->mu_free_link(mu->mu_ref, *link); + *link = NULL; +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Creation of sah_Key_Link failed due to bad key flag!\n"); +#endif /*DIAG_SECURITY_FUNC*/ + } + + } else { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Allocation of memory for sah_Key_Link failed!\n"); +#endif /*DIAG_SECURITY_FUNC*/ + } + + return status; +} + + +/** + * Append Link + * + * @brief Allocate Memory for Link structure and append it to the end of + * the link chain. + * + * @post On allocation failure, @a p will be freed if #SAH_OWNS_LINK_DATA is + * p set in @a flags. + * + * @param mu Memory functions + * @param link_head Pointer to (head of) existing link chain + * @param p Pointer to data to use in link + * @param length Length of buffer 'p' in bytes + * @param flags Indicates whether memory has been allocated by the calling + * function or the security function + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_Append_Link( + const sah_Mem_Util *mu, + sah_Link *link_head, + uint8_t *p, + const size_t length, + const sah_Link_Flags flags) +{ + sah_Link* new_link; + fsl_shw_return_t status; + + + status = sah_Create_Link(mu, &new_link, p, length, flags); + + if (status == FSL_RETURN_OK_S) { + /* chase for the tail */ + while (link_head->next != NULL) { + link_head = link_head->next; + } + + /* and add new tail */ + link_head->next = new_link; + } + + return status; +} + + +/** + * Create and populate a single descriptor + * + * The pointer and length fields will be be set based on the chains passed in + * as @a link1 and @a link2. + * + * @param mu Memory utility suite + * @param desc Location to store pointer of new descriptor + * @param head_desc Non-zero if this will be first in chain; zero otherwise + * @param header The Sahara header value to store in the descriptor + * @param link1 A value (or NULL) for the first ptr + * @param link2 A value (or NULL) for the second ptr + * + * @post If allocation succeeded, the @a link1 and @link2 will be linked into + * the descriptor. If allocation failed, those link structues will be + * freed, and the @a desc will be unchanged. + * + * @return A return code of type #fsl_shw_return_t. + */ +static fsl_shw_return_t sah_Create_Desc( + const sah_Mem_Util *mu, + sah_Desc ** desc, + int head_desc, + uint32_t header, + sah_Link * link1, + sah_Link * link2) +{ + fsl_shw_return_t status = FSL_RETURN_NO_RESOURCE_S; +#ifdef DIAG_SECURITY_FUNC_UGLY + char diag[50]; +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + + + if (head_desc != 0) { + *desc = (sah_Desc *)mu->mu_alloc_head_desc(mu->mu_ref); + } else { + *desc = mu->mu_alloc_desc(mu->mu_ref); + } + + /* populate descriptor if memory allocation successful */ + if ((*desc) != NULL) { + sah_Link* temp_link; + + status = FSL_RETURN_OK_S; + (*desc)->header = header; + + temp_link = (*desc)->ptr1 = link1; + (*desc)->len1 = 0; + while (temp_link != NULL) { + (*desc)->len1 += temp_link->len; + temp_link = temp_link->next; + } + + temp_link = (*desc)->ptr2 = link2; + (*desc)->len2 = 0; + while (temp_link != NULL) { + (*desc)->len2 += temp_link->len; + temp_link = temp_link->next; + } + + (*desc)->next = NULL; + +#ifdef DIAG_SECURITY_FUNC_UGLY + LOG_DIAG("Created Desc"); + LOG_DIAG("------------"); + sprintf(diag," address = 0x%x",(int) *desc); + LOG_DIAG(diag); + sprintf(diag," desc->header = 0x%x",(*desc)->header); + LOG_DIAG(diag); + sprintf(diag," desc->len1 = %d",(*desc)->len1); + LOG_DIAG(diag); + sprintf(diag," desc->ptr1 = 0x%x",(int) ((*desc)->ptr1)); + LOG_DIAG(diag); + sprintf(diag," desc->len2 = %d",(*desc)->len2); + LOG_DIAG(diag); + sprintf(diag," desc->ptr2 = 0x%x",(int) ((*desc)->ptr2)); + LOG_DIAG(diag); + sprintf(diag," desc->next = 0x%x",(int) ((*desc)->next)); + LOG_DIAG(diag); +#endif /*DIAG_SECURITY_FUNC_UGLY*/ + } else { +#ifdef DIAG_SECURITY_FUNC + LOG_DIAG("Allocation of memory for sah_Desc failed!\n"); +#endif /*DIAG_SECURITY_FUNC*/ + + /* Destroy the links, otherwise the memory allocated by the Security + Function layer for the links (and possibly the data within the links) + will be lost */ + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } + + return status; +} + + +/** + * Destroy a link (chain) and free memory + * + * @param mu memory utility suite + * @param link The Link to destroy + * + * @return none + */ +void sah_Destroy_Link( + const sah_Mem_Util *mu, + sah_Link * link) +{ + + while (link != NULL) { + sah_Link * next_link = link->next; + + if (link->flags & SAH_OWNS_LINK_DATA) { + /* zero data for security purposes */ + mu->mu_memset(mu->mu_ref, link->data, 0x00, link->len); + mu->mu_free(mu->mu_ref, link->data); + } + + link->data = NULL; + link->next = NULL; + mu->mu_free_link(mu->mu_ref, link); + + link = next_link; + } +} + + +/** + * Add descriptor where both links are inputs. + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The second input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_two_in_desc(uint32_t header, + const uint8_t* in1, + uint32_t in1_length, + const uint8_t* in2, + uint32_t in2_length, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link* link1 = NULL; + sah_Link* link2 = NULL; + + if (in1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in1, in1_length, SAH_USES_LINK_DATA); + } + + if ( (in2 != NULL) && (status == FSL_RETURN_OK_S) ) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) in2, in2_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + +/*! + * Add descriptor where neither link needs sync + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The second input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_two_d_desc(uint32_t header, + const uint8_t * in1, + uint32_t in1_length, + const uint8_t * in2, + uint32_t in2_length, + const sah_Mem_Util * mu, + sah_Head_Desc ** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + printk("Entering sah_add_two_d_desc \n"); + + if (in1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in1, in1_length, + SAH_USES_LINK_DATA); + } + + if ((in2 != NULL) && (status == FSL_RETURN_OK_S)) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) in2, in2_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} /* sah_add_two_d_desc() */ + +/** + * Add descriptor where both links are inputs, the second one being a key. + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The second input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_in_key_desc(uint32_t header, + const uint8_t* in1, + uint32_t in1_length, + fsl_shw_sko_t* key_info, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + if (in1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in1, in1_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + goto out; + } + + status = sah_Create_Key_Link(mu, &link2, key_info); + + + if (status != FSL_RETURN_OK_S) { + goto out; + } + + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + +out: + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } + + return status; +} + + +/** + * Create two links using keys allocated in the scc + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The second input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_key_key_desc(uint32_t header, + fsl_shw_sko_t *key_info1, + fsl_shw_sko_t *key_info2, + const sah_Mem_Util *mu, + sah_Head_Desc **desc_chain) +{ + fsl_shw_return_t status; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + + status = sah_Create_Key_Link(mu, &link1, key_info1); + + if (status == FSL_RETURN_OK_S) { + status = sah_Create_Key_Link(mu, &link2, key_info2); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + + +/** + * Add descriptor where first link is input, the second is a changing key + * + * @param header The Sahara header value for the descriptor. + * @param in1 The first input buffer (or NULL) + * @param in1_length Size of @a in1 + * @param[out] in2 The key for output + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_in_keyout_desc(uint32_t header, + const uint8_t* in1, + uint32_t in1_length, + fsl_shw_sko_t* key_info, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + if (in1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in1, in1_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + goto out; + } + + status = sah_Create_Key_Link(mu, &link2, key_info); + + if (status != FSL_RETURN_OK_S) { + goto out; + } + +link2->flags |= SAH_OUTPUT_LINK; /* mark key for output */ +status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + +out: + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } + + return status; +} + +/** + * Add descriptor where both links are outputs. + * + * @param header The Sahara header value for the descriptor. + * @param out1 The first output buffer (or NULL) + * @param out1_length Size of @a out1 + * @param[out] out2 The second output buffer (or NULL) + * @param out2_length Size of @a out2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_two_out_desc(uint32_t header, + uint8_t* out1, + uint32_t out1_length, + uint8_t* out2, + uint32_t out2_length, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + + if (out1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) out1, out1_length, + SAH_OUTPUT_LINK | SAH_USES_LINK_DATA); + } + + if ( (out2 != NULL) && (status == FSL_RETURN_OK_S) ) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) out2, out2_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + + +/** + * Add descriptor where first link is output, second is output + * + * @param header The Sahara header value for the descriptor. + * @param out1 The first output buffer (or NULL) + * @param out1_length Size of @a out1 + * @param[out] in2 The input buffer (or NULL) + * @param in2_length Size of @a in2 + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_out_in_desc(uint32_t header, + uint8_t* out1, + uint32_t out1_length, + const uint8_t* in2, + uint32_t in2_length, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + + if (out1 != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) out1, out1_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + } + + if ( (in2 != NULL) && (status == FSL_RETURN_OK_S) ) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) in2, in2_length, + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + + +/** + * Add descriptor where link1 is input buffer, link2 is output buffer. + * + * @param header The Sahara header value for the descriptor. + * @param in The input buffer + * @param in_length Size of the input buffer + * @param[out] out The output buffer + * @param out_length Size of the output buffer + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_in_out_desc(uint32_t header, + const uint8_t* in, uint32_t in_length, + uint8_t* out, uint32_t out_length, + const sah_Mem_Util* mu, + sah_Head_Desc** desc_chain) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + if (in != NULL) { + status = sah_Create_Link(mu, &link1, + (sah_Oct_Str) in, in_length, + SAH_USES_LINK_DATA); + } + + if ((status == FSL_RETURN_OK_S) && (out != NULL)) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) out, out_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + } + + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } else { + status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + } + + return status; +} + + +/** + * Add descriptor where link1 is a key, link2 is output buffer. + * + * @param header The Sahara header value for the descriptor. + * @param key_info Key information + * @param[out] out The output buffer + * @param out_length Size of the output buffer + * @param mu Memory functions + * @param[in,out] desc_chain Chain to start or append to + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_add_key_out_desc(uint32_t header, + const fsl_shw_sko_t *key_info, + uint8_t* out, uint32_t out_length, + const sah_Mem_Util *mu, + sah_Head_Desc **desc_chain) +{ + fsl_shw_return_t status; + sah_Link *link1 = NULL; + sah_Link *link2 = NULL; + + status = sah_Create_Key_Link(mu, &link1, (fsl_shw_sko_t *) key_info); + if (status != FSL_RETURN_OK_S) { + goto out; + } + + + if (out != NULL) { + status = sah_Create_Link(mu, &link2, + (sah_Oct_Str) out, out_length, + SAH_OUTPUT_LINK | + SAH_USES_LINK_DATA); + if (status != FSL_RETURN_OK_S) { + goto out; + } + } +status = sah_Append_Desc(mu, desc_chain, header, link1, link2); + +out: + if (status != FSL_RETURN_OK_S) { + if (link1 != NULL) { + sah_Destroy_Link(mu, link1); + } + if (link2 != NULL) { + sah_Destroy_Link(mu, link2); + } + } + + return status; +} + + +/** + * Sanity checks the user context object fields to ensure that they make some + * sense before passing the uco as a parameter + * + * @brief Verify the user context object + * + * @param uco user context object + * + * @return A return code of type #fsl_shw_return_t. + */ +fsl_shw_return_t sah_validate_uco(fsl_shw_uco_t *uco) +{ + fsl_shw_return_t status = FSL_RETURN_OK_S; + + + /* check if file is opened */ + if (uco->sahara_openfd < 0) { + status = FSL_RETURN_NO_RESOURCE_S; + } else { + /* check flag combination: the only invalid setting of the + * blocking and callback flags is blocking with callback. So check + * for that + */ + if ((uco->flags & (FSL_UCO_BLOCKING_MODE | FSL_UCO_CALLBACK_MODE)) == + (FSL_UCO_BLOCKING_MODE | FSL_UCO_CALLBACK_MODE)) { + status = FSL_RETURN_BAD_FLAG_S; + } else { + /* check that memory utilities have been attached */ + if (uco->mem_util == NULL) { + status = FSL_RETURN_MEMORY_ERROR_S; + } else { + /* must have pool of at least 1, even for blocking mode */ + if (uco->pool_size == 0) { + status = FSL_RETURN_ERROR_S; + } else { + /* if callback flag is set, it better have a callback + * routine */ + if (uco->flags & FSL_UCO_CALLBACK_MODE) { + if (uco->callback == NULL) { + status = FSL_RETURN_INTERNAL_ERROR_S; + } + } + } + } + } + } + + return status; +} + + +/** + * Perform any post-processing on non-blocking results. + * + * For instance, free descriptor chains, compare authentication codes, ... + * + * @param user_ctx User context object + * @param result_info A set of results + */ +void sah_Postprocess_Results(fsl_shw_uco_t* user_ctx, sah_results* result_info) +{ + unsigned i; + + /* for each result returned */ + for (i = 0; i < *result_info->actual; i++) { + sah_Head_Desc* desc = result_info->results[i].user_desc; + uint8_t* out1 = desc->out1_ptr; + uint8_t* out2 = desc->out2_ptr; + uint32_t len = desc->out_len; + + /* + * For now, tne only post-processing besides freeing the + * chain is the need to check the auth code for fsl_shw_auth_decrypt(). + * + * If other uses are required in the future, this code will probably + * need a flag in the sah_Head_Desc (or a function pointer!) to + * determine what needs to be done. + */ + if ((out1 != NULL) && (out2 != NULL)) { + unsigned j; + for (j = 0; j < len; j++) { + if (out1[j] != out2[j]) { + /* Problem detected. Change result. */ + result_info->results[i].code = FSL_RETURN_AUTH_FAILED_S; + break; + } + } + /* free allocated 'calced_auth' */ + user_ctx->mem_util-> + mu_free(user_ctx->mem_util->mu_ref, out1); + } + + /* Free the API-created chain, unless tagged as not-from-API */ + if (! (desc->uco_flags & FSL_UCO_SAVE_DESC_CHAIN)) { + sah_Descriptor_Chain_Destroy(user_ctx->mem_util, &desc); + } + } +} + + +/* End of sf_util.c */ diff --git a/drivers/mxc/security/scc2_driver.c b/drivers/mxc/security/scc2_driver.c new file mode 100644 index 000000000000..e0cbb28a0ad0 --- /dev/null +++ b/drivers/mxc/security/scc2_driver.c @@ -0,0 +1,2401 @@ +/* + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! @file scc2_driver.c + * + * This is the driver code for the Security Controller version 2 (SCC2). It's + * interaction with the Linux kernel is from calls to #scc_init() when the + * driver is loaded, and #scc_cleanup() should the driver be unloaded. The + * driver uses locking and (task-sleep/task-wakeup) functions from the kernel. + * It also registers itself to handle the interrupt line(s) from the SCC. New + * to this version of the driver is an interface providing access to the secure + * partitions. This is in turn exposed to the API user through the + * fsl_shw_smalloc() series of functions. Other drivers in the kernel may use + * the remaining API functions to get at the services of the SCC. The main + * service provided is the Secure Memory, which allows encoding and decoding of + * secrets with a per-chip secret key. + * + * The SCC is single-threaded, and so is this module. When the scc_crypt() + * routine is called, it will lock out other accesses to the function. If + * another task is already in the module, the subsequent caller will spin on a + * lock waiting for the other access to finish. + * + * Note that long crypto operations could cause a task to spin for a while, + * preventing other kernel work (other than interrupt processing) to get done. + * + * The external (kernel module) interface is through the following functions: + * @li scc_get_configuration() @li scc_crypt() @li scc_zeroize_memories() @li + * scc_monitor_security_failure() @li scc_stop_monitoring_security_failure() + * @li scc_set_sw_alarm() @li scc_read_register() @li scc_write_register() @li + * scc_allocate_partition() @li scc_initialize_partition @li + * scc_release_partition() @li scc_diminish_permissions @li + * scc_encrypt_region() @li scc_decrypt_region() @li scc_virt_to_phys + * + * All other functions are internal to the driver. + */ + +#include "sahara2/include/portable_os.h" +#include "scc2_internals.h" +#include + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + +#include +#include +#include + +#else + +#include +#include +#include + +#endif + +#include + +/** + * This is the set of errors which signal that access to the SCM RAM has + * failed or will fail. + */ +#define SCM_ACCESS_ERRORS \ + (SCM_ERRSTAT_ILM | SCM_ERRSTAT_SUP | SCM_ERRSTAT_ERC_MASK) + +/****************************************************************************** + * + * Global / Static Variables + * + *****************************************************************************/ + +#ifdef SCC_REGISTER_DEBUG + +#define REG_PRINT_BUFFER_SIZE 200 + +static char reg_print_buffer[REG_PRINT_BUFFER_SIZE]; + +typedef char *(*reg_print_routine_t) (uint32_t value, char *print_buffer, + int buf_size); + +#endif + +/** + * This is type void* so that a) it cannot directly be dereferenced, + * and b) pointer arithmetic on it will function in a 'normal way' for + * the offsets in scc_defines.h + * + * scc_base is the location in the iomap where the SCC's registers + * (and memory) start. + * + * The referenced data is declared volatile so that the compiler will + * not make any assumptions about the value of registers in the SCC, + * and thus will always reload the register into CPU memory before + * using it (i.e. wherever it is referenced in the driver). + * + * This value should only be referenced by the #SCC_READ_REGISTER and + * #SCC_WRITE_REGISTER macros and their ilk. All dereferences must be + * 32 bits wide. + */ +static volatile void *scc_base; +uint32_t scc_phys_base; + +/** Array to hold function pointers registered by + #scc_monitor_security_failure() and processed by + #scc_perform_callbacks() */ +static void (*scc_callbacks[SCC_CALLBACK_SIZE]) (void); +/*SCC need IRAM's base address but use only the partitions allocated for it.*/ +uint32_t scm_ram_phys_base; + +void *scm_ram_base = NULL; + +/** Calculated once for quick reference to size of the unreserved space in + * RAM in SCM. + */ +uint32_t scm_memory_size_bytes; + +/** Structure returned by #scc_get_configuration() */ +static scc_config_t scc_configuration = { + .driver_major_version = SCC_DRIVER_MAJOR_VERSION, + .driver_minor_version = SCC_DRIVER_MINOR_VERSION_2, + .scm_version = -1, + .smn_version = -1, + .block_size_bytes = -1, + .partition_size_bytes = -1, + .partition_count = -1, +}; + +/** Internal flag to know whether SCC is in Failed state (and thus many + * registers are unavailable). Once it goes failed, it never leaves it. */ +static volatile enum scc_status scc_availability = SCC_STATUS_INITIAL; + +/** Flag to say whether interrupt handler has been registered for + * SMN interrupt */ +static int smn_irq_set = 0; + +/** Flag to say whether interrupt handler has been registered for + * SCM interrupt */ +static int scm_irq_set = 0; + +/** This lock protects the #scc_callbacks list as well as the @c + * callbacks_performed flag in #scc_perform_callbacks. Since the data this + * protects may be read or written from either interrupt or base level, all + * operations should use the irqsave/irqrestore or similar to make sure that + * interrupts are inhibited when locking from base level. + */ +static os_lock_t scc_callbacks_lock = NULL; + +/** + * Ownership of this lock prevents conflicts on the crypto operation in the + * SCC. + */ +static os_lock_t scc_crypto_lock = NULL; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)) +/** Pointer to SCC's clock information. Initialized during scc_init(). */ +static struct clk *scc_clk = NULL; +#endif + +/** The lookup table for an 8-bit value. Calculated once + * by #scc_init_ccitt_crc(). + */ +static uint16_t scc_crc_lookup_table[256]; + +/****************************************************************************** + * + * Function Implementations - Externally Accessible + * + *****************************************************************************/ + +/** + * Allocate a partition of secure memory + * + * @param smid_value Value to use for the SMID register. Must be 0 for + * kernel mode access. + * @param[out] part_no (If successful) Assigned partition number. + * @param[out] part_base Kernel virtual address of the partition. + * @param[out] part_phys Physical address of the partition. + * + * @return + */ +scc_return_t scc_allocate_partition(uint32_t smid_value, + int *part_no, + void **part_base, uint32_t *part_phys) +{ + uint32_t i; + os_lock_context_t irq_flags = 0; /* for IRQ save/restore */ + int local_part; + scc_return_t retval = SCC_RET_FAIL; + void *base_addr = NULL; + uint32_t reg_value; + + local_part = -1; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + if (scc_availability == SCC_STATUS_UNIMPLEMENTED) { + goto out; + } + + /* ACQUIRE LOCK to prevent others from using crypto or acquiring a + * partition. Note that crypto operations could take a long time, so the + * calling process could potentially spin for some time. + */ + os_lock_save_context(scc_crypto_lock, irq_flags); + + do { + /* Find current state of partition ownership */ + reg_value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG); + + /* Search for a free one */ + for (i = 0; i < scc_configuration.partition_count; i++) { + if (((reg_value >> (SCM_POWN_SHIFT * i)) + & SCM_POWN_MASK) == SCM_POWN_PART_FREE) { + break; /* found a free one */ + } + } + if (i == local_part) { + /* found this one last time, and failed to allocated it */ + pr_debug(KERN_ERR "Partition %d cannot be allocated\n", + i); + goto out; + } + if (i >= scc_configuration.partition_count) { + retval = SCC_RET_INSUFFICIENT_SPACE; /* all used up */ + goto out; + } + + pr_debug + ("SCC2: Attempting to allocate partition %i, owners:%08x\n", + i, SCC_READ_REGISTER(SCM_PART_OWNERS_REG)); + + local_part = i; + /* Store SMID to grab a partition */ + SCC_WRITE_REGISTER(SCM_SMID0_REG + + SCM_SMID_WIDTH * (local_part), smid_value); + mdelay(2); + + /* Now make sure it is ours... ? */ + reg_value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG); + + if (((reg_value >> (SCM_POWN_SHIFT * (local_part))) + & SCM_POWN_MASK) != SCM_POWN_PART_OWNED) { + continue; /* try for another */ + } + base_addr = scm_ram_base + + (local_part * scc_configuration.partition_size_bytes); + break; + } while (1); + +out: + + /* Free the lock */ + os_unlock_restore_context(scc_callbacks_lock, irq_flags); + + /* If the base address was assigned, then a partition was successfully + * acquired. + */ + if (base_addr != NULL) { + pr_debug("SCC2 Part owners: %08x, engaged: %08x\n", + reg_value, SCC_READ_REGISTER(SCM_PART_ENGAGED_REG)); + pr_debug("SCC2 MAP for part %d: %08x\n", + local_part, + SCC_READ_REGISTER(SCM_ACC0_REG + 8 * local_part)); + + /* Copy the partition information to the data structures passed by the + * user. + */ + *part_no = local_part; + *part_base = base_addr; + *part_phys = (uint32_t) scm_ram_phys_base + + (local_part * scc_configuration.partition_size_bytes); + retval = SCC_RET_OK; + + pr_debug + ("SCC2 partition engaged. Kernel address: %p. Physical " + "address: %p, pfn: %08x\n", *part_base, (void *)*part_phys, + __phys_to_pfn(*part_phys)); + } + + return retval; +} /* allocate_partition() */ + +/** + * Release a partition of secure memory + * + * @param part_base Kernel virtual address of the partition to be released. + * + * @return SCC_RET_OK if successful. + */ +scc_return_t scc_release_partition(void *part_base) +{ + uint32_t partition_no; + + if (part_base == NULL) { + return SCC_RET_FAIL; + } + + /* Ensure that this is a proper partition location */ + partition_no = SCM_PART_NUMBER((uint32_t) part_base); + + pr_debug("SCC2: Attempting to release partition %i, owners:%08x\n", + partition_no, SCC_READ_REGISTER(SCM_PART_OWNERS_REG)); + + /* check that the partition is ours to de-establish */ + if (!host_owns_partition(partition_no)) { + return SCC_RET_FAIL; + } + + /* TODO: The state of the zeroize engine (SRS field in the Command Status + * Register) should be examined before issuing the zeroize command here. + * To make the driver thread-safe, a lock should be taken out before + * issuing the check and released after the zeroize command has been + * issued. + */ + + /* Zero the partition to release it */ + scc_write_register(SCM_ZCMD_REG, + (partition_no << SCM_ZCMD_PART_SHIFT) | + (ZCMD_DEALLOC_PART << SCM_ZCMD_CCMD_SHIFT)); + mdelay(2); + + pr_debug("SCC2: done releasing partition %i, owners:%08x\n", + partition_no, SCC_READ_REGISTER(SCM_PART_OWNERS_REG)); + + /* Check that the de-assignment went correctly */ + if (host_owns_partition(partition_no)) { + return SCC_RET_FAIL; + } + + return SCC_RET_OK; +} + +/** + * Diminish the permissions on a partition of secure memory + * + * @param part_base Kernel virtual address of the partition. + * @param permissions ORed values of the type SCM_PERM_* which will be used as + * initial partition permissions. SHW API users should use + * the FSL_PERM_* definitions instead. + * + * @return SCC_RET_OK if successful. + */ +scc_return_t scc_diminish_permissions(void *part_base, uint32_t permissions) +{ + uint32_t partition_no; + uint32_t permissions_requested; + permissions_requested = permissions; + + /* ensure that this is a proper partition location */ + partition_no = SCM_PART_NUMBER((uint32_t) part_base); + + /* invert the permissions, masking out unused bits */ + permissions = (~permissions) & SCM_PERM_MASK; + + /* attempt to diminish the permissions */ + scc_write_register(SCM_ACC0_REG + 8 * partition_no, permissions); + mdelay(2); + + /* Reading it back puts it into the original form */ + permissions = SCC_READ_REGISTER(SCM_ACC0_REG + 8 * partition_no); + if (permissions == permissions_requested) { + pr_debug("scc_partition_diminish_perms: successful\n"); + pr_debug("scc_partition_diminish_perms: successful\n"); + return SCC_RET_OK; + } + pr_debug("scc_partition_diminish_perms: not successful\n"); + + return SCC_RET_FAIL; +} + +extern scc_partition_status_t scc_partition_status(void *part_base) +{ + uint32_t part_no; + uint32_t part_owner; + + /* Determine the partition number from the address */ + part_no = SCM_PART_NUMBER((uint32_t) part_base); + + /* Check if the partition is implemented */ + if (part_no >= scc_configuration.partition_count) { + return SCC_PART_S_UNUSABLE; + } + + /* Determine the value of the partition owners register */ + part_owner = (SCC_READ_REGISTER(SCM_PART_OWNERS_REG) + >> (part_no * SCM_POWN_SHIFT)) & SCM_POWN_MASK; + + switch (part_owner) { + case SCM_POWN_PART_OTHER: + return SCC_PART_S_UNAVAILABLE; + break; + case SCM_POWN_PART_FREE: + return SCC_PART_S_AVAILABLE; + break; + case SCM_POWN_PART_OWNED: + /* could be allocated or engaged*/ + if (partition_engaged(part_no)) { + return SCC_PART_S_ENGAGED; + } else { + return SCC_PART_S_ALLOCATED; + } + break; + case SCM_POWN_PART_UNUSABLE: + default: + return SCC_PART_S_UNUSABLE; + break; + } +} + +/** + * Calculate the physical address from the kernel virtual address. + * + * @param address Kernel virtual address of data in an Secure Partition. + * @return Physical address of said data. + */ +uint32_t scc_virt_to_phys(void *address) +{ + return (uint32_t) address - (uint32_t) scm_ram_base + + (uint32_t) scm_ram_phys_base; +} + +/** + * Engage partition of secure memory + * + * @param part_base (kernel) Virtual + * @param UMID NULL, or 16-byte UMID for partition security + * @param permissions ORed values from fsl_shw_permission_t which + * will be used as initial partiition permissions. + * + * @return SCC_RET_OK if successful. + */ + +scc_return_t +scc_engage_partition(void *part_base, + const uint8_t *UMID, uint32_t permissions) +{ + uint32_t partition_no; + uint8_t *UMID_base = part_base + 0x10; + uint32_t *MAP_base = part_base; + uint8_t i; + + partition_no = SCM_PART_NUMBER((uint32_t) part_base); + + if (!host_owns_partition(partition_no) || + partition_engaged(partition_no) || + !(SCC_READ_REGISTER(SCM_SMID0_REG + (partition_no * 8)) == 0)) { + + return SCC_RET_FAIL; + } + + if (UMID != NULL) { + for (i = 0; i < 16; i++) { + UMID_base[i] = UMID[i]; + } + } + + MAP_base[0] = permissions; + + udelay(20); + + /* Check that the partition was engaged correctly, and that it has the + * proper permissions. + */ + + if ((!partition_engaged(partition_no)) || + (permissions != + SCC_READ_REGISTER(SCM_ACC0_REG + 8 * partition_no))) { + return SCC_RET_FAIL; + } + + return SCC_RET_OK; +} + +/*****************************************************************************/ +/* fn scc_init() */ +/*****************************************************************************/ +/** + * Initialize the driver at boot time or module load time. + * + * Register with the kernel as the interrupt handler for the SCC interrupt + * line(s). + * + * Map the SCC's register space into the driver's memory space. + * + * Query the SCC for its configuration and status. Save the configuration in + * #scc_configuration and save the status in #scc_availability. Called by the + * kernel. + * + * Do any locking/wait queue initialization which may be necessary. + * + * The availability fuse may be checked, depending on platform. + */ +static int scc_init(void) +{ + uint32_t smn_status; + int i; + int return_value = -EIO; /* assume error */ + + if (scc_availability == SCC_STATUS_INITIAL) { + + /* Set this until we get an initial reading */ + scc_availability = SCC_STATUS_CHECKING; + + /* Initialize the constant for the CRC function */ + scc_init_ccitt_crc(); + + /* initialize the callback table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + scc_callbacks[i] = 0; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) + mxc_clks_enable(SCC_CLK); +#else + if (IS_ERR(scc_clk)) { + return_value = PTR_ERR(scc_clk); + goto out; + } else + clk_enable(scc_clk); +#endif + + /* Set up the hardware access locks */ + scc_callbacks_lock = os_lock_alloc_init(); + scc_crypto_lock = os_lock_alloc_init(); + if (scc_callbacks_lock == NULL || scc_crypto_lock == NULL) { + os_printk(KERN_ERR + "SCC2: Failed to allocate context locks. Exiting.\n"); + goto out; + } + + /* See whether there is an SCC available */ + if (0 && !SCC_ENABLED()) { + os_printk(KERN_ERR + "SCC2: Fuse for SCC is set to disabled. Exiting.\n"); + goto out; + } + /* Map the SCC (SCM and SMN) memory on the internal bus into + kernel address space */ + scc_base = (void *)ioremap(scc_phys_base, SZ_4K); + if (scc_base == NULL) { + os_printk(KERN_ERR + "SCC2: Register mapping failed. Exiting.\n"); + goto out; + } + + /* If that worked, we can try to use the SCC */ + /* Get SCM into 'clean' condition w/interrupts cleared & + disabled */ + SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0); + + /* Clear error status register */ + (void)SCC_READ_REGISTER(SCM_ERR_STATUS_REG); + + /* + * There is an SCC. Determine its current state. Side effect + * is to populate scc_config and scc_availability + */ + smn_status = scc_grab_config_values(); + + /* Try to set up interrupt handler(s) */ + if (scc_availability != SCC_STATUS_OK) { + goto out; + } + + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) + scm_ram_phys_base += 0x8000; + + scm_ram_base = (void *)ioremap_nocache(scm_ram_phys_base, + scc_configuration. + partition_count * + scc_configuration. + partition_size_bytes); + if (scm_ram_base == NULL) { + os_printk(KERN_ERR + "SCC2: RAM failed to remap: %p for %d bytes\n", + (void *)scm_ram_phys_base, + scc_configuration.partition_count * + scc_configuration.partition_size_bytes); + goto out; + } + pr_debug("SCC2: RAM at Physical %p / Virtual %p\n", + (void *)scm_ram_phys_base, scm_ram_base); + + pr_debug("Secure Partition Table: Found %i partitions\n", + scc_configuration.partition_count); + + if (setup_interrupt_handling() != 0) { + unsigned err_cond; + /** + * The error could be only that the SCM interrupt was + * not set up. This interrupt is always masked, so + * that is not an issue. + * The SMN's interrupt may be shared on that line, it + * may be separate, or it may not be wired. Do what + * is necessary to check its status. + * Although the driver is coded for possibility of not + * having SMN interrupt, the fact that there is one + * means it should be available and used. + */ +#ifdef USE_SMN_INTERRUPT + err_cond = !smn_irq_set; /* Separate. Check SMN binding */ +#elif !defined(NO_SMN_INTERRUPT) + err_cond = !scm_irq_set; /* Shared. Check SCM binding */ +#else + err_cond = FALSE; /* SMN not wired at all. Ignore. */ +#endif + if (err_cond) { + /* setup was not able to set up SMN interrupt */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; + goto out; + } + } + + /* interrupt handling returned non-zero */ + /* Get SMN into 'clean' condition w/interrupts cleared & + enabled */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT + | SMN_COMMAND_ENABLE_INTERRUPT); + + out: + /* + * If status is SCC_STATUS_UNIMPLEMENTED or is still + * SCC_STATUS_CHECKING, could be leaving here with the driver partially + * initialized. In either case, cleanup (which will mark the SCC as + * UNIMPLEMENTED). + */ + if (scc_availability == SCC_STATUS_CHECKING || + scc_availability == SCC_STATUS_UNIMPLEMENTED) { + scc_cleanup(); + } else { + return_value = 0; /* All is well */ + } + } + /* ! STATUS_INITIAL */ + os_printk(KERN_ALERT "SCC2: Driver Status is %s\n", + (scc_availability == SCC_STATUS_INITIAL) ? "INITIAL" : + (scc_availability == SCC_STATUS_CHECKING) ? "CHECKING" : + (scc_availability == + SCC_STATUS_UNIMPLEMENTED) ? "UNIMPLEMENTED" + : (scc_availability == + SCC_STATUS_OK) ? "OK" : (scc_availability == + SCC_STATUS_FAILED) ? "FAILED" : + "UNKNOWN"); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_disable(SCC_CLK); +#else + if (!IS_ERR(scc_clk)) + clk_disable(scc_clk); +#endif + + return return_value; +} /* scc_init */ + +/*****************************************************************************/ +/* fn scc_cleanup() */ +/*****************************************************************************/ +/** + * Perform cleanup before driver/module is unloaded by setting the machine + * state close to what it was when the driver was loaded. This function is + * called when the kernel is shutting down or when this driver is being + * unloaded. + * + * A driver like this should probably never be unloaded, especially if there + * are other module relying upon the callback feature for monitoring the SCC + * status. + * + * In any case, cleanup the callback table (by clearing out all of the + * pointers). Deregister the interrupt handler(s). Unmap SCC registers. + * + * Note that this will not release any partitions that have been allocated. + * + */ +static void scc_cleanup(void) +{ + int i; + + /******************************************************/ + + /* Mark the driver / SCC as unusable. */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; + + /* Clear out callback table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + scc_callbacks[i] = 0; + } + + /* If SCC has been mapped in, clean it up and unmap it */ + if (scc_base) { + /* For the SCM, disable interrupts. */ + SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0); + + /* For the SMN, clear and disable interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT); + } + + /* Now that interrupts cannot occur, disassociate driver from the interrupt + * lines. + */ + + /* Deregister SCM interrupt handler */ + if (scm_irq_set) { + os_deregister_interrupt(INT_SCC_SCM); + } + + /* Deregister SMN interrupt handler */ + if (smn_irq_set) { +#ifdef USE_SMN_INTERRUPT + os_deregister_interrupt(INT_SCC_SMN); +#endif + } + + /* Finally, release the mapped memory */ + iounmap(scm_ram_base); + + if (scc_callbacks_lock != NULL) + os_lock_deallocate(scc_callbacks_lock); + + if (scc_crypto_lock != NULL) + os_lock_deallocate(scc_crypto_lock); + + /*Disabling SCC Clock*/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_disable(SCC_CLK); +#else + if (!IS_ERR(scc_clk)) + clk_disable(scc_clk); + clk_put(scc_clk); +#endif + pr_debug("SCC2 driver cleaned up.\n"); + +} /* scc_cleanup */ + +/*****************************************************************************/ +/* fn scc_get_configuration() */ +/*****************************************************************************/ +scc_config_t *scc_get_configuration(void) +{ + /* + * If some other driver calls scc before the kernel does, make sure that + * this driver's initialization is performed. + */ + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /** + * If there is no SCC, yet the driver exists, the value -1 will be in + * the #scc_config_t fields for other than the driver versions. + */ + return &scc_configuration; +} /* scc_get_configuration */ + +/*****************************************************************************/ +/* fn scc_zeroize_memories() */ +/*****************************************************************************/ +scc_return_t scc_zeroize_memories(void) +{ + scc_return_t return_status = SCC_RET_FAIL; + + return return_status; +} /* scc_zeroize_memories */ + +/*****************************************************************************/ +/* fn scc_set_sw_alarm() */ +/*****************************************************************************/ +void scc_set_sw_alarm(void) +{ + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Update scc_availability based on current SMN status. This might + * perform callbacks. + */ + (void)scc_update_state(); + + /* if everything is OK, make it fail */ + if (scc_availability == SCC_STATUS_OK) { + + /* sound the alarm (and disable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_SET_SOFTWARE_ALARM); + + scc_availability = SCC_STATUS_FAILED; /* Remember what we've done */ + + /* In case SMN interrupt is not available, tell the world */ + scc_perform_callbacks(); + } + + return; +} /* scc_set_sw_alarm */ + +/*****************************************************************************/ +/* fn scc_monitor_security_failure() */ +/*****************************************************************************/ +scc_return_t scc_monitor_security_failure(void callback_func(void)) +{ + int i; + os_lock_context_t irq_flags; /* for IRQ save/restore */ + scc_return_t return_status = SCC_RET_TOO_MANY_FUNCTIONS; + int function_stored = FALSE; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Acquire lock of callbacks table. Could be spin_lock_irq() if this + * routine were just called from base (not interrupt) level + */ + os_lock_save_context(scc_callbacks_lock, irq_flags); + + /* Search through table looking for empty slot */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + if (scc_callbacks[i] == callback_func) { + if (function_stored) { + /* Saved duplicate earlier. Clear this later one. */ + scc_callbacks[i] = NULL; + } + /* Exactly one copy is now stored */ + return_status = SCC_RET_OK; + break; + } else if (scc_callbacks[i] == NULL && !function_stored) { + /* Found open slot. Save it and remember */ + scc_callbacks[i] = callback_func; + return_status = SCC_RET_OK; + function_stored = TRUE; + } + } + + /* Free the lock */ + os_unlock_restore_context(scc_callbacks_lock, irq_flags); + + return return_status; +} /* scc_monitor_security_failure */ + +/*****************************************************************************/ +/* fn scc_stop_monitoring_security_failure() */ +/*****************************************************************************/ +void scc_stop_monitoring_security_failure(void callback_func(void)) +{ + os_lock_context_t irq_flags; /* for IRQ save/restore */ + int i; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* Acquire lock of callbacks table. Could be spin_lock_irq() if this + * routine were just called from base (not interrupt) level + */ + os_lock_save_context(scc_callbacks_lock, irq_flags); + + /* Search every entry of the table for this function */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + if (scc_callbacks[i] == callback_func) { + scc_callbacks[i] = NULL; /* found instance - clear it out */ + break; + } + } + + /* Free the lock */ + os_unlock_restore_context(scc_callbacks_lock, irq_flags); + + return; +} /* scc_stop_monitoring_security_failure */ + +/*****************************************************************************/ +/* fn scc_read_register() */ +/*****************************************************************************/ +scc_return_t scc_read_register(int register_offset, uint32_t * value) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t smn_status; + uint32_t scm_status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* First layer of protection -- completely unaccessible SCC */ + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + + /* Second layer -- that offset is valid */ + if (register_offset != SMN_BB_DEC_REG && /* write only! */ + check_register_offset(register_offset) == SCC_RET_OK) { + + /* Get current status / update local state */ + smn_status = scc_update_state(); + scm_status = SCC_READ_REGISTER(SCM_STATUS_REG); + + /* + * Third layer - verify that the register being requested is + * available in the current state of the SCC. + */ + if ((return_status = + check_register_accessible(register_offset, + smn_status, + scm_status)) == + SCC_RET_OK) { + *value = SCC_READ_REGISTER(register_offset); + } + } + } + + return return_status; +} /* scc_read_register */ + +/*****************************************************************************/ +/* fn scc_write_register() */ +/*****************************************************************************/ +scc_return_t scc_write_register(int register_offset, uint32_t value) +{ + scc_return_t return_status = SCC_RET_FAIL; + uint32_t smn_status; + uint32_t scm_status; + + if (scc_availability == SCC_STATUS_INITIAL) { + scc_init(); + } + + /* First layer of protection -- completely unaccessible SCC */ + if (scc_availability != SCC_STATUS_UNIMPLEMENTED) { + + /* Second layer -- that offset is valid */ + if (!((register_offset == SCM_STATUS_REG) || /* These registers are */ + (register_offset == SCM_VERSION_REG) || /* Read Only */ + (register_offset == SMN_BB_CNT_REG) || + (register_offset == SMN_TIMER_REG)) && + check_register_offset(register_offset) == SCC_RET_OK) { + + /* Get current status / update local state */ + smn_status = scc_update_state(); + scm_status = SCC_READ_REGISTER(SCM_STATUS_REG); + + /* + * Third layer - verify that the register being requested is + * available in the current state of the SCC. + */ + if (check_register_accessible + (register_offset, smn_status, scm_status) == 0) { + SCC_WRITE_REGISTER(register_offset, value); + return_status = SCC_RET_OK; + } + } + } + + return return_status; +} /* scc_write_register() */ + +/****************************************************************************** + * + * Function Implementations - Internal + * + *****************************************************************************/ + +/*****************************************************************************/ +/* fn scc_irq() */ +/*****************************************************************************/ +/** + * This is the interrupt handler for the SCC. + * + * This function checks the SMN Status register to see whether it + * generated the interrupt, then it checks the SCM Status register to + * see whether it needs attention. + * + * If an SMN Interrupt is active, then the SCC state set to failure, and + * #scc_perform_callbacks() is invoked to notify any interested parties. + * + * The SCM Interrupt should be masked, as this driver uses polling to determine + * when the SCM has completed a crypto or zeroing operation. Therefore, if the + * interrupt is active, the driver will just clear the interrupt and (re)mask. + */ +OS_DEV_ISR(scc_irq) +{ + uint32_t smn_status; + uint32_t scm_status; + int handled = 0; /* assume interrupt isn't from SMN */ +#if defined(USE_SMN_INTERRUPT) + int smn_irq = INT_SCC_SMN; /* SMN interrupt is on a line by itself */ +#elif defined (NO_SMN_INTERRUPT) + int smn_irq = -1; /* not wired to CPU at all */ +#else + int smn_irq = INT_SCC_SCM; /* SMN interrupt shares a line with SCM */ +#endif + + /* Update current state... This will perform callbacks... */ + smn_status = scc_update_state(); + + /* SMN is on its own interrupt line. Verify the IRQ was triggered + * before clearing the interrupt and marking it handled. */ + if ((os_dev_get_irq() == smn_irq) && + (smn_status & SMN_STATUS_SMN_STATUS_IRQ)) { + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT); + handled++; /* tell kernel that interrupt was handled */ + } + + /* Check on the health of the SCM */ + scm_status = SCC_READ_REGISTER(SCM_STATUS_REG); + + /* The driver masks interrupts, so this should never happen. */ + if (os_dev_get_irq() == INT_SCC_SCM) { + /* but if it does, try to prevent it in the future */ + SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0); + handled++; + } + + /* Any non-zero value of handled lets kernel know we got something */ + os_dev_isr_return(handled); +} + +/*****************************************************************************/ +/* fn scc_perform_callbacks() */ +/*****************************************************************************/ +/** Perform callbacks registered by #scc_monitor_security_failure(). + * + * Make sure callbacks only happen once... Since there may be some reason why + * the interrupt isn't generated, this routine could be called from base(task) + * level. + * + * One at a time, go through #scc_callbacks[] and call any non-null pointers. + */ +static void scc_perform_callbacks(void) +{ + static int callbacks_performed = 0; + unsigned long irq_flags; /* for IRQ save/restore */ + int i; + + /* Acquire lock of callbacks table and callbacks_performed flag */ + os_lock_save_context(scc_callbacks_lock, irq_flags); + + if (!callbacks_performed) { + callbacks_performed = 1; + + /* Loop over all of the entries in the table */ + for (i = 0; i < SCC_CALLBACK_SIZE; i++) { + /* If not null, ... */ + if (scc_callbacks[i]) { + scc_callbacks[i] (); /* invoke the callback routine */ + } + } + } + + os_unlock_restore_context(scc_callbacks_lock, irq_flags); + + return; +} + +/*****************************************************************************/ +/* fn scc_update_state() */ +/*****************************************************************************/ +/** + * Make certain SCC is still running. + * + * Side effect is to update #scc_availability and, if the state goes to failed, + * run #scc_perform_callbacks(). + * + * (If #SCC_BRINGUP is defined, bring SCC to secure state if it is found to be + * in health check state) + * + * @return Current value of #SMN_STATUS_REG register. + */ +static uint32_t scc_update_state(void) +{ + uint32_t smn_status_register = SMN_STATE_FAIL; + int smn_state; + + /* if FAIL or UNIMPLEMENTED, don't bother */ + if (scc_availability == SCC_STATUS_CHECKING || + scc_availability == SCC_STATUS_OK) { + + smn_status_register = SCC_READ_REGISTER(SMN_STATUS_REG); + smn_state = smn_status_register & SMN_STATUS_STATE_MASK; + +#ifdef SCC_BRINGUP + /* If in Health Check while booting, try to 'bringup' to Secure mode */ + if (scc_availability == SCC_STATUS_CHECKING && + smn_state == SMN_STATE_HEALTH_CHECK) { + /* Code up a simple algorithm for the ASC */ + SCC_WRITE_REGISTER(SMN_SEQ_START_REG, 0xaaaa); + SCC_WRITE_REGISTER(SMN_SEQ_END_REG, 0x5555); + SCC_WRITE_REGISTER(SMN_SEQ_CHECK_REG, 0x5555); + /* State should be SECURE now */ + smn_status_register = SCC_READ_REGISTER(SMN_STATUS); + smn_state = smn_status_register & SMN_STATUS_STATE_MASK; + } +#endif + + /* + * State should be SECURE or NON_SECURE for operation of the part. If + * FAIL, mark failed (i.e. limited access to registers). Any other + * state, mark unimplemented, as the SCC is unuseable. + */ + if (smn_state == SMN_STATE_SECURE + || smn_state == SMN_STATE_NON_SECURE) { + /* Healthy */ + scc_availability = SCC_STATUS_OK; + } else if (smn_state == SMN_STATE_FAIL) { + scc_availability = SCC_STATUS_FAILED; /* uh oh - unhealthy */ + scc_perform_callbacks(); + os_printk(KERN_ERR "SCC2: SCC went into FAILED mode\n"); + } else { + /* START, ZEROIZE RAM, HEALTH CHECK, or unknown */ + scc_availability = SCC_STATUS_UNIMPLEMENTED; /* unuseable */ + os_printk(KERN_ERR + "SCC2: SCC declared UNIMPLEMENTED\n"); + } + } + /* if availability is initial or ok */ + return smn_status_register; +} + +/*****************************************************************************/ +/* fn scc_init_ccitt_crc() */ +/*****************************************************************************/ +/** + * Populate the partial CRC lookup table. + * + * @return none + * + */ +static void scc_init_ccitt_crc(void) +{ + int dividend; /* index for lookup table */ + uint16_t remainder; /* partial value for a given dividend */ + int bit; /* index into bits of a byte */ + + /* + * Compute the remainder of each possible dividend. + */ + for (dividend = 0; dividend < 256; ++dividend) { + /* + * Start with the dividend followed by zeros. + */ + remainder = dividend << (8); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) { + /* + * Try to divide the current data bit. + */ + if (remainder & 0x8000) { + remainder = (remainder << 1) ^ CRC_POLYNOMIAL; + } else { + remainder = (remainder << 1); + } + } + + /* + * Store the result into the table. + */ + scc_crc_lookup_table[dividend] = remainder; + } + +} /* scc_init_ccitt_crc() */ + +/*****************************************************************************/ +/* fn grab_config_values() */ +/*****************************************************************************/ +/** + * grab_config_values() will read the SCM Configuration and SMN Status + * registers and store away version and size information for later use. + * + * @return The current value of the SMN Status register. + */ +static uint32_t scc_grab_config_values(void) +{ + uint32_t scm_version_register; + uint32_t smn_status_register = SMN_STATE_FAIL; + + if (scc_availability != SCC_STATUS_CHECKING) { + goto out; + } + scm_version_register = SCC_READ_REGISTER(SCM_VERSION_REG); + pr_debug("SCC2 Driver: SCM version is 0x%08x\n", scm_version_register); + + /* Get SMN status and update scc_availability */ + smn_status_register = scc_update_state(); + pr_debug("SCC2 Driver: SMN status is 0x%08x\n", smn_status_register); + + /* save sizes and versions information for later use */ + scc_configuration.block_size_bytes = 16; /* BPCP ? */ + scc_configuration.partition_count = + 1 + ((scm_version_register & SCM_VER_NP_MASK) >> SCM_VER_NP_SHIFT); + scc_configuration.partition_size_bytes = + 1 << ((scm_version_register & SCM_VER_BPP_MASK) >> + SCM_VER_BPP_SHIFT); + scc_configuration.scm_version = + (scm_version_register & SCM_VER_MAJ_MASK) >> SCM_VER_MAJ_SHIFT; + scc_configuration.smn_version = + (smn_status_register & SMN_STATUS_VERSION_ID_MASK) + >> SMN_STATUS_VERSION_ID_SHIFT; + if (scc_configuration.scm_version != SCM_MAJOR_VERSION_2) { + scc_availability = SCC_STATUS_UNIMPLEMENTED; /* Unknown version */ + } + + out: + return smn_status_register; +} /* grab_config_values */ + +/*****************************************************************************/ +/* fn setup_interrupt_handling() */ +/*****************************************************************************/ +/** + * Register the SCM and SMN interrupt handlers. + * + * Called from #scc_init() + * + * @return 0 on success + */ +static int setup_interrupt_handling(void) +{ + int smn_error_code = -1; + int scm_error_code = -1; + + /* Disnable SCM interrupts */ + SCC_WRITE_REGISTER(SCM_INT_CTL_REG, 0); + +#ifdef USE_SMN_INTERRUPT + /* Install interrupt service routine for SMN. */ + smn_error_code = os_register_interrupt(SCC_DRIVER_NAME, + INT_SCC_SMN, scc_irq); + if (smn_error_code != 0) { + os_printk(KERN_ERR + "SCC2 Driver: Error installing SMN Interrupt Handler: %d\n", + smn_error_code); + } else { + smn_irq_set = 1; /* remember this for cleanup */ + /* Enable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT | + SMN_COMMAND_ENABLE_INTERRUPT); + } +#else + smn_error_code = 0; /* no problems... will handle later */ +#endif + + /* + * Install interrupt service routine for SCM (or both together). + */ + scm_error_code = os_register_interrupt(SCC_DRIVER_NAME, + INT_SCC_SCM, scc_irq); + if (scm_error_code != 0) { +#ifndef MXC + os_printk(KERN_ERR + "SCC2 Driver: Error installing SCM Interrupt Handler: %d\n", + scm_error_code); +#else + os_printk(KERN_ERR + "SCC2 Driver: Error installing SCC Interrupt Handler: %d\n", + scm_error_code); +#endif + } else { + scm_irq_set = 1; /* remember this for cleanup */ +#if defined(USE_SMN_INTERRUPT) && !defined(NO_SMN_INTERRUPT) + /* Enable SMN interrupts */ + SCC_WRITE_REGISTER(SMN_COMMAND_REG, + SMN_COMMAND_CLEAR_INTERRUPT | + SMN_COMMAND_ENABLE_INTERRUPT); +#endif + } + + /* Return an error if one was encountered */ + return scm_error_code ? scm_error_code : smn_error_code; +} /* setup_interrupt_handling */ + +/*****************************************************************************/ +/* fn scc_do_crypto() */ +/*****************************************************************************/ +/** Have the SCM perform the crypto function. + * + * Set up length register, and the store @c scm_control into control register + * to kick off the operation. Wait for completion, gather status, clear + * interrupt / status. + * + * @param byte_count number of bytes to perform in this operation + * @param scm_command Bit values to be set in @c SCM_CCMD_REG register + * + * @return 0 on success, value of #SCM_ERR_STATUS_REG on failure + */ +static uint32_t scc_do_crypto(int byte_count, uint32_t scm_command) +{ + int block_count = byte_count / SCC_BLOCK_SIZE_BYTES(); + uint32_t crypto_status; + scc_return_t ret; + + /* This seems to be necessary in order to allow subsequent cipher + * operations to succeed when a partition is deallocated/reallocated! + */ + (void)SCC_READ_REGISTER(SCM_STATUS_REG); + + /* In length register, 0 means 1, etc. */ + scm_command |= (block_count - 1) << SCM_CCMD_LENGTH_SHIFT; + + /* set modes and kick off the operation */ + SCC_WRITE_REGISTER(SCM_CCMD_REG, scm_command); + + ret = scc_wait_completion(&crypto_status); + + /* Only done bit should be on */ + if (crypto_status & SCM_STATUS_ERR) { + /* Replace with error status instead */ + crypto_status = SCC_READ_REGISTER(SCM_ERR_STATUS_REG); + pr_debug("SCM Failure: 0x%x\n", crypto_status); + if (crypto_status == 0) { + /* That came up 0. Turn on arbitrary bit to signal error. */ + crypto_status = SCM_ERRSTAT_ILM; + } + } else { + crypto_status = 0; + } + pr_debug("SCC2: Done waiting.\n"); + + return crypto_status; +} + +/** + * Encrypt a region of secure memory. + * + * @param part_base Kernel virtual address of the partition. + * @param offset_bytes Offset from the start of the partition to the plaintext + * data. + * @param byte_count Length of the region (octets). + * @param black_data Physical location to store the encrypted data. + * @param IV Value to use for the IV. + * @param cypher_mode Cyphering mode to use, specified by type + * #scc_cypher_mode_t + * + * @return SCC_RET_OK if successful. + */ +scc_return_t +scc_encrypt_region(uint32_t part_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t *black_data, + uint32_t *IV, scc_cypher_mode_t cypher_mode) +{ + os_lock_context_t irq_flags; /* for IRQ save/restore */ + scc_return_t status = SCC_RET_OK; + uint32_t crypto_status; + uint32_t scm_command; + int offset_blocks = offset_bytes / SCC_BLOCK_SIZE_BYTES(); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_enable(SCC_CLK); +#else + if (IS_ERR(scc_clk)) { + status = SCC_RET_FAIL; + goto out; + } else + clk_enable(scc_clk); +#endif + + scm_command = ((offset_blocks << SCM_CCMD_OFFSET_SHIFT) | + (SCM_PART_NUMBER(part_base) << SCM_CCMD_PART_SHIFT)); + + switch (cypher_mode) { + case SCC_CYPHER_MODE_CBC: + scm_command |= SCM_CCMD_AES_ENC_CBC; + break; + case SCC_CYPHER_MODE_ECB: + scm_command |= SCM_CCMD_AES_ENC_ECB; + break; + default: + status = SCC_RET_FAIL; + break; + } + + pr_debug("Received encrypt request. SCM_C_BLACK_ST_REG: %p, " + "scm_Command: %08x, length: %i (part_base: %08x, " + "offset: %i)\n", + black_data, scm_command, byte_count, part_base, offset_blocks); + + if (status != SCC_RET_OK) + goto out; + + /* ACQUIRE LOCK to prevent others from using crypto or releasing slot */ + os_lock_save_context(scc_crypto_lock, irq_flags); + + if (status == SCC_RET_OK) { + SCC_WRITE_REGISTER(SCM_C_BLACK_ST_REG, (uint32_t) black_data); + + /* Only write the IV if it will actually be used */ + if (cypher_mode == SCC_CYPHER_MODE_CBC) { + /* Write the IV register */ + SCC_WRITE_REGISTER(SCM_AES_CBC_IV0_REG, *(IV)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV1_REG, *(IV + 1)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV2_REG, *(IV + 2)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV3_REG, *(IV + 3)); + } + + /* Set modes and kick off the encryption */ + crypto_status = scc_do_crypto(byte_count, scm_command); + + if (crypto_status != 0) { + pr_debug("SCM encrypt red crypto failure: 0x%x\n", + crypto_status); + } else { + status = SCC_RET_OK; + pr_debug("SCC2: Encrypted %d bytes\n", byte_count); + } + } + + os_unlock_restore_context(scc_crypto_lock, irq_flags); + +out: +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_disable(SCC_CLK); +#else + if (!IS_ERR(scc_clk)) + clk_disable(scc_clk); +#endif + + return status; +} + +/* Decrypt a region into secure memory + * + * @param part_base Kernel virtual address of the partition. + * @param offset_bytes Offset from the start of the partition to store the + * plaintext data. + * @param byte_counts Length of the region (octets). + * @param black_data Physical location of the encrypted data. + * @param IV Value to use for the IV. + * @param cypher_mode Cyphering mode to use, specified by type + * #scc_cypher_mode_t + * + * @return SCC_RET_OK if successful. + */ +scc_return_t +scc_decrypt_region(uint32_t part_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t *black_data, + uint32_t *IV, scc_cypher_mode_t cypher_mode) +{ + os_lock_context_t irq_flags; /* for IRQ save/restore */ + scc_return_t status = SCC_RET_OK; + uint32_t crypto_status; + uint32_t scm_command; + int offset_blocks = offset_bytes / SCC_BLOCK_SIZE_BYTES(); + + /*Enabling SCC clock.*/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_enable(SCC_CLK); +#else + if (IS_ERR(scc_clk)) { + status = SCC_RET_FAIL; + goto out; + } else + clk_enable(scc_clk); +#endif + scm_command = ((offset_blocks << SCM_CCMD_OFFSET_SHIFT) | + (SCM_PART_NUMBER(part_base) << SCM_CCMD_PART_SHIFT)); + + switch (cypher_mode) { + case SCC_CYPHER_MODE_CBC: + scm_command |= SCM_CCMD_AES_DEC_CBC; + break; + case SCC_CYPHER_MODE_ECB: + scm_command |= SCM_CCMD_AES_DEC_ECB; + break; + default: + status = SCC_RET_FAIL; + break; + } + + pr_debug("Received decrypt request. SCM_C_BLACK_ST_REG: %p, " + "scm_Command: %08x, length: %i (part_base: %08x, " + "offset: %i)\n", + black_data, scm_command, byte_count, part_base, offset_blocks); + + if (status != SCC_RET_OK) + goto out; + + /* ACQUIRE LOCK to prevent others from using crypto or releasing slot */ + os_lock_save_context(scc_crypto_lock, irq_flags); + + if (status == SCC_RET_OK) { + status = SCC_RET_FAIL; /* reset expectations */ + SCC_WRITE_REGISTER(SCM_C_BLACK_ST_REG, (uint32_t) black_data); + + /* Write the IV register */ + SCC_WRITE_REGISTER(SCM_AES_CBC_IV0_REG, *(IV)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV1_REG, *(IV + 1)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV2_REG, *(IV + 2)); + SCC_WRITE_REGISTER(SCM_AES_CBC_IV3_REG, *(IV + 3)); + + /* Set modes and kick off the decryption */ + crypto_status = scc_do_crypto(byte_count, scm_command); + + if (crypto_status != 0) { + pr_debug("SCM decrypt black crypto failure: 0x%x\n", + crypto_status); + } else { + status = SCC_RET_OK; + pr_debug("SCC2: Decrypted %d bytes\n", byte_count); + } + } + + os_unlock_restore_context(scc_crypto_lock, irq_flags); +out: + /*Disabling the Clock when the driver is not in use.*/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + mxc_clks_disable(SCC_CLK); +#else + if (!IS_ERR(scc_clk)) + clk_disable(scc_clk); +#endif + return status; +} + +/*****************************************************************************/ +/* fn host_owns_partition() */ +/*****************************************************************************/ +/** + * Determine if the host owns a given partition. + * + * @internal + * + * @param part_no Partition number to query + * + * @return TRUE if the host owns the partition, FALSE otherwise. + */ + +static uint32_t host_owns_partition(uint32_t part_no) +{ + uint32_t value; + + if (part_no < scc_configuration.partition_count) { + + /* Check the partition owners register */ + value = SCC_READ_REGISTER(SCM_PART_OWNERS_REG); + if (((value >> (part_no * SCM_POWN_SHIFT)) & SCM_POWN_MASK) + == SCM_POWN_PART_OWNED) + return TRUE; + } + return FALSE; +} + +/*****************************************************************************/ +/* fn partition_engaged() */ +/*****************************************************************************/ +/** + * Determine if the given partition is engaged. + * + * @internal + * + * @param part_no Partition number to query + * + * @return TRUE if the partition is engaged, FALSE otherwise. + */ + +static uint32_t partition_engaged(uint32_t part_no) +{ + uint32_t value; + + if (part_no < scc_configuration.partition_count) { + + /* Check the partition engaged register */ + value = SCC_READ_REGISTER(SCM_PART_ENGAGED_REG); + if (((value >> (part_no * SCM_PENG_SHIFT)) & 0x1) + == SCM_PENG_ENGAGED) + return TRUE; + } + return FALSE; +} + +/*****************************************************************************/ +/* fn scc_wait_completion() */ +/*****************************************************************************/ +/** + * Poll looking for end-of-cipher indication. Only used + * if @c SCC_SCM_SLEEP is not defined. + * + * @internal + * + * On a Tahiti, crypto under 230 or so bytes is done after the first loop, all + * the way up to five sets of spins for 1024 bytes. (8- and 16-byte functions + * are done when we first look. Zeroizing takes one pass around. + * + * @param scm_status Address of the SCM_STATUS register + * + * @return A return code of type #scc_return_t + */ +static scc_return_t scc_wait_completion(uint32_t * scm_status) +{ + scc_return_t ret; + int done; + int i = 0; + + /* check for completion by polling */ + do { + done = is_cipher_done(scm_status); + if (done) + break; + /* TODO: shorten this delay */ + udelay(1000); + } while (i++ < SCC_CIPHER_MAX_POLL_COUNT); + + pr_debug("SCC2: Polled DONE %d times\n", i); + if (!done) { + ret = SCC_RET_FAIL; + } + + return ret; +} /* scc_wait_completion() */ + +/*****************************************************************************/ +/* fn is_cipher_done() */ +/*****************************************************************************/ +/** + * This function returns non-zero if SCM Status register indicates + * that a cipher has terminated or some other interrupt-generating + * condition has occurred. + * + * @param scm_status Address of the SCM STATUS register + * + * @return 0 if cipher operations are finished + */ +static int is_cipher_done(uint32_t * scm_status) +{ + register unsigned status; + register int cipher_done; + + *scm_status = SCC_READ_REGISTER(SCM_STATUS_REG); + status = (*scm_status & SCM_STATUS_SRS_MASK) >> SCM_STATUS_SRS_SHIFT; + + /* + * Done when SCM is not in 'currently performing a function' states. + */ + cipher_done = ((status != SCM_STATUS_SRS_ZBUSY) + && (status != SCM_STATUS_SRS_CBUSY) + && (status != SCM_STATUS_SRS_ABUSY)); + + return cipher_done; +} /* is_cipher_done() */ + +/*****************************************************************************/ +/* fn offset_within_smn() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SMN register set. + * + * @param[in] register_offset register offset of SMN. + * + * @return 1 if true, 0 if false (not within SMN) + */ +static inline int offset_within_smn(uint32_t register_offset) +{ + return ((register_offset >= SMN_STATUS_REG) + && (register_offset <= SMN_HAC_REG)); +} + +/*****************************************************************************/ +/* fn offset_within_scm() */ +/*****************************************************************************/ +/*! + * Check that the offset is with the bounds of the SCM register set. + * + * @param[in] register_offset Register offset of SCM + * + * @return 1 if true, 0 if false (not within SCM) + */ +static inline int offset_within_scm(uint32_t register_offset) +{ + return 1; /* (register_offset >= SCM_RED_START) + && (register_offset < scm_highest_memory_address); */ +/* Although this would cause trouble for zeroize testing, this change would + * close a security hole which currently allows any kernel program to access + * any location in RED RAM. Perhaps enforce in non-SCC_DEBUG compiles? + && (register_offset <= SCM_INIT_VECTOR_1); */ +} + +/*****************************************************************************/ +/* fn check_register_accessible() */ +/*****************************************************************************/ +/** + * Given the current SCM and SMN status, verify that access to the requested + * register should be OK. + * + * @param[in] register_offset register offset within SCC + * @param[in] smn_status recent value from #SMN_STATUS_REG + * @param[in] scm_status recent value from #SCM_STATUS_REG + * + * @return #SCC_RET_OK if ok, #SCC_RET_FAIL if not + */ +static scc_return_t +check_register_accessible(uint32_t register_offset, uint32_t smn_status, + uint32_t scm_status) +{ + int error_code = SCC_RET_FAIL; + + /* Verify that the register offset passed in is not among the verboten set + * if the SMN is in Fail mode. + */ + if (offset_within_smn(register_offset)) { + if ((smn_status & SMN_STATUS_STATE_MASK) == SMN_STATE_FAIL) { + if (!((register_offset == SMN_STATUS_REG) || + (register_offset == SMN_COMMAND_REG) || + (register_offset == SMN_SEC_VIO_REG))) { + pr_debug + ("SCC2 Driver: Note: Security State is in FAIL state.\n"); + } /* register not a safe one */ + else { + /* SMN is in FAIL, but register is a safe one */ + error_code = SCC_RET_OK; + } + } /* State is FAIL */ + else { + /* State is not fail. All registers accessible. */ + error_code = SCC_RET_OK; + } + } + /* offset within SMN */ + /* Not SCM register. Check for SCM busy. */ + else if (offset_within_scm(register_offset)) { + /* This is the 'cannot access' condition in the SCM */ + if (0 /* (scm_status & SCM_STATUS_BUSY) */ + /* these are always available - rest fail on busy */ + && !((register_offset == SCM_STATUS_REG) || + (register_offset == SCM_ERR_STATUS_REG) || + (register_offset == SCM_INT_CTL_REG) || + (register_offset == SCM_VERSION_REG))) { + pr_debug + ("SCC2 Driver: Note: Secure Memory is in BUSY state.\n"); + } /* status is busy & register inaccessible */ + else { + error_code = SCC_RET_OK; + } + } + /* offset within SCM */ + return error_code; + +} /* check_register_accessible() */ + +/*****************************************************************************/ +/* fn check_register_offset() */ +/*****************************************************************************/ +/** + * Check that the offset is with the bounds of the SCC register set. + * + * @param[in] register_offset register offset of SMN. + * + * #SCC_RET_OK if ok, #SCC_RET_FAIL if not + */ +static scc_return_t check_register_offset(uint32_t register_offset) +{ + int return_value = SCC_RET_FAIL; + + /* Is it valid word offset ? */ + if (SCC_BYTE_OFFSET(register_offset) == 0) { + /* Yes. Is register within SCM? */ + if (offset_within_scm(register_offset)) { + return_value = SCC_RET_OK; /* yes, all ok */ + } + /* Not in SCM. Now look within the SMN */ + else if (offset_within_smn(register_offset)) { + return_value = SCC_RET_OK; /* yes, all ok */ + } + } + + return return_value; +} + +#ifdef SCC_REGISTER_DEBUG + +/** + * Names of the SCC Registers, indexed by register number + */ +static char *scc_regnames[] = { + "SCM_VERSION_REG", + "0x04", + "SCM_INT_CTL_REG", + "SCM_STATUS_REG", + "SCM_ERR_STATUS_REG", + "SCM_FAULT_ADR_REG", + "SCM_PART_OWNERS_REG", + "SCM_PART_ENGAGED_REG", + "SCM_UNIQUE_ID0_REG", + "SCM_UNIQUE_ID1_REG", + "SCM_UNIQUE_ID2_REG", + "SCM_UNIQUE_ID3_REG", + "0x30", + "0x34", + "0x38", + "0x3C", + "0x40", + "0x44", + "0x48", + "0x4C", + "SCM_ZCMD_REG", + "SCM_CCMD_REG", + "SCM_C_BLACK_ST_REG", + "SCM_DBG_STATUS_REG", + "SCM_AES_CBC_IV0_REG", + "SCM_AES_CBC_IV1_REG", + "SCM_AES_CBC_IV2_REG", + "SCM_AES_CBC_IV3_REG", + "0x70", + "0x74", + "0x78", + "0x7C", + "SCM_SMID0_REG", + "SCM_ACC0_REG", + "SCM_SMID1_REG", + "SCM_ACC1_REG", + "SCM_SMID2_REG", + "SCM_ACC2_REG", + "SCM_SMID3_REG", + "SCM_ACC3_REG", + "SCM_SMID4_REG", + "SCM_ACC4_REG", + "SCM_SMID5_REG", + "SCM_ACC5_REG", + "SCM_SMID6_REG", + "SCM_ACC6_REG", + "SCM_SMID7_REG", + "SCM_ACC7_REG", + "SCM_SMID8_REG", + "SCM_ACC8_REG", + "SCM_SMID9_REG", + "SCM_ACC9_REG", + "SCM_SMID10_REG", + "SCM_ACC10_REG", + "SCM_SMID11_REG", + "SCM_ACC11_REG", + "SCM_SMID12_REG", + "SCM_ACC12_REG", + "SCM_SMID13_REG", + "SCM_ACC13_REG", + "SCM_SMID14_REG", + "SCM_ACC14_REG", + "SCM_SMID15_REG", + "SCM_ACC15_REG", + "SMN_STATUS_REG", + "SMN_COMMAND_REG", + "SMN_SEQ_START_REG", + "SMN_SEQ_END_REG", + "SMN_SEQ_CHECK_REG", + "SMN_BB_CNT_REG", + "SMN_BB_INC_REG", + "SMN_BB_DEC_REG", + "SMN_COMPARE_REG", + "SMN_PT_CHK_REG", + "SMN_CT_CHK_REG", + "SMN_TIMER_IV_REG", + "SMN_TIMER_CTL_REG", + "SMN_SEC_VIO_REG", + "SMN_TIMER_REG", + "SMN_HAC_REG" +}; + +/** + * Names of the Secure RAM States + */ +static char *srs_names[] = { + "SRS_Reset", + "SRS_All_Ready", + "SRS_ZeroizeBusy", + "SRS_CipherBusy", + "SRS_AllBusy", + "SRS_ZeroizeDoneCipherReady", + "SRS_CipherDoneZeroizeReady", + "SRS_ZeroizeDoneCipherBusy", + "SRS_CipherDoneZeroizeBusy", + "SRS_UNKNOWN_STATE_9", + "SRS_TransitionalA", + "SRS_TransitionalB", + "SRS_TransitionalC", + "SRS_TransitionalD", + "SRS_AllDone", + "SRS_UNKNOWN_STATE_E", + "SRS_FAIL" +}; + +/** + * Create a text interpretation of the SCM Version Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_version_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, + "Bpp: %u, Bpcb: %u, np: %u, maj: %u, min: %u", + (value & SCM_VER_BPP_MASK) >> SCM_VER_BPP_SHIFT, + ((value & SCM_VER_BPCB_MASK) >> SCM_VER_BPCB_SHIFT) + 1, + ((value & SCM_VER_NP_MASK) >> SCM_VER_NP_SHIFT) + 1, + (value & SCM_VER_MAJ_MASK) >> SCM_VER_MAJ_SHIFT, + (value & SCM_VER_MIN_MASK) >> SCM_VER_MIN_SHIFT); + + return print_buffer; +} + +/** + * Create a text interpretation of the SCM Status Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_status_reg(uint32_t value, char *print_buffer, int buf_size) +{ + + snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s%s%s%s", + (value & SCM_STATUS_KST_DEFAULT_KEY) ? "KST_DefaultKey " : "", + /* reserved */ + (value & SCM_STATUS_KST_WRONG_KEY) ? "KST_WrongKey " : "", + (value & SCM_STATUS_KST_BAD_KEY) ? "KST_BadKey " : "", + (value & SCM_STATUS_ERR) ? "Error " : "", + (value & SCM_STATUS_MSS_FAIL) ? "MSS_FailState " : "", + (value & SCM_STATUS_MSS_SEC) ? "MSS_SecureState " : "", + (value & SCM_STATUS_RSS_FAIL) ? "RSS_FailState " : "", + (value & SCM_STATUS_RSS_SEC) ? "RSS_SecureState " : "", + (value & SCM_STATUS_RSS_INIT) ? "RSS_Initializing " : "", + (value & SCM_STATUS_UNV) ? "UID_Invalid " : "", + (value & SCM_STATUS_BIG) ? "BigEndian " : "", + (value & SCM_STATUS_USK) ? "SecretKey " : "", + srs_names[(value & SCM_STATUS_SRS_MASK) >> + SCM_STATUS_SRS_SHIFT]); + + return print_buffer; +} + +/** + * Names of the SCM Error Codes + */ +static +char *scm_err_code[] = { + "Unknown_0", + "UnknownAddress", + "UnknownCommand", + "ReadPermErr", + "WritePermErr", + "DMAErr", + "EncBlockLenOvfl", + "KeyNotEngaged", + "ZeroizeCmdQOvfl", + "CipherCmdQOvfl", + "ProcessIntr", + "WrongKey", + "DeviceBusy", + "DMAUnalignedAddr", + "Unknown_E", + "Unknown_F", +}; + +/** + * Names of the SMN States + */ +static char *smn_state_name[] = { + "Start", + "Invalid_01", + "Invalid_02", + "Invalid_03", + "Zeroizing_04", + "Zeroizing", + "HealthCheck", + "HealthCheck_07", + "Invalid_08", + "Fail", + "Secure", + "Invalid_0B", + "NonSecure", + "Invalid_0D", + "Invalid_0E", + "Invalid_0F", + "Invalid_10", + "Invalid_11", + "Invalid_12", + "Invalid_13", + "Invalid_14", + "Invalid_15", + "Invalid_16", + "Invalid_17", + "Invalid_18", + "FailHard", + "Invalid_1A", + "Invalid_1B", + "Invalid_1C", + "Invalid_1D", + "Invalid_1E", + "Invalid_1F" +}; + +/** + * Create a text interpretation of the SCM Error Status Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_err_status_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, + "MID: 0x%x, %s%s ErrorCode: %s, SMSState: %s, SCMState: %s", + (value & SCM_ERRSTAT_MID_MASK) >> SCM_ERRSTAT_MID_SHIFT, + (value & SCM_ERRSTAT_ILM) ? "ILM, " : "", + (value & SCM_ERRSTAT_SUP) ? "SUP, " : "", + scm_err_code[(value & SCM_ERRSTAT_ERC_MASK) >> + SCM_ERRSTAT_ERC_SHIFT], + smn_state_name[(value & SCM_ERRSTAT_SMS_MASK) >> + SCM_ERRSTAT_SMS_SHIFT], + srs_names[(value & SCM_ERRSTAT_SRS_MASK) >> + SCM_ERRSTAT_SRS_SHIFT]); + return print_buffer; +} + +/** + * Create a text interpretation of the SCM Zeroize Command Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_zcmd_reg(uint32_t value, char *print_buffer, int buf_size) +{ + unsigned cmd = (value & SCM_ZCMD_CCMD_MASK) >> SCM_CCMD_CCMD_SHIFT; + + snprintf(print_buffer, buf_size, "%s %u", + (cmd == + ZCMD_DEALLOC_PART) ? "DeallocPartition" : + "(unknown function)", + (value & SCM_ZCMD_PART_MASK) >> SCM_ZCMD_PART_SHIFT); + + return print_buffer; +} + +/** + * Create a text interpretation of the SCM Cipher Command Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_ccmd_reg(uint32_t value, char *print_buffer, int buf_size) +{ + unsigned cmd = (value & SCM_CCMD_CCMD_MASK) >> SCM_CCMD_CCMD_SHIFT; + + snprintf(print_buffer, buf_size, + "%s %u bytes, %s offset 0x%x, in partition %u", + (cmd == SCM_CCMD_AES_DEC_ECB) ? "ECB Decrypt" : (cmd == + SCM_CCMD_AES_ENC_ECB) + ? "ECB Encrypt" : (cmd == + SCM_CCMD_AES_DEC_CBC) ? "CBC Decrypt" : (cmd + == + SCM_CCMD_AES_ENC_CBC) + ? "CBC Encrypt" : "(unknown function)", + 16 + + 16 * ((value & SCM_CCMD_LENGTH_MASK) >> SCM_CCMD_LENGTH_SHIFT), + ((cmd == SCM_CCMD_AES_ENC_CBC) + || (cmd == SCM_CCMD_AES_ENC_ECB)) ? "at" : "to", + 16 * ((value & SCM_CCMD_OFFSET_MASK) >> SCM_CCMD_OFFSET_SHIFT), + (value & SCM_CCMD_PART_MASK) >> SCM_CCMD_PART_SHIFT); + + return print_buffer; +} + +/** + * Create a text interpretation of an SCM Access Permissions Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_acc_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s", + (value & SCM_PERM_NO_ZEROIZE) ? "NO_ZERO " : "", + (value & SCM_PERM_HD_SUP_DISABLE) ? "SUP_DIS " : "", + (value & SCM_PERM_HD_READ) ? "HD_RD " : "", + (value & SCM_PERM_HD_WRITE) ? "HD_WR " : "", + (value & SCM_PERM_HD_EXECUTE) ? "HD_EX " : "", + (value & SCM_PERM_TH_READ) ? "TH_RD " : "", + (value & SCM_PERM_TH_WRITE) ? "TH_WR " : "", + (value & SCM_PERM_OT_READ) ? "OT_RD " : "", + (value & SCM_PERM_OT_WRITE) ? "OT_WR " : "", + (value & SCM_PERM_OT_EXECUTE) ? "OT_EX" : ""); + + return print_buffer; +} + +/** + * Create a text interpretation of the SCM Partitions Engaged Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *scm_print_part_eng_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", + (value & 0x8000) ? "15 " : "", + (value & 0x4000) ? "14 " : "", + (value & 0x2000) ? "13 " : "", + (value & 0x1000) ? "12 " : "", + (value & 0x0800) ? "11 " : "", + (value & 0x0400) ? "10 " : "", + (value & 0x0200) ? "9 " : "", + (value & 0x0100) ? "8 " : "", + (value & 0x0080) ? "7 " : "", + (value & 0x0040) ? "6 " : "", + (value & 0x0020) ? "5 " : "", + (value & 0x0010) ? "4 " : "", + (value & 0x0008) ? "3 " : "", + (value & 0x0004) ? "2 " : "", + (value & 0x0002) ? "1 " : "", (value & 0x0001) ? "0" : ""); + + return print_buffer; +} + +/** + * Create a text interpretation of the SMN Status Register + * + * @param value The value of the register + * @param[out] print_buffer Place to store the interpretation + * @param buf_size Number of bytes available at print_buffer + * + * @return The print_buffer + */ +static +char *smn_print_status_reg(uint32_t value, char *print_buffer, int buf_size) +{ + snprintf(print_buffer, buf_size, + "Version %d %s%s%s%s%s%s%s%s%s%s%s%s%s", + (value & SMN_STATUS_VERSION_ID_MASK) >> + SMN_STATUS_VERSION_ID_SHIFT, + (value & SMN_STATUS_ILLEGAL_MASTER) ? "IllMaster " : "", + (value & SMN_STATUS_SCAN_EXIT) ? "ScanExit " : "", + (value & SMN_STATUS_PERIP_INIT) ? "PeripInit " : "", + (value & SMN_STATUS_SMN_ERROR) ? "SMNError " : "", + (value & SMN_STATUS_SOFTWARE_ALARM) ? "SWAlarm " : "", + (value & SMN_STATUS_TIMER_ERROR) ? "TimerErr " : "", + (value & SMN_STATUS_PC_ERROR) ? "PTCTErr " : "", + (value & SMN_STATUS_BITBANK_ERROR) ? "BitbankErr " : "", + (value & SMN_STATUS_ASC_ERROR) ? "ASCErr " : "", + (value & SMN_STATUS_SECURITY_POLICY_ERROR) ? "SecPlcyErr " : + "", + (value & SMN_STATUS_SEC_VIO_ACTIVE_ERROR) ? "SecVioAct " : "", + (value & SMN_STATUS_INTERNAL_BOOT) ? "IntBoot " : "", + smn_state_name[(value & SMN_STATUS_STATE_MASK) >> + SMN_STATUS_STATE_SHIFT]); + + return print_buffer; +} + +/** + * The array, indexed by register number (byte-offset / 4), of print routines + * for the SCC (SCM and SMN) registers. + */ +static reg_print_routine_t reg_printers[] = { + scm_print_version_reg, + NULL, /* 0x04 */ + NULL, /* SCM_INT_CTL_REG */ + scm_print_status_reg, + scm_print_err_status_reg, + NULL, /* SCM_FAULT_ADR_REG */ + NULL, /* SCM_PART_OWNERS_REG */ + scm_print_part_eng_reg, + NULL, /* SCM_UNIQUE_ID0_REG */ + NULL, /* SCM_UNIQUE_ID1_REG */ + NULL, /* SCM_UNIQUE_ID2_REG */ + NULL, /* SCM_UNIQUE_ID3_REG */ + NULL, /* 0x30 */ + NULL, /* 0x34 */ + NULL, /* 0x38 */ + NULL, /* 0x3C */ + NULL, /* 0x40 */ + NULL, /* 0x44 */ + NULL, /* 0x48 */ + NULL, /* 0x4C */ + scm_print_zcmd_reg, + scm_print_ccmd_reg, + NULL, /* SCM_C_BLACK_ST_REG */ + NULL, /* SCM_DBG_STATUS_REG */ + NULL, /* SCM_AES_CBC_IV0_REG */ + NULL, /* SCM_AES_CBC_IV1_REG */ + NULL, /* SCM_AES_CBC_IV2_REG */ + NULL, /* SCM_AES_CBC_IV3_REG */ + NULL, /* 0x70 */ + NULL, /* 0x74 */ + NULL, /* 0x78 */ + NULL, /* 0x7C */ + NULL, /* SCM_SMID0_REG */ + scm_print_acc_reg, /* ACC0 */ + NULL, /* SCM_SMID1_REG */ + scm_print_acc_reg, /* ACC1 */ + NULL, /* SCM_SMID2_REG */ + scm_print_acc_reg, /* ACC2 */ + NULL, /* SCM_SMID3_REG */ + scm_print_acc_reg, /* ACC3 */ + NULL, /* SCM_SMID4_REG */ + scm_print_acc_reg, /* ACC4 */ + NULL, /* SCM_SMID5_REG */ + scm_print_acc_reg, /* ACC5 */ + NULL, /* SCM_SMID6_REG */ + scm_print_acc_reg, /* ACC6 */ + NULL, /* SCM_SMID7_REG */ + scm_print_acc_reg, /* ACC7 */ + NULL, /* SCM_SMID8_REG */ + scm_print_acc_reg, /* ACC8 */ + NULL, /* SCM_SMID9_REG */ + scm_print_acc_reg, /* ACC9 */ + NULL, /* SCM_SMID10_REG */ + scm_print_acc_reg, /* ACC10 */ + NULL, /* SCM_SMID11_REG */ + scm_print_acc_reg, /* ACC11 */ + NULL, /* SCM_SMID12_REG */ + scm_print_acc_reg, /* ACC12 */ + NULL, /* SCM_SMID13_REG */ + scm_print_acc_reg, /* ACC13 */ + NULL, /* SCM_SMID14_REG */ + scm_print_acc_reg, /* ACC14 */ + NULL, /* SCM_SMID15_REG */ + scm_print_acc_reg, /* ACC15 */ + smn_print_status_reg, + NULL, /* SMN_COMMAND_REG */ + NULL, /* SMN_SEQ_START_REG */ + NULL, /* SMN_SEQ_END_REG */ + NULL, /* SMN_SEQ_CHECK_REG */ + NULL, /* SMN_BB_CNT_REG */ + NULL, /* SMN_BB_INC_REG */ + NULL, /* SMN_BB_DEC_REG */ + NULL, /* SMN_COMPARE_REG */ + NULL, /* SMN_PT_CHK_REG */ + NULL, /* SMN_CT_CHK_REG */ + NULL, /* SMN_TIMER_IV_REG */ + NULL, /* SMN_TIMER_CTL_REG */ + NULL, /* SMN_SEC_VIO_REG */ + NULL, /* SMN_TIMER_REG */ + NULL, /* SMN_HAC_REG */ +}; + +/*****************************************************************************/ +/* fn dbg_scc_read_register() */ +/*****************************************************************************/ +/** + * Noisily read a 32-bit value to an SCC register. + * @param offset The address of the register to read. + * + * @return The register value + * */ +uint32_t dbg_scc_read_register(uint32_t offset) +{ + uint32_t value; + char *regname = scc_regnames[offset / 4]; + + value = __raw_readl(scc_base + offset); + pr_debug("SCC2 RD: 0x%03x : 0x%08x (%s) %s\n", offset, value, regname, + reg_printers[offset / 4] + ? reg_printers[offset / 4] (value, reg_print_buffer, + REG_PRINT_BUFFER_SIZE) + : ""); + + return value; +} + +/*****************************************************************************/ +/* fn dbg_scc_write_register() */ +/*****************************************************************************/ +/* + * Noisily read a 32-bit value to an SCC register. + * @param offset The address of the register to written. + * + * @param value The new register value + */ +void dbg_scc_write_register(uint32_t offset, uint32_t value) +{ + char *regname = scc_regnames[offset / 4]; + + pr_debug("SCC2 WR: 0x%03x : 0x%08x (%s) %s\n", offset, value, regname, + reg_printers[offset / 4] + ? reg_printers[offset / 4] (value, reg_print_buffer, + REG_PRINT_BUFFER_SIZE) + : ""); + (void)__raw_writel(value, scc_base + offset); + +} + +#endif /* SCC_REGISTER_DEBUG */ + +static int scc_dev_probe(struct platform_device *pdev) +{ + struct resource *r; + int ret = 0; + + /* get the scc registers base address */ + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "can't get IORESOURCE_MEM (0)\n"); + ret = -ENXIO; + goto exit; + } + + scc_phys_base = r->start; + + + /* get the scc ram base address */ + r = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!r) { + dev_err(&pdev->dev, "can't get IORESOURCE_MEM (1)\n"); + ret = -ENXIO; + goto exit; + } + + scm_ram_phys_base = r->start; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)) + scc_clk = clk_get(&pdev->dev, "scc_clk"); +#endif + + /* now initialize the SCC */ + ret = scc_init(); + +exit: + return ret; +} + +static int scc_dev_remove(struct platform_device *pdev) +{ + scc_cleanup(); + return 0; +} + + +#ifdef CONFIG_PM +static int scc_suspend(struct platform_device *pdev, + pm_message_t state) +{ + return 0; +} + +static int scc_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define scc_suspend NULL +#define scc_resume NULL +#endif + +/*! Linux Driver definition + * + */ +static struct platform_driver mxcscc_driver = { + .driver = { + .name = SCC_DRIVER_NAME, + }, + .probe = scc_dev_probe, + .remove = scc_dev_remove, + .suspend = scc_suspend, + .resume = scc_resume, +}; + +static int __init scc_driver_init(void) +{ + return platform_driver_register(&mxcscc_driver); +} + +module_init(scc_driver_init); + +static void __exit scc_driver_exit(void) +{ + platform_driver_unregister(&mxcscc_driver); +} + +module_exit(scc_driver_exit); diff --git a/drivers/mxc/security/scc2_internals.h b/drivers/mxc/security/scc2_internals.h new file mode 100644 index 000000000000..1c047de0082e --- /dev/null +++ b/drivers/mxc/security/scc2_internals.h @@ -0,0 +1,519 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef SCC_INTERNALS_H +#define SCC_INTERNALS_H + +/** @file scc2_internals.h + * + * @brief This is intended to be the file which contains most or all of the + * code or changes need to port the driver. It also includes other definitions + * needed by the driver. + * + * This header file should only ever be included by scc2_driver.c + * + * Compile-time flags minimally needed: + * + * @li Some sort of platform flag. Currently TAHITI and MXC are understood. + * @li Some start-of-SCC consideration, such as SCC_BASE_ADDR + * + * Some changes which could be made when porting this driver: + * #SCC_SPIN_COUNT + * + */ + +#include /* Current version Linux kernel */ +#include /* Basic support for loadable modules, + printk */ +#include /* module_init, module_exit */ +#include /* General kernel system calls */ +#include /* for interrupt.h */ +#include + +#include /* ioremap() */ +#include /* IRQ / interrupt definitions */ + + +#include + +#if defined(MXC) + +#include +#include + + +/** + * This macro is used to determine whether the SCC is enabled/available + * on the platform. This macro may need to be ported. + */ +#define SCC_FUSE __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMHWV1)) +#define SCC_ENABLED() ((SCC_FUSE & MXC_IIMHWV1_SCC_DISABLE) == 0) + +#else /* neither TAHITI nor MXC */ + +#error Do not understand target architecture + +#endif /* TAHITI */ +/** + * Define the number of Stored Keys which the SCC driver will make available. + * Value shall be from 0 to 20. Default is zero (0). + */ +/*#define SCC_KEY_SLOTS 20*/ + + +/* Temporarily define compile-time flags to make Doxygen happy. */ +#ifdef DOXYGEN_HACK +/** @addtogroup scccompileflags */ +/** @{ */ + + +/** @def NO_SMN_INTERRUPT + * The SMN interrupt is not wired to the CPU at all. + */ +#define NO_SMN_INTERRUPT + + +/** + * Register an interrupt handler for the SMN as well as + * the SCM. In some implementations, the SMN is not connected at all (see + * #NO_SMN_INTERRUPT), and in others, it is on the same interrupt line as the + * SCM. When defining this flag, the SMN interrupt should be on a separate + * line from the SCM interrupt. + */ + +#define USE_SMN_INTERRUPT + + +/** + * Turn on generation of run-time operational, debug, and error messages + */ +#define SCC_DEBUG + + +/** + * Turn on generation of run-time logging of access to the SCM and SMN + * registers. + */ +#define SCC_REGISTER_DEBUG + + +/** + * Turn on generation of run-time logging of access to the SCM Red and + * Black memories. Will only work if #SCC_REGISTER_DEBUG is also defined. + */ +#define SCC_RAM_DEBUG + + +/** + * If the driver finds the SCC in HEALTH_CHECK state, go ahead and + * run a quick ASC to bring it to SECURE state. + */ +#define SCC_BRINGUP + + +/** + * Expected to come from platform header files or compile command line. + * This symbol must be the address of the SCC + */ +#define SCC_BASE + +/** + * This must be the interrupt line number of the SCM interrupt. + */ +#define INT_SCM + +/** + * if #USE_SMN_INTERRUPT is defined, this must be the interrupt line number of + * the SMN interrupt. + */ +#define INT_SMN + +/** + * Define the number of Stored Keys which the SCC driver will make available. + * Value shall be from 0 to 20. Default is zero (0). + */ +#define SCC_KEY_SLOTS + +/** + * Make sure that this flag is defined if compiling for a Little-Endian + * platform. Linux Kernel builds provide this flag. + */ +#define __LITTLE_ENDIAN + +/** + * Make sure that this flag is defined if compiling for a Big-Endian platform. + * Linux Kernel builds provide this flag. + */ +#define __BIG_ENDIAN + +/** + * Read a 32-bit register value from a 'peripheral'. Standard Linux/Unix + * macro. + * + * @param offset Bus address of register to be read + * + * @return The value of the register + */ +#define readl(offset) + + +/** + * Write a 32-bit value to a register in a 'peripheral'. Standard Linux/Unix + * macro. + * + * @param value The 32-bit value to store + * @param offset Bus address of register to be written + * + * return (none) + */ +#define writel(value,offset) + + +/** @} */ /* end group scccompileflags */ + +#endif /* DOXYGEN_HACK */ + + +#ifndef SCC_KEY_SLOTS +#define SCC_KEY_SLOTS 0 + +#else + +#if (SCC_KEY_SLOTS < 0) || (SCC_KEY_SLOTS > 20) +#error Bad value for SCC_KEY_SLOTS +#endif + +#endif + + +/** + * Maximum length of key/secret value which can be stored in SCC. + */ +#define SCC_MAX_KEY_SIZE 256 + + +/** + * This is the size, in bytes, of each key slot, and therefore the maximum size + * of the wrapped key. + */ +#define SCC_KEY_SLOT_SIZE 32 + + +/* These come for free with Linux, but may need to be set in a port. */ +#ifndef __BIG_ENDIAN +#ifndef __LITTLE_ENDIAN +#error One of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined +#endif +#else +#ifdef __LITTLE_ENDIAN +#error Exactly one of __LITTLE_ENDIAN or __BIG_ENDIAN must be #defined +#endif +#endif + + +#ifndef SCC_CALLBACK_SIZE +/** The number of function pointers which can be stored in #scc_callbacks. + * Defaults to 4, can be overridden with compile-line argument. + */ +#define SCC_CALLBACK_SIZE 4 +#endif + + +/** Initial CRC value for CCITT-CRC calculation. */ +#define CRC_CCITT_START 0xFFFF + + +#ifdef TAHITI + +/** + * The SCC_BASE has to be SMN_BASE_ADDR on TAHITI, as the banks of + * registers are swapped in place. + */ +#define SCC_BASE SMN_BASE_ADDR + + +/** The interrupt number for the SCC (SCM only!) on Tahiti */ +#define INT_SCC_SCM 62 + + +/** Tahiti does not have the SMN interrupt wired to the CPU. */ +#define NO_SMN_INTERRUPT + + +#endif /* TAHITI */ + + +/** Number of times to spin between polling of SCC while waiting for cipher + * or zeroizing function to complete. See also #SCC_CIPHER_MAX_POLL_COUNT. */ +#define SCC_SPIN_COUNT 1000 + + +/** Number of times to polling SCC while waiting for cipher + * or zeroizing function to complete. See also #SCC_SPIN_COUNT. */ +#define SCC_CIPHER_MAX_POLL_COUNT 100 + + +/** + * @def SCC_READ_REGISTER + * Read a 32-bit value from an SCC register. Macro which depends upon + * #scc_base. Linux readl()/writel() macros operate on 32-bit quantities, as + * do SCC register reads/writes. + * + * @param offset Register offset within SCC. + * + * @return The value from the SCC's register. + */ +#ifndef SCC_REGISTER_DEBUG +#define SCC_READ_REGISTER(offset) __raw_readl(scc_base+(offset)) +#else +#define SCC_READ_REGISTER(offset) dbg_scc_read_register(offset) +#endif + + +/** + * Write a 32-bit value to an SCC register. Macro depends upon #scc_base. + * Linux readl()/writel() macros operate on 32-bit quantities, as do SCC + * register reads/writes. + * + * @param offset Register offset within SCC. + * @param value 32-bit value to store into the register + * + * @return (void) + */ +#ifndef SCC_REGISTER_DEBUG +#define SCC_WRITE_REGISTER(offset,value) \ + (void)__raw_writel(value, scc_base+(offset)) +#else +#define SCC_WRITE_REGISTER(offset,value) \ + dbg_scc_write_register(offset, value) +#endif + +/** + * Calculate the kernel virtual address of a partition from the partition number. + */ +#define SCM_PART_ADDRESS(part) \ + (scm_ram_base + (part*scc_configuration.partition_size_bytes)) + +/** + * Calculate the partition number from the kernel virtual address. + */ +#define SCM_PART_NUMBER(address) \ + ((address - (uint32_t)scm_ram_base)/scc_configuration.partition_size_bytes) + +/** + * Calculates the byte offset into a word + * @param bp The byte (char*) pointer + * @return The offset (0, 1, 2, or 3) + */ +#define SCC_BYTE_OFFSET(bp) ((uint32_t)(bp) % sizeof(uint32_t)) + + +/** + * Converts (by rounding down) a byte pointer into a word pointer + * @param bp The byte (char*) pointer + * @return The word (uint32_t) as though it were an aligned (uint32_t*) + */ +#define SCC_WORD_PTR(bp) (((uint32_t)(bp)) & ~(sizeof(uint32_t)-1)) + + +/** + * Determine number of bytes in an SCC block + * + * @return Bytes / block + */ +#define SCC_BLOCK_SIZE_BYTES() scc_configuration.block_size_bytes + + +/** + * Maximum number of additional bytes which may be added in CRC+padding mode. + */ +#define PADDING_BUFFER_MAX_BYTES (CRC_SIZE_BYTES + sizeof(scc_block_padding)) + +/** + * Shorthand (clearer, anyway) for number of bytes in a CRC. + */ +#define CRC_SIZE_BYTES (sizeof(crc_t)) + +/** + * The polynomial used in CCITT-CRC calculation + */ +#define CRC_POLYNOMIAL 0x1021 + +/** + * Calculate CRC on one byte of data + * + * @param[in,out] running_crc A value of type crc_t where CRC is kept. This + * must be an rvalue and an lvalue. + * @param[in] byte_value The byte (uint8_t, char) to be put in the CRC + * + * @return none + */ +#define CALC_CRC(byte_value,running_crc) { \ + uint8_t data; \ + data = (0xff&(byte_value)) ^ (running_crc >> 8); \ + running_crc = scc_crc_lookup_table[data] ^ (running_crc << 8); \ +} + +/** Value of 'beginning of padding' marker in driver-provided padding */ +#define SCC_DRIVER_PAD_CHAR 0x80 + + +/** Name of the driver. Used (on Linux, anyway) when registering interrupts */ +#define SCC_DRIVER_NAME "mxc_scc" + + +/* Port -- these symbols are defined in Linux 2.6 and later. They are defined + * here for backwards compatibility because this started life as a 2.4 + * driver, and as a guide to portation to other platforms. + */ + +#if !defined(LINUX_VERSION_CODE) || LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + +#define irqreturn_t void /* Return type of an interrupt handler */ + +#define IRQ_HANDLED /* Would be '1' for handled -- as in return IRQ_HANDLED; */ + +#define IRQ_NONE /* would be '0' for not handled -- as in return IRQ_NONE; */ + +#define IRQ_RETVAL(x) /* Return x==0 (not handled) or non-zero (handled) */ + +#endif /* LINUX earlier than 2.5 */ + + +/* These are nice to have around */ +#ifndef FALSE +#define FALSE 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif + + +/** Provide a typedef for the CRC which can be used in encrypt/decrypt */ +typedef uint16_t crc_t; + + +/** Gives high-level view of state of the SCC */ +enum scc_status { + SCC_STATUS_INITIAL, /**< State of driver before ever checking */ + SCC_STATUS_CHECKING, /**< Transient state while driver loading */ + SCC_STATUS_UNIMPLEMENTED, /**< SCC is non-existent or unuseable */ + SCC_STATUS_OK, /**< SCC is in Secure or Default state */ + SCC_STATUS_FAILED /**< In Failed state */ +}; + +/** + * Information about a key slot. + */ +struct scc_key_slot +{ + uint64_t owner_id; /**< Access control value. */ + uint32_t length; /**< Length of value in slot. */ + uint32_t offset; /**< Offset of value from start of RAM. */ + uint32_t status; /**< 0 = unassigned, 1 = assigned. */ + uint32_t part_ctl; /**< for the CCMD register */ +}; + +/* Forward-declare a number routines which are not part of user api */ +static int scc_init(void); +static void scc_cleanup(void); +static int __init scc_driver_init(void); +static void __exit scc_driver_exit(void); + +/* Forward defines of internal functions */ +OS_DEV_ISR(scc_irq); +/*static irqreturn_t scc_irq(int irq, void *dev_id);*/ +/** Perform callbacks registered by #scc_monitor_security_failure(). + * + * Make sure callbacks only happen once... Since there may be some reason why + * the interrupt isn't generated, this routine could be called from base(task) + * level. + * + * One at a time, go through #scc_callbacks[] and call any non-null pointers. + */ +static void scc_perform_callbacks(void); +/*static uint32_t copy_to_scc(const uint8_t* from, uint32_t to, unsigned long count_bytes, uint16_t* crc); +static uint32_t copy_from_scc(const uint32_t from, uint8_t* to,unsigned long count_bytes, uint16_t* crc); +static scc_return_t scc_strip_padding(uint8_t* from,unsigned* count_bytes_stripped);*/ +static uint32_t scc_update_state(void); +static void scc_init_ccitt_crc(void); +static uint32_t scc_grab_config_values(void); +static int setup_interrupt_handling(void); +/** + * Perform an encryption on the input. If @c verify_crc is true, a CRC must be + * calculated on the plaintext, and appended, with padding, before computing + * the ciphertext. + * + * @param[in] count_in_bytes Count of bytes of plaintext + * @param[in] data_in Pointer to the plaintext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing ciphertext + * @param[in] add_crc Flag for computing CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + */ +/*static scc_return_t scc_encrypt(uint32_t count_in_bytes, uint8_t* data_in, uint32_t scm_control, uint8_t* data_out,int add_crc, unsigned long* count_out_bytes);*/ +/** + * Perform a decryption on the input. If @c verify_crc is true, the last block + * (maybe the two last blocks) is special - it should contain a CRC and + * padding. These must be stripped and verified. + * + * @param[in] count_in_bytes Count of bytes of ciphertext + * @param[in] data_in Pointer to the ciphertext + * @param[in] scm_control Bit values for the SCM_CONTROL register + * @param[in,out] data_out Pointer for storing plaintext + * @param[in] verify_crc Flag for running CRC - 0 no, else yes + * @param[in,out] count_out_bytes Number of bytes available at @c data_out + + */ +/*static scc_return_t scc_decrypt(uint32_t count_in_bytes, uint8_t* data_in, uint32_t scm_control, uint8_t* data_out, int verify_crc, unsigned long* count_out_bytes);*/ +static uint32_t host_owns_partition(uint32_t part_no); +static uint32_t partition_engaged(uint32_t part_no); + +static scc_return_t scc_wait_completion(uint32_t* scm_status); +static int is_cipher_done(uint32_t* scm_status); +static scc_return_t check_register_accessible (uint32_t offset, + uint32_t smn_status, + uint32_t scm_status); +static scc_return_t check_register_offset(uint32_t offset); +/*uint8_t make_vpu_partition(void);*/ + +#ifdef SCC_REGISTER_DEBUG +static uint32_t dbg_scc_read_register(uint32_t offset); +static void dbg_scc_write_register(uint32_t offset, uint32_t value); +#endif + + +/* For Linux kernel, export the API functions to other kernel modules */ +EXPORT_SYMBOL(scc_get_configuration); +EXPORT_SYMBOL(scc_zeroize_memories); +/*EXPORT_SYMBOL(scc_crypt);*/ +EXPORT_SYMBOL(scc_set_sw_alarm); +EXPORT_SYMBOL(scc_monitor_security_failure); +EXPORT_SYMBOL(scc_stop_monitoring_security_failure); +EXPORT_SYMBOL(scc_read_register); +EXPORT_SYMBOL(scc_write_register); +EXPORT_SYMBOL(scc_allocate_partition); +EXPORT_SYMBOL(scc_engage_partition); +EXPORT_SYMBOL(scc_release_partition); +EXPORT_SYMBOL(scc_diminish_permissions); +EXPORT_SYMBOL(scc_encrypt_region); +EXPORT_SYMBOL(scc_decrypt_region); +/*EXPORT_SYMBOL(make_vpu_partition);*/ + + +/* Tell Linux this is not GPL code */ +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Device Driver for SCC (SMN/SCM)"); + + +#endif /* SCC_INTERNALS_H */ diff --git a/drivers/mxc/ssi/Kconfig b/drivers/mxc/ssi/Kconfig new file mode 100644 index 000000000000..4cb581c2f945 --- /dev/null +++ b/drivers/mxc/ssi/Kconfig @@ -0,0 +1,12 @@ +# +# SPI device configuration +# + +menu "MXC SSI support" + +config MXC_SSI + tristate "SSI support" + ---help--- + Say Y to get the SSI services API available on MXC platform. + +endmenu diff --git a/drivers/mxc/ssi/Makefile b/drivers/mxc/ssi/Makefile new file mode 100644 index 000000000000..f9bb4419fc19 --- /dev/null +++ b/drivers/mxc/ssi/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the kernel SSI device drivers. +# + +obj-$(CONFIG_MXC_SSI) += ssimod.o + +ssimod-objs := ssi.o diff --git a/drivers/mxc/ssi/registers.h b/drivers/mxc/ssi/registers.h new file mode 100644 index 000000000000..a9f4512596c6 --- /dev/null +++ b/drivers/mxc/ssi/registers.h @@ -0,0 +1,208 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file ../ssi/registers.h + * @brief This header file contains SSI driver low level definition to access module registers. + * + * @ingroup SSI + */ + +#ifndef __MXC_SSI_REGISTERS_H__ +#define __MXC_SSI_REGISTERS_H__ + +/*! + * This include to define bool type, false and true definitions. + */ +#include + +#define SPBA_CPU_SSI 0x07 + +#define MXC_SSISTX0 0x00 +#define MXC_SSISTX1 0x04 +#define MXC_SSISRX0 0x08 +#define MXC_SSISRX1 0x0C +#define MXC_SSISCR 0x10 +#define MXC_SSISISR 0x14 +#define MXC_SSISIER 0x18 +#define MXC_SSISTCR 0x1C +#define MXC_SSISRCR 0x20 +#define MXC_SSISTCCR 0x24 +#define MXC_SSISRCCR 0x28 +#define MXC_SSISFCSR 0x2C +#define MXC_SSISTR 0x30 +#define MXC_SSISOR 0x34 +#define MXC_SSISACNT 0x38 +#define MXC_SSISACADD 0x3C +#define MXC_SSISACDAT 0x40 +#define MXC_SSISATAG 0x44 +#define MXC_SSISTMSK 0x48 +#define MXC_SSISRMSK 0x4C + +/* MXC 91221 only */ +#define MXC_SSISACCST 0x50 +#define MXC_SSISACCEN 0x54 +#define MXC_SSISACCDIS 0x58 + +/*! SSI1 registers offset*/ +#define MXC_SSI1STX0 0x00 +#define MXC_SSI1STX1 0x04 +#define MXC_SSI1SRX0 0x08 +#define MXC_SSI1SRX1 0x0C +#define MXC_SSI1SCR 0x10 +#define MXC_SSI1SISR 0x14 +#define MXC_SSI1SIER 0x18 +#define MXC_SSI1STCR 0x1C +#define MXC_SSI1SRCR 0x20 +#define MXC_SSI1STCCR 0x24 +#define MXC_SSI1SRCCR 0x28 +#define MXC_SSI1SFCSR 0x2C +#define MXC_SSI1STR 0x30 +#define MXC_SSI1SOR 0x34 +#define MXC_SSI1SACNT 0x38 +#define MXC_SSI1SACADD 0x3C +#define MXC_SSI1SACDAT 0x40 +#define MXC_SSI1SATAG 0x44 +#define MXC_SSI1STMSK 0x48 +#define MXC_SSI1SRMSK 0x4C + +/* MXC91221 only */ + +#define MXC_SSISACCST 0x50 +#define MXC_SSISACCEN 0x54 +#define MXC_SSISACCDIS 0x58 + +/* Not on MXC91221 */ +/*! SSI2 registers offset*/ +#define MXC_SSI2STX0 0x00 +#define MXC_SSI2STX1 0x04 +#define MXC_SSI2SRX0 0x08 +#define MXC_SSI2SRX1 0x0C +#define MXC_SSI2SCR 0x10 +#define MXC_SSI2SISR 0x14 +#define MXC_SSI2SIER 0x18 +#define MXC_SSI2STCR 0x1C +#define MXC_SSI2SRCR 0x20 +#define MXC_SSI2STCCR 0x24 +#define MXC_SSI2SRCCR 0x28 +#define MXC_SSI2SFCSR 0x2C +#define MXC_SSI2STR 0x30 +#define MXC_SSI2SOR 0x34 +#define MXC_SSI2SACNT 0x38 +#define MXC_SSI2SACADD 0x3C +#define MXC_SSI2SACDAT 0x40 +#define MXC_SSI2SATAG 0x44 +#define MXC_SSI2STMSK 0x48 +#define MXC_SSI2SRMSK 0x4C + +/*! + * SCR Register bit shift definitions + */ +#define SSI_ENABLE_SHIFT 0 +#define SSI_TRANSMIT_ENABLE_SHIFT 1 +#define SSI_RECEIVE_ENABLE_SHIFT 2 +#define SSI_NETWORK_MODE_SHIFT 3 +#define SSI_SYNCHRONOUS_MODE_SHIFT 4 +#define SSI_I2S_MODE_SHIFT 5 +#define SSI_SYSTEM_CLOCK_SHIFT 7 +#define SSI_TWO_CHANNEL_SHIFT 8 +#define SSI_CLOCK_IDLE_SHIFT 9 + +/* MXC91221 only*/ +#define SSI_TX_FRAME_CLOCK_DISABLE_SHIFT 10 +#define SSI_RX_FRAME_CLOCK_DISABLE_SHIFT 11 + +/*! + * STCR & SRCR Registers bit shift definitions + */ +#define SSI_EARLY_FRAME_SYNC_SHIFT 0 +#define SSI_FRAME_SYNC_LENGTH_SHIFT 1 +#define SSI_FRAME_SYNC_INVERT_SHIFT 2 +#define SSI_CLOCK_POLARITY_SHIFT 3 +#define SSI_SHIFT_DIRECTION_SHIFT 4 +#define SSI_CLOCK_DIRECTION_SHIFT 5 +#define SSI_FRAME_DIRECTION_SHIFT 6 +#define SSI_FIFO_ENABLE_0_SHIFT 7 +#define SSI_FIFO_ENABLE_1_SHIFT 8 +#define SSI_BIT_0_SHIFT 9 + +/* MXC91221 only*/ +#define SSI_TX_FRAME_CLOCK_DISABLE_SHIFT 10 +#define SSI_RX_DATA_EXTENSION_SHIFT 10 /*SRCR only */ +/*! + * STCCR & SRCCR Registers bit shift definitions + */ +#define SSI_PRESCALER_MODULUS_SHIFT 0 +#define SSI_FRAME_RATE_DIVIDER_SHIFT 8 +#define SSI_WORD_LENGTH_SHIFT 13 +#define SSI_PRESCALER_RANGE_SHIFT 17 +#define SSI_DIVIDE_BY_TWO_SHIFT 18 +#define SSI_FRAME_DIVIDER_MASK 31 +#define SSI_MIN_FRAME_DIVIDER_RATIO 1 +#define SSI_MAX_FRAME_DIVIDER_RATIO 32 +#define SSI_PRESCALER_MODULUS_MASK 255 +#define SSI_MIN_PRESCALER_MODULUS_RATIO 1 +#define SSI_MAX_PRESCALER_MODULUS_RATIO 256 +#define SSI_WORD_LENGTH_MASK 15 + +#define SSI_IRQ_STATUS_NUMBER 25 + +/*! + * SFCSR Register bit shift definitions + */ +#define SSI_RX_FIFO_1_COUNT_SHIFT 28 +#define SSI_TX_FIFO_1_COUNT_SHIFT 24 +#define SSI_RX_FIFO_1_WATERMARK_SHIFT 20 +#define SSI_TX_FIFO_1_WATERMARK_SHIFT 16 +#define SSI_RX_FIFO_0_COUNT_SHIFT 12 +#define SSI_TX_FIFO_0_COUNT_SHIFT 8 +#define SSI_RX_FIFO_0_WATERMARK_SHIFT 4 +#define SSI_TX_FIFO_0_WATERMARK_SHIFT 0 +#define SSI_MIN_FIFO_WATERMARK 0 +#define SSI_MAX_FIFO_WATERMARK 8 + +/*! + * SSI Option Register (SOR) bit shift definitions + */ +#define SSI_FRAME_SYN_RESET_SHIFT 0 +#define SSI_WAIT_SHIFT 1 +#define SSI_INIT_SHIFT 3 +#define SSI_TRANSMITTER_CLEAR_SHIFT 4 +#define SSI_RECEIVER_CLEAR_SHIFT 5 +#define SSI_CLOCK_OFF_SHIFT 6 +#define SSI_WAIT_STATE_MASK 0x3 + +/*! + * SSI AC97 Control Register (SACNT) bit shift definitions + */ +#define AC97_MODE_ENABLE_SHIFT 0 +#define AC97_VARIABLE_OPERATION_SHIFT 1 +#define AC97_TAG_IN_FIFO_SHIFT 2 +#define AC97_READ_COMMAND_SHIFT 3 +#define AC97_WRITE_COMMAND_SHIFT 4 +#define AC97_FRAME_RATE_DIVIDER_SHIFT 5 +#define AC97_FRAME_RATE_MASK 0x3F + +/*! + * SSI Test Register (STR) bit shift definitions + */ +#define SSI_TEST_MODE_SHIFT 15 +#define SSI_RCK2TCK_SHIFT 14 +#define SSI_RFS2TFS_SHIFT 13 +#define SSI_RXSTATE_SHIFT 8 +#define SSI_TXD2RXD_SHIFT 7 +#define SSI_TCK2RCK_SHIFT 6 +#define SSI_TFS2RFS_SHIFT 5 +#define SSI_TXSTATE_SHIFT 0 + +#endif /* __MXC_SSI_REGISTERS_H__ */ diff --git a/drivers/mxc/ssi/ssi.c b/drivers/mxc/ssi/ssi.c new file mode 100644 index 000000000000..f849a3ec7072 --- /dev/null +++ b/drivers/mxc/ssi/ssi.c @@ -0,0 +1,1221 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ssi.c + * @brief This file contains the implementation of the SSI driver main services + * + * + * @ingroup SSI + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "registers.h" +#include "ssi.h" + +static spinlock_t ssi_lock; +struct mxc_audio_platform_data *ssi_platform_data; + +EXPORT_SYMBOL(ssi_ac97_frame_rate_divider); +EXPORT_SYMBOL(ssi_ac97_get_command_address_register); +EXPORT_SYMBOL(ssi_ac97_get_command_data_register); +EXPORT_SYMBOL(ssi_ac97_get_tag_register); +EXPORT_SYMBOL(ssi_ac97_mode_enable); +EXPORT_SYMBOL(ssi_ac97_tag_in_fifo); +EXPORT_SYMBOL(ssi_ac97_read_command); +EXPORT_SYMBOL(ssi_ac97_set_command_address_register); +EXPORT_SYMBOL(ssi_ac97_set_command_data_register); +EXPORT_SYMBOL(ssi_ac97_set_tag_register); +EXPORT_SYMBOL(ssi_ac97_variable_mode); +EXPORT_SYMBOL(ssi_ac97_write_command); +EXPORT_SYMBOL(ssi_clock_idle_state); +EXPORT_SYMBOL(ssi_clock_off); +EXPORT_SYMBOL(ssi_enable); +EXPORT_SYMBOL(ssi_get_data); +EXPORT_SYMBOL(ssi_get_status); +EXPORT_SYMBOL(ssi_i2s_mode); +EXPORT_SYMBOL(ssi_interrupt_disable); +EXPORT_SYMBOL(ssi_interrupt_enable); +EXPORT_SYMBOL(ssi_network_mode); +EXPORT_SYMBOL(ssi_receive_enable); +EXPORT_SYMBOL(ssi_rx_bit0); +EXPORT_SYMBOL(ssi_rx_clock_direction); +EXPORT_SYMBOL(ssi_rx_clock_divide_by_two); +EXPORT_SYMBOL(ssi_rx_clock_polarity); +EXPORT_SYMBOL(ssi_rx_clock_prescaler); +EXPORT_SYMBOL(ssi_rx_early_frame_sync); +EXPORT_SYMBOL(ssi_rx_fifo_counter); +EXPORT_SYMBOL(ssi_rx_fifo_enable); +EXPORT_SYMBOL(ssi_rx_fifo_full_watermark); +EXPORT_SYMBOL(ssi_rx_flush_fifo); +EXPORT_SYMBOL(ssi_rx_frame_direction); +EXPORT_SYMBOL(ssi_rx_frame_rate); +EXPORT_SYMBOL(ssi_rx_frame_sync_active); +EXPORT_SYMBOL(ssi_rx_frame_sync_length); +EXPORT_SYMBOL(ssi_rx_mask_time_slot); +EXPORT_SYMBOL(ssi_rx_prescaler_modulus); +EXPORT_SYMBOL(ssi_rx_shift_direction); +EXPORT_SYMBOL(ssi_rx_word_length); +EXPORT_SYMBOL(ssi_set_data); +EXPORT_SYMBOL(ssi_set_wait_states); +EXPORT_SYMBOL(ssi_synchronous_mode); +EXPORT_SYMBOL(ssi_system_clock); +EXPORT_SYMBOL(ssi_transmit_enable); +EXPORT_SYMBOL(ssi_two_channel_mode); +EXPORT_SYMBOL(ssi_tx_bit0); +EXPORT_SYMBOL(ssi_tx_clock_direction); +EXPORT_SYMBOL(ssi_tx_clock_divide_by_two); +EXPORT_SYMBOL(ssi_tx_clock_polarity); +EXPORT_SYMBOL(ssi_tx_clock_prescaler); +EXPORT_SYMBOL(ssi_tx_early_frame_sync); +EXPORT_SYMBOL(ssi_tx_fifo_counter); +EXPORT_SYMBOL(ssi_tx_fifo_empty_watermark); +EXPORT_SYMBOL(ssi_tx_fifo_enable); +EXPORT_SYMBOL(ssi_tx_flush_fifo); +EXPORT_SYMBOL(ssi_tx_frame_direction); +EXPORT_SYMBOL(ssi_tx_frame_rate); +EXPORT_SYMBOL(ssi_tx_frame_sync_active); +EXPORT_SYMBOL(ssi_tx_frame_sync_length); +EXPORT_SYMBOL(ssi_tx_mask_time_slot); +EXPORT_SYMBOL(ssi_tx_prescaler_modulus); +EXPORT_SYMBOL(ssi_tx_shift_direction); +EXPORT_SYMBOL(ssi_tx_word_length); +EXPORT_SYMBOL(get_ssi_fifo_addr); + +struct resource *res; +unsigned long base_addr_1; +unsigned long base_addr_2; + +unsigned int get_ssi_fifo_addr(unsigned int ssi, int direction) +{ + unsigned int fifo_addr; + if (direction == 1) { + if (ssi_platform_data->ssi_num == 2) { + fifo_addr = + (ssi == + SSI1) ? (int)(base_addr_1 + + MXC_SSI1STX0) : (int)(base_addr_2 + + MXC_SSI2STX0); + } else { + fifo_addr = (int)(base_addr_1 + MXC_SSI1STX0); + } + } else { + fifo_addr = (int)(base_addr_1 + MXC_SSI1SRX0); + } + return fifo_addr; +} + +void *get_ssi_base_addr(unsigned int ssi) +{ + if (ssi_platform_data->ssi_num == 2) { + if (ssi == SSI1) + return IO_ADDRESS(base_addr_1); + else + return IO_ADDRESS(base_addr_2); + } + return IO_ADDRESS(base_addr_1); +} + +void set_register_bits(unsigned int mask, unsigned int data, + unsigned int offset, unsigned int ssi) +{ + volatile unsigned long reg = 0; + void *base_addr = get_ssi_base_addr(ssi); + unsigned long flags = 0; + + spin_lock_irqsave(&ssi_lock, flags); + reg = __raw_readl(base_addr + offset); + reg = (reg & (~mask)) | data; + __raw_writel(reg, base_addr + offset); + spin_unlock_irqrestore(&ssi_lock, flags); +} + +unsigned long getreg_value(unsigned int offset, unsigned int ssi) +{ + void *base_addr = get_ssi_base_addr(ssi); + return __raw_readl(base_addr + offset); +} + +void set_register(unsigned int data, unsigned int offset, unsigned int ssi) +{ + void *base_addr = get_ssi_base_addr(ssi); + __raw_writel(data, base_addr + offset); +} + +/*! + * This function controls the AC97 frame rate divider. + * + * @param module the module number + * @param frame_rate_divider the AC97 frame rate divider + */ +void ssi_ac97_frame_rate_divider(ssi_mod module, + unsigned char frame_rate_divider) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + reg |= ((frame_rate_divider & AC97_FRAME_RATE_MASK) + << AC97_FRAME_RATE_DIVIDER_SHIFT); + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function gets the AC97 command address register. + * + * @param module the module number + * @return This function returns the command address slot information. + */ +unsigned int ssi_ac97_get_command_address_register(ssi_mod module) +{ + return getreg_value(MXC_SSISACADD, module); +} + +/*! + * This function gets the AC97 command data register. + * + * @param module the module number + * @return This function returns the command data slot information. + */ +unsigned int ssi_ac97_get_command_data_register(ssi_mod module) +{ + return getreg_value(MXC_SSISACDAT, module); +} + +/*! + * This function gets the AC97 tag register. + * + * @param module the module number + * @return This function returns the tag information. + */ +unsigned int ssi_ac97_get_tag_register(ssi_mod module) +{ + return getreg_value(MXC_SSISATAG, module); +} + +/*! + * This function controls the AC97 mode. + * + * @param module the module number + * @param state the AC97 mode state (enabled or disabled) + */ +void ssi_ac97_mode_enable(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_MODE_ENABLE_SHIFT); + } else { + reg &= ~(1 << AC97_MODE_ENABLE_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function controls the AC97 tag in FIFO behavior. + * + * @param module the module number + * @param state the tag in fifo behavior (Tag info stored in Rx FIFO 0 if true, + * Tag info stored in SATAG register otherwise) + */ +void ssi_ac97_tag_in_fifo(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_TAG_IN_FIFO_SHIFT); + } else { + reg &= ~(1 << AC97_TAG_IN_FIFO_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function controls the AC97 read command. + * + * @param module the module number + * @param state the next AC97 command is a read command or not + */ +void ssi_ac97_read_command(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_READ_COMMAND_SHIFT); + } else { + reg &= ~(1 << AC97_READ_COMMAND_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function sets the AC97 command address register. + * + * @param module the module number + * @param address the command address slot information + */ +void ssi_ac97_set_command_address_register(ssi_mod module, unsigned int address) +{ + set_register(address, MXC_SSISACADD, module); +} + +/*! + * This function sets the AC97 command data register. + * + * @param module the module number + * @param data the command data slot information + */ +void ssi_ac97_set_command_data_register(ssi_mod module, unsigned int data) +{ + set_register(data, MXC_SSISACDAT, module); +} + +/*! + * This function sets the AC97 tag register. + * + * @param module the module number + * @param tag the tag information + */ +void ssi_ac97_set_tag_register(ssi_mod module, unsigned int tag) +{ + set_register(tag, MXC_SSISATAG, module); +} + +/*! + * This function controls the AC97 variable mode. + * + * @param module the module number + * @param state the AC97 variable mode state (enabled or disabled) + */ void ssi_ac97_variable_mode(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_VARIABLE_OPERATION_SHIFT); + } else { + reg &= ~(1 << AC97_VARIABLE_OPERATION_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function controls the AC97 write command. + * + * @param module the module number + * @param state the next AC97 command is a write command or not + */ +void ssi_ac97_write_command(ssi_mod module, bool state) +{ + unsigned int reg = 0; + + reg = getreg_value(MXC_SSISACNT, module); + if (state == true) { + reg |= (1 << AC97_WRITE_COMMAND_SHIFT); + } else { + reg &= ~(1 << AC97_WRITE_COMMAND_SHIFT); + } + + set_register(reg, MXC_SSISACNT, module); +} + +/*! + * This function controls the idle state of the transmit clock port during SSI internal gated mode. + * + * @param module the module number + * @param state the clock idle state + */ +void ssi_clock_idle_state(ssi_mod module, idle_state state) +{ + set_register_bits(1 << SSI_CLOCK_IDLE_SHIFT, + state << SSI_CLOCK_IDLE_SHIFT, MXC_SSISCR, module); +} + +/*! + * This function turns off/on the ccm_ssi_clk to reduce power consumption. + * + * @param module the module number + * @param state the state for ccm_ssi_clk (true: turn off, else:turn on) + */ +void ssi_clock_off(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_CLOCK_OFF_SHIFT, + state << SSI_CLOCK_OFF_SHIFT, MXC_SSISOR, module); +} + +/*! + * This function enables/disables the SSI module. + * + * @param module the module number + * @param state the state for SSI module + */ +void ssi_enable(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_ENABLE_SHIFT, state << SSI_ENABLE_SHIFT, + MXC_SSISCR, module); +} + +/*! + * This function gets the data word in the Receive FIFO of the SSI module. + * + * @param module the module number + * @param fifo the Receive FIFO to read + * @return This function returns the read data. + */ +unsigned int ssi_get_data(ssi_mod module, fifo_nb fifo) +{ + unsigned int result = 0; + + if (ssi_fifo_0 == fifo) { + result = getreg_value(MXC_SSISRX0, module); + } else { + result = getreg_value(MXC_SSISRX1, module); + } + + return result; +} + +/*! + * This function returns the status of the SSI module (SISR register) as a combination of status. + * + * @param module the module number + * @return This function returns the status of the SSI module + */ +ssi_status_enable_mask ssi_get_status(ssi_mod module) +{ + unsigned int result; + + result = getreg_value(MXC_SSISISR, module); + result &= ((1 << SSI_IRQ_STATUS_NUMBER) - 1); + + return (ssi_status_enable_mask) result; +} + +/*! + * This function selects the I2S mode of the SSI module. + * + * @param module the module number + * @param mode the I2S mode + */ +void ssi_i2s_mode(ssi_mod module, mode_i2s mode) +{ + set_register_bits(3 << SSI_I2S_MODE_SHIFT, mode << SSI_I2S_MODE_SHIFT, + MXC_SSISCR, module); +} + +/*! + * This function disables the interrupts of the SSI module. + * + * @param module the module number + * @param mask the mask of the interrupts to disable + */ +void ssi_interrupt_disable(ssi_mod module, ssi_status_enable_mask mask) +{ + set_register_bits(mask, 0, MXC_SSISIER, module); +} + +/*! + * This function enables the interrupts of the SSI module. + * + * @param module the module number + * @param mask the mask of the interrupts to enable + */ +void ssi_interrupt_enable(ssi_mod module, ssi_status_enable_mask mask) +{ + set_register_bits(0, mask, MXC_SSISIER, module); +} + +/*! + * This function enables/disables the network mode of the SSI module. + * + * @param module the module number + * @param state the network mode state + */ +void ssi_network_mode(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_NETWORK_MODE_SHIFT, + state << SSI_NETWORK_MODE_SHIFT, MXC_SSISCR, module); +} + +/*! + * This function enables/disables the receive section of the SSI module. + * + * @param module the module number + * @param state the receive section state + */ +void ssi_receive_enable(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_RECEIVE_ENABLE_SHIFT, + state << SSI_RECEIVE_ENABLE_SHIFT, MXC_SSISCR, + module); +} + +/*! + * This function configures the SSI module to receive data word at bit position 0 or 23 in the Receive shift register. + * + * @param module the module number + * @param state the state to receive at bit 0 + */ +void ssi_rx_bit0(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_BIT_0_SHIFT, state << SSI_BIT_0_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function controls the source of the clock signal used to clock the Receive shift register. + * + * @param module the module number + * @param direction the clock signal direction + */ +void ssi_rx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction) +{ + set_register_bits(1 << SSI_CLOCK_DIRECTION_SHIFT, + direction << SSI_CLOCK_DIRECTION_SHIFT, MXC_SSISRCR, + module); +} + +/*! + * This function configures the divide-by-two divider of the SSI module for the receive section. + * + * @param module the module number + * @param state the divider state + */ +void ssi_rx_clock_divide_by_two(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_DIVIDE_BY_TWO_SHIFT, + state << SSI_DIVIDE_BY_TWO_SHIFT, MXC_SSISRCCR, + module); +} + +/*! + * This function controls which bit clock edge is used to clock in data. + * + * @param module the module number + * @param polarity the clock polarity + */ +void ssi_rx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity) +{ + set_register_bits(1 << SSI_CLOCK_POLARITY_SHIFT, + polarity << SSI_CLOCK_POLARITY_SHIFT, MXC_SSISRCR, + module); +} + +/*! + * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the receive section. + * + * @param module the module number + * @param state the prescaler state + */ +void ssi_rx_clock_prescaler(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_PRESCALER_RANGE_SHIFT, + state << SSI_PRESCALER_RANGE_SHIFT, + MXC_SSISRCCR, module); +} + +/*! + * This function controls the early frame sync configuration. + * + * @param module the module number + * @param early the early frame sync configuration + */ +void ssi_rx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early) +{ + set_register_bits(1 << SSI_EARLY_FRAME_SYNC_SHIFT, + early << SSI_EARLY_FRAME_SYNC_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function gets the number of data words in the Receive FIFO. + * + * @param module the module number + * @param fifo the fifo + * @return This function returns the number of words in the Rx FIFO. + */ +unsigned char ssi_rx_fifo_counter(ssi_mod module, fifo_nb fifo) +{ + unsigned char result; + result = 0; + + if (ssi_fifo_0 == fifo) { + result = getreg_value(MXC_SSISFCSR, module); + result &= (0xF << SSI_RX_FIFO_0_COUNT_SHIFT); + result = result >> SSI_RX_FIFO_0_COUNT_SHIFT; + } else { + result = getreg_value(MXC_SSISFCSR, module); + result &= (0xF << SSI_RX_FIFO_1_COUNT_SHIFT); + result = result >> SSI_RX_FIFO_1_COUNT_SHIFT; + } + + return result; +} + +/*! + * This function enables the Receive FIFO. + * + * @param module the module number + * @param fifo the fifo to enable + * @param enable the state of the fifo, enabled or disabled + */ + +void ssi_rx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable) +{ + volatile unsigned int reg; + + reg = getreg_value(MXC_SSISRCR, module); + if (enable == true) { + reg |= ((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT); + } else { + reg &= ~((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT); + } + + set_register(reg, MXC_SSISRCR, module); +} + +/*! + * This function controls the threshold at which the RFFx flag will be set. + * + * @param module the module number + * @param fifo the fifo to enable + * @param watermark the watermark + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_fifo_full_watermark(ssi_mod module, + fifo_nb fifo, unsigned char watermark) +{ + int result = -1; + result = -1; + + if ((watermark > SSI_MIN_FIFO_WATERMARK) && + (watermark <= SSI_MAX_FIFO_WATERMARK)) { + if (ssi_fifo_0 == fifo) { + set_register_bits(0xf << SSI_RX_FIFO_0_WATERMARK_SHIFT, + watermark << + SSI_RX_FIFO_0_WATERMARK_SHIFT, + MXC_SSISFCSR, module); + } else { + set_register_bits(0xf << SSI_RX_FIFO_1_WATERMARK_SHIFT, + watermark << + SSI_RX_FIFO_1_WATERMARK_SHIFT, + MXC_SSISFCSR, module); + } + + result = 0; + } + + return result; +} + +/*! + * This function flushes the Receive FIFOs. + * + * @param module the module number + */ +void ssi_rx_flush_fifo(ssi_mod module) +{ + set_register_bits(0, 1 << SSI_RECEIVER_CLEAR_SHIFT, MXC_SSISOR, module); +} + +/*! + * This function controls the direction of the Frame Sync signal for the receive section. + * + * @param module the module number + * @param direction the Frame Sync signal direction + */ +void ssi_rx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction) +{ + set_register_bits(1 << SSI_FRAME_DIRECTION_SHIFT, + direction << SSI_FRAME_DIRECTION_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function configures the Receive frame rate divider for the receive section. + * + * @param module the module number + * @param ratio the divide ratio from 1 to 32 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_frame_rate(ssi_mod module, unsigned char ratio) +{ + int result = -1; + + if ((ratio >= SSI_MIN_FRAME_DIVIDER_RATIO) && + (ratio <= SSI_MAX_FRAME_DIVIDER_RATIO)) { + set_register_bits(SSI_FRAME_DIVIDER_MASK << + SSI_FRAME_RATE_DIVIDER_SHIFT, + (ratio - 1) << SSI_FRAME_RATE_DIVIDER_SHIFT, + MXC_SSISRCCR, module); + result = 0; + } + + return result; +} + +/*! + * This function controls the Frame Sync active polarity for the receive section. + * + * @param module the module number + * @param active the Frame Sync active polarity + */ +void ssi_rx_frame_sync_active(ssi_mod module, + ssi_tx_rx_frame_sync_active active) +{ + set_register_bits(1 << SSI_FRAME_SYNC_INVERT_SHIFT, + active << SSI_FRAME_SYNC_INVERT_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function controls the Frame Sync length (one word or one bit long) for the receive section. + * + * @param module the module number + * @param length the Frame Sync length + */ +void ssi_rx_frame_sync_length(ssi_mod module, + ssi_tx_rx_frame_sync_length length) +{ + set_register_bits(1 << SSI_FRAME_SYNC_LENGTH_SHIFT, + length << SSI_FRAME_SYNC_LENGTH_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function configures the time slot(s) to mask for the receive section. + * + * @param module the module number + * @param mask the mask to indicate the time slot(s) masked + */ +void ssi_rx_mask_time_slot(ssi_mod module, unsigned int mask) +{ + set_register_bits(0xFFFFFFFF, mask, MXC_SSISRMSK, module); +} + +/*! + * This function configures the Prescale divider for the receive section. + * + * @param module the module number + * @param divider the divide ratio from 1 to 256 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_prescaler_modulus(ssi_mod module, unsigned int divider) +{ + int result = -1; + + if ((divider >= SSI_MIN_PRESCALER_MODULUS_RATIO) && + (divider <= SSI_MAX_PRESCALER_MODULUS_RATIO)) { + + set_register_bits(SSI_PRESCALER_MODULUS_MASK << + SSI_PRESCALER_MODULUS_SHIFT, + (divider - 1) << SSI_PRESCALER_MODULUS_SHIFT, + MXC_SSISRCCR, module); + result = 0; + } + + return result; +} + +/*! + * This function controls whether the MSB or LSB will be received first in a sample. + * + * @param module the module number + * @param direction the shift direction + */ +void ssi_rx_shift_direction(ssi_mod module, ssi_tx_rx_shift_direction direction) +{ + set_register_bits(1 << SSI_SHIFT_DIRECTION_SHIFT, + direction << SSI_SHIFT_DIRECTION_SHIFT, + MXC_SSISRCR, module); +} + +/*! + * This function configures the Receive word length. + * + * @param module the module number + * @param length the word length + */ +void ssi_rx_word_length(ssi_mod module, ssi_word_length length) +{ + set_register_bits(SSI_WORD_LENGTH_MASK << SSI_WORD_LENGTH_SHIFT, + length << SSI_WORD_LENGTH_SHIFT, + MXC_SSISRCCR, module); +} + +/*! + * This function sets the data word in the Transmit FIFO of the SSI module. + * + * @param module the module number + * @param fifo the FIFO number + * @param data the data to load in the FIFO + */ + +void ssi_set_data(ssi_mod module, fifo_nb fifo, unsigned int data) +{ + if (ssi_fifo_0 == fifo) { + set_register(data, MXC_SSISTX0, module); + } else { + set_register(data, MXC_SSISTX1, module); + } +} + +/*! + * This function controls the number of wait states between the core and SSI. + * + * @param module the module number + * @param wait the number of wait state(s) + */ +void ssi_set_wait_states(ssi_mod module, ssi_wait_states wait) +{ + set_register_bits(SSI_WAIT_STATE_MASK << SSI_WAIT_SHIFT, + wait << SSI_WAIT_SHIFT, MXC_SSISOR, module); +} + +/*! + * This function enables/disables the synchronous mode of the SSI module. + * + * @param module the module number + * @param state the synchronous mode state + */ +void ssi_synchronous_mode(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_SYNCHRONOUS_MODE_SHIFT, + state << SSI_SYNCHRONOUS_MODE_SHIFT, + MXC_SSISCR, module); +} + +/*! + * This function allows the SSI module to output the SYS_CLK at the SRCK port. + * + * @param module the module number + * @param state the system clock state + */ +void ssi_system_clock(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_SYSTEM_CLOCK_SHIFT, + state << SSI_SYSTEM_CLOCK_SHIFT, MXC_SSISCR, module); +} + +/*! + * This function enables/disables the transmit section of the SSI module. + * + * @param module the module number + * @param state the transmit section state + */ +void ssi_transmit_enable(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_TRANSMIT_ENABLE_SHIFT, + state << SSI_TRANSMIT_ENABLE_SHIFT, + MXC_SSISCR, module); +} + +/*! + * This function allows the SSI module to operate in the two channel mode. + * + * @param module the module number + * @param state the two channel mode state + */ +void ssi_two_channel_mode(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_TWO_CHANNEL_SHIFT, + state << SSI_TWO_CHANNEL_SHIFT, MXC_SSISCR, module); +} + +/*! + * This function configures the SSI module to transmit data word from bit position 0 or 23 in the Transmit shift register. + * + * @param module the module number + * @param state the transmit from bit 0 state + */ +void ssi_tx_bit0(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_BIT_0_SHIFT, + state << SSI_BIT_0_SHIFT, MXC_SSISTCR, module); +} + +/*! + * This function controls the direction of the clock signal used to clock the Transmit shift register. + * + * @param module the module number + * @param direction the clock signal direction + */ +void ssi_tx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction) +{ + set_register_bits(1 << SSI_CLOCK_DIRECTION_SHIFT, + direction << SSI_CLOCK_DIRECTION_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures the divide-by-two divider of the SSI module for the transmit section. + * + * @param module the module number + * @param state the divider state + */ +void ssi_tx_clock_divide_by_two(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_DIVIDE_BY_TWO_SHIFT, + state << SSI_DIVIDE_BY_TWO_SHIFT, + MXC_SSISTCCR, module); +} + +/*! + * This function controls which bit clock edge is used to clock out data. + * + * @param module the module number + * @param polarity the clock polarity + */ +void ssi_tx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity) +{ + set_register_bits(1 << SSI_CLOCK_POLARITY_SHIFT, + polarity << SSI_CLOCK_POLARITY_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the transmit section. + * + * @param module the module number + * @param state the prescaler state + */ +void ssi_tx_clock_prescaler(ssi_mod module, bool state) +{ + set_register_bits(1 << SSI_PRESCALER_RANGE_SHIFT, + state << SSI_PRESCALER_RANGE_SHIFT, + MXC_SSISTCCR, module); +} + +/*! + * This function controls the early frame sync configuration for the transmit section. + * + * @param module the module number + * @param early the early frame sync configuration + */ +void ssi_tx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early) +{ + set_register_bits(1 << SSI_EARLY_FRAME_SYNC_SHIFT, + early << SSI_EARLY_FRAME_SYNC_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function gets the number of data words in the Transmit FIFO. + * + * @param module the module number + * @param fifo the fifo + * @return This function returns the number of words in the Tx FIFO. + */ +unsigned char ssi_tx_fifo_counter(ssi_mod module, fifo_nb fifo) +{ + unsigned char result = 0; + + if (ssi_fifo_0 == fifo) { + result = getreg_value(MXC_SSISFCSR, module); + result &= (0xF << SSI_TX_FIFO_0_COUNT_SHIFT); + result >>= SSI_TX_FIFO_0_COUNT_SHIFT; + } else { + result = getreg_value(MXC_SSISFCSR, module); + result &= (0xF << SSI_TX_FIFO_1_COUNT_SHIFT); + result >>= SSI_TX_FIFO_1_COUNT_SHIFT; + } + + return result; +} + +/*! + * This function controls the threshold at which the TFEx flag will be set. + * + * @param module the module number + * @param fifo the fifo to enable + * @param watermark the watermark + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_fifo_empty_watermark(ssi_mod module, + fifo_nb fifo, unsigned char watermark) +{ + int result = -1; + + if ((watermark > SSI_MIN_FIFO_WATERMARK) && + (watermark <= SSI_MAX_FIFO_WATERMARK)) { + if (ssi_fifo_0 == fifo) { + set_register_bits(0xf << SSI_TX_FIFO_0_WATERMARK_SHIFT, + watermark << + SSI_TX_FIFO_0_WATERMARK_SHIFT, + MXC_SSISFCSR, module); + } else { + set_register_bits(0xf << SSI_TX_FIFO_1_WATERMARK_SHIFT, + watermark << + SSI_TX_FIFO_1_WATERMARK_SHIFT, + MXC_SSISFCSR, module); + } + + result = 0; + } + + return result; +} + +/*! + * This function enables the Transmit FIFO. + * + * @param module the module number + * @param fifo the fifo to enable + * @param enable the state of the fifo, enabled or disabled + */ + +void ssi_tx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable) +{ + unsigned int reg; + + reg = getreg_value(MXC_SSISTCR, module); + if (enable == true) { + reg |= ((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT); + } else { + reg &= ~((1 + fifo) << SSI_FIFO_ENABLE_0_SHIFT); + } + + set_register(reg, MXC_SSISTCR, module); +} + +/*! + * This function flushes the Transmit FIFOs. + * + * @param module the module number + */ +void ssi_tx_flush_fifo(ssi_mod module) +{ + set_register_bits(0, 1 << SSI_TRANSMITTER_CLEAR_SHIFT, + MXC_SSISOR, module); +} + +/*! + * This function controls the direction of the Frame Sync signal for the transmit section. + * + * @param module the module number + * @param direction the Frame Sync signal direction + */ +void ssi_tx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction) +{ + set_register_bits(1 << SSI_FRAME_DIRECTION_SHIFT, + direction << SSI_FRAME_DIRECTION_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures the Transmit frame rate divider. + * + * @param module the module number + * @param ratio the divide ratio from 1 to 32 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_frame_rate(ssi_mod module, unsigned char ratio) +{ + int result = -1; + + if ((ratio >= SSI_MIN_FRAME_DIVIDER_RATIO) && + (ratio <= SSI_MAX_FRAME_DIVIDER_RATIO)) { + + set_register_bits(SSI_FRAME_DIVIDER_MASK << + SSI_FRAME_RATE_DIVIDER_SHIFT, + (ratio - 1) << SSI_FRAME_RATE_DIVIDER_SHIFT, + MXC_SSISTCCR, module); + result = 0; + } + + return result; +} + +/*! + * This function controls the Frame Sync active polarity for the transmit section. + * + * @param module the module number + * @param active the Frame Sync active polarity + */ +void ssi_tx_frame_sync_active(ssi_mod module, + ssi_tx_rx_frame_sync_active active) +{ + set_register_bits(1 << SSI_FRAME_SYNC_INVERT_SHIFT, + active << SSI_FRAME_SYNC_INVERT_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function controls the Frame Sync length (one word or one bit long) for the transmit section. + * + * @param module the module number + * @param length the Frame Sync length + */ +void ssi_tx_frame_sync_length(ssi_mod module, + ssi_tx_rx_frame_sync_length length) +{ + set_register_bits(1 << SSI_FRAME_SYNC_LENGTH_SHIFT, + length << SSI_FRAME_SYNC_LENGTH_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures the time slot(s) to mask for the transmit section. + * + * @param module the module number + * @param mask the mask to indicate the time slot(s) masked + */ +void ssi_tx_mask_time_slot(ssi_mod module, unsigned int mask) +{ + set_register_bits(0xFFFFFFFF, mask, MXC_SSISTMSK, module); +} + +/*! + * This function configures the Prescale divider for the transmit section. + * + * @param module the module number + * @param divider the divide ratio from 1 to 256 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_prescaler_modulus(ssi_mod module, unsigned int divider) +{ + int result = -1; + + if ((divider >= SSI_MIN_PRESCALER_MODULUS_RATIO) && + (divider <= SSI_MAX_PRESCALER_MODULUS_RATIO)) { + + set_register_bits(SSI_PRESCALER_MODULUS_MASK << + SSI_PRESCALER_MODULUS_SHIFT, + (divider - 1) << SSI_PRESCALER_MODULUS_SHIFT, + MXC_SSISTCCR, module); + result = 0; + } + + return result; +} + +/*! + * This function controls whether the MSB or LSB will be transmitted first in a sample. + * + * @param module the module number + * @param direction the shift direction + */ +void ssi_tx_shift_direction(ssi_mod module, ssi_tx_rx_shift_direction direction) +{ + set_register_bits(1 << SSI_SHIFT_DIRECTION_SHIFT, + direction << SSI_SHIFT_DIRECTION_SHIFT, + MXC_SSISTCR, module); +} + +/*! + * This function configures the Transmit word length. + * + * @param module the module number + * @param length the word length + */ +void ssi_tx_word_length(ssi_mod module, ssi_word_length length) +{ + set_register_bits(SSI_WORD_LENGTH_MASK << SSI_WORD_LENGTH_SHIFT, + length << SSI_WORD_LENGTH_SHIFT, + MXC_SSISTCCR, module); +} + +/*! + * This function initializes the driver in terms of memory of the soundcard + * and some basic HW clock settings. + * + * @return 0 on success, -1 otherwise. + */ +static int __init ssi_probe(struct platform_device *pdev) +{ + int ret = -1; + ssi_platform_data = + (struct mxc_audio_platform_data *)pdev->dev.platform_data; + if (!ssi_platform_data) { + dev_err(&pdev->dev, "can't get the platform data for SSI\n"); + return -EINVAL; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res) { + dev_err(&pdev->dev, "can't get platform resource - SSI\n"); + ret = -ENOMEM; + goto err; + } + + if (pdev->id == 0) { + base_addr_1 = res->start; + } else if (pdev->id == 1) { + base_addr_2 = res->start; + } + + printk(KERN_INFO "SSI %d module loaded successfully \n", pdev->id + 1); + + return 0; + err: + return -1; + +} + +static int ssi_remove(struct platform_device *dev) +{ + return 0; +} + +static struct platform_driver mxc_ssi_driver = { + .probe = ssi_probe, + .remove = ssi_remove, + .driver = { + .name = "mxc_ssi", + }, +}; + +/*! + * This function implements the init function of the SSI device. + * This function is called when the module is loaded. + * + * @return This function returns 0. + */ +static int __init ssi_init(void) +{ + spin_lock_init(&ssi_lock); + return platform_driver_register(&mxc_ssi_driver); + +} + +/*! + * This function implements the exit function of the SPI device. + * This function is called when the module is unloaded. + * + */ +static void __exit ssi_exit(void) +{ + platform_driver_unregister(&mxc_ssi_driver); + printk(KERN_INFO "SSI module unloaded successfully\n"); +} + +module_init(ssi_init); +module_exit(ssi_exit); + +MODULE_DESCRIPTION("SSI char device driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/mxc/ssi/ssi.h b/drivers/mxc/ssi/ssi.h new file mode 100644 index 000000000000..6edd3a3b3110 --- /dev/null +++ b/drivers/mxc/ssi/ssi.h @@ -0,0 +1,574 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @defgroup SSI Synchronous Serial Interface (SSI) Driver + */ + + /*! + * @file ssi.h + * @brief This header file contains SSI driver functions prototypes. + * + * @ingroup SSI + */ + +#ifndef __MXC_SSI_H__ +#define __MXC_SSI_H__ + +#include "ssi_types.h" + +/*! + * This function gets the SSI fifo address. + * + * @param ssi ssi number + * @param direction To indicate playback / recording + * @return This function returns the SSI fifo address. + */ +unsigned int get_ssi_fifo_addr(unsigned int ssi, int direction); + +/*! + * This function controls the AC97 frame rate divider. + * + * @param module the module number + * @param frame_rate_divider the AC97 frame rate divider + */ +void ssi_ac97_frame_rate_divider(ssi_mod module, + unsigned char frame_rate_divider); + +/*! + * This function gets the AC97 command address register. + * + * @param module the module number + * @return This function returns the command address slot information. + */ +unsigned int ssi_ac97_get_command_address_register(ssi_mod module); + +/*! + * This function gets the AC97 command data register. + * + * @param module the module number + * @return This function returns the command data slot information. + */ +unsigned int ssi_ac97_get_command_data_register(ssi_mod module); + +/*! + * This function gets the AC97 tag register. + * + * @param module the module number + * @return This function returns the tag information. + */ +unsigned int ssi_ac97_get_tag_register(ssi_mod module); + +/*! + * This function controls the AC97 mode. + * + * @param module the module number + * @param state the AC97 mode state (enabled or disabled) + */ +void ssi_ac97_mode_enable(ssi_mod module, bool state); + +/*! + * This function controls the AC97 tag in FIFO behavior. + * + * @param module the module number + * @param state the tag in fifo behavior (Tag info stored in Rx FIFO 0 if TRUE, + * Tag info stored in SATAG register otherwise) + */ +void ssi_ac97_tag_in_fifo(ssi_mod module, bool state); + +/*! + * This function controls the AC97 read command. + * + * @param module the module number + * @param state the next AC97 command is a read command or not + */ +void ssi_ac97_read_command(ssi_mod module, bool state); + +/*! + * This function sets the AC97 command address register. + * + * @param module the module number + * @param address the command address slot information + */ +void ssi_ac97_set_command_address_register(ssi_mod module, + unsigned int address); + +/*! + * This function sets the AC97 command data register. + * + * @param module the module number + * @param data the command data slot information + */ +void ssi_ac97_set_command_data_register(ssi_mod module, unsigned int data); + +/*! + * This function sets the AC97 tag register. + * + * @param module the module number + * @param tag the tag information + */ +void ssi_ac97_set_tag_register(ssi_mod module, unsigned int tag); + +/*! + * This function controls the AC97 variable mode. + * + * @param module the module number + * @param state the AC97 variable mode state (enabled or disabled) + */ +void ssi_ac97_variable_mode(ssi_mod module, bool state); + +/*! + * This function controls the AC97 write command. + * + * @param module the module number + * @param state the next AC97 command is a write command or not + */ +void ssi_ac97_write_command(ssi_mod module, bool state); + +/*! + * This function controls the idle state of the transmit clock port during SSI internal gated mode. + * + * @param module the module number + * @param state the clock idle state + */ +void ssi_clock_idle_state(ssi_mod module, idle_state state); + +/*! + * This function turns off/on the ccm_ssi_clk to reduce power consumption. + * + * @param module the module number + * @param state the state for ccm_ssi_clk (true: turn off, else:turn on) + */ +void ssi_clock_off(ssi_mod module, bool state); + +/*! + * This function enables/disables the SSI module. + * + * @param module the module number + * @param state the state for SSI module + */ +void ssi_enable(ssi_mod module, bool state); + +/*! + * This function gets the data word in the Receive FIFO of the SSI module. + * + * @param module the module number + * @param fifo the Receive FIFO to read + * @return This function returns the read data. + */ +unsigned int ssi_get_data(ssi_mod module, fifo_nb fifo); + +/*! + * This function returns the status of the SSI module (SISR register) as a combination of status. + * + * @param module the module number + * @return This function returns the status of the SSI module. + */ +ssi_status_enable_mask ssi_get_status(ssi_mod module); + +/*! + * This function selects the I2S mode of the SSI module. + * + * @param module the module number + * @param mode the I2S mode + */ +void ssi_i2s_mode(ssi_mod module, mode_i2s mode); + +/*! + * This function disables the interrupts of the SSI module. + * + * @param module the module number + * @param mask the mask of the interrupts to disable + */ +void ssi_interrupt_disable(ssi_mod module, ssi_status_enable_mask mask); + +/*! + * This function enables the interrupts of the SSI module. + * + * @param module the module number + * @param mask the mask of the interrupts to enable + */ +void ssi_interrupt_enable(ssi_mod module, ssi_status_enable_mask mask); + +/*! + * This function enables/disables the network mode of the SSI module. + * + * @param module the module number + * @param state the network mode state + */ +void ssi_network_mode(ssi_mod module, bool state); + +/*! + * This function enables/disables the receive section of the SSI module. + * + * @param module the module number + * @param state the receive section state + */ +void ssi_receive_enable(ssi_mod module, bool state); + +/*! + * This function configures the SSI module to receive data word at bit position 0 or 23 in the Receive shift register. + * + * @param module the module number + * @param state the state to receive at bit 0 + */ +void ssi_rx_bit0(ssi_mod module, bool state); + +/*! + * This function controls the source of the clock signal used to clock the Receive shift register. + * + * @param module the module number + * @param direction the clock signal direction + */ +void ssi_rx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction); + +/*! + * This function configures the divide-by-two divider of the SSI module for the receive section. + * + * @param module the module number + * @param state the divider state + */ +void ssi_rx_clock_divide_by_two(ssi_mod module, bool state); + +/*! + * This function controls which bit clock edge is used to clock in data. + * + * @param module the module number + * @param polarity the clock polarity + */ +void ssi_rx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity); + +/*! + * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the receive section. + * + * @param module the module number + * @param state the prescaler state + */ +void ssi_rx_clock_prescaler(ssi_mod module, bool state); + +/*! + * This function controls the early frame sync configuration. + * + * @param module the module number + * @param early the early frame sync configuration + */ +void ssi_rx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early); + +/*! + * This function gets the number of data words in the Receive FIFO. + * + * @param module the module number + * @param fifo the fifo + * @return This function returns the number of words in the Rx FIFO. + */ +unsigned char ssi_rx_fifo_counter(ssi_mod module, fifo_nb fifo); + +/*! + * This function enables the Receive FIFO. + * + * @param module the module number + * @param fifo the fifo to enable + * @param enabled the state of the fifo, enabled or disabled + */ +void ssi_rx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enabled); + +/*! + * This function controls the threshold at which the RFFx flag will be set. + * + * @param module the module number + * @param fifo the fifo to enable + * @param watermark the watermark + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_fifo_full_watermark(ssi_mod module, + fifo_nb fifo, unsigned char watermark); + +/*! + * This function flushes the Receive FIFOs. + * + * @param module the module number + */ +void ssi_rx_flush_fifo(ssi_mod module); + +/*! + * This function controls the direction of the Frame Sync signal for the receive section. + * + * @param module the module number + * @param direction the Frame Sync signal direction + */ +void ssi_rx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction); + +/*! + * This function configures the Receive frame rate divider for the receive section. + * + * @param module the module number + * @param ratio the divide ratio from 1 to 32 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_frame_rate(ssi_mod module, unsigned char ratio); + +/*! + * This function controls the Frame Sync active polarity for the receive section. + * + * @param module the module number + * @param active the Frame Sync active polarity + */ +void ssi_rx_frame_sync_active(ssi_mod module, + ssi_tx_rx_frame_sync_active active); + +/*! + * This function controls the Frame Sync length (one word or one bit long) for the receive section. + * + * @param module the module number + * @param length the Frame Sync length + */ +void ssi_rx_frame_sync_length(ssi_mod module, + ssi_tx_rx_frame_sync_length length); + +/*! + * This function configures the time slot(s) to mask for the receive section. + * + * @param module the module number + * @param mask the mask to indicate the time slot(s) masked + */ +void ssi_rx_mask_time_slot(ssi_mod module, unsigned int mask); + +/*! + * This function configures the Prescale divider for the receive section. + * + * @param module the module number + * @param divider the divide ratio from 1 to 256 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_rx_prescaler_modulus(ssi_mod module, unsigned int divider); + +/*! + * This function controls whether the MSB or LSB will be received first in a sample. + * + * @param module the module number + * @param direction the shift direction + */ +void ssi_rx_shift_direction(ssi_mod module, + ssi_tx_rx_shift_direction direction); + +/*! + * This function configures the Receive word length. + * + * @param module the module number + * @param length the word length + */ +void ssi_rx_word_length(ssi_mod module, ssi_word_length length); + +/*! + * This function sets the data word in the Transmit FIFO of the SSI module. + * + * @param module the module number + * @param fifo the FIFO number + * @param data the data to load in the FIFO + */ +void ssi_set_data(ssi_mod module, fifo_nb fifo, unsigned int data); + +/*! + * This function controls the number of wait states between the core and SSI. + * + * @param module the module number + * @param wait the number of wait state(s) + */ +void ssi_set_wait_states(ssi_mod module, ssi_wait_states wait); + +/*! + * This function enables/disables the synchronous mode of the SSI module. + * + * @param module the module number + * @param state the synchronous mode state + */ +void ssi_synchronous_mode(ssi_mod module, bool state); + +/*! + * This function allows the SSI module to output the SYS_CLK at the SRCK port. + * + * @param module the module number + * @param state the system clock state + */ +void ssi_system_clock(ssi_mod module, bool state); + +/*! + * This function enables/disables the transmit section of the SSI module. + * + * @param module the module number + * @param state the transmit section state + */ +void ssi_transmit_enable(ssi_mod module, bool state); + +/*! + * This function allows the SSI module to operate in the two channel mode. + * + * @param module the module number + * @param state the two channel mode state + */ +void ssi_two_channel_mode(ssi_mod module, bool state); + +/*! + * This function configures the SSI module to transmit data word from bit position 0 or 23 in the Transmit shift register. + * + * @param module the module number + * @param state the transmit from bit 0 state + */ +void ssi_tx_bit0(ssi_mod module, bool state); + +/*! + * This function controls the direction of the clock signal used to clock the Transmit shift register. + * + * @param module the module number + * @param direction the clock signal direction + */ +void ssi_tx_clock_direction(ssi_mod module, ssi_tx_rx_direction direction); + +/*! + * This function configures the divide-by-two divider of the SSI module for the transmit section. + * + * @param module the module number + * @param state the divider state + */ +void ssi_tx_clock_divide_by_two(ssi_mod module, bool state); + +/*! + * This function controls which bit clock edge is used to clock out data. + * + * @param module the module number + * @param polarity the clock polarity + */ +void ssi_tx_clock_polarity(ssi_mod module, ssi_tx_rx_clock_polarity polarity); + +/*! + * This function configures a fixed divide-by-eight clock prescaler divider of the SSI module in series with the variable prescaler for the transmit section. + * + * @param module the module number + * @param state the prescaler state + */ +void ssi_tx_clock_prescaler(ssi_mod module, bool state); + +/*! + * This function controls the early frame sync configuration for the transmit section. + * + * @param module the module number + * @param early the early frame sync configuration + */ +void ssi_tx_early_frame_sync(ssi_mod module, ssi_tx_rx_early_frame_sync early); + +/*! + * This function gets the number of data words in the Transmit FIFO. + * + * @param module the module number + * @param fifo the fifo + * @return This function returns the number of words in the Tx FIFO. + */ +unsigned char ssi_tx_fifo_counter(ssi_mod module, fifo_nb fifo); + +/*! + * This function controls the threshold at which the TFEx flag will be set. + * + * @param module the module number + * @param fifo the fifo to enable + * @param watermark the watermark + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_fifo_empty_watermark(ssi_mod module, fifo_nb fifo, + unsigned char watermark); + +/*! + * This function enables the Transmit FIFO. + * + * @param module the module number + * @param fifo the fifo to enable + * @param enable the state of the FIFO, enabled or disabled + */ +void ssi_tx_fifo_enable(ssi_mod module, fifo_nb fifo, bool enable); + +/*! + * This function flushes the Transmit FIFOs. + * + * @param module the module number + */ +void ssi_tx_flush_fifo(ssi_mod module); + +/*! + * This function controls the direction of the Frame Sync signal for the transmit section. + * + * @param module the module number + * @param direction the Frame Sync signal direction + */ +void ssi_tx_frame_direction(ssi_mod module, ssi_tx_rx_direction direction); + +/*! + * This function configures the Transmit frame rate divider. + * + * @param module the module number + * @param ratio the divide ratio from 1 to 32 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_frame_rate(ssi_mod module, unsigned char ratio); + +/*! + * This function controls the Frame Sync active polarity for the transmit section. + * + * @param module the module number + * @param active the Frame Sync active polarity + */ +void ssi_tx_frame_sync_active(ssi_mod module, + ssi_tx_rx_frame_sync_active active); + +/*! + * This function controls the Frame Sync length (one word or one bit long) for the transmit section. + * + * @param module the module number + * @param length the Frame Sync length + */ +void ssi_tx_frame_sync_length(ssi_mod module, + ssi_tx_rx_frame_sync_length length); + +/*! + * This function configures the time slot(s) to mask for the transmit section. + * + * @param module the module number + * @param mask the mask to indicate the time slot(s) masked + */ +void ssi_tx_mask_time_slot(ssi_mod module, unsigned int mask); + +/*! + * This function configures the Prescale divider for the transmit section. + * + * @param module the module number + * @param divider the divide ratio from 1 to 256 + * @return This function returns the result of the operation (0 if successful, -1 otherwise). + */ +int ssi_tx_prescaler_modulus(ssi_mod module, unsigned int divider); + +/*! + * This function controls whether the MSB or LSB will be transmited first in a sample. + * + * @param module the module number + * @param direction the shift direction + */ +void ssi_tx_shift_direction(ssi_mod module, + ssi_tx_rx_shift_direction direction); + +/*! + * This function configures the Transmit word length. + * + * @param module the module number + * @param length the word length + */ +void ssi_tx_word_length(ssi_mod module, ssi_word_length length); + +#endif /* __MXC_SSI_H__ */ diff --git a/drivers/mxc/ssi/ssi_types.h b/drivers/mxc/ssi/ssi_types.h new file mode 100644 index 000000000000..5d8a6b845b6f --- /dev/null +++ b/drivers/mxc/ssi/ssi_types.h @@ -0,0 +1,367 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file ssi_types.h + * @brief This header file contains SSI types. + * + * @ingroup SSI + */ + +#ifndef __MXC_SSI_TYPES_H__ +#define __MXC_SSI_TYPES_H__ + +/*! + * This enumeration describes the FIFO number. + */ +typedef enum { + /*! + * FIFO 0 + */ + ssi_fifo_0 = 0, + /*! + * FIFO 1 + */ + ssi_fifo_1 = 1 +} fifo_nb; + +/*! + * This enumeration describes the clock idle state. + */ +typedef enum { + /*! + * Clock idle state is 1 + */ + clock_idle_state_1 = 0, + /*! + * Clock idle state is 0 + */ + clock_idle_state_0 = 1 +} idle_state; + +/*! + * This enumeration describes I2S mode. + */ +typedef enum { + /*! + * Normal mode + */ + i2s_normal = 0, + /*! + * Master mode + */ + i2s_master = 1, + /*! + * Slave mode + */ + i2s_slave = 2 +} mode_i2s; + +/*! + * This enumeration describes index for both SSI1 and SSI2 modules. + */ +typedef enum { + /*! + * SSI1 index + */ + SSI1 = 0, + /*! + * SSI2 index not present on MXC 91221 and MXC91311 + */ + SSI2 = 1 +} ssi_mod; + +/*! + * This enumeration describes the status/enable bits for interrupt source of the SSI module. + */ +typedef enum { + /*! + * SSI Transmit FIFO 0 empty bit + */ + ssi_tx_fifo_0_empty = 0x00000001, + /*! + * SSI Transmit FIFO 1 empty bit + */ + ssi_tx_fifo_1_empty = 0x00000002, + /*! + * SSI Receive FIFO 0 full bit + */ + ssi_rx_fifo_0_full = 0x00000004, + /*! + * SSI Receive FIFO 1 full bit + */ + ssi_rx_fifo_1_full = 0x00000008, + /*! + * SSI Receive Last Time Slot bit + */ + ssi_rls = 0x00000010, + /*! + * SSI Transmit Last Time Slot bit + */ + ssi_tls = 0x00000020, + /*! + * SSI Receive Frame Sync bit + */ + ssi_rfs = 0x00000040, + /*! + * SSI Transmit Frame Sync bit + */ + ssi_tfs = 0x00000080, + /*! + * SSI Transmitter underrun 0 bit + */ + ssi_transmitter_underrun_0 = 0x00000100, + /*! + * SSI Transmitter underrun 1 bit + */ + ssi_transmitter_underrun_1 = 0x00000200, + /*! + * SSI Receiver overrun 0 bit + */ + ssi_receiver_overrun_0 = 0x00000400, + /*! + * SSI Receiver overrun 1 bit + */ + ssi_receiver_overrun_1 = 0x00000800, + /*! + * SSI Transmit Data register empty 0 bit + */ + ssi_tx_data_reg_empty_0 = 0x00001000, + /*! + * SSI Transmit Data register empty 1 bit + */ + ssi_tx_data_reg_empty_1 = 0x00002000, + + /*! + * SSI Receive Data Ready 0 bit + */ + ssi_rx_data_ready_0 = 0x00004000, + /*! + * SSI Receive Data Ready 1 bit + */ + ssi_rx_data_ready_1 = 0x00008000, + /*! + * SSI Receive tag updated bit + */ + ssi_rx_tag_updated = 0x00010000, + /*! + * SSI Command data register updated bit + */ + ssi_cmd_data_reg_updated = 0x00020000, + /*! + * SSI Command address register updated bit + */ + ssi_cmd_address_reg_updated = 0x00040000, + /*! + * SSI Transmit interrupt enable bit + */ + ssi_tx_interrupt_enable = 0x00080000, + /*! + * SSI Transmit DMA enable bit + */ + ssi_tx_dma_interrupt_enable = 0x00100000, + /*! + * SSI Receive interrupt enable bit + */ + ssi_rx_interrupt_enable = 0x00200000, + /*! + * SSI Receive DMA enable bit + */ + ssi_rx_dma_interrupt_enable = 0x00400000, + /*! + * SSI Tx frame complete enable bit on MXC91221 & MXC91311 only + */ + ssi_tx_frame_complete = 0x00800000, + /*! + * SSI Rx frame complete on MXC91221 & MXC91311 only + */ + ssi_rx_frame_complete = 0x001000000 +} ssi_status_enable_mask; + +/*! + * This enumeration describes the clock edge to clock in or clock out data. + */ +typedef enum { + /*! + * Clock on rising edge + */ + ssi_clock_on_rising_edge = 0, + /*! + * Clock on falling edge + */ + ssi_clock_on_falling_edge = 1 +} ssi_tx_rx_clock_polarity; + +/*! + * This enumeration describes the clock direction. + */ +typedef enum { + /*! + * Clock is external + */ + ssi_tx_rx_externally = 0, + /*! + * Clock is generated internally + */ + ssi_tx_rx_internally = 1 +} ssi_tx_rx_direction; + +/*! + * This enumeration describes the early frame sync behavior. + */ +typedef enum { + /*! + * Frame Sync starts on the first data bit + */ + ssi_frame_sync_first_bit = 0, + /*! + * Frame Sync starts one bit before the first data bit + */ + ssi_frame_sync_one_bit_before = 1 +} ssi_tx_rx_early_frame_sync; + +/*! + * This enumeration describes the Frame Sync active value. + */ +typedef enum { + /*! + * Frame Sync is active when high + */ + ssi_frame_sync_active_high = 0, + /*! + * Frame Sync is active when low + */ + ssi_frame_sync_active_low = 1 +} ssi_tx_rx_frame_sync_active; + +/*! + * This enumeration describes the Frame Sync active length. + */ +typedef enum { + /*! + * Frame Sync is active when high + */ + ssi_frame_sync_one_word = 0, + /*! + * Frame Sync is active when low + */ + ssi_frame_sync_one_bit = 1 +} ssi_tx_rx_frame_sync_length; + +/*! + * This enumeration describes the Tx/Rx frame shift direction. + */ +typedef enum { + /*! + * MSB first + */ + ssi_msb_first = 0, + /*! + * LSB first + */ + ssi_lsb_first = 1 +} ssi_tx_rx_shift_direction; + +/*! + * This enumeration describes the wait state number. + */ +typedef enum { + /*! + * 0 wait state + */ + ssi_waitstates0 = 0x0, + /*! + * 1 wait state + */ + ssi_waitstates1 = 0x1, + /*! + * 2 wait states + */ + ssi_waitstates2 = 0x2, + /*! + * 3 wait states + */ + ssi_waitstates3 = 0x3 +} ssi_wait_states; + +/*! + * This enumeration describes the word length. + */ +typedef enum { + /*! + * 2 bits long + */ + ssi_2_bits = 0x0, + /*! + * 4 bits long + */ + ssi_4_bits = 0x1, + /*! + * 6 bits long + */ + ssi_6_bits = 0x2, + /*! + * 8 bits long + */ + ssi_8_bits = 0x3, + /*! + * 10 bits long + */ + ssi_10_bits = 0x4, + /*! + * 12 bits long + */ + ssi_12_bits = 0x5, + /*! + * 14 bits long + */ + ssi_14_bits = 0x6, + /*! + * 16 bits long + */ + ssi_16_bits = 0x7, + /*! + * 18 bits long + */ + ssi_18_bits = 0x8, + /*! + * 20 bits long + */ + ssi_20_bits = 0x9, + /*! + * 22 bits long + */ + ssi_22_bits = 0xA, + /*! + * 24 bits long + */ + ssi_24_bits = 0xB, + /*! + * 26 bits long + */ + ssi_26_bits = 0xC, + /*! + * 28 bits long + */ + ssi_28_bits = 0xD, + /*! + * 30 bits long + */ + ssi_30_bits = 0xE, + /*! + * 32 bits long + */ + ssi_32_bits = 0xF +} ssi_word_length; + +#endif /* __MXC_SSI_TYPES_H__ */ diff --git a/drivers/mxc/vpu/Kconfig b/drivers/mxc/vpu/Kconfig new file mode 100644 index 000000000000..37e55e03d2f2 --- /dev/null +++ b/drivers/mxc/vpu/Kconfig @@ -0,0 +1,30 @@ +# +# Codec configuration +# + +menu "MXC VPU(Video Processing Unit) support" + +config MXC_VPU + tristate "Support for MXC VPU(Video Processing Unit)" + depends on (ARCH_MX3 || ARCH_MX27 || ARCH_MX37 || ARCH_MX5) + default y + ---help--- + The VPU codec device provides codec function for H.264/MPEG4/H.263, + as well as MPEG2/VC-1/DivX on some platforms. + +config MXC_VPU_IRAM + tristate "Use IRAM as temporary buffer for VPU to enhance performace" + depends on (ARCH_MX37 || ARCH_MX5) + default y + ---help--- + The VPU can use internal RAM as temporary buffer to save external + memroy bandwith, thus to enhance video performance. + +config MXC_VPU_DEBUG + bool "MXC VPU debugging" + depends on MXC_VPU != n + help + This is an option for the developers; most people should + say N here. This enables MXC VPU driver debugging. + +endmenu diff --git a/drivers/mxc/vpu/Makefile b/drivers/mxc/vpu/Makefile new file mode 100644 index 000000000000..88e8f2c084a0 --- /dev/null +++ b/drivers/mxc/vpu/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the VPU drivers. +# + +obj-$(CONFIG_MXC_VPU) += vpu.o +vpu-objs := mxc_vpu.o mxc_vl2cc.o + +ifeq ($(CONFIG_MXC_VPU_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif diff --git a/drivers/mxc/vpu/mxc_vl2cc.c b/drivers/mxc/vpu/mxc_vl2cc.c new file mode 100644 index 000000000000..c077ac1c2639 --- /dev/null +++ b/drivers/mxc/vpu/mxc_vl2cc.c @@ -0,0 +1,124 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_vl2cc.c + * + * @brief VL2CC initialization and flush operation implementation + * + * @ingroup VL2CC + */ + +#include +#include +#include +#include +#include +#include + +#define VL2CC_CTRL_OFFSET (0x100) +#define VL2CC_AUXCTRL_OFFSET (0x104) +#define VL2CC_INVWAY_OFFSET (0x77C) +#define VL2CC_CLEANWAY_OFFSET (0x7BC) + +/*! VL2CC clock handle. */ +static struct clk *vl2cc_clk; +static u32 *vl2cc_base; + +/*! + * Initialization function of VL2CC. Remap the VL2CC base address. + * + * @return status 0 success. + */ +int vl2cc_init(u32 vl2cc_hw_base) +{ + vl2cc_base = ioremap(vl2cc_hw_base, SZ_8K - 1); + if (vl2cc_base == NULL) { + printk(KERN_INFO "vl2cc: Unable to ioremap\n"); + return -ENOMEM; + } + + vl2cc_clk = clk_get(NULL, "vl2cc_clk"); + if (IS_ERR(vl2cc_clk)) { + printk(KERN_INFO "vl2cc: Unable to get clock\n"); + iounmap(vl2cc_base); + return -EIO; + } + + printk(KERN_INFO "VL2CC initialized\n"); + return 0; +} + +/*! + * Enable VL2CC hardware + */ +void vl2cc_enable(void) +{ + volatile u32 reg; + + clk_enable(vl2cc_clk); + + /* Disable VL2CC */ + reg = __raw_readl(vl2cc_base + VL2CC_CTRL_OFFSET); + reg &= 0xFFFFFFFE; + __raw_writel(reg, vl2cc_base + VL2CC_CTRL_OFFSET); + + /* Set the latency for data RAM reads, data RAM writes, tag RAM and + * dirty RAM to 1 cycle - write 0x0 to AUX CTRL [11:0] and also + * configure the number of ways to 8 - write 8 to AUX CTRL [16:13] + */ + reg = __raw_readl(vl2cc_base + VL2CC_AUXCTRL_OFFSET); + reg &= 0xFFFE1000; /* Clear [16:13] too */ + reg |= (0x8 << 13); /* [16:13] = 8; */ + __raw_writel(reg, vl2cc_base + VL2CC_AUXCTRL_OFFSET); + + /* Invalidate the VL2CC ways - write 0xff to INV BY WAY and poll the + * register until its value is 0x0 + */ + __raw_writel(0xff, vl2cc_base + VL2CC_INVWAY_OFFSET); + while (__raw_readl(vl2cc_base + VL2CC_INVWAY_OFFSET) != 0x0) + ; + + /* Enable VL2CC */ + reg = __raw_readl(vl2cc_base + VL2CC_CTRL_OFFSET); + reg |= 0x1; + __raw_writel(reg, vl2cc_base + VL2CC_CTRL_OFFSET); +} + +/*! + * Flush VL2CC + */ +void vl2cc_flush(void) +{ + __raw_writel(0xff, vl2cc_base + VL2CC_CLEANWAY_OFFSET); + while (__raw_readl(vl2cc_base + VL2CC_CLEANWAY_OFFSET) != 0x0) + ; +} + +/*! + * Disable VL2CC + */ +void vl2cc_disable(void) +{ + __raw_writel(0, vl2cc_base + VL2CC_CTRL_OFFSET); + clk_disable(vl2cc_clk); +} + +/*! + * Cleanup VL2CC + */ +void vl2cc_cleanup(void) +{ + clk_put(vl2cc_clk); + iounmap(vl2cc_base); +} diff --git a/drivers/mxc/vpu/mxc_vpu.c b/drivers/mxc/vpu/mxc_vpu.c new file mode 100644 index 000000000000..67b9ebbdca42 --- /dev/null +++ b/drivers/mxc/vpu/mxc_vpu.c @@ -0,0 +1,881 @@ +/* + * Copyright 2006-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_vpu.c + * + * @brief VPU system initialization and file operation implementation + * + * @ingroup VPU + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +struct vpu_priv { + struct fasync_struct *async_queue; + struct work_struct work; + struct workqueue_struct *workqueue; +}; + +/* To track the allocated memory buffer */ +typedef struct memalloc_record { + struct list_head list; + struct vpu_mem_desc mem; +} memalloc_record; + +struct iram_setting { + u32 start; + u32 end; +}; + +static DEFINE_SPINLOCK(vpu_lock); +static LIST_HEAD(head); + +static int vpu_major; +static int vpu_clk_usercount; +static struct class *vpu_class; +static struct vpu_priv vpu_data; +static u8 open_count; +static struct clk *vpu_clk; +static struct vpu_mem_desc bitwork_mem = { 0 }; +static struct vpu_mem_desc pic_para_mem = { 0 }; +static struct vpu_mem_desc user_data_mem = { 0 }; +static struct vpu_mem_desc share_mem = { 0 }; + +static void __iomem *vpu_base; +static int vpu_irq; +static u32 phy_vpu_base_addr; +static struct mxc_vpu_platform_data *vpu_plat; + +/* IRAM setting */ +static struct iram_setting iram; + +/* implement the blocking ioctl */ +static int codec_done; +static wait_queue_head_t vpu_queue; + +static u32 workctrl_regsave[6]; +static u32 rd_ptr_regsave[4]; +static u32 wr_ptr_regsave[4]; +static u32 dis_flag_regsave[4]; + +#define READ_REG(x) __raw_readl(vpu_base + x) +#define WRITE_REG(val, x) __raw_writel(val, vpu_base + x) +#define SAVE_WORK_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(workctrl_regsave)/2; i++) \ + workctrl_regsave[i] = READ_REG(BIT_WORK_CTRL_BUF_REG(i));\ +} while (0) +#define RESTORE_WORK_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(workctrl_regsave)/2; i++) \ + WRITE_REG(workctrl_regsave[i], BIT_WORK_CTRL_BUF_REG(i));\ +} while (0) +#define SAVE_CTRL_REGS do { \ + int i; \ + for (i = ARRAY_SIZE(workctrl_regsave)/2; \ + i < ARRAY_SIZE(workctrl_regsave); i++) \ + workctrl_regsave[i] = READ_REG(BIT_WORK_CTRL_BUF_REG(i));\ +} while (0) +#define RESTORE_CTRL_REGS do { \ + int i; \ + for (i = ARRAY_SIZE(workctrl_regsave)/2; \ + i < ARRAY_SIZE(workctrl_regsave); i++) \ + WRITE_REG(workctrl_regsave[i], BIT_WORK_CTRL_BUF_REG(i));\ +} while (0) +#define SAVE_RDWR_PTR_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(rd_ptr_regsave); i++) \ + rd_ptr_regsave[i] = READ_REG(BIT_RD_PTR_REG(i)); \ + for (i = 0; i < ARRAY_SIZE(wr_ptr_regsave); i++) \ + wr_ptr_regsave[i] = READ_REG(BIT_WR_PTR_REG(i)); \ +} while (0) +#define RESTORE_RDWR_PTR_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(rd_ptr_regsave); i++) \ + WRITE_REG(rd_ptr_regsave[i], BIT_RD_PTR_REG(i)); \ + for (i = 0; i < ARRAY_SIZE(wr_ptr_regsave); i++) \ + WRITE_REG(wr_ptr_regsave[i], BIT_WR_PTR_REG(i)); \ +} while (0) +#define SAVE_DIS_FLAG_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(dis_flag_regsave); i++) \ + dis_flag_regsave[i] = READ_REG(BIT_FRM_DIS_FLG_REG(i)); \ +} while (0) +#define RESTORE_DIS_FLAG_REGS do { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(dis_flag_regsave); i++) \ + WRITE_REG(dis_flag_regsave[i], BIT_FRM_DIS_FLG_REG(i)); \ +} while (0) + +/*! + * Private function to alloc dma buffer + * @return status 0 success. + */ +static int vpu_alloc_dma_buffer(struct vpu_mem_desc *mem) +{ + mem->cpu_addr = (unsigned long) + dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size), + (dma_addr_t *) (&mem->phy_addr), + GFP_DMA | GFP_KERNEL); + pr_debug("[ALLOC] mem alloc cpu_addr = 0x%x\n", mem->cpu_addr); + if ((void *)(mem->cpu_addr) == NULL) { + printk(KERN_ERR "Physical memory allocation error!\n"); + return -1; + } + return 0; +} + +/*! + * Private function to free dma buffer + */ +static void vpu_free_dma_buffer(struct vpu_mem_desc *mem) +{ + if (mem->cpu_addr != 0) { + dma_free_coherent(0, PAGE_ALIGN(mem->size), + (void *)mem->cpu_addr, mem->phy_addr); + } +} + +/*! + * Private function to free buffers + * @return status 0 success. + */ +static int vpu_free_buffers(void) +{ + struct memalloc_record *rec, *n; + struct vpu_mem_desc mem; + + list_for_each_entry_safe(rec, n, &head, list) { + mem = rec->mem; + if (mem.cpu_addr != 0) { + vpu_free_dma_buffer(&mem); + pr_debug("[FREE] freed paddr=0x%08X\n", mem.phy_addr); + /* delete from list */ + list_del(&rec->list); + kfree(rec); + } + } + + return 0; +} + +static inline void vpu_worker_callback(struct work_struct *w) +{ + struct vpu_priv *dev = container_of(w, struct vpu_priv, + work); + + if (dev->async_queue) + kill_fasync(&dev->async_queue, SIGIO, POLL_IN); + + codec_done = 1; + wake_up_interruptible(&vpu_queue); + + /* + * Clock is gated on when dec/enc started, gate it off when + * interrupt is received. + */ + clk_disable(vpu_clk); +} + +/*! + * @brief vpu interrupt handler + */ +static irqreturn_t vpu_irq_handler(int irq, void *dev_id) +{ + struct vpu_priv *dev = dev_id; + + READ_REG(BIT_INT_STATUS); + WRITE_REG(0x1, BIT_INT_CLEAR); + + queue_work(dev->workqueue, &dev->work); + + return IRQ_HANDLED; +} + +/*! + * @brief open function for vpu file operation + * + * @return 0 on success or negative error code on error + */ +static int vpu_open(struct inode *inode, struct file *filp) +{ + spin_lock(&vpu_lock); + if ((open_count++ == 0) && cpu_is_mx32()) + vl2cc_enable(); + filp->private_data = (void *)(&vpu_data); + spin_unlock(&vpu_lock); + return 0; +} + +/*! + * @brief IO ctrl function for vpu file operation + * @param cmd IO ctrl command + * @return 0 on success or negative error code on error + */ +static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, + u_long arg) +{ + int ret = 0; + + switch (cmd) { + case VPU_IOC_PHYMEM_ALLOC: + { + struct memalloc_record *rec; + + rec = kzalloc(sizeof(*rec), GFP_KERNEL); + if (!rec) + return -ENOMEM; + + ret = copy_from_user(&(rec->mem), + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc)); + if (ret) { + kfree(rec); + return -EFAULT; + } + + pr_debug("[ALLOC] mem alloc size = 0x%x\n", + rec->mem.size); + + ret = vpu_alloc_dma_buffer(&(rec->mem)); + if (ret == -1) { + kfree(rec); + printk(KERN_ERR + "Physical memory allocation error!\n"); + break; + } + ret = copy_to_user((void __user *)arg, &(rec->mem), + sizeof(struct vpu_mem_desc)); + if (ret) { + kfree(rec); + ret = -EFAULT; + break; + } + + spin_lock(&vpu_lock); + list_add(&rec->list, &head); + spin_unlock(&vpu_lock); + + break; + } + case VPU_IOC_PHYMEM_FREE: + { + struct memalloc_record *rec, *n; + struct vpu_mem_desc vpu_mem; + + ret = copy_from_user(&vpu_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc)); + if (ret) + return -EACCES; + + pr_debug("[FREE] mem freed cpu_addr = 0x%x\n", + vpu_mem.cpu_addr); + if ((void *)vpu_mem.cpu_addr != NULL) { + vpu_free_dma_buffer(&vpu_mem); + } + + spin_lock(&vpu_lock); + list_for_each_entry_safe(rec, n, &head, list) { + if (rec->mem.cpu_addr == vpu_mem.cpu_addr) { + /* delete from list */ + list_del(&rec->list); + kfree(rec); + break; + } + } + spin_unlock(&vpu_lock); + + break; + } + case VPU_IOC_WAIT4INT: + { + u_long timeout = (u_long) arg; + if (!wait_event_interruptible_timeout + (vpu_queue, codec_done != 0, + msecs_to_jiffies(timeout))) { + printk(KERN_WARNING "VPU blocking: timeout.\n"); + ret = -ETIME; + } else if (signal_pending(current)) { + printk(KERN_WARNING + "VPU interrupt received.\n"); + ret = -ERESTARTSYS; + } else + codec_done = 0; + break; + } + case VPU_IOC_VL2CC_FLUSH: + if (cpu_is_mx32()) { + vl2cc_flush(); + } + break; + case VPU_IOC_IRAM_SETTING: + { + ret = copy_to_user((void __user *)arg, &iram, + sizeof(struct iram_setting)); + if (ret) + ret = -EFAULT; + + break; + } + case VPU_IOC_CLKGATE_SETTING: + { + u32 clkgate_en; + + if (get_user(clkgate_en, (u32 __user *) arg)) + return -EFAULT; + + if (clkgate_en) { + clk_enable(vpu_clk); + } else { + clk_disable(vpu_clk); + } + + break; + } + case VPU_IOC_GET_SHARE_MEM: + { + spin_lock(&vpu_lock); + if (share_mem.cpu_addr != 0) { + ret = copy_to_user((void __user *)arg, + &share_mem, + sizeof(struct vpu_mem_desc)); + spin_unlock(&vpu_lock); + break; + } else { + if (copy_from_user(&share_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc))) { + spin_unlock(&vpu_lock); + return -EFAULT; + } + if (vpu_alloc_dma_buffer(&share_mem) == -1) + ret = -EFAULT; + else { + if (copy_to_user((void __user *)arg, + &share_mem, + sizeof(struct + vpu_mem_desc))) + ret = -EFAULT; + } + } + spin_unlock(&vpu_lock); + break; + } + case VPU_IOC_GET_WORK_ADDR: + { + if (bitwork_mem.cpu_addr != 0) { + ret = + copy_to_user((void __user *)arg, + &bitwork_mem, + sizeof(struct vpu_mem_desc)); + break; + } else { + if (copy_from_user(&bitwork_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc))) + return -EFAULT; + + if (vpu_alloc_dma_buffer(&bitwork_mem) == -1) + ret = -EFAULT; + else if (copy_to_user((void __user *)arg, + &bitwork_mem, + sizeof(struct + vpu_mem_desc))) + ret = -EFAULT; + } + break; + } + case VPU_IOC_GET_PIC_PARA_ADDR: + { + if (pic_para_mem.cpu_addr != 0) { + ret = + copy_to_user((void __user *)arg, + &pic_para_mem, + sizeof(struct vpu_mem_desc)); + break; + } else { + if (copy_from_user(&pic_para_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc))) + return -EFAULT; + + if (vpu_alloc_dma_buffer(&pic_para_mem) == -1) + ret = -EFAULT; + else if (copy_to_user((void __user *)arg, + &pic_para_mem, + sizeof(struct + vpu_mem_desc))) + ret = -EFAULT; + } + break; + } + case VPU_IOC_GET_USER_DATA_ADDR: + { + if (user_data_mem.cpu_addr != 0) { + ret = + copy_to_user((void __user *)arg, + &user_data_mem, + sizeof(struct vpu_mem_desc)); + break; + } else { + if (copy_from_user(&user_data_mem, + (struct vpu_mem_desc *)arg, + sizeof(struct vpu_mem_desc))) + return -EFAULT; + + if (vpu_alloc_dma_buffer(&user_data_mem) == -1) + ret = -EFAULT; + else if (copy_to_user((void __user *)arg, + &user_data_mem, + sizeof(struct + vpu_mem_desc))) + ret = -EFAULT; + } + break; + } + case VPU_IOC_SYS_SW_RESET: + { + if (vpu_plat->reset) + vpu_plat->reset(); + + break; + } + case VPU_IOC_REG_DUMP: + break; + case VPU_IOC_PHYMEM_DUMP: + break; + default: + { + printk(KERN_ERR "No such IOCTL, cmd is %d\n", cmd); + break; + } + } + return ret; +} + +/*! + * @brief Release function for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_release(struct inode *inode, struct file *filp) +{ + spin_lock(&vpu_lock); + if (open_count > 0 && !(--open_count)) { + vpu_free_buffers(); + + if (cpu_is_mx32()) + vl2cc_disable(); + + /* Free shared memory when vpu device is idle */ + vpu_free_dma_buffer(&share_mem); + share_mem.cpu_addr = 0; + } + spin_unlock(&vpu_lock); + + return 0; +} + +/*! + * @brief fasync function for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_fasync(int fd, struct file *filp, int mode) +{ + struct vpu_priv *dev = (struct vpu_priv *)filp->private_data; + return fasync_helper(fd, filp, mode, &dev->async_queue); +} + +/*! + * @brief memory map function of harware registers for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_map_hwregs(struct file *fp, struct vm_area_struct *vm) +{ + unsigned long pfn; + + vm->vm_flags |= VM_IO | VM_RESERVED; + vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot); + pfn = phy_vpu_base_addr >> PAGE_SHIFT; + pr_debug("size=0x%x, page no.=0x%x\n", + (int)(vm->vm_end - vm->vm_start), (int)pfn); + return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end - vm->vm_start, + vm->vm_page_prot) ? -EAGAIN : 0; +} + +/*! + * @brief memory map function of memory for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_map_mem(struct file *fp, struct vm_area_struct *vm) +{ + int request_size; + request_size = vm->vm_end - vm->vm_start; + + pr_debug(" start=0x%x, pgoff=0x%x, size=0x%x\n", + (unsigned int)(vm->vm_start), (unsigned int)(vm->vm_pgoff), + request_size); + + vm->vm_flags |= VM_IO | VM_RESERVED; + vm->vm_page_prot = pgprot_writecombine(vm->vm_page_prot); + + return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, + request_size, vm->vm_page_prot) ? -EAGAIN : 0; + +} + +/*! + * @brief memory map interface for vpu file operation + * @return 0 on success or negative error code on error + */ +static int vpu_mmap(struct file *fp, struct vm_area_struct *vm) +{ + if (vm->vm_pgoff) + return vpu_map_mem(fp, vm); + else + return vpu_map_hwregs(fp, vm); +} + +struct file_operations vpu_fops = { + .owner = THIS_MODULE, + .open = vpu_open, + .ioctl = vpu_ioctl, + .release = vpu_release, + .fasync = vpu_fasync, + .mmap = vpu_mmap, +}; + +/*! + * This function is called by the driver framework to initialize the vpu device. + * @param dev The device structure for the vpu passed in by the framework. + * @return 0 on success or negative error code on error + */ +static int vpu_dev_probe(struct platform_device *pdev) +{ + int err = 0; + struct device *temp_class; + struct resource *res; + unsigned long addr = 0; + + vpu_plat = pdev->dev.platform_data; + + if (VPU_IRAM_SIZE) + iram_alloc(VPU_IRAM_SIZE, &addr); + if (addr == 0) + iram.start = iram.end = 0; + else { + iram.start = addr; + iram.end = addr + VPU_IRAM_SIZE - 1; + } + + if (cpu_is_mx32()) { + err = vl2cc_init(iram.start); + if (err != 0) + return err; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk(KERN_ERR "vpu: unable to get vpu base addr\n"); + return -ENODEV; + } + phy_vpu_base_addr = res->start; + vpu_base = ioremap(res->start, res->end - res->start); + + vpu_major = register_chrdev(vpu_major, "mxc_vpu", &vpu_fops); + if (vpu_major < 0) { + printk(KERN_ERR "vpu: unable to get a major for VPU\n"); + err = -EBUSY; + goto error; + } + + vpu_class = class_create(THIS_MODULE, "mxc_vpu"); + if (IS_ERR(vpu_class)) { + err = PTR_ERR(vpu_class); + goto err_out_chrdev; + } + + temp_class = device_create(vpu_class, NULL, MKDEV(vpu_major, 0), + NULL, "mxc_vpu"); + if (IS_ERR(temp_class)) { + err = PTR_ERR(temp_class); + goto err_out_class; + } + + vpu_clk = clk_get(&pdev->dev, "vpu_clk"); + if (IS_ERR(vpu_clk)) { + err = -ENOENT; + goto err_out_class; + } + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + printk(KERN_ERR "vpu: unable to get vpu interrupt\n"); + err = -ENXIO; + goto err_out_class; + } + vpu_irq = res->start; + + err = request_irq(vpu_irq, vpu_irq_handler, 0, "VPU_CODEC_IRQ", + (void *)(&vpu_data)); + if (err) + goto err_out_class; + + vpu_data.workqueue = create_workqueue("vpu_wq"); + INIT_WORK(&vpu_data.work, vpu_worker_callback); + printk(KERN_INFO "VPU initialized\n"); + goto out; + + err_out_class: + device_destroy(vpu_class, MKDEV(vpu_major, 0)); + class_destroy(vpu_class); + err_out_chrdev: + unregister_chrdev(vpu_major, "mxc_vpu"); + error: + iounmap(vpu_base); + if (cpu_is_mx32()) { + vl2cc_cleanup(); + } + out: + return err; +} + +static int vpu_dev_remove(struct platform_device *pdev) +{ + free_irq(vpu_irq, &vpu_data); + cancel_work_sync(&vpu_data.work); + flush_workqueue(vpu_data.workqueue); + destroy_workqueue(vpu_data.workqueue); + + iounmap(vpu_base); + if (VPU_IRAM_SIZE) + iram_free(iram.start, VPU_IRAM_SIZE); + + return 0; +} + +#ifdef CONFIG_PM +static int vpu_suspend(struct platform_device *pdev, pm_message_t state) +{ + int i; + unsigned long timeout; + + /* Wait for vpu go to idle state, suspect vpu cannot be changed + to idle state after about 1 sec */ + if (open_count > 0) { + timeout = jiffies + HZ; + clk_enable(vpu_clk); + while (READ_REG(BIT_BUSY_FLAG)) { + msleep(1); + if (time_after(jiffies, timeout)) + goto out; + } + clk_disable(vpu_clk); + } + + /* Make sure clock is disabled before suspend */ + vpu_clk_usercount = clk_get_usecount(vpu_clk); + for (i = 0; i < vpu_clk_usercount; i++) + clk_disable(vpu_clk); + + if (!cpu_is_mx53()) { + clk_enable(vpu_clk); + if (bitwork_mem.cpu_addr != 0) { + SAVE_WORK_REGS; + SAVE_CTRL_REGS; + SAVE_RDWR_PTR_REGS; + SAVE_DIS_FLAG_REGS; + + WRITE_REG(0x1, BIT_BUSY_FLAG); + WRITE_REG(VPU_SLEEP_REG_VALUE, BIT_RUN_COMMAND); + while (READ_REG(BIT_BUSY_FLAG)) + ; + } + clk_disable(vpu_clk); + } + + if (cpu_is_mx37() || cpu_is_mx51()) + mxc_pg_enable(pdev); + + return 0; + +out: + clk_disable(vpu_clk); + return -EAGAIN; + +} + +static int vpu_resume(struct platform_device *pdev) +{ + int i; + + if (cpu_is_mx37() || cpu_is_mx51()) + mxc_pg_disable(pdev); + + if (cpu_is_mx53()) + goto recover_clk; + + clk_enable(vpu_clk); + if (bitwork_mem.cpu_addr != 0) { + u32 *p = (u32 *) bitwork_mem.cpu_addr; + u32 data; + u16 data_hi; + u16 data_lo; + + RESTORE_WORK_REGS; + + WRITE_REG(0x0, BIT_RESET_CTRL); + WRITE_REG(0x0, BIT_CODE_RUN); + + /* + * Re-load boot code, from the codebuffer in external RAM. + * Thankfully, we only need 4096 bytes, same for all platforms. + */ + if (cpu_is_mx51()) { + for (i = 0; i < 2048; i += 4) { + data = p[(i / 2) + 1]; + data_hi = (data >> 16) & 0xFFFF; + data_lo = data & 0xFFFF; + WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN); + WRITE_REG(((i + 1) << 16) | data_lo, + BIT_CODE_DOWN); + + data = p[i / 2]; + data_hi = (data >> 16) & 0xFFFF; + data_lo = data & 0xFFFF; + WRITE_REG(((i + 2) << 16) | data_hi, + BIT_CODE_DOWN); + WRITE_REG(((i + 3) << 16) | data_lo, + BIT_CODE_DOWN); + } + } else { + for (i = 0; i < 2048; i += 2) { + if (cpu_is_mx37()) + data = swab32(p[i / 2]); + else + data = p[i / 2]; + data_hi = (data >> 16) & 0xFFFF; + data_lo = data & 0xFFFF; + + WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN); + WRITE_REG(((i + 1) << 16) | data_lo, + BIT_CODE_DOWN); + } + } + + RESTORE_CTRL_REGS; + + WRITE_REG(BITVAL_PIC_RUN, BIT_INT_ENABLE); + + WRITE_REG(0x1, BIT_BUSY_FLAG); + WRITE_REG(0x1, BIT_CODE_RUN); + while (READ_REG(BIT_BUSY_FLAG)) + ; + + RESTORE_RDWR_PTR_REGS; + RESTORE_DIS_FLAG_REGS; + + WRITE_REG(0x1, BIT_BUSY_FLAG); + WRITE_REG(VPU_WAKE_REG_VALUE, BIT_RUN_COMMAND); + while (READ_REG(BIT_BUSY_FLAG)) + ; + } + clk_disable(vpu_clk); + +recover_clk: + /* Recover vpu clock */ + for (i = 0; i < vpu_clk_usercount; i++) + clk_enable(vpu_clk); + + return 0; +} +#else +#define vpu_suspend NULL +#define vpu_resume NULL +#endif /* !CONFIG_PM */ + +/*! Driver definition + * + */ +static struct platform_driver mxcvpu_driver = { + .driver = { + .name = "mxc_vpu", + }, + .probe = vpu_dev_probe, + .remove = vpu_dev_remove, + .suspend = vpu_suspend, + .resume = vpu_resume, +}; + +static int __init vpu_init(void) +{ + int ret = platform_driver_register(&mxcvpu_driver); + + init_waitqueue_head(&vpu_queue); + + return ret; +} + +static void __exit vpu_exit(void) +{ + if (vpu_major > 0) { + device_destroy(vpu_class, MKDEV(vpu_major, 0)); + class_destroy(vpu_class); + unregister_chrdev(vpu_major, "mxc_vpu"); + vpu_major = 0; + } + + if (cpu_is_mx32()) { + vl2cc_cleanup(); + } + + vpu_free_dma_buffer(&bitwork_mem); + vpu_free_dma_buffer(&pic_para_mem); + vpu_free_dma_buffer(&user_data_mem); + + clk_put(vpu_clk); + + platform_driver_unregister(&mxcvpu_driver); + return; +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX/MXC"); +MODULE_LICENSE("GPL"); + +module_init(vpu_init); +module_exit(vpu_exit); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ce2fcdd4ab90..aaae8b17f83a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1908,12 +1908,43 @@ config 68360_ENET config FEC bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)" depends on M523x || M527x || M5272 || M528x || M520x || M532x || \ - MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 + MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 || ARCH_MX28 select PHYLIB help Say Y here if you want to use the built-in 10/100 Fast ethernet controller on some Motorola ColdFire and Freescale i.MX processors. +config FEC_1588 + bool "Enable FEC 1588 timestamping" + depends on FEC + +choice + prompt "IEEE 1588 operation mode" + depends on ARCH_MX5 && FEC_1588 + default OUT_OF_BAND + +config OUT_OF_BAND + bool "out-of-band mode" + help + IEEE 1588 operation mode is out-of-band, in this mode, the Tx and Rx + timestamp will be caputred into special registers. + +config IN_BAND + bool "in-band mode" + help + IEEE 1588 operation mode is in-band, in this mode, the Tx timestamp + will be captured into special retisters, but the Rx timestamp will be + captured into the first eight bytes of received ethernet packet. + +endchoice + +config FEC_L2SWITCH + bool "L2 Switch Ethernet Controller (of ColdFire CPUs)" + depends on ARCH_MX28 && !FEC + help + Say Y here if you want to use the built-in 10/100 Ethernet Switch + Controller on some Motorola ColdFire processors. + config FEC2 bool "Second FEC ethernet controller (on some ColdFire CPUs)" depends on FEC diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 0a0512ae77da..887cc5faddeb 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -120,6 +120,13 @@ obj-$(CONFIG_PCMCIA_PCNET) += 8390.o obj-$(CONFIG_HP100) += hp100.o obj-$(CONFIG_SMC9194) += smc9194.o obj-$(CONFIG_FEC) += fec.o +ifeq ($(CONFIG_ARCH_MX53),y) + obj-$(CONFIG_FEC_1588) += imx_ptp.o +endif +ifeq ($(CONFIG_ARCH_MX28),y) + obj-$(CONFIG_FEC_1588) += fec_1588.o +endif +obj-$(CONFIG_FEC_L2SWITCH) += fec_switch.o obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx.o ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y) obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c index 24df0325090c..ce58bc175f2c 100644 --- a/drivers/net/arm/ixp4xx_eth.c +++ b/drivers/net/arm/ixp4xx_eth.c @@ -771,7 +771,8 @@ static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) if (!netif_running(dev)) return -EINVAL; - return phy_mii_ioctl(port->phydev, if_mii(req), cmd); + + return phy_mii_ioctl(port->phydev, req, cmd); } /* ethtool support */ diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c index ece6128bef14..386d4feec652 100644 --- a/drivers/net/au1000_eth.c +++ b/drivers/net/au1000_eth.c @@ -978,7 +978,7 @@ static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (!aup->phy_dev) return -EINVAL; /* PHY not controllable */ - return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd); + return phy_mii_ioctl(aup->phy_dev, rq, cmd); } static const struct net_device_ops au1000_netdev_ops = { diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index faf5add894d7..0d2c5da08937 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -1496,7 +1496,7 @@ static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (priv->has_phy) { if (!priv->phydev) return -ENODEV; - return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); + return phy_mii_ioctl(priv->phydev, rq, cmd); } else { struct mii_if_info mii; diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig index 2c5227c02fa0..75dba17f107d 100644 --- a/drivers/net/can/Kconfig +++ b/drivers/net/can/Kconfig @@ -89,4 +89,13 @@ config CAN_DEBUG_DEVICES a problem with CAN support and want to see more of what is going on. +config CAN_FLEXCAN + tristate "Freescale FlexCAN" + depends on CAN && (ARCH_MX25 || ARCH_MX35 || ARCH_MX28 || ARCH_MX53) + default y + ---help--- + This select the support of Freescale CAN(FlexCAN). + This driver can also be built as a module. + If unsure, say N. + endmenu diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile index 9047cd066fea..3d7b76ab3147 100644 --- a/drivers/net/can/Makefile +++ b/drivers/net/can/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_CAN_VCAN) += vcan.o +obj-$(CONFIG_CAN_FLEXCAN) += flexcan/ obj-$(CONFIG_CAN_DEV) += can-dev.o can-dev-y := dev.o diff --git a/drivers/net/can/flexcan/Makefile b/drivers/net/can/flexcan/Makefile new file mode 100644 index 000000000000..b2dbb4fb2793 --- /dev/null +++ b/drivers/net/can/flexcan/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_CAN_FLEXCAN) += flexcan.o + +flexcan-y := dev.o drv.o mbm.o diff --git a/drivers/net/can/flexcan/dev.c b/drivers/net/can/flexcan/dev.c new file mode 100644 index 000000000000..05a48d27236e --- /dev/null +++ b/drivers/net/can/flexcan/dev.c @@ -0,0 +1,743 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file dev.c + * + * @brief Driver for Freescale CAN Controller FlexCAN. + * + * @ingroup can + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#ifdef CONFIG_ARCH_MXS +#include +#endif +#include "flexcan.h" + +#define DEFAULT_BITRATE 500000 +#define TIME_SEGMENT_MIN 8 +#define TIME_SEGMENT_MAX 25 +#define TIME_SEGMENT_MID ((TIME_SEGMENT_MIN + TIME_SEGMENT_MAX)/2) + +struct time_segment { + char propseg; + char pseg1; + char pseg2; +}; + +struct time_segment time_segments[] = { + { /* total 8 timequanta */ + 1, 2, 1 + }, + { /* total 9 timequanta */ + 1, 2, 2 + }, + { /* total 10 timequanta */ + 2, 2, 2 + }, + { /* total 11 timequanta */ + 2, 2, 3 + }, + { /* total 12 timequanta */ + 2, 3, 3 + }, + { /* total 13 timequanta */ + 3, 3, 3 + }, + { /* total 14 timequanta */ + 3, 3, 4 + }, + { /* total 15 timequanta */ + 3, 4, 4 + }, + { /* total 16 timequanta */ + 4, 4, 4 + }, + { /* total 17 timequanta */ + 4, 4, 5 + }, + { /* total 18 timequanta */ + 4, 5, 5 + }, + { /* total 19 timequanta */ + 5, 5, 5 + }, + { /* total 20 timequanta */ + 5, 5, 6 + }, + { /* total 21 timequanta */ + 5, 6, 6 + }, + { /* total 22 timequanta */ + 6, 6, 6 + }, + { /* total 23 timequanta */ + 6, 6, 7 + }, + { /* total 24 timequanta */ + 6, 7, 7 + }, + { /* total 25 timequanta */ + 7, 7, 7 + }, +}; + +enum { + FLEXCAN_ATTR_STATE = 0, + FLEXCAN_ATTR_BITRATE, + FLEXCAN_ATTR_BR_PRESDIV, + FLEXCAN_ATTR_BR_RJW, + FLEXCAN_ATTR_BR_PROPSEG, + FLEXCAN_ATTR_BR_PSEG1, + FLEXCAN_ATTR_BR_PSEG2, + FLEXCAN_ATTR_BR_CLKSRC, + FLEXCAN_ATTR_MAXMB, + FLEXCAN_ATTR_XMIT_MAXMB, + FLEXCAN_ATTR_FIFO, + FLEXCAN_ATTR_WAKEUP, + FLEXCAN_ATTR_SRX_DIS, + FLEXCAN_ATTR_WAK_SRC, + FLEXCAN_ATTR_BCC, + FLEXCAN_ATTR_LOCAL_PRIORITY, + FLEXCAN_ATTR_ABORT, + FLEXCAN_ATTR_LOOPBACK, + FLEXCAN_ATTR_SMP, + FLEXCAN_ATTR_BOFF_REC, + FLEXCAN_ATTR_TSYN, + FLEXCAN_ATTR_LISTEN, + FLEXCAN_ATTR_EXTEND_MSG, + FLEXCAN_ATTR_STANDARD_MSG, +#ifdef CONFIG_CAN_DEBUG_DEVICES + FLEXCAN_ATTR_DUMP_REG, + FLEXCAN_ATTR_DUMP_XMIT_MB, + FLEXCAN_ATTR_DUMP_RX_MB, +#endif + FLEXCAN_ATTR_MAX +}; + +static ssize_t flexcan_show_attr(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t flexcan_set_attr(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count); + +static struct device_attribute flexcan_dev_attr[FLEXCAN_ATTR_MAX] = { + [FLEXCAN_ATTR_STATE] = __ATTR(state, 0444, flexcan_show_attr, NULL), + [FLEXCAN_ATTR_BITRATE] = + __ATTR(bitrate, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_PRESDIV] = + __ATTR(br_presdiv, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_RJW] = + __ATTR(br_rjw, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_PROPSEG] = + __ATTR(br_propseg, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_PSEG1] = + __ATTR(br_pseg1, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_PSEG2] = + __ATTR(br_pseg2, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BR_CLKSRC] = + __ATTR(br_clksrc, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_MAXMB] = + __ATTR(maxmb, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_XMIT_MAXMB] = + __ATTR(xmit_maxmb, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_FIFO] = + __ATTR(fifo, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_WAKEUP] = + __ATTR(wakeup, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_SRX_DIS] = + __ATTR(srx_dis, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_WAK_SRC] = + __ATTR(wak_src, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BCC] = + __ATTR(bcc, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_LOCAL_PRIORITY] = + __ATTR(local_priority, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_ABORT] = + __ATTR(abort, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_LOOPBACK] = + __ATTR(loopback, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_SMP] = + __ATTR(smp, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_BOFF_REC] = + __ATTR(boff_rec, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_TSYN] = + __ATTR(tsyn, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_LISTEN] = + __ATTR(listen, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_EXTEND_MSG] = + __ATTR(ext_msg, 0644, flexcan_show_attr, flexcan_set_attr), + [FLEXCAN_ATTR_STANDARD_MSG] = + __ATTR(std_msg, 0644, flexcan_show_attr, flexcan_set_attr), +#ifdef CONFIG_CAN_DEBUG_DEVICES + [FLEXCAN_ATTR_DUMP_REG] = + __ATTR(dump_reg, 0444, flexcan_show_attr, NULL), + [FLEXCAN_ATTR_DUMP_XMIT_MB] = + __ATTR(dump_xmit_mb, 0444, flexcan_show_attr, NULL), + [FLEXCAN_ATTR_DUMP_RX_MB] = + __ATTR(dump_rx_mb, 0444, flexcan_show_attr, NULL), +#endif +}; + +static void flexcan_set_bitrate(struct flexcan_device *flexcan, int bitrate) +{ + /* TODO:: implement in future + * based on the bitrate to get the timing of + * presdiv, pseg1, pseg2, propseg + */ + int i, rate, div; + bool found = false; + struct time_segment *segment; + rate = clk_get_rate(flexcan->clk); + + if (!bitrate) + bitrate = DEFAULT_BITRATE; + + if (rate % bitrate == 0) { + div = rate / bitrate; + for (i = TIME_SEGMENT_MID; i <= TIME_SEGMENT_MAX; i++) { + if (div % i == 0) { + found = true; + break; + } + } + if (!found) { + for (i = TIME_SEGMENT_MID - 1; + i >= TIME_SEGMENT_MIN; i--) { + if (div % i == 0) { + found = true; + break; + } + } + + } + } + + if (found) { + segment = &time_segments[i - TIME_SEGMENT_MIN]; + flexcan->br_presdiv = div/i - 1; + flexcan->br_propseg = segment->propseg; + flexcan->br_pseg1 = segment->pseg1; + flexcan->br_pseg2 = segment->pseg2; + flexcan->bitrate = bitrate; + } else { + pr_info("The bitrate %d can't supported with clock \ + rate of %d \n", bitrate, rate); + } +} + +static void flexcan_update_bitrate(struct flexcan_device *flexcan) +{ + int rate, div; + struct flexcan_platform_data *plat_data; + plat_data = flexcan->dev->dev.platform_data; + + if (plat_data->root_clk_id) + rate = clk_get_rate(flexcan->clk); + else { + if (flexcan->br_clksrc) + rate = clk_get_rate(flexcan->clk); + else { + struct clk *clk; + clk = clk_get(NULL, "ckih"); + if (!clk) + return; + rate = clk_get_rate(clk); + clk_put(clk); + } + } + if (!rate) + return; + + div = (flexcan->br_presdiv + 1); + div *= + (flexcan->br_propseg + flexcan->br_pseg1 + flexcan->br_pseg2 + 4); + flexcan->bitrate = (rate + div - 1) / div; +} + +#ifdef CONFIG_CAN_DEBUG_DEVICES +static int flexcan_dump_reg(struct flexcan_device *flexcan, char *buf) +{ + int ret = 0; + unsigned int reg; + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + ret += sprintf(buf + ret, "MCR::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL); + ret += sprintf(buf + ret, "CTRL::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RXGMASK); + ret += sprintf(buf + ret, "RXGMASK::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RX14MASK); + ret += sprintf(buf + ret, "RX14MASK::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RX15MASK); + ret += sprintf(buf + ret, "RX15MASK::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR); + ret += sprintf(buf + ret, "ECR::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR); + ret += sprintf(buf + ret, "ESR::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK2); + ret += sprintf(buf + ret, "IMASK2::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1); + ret += sprintf(buf + ret, "IMASK1::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG2); + ret += sprintf(buf + ret, "IFLAG2::0x%x\n", reg); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1); + ret += sprintf(buf + ret, "IFLAG1::0x%x\n", reg); + return ret; +} + +static int flexcan_dump_xmit_mb(struct flexcan_device *flexcan, char *buf) +{ + int ret = 0, i; + i = flexcan->xmit_maxmb + 1; + for (; i <= flexcan->maxmb; i++) + ret += + sprintf(buf + ret, + "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n", + i, flexcan->hwmb[i].mb_cs, + flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1], + flexcan->hwmb[i].mb_data[2]); + return ret; +} + +static int flexcan_dump_rx_mb(struct flexcan_device *flexcan, char *buf) +{ + int ret = 0, i; + for (i = 0; i <= flexcan->xmit_maxmb; i++) + ret += + sprintf(buf + ret, + "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n", + i, flexcan->hwmb[i].mb_cs, + flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1], + flexcan->hwmb[i].mb_data[2]); + return ret; +} +#endif + +static ssize_t flexcan_show_state(struct net_device *net, char *buf) +{ + int ret, esr; + struct flexcan_device *flexcan = netdev_priv(net); + ret = sprintf(buf, "%s::", netif_running(net) ? "Start" : "Stop"); + if (netif_carrier_ok(net)) { + esr = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR); + switch ((esr & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) { + case 0: + ret += sprintf(buf + ret, "normal\n"); + break; + case 1: + ret += sprintf(buf + ret, "error passive\n"); + break; + default: + ret += sprintf(buf + ret, "bus off\n"); + } + } else + ret += sprintf(buf + ret, "bus off\n"); + return ret; +} + +static ssize_t flexcan_show_attr(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int attr_id; + struct net_device *net; + struct flexcan_device *flexcan; + + net = dev_get_drvdata(dev); + BUG_ON(!net); + flexcan = netdev_priv(net); + BUG_ON(!flexcan); + + attr_id = attr - flexcan_dev_attr; + switch (attr_id) { + case FLEXCAN_ATTR_STATE: + return flexcan_show_state(net, buf); + case FLEXCAN_ATTR_BITRATE: + return sprintf(buf, "%d\n", flexcan->bitrate); + case FLEXCAN_ATTR_BR_PRESDIV: + return sprintf(buf, "%d\n", flexcan->br_presdiv + 1); + case FLEXCAN_ATTR_BR_RJW: + return sprintf(buf, "%d\n", flexcan->br_rjw); + case FLEXCAN_ATTR_BR_PROPSEG: + return sprintf(buf, "%d\n", flexcan->br_propseg + 1); + case FLEXCAN_ATTR_BR_PSEG1: + return sprintf(buf, "%d\n", flexcan->br_pseg1 + 1); + case FLEXCAN_ATTR_BR_PSEG2: + return sprintf(buf, "%d\n", flexcan->br_pseg2 + 1); + case FLEXCAN_ATTR_BR_CLKSRC: + return sprintf(buf, "%s\n", flexcan->br_clksrc ? "bus" : "osc"); + case FLEXCAN_ATTR_MAXMB: + return sprintf(buf, "%d\n", flexcan->maxmb + 1); + case FLEXCAN_ATTR_XMIT_MAXMB: + return sprintf(buf, "%d\n", flexcan->xmit_maxmb + 1); + case FLEXCAN_ATTR_FIFO: + return sprintf(buf, "%d\n", flexcan->fifo); + case FLEXCAN_ATTR_WAKEUP: + return sprintf(buf, "%d\n", flexcan->wakeup); + case FLEXCAN_ATTR_SRX_DIS: + return sprintf(buf, "%d\n", flexcan->srx_dis); + case FLEXCAN_ATTR_WAK_SRC: + return sprintf(buf, "%d\n", flexcan->wak_src); + case FLEXCAN_ATTR_BCC: + return sprintf(buf, "%d\n", flexcan->bcc); + case FLEXCAN_ATTR_LOCAL_PRIORITY: + return sprintf(buf, "%d\n", flexcan->lprio); + case FLEXCAN_ATTR_ABORT: + return sprintf(buf, "%d\n", flexcan->abort); + case FLEXCAN_ATTR_LOOPBACK: + return sprintf(buf, "%d\n", flexcan->loopback); + case FLEXCAN_ATTR_SMP: + return sprintf(buf, "%d\n", flexcan->smp); + case FLEXCAN_ATTR_BOFF_REC: + return sprintf(buf, "%d\n", flexcan->boff_rec); + case FLEXCAN_ATTR_TSYN: + return sprintf(buf, "%d\n", flexcan->tsyn); + case FLEXCAN_ATTR_LISTEN: + return sprintf(buf, "%d\n", flexcan->listen); + case FLEXCAN_ATTR_EXTEND_MSG: + return sprintf(buf, "%d\n", flexcan->ext_msg); + case FLEXCAN_ATTR_STANDARD_MSG: + return sprintf(buf, "%d\n", flexcan->std_msg); +#ifdef CONFIG_CAN_DEBUG_DEVICES + case FLEXCAN_ATTR_DUMP_REG: + return flexcan_dump_reg(flexcan, buf); + case FLEXCAN_ATTR_DUMP_XMIT_MB: + return flexcan_dump_xmit_mb(flexcan, buf); + case FLEXCAN_ATTR_DUMP_RX_MB: + return flexcan_dump_rx_mb(flexcan, buf); +#endif + default: + return sprintf(buf, "%s:%p->%p\n", __func__, flexcan_dev_attr, + attr); + } +} + +static ssize_t flexcan_set_attr(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int attr_id, tmp; + struct net_device *net; + struct flexcan_device *flexcan; + + net = dev_get_drvdata(dev); + BUG_ON(!net); + flexcan = netdev_priv(net); + BUG_ON(!flexcan); + + attr_id = attr - flexcan_dev_attr; + + if (mutex_lock_interruptible(&flexcan->mutex)) + return count; + + if (netif_running(net)) + goto set_finish; + + if (attr_id == FLEXCAN_ATTR_BR_CLKSRC) { + if (!strncasecmp(buf, "bus", 3)) + flexcan->br_clksrc = 1; + else if (!strncasecmp(buf, "osc", 3)) + flexcan->br_clksrc = 0; + goto set_finish; + } + + tmp = simple_strtoul(buf, NULL, 0); + switch (attr_id) { + case FLEXCAN_ATTR_BITRATE: + flexcan_set_bitrate(flexcan, tmp); + break; + case FLEXCAN_ATTR_BR_PRESDIV: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PRESDIV)) { + flexcan->br_presdiv = tmp - 1; + flexcan_update_bitrate(flexcan); + } + break; + case FLEXCAN_ATTR_BR_RJW: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_RJW)) + flexcan->br_rjw = tmp - 1; + break; + case FLEXCAN_ATTR_BR_PROPSEG: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PROPSEG)) { + flexcan->br_propseg = tmp - 1; + flexcan_update_bitrate(flexcan); + } + break; + case FLEXCAN_ATTR_BR_PSEG1: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PSEG1)) { + flexcan->br_pseg1 = tmp - 1; + flexcan_update_bitrate(flexcan); + } + break; + case FLEXCAN_ATTR_BR_PSEG2: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PSEG2)) { + flexcan->br_pseg2 = tmp - 1; + flexcan_update_bitrate(flexcan); + } + break; + case FLEXCAN_ATTR_MAXMB: + if ((tmp > 0) && (tmp <= FLEXCAN_MAX_MB)) { + if (flexcan->maxmb != (tmp - 1)) { + flexcan->maxmb = tmp - 1; + if (flexcan->xmit_maxmb < flexcan->maxmb) + flexcan->xmit_maxmb = flexcan->maxmb; + } + } + break; + case FLEXCAN_ATTR_XMIT_MAXMB: + if ((tmp > 0) && (tmp <= (flexcan->maxmb + 1))) { + if (flexcan->xmit_maxmb != (tmp - 1)) + flexcan->xmit_maxmb = tmp - 1; + } + break; + case FLEXCAN_ATTR_FIFO: + flexcan->fifo = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_WAKEUP: + flexcan->wakeup = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_SRX_DIS: + flexcan->srx_dis = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_WAK_SRC: + flexcan->wak_src = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_BCC: + flexcan->bcc = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_LOCAL_PRIORITY: + flexcan->lprio = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_ABORT: + flexcan->abort = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_LOOPBACK: + flexcan->loopback = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_SMP: + flexcan->smp = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_BOFF_REC: + flexcan->boff_rec = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_TSYN: + flexcan->tsyn = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_LISTEN: + flexcan->listen = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_EXTEND_MSG: + flexcan->ext_msg = tmp ? 1 : 0; + break; + case FLEXCAN_ATTR_STANDARD_MSG: + flexcan->std_msg = tmp ? 1 : 0; + break; + } + set_finish: + mutex_unlock(&flexcan->mutex); + return count; +} + +static void flexcan_device_default(struct flexcan_device *dev) +{ + struct platform_device *pdev = dev->dev; + struct flexcan_platform_data *plat_data = (pdev->dev).platform_data; + dev->br_clksrc = plat_data->br_clksrc; + dev->br_rjw = plat_data->br_rjw; + dev->br_presdiv = plat_data->br_presdiv; + dev->br_propseg = plat_data->br_propseg; + dev->br_pseg1 = plat_data->br_pseg1; + dev->br_pseg2 = plat_data->br_pseg2; + + dev->bcc = plat_data->bcc; + dev->srx_dis = plat_data->srx_dis; + dev->smp = plat_data->smp; + dev->boff_rec = plat_data->boff_rec; + + dev->maxmb = FLEXCAN_MAX_MB - 1; + dev->xmit_maxmb = (FLEXCAN_MAX_MB >> 1) - 1; + dev->xmit_mb = dev->maxmb - dev->xmit_maxmb; + + dev->ext_msg = plat_data->ext_msg; + dev->std_msg = plat_data->std_msg; +} + +static int flexcan_device_attach(struct flexcan_device *flexcan) +{ + int ret; + struct resource *res; + struct platform_device *pdev = flexcan->dev; + struct flexcan_platform_data *plat_data = (pdev->dev).platform_data; + struct clk *can_root_clk; + + res = platform_get_resource(flexcan->dev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + flexcan->io_base = ioremap(res->start, res->end - res->start + 1); + if (!flexcan->io_base) + return -ENOMEM; + + flexcan->irq = platform_get_irq(flexcan->dev, 0); + if (!flexcan->irq) { + ret = -ENODEV; + goto no_irq_err; + } + + ret = -EINVAL; + if (plat_data) { + if (plat_data->core_reg) { + flexcan->core_reg = regulator_get(&pdev->dev, + plat_data->core_reg); + if (!flexcan->core_reg) + goto plat_err; + } + + if (plat_data->io_reg) { + flexcan->io_reg = regulator_get(&pdev->dev, + plat_data->io_reg); + if (!flexcan->io_reg) + goto plat_err; + } + } + flexcan->clk = clk_get(&(flexcan->dev)->dev, "can_clk"); + if (plat_data->root_clk_id) { + can_root_clk = clk_get(NULL, plat_data->root_clk_id); + clk_set_parent(flexcan->clk, can_root_clk); + } + flexcan->hwmb = (struct can_hw_mb *)(flexcan->io_base + CAN_MB_BASE); + flexcan->rx_mask = (unsigned int *)(flexcan->io_base + CAN_RXMASK_BASE); + + return 0; + plat_err: + if (flexcan->core_reg) { + regulator_put(flexcan->core_reg); + flexcan->core_reg = NULL; + } + no_irq_err: + if (flexcan->io_base) + iounmap(flexcan->io_base); + return ret; +} + +static void flexcan_device_detach(struct flexcan_device *flexcan) +{ + if (flexcan->clk) { + clk_put(flexcan->clk); + flexcan->clk = NULL; + } + + if (flexcan->io_reg) { + regulator_put(flexcan->io_reg); + flexcan->io_reg = NULL; + } + + if (flexcan->core_reg) { + regulator_put(flexcan->core_reg); + flexcan->core_reg = NULL; + } + + if (flexcan->io_base) + iounmap(flexcan->io_base); +} + +/*! + * @brief The function allocates can device. + * + * @param pdev the pointer of platform device. + * @param setup the initial function pointer of network device. + * + * @return none + */ +struct net_device *flexcan_device_alloc(struct platform_device *pdev, + void (*setup) (struct net_device *dev)) +{ + struct flexcan_device *flexcan; + struct net_device *net; + int i, num; + + net = alloc_netdev(sizeof(*flexcan), "can%d", setup); + if (net == NULL) { + printk(KERN_ERR "Allocate netdevice for FlexCAN fail!\n"); + return NULL; + } + flexcan = netdev_priv(net); + memset(flexcan, 0, sizeof(*flexcan)); + + mutex_init(&flexcan->mutex); + init_timer(&flexcan->timer); + + flexcan->dev = pdev; + if (flexcan_device_attach(flexcan)) { + printk(KERN_ERR "Attach FlexCAN fail!\n"); + free_netdev(net); + return NULL; + } + flexcan_device_default(flexcan); + flexcan_set_bitrate(flexcan, flexcan->bitrate); + flexcan_update_bitrate(flexcan); + + num = ARRAY_SIZE(flexcan_dev_attr); + + for (i = 0; i < num; i++) { + if (device_create_file(&pdev->dev, flexcan_dev_attr + i)) { + printk(KERN_ERR "Create attribute file fail!\n"); + break; + } + } + + if (i != num) { + for (; i >= 0; i--) + device_remove_file(&pdev->dev, flexcan_dev_attr + i); + free_netdev(net); + return NULL; + } + dev_set_drvdata(&pdev->dev, net); + return net; +} + +/*! + * @brief The function frees can device. + * + * @param pdev the pointer of platform device. + * + * @return none + */ +void flexcan_device_free(struct platform_device *pdev) +{ + struct net_device *net; + struct flexcan_device *flexcan; + int i, num; + net = (struct net_device *)dev_get_drvdata(&pdev->dev); + + unregister_netdev(net); + flexcan = netdev_priv(net); + del_timer(&flexcan->timer); + + num = ARRAY_SIZE(flexcan_dev_attr); + + for (i = 0; i < num; i++) + device_remove_file(&pdev->dev, flexcan_dev_attr + i); + + flexcan_device_detach(netdev_priv(net)); + free_netdev(net); +} diff --git a/drivers/net/can/flexcan/drv.c b/drivers/net/can/flexcan/drv.c new file mode 100644 index 000000000000..f0a408d5640f --- /dev/null +++ b/drivers/net/can/flexcan/drv.c @@ -0,0 +1,628 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drv.c + * + * @brief Driver for Freescale CAN Controller FlexCAN. + * + * @ingroup can + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "flexcan.h" + +static void flexcan_hw_start(struct flexcan_device *flexcan) +{ + unsigned int reg; + if ((flexcan->maxmb + 1) > 32) { + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IMASK1); + reg = (1 << (flexcan->maxmb - 31)) - 1; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_IMASK2); + } else { + reg = (1 << (flexcan->maxmb + 1)) - 1; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_IMASK1); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2); + } + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR) & (~__MCR_HALT); + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); +} + +static void flexcan_hw_stop(struct flexcan_device *flexcan) +{ + unsigned int reg; + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + __raw_writel(reg | __MCR_HALT, flexcan->io_base + CAN_HW_REG_MCR); +} + +static int flexcan_hw_reset(struct flexcan_device *flexcan) +{ + unsigned int reg; + int timeout = 100000; + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + __raw_writel(reg | __MCR_MDIS, flexcan->io_base + CAN_HW_REG_MCR); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL); + if (flexcan->br_clksrc) + reg |= __CTRL_CLK_SRC; + else + reg &= ~__CTRL_CLK_SRC; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_CTRL); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR) & (~__MCR_MDIS); + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); + reg |= __MCR_SOFT_RST; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + while (reg & __MCR_SOFT_RST) { + if (--timeout <= 0) { + printk(KERN_ERR "Flexcan software Reset Timeouted\n"); + return -1; + } + udelay(10); + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + } + return 0; +} + +static inline void flexcan_mcr_setup(struct flexcan_device *flexcan) +{ + unsigned int reg; + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + reg &= ~(__MCR_MAX_MB_MASK | __MCR_WAK_MSK | __MCR_MAX_IDAM_MASK); + + if (flexcan->fifo) + reg |= __MCR_FEN; + else + reg &= ~__MCR_FEN; + + if (flexcan->wakeup) + reg |= __MCR_SLF_WAK | __MCR_WAK_MSK; + else + reg &= ~(__MCR_SLF_WAK | __MCR_WAK_MSK); + + if (flexcan->wak_src) + reg |= __MCR_WAK_SRC; + else + reg &= ~__MCR_WAK_SRC; + + if (flexcan->srx_dis) + reg |= __MCR_SRX_DIS; + else + reg &= ~__MCR_SRX_DIS; + + if (flexcan->bcc) + reg |= __MCR_BCC; + else + reg &= ~__MCR_BCC; + + if (flexcan->lprio) + reg |= __MCR_LPRIO_EN; + else + reg &= ~__MCR_LPRIO_EN; + + if (flexcan->abort) + reg |= __MCR_AEN; + else + reg &= ~__MCR_AEN; + + reg |= (flexcan->maxmb << __MCR_MAX_MB_OFFSET); + reg |= __MCR_DOZE | __MCR_MAX_IDAM_C; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); +} + +static inline void flexcan_ctrl_setup(struct flexcan_device *flexcan) +{ + unsigned int reg; + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL); + reg &= ~(__CTRL_PRESDIV_MASK | __CTRL_RJW_MASK | __CTRL_PSEG1_MASK | + __CTRL_PSEG2_MASK | __CTRL_PROPSEG_MASK); + + if (flexcan->loopback) + reg |= __CTRL_LPB; + else + reg &= ~__CTRL_LPB; + + if (flexcan->smp) + reg |= __CTRL_SMP; + else + reg &= ~__CTRL_SMP; + + if (flexcan->boff_rec) + reg |= __CTRL_BOFF_REC; + else + reg &= ~__CTRL_BOFF_REC; + + if (flexcan->tsyn) + reg |= __CTRL_TSYN; + else + reg &= ~__CTRL_TSYN; + + if (flexcan->listen) + reg |= __CTRL_LOM; + else + reg &= ~__CTRL_LOM; + + reg |= (flexcan->br_presdiv << __CTRL_PRESDIV_OFFSET) | + (flexcan->br_rjw << __CTRL_RJW_OFFSET) | + (flexcan->br_pseg1 << __CTRL_PSEG1_OFFSET) | + (flexcan->br_pseg2 << __CTRL_PSEG2_OFFSET) | + (flexcan->br_propseg << __CTRL_PROPSEG_OFFSET); + + reg &= ~__CTRL_LBUF; + + reg |= __CTRL_TWRN_MSK | __CTRL_RWRN_MSK | __CTRL_BOFF_MSK | + __CTRL_ERR_MSK; + + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_CTRL); +} + +static int flexcan_hw_restart(struct net_device *dev) +{ + unsigned int reg; + struct flexcan_device *flexcan = netdev_priv(dev); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + if (reg & __MCR_SOFT_RST) + return 1; + + flexcan_mcr_setup(flexcan); + + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK1); + + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG2); + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG1); + + __raw_writel(0, flexcan->io_base + CAN_HW_REG_ECR); + + flexcan_mbm_init(flexcan); + netif_carrier_on(dev); + flexcan_hw_start(flexcan); + + if (netif_queue_stopped(dev)) + netif_start_queue(dev); + + return 0; +} + +static void flexcan_hw_watch(unsigned long data) +{ + unsigned int reg, ecr; + struct net_device *dev = (struct net_device *)data; + struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL; + + BUG_ON(!flexcan); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + if (reg & __MCR_MDIS) { + if (flexcan_hw_restart(dev)) + mod_timer(&flexcan->timer, HZ / 20); + return; + } + ecr = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR); + if (flexcan->boff_rec) { + if (((reg & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) > 1) { + reg |= __MCR_SOFT_RST; + __raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR); + mod_timer(&flexcan->timer, HZ / 20); + return; + } + netif_carrier_on(dev); + } +} + +static void flexcan_hw_busoff(struct net_device *dev) +{ + struct flexcan_device *flexcan = netdev_priv(dev); + unsigned int reg; + + netif_carrier_off(dev); + + flexcan->timer.function = flexcan_hw_watch; + flexcan->timer.data = (unsigned long)dev; + + if (flexcan->boff_rec) { + mod_timer(&flexcan->timer, HZ / 10); + return; + } + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR); + __raw_writel(reg | __MCR_SOFT_RST, flexcan->io_base + CAN_HW_REG_MCR); + mod_timer(&flexcan->timer, HZ / 20); +} + +static int flexcan_hw_open(struct flexcan_device *flexcan) +{ + if (flexcan_hw_reset(flexcan)) + return -EFAULT; + + flexcan_mcr_setup(flexcan); + flexcan_ctrl_setup(flexcan); + + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK1); + + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG2); + __raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG1); + + __raw_writel(0, flexcan->io_base + CAN_HW_REG_ECR); + return 0; +} + +static void flexcan_err_handler(struct net_device *dev) +{ + struct flexcan_device *flexcan = netdev_priv(dev); + struct sk_buff *skb; + struct can_frame *frame; + unsigned int esr, ecr; + + esr = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR); + __raw_writel(esr & __ESR_INTERRUPTS, flexcan->io_base + CAN_HW_REG_ESR); + + if (esr & __ESR_WAK_INT) + return; + + skb = dev_alloc_skb(sizeof(struct can_frame)); + if (!skb) { + printk(KERN_ERR "%s: allocates skb fail in\n", __func__); + return; + } + frame = (struct can_frame *)skb_put(skb, sizeof(*frame)); + memset(frame, 0, sizeof(*frame)); + frame->can_id = CAN_ERR_FLAG | CAN_ERR_CRTL; + frame->can_dlc = CAN_ERR_DLC; + + if (esr & __ESR_TWRN_INT) + frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; + + if (esr & __ESR_RWRN_INT) + frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; + + if (esr & __ESR_BOFF_INT) + frame->can_id |= CAN_ERR_BUSOFF; + + if (esr & __ESR_ERR_INT) { + if (esr & __ESR_BIT1_ERR) + frame->data[2] |= CAN_ERR_PROT_BIT1; + + if (esr & __ESR_BIT0_ERR) + frame->data[2] |= CAN_ERR_PROT_BIT0; + + if (esr & __ESR_ACK_ERR) + frame->can_id |= CAN_ERR_ACK; + + /*TODO:// if (esr & __ESR_CRC_ERR) */ + + if (esr & __ESR_FRM_ERR) + frame->data[2] |= CAN_ERR_PROT_FORM; + + if (esr & __ESR_STF_ERR) + frame->data[2] |= CAN_ERR_PROT_STUFF; + + ecr = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR); + switch ((esr & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) { + case 0: + if (__ECR_TX_ERR_COUNTER(ecr) >= __ECR_ACTIVE_THRESHOLD) + frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; + if (__ECR_RX_ERR_COUNTER(ecr) >= __ECR_ACTIVE_THRESHOLD) + frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; + break; + case 1: + if (__ECR_TX_ERR_COUNTER(ecr) >= + __ECR_PASSIVE_THRESHOLD) + frame->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; + + if (__ECR_RX_ERR_COUNTER(ecr) >= + __ECR_PASSIVE_THRESHOLD) + frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; + break; + default: + frame->can_id |= CAN_ERR_BUSOFF; + } + } + + if (frame->can_id & CAN_ERR_BUSOFF) + flexcan_hw_busoff(dev); + + skb->dev = dev; + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_receive_skb(skb); +} + +static irqreturn_t flexcan_irq_handler(int irq, void *data) +{ + struct net_device *dev = (struct net_device *)data; + struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL; + unsigned int reg; + + BUG_ON(!flexcan); + + reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR); + if (reg & __ESR_INTERRUPTS) { + flexcan_err_handler(dev); + return IRQ_HANDLED; + } + + flexcan_mbm_isr(dev); + return IRQ_HANDLED; +} + +static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct can_frame *frame = (struct can_frame *)skb->data; + struct flexcan_device *flexcan = netdev_priv(dev); + struct net_device_stats *stats = &dev->stats; + + BUG_ON(!flexcan); + + if (frame->can_dlc > 8) + return -EINVAL; + + if (!flexcan_mbm_xmit(flexcan, frame)) { + dev_kfree_skb(skb); + stats->tx_bytes += frame->can_dlc; + stats->tx_packets++; + dev->trans_start = jiffies; + return NETDEV_TX_OK; + } + netif_stop_queue(dev); + return NETDEV_TX_BUSY; +} + +static int flexcan_open(struct net_device *dev) +{ + struct flexcan_device *flexcan; + struct platform_device *pdev; + struct flexcan_platform_data *plat_data; + + flexcan = netdev_priv(dev); + BUG_ON(!flexcan); + + pdev = flexcan->dev; + plat_data = (pdev->dev).platform_data; + if (plat_data && plat_data->active) + plat_data->active(pdev->id); + + if (flexcan->clk) + if (clk_enable(flexcan->clk)) + goto clk_err; + + if (flexcan->core_reg) + if (regulator_enable(flexcan->core_reg)) + goto core_reg_err; + + if (flexcan->io_reg) + if (regulator_enable(flexcan->io_reg)) + goto io_reg_err; + + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 1); + + if (request_irq(flexcan->irq, flexcan_irq_handler, IRQF_SHARED, + dev->name, dev)) + goto irq_err; + add_interrupt_randomness(flexcan->irq); + + if (flexcan_hw_open(flexcan)) + goto open_err; + + flexcan_mbm_init(flexcan); + netif_carrier_on(dev); + flexcan_hw_start(flexcan); + return 0; + open_err: + free_irq(flexcan->irq, dev); + irq_err: + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 0); + + if (flexcan->io_reg) + regulator_disable(flexcan->io_reg); + io_reg_err: + if (flexcan->core_reg) + regulator_disable(flexcan->core_reg); + core_reg_err: + if (flexcan->clk) + clk_disable(flexcan->clk); + clk_err: + if (plat_data && plat_data->inactive) + plat_data->inactive(pdev->id); + return -ENODEV; +} + +static int flexcan_stop(struct net_device *dev) +{ + struct flexcan_device *flexcan; + struct platform_device *pdev; + struct flexcan_platform_data *plat_data; + + flexcan = netdev_priv(dev); + + BUG_ON(!flexcan); + + pdev = flexcan->dev; + plat_data = (pdev->dev).platform_data; + + flexcan_hw_stop(flexcan); + + free_irq(flexcan->irq, dev); + + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 0); + + if (flexcan->io_reg) + regulator_disable(flexcan->io_reg); + if (flexcan->core_reg) + regulator_disable(flexcan->core_reg); + if (flexcan->clk) + clk_disable(flexcan->clk); + if (plat_data && plat_data->inactive) + plat_data->inactive(pdev->id); + return 0; +} + +static struct net_device_ops flexcan_netdev_ops = { + .ndo_open = flexcan_open, + .ndo_stop = flexcan_stop, + .ndo_start_xmit = flexcan_start_xmit, +}; + +static void flexcan_setup(struct net_device *dev) +{ + dev->type = ARPHRD_CAN; + dev->mtu = sizeof(struct can_frame); + dev->hard_header_len = 0; + dev->addr_len = 0; + dev->tx_queue_len = FLEXCAN_MAX_MB; + dev->flags = IFF_NOARP; + dev->features = NETIF_F_NO_CSUM; + + dev->netdev_ops = &flexcan_netdev_ops; +} + +static int flexcan_probe(struct platform_device *pdev) +{ + struct net_device *net; + net = flexcan_device_alloc(pdev, flexcan_setup); + if (!net) + return -ENOMEM; + + if (register_netdev(net)) { + flexcan_device_free(pdev); + return -ENODEV; + } + return 0; +} + +static int flexcan_remove(struct platform_device *pdev) +{ + flexcan_device_free(pdev); + return 0; +} + +static int flexcan_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct net_device *net; + struct flexcan_device *flexcan; + struct flexcan_platform_data *plat_data; + net = (struct net_device *)dev_get_drvdata(&pdev->dev); + flexcan = netdev_priv(net); + + BUG_ON(!flexcan); + + if (!(net->flags & IFF_UP)) + return 0; + if (flexcan->wakeup) + set_irq_wake(flexcan->irq, 1); + else { + plat_data = (pdev->dev).platform_data; + + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 0); + + if (flexcan->io_reg) + regulator_disable(flexcan->io_reg); + if (flexcan->core_reg) + regulator_disable(flexcan->core_reg); + if (flexcan->clk) + clk_disable(flexcan->clk); + if (plat_data && plat_data->inactive) + plat_data->inactive(pdev->id); + } + return 0; +} + +static int flexcan_resume(struct platform_device *pdev) +{ + struct net_device *net; + struct flexcan_device *flexcan; + struct flexcan_platform_data *plat_data; + net = (struct net_device *)dev_get_drvdata(&pdev->dev); + flexcan = netdev_priv(net); + + BUG_ON(!flexcan); + + if (!(net->flags & IFF_UP)) + return 0; + + if (flexcan->wakeup) + set_irq_wake(flexcan->irq, 0); + else { + plat_data = (pdev->dev).platform_data; + if (plat_data && plat_data->active) + plat_data->active(pdev->id); + + if (flexcan->clk) { + if (clk_enable(flexcan->clk)) + printk(KERN_ERR "%s:enable clock fail\n", + __func__); + } + + if (flexcan->core_reg) { + if (regulator_enable(flexcan->core_reg)) + printk(KERN_ERR "%s:enable core voltage\n", + __func__); + } + if (flexcan->io_reg) { + if (regulator_enable(flexcan->io_reg)) + printk(KERN_ERR "%s:enable io voltage\n", + __func__); + } + + if (plat_data && plat_data->xcvr_enable) + plat_data->xcvr_enable(pdev->id, 1); + } + return 0; +} + +static struct platform_driver flexcan_driver = { + .driver = { + .name = FLEXCAN_DEVICE_NAME, + }, + .probe = flexcan_probe, + .remove = flexcan_remove, + .suspend = flexcan_suspend, + .resume = flexcan_resume, +}; + +static __init int flexcan_init(void) +{ + pr_info("Freescale FlexCAN Driver \n"); + return platform_driver_register(&flexcan_driver); +} + +static __exit void flexcan_exit(void) +{ + return platform_driver_unregister(&flexcan_driver); +} + +module_init(flexcan_init); +module_exit(flexcan_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/net/can/flexcan/flexcan.h b/drivers/net/can/flexcan/flexcan.h new file mode 100644 index 000000000000..51a800bd8e55 --- /dev/null +++ b/drivers/net/can/flexcan/flexcan.h @@ -0,0 +1,222 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file flexcan.h + * + * @brief FlexCan definitions. + * + * @ingroup can + */ + +#ifndef __CAN_FLEXCAN_H__ +#define __CAN_FLEXCAN_H__ + +#include +#include +#include +#include +#include +#include +#include + +#define FLEXCAN_DEVICE_NAME "FlexCAN" + +#define CAN_MB_RX_INACTIVE 0x0 +#define CAN_MB_RX_EMPTY 0x4 +#define CAN_MB_RX_FULL 0x2 +#define CAN_MB_RX_OVERRUN 0x6 +#define CAN_MB_RX_BUSY 0x1 + +#define CAN_MB_TX_INACTIVE 0x8 +#define CAN_MB_TX_ABORT 0x9 +#define CAN_MB_TX_ONCE 0xC +#define CAN_MB_TX_REMOTE 0xA + +struct can_hw_mb { + unsigned int mb_cs; + unsigned int mb_id; + unsigned char mb_data[8]; +}; + +#define MB_CS_CODE_OFFSET 24 +#define MB_CS_CODE_MASK (0xF << MB_CS_CODE_OFFSET) +#define MB_CS_SRR_OFFSET 22 +#define MB_CS_SRR_MASK (0x1 << MB_CS_SRR_OFFSET) +#define MB_CS_IDE_OFFSET 21 +#define MB_CS_IDE_MASK (0x1 << MB_CS_IDE_OFFSET) +#define MB_CS_RTR_OFFSET 20 +#define MB_CS_RTR_MASK (0x1 << MB_CS_RTR_OFFSET) +#define MB_CS_LENGTH_OFFSET 16 +#define MB_CS_LENGTH_MASK (0xF << MB_CS_LENGTH_OFFSET) +#define MB_CS_TIMESTAMP_OFFSET 0 +#define MB_CS_TIMESTAMP_MASK (0xFF << MB_CS_TIMESTAMP_OFFSET) + +#define CAN_HW_REG_MCR 0x00 +#define CAN_HW_REG_CTRL 0x04 +#define CAN_HW_REG_TIMER 0x08 +#define CAN_HW_REG_RXGMASK 0x10 +#define CAN_HW_REG_RX14MASK 0x14 +#define CAN_HW_REG_RX15MASK 0x18 +#define CAN_HW_REG_ECR 0x1C +#define CAN_HW_REG_ESR 0x20 +#define CAN_HW_REG_IMASK2 0x24 +#define CAN_HW_REG_IMASK1 0x28 +#define CAN_HW_REG_IFLAG2 0x2C +#define CAN_HW_REG_IFLAG1 0x30 + +#define CAN_MB_BASE 0x0080 +#define CAN_RXMASK_BASE 0x0880 +#define CAN_FIFO_BASE 0xE0 + +#define __MCR_MDIS (1 << 31) +#define __MCR_FRZ (1 << 30) +#define __MCR_FEN (1 << 29) +#define __MCR_HALT (1 << 28) +#define __MCR_NOTRDY (1 << 27) +#define __MCR_WAK_MSK (1 << 26) +#define __MCR_SOFT_RST (1 << 25) +#define __MCR_FRZ_ACK (1 << 24) +#define __MCR_SLF_WAK (1 << 22) +#define __MCR_WRN_EN (1 << 21) +#define __MCR_LPM_ACK (1 << 20) +#define __MCR_WAK_SRC (1 << 19) +#define __MCR_DOZE (1 << 18) +#define __MCR_SRX_DIS (1 << 17) +#define __MCR_BCC (1 << 16) +#define __MCR_LPRIO_EN (1 << 13) +#define __MCR_AEN (1 << 12) +#define __MCR_MAX_IDAM_OFFSET 8 +#define __MCR_MAX_IDAM_MASK (0x3 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_IDAM_A (0x0 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_IDAM_B (0x1 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_IDAM_C (0x2 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_IDAM_D (0x3 << __MCR_MAX_IDAM_OFFSET) +#define __MCR_MAX_MB_OFFSET 0 +#define __MCR_MAX_MB_MASK (0x3F) + +#define __CTRL_PRESDIV_OFFSET 24 +#define __CTRL_PRESDIV_MASK (0xFF << __CTRL_PRESDIV_OFFSET) +#define __CTRL_RJW_OFFSET 22 +#define __CTRL_RJW_MASK (0x3 << __CTRL_RJW_OFFSET) +#define __CTRL_PSEG1_OFFSET 19 +#define __CTRL_PSEG1_MASK (0x7 << __CTRL_PSEG1_OFFSET) +#define __CTRL_PSEG2_OFFSET 16 +#define __CTRL_PSEG2_MASK (0x7 << __CTRL_PSEG2_OFFSET) +#define __CTRL_BOFF_MSK (0x1 << 15) +#define __CTRL_ERR_MSK (0x1 << 14) +#define __CTRL_CLK_SRC (0x1 << 13) +#define __CTRL_LPB (0x1 << 12) +#define __CTRL_TWRN_MSK (0x1 << 11) +#define __CTRL_RWRN_MSK (0x1 << 10) +#define __CTRL_SMP (0x1 << 7) +#define __CTRL_BOFF_REC (0x1 << 6) +#define __CTRL_TSYN (0x1 << 5) +#define __CTRL_LBUF (0x1 << 4) +#define __CTRL_LOM (0x1 << 3) +#define __CTRL_PROPSEG_OFFSET 0 +#define __CTRL_PROPSEG_MASK (0x7) + +#define __ECR_TX_ERR_COUNTER(x) ((x) & 0xFF) +#define __ECR_RX_ERR_COUNTER(x) (((x) >> 8) & 0xFF) +#define __ECR_PASSIVE_THRESHOLD 128 +#define __ECR_ACTIVE_THRESHOLD 96 + +#define __ESR_TWRN_INT (0x1 << 17) +#define __ESR_RWRN_INT (0x1 << 16) +#define __ESR_BIT1_ERR (0x1 << 15) +#define __ESR_BIT0_ERR (0x1 << 14) +#define __ESR_ACK_ERR (0x1 << 13) +#define __ESR_CRC_ERR (0x1 << 12) +#define __ESR_FRM_ERR (0x1 << 11) +#define __ESR_STF_ERR (0x1 << 10) +#define __ESR_TX_WRN (0x1 << 9) +#define __ESR_RX_WRN (0x1 << 8) +#define __ESR_IDLE (0x1 << 7) +#define __ESR_TXRX (0x1 << 6) +#define __ESR_FLT_CONF_OFF 4 +#define __ESR_FLT_CONF_MASK (0x3 << __ESR_FLT_CONF_OFF) +#define __ESR_BOFF_INT (0x1 << 2) +#define __ESR_ERR_INT (0x1 << 1) +#define __ESR_WAK_INT (0x1) + +#define __ESR_INTERRUPTS (__ESR_WAK_INT | __ESR_ERR_INT | \ + __ESR_BOFF_INT | __ESR_TWRN_INT | \ + __ESR_RWRN_INT) + +#define __FIFO_OV_INT 0x0080 +#define __FIFO_WARN_INT 0x0040 +#define __FIFO_RDY_INT 0x0020 + +struct flexcan_device { + struct mutex mutex; + void *io_base; + struct can_hw_mb *hwmb; + unsigned int *rx_mask; + unsigned int xmit_mb; + unsigned int bitrate; + /* word 1 */ + unsigned int br_presdiv:8; + unsigned int br_rjw:2; + unsigned int br_propseg:3; + unsigned int br_pseg1:3; + unsigned int br_pseg2:3; + unsigned int maxmb:6; + unsigned int xmit_maxmb:6; + unsigned int wd1_resv:1; + + /* word 2 */ + unsigned int fifo:1; + unsigned int wakeup:1; + unsigned int srx_dis:1; + unsigned int wak_src:1; + unsigned int bcc:1; + unsigned int lprio:1; + unsigned int abort:1; + unsigned int br_clksrc:1; + unsigned int loopback:1; + unsigned int smp:1; + unsigned int boff_rec:1; + unsigned int tsyn:1; + unsigned int listen:1; + + unsigned int ext_msg:1; + unsigned int std_msg:1; + + struct timer_list timer; + struct platform_device *dev; + struct regulator *core_reg; + struct regulator *io_reg; + struct clk *clk; + int irq; +}; + +#define FLEXCAN_MAX_FIFO_MB 8 +#define FLEXCAN_MAX_MB 64 +#define FLEXCAN_MAX_PRESDIV 256 +#define FLEXCAN_MAX_RJW 4 +#define FLEXCAN_MAX_PSEG1 8 +#define FLEXCAN_MAX_PSEG2 8 +#define FLEXCAN_MAX_PROPSEG 8 +#define FLEXCAN_MAX_BITRATE 1000000 + +extern struct net_device *flexcan_device_alloc(struct platform_device *pdev, + void (*setup) (struct net_device + *dev)); +extern void flexcan_device_free(struct platform_device *pdev); + +extern void flexcan_mbm_init(struct flexcan_device *flexcan); +extern void flexcan_mbm_isr(struct net_device *dev); +extern int flexcan_mbm_xmit(struct flexcan_device *flexcan, + struct can_frame *frame); +#endif /* __CAN_FLEXCAN_H__ */ diff --git a/drivers/net/can/flexcan/mbm.c b/drivers/net/can/flexcan/mbm.c new file mode 100644 index 000000000000..c846d97daadb --- /dev/null +++ b/drivers/net/can/flexcan/mbm.c @@ -0,0 +1,361 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mbm.c + * + * @brief Driver for Freescale CAN Controller FlexCAN. + * + * @ingroup can + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "flexcan.h" + +#define flexcan_swab32(x) \ + (((x) << 24) | ((x) >> 24) |\ + (((x) & (__u32)0x0000ff00UL) << 8) |\ + (((x) & (__u32)0x00ff0000UL) >> 8)) + +static inline void flexcan_memcpy(void *dst, void *src, int len) +{ + int i; + unsigned int *d = (unsigned int *)dst, *s = (unsigned int *)src; + len = (len + 3) >> 2; + for (i = 0; i < len; i++, s++, d++) + *d = flexcan_swab32(*s); +} + +static void flexcan_mb_bottom(struct net_device *dev, int index) +{ + struct flexcan_device *flexcan = netdev_priv(dev); + struct net_device_stats *stats = &dev->stats; + struct can_hw_mb *hwmb; + struct can_frame *frame; + struct sk_buff *skb; + unsigned int tmp; + + hwmb = flexcan->hwmb + index; + if (flexcan->fifo || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) { + if ((hwmb->mb_cs & MB_CS_CODE_MASK) >> MB_CS_CODE_OFFSET == + CAN_MB_TX_ABORT) { + hwmb->mb_cs &= ~MB_CS_CODE_MASK; + hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET; + } + + if (hwmb->mb_cs & (CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET)) { + if (netif_queue_stopped(dev)) + netif_start_queue(dev); + return; + } + } + skb = dev_alloc_skb(sizeof(struct can_frame)); + if (skb) { + frame = (struct can_frame *)skb_put(skb, sizeof(*frame)); + memset(frame, 0, sizeof(*frame)); + if (hwmb->mb_cs & MB_CS_IDE_MASK) + frame->can_id = + (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG; + else + frame->can_id = (hwmb->mb_id >> 18) & CAN_SFF_MASK; + + if (hwmb->mb_cs & MB_CS_RTR_MASK) + frame->can_id |= CAN_RTR_FLAG; + + frame->can_dlc = + (hwmb->mb_cs & MB_CS_LENGTH_MASK) >> MB_CS_LENGTH_OFFSET; + + if (frame->can_dlc && frame->can_dlc) + flexcan_memcpy(frame->data, hwmb->mb_data, + frame->can_dlc); + + if (flexcan->fifo + || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) { + hwmb->mb_cs &= ~MB_CS_CODE_MASK; + hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET; + if (netif_queue_stopped(dev)) + netif_start_queue(dev); + } + + tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER); + + dev->last_rx = jiffies; + stats->rx_packets++; + stats->rx_bytes += frame->can_dlc; + + skb->dev = dev; + skb->protocol = __constant_htons(ETH_P_CAN); + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_rx(skb); + } else { + tmp = hwmb->mb_cs; + tmp = hwmb->mb_id; + tmp = hwmb->mb_data[0]; + if (flexcan->fifo + || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) { + hwmb->mb_cs &= ~MB_CS_CODE_MASK; + hwmb->mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET; + if (netif_queue_stopped(dev)) + netif_start_queue(dev); + } + tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER); + stats->rx_dropped++; + } +} + +static void flexcan_fifo_isr(struct net_device *dev, unsigned int iflag1) +{ + struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL; + struct net_device_stats *stats = &dev->stats; + struct sk_buff *skb; + struct can_hw_mb *hwmb = flexcan->hwmb; + struct can_frame *frame; + unsigned int tmp; + + if (iflag1 & __FIFO_RDY_INT) { + skb = dev_alloc_skb(sizeof(struct can_frame)); + if (skb) { + frame = + (struct can_frame *)skb_put(skb, sizeof(*frame)); + memset(frame, 0, sizeof(*frame)); + if (hwmb->mb_cs & MB_CS_IDE_MASK) + frame->can_id = + (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG; + else + frame->can_id = + (hwmb->mb_id >> 18) & CAN_SFF_MASK; + + if (hwmb->mb_cs & MB_CS_RTR_MASK) + frame->can_id |= CAN_RTR_FLAG; + + frame->can_dlc = + (hwmb->mb_cs & MB_CS_LENGTH_MASK) >> + MB_CS_LENGTH_OFFSET; + + if (frame->can_dlc && (frame->can_dlc <= 8)) + flexcan_memcpy(frame->data, hwmb->mb_data, + frame->can_dlc); + tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER); + + dev->last_rx = jiffies; + + stats->rx_packets++; + stats->rx_bytes += frame->can_dlc; + + skb->dev = dev; + skb->protocol = __constant_htons(ETH_P_CAN); + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_rx(skb); + } else { + tmp = hwmb->mb_cs; + tmp = hwmb->mb_id; + tmp = hwmb->mb_data[0]; + tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER); + } + } + + if (iflag1 & (__FIFO_OV_INT | __FIFO_WARN_INT)) { + skb = dev_alloc_skb(sizeof(struct can_frame)); + if (skb) { + frame = + (struct can_frame *)skb_put(skb, sizeof(*frame)); + memset(frame, 0, sizeof(*frame)); + frame->can_id = CAN_ERR_FLAG | CAN_ERR_CRTL; + frame->can_dlc = CAN_ERR_DLC; + if (iflag1 & __FIFO_WARN_INT) + frame->data[1] |= + CAN_ERR_CRTL_TX_WARNING | + CAN_ERR_CRTL_RX_WARNING; + if (iflag1 & __FIFO_OV_INT) + frame->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; + + skb->dev = dev; + skb->protocol = __constant_htons(ETH_P_CAN); + skb->ip_summed = CHECKSUM_UNNECESSARY; + netif_rx(skb); + } + } +} + +/*! + * @brief The function call by CAN ISR to handle mb events. + * + * @param dev the pointer of network device. + * + * @return none + */ +void flexcan_mbm_isr(struct net_device *dev) +{ + int i, iflag1, iflag2, maxmb; + struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL; + + if (flexcan->maxmb > 31) { + maxmb = flexcan->maxmb + 1 - 32; + iflag1 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1) & + __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1); + iflag2 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG2) & + __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK2); + iflag2 &= (1 << maxmb) - 1; + maxmb = 32; + } else { + maxmb = flexcan->maxmb + 1; + iflag1 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1) & + __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1); + iflag1 &= (1 << maxmb) - 1; + iflag2 = 0; + } + + __raw_writel(iflag1, flexcan->io_base + CAN_HW_REG_IFLAG1); + __raw_writel(iflag2, flexcan->io_base + CAN_HW_REG_IFLAG2); + + if (flexcan->fifo) { + flexcan_fifo_isr(dev, iflag1); + iflag1 &= 0xFFFFFF00; + } + for (i = 0; iflag1 && (i < maxmb); i++) { + if (iflag1 & (1 << i)) { + iflag1 &= ~(1 << i); + flexcan_mb_bottom(dev, i); + } + } + + for (i = maxmb; iflag2 && (i <= flexcan->maxmb); i++) { + if (iflag2 & (1 << (i - 32))) { + iflag2 &= ~(1 << (i - 32)); + flexcan_mb_bottom(dev, i); + } + } +} + +/*! + * @brief function to xmit message buffer + * + * @param flexcan the pointer of can hardware device. + * @param frame the pointer of can message frame. + * + * @return Returns 0 if xmit is success. otherwise returns non-zero. + */ +int flexcan_mbm_xmit(struct flexcan_device *flexcan, struct can_frame *frame) +{ + int i = flexcan->xmit_mb; + struct can_hw_mb *hwmb = flexcan->hwmb; + + do { + if ((hwmb[i].mb_cs & MB_CS_CODE_MASK) >> MB_CS_CODE_OFFSET == + CAN_MB_TX_INACTIVE) + break; + if ((++i) > flexcan->maxmb) { + if (flexcan->fifo) + i = FLEXCAN_MAX_FIFO_MB; + else + i = flexcan->xmit_maxmb + 1; + } + if (i == flexcan->xmit_mb) + return -1; + } while (1); + + flexcan->xmit_mb = i + 1; + if (flexcan->xmit_mb > flexcan->maxmb) { + if (flexcan->fifo) + flexcan->xmit_mb = FLEXCAN_MAX_FIFO_MB; + else + flexcan->xmit_mb = flexcan->xmit_maxmb + 1; + } + + if (frame->can_id & CAN_RTR_FLAG) + hwmb[i].mb_cs |= 1 << MB_CS_RTR_OFFSET; + else + hwmb[i].mb_cs &= ~MB_CS_RTR_MASK; + + if (frame->can_id & CAN_EFF_FLAG) { + hwmb[i].mb_cs |= 1 << MB_CS_IDE_OFFSET; + hwmb[i].mb_cs |= 1 << MB_CS_SRR_OFFSET; + hwmb[i].mb_id = frame->can_id & CAN_EFF_MASK; + } else { + hwmb[i].mb_cs &= ~MB_CS_IDE_MASK; + hwmb[i].mb_id = (frame->can_id & CAN_SFF_MASK) << 18; + } + + hwmb[i].mb_cs &= ~MB_CS_LENGTH_MASK; + hwmb[i].mb_cs |= frame->can_dlc << MB_CS_LENGTH_OFFSET; + flexcan_memcpy(hwmb[i].mb_data, frame->data, frame->can_dlc); + hwmb[i].mb_cs &= ~MB_CS_CODE_MASK; + hwmb[i].mb_cs |= CAN_MB_TX_ONCE << MB_CS_CODE_OFFSET; + return 0; +} + +/*! + * @brief function to initial message buffer + * + * @param flexcan the pointer of can hardware device. + * + * @return none + */ +void flexcan_mbm_init(struct flexcan_device *flexcan) +{ + struct can_hw_mb *hwmb; + int rx_mb, i; + + /* Set global mask to receive all messages */ + __raw_writel(0, flexcan->io_base + CAN_HW_REG_RXGMASK); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_RX14MASK); + __raw_writel(0, flexcan->io_base + CAN_HW_REG_RX15MASK); + + memset(flexcan->hwmb, 0, sizeof(*hwmb) * FLEXCAN_MAX_MB); + /* Set individual mask to receive all messages */ + memset(flexcan->rx_mask, 0, sizeof(unsigned int) * FLEXCAN_MAX_MB); + + if (flexcan->fifo) + rx_mb = FLEXCAN_MAX_FIFO_MB; + else + rx_mb = flexcan->maxmb - flexcan->xmit_maxmb; + + hwmb = flexcan->hwmb; + if (flexcan->fifo) { + unsigned long *id_table = flexcan->io_base + CAN_FIFO_BASE; + for (i = 0; i < rx_mb; i++) + id_table[i] = 0; + } else { + for (i = 0; i < rx_mb; i++) { + hwmb[i].mb_cs &= ~MB_CS_CODE_MASK; + hwmb[i].mb_cs |= CAN_MB_RX_EMPTY << MB_CS_CODE_OFFSET; + /* + * IDE bit can not control by mask registers + * So set message buffer to receive extend + * or standard message. + */ + if (flexcan->ext_msg && flexcan->std_msg) { + hwmb[i].mb_cs &= ~MB_CS_IDE_MASK; + hwmb[i].mb_cs |= (i & 1) << MB_CS_IDE_OFFSET; + } else { + if (flexcan->ext_msg) + hwmb[i].mb_cs |= 1 << MB_CS_IDE_OFFSET; + } + } + } + + for (; i <= flexcan->maxmb; i++) { + hwmb[i].mb_cs &= ~MB_CS_CODE_MASK; + hwmb[i].mb_cs |= CAN_MB_TX_INACTIVE << MB_CS_CODE_OFFSET; + } + + flexcan->xmit_mb = rx_mb; +} diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index 23786ee34bed..7056a7c17f6e 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -846,11 +846,8 @@ static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) return -EINVAL; if (!priv->phy) return -EINVAL; - if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) || - (cmd == SIOCSMIIREG)) - return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd); - return -EOPNOTSUPP; + return phy_mii_ioctl(priv->phy, ifr, cmd); } static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c index 8b0f50bbf3e5..4ea7141f525d 100644 --- a/drivers/net/dnet.c +++ b/drivers/net/dnet.c @@ -797,7 +797,7 @@ static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (!phydev) return -ENODEV; - return phy_mii_ioctl(phydev, if_mii(rq), cmd); + return phy_mii_ioctl(phydev, rq, cmd); } static void dnet_get_drvinfo(struct net_device *dev, diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 112c5aa9af7f..b08d2d3c1ab3 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -35,6 +35,7 @@ #define DRV_VERSION "1.01" #define SPI_OPLEN 1 +#define MAX_ENC_CARDS 1 #define ENC28J60_MSG_DEFAULT \ (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK) @@ -48,6 +49,18 @@ /* Max TX retries in case of collision as suggested by errata datasheet */ #define MAX_TX_RETRYCOUNT 16 +#ifdef CONFIG_ARCH_STMP3XXX +#include +#include +#include +#endif +#ifdef CONFIG_ARCH_MXS +#include +#include +#include +#define REGS_OCOTP_BASE IO_ADDRESS(OCOTP_PHYS_ADDR) +#endif + enum { RXFILTER_NORMAL, RXFILTER_MULTI, @@ -80,6 +93,71 @@ static struct { u32 msg_enable; } debug = { -1 }; +static int random_mac; /* = 0 */ +static char *mac[MAX_ENC_CARDS]; + +static int enc28j60_get_mac(unsigned char *dev_addr, int idx) +{ + int i, r; + char *p, *item; + unsigned long v; + unsigned char sv[10]; + + if (idx < 0) + idx = 0; + if (idx > MAX_ENC_CARDS) + return false; + + if (!mac[idx]) { +#if defined(CONFIG_ARCH_STMP3XXX) || defined(CONFIG_ARCH_MXS) + if (get_evk_board_version() >= 1) { + int mac1 , mac2 , retry = 0; + + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET); + while (__raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL) & + BM_OCOTP_CTRL_BUSY) { + msleep(10); + retry++; + if (retry > 10) + return false; + } + + mac1 = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(0)); + mac2 = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(1)); + if (MAX_ADDR_LEN < 6) + return false; + + dev_addr[0] = (mac1 >> 24) & 0xFF; + dev_addr[1] = (mac1 >> 16) & 0xFF; + dev_addr[2] = (mac1 >> 8) & 0xFF; + dev_addr[3] = (mac1 >> 0) & 0xFF; + dev_addr[4] = (mac2 >> 8) & 0xFF; + dev_addr[5] = (mac2 >> 0) & 0xFF; + return true; + } +#endif + return false; + } + + item = mac[idx]; + for (i = 0; i < MAX_ADDR_LEN; i++) { + p = strchr(item, ':'); + if (!p) + sprintf(sv, "0x%s", item); + else + sprintf(sv, "0x%*.*s", p - item, p-item, item); + r = strict_strtoul(sv, 0, &v); + dev_addr[i] = v; + if (p) + item = p + 1; + else + break; + if (r < 0) + return false; + } + return true; +} /* * SPI read buffer * wait for the SPI transfer and copy received data to destination @@ -89,10 +167,13 @@ spi_read_buf(struct enc28j60_net *priv, int len, u8 *data) { u8 *rx_buf = priv->spi_transfer_buf + 4; u8 *tx_buf = priv->spi_transfer_buf; - struct spi_transfer t = { - .tx_buf = tx_buf, - .rx_buf = rx_buf, - .len = SPI_OPLEN + len, + struct spi_transfer tt = { + .tx_buf = tx_buf, + .len = SPI_OPLEN, + }; + struct spi_transfer tr = { + .rx_buf = rx_buf, + .len = len, }; struct spi_message msg; int ret; @@ -101,10 +182,11 @@ spi_read_buf(struct enc28j60_net *priv, int len, u8 *data) tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */ spi_message_init(&msg); - spi_message_add_tail(&t, &msg); + spi_message_add_tail(&tt, &msg); + spi_message_add_tail(&tr, &msg); ret = spi_sync(priv->spi, &msg); if (ret == 0) { - memcpy(data, &rx_buf[SPI_OPLEN], len); + memcpy(data, rx_buf, len); ret = msg.status; } if (ret && netif_msg_drv(priv)) @@ -1107,8 +1189,24 @@ static int enc28j60_rx_interrupt(struct net_device *ndev) priv->max_pk_counter); } ret = pk_counter; - while (pk_counter-- > 0) + while (pk_counter-- > 0) { + if (!priv->full_duplex) { + /* + * This works only in HALF DUPLEX mode: + * when more than 2 packets are available, start + * transmission of 11111.. frame by setting + * FCON0 (0x01) in EFLOCON + * + * This bit can be cleared either explicitly, or by + * trasmitting the packet in enc28j60_hw_tx. + */ + if (pk_counter > 2) + locked_reg_bfset(priv, EFLOCON, 0x01); + if (pk_counter == 1) + locked_reg_bfclr(priv, EFLOCON, 0x01); + } enc28j60_hw_rx(ndev); + } return ret; } @@ -1192,7 +1290,7 @@ static void enc28j60_irq_work_handler(struct work_struct *work) printk(KERN_DEBUG DRV_NAME ": LateCollision TXErr (%d)\n", priv->tx_retry_count); - if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT) + if (priv->tx_retry_count++ > MAX_TX_RETRYCOUNT) locked_reg_bfset(priv, ECON1, ECON1_TXRTS); else @@ -1234,6 +1332,11 @@ static void enc28j60_irq_work_handler(struct work_struct *work) */ static void enc28j60_hw_tx(struct enc28j60_net *priv) { + if (!priv->tx_skb) { + enc28j60_tx_clear(priv->netdev, false); + return; + } + if (netif_msg_tx_queued(priv)) printk(KERN_DEBUG DRV_NAME ": Tx Packet Len:%d\n", priv->tx_skb->len); @@ -1545,6 +1648,7 @@ static int __devinit enc28j60_probe(struct spi_device *spi) struct net_device *dev; struct enc28j60_net *priv; int ret = 0; + int set; if (netif_msg_drv(&debug)) dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n", @@ -1578,7 +1682,11 @@ static int __devinit enc28j60_probe(struct spi_device *spi) ret = -EIO; goto error_irq; } - random_ether_addr(dev->dev_addr); + + /* need a counter here, to count instances of enc28j60 devices */ + set = enc28j60_get_mac(dev->dev_addr, -1); + if (!set || random_mac) + random_ether_addr(dev->dev_addr); enc28j60_set_hw_macaddr(dev); /* Board setup must set the relevant edge trigger type; @@ -1633,6 +1741,40 @@ static int __devexit enc28j60_remove(struct spi_device *spi) return 0; } +#ifdef CONFIG_PM +static int +enc28j60_suspend(struct spi_device *spi, pm_message_t state) +{ + struct enc28j60_net *priv = dev_get_drvdata(&spi->dev); + struct net_device *net_dev = priv ? priv->netdev : NULL; + + if (net_dev && netif_running(net_dev)) { + netif_stop_queue(net_dev); + netif_device_detach(net_dev); + disable_irq(spi->irq); + } + return 0; +} + +static int +enc28j60_resume(struct spi_device *spi) +{ + struct enc28j60_net *priv = dev_get_drvdata(&spi->dev); + struct net_device *net_dev = priv ? priv->netdev : NULL; + + if (net_dev && netif_running(net_dev)) { + enable_irq(spi->irq); + netif_device_attach(net_dev); + netif_start_queue(net_dev); + schedule_work(&priv->restart_work); + } + return 0; +} +#else +#define enc28j60_resume NULL +#define enc28j60_suspend NULL +#endif + static struct spi_driver enc28j60_driver = { .driver = { .name = DRV_NAME, @@ -1640,6 +1782,8 @@ static struct spi_driver enc28j60_driver = { }, .probe = enc28j60_probe, .remove = __devexit_p(enc28j60_remove), + .suspend = enc28j60_suspend, + .resume = enc28j60_resume, }; static int __init enc28j60_init(void) @@ -1662,5 +1806,7 @@ MODULE_DESCRIPTION(DRV_NAME " ethernet driver"); MODULE_AUTHOR("Claudio Lanconelli "); MODULE_LICENSE("GPL"); module_param_named(debug, debug.msg_enable, int, 0); +module_param(random_mac, int, 0444); +module_param_array(mac, charp, NULL, 0); MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)"); MODULE_ALIAS("spi:" DRV_NAME); diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index 6ed2df14ec84..8102f01e1cb6 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -734,7 +734,7 @@ static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) phy = priv->phy; } - return phy_mii_ioctl(phy, mdio, cmd); + return phy_mii_ioctl(phy, ifr, cmd); } static int ethoc_config(struct net_device *dev, struct ifmap *map) diff --git a/drivers/net/fec.c b/drivers/net/fec.c index edfff92a6d8e..d0e2e690b66e 100644 --- a/drivers/net/fec.c +++ b/drivers/net/fec.c @@ -17,6 +17,9 @@ * * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) * Copyright (c) 2004-2006 Macq Electronique SA. + * + * Support for FEC IEEE 1588. + * Copyright (C) 2010 Freescale Semiconductor, Inc. */ #include @@ -40,34 +43,29 @@ #include #include #include +#include #include #include #include #ifndef CONFIG_ARCH_MXC +#ifndef CONFIG_ARCH_MXS #include #include #endif +#endif #include "fec.h" +#include "fec_1588.h" -#ifdef CONFIG_ARCH_MXC -#include +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS) #define FEC_ALIGNMENT 0xf #else #define FEC_ALIGNMENT 0x3 #endif -/* - * Define the fixed address of the FEC hardware. - */ #if defined(CONFIG_M5272) - -static unsigned char fec_mac_default[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - /* * Some hardware gets it MAC address out of local flash memory. * if this is non-zero then assume it is the address to get MAC from. @@ -117,6 +115,15 @@ static unsigned char fec_mac_default[] = { #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ +#define FEC_ENET_TS_AVAIL ((uint)0x00010000) +#define FEC_ENET_TS_TIMER ((uint)0x00008000) + +#if defined(CONFIG_FEC_1588) && defined(CONFIG_ARCH_MX28) +#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | \ + FEC_ENET_TS_AVAIL | FEC_ENET_TS_TIMER) +#else +#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) +#endif /* The FEC stores dest/src/type, data, and checksum for receive packets. */ @@ -131,7 +138,8 @@ static unsigned char fec_mac_default[] = { * account when setting it. */ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) + defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ + defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS) #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) #else #define OPT_FRAME_SIZE 0 @@ -187,8 +195,18 @@ struct fec_enet_private { int index; int link; int full_duplex; + struct completion mdio_done; + + struct fec_ptp_private *ptp_priv; + uint ptimer_present; }; +/* + * Define the fixed address of the FEC hardware. + */ +static unsigned char fec_mac_default[ETH_ALEN]; +static struct mii_bus *fec_mii_bus; + static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); static void fec_enet_tx(struct net_device *dev); static void fec_enet_rx(struct net_device *dev); @@ -205,11 +223,24 @@ static void fec_stop(struct net_device *dev); #define FEC_MMFR_TA (2 << 16) #define FEC_MMFR_DATA(v) (v & 0xffff) -#define FEC_MII_TIMEOUT 10000 +#define FEC_MII_TIMEOUT 1000 /* Transmitter timeout */ #define TX_TIMEOUT (2 * HZ) +#ifdef CONFIG_ARCH_MXS +static void *swap_buffer(void *bufaddr, int len) +{ + int i; + unsigned int *buf = bufaddr; + + for (i = 0; i < (len + 3) / 4; i++, buf++) + *buf = __swab32(*buf); + + return bufaddr; +} +#endif + static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) { @@ -217,10 +248,12 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) struct bufdesc *bdp; void *bufaddr; unsigned short status; + unsigned long estatus; unsigned long flags; if (!fep->link) { /* Link is down or autonegotiation is in progress. */ + netif_stop_queue(dev); return NETDEV_TX_BUSY; } @@ -258,6 +291,21 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) bufaddr = fep->tx_bounce[index]; } + if (fep->ptimer_present) { + if (fec_ptp_do_txstamp(skb)) { + estatus = BD_ENET_TX_TS; + status |= BD_ENET_TX_PTP; + } else + estatus = 0; +#ifdef CONFIG_ENHANCED_BD + bdp->cbd_esc = (estatus | BD_ENET_TX_INT); + bdp->cbd_bdu = 0; +#endif + } + +#ifdef CONFIG_ARCH_MXS + swap_buffer(bufaddr, skb->len); +#endif /* Save skb pointer */ fep->tx_skbuff[fep->skb_cur] = skb; @@ -314,6 +362,7 @@ fec_enet_interrupt(int irq, void * dev_id) { struct net_device *dev = dev_id; struct fec_enet_private *fep = netdev_priv(dev); + struct fec_ptp_private *fpp = fep->ptp_priv; uint int_events; irqreturn_t ret = IRQ_NONE; @@ -334,6 +383,17 @@ fec_enet_interrupt(int irq, void * dev_id) ret = IRQ_HANDLED; fec_enet_tx(dev); } + + if (int_events & FEC_ENET_TS_TIMER) { + ret = IRQ_HANDLED; + if (fep->ptimer_present && fpp) + fpp->prtc++; + } + + if (int_events & FEC_ENET_MII) { + ret = IRQ_HANDLED; + complete(&fep->mdio_done); + } } while (int_events); return ret; @@ -344,11 +404,14 @@ static void fec_enet_tx(struct net_device *dev) { struct fec_enet_private *fep; + struct fec_ptp_private *fpp; struct bufdesc *bdp; unsigned short status; + unsigned long estatus; struct sk_buff *skb; fep = netdev_priv(dev); + fpp = fep->ptp_priv; spin_lock(&fep->hw_lock); bdp = fep->dirty_tx; @@ -388,6 +451,19 @@ fec_enet_tx(struct net_device *dev) if (status & BD_ENET_TX_DEF) dev->stats.collisions++; +#if defined(CONFIG_ENHANCED_BD) + if (fep->ptimer_present) { + estatus = bdp->cbd_esc; + if (estatus & BD_ENET_TX_TS) + fec_ptp_store_txstamp(fpp, skb, bdp); + } +#elif defined(CONFIG_IN_BAND) + if (fep->ptimer_present) { + if (status & BD_ENET_TX_PTP) + fec_ptp_store_txstamp(fpp, skb, bdp); + } +#endif + /* Free the sk buffer associated with this last transmit */ dev_kfree_skb_any(skb); fep->tx_skbuff[fep->skb_dirty] = NULL; @@ -421,6 +497,7 @@ static void fec_enet_rx(struct net_device *dev) { struct fec_enet_private *fep = netdev_priv(dev); + struct fec_ptp_private *fpp = fep->ptp_priv; struct bufdesc *bdp; unsigned short status; struct sk_buff *skb; @@ -483,7 +560,9 @@ fec_enet_rx(struct net_device *dev) dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, DMA_FROM_DEVICE); - +#ifdef CONFIG_ARCH_MXS + swap_buffer(data, pkt_len); +#endif /* This does 16 byte alignment, exactly what we need. * The packet length includes FCS, but we don't want to * include that when passing upstream as it messes up @@ -499,6 +578,9 @@ fec_enet_rx(struct net_device *dev) skb_reserve(skb, NET_IP_ALIGN); skb_put(skb, pkt_len - 4); /* Make room */ skb_copy_to_linear_data(skb, data, pkt_len - 4); + /* 1588 messeage TS handle */ + if (fep->ptimer_present) + fec_ptp_store_rxstamp(fpp, skb, bdp); skb->protocol = eth_type_trans(skb, dev); netif_rx(skb); } @@ -512,6 +594,11 @@ rx_processing_done: /* Mark the buffer empty */ status |= BD_ENET_RX_EMPTY; bdp->cbd_sc = status; +#ifdef CONFIG_ENHANCED_BD + bdp->cbd_esc = BD_ENET_RX_INT; + bdp->cbd_prot = 0; + bdp->cbd_bdu = 0; +#endif /* Update BD pointer to next entry */ if (status & BD_ENET_RX_WRAP) @@ -530,12 +617,13 @@ rx_processing_done: } /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_M5272 static void __inline__ fec_get_mac(struct net_device *dev) { struct fec_enet_private *fep = netdev_priv(dev); unsigned char *iap, tmpaddr[ETH_ALEN]; + static int index; +#ifdef CONFIG_M5272 if (FEC_FLASHMAC) { /* * Get MAC address from FLASH. @@ -548,19 +636,26 @@ static void __inline__ fec_get_mac(struct net_device *dev) if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) iap = fec_mac_default; - } else { - *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW); - *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16); + } +#else + if (is_valid_ether_addr(fec_mac_default)) { + iap = fec_mac_default; + } +#endif + else { + *((unsigned long *) &tmpaddr[0]) = be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); + *((unsigned short *) &tmpaddr[4]) = be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); iap = &tmpaddr[0]; } memcpy(dev->dev_addr, iap, ETH_ALEN); /* Adjust MAC if using default MAC address */ - if (iap == fec_mac_default) - dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; + if (iap == fec_mac_default) { + dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + index; + index++; +} } -#endif /* ------------------------------------------------------------------------- */ @@ -594,8 +689,15 @@ static void fec_enet_adjust_link(struct net_device *dev) /* Link on or off change */ if (phy_dev->link != fep->link) { fep->link = phy_dev->link; - if (phy_dev->link) + if (phy_dev->link) { fec_restart(dev, phy_dev->duplex); + + /* if link becomes up and tx be stopped, start it */ + if (netif_queue_stopped(dev)) { + netif_start_queue(dev); + netif_wake_queue(dev); + } + } else fec_stop(dev); status_change = 1; @@ -608,18 +710,13 @@ spin_unlock: phy_print_status(phy_dev); } -/* - * NOTE: a MII transaction is during around 25 us, so polling it... - */ static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) { struct fec_enet_private *fep = bus->priv; - int timeout = FEC_MII_TIMEOUT; + unsigned long time_left; fep->mii_timeout = 0; - - /* clear MII end of transfer bit*/ - writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); + init_completion(&fep->mdio_done); /* start a read op */ writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | @@ -627,15 +724,13 @@ static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); /* wait for end of transfer */ - while (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_MII)) { - cpu_relax(); - if (timeout-- < 0) { - fep->mii_timeout = 1; - printk(KERN_ERR "FEC: MDIO read timeout\n"); - return -ETIMEDOUT; - } + time_left = wait_for_completion_timeout(&fep->mdio_done, + usecs_to_jiffies(FEC_MII_TIMEOUT)); + if (time_left == 0) { + fep->mii_timeout = 1; + printk(KERN_ERR "FEC: MDIO read timeout\n"); + return -ETIMEDOUT; } - /* return value */ return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); } @@ -644,27 +739,24 @@ static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) { struct fec_enet_private *fep = bus->priv; - int timeout = FEC_MII_TIMEOUT; + unsigned long time_left; fep->mii_timeout = 0; + init_completion(&fep->mdio_done); - /* clear MII end of transfer bit*/ - writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); - - /* start a read op */ - writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | + /* start a write op */ + writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | FEC_MMFR_TA | FEC_MMFR_DATA(value), fep->hwp + FEC_MII_DATA); /* wait for end of transfer */ - while (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_MII)) { - cpu_relax(); - if (timeout-- < 0) { - fep->mii_timeout = 1; - printk(KERN_ERR "FEC: MDIO write timeout\n"); - return -ETIMEDOUT; - } + time_left = wait_for_completion_timeout(&fep->mdio_done, + usecs_to_jiffies(FEC_MII_TIMEOUT)); + if (time_left == 0) { + fep->mii_timeout = 1; + printk(KERN_ERR "FEC: MDIO write timeout\n"); + return -ETIMEDOUT; } return 0; @@ -680,12 +772,15 @@ static int fec_enet_mii_probe(struct net_device *dev) struct fec_enet_private *fep = netdev_priv(dev); struct phy_device *phy_dev = NULL; int phy_addr; + int fec_index = fep->pdev->id > 0 ? fep->pdev->id : 0; fep->phy_dev = NULL; - /* find the first phy */ + /* find the phy, assuming fec index corresponds to addr */ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { if (fep->mii_bus->phy_map[phy_addr]) { + if (fec_index--) + continue; phy_dev = fep->mii_bus->phy_map[phy_addr]; break; } @@ -699,7 +794,7 @@ static int fec_enet_mii_probe(struct net_device *dev) /* attach the mac to the phy */ phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &fec_enet_adjust_link, 0, - PHY_INTERFACE_MODE_MII); + fep->phy_interface); if (IS_ERR(phy_dev)) { printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); return PTR_ERR(phy_dev); @@ -721,7 +816,7 @@ static int fec_enet_mii_probe(struct net_device *dev) return 0; } -static int fec_enet_mii_init(struct platform_device *pdev) +static struct mii_bus *fec_enet_mii_init(struct platform_device *pdev) { struct net_device *dev = platform_get_drvdata(pdev); struct fec_enet_private *fep = netdev_priv(dev); @@ -733,6 +828,10 @@ static int fec_enet_mii_init(struct platform_device *pdev) * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) */ fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; +#ifdef CONFIG_ARCH_MXS + /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it*/ + fep->phy_speed <<= 2; +#endif writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); fep->mii_bus = mdiobus_alloc(); @@ -763,14 +862,14 @@ static int fec_enet_mii_init(struct platform_device *pdev) if (mdiobus_register(fep->mii_bus)) goto err_out_free_mdio_irq; - return 0; + return fep->mii_bus; err_out_free_mdio_irq: kfree(fep->mii_bus->irq); err_out_free_mdiobus: mdiobus_free(fep->mii_bus); err_out: - return err; + return ERR_PTR(err); } static void fec_enet_mii_remove(struct fec_enet_private *fep) @@ -834,7 +933,7 @@ static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (!phydev) return -ENODEV; - return phy_mii_ioctl(phydev, if_mii(rq), cmd); + return phy_mii_ioctl(phydev, rq, cmd); } static void fec_enet_free_buffers(struct net_device *dev) @@ -880,6 +979,9 @@ static int fec_enet_alloc_buffers(struct net_device *dev) bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); bdp->cbd_sc = BD_ENET_RX_EMPTY; +#ifdef CONFIG_ENHANCED_BD + bdp->cbd_esc = BD_ENET_RX_INT; +#endif bdp++; } @@ -893,6 +995,9 @@ static int fec_enet_alloc_buffers(struct net_device *dev) bdp->cbd_sc = 0; bdp->cbd_bufaddr = 0; +#ifdef CONFIG_ENHANCED_BD + bdp->cbd_esc = BD_ENET_TX_INT; +#endif bdp++; } @@ -912,7 +1017,7 @@ fec_enet_open(struct net_device *dev) /* I should reset the ring buffers here, but I don't yet know * a simple way to do that. */ - + clk_enable(fep->clk); ret = fec_enet_alloc_buffers(dev); if (ret) return ret; @@ -924,7 +1029,7 @@ fec_enet_open(struct net_device *dev) return ret; } phy_start(fep->phy_dev); - netif_start_queue(dev); + fec_restart(dev, fep->phy_dev->duplex); fep->opened = 1; return 0; } @@ -936,13 +1041,14 @@ fec_enet_close(struct net_device *dev) /* Don't know what to do yet. */ fep->opened = 0; - netif_stop_queue(dev); fec_stop(dev); - if (fep->phy_dev) + if (fep->phy_dev) { + phy_stop(fep->phy_dev); phy_disconnect(fep->phy_dev); - + } fec_enet_free_buffers(dev); + clk_disable(fep->clk); return 0; } @@ -1058,6 +1164,31 @@ static const struct net_device_ops fec_netdev_ops = { .ndo_do_ioctl = fec_enet_ioctl, }; +static int fec_mac_addr_setup(char *mac_addr) +{ + char *ptr, *p = mac_addr; + unsigned long tmp; + int i = 0, ret = 0; + + while (p && (*p) && i < 6) { + ptr = strchr(p, ':'); + if (ptr) + *ptr++ = '\0'; + + if (strlen(p)) { + ret = strict_strtoul(p, 16, &tmp); + if (ret < 0 || tmp > 0xff) + break; + fec_mac_default[i++] = tmp; + } + p = ptr; + } + + return 0; +} + +__setup("fec_mac=", fec_mac_addr_setup); + /* * XXX: We need to clean up on failure exits here. * @@ -1085,21 +1216,7 @@ static int fec_enet_init(struct net_device *dev, int index) fep->netdev = dev; /* Set the Ethernet address */ -#ifdef CONFIG_M5272 fec_get_mac(dev); -#else - { - unsigned long l; - l = readl(fep->hwp + FEC_ADDR_LOW); - dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24); - dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16); - dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8); - dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0); - l = readl(fep->hwp + FEC_ADDR_HIGH); - dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24); - dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16); - } -#endif /* Set receive and transmit descriptor base. */ fep->rx_bd_base = cbd_base; @@ -1151,11 +1268,20 @@ fec_restart(struct net_device *dev, int duplex) { struct fec_enet_private *fep = netdev_priv(dev); int i; + uint ret = 0; + u32 temp_mac[2]; + unsigned long reg; + int val; /* Whack a reset. We should wait for this. */ writel(1, fep->hwp + FEC_ECNTRL); udelay(10); + /* Reset fec will reset MAC to zero, reconfig it again */ + memcpy(&temp_mac, dev->dev_addr, ETH_ALEN); + writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); + writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); + /* Clear any outstanding interrupt. */ writel(0xffc00000, fep->hwp + FEC_IEVENT); @@ -1199,9 +1325,46 @@ fec_restart(struct net_device *dev, int duplex) } fep->full_duplex = duplex; +#ifdef CONFIG_ARCH_MXS + + reg = readl(fep->hwp + FEC_R_CNTRL); + + /* Enable flow control and length check */ + reg |= (0x40000000 | 0x00000020); + + /* Check MII or RMII */ + if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) + reg |= 0x00000100; + else + reg &= ~0x00000100; + + /* Check 10M or 100M */ + if (fep->phy_dev && fep->phy_dev->speed == SPEED_100) + reg &= ~0x00000200; /* 100M */ + else + reg |= 0x00000200; /* 10M */ + + writel(reg, fep->hwp + FEC_R_CNTRL); + +#endif /* Set MII speed */ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); + if (fep->ptimer_present) { + /* Set Timer count */ + ret = fec_ptp_start(fep->ptp_priv); + if (ret) { + fep->ptimer_present = 0; + reg = 0x0; + } else +#ifdef CONFIG_ARCH_MX28 + reg = 0x00000010; +#else + reg = 0x0; +#endif + } else + reg = 0x0; + #ifdef FEC_MIIGSK_ENR if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { /* disable the gasket and wait */ @@ -1210,7 +1373,10 @@ fec_restart(struct net_device *dev, int duplex) udelay(1); /* configure the gasket: RMII, 50 MHz, no loopback, no echo */ - writel(1, fep->hwp + FEC_MIIGSK_CFGR); + val = 1; + if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) + val |= 1 << 6; + writel(val, fep->hwp + FEC_MIIGSK_CFGR); /* re-enable the gasket */ writel(2, fep->hwp + FEC_MIIGSK_ENR); @@ -1218,11 +1384,12 @@ fec_restart(struct net_device *dev, int duplex) #endif /* And last, enable the transmit and receive processing */ - writel(2, fep->hwp + FEC_ECNTRL); + reg |= 0x00000002; + writel(reg, fep->hwp + FEC_ECNTRL); writel(0, fep->hwp + FEC_R_DES_ACTIVE); /* Enable interrupts we wish to service */ - writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->hwp + FEC_IMASK); + writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); } static void @@ -1242,10 +1409,24 @@ fec_stop(struct net_device *dev) writel(1, fep->hwp + FEC_ECNTRL); udelay(10); +#ifdef CONFIG_ARCH_MXS + /* Check MII or RMII */ + if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) + writel(readl(fep->hwp + FEC_R_CNTRL) | 0x100, + fep->hwp + FEC_R_CNTRL); + else + writel(readl(fep->hwp + FEC_R_CNTRL) & ~0x100, + fep->hwp + FEC_R_CNTRL); +#endif /* Clear outstanding MII command interrupts. */ writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); - writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); + if (fep->ptimer_present) + fec_ptp_stop(fep->ptp_priv); + writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + + netif_stop_queue(dev); + fep->link = 0; } static int __devinit @@ -1290,6 +1471,9 @@ fec_probe(struct platform_device *pdev) if (pdata) fep->phy_interface = pdata->phy; + if (pdata && !is_valid_ether_addr(fec_mac_default)) + memcpy(fec_mac_default, pdata->mac, sizeof(fec_mac_default)); + /* This device has up to three irqs on some platforms */ for (i = 0; i < 3; i++) { irq = platform_get_irq(pdev, i); @@ -1313,22 +1497,63 @@ fec_probe(struct platform_device *pdev) } clk_enable(fep->clk); + /* PHY reset should be done during clock on */ + if (pdata && pdata->init) + ret = pdata->init(); + if (ret) + goto failed_platform_init; + /* + * The priority for getting MAC address is: + * (1) kernel command line fec_mac = xx:xx:xx... + * (2) platform data mac field got from fuse etc + * (3) bootloader set the FEC mac register + */ + + if (pdata && !is_valid_ether_addr(fec_mac_default) && + pdata->mac && is_valid_ether_addr(pdata->mac)) + memcpy(fec_mac_default, pdata->mac, + sizeof(fec_mac_default)); + ret = fec_enet_init(ndev, 0); if (ret) goto failed_init; - ret = fec_enet_mii_init(pdev); - if (ret) + if (pdev->id == 0) { + fec_mii_bus = fec_enet_mii_init(pdev); + if (IS_ERR(fec_mii_bus)) { + ret = -ENOMEM; goto failed_mii_init; + } + } else { + fep->mii_bus = fec_mii_bus; + } + + if (fec_ptp_malloc_priv(&(fep->ptp_priv))) { + if (fep->ptp_priv) { + fep->ptp_priv->hwp = fep->hwp; + ret = fec_ptp_init(fep->ptp_priv, pdev->id); + if (ret) + printk(KERN_WARNING + "IEEE1588: ptp-timer is unavailable\n"); + else + fep->ptimer_present = 1; + } else + printk(KERN_ERR "IEEE1588: failed to malloc memory\n"); + } ret = register_netdev(ndev); if (ret) goto failed_register; + clk_disable(fep->clk); + return 0; failed_register: fec_enet_mii_remove(fep); + if (fep->ptimer_present) + fec_ptp_cleanup(fep->ptp_priv); + kfree(fep->ptp_priv); failed_mii_init: failed_init: clk_disable(fep->clk); @@ -1342,6 +1567,7 @@ failed_clk: failed_irq: iounmap((void __iomem *)ndev->base_addr); failed_ioremap: +failed_platform_init: free_netdev(ndev); return ret; @@ -1352,14 +1578,20 @@ fec_drv_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct fec_enet_private *fep = netdev_priv(ndev); + struct fec_platform_data *pdata = pdev->dev.platform_data; platform_set_drvdata(pdev, NULL); fec_stop(ndev); fec_enet_mii_remove(fep); + if (pdata && pdata->uninit) + pdata->uninit(); clk_disable(fep->clk); clk_put(fep->clk); iounmap((void __iomem *)ndev->base_addr); + if (fep->ptimer_present) + fec_ptp_cleanup(fep->ptp_priv); + kfree(fep->ptp_priv); unregister_netdev(ndev); free_netdev(ndev); return 0; @@ -1373,9 +1605,12 @@ fec_suspend(struct platform_device *dev, pm_message_t state) if (ndev) { fep = netdev_priv(ndev); - if (netif_running(ndev)) - fec_enet_close(ndev); - clk_disable(fep->clk); + if (netif_running(ndev)) { + netif_device_detach(ndev); + fec_stop(ndev); + netif_carrier_off(ndev); + clk_disable(fep->clk); + } } return 0; } @@ -1388,9 +1623,11 @@ fec_resume(struct platform_device *dev) if (ndev) { fep = netdev_priv(ndev); - clk_enable(fep->clk); - if (netif_running(ndev)) - fec_enet_open(ndev); + if (netif_running(ndev)) { + clk_enable(fep->clk); + fec_restart(ndev, fep->full_duplex); + netif_device_attach(ndev); + } } return 0; } diff --git a/drivers/net/fec.h b/drivers/net/fec.h index 2c48b25668d5..0bd534dfcbd9 100644 --- a/drivers/net/fec.h +++ b/drivers/net/fec.h @@ -14,7 +14,8 @@ /****************************************************************************/ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) + defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ + defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS) /* * Just figures, Motorola would have to change the offsets for * registers in the same peripheral device on different models @@ -46,6 +47,15 @@ #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ +/* Define the FEC 1588 registers offset */ +#define FEC_ATIME_CTRL 0x400 +#define FEC_ATIME 0x404 +#define FEC_ATIME_EVT_OFFSET 0x408 +#define FEC_ATIME_EVT_PERIOD 0x40c +#define FEC_ATIME_CORR 0x410 +#define FEC_ATIME_INC 0x414 +#define FEC_TS_TIMESTAMP 0x418 + #else #define FEC_ECNTRL 0x000 /* Ethernet control reg */ @@ -74,15 +84,25 @@ #endif /* CONFIG_M5272 */ +#if defined(CONFIG_ARCH_MX28) && defined(CONFIG_FEC_1588) +#define CONFIG_ENHANCED_BD +#endif /* * Define the buffer descriptor structure. */ -#ifdef CONFIG_ARCH_MXC +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS) struct bufdesc { unsigned short cbd_datlen; /* Data length */ unsigned short cbd_sc; /* Control and status info */ unsigned long cbd_bufaddr; /* Buffer address */ +#ifdef CONFIG_ENHANCED_BD + unsigned long cbd_esc; + unsigned long cbd_prot; + unsigned long cbd_bdu; + unsigned long ts; + unsigned short res0[4]; +#endif }; #else struct bufdesc { @@ -125,6 +145,9 @@ struct bufdesc { #define BD_ENET_RX_CL ((ushort)0x0001) #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ +#define BD_ENET_RX_INT 0x00800000 +#define BD_ENET_RX_PTP ((ushort)0x0400) + /* Buffer descriptor control/status used by Ethernet transmit. */ #define BD_ENET_TX_READY ((ushort)0x8000) @@ -142,6 +165,8 @@ struct bufdesc { #define BD_ENET_TX_CSL ((ushort)0x0001) #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ +#define BD_ENET_TX_INT 0x40000000 +#define BD_ENET_TX_PTP ((ushort)0x0100) /****************************************************************************/ #endif /* FEC_H */ diff --git a/drivers/net/fec_1588.c b/drivers/net/fec_1588.c new file mode 100644 index 000000000000..0b53cb52991d --- /dev/null +++ b/drivers/net/fec_1588.c @@ -0,0 +1,796 @@ +/* + * drivers/net/fec_1588.c + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2009 IXXAT Automation, GmbH + * + * FEC Ethernet Driver -- IEEE 1588 interface functionality + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "fec.h" +#include "fec_1588.h" + +static DECLARE_WAIT_QUEUE_HEAD(ptp_rx_ts_wait); +static DECLARE_WAIT_QUEUE_HEAD(ptp_tx_ts_wait); +#define PTP_GET_RX_TIMEOUT (HZ/10) +#define PTP_GET_TX_TIMEOUT (HZ/100) + +static struct fec_ptp_private *ptp_private[2]; + +/* Alloc the ring resource */ +static int fec_ptp_init_circ(struct circ_buf *ptp_buf, int size) +{ + ptp_buf->buf = vmalloc(size * sizeof(struct fec_ptp_data_t)); + + if (!ptp_buf->buf) + return 1; + ptp_buf->head = 0; + ptp_buf->tail = 0; + + return 0; +} + +static inline int fec_ptp_calc_index(int size, int curr_index, int offset) +{ + return (curr_index + offset) % size; +} + +static int fec_ptp_is_empty(struct circ_buf *buf) +{ + return (buf->head == buf->tail); +} + +static int fec_ptp_nelems(struct circ_buf *buf, int size) +{ + const int front = buf->head; + const int end = buf->tail; + int n_items; + + if (end > front) + n_items = end - front; + else if (end < front) + n_items = size - (front - end); + else + n_items = 0; + + return n_items; +} + +static int fec_ptp_is_full(struct circ_buf *buf, int size) +{ + if (fec_ptp_nelems(buf, size) == + (size - 1)) + return 1; + else + return 0; +} + +static int fec_ptp_insert(struct circ_buf *ptp_buf, + struct fec_ptp_data_t *data, + struct fec_ptp_private *priv, + int size) +{ + struct fec_ptp_data_t *tmp; + + if (fec_ptp_is_full(ptp_buf, size)) + return 1; + + spin_lock(&priv->ptp_lock); + tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + ptp_buf->tail; + + tmp->key = data->key; + memcpy(tmp->spid, data->spid, 10); + tmp->ts_time.sec = data->ts_time.sec; + tmp->ts_time.nsec = data->ts_time.nsec; + + ptp_buf->tail = fec_ptp_calc_index(size, ptp_buf->tail, 1); + spin_unlock(&priv->ptp_lock); + + return 0; +} + +static int fec_ptp_find_and_remove(struct circ_buf *ptp_buf, + struct fec_ptp_data_t *data, + struct fec_ptp_private *priv, + int size) +{ + int i; + int end = ptp_buf->tail; + unsigned long flags; + struct fec_ptp_data_t *tmp; + + if (fec_ptp_is_empty(ptp_buf)) + return 1; + + i = ptp_buf->head; + while (i != end) { + tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + i; + if (tmp->key == data->key && + !memcmp(tmp->spid, data->spid, 10)) + break; + i = fec_ptp_calc_index(size, i, 1); + } + + spin_lock_irqsave(&priv->ptp_lock, flags); + if (i == end) { + ptp_buf->head = end; + spin_unlock_irqrestore(&priv->ptp_lock, flags); + return 1; + } + + data->ts_time.sec = tmp->ts_time.sec; + data->ts_time.nsec = tmp->ts_time.nsec; + + ptp_buf->head = fec_ptp_calc_index(size, i, 1); + spin_unlock_irqrestore(&priv->ptp_lock, flags); + + return 0; +} + +/* 1588 Module intialization */ +int fec_ptp_start(struct fec_ptp_private *priv) +{ + struct fec_ptp_private *fpp = priv; + + /* Select 1588 Timer source and enable module for starting Tmr Clock * + * When enable both FEC0 and FEC1 1588 Timer in the same time, * + * enable FEC1 timer's slave mode. */ + if ((fpp == ptp_private[0]) || !(ptp_private[0]->ptp_active)) { + writel(FEC_T_CTRL_RESTART, fpp->hwp + FEC_ATIME_CTRL); + writel(FEC_T_INC_40MHZ << FEC_T_INC_OFFSET, + fpp->hwp + FEC_ATIME_INC); + writel(FEC_T_PERIOD_ONE_SEC, fpp->hwp + FEC_ATIME_EVT_PERIOD); + /* start counter */ + writel(FEC_T_CTRL_PERIOD_RST | FEC_T_CTRL_ENABLE, + fpp->hwp + FEC_ATIME_CTRL); + fpp->ptp_slave = 0; + fpp->ptp_active = 1; + /* if the FEC1 timer was enabled, set it to slave mode */ + if ((fpp == ptp_private[0]) && (ptp_private[1]->ptp_active)) { + writel(0, ptp_private[1]->hwp + FEC_ATIME_CTRL); + fpp->prtc = ptp_private[1]->prtc; + writel(FEC_T_CTRL_RESTART, + ptp_private[1]->hwp + FEC_ATIME_CTRL); + writel(FEC_T_INC_40MHZ << FEC_T_INC_OFFSET, + ptp_private[1]->hwp + FEC_ATIME_INC); + /* Set the timer as slave mode */ + writel(FEC_T_CTRL_SLAVE, + ptp_private[1]->hwp + FEC_ATIME_CTRL); + ptp_private[1]->ptp_slave = 1; + ptp_private[1]->ptp_active = 1; + } + } else { + writel(FEC_T_INC_40MHZ << FEC_T_INC_OFFSET, + fpp->hwp + FEC_ATIME_INC); + /* Set the timer as slave mode */ + writel(FEC_T_CTRL_SLAVE, fpp->hwp + FEC_ATIME_CTRL); + fpp->ptp_slave = 1; + fpp->ptp_active = 1; + } + + return 0; +} + +/* Cleanup routine for 1588 module. + * When PTP is disabled this routing is called */ +void fec_ptp_stop(struct fec_ptp_private *priv) +{ + struct fec_ptp_private *fpp = priv; + + writel(0, fpp->hwp + FEC_ATIME_CTRL); + writel(FEC_T_CTRL_RESTART, fpp->hwp + FEC_ATIME_CTRL); + priv->ptp_active = 0; + priv->ptp_slave = 0; + +} + +static void fec_get_curr_cnt(struct fec_ptp_private *priv, + struct ptp_rtc_time *curr_time) +{ + u32 tempval; + struct fec_ptp_private *tmp_priv; + + if (!priv->ptp_slave) + tmp_priv = priv; + else + tmp_priv = ptp_private[0]; + + writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL); + writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL); + curr_time->rtc_time.nsec = readl(priv->hwp + FEC_ATIME); + curr_time->rtc_time.sec = tmp_priv->prtc; + + writel(FEC_T_CTRL_CAPTURE, priv->hwp + FEC_ATIME_CTRL); + tempval = readl(priv->hwp + FEC_ATIME); + if (tempval < curr_time->rtc_time.nsec) { + curr_time->rtc_time.nsec = tempval; + curr_time->rtc_time.sec = tmp_priv->prtc; + } +} + +/* Set the 1588 timer counter registers */ +static void fec_set_1588cnt(struct fec_ptp_private *priv, + struct ptp_rtc_time *fec_time) +{ + u32 tempval; + unsigned long flags; + struct fec_ptp_private *tmp_priv; + + if (!priv->ptp_slave) + tmp_priv = priv; + else + tmp_priv = ptp_private[0]; + + spin_lock_irqsave(&priv->cnt_lock, flags); + tmp_priv->prtc = fec_time->rtc_time.sec; + + tempval = fec_time->rtc_time.nsec; + writel(tempval, tmp_priv->hwp + FEC_ATIME); + spin_unlock_irqrestore(&priv->cnt_lock, flags); +} + +/* Set the BD to ptp */ +int fec_ptp_do_txstamp(struct sk_buff *skb) +{ + struct iphdr *iph; + struct udphdr *udph; + + if (skb->len > 44) { + /* Check if port is 319 for PTP Event, and check for UDP */ + iph = ip_hdr(skb); + if (iph == NULL || iph->protocol != FEC_PACKET_TYPE_UDP) + return 0; + + udph = udp_hdr(skb); + if (udph != NULL && ntohs(udph->dest) == 319) + return 1; + } + + return 0; +} + +void fec_ptp_store_txstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp) +{ + int msg_type, seq_id, control; + struct fec_ptp_data_t tmp_tx_time; + struct fec_ptp_private *fpp; + unsigned char *sp_id; + unsigned short portnum; + + if (!priv->ptp_slave) + fpp = priv; + else + fpp = ptp_private[0]; + + seq_id = *((u16 *)(skb->data + FEC_PTP_SEQ_ID_OFFS)); + control = *((u8 *)(skb->data + FEC_PTP_CTRL_OFFS)); + sp_id = skb->data + FEC_PTP_SPORT_ID_OFFS; + portnum = ntohs(*((unsigned short *)(sp_id + 8))); + + tmp_tx_time.key = ntohs(seq_id); + memcpy(tmp_tx_time.spid, sp_id, 8); + memcpy(tmp_tx_time.spid + 8, (unsigned char *)&portnum, 2); + tmp_tx_time.ts_time.sec = fpp->prtc; + tmp_tx_time.ts_time.nsec = bdp->ts; + + switch (control) { + + case PTP_MSG_SYNC: + fec_ptp_insert(&(priv->tx_time_sync), &tmp_tx_time, priv, + DEFAULT_PTP_TX_BUF_SZ); + break; + + case PTP_MSG_DEL_REQ: + fec_ptp_insert(&(priv->tx_time_del_req), &tmp_tx_time, priv, + DEFAULT_PTP_TX_BUF_SZ); + break; + + /* clear transportSpecific field*/ + case PTP_MSG_ALL_OTHER: + msg_type = (*((u8 *)(skb->data + + FEC_PTP_MSG_TYPE_OFFS))) & 0x0F; + switch (msg_type) { + case PTP_MSG_P_DEL_REQ: + fec_ptp_insert(&(priv->tx_time_pdel_req), &tmp_tx_time, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + fec_ptp_insert(&(priv->tx_time_pdel_resp), &tmp_tx_time, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + default: + break; + } + break; + default: + break; + } + + wake_up_interruptible(&ptp_tx_ts_wait); +} + +void fec_ptp_store_rxstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp) +{ + int msg_type, seq_id, control; + struct fec_ptp_data_t tmp_rx_time; + struct fec_ptp_private *fpp; + struct iphdr *iph; + struct udphdr *udph; + unsigned char *sp_id; + unsigned short portnum; + + if (!priv->ptp_slave) + fpp = priv; + else + fpp = ptp_private[0]; + + /* Check for UDP, and Check if port is 319 for PTP Event */ + iph = (struct iphdr *)(skb->data + FEC_PTP_IP_OFFS); + if (iph->protocol != FEC_PACKET_TYPE_UDP) + return; + + udph = (struct udphdr *)(skb->data + FEC_PTP_UDP_OFFS); + if (ntohs(udph->dest) != 319) + return; + + seq_id = *((u16 *)(skb->data + FEC_PTP_SEQ_ID_OFFS)); + control = *((u8 *)(skb->data + FEC_PTP_CTRL_OFFS)); + sp_id = skb->data + FEC_PTP_SPORT_ID_OFFS; + portnum = ntohs(*((unsigned short *)(sp_id + 8))); + + tmp_rx_time.key = ntohs(seq_id); + memcpy(tmp_rx_time.spid, sp_id, 8); + memcpy(tmp_rx_time.spid + 8, (unsigned char *)&portnum, 2); + tmp_rx_time.ts_time.sec = fpp->prtc; + tmp_rx_time.ts_time.nsec = bdp->ts; + + switch (control) { + + case PTP_MSG_SYNC: + fec_ptp_insert(&(priv->rx_time_sync), &tmp_rx_time, priv, + DEFAULT_PTP_RX_BUF_SZ); + break; + + case PTP_MSG_DEL_REQ: + fec_ptp_insert(&(priv->rx_time_del_req), &tmp_rx_time, priv, + DEFAULT_PTP_RX_BUF_SZ); + break; + + /* clear transportSpecific field*/ + case PTP_MSG_ALL_OTHER: + msg_type = (*((u8 *)(skb->data + + FEC_PTP_MSG_TYPE_OFFS))) & 0x0F; + switch (msg_type) { + case PTP_MSG_P_DEL_REQ: + fec_ptp_insert(&(priv->rx_time_pdel_req), &tmp_rx_time, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + fec_ptp_insert(&(priv->rx_time_pdel_resp), &tmp_rx_time, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + default: + break; + } + break; + default: + break; + } + + wake_up_interruptible(&ptp_rx_ts_wait); +} + +static uint8_t fec_get_tx_timestamp(struct fec_ptp_private *priv, + struct ptp_ts_data *pts, + struct ptp_time *tx_time) +{ + struct fec_ptp_data_t tmp; + int flag; + u8 mode; + + tmp.key = pts->seq_id; + memcpy(tmp.spid, pts->spid, 10); + mode = pts->message_type; + switch (mode) { + case PTP_MSG_SYNC: + flag = fec_ptp_find_and_remove(&(priv->tx_time_sync), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->tx_time_del_req), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + + case PTP_MSG_P_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->tx_time_pdel_req), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + flag = fec_ptp_find_and_remove(&(priv->tx_time_pdel_resp), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + + default: + flag = 1; + printk(KERN_ERR "ERROR\n"); + break; + } + + if (!flag) { + tx_time->sec = tmp.ts_time.sec; + tx_time->nsec = tmp.ts_time.nsec; + return 0; + } else { + wait_event_interruptible_timeout(ptp_tx_ts_wait, 0, + PTP_GET_TX_TIMEOUT); + + switch (mode) { + case PTP_MSG_SYNC: + flag = fec_ptp_find_and_remove(&(priv->tx_time_sync), + &tmp, priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->tx_time_del_req), + &tmp, priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_P_DEL_REQ: + flag = fec_ptp_find_and_remove( + &(priv->tx_time_pdel_req), &tmp, priv, + DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + flag = fec_ptp_find_and_remove( + &(priv->tx_time_pdel_resp), &tmp, priv, + DEFAULT_PTP_TX_BUF_SZ); + break; + } + + if (flag == 0) { + tx_time->sec = tmp.ts_time.sec; + tx_time->nsec = tmp.ts_time.nsec; + return 0; + } + + return -1; + } +} + +static uint8_t fec_get_rx_timestamp(struct fec_ptp_private *priv, + struct ptp_ts_data *pts, + struct ptp_time *rx_time) +{ + struct fec_ptp_data_t tmp; + int flag; + u8 mode; + + tmp.key = pts->seq_id; + memcpy(tmp.spid, pts->spid, 10); + mode = pts->message_type; + switch (mode) { + case PTP_MSG_SYNC: + flag = fec_ptp_find_and_remove(&(priv->rx_time_sync), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->rx_time_del_req), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + + case PTP_MSG_P_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_req), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_resp), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + + default: + flag = 1; + printk(KERN_ERR "ERROR\n"); + break; + } + + if (!flag) { + rx_time->sec = tmp.ts_time.sec; + rx_time->nsec = tmp.ts_time.nsec; + return 0; + } else { + wait_event_interruptible_timeout(ptp_rx_ts_wait, 0, + PTP_GET_RX_TIMEOUT); + + switch (mode) { + case PTP_MSG_SYNC: + flag = fec_ptp_find_and_remove(&(priv->rx_time_sync), + &tmp, priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_DEL_REQ: + flag = fec_ptp_find_and_remove( + &(priv->rx_time_del_req), &tmp, priv, + DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_P_DEL_REQ: + flag = fec_ptp_find_and_remove( + &(priv->rx_time_pdel_req), &tmp, priv, + DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + flag = fec_ptp_find_and_remove( + &(priv->rx_time_pdel_resp), &tmp, priv, + DEFAULT_PTP_RX_BUF_SZ); + break; + } + + if (flag == 0) { + rx_time->sec = tmp.ts_time.sec; + rx_time->nsec = tmp.ts_time.nsec; + return 0; + } + + return -1; + } +} + +static void fec_handle_ptpdrift(struct ptp_set_comp *comp, + struct ptp_time_correct *ptc) +{ + u32 ndrift; + u32 i; + u32 tmp_current, tmp_winner; + + ndrift = comp->drift; + + if (ndrift == 0) { + ptc->corr_inc = 0; + ptc->corr_period = 0; + return; + } else if (ndrift >= FEC_ATIME_40MHZ) { + ptc->corr_inc = (u32)(ndrift / FEC_ATIME_40MHZ); + ptc->corr_period = 1; + return; + } else if ((ndrift < FEC_ATIME_40MHZ) && (comp->o_ops == 0)) { + tmp_winner = 0xFFFFFFFF; + for (i = 1; i < 25; i++) { + tmp_current = (FEC_ATIME_40MHZ * i) % ndrift; + if (tmp_current == 0) { + ptc->corr_inc = i; + ptc->corr_period = (u32)((FEC_ATIME_40MHZ * i) + / ndrift); + break; + } else if (tmp_current < tmp_winner) { + ptc->corr_inc = i; + ptc->corr_period = (u32)((FEC_ATIME_40MHZ * i) + / ndrift); + tmp_winner = tmp_current; + } + } + } else if ((ndrift < FEC_ATIME_40MHZ) && (comp->o_ops == 1)) { + tmp_winner = 0xFFFFFFFF; + for (i = 1; i < 100; i++) { + tmp_current = (FEC_ATIME_40MHZ * i) % ndrift; + if (tmp_current == 0) { + ptc->corr_inc = i; + ptc->corr_period = (u32)((FEC_ATIME_40MHZ * i) + / ndrift); + break; + } else if (tmp_current < tmp_winner) { + ptc->corr_inc = i; + ptc->corr_period = (u32)((FEC_ATIME_40MHZ * i) + / ndrift); + tmp_winner = tmp_current; + } + } + } + +} + +static void fec_set_drift(struct fec_ptp_private *priv, + struct ptp_set_comp *comp) +{ + struct ptp_time_correct tc; + struct fec_ptp_private *fpp; + u32 tmp, corr_ns; + + memset(&tc, 0, sizeof(struct ptp_time_correct)); + fec_handle_ptpdrift(comp, &tc); + if (tc.corr_inc == 0) + return; + + if (comp->o_ops == TRUE) + corr_ns = FEC_T_INC_40MHZ + tc.corr_inc; + else + corr_ns = FEC_T_INC_40MHZ - tc.corr_inc; + + if (!priv->ptp_slave) + fpp = priv; + else + fpp = ptp_private[0]; + tmp = readl(fpp->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; + tmp |= corr_ns << FEC_T_INC_CORR_OFFSET; + writel(tmp, fpp->hwp + FEC_ATIME_INC); + + writel(tc.corr_period, fpp->hwp + FEC_ATIME_CORR); +} + +static int ptp_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int ptp_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static int ptp_ioctl( + struct inode *inode, + struct file *file, + unsigned int cmd, + unsigned long arg) +{ + struct ptp_rtc_time *cnt; + struct ptp_rtc_time curr_time; + struct ptp_time rx_time, tx_time; + struct ptp_ts_data *p_ts; + struct ptp_set_comp *p_comp; + struct fec_ptp_private *priv; + unsigned int minor = MINOR(inode->i_rdev); + int retval = 0; + + priv = (struct fec_ptp_private *) ptp_private[minor]; + switch (cmd) { + case PTP_GET_RX_TIMESTAMP: + p_ts = (struct ptp_ts_data *)arg; + retval = fec_get_rx_timestamp(priv, p_ts, &rx_time); + if (retval == 0) + copy_to_user((void __user *)(&(p_ts->ts)), &rx_time, + sizeof(rx_time)); + break; + case PTP_GET_TX_TIMESTAMP: + p_ts = (struct ptp_ts_data *)arg; + fec_get_tx_timestamp(priv, p_ts, &tx_time); + copy_to_user((void __user *)(&(p_ts->ts)), &tx_time, + sizeof(tx_time)); + break; + case PTP_GET_CURRENT_TIME: + fec_get_curr_cnt(priv, &curr_time); + copy_to_user((void __user *)arg, &curr_time, sizeof(curr_time)); + break; + case PTP_SET_RTC_TIME: + cnt = (struct ptp_rtc_time *)arg; + fec_set_1588cnt(priv, cnt); + break; + case PTP_FLUSH_TIMESTAMP: + /* reset sync buffer */ + priv->rx_time_sync.head = 0; + priv->rx_time_sync.tail = 0; + priv->tx_time_sync.head = 0; + priv->tx_time_sync.tail = 0; + /* reset delay_req buffer */ + priv->rx_time_del_req.head = 0; + priv->rx_time_del_req.tail = 0; + priv->tx_time_del_req.head = 0; + priv->tx_time_del_req.tail = 0; + /* reset pdelay_req buffer */ + priv->rx_time_pdel_req.head = 0; + priv->rx_time_pdel_req.tail = 0; + priv->tx_time_pdel_req.head = 0; + priv->tx_time_pdel_req.tail = 0; + /* reset pdelay_resp buffer */ + priv->rx_time_pdel_resp.head = 0; + priv->rx_time_pdel_resp.tail = 0; + priv->tx_time_pdel_resp.head = 0; + priv->tx_time_pdel_resp.tail = 0; + break; + case PTP_SET_COMPENSATION: + p_comp = (struct ptp_set_comp *)arg; + fec_set_drift(priv, p_comp); + break; + case PTP_GET_ORIG_COMP: + ((struct ptp_get_comp *)arg)->dw_origcomp = FEC_PTP_ORIG_COMP; + break; + default: + return -EINVAL; + } + return retval; +} + +static const struct file_operations ptp_fops = { + .owner = THIS_MODULE, + .llseek = NULL, + .read = NULL, + .write = NULL, + .ioctl = ptp_ioctl, + .open = ptp_open, + .release = ptp_release, +}; + +static int init_ptp(void) +{ + if (register_chrdev(PTP_MAJOR, "ptp", &ptp_fops)) + printk(KERN_ERR "Unable to register PTP device as char\n"); + else + printk(KERN_INFO "Register PTP device as char /dev/ptp\n"); + + return 0; +} + +static void ptp_free(void) +{ + /*unregister the PTP device*/ + unregister_chrdev(PTP_MAJOR, "ptp"); +} + +/* + * Resource required for accessing 1588 Timer Registers. + */ +int fec_ptp_init(struct fec_ptp_private *priv, int id) +{ + fec_ptp_init_circ(&(priv->rx_time_sync), DEFAULT_PTP_RX_BUF_SZ); + fec_ptp_init_circ(&(priv->rx_time_del_req), DEFAULT_PTP_RX_BUF_SZ); + fec_ptp_init_circ(&(priv->rx_time_pdel_req), DEFAULT_PTP_RX_BUF_SZ); + fec_ptp_init_circ(&(priv->rx_time_pdel_resp), DEFAULT_PTP_RX_BUF_SZ); + fec_ptp_init_circ(&(priv->tx_time_sync), DEFAULT_PTP_TX_BUF_SZ); + fec_ptp_init_circ(&(priv->tx_time_del_req), DEFAULT_PTP_TX_BUF_SZ); + fec_ptp_init_circ(&(priv->tx_time_pdel_req), DEFAULT_PTP_TX_BUF_SZ); + fec_ptp_init_circ(&(priv->tx_time_pdel_resp), DEFAULT_PTP_TX_BUF_SZ); + + spin_lock_init(&priv->ptp_lock); + spin_lock_init(&priv->cnt_lock); + ptp_private[id] = priv; + priv->dev_id = id; + if (id == 0) + init_ptp(); + return 0; +} +EXPORT_SYMBOL(fec_ptp_init); + +void fec_ptp_cleanup(struct fec_ptp_private *priv) +{ + + if (priv->rx_time_sync.buf) + vfree(priv->rx_time_sync.buf); + if (priv->rx_time_del_req.buf) + vfree(priv->rx_time_del_req.buf); + if (priv->rx_time_pdel_req.buf) + vfree(priv->rx_time_pdel_req.buf); + if (priv->rx_time_pdel_resp.buf) + vfree(priv->rx_time_pdel_resp.buf); + if (priv->tx_time_sync.buf) + vfree(priv->tx_time_sync.buf); + if (priv->tx_time_del_req.buf) + vfree(priv->tx_time_del_req.buf); + if (priv->tx_time_pdel_req.buf) + vfree(priv->tx_time_pdel_req.buf); + if (priv->tx_time_pdel_resp.buf) + vfree(priv->tx_time_pdel_resp.buf); + + ptp_free(); +} +EXPORT_SYMBOL(fec_ptp_cleanup); diff --git a/drivers/net/fec_1588.h b/drivers/net/fec_1588.h new file mode 100644 index 000000000000..bb43c66f3bc1 --- /dev/null +++ b/drivers/net/fec_1588.h @@ -0,0 +1,217 @@ +/* + * drivers/net/fec_1588.h + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#ifndef FEC_1588_H +#define FEC_1588_H + +#include +#include +#include + +#define FALSE 0 +#define TRUE 1 + +/* FEC 1588 register bits */ +#define FEC_T_CTRL_SLAVE 0x00002000 +#define FEC_T_CTRL_CAPTURE 0x00000800 +#define FEC_T_CTRL_RESTART 0x00000200 +#define FEC_T_CTRL_PERIOD_RST 0x00000030 +#define FEC_T_CTRL_ENABLE 0x00000001 + +#define FEC_T_INC_MASK 0x0000007f +#define FEC_T_INC_OFFSET 0 +#define FEC_T_INC_CORR_MASK 0x00007f00 +#define FEC_T_INC_CORR_OFFSET 8 + +#define FEC_T_INC_40MHZ 25 +#define FEC_ATIME_40MHZ 40000000 + +#define FEC_T_PERIOD_ONE_SEC 0x3B9ACA00 + +/* IEEE 1588 definition */ +#define FEC_ECNTRL_TS_EN 0x10 +#define PTP_MAJOR 232 /*the temporary major number + *used by PTP driver, the major + *number 232~239 is unassigned*/ + +#define DEFAULT_PTP_RX_BUF_SZ 2048 +#define DEFAULT_PTP_TX_BUF_SZ 16 +#define PTP_MSG_SYNC 0x0 +#define PTP_MSG_DEL_REQ 0x1 +#define PTP_MSG_P_DEL_REQ 0x2 +#define PTP_MSG_P_DEL_RESP 0x3 +#define PTP_MSG_DEL_RESP 0x4 +#define PTP_MSG_ALL_OTHER 0x5 + +#define PTP_GET_TX_TIMESTAMP 0x1 +#define PTP_GET_RX_TIMESTAMP 0x9 +#define PTP_SET_RTC_TIME 0x3 +#define PTP_SET_COMPENSATION 0x4 +#define PTP_GET_CURRENT_TIME 0x5 +#define PTP_FLUSH_TIMESTAMP 0x6 +#define PTP_ADJ_ADDEND 0x7 +#define PTP_GET_ORIG_COMP 0x8 +#define PTP_GET_ADDEND 0xB +#define PTP_GET_RX_TIMESTAMP_PDELAY_REQ 0xC +#define PTP_GET_RX_TIMESTAMP_PDELAY_RESP 0xD + +#define FEC_PTP_DOMAIN_DLFT 0xe0000181 +#define FEC_PTP_IP_OFFS 0xE +#define FEC_PTP_UDP_OFFS 0x22 +#define FEC_PTP_MSG_TYPE_OFFS 0x2A +#define FEC_PTP_SPORT_ID_OFFS 0x3E +#define FEC_PTP_SEQ_ID_OFFS 0x48 +#define FEC_PTP_CTRL_OFFS 0x4A +#define FEC_PACKET_TYPE_UDP 0x11 + +#define FEC_PTP_ORIG_COMP 0x15555555 + +/* PTP standard time representation structure */ +struct ptp_time{ + u64 sec; /* seconds */ + u32 nsec; /* nanoseconds */ +}; + +/* Structure for PTP Time Stamp */ +struct fec_ptp_data_t { + u8 spid[10]; + int key; + struct ptp_time ts_time; +}; + +/* interface for PTP driver command GET_TX_TIME */ +struct ptp_ts_data { + /* PTP version */ + u8 version; + /* PTP source port ID */ + u8 spid[10]; + /* PTP sequence ID */ + u16 seq_id; + /* PTP message type */ + u8 message_type; + /* PTP timestamp */ + struct ptp_time ts; +}; + +/* interface for PTP driver command SET_RTC_TIME/GET_CURRENT_TIME */ +struct ptp_rtc_time { + struct ptp_time rtc_time; +}; + +/* interface for PTP driver command SET_COMPENSATION */ +struct ptp_set_comp { + u32 drift; + bool o_ops; + u32 freq_compensation; +}; + +/* interface for PTP driver command GET_ORIG_COMP */ +struct ptp_get_comp { + /* the initial compensation value */ + u32 dw_origcomp; + /* the minimum compensation value */ + u32 dw_mincomp; + /*the max compensation value*/ + u32 dw_maxcomp; + /*the min drift applying min compensation value in ppm*/ + u32 dw_mindrift; + /*the max drift applying max compensation value in ppm*/ + u32 dw_maxdrift; +}; + +struct ptp_time_correct { + u32 corr_period; + u32 corr_inc; +}; + +/* PTP message version */ +#define PTP_1588_MSG_VER_1 1 +#define PTP_1588_MSG_VER_2 2 + +#define BD_ENET_TX_TS 0x20000000 +#define BD_ENET_TX_BDU 0x80000000 + +struct fec_ptp_private { + void __iomem *hwp; + int dev_id; + + struct circ_buf rx_time_sync; + struct circ_buf rx_time_del_req; + struct circ_buf rx_time_pdel_req; + struct circ_buf rx_time_pdel_resp; + struct circ_buf tx_time_sync; + struct circ_buf tx_time_del_req; + struct circ_buf tx_time_pdel_req; + struct circ_buf tx_time_pdel_resp; + spinlock_t ptp_lock; + spinlock_t cnt_lock; + + u64 prtc; + u8 ptp_active; + u8 ptp_slave; + struct circ_buf txstamp; +}; + +#ifdef CONFIG_FEC_1588 +static inline int fec_ptp_malloc_priv(struct fec_ptp_private **priv) +{ + *priv = kzalloc(sizeof(struct fec_ptp_private), GFP_KERNEL); + return 1; +} +extern int fec_ptp_init(struct fec_ptp_private *priv, int id); +extern void fec_ptp_cleanup(struct fec_ptp_private *priv); +extern int fec_ptp_start(struct fec_ptp_private *priv); +extern void fec_ptp_stop(struct fec_ptp_private *priv); +extern int fec_ptp_do_txstamp(struct sk_buff *skb); +extern void fec_ptp_store_txstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp); +extern void fec_ptp_store_rxstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp); +#else +static inline int fec_ptp_malloc_priv(struct fec_ptp_private **priv) +{ + return 0; +} +static inline int fec_ptp_init(struct fec_ptp_private *priv, int id) +{ + return 1; +} +static inline void fec_ptp_cleanup(struct fec_ptp_private *priv) { } +static inline int fec_ptp_start(struct fec_ptp_private *priv) +{ + return 1; +} +static inline void fec_ptp_stop(struct fec_ptp_private *priv) {} +static inline int fec_ptp_do_txstamp(struct sk_buff *skb) +{ + return 0; +} +static inline void fec_ptp_store_txstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp) {} +static inline void fec_ptp_store_rxstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp) {} +#endif /* 1588 */ + +#endif diff --git a/drivers/net/fec_mpc52xx.c b/drivers/net/fec_mpc52xx.c index 25e6cc6840b1..fdbf148e1356 100644 --- a/drivers/net/fec_mpc52xx.c +++ b/drivers/net/fec_mpc52xx.c @@ -826,7 +826,7 @@ static int mpc52xx_fec_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (!priv->phydev) return -ENOTSUPP; - return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); + return phy_mii_ioctl(priv->phydev, rq, cmd); } static const struct net_device_ops mpc52xx_fec_netdev_ops = { diff --git a/drivers/net/fec_switch.c b/drivers/net/fec_switch.c new file mode 100644 index 000000000000..8467f746ef63 --- /dev/null +++ b/drivers/net/fec_switch.c @@ -0,0 +1,4313 @@ +/* + * L2 switch Controller (Etheren switch) driver for Mx28. + * + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Shrek Wu (B16972@freescale.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "fec_switch.h" + +#define SWITCH_MAX_PORTS 1 + +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS) +#include +#define FEC_ALIGNMENT 0xf +#else +#define FEC_ALIGNMENT 0x3 +#endif + +/* The number of Tx and Rx buffers. These are allocated from the page + * pool. The code may assume these are power of two, so it it best + * to keep them that size. + * We don't need to allocate pages for the transmitter. We just use + * the skbuffer directly. + */ +#define FEC_ENET_RX_PAGES 8 +#define FEC_ENET_RX_FRSIZE 2048 +#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) +#define FEC_ENET_TX_FRSIZE 2048 +#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) +#define TX_RING_SIZE 16 /* Must be power of two */ +#define TX_RING_MOD_MASK 15 /* for this to work */ + +#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) +#error "FEC: descriptor ring size constants too large" +#endif + +/* Interrupt events/masks */ +#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ +#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ +#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ +#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ +#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ +#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ +#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ +#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ +#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ +#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ + +/* FEC MII MMFR bits definition */ +#define FEC_MMFR_ST (1 << 30) +#define FEC_MMFR_OP_READ (2 << 28) +#define FEC_MMFR_OP_WRITE (1 << 28) +#define FEC_MMFR_PA(v) ((v & 0x1f) << 23) +#define FEC_MMFR_RA(v) ((v & 0x1f) << 18) +#define FEC_MMFR_TA (2 << 16) +#define FEC_MMFR_DATA(v) (v & 0xffff) + +#define FEC_MII_TIMEOUT 1000 + +static struct mii_bus *fec_mii_bus; + +static int switch_enet_open(struct net_device *dev); +static int switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); +static irqreturn_t switch_enet_interrupt(int irq, void *dev_id); +static void switch_enet_tx(struct net_device *dev); +static void switch_enet_rx(struct net_device *dev); +static int switch_enet_close(struct net_device *dev); +static void set_multicast_list(struct net_device *dev); +static void switch_restart(struct net_device *dev, int duplex); +static void switch_stop(struct net_device *dev); + +#define NMII 20 + +/* Transmitter timeout */ +#define TX_TIMEOUT (2*HZ) + +#ifdef CONFIG_ARCH_MXS +static void *swap_buffer(void *bufaddr, int len) +{ + int i; + unsigned int *buf = bufaddr; + + for (i = 0; i < (len + 3) / 4; i++, buf++) + *buf = __swab32(*buf); + + return bufaddr; +} +#endif + +/*last read entry from learning interface*/ +struct eswPortInfo g_info; + +#ifdef USE_DEFAULT_SWITCH_PORT0_MAC +static unsigned char switch_mac_default[] = { + 0x00, 0x08, 0x02, 0x6B, 0xA3, 0x1A, +}; +#else +static unsigned char switch_mac_default[ETH_ALEN]; +#endif + +static void switch_request_intrs(struct net_device *dev, + irqreturn_t switch_net_irq_handler(int irq, void *private), + void *irq_privatedata) +{ + struct switch_enet_private *fep; + + fep = netdev_priv(dev); + + /* Setup interrupt handlers */ + if (request_irq(dev->irq, + switch_net_irq_handler, IRQF_DISABLED, + "mxs-l2switch", irq_privatedata) != 0) + printk(KERN_ERR "FEC: Could not alloc %s IRQ(%d)!\n", + dev->name, dev->irq); +} + +static void switch_set_mii(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct switch_t *fecp; + + fecp = (struct switch_t *)fep->hwp; + + writel(MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | + MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD, + fep->enet_addr + MCF_FEC_RCR0); + writel(MCF_FEC_RCR_PROM | MCF_FEC_RCR_RMII_MODE | + MCF_FEC_RCR_MAX_FL(1522) | MCF_FEC_RCR_CRC_FWD, + fep->enet_addr + MCF_FEC_RCR1); + /* TCR */ + writel(MCF_FEC_TCR_FDEN, fep->enet_addr + MCF_FEC_TCR0); + writel(MCF_FEC_TCR_FDEN, fep->enet_addr + MCF_FEC_TCR1); + + /* ECR */ +#ifdef L2SWITCH_ENHANCED_BUFFER + writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588, + fep->enet_addr + MCF_FEC_ECR0); + writel(MCF_FEC_ECR_ETHER_EN | MCF_FEC_ECR_ENA_1588, + fep->enet_addr + MCF_FEC_ECR1); +#else /*legac buffer*/ + writel(MCF_FEC_ECR_ETHER_EN, fep->enet_addr + MCF_FEC_ECR0); + writel(MCF_FEC_ECR_ETHER_EN, fep->enet_addr + MCF_FEC_ECR1); +#endif + + writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, + fep->enet_addr + MCF_FEC_EIMR0); + writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, + fep->enet_addr + MCF_FEC_EIMR1); + + /* + * Set MII speed to 2.5 MHz + */ + writel(DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1, + fep->enet_addr + MCF_FEC_MSCR0); + writel(DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1, + fep->enet_addr + MCF_FEC_MSCR1); + +#ifdef CONFIG_ARCH_MXS + /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it*/ + fep->phy_speed = readl(fep->enet_addr + MCF_FEC_MSCR0) << 2; + writel(fep->phy_speed, fep->enet_addr + MCF_FEC_MSCR0); + writel(fep->phy_speed, fep->enet_addr + MCF_FEC_MSCR1); +#endif + +} + +static void switch_get_mac(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + unsigned char *iap, tmpaddr[ETH_ALEN]; + static int index; +#ifdef CONFIG_M5272 + if (FEC_FLASHMAC) { + /* + * Get MAC address from FLASH. + * If it is all 1's or 0's, use the default. + */ + iap = (unsigned char *)FEC_FLASHMAC; + if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && + (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) + iap = switch_mac_default; + if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && + (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) + iap = switch_mac_default; + } +#else + if (is_valid_ether_addr(switch_mac_default)) + iap = switch_mac_default; +#endif + else { + *((unsigned long *) &tmpaddr[0]) = + be32_to_cpu(readl(fep->enet_addr + + FEC_ADDR_LOW / sizeof(unsigned long))); + *((unsigned short *) &tmpaddr[4]) = + be16_to_cpu(readl(fep->enet_addr + + FEC_ADDR_HIGH / sizeof(unsigned long)) >> 16); + iap = &tmpaddr[0]; + } + + memcpy(dev->dev_addr, iap, ETH_ALEN); + + /* Adjust MAC if using default MAC address */ + if (iap == switch_mac_default) { + dev->dev_addr[ETH_ALEN-1] = + switch_mac_default[ETH_ALEN-1] + index; + index++; + } +} + +static void switch_enable_phy_intr(void) +{ +} + +static void switch_disable_phy_intr(void) +{ +} + +static void switch_phy_ack_intr(void) +{ +} + +static void switch_localhw_setup(void) +{ +} + +static void switch_uncache(unsigned long addr) +{ +} + +static void switch_platform_flush_cache(void) +{ +} + +/* + * Calculate Galois Field Arithmetic CRC for Polynom x^8+x^2+x+1. + * It omits the final shift in of 8 zeroes a "normal" CRC would do + * (getting the remainder). + * + * Examples (hexadecimal values):
+ * 10-11-12-13-14-15 => CRC=0xc2 + * 10-11-cc-dd-ee-00 => CRC=0xe6 + * + * param: pmacaddress + * A 6-byte array with the MAC address. + * The first byte is the first byte transmitted + * return The 8-bit CRC in bits 7:0 + */ +static int crc8_calc(unsigned char *pmacaddress) +{ + /* byte index */ + int byt; + /* bit index */ + int bit; + int inval; + int crc; + /* preset */ + crc = 0x12; + for (byt = 0; byt < 6; byt++) { + inval = (((int)pmacaddress[byt]) & 0xff); + /* + * shift bit 0 to bit 8 so all our bits + * travel through bit 8 + * (simplifies below calc) + */ + inval <<= 8; + + for (bit = 0; bit < 8; bit++) { + /* next input bit comes into d7 after shift */ + crc |= inval & 0x100; + if (crc & 0x01) + /* before shift */ + crc ^= 0x1c0; + + crc >>= 1; + inval >>= 1; + } + + } + /* upper bits are clean as we shifted in zeroes! */ + return crc; +} + +static void read_atable(struct switch_enet_private *fep, + int index, + unsigned long *read_lo, unsigned long *read_hi) +{ + unsigned long atable_base = (unsigned long)fep->hwentry; + + *read_lo = readl(atable_base + (index<<3)); + *read_hi = readl(atable_base + (index<<3) + 4); +} + +static void write_atable(struct switch_enet_private *fep, + int index, + unsigned long write_lo, unsigned long write_hi) +{ + unsigned long atable_base = (unsigned long)fep->hwentry; + + writel(write_lo, atable_base + (index<<3)); + writel(write_hi, atable_base + (index<<3) + 4); +} + +/* Read one element from the HW receive FIFO (Queue) + * if available and return it. + * return ms_HwPortInfo or null if no data is available + */ +static struct eswPortInfo *esw_portinfofifo_read( + struct switch_enet_private *fep) +{ + struct switch_t *fecp; + unsigned long tmp; + + fecp = fep->hwp; + if (readl(&fecp->ESW_LSR) == 0) { + printk(KERN_ERR "%s: ESW_LSR = %lx\n", + __func__, readl(&fecp->ESW_LSR)); + return NULL; + } + /* read word from FIFO */ + g_info.maclo = readl(&fecp->ESW_LREC0); + /* but verify that we actually did so + * (0=no data available) + */ + if (g_info.maclo == 0) { + printk(KERN_ERR "%s: mac lo %x\n", + __func__, g_info.maclo); + return NULL; + } + /* read 2nd word from FIFO */ + tmp = readl(&fecp->ESW_LREC1); + g_info.machi = tmp & 0xffff; + g_info.hash = (tmp >> 16) & 0xff; + g_info.port = (tmp >> 24) & 0xf; + + return &g_info; +} + + +/* + * Clear complete MAC Look Up Table + */ +static void esw_clear_atable(struct switch_enet_private *fep) +{ + int index; + for (index = 0; index < 2048; index++) + write_atable(fep, index, 0, 0); +} + +/* + * pdates MAC address lookup table with a static entry + * Searches if the MAC address is already there in the block and replaces + * the older entry with new one. If MAC address is not there then puts a + * new entry in the first empty slot available in the block + * + * mac_addr Pointer to the array containing MAC address to + * be put as static entry + * port Port bitmask numbers to be added in static entry, + * valid values are 1-7 + * priority Priority for the static entry in table + * + * return 0 for a successful update else -1 when no slot available + */ +static int esw_update_atable_static(unsigned char *mac_addr, + unsigned int port, unsigned int priority, + struct switch_enet_private *fep) +{ + unsigned long block_index, entry, index_end; + + unsigned long read_lo, read_hi; + unsigned long write_lo, write_hi; + + write_lo = (unsigned long)((mac_addr[3] << 24) | + (mac_addr[2] << 16) | + (mac_addr[1] << 8) | + mac_addr[0]); + write_hi = (unsigned long)(0 | + (port << AT_SENTRY_PORTMASK_shift) | + (priority << AT_SENTRY_PRIO_shift) | + (AT_ENTRY_TYPE_STATIC << AT_ENTRY_TYPE_shift) | + (AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift) | + (mac_addr[5] << 8) | (mac_addr[4])); + + block_index = GET_BLOCK_PTR(crc8_calc(mac_addr)); + index_end = block_index + ATABLE_ENTRY_PER_SLOT; + /* Now search all the entries in the selected block */ + for (entry = block_index; entry < index_end; entry++) { + read_atable(fep, entry, &read_lo, &read_hi); + /* + * MAC address matched, so update the + * existing entry + * even if its a dynamic one + */ + if ((read_lo == write_lo) && + ((read_hi & 0x0000ffff) == + (write_hi & 0x0000ffff))) { + write_atable(fep, entry, write_lo, write_hi); + return 0; + } else if (!(read_hi & (1 << 16))) { + /* + * Fill this empty slot (valid bit zero), + * assuming no holes in the block + */ + write_atable(fep, entry, write_lo, write_hi); + fep->atCurrEntries++; + return 0; + } + } + + /* No space available for this static entry */ + return -1; +} + +static int esw_update_atable_dynamic1(unsigned long write_lo, + unsigned long write_hi, int block_index, + unsigned int port, unsigned int currTime, + struct switch_enet_private *fep) +{ + unsigned long entry, index_end; + unsigned long read_lo, read_hi; + unsigned long tmp; + int time, timeold, indexold; + + /* prepare update port and timestamp */ + tmp = AT_ENTRY_RECORD_VALID << AT_ENTRY_VALID_shift; + tmp |= AT_ENTRY_TYPE_DYNAMIC << AT_ENTRY_TYPE_shift; + tmp |= currTime << AT_DENTRY_TIME_shift; + tmp |= port << AT_DENTRY_PORT_shift; + tmp |= write_hi; + + /* + * linear search through all slot + * entries and update if found + */ + index_end = block_index + ATABLE_ENTRY_PER_SLOT; + /* Now search all the entries in the selected block */ + for (entry = block_index; entry < index_end; entry++) { + read_atable(fep, entry, &read_lo, &read_hi); + if ((read_lo == write_lo) && + ((read_hi & 0x0000ffff) == + (write_hi & 0x0000ffff))) { + /* found correct address, + * update timestamp. + */ + write_atable(fep, entry, write_lo, tmp); + return 0; + } else if (!(read_hi & (1 << 16))) { + /* slot is empty, then use it + * for new entry + * Note: There are no holes, + * therefore cannot be any + * more that need to be compared. + */ + write_atable(fep, entry, write_lo, tmp); + /* statistics (we do it between writing + * .hi an .lo due to + * hardware limitation... + */ + fep->atCurrEntries++; + /* newly inserted */ + return 1; + } + } + + /* + * no more entry available in block ... + * overwrite oldest + */ + timeold = 0; + indexold = 0; + for (entry = block_index; entry < index_end; entry++) { + read_atable(fep, entry, &read_lo, &read_hi); + time = AT_EXTRACT_TIMESTAMP(read_hi); + printk(KERN_ERR "%s : time %x currtime %x\n", + __func__, time, currTime); + time = TIMEDELTA(currTime, time); + if (time > timeold) { + /* is it older ? */ + timeold = time; + indexold = entry; + } + } + + write_atable(fep, indexold, write_lo, tmp); + /* + * Statistics (do it inbetween + *writing to .lo and .hi + */ + fep->atBlockOverflows++; + printk(KERN_ERR "%s update time, atBlockOverflows %x\n", + __func__, fep->atBlockOverflows); + /* newly inserted */ + return 1; +} + +/* dynamicms MAC address table learn and migration */ +static int esw_atable_dynamicms_learn_migration( + struct switch_enet_private *fep, + int currTime) +{ + struct eswPortInfo *pESWPortInfo; + int index; + int inserted = 0; + + pESWPortInfo = esw_portinfofifo_read(fep); + /* Anything to learn */ + if (pESWPortInfo != 0) { + /* get block index from lookup table */ + index = GET_BLOCK_PTR(pESWPortInfo->hash); + inserted = esw_update_atable_dynamic1( + pESWPortInfo->maclo, + pESWPortInfo->machi, index, + pESWPortInfo->port, currTime, fep); + } else { + printk(KERN_ERR "%s:hav invalidate learned data \n", __func__); + return -1; + } + + return 0; + +} + +/* + * esw_forced_forward + * The frame is forwared to the forced destination ports. + * It only replace the MAC lookup function, + * all other filtering(eg.VLAN verification) act as normal + */ +static int esw_forced_forward(struct switch_enet_private *fep, + int port1, int port2, int enable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + /* Enable Forced forwarding for port num */ + if ((port1 == 1) && (port2 == 1)) + tmp |= MCF_ESW_P0FFEN_FD(3); + else if (port1 == 1) + /* Enable Forced forwarding for port 1 only */ + tmp |= MCF_ESW_P0FFEN_FD(1); + else if (port2 == 1) + /* Enable Forced forwarding for port 2 only */ + tmp |= MCF_ESW_P0FFEN_FD(2); + else { + printk(KERN_ERR "%s:do not support " + "the forced forward mode" + "port1 %x port2 %x\n", + __func__, port1, port2); + return -1; + } + + if (enable == 1) + tmp |= MCF_ESW_P0FFEN_FEN; + else if (enable == 0) + tmp &= ~MCF_ESW_P0FFEN_FEN; + else { + printk(KERN_ERR "%s: the enable %x is error\n", + __func__, enable); + return -2; + } + + writel(tmp, &fecp->ESW_P0FFEN); + return 0; +} + +static int esw_get_forced_forward( + struct switch_enet_private *fep, + unsigned long *ulForceForward) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulForceForward = readl(&fecp->ESW_P0FFEN); +#ifdef DEBUG_FORCED_FORWARD + printk(KERN_INFO "%s ESW_P0FFEN %#lx\n", + __func__, readl(&fecp->ESW_P0FFEN)); +#endif + return 0; +} + +static void esw_get_port_enable( + struct switch_enet_private *fep, + unsigned long *ulPortEnable) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortEnable = readl(&fecp->ESW_PER); +#ifdef DEBUG_PORT_ENABLE + printk(KERN_INFO "%s fecp->ESW_PER %#lx\n", + __func__, readl(&fecp->ESW_PER)); +#endif +} +/* + * enable or disable port n tx or rx + * tx_en 0 disable port n tx + * tx_en 1 enable port n tx + * rx_en 0 disbale port n rx + * rx_en 1 enable port n rx + */ +static int esw_port_enable_config(struct switch_enet_private *fep, + int port, int tx_en, int rx_en) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + tmp = fecp->ESW_PER; + if (tx_en == 1) { + if (port == 0) + tmp |= MCF_ESW_PER_TE0; + else if (port == 1) + tmp |= MCF_ESW_PER_TE1; + else if (port == 2) + tmp |= MCF_ESW_PER_TE2; + else { + printk(KERN_ERR "%s:do not support the" + " port %x tx enable %d\n", + __func__, port, tx_en); + return -1; + } + } else if (tx_en == 0) { + if (port == 0) + tmp &= (~MCF_ESW_PER_TE0); + else if (port == 1) + tmp &= (~MCF_ESW_PER_TE1); + else if (port == 2) + tmp &= (~MCF_ESW_PER_TE2); + else { + printk(KERN_ERR "%s:do not support " + "the port %x tx disable %d\n", + __func__, port, tx_en); + return -2; + } + } else { + printk(KERN_ERR "%s:do not support the port %x" + " tx op value %x\n", + __func__, port, tx_en); + return -3; + } + + if (rx_en == 1) { + if (port == 0) + tmp |= MCF_ESW_PER_RE0; + else if (port == 1) + tmp |= MCF_ESW_PER_RE1; + else if (port == 2) + tmp |= MCF_ESW_PER_RE2; + else { + printk(KERN_ERR "%s:do not support the " + "port %x rx enable %d\n", + __func__, port, tx_en); + return -4; + } + } else if (rx_en == 0) { + if (port == 0) + tmp &= (~MCF_ESW_PER_RE0); + else if (port == 1) + tmp &= (~MCF_ESW_PER_RE1); + else if (port == 2) + tmp &= (~MCF_ESW_PER_RE2); + else { + printk(KERN_ERR "%s:do not support the " + "port %x rx disable %d\n", + __func__, port, rx_en); + return -5; + } + } else { + printk(KERN_ERR "%s:do not support the port %x" + " rx op value %x\n", + __func__, port, tx_en); + return -6; + } + + writel(tmp, &fecp->ESW_PER); + return 0; +} + + +static void esw_get_port_broadcast( + struct switch_enet_private *fep, + unsigned long *ulPortBroadcast) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortBroadcast = readl(&fecp->ESW_DBCR); +#ifdef DEBUG_PORT_BROADCAST + printk(KERN_INFO "%s fecp->ESW_DBCR %#lx\n", + __func__, readl(&fecp->ESW_DBCR)); +#endif +} + +static int esw_port_broadcast_config( + struct switch_enet_private *fep, + int port, int enable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port > 2) || (port < 0)) { + printk(KERN_ERR "%s:do not support the port %x" + " default broadcast\n", + __func__, port); + return -1; + } + + tmp = readl(&fecp->ESW_DBCR); + if (enable == 1) { + if (port == 0) + tmp |= MCF_ESW_DBCR_P0; + else if (port == 1) + tmp |= MCF_ESW_DBCR_P1; + else if (port == 2) + tmp |= MCF_ESW_DBCR_P2; + } else if (enable == 0) { + if (port == 0) + tmp &= ~MCF_ESW_DBCR_P0; + else if (port == 1) + tmp &= ~MCF_ESW_DBCR_P1; + else if (port == 2) + tmp &= ~MCF_ESW_DBCR_P2; + } + + writel(tmp, &fecp->ESW_DBCR); + return 0; +} + + +static void esw_get_port_multicast( + struct switch_enet_private *fep, + unsigned long *ulPortMulticast) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortMulticast = readl(&fecp->ESW_DMCR); +#ifdef DEBUG_PORT_MULTICAST + printk(KERN_INFO "%s fecp->ESW_DMCR %#lx\n", + __func__, readl(&fecp->ESW_DMCR)); +#endif +} + +static int esw_port_multicast_config( + struct switch_enet_private *fep, + int port, int enable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port > 2) || (port < 0)) { + printk(KERN_ERR "%s:do not support the port %x" + " default broadcast\n", + __func__, port); + return -1; + } + + tmp = readl(&fecp->ESW_DMCR); + if (enable == 1) { + if (port == 0) + tmp |= MCF_ESW_DMCR_P0; + else if (port == 1) + tmp |= MCF_ESW_DMCR_P1; + else if (port == 2) + tmp |= MCF_ESW_DMCR_P2; + } else if (enable == 0) { + if (port == 0) + tmp &= ~MCF_ESW_DMCR_P0; + else if (port == 1) + tmp &= ~MCF_ESW_DMCR_P1; + else if (port == 2) + tmp &= ~MCF_ESW_DMCR_P2; + } + + writel(tmp, &fecp->ESW_DMCR); + return 0; +} + + +static void esw_get_port_blocking( + struct switch_enet_private *fep, + unsigned long *ulPortBlocking) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortBlocking = (readl(&fecp->ESW_BKLR) & 0x00ff); +#ifdef DEBUG_PORT_BLOCKING + printk(KERN_INFO "%s fecp->ESW_BKLR %#lx\n", + __func__, readl(&fecp->ESW_BKLR)); +#endif +} + +static int esw_port_blocking_config( + struct switch_enet_private *fep, + int port, int enable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port > 2) || (port < 0)) { + printk(KERN_ERR "%s:do not support the port %x" + " default broadcast\n", + __func__, port); + return -1; + } + + tmp = readl(&fecp->ESW_BKLR); + if (enable == 1) { + if (port == 0) + tmp |= MCF_ESW_BKLR_BE0; + else if (port == 1) + tmp |= MCF_ESW_BKLR_BE1; + else if (port == 2) + tmp |= MCF_ESW_BKLR_BE2; + } else if (enable == 0) { + if (port == 0) + tmp &= ~MCF_ESW_BKLR_BE0; + else if (port == 1) + tmp &= ~MCF_ESW_BKLR_BE1; + else if (port == 2) + tmp &= ~MCF_ESW_BKLR_BE2; + } + + writel(tmp, &fecp->ESW_BKLR); + return 0; +} + + +static void esw_get_port_learning( + struct switch_enet_private *fep, + unsigned long *ulPortLearning) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulPortLearning = (readl(&fecp->ESW_BKLR) & 0xff0000) >> 16; +#ifdef DEBUG_PORT_LEARNING + printk(KERN_INFO "%s fecp->ESW_BKLR %#lx\n", + __func__, readl(&fecp->ESW_BKLR)); +#endif +} + +static int esw_port_learning_config( + struct switch_enet_private *fep, + int port, int disable) +{ + unsigned long tmp = 0; + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port > 2) || (port < 0)) { + printk(KERN_ERR "%s:do not support the port %x" + " default broadcast\n", + __func__, port); + return -1; + } + + tmp = readl(&fecp->ESW_BKLR); + if (disable == 1) { + fep->learning_irqhandle_enable = 0; + fecp->switch_imask &= ~MCF_ESW_IMR_LRN; + if (port == 0) + tmp |= MCF_ESW_BKLR_LD0; + else if (port == 1) + tmp |= MCF_ESW_BKLR_LD1; + else if (port == 2) + tmp |= MCF_ESW_BKLR_LD2; + } else if (disable == 0) { + fep->learning_irqhandle_enable = 1; + fecp->switch_imask |= MCF_ESW_IMR_LRN; + if (port == 0) + tmp &= ~MCF_ESW_BKLR_LD0; + else if (port == 1) + tmp &= ~MCF_ESW_BKLR_LD1; + else if (port == 2) + tmp &= ~MCF_ESW_BKLR_LD2; + } + + writel(tmp, &fecp->ESW_BKLR); +#ifdef DEBUG_PORT_LEARNING + printk(KERN_INFO "%s ESW_BKLR %#lx, switch_imask %#lx\n", + __func__, readl(&fecp->ESW_BKLR), readl(&fecp->switch_imask)); +#endif + return 0; +} + +/* + * Checks IP Snoop options of handling the snooped frame. + * mode 0 : The snooped frame is forward only to management port + * mode 1 : The snooped frame is copy to management port and + * normal forwarding is checked. + * mode 2 : The snooped frame is discarded. + * mode 3 : Disable the ip snoop function + * ip_header_protocol : the IP header protocol field + */ +static int esw_ip_snoop_config(struct switch_enet_private *fep, + int num, int mode, unsigned long ip_header_protocol) +{ + struct switch_t *fecp; + unsigned long tmp = 0, protocol_type = 0; + + fecp = fep->hwp; + /* Config IP Snooping */ + if (mode == 0) { + /* Enable IP Snooping */ + tmp = MCF_ESW_IPSNP_EN; + tmp |= MCF_ESW_IPSNP_MODE(0);/*For Forward*/ + } else if (mode == 1) { + /* Enable IP Snooping */ + tmp = MCF_ESW_IPSNP_EN; + /*For Forward and copy_to_mangmnt_port*/ + tmp |= MCF_ESW_IPSNP_MODE(1); + } else if (mode == 2) { + /* Enable IP Snooping */ + tmp = MCF_ESW_IPSNP_EN; + tmp |= MCF_ESW_IPSNP_MODE(2);/*discard*/ + } else if (mode == 3) { + /* disable IP Snooping */ + tmp = MCF_ESW_IPSNP_EN; + tmp &= ~MCF_ESW_IPSNP_EN; + } else { + printk(KERN_ERR "%s: the mode %x " + "we do not support\n", __func__, mode); + return -1; + } + + protocol_type = ip_header_protocol; + writel(tmp | MCF_ESW_IPSNP_PROTOCOL(protocol_type), + &fecp->ESW_IPSNP[num]); + printk(KERN_INFO "%s : ESW_IPSNP[%d] %#lx\n", + __func__, num, readl(&fecp->ESW_IPSNP[num])); + return 0; +} + +static void esw_get_ip_snoop_config( + struct switch_enet_private *fep, + unsigned long *ulpESW_IPSNP) +{ + int i; + struct switch_t *fecp; + + fecp = fep->hwp; + for (i = 0; i < 8; i++) + *(ulpESW_IPSNP + i) = readl(&fecp->ESW_IPSNP[i]); +#ifdef DEBUG_IP_SNOOP + printk(KERN_INFO "%s ", __func__); + for (i = 0; i < 8; i++) + printk(KERN_INFO " reg(%d) %#lx", readl(&fecp->ESW_IPSNP[i])); + printk(KERN_INFO "\n"); +#endif + +} +/* + * Checks TCP/UDP Port Snoop options of handling the snooped frame. + * mode 0 : The snooped frame is forward only to management port + * mode 1 : The snooped frame is copy to management port and + * normal forwarding is checked. + * mode 2 : The snooped frame is discarded. + * compare_port : port number in the TCP/UDP header + * compare_num 1: TCP/UDP source port number is compared + * compare_num 2: TCP/UDP destination port number is compared + * compare_num 3: TCP/UDP source and destination port number is compared + */ +static int esw_tcpudp_port_snoop_config(struct switch_enet_private *fep, + int num, int mode, int compare_port, int compare_num) +{ + struct switch_t *fecp; + unsigned long tmp = 0; + + fecp = fep->hwp; + + /* Enable TCP/UDP port Snooping */ + tmp = MCF_ESW_PSNP_EN; + if (mode == 0) + tmp |= MCF_ESW_PSNP_MODE(0);/* For Forward */ + else if (mode == 1)/*For Forward and copy_to_mangmnt_port*/ + tmp |= MCF_ESW_PSNP_MODE(1); + else if (mode == 2) + tmp |= MCF_ESW_PSNP_MODE(2);/* discard */ + else if (mode == 3) /* disable the port function */ + tmp &= (~MCF_ESW_PSNP_EN); + else { + printk(KERN_ERR "%s: the mode %x we do not support\n", + __func__, mode); + return -1; + } + + if (compare_num == 1) + tmp |= MCF_ESW_PSNP_CS; + else if (compare_num == 2) + tmp |= MCF_ESW_PSNP_CD; + else if (compare_num == 3) + tmp |= MCF_ESW_PSNP_CD | MCF_ESW_PSNP_CS; + else { + printk(KERN_ERR "%s: the compare port address %x" + " we do not support\n", + __func__, compare_num); + return -1; + } + + writel(tmp | MCF_ESW_PSNP_PORT_COMPARE(compare_port), + &fecp->ESW_PSNP[num]); + printk(KERN_INFO "ESW_PSNP[%d] %#lx\n", + num, fecp->ESW_PSNP[num]); + return 0; +} + +static void esw_get_tcpudp_port_snoop_config( + struct switch_enet_private *fep, + unsigned long *ulpESW_PSNP) +{ + int i; + struct switch_t *fecp; + + fecp = fep->hwp; + for (i = 0; i < 8; i++) + *(ulpESW_PSNP + i) = readl(&fecp->ESW_PSNP[i]); +#ifdef DEBUG_TCPUDP_PORT_SNOOP + printk(KERN_INFO "%s ", __func__); + for (i = 0; i < 8; i++) + printk(KERN_INFO " reg(%d) %#lx", readl(fecp->ESW_PSNP[i])); + printk(KERN_INFO "\n"); +#endif + +} + +static void esw_get_port_mirroring( + struct switch_enet_private *fep, + struct eswIoctlPortMirrorStatus *pPortMirrorStatus) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + pPortMirrorStatus->ESW_MCR = readl(&fecp->ESW_MCR); + pPortMirrorStatus->ESW_EGMAP = readl(&fecp->ESW_EGMAP); + pPortMirrorStatus->ESW_INGMAP = readl(&fecp->ESW_INGMAP); + pPortMirrorStatus->ESW_INGSAL = readl(&fecp->ESW_INGSAL); + pPortMirrorStatus->ESW_INGSAH = readl(&fecp->ESW_INGSAH); + pPortMirrorStatus->ESW_INGDAL = readl(&fecp->ESW_INGDAL); + pPortMirrorStatus->ESW_INGDAH = readl(&fecp->ESW_INGDAH); + pPortMirrorStatus->ESW_ENGSAL = readl(&fecp->ESW_ENGSAL); + pPortMirrorStatus->ESW_ENGSAH = readl(&fecp->ESW_ENGSAH); + pPortMirrorStatus->ESW_ENGDAL = readl(&fecp->ESW_ENGDAL); + pPortMirrorStatus->ESW_ENGDAH = readl(&fecp->ESW_ENGDAH); + pPortMirrorStatus->ESW_MCVAL = readl(&fecp->ESW_MCVAL); +#ifdef DEBUG_PORT_MIRROR + printk(KERN_INFO "%s : ESW_MCR %#lx, ESW_EGMAP %#lx\n" + "ESW_INGMAP %#lx, ESW_INGSAL %#lx, " + "ESW_INGSAH %#lx ESW_INGDAL %#lx, ESW_INGDAH %#lx\n" + "ESW_ENGSAL %#lx, ESW_ENGSAH%#lx, ESW_ENGDAL %#lx," + "ESW_ENGDAH %#lx, ESW_MCVAL %#lx\n", + __func__, readl(&fecp->ESW_MCR), + readl(&fecp->ESW_EGMAP), + readl(&fecp->ESW_INGMAP), + readl(&fecp->ESW_INGSAL), + readl(&fecp->ESW_INGSAH), + readl(&fecp->ESW_INGDAL), + readl(&fecp->ESW_INGDAH), + readl(&fecp->ESW_ENGSAL), + readl(&fecp->ESW_ENGSAH), + readl(&fecp->ESW_ENGDAL), + readl(&fecp->ESW_ENGDAH), + readl(&fecp->ESW_MCVAL)); +#endif +} + +static int esw_port_mirroring_config(struct switch_enet_private *fep, + int mirror_port, int port, int mirror_enable, + unsigned char *src_mac, unsigned char *des_mac, + int egress_en, int ingress_en, + int egress_mac_src_en, int egress_mac_des_en, + int ingress_mac_src_en, int ingress_mac_des_en) +{ + struct switch_t *fecp; + unsigned long tmp = 0; + + fecp = fep->hwp; + + /*mirroring config*/ + tmp = 0; + if (egress_en == 1) { + tmp |= MCF_ESW_MCR_EGMAP; + if (port == 0) + fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG0; + else if (port == 1) + fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG1; + else if (port == 2) + fecp->ESW_EGMAP = MCF_ESW_EGMAP_EG2; + else { + printk(KERN_ERR "%s: the port %x we do not support\n", + __func__, port); + return -1; + } + } else if (egress_en == 0) { + tmp &= (~MCF_ESW_MCR_EGMAP); + } else { + printk(KERN_ERR "%s: egress_en %x we do not support\n", + __func__, egress_en); + return -1; + } + + if (ingress_en == 1) { + tmp |= MCF_ESW_MCR_INGMAP; + if (port == 0) + fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING0; + else if (port == 1) + fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING1; + else if (port == 2) + fecp->ESW_INGMAP = MCF_ESW_INGMAP_ING2; + else { + printk(KERN_ERR "%s: the port %x we do not support\n", + __func__, port); + return -1; + } + } else if (ingress_en == 0) { + tmp &= ~MCF_ESW_MCR_INGMAP; + } else{ + printk(KERN_ERR "%s: ingress_en %x we do not support\n", + __func__, ingress_en); + return -1; + } + + if (egress_mac_src_en == 1) { + tmp |= MCF_ESW_MCR_EGSA; + fecp->ESW_ENGSAH = (src_mac[5] << 8) | (src_mac[4]); + fecp->ESW_ENGSAL = (unsigned long)((src_mac[3] << 24) | + (src_mac[2] << 16) | + (src_mac[1] << 8) | + src_mac[0]); + } else if (egress_mac_src_en == 0) { + tmp &= ~MCF_ESW_MCR_EGSA; + } else { + printk(KERN_ERR "%s: egress_mac_src_en %x we do not support\n", + __func__, egress_mac_src_en); + return -1; + } + + if (egress_mac_des_en == 1) { + tmp |= MCF_ESW_MCR_EGDA; + fecp->ESW_ENGDAH = (des_mac[5] << 8) | (des_mac[4]); + fecp->ESW_ENGDAL = (unsigned long)((des_mac[3] << 24) | + (des_mac[2] << 16) | + (des_mac[1] << 8) | + des_mac[0]); + } else if (egress_mac_des_en == 0) { + tmp &= ~MCF_ESW_MCR_EGDA; + } else { + printk(KERN_ERR "%s: egress_mac_des_en %x we do not support\n", + __func__, egress_mac_des_en); + return -1; + } + + if (ingress_mac_src_en == 1) { + tmp |= MCF_ESW_MCR_INGSA; + fecp->ESW_INGSAH = (src_mac[5] << 8) | (src_mac[4]); + fecp->ESW_INGSAL = (unsigned long)((src_mac[3] << 24) | + (src_mac[2] << 16) | + (src_mac[1] << 8) | + src_mac[0]); + } else if (ingress_mac_src_en == 0) { + tmp &= ~MCF_ESW_MCR_INGSA; + } else { + printk(KERN_ERR "%s: ingress_mac_src_en %x we do not support\n", + __func__, ingress_mac_src_en); + return -1; + } + + if (ingress_mac_des_en == 1) { + tmp |= MCF_ESW_MCR_INGDA; + fecp->ESW_INGDAH = (des_mac[5] << 8) | (des_mac[4]); + fecp->ESW_INGDAL = (unsigned long)((des_mac[3] << 24) | + (des_mac[2] << 16) | + (des_mac[1] << 8) | + des_mac[0]); + } else if (ingress_mac_des_en == 0) { + tmp &= ~MCF_ESW_MCR_INGDA; + } else { + printk(KERN_ERR "%s: ingress_mac_des_en %x we do not support\n", + __func__, ingress_mac_des_en); + return -1; + } + + /*------------------------------------------------------------------*/ + if (mirror_enable == 1) + tmp |= MCF_ESW_MCR_MEN | MCF_ESW_MCR_PORT(mirror_port); + else if (mirror_enable == 0) + tmp &= ~MCF_ESW_MCR_MEN; + else + printk(KERN_ERR "%s: the mirror enable %x is error\n", + __func__, mirror_enable); + + + writel(tmp, &fecp->ESW_MCR); + printk(KERN_INFO "%s : MCR %#lx, EGMAP %#lx, INGMAP %#lx;\n" + "ENGSAH %#lx, ENGSAL %#lx ;ENGDAH %#lx, ENGDAL %#lx;\n" + "INGSAH %#lx, INGSAL %#lx\n;INGDAH %#lx, INGDAL %#lx;\n", + __func__, readl(fecp->ESW_MCR), + readl(&fecp->ESW_EGMAP), + readl(&fecp->ESW_INGMAP), + readl(&fecp->ESW_ENGSAH), + readl(&fecp->ESW_ENGSAL), + readl(&fecp->ESW_ENGDAH), + readl(&fecp->ESW_ENGDAL), + readl(&fecp->ESW_INGSAH), + readl(&fecp->ESW_INGSAL), + readl(&fecp->ESW_INGDAH), + readl(&fecp->ESW_INGDAL)); + return 0; +} + +static void esw_get_vlan_verification( + struct switch_enet_private *fep, + unsigned long *ulValue) +{ + struct switch_t *fecp; + fecp = fep->hwp; + *ulValue = fecp->ESW_VLANV; + +#ifdef DEBUG_VLAN_VERIFICATION_CONFIG + printk(KERN_INFO "%s: ESW_VLANV %#lx\n", + __func__, readl(&fecp->ESW_VLANV)); +#endif +} + +static int esw_set_vlan_verification( + struct switch_enet_private *fep, int port, + int vlan_domain_verify_en, + int vlan_discard_unknown_en) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + if ((port < 0) || (port > 2)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + if (vlan_domain_verify_en == 1) { + if (port == 0) + writel(readl(&fecp->ESW_VLANV) | MCF_ESW_VLANV_VV0, + &fecp->ESW_VLANV); + else if (port == 1) + writel(readl(&fecp->ESW_VLANV) | MCF_ESW_VLANV_VV1, + &fecp->ESW_VLANV); + else if (port == 2) + writel(readl(&fecp->ESW_VLANV) | MCF_ESW_VLANV_VV2, + &fecp->ESW_VLANV); + } else if (vlan_domain_verify_en == 0) { + if (port == 0) + writel(readl(&fecp->ESW_VLANV) & ~MCF_ESW_VLANV_VV0, + &fecp->ESW_VLANV); + else if (port == 1) + writel(readl(&fecp->ESW_VLANV) & ~MCF_ESW_VLANV_VV1, + &fecp->ESW_VLANV); + else if (port == 2) + writel(readl(&fecp->ESW_VLANV) & ~MCF_ESW_VLANV_VV2, + &fecp->ESW_VLANV); + } else { + printk(KERN_INFO "%s: donot support " + "vlan_domain_verify %x\n", + __func__, vlan_domain_verify_en); + return -2; + } + + if (vlan_discard_unknown_en == 1) { + if (port == 0) + writel(readl(&fecp->ESW_VLANV) | MCF_ESW_VLANV_DU0, + &fecp->ESW_VLANV); + else if (port == 1) + writel(readl(&fecp->ESW_VLANV) | MCF_ESW_VLANV_DU1, + &fecp->ESW_VLANV); + else if (port == 2) + writel(readl(&fecp->ESW_VLANV) | MCF_ESW_VLANV_DU2, + &fecp->ESW_VLANV); + } else if (vlan_discard_unknown_en == 0) { + if (port == 0) + writel(readl(&fecp->ESW_VLANV) & ~MCF_ESW_VLANV_DU0, + &fecp->ESW_VLANV); + else if (port == 1) + writel(readl(&fecp->ESW_VLANV) & ~MCF_ESW_VLANV_DU1, + &fecp->ESW_VLANV); + else if (port == 2) + writel(readl(&fecp->ESW_VLANV) & ~MCF_ESW_VLANV_DU2, + &fecp->ESW_VLANV); + } else { + printk(KERN_INFO "%s: donot support " + "vlan_discard_unknown %x\n", + __func__, vlan_discard_unknown_en); + return -3; + } + +#ifdef DEBUG_VLAN_VERIFICATION_CONFIG + printk(KERN_INFO "%s: ESW_VLANV %#lx\n", + __func__, fecp->ESW_VLANV); +#endif + return 0; +} + +static void esw_get_vlan_resolution_table( + struct switch_enet_private *fep, + int vlan_domain_num, + unsigned long *ulValue) +{ + struct switch_t *fecp; + fecp = fep->hwp; + + *ulValue = fecp->ESW_VRES[vlan_domain_num]; + +#ifdef DEBUG_VLAN_DOMAIN_TABLE + printk(KERN_INFO "%s: ESW_VRES[%d] = %#lx\n", + __func__, vlan_domain_num, + fecp->ESW_VRES[vlan_domain_num]); +#endif +} + +int esw_set_vlan_resolution_table( + struct switch_enet_private *fep, + unsigned short port_vlanid, + int vlan_domain_num, + int vlan_domain_port) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + if ((vlan_domain_num < 0) + || (vlan_domain_num > 31)) { + printk(KERN_ERR "%s: do not support the " + "vlan_domain_num %d\n", + __func__, vlan_domain_num); + return -1; + } + + if ((vlan_domain_port < 0) + || (vlan_domain_port > 7)) { + printk(KERN_ERR "%s: do not support the " + "vlan_domain_port %d\n", + __func__, vlan_domain_port); + return -2; + } + + writel(MCF_ESW_VRES_VLANID(port_vlanid) | vlan_domain_port, + &fecp->ESW_VRES[vlan_domain_num]); + +#ifdef DEBUG_VLAN_DOMAIN_TABLE + printk(KERN_INFO "%s: ESW_VRES[%d] = %#lx\n", + __func__, vlan_domain_num, + readl(&fecp->ESW_VRES[vlan_domain_num])); +#endif + return 0; +} + +static void esw_get_vlan_input_config( + struct switch_enet_private *fep, + struct eswIoctlVlanInputStatus *pVlanInputConfig) +{ + struct switch_t *fecp; + int i; + + fecp = fep->hwp; + for (i = 0; i < 3; i++) + pVlanInputConfig->ESW_PID[i] = readl(&fecp->ESW_PID[i]); + + pVlanInputConfig->ESW_VLANV = readl(&fecp->ESW_VLANV); + pVlanInputConfig->ESW_VIMSEL = readl(&fecp->ESW_VIMSEL); + pVlanInputConfig->ESW_VIMEN = readl(&fecp->ESW_VIMEN); + + for (i = 0; i < 32; i++) + pVlanInputConfig->ESW_VRES[i] = readl(&fecp->ESW_VRES[i]); +#ifdef DEBUG_VLAN_INTPUT_CONFIG + printk(KERN_INFO "%s: ESW_VLANV %#lx, ESW_VIMSEL %#lx, " + "ESW_VIMEN %#lx, ESW_PID[0], ESW_PID[1] %#lx, " + "ESW_PID[2] %#lx", __func__, + readl(&fecp->ESW_VLANV), + readl(&fecp->ESW_VIMSEL), + readl(&fecp->ESW_VIMEN), + readl(&fecp->ESW_PID[0]), + readl(&fecp->ESW_PID[1]), + readl(&fecp->ESW_PID[2]); +#endif +} + + +static int esw_vlan_input_process(struct switch_enet_private *fep, + int port, int mode, unsigned short port_vlanid, + int vlan_verify_en, int vlan_domain_num, + int vlan_domain_port) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + /*we only support mode1 mode2 mode3 mode4*/ + if ((mode < 0) || (mode > 3)) { + printk(KERN_ERR "%s: do not support the" + " VLAN input processing mode %d\n", + __func__, mode); + return -1; + } + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, mode); + return -2; + } + + if ((vlan_verify_en == 1) && ((vlan_domain_num < 0) + || (vlan_domain_num > 32))) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, mode); + return -3; + } + + fecp->ESW_PID[port] = MCF_ESW_PID_VLANID(port_vlanid); + if (port == 0) { + if (vlan_verify_en == 1) + writel(MCF_ESW_VRES_VLANID(port_vlanid) | MCF_ESW_VRES_P0, + &fecp->ESW_VRES[vlan_domain_num]); + + writel(readl(&fecp->ESW_VIMEN) | MCF_ESW_VIMEN_EN0, + &fecp->ESW_VIMEN); + writel(readl(&fecp->ESW_VIMSEL) | MCF_ESW_VIMSEL_IM0(mode), + &fecp->ESW_VIMSEL); + } else if (port == 1) { + if (vlan_verify_en == 1) + writel(MCF_ESW_VRES_VLANID(port_vlanid) | MCF_ESW_VRES_P1, + &fecp->ESW_VRES[vlan_domain_num]); + + writel(readl(&fecp->ESW_VIMEN) | MCF_ESW_VIMEN_EN1, + &fecp->ESW_VIMEN); + writel(readl(&fecp->ESW_VIMSEL) | MCF_ESW_VIMSEL_IM1(mode), + &fecp->ESW_VIMSEL); + } else if (port == 2) { + if (vlan_verify_en == 1) + writel(MCF_ESW_VRES_VLANID(port_vlanid) | MCF_ESW_VRES_P2, + &fecp->ESW_VRES[vlan_domain_num]); + + writel(readl(&fecp->ESW_VIMEN) | MCF_ESW_VIMEN_EN2, + &fecp->ESW_VIMEN); + writel(readl(&fecp->ESW_VIMSEL) | MCF_ESW_VIMSEL_IM2(mode), + &fecp->ESW_VIMSEL); + } else { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -2; + } + + return 0; +} + +static void esw_get_vlan_output_config(struct switch_enet_private *fep, + unsigned long *ulVlanOutputConfig) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + *ulVlanOutputConfig = readl(&fecp->ESW_VOMSEL); +#ifdef DEBUG_VLAN_OUTPUT_CONFIG + printk(KERN_INFO "%s: ESW_VOMSEL %#lx", __func__, + fecp->ESW_VOMSEL); +#endif +} + +static int esw_vlan_output_process(struct switch_enet_private *fep, + int port, int mode) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port < 0) || (port > 2)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, mode); + return -1; + } + + if (port == 0) { + writel(readl(&fecp->ESW_VOMSEL) | MCF_ESW_VOMSEL_OM0(mode), + &fecp->ESW_VOMSEL); + } else if (port == 1) { + writel(readl(&fecp->ESW_VOMSEL) | MCF_ESW_VOMSEL_OM1(mode), + &fecp->ESW_VOMSEL); + } else if (port == 2) { + writel(readl(&fecp->ESW_VOMSEL) | MCF_ESW_VOMSEL_OM2(mode), + &fecp->ESW_VOMSEL);; + } else { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + return 0; +} + +/* frame calssify and priority resolution */ +/* vlan priority lookup */ +static int esw_framecalssify_vlan_priority_lookup( + struct switch_enet_private *fep, + int port, int func_enable, + int vlan_pri_table_num, + int vlan_pri_table_value) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + if (func_enable == 0) { + writel(readl(&fecp->ESW_PRES[port]) & ~MCF_ESW_PRES_VLAN, + &fecp->ESW_PRES[port]); + printk(KERN_ERR "%s: disable port %d VLAN priority " + "lookup function\n", __func__, port); + return 0; + } + + if ((vlan_pri_table_num < 0) || (vlan_pri_table_num > 7)) { + printk(KERN_ERR "%s: do not support the priority %d\n", + __func__, vlan_pri_table_num); + return -1; + } + + writel(readl(&fecp->ESW_PVRES[port]) | (((vlan_pri_table_value & 0x3) + << (vlan_pri_table_num*3))), + &fecp->ESW_PVRES[port]); + /* enable port VLAN priority lookup function */ + writel(readl(&fecp->ESW_PRES[port]) | MCF_ESW_PRES_VLAN, + &fecp->ESW_PRES[port]); + + return 0; +} + +static int esw_framecalssify_ip_priority_lookup( + struct switch_enet_private *fep, + int port, int func_enable, int ipv4_en, + int ip_priority_num, + int ip_priority_value) +{ + struct switch_t *fecp; + unsigned long tmp = 0, tmp_prio = 0; + + fecp = fep->hwp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + if (func_enable == 0) { + writel(readl(&fecp->ESW_PRES[port]) & (~MCF_ESW_PRES_IP), + &fecp->ESW_PRES[port]); + printk(KERN_ERR "%s: disable port %d ip priority " + "lookup function\n", __func__, port); + return 0; + } + + /* IPV4 priority 64 entry table lookup */ + /* IPv4 head 6 bit TOS field */ + if (ipv4_en == 1) { + if ((ip_priority_num < 0) || (ip_priority_num > 63)) { + printk(KERN_ERR "%s: do not support the table entry %d\n", + __func__, ip_priority_num); + return -2; + } + } else { /* IPV6 priority 256 entry table lookup */ + /* IPv6 head 8 bit COS field */ + if ((ip_priority_num < 0) || (ip_priority_num > 255)) { + printk(KERN_ERR "%s: do not support the table entry %d\n", + __func__, ip_priority_num); + return -3; + } + } + + /* IP priority table lookup : address */ + tmp = MCF_ESW_IPRES_ADDRESS(ip_priority_num); + /* IP priority table lookup : ipv4sel */ + if (ipv4_en == 1) + tmp = tmp | MCF_ESW_IPRES_IPV4SEL; + /* IP priority table lookup : priority */ + if (port == 0) + tmp |= MCF_ESW_IPRES_PRI0(ip_priority_value); + else if (port == 1) + tmp |= MCF_ESW_IPRES_PRI1(ip_priority_value); + else if (port == 2) + tmp |= MCF_ESW_IPRES_PRI2(ip_priority_value); + + /* configure */ + writel(MCF_ESW_IPRES_READ | MCF_ESW_IPRES_ADDRESS(ip_priority_num), + &fecp->ESW_IPRES); + tmp_prio = readl(&fecp->ESW_IPRES); + + writel(tmp | tmp_prio, &fecp->ESW_IPRES); + + writel(MCF_ESW_IPRES_READ | + MCF_ESW_IPRES_ADDRESS(ip_priority_num), + &fecp->ESW_IPRES); + tmp_prio = readl(&fecp->ESW_IPRES); + + /* enable port IP priority lookup function */ + writel(MCF_ESW_PRES_IP, &fecp->ESW_PRES[port]); + + return 0; +} + +static int esw_framecalssify_mac_priority_lookup( + struct switch_enet_private *fep, + int port) +{ + struct switch_t *fecp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + fecp = fep->hwp; + writel(readl(&fecp->ESW_PRES[port]) | MCF_ESW_PRES_MAC, + &fecp->ESW_PRES[port]); + + return 0; +} + +static int esw_frame_calssify_priority_init( + struct switch_enet_private *fep, + int port, unsigned char priority_value) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + /* disable all priority lookup function */ + writel(0, &fecp->ESW_PRES[port]); + writel(MCF_ESW_PRES_DFLT_PRI(priority_value & 0x7), + &fecp->ESW_PRES[port]); + + return 0; +} + +static int esw_get_statistics_status( + struct switch_enet_private *fep, + struct esw_statistics_status *pStatistics) +{ + struct switch_t *fecp; + fecp = fep->hwp; + + pStatistics->ESW_DISCN = readl(&fecp->ESW_DISCN); + pStatistics->ESW_DISCB = readl(&fecp->ESW_DISCB); + pStatistics->ESW_NDISCN = readl(&fecp->ESW_NDISCN); + pStatistics->ESW_NDISCB = readl(&fecp->ESW_NDISCB); +#ifdef DEBUG_STATISTICS + printk(KERN_ERR "%s:ESW_DISCN %#lx, ESW_DISCB %#lx," + "ESW_NDISCN %#lx, ESW_NDISCB %#lx\n", + __func__, + readl(&fecp->ESW_DISCN), + readl(&fecp->ESW_DISCB), + readl(&fecp->ESW_NDISCN), + readl(&fecp->ESW_NDISCB)); +#endif + return 0; +} + +static int esw_get_port_statistics_status( + struct switch_enet_private *fep, + int port, + struct esw_port_statistics_status *pPortStatistics) +{ + struct switch_t *fecp; + + if ((port < 0) || (port > 3)) { + printk(KERN_ERR "%s: do not support the port %d\n", + __func__, port); + return -1; + } + + fecp = fep->hwp; + + pPortStatistics->MCF_ESW_POQC = + readl(&fecp->port_statistics_status[port].MCF_ESW_POQC); + pPortStatistics->MCF_ESW_PMVID = + readl(&fecp->port_statistics_status[port].MCF_ESW_PMVID); + pPortStatistics->MCF_ESW_PMVTAG = + readl(&fecp->port_statistics_status[port].MCF_ESW_PMVTAG); + pPortStatistics->MCF_ESW_PBL = + readl(&fecp->port_statistics_status[port].MCF_ESW_PBL); +#ifdef DEBUG_PORT_STATISTICS + printk(KERN_ERR "%s : port[%d].MCF_ESW_POQC %#lx, MCF_ESW_PMVID %#lx," + " MCF_ESW_PMVTAG %#lx, MCF_ESW_PBL %#lx\n", + __func__, port, + readl(&fecp->port_statistics_status[port].MCF_ESW_POQC), + readl(&fecp->port_statistics_status[port].MCF_ESW_PMVID), + readl(&fecp->port_statistics_status[port].MCF_ESW_PMVTAG), + readl(&fecp->port_statistics_status[port].MCF_ESW_PBL)); +#endif + return 0; +} + +static int esw_get_output_queue_status( + struct switch_enet_private *fep, + struct esw_output_queue_status *pOutputQueue) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + pOutputQueue->ESW_MMSR = readl(&fecp->ESW_MMSR); + pOutputQueue->ESW_LMT = readl(&fecp->ESW_LMT); + pOutputQueue->ESW_LFC = readl(&fecp->ESW_LFC); + pOutputQueue->ESW_IOSR = readl(&fecp->ESW_IOSR); + pOutputQueue->ESW_PCSR = readl(&fecp->ESW_PCSR); + pOutputQueue->ESW_QWT = readl(&fecp->ESW_QWT); + pOutputQueue->ESW_P0BCT = readl(&fecp->ESW_P0BCT); +#ifdef DEBUG_OUTPUT_QUEUE + printk(KERN_ERR "%s:ESW_MMSR %#lx, ESW_LMT %#lx, ESW_LFC %#lx, " + "ESW_IOSR %#lx, ESW_PCSR %#lx, ESW_QWT %#lx, ESW_P0BCT %#lx\n", + __func__, + readl(&fecp->ESW_MMSR), + readl(&fecp->ESW_LMT), + readl(&fecp->ESW_LFC), + readl(&fecp->ESW_IOSR), + readl(&fecp->ESW_PCSR), + readl(&fecp->ESW_QWT), + readl(&fecp->ESW_P0BCT)); +#endif + return 0; +} + +/* set output queue memory status and configure*/ +static int esw_set_output_queue_memory( + struct switch_enet_private *fep, + int fun_num, + struct esw_output_queue_status *pOutputQueue) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + if (fun_num == 1) { + /* memory manager status*/ + writel(pOutputQueue->ESW_MMSR, &fecp->ESW_MMSR); + } else if (fun_num == 2) { + /*low memory threshold*/ + writel(pOutputQueue->ESW_LMT, &fecp->ESW_LMT); + } else if (fun_num == 3) { + /*lowest number of free cells*/ + writel(pOutputQueue->ESW_LFC, &fecp->ESW_LFC); + } else if (fun_num == 4) { + /*queue weights*/ + writel(pOutputQueue->ESW_QWT, &fecp->ESW_QWT); + } else if (fun_num == 5) { + /*port 0 backpressure congenstion thresled*/ + writel(pOutputQueue->ESW_P0BCT, &fecp->ESW_P0BCT); + } else { + printk(KERN_INFO "%s: do not support the cmd %x\n", + __func__, fun_num); + return -1; + } +#ifdef DEBUG_OUTPUT_QUEUE + printk(KERN_ERR "%s:ESW_MMSR %#lx, ESW_LMT %#lx, ESW_LFC %#lx, " + "ESW_IOSR %#lx, ESW_PCSR %#lx, ESW_QWT %#lx, ESW_P0BCT %#lx\n", + __func__, + readl(&fecp->ESW_MMSR), + readl(&fecp->ESW_LMT), + readl(&fecp->ESW_LFC), + readl(&fecp->ESW_IOSR), + readl(&fecp->ESW_PCSR), + readl(&fecp->ESW_QWT), + readl(&fecp->ESW_P0BCT)); +#endif + return 0; +} + +int esw_set_irq_mask( + struct switch_enet_private *fep, + unsigned long mask, int enable) +{ + struct switch_t *fecp; + + fecp = fep->hwp; +#ifdef DEBUG_IRQ + printk(KERN_INFO "%s: irq event %#lx, irq mask %#lx " + " mask %x, enable %x\n", + __func__, + readl(&fecp->switch_ievent), + readl(&fecp->switch_imask), mask, enable); +#endif + if (enable == 1) + writel(readl(&fecp->switch_imask) | mask, + &fecp->switch_imask); + else if (enable == 1) + writel(readl(&fecp->switch_imask) & (~mask), + &fecp->switch_imask); + else { + printk(KERN_INFO "%s: enable %x is error value\n", + __func__, enable); + return -1; + } +#ifdef DEBUG_IRQ + printk(KERN_INFO "%s: irq event %#lx, irq mask %#lx, " + "rx_des_start %#lx, tx_des_start %#lx, " + "rx_buff_size %#lx, rx_des_active %#lx, " + "tx_des_active %#lx\n", + __func__, + readl(&fecp->switch_ievent), + readl(&fecp->switch_imask), + readl(&fecp->fec_r_des_start), + readl(&fecp->fec_x_des_start), + readl(&fecp->fec_r_buff_size), + readl(&fecp->fec_r_des_active), + readl(&fecp->fec_x_des_active)); +#endif + return 0; +} + +static void esw_get_switch_mode( + struct switch_enet_private *fep, + unsigned long *ulModeConfig) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulModeConfig = readl(&fecp->ESW_MODE); +#ifdef DEBUG_SWITCH_MODE + printk(KERN_INFO "%s: mode %#lx \n", + __func__, readl(&fecp->ESW_MODE)); +#endif +} + +static void esw_switch_mode_configure( + struct switch_enet_private *fep, + unsigned long configure) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + writel(readl(&fecp->ESW_MODE) | configure, &fecp->ESW_MODE); +#ifdef DEBUG_SWITCH_MODE + printk(KERN_INFO "%s: mode %#lx \n", + __func__, reald(&fecp->ESW_MODE)); +#endif +} + + +static void esw_get_bridge_port( + struct switch_enet_private *fep, + unsigned long *ulBMPConfig) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + *ulBMPConfig = readl(&fecp->ESW_BMPC); +#ifdef DEBUG_BRIDGE_PORT + printk(KERN_INFO "%s: bridge management port %#lx \n", + __func__, readl(&fecp->ESW_BMPC)); +#endif +} + +static void esw_bridge_port_configure( + struct switch_enet_private *fep, + unsigned long configure) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + writel(readl(&fecp->ESW_BMPC) | configure, + &fecp->ESW_BMPC); +#ifdef DEBUG_BRIDGE_PORT + printk(KERN_INFO "%s: bridge management port %#lx \n", + __func__, fecp->ESW_BMPC); +#endif +} + +/* The timer should create an interrupt every 4 seconds*/ +static void l2switch_aging_timer(unsigned long data) +{ + struct switch_enet_private *fep; + + fep = (struct switch_enet_private *)data; + + if (fep) { + TIMEINCREMENT(fep->currTime); + fep->timeChanged++; + } + + mod_timer(&fep->timer_aging, jiffies + LEARNING_AGING_TIMER); +} + +void esw_check_rxb_txb_interrupt(struct switch_enet_private *fep) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + + /*Enable Forced forwarding for port 1*/ + writel(MCF_ESW_P0FFEN_FEN | MCF_ESW_P0FFEN_FD(1), + &fecp->ESW_P0FFEN); + /*Disable learning for all ports*/ + + writel(MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF | + MCF_ESW_IMR_LRN | MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF, + &fecp->switch_imask); + printk(KERN_ERR "%s: fecp->ESW_DBCR %#lx, fecp->ESW_P0FFEN %#lx" + " fecp->ESW_BKLR %#lx\n", __func__, fecp->ESW_DBCR, + readl(&fecp->ESW_P0FFEN), + readl(&fecp->ESW_BKLR)); +} + +static int esw_mac_addr_static(struct switch_enet_private *fep) +{ + struct switch_t *fecp; + + fecp = fep->hwp; + writel(MCF_ESW_DBCR_P1, &fecp->ESW_DBCR); + + if (is_valid_ether_addr(fep->netdev->dev_addr)) + esw_update_atable_static(fep->netdev->dev_addr, 7, 7, fep); + else{ + printk(KERN_ERR "Can not add available mac address" + " for switch!!\n"); + return -EFAULT; + } + + return 0; +} + +static void esw_main(struct switch_enet_private *fep) +{ + struct switch_t *fecp; + fecp = fep->hwp; + + esw_mac_addr_static(fep); + writel(0, &fecp->ESW_BKLR); + writel(MCF_ESW_IMR_TXB | MCF_ESW_IMR_TXF | + MCF_ESW_IMR_LRN | MCF_ESW_IMR_RXB | MCF_ESW_IMR_RXF, + &fecp->switch_imask); + writel(0x70007, &fecp->ESW_PER); + writel(MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2, &fecp->ESW_DBCR); +} + +static int switch_enet_ioctl( + struct net_device *dev, + struct ifreq *ifr, int cmd) +{ + struct switch_enet_private *fep; + struct switch_t *fecp; + int ret = 0; + + printk(KERN_INFO "%s cmd %x\n", __func__, cmd); + fep = netdev_priv(dev); + fecp = (struct switch_t *)dev->base_addr; + + switch (cmd) { + case ESW_SET_PORTENABLE_CONF: + { + struct eswIoctlPortEnableConfig configData; + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlPortEnableConfig)); + if (ret) + return -EFAULT; + + ret = esw_port_enable_config(fep, + configData.port, + configData.tx_enable, + configData.rx_enable); + } + break; + case ESW_SET_BROADCAST_CONF: + { + struct eswIoctlPortConfig configData; + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortConfig)); + if (ret) + return -EFAULT; + + ret = esw_port_broadcast_config(fep, + configData.port, configData.enable); + } + break; + + case ESW_SET_MULTICAST_CONF: + { + struct eswIoctlPortConfig configData; + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortConfig)); + if (ret) + return -EFAULT; + + ret = esw_port_multicast_config(fep, + configData.port, configData.enable); + } + break; + + case ESW_SET_BLOCKING_CONF: + { + struct eswIoctlPortConfig configData; + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortConfig)); + + if (ret) + return -EFAULT; + + ret = esw_port_blocking_config(fep, + configData.port, configData.enable); + } + break; + + case ESW_SET_LEARNING_CONF: + { + struct eswIoctlPortConfig configData; + printk(KERN_INFO "ESW_SET_LEARNING_CONF\n"); + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortConfig)); + if (ret) + return -EFAULT; + printk(KERN_INFO "ESW_SET_LEARNING_CONF: %x %x\n", + configData.port, configData.enable); + ret = esw_port_learning_config(fep, + configData.port, configData.enable); + } + break; + + case ESW_SET_IP_SNOOP_CONF: + { + struct eswIoctlIpsnoopConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlIpsnoopConfig)); + if (ret) + return -EFAULT; + printk(KERN_INFO "ESW_SET_IP_SNOOP_CONF:: %x %x %x\n", + configData.num, configData.mode, + configData.ip_header_protocol); + ret = esw_ip_snoop_config(fep, + configData.num, configData.mode, + configData.ip_header_protocol); + } + break; + + case ESW_SET_PORT_SNOOP_CONF: + { + struct eswIoctlPortsnoopConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortsnoopConfig)); + if (ret) + return -EFAULT; + printk(KERN_INFO "ESW_SET_PORT_SNOOP_CONF:: %x %x %x %x\n", + configData.num, configData.mode, + configData.compare_port, configData.compare_num); + ret = esw_tcpudp_port_snoop_config(fep, + configData.num, configData.mode, + configData.compare_port, + configData.compare_num); + } + break; + + case ESW_SET_PORT_MIRROR_CONF: + { + struct eswIoctlPortMirrorConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPortMirrorConfig)); + if (ret) + return -EFAULT; + printk(KERN_INFO "ESW_SET_PORT_MIRROR_CONF:: %x %x %x " + "%s %s\n %x %x %x %x %x %x\n", + configData.mirror_port, configData.port, + configData.mirror_enable, + configData.src_mac, configData.des_mac, + configData.egress_en, configData.ingress_en, + configData.egress_mac_src_en, + configData.egress_mac_des_en, + configData.ingress_mac_src_en, + configData.ingress_mac_des_en); + ret = esw_port_mirroring_config(fep, + configData.mirror_port, configData.port, + configData.mirror_enable, + configData.src_mac, configData.des_mac, + configData.egress_en, configData.ingress_en, + configData.egress_mac_src_en, + configData.egress_mac_des_en, + configData.ingress_mac_src_en, + configData.ingress_mac_des_en); + } + break; + + case ESW_SET_PIRORITY_VLAN: + { + struct eswIoctlPriorityVlanConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlPriorityVlanConfig)); + if (ret) + return -EFAULT; + + ret = esw_framecalssify_vlan_priority_lookup(fep, + configData.port, configData.func_enable, + configData.vlan_pri_table_num, + configData.vlan_pri_table_value); + } + break; + + case ESW_SET_PIRORITY_IP: + { + struct eswIoctlPriorityIPConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlPriorityIPConfig)); + if (ret) + return -EFAULT; + + ret = esw_framecalssify_ip_priority_lookup(fep, + configData.port, configData.func_enable, + configData.ipv4_en, configData.ip_priority_num, + configData.ip_priority_value); + } + break; + + case ESW_SET_PIRORITY_MAC: + { + struct eswIoctlPriorityMacConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlPriorityMacConfig)); + if (ret) + return -EFAULT; + + ret = esw_framecalssify_mac_priority_lookup(fep, + configData.port); + } + break; + + case ESW_SET_PIRORITY_DEFAULT: + { + struct eswIoctlPriorityDefaultConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlPriorityDefaultConfig)); + if (ret) + return -EFAULT; + + ret = esw_frame_calssify_priority_init(fep, + configData.port, configData.priority_value); + } + break; + + case ESW_SET_P0_FORCED_FORWARD: + { + struct eswIoctlP0ForcedForwardConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlP0ForcedForwardConfig)); + if (ret) + return -EFAULT; + + ret = esw_forced_forward(fep, configData.port1, + configData.port2, configData.enable); + } + break; + + case ESW_SET_BRIDGE_CONFIG: + { + unsigned long configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(unsigned long)); + if (ret) + return -EFAULT; + + esw_bridge_port_configure(fep, configData); + } + break; + + case ESW_SET_SWITCH_MODE: + { + unsigned long configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(unsigned long)); + if (ret) + return -EFAULT; + + esw_switch_mode_configure(fep, configData); + } + break; + + case ESW_SET_OUTPUT_QUEUE_MEMORY: + { + struct eswIoctlOutputQueue configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlOutputQueue)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_SET_OUTPUT_QUEUE_MEMORY:: %#x \n" + "%#lx %#lx %#lx %#lx\n" + "%#lx %#lx %#lx\n", + configData.fun_num, + configData.sOutputQueue.ESW_MMSR, + configData.sOutputQueue.ESW_LMT, + configData.sOutputQueue.ESW_LFC, + configData.sOutputQueue.ESW_PCSR, + configData.sOutputQueue.ESW_IOSR, + configData.sOutputQueue.ESW_QWT, + configData.sOutputQueue.ESW_P0BCT); + ret = esw_set_output_queue_memory(fep, + configData.fun_num, &configData.sOutputQueue); + } + break; + + case ESW_SET_VLAN_OUTPUT_PROCESS: + { + struct eswIoctlVlanOutputConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, sizeof(struct eswIoctlVlanOutputConfig)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_SET_VLAN_OUTPUT_PROCESS: %x %x\n", + configData.port, configData.mode); + ret = esw_vlan_output_process(fep, + configData.port, configData.mode); + } + break; + + case ESW_SET_VLAN_INPUT_PROCESS: + { + struct eswIoctlVlanInputConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlVlanInputConfig)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_SET_VLAN_INPUT_PROCESS: %x %x" + "%x %x %x %x\n", + configData.port, configData.mode, + configData.port_vlanid, + configData.vlan_verify_en, + configData.vlan_domain_num, + configData.vlan_domain_port); + ret = esw_vlan_input_process(fep, configData.port, + configData.mode, configData.port_vlanid, + configData.vlan_verify_en, + configData.vlan_domain_num, + configData.vlan_domain_port); + } + break; + + case ESW_SET_VLAN_DOMAIN_VERIFICATION: + { + struct eswIoctlVlanVerificationConfig configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlVlanVerificationConfig)); + if (ret) + return -EFAULT; + + printk("ESW_SET_VLAN_DOMAIN_VERIFICATION: " + "%x %x %x\n", + configData.port, + configData.vlan_domain_verify_en, + configData.vlan_discard_unknown_en); + ret = esw_set_vlan_verification( + fep, configData.port, + configData.vlan_domain_verify_en, + configData.vlan_discard_unknown_en); + } + break; + + case ESW_SET_VLAN_RESOLUTION_TABLE: + { + struct eswIoctlVlanResoultionTable configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlVlanResoultionTable)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_SET_VLAN_RESOLUTION_TABLE: " + "%x %x %x\n", + configData.port_vlanid, + configData.vlan_domain_num, + configData.vlan_domain_port); + + ret = esw_set_vlan_resolution_table( + fep, configData.port_vlanid, + configData.vlan_domain_num, + configData.vlan_domain_port); + + } + break; + case ESW_UPDATE_STATIC_MACTABLE: + { + struct eswIoctlUpdateStaticMACtable configData; + + ret = copy_from_user(&configData, + ifr->ifr_data, + sizeof(struct eswIoctlUpdateStaticMACtable)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "%s: ESW_UPDATE_STATIC_MACTABLE: mac %s, " + "port %x, priority %x\n", __func__, + configData.mac_addr, + configData.port, + configData.priority); + ret = esw_update_atable_static(configData.mac_addr, + configData.port, configData.priority, fep); + } + break; + + case ESW_CLEAR_ALL_MACTABLE: + { + esw_clear_atable(fep); + } + break; + + case ESW_GET_STATISTICS_STATUS: + { + struct esw_statistics_status Statistics; + ret = esw_get_statistics_status(fep, &Statistics); + if (ret != 0) { + printk(KERN_ERR "%s: cmd %x fail\n", + __func__, cmd); + return -1; + } + + ret = copy_to_user(ifr->ifr_data, &Statistics, + sizeof(struct esw_statistics_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT0_STATISTICS_STATUS: + { + struct esw_port_statistics_status PortStatistics; + + ret = esw_get_port_statistics_status(fep, + 0, &PortStatistics); + if (ret != 0) { + printk(KERN_ERR "%s: cmd %x fail\n", + __func__, cmd); + return -1; + } + + ret = copy_to_user(ifr->ifr_data, &PortStatistics, + sizeof(struct esw_port_statistics_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT1_STATISTICS_STATUS: + { + struct esw_port_statistics_status PortStatistics; + + ret = esw_get_port_statistics_status(fep, + 1, &PortStatistics); + if (ret != 0) { + printk(KERN_ERR "%s: cmd %x fail\n", + __func__, cmd); + return -1; + } + + ret = copy_to_user(ifr->ifr_data, &PortStatistics, + sizeof(struct esw_port_statistics_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT2_STATISTICS_STATUS: + { + struct esw_port_statistics_status PortStatistics; + + ret = esw_get_port_statistics_status(fep, + 2, &PortStatistics); + if (ret != 0) { + printk(KERN_ERR "%s: cmd %x fail\n", + __func__, cmd); + return -1; + } + + ret = copy_to_user(ifr->ifr_data, &PortStatistics, + sizeof(struct esw_port_statistics_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_LEARNING_CONF: + { + unsigned long PortLearning; + + esw_get_port_learning(fep, &PortLearning); + ret = copy_to_user(ifr->ifr_data, &PortLearning, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_BLOCKING_CONF: + { + unsigned long PortBlocking; + + esw_get_port_blocking(fep, &PortBlocking); + ret = copy_to_user(ifr->ifr_data, &PortBlocking, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_MULTICAST_CONF: + { + unsigned long PortMulticast; + + esw_get_port_multicast(fep, &PortMulticast); + ret = copy_to_user(ifr->ifr_data, &PortMulticast, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_BROADCAST_CONF: + { + unsigned long PortBroadcast; + + esw_get_port_broadcast(fep, &PortBroadcast); + ret = copy_to_user(ifr->ifr_data, &PortBroadcast, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORTENABLE_CONF: + { + unsigned long PortEnable; + + esw_get_port_enable(fep, &PortEnable); + ret = copy_to_user(ifr->ifr_data, &PortEnable, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_IP_SNOOP_CONF: + { + unsigned long ESW_IPSNP[8]; + + esw_get_ip_snoop_config(fep, (unsigned long *)ESW_IPSNP); + ret = copy_to_user(ifr->ifr_data, ESW_IPSNP, + (8 * sizeof(unsigned long))); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT_SNOOP_CONF: + { + unsigned long ESW_PSNP[8]; + + esw_get_tcpudp_port_snoop_config(fep, + (unsigned long *)ESW_PSNP); + ret = copy_to_user(ifr->ifr_data, ESW_PSNP, + (8 * sizeof(unsigned long))); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_PORT_MIRROR_CONF: + { + struct eswIoctlPortMirrorStatus PortMirrorStatus; + + esw_get_port_mirroring(fep, &PortMirrorStatus); + ret = copy_to_user(ifr->ifr_data, &PortMirrorStatus, + sizeof(struct eswIoctlPortMirrorStatus)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_P0_FORCED_FORWARD: + { + unsigned long ForceForward; + + esw_get_forced_forward(fep, &ForceForward); + ret = copy_to_user(ifr->ifr_data, &ForceForward, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_SWITCH_MODE: + { + unsigned long Config; + + esw_get_switch_mode(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_BRIDGE_CONFIG: + { + unsigned long Config; + + esw_get_bridge_port(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + case ESW_GET_OUTPUT_QUEUE_STATUS: + { + struct esw_output_queue_status Config; + esw_get_output_queue_status(fep, + &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(struct esw_output_queue_status)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_VLAN_OUTPUT_PROCESS: + { + unsigned long Config; + + esw_get_vlan_output_config(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_VLAN_INPUT_PROCESS: + { + struct eswIoctlVlanInputStatus Config; + + esw_get_vlan_input_config(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(struct eswIoctlVlanInputStatus)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_VLAN_RESOLUTION_TABLE: + { + unsigned long Config; + unsigned char ConfigData; + ret = copy_from_user(&ConfigData, + ifr->ifr_data, + sizeof(unsigned char)); + if (ret) + return -EFAULT; + + printk(KERN_INFO "ESW_GET_VLAN_RESOLUTION_TABLE: %x \n", + ConfigData); + + esw_get_vlan_resolution_table(fep, ConfigData, &Config); + + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + + case ESW_GET_VLAN_DOMAIN_VERIFICATION: + { + unsigned long Config; + + esw_get_vlan_verification(fep, &Config); + ret = copy_to_user(ifr->ifr_data, &Config, + sizeof(unsigned long)); + if (ret) + return -EFAULT; + } + break; + /*------------------------------------------------------------------*/ + default: + return -EOPNOTSUPP; + } + + + return ret; +} + +static int +switch_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct switch_enet_private *fep; + struct switch_t *fecp; + struct cbd_t *bdp; + void *bufaddr; + unsigned short status; + unsigned long flags; + + fep = netdev_priv(dev); + fecp = (struct switch_t *)fep->hwp; + + if (!fep->link[0] && !fep->link[1]) { + /* Link is down or autonegotiation is in progress. */ + netif_stop_queue(dev); + return NETDEV_TX_BUSY; + } + + spin_lock_irqsave(&fep->hw_lock, flags); + /* Fill in a Tx ring entry */ + bdp = fep->cur_tx; + + status = bdp->cbd_sc; + + if (status & BD_ENET_TX_READY) { + /* + * Ooops. All transmit buffers are full. Bail out. + * This should not happen, since dev->tbusy should be set. + */ + printk(KERN_ERR "%s: tx queue full!.\n", dev->name); + spin_unlock_irqrestore(&fep->hw_lock, flags); + return NETDEV_TX_BUSY; + } + + /* Clear all of the status flags */ + status &= ~BD_ENET_TX_STATS; + + /* Set buffer length and buffer pointer */ + bufaddr = skb->data; + bdp->cbd_datlen = skb->len; + + /* + * On some FEC implementations data must be aligned on + * 4-byte boundaries. Use bounce buffers to copy data + * and get it aligned. Ugh. + */ + if ((unsigned long) bufaddr & FEC_ALIGNMENT) { + unsigned int index; + index = bdp - fep->tx_bd_base; + memcpy(fep->tx_bounce[index], + (void *)skb->data, skb->len); + bufaddr = fep->tx_bounce[index]; + } + +#ifdef CONFIG_ARCH_MXS + swap_buffer(bufaddr, skb->len); +#endif + + /* Save skb pointer. */ + fep->tx_skbuff[fep->skb_cur] = skb; + + dev->stats.tx_bytes += skb->len; + fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; + + /* + * Push the data cache so the CPM does not get stale memory + * data. + */ + bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr, + FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); + + /* + * Send it on its way. Tell FEC it's ready, interrupt when done, + * it's the last BD of the frame, and to put the CRC on the end. + */ + + status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR + | BD_ENET_TX_LAST | BD_ENET_TX_TC); + bdp->cbd_sc = status; +#ifdef L2SWITCH_ENHANCED_BUFFER + bdp->bdu = 0x00000000; + bdp->ebd_status = TX_BD_INT | TX_BD_TS; +#endif + dev->trans_start = jiffies; + + /* Trigger transmission start */ + writel(MCF_ESW_TDAR_X_DES_ACTIVE, &fecp->fec_x_des_active); + + /* If this was the last BD in the ring, + * start at the beginning again. + */ + if (status & BD_ENET_TX_WRAP) + bdp = fep->tx_bd_base; + else + bdp++; + + if (bdp == fep->dirty_tx) { + fep->tx_full = 1; + netif_stop_queue(dev); + printk(KERN_ERR "%s: net stop\n", __func__); + } + + fep->cur_tx = bdp; + + spin_unlock_irqrestore(&fep->hw_lock, flags); + + return 0; +} + +static void +switch_timeout(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + + printk(KERN_INFO "%s: transmit timed out.\n", dev->name); + dev->stats.tx_errors++; + { + int i; + struct cbd_t *bdp; + + printk(KERN_INFO "Ring data dump: cur_tx %lx%s," + "dirty_tx %lx cur_rx: %lx\n", + (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", + (unsigned long)fep->dirty_tx, + (unsigned long)fep->cur_rx); + + bdp = fep->tx_bd_base; + printk(KERN_INFO " tx: %u buffers\n", TX_RING_SIZE); + for (i = 0 ; i < TX_RING_SIZE; i++) { + printk(KERN_INFO " %08x: %04x %04x %08x\n", + (uint) bdp, + bdp->cbd_sc, + bdp->cbd_datlen, + (int) bdp->cbd_bufaddr); + bdp++; + } + + bdp = fep->rx_bd_base; + printk(KERN_INFO " rx: %lu buffers\n", + (unsigned long) RX_RING_SIZE); + for (i = 0 ; i < RX_RING_SIZE; i++) { + printk(KERN_INFO " %08x: %04x %04x %08x\n", + (uint) bdp, + bdp->cbd_sc, + bdp->cbd_datlen, + (int) bdp->cbd_bufaddr); + bdp++; + } + } + switch_restart(dev, fep->full_duplex); + netif_wake_queue(dev); +} + +/* + * The interrupt handler. + * This is called from the MPC core interrupt. + */ +static irqreturn_t +switch_enet_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct switch_enet_private *fep = netdev_priv(dev); + struct switch_t *fecp; + uint int_events; + irqreturn_t ret = IRQ_NONE; + + fecp = (struct switch_t *)dev->base_addr; + + /* Get the interrupt events that caused us to be here */ + do { + int_events = readl(&fecp->switch_ievent); + writel(int_events, &fecp->switch_ievent); + /* Handle receive event in its own function. */ + + /* Transmit OK, or non-fatal error. Update the buffer + * descriptors. FEC handles all errors, we just discover + * them as part of the transmit process. + */ + if (int_events & MCF_ESW_ISR_LRN) { + if (readl(&fep->learning_irqhandle_enable)) + esw_atable_dynamicms_learn_migration( + fep, fep->currTime); + ret = IRQ_HANDLED; + } + + if (int_events & MCF_ESW_ISR_OD0) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_OD1) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_OD2) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_RXB) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_RXF) { + ret = IRQ_HANDLED; + switch_enet_rx(dev); + } + + if (int_events & MCF_ESW_ISR_TXB) + ret = IRQ_HANDLED; + + if (int_events & MCF_ESW_ISR_TXF) { + ret = IRQ_HANDLED; + switch_enet_tx(dev); + } + + } while (int_events); + + return ret; +} + +static irqreturn_t mac0_enet_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct switch_enet_private *fep = netdev_priv(dev); + uint int_events; + irqreturn_t ret = IRQ_NONE; + + do { + int_events = readl(fep->enet_addr + MCF_FEC_EIR0); + writel(int_events, fep->enet_addr + MCF_FEC_EIR0); + + if (int_events & FEC_ENET_MII) { + ret = IRQ_HANDLED; + complete(&fep->mdio_done); + } + } while (int_events); + + return ret; +} + +static irqreturn_t mac1_enet_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct switch_enet_private *fep = netdev_priv(dev); + uint int_events; + irqreturn_t ret = IRQ_NONE; + + do { + int_events = readl(fep->enet_addr + MCF_FEC_EIR1); + writel(int_events, fep->enet_addr + MCF_FEC_EIR1); + + if (int_events & FEC_ENET_MII) { + ret = IRQ_HANDLED; + complete(&fep->mdio_done); + } + } while (int_events); + + return ret; +} + +static void +switch_enet_tx(struct net_device *dev) +{ + struct switch_enet_private *fep; + struct cbd_t *bdp; + unsigned short status; + struct sk_buff *skb; + + fep = netdev_priv(dev); + spin_lock(&fep->hw_lock); + bdp = fep->dirty_tx; + + while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { + if (bdp == fep->cur_tx && fep->tx_full == 0) + break; + + dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, + FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); + bdp->cbd_bufaddr = 0; + skb = fep->tx_skbuff[fep->skb_dirty]; + /* Check for errors */ + if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | + BD_ENET_TX_RL | BD_ENET_TX_UN | + BD_ENET_TX_CSL)) { + dev->stats.tx_errors++; + if (status & BD_ENET_TX_HB) /* No heartbeat */ + dev->stats.tx_heartbeat_errors++; + if (status & BD_ENET_TX_LC) /* Late collision */ + dev->stats.tx_window_errors++; + if (status & BD_ENET_TX_RL) /* Retrans limit */ + dev->stats.tx_aborted_errors++; + if (status & BD_ENET_TX_UN) /* Underrun */ + dev->stats.tx_fifo_errors++; + if (status & BD_ENET_TX_CSL) /* Carrier lost */ + dev->stats.tx_carrier_errors++; + } else { + dev->stats.tx_packets++; + } + + if (status & BD_ENET_TX_READY) + printk(KERN_ERR "HEY! " + "Enet xmit interrupt and TX_READY.\n"); + /* + * Deferred means some collisions occurred during transmit, + * but we eventually sent the packet OK. + */ + if (status & BD_ENET_TX_DEF) + dev->stats.collisions++; + + /* Free the sk buffer associated with this last transmit */ + dev_kfree_skb_any(skb); + fep->tx_skbuff[fep->skb_dirty] = NULL; + fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; + + /* Update pointer to next buffer descriptor to be transmitted */ + if (status & BD_ENET_TX_WRAP) + bdp = fep->tx_bd_base; + else + bdp++; + + /* + * Since we have freed up a buffer, the ring is no longer + * full. + */ + if (fep->tx_full) { + fep->tx_full = 0; + printk(KERN_ERR "%s: tx full is zero\n", __func__); + if (netif_queue_stopped(dev)) + netif_wake_queue(dev); + } + } + fep->dirty_tx = bdp; + spin_unlock(&fep->hw_lock); +} + + +/* + * During a receive, the cur_rx points to the current incoming buffer. + * When we update through the ring, if the next incoming buffer has + * not been given to the system, we just set the empty indicator, + * effectively tossing the packet. + */ +static void +switch_enet_rx(struct net_device *dev) +{ + struct switch_enet_private *fep; + struct switch_t *fecp; + struct cbd_t *bdp; + unsigned short status; + struct sk_buff *skb; + ushort pkt_len; + __u8 *data; + +#ifdef CONFIG_M532x + flush_cache_all(); +#endif + + fep = netdev_priv(dev); + fecp = (struct switch_t *)fep->hwp; + + spin_lock(&fep->hw_lock); + /* + * First, grab all of the stats for the incoming packet. + * These get messed up if we get called due to a busy condition. + */ + bdp = fep->cur_rx; +#ifdef L2SWITCH_ENHANCED_BUFFER + printk(KERN_INFO "%s: cbd_sc %x cbd_datlen %x cbd_bufaddr %x " + "ebd_status %x bdu %x length_proto_type %x " + "payload_checksum %x\n", + __func__, bdp->cbd_sc, bdp->cbd_datlen, + bdp->cbd_bufaddr, bdp->ebd_status, bdp->bdu, + bdp->length_proto_type, bdp->payload_checksum); +#endif + +while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { + /* + * Since we have allocated space to hold a complete frame, + * the last indicator should be set. + */ + if ((status & BD_ENET_RX_LAST) == 0) + printk(KERN_INFO "SWITCH ENET: rcv is not +last\n"); + + if (!fep->opened) + goto rx_processing_done; + + /* Check for errors. */ + if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | + BD_ENET_RX_CR | BD_ENET_RX_OV)) { + dev->stats.rx_errors++; + if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { + /* Frame too long or too short. */ + dev->stats.rx_length_errors++; + } + if (status & BD_ENET_RX_NO) /* Frame alignment */ + dev->stats.rx_frame_errors++; + if (status & BD_ENET_RX_CR) /* CRC Error */ + dev->stats.rx_crc_errors++; + if (status & BD_ENET_RX_OV) /* FIFO overrun */ + dev->stats.rx_fifo_errors++; + } + + /* + * Report late collisions as a frame error. + * On this error, the BD is closed, but we don't know what we + * have in the buffer. So, just drop this frame on the floor. + */ + if (status & BD_ENET_RX_CL) { + dev->stats.rx_errors++; + dev->stats.rx_frame_errors++; + goto rx_processing_done; + } + + /* Process the incoming frame */ + dev->stats.rx_packets++; + pkt_len = bdp->cbd_datlen; + dev->stats.rx_bytes += pkt_len; + data = (__u8 *)__va(bdp->cbd_bufaddr); + + dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, + DMA_FROM_DEVICE); +#ifdef CONFIG_ARCH_MXS + swap_buffer(data, pkt_len); +#endif + /* + * This does 16 byte alignment, exactly what we need. + * The packet length includes FCS, but we don't want to + * include that when passing upstream as it messes up + * bridging applications. + */ + skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN); + if (unlikely(!skb)) { + printk("%s: Memory squeeze, dropping packet.\n", + dev->name); + dev->stats.rx_dropped++; + } else { + skb_reserve(skb, NET_IP_ALIGN); + skb_put(skb, pkt_len); /* Make room */ + skb_copy_to_linear_data(skb, data, pkt_len); + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + } + + bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, + DMA_FROM_DEVICE); + +rx_processing_done: + + /* Clear the status flags for this buffer */ + status &= ~BD_ENET_RX_STATS; + + /* Mark the buffer empty */ + status |= BD_ENET_RX_EMPTY; + bdp->cbd_sc = status; + + /* Update BD pointer to next entry */ + if (status & BD_ENET_RX_WRAP) + bdp = fep->rx_bd_base; + else + bdp++; + + /* + * Doing this here will keep the FEC running while we process + * incoming frames. On a heavily loaded network, we should be + * able to keep up at the expense of system resources. + */ + writel(MCF_ESW_RDAR_R_DES_ACTIVE, &fecp->fec_r_des_active); + } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ + writel(bdp, &fep->cur_rx); + + spin_unlock(&fep->hw_lock); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Phy section + */ +static void switch_adjust_link0(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct phy_device *phy_dev = fep->phy_dev[0]; + unsigned long flags; + int status_change = 0; + + spin_lock_irqsave(&fep->hw_lock, flags); + + /* Prevent a state halted on mii error */ + if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { + phy_dev->state = PHY_RESUMING; + goto spin_unlock; + } + + /* Duplex link change */ + if (phy_dev->link) { + if (fep->full_duplex != phy_dev->duplex) + status_change = 1; + } + + /* Link on or off change */ + if (phy_dev->link != fep->link[0]) { + fep->link[0] = phy_dev->link; + if (phy_dev->link) { + /* if link becomes up and tx be stopped, start it */ + if (netif_queue_stopped(dev)) { + netif_start_queue(dev); + netif_wake_queue(dev); + } + } + status_change = 1; + } + +spin_unlock: + spin_unlock_irqrestore(&fep->hw_lock, flags); + + if (status_change) + phy_print_status(phy_dev); +} + +static void switch_adjust_link1(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct phy_device *phy_dev = fep->phy_dev[1]; + unsigned long flags; + int status_change = 0; + + spin_lock_irqsave(&fep->hw_lock, flags); + + /* Prevent a state halted on mii error */ + if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { + phy_dev->state = PHY_RESUMING; + goto spin_unlock; + } + + /* Duplex link change */ + if (phy_dev->link) { + if (fep->full_duplex != phy_dev->duplex) + status_change = 1; + } + + /* Link on or off change */ + if (phy_dev->link != fep->link[1]) { + fep->link[1] = phy_dev->link; + if (phy_dev->link) { + /* if link becomes up and tx be stopped, start it */ + if (netif_queue_stopped(dev)) { + netif_start_queue(dev); + netif_wake_queue(dev); + } + } + status_change = 1; + } + +spin_unlock: + spin_unlock_irqrestore(&fep->hw_lock, flags); + + if (status_change) + phy_print_status(phy_dev); +} + +static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + struct switch_enet_private *fep = bus->priv; + unsigned long time_left; + + fep->mii_timeout = 0; + init_completion(&fep->mdio_done); + + /* clear MII end of transfer bit */ + writel(FEC_ENET_MII, fep->enet_addr + FEC_IEVENT + / sizeof(unsigned long)); + + /* start a read op */ + writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | + FEC_MMFR_TA, fep->enet_addr + FEC_MII_DATA + / sizeof(unsigned long)); + + /* wait for end of transfer */ + time_left = wait_for_completion_timeout(&fep->mdio_done, + usecs_to_jiffies(FEC_MII_TIMEOUT)); + if (time_left == 0) { + fep->mii_timeout = 1; + printk(KERN_ERR "FEC: MDIO read timeout\n"); + return -ETIMEDOUT; + } + + /* return value */ + return FEC_MMFR_DATA(readl(fep->enet_addr + FEC_MII_DATA + / sizeof(unsigned long))); +} + +static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, + u16 value) +{ + struct switch_enet_private *fep = bus->priv; + unsigned long time_left; + + fep->mii_timeout = 0; + init_completion(&fep->mdio_done); + + /* start a write op */ + writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | + FEC_MMFR_TA | FEC_MMFR_DATA(value), + fep->enet_addr + FEC_MII_DATA + / sizeof(unsigned long)); + + /* wait for end of transfer */ + time_left = wait_for_completion_timeout(&fep->mdio_done, + usecs_to_jiffies(FEC_MII_TIMEOUT)); + if (time_left == 0) { + fep->mii_timeout = 1; + printk(KERN_ERR "FEC: MDIO write timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int fec_enet_mdio_reset(struct mii_bus *bus) +{ + return 0; +} + +static int fec_enet_mii_probe(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct phy_device *phy_dev[2] = {NULL}; + int phy_addr, i; + + fep->phy_dev[0] = NULL; + fep->phy_dev[1] = NULL; + i = 0; + + /* find the phy, assuming fec index corresponds to addr */ + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (fep->mii_bus->phy_map[phy_addr]) { + phy_dev[i] = fep->mii_bus->phy_map[phy_addr]; + i += 1; + } + if (i > 1) + break; + } + + if (!phy_dev[0] && !phy_dev[1]) { + printk(KERN_ERR "%s: no PHY found\n", dev->name); + return -ENODEV; + } + + /* attach the mac to the phy */ + phy_dev[0] = phy_connect(dev, dev_name(&phy_dev[0]->dev), + &switch_adjust_link0, 0, + fep->phy_interface); + if (IS_ERR(phy_dev[0])) { + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); + return PTR_ERR(phy_dev[0]); + } + + phy_dev[1] = phy_connect(dev, dev_name(&phy_dev[1]->dev), + &switch_adjust_link1, 0, + fep->phy_interface); + if (IS_ERR(phy_dev[1])) { + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); + return PTR_ERR(phy_dev[1]); + } + + /* mask with MAC supported features */ + for (i = 0; i < 2; i++) { + phy_dev[i]->supported &= PHY_BASIC_FEATURES; + phy_dev[i]->advertising = phy_dev[i]->supported; + fep->phy_dev[i] = phy_dev[i]; + } + + fep->link[0] = 0; + fep->link[1] = 0; + fep->full_duplex = 0; + + printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] " + "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name, + fep->phy_dev[0]->drv->name, dev_name(&fep->phy_dev[0]->dev), + fep->phy_dev[0]->irq); + + return 0; +} + +static struct mii_bus *fec_enet_mii_init(struct net_device *dev, + struct platform_device *pdev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + int err = -ENXIO, i; + + fep->mii_timeout = 0; + + /* + * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) + */ + fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; +#ifdef CONFIG_ARCH_MXS + /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */ + fep->phy_speed <<= 2; +#endif + writel(fep->phy_speed, fep->enet_addr + FEC_MII_SPEED / 4); + + fep->mii_bus = mdiobus_alloc(); + if (fep->mii_bus == NULL) { + err = -ENOMEM; + goto err_out; + } + + fep->mii_bus->name = "fec_enet_mii_bus"; + fep->mii_bus->read = fec_enet_mdio_read; + fep->mii_bus->write = fec_enet_mdio_write; + fep->mii_bus->reset = fec_enet_mdio_reset; + snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id); + fep->mii_bus->priv = fep; + fep->mii_bus->parent = &pdev->dev; + + fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); + if (!fep->mii_bus->irq) { + err = -ENOMEM; + goto err_out_free_mdiobus; + } + + for (i = 0; i < PHY_MAX_ADDR; i++) + fep->mii_bus->irq[i] = PHY_POLL; + + platform_set_drvdata(dev, fep->mii_bus); + + if (mdiobus_register(fep->mii_bus)) + goto err_out_free_mdio_irq; + + return fep->mii_bus; + +err_out_free_mdio_irq: + kfree(fep->mii_bus->irq); +err_out_free_mdiobus: + mdiobus_free(fep->mii_bus); +err_out: + return ERR_PTR(err); +} + +static void fec_enet_mii_remove(struct switch_enet_private *fep) +{ + int i; + for (i = 0; i < 2; i++) { + if (fep->phy_dev[i]) + phy_disconnect(fep->phy_dev[i]); + } + mdiobus_unregister(fep->mii_bus); + kfree(fep->mii_bus->irq); + mdiobus_free(fep->mii_bus); +} + +static int fec_enet_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct phy_device *phydev = fep->phy_dev[0]; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_gset(phydev, cmd); +} + +static int fec_enet_set_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct phy_device *phydev = fep->phy_dev[0]; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_sset(phydev, cmd); +} + +static void fec_enet_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct switch_enet_private *fep = netdev_priv(dev); + + strcpy(info->driver, fep->pdev->dev.driver->name); + strcpy(info->version, "Revision: 1.0"); + strcpy(info->bus_info, dev_name(&dev->dev)); +} + +static void fec_enet_free_buffers(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + int i; + struct sk_buff *skb; + struct cbd_t *bdp; + + bdp = fep->rx_bd_base; + for (i = 0; i < RX_RING_SIZE; i++) { + skb = fep->rx_skbuff[i]; + + if (bdp->cbd_bufaddr) + dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, + FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); + if (skb) + dev_kfree_skb(skb); + bdp++; + } + + bdp = fep->tx_bd_base; + for (i = 0; i < TX_RING_SIZE; i++) + kfree(fep->tx_bounce[i]); +} + +static int fec_enet_alloc_buffers(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + int i; + struct sk_buff *skb; + struct cbd_t *bdp; + + bdp = fep->rx_bd_base; + for (i = 0; i < RX_RING_SIZE; i++) { + skb = dev_alloc_skb(SWITCH_ENET_RX_FRSIZE); + if (!skb) { + fec_enet_free_buffers(dev); + return -ENOMEM; + } + fep->rx_skbuff[i] = skb; + + bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, + SWITCH_ENET_RX_FRSIZE, DMA_FROM_DEVICE); + bdp->cbd_sc = BD_ENET_RX_EMPTY; +#ifdef L2SWITCH_ENHANCED_BUFFER + bdp->ebd_status = RX_BD_INT; + bdp->bdu = 0x00000000; +#endif + bdp++; + } + + /* Set the last buffer to wrap. */ + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; + + bdp = fep->tx_bd_base; + for (i = 0; i < TX_RING_SIZE; i++) { + fep->tx_bounce[i] = kmalloc(SWITCH_ENET_TX_FRSIZE, GFP_KERNEL); + + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; +#ifdef L2SWITCH_ENHANCED_BUFFER + bdp->ebd_status = TX_BD_INT; + bdp->bdu = 0x00000000; +#endif + bdp++; + } + + /* Set the last buffer to wrap. */ + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; + + return 0; +} + +static int +switch_enet_open(struct net_device *dev) +{ + int ret; + struct switch_enet_private *fep = netdev_priv(dev); + /* I should reset the ring buffers here, but I don't yet know + * a simple way to do that. + */ + clk_enable(fep->clk); + ret = fec_enet_alloc_buffers(dev); + if (ret) + return ret; + + fep->link[0] = 0; + fep->link[1] = 0; + /* Probe and connect to PHY when open the interface */ + ret = fec_enet_mii_probe(dev); + if (ret) { + fec_enet_free_buffers(dev); + return ret; + } + phy_start(fep->phy_dev[0]); + phy_start(fep->phy_dev[1]); + fep->old_link = 0; + fep->link[0] = 1; + fep->link[1] = 1; + + switch_restart(dev, 1); + + fep->currTime = 0; + fep->learning_irqhandle_enable = 1; + + esw_main(fep); + + netif_start_queue(dev); + fep->opened = 1; + + return 0; /* Success */ +} + +static int +switch_enet_close(struct net_device *dev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + int i; + + fep->opened = 0; + + switch_stop(dev); + for (i = 0; i < 2; i++) { + if (fep->phy_dev[i]) { + phy_stop(fep->phy_dev[i]); + phy_disconnect(fep->phy_dev[i]); + } + phy_write(fep->phy_dev[i], MII_BMCR, BMCR_PDOWN); + } + + fec_enet_free_buffers(dev); + clk_disable(fep->clk); + + return 0; +} + +/* + * Set or clear the multicast filter for this adaptor. + * Skeleton taken from sunlance driver. + * The CPM Ethernet implementation allows Multicast as well as individual + * MAC address filtering. Some of the drivers check to make sure it is + * a group multicast address, and discard those that are not. I guess I + * will do the same for now, but just remove the test if you want + * individual filtering as well (do the upper net layers want or support + * this kind of feature?). + */ + +/* bits in hash */ +#define HASH_BITS 6 +#define CRC32_POLY 0xEDB88320 + +static void set_multicast_list(struct net_device *dev) +{ + struct switch_enet_private *fep; + struct switch_t *ep; + unsigned int i, bit, data, crc; + + fep = netdev_priv(dev); + ep = fep->hwp; + + if (dev->flags & IFF_PROMISC) { + /* ep->fec_r_cntrl |= 0x0008; */ + printk(KERN_INFO "%s IFF_PROMISC\n", __func__); + } else { + + /* ep->fec_r_cntrl &= ~0x0008; */ + + if (dev->flags & IFF_ALLMULTI) { + /* + * Catch all multicast addresses, so set the + * filter to all 1's. + */ + printk(KERN_INFO "%s IFF_ALLMULTI\n", __func__); + } else { + /* + * Clear filter and add the addresses + * in hash register + */ + /* + * ep->fec_grp_hash_table_high = 0; + * ep->fec_grp_hash_table_low = 0; + */ + struct netdev_hw_addr *ha; + u_char *addrs; + netdev_for_each_mc_addr(ha, dev) { + addrs = ha->addr; + /* Only support group multicast for now */ + if (!(*addrs & 1)) + continue; + + /* calculate crc32 value of mac address */ + crc = 0xffffffff; + + for (i = 0; i < 6; i++) { + data = addrs[i]; + for (bit = 0; bit < 8; bit++, + data >>= 1) { + crc = (crc >> 1) ^ + (((crc ^ data) & 1) ? + CRC32_POLY : 0); + } + } + + } + } + } +} + +/* Set a MAC change in hardware */ +static int +switch_set_mac_address(struct net_device *dev, void *p) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct sockaddr *addr = p; + struct switch_t *fecp; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + fecp = fep->hwp; + writel(MCF_ESW_DBCR_P1, &fecp->ESW_DBCR); + + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + + writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | + (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), + fep->enet_addr + MCF_FEC_PAUR0); + writel((dev->dev_addr[5] << 16) + | ((dev->dev_addr[4]+(unsigned char)(0)) << 24), + fep->enet_addr + MCF_FEC_PAUR0); + + writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | + (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), + fep->enet_addr + MCF_FEC_PAUR1); + writel((dev->dev_addr[5] << 16) + | ((dev->dev_addr[4]+(unsigned char)(1)) << 24), + fep->enet_addr + MCF_FEC_PAUR1); + + esw_update_atable_static(dev->dev_addr, 7, 7, fep); + writel(MCF_ESW_DBCR_P1 | MCF_ESW_DBCR_P2, &fecp->ESW_DBCR); + + return 0; +} + +static struct ethtool_ops fec_enet_ethtool_ops = { + .get_settings = fec_enet_get_settings, + .set_settings = fec_enet_set_settings, + .get_drvinfo = fec_enet_get_drvinfo, + .get_link = ethtool_op_get_link, + }; +static const struct net_device_ops fec_netdev_ops = { + .ndo_open = switch_enet_open, + .ndo_stop = switch_enet_close, + .ndo_do_ioctl = switch_enet_ioctl, + .ndo_start_xmit = switch_enet_start_xmit, + .ndo_set_multicast_list = set_multicast_list, + .ndo_tx_timeout = switch_timeout, + .ndo_set_mac_address = switch_set_mac_address, +}; + +static int switch_mac_addr_setup(char *mac_addr) +{ + char *ptr, *p = mac_addr; + unsigned long tmp; + int i = 0, ret = 0; + + while (p && (*p) && i < 6) { + ptr = strchr(p, ':'); + if (ptr) + *ptr++ = '\0'; + if (strlen(p)) { + ret = strict_strtoul(p, 16, &tmp); + if (ret < 0 || tmp > 0xff) + break; + switch_mac_default[i++] = tmp; + } + p = ptr; + } + + return 0; +} + +__setup("fec_mac=", switch_mac_addr_setup); + +/* Initialize the FEC Ethernet */ +static int __init switch_enet_init(struct net_device *dev, + int slot, struct platform_device *pdev) +{ + struct switch_enet_private *fep = netdev_priv(dev); + struct resource *r; + struct cbd_t *bdp; + struct cbd_t *cbd_base; + struct switch_t *fecp; + int i; + struct switch_platform_data *plat = pdev->dev.platform_data; + + /* Only allow us to be probed once. */ + if (slot >= SWITCH_MAX_PORTS) + return -ENXIO; + + /* Allocate memory for buffer descriptors */ + cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, + GFP_KERNEL); + if (!cbd_base) { + printk(KERN_ERR "FEC: allocate descriptor memory failed?\n"); + return -ENOMEM; + } + + spin_lock_init(&fep->hw_lock); + spin_lock_init(&fep->mii_lock); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) + return -ENXIO; + + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (!r) + return -EBUSY; + + fep->enet_addr = ioremap(r->start, resource_size(r)); + + dev->irq = platform_get_irq(pdev, 0); + fep->mac0_irq = platform_get_irq(pdev, 1); + fep->mac1_irq = platform_get_irq(pdev, 2); + + /* + * Create an Ethernet device instance. + * The switch lookup address memory start 0x800FC000 + */ + fecp = (struct switch_t *)(fep->enet_addr + ENET_SWI_PHYS_ADDR_OFFSET + / sizeof(unsigned long)); + plat->switch_hw[1] = (unsigned long)fecp + MCF_ESW_LOOKUP_MEM_OFFSET; + + fep->index = slot; + fep->hwp = fecp; + fep->hwentry = (struct eswAddrTable_t *)plat->switch_hw[1]; + fep->netdev = dev; +#ifdef CONFIG_FEC_SHARED_PHY + fep->phy_hwp = (struct switch_t *) plat->switch_hw[slot & ~1]; +#else + fep->phy_hwp = fecp; +#endif + + fep->clk = clk_get(&pdev->dev, "fec_clk"); + if (IS_ERR(fep->clk)) + return PTR_ERR(fep->clk); + clk_enable(fep->clk); + + + /* PHY reset should be done during clock on */ + if (plat) { + fep->phy_interface = plat->fec_enet->phy; + if (plat->fec_enet->init && plat->fec_enet->init()) + return -EIO; + + /* + * The priority for getting MAC address is: + * (1) kernel command line fec_mac = xx:xx:xx... + * (2) platform data mac field got from fuse etc + * (3) bootloader set the FEC mac register + */ + + if (!is_valid_ether_addr(switch_mac_default) && + plat->fec_enet->mac && + is_valid_ether_addr(plat->fec_enet->mac)) + memcpy(switch_mac_default, plat->fec_enet->mac, + sizeof(switch_mac_default)); + } else + fep->phy_interface = PHY_INTERFACE_MODE_MII; + + /* Enable MII mode */ + + /* + * SWITCH CONFIGURATION + */ + writel(MCF_ESW_MODE_SW_RST, &fecp->ESW_MODE); + udelay(10); + + /* enable switch*/ + writel(MCF_ESW_MODE_STATRST, &fecp->ESW_MODE); + writel(MCF_ESW_MODE_SW_EN, &fecp->ESW_MODE); + + /* Enable transmit/receive on all ports */ + writel(0xffffffff, &fecp->ESW_PER); + /* Management port configuration, + * make port 0 as management port + */ + writel(0, &fecp->ESW_BMPC); + + /* clear all switch irq */ + writel(0xffffffff, &fecp->switch_ievent); + writel(0, &fecp->switch_imask); + udelay(10); + + plat->request_intrs = switch_request_intrs; + plat->set_mii = switch_set_mii; + plat->get_mac = switch_get_mac; + plat->enable_phy_intr = switch_enable_phy_intr; + plat->disable_phy_intr = switch_disable_phy_intr; + plat->phy_ack_intr = switch_phy_ack_intr; + plat->localhw_setup = switch_localhw_setup; + plat->uncache = switch_uncache; + plat->platform_flush_cache = switch_platform_flush_cache; + + /* + * Set the Ethernet address. If using multiple Enets on the 8xx, + * this needs some work to get unique addresses. + * + * This is our default MAC address unless the user changes + * it via eth_mac_addr (our dev->set_mac_addr handler). + */ + if (plat && plat->get_mac) + plat->get_mac(dev); + + /* Set receive and transmit descriptor base */ + fep->rx_bd_base = cbd_base; + fep->tx_bd_base = cbd_base + RX_RING_SIZE; + + /* Initialize the receive buffer descriptors */ + bdp = fep->rx_bd_base; + for (i = 0; i < RX_RING_SIZE; i++) { + bdp->cbd_sc = 0; + +#ifdef L2SWITCH_ENHANCED_BUFFER + bdp->bdu = 0x00000000; + bdp->ebd_status = RX_BD_INT; +#endif + bdp++; + } + + /* Set the last buffer to wrap */ + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; + + /* ...and the same for transmmit */ + bdp = fep->tx_bd_base; + for (i = 0; i < TX_RING_SIZE; i++) { + /* Initialize the BD for every fragment in the page */ + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; + bdp++; + } + + /* Set the last buffer to wrap */ + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; + + /* + * Install our interrupt handlers. This varies depending on + * the architecture. + */ + if (plat && plat->request_intrs) + plat->request_intrs(dev, switch_enet_interrupt, dev); + + if (request_irq(fep->mac0_irq, mac0_enet_interrupt, IRQF_DISABLED, + "enet-1588", dev)) + printk(KERN_ERR "IEEE1588: failed to request irq\n"); + if (request_irq(fep->mac1_irq, mac1_enet_interrupt, IRQF_DISABLED, + "enet-1588", dev)) + printk(KERN_ERR "IEEE1588: failed to request irq\n"); + + dev->base_addr = (unsigned long)fecp; + + /* The FEC Ethernet specific entries in the device structure. */ + dev->netdev_ops = &fec_netdev_ops; + dev->ethtool_ops = &fec_enet_ethtool_ops; + + /* setup MII interface */ + if (plat && plat->set_mii) + plat->set_mii(dev); + + +#ifndef CONFIG_FEC_SHARED_PHY + fep->phy_addr = 0; +#else + fep->phy_addr = fep->index; +#endif + + fep->sequence_done = 1; + return 0; +} + +static void enet_reset(struct net_device *dev, int duplex) +{ + struct switch_enet_private *fep = netdev_priv(dev); + + /* ECR */ + writel(MCF_FEC_ECR_MAGIC_ENA, + fep->enet_addr + MCF_FEC_ECR0); + writel(MCF_FEC_ECR_MAGIC_ENA, + fep->enet_addr + MCF_FEC_ECR1); + + /* EMRBR */ + writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR0); + writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR1); + + /* + * set the receive and transmit BDs ring base to + * hardware registers(ERDSR & ETDSR) + */ + writel(fep->bd_dma, fep->enet_addr + MCF_FEC_ERDSR0); + writel(fep->bd_dma, fep->enet_addr + MCF_FEC_ERDSR1); + writel((unsigned long)fep->bd_dma + sizeof(struct cbd_t) * RX_RING_SIZE, + fep->enet_addr + MCF_FEC_ETDSR0); + writel((unsigned long)fep->bd_dma + sizeof(struct cbd_t) * RX_RING_SIZE, + fep->enet_addr + MCF_FEC_ETDSR1); +#ifdef CONFIG_ARCH_MXS + /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it */ + writel(fep->phy_speed, + fep->enet_addr + MCF_FEC_MSCR0); + writel(fep->phy_speed, + fep->enet_addr + MCF_FEC_MSCR1); +#endif + fep->full_duplex = duplex; + + /* EIR */ + writel(0, fep->enet_addr + MCF_FEC_EIR0); + writel(0, fep->enet_addr + MCF_FEC_EIR1); + + /* IAUR */ + writel(0, fep->enet_addr + MCF_FEC_IAUR0); + writel(0, fep->enet_addr + MCF_FEC_IAUR1); + + /* IALR */ + writel(0, fep->enet_addr + MCF_FEC_IALR0); + writel(0, fep->enet_addr + MCF_FEC_IALR1); + + /* GAUR */ + writel(0, fep->enet_addr + MCF_FEC_GAUR0); + writel(0, fep->enet_addr + MCF_FEC_GAUR1); + + /* GALR */ + writel(0, fep->enet_addr + MCF_FEC_GALR0); + writel(0, fep->enet_addr + MCF_FEC_GALR1); + + /* EMRBR */ + writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR0); + writel(PKT_MAXBLR_SIZE, fep->enet_addr + MCF_FEC_EMRBR1); + + /* EIMR */ + writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, + fep->enet_addr + MCF_FEC_EIMR0); + writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, + fep->enet_addr + MCF_FEC_EIMR1); + + /* PALR PAUR */ + /* Set the station address for the ENET Adapter */ + writel(dev->dev_addr[3] | + dev->dev_addr[2]<<8 | + dev->dev_addr[1]<<16 | + dev->dev_addr[0]<<24, fep->enet_addr + MCF_FEC_PALR0); + writel(dev->dev_addr[5]<<16 | + (dev->dev_addr[4]+(unsigned char)(0))<<24, + fep->enet_addr + MCF_FEC_PAUR0); + writel(dev->dev_addr[3] | + dev->dev_addr[2]<<8 | + dev->dev_addr[1]<<16 | + dev->dev_addr[0]<<24, fep->enet_addr + MCF_FEC_PALR1); + writel(dev->dev_addr[5]<<16 | + (dev->dev_addr[4]+(unsigned char)(1))<<24, + fep->enet_addr + MCF_FEC_PAUR1); + + /* RCR */ + writel(readl(fep->enet_addr + MCF_FEC_RCR0) + | MCF_FEC_RCR_FCE | MCF_FEC_RCR_PROM, + fep->enet_addr + MCF_FEC_RCR0); + writel(readl(fep->enet_addr + MCF_FEC_RCR1) + | MCF_FEC_RCR_FCE | MCF_FEC_RCR_PROM, + fep->enet_addr + MCF_FEC_RCR1); + + /* TCR */ + writel(0x1c, fep->enet_addr + MCF_FEC_TCR0); + writel(0x1c, fep->enet_addr + MCF_FEC_TCR1); + + /* ECR */ + writel(readl(fep->enet_addr + MCF_FEC_ECR0) | MCF_FEC_ECR_ETHER_EN, + fep->enet_addr + MCF_FEC_ECR0); + writel(readl(fep->enet_addr + MCF_FEC_ECR1) | MCF_FEC_ECR_ETHER_EN, + fep->enet_addr + MCF_FEC_ECR1); +} + +/* + * This function is called to start or restart the FEC during a link + * change. This only happens when switching between half and full + * duplex. + */ +static void +switch_restart(struct net_device *dev, int duplex) +{ + struct switch_enet_private *fep; + struct switch_t *fecp; + int i; + struct switch_platform_data *plat; + + fep = netdev_priv(dev); + fecp = fep->hwp; + plat = fep->pdev->dev.platform_data; + /* + * Whack a reset. We should wait for this. + */ + /* fecp->fec_ecntrl = 1; */ + writel(MCF_ESW_MODE_SW_RST, &fecp->ESW_MODE); + udelay(10); + writel(MCF_ESW_MODE_STATRST, &fecp->ESW_MODE); + writel(MCF_ESW_MODE_SW_EN, &fecp->ESW_MODE); + + /* Enable transmit/receive on all ports */ + writel(0xffffffff, &fecp->ESW_PER); + /* + * Management port configuration, + * make port 0 as management port + */ + writel(0, &fecp->ESW_BMPC); + + /* Clear any outstanding interrupt */ + writel(0xffffffff, &fecp->switch_ievent); + /*if (plat && plat->enable_phy_intr) + * plat->enable_phy_intr(); + */ + + /* Reset all multicast */ + /* + * fecp->fec_grp_hash_table_high = 0; + * fecp->fec_grp_hash_table_low = 0; + */ + + /* Set maximum receive buffer size */ + writel(PKT_MAXBLR_SIZE, &fecp->fec_r_buff_size); + + if (plat && plat->localhw_setup) + plat->localhw_setup(); + + /* Set receive and transmit descriptor base */ + writel(fep->bd_dma, &fecp->fec_r_des_start); + writel((unsigned long)fep->bd_dma + + sizeof(struct cbd_t) * RX_RING_SIZE, + &fecp->fec_x_des_start); + + fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; + fep->cur_rx = fep->rx_bd_base; + + /* Reset SKB transmit buffers */ + fep->skb_cur = fep->skb_dirty = 0; + for (i = 0; i <= TX_RING_MOD_MASK; i++) { + if (fep->tx_skbuff[i] != NULL) { + dev_kfree_skb_any(fep->tx_skbuff[i]); + fep->tx_skbuff[i] = NULL; + } + } + + enet_reset(dev, duplex); + esw_clear_atable(fep); + + /* And last, enable the transmit and receive processing */ + writel(MCF_ESW_RDAR_R_DES_ACTIVE, &fecp->fec_r_des_active); + + /* Enable interrupts we wish to service */ + writel(0xffffffff, &fecp->switch_ievent); + writel(MCF_ESW_IMR_RXF | MCF_ESW_IMR_TXF | + MCF_ESW_IMR_RXB | MCF_ESW_IMR_TXB, + &fecp->switch_imask); + +#ifdef SWITCH_DEBUG + printk(KERN_INFO "%s: switch hw init over." + "isr %x mask %x rx_addr %x %x tx_addr %x %x." + "fec_r_buff_size %x\n", __func__, + readl(&fecp->switch_ievent), + readl(&fecp->switch_imask), + readl(&fecp->fec_r_des_start), + &fecp->fec_r_des_start, + readl(&fecp->fec_x_des_start), + &fecp->fec_x_des_start, + readl(&fecp->fec_r_buff_size)); + printk(KERN_INFO "%s: fecp->ESW_DBCR %x, fecp->ESW_P0FFEN %x fecp->ESW_BKLR %x\n", + __func__, + readl(&fecp->ESW_DBCR), + readl(&fecp->ESW_P0FFEN), + readl(&fecp->ESW_BKLR)); + + printk(KERN_INFO "fecp->portstats[0].MCF_ESW_POQC %x," + "fecp->portstats[0].MCF_ESW_PMVID %x," + "fecp->portstats[0].MCF_ESW_PMVTAG %x," + "fecp->portstats[0].MCF_ESW_PBL %x\n", + readl(&fecp->port_statistics_status[0].MCF_ESW_POQC), + readl(&fecp->port_statistics_status[0].MCF_ESW_PMVID), + readl(&fecp->port_statistics_status[0].MCF_ESW_PMVTAG), + readl(&fecp->port_statistics_status[0].MCF_ESW_PBL)); + + printk(KERN_INFO "fecp->portstats[1].MCF_ESW_POQC %x," + "fecp->portstats[1].MCF_ESW_PMVID %x," + "fecp->portstats[1].MCF_ESW_PMVTAG %x," + "fecp->portstats[1].MCF_ESW_PBL %x\n", + readl(&fecp->port_statistics_status[1].MCF_ESW_POQC), + readl(&fecp->port_statistics_status[1].MCF_ESW_PMVID), + readl(&fecp->port_statistics_status[1].MCF_ESW_PMVTAG), + readl(&fecp->port_statistics_status[1].MCF_ESW_PBL)); + + printk(KERN_INFO "fecp->portstats[2].MCF_ESW_POQC %x," + "fecp->portstats[2].MCF_ESW_PMVID %x," + "fecp->portstats[2].MCF_ESW_PMVTAG %x," + "fecp->portstats[2].MCF_ESW_PBL %x\n", + readl(&fecp->port_statistics_status[2].MCF_ESW_POQC), + readl(&fecp->port_statistics_status[2].MCF_ESW_PMVID), + readl(&fecp->port_statistics_status[2].MCF_ESW_PMVTAG), + readl(&fecp->port_statistics_status[2].MCF_ESW_PBL)); +#endif +} + +static void +switch_stop(struct net_device *dev) +{ + struct switch_t *fecp; + struct switch_enet_private *fep; + struct switch_platform_data *plat; + +#ifdef SWITCH_DEBUG + printk(KERN_ERR "%s\n", __func__); +#endif + fep = netdev_priv(dev); + fecp = fep->hwp; + plat = fep->pdev->dev.platform_data; + /* We cannot expect a graceful transmit stop without link !!! */ + if (fep->link[0] || fep->link[1]) + udelay(10); + + /* Whack a reset. We should wait for this */ + netif_stop_queue(dev); + fep->link[0] = 0; + fep->link[1] = 0; + udelay(10); +} + +static int __init eth_switch_probe(struct platform_device *pdev) +{ + struct net_device *dev; + int i, err; + struct switch_enet_private *fep; + struct switch_platform_private *chip; + + printk(KERN_INFO "Ethernet Switch Version 1.0\n"); + chip = kzalloc(sizeof(struct switch_platform_private) + + sizeof(struct switch_enet_private *) * SWITCH_MAX_PORTS, + GFP_KERNEL); + if (!chip) { + err = -ENOMEM; + printk(KERN_ERR "%s: kzalloc fail %x\n", __func__, + (unsigned int)chip); + return err; + } + + chip->pdev = pdev; + chip->num_slots = SWITCH_MAX_PORTS; + platform_set_drvdata(pdev, chip); + + for (i = 0; (i < chip->num_slots); i++) { + dev = alloc_etherdev(sizeof(struct switch_enet_private)); + if (!dev) { + printk(KERN_ERR "%s: ethernet switch\ + alloc_etherdev fail\n", + dev->name); + return -ENOMEM; + } + + fep = netdev_priv(dev); + fep->pdev = pdev; + printk(KERN_ERR "%s: ethernet switch port %d init\n", + __func__, i); + err = switch_enet_init(dev, i, pdev); + if (err) { + free_netdev(dev); + platform_set_drvdata(pdev, NULL); + kfree(chip); + continue; + } + + chip->fep_host[i] = fep; + + /* Init phy bus */ + if (pdev->id == 0) { + fec_mii_bus = fec_enet_mii_init(dev, pdev); + if (IS_ERR(fec_mii_bus)) + printk(KERN_ERR "can't init phy bus\n"); + } else + fep->mii_bus = fec_mii_bus; + + /* setup timer for Learning Aging function */ + /* + * setup_timer(&fep->timer_aging, + * l2switch_aging_timer, (unsigned long)fep); + */ + init_timer(&fep->timer_aging); + fep->timer_aging.function = l2switch_aging_timer; + fep->timer_aging.data = (unsigned long) fep; + fep->timer_aging.expires = jiffies + LEARNING_AGING_TIMER; + + /* register network device */ + if (register_netdev(dev) != 0) { + free_netdev(dev); + platform_set_drvdata(pdev, NULL); + kfree(chip); + printk(KERN_ERR "%s: ethernet switch register_netdev fail\n", + dev->name); + return -EIO; + } + printk(KERN_INFO "%s: ethernet switch %pM\n", + dev->name, dev->dev_addr); + } + + return 0; +} + +static int eth_switch_remove(struct platform_device *pdev) +{ + int i; + struct net_device *dev; + struct switch_enet_private *fep; + struct switch_platform_private *chip; + + chip = platform_get_drvdata(pdev); + if (chip) { + for (i = 0; i < chip->num_slots; i++) { + fep = chip->fep_host[i]; + dev = fep->netdev; + fep->sequence_done = 1; + fec_enet_mii_remove(fep); + unregister_netdev(dev); + free_netdev(dev); + + del_timer_sync(&fep->timer_aging); + } + + platform_set_drvdata(pdev, NULL); + kfree(chip); + + } else + printk(KERN_ERR "%s: can not get the " + "switch_platform_private %x\n", __func__, + (unsigned int)chip); + + return 0; +} + +static struct platform_driver eth_switch_driver = { + .probe = eth_switch_probe, + .remove = eth_switch_remove, + .driver = { + .name = "mxs-l2switch", + .owner = THIS_MODULE, + }, +}; + +static int __init fec_l2switch_init(void) +{ + return platform_driver_register(ð_switch_driver);; +} + +static void __exit fec_l2_switch_exit(void) +{ + platform_driver_unregister(ð_switch_driver); +} + +module_init(fec_l2switch_init); +module_exit(fec_l2_switch_exit); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/fec_switch.h b/drivers/net/fec_switch.h new file mode 100644 index 000000000000..bb58c29c7490 --- /dev/null +++ b/drivers/net/fec_switch.h @@ -0,0 +1,1126 @@ +/****************************************************************************/ + +/* + * mcfswitch -- L2 Switch Controller for Modelo ColdFire SoC + * processors. + * + * Copyright (C) 2010 Freescale Semiconductor,Inc.All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + * + */ + +/****************************************************************************/ +#ifndef SWITCH_H +#define SWITCH_H +/****************************************************************************/ +/* The Switch stores dest/src/type, data, and checksum for receive packets. + */ +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 + +/* + * The 5441x RX control register also contains maximum frame + * size bits. + */ +#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) + +/* + * Some hardware gets it MAC address out of local flash memory. + * if this is non-zero then assume it is the address to get MAC from. + */ +#define FEC_FLASHMAC 0 + +/* The number of Tx and Rx buffers. These are allocated from the page + * pool. The code may assume these are power of two, so it it best + * to keep them that size. + * We don't need to allocate pages for the transmitter. We just use + * the skbuffer directly. + */ +#ifdef CONFIG_SWITCH_DMA_USE_SRAM +#define SWITCH_ENET_RX_PAGES 6 +#else +#define SWITCH_ENET_RX_PAGES 8 +#endif + +#define SWITCH_ENET_RX_FRSIZE 2048 +#define SWITCH_ENET_RX_FRPPG (PAGE_SIZE / SWITCH_ENET_RX_FRSIZE) +#define RX_RING_SIZE (SWITCH_ENET_RX_FRPPG * SWITCH_ENET_RX_PAGES) +#define SWITCH_ENET_TX_FRSIZE 2048 +#define SWITCH_ENET_TX_FRPPG (PAGE_SIZE / SWITCH_ENET_TX_FRSIZE) + +#ifdef CONFIG_SWITCH_DMA_USE_SRAM +#define TX_RING_SIZE 8 /* Must be power of two */ +#define TX_RING_MOD_MASK 7 /* for this to work */ +#else +#define TX_RING_SIZE 16 /* Must be power of two */ +#define TX_RING_MOD_MASK 15 /* for this to work */ +#endif + +#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) +#error "L2SWITCH: descriptor ring size constants too large" +#endif + +/*-----------------------------------------------------------------------*/ +struct esw_output_queue_status { + unsigned long ESW_MMSR; + unsigned long ESW_LMT; + unsigned long ESW_LFC; + unsigned long ESW_PCSR; + unsigned long ESW_IOSR; + unsigned long ESW_QWT; + unsigned long esw_reserved; + unsigned long ESW_P0BCT; +}; +struct esw_statistics_status { + /* + * Total number of incoming frames processed + * but discarded in switch + */ + unsigned long ESW_DISCN; + /*Sum of bytes of frames counted in ESW_DISCN*/ + unsigned long ESW_DISCB; + /* + * Total number of incoming frames processed + * but not discarded in switch + */ + unsigned long ESW_NDISCN; + /*Sum of bytes of frames counted in ESW_NDISCN*/ + unsigned long ESW_NDISCB; +}; + +struct esw_port_statistics_status { + /*outgoing frames discarded due to transmit queue congestion*/ + unsigned long MCF_ESW_POQC; + /*incoming frames discarded due to VLAN domain mismatch*/ + unsigned long MCF_ESW_PMVID; + /*incoming frames discarded due to untagged discard*/ + unsigned long MCF_ESW_PMVTAG; + /*incoming frames discarded due port is in blocking state*/ + unsigned long MCF_ESW_PBL; +}; + +struct switch_t { + unsigned long ESW_REVISION; + unsigned long ESW_SCRATCH; + unsigned long ESW_PER; + unsigned long reserved0[1]; + unsigned long ESW_VLANV; + unsigned long ESW_DBCR; + unsigned long ESW_DMCR; + unsigned long ESW_BKLR; + unsigned long ESW_BMPC; + unsigned long ESW_MODE; + unsigned long ESW_VIMSEL; + unsigned long ESW_VOMSEL; + unsigned long ESW_VIMEN; + unsigned long ESW_VID;/*0x34*/ + /*from 0x38 0x3C*/ + unsigned long esw_reserved0[2]; + unsigned long ESW_MCR;/*0x40*/ + unsigned long ESW_EGMAP; + unsigned long ESW_INGMAP; + unsigned long ESW_INGSAL; + unsigned long ESW_INGSAH; + unsigned long ESW_INGDAL; + unsigned long ESW_INGDAH; + unsigned long ESW_ENGSAL; + unsigned long ESW_ENGSAH; + unsigned long ESW_ENGDAL; + unsigned long ESW_ENGDAH; + unsigned long ESW_MCVAL;/*0x6C*/ + /*from 0x70--0x7C*/ + unsigned long esw_reserved1[4]; + unsigned long ESW_MMSR;/*0x80*/ + unsigned long ESW_LMT; + unsigned long ESW_LFC; + unsigned long ESW_PCSR; + unsigned long ESW_IOSR; + unsigned long ESW_QWT;/*0x94*/ + unsigned long esw_reserved2[1];/*0x98*/ + unsigned long ESW_P0BCT;/*0x9C*/ + /*from 0xA0-0xB8*/ + unsigned long esw_reserved3[7]; + unsigned long ESW_P0FFEN;/*0xBC*/ + unsigned long ESW_PSNP[8]; + unsigned long ESW_IPSNP[8]; + unsigned long ESW_PVRES[3]; + /*from 0x10C-0x13C*/ + unsigned long esw_reserved4[13]; + unsigned long ESW_IPRES;/*0x140*/ + /*from 0x144-0x17C*/ + unsigned long esw_reserved5[15]; + unsigned long ESW_PRES[3]; + /*from 0x18C-0x1FC*/ + unsigned long esw_reserved6[29]; + unsigned long ESW_PID[3]; + /*from 0x20C-0x27C*/ + unsigned long esw_reserved7[29]; + unsigned long ESW_VRES[32]; + unsigned long ESW_DISCN;/*0x300*/ + unsigned long ESW_DISCB; + unsigned long ESW_NDISCN; + unsigned long ESW_NDISCB;/*0xFC0DC30C*/ + struct esw_port_statistics_status port_statistics_status[3]; + /*from 0x340-0x400*/ + unsigned long esw_reserved8[48]; + + /*0xFC0DC400---0xFC0DC418*/ + /*unsigned long MCF_ESW_ISR;*/ + unsigned long switch_ievent; /* Interrupt event reg */ + /*unsigned long MCF_ESW_IMR;*/ + unsigned long switch_imask; /* Interrupt mask reg */ + /*unsigned long MCF_ESW_RDSR;*/ + unsigned long fec_r_des_start; /* Receive descriptor ring */ + /*unsigned long MCF_ESW_TDSR;*/ + unsigned long fec_x_des_start; /* Transmit descriptor ring */ + /*unsigned long MCF_ESW_MRBR;*/ + unsigned long fec_r_buff_size; /* Maximum receive buff size */ + /*unsigned long MCF_ESW_RDAR;*/ + unsigned long fec_r_des_active; /* Receive descriptor reg */ + /*unsigned long MCF_ESW_TDAR;*/ + unsigned long fec_x_des_active; /* Transmit descriptor reg */ + /*from 0x420-0x4FC*/ + unsigned long esw_reserved9[57]; + + /*0xFC0DC500---0xFC0DC508*/ + unsigned long ESW_LREC0; + unsigned long ESW_LREC1; + unsigned long ESW_LSR; +}; + +struct AddrTable64bEntry { + unsigned int lo; /* lower 32 bits */ + unsigned int hi; /* upper 32 bits */ +}; + +struct eswAddrTable_t { + struct AddrTable64bEntry eswTable64bEntry[2048]; +}; + +#define MCF_ESW_LOOKUP_MEM_OFFSET 0x4000 +#define ENET_SWI_PHYS_ADDR_OFFSET 0x8000 +#define MCF_ESW_PER (0x08 / sizeof(unsigned long)) +#define MCF_ESW_DBCR (0x14 / sizeof(unsigned long)) +#define MCF_ESW_IMR (0x404 / sizeof(unsigned long)) + +#define MCF_FEC_BASE_ADDR (fep->enet_addr) +#define MCF_FEC_EIR0 (0x04 / sizeof(unsigned long)) +#define MCF_FEC_EIR1 (0x4004 / sizeof(unsigned long)) +#define MCF_FEC_EIMR0 (0x08 / sizeof(unsigned long)) +#define MCF_FEC_EIMR1 (0x4008 / sizeof(unsigned long)) +#define MCF_FEC_MMFR0 (0x40 / sizeof(unsigned long)) +#define MCF_FEC_MMFR1 (0x4040 / sizeof(unsigned long)) +#define MCF_FEC_MSCR0 (0x44 / sizeof(unsigned long)) +#define MCF_FEC_MSCR1 (0x4044 / sizeof(unsigned long)) + +#define MCF_FEC_RCR0 (0x84 / sizeof(unsigned long)) +#define MCF_FEC_RCR1 (0x4084 / sizeof(unsigned long)) +#define MCF_FEC_TCR0 (0xC4 / sizeof(unsigned long)) +#define MCF_FEC_TCR1 (0x40C4 / sizeof(unsigned long)) +#define MCF_FEC_ECR0 (0x24 / sizeof(unsigned long)) +#define MCF_FEC_ECR1 (0x4024 / sizeof(unsigned long)) + +#define MCF_FEC_PALR0 (0xE4 / sizeof(unsigned long)) +#define MCF_FEC_PALR1 (0x40E4 / sizeof(unsigned long)) +#define MCF_FEC_PAUR0 (0xE8 / sizeof(unsigned long)) +#define MCF_FEC_PAUR1 (0x40E8 / sizeof(unsigned long)) + +#define MCF_FEC_ERDSR0 (0x180 / sizeof(unsigned long)) +#define MCF_FEC_ERDSR1 (0x4180 / sizeof(unsigned long)) +#define MCF_FEC_ETDSR0 (0x184 / sizeof(unsigned long)) +#define MCF_FEC_ETDSR1 (0x4184 / sizeof(unsigned long)) + +#define MCF_FEC_IAUR0 (0x118 / sizeof(unsigned long)) +#define MCF_FEC_IAUR1 (0x4118 / sizeof(unsigned long)) +#define MCF_FEC_IALR0 (0x11C / sizeof(unsigned long)) +#define MCF_FEC_IALR1 (0x411C / sizeof(unsigned long)) + +#define MCF_FEC_GAUR0 (0x120 / sizeof(unsigned long)) +#define MCF_FEC_GAUR1 (0x4120 / sizeof(unsigned long)) +#define MCF_FEC_GALR0 (0x124 / sizeof(unsigned long)) +#define MCF_FEC_GALR1 (0x4124 / sizeof(unsigned long)) + +#define MCF_FEC_EMRBR0 (0x188 / sizeof(unsigned long)) +#define MCF_FEC_EMRBR1 (0x4188 / sizeof(unsigned long)) + +#define MCF_FEC_RCR_DRT (0x00000002) +#define MCF_FEC_RCR_PROM (0x00000008) +#define MCF_FEC_RCR_FCE (0x00000020) +#define MCF_FEC_RCR_RMII_MODE (0x00000100) +#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x00003FFF)<<16) +#define MCF_FEC_RCR_CRC_FWD (0x00004000) +#define MCF_FEC_RCR_NO_LGTH_CHECK (0x40000000) +#define MCF_FEC_TCR_FDEN (0x00000004) + +#define MCF_FEC_ECR_RESET (0x00000001) +#define MCF_FEC_ECR_ETHER_EN (0x00000002) +#define MCF_FEC_ECR_MAGIC_ENA (0x00000004) +#define MCF_FEC_ECR_ENA_1588 (0x00000010) + +#define MCF_FEC_ERDSR(x) ((x) << 2) + +/*-------------ioctl command ---------------------------------------*/ +#define ESW_SET_LEARNING_CONF 0x9101 +#define ESW_GET_LEARNING_CONF 0x9201 +#define ESW_SET_BLOCKING_CONF 0x9102 +#define ESW_GET_BLOCKING_CONF 0x9202 +#define ESW_SET_MULTICAST_CONF 0x9103 +#define ESW_GET_MULTICAST_CONF 0x9203 +#define ESW_SET_BROADCAST_CONF 0x9104 +#define ESW_GET_BROADCAST_CONF 0x9204 +#define ESW_SET_PORTENABLE_CONF 0x9105 +#define ESW_GET_PORTENABLE_CONF 0x9205 +#define ESW_SET_IP_SNOOP_CONF 0x9106 +#define ESW_GET_IP_SNOOP_CONF 0x9206 +#define ESW_SET_PORT_SNOOP_CONF 0x9107 +#define ESW_GET_PORT_SNOOP_CONF 0x9207 +#define ESW_SET_PORT_MIRROR_CONF 0x9108 +#define ESW_GET_PORT_MIRROR_CONF 0x9208 +#define ESW_SET_PIRORITY_VLAN 0x9109 +#define ESW_GET_PIRORITY_VLAN 0x9209 +#define ESW_SET_PIRORITY_IP 0x910A +#define ESW_GET_PIRORITY_IP 0x920A +#define ESW_SET_PIRORITY_MAC 0x910B +#define ESW_GET_PIRORITY_MAC 0x920B +#define ESW_SET_PIRORITY_DEFAULT 0x910C +#define ESW_GET_PIRORITY_DEFAULT 0x920C +#define ESW_SET_P0_FORCED_FORWARD 0x910D +#define ESW_GET_P0_FORCED_FORWARD 0x920D +#define ESW_SET_SWITCH_MODE 0x910E +#define ESW_GET_SWITCH_MODE 0x920E +#define ESW_SET_BRIDGE_CONFIG 0x910F +#define ESW_GET_BRIDGE_CONFIG 0x920F +#define ESW_SET_VLAN_OUTPUT_PROCESS 0x9110 +#define ESW_GET_VLAN_OUTPUT_PROCESS 0x9210 +#define ESW_SET_VLAN_INPUT_PROCESS 0x9111 +#define ESW_GET_VLAN_INPUT_PROCESS 0x9211 +#define ESW_SET_VLAN_DOMAIN_VERIFICATION 0x9112 +#define ESW_GET_VLAN_DOMAIN_VERIFICATION 0x9212 +#define ESW_SET_VLAN_RESOLUTION_TABLE 0x9113 +#define ESW_GET_VLAN_RESOLUTION_TABLE 0x9213 + + +#define ESW_GET_STATISTICS_STATUS 0x9221 +#define ESW_GET_PORT0_STATISTICS_STATUS 0x9222 +#define ESW_GET_PORT1_STATISTICS_STATUS 0x9223 +#define ESW_GET_PORT2_STATISTICS_STATUS 0x9224 +#define ESW_SET_OUTPUT_QUEUE_MEMORY 0x9125 +#define ESW_GET_OUTPUT_QUEUE_STATUS 0x9225 +#define ESW_UPDATE_STATIC_MACTABLE 0x9226 +#define ESW_CLEAR_ALL_MACTABLE 0x9227 + +struct eswIoctlPortConfig { + int port; + int enable; +}; + +struct eswIoctlPortEnableConfig { + int port; + int tx_enable; + int rx_enable; +}; + +struct eswIoctlIpsnoopConfig { + int num; + int mode; + unsigned char ip_header_protocol; +}; + +struct eswIoctlP0ForcedForwardConfig { + int port1; + int port2; + int enable; +}; + +struct eswIoctlPortsnoopConfig { + int num; + int mode; + unsigned short compare_port; + int compare_num; +}; + +struct eswIoctlPortMirrorConfig { + int mirror_port; + int port; + int egress_en; + int ingress_en; + int egress_mac_src_en; + int egress_mac_des_en; + int ingress_mac_src_en; + int ingress_mac_des_en; + unsigned char *src_mac; + unsigned char *des_mac; + int mirror_enable; +}; + +struct eswIoctlPriorityVlanConfig { + int port; + int func_enable; + int vlan_pri_table_num; + int vlan_pri_table_value; +}; + +struct eswIoctlPriorityIPConfig { + int port; + int func_enable; + int ipv4_en; + int ip_priority_num; + int ip_priority_value; +}; + +struct eswIoctlPriorityMacConfig { + int port; +}; + +struct eswIoctlPriorityDefaultConfig{ + int port; + unsigned char priority_value; +}; + +struct eswIoctlIrqStatus { + unsigned long isr; + unsigned long imr; + unsigned long rx_buf_pointer; + unsigned long tx_buf_pointer; + unsigned long rx_max_size; + unsigned long rx_buf_active; + unsigned long tx_buf_active; +}; + +struct eswIoctlPortMirrorStatus { + unsigned long ESW_MCR; + unsigned long ESW_EGMAP; + unsigned long ESW_INGMAP; + unsigned long ESW_INGSAL; + unsigned long ESW_INGSAH; + unsigned long ESW_INGDAL; + unsigned long ESW_INGDAH; + unsigned long ESW_ENGSAL; + unsigned long ESW_ENGSAH; + unsigned long ESW_ENGDAL; + unsigned long ESW_ENGDAH; + unsigned long ESW_MCVAL; +}; + +struct eswIoctlVlanOutputConfig { + int port; + int mode; +}; + +struct eswIoctlVlanInputConfig { + int port; + int mode; + unsigned short port_vlanid; + int vlan_verify_en; + int vlan_domain_num; + int vlan_domain_port; +}; + +struct eswIoctlVlanVerificationConfig { + int port; + int vlan_domain_verify_en; + int vlan_discard_unknown_en; +}; + +struct eswIoctlVlanResoultionTable { + unsigned short port_vlanid; + int vlan_domain_num; + int vlan_domain_port; +}; + +struct eswIoctlVlanInputStatus { + unsigned long ESW_VLANV; + unsigned long ESW_PID[3]; + unsigned long ESW_VIMSEL; + unsigned long ESW_VIMEN; + unsigned long ESW_VRES[32]; +}; + +struct eswIoctlUpdateStaticMACtable { + unsigned char *mac_addr; + int port; + int priority; +}; + +struct eswIoctlOutputQueue { + int fun_num; + struct esw_output_queue_status sOutputQueue; +}; + +/*=============================================================*/ +#define LEARNING_AGING_TIMER (10 * HZ) +/* + * Info received from Hardware Learning FIFO, + * holding MAC address and corresponding Hash Value and + * port number where the frame was received (disassembled). + */ +struct eswPortInfo { + /* MAC lower 32 bits (first byte is 7:0). */ + unsigned int maclo; + /* MAC upper 16 bits (47:32). */ + unsigned int machi; + /* the hash value for this MAC address. */ + unsigned int hash; + /* the port number this MAC address is associated with. */ + unsigned int port; +}; + +/* + * Hardware Look up Address Table 64-bit element. + */ +struct eswTable64bitEntry { + unsigned int lo; /* lower 32 bits */ + unsigned int hi; /* upper 32 bits */ +}; + +/* + * Disassembled element stored in Address Table. + */ +struct eswAddrTableDynamicEntry { + /* MAC lower 32 bits (first byte is 7:0). */ + unsigned int maclo; + /* MAC upper 16 bits (47:32). */ + unsigned int machi; + /* timestamp of this entry */ + unsigned int timestamp; + /* the port number this MAC address is associated with */ + unsigned int port; +}; + +struct eswAddrTableStaticEntry { + /* MAC lower 32 bits (first byte is 7:0). */ + unsigned int maclo; + /* MAC upper 16 bits (47:32). */ + unsigned int machi; + /* priority of this entry */ + unsigned int priority; + /* the port bitmask this MAC address is associated with */ + unsigned int portbitmask; +}; +/* + * Define the buffer descriptor structure. + */ +struct cbd_t { +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_MXS) + unsigned short cbd_datlen; /* Data length */ + unsigned short cbd_sc; /* Control and status info */ +#else + unsigned short cbd_sc; /* Control and status info */ + unsigned short cbd_datlen; /* Data length */ +#endif + unsigned long cbd_bufaddr; /* Buffer address */ +#ifdef L2SWITCH_ENHANCED_BUFFER + unsigned long ebd_status; + unsigned short length_proto_type; + unsigned short payload_checksum; + unsigned long bdu; + unsigned long timestamp; + unsigned long reserverd_word1; + unsigned long reserverd_word2; +#endif +}; + +/* Forward declarations of some structures to support different PHYs + */ +struct phy_cmd_t { + uint mii_data; + void (*funct)(uint mii_reg, struct net_device *dev); +}; + +struct phy_info_t { + uint id; + char *name; + + const struct phy_cmd_t *config; + const struct phy_cmd_t *startup; + const struct phy_cmd_t *ack_int; + const struct phy_cmd_t *shutdown; +}; + +/* The switch buffer descriptors track the ring buffers. The rx_bd_base and + * tx_bd_base always point to the base of the buffer descriptors. The + * cur_rx and cur_tx point to the currently available buffer. + * The dirty_tx tracks the current buffer that is being sent by the + * controller. The cur_tx and dirty_tx are equal under both completely + * empty and completely full conditions. The empty/ready indicator in + * the buffer descriptor determines the actual condition. + */ +struct switch_enet_private { + /* Hardware registers of the switch device */ + struct switch_t *hwp; + struct eswAddrTable_t *hwentry; + unsigned long *enet_addr; + + struct net_device *netdev; + struct platform_device *pdev; + struct clk *clk; + /* The saved address of a sent-in-place packet/buffer, for skfree(). */ + unsigned char *tx_bounce[TX_RING_SIZE]; + struct sk_buff *tx_skbuff[TX_RING_SIZE]; + struct sk_buff *rx_skbuff[RX_RING_SIZE]; + ushort skb_cur; + ushort skb_dirty; + + /* CPM dual port RAM relative addresses */ + dma_addr_t bd_dma; + struct cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ + struct cbd_t *tx_bd_base; + struct cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ + struct cbd_t *dirty_tx; /* The ring entries to be free()ed. */ + uint tx_full; + /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ + spinlock_t hw_lock; + + /* hold while accessing the mii_list_t() elements */ + spinlock_t mii_lock; + struct mii_bus *mdio_bus; + struct phy_device *phydev; + phy_interface_t phy_interface; + + uint phy_id; + uint phy_id_done; + uint phy_status; + struct phy_info_t const *phy; + struct work_struct phy_task; + struct switch_t *phy_hwp; + + uint sequence_done; + uint mii_phy_task_queued; + + uint phy_addr; + + int opened; + int old_link; + int duplex; + int speed; + int msg_enable; + + /* --------------Statistics--------------------------- */ + /* when a new element deleted a element with in + * a block due to lack of space */ + int atBlockOverflows; + /* Peak number of valid entries in the address table */ + int atMaxEntries; + /* current number of valid entries in the address table */ + int atCurrEntries; + /* maximum entries within a block found + * (updated within ageing)*/ + int atMaxEntriesPerBlock; + + /* -------------------ageing function------------------ */ + /* maximum age allowed for an entry */ + int ageMax; + /* last LUT entry to block that was + * inspected by the Ageing task*/ + int ageLutIdx; + /* last element within block inspected by the Ageing task */ + int ageBlockElemIdx; + /* complete table has been processed by ageing process */ + int ageCompleted; + /* delay setting */ + int ageDelay; + /* current delay Counter */ + int ageDelayCnt; + + /* ----------------timer related---------------------------- */ + /* current time (for timestamping) */ + int currTime; + /* flag set by timer when currTime changed + * and cleared by serving function*/ + int timeChanged; + + /**/ + /* Timer for Aging */ + struct timer_list timer_aging; + int learning_irqhandle_enable; + /* Phylib and MDIO interface */ + struct mii_bus *mii_bus; + struct phy_device *phy_dev[2]; + int mii_timeout; + uint phy_speed; + int index; + int link[2]; + int full_duplex; + struct completion mdio_done; + + int mac0_irq; + int mac1_irq; +}; + +struct switch_platform_private { + struct platform_device *pdev; + + unsigned long quirks; + int num_slots; /* Slots on controller */ + struct switch_enet_private *fep_host[0]; /* Pointers to hosts */ +}; + +/******************************************************************************/ +#define FEC_IEVENT 0x004 /* Interrupt event reg */ +#define FEC_IMASK 0x008 /* Interrupt mask reg */ +#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ +#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ +#define FEC_ECNTRL 0x024 /* Ethernet control reg */ +#define FEC_MII_DATA 0x040 /* MII manage frame reg */ +#define FEC_MII_SPEED 0x044 /* MII speed control reg */ +#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ +#define FEC_R_CNTRL 0x084 /* Receive control reg */ +#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ +#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ +#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ +#define FEC_OPD 0x0ec /* Opcode + Pause duration */ +#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ +#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ +#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ +#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ +#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ +#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ +#define FEC_R_FSTART 0x150 /* FIFO receive start reg */ +#define FEC_R_DES_START 0x180 /* Receive descriptor ring */ +#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */ +#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ +#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK config register */ +#define FEC_MIIGSK_ENR 0x308 /* MIIGSK enable register */ + +/* Recieve is empty */ +#define BD_SC_EMPTY ((unsigned short)0x8000) +/* Transmit is ready */ +#define BD_SC_READY ((unsigned short)0x8000) +/* Last buffer descriptor */ +#define BD_SC_WRAP ((unsigned short)0x2000) +/* Interrupt on change */ +#define BD_SC_INTRPT ((unsigned short)0x1000) +/* Continous mode */ +#define BD_SC_CM ((unsigned short)0x0200) +/* Rec'd too many idles */ +#define BD_SC_ID ((unsigned short)0x0100) +/* xmt preamble */ +#define BD_SC_P ((unsigned short)0x0100) +/* Break received */ +#define BD_SC_BR ((unsigned short)0x0020) +/* Framing error */ +#define BD_SC_FR ((unsigned short)0x0010) +/* Parity error */ +#define BD_SC_PR ((unsigned short)0x0008) +/* Overrun */ +#define BD_SC_OV ((unsigned short)0x0002) +#define BD_SC_CD ((unsigned short)0x0001) + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((unsigned short)0x8000) +#define BD_ENET_RX_WRAP ((unsigned short)0x2000) +#define BD_ENET_RX_INTR ((unsigned short)0x1000) +#define BD_ENET_RX_LAST ((unsigned short)0x0800) +#define BD_ENET_RX_FIRST ((unsigned short)0x0400) +#define BD_ENET_RX_MISS ((unsigned short)0x0100) +#define BD_ENET_RX_LG ((unsigned short)0x0020) +#define BD_ENET_RX_NO ((unsigned short)0x0010) +#define BD_ENET_RX_SH ((unsigned short)0x0008) +#define BD_ENET_RX_CR ((unsigned short)0x0004) +#define BD_ENET_RX_OV ((unsigned short)0x0002) +#define BD_ENET_RX_CL ((unsigned short)0x0001) +/* All status bits */ +#define BD_ENET_RX_STATS ((unsigned short)0x013f) + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((unsigned short)0x8000) +#define BD_ENET_TX_PAD ((unsigned short)0x4000) +#define BD_ENET_TX_WRAP ((unsigned short)0x2000) +#define BD_ENET_TX_INTR ((unsigned short)0x1000) +#define BD_ENET_TX_LAST ((unsigned short)0x0800) +#define BD_ENET_TX_TC ((unsigned short)0x0400) +#define BD_ENET_TX_DEF ((unsigned short)0x0200) +#define BD_ENET_TX_HB ((unsigned short)0x0100) +#define BD_ENET_TX_LC ((unsigned short)0x0080) +#define BD_ENET_TX_RL ((unsigned short)0x0040) +#define BD_ENET_TX_RCMASK ((unsigned short)0x003c) +#define BD_ENET_TX_UN ((unsigned short)0x0002) +#define BD_ENET_TX_CSL ((unsigned short)0x0001) +/* All status bits */ +#define BD_ENET_TX_STATS ((unsigned short)0x03ff) + +/*Copy from validation code */ +#define RX_BUFFER_SIZE 256 +#define TX_BUFFER_SIZE 256 +#define NUM_RXBDS 20 +#define NUM_TXBDS 20 + +#define TX_BD_R 0x8000 +#define TX_BD_TO1 0x4000 +#define TX_BD_W 0x2000 +#define TX_BD_TO2 0x1000 +#define TX_BD_L 0x0800 +#define TX_BD_TC 0x0400 + +#define TX_BD_INT 0x40000000 +#define TX_BD_TS 0x20000000 +#define TX_BD_PINS 0x10000000 +#define TX_BD_IINS 0x08000000 +#define TX_BD_TXE 0x00008000 +#define TX_BD_UE 0x00002000 +#define TX_BD_EE 0x00001000 +#define TX_BD_FE 0x00000800 +#define TX_BD_LCE 0x00000400 +#define TX_BD_OE 0x00000200 +#define TX_BD_TSE 0x00000100 +#define TX_BD_BDU 0x80000000 + +#define RX_BD_E 0x8000 +#define RX_BD_R01 0x4000 +#define RX_BD_W 0x2000 +#define RX_BD_R02 0x1000 +#define RX_BD_L 0x0800 +#define RX_BD_M 0x0100 +#define RX_BD_BC 0x0080 +#define RX_BD_MC 0x0040 +#define RX_BD_LG 0x0020 +#define RX_BD_NO 0x0010 +#define RX_BD_CR 0x0004 +#define RX_BD_OV 0x0002 +#define RX_BD_TR 0x0001 + +#define RX_BD_ME 0x80000000 +#define RX_BD_PE 0x04000000 +#define RX_BD_CE 0x02000000 +#define RX_BD_UC 0x01000000 +#define RX_BD_INT 0x00800000 +#define RX_BD_ICE 0x00000020 +#define RX_BD_PCR 0x00000010 +#define RX_BD_VLAN 0x00000004 +#define RX_BD_IPV6 0x00000002 +#define RX_BD_FRAG 0x00000001 +#define RX_BD_BDU 0x80000000 +/****************************************************************************/ + +/* Address Table size in bytes(2048 64bit entry ) */ +#define ESW_ATABLE_MEM_SIZE (2048*8) +/* How many 64-bit elements fit in the address table */ +#define ESW_ATABLE_MEM_NUM_ENTRIES (2048) +/* Address Table Maximum number of entries in each Slot */ +#define ATABLE_ENTRY_PER_SLOT 8 +/* log2(ATABLE_ENTRY_PER_SLOT)*/ +#define ATABLE_ENTRY_PER_SLOT_bits 3 +/* entry size in byte */ +#define ATABLE_ENTRY_SIZE 8 +/* slot size in byte */ +#define ATABLE_SLOT_SIZE (ATABLE_ENTRY_PER_SLOT * ATABLE_ENTRY_SIZE) +/* width of timestamp variable (bits) within address table entry */ +#define AT_DENTRY_TIMESTAMP_WIDTH 10 +/* number of bits for port number storage */ +#define AT_DENTRY_PORT_WIDTH 4 +/* number of bits for port bitmask number storage */ +#define AT_SENTRY_PORT_WIDTH 11 +/* address table static entry port bitmask start address bit */ +#define AT_SENTRY_PORTMASK_shift 21 +/* address table static entry priority start address bit */ +#define AT_SENTRY_PRIO_shift 18 +/* address table dynamic entry port start address bit */ +#define AT_DENTRY_PORT_shift 28 +/* address table dynamic entry timestamp start address bit */ +#define AT_DENTRY_TIME_shift 18 +/* address table entry record type start address bit */ +#define AT_ENTRY_TYPE_shift 17 +/* address table entry record type bit: 1 static, 0 dynamic */ +#define AT_ENTRY_TYPE_STATIC 1 +#define AT_ENTRY_TYPE_DYNAMIC 0 +/* address table entry record valid start address bit */ +#define AT_ENTRY_VALID_shift 16 +#define AT_ENTRY_RECORD_VALID 1 + + +/* return block corresponding to the 8 bit hash value calculated */ +#define GET_BLOCK_PTR(hash) (hash << 3) +#define AT_EXTRACT_TIMESTAMP(x) \ + ((x >> AT_DENTRY_TIME_shift) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) +#define AT_EXTRACT_PORT(x) \ + ((x >> AT_DENTRY_PORT_shift) & ((1 << AT_DENTRY_PORT_WIDTH)-1)) +#define TIMEDELTA(newtime, oldtime) \ + ((newtime - oldtime) & \ + ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) +/* increment time value respecting modulo. */ +#define TIMEINCREMENT(time) \ + ((time) = ((time)+1) & ((1 << AT_DENTRY_TIMESTAMP_WIDTH)-1)) +/* ------------------------------------------------------------------------- */ +/* Bit definitions and macros for MCF_ESW_REVISION */ +#define MCF_ESW_REVISION_CORE_REVISION(x) (((x)&0x0000FFFF)<<0) +#define MCF_ESW_REVISION_CUSTOMER_REVISION(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_ESW_PER */ +#define MCF_ESW_PER_TE0 (0x00000001) +#define MCF_ESW_PER_TE1 (0x00000002) +#define MCF_ESW_PER_TE2 (0x00000004) +#define MCF_ESW_PER_RE0 (0x00010000) +#define MCF_ESW_PER_RE1 (0x00020000) +#define MCF_ESW_PER_RE2 (0x00040000) + +/* Bit definitions and macros for MCF_ESW_VLANV */ +#define MCF_ESW_VLANV_VV0 (0x00000001) +#define MCF_ESW_VLANV_VV1 (0x00000002) +#define MCF_ESW_VLANV_VV2 (0x00000004) +#define MCF_ESW_VLANV_DU0 (0x00010000) +#define MCF_ESW_VLANV_DU1 (0x00020000) +#define MCF_ESW_VLANV_DU2 (0x00040000) + +/* Bit definitions and macros for MCF_ESW_DBCR */ +#define MCF_ESW_DBCR_P0 (0x00000001) +#define MCF_ESW_DBCR_P1 (0x00000002) +#define MCF_ESW_DBCR_P2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_DMCR */ +#define MCF_ESW_DMCR_P0 (0x00000001) +#define MCF_ESW_DMCR_P1 (0x00000002) +#define MCF_ESW_DMCR_P2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_BKLR */ +#define MCF_ESW_BKLR_BE0 (0x00000001) +#define MCF_ESW_BKLR_BE1 (0x00000002) +#define MCF_ESW_BKLR_BE2 (0x00000004) +#define MCF_ESW_BKLR_LD0 (0x00010000) +#define MCF_ESW_BKLR_LD1 (0x00020000) +#define MCF_ESW_BKLR_LD2 (0x00040000) + +/* Bit definitions and macros for MCF_ESW_BMPC */ +#define MCF_ESW_BMPC_PORT(x) (((x)&0x0000000F)<<0) +#define MCF_ESW_BMPC_MSG_TX (0x00000020) +#define MCF_ESW_BMPC_EN (0x00000040) +#define MCF_ESW_BMPC_DIS (0x00000080) +#define MCF_ESW_BMPC_PRIORITY(x) (((x)&0x00000007)<<13) +#define MCF_ESW_BMPC_PORTMASK(x) (((x)&0x00000007)<<16) + +/* Bit definitions and macros for MCF_ESW_MODE */ +#define MCF_ESW_MODE_SW_RST (0x00000001) +#define MCF_ESW_MODE_SW_EN (0x00000002) +#define MCF_ESW_MODE_STOP (0x00000080) +#define MCF_ESW_MODE_CRC_TRAN (0x00000100) +#define MCF_ESW_MODE_P0CT (0x00000200) +#define MCF_ESW_MODE_STATRST (0x80000000) + +/* Bit definitions and macros for MCF_ESW_VIMSEL */ +#define MCF_ESW_VIMSEL_IM0(x) (((x)&0x00000003)<<0) +#define MCF_ESW_VIMSEL_IM1(x) (((x)&0x00000003)<<2) +#define MCF_ESW_VIMSEL_IM2(x) (((x)&0x00000003)<<4) + +/* Bit definitions and macros for MCF_ESW_VOMSEL */ +#define MCF_ESW_VOMSEL_OM0(x) (((x)&0x00000003)<<0) +#define MCF_ESW_VOMSEL_OM1(x) (((x)&0x00000003)<<2) +#define MCF_ESW_VOMSEL_OM2(x) (((x)&0x00000003)<<4) + +/* Bit definitions and macros for MCF_ESW_VIMEN */ +#define MCF_ESW_VIMEN_EN0 (0x00000001) +#define MCF_ESW_VIMEN_EN1 (0x00000002) +#define MCF_ESW_VIMEN_EN2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_VID */ +#define MCF_ESW_VID_TAG(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_MCR */ +#define MCF_ESW_MCR_PORT(x) (((x)&0x0000000F)<<0) +#define MCF_ESW_MCR_MEN (0x00000010) +#define MCF_ESW_MCR_INGMAP (0x00000020) +#define MCF_ESW_MCR_EGMAP (0x00000040) +#define MCF_ESW_MCR_INGSA (0x00000080) +#define MCF_ESW_MCR_INGDA (0x00000100) +#define MCF_ESW_MCR_EGSA (0x00000200) +#define MCF_ESW_MCR_EGDA (0x00000400) + +/* Bit definitions and macros for MCF_ESW_EGMAP */ +#define MCF_ESW_EGMAP_EG0 (0x00000001) +#define MCF_ESW_EGMAP_EG1 (0x00000002) +#define MCF_ESW_EGMAP_EG2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_INGMAP */ +#define MCF_ESW_INGMAP_ING0 (0x00000001) +#define MCF_ESW_INGMAP_ING1 (0x00000002) +#define MCF_ESW_INGMAP_ING2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_INGSAL */ +#define MCF_ESW_INGSAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_INGSAH */ +#define MCF_ESW_INGSAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_INGDAL */ +#define MCF_ESW_INGDAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_INGDAH */ +#define MCF_ESW_INGDAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ENGSAL */ +#define MCF_ESW_ENGSAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ENGSAH */ +#define MCF_ESW_ENGSAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ENGDAL */ +#define MCF_ESW_ENGDAL_ADDLOW(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ENGDAH */ +#define MCF_ESW_ENGDAH_ADDHIGH(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_MCVAL */ +#define MCF_ESW_MCVAL_COUNT(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF_ESW_MMSR */ +#define MCF_ESW_MMSR_BUSY (0x00000001) +#define MCF_ESW_MMSR_NOCELL (0x00000002) +#define MCF_ESW_MMSR_MEMFULL (0x00000004) +#define MCF_ESW_MMSR_MFLATCH (0x00000008) +#define MCF_ESW_MMSR_DQ_GRNT (0x00000040) +#define MCF_ESW_MMSR_CELLS_AVAIL(x) (((x)&0x000000FF)<<16) + +/* Bit definitions and macros for MCF_ESW_LMT */ +#define MCF_ESW_LMT_THRESH(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF_ESW_LFC */ +#define MCF_ESW_LFC_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_PCSR */ +#define MCF_ESW_PCSR_PC0 (0x00000001) +#define MCF_ESW_PCSR_PC1 (0x00000002) +#define MCF_ESW_PCSR_PC2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_IOSR */ +#define MCF_ESW_IOSR_OR0 (0x00000001) +#define MCF_ESW_IOSR_OR1 (0x00000002) +#define MCF_ESW_IOSR_OR2 (0x00000004) + +/* Bit definitions and macros for MCF_ESW_QWT */ +#define MCF_ESW_QWT_Q0WT(x) (((x)&0x0000001F)<<0) +#define MCF_ESW_QWT_Q1WT(x) (((x)&0x0000001F)<<8) +#define MCF_ESW_QWT_Q2WT(x) (((x)&0x0000001F)<<16) +#define MCF_ESW_QWT_Q3WT(x) (((x)&0x0000001F)<<24) + +/* Bit definitions and macros for MCF_ESW_P0BCT */ +#define MCF_ESW_P0BCT_THRESH(x) (((x)&0x000000FF)<<0) + +/* Bit definitions and macros for MCF_ESW_P0FFEN */ +#define MCF_ESW_P0FFEN_FEN (0x00000001) +#define MCF_ESW_P0FFEN_FD(x) (((x)&0x00000003)<<2) + +/* Bit definitions and macros for MCF_ESW_PSNP */ +#define MCF_ESW_PSNP_EN (0x00000001) +#define MCF_ESW_PSNP_MODE(x) (((x)&0x00000003)<<1) +#define MCF_ESW_PSNP_CD (0x00000008) +#define MCF_ESW_PSNP_CS (0x00000010) +#define MCF_ESW_PSNP_PORT_COMPARE(x) (((x)&0x0000FFFF)<<16) + +/* Bit definitions and macros for MCF_ESW_IPSNP */ +#define MCF_ESW_IPSNP_EN (0x00000001) +#define MCF_ESW_IPSNP_MODE(x) (((x)&0x00000003)<<1) +#define MCF_ESW_IPSNP_PROTOCOL(x) (((x)&0x000000FF)<<8) + +/* Bit definitions and macros for MCF_ESW_PVRES */ +#define MCF_ESW_PVRES_PRI0(x) (((x)&0x00000007)<<0) +#define MCF_ESW_PVRES_PRI1(x) (((x)&0x00000007)<<3) +#define MCF_ESW_PVRES_PRI2(x) (((x)&0x00000007)<<6) +#define MCF_ESW_PVRES_PRI3(x) (((x)&0x00000007)<<9) +#define MCF_ESW_PVRES_PRI4(x) (((x)&0x00000007)<<12) +#define MCF_ESW_PVRES_PRI5(x) (((x)&0x00000007)<<15) +#define MCF_ESW_PVRES_PRI6(x) (((x)&0x00000007)<<18) +#define MCF_ESW_PVRES_PRI7(x) (((x)&0x00000007)<<21) + +/* Bit definitions and macros for MCF_ESW_IPRES */ +#define MCF_ESW_IPRES_ADDRESS(x) (((x)&0x000000FF)<<0) +#define MCF_ESW_IPRES_IPV4SEL (0x00000100) +#define MCF_ESW_IPRES_PRI0(x) (((x)&0x00000003)<<9) +#define MCF_ESW_IPRES_PRI1(x) (((x)&0x00000003)<<11) +#define MCF_ESW_IPRES_PRI2(x) (((x)&0x00000003)<<13) +#define MCF_ESW_IPRES_READ (0x80000000) + +/* Bit definitions and macros for MCF_ESW_PRES */ +#define MCF_ESW_PRES_VLAN (0x00000001) +#define MCF_ESW_PRES_IP (0x00000002) +#define MCF_ESW_PRES_MAC (0x00000004) +#define MCF_ESW_PRES_DFLT_PRI(x) (((x)&0x00000007)<<4) + +/* Bit definitions and macros for MCF_ESW_PID */ +#define MCF_ESW_PID_VLANID(x) (((x)&0x0000FFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_VRES */ +#define MCF_ESW_VRES_P0 (0x00000001) +#define MCF_ESW_VRES_P1 (0x00000002) +#define MCF_ESW_VRES_P2 (0x00000004) +#define MCF_ESW_VRES_VLANID(x) (((x)&0x00000FFF)<<3) + +/* Bit definitions and macros for MCF_ESW_DISCN */ +#define MCF_ESW_DISCN_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_DISCB */ +#define MCF_ESW_DISCB_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_NDISCN */ +#define MCF_ESW_NDISCN_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_NDISCB */ +#define MCF_ESW_NDISCB_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_POQC */ +#define MCF_ESW_POQC_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_PMVID */ +#define MCF_ESW_PMVID_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_PMVTAG */ +#define MCF_ESW_PMVTAG_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_PBL */ +#define MCF_ESW_PBL_COUNT(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_ISR */ +#define MCF_ESW_ISR_EBERR (0x00000001) +#define MCF_ESW_ISR_RXB (0x00000002) +#define MCF_ESW_ISR_RXF (0x00000004) +#define MCF_ESW_ISR_TXB (0x00000008) +#define MCF_ESW_ISR_TXF (0x00000010) +#define MCF_ESW_ISR_QM (0x00000020) +#define MCF_ESW_ISR_OD0 (0x00000040) +#define MCF_ESW_ISR_OD1 (0x00000080) +#define MCF_ESW_ISR_OD2 (0x00000100) +#define MCF_ESW_ISR_LRN (0x00000200) + +/* Bit definitions and macros for MCF_ESW_IMR */ +#define MCF_ESW_IMR_EBERR (0x00000001) +#define MCF_ESW_IMR_RXB (0x00000002) +#define MCF_ESW_IMR_RXF (0x00000004) +#define MCF_ESW_IMR_TXB (0x00000008) +#define MCF_ESW_IMR_TXF (0x00000010) +#define MCF_ESW_IMR_QM (0x00000020) +#define MCF_ESW_IMR_OD0 (0x00000040) +#define MCF_ESW_IMR_OD1 (0x00000080) +#define MCF_ESW_IMR_OD2 (0x00000100) +#define MCF_ESW_IMR_LRN (0x00000200) + +/* Bit definitions and macros for MCF_ESW_RDSR */ +#define MCF_ESW_RDSR_ADDRESS(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_ESW_TDSR */ +#define MCF_ESW_TDSR_ADDRESS(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_ESW_MRBR */ +#define MCF_ESW_MRBR_SIZE(x) (((x)&0x000003FF)<<4) + +/* Bit definitions and macros for MCF_ESW_RDAR */ +#define MCF_ESW_RDAR_R_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_ESW_TDAR */ +#define MCF_ESW_TDAR_X_DES_ACTIVE (0x01000000) + +/* Bit definitions and macros for MCF_ESW_LREC0 */ +#define MCF_ESW_LREC0_MACADDR0(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_ESW_LREC1 */ +#define MCF_ESW_LREC1_MACADDR1(x) (((x)&0x0000FFFF)<<0) +#define MCF_ESW_LREC1_HASH(x) (((x)&0x000000FF)<<16) +#define MCF_ESW_LREC1_SWPORT(x) (((x)&0x00000003)<<24) + +/* Bit definitions and macros for MCF_ESW_LSR */ +#define MCF_ESW_LSR_DA (0x00000001) + +#endif /* SWITCH_H */ diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c index 309a0eaddd81..f08cff9020bd 100644 --- a/drivers/net/fs_enet/fs_enet-main.c +++ b/drivers/net/fs_enet/fs_enet-main.c @@ -963,12 +963,11 @@ static const struct ethtool_ops fs_ethtool_ops = { static int fs_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { struct fs_enet_private *fep = netdev_priv(dev); - struct mii_ioctl_data *mii = (struct mii_ioctl_data *)&rq->ifr_data; if (!netif_running(dev)) return -EINVAL; - return phy_mii_ioctl(fep->phydev, mii, cmd); + return phy_mii_ioctl(fep->phydev, rq, cmd); } extern int fs_mii_connect(struct net_device *dev); diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 28b53d1cd4f1..b8e9c0162e79 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -846,7 +846,7 @@ static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (!priv->phydev) return -ENODEV; - return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); + return phy_mii_ioctl(priv->phydev, rq, cmd); } static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) diff --git a/drivers/net/imx_ptp.c b/drivers/net/imx_ptp.c new file mode 100644 index 000000000000..8580b1c14a66 --- /dev/null +++ b/drivers/net/imx_ptp.c @@ -0,0 +1,1748 @@ +/* + * drivers/net/imx_ptp.c + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All rights reserved. + * + * Description: IEEE 1588 driver supporting imx5 Fast Ethernet Controller. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fec.h" +#include "fec_1588.h" +#include "imx_ptp.h" + +#ifdef PTP_DEBUG +#define VDBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \ + __func__, ## args) +#else +#define VDBG(fmt, args...) do {} while (0) +#endif + +static DECLARE_WAIT_QUEUE_HEAD(ptp_rx_ts_wait); +static DECLARE_WAIT_QUEUE_HEAD(ptp_tx_ts_wait); +#define PTP_GET_RX_TIMEOUT (HZ/10) +#define PTP_GET_TX_TIMEOUT (HZ/100) + +static struct fec_ptp_private *ptp_private; +static void ptp_rtc_get_current_time(struct ptp *p_ptp, + struct ptp_time *p_time); +static struct ptp *ptp_dev; + +/* The ring resource create and manage */ +static int fec_ptp_init_circ(struct circ_buf *ptp_buf, int size) +{ + ptp_buf->buf = vmalloc(size * sizeof(struct fec_ptp_data_t)); + + if (!ptp_buf->buf) + return 1; + ptp_buf->head = 0; + ptp_buf->tail = 0; + + return 0; +} + +static inline int fec_ptp_calc_index(int size, int curr_index, int offset) +{ + return (curr_index + offset) % size; +} + +static int fec_ptp_is_empty(struct circ_buf *buf) +{ + return (buf->head == buf->tail); +} + +static int fec_ptp_nelems(struct circ_buf *buf, int size) +{ + const int front = buf->head; + const int end = buf->tail; + int n_items; + + if (end > front) + n_items = end - front; + else if (end < front) + n_items = size - (front - end); + else + n_items = 0; + + return n_items; +} + +static int fec_ptp_is_full(struct circ_buf *buf, int size) +{ + if (fec_ptp_nelems(buf, size) == (size - 1)) + return 1; + else + return 0; +} + +static int fec_ptp_insert(struct circ_buf *ptp_buf, + struct fec_ptp_data_t *data, + struct fec_ptp_private *priv, + int size) +{ + struct fec_ptp_data_t *tmp; + + if (fec_ptp_is_full(ptp_buf, size)) + return 1; + + spin_lock(&priv->ptp_lock); + tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + ptp_buf->tail; + + tmp->key = data->key; + memcpy(tmp->spid, data->spid, 10); + tmp->ts_time.sec = data->ts_time.sec; + tmp->ts_time.nsec = data->ts_time.nsec; + + ptp_buf->tail = fec_ptp_calc_index(size, ptp_buf->tail, 1); + spin_unlock(&priv->ptp_lock); + + return 0; +} + +static int fec_ptp_find_and_remove(struct circ_buf *ptp_buf, + struct fec_ptp_data_t *data, + struct fec_ptp_private *priv, + int size) +{ + int i; + int end = ptp_buf->tail; + unsigned long flags; + struct fec_ptp_data_t *tmp; + + if (fec_ptp_is_empty(ptp_buf)) + return 1; + + i = ptp_buf->head; + tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + i; + while (i != end) { + tmp = (struct fec_ptp_data_t *)(ptp_buf->buf) + i; + if (tmp->key == data->key && + !memcmp(tmp->spid, data->spid, 10)) + break; + i = fec_ptp_calc_index(size, i, 1); + } + + spin_lock_irqsave(&priv->ptp_lock, flags); + if (i == end) { + ptp_buf->head = end; + spin_unlock_irqrestore(&priv->ptp_lock, flags); + return 1; + } + + data->ts_time.sec = tmp->ts_time.sec; + data->ts_time.nsec = tmp->ts_time.nsec; + + ptp_buf->head = fec_ptp_calc_index(size, i, 1); + spin_unlock_irqrestore(&priv->ptp_lock, flags); + + return 0; +} + +/* ptp and rtc param configuration */ +static void rtc_default_param(struct ptp_rtc *rtc) +{ + struct ptp_rtc_driver_param *drv_param = rtc->driver_param; + int i; + + rtc->bypass_compensation = DEFAULT_BYPASS_COMPENSATION; + rtc->output_clock_divisor = DEFAULT_OUTPUT_CLOCK_DIVISOR; + + drv_param->src_clock = DEFAULT_SRC_CLOCK; + drv_param->src_clock_freq_hz = clk_get_rate(rtc->clk); + + drv_param->invert_input_clk_phase = DEFAULT_INVERT_INPUT_CLK_PHASE; + drv_param->invert_output_clk_phase = DEFAULT_INVERT_OUTPUT_CLK_PHASE; + drv_param->pulse_start_mode = DEFAULT_PULSE_START_MODE; + drv_param->events_mask = DEFAULT_EVENTS_RTC_MASK; + + for (i = 0; i < PTP_RTC_NUM_OF_ALARMS; i++) + drv_param->alarm_polarity[i] = DEFAULT_ALARM_POLARITY ; + + for (i = 0; i < PTP_RTC_NUM_OF_TRIGGERS; i++) + drv_param->trigger_polarity[i] = DEFAULT_TRIGGER_POLARITY; +} + +static int ptp_rtc_config(struct ptp_rtc *rtc) +{ + /*allocate memory for RTC driver parameter*/ + rtc->driver_param = kzalloc(sizeof(struct ptp_rtc_driver_param), + GFP_KERNEL); + if (!rtc->driver_param) { + printk(KERN_ERR "allocate memory failed\n"); + return -ENOMEM; + } + + /* expected RTC input clk frequency */ + rtc->driver_param->rtc_freq_hz = PTP_RTC_FREQ * MHZ; + + /*set default RTC configuration parameters*/ + rtc_default_param(rtc); + + return 0; +} + +static void ptp_param_config(struct ptp *p_ptp) +{ + struct ptp_driver_param *drv_param; + + p_ptp->driver_param = kzalloc(sizeof(struct ptp_driver_param), + GFP_KERNEL); + if (!p_ptp->driver_param) { + printk(KERN_ERR "allocate memory failed for " + "PTP driver parameters\n"); + return; + } + + drv_param = p_ptp->driver_param; + /*set the default configuration parameters*/ + drv_param->eth_type_value = ETH_TYPE_VALUE; + drv_param->vlan_type_value = VLAN_TYPE_VALUE; + drv_param->udp_general_port = UDP_GENERAL_PORT; + drv_param->udp_event_port = UDP_EVENT_PORT; + drv_param->ip_type_value = IP_TYPE_VALUE; + drv_param->eth_type_offset = ETH_TYPE_OFFSET; + drv_param->ip_type_offset = IP_TYPE_OFFSET; + drv_param->udp_dest_port_offset = UDP_DEST_PORT_OFFSET; + drv_param->ptp_type_offset = PTP_TYPE_OFFSET; + + drv_param->ptp_msg_codes[e_PTP_MSG_SYNC] = DEFAULT_MSG_SYNC; + drv_param->ptp_msg_codes[e_PTP_MSG_DELAY_REQ] = DEFAULT_MSG_DELAY_REQ; + drv_param->ptp_msg_codes[e_PTP_MSG_FOLLOW_UP] = DEFAULT_MSG_FOLLOW_UP; + drv_param->ptp_msg_codes[e_PTP_MSG_DELAY_RESP] = DEFAULT_MSG_DELAY_RESP; + drv_param->ptp_msg_codes[e_PTP_MSG_MANAGEMENT] = DEFAULT_MSG_MANAGEMENT; +} + +/* 64 bits operation */ +static u32 div64_oper(u64 dividend, u32 divisor, u32 *quotient) +{ + u32 time_h, time_l; + u32 result; + u64 tmp_dividend; + int i; + + time_h = (u32)(dividend >> 32); + time_l = (u32)dividend; + time_h = time_h % divisor; + for (i = 1; i <= 32; i++) { + tmp_dividend = (((u64)time_h << 32) | (u64)time_l); + tmp_dividend = (tmp_dividend << 1); + time_h = (u32)(tmp_dividend >> 32); + time_l = (u32)tmp_dividend; + result = time_h / divisor; + time_h = time_h % divisor; + *quotient += (result << (32 - i)); + } + + return time_h; +} + +/*64 bites add and return the result*/ +static u64 add64_oper(u64 addend, u64 augend) +{ + u64 result = 0; + u32 addendh, addendl, augendl, augendh; + + addendh = (u32)(addend >> 32); + addendl = (u32)addend; + + augendh = (u32)(augend>>32); + augendl = (u32)augend; + + __asm__( + "adds %0,%2,%3\n" + "adc %1,%4,%5" + : "=r" (addendl), "=r" (addendh) + : "r" (addendl), "r" (augendl), "r" (addendh), "r" (augendh) + ); + + udelay(1); + result = (((u64)addendh << 32) | (u64)addendl); + + return result; +} + +/*64 bits multiplication and return the result*/ +static u64 multi64_oper(u32 multiplier, u32 multiplicand) +{ + u64 result = 0; + u64 tmp_ret = 0; + u32 tmp_multi = multiplicand; + int i; + + for (i = 0; i < 32; i++) { + if (tmp_multi & 0x1) { + tmp_ret = ((u64)multiplier << i); + result = add64_oper(result, tmp_ret); + } + tmp_multi = (tmp_multi >> 1); + } + + VDBG("multi 64 low result is 0x%x\n", result); + VDBG("multi 64 high result is 0x%x\n", (u32)(result>>32)); + + return result; +} + +/*convert the 64 bites time stamp to second and nanosecond*/ +static void convert_rtc_time(u64 *rtc_time, struct ptp_time *p_time) +{ + u32 time_h; + u32 time_sec = 0; + + time_h = div64_oper(*rtc_time, NANOSEC_IN_SEC, &time_sec); + + p_time->sec = time_sec; + p_time->nsec = time_h; +} + +/* convert rtc time to 64 bites timestamp */ +static u64 convert_unsigned_time(struct ptp_time *ptime) +{ + return add64_oper(multi64_oper(ptime->sec, NANOSEC_IN_SEC), + (u64)ptime->nsec); +} + +/*RTC interrupt handler*/ +static irqreturn_t ptp_rtc_interrupt(int irq, void *_ptp) +{ + struct ptp *p_ptp = (struct ptp *)_ptp; + struct ptp_rtc *rtc = p_ptp->rtc; + struct ptp_time time; + register u32 events; + + /*get valid events*/ + events = readl(rtc->mem_map + PTP_TMR_TEVENT); + + /*clear event bits*/ + writel(events, rtc->mem_map + PTP_TMR_TEVENT); + + /*get the current time as quickly as possible*/ + ptp_rtc_get_current_time(p_ptp, &time); + + if (events & RTC_TEVENT_ALARM_1) { + p_ptp->alarm_counters[0]++; + VDBG("PTP Alarm 1 event, time = %2d:%09d[sec:nsec]\n", + time.sec, time.nsec); + } + if (events & RTC_TEVENT_ALARM_2) { + p_ptp->alarm_counters[1]++; + VDBG("PTP Alarm 2 event, time = %2d:%09d[sec:nsec]\n", + time.sec, time.nsec); + } + if (events & RTC_TEVENT_PERIODIC_PULSE_1) { + p_ptp->pulse_counters[0]++; + VDBG("PTP Pulse 1 event, time = %2d:%09d[sec:nsec]\n", + time.sec, time.nsec); + } + if (events & RTC_TEVENT_PERIODIC_PULSE_2) { + p_ptp->pulse_counters[1]++; + VDBG("PTP Pulse 2 event, time = %2d:%09d[sec:nsec]\n", + time.sec, time.nsec); + } + if (events & RTC_TEVENT_PERIODIC_PULSE_3) { + p_ptp->pulse_counters[2]++; + VDBG("PTP Pulse 3 event, time = %2d:%09d[sec:nsec]\n", + time.sec, time.nsec); + } + + return IRQ_HANDLED; +} + +static int ptp_rtc_init(struct ptp *p_ptp) +{ + struct ptp_rtc *rtc = p_ptp->rtc; + struct ptp_rtc_driver_param *rtc_drv_param = rtc->driver_param; + void __iomem *rtc_mem = rtc->mem_map; + u32 freq_compensation = 0; + u32 tmr_ctrl = 0; + int ret = 0; + int i; + + rtc = p_ptp->rtc; + rtc_drv_param = rtc->driver_param; + rtc_mem = rtc->mem_map; + + if (!rtc->bypass_compensation) + rtc->clock_period_nansec = NANOSEC_PER_ONE_HZ_TICK / + rtc_drv_param->rtc_freq_hz; + else { + /*In bypass mode,the RTC clock equals the source clock*/ + rtc->clock_period_nansec = NANOSEC_PER_ONE_HZ_TICK / + rtc_drv_param->src_clock_freq_hz; + tmr_ctrl |= RTC_TMR_CTRL_BYP; + } + + tmr_ctrl |= ((rtc->clock_period_nansec << + RTC_TMR_CTRL_TCLK_PERIOD_SHIFT) & + RTC_TMR_CTRL_TCLK_PERIOD_MSK); + + if (rtc_drv_param->invert_input_clk_phase) + tmr_ctrl |= RTC_TMR_CTRL_CIPH; + if (rtc_drv_param->invert_output_clk_phase) + tmr_ctrl |= RTC_TMR_CTRL_COPH; + if (rtc_drv_param->pulse_start_mode == e_PTP_RTC_PULSE_START_ON_ALARM) { + tmr_ctrl |= RTC_TMR_CTRL_FS; + rtc->start_pulse_on_alarm = TRUE; + } + + for (i = 0; i < PTP_RTC_NUM_OF_ALARMS; i++) { + if (rtc_drv_param->alarm_polarity[i] == + e_PTP_RTC_ALARM_POLARITY_ACTIVE_LOW) + tmr_ctrl |= (RTC_TMR_CTRL_ALMP1 >> i); + + } + + /*clear TMR_ALARM registers*/ + writel(0xFFFFFFFF, rtc_mem + PTP_TMR_ALARM1_L); + writel(0xFFFFFFFF, rtc_mem + PTP_TMR_ALARM1_H); + writel(0xFFFFFFFF, rtc_mem + PTP_TMR_ALARM2_L); + writel(0xFFFFFFFF, rtc_mem + PTP_TMR_ALARM2_H); + + for (i = 0; i < PTP_RTC_NUM_OF_TRIGGERS; i++) { + if (rtc_drv_param->trigger_polarity[i] == + e_PTP_RTC_TRIGGER_ON_FALLING_EDGE) + tmr_ctrl |= (RTC_TMR_CTRL_ETEP1 << i); + } + + /*clear TMR_FIPER registers*/ + writel(0xFFFFFFFF, rtc_mem + PTP_TMR_FIPER1); + writel(0xFFFFFFFF, rtc_mem + PTP_TMR_FIPER2); + writel(0xFFFFFFFF, rtc_mem + PTP_TMR_FIPER3); + + /*set the source clock*/ + /*use a clock from the QE bank of clocks*/ + tmr_ctrl |= RTC_TMR_CTRL_CKSEL_EXT_CLK; + + /*write register and perform software reset*/ + writel((tmr_ctrl | RTC_TMR_CTRL_TMSR), rtc_mem + PTP_TMR_CTRL); + writel(tmr_ctrl, rtc_mem + PTP_TMR_CTRL); + + /*clear TMR_TEVEMT*/ + writel(RTC_EVENT_ALL, rtc_mem + PTP_TMR_TEVENT); + + /*initialize TMR_TEMASK*/ + writel(rtc_drv_param->events_mask, rtc_mem + PTP_TMR_TEMASK); + + /*initialize TMR_ADD with the initial frequency compensation value: + freq_compensation = (2^32 / frequency ratio)*/ + div64_oper(((u64)rtc_drv_param->rtc_freq_hz << 32), + rtc_drv_param->src_clock_freq_hz, &freq_compensation); + p_ptp->orig_freq_comp = freq_compensation; + writel(freq_compensation, rtc_mem + PTP_TMR_ADD); + + /*initialize TMR_PRSC*/ + writel(rtc->output_clock_divisor, rtc_mem + PTP_TMR_PRSC); + + /*initialize TMR_OFF*/ + writel(0, rtc_mem + PTP_TMR_OFF_L); + writel(0, rtc_mem + PTP_TMR_OFF_H); + + return ret; +} + +static void init_ptp_parser(struct ptp *p_ptp) +{ + void __iomem *mem_map = p_ptp->mem_map; + struct ptp_driver_param *drv_param = p_ptp->driver_param; + u32 reg32; + + /*initialzie PTP TSPDR1*/ + reg32 = ((drv_param->eth_type_value << PTP_TSPDR1_ETT_SHIFT) & + PTP_TSPDR1_ETT_MASK); + reg32 |= ((drv_param->ip_type_value << PTP_TSPDR1_IPT_SHIFT) & + PTP_TSPDR1_IPT_MASK); + writel(reg32, mem_map + PTP_TSPDR1); + + /*initialize PTP TSPDR2*/ + reg32 = ((drv_param->udp_general_port << PTP_TSPDR2_DPNGE_SHIFT) & + PTP_TSPDR2_DPNGE_MASK); + reg32 |= (drv_param->udp_event_port & PTP_TSPDR2_DPNEV_MASK); + writel(reg32, mem_map + PTP_TSPDR2); + + /*initialize PTP TSPDR3*/ + reg32 = ((drv_param->ptp_msg_codes[e_PTP_MSG_SYNC] << + PTP_TSPDR3_SYCTL_SHIFT) & PTP_TSPDR3_SYCTL_MASK); + reg32 |= ((drv_param->ptp_msg_codes[e_PTP_MSG_DELAY_REQ] << + PTP_TSPDR3_DRCTL_SHIFT) & PTP_TSPDR3_DRCTL_MASK); + reg32 |= ((drv_param->ptp_msg_codes[e_PTP_MSG_DELAY_RESP] << + PTP_TSPDR3_DRPCTL_SHIFT) & PTP_TSPDR3_DRPCTL_MASK); + reg32 |= (drv_param->ptp_msg_codes[e_PTP_MSG_FOLLOW_UP] & + PTP_TSPDR3_FUCTL_MASK); + writel(reg32, mem_map + PTP_TSPDR3); + + /*initialzie PTP TSPDR4*/ + reg32 = ((drv_param->ptp_msg_codes[e_PTP_MSG_MANAGEMENT] << + PTP_TSPDR4_MACTL_SHIFT) & PTP_TSPDR4_MACTL_MASK); + reg32 |= (drv_param->vlan_type_value & PTP_TSPDR4_VLAN_MASK); + writel(reg32, mem_map + PTP_TSPDR4); + + /*initialize PTP TSPOV*/ + reg32 = ((drv_param->eth_type_offset << PTP_TSPOV_ETTOF_SHIFT) & + PTP_TSPOV_ETTOF_MASK); + reg32 |= ((drv_param->ip_type_offset << PTP_TSPOV_IPTOF_SHIFT) & + PTP_TSPOV_IPTOF_MASK); + reg32 |= ((drv_param->udp_dest_port_offset << PTP_TSPOV_UDOF_SHIFT) & + PTP_TSPOV_UDOF_MASK); + reg32 |= (drv_param->ptp_type_offset & PTP_TSPOV_PTOF_MASK); + writel(reg32, mem_map + PTP_TSPOV); +} + +/* compatible with MXS 1588 */ +#ifdef CONFIG_IN_BAND +void fec_ptp_store_txstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp) +{ + int msg_type, seq_id, control; + struct fec_ptp_data_t tmp_tx_time, tmp; + struct fec_ptp_private *fpp = priv; + struct ptp *p_ptp = ptp_dev; + int flag; + unsigned char *sp_id; + unsigned short portnum; + u64 timestamp; + + /* Check for PTP Event */ + if ((bdp->cbd_sc & BD_ENET_TX_PTP) == 0) + return; + + /* Get ts from tx ts queue */ + memset(&tmp, 0, sizeof(struct fec_ptp_data_t)); + tmp.key = SEQ_ID_OUT_OF_BAND; + flag = fec_ptp_find_and_remove(&(priv->txstamp), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + if (!flag) { + tmp_tx_time.ts_time.sec = tmp.ts_time.sec; + tmp_tx_time.ts_time.nsec = tmp.ts_time.nsec; + } else { + /*read timestamp from register*/ + timestamp = ((u64)readl(p_ptp->mem_map + PTP_TMR_TXTS_H) + << 32) | + (readl(p_ptp->mem_map + PTP_TMR_TXTS_L)); + convert_rtc_time(×tamp, &(tmp_tx_time.ts_time)); + } + + seq_id = *((u16 *)(skb->data + FEC_PTP_SEQ_ID_OFFS)); + control = *((u8 *)(skb->data + FEC_PTP_CTRL_OFFS)); + sp_id = skb->data + FEC_PTP_SPORT_ID_OFFS; + portnum = ntohs(*((unsigned short *)(sp_id + 8))); + + tmp_tx_time.key = ntohs(seq_id); + memcpy(tmp_tx_time.spid, sp_id, 8); + memcpy(tmp_tx_time.spid + 8, (unsigned char *)&portnum, 2); + + switch (control) { + + case PTP_MSG_SYNC: + fec_ptp_insert(&(priv->tx_time_sync), &tmp_tx_time, priv, + DEFAULT_PTP_TX_BUF_SZ); + break; + + case PTP_MSG_DEL_REQ: + fec_ptp_insert(&(priv->tx_time_del_req), &tmp_tx_time, priv, + DEFAULT_PTP_TX_BUF_SZ); + break; + + /* clear transportSpecific field*/ + case PTP_MSG_ALL_OTHER: + msg_type = (*((u8 *)(skb->data + + FEC_PTP_MSG_TYPE_OFFS))) & 0x0F; + switch (msg_type) { + case PTP_MSG_P_DEL_REQ: + fec_ptp_insert(&(priv->tx_time_pdel_req), &tmp_tx_time, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + fec_ptp_insert(&(priv->tx_time_pdel_resp), &tmp_tx_time, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + default: + break; + } + break; + default: + break; + } + + wake_up_interruptible(&ptp_tx_ts_wait); +} +#else +void fec_ptp_store_txstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp) +{ +} +#endif + +static void ptp_store_txstamp(struct fec_ptp_private *priv, + struct ptp *p_ptp, + struct ptp_time *pts, + u32 events) +{ + struct fec_ptp_data_t tmp_tx_time; + u16 seq_id; + + seq_id = SEQ_ID_OUT_OF_BAND; + + memset(&tmp_tx_time, 0, sizeof(struct fec_ptp_data_t)); + tmp_tx_time.key = ntohs(seq_id); + tmp_tx_time.ts_time.sec = pts->sec; + tmp_tx_time.ts_time.nsec = pts->nsec; + fec_ptp_insert(&(priv->txstamp), &tmp_tx_time, + priv, DEFAULT_PTP_TX_BUF_SZ); +} + +/* out-of-band rx ts store */ +static void ptp_store_rxstamp(struct fec_ptp_private *priv, + struct ptp *p_ptp, + struct ptp_time *pts, + u32 events) +{ + int control = PTP_MSG_ALL_OTHER; + u16 seq_id; + struct fec_ptp_data_t tmp_rx_time; + + /* out-of-band mode can't get seq_id */ + seq_id = SEQ_ID_OUT_OF_BAND; + + memset(&tmp_rx_time, 0, sizeof(struct fec_ptp_data_t)); + tmp_rx_time.key = ntohs(seq_id); + tmp_rx_time.ts_time.sec = pts->sec; + tmp_rx_time.ts_time.nsec = pts->nsec; + if (events & PTP_TS_RX_SYNC1) + control = PTP_MSG_SYNC; + else if (events & PTP_TS_RX_DELAY_REQ1) + control = PTP_MSG_DEL_REQ; + else if (events & PTP_TS_PDRQRE1) + control = PTP_MSG_P_DEL_REQ; + else if (events & PTP_TS_PDRSRE1) + control = PTP_MSG_DEL_RESP; + + switch (control) { + case PTP_MSG_SYNC: + fec_ptp_insert(&(priv->rx_time_sync), &tmp_rx_time, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + + case PTP_MSG_DEL_REQ: + fec_ptp_insert(&(priv->rx_time_del_req), &tmp_rx_time, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + + case PTP_MSG_P_DEL_REQ: + fec_ptp_insert(&(priv->rx_time_pdel_req), &tmp_rx_time, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + + case PTP_MSG_P_DEL_RESP: + fec_ptp_insert(&(priv->rx_time_pdel_resp), &tmp_rx_time, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + + default: + break; + } + + wake_up_interruptible(&ptp_rx_ts_wait); + +} + +/* in-band rx ts store */ +#ifdef CONFIG_IN_BAND +void fec_ptp_store_rxstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp) +{ + int msg_type, seq_id, control; + struct fec_ptp_data_t tmp_rx_time; + struct fec_ptp_private *fpp = priv; + u64 timestamp; + unsigned char *sp_id; + unsigned short portnum; + + /* Check for PTP Event */ + if ((bdp->cbd_sc & BD_ENET_RX_PTP) == 0) { + skb_pull(skb, 8); + return; + } + + /* Get ts from skb data */ + timestamp = *((u64 *)(skb->data)); + convert_rtc_time(×tamp, &(tmp_rx_time.ts_time)); + skb_pull(skb, 8); + + seq_id = *((u16 *)(skb->data + FEC_PTP_SEQ_ID_OFFS)); + control = *((u8 *)(skb->data + FEC_PTP_CTRL_OFFS)); + sp_id = skb->data + FEC_PTP_SPORT_ID_OFFS; + portnum = ntohs(*((unsigned short *)(sp_id + 8))); + + tmp_rx_time.key = ntohs(seq_id); + memcpy(tmp_rx_time.spid, sp_id, 8); + memcpy(tmp_rx_time.spid + 8, (unsigned char *)&portnum, 2); + + switch (control) { + + case PTP_MSG_SYNC: + fec_ptp_insert(&(priv->rx_time_sync), &tmp_rx_time, priv, + DEFAULT_PTP_RX_BUF_SZ); + break; + + case PTP_MSG_DEL_REQ: + fec_ptp_insert(&(priv->rx_time_del_req), &tmp_rx_time, priv, + DEFAULT_PTP_RX_BUF_SZ); + break; + + /* clear transportSpecific field*/ + case PTP_MSG_ALL_OTHER: + msg_type = (*((u8 *)(skb->data + + FEC_PTP_MSG_TYPE_OFFS))) & 0x0F; + switch (msg_type) { + case PTP_MSG_P_DEL_REQ: + fec_ptp_insert(&(priv->rx_time_pdel_req), &tmp_rx_time, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + fec_ptp_insert(&(priv->rx_time_pdel_resp), &tmp_rx_time, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + default: + break; + } + break; + default: + break; + } + + wake_up_interruptible(&ptp_rx_ts_wait); +} +#else +void fec_ptp_store_rxstamp(struct fec_ptp_private *priv, + struct sk_buff *skb, + struct bufdesc *bdp) +{ +} +#endif + +/*PTP interrupt handler*/ +static irqreturn_t ptp_interrupt(int irq, void *dev_id) +{ + struct ptp *p_ptp = (struct ptp *)dev_id; + void __iomem *mem_map = p_ptp->mem_map; + struct ptp_time ps; + u64 timestamp; + u32 events, orig_events; + + /*get valid events*/ + events = readl(mem_map + PTP_TMR_PEVENT); + while (events) { + if (events & PTP_TS_TX_FRAME1) { + /*read timestamp from register*/ + timestamp = ((u64)readl(mem_map + PTP_TMR_TXTS_H) + << 32) | + (readl(mem_map + PTP_TMR_TXTS_L)); + + /*clear event ASAP,hoping to prevent overrun*/ + writel((u32)PTP_TS_TX_FRAME1, + mem_map + PTP_TMR_PEVENT); + /*check for overrun(which incalidates last timestamp)*/ + events = readl(mem_map + PTP_TMR_PEVENT); + + if (events & PTP_TS_TX_OVR1) { + /*lost synchronization with TX timestamps*/ + /*clear overrun event*/ + writel(PTP_TS_TX_OVR1, + mem_map + PTP_TMR_PEVENT); + + p_ptp->tx_time_stamps_overrun++; + } else { + /*insert the Tx timestamps into the queue*/ + convert_rtc_time(×tamp, &ps); + ptp_store_txstamp(ptp_private, p_ptp, + &ps, orig_events); + + /*this event is never really masked, + *but it should be reported only + *if includeed in usre events mask*/ + if (p_ptp->events_mask & PTP_TS_TX_FRAME1) + p_ptp->tx_time_stamps++; + VDBG("tx interrupt\n"); + } + } + + /*typically only one of these events is relevant, + *depending on whether the device is PTP master or slave*/ + if (events & PTP_TS_RX_ALL) { + /*out-of-band mode:read timestamp + *from registers*/ + timestamp = ((u64)readl(mem_map + PTP_TMR_RXTS_H) + << 32) | + (readl(mem_map + PTP_TMR_RXTS_L)); + + /*clear event ASAP,hoping to prevent overrun*/ + orig_events = events; + writel((u32)(PTP_TS_RX_ALL), + mem_map + PTP_TMR_PEVENT); + + /*check for overrun (which invalidates + *last tiemstamp)*/ + events = readl(mem_map + PTP_TMR_PEVENT); + + if (events & PTP_TS_RX_OVR1) { + /*lost synchronization with Rx timestamp*/ + /*clear overrun event. clear the + *timestamp event as well, because + *it may have arrived after it was + *cleared above,but still it is not + *synchronized with received frames*/ + writel((u32)(PTP_TS_RX_ALL | + PTP_TS_RX_OVR1), + mem_map + PTP_TMR_RXTS_H); + p_ptp->rx_time_stamps_overrun++; + } else { + /*insert Rx timestamp into the queue*/ + convert_rtc_time(×tamp, &ps); + ptp_store_rxstamp(ptp_private, p_ptp, + &ps, orig_events); + + /*the Rx TS event is never masked in + *out-of-ban mode,but it should be + *reported only if included in user's + *event's mask*/ + if (p_ptp->events_mask & + (PTP_TS_RX_SYNC1 | + PTP_TS_RX_DELAY_REQ1)) + p_ptp->rx_time_stamps++; + } + } + + writel(~PTP_TMR_PEVENT_VALID, mem_map + PTP_TMR_PEVENT); + events = readl(mem_map + PTP_TMR_PEVENT); + } + + return IRQ_HANDLED; +} + +static void init_ptp_tsu(struct ptp *p_ptp) +{ + struct ptp_driver_param *drv_param = p_ptp->driver_param; + void __iomem *mem_map; + u32 tsmr, pemask, events_mask; + + mem_map = p_ptp->mem_map; + + /*Tx timestamp events are required in all modes*/ + events_mask = PTP_TS_TX_FRAME1 | PTP_TS_TX_OVR1; + + /*read current values of TSU registers*/ + tsmr = readl(mem_map + PTP_TSMR); + pemask = readl(mem_map + PTP_TMR_PEMASK); + + if (drv_param->delivery_mode == e_PTP_TSU_DELIVERY_IN_BAND) { + tsmr |= PTP_TSMR_OPMODE1_IN_BAND; + events_mask &= ~(PTP_TS_TX_OVR1); + } else + /*rx timestamp events are required for out of band mode*/ + events_mask |= (PTP_TS_RX_SYNC1 | PTP_TS_RX_DELAY_REQ1 | + PTP_TS_RX_OVR1); + + pemask |= events_mask; + + /*update TSU register*/ + writel(tsmr, mem_map + PTP_TSMR); + writel(pemask, mem_map + PTP_TMR_PEMASK); +} + +/* ptp module init */ +static void ptp_tsu_init(struct ptp *p_ptp) +{ + void __iomem *mem_map = p_ptp->mem_map; + + /*initialization of registered PTP modules*/ + init_ptp_parser(p_ptp); + + /*reset timestamp*/ + writel(0, mem_map + PTP_TSMR); + writel(0, mem_map + PTP_TMR_PEMASK); + writel(PTP_TMR_PEVENT_ALL, mem_map + PTP_TMR_PEVENT); + +} + +/* TSU configure function */ +static u32 ptp_tsu_enable(struct ptp *p_ptp) +{ + void __iomem *mem_map; + u32 tsmr; + + /*enable the TSU*/ + mem_map = p_ptp->mem_map; + + /*set the TSU enable bit*/ + tsmr = readl(mem_map + PTP_TSMR); + tsmr |= PTP_TSMR_EN1; + + writel(tsmr, mem_map + PTP_TSMR); + + return 0; +} + +static u32 ptp_tsu_disable(struct ptp *p_ptp) +{ + void __iomem *mem_map; + u32 tsmr; + + mem_map = p_ptp->mem_map; + + tsmr = readl(mem_map + PTP_TSMR); + tsmr &= ~(PTP_TSMR_EN1); + writel(tsmr, mem_map + PTP_TSMR); + + return 0; +} + +static int ptp_tsu_config_events_mask(struct ptp *p_ptp, + u32 events_mask) +{ + + p_ptp->events_mask = events_mask; + + return 0; +} + +/* rtc configure function */ +static u32 rtc_enable(struct ptp_rtc *rtc, bool reset_clock) +{ + u32 tmr_ctrl; + + tmr_ctrl = readl(rtc->mem_map + PTP_TMR_CTRL); + if (reset_clock) { + writel((tmr_ctrl | RTC_TMR_CTRL_TMSR), + rtc->mem_map + PTP_TMR_CTRL); + + /*clear TMR_OFF*/ + writel(0, rtc->mem_map + PTP_TMR_OFF_L); + writel(0, rtc->mem_map + PTP_TMR_OFF_H); + } + + writel((tmr_ctrl | RTC_TMR_CTRL_TE), + rtc->mem_map + PTP_TMR_CTRL); + + return 0; +} + +static u32 rtc_disable(struct ptp_rtc *rtc) +{ + u32 tmr_ctrl; + + tmr_ctrl = readl(rtc->mem_map + PTP_TMR_CTRL); + writel((tmr_ctrl & ~RTC_TMR_CTRL_TE), + rtc->mem_map + PTP_TMR_CTRL); + + return 0; +} + +static u32 rtc_set_periodic_pulse( + struct ptp_rtc *rtc, + enum e_ptp_rtc_pulse_id pulse_ID, + u32 pulse_periodic) +{ + u32 factor; + + if (rtc->start_pulse_on_alarm) { + /*from the spec:the ratio between the prescale register value + *and the fiper value should be decisable by the clock period + *FIPER_VALUE = (prescale_value * tclk_per * N) - tclk_per*/ + factor = (u32)((pulse_periodic + rtc->clock_period_nansec) / + (rtc->clock_period_nansec * rtc->output_clock_divisor)); + + if ((factor * rtc->clock_period_nansec * + rtc->output_clock_divisor) < + (pulse_periodic + rtc->clock_period_nansec)) + pulse_periodic = ((factor * rtc->clock_period_nansec * + rtc->output_clock_divisor) - + rtc->clock_period_nansec); + } + + /* Decrease it to fix PPS question (frequecy error)*/ + pulse_periodic -= rtc->clock_period_nansec; + + writel((u32)pulse_periodic, rtc->mem_map + PTP_TMR_FIPER1 + + (pulse_ID * 4)); + return 0; +} + +static u32 ptp_rtc_set_periodic_pulse( + struct ptp *p_ptp, + enum e_ptp_rtc_pulse_id pulse_ID, + struct ptp_time *ptime) +{ + u32 ret; + u64 pulse_periodic; + + if (pulse_ID >= PTP_RTC_NUM_OF_PULSES) + return -1; + if (ptime->nsec < 0) + return -1; + + pulse_periodic = convert_unsigned_time(ptime); + if (pulse_periodic > 0xFFFFFFFF) + return -1; + + ret = rtc_set_periodic_pulse(p_ptp->rtc, pulse_ID, (u32)pulse_periodic); + + return ret; +} + +static u32 rtc_set_alarm( + struct ptp_rtc *rtc, + enum e_ptp_rtc_alarm_id alarm_ID, + u64 alarm_time) +{ + u32 fiper; + int i; + + if ((alarm_ID == e_PTP_RTC_ALARM_1) && rtc->start_pulse_on_alarm) + alarm_time -= (3 * rtc->clock_period_nansec); + + /*TMR_ALARM_L must be written first*/ + writel((u32)alarm_time, rtc->mem_map + PTP_TMR_ALARM1_L + + (alarm_ID * 4)); + writel((u32)(alarm_time >> 32), + rtc->mem_map + PTP_TMR_ALARM1_H + (alarm_ID * 4)); + + if ((alarm_ID == e_PTP_RTC_ALARM_1) && rtc->start_pulse_on_alarm) { + /*we must write the TMR_FIPER register again(hardware + *constraint),From the spec:in order to keep tracking + *the prescale output clock each tiem before enabling + *the fiper,the user must reset the fiper by writing + *a new value to the reigster*/ + for (i = 0; i < PTP_RTC_NUM_OF_PULSES; i++) { + fiper = readl(rtc->mem_map + PTP_TMR_FIPER1 + + (i * 4)); + writel(fiper, rtc->mem_map + PTP_TMR_FIPER1 + + (i * 4)); + } + } + + return 0; +} + +static u32 ptp_rtc_set_alarm( + struct ptp *p_ptp, + enum e_ptp_rtc_alarm_id alarm_ID, + struct ptp_time *ptime) +{ + u32 ret; + u64 alarm_time; + + if (alarm_ID >= PTP_RTC_NUM_OF_ALARMS) + return -1; + if (ptime->nsec < 0) + return -1; + + alarm_time = convert_unsigned_time(ptime); + + ret = rtc_set_alarm(p_ptp->rtc, alarm_ID, alarm_time); + + return ret; +} + +/* rtc ioctl function */ +/*get the current time from RTC time counter register*/ +static void ptp_rtc_get_current_time(struct ptp *p_ptp, + struct ptp_time *p_time) +{ + u64 times; + struct ptp_rtc *rtc = p_ptp->rtc; + + /*TMR_CNT_L must be read first to get an accurate value*/ + times = (u64)readl(rtc->mem_map + PTP_TMR_CNT_L); + times |= ((u64)readl(rtc->mem_map + PTP_TMR_CNT_H)) << 32; + + /*convert RTC time*/ + convert_rtc_time(×, p_time); +} + +static void ptp_rtc_reset_counter(struct ptp *p_ptp, struct ptp_time *p_time) +{ + u64 times; + struct ptp_rtc *rtc = p_ptp->rtc; + + times = convert_unsigned_time(p_time); + writel((u32)times, rtc->mem_map + PTP_TMR_CNT_L); + writel((u32)(times >> 32), rtc->mem_map + PTP_TMR_CNT_H); + +} + +static void rtc_modify_frequency_compensation( + struct ptp_rtc *rtc, + u32 freq_compensation) +{ + writel(freq_compensation, rtc->mem_map + PTP_TMR_ADD); +} + +/* Set the BD to ptp */ +int fec_ptp_do_txstamp(struct sk_buff *skb) +{ + struct iphdr *iph; + struct udphdr *udph; + + if (skb->len > 44) { + /* Check if port is 319 for PTP Event, and check for UDP */ + iph = ip_hdr(skb); + if (iph == NULL || iph->protocol != FEC_PACKET_TYPE_UDP) + return 0; + + udph = udp_hdr(skb); + if (udph != NULL && ntohs(udph->dest) == 319) + return 1; + } + + return 0; +} + +static int fec_get_tx_timestamp(struct fec_ptp_private *priv, + struct ptp_ts_data *pts, + struct ptp_time *tx_time) +{ + struct fec_ptp_data_t tmp; + int flag; + +#ifdef CONFIG_IN_BAND + u8 mode; + tmp.key = pts->seq_id; + memcpy(tmp.spid, pts->spid, 10); + mode = pts->message_type; + + switch (mode) { + case PTP_MSG_SYNC: + flag = fec_ptp_find_and_remove(&(priv->tx_time_sync), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->tx_time_del_req), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + + case PTP_MSG_P_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->tx_time_pdel_req), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + flag = fec_ptp_find_and_remove(&(priv->tx_time_pdel_resp), + &tmp, priv, DEFAULT_PTP_TX_BUF_SZ); + break; + + default: + flag = 1; + printk(KERN_ERR "ERROR\n"); + break; + } + + if (!flag) { + tx_time->sec = tmp.ts_time.sec; + tx_time->nsec = tmp.ts_time.nsec; + return 0; + } else { + wait_event_interruptible_timeout(ptp_tx_ts_wait, 0, + PTP_GET_TX_TIMEOUT); + + switch (mode) { + case PTP_MSG_SYNC: + flag = fec_ptp_find_and_remove(&(priv->tx_time_sync), + &tmp, priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_DEL_REQ: + flag = fec_ptp_find_and_remove( + &(priv->tx_time_del_req), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_P_DEL_REQ: + flag = fec_ptp_find_and_remove( + &(priv->tx_time_pdel_req), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + flag = fec_ptp_find_and_remove( + &(priv->tx_time_pdel_resp), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + break; + } + + if (flag == 0) { + tx_time->sec = tmp.ts_time.sec; + tx_time->nsec = tmp.ts_time.nsec; + return 0; + } + + return -1; + } + +#else + memset(tmp.spid, 0, 10); + tmp.key = SEQ_ID_OUT_OF_BAND; + + flag = fec_ptp_find_and_remove(&(priv->txstamp), &tmp, + priv, DEFAULT_PTP_TX_BUF_SZ); + tx_time->sec = tmp.ts_time.sec; + tx_time->nsec = tmp.ts_time.nsec; + return 0; +#endif +} + +static uint8_t fec_get_rx_timestamp(struct fec_ptp_private *priv, + struct ptp_ts_data *pts, + struct ptp_time *rx_time) +{ + struct fec_ptp_data_t tmp; + int flag; + u8 mode; + +#ifdef CONFIG_IN_BAND + tmp.key = pts->seq_id; + memcpy(tmp.spid, pts->spid, 10); +#else + memset(tmp.spid, 0, 10); + tmp.key = SEQ_ID_OUT_OF_BAND; +#endif + mode = pts->message_type; + switch (mode) { + case PTP_MSG_SYNC: + flag = fec_ptp_find_and_remove(&(priv->rx_time_sync), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->rx_time_del_req), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + + case PTP_MSG_P_DEL_REQ: + flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_req), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + flag = fec_ptp_find_and_remove(&(priv->rx_time_pdel_resp), + &tmp, priv, DEFAULT_PTP_RX_BUF_SZ); + break; + + default: + flag = 1; + printk(KERN_ERR "ERROR\n"); + break; + } + + if (!flag) { + rx_time->sec = tmp.ts_time.sec; + rx_time->nsec = tmp.ts_time.nsec; + return 0; + } else { + wait_event_interruptible_timeout(ptp_rx_ts_wait, 0, + PTP_GET_RX_TIMEOUT); + + switch (mode) { + case PTP_MSG_SYNC: + flag = fec_ptp_find_and_remove(&(priv->rx_time_sync), + &tmp, priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_DEL_REQ: + flag = fec_ptp_find_and_remove( + &(priv->rx_time_del_req), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_P_DEL_REQ: + flag = fec_ptp_find_and_remove( + &(priv->rx_time_pdel_req), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + case PTP_MSG_P_DEL_RESP: + flag = fec_ptp_find_and_remove( + &(priv->rx_time_pdel_resp), &tmp, + priv, DEFAULT_PTP_RX_BUF_SZ); + break; + } + + if (flag == 0) { + rx_time->sec = tmp.ts_time.sec; + rx_time->nsec = tmp.ts_time.nsec; + return 0; + } + + return -1; + } +} + +/* 1588 Module start */ +int fec_ptp_start(struct fec_ptp_private *priv) +{ + struct ptp *p_ptp = ptp_dev; + + /* Enable TSU clk */ + clk_enable(p_ptp->clk); + + /*initialize the TSU using the register function*/ + init_ptp_tsu(p_ptp); + + /* start counter */ + p_ptp->fpp = ptp_private; + ptp_tsu_enable(p_ptp); + + return 0; +} + +/* Cleanup routine for 1588 module. + * When PTP is disabled this routing is called */ +void fec_ptp_stop(struct fec_ptp_private *priv) +{ + struct ptp *p_ptp = ptp_dev; + + /* stop counter */ + ptp_tsu_disable(p_ptp); + clk_disable(p_ptp->clk); + + return; +} + +static int ptp_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int ptp_release(struct inode *inode, struct file *file) +{ + return 0; +} + +/* ptp device ioctl function */ +static int ptp_ioctl( + struct inode *inode, + struct file *file, + unsigned int cmd, + unsigned long arg) +{ + struct ptp_rtc_time *cnt; + struct ptp_rtc_time curr_time; + struct ptp_time rx_time, tx_time; + struct ptp_ts_data *p_ts; + struct ptp_set_comp *p_comp; + struct fec_ptp_private *priv; + int retval = 0; + + priv = (struct fec_ptp_private *) ptp_private; + switch (cmd) { + case PTP_GET_RX_TIMESTAMP: + p_ts = (struct ptp_ts_data *)arg; + retval = fec_get_rx_timestamp(priv, p_ts, &rx_time); + if (retval == 0) + retval = copy_to_user((void __user *)(&(p_ts->ts)), + &rx_time, sizeof(rx_time)); + break; + case PTP_GET_TX_TIMESTAMP: + p_ts = (struct ptp_ts_data *)arg; + fec_get_tx_timestamp(priv, p_ts, &tx_time); + retval = copy_to_user((void __user *)(&(p_ts->ts)), + &tx_time, sizeof(tx_time)); + break; + case PTP_GET_CURRENT_TIME: + ptp_rtc_get_current_time(ptp_dev, &(curr_time.rtc_time)); + retval = copy_to_user((void __user *)arg, &curr_time, + sizeof(curr_time)); + break; + case PTP_SET_RTC_TIME: + cnt = (struct ptp_rtc_time *)arg; + ptp_rtc_reset_counter(ptp_dev, &(cnt->rtc_time)); + break; + case PTP_FLUSH_TIMESTAMP: + /* reset sync buffer */ + priv->rx_time_sync.head = 0; + priv->rx_time_sync.tail = 0; + /* reset delay_req buffer */ + priv->rx_time_del_req.head = 0; + priv->rx_time_del_req.tail = 0; + /* reset pdelay_req buffer */ + priv->rx_time_pdel_req.head = 0; + priv->rx_time_pdel_req.tail = 0; + /* reset pdelay_resp buffer */ + priv->rx_time_pdel_resp.head = 0; + priv->rx_time_pdel_resp.tail = 0; + /* reset sync buffer */ + priv->tx_time_sync.head = 0; + priv->tx_time_sync.tail = 0; + /* reset delay_req buffer */ + priv->tx_time_del_req.head = 0; + priv->tx_time_del_req.tail = 0; + /* reset pdelay_req buffer */ + priv->tx_time_pdel_req.head = 0; + priv->tx_time_pdel_req.tail = 0; + /* reset pdelay_resp buffer */ + priv->tx_time_pdel_resp.head = 0; + priv->tx_time_pdel_resp.tail = 0; + priv->txstamp.head = 0; + priv->txstamp.tail = 0; + break; + case PTP_SET_COMPENSATION: + p_comp = (struct ptp_set_comp *)arg; + rtc_modify_frequency_compensation(ptp_dev->rtc, + p_comp->freq_compensation); + break; + case PTP_GET_ORIG_COMP: + ((struct ptp_get_comp *)arg)->dw_origcomp = + ptp_dev->orig_freq_comp; + break; + default: + return -EINVAL; + } + return retval; +} + +static const struct file_operations ptp_fops = { + .owner = THIS_MODULE, + .llseek = NULL, + .read = NULL, + .write = NULL, + .ioctl = ptp_ioctl, + .open = ptp_open, + .release = ptp_release, +}; + +static int init_ptp_driver(struct ptp *p_ptp) +{ + struct ptp_time ptime; + int ret; + + /* configure RTC param */ + ret = ptp_rtc_config(p_ptp->rtc); + if (ret) + return -1; + + /* initialize RTC register */ + ptp_rtc_init(p_ptp); + + /* initialize PTP TSU param */ + ptp_param_config(p_ptp); + + /* set TSU configuration parameters */ +#ifdef CONFIG_IN_BAND + p_ptp->driver_param->delivery_mode = e_PTP_TSU_DELIVERY_IN_BAND; +#else + p_ptp->driver_param->delivery_mode = e_PTP_TSU_DELIVERY_OUT_OF_BAND; +#endif + + if (ptp_tsu_config_events_mask(p_ptp, DEFAULT_events_PTP_Mask)) + goto end; + + /* initialize PTP TSU register */ + ptp_tsu_init(p_ptp); + + /* set periodic pulses */ + ptime.sec = USE_CASE_PULSE_1_PERIOD / NANOSEC_IN_SEC; + ptime.nsec = USE_CASE_PULSE_1_PERIOD % NANOSEC_IN_SEC; + ret = ptp_rtc_set_periodic_pulse(p_ptp, e_PTP_RTC_PULSE_1, &ptime); + if (ret) + goto end; + + ptime.sec = USE_CASE_PULSE_2_PERIOD / NANOSEC_IN_SEC; + ptime.nsec = USE_CASE_PULSE_2_PERIOD % NANOSEC_IN_SEC; + ret = ptp_rtc_set_periodic_pulse(p_ptp, e_PTP_RTC_PULSE_2, &ptime); + if (ret) + goto end; + + ptime.sec = USE_CASE_PULSE_3_PERIOD / NANOSEC_IN_SEC; + ptime.nsec = USE_CASE_PULSE_3_PERIOD % NANOSEC_IN_SEC; + ret = ptp_rtc_set_periodic_pulse(p_ptp, e_PTP_RTC_PULSE_3, &ptime); + if (ret) + goto end; + + /* set alarm */ + ptime.sec = (USE_CASE_ALARM_1_TIME / NANOSEC_IN_SEC); + ptime.nsec = (USE_CASE_ALARM_1_TIME % NANOSEC_IN_SEC); + ret = ptp_rtc_set_alarm(p_ptp, e_PTP_RTC_ALARM_1, &ptime); + if (ret) + goto end; + + ptime.sec = (USE_CASE_ALARM_2_TIME / NANOSEC_IN_SEC); + ptime.nsec = (USE_CASE_ALARM_2_TIME % NANOSEC_IN_SEC); + ret = ptp_rtc_set_alarm(p_ptp, e_PTP_RTC_ALARM_2, &ptime); + if (ret) + goto end; + + /* enable the RTC */ + ret = rtc_enable(p_ptp->rtc, FALSE); + if (ret) + goto end; + + udelay(10); + ptp_rtc_get_current_time(p_ptp, &ptime); + if (ptime.nsec == 0) { + printk(KERN_ERR "PTP RTC is not running\n"); + goto end; + } + + if (register_chrdev(PTP_MAJOR, "ptp", &ptp_fops)) + printk(KERN_ERR "Unable to register PTP device as char\n"); + else + printk(KERN_INFO "Register PTP as char device\n"); + +end: + return ret; +} + +static void ptp_free(void) +{ + rtc_disable(ptp_dev->rtc); + /*unregister the PTP device*/ + unregister_chrdev(PTP_MAJOR, "ptp"); +} + +/* + * Resource required for accessing 1588 Timer Registers. + */ +int fec_ptp_init(struct fec_ptp_private *priv, int id) +{ + fec_ptp_init_circ(&(priv->rx_time_sync), DEFAULT_PTP_RX_BUF_SZ); + fec_ptp_init_circ(&(priv->rx_time_del_req), DEFAULT_PTP_RX_BUF_SZ); + fec_ptp_init_circ(&(priv->rx_time_pdel_req), DEFAULT_PTP_RX_BUF_SZ); + fec_ptp_init_circ(&(priv->rx_time_pdel_resp), DEFAULT_PTP_RX_BUF_SZ); + fec_ptp_init_circ(&(priv->tx_time_sync), DEFAULT_PTP_TX_BUF_SZ); + fec_ptp_init_circ(&(priv->tx_time_del_req), DEFAULT_PTP_TX_BUF_SZ); + fec_ptp_init_circ(&(priv->tx_time_pdel_req), DEFAULT_PTP_TX_BUF_SZ); + fec_ptp_init_circ(&(priv->tx_time_pdel_resp), DEFAULT_PTP_TX_BUF_SZ); + + fec_ptp_init_circ(&(priv->txstamp), DEFAULT_PTP_TX_BUF_SZ); + + spin_lock_init(&priv->ptp_lock); + spin_lock_init(&priv->cnt_lock); + ptp_private = priv; + + return 0; +} +EXPORT_SYMBOL(fec_ptp_init); + +void fec_ptp_cleanup(struct fec_ptp_private *priv) +{ + if (priv->rx_time_sync.buf) + vfree(priv->rx_time_sync.buf); + if (priv->rx_time_del_req.buf) + vfree(priv->rx_time_del_req.buf); + if (priv->rx_time_pdel_req.buf) + vfree(priv->rx_time_pdel_req.buf); + if (priv->rx_time_pdel_resp.buf) + vfree(priv->rx_time_pdel_resp.buf); + if (priv->tx_time_sync.buf) + vfree(priv->tx_time_sync.buf); + if (priv->tx_time_del_req.buf) + vfree(priv->tx_time_del_req.buf); + if (priv->tx_time_pdel_req.buf) + vfree(priv->tx_time_pdel_req.buf); + if (priv->tx_time_pdel_resp.buf) + vfree(priv->tx_time_pdel_resp.buf); + if (priv->txstamp.buf) + vfree(priv->txstamp.buf); + + ptp_free(); +} +EXPORT_SYMBOL(fec_ptp_cleanup); + +/* probe just register memory and irq */ +static int __devinit +ptp_probe(struct platform_device *pdev) +{ + int i, irq, ret = 0; + struct resource *r; + + /* setup board info structure */ + ptp_dev = kzalloc(sizeof(struct ptp), GFP_KERNEL); + if (!ptp_dev) { + ret = -ENOMEM; + goto err1; + } + ptp_dev->rtc = kzalloc(sizeof(struct ptp_rtc), + GFP_KERNEL); + if (!ptp_dev->rtc) { + ret = -ENOMEM; + goto err2; + } + + /* PTP register memory */ + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENXIO; + goto err3; + } + + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (!r) { + ret = -EBUSY; + goto err3; + } + + ptp_dev->mem_map = ioremap(r->start, resource_size(r)); + if (!ptp_dev->mem_map) { + ret = -ENOMEM; + goto failed_ioremap; + } + + /* RTC register memory */ + r = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!r) { + ret = -ENXIO; + goto err4; + } + + r = request_mem_region(r->start, resource_size(r), "PTP_RTC"); + if (!r) { + ret = -EBUSY; + goto err4; + } + + ptp_dev->rtc->mem_map = ioremap(r->start, resource_size(r)); + + if (!ptp_dev->rtc->mem_map) { + ret = -ENOMEM; + goto failed_ioremap1; + } + + /* This device has up to two irqs on some platforms */ + for (i = 0; i < 2; i++) { + irq = platform_get_irq(pdev, i); + if (i && irq < 0) + break; + if (i == 0) + ret = request_irq(irq, ptp_interrupt, + IRQF_DISABLED, pdev->name, ptp_dev); + else + ret = request_irq(irq, ptp_rtc_interrupt, + IRQF_DISABLED, "ptp_rtc", ptp_dev); + if (ret) { + while (i >= 0) { + irq = platform_get_irq(pdev, i); + free_irq(irq, ptp_dev); + i--; + } + goto failed_irq; + } + } + + ptp_dev->rtc->clk = clk_get(NULL, "ieee_rtc_clk"); + if (IS_ERR(ptp_dev->rtc->clk)) { + ret = PTR_ERR(ptp_dev->rtc->clk); + goto failed_clk1; + } + + ptp_dev->clk = clk_get(&pdev->dev, "ieee_1588_clk"); + if (IS_ERR(ptp_dev->clk)) { + ret = PTR_ERR(ptp_dev->clk); + goto failed_clk2; + } + + clk_enable(ptp_dev->clk); + + init_ptp_driver(ptp_dev); + clk_disable(ptp_dev->clk); + + return 0; + +failed_clk2: + clk_put(ptp_dev->rtc->clk); +failed_clk1: + for (i = 0; i < 2; i++) { + irq = platform_get_irq(pdev, i); + if (irq > 0) + free_irq(irq, ptp_dev); + } +failed_irq: + iounmap((void __iomem *)ptp_dev->rtc->mem_map); +failed_ioremap1: +err4: + iounmap((void __iomem *)ptp_dev->mem_map); +failed_ioremap: +err3: + kfree(ptp_dev->rtc); +err2: + kfree(ptp_dev); +err1: + return ret; +} + +static int __devexit +ptp_drv_remove(struct platform_device *pdev) +{ + clk_disable(ptp_dev->clk); + clk_put(ptp_dev->clk); + clk_put(ptp_dev->rtc->clk); + iounmap((void __iomem *)ptp_dev->rtc->mem_map); + iounmap((void __iomem *)ptp_dev->mem_map); + kfree(ptp_dev->rtc->driver_param); + kfree(ptp_dev->rtc); + kfree(ptp_dev->driver_param); + kfree(ptp_dev); + return 0; +} + +static struct platform_driver ptp_driver = { + .driver = { + .name = "ptp", + .owner = THIS_MODULE, + }, + .probe = ptp_probe, + .remove = __devexit_p(ptp_drv_remove), +}; + +static int __init +ptp_module_init(void) +{ + printk(KERN_INFO "iMX PTP Driver\n"); + + return platform_driver_register(&ptp_driver); +} + +static void __exit +ptp_cleanup(void) +{ + platform_driver_unregister(&ptp_driver); +} + +module_exit(ptp_cleanup); +module_init(ptp_module_init); + +MODULE_LICENSE("GPL"); diff --git a/drivers/net/imx_ptp.h b/drivers/net/imx_ptp.h new file mode 100644 index 000000000000..53a49779010c --- /dev/null +++ b/drivers/net/imx_ptp.h @@ -0,0 +1,356 @@ +/* + * drivers/net/imx_ptp.h + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. All rights reserved. + * + * Description: IEEE 1588 driver supporting imx5 Fast Ethernet Controller. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _PTP_H_ +#define _PTP_H_ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#define PTP_NUM_OF_PORTS 2 +#define SEQ_ID_OUT_OF_BAND 0xFFFF + +/* PTP message types */ +enum e_ptp_message { + e_PTP_MSG_SYNC = 0, /*Sync message*/ + e_PTP_MSG_DELAY_REQ, /*Dealy_req message*/ + e_PTP_MSG_FOLLOW_UP, /*Follow_up message*/ + e_PTP_MSG_DELAY_RESP, /*Delay_resp message*/ + e_PTP_MSG_MANAGEMENT, /*Management message*/ + e_PTP_MSG_DUMMY_LAST +}; + +/* PTP time stamp delivery mode*/ +enum e_ptp_tsu_delivery_mode { + e_PTP_TSU_DELIVERY_IN_BAND, /*in-band time-sttamp delivery mode*/ + e_PTP_TSU_DELIVERY_OUT_OF_BAND /*out-of-band time stamp delivery mode*/ +}; + +/*PTP RTC Alarm Polarity Options*/ +enum e_ptp_rtc_alarm_polarity { + e_PTP_RTC_ALARM_POLARITY_ACTIVE_HIGH, /*active-high output polarity*/ + e_PTP_RTC_ALARM_POLARITY_ACTIVE_LOW /*active-low output polarity*/ +}; + +/*PTP RTC Trigger Polarity Options*/ +enum e_ptp_rtc_trig_polarity { + e_PTP_RTC_TRIGGER_ON_RISING_EDGE, /*trigger on rising edge*/ + e_PTP_RTC_TRIGGER_ON_FALLING_EDGE /*trigger on falling edge*/ +}; + +/*PTP RTC Periodic Pulse Start Mode*/ +enum e_ptp_rtc_pulse_start_mode { + e_PTP_RTC_PULSE_START_AUTO, /*start pulse when RTC is enabled*/ + e_PTP_RTC_PULSE_START_ON_ALARM /*start pulse on alarm 1 event*/ +}; + +/*PTP RTC Alarm ID*/ +enum e_ptp_rtc_alarm_id { + e_PTP_RTC_ALARM_1 = 0, /*alarm signal 1*/ + e_PTP_RTC_ALARM_2, /*slarm signal 2*/ + e_PTP_RTC_ALARM_DUMMY_LAST +}; +#define PTP_RTC_NUM_OF_ALARMS e_PTP_RTC_ALARM_DUMMY_LAST + +/*PTP RTC Periodic Pulse ID*/ +enum e_ptp_rtc_pulse_id { + e_PTP_RTC_PULSE_1 = 0, /*periodic pulse 1*/ + e_PTP_RTC_PULSE_2, /*periodic pulse 2*/ + e_PTP_RTC_PULSE_3, /*periodic pulse 3*/ + e_PTP_RTC_PULSE_DUMMY_LASR +}; +#define PTP_RTC_NUM_OF_PULSES e_PTP_RTC_PULSE_DUMMY_LASR + +/*PTP RTC External trigger ID*/ +enum e_ptp_rtc_trigger_id { + e_PTP_RTC_TRIGGER_1 = 0, /*External trigger 1*/ + e_PTP_RTC_TRIGGER_2, /*External trigger 2*/ + e_PTP_RTC_TRIGGER_DUMMY_LAST +}; +#define PTP_RTC_NUM_OF_TRIGGERS e_PTP_RTC_TRIGGER_DUMMY_LAST + +/* PTP register definition */ +#define PTP_TSPDR1 0x0 +#define PTP_TSPDR2 0x4 +#define PTP_TSPDR3 0x8 +#define PTP_TSPDR4 0xc +#define PTP_TSPOV 0x10 +#define PTP_TSMR 0x14 +#define PTP_TMR_PEVENT 0x18 +#define PTP_TMR_PEMASK 0x1c +#define PTP_TMR_RXTS_H 0x20 +#define PTP_TMR_RXTS_L 0x30 +#define PTP_TMR_TXTS_H 0x40 +#define PTP_TMR_TXTS_L 0x50 +#define PTP_TSPDR5 0x60 +#define PTP_TSPDR6 0x64 +#define PTP_TSPDR7 0x68 + +/* RTC register definition */ +#define PTP_TMR_CTRL 0x0 +#define PTP_TMR_TEVENT 0x4 +#define PTP_TMR_TEMASK 0x8 +#define PTP_TMR_CNT_L 0xc +#define PTP_TMR_CNT_H 0x10 +#define PTP_TMR_ADD 0x14 +#define PTP_TMR_ACC 0x18 +#define PTP_TMR_PRSC 0x1c +#define PTP_TMR_OFF_L 0x20 +#define PTP_TMR_OFF_H 0x24 +#define PTP_TMR_ALARM1_L 0x28 +#define PTP_TMR_ALARM1_H 0x2c +#define PTP_TMR_ALARM2_L 0x30 +#define PTP_TMR_ALARM2_H 0x34 +#define PTP_TMR_FIPER1 0x38 +#define PTP_TMR_FIPER2 0x3c +#define PTP_TMR_FIPER3 0x40 +#define PTP_TMR_ETTS1_L 0x44 +#define PTP_TMR_ETTS1_H 0x48 +#define PTP_TMR_ETTS2_L 0x4c +#define PTP_TMR_ETTS2_H 0x50 +#define PTP_TMR_FSV_L 0x54 +#define PTP_TMR_FSV_H 0x58 + +/* PTP parser registers*/ +#define PTP_TSPDR1_ETT_MASK 0xFFFF0000 +#define PTP_TSPDR1_IPT_MASK 0x0000FF00 +#define PTP_TSPDR1_ETT_SHIFT 16 +#define PTP_TSPDR1_IPT_SHIFT 8 + +#define PTP_TSPDR2_DPNGE_MASK 0xFFFF0000 +#define PTP_TSPDR2_DPNEV_MASK 0x0000FFFF +#define PTP_TSPDR2_DPNGE_SHIFT 16 + +#define PTP_TSPDR3_SYCTL_MASK 0xFF000000 +#define PTP_TSPDR3_DRCTL_MASK 0x00FF0000 +#define PTP_TSPDR3_DRPCTL_MASK 0x0000FF00 +#define PTP_TSPDR3_FUCTL_MASK 0x000000FF +#define PTP_TSPDR3_SYCTL_SHIFT 24 +#define PTP_TSPDR3_DRCTL_SHIFT 16 +#define PTP_TSPDR3_DRPCTL_SHIFT 8 + +#define PTP_TSPDR4_MACTL_MASK 0xFF000000 +#define PTP_TSPDR4_VLAN_MASK 0x0000FFFF +#define PTP_TSPDR4_MACTL_SHIFT 24 + +/*PTP Parsing Offset Values*/ +#define PTP_TSPOV_ETTOF_MASK 0xFF000000 +#define PTP_TSPOV_IPTOF_MASK 0x00FF0000 +#define PTP_TSPOV_UDOF_MASK 0x0000FF00 +#define PTP_TSPOV_PTOF_MASK 0x000000FF +#define PTP_TSPOV_ETTOF_SHIFT 24 +#define PTP_TSPOV_IPTOF_SHIFT 16 +#define PTP_TSPOV_UDOF_SHIFT 8 + +/*PTP Mode register*/ +#define PTP_TSMR_OPMODE1_IN_BAND 0x00080000 +#define PTP_TSMR_OPMODE2_IN_BAND 0x00040000 +#define PTP_TSMR_OPMODE3_IN_BAND 0x00020000 +#define PTP_TSMR_OPMODE4_IN_BAND 0x00010000 +#define PTP_TSMR_EN1 0x00000008 +#define PTP_TSMR_EN2 0x00000004 +#define PTP_TSMR_EN3 0x00000002 +#define PTP_TSMR_EN4 0x00000001 + +/*ptp tsu event register*/ +#define PTP_TS_EXR 0x80000000 /*rx, EX to receiver */ +#define PTP_TS_RX_OVR1 0x40000000 /*rx,overrun */ +#define PTP_TS_TX_OVR1 0x20000000 /*tx,overrun */ +#define PTP_TS_RX_SYNC1 0x10000000 /*rx,Sync Frame */ +#define PTP_TS_RX_DELAY_REQ1 0x08000000 /*rx,dealy_req frame */ +#define PTP_TS_TX_FRAME1 0x04000000 /*tx,PTP frame */ +#define PTP_TS_PDRQRE1 0x02000000 /*rx,Pdelay_Req frame */ +#define PTP_TS_PDRSRE1 0x01000000 /*rx,Pdelay_Resp frame */ +#define PTP_TS_EXT 0x00800000 /*tx, EX to transmitter */ +#define DEFAULT_events_PTP_Mask 0xFF800000 +#define PTP_TMR_PEVENT_ALL DEFAULT_events_PTP_Mask +#define PTP_TMR_PEVENT_VALID 0x7F000000 + +#define PTP_TS_RX_ALL \ + (PTP_TS_RX_SYNC1 |\ + PTP_TS_RX_DELAY_REQ1 |\ + PTP_TS_PDRQRE1 |\ + PTP_TS_PDRSRE1) + +/*RTC timer control register*/ +#define RTC_TMR_CTRL_ALMP1 0x80000000 /*active low output*/ +#define RTC_TMR_CTRL_ALMP2 0x40000000 /*active low output*/ +#define RTC_TMR_CTRL_FS 0x10000000 +#define RTC_TMR_CTRL_TCLK_PERIOD_MSK 0x03FF0000 +#define RTC_TMR_CTRL_ETEP2 0x00000200 +#define RTC_TMR_CTRL_ETEP1 0x00000100 +#define RTC_TMR_CTRL_COPH 0x00000080 +#define RTC_TMR_CTRL_CIPH 0x00000040 +#define RTC_TMR_CTRL_TMSR 0x00000020 +#define RTC_TMR_CTRL_DBG 0x00000010 +#define RTC_TMR_CTRL_BYP 0x00000008 +#define RTC_TMR_CTRL_TE 0x00000004 +#define RTC_TMR_CTRL_CKSEL_TX_CLK 0x00000002 +#define RTC_TMR_CTRL_CKSEL_QE_CLK 0x00000001 +#define RTC_TMR_CTRL_CKSEL_EXT_CLK 0x00000000 +#define RTC_TMR_CTRL_TCLK_PERIOD_SHIFT 16 + +/*RTC event register*/ +#define RTC_TEVENT_EXT_TRIGGER_2_TS 0x02000000 /*External trigger2 TS*/ +#define RTC_TEVENT_EXT_TRIGGER_1_TS 0x01000000 /*External trigger1 TS*/ +#define RTC_TEVENT_ALARM_2 0x00020000 /*Alarm 2*/ +#define RTC_TEVENT_ALARM_1 0x00010000 /*Alarm 1*/ +#define RTC_TEVENT_PERIODIC_PULSE_1 0x00000080 /*Periodic pulse 1*/ +#define RTC_TEVENT_PERIODIC_PULSE_2 0x00000040 /*Periodic pulse 2*/ +#define RTC_TEVENT_PERIODIC_PULSE_3 0x00000020 /*Periodic pulse 3*/ + +#define RTC_EVENT_ALL \ + (RTC_TEVENT_EXT_TRIGGER_2_TS |\ + RTC_TEVENT_EXT_TRIGGER_1_TS |\ + RTC_TEVENT_ALARM_2 |\ + RTC_TEVENT_ALARM_1 |\ + RTC_TEVENT_PERIODIC_PULSE_1 |\ + RTC_TEVENT_PERIODIC_PULSE_2 |\ + RTC_TEVENT_PERIODIC_PULSE_3) + +#define OFFSET_RTC 0x0000 +#define OFFSET_PTP1 0x0080 +#define OFFSET_PTP2 0x0100 + +#define NUM_OF_MODULE 2 + +/*General definitions*/ +#define NANOSEC_PER_ONE_HZ_TICK 1000000000 +#define NANOSEC_IN_SEC NANOSEC_PER_ONE_HZ_TICK +#define MIN_RTC_CLK_FREQ_HZ 1000 +#define MHZ 1000000 +#define PTP_RTC_FREQ 50 /*MHz*/ + +/*PTP driver's default values*/ +#define ETH_TYPE_VALUE 0x0800 /*IP frame*/ +#define VLAN_TYPE_VALUE 0x8100 +#define IP_TYPE_VALUE 0x11 /*UDP frame*/ +#define UDP_GENERAL_PORT 320 +#define UDP_EVENT_PORT 319 +#define ETH_TYPE_OFFSET 12 +#define IP_TYPE_OFFSET 23 +#define UDP_DEST_PORT_OFFSET 36 +#define PTP_TYPE_OFFSET 74 +#define PTP_SEQUENCE_OFFSET 72 +#define LENGTH_OF_TS 8 + +#define PTP_TX 0x00800000 +#define PTP_RX 0x02000000 + +/*RTC default values*/ +#define DEFAULT_SRC_CLOCK 0 /*external clock source*/ +#define DEFAULT_BYPASS_COMPENSATION FALSE +#define DEFAULT_INVERT_INPUT_CLK_PHASE FALSE +#define DEFAULT_INVERT_OUTPUT_CLK_PHASE FALSE +#define DEFAULT_OUTPUT_CLOCK_DIVISOR 0x0001 +#define DEFAULT_ALARM_POLARITY e_PTP_RTC_ALARM_POLARITY_ACTIVE_HIGH +#define DEFAULT_TRIGGER_POLARITY e_PTP_RTC_TRIGGER_ON_RISING_EDGE +#define DEFAULT_PULSE_START_MODE e_PTP_RTC_PULSE_START_AUTO +#define DEFAULT_EVENTS_RTC_MASK RTC_EVENT_ALL + +/*PTP default message type*/ +#define DEFAULT_MSG_SYNC e_PTP_MSG_SYNC +#define DEFAULT_MSG_DELAY_REQ e_PTP_MSG_DELAY_REQ +#define DEFAULT_MSG_FOLLOW_UP e_PTP_MSG_FOLLOW_UP +#define DEFAULT_MSG_DELAY_RESP e_PTP_MSG_DELAY_RESP +#define DEFAULT_MSG_MANAGEMENT e_PTP_MSG_MANAGEMENT + +#define USE_CASE_PULSE_1_PERIOD (NANOSEC_IN_SEC) +#define USE_CASE_PULSE_2_PERIOD (NANOSEC_IN_SEC / 2) +#define USE_CASE_PULSE_3_PERIOD (NANOSEC_IN_SEC / 4) + +#define USE_CASE_ALARM_1_TIME (NANOSEC_IN_SEC) +#define USE_CASE_ALARM_2_TIME (NANOSEC_IN_SEC * 2) + +#define UCC_PTP_ENABLE 0x40000000 + +struct ptp_rtc_driver_param { + u32 src_clock; + u32 src_clock_freq_hz; + u32 rtc_freq_hz; + bool invert_input_clk_phase; + bool invert_output_clk_phase; + u32 events_mask; + enum e_ptp_rtc_pulse_start_mode pulse_start_mode; + enum e_ptp_rtc_alarm_polarity alarm_polarity[PTP_RTC_NUM_OF_ALARMS]; + enum e_ptp_rtc_trig_polarity trigger_polarity[PTP_RTC_NUM_OF_TRIGGERS]; +}; + +struct ptp_rtc { + void __iomem *mem_map; /*pointer to RTC mem*/ + bool bypass_compensation; /*is bypass?*/ + bool start_pulse_on_alarm; /*start on alarm 1*/ + u32 clock_period_nansec; /*clock periodic in ns*/ + u16 output_clock_divisor; /*clock divisor*/ + struct ptp_rtc_driver_param *driver_param; /*driver parameters*/ + u32 rtc_irq; + struct clk *clk; + struct { + void *ext_trig_timestamp_queue; + } ext_trig_ts[2]; /*external trigger ts*/ +}; + +/*PTP driver parameters*/ +struct ptp_driver_param { + u16 eth_type_value; + u16 vlan_type_value; + u16 udp_general_port; + u16 udp_event_port; + u8 ip_type_value; + u8 eth_type_offset; + u8 ip_type_offset; + u8 udp_dest_port_offset; /*offset of UDP destination port*/ + u8 ptp_type_offset; + u8 ptp_msg_codes[e_PTP_MSG_DUMMY_LAST]; + + enum e_ptp_tsu_delivery_mode delivery_mode; +}; + +/*PTP control structure*/ +struct ptp { + spinlock_t lock; + void __iomem *mem_map; + + /*TSU*/ + u32 events_mask; + struct fec_ptp_private *fpp; + struct clk *clk; + + /*RTC*/ + struct ptp_rtc *rtc; /*pointer to RTC control structure*/ + u32 orig_freq_comp; /*the initial frequency compensation*/ + + /*driver parameters*/ + struct ptp_driver_param *driver_param; + + u32 tx_time_stamps; + u32 rx_time_stamps; + u32 tx_time_stamps_overrun; + u32 rx_time_stamps_overrun; + u32 alarm_counters[PTP_RTC_NUM_OF_ALARMS]; + u32 pulse_counters[PTP_RTC_NUM_OF_PULSES]; +}; + +#endif diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig index 25bb2a015e18..c71ccb108a8a 100644 --- a/drivers/net/irda/Kconfig +++ b/drivers/net/irda/Kconfig @@ -403,5 +403,9 @@ config SH_IRDA help Say Y here if your want to enable SuperH IrDA devices. +config MXC_FIR + tristate "Freescale MXC FIR driver" + depends on ARCH_MXC && IRDA + endmenu diff --git a/drivers/net/irda/Makefile b/drivers/net/irda/Makefile index dfc64537f62f..36cbac4c5788 100644 --- a/drivers/net/irda/Makefile +++ b/drivers/net/irda/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_VLSI_FIR) += vlsi_ir.o obj-$(CONFIG_VIA_FIR) += via-ircc.o obj-$(CONFIG_PXA_FICP) += pxaficp_ir.o obj-$(CONFIG_MCS_FIR) += mcs7780.o +obj-$(CONFIG_MXC_FIR) += mxc_ir.o obj-$(CONFIG_AU1000_FIR) += au1k_ir.o obj-$(CONFIG_SH_IRDA) += sh_irda.o # SIR drivers diff --git a/drivers/net/irda/mxc_ir.c b/drivers/net/irda/mxc_ir.c new file mode 100644 index 000000000000..c3636d6bc553 --- /dev/null +++ b/drivers/net/irda/mxc_ir.c @@ -0,0 +1,1781 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * Based on sa1100_ir.c - Copyright 2000-2001 Russell King + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_ir.c + * + * @brief Driver for the Freescale Semiconductor MXC FIRI. + * + * This driver is based on drivers/net/irda/sa1100_ir.c, by Russell King. + * + * @ingroup FIRI + */ + +/* + * Include Files + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include "mxc_ir.h" + +#define IS_SIR(mi) ((mi)->speed <= 115200) +#define IS_MIR(mi) ((mi)->speed < 4000000 && (mi)->speed >= 576000) +#define IS_FIR(mi) ((mi)->speed >= 4000000) + +#define SDMA_START_DELAY() { \ + volatile int j, k;\ + int i;\ + for (i = 0; i < 10000; i++)\ + k = j;\ + } + +#define IRDA_FRAME_SIZE_LIMIT 2047 +#define UART_BUFF_SIZE 14384 + +#define UART4_UFCR_TXTL 16 +#define UART4_UFCR_RXTL 1 + +#define FIRI_SDMA_TX +#define FIRI_SDMA_RX + +/*! + * This structure is a way for the low level driver to define their own + * \b mxc_irda structure. This structure includes SK buffers, DMA buffers. + * and has other elements that are specifically required by this driver. + */ +struct mxc_irda { + /*! + * This keeps track of device is running or not + */ + unsigned char open; + + /*! + * This holds current FIRI communication speed + */ + int speed; + + /*! + * This holds FIRI communication speed for next packet + */ + int newspeed; + + /*! + * SK buffer for transmitter + */ + struct sk_buff *txskb; + + /*! + * SK buffer for receiver + */ + struct sk_buff *rxskb; + +#ifdef FIRI_SDMA_RX + /*! + * SK buffer for tasklet + */ + struct sk_buff *tskb; +#endif + + /*! + * DMA address for transmitter + */ + dma_addr_t dma_rx_buff_phy; + + /*! + * DMA address for receiver + */ + dma_addr_t dma_tx_buff_phy; + + /*! + * DMA Transmit buffer length + */ + unsigned int dma_tx_buff_len; + + /*! + * DMA channel for transmitter + */ + int txdma_ch; + + /*! + * DMA channel for receiver + */ + int rxdma_ch; + + /*! + * IrDA network device statistics + */ + struct net_device_stats stats; + + /*! + * The device structure used to get FIRI information + */ + struct device *dev; + + /*! + * Resource structure for UART, which will maintain base addresses and IRQs. + */ + struct resource *uart_res; + + /*! + * Base address of UART, used in readl and writel. + */ + void *uart_base; + + /*! + * Resource structure for FIRI, which will maintain base addresses and IRQs. + */ + struct resource *firi_res; + + /*! + * Base address of FIRI, used in readl and writel. + */ + void *firi_base; + + /*! + * UART IRQ number. + */ + int uart_irq; + + /*! + * Second UART IRQ number in case the interrupt lines are not muxed. + */ + int uart_irq1; + + /*! + * UART clock needed for baud rate calculations + */ + struct clk *uart_clk; + + /*! + * UART clock needed for baud rate calculations + */ + unsigned long uart_clk_rate; + + /*! + * FIRI clock needed for baud rate calculations + */ + struct clk *firi_clk; + + /*! + * FIRI IRQ number. + */ + int firi_irq; + + /*! + * IrLAP layer instance + */ + struct irlap_cb *irlap; + + /*! + * Driver supported baudrate capabilities + */ + struct qos_info qos; + + /*! + * Temporary transmit buffer used by the driver + */ + iobuff_t tx_buff; + + /*! + * Temporary receive buffer used by the driver + */ + iobuff_t rx_buff; + + /*! + * Pointer to platform specific data structure. + */ + struct mxc_ir_platform_data *mxc_ir_plat; + + /*! + * This holds the power management status of this module. + */ + int suspend; + +}; + +extern void gpio_firi_active(void *, unsigned int); +extern void gpio_firi_inactive(void); +extern void gpio_firi_init(void); + +void mxc_irda_firi_init(struct mxc_irda *si); +#ifdef FIRI_SDMA_RX +static void mxc_irda_fir_dma_rx_irq(void *id, int error_status, + unsigned int count); +#endif +#ifdef FIRI_SDMA_TX +static void mxc_irda_fir_dma_tx_irq(void *id, int error_status, + unsigned int count); +#endif + +/*! + * This function allocates and maps the receive buffer, + * unless it is already allocated. + * + * @param si FIRI device specific structure. + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_rx_alloc(struct mxc_irda *si) +{ +#ifdef FIRI_SDMA_RX + mxc_dma_requestbuf_t dma_request; +#endif + if (si->rxskb) { + return 0; + } + + si->rxskb = alloc_skb(IRDA_FRAME_SIZE_LIMIT + 1, GFP_ATOMIC); + + if (!si->rxskb) { + dev_err(si->dev, "mxc_ir: out of memory for RX SKB\n"); + return -ENOMEM; + } + + /* + * Align any IP headers that may be contained + * within the frame. + */ + skb_reserve(si->rxskb, 1); + +#ifdef FIRI_SDMA_RX + si->dma_rx_buff_phy = + dma_map_single(si->dev, si->rxskb->data, IRDA_FRAME_SIZE_LIMIT, + DMA_FROM_DEVICE); + + dma_request.num_of_bytes = IRDA_FRAME_SIZE_LIMIT; + dma_request.dst_addr = si->dma_rx_buff_phy; + dma_request.src_addr = si->firi_res->start; + + mxc_dma_config(si->rxdma_ch, &dma_request, 1, MXC_DMA_MODE_READ); +#endif + return 0; +} + +/*! + * This function is called to disable the FIRI dma + * + * @param si FIRI port specific structure. + */ +static void mxc_irda_disabledma(struct mxc_irda *si) +{ + /* Stop all DMA activity. */ +#ifdef FIRI_SDMA_TX + mxc_dma_disable(si->txdma_ch); +#endif +#ifdef FIRI_SDMA_RX + mxc_dma_disable(si->rxdma_ch); +#endif +} + +/*! + * This function is called to set the IrDA communications speed. + * + * @param si FIRI specific structure. + * @param speed new Speed to be configured for. + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_set_speed(struct mxc_irda *si, int speed) +{ + unsigned long flags; + int ret = 0; + unsigned int num, denom, baud; + unsigned int cr; + + dev_dbg(si->dev, "speed:%d\n", speed); + switch (speed) { + case 9600: + case 19200: + case 38400: + case 57600: + case 115200: + dev_dbg(si->dev, "starting SIR\n"); + baud = speed; + if (IS_FIR(si)) { +#ifdef FIRI_SDMA_RX + mxc_dma_disable(si->rxdma_ch); +#endif + cr = readl(si->firi_base + FIRITCR); + cr &= ~FIRITCR_TE; + writel(cr, si->firi_base + FIRITCR); + + cr = readl(si->firi_base + FIRIRCR); + cr &= ~FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + + } + local_irq_save(flags); + + /* Disable Tx and Rx */ + cr = readl(si->uart_base + MXC_UARTUCR2); + cr &= ~(MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN); + writel(cr, si->uart_base + MXC_UARTUCR2); + + gpio_firi_inactive(); + + num = baud / 100 - 1; + denom = si->uart_clk_rate / 1600 - 1; + if ((denom < 65536) && (si->uart_clk_rate > 1600)) { + writel(num, si->uart_base + MXC_UARTUBIR); + writel(denom, si->uart_base + MXC_UARTUBMR); + } + + si->speed = speed; + + writel(0xFFFF, si->uart_base + MXC_UARTUSR1); + writel(0xFFFF, si->uart_base + MXC_UARTUSR2); + + /* Enable Receive Overrun and Data Ready interrupts. */ + cr = readl(si->uart_base + MXC_UARTUCR4); + cr |= (MXC_UARTUCR4_OREN | MXC_UARTUCR4_DREN); + writel(cr, si->uart_base + MXC_UARTUCR4); + + cr = readl(si->uart_base + MXC_UARTUCR2); + cr |= (MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN); + writel(cr, si->uart_base + MXC_UARTUCR2); + + local_irq_restore(flags); + break; + case 4000000: + local_irq_save(flags); + + /* Disable Receive Overrun and Data Ready interrupts. */ + cr = readl(si->uart_base + MXC_UARTUCR4); + cr &= ~(MXC_UARTUCR4_OREN | MXC_UARTUCR4_DREN); + writel(cr, si->uart_base + MXC_UARTUCR4); + + /* Disable Tx and Rx */ + cr = readl(si->uart_base + MXC_UARTUCR2); + cr &= ~(MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN); + writel(cr, si->uart_base + MXC_UARTUCR2); + + /* + * FIR configuration + */ + mxc_irda_disabledma(si); + + cr = readl(si->firi_base + FIRITCR); + cr &= ~FIRITCR_TE; + writel(cr, si->firi_base + FIRITCR); + + gpio_firi_active(si->firi_base + FIRITCR, FIRITCR_TPP); + + si->speed = speed; + + cr = readl(si->firi_base + FIRIRCR); + cr |= FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + + dev_dbg(si->dev, "Going for fast IRDA ...\n"); + ret = mxc_irda_rx_alloc(si); + + /* clear RX status register */ + writel(0xFFFF, si->firi_base + FIRIRSR); +#ifdef FIRI_SDMA_RX + if (si->rxskb) { + mxc_dma_enable(si->rxdma_ch); + } +#endif + local_irq_restore(flags); + + break; + default: + dev_err(si->dev, "speed not supported by FIRI\n"); + break; + } + + return ret; +} + +/*! + * This function is called to set the IrDA communications speed. + * + * @param si FIRI specific structure. + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static inline int mxc_irda_fir_error(struct mxc_irda *si) +{ + struct sk_buff *skb = si->rxskb; + unsigned int dd_error, crc_error, overrun_error; + unsigned int sr; + + if (!skb) { + dev_err(si->dev, "no skb!\n"); + return -1; + } + + sr = readl(si->firi_base + FIRIRSR); + dd_error = sr & FIRIRSR_DDE; + crc_error = sr & FIRIRSR_CRCE; + overrun_error = sr & FIRIRSR_RFO; + + if (!(dd_error | crc_error | overrun_error)) { + return 0; + } + dev_err(si->dev, "dde,crce,rfo=%d,%d,%d.\n", dd_error, crc_error, + overrun_error); + si->stats.rx_errors++; + if (crc_error) { + si->stats.rx_crc_errors++; + } + if (dd_error) { + si->stats.rx_frame_errors++; + } + if (overrun_error) { + si->stats.rx_frame_errors++; + } + writel(sr, si->firi_base + FIRIRSR); + + return -1; +} + +#ifndef FIRI_SDMA_RX +/*! + * FIR interrupt service routine to handle receive. + * + * @param dev pointer to the net_device structure + */ +void mxc_irda_fir_irq_rx(struct net_device *dev) +{ + struct mxc_irda *si = dev->priv; + struct sk_buff *skb = si->rxskb; + unsigned int sr, len; + int i; + unsigned char *p = skb->data; + + /* + * Deal with any receive errors. + */ + if (mxc_irda_fir_error(si) != 0) { + return; + } + + sr = readl(si->firi_base + FIRIRSR); + + if (!(sr & FIRIRSR_RPE)) { + return; + } + + /* + * Coming here indicates that fir rx packet has been successfully recieved. + * And No error happened so far. + */ + writel(sr | FIRIRSR_RPE, si->firi_base + FIRIRSR); + + len = (sr & FIRIRSR_RFP) >> 8; + + /* 4 bytes of CRC */ + len -= 4; + + skb_put(skb, len); + + for (i = 0; i < len; i++) { + *p++ = readb(si->firi_base + FIRIRXFIFO); + } + + /* Discard the four CRC bytes */ + for (i = 0; i < 4; i++) { + readb(si->firi_base + FIRIRXFIFO); + } + + /* + * Deal with the case of packet complete. + */ + skb->dev = dev; + skb->mac.raw = skb->data; + skb->protocol = htons(ETH_P_IRDA); + si->stats.rx_packets++; + si->stats.rx_bytes += len; + netif_rx(skb); + + si->rxskb = NULL; + mxc_irda_rx_alloc(si); + + writel(0xFFFF, si->firi_base + FIRIRSR); + +} +#endif + +/*! + * FIR interrupt service routine to handle transmit. + * + * @param dev pointer to the net_device structure + */ +void mxc_irda_fir_irq_tx(struct net_device *dev) +{ + struct mxc_irda *si = netdev_priv(dev); + struct sk_buff *skb = si->txskb; + unsigned int cr, sr; + + sr = readl(si->firi_base + FIRITSR); + writel(sr, si->firi_base + FIRITSR); + + if (sr & FIRITSR_TC) { + +#ifdef FIRI_SDMA_TX + mxc_dma_disable(si->txdma_ch); +#endif + cr = readl(si->firi_base + FIRITCR); + cr &= ~(FIRITCR_TCIE | FIRITCR_TE); + writel(cr, si->firi_base + FIRITCR); + + if (si->newspeed) { + mxc_irda_set_speed(si, si->newspeed); + si->newspeed = 0; + } + si->txskb = NULL; + + cr = readl(si->firi_base + FIRIRCR); + cr |= FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + + writel(0xFFFF, si->firi_base + FIRIRSR); + /* + * Account and free the packet. + */ + if (skb) { +#ifdef FIRI_SDMA_TX + dma_unmap_single(si->dev, si->dma_tx_buff_phy, skb->len, + DMA_TO_DEVICE); +#endif + si->stats.tx_packets++; + si->stats.tx_bytes += skb->len; + dev_kfree_skb_irq(skb); + } + /* + * Make sure that the TX queue is available for sending + * (for retries). TX has priority over RX at all times. + */ + netif_wake_queue(dev); + } +} + +/*! + * This is FIRI interrupt handler. + * + * @param dev pointer to the net_device structure + */ +void mxc_irda_fir_irq(struct net_device *dev) +{ + struct mxc_irda *si = netdev_priv(dev); + unsigned int sr1, sr2; + + sr1 = readl(si->firi_base + FIRIRSR); + sr2 = readl(si->firi_base + FIRITSR); + + if (sr2 & FIRITSR_TC) + mxc_irda_fir_irq_tx(dev); +#ifndef FIRI_SDMA_RX + if (sr1 & (FIRIRSR_RPE | FIRIRSR_RFO)) + mxc_irda_fir_irq_rx(dev); +#endif + +} + +/*! + * This is the SIR transmit routine. + * + * @param si FIRI specific structure. + * + * @param dev pointer to the net_device structure + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_sir_txirq(struct mxc_irda *si, struct net_device *dev) +{ + unsigned int sr1, sr2, cr; + unsigned int status; + + sr1 = readl(si->uart_base + MXC_UARTUSR1); + sr2 = readl(si->uart_base + MXC_UARTUSR2); + cr = readl(si->uart_base + MXC_UARTUCR2); + + /* + * Echo cancellation for IRDA Transmit chars + * Disable the receiver and enable Transmit complete. + */ + cr &= ~MXC_UARTUCR2_RXEN; + writel(cr, si->uart_base + MXC_UARTUCR2); + cr = readl(si->uart_base + MXC_UARTUCR4); + cr |= MXC_UARTUCR4_TCEN; + writel(cr, si->uart_base + MXC_UARTUCR4); + + while ((sr1 & MXC_UARTUSR1_TRDY) && si->tx_buff.len) { + + writel(*si->tx_buff.data++, si->uart_base + MXC_UARTUTXD); + si->tx_buff.len -= 1; + sr1 = readl(si->uart_base + MXC_UARTUSR1); + } + + if (si->tx_buff.len == 0) { + si->stats.tx_packets++; + si->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head; + + /*Yoohoo...we are done...Lets stop Tx */ + cr = readl(si->uart_base + MXC_UARTUCR1); + cr &= ~MXC_UARTUCR1_TRDYEN; + writel(cr, si->uart_base + MXC_UARTUCR1); + + do { + status = readl(si->uart_base + MXC_UARTUSR2); + } while (!(status & MXC_UARTUSR2_TXDC)); + + if (si->newspeed) { + mxc_irda_set_speed(si, si->newspeed); + si->newspeed = 0; + } + /* I'm hungry! */ + netif_wake_queue(dev); + + /* Is the transmit complete to reenable the receiver? */ + if (status & MXC_UARTUSR2_TXDC) { + + cr = readl(si->uart_base + MXC_UARTUCR2); + cr |= MXC_UARTUCR2_RXEN; + writel(cr, si->uart_base + MXC_UARTUCR2); + /* Disable the Transmit complete interrupt bit */ + cr = readl(si->uart_base + MXC_UARTUCR4); + cr &= ~MXC_UARTUCR4_TCEN; + writel(cr, si->uart_base + MXC_UARTUCR4); + } + } + + return 0; +} + +/*! + * This is the SIR receive routine. + * + * @param si FIRI specific structure. + * + * @param dev pointer to the net_device structure + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_sir_rxirq(struct mxc_irda *si, struct net_device *dev) +{ + unsigned int data, status; + volatile unsigned int sr2; + + sr2 = readl(si->uart_base + MXC_UARTUSR2); + while ((sr2 & MXC_UARTUSR2_RDR) == 1) { + data = readl(si->uart_base + MXC_UARTURXD); + status = data & 0xf400; + if (status & MXC_UARTURXD_ERR) { + dev_err(si->dev, "Receive an incorrect data =0x%x.\n", + data); + si->stats.rx_errors++; + if (status & MXC_UARTURXD_OVRRUN) { + si->stats.rx_fifo_errors++; + dev_err(si->dev, "Rx overrun.\n"); + } + if (status & MXC_UARTURXD_FRMERR) { + si->stats.rx_frame_errors++; + dev_err(si->dev, "Rx frame error.\n"); + } + if (status & MXC_UARTURXD_PRERR) { + dev_err(si->dev, "Rx parity error.\n"); + } + /* Other: it is the Break char. + * Do nothing for it. throw out the data. + */ + async_unwrap_char(dev, &si->stats, &si->rx_buff, + (data & 0xFF)); + } else { + /* It is correct data. */ + data &= 0xFF; + async_unwrap_char(dev, &si->stats, &si->rx_buff, data); + + dev->last_rx = jiffies; + } + sr2 = readl(si->uart_base + MXC_UARTUSR2); + + writel(0xFFFF, si->uart_base + MXC_UARTUSR1); + writel(0xFFFF, si->uart_base + MXC_UARTUSR2); + } /*while */ + return 0; + +} + +static irqreturn_t mxc_irda_irq(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct mxc_irda *si = netdev_priv(dev); + + if (IS_FIR(si)) { + mxc_irda_fir_irq(dev); + return IRQ_HANDLED; + } + + if (readl(si->uart_base + MXC_UARTUCR2) & MXC_UARTUCR2_RXEN) { + mxc_irda_sir_rxirq(si, dev); + } + if ((readl(si->uart_base + MXC_UARTUCR1) & MXC_UARTUCR1_TRDYEN) && + (readl(si->uart_base + MXC_UARTUSR1) & MXC_UARTUSR1_TRDY)) { + mxc_irda_sir_txirq(si, dev); + } + + return IRQ_HANDLED; +} + +static irqreturn_t mxc_irda_tx_irq(int irq, void *dev_id) +{ + + struct net_device *dev = dev_id; + struct mxc_irda *si = netdev_priv(dev); + + mxc_irda_sir_txirq(si, dev); + + return IRQ_HANDLED; +} + +static irqreturn_t mxc_irda_rx_irq(int irq, void *dev_id) +{ + + struct net_device *dev = dev_id; + struct mxc_irda *si = netdev_priv(dev); + + /* Clear the aging timer bit */ + writel(MXC_UARTUSR1_AGTIM, si->uart_base + MXC_UARTUSR1); + + mxc_irda_sir_rxirq(si, dev); + + return IRQ_HANDLED; +} + +#ifdef FIRI_SDMA_RX +struct tasklet_struct dma_rx_tasklet; + +static void mxc_irda_rx_task(unsigned long tparam) +{ + struct mxc_irda *si = (struct mxc_irda *)tparam; + struct sk_buff *lskb = si->tskb; + + si->tskb = NULL; + if (lskb) { + lskb->mac_header = lskb->data; + lskb->protocol = htons(ETH_P_IRDA); + netif_rx(lskb); + } +} + +/*! + * Receiver DMA callback routine. + * + * @param id pointer to network device structure + * @param error_status used to pass error status to this callback function + * @param count number of bytes received + */ +static void mxc_irda_fir_dma_rx_irq(void *id, int error_status, + unsigned int count) +{ + struct net_device *dev = id; + struct mxc_irda *si = netdev_priv(dev); + struct sk_buff *skb = si->rxskb; + unsigned int cr; + unsigned int len; + + cr = readl(si->firi_base + FIRIRCR); + cr &= ~FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + cr = readl(si->firi_base + FIRIRCR); + cr |= FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + len = count - 4; /* remove 4 bytes for CRC */ + skb_put(skb, len); + skb->dev = dev; + si->tskb = skb; + tasklet_schedule(&dma_rx_tasklet); + + if (si->dma_rx_buff_phy != 0) + dma_unmap_single(si->dev, si->dma_rx_buff_phy, + IRDA_FRAME_SIZE_LIMIT, DMA_FROM_DEVICE); + + si->rxskb = NULL; + mxc_irda_rx_alloc(si); + + SDMA_START_DELAY(); + writel(0xFFFF, si->firi_base + FIRIRSR); + + if (si->rxskb) { + mxc_dma_enable(si->rxdma_ch); + } +} +#endif + +#ifdef FIRI_SDMA_TX +/*! + * This function is called by SDMA Interrupt Service Routine to indicate + * requested DMA transfer is completed. + * + * @param id pointer to network device structure + * @param error_status used to pass error status to this callback function + * @param count number of bytes sent + */ +static void mxc_irda_fir_dma_tx_irq(void *id, int error_status, + unsigned int count) +{ + struct net_device *dev = id; + struct mxc_irda *si = netdev_priv(dev); + + mxc_dma_disable(si->txdma_ch); +} +#endif + +/*! + * This function is called by Linux IrDA network subsystem to + * transmit the Infrared data packet. The TX DMA channel is configured + * to transfer SK buffer data to FIRI TX FIFO along with DMA transfer + * completion routine. + * + * @param skb The packet that is queued to be sent + * @param dev net_device structure. + * + * @return The function returns 0 on success and a negative value on + * failure. + */ +static int mxc_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct mxc_irda *si = netdev_priv(dev); + int speed = irda_get_next_speed(skb); + unsigned int cr; + + /* + * Does this packet contain a request to change the interface + * speed? If so, remember it until we complete the transmission + * of this frame. + */ + if (speed != si->speed && speed != -1) { + si->newspeed = speed; + } + + /* If this is an empty frame, we can bypass a lot. */ + if (skb->len == 0) { + if (si->newspeed) { + si->newspeed = 0; + mxc_irda_set_speed(si, speed); + } + dev_kfree_skb(skb); + return 0; + } + + /* We must not be transmitting... */ + netif_stop_queue(dev); + if (IS_SIR(si)) { + + si->tx_buff.data = si->tx_buff.head; + si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, + si->tx_buff.truesize); + cr = readl(si->uart_base + MXC_UARTUCR1); + cr |= MXC_UARTUCR1_TRDYEN; + writel(cr, si->uart_base + MXC_UARTUCR1); + dev_kfree_skb(skb); + } else { + unsigned int mtt = irda_get_mtt(skb); + unsigned char *p = skb->data; + unsigned int skb_len = skb->len; +#ifdef FIRI_SDMA_TX + mxc_dma_requestbuf_t dma_request; +#else + unsigned int i, sr; +#endif + + skb_len = skb_len + ((4 - (skb_len % 4)) % 4); + + if (si->txskb) { + BUG(); + } + si->txskb = skb; + + /* + * If we have a mean turn-around time, impose the specified + * specified delay. We could shorten this by timing from + * the point we received the packet. + */ + if (mtt) { + udelay(mtt); + } + + cr = readl(si->firi_base + FIRIRCR); + cr &= ~FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + + writel(skb->len - 1, si->firi_base + FIRITCTR); + +#ifdef FIRI_SDMA_TX + /* + * Configure DMA Tx Channel for source and destination addresses, + * Number of bytes in SK buffer to transfer and Transfer complete + * callback function. + */ + si->dma_tx_buff_len = skb_len; + si->dma_tx_buff_phy = + dma_map_single(si->dev, p, skb_len, DMA_TO_DEVICE); + + dma_request.num_of_bytes = skb_len; + dma_request.dst_addr = si->firi_res->start + FIRITXFIFO; + dma_request.src_addr = si->dma_tx_buff_phy; + + mxc_dma_config(si->txdma_ch, &dma_request, 1, + MXC_DMA_MODE_WRITE); + + mxc_dma_enable(si->txdma_ch); +#endif + cr = readl(si->firi_base + FIRITCR); + cr |= FIRITCR_TCIE; + writel(cr, si->firi_base + FIRITCR); + + cr |= FIRITCR_TE; + writel(cr, si->firi_base + FIRITCR); + +#ifndef FIRI_SDMA_TX + for (i = 0; i < skb->len;) { + sr = readl(si->firi_base + FIRITSR); + /* TFP = number of bytes in the TX FIFO for the + * Transmitter + * */ + if ((sr >> 8) < 128) { + writeb(*p, si->firi_base + FIRITXFIFO); + p++; + i++; + } + } +#endif + } + + dev->trans_start = jiffies; + return 0; +} + +/*! + * This function handles network interface ioctls passed to this driver.. + * + * @param dev net device structure + * @param ifreq user request data + * @param cmd command issued + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) +{ + struct if_irda_req *rq = (struct if_irda_req *)ifreq; + struct mxc_irda *si = netdev_priv(dev); + int ret = -EOPNOTSUPP; + + switch (cmd) { + /* This function will be used by IrLAP to change the speed */ + case SIOCSBANDWIDTH: + dev_dbg(si->dev, "%s:with cmd SIOCSBANDWIDTH\n", __FUNCTION__); + if (capable(CAP_NET_ADMIN)) { + /* + * We are unable to set the speed if the + * device is not running. + */ + if (si->open) { + ret = mxc_irda_set_speed(si, rq->ifr_baudrate); + } else { + dev_err(si->dev, "mxc_ir_ioctl: SIOCSBANDWIDTH:\ + !netif_running\n"); + ret = 0; + } + } + break; + case SIOCSMEDIABUSY: + dev_dbg(si->dev, "%s:with cmd SIOCSMEDIABUSY\n", __FUNCTION__); + ret = -EPERM; + if (capable(CAP_NET_ADMIN)) { + irda_device_set_media_busy(dev, TRUE); + ret = 0; + } + break; + case SIOCGRECEIVING: + rq->ifr_receiving = + IS_SIR(si) ? si->rx_buff.state != OUTSIDE_FRAME : 0; + ret = 0; + break; + default: + break; + } + return ret; +} + +/*! + * Kernel interface routine to get current statistics of the device + * which includes the number bytes/packets transmitted/received, + * receive errors, CRC errors, framing errors etc. + * + * @param dev the net_device structure + * + * @return This function returns IrDA network statistics + */ +static struct net_device_stats *mxc_irda_stats(struct net_device *dev) +{ + struct mxc_irda *si = netdev_priv(dev); + return &si->stats; +} + +/*! + * FIRI init function + * + * @param si FIRI device specific structure. + */ +void mxc_irda_firi_init(struct mxc_irda *si) +{ + unsigned int firi_baud, osf = 6; + unsigned int tcr, rcr, cr; + + si->firi_clk = clk_get(si->dev, "firi_clk"); + firi_baud = clk_round_rate(si->firi_clk, 48004500); + if ((firi_baud < 47995500) || + (clk_set_rate(si->firi_clk, firi_baud) < 0)) { + dev_err(si->dev, "Unable to set FIR clock to 48MHz.\n"); + return; + } + clk_enable(si->firi_clk); + + writel(0xFFFF, si->firi_base + FIRITSR); + writel(0xFFFF, si->firi_base + FIRIRSR); + writel(0x00, si->firi_base + FIRITCR); + writel(0x00, si->firi_base + FIRIRCR); + + /* set _BL & _OSF */ + cr = (osf - 1) | (16 << 5); + writel(cr, si->firi_base + FIRICR); + +#ifdef FIRI_SDMA_TX + tcr = + FIRITCR_TDT_FIR | FIRITCR_TM_FIR | FIRITCR_TCIE | + FIRITCR_PCF | FIRITCR_PC; +#else + tcr = FIRITCR_TM_FIR | FIRITCR_TCIE | FIRITCR_PCF | FIRITCR_PC; +#endif + +#ifdef FIRI_SDMA_RX + rcr = + FIRIRCR_RPEDE | FIRIRCR_RM_FIR | FIRIRCR_RDT_FIR | + FIRIRCR_RPA | FIRIRCR_RPP; +#else + rcr = + FIRIRCR_RPEDE | FIRIRCR_RM_FIR | FIRIRCR_RDT_FIR | FIRIRCR_RPEIE | + FIRIRCR_RPA | FIRIRCR_PAIE | FIRIRCR_RFOIE | FIRIRCR_RPP; +#endif + + writel(tcr, si->firi_base + FIRITCR); + writel(rcr, si->firi_base + FIRIRCR); + cr = 0; + writel(cr, si->firi_base + FIRITCTR); +} + +/*! + * This function initialises the UART. + * + * @param si FIRI port specific structure. + * + * @return The function returns 0 on success. + */ +static int mxc_irda_uart_init(struct mxc_irda *si) +{ + unsigned int per_clk; + unsigned int num, denom, baud, ufcr = 0; + unsigned int cr; + int d = 1; + int uart_ir_mux = 0; + + if (si->mxc_ir_plat) + uart_ir_mux = si->mxc_ir_plat->uart_ir_mux; + /* + * Clear Status Registers 1 and 2 + **/ + writel(0xFFFF, si->uart_base + MXC_UARTUSR1); + writel(0xFFFF, si->uart_base + MXC_UARTUSR2); + + /* Configure the IOMUX for the UART */ + gpio_firi_init(); + + per_clk = clk_get_rate(si->uart_clk); + baud = per_clk / 16; + if (baud > 1500000) { + baud = 1500000; + d = per_clk / ((baud * 16) + 1000); + if (d > 6) { + d = 6; + } + } + clk_enable(si->uart_clk); + + si->uart_clk_rate = per_clk / d; + writel(si->uart_clk_rate / 1000, si->uart_base + MXC_UARTONEMS); + + writel(si->mxc_ir_plat->ir_rx_invert | MXC_UARTUCR4_IRSC, + si->uart_base + MXC_UARTUCR4); + + if (uart_ir_mux) { + writel(MXC_UARTUCR3_RXDMUXSEL | si->mxc_ir_plat->ir_tx_invert | + MXC_UARTUCR3_DSR, si->uart_base + MXC_UARTUCR3); + } else { + writel(si->mxc_ir_plat->ir_tx_invert | MXC_UARTUCR3_DSR, + si->uart_base + MXC_UARTUCR3); + } + + writel(MXC_UARTUCR2_IRTS | MXC_UARTUCR2_CTS | MXC_UARTUCR2_WS | + MXC_UARTUCR2_ATEN | MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN, + si->uart_base + MXC_UARTUCR2); + /* Wait till we are out of software reset */ + do { + cr = readl(si->uart_base + MXC_UARTUCR2); + } while (!(cr & MXC_UARTUCR2_SRST)); + + ufcr |= (UART4_UFCR_TXTL << MXC_UARTUFCR_TXTL_OFFSET) | + ((6 - d) << MXC_UARTUFCR_RFDIV_OFFSET) | UART4_UFCR_RXTL; + writel(ufcr, si->uart_base + MXC_UARTUFCR); + + writel(MXC_UARTUCR1_UARTEN | MXC_UARTUCR1_IREN, + si->uart_base + MXC_UARTUCR1); + + baud = 9600; + num = baud / 100 - 1; + denom = si->uart_clk_rate / 1600 - 1; + + if ((denom < 65536) && (si->uart_clk_rate > 1600)) { + writel(num, si->uart_base + MXC_UARTUBIR); + writel(denom, si->uart_base + MXC_UARTUBMR); + } + + writel(0x0000, si->uart_base + MXC_UARTUTS); + return 0; + +} + +/*! + * This function enables FIRI port. + * + * @param si FIRI port specific structure. + * + * @return The function returns 0 on success and a non-zero value on + * failure. + */ +static int mxc_irda_startup(struct mxc_irda *si) +{ + int ret = 0; + + mxc_irda_uart_init(si); + mxc_irda_firi_init(si); + + /* configure FIRI device for speed */ + ret = mxc_irda_set_speed(si, si->speed = 9600); + + return ret; +} + +/*! + * When an ifconfig is issued which changes the device flag to include + * IFF_UP this function is called. It is only called when the change + * occurs, not when the interface remains up. The function grabs the interrupt + * resources and registers FIRI interrupt service routines, requests for DMA + * channels, configures the DMA channel. It then initializes the IOMUX + * registers to configure the pins for FIRI signals and finally initializes the + * various FIRI registers and enables the port for reception. + * + * @param dev net device structure that is being opened + * + * @return The function returns 0 for a successful open and non-zero value + * on failure. + */ +static int mxc_irda_start(struct net_device *dev) +{ + struct mxc_irda *si = netdev_priv(dev); + int err; + int ints_muxed = 0; + mxc_dma_device_t dev_id = 0; + + if (si->uart_irq == si->uart_irq1) + ints_muxed = 1; + + si->speed = 9600; + + if (si->uart_irq == si->firi_irq) { + err = + request_irq(si->uart_irq, mxc_irda_irq, 0, dev->name, dev); + if (err) { + dev_err(si->dev, "%s:Failed to request the IRQ\n", + __FUNCTION__); + return err; + } + /* + * The interrupt must remain disabled for now. + */ + disable_irq(si->uart_irq); + } else { + err = + request_irq(si->firi_irq, mxc_irda_irq, 0, dev->name, dev); + if (err) { + dev_err(si->dev, "%s:Failed to request FIRI IRQ\n", + __FUNCTION__); + return err; + } + /* + * The interrupt must remain disabled for now. + */ + disable_irq(si->firi_irq); + if (ints_muxed) { + + err = request_irq(si->uart_irq, mxc_irda_irq, 0, + dev->name, dev); + if (err) { + dev_err(si->dev, + "%s:Failed to request UART IRQ\n", + __FUNCTION__); + goto err_irq1; + } + /* + * The interrupt must remain disabled for now. + */ + disable_irq(si->uart_irq); + } else { + err = request_irq(si->uart_irq, mxc_irda_tx_irq, 0, + dev->name, dev); + if (err) { + dev_err(si->dev, + "%s:Failed to request UART IRQ\n", + __FUNCTION__); + goto err_irq1; + } + err = request_irq(si->uart_irq1, mxc_irda_rx_irq, 0, + dev->name, dev); + if (err) { + dev_err(si->dev, + "%s:Failed to request UART1 IRQ\n", + __FUNCTION__); + goto err_irq2; + } + /* + * The interrupts must remain disabled for now. + */ + disable_irq(si->uart_irq); + disable_irq(si->uart_irq1); + } + } +#ifdef FIRI_SDMA_RX + dev_id = MXC_DMA_FIR_RX; + si->rxdma_ch = mxc_dma_request(dev_id, "MXC FIRI RX"); + if (si->rxdma_ch < 0) { + dev_err(si->dev, "Cannot allocate FIR DMA channel\n"); + goto err_rx_dma; + } + mxc_dma_callback_set(si->rxdma_ch, mxc_irda_fir_dma_rx_irq, + (void *)dev_get_drvdata(si->dev)); +#endif +#ifdef FIRI_SDMA_TX + + dev_id = MXC_DMA_FIR_TX; + si->txdma_ch = mxc_dma_request(dev_id, "MXC FIRI TX"); + if (si->txdma_ch < 0) { + dev_err(si->dev, "Cannot allocate FIR DMA channel\n"); + goto err_tx_dma; + } + mxc_dma_callback_set(si->txdma_ch, mxc_irda_fir_dma_tx_irq, + (void *)dev_get_drvdata(si->dev)); +#endif + /* Setup the serial port port for the initial speed. */ + err = mxc_irda_startup(si); + if (err) { + goto err_startup; + } + + /* Open a new IrLAP layer instance. */ + si->irlap = irlap_open(dev, &si->qos, "mxc"); + err = -ENOMEM; + if (!si->irlap) { + goto err_irlap; + } + + /* Now enable the interrupt and start the queue */ + si->open = 1; + si->suspend = 0; + + if (si->uart_irq == si->firi_irq) { + enable_irq(si->uart_irq); + } else { + enable_irq(si->firi_irq); + if (ints_muxed == 1) { + enable_irq(si->uart_irq); + } else { + enable_irq(si->uart_irq); + enable_irq(si->uart_irq1); + } + } + + netif_start_queue(dev); + return 0; + + err_irlap: + si->open = 0; + mxc_irda_disabledma(si); + err_startup: +#ifdef FIRI_SDMA_TX + mxc_dma_free(si->txdma_ch); + err_tx_dma: +#endif +#ifdef FIRI_SDMA_RX + mxc_dma_free(si->rxdma_ch); + err_rx_dma: +#endif + if (si->uart_irq1 && !ints_muxed) + free_irq(si->uart_irq1, dev); + err_irq2: + if (si->uart_irq != si->firi_irq) + free_irq(si->uart_irq, dev); + err_irq1: + if (si->firi_irq) + free_irq(si->firi_irq, dev); + return err; +} + +/*! + * This function is called when IFF_UP flag has been cleared by the user via + * the ifconfig irda0 down command. This function stops any further + * transmissions being queued, and then disables the interrupts. + * Finally it resets the device. + * @param dev the net_device structure + * + * @return int the function always returns 0 indicating a success. + */ +static int mxc_irda_stop(struct net_device *dev) +{ + struct mxc_irda *si = netdev_priv(dev); + unsigned long flags; + + /* Stop IrLAP */ + if (si->irlap) { + irlap_close(si->irlap); + si->irlap = NULL; + } + + netif_stop_queue(dev); + + /*Save flags and disable the FIRI interrupts.. */ + if (si->open) { + local_irq_save(flags); + disable_irq(si->uart_irq); + free_irq(si->uart_irq, dev); + if (si->uart_irq != si->firi_irq) { + disable_irq(si->firi_irq); + free_irq(si->firi_irq, dev); + if (si->uart_irq1 != si->uart_irq) { + disable_irq(si->uart_irq1); + free_irq(si->uart_irq1, dev); + } + } + local_irq_restore(flags); + si->open = 0; + } +#ifdef FIRI_SDMA_RX + if (si->rxdma_ch) { + mxc_dma_disable(si->rxdma_ch); + mxc_dma_free(si->rxdma_ch); + if (si->dma_rx_buff_phy) { + dma_unmap_single(si->dev, si->dma_rx_buff_phy, + IRDA_FRAME_SIZE_LIMIT, + DMA_FROM_DEVICE); + si->dma_rx_buff_phy = 0; + } + si->rxdma_ch = 0; + } + tasklet_kill(&dma_rx_tasklet); +#endif +#ifdef FIRI_SDMA_TX + if (si->txdma_ch) { + mxc_dma_disable(si->txdma_ch); + mxc_dma_free(si->txdma_ch); + if (si->dma_tx_buff_phy) { + dma_unmap_single(si->dev, si->dma_tx_buff_phy, + si->dma_tx_buff_len, DMA_TO_DEVICE); + si->dma_tx_buff_phy = 0; + } + si->txdma_ch = 0; + } +#endif + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function is called to put the FIRI in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which FIRI + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_irda_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct mxc_irda *si = netdev_priv(ndev); + unsigned int cr; + unsigned long flags; + + if (!si) { + return 0; + } + if (si->suspend == 1) { + dev_err(si->dev, + " suspend - Device is already suspended ... \n"); + return 0; + } + if (si->open) { + + netif_device_detach(ndev); + mxc_irda_disabledma(si); + + /*Save flags and disable the FIRI interrupts.. */ + local_irq_save(flags); + disable_irq(si->uart_irq); + if (si->uart_irq != si->firi_irq) { + disable_irq(si->firi_irq); + if (si->uart_irq != si->uart_irq1) { + disable_irq(si->uart_irq1); + } + } + local_irq_restore(flags); + + /* Disable Tx and Rx and then disable the UART clock */ + cr = readl(si->uart_base + MXC_UARTUCR2); + cr &= ~(MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN); + writel(cr, si->uart_base + MXC_UARTUCR2); + cr = readl(si->uart_base + MXC_UARTUCR1); + cr &= ~MXC_UARTUCR1_UARTEN; + writel(cr, si->uart_base + MXC_UARTUCR1); + clk_disable(si->uart_clk); + + /*Disable Tx and Rx for FIRI and then disable the FIRI clock.. */ + cr = readl(si->firi_base + FIRITCR); + cr &= ~FIRITCR_TE; + writel(cr, si->firi_base + FIRITCR); + cr = readl(si->firi_base + FIRIRCR); + cr &= ~FIRIRCR_RE; + writel(cr, si->firi_base + FIRIRCR); + clk_disable(si->firi_clk); + + gpio_firi_inactive(); + + si->suspend = 1; + si->open = 0; + } + return 0; +} + +/*! + * This function is called to bring the FIRI back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which FIRI + * to resume + * + * @return The function always returns 0. + */ +static int mxc_irda_resume(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct mxc_irda *si = netdev_priv(ndev); + unsigned long flags; + + if (!si) { + return 0; + } + + if (si->suspend == 1 && !si->open) { + + /*Initialise the UART first */ + clk_enable(si->uart_clk); + + /*Now init FIRI */ + gpio_firi_active(si->firi_base + FIRITCR, FIRITCR_TPP); + mxc_irda_startup(si); + + /* Enable the UART and FIRI interrupts.. */ + local_irq_save(flags); + enable_irq(si->uart_irq); + if (si->uart_irq != si->firi_irq) { + enable_irq(si->firi_irq); + if (si->uart_irq != si->uart_irq1) { + enable_irq(si->uart_irq1); + } + } + local_irq_restore(flags); + + /* Let the kernel know that we are alive and kicking.. */ + netif_device_attach(ndev); + + si->suspend = 0; + si->open = 1; + } + return 0; +} +#else +#define mxc_irda_suspend NULL +#define mxc_irda_resume NULL +#endif + +static int mxc_irda_init_iobuf(iobuff_t *io, int size) +{ + io->head = kmalloc(size, GFP_KERNEL | GFP_DMA); + if (io->head != NULL) { + io->truesize = size; + io->in_frame = FALSE; + io->state = OUTSIDE_FRAME; + io->data = io->head; + } + return io->head ? 0 : -ENOMEM; + +} + +static struct net_device_ops mxc_irda_ops = { + .ndo_start_xmit = mxc_irda_hard_xmit, + .ndo_open = mxc_irda_start, + .ndo_stop = mxc_irda_stop, + .ndo_do_ioctl = mxc_irda_ioctl, + .ndo_get_stats = mxc_irda_stats, +}; + +/*! + * This function is called during the driver binding process. + * This function requests for memory, initializes net_device structure and + * registers with kernel. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function returns 0 on success and a non-zero value on failure + */ +static int mxc_irda_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct mxc_irda *si; + struct resource *uart_res, *firi_res; + int uart_irq, firi_irq, uart_irq1; + unsigned int baudrate_mask = 0; + int err; + + uart_res = &pdev->resource[0]; + uart_irq = pdev->resource[1].start; + + firi_res = &pdev->resource[2]; + firi_irq = pdev->resource[3].start; + + uart_irq1 = pdev->resource[4].start; + + if (!uart_res || uart_irq == NO_IRQ || !firi_res || firi_irq == NO_IRQ) { + dev_err(&pdev->dev, "Unable to find resources\n"); + return -ENXIO; + } + + err = + request_mem_region(uart_res->start, SZ_16K, + "MXC_IRDA") ? 0 : -EBUSY; + if (err) { + dev_err(&pdev->dev, "Failed to request UART memory region\n"); + return -ENOMEM; + } + + err = + request_mem_region(firi_res->start, SZ_16K, + "MXC_IRDA") ? 0 : -EBUSY; + if (err) { + dev_err(&pdev->dev, "Failed to request FIRI memory region\n"); + goto err_mem_1; + } + + dev = alloc_irdadev(sizeof(struct mxc_irda)); + if (!dev) { + goto err_mem_2; + } + + si = netdev_priv(dev); + si->dev = &pdev->dev; + + si->mxc_ir_plat = pdev->dev.platform_data; + si->uart_clk = si->mxc_ir_plat->uart_clk; + + si->uart_res = uart_res; + si->firi_res = firi_res; + si->uart_irq = uart_irq; + si->firi_irq = firi_irq; + si->uart_irq1 = uart_irq1; + + si->uart_base = ioremap(uart_res->start, SZ_16K); + si->firi_base = ioremap(firi_res->start, SZ_16K); + + if (!(si->uart_base || si->firi_base)) { + err = -ENOMEM; + goto err_mem_3; + } + + /* + * Initialise the SIR buffers + */ + err = mxc_irda_init_iobuf(&si->rx_buff, UART_BUFF_SIZE); + if (err) { + goto err_mem_4; + } + + err = mxc_irda_init_iobuf(&si->tx_buff, UART_BUFF_SIZE); + if (err) { + goto err_mem_5; + } + + dev->netdev_ops = &mxc_irda_ops; + + irda_init_max_qos_capabilies(&si->qos); + + /* + * We support + * SIR(9600, 19200,38400, 57600 and 115200 bps) + * FIR(4 Mbps) + * Min Turn Time set to 1ms or greater. + */ + baudrate_mask |= IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200; + baudrate_mask |= IR_4000000 << 8; + + si->qos.baud_rate.bits &= baudrate_mask; + si->qos.min_turn_time.bits = 0x7; + + irda_qos_bits_to_value(&si->qos); + +#ifdef FIRI_SDMA_RX + si->tskb = NULL; + tasklet_init(&dma_rx_tasklet, mxc_irda_rx_task, (unsigned long)si); +#endif + err = register_netdev(dev); + if (err == 0) { + platform_set_drvdata(pdev, dev); + } else { + kfree(si->tx_buff.head); + err_mem_5: + kfree(si->rx_buff.head); + err_mem_4: + iounmap(si->uart_base); + iounmap(si->firi_base); + err_mem_3: + free_netdev(dev); + err_mem_2: + release_mem_region(firi_res->start, SZ_16K); + err_mem_1: + release_mem_region(uart_res->start, SZ_16K); + } + return err; +} + +/*! + * Dissociates the driver from the FIRI device. Removes the appropriate FIRI + * port structure from the kernel. + * + * @param pdev the device structure used to give information on which FIRI + * to remove + * + * @return The function always returns 0. + */ +static int mxc_irda_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct mxc_irda *si = netdev_priv(dev); + + if (si->uart_base) + iounmap(si->uart_base); + if (si->firi_base) + iounmap(si->firi_base); + if (si->firi_res->start) + release_mem_region(si->firi_res->start, SZ_16K); + if (si->uart_res->start) + release_mem_region(si->uart_res->start, SZ_16K); + if (si->tx_buff.head) + kfree(si->tx_buff.head); + if (si->rx_buff.head) + kfree(si->rx_buff.head); + + platform_set_drvdata(pdev, NULL); + unregister_netdev(dev); + free_netdev(dev); + + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcir_driver = { + .driver = { + .name = "mxcir", + }, + .probe = mxc_irda_probe, + .remove = mxc_irda_remove, + .suspend = mxc_irda_suspend, + .resume = mxc_irda_resume, +}; + +/*! + * This function is used to initialize the FIRI driver module. The function + * registers the power management callback functions with the kernel and also + * registers the FIRI callback functions. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxc_irda_init(void) +{ + return platform_driver_register(&mxcir_driver); +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxc_irda_exit(void) +{ + platform_driver_unregister(&mxcir_driver); +} + +module_init(mxc_irda_init); +module_exit(mxc_irda_exit); + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("MXC IrDA(SIR/FIR) driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/irda/mxc_ir.h b/drivers/net/irda/mxc_ir.h new file mode 100644 index 000000000000..601731029024 --- /dev/null +++ b/drivers/net/irda/mxc_ir.h @@ -0,0 +1,131 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MXC_FIRI_REG_H__ +#define __MXC_FIRI_REG_H__ + +/*! + * @defgroup FIRI Fast IR Driver + */ + +/*! + * @file mxc_ir.h + * + * @brief MXC FIRI header file + * + * This file defines base address and bits of FIRI registers + * + * @ingroup FIRI + */ + +/*! + * FIRI maximum packet length + */ +#define FIR_MAX_RXLEN 2047 + +/* + * FIRI Transmitter Control Register + */ +#define FIRITCR 0x00 +/* + * FIRI Transmitter Count Register + */ +#define FIRITCTR 0x04 +/* + * FIRI Receiver Control Register + */ +#define FIRIRCR 0x08 +/* + * FIRI Transmitter Status Register + */ +#define FIRITSR 0x0C +/* + * FIRI Receiver Status Register + */ +#define FIRIRSR 0x10 +/* + * FIRI Transmitter FIFO + */ +#define FIRITXFIFO 0x14 +/* + * FIRI Receiver FIFO + */ +#define FIRIRXFIFO 0x18 +/* + * FIRI Control Register + */ +#define FIRICR 0x1C + +/* + * Bit definitions of Transmitter Controller Register + */ +#define FIRITCR_HAG (1<<24) /* H/W address generator */ +#define FIRITCR_SRF_FIR (0<<13) /* Start field repeat factor */ +#define FIRITCR_SRF_MIR (1<<13) /* Start field Repeat Factor */ +#define FIRITCR_TDT_MIR (2<<10) /* TX trigger for MIR is set to 32 bytes) */ +#define FIRITCR_TDT_FIR (1<<10) /* TX trigger for FIR is set to 16 bytes) */ +#define FIRITCR_TCIE (1<<9) /* TX Complete Interrupt Enable */ +#define FIRITCR_TPEIE (1<<8) /* TX Packet End Interrupt Enable */ +#define FIRITCR_TFUIE (1<<7) /* TX FIFO Under-run Interrupt Enable */ +#define FIRITCR_PCF (1<<6) /* Packet Complete by FIFO */ +#define FIRITCR_PC (1<<5) /* Packet Complete */ +#define FIRITCR_SIP (1<<4) /* TX Enable of SIP */ +#define FIRITCR_TPP (1<<3) /* TX Pulse Polarity bit */ +#define FIRITCR_TM_FIR (0<<1) /* TX Mode 4 Mbps */ +#define FIRITCR_TM_MIR1 (1<<1) /* TX Mode 0.576 Mbps */ +#define FIRITCR_TM_MIR2 (1<<2) /* TX Mode 1.152 Mbps */ +#define FIRITCR_TE (1<<0) /* TX Enable */ + +/* + * Bit definitions of Transmitter Count Register + */ +#define FIRITCTR_TPL 511 /* TX Packet Length set to 512 bytes */ + +/* + * Bit definitions of Receiver Control Register + */ +#define FIRIRCR_RAM (1<<24) /* RX Address Match */ +#define FIRIRCR_RPEDE (1<<11) /* Packet End DMA request Enable */ +#define FIRIRCR_RDT_MIR (2<<8) /* DMA Trigger level(64 bytes in RXFIFO) */ +#define FIRIRCR_RDT_FIR (1<<8) /* DMA Trigger level(16 bytes in RXFIFO) */ +#define FIRIRCR_RPA (1<<7) /* RX Packet Abort */ +#define FIRIRCR_RPEIE (1<<6) /* RX Packet End Interrupt Enable */ +#define FIRIRCR_PAIE (1<<5) /* Packet Abort Interrupt Enable */ +#define FIRIRCR_RFOIE (1<<4) /* RX FIFO Overrun Interrupt Enable */ +#define FIRIRCR_RPP (1<<3) /* RX Pulse Polarity bit */ +#define FIRIRCR_RM_FIR (0<<1) /* 4 Mbps */ +#define FIRIRCR_RM_MIR1 (1<<1) /* 0.576 Mbps */ +#define FIRIRCR_RM_MIR2 (1<<2) /* 1.152 Mbps */ +#define FIRIRCR_RE (1<<0) /* RX Enable */ + +/* Transmitter Status Register */ +#define FIRITSR_TFP 0xFF00 /* Mask for available bytes in TX FIFO */ +#define FIRITSR_TC (1<<3) /* Transmit Complete bit */ +#define FIRITSR_SIPE (1<<2) /* SIP End bit */ +#define FIRITSR_TPE (1<<1) /* Transmit Packet End */ +#define FIRITSR_TFU (1<<0) /* TX FIFO Under-run */ + +/* Receiver Status Register */ +#define FIRIRSR_RFP 0xFF00 /* mask for available bytes RX FIFO */ +#define FIRIRSR_PAS (1<<5) /* preamble search */ +#define FIRIRSR_RPE (1<<4) /* RX Packet End */ +#define FIRIRSR_RFO (1<<3) /* RX FIFO Overrun */ +#define FIRIRSR_BAM (1<<2) /* Broadcast Address Match */ +#define FIRIRSR_CRCE (1<<1) /* CRC error */ +#define FIRIRSR_DDE (1<<0) /* Address, control or data field error */ + +/* FIRI Control Register */ +#define FIRICR_BL (32<<5) /* Burst Length is set to 32 */ +#define FIRICR_OSF (0<<1) /* Over Sampling Factor */ + +#endif /* __MXC_FIRI_REG_H__ */ diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 40797fbdca9f..ff2f158ab0b9 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -1082,7 +1082,7 @@ static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (!phydev) return -ENODEV; - return phy_mii_ioctl(phydev, if_mii(rq), cmd); + return phy_mii_ioctl(phydev, rq, cmd); } static const struct net_device_ops macb_netdev_ops = { diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 73bb8ea6f54a..537ffb0283e7 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c @@ -2456,7 +2456,7 @@ static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) struct mv643xx_eth_private *mp = netdev_priv(dev); if (mp->phy != NULL) - return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd); + return phy_mii_ioctl(mp->phy, ifr, cmd); return -EOPNOTSUPP; } diff --git a/drivers/net/octeon/octeon_mgmt.c b/drivers/net/octeon/octeon_mgmt.c index 000e792d57c0..73a267167dfc 100644 --- a/drivers/net/octeon/octeon_mgmt.c +++ b/drivers/net/octeon/octeon_mgmt.c @@ -620,7 +620,7 @@ static int octeon_mgmt_ioctl(struct net_device *netdev, if (!p->phydev) return -EINVAL; - return phy_mii_ioctl(p->phydev, if_mii(rq), cmd); + return phy_mii_ioctl(p->phydev, rq, cmd); } static void octeon_mgmt_adjust_link(struct net_device *netdev) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 64be4664ccab..bd88d818f082 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -309,8 +309,9 @@ EXPORT_SYMBOL(phy_ethtool_gset); * current state. Use at own risk. */ int phy_mii_ioctl(struct phy_device *phydev, - struct mii_ioctl_data *mii_data, int cmd) + struct ifreq *ifr, int cmd) { + struct mii_ioctl_data *mii_data = if_mii(ifr); u16 val = mii_data->val_in; switch (cmd) { diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c index 79eee3062083..8e6bd45b9f31 100644 --- a/drivers/net/sb1250-mac.c +++ b/drivers/net/sb1250-mac.c @@ -2532,7 +2532,7 @@ static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (!netif_running(dev) || !sc->phy_dev) return -EINVAL; - return phy_mii_ioctl(sc->phy_dev, if_mii(rq), cmd); + return phy_mii_ioctl(sc->phy_dev, rq, cmd); } static int sbmac_close(struct net_device *dev) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 501a55ffce57..8279f8e9459b 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -1233,7 +1233,7 @@ static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, if (!phydev) return -ENODEV; - return phy_mii_ioctl(phydev, if_mii(rq), cmd); + return phy_mii_ioctl(phydev, rq, cmd); } #if defined(SH_ETH_HAS_TSU) diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c index 7a7b01a0fff8..c09d5ddee238 100644 --- a/drivers/net/smsc911x.c +++ b/drivers/net/smsc911x.c @@ -1550,7 +1550,7 @@ static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) if (!netif_running(dev) || !pdata->phy_dev) return -EINVAL; - return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd); + return phy_mii_ioctl(pdata->phy_dev, ifr, cmd); } static int @@ -2120,6 +2120,9 @@ static int smsc911x_suspend(struct device *dev) { struct net_device *ndev = dev_get_drvdata(dev); struct smsc911x_data *pdata = netdev_priv(ndev); + struct phy_device *phy_dev = pdata->phy_dev; + + smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_PDOWN); /* enable wake on LAN, energy detection and the external PME * signal. */ @@ -2134,6 +2137,7 @@ static int smsc911x_resume(struct device *dev) { struct net_device *ndev = dev_get_drvdata(dev); struct smsc911x_data *pdata = netdev_priv(ndev); + struct phy_device *phy_dev = pdata->phy_dev; unsigned int to = 100; /* Note 3.11 from the datasheet: @@ -2148,6 +2152,8 @@ static int smsc911x_resume(struct device *dev) while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) udelay(1000); + smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); + return (to == 0) ? -EIO : 0; } diff --git a/drivers/net/smsc9420.c b/drivers/net/smsc9420.c index 6cdee6a15f9f..b09ee1c319e8 100644 --- a/drivers/net/smsc9420.c +++ b/drivers/net/smsc9420.c @@ -245,7 +245,7 @@ static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) if (!netif_running(dev) || !pd->phy_dev) return -EINVAL; - return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd); + return phy_mii_ioctl(pd->phy_dev, ifr, cmd); } static int smsc9420_ethtool_get_settings(struct net_device *dev, diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c index a31d580f306d..acf061686940 100644 --- a/drivers/net/stmmac/stmmac_main.c +++ b/drivers/net/stmmac/stmmac_main.c @@ -1437,24 +1437,18 @@ static void stmmac_poll_controller(struct net_device *dev) static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) { struct stmmac_priv *priv = netdev_priv(dev); - int ret = -EOPNOTSUPP; + int ret; if (!netif_running(dev)) return -EINVAL; - switch (cmd) { - case SIOCGMIIPHY: - case SIOCGMIIREG: - case SIOCSMIIREG: - if (!priv->phydev) - return -EINVAL; - - spin_lock(&priv->lock); - ret = phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); - spin_unlock(&priv->lock); - default: - break; - } + if (!priv->phydev) + return -EINVAL; + + spin_lock(&priv->lock); + ret = phy_mii_ioctl(priv->phydev, rq, cmd); + spin_unlock(&priv->lock); + return ret; } diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c index be08b75dbc15..99e423a5b9f1 100644 --- a/drivers/net/tc35815.c +++ b/drivers/net/tc35815.c @@ -2066,7 +2066,7 @@ static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) return -EINVAL; if (!lp->phy_dev) return -ENODEV; - return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd); + return phy_mii_ioctl(lp->phy_dev, rq, cmd); } static void tc35815_chip_reset(struct net_device *dev) diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 573054ae7b58..b4d2d970af11 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -10914,7 +10914,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) return -EAGAIN; phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; - return phy_mii_ioctl(phydev, data, cmd); + return phy_mii_ioctl(phydev, ifr, cmd); } switch (cmd) { diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index 807470e156af..75ddca34f823 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c @@ -3704,6 +3704,19 @@ static phy_interface_t to_phy_interface(const char *phy_connection_type) return PHY_INTERFACE_MODE_MII; } +static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct ucc_geth_private *ugeth = netdev_priv(dev); + + if (!netif_running(dev)) + return -EINVAL; + + if (!ugeth->phydev) + return -ENODEV; + + return phy_mii_ioctl(ugeth->phydev, rq, cmd); +} + static const struct net_device_ops ucc_geth_netdev_ops = { .ndo_open = ucc_geth_open, .ndo_stop = ucc_geth_close, diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig index 174e3442d519..0d5d168e4ec5 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig @@ -281,5 +281,6 @@ source "drivers/net/wireless/p54/Kconfig" source "drivers/net/wireless/rt2x00/Kconfig" source "drivers/net/wireless/wl12xx/Kconfig" source "drivers/net/wireless/zd1211rw/Kconfig" +source "drivers/net/wireless/ath6kl/Kconfig" endif # WLAN diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile index 5d4ce4d2b32b..bd74b0111d77 100644 --- a/drivers/net/wireless/Makefile +++ b/drivers/net/wireless/Makefile @@ -52,3 +52,5 @@ obj-$(CONFIG_MAC80211_HWSIM) += mac80211_hwsim.o obj-$(CONFIG_WL12XX) += wl12xx/ obj-$(CONFIG_IWM) += iwmc3200wifi/ + +obj-$(CONFIG_ATH6K_LEGACY) += ath6kl/ diff --git a/drivers/net/wireless/ath6kl/Kconfig b/drivers/net/wireless/ath6kl/Kconfig new file mode 100644 index 000000000000..fa4c2447f80e --- /dev/null +++ b/drivers/net/wireless/ath6kl/Kconfig @@ -0,0 +1,152 @@ +config ATH6K_LEGACY + tristate "Atheros AR600x support (non mac80211)" + depends on MMC + depends on WLAN + select WIRELESS_EXT + select WEXT_SPY + select WEXT_PRIV + help + This module adds support for wireless adapters based on Atheros AR600x chipset running over SDIO. If you choose to build it as a module, it will be called ath6kl. + +choice + prompt "AR600x Board Data Configuration" + depends on ATH6K_LEGACY + default AR600x_SD31_XXX + help + Select the appropriate board data template from the list below that matches your AR600x based reference design. + +config AR600x_SD31_XXX + bool "SD31-xxx" + help + Board Data file for a standard SD31 reference design (File: bdata.SD31.bin) + +config AR600x_WB31_XXX + bool "WB31-xxx" + help + Board Data file for a standard WB31 (BT/WiFi) reference design (File: bdata.WB31.bin) + +config AR600x_SD32_XXX + bool "SD32-xxx" + help + Board Data file for a standard SD32 (5GHz) reference design (File: bdata.SD32.bin) + +config AR600x_CUSTOM_XXX + bool "CUSTOM-xxx" + help + Board Data file for a custom reference design (File: should be named as bdata.CUSTOM.bin) +endchoice + +config ATH6KL_ENABLE_COEXISTENCE + bool "BT Coexistence support" + depends on ATH6K_LEGACY + help + Enables WLAN/BT coexistence support. Select the apprpriate configuration from below. + +choice + prompt "Front-End Antenna Configuration" + depends on ATH6KL_ENABLE_COEXISTENCE + default AR600x_DUAL_ANTENNA + help + Select the appropriate configuration from the list below that matches your AR600x based reference design. + +config AR600x_DUAL_ANTENNA + bool "Dual Antenna" + help + Dual Antenna Design + +config AR600x_SINGLE_ANTENNA + bool "Single Antenna" + help + Single Antenna Design +endchoice + +choice + prompt "Collocated Bluetooth Type" + depends on ATH6KL_ENABLE_COEXISTENCE + default AR600x_BT_AR3001 + help + Select the appropriate configuration from the list below that matches your AR600x based reference design. + +config AR600x_BT_QCOM + bool "Qualcomm BTS4020X" + help + Qualcomm BT (3 Wire PTA) + +config AR600x_BT_CSR + bool "CSR BC06" + help + CSR BT (3 Wire PTA) + +config AR600x_BT_AR3001 + bool "Atheros AR3001" + help + Atheros BT (3 Wire PTA) +endchoice + +config ATH6KL_HCI_BRIDGE + bool "HCI over SDIO support" + depends on ATH6K_LEGACY + help + Enables BT over SDIO. Applicable only for combo designs (eg: WB31) + +config ATH6KL_CONFIG_GPIO_BT_RESET + bool "Configure BT Reset GPIO" + depends on ATH6KL_HCI_BRIDGE + help + Configure a WLAN GPIO for use with BT. + +config AR600x_BT_RESET_PIN + int "GPIO" + depends on ATH6KL_CONFIG_GPIO_BT_RESET + default 22 + help + WLAN GPIO to be used for resetting BT + +config ATH6KL_CFG80211 + bool "CFG80211 support" + depends on ATH6K_LEGACY + help + Enables support for CFG80211 APIs + +config ATH6KL_HTC_RAW_INTERFACE + bool "RAW HTC support" + depends on ATH6K_LEGACY + help + Enables raw HTC interface. Allows application to directly talk to the HTC interface via the ioctl interface + +config ATH6KL_VIRTUAL_SCATTER_GATHER + bool "Virtual Scatter-Gather support" + depends on ATH6K_LEGACY + help + Enables virtual scatter gather support for the hardware that does not support it natively. + +config ATH6KL_DEBUG + bool "Debug support" + depends on ATH6K_LEGACY + help + Enables debug support + +config ATH6KL_ENABLE_HOST_DEBUG + bool "Host Debug support" + depends on ATH6KL_DEBUG + help + Enables debug support in the driver + +config ATH6KL_ENABLE_TARGET_DEBUG_PRINTS + bool "Target Debug support - Enable UART prints" + depends on ATH6KL_DEBUG + help + Enables uart prints + +config AR600x_DEBUG_UART_TX_PIN + int "GPIO" + depends on ATH6KL_ENABLE_TARGET_DEBUG_PRINTS + default 8 + help + WLAN GPIO to be used for Debug UART (Tx) + +config ATH6KL_DISABLE_TARGET_DBGLOGS + bool "Target Debug support - Disable Debug logs" + depends on ATH6KL_DEBUG + help + Enables debug logs diff --git a/drivers/net/wireless/ath6kl/Makefile b/drivers/net/wireless/ath6kl/Makefile new file mode 100644 index 000000000000..b839dc5c54c5 --- /dev/null +++ b/drivers/net/wireless/ath6kl/Makefile @@ -0,0 +1,138 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2005-2010 Atheros Corporation. All rights reserved. +# +# $ATH_LICENSE_HOSTSDK0_C$ +#------------------------------------------------------------------------------ +#============================================================================== +# Author(s): ="Atheros" +#============================================================================== + +ccflags-y += -I$(obj)/include +ccflags-y += -I$(obj)/wlan/include +ccflags-y += -I$(obj)/os/linux/include +ccflags-y += -I$(obj)/os +ccflags-y += -I$(obj)/bmi/include +ccflags-y += -I$(obj)/include/AR6002/hw4.0 + +ifeq ($(CONFIG_AR600x_SD31_XXX),y) +ccflags-y += -DAR600x_SD31_XXX +endif + +ifeq ($(CONFIG_AR600x_WB31_XXX),y) +ccflags-y += -DAR600x_WB31_XXX +endif + +ifeq ($(CONFIG_AR600x_SD32_XXX),y) +ccflags-y += -DAR600x_SD32_XXX +endif + +ifeq ($(CONFIG_AR600x_CUSTOM_XXX),y) +ccflags-y += -DAR600x_CUSTOM_XXX +endif + +ifeq ($(CONFIG_ATH6KL_ENABLE_COEXISTENCE),y) +ccflags-y += -DENABLE_COEXISTENCE +endif + +ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y) +ccflags-y += -DAR600x_DUAL_ANTENNA +endif + +ifeq ($(CONFIG_AR600x_SINGLE_ANTENNA),y) +ccflags-y += -DAR600x_SINGLE_ANTENNA +endif + +ifeq ($(CONFIG_AR600x_BT_QCOM),y) +ccflags-y += -DAR600x_BT_QCOM +endif + +ifeq ($(CONFIG_AR600x_BT_CSR),y) +ccflags-y += -DAR600x_BT_CSR +endif + +ifeq ($(CONFIG_AR600x_BT_AR3001),y) +ccflags-y += -DAR600x_BT_AR3001 +endif + +ifeq ($(CONFIG_ATH6KL_HCI_BRIDGE),y) +ccflags-y += -DATH_AR6K_ENABLE_GMBOX +ccflags-y += -DHCI_TRANSPORT_SDIO +ccflags-y += -DSETUPHCI_ENABLED +ccflags-y += -DSETUPBTDEV_ENABLED +ath6kl-y += htc2/AR6000/ar6k_gmbox.o +ath6kl-y += htc2/AR6000/ar6k_gmbox_hciuart.o +ath6kl-y += miscdrv/ar3kconfig.o +ath6kl-y += miscdrv/ar3kps/ar3kpsconfig.o +ath6kl-y += miscdrv/ar3kps/ar3kpsparser.o +endif + +ifeq ($(CONFIG_ATH6KL_CONFIG_GPIO_BT_RESET),y) +ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET +endif + +ifeq ($(CONFIG_ATH6KL_CFG80211),y) +ccflags-y += -DATH6K_CONFIG_CFG80211 +ath6kl-y += os/linux/cfg80211.o +endif + +ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y) +ccflags-y += -DHTC_RAW_INTERFACE +endif + +ifeq ($(CONFIG_ATH6KL_ENABLE_HOST_DEBUG),y) +ccflags-y += -DDEBUG +endif + +ifeq ($(CONFIG_ATH6KL_ENABLE_TARGET_DEBUG_PRINTS),y) +ccflags-y += -DENABLEUARTPRINT_SET +endif + +ifeq ($(CONFIG_ATH6KL_DISABLE_TARGET_DBGLOGS),y) +ccflags-y += -DATH6KL_DISABLE_TARGET_DBGLOGS +endif + +ifeq ($(CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER),y) +ccflags-y += -DATH6K_CONFIG_HIF_VIRTUAL_SCATTER +endif + +ccflags-y += -DLINUX -DKERNEL_2_6 +ccflags-y += -DTCMD +ccflags-y += -DSEND_EVENT_TO_APP +ccflags-y += -DUSER_KEYS +ccflags-y += -DNO_SYNC_FLUSH +ccflags-y += -DHTC_EP_STAT_PROFILING +ccflags-y += -DATH_AR6K_11N_SUPPORT +ccflags-y += -DWAPI_ENABLE +ccflags-y += -DCHECKSUM_OFFLOAD +ccflags-y += -DWLAN_HEADERS +ccflags-y += -DINIT_MODE_DRV_ENABLED +ccflags-y += -DBMIENABLE_SET + +obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o +ath6kl-y += htc2/AR6000/ar6k.o +ath6kl-y += htc2/AR6000/ar6k_events.o +ath6kl-y += htc2/htc_send.o +ath6kl-y += htc2/htc_recv.o +ath6kl-y += htc2/htc_services.o +ath6kl-y += htc2/htc.o +ath6kl-y += bmi/src/bmi.o +ath6kl-y += os/linux/ar6000_drv.o +ath6kl-y += os/linux/ar6000_raw_if.o +ath6kl-y += os/linux/netbuf.o +ath6kl-y += os/linux/wireless_ext.o +ath6kl-y += os/linux/ioctl.o +ath6kl-y += os/linux/hci_bridge.o +ath6kl-y += miscdrv/common_drv.o +ath6kl-y += miscdrv/credit_dist.o +ath6kl-y += wmi/wmi.o +ath6kl-y += reorder/rcv_aggr.o +ath6kl-y += wlan/src/wlan_node.o +ath6kl-y += wlan/src/wlan_recv_beacon.o +ath6kl-y += wlan/src/wlan_utils.o + +# ATH_HIF_TYPE := sdio +ccflags-y += -I$(obj)/hif/sdio/linux_sdio/include +ccflags-y += -DSDIO +ath6kl-y += hif/sdio/linux_sdio/src/hif.o +ath6kl-y += hif/sdio/linux_sdio/src/hif_scatter.o diff --git a/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h b/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h new file mode 100644 index 000000000000..729e3a6ac54d --- /dev/null +++ b/drivers/net/wireless/ath6kl/bmi/include/bmi_internal.h @@ -0,0 +1,51 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef BMI_INTERNAL_H +#define BMI_INTERNAL_H + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#define ATH_MODULE_NAME bmi +#include "a_debug.h" +#include "AR6002/hw2.0/hw/mbox_host_reg.h" +#include "bmi_msg.h" + +#define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0) + + +#define BMI_COMMUNICATION_TIMEOUT 100000 + +/* ------ Global Variable Declarations ------- */ +A_BOOL bmiDone; + +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout); + +#endif diff --git a/drivers/net/wireless/ath6kl/bmi/src/bmi.c b/drivers/net/wireless/ath6kl/bmi/src/bmi.c new file mode 100644 index 000000000000..4fe280a06478 --- /dev/null +++ b/drivers/net/wireless/ath6kl/bmi/src/bmi.c @@ -0,0 +1,984 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// +// Author(s): ="Atheros" +//============================================================================== + + +#include "hif.h" +#include "bmi.h" +#include "htc_api.h" +#include "bmi_internal.h" + +#ifdef DEBUG +static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = { + { ATH_DEBUG_BMI , "BMI Tracing"}, +}; + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi, + "bmi", + "Boot Manager Interface", + ATH_DEBUG_MASK_DEFAULTS, + ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc), + bmi_debug_desc); + +#endif + +/* +Although we had envisioned BMI to run on top of HTC, this is not how the +final implementation ended up. On the Target side, BMI is a part of the BSP +and does not use the HTC protocol nor even DMA -- it is intentionally kept +very simple. +*/ + +static A_BOOL pendingEventsFuncCheck = FALSE; +static A_UINT32 *pBMICmdCredits; +static A_UCHAR *pBMICmdBuf; +#define MAX_BMI_CMDBUF_SZ (BMI_DATASZ_MAX + \ + sizeof(A_UINT32) /* cmd */ + \ + sizeof(A_UINT32) /* addr */ + \ + sizeof(A_UINT32))/* length */ +#define BMI_COMMAND_FITS(sz) ((sz) <= MAX_BMI_CMDBUF_SZ) + +/* APIs visible to the driver */ +void +BMIInit(void) +{ + bmiDone = FALSE; + pendingEventsFuncCheck = FALSE; + + /* + * On some platforms, it's not possible to DMA to a static variable + * in a device driver (e.g. Linux loadable driver module). + * So we need to A_MALLOC space for "command credits" and for commands. + * + * Note: implicitly relies on A_MALLOC to provide a buffer that is + * suitable for DMA (or PIO). This buffer will be passed down the + * bus stack. + */ + if (!pBMICmdCredits) { + pBMICmdCredits = (A_UINT32 *)A_MALLOC_NOWAIT(4); + A_ASSERT(pBMICmdCredits); + } + + if (!pBMICmdBuf) { + pBMICmdBuf = (A_UCHAR *)A_MALLOC_NOWAIT(MAX_BMI_CMDBUF_SZ); + A_ASSERT(pBMICmdBuf); + } + + A_REGISTER_MODULE_DEBUG_INFO(bmi); +} + +A_STATUS +BMIDone(HIF_DEVICE *device) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n")); + return A_OK; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device)); + bmiDone = TRUE; + cid = BMI_DONE; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + if (pBMICmdCredits) { + A_FREE(pBMICmdCredits); + pBMICmdCredits = NULL; + } + + if (pBMICmdBuf) { + A_FREE(pBMICmdBuf); + pBMICmdBuf = NULL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info) +{ + A_STATUS status; + A_UINT32 cid; + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device)); + cid = BMI_GET_TARGET_INFO; + + status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid)); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver, + sizeof(targ_info->target_ver), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n")); + return A_ERROR; + } + + if (targ_info->target_ver == TARGET_VERSION_SENTINAL) { + /* Determine how many bytes are in the Target's targ_info */ + status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count, + sizeof(targ_info->target_info_byte_count), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n")); + return A_ERROR; + } + + /* + * The Target's targ_info doesn't match the Host's targ_info. + * We need to do some backwards compatibility work to make this OK. + */ + A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info)); + + /* Read the remainder of the targ_info */ + status = bmiBufferReceive(device, + ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count), + sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n", + targ_info->target_info_byte_count)); + return A_ERROR; + } + } else { + /* + * Target must be an AR6001 whose firmware does not + * support BMI_GET_TARGET_INFO. Construct the data + * that it would have sent. + */ + targ_info->target_info_byte_count=sizeof(*targ_info); + targ_info->target_type=TARGET_TYPE_AR6001; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n", + targ_info->target_ver, targ_info->target_type)); + + return A_OK; +} + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, rxlen; + + A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length))); + memset (pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_READ_MEMORY; + + remaining = length; + + while (remaining) + { + rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX; + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&(pBMICmdBuf[offset]), &rxlen, sizeof(rxlen)); + offset += sizeof(length); + + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + status = bmiBufferReceive(device, pBMICmdBuf, rxlen, TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(&buffer[length - remaining], pBMICmdBuf, rxlen); + remaining -= rxlen; address += rxlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n")); + return A_OK; +} + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length); + + A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + header)); + memset (pBMICmdBuf, 0, BMI_DATASZ_MAX + header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n", + device, address, length)); + + cid = BMI_WRITE_MEMORY; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&(pBMICmdBuf[offset]), &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&(pBMICmdBuf[offset]), &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; address += txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param))); + memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, *param)); + + cid = BMI_EXECUTE; + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&(pBMICmdBuf[offset]), param, sizeof(*param)); + offset += sizeof(*param); + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*param), FALSE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + + A_MEMCPY(param, pBMICmdBuf, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address))); + memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_SET_APP_START; + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n")); + return A_OK; +} + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address))); + memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_READ_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address)); + offset += sizeof(address); + + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*param), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(param, pBMICmdBuf, sizeof(*param)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param)); + return A_OK; +} + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address) + sizeof(param))); + memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address) + sizeof(param)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n", + device, address, param)); + + cid = BMI_WRITE_SOC_REGISTER; + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address)); + offset += sizeof(address); + A_MEMCPY(&(pBMICmdBuf[offset]), ¶m, sizeof(param)); + offset += sizeof(param); + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n")); + return A_OK; +} + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate))); + memset(pBMICmdBuf, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) + + sizeof(nbytes) + sizeof(do_activate)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n", + device, ROM_addr, RAM_addr, nbytes, do_activate)); + + cid = BMI_ROMPATCH_INSTALL; + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &ROM_addr, sizeof(ROM_addr)); + offset += sizeof(ROM_addr); + A_MEMCPY(&(pBMICmdBuf[offset]), &RAM_addr, sizeof(RAM_addr)); + offset += sizeof(RAM_addr); + A_MEMCPY(&(pBMICmdBuf[offset]), &nbytes, sizeof(nbytes)); + offset += sizeof(nbytes); + A_MEMCPY(&(pBMICmdBuf[offset]), &do_activate, sizeof(do_activate)); + offset += sizeof(do_activate); + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + status = bmiBufferReceive(device, pBMICmdBuf, sizeof(*rompatch_id), TRUE); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n")); + return A_ERROR; + } + A_MEMCPY(rompatch_id, pBMICmdBuf, sizeof(*rompatch_id)); + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id)); + return A_OK; +} + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(rompatch_id))); + memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(rompatch_id)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n", + device, rompatch_id)); + + cid = BMI_ROMPATCH_UNINSTALL; + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &rompatch_id, sizeof(rompatch_id)); + offset += sizeof(rompatch_id); + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id)); + return A_OK; +} + +static A_STATUS +_BMIrompatchChangeActivation(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list, + A_UINT32 do_activate) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 length; + + A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count))); + memset(pBMICmdBuf, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n", + device, rompatch_count)); + + cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE; + + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &rompatch_count, sizeof(rompatch_count)); + offset += sizeof(rompatch_count); + length = rompatch_count * sizeof(*rompatch_list); + A_MEMCPY(&(pBMICmdBuf[offset]), rompatch_list, length); + offset += length; + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n")); + + return A_OK; +} + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1); +} + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list) +{ + return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0); +} + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + A_UINT32 remaining, txlen; + const A_UINT32 header = sizeof(cid) + sizeof(length); + + A_ASSERT(BMI_COMMAND_FITS(BMI_DATASZ_MAX+header)); + memset (pBMICmdBuf, 0, BMI_DATASZ_MAX+header); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI Send LZ Data: Enter (device: 0x%p, length: %d)\n", + device, length)); + + cid = BMI_LZ_DATA; + + remaining = length; + while (remaining) + { + txlen = (remaining < (BMI_DATASZ_MAX - header)) ? + remaining : (BMI_DATASZ_MAX - header); + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &txlen, sizeof(txlen)); + offset += sizeof(txlen); + A_MEMCPY(&(pBMICmdBuf[offset]), &buffer[length - remaining], txlen); + offset += txlen; + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n")); + return A_ERROR; + } + remaining -= txlen; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Data: Exit\n")); + + return A_OK; +} + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address) +{ + A_UINT32 cid; + A_STATUS status; + A_UINT32 offset; + + A_ASSERT(BMI_COMMAND_FITS(sizeof(cid) + sizeof(address))); + memset (pBMICmdBuf, 0, sizeof(cid) + sizeof(address)); + + if (bmiDone) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, + ("BMI LZ Stream Start: Enter (device: 0x%p, address: 0x%x)\n", + device, address)); + + cid = BMI_LZ_STREAM_START; + offset = 0; + A_MEMCPY(&(pBMICmdBuf[offset]), &cid, sizeof(cid)); + offset += sizeof(cid); + A_MEMCPY(&(pBMICmdBuf[offset]), &address, sizeof(address)); + offset += sizeof(address); + status = bmiBufferSend(device, pBMICmdBuf, offset); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to Start LZ Stream to the device\n")); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI LZ Stream Start: Exit\n")); + + return A_OK; +} + +/* BMI Access routines */ +A_STATUS +bmiBufferSend(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length) +{ + A_STATUS status; + A_UINT32 timeout; + A_UINT32 address; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + *pBMICmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + + while(timeout-- && !(*pBMICmdCredits)) { + /* Read the counter register to get the command credits */ + address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4; + /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause + * a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to + * make all HIF accesses 4-byte aligned */ + status = HIFReadWrite(device, address, (A_UINT8 *)pBMICmdCredits, 4, + HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n")); + return A_ERROR; + } + /* the counter is only 8=bits, ignore anything in the upper 3 bytes */ + (*pBMICmdCredits) &= 0xFF; + } + + if (*pBMICmdCredits) { + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, + HIF_WR_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n")); + return A_ERROR; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferSend\n")); + return A_ERROR; + } + + return status; +} + +A_STATUS +bmiBufferReceive(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout) +{ + A_STATUS status; + A_UINT32 address; + A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX]; + HIF_PENDING_EVENTS_INFO hifPendingEvents; + static HIF_PENDING_EVENTS_FUNC getPendingEventsFunc = NULL; + + if (!pendingEventsFuncCheck) { + /* see if the HIF layer implements an alternative function to get pending events + * do this only once! */ + HIFConfigureDevice(device, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &getPendingEventsFunc, + sizeof(getPendingEventsFunc)); + pendingEventsFuncCheck = TRUE; + } + + HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR, + &mboxAddress[0], sizeof(mboxAddress)); + + /* + * During normal bootup, small reads may be required. + * Rather than issue an HIF Read and then wait as the Target + * adds successive bytes to the FIFO, we wait here until + * we know that response data is available. + * + * This allows us to cleanly timeout on an unexpected + * Target failure rather than risk problems at the HIF level. In + * particular, this avoids SDIO timeouts and possibly garbage + * data on some host controllers. And on an interconnect + * such as Compact Flash (as well as some SDIO masters) which + * does not provide any indication on data timeout, it avoids + * a potential hang or garbage response. + * + * Synchronization is more difficult for reads larger than the + * size of the MBOX FIFO (128B), because the Target is unable + * to push the 129th byte of data until AFTER the Host posts an + * HIF Read and removes some FIFO data. So for large reads the + * Host proceeds to post an HIF Read BEFORE all the data is + * actually available to read. Fortunately, large BMI reads do + * not occur in practice -- they're supported for debug/development. + * + * So Host/Target BMI synchronization is divided into these cases: + * CASE 1: length < 4 + * Should not happen + * + * CASE 2: 4 <= length <= 128 + * Wait for first 4 bytes to be in FIFO + * If CONSERVATIVE_BMI_READ is enabled, also wait for + * a BMI command credit, which indicates that the ENTIRE + * response is available in the the FIFO + * + * CASE 3: length > 128 + * Wait for the first 4 bytes to be in FIFO + * + * For most uses, a small timeout should be sufficient and we will + * usually see a response quickly; but there may be some unusual + * (debug) cases of BMI_EXECUTE where we want an larger timeout. + * For now, we use an unbounded busy loop while waiting for + * BMI_EXECUTE. + * + * If BMI_EXECUTE ever needs to support longer-latency execution, + * especially in production, this code needs to be enhanced to sleep + * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently + * a function of Host processor speed. + */ + if (length >= 4) { /* NB: Currently, always true */ + /* + * NB: word_available is declared static for esoteric reasons + * having to do with protection on some OSes. + */ + static A_UINT32 word_available; + A_UINT32 timeout; + + word_available = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while((!want_timeout || timeout--) && !word_available) { + + if (getPendingEventsFunc != NULL) { + status = getPendingEventsFunc(device, + &hifPendingEvents, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to get pending events \n")); + break; + } + + if (hifPendingEvents.AvailableRecvBytes >= sizeof(A_UINT32)) { + word_available = 1; + } + continue; + } + + status = HIFReadWrite(device, RX_LOOKAHEAD_VALID_ADDRESS, (A_UINT8 *)&word_available, + sizeof(word_available), HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read RX_LOOKAHEAD_VALID register\n")); + return A_ERROR; + } + /* We did a 4-byte read to the same register; all we really want is one bit */ + word_available &= (1 << ENDPOINT1); + } + + if (!word_available) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout - bmiBufferReceive FIFO empty\n")); + return A_ERROR; + } + } + +#define CONSERVATIVE_BMI_READ 0 +#if CONSERVATIVE_BMI_READ + /* + * This is an extra-conservative CREDIT check. It guarantees + * that ALL data is available in the FIFO before we start to + * read from the interconnect. + * + * This credit check is useless when firmware chooses to + * allow multiple outstanding BMI Command Credits, since the next + * credit will already be present. To restrict the Target to one + * BMI Command Credit, see HI_OPTION_BMI_CRED_LIMIT. + * + * And for large reads (when HI_OPTION_BMI_CRED_LIMIT is set) + * we cannot wait for the next credit because the Target's FIFO + * will not hold the entire response. So we need the Host to + * start to empty the FIFO sooner. (And again, large reads are + * not used in practice; they are for debug/development only.) + * + * For a more conservative Host implementation (which would be + * safer for a Compact Flash interconnect): + * Set CONSERVATIVE_BMI_READ (above) to 1 + * Set HI_OPTION_BMI_CRED_LIMIT and + * reduce BMI_DATASZ_MAX to 32 or 64 + */ + if ((length > 4) && (length < 128)) { /* check against MBOX FIFO size */ + A_UINT32 timeout; + + *pBMICmdCredits = 0; + timeout = BMI_COMMUNICATION_TIMEOUT; + while((!want_timeout || timeout--) && !(*pBMICmdCredits) { + /* Read the counter register to get the command credits */ + address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1; + /* read the counter using a 4-byte read. Since the counter is NOT auto-decrementing, + * we can read this counter multiple times using a non-incrementing address mode. + * The rationale here is to make all HIF accesses a multiple of 4 bytes */ + status = HIFReadWrite(device, address, (A_UINT8 *)pBMICmdCredits, sizeof(*pBMICmdCredits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n")); + return A_ERROR; + } + /* we did a 4-byte read to the same count register so mask off upper bytes */ + (*pBMICmdCredits) &= 0xFF; + } + + if (!(*pBMICmdCredits)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout- bmiBufferReceive no credit\n")); + return A_ERROR; + } + } +#endif + + address = mboxAddress[ENDPOINT1]; + status = HIFReadWrite(device, address, buffer, length, HIF_RD_SYNC_BYTE_INC, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n")); + return A_ERROR; + } + + return A_OK; +} + +A_STATUS +BMIFastDownload(HIF_DEVICE *device, A_UINT32 address, A_UCHAR *buffer, A_UINT32 length) +{ + A_STATUS status = A_ERROR; + A_UINT32 lastWord = 0; + A_UINT32 lastWordOffset = length & ~0x3; + A_UINT32 unalignedBytes = length & 0x3; + + status = BMILZStreamStart (device, address); + if (A_FAILED(status)) { + return A_ERROR; + } + + if (unalignedBytes) { + /* copy the last word into a zero padded buffer */ + A_MEMCPY(&lastWord, &buffer[lastWordOffset], unalignedBytes); + } + + status = BMILZData(device, buffer, lastWordOffset); + + if (A_FAILED(status)) { + return A_ERROR; + } + + if (unalignedBytes) { + status = BMILZData(device, (A_UINT8 *)&lastWord, 4); + } + + if (A_SUCCESS(status)) { + // + // Close compressed stream and open a new (fake) one. This serves mainly to flush Target caches. + // + status = BMILZStreamStart (device, 0x00); + if (A_FAILED(status)) { + return A_ERROR; + } + } + return status; +} + +A_STATUS +BMIRawWrite(HIF_DEVICE *device, A_UCHAR *buffer, A_UINT32 length) +{ + return bmiBufferSend(device, buffer, length); +} + +A_STATUS +BMIRawRead(HIF_DEVICE *device, A_UCHAR *buffer, A_UINT32 length, A_BOOL want_timeout) +{ + return bmiBufferReceive(device, buffer, length, want_timeout); +} diff --git a/drivers/net/wireless/ath6kl/bmi/src/makefile b/drivers/net/wireless/ath6kl/bmi/src/makefile new file mode 100644 index 000000000000..6e53a111b67f --- /dev/null +++ b/drivers/net/wireless/ath6kl/bmi/src/makefile @@ -0,0 +1,22 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation; +# +# Software distributed under the License is distributed on an "AS +# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# +#------------------------------------------------------------------------------ +#============================================================================== +# Author(s): ="Atheros" +#============================================================================== +!INCLUDE $(_MAKEENVROOT)\makefile.def + + + diff --git a/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h b/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h new file mode 100644 index 000000000000..78d29ca14dc2 --- /dev/null +++ b/drivers/net/wireless/ath6kl/hif/common/hif_sdio_common.h @@ -0,0 +1,88 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// common header file for HIF modules designed for SDIO +// +// Author(s): ="Atheros" +//============================================================================== + +#ifndef HIF_SDIO_COMMON_H_ +#define HIF_SDIO_COMMON_H_ + + /* SDIO manufacturer ID and Codes */ +#define MANUFACTURER_ID_AR6001_BASE 0x100 +#define MANUFACTURER_ID_AR6002_BASE 0x200 +#define MANUFACTURER_ID_AR6003_BASE 0x300 +#define MANUFACTURER_ID_AR6K_BASE_MASK 0xFF00 +#define FUNCTION_CLASS 0x0 +#define MANUFACTURER_CODE 0x271 /* Atheros */ + + /* Mailbox address in SDIO address space */ +#define HIF_MBOX_BASE_ADDR 0x800 +#define HIF_MBOX_WIDTH 0x800 +#define HIF_MBOX_START_ADDR(mbox) \ + ( HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH) + +#define HIF_MBOX_END_ADDR(mbox) \ + (HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1) + + /* extended MBOX address for larger MBOX writes to MBOX 0*/ +#define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800 +#define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6*1024) +#define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18*1024) + + /* version 1 of the chip has only a 12K extended mbox range */ +#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000 +#define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12*1024) + + /* GMBOX addresses */ +#define HIF_GMBOX_BASE_ADDR 0x7000 +#define HIF_GMBOX_WIDTH 0x4000 + + /* for SDIO we recommend a 128-byte block size */ +#define HIF_DEFAULT_IO_BLOCK_SIZE 128 + + /* set extended MBOX window information for SDIO interconnects */ +static INLINE void SetExtendedMboxWindowInfo(A_UINT16 Manfid, HIF_DEVICE_MBOX_INFO *pInfo) +{ + switch (Manfid & MANUFACTURER_ID_AR6K_BASE_MASK) { + case MANUFACTURER_ID_AR6001_BASE : + /* no extended MBOX */ + break; + case MANUFACTURER_ID_AR6002_BASE : + /* MBOX 0 has an extended range */ + pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR; + pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6002; + break; + case MANUFACTURER_ID_AR6003_BASE : + /* MBOX 0 has an extended range */ + pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1; + pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1; + pInfo->GMboxAddress = HIF_GMBOX_BASE_ADDR; + pInfo->GMboxSize = HIF_GMBOX_WIDTH; + break; + default: + A_ASSERT(FALSE); + break; + } +} + +/* special CCCR (func 0) registers */ + +#define CCCR_SDIO_IRQ_MODE_REG 0xF0 /* interrupt mode register */ +#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0) /* mode to enable special 4-bit interrupt assertion without clock*/ + +#endif /*HIF_SDIO_COMMON_H_*/ diff --git a/drivers/net/wireless/ath6kl/hif/sdio/Makefile b/drivers/net/wireless/ath6kl/hif/sdio/Makefile new file mode 100644 index 000000000000..6f282bb8ad5f --- /dev/null +++ b/drivers/net/wireless/ath6kl/hif/sdio/Makefile @@ -0,0 +1,86 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2005-2008 Atheros Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation; +# +# Software distributed under the License is distributed on an "AS +# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# +#------------------------------------------------------------------------------ +#============================================================================== +# Author(s): ="Atheros" +#============================================================================== + +# +#SDIO HIF makefile for atheros SDIO stack +# + +# Check for SDIO stack +ifdef ATH_SDIO_STACK_BASE +# Someone already set it on entry, the stack resides outside this tree, we will try to build it +_SDIO_STACK = YES +else +# Check for SDIO stack within this tree +_SDIO_STACK = $(shell if [ -f $(ATH_SRC_BASE)/sdiostack/src/Makefile ]; then echo "YES"; else echo "NO"; fi) + +ifeq ($(_SDIO_STACK), YES) + # SDIO stack is part of the kit and will need to be compiled +ATH_SDIO_STACK_BASE := $(ATH_SRC_BASE)/sdiostack +endif +endif + + +ifeq ($(ATH_BUS_SUBTYPE),linux_sdio) +_HIF_SUB_TYPE = linux_sdio +_SDIO_STACK = NO +else +_HIF_SUB_TYPE = linux_athsdio +endif + + +ifeq ($(_SDIO_STACK), YES) + # Pass and translate build variables to the SDIO stack makefile +_SDIO_STACK_MAKE_PARAMS := CT_BUILD_TYPE=$(ATH_BUILD_TYPE) \ + CT_OS_TYPE=linux \ + CT_OS_SUB_TYPE=$(ATH_OS_SUB_TYPE) \ + CT_LINUXPATH=$(ATH_LINUXPATH) \ + CT_BUILD_TYPE=$(ATH_BUILD_TYPE) \ + CT_CROSS_COMPILE_TYPE=$(ATH_CROSS_COMPILE_TYPE) \ + CT_ARCH_CPU_TYPE=$(ATH_ARCH_CPU_TYPE) \ + CT_HC_DRIVERS=$(ATH_HC_DRIVERS) \ + CT_MAKE_INCLUDE_OVERRIDE=$(_LOCALMAKE_INCLUDE) \ + CT_BUILD_OUTPUT_OVERRIDE=$(COMPILED_IMAGE_OBJECTS_PATH) \ + BUS_BUILD=1 +endif +EXTRA_CFLAGS += -I$(ATH_SRC_BASE)/hif/sdio/$(_HIF_SUB_TYPE)/include +EXTRA_CFLAGS += -DSDIO +EXTRA_CFLAGS += -I$(ATH_SDIO_STACK_BASE)/src/include + +ifeq ($(ATH_OS_SUB_TYPE),linux_2_4) +obj-y += ../../hif/sdio/linux_athsdio/src/hif.o +obj-y += ../../hif/sdio/linux_athsdio/src/hif_scatter.o +endif + +ifneq ($(ATH_OS_SUB_TYPE),linux_2_4) +ar6000-objs := ../../hif/sdio/$(_HIF_SUB_TYPE)/src/hif.o \ + ../../hif/sdio/$(_HIF_SUB_TYPE)/src/hif_scatter.o + + +endif + +all: +ifeq ($(_SDIO_STACK),YES) + $(MAKE) $(_SDIO_STACK_MAKE_PARAMS) -C $(ATH_SDIO_STACK_BASE)/src default + -cp -f $(ATH_SDIO_STACK_BASE)/src/Module.symvers $(COMPILED_IMAGE_OBJECTS_PATH) +endif + +clean: +ifeq ($(_SDIO_STACK),YES) + $(MAKE) $(_SDIO_STACK_MAKE_PARAMS) -C $(ATH_SDIO_STACK_BASE)/src clean +endif diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h new file mode 100644 index 000000000000..efdfd0dbfb9c --- /dev/null +++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h @@ -0,0 +1,134 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// internal header file for hif layer +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HIF_INTERNAL_H_ +#define _HIF_INTERNAL_H_ + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "hif.h" +#include "../../../common/hif_sdio_common.h" +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) +#include +#define HIF_LINUX_MMC_SCATTER_SUPPORT +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27) +#include +#else +#include +#endif + +#define BUS_REQUEST_MAX_NUM 64 + +#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000 +#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20 +#define FLAGS_CARD_ENAB 0x02 +#define FLAGS_CARD_IRQ_UNMSK 0x04 + +#define HIF_MBOX_BLOCK_SIZE HIF_DEFAULT_IO_BLOCK_SIZE +#define HIF_MBOX0_BLOCK_SIZE 1 +#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE +#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE + +struct _HIF_SCATTER_REQ_PRIV; + +typedef struct bus_request { + struct bus_request *next; /* link list of available requests */ + struct bus_request *inusenext; /* link list of in use requests */ + struct semaphore sem_req; + A_UINT32 address; /* request data */ + A_UCHAR *buffer; + A_UINT32 length; + A_UINT32 request; + void *context; + A_STATUS status; + struct _HIF_SCATTER_REQ_PRIV *pScatterReq; /* this request is a scatter request */ +} BUS_REQUEST; + +struct hif_device { + struct sdio_func *func; + spinlock_t asynclock; + struct task_struct* async_task; /* task to handle async commands */ + struct semaphore sem_async; /* wake up for async task */ + int async_shutdown; /* stop the async task */ + struct completion async_completion; /* thread completion */ + BUS_REQUEST *asyncreq; /* request for async tasklet */ + BUS_REQUEST *taskreq; /* async tasklet data */ + spinlock_t lock; + BUS_REQUEST *s_busRequestFreeQueue; /* free list */ + BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */ + void *claimedContext; + HTC_CALLBACKS htcCallbacks; + A_UINT8 *dma_buffer; + DL_LIST ScatterReqHead; /* scatter request list head */ + A_BOOL scatter_enabled; /* scatter enabled flag */ + A_BOOL is_suspend; +}; + +#define HIF_DMA_BUFFER_SIZE (32 * 1024) +#define CMD53_FIXED_ADDRESS 1 +#define CMD53_INCR_ADDRESS 2 + +BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device); +void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest); +void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest); + +#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT + +#define MAX_SCATTER_REQUESTS 4 +#define MAX_SCATTER_ENTRIES_PER_REQ 16 +#define MAX_SCATTER_REQ_TRANSFER_SIZE 32*1024 + +typedef struct _HIF_SCATTER_REQ_PRIV { + HIF_SCATTER_REQ *pHifScatterReq; /* HIF scatter request with allocated entries */ + HIF_DEVICE *device; /* this device */ + BUS_REQUEST *busrequest; /* request associated with request */ + /* scatter list for linux */ + struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ]; +} HIF_SCATTER_REQ_PRIV; + +#define ATH_DEBUG_SCATTER ATH_DEBUG_MAKE_MODULE_MASK(0) + +A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo); +void CleanupHIFScatterResources(HIF_DEVICE *device); +A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest); + +#else // HIF_LINUX_MMC_SCATTER_SUPPORT + +static inline A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo) +{ + return A_ENOTSUP; +} + +static inline A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest) +{ + return A_ENOTSUP; +} + +#define CleanupHIFScatterResources(d) { } + +#endif // HIF_LINUX_MMC_SCATTER_SUPPORT + +#endif // _HIF_INTERNAL_H_ + diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt new file mode 100644 index 000000000000..0c98fd89a343 --- /dev/null +++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/nativemmcstack_readme.txt @@ -0,0 +1,35 @@ +HIF support for native Linux MMC Stack. +paull@atheros.com + +11/6/09 +Added patches for the MMC stacks Standard Host Controller for 2.6.30 and 2.6.32 +Patches enable ENE board support and speed up transfers for any Standard Host Controller +linux2.6.30_mmc_std_host.patch +linuxMMC_std_host_2.6.32-rc5sdio.patch + + +2/18/2009 +Added patch for Freescale MX35 SD host driver. tested with SD25 AR6102 Olca 2.1.2 + +12/18/2008 +Tested on Freescale MX27 and OMAP3530 Beageleboard Linux ver 2.6.28 +adds DMA bounce buffer support +hif.c ver 5 and hif.h ver 4 are for the old HTC/HIF interface and shouold be useable with 2.1 drivers +ver 6 and 5 are for the new HTC/HIF interface +For older Linux MMC stack versions, comment out in hif.c hifDeviceInserted() the lines: + /* give us some time to enable, in ms */ + func->enable_timeout = 100; +it is only required on some platforms, eg Beagleboard. + +7/18/2008 + +a. tested on Fedora Core 9 kernel 2.6.25.6, x86 with ENE standrad host controller,using the Olca 2.1.1RC.15 +b. requires applying the linux2.6.25.6mmc.patch to the kernel drivers/mmc directory +c. through put is 20-22mbs up/down link +d. new platform type is: + ATH_PLATFORM=LOCAL_i686_NATIVEMMC-SDIO + TARGET_TYPE=AR6002 +e. known issues: unloading the driver on Fedora Core 9 after conecting to an AP seems to not be complete. + + + diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c new file mode 100644 index 000000000000..75becd04cc49 --- /dev/null +++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif.c @@ -0,0 +1,1010 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF layer reference implementation for Linux Native MMC stack +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#include +#include +#include + +/* by default setup a bounce buffer for the data packets, if the underlying host controller driver + does not use DMA you may be able to skip this step and save the memory allocation and transfer time */ +#define HIF_USE_DMA_BOUNCE_BUFFER 1 +#include "hif_internal.h" +#define ATH_MODULE_NAME hif +#include "a_debug.h" + + +#if HIF_USE_DMA_BOUNCE_BUFFER +/* macro to check if DMA buffer is WORD-aligned and DMA-able. Most host controllers assume the + * buffer is DMA'able and will bug-check otherwise (i.e. buffers on the stack). + * virt_addr_valid check fails on stack memory. + */ +#define BUFFER_NEEDS_BOUNCE(buffer) (((A_UINT32)(buffer) & 0x3) || !virt_addr_valid((buffer))) +#else +#define BUFFER_NEEDS_BOUNCE(buffer) (FALSE) +#endif + +/* ATHENV */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM) +#define dev_to_sdio_func(d) container_of(d, struct sdio_func, dev) +#define to_sdio_driver(d) container_of(d, struct sdio_driver, drv) +static int hifDeviceSuspend(struct device *dev); +static int hifDeviceResume(struct device *dev); +#endif /* CONFIG_PM */ +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id); +static void hifDeviceRemoved(struct sdio_func *func); +static HIF_DEVICE *addHifDevice(struct sdio_func *func); +static HIF_DEVICE *getHifDevice(struct sdio_func *func); +static void delHifDevice(HIF_DEVICE * device); +static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte); + +int reset_sdio_on_unload = 0; +module_param(reset_sdio_on_unload, int, 0644); + +extern A_UINT32 nohifscattersupport; + + +/* ------ Static Variables ------ */ +static const struct sdio_device_id ar6k_id_table[] = { + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) }, + { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1)) }, + { /* null */ }, +}; +MODULE_DEVICE_TABLE(sdio, ar6k_id_table); + +static struct sdio_driver ar6k_driver = { + .name = "ar6k_wlan", + .id_table = ar6k_id_table, + .probe = hifDeviceInserted, + .remove = hifDeviceRemoved, +}; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM) +/* New suspend/resume based on linux-2.6.32 + * Need to patch linux-2.6.32 with mmc2.6.32_suspend.patch + * Need to patch with msmsdcc2.6.29_suspend.patch for msm_sdcc host + */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) +static struct dev_pm_ops ar6k_device_pm_ops = { +#else +static struct pm_ops ar6k_device_pm_ops = { +#endif + .suspend = hifDeviceSuspend, + .resume = hifDeviceResume, +}; +#endif /* CONFIG_PM */ + +/* make sure we only unregister when registered. */ +static int registered = 0; + +OSDRV_CALLBACKS osdrvCallbacks; +extern A_UINT32 onebitmode; +extern A_UINT32 busspeedlow; +extern A_UINT32 debughif; + +static void ResetAllCards(void); + +#ifdef DEBUG + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(hif, + "hif", + "(Linux MMC) Host Interconnect Framework", + ATH_DEBUG_MASK_DEFAULTS, + 0, + NULL); + +#endif + + +/* ------ Functions ------ */ +A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks) +{ + int status; + AR_DEBUG_ASSERT(callbacks != NULL); + + A_REGISTER_MODULE_DEBUG_INFO(hif); + + /* store the callback handlers */ + osdrvCallbacks = *callbacks; + + /* Register with bus driver core */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n")); + registered = 1; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM) + if (callbacks->deviceSuspendHandler && callbacks->deviceResumeHandler) { + ar6k_driver.drv.pm = &ar6k_device_pm_ops; + } +#endif /* CONFIG_PM */ + status = sdio_register_driver(&ar6k_driver); + AR_DEBUG_ASSERT(status==0); + + if (status != 0) { + return A_ERROR; + } + + return A_OK; + +} + +static A_STATUS +__HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_UINT8 opcode; + A_STATUS status = A_OK; + int ret; + A_UINT8 *tbuffer; + A_BOOL bounced = FALSE; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: 0x%p, buffer:0x%p (addr:0x%X)\n", + device, buffer, address)); + + do { + if (request & HIF_EXTENDED_IO) { + //AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Command type: CMD53\n")); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid command type: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_BLOCK_BASIS) { + /* round to whole block length size */ + length = (length / HIF_MBOX_BLOCK_SIZE) * HIF_MBOX_BLOCK_SIZE; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Block mode (BlockLen: %d)\n", + length)); + } else if (request & HIF_BYTE_BASIS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Byte mode (BlockLen: %d)\n", + length)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid data mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + +#if 0 + /* useful for checking register accesses */ + if (length & 0x3) { + A_PRINTF(KERN_ALERT"AR6000: HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n", + request & HIF_WRITE ? "write":"read", address, length); + } +#endif + + if (request & HIF_WRITE) { + if ((address >= HIF_MBOX_START_ADDR(0)) && + (address <= HIF_MBOX_END_ADDR(3))) + { + + AR_DEBUG_ASSERT(length <= HIF_MBOX_WIDTH); + + /* + * Mailbox write. Adjust the address so that the last byte + * falls on the EOM address. + */ + address += (HIF_MBOX_WIDTH - length); + } + } + + if (request & HIF_FIXED_ADDRESS) { + opcode = CMD53_FIXED_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Fixed 0x%X\n", address)); + } else if (request & HIF_INCREMENTAL_ADDRESS) { + opcode = CMD53_INCR_ADDRESS; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Address mode: Incremental 0x%X\n", address)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid address mode: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (request & HIF_WRITE) { +#if HIF_USE_DMA_BOUNCE_BUFFER + if (BUFFER_NEEDS_BOUNCE(buffer)) { + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + tbuffer = device->dma_buffer; + /* copy the write data to the dma buffer */ + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + memcpy(tbuffer, buffer, length); + bounced = TRUE; + } else { + tbuffer = buffer; + } +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_writesb(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writesb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_toio(device->func, address, tbuffer, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: writeio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } + } else if (request & HIF_READ) { +#if HIF_USE_DMA_BOUNCE_BUFFER + if (BUFFER_NEEDS_BOUNCE(buffer)) { + AR_DEBUG_ASSERT(device->dma_buffer != NULL); + AR_DEBUG_ASSERT(length <= HIF_DMA_BUFFER_SIZE); + tbuffer = device->dma_buffer; + bounced = TRUE; + } else { + tbuffer = buffer; + } +#else + tbuffer = buffer; +#endif + if (opcode == CMD53_FIXED_ADDRESS) { + ret = sdio_readsb(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readsb ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } else { + ret = sdio_memcpy_fromio(device->func, tbuffer, address, length); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: readio ret=%d address: 0x%X, len: %d, 0x%X\n", + ret, address, length, *(int *)tbuffer)); + } +#if HIF_USE_DMA_BOUNCE_BUFFER + if (bounced) { + /* copy the read data from the dma buffer */ + memcpy(buffer, tbuffer, length); + } +#endif + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid direction: 0x%08x\n", request)); + status = A_EINVAL; + break; + } + + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: SDIO bus operation failed! MMC stack returned : %d \n", ret)); + status = A_ERROR; + } + } while (FALSE); + + return status; +} + +void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest) +{ + unsigned long flags; + BUS_REQUEST *async; + BUS_REQUEST *active; + + spin_lock_irqsave(&device->asynclock, flags); + active = device->asyncreq; + if (active == NULL) { + device->asyncreq = busrequest; + device->asyncreq->inusenext = NULL; + } else { + for (async = device->asyncreq; + async != NULL; + async = async->inusenext) { + active = async; + } + active->inusenext = busrequest; + busrequest->inusenext = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); +} + + +/* queue a read/write request */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context) +{ + A_STATUS status = A_OK; + BUS_REQUEST *busrequest; + + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device: %p addr:0x%X\n", device,address)); + + do { + if ((request & HIF_ASYNCHRONOUS) || (request & HIF_SYNCHRONOUS)){ + /* serialize all requests through the async thread */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Execution mode: %s\n", + (request & HIF_ASYNCHRONOUS)?"Async":"Synch")); + busrequest = hifAllocateBusRequest(device); + if (busrequest == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: no async bus requests available (%s, addr:0x%X, len:%d) \n", + request & HIF_READ ? "READ":"WRITE", address, length)); + return A_ERROR; + } + busrequest->address = address; + busrequest->buffer = buffer; + busrequest->length = length; + busrequest->request = request; + busrequest->context = context; + + AddToAsyncList(device, busrequest); + + if (request & HIF_SYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued sync req: 0x%X\n", (unsigned int)busrequest)); + + /* wait for completion */ + up(&device->sem_async); + if (down_interruptible(&busrequest->sem_req) != 0) { + /* interrupted, exit */ + return A_ERROR; + } else { + A_STATUS status = busrequest->status; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: sync return freeing 0x%X: 0x%X\n", + (unsigned int)busrequest, busrequest->status)); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, busrequest); + return status; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: queued async req: 0x%X\n", (unsigned int)busrequest)); + up(&device->sem_async); + return A_PENDING; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("AR6000: Invalid execution mode: 0x%08x\n", (unsigned int)request)); + status = A_EINVAL; + break; + } + } while(0); + + return status; +} +/* thread to serialize all requests, both sync and async */ +static int async_task(void *param) + { + HIF_DEVICE *device; + BUS_REQUEST *request; + A_STATUS status; + unsigned long flags; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task\n")); + set_current_state(TASK_INTERRUPTIBLE); + while(!device->async_shutdown) { + /* wait for work */ + if (down_interruptible(&device->sem_async) != 0) { + /* interrupted, exit */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task interrupted\n")); + break; + } + if (device->async_shutdown) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async task stopping\n")); + break; + } + /* we want to hold the host over multiple cmds if possible, but holding the host blocks card interrupts */ + sdio_claim_host(device->func); + spin_lock_irqsave(&device->asynclock, flags); + /* pull the request to work on */ + while (device->asyncreq != NULL) { + request = device->asyncreq; + if (request->inusenext != NULL) { + device->asyncreq = request->inusenext; + } else { + device->asyncreq = NULL; + } + spin_unlock_irqrestore(&device->asynclock, flags); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task processing req: 0x%X\n", (unsigned int)request)); + + if (request->pScatterReq != NULL) { + A_ASSERT(device->scatter_enabled); + /* this is a queued scatter request, pass the request to scatter routine which + * executes it synchronously, note, no need to free the request since scatter requests + * are maintained on a separate list */ + status = DoHifReadWriteScatter(device,request); + } else { + /* call HIFReadWrite in sync mode to do the work */ + status = __HIFReadWrite(device, request->address, request->buffer, + request->length, request->request & ~HIF_SYNCHRONOUS, NULL); + if (request->request & HIF_ASYNCHRONOUS) { + void *context = request->context; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task freeing req: 0x%X\n", (unsigned int)request)); + hifFreeBusRequest(device, request); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task completion routine req: 0x%X\n", (unsigned int)request)); + device->htcCallbacks.rwCompletionHandler(context, status); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: async_task upping req: 0x%X\n", (unsigned int)request)); + request->status = status; + up(&request->sem_req); + } + } + spin_lock_irqsave(&device->asynclock, flags); + } + spin_unlock_irqrestore(&device->asynclock, flags); + sdio_release_host(device->func); + } + + complete_and_exit(&device->async_completion, 0); + return 0; + } + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen) +{ + A_UINT32 count; + A_STATUS status; + + switch(opcode) { + case HIF_DEVICE_GET_MBOX_BLOCK_SIZE: + ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE; + ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE; + ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE; + ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE; + break; + + case HIF_DEVICE_GET_MBOX_ADDR: + for (count = 0; count < 4; count ++) { + ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count); + } + + if (configLen >= sizeof(HIF_DEVICE_MBOX_INFO)) { + SetExtendedMboxWindowInfo((A_UINT16)device->func->device, + (HIF_DEVICE_MBOX_INFO *)config); + } + + break; + case HIF_DEVICE_GET_IRQ_PROC_MODE: + *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_SYNC_ONLY; + break; + case HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT: + if (!device->scatter_enabled) { + return A_ENOTSUP; + } + status = SetupHIFScatterSupport(device, (HIF_DEVICE_SCATTER_SUPPORT_INFO *)config); + if (A_FAILED(status)) { + device->scatter_enabled = FALSE; + } + return status; + case HIF_DEVICE_GET_OS_DEVICE: + /* pass back a pointer to the SDIO function's "dev" struct */ + ((HIF_DEVICE_OS_DEVICE_INFO *)config)->pOSDevice = &device->func->dev; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + ("AR6000: Unsupported configuration opcode: %d\n", opcode)); + return A_ERROR; + } + + return A_OK; +} + +void +HIFShutDownDevice(HIF_DEVICE *device) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +HIFShutDownDevice\n")); + if (device != NULL) { + AR_DEBUG_ASSERT(device->func != NULL); + } else { + /* since we are unloading the driver anyways, reset all cards in case the SDIO card + * is externally powered and we are unloading the SDIO stack. This avoids the problem when + * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already + * enumerated */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFShutDownDevice, resetting\n")); + ResetAllCards(); + + /* Unregister with bus driver core */ + if (registered) { + registered = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistering with the bus driver\n")); + sdio_unregister_driver(&ar6k_driver); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: Unregistered\n")); + } + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -HIFShutDownDevice\n")); +} + +static void +hifIRQHandler(struct sdio_func *func) +{ + A_STATUS status; + HIF_DEVICE *device; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n")); + + device = getHifDevice(func); + /* release the host during ints so we can pick it back up when we process cmds */ + sdio_release_host(device->func); + status = device->htcCallbacks.dsrHandler(device->htcCallbacks.context); + sdio_claim_host(device->func); + AR_DEBUG_ASSERT(status == A_OK || status == A_ECANCELED); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifIRQHandler\n")); +} + +/* handle HTC startup via thread*/ +static int startup_task(void *param) +{ + HIF_DEVICE *device; + + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from startup_task\n")); + /* start up inform DRV layer */ + if ((osdrvCallbacks.deviceInsertedHandler(osdrvCallbacks.context,device)) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n")); + } + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM) +/* handle HTC startup via thread*/ +static int resume_task(void *param) +{ + HIF_DEVICE *device; + device = (HIF_DEVICE *)param; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: call HTC from resume_task\n")); + /* start up inform DRV layer */ + if (device && device->claimedContext && osdrvCallbacks.deviceResumeHandler && + osdrvCallbacks.deviceResumeHandler(device->claimedContext) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: Device rejected\n")); + } + return 0; +} +#endif /* CONFIG_PM */ + +static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id) +{ + int ret; + HIF_DEVICE * device; + int count; + struct task_struct* startup_task_struct; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, + ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n", + func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize)); + + addHifDevice(func); + device = getHifDevice(func); + + spin_lock_init(&device->lock); + + spin_lock_init(&device->asynclock); + + DL_LIST_INIT(&device->ScatterReqHead); + + if (!nohifscattersupport) { + /* try to allow scatter operation on all instances, + * unless globally overridden */ + device->scatter_enabled = TRUE; + } + + /* enable the SDIO function */ + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: claim\n")); + sdio_claim_host(func); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: enable\n")); + + if ((id->device & MANUFACTURER_ID_AR6K_BASE_MASK) >= MANUFACTURER_ID_AR6003_BASE) { + /* enable 4-bit ASYNC interrupt on AR6003 or later devices */ + ret = Func0_CMD52WriteByte(func->card, CCCR_SDIO_IRQ_MODE_REG, SDIO_IRQ_MODE_ASYNC_4BIT_IRQ); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: failed to enable 4-bit ASYNC IRQ mode %d \n",ret)); + sdio_release_host(func); + return ret; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: 4-bit ASYNC IRQ mode enabled\n")); + } + + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + /* give us some time to enable, in ms */ + func->enable_timeout = 100; +#endif + ret = sdio_enable_func(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n", + __FUNCTION__, ret)); + sdio_release_host(func); + return ret; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: set block size 0x%X\n", HIF_MBOX_BLOCK_SIZE)); + ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); + sdio_release_host(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n", + __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret)); + return ret; + } + /* Initialize the bus requests to be used later */ + A_MEMZERO(device->busRequest, sizeof(device->busRequest)); + for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) { + sema_init(&device->busRequest[count].sem_req, 0); + hifFreeBusRequest(device, &device->busRequest[count]); + } + + /* create async I/O thread */ + device->async_shutdown = 0; + device->async_task = kthread_create(async_task, + (void *)device, + "AR6K Async"); + if (IS_ERR(device->async_task)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__)); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n")); + sema_init(&device->sem_async, 0); + wake_up_process(device->async_task ); + + /* create startup thread */ + startup_task_struct = kthread_create(startup_task, + (void *)device, + "AR6K startup"); + if (IS_ERR(startup_task_struct)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create startup task\n", __FUNCTION__)); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start startup task\n")); + wake_up_process(startup_task_struct); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: return %d\n", ret)); + return ret; +} + + +void +HIFAckInterrupt(HIF_DEVICE *device) +{ + AR_DEBUG_ASSERT(device != NULL); + + /* Acknowledge our function IRQ */ +} + +void +HIFUnMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFUnMaskInterrupt\n")); + + /* Register the IRQ Handler */ + sdio_claim_host(device->func); + ret = sdio_claim_irq(device->func, hifIRQHandler); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +void HIFMaskInterrupt(HIF_DEVICE *device) +{ + int ret;; + + AR_DEBUG_ASSERT(device != NULL); + AR_DEBUG_ASSERT(device->func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFMaskInterrupt\n")); + + /* Mask our function IRQ */ + sdio_claim_host(device->func); + ret = sdio_release_irq(device->func); + sdio_release_host(device->func); + AR_DEBUG_ASSERT(ret == 0); +} + +BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device) +{ + BUS_REQUEST *busrequest; + unsigned long flag; + + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + /* Remove first in list */ + if((busrequest = device->s_busRequestFreeQueue) != NULL) + { + device->s_busRequestFreeQueue = busrequest->next; + } + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifAllocateBusRequest: 0x%p\n", busrequest)); + return busrequest; +} + +void +hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest) +{ + unsigned long flag; + + AR_DEBUG_ASSERT(busrequest != NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: hifFreeBusRequest: 0x%p\n", busrequest)); + /* Acquire lock */ + spin_lock_irqsave(&device->lock, flag); + + + /* Insert first in list */ + busrequest->next = device->s_busRequestFreeQueue; + busrequest->inusenext = NULL; + device->s_busRequestFreeQueue = busrequest; + + /* Release lock */ + spin_unlock_irqrestore(&device->lock, flag); +} + +static int hifDisableFunc(HIF_DEVICE *device, struct sdio_func *func) +{ + int ret = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n")); + device = getHifDevice(func); + if (!IS_ERR(device->async_task)) { + init_completion(&device->async_completion); + device->async_shutdown = 1; + up(&device->sem_async); + wait_for_completion(&device->async_completion); + device->async_task = NULL; + } + /* Disable the card */ + sdio_claim_host(device->func); + ret = sdio_disable_func(device->func); + + if (reset_sdio_on_unload) { + /* reset the SDIO interface. This is useful in automated testing where the card + * does not need to be removed at the end of the test. It is expected that the user will + * also unload/reload the host controller driver to force the bus driver to re-enumerate the slot */ + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("AR6000: reseting SDIO card back to uninitialized state \n")); + + /* NOTE : sdio_f0_writeb() cannot be used here, that API only allows access + * to undefined registers in the range of: 0xF0-0xFF */ + + ret = Func0_CMD52WriteByte(device->func->card, SDIO_CCCR_ABORT, (1 << 3)); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: reset failed : %d \n",ret)); + } + } + + sdio_release_host(device->func); + return ret; +} + +static void hifDeviceRemoved(struct sdio_func *func) +{ + A_STATUS status = A_OK; + HIF_DEVICE *device; + AR_DEBUG_ASSERT(func != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n")); + device = getHifDevice(func); + if (device->claimedContext != NULL) { + status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device); + } + + if (device->is_suspend) { + device->is_suspend = FALSE; + } else { + if (hifDisableFunc(device, func)!=0) { + status = A_ERROR; + } + } + CleanupHIFScatterResources(device); + + delHifDevice(device); + AR_DEBUG_ASSERT(status == A_OK); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n")); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) && defined(CONFIG_PM) +static int hifDeviceSuspend(struct device *dev) +{ + struct sdio_func *func = dev_to_sdio_func(dev); + A_STATUS status = A_OK; + HIF_DEVICE *device; + device = getHifDevice(func); + if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) { + status = osdrvCallbacks.deviceSuspendHandler(device->claimedContext); + } + if (status == A_OK) { + hifDisableFunc(device, func); + device->is_suspend = TRUE; + } else if (status == A_EBUSY) { + status = A_OK; /* assume that sdio host controller will take care the power of wifi chip */ + } + return A_SUCCESS(status) ? 0 : status; +} + +static int hifDeviceResume(struct device *dev) +{ + struct task_struct* pTask; + const char *taskName; + int (*taskFunc)(void *); + struct sdio_func *func = dev_to_sdio_func(dev); + A_STATUS ret = A_OK; + HIF_DEVICE *device; + device = getHifDevice(func); + + if (device->is_suspend) { + /* enable the SDIO function */ + sdio_claim_host(func); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + /* give us some time to enable, in ms */ + func->enable_timeout = 100; +#endif + ret = sdio_enable_func(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n", + __FUNCTION__, ret)); + sdio_release_host(func); + return ret; + } + ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE); + sdio_release_host(func); + if (ret) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n", + __FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret)); + return ret; + } + device->is_suspend = FALSE; + /* create async I/O thread */ + if (!device->async_task) { + device->async_shutdown = 0; + device->async_task = kthread_create(async_task, + (void *)device, + "AR6K Async"); + if (IS_ERR(device->async_task)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__)); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n")); + wake_up_process(device->async_task ); + } + } + + if (!device->claimedContext) { + printk("WARNING!!! No claimedContext during resume wlan\n"); + taskFunc = startup_task; + taskName = "AR6K startup"; + } else { + taskFunc = resume_task; + taskName = "AR6K resume"; + } + /* create resume thread */ + pTask = kthread_create(taskFunc, (void *)device, taskName); + if (IS_ERR(pTask)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create resume task\n", __FUNCTION__)); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start resume task\n")); + wake_up_process(pTask); + return A_SUCCESS(ret) ? 0 : ret; +} +#endif /* CONFIG_PM */ + +static HIF_DEVICE * +addHifDevice(struct sdio_func *func) +{ + HIF_DEVICE *hifdevice; + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n")); + AR_DEBUG_ASSERT(func != NULL); + hifdevice = (HIF_DEVICE *)kzalloc(sizeof(HIF_DEVICE), GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice != NULL); +#if HIF_USE_DMA_BOUNCE_BUFFER + hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL); + AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL); +#endif + hifdevice->func = func; + sdio_set_drvdata(func, hifdevice); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice)); + return hifdevice; +} + +static HIF_DEVICE * +getHifDevice(struct sdio_func *func) +{ + AR_DEBUG_ASSERT(func != NULL); + return (HIF_DEVICE *)sdio_get_drvdata(func); +} + +static void +delHifDevice(HIF_DEVICE * device) +{ + AR_DEBUG_ASSERT(device!= NULL); + AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: delHifDevice; 0x%p\n", device)); + if (device->dma_buffer != NULL) { + kfree(device->dma_buffer); + } + kfree(device); +} + +static void ResetAllCards(void) +{ +} + +void HIFClaimDevice(HIF_DEVICE *device, void *context) +{ + device->claimedContext = context; +} + +void HIFReleaseDevice(HIF_DEVICE *device) +{ + device->claimedContext = NULL; +} + +A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks) +{ + if (device->htcCallbacks.context != NULL) { + /* already in use! */ + return A_ERROR; + } + device->htcCallbacks = *callbacks; + return A_OK; +} + +void HIFDetachHTC(HIF_DEVICE *device) +{ + A_MEMZERO(&device->htcCallbacks,sizeof(device->htcCallbacks)); +} + +#define SDIO_SET_CMD52_ARG(arg,rw,func,raw,address,writedata) \ + (arg) = (((rw) & 1) << 31) | \ + (((func) & 0x7) << 28) | \ + (((raw) & 1) << 27) | \ + (1 << 26) | \ + (((address) & 0x1FFFF) << 9) | \ + (1 << 8) | \ + ((writedata) & 0xFF) + +#define SDIO_SET_CMD52_READ_ARG(arg,func,address) \ + SDIO_SET_CMD52_ARG(arg,0,(func),0,address,0x00) +#define SDIO_SET_CMD52_WRITE_ARG(arg,func,address,value) \ + SDIO_SET_CMD52_ARG(arg,1,(func),0,address,value) + +static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte) +{ + struct mmc_command ioCmd; + unsigned long arg; + + memset(&ioCmd,0,sizeof(ioCmd)); + SDIO_SET_CMD52_WRITE_ARG(arg,0,address,byte); + ioCmd.opcode = SD_IO_RW_DIRECT; + ioCmd.arg = arg; + ioCmd.flags = MMC_RSP_R5 | MMC_CMD_AC; + + return mmc_wait_for_cmd(card->host, &ioCmd, 0); +} + + + + diff --git a/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c new file mode 100644 index 000000000000..de236d269f0d --- /dev/null +++ b/drivers/net/wireless/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c @@ -0,0 +1,390 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF scatter implementation +// +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include +#include +#include "hif_internal.h" +#define ATH_MODULE_NAME hif +#include "a_debug.h" + +#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT + +#define _CMD53_ARG_READ 0 +#define _CMD53_ARG_WRITE 1 +#define _CMD53_ARG_BLOCK_BASIS 1 +#define _CMD53_ARG_FIXED_ADDRESS 0 +#define _CMD53_ARG_INCR_ADDRESS 1 + +#define SDIO_SET_CMD53_ARG(arg,rw,func,mode,opcode,address,bytes_blocks) \ + (arg) = (((rw) & 1) << 31) | \ + (((func) & 0x7) << 28) | \ + (((mode) & 1) << 27) | \ + (((opcode) & 1) << 26) | \ + (((address) & 0x1FFFF) << 9) | \ + ((bytes_blocks) & 0x1FF) + +static void FreeScatterReq(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq) +{ + unsigned long flag; + + spin_lock_irqsave(&device->lock, flag); + + DL_ListInsertTail(&device->ScatterReqHead, &pReq->ListLink); + + spin_unlock_irqrestore(&device->lock, flag); + +} + +static HIF_SCATTER_REQ *AllocScatterReq(HIF_DEVICE *device) +{ + DL_LIST *pItem; + unsigned long flag; + + spin_lock_irqsave(&device->lock, flag); + + pItem = DL_ListRemoveItemFromHead(&device->ScatterReqHead); + + spin_unlock_irqrestore(&device->lock, flag); + + if (pItem != NULL) { + return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink); + } + + return NULL; +} + + /* called by async task to perform the operation synchronously using direct MMC APIs */ +A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest) +{ + int i; + A_UINT8 rw; + A_UINT8 opcode; + struct mmc_request mmcreq; + struct mmc_command cmd; + struct mmc_data data; + HIF_SCATTER_REQ_PRIV *pReqPriv; + HIF_SCATTER_REQ *pReq; + A_STATUS status = A_OK; + struct scatterlist *pSg; + + pReqPriv = busrequest->pScatterReq; + + A_ASSERT(pReqPriv != NULL); + + pReq = pReqPriv->pHifScatterReq; + + memset(&mmcreq, 0, sizeof(struct mmc_request)); + memset(&cmd, 0, sizeof(struct mmc_command)); + memset(&data, 0, sizeof(struct mmc_data)); + + data.blksz = HIF_MBOX_BLOCK_SIZE; + data.blocks = pReq->TotalLength / HIF_MBOX_BLOCK_SIZE; + + AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: (%s) Address: 0x%X, (BlockLen: %d, BlockCount: %d) , (tot:%d,sg:%d)\n", + (pReq->Request & HIF_WRITE) ? "WRITE":"READ", pReq->Address, data.blksz, data.blocks, + pReq->TotalLength,pReq->ValidScatterEntries)); + + if (pReq->Request & HIF_WRITE) { + rw = _CMD53_ARG_WRITE; + data.flags = MMC_DATA_WRITE; + } else { + rw = _CMD53_ARG_READ; + data.flags = MMC_DATA_READ; + } + + if (pReq->Request & HIF_FIXED_ADDRESS) { + opcode = _CMD53_ARG_FIXED_ADDRESS; + } else { + opcode = _CMD53_ARG_INCR_ADDRESS; + } + + /* fill SG entries */ + pSg = pReqPriv->sgentries; + sg_init_table(pSg, pReq->ValidScatterEntries); + + /* assemble SG list */ + for (i = 0 ; i < pReq->ValidScatterEntries ; i++, pSg++) { + /* setup each sg entry */ + if ((A_UINT32)pReq->ScatterList[i].pBuffer & 0x3) { + /* note some scatter engines can handle unaligned buffers, print this + * as informational only */ + AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, + ("HIF: (%s) Scatter Buffer is unaligned 0x%08x\n", + pReq->Request & HIF_WRITE ? "WRITE":"READ", + (A_UINT32)pReq->ScatterList[i].pBuffer)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, (" %d: Addr:0x%X, Len:%d \n", + i,(A_UINT32)pReq->ScatterList[i].pBuffer,pReq->ScatterList[i].Length)); + + sg_set_buf(pSg, pReq->ScatterList[i].pBuffer, pReq->ScatterList[i].Length); + } + /* set scatter-gather table for request */ + data.sg = pReqPriv->sgentries; + data.sg_len = pReq->ValidScatterEntries; + /* set command argument */ + SDIO_SET_CMD53_ARG(cmd.arg, + rw, + device->func->num, + _CMD53_ARG_BLOCK_BASIS, + opcode, + pReq->Address, + data.blocks); + + cmd.opcode = SD_IO_RW_EXTENDED; + cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC; + + mmcreq.cmd = &cmd; + mmcreq.data = &data; + + mmc_set_data_timeout(&data, device->func->card); + /* synchronous call to process request */ + mmc_wait_for_req(device->func->card->host, &mmcreq); + + if (cmd.error) { + status = A_ERROR; + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: cmd error: %d \n",cmd.error)); + } + + if (data.error) { + status = A_ERROR; + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: data error: %d \n",data.error)); + } + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: FAILED!!! (%s) Address: 0x%X, Block mode (BlockLen: %d, BlockCount: %d)\n", + (pReq->Request & HIF_WRITE) ? "WRITE":"READ",pReq->Address, data.blksz, data.blocks)); + } + + /* set completion status, fail or success */ + pReq->CompletionStatus = status; + + if (pReq->Request & HIF_ASYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: async_task completion routine req: 0x%X (%d)\n",(unsigned int)busrequest, status)); + /* complete the request */ + A_ASSERT(pReq->CompletionRoutine != NULL); + pReq->CompletionRoutine(pReq); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER async_task upping busrequest : 0x%X (%d)\n", (unsigned int)busrequest,status)); + /* signal wait */ + up(&busrequest->sem_req); + } + + return status; +} + + /* callback to issue a read-write scatter request */ +static A_STATUS HifReadWriteScatter(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq) +{ + A_STATUS status = A_EINVAL; + A_UINT32 request = pReq->Request; + HIF_SCATTER_REQ_PRIV *pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0]; + + do { + + A_ASSERT(pReqPriv != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: total len: %d Scatter Entries: %d\n", + pReq->TotalLength, pReq->ValidScatterEntries)); + + if (!(request & HIF_EXTENDED_IO)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("HIF-SCATTER: Invalid command type: 0x%08x\n", request)); + break; + } + + if (!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS))) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("HIF-SCATTER: Invalid execution mode: 0x%08x\n", request)); + break; + } + + if (!(request & HIF_BLOCK_BASIS)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("HIF-SCATTER: Invalid data mode: 0x%08x\n", request)); + break; + } + + if (pReq->TotalLength > MAX_SCATTER_REQ_TRANSFER_SIZE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, + ("HIF-SCATTER: Invalid length: %d \n", pReq->TotalLength)); + break; + } + + if (pReq->TotalLength == 0) { + A_ASSERT(FALSE); + break; + } + + /* add bus request to the async list for the async I/O thread to process */ + AddToAsyncList(device, pReqPriv->busrequest); + + if (request & HIF_SYNCHRONOUS) { + AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued sync req: 0x%X\n", (unsigned int)pReqPriv->busrequest)); + /* signal thread and wait */ + up(&device->sem_async); + if (down_interruptible(&pReqPriv->busrequest->sem_req) != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,("HIF-SCATTER: interrupted! \n")); + /* interrupted, exit */ + status = A_ERROR; + break; + } else { + status = pReq->CompletionStatus; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued async req: 0x%X\n", (unsigned int)pReqPriv->busrequest)); + /* wake thread, it will process and then take care of the async callback */ + up(&device->sem_async); + status = A_OK; + } + + } while (FALSE); + + if (A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) { + pReq->CompletionStatus = status; + pReq->CompletionRoutine(pReq); + status = A_OK; + } + + return status; +} + + /* setup of HIF scatter resources */ +A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo) +{ + A_STATUS status = A_ERROR; + int i; + HIF_SCATTER_REQ_PRIV *pReqPriv; + BUS_REQUEST *busrequest; + + do { + + /* check if host supports scatter requests and it meets our requirements */ + if (device->func->card->host->max_hw_segs < MAX_SCATTER_ENTRIES_PER_REQ) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : host only supports scatter of : %d entries, need: %d \n", + device->func->card->host->max_hw_segs, MAX_SCATTER_ENTRIES_PER_REQ)); + status = A_ENOTSUP; + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HIF-SCATTER Enabled: max scatter req : %d entries: %d \n", + MAX_SCATTER_REQUESTS, MAX_SCATTER_ENTRIES_PER_REQ)); + + for (i = 0; i < MAX_SCATTER_REQUESTS; i++) { + /* allocate the private request blob */ + pReqPriv = (HIF_SCATTER_REQ_PRIV *)A_MALLOC(sizeof(HIF_SCATTER_REQ_PRIV)); + if (NULL == pReqPriv) { + break; + } + A_MEMZERO(pReqPriv, sizeof(HIF_SCATTER_REQ_PRIV)); + /* save the device instance*/ + pReqPriv->device = device; + /* allocate the scatter request */ + pReqPriv->pHifScatterReq = (HIF_SCATTER_REQ *)A_MALLOC(sizeof(HIF_SCATTER_REQ) + + (MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM))); + + if (NULL == pReqPriv->pHifScatterReq) { + A_FREE(pReqPriv); + break; + } + /* just zero the main part of the scatter request */ + A_MEMZERO(pReqPriv->pHifScatterReq, sizeof(HIF_SCATTER_REQ)); + /* back pointer to the private struct */ + pReqPriv->pHifScatterReq->HIFPrivate[0] = pReqPriv; + /* allocate a bus request for this scatter request */ + busrequest = hifAllocateBusRequest(device); + if (NULL == busrequest) { + A_FREE(pReqPriv->pHifScatterReq); + A_FREE(pReqPriv); + break; + } + /* assign the scatter request to this bus request */ + busrequest->pScatterReq = pReqPriv; + /* point back to the request */ + pReqPriv->busrequest = busrequest; + /* add it to the scatter pool */ + FreeScatterReq(device,pReqPriv->pHifScatterReq); + } + + if (i != MAX_SCATTER_REQUESTS) { + status = A_NO_MEMORY; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : failed to alloc scatter resources !\n")); + break; + } + + /* set scatter function pointers */ + pInfo->pAllocateReqFunc = AllocScatterReq; + pInfo->pFreeReqFunc = FreeScatterReq; + pInfo->pReadWriteScatterFunc = HifReadWriteScatter; + pInfo->MaxScatterEntries = MAX_SCATTER_ENTRIES_PER_REQ; + pInfo->MaxTransferSizePerScatterReq = MAX_SCATTER_REQ_TRANSFER_SIZE; + + status = A_OK; + + } while (FALSE); + + if (A_FAILED(status)) { + CleanupHIFScatterResources(device); + } + + return status; +} + + /* clean up scatter support */ +void CleanupHIFScatterResources(HIF_DEVICE *device) +{ + HIF_SCATTER_REQ_PRIV *pReqPriv; + HIF_SCATTER_REQ *pReq; + + /* empty the free list */ + + while (1) { + + pReq = AllocScatterReq(device); + + if (NULL == pReq) { + break; + } + + pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0]; + A_ASSERT(pReqPriv != NULL); + + if (pReqPriv->busrequest != NULL) { + pReqPriv->busrequest->pScatterReq = NULL; + /* free bus request */ + hifFreeBusRequest(device, pReqPriv->busrequest); + pReqPriv->busrequest = NULL; + } + + if (pReqPriv->pHifScatterReq != NULL) { + A_FREE(pReqPriv->pHifScatterReq); + pReqPriv->pHifScatterReq = NULL; + } + + A_FREE(pReqPriv); + } +} + +#endif // HIF_LINUX_MMC_SCATTER_SUPPORT diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c new file mode 100644 index 000000000000..dfcc60b548e4 --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.c @@ -0,0 +1,1399 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "AR6002/hw2.0/hw/mbox_host_reg.h" +#include "a_osapi.h" +#include "../htc_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + +#define MAILBOX_FOR_BLOCK_SIZE 1 + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + +static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev); + +void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket) +{ + LOCK_AR6K(pDev); + HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket); + UNLOCK_AR6K(pDev); +} + +HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev) +{ + HTC_PACKET *pPacket; + + LOCK_AR6K(pDev); + pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList); + UNLOCK_AR6K(pDev); + + return pPacket; +} + +void DevCleanup(AR6K_DEVICE *pDev) +{ + DevCleanupGMbox(pDev); + + if (pDev->HifAttached) { + HIFDetachHTC(pDev->HIFDevice); + pDev->HifAttached = FALSE; + } + + DevCleanupVirtualScatterSupport(pDev); + + if (A_IS_MUTEX_VALID(&pDev->Lock)) { + A_MUTEX_DELETE(&pDev->Lock); + } +} + +A_STATUS DevSetup(AR6K_DEVICE *pDev) +{ + A_UINT32 blocksizes[AR6K_MAILBOXES]; + A_STATUS status = A_OK; + int i; + HTC_CALLBACKS htcCallbacks; + + do { + + DL_LIST_INIT(&pDev->ScatterReqHead); + /* initialize our free list of IO packets */ + INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList); + A_MUTEX_INIT(&pDev->Lock); + + A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS)); + /* the device layer handles these */ + htcCallbacks.rwCompletionHandler = DevRWCompletionHandler; + htcCallbacks.dsrHandler = DevDsrHandler; + htcCallbacks.context = pDev; + + status = HIFAttachHTC(pDev->HIFDevice, &htcCallbacks); + + if (A_FAILED(status)) { + break; + } + + pDev->HifAttached = TRUE; + + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + &pDev->MailBoxInfo, sizeof(pDev->MailBoxInfo)); + + if (status != A_OK) { + A_ASSERT(FALSE); + break; + } + + /* carve up register I/O packets (these are for ASYNC register I/O ) */ + for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) { + HTC_PACKET *pIOPacket; + pIOPacket = &pDev->RegIOBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket, + pDev, + pDev->RegIOBuffers[i].Buffer, + AR6K_REG_IO_BUFFER_SIZE, + 0); /* don't care */ + AR6KFreeIOPacket(pDev,pIOPacket); + } + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (status != A_OK) { + A_ASSERT(FALSE); + break; + } + + /* note: we actually get the block size of a mailbox other than 0, for SDIO the block + * size on mailbox 0 is artificially set to 1. So we use the block size that is set + * for the other 3 mailboxes */ + pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE]; + /* must be a power of 2 */ + A_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0); + + /* assemble mask, used for padding to a block */ + pDev->BlockMask = pDev->BlockSize - 1; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n", + pDev->BlockSize, pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX])); + + pDev->GetPendingEventsFunc = NULL; + /* see if the HIF layer implements the get pending events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + &pDev->GetPendingEventsFunc, + sizeof(pDev->GetPendingEventsFunc)); + + /* assume we can process HIF interrupt events asynchronously */ + pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC; + + /* see if the HIF layer overrides this assumption */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_IRQ_PROC_MODE, + &pDev->HifIRQProcessingMode, + sizeof(pDev->HifIRQProcessingMode)); + + switch (pDev->HifIRQProcessingMode) { + case HIF_DEVICE_IRQ_SYNC_ONLY: + AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("HIF Interrupt processing is SYNC ONLY\n")); + /* see if HIF layer wants HTC to yield */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_IRQ_YIELD_PARAMS, + &pDev->HifIRQYieldParams, + sizeof(pDev->HifIRQYieldParams)); + + if (pDev->HifIRQYieldParams.RecvPacketYieldCount > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + ("HIF requests that DSR yield per %d RECV packets \n", + pDev->HifIRQYieldParams.RecvPacketYieldCount)); + pDev->DSRCanYield = TRUE; + } + break; + case HIF_DEVICE_IRQ_ASYNC_SYNC: + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n")); + break; + default: + A_ASSERT(FALSE); + } + + pDev->HifMaskUmaskRecvEvent = NULL; + + /* see if the HIF layer implements the mask/unmask recv events function */ + HIFConfigureDevice(pDev->HIFDevice, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + &pDev->HifMaskUmaskRecvEvent, + sizeof(pDev->HifMaskUmaskRecvEvent)); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n", + (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent)); + + status = DevDisableInterrupts(pDev); + + if (A_FAILED(status)) { + break; + } + + status = DevSetupGMbox(pDev); + + } while (FALSE); + + if (A_FAILED(status)) { + if (pDev->HifAttached) { + HIFDetachHTC(pDev->HIFDevice); + pDev->HifAttached = FALSE; + } + } + + return status; + +} + +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev) +{ + A_STATUS status; + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + + /* Enable all the interrupts except for the internal AR6000 CPU interrupt */ + pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) | + INT_STATUS_ENABLE_CPU_SET(0x01) | + INT_STATUS_ENABLE_COUNTER_SET(0x01); + + if (NULL == pDev->GetPendingEventsFunc) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + /* The HIF layer provided us with a pending events function which means that + * the detection of pending mbox messages is handled in the HIF layer. + * This is the case for the SPI2 interface. + * In the normal case we enable MBOX interrupts, for the case + * with HIFs that offer this mechanism, we keep these interrupts + * masked */ + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + + /* Set up the CPU Interrupt Status Register */ + pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00); + + /* Set up the Error Interrupt Status Register */ + pDev->IrqEnableRegisters.error_status_enable = + ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) | + ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01); + + /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */ + pDev->IrqEnableRegisters.counter_int_status_enable = + COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK); + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + + /* always synchronous */ + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + /* Can't write it for some reason */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to update interrupt control registers err: %d\n", status)); + + } + + return status; +} + +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev) +{ + AR6K_IRQ_ENABLE_REGISTERS regs; + + LOCK_AR6K(pDev); + /* Disable all interrupts */ + pDev->IrqEnableRegisters.int_status_enable = 0; + pDev->IrqEnableRegisters.cpu_int_status_enable = 0; + pDev->IrqEnableRegisters.error_status_enable = 0; + pDev->IrqEnableRegisters.counter_int_status_enable = 0; + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + + /* always synchronous */ + return HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); +} + +/* enable device interrupts */ +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev) +{ + /* for good measure, make sure interrupt are disabled before unmasking at the HIF + * layer. + * The rationale here is that between device insertion (where we clear the interrupts the first time) + * and when HTC is finally ready to handle interrupts, other software can perform target "soft" resets. + * The AR6K interrupt enables reset back to an "enabled" state when this happens. + * */ + DevDisableInterrupts(pDev); + + /* Unmask the host controller interrupts */ + HIFUnMaskInterrupt(pDev->HIFDevice); + + return DevEnableInterrupts(pDev); +} + +/* disable all device interrupts */ +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev) +{ + /* mask the interrupt at the HIF layer, we don't want a stray interrupt taken while + * we zero out our shadow registers in DevDisableInterrupts()*/ + HIFMaskInterrupt(pDev->HIFDevice); + + return DevDisableInterrupts(pDev); +} + +/* callback when our fetch to enable/disable completes */ +static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Failed to disable receiver, status:%d \n", pPacket->Status)); + } + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n")); +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "override" method when the HIF reports another methods to + * disable recv events */ +static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n", + EnableRecv,AsyncMode)); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + A_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* call the HIF layer override and do this asynchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice, + EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + +/* disable packet reception (used in case the host runs out of buffers) + * this is the "normal" method using the interrupt enable registers through + * the host I/F */ +static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + AR6K_IRQ_ENABLE_REGISTERS regs; + + /* take the lock to protect interrupt enable shadows */ + LOCK_AR6K(pDev); + + if (EnableRecv) { + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } else { + pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01); + } + + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + UNLOCK_AR6K(pDev); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + A_ASSERT(FALSE); + break; + } + + /* copy values to write to our async I/O buffer */ + A_MEMCPY(pIOPacket->pBuffer,®s,AR6K_IRQ_ENABLE_REGS_SIZE); + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler; + pIOPacket->pContext = pDev; + + /* write it out asynchronously */ + HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_ASYNC_BYTE_INC, + pIOPacket); + break; + } + + /* if we get here we are doing it synchronously */ + + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + + } while (FALSE); + + if (A_FAILED(status) && (pIOPacket != NULL)) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + + +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode); + } +} + +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode) +{ + if (NULL == pDev->HifMaskUmaskRecvEvent) { + return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode); + } else { + return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode); + } +} + +void DevDumpRegisters(AR6K_DEVICE *pDev, + AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("\n<------- Register Table -------->\n")); + + if (pIrqProcRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Host Int Status: 0x%x\n",pIrqProcRegs->host_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("CPU Int Status: 0x%x\n",pIrqProcRegs->cpu_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Error Int Status: 0x%x\n",pIrqProcRegs->error_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Counter Int Status: 0x%x\n",pIrqProcRegs->counter_int_status)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Mbox Frame: 0x%x\n",pIrqProcRegs->mbox_frame)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Rx Lookahead Valid: 0x%x\n",pIrqProcRegs->rx_lookahead_valid)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Rx Lookahead 0: 0x%x\n",pIrqProcRegs->rx_lookahead[0])); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Rx Lookahead 1: 0x%x\n",pIrqProcRegs->rx_lookahead[1])); + + if (pDev->MailBoxInfo.GMboxAddress != 0) { + /* if the target supports GMBOX hardware, dump some additional state */ + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("GMBOX Host Int Status 2: 0x%x\n",pIrqProcRegs->host_int_status2)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("GMBOX RX Avail: 0x%x\n",pIrqProcRegs->gmbox_rx_avail)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("GMBOX lookahead alias 0: 0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[0])); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("GMBOX lookahead alias 1: 0x%x\n",pIrqProcRegs->rx_gmbox_lookahead_alias[1])); + } + + } + + if (pIrqEnableRegs != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Int Status Enable: 0x%x\n",pIrqEnableRegs->int_status_enable)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable)); + } + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------->\n")); +} + + +#define DEV_GET_VIRT_DMA_INFO(p) ((DEV_SCATTER_DMA_VIRTUAL_INFO *)((p)->HIFPrivate[0])) + +static HIF_SCATTER_REQ *DevAllocScatterReq(HIF_DEVICE *Context) +{ + DL_LIST *pItem; + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + LOCK_AR6K(pDev); + pItem = DL_ListRemoveItemFromHead(&pDev->ScatterReqHead); + UNLOCK_AR6K(pDev); + if (pItem != NULL) { + return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink); + } + return NULL; +} + +static void DevFreeScatterReq(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + LOCK_AR6K(pDev); + DL_ListInsertTail(&pDev->ScatterReqHead, &pReq->ListLink); + UNLOCK_AR6K(pDev); +} + +A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA) +{ + A_UINT8 *pDMABuffer = NULL; + int i, remaining; + A_UINT32 length; + + pDMABuffer = pReq->pScatterBounceBuffer; + + if (pDMABuffer == NULL) { + A_ASSERT(FALSE); + return A_EINVAL; + } + + remaining = (int)pReq->TotalLength; + + for (i = 0; i < pReq->ValidScatterEntries; i++) { + + length = min((int)pReq->ScatterList[i].Length, remaining); + + if (length != (int)pReq->ScatterList[i].Length) { + A_ASSERT(FALSE); + /* there is a problem with the scatter list */ + return A_EINVAL; + } + + if (FromDMA) { + /* from DMA buffer */ + A_MEMCPY(pReq->ScatterList[i].pBuffer, pDMABuffer , length); + } else { + /* to DMA buffer */ + A_MEMCPY(pDMABuffer, pReq->ScatterList[i].pBuffer, length); + } + + pDMABuffer += length; + remaining -= length; + } + + return A_OK; +} + +static void DevReadWriteScatterAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + HIF_SCATTER_REQ *pReq = (HIF_SCATTER_REQ *)pPacket->pPktContext; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevReadWriteScatterAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + pReq->CompletionStatus = pPacket->Status; + + AR6KFreeIOPacket(pDev,pPacket); + + pReq->CompletionRoutine(pReq); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevReadWriteScatterAsyncHandler \n")); +} + +static A_STATUS DevReadWriteScatter(HIF_DEVICE *Context, HIF_SCATTER_REQ *pReq) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + A_UINT32 request = pReq->Request; + + do { + + if (pReq->TotalLength > AR6K_MAX_TRANSFER_SIZE_PER_SCATTER) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Invalid length: %d \n", pReq->TotalLength)); + break; + } + + if (pReq->TotalLength == 0) { + A_ASSERT(FALSE); + break; + } + + if (request & HIF_ASYNCHRONOUS) { + /* use an I/O packet to carry this request */ + pIOPacket = AR6KAllocIOPacket(pDev); + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + break; + } + + /* save the request */ + pIOPacket->pPktContext = pReq; + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevReadWriteScatterAsyncHandler; + pIOPacket->pContext = pDev; + } + + if (request & HIF_WRITE) { + /* in virtual DMA, we are issuing the requests through the legacy HIFReadWrite API + * this API will adjust the address automatically for the last byte to fall on the mailbox + * EOM. */ + + /* if the address is an extended address, we can adjust the address here since the extended + * address will bypass the normal checks in legacy HIF layers */ + if (pReq->Address == pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress) { + pReq->Address += pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize - pReq->TotalLength; + } + } + + /* use legacy readwrite */ + status = HIFReadWrite(pDev->HIFDevice, + pReq->Address, + DEV_GET_VIRT_DMA_INFO(pReq)->pVirtDmaBuffer, + pReq->TotalLength, + request, + (request & HIF_ASYNCHRONOUS) ? pIOPacket : NULL); + + } while (FALSE); + + if ((status != A_PENDING) && A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) { + if (pIOPacket != NULL) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + pReq->CompletionStatus = status; + pReq->CompletionRoutine(pReq); + status = A_OK; + } + + return status; +} + + +static void DevCleanupVirtualScatterSupport(AR6K_DEVICE *pDev) +{ + HIF_SCATTER_REQ *pReq; + + while (1) { + pReq = DevAllocScatterReq((HIF_DEVICE *)pDev); + if (NULL == pReq) { + break; + } + A_FREE(pReq); + } + +} + + /* function to set up virtual scatter support if HIF layer has not implemented the interface */ +static A_STATUS DevSetupVirtualScatterSupport(AR6K_DEVICE *pDev) +{ + A_STATUS status = A_OK; + int bufferSize, sgreqSize; + int i; + DEV_SCATTER_DMA_VIRTUAL_INFO *pVirtualInfo; + HIF_SCATTER_REQ *pReq; + + bufferSize = sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO) + + 2 * (A_GET_CACHE_LINE_BYTES()) + AR6K_MAX_TRANSFER_SIZE_PER_SCATTER; + + sgreqSize = sizeof(HIF_SCATTER_REQ) + + (AR6K_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM)); + + for (i = 0; i < AR6K_SCATTER_REQS; i++) { + /* allocate the scatter request, buffer info and the actual virtual buffer itself */ + pReq = (HIF_SCATTER_REQ *)A_MALLOC(sgreqSize + bufferSize); + + if (NULL == pReq) { + status = A_NO_MEMORY; + break; + } + + A_MEMZERO(pReq, sgreqSize); + + /* the virtual DMA starts after the scatter request struct */ + pVirtualInfo = (DEV_SCATTER_DMA_VIRTUAL_INFO *)((A_UINT8 *)pReq + sgreqSize); + A_MEMZERO(pVirtualInfo, sizeof(DEV_SCATTER_DMA_VIRTUAL_INFO)); + + pVirtualInfo->pVirtDmaBuffer = &pVirtualInfo->DataArea[0]; + /* align buffer to cache line in case host controller can actually DMA this */ + pVirtualInfo->pVirtDmaBuffer = A_ALIGN_TO_CACHE_LINE(pVirtualInfo->pVirtDmaBuffer); + /* store the structure in the private area */ + pReq->HIFPrivate[0] = pVirtualInfo; + /* we emulate a DMA bounce interface */ + pReq->ScatterMethod = HIF_SCATTER_DMA_BOUNCE; + pReq->pScatterBounceBuffer = pVirtualInfo->pVirtDmaBuffer; + /* free request to the list */ + DevFreeScatterReq((HIF_DEVICE *)pDev,pReq); + } + + if (A_FAILED(status)) { + DevCleanupVirtualScatterSupport(pDev); + } else { + pDev->HifScatterInfo.pAllocateReqFunc = DevAllocScatterReq; + pDev->HifScatterInfo.pFreeReqFunc = DevFreeScatterReq; + pDev->HifScatterInfo.pReadWriteScatterFunc = DevReadWriteScatter; + pDev->HifScatterInfo.MaxScatterEntries = AR6K_SCATTER_ENTRIES_PER_REQ; + pDev->HifScatterInfo.MaxTransferSizePerScatterReq = AR6K_MAX_TRANSFER_SIZE_PER_SCATTER; + pDev->ScatterIsVirtual = TRUE; + } + + return status; +} + + +A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer) +{ + A_STATUS status; + + if (pDev->MailBoxInfo.Flags & HIF_MBOX_FLAG_NO_BUNDLING) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HIF requires bundling disabled\n")); + return A_ENOTSUP; + } + + status = HIFConfigureDevice(pDev->HIFDevice, + HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT, + &pDev->HifScatterInfo, + sizeof(pDev->HifScatterInfo)); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + ("AR6K: ** HIF layer does not support scatter requests (%d) \n",status)); + + /* we can try to use a virtual DMA scatter mechanism using legacy HIFReadWrite() */ + status = DevSetupVirtualScatterSupport(pDev); + + if (A_SUCCESS(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("AR6K: virtual scatter transfers enabled (max scatter items:%d: maxlen:%d) \n", + DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev))); + } + + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("AR6K: HIF layer supports scatter requests (max scatter items:%d: maxlen:%d) \n", + DEV_GET_MAX_MSG_PER_BUNDLE(pDev), DEV_GET_MAX_BUNDLE_LENGTH(pDev))); + } + + if (A_SUCCESS(status)) { + /* for the recv path, the maximum number of bytes per recv bundle is just limited + * by the maximum transfer size at the HIF layer */ + pDev->MaxRecvBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq; + + /* for the send path, the max transfer size is limited by the existence and size of + * the extended mailbox address range */ + if (pDev->MailBoxInfo.MboxProp[0].ExtendedAddress != 0) { + pDev->MaxSendBundleSize = pDev->MailBoxInfo.MboxProp[0].ExtendedSize; + } else { + /* legacy */ + pDev->MaxSendBundleSize = AR6K_LEGACY_MAX_WRITE_LENGTH; + } + + if (pDev->MaxSendBundleSize > pDev->HifScatterInfo.MaxTransferSizePerScatterReq) { + /* limit send bundle size to what the HIF can support for scatter requests */ + pDev->MaxSendBundleSize = pDev->HifScatterInfo.MaxTransferSizePerScatterReq; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("AR6K: max recv: %d max send: %d \n", + DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev), DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev))); + + } + return status; +} + +A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async) +{ + A_STATUS status; + + if (Read) { + /* read operation */ + pScatterReq->Request = (Async) ? HIF_RD_ASYNC_BLOCK_FIX : HIF_RD_SYNC_BLOCK_FIX; + pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX]; + A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev)); + } else { + A_UINT32 mailboxWidth; + + /* write operation */ + pScatterReq->Request = (Async) ? HIF_WR_ASYNC_BLOCK_INC : HIF_WR_SYNC_BLOCK_INC; + A_ASSERT(pScatterReq->TotalLength <= (A_UINT32)DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev)); + if (pScatterReq->TotalLength > AR6K_LEGACY_MAX_WRITE_LENGTH) { + /* for large writes use the extended address */ + pScatterReq->Address = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedAddress; + mailboxWidth = pDev->MailBoxInfo.MboxProp[HTC_MAILBOX].ExtendedSize; + } else { + pScatterReq->Address = pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX]; + mailboxWidth = AR6K_LEGACY_MAX_WRITE_LENGTH; + } + + if (!pDev->ScatterIsVirtual) { + /* we are passing this scatter list down to the HIF layer' scatter request handler, fixup the address + * so that the last byte falls on the EOM, we do this for those HIFs that support the + * scatter API */ + pScatterReq->Address += (mailboxWidth - pScatterReq->TotalLength); + } + + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV | ATH_DEBUG_SEND, + ("DevSubmitScatterRequest, Entries: %d, Total Length: %d Mbox:0x%X (mode: %s : %s)\n", + pScatterReq->ValidScatterEntries, + pScatterReq->TotalLength, + pScatterReq->Address, + Async ? "ASYNC" : "SYNC", + (Read) ? "RD" : "WR")); + + status = DEV_PREPARE_SCATTER_OPERATION(pScatterReq); + + if (A_FAILED(status)) { + if (Async) { + pScatterReq->CompletionStatus = status; + pScatterReq->CompletionRoutine(pScatterReq); + return A_OK; + } + return status; + } + + status = pDev->HifScatterInfo.pReadWriteScatterFunc(pDev->ScatterIsVirtual ? pDev : pDev->HIFDevice, + pScatterReq); + if (!Async) { + /* in sync mode, we can touch the scatter request */ + pScatterReq->CompletionStatus = status; + DEV_FINISH_SCATTER_OPERATION(pScatterReq); + } else { + if (status == A_PENDING) { + status = A_OK; + } + } + + return status; +} + + +#ifdef MBOXHW_UNIT_TEST + + +/* This is a mailbox hardware unit test that must be called in a schedulable context + * This test is very simple, it will send a list of buffers with a counting pattern + * and the target will invert the data and send the message back + * + * the unit test has the following constraints: + * + * The target has at least 8 buffers of 256 bytes each. The host will send + * the following pattern of buffers in rapid succession : + * + * 1 buffer - 128 bytes + * 1 buffer - 256 bytes + * 1 buffer - 512 bytes + * 1 buffer - 1024 bytes + * + * The host will send the buffers to one mailbox and wait for buffers to be reflected + * back from the same mailbox. The target sends the buffers FIFO order. + * Once the final buffer has been received for a mailbox, the next mailbox is tested. + * + * + * Note: To simplifythe test , we assume that the chosen buffer sizes + * will fall on a nice block pad + * + * It is expected that higher-order tests will be written to stress the mailboxes using + * a message-based protocol (with some performance timming) that can create more + * randomness in the packets sent over mailboxes. + * + * */ + +#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1)) + +#define BUFFER_BLOCK_PAD 128 + +#if 0 +#define BUFFER1 128 +#define BUFFER2 256 +#define BUFFER3 512 +#define BUFFER4 1024 +#endif + +#if 1 +#define BUFFER1 80 +#define BUFFER2 200 +#define BUFFER3 444 +#define BUFFER4 800 +#endif + +#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \ + A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) ) + +#define TEST_BYTES (BUFFER1 + BUFFER2 + BUFFER3 + BUFFER4) + +#define TEST_CREDITS_RECV_TIMEOUT 100 + +static A_UINT8 g_Buffer[TOTAL_BYTES]; +static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES]; +static A_UINT32 g_BlockSizes[AR6K_MAILBOXES]; + +#define BUFFER_PROC_LIST_DEPTH 4 + +typedef struct _BUFFER_PROC_LIST{ + A_UINT8 *pBuffer; + A_UINT32 length; +}BUFFER_PROC_LIST; + + +#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \ +{ \ + (pList)->pBuffer = (pCurrpos); \ + (pList)->length = (len); \ + (pCurrpos) += (len); \ + (pList)++; \ +} + +/* a simple and crude way to send different "message" sizes */ +static void AssembleBufferList(BUFFER_PROC_LIST *pList) +{ + A_UINT8 *pBuffer = g_Buffer; + +#if BUFFER_PROC_LIST_DEPTH < 4 +#error "Buffer processing list depth is not deep enough!!" +#endif + + PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer); + PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer); + +} + +#define FILL_ZERO TRUE +#define FILL_COUNTING FALSE +static void InitBuffers(A_BOOL Zero) +{ + A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer; + int i; + + /* fill buffer with 16 bit counting pattern or zeros */ + for (i = 0; i < (TOTAL_BYTES / 2) ; i++) { + if (!Zero) { + pBuffer16[i] = (A_UINT16)i; + } else { + pBuffer16[i] = 0; + } + } +} + + +static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length) +{ + int i; + A_UINT16 startCount; + A_BOOL success = TRUE; + + /* get the starting count */ + startCount = pBuffer16[0]; + /* invert it, this is the expected value */ + startCount = ~startCount; + /* scan the buffer and verify */ + for (i = 0; i < (Length / 2) ; i++,startCount++) { + /* target will invert all the data */ + if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) { + success = FALSE; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n", + pBuffer16[i], ((A_UINT16)~startCount), i, Length)); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n", + pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3])); + break; + } + } + + return success; +} + +static A_BOOL CheckBuffers(void) +{ + int i; + A_BOOL success = TRUE; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* assemble the list */ + AssembleBufferList(checkList); + + /* scan the buffers and verify */ + for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) { + success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length); + if (!success) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n", + (A_UINT32)checkList[i].pBuffer, checkList[i].length)); + break; + } + } + + return success; +} + + /* find the end marker for the last buffer we will be sending */ +static A_UINT16 GetEndMarker(void) +{ + A_UINT8 *pBuffer; + BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH]; + + /* fill up buffers with the normal counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the list we will be sending down */ + AssembleBufferList(checkList); + /* point to the last 2 bytes of the last buffer */ + pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]); + + /* the last count in the last buffer is the marker */ + return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8); +} + +#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR + +/* send the ordered buffers to the target */ +static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_WR_SYNC_BLOCK_INC; + BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH]; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox)); + + /* fill buffer with counting pattern */ + InitBuffers(FILL_COUNTING); + + /* assemble the order in which we send */ + AssembleBufferList(sendList); + + for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) { + + /* we are doing block transfers, so we need to pad everything to a block size */ + paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + /* send each buffer synchronously */ + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + sendList[i].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + break; + } + totalBytes += sendList[i].length; + totalwPadding += paddedLength; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox)); + + return status; +} + +/* poll the mailbox credit counter until we get a credit or timeout */ +static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits) +{ + A_STATUS status = A_OK; + int timeout = TEST_CREDITS_RECV_TIMEOUT; + A_UINT8 credits = 0; + A_UINT32 address; + + while (TRUE) { + + /* Read the counter register to get credits, this auto-decrements */ + address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4; + status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits), + HIF_RD_SYNC_BYTE_FIX, NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Unable to decrement the command credit count register (mbox=%d)\n",mbox)); + status = A_ERROR; + break; + } + + if (credits) { + break; + } + + timeout--; + + if (timeout <= 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address)); + status = A_ERROR; + break; + } + + /* delay a little, target may not be ready */ + A_MDELAY(1000); + + } + + if (status == A_OK) { + *pCredits = credits; + } + + return status; +} + + +/* wait for the buffers to come back */ +static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status = A_OK; + A_UINT32 request = HIF_RD_SYNC_BLOCK_INC; + BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH]; + int curBuffer; + int credits; + int i; + int totalBytes = 0; + int paddedLength; + int totalwPadding = 0; + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox)); + + /* zero the buffers */ + InitBuffers(FILL_ZERO); + + /* assemble the order in which we should receive */ + AssembleBufferList(recvList); + + curBuffer = 0; + + while (curBuffer < BUFFER_PROC_LIST_DEPTH) { + + /* get number of buffers that have been completed, this blocks + * until we get at least 1 credit or it times out */ + status = GetCredits(pDev, mbox, &credits); + + if (status != A_OK) { + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox)); + + /* get all the buffers that are sitting on the queue */ + for (i = 0; i < credits; i++) { + A_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH); + /* recv the current buffer synchronously, the buffers should come back in + * order... with padding applied by the target */ + paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) & + (~(g_BlockSizes[mbox] - 1)); + + status = HIFReadWrite(pDev->HIFDevice, + g_MailboxAddrs[mbox], + recvList[curBuffer].pBuffer, + paddedLength, + request, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n", + recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox])); + break; + } + + totalwPadding += paddedLength; + totalBytes += recvList[curBuffer].length; + curBuffer++; + } + + if (status != A_OK) { + break; + } + /* go back and get some more */ + credits = 0; + } + + if (totalBytes != TEST_BYTES) { + A_ASSERT(FALSE); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n", + mbox, totalBytes, totalwPadding)); + } + + return status; + + +} + +static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox) +{ + A_STATUS status; + + do { + /* send out buffers */ + status = SendBuffers(pDev,mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* go get them, this will block */ + status = RecvBuffers(pDev, mbox); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox)); + break; + } + + /* check the returned data patterns */ + if (!CheckBuffers()) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox)); + status = A_ERROR; + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox)); + + } while (FALSE); + + return status; +} + +/* here is where the test starts */ +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev) +{ + int i; + A_STATUS status; + int credits = 0; + A_UINT8 params[4]; + int numBufs; + int bufferSize; + A_UINT16 temp; + + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n")); + + do { + /* get the addresses for all 4 mailboxes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR, + g_MailboxAddrs, sizeof(g_MailboxAddrs)); + + if (status != A_OK) { + A_ASSERT(FALSE); + break; + } + + /* get the block sizes */ + status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + g_BlockSizes, sizeof(g_BlockSizes)); + + if (status != A_OK) { + A_ASSERT(FALSE); + break; + } + + /* note, the HIF layer usually reports mbox 0 to have a block size of + * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes + * the same. */ + g_BlockSizes[0] = g_BlockSizes[1]; + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0])); + + if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n", + g_BlockSizes[1], BUFFER_BLOCK_PAD)); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n")); + + /* the target lets us know it is ready by giving us 1 credit on + * mailbox 0 */ + status = GetCredits(pDev, 0, &credits); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n")); + + /* read the first 4 scratch registers */ + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS, + params, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n")); + break; + } + + numBufs = params[0]; + bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]); + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, + ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n", + numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES)); + + if ((numBufs * bufferSize) < TOTAL_BYTES) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n", + TOTAL_BYTES, (numBufs*bufferSize))); + status = A_ERROR; + break; + } + + temp = GetEndMarker(); + + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 4, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp)); + + temp = (A_UINT16)g_BlockSizes[1]; + /* convert to a mask */ + temp = temp - 1; + status = HIFReadWrite(pDev->HIFDevice, + SCRATCH_ADDRESS + 6, + (A_UINT8 *)&temp, + 2, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp)); + + /* execute the test on each mailbox */ + for (i = 0; i < AR6K_MAILBOXES; i++) { + status = DoOneMboxHWTest(pDev, i); + if (status != A_OK) { + break; + } + } + + } while (FALSE); + + if (status == A_OK) { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n")); + } else { + AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n")); + } + /* don't let HTC_Start continue, the target is actually not running any HTC code */ + return A_ERROR; +} +#endif + + + diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h new file mode 100644 index 000000000000..b71ddb96cbde --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k.h @@ -0,0 +1,383 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K device layer that handles register level I/O +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef AR6K_H_ +#define AR6K_H_ + +#include "hci_transport_api.h" +#include "../htc_debug.h" + +#define AR6K_MAILBOXES 4 + +/* HTC runs over mailbox 0 */ +#define HTC_MAILBOX 0 + +#define AR6K_TARGET_DEBUG_INTR_MASK 0x01 + +#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \ + INT_STATUS_ENABLE_CPU_MASK | \ + INT_STATUS_ENABLE_COUNTER_MASK) + + +//#define MBOXHW_UNIT_TEST 1 + +#include "athstartpack.h" +typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS { + A_UINT8 host_int_status; + A_UINT8 cpu_int_status; + A_UINT8 error_int_status; + A_UINT8 counter_int_status; + A_UINT8 mbox_frame; + A_UINT8 rx_lookahead_valid; + A_UINT8 host_int_status2; + A_UINT8 gmbox_rx_avail; + A_UINT32 rx_lookahead[2]; + A_UINT32 rx_gmbox_lookahead_alias[2]; +} POSTPACK AR6K_IRQ_PROC_REGISTERS; + +#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS) + +typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS { + A_UINT8 int_status_enable; + A_UINT8 cpu_int_status_enable; + A_UINT8 error_status_enable; + A_UINT8 counter_int_status_enable; +} POSTPACK AR6K_IRQ_ENABLE_REGISTERS; + +typedef PREPACK struct _AR6K_GMBOX_CTRL_REGISTERS { + A_UINT8 int_status_enable; +} POSTPACK AR6K_GMBOX_CTRL_REGISTERS; + +#include "athendpack.h" + +#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS) + +#define AR6K_REG_IO_BUFFER_SIZE 32 +#define AR6K_MAX_REG_IO_BUFFERS 8 +#define FROM_DMA_BUFFER TRUE +#define TO_DMA_BUFFER FALSE +#define AR6K_SCATTER_ENTRIES_PER_REQ 16 +#define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024 +#define AR6K_SCATTER_REQS 4 +#define AR6K_LEGACY_MAX_WRITE_LENGTH 2048 + +/* buffers for ASYNC I/O */ +typedef struct AR6K_ASYNC_REG_IO_BUFFER { + HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */ + A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; +} AR6K_ASYNC_REG_IO_BUFFER; + +typedef struct _AR6K_GMBOX_INFO { + void *pProtocolContext; + A_STATUS (*pMessagePendingCallBack)(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes); + A_STATUS (*pCreditsPendingCallback)(void *pContext, int NumCredits, A_BOOL CreditIRQEnabled); + void (*pTargetFailureCallback)(void *pContext, A_STATUS Status); + void (*pStateDumpCallback)(void *pContext); + A_BOOL CreditCountIRQEnabled; +} AR6K_GMBOX_INFO; + +typedef struct _AR6K_DEVICE { + A_MUTEX_T Lock; + AR6K_IRQ_PROC_REGISTERS IrqProcRegisters; + AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; + void *HIFDevice; + A_UINT32 BlockSize; + A_UINT32 BlockMask; + HIF_DEVICE_MBOX_INFO MailBoxInfo; + HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc; + void *HTCContext; + HTC_PACKET_QUEUE RegisterIOList; + AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS]; + void (*TargetFailureCallback)(void *Context); + A_STATUS (*MessagePendingCallback)(void *Context, + A_UINT32 LookAheads[], + int NumLookAheads, + A_BOOL *pAsyncProc, + int *pNumPktsFetched); + HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode; + HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent; + A_BOOL HifAttached; + HIF_DEVICE_IRQ_YIELD_PARAMS HifIRQYieldParams; + A_BOOL DSRCanYield; + int CurrentDSRRecvCount; + HIF_DEVICE_SCATTER_SUPPORT_INFO HifScatterInfo; + DL_LIST ScatterReqHead; + A_BOOL ScatterIsVirtual; + int MaxRecvBundleSize; + int MaxSendBundleSize; + AR6K_GMBOX_INFO GMboxInfo; + A_BOOL GMboxEnabled; + AR6K_GMBOX_CTRL_REGISTERS GMboxControlRegisters; + int RecheckIRQStatusCnt; +} AR6K_DEVICE; + +#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock); +#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock); +#define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1 /* note: no need to lock this, it only gets set */ + +A_STATUS DevSetup(AR6K_DEVICE *pDev); +void DevCleanup(AR6K_DEVICE *pDev); +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS); +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status); +A_STATUS DevDsrHandler(void *context); +A_STATUS DevCheckPendingRecvMsgsAsync(void *context); +void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev); +void DevDumpRegisters(AR6K_DEVICE *pDev, + AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs, + AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs); + +#define DEV_STOP_RECV_ASYNC TRUE +#define DEV_STOP_RECV_SYNC FALSE +#define DEV_ENABLE_RECV_ASYNC TRUE +#define DEV_ENABLE_RECV_SYNC FALSE +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); +A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); +A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); + + +#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask))) +#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length) +#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0) + +static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) { + A_UINT32 paddedLength; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + A_STATUS status; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, SendLength); + +#if 0 + if (paddedLength > pPacket->BufferLength) { + A_ASSERT(FALSE); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + return A_OK; + } + return A_EINVAL; + } +#endif + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n", + paddedLength, + pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX], + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX], + pPacket->pBuffer, + paddedLength, /* the padded length */ + sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } else { + if (status == A_PENDING) { + status = A_OK; + } + } + + return status; +} + +static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) { + A_UINT32 paddedLength; + A_STATUS status; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, RecvLength); + + if (paddedLength > pPacket->BufferLength) { + A_ASSERT(FALSE); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n", + paddedLength,RecvLength,pPacket->BufferLength)); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + return A_OK; + } + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("DevRecvPacket (0x%X : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n", + (A_UINT32)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr, + paddedLength, + pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX], + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX], + pPacket->pBuffer, + paddedLength, + sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + +#define DEV_CHECK_RECV_YIELD(pDev) \ + ((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount) + +#define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode) +#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY) + +/**************************************************/ +/****** Scatter Function and Definitions + * + * + */ + +A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA); + + /* copy any READ data back into scatter list */ +#define DEV_FINISH_SCATTER_OPERATION(pR) \ + if (A_SUCCESS((pR)->CompletionStatus) && \ + !((pR)->Request & HIF_WRITE) && \ + ((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) { \ + (pR)->CompletionStatus = DevCopyScatterListToFromDMABuffer((pR),FROM_DMA_BUFFER); \ + } + + /* copy any WRITE data to bounce buffer */ +static INLINE A_STATUS DEV_PREPARE_SCATTER_OPERATION(HIF_SCATTER_REQ *pReq) { + if ((pReq->Request & HIF_WRITE) && (pReq->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) { + return DevCopyScatterListToFromDMABuffer(pReq,TO_DMA_BUFFER); + } else { + return A_OK; + } +} + + +A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer); + +#define DEV_GET_MAX_MSG_PER_BUNDLE(pDev) (pDev)->HifScatterInfo.MaxScatterEntries +#define DEV_GET_MAX_BUNDLE_LENGTH(pDev) (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq +#define DEV_ALLOC_SCATTER_REQ(pDev) \ + (pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice) + +#define DEV_FREE_SCATTER_REQ(pDev,pR) \ + (pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR)) + +#define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev) (pDev)->MaxRecvBundleSize +#define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev) (pDev)->MaxSendBundleSize + +#define DEV_SCATTER_READ TRUE +#define DEV_SCATTER_WRITE FALSE +#define DEV_SCATTER_ASYNC TRUE +#define DEV_SCATTER_SYNC FALSE +A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async); + +#ifdef MBOXHW_UNIT_TEST +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev); +#endif + + /* completely virtual */ +typedef struct _DEV_SCATTER_DMA_VIRTUAL_INFO { + A_UINT8 *pVirtDmaBuffer; /* dma-able buffer - CPU accessible address */ + A_UINT8 DataArea[1]; /* start of data area */ +} DEV_SCATTER_DMA_VIRTUAL_INFO; + + + +void DumpAR6KDevState(AR6K_DEVICE *pDev); + +/**************************************************/ +/****** GMBOX functions and definitions + * + * + */ + +#ifdef ATH_AR6K_ENABLE_GMBOX + +void DevCleanupGMbox(AR6K_DEVICE *pDev); +A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev); +A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev); +void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev); + +#else + + /* compiled out */ +#define DevCleanupGMbox(p) +#define DevCheckGMboxInterrupts(p) A_OK +#define DevNotifyGMboxTargetFailure(p) + +static INLINE A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev) { + pDev->GMboxEnabled = FALSE; + return A_OK; +} + +#endif + +#ifdef ATH_AR6K_ENABLE_GMBOX + + /* GMBOX protocol modules must expose each of these internal APIs */ +HCI_TRANSPORT_HANDLE GMboxAttachProtocol(AR6K_DEVICE *pDev, HCI_TRANSPORT_CONFIG_INFO *pInfo); +A_STATUS GMboxProtocolInstall(AR6K_DEVICE *pDev); +void GMboxProtocolUninstall(AR6K_DEVICE *pDev); + + /* API used by GMBOX protocol modules */ +AR6K_DEVICE *HTCGetAR6KDevice(void *HTCHandle); +#define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \ +{ \ + (pDev)->GMboxInfo.pProtocolContext = (context); \ + (pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback); \ + (pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \ + (pDev)->GMboxInfo.pTargetFailureCallback = (failure); \ + (pDev)->GMboxInfo.pStateDumpCallback = (statedump); \ +} + +#define DEV_GMBOX_GET_PROTOCOL(pDev) (pDev)->GMboxInfo.pProtocolContext + +A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength); +A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength); + +#define PROC_IO_ASYNC TRUE +#define PROC_IO_SYNC FALSE +typedef enum GMBOX_IRQ_ACTION_TYPE { + GMBOX_ACTION_NONE = 0, + GMBOX_DISABLE_ALL, + GMBOX_ERRORS_IRQ_ENABLE, + GMBOX_RECV_IRQ_ENABLE, + GMBOX_RECV_IRQ_DISABLE, + GMBOX_CREDIT_IRQ_ENABLE, + GMBOX_CREDIT_IRQ_DISABLE, +} GMBOX_IRQ_ACTION_TYPE; + +A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE, A_BOOL AsyncMode); +A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits); +A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize); +A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes); +A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int SignalNumber, int AckTimeoutMS); + +#endif + +#endif /*AR6K_H_*/ diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c new file mode 100644 index 000000000000..178cbb3e2962 --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_events.c @@ -0,0 +1,762 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR6K Driver layer event handling (i.e. interrupts, message polling) +// +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "AR6002/hw2.0/hw/mbox_host_reg.h" +#include "a_osapi.h" +#include "../htc_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" + +extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket); +extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev); + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev); + +#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */ + +/* completion routine for ALL HIF layer async I/O */ +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status) +{ + HTC_PACKET *pPacket = (HTC_PACKET *)context; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("+DevRWCompletionHandler (Pkt:0x%X) , Status: %d \n", + (A_UINT32)pPacket, + status)); + + COMPLETE_HTC_PACKET(pPacket,status); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("-DevRWCompletionHandler\n")); + + return A_OK; +} + +/* mailbox recv message polling */ +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev, + A_UINT32 *pLookAhead, + int TimeoutMS) +{ + A_STATUS status = A_OK; + int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS; + + A_ASSERT(timeout > 0); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n")); + + while (TRUE) { + + if (pDev->GetPendingEventsFunc != NULL) { + + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events, do this + * synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + if (A_FAILED(status)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n")); + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) + { + /* there is a message available, the lookahead should be valid now */ + *pLookAhead = events.LookAhead; + + break; + } + } else { + + /* this is the standard HIF way.... */ + /* load the register table */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n")); + break; + } + + /* check for MBOX data and valid lookahead */ + if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) { + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) + { + /* mailbox has a message and the look ahead is valid */ + *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + break; + } + } + + } + + timeout--; + + if (timeout <= 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n")); + status = A_ERROR; + + /* check if the target asserted */ + if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + /* target signaled an assert, process this pending interrupt + * this will call the target failure handler */ + DevServiceDebugInterrupt(pDev); + } + + break; + } + + /* delay a little */ + A_MDELAY(DELAY_PER_INTERVAL_MS); + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n")); + + return status; +} + +static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 cpu_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n")); + cpu_int_status = pDev->IrqProcRegisters.cpu_int_status & + pDev->IrqEnableRegisters.cpu_int_status_enable; + A_ASSERT(cpu_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", + cpu_int_status)); + + /* Clear the interrupt */ + pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = cpu_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + CPU_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + A_ASSERT(status == A_OK); + return status; +} + + +static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev) +{ + A_STATUS status; + A_UINT8 error_int_status; + A_UINT8 regBuffer[4]; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n")); + error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F; + A_ASSERT(error_int_status); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", + error_int_status)); + + if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) { + /* Wakeup */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n")); + } + + if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) { + /* Rx Underflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n")); + } + + if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) { + /* Tx Overflow */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n")); + } + + /* Clear the interrupt */ + pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */ + + /* set up the register transfer buffer to hit the register 4 times , this is done + * to make the access 4-byte aligned to mitigate issues with host bus interconnects that + * restrict bus transfer lengths to be a multiple of 4-bytes */ + + /* set W1C value to clear the interrupt, this hits the register first */ + regBuffer[0] = error_int_status; + /* the remaining 4 values are set to zero which have no-effect */ + regBuffer[1] = 0; + regBuffer[2] = 0; + regBuffer[3] = 0; + + status = HIFReadWrite(pDev->HIFDevice, + ERROR_INT_STATUS_ADDRESS, + regBuffer, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + A_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT32 dummy; + A_STATUS status; + + /* Send a target failure event to the application */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n")); + + if (pDev->TargetFailureCallback != NULL) { + pDev->TargetFailureCallback(pDev->HTCContext); + } + + if (pDev->GMboxEnabled) { + DevNotifyGMboxTargetFailure(pDev); + } + + /* clear the interrupt , the debug error interrupt is + * counter 0 */ + /* read counter to clear interrupt */ + status = HIFReadWrite(pDev->HIFDevice, + COUNT_DEC_ADDRESS, + (A_UINT8 *)&dummy, + 4, + HIF_RD_SYNC_BYTE_INC, + NULL); + + A_ASSERT(status == A_OK); + return status; +} + +static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev) +{ + A_UINT8 counter_int_status; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n")); + + counter_int_status = pDev->IrqProcRegisters.counter_int_status & + pDev->IrqEnableRegisters.counter_int_status_enable; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", + counter_int_status)); + + /* Check if the debug interrupt is pending + * NOTE: other modules like GMBOX may use the counter interrupt for + * credit flow control on other counters, we only need to check for the debug assertion + * counter interrupt */ + if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) { + return DevServiceDebugInterrupt(pDev); + } + + return A_OK; +} + +/* callback when our fetch to get interrupt status registers completes */ +static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + A_UINT32 lookAhead = 0; + A_BOOL otherInts = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" GetEvents I/O request failed, status:%d \n", pPacket->Status)); + /* bail out, don't unmask HIF interrupt */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + /* the HIF layer collected the information for us */ + HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer; + if (pEvents->Events & HIF_RECV_MSG_AVAIL) { + lookAhead = pEvents->LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n")); + } + } + if (pEvents->Events & HIF_OTHER_EVENTS) { + otherInts = TRUE; + } + } else { + /* standard interrupt table handling.... */ + AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer; + A_UINT8 host_int_status; + + host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable; + + if (host_int_status & (1 << HTC_MAILBOX)) { + host_int_status &= ~(1 << HTC_MAILBOX); + if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pReg->rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n")); + } + } + } + + if (host_int_status) { + /* there are other interrupts to handle */ + otherInts = TRUE; + } + } + + if (otherInts || (lookAhead == 0)) { + /* if there are other interrupts to process, we cannot do this in the async handler so + * ack the interrupt which will cause our sync handler to run again + * if however there are no more messages, we can now ack the interrupt */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n", + otherInts, lookAhead)); + HIFAckInterrupt(pDev->HIFDevice); + } else { + int fetched = 0; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n", + lookAhead)); + /* lookahead is non-zero and there are no other interrupts to service, + * go get the next message */ + status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, NULL, &fetched); + + if (A_SUCCESS(status) && !fetched) { + /* HTC layer could not pull out messages due to lack of resources, stop IRQ processing */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("MessagePendingCallback did not pull any messages, force-ack \n")); + DevAsyncIrqProcessComplete(pDev); + } + } + + } while (FALSE); + + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n")); +} + +/* called by the HTC layer when it wants us to check if the device has any more pending + * recv messages, this starts off a series of async requests to read interrupt registers */ +A_STATUS DevCheckPendingRecvMsgsAsync(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket; + + /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can + * cause us to switch contexts */ + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev)); + + do { + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* break the async processing chain right here, no need to continue. + * The DevDsrHandler() will handle things in a loop when things are driven + * synchronously */ + break; + } + + /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake + * the target, if upper layers determine that we are in a low-throughput mode, we can + * rely on taking another interrupt rather than re-checking the status registers which can + * re-wake the target */ + if (pDev->RecheckIRQStatusCnt == 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, re-acking HIF interrupts\n")); + /* ack interrupt */ + HIFAckInterrupt(pDev->HIFDevice); + break; + } + + /* first allocate one of our HTC packets we created for async I/O + * we reuse HTC packet definitions so that we can use the completion mechanism + * in DevRWCompletionHandler() */ + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + /* there should be only 1 asynchronous request out at a time to read these registers + * so this should actually never happen */ + status = A_NO_MEMORY; + A_ASSERT(FALSE); + break; + } + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevGetEventAsyncHandler; + pIOPacket->pContext = pDev; + + if (pDev->GetPendingEventsFunc) { + /* HIF layer has it's own mechanism, pass the IO to it.. */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer, + pIOPacket); + + } else { + /* standard way, read the interrupt register table asynchronously again */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_ASYNC_BYTE_INC, + pIOPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n")); + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n")); + + return status; +} + +void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("DevAsyncIrqProcessComplete - forcing HIF IRQ ACK \n")); + HIFAckInterrupt(pDev->HIFDevice); +} + +/* process pending interrupts synchronously */ +static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing) +{ + A_STATUS status = A_OK; + A_UINT8 host_int_status = 0; + A_UINT32 lookAhead = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev)); + + /*** NOTE: the HIF implementation guarantees that the context of this call allows + * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that + * can block or switch thread/task ontexts. + * This is a fully schedulable context. + * */ + do { + + if (pDev->IrqEnableRegisters.int_status_enable == 0) { + /* interrupt enables have been cleared, do not try to process any pending interrupts that + * may result in more bus transactions. The target may be unresponsive at this + * point. */ + break; + } + + if (pDev->GetPendingEventsFunc != NULL) { + HIF_PENDING_EVENTS_INFO events; + + /* the HIF layer uses a special mechanism to get events + * get this synchronously */ + status = pDev->GetPendingEventsFunc(pDev->HIFDevice, + &events, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (events.Events & HIF_RECV_MSG_AVAIL) { + lookAhead = events.LookAhead; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n")); + } + } + + if (!(events.Events & HIF_OTHER_EVENTS) || + !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) { + /* no need to read the register table, no other interesting interrupts. + * Some interfaces (like SPI) can shadow interrupt sources without + * requiring the host to do a full table read */ + break; + } + + /* otherwise fall through and read the register table */ + } + + /* + * Read the first 28 bytes of the HTC register table. This will yield us + * the value of different int status registers and the lookahead + * registers. + * length = sizeof(int_status) + sizeof(cpu_int_status) + + * sizeof(error_int_status) + sizeof(counter_int_status) + + * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) + + * sizeof(hole) + sizeof(rx_lookahead) + + * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) + + * sizeof(error_status_enable) + + * sizeof(counter_int_status_enable); + * + */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&pDev->IrqProcRegisters, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) { + break; + } + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) { + DevDumpRegisters(pDev, + &pDev->IrqProcRegisters, + &pDev->IrqEnableRegisters); + } + + /* Update only those registers that are enabled */ + host_int_status = pDev->IrqProcRegisters.host_int_status & + pDev->IrqEnableRegisters.int_status_enable; + + if (NULL == pDev->GetPendingEventsFunc) { + /* only look at mailbox status if the HIF layer did not provide this function, + * on some HIF interfaces reading the RX lookahead is not valid to do */ + if (host_int_status & (1 << HTC_MAILBOX)) { + /* mask out pending mailbox value, we use "lookAhead" as the real flag for + * mailbox processing below */ + host_int_status &= ~(1 << HTC_MAILBOX); + if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) { + /* mailbox has a message and the look ahead is valid */ + lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX]; + if (0 == lookAhead) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n")); + } + } + } + } else { + /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/ + host_int_status &= ~(1 << HTC_MAILBOX); + } + + if (pDev->GMboxEnabled) { + /*call GMBOX layer to process any interrupts of interest */ + status = DevCheckGMboxInterrupts(pDev); + } + + } while (FALSE); + + + do { + + /* did the interrupt status fetches succeed? */ + if (A_FAILED(status)) { + break; + } + + if ((0 == host_int_status) && (0 == lookAhead)) { + /* nothing to process, the caller can use this to break out of a loop */ + *pDone = TRUE; + break; + } + + if (lookAhead != 0) { + int fetched = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead)); + /* Mailbox Interrupt, the HTC layer may issue async requests to empty the + * mailbox... + * When emptying the recv mailbox we use the async handler above called from the + * completion routine of the callers read request. This can improve performance + * by reducing context switching when we rapidly pull packets */ + status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, pASyncProcessing, &fetched); + if (A_FAILED(status)) { + break; + } + + if (!fetched) { + /* HTC could not pull any messages out due to lack of resources */ + /* force DSR handler to ack the interrupt */ + *pASyncProcessing = FALSE; + pDev->RecheckIRQStatusCnt = 0; + } + } + + /* now handle the rest of them */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n", + host_int_status)); + + if (HOST_INT_STATUS_CPU_GET(host_int_status)) { + /* CPU Interrupt */ + status = DevServiceCPUInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_ERROR_GET(host_int_status)) { + /* Error Interrupt */ + status = DevServiceErrorInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) { + /* Counter Interrupt */ + status = DevServiceCounterInterrupt(pDev); + if (A_FAILED(status)){ + break; + } + } + + } while (FALSE); + + /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake + * the target, if upper layers determine that we are in a low-throughput mode, we can + * rely on taking another interrupt rather than re-checking the status registers which can + * re-wake the target. + * + * NOTE : for host interfaces that use the special GetPendingEventsFunc, this optimization cannot + * be used due to possible side-effects. For example, SPI requires the host to drain all + * messages from the mailbox before exiting the ISR routine. */ + if (!(*pASyncProcessing) && (pDev->RecheckIRQStatusCnt == 0) && (pDev->GetPendingEventsFunc == NULL)) { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, forcing done \n")); + *pDone = TRUE; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n", + *pDone, *pASyncProcessing, status)); + + return status; +} + + +/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/ +A_STATUS DevDsrHandler(void *context) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)context; + A_STATUS status = A_OK; + A_BOOL done = FALSE; + A_BOOL asyncProc = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + /* reset the recv counter that tracks when we need to yield from the DSR */ + pDev->CurrentDSRRecvCount = 0; + /* reset counter used to flag a re-scan of IRQ status registers on the target */ + pDev->RecheckIRQStatusCnt = 0; + + while (!done) { + status = ProcessPendingIRQs(pDev, &done, &asyncProc); + if (A_FAILED(status)) { + break; + } + + if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) { + /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */ + asyncProc = FALSE; + /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers. + * this has a nice side effect of blocking us until all async read requests are completed. + * This behavior is required on some HIF implementations that do not allow ASYNC + * processing in interrupt handlers (like Windows CE) */ + + if (pDev->DSRCanYield && DEV_CHECK_RECV_YIELD(pDev)) { + /* ProcessPendingIRQs() pulled enough recv messages to satisfy the yield count, stop + * checking for more messages and return */ + break; + } + } + + if (asyncProc) { + /* the function performed some async I/O for performance, we + need to exit the ISR immediately, the check below will prevent the interrupt from being + Ack'd while we handle it asynchronously */ + break; + } + + } + + if (A_SUCCESS(status) && !asyncProc) { + /* Ack the interrupt only if : + * 1. we did not get any errors in processing interrupts + * 2. there are no outstanding async processing requests */ + if (pDev->DSRCanYield) { + /* if the DSR can yield do not ACK the interrupt, there could be more pending messages. + * The HIF layer must ACK the interrupt on behalf of HTC */ + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Yield in effect (cur RX count: %d) \n", pDev->CurrentDSRRecvCount)); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n")); + HIFAckInterrupt(pDev->HIFDevice); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n")); + return status; +} + +void DumpAR6KDevState(AR6K_DEVICE *pDev) +{ + A_STATUS status; + AR6K_IRQ_ENABLE_REGISTERS regs; + AR6K_IRQ_PROC_REGISTERS procRegs; + + LOCK_AR6K(pDev); + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + UNLOCK_AR6K(pDev); + + /* load the register table from the device */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&procRegs, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DumpAR6KDevState : Failed to read register table (%d) \n",status)); + return; + } + + DevDumpRegisters(pDev,&procRegs,®s); + + if (pDev->GMboxInfo.pStateDumpCallback != NULL) { + pDev->GMboxInfo.pStateDumpCallback(pDev->GMboxInfo.pProtocolContext); + } + + /* dump any bus state at the HIF layer */ + HIFConfigureDevice(pDev->HIFDevice,HIF_DEVICE_DEBUG_BUS_STATE,NULL,0); + +} + + diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c new file mode 100644 index 000000000000..f1408082a809 --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox.c @@ -0,0 +1,752 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Generic MBOX API implementation +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "../htc_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" +#include "hw/mbox_host_reg.h" +#include "gmboxif.h" + +/* + * This file provides management functions and a toolbox for GMBOX protocol modules. + * Only one protocol module can be installed at a time. The determination of which protocol + * module is installed is determined at compile time. + * + */ +#ifdef ATH_AR6K_ENABLE_GMBOX + /* GMBOX definitions */ +#define GMBOX_INT_STATUS_ENABLE_REG 0x488 +#define GMBOX_INT_STATUS_RX_DATA (1 << 0) +#define GMBOX_INT_STATUS_TX_OVERFLOW (1 << 1) +#define GMBOX_INT_STATUS_RX_OVERFLOW (1 << 2) + +#define GMBOX_LOOKAHEAD_MUX_REG 0x498 +#define GMBOX_LA_MUX_OVERRIDE_2_3 (1 << 0) + +#define AR6K_GMBOX_CREDIT_DEC_ADDRESS (COUNT_DEC_ADDRESS + 4 * AR6K_GMBOX_CREDIT_COUNTER) +#define AR6K_GMBOX_CREDIT_SIZE_ADDRESS (COUNT_ADDRESS + AR6K_GMBOX_CREDIT_SIZE_COUNTER) + + + /* external APIs for allocating and freeing internal I/O packets to handle ASYNC I/O */ +extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket); +extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev); + + +/* callback when our fetch to enable/disable completes */ +static void DevGMboxIRQActionAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxIRQActionAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("IRQAction Operation (%d) failed! status:%d \n", pPacket->PktInfo.AsRx.HTCRxFlags,pPacket->Status)); + } + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxIRQActionAsyncHandler \n")); +} + +static A_STATUS DevGMboxCounterEnableDisable(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + AR6K_IRQ_ENABLE_REGISTERS regs; + HTC_PACKET *pIOPacket = NULL; + + LOCK_AR6K(pDev); + + if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) { + pDev->GMboxInfo.CreditCountIRQEnabled = TRUE; + pDev->IrqEnableRegisters.counter_int_status_enable |= + COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER); + pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_COUNTER_SET(0x01); + } else { + pDev->GMboxInfo.CreditCountIRQEnabled = FALSE; + pDev->IrqEnableRegisters.counter_int_status_enable &= + ~(COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER)); + } + /* copy into our temp area */ + A_MEMCPY(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + UNLOCK_AR6K(pDev); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + A_ASSERT(FALSE); + break; + } + + /* copy values to write to our async I/O buffer */ + A_MEMCPY(pIOPacket->pBuffer,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE); + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevGMboxIRQActionAsyncHandler; + pIOPacket->pContext = pDev; + pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction; + /* write it out asynchronously */ + HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + pIOPacket->pBuffer, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_ASYNC_BYTE_INC, + pIOPacket); + + pIOPacket = NULL; + break; + } + + /* if we get here we are doing it synchronously */ + status = HIFReadWrite(pDev->HIFDevice, + INT_STATUS_ENABLE_ADDRESS, + ®s.int_status_enable, + AR6K_IRQ_ENABLE_REGS_SIZE, + HIF_WR_SYNC_BYTE_INC, + NULL); + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status)); + } else { + if (!AsyncMode) { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" IRQAction Operation (%d) success \n", IrqAction)); + } + } + + if (pIOPacket != NULL) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + + +A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + A_UINT8 GMboxIntControl[4]; + + if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) { + return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_ENABLE, AsyncMode); + } else if(GMBOX_CREDIT_IRQ_DISABLE == IrqAction) { + return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode); + } + + if (GMBOX_DISABLE_ALL == IrqAction) { + /* disable credit IRQ, those are on a different set of registers */ + DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode); + } + + /* take the lock to protect interrupt enable shadows */ + LOCK_AR6K(pDev); + + switch (IrqAction) { + + case GMBOX_DISABLE_ALL: + pDev->GMboxControlRegisters.int_status_enable = 0; + break; + case GMBOX_ERRORS_IRQ_ENABLE: + pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_TX_OVERFLOW | + GMBOX_INT_STATUS_RX_OVERFLOW; + break; + case GMBOX_RECV_IRQ_ENABLE: + pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_RX_DATA; + break; + case GMBOX_RECV_IRQ_DISABLE: + pDev->GMboxControlRegisters.int_status_enable &= ~GMBOX_INT_STATUS_RX_DATA; + break; + case GMBOX_ACTION_NONE: + default: + A_ASSERT(FALSE); + break; + } + + GMboxIntControl[0] = pDev->GMboxControlRegisters.int_status_enable; + GMboxIntControl[1] = GMboxIntControl[0]; + GMboxIntControl[2] = GMboxIntControl[0]; + GMboxIntControl[3] = GMboxIntControl[0]; + + UNLOCK_AR6K(pDev); + + do { + + if (AsyncMode) { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + A_ASSERT(FALSE); + break; + } + + /* copy values to write to our async I/O buffer */ + A_MEMCPY(pIOPacket->pBuffer,GMboxIntControl,sizeof(GMboxIntControl)); + + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevGMboxIRQActionAsyncHandler; + pIOPacket->pContext = pDev; + pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction; + /* write it out asynchronously */ + HIFReadWrite(pDev->HIFDevice, + GMBOX_INT_STATUS_ENABLE_REG, + pIOPacket->pBuffer, + sizeof(GMboxIntControl), + HIF_WR_ASYNC_BYTE_FIX, + pIOPacket); + pIOPacket = NULL; + break; + } + + /* if we get here we are doing it synchronously */ + + status = HIFReadWrite(pDev->HIFDevice, + GMBOX_INT_STATUS_ENABLE_REG, + GMboxIntControl, + sizeof(GMboxIntControl), + HIF_WR_SYNC_BYTE_FIX, + NULL); + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status)); + } else { + if (!AsyncMode) { + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, + (" IRQAction Operation (%d) success \n", IrqAction)); + } + } + + if (pIOPacket != NULL) { + AR6KFreeIOPacket(pDev,pIOPacket); + } + + return status; +} + +void DevCleanupGMbox(AR6K_DEVICE *pDev) +{ + if (pDev->GMboxEnabled) { + pDev->GMboxEnabled = FALSE; + GMboxProtocolUninstall(pDev); + } +} + +A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev) +{ + A_STATUS status = A_OK; + A_UINT8 muxControl[4]; + + do { + + if (0 == pDev->MailBoxInfo.GMboxAddress) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(" GMBOX Advertised: Address:0x%X , size:%d \n", + pDev->MailBoxInfo.GMboxAddress, pDev->MailBoxInfo.GMboxSize)); + + status = DevGMboxIRQAction(pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC); + + if (A_FAILED(status)) { + break; + } + + /* write to mailbox look ahead mux control register, we want the + * GMBOX lookaheads to appear on lookaheads 2 and 3 + * the register is 1-byte wide so we need to hit it 4 times to align the operation + * to 4-bytes */ + muxControl[0] = GMBOX_LA_MUX_OVERRIDE_2_3; + muxControl[1] = GMBOX_LA_MUX_OVERRIDE_2_3; + muxControl[2] = GMBOX_LA_MUX_OVERRIDE_2_3; + muxControl[3] = GMBOX_LA_MUX_OVERRIDE_2_3; + + status = HIFReadWrite(pDev->HIFDevice, + GMBOX_LOOKAHEAD_MUX_REG, + muxControl, + sizeof(muxControl), + HIF_WR_SYNC_BYTE_FIX, /* hit this register 4 times */ + NULL); + + if (A_FAILED(status)) { + break; + } + + status = GMboxProtocolInstall(pDev); + + if (A_FAILED(status)) { + break; + } + + pDev->GMboxEnabled = TRUE; + + } while (FALSE); + + return status; +} + +A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev) +{ + A_STATUS status = A_OK; + A_UINT8 counter_int_status; + int credits; + A_UINT8 host_int_status2; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("+DevCheckGMboxInterrupts \n")); + + /* the caller guarantees that this is a context that allows for blocking I/O */ + + do { + + host_int_status2 = pDev->IrqProcRegisters.host_int_status2 & + pDev->GMboxControlRegisters.int_status_enable; + + if (host_int_status2 & GMBOX_INT_STATUS_TX_OVERFLOW) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : TX Overflow \n")); + status = A_ECOMM; + } + + if (host_int_status2 & GMBOX_INT_STATUS_RX_OVERFLOW) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : RX Overflow \n")); + status = A_ECOMM; + } + + if (A_FAILED(status)) { + if (pDev->GMboxInfo.pTargetFailureCallback != NULL) { + pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, status); + } + break; + } + + if (host_int_status2 & GMBOX_INT_STATUS_RX_DATA) { + if (pDev->IrqProcRegisters.gmbox_rx_avail > 0) { + A_ASSERT(pDev->GMboxInfo.pMessagePendingCallBack != NULL); + status = pDev->GMboxInfo.pMessagePendingCallBack( + pDev->GMboxInfo.pProtocolContext, + (A_UINT8 *)&pDev->IrqProcRegisters.rx_gmbox_lookahead_alias[0], + pDev->IrqProcRegisters.gmbox_rx_avail); + } + } + + if (A_FAILED(status)) { + break; + } + + counter_int_status = pDev->IrqProcRegisters.counter_int_status & + pDev->IrqEnableRegisters.counter_int_status_enable; + + /* check if credit interrupt is pending */ + if (counter_int_status & (COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER))) { + + /* do synchronous read */ + status = DevGMboxReadCreditCounter(pDev, PROC_IO_SYNC, &credits); + + if (A_FAILED(status)) { + break; + } + + A_ASSERT(pDev->GMboxInfo.pCreditsPendingCallback != NULL); + status = pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext, + credits, + pDev->GMboxInfo.CreditCountIRQEnabled); + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("-DevCheckGMboxInterrupts (%d) \n",status)); + + return status; +} + + +A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength) +{ + A_UINT32 paddedLength; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + A_STATUS status; + A_UINT32 address; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, WriteLength); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("DevGMboxWrite, Padded Length: %d Mbox:0x%X (mode:%s)\n", + WriteLength, + pDev->MailBoxInfo.GMboxAddress, + sync ? "SYNC" : "ASYNC")); + + /* last byte of packet has to hit the EOM marker */ + address = pDev->MailBoxInfo.GMboxAddress + pDev->MailBoxInfo.GMboxSize - paddedLength; + + status = HIFReadWrite(pDev->HIFDevice, + address, + pPacket->pBuffer, + paddedLength, /* the padded length */ + sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } else { + if (status == A_PENDING) { + status = A_OK; + } + } + + return status; +} + +A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength) +{ + + A_UINT32 paddedLength; + A_STATUS status; + A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; + + /* adjust the length to be a multiple of block size if appropriate */ + paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, ReadLength); + + if (paddedLength > pPacket->BufferLength) { + A_ASSERT(FALSE); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevGMboxRead, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n", + paddedLength,ReadLength,pPacket->BufferLength)); + if (pPacket->Completion != NULL) { + COMPLETE_HTC_PACKET(pPacket,A_EINVAL); + return A_OK; + } + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("DevGMboxRead (0x%X : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n", + (A_UINT32)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr, + paddedLength, + pDev->MailBoxInfo.GMboxAddress, + sync ? "SYNC" : "ASYNC")); + + status = HIFReadWrite(pDev->HIFDevice, + pDev->MailBoxInfo.GMboxAddress, + pPacket->pBuffer, + paddedLength, + sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX, + sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */ + + if (sync) { + pPacket->Status = status; + } + + return status; +} + + +static int ProcessCreditCounterReadBuffer(A_UINT8 *pBuffer, int Length) +{ + int credits = 0; + + /* theory of how this works: + * We read the credit decrement register multiple times on a byte-wide basis. + * The number of times (32) aligns the I/O operation to be a multiple of 4 bytes and provides a + * reasonable chance to acquire "all" pending credits in a single I/O operation. + * + * Once we obtain the filled buffer, we can walk through it looking for credit decrement transitions. + * Each non-zero byte represents a single credit decrement (which is a credit given back to the host) + * For example if the target provides 3 credits and added 4 more during the 32-byte read operation the following + * pattern "could" appear: + * + * 0x3 0x2 0x1 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 ......rest zeros + * <---------> <-----------------------------> + * \_ credits aleady there \_ target adding 4 more credits + * + * The total available credits would be 7, since there are 7 non-zero bytes in the buffer. + * + * */ + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + DebugDumpBytes(pBuffer, Length, "GMBOX Credit read buffer"); + } + + while (Length) { + if (*pBuffer != 0) { + credits++; + } + Length--; + pBuffer++; + } + + return credits; +} + + +/* callback when our fetch to enable/disable completes */ +static void DevGMboxReadCreditsAsyncHandler(void *Context, HTC_PACKET *pPacket) +{ + AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context; + + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxReadCreditsAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev)); + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Read Credit Operation failed! status:%d \n", pPacket->Status)); + } else { + int credits = 0; + credits = ProcessCreditCounterReadBuffer(pPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE); + pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext, + credits, + pDev->GMboxInfo.CreditCountIRQEnabled); + + + } + /* free this IO packet */ + AR6KFreeIOPacket(pDev,pPacket); + AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxReadCreditsAsyncHandler \n")); +} + +A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits) +{ + A_STATUS status = A_OK; + HTC_PACKET *pIOPacket = NULL; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+DevGMboxReadCreditCounter (%s) \n", AsyncMode ? "ASYNC" : "SYNC")); + + do { + + pIOPacket = AR6KAllocIOPacket(pDev); + + if (NULL == pIOPacket) { + status = A_NO_MEMORY; + A_ASSERT(FALSE); + break; + } + + A_MEMZERO(pIOPacket->pBuffer,AR6K_REG_IO_BUFFER_SIZE); + + if (AsyncMode) { + /* stick in our completion routine when the I/O operation completes */ + pIOPacket->Completion = DevGMboxReadCreditsAsyncHandler; + pIOPacket->pContext = pDev; + /* read registers asynchronously */ + HIFReadWrite(pDev->HIFDevice, + AR6K_GMBOX_CREDIT_DEC_ADDRESS, + pIOPacket->pBuffer, + AR6K_REG_IO_BUFFER_SIZE, /* hit the register multiple times */ + HIF_RD_ASYNC_BYTE_FIX, + pIOPacket); + pIOPacket = NULL; + break; + } + + pIOPacket->Completion = NULL; + /* if we get here we are doing it synchronously */ + status = HIFReadWrite(pDev->HIFDevice, + AR6K_GMBOX_CREDIT_DEC_ADDRESS, + pIOPacket->pBuffer, + AR6K_REG_IO_BUFFER_SIZE, + HIF_RD_SYNC_BYTE_FIX, + NULL); + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" DevGMboxReadCreditCounter failed! status:%d \n", status)); + } + + if (pIOPacket != NULL) { + if (A_SUCCESS(status)) { + /* sync mode processing */ + *pCredits = ProcessCreditCounterReadBuffer(pIOPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE); + } + AR6KFreeIOPacket(pDev,pIOPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-DevGMboxReadCreditCounter (%s) (%d) \n", + AsyncMode ? "ASYNC" : "SYNC", status)); + + return status; +} + +A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize) +{ + A_STATUS status; + A_UINT8 buffer[4]; + + status = HIFReadWrite(pDev->HIFDevice, + AR6K_GMBOX_CREDIT_SIZE_ADDRESS, + buffer, + sizeof(buffer), + HIF_RD_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */ + NULL); + + if (A_SUCCESS(status)) { + if (buffer[0] == 0) { + *pCreditSize = 256; + } else { + *pCreditSize = buffer[0]; + } + + } + + return status; +} + +void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev) +{ + /* Target ASSERTED!!! */ + if (pDev->GMboxInfo.pTargetFailureCallback != NULL) { + pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, A_HARDWARE); + } +} + +A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes) +{ + + A_STATUS status = A_OK; + AR6K_IRQ_PROC_REGISTERS procRegs; + int maxCopy; + + do { + /* on entry the caller provides the length of the lookahead buffer */ + if (*pLookAheadBytes > sizeof(procRegs.rx_gmbox_lookahead_alias)) { + A_ASSERT(FALSE); + status = A_EINVAL; + break; + } + + maxCopy = *pLookAheadBytes; + *pLookAheadBytes = 0; + /* load the register table from the device */ + status = HIFReadWrite(pDev->HIFDevice, + HOST_INT_STATUS_ADDRESS, + (A_UINT8 *)&procRegs, + AR6K_IRQ_PROC_REGS_SIZE, + HIF_RD_SYNC_BYTE_INC, + NULL); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevGMboxRecvLookAheadPeek : Failed to read register table (%d) \n",status)); + break; + } + + if (procRegs.gmbox_rx_avail > 0) { + int bytes = procRegs.gmbox_rx_avail > maxCopy ? maxCopy : procRegs.gmbox_rx_avail; + A_MEMCPY(pLookAheadBuffer,&procRegs.rx_gmbox_lookahead_alias[0],bytes); + *pLookAheadBytes = bytes; + } + + } while (FALSE); + + return status; +} + +A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int Signal, int AckTimeoutMS) +{ + A_STATUS status = A_OK; + int i; + A_UINT8 buffer[4]; + + A_MEMZERO(buffer, sizeof(buffer)); + + do { + + if (Signal >= MBOX_SIG_HCI_BRIDGE_MAX) { + status = A_EINVAL; + break; + } + + /* set the last buffer to do the actual signal trigger */ + buffer[3] = (1 << Signal); + + status = HIFReadWrite(pDev->HIFDevice, + INT_WLAN_ADDRESS, + buffer, + sizeof(buffer), + HIF_WR_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */ + NULL); + + if (A_FAILED(status)) { + break; + } + + } while (FALSE); + + + if (A_SUCCESS(status)) { + /* now read back the register to see if the bit cleared */ + while (AckTimeoutMS) { + status = HIFReadWrite(pDev->HIFDevice, + INT_WLAN_ADDRESS, + buffer, + sizeof(buffer), + HIF_RD_SYNC_BYTE_FIX, + NULL); + + if (A_FAILED(status)) { + break; + } + + for (i = 0; i < sizeof(buffer); i++) { + if (buffer[i] & (1 << Signal)) { + /* bit is still set */ + break; + } + } + + if (i >= sizeof(buffer)) { + /* done */ + break; + } + + AckTimeoutMS--; + A_MDELAY(1); + } + + if (0 == AckTimeoutMS) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("DevGMboxSetTargetInterrupt : Ack Timed-out (sig:%d) \n",Signal)); + status = A_ERROR; + } + } + + return status; + +} + +#endif //ATH_AR6K_ENABLE_GMBOX + + + + diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c new file mode 100644 index 000000000000..ec5c1dc18ed2 --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c @@ -0,0 +1,1255 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Protocol module for use in bridging HCI-UART packets over the GMBOX interface +// +// Author(s): ="Atheros" +//============================================================================== +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "../htc_debug.h" +#include "hif.h" +#include "htc_packet.h" +#include "ar6k.h" +#include "hci_transport_api.h" +#include "gmboxif.h" +#include "ar6000_diag.h" +#include "hw/apb_map.h" +#include "hw/mbox_reg.h" + +#ifdef ATH_AR6K_ENABLE_GMBOX +#define HCI_UART_COMMAND_PKT 0x01 +#define HCI_UART_ACL_PKT 0x02 +#define HCI_UART_SCO_PKT 0x03 +#define HCI_UART_EVENT_PKT 0x04 + +#define HCI_RECV_WAIT_BUFFERS (1 << 0) + +#define HCI_SEND_WAIT_CREDITS (1 << 0) + +#define HCI_UART_BRIDGE_CREDIT_SIZE 128 + +#define CREDIT_POLL_COUNT 256 + +#define HCI_DELAY_PER_INTERVAL_MS 10 +#define BTON_TIMEOUT_MS 500 +#define BTOFF_TIMEOUT_MS 500 +#define BAUD_TIMEOUT_MS 1 + +typedef struct { + HCI_TRANSPORT_CONFIG_INFO HCIConfig; + A_BOOL HCIAttached; + A_BOOL HCIStopped; + A_UINT32 RecvStateFlags; + A_UINT32 SendStateFlags; + HCI_TRANSPORT_PACKET_TYPE WaitBufferType; + HTC_PACKET_QUEUE SendQueue; /* write queue holding HCI Command and ACL packets */ + HTC_PACKET_QUEUE HCIACLRecvBuffers; /* recv queue holding buffers for incomming ACL packets */ + HTC_PACKET_QUEUE HCIEventBuffers; /* recv queue holding buffers for incomming event packets */ + AR6K_DEVICE *pDev; + A_MUTEX_T HCIRxLock; + A_MUTEX_T HCITxLock; + int CreditsMax; + int CreditsConsumed; + int CreditsAvailable; + int CreditSize; + int CreditsCurrentSeek; + int SendProcessCount; +} GMBOX_PROTO_HCI_UART; + +#define LOCK_HCI_RX(t) A_MUTEX_LOCK(&(t)->HCIRxLock); +#define UNLOCK_HCI_RX(t) A_MUTEX_UNLOCK(&(t)->HCIRxLock); +#define LOCK_HCI_TX(t) A_MUTEX_LOCK(&(t)->HCITxLock); +#define UNLOCK_HCI_TX(t) A_MUTEX_UNLOCK(&(t)->HCITxLock); + +#define DO_HCI_RECV_INDICATION(p,pt) \ +{ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI: Indicate Recv on packet:0x%X status:%d len:%d type:%d \n", \ + (A_UINT32)(pt),(pt)->Status, A_SUCCESS((pt)->Status) ? (pt)->ActualLength : 0, HCI_GET_PACKET_TYPE(pt))); \ + (p)->HCIConfig.pHCIPktRecv((p)->HCIConfig.pContext, (pt)); \ +} + +#define DO_HCI_SEND_INDICATION(p,pt) \ +{ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Indicate Send on packet:0x%X status:%d type:%d \n", \ + (A_UINT32)(pt),(pt)->Status,HCI_GET_PACKET_TYPE(pt))); \ + (p)->HCIConfig.pHCISendComplete((p)->HCIConfig.pContext, (pt)); \ +} + +static A_STATUS HCITrySend(GMBOX_PROTO_HCI_UART *pProt, HTC_PACKET *pPacket, A_BOOL Synchronous); + +static void HCIUartCleanup(GMBOX_PROTO_HCI_UART *pProtocol) +{ + A_ASSERT(pProtocol != NULL); + + A_MUTEX_DELETE(&pProtocol->HCIRxLock); + A_MUTEX_DELETE(&pProtocol->HCITxLock); + + A_FREE(pProtocol); +} + +static A_STATUS InitTxCreditState(GMBOX_PROTO_HCI_UART *pProt) +{ + A_STATUS status; + int credits; + int creditPollCount = CREDIT_POLL_COUNT; + A_BOOL gotCredits = FALSE; + + pProt->CreditsConsumed = 0; + + do { + + if (pProt->CreditsMax != 0) { + /* we can only call this only once per target reset */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI: InitTxCreditState - already called! \n")); + A_ASSERT(FALSE); + status = A_EINVAL; + break; + } + + /* read the credit counter. At startup the target will set the credit counter + * to the max available, we read this in a loop because it may take + * multiple credit counter reads to get all credits */ + + while (creditPollCount) { + + credits = 0; + + status = DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_SYNC, &credits); + + if (A_FAILED(status)) { + break; + } + + if (!gotCredits && (0 == credits)) { + creditPollCount--; + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: credit is 0, retrying (%d) \n",creditPollCount)); + A_MDELAY(HCI_DELAY_PER_INTERVAL_MS); + continue; + } else { + gotCredits = TRUE; + } + + if (0 == credits) { + break; + } + + pProt->CreditsMax += credits; + } + + if (A_FAILED(status)) { + break; + } + + if (0 == creditPollCount) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("** HCI : Failed to get credits! GMBOX Target was not available \n")); + status = A_ERROR; + break; + } + + /* now get the size */ + status = DevGMboxReadCreditSize(pProt->pDev, &pProt->CreditSize); + + if (A_FAILED(status)) { + break; + } + + } while (FALSE); + + if (A_SUCCESS(status)) { + pProt->CreditsAvailable = pProt->CreditsMax; + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HCI : InitTxCreditState - credits avail: %d, size: %d \n", + pProt->CreditsAvailable, pProt->CreditSize)); + } + + return status; +} + +static A_STATUS CreditsAvailableCallback(void *pContext, int Credits, A_BOOL CreditIRQEnabled) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext; + A_BOOL enableCreditIrq = FALSE; + A_BOOL disableCreditIrq = FALSE; + A_BOOL doPendingSends = FALSE; + A_STATUS status = A_OK; + + /** this callback is called under 2 conditions: + * 1. The credit IRQ interrupt was enabled and signaled. + * 2. A credit counter read completed. + * + * The function must not assume that the calling context can block ! + */ + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+CreditsAvailableCallback (Credits:%d, IRQ:%s) \n", + Credits, CreditIRQEnabled ? "ON" : "OFF")); + + LOCK_HCI_RX(pProt); + + do { + + if (0 == Credits) { + if (!CreditIRQEnabled) { + /* enable credit IRQ */ + enableCreditIrq = TRUE; + } + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: current credit state, consumed:%d available:%d max:%d seek:%d\n", + pProt->CreditsConsumed, + pProt->CreditsAvailable, + pProt->CreditsMax, + pProt->CreditsCurrentSeek)); + + pProt->CreditsAvailable += Credits; + A_ASSERT(pProt->CreditsAvailable <= pProt->CreditsMax); + pProt->CreditsConsumed -= Credits; + A_ASSERT(pProt->CreditsConsumed >= 0); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: new credit state, consumed:%d available:%d max:%d seek:%d\n", + pProt->CreditsConsumed, + pProt->CreditsAvailable, + pProt->CreditsMax, + pProt->CreditsCurrentSeek)); + + if (pProt->CreditsAvailable >= pProt->CreditsCurrentSeek) { + /* we have enough credits to fullfill at least 1 packet waiting in the queue */ + pProt->CreditsCurrentSeek = 0; + pProt->SendStateFlags &= ~HCI_SEND_WAIT_CREDITS; + doPendingSends = TRUE; + if (CreditIRQEnabled) { + /* credit IRQ was enabled, we shouldn't need it anymore */ + disableCreditIrq = TRUE; + } + } else { + /* not enough credits yet, enable credit IRQ if we haven't already */ + if (!CreditIRQEnabled) { + enableCreditIrq = TRUE; + } + } + + } while (FALSE); + + UNLOCK_HCI_RX(pProt); + + if (enableCreditIrq) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Enabling credit count IRQ...\n")); + /* must use async only */ + status = DevGMboxIRQAction(pProt->pDev, GMBOX_CREDIT_IRQ_ENABLE, PROC_IO_ASYNC); + } else if (disableCreditIrq) { + /* must use async only */ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Disabling credit count IRQ...\n")); + status = DevGMboxIRQAction(pProt->pDev, GMBOX_CREDIT_IRQ_DISABLE, PROC_IO_ASYNC); + } + + if (doPendingSends) { + HCITrySend(pProt, NULL, FALSE); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+CreditsAvailableCallback \n")); + return status; +} + +static INLINE void NotifyTransportFailure(GMBOX_PROTO_HCI_UART *pProt, A_STATUS status) +{ + if (pProt->HCIConfig.TransportFailure != NULL) { + pProt->HCIConfig.TransportFailure(pProt->HCIConfig.pContext, status); + } +} + +static void FailureCallback(void *pContext, A_STATUS Status) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext; + + /* target assertion occured */ + NotifyTransportFailure(pProt, Status); +} + +static void StateDumpCallback(void *pContext) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext; + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("============ HCIUart State ======================\n")); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("RecvStateFlags : 0x%X \n",pProt->RecvStateFlags)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("SendStateFlags : 0x%X \n",pProt->SendStateFlags)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("WaitBufferType : %d \n",pProt->WaitBufferType)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("SendQueue Depth : %d \n",HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue))); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsMax : %d \n",pProt->CreditsMax)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsConsumed : %d \n",pProt->CreditsConsumed)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("CreditsAvailable : %d \n",pProt->CreditsAvailable)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("==================================================\n")); +} + +static A_STATUS HCIUartMessagePending(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)pContext; + A_STATUS status = A_OK; + int totalRecvLength = 0; + HCI_TRANSPORT_PACKET_TYPE pktType = HCI_PACKET_INVALID; + A_BOOL recvRefillCalled = FALSE; + A_BOOL blockRecv = FALSE; + HTC_PACKET *pPacket = NULL; + + /** caller guarantees that this is a fully block-able context (synch I/O is allowed) */ + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HCIUartMessagePending Lookahead Bytes:%d \n",ValidBytes)); + + LOCK_HCI_RX(pProt); + + do { + + if (ValidBytes < 3) { + /* not enough for ACL or event header */ + break; + } + + if ((LookAheadBytes[0] == HCI_UART_ACL_PKT) && (ValidBytes < 5)) { + /* not enough for ACL data header */ + break; + } + + switch (LookAheadBytes[0]) { + case HCI_UART_EVENT_PKT: + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI Event: %d param length: %d \n", + LookAheadBytes[1], LookAheadBytes[2])); + totalRecvLength = LookAheadBytes[2]; + totalRecvLength += 3; /* add type + event code + length field */ + pktType = HCI_EVENT_TYPE; + break; + case HCI_UART_ACL_PKT: + totalRecvLength = (LookAheadBytes[4] << 8) | LookAheadBytes[3]; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI ACL: conn:0x%X length: %d \n", + ((LookAheadBytes[2] & 0xF0) << 8) | LookAheadBytes[1], totalRecvLength)); + totalRecvLength += 5; /* add type + connection handle + length field */ + pktType = HCI_ACL_TYPE; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("**Invalid HCI packet type: %d \n",LookAheadBytes[0])); + status = A_EPROTO; + break; + } + + if (A_FAILED(status)) { + break; + } + + if (pProt->HCIConfig.pHCIPktRecvAlloc != NULL) { + UNLOCK_HCI_RX(pProt); + /* user is using a per-packet allocation callback */ + pPacket = pProt->HCIConfig.pHCIPktRecvAlloc(pProt->HCIConfig.pContext, + pktType, + totalRecvLength); + LOCK_HCI_RX(pProt); + + } else { + HTC_PACKET_QUEUE *pQueue; + /* user is using a refill handler that can refill multiple HTC buffers */ + + /* select buffer queue */ + if (pktType == HCI_ACL_TYPE) { + pQueue = &pProt->HCIACLRecvBuffers; + } else { + pQueue = &pProt->HCIEventBuffers; + } + + if (HTC_QUEUE_EMPTY(pQueue)) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("** HCI pkt type: %d has no buffers available calling allocation handler \n", + pktType)); + /* check for refill handler */ + if (pProt->HCIConfig.pHCIPktRecvRefill != NULL) { + recvRefillCalled = TRUE; + UNLOCK_HCI_RX(pProt); + /* call the re-fill handler */ + pProt->HCIConfig.pHCIPktRecvRefill(pProt->HCIConfig.pContext, + pktType, + 0); + LOCK_HCI_RX(pProt); + /* check if we have more buffers */ + pPacket = HTC_PACKET_DEQUEUE(pQueue); + /* fall through */ + } + } else { + pPacket = HTC_PACKET_DEQUEUE(pQueue); + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HCI pkt type: %d now has %d recv buffers left \n", + pktType, HTC_PACKET_QUEUE_DEPTH(pQueue))); + } + } + + if (NULL == pPacket) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("** HCI pkt type: %d has no buffers available stopping recv...\n", pktType)); + /* this is not an error, we simply need to mark that we are waiting for buffers.*/ + pProt->RecvStateFlags |= HCI_RECV_WAIT_BUFFERS; + pProt->WaitBufferType = pktType; + blockRecv = TRUE; + break; + } + + if (totalRecvLength > (int)pPacket->BufferLength) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI-UART pkt: %d requires %d bytes (%d buffer bytes avail) ! \n", + LookAheadBytes[0], totalRecvLength, pPacket->BufferLength)); + status = A_EINVAL; + break; + } + + } while (FALSE); + + UNLOCK_HCI_RX(pProt); + + /* locks are released, we can go fetch the packet */ + + do { + + if (A_FAILED(status) || (NULL == pPacket)) { + break; + } + + /* do this synchronously, we don't need to be fast here */ + pPacket->Completion = NULL; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI : getting recv packet len:%d hci-uart-type: %s \n", + totalRecvLength, (LookAheadBytes[0] == HCI_UART_EVENT_PKT) ? "EVENT" : "ACL")); + + status = DevGMboxRead(pProt->pDev, pPacket, totalRecvLength); + + if (A_FAILED(status)) { + break; + } + + if (pPacket->pBuffer[0] != LookAheadBytes[0]) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not contain expected packet type: %d ! \n", + pPacket->pBuffer[0])); + status = A_EPROTO; + break; + } + + if (pPacket->pBuffer[0] == HCI_UART_EVENT_PKT) { + /* validate event header fields */ + if ((pPacket->pBuffer[1] != LookAheadBytes[1]) || + (pPacket->pBuffer[2] != LookAheadBytes[2])) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not match lookahead! \n")); + DebugDumpBytes(LookAheadBytes, 3, "Expected HCI-UART Header"); + DebugDumpBytes(pPacket->pBuffer, 3, "** Bad HCI-UART Header"); + status = A_EPROTO; + break; + } + } else if (pPacket->pBuffer[0] == HCI_UART_ACL_PKT) { + /* validate acl header fields */ + if ((pPacket->pBuffer[1] != LookAheadBytes[1]) || + (pPacket->pBuffer[2] != LookAheadBytes[2]) || + (pPacket->pBuffer[3] != LookAheadBytes[3]) || + (pPacket->pBuffer[4] != LookAheadBytes[4])) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** HCI buffer does not match lookahead! \n")); + DebugDumpBytes(LookAheadBytes, 5, "Expected HCI-UART Header"); + DebugDumpBytes(pPacket->pBuffer, 5, "** Bad HCI-UART Header"); + status = A_EPROTO; + break; + } + } + + /* adjust buffer to move past packet ID */ + pPacket->pBuffer++; + pPacket->ActualLength = totalRecvLength - 1; + pPacket->Status = A_OK; + /* indicate packet */ + DO_HCI_RECV_INDICATION(pProt,pPacket); + pPacket = NULL; + + /* check if we need to refill recv buffers */ + if ((pProt->HCIConfig.pHCIPktRecvRefill != NULL) && !recvRefillCalled) { + HTC_PACKET_QUEUE *pQueue; + int watermark; + + if (pktType == HCI_ACL_TYPE) { + watermark = pProt->HCIConfig.ACLRecvBufferWaterMark; + pQueue = &pProt->HCIACLRecvBuffers; + } else { + watermark = pProt->HCIConfig.EventRecvBufferWaterMark; + pQueue = &pProt->HCIEventBuffers; + } + + if (HTC_PACKET_QUEUE_DEPTH(pQueue) < watermark) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("** HCI pkt type: %d watermark hit (%d) current:%d \n", + pktType, watermark, HTC_PACKET_QUEUE_DEPTH(pQueue))); + /* call the re-fill handler */ + pProt->HCIConfig.pHCIPktRecvRefill(pProt->HCIConfig.pContext, + pktType, + HTC_PACKET_QUEUE_DEPTH(pQueue)); + } + } + + } while (FALSE); + + /* check if we need to disable the reciever */ + if (A_FAILED(status) || blockRecv) { + DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_DISABLE, PROC_IO_SYNC); + } + + /* see if we need to recycle the recv buffer */ + if (A_FAILED(status) && (pPacket != NULL)) { + HTC_PACKET_QUEUE queue; + + if (A_EPROTO == status) { + DebugDumpBytes(pPacket->pBuffer, totalRecvLength, "Bad HCI-UART Recv packet"); + } + /* recycle packet */ + HTC_PACKET_RESET_RX(pPacket); + INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket); + HCI_TransportAddReceivePkts(pProt,&queue); + NotifyTransportFailure(pProt,status); + } + + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HCIUartMessagePending \n")); + + return status; +} + +static void HCISendPacketCompletion(void *Context, HTC_PACKET *pPacket) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)Context; + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCISendPacketCompletion (pPacket:0x%X) \n",(A_UINT32)pPacket)); + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Send Packet (0x%X) failed: %d , len:%d \n", + (A_UINT32)pPacket, pPacket->Status, pPacket->ActualLength)); + } + + DO_HCI_SEND_INDICATION(pProt,pPacket); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCISendPacketCompletion \n")); +} + +static A_STATUS SeekCreditsSynch(GMBOX_PROTO_HCI_UART *pProt) +{ + A_STATUS status = A_OK; + int credits; + int retry = 100; + + while (TRUE) { + credits = 0; + status = DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_SYNC, &credits); + if (A_FAILED(status)) { + break; + } + LOCK_HCI_TX(pProt); + pProt->CreditsAvailable += credits; + pProt->CreditsConsumed -= credits; + if (pProt->CreditsAvailable >= pProt->CreditsCurrentSeek) { + pProt->CreditsCurrentSeek = 0; + UNLOCK_HCI_TX(pProt); + break; + } + UNLOCK_HCI_TX(pProt); + retry--; + if (0 == retry) { + status = A_EBUSY; + break; + } + A_MDELAY(20); + } + + return status; +} + +static A_STATUS HCITrySend(GMBOX_PROTO_HCI_UART *pProt, HTC_PACKET *pPacket, A_BOOL Synchronous) +{ + A_STATUS status = A_OK; + int transferLength; + int creditsRequired, remainder; + A_UINT8 hciUartType; + A_BOOL synchSendComplete = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HCITrySend (pPacket:0x%X) %s \n",(A_UINT32)pPacket, + Synchronous ? "SYNC" :"ASYNC")); + + LOCK_HCI_TX(pProt); + + /* increment write processing count on entry */ + pProt->SendProcessCount++; + + do { + + if (pProt->HCIStopped) { + status = A_ECANCELED; + break; + } + + if (pPacket != NULL) { + /* packet was supplied */ + if (Synchronous) { + /* in synchronous mode, the send queue can only hold 1 packet */ + if (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) { + status = A_EBUSY; + A_ASSERT(FALSE); + break; + } + + if (pProt->SendProcessCount > 1) { + /* another thread or task is draining the TX queues */ + status = A_EBUSY; + A_ASSERT(FALSE); + break; + } + + HTC_PACKET_ENQUEUE(&pProt->SendQueue,pPacket); + + } else { + /* see if adding this packet hits the max depth (asynchronous mode only) */ + if ((pProt->HCIConfig.MaxSendQueueDepth > 0) && + ((HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue) + 1) >= pProt->HCIConfig.MaxSendQueueDepth)) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("HCI Send queue is full, Depth:%d, Max:%d \n", + HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue), + pProt->HCIConfig.MaxSendQueueDepth)); + /* queue will be full, invoke any callbacks to determine what action to take */ + if (pProt->HCIConfig.pHCISendFull != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("HCI : Calling driver's send full callback.... \n")); + if (pProt->HCIConfig.pHCISendFull(pProt->HCIConfig.pContext, + pPacket) == HCI_SEND_FULL_DROP) { + /* drop it */ + status = A_NO_RESOURCE; + break; + } + } + } + + HTC_PACKET_ENQUEUE(&pProt->SendQueue,pPacket); + } + + } + + if (pProt->SendStateFlags & HCI_SEND_WAIT_CREDITS) { + break; + } + + if (pProt->SendProcessCount > 1) { + /* another thread or task is draining the TX queues */ + break; + } + + /***** beyond this point only 1 thread may enter ******/ + + /* now drain the send queue for transmission as long as we have enough + * credits */ + while (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) { + + pPacket = HTC_PACKET_DEQUEUE(&pProt->SendQueue); + + switch (HCI_GET_PACKET_TYPE(pPacket)) { + case HCI_COMMAND_TYPE: + hciUartType = HCI_UART_COMMAND_PKT; + break; + case HCI_ACL_TYPE: + hciUartType = HCI_UART_ACL_PKT; + break; + default: + status = A_EINVAL; + A_ASSERT(FALSE); + break; + } + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Got head packet:0x%X , Type:%d Length: %d Remaining Queue Depth: %d\n", + (A_UINT32)pPacket, HCI_GET_PACKET_TYPE(pPacket), pPacket->ActualLength, + HTC_PACKET_QUEUE_DEPTH(&pProt->SendQueue))); + + transferLength = 1; /* UART type header is 1 byte */ + transferLength += pPacket->ActualLength; + transferLength = DEV_CALC_SEND_PADDED_LEN(pProt->pDev, transferLength); + + /* figure out how many credits this message requires */ + creditsRequired = transferLength / pProt->CreditSize; + remainder = transferLength % pProt->CreditSize; + + if (remainder) { + creditsRequired++; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: Creds Required:%d Got:%d\n", + creditsRequired, pProt->CreditsAvailable)); + + if (creditsRequired > pProt->CreditsAvailable) { + if (Synchronous) { + /* in synchronous mode we need to seek credits in synchronously */ + pProt->CreditsCurrentSeek = creditsRequired; + UNLOCK_HCI_TX(pProt); + status = SeekCreditsSynch(pProt); + LOCK_HCI_TX(pProt); + if (A_FAILED(status)) { + break; + } + /* fall through and continue processing this send op */ + } else { + /* not enough credits, queue back to the head */ + HTC_PACKET_ENQUEUE_TO_HEAD(&pProt->SendQueue,pPacket); + /* waiting for credits */ + pProt->SendStateFlags |= HCI_SEND_WAIT_CREDITS; + /* provide a hint to reduce attempts to re-send if credits are dribbling back + * this hint is the short fall of credits */ + pProt->CreditsCurrentSeek = creditsRequired; + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: packet:0x%X placed back in queue. head packet needs: %d credits \n", + (A_UINT32)pPacket, pProt->CreditsCurrentSeek)); + pPacket = NULL; + UNLOCK_HCI_TX(pProt); + + /* schedule a credit counter read, our CreditsAvailableCallback callback will be called + * with the result */ + DevGMboxReadCreditCounter(pProt->pDev, PROC_IO_ASYNC, NULL); + + LOCK_HCI_TX(pProt); + break; + } + } + + /* caller guarantees some head room */ + pPacket->pBuffer--; + pPacket->pBuffer[0] = hciUartType; + + pProt->CreditsAvailable -= creditsRequired; + pProt->CreditsConsumed += creditsRequired; + A_ASSERT(pProt->CreditsConsumed <= pProt->CreditsMax); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("HCI: new credit state: consumed:%d available:%d max:%d\n", + pProt->CreditsConsumed, pProt->CreditsAvailable, pProt->CreditsMax)); + + UNLOCK_HCI_TX(pProt); + + /* write it out */ + if (Synchronous) { + pPacket->Completion = NULL; + pPacket->pContext = NULL; + } else { + pPacket->Completion = HCISendPacketCompletion; + pPacket->pContext = pProt; + } + + status = DevGMboxWrite(pProt->pDev,pPacket,transferLength); + if (Synchronous) { + synchSendComplete = TRUE; + } else { + pPacket = NULL; + } + + LOCK_HCI_TX(pProt); + + } + + } while (FALSE); + + pProt->SendProcessCount--; + A_ASSERT(pProt->SendProcessCount >= 0); + UNLOCK_HCI_TX(pProt); + + if (Synchronous) { + A_ASSERT(pPacket != NULL); + if (A_SUCCESS(status) && (!synchSendComplete)) { + status = A_EBUSY; + A_ASSERT(FALSE); + LOCK_HCI_TX(pProt); + if (pPacket->ListLink.pNext != NULL) { + /* remove from the queue */ + HTC_PACKET_REMOVE(&pProt->SendQueue,pPacket); + } + UNLOCK_HCI_TX(pProt); + } + } else { + if (A_FAILED(status) && (pPacket != NULL)) { + pPacket->Status = status; + DO_HCI_SEND_INDICATION(pProt,pPacket); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HCITrySend: \n")); + return status; +} + +static void FlushSendQueue(GMBOX_PROTO_HCI_UART *pProt) +{ + HTC_PACKET *pPacket; + HTC_PACKET_QUEUE discardQueue; + + INIT_HTC_PACKET_QUEUE(&discardQueue); + + LOCK_HCI_TX(pProt); + + if (!HTC_QUEUE_EMPTY(&pProt->SendQueue)) { + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->SendQueue); + } + + UNLOCK_HCI_TX(pProt); + + /* discard packets */ + while (!HTC_QUEUE_EMPTY(&discardQueue)) { + pPacket = HTC_PACKET_DEQUEUE(&discardQueue); + pPacket->Status = A_ECANCELED; + DO_HCI_SEND_INDICATION(pProt,pPacket); + } + +} + +static void FlushRecvBuffers(GMBOX_PROTO_HCI_UART *pProt) +{ + HTC_PACKET_QUEUE discardQueue; + HTC_PACKET *pPacket; + + INIT_HTC_PACKET_QUEUE(&discardQueue); + + LOCK_HCI_RX(pProt); + /*transfer list items from ACL and event buffer queues to the discard queue */ + if (!HTC_QUEUE_EMPTY(&pProt->HCIACLRecvBuffers)) { + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->HCIACLRecvBuffers); + } + if (!HTC_QUEUE_EMPTY(&pProt->HCIEventBuffers)) { + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&discardQueue,&pProt->HCIEventBuffers); + } + UNLOCK_HCI_RX(pProt); + + /* now empty the discard queue */ + while (!HTC_QUEUE_EMPTY(&discardQueue)) { + pPacket = HTC_PACKET_DEQUEUE(&discardQueue); + pPacket->Status = A_ECANCELED; + DO_HCI_RECV_INDICATION(pProt,pPacket); + } + +} + +/*** protocol module install entry point ***/ + +A_STATUS GMboxProtocolInstall(AR6K_DEVICE *pDev) +{ + A_STATUS status = A_OK; + GMBOX_PROTO_HCI_UART *pProtocol = NULL; + + do { + + pProtocol = A_MALLOC(sizeof(GMBOX_PROTO_HCI_UART)); + + if (NULL == pProtocol) { + status = A_NO_MEMORY; + break; + } + + A_MEMZERO(pProtocol, sizeof(*pProtocol)); + pProtocol->pDev = pDev; + INIT_HTC_PACKET_QUEUE(&pProtocol->SendQueue); + INIT_HTC_PACKET_QUEUE(&pProtocol->HCIACLRecvBuffers); + INIT_HTC_PACKET_QUEUE(&pProtocol->HCIEventBuffers); + A_MUTEX_INIT(&pProtocol->HCIRxLock); + A_MUTEX_INIT(&pProtocol->HCITxLock); + + } while (FALSE); + + if (A_SUCCESS(status)) { + LOCK_AR6K(pDev); + DEV_GMBOX_SET_PROTOCOL(pDev, + HCIUartMessagePending, + CreditsAvailableCallback, + FailureCallback, + StateDumpCallback, + pProtocol); + UNLOCK_AR6K(pDev); + } else { + if (pProtocol != NULL) { + HCIUartCleanup(pProtocol); + } + } + + return status; +} + +/*** protocol module uninstall entry point ***/ +void GMboxProtocolUninstall(AR6K_DEVICE *pDev) +{ + GMBOX_PROTO_HCI_UART *pProtocol = (GMBOX_PROTO_HCI_UART *)DEV_GMBOX_GET_PROTOCOL(pDev); + + if (pProtocol != NULL) { + + /* notify anyone attached */ + if (pProtocol->HCIAttached) { + A_ASSERT(pProtocol->HCIConfig.TransportRemoved != NULL); + pProtocol->HCIConfig.TransportRemoved(pProtocol->HCIConfig.pContext); + pProtocol->HCIAttached = FALSE; + } + + HCIUartCleanup(pProtocol); + DEV_GMBOX_SET_PROTOCOL(pDev,NULL,NULL,NULL,NULL,NULL); + } + +} + +static A_STATUS NotifyTransportReady(GMBOX_PROTO_HCI_UART *pProt) +{ + HCI_TRANSPORT_PROPERTIES props; + A_STATUS status = A_OK; + + do { + + A_MEMZERO(&props,sizeof(props)); + + /* HCI UART only needs one extra byte at the head to indicate the packet TYPE */ + props.HeadRoom = 1; + props.TailRoom = 0; + props.IOBlockPad = pProt->pDev->BlockSize; + if (pProt->HCIAttached) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HCI: notifying attached client to transport... \n")); + A_ASSERT(pProt->HCIConfig.TransportReady != NULL); + status = pProt->HCIConfig.TransportReady(pProt, + &props, + pProt->HCIConfig.pContext); + } + + } while (FALSE); + + return status; +} + +/*********** HCI UART protocol implementation ************************************************/ + +HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo) +{ + GMBOX_PROTO_HCI_UART *pProtocol = NULL; + AR6K_DEVICE *pDev; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportAttach \n")); + + pDev = HTCGetAR6KDevice(HTCHandle); + + LOCK_AR6K(pDev); + + do { + + pProtocol = (GMBOX_PROTO_HCI_UART *)DEV_GMBOX_GET_PROTOCOL(pDev); + + if (NULL == pProtocol) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol not installed! \n")); + break; + } + + if (pProtocol->HCIAttached) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol already attached! \n")); + break; + } + + A_MEMCPY(&pProtocol->HCIConfig, pInfo, sizeof(HCI_TRANSPORT_CONFIG_INFO)); + + A_ASSERT(pProtocol->HCIConfig.pHCIPktRecv != NULL); + A_ASSERT(pProtocol->HCIConfig.pHCISendComplete != NULL); + + pProtocol->HCIAttached = TRUE; + + } while (FALSE); + + UNLOCK_AR6K(pDev); + + if (pProtocol != NULL) { + /* TODO ... should we use a worker? */ + NotifyTransportReady(pProtocol); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportAttach (0x%X) \n",(A_UINT32)pProtocol)); + return (HCI_TRANSPORT_HANDLE)pProtocol; +} + +void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans) +{ + GMBOX_PROTO_HCI_UART *pProtocol = (GMBOX_PROTO_HCI_UART *)HciTrans; + AR6K_DEVICE *pDev = pProtocol->pDev; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportDetach \n")); + + LOCK_AR6K(pDev); + if (!pProtocol->HCIAttached) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("GMBOX protocol not attached! \n")); + UNLOCK_AR6K(pDev); + return; + } + pProtocol->HCIAttached = FALSE; + UNLOCK_AR6K(pDev); + + HCI_TransportStop(HciTrans); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportAttach \n")); +} + +A_STATUS HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; + A_STATUS status = A_OK; + A_BOOL unblockRecv = FALSE; + HTC_PACKET *pPacket; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HCI_TransportAddReceivePkt \n")); + + LOCK_HCI_RX(pProt); + + do { + + if (pProt->HCIStopped) { + status = A_ECANCELED; + break; + } + + pPacket = HTC_GET_PKT_AT_HEAD(pQueue); + + if (NULL == pPacket) { + status = A_EINVAL; + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" HCI recv packet added, type :%d, len:%d num:%d \n", + HCI_GET_PACKET_TYPE(pPacket), pPacket->BufferLength, HTC_PACKET_QUEUE_DEPTH(pQueue))); + + if (HCI_GET_PACKET_TYPE(pPacket) == HCI_EVENT_TYPE) { + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pProt->HCIEventBuffers, pQueue); + } else if (HCI_GET_PACKET_TYPE(pPacket) == HCI_ACL_TYPE) { + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pProt->HCIACLRecvBuffers, pQueue); + } else { + status = A_EINVAL; + break; + } + + if (pProt->RecvStateFlags & HCI_RECV_WAIT_BUFFERS) { + if (pProt->WaitBufferType == HCI_GET_PACKET_TYPE(pPacket)) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" HCI recv was blocked on packet type :%d, unblocking.. \n", + pProt->WaitBufferType)); + pProt->RecvStateFlags &= ~HCI_RECV_WAIT_BUFFERS; + pProt->WaitBufferType = HCI_PACKET_INVALID; + unblockRecv = TRUE; + } + } + + } while (FALSE); + + UNLOCK_HCI_RX(pProt); + + if (A_FAILED(status)) { + while (!HTC_QUEUE_EMPTY(pQueue)) { + pPacket = HTC_PACKET_DEQUEUE(pQueue); + pPacket->Status = A_ECANCELED; + DO_HCI_RECV_INDICATION(pProt,pPacket); + } + } + + if (unblockRecv) { + DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_ENABLE, PROC_IO_ASYNC); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HCI_TransportAddReceivePkt \n")); + + return A_OK; +} + +A_STATUS HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; + + return HCITrySend(pProt,pPacket,Synchronous); +} + +void HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportStop \n")); + + LOCK_AR6K(pProt->pDev); + if (pProt->HCIStopped) { + UNLOCK_AR6K(pProt->pDev); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStop \n")); + return; + } + pProt->HCIStopped = TRUE; + UNLOCK_AR6K(pProt->pDev); + + /* disable interrupts */ + DevGMboxIRQAction(pProt->pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC); + FlushSendQueue(pProt); + FlushRecvBuffers(pProt); + + /* signal bridge side to power down BT */ + DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BT_OFF, BTOFF_TIMEOUT_MS); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStop \n")); +} + +A_STATUS HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans) +{ + A_STATUS status; + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("+HCI_TransportStart \n")); + + /* set stopped in case we have a problem in starting */ + pProt->HCIStopped = TRUE; + + do { + + status = InitTxCreditState(pProt); + + if (A_FAILED(status)) { + break; + } + + status = DevGMboxIRQAction(pProt->pDev, GMBOX_ERRORS_IRQ_ENABLE, PROC_IO_SYNC); + + if (A_FAILED(status)) { + break; + } + /* enable recv */ + status = DevGMboxIRQAction(pProt->pDev, GMBOX_RECV_IRQ_ENABLE, PROC_IO_SYNC); + + if (A_FAILED(status)) { + break; + } + /* signal bridge side to power up BT */ + status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BT_ON, BTON_TIMEOUT_MS); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI_TransportStart : Failed to trigger BT ON \n")); + break; + } + + /* we made it */ + pProt->HCIStopped = FALSE; + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("-HCI_TransportStart \n")); + + return status; +} + +A_STATUS HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; + return DevGMboxIRQAction(pProt->pDev, + Enable ? GMBOX_RECV_IRQ_ENABLE : GMBOX_RECV_IRQ_DISABLE, + PROC_IO_SYNC); + +} + +A_STATUS HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans, + HTC_PACKET *pPacket, + int MaxPollMS) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; + A_STATUS status = A_OK; + A_UINT8 lookAhead[8]; + int bytes; + int totalRecvLength; + + MaxPollMS = MaxPollMS / 16; + + if (MaxPollMS < 2) { + MaxPollMS = 2; + } + + while (MaxPollMS) { + + bytes = sizeof(lookAhead); + status = DevGMboxRecvLookAheadPeek(pProt->pDev,lookAhead,&bytes); + if (A_FAILED(status)) { + break; + } + + if (bytes < 3) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI recv poll got bytes: %d, retry : %d \n", + bytes, MaxPollMS)); + A_MDELAY(16); + MaxPollMS--; + continue; + } + + totalRecvLength = 0; + switch (lookAhead[0]) { + case HCI_UART_EVENT_PKT: + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HCI Event: %d param length: %d \n", + lookAhead[1], lookAhead[2])); + totalRecvLength = lookAhead[2]; + totalRecvLength += 3; /* add type + event code + length field */ + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("**Invalid HCI packet type: %d \n",lookAhead[0])); + status = A_EPROTO; + break; + } + + if (A_FAILED(status)) { + break; + } + + pPacket->Completion = NULL; + status = DevGMboxRead(pProt->pDev,pPacket,totalRecvLength); + if (A_FAILED(status)) { + break; + } + + pPacket->pBuffer++; + pPacket->ActualLength = totalRecvLength - 1; + pPacket->Status = A_OK; + break; + } + + if (MaxPollMS == 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HCI recv poll timeout! \n")); + status = A_ERROR; + } + + return status; +} + +#define LSB_SCRATCH_IDX 4 +#define MSB_SCRATCH_IDX 5 +A_STATUS HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud) +{ + GMBOX_PROTO_HCI_UART *pProt = (GMBOX_PROTO_HCI_UART *)HciTrans; + HIF_DEVICE *pHIFDevice = (HIF_DEVICE *)(pProt->pDev->HIFDevice); + A_UINT32 scaledBaud, scratchAddr; + A_STATUS status = A_OK; + + /* Divide the desired baud rate by 100 + * Store the LSB in the local scratch register 4 and the MSB in the local + * scratch register 5 for the target to read + */ + scratchAddr = MBOX_BASE_ADDRESS | (LOCAL_SCRATCH_ADDRESS + 4 * LSB_SCRATCH_IDX); + scaledBaud = (Baud / 100) & LOCAL_SCRATCH_VALUE_MASK; + status = ar6000_WriteRegDiag(pHIFDevice, &scratchAddr, &scaledBaud); + scratchAddr = MBOX_BASE_ADDRESS | (LOCAL_SCRATCH_ADDRESS + 4 * MSB_SCRATCH_IDX); + scaledBaud = ((Baud / 100) >> (LOCAL_SCRATCH_VALUE_MSB+1)) & LOCAL_SCRATCH_VALUE_MASK; + status |= ar6000_WriteRegDiag(pHIFDevice, &scratchAddr, &scaledBaud); + if (A_OK != status) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to set up baud rate in scratch register!")); + return status; + } + + /* Now interrupt the target to tell it about the baud rate */ + status = DevGMboxSetTargetInterrupt(pProt->pDev, MBOX_SIG_HCI_BRIDGE_BAUD_SET, BAUD_TIMEOUT_MS); + if (A_OK != status) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to tell target to change baud rate!")); + } + + return status; +} + +#endif //ATH_AR6K_ENABLE_GMBOX + diff --git a/drivers/net/wireless/ath6kl/htc2/AR6000/makefile b/drivers/net/wireless/ath6kl/htc2/AR6000/makefile new file mode 100644 index 000000000000..6e53a111b67f --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/AR6000/makefile @@ -0,0 +1,22 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation; +# +# Software distributed under the License is distributed on an "AS +# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# +#------------------------------------------------------------------------------ +#============================================================================== +# Author(s): ="Atheros" +#============================================================================== +!INCLUDE $(_MAKEENVROOT)\makefile.def + + + diff --git a/drivers/net/wireless/ath6kl/htc2/htc.c b/drivers/net/wireless/ath6kl/htc2/htc.c new file mode 100644 index 000000000000..0068685972a9 --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/htc.c @@ -0,0 +1,558 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +#ifdef DEBUG +static ATH_DEBUG_MASK_DESCRIPTION g_HTCDebugDescription[] = { + { ATH_DEBUG_SEND , "Send"}, + { ATH_DEBUG_RECV , "Recv"}, + { ATH_DEBUG_SYNC , "Sync"}, + { ATH_DEBUG_DUMP , "Dump Data (RX or TX)"}, + { ATH_DEBUG_IRQ , "Interrupt Processing"} +}; + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(htc, + "htc", + "Host Target Communications", + ATH_DEBUG_MASK_DEFAULTS, + ATH_DEBUG_DESCRIPTION_COUNT(g_HTCDebugDescription), + g_HTCDebugDescription); + +#endif + +static void HTCReportFailure(void *Context); +static void ResetEndpointStates(HTC_TARGET *target); + +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList) +{ + LOCK_HTC(target); + HTC_PACKET_ENQUEUE(pList,pPacket); + UNLOCK_HTC(target); +} + +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList) +{ + HTC_PACKET *pPacket; + + LOCK_HTC(target); + pPacket = HTC_PACKET_DEQUEUE(pList); + UNLOCK_HTC(target); + + return pPacket; +} + +/* cleanup the HTC instance */ +static void HTCCleanup(HTC_TARGET *target) +{ + A_INT32 i; + + DevCleanup(&target->Device); + + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + if (target->HTCControlBuffers[i].Buffer) { + A_FREE(target->HTCControlBuffers[i].Buffer); + } + } + + if (A_IS_MUTEX_VALID(&target->HTCLock)) { + A_MUTEX_DELETE(&target->HTCLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCRxLock)) { + A_MUTEX_DELETE(&target->HTCRxLock); + } + + if (A_IS_MUTEX_VALID(&target->HTCTxLock)) { + A_MUTEX_DELETE(&target->HTCTxLock); + } + /* free our instance */ + A_FREE(target); +} + +/* registered target arrival callback from the HIF layer */ +HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo) +{ + HTC_TARGET *target = NULL; + A_STATUS status = A_OK; + int i; + A_UINT32 ctrl_bufsz; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n")); + + A_REGISTER_MODULE_DEBUG_INFO(htc); + + do { + + /* allocate target memory */ + if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + + A_MEMZERO(target, sizeof(HTC_TARGET)); + A_MUTEX_INIT(&target->HTCLock); + A_MUTEX_INIT(&target->HTCRxLock); + A_MUTEX_INIT(&target->HTCTxLock); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList); + INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList); + + /* give device layer the hif device handle */ + target->Device.HIFDevice = hif_handle; + /* give the device layer our context (for event processing) + * the device layer will register it's own context with HIF + * so we need to set this so we can fetch it in the target remove handler */ + target->Device.HTCContext = target; + /* set device layer target failure callback */ + target->Device.TargetFailureCallback = HTCReportFailure; + /* set device layer recv message pending callback */ + target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler; + target->EpWaitingForBuffers = ENDPOINT_MAX; + + A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO)); + + ResetEndpointStates(target); + + /* setup device layer */ + status = DevSetup(&target->Device); + + if (A_FAILED(status)) { + break; + } + + + /* get the block sizes */ + status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + + /* Set the control buffer size based on the block size */ + if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) { + ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH; + } else { + ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH; + } + for (i = 0;i < NUM_CONTROL_BUFFERS;i++) { + target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz); + if (target->HTCControlBuffers[i].Buffer == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n")); + status = A_ERROR; + break; + } + } + + if (A_FAILED(status)) { + break; + } + + /* carve up buffers/packets for control messages */ + for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket, + target, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz, + ENDPOINT_0); + HTC_FREE_CONTROL_RX(target,pControlPacket); + } + + for (;i < NUM_CONTROL_BUFFERS;i++) { + HTC_PACKET *pControlPacket; + pControlPacket = &target->HTCControlBuffers[i].HtcPacket; + INIT_HTC_PACKET_INFO(pControlPacket, + target->HTCControlBuffers[i].Buffer, + ctrl_bufsz); + HTC_FREE_CONTROL_TX(target,pControlPacket); + } + + } while (FALSE); + + if (A_FAILED(status)) { + if (target != NULL) { + HTCCleanup(target); + target = NULL; + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n")); + + return target; +} + +void HTCDestroy(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy .. Destroying :0x%X \n",(A_UINT32)target)); + HTCCleanup(target); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n")); +} + +/* get the low level HIF device for the caller , the caller may wish to do low level + * HIF requests */ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + return target->Device.HIFDevice; +} + +/* wait for the target to arrive (sends HTC Ready message) + * this operation is fully synchronous and the message is polled for */ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status; + HTC_PACKET *pPacket = NULL; + HTC_READY_EX_MSG *pRdyMsg; + HTC_SERVICE_CONNECT_REQ connect; + HTC_SERVICE_CONNECT_RESP resp; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target)); + + do { + +#ifdef MBOXHW_UNIT_TEST + + status = DoMboxHWTest(&target->Device); + + if (status != A_OK) { + break; + } + +#endif + + /* we should be getting 1 control message that the target is ready */ + status = HTCWaitforControlMessage(target, &pPacket); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n")); + break; + } + + /* we controlled the buffer creation so it has to be properly aligned */ + pRdyMsg = (HTC_READY_EX_MSG *)pPacket->pBuffer; + + if ((pRdyMsg->Version2_0_Info.MessageID != HTC_MSG_READY_ID) || + (pPacket->ActualLength < sizeof(HTC_READY_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + + if (pRdyMsg->Version2_0_Info.CreditCount == 0 || pRdyMsg->Version2_0_Info.CreditSize == 0) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + target->TargetCredits = pRdyMsg->Version2_0_Info.CreditCount; + target->TargetCreditSize = pRdyMsg->Version2_0_Info.CreditSize; + + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, (" Target Ready: credits: %d credit size: %d\n", + target->TargetCredits, target->TargetCreditSize)); + + /* check if this is an extended ready message */ + if (pPacket->ActualLength >= sizeof(HTC_READY_EX_MSG)) { + /* this is an extended message */ + target->HTCTargetVersion = pRdyMsg->HTCVersion; + target->MaxMsgPerBundle = pRdyMsg->MaxMsgsPerHTCBundle; + } else { + /* legacy */ + target->HTCTargetVersion = HTC_VERSION_2P0; + target->MaxMsgPerBundle = 0; + } + +#ifdef HTC_FORCE_LEGACY_2P0 + /* for testing and comparison...*/ + target->HTCTargetVersion = HTC_VERSION_2P0; + target->MaxMsgPerBundle = 0; +#endif + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, + ("Using HTC Protocol Version : %s (%d)\n ", + (target->HTCTargetVersion == HTC_VERSION_2P0) ? "2.0" : ">= 2.1", + target->HTCTargetVersion)); + + if (target->MaxMsgPerBundle > 0) { + /* limit what HTC can handle */ + target->MaxMsgPerBundle = min(HTC_HOST_MAX_MSG_PER_BUNDLE, target->MaxMsgPerBundle); + /* target supports message bundling, setup device layer */ + if (A_FAILED(DevSetupMsgBundling(&target->Device,target->MaxMsgPerBundle))) { + /* device layer can't handle bundling */ + target->MaxMsgPerBundle = 0; + } else { + /* limit bundle what the device layer can handle */ + target->MaxMsgPerBundle = min(DEV_GET_MAX_MSG_PER_BUNDLE(&target->Device), + target->MaxMsgPerBundle); + } + } + + if (target->MaxMsgPerBundle > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, + (" HTC bundling allowed. Max Msg Per HTC Bundle: %d\n", target->MaxMsgPerBundle)); + target->SendBundlingEnabled = TRUE; + target->RecvBundlingEnabled = TRUE; + if (!DEV_IS_LEN_BLOCK_ALIGNED(&target->Device,target->TargetCreditSize)) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("*** Credit size: %d is not block aligned! Disabling send bundling \n", + target->TargetCreditSize)); + /* disallow send bundling since the credit size is not aligned to a block size + * the I/O block padding will spill into the next credit buffer which is fatal */ + target->SendBundlingEnabled = FALSE; + } + } + + /* setup our pseudo HTC control endpoint connection */ + A_MEMZERO(&connect,sizeof(connect)); + A_MEMZERO(&resp,sizeof(resp)); + connect.EpCallbacks.pContext = target; + connect.EpCallbacks.EpTxComplete = HTCControlTxComplete; + connect.EpCallbacks.EpRecv = HTCControlRecv; + connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */ + connect.EpCallbacks.EpSendFull = NULL; /* not nedded */ + connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS; + connect.ServiceID = HTC_CTRL_RSVD_SVC; + + /* connect fake service */ + status = HTCConnectService((HTC_HANDLE)target, + &connect, + &resp); + + if (!A_FAILED(status)) { + break; + } + + } while (FALSE); + + if (pPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n")); + + return status; +} + + + +/* Start HTC, enable interrupts and let the target know host has finished setup */ +A_STATUS HTCStart(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_PACKET *pPacket; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n")); + + /* make sure interrupts are disabled at the chip level, + * this function can be called again from a reboot of the target without shutting down HTC */ + DevDisableInterrupts(&target->Device); + /* make sure state is cleared again */ + target->OpStateFlags = 0; + target->RecvStateFlags = 0; + + /* now that we are starting, push control receive buffers into the + * HTC control endpoint */ + + while (1) { + pPacket = HTC_ALLOC_CONTROL_RX(target); + if (NULL == pPacket) { + break; + } + HTCAddReceivePkt((HTC_HANDLE)target,pPacket); + } + + do { + + AR_DEBUG_ASSERT(target->InitCredits != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL); + AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL); + + /* call init credits callback to do the distribution , + * NOTE: the first entry in the distribution list is ENDPOINT_0, so + * we pass the start of the list after this one. */ + target->InitCredits(target->pCredDistContext, + target->EpCreditDistributionListHead->pNext, + target->TargetCredits); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) { + DumpCreditDistStates(target); + } + + /* the caller is done connecting to services, so we can indicate to the + * target that the setup phase is complete */ + status = HTCSendSetupComplete(target); + + if (A_FAILED(status)) { + break; + } + + /* unmask interrupts */ + status = DevUnmaskInterrupts(&target->Device); + + if (A_FAILED(status)) { + HTCStop(target); + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n")); + return status; +} + +static void ResetEndpointStates(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + + A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist)); + pEndpoint->ServiceID = 0; + pEndpoint->MaxMsgLength = 0; + pEndpoint->MaxTxQueueDepth = 0; +#ifdef HTC_EP_STAT_PROFILING + A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats)); +#endif + INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers); + INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue); + INIT_HTC_PACKET_QUEUE(&pEndpoint->RecvIndicationQueue); + pEndpoint->target = target; + } + /* reset distribution list */ + target->EpCreditDistributionListHead = NULL; +} + +/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */ +void HTCStop(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n")); + + LOCK_HTC(target); + /* mark that we are shutting down .. */ + target->OpStateFlags |= HTC_OP_STATE_STOPPING; + UNLOCK_HTC(target); + + /* Masking interrupts is a synchronous operation, when this function returns + * all pending HIF I/O has completed, we can safely flush the queues */ + DevMaskInterrupts(&target->Device); + + /* flush all send packets */ + HTCFlushSendPkts(target); + /* flush all recv buffers */ + HTCFlushRecvBuffers(target); + + ResetEndpointStates(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n")); +} + +void HTCDumpCreditStates(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + LOCK_HTC_TX(target); + + DumpCreditDistStates(target); + + UNLOCK_HTC_TX(target); + + DumpAR6KDevState(&target->Device); +} + +/* report a target failure from the device, this is a callback from the device layer + * which uses a mechanism to report errors from the target (i.e. special interrupts) */ +static void HTCReportFailure(void *Context) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + + target->TargetFailure = TRUE; + + if (target->HTCInitInfo.TargetFailure != NULL) { + /* let upper layer know, it needs to call HTCStop() */ + target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR); + } +} + +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats) +{ + +#ifdef HTC_EP_STAT_PROFILING + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL clearStats = FALSE; + A_BOOL sample = FALSE; + + switch (Action) { + case HTC_EP_STAT_SAMPLE : + sample = TRUE; + break; + case HTC_EP_STAT_SAMPLE_AND_CLEAR : + sample = TRUE; + clearStats = TRUE; + break; + case HTC_EP_STAT_CLEAR : + clearStats = TRUE; + break; + default: + break; + } + + A_ASSERT(Endpoint < ENDPOINT_MAX); + + /* lock out TX and RX while we sample and/or clear */ + LOCK_HTC_TX(target); + LOCK_HTC_RX(target); + + if (sample) { + A_ASSERT(pStats != NULL); + /* return the stats to the caller */ + A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + if (clearStats) { + /* reset stats */ + A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS)); + } + + UNLOCK_HTC_RX(target); + UNLOCK_HTC_TX(target); + + return TRUE; +#else + return FALSE; +#endif +} + +AR6K_DEVICE *HTCGetAR6KDevice(void *HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + return &target->Device; +} + diff --git a/drivers/net/wireless/ath6kl/htc2/htc_debug.h b/drivers/net/wireless/ath6kl/htc2/htc_debug.h new file mode 100644 index 000000000000..0ceecf0dd36c --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/htc_debug.h @@ -0,0 +1,34 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_DEBUG_H_ +#define HTC_DEBUG_H_ + +#define ATH_MODULE_NAME htc +#include "a_debug.h" + +/* ------- Debug related stuff ------- */ + +#define ATH_DEBUG_SEND ATH_DEBUG_MAKE_MODULE_MASK(0) +#define ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(1) +#define ATH_DEBUG_SYNC ATH_DEBUG_MAKE_MODULE_MASK(2) +#define ATH_DEBUG_DUMP ATH_DEBUG_MAKE_MODULE_MASK(3) +#define ATH_DEBUG_IRQ ATH_DEBUG_MAKE_MODULE_MASK(4) + + +#endif /*HTC_DEBUG_H_*/ diff --git a/drivers/net/wireless/ath6kl/htc2/htc_internal.h b/drivers/net/wireless/ath6kl/htc2/htc_internal.h new file mode 100644 index 000000000000..fbff23f598f1 --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/htc_internal.h @@ -0,0 +1,213 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_INTERNAL_H_ +#define _HTC_INTERNAL_H_ + +/* for debugging, uncomment this to capture the last frame header, on frame header + * processing errors, the last frame header is dump for comparison */ +//#define HTC_CAPTURE_LAST_FRAME + +//#define HTC_EP_STAT_PROFILING + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc_debug.h" +#include "htc.h" +#include "htc_api.h" +#include "bmi_msg.h" +#include "hif.h" +#include "AR6000/ar6k.h" + +/* HTC operational parameters */ +#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */ +#define HTC_TARGET_DEBUG_INTR_MASK 0x01 +#define HTC_TARGET_CREDIT_INTR_MASK 0xF0 + +#define HTC_HOST_MAX_MSG_PER_BUNDLE 8 +#define HTC_MIN_HTC_MSGS_TO_BUNDLE 2 + +/* packet flags */ + +#define HTC_RX_PKT_IGNORE_LOOKAHEAD (1 << 0) +#define HTC_RX_PKT_REFRESH_HDR (1 << 1) +#define HTC_RX_PKT_PART_OF_BUNDLE (1 << 2) +#define HTC_RX_PKT_NO_RECYCLE (1 << 3) + +/* scatter request flags */ + +#define HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE (1 << 0) + +typedef struct _HTC_ENDPOINT { + HTC_ENDPOINT_ID Id; + HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to + non-zero value means this endpoint is in use */ + HTC_PACKET_QUEUE TxQueue; /* HTC frame buffer TX queue */ + HTC_PACKET_QUEUE RxBuffers; /* HTC frame buffer RX list */ + HTC_ENDPOINT_CREDIT_DIST CreditDist; /* credit distribution structure (exposed to driver layer) */ + HTC_EP_CALLBACKS EpCallBacks; /* callbacks associated with this endpoint */ + int MaxTxQueueDepth; /* max depth of the TX queue before we need to + call driver's full handler */ + int MaxMsgLength; /* max length of endpoint message */ + int TxProcessCount; /* reference count to continue tx processing */ + HTC_PACKET_QUEUE RecvIndicationQueue; /* recv packets ready to be indicated */ + int RxProcessCount; /* reference count to allow single processing context */ + struct _HTC_TARGET *target; /* back pointer to target */ + A_UINT8 SeqNo; /* TX seq no (helpful) for debugging */ + A_UINT32 LocalConnectionFlags; /* local connection flags */ +#ifdef HTC_EP_STAT_PROFILING + HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */ +#endif +} HTC_ENDPOINT; + +#ifdef HTC_EP_STAT_PROFILING +#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count); +#else +#define INC_HTC_EP_STAT(p,stat,count) +#endif + +#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL + +#define NUM_CONTROL_BUFFERS 8 +#define NUM_CONTROL_TX_BUFFERS 2 +#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS) + +typedef struct HTC_CONTROL_BUFFER { + HTC_PACKET HtcPacket; + A_UINT8 *Buffer; +} HTC_CONTROL_BUFFER; + +#define HTC_RECV_WAIT_BUFFERS (1 << 0) +#define HTC_OP_STATE_STOPPING (1 << 0) + +/* our HTC target state */ +typedef struct _HTC_TARGET { + HTC_ENDPOINT EndPoint[ENDPOINT_MAX]; + HTC_CONTROL_BUFFER HTCControlBuffers[NUM_CONTROL_BUFFERS]; + HTC_ENDPOINT_CREDIT_DIST *EpCreditDistributionListHead; + HTC_PACKET_QUEUE ControlBufferTXFreeList; + HTC_PACKET_QUEUE ControlBufferRXFreeList; + HTC_CREDIT_DIST_CALLBACK DistributeCredits; + HTC_CREDIT_INIT_CALLBACK InitCredits; + void *pCredDistContext; + int TargetCredits; + unsigned int TargetCreditSize; + A_MUTEX_T HTCLock; + A_MUTEX_T HTCRxLock; + A_MUTEX_T HTCTxLock; + AR6K_DEVICE Device; /* AR6K - specific state */ + A_UINT32 OpStateFlags; + A_UINT32 RecvStateFlags; + HTC_ENDPOINT_ID EpWaitingForBuffers; + A_BOOL TargetFailure; +#ifdef HTC_CAPTURE_LAST_FRAME + HTC_FRAME_HDR LastFrameHdr; /* useful for debugging */ + A_UINT8 LastTrailer[256]; + A_UINT8 LastTrailerLength; +#endif + HTC_INIT_INFO HTCInitInfo; + A_UINT8 HTCTargetVersion; + int MaxMsgPerBundle; /* max messages per bundle for HTC */ + A_BOOL SendBundlingEnabled; /* run time enable for send bundling (dynamic) */ + int RecvBundlingEnabled; /* run time enable for recv bundling (dynamic) */ +} HTC_TARGET; + +#define HTC_STOPPING(t) ((t)->OpStateFlags & HTC_OP_STATE_STOPPING) +#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock); +#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock); +#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock); +#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock); +#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock); +#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock); + +#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd)) +#define HTC_RECYCLE_RX_PKT(target,p,e) \ +{ \ + if ((p)->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_NO_RECYCLE) { \ + HTC_PACKET_RESET_RX(pPacket); \ + pPacket->Status = A_ECANCELED; \ + (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \ + (p)); \ + } else { \ + HTC_PACKET_RESET_RX(pPacket); \ + HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \ + } \ +} + +/* internal HTC functions */ +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket); +void HTCControlRecv(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket); +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList); +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList); +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket); +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket); +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched); +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint); +A_STATUS HTCSendSetupComplete(HTC_TARGET *target); +void HTCFlushRecvBuffers(HTC_TARGET *target); +void HTCFlushSendPkts(HTC_TARGET *target); +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist); +void DumpCreditDistStates(HTC_TARGET *target); +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) { + HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList); + if (pPacket != NULL) { + /* set payload pointer area with some headroom */ + pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH; + } + return pPacket; +} + +#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList) +#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList) +#define HTC_FREE_CONTROL_RX(t,p) \ +{ \ + HTC_PACKET_RESET_RX(p); \ + HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \ +} + +#define HTC_PREPARE_SEND_PKT(pP,sendflags,ctrl0,ctrl1) \ +{ \ + A_UINT8 *pHdrBuf; \ + (pP)->pBuffer -= HTC_HDR_LENGTH; \ + pHdrBuf = (pP)->pBuffer; \ + A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)(pP)->ActualLength); \ + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,(sendflags)); \ + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)(pP)->Endpoint); \ + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[0], (A_UINT8)(ctrl0)); \ + A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[1], (A_UINT8)(ctrl1)); \ +} + +#define HTC_UNPREPARE_SEND_PKT(pP) \ + (pP)->pBuffer += HTC_HDR_LENGTH; \ + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_INTERNAL_H_ */ diff --git a/drivers/net/wireless/ath6kl/htc2/htc_recv.c b/drivers/net/wireless/ath6kl/htc2/htc_recv.c new file mode 100644 index 000000000000..2b4c130b9467 --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/htc_recv.c @@ -0,0 +1,1545 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +#define HTCIssueRecv(t, p) \ + DevRecvPacket(&(t)->Device, \ + (p), \ + (p)->ActualLength) + +#define DO_RCV_COMPLETION(e,q) DoRecvCompletion(e,q) + +#define DUMP_RECV_PKT_INFO(pP) \ + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC RECV packet 0x%X (%d bytes) (hdr:0x%X) on ep : %d \n", \ + (A_UINT32)(pP), \ + (pP)->ActualLength, \ + (pP)->PktInfo.AsRx.ExpectedHdr, \ + (pP)->Endpoint)) + +#ifdef HTC_EP_STAT_PROFILING +#define HTC_RX_STAT_PROFILE(t,ep,numLookAheads) \ +{ \ + INC_HTC_EP_STAT((ep), RxReceived, 1); \ + if ((numLookAheads) == 1) { \ + INC_HTC_EP_STAT((ep), RxLookAheads, 1); \ + } else if ((numLookAheads) > 1) { \ + INC_HTC_EP_STAT((ep), RxBundleLookAheads, 1); \ + } \ +} +#else +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) +#endif + +static void DoRecvCompletion(HTC_ENDPOINT *pEndpoint, + HTC_PACKET_QUEUE *pQueueToIndicate) +{ + + do { + + if (HTC_QUEUE_EMPTY(pQueueToIndicate)) { + /* nothing to indicate */ + break; + } + + if (pEndpoint->EpCallBacks.EpRecvPktMultiple != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC calling ep %d, recv multiple callback (%d pkts) \n", + pEndpoint->Id, HTC_PACKET_QUEUE_DEPTH(pQueueToIndicate))); + /* a recv multiple handler is being used, pass the queue to the handler */ + pEndpoint->EpCallBacks.EpRecvPktMultiple(pEndpoint->EpCallBacks.pContext, + pQueueToIndicate); + INIT_HTC_PACKET_QUEUE(pQueueToIndicate); + } else { + HTC_PACKET *pPacket; + /* using legacy EpRecv */ + do { + pPacket = HTC_PACKET_DEQUEUE(pQueueToIndicate); + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" HTC calling ep %d recv callback on packet 0x%X \n", \ + pEndpoint->Id, (A_UINT32)(pPacket))); + pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext, pPacket); + } while (!HTC_QUEUE_EMPTY(pQueueToIndicate)); + } + + } while (FALSE); + +} + +static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target, + A_UINT8 *pBuffer, + int Length, + A_UINT32 *pNextLookAheads, + int *pNumLookAheads, + HTC_ENDPOINT_ID FromEndpoint) +{ + HTC_RECORD_HDR *pRecord; + A_UINT8 *pRecordBuf; + HTC_LOOKAHEAD_REPORT *pLookAhead; + A_UINT8 *pOrigBuffer; + int origLength; + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length)); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer"); + } + + pOrigBuffer = pBuffer; + origLength = Length; + status = A_OK; + + while (Length > 0) { + + if (Length < sizeof(HTC_RECORD_HDR)) { + status = A_EPROTO; + break; + } + /* these are byte aligned structs */ + pRecord = (HTC_RECORD_HDR *)pBuffer; + Length -= sizeof(HTC_RECORD_HDR); + pBuffer += sizeof(HTC_RECORD_HDR); + + if (pRecord->Length > Length) { + /* no room left in buffer for record */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" invalid record length: %d (id:%d) buffer has: %d bytes left \n", + pRecord->Length, pRecord->RecordID, Length)); + status = A_EPROTO; + break; + } + /* start of record follows the header */ + pRecordBuf = pBuffer; + + switch (pRecord->RecordID) { + case HTC_RECORD_CREDITS: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT)); + HTCProcessCreditRpt(target, + (HTC_CREDIT_REPORT *)pRecordBuf, + pRecord->Length / (sizeof(HTC_CREDIT_REPORT)), + FromEndpoint); + break; + case HTC_RECORD_LOOKAHEAD: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT)); + pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf; + if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) && + (pNextLookAheads != NULL)) { + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n", + pLookAhead->PreValid, + pLookAhead->PostValid)); + + /* look ahead bytes are valid, copy them over */ + ((A_UINT8 *)(&pNextLookAheads[0]))[0] = pLookAhead->LookAhead[0]; + ((A_UINT8 *)(&pNextLookAheads[0]))[1] = pLookAhead->LookAhead[1]; + ((A_UINT8 *)(&pNextLookAheads[0]))[2] = pLookAhead->LookAhead[2]; + ((A_UINT8 *)(&pNextLookAheads[0]))[3] = pLookAhead->LookAhead[3]; + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + DebugDumpBytes((A_UINT8 *)pNextLookAheads,4,"Next Look Ahead"); + } + /* just one normal lookahead */ + *pNumLookAheads = 1; + } + break; + case HTC_RECORD_LOOKAHEAD_BUNDLE: + AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT)); + if (pRecord->Length >= sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT) && + (pNextLookAheads != NULL)) { + HTC_BUNDLED_LOOKAHEAD_REPORT *pBundledLookAheadRpt; + int i; + + pBundledLookAheadRpt = (HTC_BUNDLED_LOOKAHEAD_REPORT *)pRecordBuf; + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + DebugDumpBytes(pRecordBuf,pRecord->Length,"Bundle LookAhead"); + } + + if ((pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))) > + HTC_HOST_MAX_MSG_PER_BUNDLE) { + /* this should never happen, the target restricts the number + * of messages per bundle configured by the host */ + A_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + for (i = 0; i < (int)(pRecord->Length / (sizeof(HTC_BUNDLED_LOOKAHEAD_REPORT))); i++) { + ((A_UINT8 *)(&pNextLookAheads[i]))[0] = pBundledLookAheadRpt->LookAhead[0]; + ((A_UINT8 *)(&pNextLookAheads[i]))[1] = pBundledLookAheadRpt->LookAhead[1]; + ((A_UINT8 *)(&pNextLookAheads[i]))[2] = pBundledLookAheadRpt->LookAhead[2]; + ((A_UINT8 *)(&pNextLookAheads[i]))[3] = pBundledLookAheadRpt->LookAhead[3]; + pBundledLookAheadRpt++; + } + + *pNumLookAheads = i; + } + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n", + pRecord->RecordID, pRecord->Length)); + break; + } + + if (A_FAILED(status)) { + break; + } + + /* advance buffer past this record for next time around */ + pBuffer += pRecord->Length; + Length -= pRecord->Length; + } + + if (A_FAILED(status)) { + DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer"); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n")); + return status; + +} + +/* process a received message (i.e. strip off header, process any trailer data) + * note : locks must be released when this function is called */ +static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, + HTC_PACKET *pPacket, + A_UINT32 *pNextLookAheads, + int *pNumLookAheads) +{ + A_UINT8 temp; + A_UINT8 *pBuf; + A_STATUS status = A_OK; + A_UINT16 payloadLen; + A_UINT32 lookAhead; + + pBuf = pPacket->pBuffer; + + if (pNumLookAheads != NULL) { + *pNumLookAheads = 0; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n")); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT"); + } + + do { + /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to + * retrieve 16 bit fields */ + payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen); + + ((A_UINT8 *)&lookAhead)[0] = pBuf[0]; + ((A_UINT8 *)&lookAhead)[1] = pBuf[1]; + ((A_UINT8 *)&lookAhead)[2] = pBuf[2]; + ((A_UINT8 *)&lookAhead)[3] = pBuf[3]; + + if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_REFRESH_HDR) { + /* refresh expected hdr, since this was unknown at the time we grabbed the packets + * as part of a bundle */ + pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead; + /* refresh actual length since we now have the real header */ + pPacket->ActualLength = payloadLen + HTC_HDR_LENGTH; + + /* validate the actual header that was refreshed */ + if (pPacket->ActualLength > pPacket->BufferLength) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Refreshed HDR payload length (%d) in bundled RECV is invalid (hdr: 0x%X) \n", + payloadLen, lookAhead)); + /* limit this to max buffer just to print out some of the buffer */ + pPacket->ActualLength = min(pPacket->ActualLength, pPacket->BufferLength); + status = A_EPROTO; + break; + } + + if (pPacket->Endpoint != A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, EndpointID)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Refreshed HDR endpoint (%d) does not match expected endpoint (%d) \n", + A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, EndpointID), pPacket->Endpoint)); + status = A_EPROTO; + break; + } + } + + if (lookAhead != pPacket->PktInfo.AsRx.ExpectedHdr) { + /* somehow the lookahead that gave us the full read length did not + * reflect the actual header in the pending message */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, lookahead mismatch! (pPkt:0x%X flags:0x%X) \n", + (A_UINT32)pPacket, pPacket->PktInfo.AsRx.HTCRxFlags)); + DebugDumpBytes((A_UINT8 *)&pPacket->PktInfo.AsRx.ExpectedHdr,4,"Expected Message LookAhead"); + DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header"); +#ifdef HTC_CAPTURE_LAST_FRAME + DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header"); + if (target->LastTrailerLength != 0) { + DebugDumpBytes(target->LastTrailer, + target->LastTrailerLength, + "Last trailer"); + } +#endif + status = A_EPROTO; + break; + } + + /* get flags */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags); + + if (temp & HTC_FLAGS_RECV_TRAILER) { + /* this packet has a trailer */ + + /* extract the trailer length in control byte 0 */ + temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]); + + if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n", + payloadLen, temp)); + status = A_EPROTO; + break; + } + + if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_IGNORE_LOOKAHEAD) { + /* this packet was fetched as part of an HTC bundle, the embedded lookahead is + * not valid since the next packet may have already been fetched as part of the + * bundle */ + pNextLookAheads = NULL; + pNumLookAheads = NULL; + } + + /* process trailer data that follows HDR + application payload */ + status = HTCProcessTrailer(target, + (pBuf + HTC_HDR_LENGTH + payloadLen - temp), + temp, + pNextLookAheads, + pNumLookAheads, + pPacket->Endpoint); + + if (A_FAILED(status)) { + break; + } + +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp); + target->LastTrailerLength = temp; +#endif + /* trim length by trailer bytes */ + pPacket->ActualLength -= temp; + } +#ifdef HTC_CAPTURE_LAST_FRAME + else { + target->LastTrailerLength = 0; + } +#endif + + /* if we get to this point, the packet is good */ + /* remove header and adjust length */ + pPacket->pBuffer += HTC_HDR_LENGTH; + pPacket->ActualLength -= HTC_HDR_LENGTH; + + } while (FALSE); + + if (A_FAILED(status)) { + /* dump the whole packet */ + DebugDumpBytes(pBuf,pPacket->ActualLength < 256 ? pPacket->ActualLength : 256 ,"BAD HTC Recv PKT"); + } else { +#ifdef HTC_CAPTURE_LAST_FRAME + A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR)); +#endif + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) { + if (pPacket->ActualLength > 0) { + AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg"); + } + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n")); + return status; +} + +static INLINE void HTCAsyncRecvCheckMorePackets(HTC_TARGET *target, + A_UINT32 NextLookAheads[], + int NumLookAheads, + A_BOOL CheckMoreMsgs) +{ + /* was there a lookahead for the next packet? */ + if (NumLookAheads > 0) { + A_STATUS nextStatus; + int fetched = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCAsyncRecvCheckMorePackets - num lookaheads were non-zero : %d \n", + NumLookAheads)); + /* force status re-check */ + REF_IRQ_STATUS_RECHECK(&target->Device); + /* we have more packets, get the next packet fetch started */ + nextStatus = HTCRecvMessagePendingHandler(target, NextLookAheads, NumLookAheads, NULL, &fetched); + if (A_EPROTO == nextStatus) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Next look ahead from recv header was INVALID\n")); + DebugDumpBytes((A_UINT8 *)NextLookAheads, + NumLookAheads * (sizeof(A_UINT32)), + "BAD lookaheads from lookahead report"); + } + if (A_SUCCESS(nextStatus) && !fetched) { + /* we could not fetch any more packets due to resources */ + DevAsyncIrqProcessComplete(&target->Device); + } + } else { + if (CheckMoreMsgs) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCAsyncRecvCheckMorePackets - rechecking for more messages...\n")); + /* if we did not get anything on the look-ahead, + * call device layer to asynchronously re-check for messages. If we can keep the async + * processing going we get better performance. If there is a pending message we will keep processing + * messages asynchronously which should pipeline things nicely */ + DevCheckPendingRecvMsgsAsync(&target->Device); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("HTCAsyncRecvCheckMorePackets - no check \n")); + } + } + + +} + + /* unload the recv completion queue */ +static INLINE void DrainRecvIndicationQueue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint) +{ + HTC_PACKET_QUEUE recvCompletions; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+DrainRecvIndicationQueue \n")); + + INIT_HTC_PACKET_QUEUE(&recvCompletions); + + LOCK_HTC_RX(target); + + /* increment rx processing count on entry */ + pEndpoint->RxProcessCount++; + if (pEndpoint->RxProcessCount > 1) { + pEndpoint->RxProcessCount--; + /* another thread or task is draining the RX completion queue on this endpoint + * that thread will reset the rx processing count when the queue is drained */ + UNLOCK_HTC_RX(target); + return; + } + + /******* at this point only 1 thread may enter ******/ + + while (TRUE) { + + /* transfer items from main recv queue to the local one so we can release the lock */ + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&recvCompletions, &pEndpoint->RecvIndicationQueue); + + if (HTC_QUEUE_EMPTY(&recvCompletions)) { + /* all drained */ + break; + } + + /* release lock while we do the recv completions + * other threads can now queue more recv completions */ + UNLOCK_HTC_RX(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("DrainRecvIndicationQueue : completing %d RECV packets \n", + HTC_PACKET_QUEUE_DEPTH(&recvCompletions))); + /* do completion */ + DO_RCV_COMPLETION(pEndpoint,&recvCompletions); + + /* re-acquire lock to grab some more completions */ + LOCK_HTC_RX(target); + } + + /* reset count */ + pEndpoint->RxProcessCount = 0; + UNLOCK_HTC_RX(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-DrainRecvIndicationQueue \n")); + +} + + /* optimization for recv packets, we can indicate a "hint" that there are more + * single-packets to fetch on this endpoint */ +#define SET_MORE_RX_PACKET_INDICATION_FLAG(L,N,E,P) \ + if ((N) > 0) { SetRxPacketIndicationFlags((L)[0],(E),(P)); } + + /* for bundled frames, we can force the flag to indicate there are more packets */ +#define FORCE_MORE_RX_PACKET_INDICATION_FLAG(P) \ + (P)->PktInfo.AsRx.IndicationFlags |= HTC_RX_FLAGS_INDICATE_MORE_PKTS; + + /* note: this function can be called with the RX lock held */ +static INLINE void SetRxPacketIndicationFlags(A_UINT32 LookAhead, + HTC_ENDPOINT *pEndpoint, + HTC_PACKET *pPacket) +{ + HTC_FRAME_HDR *pHdr = (HTC_FRAME_HDR *)&LookAhead; + /* check to see if the "next" packet is from the same endpoint of the + completing packet */ + if (pHdr->EndpointID == pPacket->Endpoint) { + /* check that there is a buffer available to actually fetch it */ + if (!HTC_QUEUE_EMPTY(&pEndpoint->RxBuffers)) { + /* provide a hint that there are more RX packets to fetch */ + FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket); + } + } +} + + +/* asynchronous completion handler for recv packet fetching, when the device layer + * completes a read request, it will call this completion handler */ +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint; + A_UINT32 nextLookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE]; + int numLookAheads = 0; + A_STATUS status; + A_BOOL checkMorePkts = TRUE; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (pkt:0x%X, status:%d, ep:%d) \n", + (A_UINT32)pPacket, pPacket->Status, pPacket->Endpoint)); + + A_ASSERT(!IS_DEV_IRQ_PROC_SYNC_MODE(&target->Device)); + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + pPacket->Completion = NULL; + + /* get completion status */ + status = pPacket->Status; + + do { + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n", + pPacket->Status, pPacket->Endpoint)); + break; + } + /* process the header for any trailer data */ + status = HTCProcessRecvHeader(target,pPacket,nextLookAheads,&numLookAheads); + + if (A_FAILED(status)) { + break; + } + + if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_IGNORE_LOOKAHEAD) { + /* this packet was part of a bundle that had to be broken up. + * It was fetched one message at a time. There may be other asynchronous reads queued behind this one. + * Do no issue another check for more packets since the last one in the series of requests + * will handle it */ + checkMorePkts = FALSE; + } + + DUMP_RECV_PKT_INFO(pPacket); + LOCK_HTC_RX(target); + SET_MORE_RX_PACKET_INDICATION_FLAG(nextLookAheads,numLookAheads,pEndpoint,pPacket); + /* we have a good packet, queue it to the completion queue */ + HTC_PACKET_ENQUEUE(&pEndpoint->RecvIndicationQueue,pPacket); + HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads); + UNLOCK_HTC_RX(target); + + /* check for more recv packets before indicating */ + HTCAsyncRecvCheckMorePackets(target,nextLookAheads,numLookAheads,checkMorePkts); + + } while (FALSE); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n", + status)); + /* recycle this packet */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + } else { + /* a good packet was queued, drain the queue */ + DrainRecvIndicationQueue(target,pEndpoint); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n")); +} + +/* synchronously wait for a control message from the target, + * This function is used at initialization time ONLY. At init messages + * on ENDPOINT 0 are expected. */ +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket) +{ + A_STATUS status; + A_UINT32 lookAhead; + HTC_PACKET *pPacket = NULL; + HTC_FRAME_HDR *pHdr; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n")); + + do { + + *ppControlPacket = NULL; + + /* call the polling function to see if we have a message */ + status = DevPollMboxMsgRecv(&target->Device, + &lookAhead, + HTC_TARGET_RESPONSE_TIMEOUT); + + if (A_FAILED(status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead)); + + /* check the lookahead */ + pHdr = (HTC_FRAME_HDR *)&lookAhead; + + if (pHdr->EndpointID != ENDPOINT_0) { + /* unexpected endpoint number, should be zero */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + if (A_FAILED(status)) { + /* bad message */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pPacket = HTC_ALLOC_CONTROL_RX(target); + + if (pPacket == NULL) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + + pPacket->PktInfo.AsRx.HTCRxFlags = 0; + pPacket->PktInfo.AsRx.ExpectedHdr = lookAhead; + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + + if (pPacket->ActualLength > pPacket->BufferLength) { + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + /* we want synchronous operation */ + pPacket->Completion = NULL; + + /* get the message from the device, this will block */ + status = HTCIssueRecv(target, pPacket); + + if (A_FAILED(status)) { + break; + } + + /* process receive header */ + status = HTCProcessRecvHeader(target,pPacket,NULL,NULL); + + pPacket->Status = status; + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n", + status)); + break; + } + + /* give the caller this control message packet, they are responsible to free */ + *ppControlPacket = pPacket; + + } while (FALSE); + + if (A_FAILED(status)) { + if (pPacket != NULL) { + /* cleanup buffer on error */ + HTC_FREE_CONTROL_RX(target,pPacket); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n")); + + return status; +} + +static A_STATUS AllocAndPrepareRxPackets(HTC_TARGET *target, + A_UINT32 LookAheads[], + int Messages, + HTC_ENDPOINT *pEndpoint, + HTC_PACKET_QUEUE *pQueue) +{ + A_STATUS status = A_OK; + HTC_PACKET *pPacket; + HTC_FRAME_HDR *pHdr; + int i,j; + int numMessages; + int fullLength; + A_BOOL noRecycle; + + /* lock RX while we assemble the packet buffers */ + LOCK_HTC_RX(target); + + for (i = 0; i < Messages; i++) { + + pHdr = (HTC_FRAME_HDR *)&LookAheads[i]; + + if (pHdr->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID)); + /* invalid endpoint */ + status = A_EPROTO; + break; + } + + if (pHdr->EndpointID != pEndpoint->Id) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d should be : %d (index:%d)\n", + pHdr->EndpointID, pEndpoint->Id, i)); + /* invalid endpoint */ + status = A_EPROTO; + break; + } + + if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n", + pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH)); + status = A_EPROTO; + break; + } + + if (0 == pEndpoint->ServiceID) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID)); + /* endpoint isn't even connected */ + status = A_EPROTO; + break; + } + + if ((pHdr->Flags & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) == 0) { + /* HTC header only indicates 1 message to fetch */ + numMessages = 1; + } else { + /* HTC header indicates that every packet to follow has the same padded length so that it can + * be optimally fetched as a full bundle */ + numMessages = (pHdr->Flags & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT; + /* the count doesn't include the starter frame, just a count of frames to follow */ + numMessages++; + A_ASSERT(numMessages <= target->MaxMsgPerBundle); + INC_HTC_EP_STAT(pEndpoint, RxBundleIndFromHdr, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("HTC header indicates :%d messages can be fetched as a bundle \n",numMessages)); + } + + fullLength = DEV_CALC_RECV_PADDED_LEN(&target->Device,pHdr->PayloadLen + sizeof(HTC_FRAME_HDR)); + + /* get packet buffers for each message, if there was a bundle detected in the header, + * use pHdr as a template to fetch all packets in the bundle */ + for (j = 0; j < numMessages; j++) { + + /* reset flag, any packets allocated using the RecvAlloc() API cannot be recycled on cleanup, + * they must be explicitly returned */ + noRecycle = FALSE; + + if (pEndpoint->EpCallBacks.EpRecvAlloc != NULL) { + UNLOCK_HTC_RX(target); + noRecycle = TRUE; + /* user is using a per-packet allocation callback */ + pPacket = pEndpoint->EpCallBacks.EpRecvAlloc(pEndpoint->EpCallBacks.pContext, + pEndpoint->Id, + fullLength); + LOCK_HTC_RX(target); + + } else if ((pEndpoint->EpCallBacks.EpRecvAllocThresh != NULL) && + (fullLength > pEndpoint->EpCallBacks.RecvAllocThreshold)) { + INC_HTC_EP_STAT(pEndpoint,RxAllocThreshHit,1); + INC_HTC_EP_STAT(pEndpoint,RxAllocThreshBytes,pHdr->PayloadLen); + /* threshold was hit, call the special recv allocation callback */ + UNLOCK_HTC_RX(target); + noRecycle = TRUE; + /* user wants to allocate packets above a certain threshold */ + pPacket = pEndpoint->EpCallBacks.EpRecvAllocThresh(pEndpoint->EpCallBacks.pContext, + pEndpoint->Id, + fullLength); + LOCK_HTC_RX(target); + + } else { + /* user is using a refill handler that can refill multiple HTC buffers */ + + /* get a packet from the endpoint recv queue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + + if (NULL == pPacket) { + /* check for refill handler */ + if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) { + UNLOCK_HTC_RX(target); + /* call the re-fill handler */ + pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext, + pEndpoint->Id); + LOCK_HTC_RX(target); + /* check if we have more buffers */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers); + /* fall through */ + } + } + } + + if (NULL == pPacket) { + /* this is not an error, we simply need to mark that we are waiting for buffers.*/ + target->RecvStateFlags |= HTC_RECV_WAIT_BUFFERS; + target->EpWaitingForBuffers = pEndpoint->Id; + status = A_NO_RESOURCE; + break; + } + + AR_DEBUG_ASSERT(pPacket->Endpoint == pEndpoint->Id); + /* clear flags */ + pPacket->PktInfo.AsRx.HTCRxFlags = 0; + pPacket->PktInfo.AsRx.IndicationFlags = 0; + pPacket->Status = A_OK; + + if (noRecycle) { + /* flag that these packets cannot be recycled, they have to be returned to the + * user */ + pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_NO_RECYCLE; + } + /* add packet to queue (also incase we need to cleanup down below) */ + HTC_PACKET_ENQUEUE(pQueue,pPacket); + + if (HTC_STOPPING(target)) { + status = A_ECANCELED; + break; + } + + /* make sure this message can fit in the endpoint buffer */ + if ((A_UINT32)fullLength > pPacket->BufferLength) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Payload Length Error : header reports payload of: %d (%d) endpoint buffer size: %d \n", + pHdr->PayloadLen, fullLength, pPacket->BufferLength)); + status = A_EPROTO; + break; + } + + if (j > 0) { + /* for messages fetched in a bundle the expected lookahead is unknown since we + * are only using the lookahead of the first packet as a template of what to + * expect for lengths */ + /* flag that once we get the real HTC header we need to refesh the information */ + pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_REFRESH_HDR; + /* set it to something invalid */ + pPacket->PktInfo.AsRx.ExpectedHdr = 0xFFFFFFFF; + } else { + + pPacket->PktInfo.AsRx.ExpectedHdr = LookAheads[i]; /* set expected look ahead */ + } + /* set the amount of data to fetch */ + pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH; + } + + if (A_FAILED(status)) { + if (A_NO_RESOURCE == status) { + /* this is actually okay */ + status = A_OK; + } + break; + } + + } + + UNLOCK_HTC_RX(target); + + if (A_FAILED(status)) { + while (!HTC_QUEUE_EMPTY(pQueue)) { + pPacket = HTC_PACKET_DEQUEUE(pQueue); + /* recycle all allocated packets */ + HTC_RECYCLE_RX_PKT(target,pPacket,&target->EndPoint[pPacket->Endpoint]); + } + } + + return status; +} + +static void HTCAsyncRecvScatterCompletion(HIF_SCATTER_REQ *pScatterReq) +{ + int i; + HTC_PACKET *pPacket; + HTC_ENDPOINT *pEndpoint; + A_UINT32 lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE]; + int numLookAheads = 0; + HTC_TARGET *target = (HTC_TARGET *)pScatterReq->Context; + A_STATUS status; + A_BOOL partialBundle = FALSE; + HTC_PACKET_QUEUE localRecvQueue; + A_BOOL procError = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCAsyncRecvScatterCompletion TotLen: %d Entries: %d\n", + pScatterReq->TotalLength, pScatterReq->ValidScatterEntries)); + + A_ASSERT(!IS_DEV_IRQ_PROC_SYNC_MODE(&target->Device)); + + if (A_FAILED(pScatterReq->CompletionStatus)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Recv Scatter Request Failed: %d \n",pScatterReq->CompletionStatus)); + } + + if (pScatterReq->CallerFlags & HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE) { + partialBundle = TRUE; + } + + DEV_FINISH_SCATTER_OPERATION(pScatterReq); + + INIT_HTC_PACKET_QUEUE(&localRecvQueue); + + pPacket = (HTC_PACKET *)pScatterReq->ScatterList[0].pCallerContexts[0]; + /* note: all packets in a scatter req are for the same endpoint ! */ + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + /* walk through the scatter list and process */ + /* **** NOTE: DO NOT HOLD ANY LOCKS here, HTCProcessRecvHeader can take the TX lock + * as it processes credit reports */ + for (i = 0; i < pScatterReq->ValidScatterEntries; i++) { + pPacket = (HTC_PACKET *)pScatterReq->ScatterList[i].pCallerContexts[0]; + A_ASSERT(pPacket != NULL); + /* reset count, we are only interested in the look ahead in the last packet when we + * break out of this loop */ + numLookAheads = 0; + + if (A_SUCCESS(pScatterReq->CompletionStatus)) { + /* process header for each of the recv packets */ + status = HTCProcessRecvHeader(target,pPacket,lookAheads,&numLookAheads); + } else { + status = A_ERROR; + } + + if (A_SUCCESS(status)) { +#ifdef HTC_EP_STAT_PROFILING + LOCK_HTC_RX(target); + HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads); + INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1); + UNLOCK_HTC_RX(target); +#endif + if (i == (pScatterReq->ValidScatterEntries - 1)) { + /* last packet's more packets flag is set based on the lookahead */ + SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,numLookAheads,pEndpoint,pPacket); + } else { + /* packets in a bundle automatically have this flag set */ + FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket); + } + + DUMP_RECV_PKT_INFO(pPacket); + /* since we can't hold a lock in this loop, we insert into our local recv queue for + * storage until we can transfer them to the recv completion queue */ + HTC_PACKET_ENQUEUE(&localRecvQueue,pPacket); + + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Recv packet scatter entry %d failed (out of %d) \n", + i, pScatterReq->ValidScatterEntries)); + /* recycle failed recv */ + HTC_RECYCLE_RX_PKT(target, pPacket, pEndpoint); + /* set flag and continue processing the remaining scatter entries */ + procError = TRUE; + } + + } + + /* free scatter request */ + DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq); + + LOCK_HTC_RX(target); + /* transfer the packets in the local recv queue to the recv completion queue */ + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RecvIndicationQueue, &localRecvQueue); + + UNLOCK_HTC_RX(target); + + if (!procError) { + /* pipeline the next check (asynchronously) for more packets */ + HTCAsyncRecvCheckMorePackets(target, + lookAheads, + numLookAheads, + partialBundle ? FALSE : TRUE); + } + + /* now drain the indication queue */ + DrainRecvIndicationQueue(target,pEndpoint); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCAsyncRecvScatterCompletion \n")); +} + +static A_STATUS HTCIssueRecvPacketBundle(HTC_TARGET *target, + HTC_PACKET_QUEUE *pRecvPktQueue, + HTC_PACKET_QUEUE *pSyncCompletionQueue, + int *pNumPacketsFetched, + A_BOOL PartialBundle) +{ + A_STATUS status = A_OK; + HIF_SCATTER_REQ *pScatterReq; + int i, totalLength; + int pktsToScatter; + HTC_PACKET *pPacket; + A_BOOL asyncMode = (pSyncCompletionQueue == NULL) ? TRUE : FALSE; + int scatterSpaceRemaining = DEV_GET_MAX_BUNDLE_RECV_LENGTH(&target->Device); + + pktsToScatter = HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue); + pktsToScatter = min(pktsToScatter, target->MaxMsgPerBundle); + + if ((HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue) - pktsToScatter) > 0) { + /* we were forced to split this bundle receive operation + * all packets in this partial bundle must have their lookaheads ignored */ + PartialBundle = TRUE; + /* this would only happen if the target ignored our max bundle limit */ + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + ("HTCIssueRecvPacketBundle : partial bundle detected num:%d , %d \n", + HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue), pktsToScatter)); + } + + totalLength = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCIssueRecvPacketBundle (Numpackets: %d , actual : %d) \n", + HTC_PACKET_QUEUE_DEPTH(pRecvPktQueue), pktsToScatter)); + + do { + + pScatterReq = DEV_ALLOC_SCATTER_REQ(&target->Device); + + if (pScatterReq == NULL) { + /* no scatter resources left, just let caller handle it the legacy way */ + break; + } + + pScatterReq->CallerFlags = 0; + + if (PartialBundle) { + /* mark that this is a partial bundle, this has special ramifications to the + * scatter completion routine */ + pScatterReq->CallerFlags |= HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE; + } + + /* convert HTC packets to scatter list */ + for (i = 0; i < pktsToScatter; i++) { + int paddedLength; + + pPacket = HTC_PACKET_DEQUEUE(pRecvPktQueue); + A_ASSERT(pPacket != NULL); + + paddedLength = DEV_CALC_RECV_PADDED_LEN(&target->Device, pPacket->ActualLength); + + if ((scatterSpaceRemaining - paddedLength) < 0) { + /* exceeds what we can transfer, put the packet back */ + HTC_PACKET_ENQUEUE_TO_HEAD(pRecvPktQueue,pPacket); + break; + } + + scatterSpaceRemaining -= paddedLength; + + if (PartialBundle || (i < (pktsToScatter - 1))) { + /* packet 0..n-1 cannot be checked for look-aheads since we are fetching a bundle + * the last packet however can have it's lookahead used */ + pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_IGNORE_LOOKAHEAD; + } + + /* note: 1 HTC packet per scatter entry */ + /* setup packet into */ + pScatterReq->ScatterList[i].pBuffer = pPacket->pBuffer; + pScatterReq->ScatterList[i].Length = paddedLength; + + pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_PART_OF_BUNDLE; + + if (asyncMode) { + /* save HTC packet for async completion routine */ + pScatterReq->ScatterList[i].pCallerContexts[0] = pPacket; + } else { + /* queue to caller's sync completion queue, caller will unload this when we return */ + HTC_PACKET_ENQUEUE(pSyncCompletionQueue,pPacket); + } + + A_ASSERT(pScatterReq->ScatterList[i].Length); + totalLength += pScatterReq->ScatterList[i].Length; + } + + pScatterReq->TotalLength = totalLength; + pScatterReq->ValidScatterEntries = i; + + if (asyncMode) { + pScatterReq->CompletionRoutine = HTCAsyncRecvScatterCompletion; + pScatterReq->Context = target; + } + + status = DevSubmitScatterRequest(&target->Device, pScatterReq, DEV_SCATTER_READ, asyncMode); + + if (A_SUCCESS(status)) { + *pNumPacketsFetched = i; + } + + if (!asyncMode) { + /* free scatter request */ + DEV_FREE_SCATTER_REQ(&target->Device, pScatterReq); + } + + } while (FALSE); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCIssueRecvPacketBundle (status:%d) (fetched:%d) \n", + status,*pNumPacketsFetched)); + + return status; +} + +static INLINE void CheckRecvWaterMark(HTC_ENDPOINT *pEndpoint) +{ + /* see if endpoint is using a refill watermark + * ** no need to use a lock here, since we are only inspecting... + * caller may must not hold locks when calling this function */ + if (pEndpoint->EpCallBacks.RecvRefillWaterMark > 0) { + if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->RxBuffers) < pEndpoint->EpCallBacks.RecvRefillWaterMark) { + /* call the re-fill handler before we continue */ + pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext, + pEndpoint->Id); + } + } +} + +/* callback when device layer or lookahead report parsing detects a pending message */ +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + A_STATUS status = A_OK; + HTC_PACKET *pPacket; + HTC_ENDPOINT *pEndpoint; + A_BOOL asyncProc = FALSE; + A_UINT32 lookAheads[HTC_HOST_MAX_MSG_PER_BUNDLE]; + int pktsFetched; + HTC_PACKET_QUEUE recvPktQueue, syncCompletedPktsQueue; + A_BOOL partialBundle; + HTC_ENDPOINT_ID id; + int totalFetched = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler NumLookAheads: %d \n",NumLookAheads)); + + if (pNumPktsFetched != NULL) { + *pNumPktsFetched = 0; + } + + if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) { + /* We use async mode to get the packets if the device layer supports it. + * The device layer interfaces with HIF in which HIF may have restrictions on + * how interrupts are processed */ + asyncProc = TRUE; + } + + if (pAsyncProc != NULL) { + /* indicate to caller how we decided to process this */ + *pAsyncProc = asyncProc; + } + + if (NumLookAheads > HTC_HOST_MAX_MSG_PER_BUNDLE) { + A_ASSERT(FALSE); + return A_EPROTO; + } + + /* on first entry copy the lookaheads into our temp array for processing */ + A_MEMCPY(lookAheads, MsgLookAheads, (sizeof(A_UINT32)) * NumLookAheads); + + while (TRUE) { + + /* reset packets queues */ + INIT_HTC_PACKET_QUEUE(&recvPktQueue); + INIT_HTC_PACKET_QUEUE(&syncCompletedPktsQueue); + + if (NumLookAheads > HTC_HOST_MAX_MSG_PER_BUNDLE) { + status = A_EPROTO; + A_ASSERT(FALSE); + break; + } + + /* first lookahead sets the expected endpoint IDs for all packets in a bundle */ + id = ((HTC_FRAME_HDR *)&lookAheads[0])->EndpointID; + pEndpoint = &target->EndPoint[id]; + + if (id >= ENDPOINT_MAX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MsgPend, Invalid Endpoint in look-ahead: %d \n",id)); + status = A_EPROTO; + break; + } + + /* try to allocate as many HTC RX packets indicated by the lookaheads + * these packets are stored in the recvPkt queue */ + status = AllocAndPrepareRxPackets(target, + lookAheads, + NumLookAheads, + pEndpoint, + &recvPktQueue); + if (A_FAILED(status)) { + break; + } + + if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) >= 2) { + /* a recv bundle was detected, force IRQ status re-check again */ + REF_IRQ_STATUS_RECHECK(&target->Device); + } + + totalFetched += HTC_PACKET_QUEUE_DEPTH(&recvPktQueue); + + /* we've got packet buffers for all we can currently fetch, + * this count is not valid anymore */ + NumLookAheads = 0; + partialBundle = FALSE; + + /* now go fetch the list of HTC packets */ + while (!HTC_QUEUE_EMPTY(&recvPktQueue)) { + + pktsFetched = 0; + + if (target->RecvBundlingEnabled && (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) > 1)) { + /* there are enough packets to attempt a bundle transfer and recv bundling is allowed */ + status = HTCIssueRecvPacketBundle(target, + &recvPktQueue, + asyncProc ? NULL : &syncCompletedPktsQueue, + &pktsFetched, + partialBundle); + if (A_FAILED(status)) { + break; + } + + if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) != 0) { + /* we couldn't fetch all packets at one time, this creates a broken + * bundle */ + partialBundle = TRUE; + } + } + + /* see if the previous operation fetched any packets using bundling */ + if (0 == pktsFetched) { + /* dequeue one packet */ + pPacket = HTC_PACKET_DEQUEUE(&recvPktQueue); + A_ASSERT(pPacket != NULL); + + if (asyncProc) { + /* we use async mode to get the packet if the device layer supports it + * set our callback and context */ + pPacket->Completion = HTCRecvCompleteHandler; + pPacket->pContext = target; + } else { + /* fully synchronous */ + pPacket->Completion = NULL; + } + + if (HTC_PACKET_QUEUE_DEPTH(&recvPktQueue) > 0) { + /* lookaheads in all packets except the last one in the bundle must be ignored */ + pPacket->PktInfo.AsRx.HTCRxFlags |= HTC_RX_PKT_IGNORE_LOOKAHEAD; + } + + /* go fetch the packet */ + status = HTCIssueRecv(target, pPacket); + if (A_FAILED(status)) { + break; + } + + if (!asyncProc) { + /* sent synchronously, queue this packet for synchronous completion */ + HTC_PACKET_ENQUEUE(&syncCompletedPktsQueue,pPacket); + } + + } + + } + + if (A_SUCCESS(status)) { + CheckRecvWaterMark(pEndpoint); + } + + if (asyncProc) { + /* we did this asynchronously so we can get out of the loop, the asynch processing + * creates a chain of requests to continue processing pending messages in the + * context of callbacks */ + break; + } + + /* synchronous handling */ + if (target->Device.DSRCanYield) { + /* for the SYNC case, increment count that tracks when the DSR should yield */ + target->Device.CurrentDSRRecvCount++; + } + + /* in the sync case, all packet buffers are now filled, + * we can process each packet, check lookaheads and then repeat */ + + /* unload sync completion queue */ + while (!HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) { + HTC_PACKET_QUEUE container; + + pPacket = HTC_PACKET_DEQUEUE(&syncCompletedPktsQueue); + A_ASSERT(pPacket != NULL); + + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + /* reset count on each iteration, we are only interested in the last packet's lookahead + * information when we break out of this loop */ + NumLookAheads = 0; + /* process header for each of the recv packets + * note: the lookahead of the last packet is useful for us to continue in this loop */ + status = HTCProcessRecvHeader(target,pPacket,lookAheads,&NumLookAheads); + if (A_FAILED(status)) { + break; + } + + if (HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) { + /* last packet's more packets flag is set based on the lookahead */ + SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,NumLookAheads,pEndpoint,pPacket); + } else { + /* packets in a bundle automatically have this flag set */ + FORCE_MORE_RX_PACKET_INDICATION_FLAG(pPacket); + } + /* good packet, indicate it */ + HTC_RX_STAT_PROFILE(target,pEndpoint,NumLookAheads); + + if (pPacket->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_PART_OF_BUNDLE) { + INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1); + } + + INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket); + DO_RCV_COMPLETION(pEndpoint,&container); + } + + if (A_FAILED(status)) { + break; + } + + if (NumLookAheads == 0) { + /* no more look aheads */ + break; + } + + /* when we process recv synchronously we need to check if we should yield and stop + * fetching more packets indicated by the embedded lookaheads */ + if (target->Device.DSRCanYield) { + if (DEV_CHECK_RECV_YIELD(&target->Device)) { + /* break out, don't fetch any more packets */ + break; + } + } + + + /* check whether other OS contexts have queued any WMI command/data for WLAN. + * This check is needed only if WLAN Tx and Rx happens in same thread context */ + A_CHECK_DRV_TX(); + + /* for SYNCH processing, if we get here, we are running through the loop again due to a detected lookahead. + * Set flag that we should re-check IRQ status registers again before leaving IRQ processing, + * this can net better performance in high throughput situations */ + REF_IRQ_STATUS_RECHECK(&target->Device); + } + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Failed to get pending recv messages (%d) \n",status)); + /* cleanup any packets we allocated but didn't use to actually fetch any packets */ + while (!HTC_QUEUE_EMPTY(&recvPktQueue)) { + pPacket = HTC_PACKET_DEQUEUE(&recvPktQueue); + /* clean up packets */ + HTC_RECYCLE_RX_PKT(target, pPacket, &target->EndPoint[pPacket->Endpoint]); + } + /* cleanup any packets in sync completion queue */ + while (!HTC_QUEUE_EMPTY(&syncCompletedPktsQueue)) { + pPacket = HTC_PACKET_DEQUEUE(&syncCompletedPktsQueue); + /* clean up packets */ + HTC_RECYCLE_RX_PKT(target, pPacket, &target->EndPoint[pPacket->Endpoint]); + } + } + + /* before leaving, check to see if host ran out of buffers and needs to stop the + * receiver */ + if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, + (" Host has no RX buffers, blocking receiver to prevent overrun.. \n")); + /* try to stop receive at the device layer */ + DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC); + } + + if (pNumPktsFetched != NULL) { + *pNumPktsFetched = totalFetched; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n")); + + return status; +} + +A_STATUS HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + A_BOOL unblockRecv = FALSE; + A_STATUS status = A_OK; + HTC_PACKET *pFirstPacket; + + pFirstPacket = HTC_GET_PKT_AT_HEAD(pPktQueue); + + if (NULL == pFirstPacket) { + A_ASSERT(FALSE); + return A_EINVAL; + } + + AR_DEBUG_ASSERT(pFirstPacket->Endpoint < ENDPOINT_MAX); + + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, + ("+- HTCAddReceivePktMultiple : endPointId: %d, cnt:%d, length: %d\n", + pFirstPacket->Endpoint, + HTC_PACKET_QUEUE_DEPTH(pPktQueue), + pFirstPacket->BufferLength)); + + do { + + pEndpoint = &target->EndPoint[pFirstPacket->Endpoint]; + + LOCK_HTC_RX(target); + + if (HTC_STOPPING(target)) { + HTC_PACKET *pPacket; + + UNLOCK_HTC_RX(target); + + /* walk through queue and mark each one canceled */ + HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue,pPacket) { + pPacket->Status = A_ECANCELED; + } HTC_PACKET_QUEUE_ITERATE_END; + + DO_RCV_COMPLETION(pEndpoint,pPktQueue); + break; + } + + /* store receive packets */ + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RxBuffers, pPktQueue); + + /* check if we are blocked waiting for a new buffer */ + if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) { + if (target->EpWaitingForBuffers == pFirstPacket->Endpoint) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->RecvStateFlags &= ~HTC_RECV_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* TODO : implement a buffer threshold count? */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } + + } while (FALSE); + + return status; +} + +/* Makes a buffer available to the HTC module */ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_PACKET_QUEUE queue; + INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket); + return HTCAddReceivePktMultiple(HTCHandle, &queue); +} + +void HTCUnblockRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_BOOL unblockRecv = FALSE; + + LOCK_HTC_RX(target); + + /* check if we are blocked waiting for a new buffer */ + if (target->RecvStateFlags & HTC_RECV_WAIT_BUFFERS) { + AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("HTCUnblockRx : receiver was blocked on ep:%d, unblocking.. \n", + target->EpWaitingForBuffers)); + target->RecvStateFlags &= ~HTC_RECV_WAIT_BUFFERS; + target->EpWaitingForBuffers = ENDPOINT_MAX; + unblockRecv = TRUE; + } + + UNLOCK_HTC_RX(target); + + if (unblockRecv && !HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_ASYNC); + } +} + +static void HTCFlushRxQueue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_PACKET_QUEUE *pQueue) +{ + HTC_PACKET *pPacket; + HTC_PACKET_QUEUE container; + + LOCK_HTC_RX(target); + + while (1) { + pPacket = HTC_PACKET_DEQUEUE(pQueue); + if (NULL == pPacket) { + break; + } + UNLOCK_HTC_RX(target); + pPacket->Status = A_ECANCELED; + pPacket->ActualLength = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" Flushing RX packet:0x%X, length:%d, ep:%d \n", + (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint)); + INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket); + /* give the packet back */ + DO_RCV_COMPLETION(pEndpoint,&container); + LOCK_HTC_RX(target); + } + + UNLOCK_HTC_RX(target); +} + +static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint) +{ + /* flush any recv indications not already made */ + HTCFlushRxQueue(target,pEndpoint,&pEndpoint->RecvIndicationQueue); + /* flush any rx buffers */ + HTCFlushRxQueue(target,pEndpoint,&pEndpoint->RxBuffers); +} + +void HTCFlushRecvBuffers(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointRX(target,pEndpoint); + } +} + + +void HTCEnableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* re-enable */ + DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} + +void HTCDisableRecv(HTC_HANDLE HTCHandle) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + + if (!HTC_STOPPING(target)) { + /* disable */ + DevStopRecv(&target->Device,DEV_ENABLE_RECV_SYNC); + } +} + +int HTCGetNumRecvBuffers(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + return HTC_PACKET_QUEUE_DEPTH(&(target->EndPoint[Endpoint].RxBuffers)); +} + diff --git a/drivers/net/wireless/ath6kl/htc2/htc_send.c b/drivers/net/wireless/ath6kl/htc2/htc_send.c new file mode 100644 index 000000000000..13eef67aaeaf --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/htc_send.c @@ -0,0 +1,1019 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +typedef enum _HTC_SEND_QUEUE_RESULT { + HTC_SEND_QUEUE_OK = 0, /* packet was queued */ + HTC_SEND_QUEUE_DROP = 1, /* this packet should be dropped */ +} HTC_SEND_QUEUE_RESULT; + +#define DO_EP_TX_COMPLETION(ep,q) DoSendCompletion(ep,q) + +/* call the distribute credits callback with the distribution */ +#define DO_DISTRIBUTION(t,reason,description,pList) \ +{ \ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, \ + (" calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \ + (description), \ + (A_UINT32)(t)->DistributeCredits, \ + (A_UINT32)(t)->pCredDistContext, \ + (A_UINT32)pList)); \ + (t)->DistributeCredits((t)->pCredDistContext, \ + (pList), \ + (reason)); \ +} + +static void DoSendCompletion(HTC_ENDPOINT *pEndpoint, + HTC_PACKET_QUEUE *pQueueToIndicate) +{ + do { + + if (HTC_QUEUE_EMPTY(pQueueToIndicate)) { + /* nothing to indicate */ + break; + } + + if (pEndpoint->EpCallBacks.EpTxCompleteMultiple != NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" HTC calling ep %d, send complete multiple callback (%d pkts) \n", + pEndpoint->Id, HTC_PACKET_QUEUE_DEPTH(pQueueToIndicate))); + /* a multiple send complete handler is being used, pass the queue to the handler */ + pEndpoint->EpCallBacks.EpTxCompleteMultiple(pEndpoint->EpCallBacks.pContext, + pQueueToIndicate); + /* all packets are now owned by the callback, reset queue to be safe */ + INIT_HTC_PACKET_QUEUE(pQueueToIndicate); + } else { + HTC_PACKET *pPacket; + /* using legacy EpTxComplete */ + do { + pPacket = HTC_PACKET_DEQUEUE(pQueueToIndicate); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" HTC calling ep %d send complete callback on packet 0x%X \n", \ + pEndpoint->Id, (A_UINT32)(pPacket))); + pEndpoint->EpCallBacks.EpTxComplete(pEndpoint->EpCallBacks.pContext, pPacket); + } while (!HTC_QUEUE_EMPTY(pQueueToIndicate)); + } + + } while (FALSE); + +} + +/* do final completion on sent packet */ +static INLINE void CompleteSentPacket(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_PACKET *pPacket) +{ + pPacket->Completion = NULL; + + if (A_FAILED(pPacket->Status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("CompleteSentPacket: request failed (status:%d, ep:%d, length:%d creds:%d) \n", + pPacket->Status, pPacket->Endpoint, pPacket->ActualLength, pPacket->PktInfo.AsTx.CreditsUsed)); + /* on failure to submit, reclaim credits for this packet */ + LOCK_HTC_TX(target); + pEndpoint->CreditDist.TxCreditsToDist += pPacket->PktInfo.AsTx.CreditsUsed; + pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue); + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEND_COMPLETE, + "Send Complete", + target->EpCreditDistributionListHead->pNext); + UNLOCK_HTC_TX(target); + } + /* first, fixup the head room we allocated */ + pPacket->pBuffer += HTC_HDR_LENGTH; +} + +/* our internal send packet completion handler when packets are submited to the AR6K device + * layer */ +static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket) +{ + HTC_TARGET *target = (HTC_TARGET *)Context; + HTC_ENDPOINT *pEndpoint = &target->EndPoint[pPacket->Endpoint]; + HTC_PACKET_QUEUE container; + + CompleteSentPacket(target,pEndpoint,pPacket); + INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket); + /* do completion */ + DO_EP_TX_COMPLETION(pEndpoint,&container); +} + +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket) +{ + A_STATUS status; + A_BOOL sync = FALSE; + + if (pPacket->Completion == NULL) { + /* mark that this request was synchronously issued */ + sync = TRUE; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+-HTCIssueSend: transmit length : %d (%s) \n", + pPacket->ActualLength + HTC_HDR_LENGTH, + sync ? "SYNC" : "ASYNC" )); + + /* send message to device */ + status = DevSendPacket(&target->Device, + pPacket, + pPacket->ActualLength + HTC_HDR_LENGTH); + + if (sync) { + /* use local sync variable. If this was issued asynchronously, pPacket is no longer + * safe to access. */ + pPacket->pBuffer += HTC_HDR_LENGTH; + } + + /* if this request was asynchronous, the packet completion routine will be invoked by + * the device layer when the HIF layer completes the request */ + + return status; +} + + /* get HTC send packets from the TX queue on an endpoint */ +static INLINE void GetHTCSendPackets(HTC_TARGET *target, + HTC_ENDPOINT *pEndpoint, + HTC_PACKET_QUEUE *pQueue) +{ + int creditsRequired; + int remainder; + A_UINT8 sendFlags; + HTC_PACKET *pPacket; + unsigned int transferLength; + + /****** NOTE : the TX lock is held when this function is called *****************/ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+GetHTCSendPackets \n")); + + /* loop until we can grab as many packets out of the queue as we can */ + while (TRUE) { + + sendFlags = 0; + /* get packet at head, but don't remove it */ + pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue); + if (pPacket == NULL) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n", + (A_UINT32)pPacket, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue))); + + transferLength = DEV_CALC_SEND_PADDED_LEN(&target->Device, pPacket->ActualLength + HTC_HDR_LENGTH); + + if (transferLength <= target->TargetCreditSize) { + creditsRequired = 1; + } else { + /* figure out how many credits this message requires */ + creditsRequired = transferLength / target->TargetCreditSize; + remainder = transferLength % target->TargetCreditSize; + + if (remainder) { + creditsRequired++; + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d Got:%d\n", + creditsRequired, pEndpoint->CreditDist.TxCredits)); + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + + /* not enough credits */ + if (pPacket->Endpoint == ENDPOINT_0) { + /* leave it in the queue */ + break; + } + /* invoke the registered distribution function only if this is not + * endpoint 0, we let the driver layer provide more credits if it can. + * We pass the credit distribution list starting at the endpoint in question + * */ + + /* set how many credits we need */ + pEndpoint->CreditDist.TxCreditsSeek = + creditsRequired - pEndpoint->CreditDist.TxCredits; + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + pEndpoint->CreditDist.TxCreditsSeek = 0; + + if (pEndpoint->CreditDist.TxCredits < creditsRequired) { + /* still not enough credits to send, leave packet in the queue */ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + (" Not enough credits for ep %d leaving packet in queue..\n", + pPacket->Endpoint)); + break; + } + + } + + pEndpoint->CreditDist.TxCredits -= creditsRequired; + INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired); + + /* check if we need credits back from the target */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* we are getting low on credits, see if we can ask for more from the distribution function */ + pEndpoint->CreditDist.TxCreditsSeek = + pEndpoint->CreditDist.TxCreditsPerMaxMsg - pEndpoint->CreditDist.TxCredits; + + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEEK_CREDITS, + "Seek Credits", + &pEndpoint->CreditDist); + + pEndpoint->CreditDist.TxCreditsSeek = 0; + /* see if we were successful in getting more */ + if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + /* tell the target we need credits ASAP! */ + sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE; + INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits \n")); + } + } + + /* now we can fully dequeue */ + pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue); + /* save the number of credits this packet consumed */ + pPacket->PktInfo.AsTx.CreditsUsed = creditsRequired; + /* all TX packets are handled asynchronously */ + pPacket->Completion = HTCSendPktCompletionHandler; + pPacket->pContext = target; + INC_HTC_EP_STAT(pEndpoint, TxIssued, 1); + /* save send flags */ + pPacket->PktInfo.AsTx.SendFlags = sendFlags; + pPacket->PktInfo.AsTx.SeqNo = pEndpoint->SeqNo; + pEndpoint->SeqNo++; + /* queue this packet into the caller's queue */ + HTC_PACKET_ENQUEUE(pQueue,pPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-GetHTCSendPackets \n")); + +} + +static void HTCAsyncSendScatterCompletion(HIF_SCATTER_REQ *pScatterReq) +{ + int i; + HTC_PACKET *pPacket; + HTC_ENDPOINT *pEndpoint = (HTC_ENDPOINT *)pScatterReq->Context; + HTC_TARGET *target = (HTC_TARGET *)pEndpoint->target; + A_STATUS status = A_OK; + HTC_PACKET_QUEUE sendCompletes; + + INIT_HTC_PACKET_QUEUE(&sendCompletes); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCAsyncSendScatterCompletion TotLen: %d Entries: %d\n", + pScatterReq->TotalLength, pScatterReq->ValidScatterEntries)); + + DEV_FINISH_SCATTER_OPERATION(pScatterReq); + + if (A_FAILED(pScatterReq->CompletionStatus)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Send Scatter Request Failed: %d \n",pScatterReq->CompletionStatus)); + status = A_ERROR; + } + + /* walk through the scatter list and process */ + for (i = 0; i < pScatterReq->ValidScatterEntries; i++) { + pPacket = (HTC_PACKET *)(pScatterReq->ScatterList[i].pCallerContexts[0]); + A_ASSERT(pPacket != NULL); + pPacket->Status = status; + CompleteSentPacket(target,pEndpoint,pPacket); + /* add it to the completion queue */ + HTC_PACKET_ENQUEUE(&sendCompletes, pPacket); + } + + /* free scatter request */ + DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq); + /* complete all packets */ + DO_EP_TX_COMPLETION(pEndpoint,&sendCompletes); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCAsyncSendScatterCompletion \n")); +} + + /* drain a queue and send as bundles + * this function may return without fully draining the queue under the following conditions : + * - scatter resources are exhausted + * - a message that will consume a partial credit will stop the bundling process early + * - we drop below the minimum number of messages for a bundle + * */ +static void HTCIssueSendBundle(HTC_ENDPOINT *pEndpoint, + HTC_PACKET_QUEUE *pQueue, + int *pBundlesSent, + int *pTotalBundlesPkts) +{ + int pktsToScatter; + unsigned int scatterSpaceRemaining; + HIF_SCATTER_REQ *pScatterReq = NULL; + int i, packetsInScatterReq; + unsigned int transferLength; + HTC_PACKET *pPacket; + A_BOOL done = FALSE; + int bundlesSent = 0; + int totalPktsInBundle = 0; + HTC_TARGET *target = pEndpoint->target; + int creditRemainder = 0; + int creditPad; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCIssueSendBundle \n")); + + while (!done) { + + pktsToScatter = HTC_PACKET_QUEUE_DEPTH(pQueue); + pktsToScatter = min(pktsToScatter, target->MaxMsgPerBundle); + + if (pktsToScatter < HTC_MIN_HTC_MSGS_TO_BUNDLE) { + /* not enough to bundle */ + break; + } + + pScatterReq = DEV_ALLOC_SCATTER_REQ(&target->Device); + + if (pScatterReq == NULL) { + /* no scatter resources */ + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" No more scatter resources \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" pkts to scatter: %d \n", pktsToScatter)); + + pScatterReq->TotalLength = 0; + pScatterReq->ValidScatterEntries = 0; + + packetsInScatterReq = 0; + scatterSpaceRemaining = DEV_GET_MAX_BUNDLE_SEND_LENGTH(&target->Device); + + for (i = 0; i < pktsToScatter; i++) { + + pScatterReq->ScatterList[i].pCallerContexts[0] = NULL; + + pPacket = HTC_GET_PKT_AT_HEAD(pQueue); + if (pPacket == NULL) { + A_ASSERT(FALSE); + break; + } + + creditPad = 0; + transferLength = DEV_CALC_SEND_PADDED_LEN(&target->Device, + pPacket->ActualLength + HTC_HDR_LENGTH); + /* see if the padded transfer length falls on a credit boundary */ + creditRemainder = transferLength % target->TargetCreditSize; + + if (creditRemainder != 0) { + /* the transfer consumes a "partial" credit, this packet cannot be bundled unless + * we add additional "dummy" padding (max 255 bytes) to consume the entire credit + *** NOTE: only allow the send padding if the endpoint is allowed to */ + if (pEndpoint->LocalConnectionFlags & HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING) { + if (transferLength < target->TargetCreditSize) { + /* special case where the transfer is less than a credit */ + creditPad = target->TargetCreditSize - transferLength; + } else { + creditPad = creditRemainder; + } + + /* now check to see if we can indicate padding in the HTC header */ + if ((creditPad > 0) && (creditPad <= 255)) { + /* adjust the transferlength of this packet with the new credit padding */ + transferLength += creditPad; + } else { + /* the amount to pad is too large, bail on this packet, we have to + * send it using the non-bundled method */ + pPacket = NULL; + } + } else { + /* bail on this packet, user does not want padding applied */ + pPacket = NULL; + } + } + + if (NULL == pPacket) { + /* can't bundle */ + done = TRUE; + break; + } + + if (scatterSpaceRemaining < transferLength) { + /* exceeds what we can transfer */ + break; + } + + scatterSpaceRemaining -= transferLength; + /* now remove it from the queue */ + pPacket = HTC_PACKET_DEQUEUE(pQueue); + /* save it in the scatter list */ + pScatterReq->ScatterList[i].pCallerContexts[0] = pPacket; + /* prepare packet and flag message as part of a send bundle */ + HTC_PREPARE_SEND_PKT(pPacket, + pPacket->PktInfo.AsTx.SendFlags | HTC_FLAGS_SEND_BUNDLE, + creditPad, + pPacket->PktInfo.AsTx.SeqNo); + pScatterReq->ScatterList[i].pBuffer = pPacket->pBuffer; + pScatterReq->ScatterList[i].Length = transferLength; + A_ASSERT(transferLength); + pScatterReq->TotalLength += transferLength; + pScatterReq->ValidScatterEntries++; + packetsInScatterReq++; + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" %d, Adding packet : 0x%X, len:%d (remaining space:%d) \n", + i, (A_UINT32)pPacket,transferLength,scatterSpaceRemaining)); + } + + if (packetsInScatterReq >= HTC_MIN_HTC_MSGS_TO_BUNDLE) { + /* send path is always asynchronous */ + pScatterReq->CompletionRoutine = HTCAsyncSendScatterCompletion; + pScatterReq->Context = pEndpoint; + bundlesSent++; + totalPktsInBundle += packetsInScatterReq; + packetsInScatterReq = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Send Scatter total bytes: %d , entries: %d\n", + pScatterReq->TotalLength,pScatterReq->ValidScatterEntries)); + DevSubmitScatterRequest(&target->Device, pScatterReq, DEV_SCATTER_WRITE, DEV_SCATTER_ASYNC); + /* we don't own this anymore */ + pScatterReq = NULL; + /* try to send some more */ + continue; + } + + /* not enough packets to use the scatter request, cleanup */ + if (pScatterReq != NULL) { + if (packetsInScatterReq > 0) { + /* work backwards to requeue requests */ + for (i = (packetsInScatterReq - 1); i >= 0; i--) { + pPacket = (HTC_PACKET *)(pScatterReq->ScatterList[i].pCallerContexts[0]); + if (pPacket != NULL) { + /* undo any prep */ + HTC_UNPREPARE_SEND_PKT(pPacket); + /* queue back to the head */ + HTC_PACKET_ENQUEUE_TO_HEAD(pQueue,pPacket); + } + } + } + DEV_FREE_SCATTER_REQ(&target->Device,pScatterReq); + } + + /* if we get here, we sent all that we could, get out */ + break; + + } + + *pBundlesSent = bundlesSent; + *pTotalBundlesPkts = totalPktsInBundle; + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCIssueSendBundle (sent:%d) \n",bundlesSent)); + + return; +} + +/* + * if there are no credits, the packet(s) remains in the queue. + * this function returns the result of the attempt to send a queue of HTC packets */ +static HTC_SEND_QUEUE_RESULT HTCTrySend(HTC_TARGET *target, + HTC_ENDPOINT *pEndpoint, + HTC_PACKET_QUEUE *pCallersSendQueue) +{ + HTC_PACKET_QUEUE sendQueue; /* temp queue to hold packets at various stages */ + HTC_PACKET *pPacket; + int bundlesSent; + int pktsInBundles; + int overflow; + HTC_SEND_QUEUE_RESULT result = HTC_SEND_QUEUE_OK; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (Queue:0x%X Depth:%d)\n", + (A_UINT32)pCallersSendQueue, + (pCallersSendQueue == NULL) ? 0 : HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue))); + + /* init the local send queue */ + INIT_HTC_PACKET_QUEUE(&sendQueue); + + do { + + if (NULL == pCallersSendQueue) { + /* caller didn't provide a queue, just wants us to check queues and send */ + break; + } + + if (HTC_QUEUE_EMPTY(pCallersSendQueue)) { + /* empty queue */ + result = HTC_SEND_QUEUE_DROP; + break; + } + + if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) >= pEndpoint->MaxTxQueueDepth) { + /* we've already overflowed */ + overflow = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue); + } else { + /* figure out how much we will overflow by */ + overflow = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue); + overflow += HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue); + /* figure out how much we will overflow the TX queue by */ + overflow -= pEndpoint->MaxTxQueueDepth; + } + + /* if overflow is negative or zero, we are okay */ + if (overflow > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + (" Endpoint %d, TX queue will overflow :%d , Tx Depth:%d, Max:%d \n", + pEndpoint->Id, overflow, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue), pEndpoint->MaxTxQueueDepth)); + } + if ((overflow <= 0) || (pEndpoint->EpCallBacks.EpSendFull == NULL)) { + /* all packets will fit or caller did not provide send full indication handler + * -- just move all of them to the local sendQueue object */ + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&sendQueue, pCallersSendQueue); + } else { + int i; + int goodPkts = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue) - overflow; + + A_ASSERT(goodPkts >= 0); + /* we have overflowed, and a callback is provided */ + /* dequeue all non-overflow packets into the sendqueue */ + for (i = 0; i < goodPkts; i++) { + /* pop off caller's queue*/ + pPacket = HTC_PACKET_DEQUEUE(pCallersSendQueue); + A_ASSERT(pPacket != NULL); + /* insert into local queue */ + HTC_PACKET_ENQUEUE(&sendQueue,pPacket); + } + + /* the caller's queue has all the packets that won't fit*/ + /* walk through the caller's queue and indicate each one to the send full handler */ + ITERATE_OVER_LIST_ALLOW_REMOVE(&pCallersSendQueue->QueueHead, pPacket, HTC_PACKET, ListLink) { + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Indicating overflowed TX packet: 0x%X \n", + (A_UINT32)pPacket)); + if (pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext, + pPacket) == HTC_SEND_FULL_DROP) { + /* callback wants the packet dropped */ + INC_HTC_EP_STAT(pEndpoint, TxDropped, 1); + /* leave this one in the caller's queue for cleanup */ + } else { + /* callback wants to keep this packet, remove from caller's queue */ + HTC_PACKET_REMOVE(pCallersSendQueue, pPacket); + /* put it in the send queue */ + HTC_PACKET_ENQUEUE(&sendQueue,pPacket); + } + + } ITERATE_END; + + if (HTC_QUEUE_EMPTY(&sendQueue)) { + /* no packets made it in, caller will cleanup */ + result = HTC_SEND_QUEUE_DROP; + break; + } + } + + } while (FALSE); + + if (result != HTC_SEND_QUEUE_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + return result; + } + + LOCK_HTC_TX(target); + + if (!HTC_QUEUE_EMPTY(&sendQueue)) { + /* transfer packets */ + HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->TxQueue,&sendQueue); + A_ASSERT(HTC_QUEUE_EMPTY(&sendQueue)); + INIT_HTC_PACKET_QUEUE(&sendQueue); + } + + /* increment tx processing count on entry */ + pEndpoint->TxProcessCount++; + if (pEndpoint->TxProcessCount > 1) { + /* another thread or task is draining the TX queues on this endpoint + * that thread will reset the tx processing count when the queue is drained */ + pEndpoint->TxProcessCount--; + UNLOCK_HTC_TX(target); + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend (busy) \n")); + return HTC_SEND_QUEUE_OK; + } + + /***** beyond this point only 1 thread may enter ******/ + + /* now drain the endpoint TX queue for transmission as long as we have enough + * credits */ + while (TRUE) { + + if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) == 0) { + break; + } + + /* get all the packets for this endpoint that we can for this pass */ + GetHTCSendPackets(target, pEndpoint, &sendQueue); + + if (HTC_PACKET_QUEUE_DEPTH(&sendQueue) == 0) { + /* didn't get any packets due to a lack of credits */ + break; + } + + UNLOCK_HTC_TX(target); + + /* any packets to send are now in our local send queue */ + + bundlesSent = 0; + pktsInBundles = 0; + + while (TRUE) { + + /* try to send a bundle on each pass */ + if ((target->SendBundlingEnabled) && + (HTC_PACKET_QUEUE_DEPTH(&sendQueue) >= HTC_MIN_HTC_MSGS_TO_BUNDLE)) { + int temp1,temp2; + /* bundling is enabled and there is at least a minimum number of packets in the send queue + * send what we can in this pass */ + HTCIssueSendBundle(pEndpoint, &sendQueue, &temp1, &temp2); + bundlesSent += temp1; + pktsInBundles += temp2; + } + + /* if not bundling or there was a packet that could not be placed in a bundle, pull it out + * and send it the normal way */ + pPacket = HTC_PACKET_DEQUEUE(&sendQueue); + if (NULL == pPacket) { + /* local queue is fully drained */ + break; + } + HTC_PREPARE_SEND_PKT(pPacket, + pPacket->PktInfo.AsTx.SendFlags, + 0, + pPacket->PktInfo.AsTx.SeqNo); + HTCIssueSend(target, pPacket); + + /* go back and see if we can bundle some more */ + } + + LOCK_HTC_TX(target); + + INC_HTC_EP_STAT(pEndpoint, TxBundles, bundlesSent); + INC_HTC_EP_STAT(pEndpoint, TxPacketsBundled, pktsInBundles); + + } + + /* done with this endpoint, we can clear the count */ + pEndpoint->TxProcessCount = 0; + UNLOCK_HTC_TX(target); + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n")); + + return HTC_SEND_QUEUE_OK; +} + +A_STATUS HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint; + HTC_PACKET *pPacket; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCSendPktsMultiple: Queue: 0x%X, Pkts %d \n", + (A_UINT32)pPktQueue, HTC_PACKET_QUEUE_DEPTH(pPktQueue))); + + /* get packet at head to figure out which endpoint these packets will go into */ + pPacket = HTC_GET_PKT_AT_HEAD(pPktQueue); + if (NULL == pPacket) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPktsMultiple \n")); + return A_EINVAL; + } + + AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX); + pEndpoint = &target->EndPoint[pPacket->Endpoint]; + + HTCTrySend(target, pEndpoint, pPktQueue); + + /* do completion on any packets that couldn't get in */ + if (!HTC_QUEUE_EMPTY(pPktQueue)) { + + HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue,pPacket) { + if (HTC_STOPPING(target)) { + pPacket->Status = A_ECANCELED; + } else { + pPacket->Status = A_NO_RESOURCE; + } + } HTC_PACKET_QUEUE_ITERATE_END; + + DO_EP_TX_COMPLETION(pEndpoint,pPktQueue); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPktsMultiple \n")); + + return A_OK; +} + +/* HTC API - HTCSendPkt */ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket) +{ + HTC_PACKET_QUEUE queue; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, + ("+-HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n", + pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength)); + INIT_HTC_PACKET_QUEUE_AND_ADD(&queue,pPacket); + return HTCSendPktsMultiple(HTCHandle, &queue); +} + +/* check TX queues to drain because of credit distribution update */ +static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + HTC_ENDPOINT_CREDIT_DIST *pDistItem; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n")); + pDistItem = target->EpCreditDistributionListHead; + + /* run through the credit distribution list to see + * if there are packets queued + * NOTE: no locks need to be taken since the distribution list + * is not dynamic (cannot be re-ordered) and we are not modifying any state */ + while (pDistItem != NULL) { + pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved; + + if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n", + pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue))); + /* try to start the stalled queue, this list is ordered by priority. + * Highest priority queue get's processed first, if there are credits available the + * highest priority queue will get a chance to reclaim credits from lower priority + * ones */ + HTCTrySend(target, pEndpoint, NULL); + } + + pDistItem = pDistItem->pNext; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n")); +} + +/* process credit reports and call distribution function */ +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint) +{ + int i; + HTC_ENDPOINT *pEndpoint; + int totalCredits = 0; + A_BOOL doDist = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries)); + + /* lock out TX while we update credits */ + LOCK_HTC_TX(target); + + for (i = 0; i < NumEntries; i++, pRpt++) { + if (pRpt->EndpointID >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[pRpt->EndpointID]; + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n", + pRpt->EndpointID, pRpt->Credits)); + + +#ifdef HTC_EP_STAT_PROFILING + + INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1); + INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits); + + if (FromEndpoint == pRpt->EndpointID) { + /* this credit report arrived on the same endpoint indicating it arrived in an RX + * packet */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1); + } else if (FromEndpoint == ENDPOINT_0) { + /* this credit arrived on endpoint 0 as a NULL message */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1); + } else { + /* arrived on another endpoint */ + INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits); + INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1); + } + +#endif + + if (ENDPOINT_0 == pRpt->EndpointID) { + /* always give endpoint 0 credits back */ + pEndpoint->CreditDist.TxCredits += pRpt->Credits; + } else { + /* for all other endpoints, update credits to distribute, the distribution function + * will handle giving out credits back to the endpoints */ + pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits; + /* flag that we have to do the distribution */ + doDist = TRUE; + } + + /* refresh tx depth for distribution function that will recover these credits + * NOTE: this is only valid when there are credits to recover! */ + pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue); + + totalCredits += pRpt->Credits; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Report indicated %d credits to distribute \n", totalCredits)); + + if (doDist) { + /* this was a credit return based on a completed send operations + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_SEND_COMPLETE, + "Send Complete", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (totalCredits) { + HTCCheckEndpointTxQueues(target); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n")); +} + +/* flush endpoint TX queue */ +static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag) +{ + HTC_PACKET *pPacket; + HTC_PACKET_QUEUE discardQueue; + HTC_PACKET_QUEUE container; + + /* initialize the discard queue */ + INIT_HTC_PACKET_QUEUE(&discardQueue); + + LOCK_HTC_TX(target); + + /* interate from the front of the TX queue and flush out packets */ + ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue.QueueHead, pPacket, HTC_PACKET, ListLink) { + + /* check for removal */ + if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) { + /* remove from queue */ + HTC_PACKET_REMOVE(&pEndpoint->TxQueue, pPacket); + /* add it to the discard pile */ + HTC_PACKET_ENQUEUE(&discardQueue, pPacket); + } + + } ITERATE_END; + + UNLOCK_HTC_TX(target); + + /* empty the discard queue */ + while (1) { + pPacket = HTC_PACKET_DEQUEUE(&discardQueue); + if (NULL == pPacket) { + break; + } + pPacket->Status = A_ECANCELED; + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n", + (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag)); + INIT_HTC_PACKET_QUEUE_AND_ADD(&container,pPacket); + DO_EP_TX_COMPLETION(pEndpoint,&container); + } + +} + +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d ServiceID: 0x%X --------------\n", + pEPDist->Endpoint, pEPDist->ServiceID)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n", + (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags : 0x%X \n", pEPDist->DistFlags)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm : %d \n", pEPDist->TxCreditsNorm)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin : %d \n", pEPDist->TxCreditsMin)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits : %d \n", pEPDist->TxCredits)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned : %d \n", pEPDist->TxCreditsAssigned)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek : %d \n", pEPDist->TxCreditsSeek)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize : %d \n", pEPDist->TxCreditSize)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist : %d \n", pEPDist->TxCreditsToDist)); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth : %d \n", + HTC_PACKET_QUEUE_DEPTH(&((HTC_ENDPOINT *)pEPDist->pHTCReserved)->TxQueue))); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n")); +} + +void DumpCreditDistStates(HTC_TARGET *target) +{ + HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead; + + while (pEPList != NULL) { + DumpCreditDist(pEPList); + pEPList = pEPList->pNext; + } + + if (target->DistributeCredits != NULL) { + DO_DISTRIBUTION(target, + HTC_DUMP_CREDIT_STATE, + "Dump State", + NULL); + } +} + +/* flush all send packets from all endpoint queues */ +void HTCFlushSendPkts(HTC_TARGET *target) +{ + HTC_ENDPOINT *pEndpoint; + int i; + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) { + DumpCreditDistStates(target); + } + + for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) { + pEndpoint = &target->EndPoint[i]; + if (pEndpoint->ServiceID == 0) { + /* not in use.. */ + continue; + } + HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL); + } + + +} + +/* HTC API to flush an endpoint's TX queue*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + HTCFlushEndpointTX(target, pEndpoint, Tag); +} + +/* HTC API to indicate activity to the credit distribution function */ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + A_BOOL doDist = FALSE; + + if (pEndpoint->ServiceID == 0) { + AR_DEBUG_ASSERT(FALSE); + /* not in use.. */ + return; + } + + LOCK_HTC_TX(target); + + if (Active) { + if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) { + /* mark active now */ + pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE; + doDist = TRUE; + } + } else { + if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) { + /* mark inactive now */ + pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE; + doDist = TRUE; + } + } + + if (doDist) { + /* indicate current Tx Queue depth to the credit distribution function */ + pEndpoint->CreditDist.TxQueueDepth = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue); + /* do distribution again based on activity change + * note, this is done with the lock held */ + DO_DISTRIBUTION(target, + HTC_CREDIT_DIST_ACTIVITY_CHANGE, + "Activity Change", + target->EpCreditDistributionListHead->pNext); + } + + UNLOCK_HTC_TX(target); + + if (doDist && !Active) { + /* if a stream went inactive and this resulted in a credit distribution change, + * some credits may now be available for HTC packets that are stuck in + * HTC queues */ + HTCCheckEndpointTxQueues(target); + } +} + +A_BOOL HTCIsEndpointActive(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint]; + + if (pEndpoint->ServiceID == 0) { + return FALSE; + } + + if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) { + return TRUE; + } + + return FALSE; +} diff --git a/drivers/net/wireless/ath6kl/htc2/htc_services.c b/drivers/net/wireless/ath6kl/htc2/htc_services.c new file mode 100644 index 000000000000..acef96e238c3 --- /dev/null +++ b/drivers/net/wireless/ath6kl/htc2/htc_services.c @@ -0,0 +1,444 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#include "htc_internal.h" + +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket) +{ + /* not implemented + * we do not send control TX frames during normal runtime, only during setup */ + AR_DEBUG_ASSERT(FALSE); +} + + /* callback when a control message arrives on this endpoint */ +void HTCControlRecv(void *Context, HTC_PACKET *pPacket) +{ + AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0); + + if (pPacket->Status == A_ECANCELED) { + /* this is a flush operation, return the control packet back to the pool */ + HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket); + return; + } + + /* the only control messages we are expecting are NULL messages (credit resports) */ + if (pPacket->ActualLength > 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("HTCControlRecv, got message with length:%d \n", + pPacket->ActualLength + HTC_HDR_LENGTH)); + + /* dump header and message */ + DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH, + pPacket->ActualLength + HTC_HDR_LENGTH, + "Unexpected ENDPOINT 0 Message"); + } + + HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]); +} + +A_STATUS HTCSendSetupComplete(HTC_TARGET *target) +{ + HTC_PACKET *pSendPacket = NULL; + A_STATUS status; + + do { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + status = A_NO_MEMORY; + break; + } + + if (target->HTCTargetVersion >= HTC_VERSION_2P1) { + HTC_SETUP_COMPLETE_EX_MSG *pSetupCompleteEx; + A_UINT32 setupFlags = 0; + + pSetupCompleteEx = (HTC_SETUP_COMPLETE_EX_MSG *)pSendPacket->pBuffer; + A_MEMZERO(pSetupCompleteEx, sizeof(HTC_SETUP_COMPLETE_EX_MSG)); + pSetupCompleteEx->MessageID = HTC_MSG_SETUP_COMPLETE_EX_ID; + if (target->MaxMsgPerBundle > 0) { + /* host can do HTC bundling, indicate this to the target */ + setupFlags |= HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV; + pSetupCompleteEx->MaxMsgsPerBundledRecv = target->MaxMsgPerBundle; + } + A_MEMCPY(&pSetupCompleteEx->SetupFlags, &setupFlags, sizeof(pSetupCompleteEx->SetupFlags)); + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pSetupCompleteEx, + sizeof(HTC_SETUP_COMPLETE_EX_MSG), + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + } else { + HTC_SETUP_COMPLETE_MSG *pSetupComplete; + /* assemble setup complete message */ + pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer; + A_MEMZERO(pSetupComplete, sizeof(HTC_SETUP_COMPLETE_MSG)); + pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID; + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pSetupComplete, + sizeof(HTC_SETUP_COMPLETE_MSG), + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + } + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0); + /* send the message */ + status = HTCIssueSend(target,pSendPacket); + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + return status; +} + + +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pConnectReq, + HTC_SERVICE_CONNECT_RESP *pConnectResp) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + A_STATUS status = A_OK; + HTC_PACKET *pRecvPacket = NULL; + HTC_PACKET *pSendPacket = NULL; + HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg; + HTC_CONNECT_SERVICE_MSG *pConnectMsg; + HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX; + HTC_ENDPOINT *pEndpoint; + unsigned int maxMsgSize = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n", + (A_UINT32)target, pConnectReq->ServiceID)); + + do { + + AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0); + + if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) { + /* special case for pseudo control service */ + assignedEndpoint = ENDPOINT_0; + maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH; + } else { + /* allocate a packet to send to the target */ + pSendPacket = HTC_ALLOC_CONTROL_TX(target); + + if (NULL == pSendPacket) { + AR_DEBUG_ASSERT(FALSE); + status = A_NO_MEMORY; + break; + } + /* assemble connect service message */ + pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer; + AR_DEBUG_ASSERT(pConnectMsg != NULL); + A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG)); + pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID; + pConnectMsg->ServiceID = pConnectReq->ServiceID; + pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags; + /* check caller if it wants to transfer meta data */ + if ((pConnectReq->pMetaData != NULL) && + (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* copy meta data into message buffer (after header ) */ + A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG), + pConnectReq->pMetaData, + pConnectReq->MetaDataLength); + pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength; + } + + SET_HTC_PACKET_INFO_TX(pSendPacket, + NULL, + (A_UINT8 *)pConnectMsg, + sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength, + ENDPOINT_0, + HTC_SERVICE_TX_PACKET_TAG); + + /* we want synchronous operation */ + pSendPacket->Completion = NULL; + HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0); + status = HTCIssueSend(target,pSendPacket); + + if (A_FAILED(status)) { + break; + } + + /* wait for response */ + status = HTCWaitforControlMessage(target, &pRecvPacket); + + if (A_FAILED(status)) { + break; + } + /* we controlled the buffer creation so it has to be properly aligned */ + pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer; + + if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) || + (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) { + /* this message is not valid */ + AR_DEBUG_ASSERT(FALSE); + status = A_EPROTO; + break; + } + + pConnectResp->ConnectRespCode = pResponseMsg->Status; + /* check response status */ + if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + (" Target failed service 0x%X connect request (status:%d)\n", + pResponseMsg->ServiceID, pResponseMsg->Status)); + status = A_EPROTO; + break; + } + + assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID; + maxMsgSize = pResponseMsg->MaxMsgSize; + + if ((pConnectResp->pMetaData != NULL) && + (pResponseMsg->ServiceMetaLength > 0) && + (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) { + /* caller supplied a buffer and the target responded with data */ + int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength); + /* copy the meta data */ + A_MEMCPY(pConnectResp->pMetaData, + ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG), + copyLength); + pConnectResp->ActualLength = copyLength; + } + + } + + /* the rest of these are parameter checks so set the error status */ + status = A_EPROTO; + + if (assignedEndpoint >= ENDPOINT_MAX) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + if (0 == maxMsgSize) { + AR_DEBUG_ASSERT(FALSE); + break; + } + + pEndpoint = &target->EndPoint[assignedEndpoint]; + pEndpoint->Id = assignedEndpoint; + if (pEndpoint->ServiceID != 0) { + /* endpoint already in use! */ + AR_DEBUG_ASSERT(FALSE); + break; + } + + /* return assigned endpoint to caller */ + pConnectResp->Endpoint = assignedEndpoint; + pConnectResp->MaxMsgLength = maxMsgSize; + + /* setup the endpoint */ + pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */ + pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth; + pEndpoint->MaxMsgLength = maxMsgSize; + /* copy all the callbacks */ + pEndpoint->EpCallBacks = pConnectReq->EpCallbacks; + /* set the credit distribution info for this endpoint, this information is + * passed back to the credit distribution callback function */ + pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID; + pEndpoint->CreditDist.pHTCReserved = pEndpoint; + pEndpoint->CreditDist.Endpoint = assignedEndpoint; + pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize; + + if (pConnectReq->MaxSendMsgSize != 0) { + /* override TxCreditsPerMaxMsg calculation, this optimizes the credit-low indications + * since the host will actually issue smaller messages in the Send path */ + if (pConnectReq->MaxSendMsgSize > maxMsgSize) { + /* can't be larger than the maximum the target can support */ + AR_DEBUG_ASSERT(FALSE); + break; + } + pEndpoint->CreditDist.TxCreditsPerMaxMsg = pConnectReq->MaxSendMsgSize / target->TargetCreditSize; + } else { + pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize; + } + + if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) { + pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1; + } + + /* save local connection flags */ + pEndpoint->LocalConnectionFlags = pConnectReq->LocalConnectionFlags; + + status = A_OK; + + } while (FALSE); + + if (pSendPacket != NULL) { + HTC_FREE_CONTROL_TX(target,pSendPacket); + } + + if (pRecvPacket != NULL) { + HTC_FREE_CONTROL_RX(target,pRecvPacket); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n")); + + return status; +} + +static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry; + + if (NULL == target->EpCreditDistributionListHead) { + target->EpCreditDistributionListHead = pEpDist; + pEpDist->pNext = NULL; + pEpDist->pPrev = NULL; + return; + } + + /* queue to the end of the list, this does not have to be very + * fast since this list is built at startup time */ + pCurEntry = target->EpCreditDistributionListHead; + + while (pCurEntry) { + pLastEntry = pCurEntry; + pCurEntry = pCurEntry->pNext; + } + + pLastEntry->pNext = pEpDist; + pEpDist->pPrev = pLastEntry; + pEpDist->pNext = NULL; +} + + + +/* default credit init callback */ +static void HTCDefaultCreditInit(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int totalEps = 0; + int creditsPerEndpoint; + + pCurEpDist = pEPList; + /* first run through the list and figure out how many endpoints we are dealing with */ + while (pCurEpDist != NULL) { + pCurEpDist = pCurEpDist->pNext; + totalEps++; + } + + /* even distribution */ + creditsPerEndpoint = TotalCredits/totalEps; + + pCurEpDist = pEPList; + /* run through the list and set minimum and normal credits and + * provide the endpoint with some credits to start */ + while (pCurEpDist != NULL) { + + if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) { + /* too many endpoints and not enough credits */ + AR_DEBUG_ASSERT(FALSE); + break; + } + /* our minimum is set for at least 1 max message */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + /* this value is ignored by our credit alg, since we do + * not dynamically adjust credits, this is the policy of + * the "default" credit distribution, something simple and easy */ + pCurEpDist->TxCreditsNorm = 0xFFFF; + /* give the endpoint minimum credits */ + pCurEpDist->TxCredits = creditsPerEndpoint; + pCurEpDist->TxCreditsAssigned = creditsPerEndpoint; + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* default credit distribution callback, NOTE, this callback holds the TX lock */ +void HTCDefaultCreditDist(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + + if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) { + pCurEpDist = pEPDistList; + /* simple distribution */ + while (pCurEpDist != NULL) { + if (pCurEpDist->TxCreditsToDist > 0) { + /* just give the endpoint back the credits */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + pCurEpDist->TxCreditsToDist = 0; + } + pCurEpDist = pCurEpDist->pNext; + } + } + + /* note we do not need to handle the other reason codes as this is a very + * simple distribution scheme, no need to seek for more credits or handle inactivity */ +} + +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength) +{ + HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle); + int i; + int ep; + + if (CreditInitFunc != NULL) { + /* caller has supplied their own distribution functions */ + target->InitCredits = CreditInitFunc; + AR_DEBUG_ASSERT(CreditDistFunc != NULL); + target->DistributeCredits = CreditDistFunc; + target->pCredDistContext = pCreditDistContext; + } else { + /* caller wants HTC to do distribution */ + /* if caller wants service to handle distributions then + * it must set both of these to NULL! */ + AR_DEBUG_ASSERT(CreditDistFunc == NULL); + target->InitCredits = HTCDefaultCreditInit; + target->DistributeCredits = HTCDefaultCreditDist; + target->pCredDistContext = target; + } + + /* always add HTC control endpoint first, we only expose the list after the + * first one, this is added for TX queue checking */ + AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist); + + /* build the list of credit distribution structures in priority order + * supplied by the caller, these will follow endpoint 0 */ + for (i = 0; i < ListLength; i++) { + /* match services with endpoints and add the endpoints to the distribution list + * in FIFO order */ + for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) { + if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) { + /* queue this one to the list */ + AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist); + break; + } + } + AR_DEBUG_ASSERT(ep < ENDPOINT_MAX); + } + +} diff --git a/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h b/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h new file mode 100644 index 000000000000..9e071548ed92 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/AR6002_regdump.h @@ -0,0 +1,57 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2006 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __AR6002_REGDUMP_H__ +#define __AR6002_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + A_UINT32 xt_pc; + A_UINT32 xt_ps; + A_UINT32 xt_sar; + A_UINT32 xt_vpri; + A_UINT32 xt_a2; + A_UINT32 xt_a3; + A_UINT32 xt_a4; + A_UINT32 xt_a5; + A_UINT32 xt_exccause; + A_UINT32 xt_lcount; + A_UINT32 xt_lbeg; + A_UINT32 xt_lend; + + A_UINT32 epc1, epc2, epc3, epc4; + + /* Extra info to simplify post-mortem stack walkback */ +#define AR6002_REGDUMP_FRAMES 10 + struct { + A_UINT32 a0; /* pc */ + A_UINT32 a1; /* sp */ + A_UINT32 a2; + A_UINT32 a3; + } wb[AR6002_REGDUMP_FRAMES]; +}; +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __AR6002_REGDUMP_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h b/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h new file mode 100644 index 000000000000..ca45848c3caa --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/AR6K_version.h @@ -0,0 +1,47 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define __VER_MAJOR_ 3 +#define __VER_MINOR_ 0 +#define __VER_PATCH_ 0 + +/* The makear6ksdk script (used for release builds) modifies the following line. */ +#define __BUILD_NUMBER_ 1057 + + +/* Format of the version number. */ +#define VER_MAJOR_BIT_OFFSET 28 +#define VER_MINOR_BIT_OFFSET 24 +#define VER_PATCH_BIT_OFFSET 16 +#define VER_BUILD_NUM_BIT_OFFSET 0 + + +/* + * The version has the following format: + * Bits 28-31: Major version + * Bits 24-27: Minor version + * Bits 16-23: Patch version + * Bits 0-15: Build number (automatically generated during build process ) + * E.g. Build 1.1.3.7 would be represented as 0x11030007. + * + * DO NOT split the following macro into multiple lines as this may confuse the build scripts. + */ +#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) ) + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/addrs.h b/drivers/net/wireless/ath6kl/include/AR6002/addrs.h new file mode 100644 index 000000000000..bbb647fb942a --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/addrs.h @@ -0,0 +1,86 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __ADDRS_H__ +#define __ADDRS_H__ + +/* + * Special AR6002 Addresses that may be needed by special + * applications (e.g. ART) on the Host as well as Target. + */ + +#if defined(AR6002_REV2) +#define AR6K_RAM_START 0x00500000 +#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff) +#define TARG_RAM_SZ (184*1024) +#define TARG_ROM_SZ (80*1024) +#endif +#if defined(AR6002_REV4) || defined(AR6003) +#define AR6K_RAM_START 0x00540000 +#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000) +#define TARG_RAM_SZ (256*1024) +#define TARG_ROM_SZ (256*1024) +#endif + +#define AR6002_BOARD_DATA_SZ 768 +#define AR6003_BOARD_DATA_SZ 1024 + +#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset)) +#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset) + +#define AR6K_ROM_START 0x004e0000 +#define TARG_ROM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x1fffff) - 0xe0000) +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +/* + * At this ROM address is a pointer to the start of the ROM DataSet Index. + * If there are no ROM DataSets, there's a 0 at this address. + */ +#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8) +#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4) + +/* + * The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to + * board data. + */ + +/* Size of Board Data, in bytes */ +#if defined(AR6002_REV4) || defined(AR6003) +#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ +#else +#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ +#endif + + +/* + * Constants used by ASM code to access fields of host_interest_s, + * which is at a fixed location in RAM. + */ +#if defined(AR6002_REV4) || defined(AR6003) +#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x60c) +#else +#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c) +#endif +#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR + +#endif /* __ADDRS_H__ */ + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h new file mode 100644 index 000000000000..28b972afc8d7 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_intf_reg.h @@ -0,0 +1,83 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_INTF_REG_REG_H_ +#define _ANALOG_INTF_REG_REG_H_ + +#define SW_OVERRIDE_ADDRESS 0x00000080 +#define SW_OVERRIDE_OFFSET 0x00000080 +#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002 +#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB) +#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK) +#define SW_OVERRIDE_ENABLE_MSB 0 +#define SW_OVERRIDE_ENABLE_LSB 0 +#define SW_OVERRIDE_ENABLE_MASK 0x00000001 +#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB) +#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK) + +#define SIN_VAL_ADDRESS 0x00000084 +#define SIN_VAL_OFFSET 0x00000084 +#define SIN_VAL_SIN_MSB 0 +#define SIN_VAL_SIN_LSB 0 +#define SIN_VAL_SIN_MASK 0x00000001 +#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB) +#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK) + +#define SW_SCLK_ADDRESS 0x00000088 +#define SW_SCLK_OFFSET 0x00000088 +#define SW_SCLK_SW_SCLK_MSB 0 +#define SW_SCLK_SW_SCLK_LSB 0 +#define SW_SCLK_SW_SCLK_MASK 0x00000001 +#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB) +#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK) + +#define SW_CNTL_ADDRESS 0x0000008c +#define SW_CNTL_OFFSET 0x0000008c +#define SW_CNTL_SW_SCAPTURE_MSB 2 +#define SW_CNTL_SW_SCAPTURE_LSB 2 +#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004 +#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB) +#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK) +#define SW_CNTL_SW_SUPDATE_MSB 1 +#define SW_CNTL_SW_SUPDATE_LSB 1 +#define SW_CNTL_SW_SUPDATE_MASK 0x00000002 +#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB) +#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK) +#define SW_CNTL_SW_SOUT_MSB 0 +#define SW_CNTL_SW_SOUT_LSB 0 +#define SW_CNTL_SW_SOUT_MASK 0x00000001 +#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB) +#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_reg_reg_s { + unsigned char pad0[128]; /* pad to 0x80 */ + volatile unsigned int sw_override; + volatile unsigned int sin_val; + volatile unsigned int sw_sclk; + volatile unsigned int sw_cntl; +} analog_intf_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h new file mode 100644 index 000000000000..c485ac725c2f --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/analog_reg.h @@ -0,0 +1,1951 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_REG_REG_H_ +#define _ANALOG_REG_REG_H_ + +#define SYNTH_SYNTH1_ADDRESS 0x00000000 +#define SYNTH_SYNTH1_OFFSET 0x00000000 +#define SYNTH_SYNTH1_PWD_BIAS_MSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_LSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB) +#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK) +#define SYNTH_SYNTH1_PWD_CP_MSB 30 +#define SYNTH_SYNTH1_PWD_CP_LSB 30 +#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000 +#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB) +#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK) +#define SYNTH_SYNTH1_PWD_VCMON_MSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_LSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB) +#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK) +#define SYNTH_SYNTH1_PWD_VCO_MSB 28 +#define SYNTH_SYNTH1_PWD_VCO_LSB 28 +#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000 +#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB) +#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK) +#define SYNTH_SYNTH1_PWD_PRESC_MSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_LSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB) +#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK) +#define SYNTH_SYNTH1_PWD_LODIV_MSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_LSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000 +#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB) +#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK) +#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000 +#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB) +#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK) +#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000 +#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB) +#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) +#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000 +#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB) +#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) +#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000 +#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB) +#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) +#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21 +#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20 +#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000 +#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB) +#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) +#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19 +#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18 +#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000 +#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB) +#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK) +#define SYNTH_SYNTH1_SLIDINGIF_MSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_LSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000 +#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB) +#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK) +#define SYNTH_SYNTH1_SPARE_PWD_MSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_LSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000 +#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB) +#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK) +#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000 +#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB) +#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000 +#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB) +#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000 +#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB) +#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) +#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12 +#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10 +#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00 +#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB) +#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_MSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_LSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020 +#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK) +#define SYNTH_SYNTH1_MONITOR_REF_MSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_LSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010 +#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB) +#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) + +#define SYNTH_SYNTH2_ADDRESS 0x00000004 +#define SYNTH_SYNTH2_OFFSET 0x00000004 +#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31 +#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29 +#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB) +#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK) +#define SYNTH_SYNTH2_VC_HI_REF_MSB 28 +#define SYNTH_SYNTH2_VC_HI_REF_LSB 26 +#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB) +#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK) +#define SYNTH_SYNTH2_VC_MID_REF_MSB 25 +#define SYNTH_SYNTH2_VC_MID_REF_LSB 23 +#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB) +#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK) +#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22 +#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20 +#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB) +#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) +#define SYNTH_SYNTH2_LOOP_CP_MSB 14 +#define SYNTH_SYNTH2_LOOP_CP_LSB 10 +#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00 +#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB) +#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK) +#define SYNTH_SYNTH2_LOOP_RS_MSB 9 +#define SYNTH_SYNTH2_LOOP_RS_LSB 5 +#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0 +#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB) +#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK) +#define SYNTH_SYNTH2_LOOP_CS_MSB 4 +#define SYNTH_SYNTH2_LOOP_CS_LSB 3 +#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018 +#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB) +#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK) +#define SYNTH_SYNTH2_SPARE_BITS_MSB 2 +#define SYNTH_SYNTH2_SPARE_BITS_LSB 0 +#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007 +#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB) +#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK) + +#define SYNTH_SYNTH3_ADDRESS 0x00000008 +#define SYNTH_SYNTH3_OFFSET 0x00000008 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) +#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23 +#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18 +#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) + +#define SYNTH_SYNTH4_ADDRESS 0x0000000c +#define SYNTH_SYNTH4_OFFSET 0x0000000c +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) +#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB) +#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) +#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB) +#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK) +#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB) +#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) +#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25 +#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18 +#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB) +#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) +#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB) +#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) +#define SYNTH_SYNTH4_REFDIVSEL_MSB 16 +#define SYNTH_SYNTH4_REFDIVSEL_LSB 15 +#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000 +#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB) +#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK) +#define SYNTH_SYNTH4_PFDDELAY_MSB 14 +#define SYNTH_SYNTH4_PFDDELAY_LSB 14 +#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000 +#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB) +#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK) +#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB) +#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK) +#define SYNTH_SYNTH4_PRESCSEL_MSB 12 +#define SYNTH_SYNTH4_PRESCSEL_LSB 11 +#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800 +#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB) +#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK) +#define SYNTH_SYNTH4_RESET_PRESC_MSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_LSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB) +#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK) +#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB) +#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK) +#define SYNTH_SYNTH4_SDM_MODE_MSB 8 +#define SYNTH_SYNTH4_SDM_MODE_LSB 8 +#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100 +#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB) +#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK) +#define SYNTH_SYNTH4_SDM_DITHER_MSB 7 +#define SYNTH_SYNTH4_SDM_DITHER_LSB 6 +#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB) +#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) +#define SYNTH_SYNTH4_SPARE_MISC_MSB 3 +#define SYNTH_SYNTH4_SPARE_MISC_LSB 2 +#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c +#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB) +#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK) +#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB) +#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) + +#define SYNTH_SYNTH5_ADDRESS 0x00000010 +#define SYNTH_SYNTH5_OFFSET 0x00000010 +#define SYNTH_SYNTH5_LOOP_IP0_MSB 31 +#define SYNTH_SYNTH5_LOOP_IP0_LSB 28 +#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000 +#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB) +#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK) +#define SYNTH_SYNTH5_SLOPE_IP_MSB 27 +#define SYNTH_SYNTH5_SLOPE_IP_LSB 25 +#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000 +#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB) +#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK) +#define SYNTH_SYNTH5_CPBIAS_MSB 24 +#define SYNTH_SYNTH5_CPBIAS_LSB 23 +#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000 +#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB) +#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK) +#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000 +#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB) +#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) +#define SYNTH_SYNTH5_CPLOWLK_MSB 21 +#define SYNTH_SYNTH5_CPLOWLK_LSB 21 +#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000 +#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB) +#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK) +#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20 +#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17 +#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000 +#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB) +#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) +#define SYNTH_SYNTH5_CAPRANGE1_MSB 16 +#define SYNTH_SYNTH5_CAPRANGE1_LSB 13 +#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000 +#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB) +#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK) +#define SYNTH_SYNTH5_CAPRANGE2_MSB 12 +#define SYNTH_SYNTH5_CAPRANGE2_LSB 9 +#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00 +#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB) +#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK) +#define SYNTH_SYNTH5_CAPRANGE3_MSB 8 +#define SYNTH_SYNTH5_CAPRANGE3_LSB 5 +#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0 +#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB) +#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) +#define SYNTH_SYNTH5_SPARE_MSB 1 +#define SYNTH_SYNTH5_SPARE_LSB 0 +#define SYNTH_SYNTH5_SPARE_MASK 0x00000003 +#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB) +#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK) + +#define SYNTH_SYNTH6_ADDRESS 0x00000014 +#define SYNTH_SYNTH6_OFFSET 0x00000014 +#define SYNTH_SYNTH6_IRCP_MSB 31 +#define SYNTH_SYNTH6_IRCP_LSB 29 +#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000 +#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB) +#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK) +#define SYNTH_SYNTH6_IRVCMON_MSB 28 +#define SYNTH_SYNTH6_IRVCMON_LSB 26 +#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000 +#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB) +#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK) +#define SYNTH_SYNTH6_IRSPARE_MSB 25 +#define SYNTH_SYNTH6_IRSPARE_LSB 23 +#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000 +#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB) +#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK) +#define SYNTH_SYNTH6_ICPRESC_MSB 22 +#define SYNTH_SYNTH6_ICPRESC_LSB 20 +#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000 +#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB) +#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK) +#define SYNTH_SYNTH6_ICLODIV_MSB 19 +#define SYNTH_SYNTH6_ICLODIV_LSB 17 +#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000 +#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB) +#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK) +#define SYNTH_SYNTH6_ICLOMIX_MSB 16 +#define SYNTH_SYNTH6_ICLOMIX_LSB 14 +#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000 +#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB) +#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK) +#define SYNTH_SYNTH6_ICSPAREA_MSB 13 +#define SYNTH_SYNTH6_ICSPAREA_LSB 11 +#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800 +#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB) +#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK) +#define SYNTH_SYNTH6_ICSPAREB_MSB 10 +#define SYNTH_SYNTH6_ICSPAREB_LSB 8 +#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700 +#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB) +#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK) +#define SYNTH_SYNTH6_ICVCO_MSB 7 +#define SYNTH_SYNTH6_ICVCO_LSB 5 +#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0 +#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB) +#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK) +#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4 +#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3 +#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018 +#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB) +#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) +#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2 +#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0 +#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007 +#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB) +#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK) + +#define SYNTH_SYNTH7_ADDRESS 0x00000018 +#define SYNTH_SYNTH7_OFFSET 0x00000018 +#define SYNTH_SYNTH7_SYNTH_ON_MSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_LSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000 +#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB) +#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) +#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000 +#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB) +#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) +#define SYNTH_SYNTH7_PIN_VC_MSB 24 +#define SYNTH_SYNTH7_PIN_VC_LSB 24 +#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000 +#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB) +#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK) +#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23 +#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16 +#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000 +#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB) +#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) +#define SYNTH_SYNTH7_SHORT_R_MSB 15 +#define SYNTH_SYNTH7_SHORT_R_LSB 15 +#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000 +#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB) +#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK) +#define SYNTH_SYNTH7_RESET_RFD_MSB 14 +#define SYNTH_SYNTH7_RESET_RFD_LSB 14 +#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000 +#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB) +#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK) +#define SYNTH_SYNTH7_RESET_PFD_MSB 13 +#define SYNTH_SYNTH7_RESET_PFD_LSB 13 +#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000 +#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB) +#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) +#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800 +#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB) +#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK) +#define SYNTH_SYNTH7_VC2HIGH_MSB 10 +#define SYNTH_SYNTH7_VC2HIGH_LSB 10 +#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400 +#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB) +#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK) +#define SYNTH_SYNTH7_VC2LOW_MSB 9 +#define SYNTH_SYNTH7_VC2LOW_LSB 9 +#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200 +#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB) +#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK) +#define SYNTH_SYNTH7_LOOP_IP_MSB 8 +#define SYNTH_SYNTH7_LOOP_IP_LSB 5 +#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0 +#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB) +#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK) +#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3 +#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018 +#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH7_SPARE_READ_MSB 2 +#define SYNTH_SYNTH7_SPARE_READ_LSB 0 +#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007 +#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB) +#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK) + +#define SYNTH_SYNTH8_ADDRESS 0x0000001c +#define SYNTH_SYNTH8_OFFSET 0x0000001c +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) +#define SYNTH_SYNTH8_FRACMODE_MSB 30 +#define SYNTH_SYNTH8_FRACMODE_LSB 30 +#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000 +#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB) +#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK) +#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29 +#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28 +#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000 +#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB) +#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK) +#define SYNTH_SYNTH8_SPARE_MSB 27 +#define SYNTH_SYNTH8_SPARE_LSB 27 +#define SYNTH_SYNTH8_SPARE_MASK 0x08000000 +#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB) +#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK) +#define SYNTH_SYNTH8_CHANSEL_MSB 26 +#define SYNTH_SYNTH8_CHANSEL_LSB 18 +#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000 +#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB) +#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK) +#define SYNTH_SYNTH8_CHANFRAC_MSB 17 +#define SYNTH_SYNTH8_CHANFRAC_LSB 1 +#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe +#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB) +#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK) +#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001 +#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB) +#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) + +#define RF5G_RF5G1_ADDRESS 0x00000020 +#define RF5G_RF5G1_OFFSET 0x00000020 +#define RF5G_RF5G1_PDTXLO5_MSB 31 +#define RF5G_RF5G1_PDTXLO5_LSB 31 +#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000 +#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB) +#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK) +#define RF5G_RF5G1_PDTXMIX5_MSB 30 +#define RF5G_RF5G1_PDTXMIX5_LSB 30 +#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000 +#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB) +#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK) +#define RF5G_RF5G1_PDTXBUF5_MSB 29 +#define RF5G_RF5G1_PDTXBUF5_LSB 29 +#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000 +#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB) +#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK) +#define RF5G_RF5G1_PDPADRV5_MSB 28 +#define RF5G_RF5G1_PDPADRV5_LSB 28 +#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000 +#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB) +#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK) +#define RF5G_RF5G1_PDPAOUT5_MSB 27 +#define RF5G_RF5G1_PDPAOUT5_LSB 27 +#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000 +#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB) +#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK) +#define RF5G_RF5G1_TUNE_PADRV5_MSB 26 +#define RF5G_RF5G1_TUNE_PADRV5_LSB 24 +#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000 +#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB) +#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK) +#define RF5G_RF5G1_PWDTXPKD_MSB 23 +#define RF5G_RF5G1_PWDTXPKD_LSB 21 +#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000 +#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB) +#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK) +#define RF5G_RF5G1_DB5_MSB 20 +#define RF5G_RF5G1_DB5_LSB 18 +#define RF5G_RF5G1_DB5_MASK 0x001c0000 +#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB) +#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK) +#define RF5G_RF5G1_OB5_MSB 17 +#define RF5G_RF5G1_OB5_LSB 15 +#define RF5G_RF5G1_OB5_MASK 0x00038000 +#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB) +#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK) +#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14 +#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12 +#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000 +#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB) +#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK) +#define RF5G_RF5G1_PDLO5DIV_MSB 11 +#define RF5G_RF5G1_PDLO5DIV_LSB 11 +#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800 +#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB) +#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK) +#define RF5G_RF5G1_PDLO5MIX_MSB 10 +#define RF5G_RF5G1_PDLO5MIX_LSB 10 +#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400 +#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB) +#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK) +#define RF5G_RF5G1_PDQBUF5_MSB 9 +#define RF5G_RF5G1_PDQBUF5_LSB 9 +#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200 +#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB) +#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK) +#define RF5G_RF5G1_PDLO5AGC_MSB 8 +#define RF5G_RF5G1_PDLO5AGC_LSB 8 +#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100 +#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB) +#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK) +#define RF5G_RF5G1_PDREGLO5_MSB 7 +#define RF5G_RF5G1_PDREGLO5_LSB 7 +#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080 +#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB) +#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK) +#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6 +#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4 +#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070 +#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB) +#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK) +#define RF5G_RF5G1_LO5CONTROL_MSB 3 +#define RF5G_RF5G1_LO5CONTROL_LSB 3 +#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008 +#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB) +#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK) +#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004 +#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB) +#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK) +#define RF5G_RF5G1_SPARE_MSB 1 +#define RF5G_RF5G1_SPARE_LSB 0 +#define RF5G_RF5G1_SPARE_MASK 0x00000003 +#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB) +#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK) + +#define RF5G_RF5G2_ADDRESS 0x00000024 +#define RF5G_RF5G2_OFFSET 0x00000024 +#define RF5G_RF5G2_AGCLO_B_MSB 31 +#define RF5G_RF5G2_AGCLO_B_LSB 29 +#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000 +#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB) +#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK) +#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28 +#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26 +#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000 +#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB) +#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK) +#define RF5G_RF5G2_PDCMOSLO5_MSB 25 +#define RF5G_RF5G2_PDCMOSLO5_LSB 25 +#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000 +#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB) +#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK) +#define RF5G_RF5G2_PDVGM5_MSB 24 +#define RF5G_RF5G2_PDVGM5_LSB 24 +#define RF5G_RF5G2_PDVGM5_MASK 0x01000000 +#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB) +#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK) +#define RF5G_RF5G2_PDCSLNA5_MSB 23 +#define RF5G_RF5G2_PDCSLNA5_LSB 23 +#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000 +#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB) +#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK) +#define RF5G_RF5G2_PDRFVGA5_MSB 22 +#define RF5G_RF5G2_PDRFVGA5_LSB 22 +#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000 +#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB) +#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK) +#define RF5G_RF5G2_PDREGFE5_MSB 21 +#define RF5G_RF5G2_PDREGFE5_LSB 21 +#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000 +#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB) +#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK) +#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20 +#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18 +#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000 +#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB) +#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK) +#define RF5G_RF5G2_BRFVGA5_MSB 17 +#define RF5G_RF5G2_BRFVGA5_LSB 15 +#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000 +#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB) +#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK) +#define RF5G_RF5G2_BCSLNA5_MSB 14 +#define RF5G_RF5G2_BCSLNA5_LSB 12 +#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000 +#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB) +#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK) +#define RF5G_RF5G2_BVGM5_MSB 11 +#define RF5G_RF5G2_BVGM5_LSB 9 +#define RF5G_RF5G2_BVGM5_MASK 0x00000e00 +#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB) +#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK) +#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100 +#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB) +#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK) +#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7 +#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6 +#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0 +#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB) +#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) +#define RF5G_RF5G2_ENABLE_PCA_MSB 5 +#define RF5G_RF5G2_ENABLE_PCA_LSB 5 +#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020 +#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB) +#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK) +#define RF5G_RF5G2_TUNE_LO_MSB 4 +#define RF5G_RF5G2_TUNE_LO_LSB 2 +#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c +#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB) +#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK) +#define RF5G_RF5G2_SPARE_MSB 1 +#define RF5G_RF5G2_SPARE_LSB 0 +#define RF5G_RF5G2_SPARE_MASK 0x00000003 +#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB) +#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK) + +#define RF2G_RF2G1_ADDRESS 0x00000028 +#define RF2G_RF2G1_OFFSET 0x00000028 +#define RF2G_RF2G1_BLNA1_MSB 31 +#define RF2G_RF2G1_BLNA1_LSB 29 +#define RF2G_RF2G1_BLNA1_MASK 0xe0000000 +#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB) +#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK) +#define RF2G_RF2G1_BLNA1F_MSB 28 +#define RF2G_RF2G1_BLNA1F_LSB 26 +#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000 +#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB) +#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK) +#define RF2G_RF2G1_BLNA1BUF_MSB 25 +#define RF2G_RF2G1_BLNA1BUF_LSB 23 +#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000 +#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB) +#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK) +#define RF2G_RF2G1_BLNA2_MSB 22 +#define RF2G_RF2G1_BLNA2_LSB 20 +#define RF2G_RF2G1_BLNA2_MASK 0x00700000 +#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB) +#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK) +#define RF2G_RF2G1_DB_MSB 19 +#define RF2G_RF2G1_DB_LSB 17 +#define RF2G_RF2G1_DB_MASK 0x000e0000 +#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB) +#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK) +#define RF2G_RF2G1_OB_MSB 16 +#define RF2G_RF2G1_OB_LSB 14 +#define RF2G_RF2G1_OB_MASK 0x0001c000 +#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB) +#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK) +#define RF2G_RF2G1_FE_ATB_SEL_MSB 13 +#define RF2G_RF2G1_FE_ATB_SEL_LSB 11 +#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800 +#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB) +#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK) +#define RF2G_RF2G1_RF_ATB_SEL_MSB 10 +#define RF2G_RF2G1_RF_ATB_SEL_LSB 8 +#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700 +#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB) +#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK) +#define RF2G_RF2G1_SELLNA_MSB 7 +#define RF2G_RF2G1_SELLNA_LSB 7 +#define RF2G_RF2G1_SELLNA_MASK 0x00000080 +#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB) +#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK) +#define RF2G_RF2G1_LOCONTROL_MSB 6 +#define RF2G_RF2G1_LOCONTROL_LSB 6 +#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040 +#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB) +#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK) +#define RF2G_RF2G1_SHORTLNA2_MSB 5 +#define RF2G_RF2G1_SHORTLNA2_LSB 5 +#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020 +#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB) +#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK) +#define RF2G_RF2G1_SPARE_MSB 4 +#define RF2G_RF2G1_SPARE_LSB 0 +#define RF2G_RF2G1_SPARE_MASK 0x0000001f +#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB) +#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK) + +#define RF2G_RF2G2_ADDRESS 0x0000002c +#define RF2G_RF2G2_OFFSET 0x0000002c +#define RF2G_RF2G2_PDCGLNA_MSB 31 +#define RF2G_RF2G2_PDCGLNA_LSB 31 +#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000 +#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB) +#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK) +#define RF2G_RF2G2_PDCGLNABUF_MSB 30 +#define RF2G_RF2G2_PDCGLNABUF_LSB 30 +#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000 +#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB) +#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK) +#define RF2G_RF2G2_PDCSLNA_MSB 29 +#define RF2G_RF2G2_PDCSLNA_LSB 29 +#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000 +#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB) +#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK) +#define RF2G_RF2G2_PDDIV_MSB 28 +#define RF2G_RF2G2_PDDIV_LSB 28 +#define RF2G_RF2G2_PDDIV_MASK 0x10000000 +#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB) +#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK) +#define RF2G_RF2G2_PDPADRV_MSB 27 +#define RF2G_RF2G2_PDPADRV_LSB 27 +#define RF2G_RF2G2_PDPADRV_MASK 0x08000000 +#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB) +#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK) +#define RF2G_RF2G2_PDPAOUT_MSB 26 +#define RF2G_RF2G2_PDPAOUT_LSB 26 +#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000 +#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB) +#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK) +#define RF2G_RF2G2_PDREGLNA_MSB 25 +#define RF2G_RF2G2_PDREGLNA_LSB 25 +#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000 +#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB) +#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK) +#define RF2G_RF2G2_PDREGLO_MSB 24 +#define RF2G_RF2G2_PDREGLO_LSB 24 +#define RF2G_RF2G2_PDREGLO_MASK 0x01000000 +#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB) +#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK) +#define RF2G_RF2G2_PDRFGM_MSB 23 +#define RF2G_RF2G2_PDRFGM_LSB 23 +#define RF2G_RF2G2_PDRFGM_MASK 0x00800000 +#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB) +#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK) +#define RF2G_RF2G2_PDRXLO_MSB 22 +#define RF2G_RF2G2_PDRXLO_LSB 22 +#define RF2G_RF2G2_PDRXLO_MASK 0x00400000 +#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB) +#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK) +#define RF2G_RF2G2_PDTXLO_MSB 21 +#define RF2G_RF2G2_PDTXLO_LSB 21 +#define RF2G_RF2G2_PDTXLO_MASK 0x00200000 +#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB) +#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK) +#define RF2G_RF2G2_PDTXMIX_MSB 20 +#define RF2G_RF2G2_PDTXMIX_LSB 20 +#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000 +#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB) +#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK) +#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000 +#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB) +#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK) +#define RF2G_RF2G2_REGLO_BYPASS_MSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_LSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000 +#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB) +#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK) +#define RF2G_RF2G2_ENABLE_PCB_MSB 17 +#define RF2G_RF2G2_ENABLE_PCB_LSB 17 +#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000 +#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB) +#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK) +#define RF2G_RF2G2_SPARE_MSB 16 +#define RF2G_RF2G2_SPARE_LSB 0 +#define RF2G_RF2G2_SPARE_MASK 0x0001ffff +#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB) +#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK) + +#define TOP_GAIN_ADDRESS 0x00000030 +#define TOP_GAIN_OFFSET 0x00000030 +#define TOP_GAIN_TX6DBLOQGAIN_MSB 31 +#define TOP_GAIN_TX6DBLOQGAIN_LSB 30 +#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000 +#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB) +#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK) +#define TOP_GAIN_TX1DBLOQGAIN_MSB 29 +#define TOP_GAIN_TX1DBLOQGAIN_LSB 27 +#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000 +#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB) +#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK) +#define TOP_GAIN_TXV2IGAIN_MSB 26 +#define TOP_GAIN_TXV2IGAIN_LSB 25 +#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000 +#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB) +#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK) +#define TOP_GAIN_PABUF5GN_MSB 24 +#define TOP_GAIN_PABUF5GN_LSB 24 +#define TOP_GAIN_PABUF5GN_MASK 0x01000000 +#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB) +#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK) +#define TOP_GAIN_PADRVGN_MSB 23 +#define TOP_GAIN_PADRVGN_LSB 21 +#define TOP_GAIN_PADRVGN_MASK 0x00e00000 +#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB) +#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK) +#define TOP_GAIN_PAOUT2GN_MSB 20 +#define TOP_GAIN_PAOUT2GN_LSB 18 +#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000 +#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB) +#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK) +#define TOP_GAIN_LNAON_MSB 17 +#define TOP_GAIN_LNAON_LSB 17 +#define TOP_GAIN_LNAON_MASK 0x00020000 +#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB) +#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK) +#define TOP_GAIN_LNAGAIN_MSB 16 +#define TOP_GAIN_LNAGAIN_LSB 13 +#define TOP_GAIN_LNAGAIN_MASK 0x0001e000 +#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB) +#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK) +#define TOP_GAIN_RFVGA5GAIN_MSB 12 +#define TOP_GAIN_RFVGA5GAIN_LSB 11 +#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800 +#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB) +#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK) +#define TOP_GAIN_RFGMGN_MSB 10 +#define TOP_GAIN_RFGMGN_LSB 8 +#define TOP_GAIN_RFGMGN_MASK 0x00000700 +#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB) +#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK) +#define TOP_GAIN_RX6DBLOQGAIN_MSB 7 +#define TOP_GAIN_RX6DBLOQGAIN_LSB 6 +#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0 +#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB) +#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK) +#define TOP_GAIN_RX1DBLOQGAIN_MSB 5 +#define TOP_GAIN_RX1DBLOQGAIN_LSB 3 +#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038 +#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB) +#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK) +#define TOP_GAIN_RX6DBHIQGAIN_MSB 2 +#define TOP_GAIN_RX6DBHIQGAIN_LSB 1 +#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006 +#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB) +#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK) +#define TOP_GAIN_SPARE_MSB 0 +#define TOP_GAIN_SPARE_LSB 0 +#define TOP_GAIN_SPARE_MASK 0x00000001 +#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB) +#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK) + +#define TOP_TOP_ADDRESS 0x00000034 +#define TOP_TOP_OFFSET 0x00000034 +#define TOP_TOP_LOCALTXGAIN_MSB 31 +#define TOP_TOP_LOCALTXGAIN_LSB 31 +#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000 +#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB) +#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK) +#define TOP_TOP_LOCALRXGAIN_MSB 30 +#define TOP_TOP_LOCALRXGAIN_LSB 30 +#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000 +#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB) +#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK) +#define TOP_TOP_LOCALMODE_MSB 29 +#define TOP_TOP_LOCALMODE_LSB 29 +#define TOP_TOP_LOCALMODE_MASK 0x20000000 +#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB) +#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK) +#define TOP_TOP_CALFC_MSB 28 +#define TOP_TOP_CALFC_LSB 28 +#define TOP_TOP_CALFC_MASK 0x10000000 +#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB) +#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK) +#define TOP_TOP_CALDC_MSB 27 +#define TOP_TOP_CALDC_LSB 27 +#define TOP_TOP_CALDC_MASK 0x08000000 +#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB) +#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK) +#define TOP_TOP_CAL_RESIDUE_MSB 26 +#define TOP_TOP_CAL_RESIDUE_LSB 26 +#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000 +#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB) +#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK) +#define TOP_TOP_BMODE_MSB 25 +#define TOP_TOP_BMODE_LSB 25 +#define TOP_TOP_BMODE_MASK 0x02000000 +#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB) +#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK) +#define TOP_TOP_SYNTHON_MSB 24 +#define TOP_TOP_SYNTHON_LSB 24 +#define TOP_TOP_SYNTHON_MASK 0x01000000 +#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB) +#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK) +#define TOP_TOP_RXON_MSB 23 +#define TOP_TOP_RXON_LSB 23 +#define TOP_TOP_RXON_MASK 0x00800000 +#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB) +#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK) +#define TOP_TOP_TXON_MSB 22 +#define TOP_TOP_TXON_LSB 22 +#define TOP_TOP_TXON_MASK 0x00400000 +#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB) +#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK) +#define TOP_TOP_PAON_MSB 21 +#define TOP_TOP_PAON_LSB 21 +#define TOP_TOP_PAON_MASK 0x00200000 +#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB) +#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK) +#define TOP_TOP_CALTX_MSB 20 +#define TOP_TOP_CALTX_LSB 20 +#define TOP_TOP_CALTX_MASK 0x00100000 +#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB) +#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK) +#define TOP_TOP_LOCALADDAC_MSB 19 +#define TOP_TOP_LOCALADDAC_LSB 19 +#define TOP_TOP_LOCALADDAC_MASK 0x00080000 +#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB) +#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK) +#define TOP_TOP_PWDPLL_MSB 18 +#define TOP_TOP_PWDPLL_LSB 18 +#define TOP_TOP_PWDPLL_MASK 0x00040000 +#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB) +#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK) +#define TOP_TOP_PWDADC_MSB 17 +#define TOP_TOP_PWDADC_LSB 17 +#define TOP_TOP_PWDADC_MASK 0x00020000 +#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB) +#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK) +#define TOP_TOP_PWDDAC_MSB 16 +#define TOP_TOP_PWDDAC_LSB 16 +#define TOP_TOP_PWDDAC_MASK 0x00010000 +#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB) +#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK) +#define TOP_TOP_LOCALXTAL_MSB 15 +#define TOP_TOP_LOCALXTAL_LSB 15 +#define TOP_TOP_LOCALXTAL_MASK 0x00008000 +#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB) +#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK) +#define TOP_TOP_PWDCLKIN_MSB 14 +#define TOP_TOP_PWDCLKIN_LSB 14 +#define TOP_TOP_PWDCLKIN_MASK 0x00004000 +#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB) +#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK) +#define TOP_TOP_OSCON_MSB 13 +#define TOP_TOP_OSCON_LSB 13 +#define TOP_TOP_OSCON_MASK 0x00002000 +#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB) +#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK) +#define TOP_TOP_SCLKEN_FORCE_MSB 12 +#define TOP_TOP_SCLKEN_FORCE_LSB 12 +#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000 +#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB) +#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK) +#define TOP_TOP_SYNTHON_FORCE_MSB 11 +#define TOP_TOP_SYNTHON_FORCE_LSB 11 +#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800 +#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB) +#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK) +#define TOP_TOP_PDBIAS_MSB 10 +#define TOP_TOP_PDBIAS_LSB 10 +#define TOP_TOP_PDBIAS_MASK 0x00000400 +#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB) +#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK) +#define TOP_TOP_DATAOUTSEL_MSB 9 +#define TOP_TOP_DATAOUTSEL_LSB 8 +#define TOP_TOP_DATAOUTSEL_MASK 0x00000300 +#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB) +#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK) +#define TOP_TOP_REVID_MSB 7 +#define TOP_TOP_REVID_LSB 5 +#define TOP_TOP_REVID_MASK 0x000000e0 +#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB) +#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK) +#define TOP_TOP_INT2PAD_MSB 4 +#define TOP_TOP_INT2PAD_LSB 4 +#define TOP_TOP_INT2PAD_MASK 0x00000010 +#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB) +#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK) +#define TOP_TOP_INTH2PAD_MSB 3 +#define TOP_TOP_INTH2PAD_LSB 3 +#define TOP_TOP_INTH2PAD_MASK 0x00000008 +#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB) +#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK) +#define TOP_TOP_PAD2GND_MSB 2 +#define TOP_TOP_PAD2GND_LSB 2 +#define TOP_TOP_PAD2GND_MASK 0x00000004 +#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB) +#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK) +#define TOP_TOP_INT2GND_MSB 1 +#define TOP_TOP_INT2GND_LSB 1 +#define TOP_TOP_INT2GND_MASK 0x00000002 +#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB) +#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK) +#define TOP_TOP_FORCE_XPAON_MSB 0 +#define TOP_TOP_FORCE_XPAON_LSB 0 +#define TOP_TOP_FORCE_XPAON_MASK 0x00000001 +#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB) +#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK) + +#define BIAS_BIAS_SEL_ADDRESS 0x00000038 +#define BIAS_BIAS_SEL_OFFSET 0x00000038 +#define BIAS_BIAS_SEL_PADON_MSB 31 +#define BIAS_BIAS_SEL_PADON_LSB 31 +#define BIAS_BIAS_SEL_PADON_MASK 0x80000000 +#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB) +#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK) +#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30 +#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25 +#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000 +#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB) +#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK) +#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24 +#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21 +#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000 +#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_SPARE_MSB 20 +#define BIAS_BIAS_SEL_SPARE_LSB 20 +#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000 +#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e +#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) +#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001 +#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB) +#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) + +#define BIAS_BIAS1_ADDRESS 0x0000003c +#define BIAS_BIAS1_OFFSET 0x0000003c +#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31 +#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29 +#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000 +#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB) +#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) +#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28 +#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26 +#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000 +#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB) +#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) +#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25 +#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23 +#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000 +#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB) +#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) +#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22 +#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20 +#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000 +#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000 +#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000 +#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) +#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000 +#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB) +#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13 +#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11 +#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800 +#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) +#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7 +#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5 +#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0 +#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB) +#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c +#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) +#define BIAS_BIAS1_SPARE_MSB 1 +#define BIAS_BIAS1_SPARE_LSB 0 +#define BIAS_BIAS1_SPARE_MASK 0x00000003 +#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB) +#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK) + +#define BIAS_BIAS2_ADDRESS 0x00000040 +#define BIAS_BIAS2_OFFSET 0x00000040 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31 +#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000 +#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB) +#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) +#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28 +#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26 +#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000 +#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB) +#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) +#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25 +#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23 +#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000 +#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IRPLL25_MSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_LSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000 +#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB) +#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK) +#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21 +#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19 +#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000 +#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB) +#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK) +#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18 +#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16 +#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000 +#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB) +#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK) +#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15 +#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13 +#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000 +#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB) +#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK) +#define BIAS_BIAS2_PWD_IRLDO25_MSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_LSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000 +#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB) +#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) +#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8 +#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6 +#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0 +#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) + +#define BIAS_BIAS3_ADDRESS 0x00000044 +#define BIAS_BIAS3_OFFSET 0x00000044 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) +#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) +#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28 +#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26 +#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000 +#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB) +#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) +#define BIAS_BIAS3_PWD_ICDAC50_MSB 25 +#define BIAS_BIAS3_PWD_ICDAC50_LSB 23 +#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000 +#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB) +#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK) +#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000 +#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB) +#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) +#define BIAS_BIAS3_PWD_ICBB50_MSB 21 +#define BIAS_BIAS3_PWD_ICBB50_LSB 21 +#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000 +#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB) +#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK) +#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20 +#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18 +#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000 +#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB) +#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) +#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000 +#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB) +#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) +#define BIAS_BIAS3_PWD_IRBB50_MSB 16 +#define BIAS_BIAS3_PWD_IRBB50_LSB 16 +#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000 +#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB) +#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15 +#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13 +#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000 +#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12 +#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10 +#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00 +#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9 +#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7 +#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380 +#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6 +#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4 +#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070 +#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) +#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3 +#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1 +#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e +#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB) +#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) +#define BIAS_BIAS3_SPARE_MSB 0 +#define BIAS_BIAS3_SPARE_LSB 0 +#define BIAS_BIAS3_SPARE_MASK 0x00000001 +#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB) +#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK) + +#define TXPC_TXPC_ADDRESS 0x00000048 +#define TXPC_TXPC_OFFSET 0x00000048 +#define TXPC_TXPC_SELINTPD_MSB 31 +#define TXPC_TXPC_SELINTPD_LSB 31 +#define TXPC_TXPC_SELINTPD_MASK 0x80000000 +#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB) +#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK) +#define TXPC_TXPC_TEST_MSB 30 +#define TXPC_TXPC_TEST_LSB 30 +#define TXPC_TXPC_TEST_MASK 0x40000000 +#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB) +#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK) +#define TXPC_TXPC_TESTGAIN_MSB 29 +#define TXPC_TXPC_TESTGAIN_LSB 28 +#define TXPC_TXPC_TESTGAIN_MASK 0x30000000 +#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB) +#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK) +#define TXPC_TXPC_TESTDAC_MSB 27 +#define TXPC_TXPC_TESTDAC_LSB 22 +#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000 +#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB) +#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK) +#define TXPC_TXPC_TESTPWDPC_MSB 21 +#define TXPC_TXPC_TESTPWDPC_LSB 21 +#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000 +#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB) +#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK) +#define TXPC_TXPC_CURHALF_MSB 20 +#define TXPC_TXPC_CURHALF_LSB 20 +#define TXPC_TXPC_CURHALF_MASK 0x00100000 +#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB) +#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK) +#define TXPC_TXPC_NEGOUT_MSB 19 +#define TXPC_TXPC_NEGOUT_LSB 19 +#define TXPC_TXPC_NEGOUT_MASK 0x00080000 +#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB) +#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK) +#define TXPC_TXPC_CLKDELAY_MSB 18 +#define TXPC_TXPC_CLKDELAY_LSB 18 +#define TXPC_TXPC_CLKDELAY_MASK 0x00040000 +#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB) +#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK) +#define TXPC_TXPC_SELMODREF_MSB 17 +#define TXPC_TXPC_SELMODREF_LSB 17 +#define TXPC_TXPC_SELMODREF_MASK 0x00020000 +#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB) +#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK) +#define TXPC_TXPC_SELCMOUT_MSB 16 +#define TXPC_TXPC_SELCMOUT_LSB 16 +#define TXPC_TXPC_SELCMOUT_MASK 0x00010000 +#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB) +#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK) +#define TXPC_TXPC_TSMODE_MSB 15 +#define TXPC_TXPC_TSMODE_LSB 14 +#define TXPC_TXPC_TSMODE_MASK 0x0000c000 +#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB) +#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK) +#define TXPC_TXPC_N_MSB 13 +#define TXPC_TXPC_N_LSB 6 +#define TXPC_TXPC_N_MASK 0x00003fc0 +#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB) +#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK) +#define TXPC_TXPC_ON1STSYNTHON_MSB 5 +#define TXPC_TXPC_ON1STSYNTHON_LSB 5 +#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020 +#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB) +#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK) +#define TXPC_TXPC_SELINIT_MSB 4 +#define TXPC_TXPC_SELINIT_LSB 3 +#define TXPC_TXPC_SELINIT_MASK 0x00000018 +#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB) +#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK) +#define TXPC_TXPC_SELCOUNT_MSB 2 +#define TXPC_TXPC_SELCOUNT_LSB 2 +#define TXPC_TXPC_SELCOUNT_MASK 0x00000004 +#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB) +#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK) +#define TXPC_TXPC_ATBSEL_MSB 1 +#define TXPC_TXPC_ATBSEL_LSB 0 +#define TXPC_TXPC_ATBSEL_MASK 0x00000003 +#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB) +#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK) + +#define TXPC_MISC_ADDRESS 0x0000004c +#define TXPC_MISC_OFFSET 0x0000004c +#define TXPC_MISC_FLIPBMODE_MSB 31 +#define TXPC_MISC_FLIPBMODE_LSB 31 +#define TXPC_MISC_FLIPBMODE_MASK 0x80000000 +#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB) +#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK) +#define TXPC_MISC_LEVEL_MSB 30 +#define TXPC_MISC_LEVEL_LSB 29 +#define TXPC_MISC_LEVEL_MASK 0x60000000 +#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB) +#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK) +#define TXPC_MISC_LDO_TEST_MODE_MSB 28 +#define TXPC_MISC_LDO_TEST_MODE_LSB 28 +#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000 +#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB) +#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK) +#define TXPC_MISC_NOTCXODET_MSB 27 +#define TXPC_MISC_NOTCXODET_LSB 27 +#define TXPC_MISC_NOTCXODET_MASK 0x08000000 +#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB) +#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK) +#define TXPC_MISC_PWDCLKIND_MSB 26 +#define TXPC_MISC_PWDCLKIND_LSB 26 +#define TXPC_MISC_PWDCLKIND_MASK 0x04000000 +#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB) +#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK) +#define TXPC_MISC_PWDXINPAD_MSB 25 +#define TXPC_MISC_PWDXINPAD_LSB 25 +#define TXPC_MISC_PWDXINPAD_MASK 0x02000000 +#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB) +#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK) +#define TXPC_MISC_LOCALBIAS_MSB 24 +#define TXPC_MISC_LOCALBIAS_LSB 24 +#define TXPC_MISC_LOCALBIAS_MASK 0x01000000 +#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB) +#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK) +#define TXPC_MISC_LOCALBIAS2X_MSB 23 +#define TXPC_MISC_LOCALBIAS2X_LSB 23 +#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000 +#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB) +#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK) +#define TXPC_MISC_SELTSP_MSB 22 +#define TXPC_MISC_SELTSP_LSB 22 +#define TXPC_MISC_SELTSP_MASK 0x00400000 +#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB) +#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK) +#define TXPC_MISC_SELTSN_MSB 21 +#define TXPC_MISC_SELTSN_LSB 21 +#define TXPC_MISC_SELTSN_MASK 0x00200000 +#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB) +#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK) +#define TXPC_MISC_SPARE_A_MSB 20 +#define TXPC_MISC_SPARE_A_LSB 18 +#define TXPC_MISC_SPARE_A_MASK 0x001c0000 +#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB) +#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK) +#define TXPC_MISC_DECOUT_MSB 17 +#define TXPC_MISC_DECOUT_LSB 8 +#define TXPC_MISC_DECOUT_MASK 0x0003ff00 +#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB) +#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK) +#define TXPC_MISC_XTALDIV_MSB 7 +#define TXPC_MISC_XTALDIV_LSB 6 +#define TXPC_MISC_XTALDIV_MASK 0x000000c0 +#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB) +#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK) +#define TXPC_MISC_SPARE_MSB 5 +#define TXPC_MISC_SPARE_LSB 0 +#define TXPC_MISC_SPARE_MASK 0x0000003f +#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB) +#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK) + +#define RXTXBB_RXTXBB1_ADDRESS 0x00000050 +#define RXTXBB_RXTXBB1_OFFSET 0x00000050 +#define RXTXBB_RXTXBB1_SPARE_MSB 31 +#define RXTXBB_RXTXBB1_SPARE_LSB 19 +#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000 +#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB) +#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK) +#define RXTXBB_RXTXBB1_FNOTCH_MSB 18 +#define RXTXBB_RXTXBB1_FNOTCH_LSB 17 +#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000 +#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB) +#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK) +#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16 +#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9 +#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00 +#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB) +#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) +#define RXTXBB_RXTXBB1_PDV2I_MSB 7 +#define RXTXBB_RXTXBB1_PDV2I_LSB 7 +#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080 +#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB) +#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK) +#define RXTXBB_RXTXBB1_PDI2V_MSB 6 +#define RXTXBB_RXTXBB1_PDI2V_LSB 6 +#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040 +#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB) +#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK) +#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020 +#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB) +#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) +#define RXTXBB_RXTXBB1_PDLOQ_MSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_LSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002 +#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB) +#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK) +#define RXTXBB_RXTXBB1_PDHIQ_MSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_LSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001 +#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB) +#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK) + +#define RXTXBB_RXTXBB2_ADDRESS 0x00000054 +#define RXTXBB_RXTXBB2_OFFSET 0x00000054 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) +#define RXTXBB_RXTXBB2_SPARE_MSB 22 +#define RXTXBB_RXTXBB2_SPARE_LSB 21 +#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000 +#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB) +#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK) +#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000 +#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB) +#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) +#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000 +#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB) +#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) +#define RXTXBB_RXTXBB2_CMSEL_MSB 14 +#define RXTXBB_RXTXBB2_CMSEL_LSB 13 +#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000 +#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB) +#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK) +#define RXTXBB_RXTXBB2_FILTERFC_MSB 12 +#define RXTXBB_RXTXBB2_FILTERFC_LSB 8 +#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00 +#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB) +#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) + +#define RXTXBB_RXTXBB3_ADDRESS 0x00000058 +#define RXTXBB_RXTXBB3_OFFSET 0x00000058 +#define RXTXBB_RXTXBB3_SPARE_MSB 31 +#define RXTXBB_RXTXBB3_SPARE_LSB 27 +#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000 +#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB) +#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) + +#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c +#define RXTXBB_RXTXBB4_OFFSET 0x0000005c +#define RXTXBB_RXTXBB4_SPARE_MSB 31 +#define RXTXBB_RXTXBB4_SPARE_LSB 31 +#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000 +#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB) +#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK) +#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000 +#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB) +#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29 +#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25 +#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000 +#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) + +#define ADDAC_ADDAC1_ADDRESS 0x00000060 +#define ADDAC_ADDAC1_OFFSET 0x00000060 +#define ADDAC_ADDAC1_PLL_SVREG_MSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_LSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000 +#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB) +#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK) +#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30 +#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28 +#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000 +#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB) +#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) +#define ADDAC_ADDAC1_PLL_ATB_MSB 27 +#define ADDAC_ADDAC1_PLL_ATB_LSB 26 +#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000 +#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB) +#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK) +#define ADDAC_ADDAC1_PLL_ICP_MSB 25 +#define ADDAC_ADDAC1_PLL_ICP_LSB 23 +#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000 +#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB) +#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK) +#define ADDAC_ADDAC1_PLL_FILTER_MSB 22 +#define ADDAC_ADDAC1_PLL_FILTER_LSB 15 +#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000 +#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB) +#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK) +#define ADDAC_ADDAC1_PWDPLL_MSB 14 +#define ADDAC_ADDAC1_PWDPLL_LSB 14 +#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000 +#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB) +#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK) +#define ADDAC_ADDAC1_PWDADC_MSB 13 +#define ADDAC_ADDAC1_PWDADC_LSB 13 +#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000 +#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB) +#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK) +#define ADDAC_ADDAC1_PWDDAC_MSB 12 +#define ADDAC_ADDAC1_PWDDAC_LSB 12 +#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000 +#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB) +#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK) +#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800 +#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB) +#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) +#define ADDAC_ADDAC1_SELMANPWDS_MSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_LSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400 +#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB) +#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK) +#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200 +#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB) +#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) +#define ADDAC_ADDAC1_CM_SEL_MSB 8 +#define ADDAC_ADDAC1_CM_SEL_LSB 7 +#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180 +#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB) +#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) +#define ADDAC_ADDAC1_SPARE_MSB 5 +#define ADDAC_ADDAC1_SPARE_LSB 0 +#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f +#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB) +#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_reg_reg_s { + volatile unsigned int synth_synth1; + volatile unsigned int synth_synth2; + volatile unsigned int synth_synth3; + volatile unsigned int synth_synth4; + volatile unsigned int synth_synth5; + volatile unsigned int synth_synth6; + volatile unsigned int synth_synth7; + volatile unsigned int synth_synth8; + volatile unsigned int rf5g_rf5g1; + volatile unsigned int rf5g_rf5g2; + volatile unsigned int rf2g_rf2g1; + volatile unsigned int rf2g_rf2g2; + volatile unsigned int top_gain; + volatile unsigned int top_top; + volatile unsigned int bias_bias_sel; + volatile unsigned int bias_bias1; + volatile unsigned int bias_bias2; + volatile unsigned int bias_bias3; + volatile unsigned int txpc_txpc; + volatile unsigned int txpc_misc; + volatile unsigned int rxtxbb_rxtxbb1; + volatile unsigned int rxtxbb_rxtxbb2; + volatile unsigned int rxtxbb_rxtxbb3; + volatile unsigned int rxtxbb_rxtxbb4; + volatile unsigned int addac_addac1; +} analog_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h new file mode 100644 index 000000000000..bba885ed1f08 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/apb_map.h @@ -0,0 +1,32 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _APB_MAP_H_ +#define _APB_MAP_H_ + +#define RTC_BASE_ADDRESS 0x00004000 +#define VMC_BASE_ADDRESS 0x00008000 +#define UART_BASE_ADDRESS 0x0000c000 +#define SI_BASE_ADDRESS 0x00010000 +#define GPIO_BASE_ADDRESS 0x00014000 +#define MBOX_BASE_ADDRESS 0x00018000 +#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define MAC_BASE_ADDRESS 0x00020000 + +#endif /* _APB_MAP_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h new file mode 100644 index 000000000000..de88e8cc91bb --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/gpio_reg.h @@ -0,0 +1,996 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _GPIO_REG_REG_H_ +#define _GPIO_REG_REG_H_ + +#define GPIO_OUT_ADDRESS 0x00000000 +#define GPIO_OUT_OFFSET 0x00000000 +#define GPIO_OUT_DATA_MSB 17 +#define GPIO_OUT_DATA_LSB 0 +#define GPIO_OUT_DATA_MASK 0x0003ffff +#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB) +#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK) + +#define GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define GPIO_OUT_W1TS_OFFSET 0x00000004 +#define GPIO_OUT_W1TS_DATA_MSB 17 +#define GPIO_OUT_W1TS_DATA_LSB 0 +#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB) +#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK) + +#define GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define GPIO_OUT_W1TC_OFFSET 0x00000008 +#define GPIO_OUT_W1TC_DATA_MSB 17 +#define GPIO_OUT_W1TC_DATA_LSB 0 +#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB) +#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK) + +#define GPIO_ENABLE_ADDRESS 0x0000000c +#define GPIO_ENABLE_OFFSET 0x0000000c +#define GPIO_ENABLE_DATA_MSB 17 +#define GPIO_ENABLE_DATA_LSB 0 +#define GPIO_ENABLE_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB) +#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK) + +#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define GPIO_ENABLE_W1TS_DATA_MSB 17 +#define GPIO_ENABLE_W1TS_DATA_LSB 0 +#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB) +#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK) + +#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define GPIO_ENABLE_W1TC_DATA_MSB 17 +#define GPIO_ENABLE_W1TC_DATA_LSB 0 +#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB) +#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK) + +#define GPIO_IN_ADDRESS 0x00000018 +#define GPIO_IN_OFFSET 0x00000018 +#define GPIO_IN_DATA_MSB 17 +#define GPIO_IN_DATA_LSB 0 +#define GPIO_IN_DATA_MASK 0x0003ffff +#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB) +#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK) + +#define GPIO_STATUS_ADDRESS 0x0000001c +#define GPIO_STATUS_OFFSET 0x0000001c +#define GPIO_STATUS_INTERRUPT_MSB 17 +#define GPIO_STATUS_INTERRUPT_LSB 0 +#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB) +#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define GPIO_PIN0_ADDRESS 0x00000028 +#define GPIO_PIN0_OFFSET 0x00000028 +#define GPIO_PIN0_CONFIG_MSB 12 +#define GPIO_PIN0_CONFIG_LSB 11 +#define GPIO_PIN0_CONFIG_MASK 0x00001800 +#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB) +#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define GPIO_PIN0_INT_TYPE_MSB 9 +#define GPIO_PIN0_INT_TYPE_LSB 7 +#define GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB) +#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK) +#define GPIO_PIN0_PAD_DRIVER_MSB 2 +#define GPIO_PIN0_PAD_DRIVER_LSB 2 +#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB) +#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK) +#define GPIO_PIN0_SOURCE_MSB 0 +#define GPIO_PIN0_SOURCE_LSB 0 +#define GPIO_PIN0_SOURCE_MASK 0x00000001 +#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB) +#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK) + +#define GPIO_PIN1_ADDRESS 0x0000002c +#define GPIO_PIN1_OFFSET 0x0000002c +#define GPIO_PIN1_CONFIG_MSB 12 +#define GPIO_PIN1_CONFIG_LSB 11 +#define GPIO_PIN1_CONFIG_MASK 0x00001800 +#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB) +#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define GPIO_PIN1_INT_TYPE_MSB 9 +#define GPIO_PIN1_INT_TYPE_LSB 7 +#define GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB) +#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK) +#define GPIO_PIN1_PAD_DRIVER_MSB 2 +#define GPIO_PIN1_PAD_DRIVER_LSB 2 +#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB) +#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK) +#define GPIO_PIN1_SOURCE_MSB 0 +#define GPIO_PIN1_SOURCE_LSB 0 +#define GPIO_PIN1_SOURCE_MASK 0x00000001 +#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB) +#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK) + +#define GPIO_PIN2_ADDRESS 0x00000030 +#define GPIO_PIN2_OFFSET 0x00000030 +#define GPIO_PIN2_CONFIG_MSB 12 +#define GPIO_PIN2_CONFIG_LSB 11 +#define GPIO_PIN2_CONFIG_MASK 0x00001800 +#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB) +#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define GPIO_PIN2_INT_TYPE_MSB 9 +#define GPIO_PIN2_INT_TYPE_LSB 7 +#define GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB) +#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK) +#define GPIO_PIN2_PAD_DRIVER_MSB 2 +#define GPIO_PIN2_PAD_DRIVER_LSB 2 +#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB) +#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK) +#define GPIO_PIN2_SOURCE_MSB 0 +#define GPIO_PIN2_SOURCE_LSB 0 +#define GPIO_PIN2_SOURCE_MASK 0x00000001 +#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB) +#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK) + +#define GPIO_PIN3_ADDRESS 0x00000034 +#define GPIO_PIN3_OFFSET 0x00000034 +#define GPIO_PIN3_CONFIG_MSB 12 +#define GPIO_PIN3_CONFIG_LSB 11 +#define GPIO_PIN3_CONFIG_MASK 0x00001800 +#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB) +#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define GPIO_PIN3_INT_TYPE_MSB 9 +#define GPIO_PIN3_INT_TYPE_LSB 7 +#define GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB) +#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK) +#define GPIO_PIN3_PAD_DRIVER_MSB 2 +#define GPIO_PIN3_PAD_DRIVER_LSB 2 +#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB) +#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK) +#define GPIO_PIN3_SOURCE_MSB 0 +#define GPIO_PIN3_SOURCE_LSB 0 +#define GPIO_PIN3_SOURCE_MASK 0x00000001 +#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB) +#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK) + +#define GPIO_PIN4_ADDRESS 0x00000038 +#define GPIO_PIN4_OFFSET 0x00000038 +#define GPIO_PIN4_CONFIG_MSB 12 +#define GPIO_PIN4_CONFIG_LSB 11 +#define GPIO_PIN4_CONFIG_MASK 0x00001800 +#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB) +#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define GPIO_PIN4_INT_TYPE_MSB 9 +#define GPIO_PIN4_INT_TYPE_LSB 7 +#define GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB) +#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK) +#define GPIO_PIN4_PAD_DRIVER_MSB 2 +#define GPIO_PIN4_PAD_DRIVER_LSB 2 +#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB) +#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK) +#define GPIO_PIN4_SOURCE_MSB 0 +#define GPIO_PIN4_SOURCE_LSB 0 +#define GPIO_PIN4_SOURCE_MASK 0x00000001 +#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB) +#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK) + +#define GPIO_PIN5_ADDRESS 0x0000003c +#define GPIO_PIN5_OFFSET 0x0000003c +#define GPIO_PIN5_CONFIG_MSB 12 +#define GPIO_PIN5_CONFIG_LSB 11 +#define GPIO_PIN5_CONFIG_MASK 0x00001800 +#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB) +#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define GPIO_PIN5_INT_TYPE_MSB 9 +#define GPIO_PIN5_INT_TYPE_LSB 7 +#define GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB) +#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK) +#define GPIO_PIN5_PAD_DRIVER_MSB 2 +#define GPIO_PIN5_PAD_DRIVER_LSB 2 +#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB) +#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK) +#define GPIO_PIN5_SOURCE_MSB 0 +#define GPIO_PIN5_SOURCE_LSB 0 +#define GPIO_PIN5_SOURCE_MASK 0x00000001 +#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB) +#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK) + +#define GPIO_PIN6_ADDRESS 0x00000040 +#define GPIO_PIN6_OFFSET 0x00000040 +#define GPIO_PIN6_CONFIG_MSB 12 +#define GPIO_PIN6_CONFIG_LSB 11 +#define GPIO_PIN6_CONFIG_MASK 0x00001800 +#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB) +#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define GPIO_PIN6_INT_TYPE_MSB 9 +#define GPIO_PIN6_INT_TYPE_LSB 7 +#define GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB) +#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK) +#define GPIO_PIN6_PAD_DRIVER_MSB 2 +#define GPIO_PIN6_PAD_DRIVER_LSB 2 +#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB) +#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK) +#define GPIO_PIN6_SOURCE_MSB 0 +#define GPIO_PIN6_SOURCE_LSB 0 +#define GPIO_PIN6_SOURCE_MASK 0x00000001 +#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB) +#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK) + +#define GPIO_PIN7_ADDRESS 0x00000044 +#define GPIO_PIN7_OFFSET 0x00000044 +#define GPIO_PIN7_CONFIG_MSB 12 +#define GPIO_PIN7_CONFIG_LSB 11 +#define GPIO_PIN7_CONFIG_MASK 0x00001800 +#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB) +#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define GPIO_PIN7_INT_TYPE_MSB 9 +#define GPIO_PIN7_INT_TYPE_LSB 7 +#define GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB) +#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK) +#define GPIO_PIN7_PAD_DRIVER_MSB 2 +#define GPIO_PIN7_PAD_DRIVER_LSB 2 +#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB) +#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK) +#define GPIO_PIN7_SOURCE_MSB 0 +#define GPIO_PIN7_SOURCE_LSB 0 +#define GPIO_PIN7_SOURCE_MASK 0x00000001 +#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB) +#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK) + +#define GPIO_PIN8_ADDRESS 0x00000048 +#define GPIO_PIN8_OFFSET 0x00000048 +#define GPIO_PIN8_CONFIG_MSB 12 +#define GPIO_PIN8_CONFIG_LSB 11 +#define GPIO_PIN8_CONFIG_MASK 0x00001800 +#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB) +#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define GPIO_PIN8_INT_TYPE_MSB 9 +#define GPIO_PIN8_INT_TYPE_LSB 7 +#define GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB) +#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK) +#define GPIO_PIN8_PAD_DRIVER_MSB 2 +#define GPIO_PIN8_PAD_DRIVER_LSB 2 +#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB) +#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK) +#define GPIO_PIN8_SOURCE_MSB 0 +#define GPIO_PIN8_SOURCE_LSB 0 +#define GPIO_PIN8_SOURCE_MASK 0x00000001 +#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB) +#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK) + +#define GPIO_PIN9_ADDRESS 0x0000004c +#define GPIO_PIN9_OFFSET 0x0000004c +#define GPIO_PIN9_CONFIG_MSB 12 +#define GPIO_PIN9_CONFIG_LSB 11 +#define GPIO_PIN9_CONFIG_MASK 0x00001800 +#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB) +#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define GPIO_PIN9_INT_TYPE_MSB 9 +#define GPIO_PIN9_INT_TYPE_LSB 7 +#define GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB) +#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK) +#define GPIO_PIN9_PAD_DRIVER_MSB 2 +#define GPIO_PIN9_PAD_DRIVER_LSB 2 +#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB) +#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK) +#define GPIO_PIN9_SOURCE_MSB 0 +#define GPIO_PIN9_SOURCE_LSB 0 +#define GPIO_PIN9_SOURCE_MASK 0x00000001 +#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB) +#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK) + +#define GPIO_PIN10_ADDRESS 0x00000050 +#define GPIO_PIN10_OFFSET 0x00000050 +#define GPIO_PIN10_CONFIG_MSB 12 +#define GPIO_PIN10_CONFIG_LSB 11 +#define GPIO_PIN10_CONFIG_MASK 0x00001800 +#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB) +#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define GPIO_PIN10_INT_TYPE_MSB 9 +#define GPIO_PIN10_INT_TYPE_LSB 7 +#define GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB) +#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK) +#define GPIO_PIN10_PAD_DRIVER_MSB 2 +#define GPIO_PIN10_PAD_DRIVER_LSB 2 +#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB) +#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK) +#define GPIO_PIN10_SOURCE_MSB 0 +#define GPIO_PIN10_SOURCE_LSB 0 +#define GPIO_PIN10_SOURCE_MASK 0x00000001 +#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB) +#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK) + +#define GPIO_PIN11_ADDRESS 0x00000054 +#define GPIO_PIN11_OFFSET 0x00000054 +#define GPIO_PIN11_CONFIG_MSB 12 +#define GPIO_PIN11_CONFIG_LSB 11 +#define GPIO_PIN11_CONFIG_MASK 0x00001800 +#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB) +#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define GPIO_PIN11_INT_TYPE_MSB 9 +#define GPIO_PIN11_INT_TYPE_LSB 7 +#define GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB) +#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK) +#define GPIO_PIN11_PAD_DRIVER_MSB 2 +#define GPIO_PIN11_PAD_DRIVER_LSB 2 +#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB) +#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK) +#define GPIO_PIN11_SOURCE_MSB 0 +#define GPIO_PIN11_SOURCE_LSB 0 +#define GPIO_PIN11_SOURCE_MASK 0x00000001 +#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB) +#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK) + +#define GPIO_PIN12_ADDRESS 0x00000058 +#define GPIO_PIN12_OFFSET 0x00000058 +#define GPIO_PIN12_CONFIG_MSB 12 +#define GPIO_PIN12_CONFIG_LSB 11 +#define GPIO_PIN12_CONFIG_MASK 0x00001800 +#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB) +#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define GPIO_PIN12_INT_TYPE_MSB 9 +#define GPIO_PIN12_INT_TYPE_LSB 7 +#define GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB) +#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK) +#define GPIO_PIN12_PAD_DRIVER_MSB 2 +#define GPIO_PIN12_PAD_DRIVER_LSB 2 +#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB) +#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK) +#define GPIO_PIN12_SOURCE_MSB 0 +#define GPIO_PIN12_SOURCE_LSB 0 +#define GPIO_PIN12_SOURCE_MASK 0x00000001 +#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB) +#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK) + +#define GPIO_PIN13_ADDRESS 0x0000005c +#define GPIO_PIN13_OFFSET 0x0000005c +#define GPIO_PIN13_CONFIG_MSB 12 +#define GPIO_PIN13_CONFIG_LSB 11 +#define GPIO_PIN13_CONFIG_MASK 0x00001800 +#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB) +#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define GPIO_PIN13_INT_TYPE_MSB 9 +#define GPIO_PIN13_INT_TYPE_LSB 7 +#define GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB) +#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK) +#define GPIO_PIN13_PAD_DRIVER_MSB 2 +#define GPIO_PIN13_PAD_DRIVER_LSB 2 +#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB) +#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK) +#define GPIO_PIN13_SOURCE_MSB 0 +#define GPIO_PIN13_SOURCE_LSB 0 +#define GPIO_PIN13_SOURCE_MASK 0x00000001 +#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB) +#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK) + +#define GPIO_PIN14_ADDRESS 0x00000060 +#define GPIO_PIN14_OFFSET 0x00000060 +#define GPIO_PIN14_CONFIG_MSB 12 +#define GPIO_PIN14_CONFIG_LSB 11 +#define GPIO_PIN14_CONFIG_MASK 0x00001800 +#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB) +#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define GPIO_PIN14_INT_TYPE_MSB 9 +#define GPIO_PIN14_INT_TYPE_LSB 7 +#define GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB) +#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK) +#define GPIO_PIN14_PAD_DRIVER_MSB 2 +#define GPIO_PIN14_PAD_DRIVER_LSB 2 +#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB) +#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK) +#define GPIO_PIN14_SOURCE_MSB 0 +#define GPIO_PIN14_SOURCE_LSB 0 +#define GPIO_PIN14_SOURCE_MASK 0x00000001 +#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB) +#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK) + +#define GPIO_PIN15_ADDRESS 0x00000064 +#define GPIO_PIN15_OFFSET 0x00000064 +#define GPIO_PIN15_CONFIG_MSB 12 +#define GPIO_PIN15_CONFIG_LSB 11 +#define GPIO_PIN15_CONFIG_MASK 0x00001800 +#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB) +#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define GPIO_PIN15_INT_TYPE_MSB 9 +#define GPIO_PIN15_INT_TYPE_LSB 7 +#define GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB) +#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK) +#define GPIO_PIN15_PAD_DRIVER_MSB 2 +#define GPIO_PIN15_PAD_DRIVER_LSB 2 +#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB) +#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK) +#define GPIO_PIN15_SOURCE_MSB 0 +#define GPIO_PIN15_SOURCE_LSB 0 +#define GPIO_PIN15_SOURCE_MASK 0x00000001 +#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB) +#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK) + +#define GPIO_PIN16_ADDRESS 0x00000068 +#define GPIO_PIN16_OFFSET 0x00000068 +#define GPIO_PIN16_CONFIG_MSB 12 +#define GPIO_PIN16_CONFIG_LSB 11 +#define GPIO_PIN16_CONFIG_MASK 0x00001800 +#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB) +#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define GPIO_PIN16_INT_TYPE_MSB 9 +#define GPIO_PIN16_INT_TYPE_LSB 7 +#define GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB) +#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK) +#define GPIO_PIN16_PAD_DRIVER_MSB 2 +#define GPIO_PIN16_PAD_DRIVER_LSB 2 +#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB) +#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK) +#define GPIO_PIN16_SOURCE_MSB 0 +#define GPIO_PIN16_SOURCE_LSB 0 +#define GPIO_PIN16_SOURCE_MASK 0x00000001 +#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB) +#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK) + +#define GPIO_PIN17_ADDRESS 0x0000006c +#define GPIO_PIN17_OFFSET 0x0000006c +#define GPIO_PIN17_CONFIG_MSB 12 +#define GPIO_PIN17_CONFIG_LSB 11 +#define GPIO_PIN17_CONFIG_MASK 0x00001800 +#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB) +#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define GPIO_PIN17_INT_TYPE_MSB 9 +#define GPIO_PIN17_INT_TYPE_LSB 7 +#define GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB) +#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK) +#define GPIO_PIN17_PAD_DRIVER_MSB 2 +#define GPIO_PIN17_PAD_DRIVER_LSB 2 +#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB) +#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK) +#define GPIO_PIN17_SOURCE_MSB 0 +#define GPIO_PIN17_SOURCE_LSB 0 +#define GPIO_PIN17_SOURCE_MASK 0x00000001 +#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB) +#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK) + +#define SDIO_PIN_ADDRESS 0x00000070 +#define SDIO_PIN_OFFSET 0x00000070 +#define SDIO_PIN_PAD_PULL_MSB 3 +#define SDIO_PIN_PAD_PULL_LSB 2 +#define SDIO_PIN_PAD_PULL_MASK 0x0000000c +#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB) +#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK) +#define SDIO_PIN_PAD_STRENGTH_MSB 1 +#define SDIO_PIN_PAD_STRENGTH_LSB 0 +#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB) +#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK) + +#define CLK_REQ_PIN_ADDRESS 0x00000074 +#define CLK_REQ_PIN_OFFSET 0x00000074 +#define CLK_REQ_PIN_ATE_OE_L_MSB 4 +#define CLK_REQ_PIN_ATE_OE_L_LSB 4 +#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010 +#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB) +#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK) +#define CLK_REQ_PIN_PAD_PULL_MSB 3 +#define CLK_REQ_PIN_PAD_PULL_LSB 2 +#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c +#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB) +#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK) +#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1 +#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0 +#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003 +#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB) +#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK) + +#define SIGMA_DELTA_ADDRESS 0x00000078 +#define SIGMA_DELTA_OFFSET 0x00000078 +#define SIGMA_DELTA_ENABLE_MSB 16 +#define SIGMA_DELTA_ENABLE_LSB 16 +#define SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB) +#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK) +#define SIGMA_DELTA_PRESCALAR_MSB 15 +#define SIGMA_DELTA_PRESCALAR_LSB 8 +#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB) +#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK) +#define SIGMA_DELTA_TARGET_MSB 7 +#define SIGMA_DELTA_TARGET_LSB 0 +#define SIGMA_DELTA_TARGET_MASK 0x000000ff +#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB) +#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK) + +#define DEBUG_CONTROL_ADDRESS 0x0000007c +#define DEBUG_CONTROL_OFFSET 0x0000007c +#define DEBUG_CONTROL_OBS_OE_L_MSB 1 +#define DEBUG_CONTROL_OBS_OE_L_LSB 1 +#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002 +#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB) +#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK) +#define DEBUG_CONTROL_ENABLE_MSB 0 +#define DEBUG_CONTROL_ENABLE_LSB 0 +#define DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB) +#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK) + +#define DEBUG_INPUT_SEL_ADDRESS 0x00000080 +#define DEBUG_INPUT_SEL_OFFSET 0x00000080 +#define DEBUG_INPUT_SEL_SRC_MSB 3 +#define DEBUG_INPUT_SEL_SRC_LSB 0 +#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB) +#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK) + +#define DEBUG_OUT_ADDRESS 0x00000084 +#define DEBUG_OUT_OFFSET 0x00000084 +#define DEBUG_OUT_DATA_MSB 17 +#define DEBUG_OUT_DATA_LSB 0 +#define DEBUG_OUT_DATA_MASK 0x0003ffff +#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB) +#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK) + +#define LA_CONTROL_ADDRESS 0x00000088 +#define LA_CONTROL_OFFSET 0x00000088 +#define LA_CONTROL_RUN_MSB 1 +#define LA_CONTROL_RUN_LSB 1 +#define LA_CONTROL_RUN_MASK 0x00000002 +#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB) +#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK) +#define LA_CONTROL_TRIGGERED_MSB 0 +#define LA_CONTROL_TRIGGERED_LSB 0 +#define LA_CONTROL_TRIGGERED_MASK 0x00000001 +#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB) +#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK) + +#define LA_CLOCK_ADDRESS 0x0000008c +#define LA_CLOCK_OFFSET 0x0000008c +#define LA_CLOCK_DIV_MSB 7 +#define LA_CLOCK_DIV_LSB 0 +#define LA_CLOCK_DIV_MASK 0x000000ff +#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB) +#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK) + +#define LA_STATUS_ADDRESS 0x00000090 +#define LA_STATUS_OFFSET 0x00000090 +#define LA_STATUS_INTERRUPT_MSB 0 +#define LA_STATUS_INTERRUPT_LSB 0 +#define LA_STATUS_INTERRUPT_MASK 0x00000001 +#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB) +#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK) + +#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094 +#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094 +#define LA_TRIGGER_SAMPLE_COUNT_MSB 15 +#define LA_TRIGGER_SAMPLE_COUNT_LSB 0 +#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff +#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB) +#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK) + +#define LA_TRIGGER_POSITION_ADDRESS 0x00000098 +#define LA_TRIGGER_POSITION_OFFSET 0x00000098 +#define LA_TRIGGER_POSITION_VALUE_MSB 15 +#define LA_TRIGGER_POSITION_VALUE_LSB 0 +#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff +#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB) +#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK) + +#define LA_PRE_TRIGGER_ADDRESS 0x0000009c +#define LA_PRE_TRIGGER_OFFSET 0x0000009c +#define LA_PRE_TRIGGER_COUNT_MSB 15 +#define LA_PRE_TRIGGER_COUNT_LSB 0 +#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB) +#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK) + +#define LA_POST_TRIGGER_ADDRESS 0x000000a0 +#define LA_POST_TRIGGER_OFFSET 0x000000a0 +#define LA_POST_TRIGGER_COUNT_MSB 15 +#define LA_POST_TRIGGER_COUNT_LSB 0 +#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB) +#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK) + +#define LA_FILTER_CONTROL_ADDRESS 0x000000a4 +#define LA_FILTER_CONTROL_OFFSET 0x000000a4 +#define LA_FILTER_CONTROL_DELTA_MSB 0 +#define LA_FILTER_CONTROL_DELTA_LSB 0 +#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001 +#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB) +#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK) + +#define LA_FILTER_DATA_ADDRESS 0x000000a8 +#define LA_FILTER_DATA_OFFSET 0x000000a8 +#define LA_FILTER_DATA_MATCH_MSB 17 +#define LA_FILTER_DATA_MATCH_LSB 0 +#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff +#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB) +#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK) + +#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac +#define LA_FILTER_WILDCARD_OFFSET 0x000000ac +#define LA_FILTER_WILDCARD_MATCH_MSB 17 +#define LA_FILTER_WILDCARD_MATCH_LSB 0 +#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB) +#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0 +#define LA_TRIGGERA_DATA_OFFSET 0x000000b0 +#define LA_TRIGGERA_DATA_MATCH_MSB 17 +#define LA_TRIGGERA_DATA_MATCH_LSB 0 +#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB) +#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK) + +#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4 +#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4 +#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB) +#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8 +#define LA_TRIGGERB_DATA_OFFSET 0x000000b8 +#define LA_TRIGGERB_DATA_MATCH_MSB 17 +#define LA_TRIGGERB_DATA_MATCH_LSB 0 +#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB) +#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK) + +#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc +#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc +#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB) +#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK) + +#define LA_TRIGGER_ADDRESS 0x000000c0 +#define LA_TRIGGER_OFFSET 0x000000c0 +#define LA_TRIGGER_EVENT_MSB 2 +#define LA_TRIGGER_EVENT_LSB 0 +#define LA_TRIGGER_EVENT_MASK 0x00000007 +#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB) +#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK) + +#define LA_FIFO_ADDRESS 0x000000c4 +#define LA_FIFO_OFFSET 0x000000c4 +#define LA_FIFO_FULL_MSB 1 +#define LA_FIFO_FULL_LSB 1 +#define LA_FIFO_FULL_MASK 0x00000002 +#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB) +#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK) +#define LA_FIFO_EMPTY_MSB 0 +#define LA_FIFO_EMPTY_LSB 0 +#define LA_FIFO_EMPTY_MASK 0x00000001 +#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB) +#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK) + +#define LA_ADDRESS 0x000000c8 +#define LA_OFFSET 0x000000c8 +#define LA_DATA_MSB 17 +#define LA_DATA_LSB 0 +#define LA_DATA_MASK 0x0003ffff +#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB) +#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK) + +#define ANT_PIN_ADDRESS 0x000000d0 +#define ANT_PIN_OFFSET 0x000000d0 +#define ANT_PIN_PAD_PULL_MSB 3 +#define ANT_PIN_PAD_PULL_LSB 2 +#define ANT_PIN_PAD_PULL_MASK 0x0000000c +#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB) +#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK) +#define ANT_PIN_PAD_STRENGTH_MSB 1 +#define ANT_PIN_PAD_STRENGTH_LSB 0 +#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB) +#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK) + +#define ANTD_PIN_ADDRESS 0x000000d4 +#define ANTD_PIN_OFFSET 0x000000d4 +#define ANTD_PIN_PAD_PULL_MSB 1 +#define ANTD_PIN_PAD_PULL_LSB 0 +#define ANTD_PIN_PAD_PULL_MASK 0x00000003 +#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB) +#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK) + +#define GPIO_PIN_ADDRESS 0x000000d8 +#define GPIO_PIN_OFFSET 0x000000d8 +#define GPIO_PIN_PAD_PULL_MSB 3 +#define GPIO_PIN_PAD_PULL_LSB 2 +#define GPIO_PIN_PAD_PULL_MASK 0x0000000c +#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB) +#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK) +#define GPIO_PIN_PAD_STRENGTH_MSB 1 +#define GPIO_PIN_PAD_STRENGTH_LSB 0 +#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB) +#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK) + +#define GPIO_H_PIN_ADDRESS 0x000000dc +#define GPIO_H_PIN_OFFSET 0x000000dc +#define GPIO_H_PIN_PAD_PULL_MSB 1 +#define GPIO_H_PIN_PAD_PULL_LSB 0 +#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003 +#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB) +#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK) + +#define BT_PIN_ADDRESS 0x000000e0 +#define BT_PIN_OFFSET 0x000000e0 +#define BT_PIN_PAD_PULL_MSB 3 +#define BT_PIN_PAD_PULL_LSB 2 +#define BT_PIN_PAD_PULL_MASK 0x0000000c +#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB) +#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK) +#define BT_PIN_PAD_STRENGTH_MSB 1 +#define BT_PIN_PAD_STRENGTH_LSB 0 +#define BT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB) +#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK) + +#define BT_WLAN_PIN_ADDRESS 0x000000e4 +#define BT_WLAN_PIN_OFFSET 0x000000e4 +#define BT_WLAN_PIN_PAD_PULL_MSB 1 +#define BT_WLAN_PIN_PAD_PULL_LSB 0 +#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003 +#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB) +#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK) + +#define SI_UART_PIN_ADDRESS 0x000000e8 +#define SI_UART_PIN_OFFSET 0x000000e8 +#define SI_UART_PIN_PAD_PULL_MSB 3 +#define SI_UART_PIN_PAD_PULL_LSB 2 +#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c +#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB) +#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK) +#define SI_UART_PIN_PAD_STRENGTH_MSB 1 +#define SI_UART_PIN_PAD_STRENGTH_LSB 0 +#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB) +#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK) + +#define CLK32K_PIN_ADDRESS 0x000000ec +#define CLK32K_PIN_OFFSET 0x000000ec +#define CLK32K_PIN_PAD_PULL_MSB 1 +#define CLK32K_PIN_PAD_PULL_LSB 0 +#define CLK32K_PIN_PAD_PULL_MASK 0x00000003 +#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB) +#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK) + +#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0 +#define RESET_TUPLE_STATUS_OFFSET 0x000000f0 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_reg_reg_s { + volatile unsigned int gpio_out; + volatile unsigned int gpio_out_w1ts; + volatile unsigned int gpio_out_w1tc; + volatile unsigned int gpio_enable; + volatile unsigned int gpio_enable_w1ts; + volatile unsigned int gpio_enable_w1tc; + volatile unsigned int gpio_in; + volatile unsigned int gpio_status; + volatile unsigned int gpio_status_w1ts; + volatile unsigned int gpio_status_w1tc; + volatile unsigned int gpio_pin0; + volatile unsigned int gpio_pin1; + volatile unsigned int gpio_pin2; + volatile unsigned int gpio_pin3; + volatile unsigned int gpio_pin4; + volatile unsigned int gpio_pin5; + volatile unsigned int gpio_pin6; + volatile unsigned int gpio_pin7; + volatile unsigned int gpio_pin8; + volatile unsigned int gpio_pin9; + volatile unsigned int gpio_pin10; + volatile unsigned int gpio_pin11; + volatile unsigned int gpio_pin12; + volatile unsigned int gpio_pin13; + volatile unsigned int gpio_pin14; + volatile unsigned int gpio_pin15; + volatile unsigned int gpio_pin16; + volatile unsigned int gpio_pin17; + volatile unsigned int sdio_pin; + volatile unsigned int clk_req_pin; + volatile unsigned int sigma_delta; + volatile unsigned int debug_control; + volatile unsigned int debug_input_sel; + volatile unsigned int debug_out; + volatile unsigned int la_control; + volatile unsigned int la_clock; + volatile unsigned int la_status; + volatile unsigned int la_trigger_sample; + volatile unsigned int la_trigger_position; + volatile unsigned int la_pre_trigger; + volatile unsigned int la_post_trigger; + volatile unsigned int la_filter_control; + volatile unsigned int la_filter_data; + volatile unsigned int la_filter_wildcard; + volatile unsigned int la_triggera_data; + volatile unsigned int la_triggera_wildcard; + volatile unsigned int la_triggerb_data; + volatile unsigned int la_triggerb_wildcard; + volatile unsigned int la_trigger; + volatile unsigned int la_fifo; + volatile unsigned int la[2]; + volatile unsigned int ant_pin; + volatile unsigned int antd_pin; + volatile unsigned int gpio_pin; + volatile unsigned int gpio_h_pin; + volatile unsigned int bt_pin; + volatile unsigned int bt_wlan_pin; + volatile unsigned int si_uart_pin; + volatile unsigned int clk32k_pin; + volatile unsigned int reset_tuple_status; +} gpio_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h new file mode 100644 index 000000000000..20ac2b5c8920 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_host_reg.h @@ -0,0 +1,405 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_HOST_REG_REG_H_ +#define _MBOX_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_DRAGON_INT_MSB 5 +#define HOST_INT_STATUS_DRAGON_INT_LSB 5 +#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020 +#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB) +#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB) +#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define SPI_CONFIG_ADDRESS 0x00000480 +#define SPI_CONFIG_OFFSET 0x00000480 +#define SPI_CONFIG_SPI_RESET_MSB 4 +#define SPI_CONFIG_SPI_RESET_LSB 4 +#define SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB) +#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK) +#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define SPI_CONFIG_TEST_MODE_MSB 2 +#define SPI_CONFIG_TEST_MODE_LSB 2 +#define SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB) +#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK) +#define SPI_CONFIG_DATA_SIZE_MSB 1 +#define SPI_CONFIG_DATA_SIZE_LSB 0 +#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB) +#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK) + +#define SPI_STATUS_ADDRESS 0x00000481 +#define SPI_STATUS_OFFSET 0x00000481 +#define SPI_STATUS_ADDR_ERR_MSB 3 +#define SPI_STATUS_ADDR_ERR_LSB 3 +#define SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB) +#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK) +#define SPI_STATUS_RD_ERR_MSB 2 +#define SPI_STATUS_RD_ERR_LSB 2 +#define SPI_STATUS_RD_ERR_MASK 0x00000004 +#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB) +#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK) +#define SPI_STATUS_WR_ERR_MSB 1 +#define SPI_STATUS_WR_ERR_LSB 1 +#define SPI_STATUS_WR_ERR_MASK 0x00000002 +#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB) +#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK) +#define SPI_STATUS_READY_MSB 0 +#define SPI_STATUS_READY_LSB 0 +#define SPI_STATUS_READY_MASK 0x00000001 +#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB) +#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + unsigned char pad1[2]; /* pad to 0x408 */ + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad2[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad3[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad4[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad5[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad6[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char spi_config; + volatile unsigned char spi_status; + volatile unsigned char non_assoc_sleep_en; + unsigned char pad7[381]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_HOST_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h new file mode 100644 index 000000000000..d232764d5af6 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/mbox_reg.h @@ -0,0 +1,500 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_REG_REG_H_ +#define _MBOX_REG_REG_H_ + +#define MBOX_FIFO_ADDRESS 0x00000000 +#define MBOX_FIFO_OFFSET 0x00000000 +#define MBOX_FIFO_DATA_MSB 19 +#define MBOX_FIFO_DATA_LSB 0 +#define MBOX_FIFO_DATA_MASK 0x000fffff +#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB) +#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK) + +#define MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK) +#define MBOX_FIFO_STATUS_FULL_MSB 15 +#define MBOX_FIFO_STATUS_FULL_LSB 12 +#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB) +#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK) + +#define MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define MBOX_DMA_POLICY_OFFSET 0x00000014 +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX_INT_STATUS_ADDRESS 0x00000058 +#define MBOX_INT_STATUS_OFFSET 0x00000058 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define MBOX_INT_STATUS_HOST_MSB 7 +#define MBOX_INT_STATUS_HOST_LSB 0 +#define MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB) +#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK) + +#define MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define MBOX_INT_ENABLE_OFFSET 0x0000005c +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define MBOX_INT_ENABLE_HOST_MSB 7 +#define MBOX_INT_ENABLE_HOST_LSB 0 +#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB) +#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK) + +#define INT_HOST_ADDRESS 0x00000060 +#define INT_HOST_OFFSET 0x00000060 +#define INT_HOST_VECTOR_MSB 7 +#define INT_HOST_VECTOR_LSB 0 +#define INT_HOST_VECTOR_MASK 0x000000ff +#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB) +#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK) + +#define LOCAL_COUNT_ADDRESS 0x00000080 +#define LOCAL_COUNT_OFFSET 0x00000080 +#define LOCAL_COUNT_VALUE_MSB 7 +#define LOCAL_COUNT_VALUE_LSB 0 +#define LOCAL_COUNT_VALUE_MASK 0x000000ff +#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB) +#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK) + +#define COUNT_INC_ADDRESS 0x000000a0 +#define COUNT_INC_OFFSET 0x000000a0 +#define COUNT_INC_VALUE_MSB 7 +#define COUNT_INC_VALUE_LSB 0 +#define COUNT_INC_VALUE_MASK 0x000000ff +#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB) +#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK) + +#define LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define LOCAL_SCRATCH_OFFSET 0x000000c0 +#define LOCAL_SCRATCH_VALUE_MSB 7 +#define LOCAL_SCRATCH_VALUE_LSB 0 +#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB) +#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK) + +#define USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define USE_LOCAL_BUS_OFFSET 0x000000e0 +#define USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK) + +#define SDIO_CONFIG_ADDRESS 0x000000e4 +#define SDIO_CONFIG_OFFSET 0x000000e4 +#define SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK) + +#define MBOX_DEBUG_ADDRESS 0x000000e8 +#define MBOX_DEBUG_OFFSET 0x000000e8 +#define MBOX_DEBUG_SEL_MSB 2 +#define MBOX_DEBUG_SEL_LSB 0 +#define MBOX_DEBUG_SEL_MASK 0x00000007 +#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB) +#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK) + +#define MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define MBOX_FIFO_RESET_OFFSET 0x000000ec +#define MBOX_FIFO_RESET_INIT_MSB 0 +#define MBOX_FIFO_RESET_INIT_LSB 0 +#define MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB) +#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK) + +#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define MBOX_TXFIFO_POP_DATA_MSB 0 +#define MBOX_TXFIFO_POP_DATA_LSB 0 +#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB) +#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK) + +#define MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define MBOX_RXFIFO_POP_DATA_MSB 0 +#define MBOX_RXFIFO_POP_DATA_LSB 0 +#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB) +#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK) + +#define SDIO_DEBUG_ADDRESS 0x00000110 +#define SDIO_DEBUG_OFFSET 0x00000110 +#define SDIO_DEBUG_SEL_MSB 3 +#define SDIO_DEBUG_SEL_LSB 0 +#define SDIO_DEBUG_SEL_MASK 0x0000000f +#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB) +#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK) + +#define HOST_IF_WINDOW_ADDRESS 0x00002000 +#define HOST_IF_WINDOW_OFFSET 0x00002000 +#define HOST_IF_WINDOW_DATA_MSB 7 +#define HOST_IF_WINDOW_DATA_LSB 0 +#define HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB) +#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_reg_reg_s { + volatile unsigned int mbox_fifo[4]; + volatile unsigned int mbox_fifo_status; + volatile unsigned int mbox_dma_policy; + volatile unsigned int mbox0_dma_rx_descriptor_base; + volatile unsigned int mbox0_dma_rx_control; + volatile unsigned int mbox0_dma_tx_descriptor_base; + volatile unsigned int mbox0_dma_tx_control; + volatile unsigned int mbox1_dma_rx_descriptor_base; + volatile unsigned int mbox1_dma_rx_control; + volatile unsigned int mbox1_dma_tx_descriptor_base; + volatile unsigned int mbox1_dma_tx_control; + volatile unsigned int mbox2_dma_rx_descriptor_base; + volatile unsigned int mbox2_dma_rx_control; + volatile unsigned int mbox2_dma_tx_descriptor_base; + volatile unsigned int mbox2_dma_tx_control; + volatile unsigned int mbox3_dma_rx_descriptor_base; + volatile unsigned int mbox3_dma_rx_control; + volatile unsigned int mbox3_dma_tx_descriptor_base; + volatile unsigned int mbox3_dma_tx_control; + volatile unsigned int mbox_int_status; + volatile unsigned int mbox_int_enable; + volatile unsigned int int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int local_count[8]; + volatile unsigned int count_inc[8]; + volatile unsigned int local_scratch[8]; + volatile unsigned int use_local_bus; + volatile unsigned int sdio_config; + volatile unsigned int mbox_debug; + volatile unsigned int mbox_fifo_reset; + volatile unsigned int mbox_txfifo_pop[4]; + volatile unsigned int mbox_rxfifo_pop[4]; + volatile unsigned int sdio_debug; + unsigned char pad1[7916]; /* pad to 0x2000 */ + volatile unsigned int host_if_window[2048]; +} mbox_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h new file mode 100644 index 000000000000..cc2cb7350a78 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/rtc_reg.h @@ -0,0 +1,1182 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RTC_REG_REG_H_ +#define _RTC_REG_REG_H_ + +#define RESET_CONTROL_ADDRESS 0x00000000 +#define RESET_CONTROL_OFFSET 0x00000000 +#define RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define RESET_CONTROL_RST_OUT_MSB 9 +#define RESET_CONTROL_RST_OUT_LSB 9 +#define RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB) +#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK) +#define RESET_CONTROL_COLD_RST_MSB 8 +#define RESET_CONTROL_COLD_RST_LSB 8 +#define RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) +#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) +#define RESET_CONTROL_WARM_RST_MSB 7 +#define RESET_CONTROL_WARM_RST_LSB 7 +#define RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) +#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) +#define RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) +#define RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) +#define RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) +#define RESET_CONTROL_MBOX_RST_MSB 2 +#define RESET_CONTROL_MBOX_RST_LSB 2 +#define RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB) +#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK) +#define RESET_CONTROL_UART_RST_MSB 1 +#define RESET_CONTROL_UART_RST_LSB 1 +#define RESET_CONTROL_UART_RST_MASK 0x00000002 +#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB) +#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK) +#define RESET_CONTROL_SI0_RST_MSB 0 +#define RESET_CONTROL_SI0_RST_LSB 0 +#define RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB) +#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK) + +#define XTAL_CONTROL_ADDRESS 0x00000004 +#define XTAL_CONTROL_OFFSET 0x00000004 +#define XTAL_CONTROL_TCXO_MSB 0 +#define XTAL_CONTROL_TCXO_LSB 0 +#define XTAL_CONTROL_TCXO_MASK 0x00000001 +#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB) +#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK) + +#define TCXO_DETECT_ADDRESS 0x00000008 +#define TCXO_DETECT_OFFSET 0x00000008 +#define TCXO_DETECT_PRESENT_MSB 0 +#define TCXO_DETECT_PRESENT_LSB 0 +#define TCXO_DETECT_PRESENT_MASK 0x00000001 +#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB) +#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK) + +#define XTAL_TEST_ADDRESS 0x0000000c +#define XTAL_TEST_OFFSET 0x0000000c +#define XTAL_TEST_NOTCXODET_MSB 0 +#define XTAL_TEST_NOTCXODET_LSB 0 +#define XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB) +#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK) + +#define QUADRATURE_ADDRESS 0x00000010 +#define QUADRATURE_OFFSET 0x00000010 +#define QUADRATURE_ADC_MSB 5 +#define QUADRATURE_ADC_LSB 4 +#define QUADRATURE_ADC_MASK 0x00000030 +#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB) +#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK) +#define QUADRATURE_SEL_MSB 2 +#define QUADRATURE_SEL_LSB 2 +#define QUADRATURE_SEL_MASK 0x00000004 +#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB) +#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK) +#define QUADRATURE_DAC_MSB 1 +#define QUADRATURE_DAC_LSB 0 +#define QUADRATURE_DAC_MASK 0x00000003 +#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB) +#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK) + +#define PLL_CONTROL_ADDRESS 0x00000014 +#define PLL_CONTROL_OFFSET 0x00000014 +#define PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) +#define PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) +#define PLL_CONTROL_NOPWD_MSB 18 +#define PLL_CONTROL_NOPWD_LSB 18 +#define PLL_CONTROL_NOPWD_MASK 0x00040000 +#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB) +#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK) +#define PLL_CONTROL_UPDATING_MSB 17 +#define PLL_CONTROL_UPDATING_LSB 17 +#define PLL_CONTROL_UPDATING_MASK 0x00020000 +#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB) +#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK) +#define PLL_CONTROL_BYPASS_MSB 16 +#define PLL_CONTROL_BYPASS_LSB 16 +#define PLL_CONTROL_BYPASS_MASK 0x00010000 +#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB) +#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK) +#define PLL_CONTROL_REFDIV_MSB 15 +#define PLL_CONTROL_REFDIV_LSB 12 +#define PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB) +#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK) +#define PLL_CONTROL_DIV_MSB 9 +#define PLL_CONTROL_DIV_LSB 0 +#define PLL_CONTROL_DIV_MASK 0x000003ff +#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB) +#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK) + +#define PLL_SETTLE_ADDRESS 0x00000018 +#define PLL_SETTLE_OFFSET 0x00000018 +#define PLL_SETTLE_TIME_MSB 11 +#define PLL_SETTLE_TIME_LSB 0 +#define PLL_SETTLE_TIME_MASK 0x00000fff +#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB) +#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK) + +#define XTAL_SETTLE_ADDRESS 0x0000001c +#define XTAL_SETTLE_OFFSET 0x0000001c +#define XTAL_SETTLE_TIME_MSB 7 +#define XTAL_SETTLE_TIME_LSB 0 +#define XTAL_SETTLE_TIME_MASK 0x000000ff +#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB) +#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK) + +#define CPU_CLOCK_ADDRESS 0x00000020 +#define CPU_CLOCK_OFFSET 0x00000020 +#define CPU_CLOCK_STANDARD_MSB 1 +#define CPU_CLOCK_STANDARD_LSB 0 +#define CPU_CLOCK_STANDARD_MASK 0x00000003 +#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB) +#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) + +#define CLOCK_OUT_ADDRESS 0x00000024 +#define CLOCK_OUT_OFFSET 0x00000024 +#define CLOCK_OUT_SELECT_MSB 3 +#define CLOCK_OUT_SELECT_LSB 0 +#define CLOCK_OUT_SELECT_MASK 0x0000000f +#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB) +#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK) + +#define CLOCK_CONTROL_ADDRESS 0x00000028 +#define CLOCK_CONTROL_OFFSET 0x00000028 +#define CLOCK_CONTROL_LF_CLK32_MSB 2 +#define CLOCK_CONTROL_LF_CLK32_LSB 2 +#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) +#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) +#define CLOCK_CONTROL_UART_CLK_MSB 1 +#define CLOCK_CONTROL_UART_CLK_LSB 1 +#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 +#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB) +#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK) +#define CLOCK_CONTROL_SI0_CLK_MSB 0 +#define CLOCK_CONTROL_SI0_CLK_LSB 0 +#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB) +#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK) + +#define BIAS_OVERRIDE_ADDRESS 0x0000002c +#define BIAS_OVERRIDE_OFFSET 0x0000002c +#define BIAS_OVERRIDE_ON_MSB 0 +#define BIAS_OVERRIDE_ON_LSB 0 +#define BIAS_OVERRIDE_ON_MASK 0x00000001 +#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB) +#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK) + +#define WDT_CONTROL_ADDRESS 0x00000030 +#define WDT_CONTROL_OFFSET 0x00000030 +#define WDT_CONTROL_ACTION_MSB 2 +#define WDT_CONTROL_ACTION_LSB 0 +#define WDT_CONTROL_ACTION_MASK 0x00000007 +#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB) +#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK) + +#define WDT_STATUS_ADDRESS 0x00000034 +#define WDT_STATUS_OFFSET 0x00000034 +#define WDT_STATUS_INTERRUPT_MSB 0 +#define WDT_STATUS_INTERRUPT_LSB 0 +#define WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB) +#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK) + +#define WDT_ADDRESS 0x00000038 +#define WDT_OFFSET 0x00000038 +#define WDT_TARGET_MSB 21 +#define WDT_TARGET_LSB 0 +#define WDT_TARGET_MASK 0x003fffff +#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB) +#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK) + +#define WDT_COUNT_ADDRESS 0x0000003c +#define WDT_COUNT_OFFSET 0x0000003c +#define WDT_COUNT_VALUE_MSB 21 +#define WDT_COUNT_VALUE_LSB 0 +#define WDT_COUNT_VALUE_MASK 0x003fffff +#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB) +#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK) + +#define WDT_RESET_ADDRESS 0x00000040 +#define WDT_RESET_OFFSET 0x00000040 +#define WDT_RESET_VALUE_MSB 0 +#define WDT_RESET_VALUE_LSB 0 +#define WDT_RESET_VALUE_MASK 0x00000001 +#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB) +#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK) + +#define INT_STATUS_ADDRESS 0x00000044 +#define INT_STATUS_OFFSET 0x00000044 +#define INT_STATUS_RTC_POWER_MSB 14 +#define INT_STATUS_RTC_POWER_LSB 14 +#define INT_STATUS_RTC_POWER_MASK 0x00004000 +#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB) +#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK) +#define INT_STATUS_MAC_MSB 13 +#define INT_STATUS_MAC_LSB 13 +#define INT_STATUS_MAC_MASK 0x00002000 +#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB) +#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK) +#define INT_STATUS_MAILBOX_MSB 12 +#define INT_STATUS_MAILBOX_LSB 12 +#define INT_STATUS_MAILBOX_MASK 0x00001000 +#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB) +#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK) +#define INT_STATUS_RTC_ALARM_MSB 11 +#define INT_STATUS_RTC_ALARM_LSB 11 +#define INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB) +#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK) +#define INT_STATUS_HF_TIMER_MSB 10 +#define INT_STATUS_HF_TIMER_LSB 10 +#define INT_STATUS_HF_TIMER_MASK 0x00000400 +#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB) +#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK) +#define INT_STATUS_LF_TIMER3_MSB 9 +#define INT_STATUS_LF_TIMER3_LSB 9 +#define INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB) +#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK) +#define INT_STATUS_LF_TIMER2_MSB 8 +#define INT_STATUS_LF_TIMER2_LSB 8 +#define INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB) +#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK) +#define INT_STATUS_LF_TIMER1_MSB 7 +#define INT_STATUS_LF_TIMER1_LSB 7 +#define INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB) +#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK) +#define INT_STATUS_LF_TIMER0_MSB 6 +#define INT_STATUS_LF_TIMER0_LSB 6 +#define INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB) +#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK) +#define INT_STATUS_KEYPAD_MSB 5 +#define INT_STATUS_KEYPAD_LSB 5 +#define INT_STATUS_KEYPAD_MASK 0x00000020 +#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB) +#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK) +#define INT_STATUS_SI_MSB 4 +#define INT_STATUS_SI_LSB 4 +#define INT_STATUS_SI_MASK 0x00000010 +#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB) +#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK) +#define INT_STATUS_GPIO_MSB 3 +#define INT_STATUS_GPIO_LSB 3 +#define INT_STATUS_GPIO_MASK 0x00000008 +#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB) +#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK) +#define INT_STATUS_UART_MSB 2 +#define INT_STATUS_UART_LSB 2 +#define INT_STATUS_UART_MASK 0x00000004 +#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB) +#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK) +#define INT_STATUS_ERROR_MSB 1 +#define INT_STATUS_ERROR_LSB 1 +#define INT_STATUS_ERROR_MASK 0x00000002 +#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB) +#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK) +#define INT_STATUS_WDT_INT_MSB 0 +#define INT_STATUS_WDT_INT_LSB 0 +#define INT_STATUS_WDT_INT_MASK 0x00000001 +#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB) +#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK) + +#define LF_TIMER0_ADDRESS 0x00000048 +#define LF_TIMER0_OFFSET 0x00000048 +#define LF_TIMER0_TARGET_MSB 31 +#define LF_TIMER0_TARGET_LSB 0 +#define LF_TIMER0_TARGET_MASK 0xffffffff +#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB) +#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK) + +#define LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define LF_TIMER_COUNT0_OFFSET 0x0000004c +#define LF_TIMER_COUNT0_VALUE_MSB 31 +#define LF_TIMER_COUNT0_VALUE_LSB 0 +#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB) +#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK) + +#define LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL0_RESET_MSB 0 +#define LF_TIMER_CONTROL0_RESET_LSB 0 +#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) +#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK) + +#define LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define LF_TIMER_STATUS0_OFFSET 0x00000054 +#define LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define LF_TIMER1_ADDRESS 0x00000058 +#define LF_TIMER1_OFFSET 0x00000058 +#define LF_TIMER1_TARGET_MSB 31 +#define LF_TIMER1_TARGET_LSB 0 +#define LF_TIMER1_TARGET_MASK 0xffffffff +#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB) +#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK) + +#define LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define LF_TIMER_COUNT1_OFFSET 0x0000005c +#define LF_TIMER_COUNT1_VALUE_MSB 31 +#define LF_TIMER_COUNT1_VALUE_LSB 0 +#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB) +#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK) + +#define LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL1_RESET_MSB 0 +#define LF_TIMER_CONTROL1_RESET_LSB 0 +#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) +#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK) + +#define LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define LF_TIMER_STATUS1_OFFSET 0x00000064 +#define LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define LF_TIMER2_ADDRESS 0x00000068 +#define LF_TIMER2_OFFSET 0x00000068 +#define LF_TIMER2_TARGET_MSB 31 +#define LF_TIMER2_TARGET_LSB 0 +#define LF_TIMER2_TARGET_MASK 0xffffffff +#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB) +#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK) + +#define LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define LF_TIMER_COUNT2_OFFSET 0x0000006c +#define LF_TIMER_COUNT2_VALUE_MSB 31 +#define LF_TIMER_COUNT2_VALUE_LSB 0 +#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB) +#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK) + +#define LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL2_RESET_MSB 0 +#define LF_TIMER_CONTROL2_RESET_LSB 0 +#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) +#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK) + +#define LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define LF_TIMER_STATUS2_OFFSET 0x00000074 +#define LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define LF_TIMER3_ADDRESS 0x00000078 +#define LF_TIMER3_OFFSET 0x00000078 +#define LF_TIMER3_TARGET_MSB 31 +#define LF_TIMER3_TARGET_LSB 0 +#define LF_TIMER3_TARGET_MASK 0xffffffff +#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB) +#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK) + +#define LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define LF_TIMER_COUNT3_OFFSET 0x0000007c +#define LF_TIMER_COUNT3_VALUE_MSB 31 +#define LF_TIMER_COUNT3_VALUE_LSB 0 +#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB) +#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK) + +#define LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL3_RESET_MSB 0 +#define LF_TIMER_CONTROL3_RESET_LSB 0 +#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) +#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK) + +#define LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define LF_TIMER_STATUS3_OFFSET 0x00000084 +#define LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define HF_TIMER_ADDRESS 0x00000088 +#define HF_TIMER_OFFSET 0x00000088 +#define HF_TIMER_TARGET_MSB 31 +#define HF_TIMER_TARGET_LSB 12 +#define HF_TIMER_TARGET_MASK 0xfffff000 +#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB) +#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK) + +#define HF_TIMER_COUNT_ADDRESS 0x0000008c +#define HF_TIMER_COUNT_OFFSET 0x0000008c +#define HF_TIMER_COUNT_VALUE_MSB 31 +#define HF_TIMER_COUNT_VALUE_LSB 12 +#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB) +#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK) + +#define HF_LF_COUNT_ADDRESS 0x00000090 +#define HF_LF_COUNT_OFFSET 0x00000090 +#define HF_LF_COUNT_VALUE_MSB 31 +#define HF_LF_COUNT_VALUE_LSB 0 +#define HF_LF_COUNT_VALUE_MASK 0xffffffff +#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB) +#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK) + +#define HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define HF_TIMER_CONTROL_OFFSET 0x00000094 +#define HF_TIMER_CONTROL_ENABLE_MSB 3 +#define HF_TIMER_CONTROL_ENABLE_LSB 3 +#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) +#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) +#define HF_TIMER_CONTROL_ON_MSB 2 +#define HF_TIMER_CONTROL_ON_LSB 2 +#define HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB) +#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define HF_TIMER_CONTROL_RESET_MSB 0 +#define HF_TIMER_CONTROL_RESET_LSB 0 +#define HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB) +#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK) + +#define HF_TIMER_STATUS_ADDRESS 0x00000098 +#define HF_TIMER_STATUS_OFFSET 0x00000098 +#define HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) + +#define RTC_CONTROL_ADDRESS 0x0000009c +#define RTC_CONTROL_OFFSET 0x0000009c +#define RTC_CONTROL_ENABLE_MSB 2 +#define RTC_CONTROL_ENABLE_LSB 2 +#define RTC_CONTROL_ENABLE_MASK 0x00000004 +#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB) +#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK) +#define RTC_CONTROL_LOAD_RTC_MSB 1 +#define RTC_CONTROL_LOAD_RTC_LSB 1 +#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB) +#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK) +#define RTC_CONTROL_LOAD_ALARM_MSB 0 +#define RTC_CONTROL_LOAD_ALARM_LSB 0 +#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) +#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) + +#define RTC_TIME_ADDRESS 0x000000a0 +#define RTC_TIME_OFFSET 0x000000a0 +#define RTC_TIME_WEEK_DAY_MSB 26 +#define RTC_TIME_WEEK_DAY_LSB 24 +#define RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB) +#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK) +#define RTC_TIME_HOUR_MSB 21 +#define RTC_TIME_HOUR_LSB 16 +#define RTC_TIME_HOUR_MASK 0x003f0000 +#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB) +#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK) +#define RTC_TIME_MINUTE_MSB 14 +#define RTC_TIME_MINUTE_LSB 8 +#define RTC_TIME_MINUTE_MASK 0x00007f00 +#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB) +#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK) +#define RTC_TIME_SECOND_MSB 6 +#define RTC_TIME_SECOND_LSB 0 +#define RTC_TIME_SECOND_MASK 0x0000007f +#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB) +#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK) + +#define RTC_DATE_ADDRESS 0x000000a4 +#define RTC_DATE_OFFSET 0x000000a4 +#define RTC_DATE_YEAR_MSB 23 +#define RTC_DATE_YEAR_LSB 16 +#define RTC_DATE_YEAR_MASK 0x00ff0000 +#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB) +#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK) +#define RTC_DATE_MONTH_MSB 12 +#define RTC_DATE_MONTH_LSB 8 +#define RTC_DATE_MONTH_MASK 0x00001f00 +#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB) +#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK) +#define RTC_DATE_MONTH_DAY_MSB 5 +#define RTC_DATE_MONTH_DAY_LSB 0 +#define RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB) +#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK) + +#define RTC_SET_TIME_ADDRESS 0x000000a8 +#define RTC_SET_TIME_OFFSET 0x000000a8 +#define RTC_SET_TIME_WEEK_DAY_MSB 26 +#define RTC_SET_TIME_WEEK_DAY_LSB 24 +#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB) +#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK) +#define RTC_SET_TIME_HOUR_MSB 21 +#define RTC_SET_TIME_HOUR_LSB 16 +#define RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB) +#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK) +#define RTC_SET_TIME_MINUTE_MSB 14 +#define RTC_SET_TIME_MINUTE_LSB 8 +#define RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB) +#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK) +#define RTC_SET_TIME_SECOND_MSB 6 +#define RTC_SET_TIME_SECOND_LSB 0 +#define RTC_SET_TIME_SECOND_MASK 0x0000007f +#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB) +#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK) + +#define RTC_SET_DATE_ADDRESS 0x000000ac +#define RTC_SET_DATE_OFFSET 0x000000ac +#define RTC_SET_DATE_YEAR_MSB 23 +#define RTC_SET_DATE_YEAR_LSB 16 +#define RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB) +#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK) +#define RTC_SET_DATE_MONTH_MSB 12 +#define RTC_SET_DATE_MONTH_LSB 8 +#define RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB) +#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK) +#define RTC_SET_DATE_MONTH_DAY_MSB 5 +#define RTC_SET_DATE_MONTH_DAY_LSB 0 +#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) +#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) + +#define RTC_SET_ALARM_ADDRESS 0x000000b0 +#define RTC_SET_ALARM_OFFSET 0x000000b0 +#define RTC_SET_ALARM_HOUR_MSB 21 +#define RTC_SET_ALARM_HOUR_LSB 16 +#define RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB) +#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK) +#define RTC_SET_ALARM_MINUTE_MSB 14 +#define RTC_SET_ALARM_MINUTE_LSB 8 +#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB) +#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK) +#define RTC_SET_ALARM_SECOND_MSB 6 +#define RTC_SET_ALARM_SECOND_LSB 0 +#define RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB) +#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK) + +#define RTC_CONFIG_ADDRESS 0x000000b4 +#define RTC_CONFIG_OFFSET 0x000000b4 +#define RTC_CONFIG_BCD_MSB 2 +#define RTC_CONFIG_BCD_LSB 2 +#define RTC_CONFIG_BCD_MASK 0x00000004 +#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB) +#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK) +#define RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) +#define RTC_CONFIG_DSE_MSB 0 +#define RTC_CONFIG_DSE_LSB 0 +#define RTC_CONFIG_DSE_MASK 0x00000001 +#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB) +#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK) + +#define RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define RTC_ALARM_STATUS_ENABLE_MSB 1 +#define RTC_ALARM_STATUS_ENABLE_LSB 1 +#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) +#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) +#define RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define UART_WAKEUP_ADDRESS 0x000000bc +#define UART_WAKEUP_OFFSET 0x000000bc +#define UART_WAKEUP_ENABLE_MSB 0 +#define UART_WAKEUP_ENABLE_LSB 0 +#define UART_WAKEUP_ENABLE_MASK 0x00000001 +#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB) +#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK) + +#define RESET_CAUSE_ADDRESS 0x000000c0 +#define RESET_CAUSE_OFFSET 0x000000c0 +#define RESET_CAUSE_LAST_MSB 2 +#define RESET_CAUSE_LAST_LSB 0 +#define RESET_CAUSE_LAST_MASK 0x00000007 +#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) +#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) + +#define SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define SYSTEM_SLEEP_OFFSET 0x000000c4 +#define SYSTEM_SLEEP_HOST_IF_MSB 4 +#define SYSTEM_SLEEP_HOST_IF_LSB 4 +#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB) +#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK) +#define SYSTEM_SLEEP_MBOX_MSB 3 +#define SYSTEM_SLEEP_MBOX_LSB 3 +#define SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB) +#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK) +#define SYSTEM_SLEEP_MAC_IF_MSB 2 +#define SYSTEM_SLEEP_MAC_IF_LSB 2 +#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB) +#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK) +#define SYSTEM_SLEEP_LIGHT_MSB 1 +#define SYSTEM_SLEEP_LIGHT_LSB 1 +#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB) +#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK) +#define SYSTEM_SLEEP_DISABLE_MSB 0 +#define SYSTEM_SLEEP_DISABLE_LSB 0 +#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB) +#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) + +#define SDIO_WRAPPER_ADDRESS 0x000000c8 +#define SDIO_WRAPPER_OFFSET 0x000000c8 +#define SDIO_WRAPPER_SLEEP_MSB 3 +#define SDIO_WRAPPER_SLEEP_LSB 3 +#define SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB) +#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK) +#define SDIO_WRAPPER_WAKEUP_MSB 2 +#define SDIO_WRAPPER_WAKEUP_LSB 2 +#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB) +#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK) +#define SDIO_WRAPPER_SOC_ON_MSB 1 +#define SDIO_WRAPPER_SOC_ON_LSB 1 +#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB) +#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK) +#define SDIO_WRAPPER_ON_MSB 0 +#define SDIO_WRAPPER_ON_LSB 0 +#define SDIO_WRAPPER_ON_MASK 0x00000001 +#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB) +#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK) + +#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define KEEP_AWAKE_ADDRESS 0x000000d0 +#define KEEP_AWAKE_OFFSET 0x000000d0 +#define KEEP_AWAKE_COUNT_MSB 7 +#define KEEP_AWAKE_COUNT_LSB 0 +#define KEEP_AWAKE_COUNT_MASK 0x000000ff +#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB) +#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK) + +#define LPO_CAL_TIME_ADDRESS 0x000000d4 +#define LPO_CAL_TIME_OFFSET 0x000000d4 +#define LPO_CAL_TIME_LENGTH_MSB 13 +#define LPO_CAL_TIME_LENGTH_LSB 0 +#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB) +#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK) + +#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define LPO_CAL_ADDRESS 0x000000e0 +#define LPO_CAL_OFFSET 0x000000e0 +#define LPO_CAL_ENABLE_MSB 20 +#define LPO_CAL_ENABLE_LSB 20 +#define LPO_CAL_ENABLE_MASK 0x00100000 +#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB) +#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) +#define LPO_CAL_COUNT_MSB 19 +#define LPO_CAL_COUNT_LSB 0 +#define LPO_CAL_COUNT_MASK 0x000fffff +#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB) +#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK) + +#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define LPO_CAL_TEST_STATUS_READY_MSB 16 +#define LPO_CAL_TEST_STATUS_READY_LSB 16 +#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) +#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) +#define LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define CHIP_ID_ADDRESS 0x000000ec +#define CHIP_ID_OFFSET 0x000000ec +#define CHIP_ID_DEVICE_ID_MSB 31 +#define CHIP_ID_DEVICE_ID_LSB 16 +#define CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB) +#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK) +#define CHIP_ID_CONFIG_ID_MSB 15 +#define CHIP_ID_CONFIG_ID_LSB 4 +#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB) +#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK) +#define CHIP_ID_VERSION_ID_MSB 3 +#define CHIP_ID_VERSION_ID_LSB 0 +#define CHIP_ID_VERSION_ID_MASK 0x0000000f +#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB) +#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK) + +#define DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define DERIVED_RTC_CLK_FORCE_MSB 17 +#define DERIVED_RTC_CLK_FORCE_LSB 16 +#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB) +#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK) +#define DERIVED_RTC_CLK_PERIOD_MSB 15 +#define DERIVED_RTC_CLK_PERIOD_LSB 1 +#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) +#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c +#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) + +#define POWER_REG_ADDRESS 0x00000110 +#define POWER_REG_OFFSET 0x00000110 +#define POWER_REG_VLVL_MSB 11 +#define POWER_REG_VLVL_LSB 8 +#define POWER_REG_VLVL_MASK 0x00000f00 +#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB) +#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK) +#define POWER_REG_CPU_INT_ENABLE_MSB 7 +#define POWER_REG_CPU_INT_ENABLE_LSB 7 +#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) +#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) +#define POWER_REG_WLAN_ISO_DIS_MSB 6 +#define POWER_REG_WLAN_ISO_DIS_LSB 6 +#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) +#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) +#define POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) +#define POWER_REG_RADIO_PWD_EN_MSB 4 +#define POWER_REG_RADIO_PWD_EN_LSB 4 +#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB) +#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK) +#define POWER_REG_SOC_SCALE_EN_MSB 3 +#define POWER_REG_SOC_SCALE_EN_LSB 3 +#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 +#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB) +#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK) +#define POWER_REG_WLAN_SCALE_EN_MSB 2 +#define POWER_REG_WLAN_SCALE_EN_LSB 2 +#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 +#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) +#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) +#define POWER_REG_WLAN_PWD_EN_MSB 1 +#define POWER_REG_WLAN_PWD_EN_LSB 1 +#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB) +#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK) +#define POWER_REG_POWER_EN_MSB 0 +#define POWER_REG_POWER_EN_LSB 0 +#define POWER_REG_POWER_EN_MASK 0x00000001 +#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB) +#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK) + +#define CORE_CLK_CTRL_ADDRESS 0x00000114 +#define CORE_CLK_CTRL_OFFSET 0x00000114 +#define CORE_CLK_CTRL_DIV_MSB 2 +#define CORE_CLK_CTRL_DIV_LSB 0 +#define CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB) +#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK) + +#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 +#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 +#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 +#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 +#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) +#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) + +#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 +#define SDIO_SETUP_CONFIG_OFFSET 0x00000140 +#define SDIO_SETUP_CONFIG_ENABLE_MSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_LSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) +#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) +#define SDIO_SETUP_CONFIG_CLEAR_MSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_LSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) +#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CONFIG_ADDRESS 0x00000144 +#define CPU_SETUP_CONFIG_OFFSET 0x00000144 +#define CPU_SETUP_CONFIG_ENABLE_MSB 1 +#define CPU_SETUP_CONFIG_ENABLE_LSB 1 +#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) +#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) +#define CPU_SETUP_CONFIG_CLEAR_MSB 0 +#define CPU_SETUP_CONFIG_CLEAR_LSB 0 +#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) +#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 +#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 +#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 +#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 +#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) +#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) + +#define BB_SETUP_CONFIG_ADDRESS 0x00000180 +#define BB_SETUP_CONFIG_OFFSET 0x00000180 +#define BB_SETUP_CONFIG_ENABLE_MSB 1 +#define BB_SETUP_CONFIG_ENABLE_LSB 1 +#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) +#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) +#define BB_SETUP_CONFIG_CLEAR_MSB 0 +#define BB_SETUP_CONFIG_CLEAR_LSB 0 +#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB) +#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK) + +#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 +#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 +#define BB_SETUP_CIRCUIT_VECTOR_MSB 7 +#define BB_SETUP_CIRCUIT_VECTOR_LSB 0 +#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) +#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) + +#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 +#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_reg_reg_s { + volatile unsigned int reset_control; + volatile unsigned int xtal_control; + volatile unsigned int tcxo_detect; + volatile unsigned int xtal_test; + volatile unsigned int quadrature; + volatile unsigned int pll_control; + volatile unsigned int pll_settle; + volatile unsigned int xtal_settle; + volatile unsigned int cpu_clock; + volatile unsigned int clock_out; + volatile unsigned int clock_control; + volatile unsigned int bias_override; + volatile unsigned int wdt_control; + volatile unsigned int wdt_status; + volatile unsigned int wdt; + volatile unsigned int wdt_count; + volatile unsigned int wdt_reset; + volatile unsigned int int_status; + volatile unsigned int lf_timer0; + volatile unsigned int lf_timer_count0; + volatile unsigned int lf_timer_control0; + volatile unsigned int lf_timer_status0; + volatile unsigned int lf_timer1; + volatile unsigned int lf_timer_count1; + volatile unsigned int lf_timer_control1; + volatile unsigned int lf_timer_status1; + volatile unsigned int lf_timer2; + volatile unsigned int lf_timer_count2; + volatile unsigned int lf_timer_control2; + volatile unsigned int lf_timer_status2; + volatile unsigned int lf_timer3; + volatile unsigned int lf_timer_count3; + volatile unsigned int lf_timer_control3; + volatile unsigned int lf_timer_status3; + volatile unsigned int hf_timer; + volatile unsigned int hf_timer_count; + volatile unsigned int hf_lf_count; + volatile unsigned int hf_timer_control; + volatile unsigned int hf_timer_status; + volatile unsigned int rtc_control; + volatile unsigned int rtc_time; + volatile unsigned int rtc_date; + volatile unsigned int rtc_set_time; + volatile unsigned int rtc_set_date; + volatile unsigned int rtc_set_alarm; + volatile unsigned int rtc_config; + volatile unsigned int rtc_alarm_status; + volatile unsigned int uart_wakeup; + volatile unsigned int reset_cause; + volatile unsigned int system_sleep; + volatile unsigned int sdio_wrapper; + volatile unsigned int mac_sleep_control; + volatile unsigned int keep_awake; + volatile unsigned int lpo_cal_time; + volatile unsigned int lpo_init_dividend_int; + volatile unsigned int lpo_init_dividend_fraction; + volatile unsigned int lpo_cal; + volatile unsigned int lpo_cal_test_control; + volatile unsigned int lpo_cal_test_status; + volatile unsigned int chip_id; + volatile unsigned int derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int mac_pcu_slp_beacon; + volatile unsigned int power_reg; + volatile unsigned int core_clk_ctrl; + unsigned char pad0[8]; /* pad to 0x120 */ + volatile unsigned int sdio_setup_circuit[8]; + volatile unsigned int sdio_setup_config; + volatile unsigned int cpu_setup_config; + unsigned char pad1[24]; /* pad to 0x160 */ + volatile unsigned int cpu_setup_circuit[8]; + volatile unsigned int bb_setup_config; + unsigned char pad2[28]; /* pad to 0x1a0 */ + volatile unsigned int bb_setup_circuit[8]; + volatile unsigned int gpio_wakeup_control; +} rtc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h new file mode 100644 index 000000000000..44d24661761e --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/si_reg.h @@ -0,0 +1,205 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h new file mode 100644 index 000000000000..db573106dcd2 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/uart_reg.h @@ -0,0 +1,346 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define RBR_ADDRESS 0x00000000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00000000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00000000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00000004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00000004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00000008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00000008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0000000c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00000010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00000014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00000018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + +#define SCR_ADDRESS 0x0000001c +#define SCR_OFFSET 0x0000001c +#define SCR_SCR_MSB 7 +#define SCR_SCR_LSB 0 +#define SCR_SCR_MASK 0x000000ff +#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB) +#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK) + +#define SRBR_ADDRESS 0x00000020 +#define SRBR_OFFSET 0x00000020 +#define SRBR_SRBR_MSB 7 +#define SRBR_SRBR_LSB 0 +#define SRBR_SRBR_MASK 0x000000ff +#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB) +#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK) + +#define SIIR_ADDRESS 0x00000028 +#define SIIR_OFFSET 0x00000028 +#define SIIR_SIIR_MSB 7 +#define SIIR_SIIR_LSB 0 +#define SIIR_SIIR_MASK 0x000000ff +#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB) +#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK) + +#define MWR_ADDRESS 0x0000002c +#define MWR_OFFSET 0x0000002c +#define MWR_MWR_MSB 31 +#define MWR_MWR_LSB 0 +#define MWR_MWR_MASK 0xffffffff +#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB) +#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK) + +#define SLSR_ADDRESS 0x00000034 +#define SLSR_OFFSET 0x00000034 +#define SLSR_SLSR_MSB 7 +#define SLSR_SLSR_LSB 0 +#define SLSR_SLSR_MASK 0x000000ff +#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB) +#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK) + +#define SMSR_ADDRESS 0x00000038 +#define SMSR_OFFSET 0x00000038 +#define SMSR_SMSR_MSB 7 +#define SMSR_SMSR_LSB 0 +#define SMSR_SMSR_MASK 0x000000ff +#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB) +#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK) + +#define MRR_ADDRESS 0x0000003c +#define MRR_OFFSET 0x0000003c +#define MRR_MRR_MSB 31 +#define MRR_MRR_LSB 0 +#define MRR_MRR_MASK 0xffffffff +#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB) +#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int rbr; + volatile unsigned int dlh; + volatile unsigned int iir; + volatile unsigned int lcr; + volatile unsigned int mcr; + volatile unsigned int lsr; + volatile unsigned int msr; + volatile unsigned int scr; + volatile unsigned int srbr; + unsigned char pad0[4]; /* pad to 0x28 */ + volatile unsigned int siir; + volatile unsigned int mwr; + unsigned char pad1[4]; /* pad to 0x34 */ + volatile unsigned int slsr; + volatile unsigned int smsr; + volatile unsigned int mrr; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h new file mode 100644 index 000000000000..0c15ebfaeaa6 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw/vmc_reg.h @@ -0,0 +1,95 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _VMC_REG_REG_H_ +#define _VMC_REG_REG_H_ + +#define MC_TCAM_VALID_ADDRESS 0x00000000 +#define MC_TCAM_VALID_OFFSET 0x00000000 +#define MC_TCAM_VALID_BIT_MSB 0 +#define MC_TCAM_VALID_BIT_LSB 0 +#define MC_TCAM_VALID_BIT_MASK 0x00000001 +#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB) +#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK) + +#define MC_TCAM_MASK_ADDRESS 0x00000080 +#define MC_TCAM_MASK_OFFSET 0x00000080 +#define MC_TCAM_MASK_SIZE_MSB 2 +#define MC_TCAM_MASK_SIZE_LSB 0 +#define MC_TCAM_MASK_SIZE_MASK 0x00000007 +#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB) +#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK) + +#define MC_TCAM_COMPARE_ADDRESS 0x00000100 +#define MC_TCAM_COMPARE_OFFSET 0x00000100 +#define MC_TCAM_COMPARE_KEY_MSB 21 +#define MC_TCAM_COMPARE_KEY_LSB 5 +#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0 +#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB) +#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK) + +#define MC_TCAM_TARGET_ADDRESS 0x00000180 +#define MC_TCAM_TARGET_OFFSET 0x00000180 +#define MC_TCAM_TARGET_ADDR_MSB 21 +#define MC_TCAM_TARGET_ADDR_LSB 5 +#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0 +#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB) +#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK) + +#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200 +#define ADDR_ERROR_CONTROL_OFFSET 0x00000200 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define ADDR_ERROR_STATUS_ADDRESS 0x00000204 +#define ADDR_ERROR_STATUS_OFFSET 0x00000204 +#define ADDR_ERROR_STATUS_WRITE_MSB 25 +#define ADDR_ERROR_STATUS_WRITE_LSB 25 +#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB) +#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK) +#define ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB) +#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_reg_reg_s { + volatile unsigned int mc_tcam_valid[32]; + volatile unsigned int mc_tcam_mask[32]; + volatile unsigned int mc_tcam_compare[32]; + volatile unsigned int mc_tcam_target[32]; + volatile unsigned int addr_error_control; + volatile unsigned int addr_error_status; +} vmc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h new file mode 100644 index 000000000000..28b972afc8d7 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_intf_reg.h @@ -0,0 +1,83 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_INTF_REG_REG_H_ +#define _ANALOG_INTF_REG_REG_H_ + +#define SW_OVERRIDE_ADDRESS 0x00000080 +#define SW_OVERRIDE_OFFSET 0x00000080 +#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1 +#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002 +#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB) +#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK) +#define SW_OVERRIDE_ENABLE_MSB 0 +#define SW_OVERRIDE_ENABLE_LSB 0 +#define SW_OVERRIDE_ENABLE_MASK 0x00000001 +#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB) +#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK) + +#define SIN_VAL_ADDRESS 0x00000084 +#define SIN_VAL_OFFSET 0x00000084 +#define SIN_VAL_SIN_MSB 0 +#define SIN_VAL_SIN_LSB 0 +#define SIN_VAL_SIN_MASK 0x00000001 +#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB) +#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK) + +#define SW_SCLK_ADDRESS 0x00000088 +#define SW_SCLK_OFFSET 0x00000088 +#define SW_SCLK_SW_SCLK_MSB 0 +#define SW_SCLK_SW_SCLK_LSB 0 +#define SW_SCLK_SW_SCLK_MASK 0x00000001 +#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB) +#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK) + +#define SW_CNTL_ADDRESS 0x0000008c +#define SW_CNTL_OFFSET 0x0000008c +#define SW_CNTL_SW_SCAPTURE_MSB 2 +#define SW_CNTL_SW_SCAPTURE_LSB 2 +#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004 +#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB) +#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK) +#define SW_CNTL_SW_SUPDATE_MSB 1 +#define SW_CNTL_SW_SUPDATE_LSB 1 +#define SW_CNTL_SW_SUPDATE_MASK 0x00000002 +#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB) +#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK) +#define SW_CNTL_SW_SOUT_MSB 0 +#define SW_CNTL_SW_SOUT_LSB 0 +#define SW_CNTL_SW_SOUT_MASK 0x00000001 +#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB) +#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_reg_reg_s { + unsigned char pad0[128]; /* pad to 0x80 */ + volatile unsigned int sw_override; + volatile unsigned int sin_val; + volatile unsigned int sw_sclk; + volatile unsigned int sw_cntl; +} analog_intf_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h new file mode 100644 index 000000000000..c485ac725c2f --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/analog_reg.h @@ -0,0 +1,1951 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _ANALOG_REG_REG_H_ +#define _ANALOG_REG_REG_H_ + +#define SYNTH_SYNTH1_ADDRESS 0x00000000 +#define SYNTH_SYNTH1_OFFSET 0x00000000 +#define SYNTH_SYNTH1_PWD_BIAS_MSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_LSB 31 +#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB) +#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK) +#define SYNTH_SYNTH1_PWD_CP_MSB 30 +#define SYNTH_SYNTH1_PWD_CP_LSB 30 +#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000 +#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB) +#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK) +#define SYNTH_SYNTH1_PWD_VCMON_MSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_LSB 29 +#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB) +#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK) +#define SYNTH_SYNTH1_PWD_VCO_MSB 28 +#define SYNTH_SYNTH1_PWD_VCO_LSB 28 +#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000 +#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB) +#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK) +#define SYNTH_SYNTH1_PWD_PRESC_MSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_LSB 27 +#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB) +#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK) +#define SYNTH_SYNTH1_PWD_LODIV_MSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_LSB 26 +#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000 +#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB) +#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK) +#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25 +#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000 +#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB) +#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK) +#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24 +#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000 +#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB) +#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) +#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23 +#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000 +#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB) +#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) +#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22 +#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000 +#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB) +#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) +#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21 +#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20 +#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000 +#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB) +#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) +#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19 +#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18 +#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000 +#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB) +#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK) +#define SYNTH_SYNTH1_SLIDINGIF_MSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_LSB 17 +#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000 +#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB) +#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK) +#define SYNTH_SYNTH1_SPARE_PWD_MSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_LSB 16 +#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000 +#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB) +#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK) +#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15 +#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000 +#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB) +#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14 +#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000 +#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB) +#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK) +#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13 +#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000 +#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB) +#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) +#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12 +#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10 +#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00 +#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB) +#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200 +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) +#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100 +#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080 +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040 +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) +#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_MSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_LSB 5 +#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020 +#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK) +#define SYNTH_SYNTH1_MONITOR_REF_MSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_LSB 4 +#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010 +#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB) +#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008 +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) +#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004 +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002 +#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) +#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001 +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) +#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) + +#define SYNTH_SYNTH2_ADDRESS 0x00000004 +#define SYNTH_SYNTH2_OFFSET 0x00000004 +#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31 +#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29 +#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB) +#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK) +#define SYNTH_SYNTH2_VC_HI_REF_MSB 28 +#define SYNTH_SYNTH2_VC_HI_REF_LSB 26 +#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB) +#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK) +#define SYNTH_SYNTH2_VC_MID_REF_MSB 25 +#define SYNTH_SYNTH2_VC_MID_REF_LSB 23 +#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB) +#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK) +#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22 +#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20 +#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB) +#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000 +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) +#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) +#define SYNTH_SYNTH2_LOOP_CP_MSB 14 +#define SYNTH_SYNTH2_LOOP_CP_LSB 10 +#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00 +#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB) +#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK) +#define SYNTH_SYNTH2_LOOP_RS_MSB 9 +#define SYNTH_SYNTH2_LOOP_RS_LSB 5 +#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0 +#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB) +#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK) +#define SYNTH_SYNTH2_LOOP_CS_MSB 4 +#define SYNTH_SYNTH2_LOOP_CS_LSB 3 +#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018 +#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB) +#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK) +#define SYNTH_SYNTH2_SPARE_BITS_MSB 2 +#define SYNTH_SYNTH2_SPARE_BITS_LSB 0 +#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007 +#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB) +#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK) + +#define SYNTH_SYNTH3_ADDRESS 0x00000008 +#define SYNTH_SYNTH3_OFFSET 0x00000008 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) +#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) +#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23 +#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18 +#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB) +#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) +#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) +#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) + +#define SYNTH_SYNTH4_ADDRESS 0x0000000c +#define SYNTH_SYNTH4_OFFSET 0x0000000c +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) +#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) +#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30 +#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB) +#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) +#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) +#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) +#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27 +#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB) +#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK) +#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26 +#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB) +#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) +#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25 +#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18 +#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB) +#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) +#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17 +#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB) +#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) +#define SYNTH_SYNTH4_REFDIVSEL_MSB 16 +#define SYNTH_SYNTH4_REFDIVSEL_LSB 15 +#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000 +#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB) +#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK) +#define SYNTH_SYNTH4_PFDDELAY_MSB 14 +#define SYNTH_SYNTH4_PFDDELAY_LSB 14 +#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000 +#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB) +#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK) +#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13 +#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB) +#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK) +#define SYNTH_SYNTH4_PRESCSEL_MSB 12 +#define SYNTH_SYNTH4_PRESCSEL_LSB 11 +#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800 +#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB) +#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK) +#define SYNTH_SYNTH4_RESET_PRESC_MSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_LSB 10 +#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB) +#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK) +#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9 +#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB) +#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK) +#define SYNTH_SYNTH4_SDM_MODE_MSB 8 +#define SYNTH_SYNTH4_SDM_MODE_LSB 8 +#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100 +#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB) +#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK) +#define SYNTH_SYNTH4_SDM_DITHER_MSB 7 +#define SYNTH_SYNTH4_SDM_DITHER_LSB 6 +#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB) +#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) +#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010 +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) +#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) +#define SYNTH_SYNTH4_SPARE_MISC_MSB 3 +#define SYNTH_SYNTH4_SPARE_MISC_LSB 2 +#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c +#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB) +#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK) +#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1 +#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB) +#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001 +#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) +#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) + +#define SYNTH_SYNTH5_ADDRESS 0x00000010 +#define SYNTH_SYNTH5_OFFSET 0x00000010 +#define SYNTH_SYNTH5_LOOP_IP0_MSB 31 +#define SYNTH_SYNTH5_LOOP_IP0_LSB 28 +#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000 +#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB) +#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK) +#define SYNTH_SYNTH5_SLOPE_IP_MSB 27 +#define SYNTH_SYNTH5_SLOPE_IP_LSB 25 +#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000 +#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB) +#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK) +#define SYNTH_SYNTH5_CPBIAS_MSB 24 +#define SYNTH_SYNTH5_CPBIAS_LSB 23 +#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000 +#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB) +#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK) +#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22 +#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000 +#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB) +#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) +#define SYNTH_SYNTH5_CPLOWLK_MSB 21 +#define SYNTH_SYNTH5_CPLOWLK_LSB 21 +#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000 +#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB) +#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK) +#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20 +#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17 +#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000 +#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB) +#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) +#define SYNTH_SYNTH5_CAPRANGE1_MSB 16 +#define SYNTH_SYNTH5_CAPRANGE1_LSB 13 +#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000 +#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB) +#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK) +#define SYNTH_SYNTH5_CAPRANGE2_MSB 12 +#define SYNTH_SYNTH5_CAPRANGE2_LSB 9 +#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00 +#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB) +#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK) +#define SYNTH_SYNTH5_CAPRANGE3_MSB 8 +#define SYNTH_SYNTH5_CAPRANGE3_LSB 5 +#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0 +#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB) +#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2 +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) +#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) +#define SYNTH_SYNTH5_SPARE_MSB 1 +#define SYNTH_SYNTH5_SPARE_LSB 0 +#define SYNTH_SYNTH5_SPARE_MASK 0x00000003 +#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB) +#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK) + +#define SYNTH_SYNTH6_ADDRESS 0x00000014 +#define SYNTH_SYNTH6_OFFSET 0x00000014 +#define SYNTH_SYNTH6_IRCP_MSB 31 +#define SYNTH_SYNTH6_IRCP_LSB 29 +#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000 +#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB) +#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK) +#define SYNTH_SYNTH6_IRVCMON_MSB 28 +#define SYNTH_SYNTH6_IRVCMON_LSB 26 +#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000 +#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB) +#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK) +#define SYNTH_SYNTH6_IRSPARE_MSB 25 +#define SYNTH_SYNTH6_IRSPARE_LSB 23 +#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000 +#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB) +#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK) +#define SYNTH_SYNTH6_ICPRESC_MSB 22 +#define SYNTH_SYNTH6_ICPRESC_LSB 20 +#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000 +#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB) +#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK) +#define SYNTH_SYNTH6_ICLODIV_MSB 19 +#define SYNTH_SYNTH6_ICLODIV_LSB 17 +#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000 +#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB) +#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK) +#define SYNTH_SYNTH6_ICLOMIX_MSB 16 +#define SYNTH_SYNTH6_ICLOMIX_LSB 14 +#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000 +#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB) +#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK) +#define SYNTH_SYNTH6_ICSPAREA_MSB 13 +#define SYNTH_SYNTH6_ICSPAREA_LSB 11 +#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800 +#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB) +#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK) +#define SYNTH_SYNTH6_ICSPAREB_MSB 10 +#define SYNTH_SYNTH6_ICSPAREB_LSB 8 +#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700 +#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB) +#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK) +#define SYNTH_SYNTH6_ICVCO_MSB 7 +#define SYNTH_SYNTH6_ICVCO_LSB 5 +#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0 +#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB) +#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK) +#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4 +#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3 +#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018 +#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB) +#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) +#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2 +#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0 +#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007 +#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB) +#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK) + +#define SYNTH_SYNTH7_ADDRESS 0x00000018 +#define SYNTH_SYNTH7_OFFSET 0x00000018 +#define SYNTH_SYNTH7_SYNTH_ON_MSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_LSB 31 +#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000 +#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB) +#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000 +#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) +#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) +#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26 +#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000 +#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB) +#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) +#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) +#define SYNTH_SYNTH7_PIN_VC_MSB 24 +#define SYNTH_SYNTH7_PIN_VC_LSB 24 +#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000 +#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB) +#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK) +#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23 +#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16 +#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000 +#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB) +#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) +#define SYNTH_SYNTH7_SHORT_R_MSB 15 +#define SYNTH_SYNTH7_SHORT_R_LSB 15 +#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000 +#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB) +#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK) +#define SYNTH_SYNTH7_RESET_RFD_MSB 14 +#define SYNTH_SYNTH7_RESET_RFD_LSB 14 +#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000 +#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB) +#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK) +#define SYNTH_SYNTH7_RESET_PFD_MSB 13 +#define SYNTH_SYNTH7_RESET_PFD_LSB 13 +#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000 +#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB) +#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000 +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) +#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) +#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11 +#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800 +#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB) +#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK) +#define SYNTH_SYNTH7_VC2HIGH_MSB 10 +#define SYNTH_SYNTH7_VC2HIGH_LSB 10 +#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400 +#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB) +#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK) +#define SYNTH_SYNTH7_VC2LOW_MSB 9 +#define SYNTH_SYNTH7_VC2LOW_LSB 9 +#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200 +#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB) +#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK) +#define SYNTH_SYNTH7_LOOP_IP_MSB 8 +#define SYNTH_SYNTH7_LOOP_IP_LSB 5 +#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0 +#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB) +#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK) +#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4 +#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3 +#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018 +#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB) +#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) +#define SYNTH_SYNTH7_SPARE_READ_MSB 2 +#define SYNTH_SYNTH7_SPARE_READ_LSB 0 +#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007 +#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB) +#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK) + +#define SYNTH_SYNTH8_ADDRESS 0x0000001c +#define SYNTH_SYNTH8_OFFSET 0x0000001c +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000 +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) +#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) +#define SYNTH_SYNTH8_FRACMODE_MSB 30 +#define SYNTH_SYNTH8_FRACMODE_LSB 30 +#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000 +#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB) +#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK) +#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29 +#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28 +#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000 +#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB) +#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK) +#define SYNTH_SYNTH8_SPARE_MSB 27 +#define SYNTH_SYNTH8_SPARE_LSB 27 +#define SYNTH_SYNTH8_SPARE_MASK 0x08000000 +#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB) +#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK) +#define SYNTH_SYNTH8_CHANSEL_MSB 26 +#define SYNTH_SYNTH8_CHANSEL_LSB 18 +#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000 +#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB) +#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK) +#define SYNTH_SYNTH8_CHANFRAC_MSB 17 +#define SYNTH_SYNTH8_CHANFRAC_LSB 1 +#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe +#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB) +#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK) +#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0 +#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001 +#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB) +#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) + +#define RF5G_RF5G1_ADDRESS 0x00000020 +#define RF5G_RF5G1_OFFSET 0x00000020 +#define RF5G_RF5G1_PDTXLO5_MSB 31 +#define RF5G_RF5G1_PDTXLO5_LSB 31 +#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000 +#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB) +#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK) +#define RF5G_RF5G1_PDTXMIX5_MSB 30 +#define RF5G_RF5G1_PDTXMIX5_LSB 30 +#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000 +#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB) +#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK) +#define RF5G_RF5G1_PDTXBUF5_MSB 29 +#define RF5G_RF5G1_PDTXBUF5_LSB 29 +#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000 +#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB) +#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK) +#define RF5G_RF5G1_PDPADRV5_MSB 28 +#define RF5G_RF5G1_PDPADRV5_LSB 28 +#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000 +#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB) +#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK) +#define RF5G_RF5G1_PDPAOUT5_MSB 27 +#define RF5G_RF5G1_PDPAOUT5_LSB 27 +#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000 +#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB) +#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK) +#define RF5G_RF5G1_TUNE_PADRV5_MSB 26 +#define RF5G_RF5G1_TUNE_PADRV5_LSB 24 +#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000 +#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB) +#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK) +#define RF5G_RF5G1_PWDTXPKD_MSB 23 +#define RF5G_RF5G1_PWDTXPKD_LSB 21 +#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000 +#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB) +#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK) +#define RF5G_RF5G1_DB5_MSB 20 +#define RF5G_RF5G1_DB5_LSB 18 +#define RF5G_RF5G1_DB5_MASK 0x001c0000 +#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB) +#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK) +#define RF5G_RF5G1_OB5_MSB 17 +#define RF5G_RF5G1_OB5_LSB 15 +#define RF5G_RF5G1_OB5_MASK 0x00038000 +#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB) +#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK) +#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14 +#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12 +#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000 +#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB) +#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK) +#define RF5G_RF5G1_PDLO5DIV_MSB 11 +#define RF5G_RF5G1_PDLO5DIV_LSB 11 +#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800 +#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB) +#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK) +#define RF5G_RF5G1_PDLO5MIX_MSB 10 +#define RF5G_RF5G1_PDLO5MIX_LSB 10 +#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400 +#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB) +#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK) +#define RF5G_RF5G1_PDQBUF5_MSB 9 +#define RF5G_RF5G1_PDQBUF5_LSB 9 +#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200 +#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB) +#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK) +#define RF5G_RF5G1_PDLO5AGC_MSB 8 +#define RF5G_RF5G1_PDLO5AGC_LSB 8 +#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100 +#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB) +#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK) +#define RF5G_RF5G1_PDREGLO5_MSB 7 +#define RF5G_RF5G1_PDREGLO5_LSB 7 +#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080 +#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB) +#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK) +#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6 +#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4 +#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070 +#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB) +#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK) +#define RF5G_RF5G1_LO5CONTROL_MSB 3 +#define RF5G_RF5G1_LO5CONTROL_LSB 3 +#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008 +#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB) +#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK) +#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2 +#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004 +#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB) +#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK) +#define RF5G_RF5G1_SPARE_MSB 1 +#define RF5G_RF5G1_SPARE_LSB 0 +#define RF5G_RF5G1_SPARE_MASK 0x00000003 +#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB) +#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK) + +#define RF5G_RF5G2_ADDRESS 0x00000024 +#define RF5G_RF5G2_OFFSET 0x00000024 +#define RF5G_RF5G2_AGCLO_B_MSB 31 +#define RF5G_RF5G2_AGCLO_B_LSB 29 +#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000 +#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB) +#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK) +#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28 +#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26 +#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000 +#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB) +#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK) +#define RF5G_RF5G2_PDCMOSLO5_MSB 25 +#define RF5G_RF5G2_PDCMOSLO5_LSB 25 +#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000 +#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB) +#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK) +#define RF5G_RF5G2_PDVGM5_MSB 24 +#define RF5G_RF5G2_PDVGM5_LSB 24 +#define RF5G_RF5G2_PDVGM5_MASK 0x01000000 +#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB) +#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK) +#define RF5G_RF5G2_PDCSLNA5_MSB 23 +#define RF5G_RF5G2_PDCSLNA5_LSB 23 +#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000 +#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB) +#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK) +#define RF5G_RF5G2_PDRFVGA5_MSB 22 +#define RF5G_RF5G2_PDRFVGA5_LSB 22 +#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000 +#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB) +#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK) +#define RF5G_RF5G2_PDREGFE5_MSB 21 +#define RF5G_RF5G2_PDREGFE5_LSB 21 +#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000 +#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB) +#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK) +#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20 +#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18 +#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000 +#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB) +#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK) +#define RF5G_RF5G2_BRFVGA5_MSB 17 +#define RF5G_RF5G2_BRFVGA5_LSB 15 +#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000 +#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB) +#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK) +#define RF5G_RF5G2_BCSLNA5_MSB 14 +#define RF5G_RF5G2_BCSLNA5_LSB 12 +#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000 +#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB) +#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK) +#define RF5G_RF5G2_BVGM5_MSB 11 +#define RF5G_RF5G2_BVGM5_LSB 9 +#define RF5G_RF5G2_BVGM5_MASK 0x00000e00 +#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB) +#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK) +#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8 +#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100 +#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB) +#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK) +#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7 +#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6 +#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0 +#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB) +#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) +#define RF5G_RF5G2_ENABLE_PCA_MSB 5 +#define RF5G_RF5G2_ENABLE_PCA_LSB 5 +#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020 +#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB) +#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK) +#define RF5G_RF5G2_TUNE_LO_MSB 4 +#define RF5G_RF5G2_TUNE_LO_LSB 2 +#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c +#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB) +#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK) +#define RF5G_RF5G2_SPARE_MSB 1 +#define RF5G_RF5G2_SPARE_LSB 0 +#define RF5G_RF5G2_SPARE_MASK 0x00000003 +#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB) +#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK) + +#define RF2G_RF2G1_ADDRESS 0x00000028 +#define RF2G_RF2G1_OFFSET 0x00000028 +#define RF2G_RF2G1_BLNA1_MSB 31 +#define RF2G_RF2G1_BLNA1_LSB 29 +#define RF2G_RF2G1_BLNA1_MASK 0xe0000000 +#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB) +#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK) +#define RF2G_RF2G1_BLNA1F_MSB 28 +#define RF2G_RF2G1_BLNA1F_LSB 26 +#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000 +#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB) +#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK) +#define RF2G_RF2G1_BLNA1BUF_MSB 25 +#define RF2G_RF2G1_BLNA1BUF_LSB 23 +#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000 +#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB) +#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK) +#define RF2G_RF2G1_BLNA2_MSB 22 +#define RF2G_RF2G1_BLNA2_LSB 20 +#define RF2G_RF2G1_BLNA2_MASK 0x00700000 +#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB) +#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK) +#define RF2G_RF2G1_DB_MSB 19 +#define RF2G_RF2G1_DB_LSB 17 +#define RF2G_RF2G1_DB_MASK 0x000e0000 +#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB) +#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK) +#define RF2G_RF2G1_OB_MSB 16 +#define RF2G_RF2G1_OB_LSB 14 +#define RF2G_RF2G1_OB_MASK 0x0001c000 +#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB) +#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK) +#define RF2G_RF2G1_FE_ATB_SEL_MSB 13 +#define RF2G_RF2G1_FE_ATB_SEL_LSB 11 +#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800 +#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB) +#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK) +#define RF2G_RF2G1_RF_ATB_SEL_MSB 10 +#define RF2G_RF2G1_RF_ATB_SEL_LSB 8 +#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700 +#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB) +#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK) +#define RF2G_RF2G1_SELLNA_MSB 7 +#define RF2G_RF2G1_SELLNA_LSB 7 +#define RF2G_RF2G1_SELLNA_MASK 0x00000080 +#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB) +#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK) +#define RF2G_RF2G1_LOCONTROL_MSB 6 +#define RF2G_RF2G1_LOCONTROL_LSB 6 +#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040 +#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB) +#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK) +#define RF2G_RF2G1_SHORTLNA2_MSB 5 +#define RF2G_RF2G1_SHORTLNA2_LSB 5 +#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020 +#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB) +#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK) +#define RF2G_RF2G1_SPARE_MSB 4 +#define RF2G_RF2G1_SPARE_LSB 0 +#define RF2G_RF2G1_SPARE_MASK 0x0000001f +#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB) +#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK) + +#define RF2G_RF2G2_ADDRESS 0x0000002c +#define RF2G_RF2G2_OFFSET 0x0000002c +#define RF2G_RF2G2_PDCGLNA_MSB 31 +#define RF2G_RF2G2_PDCGLNA_LSB 31 +#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000 +#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB) +#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK) +#define RF2G_RF2G2_PDCGLNABUF_MSB 30 +#define RF2G_RF2G2_PDCGLNABUF_LSB 30 +#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000 +#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB) +#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK) +#define RF2G_RF2G2_PDCSLNA_MSB 29 +#define RF2G_RF2G2_PDCSLNA_LSB 29 +#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000 +#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB) +#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK) +#define RF2G_RF2G2_PDDIV_MSB 28 +#define RF2G_RF2G2_PDDIV_LSB 28 +#define RF2G_RF2G2_PDDIV_MASK 0x10000000 +#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB) +#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK) +#define RF2G_RF2G2_PDPADRV_MSB 27 +#define RF2G_RF2G2_PDPADRV_LSB 27 +#define RF2G_RF2G2_PDPADRV_MASK 0x08000000 +#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB) +#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK) +#define RF2G_RF2G2_PDPAOUT_MSB 26 +#define RF2G_RF2G2_PDPAOUT_LSB 26 +#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000 +#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB) +#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK) +#define RF2G_RF2G2_PDREGLNA_MSB 25 +#define RF2G_RF2G2_PDREGLNA_LSB 25 +#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000 +#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB) +#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK) +#define RF2G_RF2G2_PDREGLO_MSB 24 +#define RF2G_RF2G2_PDREGLO_LSB 24 +#define RF2G_RF2G2_PDREGLO_MASK 0x01000000 +#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB) +#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK) +#define RF2G_RF2G2_PDRFGM_MSB 23 +#define RF2G_RF2G2_PDRFGM_LSB 23 +#define RF2G_RF2G2_PDRFGM_MASK 0x00800000 +#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB) +#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK) +#define RF2G_RF2G2_PDRXLO_MSB 22 +#define RF2G_RF2G2_PDRXLO_LSB 22 +#define RF2G_RF2G2_PDRXLO_MASK 0x00400000 +#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB) +#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK) +#define RF2G_RF2G2_PDTXLO_MSB 21 +#define RF2G_RF2G2_PDTXLO_LSB 21 +#define RF2G_RF2G2_PDTXLO_MASK 0x00200000 +#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB) +#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK) +#define RF2G_RF2G2_PDTXMIX_MSB 20 +#define RF2G_RF2G2_PDTXMIX_LSB 20 +#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000 +#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB) +#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK) +#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19 +#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000 +#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB) +#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK) +#define RF2G_RF2G2_REGLO_BYPASS_MSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_LSB 18 +#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000 +#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB) +#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK) +#define RF2G_RF2G2_ENABLE_PCB_MSB 17 +#define RF2G_RF2G2_ENABLE_PCB_LSB 17 +#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000 +#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB) +#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK) +#define RF2G_RF2G2_SPARE_MSB 16 +#define RF2G_RF2G2_SPARE_LSB 0 +#define RF2G_RF2G2_SPARE_MASK 0x0001ffff +#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB) +#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK) + +#define TOP_GAIN_ADDRESS 0x00000030 +#define TOP_GAIN_OFFSET 0x00000030 +#define TOP_GAIN_TX6DBLOQGAIN_MSB 31 +#define TOP_GAIN_TX6DBLOQGAIN_LSB 30 +#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000 +#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB) +#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK) +#define TOP_GAIN_TX1DBLOQGAIN_MSB 29 +#define TOP_GAIN_TX1DBLOQGAIN_LSB 27 +#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000 +#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB) +#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK) +#define TOP_GAIN_TXV2IGAIN_MSB 26 +#define TOP_GAIN_TXV2IGAIN_LSB 25 +#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000 +#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB) +#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK) +#define TOP_GAIN_PABUF5GN_MSB 24 +#define TOP_GAIN_PABUF5GN_LSB 24 +#define TOP_GAIN_PABUF5GN_MASK 0x01000000 +#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB) +#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK) +#define TOP_GAIN_PADRVGN_MSB 23 +#define TOP_GAIN_PADRVGN_LSB 21 +#define TOP_GAIN_PADRVGN_MASK 0x00e00000 +#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB) +#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK) +#define TOP_GAIN_PAOUT2GN_MSB 20 +#define TOP_GAIN_PAOUT2GN_LSB 18 +#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000 +#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB) +#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK) +#define TOP_GAIN_LNAON_MSB 17 +#define TOP_GAIN_LNAON_LSB 17 +#define TOP_GAIN_LNAON_MASK 0x00020000 +#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB) +#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK) +#define TOP_GAIN_LNAGAIN_MSB 16 +#define TOP_GAIN_LNAGAIN_LSB 13 +#define TOP_GAIN_LNAGAIN_MASK 0x0001e000 +#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB) +#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK) +#define TOP_GAIN_RFVGA5GAIN_MSB 12 +#define TOP_GAIN_RFVGA5GAIN_LSB 11 +#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800 +#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB) +#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK) +#define TOP_GAIN_RFGMGN_MSB 10 +#define TOP_GAIN_RFGMGN_LSB 8 +#define TOP_GAIN_RFGMGN_MASK 0x00000700 +#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB) +#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK) +#define TOP_GAIN_RX6DBLOQGAIN_MSB 7 +#define TOP_GAIN_RX6DBLOQGAIN_LSB 6 +#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0 +#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB) +#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK) +#define TOP_GAIN_RX1DBLOQGAIN_MSB 5 +#define TOP_GAIN_RX1DBLOQGAIN_LSB 3 +#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038 +#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB) +#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK) +#define TOP_GAIN_RX6DBHIQGAIN_MSB 2 +#define TOP_GAIN_RX6DBHIQGAIN_LSB 1 +#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006 +#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB) +#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK) +#define TOP_GAIN_SPARE_MSB 0 +#define TOP_GAIN_SPARE_LSB 0 +#define TOP_GAIN_SPARE_MASK 0x00000001 +#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB) +#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK) + +#define TOP_TOP_ADDRESS 0x00000034 +#define TOP_TOP_OFFSET 0x00000034 +#define TOP_TOP_LOCALTXGAIN_MSB 31 +#define TOP_TOP_LOCALTXGAIN_LSB 31 +#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000 +#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB) +#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK) +#define TOP_TOP_LOCALRXGAIN_MSB 30 +#define TOP_TOP_LOCALRXGAIN_LSB 30 +#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000 +#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB) +#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK) +#define TOP_TOP_LOCALMODE_MSB 29 +#define TOP_TOP_LOCALMODE_LSB 29 +#define TOP_TOP_LOCALMODE_MASK 0x20000000 +#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB) +#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK) +#define TOP_TOP_CALFC_MSB 28 +#define TOP_TOP_CALFC_LSB 28 +#define TOP_TOP_CALFC_MASK 0x10000000 +#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB) +#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK) +#define TOP_TOP_CALDC_MSB 27 +#define TOP_TOP_CALDC_LSB 27 +#define TOP_TOP_CALDC_MASK 0x08000000 +#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB) +#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK) +#define TOP_TOP_CAL_RESIDUE_MSB 26 +#define TOP_TOP_CAL_RESIDUE_LSB 26 +#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000 +#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB) +#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK) +#define TOP_TOP_BMODE_MSB 25 +#define TOP_TOP_BMODE_LSB 25 +#define TOP_TOP_BMODE_MASK 0x02000000 +#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB) +#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK) +#define TOP_TOP_SYNTHON_MSB 24 +#define TOP_TOP_SYNTHON_LSB 24 +#define TOP_TOP_SYNTHON_MASK 0x01000000 +#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB) +#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK) +#define TOP_TOP_RXON_MSB 23 +#define TOP_TOP_RXON_LSB 23 +#define TOP_TOP_RXON_MASK 0x00800000 +#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB) +#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK) +#define TOP_TOP_TXON_MSB 22 +#define TOP_TOP_TXON_LSB 22 +#define TOP_TOP_TXON_MASK 0x00400000 +#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB) +#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK) +#define TOP_TOP_PAON_MSB 21 +#define TOP_TOP_PAON_LSB 21 +#define TOP_TOP_PAON_MASK 0x00200000 +#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB) +#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK) +#define TOP_TOP_CALTX_MSB 20 +#define TOP_TOP_CALTX_LSB 20 +#define TOP_TOP_CALTX_MASK 0x00100000 +#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB) +#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK) +#define TOP_TOP_LOCALADDAC_MSB 19 +#define TOP_TOP_LOCALADDAC_LSB 19 +#define TOP_TOP_LOCALADDAC_MASK 0x00080000 +#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB) +#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK) +#define TOP_TOP_PWDPLL_MSB 18 +#define TOP_TOP_PWDPLL_LSB 18 +#define TOP_TOP_PWDPLL_MASK 0x00040000 +#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB) +#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK) +#define TOP_TOP_PWDADC_MSB 17 +#define TOP_TOP_PWDADC_LSB 17 +#define TOP_TOP_PWDADC_MASK 0x00020000 +#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB) +#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK) +#define TOP_TOP_PWDDAC_MSB 16 +#define TOP_TOP_PWDDAC_LSB 16 +#define TOP_TOP_PWDDAC_MASK 0x00010000 +#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB) +#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK) +#define TOP_TOP_LOCALXTAL_MSB 15 +#define TOP_TOP_LOCALXTAL_LSB 15 +#define TOP_TOP_LOCALXTAL_MASK 0x00008000 +#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB) +#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK) +#define TOP_TOP_PWDCLKIN_MSB 14 +#define TOP_TOP_PWDCLKIN_LSB 14 +#define TOP_TOP_PWDCLKIN_MASK 0x00004000 +#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB) +#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK) +#define TOP_TOP_OSCON_MSB 13 +#define TOP_TOP_OSCON_LSB 13 +#define TOP_TOP_OSCON_MASK 0x00002000 +#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB) +#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK) +#define TOP_TOP_SCLKEN_FORCE_MSB 12 +#define TOP_TOP_SCLKEN_FORCE_LSB 12 +#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000 +#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB) +#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK) +#define TOP_TOP_SYNTHON_FORCE_MSB 11 +#define TOP_TOP_SYNTHON_FORCE_LSB 11 +#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800 +#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB) +#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK) +#define TOP_TOP_PDBIAS_MSB 10 +#define TOP_TOP_PDBIAS_LSB 10 +#define TOP_TOP_PDBIAS_MASK 0x00000400 +#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB) +#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK) +#define TOP_TOP_DATAOUTSEL_MSB 9 +#define TOP_TOP_DATAOUTSEL_LSB 8 +#define TOP_TOP_DATAOUTSEL_MASK 0x00000300 +#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB) +#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK) +#define TOP_TOP_REVID_MSB 7 +#define TOP_TOP_REVID_LSB 5 +#define TOP_TOP_REVID_MASK 0x000000e0 +#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB) +#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK) +#define TOP_TOP_INT2PAD_MSB 4 +#define TOP_TOP_INT2PAD_LSB 4 +#define TOP_TOP_INT2PAD_MASK 0x00000010 +#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB) +#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK) +#define TOP_TOP_INTH2PAD_MSB 3 +#define TOP_TOP_INTH2PAD_LSB 3 +#define TOP_TOP_INTH2PAD_MASK 0x00000008 +#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB) +#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK) +#define TOP_TOP_PAD2GND_MSB 2 +#define TOP_TOP_PAD2GND_LSB 2 +#define TOP_TOP_PAD2GND_MASK 0x00000004 +#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB) +#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK) +#define TOP_TOP_INT2GND_MSB 1 +#define TOP_TOP_INT2GND_LSB 1 +#define TOP_TOP_INT2GND_MASK 0x00000002 +#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB) +#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK) +#define TOP_TOP_FORCE_XPAON_MSB 0 +#define TOP_TOP_FORCE_XPAON_LSB 0 +#define TOP_TOP_FORCE_XPAON_MASK 0x00000001 +#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB) +#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK) + +#define BIAS_BIAS_SEL_ADDRESS 0x00000038 +#define BIAS_BIAS_SEL_OFFSET 0x00000038 +#define BIAS_BIAS_SEL_PADON_MSB 31 +#define BIAS_BIAS_SEL_PADON_LSB 31 +#define BIAS_BIAS_SEL_PADON_MASK 0x80000000 +#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB) +#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK) +#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30 +#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25 +#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000 +#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB) +#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK) +#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24 +#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21 +#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000 +#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_SPARE_MSB 20 +#define BIAS_BIAS_SEL_SPARE_LSB 20 +#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000 +#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB) +#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000 +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000 +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000 +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) +#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000 +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000 +#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00 +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380 +#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) +#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070 +#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1 +#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e +#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) +#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) +#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0 +#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001 +#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB) +#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) + +#define BIAS_BIAS1_ADDRESS 0x0000003c +#define BIAS_BIAS1_OFFSET 0x0000003c +#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31 +#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29 +#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000 +#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB) +#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) +#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28 +#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26 +#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000 +#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB) +#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) +#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25 +#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23 +#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000 +#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB) +#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) +#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22 +#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20 +#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000 +#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000 +#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) +#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16 +#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000 +#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) +#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15 +#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000 +#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB) +#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) +#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14 +#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000 +#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB) +#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13 +#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11 +#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800 +#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700 +#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) +#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) +#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7 +#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5 +#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0 +#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB) +#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2 +#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c +#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) +#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) +#define BIAS_BIAS1_SPARE_MSB 1 +#define BIAS_BIAS1_SPARE_LSB 0 +#define BIAS_BIAS1_SPARE_MASK 0x00000003 +#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB) +#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK) + +#define BIAS_BIAS2_ADDRESS 0x00000040 +#define BIAS_BIAS2_OFFSET 0x00000040 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31 +#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29 +#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000 +#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB) +#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) +#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28 +#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26 +#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000 +#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB) +#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) +#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25 +#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23 +#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000 +#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IRPLL25_MSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_LSB 22 +#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000 +#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB) +#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK) +#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21 +#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19 +#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000 +#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB) +#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK) +#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18 +#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16 +#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000 +#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB) +#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK) +#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15 +#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13 +#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000 +#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB) +#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK) +#define BIAS_BIAS2_PWD_IRLDO25_MSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_LSB 12 +#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000 +#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB) +#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00 +#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) +#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) +#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8 +#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6 +#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0 +#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038 +#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) +#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007 +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) +#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) + +#define BIAS_BIAS3_ADDRESS 0x00000044 +#define BIAS_BIAS3_OFFSET 0x00000044 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000 +#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) +#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) +#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28 +#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26 +#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000 +#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB) +#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) +#define BIAS_BIAS3_PWD_ICDAC50_MSB 25 +#define BIAS_BIAS3_PWD_ICDAC50_LSB 23 +#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000 +#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB) +#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK) +#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22 +#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000 +#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB) +#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) +#define BIAS_BIAS3_PWD_ICBB50_MSB 21 +#define BIAS_BIAS3_PWD_ICBB50_LSB 21 +#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000 +#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB) +#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK) +#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20 +#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18 +#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000 +#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB) +#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) +#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17 +#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000 +#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB) +#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) +#define BIAS_BIAS3_PWD_IRBB50_MSB 16 +#define BIAS_BIAS3_PWD_IRBB50_LSB 16 +#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000 +#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB) +#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15 +#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13 +#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000 +#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12 +#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10 +#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00 +#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9 +#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7 +#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380 +#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) +#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6 +#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4 +#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070 +#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB) +#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) +#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3 +#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1 +#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e +#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB) +#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) +#define BIAS_BIAS3_SPARE_MSB 0 +#define BIAS_BIAS3_SPARE_LSB 0 +#define BIAS_BIAS3_SPARE_MASK 0x00000001 +#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB) +#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK) + +#define TXPC_TXPC_ADDRESS 0x00000048 +#define TXPC_TXPC_OFFSET 0x00000048 +#define TXPC_TXPC_SELINTPD_MSB 31 +#define TXPC_TXPC_SELINTPD_LSB 31 +#define TXPC_TXPC_SELINTPD_MASK 0x80000000 +#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB) +#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK) +#define TXPC_TXPC_TEST_MSB 30 +#define TXPC_TXPC_TEST_LSB 30 +#define TXPC_TXPC_TEST_MASK 0x40000000 +#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB) +#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK) +#define TXPC_TXPC_TESTGAIN_MSB 29 +#define TXPC_TXPC_TESTGAIN_LSB 28 +#define TXPC_TXPC_TESTGAIN_MASK 0x30000000 +#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB) +#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK) +#define TXPC_TXPC_TESTDAC_MSB 27 +#define TXPC_TXPC_TESTDAC_LSB 22 +#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000 +#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB) +#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK) +#define TXPC_TXPC_TESTPWDPC_MSB 21 +#define TXPC_TXPC_TESTPWDPC_LSB 21 +#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000 +#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB) +#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK) +#define TXPC_TXPC_CURHALF_MSB 20 +#define TXPC_TXPC_CURHALF_LSB 20 +#define TXPC_TXPC_CURHALF_MASK 0x00100000 +#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB) +#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK) +#define TXPC_TXPC_NEGOUT_MSB 19 +#define TXPC_TXPC_NEGOUT_LSB 19 +#define TXPC_TXPC_NEGOUT_MASK 0x00080000 +#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB) +#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK) +#define TXPC_TXPC_CLKDELAY_MSB 18 +#define TXPC_TXPC_CLKDELAY_LSB 18 +#define TXPC_TXPC_CLKDELAY_MASK 0x00040000 +#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB) +#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK) +#define TXPC_TXPC_SELMODREF_MSB 17 +#define TXPC_TXPC_SELMODREF_LSB 17 +#define TXPC_TXPC_SELMODREF_MASK 0x00020000 +#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB) +#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK) +#define TXPC_TXPC_SELCMOUT_MSB 16 +#define TXPC_TXPC_SELCMOUT_LSB 16 +#define TXPC_TXPC_SELCMOUT_MASK 0x00010000 +#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB) +#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK) +#define TXPC_TXPC_TSMODE_MSB 15 +#define TXPC_TXPC_TSMODE_LSB 14 +#define TXPC_TXPC_TSMODE_MASK 0x0000c000 +#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB) +#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK) +#define TXPC_TXPC_N_MSB 13 +#define TXPC_TXPC_N_LSB 6 +#define TXPC_TXPC_N_MASK 0x00003fc0 +#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB) +#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK) +#define TXPC_TXPC_ON1STSYNTHON_MSB 5 +#define TXPC_TXPC_ON1STSYNTHON_LSB 5 +#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020 +#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB) +#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK) +#define TXPC_TXPC_SELINIT_MSB 4 +#define TXPC_TXPC_SELINIT_LSB 3 +#define TXPC_TXPC_SELINIT_MASK 0x00000018 +#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB) +#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK) +#define TXPC_TXPC_SELCOUNT_MSB 2 +#define TXPC_TXPC_SELCOUNT_LSB 2 +#define TXPC_TXPC_SELCOUNT_MASK 0x00000004 +#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB) +#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK) +#define TXPC_TXPC_ATBSEL_MSB 1 +#define TXPC_TXPC_ATBSEL_LSB 0 +#define TXPC_TXPC_ATBSEL_MASK 0x00000003 +#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB) +#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK) + +#define TXPC_MISC_ADDRESS 0x0000004c +#define TXPC_MISC_OFFSET 0x0000004c +#define TXPC_MISC_FLIPBMODE_MSB 31 +#define TXPC_MISC_FLIPBMODE_LSB 31 +#define TXPC_MISC_FLIPBMODE_MASK 0x80000000 +#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB) +#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK) +#define TXPC_MISC_LEVEL_MSB 30 +#define TXPC_MISC_LEVEL_LSB 29 +#define TXPC_MISC_LEVEL_MASK 0x60000000 +#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB) +#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK) +#define TXPC_MISC_LDO_TEST_MODE_MSB 28 +#define TXPC_MISC_LDO_TEST_MODE_LSB 28 +#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000 +#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB) +#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK) +#define TXPC_MISC_NOTCXODET_MSB 27 +#define TXPC_MISC_NOTCXODET_LSB 27 +#define TXPC_MISC_NOTCXODET_MASK 0x08000000 +#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB) +#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK) +#define TXPC_MISC_PWDCLKIND_MSB 26 +#define TXPC_MISC_PWDCLKIND_LSB 26 +#define TXPC_MISC_PWDCLKIND_MASK 0x04000000 +#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB) +#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK) +#define TXPC_MISC_PWDXINPAD_MSB 25 +#define TXPC_MISC_PWDXINPAD_LSB 25 +#define TXPC_MISC_PWDXINPAD_MASK 0x02000000 +#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB) +#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK) +#define TXPC_MISC_LOCALBIAS_MSB 24 +#define TXPC_MISC_LOCALBIAS_LSB 24 +#define TXPC_MISC_LOCALBIAS_MASK 0x01000000 +#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB) +#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK) +#define TXPC_MISC_LOCALBIAS2X_MSB 23 +#define TXPC_MISC_LOCALBIAS2X_LSB 23 +#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000 +#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB) +#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK) +#define TXPC_MISC_SELTSP_MSB 22 +#define TXPC_MISC_SELTSP_LSB 22 +#define TXPC_MISC_SELTSP_MASK 0x00400000 +#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB) +#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK) +#define TXPC_MISC_SELTSN_MSB 21 +#define TXPC_MISC_SELTSN_LSB 21 +#define TXPC_MISC_SELTSN_MASK 0x00200000 +#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB) +#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK) +#define TXPC_MISC_SPARE_A_MSB 20 +#define TXPC_MISC_SPARE_A_LSB 18 +#define TXPC_MISC_SPARE_A_MASK 0x001c0000 +#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB) +#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK) +#define TXPC_MISC_DECOUT_MSB 17 +#define TXPC_MISC_DECOUT_LSB 8 +#define TXPC_MISC_DECOUT_MASK 0x0003ff00 +#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB) +#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK) +#define TXPC_MISC_XTALDIV_MSB 7 +#define TXPC_MISC_XTALDIV_LSB 6 +#define TXPC_MISC_XTALDIV_MASK 0x000000c0 +#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB) +#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK) +#define TXPC_MISC_SPARE_MSB 5 +#define TXPC_MISC_SPARE_LSB 0 +#define TXPC_MISC_SPARE_MASK 0x0000003f +#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB) +#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK) + +#define RXTXBB_RXTXBB1_ADDRESS 0x00000050 +#define RXTXBB_RXTXBB1_OFFSET 0x00000050 +#define RXTXBB_RXTXBB1_SPARE_MSB 31 +#define RXTXBB_RXTXBB1_SPARE_LSB 19 +#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000 +#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB) +#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK) +#define RXTXBB_RXTXBB1_FNOTCH_MSB 18 +#define RXTXBB_RXTXBB1_FNOTCH_LSB 17 +#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000 +#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB) +#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK) +#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16 +#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9 +#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00 +#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB) +#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100 +#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) +#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) +#define RXTXBB_RXTXBB1_PDV2I_MSB 7 +#define RXTXBB_RXTXBB1_PDV2I_LSB 7 +#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080 +#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB) +#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK) +#define RXTXBB_RXTXBB1_PDI2V_MSB 6 +#define RXTXBB_RXTXBB1_PDI2V_LSB 6 +#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040 +#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB) +#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK) +#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5 +#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020 +#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB) +#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010 +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008 +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004 +#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) +#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) +#define RXTXBB_RXTXBB1_PDLOQ_MSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_LSB 1 +#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002 +#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB) +#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK) +#define RXTXBB_RXTXBB1_PDHIQ_MSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_LSB 0 +#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001 +#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB) +#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK) + +#define RXTXBB_RXTXBB2_ADDRESS 0x00000054 +#define RXTXBB_RXTXBB2_OFFSET 0x00000054 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000 +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) +#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) +#define RXTXBB_RXTXBB2_SPARE_MSB 22 +#define RXTXBB_RXTXBB2_SPARE_LSB 21 +#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000 +#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB) +#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK) +#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20 +#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000 +#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB) +#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) +#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19 +#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000 +#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB) +#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000 +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000 +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000 +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000 +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) +#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) +#define RXTXBB_RXTXBB2_CMSEL_MSB 14 +#define RXTXBB_RXTXBB2_CMSEL_LSB 13 +#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000 +#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB) +#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK) +#define RXTXBB_RXTXBB2_FILTERFC_MSB 12 +#define RXTXBB_RXTXBB2_FILTERFC_LSB 8 +#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00 +#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB) +#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080 +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) +#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040 +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) +#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020 +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010 +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008 +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004 +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002 +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) +#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001 +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) +#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) + +#define RXTXBB_RXTXBB3_ADDRESS 0x00000058 +#define RXTXBB_RXTXBB3_OFFSET 0x00000058 +#define RXTXBB_RXTXBB3_SPARE_MSB 31 +#define RXTXBB_RXTXBB3_SPARE_LSB 27 +#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000 +#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB) +#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000 +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000 +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000 +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000 +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000 +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00 +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0 +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038 +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007 +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) +#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) + +#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c +#define RXTXBB_RXTXBB4_OFFSET 0x0000005c +#define RXTXBB_RXTXBB4_SPARE_MSB 31 +#define RXTXBB_RXTXBB4_SPARE_LSB 31 +#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000 +#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB) +#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK) +#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30 +#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000 +#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB) +#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29 +#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25 +#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000 +#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000 +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000 +#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00 +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0 +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) +#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) + +#define ADDAC_ADDAC1_ADDRESS 0x00000060 +#define ADDAC_ADDAC1_OFFSET 0x00000060 +#define ADDAC_ADDAC1_PLL_SVREG_MSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_LSB 31 +#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000 +#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB) +#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK) +#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30 +#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28 +#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000 +#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB) +#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) +#define ADDAC_ADDAC1_PLL_ATB_MSB 27 +#define ADDAC_ADDAC1_PLL_ATB_LSB 26 +#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000 +#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB) +#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK) +#define ADDAC_ADDAC1_PLL_ICP_MSB 25 +#define ADDAC_ADDAC1_PLL_ICP_LSB 23 +#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000 +#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB) +#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK) +#define ADDAC_ADDAC1_PLL_FILTER_MSB 22 +#define ADDAC_ADDAC1_PLL_FILTER_LSB 15 +#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000 +#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB) +#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK) +#define ADDAC_ADDAC1_PWDPLL_MSB 14 +#define ADDAC_ADDAC1_PWDPLL_LSB 14 +#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000 +#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB) +#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK) +#define ADDAC_ADDAC1_PWDADC_MSB 13 +#define ADDAC_ADDAC1_PWDADC_LSB 13 +#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000 +#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB) +#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK) +#define ADDAC_ADDAC1_PWDDAC_MSB 12 +#define ADDAC_ADDAC1_PWDDAC_LSB 12 +#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000 +#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB) +#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK) +#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11 +#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800 +#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB) +#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) +#define ADDAC_ADDAC1_SELMANPWDS_MSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_LSB 10 +#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400 +#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB) +#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK) +#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9 +#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200 +#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB) +#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) +#define ADDAC_ADDAC1_CM_SEL_MSB 8 +#define ADDAC_ADDAC1_CM_SEL_LSB 7 +#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180 +#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB) +#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040 +#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) +#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) +#define ADDAC_ADDAC1_SPARE_MSB 5 +#define ADDAC_ADDAC1_SPARE_LSB 0 +#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f +#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB) +#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_reg_reg_s { + volatile unsigned int synth_synth1; + volatile unsigned int synth_synth2; + volatile unsigned int synth_synth3; + volatile unsigned int synth_synth4; + volatile unsigned int synth_synth5; + volatile unsigned int synth_synth6; + volatile unsigned int synth_synth7; + volatile unsigned int synth_synth8; + volatile unsigned int rf5g_rf5g1; + volatile unsigned int rf5g_rf5g2; + volatile unsigned int rf2g_rf2g1; + volatile unsigned int rf2g_rf2g2; + volatile unsigned int top_gain; + volatile unsigned int top_top; + volatile unsigned int bias_bias_sel; + volatile unsigned int bias_bias1; + volatile unsigned int bias_bias2; + volatile unsigned int bias_bias3; + volatile unsigned int txpc_txpc; + volatile unsigned int txpc_misc; + volatile unsigned int rxtxbb_rxtxbb1; + volatile unsigned int rxtxbb_rxtxbb2; + volatile unsigned int rxtxbb_rxtxbb3; + volatile unsigned int rxtxbb_rxtxbb4; + volatile unsigned int addac_addac1; +} analog_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h new file mode 100644 index 000000000000..bba885ed1f08 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/apb_map.h @@ -0,0 +1,32 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _APB_MAP_H_ +#define _APB_MAP_H_ + +#define RTC_BASE_ADDRESS 0x00004000 +#define VMC_BASE_ADDRESS 0x00008000 +#define UART_BASE_ADDRESS 0x0000c000 +#define SI_BASE_ADDRESS 0x00010000 +#define GPIO_BASE_ADDRESS 0x00014000 +#define MBOX_BASE_ADDRESS 0x00018000 +#define ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define MAC_BASE_ADDRESS 0x00020000 + +#endif /* _APB_MAP_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h new file mode 100644 index 000000000000..de88e8cc91bb --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/gpio_reg.h @@ -0,0 +1,996 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _GPIO_REG_REG_H_ +#define _GPIO_REG_REG_H_ + +#define GPIO_OUT_ADDRESS 0x00000000 +#define GPIO_OUT_OFFSET 0x00000000 +#define GPIO_OUT_DATA_MSB 17 +#define GPIO_OUT_DATA_LSB 0 +#define GPIO_OUT_DATA_MASK 0x0003ffff +#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB) +#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK) + +#define GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define GPIO_OUT_W1TS_OFFSET 0x00000004 +#define GPIO_OUT_W1TS_DATA_MSB 17 +#define GPIO_OUT_W1TS_DATA_LSB 0 +#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB) +#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK) + +#define GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define GPIO_OUT_W1TC_OFFSET 0x00000008 +#define GPIO_OUT_W1TC_DATA_MSB 17 +#define GPIO_OUT_W1TC_DATA_LSB 0 +#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff +#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB) +#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK) + +#define GPIO_ENABLE_ADDRESS 0x0000000c +#define GPIO_ENABLE_OFFSET 0x0000000c +#define GPIO_ENABLE_DATA_MSB 17 +#define GPIO_ENABLE_DATA_LSB 0 +#define GPIO_ENABLE_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB) +#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK) + +#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define GPIO_ENABLE_W1TS_DATA_MSB 17 +#define GPIO_ENABLE_W1TS_DATA_LSB 0 +#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB) +#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK) + +#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define GPIO_ENABLE_W1TC_DATA_MSB 17 +#define GPIO_ENABLE_W1TC_DATA_LSB 0 +#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff +#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB) +#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK) + +#define GPIO_IN_ADDRESS 0x00000018 +#define GPIO_IN_OFFSET 0x00000018 +#define GPIO_IN_DATA_MSB 17 +#define GPIO_IN_DATA_LSB 0 +#define GPIO_IN_DATA_MASK 0x0003ffff +#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB) +#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK) + +#define GPIO_STATUS_ADDRESS 0x0000001c +#define GPIO_STATUS_OFFSET 0x0000001c +#define GPIO_STATUS_INTERRUPT_MSB 17 +#define GPIO_STATUS_INTERRUPT_LSB 0 +#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB) +#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17 +#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define GPIO_PIN0_ADDRESS 0x00000028 +#define GPIO_PIN0_OFFSET 0x00000028 +#define GPIO_PIN0_CONFIG_MSB 12 +#define GPIO_PIN0_CONFIG_LSB 11 +#define GPIO_PIN0_CONFIG_MASK 0x00001800 +#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB) +#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define GPIO_PIN0_INT_TYPE_MSB 9 +#define GPIO_PIN0_INT_TYPE_LSB 7 +#define GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB) +#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK) +#define GPIO_PIN0_PAD_DRIVER_MSB 2 +#define GPIO_PIN0_PAD_DRIVER_LSB 2 +#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB) +#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK) +#define GPIO_PIN0_SOURCE_MSB 0 +#define GPIO_PIN0_SOURCE_LSB 0 +#define GPIO_PIN0_SOURCE_MASK 0x00000001 +#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB) +#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK) + +#define GPIO_PIN1_ADDRESS 0x0000002c +#define GPIO_PIN1_OFFSET 0x0000002c +#define GPIO_PIN1_CONFIG_MSB 12 +#define GPIO_PIN1_CONFIG_LSB 11 +#define GPIO_PIN1_CONFIG_MASK 0x00001800 +#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB) +#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define GPIO_PIN1_INT_TYPE_MSB 9 +#define GPIO_PIN1_INT_TYPE_LSB 7 +#define GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB) +#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK) +#define GPIO_PIN1_PAD_DRIVER_MSB 2 +#define GPIO_PIN1_PAD_DRIVER_LSB 2 +#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB) +#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK) +#define GPIO_PIN1_SOURCE_MSB 0 +#define GPIO_PIN1_SOURCE_LSB 0 +#define GPIO_PIN1_SOURCE_MASK 0x00000001 +#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB) +#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK) + +#define GPIO_PIN2_ADDRESS 0x00000030 +#define GPIO_PIN2_OFFSET 0x00000030 +#define GPIO_PIN2_CONFIG_MSB 12 +#define GPIO_PIN2_CONFIG_LSB 11 +#define GPIO_PIN2_CONFIG_MASK 0x00001800 +#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB) +#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define GPIO_PIN2_INT_TYPE_MSB 9 +#define GPIO_PIN2_INT_TYPE_LSB 7 +#define GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB) +#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK) +#define GPIO_PIN2_PAD_DRIVER_MSB 2 +#define GPIO_PIN2_PAD_DRIVER_LSB 2 +#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB) +#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK) +#define GPIO_PIN2_SOURCE_MSB 0 +#define GPIO_PIN2_SOURCE_LSB 0 +#define GPIO_PIN2_SOURCE_MASK 0x00000001 +#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB) +#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK) + +#define GPIO_PIN3_ADDRESS 0x00000034 +#define GPIO_PIN3_OFFSET 0x00000034 +#define GPIO_PIN3_CONFIG_MSB 12 +#define GPIO_PIN3_CONFIG_LSB 11 +#define GPIO_PIN3_CONFIG_MASK 0x00001800 +#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB) +#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define GPIO_PIN3_INT_TYPE_MSB 9 +#define GPIO_PIN3_INT_TYPE_LSB 7 +#define GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB) +#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK) +#define GPIO_PIN3_PAD_DRIVER_MSB 2 +#define GPIO_PIN3_PAD_DRIVER_LSB 2 +#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB) +#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK) +#define GPIO_PIN3_SOURCE_MSB 0 +#define GPIO_PIN3_SOURCE_LSB 0 +#define GPIO_PIN3_SOURCE_MASK 0x00000001 +#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB) +#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK) + +#define GPIO_PIN4_ADDRESS 0x00000038 +#define GPIO_PIN4_OFFSET 0x00000038 +#define GPIO_PIN4_CONFIG_MSB 12 +#define GPIO_PIN4_CONFIG_LSB 11 +#define GPIO_PIN4_CONFIG_MASK 0x00001800 +#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB) +#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define GPIO_PIN4_INT_TYPE_MSB 9 +#define GPIO_PIN4_INT_TYPE_LSB 7 +#define GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB) +#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK) +#define GPIO_PIN4_PAD_DRIVER_MSB 2 +#define GPIO_PIN4_PAD_DRIVER_LSB 2 +#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB) +#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK) +#define GPIO_PIN4_SOURCE_MSB 0 +#define GPIO_PIN4_SOURCE_LSB 0 +#define GPIO_PIN4_SOURCE_MASK 0x00000001 +#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB) +#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK) + +#define GPIO_PIN5_ADDRESS 0x0000003c +#define GPIO_PIN5_OFFSET 0x0000003c +#define GPIO_PIN5_CONFIG_MSB 12 +#define GPIO_PIN5_CONFIG_LSB 11 +#define GPIO_PIN5_CONFIG_MASK 0x00001800 +#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB) +#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define GPIO_PIN5_INT_TYPE_MSB 9 +#define GPIO_PIN5_INT_TYPE_LSB 7 +#define GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB) +#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK) +#define GPIO_PIN5_PAD_DRIVER_MSB 2 +#define GPIO_PIN5_PAD_DRIVER_LSB 2 +#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB) +#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK) +#define GPIO_PIN5_SOURCE_MSB 0 +#define GPIO_PIN5_SOURCE_LSB 0 +#define GPIO_PIN5_SOURCE_MASK 0x00000001 +#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB) +#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK) + +#define GPIO_PIN6_ADDRESS 0x00000040 +#define GPIO_PIN6_OFFSET 0x00000040 +#define GPIO_PIN6_CONFIG_MSB 12 +#define GPIO_PIN6_CONFIG_LSB 11 +#define GPIO_PIN6_CONFIG_MASK 0x00001800 +#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB) +#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define GPIO_PIN6_INT_TYPE_MSB 9 +#define GPIO_PIN6_INT_TYPE_LSB 7 +#define GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB) +#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK) +#define GPIO_PIN6_PAD_DRIVER_MSB 2 +#define GPIO_PIN6_PAD_DRIVER_LSB 2 +#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB) +#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK) +#define GPIO_PIN6_SOURCE_MSB 0 +#define GPIO_PIN6_SOURCE_LSB 0 +#define GPIO_PIN6_SOURCE_MASK 0x00000001 +#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB) +#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK) + +#define GPIO_PIN7_ADDRESS 0x00000044 +#define GPIO_PIN7_OFFSET 0x00000044 +#define GPIO_PIN7_CONFIG_MSB 12 +#define GPIO_PIN7_CONFIG_LSB 11 +#define GPIO_PIN7_CONFIG_MASK 0x00001800 +#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB) +#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define GPIO_PIN7_INT_TYPE_MSB 9 +#define GPIO_PIN7_INT_TYPE_LSB 7 +#define GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB) +#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK) +#define GPIO_PIN7_PAD_DRIVER_MSB 2 +#define GPIO_PIN7_PAD_DRIVER_LSB 2 +#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB) +#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK) +#define GPIO_PIN7_SOURCE_MSB 0 +#define GPIO_PIN7_SOURCE_LSB 0 +#define GPIO_PIN7_SOURCE_MASK 0x00000001 +#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB) +#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK) + +#define GPIO_PIN8_ADDRESS 0x00000048 +#define GPIO_PIN8_OFFSET 0x00000048 +#define GPIO_PIN8_CONFIG_MSB 12 +#define GPIO_PIN8_CONFIG_LSB 11 +#define GPIO_PIN8_CONFIG_MASK 0x00001800 +#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB) +#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define GPIO_PIN8_INT_TYPE_MSB 9 +#define GPIO_PIN8_INT_TYPE_LSB 7 +#define GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB) +#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK) +#define GPIO_PIN8_PAD_DRIVER_MSB 2 +#define GPIO_PIN8_PAD_DRIVER_LSB 2 +#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB) +#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK) +#define GPIO_PIN8_SOURCE_MSB 0 +#define GPIO_PIN8_SOURCE_LSB 0 +#define GPIO_PIN8_SOURCE_MASK 0x00000001 +#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB) +#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK) + +#define GPIO_PIN9_ADDRESS 0x0000004c +#define GPIO_PIN9_OFFSET 0x0000004c +#define GPIO_PIN9_CONFIG_MSB 12 +#define GPIO_PIN9_CONFIG_LSB 11 +#define GPIO_PIN9_CONFIG_MASK 0x00001800 +#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB) +#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define GPIO_PIN9_INT_TYPE_MSB 9 +#define GPIO_PIN9_INT_TYPE_LSB 7 +#define GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB) +#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK) +#define GPIO_PIN9_PAD_DRIVER_MSB 2 +#define GPIO_PIN9_PAD_DRIVER_LSB 2 +#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB) +#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK) +#define GPIO_PIN9_SOURCE_MSB 0 +#define GPIO_PIN9_SOURCE_LSB 0 +#define GPIO_PIN9_SOURCE_MASK 0x00000001 +#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB) +#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK) + +#define GPIO_PIN10_ADDRESS 0x00000050 +#define GPIO_PIN10_OFFSET 0x00000050 +#define GPIO_PIN10_CONFIG_MSB 12 +#define GPIO_PIN10_CONFIG_LSB 11 +#define GPIO_PIN10_CONFIG_MASK 0x00001800 +#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB) +#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define GPIO_PIN10_INT_TYPE_MSB 9 +#define GPIO_PIN10_INT_TYPE_LSB 7 +#define GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB) +#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK) +#define GPIO_PIN10_PAD_DRIVER_MSB 2 +#define GPIO_PIN10_PAD_DRIVER_LSB 2 +#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB) +#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK) +#define GPIO_PIN10_SOURCE_MSB 0 +#define GPIO_PIN10_SOURCE_LSB 0 +#define GPIO_PIN10_SOURCE_MASK 0x00000001 +#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB) +#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK) + +#define GPIO_PIN11_ADDRESS 0x00000054 +#define GPIO_PIN11_OFFSET 0x00000054 +#define GPIO_PIN11_CONFIG_MSB 12 +#define GPIO_PIN11_CONFIG_LSB 11 +#define GPIO_PIN11_CONFIG_MASK 0x00001800 +#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB) +#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define GPIO_PIN11_INT_TYPE_MSB 9 +#define GPIO_PIN11_INT_TYPE_LSB 7 +#define GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB) +#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK) +#define GPIO_PIN11_PAD_DRIVER_MSB 2 +#define GPIO_PIN11_PAD_DRIVER_LSB 2 +#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB) +#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK) +#define GPIO_PIN11_SOURCE_MSB 0 +#define GPIO_PIN11_SOURCE_LSB 0 +#define GPIO_PIN11_SOURCE_MASK 0x00000001 +#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB) +#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK) + +#define GPIO_PIN12_ADDRESS 0x00000058 +#define GPIO_PIN12_OFFSET 0x00000058 +#define GPIO_PIN12_CONFIG_MSB 12 +#define GPIO_PIN12_CONFIG_LSB 11 +#define GPIO_PIN12_CONFIG_MASK 0x00001800 +#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB) +#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define GPIO_PIN12_INT_TYPE_MSB 9 +#define GPIO_PIN12_INT_TYPE_LSB 7 +#define GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB) +#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK) +#define GPIO_PIN12_PAD_DRIVER_MSB 2 +#define GPIO_PIN12_PAD_DRIVER_LSB 2 +#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB) +#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK) +#define GPIO_PIN12_SOURCE_MSB 0 +#define GPIO_PIN12_SOURCE_LSB 0 +#define GPIO_PIN12_SOURCE_MASK 0x00000001 +#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB) +#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK) + +#define GPIO_PIN13_ADDRESS 0x0000005c +#define GPIO_PIN13_OFFSET 0x0000005c +#define GPIO_PIN13_CONFIG_MSB 12 +#define GPIO_PIN13_CONFIG_LSB 11 +#define GPIO_PIN13_CONFIG_MASK 0x00001800 +#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB) +#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define GPIO_PIN13_INT_TYPE_MSB 9 +#define GPIO_PIN13_INT_TYPE_LSB 7 +#define GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB) +#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK) +#define GPIO_PIN13_PAD_DRIVER_MSB 2 +#define GPIO_PIN13_PAD_DRIVER_LSB 2 +#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB) +#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK) +#define GPIO_PIN13_SOURCE_MSB 0 +#define GPIO_PIN13_SOURCE_LSB 0 +#define GPIO_PIN13_SOURCE_MASK 0x00000001 +#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB) +#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK) + +#define GPIO_PIN14_ADDRESS 0x00000060 +#define GPIO_PIN14_OFFSET 0x00000060 +#define GPIO_PIN14_CONFIG_MSB 12 +#define GPIO_PIN14_CONFIG_LSB 11 +#define GPIO_PIN14_CONFIG_MASK 0x00001800 +#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB) +#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define GPIO_PIN14_INT_TYPE_MSB 9 +#define GPIO_PIN14_INT_TYPE_LSB 7 +#define GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB) +#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK) +#define GPIO_PIN14_PAD_DRIVER_MSB 2 +#define GPIO_PIN14_PAD_DRIVER_LSB 2 +#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB) +#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK) +#define GPIO_PIN14_SOURCE_MSB 0 +#define GPIO_PIN14_SOURCE_LSB 0 +#define GPIO_PIN14_SOURCE_MASK 0x00000001 +#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB) +#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK) + +#define GPIO_PIN15_ADDRESS 0x00000064 +#define GPIO_PIN15_OFFSET 0x00000064 +#define GPIO_PIN15_CONFIG_MSB 12 +#define GPIO_PIN15_CONFIG_LSB 11 +#define GPIO_PIN15_CONFIG_MASK 0x00001800 +#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB) +#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define GPIO_PIN15_INT_TYPE_MSB 9 +#define GPIO_PIN15_INT_TYPE_LSB 7 +#define GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB) +#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK) +#define GPIO_PIN15_PAD_DRIVER_MSB 2 +#define GPIO_PIN15_PAD_DRIVER_LSB 2 +#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB) +#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK) +#define GPIO_PIN15_SOURCE_MSB 0 +#define GPIO_PIN15_SOURCE_LSB 0 +#define GPIO_PIN15_SOURCE_MASK 0x00000001 +#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB) +#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK) + +#define GPIO_PIN16_ADDRESS 0x00000068 +#define GPIO_PIN16_OFFSET 0x00000068 +#define GPIO_PIN16_CONFIG_MSB 12 +#define GPIO_PIN16_CONFIG_LSB 11 +#define GPIO_PIN16_CONFIG_MASK 0x00001800 +#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB) +#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define GPIO_PIN16_INT_TYPE_MSB 9 +#define GPIO_PIN16_INT_TYPE_LSB 7 +#define GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB) +#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK) +#define GPIO_PIN16_PAD_DRIVER_MSB 2 +#define GPIO_PIN16_PAD_DRIVER_LSB 2 +#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB) +#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK) +#define GPIO_PIN16_SOURCE_MSB 0 +#define GPIO_PIN16_SOURCE_LSB 0 +#define GPIO_PIN16_SOURCE_MASK 0x00000001 +#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB) +#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK) + +#define GPIO_PIN17_ADDRESS 0x0000006c +#define GPIO_PIN17_OFFSET 0x0000006c +#define GPIO_PIN17_CONFIG_MSB 12 +#define GPIO_PIN17_CONFIG_LSB 11 +#define GPIO_PIN17_CONFIG_MASK 0x00001800 +#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB) +#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define GPIO_PIN17_INT_TYPE_MSB 9 +#define GPIO_PIN17_INT_TYPE_LSB 7 +#define GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB) +#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK) +#define GPIO_PIN17_PAD_DRIVER_MSB 2 +#define GPIO_PIN17_PAD_DRIVER_LSB 2 +#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB) +#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK) +#define GPIO_PIN17_SOURCE_MSB 0 +#define GPIO_PIN17_SOURCE_LSB 0 +#define GPIO_PIN17_SOURCE_MASK 0x00000001 +#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB) +#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK) + +#define SDIO_PIN_ADDRESS 0x00000070 +#define SDIO_PIN_OFFSET 0x00000070 +#define SDIO_PIN_PAD_PULL_MSB 3 +#define SDIO_PIN_PAD_PULL_LSB 2 +#define SDIO_PIN_PAD_PULL_MASK 0x0000000c +#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB) +#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK) +#define SDIO_PIN_PAD_STRENGTH_MSB 1 +#define SDIO_PIN_PAD_STRENGTH_LSB 0 +#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB) +#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK) + +#define CLK_REQ_PIN_ADDRESS 0x00000074 +#define CLK_REQ_PIN_OFFSET 0x00000074 +#define CLK_REQ_PIN_ATE_OE_L_MSB 4 +#define CLK_REQ_PIN_ATE_OE_L_LSB 4 +#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010 +#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB) +#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK) +#define CLK_REQ_PIN_PAD_PULL_MSB 3 +#define CLK_REQ_PIN_PAD_PULL_LSB 2 +#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c +#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB) +#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK) +#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1 +#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0 +#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003 +#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB) +#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK) + +#define SIGMA_DELTA_ADDRESS 0x00000078 +#define SIGMA_DELTA_OFFSET 0x00000078 +#define SIGMA_DELTA_ENABLE_MSB 16 +#define SIGMA_DELTA_ENABLE_LSB 16 +#define SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB) +#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK) +#define SIGMA_DELTA_PRESCALAR_MSB 15 +#define SIGMA_DELTA_PRESCALAR_LSB 8 +#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB) +#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK) +#define SIGMA_DELTA_TARGET_MSB 7 +#define SIGMA_DELTA_TARGET_LSB 0 +#define SIGMA_DELTA_TARGET_MASK 0x000000ff +#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB) +#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK) + +#define DEBUG_CONTROL_ADDRESS 0x0000007c +#define DEBUG_CONTROL_OFFSET 0x0000007c +#define DEBUG_CONTROL_OBS_OE_L_MSB 1 +#define DEBUG_CONTROL_OBS_OE_L_LSB 1 +#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002 +#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB) +#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK) +#define DEBUG_CONTROL_ENABLE_MSB 0 +#define DEBUG_CONTROL_ENABLE_LSB 0 +#define DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB) +#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK) + +#define DEBUG_INPUT_SEL_ADDRESS 0x00000080 +#define DEBUG_INPUT_SEL_OFFSET 0x00000080 +#define DEBUG_INPUT_SEL_SRC_MSB 3 +#define DEBUG_INPUT_SEL_SRC_LSB 0 +#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB) +#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK) + +#define DEBUG_OUT_ADDRESS 0x00000084 +#define DEBUG_OUT_OFFSET 0x00000084 +#define DEBUG_OUT_DATA_MSB 17 +#define DEBUG_OUT_DATA_LSB 0 +#define DEBUG_OUT_DATA_MASK 0x0003ffff +#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB) +#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK) + +#define LA_CONTROL_ADDRESS 0x00000088 +#define LA_CONTROL_OFFSET 0x00000088 +#define LA_CONTROL_RUN_MSB 1 +#define LA_CONTROL_RUN_LSB 1 +#define LA_CONTROL_RUN_MASK 0x00000002 +#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB) +#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK) +#define LA_CONTROL_TRIGGERED_MSB 0 +#define LA_CONTROL_TRIGGERED_LSB 0 +#define LA_CONTROL_TRIGGERED_MASK 0x00000001 +#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB) +#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK) + +#define LA_CLOCK_ADDRESS 0x0000008c +#define LA_CLOCK_OFFSET 0x0000008c +#define LA_CLOCK_DIV_MSB 7 +#define LA_CLOCK_DIV_LSB 0 +#define LA_CLOCK_DIV_MASK 0x000000ff +#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB) +#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK) + +#define LA_STATUS_ADDRESS 0x00000090 +#define LA_STATUS_OFFSET 0x00000090 +#define LA_STATUS_INTERRUPT_MSB 0 +#define LA_STATUS_INTERRUPT_LSB 0 +#define LA_STATUS_INTERRUPT_MASK 0x00000001 +#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB) +#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK) + +#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094 +#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094 +#define LA_TRIGGER_SAMPLE_COUNT_MSB 15 +#define LA_TRIGGER_SAMPLE_COUNT_LSB 0 +#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff +#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB) +#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK) + +#define LA_TRIGGER_POSITION_ADDRESS 0x00000098 +#define LA_TRIGGER_POSITION_OFFSET 0x00000098 +#define LA_TRIGGER_POSITION_VALUE_MSB 15 +#define LA_TRIGGER_POSITION_VALUE_LSB 0 +#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff +#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB) +#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK) + +#define LA_PRE_TRIGGER_ADDRESS 0x0000009c +#define LA_PRE_TRIGGER_OFFSET 0x0000009c +#define LA_PRE_TRIGGER_COUNT_MSB 15 +#define LA_PRE_TRIGGER_COUNT_LSB 0 +#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB) +#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK) + +#define LA_POST_TRIGGER_ADDRESS 0x000000a0 +#define LA_POST_TRIGGER_OFFSET 0x000000a0 +#define LA_POST_TRIGGER_COUNT_MSB 15 +#define LA_POST_TRIGGER_COUNT_LSB 0 +#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff +#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB) +#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK) + +#define LA_FILTER_CONTROL_ADDRESS 0x000000a4 +#define LA_FILTER_CONTROL_OFFSET 0x000000a4 +#define LA_FILTER_CONTROL_DELTA_MSB 0 +#define LA_FILTER_CONTROL_DELTA_LSB 0 +#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001 +#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB) +#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK) + +#define LA_FILTER_DATA_ADDRESS 0x000000a8 +#define LA_FILTER_DATA_OFFSET 0x000000a8 +#define LA_FILTER_DATA_MATCH_MSB 17 +#define LA_FILTER_DATA_MATCH_LSB 0 +#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff +#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB) +#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK) + +#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac +#define LA_FILTER_WILDCARD_OFFSET 0x000000ac +#define LA_FILTER_WILDCARD_MATCH_MSB 17 +#define LA_FILTER_WILDCARD_MATCH_LSB 0 +#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB) +#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0 +#define LA_TRIGGERA_DATA_OFFSET 0x000000b0 +#define LA_TRIGGERA_DATA_MATCH_MSB 17 +#define LA_TRIGGERA_DATA_MATCH_LSB 0 +#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB) +#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK) + +#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4 +#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4 +#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB) +#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK) + +#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8 +#define LA_TRIGGERB_DATA_OFFSET 0x000000b8 +#define LA_TRIGGERB_DATA_MATCH_MSB 17 +#define LA_TRIGGERB_DATA_MATCH_LSB 0 +#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB) +#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK) + +#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc +#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc +#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17 +#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0 +#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff +#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB) +#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK) + +#define LA_TRIGGER_ADDRESS 0x000000c0 +#define LA_TRIGGER_OFFSET 0x000000c0 +#define LA_TRIGGER_EVENT_MSB 2 +#define LA_TRIGGER_EVENT_LSB 0 +#define LA_TRIGGER_EVENT_MASK 0x00000007 +#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB) +#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK) + +#define LA_FIFO_ADDRESS 0x000000c4 +#define LA_FIFO_OFFSET 0x000000c4 +#define LA_FIFO_FULL_MSB 1 +#define LA_FIFO_FULL_LSB 1 +#define LA_FIFO_FULL_MASK 0x00000002 +#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB) +#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK) +#define LA_FIFO_EMPTY_MSB 0 +#define LA_FIFO_EMPTY_LSB 0 +#define LA_FIFO_EMPTY_MASK 0x00000001 +#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB) +#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK) + +#define LA_ADDRESS 0x000000c8 +#define LA_OFFSET 0x000000c8 +#define LA_DATA_MSB 17 +#define LA_DATA_LSB 0 +#define LA_DATA_MASK 0x0003ffff +#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB) +#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK) + +#define ANT_PIN_ADDRESS 0x000000d0 +#define ANT_PIN_OFFSET 0x000000d0 +#define ANT_PIN_PAD_PULL_MSB 3 +#define ANT_PIN_PAD_PULL_LSB 2 +#define ANT_PIN_PAD_PULL_MASK 0x0000000c +#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB) +#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK) +#define ANT_PIN_PAD_STRENGTH_MSB 1 +#define ANT_PIN_PAD_STRENGTH_LSB 0 +#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB) +#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK) + +#define ANTD_PIN_ADDRESS 0x000000d4 +#define ANTD_PIN_OFFSET 0x000000d4 +#define ANTD_PIN_PAD_PULL_MSB 1 +#define ANTD_PIN_PAD_PULL_LSB 0 +#define ANTD_PIN_PAD_PULL_MASK 0x00000003 +#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB) +#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK) + +#define GPIO_PIN_ADDRESS 0x000000d8 +#define GPIO_PIN_OFFSET 0x000000d8 +#define GPIO_PIN_PAD_PULL_MSB 3 +#define GPIO_PIN_PAD_PULL_LSB 2 +#define GPIO_PIN_PAD_PULL_MASK 0x0000000c +#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB) +#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK) +#define GPIO_PIN_PAD_STRENGTH_MSB 1 +#define GPIO_PIN_PAD_STRENGTH_LSB 0 +#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003 +#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB) +#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK) + +#define GPIO_H_PIN_ADDRESS 0x000000dc +#define GPIO_H_PIN_OFFSET 0x000000dc +#define GPIO_H_PIN_PAD_PULL_MSB 1 +#define GPIO_H_PIN_PAD_PULL_LSB 0 +#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003 +#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB) +#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK) + +#define BT_PIN_ADDRESS 0x000000e0 +#define BT_PIN_OFFSET 0x000000e0 +#define BT_PIN_PAD_PULL_MSB 3 +#define BT_PIN_PAD_PULL_LSB 2 +#define BT_PIN_PAD_PULL_MASK 0x0000000c +#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB) +#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK) +#define BT_PIN_PAD_STRENGTH_MSB 1 +#define BT_PIN_PAD_STRENGTH_LSB 0 +#define BT_PIN_PAD_STRENGTH_MASK 0x00000003 +#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB) +#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK) + +#define BT_WLAN_PIN_ADDRESS 0x000000e4 +#define BT_WLAN_PIN_OFFSET 0x000000e4 +#define BT_WLAN_PIN_PAD_PULL_MSB 1 +#define BT_WLAN_PIN_PAD_PULL_LSB 0 +#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003 +#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB) +#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK) + +#define SI_UART_PIN_ADDRESS 0x000000e8 +#define SI_UART_PIN_OFFSET 0x000000e8 +#define SI_UART_PIN_PAD_PULL_MSB 3 +#define SI_UART_PIN_PAD_PULL_LSB 2 +#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c +#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB) +#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK) +#define SI_UART_PIN_PAD_STRENGTH_MSB 1 +#define SI_UART_PIN_PAD_STRENGTH_LSB 0 +#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003 +#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB) +#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK) + +#define CLK32K_PIN_ADDRESS 0x000000ec +#define CLK32K_PIN_OFFSET 0x000000ec +#define CLK32K_PIN_PAD_PULL_MSB 1 +#define CLK32K_PIN_PAD_PULL_LSB 0 +#define CLK32K_PIN_PAD_PULL_MASK 0x00000003 +#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB) +#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK) + +#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0 +#define RESET_TUPLE_STATUS_OFFSET 0x000000f0 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_reg_reg_s { + volatile unsigned int gpio_out; + volatile unsigned int gpio_out_w1ts; + volatile unsigned int gpio_out_w1tc; + volatile unsigned int gpio_enable; + volatile unsigned int gpio_enable_w1ts; + volatile unsigned int gpio_enable_w1tc; + volatile unsigned int gpio_in; + volatile unsigned int gpio_status; + volatile unsigned int gpio_status_w1ts; + volatile unsigned int gpio_status_w1tc; + volatile unsigned int gpio_pin0; + volatile unsigned int gpio_pin1; + volatile unsigned int gpio_pin2; + volatile unsigned int gpio_pin3; + volatile unsigned int gpio_pin4; + volatile unsigned int gpio_pin5; + volatile unsigned int gpio_pin6; + volatile unsigned int gpio_pin7; + volatile unsigned int gpio_pin8; + volatile unsigned int gpio_pin9; + volatile unsigned int gpio_pin10; + volatile unsigned int gpio_pin11; + volatile unsigned int gpio_pin12; + volatile unsigned int gpio_pin13; + volatile unsigned int gpio_pin14; + volatile unsigned int gpio_pin15; + volatile unsigned int gpio_pin16; + volatile unsigned int gpio_pin17; + volatile unsigned int sdio_pin; + volatile unsigned int clk_req_pin; + volatile unsigned int sigma_delta; + volatile unsigned int debug_control; + volatile unsigned int debug_input_sel; + volatile unsigned int debug_out; + volatile unsigned int la_control; + volatile unsigned int la_clock; + volatile unsigned int la_status; + volatile unsigned int la_trigger_sample; + volatile unsigned int la_trigger_position; + volatile unsigned int la_pre_trigger; + volatile unsigned int la_post_trigger; + volatile unsigned int la_filter_control; + volatile unsigned int la_filter_data; + volatile unsigned int la_filter_wildcard; + volatile unsigned int la_triggera_data; + volatile unsigned int la_triggera_wildcard; + volatile unsigned int la_triggerb_data; + volatile unsigned int la_triggerb_wildcard; + volatile unsigned int la_trigger; + volatile unsigned int la_fifo; + volatile unsigned int la[2]; + volatile unsigned int ant_pin; + volatile unsigned int antd_pin; + volatile unsigned int gpio_pin; + volatile unsigned int gpio_h_pin; + volatile unsigned int bt_pin; + volatile unsigned int bt_wlan_pin; + volatile unsigned int si_uart_pin; + volatile unsigned int clk32k_pin; + volatile unsigned int reset_tuple_status; +} gpio_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h new file mode 100644 index 000000000000..20ac2b5c8920 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_host_reg.h @@ -0,0 +1,405 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_HOST_REG_REG_H_ +#define _MBOX_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_DRAGON_INT_MSB 5 +#define HOST_INT_STATUS_DRAGON_INT_LSB 5 +#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020 +#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB) +#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5 +#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB) +#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define SPI_CONFIG_ADDRESS 0x00000480 +#define SPI_CONFIG_OFFSET 0x00000480 +#define SPI_CONFIG_SPI_RESET_MSB 4 +#define SPI_CONFIG_SPI_RESET_LSB 4 +#define SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB) +#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK) +#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define SPI_CONFIG_TEST_MODE_MSB 2 +#define SPI_CONFIG_TEST_MODE_LSB 2 +#define SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB) +#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK) +#define SPI_CONFIG_DATA_SIZE_MSB 1 +#define SPI_CONFIG_DATA_SIZE_LSB 0 +#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB) +#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK) + +#define SPI_STATUS_ADDRESS 0x00000481 +#define SPI_STATUS_OFFSET 0x00000481 +#define SPI_STATUS_ADDR_ERR_MSB 3 +#define SPI_STATUS_ADDR_ERR_LSB 3 +#define SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB) +#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK) +#define SPI_STATUS_RD_ERR_MSB 2 +#define SPI_STATUS_RD_ERR_LSB 2 +#define SPI_STATUS_RD_ERR_MASK 0x00000004 +#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB) +#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK) +#define SPI_STATUS_WR_ERR_MSB 1 +#define SPI_STATUS_WR_ERR_LSB 1 +#define SPI_STATUS_WR_ERR_MASK 0x00000002 +#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB) +#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK) +#define SPI_STATUS_READY_MSB 0 +#define SPI_STATUS_READY_LSB 0 +#define SPI_STATUS_READY_MASK 0x00000001 +#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB) +#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + unsigned char pad1[2]; /* pad to 0x408 */ + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad2[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad3[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad4[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad5[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad6[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char spi_config; + volatile unsigned char spi_status; + volatile unsigned char non_assoc_sleep_en; + unsigned char pad7[381]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_HOST_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h new file mode 100644 index 000000000000..d232764d5af6 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/mbox_reg.h @@ -0,0 +1,500 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_REG_REG_H_ +#define _MBOX_REG_REG_H_ + +#define MBOX_FIFO_ADDRESS 0x00000000 +#define MBOX_FIFO_OFFSET 0x00000000 +#define MBOX_FIFO_DATA_MSB 19 +#define MBOX_FIFO_DATA_LSB 0 +#define MBOX_FIFO_DATA_MASK 0x000fffff +#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB) +#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK) + +#define MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK) +#define MBOX_FIFO_STATUS_FULL_MSB 15 +#define MBOX_FIFO_STATUS_FULL_LSB 12 +#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB) +#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK) + +#define MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define MBOX_DMA_POLICY_OFFSET 0x00000014 +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define MBOX_INT_STATUS_ADDRESS 0x00000058 +#define MBOX_INT_STATUS_OFFSET 0x00000058 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define MBOX_INT_STATUS_HOST_MSB 7 +#define MBOX_INT_STATUS_HOST_LSB 0 +#define MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB) +#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK) + +#define MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define MBOX_INT_ENABLE_OFFSET 0x0000005c +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define MBOX_INT_ENABLE_HOST_MSB 7 +#define MBOX_INT_ENABLE_HOST_LSB 0 +#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB) +#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK) + +#define INT_HOST_ADDRESS 0x00000060 +#define INT_HOST_OFFSET 0x00000060 +#define INT_HOST_VECTOR_MSB 7 +#define INT_HOST_VECTOR_LSB 0 +#define INT_HOST_VECTOR_MASK 0x000000ff +#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB) +#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK) + +#define LOCAL_COUNT_ADDRESS 0x00000080 +#define LOCAL_COUNT_OFFSET 0x00000080 +#define LOCAL_COUNT_VALUE_MSB 7 +#define LOCAL_COUNT_VALUE_LSB 0 +#define LOCAL_COUNT_VALUE_MASK 0x000000ff +#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB) +#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK) + +#define COUNT_INC_ADDRESS 0x000000a0 +#define COUNT_INC_OFFSET 0x000000a0 +#define COUNT_INC_VALUE_MSB 7 +#define COUNT_INC_VALUE_LSB 0 +#define COUNT_INC_VALUE_MASK 0x000000ff +#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB) +#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK) + +#define LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define LOCAL_SCRATCH_OFFSET 0x000000c0 +#define LOCAL_SCRATCH_VALUE_MSB 7 +#define LOCAL_SCRATCH_VALUE_LSB 0 +#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB) +#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK) + +#define USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define USE_LOCAL_BUS_OFFSET 0x000000e0 +#define USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK) + +#define SDIO_CONFIG_ADDRESS 0x000000e4 +#define SDIO_CONFIG_OFFSET 0x000000e4 +#define SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK) + +#define MBOX_DEBUG_ADDRESS 0x000000e8 +#define MBOX_DEBUG_OFFSET 0x000000e8 +#define MBOX_DEBUG_SEL_MSB 2 +#define MBOX_DEBUG_SEL_LSB 0 +#define MBOX_DEBUG_SEL_MASK 0x00000007 +#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB) +#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK) + +#define MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define MBOX_FIFO_RESET_OFFSET 0x000000ec +#define MBOX_FIFO_RESET_INIT_MSB 0 +#define MBOX_FIFO_RESET_INIT_LSB 0 +#define MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB) +#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK) + +#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define MBOX_TXFIFO_POP_DATA_MSB 0 +#define MBOX_TXFIFO_POP_DATA_LSB 0 +#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB) +#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK) + +#define MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define MBOX_RXFIFO_POP_DATA_MSB 0 +#define MBOX_RXFIFO_POP_DATA_LSB 0 +#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB) +#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK) + +#define SDIO_DEBUG_ADDRESS 0x00000110 +#define SDIO_DEBUG_OFFSET 0x00000110 +#define SDIO_DEBUG_SEL_MSB 3 +#define SDIO_DEBUG_SEL_LSB 0 +#define SDIO_DEBUG_SEL_MASK 0x0000000f +#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB) +#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK) + +#define HOST_IF_WINDOW_ADDRESS 0x00002000 +#define HOST_IF_WINDOW_OFFSET 0x00002000 +#define HOST_IF_WINDOW_DATA_MSB 7 +#define HOST_IF_WINDOW_DATA_LSB 0 +#define HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB) +#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_reg_reg_s { + volatile unsigned int mbox_fifo[4]; + volatile unsigned int mbox_fifo_status; + volatile unsigned int mbox_dma_policy; + volatile unsigned int mbox0_dma_rx_descriptor_base; + volatile unsigned int mbox0_dma_rx_control; + volatile unsigned int mbox0_dma_tx_descriptor_base; + volatile unsigned int mbox0_dma_tx_control; + volatile unsigned int mbox1_dma_rx_descriptor_base; + volatile unsigned int mbox1_dma_rx_control; + volatile unsigned int mbox1_dma_tx_descriptor_base; + volatile unsigned int mbox1_dma_tx_control; + volatile unsigned int mbox2_dma_rx_descriptor_base; + volatile unsigned int mbox2_dma_rx_control; + volatile unsigned int mbox2_dma_tx_descriptor_base; + volatile unsigned int mbox2_dma_tx_control; + volatile unsigned int mbox3_dma_rx_descriptor_base; + volatile unsigned int mbox3_dma_rx_control; + volatile unsigned int mbox3_dma_tx_descriptor_base; + volatile unsigned int mbox3_dma_tx_control; + volatile unsigned int mbox_int_status; + volatile unsigned int mbox_int_enable; + volatile unsigned int int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int local_count[8]; + volatile unsigned int count_inc[8]; + volatile unsigned int local_scratch[8]; + volatile unsigned int use_local_bus; + volatile unsigned int sdio_config; + volatile unsigned int mbox_debug; + volatile unsigned int mbox_fifo_reset; + volatile unsigned int mbox_txfifo_pop[4]; + volatile unsigned int mbox_rxfifo_pop[4]; + volatile unsigned int sdio_debug; + unsigned char pad1[7916]; /* pad to 0x2000 */ + volatile unsigned int host_if_window[2048]; +} mbox_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h new file mode 100644 index 000000000000..cc2cb7350a78 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/rtc_reg.h @@ -0,0 +1,1182 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RTC_REG_REG_H_ +#define _RTC_REG_REG_H_ + +#define RESET_CONTROL_ADDRESS 0x00000000 +#define RESET_CONTROL_OFFSET 0x00000000 +#define RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define RESET_CONTROL_RST_OUT_MSB 9 +#define RESET_CONTROL_RST_OUT_LSB 9 +#define RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB) +#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK) +#define RESET_CONTROL_COLD_RST_MSB 8 +#define RESET_CONTROL_COLD_RST_LSB 8 +#define RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) +#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) +#define RESET_CONTROL_WARM_RST_MSB 7 +#define RESET_CONTROL_WARM_RST_LSB 7 +#define RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) +#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) +#define RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) +#define RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) +#define RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) +#define RESET_CONTROL_MBOX_RST_MSB 2 +#define RESET_CONTROL_MBOX_RST_LSB 2 +#define RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB) +#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK) +#define RESET_CONTROL_UART_RST_MSB 1 +#define RESET_CONTROL_UART_RST_LSB 1 +#define RESET_CONTROL_UART_RST_MASK 0x00000002 +#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB) +#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK) +#define RESET_CONTROL_SI0_RST_MSB 0 +#define RESET_CONTROL_SI0_RST_LSB 0 +#define RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB) +#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK) + +#define XTAL_CONTROL_ADDRESS 0x00000004 +#define XTAL_CONTROL_OFFSET 0x00000004 +#define XTAL_CONTROL_TCXO_MSB 0 +#define XTAL_CONTROL_TCXO_LSB 0 +#define XTAL_CONTROL_TCXO_MASK 0x00000001 +#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB) +#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK) + +#define TCXO_DETECT_ADDRESS 0x00000008 +#define TCXO_DETECT_OFFSET 0x00000008 +#define TCXO_DETECT_PRESENT_MSB 0 +#define TCXO_DETECT_PRESENT_LSB 0 +#define TCXO_DETECT_PRESENT_MASK 0x00000001 +#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB) +#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK) + +#define XTAL_TEST_ADDRESS 0x0000000c +#define XTAL_TEST_OFFSET 0x0000000c +#define XTAL_TEST_NOTCXODET_MSB 0 +#define XTAL_TEST_NOTCXODET_LSB 0 +#define XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB) +#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK) + +#define QUADRATURE_ADDRESS 0x00000010 +#define QUADRATURE_OFFSET 0x00000010 +#define QUADRATURE_ADC_MSB 5 +#define QUADRATURE_ADC_LSB 4 +#define QUADRATURE_ADC_MASK 0x00000030 +#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB) +#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK) +#define QUADRATURE_SEL_MSB 2 +#define QUADRATURE_SEL_LSB 2 +#define QUADRATURE_SEL_MASK 0x00000004 +#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB) +#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK) +#define QUADRATURE_DAC_MSB 1 +#define QUADRATURE_DAC_LSB 0 +#define QUADRATURE_DAC_MASK 0x00000003 +#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB) +#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK) + +#define PLL_CONTROL_ADDRESS 0x00000014 +#define PLL_CONTROL_OFFSET 0x00000014 +#define PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) +#define PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) +#define PLL_CONTROL_NOPWD_MSB 18 +#define PLL_CONTROL_NOPWD_LSB 18 +#define PLL_CONTROL_NOPWD_MASK 0x00040000 +#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB) +#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK) +#define PLL_CONTROL_UPDATING_MSB 17 +#define PLL_CONTROL_UPDATING_LSB 17 +#define PLL_CONTROL_UPDATING_MASK 0x00020000 +#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB) +#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK) +#define PLL_CONTROL_BYPASS_MSB 16 +#define PLL_CONTROL_BYPASS_LSB 16 +#define PLL_CONTROL_BYPASS_MASK 0x00010000 +#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB) +#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK) +#define PLL_CONTROL_REFDIV_MSB 15 +#define PLL_CONTROL_REFDIV_LSB 12 +#define PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB) +#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK) +#define PLL_CONTROL_DIV_MSB 9 +#define PLL_CONTROL_DIV_LSB 0 +#define PLL_CONTROL_DIV_MASK 0x000003ff +#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB) +#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK) + +#define PLL_SETTLE_ADDRESS 0x00000018 +#define PLL_SETTLE_OFFSET 0x00000018 +#define PLL_SETTLE_TIME_MSB 11 +#define PLL_SETTLE_TIME_LSB 0 +#define PLL_SETTLE_TIME_MASK 0x00000fff +#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB) +#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK) + +#define XTAL_SETTLE_ADDRESS 0x0000001c +#define XTAL_SETTLE_OFFSET 0x0000001c +#define XTAL_SETTLE_TIME_MSB 7 +#define XTAL_SETTLE_TIME_LSB 0 +#define XTAL_SETTLE_TIME_MASK 0x000000ff +#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB) +#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK) + +#define CPU_CLOCK_ADDRESS 0x00000020 +#define CPU_CLOCK_OFFSET 0x00000020 +#define CPU_CLOCK_STANDARD_MSB 1 +#define CPU_CLOCK_STANDARD_LSB 0 +#define CPU_CLOCK_STANDARD_MASK 0x00000003 +#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB) +#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) + +#define CLOCK_OUT_ADDRESS 0x00000024 +#define CLOCK_OUT_OFFSET 0x00000024 +#define CLOCK_OUT_SELECT_MSB 3 +#define CLOCK_OUT_SELECT_LSB 0 +#define CLOCK_OUT_SELECT_MASK 0x0000000f +#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB) +#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK) + +#define CLOCK_CONTROL_ADDRESS 0x00000028 +#define CLOCK_CONTROL_OFFSET 0x00000028 +#define CLOCK_CONTROL_LF_CLK32_MSB 2 +#define CLOCK_CONTROL_LF_CLK32_LSB 2 +#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) +#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) +#define CLOCK_CONTROL_UART_CLK_MSB 1 +#define CLOCK_CONTROL_UART_CLK_LSB 1 +#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 +#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB) +#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK) +#define CLOCK_CONTROL_SI0_CLK_MSB 0 +#define CLOCK_CONTROL_SI0_CLK_LSB 0 +#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB) +#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK) + +#define BIAS_OVERRIDE_ADDRESS 0x0000002c +#define BIAS_OVERRIDE_OFFSET 0x0000002c +#define BIAS_OVERRIDE_ON_MSB 0 +#define BIAS_OVERRIDE_ON_LSB 0 +#define BIAS_OVERRIDE_ON_MASK 0x00000001 +#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB) +#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK) + +#define WDT_CONTROL_ADDRESS 0x00000030 +#define WDT_CONTROL_OFFSET 0x00000030 +#define WDT_CONTROL_ACTION_MSB 2 +#define WDT_CONTROL_ACTION_LSB 0 +#define WDT_CONTROL_ACTION_MASK 0x00000007 +#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB) +#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK) + +#define WDT_STATUS_ADDRESS 0x00000034 +#define WDT_STATUS_OFFSET 0x00000034 +#define WDT_STATUS_INTERRUPT_MSB 0 +#define WDT_STATUS_INTERRUPT_LSB 0 +#define WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB) +#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK) + +#define WDT_ADDRESS 0x00000038 +#define WDT_OFFSET 0x00000038 +#define WDT_TARGET_MSB 21 +#define WDT_TARGET_LSB 0 +#define WDT_TARGET_MASK 0x003fffff +#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB) +#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK) + +#define WDT_COUNT_ADDRESS 0x0000003c +#define WDT_COUNT_OFFSET 0x0000003c +#define WDT_COUNT_VALUE_MSB 21 +#define WDT_COUNT_VALUE_LSB 0 +#define WDT_COUNT_VALUE_MASK 0x003fffff +#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB) +#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK) + +#define WDT_RESET_ADDRESS 0x00000040 +#define WDT_RESET_OFFSET 0x00000040 +#define WDT_RESET_VALUE_MSB 0 +#define WDT_RESET_VALUE_LSB 0 +#define WDT_RESET_VALUE_MASK 0x00000001 +#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB) +#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK) + +#define INT_STATUS_ADDRESS 0x00000044 +#define INT_STATUS_OFFSET 0x00000044 +#define INT_STATUS_RTC_POWER_MSB 14 +#define INT_STATUS_RTC_POWER_LSB 14 +#define INT_STATUS_RTC_POWER_MASK 0x00004000 +#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB) +#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK) +#define INT_STATUS_MAC_MSB 13 +#define INT_STATUS_MAC_LSB 13 +#define INT_STATUS_MAC_MASK 0x00002000 +#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB) +#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK) +#define INT_STATUS_MAILBOX_MSB 12 +#define INT_STATUS_MAILBOX_LSB 12 +#define INT_STATUS_MAILBOX_MASK 0x00001000 +#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB) +#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK) +#define INT_STATUS_RTC_ALARM_MSB 11 +#define INT_STATUS_RTC_ALARM_LSB 11 +#define INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB) +#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK) +#define INT_STATUS_HF_TIMER_MSB 10 +#define INT_STATUS_HF_TIMER_LSB 10 +#define INT_STATUS_HF_TIMER_MASK 0x00000400 +#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB) +#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK) +#define INT_STATUS_LF_TIMER3_MSB 9 +#define INT_STATUS_LF_TIMER3_LSB 9 +#define INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB) +#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK) +#define INT_STATUS_LF_TIMER2_MSB 8 +#define INT_STATUS_LF_TIMER2_LSB 8 +#define INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB) +#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK) +#define INT_STATUS_LF_TIMER1_MSB 7 +#define INT_STATUS_LF_TIMER1_LSB 7 +#define INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB) +#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK) +#define INT_STATUS_LF_TIMER0_MSB 6 +#define INT_STATUS_LF_TIMER0_LSB 6 +#define INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB) +#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK) +#define INT_STATUS_KEYPAD_MSB 5 +#define INT_STATUS_KEYPAD_LSB 5 +#define INT_STATUS_KEYPAD_MASK 0x00000020 +#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB) +#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK) +#define INT_STATUS_SI_MSB 4 +#define INT_STATUS_SI_LSB 4 +#define INT_STATUS_SI_MASK 0x00000010 +#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB) +#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK) +#define INT_STATUS_GPIO_MSB 3 +#define INT_STATUS_GPIO_LSB 3 +#define INT_STATUS_GPIO_MASK 0x00000008 +#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB) +#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK) +#define INT_STATUS_UART_MSB 2 +#define INT_STATUS_UART_LSB 2 +#define INT_STATUS_UART_MASK 0x00000004 +#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB) +#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK) +#define INT_STATUS_ERROR_MSB 1 +#define INT_STATUS_ERROR_LSB 1 +#define INT_STATUS_ERROR_MASK 0x00000002 +#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB) +#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK) +#define INT_STATUS_WDT_INT_MSB 0 +#define INT_STATUS_WDT_INT_LSB 0 +#define INT_STATUS_WDT_INT_MASK 0x00000001 +#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB) +#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK) + +#define LF_TIMER0_ADDRESS 0x00000048 +#define LF_TIMER0_OFFSET 0x00000048 +#define LF_TIMER0_TARGET_MSB 31 +#define LF_TIMER0_TARGET_LSB 0 +#define LF_TIMER0_TARGET_MASK 0xffffffff +#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB) +#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK) + +#define LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define LF_TIMER_COUNT0_OFFSET 0x0000004c +#define LF_TIMER_COUNT0_VALUE_MSB 31 +#define LF_TIMER_COUNT0_VALUE_LSB 0 +#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB) +#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK) + +#define LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL0_RESET_MSB 0 +#define LF_TIMER_CONTROL0_RESET_LSB 0 +#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) +#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK) + +#define LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define LF_TIMER_STATUS0_OFFSET 0x00000054 +#define LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define LF_TIMER1_ADDRESS 0x00000058 +#define LF_TIMER1_OFFSET 0x00000058 +#define LF_TIMER1_TARGET_MSB 31 +#define LF_TIMER1_TARGET_LSB 0 +#define LF_TIMER1_TARGET_MASK 0xffffffff +#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB) +#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK) + +#define LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define LF_TIMER_COUNT1_OFFSET 0x0000005c +#define LF_TIMER_COUNT1_VALUE_MSB 31 +#define LF_TIMER_COUNT1_VALUE_LSB 0 +#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB) +#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK) + +#define LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL1_RESET_MSB 0 +#define LF_TIMER_CONTROL1_RESET_LSB 0 +#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) +#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK) + +#define LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define LF_TIMER_STATUS1_OFFSET 0x00000064 +#define LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define LF_TIMER2_ADDRESS 0x00000068 +#define LF_TIMER2_OFFSET 0x00000068 +#define LF_TIMER2_TARGET_MSB 31 +#define LF_TIMER2_TARGET_LSB 0 +#define LF_TIMER2_TARGET_MASK 0xffffffff +#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB) +#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK) + +#define LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define LF_TIMER_COUNT2_OFFSET 0x0000006c +#define LF_TIMER_COUNT2_VALUE_MSB 31 +#define LF_TIMER_COUNT2_VALUE_LSB 0 +#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB) +#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK) + +#define LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL2_RESET_MSB 0 +#define LF_TIMER_CONTROL2_RESET_LSB 0 +#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) +#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK) + +#define LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define LF_TIMER_STATUS2_OFFSET 0x00000074 +#define LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define LF_TIMER3_ADDRESS 0x00000078 +#define LF_TIMER3_OFFSET 0x00000078 +#define LF_TIMER3_TARGET_MSB 31 +#define LF_TIMER3_TARGET_LSB 0 +#define LF_TIMER3_TARGET_MASK 0xffffffff +#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB) +#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK) + +#define LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define LF_TIMER_COUNT3_OFFSET 0x0000007c +#define LF_TIMER_COUNT3_VALUE_MSB 31 +#define LF_TIMER_COUNT3_VALUE_LSB 0 +#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB) +#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK) + +#define LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define LF_TIMER_CONTROL3_RESET_MSB 0 +#define LF_TIMER_CONTROL3_RESET_LSB 0 +#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) +#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK) + +#define LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define LF_TIMER_STATUS3_OFFSET 0x00000084 +#define LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define HF_TIMER_ADDRESS 0x00000088 +#define HF_TIMER_OFFSET 0x00000088 +#define HF_TIMER_TARGET_MSB 31 +#define HF_TIMER_TARGET_LSB 12 +#define HF_TIMER_TARGET_MASK 0xfffff000 +#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB) +#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK) + +#define HF_TIMER_COUNT_ADDRESS 0x0000008c +#define HF_TIMER_COUNT_OFFSET 0x0000008c +#define HF_TIMER_COUNT_VALUE_MSB 31 +#define HF_TIMER_COUNT_VALUE_LSB 12 +#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB) +#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK) + +#define HF_LF_COUNT_ADDRESS 0x00000090 +#define HF_LF_COUNT_OFFSET 0x00000090 +#define HF_LF_COUNT_VALUE_MSB 31 +#define HF_LF_COUNT_VALUE_LSB 0 +#define HF_LF_COUNT_VALUE_MASK 0xffffffff +#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB) +#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK) + +#define HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define HF_TIMER_CONTROL_OFFSET 0x00000094 +#define HF_TIMER_CONTROL_ENABLE_MSB 3 +#define HF_TIMER_CONTROL_ENABLE_LSB 3 +#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) +#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) +#define HF_TIMER_CONTROL_ON_MSB 2 +#define HF_TIMER_CONTROL_ON_LSB 2 +#define HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB) +#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define HF_TIMER_CONTROL_RESET_MSB 0 +#define HF_TIMER_CONTROL_RESET_LSB 0 +#define HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB) +#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK) + +#define HF_TIMER_STATUS_ADDRESS 0x00000098 +#define HF_TIMER_STATUS_OFFSET 0x00000098 +#define HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) + +#define RTC_CONTROL_ADDRESS 0x0000009c +#define RTC_CONTROL_OFFSET 0x0000009c +#define RTC_CONTROL_ENABLE_MSB 2 +#define RTC_CONTROL_ENABLE_LSB 2 +#define RTC_CONTROL_ENABLE_MASK 0x00000004 +#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB) +#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK) +#define RTC_CONTROL_LOAD_RTC_MSB 1 +#define RTC_CONTROL_LOAD_RTC_LSB 1 +#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB) +#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK) +#define RTC_CONTROL_LOAD_ALARM_MSB 0 +#define RTC_CONTROL_LOAD_ALARM_LSB 0 +#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) +#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) + +#define RTC_TIME_ADDRESS 0x000000a0 +#define RTC_TIME_OFFSET 0x000000a0 +#define RTC_TIME_WEEK_DAY_MSB 26 +#define RTC_TIME_WEEK_DAY_LSB 24 +#define RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB) +#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK) +#define RTC_TIME_HOUR_MSB 21 +#define RTC_TIME_HOUR_LSB 16 +#define RTC_TIME_HOUR_MASK 0x003f0000 +#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB) +#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK) +#define RTC_TIME_MINUTE_MSB 14 +#define RTC_TIME_MINUTE_LSB 8 +#define RTC_TIME_MINUTE_MASK 0x00007f00 +#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB) +#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK) +#define RTC_TIME_SECOND_MSB 6 +#define RTC_TIME_SECOND_LSB 0 +#define RTC_TIME_SECOND_MASK 0x0000007f +#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB) +#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK) + +#define RTC_DATE_ADDRESS 0x000000a4 +#define RTC_DATE_OFFSET 0x000000a4 +#define RTC_DATE_YEAR_MSB 23 +#define RTC_DATE_YEAR_LSB 16 +#define RTC_DATE_YEAR_MASK 0x00ff0000 +#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB) +#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK) +#define RTC_DATE_MONTH_MSB 12 +#define RTC_DATE_MONTH_LSB 8 +#define RTC_DATE_MONTH_MASK 0x00001f00 +#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB) +#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK) +#define RTC_DATE_MONTH_DAY_MSB 5 +#define RTC_DATE_MONTH_DAY_LSB 0 +#define RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB) +#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK) + +#define RTC_SET_TIME_ADDRESS 0x000000a8 +#define RTC_SET_TIME_OFFSET 0x000000a8 +#define RTC_SET_TIME_WEEK_DAY_MSB 26 +#define RTC_SET_TIME_WEEK_DAY_LSB 24 +#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB) +#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK) +#define RTC_SET_TIME_HOUR_MSB 21 +#define RTC_SET_TIME_HOUR_LSB 16 +#define RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB) +#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK) +#define RTC_SET_TIME_MINUTE_MSB 14 +#define RTC_SET_TIME_MINUTE_LSB 8 +#define RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB) +#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK) +#define RTC_SET_TIME_SECOND_MSB 6 +#define RTC_SET_TIME_SECOND_LSB 0 +#define RTC_SET_TIME_SECOND_MASK 0x0000007f +#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB) +#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK) + +#define RTC_SET_DATE_ADDRESS 0x000000ac +#define RTC_SET_DATE_OFFSET 0x000000ac +#define RTC_SET_DATE_YEAR_MSB 23 +#define RTC_SET_DATE_YEAR_LSB 16 +#define RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB) +#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK) +#define RTC_SET_DATE_MONTH_MSB 12 +#define RTC_SET_DATE_MONTH_LSB 8 +#define RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB) +#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK) +#define RTC_SET_DATE_MONTH_DAY_MSB 5 +#define RTC_SET_DATE_MONTH_DAY_LSB 0 +#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) +#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) + +#define RTC_SET_ALARM_ADDRESS 0x000000b0 +#define RTC_SET_ALARM_OFFSET 0x000000b0 +#define RTC_SET_ALARM_HOUR_MSB 21 +#define RTC_SET_ALARM_HOUR_LSB 16 +#define RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB) +#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK) +#define RTC_SET_ALARM_MINUTE_MSB 14 +#define RTC_SET_ALARM_MINUTE_LSB 8 +#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB) +#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK) +#define RTC_SET_ALARM_SECOND_MSB 6 +#define RTC_SET_ALARM_SECOND_LSB 0 +#define RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB) +#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK) + +#define RTC_CONFIG_ADDRESS 0x000000b4 +#define RTC_CONFIG_OFFSET 0x000000b4 +#define RTC_CONFIG_BCD_MSB 2 +#define RTC_CONFIG_BCD_LSB 2 +#define RTC_CONFIG_BCD_MASK 0x00000004 +#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB) +#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK) +#define RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) +#define RTC_CONFIG_DSE_MSB 0 +#define RTC_CONFIG_DSE_LSB 0 +#define RTC_CONFIG_DSE_MASK 0x00000001 +#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB) +#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK) + +#define RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define RTC_ALARM_STATUS_ENABLE_MSB 1 +#define RTC_ALARM_STATUS_ENABLE_LSB 1 +#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) +#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) +#define RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define UART_WAKEUP_ADDRESS 0x000000bc +#define UART_WAKEUP_OFFSET 0x000000bc +#define UART_WAKEUP_ENABLE_MSB 0 +#define UART_WAKEUP_ENABLE_LSB 0 +#define UART_WAKEUP_ENABLE_MASK 0x00000001 +#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB) +#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK) + +#define RESET_CAUSE_ADDRESS 0x000000c0 +#define RESET_CAUSE_OFFSET 0x000000c0 +#define RESET_CAUSE_LAST_MSB 2 +#define RESET_CAUSE_LAST_LSB 0 +#define RESET_CAUSE_LAST_MASK 0x00000007 +#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) +#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) + +#define SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define SYSTEM_SLEEP_OFFSET 0x000000c4 +#define SYSTEM_SLEEP_HOST_IF_MSB 4 +#define SYSTEM_SLEEP_HOST_IF_LSB 4 +#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB) +#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK) +#define SYSTEM_SLEEP_MBOX_MSB 3 +#define SYSTEM_SLEEP_MBOX_LSB 3 +#define SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB) +#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK) +#define SYSTEM_SLEEP_MAC_IF_MSB 2 +#define SYSTEM_SLEEP_MAC_IF_LSB 2 +#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB) +#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK) +#define SYSTEM_SLEEP_LIGHT_MSB 1 +#define SYSTEM_SLEEP_LIGHT_LSB 1 +#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB) +#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK) +#define SYSTEM_SLEEP_DISABLE_MSB 0 +#define SYSTEM_SLEEP_DISABLE_LSB 0 +#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB) +#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) + +#define SDIO_WRAPPER_ADDRESS 0x000000c8 +#define SDIO_WRAPPER_OFFSET 0x000000c8 +#define SDIO_WRAPPER_SLEEP_MSB 3 +#define SDIO_WRAPPER_SLEEP_LSB 3 +#define SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB) +#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK) +#define SDIO_WRAPPER_WAKEUP_MSB 2 +#define SDIO_WRAPPER_WAKEUP_LSB 2 +#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB) +#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK) +#define SDIO_WRAPPER_SOC_ON_MSB 1 +#define SDIO_WRAPPER_SOC_ON_LSB 1 +#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB) +#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK) +#define SDIO_WRAPPER_ON_MSB 0 +#define SDIO_WRAPPER_ON_LSB 0 +#define SDIO_WRAPPER_ON_MASK 0x00000001 +#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB) +#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK) + +#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define KEEP_AWAKE_ADDRESS 0x000000d0 +#define KEEP_AWAKE_OFFSET 0x000000d0 +#define KEEP_AWAKE_COUNT_MSB 7 +#define KEEP_AWAKE_COUNT_LSB 0 +#define KEEP_AWAKE_COUNT_MASK 0x000000ff +#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB) +#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK) + +#define LPO_CAL_TIME_ADDRESS 0x000000d4 +#define LPO_CAL_TIME_OFFSET 0x000000d4 +#define LPO_CAL_TIME_LENGTH_MSB 13 +#define LPO_CAL_TIME_LENGTH_LSB 0 +#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB) +#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK) + +#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define LPO_CAL_ADDRESS 0x000000e0 +#define LPO_CAL_OFFSET 0x000000e0 +#define LPO_CAL_ENABLE_MSB 20 +#define LPO_CAL_ENABLE_LSB 20 +#define LPO_CAL_ENABLE_MASK 0x00100000 +#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB) +#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) +#define LPO_CAL_COUNT_MSB 19 +#define LPO_CAL_COUNT_LSB 0 +#define LPO_CAL_COUNT_MASK 0x000fffff +#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB) +#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK) + +#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define LPO_CAL_TEST_STATUS_READY_MSB 16 +#define LPO_CAL_TEST_STATUS_READY_LSB 16 +#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) +#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) +#define LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define CHIP_ID_ADDRESS 0x000000ec +#define CHIP_ID_OFFSET 0x000000ec +#define CHIP_ID_DEVICE_ID_MSB 31 +#define CHIP_ID_DEVICE_ID_LSB 16 +#define CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB) +#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK) +#define CHIP_ID_CONFIG_ID_MSB 15 +#define CHIP_ID_CONFIG_ID_LSB 4 +#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB) +#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK) +#define CHIP_ID_VERSION_ID_MSB 3 +#define CHIP_ID_VERSION_ID_LSB 0 +#define CHIP_ID_VERSION_ID_MASK 0x0000000f +#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB) +#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK) + +#define DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define DERIVED_RTC_CLK_FORCE_MSB 17 +#define DERIVED_RTC_CLK_FORCE_LSB 16 +#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB) +#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK) +#define DERIVED_RTC_CLK_PERIOD_MSB 15 +#define DERIVED_RTC_CLK_PERIOD_LSB 1 +#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) +#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c +#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) +#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) + +#define POWER_REG_ADDRESS 0x00000110 +#define POWER_REG_OFFSET 0x00000110 +#define POWER_REG_VLVL_MSB 11 +#define POWER_REG_VLVL_LSB 8 +#define POWER_REG_VLVL_MASK 0x00000f00 +#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB) +#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK) +#define POWER_REG_CPU_INT_ENABLE_MSB 7 +#define POWER_REG_CPU_INT_ENABLE_LSB 7 +#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) +#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) +#define POWER_REG_WLAN_ISO_DIS_MSB 6 +#define POWER_REG_WLAN_ISO_DIS_LSB 6 +#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) +#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) +#define POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) +#define POWER_REG_RADIO_PWD_EN_MSB 4 +#define POWER_REG_RADIO_PWD_EN_LSB 4 +#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB) +#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK) +#define POWER_REG_SOC_SCALE_EN_MSB 3 +#define POWER_REG_SOC_SCALE_EN_LSB 3 +#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 +#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB) +#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK) +#define POWER_REG_WLAN_SCALE_EN_MSB 2 +#define POWER_REG_WLAN_SCALE_EN_LSB 2 +#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 +#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) +#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) +#define POWER_REG_WLAN_PWD_EN_MSB 1 +#define POWER_REG_WLAN_PWD_EN_LSB 1 +#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB) +#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK) +#define POWER_REG_POWER_EN_MSB 0 +#define POWER_REG_POWER_EN_LSB 0 +#define POWER_REG_POWER_EN_MASK 0x00000001 +#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB) +#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK) + +#define CORE_CLK_CTRL_ADDRESS 0x00000114 +#define CORE_CLK_CTRL_OFFSET 0x00000114 +#define CORE_CLK_CTRL_DIV_MSB 2 +#define CORE_CLK_CTRL_DIV_LSB 0 +#define CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB) +#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK) + +#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 +#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 +#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 +#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 +#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) +#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) + +#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 +#define SDIO_SETUP_CONFIG_OFFSET 0x00000140 +#define SDIO_SETUP_CONFIG_ENABLE_MSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_LSB 1 +#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) +#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) +#define SDIO_SETUP_CONFIG_CLEAR_MSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_LSB 0 +#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) +#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CONFIG_ADDRESS 0x00000144 +#define CPU_SETUP_CONFIG_OFFSET 0x00000144 +#define CPU_SETUP_CONFIG_ENABLE_MSB 1 +#define CPU_SETUP_CONFIG_ENABLE_LSB 1 +#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) +#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) +#define CPU_SETUP_CONFIG_CLEAR_MSB 0 +#define CPU_SETUP_CONFIG_CLEAR_LSB 0 +#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) +#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) + +#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 +#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 +#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 +#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 +#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) +#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) + +#define BB_SETUP_CONFIG_ADDRESS 0x00000180 +#define BB_SETUP_CONFIG_OFFSET 0x00000180 +#define BB_SETUP_CONFIG_ENABLE_MSB 1 +#define BB_SETUP_CONFIG_ENABLE_LSB 1 +#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 +#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) +#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) +#define BB_SETUP_CONFIG_CLEAR_MSB 0 +#define BB_SETUP_CONFIG_CLEAR_LSB 0 +#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 +#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB) +#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK) + +#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 +#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 +#define BB_SETUP_CIRCUIT_VECTOR_MSB 7 +#define BB_SETUP_CIRCUIT_VECTOR_LSB 0 +#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff +#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) +#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) + +#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 +#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_reg_reg_s { + volatile unsigned int reset_control; + volatile unsigned int xtal_control; + volatile unsigned int tcxo_detect; + volatile unsigned int xtal_test; + volatile unsigned int quadrature; + volatile unsigned int pll_control; + volatile unsigned int pll_settle; + volatile unsigned int xtal_settle; + volatile unsigned int cpu_clock; + volatile unsigned int clock_out; + volatile unsigned int clock_control; + volatile unsigned int bias_override; + volatile unsigned int wdt_control; + volatile unsigned int wdt_status; + volatile unsigned int wdt; + volatile unsigned int wdt_count; + volatile unsigned int wdt_reset; + volatile unsigned int int_status; + volatile unsigned int lf_timer0; + volatile unsigned int lf_timer_count0; + volatile unsigned int lf_timer_control0; + volatile unsigned int lf_timer_status0; + volatile unsigned int lf_timer1; + volatile unsigned int lf_timer_count1; + volatile unsigned int lf_timer_control1; + volatile unsigned int lf_timer_status1; + volatile unsigned int lf_timer2; + volatile unsigned int lf_timer_count2; + volatile unsigned int lf_timer_control2; + volatile unsigned int lf_timer_status2; + volatile unsigned int lf_timer3; + volatile unsigned int lf_timer_count3; + volatile unsigned int lf_timer_control3; + volatile unsigned int lf_timer_status3; + volatile unsigned int hf_timer; + volatile unsigned int hf_timer_count; + volatile unsigned int hf_lf_count; + volatile unsigned int hf_timer_control; + volatile unsigned int hf_timer_status; + volatile unsigned int rtc_control; + volatile unsigned int rtc_time; + volatile unsigned int rtc_date; + volatile unsigned int rtc_set_time; + volatile unsigned int rtc_set_date; + volatile unsigned int rtc_set_alarm; + volatile unsigned int rtc_config; + volatile unsigned int rtc_alarm_status; + volatile unsigned int uart_wakeup; + volatile unsigned int reset_cause; + volatile unsigned int system_sleep; + volatile unsigned int sdio_wrapper; + volatile unsigned int mac_sleep_control; + volatile unsigned int keep_awake; + volatile unsigned int lpo_cal_time; + volatile unsigned int lpo_init_dividend_int; + volatile unsigned int lpo_init_dividend_fraction; + volatile unsigned int lpo_cal; + volatile unsigned int lpo_cal_test_control; + volatile unsigned int lpo_cal_test_status; + volatile unsigned int chip_id; + volatile unsigned int derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int mac_pcu_slp_beacon; + volatile unsigned int power_reg; + volatile unsigned int core_clk_ctrl; + unsigned char pad0[8]; /* pad to 0x120 */ + volatile unsigned int sdio_setup_circuit[8]; + volatile unsigned int sdio_setup_config; + volatile unsigned int cpu_setup_config; + unsigned char pad1[24]; /* pad to 0x160 */ + volatile unsigned int cpu_setup_circuit[8]; + volatile unsigned int bb_setup_config; + unsigned char pad2[28]; /* pad to 0x1a0 */ + volatile unsigned int bb_setup_circuit[8]; + volatile unsigned int gpio_wakeup_control; +} rtc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h new file mode 100644 index 000000000000..44d24661761e --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/si_reg.h @@ -0,0 +1,205 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h new file mode 100644 index 000000000000..db573106dcd2 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/uart_reg.h @@ -0,0 +1,346 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define RBR_ADDRESS 0x00000000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00000000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00000000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00000004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00000004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00000008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00000008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0000000c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00000010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00000014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00000018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + +#define SCR_ADDRESS 0x0000001c +#define SCR_OFFSET 0x0000001c +#define SCR_SCR_MSB 7 +#define SCR_SCR_LSB 0 +#define SCR_SCR_MASK 0x000000ff +#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB) +#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK) + +#define SRBR_ADDRESS 0x00000020 +#define SRBR_OFFSET 0x00000020 +#define SRBR_SRBR_MSB 7 +#define SRBR_SRBR_LSB 0 +#define SRBR_SRBR_MASK 0x000000ff +#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB) +#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK) + +#define SIIR_ADDRESS 0x00000028 +#define SIIR_OFFSET 0x00000028 +#define SIIR_SIIR_MSB 7 +#define SIIR_SIIR_LSB 0 +#define SIIR_SIIR_MASK 0x000000ff +#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB) +#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK) + +#define MWR_ADDRESS 0x0000002c +#define MWR_OFFSET 0x0000002c +#define MWR_MWR_MSB 31 +#define MWR_MWR_LSB 0 +#define MWR_MWR_MASK 0xffffffff +#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB) +#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK) + +#define SLSR_ADDRESS 0x00000034 +#define SLSR_OFFSET 0x00000034 +#define SLSR_SLSR_MSB 7 +#define SLSR_SLSR_LSB 0 +#define SLSR_SLSR_MASK 0x000000ff +#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB) +#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK) + +#define SMSR_ADDRESS 0x00000038 +#define SMSR_OFFSET 0x00000038 +#define SMSR_SMSR_MSB 7 +#define SMSR_SMSR_LSB 0 +#define SMSR_SMSR_MASK 0x000000ff +#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB) +#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK) + +#define MRR_ADDRESS 0x0000003c +#define MRR_OFFSET 0x0000003c +#define MRR_MRR_MSB 31 +#define MRR_MRR_LSB 0 +#define MRR_MRR_MASK 0xffffffff +#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB) +#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int rbr; + volatile unsigned int dlh; + volatile unsigned int iir; + volatile unsigned int lcr; + volatile unsigned int mcr; + volatile unsigned int lsr; + volatile unsigned int msr; + volatile unsigned int scr; + volatile unsigned int srbr; + unsigned char pad0[4]; /* pad to 0x28 */ + volatile unsigned int siir; + volatile unsigned int mwr; + unsigned char pad1[4]; /* pad to 0x34 */ + volatile unsigned int slsr; + volatile unsigned int smsr; + volatile unsigned int mrr; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h new file mode 100644 index 000000000000..0c15ebfaeaa6 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw2.0/hw/vmc_reg.h @@ -0,0 +1,95 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _VMC_REG_REG_H_ +#define _VMC_REG_REG_H_ + +#define MC_TCAM_VALID_ADDRESS 0x00000000 +#define MC_TCAM_VALID_OFFSET 0x00000000 +#define MC_TCAM_VALID_BIT_MSB 0 +#define MC_TCAM_VALID_BIT_LSB 0 +#define MC_TCAM_VALID_BIT_MASK 0x00000001 +#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB) +#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK) + +#define MC_TCAM_MASK_ADDRESS 0x00000080 +#define MC_TCAM_MASK_OFFSET 0x00000080 +#define MC_TCAM_MASK_SIZE_MSB 2 +#define MC_TCAM_MASK_SIZE_LSB 0 +#define MC_TCAM_MASK_SIZE_MASK 0x00000007 +#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB) +#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK) + +#define MC_TCAM_COMPARE_ADDRESS 0x00000100 +#define MC_TCAM_COMPARE_OFFSET 0x00000100 +#define MC_TCAM_COMPARE_KEY_MSB 21 +#define MC_TCAM_COMPARE_KEY_LSB 5 +#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0 +#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB) +#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK) + +#define MC_TCAM_TARGET_ADDRESS 0x00000180 +#define MC_TCAM_TARGET_OFFSET 0x00000180 +#define MC_TCAM_TARGET_ADDR_MSB 21 +#define MC_TCAM_TARGET_ADDR_LSB 5 +#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0 +#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB) +#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK) + +#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200 +#define ADDR_ERROR_CONTROL_OFFSET 0x00000200 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB) +#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define ADDR_ERROR_STATUS_ADDRESS 0x00000204 +#define ADDR_ERROR_STATUS_OFFSET 0x00000204 +#define ADDR_ERROR_STATUS_WRITE_MSB 25 +#define ADDR_ERROR_STATUS_WRITE_LSB 25 +#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB) +#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK) +#define ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB) +#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_reg_reg_s { + volatile unsigned int mc_tcam_valid[32]; + volatile unsigned int mc_tcam_mask[32]; + volatile unsigned int mc_tcam_compare[32]; + volatile unsigned int mc_tcam_target[32]; + volatile unsigned int addr_error_control; + volatile unsigned int addr_error_status; +} vmc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h new file mode 100644 index 000000000000..20194688df1d --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_ares_reg.h @@ -0,0 +1,3287 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _ANALOG_INTF_ARES_REG_REG_H_ +#define _ANALOG_INTF_ARES_REG_REG_H_ + + +/* macros for RXRF_BIAS1 */ +#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_BIAS2 */ +#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MSB 10 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_LSB 8 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MASK 0x00000700 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MSB 13 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_LSB 11 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MASK 0x00003800 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MSB 16 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_LSB 14 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MASK 0x0001c000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MSB 19 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_LSB 17 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MASK 0x000e0000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MSB 22 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_LSB 20 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MASK 0x00700000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MSB 25 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_LSB 23 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MASK 0x03800000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXRF_GAINSTAGES */ +#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_AGC */ +#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c +#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c +#define PHY_ANALOG_RXRF_AGC_SPARE_MSB 5 +#define PHY_ANALOG_RXRF_AGC_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_AGC_SPARE_MASK 0x0000003f +#define PHY_ANALOG_RXRF_AGC_SPARE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_RXRF_AGC_SPARE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF1 */ +#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040 +#define PHY_ANALOG_TXRF1_OFFSET 0x00000040 +#define PHY_ANALOG_TXRF1_DCAS2G_MSB 2 +#define PHY_ANALOG_TXRF1_DCAS2G_LSB 0 +#define PHY_ANALOG_TXRF1_DCAS2G_MASK 0x00000007 +#define PHY_ANALOG_TXRF1_DCAS2G_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF1_DCAS2G_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MSB 5 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_LSB 3 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MASK 0x00000038 +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF1_OB2G_PALOFF_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF1_OB2G_QAM_MSB 8 +#define PHY_ANALOG_TXRF1_OB2G_QAM_LSB 6 +#define PHY_ANALOG_TXRF1_OB2G_QAM_MASK 0x000001c0 +#define PHY_ANALOG_TXRF1_OB2G_QAM_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF1_OB2G_QAM_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF1_OB2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF1_OB2G_PSK_LSB 9 +#define PHY_ANALOG_TXRF1_OB2G_PSK_MASK 0x00000e00 +#define PHY_ANALOG_TXRF1_OB2G_PSK_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF1_OB2G_PSK_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF1_OB2G_CCK_MSB 14 +#define PHY_ANALOG_TXRF1_OB2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF1_OB2G_CCK_MASK 0x00007000 +#define PHY_ANALOG_TXRF1_OB2G_CCK_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF1_OB2G_CCK_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF1_DB2G_MSB 17 +#define PHY_ANALOG_TXRF1_DB2G_LSB 15 +#define PHY_ANALOG_TXRF1_DB2G_MASK 0x00038000 +#define PHY_ANALOG_TXRF1_DB2G_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF1_DB2G_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 18 +#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 18 +#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00040000 +#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TXRF1_PDDR2G_MSB 19 +#define PHY_ANALOG_TXRF1_PDDR2G_LSB 19 +#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00080000 +#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 20 +#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 20 +#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF1_PDLO2G_MSB 21 +#define PHY_ANALOG_TXRF1_PDLO2G_LSB 21 +#define PHY_ANALOG_TXRF1_PDLO2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF1_PDLO2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF1_PDLO2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30 +#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24 +#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF2 */ +#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044 +#define PHY_ANALOG_TXRF2_OFFSET 0x00000044 +#define PHY_ANALOG_TXRF2_SPARE2_MSB 0 +#define PHY_ANALOG_TXRF2_SPARE2_LSB 0 +#define PHY_ANALOG_TXRF2_SPARE2_MASK 0x00000001 +#define PHY_ANALOG_TXRF2_SPARE2_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF2_SPARE2_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF2_D3B5G_MSB 3 +#define PHY_ANALOG_TXRF2_D3B5G_LSB 1 +#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x0000000e +#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_TXRF2_D4B5G_MSB 6 +#define PHY_ANALOG_TXRF2_D4B5G_LSB 4 +#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000070 +#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 10 +#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 7 +#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x00000780 +#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x00000780) >> 7) +#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 7) & 0x00000780) +#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 11 +#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 11 +#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x00000800 +#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF2_PDLOBUF5G_MSB 12 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_LSB 12 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_MASK 0x00001000 +#define PHY_ANALOG_TXRF2_PDLOBUF5G_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TXRF2_PDLOBUF5G_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TXRF2_PDLODIV5G_MSB 13 +#define PHY_ANALOG_TXRF2_PDLODIV5G_LSB 13 +#define PHY_ANALOG_TXRF2_PDLODIV5G_MASK 0x00002000 +#define PHY_ANALOG_TXRF2_PDLODIV5G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF2_PDLODIV5G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MSB 14 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_LSB 14 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MASK 0x00004000 +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MSB 15 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_LSB 15 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MASK 0x00008000 +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TXRF2_LODIV5GFORCED_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TXRF2_PADRV2GN5G_MSB 19 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_LSB 16 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF2_PADRV2GN5G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF2_PADRV2GN5G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF2_PADRV3GN5G_MSB 23 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_LSB 20 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_MASK 0x00f00000 +#define PHY_ANALOG_TXRF2_PADRV3GN5G_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_ANALOG_TXRF2_PADRV3GN5G_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_ANALOG_TXRF2_PADRV4GN5G_MSB 27 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_LSB 24 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_MASK 0x0f000000 +#define PHY_ANALOG_TXRF2_PADRV4GN5G_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_ANALOG_TXRF2_PADRV4GN5G_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MSB 28 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_LSB 28 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MASK 0x10000000 +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TXRF2_OCAS2G_MSB 31 +#define PHY_ANALOG_TXRF2_OCAS2G_LSB 29 +#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF3 */ +#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048 +#define PHY_ANALOG_TXRF3_OFFSET 0x00000048 +#define PHY_ANALOG_TXRF3_SPARE3_MSB 22 +#define PHY_ANALOG_TXRF3_SPARE3_LSB 0 +#define PHY_ANALOG_TXRF3_SPARE3_MASK 0x007fffff +#define PHY_ANALOG_TXRF3_SPARE3_GET(x) (((x) & 0x007fffff) >> 0) +#define PHY_ANALOG_TXRF3_SPARE3_SET(x) (((x) << 0) & 0x007fffff) +#define PHY_ANALOG_TXRF3_CAS5G_MSB 25 +#define PHY_ANALOG_TXRF3_CAS5G_LSB 23 +#define PHY_ANALOG_TXRF3_CAS5G_MASK 0x03800000 +#define PHY_ANALOG_TXRF3_CAS5G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF3_CAS5G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF3_OB5G_MSB 28 +#define PHY_ANALOG_TXRF3_OB5G_LSB 26 +#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF3_D2B5G_MSB 31 +#define PHY_ANALOG_TXRF3_D2B5G_LSB 29 +#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF4 */ +#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c +#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 2 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 0 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x00000007 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 5 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 3 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x00000038 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 8 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 6 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x000001c0 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 9 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x00000e00 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 14 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x00007000 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 17 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 15 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0x00038000 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF4_FILTR2G_MSB 19 +#define PHY_ANALOG_TXRF4_FILTR2G_LSB 18 +#define PHY_ANALOG_TXRF4_FILTR2G_MASK 0x000c0000 +#define PHY_ANALOG_TXRF4_FILTR2G_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_TXRF4_FILTR2G_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_TXRF4_PWDFB2_2G_MSB 20 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_LSB 20 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF4_PWDFB2_2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF4_PWDFB2_2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF4_PWDFB1_2G_MSB 21 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_LSB 21 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF4_PWDFB1_2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF4_PWDFB1_2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF4_PDFB2G_MSB 22 +#define PHY_ANALOG_TXRF4_PDFB2G_LSB 22 +#define PHY_ANALOG_TXRF4_PDFB2G_MASK 0x00400000 +#define PHY_ANALOG_TXRF4_PDFB2G_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF4_PDFB2G_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF4_RDIV5G_MSB 24 +#define PHY_ANALOG_TXRF4_RDIV5G_LSB 23 +#define PHY_ANALOG_TXRF4_RDIV5G_MASK 0x01800000 +#define PHY_ANALOG_TXRF4_RDIV5G_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_TXRF4_RDIV5G_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_TXRF4_CAPDIV5G_MSB 27 +#define PHY_ANALOG_TXRF4_CAPDIV5G_LSB 25 +#define PHY_ANALOG_TXRF4_CAPDIV5G_MASK 0x0e000000 +#define PHY_ANALOG_TXRF4_CAPDIV5G_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_TXRF4_CAPDIV5G_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_TXRF4_PDPREDIST5G_MSB 28 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_LSB 28 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_MASK 0x10000000 +#define PHY_ANALOG_TXRF4_PDPREDIST5G_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TXRF4_PDPREDIST5G_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TXRF4_RDIV2G_MSB 30 +#define PHY_ANALOG_TXRF4_RDIV2G_LSB 29 +#define PHY_ANALOG_TXRF4_RDIV2G_MASK 0x60000000 +#define PHY_ANALOG_TXRF4_RDIV2G_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_TXRF4_RDIV2G_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_TXRF4_PDPREDIST2G_MSB 31 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_LSB 31 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF4_PDPREDIST2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF4_PDPREDIST2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF5 */ +#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050 +#define PHY_ANALOG_TXRF5_OFFSET 0x00000050 +#define PHY_ANALOG_TXRF5_FBHI2G_MSB 0 +#define PHY_ANALOG_TXRF5_FBHI2G_LSB 0 +#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000001 +#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF5_FBLO2G_MSB 1 +#define PHY_ANALOG_TXRF5_FBLO2G_LSB 1 +#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000002 +#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF5_REFHI2G_MSB 4 +#define PHY_ANALOG_TXRF5_REFHI2G_LSB 2 +#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0000001c +#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF5_REFLO2G_MSB 7 +#define PHY_ANALOG_TXRF5_REFLO2G_LSB 5 +#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 9 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 8 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00000300 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 11 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 10 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x00000c00 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 10) & 0x00000c00) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 13 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 12 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x00003000 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 15 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 14 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x0000c000 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 17 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 16 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0x00030000 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MSB 19 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_LSB 18 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MASK 0x000c0000 +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_TXRF5_PK1B2G_CCK_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MSB 22 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_LSB 20 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MASK 0x00700000 +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF5_MIOB2G_QAM_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_LSB 23 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MASK 0x03800000 +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF5_MIOB2G_PSK_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MSB 28 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MASK 0x1c000000 +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF5_MIOB2G_CCK_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF5_COMP2G_QAM_MSB 31 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_LSB 29 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_MASK 0xe0000000 +#define PHY_ANALOG_TXRF5_COMP2G_QAM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF5_COMP2G_QAM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF6 */ +#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054 +#define PHY_ANALOG_TXRF6_OFFSET 0x00000054 +#define PHY_ANALOG_TXRF6_SPARE6_MSB 0 +#define PHY_ANALOG_TXRF6_SPARE6_LSB 0 +#define PHY_ANALOG_TXRF6_SPARE6_MASK 0x00000001 +#define PHY_ANALOG_TXRF6_SPARE6_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF6_SPARE6_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF6_PAL_LOCKED_MSB 1 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_LSB 1 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_MASK 0x00000002 +#define PHY_ANALOG_TXRF6_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MSB 7 +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_LSB 2 +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MASK 0x000000fc +#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 10 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 8 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 11 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 11 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00000800 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 15 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 12 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x0000f000 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 18 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 16 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x00070000 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 21 +#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 19 +#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x00380000 +#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 22 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 22 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x00400000 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF6_ENPACAL2G_MSB 23 +#define PHY_ANALOG_TXRF6_ENPACAL2G_LSB 23 +#define PHY_ANALOG_TXRF6_ENPACAL2G_MASK 0x00800000 +#define PHY_ANALOG_TXRF6_ENPACAL2G_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF6_ENPACAL2G_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF6_OFFSET2G_MSB 30 +#define PHY_ANALOG_TXRF6_OFFSET2G_LSB 24 +#define PHY_ANALOG_TXRF6_OFFSET2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF6_OFFSET2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF6_OFFSET2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MSB 31 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_LSB 31 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF7 */ +#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058 +#define PHY_ANALOG_TXRF7_OFFSET 0x00000058 +#define PHY_ANALOG_TXRF7_SPARE7_MSB 1 +#define PHY_ANALOG_TXRF7_SPARE7_LSB 0 +#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003 +#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF8 */ +#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c +#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c +#define PHY_ANALOG_TXRF8_SPARE8_MSB 1 +#define PHY_ANALOG_TXRF8_SPARE8_LSB 0 +#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003 +#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF9 */ +#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060 +#define PHY_ANALOG_TXRF9_OFFSET 0x00000060 +#define PHY_ANALOG_TXRF9_SPARE9_MSB 1 +#define PHY_ANALOG_TXRF9_SPARE9_LSB 0 +#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003 +#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF10 */ +#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064 +#define PHY_ANALOG_TXRF10_OFFSET 0x00000064 +#define PHY_ANALOG_TXRF10_SPARE10_MSB 12 +#define PHY_ANALOG_TXRF10_SPARE10_LSB 0 +#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00001fff +#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00001fff) >> 0) +#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00001fff) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 13 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 13 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00002000 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 16 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 14 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x0001c000 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 19 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 17 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x000e0000 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 26 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 20 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x07f00000 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x07f00000) >> 20) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 20) & 0x07f00000) +#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 29 +#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 27 +#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x38000000 +#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 30 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 30 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x40000000 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 31 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 31 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x80000000 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF11 */ +#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068 +#define PHY_ANALOG_TXRF11_OFFSET 0x00000068 +#define PHY_ANALOG_TXRF11_SPARE11_MSB 1 +#define PHY_ANALOG_TXRF11_SPARE11_LSB 0 +#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003 +#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MSB 4 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_LSB 2 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MASK 0x0000001c +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 7 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 5 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 10 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 8 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 13 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 11 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00003800 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 16 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 14 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 19 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 17 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x000e0000 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF12 */ +#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c +#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c +#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7 +#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0 +#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff +#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 15 +#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8 +#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x0000ff00 +#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 19 +#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 16 +#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 22 +#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 20 +#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x00700000 +#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 25 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 23 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x03800000 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 28 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 26 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x1c000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 31 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 29 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0xe0000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH1 */ +#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080 +#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15 +#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13 +#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000 +#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000 +#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000 +#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH2 */ +#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084 +#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f +#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MSB 15 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_LSB 12 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MASK 0x0000f000 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_SYNTH2_CPLOWLK_MSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_LSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_MASK 0x00010000 +#define PHY_ANALOG_SYNTH2_CPLOWLK_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH2_CPLOWLK_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH2_CPBIAS_MSB 19 +#define PHY_ANALOG_SYNTH2_CPBIAS_LSB 18 +#define PHY_ANALOG_SYNTH2_CPBIAS_MASK 0x000c0000 +#define PHY_ANALOG_SYNTH2_CPBIAS_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_SYNTH2_CPBIAS_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH3 */ +#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088 +#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH4 */ +#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c +#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH4_SDM_DITHER_MSB 7 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_LSB 6 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH4_SDM_DITHER_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH4_SDM_DITHER_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100 +#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12 +#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11 +#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800 +#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH5 */ +#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090 +#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1 +#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003 +#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_SYNTH5_SPARE5A_MSB 31 +#define PHY_ANALOG_SYNTH5_SPARE5A_LSB 30 +#define PHY_ANALOG_SYNTH5_SPARE5A_MASK 0xc0000000 +#define PHY_ANALOG_SYNTH5_SPARE5A_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_SYNTH5_SPARE5A_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for SYNTH6 */ +#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094 +#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8 +#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2 +#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc +#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2) +#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200 +#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400 +#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000 +#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000 +#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000 +#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000 +#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for SYNTH7 */ +#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098 +#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18 +#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2 +#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc +#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2) +#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc) +#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27 +#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19 +#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000 +#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19) +#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000 +#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH8 */ +#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c +#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31 +#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27 +#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH9 */ +#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0 +#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31 +#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27 +#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH10 */ +#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4 +#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4 +#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000001 +#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 3 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 1 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000000e +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MSB 4 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_LSB 4 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MASK 0x00000010 +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH11 */ +#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8 +#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8 +#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4 +#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0 +#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f +#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7 +#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6 +#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH12 */ +#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac +#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac +#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 17 +#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0 +#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x0003ffff +#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x0003ffff) +#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000 +#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22 +#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19 +#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000 +#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26 +#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23 +#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000 +#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30 +#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27 +#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000 +#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BIAS1 */ +#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0 +#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0 +#define PHY_ANALOG_BIAS1_SPARE1_MSB 6 +#define PHY_ANALOG_BIAS1_SPARE1_LSB 0 +#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f +#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31 +#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25 +#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000 +#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25) +#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000) + +/* macros for BIAS2 */ +#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4 +#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4 +#define PHY_ANALOG_BIAS2_SPARE2_MSB 4 +#define PHY_ANALOG_BIAS2_SPARE2_LSB 0 +#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f +#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MSB 7 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_LSB 5 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MASK 0x000000e0 +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MSB 19 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_LSB 17 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MASK 0x000e0000 +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS3 */ +#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8 +#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8 +#define PHY_ANALOG_BIAS3_SPARE3_MSB 1 +#define PHY_ANALOG_BIAS3_SPARE3_LSB 0 +#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003 +#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MSB 4 +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_LSB 2 +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MASK 0x0000001c +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MSB 13 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_LSB 11 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MASK 0x00003800 +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS4 */ +#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc +#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc +#define PHY_ANALOG_BIAS4_SPARE4_MSB 13 +#define PHY_ANALOG_BIAS4_SPARE4_LSB 0 +#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x00003fff +#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MSB 22 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_LSB 20 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MASK 0x00700000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX1 */ +#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100 +#define PHY_ANALOG_RXTX1_OFFSET 0x00000100 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002 +#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c +#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18 +#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15 +#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000 +#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30 +#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27 +#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000 +#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000 +#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXTX2 */ +#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104 +#define PHY_ANALOG_RXTX2_OFFSET 0x00000104 +#define PHY_ANALOG_RXTX2_BMODE_MSB 0 +#define PHY_ANALOG_RXTX2_BMODE_LSB 0 +#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001 +#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002 +#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004 +#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX2_BW_ST_MSB 5 +#define PHY_ANALOG_RXTX2_BW_ST_LSB 4 +#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030 +#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX2_TXON_MSB 7 +#define PHY_ANALOG_RXTX2_TXON_LSB 7 +#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080 +#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX2_PAON_MSB 9 +#define PHY_ANALOG_RXTX2_PAON_LSB 9 +#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200 +#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX2_RXON_MSB 11 +#define PHY_ANALOG_RXTX2_RXON_LSB 11 +#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800 +#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000 +#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RXTX2_AGCON_MSB 13 +#define PHY_ANALOG_RXTX2_AGCON_LSB 13 +#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000 +#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000 +#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX2_TXMOD_MSB 17 +#define PHY_ANALOG_RXTX2_TXMOD_LSB 15 +#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000 +#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25 +#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24 +#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000 +#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28 +#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26 +#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000 +#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31 +#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29 +#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000 +#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX3 */ +#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108 +#define PHY_ANALOG_RXTX3_OFFSET 0x00000108 +#define PHY_ANALOG_RXTX3_SPARE3_MSB 2 +#define PHY_ANALOG_RXTX3_SPARE3_LSB 0 +#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007 +#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 3 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 3 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000008 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX3_DACRSTB_MSB 4 +#define PHY_ANALOG_RXTX3_DACRSTB_LSB 4 +#define PHY_ANALOG_RXTX3_DACRSTB_MASK 0x00000010 +#define PHY_ANALOG_RXTX3_DACRSTB_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXTX3_DACRSTB_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MSB 5 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_LSB 5 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MASK 0x00000020 +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040 +#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX3_DACPWD_MSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_LSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080 +#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200 +#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000 +#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000 +#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_RXTX3_CALFC_MSB 22 +#define PHY_ANALOG_RXTX3_CALFC_LSB 22 +#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000 +#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000 +#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_RXTX3_CALTX_MSB 24 +#define PHY_ANALOG_RXTX3_CALTX_LSB 24 +#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000 +#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000 +#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_RXTX3_CALPA_MSB 28 +#define PHY_ANALOG_RXTX3_CALPA_LSB 28 +#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000 +#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXTX3_SPURON_MSB 30 +#define PHY_ANALOG_RXTX3_SPURON_LSB 30 +#define PHY_ANALOG_RXTX3_SPURON_MASK 0x40000000 +#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXTX3_SPURON_OVR_MSB 31 +#define PHY_ANALOG_RXTX3_SPURON_OVR_LSB 31 +#define PHY_ANALOG_RXTX3_SPURON_OVR_MASK 0x80000000 +#define PHY_ANALOG_RXTX3_SPURON_OVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX3_SPURON_OVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB1 */ +#define PHY_ANALOG_BB1_ADDRESS 0x00000140 +#define PHY_ANALOG_BB1_OFFSET 0x00000140 +#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001 +#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002 +#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004 +#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010 +#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100 +#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200 +#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400 +#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800 +#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000 +#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_BB1_CMSEL_MSB 15 +#define PHY_ANALOG_BB1_CMSEL_LSB 13 +#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000 +#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BB1_ATBSEL_MSB 17 +#define PHY_ANALOG_BB1_ATBSEL_LSB 16 +#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000 +#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000 +#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31 +#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30 +#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000 +#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB2 */ +#define PHY_ANALOG_BB2_ADDRESS 0x00000144 +#define PHY_ANALOG_BB2_OFFSET 0x00000144 +#define PHY_ANALOG_BB2_SPARE_MSB 6 +#define PHY_ANALOG_BB2_SPARE_LSB 0 +#define PHY_ANALOG_BB2_SPARE_MASK 0x0000007f +#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BB2_SEL_TEST_MSB 9 +#define PHY_ANALOG_BB2_SEL_TEST_LSB 7 +#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000380 +#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BB2_SCFIR_CAP_MSB 14 +#define PHY_ANALOG_BB2_SCFIR_CAP_LSB 10 +#define PHY_ANALOG_BB2_SCFIR_CAP_MASK 0x00007c00 +#define PHY_ANALOG_BB2_SCFIR_CAP_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_ANALOG_BB2_SCFIR_CAP_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_LSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MASK 0x00008000 +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_BB2_FNOTCH_MSB 19 +#define PHY_ANALOG_BB2_FNOTCH_LSB 16 +#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000 +#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_BB2_FILTERFC_MSB 25 +#define PHY_ANALOG_BB2_FILTERFC_LSB 21 +#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000 +#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TOP1 */ +#define PHY_ANALOG_TOP1_ADDRESS 0x00000280 +#define PHY_ANALOG_TOP1_OFFSET 0x00000280 +#define PHY_ANALOG_TOP1_SEL_KVCO_MSB 1 +#define PHY_ANALOG_TOP1_SEL_KVCO_LSB 0 +#define PHY_ANALOG_TOP1_SEL_KVCO_MASK 0x00000003 +#define PHY_ANALOG_TOP1_SEL_KVCO_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TOP1_SEL_KVCO_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TOP1_PLLATB_MSB 3 +#define PHY_ANALOG_TOP1_PLLATB_LSB 2 +#define PHY_ANALOG_TOP1_PLLATB_MASK 0x0000000c +#define PHY_ANALOG_TOP1_PLLATB_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_TOP1_PLLATB_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_TOP1_PLL_SVREG_MSB 4 +#define PHY_ANALOG_TOP1_PLL_SVREG_LSB 4 +#define PHY_ANALOG_TOP1_PLL_SVREG_MASK 0x00000010 +#define PHY_ANALOG_TOP1_PLL_SVREG_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP1_PLL_SVREG_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP1_HI_FREQ_EN_MSB 5 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_LSB 5 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_MASK 0x00000020 +#define PHY_ANALOG_TOP1_HI_FREQ_EN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP1_HI_FREQ_EN_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP1_PWDPLL_MSB 6 +#define PHY_ANALOG_TOP1_PWDPLL_LSB 6 +#define PHY_ANALOG_TOP1_PWDPLL_MASK 0x00000040 +#define PHY_ANALOG_TOP1_PWDPLL_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP1_PWDPLL_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MSB 7 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_LSB 7 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MASK 0x00000080 +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MSB 9 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_LSB 8 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MASK 0x00000300 +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TOP1_ADCPWD_PHASE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MSB 11 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_LSB 10 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MASK 0x00000c00 +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_ANALOG_TOP1_ADCCLK_PHASE_SET(x) (((x) << 10) & 0x00000c00) +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MSB 13 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_LSB 12 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MASK 0x00003000 +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_TOP1_DAC_CLK_SEL_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MSB 15 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_LSB 14 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MASK 0x0000c000 +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TOP1_ADC_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TOP1_REFDIV_MSB 19 +#define PHY_ANALOG_TOP1_REFDIV_LSB 16 +#define PHY_ANALOG_TOP1_REFDIV_MASK 0x000f0000 +#define PHY_ANALOG_TOP1_REFDIV_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TOP1_REFDIV_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TOP1_DIV_MSB 29 +#define PHY_ANALOG_TOP1_DIV_LSB 20 +#define PHY_ANALOG_TOP1_DIV_MASK 0x3ff00000 +#define PHY_ANALOG_TOP1_DIV_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_ANALOG_TOP1_DIV_SET(x) (((x) << 20) & 0x3ff00000) +#define PHY_ANALOG_TOP1_PLLBYPASS_MSB 30 +#define PHY_ANALOG_TOP1_PLLBYPASS_LSB 30 +#define PHY_ANALOG_TOP1_PLLBYPASS_MASK 0x40000000 +#define PHY_ANALOG_TOP1_PLLBYPASS_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP1_PLLBYPASS_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MSB 31 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_LSB 31 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MASK 0x80000000 +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TOP1_CLKMOD_RSTB_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TOP2 */ +#define PHY_ANALOG_TOP2_ADDRESS 0x00000284 +#define PHY_ANALOG_TOP2_OFFSET 0x00000284 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MSB 0 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_LSB 0 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MASK 0x00000001 +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TOP2_PLL_LOWLEAK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TOP2_PLL_LEAK_MSB 4 +#define PHY_ANALOG_TOP2_PLL_LEAK_LSB 1 +#define PHY_ANALOG_TOP2_PLL_LEAK_MASK 0x0000001e +#define PHY_ANALOG_TOP2_PLL_LEAK_GET(x) (((x) & 0x0000001e) >> 1) +#define PHY_ANALOG_TOP2_PLL_LEAK_SET(x) (((x) << 1) & 0x0000001e) +#define PHY_ANALOG_TOP2_PLLFRAC_MSB 19 +#define PHY_ANALOG_TOP2_PLLFRAC_LSB 5 +#define PHY_ANALOG_TOP2_PLLFRAC_MASK 0x000fffe0 +#define PHY_ANALOG_TOP2_PLLFRAC_GET(x) (((x) & 0x000fffe0) >> 5) +#define PHY_ANALOG_TOP2_PLLFRAC_SET(x) (((x) << 5) & 0x000fffe0) +#define PHY_ANALOG_TOP2_PWD_PLLSDM_MSB 20 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_LSB 20 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_MASK 0x00100000 +#define PHY_ANALOG_TOP2_PWD_PLLSDM_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP2_PWD_PLLSDM_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP2_PLLICP_MSB 23 +#define PHY_ANALOG_TOP2_PLLICP_LSB 21 +#define PHY_ANALOG_TOP2_PLLICP_MASK 0x00e00000 +#define PHY_ANALOG_TOP2_PLLICP_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_TOP2_PLLICP_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_TOP2_PLLFILTER_MSB 31 +#define PHY_ANALOG_TOP2_PLLFILTER_LSB 24 +#define PHY_ANALOG_TOP2_PLLFILTER_MASK 0xff000000 +#define PHY_ANALOG_TOP2_PLLFILTER_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_ANALOG_TOP2_PLLFILTER_SET(x) (((x) << 24) & 0xff000000) + +/* macros for TOP3 */ +#define PHY_ANALOG_TOP3_ADDRESS 0x00000288 +#define PHY_ANALOG_TOP3_OFFSET 0x00000288 +#define PHY_ANALOG_TOP3_INT2GND_MSB 0 +#define PHY_ANALOG_TOP3_INT2GND_LSB 0 +#define PHY_ANALOG_TOP3_INT2GND_MASK 0x00000001 +#define PHY_ANALOG_TOP3_INT2GND_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TOP3_INT2GND_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TOP3_PWDPALCLK_MSB 1 +#define PHY_ANALOG_TOP3_PWDPALCLK_LSB 1 +#define PHY_ANALOG_TOP3_PWDPALCLK_MASK 0x00000002 +#define PHY_ANALOG_TOP3_PWDPALCLK_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TOP3_PWDPALCLK_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_TOP3_PWDAGCCLK_MSB 2 +#define PHY_ANALOG_TOP3_PWDAGCCLK_LSB 2 +#define PHY_ANALOG_TOP3_PWDAGCCLK_MASK 0x00000004 +#define PHY_ANALOG_TOP3_PWDAGCCLK_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TOP3_PWDAGCCLK_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TOP3_PWDV2I_MSB 3 +#define PHY_ANALOG_TOP3_PWDV2I_LSB 3 +#define PHY_ANALOG_TOP3_PWDV2I_MASK 0x00000008 +#define PHY_ANALOG_TOP3_PWDV2I_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TOP3_PWDV2I_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TOP3_PWDBIAS_MSB 4 +#define PHY_ANALOG_TOP3_PWDBIAS_LSB 4 +#define PHY_ANALOG_TOP3_PWDBIAS_MASK 0x00000010 +#define PHY_ANALOG_TOP3_PWDBIAS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP3_PWDBIAS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP3_PWDBG_MSB 5 +#define PHY_ANALOG_TOP3_PWDBG_LSB 5 +#define PHY_ANALOG_TOP3_PWDBG_MASK 0x00000020 +#define PHY_ANALOG_TOP3_PWDBG_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP3_PWDBG_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP3_XTAL_SELVREG_MSB 6 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_LSB 6 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_MASK 0x00000040 +#define PHY_ANALOG_TOP3_XTAL_SELVREG_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP3_XTAL_SELVREG_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP3_XTAL_PWDREG_MSB 7 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_LSB 7 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_MASK 0x00000080 +#define PHY_ANALOG_TOP3_XTAL_PWDREG_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP3_XTAL_PWDREG_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MSB 8 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_LSB 8 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MASK 0x00000100 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MSB 9 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_LSB 9 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MASK 0x00000200 +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_TOP3_XTAL_OSCON_MSB 10 +#define PHY_ANALOG_TOP3_XTAL_OSCON_LSB 10 +#define PHY_ANALOG_TOP3_XTAL_OSCON_MASK 0x00000400 +#define PHY_ANALOG_TOP3_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_TOP3_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MSB 11 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_LSB 11 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MASK 0x00000800 +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MSB 12 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_LSB 12 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MASK 0x00001000 +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MSB 13 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_LSB 13 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MASK 0x00002000 +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TOP3_XTAL_HIGHZ_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MSB 15 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_LSB 14 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MASK 0x0000c000 +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_TOP3_XTAL_DRVPNR_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MSB 22 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_LSB 16 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MASK 0x007f0000 +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MSB 29 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_LSB 23 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MASK 0x3f800000 +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MSB 30 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_LSB 30 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MASK 0x40000000 +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP3_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP3_TCXODET_MSB 31 +#define PHY_ANALOG_TOP3_TCXODET_LSB 31 +#define PHY_ANALOG_TOP3_TCXODET_MASK 0x80000000 +#define PHY_ANALOG_TOP3_TCXODET_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for TOP4 */ +#define PHY_ANALOG_TOP4_ADDRESS 0x0000028c +#define PHY_ANALOG_TOP4_OFFSET 0x0000028c +#define PHY_ANALOG_TOP4_SPARE4_MSB 19 +#define PHY_ANALOG_TOP4_SPARE4_LSB 0 +#define PHY_ANALOG_TOP4_SPARE4_MASK 0x000fffff +#define PHY_ANALOG_TOP4_SPARE4_GET(x) (((x) & 0x000fffff) >> 0) +#define PHY_ANALOG_TOP4_SPARE4_SET(x) (((x) << 0) & 0x000fffff) +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MSB 20 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_LSB 20 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MASK 0x00100000 +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP4_ADCPWD_OVR_MSB 21 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_LSB 21 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_MASK 0x00200000 +#define PHY_ANALOG_TOP4_ADCPWD_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TOP4_ADCPWD_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TOP4_ADCPWD_INT_MSB 22 +#define PHY_ANALOG_TOP4_ADCPWD_INT_LSB 22 +#define PHY_ANALOG_TOP4_ADCPWD_INT_MASK 0x00400000 +#define PHY_ANALOG_TOP4_ADCPWD_INT_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TOP4_ADCPWD_INT_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TOP4_TESTIQ_OFF_MSB 23 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_LSB 23 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_MASK 0x00800000 +#define PHY_ANALOG_TOP4_TESTIQ_OFF_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TOP4_TESTIQ_OFF_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MSB 24 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_LSB 24 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MASK 0x01000000 +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MSB 25 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_LSB 25 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MASK 0x02000000 +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MSB 26 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_LSB 26 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MASK 0x04000000 +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_TOP4_ENBTCLK_MSB 27 +#define PHY_ANALOG_TOP4_ENBTCLK_LSB 27 +#define PHY_ANALOG_TOP4_ENBTCLK_MASK 0x08000000 +#define PHY_ANALOG_TOP4_ENBTCLK_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_TOP4_ENBTCLK_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_TOP4_PAD2GND_MSB 28 +#define PHY_ANALOG_TOP4_PAD2GND_LSB 28 +#define PHY_ANALOG_TOP4_PAD2GND_MASK 0x10000000 +#define PHY_ANALOG_TOP4_PAD2GND_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TOP4_PAD2GND_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TOP4_INTH2PAD_MSB 29 +#define PHY_ANALOG_TOP4_INTH2PAD_LSB 29 +#define PHY_ANALOG_TOP4_INTH2PAD_MASK 0x20000000 +#define PHY_ANALOG_TOP4_INTH2PAD_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_TOP4_INTH2PAD_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_TOP4_INTH2GND_MSB 30 +#define PHY_ANALOG_TOP4_INTH2GND_LSB 30 +#define PHY_ANALOG_TOP4_INTH2GND_MASK 0x40000000 +#define PHY_ANALOG_TOP4_INTH2GND_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_TOP4_INTH2GND_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_TOP4_INT2PAD_MSB 31 +#define PHY_ANALOG_TOP4_INT2PAD_LSB 31 +#define PHY_ANALOG_TOP4_INT2PAD_MASK 0x80000000 +#define PHY_ANALOG_TOP4_INT2PAD_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TOP4_INT2PAD_SET(x) (((x) << 31) & 0x80000000) + +/* macros for rbist_cntrl */ +#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000) + +/* macros for tx_dc_offset */ +#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000) + +/* macros for tx_tonegen0 */ +#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_tonegen1 */ +#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_lftonegen0 */ +#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_linear_ramp_i */ +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_linear_ramp_q */ +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_prbs_mag */ +#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for tx_prbs_seed_i */ +#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for tx_prbs_seed_q */ +#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for cmac_dc_cancel */ +#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for cmac_dc_offset */ +#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_corr */ +#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00) + +/* macros for cmac_power */ +#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_cross_corr */ +#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_i2q2 */ +#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_power_hpf */ +#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0) + +/* macros for rxdac_set1 */ +#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000) + +/* macros for rxdac_set2 */ +#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for rxdac_long_shift */ +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00) + +/* macros for cmac_results_i */ +#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for cmac_results_q */ +#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for PMU1 */ +#define PHY_ANALOG_PMU1_ADDRESS 0x00000740 +#define PHY_ANALOG_PMU1_OFFSET 0x00000740 +#define PHY_ANALOG_PMU1_SPARE_MSB 10 +#define PHY_ANALOG_PMU1_SPARE_LSB 0 +#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff +#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000 +#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000 +#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000 +#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for PMU2 */ +#define PHY_ANALOG_PMU2_ADDRESS 0x00000744 +#define PHY_ANALOG_PMU2_OFFSET 0x00000744 +#define PHY_ANALOG_PMU2_SPARE_MSB 7 +#define PHY_ANALOG_PMU2_SPARE_LSB 0 +#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff +#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27 +#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25 +#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000 +#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000 +#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_ares_reg_reg_s { + volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */ + volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */ + volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */ + volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */ + volatile char pad__0[0x30]; /* 0x10 - 0x40 */ + volatile unsigned int TXRF1; /* 0x40 - 0x44 */ + volatile unsigned int TXRF2; /* 0x44 - 0x48 */ + volatile unsigned int TXRF3; /* 0x48 - 0x4c */ + volatile unsigned int TXRF4; /* 0x4c - 0x50 */ + volatile unsigned int TXRF5; /* 0x50 - 0x54 */ + volatile unsigned int TXRF6; /* 0x54 - 0x58 */ + volatile unsigned int TXRF7; /* 0x58 - 0x5c */ + volatile unsigned int TXRF8; /* 0x5c - 0x60 */ + volatile unsigned int TXRF9; /* 0x60 - 0x64 */ + volatile unsigned int TXRF10; /* 0x64 - 0x68 */ + volatile unsigned int TXRF11; /* 0x68 - 0x6c */ + volatile unsigned int TXRF12; /* 0x6c - 0x70 */ + volatile char pad__1[0x10]; /* 0x70 - 0x80 */ + volatile unsigned int SYNTH1; /* 0x80 - 0x84 */ + volatile unsigned int SYNTH2; /* 0x84 - 0x88 */ + volatile unsigned int SYNTH3; /* 0x88 - 0x8c */ + volatile unsigned int SYNTH4; /* 0x8c - 0x90 */ + volatile unsigned int SYNTH5; /* 0x90 - 0x94 */ + volatile unsigned int SYNTH6; /* 0x94 - 0x98 */ + volatile unsigned int SYNTH7; /* 0x98 - 0x9c */ + volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */ + volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */ + volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */ + volatile unsigned int SYNTH11; /* 0xa8 - 0xac */ + volatile unsigned int SYNTH12; /* 0xac - 0xb0 */ + volatile char pad__2[0x10]; /* 0xb0 - 0xc0 */ + volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */ + volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */ + volatile unsigned int BIAS3; /* 0xc8 - 0xcc */ + volatile unsigned int BIAS4; /* 0xcc - 0xd0 */ + volatile char pad__3[0x30]; /* 0xd0 - 0x100 */ + volatile unsigned int RXTX1; /* 0x100 - 0x104 */ + volatile unsigned int RXTX2; /* 0x104 - 0x108 */ + volatile unsigned int RXTX3; /* 0x108 - 0x10c */ + volatile char pad__4[0x34]; /* 0x10c - 0x140 */ + volatile unsigned int BB1; /* 0x140 - 0x144 */ + volatile unsigned int BB2; /* 0x144 - 0x148 */ + volatile char pad__5[0x138]; /* 0x148 - 0x280 */ + volatile unsigned int TOP1; /* 0x280 - 0x284 */ + volatile unsigned int TOP2; /* 0x284 - 0x288 */ + volatile unsigned int TOP3; /* 0x288 - 0x28c */ + volatile unsigned int TOP4; /* 0x28c - 0x290 */ + volatile char pad__6[0xf0]; /* 0x290 - 0x380 */ + volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */ + volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */ + volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */ + volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */ + volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */ + volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */ + volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */ + volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */ + volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */ + volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */ + volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */ + volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */ + volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */ + volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */ + volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */ + volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */ + volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */ + volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */ + volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */ + volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */ + volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */ + volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */ + volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */ + volatile unsigned int PMU1; /* 0x740 - 0x744 */ + volatile unsigned int PMU2; /* 0x744 - 0x748 */ +} analog_intf_ares_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_ARES_REG_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h new file mode 100644 index 000000000000..55ed918fa6ec --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h @@ -0,0 +1,3670 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ +#define _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ + + +/* macros for RXRF_BIAS1 */ +#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_BIAS2 */ +#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1 +#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e +#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070 +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080 +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MSB 10 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_LSB 8 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MASK 0x00000700 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MSB 13 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_LSB 11 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MASK 0x00003800 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MSB 16 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_LSB 14 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MASK 0x0001c000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MSB 19 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_LSB 17 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MASK 0x000e0000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MSB 22 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_LSB 20 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MASK 0x00700000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MSB 25 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_LSB 23 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MASK 0x03800000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000 +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXRF_GAINSTAGES */ +#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001 +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000 +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000 +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28) +#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXRF_AGC */ +#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c +#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MSB 0 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_LSB 0 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MASK 0x00000001 +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MSB 1 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_LSB 1 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MASK 0x00000002 +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MSB 2 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_LSB 2 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MASK 0x00000004 +#define PHY_ANALOG_RXRF_AGC_AGC_OUT_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MSB 3 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_LSB 3 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MASK 0x00000008 +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MSB 4 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_LSB 4 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MASK 0x00000010 +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MSB 5 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_LSB 5 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MASK 0x00000020 +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0 +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00 +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000 +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000 +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000 +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF1 */ +#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040 +#define PHY_ANALOG_TXRF1_OFFSET 0x00000040 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_MSB 0 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_LSB 0 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_MASK 0x00000001 +#define PHY_ANALOG_TXRF1_PDLOBUF5G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF1_PDLOBUF5G_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF1_PDLODIV5G_MSB 1 +#define PHY_ANALOG_TXRF1_PDLODIV5G_LSB 1 +#define PHY_ANALOG_TXRF1_PDLODIV5G_MASK 0x00000002 +#define PHY_ANALOG_TXRF1_PDLODIV5G_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF1_PDLODIV5G_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MSB 2 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_LSB 2 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MASK 0x00000004 +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MSB 3 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_LSB 3 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MASK 0x00000008 +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF1_LODIV5GFORCED_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF1_PADRV2GN5G_MSB 7 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_LSB 4 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_MASK 0x000000f0 +#define PHY_ANALOG_TXRF1_PADRV2GN5G_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_TXRF1_PADRV2GN5G_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_TXRF1_PADRV3GN5G_MSB 11 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_LSB 8 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_MASK 0x00000f00 +#define PHY_ANALOG_TXRF1_PADRV3GN5G_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TXRF1_PADRV3GN5G_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TXRF1_PADRV4GN5G_MSB 15 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_LSB 12 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_MASK 0x0000f000 +#define PHY_ANALOG_TXRF1_PADRV4GN5G_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_TXRF1_PADRV4GN5G_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MSB 16 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_LSB 16 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MASK 0x00010000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 17 +#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 17 +#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00020000 +#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_TXRF1_PDDR2G_MSB 18 +#define PHY_ANALOG_TXRF1_PDDR2G_LSB 18 +#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00040000 +#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 19 +#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 19 +#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00080000 +#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TXRF1_PDLOBUF2G_MSB 20 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_LSB 20 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_MASK 0x00100000 +#define PHY_ANALOG_TXRF1_PDLOBUF2G_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF1_PDLOBUF2G_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF1_PDLODIV2G_MSB 21 +#define PHY_ANALOG_TXRF1_PDLODIV2G_LSB 21 +#define PHY_ANALOG_TXRF1_PDLODIV2G_MASK 0x00200000 +#define PHY_ANALOG_TXRF1_PDLODIV2G_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF1_PDLODIV2G_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000 +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000 +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30 +#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24 +#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000 +#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000 +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF2 */ +#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044 +#define PHY_ANALOG_TXRF2_OFFSET 0x00000044 +#define PHY_ANALOG_TXRF2_D3B5G_MSB 2 +#define PHY_ANALOG_TXRF2_D3B5G_LSB 0 +#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x00000007 +#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF2_D4B5G_MSB 5 +#define PHY_ANALOG_TXRF2_D4B5G_LSB 3 +#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000038 +#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_TXRF2_OCAS2G_MSB 8 +#define PHY_ANALOG_TXRF2_OCAS2G_LSB 6 +#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0x000001c0 +#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_ANALOG_TXRF2_DCAS2G_MSB 11 +#define PHY_ANALOG_TXRF2_DCAS2G_LSB 9 +#define PHY_ANALOG_TXRF2_DCAS2G_MASK 0x00000e00 +#define PHY_ANALOG_TXRF2_DCAS2G_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_TXRF2_DCAS2G_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MSB 14 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_LSB 12 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MASK 0x00007000 +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF2_OB2G_PALOFF_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF2_OB2G_QAM_MSB 17 +#define PHY_ANALOG_TXRF2_OB2G_QAM_LSB 15 +#define PHY_ANALOG_TXRF2_OB2G_QAM_MASK 0x00038000 +#define PHY_ANALOG_TXRF2_OB2G_QAM_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_TXRF2_OB2G_QAM_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_TXRF2_OB2G_PSK_MSB 20 +#define PHY_ANALOG_TXRF2_OB2G_PSK_LSB 18 +#define PHY_ANALOG_TXRF2_OB2G_PSK_MASK 0x001c0000 +#define PHY_ANALOG_TXRF2_OB2G_PSK_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_TXRF2_OB2G_PSK_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_TXRF2_OB2G_CCK_MSB 23 +#define PHY_ANALOG_TXRF2_OB2G_CCK_LSB 21 +#define PHY_ANALOG_TXRF2_OB2G_CCK_MASK 0x00e00000 +#define PHY_ANALOG_TXRF2_OB2G_CCK_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_TXRF2_OB2G_CCK_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_TXRF2_DB2G_MSB 26 +#define PHY_ANALOG_TXRF2_DB2G_LSB 24 +#define PHY_ANALOG_TXRF2_DB2G_MASK 0x07000000 +#define PHY_ANALOG_TXRF2_DB2G_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_TXRF2_DB2G_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 30 +#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 27 +#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x78000000 +#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 31 +#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 31 +#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x80000000 +#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF3 */ +#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048 +#define PHY_ANALOG_TXRF3_OFFSET 0x00000048 +#define PHY_ANALOG_TXRF3_FILTR2G_MSB 1 +#define PHY_ANALOG_TXRF3_FILTR2G_LSB 0 +#define PHY_ANALOG_TXRF3_FILTR2G_MASK 0x00000003 +#define PHY_ANALOG_TXRF3_FILTR2G_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF3_FILTR2G_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF3_PWDFB2_2G_MSB 2 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_LSB 2 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_MASK 0x00000004 +#define PHY_ANALOG_TXRF3_PWDFB2_2G_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF3_PWDFB2_2G_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_TXRF3_PWDFB1_2G_MSB 3 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_LSB 3 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_MASK 0x00000008 +#define PHY_ANALOG_TXRF3_PWDFB1_2G_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF3_PWDFB1_2G_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF3_PDFB2G_MSB 4 +#define PHY_ANALOG_TXRF3_PDFB2G_LSB 4 +#define PHY_ANALOG_TXRF3_PDFB2G_MASK 0x00000010 +#define PHY_ANALOG_TXRF3_PDFB2G_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TXRF3_PDFB2G_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TXRF3_RDIV5G_MSB 6 +#define PHY_ANALOG_TXRF3_RDIV5G_LSB 5 +#define PHY_ANALOG_TXRF3_RDIV5G_MASK 0x00000060 +#define PHY_ANALOG_TXRF3_RDIV5G_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_ANALOG_TXRF3_RDIV5G_SET(x) (((x) << 5) & 0x00000060) +#define PHY_ANALOG_TXRF3_CAPDIV5G_MSB 9 +#define PHY_ANALOG_TXRF3_CAPDIV5G_LSB 7 +#define PHY_ANALOG_TXRF3_CAPDIV5G_MASK 0x00000380 +#define PHY_ANALOG_TXRF3_CAPDIV5G_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_TXRF3_CAPDIV5G_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_TXRF3_PDPREDIST5G_MSB 10 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_LSB 10 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_MASK 0x00000400 +#define PHY_ANALOG_TXRF3_PDPREDIST5G_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_TXRF3_PDPREDIST5G_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_TXRF3_RDIV2G_MSB 12 +#define PHY_ANALOG_TXRF3_RDIV2G_LSB 11 +#define PHY_ANALOG_TXRF3_RDIV2G_MASK 0x00001800 +#define PHY_ANALOG_TXRF3_RDIV2G_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_TXRF3_RDIV2G_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_TXRF3_PDPREDIST2G_MSB 13 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_LSB 13 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_MASK 0x00002000 +#define PHY_ANALOG_TXRF3_PDPREDIST2G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF3_PDPREDIST2G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF3_OCAS5G_MSB 16 +#define PHY_ANALOG_TXRF3_OCAS5G_LSB 14 +#define PHY_ANALOG_TXRF3_OCAS5G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF3_OCAS5G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF3_OCAS5G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF3_D2CAS5G_MSB 19 +#define PHY_ANALOG_TXRF3_D2CAS5G_LSB 17 +#define PHY_ANALOG_TXRF3_D2CAS5G_MASK 0x000e0000 +#define PHY_ANALOG_TXRF3_D2CAS5G_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF3_D2CAS5G_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF3_D3CAS5G_MSB 22 +#define PHY_ANALOG_TXRF3_D3CAS5G_LSB 20 +#define PHY_ANALOG_TXRF3_D3CAS5G_MASK 0x00700000 +#define PHY_ANALOG_TXRF3_D3CAS5G_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF3_D3CAS5G_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF3_D4CAS5G_MSB 25 +#define PHY_ANALOG_TXRF3_D4CAS5G_LSB 23 +#define PHY_ANALOG_TXRF3_D4CAS5G_MASK 0x03800000 +#define PHY_ANALOG_TXRF3_D4CAS5G_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF3_D4CAS5G_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF3_OB5G_MSB 28 +#define PHY_ANALOG_TXRF3_OB5G_LSB 26 +#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF3_D2B5G_MSB 31 +#define PHY_ANALOG_TXRF3_D2B5G_LSB 29 +#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF4 */ +#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c +#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MSB 1 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_LSB 0 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MASK 0x00000003 +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF4_PK1B2G_CCK_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MSB 4 +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_LSB 2 +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MASK 0x0000001c +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF4_MIOB2G_QAM_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MSB 7 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_LSB 5 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MASK 0x000000e0 +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF4_MIOB2G_PSK_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MSB 10 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_LSB 8 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MASK 0x00000700 +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF4_MIOB2G_CCK_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF4_COMP2G_QAM_MSB 13 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_LSB 11 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_MASK 0x00003800 +#define PHY_ANALOG_TXRF4_COMP2G_QAM_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF4_COMP2G_QAM_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 16 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 14 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x0001c000 +#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 19 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 17 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x000e0000 +#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 22 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 20 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x00700000 +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 23 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x03800000 +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 28 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x1c000000 +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 31 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 29 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF5 */ +#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050 +#define PHY_ANALOG_TXRF5_OFFSET 0x00000050 +#define PHY_ANALOG_TXRF5_SPARE5_MSB 0 +#define PHY_ANALOG_TXRF5_SPARE5_LSB 0 +#define PHY_ANALOG_TXRF5_SPARE5_MASK 0x00000001 +#define PHY_ANALOG_TXRF5_SPARE5_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF5_SPARE5_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF5_PAL_LOCKED_MSB 1 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_LSB 1 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_MASK 0x00000002 +#define PHY_ANALOG_TXRF5_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_TXRF5_FBHI2G_MSB 2 +#define PHY_ANALOG_TXRF5_FBHI2G_LSB 2 +#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000004 +#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_TXRF5_FBLO2G_MSB 3 +#define PHY_ANALOG_TXRF5_FBLO2G_LSB 3 +#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000008 +#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MSB 4 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_LSB 4 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MASK 0x00000010 +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TXRF5_NOPALGAIN2G_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TXRF5_ENPACAL2G_MSB 5 +#define PHY_ANALOG_TXRF5_ENPACAL2G_LSB 5 +#define PHY_ANALOG_TXRF5_ENPACAL2G_MASK 0x00000020 +#define PHY_ANALOG_TXRF5_ENPACAL2G_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TXRF5_ENPACAL2G_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TXRF5_OFFSET2G_MSB 12 +#define PHY_ANALOG_TXRF5_OFFSET2G_LSB 6 +#define PHY_ANALOG_TXRF5_OFFSET2G_MASK 0x00001fc0 +#define PHY_ANALOG_TXRF5_OFFSET2G_GET(x) (((x) & 0x00001fc0) >> 6) +#define PHY_ANALOG_TXRF5_OFFSET2G_SET(x) (((x) << 6) & 0x00001fc0) +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MSB 13 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_LSB 13 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MASK 0x00002000 +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TXRF5_REFHI2G_MSB 16 +#define PHY_ANALOG_TXRF5_REFHI2G_LSB 14 +#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF5_REFLO2G_MSB 19 +#define PHY_ANALOG_TXRF5_REFLO2G_LSB 17 +#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000e0000 +#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF5_PALCLAMP2G_MSB 21 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_LSB 20 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_MASK 0x00300000 +#define PHY_ANALOG_TXRF5_PALCLAMP2G_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_TXRF5_PALCLAMP2G_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 23 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 22 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00c00000 +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 25 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 24 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x03000000 +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 27 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 26 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x0c000000 +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 29 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 28 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x30000000 +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 31 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 30 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0xc0000000 +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for TXRF6 */ +#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054 +#define PHY_ANALOG_TXRF6_OFFSET 0x00000054 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MSB 0 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_LSB 0 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MASK 0x00000001 +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_TXRF6_PALCLKGATE2G_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MSB 8 +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_LSB 1 +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MASK 0x000001fe +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MSB 10 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_LSB 9 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MASK 0x00000600 +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_GET(x) (((x) & 0x00000600) >> 9) +#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_SET(x) (((x) << 9) & 0x00000600) +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MSB 11 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_LSB 11 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MASK 0x00000800 +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 14 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 12 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00007000 +#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00007000) >> 12) +#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 12) & 0x00007000) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 15 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 15 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00008000 +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MSB 19 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_LSB 16 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MASK 0x000f0000 +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_TXRF6_CAPDIV_I2G_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 23 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 20 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x00f00000 +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 26 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 24 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x07000000 +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 30 +#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 27 +#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x78000000 +#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 31 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 31 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x80000000 +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for TXRF7 */ +#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058 +#define PHY_ANALOG_TXRF7_OFFSET 0x00000058 +#define PHY_ANALOG_TXRF7_SPARE7_MSB 1 +#define PHY_ANALOG_TXRF7_SPARE7_LSB 0 +#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003 +#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000 +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF8 */ +#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c +#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c +#define PHY_ANALOG_TXRF8_SPARE8_MSB 1 +#define PHY_ANALOG_TXRF8_SPARE8_LSB 0 +#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003 +#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000 +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF9 */ +#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060 +#define PHY_ANALOG_TXRF9_OFFSET 0x00000060 +#define PHY_ANALOG_TXRF9_SPARE9_MSB 1 +#define PHY_ANALOG_TXRF9_SPARE9_LSB 0 +#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003 +#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000 +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for TXRF10 */ +#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064 +#define PHY_ANALOG_TXRF10_OFFSET 0x00000064 +#define PHY_ANALOG_TXRF10_SPARE10_MSB 2 +#define PHY_ANALOG_TXRF10_SPARE10_LSB 0 +#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00000007 +#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 3 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 3 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00000008 +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 6 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 4 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x00000070 +#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x00000070) >> 4) +#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 4) & 0x00000070) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 9 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 7 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x00000380 +#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 16 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 10 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x0001fc00 +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 10) & 0x0001fc00) +#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 19 +#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 17 +#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x000e0000 +#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 20 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 20 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x00100000 +#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 21 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 21 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x00200000 +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MSB 27 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_LSB 22 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MASK 0x0fc00000 +#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MSB 31 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_LSB 28 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MASK 0xf0000000 +#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_GET(x) (((x) & 0xf0000000) >> 28) + +/* macros for TXRF11 */ +#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068 +#define PHY_ANALOG_TXRF11_OFFSET 0x00000068 +#define PHY_ANALOG_TXRF11_SPARE11_MSB 1 +#define PHY_ANALOG_TXRF11_SPARE11_LSB 0 +#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003 +#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 4 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 2 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x0000001c +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 7 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 5 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x000000e0 +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 10 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 8 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00000700 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 13 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 11 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x00003800 +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 16 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 14 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x0001c000 +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MSB 19 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_LSB 17 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MASK 0x000e0000 +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000 +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for TXRF12 */ +#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c +#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c +#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7 +#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0 +#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff +#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 9 +#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8 +#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x00000300 +#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 13 +#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 10 +#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x00003c00 +#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 16 +#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 14 +#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x0001c000 +#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 19 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 17 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x000e0000 +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MSB 22 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_LSB 20 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MASK 0x00700000 +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 25 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 23 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x03800000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 28 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 26 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0x1c000000 +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MSB 31 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_LSB 29 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MASK 0xe0000000 +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH1 */ +#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080 +#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007 +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038 +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040 +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100 +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400 +#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800 +#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000 +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15 +#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13 +#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000 +#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000 +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000 +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000 +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19) +#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000 +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000 +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000 +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000 +#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000 +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28 +#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000 +#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000 +#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30 +#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000 +#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000 +#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH2 */ +#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084 +#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0 +#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f +#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MSB 15 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_LSB 12 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MASK 0x0000f000 +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_LSB 16 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MASK 0x00010000 +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MSB 19 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_LSB 18 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MASK 0x000c0000 +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000 +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000 +#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for SYNTH3 */ +#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088 +#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0 +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000 +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000 +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000 +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000 +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH4 */ +#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c +#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001 +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002 +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2 +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010 +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020 +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MSB 7 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_LSB 6 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH4_SDM_DITHER1_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8 +#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100 +#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200 +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400 +#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12 +#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11 +#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800 +#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11) +#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000 +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000 +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000 +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000 +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000 +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000 +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000 +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000 +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000 +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000 +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000 +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH5 */ +#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090 +#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1 +#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0 +#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003 +#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800 +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000 +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000 +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000 +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27) +#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000) +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MSB 31 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_LSB 30 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MASK 0xc0000000 +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_SYNTH5_SDM_DITHER2_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for SYNTH6 */ +#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094 +#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003 +#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8 +#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2 +#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc +#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2) +#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9 +#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200 +#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10 +#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400 +#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800 +#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000 +#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13 +#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000 +#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14 +#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000 +#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15 +#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000 +#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000 +#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24 +#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000 +#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000 +#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000 +#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000 +#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000 +#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for SYNTH7 */ +#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098 +#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001 +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002 +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18 +#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2 +#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc +#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2) +#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc) +#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27 +#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19 +#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000 +#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19) +#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000 +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000) +#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30 +#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000 +#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000 +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH8 */ +#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c +#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1 +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31 +#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27 +#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH9 */ +#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0 +#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001 +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1 +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31 +#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27 +#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH10 */ +#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4 +#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4 +#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 1 +#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0 +#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000003 +#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 4 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 2 +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000001c +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0 +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700 +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800 +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH11 */ +#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8 +#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8 +#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4 +#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0 +#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f +#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020 +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7 +#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6 +#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300 +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400 +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800 +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000 +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000 +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH12 */ +#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac +#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac +#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 9 +#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0 +#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x000003ff +#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MSB 13 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_LSB 10 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MASK 0x00003c00 +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MSB 14 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_LSB 14 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MASK 0x00004000 +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MSB 16 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_LSB 15 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MASK 0x00018000 +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_GET(x) (((x) & 0x00018000) >> 15) +#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_SET(x) (((x) << 15) & 0x00018000) +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MSB 17 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_LSB 17 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MASK 0x00020000 +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18 +#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000 +#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22 +#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19 +#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000 +#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26 +#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23 +#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000 +#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30 +#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27 +#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000 +#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000 +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for SYNTH13 */ +#define PHY_ANALOG_SYNTH13_ADDRESS 0x000000b0 +#define PHY_ANALOG_SYNTH13_OFFSET 0x000000b0 +#define PHY_ANALOG_SYNTH13_SPARE13A_MSB 0 +#define PHY_ANALOG_SYNTH13_SPARE13A_LSB 0 +#define PHY_ANALOG_SYNTH13_SPARE13A_MASK 0x00000001 +#define PHY_ANALOG_SYNTH13_SPARE13A_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_SYNTH13_SPARE13A_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MSB 3 +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_LSB 1 +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MASK 0x0000000e +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MSB 7 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_LSB 4 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MASK 0x000000f0 +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MSB 11 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_LSB 8 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MASK 0x00000f00 +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MSB 16 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_LSB 12 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MASK 0x0001f000 +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MSB 21 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_LSB 17 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MASK 0x003e0000 +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MSB 26 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_LSB 22 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MASK 0x07c00000 +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_GET(x) (((x) & 0x07c00000) >> 22) +#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_SET(x) (((x) << 22) & 0x07c00000) +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MSB 31 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_LSB 27 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MASK 0xf8000000 +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for SYNTH14 */ +#define PHY_ANALOG_SYNTH14_ADDRESS 0x000000b4 +#define PHY_ANALOG_SYNTH14_OFFSET 0x000000b4 +#define PHY_ANALOG_SYNTH14_SPARE14A_MSB 1 +#define PHY_ANALOG_SYNTH14_SPARE14A_LSB 0 +#define PHY_ANALOG_SYNTH14_SPARE14A_MASK 0x00000003 +#define PHY_ANALOG_SYNTH14_SPARE14A_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_SYNTH14_SPARE14A_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MSB 3 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_LSB 2 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MASK 0x0000000c +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MSB 5 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_LSB 4 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MASK 0x00000030 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MSB 7 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_LSB 6 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MASK 0x000000c0 +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MSB 9 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_LSB 8 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MASK 0x00000300 +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MSB 10 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_LSB 10 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MASK 0x00000400 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MSB 11 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_LSB 11 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MASK 0x00000800 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MSB 12 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_LSB 12 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MASK 0x00001000 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MSB 13 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_LSB 13 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MASK 0x00002000 +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MSB 16 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_LSB 14 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MASK 0x0001c000 +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MSB 19 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_LSB 17 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MASK 0x000e0000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MSB 22 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_LSB 20 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MASK 0x00700000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MSB 25 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_LSB 23 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MASK 0x03800000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MSB 28 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_LSB 26 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MASK 0x1c000000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MSB 31 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_LSB 29 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MASK 0xe0000000 +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS1 */ +#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0 +#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0 +#define PHY_ANALOG_BIAS1_SPARE1_MSB 6 +#define PHY_ANALOG_BIAS1_SPARE1_LSB 0 +#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f +#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380 +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7) +#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00 +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000 +#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000 +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000 +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000 +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31 +#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25 +#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000 +#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25) +#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000) + +/* macros for BIAS2 */ +#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4 +#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4 +#define PHY_ANALOG_BIAS2_SPARE2_MSB 4 +#define PHY_ANALOG_BIAS2_SPARE2_LSB 0 +#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f +#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MSB 7 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_LSB 5 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MASK 0x000000e0 +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS2_PWD_IC25XPA_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700 +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800 +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000 +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MSB 19 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_LSB 17 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MASK 0x000e0000 +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000 +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS3 */ +#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8 +#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8 +#define PHY_ANALOG_BIAS3_SPARE3_MSB 1 +#define PHY_ANALOG_BIAS3_SPARE3_LSB 0 +#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003 +#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MSB 4 +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_LSB 2 +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MASK 0x0000001c +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_ANALOG_BIAS3_PWD_IR25SAR_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0 +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700 +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700) +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MSB 13 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_LSB 11 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MASK 0x00003800 +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000 +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000 +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000 +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000 +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000 +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for BIAS4 */ +#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc +#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc +#define PHY_ANALOG_BIAS4_SPARE4_MSB 10 +#define PHY_ANALOG_BIAS4_SPARE4_LSB 0 +#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x000007ff +#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MSB 13 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_LSB 11 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MASK 0x00003800 +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_GET(x) (((x) & 0x00003800) >> 11) +#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_SET(x) (((x) << 11) & 0x00003800) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000 +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MSB 22 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_LSB 20 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MASK 0x00700000 +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_GET(x) (((x) & 0x00700000) >> 20) +#define PHY_ANALOG_BIAS4_PWD_IR25XPA_SET(x) (((x) << 20) & 0x00700000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000 +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX1 */ +#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100 +#define PHY_ANALOG_RXTX1_OFFSET 0x00000100 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001 +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1 +#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002 +#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2 +#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c +#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2) +#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040 +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00 +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000 +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000 +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18 +#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15 +#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000 +#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15) +#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000 +#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000 +#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23) +#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000) +#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30 +#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27 +#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000 +#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000) +#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31 +#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000 +#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for RXTX2 */ +#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104 +#define PHY_ANALOG_RXTX2_OFFSET 0x00000104 +#define PHY_ANALOG_RXTX2_BMODE_MSB 0 +#define PHY_ANALOG_RXTX2_BMODE_LSB 0 +#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001 +#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1 +#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002 +#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2 +#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004 +#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008 +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX2_BW_ST_MSB 5 +#define PHY_ANALOG_RXTX2_BW_ST_LSB 4 +#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030 +#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040 +#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX2_TXON_MSB 7 +#define PHY_ANALOG_RXTX2_TXON_LSB 7 +#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080 +#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8 +#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX2_PAON_MSB 9 +#define PHY_ANALOG_RXTX2_PAON_LSB 9 +#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200 +#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10 +#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX2_RXON_MSB 11 +#define PHY_ANALOG_RXTX2_RXON_LSB 11 +#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800 +#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12 +#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000 +#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RXTX2_AGCON_MSB 13 +#define PHY_ANALOG_RXTX2_AGCON_LSB 13 +#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000 +#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14 +#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000 +#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RXTX2_TXMOD_MSB 17 +#define PHY_ANALOG_RXTX2_TXMOD_LSB 15 +#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000 +#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15) +#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000 +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000 +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25 +#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24 +#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000 +#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28 +#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26 +#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000 +#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000) +#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31 +#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29 +#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000 +#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for RXTX3 */ +#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108 +#define PHY_ANALOG_RXTX3_OFFSET 0x00000108 +#define PHY_ANALOG_RXTX3_SPARE3_MSB 2 +#define PHY_ANALOG_RXTX3_SPARE3_LSB 0 +#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007 +#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_RXTX3_SPURON_MSB 3 +#define PHY_ANALOG_RXTX3_SPURON_LSB 3 +#define PHY_ANALOG_RXTX3_SPURON_MASK 0x00000008 +#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MSB 4 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_LSB 4 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MASK 0x00000010 +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 5 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 5 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000020 +#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6 +#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040 +#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RXTX3_DACPWD_MSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_LSB 7 +#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080 +#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100 +#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9 +#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200 +#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400 +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800 +#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17 +#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000 +#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000 +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19 +#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000 +#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20 +#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000 +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_RXTX3_CALFC_MSB 22 +#define PHY_ANALOG_RXTX3_CALFC_LSB 22 +#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000 +#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23 +#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000 +#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_RXTX3_CALTX_MSB 24 +#define PHY_ANALOG_RXTX3_CALTX_LSB 24 +#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000 +#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25 +#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000 +#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000 +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_RXTX3_CALPA_MSB 28 +#define PHY_ANALOG_RXTX3_CALPA_LSB 28 +#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000 +#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29 +#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000 +#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_RXTX3_TURBOADC_MSB 30 +#define PHY_ANALOG_RXTX3_TURBOADC_LSB 30 +#define PHY_ANALOG_RXTX3_TURBOADC_MASK 0x40000000 +#define PHY_ANALOG_RXTX3_TURBOADC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_RXTX3_TURBOADC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MSB 31 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_LSB 31 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MASK 0x80000000 +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_RXTX3_TURBOADC_OVR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB1 */ +#define PHY_ANALOG_BB1_ADDRESS 0x00000140 +#define PHY_ANALOG_BB1_OFFSET 0x00000140 +#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0 +#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001 +#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1 +#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002 +#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2 +#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004 +#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008 +#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4 +#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010 +#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020 +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040 +#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080 +#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8 +#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100 +#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9 +#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200 +#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10 +#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400 +#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11 +#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800 +#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12 +#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000 +#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_BB1_CMSEL_MSB 15 +#define PHY_ANALOG_BB1_CMSEL_LSB 13 +#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000 +#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_ANALOG_BB1_ATBSEL_MSB 17 +#define PHY_ANALOG_BB1_ATBSEL_LSB 16 +#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000 +#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000 +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000 +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19) +#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000 +#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29 +#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000 +#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31 +#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30 +#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000 +#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB2 */ +#define PHY_ANALOG_BB2_ADDRESS 0x00000144 +#define PHY_ANALOG_BB2_OFFSET 0x00000144 +#define PHY_ANALOG_BB2_SPARE_MSB 3 +#define PHY_ANALOG_BB2_SPARE_LSB 0 +#define PHY_ANALOG_BB2_SPARE_MASK 0x0000000f +#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MSB 7 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_LSB 4 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MASK 0x000000f0 +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_ANALOG_BB2_SEL_TEST_MSB 9 +#define PHY_ANALOG_BB2_SEL_TEST_LSB 8 +#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000300 +#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 8) & 0x00000300) +#define PHY_ANALOG_BB2_RCFILTER_CAP_MSB 14 +#define PHY_ANALOG_BB2_RCFILTER_CAP_LSB 10 +#define PHY_ANALOG_BB2_RCFILTER_CAP_MASK 0x00007c00 +#define PHY_ANALOG_BB2_RCFILTER_CAP_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_ANALOG_BB2_RCFILTER_CAP_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_LSB 15 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MASK 0x00008000 +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_BB2_FNOTCH_MSB 19 +#define PHY_ANALOG_BB2_FNOTCH_LSB 16 +#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000 +#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000 +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_BB2_FILTERFC_MSB 25 +#define PHY_ANALOG_BB2_FILTERFC_LSB 21 +#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000 +#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000 +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000 +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000 +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000 +#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000 +#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000 +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB3 */ +#define PHY_ANALOG_BB3_ADDRESS 0x00000148 +#define PHY_ANALOG_BB3_OFFSET 0x00000148 +#define PHY_ANALOG_BB3_SPARE_MSB 15 +#define PHY_ANALOG_BB3_SPARE_LSB 0 +#define PHY_ANALOG_BB3_SPARE_MASK 0x0000ffff +#define PHY_ANALOG_BB3_SPARE_GET(x) (((x) & 0x0000ffff) >> 0) +#define PHY_ANALOG_BB3_SPARE_SET(x) (((x) << 0) & 0x0000ffff) +#define PHY_ANALOG_BB3_FILTERFC_MSB 20 +#define PHY_ANALOG_BB3_FILTERFC_LSB 16 +#define PHY_ANALOG_BB3_FILTERFC_MASK 0x001f0000 +#define PHY_ANALOG_BB3_FILTERFC_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MSB 25 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_LSB 21 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MASK 0x03e00000 +#define PHY_ANALOG_BB3_OFSTCORRI2VQ_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_ANALOG_BB3_OFSTCORRI2VI_MSB 30 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_LSB 26 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_MASK 0x7c000000 +#define PHY_ANALOG_BB3_OFSTCORRI2VI_GET(x) (((x) & 0x7c000000) >> 26) +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MSB 31 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_LSB 31 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MASK 0x80000000 +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for PLLCLKMODA */ +#define PHY_ANALOG_PLLCLKMODA_ADDRESS 0x00000280 +#define PHY_ANALOG_PLLCLKMODA_OFFSET 0x00000280 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MSB 0 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_LSB 0 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MASK 0x00000001 +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MSB 1 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_LSB 1 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MASK 0x00000002 +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_PLLCLKMODA_PWDPLL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MSB 16 +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_LSB 2 +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MASK 0x0001fffc +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_GET(x) (((x) & 0x0001fffc) >> 2) +#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_SET(x) (((x) << 2) & 0x0001fffc) +#define PHY_ANALOG_PLLCLKMODA_REFDIV_MSB 20 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_LSB 17 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_MASK 0x001e0000 +#define PHY_ANALOG_PLLCLKMODA_REFDIV_GET(x) (((x) & 0x001e0000) >> 17) +#define PHY_ANALOG_PLLCLKMODA_REFDIV_SET(x) (((x) << 17) & 0x001e0000) +#define PHY_ANALOG_PLLCLKMODA_DIV_MSB 30 +#define PHY_ANALOG_PLLCLKMODA_DIV_LSB 21 +#define PHY_ANALOG_PLLCLKMODA_DIV_MASK 0x7fe00000 +#define PHY_ANALOG_PLLCLKMODA_DIV_GET(x) (((x) & 0x7fe00000) >> 21) +#define PHY_ANALOG_PLLCLKMODA_DIV_SET(x) (((x) << 21) & 0x7fe00000) +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MSB 31 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_LSB 31 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MASK 0x80000000 +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for PLLCLKMODA2 */ +#define PHY_ANALOG_PLLCLKMODA2_ADDRESS 0x00000284 +#define PHY_ANALOG_PLLCLKMODA2_OFFSET 0x00000284 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_MSB 3 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_LSB 0 +#define PHY_ANALOG_PLLCLKMODA2_SPARE_MASK 0x0000000f +#define PHY_ANALOG_PLLCLKMODA2_SPARE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_PLLCLKMODA2_SPARE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MSB 4 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_LSB 4 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MASK 0x00000010 +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_PLLCLKMODA2_DACPWD_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MSB 5 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_LSB 5 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MASK 0x00000020 +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MSB 6 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_LSB 6 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MASK 0x00000040 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MSB 8 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_LSB 7 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MASK 0x00000180 +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_GET(x) (((x) & 0x00000180) >> 7) +#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_SET(x) (((x) << 7) & 0x00000180) +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MSB 12 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_LSB 9 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MASK 0x00001e00 +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_GET(x) (((x) & 0x00001e00) >> 9) +#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_SET(x) (((x) << 9) & 0x00001e00) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MSB 13 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_LSB 13 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MASK 0x00002000 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MSB 14 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_LSB 14 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MASK 0x00004000 +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MSB 15 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_LSB 15 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MASK 0x00008000 +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MSB 17 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_LSB 16 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MASK 0x00030000 +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_ANALOG_PLLCLKMODA2_PLLATB_SET(x) (((x) << 16) & 0x00030000) +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MSB 18 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_LSB 18 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MASK 0x00040000 +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MSB 19 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_LSB 19 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MASK 0x00080000 +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MSB 20 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_LSB 20 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MASK 0x00100000 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MSB 21 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_LSB 21 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MASK 0x00200000 +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MSB 23 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_LSB 22 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MASK 0x00c00000 +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MSB 26 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_LSB 24 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MASK 0x07000000 +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_ANALOG_PLLCLKMODA2_PLLICP_SET(x) (((x) << 24) & 0x07000000) +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MSB 31 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_LSB 27 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MASK 0xf8000000 +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for TOP */ +#define PHY_ANALOG_TOP_ADDRESS 0x00000288 +#define PHY_ANALOG_TOP_OFFSET 0x00000288 +#define PHY_ANALOG_TOP_SPARE_MSB 2 +#define PHY_ANALOG_TOP_SPARE_LSB 0 +#define PHY_ANALOG_TOP_SPARE_MASK 0x00000007 +#define PHY_ANALOG_TOP_SPARE_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_TOP_SPARE_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_TOP_PWDBIAS_MSB 3 +#define PHY_ANALOG_TOP_PWDBIAS_LSB 3 +#define PHY_ANALOG_TOP_PWDBIAS_MASK 0x00000008 +#define PHY_ANALOG_TOP_PWDBIAS_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_TOP_PWDBIAS_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_TOP_FLIP_XPABIAS_MSB 4 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_LSB 4 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_MASK 0x00000010 +#define PHY_ANALOG_TOP_FLIP_XPABIAS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_TOP_FLIP_XPABIAS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_TOP_XPAON2_MSB 5 +#define PHY_ANALOG_TOP_XPAON2_LSB 5 +#define PHY_ANALOG_TOP_XPAON2_MASK 0x00000020 +#define PHY_ANALOG_TOP_XPAON2_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_TOP_XPAON2_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_TOP_XPAON5_MSB 6 +#define PHY_ANALOG_TOP_XPAON5_LSB 6 +#define PHY_ANALOG_TOP_XPAON5_MASK 0x00000040 +#define PHY_ANALOG_TOP_XPAON5_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_TOP_XPAON5_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_TOP_XPASHORT2GND_MSB 7 +#define PHY_ANALOG_TOP_XPASHORT2GND_LSB 7 +#define PHY_ANALOG_TOP_XPASHORT2GND_MASK 0x00000080 +#define PHY_ANALOG_TOP_XPASHORT2GND_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_TOP_XPASHORT2GND_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_TOP_XPABIASLVL_MSB 11 +#define PHY_ANALOG_TOP_XPABIASLVL_LSB 8 +#define PHY_ANALOG_TOP_XPABIASLVL_MASK 0x00000f00 +#define PHY_ANALOG_TOP_XPABIASLVL_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TOP_XPABIASLVL_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TOP_XPABIAS_EN_MSB 12 +#define PHY_ANALOG_TOP_XPABIAS_EN_LSB 12 +#define PHY_ANALOG_TOP_XPABIAS_EN_MASK 0x00001000 +#define PHY_ANALOG_TOP_XPABIAS_EN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_TOP_XPABIAS_EN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_TOP_ATBSELECT_MSB 13 +#define PHY_ANALOG_TOP_ATBSELECT_LSB 13 +#define PHY_ANALOG_TOP_ATBSELECT_MASK 0x00002000 +#define PHY_ANALOG_TOP_ATBSELECT_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_TOP_ATBSELECT_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_TOP_LOCAL_XPA_MSB 14 +#define PHY_ANALOG_TOP_LOCAL_XPA_LSB 14 +#define PHY_ANALOG_TOP_LOCAL_XPA_MASK 0x00004000 +#define PHY_ANALOG_TOP_LOCAL_XPA_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_TOP_LOCAL_XPA_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MSB 15 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_LSB 15 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MASK 0x00008000 +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_TOP_XPABIAS_BYPASS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_TOP_TEST_PADQ_EN_MSB 16 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_LSB 16 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_MASK 0x00010000 +#define PHY_ANALOG_TOP_TEST_PADQ_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_TOP_TEST_PADQ_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_TOP_TEST_PADI_EN_MSB 17 +#define PHY_ANALOG_TOP_TEST_PADI_EN_LSB 17 +#define PHY_ANALOG_TOP_TEST_PADI_EN_MASK 0x00020000 +#define PHY_ANALOG_TOP_TEST_PADI_EN_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_TOP_TEST_PADI_EN_SET(x) (((x) << 17) & 0x00020000) +#define PHY_ANALOG_TOP_TESTIQ_RSEL_MSB 18 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_LSB 18 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_MASK 0x00040000 +#define PHY_ANALOG_TOP_TESTIQ_RSEL_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_ANALOG_TOP_TESTIQ_RSEL_SET(x) (((x) << 18) & 0x00040000) +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MSB 19 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_LSB 19 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MASK 0x00080000 +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_TOP_TESTIQ_BUFEN_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_TOP_PAD2GND_MSB 20 +#define PHY_ANALOG_TOP_PAD2GND_LSB 20 +#define PHY_ANALOG_TOP_PAD2GND_MASK 0x00100000 +#define PHY_ANALOG_TOP_PAD2GND_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_ANALOG_TOP_PAD2GND_SET(x) (((x) << 20) & 0x00100000) +#define PHY_ANALOG_TOP_INTH2PAD_MSB 21 +#define PHY_ANALOG_TOP_INTH2PAD_LSB 21 +#define PHY_ANALOG_TOP_INTH2PAD_MASK 0x00200000 +#define PHY_ANALOG_TOP_INTH2PAD_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_ANALOG_TOP_INTH2PAD_SET(x) (((x) << 21) & 0x00200000) +#define PHY_ANALOG_TOP_INTH2GND_MSB 22 +#define PHY_ANALOG_TOP_INTH2GND_LSB 22 +#define PHY_ANALOG_TOP_INTH2GND_MASK 0x00400000 +#define PHY_ANALOG_TOP_INTH2GND_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_TOP_INTH2GND_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_TOP_INT2PAD_MSB 23 +#define PHY_ANALOG_TOP_INT2PAD_LSB 23 +#define PHY_ANALOG_TOP_INT2PAD_MASK 0x00800000 +#define PHY_ANALOG_TOP_INT2PAD_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_TOP_INT2PAD_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_TOP_INT2GND_MSB 24 +#define PHY_ANALOG_TOP_INT2GND_LSB 24 +#define PHY_ANALOG_TOP_INT2GND_MASK 0x01000000 +#define PHY_ANALOG_TOP_INT2GND_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_TOP_INT2GND_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_TOP_PWDPALCLK_MSB 25 +#define PHY_ANALOG_TOP_PWDPALCLK_LSB 25 +#define PHY_ANALOG_TOP_PWDPALCLK_MASK 0x02000000 +#define PHY_ANALOG_TOP_PWDPALCLK_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_ANALOG_TOP_PWDPALCLK_SET(x) (((x) << 25) & 0x02000000) +#define PHY_ANALOG_TOP_INV_CLK320_ADC_MSB 26 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_LSB 26 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_MASK 0x04000000 +#define PHY_ANALOG_TOP_INV_CLK320_ADC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_ANALOG_TOP_INV_CLK320_ADC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_ANALOG_TOP_FLIP_REFCLK40_MSB 27 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_LSB 27 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_MASK 0x08000000 +#define PHY_ANALOG_TOP_FLIP_REFCLK40_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_TOP_FLIP_REFCLK40_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MSB 28 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_LSB 28 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MASK 0x10000000 +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_TOP_FLIP_PLLCLK320_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MSB 29 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_LSB 29 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MASK 0x20000000 +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_TOP_FLIP_PLLCLK160_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_TOP_CLK_SEL_MSB 31 +#define PHY_ANALOG_TOP_CLK_SEL_LSB 30 +#define PHY_ANALOG_TOP_CLK_SEL_MASK 0xc0000000 +#define PHY_ANALOG_TOP_CLK_SEL_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_ANALOG_TOP_CLK_SEL_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for THERM */ +#define PHY_ANALOG_THERM_ADDRESS 0x0000028c +#define PHY_ANALOG_THERM_OFFSET 0x0000028c +#define PHY_ANALOG_THERM_LOREG_LVL_MSB 2 +#define PHY_ANALOG_THERM_LOREG_LVL_LSB 0 +#define PHY_ANALOG_THERM_LOREG_LVL_MASK 0x00000007 +#define PHY_ANALOG_THERM_LOREG_LVL_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_ANALOG_THERM_LOREG_LVL_SET(x) (((x) << 0) & 0x00000007) +#define PHY_ANALOG_THERM_RFREG_LVL_MSB 5 +#define PHY_ANALOG_THERM_RFREG_LVL_LSB 3 +#define PHY_ANALOG_THERM_RFREG_LVL_MASK 0x00000038 +#define PHY_ANALOG_THERM_RFREG_LVL_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_ANALOG_THERM_RFREG_LVL_SET(x) (((x) << 3) & 0x00000038) +#define PHY_ANALOG_THERM_SAR_ADC_DONE_MSB 6 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_LSB 6 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_MASK 0x00000040 +#define PHY_ANALOG_THERM_SAR_ADC_DONE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_THERM_SAR_ADC_OUT_MSB 14 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_LSB 7 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_MASK 0x00007f80 +#define PHY_ANALOG_THERM_SAR_ADC_OUT_GET(x) (((x) & 0x00007f80) >> 7) +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MSB 22 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_LSB 15 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MASK 0x007f8000 +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_GET(x) (((x) & 0x007f8000) >> 15) +#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_SET(x) (((x) << 15) & 0x007f8000) +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MSB 23 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_LSB 23 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MASK 0x00800000 +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_ANALOG_THERM_SAR_DACTEST_EN_SET(x) (((x) << 23) & 0x00800000) +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MSB 24 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_LSB 24 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MASK 0x01000000 +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_ANALOG_THERM_THERMSEL_MSB 26 +#define PHY_ANALOG_THERM_THERMSEL_LSB 25 +#define PHY_ANALOG_THERM_THERMSEL_MASK 0x06000000 +#define PHY_ANALOG_THERM_THERMSEL_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_ANALOG_THERM_THERMSEL_SET(x) (((x) << 25) & 0x06000000) +#define PHY_ANALOG_THERM_SAR_SLOW_EN_MSB 27 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_LSB 27 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_MASK 0x08000000 +#define PHY_ANALOG_THERM_SAR_SLOW_EN_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_ANALOG_THERM_SAR_SLOW_EN_SET(x) (((x) << 27) & 0x08000000) +#define PHY_ANALOG_THERM_THERMSTART_MSB 28 +#define PHY_ANALOG_THERM_THERMSTART_LSB 28 +#define PHY_ANALOG_THERM_THERMSTART_MASK 0x10000000 +#define PHY_ANALOG_THERM_THERMSTART_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_THERM_THERMSTART_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MSB 29 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_LSB 29 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MASK 0x20000000 +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_ANALOG_THERM_THERMON_MSB 30 +#define PHY_ANALOG_THERM_THERMON_LSB 30 +#define PHY_ANALOG_THERM_THERMON_MASK 0x40000000 +#define PHY_ANALOG_THERM_THERMON_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_THERM_THERMON_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_THERM_LOCAL_THERM_MSB 31 +#define PHY_ANALOG_THERM_LOCAL_THERM_LSB 31 +#define PHY_ANALOG_THERM_LOCAL_THERM_MASK 0x80000000 +#define PHY_ANALOG_THERM_LOCAL_THERM_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_THERM_LOCAL_THERM_SET(x) (((x) << 31) & 0x80000000) + +/* macros for XTAL */ +#define PHY_ANALOG_XTAL_ADDRESS 0x00000290 +#define PHY_ANALOG_XTAL_OFFSET 0x00000290 +#define PHY_ANALOG_XTAL_SPARE_MSB 5 +#define PHY_ANALOG_XTAL_SPARE_LSB 0 +#define PHY_ANALOG_XTAL_SPARE_MASK 0x0000003f +#define PHY_ANALOG_XTAL_SPARE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_ANALOG_XTAL_SPARE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MSB 6 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_LSB 6 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MASK 0x00000040 +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_XTAL_LOCALBIAS2X_MSB 7 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_LSB 7 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_MASK 0x00000080 +#define PHY_ANALOG_XTAL_LOCALBIAS2X_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_XTAL_LOCALBIAS2X_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_XTAL_LOCAL_XTAL_MSB 8 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_LSB 8 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_MASK 0x00000100 +#define PHY_ANALOG_XTAL_LOCAL_XTAL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_XTAL_LOCAL_XTAL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MSB 9 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_LSB 9 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MASK 0x00000200 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_XTAL_XTAL_OSCON_MSB 10 +#define PHY_ANALOG_XTAL_XTAL_OSCON_LSB 10 +#define PHY_ANALOG_XTAL_XTAL_OSCON_MASK 0x00000400 +#define PHY_ANALOG_XTAL_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_XTAL_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MSB 11 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_LSB 11 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MASK 0x00000800 +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MSB 12 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_LSB 12 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MASK 0x00001000 +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MSB 13 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_LSB 13 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MASK 0x00002000 +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MSB 15 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_LSB 14 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MASK 0x0000c000 +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_ANALOG_XTAL_XTAL_DRVSTR_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MSB 22 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_LSB 16 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MASK 0x007f0000 +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MSB 29 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_LSB 23 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MASK 0x3f800000 +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MSB 30 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_LSB 30 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MASK 0x40000000 +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_ANALOG_XTAL_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000) +#define PHY_ANALOG_XTAL_TCXODET_MSB 31 +#define PHY_ANALOG_XTAL_TCXODET_LSB 31 +#define PHY_ANALOG_XTAL_TCXODET_MASK 0x80000000 +#define PHY_ANALOG_XTAL_TCXODET_GET(x) (((x) & 0x80000000) >> 31) + +/* macros for rbist_cntrl */ +#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080 +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000 +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000) + +/* macros for tx_dc_offset */ +#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000 +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000) + +/* macros for tx_tonegen0 */ +#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_tonegen1 */ +#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_lftonegen0 */ +#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000 +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for tx_linear_ramp_i */ +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_linear_ramp_q */ +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000 +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for tx_prbs_mag */ +#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000 +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for tx_prbs_seed_i */ +#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for tx_prbs_seed_q */ +#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0 +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0) +#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff) + +/* macros for cmac_dc_cancel */ +#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000 +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for cmac_dc_offset */ +#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_corr */ +#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00 +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00) + +/* macros for cmac_power */ +#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_cross_corr */ +#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_i2q2 */ +#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f) + +/* macros for cmac_power_hpf */ +#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0 +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0) + +/* macros for rxdac_set1 */ +#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000 +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000) + +/* macros for rxdac_set2 */ +#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000 +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for rxdac_long_shift */ +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00 +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00) + +/* macros for cmac_results_i */ +#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for cmac_results_q */ +#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0 +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for PMU1 */ +#define PHY_ANALOG_PMU1_ADDRESS 0x00000740 +#define PHY_ANALOG_PMU1_OFFSET 0x00000740 +#define PHY_ANALOG_PMU1_SPARE_MSB 10 +#define PHY_ANALOG_PMU1_SPARE_LSB 0 +#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff +#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800 +#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12 +#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000 +#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14 +#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000 +#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000 +#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16 +#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000 +#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000 +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000 +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000 +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000 +#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000 +#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28 +#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000 +#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000 +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29) +#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000) + +/* macros for PMU2 */ +#define PHY_ANALOG_PMU2_ADDRESS 0x00000744 +#define PHY_ANALOG_PMU2_OFFSET 0x00000744 +#define PHY_ANALOG_PMU2_SPARE_MSB 7 +#define PHY_ANALOG_PMU2_SPARE_LSB 0 +#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff +#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100 +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200 +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400 +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800 +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000 +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000 +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000 +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000 +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000 +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000 +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17) +#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000 +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000 +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000 +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000 +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23) +#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000) +#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27 +#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25 +#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000 +#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28 +#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000 +#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000 +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000 +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000) + + +#ifndef __ASSEMBLER__ + +typedef struct analog_intf_athr_wlan_reg_reg_s { + volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */ + volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */ + volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */ + volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */ + volatile char pad__0[0x30]; /* 0x10 - 0x40 */ + volatile unsigned int TXRF1; /* 0x40 - 0x44 */ + volatile unsigned int TXRF2; /* 0x44 - 0x48 */ + volatile unsigned int TXRF3; /* 0x48 - 0x4c */ + volatile unsigned int TXRF4; /* 0x4c - 0x50 */ + volatile unsigned int TXRF5; /* 0x50 - 0x54 */ + volatile unsigned int TXRF6; /* 0x54 - 0x58 */ + volatile unsigned int TXRF7; /* 0x58 - 0x5c */ + volatile unsigned int TXRF8; /* 0x5c - 0x60 */ + volatile unsigned int TXRF9; /* 0x60 - 0x64 */ + volatile unsigned int TXRF10; /* 0x64 - 0x68 */ + volatile unsigned int TXRF11; /* 0x68 - 0x6c */ + volatile unsigned int TXRF12; /* 0x6c - 0x70 */ + volatile char pad__1[0x10]; /* 0x70 - 0x80 */ + volatile unsigned int SYNTH1; /* 0x80 - 0x84 */ + volatile unsigned int SYNTH2; /* 0x84 - 0x88 */ + volatile unsigned int SYNTH3; /* 0x88 - 0x8c */ + volatile unsigned int SYNTH4; /* 0x8c - 0x90 */ + volatile unsigned int SYNTH5; /* 0x90 - 0x94 */ + volatile unsigned int SYNTH6; /* 0x94 - 0x98 */ + volatile unsigned int SYNTH7; /* 0x98 - 0x9c */ + volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */ + volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */ + volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */ + volatile unsigned int SYNTH11; /* 0xa8 - 0xac */ + volatile unsigned int SYNTH12; /* 0xac - 0xb0 */ + volatile unsigned int SYNTH13; /* 0xb0 - 0xb4 */ + volatile unsigned int SYNTH14; /* 0xb4 - 0xb8 */ + volatile char pad__2[0x8]; /* 0xb8 - 0xc0 */ + volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */ + volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */ + volatile unsigned int BIAS3; /* 0xc8 - 0xcc */ + volatile unsigned int BIAS4; /* 0xcc - 0xd0 */ + volatile char pad__3[0x30]; /* 0xd0 - 0x100 */ + volatile unsigned int RXTX1; /* 0x100 - 0x104 */ + volatile unsigned int RXTX2; /* 0x104 - 0x108 */ + volatile unsigned int RXTX3; /* 0x108 - 0x10c */ + volatile char pad__4[0x34]; /* 0x10c - 0x140 */ + volatile unsigned int BB1; /* 0x140 - 0x144 */ + volatile unsigned int BB2; /* 0x144 - 0x148 */ + volatile unsigned int BB3; /* 0x148 - 0x14c */ + volatile char pad__5[0x134]; /* 0x14c - 0x280 */ + volatile unsigned int PLLCLKMODA; /* 0x280 - 0x284 */ + volatile unsigned int PLLCLKMODA2; /* 0x284 - 0x288 */ + volatile unsigned int TOP; /* 0x288 - 0x28c */ + volatile unsigned int THERM; /* 0x28c - 0x290 */ + volatile unsigned int XTAL; /* 0x290 - 0x294 */ + volatile char pad__6[0xec]; /* 0x294 - 0x380 */ + volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */ + volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */ + volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */ + volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */ + volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */ + volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */ + volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */ + volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */ + volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */ + volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */ + volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */ + volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */ + volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */ + volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */ + volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */ + volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */ + volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */ + volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */ + volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */ + volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */ + volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */ + volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */ + volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */ + volatile unsigned int PMU1; /* 0x740 - 0x744 */ + volatile unsigned int PMU2; /* 0x744 - 0x748 */ +} analog_intf_athr_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h new file mode 100644 index 000000000000..7e6320d28ac6 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/analog_intf_reg.h @@ -0,0 +1,33 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "analog_intf_athr_wlan_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h new file mode 100644 index 000000000000..143460719bbf --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h @@ -0,0 +1,36 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _APB_ATHR_WLAN_MAP_H_ +#define _APB_ATHR_WLAN_MAP_H_ + +#define WLAN_RTC_BASE_ADDRESS 0x00004000 +#define WLAN_VMC_BASE_ADDRESS 0x00008000 +#define WLAN_UART_BASE_ADDRESS 0x0000c000 +#define WLAN_DBG_UART_BASE_ADDRESS 0x0000d000 +#define WLAN_UMBOX_BASE_ADDRESS 0x0000e000 +#define WLAN_SI_BASE_ADDRESS 0x00010000 +#define WLAN_GPIO_BASE_ADDRESS 0x00014000 +#define WLAN_MBOX_BASE_ADDRESS 0x00018000 +#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 +#define WLAN_MAC_BASE_ADDRESS 0x00020000 +#define WLAN_RDMA_BASE_ADDRESS 0x00030100 +#define EFUSE_BASE_ADDRESS 0x00031000 + +#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h new file mode 100644 index 000000000000..6c85e2643d24 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/apb_map.h @@ -0,0 +1,44 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "apb_athr_wlan_map.h" + + +#ifndef BT_HEADERS + +#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS +#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS +#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS +#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS +#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS +#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS +#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS +#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS +#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS +#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS +#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS + + +#endif +#endif + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h new file mode 100644 index 000000000000..61827bc79cba --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/bb_lc_reg.h @@ -0,0 +1,7072 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + +/* Copyright (C) 2009 Denali Software Inc. All rights reserved */ +/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */ + + +#ifndef _BB_LC_REG_REG_H_ +#define _BB_LC_REG_REG_H_ + + +/* macros for BB_test_controls */ +#define PHY_BB_TEST_CONTROLS_ADDRESS 0x00009800 +#define PHY_BB_TEST_CONTROLS_OFFSET 0x00009800 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB 3 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB 0 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK 0x0000000f +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB 4 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB 4 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK 0x00000010 +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB 6 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB 5 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK 0x00000060 +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x) (((x) << 5) & 0x00000060) +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB 9 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB 8 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK 0x00000300 +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB 10 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB 10 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK 0x00000400 +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB 13 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB 13 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK 0x00002000 +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB 15 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB 15 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK 0x00008000 +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB 17 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB 17 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK 0x00020000 +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB 18 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB 18 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK 0x00040000 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB 22 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB 19 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK 0x00780000 +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x) (((x) << 19) & 0x00780000) +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB 23 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB 23 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK 0x00800000 +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB 24 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB 24 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK 0x01000000 +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB 28 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB 28 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK 0x10000000 +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB 31 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB 30 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK 0xc0000000 +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_gen_controls */ +#define PHY_BB_GEN_CONTROLS_ADDRESS 0x00009804 +#define PHY_BB_GEN_CONTROLS_OFFSET 0x00009804 +#define PHY_BB_GEN_CONTROLS_TURBO_MSB 0 +#define PHY_BB_GEN_CONTROLS_TURBO_LSB 0 +#define PHY_BB_GEN_CONTROLS_TURBO_MASK 0x00000001 +#define PHY_BB_GEN_CONTROLS_TURBO_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_GEN_CONTROLS_TURBO_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MSB 1 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_LSB 1 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MASK 0x00000002 +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_GEN_CONTROLS_CF_SHORT20_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_MSB 2 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_LSB 2 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_MASK 0x00000004 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MSB 3 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_LSB 3 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MASK 0x00000008 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MSB 4 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_LSB 4 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MASK 0x00000010 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MSB 5 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_LSB 5 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MASK 0x00000020 +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MSB 6 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_LSB 6 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MASK 0x00000040 +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_GEN_CONTROLS_HT_ENABLE_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB 7 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB 7 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK 0x00000080 +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MSB 8 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_LSB 8 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MASK 0x00000100 +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MSB 9 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_LSB 9 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MASK 0x00000200 +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB 10 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB 10 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK 0x00000400 +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MSB 11 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_LSB 11 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MASK 0x00000800 +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_SET(x) (((x) << 11) & 0x00000800) + +/* macros for BB_test_controls_status */ +#define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS 0x00009808 +#define PHY_BB_TEST_CONTROLS_STATUS_OFFSET 0x00009808 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB 0 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB 0 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK 0x00000001 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB 1 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB 1 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK 0x00000002 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB 4 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB 2 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK 0x0000001c +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x) (((x) & 0x0000001c) >> 2) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x) (((x) << 2) & 0x0000001c) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB 6 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB 5 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK 0x00000060 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x) (((x) & 0x00000060) >> 5) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x) (((x) << 5) & 0x00000060) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB 7 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB 7 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK 0x00000080 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB 8 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB 8 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK 0x00000100 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB 9 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB 9 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK 0x00000200 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB 13 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB 10 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK 0x00003c00 +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB 14 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB 14 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK 0x00004000 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB 15 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB 15 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK 0x00008000 +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB 18 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB 16 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK 0x00070000 +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB 19 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB 19 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK 0x00080000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB 23 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB 23 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK 0x00800000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB 27 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB 27 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK 0x08000000 +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB 28 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB 28 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK 0x10000000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB 30 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB 29 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK 0x60000000 +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x) (((x) << 29) & 0x60000000) + +/* macros for BB_timing_controls_1 */ +#define PHY_BB_TIMING_CONTROLS_1_ADDRESS 0x0000980c +#define PHY_BB_TIMING_CONTROLS_1_OFFSET 0x0000980c +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB 6 +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB 0 +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK 0x0000007f +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB 12 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB 7 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK 0x00001f80 +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x) (((x) & 0x00001f80) >> 7) +#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x) (((x) << 7) & 0x00001f80) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MSB 16 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_LSB 13 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MASK 0x0001e000 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_GET(x) (((x) & 0x0001e000) >> 13) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_SET(x) (((x) << 13) & 0x0001e000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MSB 17 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_LSB 17 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MASK 0x00020000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB 19 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB 18 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK 0x000c0000 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB 21 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB 20 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK 0x00300000 +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x) (((x) << 20) & 0x00300000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB 22 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB 22 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK 0x00400000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB 23 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB 23 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK 0x00800000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB 24 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB 24 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK 0x01000000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB 26 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB 25 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK 0x06000000 +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB 27 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB 27 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK 0x08000000 +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB 28 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB 28 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB 30 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB 29 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK 0x60000000 +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x) (((x) << 29) & 0x60000000) +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB 31 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB 31 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_controls_2 */ +#define PHY_BB_TIMING_CONTROLS_2_ADDRESS 0x00009810 +#define PHY_BB_TIMING_CONTROLS_2_OFFSET 0x00009810 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB 11 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB 0 +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK 0x00000fff +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB 12 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB 12 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK 0x00001000 +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB 13 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB 13 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK 0x00002000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MSB 14 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_LSB 14 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MASK 0x00004000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB 15 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB 15 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK 0x00008000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB 22 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB 16 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK 0x007f0000 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB 26 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB 24 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK 0x07000000 +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x) (((x) << 24) & 0x07000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB 27 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB 27 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK 0x08000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB 28 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB 28 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB 29 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB 29 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK 0x20000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB 30 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB 30 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB 31 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB 31 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_controls_3 */ +#define PHY_BB_TIMING_CONTROLS_3_ADDRESS 0x00009814 +#define PHY_BB_TIMING_CONTROLS_3_OFFSET 0x00009814 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB 7 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB 0 +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK 0x000000ff +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB 8 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB 8 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK 0x00000100 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB 9 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB 9 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK 0x00000200 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB 10 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB 10 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK 0x00000400 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB 11 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB 11 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK 0x00000800 +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB 12 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB 12 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK 0x00001000 +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB 16 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB 13 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK 0x0001e000 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x) (((x) & 0x0001e000) >> 13) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x) (((x) << 13) & 0x0001e000) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB 31 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB 17 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK 0xfffe0000 +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x) (((x) & 0xfffe0000) >> 17) +#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x) (((x) << 17) & 0xfffe0000) + +/* macros for BB_D2_chip_id */ +#define PHY_BB_D2_CHIP_ID_ADDRESS 0x00009818 +#define PHY_BB_D2_CHIP_ID_OFFSET 0x00009818 +#define PHY_BB_D2_CHIP_ID_OLD_ID_MSB 7 +#define PHY_BB_D2_CHIP_ID_OLD_ID_LSB 0 +#define PHY_BB_D2_CHIP_ID_OLD_ID_MASK 0x000000ff +#define PHY_BB_D2_CHIP_ID_OLD_ID_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_D2_CHIP_ID_ID_MSB 31 +#define PHY_BB_D2_CHIP_ID_ID_LSB 8 +#define PHY_BB_D2_CHIP_ID_ID_MASK 0xffffff00 +#define PHY_BB_D2_CHIP_ID_ID_GET(x) (((x) & 0xffffff00) >> 8) + +/* macros for BB_active */ +#define PHY_BB_ACTIVE_ADDRESS 0x0000981c +#define PHY_BB_ACTIVE_OFFSET 0x0000981c +#define PHY_BB_ACTIVE_CF_ACTIVE_MSB 0 +#define PHY_BB_ACTIVE_CF_ACTIVE_LSB 0 +#define PHY_BB_ACTIVE_CF_ACTIVE_MASK 0x00000001 +#define PHY_BB_ACTIVE_CF_ACTIVE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_ACTIVE_CF_ACTIVE_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_tx_timing_1 */ +#define PHY_BB_TX_TIMING_1_ADDRESS 0x00009820 +#define PHY_BB_TX_TIMING_1_OFFSET 0x00009820 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB 7 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB 0 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK 0x000000ff +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB 15 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB 8 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB 23 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB 16 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB 31 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB 24 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK 0xff000000 +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_tx_timing_2 */ +#define PHY_BB_TX_TIMING_2_ADDRESS 0x00009824 +#define PHY_BB_TX_TIMING_2_OFFSET 0x00009824 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB 7 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB 0 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK 0x000000ff +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB 15 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB 8 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB 23 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB 16 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB 31 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB 24 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK 0xff000000 +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_tx_timing_3 */ +#define PHY_BB_TX_TIMING_3_ADDRESS 0x00009828 +#define PHY_BB_TX_TIMING_3_OFFSET 0x00009828 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB 7 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB 0 +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK 0x000000ff +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB 15 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB 8 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK 0x0000ff00 +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB 23 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB 16 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK 0x00ff0000 +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB 31 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB 24 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK 0xff000000 +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_addac_parallel_control */ +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS 0x0000982c +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFFSET 0x0000982c +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB 12 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB 12 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK 0x00001000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB 13 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB 13 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK 0x00002000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB 15 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB 15 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK 0x00008000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB 28 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB 28 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK 0x10000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB 29 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB 29 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK 0x20000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB 31 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB 31 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK 0x80000000 +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_xpa_timing_control */ +#define PHY_BB_XPA_TIMING_CONTROL_ADDRESS 0x00009834 +#define PHY_BB_XPA_TIMING_CONTROL_OFFSET 0x00009834 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB 7 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB 0 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK 0x000000ff +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB 15 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB 8 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK 0x0000ff00 +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB 23 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB 16 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK 0x00ff0000 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB 31 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB 24 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK 0xff000000 +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_misc_pa_control */ +#define PHY_BB_MISC_PA_CONTROL_ADDRESS 0x00009838 +#define PHY_BB_MISC_PA_CONTROL_OFFSET 0x00009838 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB 0 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB 0 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK 0x00000001 +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB 1 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB 1 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK 0x00000002 +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB 2 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB 2 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK 0x00000004 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB 3 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB 3 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK 0x00000008 +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x) (((x) << 3) & 0x00000008) + +/* macros for BB_tstdac_constant */ +#define PHY_BB_TSTDAC_CONSTANT_ADDRESS 0x0000983c +#define PHY_BB_TSTDAC_CONSTANT_OFFSET 0x0000983c +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB 10 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB 0 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK 0x000007ff +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x) (((x) & 0x000007ff) >> 0) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x) (((x) << 0) & 0x000007ff) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB 21 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB 11 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK 0x003ff800 +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x) (((x) & 0x003ff800) >> 11) +#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x) (((x) << 11) & 0x003ff800) + +/* macros for BB_find_signal_low */ +#define PHY_BB_FIND_SIGNAL_LOW_ADDRESS 0x00009840 +#define PHY_BB_FIND_SIGNAL_LOW_OFFSET 0x00009840 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB 5 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB 0 +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK 0x0000003f +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB 11 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB 6 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK 0x00000fc0 +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB 19 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB 12 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK 0x000ff000 +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x) (((x) & 0x000ff000) >> 12) +#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x) (((x) << 12) & 0x000ff000) +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB 23 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB 20 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK 0x00f00000 +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB 30 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB 24 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK 0x7f000000 +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_settling_time */ +#define PHY_BB_SETTLING_TIME_ADDRESS 0x00009844 +#define PHY_BB_SETTLING_TIME_OFFSET 0x00009844 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MSB 6 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_LSB 0 +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MASK 0x0000007f +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_SETTLING_TIME_AGC_SETTLING_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MSB 13 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_LSB 7 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MASK 0x00003f80 +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MSB 19 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_LSB 14 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MASK 0x000fc000 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_SET(x) (((x) << 14) & 0x000fc000) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MSB 25 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_LSB 20 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MASK 0x03f00000 +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_GET(x) (((x) & 0x03f00000) >> 20) +#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_SET(x) (((x) << 20) & 0x03f00000) +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MSB 29 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_LSB 26 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MASK 0x3c000000 +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_GET(x) (((x) & 0x3c000000) >> 26) +#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_SET(x) (((x) << 26) & 0x3c000000) + +/* macros for BB_gain_force_max_gains_b0 */ +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ADDRESS 0x00009848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_OFFSET 0x00009848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MSB 13 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_LSB 7 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MASK 0x00003f80 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MSB 20 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_LSB 14 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MASK 0x001fc000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MSB 21 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_LSB 21 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MASK 0x00200000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MSB 31 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_LSB 31 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MASK 0x80000000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_gains_min_offsets_b0 */ +#define PHY_BB_GAINS_MIN_OFFSETS_B0_ADDRESS 0x0000984c +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSET 0x0000984c +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MSB 6 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_LSB 0 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MASK 0x0000007f +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MSB 11 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_LSB 7 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MASK 0x00000f80 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_GET(x) (((x) & 0x00000f80) >> 7) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_SET(x) (((x) << 7) & 0x00000f80) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MSB 16 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_LSB 12 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MASK 0x0001f000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MSB 24 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_LSB 17 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MASK 0x01fe0000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_SET(x) (((x) << 17) & 0x01fe0000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_LSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MASK 0x02000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_LSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MASK 0x04000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_SET(x) (((x) << 26) & 0x04000000) + +/* macros for BB_desired_sigsize */ +#define PHY_BB_DESIRED_SIGSIZE_ADDRESS 0x00009850 +#define PHY_BB_DESIRED_SIGSIZE_OFFSET 0x00009850 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MSB 7 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_LSB 0 +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MASK 0x000000ff +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MSB 27 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_LSB 20 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MASK 0x0ff00000 +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_GET(x) (((x) & 0x0ff00000) >> 20) +#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_SET(x) (((x) << 20) & 0x0ff00000) +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MSB 29 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_LSB 28 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MASK 0x30000000 +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_GET(x) (((x) & 0x30000000) >> 28) +#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_SET(x) (((x) << 28) & 0x30000000) +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MSB 30 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_LSB 30 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MASK 0x40000000 +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MSB 31 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_LSB 31 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MASK 0x80000000 +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_3a */ +#define PHY_BB_TIMING_CONTROL_3A_ADDRESS 0x00009854 +#define PHY_BB_TIMING_CONTROL_3A_OFFSET 0x00009854 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MSB 6 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_LSB 0 +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MASK 0x0000007f +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_SET(x) (((x) << 0) & 0x0000007f) + +/* macros for BB_find_signal */ +#define PHY_BB_FIND_SIGNAL_ADDRESS 0x00009858 +#define PHY_BB_FIND_SIGNAL_OFFSET 0x00009858 +#define PHY_BB_FIND_SIGNAL_RELSTEP_MSB 5 +#define PHY_BB_FIND_SIGNAL_RELSTEP_LSB 0 +#define PHY_BB_FIND_SIGNAL_RELSTEP_MASK 0x0000003f +#define PHY_BB_FIND_SIGNAL_RELSTEP_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_FIND_SIGNAL_RELSTEP_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_FIND_SIGNAL_RELPWR_MSB 11 +#define PHY_BB_FIND_SIGNAL_RELPWR_LSB 6 +#define PHY_BB_FIND_SIGNAL_RELPWR_MASK 0x00000fc0 +#define PHY_BB_FIND_SIGNAL_RELPWR_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_FIND_SIGNAL_RELPWR_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_FIND_SIGNAL_FIRSTEP_MSB 17 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_LSB 12 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_MASK 0x0003f000 +#define PHY_BB_FIND_SIGNAL_FIRSTEP_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_FIND_SIGNAL_FIRSTEP_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_FIND_SIGNAL_FIRPWR_MSB 25 +#define PHY_BB_FIND_SIGNAL_FIRPWR_LSB 18 +#define PHY_BB_FIND_SIGNAL_FIRPWR_MASK 0x03fc0000 +#define PHY_BB_FIND_SIGNAL_FIRPWR_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_BB_FIND_SIGNAL_FIRPWR_SET(x) (((x) << 18) & 0x03fc0000) +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MSB 31 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_LSB 26 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MASK 0xfc000000 +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for BB_agc */ +#define PHY_BB_AGC_ADDRESS 0x0000985c +#define PHY_BB_AGC_OFFSET 0x0000985c +#define PHY_BB_AGC_COARSEPWR_CONST_MSB 6 +#define PHY_BB_AGC_COARSEPWR_CONST_LSB 0 +#define PHY_BB_AGC_COARSEPWR_CONST_MASK 0x0000007f +#define PHY_BB_AGC_COARSEPWR_CONST_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_AGC_COARSEPWR_CONST_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_AGC_COARSE_LOW_MSB 14 +#define PHY_BB_AGC_COARSE_LOW_LSB 7 +#define PHY_BB_AGC_COARSE_LOW_MASK 0x00007f80 +#define PHY_BB_AGC_COARSE_LOW_GET(x) (((x) & 0x00007f80) >> 7) +#define PHY_BB_AGC_COARSE_LOW_SET(x) (((x) << 7) & 0x00007f80) +#define PHY_BB_AGC_COARSE_HIGH_MSB 21 +#define PHY_BB_AGC_COARSE_HIGH_LSB 15 +#define PHY_BB_AGC_COARSE_HIGH_MASK 0x003f8000 +#define PHY_BB_AGC_COARSE_HIGH_GET(x) (((x) & 0x003f8000) >> 15) +#define PHY_BB_AGC_COARSE_HIGH_SET(x) (((x) << 15) & 0x003f8000) +#define PHY_BB_AGC_QUICK_DROP_MSB 29 +#define PHY_BB_AGC_QUICK_DROP_LSB 22 +#define PHY_BB_AGC_QUICK_DROP_MASK 0x3fc00000 +#define PHY_BB_AGC_QUICK_DROP_GET(x) (((x) & 0x3fc00000) >> 22) +#define PHY_BB_AGC_QUICK_DROP_SET(x) (((x) << 22) & 0x3fc00000) +#define PHY_BB_AGC_RSSI_OUT_SELECT_MSB 31 +#define PHY_BB_AGC_RSSI_OUT_SELECT_LSB 30 +#define PHY_BB_AGC_RSSI_OUT_SELECT_MASK 0xc0000000 +#define PHY_BB_AGC_RSSI_OUT_SELECT_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_AGC_RSSI_OUT_SELECT_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_agc_control */ +#define PHY_BB_AGC_CONTROL_ADDRESS 0x00009860 +#define PHY_BB_AGC_CONTROL_OFFSET 0x00009860 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB 0 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB 0 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK 0x00000001 +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB 1 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB 1 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK 0x00000002 +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB 5 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB 3 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK 0x00000038 +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB 9 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB 6 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK 0x000003c0 +#define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x) (((x) & 0x000003c0) >> 6) +#define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x) (((x) << 6) & 0x000003c0) +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB 10 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB 10 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK 0x00000400 +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB 11 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB 11 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK 0x00000800 +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MSB 12 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_LSB 12 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MASK 0x00001000 +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MSB 13 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_LSB 13 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MASK 0x00002000 +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB 15 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB 15 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK 0x00008000 +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB 16 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB 16 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK 0x00010000 +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB 17 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB 17 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK 0x00020000 +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB 18 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB 18 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK 0x00040000 +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB 19 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB 19 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK 0x00080000 +#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB 20 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB 20 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK 0x00100000 +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x) (((x) << 20) & 0x00100000) + +/* macros for BB_cca_b0 */ +#define PHY_BB_CCA_B0_ADDRESS 0x00009864 +#define PHY_BB_CCA_B0_OFFSET 0x00009864 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MSB 8 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_LSB 0 +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MASK 0x000001ff +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MSB 11 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_LSB 9 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MASK 0x00000e00 +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_SET(x) (((x) << 9) & 0x00000e00) +#define PHY_BB_CCA_B0_CF_THRESH62_MSB 19 +#define PHY_BB_CCA_B0_CF_THRESH62_LSB 12 +#define PHY_BB_CCA_B0_CF_THRESH62_MASK 0x000ff000 +#define PHY_BB_CCA_B0_CF_THRESH62_GET(x) (((x) & 0x000ff000) >> 12) +#define PHY_BB_CCA_B0_CF_THRESH62_SET(x) (((x) << 12) & 0x000ff000) +#define PHY_BB_CCA_B0_MINCCAPWR_0_MSB 28 +#define PHY_BB_CCA_B0_MINCCAPWR_0_LSB 20 +#define PHY_BB_CCA_B0_MINCCAPWR_0_MASK 0x1ff00000 +#define PHY_BB_CCA_B0_MINCCAPWR_0_GET(x) (((x) & 0x1ff00000) >> 20) + +/* macros for BB_sfcorr */ +#define PHY_BB_SFCORR_ADDRESS 0x00009868 +#define PHY_BB_SFCORR_OFFSET 0x00009868 +#define PHY_BB_SFCORR_M2COUNT_THR_MSB 4 +#define PHY_BB_SFCORR_M2COUNT_THR_LSB 0 +#define PHY_BB_SFCORR_M2COUNT_THR_MASK 0x0000001f +#define PHY_BB_SFCORR_M2COUNT_THR_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_SFCORR_M2COUNT_THR_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_SFCORR_ADCSAT_THRESH_MSB 10 +#define PHY_BB_SFCORR_ADCSAT_THRESH_LSB 5 +#define PHY_BB_SFCORR_ADCSAT_THRESH_MASK 0x000007e0 +#define PHY_BB_SFCORR_ADCSAT_THRESH_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_SFCORR_ADCSAT_THRESH_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MSB 16 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_LSB 11 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MASK 0x0001f800 +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_BB_SFCORR_ADCSAT_ICOUNT_SET(x) (((x) << 11) & 0x0001f800) +#define PHY_BB_SFCORR_M1_THRES_MSB 23 +#define PHY_BB_SFCORR_M1_THRES_LSB 17 +#define PHY_BB_SFCORR_M1_THRES_MASK 0x00fe0000 +#define PHY_BB_SFCORR_M1_THRES_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_SFCORR_M1_THRES_SET(x) (((x) << 17) & 0x00fe0000) +#define PHY_BB_SFCORR_M2_THRES_MSB 30 +#define PHY_BB_SFCORR_M2_THRES_LSB 24 +#define PHY_BB_SFCORR_M2_THRES_MASK 0x7f000000 +#define PHY_BB_SFCORR_M2_THRES_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_SFCORR_M2_THRES_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_self_corr_low */ +#define PHY_BB_SELF_CORR_LOW_ADDRESS 0x0000986c +#define PHY_BB_SELF_CORR_LOW_OFFSET 0x0000986c +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB 0 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB 0 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK 0x00000001 +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB 7 +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB 1 +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK 0x000000fe +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB 13 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB 8 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK 0x00003f00 +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB 20 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB 14 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK 0x001fc000 +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB 27 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB 21 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK 0x0fe00000 +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x) (((x) << 21) & 0x0fe00000) + +/* macros for BB_synth_control */ +#define PHY_BB_SYNTH_CONTROL_ADDRESS 0x00009874 +#define PHY_BB_SYNTH_CONTROL_OFFSET 0x00009874 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB 16 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB 0 +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK 0x0001ffff +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x) (((x) & 0x0001ffff) >> 0) +#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x) (((x) << 0) & 0x0001ffff) +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB 25 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB 17 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK 0x03fe0000 +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x) (((x) & 0x03fe0000) >> 17) +#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x) (((x) << 17) & 0x03fe0000) +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB 27 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB 26 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK 0x0c000000 +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x) (((x) & 0x0c000000) >> 26) +#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x) (((x) << 26) & 0x0c000000) +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB 28 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB 28 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK 0x10000000 +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB 29 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB 29 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK 0x20000000 +#define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB 30 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB 30 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK 0x40000000 +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_addac_clk_select */ +#define PHY_BB_ADDAC_CLK_SELECT_ADDRESS 0x00009878 +#define PHY_BB_ADDAC_CLK_SELECT_OFFSET 0x00009878 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB 3 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB 2 +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK 0x0000000c +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MSB 5 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_LSB 4 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MASK 0x00000030 +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_SET(x) (((x) << 4) & 0x00000030) + +/* macros for BB_pll_cntl */ +#define PHY_BB_PLL_CNTL_ADDRESS 0x0000987c +#define PHY_BB_PLL_CNTL_OFFSET 0x0000987c +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB 9 +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB 0 +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK 0x000003ff +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB 13 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB 10 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK 0x00003c00 +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB 15 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB 14 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK 0x0000c000 +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB 16 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB 16 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK 0x00010000 +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB 27 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB 17 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK 0x0ffe0000 +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x) (((x) & 0x0ffe0000) >> 17) +#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x) (((x) << 17) & 0x0ffe0000) + +/* macros for BB_vit_spur_mask_A */ +#define PHY_BB_VIT_SPUR_MASK_A_ADDRESS 0x00009900 +#define PHY_BB_VIT_SPUR_MASK_A_OFFSET 0x00009900 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MSB 9 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_LSB 0 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MASK 0x000003ff +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MSB 16 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_LSB 10 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MASK 0x0001fc00 +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_SET(x) (((x) << 10) & 0x0001fc00) + +/* macros for BB_vit_spur_mask_B */ +#define PHY_BB_VIT_SPUR_MASK_B_ADDRESS 0x00009904 +#define PHY_BB_VIT_SPUR_MASK_B_OFFSET 0x00009904 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MSB 9 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_LSB 0 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MASK 0x000003ff +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MSB 16 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_LSB 10 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MASK 0x0001fc00 +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_SET(x) (((x) << 10) & 0x0001fc00) + +/* macros for BB_pilot_spur_mask */ +#define PHY_BB_PILOT_SPUR_MASK_ADDRESS 0x00009908 +#define PHY_BB_PILOT_SPUR_MASK_OFFSET 0x00009908 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MSB 4 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_LSB 0 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MASK 0x0000001f +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MSB 11 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_LSB 5 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MASK 0x00000fe0 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MSB 16 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_LSB 12 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MASK 0x0001f000 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MSB 23 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_LSB 17 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MASK 0x00fe0000 +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000) + +/* macros for BB_chan_spur_mask */ +#define PHY_BB_CHAN_SPUR_MASK_ADDRESS 0x0000990c +#define PHY_BB_CHAN_SPUR_MASK_OFFSET 0x0000990c +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MSB 4 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_LSB 0 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MASK 0x0000001f +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MSB 11 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_LSB 5 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MASK 0x00000fe0 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MSB 16 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_LSB 12 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MASK 0x0001f000 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MSB 23 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_LSB 17 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MASK 0x00fe0000 +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17) +#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000) + +/* macros for BB_spectral_scan */ +#define PHY_BB_SPECTRAL_SCAN_ADDRESS 0x00009910 +#define PHY_BB_SPECTRAL_SCAN_OFFSET 0x00009910 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB 0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB 0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK 0x00000001 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB 1 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB 1 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK 0x00000002 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MSB 2 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_LSB 2 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MASK 0x00000004 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MSB 3 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_LSB 3 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MASK 0x00000008 +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MSB 7 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_LSB 4 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MASK 0x000000f0 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB 15 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB 8 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK 0x0000ff00 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB 27 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB 16 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK 0x0fff0000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x) (((x) & 0x0fff0000) >> 16) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x) (((x) << 16) & 0x0fff0000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MSB 28 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_LSB 28 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MASK 0x10000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB 29 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB 29 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK 0x20000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MSB 30 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_LSB 30 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MASK 0x40000000 +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_analog_power_on_time */ +#define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS 0x00009914 +#define PHY_BB_ANALOG_POWER_ON_TIME_OFFSET 0x00009914 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB 13 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB 0 +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK 0x00003fff +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x) (((x) << 0) & 0x00003fff) + +/* macros for BB_search_start_delay */ +#define PHY_BB_SEARCH_START_DELAY_ADDRESS 0x00009918 +#define PHY_BB_SEARCH_START_DELAY_OFFSET 0x00009918 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MSB 11 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_LSB 0 +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MASK 0x00000fff +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MSB 12 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_LSB 12 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MASK 0x00001000 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MSB 13 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_LSB 13 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MASK 0x00002000 +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_SET(x) (((x) << 13) & 0x00002000) + +/* macros for BB_max_rx_length */ +#define PHY_BB_MAX_RX_LENGTH_ADDRESS 0x0000991c +#define PHY_BB_MAX_RX_LENGTH_OFFSET 0x0000991c +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB 11 +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB 0 +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK 0x00000fff +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB 29 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB 12 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK 0x3ffff000 +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x) (((x) & 0x3ffff000) >> 12) +#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x) (((x) << 12) & 0x3ffff000) + +/* macros for BB_timing_control_4 */ +#define PHY_BB_TIMING_CONTROL_4_ADDRESS 0x00009920 +#define PHY_BB_TIMING_CONTROL_4_OFFSET 0x00009920 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB 15 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB 12 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK 0x0000f000 +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB 16 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB 16 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK 0x00010000 +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB 20 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB 17 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK 0x001e0000 +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x) (((x) & 0x001e0000) >> 17) +#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x) (((x) << 17) & 0x001e0000) +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB 27 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB 21 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK 0x0fe00000 +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB 28 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB 28 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK 0x10000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB 29 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB 29 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK 0x20000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MSB 30 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_LSB 30 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB 31 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB 31 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_5 */ +#define PHY_BB_TIMING_CONTROL_5_ADDRESS 0x00009924 +#define PHY_BB_TIMING_CONTROL_5_OFFSET 0x00009924 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB 0 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB 0 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK 0x00000001 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB 7 +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB 1 +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK 0x000000fe +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB 15 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB 15 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK 0x00008000 +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB 22 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB 16 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK 0x007f0000 +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB 29 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB 23 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK 0x3f800000 +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MSB 30 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_LSB 30 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MSB 31 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_LSB 31 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_phyonly_warm_reset */ +#define PHY_BB_PHYONLY_WARM_RESET_ADDRESS 0x00009928 +#define PHY_BB_PHYONLY_WARM_RESET_OFFSET 0x00009928 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MSB 0 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_LSB 0 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MASK 0x00000001 +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_phyonly_control */ +#define PHY_BB_PHYONLY_CONTROL_ADDRESS 0x0000992c +#define PHY_BB_PHYONLY_CONTROL_OFFSET 0x0000992c +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB 0 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB 0 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK 0x00000001 +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB 1 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB 1 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK 0x00000002 +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MSB 2 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_LSB 2 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MASK 0x00000004 +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB 3 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB 3 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK 0x00000008 +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB 4 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB 4 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK 0x00000010 +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB 5 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB 5 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK 0x00000020 +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB 6 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB 6 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK 0x00000040 +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB 7 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB 7 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK 0x00000080 +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x) (((x) << 7) & 0x00000080) + +/* macros for BB_powertx_rate1 */ +#define PHY_BB_POWERTX_RATE1_ADDRESS 0x00009934 +#define PHY_BB_POWERTX_RATE1_OFFSET 0x00009934 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_MSB 5 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_LSB 0 +#define PHY_BB_POWERTX_RATE1_POWERTX_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE1_POWERTX_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE1_POWERTX_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE1_POWERTX_1_MSB 13 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_LSB 8 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE1_POWERTX_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE1_POWERTX_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE1_POWERTX_2_MSB 21 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_LSB 16 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE1_POWERTX_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE1_POWERTX_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE1_POWERTX_3_MSB 29 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_LSB 24 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE1_POWERTX_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE1_POWERTX_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate2 */ +#define PHY_BB_POWERTX_RATE2_ADDRESS 0x00009938 +#define PHY_BB_POWERTX_RATE2_OFFSET 0x00009938 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_MSB 5 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_LSB 0 +#define PHY_BB_POWERTX_RATE2_POWERTX_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE2_POWERTX_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE2_POWERTX_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE2_POWERTX_5_MSB 13 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_LSB 8 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE2_POWERTX_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE2_POWERTX_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE2_POWERTX_6_MSB 21 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_LSB 16 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE2_POWERTX_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE2_POWERTX_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE2_POWERTX_7_MSB 29 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_LSB 24 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE2_POWERTX_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE2_POWERTX_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_max */ +#define PHY_BB_POWERTX_MAX_ADDRESS 0x0000993c +#define PHY_BB_POWERTX_MAX_OFFSET 0x0000993c +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MSB 6 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_LSB 6 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MASK 0x00000040 +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_SET(x) (((x) << 6) & 0x00000040) + +/* macros for BB_extension_radar */ +#define PHY_BB_EXTENSION_RADAR_ADDRESS 0x00009940 +#define PHY_BB_EXTENSION_RADAR_OFFSET 0x00009940 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MSB 13 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_LSB 8 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MASK 0x00003f00 +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MSB 14 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_LSB 14 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MASK 0x00004000 +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MSB 22 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_LSB 15 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MASK 0x007f8000 +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_GET(x) (((x) & 0x007f8000) >> 15) +#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_SET(x) (((x) << 15) & 0x007f8000) +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB 30 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB 23 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK 0x7f800000 +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x) (((x) & 0x7f800000) >> 23) +#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x) (((x) << 23) & 0x7f800000) +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MSB 31 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_LSB 31 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MASK 0x80000000 +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_frame_control */ +#define PHY_BB_FRAME_CONTROL_ADDRESS 0x00009944 +#define PHY_BB_FRAME_CONTROL_OFFSET 0x00009944 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB 1 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB 0 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK 0x00000003 +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MSB 2 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_LSB 2 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MASK 0x00000004 +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB 5 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB 3 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK 0x00000038 +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB 7 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB 6 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK 0x000000c0 +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB 15 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB 8 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK 0x0000ff00 +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB 16 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB 16 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK 0x00010000 +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB 17 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB 17 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK 0x00020000 +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB 18 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB 18 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK 0x00040000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MSB 19 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_LSB 19 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MASK 0x00080000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB 20 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB 20 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK 0x00100000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB 21 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB 21 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK 0x00200000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB 22 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB 22 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK 0x00400000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB 23 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB 23 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK 0x00800000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB 24 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB 24 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK 0x01000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB 25 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB 25 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK 0x02000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB 26 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB 26 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK 0x04000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB 27 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB 27 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK 0x08000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MSB 28 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_LSB 28 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MASK 0x10000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB 29 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB 29 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK 0x20000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB 30 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB 30 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK 0x40000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB 31 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB 31 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK 0x80000000 +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_timing_control_6 */ +#define PHY_BB_TIMING_CONTROL_6_ADDRESS 0x00009948 +#define PHY_BB_TIMING_CONTROL_6_OFFSET 0x00009948 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB 7 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB 0 +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK 0x000000ff +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB 14 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB 8 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK 0x00007f00 +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x) (((x) & 0x00007f00) >> 8) +#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x) (((x) << 8) & 0x00007f00) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB 20 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB 15 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK 0x001f8000 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB 27 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB 21 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK 0x0fe00000 +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MSB 31 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_LSB 28 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MASK 0xf0000000 +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_spur_mask_controls */ +#define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS 0x0000994c +#define PHY_BB_SPUR_MASK_CONTROLS_OFFSET 0x0000994c +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB 7 +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB 0 +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK 0x000000ff +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB 8 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB 8 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK 0x00000100 +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB 17 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB 17 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK 0x00020000 +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB 25 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB 18 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK 0x03fc0000 +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x) (((x) & 0x03fc0000) >> 18) +#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x) (((x) << 18) & 0x03fc0000) + +/* macros for BB_rx_iq_corr_b0 */ +#define PHY_BB_RX_IQ_CORR_B0_ADDRESS 0x00009950 +#define PHY_BB_RX_IQ_CORR_B0_OFFSET 0x00009950 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MSB 6 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_LSB 0 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MASK 0x0000007f +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MSB 13 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_LSB 7 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MASK 0x00003f80 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB 14 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB 14 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK 0x00004000 +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB 21 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB 15 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK 0x003f8000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x003f8000) >> 15) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 15) & 0x003f8000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB 28 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB 22 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK 0x1fc00000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MSB 29 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_LSB 29 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MASK 0x20000000 +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_SET(x) (((x) << 29) & 0x20000000) + +/* macros for BB_radar_detection */ +#define PHY_BB_RADAR_DETECTION_ADDRESS 0x00009954 +#define PHY_BB_RADAR_DETECTION_OFFSET 0x00009954 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB 0 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB 0 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK 0x00000001 +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MSB 5 +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_LSB 1 +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MASK 0x0000003e +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB 11 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB 6 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK 0x00000fc0 +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB 17 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB 12 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK 0x0003f000 +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MSB 23 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_LSB 18 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MASK 0x00fc0000 +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB 30 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB 24 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK 0x7f000000 +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MSB 31 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_LSB 31 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MASK 0x80000000 +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_radar_detection_2 */ +#define PHY_BB_RADAR_DETECTION_2_ADDRESS 0x00009958 +#define PHY_BB_RADAR_DETECTION_2_OFFSET 0x00009958 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MSB 7 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_LSB 0 +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MASK 0x000000ff +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB 12 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB 8 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK 0x00001f00 +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB 13 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB 13 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK 0x00002000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MSB 14 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_LSB 14 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MASK 0x00004000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MSB 15 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_LSB 15 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MASK 0x00008000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MSB 21 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_LSB 16 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MASK 0x003f0000 +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MSB 22 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_LSB 22 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MASK 0x00400000 +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MSB 23 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_LSB 23 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MASK 0x00800000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MSB 26 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_LSB 24 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MASK 0x07000000 +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_GET(x) (((x) & 0x07000000) >> 24) +#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_SET(x) (((x) << 24) & 0x07000000) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB 27 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB 27 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK 0x08000000 +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_tx_phase_ramp_b0 */ +#define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS 0x0000995c +#define PHY_BB_TX_PHASE_RAMP_B0_OFFSET 0x0000995c +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB 0 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB 0 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK 0x00000001 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB 6 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB 1 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK 0x0000007e +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x) (((x) & 0x0000007e) >> 1) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x) (((x) << 1) & 0x0000007e) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB 16 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB 7 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK 0x0001ff80 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x) (((x) & 0x0001ff80) >> 7) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x) (((x) << 7) & 0x0001ff80) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB 24 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB 17 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK 0x01fe0000 +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x) (((x) << 17) & 0x01fe0000) + +/* macros for BB_switch_table_chn_b0 */ +#define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS 0x00009960 +#define PHY_BB_SWITCH_TABLE_CHN_B0_OFFSET 0x00009960 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB 1 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB 0 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK 0x00000003 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB 3 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB 2 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK 0x0000000c +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB 5 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB 4 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK 0x00000030 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB 7 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB 6 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK 0x000000c0 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x) (((x) << 6) & 0x000000c0) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB 9 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB 8 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK 0x00000300 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB 11 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB 10 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK 0x00000c00 +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x) (((x) & 0x00000c00) >> 10) +#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x) (((x) << 10) & 0x00000c00) + +/* macros for BB_switch_table_com1 */ +#define PHY_BB_SWITCH_TABLE_COM1_ADDRESS 0x00009964 +#define PHY_BB_SWITCH_TABLE_COM1_OFFSET 0x00009964 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB 3 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB 0 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK 0x0000000f +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB 7 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB 4 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK 0x000000f0 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB 11 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB 8 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK 0x00000f00 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB 15 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB 12 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK 0x0000f000 +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x) (((x) << 12) & 0x0000f000) + +/* macros for BB_cca_ctrl_2_b0 */ +#define PHY_BB_CCA_CTRL_2_B0_ADDRESS 0x00009968 +#define PHY_BB_CCA_CTRL_2_B0_OFFSET 0x00009968 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MSB 8 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_LSB 0 +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MASK 0x000001ff +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MSB 9 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_LSB 9 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MASK 0x00000200 +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MSB 17 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_LSB 10 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MASK 0x0003fc00 +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_GET(x) (((x) & 0x0003fc00) >> 10) +#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_SET(x) (((x) << 10) & 0x0003fc00) +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MSB 18 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_LSB 18 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MASK 0x00040000 +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_SET(x) (((x) << 18) & 0x00040000) + +/* macros for BB_switch_table_com2 */ +#define PHY_BB_SWITCH_TABLE_COM2_ADDRESS 0x0000996c +#define PHY_BB_SWITCH_TABLE_COM2_OFFSET 0x0000996c +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MSB 3 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_LSB 0 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MASK 0x0000000f +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MSB 7 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_LSB 4 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MASK 0x000000f0 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MSB 11 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_LSB 8 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MASK 0x00000f00 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MSB 15 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_LSB 12 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MASK 0x0000f000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MSB 19 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_LSB 16 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MASK 0x000f0000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MSB 23 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_LSB 20 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MASK 0x00f00000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MSB 27 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_LSB 24 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MASK 0x0f000000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MSB 31 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_LSB 28 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MASK 0xf0000000 +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_restart */ +#define PHY_BB_RESTART_ADDRESS 0x00009970 +#define PHY_BB_RESTART_OFFSET 0x00009970 +#define PHY_BB_RESTART_ENABLE_RESTART_MSB 0 +#define PHY_BB_RESTART_ENABLE_RESTART_LSB 0 +#define PHY_BB_RESTART_ENABLE_RESTART_MASK 0x00000001 +#define PHY_BB_RESTART_ENABLE_RESTART_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RESTART_ENABLE_RESTART_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MSB 5 +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_LSB 1 +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MASK 0x0000003e +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MSB 6 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_LSB 6 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MASK 0x00000040 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MSB 11 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_LSB 7 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MASK 0x00000f80 +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_GET(x) (((x) & 0x00000f80) >> 7) +#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_SET(x) (((x) << 7) & 0x00000f80) +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MSB 17 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_LSB 12 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MASK 0x0003f000 +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MSB 20 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_LSB 18 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MASK 0x001c0000 +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_GET(x) (((x) & 0x001c0000) >> 18) +#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_SET(x) (((x) << 18) & 0x001c0000) +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MSB 21 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_LSB 21 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MASK 0x00200000 +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MSB 28 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_LSB 22 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MASK 0x1fc00000 +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MSB 29 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_LSB 29 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MASK 0x20000000 +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_RESTART_DISABLE_DC_RESTART_MSB 30 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_LSB 30 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_MASK 0x40000000 +#define PHY_BB_RESTART_DISABLE_DC_RESTART_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_RESTART_DISABLE_DC_RESTART_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_RESTART_RESTART_MODE_BW40_MSB 31 +#define PHY_BB_RESTART_RESTART_MODE_BW40_LSB 31 +#define PHY_BB_RESTART_RESTART_MODE_BW40_MASK 0x80000000 +#define PHY_BB_RESTART_RESTART_MODE_BW40_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_RESTART_RESTART_MODE_BW40_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_scrambler_seed */ +#define PHY_BB_SCRAMBLER_SEED_ADDRESS 0x00009978 +#define PHY_BB_SCRAMBLER_SEED_OFFSET 0x00009978 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB 6 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB 0 +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK 0x0000007f +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x) (((x) << 0) & 0x0000007f) + +/* macros for BB_rfbus_request */ +#define PHY_BB_RFBUS_REQUEST_ADDRESS 0x0000997c +#define PHY_BB_RFBUS_REQUEST_OFFSET 0x0000997c +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB 0 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB 0 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK 0x00000001 +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_timing_control_11 */ +#define PHY_BB_TIMING_CONTROL_11_ADDRESS 0x000099a0 +#define PHY_BB_TIMING_CONTROL_11_OFFSET 0x000099a0 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MSB 19 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_LSB 0 +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MASK 0x000fffff +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_GET(x) (((x) & 0x000fffff) >> 0) +#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_SET(x) (((x) << 0) & 0x000fffff) +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB 29 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB 20 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK 0x3ff00000 +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x) (((x) << 20) & 0x3ff00000) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB 30 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB 30 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK 0x40000000 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB 31 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB 31 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK 0x80000000 +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_multichain_enable */ +#define PHY_BB_MULTICHAIN_ENABLE_ADDRESS 0x000099a4 +#define PHY_BB_MULTICHAIN_ENABLE_OFFSET 0x000099a4 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB 2 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB 0 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK 0x00000007 +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007) + +/* macros for BB_multichain_control */ +#define PHY_BB_MULTICHAIN_CONTROL_ADDRESS 0x000099a8 +#define PHY_BB_MULTICHAIN_CONTROL_OFFSET 0x000099a8 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB 0 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB 0 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK 0x00000001 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB 7 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB 1 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK 0x000000fe +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB 8 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB 8 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK 0x00000100 +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB 9 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB 9 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK 0x00000200 +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB 20 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB 10 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK 0x001ffc00 +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x) (((x) & 0x001ffc00) >> 10) +#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x) (((x) << 10) & 0x001ffc00) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB 28 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB 22 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK 0x1fc00000 +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x) (((x) & 0x1fc00000) >> 22) +#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x) (((x) << 22) & 0x1fc00000) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB 29 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB 29 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK 0x20000000 +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x) (((x) << 29) & 0x20000000) + +/* macros for BB_multichain_gain_ctrl */ +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ADDRESS 0x000099ac +#define PHY_BB_MULTICHAIN_GAIN_CTRL_OFFSET 0x000099ac +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MSB 7 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_LSB 0 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MASK 0x000000ff +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MSB 8 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_LSB 8 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MASK 0x00000100 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MSB 14 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_LSB 9 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MASK 0x00007e00 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_GET(x) (((x) & 0x00007e00) >> 9) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_SET(x) (((x) << 9) & 0x00007e00) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MSB 20 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_LSB 15 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MASK 0x001f8000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MSB 21 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_LSB 21 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MASK 0x00200000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MSB 22 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_LSB 22 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MASK 0x00400000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MSB 23 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_LSB 23 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MASK 0x00800000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_SET(x) (((x) << 23) & 0x00800000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MSB 24 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_LSB 24 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MASK 0x01000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MSB 26 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_LSB 25 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MASK 0x06000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MSB 28 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_LSB 27 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MASK 0x18000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_GET(x) (((x) & 0x18000000) >> 27) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_SET(x) (((x) << 27) & 0x18000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MSB 29 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_LSB 29 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MASK 0x20000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MSB 30 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_LSB 30 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MASK 0x40000000 +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_adc_gain_dc_corr_b0 */ +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADDRESS 0x000099b4 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_OFFSET 0x000099b4 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB 5 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB 0 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK 0x0000003f +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB 11 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB 6 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK 0x00000fc0 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB 20 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB 12 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK 0x001ff000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x) (((x) & 0x001ff000) >> 12) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x) (((x) << 12) & 0x001ff000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB 29 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB 21 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK 0x3fe00000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x) (((x) & 0x3fe00000) >> 21) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x) (((x) << 21) & 0x3fe00000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB 30 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB 30 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK 0x40000000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB 31 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB 31 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK 0x80000000 +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_ext_chan_pwr_thr_1 */ +#define PHY_BB_EXT_CHAN_PWR_THR_1_ADDRESS 0x000099b8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_OFFSET 0x000099b8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MSB 7 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_LSB 0 +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MASK 0x000000ff +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MSB 15 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_LSB 8 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MASK 0x0000ff00 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MSB 20 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_LSB 16 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MASK 0x001f0000 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MSB 26 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_LSB 21 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MASK 0x07e00000 +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_ext_chan_pwr_thr_2_b0 */ +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_ADDRESS 0x000099bc +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_OFFSET 0x000099bc +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MSB 8 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_LSB 0 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MASK 0x000001ff +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MSB 15 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_LSB 9 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MASK 0x0000fe00 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_GET(x) (((x) & 0x0000fe00) >> 9) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_SET(x) (((x) << 9) & 0x0000fe00) +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MSB 24 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_LSB 16 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MASK 0x01ff0000 +#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_GET(x) (((x) & 0x01ff0000) >> 16) + +/* macros for BB_ext_chan_scorr_thr */ +#define PHY_BB_EXT_CHAN_SCORR_THR_ADDRESS 0x000099c0 +#define PHY_BB_EXT_CHAN_SCORR_THR_OFFSET 0x000099c0 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MSB 6 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_LSB 0 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MASK 0x0000007f +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_GET(x) (((x) & 0x0000007f) >> 0) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_SET(x) (((x) << 0) & 0x0000007f) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MSB 13 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_LSB 7 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MASK 0x00003f80 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MSB 20 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_LSB 14 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MASK 0x001fc000 +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_SET(x) (((x) << 14) & 0x001fc000) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MSB 27 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_LSB 21 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MASK 0x0fe00000 +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_GET(x) (((x) & 0x0fe00000) >> 21) +#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_SET(x) (((x) << 21) & 0x0fe00000) +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MSB 28 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_LSB 28 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MASK 0x10000000 +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_SET(x) (((x) << 28) & 0x10000000) + +/* macros for BB_ext_chan_detect_win */ +#define PHY_BB_EXT_CHAN_DETECT_WIN_ADDRESS 0x000099c4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_OFFSET 0x000099c4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MSB 3 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LSB 0 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MASK 0x0000000f +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MSB 7 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_LSB 4 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MASK 0x000000f0 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MSB 12 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_LSB 8 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MASK 0x00001f00 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MSB 15 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_LSB 13 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MASK 0x0000e000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_GET(x) (((x) & 0x0000e000) >> 13) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_SET(x) (((x) << 13) & 0x0000e000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MSB 18 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_LSB 16 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MASK 0x00070000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MSB 24 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_LSB 19 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MASK 0x01f80000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MSB 28 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_LSB 25 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MASK 0x1e000000 +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_GET(x) (((x) & 0x1e000000) >> 25) +#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_SET(x) (((x) << 25) & 0x1e000000) + +/* macros for BB_pwr_thr_20_40_det */ +#define PHY_BB_PWR_THR_20_40_DET_ADDRESS 0x000099c8 +#define PHY_BB_PWR_THR_20_40_DET_OFFSET 0x000099c8 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MSB 4 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_LSB 0 +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MASK 0x0000001f +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MSB 10 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_LSB 5 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MASK 0x000007e0 +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MSB 15 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_LSB 11 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MASK 0x0000f800 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_GET(x) (((x) & 0x0000f800) >> 11) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_SET(x) (((x) << 11) & 0x0000f800) +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MSB 23 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_LSB 16 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MASK 0x00ff0000 +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MSB 28 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_LSB 24 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MASK 0x1f000000 +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_SET(x) (((x) << 24) & 0x1f000000) +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MSB 29 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_LSB 29 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MASK 0x20000000 +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MSB 30 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_LSB 30 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MASK 0x40000000 +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_short_gi_delta_slope */ +#define PHY_BB_SHORT_GI_DELTA_SLOPE_ADDRESS 0x000099d0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_OFFSET 0x000099d0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MSB 3 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_LSB 0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MASK 0x0000000f +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MSB 18 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_LSB 4 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MASK 0x0007fff0 +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_GET(x) (((x) & 0x0007fff0) >> 4) +#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_SET(x) (((x) << 4) & 0x0007fff0) + +/* macros for BB_chaninfo_ctrl */ +#define PHY_BB_CHANINFO_CTRL_ADDRESS 0x000099dc +#define PHY_BB_CHANINFO_CTRL_OFFSET 0x000099dc +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB 0 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB 0 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK 0x00000001 +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB 1 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB 1 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK 0x00000002 +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x) (((x) << 1) & 0x00000002) + +/* macros for BB_heavy_clip_ctrl */ +#define PHY_BB_HEAVY_CLIP_CTRL_ADDRESS 0x000099e0 +#define PHY_BB_HEAVY_CLIP_CTRL_OFFSET 0x000099e0 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MSB 8 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_LSB 0 +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MASK 0x000001ff +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_SET(x) (((x) << 0) & 0x000001ff) +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MSB 9 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_LSB 9 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MASK 0x00000200 +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_SET(x) (((x) << 9) & 0x00000200) + +/* macros for BB_heavy_clip_20 */ +#define PHY_BB_HEAVY_CLIP_20_ADDRESS 0x000099e4 +#define PHY_BB_HEAVY_CLIP_20_OFFSET 0x000099e4 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MSB 7 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_LSB 0 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MASK 0x000000ff +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MSB 15 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_LSB 8 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MASK 0x0000ff00 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MSB 23 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_LSB 16 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MASK 0x00ff0000 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MSB 31 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_LSB 24 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MASK 0xff000000 +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_heavy_clip_40 */ +#define PHY_BB_HEAVY_CLIP_40_ADDRESS 0x000099e8 +#define PHY_BB_HEAVY_CLIP_40_OFFSET 0x000099e8 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MSB 7 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_LSB 0 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MASK 0x000000ff +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MSB 15 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_LSB 8 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MASK 0x0000ff00 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MSB 23 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_LSB 16 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MASK 0x00ff0000 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MSB 31 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_LSB 24 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MASK 0xff000000 +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_rifs_srch */ +#define PHY_BB_RIFS_SRCH_ADDRESS 0x000099ec +#define PHY_BB_RIFS_SRCH_OFFSET 0x000099ec +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MSB 7 +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_LSB 0 +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MASK 0x000000ff +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MSB 15 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_LSB 8 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MASK 0x0000ff00 +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MSB 25 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_LSB 16 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MASK 0x03ff0000 +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_SET(x) (((x) << 16) & 0x03ff0000) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MSB 26 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_LSB 26 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MASK 0x04000000 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MSB 27 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_LSB 27 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MASK 0x08000000 +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_iq_adc_cal_mode */ +#define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS 0x000099f0 +#define PHY_BB_IQ_ADC_CAL_MODE_OFFSET 0x000099f0 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB 1 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB 0 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK 0x00000003 +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x) (((x) & 0x00000003) >> 0) +#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x) (((x) << 0) & 0x00000003) +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB 2 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB 2 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK 0x00000004 +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x) (((x) << 2) & 0x00000004) + +/* macros for BB_per_chain_csd */ +#define PHY_BB_PER_CHAIN_CSD_ADDRESS 0x000099fc +#define PHY_BB_PER_CHAIN_CSD_OFFSET 0x000099fc +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MSB 4 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_LSB 0 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MASK 0x0000001f +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MSB 9 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_LSB 5 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MASK 0x000003e0 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MSB 14 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_LSB 10 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MASK 0x00007c00 +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_SET(x) (((x) << 10) & 0x00007c00) + +/* macros for BB_rx_ocgain */ +#define PHY_BB_RX_OCGAIN_ADDRESS 0x00009a00 +#define PHY_BB_RX_OCGAIN_OFFSET 0x00009a00 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MSB 31 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_LSB 0 +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MASK 0xffffffff +#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_crc */ +#define PHY_BB_TX_CRC_ADDRESS 0x00009c00 +#define PHY_BB_TX_CRC_OFFSET 0x00009c00 +#define PHY_BB_TX_CRC_TX_CRC_MSB 15 +#define PHY_BB_TX_CRC_TX_CRC_LSB 0 +#define PHY_BB_TX_CRC_TX_CRC_MASK 0x0000ffff +#define PHY_BB_TX_CRC_TX_CRC_GET(x) (((x) & 0x0000ffff) >> 0) + +/* macros for BB_iq_adc_meas_0_b0 */ +#define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS 0x00009c10 +#define PHY_BB_IQ_ADC_MEAS_0_B0_OFFSET 0x00009c10 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_1_b0 */ +#define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS 0x00009c14 +#define PHY_BB_IQ_ADC_MEAS_1_B0_OFFSET 0x00009c14 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_2_b0 */ +#define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS 0x00009c18 +#define PHY_BB_IQ_ADC_MEAS_2_B0_OFFSET 0x00009c18 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_iq_adc_meas_3_b0 */ +#define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS 0x00009c1c +#define PHY_BB_IQ_ADC_MEAS_3_B0_OFFSET 0x00009c1c +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB 31 +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB 0 +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK 0xffffffff +#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x) (((x) & 0xffffffff) >> 0) + +/* macros for BB_rfbus_grant */ +#define PHY_BB_RFBUS_GRANT_ADDRESS 0x00009c20 +#define PHY_BB_RFBUS_GRANT_OFFSET 0x00009c20 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB 0 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB 0 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK 0x00000001 +#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RFBUS_GRANT_BT_ANT_MSB 1 +#define PHY_BB_RFBUS_GRANT_BT_ANT_LSB 1 +#define PHY_BB_RFBUS_GRANT_BT_ANT_MASK 0x00000002 +#define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x) (((x) & 0x00000002) >> 1) + +/* macros for BB_tstadc */ +#define PHY_BB_TSTADC_ADDRESS 0x00009c24 +#define PHY_BB_TSTADC_OFFSET 0x00009c24 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_MSB 9 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_LSB 0 +#define PHY_BB_TSTADC_TSTADC_OUT_Q_MASK 0x000003ff +#define PHY_BB_TSTADC_TSTADC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_TSTADC_TSTADC_OUT_I_MSB 19 +#define PHY_BB_TSTADC_TSTADC_OUT_I_LSB 10 +#define PHY_BB_TSTADC_TSTADC_OUT_I_MASK 0x000ffc00 +#define PHY_BB_TSTADC_TSTADC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10) + +/* macros for BB_tstdac */ +#define PHY_BB_TSTDAC_ADDRESS 0x00009c28 +#define PHY_BB_TSTDAC_OFFSET 0x00009c28 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB 9 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB 0 +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK 0x000003ff +#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB 19 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB 10 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK 0x000ffc00 +#define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10) + +/* macros for BB_illegal_tx_rate */ +#define PHY_BB_ILLEGAL_TX_RATE_ADDRESS 0x00009c30 +#define PHY_BB_ILLEGAL_TX_RATE_OFFSET 0x00009c30 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MSB 0 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_LSB 0 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MASK 0x00000001 +#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_GET(x) (((x) & 0x00000001) >> 0) + +/* macros for BB_spur_report_b0 */ +#define PHY_BB_SPUR_REPORT_B0_ADDRESS 0x00009c34 +#define PHY_BB_SPUR_REPORT_B0_OFFSET 0x00009c34 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB 7 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB 0 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK 0x000000ff +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB 15 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB 8 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK 0x0000ff00 +#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB 31 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB 16 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK 0xffff0000 +#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x) (((x) & 0xffff0000) >> 16) + +/* macros for BB_channel_status */ +#define PHY_BB_CHANNEL_STATUS_ADDRESS 0x00009c38 +#define PHY_BB_CHANNEL_STATUS_OFFSET 0x00009c38 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB 0 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB 0 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK 0x00000001 +#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB 1 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB 1 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK 0x00000002 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB 2 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB 2 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK 0x00000004 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB 3 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB 3 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK 0x00000008 +#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB 5 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB 4 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK 0x00000030 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB 7 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB 6 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK 0x000000c0 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x) (((x) & 0x000000c0) >> 6) +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB 9 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB 8 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK 0x00000300 +#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB 13 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB 10 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK 0x00003c00 +#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB 16 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB 14 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK 0x0001c000 +#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x) (((x) & 0x0001c000) >> 14) + +/* macros for BB_rssi_b0 */ +#define PHY_BB_RSSI_B0_ADDRESS 0x00009c3c +#define PHY_BB_RSSI_B0_OFFSET 0x00009c3c +#define PHY_BB_RSSI_B0_RSSI_0_MSB 7 +#define PHY_BB_RSSI_B0_RSSI_0_LSB 0 +#define PHY_BB_RSSI_B0_RSSI_0_MASK 0x000000ff +#define PHY_BB_RSSI_B0_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RSSI_B0_RSSI_EXT_0_MSB 15 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_LSB 8 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_MASK 0x0000ff00 +#define PHY_BB_RSSI_B0_RSSI_EXT_0_GET(x) (((x) & 0x0000ff00) >> 8) + +/* macros for BB_spur_est_cck_report_b0 */ +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_ADDRESS 0x00009c40 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_OFFSET 0x00009c40 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MSB 7 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_LSB 0 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MASK 0x000000ff +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MSB 15 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_LSB 8 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MASK 0x0000ff00 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MSB 23 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_LSB 16 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MASK 0x00ff0000 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MSB 31 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_LSB 24 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MASK 0xff000000 +#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_GET(x) (((x) & 0xff000000) >> 24) + +/* macros for BB_chan_info_noise_pwr */ +#define PHY_BB_CHAN_INFO_NOISE_PWR_ADDRESS 0x00009cac +#define PHY_BB_CHAN_INFO_NOISE_PWR_OFFSET 0x00009cac +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MSB 11 +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_LSB 0 +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_GET(x) (((x) & 0x00000fff) >> 0) + +/* macros for BB_chan_info_gain_diff */ +#define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS 0x00009cb0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_OFFSET 0x00009cb0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MSB 11 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_LSB 0 +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_GET(x) (((x) & 0x00000fff) >> 0) + +/* macros for BB_chan_info_fine_timing */ +#define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS 0x00009cb4 +#define PHY_BB_CHAN_INFO_FINE_TIMING_OFFSET 0x00009cb4 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB 11 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB 0 +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK 0x00000fff +#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB 21 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB 12 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK 0x003ff000 +#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x) (((x) & 0x003ff000) >> 12) + +/* macros for BB_chan_info_gain_b0 */ +#define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS 0x00009cb8 +#define PHY_BB_CHAN_INFO_GAIN_B0_OFFSET 0x00009cb8 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB 7 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB 0 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK 0x000000ff +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB 15 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB 8 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK 0x0000ff00 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB 16 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB 16 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK 0x00010000 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB 17 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB 17 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK 0x00020000 +#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x) (((x) & 0x00020000) >> 17) + +/* macros for BB_chan_info_chan_tab_b0 */ +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_ADDRESS 0x00009cbc +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_OFFSET 0x00009cbc +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MSB 5 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_LSB 0 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MASK 0x0000003f +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MSB 11 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_LSB 6 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MASK 0x00000fc0 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MSB 15 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_LSB 12 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MASK 0x0000f000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MSB 21 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_LSB 16 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MASK 0x003f0000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MSB 27 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_LSB 22 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MASK 0x0fc00000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MSB 31 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_LSB 28 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MASK 0xf0000000 +#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_GET(x) (((x) & 0xf0000000) >> 28) + +/* macros for BB_paprd_am2am_mask */ +#define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS 0x00009de4 +#define PHY_BB_PAPRD_AM2AM_MASK_OFFSET 0x00009de4 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB 24 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB 0 +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_am2pm_mask */ +#define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS 0x00009de8 +#define PHY_BB_PAPRD_AM2PM_MASK_OFFSET 0x00009de8 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB 24 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB 0 +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_ht40_mask */ +#define PHY_BB_PAPRD_HT40_MASK_ADDRESS 0x00009dec +#define PHY_BB_PAPRD_HT40_MASK_OFFSET 0x00009dec +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB 24 +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB 0 +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK 0x01ffffff +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x) (((x) & 0x01ffffff) >> 0) +#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x) (((x) << 0) & 0x01ffffff) + +/* macros for BB_paprd_ctrl0 */ +#define PHY_BB_PAPRD_CTRL0_ADDRESS 0x00009df0 +#define PHY_BB_PAPRD_CTRL0_OFFSET 0x00009df0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MSB 0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_LSB 0 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MSB 1 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_LSB 1 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MASK 0x00000002 +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MSB 26 +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_LSB 2 +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MASK 0x07fffffc +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_GET(x) (((x) & 0x07fffffc) >> 2) +#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_SET(x) (((x) << 2) & 0x07fffffc) +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MSB 31 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_LSB 27 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MASK 0xf8000000 +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_GET(x) (((x) & 0xf8000000) >> 27) +#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_SET(x) (((x) << 27) & 0xf8000000) + +/* macros for BB_paprd_ctrl1 */ +#define PHY_BB_PAPRD_CTRL1_ADDRESS 0x00009df4 +#define PHY_BB_PAPRD_CTRL1_OFFSET 0x00009df4 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MSB 0 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_LSB 0 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MSB 1 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_LSB 1 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MASK 0x00000002 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MSB 2 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_LSB 2 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MASK 0x00000004 +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MSB 8 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_LSB 3 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MASK 0x000001f8 +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_GET(x) (((x) & 0x000001f8) >> 3) +#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_SET(x) (((x) << 3) & 0x000001f8) +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MSB 16 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_LSB 9 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MASK 0x0001fe00 +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_GET(x) (((x) & 0x0001fe00) >> 9) +#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_SET(x) (((x) << 9) & 0x0001fe00) +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MSB 26 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_LSB 17 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MASK 0x07fe0000 +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_GET(x) (((x) & 0x07fe0000) >> 17) +#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_SET(x) (((x) << 17) & 0x07fe0000) +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MSB 27 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_LSB 27 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MASK 0x08000000 +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_pa_gain123 */ +#define PHY_BB_PA_GAIN123_ADDRESS 0x00009df8 +#define PHY_BB_PA_GAIN123_OFFSET 0x00009df8 +#define PHY_BB_PA_GAIN123_PA_GAIN1_MSB 9 +#define PHY_BB_PA_GAIN123_PA_GAIN1_LSB 0 +#define PHY_BB_PA_GAIN123_PA_GAIN1_MASK 0x000003ff +#define PHY_BB_PA_GAIN123_PA_GAIN1_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PA_GAIN123_PA_GAIN1_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PA_GAIN123_PA_GAIN2_MSB 19 +#define PHY_BB_PA_GAIN123_PA_GAIN2_LSB 10 +#define PHY_BB_PA_GAIN123_PA_GAIN2_MASK 0x000ffc00 +#define PHY_BB_PA_GAIN123_PA_GAIN2_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_PA_GAIN123_PA_GAIN2_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_PA_GAIN123_PA_GAIN3_MSB 29 +#define PHY_BB_PA_GAIN123_PA_GAIN3_LSB 20 +#define PHY_BB_PA_GAIN123_PA_GAIN3_MASK 0x3ff00000 +#define PHY_BB_PA_GAIN123_PA_GAIN3_GET(x) (((x) & 0x3ff00000) >> 20) +#define PHY_BB_PA_GAIN123_PA_GAIN3_SET(x) (((x) << 20) & 0x3ff00000) + +/* macros for BB_pa_gain45 */ +#define PHY_BB_PA_GAIN45_ADDRESS 0x00009dfc +#define PHY_BB_PA_GAIN45_OFFSET 0x00009dfc +#define PHY_BB_PA_GAIN45_PA_GAIN4_MSB 9 +#define PHY_BB_PA_GAIN45_PA_GAIN4_LSB 0 +#define PHY_BB_PA_GAIN45_PA_GAIN4_MASK 0x000003ff +#define PHY_BB_PA_GAIN45_PA_GAIN4_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PA_GAIN45_PA_GAIN4_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PA_GAIN45_PA_GAIN5_MSB 19 +#define PHY_BB_PA_GAIN45_PA_GAIN5_LSB 10 +#define PHY_BB_PA_GAIN45_PA_GAIN5_MASK 0x000ffc00 +#define PHY_BB_PA_GAIN45_PA_GAIN5_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_PA_GAIN45_PA_GAIN5_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MSB 24 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_LSB 20 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MASK 0x01f00000 +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_SET(x) (((x) << 20) & 0x01f00000) + +/* macros for BB_paprd_pre_post_scale_0 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_ADDRESS 0x00009e00 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_OFFSET 0x00009e00 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_1 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_ADDRESS 0x00009e04 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_OFFSET 0x00009e04 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_2 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_ADDRESS 0x00009e08 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_OFFSET 0x00009e08 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_3 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_ADDRESS 0x00009e0c +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_OFFSET 0x00009e0c +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_4 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_ADDRESS 0x00009e10 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_OFFSET 0x00009e10 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_5 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_ADDRESS 0x00009e14 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_OFFSET 0x00009e14 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_6 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_ADDRESS 0x00009e18 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_OFFSET 0x00009e18 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_pre_post_scale_7 */ +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_ADDRESS 0x00009e1c +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_OFFSET 0x00009e1c +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MSB 17 +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_LSB 0 +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MASK 0x0003ffff +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_GET(x) (((x) & 0x0003ffff) >> 0) +#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_SET(x) (((x) << 0) & 0x0003ffff) + +/* macros for BB_paprd_mem_tab */ +#define PHY_BB_PAPRD_MEM_TAB_ADDRESS 0x00009e20 +#define PHY_BB_PAPRD_MEM_TAB_OFFSET 0x00009e20 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MSB 21 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_LSB 0 +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MASK 0x003fffff +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_GET(x) (((x) & 0x003fffff) >> 0) +#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_SET(x) (((x) << 0) & 0x003fffff) + +/* macros for BB_peak_det_ctrl_1 */ +#define PHY_BB_PEAK_DET_CTRL_1_ADDRESS 0x0000a000 +#define PHY_BB_PEAK_DET_CTRL_1_OFFSET 0x0000a000 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MSB 0 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_LSB 0 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MASK 0x00000001 +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MSB 1 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_LSB 1 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MASK 0x00000002 +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MSB 7 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_LSB 2 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MASK 0x000000fc +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_GET(x) (((x) & 0x000000fc) >> 2) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_SET(x) (((x) << 2) & 0x000000fc) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MSB 12 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_LSB 8 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MASK 0x00001f00 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_GET(x) (((x) & 0x00001f00) >> 8) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_SET(x) (((x) << 8) & 0x00001f00) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MSB 17 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_LSB 13 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MASK 0x0003e000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_GET(x) (((x) & 0x0003e000) >> 13) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_SET(x) (((x) << 13) & 0x0003e000) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MSB 22 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_LSB 18 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MASK 0x007c0000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_GET(x) (((x) & 0x007c0000) >> 18) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_SET(x) (((x) << 18) & 0x007c0000) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MSB 29 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_LSB 23 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MASK 0x3f800000 +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_SET(x) (((x) << 23) & 0x3f800000) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MSB 30 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_LSB 30 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MASK 0x40000000 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MSB 31 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_LSB 31 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MASK 0x80000000 +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_peak_det_ctrl_2 */ +#define PHY_BB_PEAK_DET_CTRL_2_ADDRESS 0x0000a004 +#define PHY_BB_PEAK_DET_CTRL_2_OFFSET 0x0000a004 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MSB 9 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_LSB 0 +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MASK 0x000003ff +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MSB 14 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_LSB 10 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MASK 0x00007c00 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MSB 19 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_LSB 15 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MASK 0x000f8000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MSB 24 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_LSB 20 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MASK 0x01f00000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MSB 29 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_LSB 25 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MASK 0x3e000000 +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_rx_gain_bounds_1 */ +#define PHY_BB_RX_GAIN_BOUNDS_1_ADDRESS 0x0000a008 +#define PHY_BB_RX_GAIN_BOUNDS_1_OFFSET 0x0000a008 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MSB 7 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_LSB 0 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MASK 0x000000ff +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MSB 15 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_LSB 8 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MASK 0x0000ff00 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MSB 23 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_LSB 16 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MASK 0x00ff0000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_LSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MASK 0x01000000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MSB 25 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_LSB 25 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MASK 0x02000000 +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_SET(x) (((x) << 25) & 0x02000000) + +/* macros for BB_rx_gain_bounds_2 */ +#define PHY_BB_RX_GAIN_BOUNDS_2_ADDRESS 0x0000a00c +#define PHY_BB_RX_GAIN_BOUNDS_2_OFFSET 0x0000a00c +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MSB 7 +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_LSB 0 +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MASK 0x000000ff +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MSB 15 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_LSB 8 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MASK 0x0000ff00 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MSB 23 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_LSB 16 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MASK 0x00ff0000 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MSB 31 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_LSB 24 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MASK 0xff000000 +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_peak_det_cal_ctrl */ +#define PHY_BB_PEAK_DET_CAL_CTRL_ADDRESS 0x0000a010 +#define PHY_BB_PEAK_DET_CAL_CTRL_OFFSET 0x0000a010 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MSB 5 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_LSB 0 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MASK 0x0000003f +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MSB 11 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_LSB 6 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MASK 0x00000fc0 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MSB 13 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_LSB 12 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MASK 0x00003000 +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000) + +/* macros for BB_agc_dig_dc_ctrl */ +#define PHY_BB_AGC_DIG_DC_CTRL_ADDRESS 0x0000a014 +#define PHY_BB_AGC_DIG_DC_CTRL_OFFSET 0x0000a014 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MSB 0 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_LSB 0 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MASK 0x00000001 +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MSB 3 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_LSB 1 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MASK 0x0000000e +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MSB 9 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_LSB 4 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MASK 0x000003f0 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MSB 31 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_LSB 16 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MASK 0xffff0000 +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_GET(x) (((x) & 0xffff0000) >> 16) +#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_SET(x) (((x) << 16) & 0xffff0000) + +/* macros for BB_agc_dig_dc_status_i_b0 */ +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_ADDRESS 0x0000a018 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_OFFSET 0x0000a018 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MSB 8 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_LSB 0 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MASK 0x000001ff +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MSB 17 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_LSB 9 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MASK 0x0003fe00 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_GET(x) (((x) & 0x0003fe00) >> 9) +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MSB 26 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_LSB 18 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MASK 0x07fc0000 +#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_GET(x) (((x) & 0x07fc0000) >> 18) + +/* macros for BB_agc_dig_dc_status_q_b0 */ +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_ADDRESS 0x0000a01c +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_OFFSET 0x0000a01c +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MSB 8 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_LSB 0 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MASK 0x000001ff +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_GET(x) (((x) & 0x000001ff) >> 0) +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MSB 17 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_LSB 9 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MASK 0x0003fe00 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_GET(x) (((x) & 0x0003fe00) >> 9) +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MSB 26 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_LSB 18 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MASK 0x07fc0000 +#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_GET(x) (((x) & 0x07fc0000) >> 18) + +/* macros for BB_bbb_txfir_0 */ +#define PHY_BB_BBB_TXFIR_0_ADDRESS 0x0000a1f4 +#define PHY_BB_BBB_TXFIR_0_OFFSET 0x0000a1f4 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB 3 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB 0 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK 0x0000000f +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB 11 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB 8 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK 0x00000f00 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB 20 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB 16 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK 0x001f0000 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB 28 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB 24 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK 0x1f000000 +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x) (((x) & 0x1f000000) >> 24) +#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x) (((x) << 24) & 0x1f000000) + +/* macros for BB_bbb_txfir_1 */ +#define PHY_BB_BBB_TXFIR_1_ADDRESS 0x0000a1f8 +#define PHY_BB_BBB_TXFIR_1_OFFSET 0x0000a1f8 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB 5 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB 0 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK 0x0000003f +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB 13 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB 8 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK 0x00003f00 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB 22 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB 16 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK 0x007f0000 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x) (((x) & 0x007f0000) >> 16) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x) (((x) << 16) & 0x007f0000) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB 30 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB 24 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK 0x7f000000 +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x) (((x) << 24) & 0x7f000000) + +/* macros for BB_bbb_txfir_2 */ +#define PHY_BB_BBB_TXFIR_2_ADDRESS 0x0000a1fc +#define PHY_BB_BBB_TXFIR_2_OFFSET 0x0000a1fc +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB 7 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB 0 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK 0x000000ff +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB 15 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB 8 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK 0x0000ff00 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB 23 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB 16 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK 0x00ff0000 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB 31 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB 24 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK 0xff000000 +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_modes_select */ +#define PHY_BB_MODES_SELECT_ADDRESS 0x0000a200 +#define PHY_BB_MODES_SELECT_OFFSET 0x0000a200 +#define PHY_BB_MODES_SELECT_CCK_MODE_MSB 0 +#define PHY_BB_MODES_SELECT_CCK_MODE_LSB 0 +#define PHY_BB_MODES_SELECT_CCK_MODE_MASK 0x00000001 +#define PHY_BB_MODES_SELECT_CCK_MODE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_MODES_SELECT_CCK_MODE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB 2 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB 2 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK 0x00000004 +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB 5 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB 5 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK 0x00000020 +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB 6 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB 6 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK 0x00000040 +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB 7 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB 7 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK 0x00000080 +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB 8 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB 8 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK 0x00000100 +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x) (((x) << 8) & 0x00000100) + +/* macros for BB_bbb_tx_ctrl */ +#define PHY_BB_BBB_TX_CTRL_ADDRESS 0x0000a204 +#define PHY_BB_BBB_TX_CTRL_OFFSET 0x0000a204 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB 0 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB 0 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK 0x00000001 +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB 1 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB 1 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK 0x00000002 +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB 3 +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB 2 +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK 0x0000000c +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB 4 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB 4 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK 0x00000010 +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB 5 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB 5 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK 0x00000020 +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB 8 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB 6 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK 0x000001c0 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x) (((x) & 0x000001c0) >> 6) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x) (((x) << 6) & 0x000001c0) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB 11 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB 9 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK 0x00000e00 +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x) (((x) & 0x00000e00) >> 9) +#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x) (((x) << 9) & 0x00000e00) + +/* macros for BB_bbb_sig_detect */ +#define PHY_BB_BBB_SIG_DETECT_ADDRESS 0x0000a208 +#define PHY_BB_BBB_SIG_DETECT_OFFSET 0x0000a208 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MSB 5 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_LSB 0 +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MASK 0x0000003f +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MSB 12 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_LSB 6 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MASK 0x00001fc0 +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_GET(x) (((x) & 0x00001fc0) >> 6) +#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_SET(x) (((x) << 6) & 0x00001fc0) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MSB 13 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_LSB 13 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MASK 0x00002000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MSB 14 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_LSB 14 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MASK 0x00004000 +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MSB 15 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_LSB 15 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MASK 0x00008000 +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MSB 16 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_LSB 16 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MASK 0x00010000 +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MSB 17 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_LSB 17 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MASK 0x00020000 +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MSB 18 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_LSB 18 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MASK 0x00040000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MSB 19 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_LSB 19 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MASK 0x00080000 +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MSB 20 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_LSB 20 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MASK 0x00100000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MSB 21 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_LSB 21 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MASK 0x00200000 +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MSB 22 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_LSB 22 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MASK 0x00400000 +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MSB 31 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_LSB 31 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MASK 0x80000000 +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_ext_atten_switch_ctl_b0 */ +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_ADDRESS 0x0000a20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_OFFSET 0x0000a20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MSB 5 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_LSB 0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MASK 0x0000003f +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MSB 11 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_LSB 6 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MASK 0x00000fc0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MSB 16 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_LSB 12 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MASK 0x0001f000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MSB 21 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_LSB 17 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MASK 0x003e0000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_SET(x) (((x) << 17) & 0x003e0000) + +/* macros for BB_bbb_rx_ctrl_1 */ +#define PHY_BB_BBB_RX_CTRL_1_ADDRESS 0x0000a210 +#define PHY_BB_BBB_RX_CTRL_1_OFFSET 0x0000a210 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MSB 2 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_LSB 0 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MASK 0x00000007 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MSB 7 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_LSB 3 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MASK 0x000000f8 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_GET(x) (((x) & 0x000000f8) >> 3) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_SET(x) (((x) << 3) & 0x000000f8) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MSB 10 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_LSB 8 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MASK 0x00000700 +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_GET(x) (((x) & 0x00000700) >> 8) +#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_SET(x) (((x) << 8) & 0x00000700) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MSB 15 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_LSB 11 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MASK 0x0000f800 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_GET(x) (((x) & 0x0000f800) >> 11) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_SET(x) (((x) << 11) & 0x0000f800) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MSB 20 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_LSB 16 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MASK 0x001f0000 +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MSB 23 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_LSB 21 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MASK 0x00e00000 +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_GET(x) (((x) & 0x00e00000) >> 21) +#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_SET(x) (((x) << 21) & 0x00e00000) +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MSB 30 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_LSB 24 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MASK 0x7f000000 +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_GET(x) (((x) & 0x7f000000) >> 24) +#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_SET(x) (((x) << 24) & 0x7f000000) +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MSB 31 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_LSB 31 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MASK 0x80000000 +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_bbb_rx_ctrl_2 */ +#define PHY_BB_BBB_RX_CTRL_2_ADDRESS 0x0000a214 +#define PHY_BB_BBB_RX_CTRL_2_OFFSET 0x0000a214 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MSB 5 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_LSB 0 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MASK 0x0000003f +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MSB 11 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_LSB 6 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MASK 0x00000fc0 +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MSB 16 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_LSB 12 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MASK 0x0001f000 +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MSB 21 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_LSB 17 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MASK 0x003e0000 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_SET(x) (((x) << 17) & 0x003e0000) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MSB 25 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_LSB 22 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MASK 0x03c00000 +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_GET(x) (((x) & 0x03c00000) >> 22) +#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_SET(x) (((x) << 22) & 0x03c00000) +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MSB 31 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_LSB 26 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MASK 0xfc000000 +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_GET(x) (((x) & 0xfc000000) >> 26) +#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_SET(x) (((x) << 26) & 0xfc000000) + +/* macros for BB_bbb_rx_ctrl_3 */ +#define PHY_BB_BBB_RX_CTRL_3_ADDRESS 0x0000a218 +#define PHY_BB_BBB_RX_CTRL_3_OFFSET 0x0000a218 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MSB 7 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_LSB 0 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MASK 0x000000ff +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MSB 15 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_LSB 8 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MASK 0x0000ff00 +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MSB 23 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_LSB 16 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MASK 0x00ff0000 +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_SET(x) (((x) << 16) & 0x00ff0000) + +/* macros for BB_bbb_rx_ctrl_4 */ +#define PHY_BB_BBB_RX_CTRL_4_ADDRESS 0x0000a21c +#define PHY_BB_BBB_RX_CTRL_4_OFFSET 0x0000a21c +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MSB 3 +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_LSB 0 +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MASK 0x0000000f +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MSB 15 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_LSB 4 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MASK 0x0000fff0 +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_GET(x) (((x) & 0x0000fff0) >> 4) +#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_SET(x) (((x) << 4) & 0x0000fff0) +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MSB 16 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_LSB 16 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MASK 0x00010000 +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MSB 17 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_LSB 17 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MASK 0x00020000 +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MSB 18 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_LSB 18 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MASK 0x00040000 +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MSB 24 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_LSB 19 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MASK 0x01f80000 +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_GET(x) (((x) & 0x01f80000) >> 19) +#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_SET(x) (((x) << 19) & 0x01f80000) +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MSB 30 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_LSB 25 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MASK 0x7e000000 +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_GET(x) (((x) & 0x7e000000) >> 25) +#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_SET(x) (((x) << 25) & 0x7e000000) + +/* macros for BB_bbb_rx_ctrl_5 */ +#define PHY_BB_BBB_RX_CTRL_5_ADDRESS 0x0000a220 +#define PHY_BB_BBB_RX_CTRL_5_OFFSET 0x0000a220 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MSB 4 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_LSB 0 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MASK 0x0000001f +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MSB 9 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_LSB 5 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MASK 0x000003e0 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MSB 15 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_LSB 10 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MASK 0x0000fc00 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_GET(x) (((x) & 0x0000fc00) >> 10) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_SET(x) (((x) << 10) & 0x0000fc00) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MSB 20 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_LSB 16 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MASK 0x001f0000 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MSB 26 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_LSB 21 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MASK 0x07e00000 +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_bbb_rx_ctrl_6 */ +#define PHY_BB_BBB_RX_CTRL_6_ADDRESS 0x0000a224 +#define PHY_BB_BBB_RX_CTRL_6_OFFSET 0x0000a224 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MSB 9 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_LSB 0 +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MASK 0x000003ff +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MSB 10 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_LSB 10 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MASK 0x00000400 +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MSB 20 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_LSB 11 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MASK 0x001ff800 +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_GET(x) (((x) & 0x001ff800) >> 11) +#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_SET(x) (((x) << 11) & 0x001ff800) + +/* macros for BB_bbb_dagc_ctrl */ +#define PHY_BB_BBB_DAGC_CTRL_ADDRESS 0x0000a228 +#define PHY_BB_BBB_DAGC_CTRL_OFFSET 0x0000a228 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MSB 0 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_LSB 0 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MASK 0x00000001 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MSB 8 +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_LSB 1 +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MASK 0x000001fe +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MSB 9 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_LSB 9 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MASK 0x00000200 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MSB 16 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_LSB 10 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MASK 0x0001fc00 +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_GET(x) (((x) & 0x0001fc00) >> 10) +#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_SET(x) (((x) << 10) & 0x0001fc00) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MSB 17 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_LSB 17 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MASK 0x00020000 +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MSB 23 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_LSB 18 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MASK 0x00fc0000 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MSB 27 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_LSB 24 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MASK 0x0f000000 +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_SET(x) (((x) << 24) & 0x0f000000) + +/* macros for BB_force_clken_cck */ +#define PHY_BB_FORCE_CLKEN_CCK_ADDRESS 0x0000a22c +#define PHY_BB_FORCE_CLKEN_CCK_OFFSET 0x0000a22c +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MSB 0 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_LSB 0 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MASK 0x00000001 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MSB 1 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_LSB 1 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MASK 0x00000002 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MSB 2 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_LSB 2 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MASK 0x00000004 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MSB 3 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_LSB 3 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MASK 0x00000008 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MSB 4 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_LSB 4 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MASK 0x00000010 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MSB 5 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_LSB 5 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MASK 0x00000020 +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_SET(x) (((x) << 5) & 0x00000020) + +/* macros for BB_rx_clear_delay */ +#define PHY_BB_RX_CLEAR_DELAY_ADDRESS 0x0000a230 +#define PHY_BB_RX_CLEAR_DELAY_OFFSET 0x0000a230 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MSB 9 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_LSB 0 +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MASK 0x000003ff +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_SET(x) (((x) << 0) & 0x000003ff) + +/* macros for BB_powertx_rate3 */ +#define PHY_BB_POWERTX_RATE3_ADDRESS 0x0000a234 +#define PHY_BB_POWERTX_RATE3_OFFSET 0x0000a234 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MSB 5 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_LSB 0 +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE3_POWERTX_1L_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MSB 21 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_LSB 16 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE3_POWERTX_2L_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MSB 29 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_LSB 24 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE3_POWERTX_2S_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate4 */ +#define PHY_BB_POWERTX_RATE4_ADDRESS 0x0000a238 +#define PHY_BB_POWERTX_RATE4_OFFSET 0x0000a238 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MSB 5 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_LSB 0 +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE4_POWERTX_55L_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MSB 13 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_LSB 8 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE4_POWERTX_55S_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MSB 21 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_LSB 16 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE4_POWERTX_11L_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MSB 29 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_LSB 24 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE4_POWERTX_11S_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_cck_spur_mit */ +#define PHY_BB_CCK_SPUR_MIT_ADDRESS 0x0000a240 +#define PHY_BB_CCK_SPUR_MIT_OFFSET 0x0000a240 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MSB 0 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_LSB 0 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MASK 0x00000001 +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MSB 8 +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_LSB 1 +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MASK 0x000001fe +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_SET(x) (((x) << 1) & 0x000001fe) +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MSB 28 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_LSB 9 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MASK 0x1ffffe00 +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_GET(x) (((x) & 0x1ffffe00) >> 9) +#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_SET(x) (((x) << 9) & 0x1ffffe00) +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MSB 30 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_LSB 29 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MASK 0x60000000 +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_SET(x) (((x) << 29) & 0x60000000) + +/* macros for BB_panic_watchdog_status */ +#define PHY_BB_PANIC_WATCHDOG_STATUS_ADDRESS 0x0000a244 +#define PHY_BB_PANIC_WATCHDOG_STATUS_OFFSET 0x0000a244 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MSB 2 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MASK 0x00000007 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MSB 3 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_LSB 3 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MASK 0x00000008 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MSB 7 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_LSB 4 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MASK 0x000000f0 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MSB 11 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_LSB 8 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MASK 0x00000f00 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_GET(x) (((x) & 0x00000f00) >> 8) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_SET(x) (((x) << 8) & 0x00000f00) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MSB 15 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_LSB 12 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MASK 0x0000f000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MSB 19 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_LSB 16 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MASK 0x000f0000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_GET(x) (((x) & 0x000f0000) >> 16) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_SET(x) (((x) << 16) & 0x000f0000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MSB 23 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_LSB 20 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MASK 0x00f00000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MSB 27 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_LSB 24 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MASK 0x0f000000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MSB 31 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_LSB 28 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MASK 0xf0000000 +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_GET(x) (((x) & 0xf0000000) >> 28) +#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_SET(x) (((x) << 28) & 0xf0000000) + +/* macros for BB_panic_watchdog_ctrl_1 */ +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ADDRESS 0x0000a248 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_OFFSET 0x0000a248 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MASK 0x00000001 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_LSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MASK 0x00000002 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MSB 15 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_LSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MASK 0x0000fffc +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_GET(x) (((x) & 0x0000fffc) >> 2) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_SET(x) (((x) << 2) & 0x0000fffc) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MSB 31 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_LSB 16 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MASK 0xffff0000 +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_GET(x) (((x) & 0xffff0000) >> 16) +#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_SET(x) (((x) << 16) & 0xffff0000) + +/* macros for BB_panic_watchdog_ctrl_2 */ +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_ADDRESS 0x0000a24c +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_OFFSET 0x0000a24c +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB 0 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK 0x00000001 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_LSB 1 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MASK 0x00000002 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_LSB 2 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MASK 0x00000004 +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_SET(x) (((x) << 2) & 0x00000004) + +/* macros for BB_iqcorr_ctrl_cck */ +#define PHY_BB_IQCORR_CTRL_CCK_ADDRESS 0x0000a250 +#define PHY_BB_IQCORR_CTRL_CCK_OFFSET 0x0000a250 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MSB 4 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_LSB 0 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MASK 0x0000001f +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MSB 10 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_LSB 5 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MASK 0x000007e0 +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_GET(x) (((x) & 0x000007e0) >> 5) +#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_SET(x) (((x) << 5) & 0x000007e0) +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MSB 11 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_LSB 11 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MASK 0x00000800 +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MSB 13 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_LSB 12 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MASK 0x00003000 +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12) +#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000) +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MSB 15 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_LSB 14 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MASK 0x0000c000 +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MSB 20 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_LSB 16 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MASK 0x001f0000 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MSB 21 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_LSB 21 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MASK 0x00200000 +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_SET(x) (((x) << 21) & 0x00200000) + +/* macros for BB_bluetooth_cntl */ +#define PHY_BB_BLUETOOTH_CNTL_ADDRESS 0x0000a254 +#define PHY_BB_BLUETOOTH_CNTL_OFFSET 0x0000a254 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB 0 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB 0 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK 0x00000001 +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB 1 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB 1 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK 0x00000002 +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x) (((x) << 1) & 0x00000002) + +/* macros for BB_tpc_1 */ +#define PHY_BB_TPC_1_ADDRESS 0x0000a258 +#define PHY_BB_TPC_1_OFFSET 0x0000a258 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MSB 0 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_LSB 0 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MASK 0x00000001 +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_1_FORCE_DAC_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MSB 5 +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_LSB 1 +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MASK 0x0000003e +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_TPC_1_FORCED_DAC_GAIN_SET(x) (((x) << 1) & 0x0000003e) +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MSB 13 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_LSB 6 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MASK 0x00003fc0 +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_GET(x) (((x) & 0x00003fc0) >> 6) +#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_SET(x) (((x) << 6) & 0x00003fc0) +#define PHY_BB_TPC_1_NUM_PD_GAIN_MSB 15 +#define PHY_BB_TPC_1_NUM_PD_GAIN_LSB 14 +#define PHY_BB_TPC_1_NUM_PD_GAIN_MASK 0x0000c000 +#define PHY_BB_TPC_1_NUM_PD_GAIN_GET(x) (((x) & 0x0000c000) >> 14) +#define PHY_BB_TPC_1_NUM_PD_GAIN_SET(x) (((x) << 14) & 0x0000c000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MSB 17 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_LSB 16 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MASK 0x00030000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_GET(x) (((x) & 0x00030000) >> 16) +#define PHY_BB_TPC_1_PD_GAIN_SETTING1_SET(x) (((x) << 16) & 0x00030000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MSB 19 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_LSB 18 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MASK 0x000c0000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_GET(x) (((x) & 0x000c0000) >> 18) +#define PHY_BB_TPC_1_PD_GAIN_SETTING2_SET(x) (((x) << 18) & 0x000c0000) +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MSB 21 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_LSB 20 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MASK 0x00300000 +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_GET(x) (((x) & 0x00300000) >> 20) +#define PHY_BB_TPC_1_PD_GAIN_SETTING3_SET(x) (((x) << 20) & 0x00300000) +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MSB 22 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_LSB 22 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MASK 0x00400000 +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MSB 28 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_LSB 23 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MASK 0x1f800000 +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_GET(x) (((x) & 0x1f800000) >> 23) +#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_SET(x) (((x) << 23) & 0x1f800000) +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MSB 29 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_LSB 29 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MASK 0x20000000 +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MSB 31 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_LSB 30 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MASK 0xc0000000 +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_GET(x) (((x) & 0xc0000000) >> 30) +#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_SET(x) (((x) << 30) & 0xc0000000) + +/* macros for BB_tpc_2 */ +#define PHY_BB_TPC_2_ADDRESS 0x0000a25c +#define PHY_BB_TPC_2_OFFSET 0x0000a25c +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB 7 +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB 0 +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK 0x000000ff +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB 15 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB 8 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK 0x0000ff00 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB 23 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB 16 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK 0x00ff0000 +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x) (((x) << 16) & 0x00ff0000) + +/* macros for BB_tpc_3 */ +#define PHY_BB_TPC_3_ADDRESS 0x0000a260 +#define PHY_BB_TPC_3_OFFSET 0x0000a260 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB 7 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB 0 +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK 0x000000ff +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB 15 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB 8 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK 0x0000ff00 +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MSB 18 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_LSB 16 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MASK 0x00070000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MSB 21 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_LSB 19 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MASK 0x00380000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_GET(x) (((x) & 0x00380000) >> 19) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_SET(x) (((x) << 19) & 0x00380000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB 24 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB 22 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK 0x01c00000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x) (((x) & 0x01c00000) >> 22) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x) (((x) << 22) & 0x01c00000) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB 27 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB 25 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK 0x0e000000 +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x) (((x) & 0x0e000000) >> 25) +#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x) (((x) << 25) & 0x0e000000) +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB 31 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB 31 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK 0x80000000 +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_tpc_4_b0 */ +#define PHY_BB_TPC_4_B0_ADDRESS 0x0000a264 +#define PHY_BB_TPC_4_B0_OFFSET 0x0000a264 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MSB 0 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_LSB 0 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MASK 0x00000001 +#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MSB 8 +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_LSB 1 +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MASK 0x000001fe +#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_GET(x) (((x) & 0x000001fe) >> 1) +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MSB 13 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_LSB 9 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MASK 0x00003e00 +#define PHY_BB_TPC_4_B0_DAC_GAIN_0_GET(x) (((x) & 0x00003e00) >> 9) +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MSB 19 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_LSB 14 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MASK 0x000fc000 +#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_GET(x) (((x) & 0x000fc000) >> 14) +#define PHY_BB_TPC_4_B0_RATE_SENT_0_MSB 24 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_LSB 20 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_MASK 0x01f00000 +#define PHY_BB_TPC_4_B0_RATE_SENT_0_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MSB 30 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_LSB 25 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MASK 0x7e000000 +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_GET(x) (((x) & 0x7e000000) >> 25) +#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_SET(x) (((x) << 25) & 0x7e000000) + +/* macros for BB_analog_swap */ +#define PHY_BB_ANALOG_SWAP_ADDRESS 0x0000a268 +#define PHY_BB_ANALOG_SWAP_OFFSET 0x0000a268 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB 2 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB 0 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK 0x00000007 +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB 5 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB 3 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK 0x00000038 +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x) (((x) & 0x00000038) >> 3) +#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x) (((x) << 3) & 0x00000038) +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB 6 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB 6 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK 0x00000040 +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB 7 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB 7 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK 0x00000080 +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB 8 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB 8 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK 0x00000100 +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x) (((x) << 8) & 0x00000100) + +/* macros for BB_tpc_5_b0 */ +#define PHY_BB_TPC_5_B0_ADDRESS 0x0000a26c +#define PHY_BB_TPC_5_B0_OFFSET 0x0000a26c +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MSB 3 +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_LSB 0 +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MASK 0x0000000f +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MSB 9 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_LSB 4 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MASK 0x000003f0 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MSB 15 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_LSB 10 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MASK 0x0000fc00 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_GET(x) (((x) & 0x0000fc00) >> 10) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_SET(x) (((x) << 10) & 0x0000fc00) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MSB 21 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_LSB 16 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MASK 0x003f0000 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MSB 27 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_LSB 22 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MASK 0x0fc00000 +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_GET(x) (((x) & 0x0fc00000) >> 22) +#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_SET(x) (((x) << 22) & 0x0fc00000) + +/* macros for BB_tpc_6_b0 */ +#define PHY_BB_TPC_6_B0_ADDRESS 0x0000a270 +#define PHY_BB_TPC_6_B0_OFFSET 0x0000a270 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MSB 5 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_LSB 0 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MASK 0x0000003f +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MSB 11 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_LSB 6 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MASK 0x00000fc0 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MSB 17 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_LSB 12 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MASK 0x0003f000 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MSB 23 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_LSB 18 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MASK 0x00fc0000 +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_SET(x) (((x) << 18) & 0x00fc0000) +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MSB 25 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_LSB 24 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MASK 0x03000000 +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_SET(x) (((x) << 24) & 0x03000000) +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MSB 28 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_LSB 26 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MASK 0x1c000000 +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_GET(x) (((x) & 0x1c000000) >> 26) +#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_SET(x) (((x) << 26) & 0x1c000000) + +/* macros for BB_tpc_7 */ +#define PHY_BB_TPC_7_ADDRESS 0x0000a274 +#define PHY_BB_TPC_7_OFFSET 0x0000a274 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB 5 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB 0 +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK 0x0000003f +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MSB 11 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_LSB 6 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MASK 0x00000fc0 +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB 12 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB 12 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK 0x00001000 +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB 13 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB 13 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK 0x00002000 +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB 14 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB 14 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK 0x00004000 +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB 15 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB 15 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK 0x00008000 +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x) (((x) << 15) & 0x00008000) + +/* macros for BB_tpc_8 */ +#define PHY_BB_TPC_8_ADDRESS 0x0000a278 +#define PHY_BB_TPC_8_OFFSET 0x0000a278 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_MSB 4 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_LSB 0 +#define PHY_BB_TPC_8_DESIRED_SCALE_0_MASK 0x0000001f +#define PHY_BB_TPC_8_DESIRED_SCALE_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_8_DESIRED_SCALE_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_8_DESIRED_SCALE_1_MSB 9 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_LSB 5 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_MASK 0x000003e0 +#define PHY_BB_TPC_8_DESIRED_SCALE_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_8_DESIRED_SCALE_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_8_DESIRED_SCALE_2_MSB 14 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_LSB 10 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_MASK 0x00007c00 +#define PHY_BB_TPC_8_DESIRED_SCALE_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_8_DESIRED_SCALE_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_8_DESIRED_SCALE_3_MSB 19 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_LSB 15 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_MASK 0x000f8000 +#define PHY_BB_TPC_8_DESIRED_SCALE_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_8_DESIRED_SCALE_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_8_DESIRED_SCALE_4_MSB 24 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_LSB 20 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_MASK 0x01f00000 +#define PHY_BB_TPC_8_DESIRED_SCALE_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_8_DESIRED_SCALE_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_8_DESIRED_SCALE_5_MSB 29 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_LSB 25 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_MASK 0x3e000000 +#define PHY_BB_TPC_8_DESIRED_SCALE_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_8_DESIRED_SCALE_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_9 */ +#define PHY_BB_TPC_9_ADDRESS 0x0000a27c +#define PHY_BB_TPC_9_OFFSET 0x0000a27c +#define PHY_BB_TPC_9_DESIRED_SCALE_6_MSB 4 +#define PHY_BB_TPC_9_DESIRED_SCALE_6_LSB 0 +#define PHY_BB_TPC_9_DESIRED_SCALE_6_MASK 0x0000001f +#define PHY_BB_TPC_9_DESIRED_SCALE_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_9_DESIRED_SCALE_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_9_DESIRED_SCALE_7_MSB 9 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_LSB 5 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_MASK 0x000003e0 +#define PHY_BB_TPC_9_DESIRED_SCALE_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_9_DESIRED_SCALE_7_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MSB 14 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_LSB 10 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MASK 0x00007c00 +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MSB 20 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_LSB 20 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MASK 0x00100000 +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MSB 26 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_LSB 21 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MASK 0x07e00000 +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_SET(x) (((x) << 21) & 0x07e00000) +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB 30 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB 27 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK 0x78000000 +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x) (((x) << 27) & 0x78000000) +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MSB 31 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_LSB 31 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MASK 0x80000000 +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_pdadc_tab_b0 */ +#define PHY_BB_PDADC_TAB_B0_ADDRESS 0x0000a280 +#define PHY_BB_PDADC_TAB_B0_OFFSET 0x0000a280 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MSB 31 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_LSB 0 +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MASK 0xffffffff +#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_tab_b0 */ +#define PHY_BB_CL_TAB_B0_ADDRESS 0x0000a300 +#define PHY_BB_CL_TAB_B0_OFFSET 0x0000a300 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB 4 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB 0 +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK 0x0000001f +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB 15 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB 5 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK 0x0000ffe0 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x) (((x) & 0x0000ffe0) >> 5) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x) (((x) << 5) & 0x0000ffe0) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB 26 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB 16 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK 0x07ff0000 +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x) (((x) & 0x07ff0000) >> 16) +#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x) (((x) << 16) & 0x07ff0000) +#define PHY_BB_CL_TAB_B0_BB_GAIN_MSB 30 +#define PHY_BB_CL_TAB_B0_BB_GAIN_LSB 27 +#define PHY_BB_CL_TAB_B0_BB_GAIN_MASK 0x78000000 +#define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x) (((x) & 0x78000000) >> 27) +#define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x) (((x) << 27) & 0x78000000) + +/* macros for BB_cl_map_0_b0 */ +#define PHY_BB_CL_MAP_0_B0_ADDRESS 0x0000a340 +#define PHY_BB_CL_MAP_0_B0_OFFSET 0x0000a340 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB 31 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB 0 +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK 0xffffffff +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_1_b0 */ +#define PHY_BB_CL_MAP_1_B0_ADDRESS 0x0000a344 +#define PHY_BB_CL_MAP_1_B0_OFFSET 0x0000a344 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB 31 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB 0 +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK 0xffffffff +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_2_b0 */ +#define PHY_BB_CL_MAP_2_B0_ADDRESS 0x0000a348 +#define PHY_BB_CL_MAP_2_B0_OFFSET 0x0000a348 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB 31 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB 0 +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK 0xffffffff +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_3_b0 */ +#define PHY_BB_CL_MAP_3_B0_ADDRESS 0x0000a34c +#define PHY_BB_CL_MAP_3_B0_OFFSET 0x0000a34c +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB 31 +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB 0 +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK 0xffffffff +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_cal_ctrl */ +#define PHY_BB_CL_CAL_CTRL_ADDRESS 0x0000a358 +#define PHY_BB_CL_CAL_CTRL_OFFSET 0x0000a358 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB 0 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB 0 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK 0x00000001 +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB 1 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB 1 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK 0x00000002 +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB 3 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB 2 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK 0x0000000c +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB 7 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB 4 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK 0x000000f0 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x) (((x) & 0x000000f0) >> 4) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x) (((x) << 4) & 0x000000f0) +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB 15 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB 8 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK 0x0000ff00 +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB 21 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB 16 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK 0x003f0000 +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB 29 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB 22 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK 0x3fc00000 +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x) (((x) & 0x3fc00000) >> 22) +#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x) (((x) << 22) & 0x3fc00000) +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB 30 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB 30 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK 0x40000000 +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x) (((x) << 30) & 0x40000000) +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB 31 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB 31 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK 0x80000000 +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_cl_map_pal_0_b0 */ +#define PHY_BB_CL_MAP_PAL_0_B0_ADDRESS 0x0000a35c +#define PHY_BB_CL_MAP_PAL_0_B0_OFFSET 0x0000a35c +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MSB 31 +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_LSB 0 +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_1_b0 */ +#define PHY_BB_CL_MAP_PAL_1_B0_ADDRESS 0x0000a360 +#define PHY_BB_CL_MAP_PAL_1_B0_OFFSET 0x0000a360 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MSB 31 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_LSB 0 +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_2_b0 */ +#define PHY_BB_CL_MAP_PAL_2_B0_ADDRESS 0x0000a364 +#define PHY_BB_CL_MAP_PAL_2_B0_OFFSET 0x0000a364 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MSB 31 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_LSB 0 +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_cl_map_pal_3_b0 */ +#define PHY_BB_CL_MAP_PAL_3_B0_ADDRESS 0x0000a368 +#define PHY_BB_CL_MAP_PAL_3_B0_OFFSET 0x0000a368 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MSB 31 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_LSB 0 +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MASK 0xffffffff +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_rifs */ +#define PHY_BB_RIFS_ADDRESS 0x0000a388 +#define PHY_BB_RIFS_OFFSET 0x0000a388 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_MSB 25 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_LSB 25 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_MASK 0x02000000 +#define PHY_BB_RIFS_DISABLE_FCC_FIX_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_RIFS_DISABLE_FCC_FIX_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB 26 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB 26 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK 0x04000000 +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MSB 27 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_LSB 27 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MASK 0x08000000 +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_RIFS_DISABLE_FCC_FIX2_SET(x) (((x) << 27) & 0x08000000) +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MSB 28 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_LSB 28 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MASK 0x10000000 +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_SET(x) (((x) << 28) & 0x10000000) +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MSB 29 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_LSB 29 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MASK 0x20000000 +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_GET(x) (((x) & 0x20000000) >> 29) +#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_SET(x) (((x) << 29) & 0x20000000) +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MSB 30 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_LSB 30 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MASK 0x40000000 +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_GET(x) (((x) & 0x40000000) >> 30) +#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_SET(x) (((x) << 30) & 0x40000000) + +/* macros for BB_powertx_rate5 */ +#define PHY_BB_POWERTX_RATE5_ADDRESS 0x0000a38c +#define PHY_BB_POWERTX_RATE5_OFFSET 0x0000a38c +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MSB 5 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_LSB 0 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MSB 13 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_LSB 8 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MSB 21 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_LSB 16 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MSB 29 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_LSB 24 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate6 */ +#define PHY_BB_POWERTX_RATE6_ADDRESS 0x0000a390 +#define PHY_BB_POWERTX_RATE6_OFFSET 0x0000a390 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MSB 5 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_LSB 0 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MSB 13 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_LSB 8 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MSB 21 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_LSB 16 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MSB 29 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_LSB 24 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_tpc_10 */ +#define PHY_BB_TPC_10_ADDRESS 0x0000a394 +#define PHY_BB_TPC_10_OFFSET 0x0000a394 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MSB 4 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_LSB 0 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MASK 0x0000001f +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MSB 9 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_LSB 5 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MASK 0x000003e0 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MSB 14 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_LSB 10 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MASK 0x00007c00 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MSB 19 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_LSB 15 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MASK 0x000f8000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MSB 24 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_LSB 20 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MASK 0x01f00000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MSB 29 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_LSB 25 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MASK 0x3e000000 +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_11_b0 */ +#define PHY_BB_TPC_11_B0_ADDRESS 0x0000a398 +#define PHY_BB_TPC_11_B0_OFFSET 0x0000a398 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MSB 4 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_LSB 0 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MASK 0x0000001f +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MSB 9 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_LSB 5 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MASK 0x000003e0 +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB 23 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB 16 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK 0x00ff0000 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MSB 31 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_LSB 24 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MASK 0xff000000 +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_GET(x) (((x) & 0xff000000) >> 24) +#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_SET(x) (((x) << 24) & 0xff000000) + +/* macros for BB_cal_chain_mask */ +#define PHY_BB_CAL_CHAIN_MASK_ADDRESS 0x0000a39c +#define PHY_BB_CAL_CHAIN_MASK_OFFSET 0x0000a39c +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB 2 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB 0 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK 0x00000007 +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007) + +/* macros for BB_powertx_sub */ +#define PHY_BB_POWERTX_SUB_ADDRESS 0x0000a3bc +#define PHY_BB_POWERTX_SUB_OFFSET 0x0000a3bc +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB 5 +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB 0 +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK 0x0000003f +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x) (((x) << 0) & 0x0000003f) + +/* macros for BB_powertx_rate7 */ +#define PHY_BB_POWERTX_RATE7_ADDRESS 0x0000a3c0 +#define PHY_BB_POWERTX_RATE7_OFFSET 0x0000a3c0 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MSB 5 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_LSB 0 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MSB 13 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_LSB 8 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MSB 21 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_LSB 16 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MSB 29 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_LSB 24 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate8 */ +#define PHY_BB_POWERTX_RATE8_ADDRESS 0x0000a3c4 +#define PHY_BB_POWERTX_RATE8_OFFSET 0x0000a3c4 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MSB 5 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_LSB 0 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MSB 13 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_LSB 8 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MSB 21 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_LSB 16 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MSB 29 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_LSB 24 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate9 */ +#define PHY_BB_POWERTX_RATE9_ADDRESS 0x0000a3c8 +#define PHY_BB_POWERTX_RATE9_OFFSET 0x0000a3c8 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MSB 5 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_LSB 0 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MSB 13 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_LSB 8 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MSB 21 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_LSB 16 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MSB 29 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_LSB 24 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate10 */ +#define PHY_BB_POWERTX_RATE10_ADDRESS 0x0000a3cc +#define PHY_BB_POWERTX_RATE10_OFFSET 0x0000a3cc +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MSB 5 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_LSB 0 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MSB 13 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_LSB 8 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MSB 21 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_LSB 16 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MSB 29 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_LSB 24 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate11 */ +#define PHY_BB_POWERTX_RATE11_ADDRESS 0x0000a3d0 +#define PHY_BB_POWERTX_RATE11_OFFSET 0x0000a3d0 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MSB 5 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_LSB 0 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MSB 13 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_LSB 8 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MSB 21 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_LSB 16 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MSB 29 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_LSB 24 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_powertx_rate12 */ +#define PHY_BB_POWERTX_RATE12_ADDRESS 0x0000a3d4 +#define PHY_BB_POWERTX_RATE12_OFFSET 0x0000a3d4 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MSB 5 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_LSB 0 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MASK 0x0000003f +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MSB 13 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_LSB 8 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MASK 0x00003f00 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MSB 21 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_LSB 16 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MASK 0x003f0000 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MSB 29 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_LSB 24 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MASK 0x3f000000 +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_force_analog */ +#define PHY_BB_FORCE_ANALOG_ADDRESS 0x0000a3d8 +#define PHY_BB_FORCE_ANALOG_OFFSET 0x0000a3d8 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB 0 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB 0 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK 0x00000001 +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB 3 +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB 1 +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK 0x0000000e +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MSB 4 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_LSB 4 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MASK 0x00000010 +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MSB 7 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_LSB 5 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MASK 0x000000e0 +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_GET(x) (((x) & 0x000000e0) >> 5) +#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_SET(x) (((x) << 5) & 0x000000e0) + +/* macros for BB_tpc_12 */ +#define PHY_BB_TPC_12_ADDRESS 0x0000a3dc +#define PHY_BB_TPC_12_OFFSET 0x0000a3dc +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MSB 4 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_LSB 0 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MASK 0x0000001f +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MSB 9 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_LSB 5 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MASK 0x000003e0 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MSB 14 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_LSB 10 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MASK 0x00007c00 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MSB 19 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_LSB 15 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MASK 0x000f8000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MSB 24 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_LSB 20 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MASK 0x01f00000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MSB 29 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_LSB 25 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MASK 0x3e000000 +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_13 */ +#define PHY_BB_TPC_13_ADDRESS 0x0000a3e0 +#define PHY_BB_TPC_13_OFFSET 0x0000a3e0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MSB 4 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_LSB 0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MASK 0x0000001f +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MSB 9 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_LSB 5 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MASK 0x000003e0 +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_SET(x) (((x) << 5) & 0x000003e0) + +/* macros for BB_tpc_14 */ +#define PHY_BB_TPC_14_ADDRESS 0x0000a3e4 +#define PHY_BB_TPC_14_OFFSET 0x0000a3e4 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MSB 4 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_LSB 0 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MASK 0x0000001f +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MSB 9 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_LSB 5 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MASK 0x000003e0 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MSB 14 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_LSB 10 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MASK 0x00007c00 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MSB 19 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_LSB 15 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MASK 0x000f8000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MSB 24 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_LSB 20 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MASK 0x01f00000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MSB 29 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_LSB 25 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MASK 0x3e000000 +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_15 */ +#define PHY_BB_TPC_15_ADDRESS 0x0000a3e8 +#define PHY_BB_TPC_15_OFFSET 0x0000a3e8 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MSB 4 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_LSB 0 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MASK 0x0000001f +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_GET(x) (((x) & 0x0000001f) >> 0) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_SET(x) (((x) << 0) & 0x0000001f) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MSB 9 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_LSB 5 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MASK 0x000003e0 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_GET(x) (((x) & 0x000003e0) >> 5) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_SET(x) (((x) << 5) & 0x000003e0) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MSB 14 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_LSB 10 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MASK 0x00007c00 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_GET(x) (((x) & 0x00007c00) >> 10) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_SET(x) (((x) << 10) & 0x00007c00) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MSB 19 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_LSB 15 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MASK 0x000f8000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_GET(x) (((x) & 0x000f8000) >> 15) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_SET(x) (((x) << 15) & 0x000f8000) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MSB 24 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_LSB 20 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MASK 0x01f00000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MSB 29 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_LSB 25 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MASK 0x3e000000 +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_tpc_16 */ +#define PHY_BB_TPC_16_ADDRESS 0x0000a3ec +#define PHY_BB_TPC_16_OFFSET 0x0000a3ec +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MSB 13 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_LSB 8 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MASK 0x00003f00 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_GET(x) (((x) & 0x00003f00) >> 8) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_SET(x) (((x) << 8) & 0x00003f00) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MSB 21 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_LSB 16 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MASK 0x003f0000 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_GET(x) (((x) & 0x003f0000) >> 16) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_SET(x) (((x) << 16) & 0x003f0000) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MSB 29 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_LSB 24 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MASK 0x3f000000 +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_GET(x) (((x) & 0x3f000000) >> 24) +#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_SET(x) (((x) << 24) & 0x3f000000) + +/* macros for BB_tpc_17 */ +#define PHY_BB_TPC_17_ADDRESS 0x0000a3f0 +#define PHY_BB_TPC_17_OFFSET 0x0000a3f0 +#define PHY_BB_TPC_17_ENABLE_PAL_MSB 0 +#define PHY_BB_TPC_17_ENABLE_PAL_LSB 0 +#define PHY_BB_TPC_17_ENABLE_PAL_MASK 0x00000001 +#define PHY_BB_TPC_17_ENABLE_PAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_17_ENABLE_PAL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MSB 1 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_LSB 1 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MASK 0x00000002 +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TPC_17_ENABLE_PAL_CCK_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MSB 2 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_LSB 2 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MASK 0x00000004 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MSB 3 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_LSB 3 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MASK 0x00000008 +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MSB 9 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_LSB 4 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MASK 0x000003f0 +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_GET(x) (((x) & 0x000003f0) >> 4) +#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_SET(x) (((x) << 4) & 0x000003f0) +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MSB 10 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_LSB 10 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MASK 0x00000400 +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MSB 16 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_LSB 11 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MASK 0x0001f800 +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_GET(x) (((x) & 0x0001f800) >> 11) +#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_SET(x) (((x) << 11) & 0x0001f800) + +/* macros for BB_tpc_18 */ +#define PHY_BB_TPC_18_ADDRESS 0x0000a3f4 +#define PHY_BB_TPC_18_OFFSET 0x0000a3f4 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_MSB 7 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_LSB 0 +#define PHY_BB_TPC_18_THERM_CAL_VALUE_MASK 0x000000ff +#define PHY_BB_TPC_18_THERM_CAL_VALUE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_18_THERM_CAL_VALUE_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MSB 15 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_LSB 8 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MASK 0x0000ff00 +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_18_VOLT_CAL_VALUE_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB 16 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB 16 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK 0x00010000 +#define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x) (((x) << 16) & 0x00010000) + +/* macros for BB_tpc_19 */ +#define PHY_BB_TPC_19_ADDRESS 0x0000a3f8 +#define PHY_BB_TPC_19_OFFSET 0x0000a3f8 +#define PHY_BB_TPC_19_ALPHA_THERM_MSB 7 +#define PHY_BB_TPC_19_ALPHA_THERM_LSB 0 +#define PHY_BB_TPC_19_ALPHA_THERM_MASK 0x000000ff +#define PHY_BB_TPC_19_ALPHA_THERM_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_TPC_19_ALPHA_THERM_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MSB 15 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_LSB 8 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MASK 0x0000ff00 +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_TPC_19_ALPHA_VOLT_MSB 20 +#define PHY_BB_TPC_19_ALPHA_VOLT_LSB 16 +#define PHY_BB_TPC_19_ALPHA_VOLT_MASK 0x001f0000 +#define PHY_BB_TPC_19_ALPHA_VOLT_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_TPC_19_ALPHA_VOLT_SET(x) (((x) << 16) & 0x001f0000) +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MSB 25 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_LSB 21 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MASK 0x03e00000 +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_GET(x) (((x) & 0x03e00000) >> 21) +#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_SET(x) (((x) << 21) & 0x03e00000) + +/* macros for BB_tpc_20 */ +#define PHY_BB_TPC_20_ADDRESS 0x0000a3fc +#define PHY_BB_TPC_20_OFFSET 0x0000a3fc +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MSB 0 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_LSB 0 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MASK 0x00000001 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MSB 1 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_LSB 1 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MASK 0x00000002 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MSB 2 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_LSB 2 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MASK 0x00000004 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_SET(x) (((x) << 2) & 0x00000004) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MSB 3 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_LSB 3 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MASK 0x00000008 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_SET(x) (((x) << 3) & 0x00000008) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MSB 4 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_LSB 4 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MASK 0x00000010 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_GET(x) (((x) & 0x00000010) >> 4) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_SET(x) (((x) << 4) & 0x00000010) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MSB 5 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_LSB 5 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MASK 0x00000020 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_GET(x) (((x) & 0x00000020) >> 5) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_SET(x) (((x) << 5) & 0x00000020) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MSB 6 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_LSB 6 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MASK 0x00000040 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_GET(x) (((x) & 0x00000040) >> 6) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_SET(x) (((x) << 6) & 0x00000040) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MSB 7 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_LSB 7 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MASK 0x00000080 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_GET(x) (((x) & 0x00000080) >> 7) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_SET(x) (((x) << 7) & 0x00000080) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MSB 8 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_LSB 8 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MASK 0x00000100 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MSB 9 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_LSB 9 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MASK 0x00000200 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MSB 10 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_LSB 10 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MASK 0x00000400 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MSB 11 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_LSB 11 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MASK 0x00000800 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MSB 12 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_LSB 12 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MASK 0x00001000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_GET(x) (((x) & 0x00001000) >> 12) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_SET(x) (((x) << 12) & 0x00001000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MSB 13 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_LSB 13 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MASK 0x00002000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_GET(x) (((x) & 0x00002000) >> 13) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_SET(x) (((x) << 13) & 0x00002000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MSB 14 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_LSB 14 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MASK 0x00004000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_GET(x) (((x) & 0x00004000) >> 14) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_SET(x) (((x) << 14) & 0x00004000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MSB 15 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_LSB 15 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MASK 0x00008000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MSB 16 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_LSB 16 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MASK 0x00010000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_GET(x) (((x) & 0x00010000) >> 16) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_SET(x) (((x) << 16) & 0x00010000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MSB 17 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_LSB 17 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MASK 0x00020000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_GET(x) (((x) & 0x00020000) >> 17) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_SET(x) (((x) << 17) & 0x00020000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MSB 18 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_LSB 18 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MASK 0x00040000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_GET(x) (((x) & 0x00040000) >> 18) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_SET(x) (((x) << 18) & 0x00040000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MSB 19 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_LSB 19 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MASK 0x00080000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_GET(x) (((x) & 0x00080000) >> 19) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_SET(x) (((x) << 19) & 0x00080000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MSB 20 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_LSB 20 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MASK 0x00100000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_GET(x) (((x) & 0x00100000) >> 20) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_SET(x) (((x) << 20) & 0x00100000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MSB 21 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_LSB 21 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MASK 0x00200000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_GET(x) (((x) & 0x00200000) >> 21) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_SET(x) (((x) << 21) & 0x00200000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MSB 22 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_LSB 22 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MASK 0x00400000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_GET(x) (((x) & 0x00400000) >> 22) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_SET(x) (((x) << 22) & 0x00400000) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MSB 23 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_LSB 23 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MASK 0x00800000 +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_GET(x) (((x) & 0x00800000) >> 23) +#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_SET(x) (((x) << 23) & 0x00800000) + +/* macros for BB_tx_gain_tab_1 */ +#define PHY_BB_TX_GAIN_TAB_1_ADDRESS 0x0000a400 +#define PHY_BB_TX_GAIN_TAB_1_OFFSET 0x0000a400 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MSB 31 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_LSB 0 +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_2 */ +#define PHY_BB_TX_GAIN_TAB_2_ADDRESS 0x0000a404 +#define PHY_BB_TX_GAIN_TAB_2_OFFSET 0x0000a404 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MSB 31 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_LSB 0 +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_3 */ +#define PHY_BB_TX_GAIN_TAB_3_ADDRESS 0x0000a408 +#define PHY_BB_TX_GAIN_TAB_3_OFFSET 0x0000a408 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MSB 31 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_LSB 0 +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_4 */ +#define PHY_BB_TX_GAIN_TAB_4_ADDRESS 0x0000a40c +#define PHY_BB_TX_GAIN_TAB_4_OFFSET 0x0000a40c +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MSB 31 +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_LSB 0 +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_5 */ +#define PHY_BB_TX_GAIN_TAB_5_ADDRESS 0x0000a410 +#define PHY_BB_TX_GAIN_TAB_5_OFFSET 0x0000a410 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MSB 31 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_LSB 0 +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_6 */ +#define PHY_BB_TX_GAIN_TAB_6_ADDRESS 0x0000a414 +#define PHY_BB_TX_GAIN_TAB_6_OFFSET 0x0000a414 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MSB 31 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_LSB 0 +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_7 */ +#define PHY_BB_TX_GAIN_TAB_7_ADDRESS 0x0000a418 +#define PHY_BB_TX_GAIN_TAB_7_OFFSET 0x0000a418 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MSB 31 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_LSB 0 +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_8 */ +#define PHY_BB_TX_GAIN_TAB_8_ADDRESS 0x0000a41c +#define PHY_BB_TX_GAIN_TAB_8_OFFSET 0x0000a41c +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MSB 31 +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_LSB 0 +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_9 */ +#define PHY_BB_TX_GAIN_TAB_9_ADDRESS 0x0000a420 +#define PHY_BB_TX_GAIN_TAB_9_OFFSET 0x0000a420 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MSB 31 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_LSB 0 +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_10 */ +#define PHY_BB_TX_GAIN_TAB_10_ADDRESS 0x0000a424 +#define PHY_BB_TX_GAIN_TAB_10_OFFSET 0x0000a424 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MSB 31 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_LSB 0 +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_11 */ +#define PHY_BB_TX_GAIN_TAB_11_ADDRESS 0x0000a428 +#define PHY_BB_TX_GAIN_TAB_11_OFFSET 0x0000a428 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MSB 31 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_LSB 0 +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_12 */ +#define PHY_BB_TX_GAIN_TAB_12_ADDRESS 0x0000a42c +#define PHY_BB_TX_GAIN_TAB_12_OFFSET 0x0000a42c +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MSB 31 +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_LSB 0 +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_13 */ +#define PHY_BB_TX_GAIN_TAB_13_ADDRESS 0x0000a430 +#define PHY_BB_TX_GAIN_TAB_13_OFFSET 0x0000a430 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MSB 31 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_LSB 0 +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_14 */ +#define PHY_BB_TX_GAIN_TAB_14_ADDRESS 0x0000a434 +#define PHY_BB_TX_GAIN_TAB_14_OFFSET 0x0000a434 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MSB 31 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_LSB 0 +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_15 */ +#define PHY_BB_TX_GAIN_TAB_15_ADDRESS 0x0000a438 +#define PHY_BB_TX_GAIN_TAB_15_OFFSET 0x0000a438 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MSB 31 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_LSB 0 +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_16 */ +#define PHY_BB_TX_GAIN_TAB_16_ADDRESS 0x0000a43c +#define PHY_BB_TX_GAIN_TAB_16_OFFSET 0x0000a43c +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MSB 31 +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_LSB 0 +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_17 */ +#define PHY_BB_TX_GAIN_TAB_17_ADDRESS 0x0000a440 +#define PHY_BB_TX_GAIN_TAB_17_OFFSET 0x0000a440 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MSB 31 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_LSB 0 +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_18 */ +#define PHY_BB_TX_GAIN_TAB_18_ADDRESS 0x0000a444 +#define PHY_BB_TX_GAIN_TAB_18_OFFSET 0x0000a444 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MSB 31 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_LSB 0 +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_19 */ +#define PHY_BB_TX_GAIN_TAB_19_ADDRESS 0x0000a448 +#define PHY_BB_TX_GAIN_TAB_19_OFFSET 0x0000a448 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MSB 31 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_LSB 0 +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_20 */ +#define PHY_BB_TX_GAIN_TAB_20_ADDRESS 0x0000a44c +#define PHY_BB_TX_GAIN_TAB_20_OFFSET 0x0000a44c +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MSB 31 +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_LSB 0 +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_21 */ +#define PHY_BB_TX_GAIN_TAB_21_ADDRESS 0x0000a450 +#define PHY_BB_TX_GAIN_TAB_21_OFFSET 0x0000a450 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MSB 31 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_LSB 0 +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_22 */ +#define PHY_BB_TX_GAIN_TAB_22_ADDRESS 0x0000a454 +#define PHY_BB_TX_GAIN_TAB_22_OFFSET 0x0000a454 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MSB 31 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_LSB 0 +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_23 */ +#define PHY_BB_TX_GAIN_TAB_23_ADDRESS 0x0000a458 +#define PHY_BB_TX_GAIN_TAB_23_OFFSET 0x0000a458 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MSB 31 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_LSB 0 +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_24 */ +#define PHY_BB_TX_GAIN_TAB_24_ADDRESS 0x0000a45c +#define PHY_BB_TX_GAIN_TAB_24_OFFSET 0x0000a45c +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MSB 31 +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_LSB 0 +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_25 */ +#define PHY_BB_TX_GAIN_TAB_25_ADDRESS 0x0000a460 +#define PHY_BB_TX_GAIN_TAB_25_OFFSET 0x0000a460 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MSB 31 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_LSB 0 +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_26 */ +#define PHY_BB_TX_GAIN_TAB_26_ADDRESS 0x0000a464 +#define PHY_BB_TX_GAIN_TAB_26_OFFSET 0x0000a464 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MSB 31 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_LSB 0 +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_27 */ +#define PHY_BB_TX_GAIN_TAB_27_ADDRESS 0x0000a468 +#define PHY_BB_TX_GAIN_TAB_27_OFFSET 0x0000a468 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MSB 31 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_LSB 0 +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_28 */ +#define PHY_BB_TX_GAIN_TAB_28_ADDRESS 0x0000a46c +#define PHY_BB_TX_GAIN_TAB_28_OFFSET 0x0000a46c +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MSB 31 +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_LSB 0 +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_29 */ +#define PHY_BB_TX_GAIN_TAB_29_ADDRESS 0x0000a470 +#define PHY_BB_TX_GAIN_TAB_29_OFFSET 0x0000a470 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MSB 31 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_LSB 0 +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_30 */ +#define PHY_BB_TX_GAIN_TAB_30_ADDRESS 0x0000a474 +#define PHY_BB_TX_GAIN_TAB_30_OFFSET 0x0000a474 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MSB 31 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_LSB 0 +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_31 */ +#define PHY_BB_TX_GAIN_TAB_31_ADDRESS 0x0000a478 +#define PHY_BB_TX_GAIN_TAB_31_OFFSET 0x0000a478 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MSB 31 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_LSB 0 +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_32 */ +#define PHY_BB_TX_GAIN_TAB_32_ADDRESS 0x0000a47c +#define PHY_BB_TX_GAIN_TAB_32_OFFSET 0x0000a47c +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MSB 31 +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_LSB 0 +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_1 */ +#define PHY_BB_TX_GAIN_TAB_PAL_1_ADDRESS 0x0000a480 +#define PHY_BB_TX_GAIN_TAB_PAL_1_OFFSET 0x0000a480 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_2 */ +#define PHY_BB_TX_GAIN_TAB_PAL_2_ADDRESS 0x0000a484 +#define PHY_BB_TX_GAIN_TAB_PAL_2_OFFSET 0x0000a484 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_3 */ +#define PHY_BB_TX_GAIN_TAB_PAL_3_ADDRESS 0x0000a488 +#define PHY_BB_TX_GAIN_TAB_PAL_3_OFFSET 0x0000a488 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_4 */ +#define PHY_BB_TX_GAIN_TAB_PAL_4_ADDRESS 0x0000a48c +#define PHY_BB_TX_GAIN_TAB_PAL_4_OFFSET 0x0000a48c +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_5 */ +#define PHY_BB_TX_GAIN_TAB_PAL_5_ADDRESS 0x0000a490 +#define PHY_BB_TX_GAIN_TAB_PAL_5_OFFSET 0x0000a490 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_6 */ +#define PHY_BB_TX_GAIN_TAB_PAL_6_ADDRESS 0x0000a494 +#define PHY_BB_TX_GAIN_TAB_PAL_6_OFFSET 0x0000a494 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_7 */ +#define PHY_BB_TX_GAIN_TAB_PAL_7_ADDRESS 0x0000a498 +#define PHY_BB_TX_GAIN_TAB_PAL_7_OFFSET 0x0000a498 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_8 */ +#define PHY_BB_TX_GAIN_TAB_PAL_8_ADDRESS 0x0000a49c +#define PHY_BB_TX_GAIN_TAB_PAL_8_OFFSET 0x0000a49c +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_9 */ +#define PHY_BB_TX_GAIN_TAB_PAL_9_ADDRESS 0x0000a4a0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_OFFSET 0x0000a4a0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_10 */ +#define PHY_BB_TX_GAIN_TAB_PAL_10_ADDRESS 0x0000a4a4 +#define PHY_BB_TX_GAIN_TAB_PAL_10_OFFSET 0x0000a4a4 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_11 */ +#define PHY_BB_TX_GAIN_TAB_PAL_11_ADDRESS 0x0000a4a8 +#define PHY_BB_TX_GAIN_TAB_PAL_11_OFFSET 0x0000a4a8 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_12 */ +#define PHY_BB_TX_GAIN_TAB_PAL_12_ADDRESS 0x0000a4ac +#define PHY_BB_TX_GAIN_TAB_PAL_12_OFFSET 0x0000a4ac +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_13 */ +#define PHY_BB_TX_GAIN_TAB_PAL_13_ADDRESS 0x0000a4b0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_OFFSET 0x0000a4b0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_14 */ +#define PHY_BB_TX_GAIN_TAB_PAL_14_ADDRESS 0x0000a4b4 +#define PHY_BB_TX_GAIN_TAB_PAL_14_OFFSET 0x0000a4b4 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_15 */ +#define PHY_BB_TX_GAIN_TAB_PAL_15_ADDRESS 0x0000a4b8 +#define PHY_BB_TX_GAIN_TAB_PAL_15_OFFSET 0x0000a4b8 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_16 */ +#define PHY_BB_TX_GAIN_TAB_PAL_16_ADDRESS 0x0000a4bc +#define PHY_BB_TX_GAIN_TAB_PAL_16_OFFSET 0x0000a4bc +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_17 */ +#define PHY_BB_TX_GAIN_TAB_PAL_17_ADDRESS 0x0000a4c0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_OFFSET 0x0000a4c0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_18 */ +#define PHY_BB_TX_GAIN_TAB_PAL_18_ADDRESS 0x0000a4c4 +#define PHY_BB_TX_GAIN_TAB_PAL_18_OFFSET 0x0000a4c4 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_19 */ +#define PHY_BB_TX_GAIN_TAB_PAL_19_ADDRESS 0x0000a4c8 +#define PHY_BB_TX_GAIN_TAB_PAL_19_OFFSET 0x0000a4c8 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_20 */ +#define PHY_BB_TX_GAIN_TAB_PAL_20_ADDRESS 0x0000a4cc +#define PHY_BB_TX_GAIN_TAB_PAL_20_OFFSET 0x0000a4cc +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_21 */ +#define PHY_BB_TX_GAIN_TAB_PAL_21_ADDRESS 0x0000a4d0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_OFFSET 0x0000a4d0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_22 */ +#define PHY_BB_TX_GAIN_TAB_PAL_22_ADDRESS 0x0000a4d4 +#define PHY_BB_TX_GAIN_TAB_PAL_22_OFFSET 0x0000a4d4 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_23 */ +#define PHY_BB_TX_GAIN_TAB_PAL_23_ADDRESS 0x0000a4d8 +#define PHY_BB_TX_GAIN_TAB_PAL_23_OFFSET 0x0000a4d8 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_24 */ +#define PHY_BB_TX_GAIN_TAB_PAL_24_ADDRESS 0x0000a4dc +#define PHY_BB_TX_GAIN_TAB_PAL_24_OFFSET 0x0000a4dc +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_25 */ +#define PHY_BB_TX_GAIN_TAB_PAL_25_ADDRESS 0x0000a4e0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_OFFSET 0x0000a4e0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_26 */ +#define PHY_BB_TX_GAIN_TAB_PAL_26_ADDRESS 0x0000a4e4 +#define PHY_BB_TX_GAIN_TAB_PAL_26_OFFSET 0x0000a4e4 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_27 */ +#define PHY_BB_TX_GAIN_TAB_PAL_27_ADDRESS 0x0000a4e8 +#define PHY_BB_TX_GAIN_TAB_PAL_27_OFFSET 0x0000a4e8 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_28 */ +#define PHY_BB_TX_GAIN_TAB_PAL_28_ADDRESS 0x0000a4ec +#define PHY_BB_TX_GAIN_TAB_PAL_28_OFFSET 0x0000a4ec +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_29 */ +#define PHY_BB_TX_GAIN_TAB_PAL_29_ADDRESS 0x0000a4f0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_OFFSET 0x0000a4f0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_30 */ +#define PHY_BB_TX_GAIN_TAB_PAL_30_ADDRESS 0x0000a4f4 +#define PHY_BB_TX_GAIN_TAB_PAL_30_OFFSET 0x0000a4f4 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_31 */ +#define PHY_BB_TX_GAIN_TAB_PAL_31_ADDRESS 0x0000a4f8 +#define PHY_BB_TX_GAIN_TAB_PAL_31_OFFSET 0x0000a4f8 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_tx_gain_tab_pal_32 */ +#define PHY_BB_TX_GAIN_TAB_PAL_32_ADDRESS 0x0000a4fc +#define PHY_BB_TX_GAIN_TAB_PAL_32_OFFSET 0x0000a4fc +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MSB 31 +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_LSB 0 +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MASK 0xffffffff +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_caltx_gain_set_0 */ +#define PHY_BB_CALTX_GAIN_SET_0_ADDRESS 0x0000a518 +#define PHY_BB_CALTX_GAIN_SET_0_OFFSET 0x0000a518 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_2 */ +#define PHY_BB_CALTX_GAIN_SET_2_ADDRESS 0x0000a51c +#define PHY_BB_CALTX_GAIN_SET_2_OFFSET 0x0000a51c +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_4 */ +#define PHY_BB_CALTX_GAIN_SET_4_ADDRESS 0x0000a520 +#define PHY_BB_CALTX_GAIN_SET_4_OFFSET 0x0000a520 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_6 */ +#define PHY_BB_CALTX_GAIN_SET_6_ADDRESS 0x0000a524 +#define PHY_BB_CALTX_GAIN_SET_6_OFFSET 0x0000a524 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_8 */ +#define PHY_BB_CALTX_GAIN_SET_8_ADDRESS 0x0000a528 +#define PHY_BB_CALTX_GAIN_SET_8_OFFSET 0x0000a528 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_10 */ +#define PHY_BB_CALTX_GAIN_SET_10_ADDRESS 0x0000a52c +#define PHY_BB_CALTX_GAIN_SET_10_OFFSET 0x0000a52c +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_12 */ +#define PHY_BB_CALTX_GAIN_SET_12_ADDRESS 0x0000a530 +#define PHY_BB_CALTX_GAIN_SET_12_OFFSET 0x0000a530 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_14 */ +#define PHY_BB_CALTX_GAIN_SET_14_ADDRESS 0x0000a534 +#define PHY_BB_CALTX_GAIN_SET_14_OFFSET 0x0000a534 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_16 */ +#define PHY_BB_CALTX_GAIN_SET_16_ADDRESS 0x0000a538 +#define PHY_BB_CALTX_GAIN_SET_16_OFFSET 0x0000a538 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_18 */ +#define PHY_BB_CALTX_GAIN_SET_18_ADDRESS 0x0000a53c +#define PHY_BB_CALTX_GAIN_SET_18_OFFSET 0x0000a53c +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_20 */ +#define PHY_BB_CALTX_GAIN_SET_20_ADDRESS 0x0000a540 +#define PHY_BB_CALTX_GAIN_SET_20_OFFSET 0x0000a540 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_22 */ +#define PHY_BB_CALTX_GAIN_SET_22_ADDRESS 0x0000a544 +#define PHY_BB_CALTX_GAIN_SET_22_OFFSET 0x0000a544 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_24 */ +#define PHY_BB_CALTX_GAIN_SET_24_ADDRESS 0x0000a548 +#define PHY_BB_CALTX_GAIN_SET_24_OFFSET 0x0000a548 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_26 */ +#define PHY_BB_CALTX_GAIN_SET_26_ADDRESS 0x0000a54c +#define PHY_BB_CALTX_GAIN_SET_26_OFFSET 0x0000a54c +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_28 */ +#define PHY_BB_CALTX_GAIN_SET_28_ADDRESS 0x0000a550 +#define PHY_BB_CALTX_GAIN_SET_28_OFFSET 0x0000a550 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_caltx_gain_set_30 */ +#define PHY_BB_CALTX_GAIN_SET_30_ADDRESS 0x0000a554 +#define PHY_BB_CALTX_GAIN_SET_30_OFFSET 0x0000a554 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MSB 13 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_LSB 0 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MASK 0x00003fff +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MSB 27 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_LSB 14 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MASK 0x0fffc000 +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiqcal_meas_b0 */ +#define PHY_BB_TXIQCAL_MEAS_B0_ADDRESS 0x0000a558 +#define PHY_BB_TXIQCAL_MEAS_B0_OFFSET 0x0000a558 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MSB 11 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_LSB 0 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MASK 0x00000fff +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MSB 23 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_LSB 12 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MASK 0x00fff000 +#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_GET(x) (((x) & 0x00fff000) >> 12) + +/* macros for BB_txiqcal_start */ +#define PHY_BB_TXIQCAL_START_ADDRESS 0x0000a6d8 +#define PHY_BB_TXIQCAL_START_OFFSET 0x0000a6d8 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MSB 0 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_LSB 0 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MASK 0x00000001 +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_SET(x) (((x) << 0) & 0x00000001) + +/* macros for BB_txiqcal_control_0 */ +#define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS 0x0000a6dc +#define PHY_BB_TXIQCAL_CONTROL_0_OFFSET 0x0000a6dc +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MSB 0 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MASK 0x00000001 +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB 6 +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB 1 +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK 0x0000007e +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x) (((x) & 0x0000007e) >> 1) +#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x) (((x) << 1) & 0x0000007e) +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB 12 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB 7 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK 0x00001f80 +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x) (((x) & 0x00001f80) >> 7) +#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x) (((x) << 7) & 0x00001f80) +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB 18 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB 13 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK 0x0007e000 +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x) (((x) & 0x0007e000) >> 13) +#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x) (((x) << 13) & 0x0007e000) +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB 22 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB 19 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK 0x00780000 +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x) (((x) & 0x00780000) >> 19) +#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x) (((x) << 19) & 0x00780000) +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB 29 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB 23 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK 0x3f800000 +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x) (((x) & 0x3f800000) >> 23) +#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x) (((x) << 23) & 0x3f800000) + +/* macros for BB_txiqcal_control_1 */ +#define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS 0x0000a6e0 +#define PHY_BB_TXIQCAL_CONTROL_1_OFFSET 0x0000a6e0 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB 5 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK 0x0000003f +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB 11 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB 6 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB 17 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB 12 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK 0x0003f000 +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB 24 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB 18 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK 0x01fc0000 +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x) (((x) & 0x01fc0000) >> 18) +#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x) (((x) << 18) & 0x01fc0000) + +/* macros for BB_txiqcal_control_2 */ +#define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS 0x0000a6e4 +#define PHY_BB_TXIQCAL_CONTROL_2_OFFSET 0x0000a6e4 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MSB 3 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MASK 0x0000000f +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_GET(x) (((x) & 0x0000000f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_SET(x) (((x) << 0) & 0x0000000f) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB 8 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB 4 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK 0x000001f0 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x) (((x) & 0x000001f0) >> 4) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x) (((x) << 4) & 0x000001f0) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB 13 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB 9 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK 0x00003e00 +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x) (((x) & 0x00003e00) >> 9) +#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x) (((x) << 9) & 0x00003e00) + +/* macros for BB_txiqcal_control_3 */ +#define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS 0x0000a6e8 +#define PHY_BB_TXIQCAL_CONTROL_3_OFFSET 0x0000a6e8 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB 5 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB 0 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK 0x0000003f +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB 11 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB 6 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB 21 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB 12 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK 0x003ff000 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB 23 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB 22 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK 0x00c00000 +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MSB 24 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_LSB 24 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MASK 0x01000000 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_SET(x) (((x) << 24) & 0x01000000) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MSB 26 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_LSB 25 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MASK 0x06000000 +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_GET(x) (((x) & 0x06000000) >> 25) +#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_SET(x) (((x) << 25) & 0x06000000) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MSB 28 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_LSB 27 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MASK 0x18000000 +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_GET(x) (((x) & 0x18000000) >> 27) +#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_SET(x) (((x) << 27) & 0x18000000) +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB 30 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB 29 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK 0x60000000 +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x) (((x) & 0x60000000) >> 29) +#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x) (((x) << 29) & 0x60000000) +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB 31 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB 31 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK 0x80000000 +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x) (((x) & 0x80000000) >> 31) +#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x) (((x) << 31) & 0x80000000) + +/* macros for BB_txiq_corr_coeff_01_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_ADDRESS 0x0000a6ec +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_OFFSET 0x0000a6ec +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_23_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_ADDRESS 0x0000a6f0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_OFFSET 0x0000a6f0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_45_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_ADDRESS 0x0000a6f4 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_OFFSET 0x0000a6f4 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_67_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_ADDRESS 0x0000a6f8 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_OFFSET 0x0000a6f8 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_89_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_ADDRESS 0x0000a6fc +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_OFFSET 0x0000a6fc +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_ab_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_ADDRESS 0x0000a700 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_OFFSET 0x0000a700 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_cd_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_ADDRESS 0x0000a704 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_OFFSET 0x0000a704 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_txiq_corr_coeff_ef_b0 */ +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_ADDRESS 0x0000a708 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_OFFSET 0x0000a708 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MSB 13 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_LSB 0 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MASK 0x00003fff +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_GET(x) (((x) & 0x00003fff) >> 0) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_SET(x) (((x) << 0) & 0x00003fff) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MSB 27 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_LSB 14 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MASK 0x0fffc000 +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_GET(x) (((x) & 0x0fffc000) >> 14) +#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_SET(x) (((x) << 14) & 0x0fffc000) + +/* macros for BB_cal_rxbb_gain_tbl_0 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS 0x0000a70c +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_OFFSET 0x0000a70c +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_4 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS 0x0000a710 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_OFFSET 0x0000a710 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_8 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS 0x0000a714 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_OFFSET 0x0000a714 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_12 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS 0x0000a718 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_OFFSET 0x0000a718 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_16 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS 0x0000a71c +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_OFFSET 0x0000a71c +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_20 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS 0x0000a720 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_OFFSET 0x0000a720 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB 11 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB 6 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK 0x00000fc0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB 17 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB 12 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK 0x0003f000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x) (((x) << 12) & 0x0003f000) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB 23 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB 18 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK 0x00fc0000 +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x) (((x) & 0x00fc0000) >> 18) +#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x) (((x) << 18) & 0x00fc0000) + +/* macros for BB_cal_rxbb_gain_tbl_24 */ +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS 0x0000a724 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_OFFSET 0x0000a724 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB 5 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB 0 +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK 0x0000003f +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x) (((x) << 0) & 0x0000003f) + +/* macros for BB_txiqcal_status_b0 */ +#define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS 0x0000a728 +#define PHY_BB_TXIQCAL_STATUS_B0_OFFSET 0x0000a728 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB 0 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB 0 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK 0x00000001 +#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB 5 +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB 1 +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK 0x0000003e +#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x) (((x) & 0x0000003e) >> 1) +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB 11 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB 6 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK 0x00000fc0 +#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB 17 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB 12 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK 0x0003f000 +#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x) (((x) & 0x0003f000) >> 12) +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB 24 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB 18 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK 0x01fc0000 +#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x) (((x) & 0x01fc0000) >> 18) + +/* macros for BB_paprd_trainer_cntl1 */ +#define PHY_BB_PAPRD_TRAINER_CNTL1_ADDRESS 0x0000a72c +#define PHY_BB_PAPRD_TRAINER_CNTL1_OFFSET 0x0000a72c +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK 0x00000001 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB 7 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB 1 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK 0x000000fe +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x) (((x) & 0x000000fe) >> 1) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x) (((x) << 1) & 0x000000fe) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB 8 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB 8 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK 0x00000100 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x) (((x) & 0x00000100) >> 8) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x) (((x) << 8) & 0x00000100) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB 9 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB 9 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK 0x00000200 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x) (((x) & 0x00000200) >> 9) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x) (((x) << 9) & 0x00000200) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB 10 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB 10 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK 0x00000400 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x) (((x) & 0x00000400) >> 10) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x) (((x) << 10) & 0x00000400) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_LSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MASK 0x00000800 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_GET(x) (((x) & 0x00000800) >> 11) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_SET(x) (((x) << 11) & 0x00000800) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MSB 18 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MASK 0x0007f000 +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_GET(x) (((x) & 0x0007f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_SET(x) (((x) << 12) & 0x0007f000) + +/* macros for BB_paprd_trainer_cntl2 */ +#define PHY_BB_PAPRD_TRAINER_CNTL2_ADDRESS 0x0000a730 +#define PHY_BB_PAPRD_TRAINER_CNTL2_OFFSET 0x0000a730 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB 31 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK 0xffffffff +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x) (((x) & 0xffffffff) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_paprd_trainer_cntl3 */ +#define PHY_BB_PAPRD_TRAINER_CNTL3_ADDRESS 0x0000a734 +#define PHY_BB_PAPRD_TRAINER_CNTL3_OFFSET 0x0000a734 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MSB 5 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MASK 0x0000003f +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB 6 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK 0x00000fc0 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB 16 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK 0x0001f000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB 19 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB 17 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK 0x000e0000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x) (((x) & 0x000e0000) >> 17) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x) (((x) << 17) & 0x000e0000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB 23 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB 20 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK 0x00f00000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x) (((x) & 0x00f00000) >> 20) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x) (((x) << 20) & 0x00f00000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB 27 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB 24 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK 0x0f000000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x) (((x) & 0x0f000000) >> 24) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x) (((x) << 24) & 0x0f000000) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB 28 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB 28 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK 0x10000000 +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x) (((x) & 0x10000000) >> 28) +#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x) (((x) << 28) & 0x10000000) + +/* macros for BB_paprd_trainer_cntl4 */ +#define PHY_BB_PAPRD_TRAINER_CNTL4_ADDRESS 0x0000a738 +#define PHY_BB_PAPRD_TRAINER_CNTL4_OFFSET 0x0000a738 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB 11 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB 0 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK 0x00000fff +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB 15 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB 12 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK 0x0000f000 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x) (((x) & 0x0000f000) >> 12) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x) (((x) << 12) & 0x0000f000) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB 25 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB 16 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK 0x03ff0000 +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x) (((x) & 0x03ff0000) >> 16) +#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x) (((x) << 16) & 0x03ff0000) + +/* macros for BB_paprd_trainer_stat1 */ +#define PHY_BB_PAPRD_TRAINER_STAT1_ADDRESS 0x0000a73c +#define PHY_BB_PAPRD_TRAINER_STAT1_OFFSET 0x0000a73c +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK 0x00000001 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB 1 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB 1 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK 0x00000002 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB 2 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB 2 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK 0x00000004 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x) (((x) & 0x00000004) >> 2) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB 3 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB 3 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK 0x00000008 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x) (((x) & 0x00000008) >> 3) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB 8 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB 4 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK 0x000001f0 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x) (((x) & 0x000001f0) >> 4) +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB 16 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB 9 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK 0x0001fe00 +#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x) (((x) & 0x0001fe00) >> 9) + +/* macros for BB_paprd_trainer_stat2 */ +#define PHY_BB_PAPRD_TRAINER_STAT2_ADDRESS 0x0000a740 +#define PHY_BB_PAPRD_TRAINER_STAT2_OFFSET 0x0000a740 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB 15 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK 0x0000ffff +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x) (((x) & 0x0000ffff) >> 0) +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB 20 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB 16 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK 0x001f0000 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x) (((x) & 0x001f0000) >> 16) +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB 22 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB 21 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK 0x00600000 +#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x) (((x) & 0x00600000) >> 21) + +/* macros for BB_paprd_trainer_stat3 */ +#define PHY_BB_PAPRD_TRAINER_STAT3_ADDRESS 0x0000a744 +#define PHY_BB_PAPRD_TRAINER_STAT3_OFFSET 0x0000a744 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB 19 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB 0 +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK 0x000fffff +#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x) (((x) & 0x000fffff) >> 0) + +/* macros for BB_fcal_1 */ +#define PHY_BB_FCAL_1_ADDRESS 0x0000a7d8 +#define PHY_BB_FCAL_1_OFFSET 0x0000a7d8 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB 9 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB 0 +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK 0x000003ff +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x) (((x) & 0x000003ff) >> 0) +#define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x) (((x) << 0) & 0x000003ff) +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB 19 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB 10 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK 0x000ffc00 +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x) (((x) & 0x000ffc00) >> 10) +#define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x) (((x) << 10) & 0x000ffc00) +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB 24 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB 20 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK 0x01f00000 +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x) (((x) & 0x01f00000) >> 20) +#define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x) (((x) << 20) & 0x01f00000) +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB 29 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB 25 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK 0x3e000000 +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x) (((x) & 0x3e000000) >> 25) +#define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x) (((x) << 25) & 0x3e000000) + +/* macros for BB_fcal_2_b0 */ +#define PHY_BB_FCAL_2_B0_ADDRESS 0x0000a7dc +#define PHY_BB_FCAL_2_B0_OFFSET 0x0000a7dc +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB 2 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB 0 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK 0x00000007 +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x) (((x) & 0x00000007) >> 0) +#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x) (((x) << 0) & 0x00000007) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB 7 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB 3 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK 0x000000f8 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x) (((x) & 0x000000f8) >> 3) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x) (((x) << 3) & 0x000000f8) +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB 9 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB 8 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK 0x00000300 +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x) (((x) & 0x00000300) >> 8) +#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x) (((x) << 8) & 0x00000300) +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB 12 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB 10 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK 0x00001c00 +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x) (((x) & 0x00001c00) >> 10) +#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x) (((x) << 10) & 0x00001c00) +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB 14 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB 13 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK 0x00006000 +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x) (((x) & 0x00006000) >> 13) +#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x) (((x) << 13) & 0x00006000) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB 15 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB 15 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK 0x00008000 +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x) (((x) & 0x00008000) >> 15) +#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x) (((x) << 15) & 0x00008000) +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB 18 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB 16 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK 0x00070000 +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x) (((x) & 0x00070000) >> 16) +#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x) (((x) << 16) & 0x00070000) +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB 24 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB 20 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK 0x01f00000 +#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x) (((x) & 0x01f00000) >> 20) + +/* macros for BB_radar_bw_filter */ +#define PHY_BB_RADAR_BW_FILTER_ADDRESS 0x0000a7e0 +#define PHY_BB_RADAR_BW_FILTER_OFFSET 0x0000a7e0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MSB 0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_LSB 0 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MASK 0x00000001 +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MSB 1 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_LSB 1 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MASK 0x00000002 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_GET(x) (((x) & 0x00000002) >> 1) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_SET(x) (((x) << 1) & 0x00000002) +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MSB 3 +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_LSB 2 +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MASK 0x0000000c +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MSB 5 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_LSB 4 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MASK 0x00000030 +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MSB 14 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_LSB 8 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MASK 0x00007f00 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_GET(x) (((x) & 0x00007f00) >> 8) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_SET(x) (((x) << 8) & 0x00007f00) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MSB 20 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_LSB 15 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MASK 0x001f8000 +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_GET(x) (((x) & 0x001f8000) >> 15) +#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_SET(x) (((x) << 15) & 0x001f8000) +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MSB 26 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_LSB 21 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MASK 0x07e00000 +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_GET(x) (((x) & 0x07e00000) >> 21) +#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_SET(x) (((x) << 21) & 0x07e00000) + +/* macros for BB_dft_tone_ctrl_b0 */ +#define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS 0x0000a7e4 +#define PHY_BB_DFT_TONE_CTRL_B0_OFFSET 0x0000a7e4 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB 0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB 0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK 0x00000001 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB 3 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB 2 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK 0x0000000c +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x) (((x) & 0x0000000c) >> 2) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x) (((x) << 2) & 0x0000000c) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB 12 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB 4 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK 0x00001ff0 +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x) (((x) & 0x00001ff0) >> 4) +#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x) (((x) << 4) & 0x00001ff0) + +/* macros for BB_therm_adc_1 */ +#define PHY_BB_THERM_ADC_1_ADDRESS 0x0000a7e8 +#define PHY_BB_THERM_ADC_1_OFFSET 0x0000a7e8 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MSB 7 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_LSB 0 +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MASK 0x000000ff +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MSB 15 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_LSB 8 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MASK 0x0000ff00 +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_SET(x) (((x) << 8) & 0x0000ff00) +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MSB 23 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_LSB 16 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MASK 0x00ff0000 +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_GET(x) (((x) & 0x00ff0000) >> 16) +#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_SET(x) (((x) << 16) & 0x00ff0000) +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MSB 25 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_LSB 24 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MASK 0x03000000 +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_GET(x) (((x) & 0x03000000) >> 24) +#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_SET(x) (((x) << 24) & 0x03000000) +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB 26 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB 26 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK 0x04000000 +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x) (((x) << 26) & 0x04000000) +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB 27 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB 27 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK 0x08000000 +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x) (((x) & 0x08000000) >> 27) +#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x) (((x) << 27) & 0x08000000) + +/* macros for BB_therm_adc_2 */ +#define PHY_BB_THERM_ADC_2_ADDRESS 0x0000a7ec +#define PHY_BB_THERM_ADC_2_OFFSET 0x0000a7ec +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MSB 11 +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_LSB 0 +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MASK 0x00000fff +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_GET(x) (((x) & 0x00000fff) >> 0) +#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_SET(x) (((x) << 0) & 0x00000fff) +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MSB 21 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_LSB 12 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MASK 0x003ff000 +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_GET(x) (((x) & 0x003ff000) >> 12) +#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_SET(x) (((x) << 12) & 0x003ff000) +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MSB 31 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_LSB 22 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MASK 0xffc00000 +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_GET(x) (((x) & 0xffc00000) >> 22) +#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_SET(x) (((x) << 22) & 0xffc00000) + +/* macros for BB_therm_adc_3 */ +#define PHY_BB_THERM_ADC_3_ADDRESS 0x0000a7f0 +#define PHY_BB_THERM_ADC_3_OFFSET 0x0000a7f0 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MSB 7 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_LSB 0 +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MASK 0x000000ff +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_SET(x) (((x) << 0) & 0x000000ff) +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MSB 16 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_LSB 8 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MASK 0x0001ff00 +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_GET(x) (((x) & 0x0001ff00) >> 8) +#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_SET(x) (((x) << 8) & 0x0001ff00) +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MSB 29 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_LSB 17 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MASK 0x3ffe0000 +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_GET(x) (((x) & 0x3ffe0000) >> 17) +#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_SET(x) (((x) << 17) & 0x3ffe0000) + +/* macros for BB_therm_adc_4 */ +#define PHY_BB_THERM_ADC_4_ADDRESS 0x0000a7f4 +#define PHY_BB_THERM_ADC_4_OFFSET 0x0000a7f4 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MSB 7 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_LSB 0 +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MASK 0x000000ff +#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MSB 15 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_LSB 8 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MASK 0x0000ff00 +#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_GET(x) (((x) & 0x0000ff00) >> 8) +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MSB 23 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_LSB 16 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MASK 0x00ff0000 +#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_GET(x) (((x) & 0x00ff0000) >> 16) + +/* macros for BB_tx_forced_gain */ +#define PHY_BB_TX_FORCED_GAIN_ADDRESS 0x0000a7f8 +#define PHY_BB_TX_FORCED_GAIN_OFFSET 0x0000a7f8 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB 0 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB 0 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK 0x00000001 +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x) (((x) & 0x00000001) >> 0) +#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x) (((x) << 0) & 0x00000001) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB 3 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB 1 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK 0x0000000e +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x) (((x) & 0x0000000e) >> 1) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x) (((x) << 1) & 0x0000000e) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB 5 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB 4 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK 0x00000030 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x) (((x) & 0x00000030) >> 4) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x) (((x) << 4) & 0x00000030) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB 9 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB 6 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK 0x000003c0 +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x) (((x) & 0x000003c0) >> 6) +#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x) (((x) << 6) & 0x000003c0) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MSB 13 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_LSB 10 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MASK 0x00003c00 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_GET(x) (((x) & 0x00003c00) >> 10) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_SET(x) (((x) << 10) & 0x00003c00) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MSB 17 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_LSB 14 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MASK 0x0003c000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_GET(x) (((x) & 0x0003c000) >> 14) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_SET(x) (((x) << 14) & 0x0003c000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MSB 21 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_LSB 18 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MASK 0x003c0000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_GET(x) (((x) & 0x003c0000) >> 18) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_SET(x) (((x) << 18) & 0x003c0000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MSB 23 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_LSB 22 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MASK 0x00c00000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_GET(x) (((x) & 0x00c00000) >> 22) +#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_SET(x) (((x) << 22) & 0x00c00000) +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB 24 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB 24 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK 0x01000000 +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x) (((x) & 0x01000000) >> 24) +#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x) (((x) << 24) & 0x01000000) + +/* macros for BB_eco_ctrl */ +#define PHY_BB_ECO_CTRL_ADDRESS 0x0000a7fc +#define PHY_BB_ECO_CTRL_OFFSET 0x0000a7fc +#define PHY_BB_ECO_CTRL_ECO_CTRL_MSB 7 +#define PHY_BB_ECO_CTRL_ECO_CTRL_LSB 0 +#define PHY_BB_ECO_CTRL_ECO_CTRL_MASK 0x000000ff +#define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x) (((x) & 0x000000ff) >> 0) +#define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x) (((x) << 0) & 0x000000ff) + +/* macros for BB_gain_force_max_gains_b1 */ +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_ADDRESS 0x0000a848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_OFFSET 0x0000a848 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MSB 13 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_LSB 7 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MASK 0x00003f80 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_GET(x) (((x) & 0x00003f80) >> 7) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_SET(x) (((x) << 7) & 0x00003f80) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MSB 20 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_LSB 14 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MASK 0x001fc000 +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_GET(x) (((x) & 0x001fc000) >> 14) +#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_SET(x) (((x) << 14) & 0x001fc000) + +/* macros for BB_gains_min_offsets_b1 */ +#define PHY_BB_GAINS_MIN_OFFSETS_B1_ADDRESS 0x0000a84c +#define PHY_BB_GAINS_MIN_OFFSETS_B1_OFFSET 0x0000a84c +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MSB 24 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_LSB 17 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MASK 0x01fe0000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_GET(x) (((x) & 0x01fe0000) >> 17) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_SET(x) (((x) << 17) & 0x01fe0000) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_LSB 25 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MASK 0x02000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_GET(x) (((x) & 0x02000000) >> 25) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_SET(x) (((x) << 25) & 0x02000000) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_LSB 26 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MASK 0x04000000 +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_GET(x) (((x) & 0x04000000) >> 26) +#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_SET(x) (((x) << 26) & 0x04000000) + +/* macros for BB_rx_ocgain2 */ +#define PHY_BB_RX_OCGAIN2_ADDRESS 0x0000aa00 +#define PHY_BB_RX_OCGAIN2_OFFSET 0x0000aa00 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MSB 31 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_LSB 0 +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MASK 0xffffffff +#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_SET(x) (((x) << 0) & 0xffffffff) + +/* macros for BB_ext_atten_switch_ctl_b1 */ +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_ADDRESS 0x0000b20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_OFFSET 0x0000b20c +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MSB 5 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_LSB 0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MASK 0x0000003f +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_GET(x) (((x) & 0x0000003f) >> 0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_SET(x) (((x) << 0) & 0x0000003f) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MSB 11 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_LSB 6 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MASK 0x00000fc0 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_GET(x) (((x) & 0x00000fc0) >> 6) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_SET(x) (((x) << 6) & 0x00000fc0) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MSB 16 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_LSB 12 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MASK 0x0001f000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_GET(x) (((x) & 0x0001f000) >> 12) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_SET(x) (((x) << 12) & 0x0001f000) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MSB 21 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_LSB 17 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MASK 0x003e0000 +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_GET(x) (((x) & 0x003e0000) >> 17) +#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_SET(x) (((x) << 17) & 0x003e0000) + + +#ifndef __ASSEMBLER__ + +typedef struct bb_lc_reg_reg_s { + volatile char pad__0[0x9800]; /* 0x0 - 0x9800 */ + volatile unsigned int BB_test_controls; /* 0x9800 - 0x9804 */ + volatile unsigned int BB_gen_controls; /* 0x9804 - 0x9808 */ + volatile unsigned int BB_test_controls_status; /* 0x9808 - 0x980c */ + volatile unsigned int BB_timing_controls_1; /* 0x980c - 0x9810 */ + volatile unsigned int BB_timing_controls_2; /* 0x9810 - 0x9814 */ + volatile unsigned int BB_timing_controls_3; /* 0x9814 - 0x9818 */ + volatile unsigned int BB_D2_chip_id; /* 0x9818 - 0x981c */ + volatile unsigned int BB_active; /* 0x981c - 0x9820 */ + volatile unsigned int BB_tx_timing_1; /* 0x9820 - 0x9824 */ + volatile unsigned int BB_tx_timing_2; /* 0x9824 - 0x9828 */ + volatile unsigned int BB_tx_timing_3; /* 0x9828 - 0x982c */ + volatile unsigned int BB_addac_parallel_control; /* 0x982c - 0x9830 */ + volatile char pad__1[0x4]; /* 0x9830 - 0x9834 */ + volatile unsigned int BB_xpa_timing_control; /* 0x9834 - 0x9838 */ + volatile unsigned int BB_misc_pa_control; /* 0x9838 - 0x983c */ + volatile unsigned int BB_tstdac_constant; /* 0x983c - 0x9840 */ + volatile unsigned int BB_find_signal_low; /* 0x9840 - 0x9844 */ + volatile unsigned int BB_settling_time; /* 0x9844 - 0x9848 */ + volatile unsigned int BB_gain_force_max_gains_b0; /* 0x9848 - 0x984c */ + volatile unsigned int BB_gains_min_offsets_b0; /* 0x984c - 0x9850 */ + volatile unsigned int BB_desired_sigsize; /* 0x9850 - 0x9854 */ + volatile unsigned int BB_timing_control_3a; /* 0x9854 - 0x9858 */ + volatile unsigned int BB_find_signal; /* 0x9858 - 0x985c */ + volatile unsigned int BB_agc; /* 0x985c - 0x9860 */ + volatile unsigned int BB_agc_control; /* 0x9860 - 0x9864 */ + volatile unsigned int BB_cca_b0; /* 0x9864 - 0x9868 */ + volatile unsigned int BB_sfcorr; /* 0x9868 - 0x986c */ + volatile unsigned int BB_self_corr_low; /* 0x986c - 0x9870 */ + volatile char pad__2[0x4]; /* 0x9870 - 0x9874 */ + volatile unsigned int BB_synth_control; /* 0x9874 - 0x9878 */ + volatile unsigned int BB_addac_clk_select; /* 0x9878 - 0x987c */ + volatile unsigned int BB_pll_cntl; /* 0x987c - 0x9880 */ + volatile char pad__3[0x80]; /* 0x9880 - 0x9900 */ + volatile unsigned int BB_vit_spur_mask_A; /* 0x9900 - 0x9904 */ + volatile unsigned int BB_vit_spur_mask_B; /* 0x9904 - 0x9908 */ + volatile unsigned int BB_pilot_spur_mask; /* 0x9908 - 0x990c */ + volatile unsigned int BB_chan_spur_mask; /* 0x990c - 0x9910 */ + volatile unsigned int BB_spectral_scan; /* 0x9910 - 0x9914 */ + volatile unsigned int BB_analog_power_on_time; /* 0x9914 - 0x9918 */ + volatile unsigned int BB_search_start_delay; /* 0x9918 - 0x991c */ + volatile unsigned int BB_max_rx_length; /* 0x991c - 0x9920 */ + volatile unsigned int BB_timing_control_4; /* 0x9920 - 0x9924 */ + volatile unsigned int BB_timing_control_5; /* 0x9924 - 0x9928 */ + volatile unsigned int BB_phyonly_warm_reset; /* 0x9928 - 0x992c */ + volatile unsigned int BB_phyonly_control; /* 0x992c - 0x9930 */ + volatile char pad__4[0x4]; /* 0x9930 - 0x9934 */ + volatile unsigned int BB_powertx_rate1; /* 0x9934 - 0x9938 */ + volatile unsigned int BB_powertx_rate2; /* 0x9938 - 0x993c */ + volatile unsigned int BB_powertx_max; /* 0x993c - 0x9940 */ + volatile unsigned int BB_extension_radar; /* 0x9940 - 0x9944 */ + volatile unsigned int BB_frame_control; /* 0x9944 - 0x9948 */ + volatile unsigned int BB_timing_control_6; /* 0x9948 - 0x994c */ + volatile unsigned int BB_spur_mask_controls; /* 0x994c - 0x9950 */ + volatile unsigned int BB_rx_iq_corr_b0; /* 0x9950 - 0x9954 */ + volatile unsigned int BB_radar_detection; /* 0x9954 - 0x9958 */ + volatile unsigned int BB_radar_detection_2; /* 0x9958 - 0x995c */ + volatile unsigned int BB_tx_phase_ramp_b0; /* 0x995c - 0x9960 */ + volatile unsigned int BB_switch_table_chn_b0; /* 0x9960 - 0x9964 */ + volatile unsigned int BB_switch_table_com1; /* 0x9964 - 0x9968 */ + volatile unsigned int BB_cca_ctrl_2_b0; /* 0x9968 - 0x996c */ + volatile unsigned int BB_switch_table_com2; /* 0x996c - 0x9970 */ + volatile unsigned int BB_restart; /* 0x9970 - 0x9974 */ + volatile char pad__5[0x4]; /* 0x9974 - 0x9978 */ + volatile unsigned int BB_scrambler_seed; /* 0x9978 - 0x997c */ + volatile unsigned int BB_rfbus_request; /* 0x997c - 0x9980 */ + volatile char pad__6[0x20]; /* 0x9980 - 0x99a0 */ + volatile unsigned int BB_timing_control_11; /* 0x99a0 - 0x99a4 */ + volatile unsigned int BB_multichain_enable; /* 0x99a4 - 0x99a8 */ + volatile unsigned int BB_multichain_control; /* 0x99a8 - 0x99ac */ + volatile unsigned int BB_multichain_gain_ctrl; /* 0x99ac - 0x99b0 */ + volatile char pad__7[0x4]; /* 0x99b0 - 0x99b4 */ + volatile unsigned int BB_adc_gain_dc_corr_b0; /* 0x99b4 - 0x99b8 */ + volatile unsigned int BB_ext_chan_pwr_thr_1; /* 0x99b8 - 0x99bc */ + volatile unsigned int BB_ext_chan_pwr_thr_2_b0; /* 0x99bc - 0x99c0 */ + volatile unsigned int BB_ext_chan_scorr_thr; /* 0x99c0 - 0x99c4 */ + volatile unsigned int BB_ext_chan_detect_win; /* 0x99c4 - 0x99c8 */ + volatile unsigned int BB_pwr_thr_20_40_det; /* 0x99c8 - 0x99cc */ + volatile char pad__8[0x4]; /* 0x99cc - 0x99d0 */ + volatile unsigned int BB_short_gi_delta_slope; /* 0x99d0 - 0x99d4 */ + volatile char pad__9[0x8]; /* 0x99d4 - 0x99dc */ + volatile unsigned int BB_chaninfo_ctrl; /* 0x99dc - 0x99e0 */ + volatile unsigned int BB_heavy_clip_ctrl; /* 0x99e0 - 0x99e4 */ + volatile unsigned int BB_heavy_clip_20; /* 0x99e4 - 0x99e8 */ + volatile unsigned int BB_heavy_clip_40; /* 0x99e8 - 0x99ec */ + volatile unsigned int BB_rifs_srch; /* 0x99ec - 0x99f0 */ + volatile unsigned int BB_iq_adc_cal_mode; /* 0x99f0 - 0x99f4 */ + volatile char pad__10[0x8]; /* 0x99f4 - 0x99fc */ + volatile unsigned int BB_per_chain_csd; /* 0x99fc - 0x9a00 */ + volatile unsigned int BB_rx_ocgain[128]; /* 0x9a00 - 0x9c00 */ + volatile unsigned int BB_tx_crc; /* 0x9c00 - 0x9c04 */ + volatile char pad__11[0xc]; /* 0x9c04 - 0x9c10 */ + volatile unsigned int BB_iq_adc_meas_0_b0; /* 0x9c10 - 0x9c14 */ + volatile unsigned int BB_iq_adc_meas_1_b0; /* 0x9c14 - 0x9c18 */ + volatile unsigned int BB_iq_adc_meas_2_b0; /* 0x9c18 - 0x9c1c */ + volatile unsigned int BB_iq_adc_meas_3_b0; /* 0x9c1c - 0x9c20 */ + volatile unsigned int BB_rfbus_grant; /* 0x9c20 - 0x9c24 */ + volatile unsigned int BB_tstadc; /* 0x9c24 - 0x9c28 */ + volatile unsigned int BB_tstdac; /* 0x9c28 - 0x9c2c */ + volatile char pad__12[0x4]; /* 0x9c2c - 0x9c30 */ + volatile unsigned int BB_illegal_tx_rate; /* 0x9c30 - 0x9c34 */ + volatile unsigned int BB_spur_report_b0; /* 0x9c34 - 0x9c38 */ + volatile unsigned int BB_channel_status; /* 0x9c38 - 0x9c3c */ + volatile unsigned int BB_rssi_b0; /* 0x9c3c - 0x9c40 */ + volatile unsigned int BB_spur_est_cck_report_b0; /* 0x9c40 - 0x9c44 */ + volatile char pad__13[0x68]; /* 0x9c44 - 0x9cac */ + volatile unsigned int BB_chan_info_noise_pwr; /* 0x9cac - 0x9cb0 */ + volatile unsigned int BB_chan_info_gain_diff; /* 0x9cb0 - 0x9cb4 */ + volatile unsigned int BB_chan_info_fine_timing; /* 0x9cb4 - 0x9cb8 */ + volatile unsigned int BB_chan_info_gain_b0; /* 0x9cb8 - 0x9cbc */ + volatile unsigned int BB_chan_info_chan_tab_b0[60]; /* 0x9cbc - 0x9dac */ + volatile char pad__14[0x38]; /* 0x9dac - 0x9de4 */ + volatile unsigned int BB_paprd_am2am_mask; /* 0x9de4 - 0x9de8 */ + volatile unsigned int BB_paprd_am2pm_mask; /* 0x9de8 - 0x9dec */ + volatile unsigned int BB_paprd_ht40_mask; /* 0x9dec - 0x9df0 */ + volatile unsigned int BB_paprd_ctrl0; /* 0x9df0 - 0x9df4 */ + volatile unsigned int BB_paprd_ctrl1; /* 0x9df4 - 0x9df8 */ + volatile unsigned int BB_pa_gain123; /* 0x9df8 - 0x9dfc */ + volatile unsigned int BB_pa_gain45; /* 0x9dfc - 0x9e00 */ + volatile unsigned int BB_paprd_pre_post_scale_0; /* 0x9e00 - 0x9e04 */ + volatile unsigned int BB_paprd_pre_post_scale_1; /* 0x9e04 - 0x9e08 */ + volatile unsigned int BB_paprd_pre_post_scale_2; /* 0x9e08 - 0x9e0c */ + volatile unsigned int BB_paprd_pre_post_scale_3; /* 0x9e0c - 0x9e10 */ + volatile unsigned int BB_paprd_pre_post_scale_4; /* 0x9e10 - 0x9e14 */ + volatile unsigned int BB_paprd_pre_post_scale_5; /* 0x9e14 - 0x9e18 */ + volatile unsigned int BB_paprd_pre_post_scale_6; /* 0x9e18 - 0x9e1c */ + volatile unsigned int BB_paprd_pre_post_scale_7; /* 0x9e1c - 0x9e20 */ + volatile unsigned int BB_paprd_mem_tab[120]; /* 0x9e20 - 0xa000 */ + volatile unsigned int BB_peak_det_ctrl_1; /* 0xa000 - 0xa004 */ + volatile unsigned int BB_peak_det_ctrl_2; /* 0xa004 - 0xa008 */ + volatile unsigned int BB_rx_gain_bounds_1; /* 0xa008 - 0xa00c */ + volatile unsigned int BB_rx_gain_bounds_2; /* 0xa00c - 0xa010 */ + volatile unsigned int BB_peak_det_cal_ctrl; /* 0xa010 - 0xa014 */ + volatile unsigned int BB_agc_dig_dc_ctrl; /* 0xa014 - 0xa018 */ + volatile unsigned int BB_agc_dig_dc_status_i_b0; /* 0xa018 - 0xa01c */ + volatile unsigned int BB_agc_dig_dc_status_q_b0; /* 0xa01c - 0xa020 */ + volatile char pad__15[0x1d4]; /* 0xa020 - 0xa1f4 */ + volatile unsigned int BB_bbb_txfir_0; /* 0xa1f4 - 0xa1f8 */ + volatile unsigned int BB_bbb_txfir_1; /* 0xa1f8 - 0xa1fc */ + volatile unsigned int BB_bbb_txfir_2; /* 0xa1fc - 0xa200 */ + volatile unsigned int BB_modes_select; /* 0xa200 - 0xa204 */ + volatile unsigned int BB_bbb_tx_ctrl; /* 0xa204 - 0xa208 */ + volatile unsigned int BB_bbb_sig_detect; /* 0xa208 - 0xa20c */ + volatile unsigned int BB_ext_atten_switch_ctl_b0; /* 0xa20c - 0xa210 */ + volatile unsigned int BB_bbb_rx_ctrl_1; /* 0xa210 - 0xa214 */ + volatile unsigned int BB_bbb_rx_ctrl_2; /* 0xa214 - 0xa218 */ + volatile unsigned int BB_bbb_rx_ctrl_3; /* 0xa218 - 0xa21c */ + volatile unsigned int BB_bbb_rx_ctrl_4; /* 0xa21c - 0xa220 */ + volatile unsigned int BB_bbb_rx_ctrl_5; /* 0xa220 - 0xa224 */ + volatile unsigned int BB_bbb_rx_ctrl_6; /* 0xa224 - 0xa228 */ + volatile unsigned int BB_bbb_dagc_ctrl; /* 0xa228 - 0xa22c */ + volatile unsigned int BB_force_clken_cck; /* 0xa22c - 0xa230 */ + volatile unsigned int BB_rx_clear_delay; /* 0xa230 - 0xa234 */ + volatile unsigned int BB_powertx_rate3; /* 0xa234 - 0xa238 */ + volatile unsigned int BB_powertx_rate4; /* 0xa238 - 0xa23c */ + volatile char pad__16[0x4]; /* 0xa23c - 0xa240 */ + volatile unsigned int BB_cck_spur_mit; /* 0xa240 - 0xa244 */ + volatile unsigned int BB_panic_watchdog_status; /* 0xa244 - 0xa248 */ + volatile unsigned int BB_panic_watchdog_ctrl_1; /* 0xa248 - 0xa24c */ + volatile unsigned int BB_panic_watchdog_ctrl_2; /* 0xa24c - 0xa250 */ + volatile unsigned int BB_iqcorr_ctrl_cck; /* 0xa250 - 0xa254 */ + volatile unsigned int BB_bluetooth_cntl; /* 0xa254 - 0xa258 */ + volatile unsigned int BB_tpc_1; /* 0xa258 - 0xa25c */ + volatile unsigned int BB_tpc_2; /* 0xa25c - 0xa260 */ + volatile unsigned int BB_tpc_3; /* 0xa260 - 0xa264 */ + volatile unsigned int BB_tpc_4_b0; /* 0xa264 - 0xa268 */ + volatile unsigned int BB_analog_swap; /* 0xa268 - 0xa26c */ + volatile unsigned int BB_tpc_5_b0; /* 0xa26c - 0xa270 */ + volatile unsigned int BB_tpc_6_b0; /* 0xa270 - 0xa274 */ + volatile unsigned int BB_tpc_7; /* 0xa274 - 0xa278 */ + volatile unsigned int BB_tpc_8; /* 0xa278 - 0xa27c */ + volatile unsigned int BB_tpc_9; /* 0xa27c - 0xa280 */ + volatile unsigned int BB_pdadc_tab_b0[32]; /* 0xa280 - 0xa300 */ + volatile unsigned int BB_cl_tab_b0[16]; /* 0xa300 - 0xa340 */ + volatile unsigned int BB_cl_map_0_b0; /* 0xa340 - 0xa344 */ + volatile unsigned int BB_cl_map_1_b0; /* 0xa344 - 0xa348 */ + volatile unsigned int BB_cl_map_2_b0; /* 0xa348 - 0xa34c */ + volatile unsigned int BB_cl_map_3_b0; /* 0xa34c - 0xa350 */ + volatile char pad__17[0x8]; /* 0xa350 - 0xa358 */ + volatile unsigned int BB_cl_cal_ctrl; /* 0xa358 - 0xa35c */ + volatile unsigned int BB_cl_map_pal_0_b0; /* 0xa35c - 0xa360 */ + volatile unsigned int BB_cl_map_pal_1_b0; /* 0xa360 - 0xa364 */ + volatile unsigned int BB_cl_map_pal_2_b0; /* 0xa364 - 0xa368 */ + volatile unsigned int BB_cl_map_pal_3_b0; /* 0xa368 - 0xa36c */ + volatile char pad__18[0x1c]; /* 0xa36c - 0xa388 */ + volatile unsigned int BB_rifs; /* 0xa388 - 0xa38c */ + volatile unsigned int BB_powertx_rate5; /* 0xa38c - 0xa390 */ + volatile unsigned int BB_powertx_rate6; /* 0xa390 - 0xa394 */ + volatile unsigned int BB_tpc_10; /* 0xa394 - 0xa398 */ + volatile unsigned int BB_tpc_11_b0; /* 0xa398 - 0xa39c */ + volatile unsigned int BB_cal_chain_mask; /* 0xa39c - 0xa3a0 */ + volatile char pad__19[0x1c]; /* 0xa3a0 - 0xa3bc */ + volatile unsigned int BB_powertx_sub; /* 0xa3bc - 0xa3c0 */ + volatile unsigned int BB_powertx_rate7; /* 0xa3c0 - 0xa3c4 */ + volatile unsigned int BB_powertx_rate8; /* 0xa3c4 - 0xa3c8 */ + volatile unsigned int BB_powertx_rate9; /* 0xa3c8 - 0xa3cc */ + volatile unsigned int BB_powertx_rate10; /* 0xa3cc - 0xa3d0 */ + volatile unsigned int BB_powertx_rate11; /* 0xa3d0 - 0xa3d4 */ + volatile unsigned int BB_powertx_rate12; /* 0xa3d4 - 0xa3d8 */ + volatile unsigned int BB_force_analog; /* 0xa3d8 - 0xa3dc */ + volatile unsigned int BB_tpc_12; /* 0xa3dc - 0xa3e0 */ + volatile unsigned int BB_tpc_13; /* 0xa3e0 - 0xa3e4 */ + volatile unsigned int BB_tpc_14; /* 0xa3e4 - 0xa3e8 */ + volatile unsigned int BB_tpc_15; /* 0xa3e8 - 0xa3ec */ + volatile unsigned int BB_tpc_16; /* 0xa3ec - 0xa3f0 */ + volatile unsigned int BB_tpc_17; /* 0xa3f0 - 0xa3f4 */ + volatile unsigned int BB_tpc_18; /* 0xa3f4 - 0xa3f8 */ + volatile unsigned int BB_tpc_19; /* 0xa3f8 - 0xa3fc */ + volatile unsigned int BB_tpc_20; /* 0xa3fc - 0xa400 */ + volatile unsigned int BB_tx_gain_tab_1; /* 0xa400 - 0xa404 */ + volatile unsigned int BB_tx_gain_tab_2; /* 0xa404 - 0xa408 */ + volatile unsigned int BB_tx_gain_tab_3; /* 0xa408 - 0xa40c */ + volatile unsigned int BB_tx_gain_tab_4; /* 0xa40c - 0xa410 */ + volatile unsigned int BB_tx_gain_tab_5; /* 0xa410 - 0xa414 */ + volatile unsigned int BB_tx_gain_tab_6; /* 0xa414 - 0xa418 */ + volatile unsigned int BB_tx_gain_tab_7; /* 0xa418 - 0xa41c */ + volatile unsigned int BB_tx_gain_tab_8; /* 0xa41c - 0xa420 */ + volatile unsigned int BB_tx_gain_tab_9; /* 0xa420 - 0xa424 */ + volatile unsigned int BB_tx_gain_tab_10; /* 0xa424 - 0xa428 */ + volatile unsigned int BB_tx_gain_tab_11; /* 0xa428 - 0xa42c */ + volatile unsigned int BB_tx_gain_tab_12; /* 0xa42c - 0xa430 */ + volatile unsigned int BB_tx_gain_tab_13; /* 0xa430 - 0xa434 */ + volatile unsigned int BB_tx_gain_tab_14; /* 0xa434 - 0xa438 */ + volatile unsigned int BB_tx_gain_tab_15; /* 0xa438 - 0xa43c */ + volatile unsigned int BB_tx_gain_tab_16; /* 0xa43c - 0xa440 */ + volatile unsigned int BB_tx_gain_tab_17; /* 0xa440 - 0xa444 */ + volatile unsigned int BB_tx_gain_tab_18; /* 0xa444 - 0xa448 */ + volatile unsigned int BB_tx_gain_tab_19; /* 0xa448 - 0xa44c */ + volatile unsigned int BB_tx_gain_tab_20; /* 0xa44c - 0xa450 */ + volatile unsigned int BB_tx_gain_tab_21; /* 0xa450 - 0xa454 */ + volatile unsigned int BB_tx_gain_tab_22; /* 0xa454 - 0xa458 */ + volatile unsigned int BB_tx_gain_tab_23; /* 0xa458 - 0xa45c */ + volatile unsigned int BB_tx_gain_tab_24; /* 0xa45c - 0xa460 */ + volatile unsigned int BB_tx_gain_tab_25; /* 0xa460 - 0xa464 */ + volatile unsigned int BB_tx_gain_tab_26; /* 0xa464 - 0xa468 */ + volatile unsigned int BB_tx_gain_tab_27; /* 0xa468 - 0xa46c */ + volatile unsigned int BB_tx_gain_tab_28; /* 0xa46c - 0xa470 */ + volatile unsigned int BB_tx_gain_tab_29; /* 0xa470 - 0xa474 */ + volatile unsigned int BB_tx_gain_tab_30; /* 0xa474 - 0xa478 */ + volatile unsigned int BB_tx_gain_tab_31; /* 0xa478 - 0xa47c */ + volatile unsigned int BB_tx_gain_tab_32; /* 0xa47c - 0xa480 */ + volatile unsigned int BB_tx_gain_tab_pal_1; /* 0xa480 - 0xa484 */ + volatile unsigned int BB_tx_gain_tab_pal_2; /* 0xa484 - 0xa488 */ + volatile unsigned int BB_tx_gain_tab_pal_3; /* 0xa488 - 0xa48c */ + volatile unsigned int BB_tx_gain_tab_pal_4; /* 0xa48c - 0xa490 */ + volatile unsigned int BB_tx_gain_tab_pal_5; /* 0xa490 - 0xa494 */ + volatile unsigned int BB_tx_gain_tab_pal_6; /* 0xa494 - 0xa498 */ + volatile unsigned int BB_tx_gain_tab_pal_7; /* 0xa498 - 0xa49c */ + volatile unsigned int BB_tx_gain_tab_pal_8; /* 0xa49c - 0xa4a0 */ + volatile unsigned int BB_tx_gain_tab_pal_9; /* 0xa4a0 - 0xa4a4 */ + volatile unsigned int BB_tx_gain_tab_pal_10; /* 0xa4a4 - 0xa4a8 */ + volatile unsigned int BB_tx_gain_tab_pal_11; /* 0xa4a8 - 0xa4ac */ + volatile unsigned int BB_tx_gain_tab_pal_12; /* 0xa4ac - 0xa4b0 */ + volatile unsigned int BB_tx_gain_tab_pal_13; /* 0xa4b0 - 0xa4b4 */ + volatile unsigned int BB_tx_gain_tab_pal_14; /* 0xa4b4 - 0xa4b8 */ + volatile unsigned int BB_tx_gain_tab_pal_15; /* 0xa4b8 - 0xa4bc */ + volatile unsigned int BB_tx_gain_tab_pal_16; /* 0xa4bc - 0xa4c0 */ + volatile unsigned int BB_tx_gain_tab_pal_17; /* 0xa4c0 - 0xa4c4 */ + volatile unsigned int BB_tx_gain_tab_pal_18; /* 0xa4c4 - 0xa4c8 */ + volatile unsigned int BB_tx_gain_tab_pal_19; /* 0xa4c8 - 0xa4cc */ + volatile unsigned int BB_tx_gain_tab_pal_20; /* 0xa4cc - 0xa4d0 */ + volatile unsigned int BB_tx_gain_tab_pal_21; /* 0xa4d0 - 0xa4d4 */ + volatile unsigned int BB_tx_gain_tab_pal_22; /* 0xa4d4 - 0xa4d8 */ + volatile unsigned int BB_tx_gain_tab_pal_23; /* 0xa4d8 - 0xa4dc */ + volatile unsigned int BB_tx_gain_tab_pal_24; /* 0xa4dc - 0xa4e0 */ + volatile unsigned int BB_tx_gain_tab_pal_25; /* 0xa4e0 - 0xa4e4 */ + volatile unsigned int BB_tx_gain_tab_pal_26; /* 0xa4e4 - 0xa4e8 */ + volatile unsigned int BB_tx_gain_tab_pal_27; /* 0xa4e8 - 0xa4ec */ + volatile unsigned int BB_tx_gain_tab_pal_28; /* 0xa4ec - 0xa4f0 */ + volatile unsigned int BB_tx_gain_tab_pal_29; /* 0xa4f0 - 0xa4f4 */ + volatile unsigned int BB_tx_gain_tab_pal_30; /* 0xa4f4 - 0xa4f8 */ + volatile unsigned int BB_tx_gain_tab_pal_31; /* 0xa4f8 - 0xa4fc */ + volatile unsigned int BB_tx_gain_tab_pal_32; /* 0xa4fc - 0xa500 */ + volatile char pad__20[0x18]; /* 0xa500 - 0xa518 */ + volatile unsigned int BB_caltx_gain_set_0; /* 0xa518 - 0xa51c */ + volatile unsigned int BB_caltx_gain_set_2; /* 0xa51c - 0xa520 */ + volatile unsigned int BB_caltx_gain_set_4; /* 0xa520 - 0xa524 */ + volatile unsigned int BB_caltx_gain_set_6; /* 0xa524 - 0xa528 */ + volatile unsigned int BB_caltx_gain_set_8; /* 0xa528 - 0xa52c */ + volatile unsigned int BB_caltx_gain_set_10; /* 0xa52c - 0xa530 */ + volatile unsigned int BB_caltx_gain_set_12; /* 0xa530 - 0xa534 */ + volatile unsigned int BB_caltx_gain_set_14; /* 0xa534 - 0xa538 */ + volatile unsigned int BB_caltx_gain_set_16; /* 0xa538 - 0xa53c */ + volatile unsigned int BB_caltx_gain_set_18; /* 0xa53c - 0xa540 */ + volatile unsigned int BB_caltx_gain_set_20; /* 0xa540 - 0xa544 */ + volatile unsigned int BB_caltx_gain_set_22; /* 0xa544 - 0xa548 */ + volatile unsigned int BB_caltx_gain_set_24; /* 0xa548 - 0xa54c */ + volatile unsigned int BB_caltx_gain_set_26; /* 0xa54c - 0xa550 */ + volatile unsigned int BB_caltx_gain_set_28; /* 0xa550 - 0xa554 */ + volatile unsigned int BB_caltx_gain_set_30; /* 0xa554 - 0xa558 */ + volatile unsigned int BB_txiqcal_meas_b0[96]; /* 0xa558 - 0xa6d8 */ + volatile unsigned int BB_txiqcal_start; /* 0xa6d8 - 0xa6dc */ + volatile unsigned int BB_txiqcal_control_0; /* 0xa6dc - 0xa6e0 */ + volatile unsigned int BB_txiqcal_control_1; /* 0xa6e0 - 0xa6e4 */ + volatile unsigned int BB_txiqcal_control_2; /* 0xa6e4 - 0xa6e8 */ + volatile unsigned int BB_txiqcal_control_3; /* 0xa6e8 - 0xa6ec */ + volatile unsigned int BB_txiq_corr_coeff_01_b0; /* 0xa6ec - 0xa6f0 */ + volatile unsigned int BB_txiq_corr_coeff_23_b0; /* 0xa6f0 - 0xa6f4 */ + volatile unsigned int BB_txiq_corr_coeff_45_b0; /* 0xa6f4 - 0xa6f8 */ + volatile unsigned int BB_txiq_corr_coeff_67_b0; /* 0xa6f8 - 0xa6fc */ + volatile unsigned int BB_txiq_corr_coeff_89_b0; /* 0xa6fc - 0xa700 */ + volatile unsigned int BB_txiq_corr_coeff_ab_b0; /* 0xa700 - 0xa704 */ + volatile unsigned int BB_txiq_corr_coeff_cd_b0; /* 0xa704 - 0xa708 */ + volatile unsigned int BB_txiq_corr_coeff_ef_b0; /* 0xa708 - 0xa70c */ + volatile unsigned int BB_cal_rxbb_gain_tbl_0; /* 0xa70c - 0xa710 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_4; /* 0xa710 - 0xa714 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_8; /* 0xa714 - 0xa718 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_12; /* 0xa718 - 0xa71c */ + volatile unsigned int BB_cal_rxbb_gain_tbl_16; /* 0xa71c - 0xa720 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_20; /* 0xa720 - 0xa724 */ + volatile unsigned int BB_cal_rxbb_gain_tbl_24; /* 0xa724 - 0xa728 */ + volatile unsigned int BB_txiqcal_status_b0; /* 0xa728 - 0xa72c */ + volatile unsigned int BB_paprd_trainer_cntl1; /* 0xa72c - 0xa730 */ + volatile unsigned int BB_paprd_trainer_cntl2; /* 0xa730 - 0xa734 */ + volatile unsigned int BB_paprd_trainer_cntl3; /* 0xa734 - 0xa738 */ + volatile unsigned int BB_paprd_trainer_cntl4; /* 0xa738 - 0xa73c */ + volatile unsigned int BB_paprd_trainer_stat1; /* 0xa73c - 0xa740 */ + volatile unsigned int BB_paprd_trainer_stat2; /* 0xa740 - 0xa744 */ + volatile unsigned int BB_paprd_trainer_stat3; /* 0xa744 - 0xa748 */ + volatile char pad__21[0x90]; /* 0xa748 - 0xa7d8 */ + volatile unsigned int BB_fcal_1; /* 0xa7d8 - 0xa7dc */ + volatile unsigned int BB_fcal_2_b0; /* 0xa7dc - 0xa7e0 */ + volatile unsigned int BB_radar_bw_filter; /* 0xa7e0 - 0xa7e4 */ + volatile unsigned int BB_dft_tone_ctrl_b0; /* 0xa7e4 - 0xa7e8 */ + volatile unsigned int BB_therm_adc_1; /* 0xa7e8 - 0xa7ec */ + volatile unsigned int BB_therm_adc_2; /* 0xa7ec - 0xa7f0 */ + volatile unsigned int BB_therm_adc_3; /* 0xa7f0 - 0xa7f4 */ + volatile unsigned int BB_therm_adc_4; /* 0xa7f4 - 0xa7f8 */ + volatile unsigned int BB_tx_forced_gain; /* 0xa7f8 - 0xa7fc */ + volatile unsigned int BB_eco_ctrl; /* 0xa7fc - 0xa800 */ + volatile char pad__22[0x48]; /* 0xa800 - 0xa848 */ + volatile unsigned int BB_gain_force_max_gains_b1; /* 0xa848 - 0xa84c */ + volatile unsigned int BB_gains_min_offsets_b1; /* 0xa84c - 0xa850 */ + volatile char pad__23[0x1b0]; /* 0xa850 - 0xaa00 */ + volatile unsigned int BB_rx_ocgain2[128]; /* 0xaa00 - 0xac00 */ + volatile char pad__24[0x60c]; /* 0xac00 - 0xb20c */ + volatile unsigned int BB_ext_atten_switch_ctl_b1; /* 0xb20c - 0xb210 */ +} bb_lc_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _BB_LC_REG_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h new file mode 100644 index 000000000000..4905152f0c0a --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/efuse_reg.h @@ -0,0 +1,104 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _EFUSE_REG_REG_H_ +#define _EFUSE_REG_REG_H_ + +#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000 +#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000 +#define EFUSE_WR_ENABLE_REG_V_MSB 0 +#define EFUSE_WR_ENABLE_REG_V_LSB 0 +#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001 +#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB) +#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK) + +#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004 +#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004 +#define EFUSE_INT_ENABLE_REG_V_MSB 0 +#define EFUSE_INT_ENABLE_REG_V_LSB 0 +#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001 +#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB) +#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK) + +#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008 +#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008 +#define EFUSE_INT_STATUS_REG_V_MSB 0 +#define EFUSE_INT_STATUS_REG_V_LSB 0 +#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001 +#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB) +#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK) + +#define BITMASK_WR_REG_ADDRESS 0x0000000c +#define BITMASK_WR_REG_OFFSET 0x0000000c +#define BITMASK_WR_REG_V_MSB 31 +#define BITMASK_WR_REG_V_LSB 0 +#define BITMASK_WR_REG_V_MASK 0xffffffff +#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB) +#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK) + +#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010 +#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010 +#define VDDQ_SETTLE_TIME_REG_V_MSB 31 +#define VDDQ_SETTLE_TIME_REG_V_LSB 0 +#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff +#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB) +#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK) + +#define RD_STROBE_PW_REG_ADDRESS 0x00000014 +#define RD_STROBE_PW_REG_OFFSET 0x00000014 +#define RD_STROBE_PW_REG_V_MSB 31 +#define RD_STROBE_PW_REG_V_LSB 0 +#define RD_STROBE_PW_REG_V_MASK 0xffffffff +#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB) +#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK) + +#define PG_STROBE_PW_REG_ADDRESS 0x00000018 +#define PG_STROBE_PW_REG_OFFSET 0x00000018 +#define PG_STROBE_PW_REG_V_MSB 31 +#define PG_STROBE_PW_REG_V_LSB 0 +#define PG_STROBE_PW_REG_V_MASK 0xffffffff +#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB) +#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK) + +#define EFUSE_INTF_ADDRESS 0x00000800 +#define EFUSE_INTF_OFFSET 0x00000800 +#define EFUSE_INTF_R_MSB 31 +#define EFUSE_INTF_R_LSB 0 +#define EFUSE_INTF_R_MASK 0xffffffff +#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB) +#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct efuse_reg_reg_s { + volatile unsigned int efuse_wr_enable_reg; + volatile unsigned int efuse_int_enable_reg; + volatile unsigned int efuse_int_status_reg; + volatile unsigned int bitmask_wr_reg; + volatile unsigned int vddq_settle_time_reg; + volatile unsigned int rd_strobe_pw_reg; + volatile unsigned int pg_strobe_pw_reg; + unsigned char pad0[2020]; /* pad to 0x800 */ + volatile unsigned int efuse_intf[512]; +} efuse_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _EFUSE_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h new file mode 100644 index 000000000000..60ea43b7806e --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h @@ -0,0 +1,1249 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _GPIO_ATHR_WLAN_REG_REG_H_ +#define _GPIO_ATHR_WLAN_REG_REG_H_ + +#define WLAN_GPIO_OUT_ADDRESS 0x00000000 +#define WLAN_GPIO_OUT_OFFSET 0x00000000 +#define WLAN_GPIO_OUT_DATA_MSB 25 +#define WLAN_GPIO_OUT_DATA_LSB 0 +#define WLAN_GPIO_OUT_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_DATA_GET(x) (((x) & WLAN_GPIO_OUT_DATA_MASK) >> WLAN_GPIO_OUT_DATA_LSB) +#define WLAN_GPIO_OUT_DATA_SET(x) (((x) << WLAN_GPIO_OUT_DATA_LSB) & WLAN_GPIO_OUT_DATA_MASK) + +#define WLAN_GPIO_OUT_W1TS_ADDRESS 0x00000004 +#define WLAN_GPIO_OUT_W1TS_OFFSET 0x00000004 +#define WLAN_GPIO_OUT_W1TS_DATA_MSB 25 +#define WLAN_GPIO_OUT_W1TS_DATA_LSB 0 +#define WLAN_GPIO_OUT_W1TS_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TS_DATA_MASK) >> WLAN_GPIO_OUT_W1TS_DATA_LSB) +#define WLAN_GPIO_OUT_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TS_DATA_LSB) & WLAN_GPIO_OUT_W1TS_DATA_MASK) + +#define WLAN_GPIO_OUT_W1TC_ADDRESS 0x00000008 +#define WLAN_GPIO_OUT_W1TC_OFFSET 0x00000008 +#define WLAN_GPIO_OUT_W1TC_DATA_MSB 25 +#define WLAN_GPIO_OUT_W1TC_DATA_LSB 0 +#define WLAN_GPIO_OUT_W1TC_DATA_MASK 0x03ffffff +#define WLAN_GPIO_OUT_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TC_DATA_MASK) >> WLAN_GPIO_OUT_W1TC_DATA_LSB) +#define WLAN_GPIO_OUT_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TC_DATA_LSB) & WLAN_GPIO_OUT_W1TC_DATA_MASK) + +#define WLAN_GPIO_ENABLE_ADDRESS 0x0000000c +#define WLAN_GPIO_ENABLE_OFFSET 0x0000000c +#define WLAN_GPIO_ENABLE_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_DATA_MASK) >> WLAN_GPIO_ENABLE_DATA_LSB) +#define WLAN_GPIO_ENABLE_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_DATA_LSB) & WLAN_GPIO_ENABLE_DATA_MASK) + +#define WLAN_GPIO_ENABLE_W1TS_ADDRESS 0x00000010 +#define WLAN_GPIO_ENABLE_W1TS_OFFSET 0x00000010 +#define WLAN_GPIO_ENABLE_W1TS_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_W1TS_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_W1TS_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TS_DATA_LSB) +#define WLAN_GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TS_DATA_LSB) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) + +#define WLAN_GPIO_ENABLE_W1TC_ADDRESS 0x00000014 +#define WLAN_GPIO_ENABLE_W1TC_OFFSET 0x00000014 +#define WLAN_GPIO_ENABLE_W1TC_DATA_MSB 25 +#define WLAN_GPIO_ENABLE_W1TC_DATA_LSB 0 +#define WLAN_GPIO_ENABLE_W1TC_DATA_MASK 0x03ffffff +#define WLAN_GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TC_DATA_LSB) +#define WLAN_GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TC_DATA_LSB) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) + +#define WLAN_GPIO_IN_ADDRESS 0x00000018 +#define WLAN_GPIO_IN_OFFSET 0x00000018 +#define WLAN_GPIO_IN_DATA_MSB 25 +#define WLAN_GPIO_IN_DATA_LSB 0 +#define WLAN_GPIO_IN_DATA_MASK 0x03ffffff +#define WLAN_GPIO_IN_DATA_GET(x) (((x) & WLAN_GPIO_IN_DATA_MASK) >> WLAN_GPIO_IN_DATA_LSB) +#define WLAN_GPIO_IN_DATA_SET(x) (((x) << WLAN_GPIO_IN_DATA_LSB) & WLAN_GPIO_IN_DATA_MASK) + +#define WLAN_GPIO_STATUS_ADDRESS 0x0000001c +#define WLAN_GPIO_STATUS_OFFSET 0x0000001c +#define WLAN_GPIO_STATUS_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_INTERRUPT_MASK) + +#define WLAN_GPIO_STATUS_W1TS_ADDRESS 0x00000020 +#define WLAN_GPIO_STATUS_W1TS_OFFSET 0x00000020 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) + +#define WLAN_GPIO_STATUS_W1TC_ADDRESS 0x00000024 +#define WLAN_GPIO_STATUS_W1TC_OFFSET 0x00000024 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB 25 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB 0 +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK 0x03ffffff +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) +#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) + +#define WLAN_GPIO_PIN0_ADDRESS 0x00000028 +#define WLAN_GPIO_PIN0_OFFSET 0x00000028 +#define WLAN_GPIO_PIN0_CONFIG_MSB 13 +#define WLAN_GPIO_PIN0_CONFIG_LSB 11 +#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN0_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN0_CONFIG_MASK) >> WLAN_GPIO_PIN0_CONFIG_LSB) +#define WLAN_GPIO_PIN0_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN0_CONFIG_LSB) & WLAN_GPIO_PIN0_CONFIG_MASK) +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN0_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN0_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN0_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN0_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN0_INT_TYPE_MASK) >> WLAN_GPIO_PIN0_INT_TYPE_LSB) +#define WLAN_GPIO_PIN0_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN0_INT_TYPE_LSB) & WLAN_GPIO_PIN0_INT_TYPE_MASK) +#define WLAN_GPIO_PIN0_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN0_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN0_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_PULL_MASK) >> WLAN_GPIO_PIN0_PAD_PULL_LSB) +#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_PULL_LSB) & WLAN_GPIO_PIN0_PAD_PULL_MASK) +#define WLAN_GPIO_PIN0_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN0_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN0_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN0_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN0_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_DRIVER_LSB) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN0_SOURCE_MSB 0 +#define WLAN_GPIO_PIN0_SOURCE_LSB 0 +#define WLAN_GPIO_PIN0_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN0_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN0_SOURCE_MASK) >> WLAN_GPIO_PIN0_SOURCE_LSB) +#define WLAN_GPIO_PIN0_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN0_SOURCE_LSB) & WLAN_GPIO_PIN0_SOURCE_MASK) + +#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c +#define WLAN_GPIO_PIN1_OFFSET 0x0000002c +#define WLAN_GPIO_PIN1_CONFIG_MSB 13 +#define WLAN_GPIO_PIN1_CONFIG_LSB 11 +#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN1_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN1_CONFIG_MASK) >> WLAN_GPIO_PIN1_CONFIG_LSB) +#define WLAN_GPIO_PIN1_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN1_CONFIG_LSB) & WLAN_GPIO_PIN1_CONFIG_MASK) +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN1_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN1_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN1_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN1_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN1_INT_TYPE_MASK) >> WLAN_GPIO_PIN1_INT_TYPE_LSB) +#define WLAN_GPIO_PIN1_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN1_INT_TYPE_LSB) & WLAN_GPIO_PIN1_INT_TYPE_MASK) +#define WLAN_GPIO_PIN1_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN1_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN1_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN1_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_PULL_MASK) >> WLAN_GPIO_PIN1_PAD_PULL_LSB) +#define WLAN_GPIO_PIN1_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_PULL_LSB) & WLAN_GPIO_PIN1_PAD_PULL_MASK) +#define WLAN_GPIO_PIN1_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN1_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN1_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN1_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN1_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_DRIVER_LSB) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN1_SOURCE_MSB 0 +#define WLAN_GPIO_PIN1_SOURCE_LSB 0 +#define WLAN_GPIO_PIN1_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN1_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN1_SOURCE_MASK) >> WLAN_GPIO_PIN1_SOURCE_LSB) +#define WLAN_GPIO_PIN1_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN1_SOURCE_LSB) & WLAN_GPIO_PIN1_SOURCE_MASK) + +#define WLAN_GPIO_PIN2_ADDRESS 0x00000030 +#define WLAN_GPIO_PIN2_OFFSET 0x00000030 +#define WLAN_GPIO_PIN2_CONFIG_MSB 13 +#define WLAN_GPIO_PIN2_CONFIG_LSB 11 +#define WLAN_GPIO_PIN2_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN2_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN2_CONFIG_MASK) >> WLAN_GPIO_PIN2_CONFIG_LSB) +#define WLAN_GPIO_PIN2_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN2_CONFIG_LSB) & WLAN_GPIO_PIN2_CONFIG_MASK) +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN2_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN2_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN2_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN2_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN2_INT_TYPE_MASK) >> WLAN_GPIO_PIN2_INT_TYPE_LSB) +#define WLAN_GPIO_PIN2_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN2_INT_TYPE_LSB) & WLAN_GPIO_PIN2_INT_TYPE_MASK) +#define WLAN_GPIO_PIN2_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN2_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN2_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN2_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_PULL_MASK) >> WLAN_GPIO_PIN2_PAD_PULL_LSB) +#define WLAN_GPIO_PIN2_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_PULL_LSB) & WLAN_GPIO_PIN2_PAD_PULL_MASK) +#define WLAN_GPIO_PIN2_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN2_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN2_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN2_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN2_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_DRIVER_LSB) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN2_SOURCE_MSB 0 +#define WLAN_GPIO_PIN2_SOURCE_LSB 0 +#define WLAN_GPIO_PIN2_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN2_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN2_SOURCE_MASK) >> WLAN_GPIO_PIN2_SOURCE_LSB) +#define WLAN_GPIO_PIN2_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN2_SOURCE_LSB) & WLAN_GPIO_PIN2_SOURCE_MASK) + +#define WLAN_GPIO_PIN3_ADDRESS 0x00000034 +#define WLAN_GPIO_PIN3_OFFSET 0x00000034 +#define WLAN_GPIO_PIN3_CONFIG_MSB 13 +#define WLAN_GPIO_PIN3_CONFIG_LSB 11 +#define WLAN_GPIO_PIN3_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN3_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN3_CONFIG_MASK) >> WLAN_GPIO_PIN3_CONFIG_LSB) +#define WLAN_GPIO_PIN3_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN3_CONFIG_LSB) & WLAN_GPIO_PIN3_CONFIG_MASK) +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN3_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN3_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN3_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN3_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN3_INT_TYPE_MASK) >> WLAN_GPIO_PIN3_INT_TYPE_LSB) +#define WLAN_GPIO_PIN3_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN3_INT_TYPE_LSB) & WLAN_GPIO_PIN3_INT_TYPE_MASK) +#define WLAN_GPIO_PIN3_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN3_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN3_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN3_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_PULL_MASK) >> WLAN_GPIO_PIN3_PAD_PULL_LSB) +#define WLAN_GPIO_PIN3_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_PULL_LSB) & WLAN_GPIO_PIN3_PAD_PULL_MASK) +#define WLAN_GPIO_PIN3_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN3_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN3_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN3_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN3_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_DRIVER_LSB) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN3_SOURCE_MSB 0 +#define WLAN_GPIO_PIN3_SOURCE_LSB 0 +#define WLAN_GPIO_PIN3_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN3_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN3_SOURCE_MASK) >> WLAN_GPIO_PIN3_SOURCE_LSB) +#define WLAN_GPIO_PIN3_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN3_SOURCE_LSB) & WLAN_GPIO_PIN3_SOURCE_MASK) + +#define WLAN_GPIO_PIN4_ADDRESS 0x00000038 +#define WLAN_GPIO_PIN4_OFFSET 0x00000038 +#define WLAN_GPIO_PIN4_CONFIG_MSB 13 +#define WLAN_GPIO_PIN4_CONFIG_LSB 11 +#define WLAN_GPIO_PIN4_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN4_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN4_CONFIG_MASK) >> WLAN_GPIO_PIN4_CONFIG_LSB) +#define WLAN_GPIO_PIN4_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN4_CONFIG_LSB) & WLAN_GPIO_PIN4_CONFIG_MASK) +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN4_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN4_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN4_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN4_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN4_INT_TYPE_MASK) >> WLAN_GPIO_PIN4_INT_TYPE_LSB) +#define WLAN_GPIO_PIN4_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN4_INT_TYPE_LSB) & WLAN_GPIO_PIN4_INT_TYPE_MASK) +#define WLAN_GPIO_PIN4_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN4_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN4_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN4_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_PULL_MASK) >> WLAN_GPIO_PIN4_PAD_PULL_LSB) +#define WLAN_GPIO_PIN4_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_PULL_LSB) & WLAN_GPIO_PIN4_PAD_PULL_MASK) +#define WLAN_GPIO_PIN4_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN4_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN4_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN4_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN4_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_DRIVER_LSB) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN4_SOURCE_MSB 0 +#define WLAN_GPIO_PIN4_SOURCE_LSB 0 +#define WLAN_GPIO_PIN4_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN4_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN4_SOURCE_MASK) >> WLAN_GPIO_PIN4_SOURCE_LSB) +#define WLAN_GPIO_PIN4_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN4_SOURCE_LSB) & WLAN_GPIO_PIN4_SOURCE_MASK) + +#define WLAN_GPIO_PIN5_ADDRESS 0x0000003c +#define WLAN_GPIO_PIN5_OFFSET 0x0000003c +#define WLAN_GPIO_PIN5_CONFIG_MSB 13 +#define WLAN_GPIO_PIN5_CONFIG_LSB 11 +#define WLAN_GPIO_PIN5_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN5_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN5_CONFIG_MASK) >> WLAN_GPIO_PIN5_CONFIG_LSB) +#define WLAN_GPIO_PIN5_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN5_CONFIG_LSB) & WLAN_GPIO_PIN5_CONFIG_MASK) +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN5_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN5_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN5_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN5_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN5_INT_TYPE_MASK) >> WLAN_GPIO_PIN5_INT_TYPE_LSB) +#define WLAN_GPIO_PIN5_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN5_INT_TYPE_LSB) & WLAN_GPIO_PIN5_INT_TYPE_MASK) +#define WLAN_GPIO_PIN5_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN5_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN5_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN5_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_PULL_MASK) >> WLAN_GPIO_PIN5_PAD_PULL_LSB) +#define WLAN_GPIO_PIN5_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_PULL_LSB) & WLAN_GPIO_PIN5_PAD_PULL_MASK) +#define WLAN_GPIO_PIN5_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN5_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN5_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN5_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN5_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_DRIVER_LSB) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN5_SOURCE_MSB 0 +#define WLAN_GPIO_PIN5_SOURCE_LSB 0 +#define WLAN_GPIO_PIN5_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN5_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN5_SOURCE_MASK) >> WLAN_GPIO_PIN5_SOURCE_LSB) +#define WLAN_GPIO_PIN5_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN5_SOURCE_LSB) & WLAN_GPIO_PIN5_SOURCE_MASK) + +#define WLAN_GPIO_PIN6_ADDRESS 0x00000040 +#define WLAN_GPIO_PIN6_OFFSET 0x00000040 +#define WLAN_GPIO_PIN6_CONFIG_MSB 13 +#define WLAN_GPIO_PIN6_CONFIG_LSB 11 +#define WLAN_GPIO_PIN6_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN6_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN6_CONFIG_MASK) >> WLAN_GPIO_PIN6_CONFIG_LSB) +#define WLAN_GPIO_PIN6_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN6_CONFIG_LSB) & WLAN_GPIO_PIN6_CONFIG_MASK) +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN6_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN6_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN6_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN6_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN6_INT_TYPE_MASK) >> WLAN_GPIO_PIN6_INT_TYPE_LSB) +#define WLAN_GPIO_PIN6_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN6_INT_TYPE_LSB) & WLAN_GPIO_PIN6_INT_TYPE_MASK) +#define WLAN_GPIO_PIN6_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN6_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN6_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN6_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_PULL_MASK) >> WLAN_GPIO_PIN6_PAD_PULL_LSB) +#define WLAN_GPIO_PIN6_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_PULL_LSB) & WLAN_GPIO_PIN6_PAD_PULL_MASK) +#define WLAN_GPIO_PIN6_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN6_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN6_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN6_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN6_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_DRIVER_LSB) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN6_SOURCE_MSB 0 +#define WLAN_GPIO_PIN6_SOURCE_LSB 0 +#define WLAN_GPIO_PIN6_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN6_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN6_SOURCE_MASK) >> WLAN_GPIO_PIN6_SOURCE_LSB) +#define WLAN_GPIO_PIN6_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN6_SOURCE_LSB) & WLAN_GPIO_PIN6_SOURCE_MASK) + +#define WLAN_GPIO_PIN7_ADDRESS 0x00000044 +#define WLAN_GPIO_PIN7_OFFSET 0x00000044 +#define WLAN_GPIO_PIN7_CONFIG_MSB 13 +#define WLAN_GPIO_PIN7_CONFIG_LSB 11 +#define WLAN_GPIO_PIN7_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN7_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN7_CONFIG_MASK) >> WLAN_GPIO_PIN7_CONFIG_LSB) +#define WLAN_GPIO_PIN7_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN7_CONFIG_LSB) & WLAN_GPIO_PIN7_CONFIG_MASK) +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN7_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN7_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN7_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN7_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN7_INT_TYPE_MASK) >> WLAN_GPIO_PIN7_INT_TYPE_LSB) +#define WLAN_GPIO_PIN7_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN7_INT_TYPE_LSB) & WLAN_GPIO_PIN7_INT_TYPE_MASK) +#define WLAN_GPIO_PIN7_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN7_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN7_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN7_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_PULL_MASK) >> WLAN_GPIO_PIN7_PAD_PULL_LSB) +#define WLAN_GPIO_PIN7_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_PULL_LSB) & WLAN_GPIO_PIN7_PAD_PULL_MASK) +#define WLAN_GPIO_PIN7_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN7_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN7_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN7_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN7_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_DRIVER_LSB) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN7_SOURCE_MSB 0 +#define WLAN_GPIO_PIN7_SOURCE_LSB 0 +#define WLAN_GPIO_PIN7_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN7_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN7_SOURCE_MASK) >> WLAN_GPIO_PIN7_SOURCE_LSB) +#define WLAN_GPIO_PIN7_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN7_SOURCE_LSB) & WLAN_GPIO_PIN7_SOURCE_MASK) + +#define WLAN_GPIO_PIN8_ADDRESS 0x00000048 +#define WLAN_GPIO_PIN8_OFFSET 0x00000048 +#define WLAN_GPIO_PIN8_CONFIG_MSB 13 +#define WLAN_GPIO_PIN8_CONFIG_LSB 11 +#define WLAN_GPIO_PIN8_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN8_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN8_CONFIG_MASK) >> WLAN_GPIO_PIN8_CONFIG_LSB) +#define WLAN_GPIO_PIN8_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN8_CONFIG_LSB) & WLAN_GPIO_PIN8_CONFIG_MASK) +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN8_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN8_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN8_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN8_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN8_INT_TYPE_MASK) >> WLAN_GPIO_PIN8_INT_TYPE_LSB) +#define WLAN_GPIO_PIN8_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN8_INT_TYPE_LSB) & WLAN_GPIO_PIN8_INT_TYPE_MASK) +#define WLAN_GPIO_PIN8_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN8_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN8_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN8_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_PULL_MASK) >> WLAN_GPIO_PIN8_PAD_PULL_LSB) +#define WLAN_GPIO_PIN8_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_PULL_LSB) & WLAN_GPIO_PIN8_PAD_PULL_MASK) +#define WLAN_GPIO_PIN8_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN8_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN8_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN8_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN8_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_DRIVER_LSB) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN8_SOURCE_MSB 0 +#define WLAN_GPIO_PIN8_SOURCE_LSB 0 +#define WLAN_GPIO_PIN8_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN8_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN8_SOURCE_MASK) >> WLAN_GPIO_PIN8_SOURCE_LSB) +#define WLAN_GPIO_PIN8_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN8_SOURCE_LSB) & WLAN_GPIO_PIN8_SOURCE_MASK) + +#define WLAN_GPIO_PIN9_ADDRESS 0x0000004c +#define WLAN_GPIO_PIN9_OFFSET 0x0000004c +#define WLAN_GPIO_PIN9_CONFIG_MSB 13 +#define WLAN_GPIO_PIN9_CONFIG_LSB 11 +#define WLAN_GPIO_PIN9_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN9_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN9_CONFIG_MASK) >> WLAN_GPIO_PIN9_CONFIG_LSB) +#define WLAN_GPIO_PIN9_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN9_CONFIG_LSB) & WLAN_GPIO_PIN9_CONFIG_MASK) +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN9_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN9_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN9_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN9_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN9_INT_TYPE_MASK) >> WLAN_GPIO_PIN9_INT_TYPE_LSB) +#define WLAN_GPIO_PIN9_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN9_INT_TYPE_LSB) & WLAN_GPIO_PIN9_INT_TYPE_MASK) +#define WLAN_GPIO_PIN9_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN9_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN9_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN9_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_PULL_MASK) >> WLAN_GPIO_PIN9_PAD_PULL_LSB) +#define WLAN_GPIO_PIN9_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_PULL_LSB) & WLAN_GPIO_PIN9_PAD_PULL_MASK) +#define WLAN_GPIO_PIN9_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN9_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN9_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN9_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN9_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_DRIVER_LSB) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN9_SOURCE_MSB 0 +#define WLAN_GPIO_PIN9_SOURCE_LSB 0 +#define WLAN_GPIO_PIN9_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN9_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN9_SOURCE_MASK) >> WLAN_GPIO_PIN9_SOURCE_LSB) +#define WLAN_GPIO_PIN9_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN9_SOURCE_LSB) & WLAN_GPIO_PIN9_SOURCE_MASK) + +#define WLAN_GPIO_PIN10_ADDRESS 0x00000050 +#define WLAN_GPIO_PIN10_OFFSET 0x00000050 +#define WLAN_GPIO_PIN10_CONFIG_MSB 13 +#define WLAN_GPIO_PIN10_CONFIG_LSB 11 +#define WLAN_GPIO_PIN10_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN10_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN10_CONFIG_MASK) >> WLAN_GPIO_PIN10_CONFIG_LSB) +#define WLAN_GPIO_PIN10_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN10_CONFIG_LSB) & WLAN_GPIO_PIN10_CONFIG_MASK) +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN10_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN10_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN10_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN10_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN10_INT_TYPE_MASK) >> WLAN_GPIO_PIN10_INT_TYPE_LSB) +#define WLAN_GPIO_PIN10_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN10_INT_TYPE_LSB) & WLAN_GPIO_PIN10_INT_TYPE_MASK) +#define WLAN_GPIO_PIN10_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN10_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN10_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN10_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_PULL_MASK) >> WLAN_GPIO_PIN10_PAD_PULL_LSB) +#define WLAN_GPIO_PIN10_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_PULL_LSB) & WLAN_GPIO_PIN10_PAD_PULL_MASK) +#define WLAN_GPIO_PIN10_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN10_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN10_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN10_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN10_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_DRIVER_LSB) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN10_SOURCE_MSB 0 +#define WLAN_GPIO_PIN10_SOURCE_LSB 0 +#define WLAN_GPIO_PIN10_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN10_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN10_SOURCE_MASK) >> WLAN_GPIO_PIN10_SOURCE_LSB) +#define WLAN_GPIO_PIN10_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN10_SOURCE_LSB) & WLAN_GPIO_PIN10_SOURCE_MASK) + +#define WLAN_GPIO_PIN11_ADDRESS 0x00000054 +#define WLAN_GPIO_PIN11_OFFSET 0x00000054 +#define WLAN_GPIO_PIN11_CONFIG_MSB 13 +#define WLAN_GPIO_PIN11_CONFIG_LSB 11 +#define WLAN_GPIO_PIN11_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN11_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN11_CONFIG_MASK) >> WLAN_GPIO_PIN11_CONFIG_LSB) +#define WLAN_GPIO_PIN11_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN11_CONFIG_LSB) & WLAN_GPIO_PIN11_CONFIG_MASK) +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN11_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN11_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN11_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN11_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN11_INT_TYPE_MASK) >> WLAN_GPIO_PIN11_INT_TYPE_LSB) +#define WLAN_GPIO_PIN11_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN11_INT_TYPE_LSB) & WLAN_GPIO_PIN11_INT_TYPE_MASK) +#define WLAN_GPIO_PIN11_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN11_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN11_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN11_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_PULL_MASK) >> WLAN_GPIO_PIN11_PAD_PULL_LSB) +#define WLAN_GPIO_PIN11_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_PULL_LSB) & WLAN_GPIO_PIN11_PAD_PULL_MASK) +#define WLAN_GPIO_PIN11_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN11_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN11_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN11_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN11_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_DRIVER_LSB) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN11_SOURCE_MSB 0 +#define WLAN_GPIO_PIN11_SOURCE_LSB 0 +#define WLAN_GPIO_PIN11_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN11_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN11_SOURCE_MASK) >> WLAN_GPIO_PIN11_SOURCE_LSB) +#define WLAN_GPIO_PIN11_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN11_SOURCE_LSB) & WLAN_GPIO_PIN11_SOURCE_MASK) + +#define WLAN_GPIO_PIN12_ADDRESS 0x00000058 +#define WLAN_GPIO_PIN12_OFFSET 0x00000058 +#define WLAN_GPIO_PIN12_CONFIG_MSB 13 +#define WLAN_GPIO_PIN12_CONFIG_LSB 11 +#define WLAN_GPIO_PIN12_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN12_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN12_CONFIG_MASK) >> WLAN_GPIO_PIN12_CONFIG_LSB) +#define WLAN_GPIO_PIN12_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN12_CONFIG_LSB) & WLAN_GPIO_PIN12_CONFIG_MASK) +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN12_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN12_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN12_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN12_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN12_INT_TYPE_MASK) >> WLAN_GPIO_PIN12_INT_TYPE_LSB) +#define WLAN_GPIO_PIN12_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN12_INT_TYPE_LSB) & WLAN_GPIO_PIN12_INT_TYPE_MASK) +#define WLAN_GPIO_PIN12_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN12_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN12_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN12_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_PULL_MASK) >> WLAN_GPIO_PIN12_PAD_PULL_LSB) +#define WLAN_GPIO_PIN12_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_PULL_LSB) & WLAN_GPIO_PIN12_PAD_PULL_MASK) +#define WLAN_GPIO_PIN12_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN12_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN12_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN12_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN12_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_DRIVER_LSB) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN12_SOURCE_MSB 0 +#define WLAN_GPIO_PIN12_SOURCE_LSB 0 +#define WLAN_GPIO_PIN12_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN12_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN12_SOURCE_MASK) >> WLAN_GPIO_PIN12_SOURCE_LSB) +#define WLAN_GPIO_PIN12_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN12_SOURCE_LSB) & WLAN_GPIO_PIN12_SOURCE_MASK) + +#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c +#define WLAN_GPIO_PIN13_OFFSET 0x0000005c +#define WLAN_GPIO_PIN13_CONFIG_MSB 13 +#define WLAN_GPIO_PIN13_CONFIG_LSB 11 +#define WLAN_GPIO_PIN13_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN13_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN13_CONFIG_MASK) >> WLAN_GPIO_PIN13_CONFIG_LSB) +#define WLAN_GPIO_PIN13_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN13_CONFIG_LSB) & WLAN_GPIO_PIN13_CONFIG_MASK) +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN13_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN13_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN13_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN13_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN13_INT_TYPE_MASK) >> WLAN_GPIO_PIN13_INT_TYPE_LSB) +#define WLAN_GPIO_PIN13_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN13_INT_TYPE_LSB) & WLAN_GPIO_PIN13_INT_TYPE_MASK) +#define WLAN_GPIO_PIN13_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN13_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN13_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN13_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_PULL_MASK) >> WLAN_GPIO_PIN13_PAD_PULL_LSB) +#define WLAN_GPIO_PIN13_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_PULL_LSB) & WLAN_GPIO_PIN13_PAD_PULL_MASK) +#define WLAN_GPIO_PIN13_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN13_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN13_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN13_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN13_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_DRIVER_LSB) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN13_SOURCE_MSB 0 +#define WLAN_GPIO_PIN13_SOURCE_LSB 0 +#define WLAN_GPIO_PIN13_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN13_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN13_SOURCE_MASK) >> WLAN_GPIO_PIN13_SOURCE_LSB) +#define WLAN_GPIO_PIN13_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN13_SOURCE_LSB) & WLAN_GPIO_PIN13_SOURCE_MASK) + +#define WLAN_GPIO_PIN14_ADDRESS 0x00000060 +#define WLAN_GPIO_PIN14_OFFSET 0x00000060 +#define WLAN_GPIO_PIN14_CONFIG_MSB 13 +#define WLAN_GPIO_PIN14_CONFIG_LSB 11 +#define WLAN_GPIO_PIN14_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN14_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN14_CONFIG_MASK) >> WLAN_GPIO_PIN14_CONFIG_LSB) +#define WLAN_GPIO_PIN14_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN14_CONFIG_LSB) & WLAN_GPIO_PIN14_CONFIG_MASK) +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN14_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN14_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN14_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN14_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN14_INT_TYPE_MASK) >> WLAN_GPIO_PIN14_INT_TYPE_LSB) +#define WLAN_GPIO_PIN14_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN14_INT_TYPE_LSB) & WLAN_GPIO_PIN14_INT_TYPE_MASK) +#define WLAN_GPIO_PIN14_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN14_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN14_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN14_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_PULL_MASK) >> WLAN_GPIO_PIN14_PAD_PULL_LSB) +#define WLAN_GPIO_PIN14_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_PULL_LSB) & WLAN_GPIO_PIN14_PAD_PULL_MASK) +#define WLAN_GPIO_PIN14_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN14_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN14_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN14_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN14_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_DRIVER_LSB) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN14_SOURCE_MSB 0 +#define WLAN_GPIO_PIN14_SOURCE_LSB 0 +#define WLAN_GPIO_PIN14_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN14_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN14_SOURCE_MASK) >> WLAN_GPIO_PIN14_SOURCE_LSB) +#define WLAN_GPIO_PIN14_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN14_SOURCE_LSB) & WLAN_GPIO_PIN14_SOURCE_MASK) + +#define WLAN_GPIO_PIN15_ADDRESS 0x00000064 +#define WLAN_GPIO_PIN15_OFFSET 0x00000064 +#define WLAN_GPIO_PIN15_CONFIG_MSB 13 +#define WLAN_GPIO_PIN15_CONFIG_LSB 11 +#define WLAN_GPIO_PIN15_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN15_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN15_CONFIG_MASK) >> WLAN_GPIO_PIN15_CONFIG_LSB) +#define WLAN_GPIO_PIN15_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN15_CONFIG_LSB) & WLAN_GPIO_PIN15_CONFIG_MASK) +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN15_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN15_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN15_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN15_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN15_INT_TYPE_MASK) >> WLAN_GPIO_PIN15_INT_TYPE_LSB) +#define WLAN_GPIO_PIN15_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN15_INT_TYPE_LSB) & WLAN_GPIO_PIN15_INT_TYPE_MASK) +#define WLAN_GPIO_PIN15_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN15_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN15_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN15_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_PULL_MASK) >> WLAN_GPIO_PIN15_PAD_PULL_LSB) +#define WLAN_GPIO_PIN15_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_PULL_LSB) & WLAN_GPIO_PIN15_PAD_PULL_MASK) +#define WLAN_GPIO_PIN15_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN15_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN15_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN15_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN15_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_DRIVER_LSB) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN15_SOURCE_MSB 0 +#define WLAN_GPIO_PIN15_SOURCE_LSB 0 +#define WLAN_GPIO_PIN15_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN15_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN15_SOURCE_MASK) >> WLAN_GPIO_PIN15_SOURCE_LSB) +#define WLAN_GPIO_PIN15_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN15_SOURCE_LSB) & WLAN_GPIO_PIN15_SOURCE_MASK) + +#define WLAN_GPIO_PIN16_ADDRESS 0x00000068 +#define WLAN_GPIO_PIN16_OFFSET 0x00000068 +#define WLAN_GPIO_PIN16_CONFIG_MSB 13 +#define WLAN_GPIO_PIN16_CONFIG_LSB 11 +#define WLAN_GPIO_PIN16_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN16_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN16_CONFIG_MASK) >> WLAN_GPIO_PIN16_CONFIG_LSB) +#define WLAN_GPIO_PIN16_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN16_CONFIG_LSB) & WLAN_GPIO_PIN16_CONFIG_MASK) +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN16_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN16_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN16_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN16_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN16_INT_TYPE_MASK) >> WLAN_GPIO_PIN16_INT_TYPE_LSB) +#define WLAN_GPIO_PIN16_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN16_INT_TYPE_LSB) & WLAN_GPIO_PIN16_INT_TYPE_MASK) +#define WLAN_GPIO_PIN16_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN16_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN16_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN16_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_PULL_MASK) >> WLAN_GPIO_PIN16_PAD_PULL_LSB) +#define WLAN_GPIO_PIN16_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_PULL_LSB) & WLAN_GPIO_PIN16_PAD_PULL_MASK) +#define WLAN_GPIO_PIN16_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN16_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN16_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN16_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN16_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_DRIVER_LSB) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN16_SOURCE_MSB 0 +#define WLAN_GPIO_PIN16_SOURCE_LSB 0 +#define WLAN_GPIO_PIN16_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN16_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN16_SOURCE_MASK) >> WLAN_GPIO_PIN16_SOURCE_LSB) +#define WLAN_GPIO_PIN16_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN16_SOURCE_LSB) & WLAN_GPIO_PIN16_SOURCE_MASK) + +#define WLAN_GPIO_PIN17_ADDRESS 0x0000006c +#define WLAN_GPIO_PIN17_OFFSET 0x0000006c +#define WLAN_GPIO_PIN17_CONFIG_MSB 13 +#define WLAN_GPIO_PIN17_CONFIG_LSB 11 +#define WLAN_GPIO_PIN17_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN17_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN17_CONFIG_MASK) >> WLAN_GPIO_PIN17_CONFIG_LSB) +#define WLAN_GPIO_PIN17_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN17_CONFIG_LSB) & WLAN_GPIO_PIN17_CONFIG_MASK) +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN17_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN17_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN17_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN17_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN17_INT_TYPE_MASK) >> WLAN_GPIO_PIN17_INT_TYPE_LSB) +#define WLAN_GPIO_PIN17_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN17_INT_TYPE_LSB) & WLAN_GPIO_PIN17_INT_TYPE_MASK) +#define WLAN_GPIO_PIN17_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN17_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN17_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN17_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_PULL_MASK) >> WLAN_GPIO_PIN17_PAD_PULL_LSB) +#define WLAN_GPIO_PIN17_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_PULL_LSB) & WLAN_GPIO_PIN17_PAD_PULL_MASK) +#define WLAN_GPIO_PIN17_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN17_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN17_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN17_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN17_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_DRIVER_LSB) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN17_SOURCE_MSB 0 +#define WLAN_GPIO_PIN17_SOURCE_LSB 0 +#define WLAN_GPIO_PIN17_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN17_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN17_SOURCE_MASK) >> WLAN_GPIO_PIN17_SOURCE_LSB) +#define WLAN_GPIO_PIN17_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN17_SOURCE_LSB) & WLAN_GPIO_PIN17_SOURCE_MASK) + +#define WLAN_GPIO_PIN18_ADDRESS 0x00000070 +#define WLAN_GPIO_PIN18_OFFSET 0x00000070 +#define WLAN_GPIO_PIN18_CONFIG_MSB 13 +#define WLAN_GPIO_PIN18_CONFIG_LSB 11 +#define WLAN_GPIO_PIN18_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN18_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN18_CONFIG_MASK) >> WLAN_GPIO_PIN18_CONFIG_LSB) +#define WLAN_GPIO_PIN18_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN18_CONFIG_LSB) & WLAN_GPIO_PIN18_CONFIG_MASK) +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN18_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN18_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN18_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN18_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN18_INT_TYPE_MASK) >> WLAN_GPIO_PIN18_INT_TYPE_LSB) +#define WLAN_GPIO_PIN18_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN18_INT_TYPE_LSB) & WLAN_GPIO_PIN18_INT_TYPE_MASK) +#define WLAN_GPIO_PIN18_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN18_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN18_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN18_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_PULL_MASK) >> WLAN_GPIO_PIN18_PAD_PULL_LSB) +#define WLAN_GPIO_PIN18_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_PULL_LSB) & WLAN_GPIO_PIN18_PAD_PULL_MASK) +#define WLAN_GPIO_PIN18_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN18_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN18_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN18_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN18_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN18_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN18_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_DRIVER_LSB) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN18_SOURCE_MSB 0 +#define WLAN_GPIO_PIN18_SOURCE_LSB 0 +#define WLAN_GPIO_PIN18_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN18_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN18_SOURCE_MASK) >> WLAN_GPIO_PIN18_SOURCE_LSB) +#define WLAN_GPIO_PIN18_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN18_SOURCE_LSB) & WLAN_GPIO_PIN18_SOURCE_MASK) + +#define WLAN_GPIO_PIN19_ADDRESS 0x00000074 +#define WLAN_GPIO_PIN19_OFFSET 0x00000074 +#define WLAN_GPIO_PIN19_CONFIG_MSB 13 +#define WLAN_GPIO_PIN19_CONFIG_LSB 11 +#define WLAN_GPIO_PIN19_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN19_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN19_CONFIG_MASK) >> WLAN_GPIO_PIN19_CONFIG_LSB) +#define WLAN_GPIO_PIN19_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN19_CONFIG_LSB) & WLAN_GPIO_PIN19_CONFIG_MASK) +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN19_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN19_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN19_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN19_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN19_INT_TYPE_MASK) >> WLAN_GPIO_PIN19_INT_TYPE_LSB) +#define WLAN_GPIO_PIN19_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN19_INT_TYPE_LSB) & WLAN_GPIO_PIN19_INT_TYPE_MASK) +#define WLAN_GPIO_PIN19_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN19_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN19_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN19_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_PULL_MASK) >> WLAN_GPIO_PIN19_PAD_PULL_LSB) +#define WLAN_GPIO_PIN19_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_PULL_LSB) & WLAN_GPIO_PIN19_PAD_PULL_MASK) +#define WLAN_GPIO_PIN19_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN19_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN19_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN19_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN19_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN19_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN19_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_DRIVER_LSB) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN19_SOURCE_MSB 0 +#define WLAN_GPIO_PIN19_SOURCE_LSB 0 +#define WLAN_GPIO_PIN19_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN19_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN19_SOURCE_MASK) >> WLAN_GPIO_PIN19_SOURCE_LSB) +#define WLAN_GPIO_PIN19_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN19_SOURCE_LSB) & WLAN_GPIO_PIN19_SOURCE_MASK) + +#define WLAN_GPIO_PIN20_ADDRESS 0x00000078 +#define WLAN_GPIO_PIN20_OFFSET 0x00000078 +#define WLAN_GPIO_PIN20_CONFIG_MSB 13 +#define WLAN_GPIO_PIN20_CONFIG_LSB 11 +#define WLAN_GPIO_PIN20_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN20_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN20_CONFIG_MASK) >> WLAN_GPIO_PIN20_CONFIG_LSB) +#define WLAN_GPIO_PIN20_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN20_CONFIG_LSB) & WLAN_GPIO_PIN20_CONFIG_MASK) +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN20_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN20_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN20_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN20_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN20_INT_TYPE_MASK) >> WLAN_GPIO_PIN20_INT_TYPE_LSB) +#define WLAN_GPIO_PIN20_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN20_INT_TYPE_LSB) & WLAN_GPIO_PIN20_INT_TYPE_MASK) +#define WLAN_GPIO_PIN20_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN20_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN20_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN20_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_PULL_MASK) >> WLAN_GPIO_PIN20_PAD_PULL_LSB) +#define WLAN_GPIO_PIN20_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_PULL_LSB) & WLAN_GPIO_PIN20_PAD_PULL_MASK) +#define WLAN_GPIO_PIN20_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN20_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN20_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN20_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN20_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN20_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN20_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_DRIVER_LSB) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN20_SOURCE_MSB 0 +#define WLAN_GPIO_PIN20_SOURCE_LSB 0 +#define WLAN_GPIO_PIN20_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN20_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN20_SOURCE_MASK) >> WLAN_GPIO_PIN20_SOURCE_LSB) +#define WLAN_GPIO_PIN20_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN20_SOURCE_LSB) & WLAN_GPIO_PIN20_SOURCE_MASK) + +#define WLAN_GPIO_PIN21_ADDRESS 0x0000007c +#define WLAN_GPIO_PIN21_OFFSET 0x0000007c +#define WLAN_GPIO_PIN21_CONFIG_MSB 13 +#define WLAN_GPIO_PIN21_CONFIG_LSB 11 +#define WLAN_GPIO_PIN21_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN21_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN21_CONFIG_MASK) >> WLAN_GPIO_PIN21_CONFIG_LSB) +#define WLAN_GPIO_PIN21_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN21_CONFIG_LSB) & WLAN_GPIO_PIN21_CONFIG_MASK) +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN21_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN21_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN21_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN21_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN21_INT_TYPE_MASK) >> WLAN_GPIO_PIN21_INT_TYPE_LSB) +#define WLAN_GPIO_PIN21_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN21_INT_TYPE_LSB) & WLAN_GPIO_PIN21_INT_TYPE_MASK) +#define WLAN_GPIO_PIN21_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN21_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN21_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN21_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_PULL_MASK) >> WLAN_GPIO_PIN21_PAD_PULL_LSB) +#define WLAN_GPIO_PIN21_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_PULL_LSB) & WLAN_GPIO_PIN21_PAD_PULL_MASK) +#define WLAN_GPIO_PIN21_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN21_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN21_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN21_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN21_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN21_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN21_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_DRIVER_LSB) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN21_SOURCE_MSB 0 +#define WLAN_GPIO_PIN21_SOURCE_LSB 0 +#define WLAN_GPIO_PIN21_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN21_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN21_SOURCE_MASK) >> WLAN_GPIO_PIN21_SOURCE_LSB) +#define WLAN_GPIO_PIN21_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN21_SOURCE_LSB) & WLAN_GPIO_PIN21_SOURCE_MASK) + +#define WLAN_GPIO_PIN22_ADDRESS 0x00000080 +#define WLAN_GPIO_PIN22_OFFSET 0x00000080 +#define WLAN_GPIO_PIN22_CONFIG_MSB 13 +#define WLAN_GPIO_PIN22_CONFIG_LSB 11 +#define WLAN_GPIO_PIN22_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN22_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN22_CONFIG_MASK) >> WLAN_GPIO_PIN22_CONFIG_LSB) +#define WLAN_GPIO_PIN22_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN22_CONFIG_LSB) & WLAN_GPIO_PIN22_CONFIG_MASK) +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN22_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN22_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN22_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN22_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN22_INT_TYPE_MASK) >> WLAN_GPIO_PIN22_INT_TYPE_LSB) +#define WLAN_GPIO_PIN22_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN22_INT_TYPE_LSB) & WLAN_GPIO_PIN22_INT_TYPE_MASK) +#define WLAN_GPIO_PIN22_PAD_PULL_MSB 6 +#define WLAN_GPIO_PIN22_PAD_PULL_LSB 5 +#define WLAN_GPIO_PIN22_PAD_PULL_MASK 0x00000060 +#define WLAN_GPIO_PIN22_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_PULL_MASK) >> WLAN_GPIO_PIN22_PAD_PULL_LSB) +#define WLAN_GPIO_PIN22_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_PULL_LSB) & WLAN_GPIO_PIN22_PAD_PULL_MASK) +#define WLAN_GPIO_PIN22_PAD_STRENGTH_MSB 4 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_LSB 3 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_MASK 0x00000018 +#define WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) +#define WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) +#define WLAN_GPIO_PIN22_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN22_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN22_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN22_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN22_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN22_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_DRIVER_LSB) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN22_SOURCE_MSB 0 +#define WLAN_GPIO_PIN22_SOURCE_LSB 0 +#define WLAN_GPIO_PIN22_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN22_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN22_SOURCE_MASK) >> WLAN_GPIO_PIN22_SOURCE_LSB) +#define WLAN_GPIO_PIN22_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN22_SOURCE_LSB) & WLAN_GPIO_PIN22_SOURCE_MASK) + +#define WLAN_GPIO_PIN23_ADDRESS 0x00000084 +#define WLAN_GPIO_PIN23_OFFSET 0x00000084 +#define WLAN_GPIO_PIN23_CONFIG_MSB 13 +#define WLAN_GPIO_PIN23_CONFIG_LSB 11 +#define WLAN_GPIO_PIN23_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN23_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN23_CONFIG_MASK) >> WLAN_GPIO_PIN23_CONFIG_LSB) +#define WLAN_GPIO_PIN23_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN23_CONFIG_LSB) & WLAN_GPIO_PIN23_CONFIG_MASK) +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN23_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN23_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN23_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN23_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN23_INT_TYPE_MASK) >> WLAN_GPIO_PIN23_INT_TYPE_LSB) +#define WLAN_GPIO_PIN23_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN23_INT_TYPE_LSB) & WLAN_GPIO_PIN23_INT_TYPE_MASK) +#define WLAN_GPIO_PIN23_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN23_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN23_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN23_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN23_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN23_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN23_PAD_DRIVER_LSB) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN23_SOURCE_MSB 0 +#define WLAN_GPIO_PIN23_SOURCE_LSB 0 +#define WLAN_GPIO_PIN23_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN23_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN23_SOURCE_MASK) >> WLAN_GPIO_PIN23_SOURCE_LSB) +#define WLAN_GPIO_PIN23_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN23_SOURCE_LSB) & WLAN_GPIO_PIN23_SOURCE_MASK) + +#define WLAN_GPIO_PIN24_ADDRESS 0x00000088 +#define WLAN_GPIO_PIN24_OFFSET 0x00000088 +#define WLAN_GPIO_PIN24_CONFIG_MSB 13 +#define WLAN_GPIO_PIN24_CONFIG_LSB 11 +#define WLAN_GPIO_PIN24_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN24_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN24_CONFIG_MASK) >> WLAN_GPIO_PIN24_CONFIG_LSB) +#define WLAN_GPIO_PIN24_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN24_CONFIG_LSB) & WLAN_GPIO_PIN24_CONFIG_MASK) +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN24_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN24_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN24_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN24_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN24_INT_TYPE_MASK) >> WLAN_GPIO_PIN24_INT_TYPE_LSB) +#define WLAN_GPIO_PIN24_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN24_INT_TYPE_LSB) & WLAN_GPIO_PIN24_INT_TYPE_MASK) +#define WLAN_GPIO_PIN24_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN24_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN24_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN24_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN24_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN24_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN24_PAD_DRIVER_LSB) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN24_SOURCE_MSB 0 +#define WLAN_GPIO_PIN24_SOURCE_LSB 0 +#define WLAN_GPIO_PIN24_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN24_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN24_SOURCE_MASK) >> WLAN_GPIO_PIN24_SOURCE_LSB) +#define WLAN_GPIO_PIN24_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN24_SOURCE_LSB) & WLAN_GPIO_PIN24_SOURCE_MASK) + +#define WLAN_GPIO_PIN25_ADDRESS 0x0000008c +#define WLAN_GPIO_PIN25_OFFSET 0x0000008c +#define WLAN_GPIO_PIN25_CONFIG_MSB 13 +#define WLAN_GPIO_PIN25_CONFIG_LSB 11 +#define WLAN_GPIO_PIN25_CONFIG_MASK 0x00003800 +#define WLAN_GPIO_PIN25_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN25_CONFIG_MASK) >> WLAN_GPIO_PIN25_CONFIG_LSB) +#define WLAN_GPIO_PIN25_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN25_CONFIG_LSB) & WLAN_GPIO_PIN25_CONFIG_MASK) +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB 10 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB 10 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK 0x00000400 +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) +#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) +#define WLAN_GPIO_PIN25_INT_TYPE_MSB 9 +#define WLAN_GPIO_PIN25_INT_TYPE_LSB 7 +#define WLAN_GPIO_PIN25_INT_TYPE_MASK 0x00000380 +#define WLAN_GPIO_PIN25_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN25_INT_TYPE_MASK) >> WLAN_GPIO_PIN25_INT_TYPE_LSB) +#define WLAN_GPIO_PIN25_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN25_INT_TYPE_LSB) & WLAN_GPIO_PIN25_INT_TYPE_MASK) +#define WLAN_GPIO_PIN25_PAD_DRIVER_MSB 2 +#define WLAN_GPIO_PIN25_PAD_DRIVER_LSB 2 +#define WLAN_GPIO_PIN25_PAD_DRIVER_MASK 0x00000004 +#define WLAN_GPIO_PIN25_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN25_PAD_DRIVER_LSB) +#define WLAN_GPIO_PIN25_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN25_PAD_DRIVER_LSB) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) +#define WLAN_GPIO_PIN25_SOURCE_MSB 0 +#define WLAN_GPIO_PIN25_SOURCE_LSB 0 +#define WLAN_GPIO_PIN25_SOURCE_MASK 0x00000001 +#define WLAN_GPIO_PIN25_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN25_SOURCE_MASK) >> WLAN_GPIO_PIN25_SOURCE_LSB) +#define WLAN_GPIO_PIN25_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN25_SOURCE_LSB) & WLAN_GPIO_PIN25_SOURCE_MASK) + +#define SDIO_ADDRESS 0x00000090 +#define SDIO_OFFSET 0x00000090 +#define SDIO_PINS_EN_MSB 0 +#define SDIO_PINS_EN_LSB 0 +#define SDIO_PINS_EN_MASK 0x00000001 +#define SDIO_PINS_EN_GET(x) (((x) & SDIO_PINS_EN_MASK) >> SDIO_PINS_EN_LSB) +#define SDIO_PINS_EN_SET(x) (((x) << SDIO_PINS_EN_LSB) & SDIO_PINS_EN_MASK) + +#define FUNC_BUS_ADDRESS 0x00000094 +#define FUNC_BUS_OFFSET 0x00000094 +#define FUNC_BUS_GPIO_MODE_MSB 22 +#define FUNC_BUS_GPIO_MODE_LSB 22 +#define FUNC_BUS_GPIO_MODE_MASK 0x00400000 +#define FUNC_BUS_GPIO_MODE_GET(x) (((x) & FUNC_BUS_GPIO_MODE_MASK) >> FUNC_BUS_GPIO_MODE_LSB) +#define FUNC_BUS_GPIO_MODE_SET(x) (((x) << FUNC_BUS_GPIO_MODE_LSB) & FUNC_BUS_GPIO_MODE_MASK) +#define FUNC_BUS_OE_L_MSB 21 +#define FUNC_BUS_OE_L_LSB 0 +#define FUNC_BUS_OE_L_MASK 0x003fffff +#define FUNC_BUS_OE_L_GET(x) (((x) & FUNC_BUS_OE_L_MASK) >> FUNC_BUS_OE_L_LSB) +#define FUNC_BUS_OE_L_SET(x) (((x) << FUNC_BUS_OE_L_LSB) & FUNC_BUS_OE_L_MASK) + +#define WL_SOC_APB_ADDRESS 0x00000098 +#define WL_SOC_APB_OFFSET 0x00000098 +#define WL_SOC_APB_TOGGLE_MSB 0 +#define WL_SOC_APB_TOGGLE_LSB 0 +#define WL_SOC_APB_TOGGLE_MASK 0x00000001 +#define WL_SOC_APB_TOGGLE_GET(x) (((x) & WL_SOC_APB_TOGGLE_MASK) >> WL_SOC_APB_TOGGLE_LSB) +#define WL_SOC_APB_TOGGLE_SET(x) (((x) << WL_SOC_APB_TOGGLE_LSB) & WL_SOC_APB_TOGGLE_MASK) + +#define WLAN_SIGMA_DELTA_ADDRESS 0x0000009c +#define WLAN_SIGMA_DELTA_OFFSET 0x0000009c +#define WLAN_SIGMA_DELTA_ENABLE_MSB 16 +#define WLAN_SIGMA_DELTA_ENABLE_LSB 16 +#define WLAN_SIGMA_DELTA_ENABLE_MASK 0x00010000 +#define WLAN_SIGMA_DELTA_ENABLE_GET(x) (((x) & WLAN_SIGMA_DELTA_ENABLE_MASK) >> WLAN_SIGMA_DELTA_ENABLE_LSB) +#define WLAN_SIGMA_DELTA_ENABLE_SET(x) (((x) << WLAN_SIGMA_DELTA_ENABLE_LSB) & WLAN_SIGMA_DELTA_ENABLE_MASK) +#define WLAN_SIGMA_DELTA_PRESCALAR_MSB 15 +#define WLAN_SIGMA_DELTA_PRESCALAR_LSB 8 +#define WLAN_SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00 +#define WLAN_SIGMA_DELTA_PRESCALAR_GET(x) (((x) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) >> WLAN_SIGMA_DELTA_PRESCALAR_LSB) +#define WLAN_SIGMA_DELTA_PRESCALAR_SET(x) (((x) << WLAN_SIGMA_DELTA_PRESCALAR_LSB) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) +#define WLAN_SIGMA_DELTA_TARGET_MSB 7 +#define WLAN_SIGMA_DELTA_TARGET_LSB 0 +#define WLAN_SIGMA_DELTA_TARGET_MASK 0x000000ff +#define WLAN_SIGMA_DELTA_TARGET_GET(x) (((x) & WLAN_SIGMA_DELTA_TARGET_MASK) >> WLAN_SIGMA_DELTA_TARGET_LSB) +#define WLAN_SIGMA_DELTA_TARGET_SET(x) (((x) << WLAN_SIGMA_DELTA_TARGET_LSB) & WLAN_SIGMA_DELTA_TARGET_MASK) + +#define WL_BOOTSTRAP_ADDRESS 0x000000a0 +#define WL_BOOTSTRAP_OFFSET 0x000000a0 +#define WL_BOOTSTRAP_STATUS_MSB 22 +#define WL_BOOTSTRAP_STATUS_LSB 0 +#define WL_BOOTSTRAP_STATUS_MASK 0x007fffff +#define WL_BOOTSTRAP_STATUS_GET(x) (((x) & WL_BOOTSTRAP_STATUS_MASK) >> WL_BOOTSTRAP_STATUS_LSB) +#define WL_BOOTSTRAP_STATUS_SET(x) (((x) << WL_BOOTSTRAP_STATUS_LSB) & WL_BOOTSTRAP_STATUS_MASK) + +#define CLOCK_GPIO_ADDRESS 0x000000a4 +#define CLOCK_GPIO_OFFSET 0x000000a4 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_MSB 2 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_LSB 2 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_MASK 0x00000004 +#define CLOCK_GPIO_CLK_REQ_OUT_EN_GET(x) (((x) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) >> CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) +#define CLOCK_GPIO_CLK_REQ_OUT_EN_SET(x) (((x) << CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) +#define CLOCK_GPIO_BT_CLK_REQ_EN_MSB 1 +#define CLOCK_GPIO_BT_CLK_REQ_EN_LSB 1 +#define CLOCK_GPIO_BT_CLK_REQ_EN_MASK 0x00000002 +#define CLOCK_GPIO_BT_CLK_REQ_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) >> CLOCK_GPIO_BT_CLK_REQ_EN_LSB) +#define CLOCK_GPIO_BT_CLK_REQ_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_REQ_EN_LSB) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) +#define CLOCK_GPIO_BT_CLK_OUT_EN_MSB 0 +#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 +#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0x00000001 +#define CLOCK_GPIO_BT_CLK_OUT_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) >> CLOCK_GPIO_BT_CLK_OUT_EN_LSB) +#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) + +#define WLAN_DEBUG_CONTROL_ADDRESS 0x000000a8 +#define WLAN_DEBUG_CONTROL_OFFSET 0x000000a8 +#define WLAN_DEBUG_CONTROL_ENABLE_MSB 0 +#define WLAN_DEBUG_CONTROL_ENABLE_LSB 0 +#define WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> WLAN_DEBUG_CONTROL_ENABLE_LSB) +#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & WLAN_DEBUG_CONTROL_ENABLE_MASK) + +#define WLAN_DEBUG_INPUT_SEL_ADDRESS 0x000000ac +#define WLAN_DEBUG_INPUT_SEL_OFFSET 0x000000ac +#define WLAN_DEBUG_INPUT_SEL_SHIFT_MSB 5 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_LSB 4 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_MASK 0x00000030 +#define WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) >> WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) +#define WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) +#define WLAN_DEBUG_INPUT_SEL_SRC_MSB 3 +#define WLAN_DEBUG_INPUT_SEL_SRC_LSB 0 +#define WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f +#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> WLAN_DEBUG_INPUT_SEL_SRC_LSB) +#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) + +#define WLAN_DEBUG_OUT_ADDRESS 0x000000b0 +#define WLAN_DEBUG_OUT_OFFSET 0x000000b0 +#define WLAN_DEBUG_OUT_DATA_MSB 17 +#define WLAN_DEBUG_OUT_DATA_LSB 0 +#define WLAN_DEBUG_OUT_DATA_MASK 0x0003ffff +#define WLAN_DEBUG_OUT_DATA_GET(x) (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) +#define WLAN_DEBUG_OUT_DATA_SET(x) (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) + +#define WLAN_RESET_TUPLE_STATUS_ADDRESS 0x000000b4 +#define WLAN_RESET_TUPLE_STATUS_OFFSET 0x000000b4 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00 +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) +#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7 +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0 +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) +#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) + +#define ANTENNA_SLEEP_CONTROL_ADDRESS 0x000000b8 +#define ANTENNA_SLEEP_CONTROL_OFFSET 0x000000b8 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MSB 14 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB 10 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK 0x00007c00 +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) >> ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) +#define ANTENNA_SLEEP_CONTROL_OVERRIDE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) +#define ANTENNA_SLEEP_CONTROL_VALUE_MSB 9 +#define ANTENNA_SLEEP_CONTROL_VALUE_LSB 5 +#define ANTENNA_SLEEP_CONTROL_VALUE_MASK 0x000003e0 +#define ANTENNA_SLEEP_CONTROL_VALUE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) >> ANTENNA_SLEEP_CONTROL_VALUE_LSB) +#define ANTENNA_SLEEP_CONTROL_VALUE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_VALUE_LSB) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) +#define ANTENNA_SLEEP_CONTROL_ENABLE_MSB 4 +#define ANTENNA_SLEEP_CONTROL_ENABLE_LSB 0 +#define ANTENNA_SLEEP_CONTROL_ENABLE_MASK 0x0000001f +#define ANTENNA_SLEEP_CONTROL_ENABLE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) >> ANTENNA_SLEEP_CONTROL_ENABLE_LSB) +#define ANTENNA_SLEEP_CONTROL_ENABLE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_ENABLE_LSB) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct gpio_athr_wlan_reg_reg_s { + volatile unsigned int wlan_gpio_out; + volatile unsigned int wlan_gpio_out_w1ts; + volatile unsigned int wlan_gpio_out_w1tc; + volatile unsigned int wlan_gpio_enable; + volatile unsigned int wlan_gpio_enable_w1ts; + volatile unsigned int wlan_gpio_enable_w1tc; + volatile unsigned int wlan_gpio_in; + volatile unsigned int wlan_gpio_status; + volatile unsigned int wlan_gpio_status_w1ts; + volatile unsigned int wlan_gpio_status_w1tc; + volatile unsigned int wlan_gpio_pin0; + volatile unsigned int wlan_gpio_pin1; + volatile unsigned int wlan_gpio_pin2; + volatile unsigned int wlan_gpio_pin3; + volatile unsigned int wlan_gpio_pin4; + volatile unsigned int wlan_gpio_pin5; + volatile unsigned int wlan_gpio_pin6; + volatile unsigned int wlan_gpio_pin7; + volatile unsigned int wlan_gpio_pin8; + volatile unsigned int wlan_gpio_pin9; + volatile unsigned int wlan_gpio_pin10; + volatile unsigned int wlan_gpio_pin11; + volatile unsigned int wlan_gpio_pin12; + volatile unsigned int wlan_gpio_pin13; + volatile unsigned int wlan_gpio_pin14; + volatile unsigned int wlan_gpio_pin15; + volatile unsigned int wlan_gpio_pin16; + volatile unsigned int wlan_gpio_pin17; + volatile unsigned int wlan_gpio_pin18; + volatile unsigned int wlan_gpio_pin19; + volatile unsigned int wlan_gpio_pin20; + volatile unsigned int wlan_gpio_pin21; + volatile unsigned int wlan_gpio_pin22; + volatile unsigned int wlan_gpio_pin23; + volatile unsigned int wlan_gpio_pin24; + volatile unsigned int wlan_gpio_pin25; + volatile unsigned int sdio; + volatile unsigned int func_bus; + volatile unsigned int wl_soc_apb; + volatile unsigned int wlan_sigma_delta; + volatile unsigned int wl_bootstrap; + volatile unsigned int clock_gpio; + volatile unsigned int wlan_debug_control; + volatile unsigned int wlan_debug_input_sel; + volatile unsigned int wlan_debug_out; + volatile unsigned int wlan_reset_tuple_status; + volatile unsigned int antenna_sleep_control; +} gpio_athr_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _GPIO_ATHR_WLAN_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h new file mode 100644 index 000000000000..2d5c1cd22aa6 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/gpio_reg.h @@ -0,0 +1,1090 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "gpio_athr_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define GPIO_OUT_ADDRESS WLAN_GPIO_OUT_ADDRESS +#define GPIO_OUT_OFFSET WLAN_GPIO_OUT_OFFSET +#define GPIO_OUT_DATA_MSB WLAN_GPIO_OUT_DATA_MSB +#define GPIO_OUT_DATA_LSB WLAN_GPIO_OUT_DATA_LSB +#define GPIO_OUT_DATA_MASK WLAN_GPIO_OUT_DATA_MASK +#define GPIO_OUT_DATA_GET(x) WLAN_GPIO_OUT_DATA_GET(x) +#define GPIO_OUT_DATA_SET(x) WLAN_GPIO_OUT_DATA_SET(x) +#define GPIO_OUT_W1TS_ADDRESS WLAN_GPIO_OUT_W1TS_ADDRESS +#define GPIO_OUT_W1TS_OFFSET WLAN_GPIO_OUT_W1TS_OFFSET +#define GPIO_OUT_W1TS_DATA_MSB WLAN_GPIO_OUT_W1TS_DATA_MSB +#define GPIO_OUT_W1TS_DATA_LSB WLAN_GPIO_OUT_W1TS_DATA_LSB +#define GPIO_OUT_W1TS_DATA_MASK WLAN_GPIO_OUT_W1TS_DATA_MASK +#define GPIO_OUT_W1TS_DATA_GET(x) WLAN_GPIO_OUT_W1TS_DATA_GET(x) +#define GPIO_OUT_W1TS_DATA_SET(x) WLAN_GPIO_OUT_W1TS_DATA_SET(x) +#define GPIO_OUT_W1TC_ADDRESS WLAN_GPIO_OUT_W1TC_ADDRESS +#define GPIO_OUT_W1TC_OFFSET WLAN_GPIO_OUT_W1TC_OFFSET +#define GPIO_OUT_W1TC_DATA_MSB WLAN_GPIO_OUT_W1TC_DATA_MSB +#define GPIO_OUT_W1TC_DATA_LSB WLAN_GPIO_OUT_W1TC_DATA_LSB +#define GPIO_OUT_W1TC_DATA_MASK WLAN_GPIO_OUT_W1TC_DATA_MASK +#define GPIO_OUT_W1TC_DATA_GET(x) WLAN_GPIO_OUT_W1TC_DATA_GET(x) +#define GPIO_OUT_W1TC_DATA_SET(x) WLAN_GPIO_OUT_W1TC_DATA_SET(x) +#define GPIO_ENABLE_ADDRESS WLAN_GPIO_ENABLE_ADDRESS +#define GPIO_ENABLE_OFFSET WLAN_GPIO_ENABLE_OFFSET +#define GPIO_ENABLE_DATA_MSB WLAN_GPIO_ENABLE_DATA_MSB +#define GPIO_ENABLE_DATA_LSB WLAN_GPIO_ENABLE_DATA_LSB +#define GPIO_ENABLE_DATA_MASK WLAN_GPIO_ENABLE_DATA_MASK +#define GPIO_ENABLE_DATA_GET(x) WLAN_GPIO_ENABLE_DATA_GET(x) +#define GPIO_ENABLE_DATA_SET(x) WLAN_GPIO_ENABLE_DATA_SET(x) +#define GPIO_ENABLE_W1TS_ADDRESS WLAN_GPIO_ENABLE_W1TS_ADDRESS +#define GPIO_ENABLE_W1TS_OFFSET WLAN_GPIO_ENABLE_W1TS_OFFSET +#define GPIO_ENABLE_W1TS_DATA_MSB WLAN_GPIO_ENABLE_W1TS_DATA_MSB +#define GPIO_ENABLE_W1TS_DATA_LSB WLAN_GPIO_ENABLE_W1TS_DATA_LSB +#define GPIO_ENABLE_W1TS_DATA_MASK WLAN_GPIO_ENABLE_W1TS_DATA_MASK +#define GPIO_ENABLE_W1TS_DATA_GET(x) WLAN_GPIO_ENABLE_W1TS_DATA_GET(x) +#define GPIO_ENABLE_W1TS_DATA_SET(x) WLAN_GPIO_ENABLE_W1TS_DATA_SET(x) +#define GPIO_ENABLE_W1TC_ADDRESS WLAN_GPIO_ENABLE_W1TC_ADDRESS +#define GPIO_ENABLE_W1TC_OFFSET WLAN_GPIO_ENABLE_W1TC_OFFSET +#define GPIO_ENABLE_W1TC_DATA_MSB WLAN_GPIO_ENABLE_W1TC_DATA_MSB +#define GPIO_ENABLE_W1TC_DATA_LSB WLAN_GPIO_ENABLE_W1TC_DATA_LSB +#define GPIO_ENABLE_W1TC_DATA_MASK WLAN_GPIO_ENABLE_W1TC_DATA_MASK +#define GPIO_ENABLE_W1TC_DATA_GET(x) WLAN_GPIO_ENABLE_W1TC_DATA_GET(x) +#define GPIO_ENABLE_W1TC_DATA_SET(x) WLAN_GPIO_ENABLE_W1TC_DATA_SET(x) +#define GPIO_IN_ADDRESS WLAN_GPIO_IN_ADDRESS +#define GPIO_IN_OFFSET WLAN_GPIO_IN_OFFSET +#define GPIO_IN_DATA_MSB WLAN_GPIO_IN_DATA_MSB +#define GPIO_IN_DATA_LSB WLAN_GPIO_IN_DATA_LSB +#define GPIO_IN_DATA_MASK WLAN_GPIO_IN_DATA_MASK +#define GPIO_IN_DATA_GET(x) WLAN_GPIO_IN_DATA_GET(x) +#define GPIO_IN_DATA_SET(x) WLAN_GPIO_IN_DATA_SET(x) +#define GPIO_STATUS_ADDRESS WLAN_GPIO_STATUS_ADDRESS +#define GPIO_STATUS_OFFSET WLAN_GPIO_STATUS_OFFSET +#define GPIO_STATUS_INTERRUPT_MSB WLAN_GPIO_STATUS_INTERRUPT_MSB +#define GPIO_STATUS_INTERRUPT_LSB WLAN_GPIO_STATUS_INTERRUPT_LSB +#define GPIO_STATUS_INTERRUPT_MASK WLAN_GPIO_STATUS_INTERRUPT_MASK +#define GPIO_STATUS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_INTERRUPT_GET(x) +#define GPIO_STATUS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_INTERRUPT_SET(x) +#define GPIO_STATUS_W1TS_ADDRESS WLAN_GPIO_STATUS_W1TS_ADDRESS +#define GPIO_STATUS_W1TS_OFFSET WLAN_GPIO_STATUS_W1TS_OFFSET +#define GPIO_STATUS_W1TS_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB +#define GPIO_STATUS_W1TS_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB +#define GPIO_STATUS_W1TS_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK +#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x) +#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x) +#define GPIO_STATUS_W1TC_ADDRESS WLAN_GPIO_STATUS_W1TC_ADDRESS +#define GPIO_STATUS_W1TC_OFFSET WLAN_GPIO_STATUS_W1TC_OFFSET +#define GPIO_STATUS_W1TC_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB +#define GPIO_STATUS_W1TC_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB +#define GPIO_STATUS_W1TC_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK +#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x) +#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x) +#define GPIO_PIN0_ADDRESS WLAN_GPIO_PIN0_ADDRESS +#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_OFFSET +#define GPIO_PIN0_CONFIG_MSB WLAN_GPIO_PIN0_CONFIG_MSB +#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB +#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK +#define GPIO_PIN0_CONFIG_GET(x) WLAN_GPIO_PIN0_CONFIG_GET(x) +#define GPIO_PIN0_CONFIG_SET(x) WLAN_GPIO_PIN0_CONFIG_SET(x) +#define GPIO_PIN0_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB +#define GPIO_PIN0_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB +#define GPIO_PIN0_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK +#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN0_INT_TYPE_MSB WLAN_GPIO_PIN0_INT_TYPE_MSB +#define GPIO_PIN0_INT_TYPE_LSB WLAN_GPIO_PIN0_INT_TYPE_LSB +#define GPIO_PIN0_INT_TYPE_MASK WLAN_GPIO_PIN0_INT_TYPE_MASK +#define GPIO_PIN0_INT_TYPE_GET(x) WLAN_GPIO_PIN0_INT_TYPE_GET(x) +#define GPIO_PIN0_INT_TYPE_SET(x) WLAN_GPIO_PIN0_INT_TYPE_SET(x) +#define GPIO_PIN0_PAD_PULL_MSB WLAN_GPIO_PIN0_PAD_PULL_MSB +#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB +#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK +#define GPIO_PIN0_PAD_PULL_GET(x) WLAN_GPIO_PIN0_PAD_PULL_GET(x) +#define GPIO_PIN0_PAD_PULL_SET(x) WLAN_GPIO_PIN0_PAD_PULL_SET(x) +#define GPIO_PIN0_PAD_STRENGTH_MSB WLAN_GPIO_PIN0_PAD_STRENGTH_MSB +#define GPIO_PIN0_PAD_STRENGTH_LSB WLAN_GPIO_PIN0_PAD_STRENGTH_LSB +#define GPIO_PIN0_PAD_STRENGTH_MASK WLAN_GPIO_PIN0_PAD_STRENGTH_MASK +#define GPIO_PIN0_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x) +#define GPIO_PIN0_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x) +#define GPIO_PIN0_PAD_DRIVER_MSB WLAN_GPIO_PIN0_PAD_DRIVER_MSB +#define GPIO_PIN0_PAD_DRIVER_LSB WLAN_GPIO_PIN0_PAD_DRIVER_LSB +#define GPIO_PIN0_PAD_DRIVER_MASK WLAN_GPIO_PIN0_PAD_DRIVER_MASK +#define GPIO_PIN0_PAD_DRIVER_GET(x) WLAN_GPIO_PIN0_PAD_DRIVER_GET(x) +#define GPIO_PIN0_PAD_DRIVER_SET(x) WLAN_GPIO_PIN0_PAD_DRIVER_SET(x) +#define GPIO_PIN0_SOURCE_MSB WLAN_GPIO_PIN0_SOURCE_MSB +#define GPIO_PIN0_SOURCE_LSB WLAN_GPIO_PIN0_SOURCE_LSB +#define GPIO_PIN0_SOURCE_MASK WLAN_GPIO_PIN0_SOURCE_MASK +#define GPIO_PIN0_SOURCE_GET(x) WLAN_GPIO_PIN0_SOURCE_GET(x) +#define GPIO_PIN0_SOURCE_SET(x) WLAN_GPIO_PIN0_SOURCE_SET(x) +#define GPIO_PIN1_ADDRESS WLAN_GPIO_PIN1_ADDRESS +#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_OFFSET +#define GPIO_PIN1_CONFIG_MSB WLAN_GPIO_PIN1_CONFIG_MSB +#define GPIO_PIN1_CONFIG_LSB WLAN_GPIO_PIN1_CONFIG_LSB +#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK +#define GPIO_PIN1_CONFIG_GET(x) WLAN_GPIO_PIN1_CONFIG_GET(x) +#define GPIO_PIN1_CONFIG_SET(x) WLAN_GPIO_PIN1_CONFIG_SET(x) +#define GPIO_PIN1_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB +#define GPIO_PIN1_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB +#define GPIO_PIN1_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK +#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN1_INT_TYPE_MSB WLAN_GPIO_PIN1_INT_TYPE_MSB +#define GPIO_PIN1_INT_TYPE_LSB WLAN_GPIO_PIN1_INT_TYPE_LSB +#define GPIO_PIN1_INT_TYPE_MASK WLAN_GPIO_PIN1_INT_TYPE_MASK +#define GPIO_PIN1_INT_TYPE_GET(x) WLAN_GPIO_PIN1_INT_TYPE_GET(x) +#define GPIO_PIN1_INT_TYPE_SET(x) WLAN_GPIO_PIN1_INT_TYPE_SET(x) +#define GPIO_PIN1_PAD_PULL_MSB WLAN_GPIO_PIN1_PAD_PULL_MSB +#define GPIO_PIN1_PAD_PULL_LSB WLAN_GPIO_PIN1_PAD_PULL_LSB +#define GPIO_PIN1_PAD_PULL_MASK WLAN_GPIO_PIN1_PAD_PULL_MASK +#define GPIO_PIN1_PAD_PULL_GET(x) WLAN_GPIO_PIN1_PAD_PULL_GET(x) +#define GPIO_PIN1_PAD_PULL_SET(x) WLAN_GPIO_PIN1_PAD_PULL_SET(x) +#define GPIO_PIN1_PAD_STRENGTH_MSB WLAN_GPIO_PIN1_PAD_STRENGTH_MSB +#define GPIO_PIN1_PAD_STRENGTH_LSB WLAN_GPIO_PIN1_PAD_STRENGTH_LSB +#define GPIO_PIN1_PAD_STRENGTH_MASK WLAN_GPIO_PIN1_PAD_STRENGTH_MASK +#define GPIO_PIN1_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x) +#define GPIO_PIN1_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x) +#define GPIO_PIN1_PAD_DRIVER_MSB WLAN_GPIO_PIN1_PAD_DRIVER_MSB +#define GPIO_PIN1_PAD_DRIVER_LSB WLAN_GPIO_PIN1_PAD_DRIVER_LSB +#define GPIO_PIN1_PAD_DRIVER_MASK WLAN_GPIO_PIN1_PAD_DRIVER_MASK +#define GPIO_PIN1_PAD_DRIVER_GET(x) WLAN_GPIO_PIN1_PAD_DRIVER_GET(x) +#define GPIO_PIN1_PAD_DRIVER_SET(x) WLAN_GPIO_PIN1_PAD_DRIVER_SET(x) +#define GPIO_PIN1_SOURCE_MSB WLAN_GPIO_PIN1_SOURCE_MSB +#define GPIO_PIN1_SOURCE_LSB WLAN_GPIO_PIN1_SOURCE_LSB +#define GPIO_PIN1_SOURCE_MASK WLAN_GPIO_PIN1_SOURCE_MASK +#define GPIO_PIN1_SOURCE_GET(x) WLAN_GPIO_PIN1_SOURCE_GET(x) +#define GPIO_PIN1_SOURCE_SET(x) WLAN_GPIO_PIN1_SOURCE_SET(x) +#define GPIO_PIN2_ADDRESS WLAN_GPIO_PIN2_ADDRESS +#define GPIO_PIN2_OFFSET WLAN_GPIO_PIN2_OFFSET +#define GPIO_PIN2_CONFIG_MSB WLAN_GPIO_PIN2_CONFIG_MSB +#define GPIO_PIN2_CONFIG_LSB WLAN_GPIO_PIN2_CONFIG_LSB +#define GPIO_PIN2_CONFIG_MASK WLAN_GPIO_PIN2_CONFIG_MASK +#define GPIO_PIN2_CONFIG_GET(x) WLAN_GPIO_PIN2_CONFIG_GET(x) +#define GPIO_PIN2_CONFIG_SET(x) WLAN_GPIO_PIN2_CONFIG_SET(x) +#define GPIO_PIN2_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB +#define GPIO_PIN2_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB +#define GPIO_PIN2_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK +#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN2_INT_TYPE_MSB WLAN_GPIO_PIN2_INT_TYPE_MSB +#define GPIO_PIN2_INT_TYPE_LSB WLAN_GPIO_PIN2_INT_TYPE_LSB +#define GPIO_PIN2_INT_TYPE_MASK WLAN_GPIO_PIN2_INT_TYPE_MASK +#define GPIO_PIN2_INT_TYPE_GET(x) WLAN_GPIO_PIN2_INT_TYPE_GET(x) +#define GPIO_PIN2_INT_TYPE_SET(x) WLAN_GPIO_PIN2_INT_TYPE_SET(x) +#define GPIO_PIN2_PAD_PULL_MSB WLAN_GPIO_PIN2_PAD_PULL_MSB +#define GPIO_PIN2_PAD_PULL_LSB WLAN_GPIO_PIN2_PAD_PULL_LSB +#define GPIO_PIN2_PAD_PULL_MASK WLAN_GPIO_PIN2_PAD_PULL_MASK +#define GPIO_PIN2_PAD_PULL_GET(x) WLAN_GPIO_PIN2_PAD_PULL_GET(x) +#define GPIO_PIN2_PAD_PULL_SET(x) WLAN_GPIO_PIN2_PAD_PULL_SET(x) +#define GPIO_PIN2_PAD_STRENGTH_MSB WLAN_GPIO_PIN2_PAD_STRENGTH_MSB +#define GPIO_PIN2_PAD_STRENGTH_LSB WLAN_GPIO_PIN2_PAD_STRENGTH_LSB +#define GPIO_PIN2_PAD_STRENGTH_MASK WLAN_GPIO_PIN2_PAD_STRENGTH_MASK +#define GPIO_PIN2_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x) +#define GPIO_PIN2_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x) +#define GPIO_PIN2_PAD_DRIVER_MSB WLAN_GPIO_PIN2_PAD_DRIVER_MSB +#define GPIO_PIN2_PAD_DRIVER_LSB WLAN_GPIO_PIN2_PAD_DRIVER_LSB +#define GPIO_PIN2_PAD_DRIVER_MASK WLAN_GPIO_PIN2_PAD_DRIVER_MASK +#define GPIO_PIN2_PAD_DRIVER_GET(x) WLAN_GPIO_PIN2_PAD_DRIVER_GET(x) +#define GPIO_PIN2_PAD_DRIVER_SET(x) WLAN_GPIO_PIN2_PAD_DRIVER_SET(x) +#define GPIO_PIN2_SOURCE_MSB WLAN_GPIO_PIN2_SOURCE_MSB +#define GPIO_PIN2_SOURCE_LSB WLAN_GPIO_PIN2_SOURCE_LSB +#define GPIO_PIN2_SOURCE_MASK WLAN_GPIO_PIN2_SOURCE_MASK +#define GPIO_PIN2_SOURCE_GET(x) WLAN_GPIO_PIN2_SOURCE_GET(x) +#define GPIO_PIN2_SOURCE_SET(x) WLAN_GPIO_PIN2_SOURCE_SET(x) +#define GPIO_PIN3_ADDRESS WLAN_GPIO_PIN3_ADDRESS +#define GPIO_PIN3_OFFSET WLAN_GPIO_PIN3_OFFSET +#define GPIO_PIN3_CONFIG_MSB WLAN_GPIO_PIN3_CONFIG_MSB +#define GPIO_PIN3_CONFIG_LSB WLAN_GPIO_PIN3_CONFIG_LSB +#define GPIO_PIN3_CONFIG_MASK WLAN_GPIO_PIN3_CONFIG_MASK +#define GPIO_PIN3_CONFIG_GET(x) WLAN_GPIO_PIN3_CONFIG_GET(x) +#define GPIO_PIN3_CONFIG_SET(x) WLAN_GPIO_PIN3_CONFIG_SET(x) +#define GPIO_PIN3_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB +#define GPIO_PIN3_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB +#define GPIO_PIN3_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK +#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN3_INT_TYPE_MSB WLAN_GPIO_PIN3_INT_TYPE_MSB +#define GPIO_PIN3_INT_TYPE_LSB WLAN_GPIO_PIN3_INT_TYPE_LSB +#define GPIO_PIN3_INT_TYPE_MASK WLAN_GPIO_PIN3_INT_TYPE_MASK +#define GPIO_PIN3_INT_TYPE_GET(x) WLAN_GPIO_PIN3_INT_TYPE_GET(x) +#define GPIO_PIN3_INT_TYPE_SET(x) WLAN_GPIO_PIN3_INT_TYPE_SET(x) +#define GPIO_PIN3_PAD_PULL_MSB WLAN_GPIO_PIN3_PAD_PULL_MSB +#define GPIO_PIN3_PAD_PULL_LSB WLAN_GPIO_PIN3_PAD_PULL_LSB +#define GPIO_PIN3_PAD_PULL_MASK WLAN_GPIO_PIN3_PAD_PULL_MASK +#define GPIO_PIN3_PAD_PULL_GET(x) WLAN_GPIO_PIN3_PAD_PULL_GET(x) +#define GPIO_PIN3_PAD_PULL_SET(x) WLAN_GPIO_PIN3_PAD_PULL_SET(x) +#define GPIO_PIN3_PAD_STRENGTH_MSB WLAN_GPIO_PIN3_PAD_STRENGTH_MSB +#define GPIO_PIN3_PAD_STRENGTH_LSB WLAN_GPIO_PIN3_PAD_STRENGTH_LSB +#define GPIO_PIN3_PAD_STRENGTH_MASK WLAN_GPIO_PIN3_PAD_STRENGTH_MASK +#define GPIO_PIN3_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x) +#define GPIO_PIN3_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x) +#define GPIO_PIN3_PAD_DRIVER_MSB WLAN_GPIO_PIN3_PAD_DRIVER_MSB +#define GPIO_PIN3_PAD_DRIVER_LSB WLAN_GPIO_PIN3_PAD_DRIVER_LSB +#define GPIO_PIN3_PAD_DRIVER_MASK WLAN_GPIO_PIN3_PAD_DRIVER_MASK +#define GPIO_PIN3_PAD_DRIVER_GET(x) WLAN_GPIO_PIN3_PAD_DRIVER_GET(x) +#define GPIO_PIN3_PAD_DRIVER_SET(x) WLAN_GPIO_PIN3_PAD_DRIVER_SET(x) +#define GPIO_PIN3_SOURCE_MSB WLAN_GPIO_PIN3_SOURCE_MSB +#define GPIO_PIN3_SOURCE_LSB WLAN_GPIO_PIN3_SOURCE_LSB +#define GPIO_PIN3_SOURCE_MASK WLAN_GPIO_PIN3_SOURCE_MASK +#define GPIO_PIN3_SOURCE_GET(x) WLAN_GPIO_PIN3_SOURCE_GET(x) +#define GPIO_PIN3_SOURCE_SET(x) WLAN_GPIO_PIN3_SOURCE_SET(x) +#define GPIO_PIN4_ADDRESS WLAN_GPIO_PIN4_ADDRESS +#define GPIO_PIN4_OFFSET WLAN_GPIO_PIN4_OFFSET +#define GPIO_PIN4_CONFIG_MSB WLAN_GPIO_PIN4_CONFIG_MSB +#define GPIO_PIN4_CONFIG_LSB WLAN_GPIO_PIN4_CONFIG_LSB +#define GPIO_PIN4_CONFIG_MASK WLAN_GPIO_PIN4_CONFIG_MASK +#define GPIO_PIN4_CONFIG_GET(x) WLAN_GPIO_PIN4_CONFIG_GET(x) +#define GPIO_PIN4_CONFIG_SET(x) WLAN_GPIO_PIN4_CONFIG_SET(x) +#define GPIO_PIN4_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB +#define GPIO_PIN4_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB +#define GPIO_PIN4_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK +#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN4_INT_TYPE_MSB WLAN_GPIO_PIN4_INT_TYPE_MSB +#define GPIO_PIN4_INT_TYPE_LSB WLAN_GPIO_PIN4_INT_TYPE_LSB +#define GPIO_PIN4_INT_TYPE_MASK WLAN_GPIO_PIN4_INT_TYPE_MASK +#define GPIO_PIN4_INT_TYPE_GET(x) WLAN_GPIO_PIN4_INT_TYPE_GET(x) +#define GPIO_PIN4_INT_TYPE_SET(x) WLAN_GPIO_PIN4_INT_TYPE_SET(x) +#define GPIO_PIN4_PAD_PULL_MSB WLAN_GPIO_PIN4_PAD_PULL_MSB +#define GPIO_PIN4_PAD_PULL_LSB WLAN_GPIO_PIN4_PAD_PULL_LSB +#define GPIO_PIN4_PAD_PULL_MASK WLAN_GPIO_PIN4_PAD_PULL_MASK +#define GPIO_PIN4_PAD_PULL_GET(x) WLAN_GPIO_PIN4_PAD_PULL_GET(x) +#define GPIO_PIN4_PAD_PULL_SET(x) WLAN_GPIO_PIN4_PAD_PULL_SET(x) +#define GPIO_PIN4_PAD_STRENGTH_MSB WLAN_GPIO_PIN4_PAD_STRENGTH_MSB +#define GPIO_PIN4_PAD_STRENGTH_LSB WLAN_GPIO_PIN4_PAD_STRENGTH_LSB +#define GPIO_PIN4_PAD_STRENGTH_MASK WLAN_GPIO_PIN4_PAD_STRENGTH_MASK +#define GPIO_PIN4_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x) +#define GPIO_PIN4_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x) +#define GPIO_PIN4_PAD_DRIVER_MSB WLAN_GPIO_PIN4_PAD_DRIVER_MSB +#define GPIO_PIN4_PAD_DRIVER_LSB WLAN_GPIO_PIN4_PAD_DRIVER_LSB +#define GPIO_PIN4_PAD_DRIVER_MASK WLAN_GPIO_PIN4_PAD_DRIVER_MASK +#define GPIO_PIN4_PAD_DRIVER_GET(x) WLAN_GPIO_PIN4_PAD_DRIVER_GET(x) +#define GPIO_PIN4_PAD_DRIVER_SET(x) WLAN_GPIO_PIN4_PAD_DRIVER_SET(x) +#define GPIO_PIN4_SOURCE_MSB WLAN_GPIO_PIN4_SOURCE_MSB +#define GPIO_PIN4_SOURCE_LSB WLAN_GPIO_PIN4_SOURCE_LSB +#define GPIO_PIN4_SOURCE_MASK WLAN_GPIO_PIN4_SOURCE_MASK +#define GPIO_PIN4_SOURCE_GET(x) WLAN_GPIO_PIN4_SOURCE_GET(x) +#define GPIO_PIN4_SOURCE_SET(x) WLAN_GPIO_PIN4_SOURCE_SET(x) +#define GPIO_PIN5_ADDRESS WLAN_GPIO_PIN5_ADDRESS +#define GPIO_PIN5_OFFSET WLAN_GPIO_PIN5_OFFSET +#define GPIO_PIN5_CONFIG_MSB WLAN_GPIO_PIN5_CONFIG_MSB +#define GPIO_PIN5_CONFIG_LSB WLAN_GPIO_PIN5_CONFIG_LSB +#define GPIO_PIN5_CONFIG_MASK WLAN_GPIO_PIN5_CONFIG_MASK +#define GPIO_PIN5_CONFIG_GET(x) WLAN_GPIO_PIN5_CONFIG_GET(x) +#define GPIO_PIN5_CONFIG_SET(x) WLAN_GPIO_PIN5_CONFIG_SET(x) +#define GPIO_PIN5_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB +#define GPIO_PIN5_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB +#define GPIO_PIN5_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK +#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN5_INT_TYPE_MSB WLAN_GPIO_PIN5_INT_TYPE_MSB +#define GPIO_PIN5_INT_TYPE_LSB WLAN_GPIO_PIN5_INT_TYPE_LSB +#define GPIO_PIN5_INT_TYPE_MASK WLAN_GPIO_PIN5_INT_TYPE_MASK +#define GPIO_PIN5_INT_TYPE_GET(x) WLAN_GPIO_PIN5_INT_TYPE_GET(x) +#define GPIO_PIN5_INT_TYPE_SET(x) WLAN_GPIO_PIN5_INT_TYPE_SET(x) +#define GPIO_PIN5_PAD_PULL_MSB WLAN_GPIO_PIN5_PAD_PULL_MSB +#define GPIO_PIN5_PAD_PULL_LSB WLAN_GPIO_PIN5_PAD_PULL_LSB +#define GPIO_PIN5_PAD_PULL_MASK WLAN_GPIO_PIN5_PAD_PULL_MASK +#define GPIO_PIN5_PAD_PULL_GET(x) WLAN_GPIO_PIN5_PAD_PULL_GET(x) +#define GPIO_PIN5_PAD_PULL_SET(x) WLAN_GPIO_PIN5_PAD_PULL_SET(x) +#define GPIO_PIN5_PAD_STRENGTH_MSB WLAN_GPIO_PIN5_PAD_STRENGTH_MSB +#define GPIO_PIN5_PAD_STRENGTH_LSB WLAN_GPIO_PIN5_PAD_STRENGTH_LSB +#define GPIO_PIN5_PAD_STRENGTH_MASK WLAN_GPIO_PIN5_PAD_STRENGTH_MASK +#define GPIO_PIN5_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x) +#define GPIO_PIN5_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x) +#define GPIO_PIN5_PAD_DRIVER_MSB WLAN_GPIO_PIN5_PAD_DRIVER_MSB +#define GPIO_PIN5_PAD_DRIVER_LSB WLAN_GPIO_PIN5_PAD_DRIVER_LSB +#define GPIO_PIN5_PAD_DRIVER_MASK WLAN_GPIO_PIN5_PAD_DRIVER_MASK +#define GPIO_PIN5_PAD_DRIVER_GET(x) WLAN_GPIO_PIN5_PAD_DRIVER_GET(x) +#define GPIO_PIN5_PAD_DRIVER_SET(x) WLAN_GPIO_PIN5_PAD_DRIVER_SET(x) +#define GPIO_PIN5_SOURCE_MSB WLAN_GPIO_PIN5_SOURCE_MSB +#define GPIO_PIN5_SOURCE_LSB WLAN_GPIO_PIN5_SOURCE_LSB +#define GPIO_PIN5_SOURCE_MASK WLAN_GPIO_PIN5_SOURCE_MASK +#define GPIO_PIN5_SOURCE_GET(x) WLAN_GPIO_PIN5_SOURCE_GET(x) +#define GPIO_PIN5_SOURCE_SET(x) WLAN_GPIO_PIN5_SOURCE_SET(x) +#define GPIO_PIN6_ADDRESS WLAN_GPIO_PIN6_ADDRESS +#define GPIO_PIN6_OFFSET WLAN_GPIO_PIN6_OFFSET +#define GPIO_PIN6_CONFIG_MSB WLAN_GPIO_PIN6_CONFIG_MSB +#define GPIO_PIN6_CONFIG_LSB WLAN_GPIO_PIN6_CONFIG_LSB +#define GPIO_PIN6_CONFIG_MASK WLAN_GPIO_PIN6_CONFIG_MASK +#define GPIO_PIN6_CONFIG_GET(x) WLAN_GPIO_PIN6_CONFIG_GET(x) +#define GPIO_PIN6_CONFIG_SET(x) WLAN_GPIO_PIN6_CONFIG_SET(x) +#define GPIO_PIN6_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB +#define GPIO_PIN6_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB +#define GPIO_PIN6_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK +#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN6_INT_TYPE_MSB WLAN_GPIO_PIN6_INT_TYPE_MSB +#define GPIO_PIN6_INT_TYPE_LSB WLAN_GPIO_PIN6_INT_TYPE_LSB +#define GPIO_PIN6_INT_TYPE_MASK WLAN_GPIO_PIN6_INT_TYPE_MASK +#define GPIO_PIN6_INT_TYPE_GET(x) WLAN_GPIO_PIN6_INT_TYPE_GET(x) +#define GPIO_PIN6_INT_TYPE_SET(x) WLAN_GPIO_PIN6_INT_TYPE_SET(x) +#define GPIO_PIN6_PAD_PULL_MSB WLAN_GPIO_PIN6_PAD_PULL_MSB +#define GPIO_PIN6_PAD_PULL_LSB WLAN_GPIO_PIN6_PAD_PULL_LSB +#define GPIO_PIN6_PAD_PULL_MASK WLAN_GPIO_PIN6_PAD_PULL_MASK +#define GPIO_PIN6_PAD_PULL_GET(x) WLAN_GPIO_PIN6_PAD_PULL_GET(x) +#define GPIO_PIN6_PAD_PULL_SET(x) WLAN_GPIO_PIN6_PAD_PULL_SET(x) +#define GPIO_PIN6_PAD_STRENGTH_MSB WLAN_GPIO_PIN6_PAD_STRENGTH_MSB +#define GPIO_PIN6_PAD_STRENGTH_LSB WLAN_GPIO_PIN6_PAD_STRENGTH_LSB +#define GPIO_PIN6_PAD_STRENGTH_MASK WLAN_GPIO_PIN6_PAD_STRENGTH_MASK +#define GPIO_PIN6_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x) +#define GPIO_PIN6_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x) +#define GPIO_PIN6_PAD_DRIVER_MSB WLAN_GPIO_PIN6_PAD_DRIVER_MSB +#define GPIO_PIN6_PAD_DRIVER_LSB WLAN_GPIO_PIN6_PAD_DRIVER_LSB +#define GPIO_PIN6_PAD_DRIVER_MASK WLAN_GPIO_PIN6_PAD_DRIVER_MASK +#define GPIO_PIN6_PAD_DRIVER_GET(x) WLAN_GPIO_PIN6_PAD_DRIVER_GET(x) +#define GPIO_PIN6_PAD_DRIVER_SET(x) WLAN_GPIO_PIN6_PAD_DRIVER_SET(x) +#define GPIO_PIN6_SOURCE_MSB WLAN_GPIO_PIN6_SOURCE_MSB +#define GPIO_PIN6_SOURCE_LSB WLAN_GPIO_PIN6_SOURCE_LSB +#define GPIO_PIN6_SOURCE_MASK WLAN_GPIO_PIN6_SOURCE_MASK +#define GPIO_PIN6_SOURCE_GET(x) WLAN_GPIO_PIN6_SOURCE_GET(x) +#define GPIO_PIN6_SOURCE_SET(x) WLAN_GPIO_PIN6_SOURCE_SET(x) +#define GPIO_PIN7_ADDRESS WLAN_GPIO_PIN7_ADDRESS +#define GPIO_PIN7_OFFSET WLAN_GPIO_PIN7_OFFSET +#define GPIO_PIN7_CONFIG_MSB WLAN_GPIO_PIN7_CONFIG_MSB +#define GPIO_PIN7_CONFIG_LSB WLAN_GPIO_PIN7_CONFIG_LSB +#define GPIO_PIN7_CONFIG_MASK WLAN_GPIO_PIN7_CONFIG_MASK +#define GPIO_PIN7_CONFIG_GET(x) WLAN_GPIO_PIN7_CONFIG_GET(x) +#define GPIO_PIN7_CONFIG_SET(x) WLAN_GPIO_PIN7_CONFIG_SET(x) +#define GPIO_PIN7_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB +#define GPIO_PIN7_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB +#define GPIO_PIN7_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK +#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN7_INT_TYPE_MSB WLAN_GPIO_PIN7_INT_TYPE_MSB +#define GPIO_PIN7_INT_TYPE_LSB WLAN_GPIO_PIN7_INT_TYPE_LSB +#define GPIO_PIN7_INT_TYPE_MASK WLAN_GPIO_PIN7_INT_TYPE_MASK +#define GPIO_PIN7_INT_TYPE_GET(x) WLAN_GPIO_PIN7_INT_TYPE_GET(x) +#define GPIO_PIN7_INT_TYPE_SET(x) WLAN_GPIO_PIN7_INT_TYPE_SET(x) +#define GPIO_PIN7_PAD_PULL_MSB WLAN_GPIO_PIN7_PAD_PULL_MSB +#define GPIO_PIN7_PAD_PULL_LSB WLAN_GPIO_PIN7_PAD_PULL_LSB +#define GPIO_PIN7_PAD_PULL_MASK WLAN_GPIO_PIN7_PAD_PULL_MASK +#define GPIO_PIN7_PAD_PULL_GET(x) WLAN_GPIO_PIN7_PAD_PULL_GET(x) +#define GPIO_PIN7_PAD_PULL_SET(x) WLAN_GPIO_PIN7_PAD_PULL_SET(x) +#define GPIO_PIN7_PAD_STRENGTH_MSB WLAN_GPIO_PIN7_PAD_STRENGTH_MSB +#define GPIO_PIN7_PAD_STRENGTH_LSB WLAN_GPIO_PIN7_PAD_STRENGTH_LSB +#define GPIO_PIN7_PAD_STRENGTH_MASK WLAN_GPIO_PIN7_PAD_STRENGTH_MASK +#define GPIO_PIN7_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x) +#define GPIO_PIN7_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x) +#define GPIO_PIN7_PAD_DRIVER_MSB WLAN_GPIO_PIN7_PAD_DRIVER_MSB +#define GPIO_PIN7_PAD_DRIVER_LSB WLAN_GPIO_PIN7_PAD_DRIVER_LSB +#define GPIO_PIN7_PAD_DRIVER_MASK WLAN_GPIO_PIN7_PAD_DRIVER_MASK +#define GPIO_PIN7_PAD_DRIVER_GET(x) WLAN_GPIO_PIN7_PAD_DRIVER_GET(x) +#define GPIO_PIN7_PAD_DRIVER_SET(x) WLAN_GPIO_PIN7_PAD_DRIVER_SET(x) +#define GPIO_PIN7_SOURCE_MSB WLAN_GPIO_PIN7_SOURCE_MSB +#define GPIO_PIN7_SOURCE_LSB WLAN_GPIO_PIN7_SOURCE_LSB +#define GPIO_PIN7_SOURCE_MASK WLAN_GPIO_PIN7_SOURCE_MASK +#define GPIO_PIN7_SOURCE_GET(x) WLAN_GPIO_PIN7_SOURCE_GET(x) +#define GPIO_PIN7_SOURCE_SET(x) WLAN_GPIO_PIN7_SOURCE_SET(x) +#define GPIO_PIN8_ADDRESS WLAN_GPIO_PIN8_ADDRESS +#define GPIO_PIN8_OFFSET WLAN_GPIO_PIN8_OFFSET +#define GPIO_PIN8_CONFIG_MSB WLAN_GPIO_PIN8_CONFIG_MSB +#define GPIO_PIN8_CONFIG_LSB WLAN_GPIO_PIN8_CONFIG_LSB +#define GPIO_PIN8_CONFIG_MASK WLAN_GPIO_PIN8_CONFIG_MASK +#define GPIO_PIN8_CONFIG_GET(x) WLAN_GPIO_PIN8_CONFIG_GET(x) +#define GPIO_PIN8_CONFIG_SET(x) WLAN_GPIO_PIN8_CONFIG_SET(x) +#define GPIO_PIN8_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB +#define GPIO_PIN8_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB +#define GPIO_PIN8_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK +#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN8_INT_TYPE_MSB WLAN_GPIO_PIN8_INT_TYPE_MSB +#define GPIO_PIN8_INT_TYPE_LSB WLAN_GPIO_PIN8_INT_TYPE_LSB +#define GPIO_PIN8_INT_TYPE_MASK WLAN_GPIO_PIN8_INT_TYPE_MASK +#define GPIO_PIN8_INT_TYPE_GET(x) WLAN_GPIO_PIN8_INT_TYPE_GET(x) +#define GPIO_PIN8_INT_TYPE_SET(x) WLAN_GPIO_PIN8_INT_TYPE_SET(x) +#define GPIO_PIN8_PAD_PULL_MSB WLAN_GPIO_PIN8_PAD_PULL_MSB +#define GPIO_PIN8_PAD_PULL_LSB WLAN_GPIO_PIN8_PAD_PULL_LSB +#define GPIO_PIN8_PAD_PULL_MASK WLAN_GPIO_PIN8_PAD_PULL_MASK +#define GPIO_PIN8_PAD_PULL_GET(x) WLAN_GPIO_PIN8_PAD_PULL_GET(x) +#define GPIO_PIN8_PAD_PULL_SET(x) WLAN_GPIO_PIN8_PAD_PULL_SET(x) +#define GPIO_PIN8_PAD_STRENGTH_MSB WLAN_GPIO_PIN8_PAD_STRENGTH_MSB +#define GPIO_PIN8_PAD_STRENGTH_LSB WLAN_GPIO_PIN8_PAD_STRENGTH_LSB +#define GPIO_PIN8_PAD_STRENGTH_MASK WLAN_GPIO_PIN8_PAD_STRENGTH_MASK +#define GPIO_PIN8_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x) +#define GPIO_PIN8_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x) +#define GPIO_PIN8_PAD_DRIVER_MSB WLAN_GPIO_PIN8_PAD_DRIVER_MSB +#define GPIO_PIN8_PAD_DRIVER_LSB WLAN_GPIO_PIN8_PAD_DRIVER_LSB +#define GPIO_PIN8_PAD_DRIVER_MASK WLAN_GPIO_PIN8_PAD_DRIVER_MASK +#define GPIO_PIN8_PAD_DRIVER_GET(x) WLAN_GPIO_PIN8_PAD_DRIVER_GET(x) +#define GPIO_PIN8_PAD_DRIVER_SET(x) WLAN_GPIO_PIN8_PAD_DRIVER_SET(x) +#define GPIO_PIN8_SOURCE_MSB WLAN_GPIO_PIN8_SOURCE_MSB +#define GPIO_PIN8_SOURCE_LSB WLAN_GPIO_PIN8_SOURCE_LSB +#define GPIO_PIN8_SOURCE_MASK WLAN_GPIO_PIN8_SOURCE_MASK +#define GPIO_PIN8_SOURCE_GET(x) WLAN_GPIO_PIN8_SOURCE_GET(x) +#define GPIO_PIN8_SOURCE_SET(x) WLAN_GPIO_PIN8_SOURCE_SET(x) +#define GPIO_PIN9_ADDRESS WLAN_GPIO_PIN9_ADDRESS +#define GPIO_PIN9_OFFSET WLAN_GPIO_PIN9_OFFSET +#define GPIO_PIN9_CONFIG_MSB WLAN_GPIO_PIN9_CONFIG_MSB +#define GPIO_PIN9_CONFIG_LSB WLAN_GPIO_PIN9_CONFIG_LSB +#define GPIO_PIN9_CONFIG_MASK WLAN_GPIO_PIN9_CONFIG_MASK +#define GPIO_PIN9_CONFIG_GET(x) WLAN_GPIO_PIN9_CONFIG_GET(x) +#define GPIO_PIN9_CONFIG_SET(x) WLAN_GPIO_PIN9_CONFIG_SET(x) +#define GPIO_PIN9_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB +#define GPIO_PIN9_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB +#define GPIO_PIN9_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK +#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN9_INT_TYPE_MSB WLAN_GPIO_PIN9_INT_TYPE_MSB +#define GPIO_PIN9_INT_TYPE_LSB WLAN_GPIO_PIN9_INT_TYPE_LSB +#define GPIO_PIN9_INT_TYPE_MASK WLAN_GPIO_PIN9_INT_TYPE_MASK +#define GPIO_PIN9_INT_TYPE_GET(x) WLAN_GPIO_PIN9_INT_TYPE_GET(x) +#define GPIO_PIN9_INT_TYPE_SET(x) WLAN_GPIO_PIN9_INT_TYPE_SET(x) +#define GPIO_PIN9_PAD_PULL_MSB WLAN_GPIO_PIN9_PAD_PULL_MSB +#define GPIO_PIN9_PAD_PULL_LSB WLAN_GPIO_PIN9_PAD_PULL_LSB +#define GPIO_PIN9_PAD_PULL_MASK WLAN_GPIO_PIN9_PAD_PULL_MASK +#define GPIO_PIN9_PAD_PULL_GET(x) WLAN_GPIO_PIN9_PAD_PULL_GET(x) +#define GPIO_PIN9_PAD_PULL_SET(x) WLAN_GPIO_PIN9_PAD_PULL_SET(x) +#define GPIO_PIN9_PAD_STRENGTH_MSB WLAN_GPIO_PIN9_PAD_STRENGTH_MSB +#define GPIO_PIN9_PAD_STRENGTH_LSB WLAN_GPIO_PIN9_PAD_STRENGTH_LSB +#define GPIO_PIN9_PAD_STRENGTH_MASK WLAN_GPIO_PIN9_PAD_STRENGTH_MASK +#define GPIO_PIN9_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x) +#define GPIO_PIN9_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x) +#define GPIO_PIN9_PAD_DRIVER_MSB WLAN_GPIO_PIN9_PAD_DRIVER_MSB +#define GPIO_PIN9_PAD_DRIVER_LSB WLAN_GPIO_PIN9_PAD_DRIVER_LSB +#define GPIO_PIN9_PAD_DRIVER_MASK WLAN_GPIO_PIN9_PAD_DRIVER_MASK +#define GPIO_PIN9_PAD_DRIVER_GET(x) WLAN_GPIO_PIN9_PAD_DRIVER_GET(x) +#define GPIO_PIN9_PAD_DRIVER_SET(x) WLAN_GPIO_PIN9_PAD_DRIVER_SET(x) +#define GPIO_PIN9_SOURCE_MSB WLAN_GPIO_PIN9_SOURCE_MSB +#define GPIO_PIN9_SOURCE_LSB WLAN_GPIO_PIN9_SOURCE_LSB +#define GPIO_PIN9_SOURCE_MASK WLAN_GPIO_PIN9_SOURCE_MASK +#define GPIO_PIN9_SOURCE_GET(x) WLAN_GPIO_PIN9_SOURCE_GET(x) +#define GPIO_PIN9_SOURCE_SET(x) WLAN_GPIO_PIN9_SOURCE_SET(x) +#define GPIO_PIN10_ADDRESS WLAN_GPIO_PIN10_ADDRESS +#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_OFFSET +#define GPIO_PIN10_CONFIG_MSB WLAN_GPIO_PIN10_CONFIG_MSB +#define GPIO_PIN10_CONFIG_LSB WLAN_GPIO_PIN10_CONFIG_LSB +#define GPIO_PIN10_CONFIG_MASK WLAN_GPIO_PIN10_CONFIG_MASK +#define GPIO_PIN10_CONFIG_GET(x) WLAN_GPIO_PIN10_CONFIG_GET(x) +#define GPIO_PIN10_CONFIG_SET(x) WLAN_GPIO_PIN10_CONFIG_SET(x) +#define GPIO_PIN10_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB +#define GPIO_PIN10_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB +#define GPIO_PIN10_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK +#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN10_INT_TYPE_MSB WLAN_GPIO_PIN10_INT_TYPE_MSB +#define GPIO_PIN10_INT_TYPE_LSB WLAN_GPIO_PIN10_INT_TYPE_LSB +#define GPIO_PIN10_INT_TYPE_MASK WLAN_GPIO_PIN10_INT_TYPE_MASK +#define GPIO_PIN10_INT_TYPE_GET(x) WLAN_GPIO_PIN10_INT_TYPE_GET(x) +#define GPIO_PIN10_INT_TYPE_SET(x) WLAN_GPIO_PIN10_INT_TYPE_SET(x) +#define GPIO_PIN10_PAD_PULL_MSB WLAN_GPIO_PIN10_PAD_PULL_MSB +#define GPIO_PIN10_PAD_PULL_LSB WLAN_GPIO_PIN10_PAD_PULL_LSB +#define GPIO_PIN10_PAD_PULL_MASK WLAN_GPIO_PIN10_PAD_PULL_MASK +#define GPIO_PIN10_PAD_PULL_GET(x) WLAN_GPIO_PIN10_PAD_PULL_GET(x) +#define GPIO_PIN10_PAD_PULL_SET(x) WLAN_GPIO_PIN10_PAD_PULL_SET(x) +#define GPIO_PIN10_PAD_STRENGTH_MSB WLAN_GPIO_PIN10_PAD_STRENGTH_MSB +#define GPIO_PIN10_PAD_STRENGTH_LSB WLAN_GPIO_PIN10_PAD_STRENGTH_LSB +#define GPIO_PIN10_PAD_STRENGTH_MASK WLAN_GPIO_PIN10_PAD_STRENGTH_MASK +#define GPIO_PIN10_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x) +#define GPIO_PIN10_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x) +#define GPIO_PIN10_PAD_DRIVER_MSB WLAN_GPIO_PIN10_PAD_DRIVER_MSB +#define GPIO_PIN10_PAD_DRIVER_LSB WLAN_GPIO_PIN10_PAD_DRIVER_LSB +#define GPIO_PIN10_PAD_DRIVER_MASK WLAN_GPIO_PIN10_PAD_DRIVER_MASK +#define GPIO_PIN10_PAD_DRIVER_GET(x) WLAN_GPIO_PIN10_PAD_DRIVER_GET(x) +#define GPIO_PIN10_PAD_DRIVER_SET(x) WLAN_GPIO_PIN10_PAD_DRIVER_SET(x) +#define GPIO_PIN10_SOURCE_MSB WLAN_GPIO_PIN10_SOURCE_MSB +#define GPIO_PIN10_SOURCE_LSB WLAN_GPIO_PIN10_SOURCE_LSB +#define GPIO_PIN10_SOURCE_MASK WLAN_GPIO_PIN10_SOURCE_MASK +#define GPIO_PIN10_SOURCE_GET(x) WLAN_GPIO_PIN10_SOURCE_GET(x) +#define GPIO_PIN10_SOURCE_SET(x) WLAN_GPIO_PIN10_SOURCE_SET(x) +#define GPIO_PIN11_ADDRESS WLAN_GPIO_PIN11_ADDRESS +#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_OFFSET +#define GPIO_PIN11_CONFIG_MSB WLAN_GPIO_PIN11_CONFIG_MSB +#define GPIO_PIN11_CONFIG_LSB WLAN_GPIO_PIN11_CONFIG_LSB +#define GPIO_PIN11_CONFIG_MASK WLAN_GPIO_PIN11_CONFIG_MASK +#define GPIO_PIN11_CONFIG_GET(x) WLAN_GPIO_PIN11_CONFIG_GET(x) +#define GPIO_PIN11_CONFIG_SET(x) WLAN_GPIO_PIN11_CONFIG_SET(x) +#define GPIO_PIN11_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB +#define GPIO_PIN11_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB +#define GPIO_PIN11_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK +#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN11_INT_TYPE_MSB WLAN_GPIO_PIN11_INT_TYPE_MSB +#define GPIO_PIN11_INT_TYPE_LSB WLAN_GPIO_PIN11_INT_TYPE_LSB +#define GPIO_PIN11_INT_TYPE_MASK WLAN_GPIO_PIN11_INT_TYPE_MASK +#define GPIO_PIN11_INT_TYPE_GET(x) WLAN_GPIO_PIN11_INT_TYPE_GET(x) +#define GPIO_PIN11_INT_TYPE_SET(x) WLAN_GPIO_PIN11_INT_TYPE_SET(x) +#define GPIO_PIN11_PAD_PULL_MSB WLAN_GPIO_PIN11_PAD_PULL_MSB +#define GPIO_PIN11_PAD_PULL_LSB WLAN_GPIO_PIN11_PAD_PULL_LSB +#define GPIO_PIN11_PAD_PULL_MASK WLAN_GPIO_PIN11_PAD_PULL_MASK +#define GPIO_PIN11_PAD_PULL_GET(x) WLAN_GPIO_PIN11_PAD_PULL_GET(x) +#define GPIO_PIN11_PAD_PULL_SET(x) WLAN_GPIO_PIN11_PAD_PULL_SET(x) +#define GPIO_PIN11_PAD_STRENGTH_MSB WLAN_GPIO_PIN11_PAD_STRENGTH_MSB +#define GPIO_PIN11_PAD_STRENGTH_LSB WLAN_GPIO_PIN11_PAD_STRENGTH_LSB +#define GPIO_PIN11_PAD_STRENGTH_MASK WLAN_GPIO_PIN11_PAD_STRENGTH_MASK +#define GPIO_PIN11_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x) +#define GPIO_PIN11_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x) +#define GPIO_PIN11_PAD_DRIVER_MSB WLAN_GPIO_PIN11_PAD_DRIVER_MSB +#define GPIO_PIN11_PAD_DRIVER_LSB WLAN_GPIO_PIN11_PAD_DRIVER_LSB +#define GPIO_PIN11_PAD_DRIVER_MASK WLAN_GPIO_PIN11_PAD_DRIVER_MASK +#define GPIO_PIN11_PAD_DRIVER_GET(x) WLAN_GPIO_PIN11_PAD_DRIVER_GET(x) +#define GPIO_PIN11_PAD_DRIVER_SET(x) WLAN_GPIO_PIN11_PAD_DRIVER_SET(x) +#define GPIO_PIN11_SOURCE_MSB WLAN_GPIO_PIN11_SOURCE_MSB +#define GPIO_PIN11_SOURCE_LSB WLAN_GPIO_PIN11_SOURCE_LSB +#define GPIO_PIN11_SOURCE_MASK WLAN_GPIO_PIN11_SOURCE_MASK +#define GPIO_PIN11_SOURCE_GET(x) WLAN_GPIO_PIN11_SOURCE_GET(x) +#define GPIO_PIN11_SOURCE_SET(x) WLAN_GPIO_PIN11_SOURCE_SET(x) +#define GPIO_PIN12_ADDRESS WLAN_GPIO_PIN12_ADDRESS +#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_OFFSET +#define GPIO_PIN12_CONFIG_MSB WLAN_GPIO_PIN12_CONFIG_MSB +#define GPIO_PIN12_CONFIG_LSB WLAN_GPIO_PIN12_CONFIG_LSB +#define GPIO_PIN12_CONFIG_MASK WLAN_GPIO_PIN12_CONFIG_MASK +#define GPIO_PIN12_CONFIG_GET(x) WLAN_GPIO_PIN12_CONFIG_GET(x) +#define GPIO_PIN12_CONFIG_SET(x) WLAN_GPIO_PIN12_CONFIG_SET(x) +#define GPIO_PIN12_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB +#define GPIO_PIN12_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB +#define GPIO_PIN12_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK +#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN12_INT_TYPE_MSB WLAN_GPIO_PIN12_INT_TYPE_MSB +#define GPIO_PIN12_INT_TYPE_LSB WLAN_GPIO_PIN12_INT_TYPE_LSB +#define GPIO_PIN12_INT_TYPE_MASK WLAN_GPIO_PIN12_INT_TYPE_MASK +#define GPIO_PIN12_INT_TYPE_GET(x) WLAN_GPIO_PIN12_INT_TYPE_GET(x) +#define GPIO_PIN12_INT_TYPE_SET(x) WLAN_GPIO_PIN12_INT_TYPE_SET(x) +#define GPIO_PIN12_PAD_PULL_MSB WLAN_GPIO_PIN12_PAD_PULL_MSB +#define GPIO_PIN12_PAD_PULL_LSB WLAN_GPIO_PIN12_PAD_PULL_LSB +#define GPIO_PIN12_PAD_PULL_MASK WLAN_GPIO_PIN12_PAD_PULL_MASK +#define GPIO_PIN12_PAD_PULL_GET(x) WLAN_GPIO_PIN12_PAD_PULL_GET(x) +#define GPIO_PIN12_PAD_PULL_SET(x) WLAN_GPIO_PIN12_PAD_PULL_SET(x) +#define GPIO_PIN12_PAD_STRENGTH_MSB WLAN_GPIO_PIN12_PAD_STRENGTH_MSB +#define GPIO_PIN12_PAD_STRENGTH_LSB WLAN_GPIO_PIN12_PAD_STRENGTH_LSB +#define GPIO_PIN12_PAD_STRENGTH_MASK WLAN_GPIO_PIN12_PAD_STRENGTH_MASK +#define GPIO_PIN12_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x) +#define GPIO_PIN12_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x) +#define GPIO_PIN12_PAD_DRIVER_MSB WLAN_GPIO_PIN12_PAD_DRIVER_MSB +#define GPIO_PIN12_PAD_DRIVER_LSB WLAN_GPIO_PIN12_PAD_DRIVER_LSB +#define GPIO_PIN12_PAD_DRIVER_MASK WLAN_GPIO_PIN12_PAD_DRIVER_MASK +#define GPIO_PIN12_PAD_DRIVER_GET(x) WLAN_GPIO_PIN12_PAD_DRIVER_GET(x) +#define GPIO_PIN12_PAD_DRIVER_SET(x) WLAN_GPIO_PIN12_PAD_DRIVER_SET(x) +#define GPIO_PIN12_SOURCE_MSB WLAN_GPIO_PIN12_SOURCE_MSB +#define GPIO_PIN12_SOURCE_LSB WLAN_GPIO_PIN12_SOURCE_LSB +#define GPIO_PIN12_SOURCE_MASK WLAN_GPIO_PIN12_SOURCE_MASK +#define GPIO_PIN12_SOURCE_GET(x) WLAN_GPIO_PIN12_SOURCE_GET(x) +#define GPIO_PIN12_SOURCE_SET(x) WLAN_GPIO_PIN12_SOURCE_SET(x) +#define GPIO_PIN13_ADDRESS WLAN_GPIO_PIN13_ADDRESS +#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_OFFSET +#define GPIO_PIN13_CONFIG_MSB WLAN_GPIO_PIN13_CONFIG_MSB +#define GPIO_PIN13_CONFIG_LSB WLAN_GPIO_PIN13_CONFIG_LSB +#define GPIO_PIN13_CONFIG_MASK WLAN_GPIO_PIN13_CONFIG_MASK +#define GPIO_PIN13_CONFIG_GET(x) WLAN_GPIO_PIN13_CONFIG_GET(x) +#define GPIO_PIN13_CONFIG_SET(x) WLAN_GPIO_PIN13_CONFIG_SET(x) +#define GPIO_PIN13_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB +#define GPIO_PIN13_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB +#define GPIO_PIN13_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK +#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN13_INT_TYPE_MSB WLAN_GPIO_PIN13_INT_TYPE_MSB +#define GPIO_PIN13_INT_TYPE_LSB WLAN_GPIO_PIN13_INT_TYPE_LSB +#define GPIO_PIN13_INT_TYPE_MASK WLAN_GPIO_PIN13_INT_TYPE_MASK +#define GPIO_PIN13_INT_TYPE_GET(x) WLAN_GPIO_PIN13_INT_TYPE_GET(x) +#define GPIO_PIN13_INT_TYPE_SET(x) WLAN_GPIO_PIN13_INT_TYPE_SET(x) +#define GPIO_PIN13_PAD_PULL_MSB WLAN_GPIO_PIN13_PAD_PULL_MSB +#define GPIO_PIN13_PAD_PULL_LSB WLAN_GPIO_PIN13_PAD_PULL_LSB +#define GPIO_PIN13_PAD_PULL_MASK WLAN_GPIO_PIN13_PAD_PULL_MASK +#define GPIO_PIN13_PAD_PULL_GET(x) WLAN_GPIO_PIN13_PAD_PULL_GET(x) +#define GPIO_PIN13_PAD_PULL_SET(x) WLAN_GPIO_PIN13_PAD_PULL_SET(x) +#define GPIO_PIN13_PAD_STRENGTH_MSB WLAN_GPIO_PIN13_PAD_STRENGTH_MSB +#define GPIO_PIN13_PAD_STRENGTH_LSB WLAN_GPIO_PIN13_PAD_STRENGTH_LSB +#define GPIO_PIN13_PAD_STRENGTH_MASK WLAN_GPIO_PIN13_PAD_STRENGTH_MASK +#define GPIO_PIN13_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x) +#define GPIO_PIN13_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x) +#define GPIO_PIN13_PAD_DRIVER_MSB WLAN_GPIO_PIN13_PAD_DRIVER_MSB +#define GPIO_PIN13_PAD_DRIVER_LSB WLAN_GPIO_PIN13_PAD_DRIVER_LSB +#define GPIO_PIN13_PAD_DRIVER_MASK WLAN_GPIO_PIN13_PAD_DRIVER_MASK +#define GPIO_PIN13_PAD_DRIVER_GET(x) WLAN_GPIO_PIN13_PAD_DRIVER_GET(x) +#define GPIO_PIN13_PAD_DRIVER_SET(x) WLAN_GPIO_PIN13_PAD_DRIVER_SET(x) +#define GPIO_PIN13_SOURCE_MSB WLAN_GPIO_PIN13_SOURCE_MSB +#define GPIO_PIN13_SOURCE_LSB WLAN_GPIO_PIN13_SOURCE_LSB +#define GPIO_PIN13_SOURCE_MASK WLAN_GPIO_PIN13_SOURCE_MASK +#define GPIO_PIN13_SOURCE_GET(x) WLAN_GPIO_PIN13_SOURCE_GET(x) +#define GPIO_PIN13_SOURCE_SET(x) WLAN_GPIO_PIN13_SOURCE_SET(x) +#define GPIO_PIN14_ADDRESS WLAN_GPIO_PIN14_ADDRESS +#define GPIO_PIN14_OFFSET WLAN_GPIO_PIN14_OFFSET +#define GPIO_PIN14_CONFIG_MSB WLAN_GPIO_PIN14_CONFIG_MSB +#define GPIO_PIN14_CONFIG_LSB WLAN_GPIO_PIN14_CONFIG_LSB +#define GPIO_PIN14_CONFIG_MASK WLAN_GPIO_PIN14_CONFIG_MASK +#define GPIO_PIN14_CONFIG_GET(x) WLAN_GPIO_PIN14_CONFIG_GET(x) +#define GPIO_PIN14_CONFIG_SET(x) WLAN_GPIO_PIN14_CONFIG_SET(x) +#define GPIO_PIN14_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB +#define GPIO_PIN14_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB +#define GPIO_PIN14_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK +#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN14_INT_TYPE_MSB WLAN_GPIO_PIN14_INT_TYPE_MSB +#define GPIO_PIN14_INT_TYPE_LSB WLAN_GPIO_PIN14_INT_TYPE_LSB +#define GPIO_PIN14_INT_TYPE_MASK WLAN_GPIO_PIN14_INT_TYPE_MASK +#define GPIO_PIN14_INT_TYPE_GET(x) WLAN_GPIO_PIN14_INT_TYPE_GET(x) +#define GPIO_PIN14_INT_TYPE_SET(x) WLAN_GPIO_PIN14_INT_TYPE_SET(x) +#define GPIO_PIN14_PAD_PULL_MSB WLAN_GPIO_PIN14_PAD_PULL_MSB +#define GPIO_PIN14_PAD_PULL_LSB WLAN_GPIO_PIN14_PAD_PULL_LSB +#define GPIO_PIN14_PAD_PULL_MASK WLAN_GPIO_PIN14_PAD_PULL_MASK +#define GPIO_PIN14_PAD_PULL_GET(x) WLAN_GPIO_PIN14_PAD_PULL_GET(x) +#define GPIO_PIN14_PAD_PULL_SET(x) WLAN_GPIO_PIN14_PAD_PULL_SET(x) +#define GPIO_PIN14_PAD_STRENGTH_MSB WLAN_GPIO_PIN14_PAD_STRENGTH_MSB +#define GPIO_PIN14_PAD_STRENGTH_LSB WLAN_GPIO_PIN14_PAD_STRENGTH_LSB +#define GPIO_PIN14_PAD_STRENGTH_MASK WLAN_GPIO_PIN14_PAD_STRENGTH_MASK +#define GPIO_PIN14_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x) +#define GPIO_PIN14_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x) +#define GPIO_PIN14_PAD_DRIVER_MSB WLAN_GPIO_PIN14_PAD_DRIVER_MSB +#define GPIO_PIN14_PAD_DRIVER_LSB WLAN_GPIO_PIN14_PAD_DRIVER_LSB +#define GPIO_PIN14_PAD_DRIVER_MASK WLAN_GPIO_PIN14_PAD_DRIVER_MASK +#define GPIO_PIN14_PAD_DRIVER_GET(x) WLAN_GPIO_PIN14_PAD_DRIVER_GET(x) +#define GPIO_PIN14_PAD_DRIVER_SET(x) WLAN_GPIO_PIN14_PAD_DRIVER_SET(x) +#define GPIO_PIN14_SOURCE_MSB WLAN_GPIO_PIN14_SOURCE_MSB +#define GPIO_PIN14_SOURCE_LSB WLAN_GPIO_PIN14_SOURCE_LSB +#define GPIO_PIN14_SOURCE_MASK WLAN_GPIO_PIN14_SOURCE_MASK +#define GPIO_PIN14_SOURCE_GET(x) WLAN_GPIO_PIN14_SOURCE_GET(x) +#define GPIO_PIN14_SOURCE_SET(x) WLAN_GPIO_PIN14_SOURCE_SET(x) +#define GPIO_PIN15_ADDRESS WLAN_GPIO_PIN15_ADDRESS +#define GPIO_PIN15_OFFSET WLAN_GPIO_PIN15_OFFSET +#define GPIO_PIN15_CONFIG_MSB WLAN_GPIO_PIN15_CONFIG_MSB +#define GPIO_PIN15_CONFIG_LSB WLAN_GPIO_PIN15_CONFIG_LSB +#define GPIO_PIN15_CONFIG_MASK WLAN_GPIO_PIN15_CONFIG_MASK +#define GPIO_PIN15_CONFIG_GET(x) WLAN_GPIO_PIN15_CONFIG_GET(x) +#define GPIO_PIN15_CONFIG_SET(x) WLAN_GPIO_PIN15_CONFIG_SET(x) +#define GPIO_PIN15_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB +#define GPIO_PIN15_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB +#define GPIO_PIN15_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK +#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN15_INT_TYPE_MSB WLAN_GPIO_PIN15_INT_TYPE_MSB +#define GPIO_PIN15_INT_TYPE_LSB WLAN_GPIO_PIN15_INT_TYPE_LSB +#define GPIO_PIN15_INT_TYPE_MASK WLAN_GPIO_PIN15_INT_TYPE_MASK +#define GPIO_PIN15_INT_TYPE_GET(x) WLAN_GPIO_PIN15_INT_TYPE_GET(x) +#define GPIO_PIN15_INT_TYPE_SET(x) WLAN_GPIO_PIN15_INT_TYPE_SET(x) +#define GPIO_PIN15_PAD_PULL_MSB WLAN_GPIO_PIN15_PAD_PULL_MSB +#define GPIO_PIN15_PAD_PULL_LSB WLAN_GPIO_PIN15_PAD_PULL_LSB +#define GPIO_PIN15_PAD_PULL_MASK WLAN_GPIO_PIN15_PAD_PULL_MASK +#define GPIO_PIN15_PAD_PULL_GET(x) WLAN_GPIO_PIN15_PAD_PULL_GET(x) +#define GPIO_PIN15_PAD_PULL_SET(x) WLAN_GPIO_PIN15_PAD_PULL_SET(x) +#define GPIO_PIN15_PAD_STRENGTH_MSB WLAN_GPIO_PIN15_PAD_STRENGTH_MSB +#define GPIO_PIN15_PAD_STRENGTH_LSB WLAN_GPIO_PIN15_PAD_STRENGTH_LSB +#define GPIO_PIN15_PAD_STRENGTH_MASK WLAN_GPIO_PIN15_PAD_STRENGTH_MASK +#define GPIO_PIN15_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x) +#define GPIO_PIN15_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x) +#define GPIO_PIN15_PAD_DRIVER_MSB WLAN_GPIO_PIN15_PAD_DRIVER_MSB +#define GPIO_PIN15_PAD_DRIVER_LSB WLAN_GPIO_PIN15_PAD_DRIVER_LSB +#define GPIO_PIN15_PAD_DRIVER_MASK WLAN_GPIO_PIN15_PAD_DRIVER_MASK +#define GPIO_PIN15_PAD_DRIVER_GET(x) WLAN_GPIO_PIN15_PAD_DRIVER_GET(x) +#define GPIO_PIN15_PAD_DRIVER_SET(x) WLAN_GPIO_PIN15_PAD_DRIVER_SET(x) +#define GPIO_PIN15_SOURCE_MSB WLAN_GPIO_PIN15_SOURCE_MSB +#define GPIO_PIN15_SOURCE_LSB WLAN_GPIO_PIN15_SOURCE_LSB +#define GPIO_PIN15_SOURCE_MASK WLAN_GPIO_PIN15_SOURCE_MASK +#define GPIO_PIN15_SOURCE_GET(x) WLAN_GPIO_PIN15_SOURCE_GET(x) +#define GPIO_PIN15_SOURCE_SET(x) WLAN_GPIO_PIN15_SOURCE_SET(x) +#define GPIO_PIN16_ADDRESS WLAN_GPIO_PIN16_ADDRESS +#define GPIO_PIN16_OFFSET WLAN_GPIO_PIN16_OFFSET +#define GPIO_PIN16_CONFIG_MSB WLAN_GPIO_PIN16_CONFIG_MSB +#define GPIO_PIN16_CONFIG_LSB WLAN_GPIO_PIN16_CONFIG_LSB +#define GPIO_PIN16_CONFIG_MASK WLAN_GPIO_PIN16_CONFIG_MASK +#define GPIO_PIN16_CONFIG_GET(x) WLAN_GPIO_PIN16_CONFIG_GET(x) +#define GPIO_PIN16_CONFIG_SET(x) WLAN_GPIO_PIN16_CONFIG_SET(x) +#define GPIO_PIN16_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB +#define GPIO_PIN16_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB +#define GPIO_PIN16_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK +#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN16_INT_TYPE_MSB WLAN_GPIO_PIN16_INT_TYPE_MSB +#define GPIO_PIN16_INT_TYPE_LSB WLAN_GPIO_PIN16_INT_TYPE_LSB +#define GPIO_PIN16_INT_TYPE_MASK WLAN_GPIO_PIN16_INT_TYPE_MASK +#define GPIO_PIN16_INT_TYPE_GET(x) WLAN_GPIO_PIN16_INT_TYPE_GET(x) +#define GPIO_PIN16_INT_TYPE_SET(x) WLAN_GPIO_PIN16_INT_TYPE_SET(x) +#define GPIO_PIN16_PAD_PULL_MSB WLAN_GPIO_PIN16_PAD_PULL_MSB +#define GPIO_PIN16_PAD_PULL_LSB WLAN_GPIO_PIN16_PAD_PULL_LSB +#define GPIO_PIN16_PAD_PULL_MASK WLAN_GPIO_PIN16_PAD_PULL_MASK +#define GPIO_PIN16_PAD_PULL_GET(x) WLAN_GPIO_PIN16_PAD_PULL_GET(x) +#define GPIO_PIN16_PAD_PULL_SET(x) WLAN_GPIO_PIN16_PAD_PULL_SET(x) +#define GPIO_PIN16_PAD_STRENGTH_MSB WLAN_GPIO_PIN16_PAD_STRENGTH_MSB +#define GPIO_PIN16_PAD_STRENGTH_LSB WLAN_GPIO_PIN16_PAD_STRENGTH_LSB +#define GPIO_PIN16_PAD_STRENGTH_MASK WLAN_GPIO_PIN16_PAD_STRENGTH_MASK +#define GPIO_PIN16_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x) +#define GPIO_PIN16_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x) +#define GPIO_PIN16_PAD_DRIVER_MSB WLAN_GPIO_PIN16_PAD_DRIVER_MSB +#define GPIO_PIN16_PAD_DRIVER_LSB WLAN_GPIO_PIN16_PAD_DRIVER_LSB +#define GPIO_PIN16_PAD_DRIVER_MASK WLAN_GPIO_PIN16_PAD_DRIVER_MASK +#define GPIO_PIN16_PAD_DRIVER_GET(x) WLAN_GPIO_PIN16_PAD_DRIVER_GET(x) +#define GPIO_PIN16_PAD_DRIVER_SET(x) WLAN_GPIO_PIN16_PAD_DRIVER_SET(x) +#define GPIO_PIN16_SOURCE_MSB WLAN_GPIO_PIN16_SOURCE_MSB +#define GPIO_PIN16_SOURCE_LSB WLAN_GPIO_PIN16_SOURCE_LSB +#define GPIO_PIN16_SOURCE_MASK WLAN_GPIO_PIN16_SOURCE_MASK +#define GPIO_PIN16_SOURCE_GET(x) WLAN_GPIO_PIN16_SOURCE_GET(x) +#define GPIO_PIN16_SOURCE_SET(x) WLAN_GPIO_PIN16_SOURCE_SET(x) +#define GPIO_PIN17_ADDRESS WLAN_GPIO_PIN17_ADDRESS +#define GPIO_PIN17_OFFSET WLAN_GPIO_PIN17_OFFSET +#define GPIO_PIN17_CONFIG_MSB WLAN_GPIO_PIN17_CONFIG_MSB +#define GPIO_PIN17_CONFIG_LSB WLAN_GPIO_PIN17_CONFIG_LSB +#define GPIO_PIN17_CONFIG_MASK WLAN_GPIO_PIN17_CONFIG_MASK +#define GPIO_PIN17_CONFIG_GET(x) WLAN_GPIO_PIN17_CONFIG_GET(x) +#define GPIO_PIN17_CONFIG_SET(x) WLAN_GPIO_PIN17_CONFIG_SET(x) +#define GPIO_PIN17_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB +#define GPIO_PIN17_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB +#define GPIO_PIN17_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK +#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN17_INT_TYPE_MSB WLAN_GPIO_PIN17_INT_TYPE_MSB +#define GPIO_PIN17_INT_TYPE_LSB WLAN_GPIO_PIN17_INT_TYPE_LSB +#define GPIO_PIN17_INT_TYPE_MASK WLAN_GPIO_PIN17_INT_TYPE_MASK +#define GPIO_PIN17_INT_TYPE_GET(x) WLAN_GPIO_PIN17_INT_TYPE_GET(x) +#define GPIO_PIN17_INT_TYPE_SET(x) WLAN_GPIO_PIN17_INT_TYPE_SET(x) +#define GPIO_PIN17_PAD_PULL_MSB WLAN_GPIO_PIN17_PAD_PULL_MSB +#define GPIO_PIN17_PAD_PULL_LSB WLAN_GPIO_PIN17_PAD_PULL_LSB +#define GPIO_PIN17_PAD_PULL_MASK WLAN_GPIO_PIN17_PAD_PULL_MASK +#define GPIO_PIN17_PAD_PULL_GET(x) WLAN_GPIO_PIN17_PAD_PULL_GET(x) +#define GPIO_PIN17_PAD_PULL_SET(x) WLAN_GPIO_PIN17_PAD_PULL_SET(x) +#define GPIO_PIN17_PAD_STRENGTH_MSB WLAN_GPIO_PIN17_PAD_STRENGTH_MSB +#define GPIO_PIN17_PAD_STRENGTH_LSB WLAN_GPIO_PIN17_PAD_STRENGTH_LSB +#define GPIO_PIN17_PAD_STRENGTH_MASK WLAN_GPIO_PIN17_PAD_STRENGTH_MASK +#define GPIO_PIN17_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x) +#define GPIO_PIN17_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x) +#define GPIO_PIN17_PAD_DRIVER_MSB WLAN_GPIO_PIN17_PAD_DRIVER_MSB +#define GPIO_PIN17_PAD_DRIVER_LSB WLAN_GPIO_PIN17_PAD_DRIVER_LSB +#define GPIO_PIN17_PAD_DRIVER_MASK WLAN_GPIO_PIN17_PAD_DRIVER_MASK +#define GPIO_PIN17_PAD_DRIVER_GET(x) WLAN_GPIO_PIN17_PAD_DRIVER_GET(x) +#define GPIO_PIN17_PAD_DRIVER_SET(x) WLAN_GPIO_PIN17_PAD_DRIVER_SET(x) +#define GPIO_PIN17_SOURCE_MSB WLAN_GPIO_PIN17_SOURCE_MSB +#define GPIO_PIN17_SOURCE_LSB WLAN_GPIO_PIN17_SOURCE_LSB +#define GPIO_PIN17_SOURCE_MASK WLAN_GPIO_PIN17_SOURCE_MASK +#define GPIO_PIN17_SOURCE_GET(x) WLAN_GPIO_PIN17_SOURCE_GET(x) +#define GPIO_PIN17_SOURCE_SET(x) WLAN_GPIO_PIN17_SOURCE_SET(x) +#define GPIO_PIN18_ADDRESS WLAN_GPIO_PIN18_ADDRESS +#define GPIO_PIN18_OFFSET WLAN_GPIO_PIN18_OFFSET +#define GPIO_PIN18_CONFIG_MSB WLAN_GPIO_PIN18_CONFIG_MSB +#define GPIO_PIN18_CONFIG_LSB WLAN_GPIO_PIN18_CONFIG_LSB +#define GPIO_PIN18_CONFIG_MASK WLAN_GPIO_PIN18_CONFIG_MASK +#define GPIO_PIN18_CONFIG_GET(x) WLAN_GPIO_PIN18_CONFIG_GET(x) +#define GPIO_PIN18_CONFIG_SET(x) WLAN_GPIO_PIN18_CONFIG_SET(x) +#define GPIO_PIN18_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB +#define GPIO_PIN18_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB +#define GPIO_PIN18_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK +#define GPIO_PIN18_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN18_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN18_INT_TYPE_MSB WLAN_GPIO_PIN18_INT_TYPE_MSB +#define GPIO_PIN18_INT_TYPE_LSB WLAN_GPIO_PIN18_INT_TYPE_LSB +#define GPIO_PIN18_INT_TYPE_MASK WLAN_GPIO_PIN18_INT_TYPE_MASK +#define GPIO_PIN18_INT_TYPE_GET(x) WLAN_GPIO_PIN18_INT_TYPE_GET(x) +#define GPIO_PIN18_INT_TYPE_SET(x) WLAN_GPIO_PIN18_INT_TYPE_SET(x) +#define GPIO_PIN18_PAD_PULL_MSB WLAN_GPIO_PIN18_PAD_PULL_MSB +#define GPIO_PIN18_PAD_PULL_LSB WLAN_GPIO_PIN18_PAD_PULL_LSB +#define GPIO_PIN18_PAD_PULL_MASK WLAN_GPIO_PIN18_PAD_PULL_MASK +#define GPIO_PIN18_PAD_PULL_GET(x) WLAN_GPIO_PIN18_PAD_PULL_GET(x) +#define GPIO_PIN18_PAD_PULL_SET(x) WLAN_GPIO_PIN18_PAD_PULL_SET(x) +#define GPIO_PIN18_PAD_STRENGTH_MSB WLAN_GPIO_PIN18_PAD_STRENGTH_MSB +#define GPIO_PIN18_PAD_STRENGTH_LSB WLAN_GPIO_PIN18_PAD_STRENGTH_LSB +#define GPIO_PIN18_PAD_STRENGTH_MASK WLAN_GPIO_PIN18_PAD_STRENGTH_MASK +#define GPIO_PIN18_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x) +#define GPIO_PIN18_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x) +#define GPIO_PIN18_PAD_DRIVER_MSB WLAN_GPIO_PIN18_PAD_DRIVER_MSB +#define GPIO_PIN18_PAD_DRIVER_LSB WLAN_GPIO_PIN18_PAD_DRIVER_LSB +#define GPIO_PIN18_PAD_DRIVER_MASK WLAN_GPIO_PIN18_PAD_DRIVER_MASK +#define GPIO_PIN18_PAD_DRIVER_GET(x) WLAN_GPIO_PIN18_PAD_DRIVER_GET(x) +#define GPIO_PIN18_PAD_DRIVER_SET(x) WLAN_GPIO_PIN18_PAD_DRIVER_SET(x) +#define GPIO_PIN18_SOURCE_MSB WLAN_GPIO_PIN18_SOURCE_MSB +#define GPIO_PIN18_SOURCE_LSB WLAN_GPIO_PIN18_SOURCE_LSB +#define GPIO_PIN18_SOURCE_MASK WLAN_GPIO_PIN18_SOURCE_MASK +#define GPIO_PIN18_SOURCE_GET(x) WLAN_GPIO_PIN18_SOURCE_GET(x) +#define GPIO_PIN18_SOURCE_SET(x) WLAN_GPIO_PIN18_SOURCE_SET(x) +#define GPIO_PIN19_ADDRESS WLAN_GPIO_PIN19_ADDRESS +#define GPIO_PIN19_OFFSET WLAN_GPIO_PIN19_OFFSET +#define GPIO_PIN19_CONFIG_MSB WLAN_GPIO_PIN19_CONFIG_MSB +#define GPIO_PIN19_CONFIG_LSB WLAN_GPIO_PIN19_CONFIG_LSB +#define GPIO_PIN19_CONFIG_MASK WLAN_GPIO_PIN19_CONFIG_MASK +#define GPIO_PIN19_CONFIG_GET(x) WLAN_GPIO_PIN19_CONFIG_GET(x) +#define GPIO_PIN19_CONFIG_SET(x) WLAN_GPIO_PIN19_CONFIG_SET(x) +#define GPIO_PIN19_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB +#define GPIO_PIN19_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB +#define GPIO_PIN19_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK +#define GPIO_PIN19_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN19_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN19_INT_TYPE_MSB WLAN_GPIO_PIN19_INT_TYPE_MSB +#define GPIO_PIN19_INT_TYPE_LSB WLAN_GPIO_PIN19_INT_TYPE_LSB +#define GPIO_PIN19_INT_TYPE_MASK WLAN_GPIO_PIN19_INT_TYPE_MASK +#define GPIO_PIN19_INT_TYPE_GET(x) WLAN_GPIO_PIN19_INT_TYPE_GET(x) +#define GPIO_PIN19_INT_TYPE_SET(x) WLAN_GPIO_PIN19_INT_TYPE_SET(x) +#define GPIO_PIN19_PAD_PULL_MSB WLAN_GPIO_PIN19_PAD_PULL_MSB +#define GPIO_PIN19_PAD_PULL_LSB WLAN_GPIO_PIN19_PAD_PULL_LSB +#define GPIO_PIN19_PAD_PULL_MASK WLAN_GPIO_PIN19_PAD_PULL_MASK +#define GPIO_PIN19_PAD_PULL_GET(x) WLAN_GPIO_PIN19_PAD_PULL_GET(x) +#define GPIO_PIN19_PAD_PULL_SET(x) WLAN_GPIO_PIN19_PAD_PULL_SET(x) +#define GPIO_PIN19_PAD_STRENGTH_MSB WLAN_GPIO_PIN19_PAD_STRENGTH_MSB +#define GPIO_PIN19_PAD_STRENGTH_LSB WLAN_GPIO_PIN19_PAD_STRENGTH_LSB +#define GPIO_PIN19_PAD_STRENGTH_MASK WLAN_GPIO_PIN19_PAD_STRENGTH_MASK +#define GPIO_PIN19_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x) +#define GPIO_PIN19_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x) +#define GPIO_PIN19_PAD_DRIVER_MSB WLAN_GPIO_PIN19_PAD_DRIVER_MSB +#define GPIO_PIN19_PAD_DRIVER_LSB WLAN_GPIO_PIN19_PAD_DRIVER_LSB +#define GPIO_PIN19_PAD_DRIVER_MASK WLAN_GPIO_PIN19_PAD_DRIVER_MASK +#define GPIO_PIN19_PAD_DRIVER_GET(x) WLAN_GPIO_PIN19_PAD_DRIVER_GET(x) +#define GPIO_PIN19_PAD_DRIVER_SET(x) WLAN_GPIO_PIN19_PAD_DRIVER_SET(x) +#define GPIO_PIN19_SOURCE_MSB WLAN_GPIO_PIN19_SOURCE_MSB +#define GPIO_PIN19_SOURCE_LSB WLAN_GPIO_PIN19_SOURCE_LSB +#define GPIO_PIN19_SOURCE_MASK WLAN_GPIO_PIN19_SOURCE_MASK +#define GPIO_PIN19_SOURCE_GET(x) WLAN_GPIO_PIN19_SOURCE_GET(x) +#define GPIO_PIN19_SOURCE_SET(x) WLAN_GPIO_PIN19_SOURCE_SET(x) +#define GPIO_PIN20_ADDRESS WLAN_GPIO_PIN20_ADDRESS +#define GPIO_PIN20_OFFSET WLAN_GPIO_PIN20_OFFSET +#define GPIO_PIN20_CONFIG_MSB WLAN_GPIO_PIN20_CONFIG_MSB +#define GPIO_PIN20_CONFIG_LSB WLAN_GPIO_PIN20_CONFIG_LSB +#define GPIO_PIN20_CONFIG_MASK WLAN_GPIO_PIN20_CONFIG_MASK +#define GPIO_PIN20_CONFIG_GET(x) WLAN_GPIO_PIN20_CONFIG_GET(x) +#define GPIO_PIN20_CONFIG_SET(x) WLAN_GPIO_PIN20_CONFIG_SET(x) +#define GPIO_PIN20_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB +#define GPIO_PIN20_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB +#define GPIO_PIN20_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK +#define GPIO_PIN20_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN20_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN20_INT_TYPE_MSB WLAN_GPIO_PIN20_INT_TYPE_MSB +#define GPIO_PIN20_INT_TYPE_LSB WLAN_GPIO_PIN20_INT_TYPE_LSB +#define GPIO_PIN20_INT_TYPE_MASK WLAN_GPIO_PIN20_INT_TYPE_MASK +#define GPIO_PIN20_INT_TYPE_GET(x) WLAN_GPIO_PIN20_INT_TYPE_GET(x) +#define GPIO_PIN20_INT_TYPE_SET(x) WLAN_GPIO_PIN20_INT_TYPE_SET(x) +#define GPIO_PIN20_PAD_PULL_MSB WLAN_GPIO_PIN20_PAD_PULL_MSB +#define GPIO_PIN20_PAD_PULL_LSB WLAN_GPIO_PIN20_PAD_PULL_LSB +#define GPIO_PIN20_PAD_PULL_MASK WLAN_GPIO_PIN20_PAD_PULL_MASK +#define GPIO_PIN20_PAD_PULL_GET(x) WLAN_GPIO_PIN20_PAD_PULL_GET(x) +#define GPIO_PIN20_PAD_PULL_SET(x) WLAN_GPIO_PIN20_PAD_PULL_SET(x) +#define GPIO_PIN20_PAD_STRENGTH_MSB WLAN_GPIO_PIN20_PAD_STRENGTH_MSB +#define GPIO_PIN20_PAD_STRENGTH_LSB WLAN_GPIO_PIN20_PAD_STRENGTH_LSB +#define GPIO_PIN20_PAD_STRENGTH_MASK WLAN_GPIO_PIN20_PAD_STRENGTH_MASK +#define GPIO_PIN20_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x) +#define GPIO_PIN20_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x) +#define GPIO_PIN20_PAD_DRIVER_MSB WLAN_GPIO_PIN20_PAD_DRIVER_MSB +#define GPIO_PIN20_PAD_DRIVER_LSB WLAN_GPIO_PIN20_PAD_DRIVER_LSB +#define GPIO_PIN20_PAD_DRIVER_MASK WLAN_GPIO_PIN20_PAD_DRIVER_MASK +#define GPIO_PIN20_PAD_DRIVER_GET(x) WLAN_GPIO_PIN20_PAD_DRIVER_GET(x) +#define GPIO_PIN20_PAD_DRIVER_SET(x) WLAN_GPIO_PIN20_PAD_DRIVER_SET(x) +#define GPIO_PIN20_SOURCE_MSB WLAN_GPIO_PIN20_SOURCE_MSB +#define GPIO_PIN20_SOURCE_LSB WLAN_GPIO_PIN20_SOURCE_LSB +#define GPIO_PIN20_SOURCE_MASK WLAN_GPIO_PIN20_SOURCE_MASK +#define GPIO_PIN20_SOURCE_GET(x) WLAN_GPIO_PIN20_SOURCE_GET(x) +#define GPIO_PIN20_SOURCE_SET(x) WLAN_GPIO_PIN20_SOURCE_SET(x) +#define GPIO_PIN21_ADDRESS WLAN_GPIO_PIN21_ADDRESS +#define GPIO_PIN21_OFFSET WLAN_GPIO_PIN21_OFFSET +#define GPIO_PIN21_CONFIG_MSB WLAN_GPIO_PIN21_CONFIG_MSB +#define GPIO_PIN21_CONFIG_LSB WLAN_GPIO_PIN21_CONFIG_LSB +#define GPIO_PIN21_CONFIG_MASK WLAN_GPIO_PIN21_CONFIG_MASK +#define GPIO_PIN21_CONFIG_GET(x) WLAN_GPIO_PIN21_CONFIG_GET(x) +#define GPIO_PIN21_CONFIG_SET(x) WLAN_GPIO_PIN21_CONFIG_SET(x) +#define GPIO_PIN21_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB +#define GPIO_PIN21_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB +#define GPIO_PIN21_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK +#define GPIO_PIN21_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN21_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN21_INT_TYPE_MSB WLAN_GPIO_PIN21_INT_TYPE_MSB +#define GPIO_PIN21_INT_TYPE_LSB WLAN_GPIO_PIN21_INT_TYPE_LSB +#define GPIO_PIN21_INT_TYPE_MASK WLAN_GPIO_PIN21_INT_TYPE_MASK +#define GPIO_PIN21_INT_TYPE_GET(x) WLAN_GPIO_PIN21_INT_TYPE_GET(x) +#define GPIO_PIN21_INT_TYPE_SET(x) WLAN_GPIO_PIN21_INT_TYPE_SET(x) +#define GPIO_PIN21_PAD_PULL_MSB WLAN_GPIO_PIN21_PAD_PULL_MSB +#define GPIO_PIN21_PAD_PULL_LSB WLAN_GPIO_PIN21_PAD_PULL_LSB +#define GPIO_PIN21_PAD_PULL_MASK WLAN_GPIO_PIN21_PAD_PULL_MASK +#define GPIO_PIN21_PAD_PULL_GET(x) WLAN_GPIO_PIN21_PAD_PULL_GET(x) +#define GPIO_PIN21_PAD_PULL_SET(x) WLAN_GPIO_PIN21_PAD_PULL_SET(x) +#define GPIO_PIN21_PAD_STRENGTH_MSB WLAN_GPIO_PIN21_PAD_STRENGTH_MSB +#define GPIO_PIN21_PAD_STRENGTH_LSB WLAN_GPIO_PIN21_PAD_STRENGTH_LSB +#define GPIO_PIN21_PAD_STRENGTH_MASK WLAN_GPIO_PIN21_PAD_STRENGTH_MASK +#define GPIO_PIN21_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x) +#define GPIO_PIN21_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x) +#define GPIO_PIN21_PAD_DRIVER_MSB WLAN_GPIO_PIN21_PAD_DRIVER_MSB +#define GPIO_PIN21_PAD_DRIVER_LSB WLAN_GPIO_PIN21_PAD_DRIVER_LSB +#define GPIO_PIN21_PAD_DRIVER_MASK WLAN_GPIO_PIN21_PAD_DRIVER_MASK +#define GPIO_PIN21_PAD_DRIVER_GET(x) WLAN_GPIO_PIN21_PAD_DRIVER_GET(x) +#define GPIO_PIN21_PAD_DRIVER_SET(x) WLAN_GPIO_PIN21_PAD_DRIVER_SET(x) +#define GPIO_PIN21_SOURCE_MSB WLAN_GPIO_PIN21_SOURCE_MSB +#define GPIO_PIN21_SOURCE_LSB WLAN_GPIO_PIN21_SOURCE_LSB +#define GPIO_PIN21_SOURCE_MASK WLAN_GPIO_PIN21_SOURCE_MASK +#define GPIO_PIN21_SOURCE_GET(x) WLAN_GPIO_PIN21_SOURCE_GET(x) +#define GPIO_PIN21_SOURCE_SET(x) WLAN_GPIO_PIN21_SOURCE_SET(x) +#define GPIO_PIN22_ADDRESS WLAN_GPIO_PIN22_ADDRESS +#define GPIO_PIN22_OFFSET WLAN_GPIO_PIN22_OFFSET +#define GPIO_PIN22_CONFIG_MSB WLAN_GPIO_PIN22_CONFIG_MSB +#define GPIO_PIN22_CONFIG_LSB WLAN_GPIO_PIN22_CONFIG_LSB +#define GPIO_PIN22_CONFIG_MASK WLAN_GPIO_PIN22_CONFIG_MASK +#define GPIO_PIN22_CONFIG_GET(x) WLAN_GPIO_PIN22_CONFIG_GET(x) +#define GPIO_PIN22_CONFIG_SET(x) WLAN_GPIO_PIN22_CONFIG_SET(x) +#define GPIO_PIN22_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB +#define GPIO_PIN22_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB +#define GPIO_PIN22_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK +#define GPIO_PIN22_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN22_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN22_INT_TYPE_MSB WLAN_GPIO_PIN22_INT_TYPE_MSB +#define GPIO_PIN22_INT_TYPE_LSB WLAN_GPIO_PIN22_INT_TYPE_LSB +#define GPIO_PIN22_INT_TYPE_MASK WLAN_GPIO_PIN22_INT_TYPE_MASK +#define GPIO_PIN22_INT_TYPE_GET(x) WLAN_GPIO_PIN22_INT_TYPE_GET(x) +#define GPIO_PIN22_INT_TYPE_SET(x) WLAN_GPIO_PIN22_INT_TYPE_SET(x) +#define GPIO_PIN22_PAD_PULL_MSB WLAN_GPIO_PIN22_PAD_PULL_MSB +#define GPIO_PIN22_PAD_PULL_LSB WLAN_GPIO_PIN22_PAD_PULL_LSB +#define GPIO_PIN22_PAD_PULL_MASK WLAN_GPIO_PIN22_PAD_PULL_MASK +#define GPIO_PIN22_PAD_PULL_GET(x) WLAN_GPIO_PIN22_PAD_PULL_GET(x) +#define GPIO_PIN22_PAD_PULL_SET(x) WLAN_GPIO_PIN22_PAD_PULL_SET(x) +#define GPIO_PIN22_PAD_STRENGTH_MSB WLAN_GPIO_PIN22_PAD_STRENGTH_MSB +#define GPIO_PIN22_PAD_STRENGTH_LSB WLAN_GPIO_PIN22_PAD_STRENGTH_LSB +#define GPIO_PIN22_PAD_STRENGTH_MASK WLAN_GPIO_PIN22_PAD_STRENGTH_MASK +#define GPIO_PIN22_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x) +#define GPIO_PIN22_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x) +#define GPIO_PIN22_PAD_DRIVER_MSB WLAN_GPIO_PIN22_PAD_DRIVER_MSB +#define GPIO_PIN22_PAD_DRIVER_LSB WLAN_GPIO_PIN22_PAD_DRIVER_LSB +#define GPIO_PIN22_PAD_DRIVER_MASK WLAN_GPIO_PIN22_PAD_DRIVER_MASK +#define GPIO_PIN22_PAD_DRIVER_GET(x) WLAN_GPIO_PIN22_PAD_DRIVER_GET(x) +#define GPIO_PIN22_PAD_DRIVER_SET(x) WLAN_GPIO_PIN22_PAD_DRIVER_SET(x) +#define GPIO_PIN22_SOURCE_MSB WLAN_GPIO_PIN22_SOURCE_MSB +#define GPIO_PIN22_SOURCE_LSB WLAN_GPIO_PIN22_SOURCE_LSB +#define GPIO_PIN22_SOURCE_MASK WLAN_GPIO_PIN22_SOURCE_MASK +#define GPIO_PIN22_SOURCE_GET(x) WLAN_GPIO_PIN22_SOURCE_GET(x) +#define GPIO_PIN22_SOURCE_SET(x) WLAN_GPIO_PIN22_SOURCE_SET(x) +#define GPIO_PIN23_ADDRESS WLAN_GPIO_PIN23_ADDRESS +#define GPIO_PIN23_OFFSET WLAN_GPIO_PIN23_OFFSET +#define GPIO_PIN23_CONFIG_MSB WLAN_GPIO_PIN23_CONFIG_MSB +#define GPIO_PIN23_CONFIG_LSB WLAN_GPIO_PIN23_CONFIG_LSB +#define GPIO_PIN23_CONFIG_MASK WLAN_GPIO_PIN23_CONFIG_MASK +#define GPIO_PIN23_CONFIG_GET(x) WLAN_GPIO_PIN23_CONFIG_GET(x) +#define GPIO_PIN23_CONFIG_SET(x) WLAN_GPIO_PIN23_CONFIG_SET(x) +#define GPIO_PIN23_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB +#define GPIO_PIN23_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB +#define GPIO_PIN23_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK +#define GPIO_PIN23_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN23_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN23_INT_TYPE_MSB WLAN_GPIO_PIN23_INT_TYPE_MSB +#define GPIO_PIN23_INT_TYPE_LSB WLAN_GPIO_PIN23_INT_TYPE_LSB +#define GPIO_PIN23_INT_TYPE_MASK WLAN_GPIO_PIN23_INT_TYPE_MASK +#define GPIO_PIN23_INT_TYPE_GET(x) WLAN_GPIO_PIN23_INT_TYPE_GET(x) +#define GPIO_PIN23_INT_TYPE_SET(x) WLAN_GPIO_PIN23_INT_TYPE_SET(x) +#define GPIO_PIN23_PAD_DRIVER_MSB WLAN_GPIO_PIN23_PAD_DRIVER_MSB +#define GPIO_PIN23_PAD_DRIVER_LSB WLAN_GPIO_PIN23_PAD_DRIVER_LSB +#define GPIO_PIN23_PAD_DRIVER_MASK WLAN_GPIO_PIN23_PAD_DRIVER_MASK +#define GPIO_PIN23_PAD_DRIVER_GET(x) WLAN_GPIO_PIN23_PAD_DRIVER_GET(x) +#define GPIO_PIN23_PAD_DRIVER_SET(x) WLAN_GPIO_PIN23_PAD_DRIVER_SET(x) +#define GPIO_PIN23_SOURCE_MSB WLAN_GPIO_PIN23_SOURCE_MSB +#define GPIO_PIN23_SOURCE_LSB WLAN_GPIO_PIN23_SOURCE_LSB +#define GPIO_PIN23_SOURCE_MASK WLAN_GPIO_PIN23_SOURCE_MASK +#define GPIO_PIN23_SOURCE_GET(x) WLAN_GPIO_PIN23_SOURCE_GET(x) +#define GPIO_PIN23_SOURCE_SET(x) WLAN_GPIO_PIN23_SOURCE_SET(x) +#define GPIO_PIN24_ADDRESS WLAN_GPIO_PIN24_ADDRESS +#define GPIO_PIN24_OFFSET WLAN_GPIO_PIN24_OFFSET +#define GPIO_PIN24_CONFIG_MSB WLAN_GPIO_PIN24_CONFIG_MSB +#define GPIO_PIN24_CONFIG_LSB WLAN_GPIO_PIN24_CONFIG_LSB +#define GPIO_PIN24_CONFIG_MASK WLAN_GPIO_PIN24_CONFIG_MASK +#define GPIO_PIN24_CONFIG_GET(x) WLAN_GPIO_PIN24_CONFIG_GET(x) +#define GPIO_PIN24_CONFIG_SET(x) WLAN_GPIO_PIN24_CONFIG_SET(x) +#define GPIO_PIN24_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB +#define GPIO_PIN24_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB +#define GPIO_PIN24_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK +#define GPIO_PIN24_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN24_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN24_INT_TYPE_MSB WLAN_GPIO_PIN24_INT_TYPE_MSB +#define GPIO_PIN24_INT_TYPE_LSB WLAN_GPIO_PIN24_INT_TYPE_LSB +#define GPIO_PIN24_INT_TYPE_MASK WLAN_GPIO_PIN24_INT_TYPE_MASK +#define GPIO_PIN24_INT_TYPE_GET(x) WLAN_GPIO_PIN24_INT_TYPE_GET(x) +#define GPIO_PIN24_INT_TYPE_SET(x) WLAN_GPIO_PIN24_INT_TYPE_SET(x) +#define GPIO_PIN24_PAD_DRIVER_MSB WLAN_GPIO_PIN24_PAD_DRIVER_MSB +#define GPIO_PIN24_PAD_DRIVER_LSB WLAN_GPIO_PIN24_PAD_DRIVER_LSB +#define GPIO_PIN24_PAD_DRIVER_MASK WLAN_GPIO_PIN24_PAD_DRIVER_MASK +#define GPIO_PIN24_PAD_DRIVER_GET(x) WLAN_GPIO_PIN24_PAD_DRIVER_GET(x) +#define GPIO_PIN24_PAD_DRIVER_SET(x) WLAN_GPIO_PIN24_PAD_DRIVER_SET(x) +#define GPIO_PIN24_SOURCE_MSB WLAN_GPIO_PIN24_SOURCE_MSB +#define GPIO_PIN24_SOURCE_LSB WLAN_GPIO_PIN24_SOURCE_LSB +#define GPIO_PIN24_SOURCE_MASK WLAN_GPIO_PIN24_SOURCE_MASK +#define GPIO_PIN24_SOURCE_GET(x) WLAN_GPIO_PIN24_SOURCE_GET(x) +#define GPIO_PIN24_SOURCE_SET(x) WLAN_GPIO_PIN24_SOURCE_SET(x) +#define GPIO_PIN25_ADDRESS WLAN_GPIO_PIN25_ADDRESS +#define GPIO_PIN25_OFFSET WLAN_GPIO_PIN25_OFFSET +#define GPIO_PIN25_CONFIG_MSB WLAN_GPIO_PIN25_CONFIG_MSB +#define GPIO_PIN25_CONFIG_LSB WLAN_GPIO_PIN25_CONFIG_LSB +#define GPIO_PIN25_CONFIG_MASK WLAN_GPIO_PIN25_CONFIG_MASK +#define GPIO_PIN25_CONFIG_GET(x) WLAN_GPIO_PIN25_CONFIG_GET(x) +#define GPIO_PIN25_CONFIG_SET(x) WLAN_GPIO_PIN25_CONFIG_SET(x) +#define GPIO_PIN25_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB +#define GPIO_PIN25_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB +#define GPIO_PIN25_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK +#define GPIO_PIN25_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x) +#define GPIO_PIN25_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x) +#define GPIO_PIN25_INT_TYPE_MSB WLAN_GPIO_PIN25_INT_TYPE_MSB +#define GPIO_PIN25_INT_TYPE_LSB WLAN_GPIO_PIN25_INT_TYPE_LSB +#define GPIO_PIN25_INT_TYPE_MASK WLAN_GPIO_PIN25_INT_TYPE_MASK +#define GPIO_PIN25_INT_TYPE_GET(x) WLAN_GPIO_PIN25_INT_TYPE_GET(x) +#define GPIO_PIN25_INT_TYPE_SET(x) WLAN_GPIO_PIN25_INT_TYPE_SET(x) +#define GPIO_PIN25_PAD_DRIVER_MSB WLAN_GPIO_PIN25_PAD_DRIVER_MSB +#define GPIO_PIN25_PAD_DRIVER_LSB WLAN_GPIO_PIN25_PAD_DRIVER_LSB +#define GPIO_PIN25_PAD_DRIVER_MASK WLAN_GPIO_PIN25_PAD_DRIVER_MASK +#define GPIO_PIN25_PAD_DRIVER_GET(x) WLAN_GPIO_PIN25_PAD_DRIVER_GET(x) +#define GPIO_PIN25_PAD_DRIVER_SET(x) WLAN_GPIO_PIN25_PAD_DRIVER_SET(x) +#define GPIO_PIN25_SOURCE_MSB WLAN_GPIO_PIN25_SOURCE_MSB +#define GPIO_PIN25_SOURCE_LSB WLAN_GPIO_PIN25_SOURCE_LSB +#define GPIO_PIN25_SOURCE_MASK WLAN_GPIO_PIN25_SOURCE_MASK +#define GPIO_PIN25_SOURCE_GET(x) WLAN_GPIO_PIN25_SOURCE_GET(x) +#define GPIO_PIN25_SOURCE_SET(x) WLAN_GPIO_PIN25_SOURCE_SET(x) +#define SIGMA_DELTA_ADDRESS WLAN_SIGMA_DELTA_ADDRESS +#define SIGMA_DELTA_OFFSET WLAN_SIGMA_DELTA_OFFSET +#define SIGMA_DELTA_ENABLE_MSB WLAN_SIGMA_DELTA_ENABLE_MSB +#define SIGMA_DELTA_ENABLE_LSB WLAN_SIGMA_DELTA_ENABLE_LSB +#define SIGMA_DELTA_ENABLE_MASK WLAN_SIGMA_DELTA_ENABLE_MASK +#define SIGMA_DELTA_ENABLE_GET(x) WLAN_SIGMA_DELTA_ENABLE_GET(x) +#define SIGMA_DELTA_ENABLE_SET(x) WLAN_SIGMA_DELTA_ENABLE_SET(x) +#define SIGMA_DELTA_PRESCALAR_MSB WLAN_SIGMA_DELTA_PRESCALAR_MSB +#define SIGMA_DELTA_PRESCALAR_LSB WLAN_SIGMA_DELTA_PRESCALAR_LSB +#define SIGMA_DELTA_PRESCALAR_MASK WLAN_SIGMA_DELTA_PRESCALAR_MASK +#define SIGMA_DELTA_PRESCALAR_GET(x) WLAN_SIGMA_DELTA_PRESCALAR_GET(x) +#define SIGMA_DELTA_PRESCALAR_SET(x) WLAN_SIGMA_DELTA_PRESCALAR_SET(x) +#define SIGMA_DELTA_TARGET_MSB WLAN_SIGMA_DELTA_TARGET_MSB +#define SIGMA_DELTA_TARGET_LSB WLAN_SIGMA_DELTA_TARGET_LSB +#define SIGMA_DELTA_TARGET_MASK WLAN_SIGMA_DELTA_TARGET_MASK +#define SIGMA_DELTA_TARGET_GET(x) WLAN_SIGMA_DELTA_TARGET_GET(x) +#define SIGMA_DELTA_TARGET_SET(x) WLAN_SIGMA_DELTA_TARGET_SET(x) +#define DEBUG_CONTROL_ADDRESS WLAN_DEBUG_CONTROL_ADDRESS +#define DEBUG_CONTROL_OFFSET WLAN_DEBUG_CONTROL_OFFSET +#define DEBUG_CONTROL_ENABLE_MSB WLAN_DEBUG_CONTROL_ENABLE_MSB +#define DEBUG_CONTROL_ENABLE_LSB WLAN_DEBUG_CONTROL_ENABLE_LSB +#define DEBUG_CONTROL_ENABLE_MASK WLAN_DEBUG_CONTROL_ENABLE_MASK +#define DEBUG_CONTROL_ENABLE_GET(x) WLAN_DEBUG_CONTROL_ENABLE_GET(x) +#define DEBUG_CONTROL_ENABLE_SET(x) WLAN_DEBUG_CONTROL_ENABLE_SET(x) +#define DEBUG_INPUT_SEL_ADDRESS WLAN_DEBUG_INPUT_SEL_ADDRESS +#define DEBUG_INPUT_SEL_OFFSET WLAN_DEBUG_INPUT_SEL_OFFSET +#define DEBUG_INPUT_SEL_SHIFT_MSB WLAN_DEBUG_INPUT_SEL_SHIFT_MSB +#define DEBUG_INPUT_SEL_SHIFT_LSB WLAN_DEBUG_INPUT_SEL_SHIFT_LSB +#define DEBUG_INPUT_SEL_SHIFT_MASK WLAN_DEBUG_INPUT_SEL_SHIFT_MASK +#define DEBUG_INPUT_SEL_SHIFT_GET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x) +#define DEBUG_INPUT_SEL_SHIFT_SET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x) +#define DEBUG_INPUT_SEL_SRC_MSB WLAN_DEBUG_INPUT_SEL_SRC_MSB +#define DEBUG_INPUT_SEL_SRC_LSB WLAN_DEBUG_INPUT_SEL_SRC_LSB +#define DEBUG_INPUT_SEL_SRC_MASK WLAN_DEBUG_INPUT_SEL_SRC_MASK +#define DEBUG_INPUT_SEL_SRC_GET(x) WLAN_DEBUG_INPUT_SEL_SRC_GET(x) +#define DEBUG_INPUT_SEL_SRC_SET(x) WLAN_DEBUG_INPUT_SEL_SRC_SET(x) +#define DEBUG_OUT_ADDRESS WLAN_DEBUG_OUT_ADDRESS +#define DEBUG_OUT_OFFSET WLAN_DEBUG_OUT_OFFSET +#define DEBUG_OUT_DATA_MSB WLAN_DEBUG_OUT_DATA_MSB +#define DEBUG_OUT_DATA_LSB WLAN_DEBUG_OUT_DATA_LSB +#define DEBUG_OUT_DATA_MASK WLAN_DEBUG_OUT_DATA_MASK +#define DEBUG_OUT_DATA_GET(x) WLAN_DEBUG_OUT_DATA_GET(x) +#define DEBUG_OUT_DATA_SET(x) WLAN_DEBUG_OUT_DATA_SET(x) +#define RESET_TUPLE_STATUS_ADDRESS WLAN_RESET_TUPLE_STATUS_ADDRESS +#define RESET_TUPLE_STATUS_OFFSET WLAN_RESET_TUPLE_STATUS_OFFSET +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) +#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) +#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) + + +#endif +#endif + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h new file mode 100644 index 000000000000..f700d41851c6 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_dma_reg.h @@ -0,0 +1,587 @@ +// +// Copyright (c) 2002-2009 Atheros Communications Inc. +// All rights reserved. +// $ATH_LICENSE_TMAC_DMAGET_C$ +// + +/*****************************************************************************/ +/* AR6003 WLAN MAC DMA register definitions */ +/*****************************************************************************/ + +#ifndef _AR6000_DMAREG_H_ +#define _AR6000_DMAREG_H_ + +/* + * Definitions for the Atheros AR6003 chipset. + */ + +/* DMA Control and Interrupt Registers */ +#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */ +#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */ +#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */ +#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */ + +#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */ + +#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */ +#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */ +#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */ +#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */ +#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */ +#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */ +#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */ +#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */ +#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */ + +#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */ +#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF + +#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */ +#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */ +#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */ + +#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */ +#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */ +#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */ + +#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */ +#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */ +#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */ + +#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */ +#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */ +#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */ +#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */ +#define MAC_DMA_FTRIG_64B 0x00000010 /* default */ +#define MAC_DMA_FTRIG_128B 0x00000020 +#define MAC_DMA_FTRIG_192B 0x00000030 +#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */ +#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800 + +#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */ +#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */ +#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */ +#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */ +#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */ + +#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */ +#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */ +#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */ +#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */ +#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */ + +#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */ +#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */ + +#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */ +#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */ + +#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */ +#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */ +#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */ + /* for which frame completions will cause */ + /* a reset of the no frame xmit'd timeout */ + +#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */ +#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */ + +#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */ +#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */ + +#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */ +#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */ +#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */ +#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */ +#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */ +#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */ + + +#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */ +/* + * Interrupt Status Registers + * + * Only the bits in the ISR_P register and the IMR_P registers + * control whether the MAC's INTA# output is asserted. The bits in + * the secondary interrupt status/mask registers control what bits + * are set in the primary interrupt status register; however the + * IMR_S* registers DO NOT determine whether INTA# is asserted. + * That is INTA# is asserted only when the logical AND of ISR_P + * and IMR_P is non-zero. The secondary interrupt mask/status + * registers affect what bits are set in ISR_P but they do not + * directly affect whether INTA# is asserted. + */ +#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */ +#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */ +#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */ +#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */ +#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */ +#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */ +#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */ +#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */ +#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */ +#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */ +#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */ +#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */ +#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */ +#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */ +#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */ +#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */ +#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */ +#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */ +#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */ +#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */ +#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */ +#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */ +#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */ +#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */ +#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */ +#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */ +#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */ +#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */ +#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */ +#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */ +#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */ + +#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */ +#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */ +#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0 +#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */ +#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16 + +#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */ +#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */ +#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0 +#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */ +#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16 + +#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */ +#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */ +#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */ +#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800 +#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000 +#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000 +#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 +#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 +#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000 +#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000 +#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000 +#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 +#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000 +#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 +#define MAC_DMA_ISR_S2_CST_MASK 0x00400000 +#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000 +#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */ +#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */ +#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ +#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ +#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */ +#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */ +#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ + +#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */ +#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ +#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ + +#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */ +#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */ + +#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */ +#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 +#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 +#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 +#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 +#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 +#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 +#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 +#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 +#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i)) +#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000 +#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 +#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 +#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 +#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 +#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 +#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000 +#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) + +#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */ +/* + * Interrupt Mask Registers + * + * Only the bits in the IMR control whether the MAC's INTA# + * output will be asserted. The bits in the secondary interrupt + * mask registers control what bits get set in the primary + * interrupt status register; however the IMR_S* registers + * DO NOT determine whether INTA# is asserted. + */ +#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */ +#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */ +#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */ +#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */ +#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */ +#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */ +#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */ +#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */ +#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */ +#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */ +#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */ +#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */ +#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */ +#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */ +#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */ +#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */ +#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */ +#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */ +#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */ +#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */ +#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */ +#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */ +#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */ +#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */ +#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */ +#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */ +#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */ +#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */ +#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/ +#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */ +#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */ + +#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */ +#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */ +#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0 +#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */ +#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16 + +#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */ +#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */ +#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0 +#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */ +#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16 + +#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */ +#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */ +#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0 +#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800 +#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000 +#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000 +#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000 +#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000 +#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000 +#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000 +#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000 +#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000 +#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000 +#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000 +#define MAC_DMA_IMR_S2_CST_MASK 0x00400000 +#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000 +#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */ +#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */ +#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */ +#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */ +#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */ +#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */ +#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */ + +#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */ +#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ +#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ +#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16 + +#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */ +#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */ + +#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */ +#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001 +#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002 +#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004 +#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008 +#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010 +#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020 +#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040 +#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i)) +#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000 +#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000 +#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000 +#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000 +#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000 +#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000 +#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000 +#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24 +#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i)) + +#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */ + +/* Shadow copies with read-and-clear access */ +#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */ +#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */ +#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */ +#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */ +#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */ +#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */ + +#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */ +#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */ +#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */ +/* QCU registers */ + +#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */ +#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */ +#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */ +#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */ +#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */ +#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */ +#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */ +#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */ +#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */ +#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */ +#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */ +#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */ +#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */ +#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */ + + +#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */ +#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */ +#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */ +#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */ +#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */ +#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */ +#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */ + +#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */ +#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */ + +#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */ +#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */ +#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */ +#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */ +#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */ +#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */ +#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */ +#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */ +#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr + (empty q) */ +#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr + (empty beacon q) */ +#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */ +#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */ +#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */ +#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */ +#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */ + +#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */ +#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */ +#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */ + +#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */ + +/* DCU registers */ + +#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */ +#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */ +#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */ +#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */ +#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */ +#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */ +#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */ +#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */ +#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */ +#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */ +#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */ + +#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */ + + +#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */ +#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2)) +#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */ +#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0 +#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */ +#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10 +#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */ +#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20 +/* + * Note: even though this field is 8 bits wide the + * maximum supported AIFS value is 0xFc. Setting the AIFS value + * to 0xFd 0xFe, or 0xFf will not work correctly and will cause + * the DCU to hang. + */ +#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */ + +#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */ +#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */ +#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */ +#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */ +#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */ +#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */ +#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */ +#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */ +#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */ +#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */ +#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */ +#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0 +#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */ +#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8 +#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */ +#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14 + +#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */ + +#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */ +#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */ +#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */ +#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */ +#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */ +#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */ +#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */ +#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */ +#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */ +#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */ +#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */ +#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */ +#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */ + +#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */ +#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */ +#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */ +#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */ +#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000 + +#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */ +#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D0_EOL_ADDRESS 0x00001180 +#define MAC_DMA_D1_EOL_ADDRESS 0x00001184 +#define MAC_DMA_D2_EOL_ADDRESS 0x00001188 +#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C +#define MAC_DMA_D4_EOL_ADDRESS 0x00001190 +#define MAC_DMA_D5_EOL_ADDRESS 0x00001194 +#define MAC_DMA_D6_EOL_ADDRESS 0x00001198 +#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C +#define MAC_DMA_D8_EOL_ADDRESS 0x00001200 +#define MAC_DMA_D9_EOL_ADDRESS 0x00001204 +#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2)) + +#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */ +#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0 +#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series + station RTS/data failure + count reset policy */ +#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series + CW reset policy */ +#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */ + +#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */ +#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */ +#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor + setting */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision + handling policy */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14 +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */ +#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */ +#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17 +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */ +#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */ +#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */ +#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */ +#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */ +#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */ + +#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */ + + + +#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */ +#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */ + +#endif /* _AR6000_DMMAEG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h new file mode 100644 index 000000000000..9825b7b984fa --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mac_pcu_reg.h @@ -0,0 +1,3061 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MAC_PCU_REG_H_ +#define _MAC_PCU_REG_H_ + +#define MAC_PCU_STA_ADDR_L32_ADDRESS 0x00008000 +#define MAC_PCU_STA_ADDR_L32_OFFSET 0x00000000 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB 31 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB 0 +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK 0xffffffff +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x) (((x) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) +#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x) (((x) << MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) + +#define MAC_PCU_STA_ADDR_U16_ADDRESS 0x00008004 +#define MAC_PCU_STA_ADDR_U16_OFFSET 0x00000004 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) +#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB 30 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB 30 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK 0x40000000 +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) +#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000 +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) +#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB 28 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB 28 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK 0x10000000 +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) +#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000 +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) +#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000 +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) +#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB 25 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB 25 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK 0x02000000 +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) +#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB 24 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB 24 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK 0x01000000 +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) +#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB 23 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB 23 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK 0x00800000 +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) +#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB 22 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB 22 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK 0x00400000 +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) +#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB 21 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB 21 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK 0x00200000 +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) +#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) +#define MAC_PCU_STA_ADDR_U16_PCF_MSB 20 +#define MAC_PCU_STA_ADDR_U16_PCF_LSB 20 +#define MAC_PCU_STA_ADDR_U16_PCF_MASK 0x00100000 +#define MAC_PCU_STA_ADDR_U16_PCF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PCF_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB) +#define MAC_PCU_STA_ADDR_U16_PCF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PCF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK) +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB 19 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB 19 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK 0x00080000 +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) +#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB 18 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB 18 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK 0x00040000 +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) +#define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) +#define MAC_PCU_STA_ADDR_U16_ADHOC_MSB 17 +#define MAC_PCU_STA_ADDR_U16_ADHOC_LSB 17 +#define MAC_PCU_STA_ADDR_U16_ADHOC_MASK 0x00020000 +#define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB) +#define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) +#define MAC_PCU_STA_ADDR_U16_STA_AP_MSB 16 +#define MAC_PCU_STA_ADDR_U16_STA_AP_LSB 16 +#define MAC_PCU_STA_ADDR_U16_STA_AP_MASK 0x00010000 +#define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB) +#define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_STA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB 15 +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB 0 +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK 0x0000ffff +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) +#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) + +#define MAC_PCU_BSSID_L32_ADDRESS 0x00008008 +#define MAC_PCU_BSSID_L32_OFFSET 0x00000008 +#define MAC_PCU_BSSID_L32_ADDR_MSB 31 +#define MAC_PCU_BSSID_L32_ADDR_LSB 0 +#define MAC_PCU_BSSID_L32_ADDR_MASK 0xffffffff +#define MAC_PCU_BSSID_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID_L32_ADDR_MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB) +#define MAC_PCU_BSSID_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID_L32_ADDR_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK) + +#define MAC_PCU_BSSID_U16_ADDRESS 0x0000800c +#define MAC_PCU_BSSID_U16_OFFSET 0x0000000c +#define MAC_PCU_BSSID_U16_AID_MSB 26 +#define MAC_PCU_BSSID_U16_AID_LSB 16 +#define MAC_PCU_BSSID_U16_AID_MASK 0x07ff0000 +#define MAC_PCU_BSSID_U16_AID_GET(x) (((x) & MAC_PCU_BSSID_U16_AID_MASK) >> MAC_PCU_BSSID_U16_AID_LSB) +#define MAC_PCU_BSSID_U16_AID_SET(x) (((x) << MAC_PCU_BSSID_U16_AID_LSB) & MAC_PCU_BSSID_U16_AID_MASK) +#define MAC_PCU_BSSID_U16_ADDR_MSB 15 +#define MAC_PCU_BSSID_U16_ADDR_LSB 0 +#define MAC_PCU_BSSID_U16_ADDR_MASK 0x0000ffff +#define MAC_PCU_BSSID_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID_U16_ADDR_MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB) +#define MAC_PCU_BSSID_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID_U16_ADDR_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK) + +#define MAC_PCU_BCN_RSSI_AVE_ADDRESS 0x00008010 +#define MAC_PCU_BCN_RSSI_AVE_OFFSET 0x00000010 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB 11 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB 0 +#define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK 0x00000fff +#define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x) (((x) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) +#define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x) (((x) << MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) + +#define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS 0x00008014 +#define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET 0x00000014 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB 29 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB 16 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000 +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) +#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB 13 +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB 0 +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) +#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) + +#define MAC_PCU_BCN_RSSI_CTL_ADDRESS 0x00008018 +#define MAC_PCU_BCN_RSSI_CTL_OFFSET 0x00000018 +#define MAC_PCU_BCN_RSSI_CTL_RESET_MSB 29 +#define MAC_PCU_BCN_RSSI_CTL_RESET_LSB 29 +#define MAC_PCU_BCN_RSSI_CTL_RESET_MASK 0x20000000 +#define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB 28 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB 24 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK 0x1f000000 +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) +#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB 15 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB 8 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK 0x0000ff00 +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0 +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) +#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) + +#define MAC_PCU_USEC_LATENCY_ADDRESS 0x0000801c +#define MAC_PCU_USEC_LATENCY_OFFSET 0x0000001c +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB 28 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB 23 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK 0x1f800000 +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) +#define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB 22 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB 14 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK 0x007fc000 +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) +#define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) +#define MAC_PCU_USEC_LATENCY_USEC_MSB 7 +#define MAC_PCU_USEC_LATENCY_USEC_LSB 0 +#define MAC_PCU_USEC_LATENCY_USEC_MASK 0x000000ff +#define MAC_PCU_USEC_LATENCY_USEC_GET(x) (((x) & MAC_PCU_USEC_LATENCY_USEC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB) +#define MAC_PCU_USEC_LATENCY_USEC_SET(x) (((x) << MAC_PCU_USEC_LATENCY_USEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK) + +#define PCU_MAX_CFP_DUR_ADDRESS 0x00008020 +#define PCU_MAX_CFP_DUR_OFFSET 0x00000020 +#define PCU_MAX_CFP_DUR_VALUE_MSB 15 +#define PCU_MAX_CFP_DUR_VALUE_LSB 0 +#define PCU_MAX_CFP_DUR_VALUE_MASK 0x0000ffff +#define PCU_MAX_CFP_DUR_VALUE_GET(x) (((x) & PCU_MAX_CFP_DUR_VALUE_MASK) >> PCU_MAX_CFP_DUR_VALUE_LSB) +#define PCU_MAX_CFP_DUR_VALUE_SET(x) (((x) << PCU_MAX_CFP_DUR_VALUE_LSB) & PCU_MAX_CFP_DUR_VALUE_MASK) + +#define MAC_PCU_RX_FILTER_ADDRESS 0x00008024 +#define MAC_PCU_RX_FILTER_OFFSET 0x00000024 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB 25 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB 24 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK 0x03000000 +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) +#define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB 23 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB 18 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK 0x00fc0000 +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) +#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) +#define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB 17 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB 17 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK 0x00020000 +#define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x) (((x) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) +#define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x) (((x) << MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000 +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) +#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB 15 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB 15 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK 0x00008000 +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) +#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) +#define MAC_PCU_RX_FILTER_PS_POLL_MSB 14 +#define MAC_PCU_RX_FILTER_PS_POLL_LSB 14 +#define MAC_PCU_RX_FILTER_PS_POLL_MASK 0x00004000 +#define MAC_PCU_RX_FILTER_PS_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_PS_POLL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB) +#define MAC_PCU_RX_FILTER_PS_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_PS_POLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK) +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB 13 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB 13 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK 0x00002000 +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x) (((x) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) +#define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x) (((x) << MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000 +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) +#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB 11 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB 11 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK 0x00000800 +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) +#define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB 10 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB 10 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK 0x00000400 +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) +#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) +#define MAC_PCU_RX_FILTER_MY_BEACON_MSB 9 +#define MAC_PCU_RX_FILTER_MY_BEACON_LSB 9 +#define MAC_PCU_RX_FILTER_MY_BEACON_MASK 0x00000200 +#define MAC_PCU_RX_FILTER_MY_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB) +#define MAC_PCU_RX_FILTER_MY_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_MY_BEACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) +#define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB 8 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB 8 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK 0x00000100 +#define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x) (((x) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) +#define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x) (((x) << MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) +#define MAC_PCU_RX_FILTER_PROBE_REQ_MSB 7 +#define MAC_PCU_RX_FILTER_PROBE_REQ_LSB 7 +#define MAC_PCU_RX_FILTER_PROBE_REQ_MASK 0x00000080 +#define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x) (((x) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB) +#define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x) (((x) << MAC_PCU_RX_FILTER_PROBE_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) +#define MAC_PCU_RX_FILTER_XR_POLL_MSB 6 +#define MAC_PCU_RX_FILTER_XR_POLL_LSB 6 +#define MAC_PCU_RX_FILTER_XR_POLL_MASK 0x00000040 +#define MAC_PCU_RX_FILTER_XR_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_XR_POLL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB) +#define MAC_PCU_RX_FILTER_XR_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_XR_POLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK) +#define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB 5 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB 5 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK 0x00000020 +#define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x) (((x) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) +#define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x) (((x) << MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) +#define MAC_PCU_RX_FILTER_BEACON_MSB 4 +#define MAC_PCU_RX_FILTER_BEACON_LSB 4 +#define MAC_PCU_RX_FILTER_BEACON_MASK 0x00000010 +#define MAC_PCU_RX_FILTER_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_BEACON_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB) +#define MAC_PCU_RX_FILTER_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_BEACON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK) +#define MAC_PCU_RX_FILTER_CONTROL_MSB 3 +#define MAC_PCU_RX_FILTER_CONTROL_LSB 3 +#define MAC_PCU_RX_FILTER_CONTROL_MASK 0x00000008 +#define MAC_PCU_RX_FILTER_CONTROL_GET(x) (((x) & MAC_PCU_RX_FILTER_CONTROL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB) +#define MAC_PCU_RX_FILTER_CONTROL_SET(x) (((x) << MAC_PCU_RX_FILTER_CONTROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK) +#define MAC_PCU_RX_FILTER_BROADCAST_MSB 2 +#define MAC_PCU_RX_FILTER_BROADCAST_LSB 2 +#define MAC_PCU_RX_FILTER_BROADCAST_MASK 0x00000004 +#define MAC_PCU_RX_FILTER_BROADCAST_GET(x) (((x) & MAC_PCU_RX_FILTER_BROADCAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB) +#define MAC_PCU_RX_FILTER_BROADCAST_SET(x) (((x) << MAC_PCU_RX_FILTER_BROADCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK) +#define MAC_PCU_RX_FILTER_MULTICAST_MSB 1 +#define MAC_PCU_RX_FILTER_MULTICAST_LSB 1 +#define MAC_PCU_RX_FILTER_MULTICAST_MASK 0x00000002 +#define MAC_PCU_RX_FILTER_MULTICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_MULTICAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB) +#define MAC_PCU_RX_FILTER_MULTICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_MULTICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK) +#define MAC_PCU_RX_FILTER_UNICAST_MSB 0 +#define MAC_PCU_RX_FILTER_UNICAST_LSB 0 +#define MAC_PCU_RX_FILTER_UNICAST_MASK 0x00000001 +#define MAC_PCU_RX_FILTER_UNICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_UNICAST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB) +#define MAC_PCU_RX_FILTER_UNICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_UNICAST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK) + +#define MAC_PCU_MCAST_FILTER_L32_ADDRESS 0x00008028 +#define MAC_PCU_MCAST_FILTER_L32_OFFSET 0x00000028 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB 31 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB 0 +#define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) +#define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) + +#define MAC_PCU_MCAST_FILTER_U32_ADDRESS 0x0000802c +#define MAC_PCU_MCAST_FILTER_U32_OFFSET 0x0000002c +#define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB 31 +#define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB 0 +#define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) +#define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) + +#define MAC_PCU_DIAG_SW_ADDRESS 0x00008030 +#define MAC_PCU_DIAG_SW_OFFSET 0x00000030 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB 31 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB 30 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK 0xc0000000 +#define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x) (((x) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) +#define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x) (((x) << MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB 29 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB 29 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK 0x20000000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB 28 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB 28 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK 0x10000000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) +#define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB 27 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB 27 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK 0x08000000 +#define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) +#define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB 26 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB 26 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK 0x04000000 +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) +#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB 25 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB 25 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK 0x02000000 +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x) (((x) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) +#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x) (((x) << MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000 +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) +#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000 +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) +#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB 22 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB 22 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK 0x00400000 +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) +#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) +#define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB 21 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB 21 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK 0x00200000 +#define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x) (((x) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) +#define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x) (((x) << MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB 20 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB 20 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK 0x00100000 +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) +#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB 19 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB 18 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK 0x000c0000 +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) +#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB 17 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB 17 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK 0x00020000 +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x) (((x) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) +#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x) (((x) << MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB 8 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB 8 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK 0x00000100 +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) +#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB 7 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB 7 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK 0x00000080 +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x) (((x) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) +#define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x) (((x) << MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) +#define MAC_PCU_DIAG_SW_LOOP_BACK_MSB 6 +#define MAC_PCU_DIAG_SW_LOOP_BACK_LSB 6 +#define MAC_PCU_DIAG_SW_LOOP_BACK_MASK 0x00000040 +#define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x) (((x) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB) +#define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x) (((x) << MAC_PCU_DIAG_SW_LOOP_BACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) +#define MAC_PCU_DIAG_SW_HALT_RX_MSB 5 +#define MAC_PCU_DIAG_SW_HALT_RX_LSB 5 +#define MAC_PCU_DIAG_SW_HALT_RX_MASK 0x00000020 +#define MAC_PCU_DIAG_SW_HALT_RX_GET(x) (((x) & MAC_PCU_DIAG_SW_HALT_RX_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB) +#define MAC_PCU_DIAG_SW_HALT_RX_SET(x) (((x) << MAC_PCU_DIAG_SW_HALT_RX_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK) +#define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB 4 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB 4 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK 0x00000010 +#define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) +#define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB 3 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB 3 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK 0x00000008 +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) +#define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) +#define MAC_PCU_DIAG_SW_NO_CTS_MSB 2 +#define MAC_PCU_DIAG_SW_NO_CTS_LSB 2 +#define MAC_PCU_DIAG_SW_NO_CTS_MASK 0x00000004 +#define MAC_PCU_DIAG_SW_NO_CTS_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_CTS_MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB) +#define MAC_PCU_DIAG_SW_NO_CTS_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_CTS_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK) +#define MAC_PCU_DIAG_SW_NO_ACK_MSB 1 +#define MAC_PCU_DIAG_SW_NO_ACK_LSB 1 +#define MAC_PCU_DIAG_SW_NO_ACK_MASK 0x00000002 +#define MAC_PCU_DIAG_SW_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB) +#define MAC_PCU_DIAG_SW_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ACK_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK) +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB 0 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB 0 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK 0x00000001 +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) +#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) + +#define MAC_PCU_TST_ADDAC_ADDRESS 0x00008034 +#define MAC_PCU_TST_ADDAC_OFFSET 0x00000034 +#define MAC_PCU_TST_ADDAC_TEST_ARM_MSB 20 +#define MAC_PCU_TST_ADDAC_TEST_ARM_LSB 20 +#define MAC_PCU_TST_ADDAC_TEST_ARM_MASK 0x00100000 +#define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB) +#define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB 19 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB 19 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK 0x00080000 +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) +#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) +#define MAC_PCU_TST_ADDAC_CONT_TEST_MSB 18 +#define MAC_PCU_TST_ADDAC_CONT_TEST_LSB 18 +#define MAC_PCU_TST_ADDAC_CONT_TEST_MASK 0x00040000 +#define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB) +#define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB 17 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB 17 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK 0x00020000 +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) +#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) +#define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB 16 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB 16 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK 0x00010000 +#define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) +#define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) +#define MAC_PCU_TST_ADDAC_UPPER_8B_MSB 14 +#define MAC_PCU_TST_ADDAC_UPPER_8B_LSB 14 +#define MAC_PCU_TST_ADDAC_UPPER_8B_MASK 0x00004000 +#define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x) (((x) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB) +#define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x) (((x) << MAC_PCU_TST_ADDAC_UPPER_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) +#define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB 13 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB 3 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK 0x00003ff8 +#define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) +#define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) +#define MAC_PCU_TST_ADDAC_LOOP_MSB 2 +#define MAC_PCU_TST_ADDAC_LOOP_LSB 2 +#define MAC_PCU_TST_ADDAC_LOOP_MASK 0x00000004 +#define MAC_PCU_TST_ADDAC_LOOP_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB) +#define MAC_PCU_TST_ADDAC_LOOP_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK) +#define MAC_PCU_TST_ADDAC_TESTMODE_MSB 1 +#define MAC_PCU_TST_ADDAC_TESTMODE_LSB 1 +#define MAC_PCU_TST_ADDAC_TESTMODE_MASK 0x00000002 +#define MAC_PCU_TST_ADDAC_TESTMODE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB) +#define MAC_PCU_TST_ADDAC_TESTMODE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TESTMODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) +#define MAC_PCU_TST_ADDAC_CONT_TX_MSB 0 +#define MAC_PCU_TST_ADDAC_CONT_TX_LSB 0 +#define MAC_PCU_TST_ADDAC_CONT_TX_MASK 0x00000001 +#define MAC_PCU_TST_ADDAC_CONT_TX_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB) +#define MAC_PCU_TST_ADDAC_CONT_TX_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) + +#define MAC_PCU_DEF_ANTENNA_ADDRESS 0x00008038 +#define MAC_PCU_DEF_ANTENNA_OFFSET 0x00000038 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000 +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) +#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB 24 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB 24 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK 0x01000000 +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) +#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) +#define MAC_PCU_DEF_ANTENNA_VALUE_MSB 23 +#define MAC_PCU_DEF_ANTENNA_VALUE_LSB 0 +#define MAC_PCU_DEF_ANTENNA_VALUE_MASK 0x00ffffff +#define MAC_PCU_DEF_ANTENNA_VALUE_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB) +#define MAC_PCU_DEF_ANTENNA_VALUE_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_VALUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) + +#define MAC_PCU_AES_MUTE_MASK_0_ADDRESS 0x0000803c +#define MAC_PCU_AES_MUTE_MASK_0_OFFSET 0x0000003c +#define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB 31 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB 16 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK 0xffff0000 +#define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) +#define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) +#define MAC_PCU_AES_MUTE_MASK_0_FC_MSB 15 +#define MAC_PCU_AES_MUTE_MASK_0_FC_LSB 0 +#define MAC_PCU_AES_MUTE_MASK_0_FC_MASK 0x0000ffff +#define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB) +#define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) + +#define MAC_PCU_AES_MUTE_MASK_1_ADDRESS 0x00008040 +#define MAC_PCU_AES_MUTE_MASK_1_OFFSET 0x00000040 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB 31 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB 16 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK 0xffff0000 +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) +#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB 15 +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB 0 +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK 0x0000ffff +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) +#define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) + +#define MAC_PCU_GATED_CLKS_ADDRESS 0x00008044 +#define MAC_PCU_GATED_CLKS_OFFSET 0x00000044 +#define MAC_PCU_GATED_CLKS_GATED_REG_MSB 3 +#define MAC_PCU_GATED_CLKS_GATED_REG_LSB 3 +#define MAC_PCU_GATED_CLKS_GATED_REG_MASK 0x00000008 +#define MAC_PCU_GATED_CLKS_GATED_REG_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB) +#define MAC_PCU_GATED_CLKS_GATED_REG_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) +#define MAC_PCU_GATED_CLKS_GATED_RX_MSB 2 +#define MAC_PCU_GATED_CLKS_GATED_RX_LSB 2 +#define MAC_PCU_GATED_CLKS_GATED_RX_MASK 0x00000004 +#define MAC_PCU_GATED_CLKS_GATED_RX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB) +#define MAC_PCU_GATED_CLKS_GATED_RX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) +#define MAC_PCU_GATED_CLKS_GATED_TX_MSB 1 +#define MAC_PCU_GATED_CLKS_GATED_TX_LSB 1 +#define MAC_PCU_GATED_CLKS_GATED_TX_MASK 0x00000002 +#define MAC_PCU_GATED_CLKS_GATED_TX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB) +#define MAC_PCU_GATED_CLKS_GATED_TX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) + +#define MAC_PCU_OBS_BUS_2_ADDRESS 0x00008048 +#define MAC_PCU_OBS_BUS_2_OFFSET 0x00000048 +#define MAC_PCU_OBS_BUS_2_VALUE_MSB 17 +#define MAC_PCU_OBS_BUS_2_VALUE_LSB 0 +#define MAC_PCU_OBS_BUS_2_VALUE_MASK 0x0003ffff +#define MAC_PCU_OBS_BUS_2_VALUE_GET(x) (((x) & MAC_PCU_OBS_BUS_2_VALUE_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB) +#define MAC_PCU_OBS_BUS_2_VALUE_SET(x) (((x) << MAC_PCU_OBS_BUS_2_VALUE_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK) + +#define MAC_PCU_OBS_BUS_1_ADDRESS 0x0000804c +#define MAC_PCU_OBS_BUS_1_OFFSET 0x0000004c +#define MAC_PCU_OBS_BUS_1_TX_STATE_MSB 30 +#define MAC_PCU_OBS_BUS_1_TX_STATE_LSB 25 +#define MAC_PCU_OBS_BUS_1_TX_STATE_MASK 0x7e000000 +#define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_STATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_RX_STATE_MSB 24 +#define MAC_PCU_OBS_BUS_1_RX_STATE_LSB 20 +#define MAC_PCU_OBS_BUS_1_RX_STATE_MASK 0x01f00000 +#define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_STATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB 17 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB 12 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK 0x0003f000 +#define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) +#define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB 11 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB 11 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK 0x00000800 +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) +#define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) +#define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB 10 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB 10 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK 0x00000400 +#define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) +#define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB 9 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB 9 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK 0x00000200 +#define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) +#define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB 8 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB 8 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK 0x00000100 +#define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) +#define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB 7 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB 7 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK 0x00000080 +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB 6 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB 6 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK 0x00000040 +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) +#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) +#define MAC_PCU_OBS_BUS_1_TX_HCF_MSB 5 +#define MAC_PCU_OBS_BUS_1_TX_HCF_LSB 5 +#define MAC_PCU_OBS_BUS_1_TX_HCF_MASK 0x00000020 +#define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB) +#define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HCF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB 4 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB 4 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK 0x00000010 +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x) (((x) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) +#define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x) (((x) << MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB 3 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB 3 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK 0x00000008 +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) +#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) +#define MAC_PCU_OBS_BUS_1_RX_WEP_MSB 2 +#define MAC_PCU_OBS_BUS_1_RX_WEP_LSB 2 +#define MAC_PCU_OBS_BUS_1_RX_WEP_MASK 0x00000004 +#define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB) +#define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_WEP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB 1 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB 1 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK 0x00000002 +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB 0 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB 0 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK 0x00000001 +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) +#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) + +#define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS 0x00008050 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET 0x00000050 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001 +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) +#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) + +#define MAC_PCU_LAST_BEACON_TSF_ADDRESS 0x00008054 +#define MAC_PCU_LAST_BEACON_TSF_OFFSET 0x00000054 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB 31 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB 0 +#define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK 0xffffffff +#define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x) (((x) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) +#define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x) (((x) << MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) + +#define MAC_PCU_NAV_ADDRESS 0x00008058 +#define MAC_PCU_NAV_OFFSET 0x00000058 +#define MAC_PCU_NAV_VALUE_MSB 25 +#define MAC_PCU_NAV_VALUE_LSB 0 +#define MAC_PCU_NAV_VALUE_MASK 0x03ffffff +#define MAC_PCU_NAV_VALUE_GET(x) (((x) & MAC_PCU_NAV_VALUE_MASK) >> MAC_PCU_NAV_VALUE_LSB) +#define MAC_PCU_NAV_VALUE_SET(x) (((x) << MAC_PCU_NAV_VALUE_LSB) & MAC_PCU_NAV_VALUE_MASK) + +#define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS 0x0000805c +#define MAC_PCU_RTS_SUCCESS_CNT_OFFSET 0x0000005c +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB 15 +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB 0 +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) +#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) + +#define MAC_PCU_RTS_FAIL_CNT_ADDRESS 0x00008060 +#define MAC_PCU_RTS_FAIL_CNT_OFFSET 0x00000060 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_ACK_FAIL_CNT_ADDRESS 0x00008064 +#define MAC_PCU_ACK_FAIL_CNT_OFFSET 0x00000064 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_FCS_FAIL_CNT_ADDRESS 0x00008068 +#define MAC_PCU_FCS_FAIL_CNT_OFFSET 0x00000068 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB 15 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB 0 +#define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) +#define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) + +#define MAC_PCU_BEACON_CNT_ADDRESS 0x0000806c +#define MAC_PCU_BEACON_CNT_OFFSET 0x0000006c +#define MAC_PCU_BEACON_CNT_VALUE_MSB 15 +#define MAC_PCU_BEACON_CNT_VALUE_LSB 0 +#define MAC_PCU_BEACON_CNT_VALUE_MASK 0x0000ffff +#define MAC_PCU_BEACON_CNT_VALUE_GET(x) (((x) & MAC_PCU_BEACON_CNT_VALUE_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB) +#define MAC_PCU_BEACON_CNT_VALUE_SET(x) (((x) << MAC_PCU_BEACON_CNT_VALUE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK) + +#define MAC_PCU_XRMODE_ADDRESS 0x00008070 +#define MAC_PCU_XRMODE_OFFSET 0x00000070 +#define MAC_PCU_XRMODE_FRAME_HOLD_MSB 31 +#define MAC_PCU_XRMODE_FRAME_HOLD_LSB 20 +#define MAC_PCU_XRMODE_FRAME_HOLD_MASK 0xfff00000 +#define MAC_PCU_XRMODE_FRAME_HOLD_GET(x) (((x) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB) +#define MAC_PCU_XRMODE_FRAME_HOLD_SET(x) (((x) << MAC_PCU_XRMODE_FRAME_HOLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB 7 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB 7 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK 0x00000080 +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x) (((x) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) +#define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x) (((x) << MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) +#define MAC_PCU_XRMODE_POLL_TYPE_MSB 5 +#define MAC_PCU_XRMODE_POLL_TYPE_LSB 0 +#define MAC_PCU_XRMODE_POLL_TYPE_MASK 0x0000003f +#define MAC_PCU_XRMODE_POLL_TYPE_GET(x) (((x) & MAC_PCU_XRMODE_POLL_TYPE_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB) +#define MAC_PCU_XRMODE_POLL_TYPE_SET(x) (((x) << MAC_PCU_XRMODE_POLL_TYPE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK) + +#define MAC_PCU_XRDEL_ADDRESS 0x00008074 +#define MAC_PCU_XRDEL_OFFSET 0x00000074 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB 31 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB 16 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK 0xffff0000 +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) +#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) +#define MAC_PCU_XRDEL_SLOT_DELAY_MSB 15 +#define MAC_PCU_XRDEL_SLOT_DELAY_LSB 0 +#define MAC_PCU_XRDEL_SLOT_DELAY_MASK 0x0000ffff +#define MAC_PCU_XRDEL_SLOT_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB) +#define MAC_PCU_XRDEL_SLOT_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_SLOT_DELAY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) + +#define MAC_PCU_XRTO_ADDRESS 0x00008078 +#define MAC_PCU_XRTO_OFFSET 0x00000078 +#define MAC_PCU_XRTO_POLL_TIMEOUT_MSB 31 +#define MAC_PCU_XRTO_POLL_TIMEOUT_LSB 16 +#define MAC_PCU_XRTO_POLL_TIMEOUT_MASK 0xffff0000 +#define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB) +#define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_POLL_TIMEOUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB 15 +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB 0 +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) +#define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) + +#define MAC_PCU_XRCRP_ADDRESS 0x0000807c +#define MAC_PCU_XRCRP_OFFSET 0x0000007c +#define MAC_PCU_XRCRP_CHIRP_GAP_MSB 31 +#define MAC_PCU_XRCRP_CHIRP_GAP_LSB 16 +#define MAC_PCU_XRCRP_CHIRP_GAP_MASK 0xffff0000 +#define MAC_PCU_XRCRP_CHIRP_GAP_GET(x) (((x) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB) +#define MAC_PCU_XRCRP_CHIRP_GAP_SET(x) (((x) << MAC_PCU_XRCRP_CHIRP_GAP_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) +#define MAC_PCU_XRCRP_SEND_CHIRP_MSB 0 +#define MAC_PCU_XRCRP_SEND_CHIRP_LSB 0 +#define MAC_PCU_XRCRP_SEND_CHIRP_MASK 0x00000001 +#define MAC_PCU_XRCRP_SEND_CHIRP_GET(x) (((x) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB) +#define MAC_PCU_XRCRP_SEND_CHIRP_SET(x) (((x) << MAC_PCU_XRCRP_SEND_CHIRP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) + +#define MAC_PCU_XRSTMP_ADDRESS 0x00008080 +#define MAC_PCU_XRSTMP_OFFSET 0x00000080 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB 23 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB 16 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB 15 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB 8 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB 5 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB 5 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK 0x00000020 +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB 4 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB 4 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK 0x00000010 +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB 3 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB 3 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK 0x00000008 +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB 2 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB 2 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK 0x00000004 +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) +#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB 1 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB 1 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK 0x00000002 +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB 0 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB 0 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK 0x00000001 +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) +#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) + +#define MAC_PCU_ADDR1_MASK_L32_ADDRESS 0x00008084 +#define MAC_PCU_ADDR1_MASK_L32_OFFSET 0x00000084 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB 31 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB 0 +#define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) +#define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) + +#define MAC_PCU_ADDR1_MASK_U16_ADDRESS 0x00008088 +#define MAC_PCU_ADDR1_MASK_U16_OFFSET 0x00000088 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB 15 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB 0 +#define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK 0x0000ffff +#define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) +#define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) + +#define MAC_PCU_TPC_ADDRESS 0x0000808c +#define MAC_PCU_TPC_OFFSET 0x0000008c +#define MAC_PCU_TPC_CHIRP_PWR_MSB 21 +#define MAC_PCU_TPC_CHIRP_PWR_LSB 16 +#define MAC_PCU_TPC_CHIRP_PWR_MASK 0x003f0000 +#define MAC_PCU_TPC_CHIRP_PWR_GET(x) (((x) & MAC_PCU_TPC_CHIRP_PWR_MASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB) +#define MAC_PCU_TPC_CHIRP_PWR_SET(x) (((x) << MAC_PCU_TPC_CHIRP_PWR_LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK) +#define MAC_PCU_TPC_CTS_PWR_MSB 13 +#define MAC_PCU_TPC_CTS_PWR_LSB 8 +#define MAC_PCU_TPC_CTS_PWR_MASK 0x00003f00 +#define MAC_PCU_TPC_CTS_PWR_GET(x) (((x) & MAC_PCU_TPC_CTS_PWR_MASK) >> MAC_PCU_TPC_CTS_PWR_LSB) +#define MAC_PCU_TPC_CTS_PWR_SET(x) (((x) << MAC_PCU_TPC_CTS_PWR_LSB) & MAC_PCU_TPC_CTS_PWR_MASK) +#define MAC_PCU_TPC_ACK_PWR_MSB 5 +#define MAC_PCU_TPC_ACK_PWR_LSB 0 +#define MAC_PCU_TPC_ACK_PWR_MASK 0x0000003f +#define MAC_PCU_TPC_ACK_PWR_GET(x) (((x) & MAC_PCU_TPC_ACK_PWR_MASK) >> MAC_PCU_TPC_ACK_PWR_LSB) +#define MAC_PCU_TPC_ACK_PWR_SET(x) (((x) << MAC_PCU_TPC_ACK_PWR_LSB) & MAC_PCU_TPC_ACK_PWR_MASK) + +#define MAC_PCU_TX_FRAME_CNT_ADDRESS 0x00008090 +#define MAC_PCU_TX_FRAME_CNT_OFFSET 0x00000090 +#define MAC_PCU_TX_FRAME_CNT_VALUE_MSB 31 +#define MAC_PCU_TX_FRAME_CNT_VALUE_LSB 0 +#define MAC_PCU_TX_FRAME_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB) +#define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_TX_FRAME_CNT_VALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) + +#define MAC_PCU_RX_FRAME_CNT_ADDRESS 0x00008094 +#define MAC_PCU_RX_FRAME_CNT_OFFSET 0x00000094 +#define MAC_PCU_RX_FRAME_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_FRAME_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_FRAME_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB) +#define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_FRAME_CNT_VALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) + +#define MAC_PCU_RX_CLEAR_CNT_ADDRESS 0x00008098 +#define MAC_PCU_RX_CLEAR_CNT_OFFSET 0x00000098 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) +#define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) + +#define MAC_PCU_CYCLE_CNT_ADDRESS 0x0000809c +#define MAC_PCU_CYCLE_CNT_OFFSET 0x0000009c +#define MAC_PCU_CYCLE_CNT_VALUE_MSB 31 +#define MAC_PCU_CYCLE_CNT_VALUE_LSB 0 +#define MAC_PCU_CYCLE_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_CYCLE_CNT_VALUE_GET(x) (((x) & MAC_PCU_CYCLE_CNT_VALUE_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB) +#define MAC_PCU_CYCLE_CNT_VALUE_SET(x) (((x) << MAC_PCU_CYCLE_CNT_VALUE_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK) + +#define MAC_PCU_QUIET_TIME_1_ADDRESS 0x000080a0 +#define MAC_PCU_QUIET_TIME_1_OFFSET 0x000000a0 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB 17 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB 17 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000 +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) +#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) + +#define MAC_PCU_QUIET_TIME_2_ADDRESS 0x000080a4 +#define MAC_PCU_QUIET_TIME_2_OFFSET 0x000000a4 +#define MAC_PCU_QUIET_TIME_2_DURATION_MSB 31 +#define MAC_PCU_QUIET_TIME_2_DURATION_LSB 16 +#define MAC_PCU_QUIET_TIME_2_DURATION_MASK 0xffff0000 +#define MAC_PCU_QUIET_TIME_2_DURATION_GET(x) (((x) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB) +#define MAC_PCU_QUIET_TIME_2_DURATION_SET(x) (((x) << MAC_PCU_QUIET_TIME_2_DURATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) + +#define MAC_PCU_QOS_NO_ACK_ADDRESS 0x000080a8 +#define MAC_PCU_QOS_NO_ACK_OFFSET 0x000000a8 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB 8 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB 7 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK 0x00000180 +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) +#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB 6 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB 4 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK 0x00000070 +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) +#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB 3 +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB 0 +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK 0x0000000f +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) +#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) + +#define MAC_PCU_PHY_ERROR_MASK_ADDRESS 0x000080ac +#define MAC_PCU_PHY_ERROR_MASK_OFFSET 0x000000ac +#define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) + +#define MAC_PCU_XRLAT_ADDRESS 0x000080b0 +#define MAC_PCU_XRLAT_OFFSET 0x000000b0 +#define MAC_PCU_XRLAT_VALUE_MSB 11 +#define MAC_PCU_XRLAT_VALUE_LSB 0 +#define MAC_PCU_XRLAT_VALUE_MASK 0x00000fff +#define MAC_PCU_XRLAT_VALUE_GET(x) (((x) & MAC_PCU_XRLAT_VALUE_MASK) >> MAC_PCU_XRLAT_VALUE_LSB) +#define MAC_PCU_XRLAT_VALUE_SET(x) (((x) << MAC_PCU_XRLAT_VALUE_LSB) & MAC_PCU_XRLAT_VALUE_MASK) + +#define MAC_PCU_RXBUF_ADDRESS 0x000080b4 +#define MAC_PCU_RXBUF_OFFSET 0x000000b4 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB 11 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB 11 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK 0x00000800 +#define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x) (((x) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) +#define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x) (((x) << MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB 10 +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB 0 +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK 0x000007ff +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) +#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) + +#define MAC_PCU_MIC_QOS_CONTROL_ADDRESS 0x000080b8 +#define MAC_PCU_MIC_QOS_CONTROL_OFFSET 0x000000b8 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB 16 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB 16 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK 0x00010000 +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB 15 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB 14 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK 0x0000c000 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB 13 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB 12 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK 0x00003000 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB 11 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB 10 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK 0x00000c00 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB 9 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB 8 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK 0x00000300 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB 7 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB 6 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK 0x000000c0 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB 5 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB 4 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK 0x00000030 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB 3 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB 2 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK 0x0000000c +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB 1 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB 0 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK 0x00000003 +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) +#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) + +#define MAC_PCU_MIC_QOS_SELECT_ADDRESS 0x000080bc +#define MAC_PCU_MIC_QOS_SELECT_OFFSET 0x000000bc +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB 31 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB 28 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK 0xf0000000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB 27 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB 24 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK 0x0f000000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB 23 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB 20 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK 0x00f00000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB 19 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB 16 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK 0x000f0000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB 15 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB 12 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK 0x0000f000 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB 11 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB 8 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK 0x00000f00 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB 7 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB 4 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK 0x000000f0 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB 3 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB 0 +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK 0x0000000f +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) +#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) + +#define MAC_PCU_MISC_MODE_ADDRESS 0x000080c0 +#define MAC_PCU_MISC_MODE_OFFSET 0x000000c0 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB 31 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB 30 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK 0xc0000000 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000 +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) +#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000 +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) +#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) +#define MAC_PCU_MISC_MODE_SEL_EVM_MSB 27 +#define MAC_PCU_MISC_MODE_SEL_EVM_LSB 27 +#define MAC_PCU_MISC_MODE_SEL_EVM_MASK 0x08000000 +#define MAC_PCU_MISC_MODE_SEL_EVM_GET(x) (((x) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB) +#define MAC_PCU_MISC_MODE_SEL_EVM_SET(x) (((x) << MAC_PCU_MISC_MODE_SEL_EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB 26 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB 26 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK 0x04000000 +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB 25 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB 25 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK 0x02000000 +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) +#define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB 24 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB 24 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK 0x01000000 +#define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) +#define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000 +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000 +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) +#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB 21 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB 21 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK 0x00200000 +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x) (((x) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) +#define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x) (((x) << MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000 +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) +#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000 +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) +#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000 +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) +#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000 +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB 11 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB 11 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK 0x00000800 +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) +#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB 10 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB 10 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK 0x00000400 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB 4 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB 4 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK 0x00000010 +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) +#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB 3 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB 3 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK 0x00000008 +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x) (((x) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) +#define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x) (((x) << MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004 +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) +#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB 1 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB 1 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK 0x00000002 +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) +#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB 0 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB 0 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001 +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) +#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) + +#define MAC_PCU_FILTER_OFDM_CNT_ADDRESS 0x000080c4 +#define MAC_PCU_FILTER_OFDM_CNT_OFFSET 0x000000c4 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB 23 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB 0 +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK 0x00ffffff +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) +#define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) + +#define MAC_PCU_FILTER_CCK_CNT_ADDRESS 0x000080c8 +#define MAC_PCU_FILTER_CCK_CNT_OFFSET 0x000000c8 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB 23 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB 0 +#define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK 0x00ffffff +#define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) +#define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_1_ADDRESS 0x000080cc +#define MAC_PCU_PHY_ERR_CNT_1_OFFSET 0x000000cc +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS 0x000080d0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET 0x000000d0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_2_ADDRESS 0x000080d4 +#define MAC_PCU_PHY_ERR_CNT_2_OFFSET 0x000000d4 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS 0x000080d8 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET 0x000000d8 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) + +#define MAC_PCU_TSF_THRESHOLD_ADDRESS 0x000080dc +#define MAC_PCU_TSF_THRESHOLD_OFFSET 0x000000dc +#define MAC_PCU_TSF_THRESHOLD_VALUE_MSB 15 +#define MAC_PCU_TSF_THRESHOLD_VALUE_LSB 0 +#define MAC_PCU_TSF_THRESHOLD_VALUE_MASK 0x0000ffff +#define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x) (((x) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB) +#define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x) (((x) << MAC_PCU_TSF_THRESHOLD_VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) + +#define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS 0x000080e0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET 0x000000e0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_3_ADDRESS 0x000080e4 +#define MAC_PCU_PHY_ERR_CNT_3_OFFSET 0x000000e4 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK 0x00ffffff +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) + +#define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS 0x000080e8 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET 0x000000e8 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB 31 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK 0xffffffff +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_MODE_ADDRESS 0x000080ec +#define MAC_PCU_BLUETOOTH_MODE_OFFSET 0x000000ec +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000 +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000 +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000 +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) +#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB 16 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB 13 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK 0x0001e000 +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) +#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) +#define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB 12 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB 12 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK 0x00001000 +#define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) +#define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) +#define MAC_PCU_BLUETOOTH_MODE_MODE_MSB 11 +#define MAC_PCU_BLUETOOTH_MODE_MODE_LSB 10 +#define MAC_PCU_BLUETOOTH_MODE_MODE_MASK 0x00000c00 +#define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB) +#define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200 +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100 +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) + +#define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS 0x000080f0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET 0x000000f0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB 31 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB 16 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB 15 +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB 0 +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) + +#define MAC_PCU_BLUETOOTH_MODE2_ADDRESS 0x000080f4 +#define MAC_PCU_BLUETOOTH_MODE2_OFFSET 0x000000f4 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000 +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000 +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000 +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000 +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000 +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000 +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000 +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000 +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000 +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000 +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000 +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) +#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) + +#define MAC_PCU_TXSIFS_ADDRESS 0x000080f8 +#define MAC_PCU_TXSIFS_OFFSET 0x000000f8 +#define MAC_PCU_TXSIFS_ACK_SHIFT_MSB 14 +#define MAC_PCU_TXSIFS_ACK_SHIFT_LSB 12 +#define MAC_PCU_TXSIFS_ACK_SHIFT_MASK 0x00007000 +#define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x) (((x) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB) +#define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x) (((x) << MAC_PCU_TXSIFS_ACK_SHIFT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) +#define MAC_PCU_TXSIFS_TX_LATENCY_MSB 11 +#define MAC_PCU_TXSIFS_TX_LATENCY_LSB 8 +#define MAC_PCU_TXSIFS_TX_LATENCY_MASK 0x00000f00 +#define MAC_PCU_TXSIFS_TX_LATENCY_GET(x) (((x) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB) +#define MAC_PCU_TXSIFS_TX_LATENCY_SET(x) (((x) << MAC_PCU_TXSIFS_TX_LATENCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) +#define MAC_PCU_TXSIFS_SIFS_TIME_MSB 7 +#define MAC_PCU_TXSIFS_SIFS_TIME_LSB 0 +#define MAC_PCU_TXSIFS_SIFS_TIME_MASK 0x000000ff +#define MAC_PCU_TXSIFS_SIFS_TIME_GET(x) (((x) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB) +#define MAC_PCU_TXSIFS_SIFS_TIME_SET(x) (((x) << MAC_PCU_TXSIFS_SIFS_TIME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) + +#define MAC_PCU_TXOP_X_ADDRESS 0x000080fc +#define MAC_PCU_TXOP_X_OFFSET 0x000000fc +#define MAC_PCU_TXOP_X_VALUE_MSB 7 +#define MAC_PCU_TXOP_X_VALUE_LSB 0 +#define MAC_PCU_TXOP_X_VALUE_MASK 0x000000ff +#define MAC_PCU_TXOP_X_VALUE_GET(x) (((x) & MAC_PCU_TXOP_X_VALUE_MASK) >> MAC_PCU_TXOP_X_VALUE_LSB) +#define MAC_PCU_TXOP_X_VALUE_SET(x) (((x) << MAC_PCU_TXOP_X_VALUE_LSB) & MAC_PCU_TXOP_X_VALUE_MASK) + +#define MAC_PCU_TXOP_0_3_ADDRESS 0x00008100 +#define MAC_PCU_TXOP_0_3_OFFSET 0x00000100 +#define MAC_PCU_TXOP_0_3_VALUE_3_MSB 31 +#define MAC_PCU_TXOP_0_3_VALUE_3_LSB 24 +#define MAC_PCU_TXOP_0_3_VALUE_3_MASK 0xff000000 +#define MAC_PCU_TXOP_0_3_VALUE_3_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_3_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_2_MSB 23 +#define MAC_PCU_TXOP_0_3_VALUE_2_LSB 16 +#define MAC_PCU_TXOP_0_3_VALUE_2_MASK 0x00ff0000 +#define MAC_PCU_TXOP_0_3_VALUE_2_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_2_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_1_MSB 15 +#define MAC_PCU_TXOP_0_3_VALUE_1_LSB 8 +#define MAC_PCU_TXOP_0_3_VALUE_1_MASK 0x0000ff00 +#define MAC_PCU_TXOP_0_3_VALUE_1_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_1_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) +#define MAC_PCU_TXOP_0_3_VALUE_0_MSB 7 +#define MAC_PCU_TXOP_0_3_VALUE_0_LSB 0 +#define MAC_PCU_TXOP_0_3_VALUE_0_MASK 0x000000ff +#define MAC_PCU_TXOP_0_3_VALUE_0_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB) +#define MAC_PCU_TXOP_0_3_VALUE_0_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) + +#define MAC_PCU_TXOP_4_7_ADDRESS 0x00008104 +#define MAC_PCU_TXOP_4_7_OFFSET 0x00000104 +#define MAC_PCU_TXOP_4_7_VALUE_7_MSB 31 +#define MAC_PCU_TXOP_4_7_VALUE_7_LSB 24 +#define MAC_PCU_TXOP_4_7_VALUE_7_MASK 0xff000000 +#define MAC_PCU_TXOP_4_7_VALUE_7_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_7_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_6_MSB 23 +#define MAC_PCU_TXOP_4_7_VALUE_6_LSB 16 +#define MAC_PCU_TXOP_4_7_VALUE_6_MASK 0x00ff0000 +#define MAC_PCU_TXOP_4_7_VALUE_6_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_6_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_5_MSB 15 +#define MAC_PCU_TXOP_4_7_VALUE_5_LSB 8 +#define MAC_PCU_TXOP_4_7_VALUE_5_MASK 0x0000ff00 +#define MAC_PCU_TXOP_4_7_VALUE_5_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_5_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) +#define MAC_PCU_TXOP_4_7_VALUE_4_MSB 7 +#define MAC_PCU_TXOP_4_7_VALUE_4_LSB 0 +#define MAC_PCU_TXOP_4_7_VALUE_4_MASK 0x000000ff +#define MAC_PCU_TXOP_4_7_VALUE_4_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB) +#define MAC_PCU_TXOP_4_7_VALUE_4_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) + +#define MAC_PCU_TXOP_8_11_ADDRESS 0x00008108 +#define MAC_PCU_TXOP_8_11_OFFSET 0x00000108 +#define MAC_PCU_TXOP_8_11_VALUE_11_MSB 31 +#define MAC_PCU_TXOP_8_11_VALUE_11_LSB 24 +#define MAC_PCU_TXOP_8_11_VALUE_11_MASK 0xff000000 +#define MAC_PCU_TXOP_8_11_VALUE_11_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_11_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_10_MSB 23 +#define MAC_PCU_TXOP_8_11_VALUE_10_LSB 16 +#define MAC_PCU_TXOP_8_11_VALUE_10_MASK 0x00ff0000 +#define MAC_PCU_TXOP_8_11_VALUE_10_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_10_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_9_MSB 15 +#define MAC_PCU_TXOP_8_11_VALUE_9_LSB 8 +#define MAC_PCU_TXOP_8_11_VALUE_9_MASK 0x0000ff00 +#define MAC_PCU_TXOP_8_11_VALUE_9_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_9_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) +#define MAC_PCU_TXOP_8_11_VALUE_8_MSB 7 +#define MAC_PCU_TXOP_8_11_VALUE_8_LSB 0 +#define MAC_PCU_TXOP_8_11_VALUE_8_MASK 0x000000ff +#define MAC_PCU_TXOP_8_11_VALUE_8_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB) +#define MAC_PCU_TXOP_8_11_VALUE_8_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) + +#define MAC_PCU_TXOP_12_15_ADDRESS 0x0000810c +#define MAC_PCU_TXOP_12_15_OFFSET 0x0000010c +#define MAC_PCU_TXOP_12_15_VALUE_15_MSB 31 +#define MAC_PCU_TXOP_12_15_VALUE_15_LSB 24 +#define MAC_PCU_TXOP_12_15_VALUE_15_MASK 0xff000000 +#define MAC_PCU_TXOP_12_15_VALUE_15_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_15_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_14_MSB 23 +#define MAC_PCU_TXOP_12_15_VALUE_14_LSB 16 +#define MAC_PCU_TXOP_12_15_VALUE_14_MASK 0x00ff0000 +#define MAC_PCU_TXOP_12_15_VALUE_14_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_14_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_13_MSB 15 +#define MAC_PCU_TXOP_12_15_VALUE_13_LSB 8 +#define MAC_PCU_TXOP_12_15_VALUE_13_MASK 0x0000ff00 +#define MAC_PCU_TXOP_12_15_VALUE_13_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_13_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) +#define MAC_PCU_TXOP_12_15_VALUE_12_MSB 7 +#define MAC_PCU_TXOP_12_15_VALUE_12_LSB 0 +#define MAC_PCU_TXOP_12_15_VALUE_12_MASK 0x000000ff +#define MAC_PCU_TXOP_12_15_VALUE_12_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB) +#define MAC_PCU_TXOP_12_15_VALUE_12_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_ADDRESS 0x00008110 +#define MAC_PCU_LOGIC_ANALYZER_OFFSET 0x00000110 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB 31 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB 18 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK 0xfffc0000 +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB 17 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB 8 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK 0x0003ff00 +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) +#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB 7 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB 4 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK 0x000000f0 +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) +#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB 3 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB 3 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK 0x00000008 +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_STATE_MSB 2 +#define MAC_PCU_LOGIC_ANALYZER_STATE_LSB 2 +#define MAC_PCU_LOGIC_ANALYZER_STATE_MASK 0x00000004 +#define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB) +#define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB 1 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB 1 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK 0x00000002 +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) +#define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) +#define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB 0 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK 0x00000001 +#define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) +#define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS 0x00008114 +#define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET 0x00000114 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB 31 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK 0xffffffff +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) +#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) + +#define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS 0x00008118 +#define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET 0x00000118 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB 15 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB 0 +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK 0x0000ffff +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) +#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) + +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS 0x0000811c +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET 0x0000011c +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB 23 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB 16 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB 15 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB 8 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB 7 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB 0 +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) +#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) + +#define MAC_PCU_AZIMUTH_MODE_ADDRESS 0x00008120 +#define MAC_PCU_AZIMUTH_MODE_OFFSET 0x00000120 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB 7 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB 7 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK 0x00000080 +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) +#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040 +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) +#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB 5 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB 5 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK 0x00000020 +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) +#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB 4 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB 4 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK 0x00000010 +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) +#define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008 +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) +#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004 +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) +#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB 1 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB 1 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002 +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) +#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001 +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) +#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) + +#define MAC_PCU_20_40_MODE_ADDRESS 0x00008124 +#define MAC_PCU_20_40_MODE_OFFSET 0x00000124 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB 15 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB 4 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK 0x0000fff0 +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x) (((x) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) +#define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x) (((x) << MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008 +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) +#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004 +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) +#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB 1 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB 1 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK 0x00000002 +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) +#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB 0 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB 0 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK 0x00000001 +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) +#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) + +#define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS 0x00008128 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET 0x00000128 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB 31 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB 0 +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK 0xffffffff +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) +#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) + +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS 0x0000812c +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET 0x0000012c +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB 2 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB 0 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007 +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) +#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) + +#define MAC_PCU_BA_BAR_CONTROL_ADDRESS 0x00008130 +#define MAC_PCU_BA_BAR_CONTROL_OFFSET 0x00000130 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000 +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) +#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800 +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) +#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400 +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) +#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0 +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) +#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0 +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) +#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) + +#define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS 0x00008134 +#define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET 0x00000134 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00 +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) +#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7 +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0 +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) +#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) + +#define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS 0x00008138 +#define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET 0x00000138 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000 +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7 +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0 +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) +#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) + +#define MAC_PCU_TX_TIMER_ADDRESS 0x0000813c +#define MAC_PCU_TX_TIMER_OFFSET 0x0000013c +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB 25 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB 25 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB 24 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB 20 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK 0x01f00000 +#define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) +#define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) +#define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB 19 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB 16 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK 0x000f0000 +#define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) +#define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB 15 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB 15 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK 0x00008000 +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) +#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) +#define MAC_PCU_TX_TIMER_TX_TIMER_MSB 14 +#define MAC_PCU_TX_TIMER_TX_TIMER_LSB 0 +#define MAC_PCU_TX_TIMER_TX_TIMER_MASK 0x00007fff +#define MAC_PCU_TX_TIMER_TX_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB) +#define MAC_PCU_TX_TIMER_TX_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) + +#define MAC_PCU_TXBUF_CTRL_ADDRESS 0x00008140 +#define MAC_PCU_TXBUF_CTRL_OFFSET 0x00000140 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000 +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) +#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB 11 +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB 0 +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK 0x00000fff +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) +#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) + +#define MAC_PCU_MISC_MODE2_ADDRESS 0x00008144 +#define MAC_PCU_MISC_MODE2_OFFSET 0x00000144 +#define MAC_PCU_MISC_MODE2_RESERVED_1_MSB 31 +#define MAC_PCU_MISC_MODE2_RESERVED_1_LSB 28 +#define MAC_PCU_MISC_MODE2_RESERVED_1_MASK 0xf0000000 +#define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000 +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) +#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000 +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) +#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB 24 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB 24 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000 +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) +#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000 +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) +#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB 21 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB 21 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK 0x00200000 +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) +#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) +#define MAC_PCU_MISC_MODE2_BUG_28676_MSB 20 +#define MAC_PCU_MISC_MODE2_BUG_28676_LSB 20 +#define MAC_PCU_MISC_MODE2_BUG_28676_MASK 0x00100000 +#define MAC_PCU_MISC_MODE2_BUG_28676_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB) +#define MAC_PCU_MISC_MODE2_BUG_28676_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000 +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) +#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB 18 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB 18 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK 0x00040000 +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) +#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) +#define MAC_PCU_MISC_MODE2_AGG_WEP_MSB 17 +#define MAC_PCU_MISC_MODE2_AGG_WEP_LSB 17 +#define MAC_PCU_MISC_MODE2_AGG_WEP_MASK 0x00020000 +#define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x) (((x) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB) +#define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x) (((x) << MAC_PCU_MISC_MODE2_AGG_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000 +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) +#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) +#define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB 15 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB 8 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK 0x0000ff00 +#define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) +#define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB 7 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB 7 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK 0x00000080 +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x) (((x) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) +#define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x) (((x) << MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040 +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_RESERVED_2_MSB 5 +#define MAC_PCU_MISC_MODE2_RESERVED_2_LSB 5 +#define MAC_PCU_MISC_MODE2_RESERVED_2_MASK 0x00000020 +#define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010 +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_RESERVED_0_MSB 3 +#define MAC_PCU_MISC_MODE2_RESERVED_0_LSB 3 +#define MAC_PCU_MISC_MODE2_RESERVED_0_MASK 0x00000008 +#define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB) +#define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004 +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) +#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002 +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001 +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) +#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) + +#define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS 0x00008148 +#define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET 0x00000148 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB 31 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB 16 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK 0xffff0000 +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x) (((x) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) +#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x) (((x) << MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) + +#define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS 0x0000814c +#define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET 0x0000014c +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB 31 +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB 0 +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK 0xffffffff +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x) (((x) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) +#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x) (((x) << MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) + +#define MAC_PCU_MAX_CFP_DUR_ADDRESS 0x00008150 +#define MAC_PCU_MAX_CFP_DUR_OFFSET 0x00000150 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0 +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) +#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) + +#define MAC_PCU_HCF_TIMEOUT_ADDRESS 0x00008154 +#define MAC_PCU_HCF_TIMEOUT_OFFSET 0x00000154 +#define MAC_PCU_HCF_TIMEOUT_VALUE_MSB 15 +#define MAC_PCU_HCF_TIMEOUT_VALUE_LSB 0 +#define MAC_PCU_HCF_TIMEOUT_VALUE_MASK 0x0000ffff +#define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB) +#define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_HCF_TIMEOUT_VALUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS 0x00008158 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET 0x00000158 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) +#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) + +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS 0x0000815c +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET 0x0000015c +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) +#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0 +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) +#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) + +#define MAC_PCU_BLUETOOTH_MODE3_ADDRESS 0x00008164 +#define MAC_PCU_BLUETOOTH_MODE3_OFFSET 0x00000164 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000 +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB 27 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB 27 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000 +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB 26 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB 25 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK 0x06000000 +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000 +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000 +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000 +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB 20 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB 20 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK 0x00100000 +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000 +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB 8 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK 0x0000ff00 +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7 +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) +#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) + +#define MAC_PCU_BLUETOOTH_MODE4_ADDRESS 0x00008168 +#define MAC_PCU_BLUETOOTH_MODE4_OFFSET 0x00000168 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000 +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15 +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0 +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) +#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) + +#define MAC_PCU_BT_BT_ADDRESS 0x00008200 +#define MAC_PCU_BT_BT_OFFSET 0x00000200 +#define MAC_PCU_BT_BT_WEIGHT_MSB 31 +#define MAC_PCU_BT_BT_WEIGHT_LSB 0 +#define MAC_PCU_BT_BT_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_WEIGHT_MASK) >> MAC_PCU_BT_BT_WEIGHT_LSB) +#define MAC_PCU_BT_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_WEIGHT_LSB) & MAC_PCU_BT_BT_WEIGHT_MASK) + +#define MAC_PCU_BT_BT_ASYNC_ADDRESS 0x00008300 +#define MAC_PCU_BT_BT_ASYNC_OFFSET 0x00000300 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB 15 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB 12 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK 0x0000f000 +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB 11 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB 8 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK 0x00000f00 +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB 7 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB 4 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK 0x000000f0 +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB 3 +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB 0 +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK 0x0000000f +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) +#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_1_ADDRESS 0x00008304 +#define MAC_PCU_BT_WL_1_OFFSET 0x00000304 +#define MAC_PCU_BT_WL_1_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_1_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_1_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_1_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_1_WEIGHT_MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB) +#define MAC_PCU_BT_WL_1_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_1_WEIGHT_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_2_ADDRESS 0x00008308 +#define MAC_PCU_BT_WL_2_OFFSET 0x00000308 +#define MAC_PCU_BT_WL_2_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_2_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_2_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_2_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_2_WEIGHT_MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB) +#define MAC_PCU_BT_WL_2_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_2_WEIGHT_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_3_ADDRESS 0x0000830c +#define MAC_PCU_BT_WL_3_OFFSET 0x0000030c +#define MAC_PCU_BT_WL_3_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_3_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_3_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_3_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_3_WEIGHT_MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB) +#define MAC_PCU_BT_WL_3_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_3_WEIGHT_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK) + +#define MAC_PCU_BT_WL_4_ADDRESS 0x00008310 +#define MAC_PCU_BT_WL_4_OFFSET 0x00000310 +#define MAC_PCU_BT_WL_4_WEIGHT_MSB 31 +#define MAC_PCU_BT_WL_4_WEIGHT_LSB 0 +#define MAC_PCU_BT_WL_4_WEIGHT_MASK 0xffffffff +#define MAC_PCU_BT_WL_4_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_4_WEIGHT_MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB) +#define MAC_PCU_BT_WL_4_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_4_WEIGHT_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK) + +#define MAC_PCU_COEX_EPTA_ADDRESS 0x00008314 +#define MAC_PCU_COEX_EPTA_OFFSET 0x00000314 +#define MAC_PCU_COEX_EPTA_WT_IDX_MSB 12 +#define MAC_PCU_COEX_EPTA_WT_IDX_LSB 6 +#define MAC_PCU_COEX_EPTA_WT_IDX_MASK 0x00001fc0 +#define MAC_PCU_COEX_EPTA_WT_IDX_GET(x) (((x) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB) +#define MAC_PCU_COEX_EPTA_WT_IDX_SET(x) (((x) << MAC_PCU_COEX_EPTA_WT_IDX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) +#define MAC_PCU_COEX_EPTA_LINKID_MSB 5 +#define MAC_PCU_COEX_EPTA_LINKID_LSB 0 +#define MAC_PCU_COEX_EPTA_LINKID_MASK 0x0000003f +#define MAC_PCU_COEX_EPTA_LINKID_GET(x) (((x) & MAC_PCU_COEX_EPTA_LINKID_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB) +#define MAC_PCU_COEX_EPTA_LINKID_SET(x) (((x) << MAC_PCU_COEX_EPTA_LINKID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS 0x00008318 +#define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET 0x00000318 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS 0x0000831c +#define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET 0x0000031c +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS 0x00008320 +#define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET 0x00000320 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) + +#define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS 0x00008324 +#define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET 0x00000324 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB 31 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB 24 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK 0xff000000 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB 23 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB 16 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK 0x00ff0000 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB 15 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB 8 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK 0x0000ff00 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB 7 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB 0 +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK 0x000000ff +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) +#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) + +#define MAC_PCU_BASIC_RATE_SET0_ADDRESS 0x00008328 +#define MAC_PCU_BASIC_RATE_SET0_OFFSET 0x00000328 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET1_ADDRESS 0x0000832c +#define MAC_PCU_BASIC_RATE_SET1_OFFSET 0x0000032c +#define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET2_ADDRESS 0x00008330 +#define MAC_PCU_BASIC_RATE_SET2_OFFSET 0x00000330 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB 29 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK 0x3fffffff +#define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) + +#define MAC_PCU_BASIC_RATE_SET3_ADDRESS 0x00008334 +#define MAC_PCU_BASIC_RATE_SET3_OFFSET 0x00000334 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB 24 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB 0 +#define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK 0x01ffffff +#define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) +#define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS0_ADDRESS 0x00008338 +#define MAC_PCU_RX_INT_STATUS0_OFFSET 0x00000338 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB 31 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB 24 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK 0xff000000 +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) +#define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB 23 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB 16 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK 0x00ff0000 +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) +#define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0 +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) +#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) + +#define MAC_PCU_RX_INT_STATUS1_ADDRESS 0x0000833c +#define MAC_PCU_RX_INT_STATUS1_OFFSET 0x0000033c +#define MAC_PCU_RX_INT_STATUS1_VALUE_MSB 17 +#define MAC_PCU_RX_INT_STATUS1_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS1_VALUE_MASK 0x0003ffff +#define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS1_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS2_ADDRESS 0x00008340 +#define MAC_PCU_RX_INT_STATUS2_OFFSET 0x00000340 +#define MAC_PCU_RX_INT_STATUS2_VALUE_MSB 26 +#define MAC_PCU_RX_INT_STATUS2_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS2_VALUE_MASK 0x07ffffff +#define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS2_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) + +#define MAC_PCU_RX_INT_STATUS3_ADDRESS 0x00008344 +#define MAC_PCU_RX_INT_STATUS3_OFFSET 0x00000344 +#define MAC_PCU_RX_INT_STATUS3_VALUE_MSB 23 +#define MAC_PCU_RX_INT_STATUS3_VALUE_LSB 0 +#define MAC_PCU_RX_INT_STATUS3_VALUE_MASK 0x00ffffff +#define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB) +#define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS3_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) + +#define HT_HALF_GI_RATE1_ADDRESS 0x00008348 +#define HT_HALF_GI_RATE1_OFFSET 0x00000348 +#define HT_HALF_GI_RATE1_MCS3_MSB 31 +#define HT_HALF_GI_RATE1_MCS3_LSB 24 +#define HT_HALF_GI_RATE1_MCS3_MASK 0xff000000 +#define HT_HALF_GI_RATE1_MCS3_GET(x) (((x) & HT_HALF_GI_RATE1_MCS3_MASK) >> HT_HALF_GI_RATE1_MCS3_LSB) +#define HT_HALF_GI_RATE1_MCS3_SET(x) (((x) << HT_HALF_GI_RATE1_MCS3_LSB) & HT_HALF_GI_RATE1_MCS3_MASK) +#define HT_HALF_GI_RATE1_MCS2_MSB 23 +#define HT_HALF_GI_RATE1_MCS2_LSB 16 +#define HT_HALF_GI_RATE1_MCS2_MASK 0x00ff0000 +#define HT_HALF_GI_RATE1_MCS2_GET(x) (((x) & HT_HALF_GI_RATE1_MCS2_MASK) >> HT_HALF_GI_RATE1_MCS2_LSB) +#define HT_HALF_GI_RATE1_MCS2_SET(x) (((x) << HT_HALF_GI_RATE1_MCS2_LSB) & HT_HALF_GI_RATE1_MCS2_MASK) +#define HT_HALF_GI_RATE1_MCS1_MSB 15 +#define HT_HALF_GI_RATE1_MCS1_LSB 8 +#define HT_HALF_GI_RATE1_MCS1_MASK 0x0000ff00 +#define HT_HALF_GI_RATE1_MCS1_GET(x) (((x) & HT_HALF_GI_RATE1_MCS1_MASK) >> HT_HALF_GI_RATE1_MCS1_LSB) +#define HT_HALF_GI_RATE1_MCS1_SET(x) (((x) << HT_HALF_GI_RATE1_MCS1_LSB) & HT_HALF_GI_RATE1_MCS1_MASK) +#define HT_HALF_GI_RATE1_MCS0_MSB 7 +#define HT_HALF_GI_RATE1_MCS0_LSB 0 +#define HT_HALF_GI_RATE1_MCS0_MASK 0x000000ff +#define HT_HALF_GI_RATE1_MCS0_GET(x) (((x) & HT_HALF_GI_RATE1_MCS0_MASK) >> HT_HALF_GI_RATE1_MCS0_LSB) +#define HT_HALF_GI_RATE1_MCS0_SET(x) (((x) << HT_HALF_GI_RATE1_MCS0_LSB) & HT_HALF_GI_RATE1_MCS0_MASK) + +#define HT_HALF_GI_RATE2_ADDRESS 0x0000834c +#define HT_HALF_GI_RATE2_OFFSET 0x0000034c +#define HT_HALF_GI_RATE2_MCS7_MSB 31 +#define HT_HALF_GI_RATE2_MCS7_LSB 24 +#define HT_HALF_GI_RATE2_MCS7_MASK 0xff000000 +#define HT_HALF_GI_RATE2_MCS7_GET(x) (((x) & HT_HALF_GI_RATE2_MCS7_MASK) >> HT_HALF_GI_RATE2_MCS7_LSB) +#define HT_HALF_GI_RATE2_MCS7_SET(x) (((x) << HT_HALF_GI_RATE2_MCS7_LSB) & HT_HALF_GI_RATE2_MCS7_MASK) +#define HT_HALF_GI_RATE2_MCS6_MSB 23 +#define HT_HALF_GI_RATE2_MCS6_LSB 16 +#define HT_HALF_GI_RATE2_MCS6_MASK 0x00ff0000 +#define HT_HALF_GI_RATE2_MCS6_GET(x) (((x) & HT_HALF_GI_RATE2_MCS6_MASK) >> HT_HALF_GI_RATE2_MCS6_LSB) +#define HT_HALF_GI_RATE2_MCS6_SET(x) (((x) << HT_HALF_GI_RATE2_MCS6_LSB) & HT_HALF_GI_RATE2_MCS6_MASK) +#define HT_HALF_GI_RATE2_MCS5_MSB 15 +#define HT_HALF_GI_RATE2_MCS5_LSB 8 +#define HT_HALF_GI_RATE2_MCS5_MASK 0x0000ff00 +#define HT_HALF_GI_RATE2_MCS5_GET(x) (((x) & HT_HALF_GI_RATE2_MCS5_MASK) >> HT_HALF_GI_RATE2_MCS5_LSB) +#define HT_HALF_GI_RATE2_MCS5_SET(x) (((x) << HT_HALF_GI_RATE2_MCS5_LSB) & HT_HALF_GI_RATE2_MCS5_MASK) +#define HT_HALF_GI_RATE2_MCS4_MSB 7 +#define HT_HALF_GI_RATE2_MCS4_LSB 0 +#define HT_HALF_GI_RATE2_MCS4_MASK 0x000000ff +#define HT_HALF_GI_RATE2_MCS4_GET(x) (((x) & HT_HALF_GI_RATE2_MCS4_MASK) >> HT_HALF_GI_RATE2_MCS4_LSB) +#define HT_HALF_GI_RATE2_MCS4_SET(x) (((x) << HT_HALF_GI_RATE2_MCS4_LSB) & HT_HALF_GI_RATE2_MCS4_MASK) + +#define HT_FULL_GI_RATE1_ADDRESS 0x00008350 +#define HT_FULL_GI_RATE1_OFFSET 0x00000350 +#define HT_FULL_GI_RATE1_MCS3_MSB 31 +#define HT_FULL_GI_RATE1_MCS3_LSB 24 +#define HT_FULL_GI_RATE1_MCS3_MASK 0xff000000 +#define HT_FULL_GI_RATE1_MCS3_GET(x) (((x) & HT_FULL_GI_RATE1_MCS3_MASK) >> HT_FULL_GI_RATE1_MCS3_LSB) +#define HT_FULL_GI_RATE1_MCS3_SET(x) (((x) << HT_FULL_GI_RATE1_MCS3_LSB) & HT_FULL_GI_RATE1_MCS3_MASK) +#define HT_FULL_GI_RATE1_MCS2_MSB 23 +#define HT_FULL_GI_RATE1_MCS2_LSB 16 +#define HT_FULL_GI_RATE1_MCS2_MASK 0x00ff0000 +#define HT_FULL_GI_RATE1_MCS2_GET(x) (((x) & HT_FULL_GI_RATE1_MCS2_MASK) >> HT_FULL_GI_RATE1_MCS2_LSB) +#define HT_FULL_GI_RATE1_MCS2_SET(x) (((x) << HT_FULL_GI_RATE1_MCS2_LSB) & HT_FULL_GI_RATE1_MCS2_MASK) +#define HT_FULL_GI_RATE1_MCS1_MSB 15 +#define HT_FULL_GI_RATE1_MCS1_LSB 8 +#define HT_FULL_GI_RATE1_MCS1_MASK 0x0000ff00 +#define HT_FULL_GI_RATE1_MCS1_GET(x) (((x) & HT_FULL_GI_RATE1_MCS1_MASK) >> HT_FULL_GI_RATE1_MCS1_LSB) +#define HT_FULL_GI_RATE1_MCS1_SET(x) (((x) << HT_FULL_GI_RATE1_MCS1_LSB) & HT_FULL_GI_RATE1_MCS1_MASK) +#define HT_FULL_GI_RATE1_MCS0_MSB 7 +#define HT_FULL_GI_RATE1_MCS0_LSB 0 +#define HT_FULL_GI_RATE1_MCS0_MASK 0x000000ff +#define HT_FULL_GI_RATE1_MCS0_GET(x) (((x) & HT_FULL_GI_RATE1_MCS0_MASK) >> HT_FULL_GI_RATE1_MCS0_LSB) +#define HT_FULL_GI_RATE1_MCS0_SET(x) (((x) << HT_FULL_GI_RATE1_MCS0_LSB) & HT_FULL_GI_RATE1_MCS0_MASK) + +#define HT_FULL_GI_RATE2_ADDRESS 0x00008354 +#define HT_FULL_GI_RATE2_OFFSET 0x00000354 +#define HT_FULL_GI_RATE2_MCS7_MSB 31 +#define HT_FULL_GI_RATE2_MCS7_LSB 24 +#define HT_FULL_GI_RATE2_MCS7_MASK 0xff000000 +#define HT_FULL_GI_RATE2_MCS7_GET(x) (((x) & HT_FULL_GI_RATE2_MCS7_MASK) >> HT_FULL_GI_RATE2_MCS7_LSB) +#define HT_FULL_GI_RATE2_MCS7_SET(x) (((x) << HT_FULL_GI_RATE2_MCS7_LSB) & HT_FULL_GI_RATE2_MCS7_MASK) +#define HT_FULL_GI_RATE2_MCS6_MSB 23 +#define HT_FULL_GI_RATE2_MCS6_LSB 16 +#define HT_FULL_GI_RATE2_MCS6_MASK 0x00ff0000 +#define HT_FULL_GI_RATE2_MCS6_GET(x) (((x) & HT_FULL_GI_RATE2_MCS6_MASK) >> HT_FULL_GI_RATE2_MCS6_LSB) +#define HT_FULL_GI_RATE2_MCS6_SET(x) (((x) << HT_FULL_GI_RATE2_MCS6_LSB) & HT_FULL_GI_RATE2_MCS6_MASK) +#define HT_FULL_GI_RATE2_MCS5_MSB 15 +#define HT_FULL_GI_RATE2_MCS5_LSB 8 +#define HT_FULL_GI_RATE2_MCS5_MASK 0x0000ff00 +#define HT_FULL_GI_RATE2_MCS5_GET(x) (((x) & HT_FULL_GI_RATE2_MCS5_MASK) >> HT_FULL_GI_RATE2_MCS5_LSB) +#define HT_FULL_GI_RATE2_MCS5_SET(x) (((x) << HT_FULL_GI_RATE2_MCS5_LSB) & HT_FULL_GI_RATE2_MCS5_MASK) +#define HT_FULL_GI_RATE2_MCS4_MSB 7 +#define HT_FULL_GI_RATE2_MCS4_LSB 0 +#define HT_FULL_GI_RATE2_MCS4_MASK 0x000000ff +#define HT_FULL_GI_RATE2_MCS4_GET(x) (((x) & HT_FULL_GI_RATE2_MCS4_MASK) >> HT_FULL_GI_RATE2_MCS4_LSB) +#define HT_FULL_GI_RATE2_MCS4_SET(x) (((x) << HT_FULL_GI_RATE2_MCS4_LSB) & HT_FULL_GI_RATE2_MCS4_MASK) + +#define LEGACY_RATE1_ADDRESS 0x00008358 +#define LEGACY_RATE1_OFFSET 0x00000358 +#define LEGACY_RATE1_RATE12_MSB 29 +#define LEGACY_RATE1_RATE12_LSB 24 +#define LEGACY_RATE1_RATE12_MASK 0x3f000000 +#define LEGACY_RATE1_RATE12_GET(x) (((x) & LEGACY_RATE1_RATE12_MASK) >> LEGACY_RATE1_RATE12_LSB) +#define LEGACY_RATE1_RATE12_SET(x) (((x) << LEGACY_RATE1_RATE12_LSB) & LEGACY_RATE1_RATE12_MASK) +#define LEGACY_RATE1_RATE11_MSB 23 +#define LEGACY_RATE1_RATE11_LSB 18 +#define LEGACY_RATE1_RATE11_MASK 0x00fc0000 +#define LEGACY_RATE1_RATE11_GET(x) (((x) & LEGACY_RATE1_RATE11_MASK) >> LEGACY_RATE1_RATE11_LSB) +#define LEGACY_RATE1_RATE11_SET(x) (((x) << LEGACY_RATE1_RATE11_LSB) & LEGACY_RATE1_RATE11_MASK) +#define LEGACY_RATE1_RATE10_MSB 17 +#define LEGACY_RATE1_RATE10_LSB 12 +#define LEGACY_RATE1_RATE10_MASK 0x0003f000 +#define LEGACY_RATE1_RATE10_GET(x) (((x) & LEGACY_RATE1_RATE10_MASK) >> LEGACY_RATE1_RATE10_LSB) +#define LEGACY_RATE1_RATE10_SET(x) (((x) << LEGACY_RATE1_RATE10_LSB) & LEGACY_RATE1_RATE10_MASK) +#define LEGACY_RATE1_RATE9_MSB 11 +#define LEGACY_RATE1_RATE9_LSB 6 +#define LEGACY_RATE1_RATE9_MASK 0x00000fc0 +#define LEGACY_RATE1_RATE9_GET(x) (((x) & LEGACY_RATE1_RATE9_MASK) >> LEGACY_RATE1_RATE9_LSB) +#define LEGACY_RATE1_RATE9_SET(x) (((x) << LEGACY_RATE1_RATE9_LSB) & LEGACY_RATE1_RATE9_MASK) +#define LEGACY_RATE1_RATE8_MSB 5 +#define LEGACY_RATE1_RATE8_LSB 0 +#define LEGACY_RATE1_RATE8_MASK 0x0000003f +#define LEGACY_RATE1_RATE8_GET(x) (((x) & LEGACY_RATE1_RATE8_MASK) >> LEGACY_RATE1_RATE8_LSB) +#define LEGACY_RATE1_RATE8_SET(x) (((x) << LEGACY_RATE1_RATE8_LSB) & LEGACY_RATE1_RATE8_MASK) + +#define LEGACY_RATE2_ADDRESS 0x0000835c +#define LEGACY_RATE2_OFFSET 0x0000035c +#define LEGACY_RATE2_RATE25_MSB 29 +#define LEGACY_RATE2_RATE25_LSB 24 +#define LEGACY_RATE2_RATE25_MASK 0x3f000000 +#define LEGACY_RATE2_RATE25_GET(x) (((x) & LEGACY_RATE2_RATE25_MASK) >> LEGACY_RATE2_RATE25_LSB) +#define LEGACY_RATE2_RATE25_SET(x) (((x) << LEGACY_RATE2_RATE25_LSB) & LEGACY_RATE2_RATE25_MASK) +#define LEGACY_RATE2_RATE24_MSB 23 +#define LEGACY_RATE2_RATE24_LSB 18 +#define LEGACY_RATE2_RATE24_MASK 0x00fc0000 +#define LEGACY_RATE2_RATE24_GET(x) (((x) & LEGACY_RATE2_RATE24_MASK) >> LEGACY_RATE2_RATE24_LSB) +#define LEGACY_RATE2_RATE24_SET(x) (((x) << LEGACY_RATE2_RATE24_LSB) & LEGACY_RATE2_RATE24_MASK) +#define LEGACY_RATE2_RATE15_MSB 17 +#define LEGACY_RATE2_RATE15_LSB 12 +#define LEGACY_RATE2_RATE15_MASK 0x0003f000 +#define LEGACY_RATE2_RATE15_GET(x) (((x) & LEGACY_RATE2_RATE15_MASK) >> LEGACY_RATE2_RATE15_LSB) +#define LEGACY_RATE2_RATE15_SET(x) (((x) << LEGACY_RATE2_RATE15_LSB) & LEGACY_RATE2_RATE15_MASK) +#define LEGACY_RATE2_RATE14_MSB 11 +#define LEGACY_RATE2_RATE14_LSB 6 +#define LEGACY_RATE2_RATE14_MASK 0x00000fc0 +#define LEGACY_RATE2_RATE14_GET(x) (((x) & LEGACY_RATE2_RATE14_MASK) >> LEGACY_RATE2_RATE14_LSB) +#define LEGACY_RATE2_RATE14_SET(x) (((x) << LEGACY_RATE2_RATE14_LSB) & LEGACY_RATE2_RATE14_MASK) +#define LEGACY_RATE2_RATE13_MSB 5 +#define LEGACY_RATE2_RATE13_LSB 0 +#define LEGACY_RATE2_RATE13_MASK 0x0000003f +#define LEGACY_RATE2_RATE13_GET(x) (((x) & LEGACY_RATE2_RATE13_MASK) >> LEGACY_RATE2_RATE13_LSB) +#define LEGACY_RATE2_RATE13_SET(x) (((x) << LEGACY_RATE2_RATE13_LSB) & LEGACY_RATE2_RATE13_MASK) + +#define LEGACY_RATE3_ADDRESS 0x00008360 +#define LEGACY_RATE3_OFFSET 0x00000360 +#define LEGACY_RATE3_RATE30_MSB 29 +#define LEGACY_RATE3_RATE30_LSB 24 +#define LEGACY_RATE3_RATE30_MASK 0x3f000000 +#define LEGACY_RATE3_RATE30_GET(x) (((x) & LEGACY_RATE3_RATE30_MASK) >> LEGACY_RATE3_RATE30_LSB) +#define LEGACY_RATE3_RATE30_SET(x) (((x) << LEGACY_RATE3_RATE30_LSB) & LEGACY_RATE3_RATE30_MASK) +#define LEGACY_RATE3_RATE29_MSB 23 +#define LEGACY_RATE3_RATE29_LSB 18 +#define LEGACY_RATE3_RATE29_MASK 0x00fc0000 +#define LEGACY_RATE3_RATE29_GET(x) (((x) & LEGACY_RATE3_RATE29_MASK) >> LEGACY_RATE3_RATE29_LSB) +#define LEGACY_RATE3_RATE29_SET(x) (((x) << LEGACY_RATE3_RATE29_LSB) & LEGACY_RATE3_RATE29_MASK) +#define LEGACY_RATE3_RATE28_MSB 17 +#define LEGACY_RATE3_RATE28_LSB 12 +#define LEGACY_RATE3_RATE28_MASK 0x0003f000 +#define LEGACY_RATE3_RATE28_GET(x) (((x) & LEGACY_RATE3_RATE28_MASK) >> LEGACY_RATE3_RATE28_LSB) +#define LEGACY_RATE3_RATE28_SET(x) (((x) << LEGACY_RATE3_RATE28_LSB) & LEGACY_RATE3_RATE28_MASK) +#define LEGACY_RATE3_RATE27_MSB 11 +#define LEGACY_RATE3_RATE27_LSB 6 +#define LEGACY_RATE3_RATE27_MASK 0x00000fc0 +#define LEGACY_RATE3_RATE27_GET(x) (((x) & LEGACY_RATE3_RATE27_MASK) >> LEGACY_RATE3_RATE27_LSB) +#define LEGACY_RATE3_RATE27_SET(x) (((x) << LEGACY_RATE3_RATE27_LSB) & LEGACY_RATE3_RATE27_MASK) +#define LEGACY_RATE3_RATE26_MSB 5 +#define LEGACY_RATE3_RATE26_LSB 0 +#define LEGACY_RATE3_RATE26_MASK 0x0000003f +#define LEGACY_RATE3_RATE26_GET(x) (((x) & LEGACY_RATE3_RATE26_MASK) >> LEGACY_RATE3_RATE26_LSB) +#define LEGACY_RATE3_RATE26_SET(x) (((x) << LEGACY_RATE3_RATE26_LSB) & LEGACY_RATE3_RATE26_MASK) + +#define RX_INT_FILTER_ADDRESS 0x00008364 +#define RX_INT_FILTER_OFFSET 0x00000364 +#define RX_INT_FILTER_BEACON_MSB 17 +#define RX_INT_FILTER_BEACON_LSB 17 +#define RX_INT_FILTER_BEACON_MASK 0x00020000 +#define RX_INT_FILTER_BEACON_GET(x) (((x) & RX_INT_FILTER_BEACON_MASK) >> RX_INT_FILTER_BEACON_LSB) +#define RX_INT_FILTER_BEACON_SET(x) (((x) << RX_INT_FILTER_BEACON_LSB) & RX_INT_FILTER_BEACON_MASK) +#define RX_INT_FILTER_AMPDU_MSB 16 +#define RX_INT_FILTER_AMPDU_LSB 16 +#define RX_INT_FILTER_AMPDU_MASK 0x00010000 +#define RX_INT_FILTER_AMPDU_GET(x) (((x) & RX_INT_FILTER_AMPDU_MASK) >> RX_INT_FILTER_AMPDU_LSB) +#define RX_INT_FILTER_AMPDU_SET(x) (((x) << RX_INT_FILTER_AMPDU_LSB) & RX_INT_FILTER_AMPDU_MASK) +#define RX_INT_FILTER_EOSP_MSB 15 +#define RX_INT_FILTER_EOSP_LSB 15 +#define RX_INT_FILTER_EOSP_MASK 0x00008000 +#define RX_INT_FILTER_EOSP_GET(x) (((x) & RX_INT_FILTER_EOSP_MASK) >> RX_INT_FILTER_EOSP_LSB) +#define RX_INT_FILTER_EOSP_SET(x) (((x) << RX_INT_FILTER_EOSP_LSB) & RX_INT_FILTER_EOSP_MASK) +#define RX_INT_FILTER_LENGTH_LOW_MSB 14 +#define RX_INT_FILTER_LENGTH_LOW_LSB 14 +#define RX_INT_FILTER_LENGTH_LOW_MASK 0x00004000 +#define RX_INT_FILTER_LENGTH_LOW_GET(x) (((x) & RX_INT_FILTER_LENGTH_LOW_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB) +#define RX_INT_FILTER_LENGTH_LOW_SET(x) (((x) << RX_INT_FILTER_LENGTH_LOW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK) +#define RX_INT_FILTER_LENGTH_HIGH_MSB 13 +#define RX_INT_FILTER_LENGTH_HIGH_LSB 13 +#define RX_INT_FILTER_LENGTH_HIGH_MASK 0x00002000 +#define RX_INT_FILTER_LENGTH_HIGH_GET(x) (((x) & RX_INT_FILTER_LENGTH_HIGH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB) +#define RX_INT_FILTER_LENGTH_HIGH_SET(x) (((x) << RX_INT_FILTER_LENGTH_HIGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK) +#define RX_INT_FILTER_RSSI_MSB 12 +#define RX_INT_FILTER_RSSI_LSB 12 +#define RX_INT_FILTER_RSSI_MASK 0x00001000 +#define RX_INT_FILTER_RSSI_GET(x) (((x) & RX_INT_FILTER_RSSI_MASK) >> RX_INT_FILTER_RSSI_LSB) +#define RX_INT_FILTER_RSSI_SET(x) (((x) << RX_INT_FILTER_RSSI_LSB) & RX_INT_FILTER_RSSI_MASK) +#define RX_INT_FILTER_RATE_LOW_MSB 11 +#define RX_INT_FILTER_RATE_LOW_LSB 11 +#define RX_INT_FILTER_RATE_LOW_MASK 0x00000800 +#define RX_INT_FILTER_RATE_LOW_GET(x) (((x) & RX_INT_FILTER_RATE_LOW_MASK) >> RX_INT_FILTER_RATE_LOW_LSB) +#define RX_INT_FILTER_RATE_LOW_SET(x) (((x) << RX_INT_FILTER_RATE_LOW_LSB) & RX_INT_FILTER_RATE_LOW_MASK) +#define RX_INT_FILTER_RATE_HIGH_MSB 10 +#define RX_INT_FILTER_RATE_HIGH_LSB 10 +#define RX_INT_FILTER_RATE_HIGH_MASK 0x00000400 +#define RX_INT_FILTER_RATE_HIGH_GET(x) (((x) & RX_INT_FILTER_RATE_HIGH_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB) +#define RX_INT_FILTER_RATE_HIGH_SET(x) (((x) << RX_INT_FILTER_RATE_HIGH_LSB) & RX_INT_FILTER_RATE_HIGH_MASK) +#define RX_INT_FILTER_MORE_FRAG_MSB 9 +#define RX_INT_FILTER_MORE_FRAG_LSB 9 +#define RX_INT_FILTER_MORE_FRAG_MASK 0x00000200 +#define RX_INT_FILTER_MORE_FRAG_GET(x) (((x) & RX_INT_FILTER_MORE_FRAG_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB) +#define RX_INT_FILTER_MORE_FRAG_SET(x) (((x) << RX_INT_FILTER_MORE_FRAG_LSB) & RX_INT_FILTER_MORE_FRAG_MASK) +#define RX_INT_FILTER_MORE_DATA_MSB 8 +#define RX_INT_FILTER_MORE_DATA_LSB 8 +#define RX_INT_FILTER_MORE_DATA_MASK 0x00000100 +#define RX_INT_FILTER_MORE_DATA_GET(x) (((x) & RX_INT_FILTER_MORE_DATA_MASK) >> RX_INT_FILTER_MORE_DATA_LSB) +#define RX_INT_FILTER_MORE_DATA_SET(x) (((x) << RX_INT_FILTER_MORE_DATA_LSB) & RX_INT_FILTER_MORE_DATA_MASK) +#define RX_INT_FILTER_RETRY_MSB 7 +#define RX_INT_FILTER_RETRY_LSB 7 +#define RX_INT_FILTER_RETRY_MASK 0x00000080 +#define RX_INT_FILTER_RETRY_GET(x) (((x) & RX_INT_FILTER_RETRY_MASK) >> RX_INT_FILTER_RETRY_LSB) +#define RX_INT_FILTER_RETRY_SET(x) (((x) << RX_INT_FILTER_RETRY_LSB) & RX_INT_FILTER_RETRY_MASK) +#define RX_INT_FILTER_CTS_MSB 6 +#define RX_INT_FILTER_CTS_LSB 6 +#define RX_INT_FILTER_CTS_MASK 0x00000040 +#define RX_INT_FILTER_CTS_GET(x) (((x) & RX_INT_FILTER_CTS_MASK) >> RX_INT_FILTER_CTS_LSB) +#define RX_INT_FILTER_CTS_SET(x) (((x) << RX_INT_FILTER_CTS_LSB) & RX_INT_FILTER_CTS_MASK) +#define RX_INT_FILTER_ACK_MSB 5 +#define RX_INT_FILTER_ACK_LSB 5 +#define RX_INT_FILTER_ACK_MASK 0x00000020 +#define RX_INT_FILTER_ACK_GET(x) (((x) & RX_INT_FILTER_ACK_MASK) >> RX_INT_FILTER_ACK_LSB) +#define RX_INT_FILTER_ACK_SET(x) (((x) << RX_INT_FILTER_ACK_LSB) & RX_INT_FILTER_ACK_MASK) +#define RX_INT_FILTER_RTS_MSB 4 +#define RX_INT_FILTER_RTS_LSB 4 +#define RX_INT_FILTER_RTS_MASK 0x00000010 +#define RX_INT_FILTER_RTS_GET(x) (((x) & RX_INT_FILTER_RTS_MASK) >> RX_INT_FILTER_RTS_LSB) +#define RX_INT_FILTER_RTS_SET(x) (((x) << RX_INT_FILTER_RTS_LSB) & RX_INT_FILTER_RTS_MASK) +#define RX_INT_FILTER_MCAST_MSB 3 +#define RX_INT_FILTER_MCAST_LSB 3 +#define RX_INT_FILTER_MCAST_MASK 0x00000008 +#define RX_INT_FILTER_MCAST_GET(x) (((x) & RX_INT_FILTER_MCAST_MASK) >> RX_INT_FILTER_MCAST_LSB) +#define RX_INT_FILTER_MCAST_SET(x) (((x) << RX_INT_FILTER_MCAST_LSB) & RX_INT_FILTER_MCAST_MASK) +#define RX_INT_FILTER_BCAST_MSB 2 +#define RX_INT_FILTER_BCAST_LSB 2 +#define RX_INT_FILTER_BCAST_MASK 0x00000004 +#define RX_INT_FILTER_BCAST_GET(x) (((x) & RX_INT_FILTER_BCAST_MASK) >> RX_INT_FILTER_BCAST_LSB) +#define RX_INT_FILTER_BCAST_SET(x) (((x) << RX_INT_FILTER_BCAST_LSB) & RX_INT_FILTER_BCAST_MASK) +#define RX_INT_FILTER_DIRECTED_MSB 1 +#define RX_INT_FILTER_DIRECTED_LSB 1 +#define RX_INT_FILTER_DIRECTED_MASK 0x00000002 +#define RX_INT_FILTER_DIRECTED_GET(x) (((x) & RX_INT_FILTER_DIRECTED_MASK) >> RX_INT_FILTER_DIRECTED_LSB) +#define RX_INT_FILTER_DIRECTED_SET(x) (((x) << RX_INT_FILTER_DIRECTED_LSB) & RX_INT_FILTER_DIRECTED_MASK) +#define RX_INT_FILTER_ENABLE_MSB 0 +#define RX_INT_FILTER_ENABLE_LSB 0 +#define RX_INT_FILTER_ENABLE_MASK 0x00000001 +#define RX_INT_FILTER_ENABLE_GET(x) (((x) & RX_INT_FILTER_ENABLE_MASK) >> RX_INT_FILTER_ENABLE_LSB) +#define RX_INT_FILTER_ENABLE_SET(x) (((x) << RX_INT_FILTER_ENABLE_LSB) & RX_INT_FILTER_ENABLE_MASK) + +#define RX_INT_OVERFLOW_ADDRESS 0x00008368 +#define RX_INT_OVERFLOW_OFFSET 0x00000368 +#define RX_INT_OVERFLOW_STATUS_MSB 0 +#define RX_INT_OVERFLOW_STATUS_LSB 0 +#define RX_INT_OVERFLOW_STATUS_MASK 0x00000001 +#define RX_INT_OVERFLOW_STATUS_GET(x) (((x) & RX_INT_OVERFLOW_STATUS_MASK) >> RX_INT_OVERFLOW_STATUS_LSB) +#define RX_INT_OVERFLOW_STATUS_SET(x) (((x) << RX_INT_OVERFLOW_STATUS_LSB) & RX_INT_OVERFLOW_STATUS_MASK) + +#define RX_FILTER_THRESH_ADDRESS 0x0000836c +#define RX_FILTER_THRESH_OFFSET 0x0000036c +#define RX_FILTER_THRESH_RSSI_LOW_MSB 23 +#define RX_FILTER_THRESH_RSSI_LOW_LSB 16 +#define RX_FILTER_THRESH_RSSI_LOW_MASK 0x00ff0000 +#define RX_FILTER_THRESH_RSSI_LOW_GET(x) (((x) & RX_FILTER_THRESH_RSSI_LOW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB) +#define RX_FILTER_THRESH_RSSI_LOW_SET(x) (((x) << RX_FILTER_THRESH_RSSI_LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK) +#define RX_FILTER_THRESH_RATE_LOW_MSB 15 +#define RX_FILTER_THRESH_RATE_LOW_LSB 8 +#define RX_FILTER_THRESH_RATE_LOW_MASK 0x0000ff00 +#define RX_FILTER_THRESH_RATE_LOW_GET(x) (((x) & RX_FILTER_THRESH_RATE_LOW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB) +#define RX_FILTER_THRESH_RATE_LOW_SET(x) (((x) << RX_FILTER_THRESH_RATE_LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK) +#define RX_FILTER_THRESH_RATE_HIGH_MSB 7 +#define RX_FILTER_THRESH_RATE_HIGH_LSB 0 +#define RX_FILTER_THRESH_RATE_HIGH_MASK 0x000000ff +#define RX_FILTER_THRESH_RATE_HIGH_GET(x) (((x) & RX_FILTER_THRESH_RATE_HIGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB) +#define RX_FILTER_THRESH_RATE_HIGH_SET(x) (((x) << RX_FILTER_THRESH_RATE_HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK) + +#define RX_FILTER_THRESH1_ADDRESS 0x00008370 +#define RX_FILTER_THRESH1_OFFSET 0x00000370 +#define RX_FILTER_THRESH1_LENGTH_LOW_MSB 23 +#define RX_FILTER_THRESH1_LENGTH_LOW_LSB 12 +#define RX_FILTER_THRESH1_LENGTH_LOW_MASK 0x00fff000 +#define RX_FILTER_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB) +#define RX_FILTER_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) +#define RX_FILTER_THRESH1_LENGTH_HIGH_MSB 11 +#define RX_FILTER_THRESH1_LENGTH_HIGH_LSB 0 +#define RX_FILTER_THRESH1_LENGTH_HIGH_MASK 0x00000fff +#define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB) +#define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_THRESH0_ADDRESS 0x00008374 +#define RX_PRIORITY_THRESH0_OFFSET 0x00000374 +#define RX_PRIORITY_THRESH0_RSSI_LOW_MSB 31 +#define RX_PRIORITY_THRESH0_RSSI_LOW_LSB 24 +#define RX_PRIORITY_THRESH0_RSSI_LOW_MASK 0xff000000 +#define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB) +#define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) +#define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB 16 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK 0x00ff0000 +#define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH0_RATE_LOW_MSB 15 +#define RX_PRIORITY_THRESH0_RATE_LOW_LSB 8 +#define RX_PRIORITY_THRESH0_RATE_LOW_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH0_RATE_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB) +#define RX_PRIORITY_THRESH0_RATE_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) +#define RX_PRIORITY_THRESH0_RATE_HIGH_MSB 7 +#define RX_PRIORITY_THRESH0_RATE_HIGH_LSB 0 +#define RX_PRIORITY_THRESH0_RATE_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB) +#define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) + +#define RX_PRIORITY_THRESH1_ADDRESS 0x00008378 +#define RX_PRIORITY_THRESH1_OFFSET 0x00000378 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB 31 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000 +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB 23 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB 12 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK 0x00fff000 +#define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) +#define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB 11 +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB 0 +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK 0x00000fff +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) +#define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_THRESH2_ADDRESS 0x0000837c +#define RX_PRIORITY_THRESH2_OFFSET 0x0000037c +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB 31 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK 0xff000000 +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000 +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB 15 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB 8 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB 7 +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) + +#define RX_PRIORITY_THRESH3_ADDRESS 0x00008380 +#define RX_PRIORITY_THRESH3_OFFSET 0x00000380 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00 +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB 7 +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK 0x000000ff +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) +#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) + +#define RX_PRIORITY_OFFSET0_ADDRESS 0x00008384 +#define RX_PRIORITY_OFFSET0_OFFSET 0x00000384 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB 29 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB 23 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB 18 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) +#define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB 11 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB 6 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) +#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) +#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) + +#define RX_PRIORITY_OFFSET1_ADDRESS 0x00008388 +#define RX_PRIORITY_OFFSET1_OFFSET 0x00000388 +#define RX_PRIORITY_OFFSET1_RTS_MSB 29 +#define RX_PRIORITY_OFFSET1_RTS_LSB 24 +#define RX_PRIORITY_OFFSET1_RTS_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET1_RTS_GET(x) (((x) & RX_PRIORITY_OFFSET1_RTS_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB) +#define RX_PRIORITY_OFFSET1_RTS_SET(x) (((x) << RX_PRIORITY_OFFSET1_RTS_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK) +#define RX_PRIORITY_OFFSET1_RETX_MSB 23 +#define RX_PRIORITY_OFFSET1_RETX_LSB 18 +#define RX_PRIORITY_OFFSET1_RETX_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET1_RETX_GET(x) (((x) & RX_PRIORITY_OFFSET1_RETX_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB) +#define RX_PRIORITY_OFFSET1_RETX_SET(x) (((x) << RX_PRIORITY_OFFSET1_RETX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK) +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB 11 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB 6 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) +#define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) +#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) + +#define RX_PRIORITY_OFFSET2_ADDRESS 0x0000838c +#define RX_PRIORITY_OFFSET2_OFFSET 0x0000038c +#define RX_PRIORITY_OFFSET2_BEACON_MSB 29 +#define RX_PRIORITY_OFFSET2_BEACON_LSB 24 +#define RX_PRIORITY_OFFSET2_BEACON_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET2_BEACON_GET(x) (((x) & RX_PRIORITY_OFFSET2_BEACON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB) +#define RX_PRIORITY_OFFSET2_BEACON_SET(x) (((x) << RX_PRIORITY_OFFSET2_BEACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK) +#define RX_PRIORITY_OFFSET2_MGMT_MSB 23 +#define RX_PRIORITY_OFFSET2_MGMT_LSB 18 +#define RX_PRIORITY_OFFSET2_MGMT_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET2_MGMT_GET(x) (((x) & RX_PRIORITY_OFFSET2_MGMT_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB) +#define RX_PRIORITY_OFFSET2_MGMT_SET(x) (((x) << RX_PRIORITY_OFFSET2_MGMT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK) +#define RX_PRIORITY_OFFSET2_ATIM_MSB 17 +#define RX_PRIORITY_OFFSET2_ATIM_LSB 12 +#define RX_PRIORITY_OFFSET2_ATIM_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET2_ATIM_GET(x) (((x) & RX_PRIORITY_OFFSET2_ATIM_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB) +#define RX_PRIORITY_OFFSET2_ATIM_SET(x) (((x) << RX_PRIORITY_OFFSET2_ATIM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK) +#define RX_PRIORITY_OFFSET2_PRESP_MSB 11 +#define RX_PRIORITY_OFFSET2_PRESP_LSB 6 +#define RX_PRIORITY_OFFSET2_PRESP_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET2_PRESP_GET(x) (((x) & RX_PRIORITY_OFFSET2_PRESP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB) +#define RX_PRIORITY_OFFSET2_PRESP_SET(x) (((x) << RX_PRIORITY_OFFSET2_PRESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK) +#define RX_PRIORITY_OFFSET2_XCAST_MSB 5 +#define RX_PRIORITY_OFFSET2_XCAST_LSB 0 +#define RX_PRIORITY_OFFSET2_XCAST_MASK 0x0000003f +#define RX_PRIORITY_OFFSET2_XCAST_GET(x) (((x) & RX_PRIORITY_OFFSET2_XCAST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB) +#define RX_PRIORITY_OFFSET2_XCAST_SET(x) (((x) << RX_PRIORITY_OFFSET2_XCAST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK) + +#define RX_PRIORITY_OFFSET3_ADDRESS 0x00008390 +#define RX_PRIORITY_OFFSET3_OFFSET 0x00000390 +#define RX_PRIORITY_OFFSET3_PS_POLL_MSB 29 +#define RX_PRIORITY_OFFSET3_PS_POLL_LSB 24 +#define RX_PRIORITY_OFFSET3_PS_POLL_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET3_PS_POLL_GET(x) (((x) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB) +#define RX_PRIORITY_OFFSET3_PS_POLL_SET(x) (((x) << RX_PRIORITY_OFFSET3_PS_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) +#define RX_PRIORITY_OFFSET3_AMSDU_MSB 23 +#define RX_PRIORITY_OFFSET3_AMSDU_LSB 18 +#define RX_PRIORITY_OFFSET3_AMSDU_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET3_AMSDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMSDU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB) +#define RX_PRIORITY_OFFSET3_AMSDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMSDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK) +#define RX_PRIORITY_OFFSET3_AMPDU_MSB 17 +#define RX_PRIORITY_OFFSET3_AMPDU_LSB 12 +#define RX_PRIORITY_OFFSET3_AMPDU_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET3_AMPDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMPDU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB) +#define RX_PRIORITY_OFFSET3_AMPDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMPDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK) +#define RX_PRIORITY_OFFSET3_EOSP_MSB 11 +#define RX_PRIORITY_OFFSET3_EOSP_LSB 6 +#define RX_PRIORITY_OFFSET3_EOSP_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET3_EOSP_GET(x) (((x) & RX_PRIORITY_OFFSET3_EOSP_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB) +#define RX_PRIORITY_OFFSET3_EOSP_SET(x) (((x) << RX_PRIORITY_OFFSET3_EOSP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK) +#define RX_PRIORITY_OFFSET3_MORE_MSB 5 +#define RX_PRIORITY_OFFSET3_MORE_LSB 0 +#define RX_PRIORITY_OFFSET3_MORE_MASK 0x0000003f +#define RX_PRIORITY_OFFSET3_MORE_GET(x) (((x) & RX_PRIORITY_OFFSET3_MORE_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB) +#define RX_PRIORITY_OFFSET3_MORE_SET(x) (((x) << RX_PRIORITY_OFFSET3_MORE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK) + +#define RX_PRIORITY_OFFSET4_ADDRESS 0x00008394 +#define RX_PRIORITY_OFFSET4_OFFSET 0x00000394 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000 +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB 23 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB 18 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK 0x00fc0000 +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB 17 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB 12 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) +#define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) +#define RX_PRIORITY_OFFSET4_NULL_MSB 11 +#define RX_PRIORITY_OFFSET4_NULL_LSB 6 +#define RX_PRIORITY_OFFSET4_NULL_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET4_NULL_GET(x) (((x) & RX_PRIORITY_OFFSET4_NULL_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB) +#define RX_PRIORITY_OFFSET4_NULL_SET(x) (((x) << RX_PRIORITY_OFFSET4_NULL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK) +#define RX_PRIORITY_OFFSET4_PREQ_MSB 5 +#define RX_PRIORITY_OFFSET4_PREQ_LSB 0 +#define RX_PRIORITY_OFFSET4_PREQ_MASK 0x0000003f +#define RX_PRIORITY_OFFSET4_PREQ_GET(x) (((x) & RX_PRIORITY_OFFSET4_PREQ_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB) +#define RX_PRIORITY_OFFSET4_PREQ_SET(x) (((x) << RX_PRIORITY_OFFSET4_PREQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK) + +#define RX_PRIORITY_OFFSET5_ADDRESS 0x00008398 +#define RX_PRIORITY_OFFSET5_OFFSET 0x00000398 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000 +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB 11 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB 6 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK 0x00000fc0 +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB 5 +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB 0 +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK 0x0000003f +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) +#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) + +#define MAC_PCU_BSSID2_L32_ADDRESS 0x0000839c +#define MAC_PCU_BSSID2_L32_OFFSET 0x0000039c +#define MAC_PCU_BSSID2_L32_ADDR_MSB 31 +#define MAC_PCU_BSSID2_L32_ADDR_LSB 0 +#define MAC_PCU_BSSID2_L32_ADDR_MASK 0xffffffff +#define MAC_PCU_BSSID2_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_L32_ADDR_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB) +#define MAC_PCU_BSSID2_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_L32_ADDR_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK) + +#define MAC_PCU_BSSID2_U16_ADDRESS 0x000083a0 +#define MAC_PCU_BSSID2_U16_OFFSET 0x000003a0 +#define MAC_PCU_BSSID2_U16_ENABLE_MSB 16 +#define MAC_PCU_BSSID2_U16_ENABLE_LSB 16 +#define MAC_PCU_BSSID2_U16_ENABLE_MASK 0x00010000 +#define MAC_PCU_BSSID2_U16_ENABLE_GET(x) (((x) & MAC_PCU_BSSID2_U16_ENABLE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB) +#define MAC_PCU_BSSID2_U16_ENABLE_SET(x) (((x) << MAC_PCU_BSSID2_U16_ENABLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK) +#define MAC_PCU_BSSID2_U16_ADDR_MSB 15 +#define MAC_PCU_BSSID2_U16_ADDR_LSB 0 +#define MAC_PCU_BSSID2_U16_ADDR_MASK 0x0000ffff +#define MAC_PCU_BSSID2_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_U16_ADDR_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB) +#define MAC_PCU_BSSID2_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_U16_ADDR_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK) + +#define MAC_PCU_TSF1_STATUS_L32_ADDRESS 0x000083a4 +#define MAC_PCU_TSF1_STATUS_L32_OFFSET 0x000003a4 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB 31 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB 0 +#define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) +#define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) + +#define MAC_PCU_TSF1_STATUS_U32_ADDRESS 0x000083a8 +#define MAC_PCU_TSF1_STATUS_U32_OFFSET 0x000003a8 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB 31 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB 0 +#define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) +#define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) + +#define MAC_PCU_TSF2_STATUS_L32_ADDRESS 0x000083ac +#define MAC_PCU_TSF2_STATUS_L32_OFFSET 0x000003ac +#define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB 31 +#define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB 0 +#define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) +#define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) + +#define MAC_PCU_TSF2_STATUS_U32_ADDRESS 0x000083b0 +#define MAC_PCU_TSF2_STATUS_U32_OFFSET 0x000003b0 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB 31 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB 0 +#define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) +#define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) + +#define MAC_PCU_TXBUF_BA_ADDRESS 0x00008400 +#define MAC_PCU_TXBUF_BA_OFFSET 0x00000400 +#define MAC_PCU_TXBUF_BA_DATA_MSB 31 +#define MAC_PCU_TXBUF_BA_DATA_LSB 0 +#define MAC_PCU_TXBUF_BA_DATA_MASK 0xffffffff +#define MAC_PCU_TXBUF_BA_DATA_GET(x) (((x) & MAC_PCU_TXBUF_BA_DATA_MASK) >> MAC_PCU_TXBUF_BA_DATA_LSB) +#define MAC_PCU_TXBUF_BA_DATA_SET(x) (((x) << MAC_PCU_TXBUF_BA_DATA_LSB) & MAC_PCU_TXBUF_BA_DATA_MASK) + +#define MAC_PCU_KEY_CACHE_1_ADDRESS 0x00008800 +#define MAC_PCU_KEY_CACHE_1_OFFSET 0x00000800 +#define MAC_PCU_KEY_CACHE_1_DATA_MSB 31 +#define MAC_PCU_KEY_CACHE_1_DATA_LSB 0 +#define MAC_PCU_KEY_CACHE_1_DATA_MASK 0xffffffff +#define MAC_PCU_KEY_CACHE_1_DATA_GET(x) (((x) & MAC_PCU_KEY_CACHE_1_DATA_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB) +#define MAC_PCU_KEY_CACHE_1_DATA_SET(x) (((x) << MAC_PCU_KEY_CACHE_1_DATA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK) + +#define MAC_PCU_BASEBAND_0_ADDRESS 0x00009800 +#define MAC_PCU_BASEBAND_0_OFFSET 0x00001800 +#define MAC_PCU_BASEBAND_0_DATA_MSB 31 +#define MAC_PCU_BASEBAND_0_DATA_LSB 0 +#define MAC_PCU_BASEBAND_0_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_0_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_0_DATA_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB) +#define MAC_PCU_BASEBAND_0_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_0_DATA_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK) + +#define MAC_PCU_BASEBAND_1_ADDRESS 0x0000a000 +#define MAC_PCU_BASEBAND_1_OFFSET 0x00002000 +#define MAC_PCU_BASEBAND_1_DATA_MSB 31 +#define MAC_PCU_BASEBAND_1_DATA_LSB 0 +#define MAC_PCU_BASEBAND_1_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_1_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_1_DATA_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB) +#define MAC_PCU_BASEBAND_1_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_1_DATA_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK) + +#define MAC_PCU_BASEBAND_2_ADDRESS 0x0000c000 +#define MAC_PCU_BASEBAND_2_OFFSET 0x00004000 +#define MAC_PCU_BASEBAND_2_DATA_MSB 31 +#define MAC_PCU_BASEBAND_2_DATA_LSB 0 +#define MAC_PCU_BASEBAND_2_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_2_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_2_DATA_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB) +#define MAC_PCU_BASEBAND_2_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_2_DATA_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK) + +#define MAC_PCU_BASEBAND_3_ADDRESS 0x0000d000 +#define MAC_PCU_BASEBAND_3_OFFSET 0x00005000 +#define MAC_PCU_BASEBAND_3_DATA_MSB 31 +#define MAC_PCU_BASEBAND_3_DATA_LSB 0 +#define MAC_PCU_BASEBAND_3_DATA_MASK 0xffffffff +#define MAC_PCU_BASEBAND_3_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_3_DATA_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB) +#define MAC_PCU_BASEBAND_3_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_3_DATA_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK) + +#define MAC_PCU_BUF_ADDRESS 0x0000e000 +#define MAC_PCU_BUF_OFFSET 0x00006000 +#define MAC_PCU_BUF_DATA_MSB 31 +#define MAC_PCU_BUF_DATA_LSB 0 +#define MAC_PCU_BUF_DATA_MASK 0xffffffff +#define MAC_PCU_BUF_DATA_GET(x) (((x) & MAC_PCU_BUF_DATA_MASK) >> MAC_PCU_BUF_DATA_LSB) +#define MAC_PCU_BUF_DATA_SET(x) (((x) << MAC_PCU_BUF_DATA_LSB) & MAC_PCU_BUF_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mac_pcu_reg_s { + volatile unsigned int mac_pcu_sta_addr_l32; + volatile unsigned int mac_pcu_sta_addr_u16; + volatile unsigned int mac_pcu_bssid_l32; + volatile unsigned int mac_pcu_bssid_u16; + volatile unsigned int mac_pcu_bcn_rssi_ave; + volatile unsigned int mac_pcu_ack_cts_timeout; + volatile unsigned int mac_pcu_bcn_rssi_ctl; + volatile unsigned int mac_pcu_usec_latency; + volatile unsigned int pcu_max_cfp_dur; + volatile unsigned int mac_pcu_rx_filter; + volatile unsigned int mac_pcu_mcast_filter_l32; + volatile unsigned int mac_pcu_mcast_filter_u32; + volatile unsigned int mac_pcu_diag_sw; + volatile unsigned int mac_pcu_tst_addac; + volatile unsigned int mac_pcu_def_antenna; + volatile unsigned int mac_pcu_aes_mute_mask_0; + volatile unsigned int mac_pcu_aes_mute_mask_1; + volatile unsigned int mac_pcu_gated_clks; + volatile unsigned int mac_pcu_obs_bus_2; + volatile unsigned int mac_pcu_obs_bus_1; + volatile unsigned int mac_pcu_dym_mimo_pwr_save; + volatile unsigned int mac_pcu_last_beacon_tsf; + volatile unsigned int mac_pcu_nav; + volatile unsigned int mac_pcu_rts_success_cnt; + volatile unsigned int mac_pcu_rts_fail_cnt; + volatile unsigned int mac_pcu_ack_fail_cnt; + volatile unsigned int mac_pcu_fcs_fail_cnt; + volatile unsigned int mac_pcu_beacon_cnt; + volatile unsigned int mac_pcu_xrmode; + volatile unsigned int mac_pcu_xrdel; + volatile unsigned int mac_pcu_xrto; + volatile unsigned int mac_pcu_xrcrp; + volatile unsigned int mac_pcu_xrstmp; + volatile unsigned int mac_pcu_addr1_mask_l32; + volatile unsigned int mac_pcu_addr1_mask_u16; + volatile unsigned int mac_pcu_tpc; + volatile unsigned int mac_pcu_tx_frame_cnt; + volatile unsigned int mac_pcu_rx_frame_cnt; + volatile unsigned int mac_pcu_rx_clear_cnt; + volatile unsigned int mac_pcu_cycle_cnt; + volatile unsigned int mac_pcu_quiet_time_1; + volatile unsigned int mac_pcu_quiet_time_2; + volatile unsigned int mac_pcu_qos_no_ack; + volatile unsigned int mac_pcu_phy_error_mask; + volatile unsigned int mac_pcu_xrlat; + volatile unsigned int mac_pcu_rxbuf; + volatile unsigned int mac_pcu_mic_qos_control; + volatile unsigned int mac_pcu_mic_qos_select; + volatile unsigned int mac_pcu_misc_mode; + volatile unsigned int mac_pcu_filter_ofdm_cnt; + volatile unsigned int mac_pcu_filter_cck_cnt; + volatile unsigned int mac_pcu_phy_err_cnt_1; + volatile unsigned int mac_pcu_phy_err_cnt_1_mask; + volatile unsigned int mac_pcu_phy_err_cnt_2; + volatile unsigned int mac_pcu_phy_err_cnt_2_mask; + volatile unsigned int mac_pcu_tsf_threshold; + volatile unsigned int mac_pcu_phy_error_eifs_mask; + volatile unsigned int mac_pcu_phy_err_cnt_3; + volatile unsigned int mac_pcu_phy_err_cnt_3_mask; + volatile unsigned int mac_pcu_bluetooth_mode; + volatile unsigned int mac_pcu_bluetooth_weights; + volatile unsigned int mac_pcu_bluetooth_mode2; + volatile unsigned int mac_pcu_txsifs; + volatile unsigned int mac_pcu_txop_x; + volatile unsigned int mac_pcu_txop_0_3; + volatile unsigned int mac_pcu_txop_4_7; + volatile unsigned int mac_pcu_txop_8_11; + volatile unsigned int mac_pcu_txop_12_15; + volatile unsigned int mac_pcu_logic_analyzer; + volatile unsigned int mac_pcu_logic_analyzer_32l; + volatile unsigned int mac_pcu_logic_analyzer_16u; + volatile unsigned int mac_pcu_phy_err_cnt_mask_cont; + volatile unsigned int mac_pcu_azimuth_mode; + volatile unsigned int mac_pcu_20_40_mode; + volatile unsigned int mac_pcu_rx_clear_diff_cnt; + volatile unsigned int mac_pcu_self_gen_antenna_mask; + volatile unsigned int mac_pcu_ba_bar_control; + volatile unsigned int mac_pcu_legacy_plcp_spoof; + volatile unsigned int mac_pcu_phy_error_mask_cont; + volatile unsigned int mac_pcu_tx_timer; + volatile unsigned int mac_pcu_txbuf_ctrl; + volatile unsigned int mac_pcu_misc_mode2; + volatile unsigned int mac_pcu_alt_aes_mute_mask; + volatile unsigned int mac_pcu_azimuth_time_stamp; + volatile unsigned int mac_pcu_max_cfp_dur; + volatile unsigned int mac_pcu_hcf_timeout; + volatile unsigned int mac_pcu_bluetooth_weights2; + volatile unsigned int mac_pcu_bluetooth_tsf_bt_active; + volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority; + volatile unsigned int mac_pcu_bluetooth_mode3; + volatile unsigned int mac_pcu_bluetooth_mode4; + unsigned char pad0[148]; /* pad to 0x200 */ + volatile unsigned int mac_pcu_bt_bt[64]; + volatile unsigned int mac_pcu_bt_bt_async; + volatile unsigned int mac_pcu_bt_wl_1; + volatile unsigned int mac_pcu_bt_wl_2; + volatile unsigned int mac_pcu_bt_wl_3; + volatile unsigned int mac_pcu_bt_wl_4; + volatile unsigned int mac_pcu_coex_epta; + volatile unsigned int mac_pcu_coex_lnamaxgain1; + volatile unsigned int mac_pcu_coex_lnamaxgain2; + volatile unsigned int mac_pcu_coex_lnamaxgain3; + volatile unsigned int mac_pcu_coex_lnamaxgain4; + volatile unsigned int mac_pcu_basic_rate_set0; + volatile unsigned int mac_pcu_basic_rate_set1; + volatile unsigned int mac_pcu_basic_rate_set2; + volatile unsigned int mac_pcu_basic_rate_set3; + volatile unsigned int mac_pcu_rx_int_status0; + volatile unsigned int mac_pcu_rx_int_status1; + volatile unsigned int mac_pcu_rx_int_status2; + volatile unsigned int mac_pcu_rx_int_status3; + volatile unsigned int ht_half_gi_rate1; + volatile unsigned int ht_half_gi_rate2; + volatile unsigned int ht_full_gi_rate1; + volatile unsigned int ht_full_gi_rate2; + volatile unsigned int legacy_rate1; + volatile unsigned int legacy_rate2; + volatile unsigned int legacy_rate3; + volatile unsigned int rx_int_filter; + volatile unsigned int rx_int_overflow; + volatile unsigned int rx_filter_thresh; + volatile unsigned int rx_filter_thresh1; + volatile unsigned int rx_priority_thresh0; + volatile unsigned int rx_priority_thresh1; + volatile unsigned int rx_priority_thresh2; + volatile unsigned int rx_priority_thresh3; + volatile unsigned int rx_priority_offset0; + volatile unsigned int rx_priority_offset1; + volatile unsigned int rx_priority_offset2; + volatile unsigned int rx_priority_offset3; + volatile unsigned int rx_priority_offset4; + volatile unsigned int rx_priority_offset5; + volatile unsigned int mac_pcu_bssid2_l32; + volatile unsigned int mac_pcu_bssid2_u16; + volatile unsigned int mac_pcu_tsf1_status_l32; + volatile unsigned int mac_pcu_tsf1_status_u32; + volatile unsigned int mac_pcu_tsf2_status_l32; + volatile unsigned int mac_pcu_tsf2_status_u32; + unsigned char pad1[76]; /* pad to 0x400 */ + volatile unsigned int mac_pcu_txbuf_ba[64]; + unsigned char pad2[768]; /* pad to 0x800 */ + volatile unsigned int mac_pcu_key_cache_1[256]; + unsigned char pad3[3072]; /* pad to 0x1800 */ + volatile unsigned int mac_pcu_baseband_0[512]; + volatile unsigned int mac_pcu_baseband_1[2048]; + volatile unsigned int mac_pcu_baseband_2[1024]; + volatile unsigned int mac_pcu_baseband_3[1024]; + volatile unsigned int mac_pcu_buf[512]; +} mac_pcu_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MAC_PCU_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h new file mode 100644 index 000000000000..e84e2e011ca2 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_host_reg.h @@ -0,0 +1,33 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "mbox_wlan_host_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h new file mode 100644 index 000000000000..2ac8528987d4 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_reg.h @@ -0,0 +1,556 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "mbox_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS +#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET +#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB +#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB +#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK +#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x) +#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x) +#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS +#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET +#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB +#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB +#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK +#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) +#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) +#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB +#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB +#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK +#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x) +#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x) +#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS +#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET +#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB +#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB +#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK +#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) +#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) +#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB +#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB +#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK +#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) +#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) +#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB +#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB +#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK +#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) +#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) +#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB +#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB +#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK +#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) +#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS +#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET +#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB +#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB +#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK +#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB +#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB +#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK +#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) +#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) +#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB +#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB +#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK +#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS +#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET +#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB +#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB +#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK +#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB +#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB +#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK +#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) +#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) +#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB +#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB +#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK +#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS +#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET +#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB +#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB +#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK +#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB +#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB +#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK +#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) +#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) +#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB +#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB +#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK +#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS +#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET +#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB +#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB +#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK +#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB +#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB +#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK +#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) +#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) +#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB +#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB +#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK +#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS +#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET +#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB +#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB +#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK +#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB +#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB +#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK +#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) +#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) +#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB +#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB +#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK +#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS +#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET +#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB +#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB +#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK +#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB +#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB +#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK +#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) +#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) +#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB +#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB +#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK +#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS +#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET +#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB +#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB +#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK +#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) +#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) +#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB +#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB +#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK +#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) +#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) +#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB +#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB +#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK +#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) +#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS +#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET +#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB +#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB +#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK +#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) +#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) +#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB +#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB +#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK +#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) +#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) +#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB +#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB +#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK +#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) +#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) +#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS +#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) +#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) +#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) +#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) +#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB +#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB +#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK +#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) +#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) +#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB +#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB +#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK +#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) +#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB +#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB +#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK +#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) +#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) +#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB +#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB +#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK +#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) +#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) +#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB +#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB +#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK +#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x) +#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x) +#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS +#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) +#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) +#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB +#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB +#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK +#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) +#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB +#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB +#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK +#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) +#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) +#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) +#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB +#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB +#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK +#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) +#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) +#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB +#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB +#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK +#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x) +#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x) +#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS +#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET +#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB +#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB +#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK +#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x) +#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x) +#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS +#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET +#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB +#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB +#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK +#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x) +#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x) +#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS +#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET +#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB +#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB +#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK +#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x) +#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x) +#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS +#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET +#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB +#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB +#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK +#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x) +#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x) +#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS +#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET +#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB +#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB +#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK +#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) +#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) +#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS +#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET +#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB +#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB +#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK +#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) +#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) +#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS +#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET +#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB +#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB +#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK +#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x) +#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x) +#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS +#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET +#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB +#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB +#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK +#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x) +#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x) +#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS +#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET +#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB +#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB +#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK +#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x) +#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x) +#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS +#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET +#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB +#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB +#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK +#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x) +#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x) +#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS +#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET +#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB +#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB +#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK +#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x) +#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x) +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS +#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET +#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB +#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB +#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK +#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) +#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) +#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB +#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB +#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK +#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) +#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) +#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB +#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB +#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK +#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) +#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) +#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) +#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS +#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET +#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB +#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB +#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK +#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) +#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) +#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB +#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB +#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK +#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) +#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) +#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB +#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB +#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK +#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) +#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) +#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS +#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET +#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB +#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB +#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK +#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) +#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) +#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB +#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB +#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK +#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) +#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) +#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) +#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB +#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB +#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK +#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) +#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) +#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS +#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET +#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB +#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB +#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK +#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) +#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) +#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) +#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) +#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) +#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB +#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB +#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK +#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) +#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) +#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS +#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET +#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB +#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB +#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK +#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x) +#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x) + + +#endif +#endif + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h new file mode 100644 index 000000000000..dbad49ea0a01 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h @@ -0,0 +1,518 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_WLAN_HOST_REG_REG_H_ +#define _MBOX_WLAN_HOST_REG_REG_H_ + +#define HOST_INT_STATUS_ADDRESS 0x00000400 +#define HOST_INT_STATUS_OFFSET 0x00000400 +#define HOST_INT_STATUS_ERROR_MSB 7 +#define HOST_INT_STATUS_ERROR_LSB 7 +#define HOST_INT_STATUS_ERROR_MASK 0x00000080 +#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) +#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK) +#define HOST_INT_STATUS_CPU_MSB 6 +#define HOST_INT_STATUS_CPU_LSB 6 +#define HOST_INT_STATUS_CPU_MASK 0x00000040 +#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) +#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK) +#define HOST_INT_STATUS_INT_MSB 5 +#define HOST_INT_STATUS_INT_LSB 5 +#define HOST_INT_STATUS_INT_MASK 0x00000020 +#define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB) +#define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK) +#define HOST_INT_STATUS_COUNTER_MSB 4 +#define HOST_INT_STATUS_COUNTER_LSB 4 +#define HOST_INT_STATUS_COUNTER_MASK 0x00000010 +#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) +#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK) +#define HOST_INT_STATUS_MBOX_DATA_MSB 3 +#define HOST_INT_STATUS_MBOX_DATA_LSB 0 +#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f +#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB) +#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ADDRESS 0x00000401 +#define CPU_INT_STATUS_OFFSET 0x00000401 +#define CPU_INT_STATUS_BIT_MSB 7 +#define CPU_INT_STATUS_BIT_LSB 0 +#define CPU_INT_STATUS_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB) +#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK) + +#define ERROR_INT_STATUS_ADDRESS 0x00000402 +#define ERROR_INT_STATUS_OFFSET 0x00000402 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_SPI_MSB 3 +#define ERROR_INT_STATUS_SPI_LSB 3 +#define ERROR_INT_STATUS_SPI_MASK 0x00000008 +#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB) +#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK) +#define ERROR_INT_STATUS_WAKEUP_MSB 2 +#define ERROR_INT_STATUS_WAKEUP_LSB 2 +#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004 +#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB) +#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK) +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB) +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB) +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ADDRESS 0x00000403 +#define COUNTER_INT_STATUS_OFFSET 0x00000403 +#define COUNTER_INT_STATUS_COUNTER_MSB 7 +#define COUNTER_INT_STATUS_COUNTER_LSB 0 +#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff +#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB) +#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK) + +#define MBOX_FRAME_ADDRESS 0x00000404 +#define MBOX_FRAME_OFFSET 0x00000404 +#define MBOX_FRAME_RX_EOM_MSB 7 +#define MBOX_FRAME_RX_EOM_LSB 4 +#define MBOX_FRAME_RX_EOM_MASK 0x000000f0 +#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB) +#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK) +#define MBOX_FRAME_RX_SOM_MSB 3 +#define MBOX_FRAME_RX_SOM_LSB 0 +#define MBOX_FRAME_RX_SOM_MASK 0x0000000f +#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB) +#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK) + +#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 +#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405 +#define RX_LOOKAHEAD_VALID_MBOX_MSB 3 +#define RX_LOOKAHEAD_VALID_MBOX_LSB 0 +#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f +#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB) +#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK) + +#define HOST_INT_STATUS2_ADDRESS 0x00000406 +#define HOST_INT_STATUS2_OFFSET 0x00000406 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004 +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) +#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002 +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) +#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) +#define HOST_INT_STATUS2_GMBOX_DATA_MSB 0 +#define HOST_INT_STATUS2_GMBOX_DATA_LSB 0 +#define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001 +#define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB) +#define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK) + +#define GMBOX_RX_AVAIL_ADDRESS 0x00000407 +#define GMBOX_RX_AVAIL_OFFSET 0x00000407 +#define GMBOX_RX_AVAIL_BYTE_MSB 6 +#define GMBOX_RX_AVAIL_BYTE_LSB 0 +#define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f +#define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB) +#define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK) + +#define RX_LOOKAHEAD0_ADDRESS 0x00000408 +#define RX_LOOKAHEAD0_OFFSET 0x00000408 +#define RX_LOOKAHEAD0_DATA_MSB 7 +#define RX_LOOKAHEAD0_DATA_LSB 0 +#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB) +#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK) + +#define RX_LOOKAHEAD1_ADDRESS 0x0000040c +#define RX_LOOKAHEAD1_OFFSET 0x0000040c +#define RX_LOOKAHEAD1_DATA_MSB 7 +#define RX_LOOKAHEAD1_DATA_LSB 0 +#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB) +#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK) + +#define RX_LOOKAHEAD2_ADDRESS 0x00000410 +#define RX_LOOKAHEAD2_OFFSET 0x00000410 +#define RX_LOOKAHEAD2_DATA_MSB 7 +#define RX_LOOKAHEAD2_DATA_LSB 0 +#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB) +#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK) + +#define RX_LOOKAHEAD3_ADDRESS 0x00000414 +#define RX_LOOKAHEAD3_OFFSET 0x00000414 +#define RX_LOOKAHEAD3_DATA_MSB 7 +#define RX_LOOKAHEAD3_DATA_LSB 0 +#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff +#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB) +#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK) + +#define INT_STATUS_ENABLE_ADDRESS 0x00000418 +#define INT_STATUS_ENABLE_OFFSET 0x00000418 +#define INT_STATUS_ENABLE_ERROR_MSB 7 +#define INT_STATUS_ENABLE_ERROR_LSB 7 +#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080 +#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB) +#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) +#define INT_STATUS_ENABLE_CPU_MSB 6 +#define INT_STATUS_ENABLE_CPU_LSB 6 +#define INT_STATUS_ENABLE_CPU_MASK 0x00000040 +#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB) +#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) +#define INT_STATUS_ENABLE_INT_MSB 5 +#define INT_STATUS_ENABLE_INT_LSB 5 +#define INT_STATUS_ENABLE_INT_MASK 0x00000020 +#define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB) +#define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK) +#define INT_STATUS_ENABLE_COUNTER_MSB 4 +#define INT_STATUS_ENABLE_COUNTER_LSB 4 +#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 +#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB) +#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK) +#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB) +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK) + +#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 +#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419 +#define CPU_INT_STATUS_ENABLE_BIT_MSB 7 +#define CPU_INT_STATUS_ENABLE_BIT_LSB 0 +#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB) +#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK) + +#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a +#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010 +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2 +#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004 +#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB) +#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) + +#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB) +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) + +#define COUNT_ADDRESS 0x00000420 +#define COUNT_OFFSET 0x00000420 +#define COUNT_VALUE_MSB 7 +#define COUNT_VALUE_LSB 0 +#define COUNT_VALUE_MASK 0x000000ff +#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB) +#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK) + +#define COUNT_DEC_ADDRESS 0x00000440 +#define COUNT_DEC_OFFSET 0x00000440 +#define COUNT_DEC_VALUE_MSB 7 +#define COUNT_DEC_VALUE_LSB 0 +#define COUNT_DEC_VALUE_MASK 0x000000ff +#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB) +#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK) + +#define SCRATCH_ADDRESS 0x00000460 +#define SCRATCH_OFFSET 0x00000460 +#define SCRATCH_VALUE_MSB 7 +#define SCRATCH_VALUE_LSB 0 +#define SCRATCH_VALUE_MASK 0x000000ff +#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB) +#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK) + +#define FIFO_TIMEOUT_ADDRESS 0x00000468 +#define FIFO_TIMEOUT_OFFSET 0x00000468 +#define FIFO_TIMEOUT_VALUE_MSB 7 +#define FIFO_TIMEOUT_VALUE_LSB 0 +#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB) +#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK) + +#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469 +#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469 +#define FIFO_TIMEOUT_ENABLE_SET_MSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_LSB 0 +#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001 +#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB) +#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK) + +#define DISABLE_SLEEP_ADDRESS 0x0000046a +#define DISABLE_SLEEP_OFFSET 0x0000046a +#define DISABLE_SLEEP_FOR_INT_MSB 1 +#define DISABLE_SLEEP_FOR_INT_LSB 1 +#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002 +#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB) +#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK) +#define DISABLE_SLEEP_ON_MSB 0 +#define DISABLE_SLEEP_ON_LSB 0 +#define DISABLE_SLEEP_ON_MASK 0x00000001 +#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB) +#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK) + +#define LOCAL_BUS_ADDRESS 0x00000470 +#define LOCAL_BUS_OFFSET 0x00000470 +#define LOCAL_BUS_STATE_MSB 1 +#define LOCAL_BUS_STATE_LSB 0 +#define LOCAL_BUS_STATE_MASK 0x00000003 +#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB) +#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK) + +#define INT_WLAN_ADDRESS 0x00000472 +#define INT_WLAN_OFFSET 0x00000472 +#define INT_WLAN_VECTOR_MSB 7 +#define INT_WLAN_VECTOR_LSB 0 +#define INT_WLAN_VECTOR_MASK 0x000000ff +#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB) +#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK) + +#define WINDOW_DATA_ADDRESS 0x00000474 +#define WINDOW_DATA_OFFSET 0x00000474 +#define WINDOW_DATA_DATA_MSB 7 +#define WINDOW_DATA_DATA_LSB 0 +#define WINDOW_DATA_DATA_MASK 0x000000ff +#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB) +#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK) + +#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 +#define WINDOW_WRITE_ADDR_OFFSET 0x00000478 +#define WINDOW_WRITE_ADDR_ADDR_MSB 7 +#define WINDOW_WRITE_ADDR_ADDR_LSB 0 +#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB) +#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK) + +#define WINDOW_READ_ADDR_ADDRESS 0x0000047c +#define WINDOW_READ_ADDR_OFFSET 0x0000047c +#define WINDOW_READ_ADDR_ADDR_MSB 7 +#define WINDOW_READ_ADDR_ADDR_LSB 0 +#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff +#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB) +#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK) + +#define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480 +#define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010 +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) +#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008 +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) +#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004 +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) +#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003 +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) +#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) + +#define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481 +#define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008 +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2 +#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2 +#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004 +#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1 +#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1 +#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002 +#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB) +#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) +#define HOST_CTRL_SPI_STATUS_READY_MSB 0 +#define HOST_CTRL_SPI_STATUS_READY_LSB 0 +#define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001 +#define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB) +#define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK) + +#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482 +#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482 +#define NON_ASSOC_SLEEP_EN_BIT_MSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_LSB 0 +#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001 +#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB) +#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK) + +#define CPU_DBG_SEL_ADDRESS 0x00000483 +#define CPU_DBG_SEL_OFFSET 0x00000483 +#define CPU_DBG_SEL_BIT_MSB 5 +#define CPU_DBG_SEL_BIT_LSB 0 +#define CPU_DBG_SEL_BIT_MASK 0x0000003f +#define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB) +#define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK) + +#define CPU_DBG_ADDRESS 0x00000484 +#define CPU_DBG_OFFSET 0x00000484 +#define CPU_DBG_DATA_MSB 7 +#define CPU_DBG_DATA_LSB 0 +#define CPU_DBG_DATA_MASK 0x000000ff +#define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB) +#define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK) + +#define INT_STATUS2_ENABLE_ADDRESS 0x00000488 +#define INT_STATUS2_ENABLE_OFFSET 0x00000488 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004 +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) +#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002 +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) +#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) +#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0 +#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0 +#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001 +#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB) +#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) + +#define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490 +#define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490 +#define GMBOX_RX_LOOKAHEAD_DATA_MSB 7 +#define GMBOX_RX_LOOKAHEAD_DATA_LSB 0 +#define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff +#define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB) +#define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK) + +#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498 +#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001 +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) +#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) + +#define CIS_WINDOW_ADDRESS 0x00000600 +#define CIS_WINDOW_OFFSET 0x00000600 +#define CIS_WINDOW_DATA_MSB 7 +#define CIS_WINDOW_DATA_LSB 0 +#define CIS_WINDOW_DATA_MASK 0x000000ff +#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB) +#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_wlan_host_reg_reg_s { + unsigned char pad0[1024]; /* pad to 0x400 */ + volatile unsigned char host_int_status; + volatile unsigned char cpu_int_status; + volatile unsigned char error_int_status; + volatile unsigned char counter_int_status; + volatile unsigned char mbox_frame; + volatile unsigned char rx_lookahead_valid; + volatile unsigned char host_int_status2; + volatile unsigned char gmbox_rx_avail; + volatile unsigned char rx_lookahead0[4]; + volatile unsigned char rx_lookahead1[4]; + volatile unsigned char rx_lookahead2[4]; + volatile unsigned char rx_lookahead3[4]; + volatile unsigned char int_status_enable; + volatile unsigned char cpu_int_status_enable; + volatile unsigned char error_status_enable; + volatile unsigned char counter_int_status_enable; + unsigned char pad1[4]; /* pad to 0x420 */ + volatile unsigned char count[8]; + unsigned char pad2[24]; /* pad to 0x440 */ + volatile unsigned char count_dec[32]; + volatile unsigned char scratch[8]; + volatile unsigned char fifo_timeout; + volatile unsigned char fifo_timeout_enable; + volatile unsigned char disable_sleep; + unsigned char pad3[5]; /* pad to 0x470 */ + volatile unsigned char local_bus; + unsigned char pad4[1]; /* pad to 0x472 */ + volatile unsigned char int_wlan; + unsigned char pad5[1]; /* pad to 0x474 */ + volatile unsigned char window_data[4]; + volatile unsigned char window_write_addr[4]; + volatile unsigned char window_read_addr[4]; + volatile unsigned char host_ctrl_spi_config; + volatile unsigned char host_ctrl_spi_status; + volatile unsigned char non_assoc_sleep_en; + volatile unsigned char cpu_dbg_sel; + volatile unsigned char cpu_dbg[4]; + volatile unsigned char int_status2_enable; + unsigned char pad6[7]; /* pad to 0x490 */ + volatile unsigned char gmbox_rx_lookahead[8]; + volatile unsigned char gmbox_rx_lookahead_mux; + unsigned char pad7[359]; /* pad to 0x600 */ + volatile unsigned char cis_window[512]; +} mbox_wlan_host_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_WLAN_HOST_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h new file mode 100644 index 000000000000..55d20216ec11 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/mbox_wlan_reg.h @@ -0,0 +1,634 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _MBOX_WLAN_REG_REG_H_ +#define _MBOX_WLAN_REG_REG_H_ + +#define WLAN_MBOX_FIFO_ADDRESS 0x00000000 +#define WLAN_MBOX_FIFO_OFFSET 0x00000000 +#define WLAN_MBOX_FIFO_DATA_MSB 19 +#define WLAN_MBOX_FIFO_DATA_LSB 0 +#define WLAN_MBOX_FIFO_DATA_MASK 0x000fffff +#define WLAN_MBOX_FIFO_DATA_GET(x) (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB) +#define WLAN_MBOX_FIFO_DATA_SET(x) (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK) + +#define WLAN_MBOX_FIFO_STATUS_ADDRESS 0x00000010 +#define WLAN_MBOX_FIFO_STATUS_OFFSET 0x00000010 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB 19 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB 16 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000 +#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) +#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) +#define WLAN_MBOX_FIFO_STATUS_FULL_MSB 15 +#define WLAN_MBOX_FIFO_STATUS_FULL_LSB 12 +#define WLAN_MBOX_FIFO_STATUS_FULL_MASK 0x0000f000 +#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB) +#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) + +#define WLAN_MBOX_DMA_POLICY_ADDRESS 0x00000014 +#define WLAN_MBOX_DMA_POLICY_OFFSET 0x00000014 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) +#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) +#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) + +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c +#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024 +#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c +#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034 +#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c +#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044 +#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c +#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054 +#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_MBOX_INT_STATUS_ADDRESS 0x00000058 +#define WLAN_MBOX_INT_STATUS_OFFSET 0x00000058 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000 +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000 +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB 17 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB 17 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000 +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000 +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000 +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB 11 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB 8 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00 +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) +#define WLAN_MBOX_INT_STATUS_HOST_MSB 7 +#define WLAN_MBOX_INT_STATUS_HOST_LSB 0 +#define WLAN_MBOX_INT_STATUS_HOST_MASK 0x000000ff +#define WLAN_MBOX_INT_STATUS_HOST_GET(x) (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB) +#define WLAN_MBOX_INT_STATUS_HOST_SET(x) (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK) + +#define WLAN_MBOX_INT_ENABLE_ADDRESS 0x0000005c +#define WLAN_MBOX_INT_ENABLE_OFFSET 0x0000005c +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000 +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000 +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000 +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000 +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000 +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00 +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) +#define WLAN_MBOX_INT_ENABLE_HOST_MSB 7 +#define WLAN_MBOX_INT_ENABLE_HOST_LSB 0 +#define WLAN_MBOX_INT_ENABLE_HOST_MASK 0x000000ff +#define WLAN_MBOX_INT_ENABLE_HOST_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB) +#define WLAN_MBOX_INT_ENABLE_HOST_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK) + +#define WLAN_INT_HOST_ADDRESS 0x00000060 +#define WLAN_INT_HOST_OFFSET 0x00000060 +#define WLAN_INT_HOST_VECTOR_MSB 7 +#define WLAN_INT_HOST_VECTOR_LSB 0 +#define WLAN_INT_HOST_VECTOR_MASK 0x000000ff +#define WLAN_INT_HOST_VECTOR_GET(x) (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB) +#define WLAN_INT_HOST_VECTOR_SET(x) (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK) + +#define WLAN_LOCAL_COUNT_ADDRESS 0x00000080 +#define WLAN_LOCAL_COUNT_OFFSET 0x00000080 +#define WLAN_LOCAL_COUNT_VALUE_MSB 7 +#define WLAN_LOCAL_COUNT_VALUE_LSB 0 +#define WLAN_LOCAL_COUNT_VALUE_MASK 0x000000ff +#define WLAN_LOCAL_COUNT_VALUE_GET(x) (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB) +#define WLAN_LOCAL_COUNT_VALUE_SET(x) (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK) + +#define WLAN_COUNT_INC_ADDRESS 0x000000a0 +#define WLAN_COUNT_INC_OFFSET 0x000000a0 +#define WLAN_COUNT_INC_VALUE_MSB 7 +#define WLAN_COUNT_INC_VALUE_LSB 0 +#define WLAN_COUNT_INC_VALUE_MASK 0x000000ff +#define WLAN_COUNT_INC_VALUE_GET(x) (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB) +#define WLAN_COUNT_INC_VALUE_SET(x) (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK) + +#define WLAN_LOCAL_SCRATCH_ADDRESS 0x000000c0 +#define WLAN_LOCAL_SCRATCH_OFFSET 0x000000c0 +#define WLAN_LOCAL_SCRATCH_VALUE_MSB 7 +#define WLAN_LOCAL_SCRATCH_VALUE_LSB 0 +#define WLAN_LOCAL_SCRATCH_VALUE_MASK 0x000000ff +#define WLAN_LOCAL_SCRATCH_VALUE_GET(x) (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB) +#define WLAN_LOCAL_SCRATCH_VALUE_SET(x) (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK) + +#define WLAN_USE_LOCAL_BUS_ADDRESS 0x000000e0 +#define WLAN_USE_LOCAL_BUS_OFFSET 0x000000e0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB 0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB 0 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001 +#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) +#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) + +#define WLAN_SDIO_CONFIG_ADDRESS 0x000000e4 +#define WLAN_SDIO_CONFIG_OFFSET 0x000000e4 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB 0 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB 0 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001 +#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) +#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) + +#define WLAN_MBOX_DEBUG_ADDRESS 0x000000e8 +#define WLAN_MBOX_DEBUG_OFFSET 0x000000e8 +#define WLAN_MBOX_DEBUG_SEL_MSB 2 +#define WLAN_MBOX_DEBUG_SEL_LSB 0 +#define WLAN_MBOX_DEBUG_SEL_MASK 0x00000007 +#define WLAN_MBOX_DEBUG_SEL_GET(x) (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB) +#define WLAN_MBOX_DEBUG_SEL_SET(x) (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK) + +#define WLAN_MBOX_FIFO_RESET_ADDRESS 0x000000ec +#define WLAN_MBOX_FIFO_RESET_OFFSET 0x000000ec +#define WLAN_MBOX_FIFO_RESET_INIT_MSB 0 +#define WLAN_MBOX_FIFO_RESET_INIT_LSB 0 +#define WLAN_MBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define WLAN_MBOX_FIFO_RESET_INIT_GET(x) (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB) +#define WLAN_MBOX_FIFO_RESET_INIT_SET(x) (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK) + +#define WLAN_MBOX_TXFIFO_POP_ADDRESS 0x000000f0 +#define WLAN_MBOX_TXFIFO_POP_OFFSET 0x000000f0 +#define WLAN_MBOX_TXFIFO_POP_DATA_MSB 0 +#define WLAN_MBOX_TXFIFO_POP_DATA_LSB 0 +#define WLAN_MBOX_TXFIFO_POP_DATA_MASK 0x00000001 +#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB) +#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) + +#define WLAN_MBOX_RXFIFO_POP_ADDRESS 0x00000100 +#define WLAN_MBOX_RXFIFO_POP_OFFSET 0x00000100 +#define WLAN_MBOX_RXFIFO_POP_DATA_MSB 0 +#define WLAN_MBOX_RXFIFO_POP_DATA_LSB 0 +#define WLAN_MBOX_RXFIFO_POP_DATA_MASK 0x00000001 +#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB) +#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) + +#define WLAN_SDIO_DEBUG_ADDRESS 0x00000110 +#define WLAN_SDIO_DEBUG_OFFSET 0x00000110 +#define WLAN_SDIO_DEBUG_SEL_MSB 3 +#define WLAN_SDIO_DEBUG_SEL_LSB 0 +#define WLAN_SDIO_DEBUG_SEL_MASK 0x0000000f +#define WLAN_SDIO_DEBUG_SEL_GET(x) (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB) +#define WLAN_SDIO_DEBUG_SEL_SET(x) (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK) + +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000118 +#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET 0x00000118 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB 1 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB 1 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) +#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS 0x00000120 +#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET 0x00000120 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB 1 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB 1 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) +#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define WLAN_GMBOX_INT_STATUS_ADDRESS 0x00000124 +#define WLAN_GMBOX_INT_STATUS_OFFSET 0x00000124 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB 6 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB 6 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000040 +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB 5 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB 5 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000020 +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010 +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004 +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002 +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB 0 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB 0 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001 +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) + +#define WLAN_GMBOX_INT_ENABLE_ADDRESS 0x00000128 +#define WLAN_GMBOX_INT_ENABLE_OFFSET 0x00000128 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB 6 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB 6 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000040 +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 5 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 5 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000020 +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010 +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004 +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002 +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001 +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) + +#define WLAN_HOST_IF_WINDOW_ADDRESS 0x00002000 +#define WLAN_HOST_IF_WINDOW_OFFSET 0x00002000 +#define WLAN_HOST_IF_WINDOW_DATA_MSB 7 +#define WLAN_HOST_IF_WINDOW_DATA_LSB 0 +#define WLAN_HOST_IF_WINDOW_DATA_MASK 0x000000ff +#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB) +#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct mbox_wlan_reg_reg_s { + volatile unsigned int wlan_mbox_fifo[4]; + volatile unsigned int wlan_mbox_fifo_status; + volatile unsigned int wlan_mbox_dma_policy; + volatile unsigned int wlan_mbox0_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox0_dma_rx_control; + volatile unsigned int wlan_mbox0_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox0_dma_tx_control; + volatile unsigned int wlan_mbox1_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox1_dma_rx_control; + volatile unsigned int wlan_mbox1_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox1_dma_tx_control; + volatile unsigned int wlan_mbox2_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox2_dma_rx_control; + volatile unsigned int wlan_mbox2_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox2_dma_tx_control; + volatile unsigned int wlan_mbox3_dma_rx_descriptor_base; + volatile unsigned int wlan_mbox3_dma_rx_control; + volatile unsigned int wlan_mbox3_dma_tx_descriptor_base; + volatile unsigned int wlan_mbox3_dma_tx_control; + volatile unsigned int wlan_mbox_int_status; + volatile unsigned int wlan_mbox_int_enable; + volatile unsigned int wlan_int_host; + unsigned char pad0[28]; /* pad to 0x80 */ + volatile unsigned int wlan_local_count[8]; + volatile unsigned int wlan_count_inc[8]; + volatile unsigned int wlan_local_scratch[8]; + volatile unsigned int wlan_use_local_bus; + volatile unsigned int wlan_sdio_config; + volatile unsigned int wlan_mbox_debug; + volatile unsigned int wlan_mbox_fifo_reset; + volatile unsigned int wlan_mbox_txfifo_pop[4]; + volatile unsigned int wlan_mbox_rxfifo_pop[4]; + volatile unsigned int wlan_sdio_debug; + volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base; + volatile unsigned int wlan_gmbox0_dma_rx_control; + volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base; + volatile unsigned int wlan_gmbox0_dma_tx_control; + volatile unsigned int wlan_gmbox_int_status; + volatile unsigned int wlan_gmbox_int_enable; + unsigned char pad1[7892]; /* pad to 0x2000 */ + volatile unsigned int wlan_host_if_window[2048]; +} mbox_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _MBOX_WLAN_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h new file mode 100644 index 000000000000..cbf4acfa7925 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rdma_reg.h @@ -0,0 +1,560 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RDMA_REG_REG_H_ +#define _RDMA_REG_REG_H_ + +#define DMA_CONFIG_ADDRESS 0x00000000 +#define DMA_CONFIG_OFFSET 0x00000000 +#define DMA_CONFIG_WLBB_PWD_EN_MSB 4 +#define DMA_CONFIG_WLBB_PWD_EN_LSB 4 +#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010 +#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB) +#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK) +#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3 +#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3 +#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008 +#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB) +#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK) +#define DMA_CONFIG_ENABLE_RETENTION_MSB 2 +#define DMA_CONFIG_ENABLE_RETENTION_LSB 2 +#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004 +#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB) +#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK) +#define DMA_CONFIG_RTC_PRIORITY_MSB 1 +#define DMA_CONFIG_RTC_PRIORITY_LSB 1 +#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002 +#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB) +#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK) +#define DMA_CONFIG_DMA_TYPE_MSB 0 +#define DMA_CONFIG_DMA_TYPE_LSB 0 +#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001 +#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB) +#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK) + +#define DMA_CONTROL_ADDRESS 0x00000004 +#define DMA_CONTROL_OFFSET 0x00000004 +#define DMA_CONTROL_START_MSB 1 +#define DMA_CONTROL_START_LSB 1 +#define DMA_CONTROL_START_MASK 0x00000002 +#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB) +#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK) +#define DMA_CONTROL_STOP_MSB 0 +#define DMA_CONTROL_STOP_LSB 0 +#define DMA_CONTROL_STOP_MASK 0x00000001 +#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB) +#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK) + +#define DMA_SRC_ADDRESS 0x00000008 +#define DMA_SRC_OFFSET 0x00000008 +#define DMA_SRC_ADDR_MSB 31 +#define DMA_SRC_ADDR_LSB 2 +#define DMA_SRC_ADDR_MASK 0xfffffffc +#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB) +#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK) + +#define DMA_DEST_ADDRESS 0x0000000c +#define DMA_DEST_OFFSET 0x0000000c +#define DMA_DEST_ADDR_MSB 31 +#define DMA_DEST_ADDR_LSB 2 +#define DMA_DEST_ADDR_MASK 0xfffffffc +#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB) +#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK) + +#define DMA_LENGTH_ADDRESS 0x00000010 +#define DMA_LENGTH_OFFSET 0x00000010 +#define DMA_LENGTH_WORDS_MSB 11 +#define DMA_LENGTH_WORDS_LSB 0 +#define DMA_LENGTH_WORDS_MASK 0x00000fff +#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB) +#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK) + +#define VMC_BASE_ADDRESS 0x00000014 +#define VMC_BASE_OFFSET 0x00000014 +#define VMC_BASE_ADDR_MSB 31 +#define VMC_BASE_ADDR_LSB 2 +#define VMC_BASE_ADDR_MASK 0xfffffffc +#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB) +#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK) + +#define INDIRECT_REG_ADDRESS 0x00000018 +#define INDIRECT_REG_OFFSET 0x00000018 +#define INDIRECT_REG_ID_MSB 31 +#define INDIRECT_REG_ID_LSB 2 +#define INDIRECT_REG_ID_MASK 0xfffffffc +#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB) +#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK) + +#define INDIRECT_RETURN_ADDRESS 0x0000001c +#define INDIRECT_RETURN_OFFSET 0x0000001c +#define INDIRECT_RETURN_ADDR_MSB 31 +#define INDIRECT_RETURN_ADDR_LSB 2 +#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc +#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB) +#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK) + +#define RDMA_REGION_0__ADDRESS 0x00000020 +#define RDMA_REGION_0__OFFSET 0x00000020 +#define RDMA_REGION_0__ADDR_MSB 31 +#define RDMA_REGION_0__ADDR_LSB 13 +#define RDMA_REGION_0__ADDR_MASK 0xffffe000 +#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB) +#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK) +#define RDMA_REGION_0__LENGTH_MSB 12 +#define RDMA_REGION_0__LENGTH_LSB 2 +#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB) +#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK) +#define RDMA_REGION_0__INDI_MSB 1 +#define RDMA_REGION_0__INDI_LSB 1 +#define RDMA_REGION_0__INDI_MASK 0x00000002 +#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB) +#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK) +#define RDMA_REGION_0__NEXT_MSB 0 +#define RDMA_REGION_0__NEXT_LSB 0 +#define RDMA_REGION_0__NEXT_MASK 0x00000001 +#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB) +#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK) + +#define RDMA_REGION_1__ADDRESS 0x00000024 +#define RDMA_REGION_1__OFFSET 0x00000024 +#define RDMA_REGION_1__ADDR_MSB 31 +#define RDMA_REGION_1__ADDR_LSB 13 +#define RDMA_REGION_1__ADDR_MASK 0xffffe000 +#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB) +#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK) +#define RDMA_REGION_1__LENGTH_MSB 12 +#define RDMA_REGION_1__LENGTH_LSB 2 +#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB) +#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK) +#define RDMA_REGION_1__INDI_MSB 1 +#define RDMA_REGION_1__INDI_LSB 1 +#define RDMA_REGION_1__INDI_MASK 0x00000002 +#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB) +#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK) +#define RDMA_REGION_1__NEXT_MSB 0 +#define RDMA_REGION_1__NEXT_LSB 0 +#define RDMA_REGION_1__NEXT_MASK 0x00000001 +#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB) +#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK) + +#define RDMA_REGION_2__ADDRESS 0x00000028 +#define RDMA_REGION_2__OFFSET 0x00000028 +#define RDMA_REGION_2__ADDR_MSB 31 +#define RDMA_REGION_2__ADDR_LSB 13 +#define RDMA_REGION_2__ADDR_MASK 0xffffe000 +#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB) +#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK) +#define RDMA_REGION_2__LENGTH_MSB 12 +#define RDMA_REGION_2__LENGTH_LSB 2 +#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB) +#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK) +#define RDMA_REGION_2__INDI_MSB 1 +#define RDMA_REGION_2__INDI_LSB 1 +#define RDMA_REGION_2__INDI_MASK 0x00000002 +#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB) +#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK) +#define RDMA_REGION_2__NEXT_MSB 0 +#define RDMA_REGION_2__NEXT_LSB 0 +#define RDMA_REGION_2__NEXT_MASK 0x00000001 +#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB) +#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK) + +#define RDMA_REGION_3__ADDRESS 0x0000002c +#define RDMA_REGION_3__OFFSET 0x0000002c +#define RDMA_REGION_3__ADDR_MSB 31 +#define RDMA_REGION_3__ADDR_LSB 13 +#define RDMA_REGION_3__ADDR_MASK 0xffffe000 +#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB) +#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK) +#define RDMA_REGION_3__LENGTH_MSB 12 +#define RDMA_REGION_3__LENGTH_LSB 2 +#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB) +#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK) +#define RDMA_REGION_3__INDI_MSB 1 +#define RDMA_REGION_3__INDI_LSB 1 +#define RDMA_REGION_3__INDI_MASK 0x00000002 +#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB) +#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK) +#define RDMA_REGION_3__NEXT_MSB 0 +#define RDMA_REGION_3__NEXT_LSB 0 +#define RDMA_REGION_3__NEXT_MASK 0x00000001 +#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB) +#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK) + +#define RDMA_REGION_4__ADDRESS 0x00000030 +#define RDMA_REGION_4__OFFSET 0x00000030 +#define RDMA_REGION_4__ADDR_MSB 31 +#define RDMA_REGION_4__ADDR_LSB 13 +#define RDMA_REGION_4__ADDR_MASK 0xffffe000 +#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB) +#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK) +#define RDMA_REGION_4__LENGTH_MSB 12 +#define RDMA_REGION_4__LENGTH_LSB 2 +#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB) +#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK) +#define RDMA_REGION_4__INDI_MSB 1 +#define RDMA_REGION_4__INDI_LSB 1 +#define RDMA_REGION_4__INDI_MASK 0x00000002 +#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB) +#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK) +#define RDMA_REGION_4__NEXT_MSB 0 +#define RDMA_REGION_4__NEXT_LSB 0 +#define RDMA_REGION_4__NEXT_MASK 0x00000001 +#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB) +#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK) + +#define RDMA_REGION_5__ADDRESS 0x00000034 +#define RDMA_REGION_5__OFFSET 0x00000034 +#define RDMA_REGION_5__ADDR_MSB 31 +#define RDMA_REGION_5__ADDR_LSB 13 +#define RDMA_REGION_5__ADDR_MASK 0xffffe000 +#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB) +#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK) +#define RDMA_REGION_5__LENGTH_MSB 12 +#define RDMA_REGION_5__LENGTH_LSB 2 +#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB) +#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK) +#define RDMA_REGION_5__INDI_MSB 1 +#define RDMA_REGION_5__INDI_LSB 1 +#define RDMA_REGION_5__INDI_MASK 0x00000002 +#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB) +#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK) +#define RDMA_REGION_5__NEXT_MSB 0 +#define RDMA_REGION_5__NEXT_LSB 0 +#define RDMA_REGION_5__NEXT_MASK 0x00000001 +#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB) +#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK) + +#define RDMA_REGION_6__ADDRESS 0x00000038 +#define RDMA_REGION_6__OFFSET 0x00000038 +#define RDMA_REGION_6__ADDR_MSB 31 +#define RDMA_REGION_6__ADDR_LSB 13 +#define RDMA_REGION_6__ADDR_MASK 0xffffe000 +#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB) +#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK) +#define RDMA_REGION_6__LENGTH_MSB 12 +#define RDMA_REGION_6__LENGTH_LSB 2 +#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB) +#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK) +#define RDMA_REGION_6__INDI_MSB 1 +#define RDMA_REGION_6__INDI_LSB 1 +#define RDMA_REGION_6__INDI_MASK 0x00000002 +#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB) +#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK) +#define RDMA_REGION_6__NEXT_MSB 0 +#define RDMA_REGION_6__NEXT_LSB 0 +#define RDMA_REGION_6__NEXT_MASK 0x00000001 +#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB) +#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK) + +#define RDMA_REGION_7__ADDRESS 0x0000003c +#define RDMA_REGION_7__OFFSET 0x0000003c +#define RDMA_REGION_7__ADDR_MSB 31 +#define RDMA_REGION_7__ADDR_LSB 13 +#define RDMA_REGION_7__ADDR_MASK 0xffffe000 +#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB) +#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK) +#define RDMA_REGION_7__LENGTH_MSB 12 +#define RDMA_REGION_7__LENGTH_LSB 2 +#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB) +#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK) +#define RDMA_REGION_7__INDI_MSB 1 +#define RDMA_REGION_7__INDI_LSB 1 +#define RDMA_REGION_7__INDI_MASK 0x00000002 +#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB) +#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK) +#define RDMA_REGION_7__NEXT_MSB 0 +#define RDMA_REGION_7__NEXT_LSB 0 +#define RDMA_REGION_7__NEXT_MASK 0x00000001 +#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB) +#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK) + +#define RDMA_REGION_8__ADDRESS 0x00000040 +#define RDMA_REGION_8__OFFSET 0x00000040 +#define RDMA_REGION_8__ADDR_MSB 31 +#define RDMA_REGION_8__ADDR_LSB 13 +#define RDMA_REGION_8__ADDR_MASK 0xffffe000 +#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB) +#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK) +#define RDMA_REGION_8__LENGTH_MSB 12 +#define RDMA_REGION_8__LENGTH_LSB 2 +#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB) +#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK) +#define RDMA_REGION_8__INDI_MSB 1 +#define RDMA_REGION_8__INDI_LSB 1 +#define RDMA_REGION_8__INDI_MASK 0x00000002 +#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB) +#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK) +#define RDMA_REGION_8__NEXT_MSB 0 +#define RDMA_REGION_8__NEXT_LSB 0 +#define RDMA_REGION_8__NEXT_MASK 0x00000001 +#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB) +#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK) + +#define RDMA_REGION_9__ADDRESS 0x00000044 +#define RDMA_REGION_9__OFFSET 0x00000044 +#define RDMA_REGION_9__ADDR_MSB 31 +#define RDMA_REGION_9__ADDR_LSB 13 +#define RDMA_REGION_9__ADDR_MASK 0xffffe000 +#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB) +#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK) +#define RDMA_REGION_9__LENGTH_MSB 12 +#define RDMA_REGION_9__LENGTH_LSB 2 +#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB) +#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK) +#define RDMA_REGION_9__INDI_MSB 1 +#define RDMA_REGION_9__INDI_LSB 1 +#define RDMA_REGION_9__INDI_MASK 0x00000002 +#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB) +#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK) +#define RDMA_REGION_9__NEXT_MSB 0 +#define RDMA_REGION_9__NEXT_LSB 0 +#define RDMA_REGION_9__NEXT_MASK 0x00000001 +#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB) +#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK) + +#define RDMA_REGION_10__ADDRESS 0x00000048 +#define RDMA_REGION_10__OFFSET 0x00000048 +#define RDMA_REGION_10__ADDR_MSB 31 +#define RDMA_REGION_10__ADDR_LSB 13 +#define RDMA_REGION_10__ADDR_MASK 0xffffe000 +#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB) +#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK) +#define RDMA_REGION_10__LENGTH_MSB 12 +#define RDMA_REGION_10__LENGTH_LSB 2 +#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB) +#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK) +#define RDMA_REGION_10__INDI_MSB 1 +#define RDMA_REGION_10__INDI_LSB 1 +#define RDMA_REGION_10__INDI_MASK 0x00000002 +#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB) +#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK) +#define RDMA_REGION_10__NEXT_MSB 0 +#define RDMA_REGION_10__NEXT_LSB 0 +#define RDMA_REGION_10__NEXT_MASK 0x00000001 +#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB) +#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK) + +#define RDMA_REGION_11__ADDRESS 0x0000004c +#define RDMA_REGION_11__OFFSET 0x0000004c +#define RDMA_REGION_11__ADDR_MSB 31 +#define RDMA_REGION_11__ADDR_LSB 13 +#define RDMA_REGION_11__ADDR_MASK 0xffffe000 +#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB) +#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK) +#define RDMA_REGION_11__LENGTH_MSB 12 +#define RDMA_REGION_11__LENGTH_LSB 2 +#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB) +#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK) +#define RDMA_REGION_11__INDI_MSB 1 +#define RDMA_REGION_11__INDI_LSB 1 +#define RDMA_REGION_11__INDI_MASK 0x00000002 +#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB) +#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK) +#define RDMA_REGION_11__NEXT_MSB 0 +#define RDMA_REGION_11__NEXT_LSB 0 +#define RDMA_REGION_11__NEXT_MASK 0x00000001 +#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB) +#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK) + +#define RDMA_REGION_12__ADDRESS 0x00000050 +#define RDMA_REGION_12__OFFSET 0x00000050 +#define RDMA_REGION_12__ADDR_MSB 31 +#define RDMA_REGION_12__ADDR_LSB 13 +#define RDMA_REGION_12__ADDR_MASK 0xffffe000 +#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB) +#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK) +#define RDMA_REGION_12__LENGTH_MSB 12 +#define RDMA_REGION_12__LENGTH_LSB 2 +#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB) +#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK) +#define RDMA_REGION_12__INDI_MSB 1 +#define RDMA_REGION_12__INDI_LSB 1 +#define RDMA_REGION_12__INDI_MASK 0x00000002 +#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB) +#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK) +#define RDMA_REGION_12__NEXT_MSB 0 +#define RDMA_REGION_12__NEXT_LSB 0 +#define RDMA_REGION_12__NEXT_MASK 0x00000001 +#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB) +#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK) + +#define RDMA_REGION_13__ADDRESS 0x00000054 +#define RDMA_REGION_13__OFFSET 0x00000054 +#define RDMA_REGION_13__ADDR_MSB 31 +#define RDMA_REGION_13__ADDR_LSB 13 +#define RDMA_REGION_13__ADDR_MASK 0xffffe000 +#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB) +#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK) +#define RDMA_REGION_13__LENGTH_MSB 12 +#define RDMA_REGION_13__LENGTH_LSB 2 +#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB) +#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK) +#define RDMA_REGION_13__INDI_MSB 1 +#define RDMA_REGION_13__INDI_LSB 1 +#define RDMA_REGION_13__INDI_MASK 0x00000002 +#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB) +#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK) +#define RDMA_REGION_13__NEXT_MSB 0 +#define RDMA_REGION_13__NEXT_LSB 0 +#define RDMA_REGION_13__NEXT_MASK 0x00000001 +#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB) +#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK) + +#define RDMA_REGION_14__ADDRESS 0x00000058 +#define RDMA_REGION_14__OFFSET 0x00000058 +#define RDMA_REGION_14__ADDR_MSB 31 +#define RDMA_REGION_14__ADDR_LSB 13 +#define RDMA_REGION_14__ADDR_MASK 0xffffe000 +#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB) +#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK) +#define RDMA_REGION_14__LENGTH_MSB 12 +#define RDMA_REGION_14__LENGTH_LSB 2 +#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB) +#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK) +#define RDMA_REGION_14__INDI_MSB 1 +#define RDMA_REGION_14__INDI_LSB 1 +#define RDMA_REGION_14__INDI_MASK 0x00000002 +#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB) +#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK) +#define RDMA_REGION_14__NEXT_MSB 0 +#define RDMA_REGION_14__NEXT_LSB 0 +#define RDMA_REGION_14__NEXT_MASK 0x00000001 +#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB) +#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK) + +#define RDMA_REGION_15__ADDRESS 0x0000005c +#define RDMA_REGION_15__OFFSET 0x0000005c +#define RDMA_REGION_15__ADDR_MSB 31 +#define RDMA_REGION_15__ADDR_LSB 13 +#define RDMA_REGION_15__ADDR_MASK 0xffffe000 +#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB) +#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK) +#define RDMA_REGION_15__LENGTH_MSB 12 +#define RDMA_REGION_15__LENGTH_LSB 2 +#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc +#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB) +#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK) +#define RDMA_REGION_15__INDI_MSB 1 +#define RDMA_REGION_15__INDI_LSB 1 +#define RDMA_REGION_15__INDI_MASK 0x00000002 +#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB) +#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK) +#define RDMA_REGION_15__NEXT_MSB 0 +#define RDMA_REGION_15__NEXT_LSB 0 +#define RDMA_REGION_15__NEXT_MASK 0x00000001 +#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB) +#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK) + +#define DMA_STATUS_ADDRESS 0x00000060 +#define DMA_STATUS_OFFSET 0x00000060 +#define DMA_STATUS_ERROR_CODE_MSB 14 +#define DMA_STATUS_ERROR_CODE_LSB 4 +#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0 +#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB) +#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK) +#define DMA_STATUS_ERROR_MSB 3 +#define DMA_STATUS_ERROR_LSB 3 +#define DMA_STATUS_ERROR_MASK 0x00000008 +#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB) +#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK) +#define DMA_STATUS_DONE_MSB 2 +#define DMA_STATUS_DONE_LSB 2 +#define DMA_STATUS_DONE_MASK 0x00000004 +#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB) +#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK) +#define DMA_STATUS_STOPPED_MSB 1 +#define DMA_STATUS_STOPPED_LSB 1 +#define DMA_STATUS_STOPPED_MASK 0x00000002 +#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB) +#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK) +#define DMA_STATUS_RUNNING_MSB 0 +#define DMA_STATUS_RUNNING_LSB 0 +#define DMA_STATUS_RUNNING_MASK 0x00000001 +#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB) +#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK) + +#define DMA_INT_EN_ADDRESS 0x00000064 +#define DMA_INT_EN_OFFSET 0x00000064 +#define DMA_INT_EN_ERROR_ENA_MSB 3 +#define DMA_INT_EN_ERROR_ENA_LSB 3 +#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008 +#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB) +#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK) +#define DMA_INT_EN_DONE_ENA_MSB 2 +#define DMA_INT_EN_DONE_ENA_LSB 2 +#define DMA_INT_EN_DONE_ENA_MASK 0x00000004 +#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB) +#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK) +#define DMA_INT_EN_STOPPED_ENA_MSB 1 +#define DMA_INT_EN_STOPPED_ENA_LSB 1 +#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002 +#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB) +#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rdma_reg_reg_s { + volatile unsigned int dma_config; + volatile unsigned int dma_control; + volatile unsigned int dma_src; + volatile unsigned int dma_dest; + volatile unsigned int dma_length; + volatile unsigned int vmc_base; + volatile unsigned int indirect_reg; + volatile unsigned int indirect_return; + volatile unsigned int rdma_region_0_; + volatile unsigned int rdma_region_1_; + volatile unsigned int rdma_region_2_; + volatile unsigned int rdma_region_3_; + volatile unsigned int rdma_region_4_; + volatile unsigned int rdma_region_5_; + volatile unsigned int rdma_region_6_; + volatile unsigned int rdma_region_7_; + volatile unsigned int rdma_region_8_; + volatile unsigned int rdma_region_9_; + volatile unsigned int rdma_region_10_; + volatile unsigned int rdma_region_11_; + volatile unsigned int rdma_region_12_; + volatile unsigned int rdma_region_13_; + volatile unsigned int rdma_region_14_; + volatile unsigned int rdma_region_15_; + volatile unsigned int dma_status; + volatile unsigned int dma_int_en; +} rdma_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RDMA_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h new file mode 100644 index 000000000000..312af9284b7c --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_reg.h @@ -0,0 +1,971 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "rtc_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS +#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET +#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB +#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB +#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK +#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) +#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) +#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB +#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB +#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK +#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) +#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) +#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB +#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB +#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK +#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) +#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) +#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB +#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB +#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK +#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) +#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) +#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB +#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB +#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK +#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) +#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) +#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB +#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB +#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK +#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x) +#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x) +#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB +#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB +#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK +#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x) +#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x) +#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB +#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB +#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK +#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x) +#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x) +#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB +#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB +#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK +#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) +#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) +#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB +#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB +#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK +#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) +#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) +#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB +#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB +#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK +#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) +#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) +#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB +#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB +#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK +#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x) +#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x) +#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB +#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB +#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK +#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x) +#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x) +#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB +#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB +#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK +#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x) +#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x) +#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS +#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET +#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB +#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB +#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK +#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x) +#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x) +#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS +#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET +#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB +#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB +#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK +#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x) +#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x) +#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS +#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET +#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB +#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB +#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK +#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x) +#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x) +#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS +#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET +#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB +#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB +#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK +#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x) +#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x) +#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB +#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB +#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK +#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x) +#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x) +#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB +#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB +#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK +#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x) +#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x) +#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS +#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET +#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB +#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB +#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK +#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) +#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) +#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB +#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB +#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK +#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) +#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) +#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB +#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB +#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK +#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x) +#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x) +#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB +#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB +#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK +#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x) +#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x) +#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB +#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB +#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK +#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x) +#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x) +#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB +#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB +#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK +#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x) +#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x) +#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB +#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB +#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK +#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x) +#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x) +#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS +#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET +#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB +#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB +#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK +#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x) +#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x) +#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS +#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET +#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB +#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB +#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK +#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x) +#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x) +#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS +#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET +#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB +#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB +#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK +#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x) +#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x) +#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS +#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET +#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB +#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB +#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK +#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x) +#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x) +#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS +#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET +#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB +#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB +#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK +#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) +#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) +#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB +#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB +#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK +#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) +#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) +#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS +#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET +#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB +#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB +#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK +#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x) +#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x) +#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS +#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET +#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB +#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB +#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK +#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x) +#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x) +#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS +#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET +#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB +#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB +#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK +#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x) +#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x) +#define WDT_ADDRESS WLAN_WDT_ADDRESS +#define WDT_OFFSET WLAN_WDT_OFFSET +#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB +#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB +#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK +#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x) +#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x) +#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS +#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET +#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB +#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB +#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK +#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x) +#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x) +#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS +#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET +#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB +#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB +#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK +#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x) +#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x) +#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS +#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET +#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB +#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB +#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK +#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x) +#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x) +#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB +#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB +#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK +#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x) +#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x) +#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB +#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB +#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK +#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) +#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) +#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB +#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB +#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK +#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x) +#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x) +#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB +#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB +#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK +#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x) +#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x) +#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB +#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB +#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK +#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x) +#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x) +#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB +#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB +#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK +#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x) +#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x) +#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB +#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB +#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK +#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x) +#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x) +#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB +#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB +#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK +#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x) +#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x) +#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB +#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB +#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK +#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x) +#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x) +#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB +#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB +#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK +#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x) +#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x) +#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB +#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB +#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK +#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x) +#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x) +#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB +#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB +#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK +#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x) +#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x) +#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB +#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB +#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK +#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x) +#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x) +#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB +#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB +#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK +#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x) +#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x) +#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB +#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB +#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK +#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x) +#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x) +#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB +#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB +#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK +#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x) +#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x) +#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB +#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB +#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK +#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x) +#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x) +#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB +#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB +#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK +#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x) +#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x) +#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB +#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB +#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK +#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x) +#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x) +#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB +#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB +#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK +#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x) +#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x) +#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB +#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB +#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK +#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x) +#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x) +#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS +#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET +#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB +#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB +#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK +#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x) +#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x) +#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS +#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET +#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB +#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB +#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK +#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x) +#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x) +#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS +#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET +#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB +#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB +#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK +#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) +#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) +#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB +#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB +#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK +#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x) +#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x) +#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS +#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET +#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB +#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB +#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK +#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) +#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) +#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS +#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET +#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB +#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB +#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK +#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x) +#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x) +#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS +#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET +#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB +#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB +#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK +#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x) +#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x) +#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS +#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET +#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB +#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB +#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK +#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) +#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) +#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB +#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB +#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK +#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x) +#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x) +#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS +#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET +#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB +#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB +#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK +#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) +#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) +#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS +#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET +#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB +#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB +#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK +#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x) +#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x) +#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS +#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET +#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB +#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB +#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK +#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x) +#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x) +#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS +#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET +#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB +#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB +#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK +#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) +#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) +#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB +#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB +#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK +#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x) +#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x) +#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS +#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET +#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB +#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB +#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK +#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) +#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) +#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS +#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET +#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB +#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB +#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK +#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x) +#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x) +#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS +#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET +#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB +#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB +#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK +#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x) +#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x) +#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS +#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET +#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB +#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB +#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK +#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) +#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) +#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB +#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB +#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK +#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) +#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) +#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB +#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB +#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK +#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x) +#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x) +#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS +#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET +#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB +#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB +#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK +#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) +#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) +#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS +#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET +#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB +#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB +#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK +#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x) +#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x) +#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS +#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET +#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB +#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB +#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK +#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x) +#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x) +#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS +#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET +#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB +#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB +#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK +#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x) +#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x) +#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS +#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET +#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB +#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB +#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK +#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) +#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) +#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB +#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB +#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK +#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x) +#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x) +#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB +#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB +#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK +#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) +#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) +#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB +#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB +#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK +#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x) +#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x) +#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS +#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET +#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB +#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB +#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK +#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) +#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) +#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS +#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET +#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB +#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB +#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK +#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x) +#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x) +#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB +#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB +#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK +#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x) +#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x) +#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB +#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB +#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK +#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) +#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) +#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS +#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET +#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB +#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB +#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK +#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x) +#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x) +#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB +#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB +#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK +#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x) +#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x) +#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB +#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB +#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK +#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x) +#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x) +#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB +#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB +#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK +#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x) +#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x) +#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS +#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET +#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB +#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB +#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK +#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x) +#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x) +#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB +#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB +#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK +#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x) +#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x) +#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB +#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB +#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK +#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x) +#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x) +#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS +#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET +#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB +#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB +#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK +#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) +#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) +#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB +#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB +#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK +#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x) +#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x) +#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB +#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB +#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK +#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x) +#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x) +#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB +#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB +#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK +#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x) +#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x) +#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS +#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET +#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB +#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB +#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK +#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x) +#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x) +#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB +#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB +#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK +#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x) +#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x) +#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB +#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB +#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK +#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) +#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) +#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS +#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET +#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB +#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB +#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK +#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x) +#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x) +#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB +#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB +#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK +#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x) +#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x) +#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB +#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB +#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK +#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x) +#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x) +#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS +#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET +#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB +#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB +#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK +#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x) +#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x) +#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB +#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB +#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK +#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) +#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) +#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB +#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB +#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK +#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x) +#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x) +#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS +#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET +#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB +#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB +#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK +#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) +#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) +#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB +#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB +#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK +#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) +#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) +#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS +#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET +#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB +#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB +#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK +#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x) +#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x) +#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS +#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET +#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB +#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB +#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK +#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x) +#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x) +#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS +#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET +#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB +#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB +#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK +#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) +#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) +#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB +#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB +#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK +#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x) +#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x) +#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB +#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB +#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK +#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) +#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) +#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB +#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB +#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK +#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x) +#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x) +#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB +#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB +#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK +#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x) +#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x) +#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS +#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET +#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB +#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB +#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK +#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x) +#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x) +#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB +#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB +#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK +#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x) +#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x) +#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB +#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB +#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK +#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x) +#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x) +#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB +#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB +#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK +#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x) +#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x) +#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS +#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET +#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB +#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB +#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK +#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) +#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) +#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS +#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET +#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB +#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB +#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK +#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x) +#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x) +#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS +#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET +#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB +#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB +#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK +#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x) +#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x) +#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS +#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET +#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB +#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB +#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK +#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) +#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) +#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS +#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) +#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) +#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS +#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET +#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB +#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB +#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK +#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x) +#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x) +#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB +#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB +#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK +#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x) +#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x) +#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS +#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET +#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB +#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB +#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK +#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) +#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) +#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) +#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS +#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET +#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB +#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB +#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK +#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) +#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) +#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB +#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB +#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK +#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) +#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) +#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS +#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET +#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB +#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB +#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK +#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x) +#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x) +#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB +#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB +#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK +#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x) +#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x) +#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB +#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB +#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK +#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x) +#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x) +#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS +#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) +#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) +#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB +#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB +#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK +#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x) +#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x) +#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB +#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB +#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK +#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) +#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) +#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS +#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) +#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) +#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB +#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB +#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK +#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x) +#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x) +#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB +#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB +#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK +#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) +#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) +#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB +#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB +#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK +#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) +#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) +#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB +#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB +#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK +#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x) +#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x) +#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB +#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB +#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK +#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) +#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) +#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB +#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB +#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK +#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) +#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) +#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB +#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB +#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK +#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) +#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) +#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB +#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB +#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK +#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x) +#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x) +#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB +#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB +#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK +#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x) +#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x) +#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB +#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB +#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK +#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x) +#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x) +#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB +#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB +#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK +#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x) +#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x) +#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB +#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB +#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK +#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x) +#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x) +#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS +#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET +#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB +#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB +#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK +#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x) +#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x) +#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS +#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET +#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB +#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB +#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK +#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) +#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) + + +#endif +#endif + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h new file mode 100644 index 000000000000..c215f2e78809 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/rtc_wlan_reg.h @@ -0,0 +1,2061 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _RTC_WLAN_REG_REG_H_ +#define _RTC_WLAN_REG_REG_H_ + +#define WLAN_RESET_CONTROL_ADDRESS 0x00000000 +#define WLAN_RESET_CONTROL_OFFSET 0x00000000 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB 14 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB 14 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK 0x00004000 +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) >> WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) +#define WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB) & WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK) +#define WLAN_RESET_CONTROL_BB_COLD_RST_MSB 13 +#define WLAN_RESET_CONTROL_BB_COLD_RST_LSB 13 +#define WLAN_RESET_CONTROL_BB_COLD_RST_MASK 0x00002000 +#define WLAN_RESET_CONTROL_BB_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) >> WLAN_RESET_CONTROL_BB_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_BB_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_COLD_RST_LSB) & WLAN_RESET_CONTROL_BB_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_BB_WARM_RST_MSB 12 +#define WLAN_RESET_CONTROL_BB_WARM_RST_LSB 12 +#define WLAN_RESET_CONTROL_BB_WARM_RST_MASK 0x00001000 +#define WLAN_RESET_CONTROL_BB_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) >> WLAN_RESET_CONTROL_BB_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_BB_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_BB_WARM_RST_LSB) & WLAN_RESET_CONTROL_BB_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB 11 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB 11 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) >> WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) +#define WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB) & WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK) +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB 10 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB 10 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) >> WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) +#define WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB) & WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK) +#define WLAN_RESET_CONTROL_RST_OUT_MSB 9 +#define WLAN_RESET_CONTROL_RST_OUT_LSB 9 +#define WLAN_RESET_CONTROL_RST_OUT_MASK 0x00000200 +#define WLAN_RESET_CONTROL_RST_OUT_GET(x) (((x) & WLAN_RESET_CONTROL_RST_OUT_MASK) >> WLAN_RESET_CONTROL_RST_OUT_LSB) +#define WLAN_RESET_CONTROL_RST_OUT_SET(x) (((x) << WLAN_RESET_CONTROL_RST_OUT_LSB) & WLAN_RESET_CONTROL_RST_OUT_MASK) +#define WLAN_RESET_CONTROL_COLD_RST_MSB 8 +#define WLAN_RESET_CONTROL_COLD_RST_LSB 8 +#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000100 +#define WLAN_RESET_CONTROL_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_COLD_RST_MASK) >> WLAN_RESET_CONTROL_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_COLD_RST_LSB) & WLAN_RESET_CONTROL_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_WARM_RST_MSB 7 +#define WLAN_RESET_CONTROL_WARM_RST_LSB 7 +#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000080 +#define WLAN_RESET_CONTROL_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_WARM_RST_MASK) >> WLAN_RESET_CONTROL_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_WARM_RST_LSB) & WLAN_RESET_CONTROL_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_CPU_WARM_RST_MSB 6 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_LSB 6 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 +#define WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) >> WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_CPU_WARM_RST_LSB) & WLAN_RESET_CONTROL_CPU_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_MAC_COLD_RST_MSB 5 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_LSB 5 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 +#define WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) >> WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) +#define WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_COLD_RST_LSB) & WLAN_RESET_CONTROL_MAC_COLD_RST_MASK) +#define WLAN_RESET_CONTROL_MAC_WARM_RST_MSB 4 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_LSB 4 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 +#define WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) >> WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) +#define WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MAC_WARM_RST_LSB) & WLAN_RESET_CONTROL_MAC_WARM_RST_MASK) +#define WLAN_RESET_CONTROL_MBOX_RST_MSB 2 +#define WLAN_RESET_CONTROL_MBOX_RST_LSB 2 +#define WLAN_RESET_CONTROL_MBOX_RST_MASK 0x00000004 +#define WLAN_RESET_CONTROL_MBOX_RST_GET(x) (((x) & WLAN_RESET_CONTROL_MBOX_RST_MASK) >> WLAN_RESET_CONTROL_MBOX_RST_LSB) +#define WLAN_RESET_CONTROL_MBOX_RST_SET(x) (((x) << WLAN_RESET_CONTROL_MBOX_RST_LSB) & WLAN_RESET_CONTROL_MBOX_RST_MASK) +#define WLAN_RESET_CONTROL_UART_RST_MSB 1 +#define WLAN_RESET_CONTROL_UART_RST_LSB 1 +#define WLAN_RESET_CONTROL_UART_RST_MASK 0x00000002 +#define WLAN_RESET_CONTROL_UART_RST_GET(x) (((x) & WLAN_RESET_CONTROL_UART_RST_MASK) >> WLAN_RESET_CONTROL_UART_RST_LSB) +#define WLAN_RESET_CONTROL_UART_RST_SET(x) (((x) << WLAN_RESET_CONTROL_UART_RST_LSB) & WLAN_RESET_CONTROL_UART_RST_MASK) +#define WLAN_RESET_CONTROL_SI0_RST_MSB 0 +#define WLAN_RESET_CONTROL_SI0_RST_LSB 0 +#define WLAN_RESET_CONTROL_SI0_RST_MASK 0x00000001 +#define WLAN_RESET_CONTROL_SI0_RST_GET(x) (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB) +#define WLAN_RESET_CONTROL_SI0_RST_SET(x) (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK) + +#define WLAN_XTAL_CONTROL_ADDRESS 0x00000004 +#define WLAN_XTAL_CONTROL_OFFSET 0x00000004 +#define WLAN_XTAL_CONTROL_TCXO_MSB 0 +#define WLAN_XTAL_CONTROL_TCXO_LSB 0 +#define WLAN_XTAL_CONTROL_TCXO_MASK 0x00000001 +#define WLAN_XTAL_CONTROL_TCXO_GET(x) (((x) & WLAN_XTAL_CONTROL_TCXO_MASK) >> WLAN_XTAL_CONTROL_TCXO_LSB) +#define WLAN_XTAL_CONTROL_TCXO_SET(x) (((x) << WLAN_XTAL_CONTROL_TCXO_LSB) & WLAN_XTAL_CONTROL_TCXO_MASK) + +#define WLAN_TCXO_DETECT_ADDRESS 0x00000008 +#define WLAN_TCXO_DETECT_OFFSET 0x00000008 +#define WLAN_TCXO_DETECT_PRESENT_MSB 0 +#define WLAN_TCXO_DETECT_PRESENT_LSB 0 +#define WLAN_TCXO_DETECT_PRESENT_MASK 0x00000001 +#define WLAN_TCXO_DETECT_PRESENT_GET(x) (((x) & WLAN_TCXO_DETECT_PRESENT_MASK) >> WLAN_TCXO_DETECT_PRESENT_LSB) +#define WLAN_TCXO_DETECT_PRESENT_SET(x) (((x) << WLAN_TCXO_DETECT_PRESENT_LSB) & WLAN_TCXO_DETECT_PRESENT_MASK) + +#define WLAN_XTAL_TEST_ADDRESS 0x0000000c +#define WLAN_XTAL_TEST_OFFSET 0x0000000c +#define WLAN_XTAL_TEST_NOTCXODET_MSB 0 +#define WLAN_XTAL_TEST_NOTCXODET_LSB 0 +#define WLAN_XTAL_TEST_NOTCXODET_MASK 0x00000001 +#define WLAN_XTAL_TEST_NOTCXODET_GET(x) (((x) & WLAN_XTAL_TEST_NOTCXODET_MASK) >> WLAN_XTAL_TEST_NOTCXODET_LSB) +#define WLAN_XTAL_TEST_NOTCXODET_SET(x) (((x) << WLAN_XTAL_TEST_NOTCXODET_LSB) & WLAN_XTAL_TEST_NOTCXODET_MASK) + +#define WLAN_QUADRATURE_ADDRESS 0x00000010 +#define WLAN_QUADRATURE_OFFSET 0x00000010 +#define WLAN_QUADRATURE_ADC_MSB 7 +#define WLAN_QUADRATURE_ADC_LSB 4 +#define WLAN_QUADRATURE_ADC_MASK 0x000000f0 +#define WLAN_QUADRATURE_ADC_GET(x) (((x) & WLAN_QUADRATURE_ADC_MASK) >> WLAN_QUADRATURE_ADC_LSB) +#define WLAN_QUADRATURE_ADC_SET(x) (((x) << WLAN_QUADRATURE_ADC_LSB) & WLAN_QUADRATURE_ADC_MASK) +#define WLAN_QUADRATURE_SEL_MSB 2 +#define WLAN_QUADRATURE_SEL_LSB 2 +#define WLAN_QUADRATURE_SEL_MASK 0x00000004 +#define WLAN_QUADRATURE_SEL_GET(x) (((x) & WLAN_QUADRATURE_SEL_MASK) >> WLAN_QUADRATURE_SEL_LSB) +#define WLAN_QUADRATURE_SEL_SET(x) (((x) << WLAN_QUADRATURE_SEL_LSB) & WLAN_QUADRATURE_SEL_MASK) +#define WLAN_QUADRATURE_DAC_MSB 1 +#define WLAN_QUADRATURE_DAC_LSB 0 +#define WLAN_QUADRATURE_DAC_MASK 0x00000003 +#define WLAN_QUADRATURE_DAC_GET(x) (((x) & WLAN_QUADRATURE_DAC_MASK) >> WLAN_QUADRATURE_DAC_LSB) +#define WLAN_QUADRATURE_DAC_SET(x) (((x) << WLAN_QUADRATURE_DAC_LSB) & WLAN_QUADRATURE_DAC_MASK) + +#define WLAN_PLL_CONTROL_ADDRESS 0x00000014 +#define WLAN_PLL_CONTROL_OFFSET 0x00000014 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB 20 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB 20 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) >> WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) +#define WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB 19 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB 19 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) >> WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) +#define WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) +#define WLAN_PLL_CONTROL_NOPWD_MSB 18 +#define WLAN_PLL_CONTROL_NOPWD_LSB 18 +#define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 +#define WLAN_PLL_CONTROL_NOPWD_GET(x) (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) +#define WLAN_PLL_CONTROL_NOPWD_SET(x) (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) +#define WLAN_PLL_CONTROL_UPDATING_MSB 17 +#define WLAN_PLL_CONTROL_UPDATING_LSB 17 +#define WLAN_PLL_CONTROL_UPDATING_MASK 0x00020000 +#define WLAN_PLL_CONTROL_UPDATING_GET(x) (((x) & WLAN_PLL_CONTROL_UPDATING_MASK) >> WLAN_PLL_CONTROL_UPDATING_LSB) +#define WLAN_PLL_CONTROL_UPDATING_SET(x) (((x) << WLAN_PLL_CONTROL_UPDATING_LSB) & WLAN_PLL_CONTROL_UPDATING_MASK) +#define WLAN_PLL_CONTROL_BYPASS_MSB 16 +#define WLAN_PLL_CONTROL_BYPASS_LSB 16 +#define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 +#define WLAN_PLL_CONTROL_BYPASS_GET(x) (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) +#define WLAN_PLL_CONTROL_BYPASS_SET(x) (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) +#define WLAN_PLL_CONTROL_REFDIV_MSB 15 +#define WLAN_PLL_CONTROL_REFDIV_LSB 12 +#define WLAN_PLL_CONTROL_REFDIV_MASK 0x0000f000 +#define WLAN_PLL_CONTROL_REFDIV_GET(x) (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) +#define WLAN_PLL_CONTROL_REFDIV_SET(x) (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) +#define WLAN_PLL_CONTROL_DIV_MSB 9 +#define WLAN_PLL_CONTROL_DIV_LSB 0 +#define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff +#define WLAN_PLL_CONTROL_DIV_GET(x) (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) +#define WLAN_PLL_CONTROL_DIV_SET(x) (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) + +#define WLAN_PLL_SETTLE_ADDRESS 0x00000018 +#define WLAN_PLL_SETTLE_OFFSET 0x00000018 +#define WLAN_PLL_SETTLE_TIME_MSB 11 +#define WLAN_PLL_SETTLE_TIME_LSB 0 +#define WLAN_PLL_SETTLE_TIME_MASK 0x00000fff +#define WLAN_PLL_SETTLE_TIME_GET(x) (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) +#define WLAN_PLL_SETTLE_TIME_SET(x) (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) + +#define WLAN_XTAL_SETTLE_ADDRESS 0x0000001c +#define WLAN_XTAL_SETTLE_OFFSET 0x0000001c +#define WLAN_XTAL_SETTLE_TIME_MSB 7 +#define WLAN_XTAL_SETTLE_TIME_LSB 0 +#define WLAN_XTAL_SETTLE_TIME_MASK 0x000000ff +#define WLAN_XTAL_SETTLE_TIME_GET(x) (((x) & WLAN_XTAL_SETTLE_TIME_MASK) >> WLAN_XTAL_SETTLE_TIME_LSB) +#define WLAN_XTAL_SETTLE_TIME_SET(x) (((x) << WLAN_XTAL_SETTLE_TIME_LSB) & WLAN_XTAL_SETTLE_TIME_MASK) + +#define WLAN_CPU_CLOCK_ADDRESS 0x00000020 +#define WLAN_CPU_CLOCK_OFFSET 0x00000020 +#define WLAN_CPU_CLOCK_STANDARD_MSB 1 +#define WLAN_CPU_CLOCK_STANDARD_LSB 0 +#define WLAN_CPU_CLOCK_STANDARD_MASK 0x00000003 +#define WLAN_CPU_CLOCK_STANDARD_GET(x) (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB) +#define WLAN_CPU_CLOCK_STANDARD_SET(x) (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK) + +#define WLAN_CLOCK_OUT_ADDRESS 0x00000024 +#define WLAN_CLOCK_OUT_OFFSET 0x00000024 +#define WLAN_CLOCK_OUT_SELECT_MSB 3 +#define WLAN_CLOCK_OUT_SELECT_LSB 0 +#define WLAN_CLOCK_OUT_SELECT_MASK 0x0000000f +#define WLAN_CLOCK_OUT_SELECT_GET(x) (((x) & WLAN_CLOCK_OUT_SELECT_MASK) >> WLAN_CLOCK_OUT_SELECT_LSB) +#define WLAN_CLOCK_OUT_SELECT_SET(x) (((x) << WLAN_CLOCK_OUT_SELECT_LSB) & WLAN_CLOCK_OUT_SELECT_MASK) + +#define WLAN_CLOCK_CONTROL_ADDRESS 0x00000028 +#define WLAN_CLOCK_CONTROL_OFFSET 0x00000028 +#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB 2 +#define WLAN_CLOCK_CONTROL_LF_CLK32_LSB 2 +#define WLAN_CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 +#define WLAN_CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) >> WLAN_CLOCK_CONTROL_LF_CLK32_LSB) +#define WLAN_CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << WLAN_CLOCK_CONTROL_LF_CLK32_LSB) & WLAN_CLOCK_CONTROL_LF_CLK32_MASK) +#define WLAN_CLOCK_CONTROL_SI0_CLK_MSB 0 +#define WLAN_CLOCK_CONTROL_SI0_CLK_LSB 0 +#define WLAN_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 +#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB) +#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) + +#define WLAN_BIAS_OVERRIDE_ADDRESS 0x0000002c +#define WLAN_BIAS_OVERRIDE_OFFSET 0x0000002c +#define WLAN_BIAS_OVERRIDE_ON_MSB 0 +#define WLAN_BIAS_OVERRIDE_ON_LSB 0 +#define WLAN_BIAS_OVERRIDE_ON_MASK 0x00000001 +#define WLAN_BIAS_OVERRIDE_ON_GET(x) (((x) & WLAN_BIAS_OVERRIDE_ON_MASK) >> WLAN_BIAS_OVERRIDE_ON_LSB) +#define WLAN_BIAS_OVERRIDE_ON_SET(x) (((x) << WLAN_BIAS_OVERRIDE_ON_LSB) & WLAN_BIAS_OVERRIDE_ON_MASK) + +#define WLAN_WDT_CONTROL_ADDRESS 0x00000030 +#define WLAN_WDT_CONTROL_OFFSET 0x00000030 +#define WLAN_WDT_CONTROL_ACTION_MSB 2 +#define WLAN_WDT_CONTROL_ACTION_LSB 0 +#define WLAN_WDT_CONTROL_ACTION_MASK 0x00000007 +#define WLAN_WDT_CONTROL_ACTION_GET(x) (((x) & WLAN_WDT_CONTROL_ACTION_MASK) >> WLAN_WDT_CONTROL_ACTION_LSB) +#define WLAN_WDT_CONTROL_ACTION_SET(x) (((x) << WLAN_WDT_CONTROL_ACTION_LSB) & WLAN_WDT_CONTROL_ACTION_MASK) + +#define WLAN_WDT_STATUS_ADDRESS 0x00000034 +#define WLAN_WDT_STATUS_OFFSET 0x00000034 +#define WLAN_WDT_STATUS_INTERRUPT_MSB 0 +#define WLAN_WDT_STATUS_INTERRUPT_LSB 0 +#define WLAN_WDT_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_WDT_STATUS_INTERRUPT_GET(x) (((x) & WLAN_WDT_STATUS_INTERRUPT_MASK) >> WLAN_WDT_STATUS_INTERRUPT_LSB) +#define WLAN_WDT_STATUS_INTERRUPT_SET(x) (((x) << WLAN_WDT_STATUS_INTERRUPT_LSB) & WLAN_WDT_STATUS_INTERRUPT_MASK) + +#define WLAN_WDT_ADDRESS 0x00000038 +#define WLAN_WDT_OFFSET 0x00000038 +#define WLAN_WDT_TARGET_MSB 21 +#define WLAN_WDT_TARGET_LSB 0 +#define WLAN_WDT_TARGET_MASK 0x003fffff +#define WLAN_WDT_TARGET_GET(x) (((x) & WLAN_WDT_TARGET_MASK) >> WLAN_WDT_TARGET_LSB) +#define WLAN_WDT_TARGET_SET(x) (((x) << WLAN_WDT_TARGET_LSB) & WLAN_WDT_TARGET_MASK) + +#define WLAN_WDT_COUNT_ADDRESS 0x0000003c +#define WLAN_WDT_COUNT_OFFSET 0x0000003c +#define WLAN_WDT_COUNT_VALUE_MSB 21 +#define WLAN_WDT_COUNT_VALUE_LSB 0 +#define WLAN_WDT_COUNT_VALUE_MASK 0x003fffff +#define WLAN_WDT_COUNT_VALUE_GET(x) (((x) & WLAN_WDT_COUNT_VALUE_MASK) >> WLAN_WDT_COUNT_VALUE_LSB) +#define WLAN_WDT_COUNT_VALUE_SET(x) (((x) << WLAN_WDT_COUNT_VALUE_LSB) & WLAN_WDT_COUNT_VALUE_MASK) + +#define WLAN_WDT_RESET_ADDRESS 0x00000040 +#define WLAN_WDT_RESET_OFFSET 0x00000040 +#define WLAN_WDT_RESET_VALUE_MSB 0 +#define WLAN_WDT_RESET_VALUE_LSB 0 +#define WLAN_WDT_RESET_VALUE_MASK 0x00000001 +#define WLAN_WDT_RESET_VALUE_GET(x) (((x) & WLAN_WDT_RESET_VALUE_MASK) >> WLAN_WDT_RESET_VALUE_LSB) +#define WLAN_WDT_RESET_VALUE_SET(x) (((x) << WLAN_WDT_RESET_VALUE_LSB) & WLAN_WDT_RESET_VALUE_MASK) + +#define WLAN_INT_STATUS_ADDRESS 0x00000044 +#define WLAN_INT_STATUS_OFFSET 0x00000044 +#define WLAN_INT_STATUS_HCI_UART_MSB 21 +#define WLAN_INT_STATUS_HCI_UART_LSB 21 +#define WLAN_INT_STATUS_HCI_UART_MASK 0x00200000 +#define WLAN_INT_STATUS_HCI_UART_GET(x) (((x) & WLAN_INT_STATUS_HCI_UART_MASK) >> WLAN_INT_STATUS_HCI_UART_LSB) +#define WLAN_INT_STATUS_HCI_UART_SET(x) (((x) << WLAN_INT_STATUS_HCI_UART_LSB) & WLAN_INT_STATUS_HCI_UART_MASK) +#define WLAN_INT_STATUS_THERM_MSB 20 +#define WLAN_INT_STATUS_THERM_LSB 20 +#define WLAN_INT_STATUS_THERM_MASK 0x00100000 +#define WLAN_INT_STATUS_THERM_GET(x) (((x) & WLAN_INT_STATUS_THERM_MASK) >> WLAN_INT_STATUS_THERM_LSB) +#define WLAN_INT_STATUS_THERM_SET(x) (((x) << WLAN_INT_STATUS_THERM_LSB) & WLAN_INT_STATUS_THERM_MASK) +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB 19 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB 19 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK 0x00080000 +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) (((x) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) >> WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) +#define WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) (((x) << WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) +#define WLAN_INT_STATUS_UART_MBOX_MSB 18 +#define WLAN_INT_STATUS_UART_MBOX_LSB 18 +#define WLAN_INT_STATUS_UART_MBOX_MASK 0x00040000 +#define WLAN_INT_STATUS_UART_MBOX_GET(x) (((x) & WLAN_INT_STATUS_UART_MBOX_MASK) >> WLAN_INT_STATUS_UART_MBOX_LSB) +#define WLAN_INT_STATUS_UART_MBOX_SET(x) (((x) << WLAN_INT_STATUS_UART_MBOX_LSB) & WLAN_INT_STATUS_UART_MBOX_MASK) +#define WLAN_INT_STATUS_GENERIC_MBOX_MSB 17 +#define WLAN_INT_STATUS_GENERIC_MBOX_LSB 17 +#define WLAN_INT_STATUS_GENERIC_MBOX_MASK 0x00020000 +#define WLAN_INT_STATUS_GENERIC_MBOX_GET(x) (((x) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) >> WLAN_INT_STATUS_GENERIC_MBOX_LSB) +#define WLAN_INT_STATUS_GENERIC_MBOX_SET(x) (((x) << WLAN_INT_STATUS_GENERIC_MBOX_LSB) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) +#define WLAN_INT_STATUS_RDMA_MSB 16 +#define WLAN_INT_STATUS_RDMA_LSB 16 +#define WLAN_INT_STATUS_RDMA_MASK 0x00010000 +#define WLAN_INT_STATUS_RDMA_GET(x) (((x) & WLAN_INT_STATUS_RDMA_MASK) >> WLAN_INT_STATUS_RDMA_LSB) +#define WLAN_INT_STATUS_RDMA_SET(x) (((x) << WLAN_INT_STATUS_RDMA_LSB) & WLAN_INT_STATUS_RDMA_MASK) +#define WLAN_INT_STATUS_BTCOEX_MSB 15 +#define WLAN_INT_STATUS_BTCOEX_LSB 15 +#define WLAN_INT_STATUS_BTCOEX_MASK 0x00008000 +#define WLAN_INT_STATUS_BTCOEX_GET(x) (((x) & WLAN_INT_STATUS_BTCOEX_MASK) >> WLAN_INT_STATUS_BTCOEX_LSB) +#define WLAN_INT_STATUS_BTCOEX_SET(x) (((x) << WLAN_INT_STATUS_BTCOEX_LSB) & WLAN_INT_STATUS_BTCOEX_MASK) +#define WLAN_INT_STATUS_RTC_POWER_MSB 14 +#define WLAN_INT_STATUS_RTC_POWER_LSB 14 +#define WLAN_INT_STATUS_RTC_POWER_MASK 0x00004000 +#define WLAN_INT_STATUS_RTC_POWER_GET(x) (((x) & WLAN_INT_STATUS_RTC_POWER_MASK) >> WLAN_INT_STATUS_RTC_POWER_LSB) +#define WLAN_INT_STATUS_RTC_POWER_SET(x) (((x) << WLAN_INT_STATUS_RTC_POWER_LSB) & WLAN_INT_STATUS_RTC_POWER_MASK) +#define WLAN_INT_STATUS_MAC_MSB 13 +#define WLAN_INT_STATUS_MAC_LSB 13 +#define WLAN_INT_STATUS_MAC_MASK 0x00002000 +#define WLAN_INT_STATUS_MAC_GET(x) (((x) & WLAN_INT_STATUS_MAC_MASK) >> WLAN_INT_STATUS_MAC_LSB) +#define WLAN_INT_STATUS_MAC_SET(x) (((x) << WLAN_INT_STATUS_MAC_LSB) & WLAN_INT_STATUS_MAC_MASK) +#define WLAN_INT_STATUS_MAILBOX_MSB 12 +#define WLAN_INT_STATUS_MAILBOX_LSB 12 +#define WLAN_INT_STATUS_MAILBOX_MASK 0x00001000 +#define WLAN_INT_STATUS_MAILBOX_GET(x) (((x) & WLAN_INT_STATUS_MAILBOX_MASK) >> WLAN_INT_STATUS_MAILBOX_LSB) +#define WLAN_INT_STATUS_MAILBOX_SET(x) (((x) << WLAN_INT_STATUS_MAILBOX_LSB) & WLAN_INT_STATUS_MAILBOX_MASK) +#define WLAN_INT_STATUS_RTC_ALARM_MSB 11 +#define WLAN_INT_STATUS_RTC_ALARM_LSB 11 +#define WLAN_INT_STATUS_RTC_ALARM_MASK 0x00000800 +#define WLAN_INT_STATUS_RTC_ALARM_GET(x) (((x) & WLAN_INT_STATUS_RTC_ALARM_MASK) >> WLAN_INT_STATUS_RTC_ALARM_LSB) +#define WLAN_INT_STATUS_RTC_ALARM_SET(x) (((x) << WLAN_INT_STATUS_RTC_ALARM_LSB) & WLAN_INT_STATUS_RTC_ALARM_MASK) +#define WLAN_INT_STATUS_HF_TIMER_MSB 10 +#define WLAN_INT_STATUS_HF_TIMER_LSB 10 +#define WLAN_INT_STATUS_HF_TIMER_MASK 0x00000400 +#define WLAN_INT_STATUS_HF_TIMER_GET(x) (((x) & WLAN_INT_STATUS_HF_TIMER_MASK) >> WLAN_INT_STATUS_HF_TIMER_LSB) +#define WLAN_INT_STATUS_HF_TIMER_SET(x) (((x) << WLAN_INT_STATUS_HF_TIMER_LSB) & WLAN_INT_STATUS_HF_TIMER_MASK) +#define WLAN_INT_STATUS_LF_TIMER3_MSB 9 +#define WLAN_INT_STATUS_LF_TIMER3_LSB 9 +#define WLAN_INT_STATUS_LF_TIMER3_MASK 0x00000200 +#define WLAN_INT_STATUS_LF_TIMER3_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER3_MASK) >> WLAN_INT_STATUS_LF_TIMER3_LSB) +#define WLAN_INT_STATUS_LF_TIMER3_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER3_LSB) & WLAN_INT_STATUS_LF_TIMER3_MASK) +#define WLAN_INT_STATUS_LF_TIMER2_MSB 8 +#define WLAN_INT_STATUS_LF_TIMER2_LSB 8 +#define WLAN_INT_STATUS_LF_TIMER2_MASK 0x00000100 +#define WLAN_INT_STATUS_LF_TIMER2_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER2_MASK) >> WLAN_INT_STATUS_LF_TIMER2_LSB) +#define WLAN_INT_STATUS_LF_TIMER2_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER2_LSB) & WLAN_INT_STATUS_LF_TIMER2_MASK) +#define WLAN_INT_STATUS_LF_TIMER1_MSB 7 +#define WLAN_INT_STATUS_LF_TIMER1_LSB 7 +#define WLAN_INT_STATUS_LF_TIMER1_MASK 0x00000080 +#define WLAN_INT_STATUS_LF_TIMER1_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER1_MASK) >> WLAN_INT_STATUS_LF_TIMER1_LSB) +#define WLAN_INT_STATUS_LF_TIMER1_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER1_LSB) & WLAN_INT_STATUS_LF_TIMER1_MASK) +#define WLAN_INT_STATUS_LF_TIMER0_MSB 6 +#define WLAN_INT_STATUS_LF_TIMER0_LSB 6 +#define WLAN_INT_STATUS_LF_TIMER0_MASK 0x00000040 +#define WLAN_INT_STATUS_LF_TIMER0_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER0_MASK) >> WLAN_INT_STATUS_LF_TIMER0_LSB) +#define WLAN_INT_STATUS_LF_TIMER0_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER0_LSB) & WLAN_INT_STATUS_LF_TIMER0_MASK) +#define WLAN_INT_STATUS_KEYPAD_MSB 5 +#define WLAN_INT_STATUS_KEYPAD_LSB 5 +#define WLAN_INT_STATUS_KEYPAD_MASK 0x00000020 +#define WLAN_INT_STATUS_KEYPAD_GET(x) (((x) & WLAN_INT_STATUS_KEYPAD_MASK) >> WLAN_INT_STATUS_KEYPAD_LSB) +#define WLAN_INT_STATUS_KEYPAD_SET(x) (((x) << WLAN_INT_STATUS_KEYPAD_LSB) & WLAN_INT_STATUS_KEYPAD_MASK) +#define WLAN_INT_STATUS_SI_MSB 4 +#define WLAN_INT_STATUS_SI_LSB 4 +#define WLAN_INT_STATUS_SI_MASK 0x00000010 +#define WLAN_INT_STATUS_SI_GET(x) (((x) & WLAN_INT_STATUS_SI_MASK) >> WLAN_INT_STATUS_SI_LSB) +#define WLAN_INT_STATUS_SI_SET(x) (((x) << WLAN_INT_STATUS_SI_LSB) & WLAN_INT_STATUS_SI_MASK) +#define WLAN_INT_STATUS_GPIO_MSB 3 +#define WLAN_INT_STATUS_GPIO_LSB 3 +#define WLAN_INT_STATUS_GPIO_MASK 0x00000008 +#define WLAN_INT_STATUS_GPIO_GET(x) (((x) & WLAN_INT_STATUS_GPIO_MASK) >> WLAN_INT_STATUS_GPIO_LSB) +#define WLAN_INT_STATUS_GPIO_SET(x) (((x) << WLAN_INT_STATUS_GPIO_LSB) & WLAN_INT_STATUS_GPIO_MASK) +#define WLAN_INT_STATUS_UART_MSB 2 +#define WLAN_INT_STATUS_UART_LSB 2 +#define WLAN_INT_STATUS_UART_MASK 0x00000004 +#define WLAN_INT_STATUS_UART_GET(x) (((x) & WLAN_INT_STATUS_UART_MASK) >> WLAN_INT_STATUS_UART_LSB) +#define WLAN_INT_STATUS_UART_SET(x) (((x) << WLAN_INT_STATUS_UART_LSB) & WLAN_INT_STATUS_UART_MASK) +#define WLAN_INT_STATUS_ERROR_MSB 1 +#define WLAN_INT_STATUS_ERROR_LSB 1 +#define WLAN_INT_STATUS_ERROR_MASK 0x00000002 +#define WLAN_INT_STATUS_ERROR_GET(x) (((x) & WLAN_INT_STATUS_ERROR_MASK) >> WLAN_INT_STATUS_ERROR_LSB) +#define WLAN_INT_STATUS_ERROR_SET(x) (((x) << WLAN_INT_STATUS_ERROR_LSB) & WLAN_INT_STATUS_ERROR_MASK) +#define WLAN_INT_STATUS_WDT_INT_MSB 0 +#define WLAN_INT_STATUS_WDT_INT_LSB 0 +#define WLAN_INT_STATUS_WDT_INT_MASK 0x00000001 +#define WLAN_INT_STATUS_WDT_INT_GET(x) (((x) & WLAN_INT_STATUS_WDT_INT_MASK) >> WLAN_INT_STATUS_WDT_INT_LSB) +#define WLAN_INT_STATUS_WDT_INT_SET(x) (((x) << WLAN_INT_STATUS_WDT_INT_LSB) & WLAN_INT_STATUS_WDT_INT_MASK) + +#define WLAN_LF_TIMER0_ADDRESS 0x00000048 +#define WLAN_LF_TIMER0_OFFSET 0x00000048 +#define WLAN_LF_TIMER0_TARGET_MSB 31 +#define WLAN_LF_TIMER0_TARGET_LSB 0 +#define WLAN_LF_TIMER0_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER0_TARGET_GET(x) (((x) & WLAN_LF_TIMER0_TARGET_MASK) >> WLAN_LF_TIMER0_TARGET_LSB) +#define WLAN_LF_TIMER0_TARGET_SET(x) (((x) << WLAN_LF_TIMER0_TARGET_LSB) & WLAN_LF_TIMER0_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT0_ADDRESS 0x0000004c +#define WLAN_LF_TIMER_COUNT0_OFFSET 0x0000004c +#define WLAN_LF_TIMER_COUNT0_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT0_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT0_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT0_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) >> WLAN_LF_TIMER_COUNT0_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT0_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT0_VALUE_LSB) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL0_ADDRESS 0x00000050 +#define WLAN_LF_TIMER_CONTROL0_OFFSET 0x00000050 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL0_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL0_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL0_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL0_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) >> WLAN_LF_TIMER_CONTROL0_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL0_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_RESET_LSB) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS0_ADDRESS 0x00000054 +#define WLAN_LF_TIMER_STATUS0_OFFSET 0x00000054 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) + +#define WLAN_LF_TIMER1_ADDRESS 0x00000058 +#define WLAN_LF_TIMER1_OFFSET 0x00000058 +#define WLAN_LF_TIMER1_TARGET_MSB 31 +#define WLAN_LF_TIMER1_TARGET_LSB 0 +#define WLAN_LF_TIMER1_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER1_TARGET_GET(x) (((x) & WLAN_LF_TIMER1_TARGET_MASK) >> WLAN_LF_TIMER1_TARGET_LSB) +#define WLAN_LF_TIMER1_TARGET_SET(x) (((x) << WLAN_LF_TIMER1_TARGET_LSB) & WLAN_LF_TIMER1_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT1_ADDRESS 0x0000005c +#define WLAN_LF_TIMER_COUNT1_OFFSET 0x0000005c +#define WLAN_LF_TIMER_COUNT1_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT1_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT1_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT1_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) >> WLAN_LF_TIMER_COUNT1_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT1_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT1_VALUE_LSB) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL1_ADDRESS 0x00000060 +#define WLAN_LF_TIMER_CONTROL1_OFFSET 0x00000060 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL1_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL1_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL1_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL1_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) >> WLAN_LF_TIMER_CONTROL1_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL1_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_RESET_LSB) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS1_ADDRESS 0x00000064 +#define WLAN_LF_TIMER_STATUS1_OFFSET 0x00000064 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) + +#define WLAN_LF_TIMER2_ADDRESS 0x00000068 +#define WLAN_LF_TIMER2_OFFSET 0x00000068 +#define WLAN_LF_TIMER2_TARGET_MSB 31 +#define WLAN_LF_TIMER2_TARGET_LSB 0 +#define WLAN_LF_TIMER2_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER2_TARGET_GET(x) (((x) & WLAN_LF_TIMER2_TARGET_MASK) >> WLAN_LF_TIMER2_TARGET_LSB) +#define WLAN_LF_TIMER2_TARGET_SET(x) (((x) << WLAN_LF_TIMER2_TARGET_LSB) & WLAN_LF_TIMER2_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT2_ADDRESS 0x0000006c +#define WLAN_LF_TIMER_COUNT2_OFFSET 0x0000006c +#define WLAN_LF_TIMER_COUNT2_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT2_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT2_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT2_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) >> WLAN_LF_TIMER_COUNT2_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT2_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT2_VALUE_LSB) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL2_ADDRESS 0x00000070 +#define WLAN_LF_TIMER_CONTROL2_OFFSET 0x00000070 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL2_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL2_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL2_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL2_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) >> WLAN_LF_TIMER_CONTROL2_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL2_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_RESET_LSB) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS2_ADDRESS 0x00000074 +#define WLAN_LF_TIMER_STATUS2_OFFSET 0x00000074 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) + +#define WLAN_LF_TIMER3_ADDRESS 0x00000078 +#define WLAN_LF_TIMER3_OFFSET 0x00000078 +#define WLAN_LF_TIMER3_TARGET_MSB 31 +#define WLAN_LF_TIMER3_TARGET_LSB 0 +#define WLAN_LF_TIMER3_TARGET_MASK 0xffffffff +#define WLAN_LF_TIMER3_TARGET_GET(x) (((x) & WLAN_LF_TIMER3_TARGET_MASK) >> WLAN_LF_TIMER3_TARGET_LSB) +#define WLAN_LF_TIMER3_TARGET_SET(x) (((x) << WLAN_LF_TIMER3_TARGET_LSB) & WLAN_LF_TIMER3_TARGET_MASK) + +#define WLAN_LF_TIMER_COUNT3_ADDRESS 0x0000007c +#define WLAN_LF_TIMER_COUNT3_OFFSET 0x0000007c +#define WLAN_LF_TIMER_COUNT3_VALUE_MSB 31 +#define WLAN_LF_TIMER_COUNT3_VALUE_LSB 0 +#define WLAN_LF_TIMER_COUNT3_VALUE_MASK 0xffffffff +#define WLAN_LF_TIMER_COUNT3_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) >> WLAN_LF_TIMER_COUNT3_VALUE_LSB) +#define WLAN_LF_TIMER_COUNT3_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT3_VALUE_LSB) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) + +#define WLAN_LF_TIMER_CONTROL3_ADDRESS 0x00000080 +#define WLAN_LF_TIMER_CONTROL3_OFFSET 0x00000080 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_MSB 2 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_LSB 2 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 +#define WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) +#define WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) +#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) +#define WLAN_LF_TIMER_CONTROL3_RESET_MSB 0 +#define WLAN_LF_TIMER_CONTROL3_RESET_LSB 0 +#define WLAN_LF_TIMER_CONTROL3_RESET_MASK 0x00000001 +#define WLAN_LF_TIMER_CONTROL3_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) >> WLAN_LF_TIMER_CONTROL3_RESET_LSB) +#define WLAN_LF_TIMER_CONTROL3_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_RESET_LSB) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) + +#define WLAN_LF_TIMER_STATUS3_ADDRESS 0x00000084 +#define WLAN_LF_TIMER_STATUS3_OFFSET 0x00000084 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB 0 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB 0 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) +#define WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) + +#define WLAN_HF_TIMER_ADDRESS 0x00000088 +#define WLAN_HF_TIMER_OFFSET 0x00000088 +#define WLAN_HF_TIMER_TARGET_MSB 31 +#define WLAN_HF_TIMER_TARGET_LSB 12 +#define WLAN_HF_TIMER_TARGET_MASK 0xfffff000 +#define WLAN_HF_TIMER_TARGET_GET(x) (((x) & WLAN_HF_TIMER_TARGET_MASK) >> WLAN_HF_TIMER_TARGET_LSB) +#define WLAN_HF_TIMER_TARGET_SET(x) (((x) << WLAN_HF_TIMER_TARGET_LSB) & WLAN_HF_TIMER_TARGET_MASK) + +#define WLAN_HF_TIMER_COUNT_ADDRESS 0x0000008c +#define WLAN_HF_TIMER_COUNT_OFFSET 0x0000008c +#define WLAN_HF_TIMER_COUNT_VALUE_MSB 31 +#define WLAN_HF_TIMER_COUNT_VALUE_LSB 12 +#define WLAN_HF_TIMER_COUNT_VALUE_MASK 0xfffff000 +#define WLAN_HF_TIMER_COUNT_VALUE_GET(x) (((x) & WLAN_HF_TIMER_COUNT_VALUE_MASK) >> WLAN_HF_TIMER_COUNT_VALUE_LSB) +#define WLAN_HF_TIMER_COUNT_VALUE_SET(x) (((x) << WLAN_HF_TIMER_COUNT_VALUE_LSB) & WLAN_HF_TIMER_COUNT_VALUE_MASK) + +#define WLAN_HF_LF_COUNT_ADDRESS 0x00000090 +#define WLAN_HF_LF_COUNT_OFFSET 0x00000090 +#define WLAN_HF_LF_COUNT_VALUE_MSB 31 +#define WLAN_HF_LF_COUNT_VALUE_LSB 0 +#define WLAN_HF_LF_COUNT_VALUE_MASK 0xffffffff +#define WLAN_HF_LF_COUNT_VALUE_GET(x) (((x) & WLAN_HF_LF_COUNT_VALUE_MASK) >> WLAN_HF_LF_COUNT_VALUE_LSB) +#define WLAN_HF_LF_COUNT_VALUE_SET(x) (((x) << WLAN_HF_LF_COUNT_VALUE_LSB) & WLAN_HF_LF_COUNT_VALUE_MASK) + +#define WLAN_HF_TIMER_CONTROL_ADDRESS 0x00000094 +#define WLAN_HF_TIMER_CONTROL_OFFSET 0x00000094 +#define WLAN_HF_TIMER_CONTROL_ENABLE_MSB 3 +#define WLAN_HF_TIMER_CONTROL_ENABLE_LSB 3 +#define WLAN_HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 +#define WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) >> WLAN_HF_TIMER_CONTROL_ENABLE_LSB) +#define WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ENABLE_LSB) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) +#define WLAN_HF_TIMER_CONTROL_ON_MSB 2 +#define WLAN_HF_TIMER_CONTROL_ON_LSB 2 +#define WLAN_HF_TIMER_CONTROL_ON_MASK 0x00000004 +#define WLAN_HF_TIMER_CONTROL_ON_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ON_MASK) >> WLAN_HF_TIMER_CONTROL_ON_LSB) +#define WLAN_HF_TIMER_CONTROL_ON_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ON_LSB) & WLAN_HF_TIMER_CONTROL_ON_MASK) +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) +#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) +#define WLAN_HF_TIMER_CONTROL_RESET_MSB 0 +#define WLAN_HF_TIMER_CONTROL_RESET_LSB 0 +#define WLAN_HF_TIMER_CONTROL_RESET_MASK 0x00000001 +#define WLAN_HF_TIMER_CONTROL_RESET_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_RESET_MASK) >> WLAN_HF_TIMER_CONTROL_RESET_LSB) +#define WLAN_HF_TIMER_CONTROL_RESET_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_RESET_LSB) & WLAN_HF_TIMER_CONTROL_RESET_MASK) + +#define WLAN_HF_TIMER_STATUS_ADDRESS 0x00000098 +#define WLAN_HF_TIMER_STATUS_OFFSET 0x00000098 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_MSB 0 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_LSB 0 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) >> WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) +#define WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) + +#define WLAN_RTC_CONTROL_ADDRESS 0x0000009c +#define WLAN_RTC_CONTROL_OFFSET 0x0000009c +#define WLAN_RTC_CONTROL_ENABLE_MSB 2 +#define WLAN_RTC_CONTROL_ENABLE_LSB 2 +#define WLAN_RTC_CONTROL_ENABLE_MASK 0x00000004 +#define WLAN_RTC_CONTROL_ENABLE_GET(x) (((x) & WLAN_RTC_CONTROL_ENABLE_MASK) >> WLAN_RTC_CONTROL_ENABLE_LSB) +#define WLAN_RTC_CONTROL_ENABLE_SET(x) (((x) << WLAN_RTC_CONTROL_ENABLE_LSB) & WLAN_RTC_CONTROL_ENABLE_MASK) +#define WLAN_RTC_CONTROL_LOAD_RTC_MSB 1 +#define WLAN_RTC_CONTROL_LOAD_RTC_LSB 1 +#define WLAN_RTC_CONTROL_LOAD_RTC_MASK 0x00000002 +#define WLAN_RTC_CONTROL_LOAD_RTC_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) >> WLAN_RTC_CONTROL_LOAD_RTC_LSB) +#define WLAN_RTC_CONTROL_LOAD_RTC_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_RTC_LSB) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) +#define WLAN_RTC_CONTROL_LOAD_ALARM_MSB 0 +#define WLAN_RTC_CONTROL_LOAD_ALARM_LSB 0 +#define WLAN_RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 +#define WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) >> WLAN_RTC_CONTROL_LOAD_ALARM_LSB) +#define WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_ALARM_LSB) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) + +#define WLAN_RTC_TIME_ADDRESS 0x000000a0 +#define WLAN_RTC_TIME_OFFSET 0x000000a0 +#define WLAN_RTC_TIME_WEEK_DAY_MSB 26 +#define WLAN_RTC_TIME_WEEK_DAY_LSB 24 +#define WLAN_RTC_TIME_WEEK_DAY_MASK 0x07000000 +#define WLAN_RTC_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_TIME_WEEK_DAY_MASK) >> WLAN_RTC_TIME_WEEK_DAY_LSB) +#define WLAN_RTC_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_TIME_WEEK_DAY_LSB) & WLAN_RTC_TIME_WEEK_DAY_MASK) +#define WLAN_RTC_TIME_HOUR_MSB 21 +#define WLAN_RTC_TIME_HOUR_LSB 16 +#define WLAN_RTC_TIME_HOUR_MASK 0x003f0000 +#define WLAN_RTC_TIME_HOUR_GET(x) (((x) & WLAN_RTC_TIME_HOUR_MASK) >> WLAN_RTC_TIME_HOUR_LSB) +#define WLAN_RTC_TIME_HOUR_SET(x) (((x) << WLAN_RTC_TIME_HOUR_LSB) & WLAN_RTC_TIME_HOUR_MASK) +#define WLAN_RTC_TIME_MINUTE_MSB 14 +#define WLAN_RTC_TIME_MINUTE_LSB 8 +#define WLAN_RTC_TIME_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_TIME_MINUTE_MASK) >> WLAN_RTC_TIME_MINUTE_LSB) +#define WLAN_RTC_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_TIME_MINUTE_LSB) & WLAN_RTC_TIME_MINUTE_MASK) +#define WLAN_RTC_TIME_SECOND_MSB 6 +#define WLAN_RTC_TIME_SECOND_LSB 0 +#define WLAN_RTC_TIME_SECOND_MASK 0x0000007f +#define WLAN_RTC_TIME_SECOND_GET(x) (((x) & WLAN_RTC_TIME_SECOND_MASK) >> WLAN_RTC_TIME_SECOND_LSB) +#define WLAN_RTC_TIME_SECOND_SET(x) (((x) << WLAN_RTC_TIME_SECOND_LSB) & WLAN_RTC_TIME_SECOND_MASK) + +#define WLAN_RTC_DATE_ADDRESS 0x000000a4 +#define WLAN_RTC_DATE_OFFSET 0x000000a4 +#define WLAN_RTC_DATE_YEAR_MSB 23 +#define WLAN_RTC_DATE_YEAR_LSB 16 +#define WLAN_RTC_DATE_YEAR_MASK 0x00ff0000 +#define WLAN_RTC_DATE_YEAR_GET(x) (((x) & WLAN_RTC_DATE_YEAR_MASK) >> WLAN_RTC_DATE_YEAR_LSB) +#define WLAN_RTC_DATE_YEAR_SET(x) (((x) << WLAN_RTC_DATE_YEAR_LSB) & WLAN_RTC_DATE_YEAR_MASK) +#define WLAN_RTC_DATE_MONTH_MSB 12 +#define WLAN_RTC_DATE_MONTH_LSB 8 +#define WLAN_RTC_DATE_MONTH_MASK 0x00001f00 +#define WLAN_RTC_DATE_MONTH_GET(x) (((x) & WLAN_RTC_DATE_MONTH_MASK) >> WLAN_RTC_DATE_MONTH_LSB) +#define WLAN_RTC_DATE_MONTH_SET(x) (((x) << WLAN_RTC_DATE_MONTH_LSB) & WLAN_RTC_DATE_MONTH_MASK) +#define WLAN_RTC_DATE_MONTH_DAY_MSB 5 +#define WLAN_RTC_DATE_MONTH_DAY_LSB 0 +#define WLAN_RTC_DATE_MONTH_DAY_MASK 0x0000003f +#define WLAN_RTC_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_DATE_MONTH_DAY_MASK) >> WLAN_RTC_DATE_MONTH_DAY_LSB) +#define WLAN_RTC_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_DATE_MONTH_DAY_LSB) & WLAN_RTC_DATE_MONTH_DAY_MASK) + +#define WLAN_RTC_SET_TIME_ADDRESS 0x000000a8 +#define WLAN_RTC_SET_TIME_OFFSET 0x000000a8 +#define WLAN_RTC_SET_TIME_WEEK_DAY_MSB 26 +#define WLAN_RTC_SET_TIME_WEEK_DAY_LSB 24 +#define WLAN_RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 +#define WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) >> WLAN_RTC_SET_TIME_WEEK_DAY_LSB) +#define WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_SET_TIME_WEEK_DAY_LSB) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) +#define WLAN_RTC_SET_TIME_HOUR_MSB 21 +#define WLAN_RTC_SET_TIME_HOUR_LSB 16 +#define WLAN_RTC_SET_TIME_HOUR_MASK 0x003f0000 +#define WLAN_RTC_SET_TIME_HOUR_GET(x) (((x) & WLAN_RTC_SET_TIME_HOUR_MASK) >> WLAN_RTC_SET_TIME_HOUR_LSB) +#define WLAN_RTC_SET_TIME_HOUR_SET(x) (((x) << WLAN_RTC_SET_TIME_HOUR_LSB) & WLAN_RTC_SET_TIME_HOUR_MASK) +#define WLAN_RTC_SET_TIME_MINUTE_MSB 14 +#define WLAN_RTC_SET_TIME_MINUTE_LSB 8 +#define WLAN_RTC_SET_TIME_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_SET_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_SET_TIME_MINUTE_MASK) >> WLAN_RTC_SET_TIME_MINUTE_LSB) +#define WLAN_RTC_SET_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_SET_TIME_MINUTE_LSB) & WLAN_RTC_SET_TIME_MINUTE_MASK) +#define WLAN_RTC_SET_TIME_SECOND_MSB 6 +#define WLAN_RTC_SET_TIME_SECOND_LSB 0 +#define WLAN_RTC_SET_TIME_SECOND_MASK 0x0000007f +#define WLAN_RTC_SET_TIME_SECOND_GET(x) (((x) & WLAN_RTC_SET_TIME_SECOND_MASK) >> WLAN_RTC_SET_TIME_SECOND_LSB) +#define WLAN_RTC_SET_TIME_SECOND_SET(x) (((x) << WLAN_RTC_SET_TIME_SECOND_LSB) & WLAN_RTC_SET_TIME_SECOND_MASK) + +#define WLAN_RTC_SET_DATE_ADDRESS 0x000000ac +#define WLAN_RTC_SET_DATE_OFFSET 0x000000ac +#define WLAN_RTC_SET_DATE_YEAR_MSB 23 +#define WLAN_RTC_SET_DATE_YEAR_LSB 16 +#define WLAN_RTC_SET_DATE_YEAR_MASK 0x00ff0000 +#define WLAN_RTC_SET_DATE_YEAR_GET(x) (((x) & WLAN_RTC_SET_DATE_YEAR_MASK) >> WLAN_RTC_SET_DATE_YEAR_LSB) +#define WLAN_RTC_SET_DATE_YEAR_SET(x) (((x) << WLAN_RTC_SET_DATE_YEAR_LSB) & WLAN_RTC_SET_DATE_YEAR_MASK) +#define WLAN_RTC_SET_DATE_MONTH_MSB 12 +#define WLAN_RTC_SET_DATE_MONTH_LSB 8 +#define WLAN_RTC_SET_DATE_MONTH_MASK 0x00001f00 +#define WLAN_RTC_SET_DATE_MONTH_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_MASK) >> WLAN_RTC_SET_DATE_MONTH_LSB) +#define WLAN_RTC_SET_DATE_MONTH_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_LSB) & WLAN_RTC_SET_DATE_MONTH_MASK) +#define WLAN_RTC_SET_DATE_MONTH_DAY_MSB 5 +#define WLAN_RTC_SET_DATE_MONTH_DAY_LSB 0 +#define WLAN_RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f +#define WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) >> WLAN_RTC_SET_DATE_MONTH_DAY_LSB) +#define WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_DAY_LSB) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) + +#define WLAN_RTC_SET_ALARM_ADDRESS 0x000000b0 +#define WLAN_RTC_SET_ALARM_OFFSET 0x000000b0 +#define WLAN_RTC_SET_ALARM_HOUR_MSB 21 +#define WLAN_RTC_SET_ALARM_HOUR_LSB 16 +#define WLAN_RTC_SET_ALARM_HOUR_MASK 0x003f0000 +#define WLAN_RTC_SET_ALARM_HOUR_GET(x) (((x) & WLAN_RTC_SET_ALARM_HOUR_MASK) >> WLAN_RTC_SET_ALARM_HOUR_LSB) +#define WLAN_RTC_SET_ALARM_HOUR_SET(x) (((x) << WLAN_RTC_SET_ALARM_HOUR_LSB) & WLAN_RTC_SET_ALARM_HOUR_MASK) +#define WLAN_RTC_SET_ALARM_MINUTE_MSB 14 +#define WLAN_RTC_SET_ALARM_MINUTE_LSB 8 +#define WLAN_RTC_SET_ALARM_MINUTE_MASK 0x00007f00 +#define WLAN_RTC_SET_ALARM_MINUTE_GET(x) (((x) & WLAN_RTC_SET_ALARM_MINUTE_MASK) >> WLAN_RTC_SET_ALARM_MINUTE_LSB) +#define WLAN_RTC_SET_ALARM_MINUTE_SET(x) (((x) << WLAN_RTC_SET_ALARM_MINUTE_LSB) & WLAN_RTC_SET_ALARM_MINUTE_MASK) +#define WLAN_RTC_SET_ALARM_SECOND_MSB 6 +#define WLAN_RTC_SET_ALARM_SECOND_LSB 0 +#define WLAN_RTC_SET_ALARM_SECOND_MASK 0x0000007f +#define WLAN_RTC_SET_ALARM_SECOND_GET(x) (((x) & WLAN_RTC_SET_ALARM_SECOND_MASK) >> WLAN_RTC_SET_ALARM_SECOND_LSB) +#define WLAN_RTC_SET_ALARM_SECOND_SET(x) (((x) << WLAN_RTC_SET_ALARM_SECOND_LSB) & WLAN_RTC_SET_ALARM_SECOND_MASK) + +#define WLAN_RTC_CONFIG_ADDRESS 0x000000b4 +#define WLAN_RTC_CONFIG_OFFSET 0x000000b4 +#define WLAN_RTC_CONFIG_BCD_MSB 2 +#define WLAN_RTC_CONFIG_BCD_LSB 2 +#define WLAN_RTC_CONFIG_BCD_MASK 0x00000004 +#define WLAN_RTC_CONFIG_BCD_GET(x) (((x) & WLAN_RTC_CONFIG_BCD_MASK) >> WLAN_RTC_CONFIG_BCD_LSB) +#define WLAN_RTC_CONFIG_BCD_SET(x) (((x) << WLAN_RTC_CONFIG_BCD_LSB) & WLAN_RTC_CONFIG_BCD_MASK) +#define WLAN_RTC_CONFIG_TWELVE_HOUR_MSB 1 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_LSB 1 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 +#define WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) >> WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) +#define WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) +#define WLAN_RTC_CONFIG_DSE_MSB 0 +#define WLAN_RTC_CONFIG_DSE_LSB 0 +#define WLAN_RTC_CONFIG_DSE_MASK 0x00000001 +#define WLAN_RTC_CONFIG_DSE_GET(x) (((x) & WLAN_RTC_CONFIG_DSE_MASK) >> WLAN_RTC_CONFIG_DSE_LSB) +#define WLAN_RTC_CONFIG_DSE_SET(x) (((x) << WLAN_RTC_CONFIG_DSE_LSB) & WLAN_RTC_CONFIG_DSE_MASK) + +#define WLAN_RTC_ALARM_STATUS_ADDRESS 0x000000b8 +#define WLAN_RTC_ALARM_STATUS_OFFSET 0x000000b8 +#define WLAN_RTC_ALARM_STATUS_ENABLE_MSB 1 +#define WLAN_RTC_ALARM_STATUS_ENABLE_LSB 1 +#define WLAN_RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 +#define WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) >> WLAN_RTC_ALARM_STATUS_ENABLE_LSB) +#define WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_ENABLE_LSB) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB 0 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB 0 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) >> WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) +#define WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) + +#define WLAN_UART_WAKEUP_ADDRESS 0x000000bc +#define WLAN_UART_WAKEUP_OFFSET 0x000000bc +#define WLAN_UART_WAKEUP_ENABLE_MSB 0 +#define WLAN_UART_WAKEUP_ENABLE_LSB 0 +#define WLAN_UART_WAKEUP_ENABLE_MASK 0x00000001 +#define WLAN_UART_WAKEUP_ENABLE_GET(x) (((x) & WLAN_UART_WAKEUP_ENABLE_MASK) >> WLAN_UART_WAKEUP_ENABLE_LSB) +#define WLAN_UART_WAKEUP_ENABLE_SET(x) (((x) << WLAN_UART_WAKEUP_ENABLE_LSB) & WLAN_UART_WAKEUP_ENABLE_MASK) + +#define WLAN_RESET_CAUSE_ADDRESS 0x000000c0 +#define WLAN_RESET_CAUSE_OFFSET 0x000000c0 +#define WLAN_RESET_CAUSE_LAST_MSB 2 +#define WLAN_RESET_CAUSE_LAST_LSB 0 +#define WLAN_RESET_CAUSE_LAST_MASK 0x00000007 +#define WLAN_RESET_CAUSE_LAST_GET(x) (((x) & WLAN_RESET_CAUSE_LAST_MASK) >> WLAN_RESET_CAUSE_LAST_LSB) +#define WLAN_RESET_CAUSE_LAST_SET(x) (((x) << WLAN_RESET_CAUSE_LAST_LSB) & WLAN_RESET_CAUSE_LAST_MASK) + +#define WLAN_SYSTEM_SLEEP_ADDRESS 0x000000c4 +#define WLAN_SYSTEM_SLEEP_OFFSET 0x000000c4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB 4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_LSB 4 +#define WLAN_SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 +#define WLAN_SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) >> WLAN_SYSTEM_SLEEP_HOST_IF_LSB) +#define WLAN_SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_HOST_IF_LSB) & WLAN_SYSTEM_SLEEP_HOST_IF_MASK) +#define WLAN_SYSTEM_SLEEP_MBOX_MSB 3 +#define WLAN_SYSTEM_SLEEP_MBOX_LSB 3 +#define WLAN_SYSTEM_SLEEP_MBOX_MASK 0x00000008 +#define WLAN_SYSTEM_SLEEP_MBOX_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MBOX_MASK) >> WLAN_SYSTEM_SLEEP_MBOX_LSB) +#define WLAN_SYSTEM_SLEEP_MBOX_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MBOX_LSB) & WLAN_SYSTEM_SLEEP_MBOX_MASK) +#define WLAN_SYSTEM_SLEEP_MAC_IF_MSB 2 +#define WLAN_SYSTEM_SLEEP_MAC_IF_LSB 2 +#define WLAN_SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 +#define WLAN_SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) >> WLAN_SYSTEM_SLEEP_MAC_IF_LSB) +#define WLAN_SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << WLAN_SYSTEM_SLEEP_MAC_IF_LSB) & WLAN_SYSTEM_SLEEP_MAC_IF_MASK) +#define WLAN_SYSTEM_SLEEP_LIGHT_MSB 1 +#define WLAN_SYSTEM_SLEEP_LIGHT_LSB 1 +#define WLAN_SYSTEM_SLEEP_LIGHT_MASK 0x00000002 +#define WLAN_SYSTEM_SLEEP_LIGHT_GET(x) (((x) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) >> WLAN_SYSTEM_SLEEP_LIGHT_LSB) +#define WLAN_SYSTEM_SLEEP_LIGHT_SET(x) (((x) << WLAN_SYSTEM_SLEEP_LIGHT_LSB) & WLAN_SYSTEM_SLEEP_LIGHT_MASK) +#define WLAN_SYSTEM_SLEEP_DISABLE_MSB 0 +#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 +#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 +#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x) (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB) +#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) + +#define WLAN_SDIO_WRAPPER_ADDRESS 0x000000c8 +#define WLAN_SDIO_WRAPPER_OFFSET 0x000000c8 +#define WLAN_SDIO_WRAPPER_SLEEP_MSB 3 +#define WLAN_SDIO_WRAPPER_SLEEP_LSB 3 +#define WLAN_SDIO_WRAPPER_SLEEP_MASK 0x00000008 +#define WLAN_SDIO_WRAPPER_SLEEP_GET(x) (((x) & WLAN_SDIO_WRAPPER_SLEEP_MASK) >> WLAN_SDIO_WRAPPER_SLEEP_LSB) +#define WLAN_SDIO_WRAPPER_SLEEP_SET(x) (((x) << WLAN_SDIO_WRAPPER_SLEEP_LSB) & WLAN_SDIO_WRAPPER_SLEEP_MASK) +#define WLAN_SDIO_WRAPPER_WAKEUP_MSB 2 +#define WLAN_SDIO_WRAPPER_WAKEUP_LSB 2 +#define WLAN_SDIO_WRAPPER_WAKEUP_MASK 0x00000004 +#define WLAN_SDIO_WRAPPER_WAKEUP_GET(x) (((x) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) >> WLAN_SDIO_WRAPPER_WAKEUP_LSB) +#define WLAN_SDIO_WRAPPER_WAKEUP_SET(x) (((x) << WLAN_SDIO_WRAPPER_WAKEUP_LSB) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) +#define WLAN_SDIO_WRAPPER_SOC_ON_MSB 1 +#define WLAN_SDIO_WRAPPER_SOC_ON_LSB 1 +#define WLAN_SDIO_WRAPPER_SOC_ON_MASK 0x00000002 +#define WLAN_SDIO_WRAPPER_SOC_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) >> WLAN_SDIO_WRAPPER_SOC_ON_LSB) +#define WLAN_SDIO_WRAPPER_SOC_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_SOC_ON_LSB) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) +#define WLAN_SDIO_WRAPPER_ON_MSB 0 +#define WLAN_SDIO_WRAPPER_ON_LSB 0 +#define WLAN_SDIO_WRAPPER_ON_MASK 0x00000001 +#define WLAN_SDIO_WRAPPER_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_ON_MASK) >> WLAN_SDIO_WRAPPER_ON_LSB) +#define WLAN_SDIO_WRAPPER_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_ON_LSB) & WLAN_SDIO_WRAPPER_ON_MASK) + +#define WLAN_MAC_SLEEP_CONTROL_ADDRESS 0x000000cc +#define WLAN_MAC_SLEEP_CONTROL_OFFSET 0x000000cc +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB 1 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB 0 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) >> WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) +#define WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) + +#define WLAN_KEEP_AWAKE_ADDRESS 0x000000d0 +#define WLAN_KEEP_AWAKE_OFFSET 0x000000d0 +#define WLAN_KEEP_AWAKE_COUNT_MSB 7 +#define WLAN_KEEP_AWAKE_COUNT_LSB 0 +#define WLAN_KEEP_AWAKE_COUNT_MASK 0x000000ff +#define WLAN_KEEP_AWAKE_COUNT_GET(x) (((x) & WLAN_KEEP_AWAKE_COUNT_MASK) >> WLAN_KEEP_AWAKE_COUNT_LSB) +#define WLAN_KEEP_AWAKE_COUNT_SET(x) (((x) << WLAN_KEEP_AWAKE_COUNT_LSB) & WLAN_KEEP_AWAKE_COUNT_MASK) + +#define WLAN_LPO_CAL_TIME_ADDRESS 0x000000d4 +#define WLAN_LPO_CAL_TIME_OFFSET 0x000000d4 +#define WLAN_LPO_CAL_TIME_LENGTH_MSB 13 +#define WLAN_LPO_CAL_TIME_LENGTH_LSB 0 +#define WLAN_LPO_CAL_TIME_LENGTH_MASK 0x00003fff +#define WLAN_LPO_CAL_TIME_LENGTH_GET(x) (((x) & WLAN_LPO_CAL_TIME_LENGTH_MASK) >> WLAN_LPO_CAL_TIME_LENGTH_LSB) +#define WLAN_LPO_CAL_TIME_LENGTH_SET(x) (((x) << WLAN_LPO_CAL_TIME_LENGTH_LSB) & WLAN_LPO_CAL_TIME_LENGTH_MASK) + +#define WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 +#define WLAN_LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) +#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) + +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) +#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) + +#define WLAN_LPO_CAL_ADDRESS 0x000000e0 +#define WLAN_LPO_CAL_OFFSET 0x000000e0 +#define WLAN_LPO_CAL_ENABLE_MSB 20 +#define WLAN_LPO_CAL_ENABLE_LSB 20 +#define WLAN_LPO_CAL_ENABLE_MASK 0x00100000 +#define WLAN_LPO_CAL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_ENABLE_MASK) >> WLAN_LPO_CAL_ENABLE_LSB) +#define WLAN_LPO_CAL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_ENABLE_LSB) & WLAN_LPO_CAL_ENABLE_MASK) +#define WLAN_LPO_CAL_COUNT_MSB 19 +#define WLAN_LPO_CAL_COUNT_LSB 0 +#define WLAN_LPO_CAL_COUNT_MASK 0x000fffff +#define WLAN_LPO_CAL_COUNT_GET(x) (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB) +#define WLAN_LPO_CAL_COUNT_SET(x) (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK) + +#define WLAN_LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 +#define WLAN_LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) +#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) +#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) + +#define WLAN_LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 +#define WLAN_LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 +#define WLAN_LPO_CAL_TEST_STATUS_READY_MSB 16 +#define WLAN_LPO_CAL_TEST_STATUS_READY_LSB 16 +#define WLAN_LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 +#define WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) >> WLAN_LPO_CAL_TEST_STATUS_READY_LSB) +#define WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_READY_LSB) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB 15 +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB 0 +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) >> WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) +#define WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) + +#define WLAN_CHIP_ID_ADDRESS 0x000000ec +#define WLAN_CHIP_ID_OFFSET 0x000000ec +#define WLAN_CHIP_ID_DEVICE_ID_MSB 31 +#define WLAN_CHIP_ID_DEVICE_ID_LSB 16 +#define WLAN_CHIP_ID_DEVICE_ID_MASK 0xffff0000 +#define WLAN_CHIP_ID_DEVICE_ID_GET(x) (((x) & WLAN_CHIP_ID_DEVICE_ID_MASK) >> WLAN_CHIP_ID_DEVICE_ID_LSB) +#define WLAN_CHIP_ID_DEVICE_ID_SET(x) (((x) << WLAN_CHIP_ID_DEVICE_ID_LSB) & WLAN_CHIP_ID_DEVICE_ID_MASK) +#define WLAN_CHIP_ID_CONFIG_ID_MSB 15 +#define WLAN_CHIP_ID_CONFIG_ID_LSB 4 +#define WLAN_CHIP_ID_CONFIG_ID_MASK 0x0000fff0 +#define WLAN_CHIP_ID_CONFIG_ID_GET(x) (((x) & WLAN_CHIP_ID_CONFIG_ID_MASK) >> WLAN_CHIP_ID_CONFIG_ID_LSB) +#define WLAN_CHIP_ID_CONFIG_ID_SET(x) (((x) << WLAN_CHIP_ID_CONFIG_ID_LSB) & WLAN_CHIP_ID_CONFIG_ID_MASK) +#define WLAN_CHIP_ID_VERSION_ID_MSB 3 +#define WLAN_CHIP_ID_VERSION_ID_LSB 0 +#define WLAN_CHIP_ID_VERSION_ID_MASK 0x0000000f +#define WLAN_CHIP_ID_VERSION_ID_GET(x) (((x) & WLAN_CHIP_ID_VERSION_ID_MASK) >> WLAN_CHIP_ID_VERSION_ID_LSB) +#define WLAN_CHIP_ID_VERSION_ID_SET(x) (((x) << WLAN_CHIP_ID_VERSION_ID_LSB) & WLAN_CHIP_ID_VERSION_ID_MASK) + +#define WLAN_DERIVED_RTC_CLK_ADDRESS 0x000000f0 +#define WLAN_DERIVED_RTC_CLK_OFFSET 0x000000f0 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) +#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) +#define WLAN_DERIVED_RTC_CLK_FORCE_MSB 17 +#define WLAN_DERIVED_RTC_CLK_FORCE_LSB 16 +#define WLAN_DERIVED_RTC_CLK_FORCE_MASK 0x00030000 +#define WLAN_DERIVED_RTC_CLK_FORCE_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) >> WLAN_DERIVED_RTC_CLK_FORCE_LSB) +#define WLAN_DERIVED_RTC_CLK_FORCE_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_FORCE_LSB) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) +#define WLAN_DERIVED_RTC_CLK_PERIOD_MSB 15 +#define WLAN_DERIVED_RTC_CLK_PERIOD_LSB 1 +#define WLAN_DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe +#define WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) >> WLAN_DERIVED_RTC_CLK_PERIOD_LSB) +#define WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_PERIOD_LSB) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) + +#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 +#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MSB 24 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB 24 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK 0x01000000 +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) +#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MSB 23 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB 23 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK 0x00800000 +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_GET(x) (((x) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) >> MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) +#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_SET(x) (((x) << MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MSB 22 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB 22 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK 0x00400000 +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_GET(x) (((x) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) >> MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) +#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_SET(x) (((x) << MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB 21 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK 0x00200000 +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) +#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) +#define MAC_PCU_SLP32_MODE_ENABLE_MSB 20 +#define MAC_PCU_SLP32_MODE_ENABLE_LSB 20 +#define MAC_PCU_SLP32_MODE_ENABLE_MASK 0x00100000 +#define MAC_PCU_SLP32_MODE_ENABLE_GET(x) (((x) & MAC_PCU_SLP32_MODE_ENABLE_MASK) >> MAC_PCU_SLP32_MODE_ENABLE_LSB) +#define MAC_PCU_SLP32_MODE_ENABLE_SET(x) (((x) << MAC_PCU_SLP32_MODE_ENABLE_LSB) & MAC_PCU_SLP32_MODE_ENABLE_MASK) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) +#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) + +#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 +#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 +#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff +#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) +#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) + +#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc +#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc +#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 +#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 +#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff +#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) +#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) + +#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 +#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) +#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) + +#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 +#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) +#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) + +#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 +#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 +#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 +#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 +#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) +#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) +#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 +#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 +#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) +#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) + +#define WLAN_POWER_REG_ADDRESS 0x0000010c +#define WLAN_POWER_REG_OFFSET 0x0000010c +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB 15 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB 15 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK 0x00008000 +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) (((x) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) >> WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) +#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) (((x) << WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) +#define WLAN_POWER_REG_DEBUG_EN_MSB 14 +#define WLAN_POWER_REG_DEBUG_EN_LSB 14 +#define WLAN_POWER_REG_DEBUG_EN_MASK 0x00004000 +#define WLAN_POWER_REG_DEBUG_EN_GET(x) (((x) & WLAN_POWER_REG_DEBUG_EN_MASK) >> WLAN_POWER_REG_DEBUG_EN_LSB) +#define WLAN_POWER_REG_DEBUG_EN_SET(x) (((x) << WLAN_POWER_REG_DEBUG_EN_LSB) & WLAN_POWER_REG_DEBUG_EN_MASK) +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB 13 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB 13 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK 0x00002000 +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB 12 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB 12 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK 0x00001000 +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) +#define WLAN_POWER_REG_VLVL_MSB 11 +#define WLAN_POWER_REG_VLVL_LSB 8 +#define WLAN_POWER_REG_VLVL_MASK 0x00000f00 +#define WLAN_POWER_REG_VLVL_GET(x) (((x) & WLAN_POWER_REG_VLVL_MASK) >> WLAN_POWER_REG_VLVL_LSB) +#define WLAN_POWER_REG_VLVL_SET(x) (((x) << WLAN_POWER_REG_VLVL_LSB) & WLAN_POWER_REG_VLVL_MASK) +#define WLAN_POWER_REG_CPU_INT_ENABLE_MSB 7 +#define WLAN_POWER_REG_CPU_INT_ENABLE_LSB 7 +#define WLAN_POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 +#define WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) >> WLAN_POWER_REG_CPU_INT_ENABLE_LSB) +#define WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << WLAN_POWER_REG_CPU_INT_ENABLE_LSB) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) +#define WLAN_POWER_REG_WLAN_ISO_DIS_MSB 6 +#define WLAN_POWER_REG_WLAN_ISO_DIS_LSB 6 +#define WLAN_POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 +#define WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) >> WLAN_POWER_REG_WLAN_ISO_DIS_LSB) +#define WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_DIS_LSB) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) +#define WLAN_POWER_REG_WLAN_ISO_CNTL_MSB 5 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_LSB 5 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 +#define WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) >> WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) +#define WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) +#define WLAN_POWER_REG_RADIO_PWD_EN_MSB 4 +#define WLAN_POWER_REG_RADIO_PWD_EN_LSB 4 +#define WLAN_POWER_REG_RADIO_PWD_EN_MASK 0x00000010 +#define WLAN_POWER_REG_RADIO_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) >> WLAN_POWER_REG_RADIO_PWD_EN_LSB) +#define WLAN_POWER_REG_RADIO_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_RADIO_PWD_EN_LSB) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) +#define WLAN_POWER_REG_SOC_ISO_EN_MSB 3 +#define WLAN_POWER_REG_SOC_ISO_EN_LSB 3 +#define WLAN_POWER_REG_SOC_ISO_EN_MASK 0x00000008 +#define WLAN_POWER_REG_SOC_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_SOC_ISO_EN_MASK) >> WLAN_POWER_REG_SOC_ISO_EN_LSB) +#define WLAN_POWER_REG_SOC_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_SOC_ISO_EN_LSB) & WLAN_POWER_REG_SOC_ISO_EN_MASK) +#define WLAN_POWER_REG_WLAN_ISO_EN_MSB 2 +#define WLAN_POWER_REG_WLAN_ISO_EN_LSB 2 +#define WLAN_POWER_REG_WLAN_ISO_EN_MASK 0x00000004 +#define WLAN_POWER_REG_WLAN_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) >> WLAN_POWER_REG_WLAN_ISO_EN_LSB) +#define WLAN_POWER_REG_WLAN_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_EN_LSB) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) +#define WLAN_POWER_REG_WLAN_PWD_EN_MSB 1 +#define WLAN_POWER_REG_WLAN_PWD_EN_LSB 1 +#define WLAN_POWER_REG_WLAN_PWD_EN_MASK 0x00000002 +#define WLAN_POWER_REG_WLAN_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_PWD_EN_LSB) +#define WLAN_POWER_REG_WLAN_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) +#define WLAN_POWER_REG_POWER_EN_MSB 0 +#define WLAN_POWER_REG_POWER_EN_LSB 0 +#define WLAN_POWER_REG_POWER_EN_MASK 0x00000001 +#define WLAN_POWER_REG_POWER_EN_GET(x) (((x) & WLAN_POWER_REG_POWER_EN_MASK) >> WLAN_POWER_REG_POWER_EN_LSB) +#define WLAN_POWER_REG_POWER_EN_SET(x) (((x) << WLAN_POWER_REG_POWER_EN_LSB) & WLAN_POWER_REG_POWER_EN_MASK) + +#define WLAN_CORE_CLK_CTRL_ADDRESS 0x00000110 +#define WLAN_CORE_CLK_CTRL_OFFSET 0x00000110 +#define WLAN_CORE_CLK_CTRL_DIV_MSB 2 +#define WLAN_CORE_CLK_CTRL_DIV_LSB 0 +#define WLAN_CORE_CLK_CTRL_DIV_MASK 0x00000007 +#define WLAN_CORE_CLK_CTRL_DIV_GET(x) (((x) & WLAN_CORE_CLK_CTRL_DIV_MASK) >> WLAN_CORE_CLK_CTRL_DIV_LSB) +#define WLAN_CORE_CLK_CTRL_DIV_SET(x) (((x) << WLAN_CORE_CLK_CTRL_DIV_LSB) & WLAN_CORE_CLK_CTRL_DIV_MASK) + +#define WLAN_GPIO_WAKEUP_CONTROL_ADDRESS 0x00000114 +#define WLAN_GPIO_WAKEUP_CONTROL_OFFSET 0x00000114 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) +#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) + +#define HT_ADDRESS 0x00000118 +#define HT_OFFSET 0x00000118 +#define HT_MODE_MSB 0 +#define HT_MODE_LSB 0 +#define HT_MODE_MASK 0x00000001 +#define HT_MODE_GET(x) (((x) & HT_MODE_MASK) >> HT_MODE_LSB) +#define HT_MODE_SET(x) (((x) << HT_MODE_LSB) & HT_MODE_MASK) + +#define MAC_PCU_TSF_L32_ADDRESS 0x0000011c +#define MAC_PCU_TSF_L32_OFFSET 0x0000011c +#define MAC_PCU_TSF_L32_VALUE_MSB 31 +#define MAC_PCU_TSF_L32_VALUE_LSB 0 +#define MAC_PCU_TSF_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF_L32_VALUE_MASK) >> MAC_PCU_TSF_L32_VALUE_LSB) +#define MAC_PCU_TSF_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF_L32_VALUE_LSB) & MAC_PCU_TSF_L32_VALUE_MASK) + +#define MAC_PCU_TSF_U32_ADDRESS 0x00000120 +#define MAC_PCU_TSF_U32_OFFSET 0x00000120 +#define MAC_PCU_TSF_U32_VALUE_MSB 31 +#define MAC_PCU_TSF_U32_VALUE_LSB 0 +#define MAC_PCU_TSF_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF_U32_VALUE_MASK) >> MAC_PCU_TSF_U32_VALUE_LSB) +#define MAC_PCU_TSF_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF_U32_VALUE_LSB) & MAC_PCU_TSF_U32_VALUE_MASK) + +#define MAC_PCU_WBTIMER_ADDRESS 0x00000124 +#define MAC_PCU_WBTIMER_OFFSET 0x00000124 +#define MAC_PCU_WBTIMER_VALUE_MSB 31 +#define MAC_PCU_WBTIMER_VALUE_LSB 0 +#define MAC_PCU_WBTIMER_VALUE_MASK 0xffffffff +#define MAC_PCU_WBTIMER_VALUE_GET(x) (((x) & MAC_PCU_WBTIMER_VALUE_MASK) >> MAC_PCU_WBTIMER_VALUE_LSB) +#define MAC_PCU_WBTIMER_VALUE_SET(x) (((x) << MAC_PCU_WBTIMER_VALUE_LSB) & MAC_PCU_WBTIMER_VALUE_MASK) + +#define MAC_PCU_GENERIC_TIMERS_ADDRESS 0x00000140 +#define MAC_PCU_GENERIC_TIMERS_OFFSET 0x00000140 +#define MAC_PCU_GENERIC_TIMERS_DATA_MSB 31 +#define MAC_PCU_GENERIC_TIMERS_DATA_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_DATA_MASK 0xffffffff +#define MAC_PCU_GENERIC_TIMERS_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS_DATA_LSB) +#define MAC_PCU_GENERIC_TIMERS_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_DATA_LSB) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE_ADDRESS 0x00000180 +#define MAC_PCU_GENERIC_TIMERS_MODE_OFFSET 0x00000180 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MSB 15 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK 0x0000ffff +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) + +#define MAC_PCU_GENERIC_TIMERS2_ADDRESS 0x000001c0 +#define MAC_PCU_GENERIC_TIMERS2_OFFSET 0x000001c0 +#define MAC_PCU_GENERIC_TIMERS2_DATA_MSB 31 +#define MAC_PCU_GENERIC_TIMERS2_DATA_LSB 0 +#define MAC_PCU_GENERIC_TIMERS2_DATA_MASK 0xffffffff +#define MAC_PCU_GENERIC_TIMERS2_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS2_DATA_LSB) +#define MAC_PCU_GENERIC_TIMERS2_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS2_DATA_LSB) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE2_ADDRESS 0x00000200 +#define MAC_PCU_GENERIC_TIMERS_MODE2_OFFSET 0x00000200 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MSB 15 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK 0x0000ffff +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) + +#define MAC_PCU_SLP1_ADDRESS 0x00000204 +#define MAC_PCU_SLP1_OFFSET 0x00000204 +#define MAC_PCU_SLP1_ASSUME_DTIM_MSB 19 +#define MAC_PCU_SLP1_ASSUME_DTIM_LSB 19 +#define MAC_PCU_SLP1_ASSUME_DTIM_MASK 0x00080000 +#define MAC_PCU_SLP1_ASSUME_DTIM_GET(x) (((x) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) >> MAC_PCU_SLP1_ASSUME_DTIM_LSB) +#define MAC_PCU_SLP1_ASSUME_DTIM_SET(x) (((x) << MAC_PCU_SLP1_ASSUME_DTIM_LSB) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) +#define MAC_PCU_SLP1_CAB_TIMEOUT_MSB 15 +#define MAC_PCU_SLP1_CAB_TIMEOUT_LSB 0 +#define MAC_PCU_SLP1_CAB_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_SLP1_CAB_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) >> MAC_PCU_SLP1_CAB_TIMEOUT_LSB) +#define MAC_PCU_SLP1_CAB_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP1_CAB_TIMEOUT_LSB) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) + +#define MAC_PCU_SLP2_ADDRESS 0x00000208 +#define MAC_PCU_SLP2_OFFSET 0x00000208 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_MSB 15 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_LSB 0 +#define MAC_PCU_SLP2_BEACON_TIMEOUT_MASK 0x0000ffff +#define MAC_PCU_SLP2_BEACON_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) >> MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) +#define MAC_PCU_SLP2_BEACON_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) + +#define MAC_PCU_RESET_TSF_ADDRESS 0x0000020c +#define MAC_PCU_RESET_TSF_OFFSET 0x0000020c +#define MAC_PCU_RESET_TSF_ONE_SHOT2_MSB 25 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_LSB 25 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_MASK 0x02000000 +#define MAC_PCU_RESET_TSF_ONE_SHOT2_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) +#define MAC_PCU_RESET_TSF_ONE_SHOT2_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) +#define MAC_PCU_RESET_TSF_ONE_SHOT_MSB 24 +#define MAC_PCU_RESET_TSF_ONE_SHOT_LSB 24 +#define MAC_PCU_RESET_TSF_ONE_SHOT_MASK 0x01000000 +#define MAC_PCU_RESET_TSF_ONE_SHOT_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT_LSB) +#define MAC_PCU_RESET_TSF_ONE_SHOT_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) + +#define MAC_PCU_TSF_ADD_PLL_ADDRESS 0x00000210 +#define MAC_PCU_TSF_ADD_PLL_OFFSET 0x00000210 +#define MAC_PCU_TSF_ADD_PLL_VALUE_MSB 7 +#define MAC_PCU_TSF_ADD_PLL_VALUE_LSB 0 +#define MAC_PCU_TSF_ADD_PLL_VALUE_MASK 0x000000ff +#define MAC_PCU_TSF_ADD_PLL_VALUE_GET(x) (((x) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) >> MAC_PCU_TSF_ADD_PLL_VALUE_LSB) +#define MAC_PCU_TSF_ADD_PLL_VALUE_SET(x) (((x) << MAC_PCU_TSF_ADD_PLL_VALUE_LSB) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) + +#define SLEEP_RETENTION_ADDRESS 0x00000214 +#define SLEEP_RETENTION_OFFSET 0x00000214 +#define SLEEP_RETENTION_TIME_MSB 9 +#define SLEEP_RETENTION_TIME_LSB 2 +#define SLEEP_RETENTION_TIME_MASK 0x000003fc +#define SLEEP_RETENTION_TIME_GET(x) (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB) +#define SLEEP_RETENTION_TIME_SET(x) (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK) +#define SLEEP_RETENTION_MODE_MSB 1 +#define SLEEP_RETENTION_MODE_LSB 1 +#define SLEEP_RETENTION_MODE_MASK 0x00000002 +#define SLEEP_RETENTION_MODE_GET(x) (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB) +#define SLEEP_RETENTION_MODE_SET(x) (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK) +#define SLEEP_RETENTION_ENABLE_MSB 0 +#define SLEEP_RETENTION_ENABLE_LSB 0 +#define SLEEP_RETENTION_ENABLE_MASK 0x00000001 +#define SLEEP_RETENTION_ENABLE_GET(x) (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB) +#define SLEEP_RETENTION_ENABLE_SET(x) (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK) + +#define BTCOEXCTRL_ADDRESS 0x00000218 +#define BTCOEXCTRL_OFFSET 0x00000218 +#define BTCOEXCTRL_WBTIMER_ENABLE_MSB 26 +#define BTCOEXCTRL_WBTIMER_ENABLE_LSB 26 +#define BTCOEXCTRL_WBTIMER_ENABLE_MASK 0x04000000 +#define BTCOEXCTRL_WBTIMER_ENABLE_GET(x) (((x) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) >> BTCOEXCTRL_WBTIMER_ENABLE_LSB) +#define BTCOEXCTRL_WBTIMER_ENABLE_SET(x) (((x) << BTCOEXCTRL_WBTIMER_ENABLE_LSB) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) +#define BTCOEXCTRL_WBSYNC_ON_BEACON_MSB 25 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_LSB 25 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_MASK 0x02000000 +#define BTCOEXCTRL_WBSYNC_ON_BEACON_GET(x) (((x) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) >> BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) +#define BTCOEXCTRL_WBSYNC_ON_BEACON_SET(x) (((x) << BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) +#define BTCOEXCTRL_PTA_MODE_MSB 24 +#define BTCOEXCTRL_PTA_MODE_LSB 23 +#define BTCOEXCTRL_PTA_MODE_MASK 0x01800000 +#define BTCOEXCTRL_PTA_MODE_GET(x) (((x) & BTCOEXCTRL_PTA_MODE_MASK) >> BTCOEXCTRL_PTA_MODE_LSB) +#define BTCOEXCTRL_PTA_MODE_SET(x) (((x) << BTCOEXCTRL_PTA_MODE_LSB) & BTCOEXCTRL_PTA_MODE_MASK) +#define BTCOEXCTRL_FREQ_TIME_MSB 22 +#define BTCOEXCTRL_FREQ_TIME_LSB 18 +#define BTCOEXCTRL_FREQ_TIME_MASK 0x007c0000 +#define BTCOEXCTRL_FREQ_TIME_GET(x) (((x) & BTCOEXCTRL_FREQ_TIME_MASK) >> BTCOEXCTRL_FREQ_TIME_LSB) +#define BTCOEXCTRL_FREQ_TIME_SET(x) (((x) << BTCOEXCTRL_FREQ_TIME_LSB) & BTCOEXCTRL_FREQ_TIME_MASK) +#define BTCOEXCTRL_PRIORITY_TIME_MSB 17 +#define BTCOEXCTRL_PRIORITY_TIME_LSB 12 +#define BTCOEXCTRL_PRIORITY_TIME_MASK 0x0003f000 +#define BTCOEXCTRL_PRIORITY_TIME_GET(x) (((x) & BTCOEXCTRL_PRIORITY_TIME_MASK) >> BTCOEXCTRL_PRIORITY_TIME_LSB) +#define BTCOEXCTRL_PRIORITY_TIME_SET(x) (((x) << BTCOEXCTRL_PRIORITY_TIME_LSB) & BTCOEXCTRL_PRIORITY_TIME_MASK) +#define BTCOEXCTRL_SYNC_DET_EN_MSB 11 +#define BTCOEXCTRL_SYNC_DET_EN_LSB 11 +#define BTCOEXCTRL_SYNC_DET_EN_MASK 0x00000800 +#define BTCOEXCTRL_SYNC_DET_EN_GET(x) (((x) & BTCOEXCTRL_SYNC_DET_EN_MASK) >> BTCOEXCTRL_SYNC_DET_EN_LSB) +#define BTCOEXCTRL_SYNC_DET_EN_SET(x) (((x) << BTCOEXCTRL_SYNC_DET_EN_LSB) & BTCOEXCTRL_SYNC_DET_EN_MASK) +#define BTCOEXCTRL_IDLE_CNT_EN_MSB 10 +#define BTCOEXCTRL_IDLE_CNT_EN_LSB 10 +#define BTCOEXCTRL_IDLE_CNT_EN_MASK 0x00000400 +#define BTCOEXCTRL_IDLE_CNT_EN_GET(x) (((x) & BTCOEXCTRL_IDLE_CNT_EN_MASK) >> BTCOEXCTRL_IDLE_CNT_EN_LSB) +#define BTCOEXCTRL_IDLE_CNT_EN_SET(x) (((x) << BTCOEXCTRL_IDLE_CNT_EN_LSB) & BTCOEXCTRL_IDLE_CNT_EN_MASK) +#define BTCOEXCTRL_FRAME_CNT_EN_MSB 9 +#define BTCOEXCTRL_FRAME_CNT_EN_LSB 9 +#define BTCOEXCTRL_FRAME_CNT_EN_MASK 0x00000200 +#define BTCOEXCTRL_FRAME_CNT_EN_GET(x) (((x) & BTCOEXCTRL_FRAME_CNT_EN_MASK) >> BTCOEXCTRL_FRAME_CNT_EN_LSB) +#define BTCOEXCTRL_FRAME_CNT_EN_SET(x) (((x) << BTCOEXCTRL_FRAME_CNT_EN_LSB) & BTCOEXCTRL_FRAME_CNT_EN_MASK) +#define BTCOEXCTRL_CLK_CNT_EN_MSB 8 +#define BTCOEXCTRL_CLK_CNT_EN_LSB 8 +#define BTCOEXCTRL_CLK_CNT_EN_MASK 0x00000100 +#define BTCOEXCTRL_CLK_CNT_EN_GET(x) (((x) & BTCOEXCTRL_CLK_CNT_EN_MASK) >> BTCOEXCTRL_CLK_CNT_EN_LSB) +#define BTCOEXCTRL_CLK_CNT_EN_SET(x) (((x) << BTCOEXCTRL_CLK_CNT_EN_LSB) & BTCOEXCTRL_CLK_CNT_EN_MASK) +#define BTCOEXCTRL_GAP_MSB 7 +#define BTCOEXCTRL_GAP_LSB 0 +#define BTCOEXCTRL_GAP_MASK 0x000000ff +#define BTCOEXCTRL_GAP_GET(x) (((x) & BTCOEXCTRL_GAP_MASK) >> BTCOEXCTRL_GAP_LSB) +#define BTCOEXCTRL_GAP_SET(x) (((x) << BTCOEXCTRL_GAP_LSB) & BTCOEXCTRL_GAP_MASK) + +#define WBSYNC_PRIORITY1_ADDRESS 0x0000021c +#define WBSYNC_PRIORITY1_OFFSET 0x0000021c +#define WBSYNC_PRIORITY1_BITMAP_MSB 31 +#define WBSYNC_PRIORITY1_BITMAP_LSB 0 +#define WBSYNC_PRIORITY1_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY1_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY1_BITMAP_MASK) >> WBSYNC_PRIORITY1_BITMAP_LSB) +#define WBSYNC_PRIORITY1_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY1_BITMAP_LSB) & WBSYNC_PRIORITY1_BITMAP_MASK) + +#define WBSYNC_PRIORITY2_ADDRESS 0x00000220 +#define WBSYNC_PRIORITY2_OFFSET 0x00000220 +#define WBSYNC_PRIORITY2_BITMAP_MSB 31 +#define WBSYNC_PRIORITY2_BITMAP_LSB 0 +#define WBSYNC_PRIORITY2_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY2_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY2_BITMAP_MASK) >> WBSYNC_PRIORITY2_BITMAP_LSB) +#define WBSYNC_PRIORITY2_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY2_BITMAP_LSB) & WBSYNC_PRIORITY2_BITMAP_MASK) + +#define WBSYNC_PRIORITY3_ADDRESS 0x00000224 +#define WBSYNC_PRIORITY3_OFFSET 0x00000224 +#define WBSYNC_PRIORITY3_BITMAP_MSB 31 +#define WBSYNC_PRIORITY3_BITMAP_LSB 0 +#define WBSYNC_PRIORITY3_BITMAP_MASK 0xffffffff +#define WBSYNC_PRIORITY3_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY3_BITMAP_MASK) >> WBSYNC_PRIORITY3_BITMAP_LSB) +#define WBSYNC_PRIORITY3_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY3_BITMAP_LSB) & WBSYNC_PRIORITY3_BITMAP_MASK) + +#define BTCOEX0_ADDRESS 0x00000228 +#define BTCOEX0_OFFSET 0x00000228 +#define BTCOEX0_SYNC_DUR_MSB 7 +#define BTCOEX0_SYNC_DUR_LSB 0 +#define BTCOEX0_SYNC_DUR_MASK 0x000000ff +#define BTCOEX0_SYNC_DUR_GET(x) (((x) & BTCOEX0_SYNC_DUR_MASK) >> BTCOEX0_SYNC_DUR_LSB) +#define BTCOEX0_SYNC_DUR_SET(x) (((x) << BTCOEX0_SYNC_DUR_LSB) & BTCOEX0_SYNC_DUR_MASK) + +#define BTCOEX1_ADDRESS 0x0000022c +#define BTCOEX1_OFFSET 0x0000022c +#define BTCOEX1_CLK_THRES_MSB 20 +#define BTCOEX1_CLK_THRES_LSB 0 +#define BTCOEX1_CLK_THRES_MASK 0x001fffff +#define BTCOEX1_CLK_THRES_GET(x) (((x) & BTCOEX1_CLK_THRES_MASK) >> BTCOEX1_CLK_THRES_LSB) +#define BTCOEX1_CLK_THRES_SET(x) (((x) << BTCOEX1_CLK_THRES_LSB) & BTCOEX1_CLK_THRES_MASK) + +#define BTCOEX2_ADDRESS 0x00000230 +#define BTCOEX2_OFFSET 0x00000230 +#define BTCOEX2_FRAME_THRES_MSB 7 +#define BTCOEX2_FRAME_THRES_LSB 0 +#define BTCOEX2_FRAME_THRES_MASK 0x000000ff +#define BTCOEX2_FRAME_THRES_GET(x) (((x) & BTCOEX2_FRAME_THRES_MASK) >> BTCOEX2_FRAME_THRES_LSB) +#define BTCOEX2_FRAME_THRES_SET(x) (((x) << BTCOEX2_FRAME_THRES_LSB) & BTCOEX2_FRAME_THRES_MASK) + +#define BTCOEX3_ADDRESS 0x00000234 +#define BTCOEX3_OFFSET 0x00000234 +#define BTCOEX3_CLK_CNT_MSB 20 +#define BTCOEX3_CLK_CNT_LSB 0 +#define BTCOEX3_CLK_CNT_MASK 0x001fffff +#define BTCOEX3_CLK_CNT_GET(x) (((x) & BTCOEX3_CLK_CNT_MASK) >> BTCOEX3_CLK_CNT_LSB) +#define BTCOEX3_CLK_CNT_SET(x) (((x) << BTCOEX3_CLK_CNT_LSB) & BTCOEX3_CLK_CNT_MASK) + +#define BTCOEX4_ADDRESS 0x00000238 +#define BTCOEX4_OFFSET 0x00000238 +#define BTCOEX4_FRAME_CNT_MSB 7 +#define BTCOEX4_FRAME_CNT_LSB 0 +#define BTCOEX4_FRAME_CNT_MASK 0x000000ff +#define BTCOEX4_FRAME_CNT_GET(x) (((x) & BTCOEX4_FRAME_CNT_MASK) >> BTCOEX4_FRAME_CNT_LSB) +#define BTCOEX4_FRAME_CNT_SET(x) (((x) << BTCOEX4_FRAME_CNT_LSB) & BTCOEX4_FRAME_CNT_MASK) + +#define BTCOEX5_ADDRESS 0x0000023c +#define BTCOEX5_OFFSET 0x0000023c +#define BTCOEX5_IDLE_CNT_MSB 15 +#define BTCOEX5_IDLE_CNT_LSB 0 +#define BTCOEX5_IDLE_CNT_MASK 0x0000ffff +#define BTCOEX5_IDLE_CNT_GET(x) (((x) & BTCOEX5_IDLE_CNT_MASK) >> BTCOEX5_IDLE_CNT_LSB) +#define BTCOEX5_IDLE_CNT_SET(x) (((x) << BTCOEX5_IDLE_CNT_LSB) & BTCOEX5_IDLE_CNT_MASK) + +#define BTCOEX6_ADDRESS 0x00000240 +#define BTCOEX6_OFFSET 0x00000240 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MSB 31 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB 0 +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK 0xffffffff +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_GET(x) (((x) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) >> BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) +#define BTCOEX6_IDLE_RESET_LVL_BITMAP_SET(x) (((x) << BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) + +#define LOCK_ADDRESS 0x00000244 +#define LOCK_OFFSET 0x00000244 +#define LOCK_TLOCK_SLAVE_MSB 31 +#define LOCK_TLOCK_SLAVE_LSB 24 +#define LOCK_TLOCK_SLAVE_MASK 0xff000000 +#define LOCK_TLOCK_SLAVE_GET(x) (((x) & LOCK_TLOCK_SLAVE_MASK) >> LOCK_TLOCK_SLAVE_LSB) +#define LOCK_TLOCK_SLAVE_SET(x) (((x) << LOCK_TLOCK_SLAVE_LSB) & LOCK_TLOCK_SLAVE_MASK) +#define LOCK_TUNLOCK_SLAVE_MSB 23 +#define LOCK_TUNLOCK_SLAVE_LSB 16 +#define LOCK_TUNLOCK_SLAVE_MASK 0x00ff0000 +#define LOCK_TUNLOCK_SLAVE_GET(x) (((x) & LOCK_TUNLOCK_SLAVE_MASK) >> LOCK_TUNLOCK_SLAVE_LSB) +#define LOCK_TUNLOCK_SLAVE_SET(x) (((x) << LOCK_TUNLOCK_SLAVE_LSB) & LOCK_TUNLOCK_SLAVE_MASK) +#define LOCK_TLOCK_MASTER_MSB 15 +#define LOCK_TLOCK_MASTER_LSB 8 +#define LOCK_TLOCK_MASTER_MASK 0x0000ff00 +#define LOCK_TLOCK_MASTER_GET(x) (((x) & LOCK_TLOCK_MASTER_MASK) >> LOCK_TLOCK_MASTER_LSB) +#define LOCK_TLOCK_MASTER_SET(x) (((x) << LOCK_TLOCK_MASTER_LSB) & LOCK_TLOCK_MASTER_MASK) +#define LOCK_TUNLOCK_MASTER_MSB 7 +#define LOCK_TUNLOCK_MASTER_LSB 0 +#define LOCK_TUNLOCK_MASTER_MASK 0x000000ff +#define LOCK_TUNLOCK_MASTER_GET(x) (((x) & LOCK_TUNLOCK_MASTER_MASK) >> LOCK_TUNLOCK_MASTER_LSB) +#define LOCK_TUNLOCK_MASTER_SET(x) (((x) << LOCK_TUNLOCK_MASTER_LSB) & LOCK_TUNLOCK_MASTER_MASK) + +#define NOLOCK_PRIORITY_ADDRESS 0x00000248 +#define NOLOCK_PRIORITY_OFFSET 0x00000248 +#define NOLOCK_PRIORITY_BITMAP_MSB 31 +#define NOLOCK_PRIORITY_BITMAP_LSB 0 +#define NOLOCK_PRIORITY_BITMAP_MASK 0xffffffff +#define NOLOCK_PRIORITY_BITMAP_GET(x) (((x) & NOLOCK_PRIORITY_BITMAP_MASK) >> NOLOCK_PRIORITY_BITMAP_LSB) +#define NOLOCK_PRIORITY_BITMAP_SET(x) (((x) << NOLOCK_PRIORITY_BITMAP_LSB) & NOLOCK_PRIORITY_BITMAP_MASK) + +#define WBSYNC_ADDRESS 0x0000024c +#define WBSYNC_OFFSET 0x0000024c +#define WBSYNC_BTCLOCK_MSB 31 +#define WBSYNC_BTCLOCK_LSB 0 +#define WBSYNC_BTCLOCK_MASK 0xffffffff +#define WBSYNC_BTCLOCK_GET(x) (((x) & WBSYNC_BTCLOCK_MASK) >> WBSYNC_BTCLOCK_LSB) +#define WBSYNC_BTCLOCK_SET(x) (((x) << WBSYNC_BTCLOCK_LSB) & WBSYNC_BTCLOCK_MASK) + +#define WBSYNC1_ADDRESS 0x00000250 +#define WBSYNC1_OFFSET 0x00000250 +#define WBSYNC1_BTCLOCK_MSB 31 +#define WBSYNC1_BTCLOCK_LSB 0 +#define WBSYNC1_BTCLOCK_MASK 0xffffffff +#define WBSYNC1_BTCLOCK_GET(x) (((x) & WBSYNC1_BTCLOCK_MASK) >> WBSYNC1_BTCLOCK_LSB) +#define WBSYNC1_BTCLOCK_SET(x) (((x) << WBSYNC1_BTCLOCK_LSB) & WBSYNC1_BTCLOCK_MASK) + +#define WBSYNC2_ADDRESS 0x00000254 +#define WBSYNC2_OFFSET 0x00000254 +#define WBSYNC2_BTCLOCK_MSB 31 +#define WBSYNC2_BTCLOCK_LSB 0 +#define WBSYNC2_BTCLOCK_MASK 0xffffffff +#define WBSYNC2_BTCLOCK_GET(x) (((x) & WBSYNC2_BTCLOCK_MASK) >> WBSYNC2_BTCLOCK_LSB) +#define WBSYNC2_BTCLOCK_SET(x) (((x) << WBSYNC2_BTCLOCK_LSB) & WBSYNC2_BTCLOCK_MASK) + +#define WBSYNC3_ADDRESS 0x00000258 +#define WBSYNC3_OFFSET 0x00000258 +#define WBSYNC3_BTCLOCK_MSB 31 +#define WBSYNC3_BTCLOCK_LSB 0 +#define WBSYNC3_BTCLOCK_MASK 0xffffffff +#define WBSYNC3_BTCLOCK_GET(x) (((x) & WBSYNC3_BTCLOCK_MASK) >> WBSYNC3_BTCLOCK_LSB) +#define WBSYNC3_BTCLOCK_SET(x) (((x) << WBSYNC3_BTCLOCK_LSB) & WBSYNC3_BTCLOCK_MASK) + +#define WB_TIMER_TARGET_ADDRESS 0x0000025c +#define WB_TIMER_TARGET_OFFSET 0x0000025c +#define WB_TIMER_TARGET_VALUE_MSB 31 +#define WB_TIMER_TARGET_VALUE_LSB 0 +#define WB_TIMER_TARGET_VALUE_MASK 0xffffffff +#define WB_TIMER_TARGET_VALUE_GET(x) (((x) & WB_TIMER_TARGET_VALUE_MASK) >> WB_TIMER_TARGET_VALUE_LSB) +#define WB_TIMER_TARGET_VALUE_SET(x) (((x) << WB_TIMER_TARGET_VALUE_LSB) & WB_TIMER_TARGET_VALUE_MASK) + +#define WB_TIMER_SLOP_ADDRESS 0x00000260 +#define WB_TIMER_SLOP_OFFSET 0x00000260 +#define WB_TIMER_SLOP_VALUE_MSB 9 +#define WB_TIMER_SLOP_VALUE_LSB 0 +#define WB_TIMER_SLOP_VALUE_MASK 0x000003ff +#define WB_TIMER_SLOP_VALUE_GET(x) (((x) & WB_TIMER_SLOP_VALUE_MASK) >> WB_TIMER_SLOP_VALUE_LSB) +#define WB_TIMER_SLOP_VALUE_SET(x) (((x) << WB_TIMER_SLOP_VALUE_LSB) & WB_TIMER_SLOP_VALUE_MASK) + +#define BTCOEX_INT_EN_ADDRESS 0x00000264 +#define BTCOEX_INT_EN_OFFSET 0x00000264 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MSB 11 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB 11 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK 0x00000800 +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) +#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) +#define BTCOEX_INT_EN_I2C_TX_FAILED_MSB 10 +#define BTCOEX_INT_EN_I2C_TX_FAILED_LSB 10 +#define BTCOEX_INT_EN_I2C_TX_FAILED_MASK 0x00000400 +#define BTCOEX_INT_EN_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) >> BTCOEX_INT_EN_I2C_TX_FAILED_LSB) +#define BTCOEX_INT_EN_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_EN_I2C_TX_FAILED_LSB) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) +#define BTCOEX_INT_EN_I2C_MESG_SENT_MSB 9 +#define BTCOEX_INT_EN_I2C_MESG_SENT_LSB 9 +#define BTCOEX_INT_EN_I2C_MESG_SENT_MASK 0x00000200 +#define BTCOEX_INT_EN_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) >> BTCOEX_INT_EN_I2C_MESG_SENT_LSB) +#define BTCOEX_INT_EN_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_EN_I2C_MESG_SENT_LSB) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) +#define BTCOEX_INT_EN_ST_MESG_RECV_MSB 8 +#define BTCOEX_INT_EN_ST_MESG_RECV_LSB 8 +#define BTCOEX_INT_EN_ST_MESG_RECV_MASK 0x00000100 +#define BTCOEX_INT_EN_ST_MESG_RECV_GET(x) (((x) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) >> BTCOEX_INT_EN_ST_MESG_RECV_LSB) +#define BTCOEX_INT_EN_ST_MESG_RECV_SET(x) (((x) << BTCOEX_INT_EN_ST_MESG_RECV_LSB) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) +#define BTCOEX_INT_EN_WB_TIMER_MSB 7 +#define BTCOEX_INT_EN_WB_TIMER_LSB 7 +#define BTCOEX_INT_EN_WB_TIMER_MASK 0x00000080 +#define BTCOEX_INT_EN_WB_TIMER_GET(x) (((x) & BTCOEX_INT_EN_WB_TIMER_MASK) >> BTCOEX_INT_EN_WB_TIMER_LSB) +#define BTCOEX_INT_EN_WB_TIMER_SET(x) (((x) << BTCOEX_INT_EN_WB_TIMER_LSB) & BTCOEX_INT_EN_WB_TIMER_MASK) +#define BTCOEX_INT_EN_NOSYNC_MSB 4 +#define BTCOEX_INT_EN_NOSYNC_LSB 4 +#define BTCOEX_INT_EN_NOSYNC_MASK 0x00000010 +#define BTCOEX_INT_EN_NOSYNC_GET(x) (((x) & BTCOEX_INT_EN_NOSYNC_MASK) >> BTCOEX_INT_EN_NOSYNC_LSB) +#define BTCOEX_INT_EN_NOSYNC_SET(x) (((x) << BTCOEX_INT_EN_NOSYNC_LSB) & BTCOEX_INT_EN_NOSYNC_MASK) +#define BTCOEX_INT_EN_SYNC_MSB 3 +#define BTCOEX_INT_EN_SYNC_LSB 3 +#define BTCOEX_INT_EN_SYNC_MASK 0x00000008 +#define BTCOEX_INT_EN_SYNC_GET(x) (((x) & BTCOEX_INT_EN_SYNC_MASK) >> BTCOEX_INT_EN_SYNC_LSB) +#define BTCOEX_INT_EN_SYNC_SET(x) (((x) << BTCOEX_INT_EN_SYNC_LSB) & BTCOEX_INT_EN_SYNC_MASK) +#define BTCOEX_INT_EN_END_MSB 2 +#define BTCOEX_INT_EN_END_LSB 2 +#define BTCOEX_INT_EN_END_MASK 0x00000004 +#define BTCOEX_INT_EN_END_GET(x) (((x) & BTCOEX_INT_EN_END_MASK) >> BTCOEX_INT_EN_END_LSB) +#define BTCOEX_INT_EN_END_SET(x) (((x) << BTCOEX_INT_EN_END_LSB) & BTCOEX_INT_EN_END_MASK) +#define BTCOEX_INT_EN_FRAME_CNT_MSB 1 +#define BTCOEX_INT_EN_FRAME_CNT_LSB 1 +#define BTCOEX_INT_EN_FRAME_CNT_MASK 0x00000002 +#define BTCOEX_INT_EN_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_EN_FRAME_CNT_MASK) >> BTCOEX_INT_EN_FRAME_CNT_LSB) +#define BTCOEX_INT_EN_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_EN_FRAME_CNT_LSB) & BTCOEX_INT_EN_FRAME_CNT_MASK) +#define BTCOEX_INT_EN_CLK_CNT_MSB 0 +#define BTCOEX_INT_EN_CLK_CNT_LSB 0 +#define BTCOEX_INT_EN_CLK_CNT_MASK 0x00000001 +#define BTCOEX_INT_EN_CLK_CNT_GET(x) (((x) & BTCOEX_INT_EN_CLK_CNT_MASK) >> BTCOEX_INT_EN_CLK_CNT_LSB) +#define BTCOEX_INT_EN_CLK_CNT_SET(x) (((x) << BTCOEX_INT_EN_CLK_CNT_LSB) & BTCOEX_INT_EN_CLK_CNT_MASK) + +#define BTCOEX_INT_STAT_ADDRESS 0x00000268 +#define BTCOEX_INT_STAT_OFFSET 0x00000268 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MSB 11 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB 11 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK 0x00000800 +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) +#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) +#define BTCOEX_INT_STAT_I2C_TX_FAILED_MSB 10 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_LSB 10 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_MASK 0x00000400 +#define BTCOEX_INT_STAT_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) >> BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) +#define BTCOEX_INT_STAT_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) +#define BTCOEX_INT_STAT_I2C_MESG_SENT_MSB 9 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_LSB 9 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_MASK 0x00000200 +#define BTCOEX_INT_STAT_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) >> BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) +#define BTCOEX_INT_STAT_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) +#define BTCOEX_INT_STAT_I2C_MESG_RECV_MSB 8 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_LSB 8 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_MASK 0x00000100 +#define BTCOEX_INT_STAT_I2C_MESG_RECV_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) >> BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) +#define BTCOEX_INT_STAT_I2C_MESG_RECV_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) +#define BTCOEX_INT_STAT_WB_TIMER_MSB 7 +#define BTCOEX_INT_STAT_WB_TIMER_LSB 7 +#define BTCOEX_INT_STAT_WB_TIMER_MASK 0x00000080 +#define BTCOEX_INT_STAT_WB_TIMER_GET(x) (((x) & BTCOEX_INT_STAT_WB_TIMER_MASK) >> BTCOEX_INT_STAT_WB_TIMER_LSB) +#define BTCOEX_INT_STAT_WB_TIMER_SET(x) (((x) << BTCOEX_INT_STAT_WB_TIMER_LSB) & BTCOEX_INT_STAT_WB_TIMER_MASK) +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MSB 6 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB 6 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK 0x00000040 +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) +#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) +#define BTCOEX_INT_STAT_BTPRIORITY_MSB 5 +#define BTCOEX_INT_STAT_BTPRIORITY_LSB 5 +#define BTCOEX_INT_STAT_BTPRIORITY_MASK 0x00000020 +#define BTCOEX_INT_STAT_BTPRIORITY_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_LSB) +#define BTCOEX_INT_STAT_BTPRIORITY_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_LSB) & BTCOEX_INT_STAT_BTPRIORITY_MASK) +#define BTCOEX_INT_STAT_NOSYNC_MSB 4 +#define BTCOEX_INT_STAT_NOSYNC_LSB 4 +#define BTCOEX_INT_STAT_NOSYNC_MASK 0x00000010 +#define BTCOEX_INT_STAT_NOSYNC_GET(x) (((x) & BTCOEX_INT_STAT_NOSYNC_MASK) >> BTCOEX_INT_STAT_NOSYNC_LSB) +#define BTCOEX_INT_STAT_NOSYNC_SET(x) (((x) << BTCOEX_INT_STAT_NOSYNC_LSB) & BTCOEX_INT_STAT_NOSYNC_MASK) +#define BTCOEX_INT_STAT_SYNC_MSB 3 +#define BTCOEX_INT_STAT_SYNC_LSB 3 +#define BTCOEX_INT_STAT_SYNC_MASK 0x00000008 +#define BTCOEX_INT_STAT_SYNC_GET(x) (((x) & BTCOEX_INT_STAT_SYNC_MASK) >> BTCOEX_INT_STAT_SYNC_LSB) +#define BTCOEX_INT_STAT_SYNC_SET(x) (((x) << BTCOEX_INT_STAT_SYNC_LSB) & BTCOEX_INT_STAT_SYNC_MASK) +#define BTCOEX_INT_STAT_END_MSB 2 +#define BTCOEX_INT_STAT_END_LSB 2 +#define BTCOEX_INT_STAT_END_MASK 0x00000004 +#define BTCOEX_INT_STAT_END_GET(x) (((x) & BTCOEX_INT_STAT_END_MASK) >> BTCOEX_INT_STAT_END_LSB) +#define BTCOEX_INT_STAT_END_SET(x) (((x) << BTCOEX_INT_STAT_END_LSB) & BTCOEX_INT_STAT_END_MASK) +#define BTCOEX_INT_STAT_FRAME_CNT_MSB 1 +#define BTCOEX_INT_STAT_FRAME_CNT_LSB 1 +#define BTCOEX_INT_STAT_FRAME_CNT_MASK 0x00000002 +#define BTCOEX_INT_STAT_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_STAT_FRAME_CNT_MASK) >> BTCOEX_INT_STAT_FRAME_CNT_LSB) +#define BTCOEX_INT_STAT_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_STAT_FRAME_CNT_LSB) & BTCOEX_INT_STAT_FRAME_CNT_MASK) +#define BTCOEX_INT_STAT_CLK_CNT_MSB 0 +#define BTCOEX_INT_STAT_CLK_CNT_LSB 0 +#define BTCOEX_INT_STAT_CLK_CNT_MASK 0x00000001 +#define BTCOEX_INT_STAT_CLK_CNT_GET(x) (((x) & BTCOEX_INT_STAT_CLK_CNT_MASK) >> BTCOEX_INT_STAT_CLK_CNT_LSB) +#define BTCOEX_INT_STAT_CLK_CNT_SET(x) (((x) << BTCOEX_INT_STAT_CLK_CNT_LSB) & BTCOEX_INT_STAT_CLK_CNT_MASK) + +#define BTPRIORITY_INT_EN_ADDRESS 0x0000026c +#define BTPRIORITY_INT_EN_OFFSET 0x0000026c +#define BTPRIORITY_INT_EN_BITMAP_MSB 31 +#define BTPRIORITY_INT_EN_BITMAP_LSB 0 +#define BTPRIORITY_INT_EN_BITMAP_MASK 0xffffffff +#define BTPRIORITY_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_INT_EN_BITMAP_MASK) >> BTPRIORITY_INT_EN_BITMAP_LSB) +#define BTPRIORITY_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_INT_EN_BITMAP_LSB) & BTPRIORITY_INT_EN_BITMAP_MASK) + +#define BTPRIORITY_INT_STAT_ADDRESS 0x00000270 +#define BTPRIORITY_INT_STAT_OFFSET 0x00000270 +#define BTPRIORITY_INT_STAT_BITMAP_MSB 31 +#define BTPRIORITY_INT_STAT_BITMAP_LSB 0 +#define BTPRIORITY_INT_STAT_BITMAP_MASK 0xffffffff +#define BTPRIORITY_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_INT_STAT_BITMAP_MASK) >> BTPRIORITY_INT_STAT_BITMAP_LSB) +#define BTPRIORITY_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_INT_STAT_BITMAP_LSB) & BTPRIORITY_INT_STAT_BITMAP_MASK) + +#define BTPRIORITY_STOMP_INT_EN_ADDRESS 0x00000274 +#define BTPRIORITY_STOMP_INT_EN_OFFSET 0x00000274 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_MSB 31 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_LSB 0 +#define BTPRIORITY_STOMP_INT_EN_BITMAP_MASK 0xffffffff +#define BTPRIORITY_STOMP_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) +#define BTPRIORITY_STOMP_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) + +#define BTPRIORITY_STOMP_INT_STAT_ADDRESS 0x00000278 +#define BTPRIORITY_STOMP_INT_STAT_OFFSET 0x00000278 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MSB 31 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB 0 +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK 0xffffffff +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) +#define BTPRIORITY_STOMP_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) + +#define MAC_PCU_BMISS_TIMEOUT_ADDRESS 0x0000027c +#define MAC_PCU_BMISS_TIMEOUT_OFFSET 0x0000027c +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MSB 24 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB 24 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) +#define MAC_PCU_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) +#define MAC_PCU_BMISS_TIMEOUT_VALUE_MSB 23 +#define MAC_PCU_BMISS_TIMEOUT_VALUE_LSB 0 +#define MAC_PCU_BMISS_TIMEOUT_VALUE_MASK 0x00ffffff +#define MAC_PCU_BMISS_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) >> MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) +#define MAC_PCU_BMISS_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) + +#define MAC_PCU_CAB_AWAKE_ADDRESS 0x00000280 +#define MAC_PCU_CAB_AWAKE_OFFSET 0x00000280 +#define MAC_PCU_CAB_AWAKE_ENABLE_MSB 16 +#define MAC_PCU_CAB_AWAKE_ENABLE_LSB 16 +#define MAC_PCU_CAB_AWAKE_ENABLE_MASK 0x00010000 +#define MAC_PCU_CAB_AWAKE_ENABLE_GET(x) (((x) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) >> MAC_PCU_CAB_AWAKE_ENABLE_LSB) +#define MAC_PCU_CAB_AWAKE_ENABLE_SET(x) (((x) << MAC_PCU_CAB_AWAKE_ENABLE_LSB) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) +#define MAC_PCU_CAB_AWAKE_DURATION_MSB 15 +#define MAC_PCU_CAB_AWAKE_DURATION_LSB 0 +#define MAC_PCU_CAB_AWAKE_DURATION_MASK 0x0000ffff +#define MAC_PCU_CAB_AWAKE_DURATION_GET(x) (((x) & MAC_PCU_CAB_AWAKE_DURATION_MASK) >> MAC_PCU_CAB_AWAKE_DURATION_LSB) +#define MAC_PCU_CAB_AWAKE_DURATION_SET(x) (((x) << MAC_PCU_CAB_AWAKE_DURATION_LSB) & MAC_PCU_CAB_AWAKE_DURATION_MASK) + +#define LP_PERF_COUNTER_ADDRESS 0x00000284 +#define LP_PERF_COUNTER_OFFSET 0x00000284 +#define LP_PERF_COUNTER_EN_MSB 0 +#define LP_PERF_COUNTER_EN_LSB 0 +#define LP_PERF_COUNTER_EN_MASK 0x00000001 +#define LP_PERF_COUNTER_EN_GET(x) (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB) +#define LP_PERF_COUNTER_EN_SET(x) (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK) + +#define LP_PERF_LIGHT_SLEEP_ADDRESS 0x00000288 +#define LP_PERF_LIGHT_SLEEP_OFFSET 0x00000288 +#define LP_PERF_LIGHT_SLEEP_CNT_MSB 31 +#define LP_PERF_LIGHT_SLEEP_CNT_LSB 0 +#define LP_PERF_LIGHT_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_LIGHT_SLEEP_CNT_GET(x) (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB) +#define LP_PERF_LIGHT_SLEEP_CNT_SET(x) (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK) + +#define LP_PERF_DEEP_SLEEP_ADDRESS 0x0000028c +#define LP_PERF_DEEP_SLEEP_OFFSET 0x0000028c +#define LP_PERF_DEEP_SLEEP_CNT_MSB 31 +#define LP_PERF_DEEP_SLEEP_CNT_LSB 0 +#define LP_PERF_DEEP_SLEEP_CNT_MASK 0xffffffff +#define LP_PERF_DEEP_SLEEP_CNT_GET(x) (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB) +#define LP_PERF_DEEP_SLEEP_CNT_SET(x) (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK) + +#define LP_PERF_ON_ADDRESS 0x00000290 +#define LP_PERF_ON_OFFSET 0x00000290 +#define LP_PERF_ON_CNT_MSB 31 +#define LP_PERF_ON_CNT_LSB 0 +#define LP_PERF_ON_CNT_MASK 0xffffffff +#define LP_PERF_ON_CNT_GET(x) (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB) +#define LP_PERF_ON_CNT_SET(x) (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK) + +#define ST_64_BIT_ADDRESS 0x00000294 +#define ST_64_BIT_OFFSET 0x00000294 +#define ST_64_BIT_TIMEOUT_MSB 26 +#define ST_64_BIT_TIMEOUT_LSB 9 +#define ST_64_BIT_TIMEOUT_MASK 0x07fffe00 +#define ST_64_BIT_TIMEOUT_GET(x) (((x) & ST_64_BIT_TIMEOUT_MASK) >> ST_64_BIT_TIMEOUT_LSB) +#define ST_64_BIT_TIMEOUT_SET(x) (((x) << ST_64_BIT_TIMEOUT_LSB) & ST_64_BIT_TIMEOUT_MASK) +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MSB 8 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB 8 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK 0x00000100 +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_GET(x) (((x) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) >> ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) +#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_SET(x) (((x) << ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) +#define ST_64_BIT_DRIVE_MODE_MSB 7 +#define ST_64_BIT_DRIVE_MODE_LSB 7 +#define ST_64_BIT_DRIVE_MODE_MASK 0x00000080 +#define ST_64_BIT_DRIVE_MODE_GET(x) (((x) & ST_64_BIT_DRIVE_MODE_MASK) >> ST_64_BIT_DRIVE_MODE_LSB) +#define ST_64_BIT_DRIVE_MODE_SET(x) (((x) << ST_64_BIT_DRIVE_MODE_LSB) & ST_64_BIT_DRIVE_MODE_MASK) +#define ST_64_BIT_CLOCK_GATE_MSB 6 +#define ST_64_BIT_CLOCK_GATE_LSB 6 +#define ST_64_BIT_CLOCK_GATE_MASK 0x00000040 +#define ST_64_BIT_CLOCK_GATE_GET(x) (((x) & ST_64_BIT_CLOCK_GATE_MASK) >> ST_64_BIT_CLOCK_GATE_LSB) +#define ST_64_BIT_CLOCK_GATE_SET(x) (((x) << ST_64_BIT_CLOCK_GATE_LSB) & ST_64_BIT_CLOCK_GATE_MASK) +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MSB 5 +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB 1 +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK 0x0000003e +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_GET(x) (((x) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) >> ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) +#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_SET(x) (((x) << ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) +#define ST_64_BIT_MODE_MSB 0 +#define ST_64_BIT_MODE_LSB 0 +#define ST_64_BIT_MODE_MASK 0x00000001 +#define ST_64_BIT_MODE_GET(x) (((x) & ST_64_BIT_MODE_MASK) >> ST_64_BIT_MODE_LSB) +#define ST_64_BIT_MODE_SET(x) (((x) << ST_64_BIT_MODE_LSB) & ST_64_BIT_MODE_MASK) + +#define MESSAGE_WR_ADDRESS 0x00000298 +#define MESSAGE_WR_OFFSET 0x00000298 +#define MESSAGE_WR_TYPE_MSB 31 +#define MESSAGE_WR_TYPE_LSB 0 +#define MESSAGE_WR_TYPE_MASK 0xffffffff +#define MESSAGE_WR_TYPE_GET(x) (((x) & MESSAGE_WR_TYPE_MASK) >> MESSAGE_WR_TYPE_LSB) +#define MESSAGE_WR_TYPE_SET(x) (((x) << MESSAGE_WR_TYPE_LSB) & MESSAGE_WR_TYPE_MASK) + +#define MESSAGE_WR_P_ADDRESS 0x0000029c +#define MESSAGE_WR_P_OFFSET 0x0000029c +#define MESSAGE_WR_P_PARAMETER_MSB 31 +#define MESSAGE_WR_P_PARAMETER_LSB 0 +#define MESSAGE_WR_P_PARAMETER_MASK 0xffffffff +#define MESSAGE_WR_P_PARAMETER_GET(x) (((x) & MESSAGE_WR_P_PARAMETER_MASK) >> MESSAGE_WR_P_PARAMETER_LSB) +#define MESSAGE_WR_P_PARAMETER_SET(x) (((x) << MESSAGE_WR_P_PARAMETER_LSB) & MESSAGE_WR_P_PARAMETER_MASK) + +#define MESSAGE_RD_ADDRESS 0x000002a0 +#define MESSAGE_RD_OFFSET 0x000002a0 +#define MESSAGE_RD_TYPE_MSB 31 +#define MESSAGE_RD_TYPE_LSB 0 +#define MESSAGE_RD_TYPE_MASK 0xffffffff +#define MESSAGE_RD_TYPE_GET(x) (((x) & MESSAGE_RD_TYPE_MASK) >> MESSAGE_RD_TYPE_LSB) +#define MESSAGE_RD_TYPE_SET(x) (((x) << MESSAGE_RD_TYPE_LSB) & MESSAGE_RD_TYPE_MASK) + +#define MESSAGE_RD_P_ADDRESS 0x000002a4 +#define MESSAGE_RD_P_OFFSET 0x000002a4 +#define MESSAGE_RD_P_PARAMETER_MSB 31 +#define MESSAGE_RD_P_PARAMETER_LSB 0 +#define MESSAGE_RD_P_PARAMETER_MASK 0xffffffff +#define MESSAGE_RD_P_PARAMETER_GET(x) (((x) & MESSAGE_RD_P_PARAMETER_MASK) >> MESSAGE_RD_P_PARAMETER_LSB) +#define MESSAGE_RD_P_PARAMETER_SET(x) (((x) << MESSAGE_RD_P_PARAMETER_LSB) & MESSAGE_RD_P_PARAMETER_MASK) + +#define CHIP_MODE_ADDRESS 0x000002a8 +#define CHIP_MODE_OFFSET 0x000002a8 +#define CHIP_MODE_BIT_MSB 1 +#define CHIP_MODE_BIT_LSB 0 +#define CHIP_MODE_BIT_MASK 0x00000003 +#define CHIP_MODE_BIT_GET(x) (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB) +#define CHIP_MODE_BIT_SET(x) (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK) + +#define CLK_REQ_FALL_EDGE_ADDRESS 0x000002ac +#define CLK_REQ_FALL_EDGE_OFFSET 0x000002ac +#define CLK_REQ_FALL_EDGE_EN_MSB 31 +#define CLK_REQ_FALL_EDGE_EN_LSB 31 +#define CLK_REQ_FALL_EDGE_EN_MASK 0x80000000 +#define CLK_REQ_FALL_EDGE_EN_GET(x) (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB) +#define CLK_REQ_FALL_EDGE_EN_SET(x) (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK) +#define CLK_REQ_FALL_EDGE_DELAY_MSB 7 +#define CLK_REQ_FALL_EDGE_DELAY_LSB 0 +#define CLK_REQ_FALL_EDGE_DELAY_MASK 0x000000ff +#define CLK_REQ_FALL_EDGE_DELAY_GET(x) (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB) +#define CLK_REQ_FALL_EDGE_DELAY_SET(x) (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK) + +#define OTP_ADDRESS 0x000002b0 +#define OTP_OFFSET 0x000002b0 +#define OTP_LDO25_EN_MSB 1 +#define OTP_LDO25_EN_LSB 1 +#define OTP_LDO25_EN_MASK 0x00000002 +#define OTP_LDO25_EN_GET(x) (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB) +#define OTP_LDO25_EN_SET(x) (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK) +#define OTP_VDD12_EN_MSB 0 +#define OTP_VDD12_EN_LSB 0 +#define OTP_VDD12_EN_MASK 0x00000001 +#define OTP_VDD12_EN_GET(x) (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB) +#define OTP_VDD12_EN_SET(x) (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK) + +#define OTP_STATUS_ADDRESS 0x000002b4 +#define OTP_STATUS_OFFSET 0x000002b4 +#define OTP_STATUS_LDO25_EN_READY_MSB 1 +#define OTP_STATUS_LDO25_EN_READY_LSB 1 +#define OTP_STATUS_LDO25_EN_READY_MASK 0x00000002 +#define OTP_STATUS_LDO25_EN_READY_GET(x) (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB) +#define OTP_STATUS_LDO25_EN_READY_SET(x) (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK) +#define OTP_STATUS_VDD12_EN_READY_MSB 0 +#define OTP_STATUS_VDD12_EN_READY_LSB 0 +#define OTP_STATUS_VDD12_EN_READY_MASK 0x00000001 +#define OTP_STATUS_VDD12_EN_READY_GET(x) (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB) +#define OTP_STATUS_VDD12_EN_READY_SET(x) (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK) + +#define PMU_ADDRESS 0x000002b8 +#define PMU_OFFSET 0x000002b8 +#define PMU_REG_WAKEUP_TIME_SEL_MSB 1 +#define PMU_REG_WAKEUP_TIME_SEL_LSB 0 +#define PMU_REG_WAKEUP_TIME_SEL_MASK 0x00000003 +#define PMU_REG_WAKEUP_TIME_SEL_GET(x) (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB) +#define PMU_REG_WAKEUP_TIME_SEL_SET(x) (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK) + +#define PMU_CONFIG_ADDRESS 0x000002c0 +#define PMU_CONFIG_OFFSET 0x000002c0 +#define PMU_CONFIG_VALUE_MSB 15 +#define PMU_CONFIG_VALUE_LSB 0 +#define PMU_CONFIG_VALUE_MASK 0x0000ffff +#define PMU_CONFIG_VALUE_GET(x) (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB) +#define PMU_CONFIG_VALUE_SET(x) (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK) + +#define PMU_BYPASS_ADDRESS 0x000002c8 +#define PMU_BYPASS_OFFSET 0x000002c8 +#define PMU_BYPASS_SWREG_MSB 2 +#define PMU_BYPASS_SWREG_LSB 2 +#define PMU_BYPASS_SWREG_MASK 0x00000004 +#define PMU_BYPASS_SWREG_GET(x) (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB) +#define PMU_BYPASS_SWREG_SET(x) (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK) +#define PMU_BYPASS_DREG_MSB 1 +#define PMU_BYPASS_DREG_LSB 1 +#define PMU_BYPASS_DREG_MASK 0x00000002 +#define PMU_BYPASS_DREG_GET(x) (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB) +#define PMU_BYPASS_DREG_SET(x) (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK) +#define PMU_BYPASS_PAREG_MSB 0 +#define PMU_BYPASS_PAREG_LSB 0 +#define PMU_BYPASS_PAREG_MASK 0x00000001 +#define PMU_BYPASS_PAREG_GET(x) (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB) +#define PMU_BYPASS_PAREG_SET(x) (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK) + +#define MAC_PCU_TSF2_L32_ADDRESS 0x000002cc +#define MAC_PCU_TSF2_L32_OFFSET 0x000002cc +#define MAC_PCU_TSF2_L32_VALUE_MSB 31 +#define MAC_PCU_TSF2_L32_VALUE_LSB 0 +#define MAC_PCU_TSF2_L32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_L32_VALUE_MASK) >> MAC_PCU_TSF2_L32_VALUE_LSB) +#define MAC_PCU_TSF2_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_L32_VALUE_LSB) & MAC_PCU_TSF2_L32_VALUE_MASK) + +#define MAC_PCU_TSF2_U32_ADDRESS 0x000002d0 +#define MAC_PCU_TSF2_U32_OFFSET 0x000002d0 +#define MAC_PCU_TSF2_U32_VALUE_MSB 31 +#define MAC_PCU_TSF2_U32_VALUE_LSB 0 +#define MAC_PCU_TSF2_U32_VALUE_MASK 0xffffffff +#define MAC_PCU_TSF2_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_U32_VALUE_MASK) >> MAC_PCU_TSF2_U32_VALUE_LSB) +#define MAC_PCU_TSF2_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_U32_VALUE_LSB) & MAC_PCU_TSF2_U32_VALUE_MASK) + +#define MAC_PCU_GENERIC_TIMERS_MODE3_ADDRESS 0x000002d4 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OFFSET 0x000002d4 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MSB 27 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB 24 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK 0x0f000000 +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MSB 19 +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB 0 +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK 0x000fffff +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) +#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) + +#define MAC_PCU_DIRECT_CONNECT_ADDRESS 0x000002d8 +#define MAC_PCU_DIRECT_CONNECT_OFFSET 0x000002d8 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MSB 2 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB 2 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK 0x00000004 +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) +#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MSB 1 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB 1 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK 0x00000002 +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) +#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MSB 0 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB 0 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK 0x00000001 +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) +#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) + +#define THERM_CTRL1_ADDRESS 0x000002dc +#define THERM_CTRL1_OFFSET 0x000002dc +#define THERM_CTRL1_BYPASS_MSB 16 +#define THERM_CTRL1_BYPASS_LSB 16 +#define THERM_CTRL1_BYPASS_MASK 0x00010000 +#define THERM_CTRL1_BYPASS_GET(x) (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB) +#define THERM_CTRL1_BYPASS_SET(x) (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK) +#define THERM_CTRL1_WIDTH_ARBITOR_MSB 15 +#define THERM_CTRL1_WIDTH_ARBITOR_LSB 12 +#define THERM_CTRL1_WIDTH_ARBITOR_MASK 0x0000f000 +#define THERM_CTRL1_WIDTH_ARBITOR_GET(x) (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB) +#define THERM_CTRL1_WIDTH_ARBITOR_SET(x) (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK) +#define THERM_CTRL1_WIDTH_MSB 11 +#define THERM_CTRL1_WIDTH_LSB 5 +#define THERM_CTRL1_WIDTH_MASK 0x00000fe0 +#define THERM_CTRL1_WIDTH_GET(x) (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB) +#define THERM_CTRL1_WIDTH_SET(x) (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK) +#define THERM_CTRL1_TYPE_MSB 4 +#define THERM_CTRL1_TYPE_LSB 3 +#define THERM_CTRL1_TYPE_MASK 0x00000018 +#define THERM_CTRL1_TYPE_GET(x) (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB) +#define THERM_CTRL1_TYPE_SET(x) (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK) +#define THERM_CTRL1_MEASURE_MSB 2 +#define THERM_CTRL1_MEASURE_LSB 2 +#define THERM_CTRL1_MEASURE_MASK 0x00000004 +#define THERM_CTRL1_MEASURE_GET(x) (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB) +#define THERM_CTRL1_MEASURE_SET(x) (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK) +#define THERM_CTRL1_INT_EN_MSB 1 +#define THERM_CTRL1_INT_EN_LSB 1 +#define THERM_CTRL1_INT_EN_MASK 0x00000002 +#define THERM_CTRL1_INT_EN_GET(x) (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB) +#define THERM_CTRL1_INT_EN_SET(x) (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK) +#define THERM_CTRL1_INT_STATUS_MSB 0 +#define THERM_CTRL1_INT_STATUS_LSB 0 +#define THERM_CTRL1_INT_STATUS_MASK 0x00000001 +#define THERM_CTRL1_INT_STATUS_GET(x) (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB) +#define THERM_CTRL1_INT_STATUS_SET(x) (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK) + +#define THERM_CTRL2_ADDRESS 0x000002e0 +#define THERM_CTRL2_OFFSET 0x000002e0 +#define THERM_CTRL2_ADC_OFF_MSB 25 +#define THERM_CTRL2_ADC_OFF_LSB 25 +#define THERM_CTRL2_ADC_OFF_MASK 0x02000000 +#define THERM_CTRL2_ADC_OFF_GET(x) (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB) +#define THERM_CTRL2_ADC_OFF_SET(x) (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK) +#define THERM_CTRL2_ADC_ON_MSB 24 +#define THERM_CTRL2_ADC_ON_LSB 24 +#define THERM_CTRL2_ADC_ON_MASK 0x01000000 +#define THERM_CTRL2_ADC_ON_GET(x) (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB) +#define THERM_CTRL2_ADC_ON_SET(x) (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK) +#define THERM_CTRL2_SAMPLE_MSB 23 +#define THERM_CTRL2_SAMPLE_LSB 16 +#define THERM_CTRL2_SAMPLE_MASK 0x00ff0000 +#define THERM_CTRL2_SAMPLE_GET(x) (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB) +#define THERM_CTRL2_SAMPLE_SET(x) (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK) +#define THERM_CTRL2_HIGH_MSB 15 +#define THERM_CTRL2_HIGH_LSB 8 +#define THERM_CTRL2_HIGH_MASK 0x0000ff00 +#define THERM_CTRL2_HIGH_GET(x) (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB) +#define THERM_CTRL2_HIGH_SET(x) (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK) +#define THERM_CTRL2_LOW_MSB 7 +#define THERM_CTRL2_LOW_LSB 0 +#define THERM_CTRL2_LOW_MASK 0x000000ff +#define THERM_CTRL2_LOW_GET(x) (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB) +#define THERM_CTRL2_LOW_SET(x) (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK) + +#define THERM_CTRL3_ADDRESS 0x000002e4 +#define THERM_CTRL3_OFFSET 0x000002e4 +#define THERM_CTRL3_ADC_GAIN_MSB 16 +#define THERM_CTRL3_ADC_GAIN_LSB 8 +#define THERM_CTRL3_ADC_GAIN_MASK 0x0001ff00 +#define THERM_CTRL3_ADC_GAIN_GET(x) (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB) +#define THERM_CTRL3_ADC_GAIN_SET(x) (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK) +#define THERM_CTRL3_ADC_OFFSET_MSB 7 +#define THERM_CTRL3_ADC_OFFSET_LSB 0 +#define THERM_CTRL3_ADC_OFFSET_MASK 0x000000ff +#define THERM_CTRL3_ADC_OFFSET_GET(x) (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB) +#define THERM_CTRL3_ADC_OFFSET_SET(x) (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct rtc_wlan_reg_reg_s { + volatile unsigned int wlan_reset_control; + volatile unsigned int wlan_xtal_control; + volatile unsigned int wlan_tcxo_detect; + volatile unsigned int wlan_xtal_test; + volatile unsigned int wlan_quadrature; + volatile unsigned int wlan_pll_control; + volatile unsigned int wlan_pll_settle; + volatile unsigned int wlan_xtal_settle; + volatile unsigned int wlan_cpu_clock; + volatile unsigned int wlan_clock_out; + volatile unsigned int wlan_clock_control; + volatile unsigned int wlan_bias_override; + volatile unsigned int wlan_wdt_control; + volatile unsigned int wlan_wdt_status; + volatile unsigned int wlan_wdt; + volatile unsigned int wlan_wdt_count; + volatile unsigned int wlan_wdt_reset; + volatile unsigned int wlan_int_status; + volatile unsigned int wlan_lf_timer0; + volatile unsigned int wlan_lf_timer_count0; + volatile unsigned int wlan_lf_timer_control0; + volatile unsigned int wlan_lf_timer_status0; + volatile unsigned int wlan_lf_timer1; + volatile unsigned int wlan_lf_timer_count1; + volatile unsigned int wlan_lf_timer_control1; + volatile unsigned int wlan_lf_timer_status1; + volatile unsigned int wlan_lf_timer2; + volatile unsigned int wlan_lf_timer_count2; + volatile unsigned int wlan_lf_timer_control2; + volatile unsigned int wlan_lf_timer_status2; + volatile unsigned int wlan_lf_timer3; + volatile unsigned int wlan_lf_timer_count3; + volatile unsigned int wlan_lf_timer_control3; + volatile unsigned int wlan_lf_timer_status3; + volatile unsigned int wlan_hf_timer; + volatile unsigned int wlan_hf_timer_count; + volatile unsigned int wlan_hf_lf_count; + volatile unsigned int wlan_hf_timer_control; + volatile unsigned int wlan_hf_timer_status; + volatile unsigned int wlan_rtc_control; + volatile unsigned int wlan_rtc_time; + volatile unsigned int wlan_rtc_date; + volatile unsigned int wlan_rtc_set_time; + volatile unsigned int wlan_rtc_set_date; + volatile unsigned int wlan_rtc_set_alarm; + volatile unsigned int wlan_rtc_config; + volatile unsigned int wlan_rtc_alarm_status; + volatile unsigned int wlan_uart_wakeup; + volatile unsigned int wlan_reset_cause; + volatile unsigned int wlan_system_sleep; + volatile unsigned int wlan_sdio_wrapper; + volatile unsigned int wlan_mac_sleep_control; + volatile unsigned int wlan_keep_awake; + volatile unsigned int wlan_lpo_cal_time; + volatile unsigned int wlan_lpo_init_dividend_int; + volatile unsigned int wlan_lpo_init_dividend_fraction; + volatile unsigned int wlan_lpo_cal; + volatile unsigned int wlan_lpo_cal_test_control; + volatile unsigned int wlan_lpo_cal_test_status; + volatile unsigned int wlan_chip_id; + volatile unsigned int wlan_derived_rtc_clk; + volatile unsigned int mac_pcu_slp32_mode; + volatile unsigned int mac_pcu_slp32_wake; + volatile unsigned int mac_pcu_slp32_inc; + volatile unsigned int mac_pcu_slp_mib1; + volatile unsigned int mac_pcu_slp_mib2; + volatile unsigned int mac_pcu_slp_mib3; + volatile unsigned int wlan_power_reg; + volatile unsigned int wlan_core_clk_ctrl; + volatile unsigned int wlan_gpio_wakeup_control; + volatile unsigned int ht; + volatile unsigned int mac_pcu_tsf_l32; + volatile unsigned int mac_pcu_tsf_u32; + volatile unsigned int mac_pcu_wbtimer; + unsigned char pad0[24]; /* pad to 0x140 */ + volatile unsigned int mac_pcu_generic_timers[16]; + volatile unsigned int mac_pcu_generic_timers_mode; + unsigned char pad1[60]; /* pad to 0x1c0 */ + volatile unsigned int mac_pcu_generic_timers2[16]; + volatile unsigned int mac_pcu_generic_timers_mode2; + volatile unsigned int mac_pcu_slp1; + volatile unsigned int mac_pcu_slp2; + volatile unsigned int mac_pcu_reset_tsf; + volatile unsigned int mac_pcu_tsf_add_pll; + volatile unsigned int sleep_retention; + volatile unsigned int btcoexctrl; + volatile unsigned int wbsync_priority1; + volatile unsigned int wbsync_priority2; + volatile unsigned int wbsync_priority3; + volatile unsigned int btcoex0; + volatile unsigned int btcoex1; + volatile unsigned int btcoex2; + volatile unsigned int btcoex3; + volatile unsigned int btcoex4; + volatile unsigned int btcoex5; + volatile unsigned int btcoex6; + volatile unsigned int lock; + volatile unsigned int nolock_priority; + volatile unsigned int wbsync; + volatile unsigned int wbsync1; + volatile unsigned int wbsync2; + volatile unsigned int wbsync3; + volatile unsigned int wb_timer_target; + volatile unsigned int wb_timer_slop; + volatile unsigned int btcoex_int_en; + volatile unsigned int btcoex_int_stat; + volatile unsigned int btpriority_int_en; + volatile unsigned int btpriority_int_stat; + volatile unsigned int btpriority_stomp_int_en; + volatile unsigned int btpriority_stomp_int_stat; + volatile unsigned int mac_pcu_bmiss_timeout; + volatile unsigned int mac_pcu_cab_awake; + volatile unsigned int lp_perf_counter; + volatile unsigned int lp_perf_light_sleep; + volatile unsigned int lp_perf_deep_sleep; + volatile unsigned int lp_perf_on; + volatile unsigned int st_64_bit; + volatile unsigned int message_wr; + volatile unsigned int message_wr_p; + volatile unsigned int message_rd; + volatile unsigned int message_rd_p; + volatile unsigned int chip_mode; + volatile unsigned int clk_req_fall_edge; + volatile unsigned int otp; + volatile unsigned int otp_status; + volatile unsigned int pmu; + unsigned char pad2[4]; /* pad to 0x2c0 */ + volatile unsigned int pmu_config[2]; + volatile unsigned int pmu_bypass; + volatile unsigned int mac_pcu_tsf2_l32; + volatile unsigned int mac_pcu_tsf2_u32; + volatile unsigned int mac_pcu_generic_timers_mode3; + volatile unsigned int mac_pcu_direct_connect; + volatile unsigned int therm_ctrl1; + volatile unsigned int therm_ctrl2; + volatile unsigned int therm_ctrl3; +} rtc_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _RTC_WLAN_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h new file mode 100644 index 000000000000..44d24661761e --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/si_reg.h @@ -0,0 +1,205 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _SI_REG_REG_H_ +#define _SI_REG_REG_H_ + +#define SI_CONFIG_ADDRESS 0x00000000 +#define SI_CONFIG_OFFSET 0x00000000 +#define SI_CONFIG_ERR_INT_MSB 19 +#define SI_CONFIG_ERR_INT_LSB 19 +#define SI_CONFIG_ERR_INT_MASK 0x00080000 +#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB) +#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_MSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 +#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 +#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_MSB 16 +#define SI_CONFIG_I2C_LSB 16 +#define SI_CONFIG_I2C_MASK 0x00010000 +#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_MSB 7 +#define SI_CONFIG_POS_SAMPLE_LSB 7 +#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 +#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_POS_DRIVE_MSB 6 +#define SI_CONFIG_POS_DRIVE_LSB 6 +#define SI_CONFIG_POS_DRIVE_MASK 0x00000040 +#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB) +#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK) +#define SI_CONFIG_INACTIVE_DATA_MSB 5 +#define SI_CONFIG_INACTIVE_DATA_LSB 5 +#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 +#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_INACTIVE_CLK_MSB 4 +#define SI_CONFIG_INACTIVE_CLK_LSB 4 +#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 +#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_DIVIDER_MSB 3 +#define SI_CONFIG_DIVIDER_LSB 0 +#define SI_CONFIG_DIVIDER_MASK 0x0000000f +#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) + +#define SI_CS_ADDRESS 0x00000004 +#define SI_CS_OFFSET 0x00000004 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800 +#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) +#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) +#define SI_CS_DONE_ERR_MSB 10 +#define SI_CS_DONE_ERR_LSB 10 +#define SI_CS_DONE_ERR_MASK 0x00000400 +#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB) +#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MSB 9 +#define SI_CS_DONE_INT_LSB 9 +#define SI_CS_DONE_INT_MASK 0x00000200 +#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB) +#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK) +#define SI_CS_START_MSB 8 +#define SI_CS_START_LSB 8 +#define SI_CS_START_MASK 0x00000100 +#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_MSB 7 +#define SI_CS_RX_CNT_LSB 4 +#define SI_CS_RX_CNT_MASK 0x000000f0 +#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_MSB 3 +#define SI_CS_TX_CNT_LSB 0 +#define SI_CS_TX_CNT_MASK 0x0000000f +#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#define SI_TX_DATA0_ADDRESS 0x00000008 +#define SI_TX_DATA0_OFFSET 0x00000008 +#define SI_TX_DATA0_DATA3_MSB 31 +#define SI_TX_DATA0_DATA3_LSB 24 +#define SI_TX_DATA0_DATA3_MASK 0xff000000 +#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB) +#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK) +#define SI_TX_DATA0_DATA2_MSB 23 +#define SI_TX_DATA0_DATA2_LSB 16 +#define SI_TX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB) +#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK) +#define SI_TX_DATA0_DATA1_MSB 15 +#define SI_TX_DATA0_DATA1_LSB 8 +#define SI_TX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB) +#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK) +#define SI_TX_DATA0_DATA0_MSB 7 +#define SI_TX_DATA0_DATA0_LSB 0 +#define SI_TX_DATA0_DATA0_MASK 0x000000ff +#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB) +#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK) + +#define SI_TX_DATA1_ADDRESS 0x0000000c +#define SI_TX_DATA1_OFFSET 0x0000000c +#define SI_TX_DATA1_DATA7_MSB 31 +#define SI_TX_DATA1_DATA7_LSB 24 +#define SI_TX_DATA1_DATA7_MASK 0xff000000 +#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB) +#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK) +#define SI_TX_DATA1_DATA6_MSB 23 +#define SI_TX_DATA1_DATA6_LSB 16 +#define SI_TX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB) +#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK) +#define SI_TX_DATA1_DATA5_MSB 15 +#define SI_TX_DATA1_DATA5_LSB 8 +#define SI_TX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB) +#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK) +#define SI_TX_DATA1_DATA4_MSB 7 +#define SI_TX_DATA1_DATA4_LSB 0 +#define SI_TX_DATA1_DATA4_MASK 0x000000ff +#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB) +#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK) + +#define SI_RX_DATA0_ADDRESS 0x00000010 +#define SI_RX_DATA0_OFFSET 0x00000010 +#define SI_RX_DATA0_DATA3_MSB 31 +#define SI_RX_DATA0_DATA3_LSB 24 +#define SI_RX_DATA0_DATA3_MASK 0xff000000 +#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB) +#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK) +#define SI_RX_DATA0_DATA2_MSB 23 +#define SI_RX_DATA0_DATA2_LSB 16 +#define SI_RX_DATA0_DATA2_MASK 0x00ff0000 +#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB) +#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK) +#define SI_RX_DATA0_DATA1_MSB 15 +#define SI_RX_DATA0_DATA1_LSB 8 +#define SI_RX_DATA0_DATA1_MASK 0x0000ff00 +#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB) +#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK) +#define SI_RX_DATA0_DATA0_MSB 7 +#define SI_RX_DATA0_DATA0_LSB 0 +#define SI_RX_DATA0_DATA0_MASK 0x000000ff +#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB) +#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK) + +#define SI_RX_DATA1_ADDRESS 0x00000014 +#define SI_RX_DATA1_OFFSET 0x00000014 +#define SI_RX_DATA1_DATA7_MSB 31 +#define SI_RX_DATA1_DATA7_LSB 24 +#define SI_RX_DATA1_DATA7_MASK 0xff000000 +#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB) +#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK) +#define SI_RX_DATA1_DATA6_MSB 23 +#define SI_RX_DATA1_DATA6_LSB 16 +#define SI_RX_DATA1_DATA6_MASK 0x00ff0000 +#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB) +#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK) +#define SI_RX_DATA1_DATA5_MSB 15 +#define SI_RX_DATA1_DATA5_LSB 8 +#define SI_RX_DATA1_DATA5_MASK 0x0000ff00 +#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB) +#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK) +#define SI_RX_DATA1_DATA4_MSB 7 +#define SI_RX_DATA1_DATA4_LSB 0 +#define SI_RX_DATA1_DATA4_MASK 0x000000ff +#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB) +#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct si_reg_reg_s { + volatile unsigned int si_config; + volatile unsigned int si_cs; + volatile unsigned int si_tx_data0; + volatile unsigned int si_tx_data1; + volatile unsigned int si_rx_data0; + volatile unsigned int si_rx_data1; +} si_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _SI_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h new file mode 100644 index 000000000000..9e01b6a0875a --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/uart_reg.h @@ -0,0 +1,256 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UART_REG_REG_H_ +#define _UART_REG_REG_H_ + +#define UART_DATA_ADDRESS 0x00000000 +#define UART_DATA_OFFSET 0x00000000 +#define UART_DATA_TX_CSR_MSB 9 +#define UART_DATA_TX_CSR_LSB 9 +#define UART_DATA_TX_CSR_MASK 0x00000200 +#define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB) +#define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK) +#define UART_DATA_RX_CSR_MSB 8 +#define UART_DATA_RX_CSR_LSB 8 +#define UART_DATA_RX_CSR_MASK 0x00000100 +#define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB) +#define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK) +#define UART_DATA_TXRX_DATA_MSB 7 +#define UART_DATA_TXRX_DATA_LSB 0 +#define UART_DATA_TXRX_DATA_MASK 0x000000ff +#define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB) +#define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK) + +#define UART_CONTROL_ADDRESS 0x00000004 +#define UART_CONTROL_OFFSET 0x00000004 +#define UART_CONTROL_RX_BUSY_MSB 15 +#define UART_CONTROL_RX_BUSY_LSB 15 +#define UART_CONTROL_RX_BUSY_MASK 0x00008000 +#define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB) +#define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK) +#define UART_CONTROL_TX_BUSY_MSB 14 +#define UART_CONTROL_TX_BUSY_LSB 14 +#define UART_CONTROL_TX_BUSY_MASK 0x00004000 +#define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB) +#define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK) +#define UART_CONTROL_HOST_INT_ENABLE_MSB 13 +#define UART_CONTROL_HOST_INT_ENABLE_LSB 13 +#define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000 +#define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB) +#define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK) +#define UART_CONTROL_HOST_INT_MSB 12 +#define UART_CONTROL_HOST_INT_LSB 12 +#define UART_CONTROL_HOST_INT_MASK 0x00001000 +#define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB) +#define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK) +#define UART_CONTROL_TX_BREAK_MSB 11 +#define UART_CONTROL_TX_BREAK_LSB 11 +#define UART_CONTROL_TX_BREAK_MASK 0x00000800 +#define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB) +#define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK) +#define UART_CONTROL_RX_BREAK_MSB 10 +#define UART_CONTROL_RX_BREAK_LSB 10 +#define UART_CONTROL_RX_BREAK_MASK 0x00000400 +#define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB) +#define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK) +#define UART_CONTROL_SERIAL_TX_READY_MSB 9 +#define UART_CONTROL_SERIAL_TX_READY_LSB 9 +#define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200 +#define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB) +#define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK) +#define UART_CONTROL_TX_READY_ORIDE_MSB 8 +#define UART_CONTROL_TX_READY_ORIDE_LSB 8 +#define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100 +#define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB) +#define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK) +#define UART_CONTROL_RX_READY_ORIDE_MSB 7 +#define UART_CONTROL_RX_READY_ORIDE_LSB 7 +#define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080 +#define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB) +#define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK) +#define UART_CONTROL_DMA_ENABLE_MSB 6 +#define UART_CONTROL_DMA_ENABLE_LSB 6 +#define UART_CONTROL_DMA_ENABLE_MASK 0x00000040 +#define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB) +#define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK) +#define UART_CONTROL_FLOW_ENABLE_MSB 5 +#define UART_CONTROL_FLOW_ENABLE_LSB 5 +#define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020 +#define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB) +#define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK) +#define UART_CONTROL_FLOW_INVERT_MSB 4 +#define UART_CONTROL_FLOW_INVERT_LSB 4 +#define UART_CONTROL_FLOW_INVERT_MASK 0x00000010 +#define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB) +#define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK) +#define UART_CONTROL_IFC_ENABLE_MSB 3 +#define UART_CONTROL_IFC_ENABLE_LSB 3 +#define UART_CONTROL_IFC_ENABLE_MASK 0x00000008 +#define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB) +#define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK) +#define UART_CONTROL_IFC_DCE_MSB 2 +#define UART_CONTROL_IFC_DCE_LSB 2 +#define UART_CONTROL_IFC_DCE_MASK 0x00000004 +#define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB) +#define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK) +#define UART_CONTROL_PARITY_ENABLE_MSB 1 +#define UART_CONTROL_PARITY_ENABLE_LSB 1 +#define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002 +#define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB) +#define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK) +#define UART_CONTROL_PARITY_EVEN_MSB 0 +#define UART_CONTROL_PARITY_EVEN_LSB 0 +#define UART_CONTROL_PARITY_EVEN_MASK 0x00000001 +#define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB) +#define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK) + +#define UART_CLKDIV_ADDRESS 0x00000008 +#define UART_CLKDIV_OFFSET 0x00000008 +#define UART_CLKDIV_CLK_SCALE_MSB 23 +#define UART_CLKDIV_CLK_SCALE_LSB 16 +#define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000 +#define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB) +#define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK) +#define UART_CLKDIV_CLK_STEP_MSB 15 +#define UART_CLKDIV_CLK_STEP_LSB 0 +#define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff +#define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB) +#define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK) + +#define UART_INT_ADDRESS 0x0000000c +#define UART_INT_OFFSET 0x0000000c +#define UART_INT_TX_EMPTY_INT_MSB 9 +#define UART_INT_TX_EMPTY_INT_LSB 9 +#define UART_INT_TX_EMPTY_INT_MASK 0x00000200 +#define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB) +#define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK) +#define UART_INT_RX_FULL_INT_MSB 8 +#define UART_INT_RX_FULL_INT_LSB 8 +#define UART_INT_RX_FULL_INT_MASK 0x00000100 +#define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB) +#define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK) +#define UART_INT_RX_BREAK_OFF_INT_MSB 7 +#define UART_INT_RX_BREAK_OFF_INT_LSB 7 +#define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080 +#define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB) +#define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK) +#define UART_INT_RX_BREAK_ON_INT_MSB 6 +#define UART_INT_RX_BREAK_ON_INT_LSB 6 +#define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040 +#define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB) +#define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK) +#define UART_INT_RX_PARITY_ERR_INT_MSB 5 +#define UART_INT_RX_PARITY_ERR_INT_LSB 5 +#define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020 +#define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB) +#define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK) +#define UART_INT_TX_OFLOW_ERR_INT_MSB 4 +#define UART_INT_TX_OFLOW_ERR_INT_LSB 4 +#define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010 +#define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB) +#define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK) +#define UART_INT_RX_OFLOW_ERR_INT_MSB 3 +#define UART_INT_RX_OFLOW_ERR_INT_LSB 3 +#define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008 +#define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB) +#define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK) +#define UART_INT_RX_FRAMING_ERR_INT_MSB 2 +#define UART_INT_RX_FRAMING_ERR_INT_LSB 2 +#define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004 +#define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB) +#define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK) +#define UART_INT_TX_READY_INT_MSB 1 +#define UART_INT_TX_READY_INT_LSB 1 +#define UART_INT_TX_READY_INT_MASK 0x00000002 +#define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB) +#define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK) +#define UART_INT_RX_VALID_INT_MSB 0 +#define UART_INT_RX_VALID_INT_LSB 0 +#define UART_INT_RX_VALID_INT_MASK 0x00000001 +#define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB) +#define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK) + +#define UART_INT_EN_ADDRESS 0x00000010 +#define UART_INT_EN_OFFSET 0x00000010 +#define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9 +#define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9 +#define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200 +#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB) +#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) +#define UART_INT_EN_RX_FULL_INT_EN_MSB 8 +#define UART_INT_EN_RX_FULL_INT_EN_LSB 8 +#define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100 +#define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB) +#define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK) +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080 +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) +#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) +#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040 +#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) +#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020 +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010 +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) +#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008 +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004 +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) +#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) +#define UART_INT_EN_TX_READY_INT_EN_MSB 1 +#define UART_INT_EN_TX_READY_INT_EN_LSB 1 +#define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002 +#define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB) +#define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK) +#define UART_INT_EN_RX_VALID_INT_EN_MSB 0 +#define UART_INT_EN_RX_VALID_INT_EN_LSB 0 +#define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001 +#define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB) +#define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct uart_reg_reg_s { + volatile unsigned int uart_data; + volatile unsigned int uart_control; + volatile unsigned int uart_clkdiv; + volatile unsigned int uart_int; + volatile unsigned int uart_int_en; +} uart_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UART_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h new file mode 100644 index 000000000000..d8a07b30043b --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_reg.h @@ -0,0 +1,33 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "umbox_wlan_reg.h" + + +#ifndef BT_HEADERS + + + +#endif +#endif + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h new file mode 100644 index 000000000000..9b63f5f40757 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/umbox_wlan_reg.h @@ -0,0 +1,318 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _UMBOX_WLAN_REG_REG_H_ +#define _UMBOX_WLAN_REG_REG_H_ + +#define UMBOX_FIFO_ADDRESS 0x00000000 +#define UMBOX_FIFO_OFFSET 0x00000000 +#define UMBOX_FIFO_DATA_MSB 8 +#define UMBOX_FIFO_DATA_LSB 0 +#define UMBOX_FIFO_DATA_MASK 0x000001ff +#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB) +#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK) + +#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008 +#define UMBOX_FIFO_STATUS_OFFSET 0x00000008 +#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3 +#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3 +#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008 +#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB) +#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) +#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2 +#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2 +#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004 +#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB) +#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK) +#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1 +#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1 +#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002 +#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB) +#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) +#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0 +#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0 +#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001 +#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB) +#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK) + +#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c +#define UMBOX_DMA_POLICY_OFFSET 0x0000000c +#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3 +#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3 +#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008 +#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB) +#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) +#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2 +#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2 +#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004 +#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB) +#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK) +#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1 +#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1 +#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002 +#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB) +#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) +#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0 +#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0 +#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001 +#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB) +#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK) + +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014 +#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014 +#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2 +#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2 +#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004 +#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB) +#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) +#define UMBOX0_DMA_RX_CONTROL_START_MSB 1 +#define UMBOX0_DMA_RX_CONTROL_START_LSB 1 +#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002 +#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB) +#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK) +#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0 +#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0 +#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001 +#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB) +#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) + +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2 +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) +#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) + +#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c +#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c +#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2 +#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2 +#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004 +#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB) +#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) +#define UMBOX0_DMA_TX_CONTROL_START_MSB 1 +#define UMBOX0_DMA_TX_CONTROL_START_LSB 1 +#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002 +#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB) +#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK) +#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0 +#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0 +#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001 +#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB) +#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) + +#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020 +#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100 +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) +#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) +#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7 +#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0 +#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff +#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB) +#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) + +#define UMBOX_INT_STATUS_ADDRESS 0x00000024 +#define UMBOX_INT_STATUS_OFFSET 0x00000024 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200 +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100 +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080 +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) +#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040 +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) +#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020 +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) +#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) +#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) +#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3 +#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3 +#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008 +#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB) +#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) +#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004 +#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) +#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002 +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) +#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) +#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0 +#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0 +#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001 +#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB) +#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) + +#define UMBOX_INT_ENABLE_ADDRESS 0x00000028 +#define UMBOX_INT_ENABLE_OFFSET 0x00000028 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200 +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100 +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080 +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040 +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020 +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) +#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) +#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) +#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008 +#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) +#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004 +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) +#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002 +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) +#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) +#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001 +#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) +#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) + +#define UMBOX_DEBUG_ADDRESS 0x0000002c +#define UMBOX_DEBUG_OFFSET 0x0000002c +#define UMBOX_DEBUG_SEL_MSB 2 +#define UMBOX_DEBUG_SEL_LSB 0 +#define UMBOX_DEBUG_SEL_MASK 0x00000007 +#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB) +#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK) + +#define UMBOX_FIFO_RESET_ADDRESS 0x00000030 +#define UMBOX_FIFO_RESET_OFFSET 0x00000030 +#define UMBOX_FIFO_RESET_INIT_MSB 0 +#define UMBOX_FIFO_RESET_INIT_LSB 0 +#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001 +#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB) +#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK) + +#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034 +#define UMBOX_HCI_FRAMER_OFFSET 0x00000034 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040 +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) +#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) +#define UMBOX_HCI_FRAMER_ENABLE_MSB 5 +#define UMBOX_HCI_FRAMER_ENABLE_LSB 5 +#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020 +#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB) +#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK) +#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010 +#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) +#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) +#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3 +#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3 +#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008 +#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB) +#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) +#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2 +#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2 +#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004 +#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB) +#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) +#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003 +#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) +#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct umbox_wlan_reg_reg_s { + volatile unsigned int umbox_fifo[2]; + volatile unsigned int umbox_fifo_status; + volatile unsigned int umbox_dma_policy; + volatile unsigned int umbox0_dma_rx_descriptor_base; + volatile unsigned int umbox0_dma_rx_control; + volatile unsigned int umbox0_dma_tx_descriptor_base; + volatile unsigned int umbox0_dma_tx_control; + volatile unsigned int umbox_fifo_timeout; + volatile unsigned int umbox_int_status; + volatile unsigned int umbox_int_enable; + volatile unsigned int umbox_debug; + volatile unsigned int umbox_fifo_reset; + volatile unsigned int umbox_hci_framer; +} umbox_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _UMBOX_WLAN_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h new file mode 100644 index 000000000000..2d7b6aa06911 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_reg.h @@ -0,0 +1,163 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifdef WLAN_HEADERS + +#include "vmc_wlan_reg.h" + + +#ifndef BT_HEADERS + +#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS +#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET +#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB +#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB +#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK +#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x) +#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x) +#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS +#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET +#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB +#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB +#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK +#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x) +#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x) +#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS +#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET +#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB +#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB +#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK +#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x) +#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x) +#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS +#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) +#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) +#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB +#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB +#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK +#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) +#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS +#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET +#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB +#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB +#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK +#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) +#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB +#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB +#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK +#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) +#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) +#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS +#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET +#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB +#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB +#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK +#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) +#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS +#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET +#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB +#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB +#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK +#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) +#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) +#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB +#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB +#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK +#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) +#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB +#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB +#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK +#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) +#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) +#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS +#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) +#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) +#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) +#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS +#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET +#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB +#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB +#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK +#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x) +#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x) +#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS +#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET +#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB +#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB +#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK +#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x) +#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x) +#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS +#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET +#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB +#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB +#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK +#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x) +#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x) +#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS +#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET +#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB +#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB +#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK +#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) +#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) +#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS +#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET +#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB +#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB +#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK +#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) +#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) +#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS +#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET +#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB +#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB +#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK +#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) +#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) +#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS +#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET +#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB +#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB +#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK +#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) +#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) + + +#endif +#endif + + + diff --git a/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h new file mode 100644 index 000000000000..ff6d14545cd0 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/AR6002/hw4.0/hw/vmc_wlan_reg.h @@ -0,0 +1,191 @@ +// ------------------------------------------------------------------ +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +// ------------------------------------------------------------------ +//=================================================================== +// Author(s): ="Atheros" +//=================================================================== + + +#ifndef _VMC_WLAN_REG_REG_H_ +#define _VMC_WLAN_REG_REG_H_ + +#define WLAN_MC_BCAM_VALID_ADDRESS 0x00000000 +#define WLAN_MC_BCAM_VALID_OFFSET 0x00000000 +#define WLAN_MC_BCAM_VALID_BIT_MSB 0 +#define WLAN_MC_BCAM_VALID_BIT_LSB 0 +#define WLAN_MC_BCAM_VALID_BIT_MASK 0x00000001 +#define WLAN_MC_BCAM_VALID_BIT_GET(x) (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB) +#define WLAN_MC_BCAM_VALID_BIT_SET(x) (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK) + +#define WLAN_MC_BCAM_COMPARE_ADDRESS 0x00000200 +#define WLAN_MC_BCAM_COMPARE_OFFSET 0x00000200 +#define WLAN_MC_BCAM_COMPARE_KEY_MSB 19 +#define WLAN_MC_BCAM_COMPARE_KEY_LSB 2 +#define WLAN_MC_BCAM_COMPARE_KEY_MASK 0x000ffffc +#define WLAN_MC_BCAM_COMPARE_KEY_GET(x) (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB) +#define WLAN_MC_BCAM_COMPARE_KEY_SET(x) (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK) + +#define WLAN_MC_BCAM_TARGET_ADDRESS 0x00000400 +#define WLAN_MC_BCAM_TARGET_OFFSET 0x00000400 +#define WLAN_MC_BCAM_TARGET_INST_MSB 31 +#define WLAN_MC_BCAM_TARGET_INST_LSB 0 +#define WLAN_MC_BCAM_TARGET_INST_MASK 0xffffffff +#define WLAN_MC_BCAM_TARGET_INST_GET(x) (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB) +#define WLAN_MC_BCAM_TARGET_INST_SET(x) (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK) + +#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS 0x00000600 +#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET 0x00000600 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) +#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) +#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS 0x00000604 +#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET 0x00000604 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB 25 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB 25 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) +#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB 24 +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) +#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) + +#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS 0x00000608 +#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET 0x00000608 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB 0 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB 0 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) +#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) + +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS 0x0000060c +#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET 0x0000060c +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB 31 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB 31 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK 0x80000000 +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB 30 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB 30 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK 0x40000000 +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB 23 +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB 0 +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x00ffffff +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) +#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) + +#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS 0x00000610 +#define WLAN_BCAM_CONFLICT_ERROR_OFFSET 0x00000610 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB 1 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB 1 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002 +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) +#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB 0 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB 0 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001 +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) +#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) + +#define WLAN_CPU_PERF_CNT_ADDRESS 0x00000614 +#define WLAN_CPU_PERF_CNT_OFFSET 0x00000614 +#define WLAN_CPU_PERF_CNT_EN_MSB 0 +#define WLAN_CPU_PERF_CNT_EN_LSB 0 +#define WLAN_CPU_PERF_CNT_EN_MASK 0x00000001 +#define WLAN_CPU_PERF_CNT_EN_GET(x) (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB) +#define WLAN_CPU_PERF_CNT_EN_SET(x) (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK) + +#define WLAN_CPU_INST_FETCH_ADDRESS 0x00000618 +#define WLAN_CPU_INST_FETCH_OFFSET 0x00000618 +#define WLAN_CPU_INST_FETCH_CNT_MSB 31 +#define WLAN_CPU_INST_FETCH_CNT_LSB 0 +#define WLAN_CPU_INST_FETCH_CNT_MASK 0xffffffff +#define WLAN_CPU_INST_FETCH_CNT_GET(x) (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB) +#define WLAN_CPU_INST_FETCH_CNT_SET(x) (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK) + +#define WLAN_CPU_DATA_FETCH_ADDRESS 0x0000061c +#define WLAN_CPU_DATA_FETCH_OFFSET 0x0000061c +#define WLAN_CPU_DATA_FETCH_CNT_MSB 31 +#define WLAN_CPU_DATA_FETCH_CNT_LSB 0 +#define WLAN_CPU_DATA_FETCH_CNT_MASK 0xffffffff +#define WLAN_CPU_DATA_FETCH_CNT_GET(x) (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB) +#define WLAN_CPU_DATA_FETCH_CNT_SET(x) (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK) + +#define WLAN_CPU_RAM1_CONFLICT_ADDRESS 0x00000620 +#define WLAN_CPU_RAM1_CONFLICT_OFFSET 0x00000620 +#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM2_CONFLICT_ADDRESS 0x00000624 +#define WLAN_CPU_RAM2_CONFLICT_OFFSET 0x00000624 +#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM3_CONFLICT_ADDRESS 0x00000628 +#define WLAN_CPU_RAM3_CONFLICT_OFFSET 0x00000628 +#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) + +#define WLAN_CPU_RAM4_CONFLICT_ADDRESS 0x0000062c +#define WLAN_CPU_RAM4_CONFLICT_OFFSET 0x0000062c +#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB 11 +#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB 0 +#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK 0x00000fff +#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB) +#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) + + +#ifndef __ASSEMBLER__ + +typedef struct vmc_wlan_reg_reg_s { + volatile unsigned int wlan_mc_bcam_valid[128]; + volatile unsigned int wlan_mc_bcam_compare[128]; + volatile unsigned int wlan_mc_bcam_target[128]; + volatile unsigned int wlan_apb_addr_error_control; + volatile unsigned int wlan_apb_addr_error_status; + volatile unsigned int wlan_ahb_addr_error_control; + volatile unsigned int wlan_ahb_addr_error_status; + volatile unsigned int wlan_bcam_conflict_error; + volatile unsigned int wlan_cpu_perf_cnt; + volatile unsigned int wlan_cpu_inst_fetch; + volatile unsigned int wlan_cpu_data_fetch; + volatile unsigned int wlan_cpu_ram1_conflict; + volatile unsigned int wlan_cpu_ram2_conflict; + volatile unsigned int wlan_cpu_ram3_conflict; + volatile unsigned int wlan_cpu_ram4_conflict; +} vmc_wlan_reg_reg_t; + +#endif /* __ASSEMBLER__ */ + +#endif /* _VMC_WLAN_REG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/a_config.h b/drivers/net/wireless/ath6kl/include/a_config.h new file mode 100644 index 000000000000..8f9ccf7d1a29 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/a_config.h @@ -0,0 +1,45 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains software configuration options that enables +// specific software "features" +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_CONFIG_H_ +#define _A_CONFIG_H_ + +#ifdef UNDER_NWIFI +#include "../os/windows/include/config.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/windows/include/config.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/config_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/config_rexos.h" +#endif + +#ifdef WIN_NWF +#include "../os/windows/include/win/config_win.h" +#endif + +#endif diff --git a/drivers/net/wireless/ath6kl/include/a_debug.h b/drivers/net/wireless/ath6kl/include/a_debug.h new file mode 100644 index 000000000000..f8f7a2cdf5d3 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/a_debug.h @@ -0,0 +1,215 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DEBUG_H_ +#define _A_DEBUG_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include +#include + + /* standard debug print masks bits 0..7 */ +#define ATH_DEBUG_ERR (1 << 0) /* errors */ +#define ATH_DEBUG_WARN (1 << 1) /* warnings */ +#define ATH_DEBUG_INFO (1 << 2) /* informational (module startup info) */ +#define ATH_DEBUG_TRC (1 << 3) /* generic function call tracing */ +#define ATH_DEBUG_RSVD1 (1 << 4) +#define ATH_DEBUG_RSVD2 (1 << 5) +#define ATH_DEBUG_RSVD3 (1 << 6) +#define ATH_DEBUG_RSVD4 (1 << 7) + +#define ATH_DEBUG_MASK_DEFAULTS (ATH_DEBUG_ERR | ATH_DEBUG_WARN) +#define ATH_DEBUG_ANY 0xFFFF + + /* other aliases used throughout */ +#define ATH_DEBUG_ERROR ATH_DEBUG_ERR +#define ATH_LOG_ERR ATH_DEBUG_ERR +#define ATH_LOG_INF ATH_DEBUG_INFO +#define ATH_LOG_TRC ATH_DEBUG_TRC +#define ATH_DEBUG_TRACE ATH_DEBUG_TRC +#define ATH_DEBUG_INIT ATH_DEBUG_INFO + + /* bits 8..31 are module-specific masks */ +#define ATH_DEBUG_MODULE_MASK_SHIFT 8 + + /* macro to make a module-specific masks */ +#define ATH_DEBUG_MAKE_MODULE_MASK(index) (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index))) + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription); + +/* Debug support on a per-module basis + * + * Usage: + * + * Each module can utilize it's own debug mask variable. A set of commonly used + * masks are provided (ERRORS, WARNINGS, TRACE etc..). It is up to each module + * to define module-specific masks using the macros above. + * + * Each module defines a single debug mask variable debug_XXX where the "name" of the module is + * common to all C-files within that module. This requires every C-file that includes a_debug.h + * to define the module name in that file. + * + * Example: + * + * #define ATH_MODULE_NAME htc + * #include "a_debug.h" + * + * This will define a debug mask structure called debug_htc and all debug macros will reference this + * variable. + * + * A module can define module-specific bit masks using the ATH_DEBUG_MAKE_MODULE_MASK() macro: + * + * #define ATH_DEBUG_MY_MASK1 ATH_DEBUG_MAKE_MODULE_MASK(0) + * #define ATH_DEBUG_MY_MASK2 ATH_DEBUG_MAKE_MODULE_MASK(1) + * + * The instantiation of the debug structure should be made by the module. When a module is + * instantiated, the module can set a description string, a default mask and an array of description + * entries containing information on each module-defined debug mask. + * NOTE: The instantiation is statically allocated, only one instance can exist per module. + * + * Example: + * + * + * #define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0) + * + * #ifdef DEBUG + * static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = { + * { ATH_DEBUG_BMI , "BMI Tracing"}, <== description of the module specific mask + * }; + * + * ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi, + * "bmi" <== module name + * "Boot Manager Interface", <== description of module + * ATH_DEBUG_MASK_DEFAULTS, <== defaults + * ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc), + * bmi_debug_desc); + * + * #endif + * + * A module can optionally register it's debug module information in order for other tools to change the + * bit mask at runtime. A module can call A_REGISTER_MODULE_DEBUG_INFO() in it's module + * init code. This macro can be called multiple times without consequence. The debug info maintains + * state to indicate whether the information was previously registered. + * + * */ + +#define ATH_DEBUG_MAX_MASK_DESC_LENGTH 32 +#define ATH_DEBUG_MAX_MOD_DESC_LENGTH 64 + +typedef struct { + A_UINT32 Mask; + A_CHAR Description[ATH_DEBUG_MAX_MASK_DESC_LENGTH]; +} ATH_DEBUG_MASK_DESCRIPTION; + +#define ATH_DEBUG_INFO_FLAGS_REGISTERED (1 << 0) + +typedef struct _ATH_DEBUG_MODULE_DBG_INFO{ + struct _ATH_DEBUG_MODULE_DBG_INFO *pNext; + A_CHAR ModuleName[16]; + A_CHAR ModuleDescription[ATH_DEBUG_MAX_MOD_DESC_LENGTH]; + A_UINT32 Flags; + A_UINT32 CurrentMask; + int MaxDescriptions; + ATH_DEBUG_MASK_DESCRIPTION *pMaskDescriptions; /* pointer to array of descriptions */ +} ATH_DEBUG_MODULE_DBG_INFO; + +#define ATH_DEBUG_DESCRIPTION_COUNT(d) (int)((sizeof((d))) / (sizeof(ATH_DEBUG_MASK_DESCRIPTION))) + +#define GET_ATH_MODULE_DEBUG_VAR_NAME(s) _XGET_ATH_MODULE_NAME_DEBUG_(s) +#define GET_ATH_MODULE_DEBUG_VAR_MASK(s) _XGET_ATH_MODULE_NAME_DEBUG_(s).CurrentMask +#define _XGET_ATH_MODULE_NAME_DEBUG_(s) debug_ ## s + +#ifdef DEBUG + + /* for source files that will instantiate the debug variables */ +#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions) \ +ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s) = \ + {NULL,(name),(moddesc),0,(initmask),count,(descriptions)} + +#ifdef ATH_MODULE_NAME +extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(ATH_MODULE_NAME); +#define AR_DEBUG_LVL_CHECK(lvl) (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (lvl)) +#endif /* ATH_MODULE_NAME */ + +#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl) GET_ATH_MODULE_DEBUG_VAR_MASK(s) = (lvl) + +#define ATH_DEBUG_DECLARE_EXTERN(s) \ + extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s) + +#define AR_DEBUG_PRINTBUF(buffer, length, desc) DebugDumpBytes(buffer,length,desc) + + +#define AR_DEBUG_ASSERT A_ASSERT + +void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo); +void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo); +#define A_DUMP_MODULE_DEBUG_INFO(s) a_dump_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s))) +#define A_REGISTER_MODULE_DEBUG_INFO(s) a_register_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s))) + +#else /* !DEBUG */ + /* NON DEBUG */ +#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions) +#define AR_DEBUG_LVL_CHECK(lvl) 0 +#define AR_DEBUG_PRINTBUF(buffer, length, desc) +#define AR_DEBUG_ASSERT(test) +#define ATH_DEBUG_DECLARE_EXTERN(s) +#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl) +#define A_DUMP_MODULE_DEBUG_INFO(s) +#define A_REGISTER_MODULE_DEBUG_INFO(s) + +#endif + +A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask); +A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask); +void a_dump_module_debug_info_by_name(A_CHAR *module_name); +void a_module_debug_support_init(void); +void a_module_debug_support_cleanup(void); + +#ifdef UNDER_NWIFI +#include "../os/windows/include/debug.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/windows/include/debug.h" +#endif + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/debug_linux.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/debug_rexos.h" +#endif + +#if defined ART_WIN +#include "../os/win_art/include/debug_win.h" +#endif + +#ifdef WIN_NWF +#include +#endif + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif diff --git a/drivers/net/wireless/ath6kl/include/a_drv.h b/drivers/net/wireless/ath6kl/include/a_drv.h new file mode 100644 index 000000000000..f7a6afe91993 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/a_drv.h @@ -0,0 +1,46 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_H_ +#define _A_DRV_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/athdrv_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/include/athdrv.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/windows/include/athdrv.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athdrv_rexos.h" +#endif + +#ifdef WIN_NWF +#include "../os/windows/include/athdrv.h" +#endif + +#endif /* _ADRV_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/a_drv_api.h b/drivers/net/wireless/ath6kl/include/a_drv_api.h new file mode 100644 index 000000000000..b3dd4f5635b4 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/a_drv_api.h @@ -0,0 +1,228 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_DRV_API_H_ +#define _A_DRV_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** WMI related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#include + +#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \ + ar6000_channelList_rx((devt), (numChan), (chanList)) + +#define A_WMI_SET_NUMDATAENDPTS(devt, num) \ + ar6000_set_numdataendpts((devt), (num)) + +#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \ + ar6000_control_tx((devt), (osbuf), (streamID)) + +#define A_WMI_TARGETSTATS_EVENT(devt, pStats, len) \ + ar6000_targetStats_event((devt), (pStats), (len)) + +#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \ + ar6000_scanComplete_event((devt), (status)) + +#ifdef CONFIG_HOST_DSET_SUPPORT + +#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_DSET_CLOSE(devt, access_cookie) \ + ar6000_dset_close((devt), (access_cookie)) + +#endif + +#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \ + ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg)) + +#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \ + ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo)) + +#define A_WMI_PSPOLL_EVENT(devt, aid)\ + ar6000_pspoll_event((devt),(aid)) + +#define A_WMI_DTIMEXPIRY_EVENT(devt)\ + ar6000_dtimexpiry_event((devt)) + +#ifdef WAPI_ENABLE +#define A_WMI_WAPI_REKEY_EVENT(devt, type, mac)\ + ap_wapi_rekey_event((devt),(type),(mac)) +#endif + +#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \ + ar6000_regDomain_event((devt), (regCode)) + +#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \ + ar6000_neighborReport_event((devt), (numAps), (info)) + +#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \ + ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus)) + +#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \ + ar6000_tkip_micerr_event((devt), (keyid), (ismcast)) + +#define A_WMI_BITRATE_RX(devt, rateKbps) \ + ar6000_bitrate_rx((devt), (rateKbps)) + +#define A_WMI_TXPWR_RX(devt, txPwr) \ + ar6000_txPwr_rx((devt), (txPwr)) + +#define A_WMI_READY_EVENT(devt, datap, phyCap, ver) \ + ar6000_ready_event((devt), (datap), (phyCap), (ver)) + +#define A_WMI_DBGLOG_INIT_DONE(ar) \ + ar6000_dbglog_init_done(ar); + +#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \ + ar6000_rssiThreshold_event((devt), (newThreshold), (rssi)) + +#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \ + ar6000_reportError_event((devt), (errorVal)) + +#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \ + ar6000_roam_tbl_event((devt), (pTbl)) + +#define A_WMI_ROAM_DATA_EVENT(devt, p) \ + ar6000_roam_data_event((devt), (p)) + +#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \ + ar6000_wow_list_event((devt), (num_filters), (wow_filters)) + +#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \ + ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion)) + +#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel) \ + ar6000_channel_change_event((devt), (oldChannel), (newChannel)) + +#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \ + ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list)) + +#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \ + ar6000_peer_event ((devt), (eventCode), (bssid)) + +#ifdef CONFIG_HOST_GPIO_SUPPORT + +#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \ + ar6000_gpio_intr_rx((intr_mask), (input_values)) + +#define A_WMI_GPIO_DATA_RX(reg_id, value) \ + ar6000_gpio_data_rx((reg_id), (value)) + +#define A_WMI_GPIO_ACK_RX() \ + ar6000_gpio_ack_rx() + +#endif + +#ifdef SEND_EVENT_TO_APP + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \ + ar6000_send_event_to_app((ar), (eventId), (datap), (len)) + +#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \ + ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len)) + +#else + +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) +#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) + +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \ + ar6000_tcmd_rx_report_event((devt), (results), (len)) +#endif + +#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \ + ar6000_hbChallengeResp_event((devt), (cookie), (source)) + +#define A_WMI_TX_RETRY_ERR_EVENT(devt) \ + ar6000_tx_retry_err_event((devt)) + +#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \ + ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr)) + +#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \ + ar6000_lqThresholdEvent_rx((devt), (range), (lqVal)) + +#define A_WMI_RATEMASK_RX(devt, ratemask) \ + ar6000_ratemask_rx((devt), (ratemask)) + +#define A_WMI_KEEPALIVE_RX(devt, configured) \ + ar6000_keepalive_rx((devt), (configured)) + +#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \ + ar6000_bssInfo_event_rx((ar), (datap), (len)) + +#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \ + ar6000_dbglog_event((ar), (dropped), (buffer), (length)); + +#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), TRUE) + +#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \ + ar6000_indicate_tx_activity((devt),(trafficClass), FALSE) +#define A_WMI_Ac2EndpointID(devht, ac)\ + ar6000_ac2_endpoint_id((devht), (ac)) + +#define A_WMI_AGGR_RECV_ADDBA_REQ_EVT(devt, cmd)\ + ar6000_aggr_rcv_addba_req_evt((devt), (cmd)) +#define A_WMI_AGGR_RECV_ADDBA_RESP_EVT(devt, cmd)\ + ar6000_aggr_rcv_addba_resp_evt((devt), (cmd)) +#define A_WMI_AGGR_RECV_DELBA_REQ_EVT(devt, cmd)\ + ar6000_aggr_rcv_delba_req_evt((devt), (cmd)) +#define A_WMI_HCI_EVENT_EVT(devt, cmd)\ + ar6000_hci_event_rcv_evt((devt), (cmd)) + +#define A_WMI_Endpoint2Ac(devt, ep) \ + ar6000_endpoint_id2_ac((devt), (ep)) + +#define A_WMI_BTCOEX_CONFIG_EVENT(devt, evt, len)\ + ar6000_btcoex_config_event((devt), (evt), (len)) + +#define A_WMI_BTCOEX_STATS_EVENT(devt, datap, len)\ + ar6000_btcoex_stats_event((devt), (datap), (len)) + +/****************************************************************************/ +/****************************************************************************/ +/** **/ +/** HTC related hooks **/ +/** **/ +/****************************************************************************/ +/****************************************************************************/ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count)) +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/net/wireless/ath6kl/include/a_hci.h b/drivers/net/wireless/ath6kl/include/a_hci.h new file mode 100644 index 000000000000..b1a66308d828 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/a_hci.h @@ -0,0 +1,668 @@ +//- +// Copyright (c) 2009 Atheros Communications Inc. +// All rights reserved. +// $ATH_LICENSE_TARGET_C$ +// +// + + +#ifndef __A_HCI_H__ +#define __A_HCI_H__ + +#define HCI_CMD_OGF_MASK 0x3F +#define HCI_CMD_OGF_SHIFT 10 +#define HCI_CMD_GET_OGF(opcode) ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK) + +#define HCI_CMD_OCF_MASK 0x3FF +#define HCI_CMD_OCF_SHIFT 0 +#define HCI_CMD_GET_OCF(opcode) (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK) + +#define HCI_FORM_OPCODE(ocf, ogf) ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \ + (ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT) + + +/*======== HCI Opcode groups ===============*/ +#define OGF_NOP 0x00 +#define OGF_LINK_CONTROL 0x01 +#define OGF_LINK_POLICY 0x03 +#define OGF_INFO_PARAMS 0x04 +#define OGF_STATUS 0x05 +#define OGF_TESTING 0x06 +#define OGF_BLUETOOTH 0x3E +#define OGF_VENDOR_DEBUG 0x3F + + + +#define OCF_NOP 0x00 + + +/*===== Link Control Commands Opcode===================*/ +#define OCF_HCI_Create_Physical_Link 0x35 +#define OCF_HCI_Accept_Physical_Link_Req 0x36 +#define OCF_HCI_Disconnect_Physical_Link 0x37 +#define OCF_HCI_Create_Logical_Link 0x38 +#define OCF_HCI_Accept_Logical_Link 0x39 +#define OCF_HCI_Disconnect_Logical_Link 0x3A +#define OCF_HCI_Logical_Link_Cancel 0x3B +#define OCF_HCI_Flow_Spec_Modify 0x3C + + + +/*===== Link Policy Commands Opcode====================*/ +#define OCF_HCI_Set_Event_Mask 0x01 +#define OCF_HCI_Reset 0x03 +#define OCF_HCI_Read_Conn_Accept_Timeout 0x15 +#define OCF_HCI_Write_Conn_Accept_Timeout 0x16 +#define OCF_HCI_Read_Link_Supervision_Timeout 0x36 +#define OCF_HCI_Write_Link_Supervision_Timeout 0x37 +#define OCF_HCI_Enhanced_Flush 0x5F +#define OCF_HCI_Read_Logical_Link_Accept_Timeout 0x61 +#define OCF_HCI_Write_Logical_Link_Accept_Timeout 0x62 +#define OCF_HCI_Set_Event_Mask_Page_2 0x63 +#define OCF_HCI_Read_Location_Data 0x64 +#define OCF_HCI_Write_Location_Data 0x65 +#define OCF_HCI_Read_Flow_Control_Mode 0x66 +#define OCF_HCI_Write_Flow_Control_Mode 0x67 +#define OCF_HCI_Read_BE_Flush_Timeout 0x69 +#define OCF_HCI_Write_BE_Flush_Timeout 0x6A +#define OCF_HCI_Short_Range_Mode 0x6B + + +/*======== Info Commands Opcode========================*/ +#define OCF_HCI_Read_Local_Ver_Info 0x01 +#define OCF_HCI_Read_Local_Supported_Cmds 0x02 +#define OCF_HCI_Read_Data_Block_Size 0x0A +/*======== Status Commands Opcode======================*/ +#define OCF_HCI_Read_Failed_Contact_Counter 0x01 +#define OCF_HCI_Reset_Failed_Contact_Counter 0x02 +#define OCF_HCI_Read_Link_Quality 0x03 +#define OCF_HCI_Read_RSSI 0x05 +#define OCF_HCI_Read_Local_AMP_Info 0x09 +#define OCF_HCI_Read_Local_AMP_ASSOC 0x0A +#define OCF_HCI_Write_Remote_AMP_ASSOC 0x0B + + +/*======= AMP_ASSOC Specific TLV tags =================*/ +#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE 0x1 +#define AMP_ASSOC_PREF_CHAN_LIST 0x2 +#define AMP_ASSOC_CONNECTED_CHAN 0x3 +#define AMP_ASSOC_PAL_CAPABILITIES 0x4 +#define AMP_ASSOC_PAL_VERSION 0x5 + + +/*========= PAL Events =================================*/ +#define PAL_COMMAND_COMPLETE_EVENT 0x0E +#define PAL_COMMAND_STATUS_EVENT 0x0F +#define PAL_HARDWARE_ERROR_EVENT 0x10 +#define PAL_FLUSH_OCCURRED_EVENT 0x11 +#define PAL_LOOPBACK_EVENT 0x19 +#define PAL_BUFFER_OVERFLOW_EVENT 0x1A +#define PAL_QOS_VIOLATION_EVENT 0x1E +#define PAL_ENHANCED_FLUSH_COMPLT_EVENT 0x39 +#define PAL_PHYSICAL_LINK_COMPL_EVENT 0x40 +#define PAL_CHANNEL_SELECT_EVENT 0x41 +#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT 0x42 +#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT 0x43 +#define PAL_PHY_LINK_RECOVERY_EVENT 0x44 +#define PAL_LOGICAL_LINK_COMPL_EVENT 0x45 +#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT 0x46 +#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT 0x47 +#define PAL_NUM_COMPL_DATA_BLOCK_EVENT 0x48 +#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT 0x4C +#define PAL_AMP_STATUS_CHANGE_EVENT 0x4D +/*======== End of PAL events definiton =================*/ + + +/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/ +#define Timer_Conn_Accept_TO 0x01 +#define Timer_Link_Supervision_TO 0x02 + +#define NUM_HCI_COMMAND_PKTS 0x1 + + +/*====== NOP Cmd ============================*/ +#define HCI_CMD_NOP HCI_FORM_OPCODE(OCF_NOP, OGF_NOP) + + +/*===== Link Control Commands================*/ +#define HCI_Create_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL) +#define HCI_Accept_Physical_Link_Req HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL) +#define HCI_Disconnect_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL) +#define HCI_Create_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL) +#define HCI_Accept_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL) +#define HCI_Disconnect_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL) +#define HCI_Logical_Link_Cancel HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL) +#define HCI_Flow_Spec_Modify HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL) + + +/*===== Link Policy Commands ================*/ +#define HCI_Set_Event_Mask HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY) +#define HCI_Reset HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY) +#define HCI_Enhanced_Flush HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY) +#define HCI_Read_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY) +#define HCI_Write_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY) +#define HCI_Read_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY) +#define HCI_Write_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY) +#define HCI_Read_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY) +#define HCI_Write_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY) +#define HCI_Read_Location_Data HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY) +#define HCI_Write_Location_Data HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY) +#define HCI_Set_Event_Mask_Page_2 HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY) +#define HCI_Read_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY) +#define HCI_Write_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY) +#define HCI_Write_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY) +#define HCI_Read_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY) +#define HCI_Short_Range_Mode HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY) + + +/*===== Info Commands =====================*/ +#define HCI_Read_Local_Ver_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info, OGF_INFO_PARAMS) +#define HCI_Read_Local_Supported_Cmds HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS) +#define HCI_Read_Data_Block_Size HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS) + +/*===== Status Commands =====================*/ +#define HCI_Read_Link_Quality HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS) +#define HCI_Read_RSSI HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS) +#define HCI_Read_Local_AMP_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS) +#define HCI_Read_Local_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS) +#define HCI_Write_Remote_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS) + +/*====== End of cmd definitions =============*/ + + + +/*===== Timeouts(private - can't come from HCI)=================*/ +#define Conn_Accept_TO HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG) +#define Link_Supervision_TO HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG) + +/*----- PAL Constants (Sec 6 of Doc)------------------------*/ +#define Max80211_PAL_PDU_Size 1492 +#define Max80211_AMP_ASSOC_Len 672 +#define MinGUserPrio 4 +#define MaxGUserPrio 7 +#define BEUserPrio0 0 +#define BEUserPrio1 3 +#define Max80211BeaconPeriod 2000 /* in millisec */ +#define ShortRangeModePowerMax 4 /* dBm */ + +/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/ +typedef enum { + ACL_DATA = 0x01, + ACTIVITY_REPORT, + SECURED_FRAMES, + LINK_SUPERVISION_REQ, + LINK_SUPERVISION_RESP, +}PAL_PROTOCOL_IDENTIFIERS; + +#define HCI_CMD_HDR_SZ 3 +#define HCI_EVENT_HDR_SIZE 2 +#define MAX_EVT_PKT_SZ 255 +#define AMP_ASSOC_MAX_FRAG_SZ 248 +#define AMP_MAX_GUARANTEED_BW 20000 + +#define DEFAULT_CONN_ACCPT_TO 5000 +#define DEFAULT_LL_ACCPT_TO 5000 +#define DEFAULT_LSTO 10000 + +#define PACKET_BASED_FLOW_CONTROL_MODE 0x00 +#define DATA_BLK_BASED_FLOW_CONTROL_MODE 0x01 + +#define SERVICE_TYPE_BEST_EFFORT 0x01 +#define SERVICE_TYPE_GUARANTEED 0x02 + +#define MAC_ADDR_LEN 6 +#define LINK_KEY_LEN 32 + +typedef enum { + ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00, + ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01, + ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02, + ACL_DATA_PB_COMPLETE_PDU = 0x03, +} ACL_DATA_PB_FLAGS; +#define ACL_DATA_PB_FLAGS_SHIFT 12 + +typedef enum { + ACL_DATA_BC_POINT_TO_POINT = 0x00, +} ACL_DATA_BC_FLAGS; +#define ACL_DATA_BC_FLAGS_SHIFT 14 + +/* Command pkt */ +typedef struct hci_cmd_pkt_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 params[255]; +} POSTPACK HCI_CMD_PKT; + +#define ACL_DATA_HDR_SIZE 4 /* hdl_and flags + data_len */ +/* Data pkt */ +typedef struct hci_acl_data_pkt_t { + A_UINT16 hdl_and_flags; + A_UINT16 data_len; + A_UINT8 data[Max80211_PAL_PDU_Size]; +} POSTPACK HCI_ACL_DATA_PKT; + +/* Event pkt */ +typedef struct hci_event_pkt_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 params[256]; +} POSTPACK HCI_EVENT_PKT; + + +/*============== HCI Command definitions ======================= */ +typedef struct hci_cmd_phy_link_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT8 link_key_len; + A_UINT8 link_key_type; + A_UINT8 link_key[LINK_KEY_LEN]; +} POSTPACK HCI_CMD_PHY_LINK; + +typedef struct hci_cmd_write_rem_amp_assoc_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT16 len_so_far; + A_UINT16 amp_assoc_remaining_len; + A_UINT8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ]; +} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC; + + +typedef struct hci_cmd_opcode_hdl_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 hdl; +} POSTPACK HCI_CMD_READ_LINK_QUAL, + HCI_CMD_FLUSH, + HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT; + +typedef struct hci_cmd_read_local_amp_assoc_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT16 len_so_far; + A_UINT16 max_rem_amp_assoc_len; +} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC; + + +typedef struct hci_cmd_set_event_mask_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT64 mask; +}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2; + + +typedef struct hci_cmd_enhanced_flush_t{ + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 hdl; + A_UINT8 type; +} POSTPACK HCI_CMD_ENHANCED_FLUSH; + + +typedef struct hci_cmd_write_timeout_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 timeout; +} POSTPACK HCI_CMD_WRITE_TIMEOUT; + +typedef struct hci_cmd_write_link_supervision_timeout_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 hdl; + A_UINT16 timeout; +} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT; + +typedef struct hci_cmd_write_flow_control_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 mode; +} POSTPACK HCI_CMD_WRITE_FLOW_CONTROL; + +typedef struct location_data_cfg_t { + A_UINT8 reg_domain_aware; + A_UINT8 reg_domain[3]; + A_UINT8 reg_options; +} POSTPACK LOCATION_DATA_CFG; + +typedef struct hci_cmd_write_location_data_t { + A_UINT16 opcode; + A_UINT8 param_length; + LOCATION_DATA_CFG cfg; +} POSTPACK HCI_CMD_WRITE_LOCATION_DATA; + + +typedef struct flow_spec_t { + A_UINT8 id; + A_UINT8 service_type; + A_UINT16 max_sdu; + A_UINT32 sdu_inter_arrival_time; + A_UINT32 access_latency; + A_UINT32 flush_timeout; +} POSTPACK FLOW_SPEC; + + +typedef struct hci_cmd_create_logical_link_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + FLOW_SPEC tx_flow_spec; + FLOW_SPEC rx_flow_spec; +} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK; + +typedef struct hci_cmd_flow_spec_modify_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 hdl; + FLOW_SPEC tx_flow_spec; + FLOW_SPEC rx_flow_spec; +} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY; + +typedef struct hci_cmd_logical_link_cancel_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT8 tx_flow_spec_id; +} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL; + +typedef struct hci_cmd_disconnect_logical_link_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT16 logical_link_hdl; +} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK; + +typedef struct hci_cmd_disconnect_phy_link_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; +} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK; + +typedef struct hci_cmd_srm_t { + A_UINT16 opcode; + A_UINT8 param_length; + A_UINT8 phy_link_hdl; + A_UINT8 mode; +} POSTPACK HCI_CMD_SHORT_RANGE_MODE; +/*============== HCI Command definitions end ======================= */ + + + +/*============== HCI Event definitions ============================= */ + +/* Command complete event */ +typedef struct hci_event_cmd_complete_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 num_hci_cmd_pkts; + A_UINT16 opcode; + A_UINT8 params[255]; +} POSTPACK HCI_EVENT_CMD_COMPLETE; + + +/* Command status event */ +typedef struct hci_event_cmd_status_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 num_hci_cmd_pkts; + A_UINT16 opcode; +} POSTPACK HCI_EVENT_CMD_STATUS; + +/* Hardware Error event */ +typedef struct hci_event_hw_err_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 hw_err_code; +} POSTPACK HCI_EVENT_HW_ERR; + +/* Flush occured event */ +/* Qos Violation event */ +typedef struct hci_event_handle_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT16 handle; +} POSTPACK HCI_EVENT_FLUSH_OCCRD, + HCI_EVENT_QOS_VIOLATION; + +/* Loopback command event */ +typedef struct hci_loopback_cmd_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 params[252]; +} POSTPACK HCI_EVENT_LOOPBACK_CMD; + +/* Data buffer overflow event */ +typedef struct hci_data_buf_overflow_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 link_type; +} POSTPACK HCI_EVENT_DATA_BUF_OVERFLOW; + +/* Enhanced Flush complete event */ +typedef struct hci_enhanced_flush_complt_t{ + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT16 hdl; +} POSTPACK HCI_EVENT_ENHANCED_FLUSH_COMPLT; + +/* Channel select event */ +typedef struct hci_event_chan_select_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 phy_link_hdl; +} POSTPACK HCI_EVENT_CHAN_SELECT; + +/* Physical Link Complete event */ +typedef struct hci_event_phy_link_complete_event_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 phy_link_hdl; +} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE; + +/* Logical Link complete event */ +typedef struct hci_event_logical_link_complete_event_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT16 logical_link_hdl; + A_UINT8 phy_hdl; + A_UINT8 tx_flow_id; +} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT; + +/* Disconnect Logical Link complete event */ +typedef struct hci_event_disconnect_logical_link_event_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT16 logical_link_hdl; + A_UINT8 reason; +} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT; + +/* Disconnect Physical Link complete event */ +typedef struct hci_event_disconnect_phy_link_complete_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 phy_link_hdl; + A_UINT8 reason; +} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE; + +typedef struct hci_event_physical_link_loss_early_warning_t{ + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 phy_hdl; + A_UINT8 reason; +} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING; + +typedef struct hci_event_physical_link_recovery_t{ + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 phy_hdl; +} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY; + + +/* Flow spec modify complete event */ +/* Flush event */ +typedef struct hci_event_status_handle_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT16 handle; +} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY, + HCI_EVENT_FLUSH; + + +/* Num of completed data blocks event */ +typedef struct hci_event_num_of_compl_data_blks_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT16 num_data_blks; + A_UINT8 num_handles; + A_UINT8 params[255]; +} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS; + +/* Short range mode change complete event */ +typedef struct hci_srm_cmpl_t { + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 phy_link; + A_UINT8 state; +} POSTPACK HCI_EVENT_SRM_COMPL; + +typedef struct hci_event_amp_status_change_t{ + A_UINT8 event_code; + A_UINT8 param_len; + A_UINT8 status; + A_UINT8 amp_status; +} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE; + +/*============== Event definitions end =========================== */ + + +typedef struct local_amp_info_resp_t { + A_UINT8 status; + A_UINT8 amp_status; + A_UINT32 total_bw; /* kbps */ + A_UINT32 max_guranteed_bw; /* kbps */ + A_UINT32 min_latency; + A_UINT32 max_pdu_size; + A_UINT8 amp_type; + A_UINT16 pal_capabilities; + A_UINT16 amp_assoc_len; + A_UINT32 max_flush_timeout; /* in ms */ + A_UINT32 be_flush_timeout; /* in ms */ +} POSTPACK LOCAL_AMP_INFO; + +typedef struct amp_assoc_cmd_resp_t{ + A_UINT8 status; + A_UINT8 phy_hdl; + A_UINT16 amp_assoc_len; + A_UINT8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ]; +}POSTPACK AMP_ASSOC_CMD_RESP; + + +enum PAL_HCI_CMD_STATUS { + PAL_HCI_CMD_PROCESSED, + PAL_HCI_CMD_IGNORED +}; + + +/*============= HCI Error Codes =======================*/ +#define HCI_SUCCESS 0x00 +#define HCI_ERR_UNKNOW_CMD 0x01 +#define HCI_ERR_UNKNOWN_CONN_ID 0x02 +#define HCI_ERR_HW_FAILURE 0x03 +#define HCI_ERR_PAGE_TIMEOUT 0x04 +#define HCI_ERR_AUTH_FAILURE 0x05 +#define HCI_ERR_KEY_MISSING 0x06 +#define HCI_ERR_MEM_CAP_EXECED 0x07 +#define HCI_ERR_CON_TIMEOUT 0x08 +#define HCI_ERR_CON_LIMIT_EXECED 0x09 +#define HCI_ERR_ACL_CONN_ALRDY_EXISTS 0x0B +#define HCI_ERR_COMMAND_DISALLOWED 0x0C +#define HCI_ERR_CONN_REJ_BY_LIMIT_RES 0x0D +#define HCI_ERR_CONN_REJ_BY_SEC 0x0E +#define HCI_ERR_CONN_REJ_BY_BAD_ADDR 0x0F +#define HCI_ERR_CONN_ACCPT_TIMEOUT 0x10 +#define HCI_ERR_UNSUPPORT_FEATURE 0x11 +#define HCI_ERR_INVALID_HCI_CMD_PARAMS 0x12 +#define HCI_ERR_REMOTE_USER_TERMINATE_CONN 0x13 +#define HCI_ERR_CON_TERM_BY_HOST 0x16 +#define HCI_ERR_UNSPECIFIED_ERROR 0x1F +#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT 0x25 +#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT 0x27 +#define HCI_ERR_QOS_UNACCEPTABLE_PARM 0x2C +#define HCI_ERR_QOS_REJECTED 0x2D +#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN 0x39 + +/*============= HCI Error Codes End =======================*/ + + +/* Following are event return parameters.. part of HCI events + */ +typedef struct timeout_read_t { + A_UINT8 status; + A_UINT16 timeout; +}POSTPACK TIMEOUT_INFO; + +typedef struct link_supervision_timeout_read_t { + A_UINT8 status; + A_UINT16 hdl; + A_UINT16 timeout; +}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO; + +typedef struct status_hdl_t { + A_UINT8 status; + A_UINT16 hdl; +}POSTPACK INFO_STATUS_HDL; + +typedef struct write_remote_amp_assoc_t{ + A_UINT8 status; + A_UINT8 hdl; +}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO; + +typedef struct read_loc_info_t { + A_UINT8 status; + LOCATION_DATA_CFG loc; +}POSTPACK READ_LOC_INFO; + +typedef struct read_flow_ctrl_mode_t { + A_UINT8 status; + A_UINT8 mode; +}POSTPACK READ_FLWCTRL_INFO; + +typedef struct read_data_blk_size_t { + A_UINT8 status; + A_UINT16 max_acl_data_pkt_len; + A_UINT16 data_block_len; + A_UINT16 total_num_data_blks; +}POSTPACK READ_DATA_BLK_SIZE_INFO; + +/* Read Link quality info */ +typedef struct link_qual_t { + A_UINT8 status; + A_UINT16 hdl; + A_UINT8 link_qual; +} POSTPACK READ_LINK_QUAL_INFO, + READ_RSSI_INFO; + +typedef struct ll_cancel_resp_t { + A_UINT8 status; + A_UINT8 phy_link_hdl; + A_UINT8 tx_flow_spec_id; +} POSTPACK LL_CANCEL_RESP; + +typedef struct read_local_ver_info_t { + A_UINT8 status; + A_UINT8 hci_version; + A_UINT16 hci_revision; + A_UINT8 pal_version; + A_UINT16 manf_name; + A_UINT16 pal_sub_ver; +} POSTPACK READ_LOCAL_VER_INFO; + + +#endif /* __A_HCI_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/a_osapi.h b/drivers/net/wireless/ath6kl/include/a_osapi.h new file mode 100644 index 000000000000..17138cec2f77 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/a_osapi.h @@ -0,0 +1,53 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_OSAPI_H_ +#define _A_OSAPI_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/osapi_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/include/osapi.h" +#include "../os/windows/include/netbuf.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/windows/include/osapi.h" +#include "../os/windows/include/netbuf.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/osapi_rexos.h" +#endif + +#if defined ART_WIN +#include "../os/win_art/include/osapi_win.h" +#include "../os/win_art/include/netbuf.h" +#endif + +#ifdef WIN_NWF +#include +#endif + +#endif /* _OSAPI_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/a_types.h b/drivers/net/wireless/ath6kl/include/a_types.h new file mode 100644 index 000000000000..bf4f1a485b45 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/a_types.h @@ -0,0 +1,50 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions of the basic atheros data types. +// It is used to map the data types in atheros files to a platform specific +// type. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _A_TYPES_H_ +#define _A_TYPES_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/athtypes_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/include/athtypes.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/windows/include/athtypes.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/athtypes_rexos.h" +#endif + +#if defined ART_WIN +#include "../os/win_art/include/athtypes_win.h" +#endif + +#ifdef WIN_NWF +#include +#endif + +#endif /* _ATHTYPES_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/aggr_recv_api.h b/drivers/net/wireless/ath6kl/include/aggr_recv_api.h new file mode 100644 index 000000000000..185354eddcde --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/aggr_recv_api.h @@ -0,0 +1,136 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef __AGGR_RECV_API_H__ +#define __AGGR_RECV_API_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (* RX_CALLBACK)(void * dev, void *osbuf); + +typedef void (* ALLOC_NETBUFS)(A_NETBUF_QUEUE_T *q, A_UINT16 num); + +/* + * aggr_init: + * Initialises the data structures, allocates data queues and + * os buffers. Netbuf allocator is the input param, used by the + * aggr module for allocation of NETBUFs from driver context. + * These NETBUFs are used for AMSDU processing. + * Returns the context for the aggr module. + */ +void * +aggr_init(ALLOC_NETBUFS netbuf_allocator); + + +/* + * aggr_register_rx_dispatcher: + * Registers OS call back function to deliver the + * frames to OS. This is generally the topmost layer of + * the driver context, after which the frames go to + * IP stack via the call back function. + * This dispatcher is active only when aggregation is ON. + */ +void +aggr_register_rx_dispatcher(void *cntxt, void * dev, RX_CALLBACK fn); + + +/* + * aggr_process_bar: + * When target receives BAR, it communicates to host driver + * for modifying window parameters. Target indicates this via the + * event: WMI_ADDBA_REQ_EVENTID. Host will dequeue all frames + * up to the indicated sequence number. + */ +void +aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no); + + +/* + * aggr_recv_addba_req_evt: + * This event is to initiate/modify the receive side window. + * Target will send WMI_ADDBA_REQ_EVENTID event to host - to setup + * recv re-ordering queues. Target will negotiate ADDBA with peer, + * and indicate via this event after succesfully completing the + * negotiation. This happens in two situations: + * 1. Initial setup of aggregation + * 2. Renegotiation of current recv window. + * Window size for re-ordering is limited by target buffer + * space, which is reflected in win_sz. + * (Re)Start the periodic timer to deliver long standing frames, + * in hold_q to OS. + */ +void +aggr_recv_addba_req_evt(void * cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz); + + +/* + * aggr_recv_delba_req_evt: + * Target indicates deletion of a BA window for a tid via the + * WMI_DELBA_EVENTID. Host would deliver all the frames in the + * hold_q, reset tid config and disable the periodic timer, if + * aggr is not enabled on any tid. + */ +void +aggr_recv_delba_req_evt(void * cntxt, A_UINT8 tid); + + + +/* + * aggr_process_recv_frm: + * Called only for data frames. When aggr is ON for a tid, the buffer + * is always consumed, and osbuf would be NULL. For a non-aggr case, + * osbuf is not modified. + * AMSDU frames are consumed and are later freed. They are sliced and + * diced to individual frames and dispatched to stack. + * After consuming a osbuf(when aggr is ON), a previously registered + * callback may be called to deliver frames in order. + */ +void +aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf); + + +/* + * aggr_module_destroy: + * Frees up all the queues and frames in them. Releases the cntxt to OS. + */ +void +aggr_module_destroy(void *cntxt); + +/* + * Dumps the aggregation stats + */ +void +aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf); + +/* + * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate + * hold Q state. Examples include when a Connect event or disconnect event is + * received. + */ +void +aggr_reset_state(void *cntxt); + + +#ifdef __cplusplus +} +#endif + +#endif /*__AGGR_RECV_API_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/ar3kconfig.h b/drivers/net/wireless/ath6kl/include/ar3kconfig.h new file mode 100644 index 000000000000..8d7bf2a6ec75 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/ar3kconfig.h @@ -0,0 +1,58 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* AR3K module configuration APIs for HCI-bridge operation */ + +#ifndef AR3KCONFIG_H_ +#define AR3KCONFIG_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT (1 << 0) +#define AR3K_CONFIG_FLAG_SET_AR3K_BAUD (1 << 1) +#define AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY (1 << 2) +#define AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP (1 << 3) + + +typedef struct { + A_UINT32 Flags; /* config flags */ + void *pHCIDev; /* HCI bridge device */ + HCI_TRANSPORT_PROPERTIES *pHCIProps; /* HCI bridge props */ + HIF_DEVICE *pHIFDevice; /* HIF layer device */ + + A_UINT32 AR3KBaudRate; /* AR3K operational baud rate */ + A_UINT16 AR6KScale; /* AR6K UART scale value */ + A_UINT16 AR6KStep; /* AR6K UART step value */ + struct hci_dev *pBtStackHCIDev; /* BT Stack HCI dev */ +} AR3K_CONFIG_INFO; + +A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfigInfo); + +A_STATUS AR3KConfigureExit(void *config); + +#ifdef __cplusplus +} +#endif + +#endif /*AR3KCONFIG_H_*/ diff --git a/drivers/net/wireless/ath6kl/include/ar6000_api.h b/drivers/net/wireless/ath6kl/include/ar6000_api.h new file mode 100644 index 000000000000..431520fb0b1c --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/ar6000_api.h @@ -0,0 +1,50 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API to access the OS dependent atheros host driver +// by the WMI or WLAN generic modules. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _AR6000_API_H_ +#define _AR6000_API_H_ + +#if defined(__linux__) && !defined(LINUX_EMULATION) +#include "../os/linux/include/ar6xapi_linux.h" +#endif + +#ifdef UNDER_NWIFI +#include "../os/windows/include/ar6xapi.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/windows/include/ar6xapi.h" +#endif + +#ifdef REXOS +#include "../os/rexos/include/common/ar6xapi_rexos.h" +#endif + +#if defined ART_WIN +#include "../os/win_art/include/ar6xapi_win.h" +#endif + +#ifdef WIN_NWF +#include "../os/windows/include/ar6xapi.h" +#endif + +#endif /* _AR6000_API_H */ + diff --git a/drivers/net/wireless/ath6kl/include/ar6000_diag.h b/drivers/net/wireless/ath6kl/include/ar6000_diag.h new file mode 100644 index 000000000000..ae87e2b23b6e --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/ar6000_diag.h @@ -0,0 +1,44 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef AR6000_DIAG_H_ +#define AR6000_DIAG_H_ + + +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length); + +A_STATUS +ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval); + +void +ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs); + +#endif /*AR6000_DIAG_H_*/ diff --git a/drivers/net/wireless/ath6kl/include/ar6kap_common.h b/drivers/net/wireless/ath6kl/include/ar6kap_common.h new file mode 100644 index 000000000000..87b183c45bf5 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/ar6kap_common.h @@ -0,0 +1,40 @@ +//------------------------------------------------------------------------------ + +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ + +//============================================================================== + +// This file contains the definitions of common AP mode data structures. +// +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _AR6KAP_COMMON_H_ +#define _AR6KAP_COMMON_H_ +/* + * Used with AR6000_XIOCTL_AP_GET_STA_LIST + */ +typedef struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 aid; + A_UINT8 keymgmt; + A_UINT8 ucipher; + A_UINT8 auth; +} station_t; +typedef struct { + station_t sta[AP_MAX_NUM_STA]; +} ap_get_sta_t; +#endif /* _AR6KAP_COMMON_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/athbtfilter.h b/drivers/net/wireless/ath6kl/include/athbtfilter.h new file mode 100644 index 000000000000..4ea3fa5b2f5d --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/athbtfilter.h @@ -0,0 +1,129 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Public Bluetooth filter APIs +// Author(s): ="Atheros" +//============================================================================== +#ifndef ATHBTFILTER_H_ +#define ATHBTFILTER_H_ + + +typedef enum _ATHBT_HCI_CTRL_TYPE { + ATHBT_HCI_COMMAND = 0, + ATHBT_HCI_EVENT = 1, +} ATHBT_HCI_CTRL_TYPE; + +typedef enum _ATHBT_STATE_INDICATION { + ATH_BT_NOOP = 0, + ATH_BT_INQUIRY = 1, + ATH_BT_CONNECT = 2, + ATH_BT_SCO = 3, + ATH_BT_ACL = 4, + ATH_BT_A2DP = 5, + ATH_BT_ESCO = 6, + /* new states go here.. */ + + ATH_BT_MAX_STATE_INDICATION +} ATHBT_STATE_INDICATION; + + /* filter function for OUTGOING commands and INCOMMING events */ +typedef void (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length); + + /* filter function for OUTGOING data HCI packets */ +typedef void (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length); + +typedef enum _ATHBT_STATE { + STATE_OFF = 0, + STATE_ON = 1, + STATE_MAX +} ATHBT_STATE; + + /* BT state indication (when filter functions are not used) */ + +typedef void (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion); + +typedef struct _ATHBT_FILTER_INSTANCE { +#ifdef UNDER_CE + WCHAR *pWlanAdapterName; /* filled in by user */ +#else + A_CHAR *pWlanAdapterName; /* filled in by user */ +#endif /* UNDER_CE */ + int FilterEnabled; /* filtering is enabled */ + int Attached; /* filter library is attached */ + void *pContext; /* private context for filter library */ + ATHBT_FILTER_CMD_EVENTS_FN pFilterCmdEvents; /* function ptr to filter a command or event */ + ATHBT_FILTER_DATA_FN pFilterAclDataOut; /* function ptr to filter ACL data out (to radio) */ + ATHBT_FILTER_DATA_FN pFilterAclDataIn; /* function ptr to filter ACL data in (from radio) */ + ATHBT_INDICATE_STATE_FN pIndicateState; /* function ptr to indicate a state */ +} ATH_BT_FILTER_INSTANCE; + + +/* API MACROS */ + +#define AthBtFilterHciCommand(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterCmdEvents((instance)->pContext, \ + ATHBT_HCI_COMMAND, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciEvent(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterCmdEvents((instance)->pContext, \ + ATHBT_HCI_EVENT, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciAclDataOut(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterAclDataOut((instance)->pContext, \ + (unsigned char *)(packet), \ + (length)); \ + } + +#define AthBtFilterHciAclDataIn(instance,packet,length) \ + if ((instance)->FilterEnabled) { \ + (instance)->pFilterAclDataIn((instance)->pContext, \ + (unsigned char *)(packet), \ + (length)); \ + } + +/* if filtering is not desired, the application can indicate the state directly using this + * macro: + */ +#define AthBtIndicateState(instance,indication,state) \ + if ((instance)->FilterEnabled) { \ + (instance)->pIndicateState((instance)->pContext, \ + (indication), \ + (state), \ + 0); \ + } + +#ifdef __cplusplus +extern "C" { +#endif + +/* API prototypes */ +int AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance, A_UINT32 flags); +void AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance); + +#ifdef __cplusplus +} +#endif + +#endif /*ATHBTFILTER_H_*/ diff --git a/drivers/net/wireless/ath6kl/include/athdefs.h b/drivers/net/wireless/ath6kl/include/athdefs.h new file mode 100644 index 000000000000..cc8bb3cc81be --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/athdefs.h @@ -0,0 +1,80 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum { + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results la +ter (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED /* Object was consumed */ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#endif /* __ATHDEFS_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/athendpack.h b/drivers/net/wireless/ath6kl/include/athendpack.h new file mode 100644 index 000000000000..b0c7e1425f74 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/athendpack.h @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// end compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athendpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + + +#ifdef UNDER_NWIFI +#include "../os/windows/include/athendpack.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/windows/include/athendpack.h" +#endif /* WINCE */ + +#ifdef WIN_NWF +#include +#endif diff --git a/drivers/net/wireless/ath6kl/include/athstartpack.h b/drivers/net/wireless/ath6kl/include/athstartpack.h new file mode 100644 index 000000000000..04b3cc240b35 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/athstartpack.h @@ -0,0 +1,47 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// start compiler-specific structure packing +// +// Author(s): ="Atheros" +//============================================================================== +#ifdef VXWORKS +#endif /* VXWORKS */ + +#if defined(LINUX) || defined(__linux__) +#endif /* LINUX */ + +#ifdef QNX +#endif /* QNX */ + +#ifdef INTEGRITY +#include "integrity/athstartpack_integrity.h" +#endif /* INTEGRITY */ + +#ifdef NUCLEUS +#endif /* NUCLEUS */ + +#ifdef UNDER_NWIFI +#include "../os/windows/include/athstartpack.h" +#endif + +#ifdef ATHR_CE_LEGACY +#include "../os/windows/include/athstartpack.h" +#endif /* WINCE */ + +#ifdef WIN_NWF +#include +#endif diff --git a/drivers/net/wireless/ath6kl/include/bmi.h b/drivers/net/wireless/ath6kl/include/bmi.h new file mode 100644 index 000000000000..64e817ed6929 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/bmi.h @@ -0,0 +1,128 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// BMI declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _BMI_H_ +#define _BMI_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "hif.h" +#include "a_osapi.h" +#include "bmi_msg.h" + +void +BMIInit(void); + +A_STATUS +BMIDone(HIF_DEVICE *device); + +A_STATUS +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info); + +A_STATUS +BMIReadMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIWriteMemory(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIExecute(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMISetAppStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMIReadSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 *param); + +A_STATUS +BMIWriteSOCRegister(HIF_DEVICE *device, + A_UINT32 address, + A_UINT32 param); + +A_STATUS +BMIrompatchInstall(HIF_DEVICE *device, + A_UINT32 ROM_addr, + A_UINT32 RAM_addr, + A_UINT32 nbytes, + A_UINT32 do_activate, + A_UINT32 *patch_id); + +A_STATUS +BMIrompatchUninstall(HIF_DEVICE *device, + A_UINT32 rompatch_id); + +A_STATUS +BMIrompatchActivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMIrompatchDeactivate(HIF_DEVICE *device, + A_UINT32 rompatch_count, + A_UINT32 *rompatch_list); + +A_STATUS +BMILZStreamStart(HIF_DEVICE *device, + A_UINT32 address); + +A_STATUS +BMILZData(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIFastDownload(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIRawWrite(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length); + +A_STATUS +BMIRawRead(HIF_DEVICE *device, + A_UCHAR *buffer, + A_UINT32 length, + A_BOOL want_timeout); + +#ifdef __cplusplus +} +#endif + +#endif /* _BMI_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/bmi_msg.h b/drivers/net/wireless/ath6kl/include/bmi_msg.h new file mode 100644 index 000000000000..1f48389f9664 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/bmi_msg.h @@ -0,0 +1,231 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __BMI_MSG_H__ +#define __BMI_MSG_H__ + +/* + * Bootloader Messaging Interface (BMI) + * + * BMI is a very simple messaging interface used during initialization + * to read memory, write memory, execute code, and to define an + * application entry PC. + * + * It is used to download an application to AR6K, to provide + * patches to code that is already resident on AR6K, and generally + * to examine and modify state. The Host has an opportunity to use + * BMI only once during bootup. Once the Host issues a BMI_DONE + * command, this opportunity ends. + * + * The Host writes BMI requests to mailbox0, and reads BMI responses + * from mailbox0. BMI requests all begin with a command + * (see below for specific commands), and are followed by + * command-specific data. + * + * Flow control: + * The Host can only issue a command once the Target gives it a + * "BMI Command Credit", using AR6K Counter #4. As soon as the + * Target has completed a command, it issues another BMI Command + * Credit (so the Host can issue the next command). + * + * BMI handles all required Target-side cache flushing. + */ + + +/* Maximum data size used for BMI transfers */ +#define BMI_DATASZ_MAX 256 + +/* BMI Commands */ + +#define BMI_NO_COMMAND 0 + +#define BMI_DONE 1 + /* + * Semantics: Host is done using BMI + * Request format: + * A_UINT32 command (BMI_DONE) + * Response format: none + */ + +#define BMI_READ_MEMORY 2 + /* + * Semantics: Host reads AR6K memory + * Request format: + * A_UINT32 command (BMI_READ_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * Response format: + * A_UINT8 data[length] + */ + +#define BMI_WRITE_MEMORY 3 + /* + * Semantics: Host writes AR6K memory + * Request format: + * A_UINT32 command (BMI_WRITE_MEMORY) + * A_UINT32 address + * A_UINT32 length, at most BMI_DATASZ_MAX + * A_UINT8 data[length] + * Response format: none + */ + +#define BMI_EXECUTE 4 + /* + * Semantics: Causes AR6K to execute code + * Request format: + * A_UINT32 command (BMI_EXECUTE) + * A_UINT32 address + * A_UINT32 parameter + * Response format: + * A_UINT32 return value + */ + +#define BMI_SET_APP_START 5 + /* + * Semantics: Set Target application starting address + * Request format: + * A_UINT32 command (BMI_SET_APP_START) + * A_UINT32 address + * Response format: none + */ + +#define BMI_READ_SOC_REGISTER 6 + /* + * Semantics: Read a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_READ_REGISTER) + * A_UINT32 address + * Response format: + * A_UINT32 value + */ + +#define BMI_WRITE_SOC_REGISTER 7 + /* + * Semantics: Write a 32-bit Target SOC register. + * Request format: + * A_UINT32 command (BMI_WRITE_REGISTER) + * A_UINT32 address + * A_UINT32 value + * + * Response format: none + */ + +#define BMI_GET_TARGET_ID 8 +#define BMI_GET_TARGET_INFO 8 + /* + * Semantics: Fetch the 4-byte Target information + * Request format: + * A_UINT32 command (BMI_GET_TARGET_ID/INFO) + * Response format1 (old firmware): + * A_UINT32 TargetVersionID + * Response format2 (newer firmware): + * A_UINT32 TARGET_VERSION_SENTINAL + * struct bmi_target_info; + */ + +struct bmi_target_info { + A_UINT32 target_info_byte_count; /* size of this structure */ + A_UINT32 target_ver; /* Target Version ID */ + A_UINT32 target_type; /* Target type */ +}; +#define TARGET_VERSION_SENTINAL 0xffffffff +#define TARGET_TYPE_AR6001 1 +#define TARGET_TYPE_AR6002 2 +#define TARGET_TYPE_AR6003 3 + + +#define BMI_ROMPATCH_INSTALL 9 + /* + * Semantics: Install a ROM Patch. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_INSTALL) + * A_UINT32 Target ROM Address + * A_UINT32 Target RAM Address or Value (depending on Target Type) + * A_UINT32 Size, in bytes + * A_UINT32 Activate? 1-->activate; + * 0-->install but do not activate + * Response format: + * A_UINT32 PatchID + */ + +#define BMI_ROMPATCH_UNINSTALL 10 + /* + * Semantics: Uninstall a previously-installed ROM Patch, + * automatically deactivating, if necessary. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_UNINSTALL) + * A_UINT32 PatchID + * + * Response format: none + */ + +#define BMI_ROMPATCH_ACTIVATE 11 + /* + * Semantics: Activate a list of previously-installed ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_ACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + +#define BMI_ROMPATCH_DEACTIVATE 12 + /* + * Semantics: Deactivate a list of active ROM Patches. + * Request format: + * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE) + * A_UINT32 rompatch_count + * A_UINT32 PatchID[rompatch_count] + * + * Response format: none + */ + + +#define BMI_LZ_STREAM_START 13 + /* + * Semantics: Begin an LZ-compressed stream of input + * which is to be uncompressed by the Target to an + * output buffer at address. The output buffer must + * be sufficiently large to hold the uncompressed + * output from the compressed input stream. This BMI + * command should be followed by a series of 1 or more + * BMI_LZ_DATA commands. + * A_UINT32 command (BMI_LZ_STREAM_START) + * A_UINT32 address + * Note: Not supported on all versions of ROM firmware. + */ + +#define BMI_LZ_DATA 14 + /* + * Semantics: Host writes AR6K memory with LZ-compressed + * data which is uncompressed by the Target. This command + * must be preceded by a BMI_LZ_STREAM_START command. A series + * of BMI_LZ_DATA commands are considered part of a single + * input stream until another BMI_LZ_STREAM_START is issued. + * Request format: + * A_UINT32 command (BMI_LZ_DATA) + * A_UINT32 length (of compressed data), + * at most BMI_DATASZ_MAX + * A_UINT8 CompressedData[length] + * Response format: none + * Note: Not supported on all versions of ROM firmware. + */ + +#endif /* __BMI_MSG_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/btcoexGpio.h b/drivers/net/wireless/ath6kl/include/btcoexGpio.h new file mode 100644 index 000000000000..8ed52a34fb1e --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/btcoexGpio.h @@ -0,0 +1,68 @@ +#ifndef BTCOEX_GPIO_H_ +#define BTCOEX_GPIO_H_ + + + +#ifdef FPGA +#define GPIO_A (15) +#define GPIO_B (16) +#define GPIO_C (17) +#define GPIO_D (18) +#define GPIO_E (19) +#define GPIO_F (21) +#define GPIO_G (21) +#else +#define GPIO_A (0) +#define GPIO_B (5) +#define GPIO_C (6) +#define GPIO_D (7) +#define GPIO_E (7) +#define GPIO_F (7) +#define GPIO_G (7) +#endif + + + + + +#define GPIO_DEBUG_WORD_1 (1< +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _CNXMGMT_H_ +#define _CNXMGMT_H_ + +typedef enum { + CM_CONNECT_WITHOUT_SCAN = 0x0001, + CM_CONNECT_ASSOC_POLICY_USER = 0x0002, + CM_CONNECT_SEND_REASSOC = 0x0004, + CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008, + CM_CONNECT_DO_WPA_OFFLOAD = 0x0010, + CM_CONNECT_DO_NOT_DEAUTH = 0x0020, +} CM_CONNECT_TYPE; + +#endif /* _CNXMGMT_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/common_drv.h b/drivers/net/wireless/ath6kl/include/common_drv.h new file mode 100644 index 000000000000..286490188605 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/common_drv.h @@ -0,0 +1,90 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2010 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef COMMON_DRV_H_ +#define COMMON_DRV_H_ + +#include "hif.h" +#include "htc_packet.h" +#include "htc_api.h" + +/* structure that is the state information for the default credit distribution callback + * drivers should instantiate (zero-init as well) this structure in their driver instance + * and pass it as a context to the HTC credit distribution functions */ +typedef struct _COMMON_CREDIT_STATE_INFO { + int TotalAvailableCredits; /* total credits in the system at startup */ + int CurrentFreeCredits; /* credits available in the pool that have not been + given out to endpoints */ + HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist; /* pointer to the lowest priority endpoint dist struct */ +} COMMON_CREDIT_STATE_INFO; + +typedef struct { + A_INT32 (*setupTransport)(void *ar); + void (*cleanupTransport)(void *ar); +} HCI_TRANSPORT_CALLBACKS; + +typedef struct { + void *netDevice; + void *hifDevice; + void *htcHandle; +} HCI_TRANSPORT_MISC_HANDLES; + +/* HTC TX packet tagging definitions */ +#define AR6K_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED +#define AR6K_DATA_PKT_TAG (AR6K_CONTROL_PKT_TAG + 1) + +#define AR6002_VERSION_REV1 0x20000086 +#define AR6002_VERSION_REV2 0x20000188 +#define AR6003_VERSION_REV1 0x300002ba +#define AR6003_VERSION_REV2 0x30000384 + +#ifdef __cplusplus +extern "C" { +#endif + +/* OS-independent APIs */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo); + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, A_UCHAR *data, A_UINT32 length); + +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, A_BOOL waitForCompletion, A_BOOL coldReset); + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType); + +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers); + +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion); + +A_STATUS ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 Flags); + +#ifdef __cplusplus +} +#endif + +#endif /*COMMON_DRV_H_*/ diff --git a/drivers/net/wireless/ath6kl/include/dbglog.h b/drivers/net/wireless/ath6kl/include/dbglog.h new file mode 100644 index 000000000000..ae05eb66c21a --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/dbglog.h @@ -0,0 +1,122 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_H_ +#define _DBGLOG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define DBGLOG_TIMESTAMP_OFFSET 0 +#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit + 8-23 of the LF0 timer */ +#define DBGLOG_DBGID_OFFSET 16 +#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */ +#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */ + +#define DBGLOG_MODULEID_OFFSET 26 +#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */ +#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */ + +/* + * Please ensure that the definition of any new module intrduced is captured + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The + * structure is required for the parser to correctly pick up the values for + * different modules. + */ +#define DBGLOG_MODULEID_START +#define DBGLOG_MODULEID_INF 0 +#define DBGLOG_MODULEID_WMI 1 +#define DBGLOG_MODULEID_MISC 2 +#define DBGLOG_MODULEID_PM 3 +#define DBGLOG_MODULEID_TXRX_MGMTBUF 4 +#define DBGLOG_MODULEID_TXRX_TXBUF 5 +#define DBGLOG_MODULEID_TXRX_RXBUF 6 +#define DBGLOG_MODULEID_WOW 7 +#define DBGLOG_MODULEID_WHAL 8 +#define DBGLOG_MODULEID_DC 9 +#define DBGLOG_MODULEID_CO 10 +#define DBGLOG_MODULEID_RO 11 +#define DBGLOG_MODULEID_CM 12 +#define DBGLOG_MODULEID_MGMT 13 +#define DBGLOG_MODULEID_TMR 14 +#define DBGLOG_MODULEID_BTCOEX 15 +#define DBGLOG_MODULEID_END + +#define DBGLOG_NUM_ARGS_OFFSET 30 +#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */ +#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */ + +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0 +#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF + +#define DBGLOG_REPORTING_ENABLED_OFFSET 16 +#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000 + +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000 + +#define DBGLOG_REPORT_SIZE_OFFSET 20 +#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000 + +#define DBGLOG_LOG_BUFFER_SIZE 1500 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90 + +struct dbglog_buf_s { + struct dbglog_buf_s *next; + A_UINT8 *buffer; + A_UINT32 bufsize; + A_UINT32 length; + A_UINT32 count; + A_UINT32 free; +}; + +struct dbglog_hdr_s { + struct dbglog_buf_s *dbuf; + A_UINT32 dropped; +}; + +struct dbglog_config_s { + A_UINT32 cfgvalid; /* Mask with valid config bits */ + union { + /* TODO: Take care of endianness */ + struct { + A_UINT32 mmask:16; /* Mask of modules with logging on */ + A_UINT32 rep:1; /* Reporting enabled or not */ + A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */ + A_UINT32 size:10; /* Report size in number of messages */ + A_UINT32 reserved:2; + } dbglog_config; + + A_UINT32 value; + } u; +}; + +#define cfgmmask u.dbglog_config.mmask +#define cfgrep u.dbglog_config.rep +#define cfgtsr u.dbglog_config.tsr +#define cfgsize u.dbglog_config.size +#define cfgvalue u.value + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/dbglog_api.h b/drivers/net/wireless/ath6kl/include/dbglog_api.h new file mode 100644 index 000000000000..4710b4c140fc --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/dbglog_api.h @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains host side debug primitives. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DBGLOG_API_H_ +#define _DBGLOG_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbglog.h" + +#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE + +#define DBGLOG_GET_DBGID(arg) \ + ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET) + +#define DBGLOG_GET_MODULEID(arg) \ + ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET) + +#define DBGLOG_GET_NUMARGS(arg) \ + ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET) + +#define DBGLOG_GET_TIMESTAMP(arg) \ + ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET) + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_API_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/dbglog_id.h b/drivers/net/wireless/ath6kl/include/dbglog_id.h new file mode 100644 index 000000000000..b5cd521a260f --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/dbglog_id.h @@ -0,0 +1,530 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DBGLOG_ID_H_ +#define _DBGLOG_ID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The nomenclature for the debug identifiers is MODULE_DESCRIPTION. + * Please ensure that the definition of any new debugid introduced is captured + * between the _DBGID_DEFINITION_START and + * _DBGID_DEFINITION_END defines. The structure is required for the + * parser to correctly pick up the values for different debug identifiers. + */ + +/* INF debug identifier definitions */ +#define INF_DBGID_DEFINITION_START +#define INF_ASSERTION_FAILED 1 +#define INF_TARGET_ID 2 +#define INF_DBGID_DEFINITION_END + +/* WMI debug identifier definitions */ +#define WMI_DBGID_DEFINITION_START +#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1 +#define WMI_EXTENDED_CMD_NOT_HANDLED 2 +#define WMI_CMD_RX_PKT_TOO_SHORT 3 +#define WMI_CALLING_WMI_EXTENSION_FN 4 +#define WMI_CMD_NOT_HANDLED 5 +#define WMI_IN_SYNC 6 +#define WMI_TARGET_WMI_SYNC_CMD 7 +#define WMI_SET_SNR_THRESHOLD_PARAMS 8 +#define WMI_SET_RSSI_THRESHOLD_PARAMS 9 +#define WMI_SET_LQ_TRESHOLD_PARAMS 10 +#define WMI_TARGET_CREATE_PSTREAM_CMD 11 +#define WMI_WI_DTM_INUSE 12 +#define WMI_TARGET_DELETE_PSTREAM_CMD 13 +#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14 +#define WMI_TARGET_GET_BIT_RATE_CMD 15 +#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16 +#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17 +#define WMI_TARGET_GET_TX_PWR_CMD 18 +#define WMI_FREE_EVBUF_WMIBUF 19 +#define WMI_FREE_EVBUF_DATABUF 20 +#define WMI_FREE_EVBUF_BADFLAG 21 +#define WMI_HTC_RX_ERROR_DATA_PACKET 22 +#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23 +#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24 +#define WMI_SENDING_READY_EVENT 25 +#define WMI_SETPOWER_MDOE_TO_MAXPERF 26 +#define WMI_SETPOWER_MDOE_TO_REC 27 +#define WMI_BSSINFO_EVENT_FROM 28 +#define WMI_TARGET_GET_STATS_CMD 29 +#define WMI_SENDING_SCAN_COMPLETE_EVENT 30 +#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31 +#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32 +#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33 +#define WMI_SENDING_ERROR_REPORT_EVENT 34 +#define WMI_SENDING_CAC_EVENT 35 +#define WMI_TARGET_GET_ROAM_TABLE_CMD 36 +#define WMI_TARGET_GET_ROAM_DATA_CMD 37 +#define WMI_SENDING_GPIO_INTR_EVENT 38 +#define WMI_SENDING_GPIO_ACK_EVENT 39 +#define WMI_SENDING_GPIO_DATA_EVENT 40 +#define WMI_CMD_RX 41 +#define WMI_CMD_RX_XTND 42 +#define WMI_EVENT_SEND 43 +#define WMI_EVENT_SEND_XTND 44 +#define WMI_CMD_PARAMS_DUMP_START 45 +#define WMI_CMD_PARAMS_DUMP_END 46 +#define WMI_CMD_PARAMS 47 +#define WMI_DBGID_DEFINITION_END + +/* MISC debug identifier definitions */ +#define MISC_DBGID_DEFINITION_START +#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR 1 +#define MISC_DBGID_DEFINITION_END + +/* TXRX debug identifier definitions */ +#define TXRX_TXBUF_DBGID_DEFINITION_START +#define TXRX_TXBUF_ALLOCATE_BUF 1 +#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2 +#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3 +#define TXRX_TXBUF_TXQ_DEPTH 4 +#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5 +#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6 +#define TXRX_TXBUF_INITIALIZE_TIMER 7 +#define TXRX_TXBUF_ARM_TIMER 8 +#define TXRX_TXBUF_DISARM_TIMER 9 +#define TXRX_TXBUF_UNINITIALIZE_TIMER 10 +#define TXRX_TXBUF_DBGID_DEFINITION_END + +#define TXRX_RXBUF_DBGID_DEFINITION_START +#define TXRX_RXBUF_ALLOCATE_BUF 1 +#define TXRX_RXBUF_QUEUE_TO_HOST 2 +#define TXRX_RXBUF_QUEUE_TO_WLAN 3 +#define TXRX_RXBUF_ZERO_LEN_BUF 4 +#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5 +#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6 +#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7 +#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8 +#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9 +#define TXRX_RXBUF_REQUEUE_ERROR 10 +#define TXRX_RXBUF_DBGID_DEFINITION_END + +#define TXRX_MGMTBUF_DBGID_DEFINITION_START +#define TXRX_MGMTBUF_ALLOCATE_BUF 1 +#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2 +#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3 +#define TXRX_MGMTBUF_GET_BUF 4 +#define TXRX_MGMTBUF_GET_SM_BUF 5 +#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6 +#define TXRX_MGMTBUF_REAPED_BUF 7 +#define TXRX_MGMTBUF_REAPED_SM_BUF 8 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10 +#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11 +#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12 +#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13 +#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14 +#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15 +#define TXRX_MGMTBUF_DRAINQ 16 +#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17 +#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18 +#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19 +#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20 +#define TXRX_MGMTBUF_RESUME_HW_TXQ 21 +#define TXRX_MGMTBUF_TEAR_DOWN_BA 22 +#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ 23 +#define TXRX_MGMTBUF_PROCESS_DELBA 24 +#define TXRX_MGMTBUF_PERFORM_BA 25 +#define TXRX_MGMTBUF_DBGID_DEFINITION_END + +/* PM (Power Module) debug identifier definitions */ +#define PM_DBGID_DEFINITION_START +#define PM_INIT 1 +#define PM_ENABLE 2 +#define PM_SET_STATE 3 +#define PM_SET_POWERMODE 4 +#define PM_CONN_NOTIFY 5 +#define PM_REF_COUNT_NEGATIVE 6 +#define PM_INFRA_STA_APSD_ENABLE 7 +#define PM_INFRA_STA_UPDATE_APSD_STATE 8 +#define PM_CHAN_OP_REQ 9 +#define PM_SET_MY_BEACON_POLICY 10 +#define PM_SET_ALL_BEACON_POLICY 11 +#define PM_INFRA_STA_SET_PM_PARAMS1 12 +#define PM_INFRA_STA_SET_PM_PARAMS2 13 +#define PM_ADHOC_SET_PM_CAPS_FAIL 14 +#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15 +#define PM_ADHOC_SET_PM_PARAMS 16 +#define PM_ADHOC_STATE1 18 +#define PM_ADHOC_STATE2 19 +#define PM_ADHOC_CONN_MAP 20 +#define PM_FAKE_SLEEP 21 +#define PM_AP_STATE1 22 +#define PM_AP_SET_PM_PARAMS 23 +#define PM_DBGID_DEFINITION_END + +/* Wake on Wireless debug identifier definitions */ +#define WOW_DBGID_DEFINITION_START +#define WOW_INIT 1 +#define WOW_GET_CONFIG_DSET 2 +#define WOW_NO_CONFIG_DSET 3 +#define WOW_INVALID_CONFIG_DSET 4 +#define WOW_USE_DEFAULT_CONFIG 5 +#define WOW_SETUP_GPIO 6 +#define WOW_INIT_DONE 7 +#define WOW_SET_GPIO_PIN 8 +#define WOW_CLEAR_GPIO_PIN 9 +#define WOW_SET_WOW_MODE_CMD 10 +#define WOW_SET_HOST_MODE_CMD 11 +#define WOW_ADD_WOW_PATTERN_CMD 12 +#define WOW_NEW_WOW_PATTERN_AT_INDEX 13 +#define WOW_DEL_WOW_PATTERN_CMD 14 +#define WOW_LIST_CONTAINS_PATTERNS 15 +#define WOW_GET_WOW_LIST_CMD 16 +#define WOW_INVALID_FILTER_ID 17 +#define WOW_INVALID_FILTER_LISTID 18 +#define WOW_NO_VALID_FILTER_AT_ID 19 +#define WOW_NO_VALID_LIST_AT_ID 20 +#define WOW_NUM_PATTERNS_EXCEEDED 21 +#define WOW_NUM_LISTS_EXCEEDED 22 +#define WOW_GET_WOW_STATS 23 +#define WOW_CLEAR_WOW_STATS 24 +#define WOW_WAKEUP_HOST 25 +#define WOW_EVENT_WAKEUP_HOST 26 +#define WOW_EVENT_DISCARD 27 +#define WOW_PATTERN_MATCH 28 +#define WOW_PATTERN_NOT_MATCH 29 +#define WOW_PATTERN_NOT_MATCH_OFFSET 30 +#define WOW_DISABLED_HOST_ASLEEP 31 +#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32 +#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33 +#define WOW_DBGID_DEFINITION_END + +/* WHAL debug identifier definitions */ +#define WHAL_DBGID_DEFINITION_START +#define WHAL_ERROR_ANI_CONTROL 1 +#define WHAL_ERROR_CHIP_TEST1 2 +#define WHAL_ERROR_CHIP_TEST2 3 +#define WHAL_ERROR_EEPROM_CHECKSUM 4 +#define WHAL_ERROR_EEPROM_MACADDR 5 +#define WHAL_ERROR_INTERRUPT_HIU 6 +#define WHAL_ERROR_KEYCACHE_RESET 7 +#define WHAL_ERROR_KEYCACHE_SET 8 +#define WHAL_ERROR_KEYCACHE_TYPE 9 +#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10 +#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11 +#define WHAL_ERROR_PHY_INVALID_CHANNEL 12 +#define WHAL_ERROR_POWER_AWAKE 13 +#define WHAL_ERROR_POWER_SET 14 +#define WHAL_ERROR_RECV_STOPDMA 15 +#define WHAL_ERROR_RECV_STOPPCU 16 +#define WHAL_ERROR_RESET_CHANNF1 17 +#define WHAL_ERROR_RESET_CHANNF2 18 +#define WHAL_ERROR_RESET_PM 19 +#define WHAL_ERROR_RESET_OFFSETCAL 20 +#define WHAL_ERROR_RESET_RFGRANT 21 +#define WHAL_ERROR_RESET_RXFRAME 22 +#define WHAL_ERROR_RESET_STOPDMA 23 +#define WHAL_ERROR_RESET_RECOVER 24 +#define WHAL_ERROR_XMIT_COMPUTE 25 +#define WHAL_ERROR_XMIT_NOQUEUE 26 +#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27 +#define WHAL_ERROR_XMIT_BADTYPE 28 +#define WHAL_ERROR_XMIT_STOPDMA 29 +#define WHAL_ERROR_INTERRUPT_BB_PANIC 30 +#define WHAL_ERROR_RESET_TXIQCAL 31 +#define WHAL_DBGID_DEFINITION_END + +/* DC debug identifier definitions */ +#define DC_DBGID_DEFINITION_START +#define DC_SCAN_CHAN_START 1 +#define DC_SCAN_CHAN_FINISH 2 +#define DC_BEACON_RECEIVE7 3 +#define DC_SSID_PROBE_CB 4 +#define DC_SEND_NEXT_SSID_PROBE 5 +#define DC_START_SEARCH 6 +#define DC_CANCEL_SEARCH_CB 7 +#define DC_STOP_SEARCH 8 +#define DC_END_SEARCH 9 +#define DC_MIN_CHDWELL_TIMEOUT 10 +#define DC_START_SEARCH_CANCELED 11 +#define DC_SET_POWER_MODE 12 +#define DC_INIT 13 +#define DC_SEARCH_OPPORTUNITY 14 +#define DC_RECEIVED_ANY_BEACON 15 +#define DC_RECEIVED_MY_BEACON 16 +#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17 +#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18 +#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19 +#define DC_SET_BEACON_UPDATE 20 +#define DC_BEACON_UPDATE_COMPLETE 21 +#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22 +#define DC_BSSINFO_EVENT_DROPPED 23 +#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT 24 +#define DC_DBGID_DEFINITION_END + +/* CO debug identifier definitions */ +#define CO_DBGID_DEFINITION_START +#define CO_INIT 1 +#define CO_ACQUIRE_LOCK 2 +#define CO_START_OP1 3 +#define CO_START_OP2 4 +#define CO_DRAIN_TX_COMPLETE_CB 5 +#define CO_CHANGE_CHANNEL_CB 6 +#define CO_RETURN_TO_HOME_CHANNEL 7 +#define CO_FINISH_OP_TIMEOUT 8 +#define CO_OP_END 9 +#define CO_CANCEL_OP 10 +#define CO_CHANGE_CHANNEL 11 +#define CO_RELEASE_LOCK 12 +#define CO_CHANGE_STATE 13 +#define CO_DBGID_DEFINITION_END + +/* RO debug identifier definitions */ +#define RO_DBGID_DEFINITION_START +#define RO_REFRESH_ROAM_TABLE 1 +#define RO_UPDATE_ROAM_CANDIDATE 2 +#define RO_UPDATE_ROAM_CANDIDATE_CB 3 +#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4 +#define RO_REFRESH_ROAM_TABLE_DONE 5 +#define RO_PERIODIC_SEARCH_CB 6 +#define RO_PERIODIC_SEARCH_TIMEOUT 7 +#define RO_INIT 8 +#define RO_BMISS_STATE1 9 +#define RO_BMISS_STATE2 10 +#define RO_SET_PERIODIC_SEARCH_ENABLE 11 +#define RO_SET_PERIODIC_SEARCH_DISABLE 12 +#define RO_ENABLE_SQ_THRESHOLD 13 +#define RO_DISABLE_SQ_THRESHOLD 14 +#define RO_ADD_BSS_TO_ROAM_TABLE 15 +#define RO_SET_PERIODIC_SEARCH_MODE 16 +#define RO_CONFIGURE_SQ_THRESHOLD1 17 +#define RO_CONFIGURE_SQ_THRESHOLD2 18 +#define RO_CONFIGURE_SQ_PARAMS 19 +#define RO_LOW_SIGNAL_QUALITY_EVENT 20 +#define RO_HIGH_SIGNAL_QUALITY_EVENT 21 +#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22 +#define RO_UPDATE_CONNECTION_STATE_METRIC 23 +#define RO_DBGID_DEFINITION_END + +/* CM debug identifier definitions */ +#define CM_DBGID_DEFINITION_START +#define CM_INITIATE_HANDOFF 1 +#define CM_INITIATE_HANDOFF_CB 2 +#define CM_CONNECT_EVENT 3 +#define CM_DISCONNECT_EVENT 4 +#define CM_INIT 5 +#define CM_HANDOFF_SOURCE 6 +#define CM_SET_HANDOFF_TRIGGERS 7 +#define CM_CONNECT_REQUEST 8 +#define CM_CONNECT_REQUEST_CB 9 +#define CM_CONTINUE_SCAN_CB 10 +#define CM_DBGID_DEFINITION_END + + +/* mgmt debug identifier definitions */ +#define MGMT_DBGID_DEFINITION_START +#define KEYMGMT_CONNECTION_INIT 1 +#define KEYMGMT_CONNECTION_COMPLETE 2 +#define KEYMGMT_CONNECTION_CLOSE 3 +#define KEYMGMT_ADD_KEY 4 +#define MLME_NEW_STATE 5 +#define MLME_CONN_INIT 6 +#define MLME_CONN_COMPLETE 7 +#define MLME_CONN_CLOSE 8 +#define MGMT_DBGID_DEFINITION_END + +/* TMR debug identifier definitions */ +#define TMR_DBGID_DEFINITION_START +#define TMR_HANG_DETECTED 1 +#define TMR_WDT_TRIGGERED 2 +#define TMR_WDT_RESET 3 +#define TMR_HANDLER_ENTRY 4 +#define TMR_HANDLER_EXIT 5 +#define TMR_SAVED_START 6 +#define TMR_SAVED_END 7 +#define TMR_DBGID_DEFINITION_END + +/* BTCOEX debug identifier definitions */ +#define BTCOEX_DBGID_DEFINITION_START +#define BTCOEX_STATUS_CMD 1 +#define BTCOEX_PARAMS_CMD 2 +#define BTCOEX_ANT_CONFIG 3 +#define BTCOEX_COLOCATED_BT_DEVICE 4 +#define BTCOEX_CLOSE_RANGE_SCO_ON 5 +#define BTCOEX_CLOSE_RANGE_SCO_OFF 6 +#define BTCOEX_CLOSE_RANGE_A2DP_ON 7 +#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8 +#define BTCOEX_A2DP_PROTECT_ON 9 +#define BTCOEX_A2DP_PROTECT_OFF 10 +#define BTCOEX_SCO_PROTECT_ON 11 +#define BTCOEX_SCO_PROTECT_OFF 12 +#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13 +#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14 +#define BTCOEX_CLOSE_RANGE_TOGGLE 15 +#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16 +#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17 +#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18 +#define BTCOEX_PTA_PRI_INTR_HANDLER 19 +#define BTCOEX_PSPOLL_QUEUED 20 +#define BTCOEX_PSPOLL_COMPLETE 21 +#define BTCOEX_DBG_PM_AWAKE 22 +#define BTCOEX_DBG_PM_SLEEP 23 +#define BTCOEX_DBG_SCO_COEX_ON 24 +#define BTCOEX_SCO_DATARECEIVE 25 +#define BTCOEX_INTR_INIT 26 +#define BTCOEX_PTA_PRI_DIFF 27 +#define BTCOEX_TIM_NOTIFICATION 28 +#define BTCOEX_SCO_WAKEUP_ON_DATA 29 +#define BTCOEX_SCO_SLEEP 30 +#define BTCOEX_SET_WEIGHTS 31 +#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL 32 +#define BTCOEX_SCO_MEASURE_TIME_DIFF 33 +#define BTCOEX_SET_EOL_VAL 34 +#define BTCOEX_OPT_DETECT_HANDLER 35 +#define BTCOEX_SCO_TOGGLE_STATE 36 +#define BTCOEX_SCO_STOMP 37 +#define BTCOEX_NULL_COMP_CALLBACK 38 +#define BTCOEX_RX_INCOMING 39 +#define BTCOEX_RX_INCOMING_CTL 40 +#define BTCOEX_RX_INCOMING_MGMT 41 +#define BTCOEX_RX_INCOMING_DATA 42 +#define BTCOEX_RTS_RECEPTION 43 +#define BTCOEX_FRAME_PRI_LOW_RATE_THRES 44 +#define BTCOEX_PM_FAKE_SLEEP 45 +#define BTCOEX_ACL_COEX_STATUS 46 +#define BTCOEX_ACL_COEX_DETECTECTION 47 +#define BTCOEX_A2DP_COEX_STATUS 48 +#define BTCOEX_SCO_STATUS 49 +#define BTCOEX_WAKEUP_ON_DATA 50 +#define BTCOEX_DATARECEIVE 51 +#define BTCOEX_GET_MAX_AGGR_SIZE 53 +#define BTCOEX_MAX_AGGR_AVAIL_TIME 54 +#define BTCOEX_DBG_WBTIMER_INTR 55 +#define BTCOEX_DBG_SCO_SYNC 57 +#define BTCOEX_UPLINK_QUEUED_RATE 59 +#define BTCOEX_DBG_UPLINK_ENABLE_EOL 60 +#define BTCOEX_UPLINK_FRAME_DURATION 61 +#define BTCOEX_UPLINK_SET_EOL 62 +#define BTCOEX_DBG_EOL_EXPIRED 63 +#define BTCOEX_DBG_DATA_COMPLETE 64 +#define BTCOEX_UPLINK_QUEUED_TIMESTAMP 65 +#define BTCOEX_DBG_DATA_COMPLETE_TIME 66 +#define BTCOEX_DBG_TX_COMP_TXQ 67 +#define BTCOEX_DBG_SCO_FL_EDGE 68 +#define BTCOEX_DBG_UPLINK_SEQ_NUM 69 +#define BTCOEX_UPLINK_AGGR_SEQ 70 +#define BTCOEX_DBG_TX_COMP_SEQ_NO 71 +#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE 72 +#define BTCOEX_DBG_ACL_TRAFFIC 73 +#define BTCOEX_CURR_AGGR_PROP 74 +#define BTCOEX_CREAT_AGGR 75 +#define BTCOEX_PSPOLL_PROCESS 76 +#define BTCOEX_RETURN_FROM_MAC 77 +#define BTCOEX_FREED_REQUEUED_CNT 78 +#define BTCOEX_DBG_TOGGLE_LOW_RATES 79 +#define BTCOEX_MAC_GOES_TO_SLEEP 80 +#define BTCOEX_DBG_A2DP_NO_SYNC 81 +#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO 82 +#define BTCOEX_RETURN_FROM_MAC_AC 83 +#define BTCOEX_CREAT_AGGR_AC 84 +#define BTCOEX_IS_PRE_UPDATE 86 +#define BTCOEX_ENQUEUED_BIT_MAP 87 +#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS 88 +#define BTCOEX_UPLINK_DESC 89 +#define BTCOEX_DBG_TXQ_DETAILS 90 +#define BTCOEX_DBG_RECV_ACK 94 +#define BTCOEX_DBG_ADDBA_INDICATION 95 +#define BTCOEX_TX_COMPLETE_EOL_FAILED 96 +#define BTCOEX_DBG_A2DP_USAGE_COMPLETE 97 +#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER 98 +#define BTCOEX_DBG_A2DP_SYNC_INTR 99 +#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION 100 +#define BTCOEX_FORM_AGGR_CURR_AGGR 101 +#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT 102 +#define BTCOEX_DBG_BT_TRAFFIC 103 +#define BTCOEX_DBG_STOMP_BT_TRAFFIC 104 +#define BTCOEX_RECV_NULL 105 +#define BTCOEX_DBG_A2DP_MASTER_BT_END 106 +#define BTCOEX_DBG_A2DP_BT_START 107 +#define BTCOEX_DBG_A2DP_SLAVE_BT_END 108 +#define BTCOEX_DBG_A2DP_STOMP_BT 109 +#define BTCOEX_DBG_GO_TO_SLEEP 110 +#define BTCOEX_DBG_A2DP_PKT 111 +#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV 112 +#define BTCOEX_DBG_A2DP_NULL 113 +#define BTCOEX_DBG_UPLINK_DATA 114 +#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL 115 +#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT 116 +#define BTCOEX_DBG_TXQ_STATE 117 +#define BTCOEX_DBG_ALLOW_SCAN 118 +#define BTCOEX_DBG_SCAN_REQUEST 119 +#define BTCOEX_A2DP_SLEEP 127 +#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT 128 +#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE 129 +#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 130 +#define BTCOEX_DATARECEIVE_AGGR 131 +#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING 132 +#define BTCOEX_DBG_DATARESP_TIMEOUT 133 +#define BTCOEX_BDG_BMISS 134 +#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM 135 +#define BTCOEX_DBG_SECOND_BMISS 136 +#define BTCOEX_DBG_SET_WLAN_STATE 138 +#define BTCOEX_BDG_FIRST_BMISS 139 +#define BTCOEX_DBG_A2DP_CHAN_OP 140 +#define BTCOEX_DBG_A2DP_INTR 141 +#define BTCOEX_DBG_BT_INQUIRY 142 +#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH 143 +#define BTCOEX_DBG_POST_INQUIRY_FINISH 144 +#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER 145 +#define BTCOEX_DBG_NULL_FRAME_SLEEP 146 +#define BTCOEX_DBG_NULL_FRAME_AWAKE 147 +#define BTCOEX_DBG_SET_AGGR_SIZE 152 +#define BTCOEX_DBG_TEAR_BA_TIMEOUT 153 +#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO 154 +#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI 155 +#define BTCOEX_DBG_COLOCATED_BT_DEV 156 +#define BTCOEX_DBG_FE_ANT_TYPE 157 +#define BTCOEX_DBG_BT_INQUIRY_CMD 158 +#define BTCOEX_DBG_SCO_CONFIG 159 +#define BTCOEX_DBG_SCO_PSPOLL_CONFIG 160 +#define BTCOEX_DBG_SCO_OPTMODE_CONFIG 161 +#define BTCOEX_DBG_A2DP_CONFIG 162 +#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG 163 +#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG 164 +#define BTCOEX_DBG_ACLCOEX_CONFIG 165 +#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG 166 +#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG 167 +#define BTCOEX_DBG_DEBUG_CMD 168 +#define BTCOEX_DBG_SET_BT_OPERATING_STATUS 169 +#define BTCOEX_DBG_GET_CONFIG 170 +#define BTCOEX_DBG_GET_STATS 171 +#define BTCOEX_DBG_BT_OPERATING_STATUS 172 +#define BTCOEX_DBG_PERFORM_RECONNECT 173 +#define BTCOEX_DBG_ACL_WLAN_MED 175 +#define BTCOEX_DBG_ACL_BT_MED 176 +#define BTCOEX_DBG_WLAN_CONNECT 177 +#define BTCOEX_DBG_A2DP_DUAL_START 178 +#define BTCOEX_DBG_PMAWAKE_NOTIFY 179 +#define BTCOEX_DBG_BEACON_SCAN_ENABLE 180 +#define BTCOEX_DBG_BEACON_SCAN_DISABLE 181 +#define BTCOEX_DBG_RX_NOTIFY 182 +#define BTCOEX_DBGID_DEFINITION_END + +#ifdef __cplusplus +} +#endif + +#endif /* _DBGLOG_ID_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/discovery.h b/drivers/net/wireless/ath6kl/include/discovery.h new file mode 100644 index 000000000000..53791df70ab9 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/discovery.h @@ -0,0 +1,71 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _DISCOVERY_H_ +#define _DISCOVERY_H_ + +/* + * DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel + */ +typedef enum { + DEFAULT_SCPRI = 0x01, + POPULAR_SCPRI = 0x02, + SSIDS_SCPRI = 0x04, + PROF_SCPRI = 0x08, +} DC_SCAN_PRIORITY; + +/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */ +typedef enum { + SCAN_RESET = 0, + SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \ + SSIDS_SCPRI | PROF_SCPRI), + + SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI), + SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI), + SCAN_PROF_MASK = (PROF_SCPRI), + SCAN_MULTI_CHANNEL = 0x000100, + SCAN_DETERMINISTIC = 0x000200, + SCAN_PROFILE_MATCH_TERMINATED = 0x000400, + SCAN_HOME_CHANNEL_SKIP = 0x000800, + SCAN_CHANNEL_LIST_CONTINUE = 0x001000, + SCAN_CURRENT_SSID_SKIP = 0x002000, + SCAN_ACTIVE_PROBE_DISABLE = 0x004000, + SCAN_CHANNEL_HINT_ONLY = 0x008000, + SCAN_ACTIVE_CHANNELS_ONLY = 0x010000, + SCAN_UNUSED1 = 0x020000, /* unused */ + SCAN_PERIODIC = 0x040000, + SCAN_FIXED_DURATION = 0x080000, + SCAN_AP_ASSISTED = 0x100000, +} DC_SCAN_TYPE; + +typedef enum { + BSS_REPORTING_DEFAULT = 0x0, + EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */ +} DC_BSS_REPORTING_POLICY; + +typedef enum { + DC_IGNORE_WPAx_GROUP_CIPHER = 0x01, + DC_PROFILE_MATCH_DONE = 0x02, + DC_IGNORE_AAC_BEACON = 0x04, + DC_CSA_FOLLOW_BSS = 0x08, +} DC_PROFILE_FILTER; + +#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS) + +#endif /* _DISCOVERY_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/dl_list.h b/drivers/net/wireless/ath6kl/include/dl_list.h new file mode 100644 index 000000000000..f07b41d7638a --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/dl_list.h @@ -0,0 +1,149 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Double-link list definitions (adapted from Atheros SDIO stack) +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef __DL_LIST_H___ +#define __DL_LIST_H___ + +#include "a_osapi.h" + +#define A_CONTAINING_STRUCT(address, struct_type, field_name)\ + ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name))) + +/* list functions */ +/* pointers for the list */ +typedef struct _DL_LIST { + struct _DL_LIST *pPrev; + struct _DL_LIST *pNext; +}DL_LIST, *PDL_LIST; +/* + * DL_LIST_INIT , initialize doubly linked list +*/ +#define DL_LIST_INIT(pList)\ + {(pList)->pPrev = pList; (pList)->pNext = pList;} + +/* faster macro to init list and add a single item */ +#define DL_LIST_INIT_AND_ADD(pList,pItem) \ +{ (pList)->pPrev = (pItem); \ + (pList)->pNext = (pItem); \ + (pItem)->pNext = (pList); \ + (pItem)->pPrev = (pList); \ +} + +#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList))) +#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext +#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev +/* + * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member + * NOT: do not use this function if the items in the list are deleted inside the + * iteration loop +*/ +#define ITERATE_OVER_LIST(pStart, pTemp) \ + for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext) + + +/* safe iterate macro that allows the item to be removed from the list + * the iteration continues to the next item in the list + */ +#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \ +{ \ + PDL_LIST pTemp; \ + pTemp = (pStart)->pNext; \ + while (pTemp != (pStart)) { \ + (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset); \ + pTemp = pTemp->pNext; \ + +#define ITERATE_END }} + +/* + * DL_ListInsertTail - insert pAdd to the end of the list +*/ +static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at tail */ + pAdd->pPrev = pList->pPrev; + pAdd->pNext = pList; + pList->pPrev->pNext = pAdd; + pList->pPrev = pAdd; + return pAdd; +} + +/* + * DL_ListInsertHead - insert pAdd into the head of the list +*/ +static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) { + /* insert at head */ + pAdd->pPrev = pList; + pAdd->pNext = pList->pNext; + pList->pNext->pPrev = pAdd; + pList->pNext = pAdd; + return pAdd; +} + +#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem)) +/* + * DL_ListRemove - remove pDel from list +*/ +static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) { + pDel->pNext->pPrev = pDel->pPrev; + pDel->pPrev->pNext = pDel->pNext; + /* point back to itself just to be safe, incase remove is called again */ + pDel->pNext = pDel; + pDel->pPrev = pDel; + return pDel; +} + +/* + * DL_ListRemoveItemFromHead - get a list item from the head +*/ +static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) { + PDL_LIST pItem = NULL; + if (pList->pNext != pList) { + pItem = pList->pNext; + /* remove the first item from head */ + DL_ListRemove(pItem); + } + return pItem; +} + +static INLINE PDL_LIST DL_ListRemoveItemFromTail(PDL_LIST pList) { + PDL_LIST pItem = NULL; + if (pList->pPrev != pList) { + pItem = pList->pPrev; + /* remove the item from tail */ + DL_ListRemove(pItem); + } + return pItem; +} + +/* transfer src list items to the tail of the destination list */ +static INLINE void DL_ListTransferItemsToTail(PDL_LIST pDest, PDL_LIST pSrc) { + /* only concatenate if src is not empty */ + if (!DL_LIST_IS_EMPTY(pSrc)) { + /* cut out circular list in src and re-attach to end of dest */ + pSrc->pPrev->pNext = pDest; + pSrc->pNext->pPrev = pDest->pPrev; + pDest->pPrev->pNext = pSrc->pNext; + pDest->pPrev = pSrc->pPrev; + /* terminate src list, it is now empty */ + pSrc->pPrev = pSrc; + pSrc->pNext = pSrc; + } +} + +#endif /* __DL_LIST_H___ */ diff --git a/drivers/net/wireless/ath6kl/include/dset_api.h b/drivers/net/wireless/ath6kl/include/dset_api.h new file mode 100644 index 000000000000..9456df988073 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/dset_api.h @@ -0,0 +1,61 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side DataSet API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _DSET_API_H_ +#define _DSET_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Host-side DataSet support is optional, and is not + * currently required for correct operation. To disable + * Host-side DataSet support, set this to 0. + */ +#ifndef CONFIG_HOST_DSET_SUPPORT +#define CONFIG_HOST_DSET_SUPPORT 1 +#endif + +/* Called to send a DataSet Open Reply back to the Target. */ +A_STATUS wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 size, + A_UINT32 version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +/* Called to send a DataSet Data Reply back to the Target. */ +A_STATUS wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *host_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* _DSET_API_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/dset_internal.h b/drivers/net/wireless/ath6kl/include/dset_internal.h new file mode 100644 index 000000000000..474f3c273574 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/dset_internal.h @@ -0,0 +1,51 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSET_INTERNAL_H__ +#define __DSET_INTERNAL_H__ + +/* + * Internal dset definitions, common for DataSet layer. + */ + +#define DSET_TYPE_STANDARD 0 +#define DSET_TYPE_BPATCHED 1 +#define DSET_TYPE_COMPRESSED 2 + +/* Dataset descriptor */ + +typedef struct dset_descriptor_s { + struct dset_descriptor_s *next; /* List link. NULL only at the last + descriptor */ + A_UINT16 id; /* Dset ID */ + A_UINT16 size; /* Dset size. */ + void *DataPtr; /* Pointer to raw data for standard + DataSet or pointer to original + dset_descriptor for patched + DataSet */ + A_UINT32 data_type; /* DSET_TYPE_*, above */ + + void *AuxPtr; /* Additional data that might + needed for data_type. For + example, pointer to patch + Dataset descriptor for BPatch. */ +} dset_descriptor_t; + +#endif /* __DSET_INTERNAL_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/dsetid.h b/drivers/net/wireless/ath6kl/include/dsetid.h new file mode 100644 index 000000000000..fc42fd20ba83 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/dsetid.h @@ -0,0 +1,122 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + + +#ifndef __DSETID_H__ +#define __DSETID_H__ + +/* Well-known DataSet IDs */ +#define DSETID_UNUSED 0x00000000 +#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */ +#define DSETID_REGDB 0x00000002 /* Regulatory Database */ +#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */ +#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */ + +#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005 +#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025 +/* + * Get DSETID for various reference clock speeds. + * For each speed there are three DataSets that correspond + * to the three columns of bank6 data (addr, 11a, 11b/g). + * This macro returns the dsetid of the first of those + * three DataSets. + */ +#define ANALOG_CONTROL_DATA_DSETID(refclk) \ + (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk) + +/* + * There are TWO STARTUP_PATCH DataSets. + * DSETID_STARTUP_PATCH is historical, and was applied before BMI on + * earlier systems. On AR6002, it is applied after BMI, just like + * DSETID_STARTUP_PATCH2. + */ +#define DSETID_STARTUP_PATCH 0x00000026 +#define DSETID_GPIO_CONFIG_PATCH 0x00000027 +#define DSETID_WLANREGS 0x00000028 /* override wlan regs */ +#define DSETID_STARTUP_PATCH2 0x00000029 + +#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */ + +/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */ +#define DSETID_INI_DATA 0x00000100 +/* Reserved for WHAL INI Tables: 0x100..0x11f */ +#define DSETID_INI_DATA_END 0x0000011f + +#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */ + +#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the + end of a memory-based + DataSet Index */ +#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */ + +/* + * PATCH DataSet format: + * A list of patches, terminated by a patch with + * address=PATCH_END. + * + * This allows for patches to be stored in flash. + */ +struct patch_s { + A_UINT32 *address; + A_UINT32 data; +}; + +/* + * Skip some patches. Can be used to erase a single patch in a + * patch DataSet without having to re-write the DataSet. May + * also be used to embed information for use by subsequent + * patch code. The "data" in a PATCH_SKIP tells how many + * bytes of length "patch_s" to skip. + */ +#define PATCH_SKIP ((A_UINT32 *)0x00000000) + +/* + * Execute code at the address specified by "data". + * The address of the patch structure is passed as + * the one parameter. + */ +#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001) + +/* + * Same as PATCH_CODE_ABS, but treat "data" as an + * offset from the start of the patch word. + */ +#define PATCH_CODE_REL ((A_UINT32 *)0x00000002) + +/* Mark the end of this patch DataSet. */ +#define PATCH_END ((A_UINT32 *)0xffffffff) + +/* + * A DataSet which contains a Binary Patch to some other DataSet + * uses the original dsetid with the DSETID_BPATCH_FLAG bit set. + * Such a BPatch DataSet consists of BPatch metadata followed by + * the bdiff bytes. BPatch metadata consists of a single 32-bit + * word that contains the size of the BPatched final image. + * + * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff + * to create "diffs": + * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs + * Then add BPatch metadata to the start of "diffs". + * + * NB: There are some implementation-induced restrictions + * on which DataSets can be BPatched. + */ +#define DSETID_BPATCH_FLAG 0x80000000 + +#endif /* __DSETID_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/epping_test.h b/drivers/net/wireless/ath6kl/include/epping_test.h new file mode 100644 index 000000000000..e76b6420758d --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/epping_test.h @@ -0,0 +1,115 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +// + +/* This file contains shared definitions for the host/target endpoint ping test */ + +#ifndef EPPING_TEST_H_ +#define EPPING_TEST_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + + /* alignment to 4-bytes */ +#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR)) + +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) + +#define EPPING_RSVD_FILL 0xCC + +#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7 + +typedef PREPACK struct { + A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */ + A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */ + A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target) + When echoed: StreamEchoSent_t == StreamEcho_h */ + A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */ + A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */ + A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host*/ + A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value + since this packet maps to a 14-byte ethernet frame we want + to make sure ethertype field is set to something unknown */ + + A_UINT8 _pad[2]; /* padding for alignment */ + A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */ + A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */ + A_UINT32 SeqNo; /* sequence number (set by host or target) */ + A_UINT16 Cmd_h; /* ping command (filled by host) */ + A_UINT16 CmdFlags_h; /* optional flags */ + A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */ + A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */ + A_UINT16 DataLength; /* length of data */ + A_UINT16 DataCRC; /* 16 bit CRC of data */ + A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */ +} POSTPACK EPPING_HEADER; + +#define EPPING_PING_MAGIC_0 0xAA +#define EPPING_PING_MAGIC_1 0x55 +#define EPPING_PING_MAGIC_2 0xCE +#define EPPING_PING_MAGIC_3 0xEC + + + +#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \ + ((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \ + ((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \ + ((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3)) + +#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \ + (pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \ + (pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \ + (pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;} + +#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */ +#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */ +#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */ + +#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP) + +#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */ +#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */ +#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */ +#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */ +#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */ +#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */ + + /* test command parameters may be no more than 8 bytes */ +typedef PREPACK struct { + A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */ + A_UINT16 PacketLength; /* length of packet to generate including header */ + A_UINT16 Flags; /* flags */ + +#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */ +#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */ +#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */ +} POSTPACK EPPING_CONT_RX_PARAMS; + +#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h) +#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16))) + +#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we + can use this to distinguish packets */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + + +#endif /*EPPING_TEST_H_*/ diff --git a/drivers/net/wireless/ath6kl/include/gmboxif.h b/drivers/net/wireless/ath6kl/include/gmboxif.h new file mode 100644 index 000000000000..0d4120e34978 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/gmboxif.h @@ -0,0 +1,73 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __GMBOXIF_H__ +#define __GMBOXIF_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +/* GMBOX interface definitions */ + +#define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */ +#define AR6K_GMBOX_CREDIT_SIZE_COUNTER 2 /* credit counter 2 is used to pass the size of each credit */ + + + /* HCI UART transport definitions when used over GMBOX interface */ +#define HCI_UART_COMMAND_PKT 0x01 +#define HCI_UART_ACL_PKT 0x02 +#define HCI_UART_SCO_PKT 0x03 +#define HCI_UART_EVENT_PKT 0x04 + + /* definitions for BT HCI packets */ +typedef PREPACK struct { + A_UINT16 Flags_ConnHandle; + A_UINT16 Length; +} POSTPACK BT_HCI_ACL_HEADER; + +typedef PREPACK struct { + A_UINT16 Flags_ConnHandle; + A_UINT8 Length; +} POSTPACK BT_HCI_SCO_HEADER; + +typedef PREPACK struct { + A_UINT16 OpCode; + A_UINT8 ParamLength; +} POSTPACK BT_HCI_COMMAND_HEADER; + +typedef PREPACK struct { + A_UINT8 EventCode; + A_UINT8 ParamLength; +} POSTPACK BT_HCI_EVENT_HEADER; + +/* MBOX host interrupt signal assignments */ + +#define MBOX_SIG_HCI_BRIDGE_MAX 8 +#define MBOX_SIG_HCI_BRIDGE_BT_ON 0 +#define MBOX_SIG_HCI_BRIDGE_BT_OFF 1 +#define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2 + + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#endif /* __GMBOXIF_H__ */ + diff --git a/drivers/net/wireless/ath6kl/include/gpio.h b/drivers/net/wireless/ath6kl/include/gpio.h new file mode 100644 index 000000000000..9865af05ebd9 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/gpio.h @@ -0,0 +1,43 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#define AR6001_GPIO_PIN_COUNT 18 +#define AR6002_GPIO_PIN_COUNT 18 +#define AR6003_GPIO_PIN_COUNT 28 + +/* + * Possible values for WMIX_GPIO_SET_REGISTER_CMDID. + * NB: These match hardware order, so that addresses can + * easily be computed. + */ +#define GPIO_ID_OUT 0x00000000 +#define GPIO_ID_OUT_W1TS 0x00000001 +#define GPIO_ID_OUT_W1TC 0x00000002 +#define GPIO_ID_ENABLE 0x00000003 +#define GPIO_ID_ENABLE_W1TS 0x00000004 +#define GPIO_ID_ENABLE_W1TC 0x00000005 +#define GPIO_ID_IN 0x00000006 +#define GPIO_ID_STATUS 0x00000007 +#define GPIO_ID_STATUS_W1TS 0x00000008 +#define GPIO_ID_STATUS_W1TC 0x00000009 +#define GPIO_ID_PIN0 0x0000000a +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) + +#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17) +#define GPIO_ID_NONE 0xffffffff diff --git a/drivers/net/wireless/ath6kl/include/gpio_api.h b/drivers/net/wireless/ath6kl/include/gpio_api.h new file mode 100644 index 000000000000..82edcdd418bb --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/gpio_api.h @@ -0,0 +1,55 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Host-side General Purpose I/O API. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _GPIO_API_H_ +#define _GPIO_API_H_ + +/* + * Send a command to the Target in order to change output on GPIO pins. + */ +A_STATUS wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask); + +/* + * Send a command to the Target requesting input state of GPIO pins. + */ +A_STATUS wmi_gpio_input_get(struct wmi_t *wmip); + +/* + * Send a command to the Target to change the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value); + +/* + * Send a command to the Target to fetch the value of a GPIO register. + */ +A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id); + +/* + * Send a command to the Target, acknowledging some GPIO interrupts. + */ +A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask); + +#endif /* _GPIO_API_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/hci_transport_api.h b/drivers/net/wireless/ath6kl/include/hci_transport_api.h new file mode 100644 index 000000000000..a6cc16fc325a --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/hci_transport_api.h @@ -0,0 +1,243 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HCI_TRANSPORT_API_H_ +#define _HCI_TRANSPORT_API_H_ + + /* Bluetooth HCI packets are stored in HTC packet containers */ +#include "htc_packet.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef void *HCI_TRANSPORT_HANDLE; + +typedef HTC_ENDPOINT_ID HCI_TRANSPORT_PACKET_TYPE; + + /* we map each HCI packet class to a static Endpoint ID */ +#define HCI_COMMAND_TYPE ENDPOINT_1 +#define HCI_EVENT_TYPE ENDPOINT_2 +#define HCI_ACL_TYPE ENDPOINT_3 +#define HCI_PACKET_INVALID ENDPOINT_MAX + +#define HCI_GET_PACKET_TYPE(pP) (pP)->Endpoint +#define HCI_SET_PACKET_TYPE(pP,s) (pP)->Endpoint = (s) + +/* callback when an HCI packet was completely sent */ +typedef void (*HCI_TRANSPORT_SEND_PKT_COMPLETE)(void *, HTC_PACKET *); +/* callback when an HCI packet is received */ +typedef void (*HCI_TRANSPORT_RECV_PKT)(void *, HTC_PACKET *); +/* Optional receive buffer re-fill callback, + * On some OSes (like Linux) packets are allocated from a global pool and indicated up + * to the network stack. The driver never gets the packets back from the OS. For these OSes + * a refill callback can be used to allocate and re-queue buffers into HTC. + * A refill callback is used for the reception of ACL and EVENT packets. The caller must + * set the watermark trigger point to cause a refill. + */ +typedef void (*HCI_TRANSPORT_RECV_REFILL)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable); +/* Optional receive packet refill + * On some systems packet buffers are an extremely limited resource. Rather than + * queue largest-possible-sized buffers to the HCI bridge, some systems would rather + * allocate a specific size as the packet is received. The trade off is + * slightly more processing (callback invoked for each RX packet) + * for the benefit of committing fewer buffer resources into the bridge. + * + * The callback is provided the length of the pending packet to fetch. This includes the + * full transport header, HCI header, plus the length of payload. The callback can return a pointer to + * the allocated HTC packet for immediate use. + * + * NOTE*** This callback is mutually exclusive with the the refill callback above. + * + * */ +typedef HTC_PACKET *(*HCI_TRANSPORT_RECV_ALLOC)(void *, HCI_TRANSPORT_PACKET_TYPE Type, int Length); + +typedef enum _HCI_SEND_FULL_ACTION { + HCI_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */ + HCI_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */ +} HCI_SEND_FULL_ACTION; + +/* callback when an HCI send queue exceeds the caller's MaxSendQueueDepth threshold, + * the callback must return the send full action to take (either DROP or KEEP) */ +typedef HCI_SEND_FULL_ACTION (*HCI_TRANSPORT_SEND_FULL)(void *, HTC_PACKET *); + +typedef struct { + int HeadRoom; /* number of bytes in front of HCI packet for header space */ + int TailRoom; /* number of bytes at the end of the HCI packet for tail space */ + int IOBlockPad; /* I/O block padding required (always a power of 2) */ +} HCI_TRANSPORT_PROPERTIES; + +typedef struct _HCI_TRANSPORT_CONFIG_INFO { + int ACLRecvBufferWaterMark; /* low watermark to trigger recv refill */ + int EventRecvBufferWaterMark; /* low watermark to trigger recv refill */ + int MaxSendQueueDepth; /* max number of packets in the single send queue */ + void *pContext; /* context for all callbacks */ + void (*TransportFailure)(void *pContext, A_STATUS Status); /* transport failure callback */ + A_STATUS (*TransportReady)(HCI_TRANSPORT_HANDLE, HCI_TRANSPORT_PROPERTIES *,void *pContext); /* transport is ready */ + void (*TransportRemoved)(void *pContext); /* transport was removed */ + /* packet processing callbacks */ + HCI_TRANSPORT_SEND_PKT_COMPLETE pHCISendComplete; + HCI_TRANSPORT_RECV_PKT pHCIPktRecv; + HCI_TRANSPORT_RECV_REFILL pHCIPktRecvRefill; + HCI_TRANSPORT_RECV_ALLOC pHCIPktRecvAlloc; + HCI_TRANSPORT_SEND_FULL pHCISendFull; +} HCI_TRANSPORT_CONFIG_INFO; + +/* ------ Function Prototypes ------ */ +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Attach to the HCI transport module + @function name: HCI_TransportAttach + @input: HTCHandle - HTC handle (see HTC apis) + pInfo - initialization information + @output: + @return: HCI_TRANSPORT_HANDLE on success, NULL on failure + @notes: The HTC module provides HCI transport services. + @example: + @see also: HCI_TransportDetach ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +HCI_TRANSPORT_HANDLE HCI_TransportAttach(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Detach from the HCI transport module + @function name: HCI_TransportDetach + @input: HciTrans - HCI transport handle + pInfo - initialization information + @output: + @return: + @notes: + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HCI_TransportDetach(HCI_TRANSPORT_HANDLE HciTrans); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Add receive packets to the HCI transport + @function name: HCI_TransportAddReceivePkts + @input: HciTrans - HCI transport handle + pQueue - a queue holding one or more packets + @output: + @return: A_OK on success + @notes: user must supply HTC packets for capturing incomming HCI packets. The caller + must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL() + macro. Each packet in the queue must be of the same type and length + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HCI_TransportAddReceivePkts(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Send an HCI packet packet + @function name: HCI_TransportSendPkt + @input: HciTrans - HCI transport handle + pPacket - packet to send + Synchronous - send the packet synchronously (blocking) + @output: + @return: A_OK + @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() and + HCI_SET_PACKET_TYPE() macros to prepare the packet. + If Synchronous is set to FALSE the call is fully asynchronous. On error or completion, + the registered send complete callback will be called. + If Synchronous is set to TRUE, the call will block until the packet is sent, if the + interface cannot send the packet within a 2 second timeout, the function will return + the failure code : A_EBUSY. + + Synchronous Mode should only be used at start-up to initialize the HCI device using + custom HCI commands. It should NOT be mixed with Asynchronous operations. Mixed synchronous + and asynchronous operation behavior is undefined. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HCI_TransportSendPkt(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous); + + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Stop HCI transport + @function name: HCI_TransportStop + @input: HciTrans - hci transport handle + @output: + @return: + @notes: HCI transport communication will be halted. All receive and pending TX packets will + be flushed. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HCI_TransportStop(HCI_TRANSPORT_HANDLE HciTrans); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Start the HCI transport + @function name: HCI_TransportStart + @input: HciTrans - hci transport handle + @output: + @return: A_OK on success + @notes: HCI transport communication will begin, the caller can expect the arrival + of HCI recv packets as soon as this call returns. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HCI_TransportStart(HCI_TRANSPORT_HANDLE HciTrans); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Enable or Disable Asynchronous Recv + @function name: HCI_TransportEnableDisableAsyncRecv + @input: HciTrans - hci transport handle + Enable - enable or disable asynchronous recv + @output: + @return: A_OK on success + @notes: This API must be called when HCI recv is handled synchronously + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HCI_TransportEnableDisableAsyncRecv(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Receive an event packet from the HCI transport synchronously using polling + @function name: HCI_TransportRecvHCIEventSync + @input: HciTrans - hci transport handle + pPacket - HTC packet to hold the recv data + MaxPollMS - maximum polling duration in Milliseconds; + @output: + @return: A_OK on success + @notes: This API should be used only during HCI device initialization, the caller must call + HCI_TransportEnableDisableAsyncRecv with Enable=FALSE prior to using this API. + This API will only capture HCI Event packets. + @example: + @see also: HCI_TransportEnableDisableAsyncRecv ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HCI_TransportRecvHCIEventSync(HCI_TRANSPORT_HANDLE HciTrans, + HTC_PACKET *pPacket, + int MaxPollMS); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Set the desired baud rate for the underlying transport layer + @function name: HCI_TransportSetBaudRate + @input: HciTrans - hci transport handle + Baud - baud rate in bps + @output: + @return: A_OK on success + @notes: This API should be used only after HCI device initialization + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HCI_TransportSetBaudRate(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud); + +#ifdef __cplusplus +} +#endif + +#endif /* _HCI_TRANSPORT_API_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/hif.h b/drivers/net/wireless/ath6kl/include/hif.h new file mode 100644 index 000000000000..bc6e6a5b3448 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/hif.h @@ -0,0 +1,421 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HIF specific declarations and prototypes +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HIF_H_ +#define _HIF_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Header files */ +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "dl_list.h" + + +typedef struct htc_callbacks HTC_CALLBACKS; +typedef struct hif_device HIF_DEVICE; + +/* + * direction - Direction of transfer (HIF_READ/HIF_WRITE). + */ +#define HIF_READ 0x00000001 +#define HIF_WRITE 0x00000002 +#define HIF_DIR_MASK (HIF_READ | HIF_WRITE) + +/* + * type - An interface may support different kind of read/write commands. + * For example: SDIO supports CMD52/CMD53s. In case of MSIO it + * translates to using different kinds of TPCs. The command type + * is thus divided into a basic and an extended command and can + * be specified using HIF_BASIC_IO/HIF_EXTENDED_IO. + */ +#define HIF_BASIC_IO 0x00000004 +#define HIF_EXTENDED_IO 0x00000008 +#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO) + +/* + * emode - This indicates the whether the command is to be executed in a + * blocking or non-blocking fashion (HIF_SYNCHRONOUS/ + * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been + * implemented using the asynchronous mode allowing the the bus + * driver to indicate the completion of operation through the + * registered callback routine. The requirement primarily comes + * from the contexts these operations get called from (a driver's + * transmit context or the ISR context in case of receive). + * Support for both of these modes is essential. + */ +#define HIF_SYNCHRONOUS 0x00000010 +#define HIF_ASYNCHRONOUS 0x00000020 +#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS) + +/* + * dmode - An interface may support different kinds of commands based on + * the tradeoff between the amount of data it can carry and the + * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/ + * HIF_BLOCK_BASIS). In case of latter, the data is rounded off + * to the nearest block size by padding. The size of the block is + * configurable at compile time using the HIF_BLOCK_SIZE and is + * negotiated with the target during initialization after the + * AR6000 interrupts are enabled. + */ +#define HIF_BYTE_BASIS 0x00000040 +#define HIF_BLOCK_BASIS 0x00000080 +#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS) + +/* + * amode - This indicates if the address has to be incremented on AR6000 + * after every read/write operation (HIF?FIXED_ADDRESS/ + * HIF_INCREMENTAL_ADDRESS). + */ +#define HIF_FIXED_ADDRESS 0x00000100 +#define HIF_INCREMENTAL_ADDRESS 0x00000200 +#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS) + +#define HIF_WR_ASYNC_BYTE_FIX \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_ASYNC_BYTE_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_ASYNC_BLOCK_INC \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BYTE_FIX \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_SYNC_BYTE_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_SYNC_BLOCK_INC \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_WR_ASYNC_BLOCK_FIX \ + (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) +#define HIF_WR_SYNC_BLOCK_FIX \ + (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_SYNC_BYTE_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BYTE_FIX \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_FIX \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) +#define HIF_RD_ASYNC_BYTE_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_ASYNC_BLOCK_INC \ + (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BLOCK_INC \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS) +#define HIF_RD_SYNC_BLOCK_FIX \ + (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS) + +typedef enum { + HIF_DEVICE_POWER_STATE = 0, + HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + HIF_DEVICE_GET_MBOX_ADDR, + HIF_DEVICE_GET_PENDING_EVENTS_FUNC, + HIF_DEVICE_GET_IRQ_PROC_MODE, + HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, + HIF_DEVICE_POWER_STATE_CHANGE, + HIF_DEVICE_GET_IRQ_YIELD_PARAMS, + HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT, + HIF_DEVICE_GET_OS_DEVICE, + HIF_DEVICE_DEBUG_BUS_STATE, +} HIF_DEVICE_CONFIG_OPCODE; + +/* + * HIF CONFIGURE definitions: + * + * HIF_DEVICE_GET_MBOX_BLOCK_SIZE + * input : none + * output : array of 4 A_UINT32s + * notes: block size is returned for each mailbox (4) + * + * HIF_DEVICE_GET_MBOX_ADDR + * input : none + * output : HIF_DEVICE_MBOX_INFO + * notes: + * + * HIF_DEVICE_GET_PENDING_EVENTS_FUNC + * input : none + * output: HIF_PENDING_EVENTS_FUNC function pointer + * notes: this is optional for the HIF layer, if the request is + * not handled then it indicates that the upper layer can use + * the standard device methods to get pending events (IRQs, mailbox messages etc..) + * otherwise it can call the function pointer to check pending events. + * + * HIF_DEVICE_GET_IRQ_PROC_MODE + * input : none + * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode) + * note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF + * layer can report whether IRQ processing is requires synchronous behavior or + * can be processed using asynchronous bus requests (typically faster). + * + * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC + * input : + * output : HIF_MASK_UNMASK_RECV_EVENT function pointer + * notes: this is optional for the HIF layer. The HIF layer may require a special mechanism + * to mask receive message events. The upper layer can call this pointer when it needs + * to mask/unmask receive events (in case it runs out of buffers). + * + * HIF_DEVICE_POWER_STATE_CHANGE + * + * input : HIF_DEVICE_POWER_CHANGE_TYPE + * output : none + * note: this is optional for the HIF layer. The HIF layer can handle power on/off state change + * requests in an interconnect specific way. This is highly OS and bus driver dependent. + * The caller must guarantee that no HIF read/write requests will be made after the device + * is powered down. + * + * HIF_DEVICE_GET_IRQ_YIELD_PARAMS + * + * input : none + * output : HIF_DEVICE_IRQ_YIELD_PARAMS + * note: This query checks if the HIF layer wishes to impose a processing yield count for the DSR handler. + * The DSR callback handler will exit after a fixed number of RX packets or events are processed. + * This query is only made if the device reports an IRQ processing mode of HIF_DEVICE_IRQ_SYNC_ONLY. + * The HIF implementation can ignore this command if it does not desire the DSR callback to yield. + * The HIF layer can indicate the maximum number of IRQ processing units (RX packets) before the + * DSR handler callback must yield and return control back to the HIF layer. When a yield limit is + * used the DSR callback will not call HIFAckInterrupts() as it would normally do before returning. + * The HIF implementation that requires a yield count must call HIFAckInterrupt() when it is prepared + * to process interrupts again. + * + * HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT + * input : none + * output : HIF_DEVICE_SCATTER_SUPPORT_INFO + * note: This query checks if the HIF layer implements the SCATTER request interface. Scatter requests + * allows upper layers to submit mailbox I/O operations using a list of buffers. This is useful for + * multi-message transfers that can better utilize the bus interconnect. + * + * + * HIF_DEVICE_GET_OS_DEVICE + * intput : none + * output : HIF_DEVICE_OS_DEVICE_INFO; + * note: On some operating systems, the HIF layer has a parent device object for the bus. This object + * may be required to register certain types of logical devices. + * + * HIF_DEVICE_DEBUG_BUS_STATE + * input : none + * output : none + * note: This configure option triggers the HIF interface to dump as much bus interface state. This + * configuration request is optional (No-OP on some HIF implementations) + * + */ + +typedef struct { + A_UINT32 ExtendedAddress; /* extended address for larger writes */ + A_UINT32 ExtendedSize; +} HIF_MBOX_PROPERTIES; + +#define HIF_MBOX_FLAG_NO_BUNDLING (1 << 0) /* do not allow bundling over the mailbox */ + +typedef struct { + A_UINT32 MboxAddresses[4]; /* must be first element for legacy HIFs that return the address in + and ARRAY of 32-bit words */ + + /* the following describe extended mailbox properties */ + HIF_MBOX_PROPERTIES MboxProp[4]; + /* if the HIF supports the GMbox extended address region it can report it + * here, some interfaces cannot support the GMBOX address range and not set this */ + A_UINT32 GMboxAddress; + A_UINT32 GMboxSize; + A_UINT32 Flags; /* flags to describe mbox behavior or usage */ +} HIF_DEVICE_MBOX_INFO; + +typedef enum { + HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all + interrupts before returning */ + HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts + using ASYNC I/O (that is HIFAckInterrupt can be called at a + later time */ +} HIF_DEVICE_IRQ_PROCESSING_MODE; + +typedef enum { + HIF_DEVICE_POWER_UP, /* HIF layer should power up interface and/or module */ + HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific measures to minimize power */ + HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific AND/OR platform-specific measures + to completely power-off the module and associated hardware (i.e. cut power supplies) + */ +} HIF_DEVICE_POWER_CHANGE_TYPE; + +typedef struct { + int RecvPacketYieldCount; /* max number of packets to force DSR to return */ +} HIF_DEVICE_IRQ_YIELD_PARAMS; + + +typedef struct _HIF_SCATTER_ITEM { + A_UINT8 *pBuffer; /* CPU accessible address of buffer */ + int Length; /* length of transfer to/from this buffer */ + void *pCallerContexts[2]; /* space for caller to insert a context associated with this item */ +} HIF_SCATTER_ITEM; + +struct _HIF_SCATTER_REQ; + +typedef void ( *HIF_SCATTER_COMP_CB)(struct _HIF_SCATTER_REQ *); + +typedef enum _HIF_SCATTER_METHOD { + HIF_SCATTER_NONE = 0, + HIF_SCATTER_DMA_REAL, /* Real SG support no restrictions */ + HIF_SCATTER_DMA_BOUNCE, /* Uses SG DMA but HIF layer uses an internal bounce buffer */ +} HIF_SCATTER_METHOD; + +typedef struct _HIF_SCATTER_REQ { + DL_LIST ListLink; /* link management */ + A_UINT32 Address; /* address for the read/write operation */ + A_UINT32 Request; /* request flags */ + A_UINT32 TotalLength; /* total length of entire transfer */ + A_UINT32 CallerFlags; /* caller specific flags can be stored here */ + HIF_SCATTER_COMP_CB CompletionRoutine; /* completion routine set by caller */ + A_STATUS CompletionStatus; /* status of completion */ + void *Context; /* caller context for this request */ + int ValidScatterEntries; /* number of valid entries set by caller */ + HIF_SCATTER_METHOD ScatterMethod; /* scatter method handled by HIF */ + void *HIFPrivate[4]; /* HIF private area */ + A_UINT8 *pScatterBounceBuffer; /* bounce buffer for upper layers to copy to/from */ + HIF_SCATTER_ITEM ScatterList[1]; /* start of scatter list */ +} HIF_SCATTER_REQ; + +typedef HIF_SCATTER_REQ * ( *HIF_ALLOCATE_SCATTER_REQUEST)(HIF_DEVICE *device); +typedef void ( *HIF_FREE_SCATTER_REQUEST)(HIF_DEVICE *device, HIF_SCATTER_REQ *request); +typedef A_STATUS ( *HIF_READWRITE_SCATTER)(HIF_DEVICE *device, HIF_SCATTER_REQ *request); + +typedef struct _HIF_DEVICE_SCATTER_SUPPORT_INFO { + /* information returned from HIF layer */ + HIF_ALLOCATE_SCATTER_REQUEST pAllocateReqFunc; + HIF_FREE_SCATTER_REQUEST pFreeReqFunc; + HIF_READWRITE_SCATTER pReadWriteScatterFunc; + int MaxScatterEntries; + int MaxTransferSizePerScatterReq; +} HIF_DEVICE_SCATTER_SUPPORT_INFO; + +typedef struct { + void *pOSDevice; +} HIF_DEVICE_OS_DEVICE_INFO; + +#define HIF_MAX_DEVICES 1 + +struct htc_callbacks { + void *context; /* context to pass to the dsrhandler + note : rwCompletionHandler is provided the context passed to HIFReadWrite */ + A_STATUS (* rwCompletionHandler)(void *rwContext, A_STATUS status); + A_STATUS (* dsrHandler)(void *context); +}; + +typedef struct osdrv_callbacks { + void *context; /* context to pass for all callbacks except deviceRemovedHandler + the deviceRemovedHandler is only called if the device is claimed */ + A_STATUS (* deviceInsertedHandler)(void *context, void *hif_handle); + A_STATUS (* deviceRemovedHandler)(void *claimedContext, void *hif_handle); + A_STATUS (* deviceSuspendHandler)(void *context); + A_STATUS (* deviceResumeHandler)(void *context); + A_STATUS (* deviceWakeupHandler)(void *context); +} OSDRV_CALLBACKS; + +#define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host + needs to read the register table to figure out what */ +#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */ + +typedef struct _HIF_PENDING_EVENTS_INFO { + A_UINT32 Events; + A_UINT32 LookAhead; + A_UINT32 AvailableRecvBytes; +} HIF_PENDING_EVENTS_INFO; + + /* function to get pending events , some HIF modules use special mechanisms + * to detect packet available and other interrupts */ +typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE *device, + HIF_PENDING_EVENTS_INFO *pEvents, + void *AsyncContext); + +#define HIF_MASK_RECV TRUE +#define HIF_UNMASK_RECV FALSE + /* function to mask recv events */ +typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE *device, + A_BOOL Mask, + void *AsyncContext); + + +/* + * This API is used to perform any global initialization of the HIF layer + * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer + * + */ +A_STATUS HIFInit(OSDRV_CALLBACKS *callbacks); + +/* This API claims the HIF device and provides a context for handling removal. + * The device removal callback is only called when the OSDRV layer claims + * a device. The claimed context must be non-NULL */ +void HIFClaimDevice(HIF_DEVICE *device, void *claimedContext); +/* release the claimed device */ +void HIFReleaseDevice(HIF_DEVICE *device); + +/* This API allows the HTC layer to attach to the HIF device */ +A_STATUS HIFAttachHTC(HIF_DEVICE *device, HTC_CALLBACKS *callbacks); +/* This API detaches the HTC layer from the HIF device */ +void HIFDetachHTC(HIF_DEVICE *device); + +/* + * This API is used to provide the read/write interface over the specific bus + * interface. + * address - Starting address in the AR6000's address space. For mailbox + * writes, it refers to the start of the mbox boundary. It should + * be ensured that the last byte falls on the mailbox's EOM. For + * mailbox reads, it refers to the end of the mbox boundary. + * buffer - Pointer to the buffer containg the data to be transmitted or + * received. + * length - Amount of data to be transmitted or received. + * request - Characterizes the attributes of the command. + */ +A_STATUS +HIFReadWrite(HIF_DEVICE *device, + A_UINT32 address, + A_UCHAR *buffer, + A_UINT32 length, + A_UINT32 request, + void *context); + +/* + * This can be initiated from the unload driver context when the OSDRV layer has no more use for + * the device. + */ +void HIFShutDownDevice(HIF_DEVICE *device); + +/* + * This should translate to an acknowledgment to the bus driver indicating that + * the previous interrupt request has been serviced and the all the relevant + * sources have been cleared. HTC is ready to process more interrupts. + * This should prevent the bus driver from raising an interrupt unless the + * previous one has been serviced and acknowledged using the previous API. + */ +void HIFAckInterrupt(HIF_DEVICE *device); + +void HIFMaskInterrupt(HIF_DEVICE *device); + +void HIFUnMaskInterrupt(HIF_DEVICE *device); + +A_STATUS +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode, + void *config, A_UINT32 configLen); + +#ifdef __cplusplus +} +#endif + +#endif /* _HIF_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/host_version.h b/drivers/net/wireless/ath6kl/include/host_version.h new file mode 100644 index 000000000000..8e464997ecf5 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/host_version.h @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains version information for the sample host driver for the +// AR6000 chip +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_VERSION_H_ +#define _HOST_VERSION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + * The version number is made up of major, minor, patch and build + * numbers. These are 16 bit numbers. The build and release script will + * set the build number using a Perforce counter. Here the build number is + * set to 9999 so that builds done without the build-release script are easily + * identifiable. + */ + +#define ATH_SW_VER_MAJOR __VER_MAJOR_ +#define ATH_SW_VER_MINOR __VER_MINOR_ +#define ATH_SW_VER_PATCH __VER_PATCH_ +#define ATH_SW_VER_BUILD __BUILD_NUMBER_ + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_VERSION_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/htc.h b/drivers/net/wireless/ath6kl/include/htc.h new file mode 100644 index 000000000000..515c8ec62bdf --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/htc.h @@ -0,0 +1,232 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_H__ +#define __HTC_H__ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field)) + +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ + (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)])) + +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a + * structure using only the type and field name. + * Use these macros if there is the potential for unaligned buffer accesses. */ +#define A_GET_UINT16_FIELD(p,type,field) \ + ASSEMBLE_UNALIGNED_UINT16(p,\ + A_OFFSETOF(type,field) + 1, \ + A_OFFSETOF(type,field)) + +#define A_SET_UINT16_FIELD(p,type,field,value) \ +{ \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \ +} + +#define A_GET_UINT8_FIELD(p,type,field) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] + +#define A_SET_UINT8_FIELD(p,type,field,value) \ + ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR{ + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + A_UINT8 EndpointID; + A_UINT8 Flags; + A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + A_UINT8 ControlBytes[2]; + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +/* frame header flags */ + + /* send direction */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */ + /* receive direction */ +#define HTC_FLAGS_RECV_UNUSED_0 (1 << 0) /* bit 0 unused */ +#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */ +#define HTC_FLAGS_RECV_UNUSED_2 (1 << 0) /* bit 2 unused */ +#define HTC_FLAGS_RECV_UNUSED_3 (1 << 0) /* bit 3 unused */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0) /* bits 7..4 */ +#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4 + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ + +#define HTC_MSG_READY_ID 1 +#define HTC_MSG_CONNECT_SERVICE_ID 2 +#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3 +#define HTC_MSG_SETUP_COMPLETE_ID 4 +#define HTC_MSG_SETUP_COMPLETE_EX_ID 5 + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct { + A_UINT16 MessageID; +} POSTPACK HTC_UNKNOWN_MSG; + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; /* ID */ + A_UINT16 CreditCount; /* number of credits the target can offer */ + A_UINT16 CreditSize; /* size of each credit */ + A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */ + A_UINT8 _Pad1; +} POSTPACK HTC_READY_MSG; + + /* extended HTC ready message */ +typedef PREPACK struct { + HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */ + /* extended information */ + A_UINT8 HTCVersion; + A_UINT8 MaxMsgsPerHTCBundle; +} POSTPACK HTC_READY_EX_MSG; + +#define HTC_VERSION_2P0 0x00 +#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */ + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID of the service to connect to */ + A_UINT16 ConnectionFlags; /* connection flags */ + +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT16 ServiceID; /* service ID that the connection request was made */ + A_UINT8 Status; /* service connection status */ + A_UINT8 EndpointID; /* assigned endpoint ID */ + A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */ + A_UINT8 ServiceMetaLength; /* length of meta data that follows */ + A_UINT8 _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +typedef PREPACK struct { + A_UINT16 MessageID; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + + /* extended setup completion message */ +typedef PREPACK struct { + A_UINT16 MessageID; + A_UINT32 SetupFlags; + A_UINT8 MaxMsgsPerBundledRecv; + A_UINT8 Rsvd[3]; +} POSTPACK HTC_SETUP_COMPLETE_EX_MSG; + +#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0) + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more + endpoints */ + +/* report record IDs */ + +#define HTC_RECORD_NULL 0 +#define HTC_RECORD_CREDITS 1 +#define HTC_RECORD_LOOKAHEAD 2 +#define HTC_RECORD_LOOKAHEAD_BUNDLE 3 + +typedef PREPACK struct { + A_UINT8 RecordID; /* Record ID */ + A_UINT8 Length; /* Length of record */ +} POSTPACK HTC_RECORD_HDR; + +typedef PREPACK struct { + A_UINT8 EndpointID; /* Endpoint that owns these credits */ + A_UINT8 Credits; /* credits to report since last report */ +} POSTPACK HTC_CREDIT_REPORT; + +typedef PREPACK struct { + A_UINT8 PreValid; /* pre valid guard */ + A_UINT8 LookAhead[4]; /* 4 byte lookahead */ + A_UINT8 PostValid; /* post valid guard */ + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +typedef PREPACK struct { + A_UINT8 LookAhead[4]; /* 4 byte lookahead */ +} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + + +#endif /* __HTC_H__ */ + diff --git a/drivers/net/wireless/ath6kl/include/htc_api.h b/drivers/net/wireless/ath6kl/include/htc_api.h new file mode 100644 index 000000000000..12f81f53ee90 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/htc_api.h @@ -0,0 +1,568 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HTC_API_H_ +#define _HTC_API_H_ + +#include +#include +#include "htc_packet.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* TODO.. for BMI */ +#define ENDPOINT1 0 +// TODO -remove me, but we have to fix BMI first +#define HTC_MAILBOX_NUM_MAX 4 + +/* this is the amount of header room required by users of HTC */ +#define HTC_HEADER_LEN HTC_HDR_LENGTH + +typedef void *HTC_HANDLE; + +typedef A_UINT16 HTC_SERVICE_ID; + +typedef struct _HTC_INIT_INFO { + void *pContext; /* context for target failure notification */ + void (*TargetFailure)(void *Instance, A_STATUS Status); +} HTC_INIT_INFO; + +/* per service connection send completion */ +typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *); +/* per service connection callback when a plurality of packets have been sent + * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback) + * to hold a list of completed send packets. + * If the handler cannot fully traverse the packet queue before returning, it should + * transfer the items of the queue into the caller's private queue using: + * HTC_PACKET_ENQUEUE() */ +typedef void (*HTC_EP_SEND_PKT_COMP_MULTIPLE)(void *,HTC_PACKET_QUEUE *); +/* per service connection pkt received */ +typedef void (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *); +/* per service connection callback when a plurality of packets are received + * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback) + * to hold a list of recv packets. + * If the handler cannot fully traverse the packet queue before returning, it should + * transfer the items of the queue into the caller's private queue using: + * HTC_PACKET_ENQUEUE() */ +typedef void (*HTC_EP_RECV_PKT_MULTIPLE)(void *,HTC_PACKET_QUEUE *); + +/* Optional per service connection receive buffer re-fill callback, + * On some OSes (like Linux) packets are allocated from a global pool and indicated up + * to the network stack. The driver never gets the packets back from the OS. For these OSes + * a refill callback can be used to allocate and re-queue buffers into HTC. + * + * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and + * the driver can re-queue these buffers into HTC. In this regard a refill callback is + * unnecessary */ +typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint); + +/* Optional per service connection receive buffer allocation callback. + * On some systems packet buffers are an extremely limited resource. Rather than + * queue largest-possible-sized buffers to HTC, some systems would rather + * allocate a specific size as the packet is received. The trade off is + * slightly more processing (callback invoked for each RX packet) + * for the benefit of committing fewer buffer resources into HTC. + * + * The callback is provided the length of the pending packet to fetch. This includes the + * HTC header length plus the length of payload. The callback can return a pointer to + * the allocated HTC packet for immediate use. + * + * Alternatively a variant of this handler can be used to allocate large receive packets as needed. + * For example an application can use the refill mechanism for normal packets and the recv-alloc mechanism to + * handle the case where a large packet buffer is required. This can significantly reduce the + * amount of "committed" memory used to receive packets. + * + * */ +typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *, HTC_ENDPOINT_ID Endpoint, int Length); + +typedef enum _HTC_SEND_FULL_ACTION { + HTC_SEND_FULL_KEEP = 0, /* packet that overflowed should be kept in the queue */ + HTC_SEND_FULL_DROP = 1, /* packet that overflowed should be dropped */ +} HTC_SEND_FULL_ACTION; + +/* Optional per service connection callback when a send queue is full. This can occur if the + * host continues queueing up TX packets faster than credits can arrive + * To prevent the host (on some Oses like Linux) from continuously queueing packets + * and consuming resources, this callback is provided so that that the host + * can disable TX in the subsystem (i.e. network stack). + * This callback is invoked for each packet that "overflows" the HTC queue. The callback can + * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or + * dropped (HTC_SEND_FULL_DROP). If a packet is dropped, the EpTxComplete handler will be called + * and the packet's status field will be set to A_NO_RESOURCE. + * Other OSes require a "per-packet" indication for each completed TX packet, this + * closed loop mechanism will prevent the network stack from overunning the NIC + * The packet to keep or drop is passed for inspection to the registered handler the handler + * must ONLY inspect the packet, it may not free or reclaim the packet. */ +typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_PACKET *pPacket); + +typedef struct _HTC_EP_CALLBACKS { + void *pContext; /* context for each callback */ + HTC_EP_SEND_PKT_COMPLETE EpTxComplete; /* tx completion callback for connected endpoint */ + HTC_EP_RECV_PKT EpRecv; /* receive callback for connected endpoint */ + HTC_EP_RECV_REFILL EpRecvRefill; /* OPTIONAL receive re-fill callback for connected endpoint */ + HTC_EP_SEND_QUEUE_FULL EpSendFull; /* OPTIONAL send full callback */ + HTC_EP_RECV_ALLOC EpRecvAlloc; /* OPTIONAL recv allocation callback */ + HTC_EP_RECV_ALLOC EpRecvAllocThresh; /* OPTIONAL recv allocation callback based on a threshold */ + HTC_EP_SEND_PKT_COMP_MULTIPLE EpTxCompleteMultiple; /* OPTIONAL completion handler for multiple complete + indications (EpTxComplete must be NULL) */ + HTC_EP_RECV_PKT_MULTIPLE EpRecvPktMultiple; /* OPTIONAL completion handler for multiple + recv packet indications (EpRecv must be NULL) */ + int RecvAllocThreshold; /* if EpRecvAllocThresh is non-NULL, HTC will compare the + threshold value to the current recv packet length and invoke + the EpRecvAllocThresh callback to acquire a packet buffer */ + int RecvRefillWaterMark; /* if a EpRecvRefill handler is provided, this value + can be used to set a trigger refill callback + when the recv queue drops below this value + if set to 0, the refill is only called when packets + are empty */ +} HTC_EP_CALLBACKS; + +/* service connection information */ +typedef struct _HTC_SERVICE_CONNECT_REQ { + HTC_SERVICE_ID ServiceID; /* service ID to connect to */ + A_UINT16 ConnectionFlags; /* connection flags, see htc protocol definition */ + A_UINT8 *pMetaData; /* ptr to optional service-specific meta-data */ + A_UINT8 MetaDataLength; /* optional meta data length */ + HTC_EP_CALLBACKS EpCallbacks; /* endpoint callbacks */ + int MaxSendQueueDepth; /* maximum depth of any send queue */ + A_UINT32 LocalConnectionFlags; /* HTC flags for the host-side (local) connection */ + unsigned int MaxSendMsgSize; /* override max message size in send direction */ +} HTC_SERVICE_CONNECT_REQ; + +#define HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING (1 << 0) /* enable send bundle padding for this endpoint */ + +/* service connection response information */ +typedef struct _HTC_SERVICE_CONNECT_RESP { + A_UINT8 *pMetaData; /* caller supplied buffer to optional meta-data */ + A_UINT8 BufferLength; /* length of caller supplied buffer */ + A_UINT8 ActualLength; /* actual length of meta data */ + HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */ + unsigned int MaxMsgLength; /* max length of all messages over this endpoint */ + A_UINT8 ConnectRespCode; /* connect response code from target */ +} HTC_SERVICE_CONNECT_RESP; + +/* endpoint distribution structure */ +typedef struct _HTC_ENDPOINT_CREDIT_DIST { + struct _HTC_ENDPOINT_CREDIT_DIST *pNext; + struct _HTC_ENDPOINT_CREDIT_DIST *pPrev; + HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */ + HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */ + A_UINT32 DistFlags; /* distribution flags, distribution function can + set default activity using SET_EP_ACTIVE() macro */ + int TxCreditsNorm; /* credits for normal operation, anything above this + indicates the endpoint is over-subscribed, this field + is only relevant to the credit distribution function */ + int TxCreditsMin; /* floor for credit distribution, this field is + only relevant to the credit distribution function */ + int TxCreditsAssigned; /* number of credits assigned to this EP, this field + is only relevant to the credit dist function */ + int TxCredits; /* current credits available, this field is used by + HTC to determine whether a message can be sent or + must be queued */ + int TxCreditsToDist; /* pending credits to distribute on this endpoint, this + is set by HTC when credit reports arrive. + The credit distribution functions sets this to zero + when it distributes the credits */ + int TxCreditsSeek; /* this is the number of credits that the current pending TX + packet needs to transmit. This is set by HTC when + and endpoint needs credits in order to transmit */ + int TxCreditSize; /* size in bytes of each credit (set by HTC) */ + int TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */ + void *pHTCReserved; /* reserved for HTC use */ + int TxQueueDepth; /* current depth of TX queue , i.e. messages waiting for credits + This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE + or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint + that has non-zero credits to recover + */ +} HTC_ENDPOINT_CREDIT_DIST; + +#define HTC_EP_ACTIVE ((A_UINT32) (1u << 31)) + +/* macro to check if an endpoint has gone active, useful for credit + * distributions */ +#define IS_EP_ACTIVE(epDist) ((epDist)->DistFlags & HTC_EP_ACTIVE) +#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE + + /* credit distibution code that is passed into the distrbution function, + * there are mandatory and optional codes that must be handled */ +typedef enum _HTC_CREDIT_DIST_REASON { + HTC_CREDIT_DIST_SEND_COMPLETE = 0, /* credits available as a result of completed + send operations (MANDATORY) resulting in credit reports */ + HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1, /* a change in endpoint activity occured (OPTIONAL) */ + HTC_CREDIT_DIST_SEEK_CREDITS, /* an endpoint needs to "seek" credits (OPTIONAL) */ + HTC_DUMP_CREDIT_STATE /* for debugging, dump any state information that is kept by + the distribution function */ +} HTC_CREDIT_DIST_REASON; + +typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + HTC_CREDIT_DIST_REASON Reason); + +typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits); + + /* endpoint statistics action */ +typedef enum _HTC_ENDPOINT_STAT_ACTION { + HTC_EP_STAT_SAMPLE = 0, /* only read statistics */ + HTC_EP_STAT_SAMPLE_AND_CLEAR = 1, /* sample and immediately clear statistics */ + HTC_EP_STAT_CLEAR /* clear only */ +} HTC_ENDPOINT_STAT_ACTION; + + /* endpoint statistics */ +typedef struct _HTC_ENDPOINT_STATS { + A_UINT32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on + this endpoint */ + A_UINT32 TxIssued; /* running count of total TX packets issued */ + A_UINT32 TxPacketsBundled; /* running count of TX packets that were issued in bundles */ + A_UINT32 TxBundles; /* running count of TX bundles that were issued */ + A_UINT32 TxDropped; /* tx packets that were dropped */ + A_UINT32 TxCreditRpts; /* running count of total credit reports received for this endpoint */ + A_UINT32 TxCreditRptsFromRx; /* credit reports received from this endpoint's RX packets */ + A_UINT32 TxCreditRptsFromOther; /* credit reports received from RX packets of other endpoints */ + A_UINT32 TxCreditRptsFromEp0; /* credit reports received from endpoint 0 RX packets */ + A_UINT32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */ + A_UINT32 TxCreditsFromOther; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsFromEp0; /* count of credits received via another endpoint */ + A_UINT32 TxCreditsConsummed; /* count of consummed credits */ + A_UINT32 TxCreditsReturned; /* count of credits returned */ + A_UINT32 RxReceived; /* count of RX packets received */ + A_UINT32 RxLookAheads; /* count of lookahead records + found in messages received on this endpoint */ + A_UINT32 RxPacketsBundled; /* count of recv packets received in a bundle */ + A_UINT32 RxBundleLookAheads; /* count of number of bundled lookaheads */ + A_UINT32 RxBundleIndFromHdr; /* count of the number of bundle indications from the HTC header */ + A_UINT32 RxAllocThreshHit; /* count of the number of times the recv allocation threshhold was hit */ + A_UINT32 RxAllocThreshBytes; /* total number of bytes */ +} HTC_ENDPOINT_STATS; + +/* ------ Function Prototypes ------ */ +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Create an instance of HTC over the underlying HIF device + @function name: HTCCreate + @input: HifDevice - hif device handle, + pInfo - initialization information + @output: + @return: HTC_HANDLE on success, NULL on failure + @notes: + @example: + @see also: HTCDestroy ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +HTC_HANDLE HTCCreate(void *HifDevice, HTC_INIT_INFO *pInfo); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get the underlying HIF device handle + @function name: HTCGetHifDevice + @input: HTCHandle - handle passed into the AddInstance callback + @output: + @return: opaque HIF device handle usable in HIF API calls. + @notes: + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void *HTCGetHifDevice(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Set credit distribution parameters + @function name: HTCSetCreditDistribution + @input: HTCHandle - HTC handle + pCreditDistCont - caller supplied context to pass into distribution functions + CreditDistFunc - Distribution function callback + CreditDistInit - Credit Distribution initialization callback + ServicePriorityOrder - Array containing list of service IDs, lowest index is highest + priority + ListLength - number of elements in ServicePriorityOrder + @output: + @return: + @notes: The user can set a custom credit distribution function to handle special requirements + for each endpoint. A default credit distribution routine can be used by setting + CreditInitFunc to NULL. The default credit distribution is only provided for simple + "fair" credit distribution without regard to any prioritization. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCSetCreditDistribution(HTC_HANDLE HTCHandle, + void *pCreditDistContext, + HTC_CREDIT_DIST_CALLBACK CreditDistFunc, + HTC_CREDIT_INIT_CALLBACK CreditInitFunc, + HTC_SERVICE_ID ServicePriorityOrder[], + int ListLength); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Wait for the target to indicate the HTC layer is ready + @function name: HTCWaitTarget + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API blocks until the target responds with an HTC ready message. + The caller should not connect services until the target has indicated it is + ready. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Start target service communications + @function name: HTCStart + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This API indicates to the target that the service connection phase is complete + and the target can freely start all connected services. This API should only be + called AFTER all service connections have been made. TCStart will issue a + SETUP_COMPLETE message to the target to indicate that all service connections + have been made and the target can start communicating over the endpoints. + @example: + @see also: HTCConnectService ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCStart(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Add receive packet to HTC + @function name: HTCAddReceivePkt + @input: HTCHandle - HTC handle + pPacket - HTC receive packet to add + @output: + @return: A_OK on success + @notes: user must supply HTC packets for capturing incomming HTC frames. The caller + must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL() + macro. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Connect to an HTC service + @function name: HTCConnectService + @input: HTCHandle - HTC handle + pReq - connection details + @output: pResp - connection response + @return: + @notes: Service connections must be performed before HTCStart. User provides callback handlers + for various endpoint events. + @example: + @see also: HTCStart ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCConnectService(HTC_HANDLE HTCHandle, + HTC_SERVICE_CONNECT_REQ *pReq, + HTC_SERVICE_CONNECT_RESP *pResp); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Send an HTC packet + @function name: HTCSendPkt + @input: HTCHandle - HTC handle + pPacket - packet to send + @output: + @return: A_OK + @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro. + This interface is fully asynchronous. On error, HTC SendPkt will + call the registered Endpoint callback to cleanup the packet. + @example: + @see also: HTCFlushEndpoint ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Stop HTC service communications + @function name: HTCStop + @input: HTCHandle - HTC handle + @output: + @return: + @notes: HTC communications is halted. All receive and pending TX packets will + be flushed. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCStop(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Destory HTC service + @function name: HTCDestroy + @input: HTCHandle + @output: + @return: + @notes: This cleans up all resources allocated by HTCCreate(). + @example: + @see also: HTCCreate ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDestroy(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Flush pending TX packets + @function name: HTCFlushEndpoint + @input: HTCHandle - HTC handle + Endpoint - Endpoint to flush + Tag - flush tag + @output: + @return: + @notes: The Tag parameter is used to selectively flush packets with matching tags. + The value of 0 forces all packets to be flush regardless of tag. + @example: + @see also: HTCSendPkt ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Dump credit distribution state + @function name: HTCDumpCreditStates + @input: HTCHandle - HTC handle + @output: + @return: + @notes: This dumps all credit distribution information to the debugger + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCDumpCreditStates(HTC_HANDLE HTCHandle); +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Indicate a traffic activity change on an endpoint + @function name: HTCIndicateActivityChange + @input: HTCHandle - HTC handle + Endpoint - endpoint in which activity has changed + Active - TRUE if active, FALSE if it has become inactive + @output: + @return: + @notes: This triggers the registered credit distribution function to + re-adjust credits for active/inactive endpoints. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCIndicateActivityChange(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + A_BOOL Active); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get endpoint statistics + @function name: HTCGetEndpointStatistics + @input: HTCHandle - HTC handle + Endpoint - Endpoint identifier + Action - action to take with statistics + @output: + pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR) + + @return: TRUE if statistics profiling is enabled, otherwise FALSE. + + @notes: Statistics is a compile-time option and this function may return FALSE + if HTC is not compiled with profiling. + + The caller can specify the statistic "action" to take when sampling + the statistics. This includes: + + HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values. + HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics + are cleared. + HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for + pStats + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint, + HTC_ENDPOINT_STAT_ACTION Action, + HTC_ENDPOINT_STATS *pStats); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Unblock HTC message reception + @function name: HTCUnblockRecv + @input: HTCHandle - HTC handle + @output: + @return: + @notes: + HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet. + The caller can use this API to indicate to HTC when resources (buffers) are available + such that the receiver can be unblocked and HTC may re-attempt fetching the pending message. + + This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket() + API to recycle or provide receive packets to HTC. + + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +void HTCUnblockRecv(HTC_HANDLE HTCHandle); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: send a series of HTC packets + @function name: HTCSendPktsMultiple + @input: HTCHandle - HTC handle + pPktQueue - local queue holding packets to send + @output: + @return: A_OK + @notes: Caller must initialize each packet using SET_HTC_PACKET_INFO_TX() macro. + The queue must only contain packets directed at the same endpoint. + Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the TX packets in FIFO order. + This API will remove the packets from the pkt queue and place them into the HTC Tx Queue + and bundle messages where possible. + The caller may allocate the pkt queue on the stack to hold the packets. + This interface is fully asynchronous. On error, HTCSendPkts will + call the registered Endpoint callback to cleanup the packet. + @example: + @see also: HTCFlushEndpoint ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCSendPktsMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Add multiple receive packets to HTC + @function name: HTCAddReceivePktMultiple + @input: HTCHandle - HTC handle + pPktQueue - HTC receive packet queue holding packets to add + @output: + @return: A_OK on success + @notes: user must supply HTC packets for capturing incomming HTC frames. The caller + must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL() + macro. The queue must only contain recv packets for the same endpoint. + Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the recv packet. + This API will remove the packets from the pkt queue and place them into internal + recv packet list. + The caller may allocate the pkt queue on the stack to hold the packets. + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_STATUS HTCAddReceivePktMultiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue); + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Check if an endpoint is marked active + @function name: HTCIsEndpointActive + @input: HTCHandle - HTC handle + Endpoint - endpoint to check for active state + @output: + @return: returns TRUE if Endpoint is Active + @notes: + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +A_BOOL HTCIsEndpointActive(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint); + + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + @desc: Get the number of recv buffers currently queued into an HTC endpoint + @function name: HTCGetNumRecvBuffers + @input: HTCHandle - HTC handle + Endpoint - endpoint to check + @output: + @return: returns number of buffers in queue + @notes: + @example: + @see also: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ +int HTCGetNumRecvBuffers(HTC_HANDLE HTCHandle, + HTC_ENDPOINT_ID Endpoint); + +/* internally used functions for testing... */ +void HTCEnableRecv(HTC_HANDLE HTCHandle); +void HTCDisableRecv(HTC_HANDLE HTCHandle); + +#ifdef __cplusplus +} +#endif + +#endif /* _HTC_API_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/htc_packet.h b/drivers/net/wireless/ath6kl/include/htc_packet.h new file mode 100644 index 000000000000..26b20f2183f3 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/htc_packet.h @@ -0,0 +1,223 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef HTC_PACKET_H_ +#define HTC_PACKET_H_ + + +#include "dl_list.h" + +/* ------ Endpoint IDS ------ */ +typedef enum +{ + ENDPOINT_UNUSED = -1, + ENDPOINT_0 = 0, + ENDPOINT_1 = 1, + ENDPOINT_2 = 2, + ENDPOINT_3, + ENDPOINT_4, + ENDPOINT_5, + ENDPOINT_6, + ENDPOINT_7, + ENDPOINT_8, + ENDPOINT_MAX, +} HTC_ENDPOINT_ID; + +struct _HTC_PACKET; + +typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *); + +typedef A_UINT16 HTC_TX_TAG; + +typedef struct _HTC_TX_PACKET_INFO { + HTC_TX_TAG Tag; /* tag used to selective flush packets */ + int CreditsUsed; /* number of credits used for this TX packet (HTC internal) */ + A_UINT8 SendFlags; /* send flags (HTC internal) */ + int SeqNo; /* internal seq no for debugging (HTC internal) */ +} HTC_TX_PACKET_INFO; + +#define HTC_TX_PACKET_TAG_ALL 0 /* a tag of zero is reserved and used to flush ALL packets */ +#define HTC_TX_PACKET_TAG_INTERNAL 1 /* internal tags start here */ +#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */ + +typedef struct _HTC_RX_PACKET_INFO { + A_UINT32 ExpectedHdr; /* HTC internal use */ + A_UINT32 HTCRxFlags; /* HTC internal use */ + A_UINT32 IndicationFlags; /* indication flags set on each RX packet indication */ +} HTC_RX_PACKET_INFO; + +#define HTC_RX_FLAGS_INDICATE_MORE_PKTS (1 << 0) /* more packets on this endpoint are being fetched */ + +/* wrapper around endpoint-specific packets */ +typedef struct _HTC_PACKET { + DL_LIST ListLink; /* double link */ + void *pPktContext; /* caller's per packet specific context */ + + A_UINT8 *pBufferStart; /* the true buffer start , the caller can + store the real buffer start here. In + receive callbacks, the HTC layer sets pBuffer + to the start of the payload past the header. This + field allows the caller to reset pBuffer when it + recycles receive packets back to HTC */ + /* + * Pointer to the start of the buffer. In the transmit + * direction this points to the start of the payload. In the + * receive direction, however, the buffer when queued up + * points to the start of the HTC header but when returned + * to the caller points to the start of the payload + */ + A_UINT8 *pBuffer; /* payload start (RX/TX) */ + A_UINT32 BufferLength; /* length of buffer */ + A_UINT32 ActualLength; /* actual length of payload */ + HTC_ENDPOINT_ID Endpoint; /* endpoint that this packet was sent/recv'd from */ + A_STATUS Status; /* completion status */ + union { + HTC_TX_PACKET_INFO AsTx; /* Tx Packet specific info */ + HTC_RX_PACKET_INFO AsRx; /* Rx Packet specific info */ + } PktInfo; + + /* the following fields are for internal HTC use */ + HTC_PACKET_COMPLETION Completion; /* completion */ + void *pContext; /* HTC private completion context */ +} HTC_PACKET; + + + +#define COMPLETE_HTC_PACKET(p,status) \ +{ \ + (p)->Status = (status); \ + (p)->Completion((p)->pContext,(p)); \ +} + +#define INIT_HTC_PACKET_INFO(p,b,len) \ +{ \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ +} + +/* macro to set an initial RX packet for refilling HTC */ +#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->pBufferStart = (b); \ + (p)->BufferLength = (len); \ + (p)->Endpoint = (ep); \ +} + +/* fast macro to recycle an RX packet that will be re-queued to HTC */ +#define HTC_PACKET_RESET_RX(p) \ + { (p)->pBuffer = (p)->pBufferStart; (p)->ActualLength = 0; } + +/* macro to set packet parameters for TX */ +#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag) \ +{ \ + (p)->pPktContext = (c); \ + (p)->pBuffer = (b); \ + (p)->ActualLength = (len); \ + (p)->Endpoint = (ep); \ + (p)->PktInfo.AsTx.Tag = (tag); \ +} + +/* HTC Packet Queueing Macros */ +typedef struct _HTC_PACKET_QUEUE { + DL_LIST QueueHead; + int Depth; +} HTC_PACKET_QUEUE; + +/* initialize queue */ +#define INIT_HTC_PACKET_QUEUE(pQ) \ +{ \ + DL_LIST_INIT(&(pQ)->QueueHead); \ + (pQ)->Depth = 0; \ +} + +/* enqueue HTC packet to the tail of the queue */ +#define HTC_PACKET_ENQUEUE(pQ,p) \ +{ DL_ListInsertTail(&(pQ)->QueueHead,&(p)->ListLink); \ + (pQ)->Depth++; \ +} + +/* enqueue HTC packet to the tail of the queue */ +#define HTC_PACKET_ENQUEUE_TO_HEAD(pQ,p) \ +{ DL_ListInsertHead(&(pQ)->QueueHead,&(p)->ListLink); \ + (pQ)->Depth++; \ +} +/* test if a queue is empty */ +#define HTC_QUEUE_EMPTY(pQ) ((pQ)->Depth == 0) +/* get packet at head without removing it */ +static INLINE HTC_PACKET *HTC_GET_PKT_AT_HEAD(HTC_PACKET_QUEUE *queue) { + if (queue->Depth == 0) { + return NULL; + } + return A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(&queue->QueueHead)),HTC_PACKET,ListLink); +} +/* remove a packet from a queue, where-ever it is in the queue */ +#define HTC_PACKET_REMOVE(pQ,p) \ +{ \ + DL_ListRemove(&(p)->ListLink); \ + (pQ)->Depth--; \ +} + +/* dequeue an HTC packet from the head of the queue */ +static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) { + DL_LIST *pItem = DL_ListRemoveItemFromHead(&queue->QueueHead); + if (pItem != NULL) { + queue->Depth--; + return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink); + } + return NULL; +} + +/* dequeue an HTC packet from the tail of the queue */ +static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE_TAIL(HTC_PACKET_QUEUE *queue) { + DL_LIST *pItem = DL_ListRemoveItemFromTail(&queue->QueueHead); + if (pItem != NULL) { + queue->Depth--; + return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink); + } + return NULL; +} + +#define HTC_PACKET_QUEUE_DEPTH(pQ) (pQ)->Depth + + +#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint +#define HTC_GET_TAG_FROM_PKT(p) (p)->PktInfo.AsTx.Tag + + /* transfer the packets from one queue to the tail of another queue */ +#define HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(pQDest,pQSrc) \ +{ \ + DL_ListTransferItemsToTail(&(pQDest)->QueueHead,&(pQSrc)->QueueHead); \ + (pQDest)->Depth += (pQSrc)->Depth; \ + (pQSrc)->Depth = 0; \ +} + + /* fast version to init and add a single packet to a queue */ +#define INIT_HTC_PACKET_QUEUE_AND_ADD(pQ,pP) \ +{ \ + DL_LIST_INIT_AND_ADD(&(pQ)->QueueHead,&(pP)->ListLink) \ + (pQ)->Depth = 1; \ +} + +#define HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pQ, pPTemp) \ + ITERATE_OVER_LIST_ALLOW_REMOVE(&(pQ)->QueueHead,(pPTemp), HTC_PACKET, ListLink) + +#define HTC_PACKET_QUEUE_ITERATE_END ITERATE_END + +#endif /*HTC_PACKET_H_*/ diff --git a/drivers/net/wireless/ath6kl/include/htc_services.h b/drivers/net/wireless/ath6kl/include/htc_services.h new file mode 100644 index 000000000000..4457d6634f26 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/htc_services.h @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum { + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +}HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group,index) \ + (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) +#define WMI_MAX_SERVICES 5 + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) + +#endif /*HTC_SERVICES_H_*/ diff --git a/drivers/net/wireless/ath6kl/include/ini_dset.h b/drivers/net/wireless/ath6kl/include/ini_dset.h new file mode 100644 index 000000000000..fcd5a68fdac3 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/ini_dset.h @@ -0,0 +1,80 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _INI_DSET_H_ +#define _INI_DSET_H_ + +/* + * Each of these represents a WHAL INI table, which consists + * of an "address column" followed by 1 or more "value columns". + * + * Software uses the base WHAL_INI_DATA_ID+column to access a + * DataSet that holds a particular column of data. + */ +typedef enum { +#if defined(AR6002_REV4) || defined(AR6003) +/* Add these definitions for compatability */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */ + WHAL_INI_DATA_ID_COMMON =6, /* 7 */ + WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */ +#ifdef FPGA + WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */ + WHAL_INI_DATA_ID_ADDAC =25, /* 26 */ +#else + WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21,22,23 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */ +#endif /* FPGA */ +#else + WHAL_INI_DATA_ID_NULL =0, + WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */ + WHAL_INI_DATA_ID_COMMON =4, /* 5 */ + WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */ +#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN + WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */ + WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */ + WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */ + WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */ + WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */ + WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */ + WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */ + WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */ + WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */ +#endif + WHAL_INI_DATA_ID_MAX =31 +} WHAL_INI_DATA_ID; + +typedef PREPACK struct { + A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common + A_UINT16 offset; + A_UINT32 newValue; +} POSTPACK INI_DSET_REG_OVERRIDE; + +#endif diff --git a/drivers/net/wireless/ath6kl/include/pkt_log.h b/drivers/net/wireless/ath6kl/include/pkt_log.h new file mode 100644 index 000000000000..1fcc1cb2750a --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/pkt_log.h @@ -0,0 +1,41 @@ +//------------------------------------------------------------------------------ +// Copyright (c) 2005 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __PKT_LOG_H__ +#define __PKT_LOG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Pkt log info */ +typedef PREPACK struct pkt_log_t { + struct info_t { + A_UINT16 st; + A_UINT16 end; + A_UINT16 cur; + }info[4096]; + A_UINT16 last_idx; +}POSTPACK PACKET_LOG; + + +#ifdef __cplusplus +} +#endif +#endif /* __PKT_LOG_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/regdump.h b/drivers/net/wireless/ath6kl/include/regdump.h new file mode 100644 index 000000000000..09755cd2874d --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/regdump.h @@ -0,0 +1,45 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ +#if defined(AR6001) +#include "AR6001/AR6001_regdump.h" +#endif +#if defined(AR6002) +#include "AR6002/AR6002_regdump.h" +#endif + +#if !defined(__ASSEMBLER__) +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +struct register_dump_s { + A_UINT32 target_id; /* Target ID */ + A_UINT32 assline; /* Line number (if assertion failure) */ + A_UINT32 pc; /* Program Counter at time of exception */ + A_UINT32 badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +}; +#endif /* __ASSEMBLER__ */ +#endif /* __REGDUMP_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/roaming.h b/drivers/net/wireless/ath6kl/include/roaming.h new file mode 100644 index 000000000000..88c1bd278490 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/roaming.h @@ -0,0 +1,37 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef _ROAMING_H_ +#define _ROAMING_H_ + +/* + * The signal quality could be in terms of either snr or rssi. We should + * have an enum for both of them. For the time being, we are going to move + * it to wmi.h that is shared by both host and the target, since we are + * repartitioning the code to the host + */ +#define SIGNAL_QUALITY_NOISE_FLOOR -96 +#define SIGNAL_QUALITY_METRICS_NUM_MAX 2 +typedef enum { + SIGNAL_QUALITY_METRICS_SNR = 0, + SIGNAL_QUALITY_METRICS_RSSI, + SIGNAL_QUALITY_METRICS_ALL, +} SIGNAL_QUALITY_METRICS_TYPE; + +#endif /* _ROAMING_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/targaddrs.h b/drivers/net/wireless/ath6kl/include/targaddrs.h new file mode 100644 index 000000000000..7b27ca2a78fe --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/targaddrs.h @@ -0,0 +1,232 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2010 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __TARGADDRS_H__ +#define __TARGADDRS_H__ +#if defined(AR6001) +#include "AR6001/addrs.h" +#endif +#if defined(AR6002) +#include "AR6002/addrs.h" +#endif + +/* + * AR6K option bits, to enable/disable various features. + * By default, all option bits are 0. + * These bits can be set in LOCAL_SCRATCH register 0. + */ +#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ +#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ +#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ +#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ +#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ +#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ +#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ +#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ + +/* + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the + * host_interest structure. It must match the address of the _host_interest + * symbol (see linker script). + * + * Host Interest is shared between Host and Target in order to coordinate + * between the two, and is intended to remain constant (with additions only + * at the end) across software releases. + * + * All addresses are available here so that it's possible to + * write a single binary that works with all Target Types. + * May be used in assembler code as well as C. + */ +#define AR6001_HOST_INTEREST_ADDRESS 0x80000600 +#define AR6002_HOST_INTEREST_ADDRESS 0x00500400 +#define AR6003_HOST_INTEREST_ADDRESS 0x00540600 + + +#define HOST_INTEREST_MAX_SIZE 0x100 + +#if !defined(__ASSEMBLER__) +struct register_dump_s; +struct dbglog_hdr_s; + +/* + * These are items that the Host may need to access + * via BMI or via the Diagnostic Window. The position + * of items in this structure must remain constant + * across firmware revisions! + * + * Types for each item must be fixed size across + * target and host platforms. + * + * More items may be added at the end. + */ +struct host_interest_s { + /* + * Pointer to application-defined area, if any. + * Set by Target application during startup. + */ + A_UINT32 hi_app_host_interest; /* 0x00 */ + + /* Pointer to register dump area, valid after Target crash. */ + A_UINT32 hi_failure_state; /* 0x04 */ + + /* Pointer to debug logging header */ + A_UINT32 hi_dbglog_hdr; /* 0x08 */ + + /* Indicates whether or not flash is present on Target. + * NB: flash_is_present indicator is here not just + * because it might be of interest to the Host; but + * also because it's set early on by Target's startup + * asm code and we need it to have a special RAM address + * so that it doesn't get reinitialized with the rest + * of data. + */ + A_UINT32 hi_flash_is_present; /* 0x0c */ + + /* + * General-purpose flag bits, similar to AR6000_OPTION_* flags. + * Can be used by application rather than by OS. + */ + A_UINT32 hi_option_flag; /* 0x10 */ + + /* + * Boolean that determines whether or not to + * display messages on the serial port. + */ + A_UINT32 hi_serial_enable; /* 0x14 */ + + /* Start address of Flash DataSet index, if any */ + A_UINT32 hi_dset_list_head; /* 0x18 */ + + /* Override Target application start address */ + A_UINT32 hi_app_start; /* 0x1c */ + + /* Clock and voltage tuning */ + A_UINT32 hi_skip_clock_init; /* 0x20 */ + A_UINT32 hi_core_clock_setting; /* 0x24 */ + A_UINT32 hi_cpu_clock_setting; /* 0x28 */ + A_UINT32 hi_system_sleep_setting; /* 0x2c */ + A_UINT32 hi_xtal_control_setting; /* 0x30 */ + A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ + A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ + A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ + A_UINT32 hi_clock_info; /* 0x40 */ + + /* + * Flash configuration overrides, used only + * when firmware is not executing from flash. + * (When using flash, modify the global variables + * with equivalent names.) + */ + A_UINT32 hi_bank0_addr_value; /* 0x44 */ + A_UINT32 hi_bank0_read_value; /* 0x48 */ + A_UINT32 hi_bank0_write_value; /* 0x4c */ + A_UINT32 hi_bank0_config_value; /* 0x50 */ + + /* Pointer to Board Data */ + A_UINT32 hi_board_data; /* 0x54 */ + A_UINT32 hi_board_data_initialized; /* 0x58 */ + + A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ + + A_UINT32 hi_desired_baud_rate; /* 0x60 */ + A_UINT32 hi_dbglog_config; /* 0x64 */ + A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ + A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ + + A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ + A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ + + A_UINT32 hi_refclk_hz; /* 0x78 */ + A_UINT32 hi_ext_clk_detected; /* 0x7c */ + A_UINT32 hi_dbg_uart_txpin; /* 0x80 */ + A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */ + A_UINT32 hi_hci_uart_baud; /* 0x88 */ + A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */ + /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ + A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */ + A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */ + + A_UINT32 hi_allocram_start; /* 0x98 */ + A_UINT32 hi_allocram_sz; /* 0x9c */ + A_UINT32 hi_hci_bridge_flags; /* 0xa0 */ + A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */ + /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ +}; + +/* Bits defined in hi_option_flag */ +#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ +#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ +#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ +#define HI_OPTION_FW_MODE_LSB 0x08 /* low bit of MODE (see below) */ +#define HI_OPTION_FW_MODE_MSB 0x10 /* high bit of MODE (see below) */ +#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ +#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ +#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ + +/* 2 bits of hi_option_flag are used to represent 3 modes */ +#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ +#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ +#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ + +/* Fw Mode Mask */ +#define HI_OPTION_FW_MODE_MASK 0x3 +#define HI_OPTION_FW_MODE_SHIFT 0x3 + +/* + * Intended for use by Host software, this macro returns the Target RAM + * address of any item in the host_interest structure. + * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); + */ +#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item))) + +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) + +#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ + ((A_UINT32)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) + +#define HOST_INTEREST_DBGLOG_IS_ENABLED() \ + (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) + +#define HOST_INTEREST_PROFILE_IS_ENABLED() \ + (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) + +/* Convert a Target virtual address into a Target physical address */ +#define AR6001_VTOP(vaddr) ((vaddr) & 0x0fffffff) +#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) +#define TARG_VTOP(TargetType, vaddr) \ + (((TargetType) == TARGET_TYPE_AR6001) ? AR6001_VTOP(vaddr) : \ + (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))) + +/* override REV2 ROM's app start address */ +#define AR6002_REV2_APP_START_OVERRIDE 0x911A00 +#define AR6003_REV1_APP_START_OVERRIDE 0x944c00 +#define AR6003_REV1_OTP_DATA_ADDRESS 0x542800 +#define AR6003_REV2_APP_START_OVERRIDE 0x945000 +#define AR6003_REV2_OTP_DATA_ADDRESS 0x543800 + + +/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */ +#define AR6003_FETCH_TARG_REGS_COUNT 64 + +#endif /* !__ASSEMBLER__ */ + +#endif /* __TARGADDRS_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/target_reg_table.h b/drivers/net/wireless/ath6kl/include/target_reg_table.h new file mode 100644 index 000000000000..4105b9c418cf --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/target_reg_table.h @@ -0,0 +1,236 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Target register table macros and structure definitions +// +// Author(s): ="Atheros" +//============================================================================== + +#ifndef TARGET_REG_TABLE_H_ +#define TARGET_REG_TABLE_H_ + +#include "targaddrs.h" + +/*** WARNING : Add to the end of the TABLE! do not change the order ****/ +typedef struct targetdef_s { + A_UINT32 d_RTC_BASE_ADDRESS; + A_UINT32 d_SYSTEM_SLEEP_OFFSET; + A_UINT32 d_SYSTEM_SLEEP_DISABLE_LSB; + A_UINT32 d_SYSTEM_SLEEP_DISABLE_MASK; + A_UINT32 d_CLOCK_CONTROL_OFFSET; + A_UINT32 d_CLOCK_CONTROL_SI0_CLK_MASK; + A_UINT32 d_RESET_CONTROL_OFFSET; + A_UINT32 d_RESET_CONTROL_SI0_RST_MASK; + A_UINT32 d_GPIO_BASE_ADDRESS; + A_UINT32 d_GPIO_PIN0_OFFSET; + A_UINT32 d_GPIO_PIN1_OFFSET; + A_UINT32 d_GPIO_PIN0_CONFIG_MASK; + A_UINT32 d_GPIO_PIN1_CONFIG_MASK; + A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_LSB; + A_UINT32 d_SI_CONFIG_BIDIR_OD_DATA_MASK; + A_UINT32 d_SI_CONFIG_I2C_LSB; + A_UINT32 d_SI_CONFIG_I2C_MASK; + A_UINT32 d_SI_CONFIG_POS_SAMPLE_LSB; + A_UINT32 d_SI_CONFIG_POS_SAMPLE_MASK; + A_UINT32 d_SI_CONFIG_INACTIVE_CLK_LSB; + A_UINT32 d_SI_CONFIG_INACTIVE_CLK_MASK; + A_UINT32 d_SI_CONFIG_INACTIVE_DATA_LSB; + A_UINT32 d_SI_CONFIG_INACTIVE_DATA_MASK; + A_UINT32 d_SI_CONFIG_DIVIDER_LSB; + A_UINT32 d_SI_CONFIG_DIVIDER_MASK; + A_UINT32 d_SI_BASE_ADDRESS; + A_UINT32 d_SI_CONFIG_OFFSET; + A_UINT32 d_SI_TX_DATA0_OFFSET; + A_UINT32 d_SI_TX_DATA1_OFFSET; + A_UINT32 d_SI_RX_DATA0_OFFSET; + A_UINT32 d_SI_RX_DATA1_OFFSET; + A_UINT32 d_SI_CS_OFFSET; + A_UINT32 d_SI_CS_DONE_ERR_MASK; + A_UINT32 d_SI_CS_DONE_INT_MASK; + A_UINT32 d_SI_CS_START_LSB; + A_UINT32 d_SI_CS_START_MASK; + A_UINT32 d_SI_CS_RX_CNT_LSB; + A_UINT32 d_SI_CS_RX_CNT_MASK; + A_UINT32 d_SI_CS_TX_CNT_LSB; + A_UINT32 d_SI_CS_TX_CNT_MASK; + A_UINT32 d_BOARD_DATA_SZ; +} TARGET_REGISTER_TABLE; + +#define BOARD_DATA_SZ_MAX 2048 + +#if defined(MY_TARGET_DEF) /* { */ + +#ifdef ATH_REG_TABLE_DIRECT_ASSIGN + +static struct targetdef_s my_target_def = { + RTC_BASE_ADDRESS, + SYSTEM_SLEEP_OFFSET, + SYSTEM_SLEEP_DISABLE_LSB, + SYSTEM_SLEEP_DISABLE_MASK, + CLOCK_CONTROL_OFFSET, + CLOCK_CONTROL_SI0_CLK_MASK, + RESET_CONTROL_OFFSET, + RESET_CONTROL_SI0_RST_MASK, + GPIO_BASE_ADDRESS, + GPIO_PIN0_OFFSET, + GPIO_PIN0_CONFIG_MASK, + GPIO_PIN1_OFFSET, + GPIO_PIN1_CONFIG_MASK, + SI_CONFIG_BIDIR_OD_DATA_LSB, + SI_CONFIG_BIDIR_OD_DATA_MASK, + SI_CONFIG_I2C_LSB, + SI_CONFIG_I2C_MASK, + SI_CONFIG_POS_SAMPLE_LSB, + SI_CONFIG_POS_SAMPLE_MASK, + SI_CONFIG_INACTIVE_CLK_LSB, + SI_CONFIG_INACTIVE_CLK_MASK, + SI_CONFIG_INACTIVE_DATA_LSB, + SI_CONFIG_INACTIVE_DATA_MASK, + SI_CONFIG_DIVIDER_LSB, + SI_CONFIG_DIVIDER_MASK, + SI_BASE_ADDRESS, + SI_CONFIG_OFFSET, + SI_TX_DATA0_OFFSET, + SI_TX_DATA1_OFFSET, + SI_RX_DATA0_OFFSET, + SI_RX_DATA1_OFFSET, + SI_CS_OFFSET, + SI_CS_DONE_ERR_MASK, + SI_CS_DONE_INT_MASK, + SI_CS_START_LSB, + SI_CS_START_MASK, + SI_CS_RX_CNT_LSB, + SI_CS_RX_CNT_MASK, + SI_CS_TX_CNT_LSB, + SI_CS_TX_CNT_MASK, + MY_TARGET_BOARD_DATA_SZ, +}; + +#else + +static struct targetdef_s my_target_def = { + .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS, + .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET, + .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB, + .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK, + .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET, + .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK, + .d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET, + .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK, + .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS, + .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET, + .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK, + .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET, + .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK, + .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB, + .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK, + .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB, + .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK, + .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB, + .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK, + .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB, + .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK, + .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB, + .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK, + .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB, + .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK, + .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS, + .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET, + .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET, + .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET, + .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET, + .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET, + .d_SI_CS_OFFSET = SI_CS_OFFSET, + .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK, + .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK, + .d_SI_CS_START_LSB = SI_CS_START_LSB, + .d_SI_CS_START_MASK = SI_CS_START_MASK, + .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB, + .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK, + .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB, + .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK, + .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ, +}; + +#endif + +#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX +#error "BOARD_DATA_SZ_MAX is too small" +#endif + +struct targetdef_s *MY_TARGET_DEF = &my_target_def; + +#else /* } { */ + +#define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS) +#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET) +#define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB) +#define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK) +#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET) +#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) +#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET) +#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK) +#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS) +#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET) +#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK) +#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET) +#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) +#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB) +#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) +#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) +#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) +#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB) +#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK) +#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS) +#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET) +#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET) +#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET) +#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET) +#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET) +#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET) +#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK) +#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK) +#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB) +#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK) +#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB) +#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB) +#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK) +#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ) + +/* SET macros */ +#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) +#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) +#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) +#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) +#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) +#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) +#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) +#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) +#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) +#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) + +#endif /* } */ + +#endif /*TARGET_REG_TABLE_H_*/ + + diff --git a/drivers/net/wireless/ath6kl/include/testcmd.h b/drivers/net/wireless/ath6kl/include/testcmd.h new file mode 100644 index 000000000000..49f2cf380296 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/testcmd.h @@ -0,0 +1,179 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2005 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef TESTCMD_H_ +#define TESTCMD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef AR6002_REV2 +#define TCMD_MAX_RATES 12 +#else +#define TCMD_MAX_RATES 28 +#endif + +typedef enum { + ZEROES_PATTERN = 0, + ONES_PATTERN, + REPEATING_10, + PN7_PATTERN, + PN9_PATTERN, + PN15_PATTERN +}TX_DATA_PATTERN; + +/* Continous tx + mode : TCMD_CONT_TX_OFF - Disabling continous tx + TCMD_CONT_TX_SINE - Enable continuous unmodulated tx + TCMD_CONT_TX_FRAME- Enable continuous modulated tx + freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g) +dataRate: 0 - 1 Mbps + 1 - 2 Mbps + 2 - 5.5 Mbps + 3 - 11 Mbps + 4 - 6 Mbps + 5 - 9 Mbps + 6 - 12 Mbps + 7 - 18 Mbps + 8 - 24 Mbps + 9 - 36 Mbps + 10 - 28 Mbps + 11 - 54 Mbps + txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx +antenna: 1 - one antenna + 2 - two antenna +Note : Enable/disable continuous tx test cmd works only when target is awake. +*/ + +typedef enum { + TCMD_CONT_TX_OFF = 0, + TCMD_CONT_TX_SINE, + TCMD_CONT_TX_FRAME, + TCMD_CONT_TX_TX99, + TCMD_CONT_TX_TX100 +} TCMD_CONT_TX_MODE; + +typedef enum { + TCMD_WLAN_MODE_HT20 = 0, + TCMD_WLAN_MODE_HT40PLUS = 1, + TCMD_WLAN_MODE_HT40MINUS = 2, +} TCMD_WLAN_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; + A_UINT32 freq; + A_UINT32 dataRate; + A_INT32 txPwr; + A_UINT32 antenna; + A_UINT32 enANI; + A_UINT32 scramblerOff; + A_UINT32 aifsn; + A_UINT16 pktSz; + A_UINT16 txPattern; + A_UINT32 shortGuard; + A_UINT32 numPackets; + A_UINT32 wlanMode; +} POSTPACK TCMD_CONT_TX; + +#define TCMD_TXPATTERN_ZERONE 0x1 +#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2 + +/* Continuous Rx + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames) + TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest + address equal specified + mac address (set via act =3) + TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the + report from the last cont + Rx test) + + TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the + target. This Overrides + the default MAC address.) + +*/ +typedef enum { + TCMD_CONT_RX_PROMIS =0, + TCMD_CONT_RX_FILTER, + TCMD_CONT_RX_REPORT, + TCMD_CONT_RX_SETMAC, + TCMD_CONT_RX_SET_ANT_SWITCH_TABLE +} TCMD_CONT_RX_ACT; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 act; + A_UINT32 enANI; + PREPACK union { + struct PREPACK TCMD_CONT_RX_PARA { + A_UINT32 freq; + A_UINT32 antenna; + A_UINT32 wlanMode; + } POSTPACK para; + struct PREPACK TCMD_CONT_RX_REPORT { + A_UINT32 totalPkt; + A_INT32 rssiInDBm; + A_UINT32 crcErrPkt; + A_UINT32 secErrPkt; + A_UINT16 rateCnt[TCMD_MAX_RATES]; + A_UINT16 rateCntShortGuard[TCMD_MAX_RATES]; + } POSTPACK report; + struct PREPACK TCMD_CONT_RX_MAC { + A_UCHAR addr[ATH_MAC_LEN]; + } POSTPACK mac; + struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE { + A_UINT32 antswitch1; + A_UINT32 antswitch2; + }POSTPACK antswitchtable; + } POSTPACK u; +} POSTPACK TCMD_CONT_RX; + +/* Force sleep/wake test cmd + mode: TCMD_PM_WAKEUP - Wakeup the target + TCMD_PM_SLEEP - Force the target to sleep. + */ +typedef enum { + TCMD_PM_WAKEUP = 1, /* be consistent with target */ + TCMD_PM_SLEEP +} TCMD_PM_MODE; + +typedef PREPACK struct { + A_UINT32 testCmdId; + A_UINT32 mode; +} POSTPACK TCMD_PM; + +typedef enum { + TCMD_CONT_TX_ID, + TCMD_CONT_RX_ID, + TCMD_PM_ID +} TCMD_ID; + +typedef PREPACK union { + TCMD_CONT_TX contTx; + TCMD_CONT_RX contRx; + TCMD_PM pm; +} POSTPACK TEST_CMD; + +#ifdef __cplusplus +} +#endif + +#endif /* TESTCMD_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/wlan_api.h b/drivers/net/wireless/ath6kl/include/wlan_api.h new file mode 100644 index 000000000000..aa17b3e1de12 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/wlan_api.h @@ -0,0 +1,122 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the API for the host wlan module +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_WLAN_API_H_ +#define _HOST_WLAN_API_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +struct ieee80211_node_table; +struct ieee80211_frame; + +struct ieee80211_common_ie { + A_UINT16 ie_chan; + A_UINT8 *ie_tstamp; + A_UINT8 *ie_ssid; + A_UINT8 *ie_rates; + A_UINT8 *ie_xrates; + A_UINT8 *ie_country; + A_UINT8 *ie_wpa; + A_UINT8 *ie_rsn; + A_UINT8 *ie_wmm; + A_UINT8 *ie_ath; + A_UINT16 ie_capInfo; + A_UINT16 ie_beaconInt; + A_UINT8 *ie_tim; + A_UINT8 *ie_chswitch; + A_UINT8 ie_erp; + A_UINT8 *ie_wsc; + A_UINT8 *ie_htcap; + A_UINT8 *ie_htop; +#ifdef WAPI_ENABLE + A_UINT8 *ie_wapi; +#endif +}; + +typedef struct bss { + A_UINT8 ni_macaddr[6]; + A_UINT8 ni_snr; + A_INT16 ni_rssi; + struct bss *ni_list_next; + struct bss *ni_list_prev; + struct bss *ni_hash_next; + struct bss *ni_hash_prev; + struct ieee80211_common_ie ni_cie; + A_UINT8 *ni_buf; + A_UINT16 ni_framelen; + struct ieee80211_node_table *ni_table; + A_UINT32 ni_refcnt; + int ni_scangen; + + A_UINT32 ni_tstamp; +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 ni_si_gen; +#endif +} bss_t; + +typedef void wlan_node_iter_func(void *arg, bss_t *); + +bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size); +void wlan_node_free(bss_t *ni); +void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr); +bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr); +void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni); +void wlan_free_allnodes(struct ieee80211_node_table *nt); +void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg); + +void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt); +void wlan_node_table_reset(struct ieee80211_node_table *nt); +void wlan_node_table_cleanup(struct ieee80211_node_table *nt); + +A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen, + struct ieee80211_common_ie *cie); + +A_UINT16 wlan_ieee2freq(int chan); +A_UINT32 wlan_freq2ieee(A_UINT16 freq); + +void wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge); + + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni); + +bss_t *wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid); + +bss_t * +wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode, + A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp); + +#ifdef __cplusplus +} +#endif + +#endif /* _HOST_WLAN_API_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/wlan_defs.h b/drivers/net/wireless/ath6kl/include/wlan_defs.h new file mode 100644 index 000000000000..1fe4b113a427 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/wlan_defs.h @@ -0,0 +1,75 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef __WLAN_DEFS_H__ +#define __WLAN_DEFS_H__ + +/* + * This file contains WLAN definitions that may be used across both + * Host and Target software. + */ + +typedef enum { + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11b/g Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ +#ifdef SUPPORT_11N + MODE_11NA_HT20 = 4, /* 11a HT20 mode */ + MODE_11NG_HT20 = 5, /* 11g HT20 mode */ + MODE_11NA_HT40 = 6, /* 11a HT40 mode */ + MODE_11NG_HT40 = 7, /* 11g HT40 mode */ + MODE_UNKNOWN = 8, + MODE_MAX = 8 +#else + MODE_UNKNOWN = 4, + MODE_MAX = 4 +#endif +} WLAN_PHY_MODE; + +typedef enum { + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3, +}WLAN_CAPABILITY; + +#ifdef SUPPORT_11N +typedef unsigned long A_RATEMASK; +#else +typedef unsigned short A_RATEMASK; +#endif + +#ifdef SUPPORT_11N +#define IS_MODE_11A(mode) (((mode) == MODE_11A) || \ + ((mode) == MODE_11NA_HT20) || \ + ((mode) == MODE_11NA_HT40)) +#define IS_MODE_11B(mode) ((mode) == MODE_11B) +#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ + ((mode) == MODE_11GONLY) || \ + ((mode) == MODE_11NG_HT20) || \ + ((mode) == MODE_11NG_HT40)) +#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) +#else +#define IS_MODE_11A(mode) ((mode) == MODE_11A) +#define IS_MODE_11B(mode) ((mode) == MODE_11B) +#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ + ((mode) == MODE_11GONLY)) +#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) +#endif /* SUPPORT_11N */ + +#endif /* __WLANDEFS_H__ */ diff --git a/drivers/net/wireless/ath6kl/include/wlan_dset.h b/drivers/net/wireless/ath6kl/include/wlan_dset.h new file mode 100644 index 000000000000..e5f9b2480c15 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/wlan_dset.h @@ -0,0 +1,30 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#ifndef __WLAN_DSET_H__ +#define __WLAN_DSET_H__ + +typedef PREPACK struct wow_config_dset { + + A_UINT8 valid_dset; + A_UINT8 gpio_enable; + A_UINT16 gpio_pin; +} POSTPACK WOW_CONFIG_DSET; + +#endif diff --git a/drivers/net/wireless/ath6kl/include/wmi.h b/drivers/net/wireless/ath6kl/include/wmi.h new file mode 100644 index 000000000000..7b140d8118b4 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/wmi.h @@ -0,0 +1,3053 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to commands + * belongs to the host driver and the WMI is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_H_ +#define _WMI_H_ + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "wmix.h" +#include "wlan_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HTC_PROTOCOL_VERSION 0x0002 +#define HTC_PROTOCOL_REVISION 0x0000 + +#define WMI_PROTOCOL_VERSION 0x0002 +#define WMI_PROTOCOL_REVISION 0x0000 + +#define ATH_MAC_LEN 6 /* length of mac in bytes */ +#define WMI_CMD_MAX_LEN 100 +#define WMI_CONTROL_MSG_MAX_LEN 256 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) +#define RFC1042OUI {0x00, 0x00, 0x00} + +#define IP_ETHERTYPE 0x0800 + +#define WMI_IMPLICIT_PSTREAM 0xFF +#define WMI_MAX_THINSTREAM 15 + +#ifdef AR6002_REV2 +#define IBSS_MAX_NUM_STA 4 +#else +#define IBSS_MAX_NUM_STA 8 +#endif + +struct host_app_area_s { + A_UINT32 wmi_protocol_ver; +}; + +/* + * Data Path + */ +typedef PREPACK struct { + A_UINT8 dstMac[ATH_MAC_LEN]; + A_UINT8 srcMac[ATH_MAC_LEN]; + A_UINT16 typeOrLen; +} POSTPACK ATH_MAC_HDR; + +typedef PREPACK struct { + A_UINT8 dsap; + A_UINT8 ssap; + A_UINT8 cntl; + A_UINT8 orgCode[3]; + A_UINT16 etherType; +} POSTPACK ATH_LLC_SNAP_HDR; + +typedef enum { + DATA_MSGTYPE = 0x0, + CNTL_MSGTYPE, + SYNC_MSGTYPE, + OPT_MSGTYPE, +} WMI_MSG_TYPE; + + +/* + * Macros for operating on WMI_DATA_HDR (info) field + */ + +#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 +#define WMI_DATA_HDR_UP_MASK 0x07 +#define WMI_DATA_HDR_UP_SHIFT 2 +/* In AP mode, the same bit (b5) is used to indicate Power save state in + * the Rx dir and More data bit state in the tx direction. + */ +#define WMI_DATA_HDR_PS_MASK 0x1 +#define WMI_DATA_HDR_PS_SHIFT 5 + +#define WMI_DATA_HDR_MORE_MASK 0x1 +#define WMI_DATA_HDR_MORE_SHIFT 5 + +typedef enum { + WMI_DATA_HDR_DATA_TYPE_802_3 = 0, + WMI_DATA_HDR_DATA_TYPE_802_11, + WMI_DATA_HDR_DATA_TYPE_ACL, +} WMI_DATA_HDR_DATA_TYPE; + +#define WMI_DATA_HDR_DATA_TYPE_MASK 0x3 +#define WMI_DATA_HDR_DATA_TYPE_SHIFT 6 + +#define WMI_DATA_HDR_SET_MORE_BIT(h) ((h)->info |= (WMI_DATA_HDR_MORE_MASK << WMI_DATA_HDR_MORE_SHIFT)) + +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) +#define WMI_DATA_HDR_GET_UP(h) (((h)->info >> WMI_DATA_HDR_UP_SHIFT) & WMI_DATA_HDR_UP_MASK) +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) + +#define WMI_DATA_HDR_GET_DATA_TYPE(h) (((h)->info >> WMI_DATA_HDR_DATA_TYPE_SHIFT) & WMI_DATA_HDR_DATA_TYPE_MASK) +#define WMI_DATA_HDR_SET_DATA_TYPE(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_DATA_TYPE_MASK << WMI_DATA_HDR_DATA_TYPE_SHIFT)) | ((p) << WMI_DATA_HDR_DATA_TYPE_SHIFT)) + +#define WMI_DATA_HDR_GET_DOT11(h) (WMI_DATA_HDR_GET_DATA_TYPE((h)) == WMI_DATA_HDR_DATA_TYPE_802_11) +#define WMI_DATA_HDR_SET_DOT11(h, p) WMI_DATA_HDR_SET_DATA_TYPE((h), (p)) + +/* Macros for operating on WMI_DATA_HDR (info2) field */ +#define WMI_DATA_HDR_SEQNO_MASK 0xFFF +#define WMI_DATA_HDR_SEQNO_SHIFT 0 + +#define WMI_DATA_HDR_AMSDU_MASK 0x1 +#define WMI_DATA_HDR_AMSDU_SHIFT 12 + +#define WMI_DATA_HDR_META_MASK 0x7 +#define WMI_DATA_HDR_META_SHIFT 13 + +#define GET_SEQ_NO(_v) ((_v) & WMI_DATA_HDR_SEQNO_MASK) +#define GET_ISMSDU(_v) ((_v) & WMI_DATA_HDR_AMSDU_MASK) + +#define WMI_DATA_HDR_GET_SEQNO(h) GET_SEQ_NO((h)->info2 >> WMI_DATA_HDR_SEQNO_SHIFT) +#define WMI_DATA_HDR_SET_SEQNO(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_SEQNO_MASK << WMI_DATA_HDR_SEQNO_SHIFT)) | (GET_SEQ_NO(_v) << WMI_DATA_HDR_SEQNO_SHIFT)) + +#define WMI_DATA_HDR_IS_AMSDU(h) GET_ISMSDU((h)->info2 >> WMI_DATA_HDR_AMSDU_SHIFT) +#define WMI_DATA_HDR_SET_AMSDU(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_AMSDU_MASK << WMI_DATA_HDR_AMSDU_SHIFT)) | (GET_ISMSDU(_v) << WMI_DATA_HDR_AMSDU_SHIFT)) + +#define WMI_DATA_HDR_GET_META(h) (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK) +#define WMI_DATA_HDR_SET_META(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | ((_v) << WMI_DATA_HDR_META_SHIFT)) + +typedef PREPACK struct { + A_INT8 rssi; + A_UINT8 info; /* usage of 'info' field(8-bit): + * b1:b0 - WMI_MSG_TYPE + * b4:b3:b2 - UP(tid) + * b5 - Used in AP mode. More-data in tx dir, PS in rx. + * b7:b6 - Dot3 header(0), + * Dot11 Header(1), + * ACL data(2) + */ + + A_UINT16 info2; /* usage of 'info2' field(16-bit): + * b11:b0 - seq_no + * b12 - A-MSDU? + * b15:b13 - META_DATA_VERSION 0 - 7 + */ + A_UINT16 reserved; +} POSTPACK WMI_DATA_HDR; + +/* + * TX META VERSION DEFINITIONS + */ +#define WMI_MAX_TX_META_SZ (12) +#define WMI_MAX_TX_META_VERSION (7) +#define WMI_META_VERSION_1 (0x01) +#define WMI_META_VERSION_2 (0X02) + +#define WMI_ACL_TO_DOT11_HEADROOM 36 + +#if 0 /* removed to prevent compile errors for WM.. */ +typedef PREPACK struct { +/* intentionally empty. Default version is no meta data. */ +} POSTPACK WMI_TX_META_V0; +#endif + +typedef PREPACK struct { + A_UINT8 pktID; /* The packet ID to identify the tx request */ + A_UINT8 ratePolicyID; /* The rate policy to be used for the tx of this frame */ +} POSTPACK WMI_TX_META_V1; + + +#define WMI_CSUM_DIR_TX (0x1) +#define TX_CSUM_CALC_FILL (0x1) +typedef PREPACK struct { + A_UINT8 csumStart; /*Offset from start of the WMI header for csum calculation to begin */ + A_UINT8 csumDest; /*Offset from start of WMI header where final csum goes*/ + A_UINT8 csumFlags; /*number of bytes over which csum is calculated*/ +} POSTPACK WMI_TX_META_V2; + + +/* + * RX META VERSION DEFINITIONS + */ +/* if RX meta data is present at all then the meta data field + * will consume WMI_MAX_RX_META_SZ bytes of space between the + * WMI_DATA_HDR and the payload. How much of the available + * Meta data is actually used depends on which meta data + * version is active. */ +#define WMI_MAX_RX_META_SZ (12) +#define WMI_MAX_RX_META_VERSION (7) + +#define WMI_RX_STATUS_OK 0 /* success */ +#define WMI_RX_STATUS_DECRYPT_ERR 1 /* decrypt error */ +#define WMI_RX_STATUS_MIC_ERR 2 /* tkip MIC error */ +#define WMI_RX_STATUS_ERR 3 /* undefined error */ + +#define WMI_RX_FLAGS_AGGR 0x0001 /* part of AGGR */ +#define WMI_RX_FlAGS_STBC 0x0002 /* used STBC */ +#define WMI_RX_FLAGS_SGI 0x0004 /* used SGI */ +#define WMI_RX_FLAGS_HT 0x0008 /* is HT packet */ +/* the flags field is also used to store the CRYPTO_TYPE of the frame + * that value is shifted by WMI_RX_FLAGS_CRYPTO_SHIFT */ +#define WMI_RX_FLAGS_CRYPTO_SHIFT 4 +#define WMI_RX_FLAGS_CRYPTO_MASK 0x1f +#define WMI_RX_META_GET_CRYPTO(flags) (((flags) >> WMI_RX_FLAGS_CRYPTO_SHIFT) & WMI_RX_FLAGS_CRYPTO_MASK) + +#if 0 /* removed to prevent compile errors for WM.. */ +typedef PREPACK struct { +/* intentionally empty. Default version is no meta data. */ +} POSTPACK WMI_RX_META_VERSION_0; +#endif + +typedef PREPACK struct { + A_UINT8 status; /* one of WMI_RX_STATUS_... */ + A_UINT8 rix; /* rate index mapped to rate at which this packet was received. */ + A_UINT8 rssi; /* rssi of packet */ + A_UINT8 channel;/* rf channel during packet reception */ + A_UINT16 flags; /* a combination of WMI_RX_FLAGS_... */ +} POSTPACK WMI_RX_META_V1; + +#define RX_CSUM_VALID_FLAG (0x1) +typedef PREPACK struct { + A_UINT16 csum; + A_UINT8 csumFlags;/* bit 0 set -partial csum valid + bit 1 set -test mode */ +} POSTPACK WMI_RX_META_V2; + + + +#define WMI_GET_DEVICE_ID(info1) ((info1) & 0xF) + +/* + * Control Path + */ +typedef PREPACK struct { + A_UINT16 commandId; +/* + * info1 - 16 bits + * b03:b00 - id + * b15:b04 - unused + */ + A_UINT16 info1; + + A_UINT16 reserved; /* For alignment */ +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + +/* + * List of Commnands + */ +typedef enum { + WMI_CONNECT_CMDID = 0x0001, + WMI_RECONNECT_CMDID, + WMI_DISCONNECT_CMDID, + WMI_SYNCHRONIZE_CMDID, + WMI_CREATE_PSTREAM_CMDID, + WMI_DELETE_PSTREAM_CMDID, + WMI_START_SCAN_CMDID, + WMI_SET_SCAN_PARAMS_CMDID, + WMI_SET_BSS_FILTER_CMDID, + WMI_SET_PROBED_SSID_CMDID, /* 10 */ + WMI_SET_LISTEN_INT_CMDID, + WMI_SET_BMISS_TIME_CMDID, + WMI_SET_DISC_TIMEOUT_CMDID, + WMI_GET_CHANNEL_LIST_CMDID, + WMI_SET_BEACON_INT_CMDID, + WMI_GET_STATISTICS_CMDID, + WMI_SET_CHANNEL_PARAMS_CMDID, + WMI_SET_POWER_MODE_CMDID, + WMI_SET_IBSS_PM_CAPS_CMDID, + WMI_SET_POWER_PARAMS_CMDID, /* 20 */ + WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + WMI_ADD_CIPHER_KEY_CMDID, + WMI_DELETE_CIPHER_KEY_CMDID, + WMI_ADD_KRK_CMDID, + WMI_DELETE_KRK_CMDID, + WMI_SET_PMKID_CMDID, + WMI_SET_TX_PWR_CMDID, + WMI_GET_TX_PWR_CMDID, + WMI_SET_ASSOC_INFO_CMDID, + WMI_ADD_BAD_AP_CMDID, /* 30 */ + WMI_DELETE_BAD_AP_CMDID, + WMI_SET_TKIP_COUNTERMEASURES_CMDID, + WMI_RSSI_THRESHOLD_PARAMS_CMDID, + WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + WMI_SET_ACCESS_PARAMS_CMDID, + WMI_SET_RETRY_LIMITS_CMDID, + WMI_SET_OPT_MODE_CMDID, + WMI_OPT_TX_FRAME_CMDID, + WMI_SET_VOICE_PKT_SIZE_CMDID, + WMI_SET_MAX_SP_LEN_CMDID, /* 40 */ + WMI_SET_ROAM_CTRL_CMDID, + WMI_GET_ROAM_TBL_CMDID, + WMI_GET_ROAM_DATA_CMDID, + WMI_ENABLE_RM_CMDID, + WMI_SET_MAX_OFFHOME_DURATION_CMDID, + WMI_EXTENSION_CMDID, /* Non-wireless extensions */ + WMI_SNR_THRESHOLD_PARAMS_CMDID, + WMI_LQ_THRESHOLD_PARAMS_CMDID, + WMI_SET_LPREAMBLE_CMDID, + WMI_SET_RTS_CMDID, /* 50 */ + WMI_CLR_RSSI_SNR_CMDID, + WMI_SET_FIXRATES_CMDID, + WMI_GET_FIXRATES_CMDID, + WMI_SET_AUTH_MODE_CMDID, + WMI_SET_REASSOC_MODE_CMDID, + WMI_SET_WMM_CMDID, + WMI_SET_WMM_TXOP_CMDID, + WMI_TEST_CMDID, + /* COEX AR6002 only*/ + WMI_SET_BT_STATUS_CMDID, + WMI_SET_BT_PARAMS_CMDID, /* 60 */ + + WMI_SET_KEEPALIVE_CMDID, + WMI_GET_KEEPALIVE_CMDID, + WMI_SET_APPIE_CMDID, + WMI_GET_APPIE_CMDID, + WMI_SET_WSC_STATUS_CMDID, + + /* Wake on Wireless */ + WMI_SET_HOST_SLEEP_MODE_CMDID, + WMI_SET_WOW_MODE_CMDID, + WMI_GET_WOW_LIST_CMDID, + WMI_ADD_WOW_PATTERN_CMDID, + WMI_DEL_WOW_PATTERN_CMDID, /* 70 */ + + WMI_SET_FRAMERATES_CMDID, + WMI_SET_AP_PS_CMDID, + WMI_SET_QOS_SUPP_CMDID, + /* WMI_THIN_RESERVED_... mark the start and end + * values for WMI_THIN_RESERVED command IDs. These + * command IDs can be found in wmi_thin.h */ + WMI_THIN_RESERVED_START = 0x8000, + WMI_THIN_RESERVED_END = 0x8fff, + /* + * Developer commands starts at 0xF000 + */ + WMI_SET_BITRATE_CMDID = 0xF000, + WMI_GET_BITRATE_CMDID, + WMI_SET_WHALPARAM_CMDID, + + + /*Should add the new command to the tail for compatible with + * etna. + */ + WMI_SET_MAC_ADDRESS_CMDID, + WMI_SET_AKMP_PARAMS_CMDID, + WMI_SET_PMKID_LIST_CMDID, + WMI_GET_PMKID_LIST_CMDID, + WMI_ABORT_SCAN_CMDID, + WMI_SET_TARGET_EVENT_REPORT_CMDID, + + // Unused + WMI_UNUSED1, + WMI_UNUSED2, + + /* + * AP mode commands + */ + WMI_AP_HIDDEN_SSID_CMDID, + WMI_AP_SET_NUM_STA_CMDID, + WMI_AP_ACL_POLICY_CMDID, + WMI_AP_ACL_MAC_LIST_CMDID, + WMI_AP_CONFIG_COMMIT_CMDID, + WMI_AP_SET_MLME_CMDID, + WMI_AP_SET_PVB_CMDID, + WMI_AP_CONN_INACT_CMDID, + WMI_AP_PROT_SCAN_TIME_CMDID, + WMI_AP_SET_COUNTRY_CMDID, + WMI_AP_SET_DTIM_CMDID, + WMI_AP_MODE_STAT_CMDID, + + WMI_SET_IP_CMDID, + WMI_SET_PARAMS_CMDID, + WMI_SET_MCAST_FILTER_CMDID, + WMI_DEL_MCAST_FILTER_CMDID, + + WMI_ALLOW_AGGR_CMDID, + WMI_ADDBA_REQ_CMDID, + WMI_DELBA_REQ_CMDID, + WMI_SET_HT_CAP_CMDID, + WMI_SET_HT_OP_CMDID, + WMI_SET_TX_SELECT_RATES_CMDID, + WMI_SET_TX_SGI_PARAM_CMDID, + WMI_SET_RATE_POLICY_CMDID, + + WMI_HCI_CMD_CMDID, + WMI_RX_FRAME_FORMAT_CMDID, + WMI_SET_THIN_MODE_CMDID, + WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID, + + WMI_AP_SET_11BG_RATESET_CMDID, + WMI_SET_PMK_CMDID, + WMI_MCAST_FILTER_CMDID, + /* COEX CMDID AR6003*/ + WMI_SET_BTCOEX_FE_ANT_CMDID, + WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID, + WMI_SET_BTCOEX_SCO_CONFIG_CMDID, + WMI_SET_BTCOEX_A2DP_CONFIG_CMDID, + WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID, + WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID, + WMI_SET_BTCOEX_DEBUG_CMDID, + WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID, + WMI_GET_BTCOEX_STATS_CMDID, + WMI_GET_BTCOEX_CONFIG_CMDID +} WMI_COMMAND_ID; + +/* + * Frame Types + */ +typedef enum { + WMI_FRAME_BEACON = 0, + WMI_FRAME_PROBE_REQ, + WMI_FRAME_PROBE_RESP, + WMI_FRAME_ASSOC_REQ, + WMI_FRAME_ASSOC_RESP, + WMI_NUM_MGMT_FRAME +} WMI_MGMT_FRAME_TYPE; + +/* + * Connect Command + */ +typedef enum { + INFRA_NETWORK = 0x01, + ADHOC_NETWORK = 0x02, + ADHOC_CREATOR = 0x04, + AP_NETWORK = 0x10, +} NETWORK_TYPE; + +typedef enum { + OPEN_AUTH = 0x01, + SHARED_AUTH = 0x02, + LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ +} DOT11_AUTH_MODE; + +typedef enum { + NONE_AUTH = 0x01, + WPA_AUTH = 0x02, + WPA2_AUTH = 0x04, + WPA_PSK_AUTH = 0x08, + WPA2_PSK_AUTH = 0x10, + WPA_AUTH_CCKM = 0x20, + WPA2_AUTH_CCKM = 0x40, +} AUTH_MODE; + +typedef enum { + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x04, + AES_CRYPT = 0x08, +#ifdef WAPI_ENABLE + WAPI_CRYPT = 0x10, +#endif /*WAPI_ENABLE*/ +} CRYPTO_TYPE; + +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) + +#ifdef WAPI_ENABLE +#undef WMI_MAX_CRYPTO_TYPE +#define WMI_MAX_CRYPTO_TYPE (WAPI_CRYPT + 1) +#endif /* WAPI_ENABLE */ + +#ifdef WAPI_ENABLE +#define IW_ENCODE_ALG_SM4 0x20 +#define IW_AUTH_WAPI_ENABLED 0x20 +#endif + +#define WMI_MIN_KEY_INDEX 0 +#define WMI_MAX_KEY_INDEX 3 + +#ifdef WAPI_ENABLE +#undef WMI_MAX_KEY_INDEX +#define WMI_MAX_KEY_INDEX 7 /* wapi grpKey 0-3, prwKey 4-7 */ +#endif /* WAPI_ENABLE */ + +#define WMI_MAX_KEY_LEN 32 + +#define WMI_MAX_SSID_LEN 32 + +typedef enum { + CONNECT_ASSOC_POLICY_USER = 0x0001, + CONNECT_SEND_REASSOC = 0x0002, + CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, + CONNECT_PROFILE_MATCH_DONE = 0x0008, + CONNECT_IGNORE_AAC_BEACON = 0x0010, + CONNECT_CSA_FOLLOW_BSS = 0x0020, + CONNECT_DO_WPA_OFFLOAD = 0x0040, + CONNECT_DO_NOT_DEAUTH = 0x0080, +} WMI_CONNECT_CTRL_FLAGS_BITS; + +#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) + +typedef PREPACK struct { + A_UINT8 networkType; + A_UINT8 dot11AuthMode; + A_UINT8 authMode; + A_UINT8 pairwiseCryptoType; + A_UINT8 pairwiseCryptoLen; + A_UINT8 groupCryptoType; + A_UINT8 groupCryptoLen; + A_UINT8 ssidLength; + A_UCHAR ssid[WMI_MAX_SSID_LEN]; + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ctrl_flags; +} POSTPACK WMI_CONNECT_CMD; + +/* + * WMI_RECONNECT_CMDID + */ +typedef PREPACK struct { + A_UINT16 channel; /* hint */ + A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */ +} POSTPACK WMI_RECONNECT_CMD; + +#define WMI_PMK_LEN 32 +typedef PREPACK struct { + A_UINT8 pmk[WMI_PMK_LEN]; +} POSTPACK WMI_SET_PMK_CMD; + +/* + * WMI_ADD_CIPHER_KEY_CMDID + */ +typedef enum { + PAIRWISE_USAGE = 0x00, + GROUP_USAGE = 0x01, + TX_USAGE = 0x02, /* default Tx Key - Static WEP only */ +} KEY_USAGE; + +/* + * Bit Flag + * Bit 0 - Initialise TSC - default is Initialize + */ +#define KEY_OP_INIT_TSC 0x01 +#define KEY_OP_INIT_RSC 0x02 +#ifdef WAPI_ENABLE +#define KEY_OP_INIT_WAPIPN 0x10 +#endif /* WAPI_ENABLE */ + +#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */ +#define KEY_OP_VALID_MASK 0x03 + +typedef PREPACK struct { + A_UINT8 keyIndex; + A_UINT8 keyType; + A_UINT8 keyUsage; /* KEY_USAGE */ + A_UINT8 keyLength; + A_UINT8 keyRSC[8]; /* key replay sequence counter */ + A_UINT8 key[WMI_MAX_KEY_LEN]; + A_UINT8 key_op_ctrl; /* Additional Key Control information */ + A_UINT8 key_macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_CIPHER_KEY_CMD; + +/* + * WMI_DELETE_CIPHER_KEY_CMDID + */ +typedef PREPACK struct { + A_UINT8 keyIndex; +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD; + +#define WMI_KRK_LEN 16 +/* + * WMI_ADD_KRK_CMDID + */ +typedef PREPACK struct { + A_UINT8 krk[WMI_KRK_LEN]; +} POSTPACK WMI_ADD_KRK_CMD; + +/* + * WMI_SET_TKIP_COUNTERMEASURES_CMDID + */ +typedef enum { + WMI_TKIP_CM_DISABLE = 0x0, + WMI_TKIP_CM_ENABLE = 0x1, +} WMI_TKIP_CM_CONTROL; + +typedef PREPACK struct { + A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */ +} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD; + +/* + * WMI_SET_PMKID_CMDID + */ + +#define WMI_PMKID_LEN 16 + +typedef enum { + PMKID_DISABLE = 0, + PMKID_ENABLE = 1, +} PMKID_ENABLE_FLG; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 enable; /* PMKID_ENABLE_FLG */ + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_SET_PMKID_CMD; + +/* + * WMI_START_SCAN_CMD + */ +typedef enum { + WMI_LONG_SCAN = 0, + WMI_SHORT_SCAN = 1, +} WMI_SCAN_TYPE; + +typedef PREPACK struct { + A_BOOL forceFgScan; + A_BOOL isLegacy; /* For Legacy Cisco AP compatibility */ + A_UINT32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */ + A_UINT32 forceScanInterval; /* Time interval between scans (milliseconds)*/ + A_UINT8 scanType; /* WMI_SCAN_TYPE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_START_SCAN_CMD; + +/* + * WMI_SET_SCAN_PARAMS_CMDID + */ +#define WMI_SHORTSCANRATIO_DEFAULT 3 +/* + * Warning: ScanCtrlFlag value of 0xFF is used to disable all flags in WMI_SCAN_PARAMS_CMD + * Do not add any more flags to WMI_SCAN_CTRL_FLAG_BITS + */ +typedef enum { + CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */ + SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */ + /* already connected to */ + ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */ + ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */ + REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */ + ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't + scan after a disconnect event */ + ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */ +} WMI_SCAN_CTRL_FLAGS_BITS; + +#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS) +#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS) +#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS) +#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS) +#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS) +#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS) +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT) + +#define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS) + + +typedef PREPACK struct { + A_UINT16 fg_start_period; /* seconds */ + A_UINT16 fg_end_period; /* seconds */ + A_UINT16 bg_period; /* seconds */ + A_UINT16 maxact_chdwell_time; /* msec */ + A_UINT16 pas_chdwell_time; /* msec */ + A_UINT8 shortScanRatio; /* how many shorts scan for one long */ + A_UINT8 scanCtrlFlags; + A_UINT16 minact_chdwell_time; /* msec */ + A_UINT16 maxact_scan_per_ssid; /* max active scans per ssid */ + A_UINT32 max_dfsch_act_time; /* msecs */ +} POSTPACK WMI_SCAN_PARAMS_CMD; + +/* + * WMI_SET_BSS_FILTER_CMDID + */ +typedef enum { + NONE_BSS_FILTER = 0x0, /* no beacons forwarded */ + ALL_BSS_FILTER, /* all beacons forwarded */ + PROFILE_FILTER, /* only beacons matching profile */ + ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */ + CURRENT_BSS_FILTER, /* only beacons matching current BSS */ + ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */ + PROBED_SSID_FILTER, /* beacons matching probed ssid */ + LAST_BSS_FILTER, /* marker only */ +} WMI_BSS_FILTER; + +typedef PREPACK struct { + A_UINT8 bssFilter; /* see WMI_BSS_FILTER */ + A_UINT8 reserved1; /* For alignment */ + A_UINT16 reserved2; /* For alignment */ + A_UINT32 ieMask; +} POSTPACK WMI_BSS_FILTER_CMD; + +/* + * WMI_SET_PROBED_SSID_CMDID + */ +#define MAX_PROBED_SSID_INDEX 9 + +typedef enum { + DISABLE_SSID_FLAG = 0, /* disables entry */ + SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */ + ANY_SSID_FLAG = 0x02, /* probes for any ssid */ +} WMI_SSID_FLAG; + +typedef PREPACK struct { + A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */ + A_UINT8 flag; /* WMI_SSID_FLG */ + A_UINT8 ssidLength; + A_UINT8 ssid[32]; +} POSTPACK WMI_PROBED_SSID_CMD; + +/* + * WMI_SET_LISTEN_INT_CMDID + * The Listen interval is between 15 and 3000 TUs + */ +#define MIN_LISTEN_INTERVAL 15 +#define MAX_LISTEN_INTERVAL 5000 +#define MIN_LISTEN_BEACONS 1 +#define MAX_LISTEN_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 listenInterval; + A_UINT16 numBeacons; +} POSTPACK WMI_LISTEN_INT_CMD; + +/* + * WMI_SET_BEACON_INT_CMDID + */ +typedef PREPACK struct { + A_UINT16 beaconInterval; +} POSTPACK WMI_BEACON_INT_CMD; + +/* + * WMI_SET_BMISS_TIME_CMDID + * valid values are between 1000 and 5000 TUs + */ + +#define MIN_BMISS_TIME 1000 +#define MAX_BMISS_TIME 5000 +#define MIN_BMISS_BEACONS 1 +#define MAX_BMISS_BEACONS 50 + +typedef PREPACK struct { + A_UINT16 bmissTime; + A_UINT16 numBeacons; +} POSTPACK WMI_BMISS_TIME_CMD; + +/* + * WMI_SET_POWER_MODE_CMDID + */ +typedef enum { + REC_POWER = 0x01, + MAX_PERF_POWER, +} WMI_POWER_MODE; + +typedef PREPACK struct { + A_UINT8 powerMode; /* WMI_POWER_MODE */ +} POSTPACK WMI_POWER_MODE_CMD; + +typedef PREPACK struct { + A_INT8 status; /* WMI_SET_PARAMS_REPLY */ +} POSTPACK WMI_SET_PARAMS_REPLY; + +typedef PREPACK struct { + A_UINT32 opcode; + A_UINT32 length; + A_CHAR buffer[1]; /* WMI_SET_PARAMS */ +} POSTPACK WMI_SET_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 multicast_mac[ATH_MAC_LEN]; /* WMI_SET_MCAST_FILTER */ +} POSTPACK WMI_SET_MCAST_FILTER_CMD; + +typedef PREPACK struct { + A_UINT8 enable; /* WMI_MCAST_FILTER */ +} POSTPACK WMI_MCAST_FILTER_CMD; + +/* + * WMI_SET_POWER_PARAMS_CMDID + */ +typedef enum { + IGNORE_DTIM = 0x01, + NORMAL_DTIM = 0x02, + STICK_DTIM = 0x03, + AUTO_DTIM = 0x04, +} WMI_DTIM_POLICY; + +/* Policy to determnine whether TX should wakeup WLAN if sleeping */ +typedef enum { + TX_WAKEUP_UPON_SLEEP = 1, + TX_DONT_WAKEUP_UPON_SLEEP = 2 +} WMI_TX_WAKEUP_POLICY_UPON_SLEEP; + +/* + * Policy to determnine whether power save failure event should be sent to + * host during scanning + */ +typedef enum { + SEND_POWER_SAVE_FAIL_EVENT_ALWAYS = 1, + IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN = 2, +} POWER_SAVE_FAIL_EVENT_POLICY; + +typedef PREPACK struct { + A_UINT16 idle_period; /* msec */ + A_UINT16 pspoll_number; + A_UINT16 dtim_policy; + A_UINT16 tx_wakeup_policy; + A_UINT16 num_tx_to_wakeup; + A_UINT16 ps_fail_event_policy; +} POSTPACK WMI_POWER_PARAMS_CMD; + +/* Adhoc power save types */ +typedef enum { + ADHOC_PS_DISABLE=1, + ADHOC_PS_ATH=2, + ADHOC_PS_IEEE=3, + ADHOC_PS_OTHER=4, +} WMI_ADHOC_PS_TYPE; + +typedef PREPACK struct { + A_UINT8 power_saving; + A_UINT8 ttl; /* number of beacon periods */ + A_UINT16 atim_windows; /* msec */ + A_UINT16 timeout_value; /* msec */ +} POSTPACK WMI_IBSS_PM_CAPS_CMD; + +/* AP power save types */ +typedef enum { + AP_PS_DISABLE=1, + AP_PS_ATH=2, +} WMI_AP_PS_TYPE; + +typedef PREPACK struct { + A_UINT32 idle_time; /* in msec */ + A_UINT32 ps_period; /* in usec */ + A_UINT8 sleep_period; /* in ps periods */ + A_UINT8 psType; +} POSTPACK WMI_AP_PS_CMD; + +/* + * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID + */ +typedef enum { + IGNORE_TIM_ALL_QUEUES_APSD = 0, + PROCESS_TIM_ALL_QUEUES_APSD = 1, + IGNORE_TIM_SIMULATED_APSD = 2, + PROCESS_TIM_SIMULATED_APSD = 3, +} APSD_TIM_POLICY; + +typedef PREPACK struct { + A_UINT16 psPollTimeout; /* msec */ + A_UINT16 triggerTimeout; /* msec */ + A_UINT32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */ + A_UINT32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */ +} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD; + +/* + * WMI_SET_VOICE_PKT_SIZE_CMDID + */ +typedef PREPACK struct { + A_UINT16 voicePktSize; +} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD; + +/* + * WMI_SET_MAX_SP_LEN_CMDID + */ +typedef enum { + DELIVER_ALL_PKT = 0x0, + DELIVER_2_PKT = 0x1, + DELIVER_4_PKT = 0x2, + DELIVER_6_PKT = 0x3, +} APSD_SP_LEN_TYPE; + +typedef PREPACK struct { + A_UINT8 maxSPLen; +} POSTPACK WMI_SET_MAX_SP_LEN_CMD; + +/* + * WMI_SET_DISC_TIMEOUT_CMDID + */ +typedef PREPACK struct { + A_UINT8 disconnectTimeout; /* seconds */ +} POSTPACK WMI_DISC_TIMEOUT_CMD; + +typedef enum { + UPLINK_TRAFFIC = 0, + DNLINK_TRAFFIC = 1, + BIDIR_TRAFFIC = 2, +} DIR_TYPE; + +typedef enum { + DISABLE_FOR_THIS_AC = 0, + ENABLE_FOR_THIS_AC = 1, + ENABLE_FOR_ALL_AC = 2, +} VOICEPS_CAP_TYPE; + +typedef enum { + TRAFFIC_TYPE_APERIODIC = 0, + TRAFFIC_TYPE_PERIODIC = 1, +}TRAFFIC_TYPE; + +/* + * WMI_SYNCHRONIZE_CMDID + */ +typedef PREPACK struct { + A_UINT8 dataSyncMap; +} POSTPACK WMI_SYNC_CMD; + +/* + * WMI_CREATE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT32 minServiceInt; /* in milli-sec */ + A_UINT32 maxServiceInt; /* in milli-sec */ + A_UINT32 inactivityInt; /* in milli-sec */ + A_UINT32 suspensionInt; /* in milli-sec */ + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; /* in bps */ + A_UINT32 meanDataRate; /* in bps */ + A_UINT32 peakDataRate; /* in bps */ + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; /* in bps */ + A_UINT32 sba; + A_UINT32 mediumTime; + A_UINT16 nominalMSDU; /* in octects */ + A_UINT16 maxMSDU; /* in octects */ + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 rxQueueNum; + A_UINT8 trafficType; /* TRAFFIC_TYPE */ + A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */ + A_UINT8 tsid; + A_UINT8 userPriority; /* 802.1D user priority */ + A_UINT8 nominalPHY; /* nominal phy rate */ +} POSTPACK WMI_CREATE_PSTREAM_CMD; + +/* + * WMI_DELETE_PSTREAM_CMDID + */ +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; + A_UINT8 tsid; +} POSTPACK WMI_DELETE_PSTREAM_CMD; + +/* + * WMI_SET_CHANNEL_PARAMS_CMDID + */ +typedef enum { + WMI_11A_MODE = 0x1, + WMI_11G_MODE = 0x2, + WMI_11AG_MODE = 0x3, + WMI_11B_MODE = 0x4, + WMI_11GONLY_MODE = 0x5, +} WMI_PHY_MODE; + +#define WMI_MAX_CHANNELS 32 + +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 scanParam; /* set if enable scan */ + A_UINT8 phyMode; /* see WMI_PHY_MODE */ + A_UINT8 numChannels; /* how many channels follow */ + A_UINT16 channelList[1]; /* channels in Mhz */ +} POSTPACK WMI_CHANNEL_PARAMS_CMD; + + +/* + * WMI_RSSI_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + * Threshold values are in the ascending order, and should agree to: + * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal + * < highThreshold_upperVal) + */ + +typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_INT16 thresholdAbove1_Val; /* lowest of upper */ + A_INT16 thresholdAbove2_Val; + A_INT16 thresholdAbove3_Val; + A_INT16 thresholdAbove4_Val; + A_INT16 thresholdAbove5_Val; + A_INT16 thresholdAbove6_Val; /* highest of upper */ + A_INT16 thresholdBelow1_Val; /* lowest of bellow */ + A_INT16 thresholdBelow2_Val; + A_INT16 thresholdBelow3_Val; + A_INT16 thresholdBelow4_Val; + A_INT16 thresholdBelow5_Val; + A_INT16 thresholdBelow6_Val; /* highest of bellow */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 reserved[3]; +} POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD; + +/* + * WMI_SNR_THRESHOLD_PARAMS_CMDID + * Setting the polltime to 0 would disable polling. + */ + +typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{ + A_UINT32 pollTime; /* Polling time as a factor of LI */ + A_UINT8 weight; /* "alpha" */ + A_UINT8 thresholdAbove1_Val; /* lowest of uppper*/ + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; /* highest of upper */ + A_UINT8 thresholdBelow1_Val; /* lowest of bellow */ + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; /* highest of bellow */ + A_UINT8 reserved[3]; +} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD; + +/* + * WMI_LQ_THRESHOLD_PARAMS_CMDID + */ +typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS { + A_UINT8 enable; + A_UINT8 thresholdAbove1_Val; + A_UINT8 thresholdAbove2_Val; + A_UINT8 thresholdAbove3_Val; + A_UINT8 thresholdAbove4_Val; + A_UINT8 thresholdBelow1_Val; + A_UINT8 thresholdBelow2_Val; + A_UINT8 thresholdBelow3_Val; + A_UINT8 thresholdBelow4_Val; + A_UINT8 reserved[3]; +} POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD; + +typedef enum { + WMI_LPREAMBLE_DISABLED = 0, + WMI_LPREAMBLE_ENABLED +} WMI_LPREAMBLE_STATUS; + +typedef enum { + WMI_IGNORE_BARKER_IN_ERP = 0, + WMI_DONOT_IGNORE_BARKER_IN_ERP +} WMI_PREAMBLE_POLICY; + +typedef PREPACK struct { + A_UINT8 status; + A_UINT8 preamblePolicy; +}POSTPACK WMI_SET_LPREAMBLE_CMD; + +typedef PREPACK struct { + A_UINT16 threshold; +}POSTPACK WMI_SET_RTS_CMD; + +/* + * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + * Sets the error reporting event bitmask in target. Target clears it + * upon an error. Subsequent errors are counted, but not reported + * via event, unless the bitmask is set again. + */ +typedef PREPACK struct { + A_UINT32 bitmask; +} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK; + +/* + * WMI_SET_TX_PWR_CMDID + */ +typedef PREPACK struct { + A_UINT8 dbM; /* in dbM units */ +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY; + +/* + * WMI_SET_ASSOC_INFO_CMDID + * + * A maximum of 2 private IEs can be sent in the [Re]Assoc request. + * A 3rd one, the CCX version IE can also be set from the host. + */ +#define WMI_MAX_ASSOC_INFO_TYPE 2 +#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */ + +#define WMI_MAX_ASSOC_INFO_LEN 240 + +typedef PREPACK struct { + A_UINT8 ieType; + A_UINT8 bufferSize; + A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */ +} POSTPACK WMI_SET_ASSOC_INFO_CMD; + + +/* + * WMI_GET_TX_PWR_CMDID does not take any parameters + */ + +/* + * WMI_ADD_BAD_AP_CMDID + */ +#define WMI_MAX_BAD_AP_INDEX 1 + +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_ADD_BAD_AP_CMD; + +/* + * WMI_DELETE_BAD_AP_CMDID + */ +typedef PREPACK struct { + A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */ +} POSTPACK WMI_DELETE_BAD_AP_CMD; + +/* + * WMI_SET_ACCESS_PARAMS_CMDID + */ +#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */ +#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */ +#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */ +#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */ +#define WMI_DEFAULT_AIFSN_ACPARAM 2 +#define WMI_MAX_AIFSN_ACPARAM 15 +typedef PREPACK struct { + A_UINT16 txop; /* in units of 32 usec */ + A_UINT8 eCWmin; + A_UINT8 eCWmax; + A_UINT8 aifsn; + A_UINT8 ac; +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD; + + +/* + * WMI_SET_RETRY_LIMITS_CMDID + * + * This command is used to customize the number of retries the + * wlan device will perform on a given frame. + */ +#define WMI_MIN_RETRIES 2 +#define WMI_MAX_RETRIES 13 +typedef enum { + MGMT_FRAMETYPE = 0, + CONTROL_FRAMETYPE = 1, + DATA_FRAMETYPE = 2 +} WMI_FRAMETYPE; + +typedef PREPACK struct { + A_UINT8 frameType; /* WMI_FRAMETYPE */ + A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */ + A_UINT8 maxRetries; + A_UINT8 enableNotify; +} POSTPACK WMI_SET_RETRY_LIMITS_CMD; + +/* + * WMI_SET_ROAM_CTRL_CMDID + * + * This command is used to influence the Roaming behaviour + * Set the host biases of the BSSs before setting the roam mode as bias + * based. + */ + +/* + * Different types of Roam Control + */ + +typedef enum { + WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */ + WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */ + WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */ + WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */ +} WMI_ROAM_CTRL_TYPE; + +#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM +#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS + +/* + * ROAM MODES + */ + +typedef enum { + WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */ + WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */ + WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */ +} WMI_ROAM_MODE; + +/* + * BSS HOST BIAS INFO + */ + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 bias; +} POSTPACK WMI_BSS_BIAS; + +typedef PREPACK struct { + A_UINT8 numBss; + WMI_BSS_BIAS bssBias[1]; +} POSTPACK WMI_BSS_BIAS_INFO; + +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS { + A_UINT16 lowrssi_scan_period; + A_INT16 lowrssi_scan_threshold; + A_INT16 lowrssi_roam_threshold; + A_UINT8 roam_rssi_floor; + A_UINT8 reserved[1]; /* For alignment */ +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS; + +typedef PREPACK struct { + PREPACK union { + A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */ + A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */ + WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */ + WMI_LOWRSSI_SCAN_PARAMS lrScanParams; + } POSTPACK info; + A_UINT8 roamCtrlType ; +} POSTPACK WMI_SET_ROAM_CTRL_CMD; + +/* + * WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID + */ +typedef enum { + BT_WLAN_CONN_PRECDENCE_WLAN=0, /* Default */ + BT_WLAN_CONN_PRECDENCE_PAL, +} BT_WLAN_CONN_PRECEDENCE; + +typedef PREPACK struct { + A_UINT8 precedence; +} POSTPACK WMI_SET_BT_WLAN_CONN_PRECEDENCE; + +/* + * WMI_ENABLE_RM_CMDID + */ +typedef PREPACK struct { + A_BOOL enable_radio_measurements; +} POSTPACK WMI_ENABLE_RM_CMD; + +/* + * WMI_SET_MAX_OFFHOME_DURATION_CMDID + */ +typedef PREPACK struct { + A_UINT8 max_offhome_duration; +} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD; + +typedef PREPACK struct { + A_UINT32 frequency; + A_UINT8 threshold; +} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD; +/*---------------------- BTCOEX RELATED -------------------------------------*/ +/*----------------------COMMON to AR6002 and AR6003 -------------------------*/ +typedef enum { + BT_STREAM_UNDEF = 0, + BT_STREAM_SCO, /* SCO stream */ + BT_STREAM_A2DP, /* A2DP stream */ + BT_STREAM_SCAN, /* BT Discovery or Page */ + BT_STREAM_ESCO, + BT_STREAM_MAX +} BT_STREAM_TYPE; + +typedef enum { + BT_PARAM_SCO_PSPOLL_LATENCY_ONE_FOURTH =1, + BT_PARAM_SCO_PSPOLL_LATENCY_HALF, + BT_PARAM_SCO_PSPOLL_LATENCY_THREE_FOURTH, +} BT_PARAMS_SCO_PSPOLL_LATENCY; + +typedef enum { + BT_PARAMS_SCO_STOMP_SCO_NEVER =1, + BT_PARAMS_SCO_STOMP_SCO_ALWAYS, + BT_PARAMS_SCO_STOMP_SCO_IN_LOWRSSI, +} BT_PARAMS_SCO_STOMP_RULES; + +typedef enum { + BT_STATUS_UNDEF = 0, + BT_STATUS_ON, + BT_STATUS_OFF, + BT_STATUS_MAX +} BT_STREAM_STATUS; + +typedef PREPACK struct { + A_UINT8 streamType; + A_UINT8 status; +} POSTPACK WMI_SET_BT_STATUS_CMD; + +typedef enum { + BT_ANT_TYPE_UNDEF=0, + BT_ANT_TYPE_DUAL, + BT_ANT_TYPE_SPLITTER, + BT_ANT_TYPE_SWITCH, + BT_ANT_TYPE_HIGH_ISO_DUAL +} BT_ANT_FRONTEND_CONFIG; + +typedef enum { + BT_COLOCATED_DEV_BTS4020=0, + BT_COLCATED_DEV_CSR , + BT_COLOCATED_DEV_VALKYRIE +} BT_COLOCATED_DEV_TYPE; + +/*********************** Applicable to AR6002 ONLY ******************************/ + +typedef enum { + BT_PARAM_SCO = 1, /* SCO stream parameters */ + BT_PARAM_A2DP , + BT_PARAM_ANTENNA_CONFIG, + BT_PARAM_COLOCATED_BT_DEVICE, + BT_PARAM_ACLCOEX, + BT_PARAM_11A_SEPARATE_ANT, + BT_PARAM_MAX +} BT_PARAM_TYPE; + + +#define BT_SCO_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_SCO_FORCE_AWAKE_OPT (1 << 1) +#define BT_SCO_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_SCO_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1) +#define BT_SCO_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3)) +#define BT_SCO_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1) +#define BT_SCO_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF) +#define BT_SCO_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF) +#define BT_SCO_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8) +#define BT_SCO_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16) + +typedef PREPACK struct { + A_UINT32 numScoCyclesForceTrigger; /* Number SCO cycles after which + force a pspoll. default = 10 */ + A_UINT32 dataResponseTimeout; /* Timeout Waiting for Downlink pkt + in response for ps-poll, + default = 10 msecs */ + A_UINT32 stompScoRules; + A_UINT32 scoOptFlags; /* SCO Options Flags : + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host supplied RSSI for OPT + 3 If set use host supplied RTS COUNT for OPT + 4..7 Unused + 8..15 Low Data Rate Min Cnt + 16..23 Low Data Rate Max Cnt + */ + + A_UINT8 stompDutyCyleVal; /* Sco cycles to limit ps-poll queuing + if stomped */ + A_UINT8 stompDutyCyleMaxVal; /*firm ware increases stomp duty cycle + gradually uptill this value on need basis*/ + A_UINT8 psPollLatencyFraction; /* Fraction of idle + period, within which + additional ps-polls + can be queued */ + A_UINT8 noSCOSlots; /* Number of SCO Tx/Rx slots. + HVx, EV3, 2EV3 = 2 */ + A_UINT8 noIdleSlots; /* Number of Bluetooth idle slots between + consecutive SCO Tx/Rx slots + HVx, EV3 = 4 + 2EV3 = 10 */ + A_UINT8 scoOptOffRssi;/*RSSI value below which we go to ps poll*/ + A_UINT8 scoOptOnRssi; /*RSSI value above which we reenter opt mode*/ + A_UINT8 scoOptRtsCount; +} POSTPACK BT_PARAMS_SCO; + +#define BT_A2DP_ALLOW_CLOSE_RANGE_OPT (1 << 0) +#define BT_A2DP_FORCE_AWAKE_OPT (1 << 1) +#define BT_A2DP_SET_RSSI_OVERRIDE(flags) ((flags) |= (1 << 2)) +#define BT_A2DP_GET_RSSI_OVERRIDE(flags) (((flags) >> 2) & 0x1) +#define BT_A2DP_SET_RTS_OVERRIDE(flags) ((flags) |= (1 << 3)) +#define BT_A2DP_GET_RTS_OVERRIDE(flags) (((flags) >> 3) & 0x1) +#define BT_A2DP_GET_MIN_LOW_RATE_CNT(flags) (((flags) >> 8) & 0xFF) +#define BT_A2DP_GET_MAX_LOW_RATE_CNT(flags) (((flags) >> 16) & 0xFF) +#define BT_A2DP_SET_MIN_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 8) +#define BT_A2DP_SET_MAX_LOW_RATE_CNT(flags,val) (flags) |= (((val) & 0xFF) << 16) + +typedef PREPACK struct { + A_UINT32 a2dpWlanUsageLimit; /* MAX time firmware uses the medium for + wlan, after it identifies the idle time + default (30 msecs) */ + A_UINT32 a2dpBurstCntMin; /* Minimum number of bluetooth data frames + to replenish Wlan Usage limit (default 3) */ + A_UINT32 a2dpDataRespTimeout; + A_UINT32 a2dpOptFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 Force awake during close range + 2 If set use host supplied RSSI for OPT + 3 If set use host supplied RTS COUNT for OPT + 4..7 Unused + 8..15 Low Data Rate Min Cnt + 16..23 Low Data Rate Max Cnt + */ + A_UINT8 isCoLocatedBtRoleMaster; + A_UINT8 a2dpOptOffRssi;/*RSSI value below which we go to ps poll*/ + A_UINT8 a2dpOptOnRssi; /*RSSI value above which we reenter opt mode*/ + A_UINT8 a2dpOptRtsCount; +}POSTPACK BT_PARAMS_A2DP; + +/* During BT ftp/ BT OPP or any another data based acl profile on bluetooth + (non a2dp).*/ +typedef PREPACK struct { + A_UINT32 aclWlanMediumUsageTime; /* Wlan usage time during Acl (non-a2dp) + coexistence (default 30 msecs) */ + A_UINT32 aclBtMediumUsageTime; /* Bt usage time during acl coexistence + (default 30 msecs)*/ + A_UINT32 aclDataRespTimeout; + A_UINT32 aclDetectTimeout; /* ACL coexistence enabled if we get + 10 Pkts in X msec(default 100 msecs) */ + A_UINT32 aclmaxPktCnt; /* No of ACL pkts to receive before + enabling ACL coex */ + +}POSTPACK BT_PARAMS_ACLCOEX; + +typedef PREPACK struct { + PREPACK union { + BT_PARAMS_SCO scoParams; + BT_PARAMS_A2DP a2dpParams; + BT_PARAMS_ACLCOEX aclCoexParams; + A_UINT8 antType; /* 0 -Disabled (default) + 1 - BT_ANT_TYPE_DUAL + 2 - BT_ANT_TYPE_SPLITTER + 3 - BT_ANT_TYPE_SWITCH */ + A_UINT8 coLocatedBtDev; /* 0 - BT_COLOCATED_DEV_BTS4020 (default) + 1 - BT_COLCATED_DEV_CSR + 2 - BT_COLOCATED_DEV_VALKYRIe + */ + } POSTPACK info; + A_UINT8 paramType ; +} POSTPACK WMI_SET_BT_PARAMS_CMD; + +/************************ END AR6002 BTCOEX *******************************/ +/*-----------------------AR6003 BTCOEX -----------------------------------*/ + +/* ---------------WMI_SET_BTCOEX_FE_ANT_CMDID --------------------------*/ +/* Indicates front end antenna configuration. This command needs to be issued + * right after initialization and after WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID. + * AR6003 enables coexistence and antenna switching based on the configuration. + */ +typedef enum { + WMI_BTCOEX_NOT_ENABLED = 0, + WMI_BTCOEX_FE_ANT_SINGLE =1, + WMI_BTCOEX_FE_ANT_DUAL=2, + WMI_BTCOEX_FE_ANT_DUAL_HIGH_ISO=3, + WMI_BTCOEX_FE_ANT_TYPE_MAX +}WMI_BTCOEX_FE_ANT_TYPE; + +typedef PREPACK struct { + A_UINT8 btcoexFeAntType; /* 1 - WMI_BTCOEX_FE_ANT_SINGLE for single antenna front end + 2 - WMI_BTCOEX_FE_ANT_DUAL for dual antenna front end + (for isolations less 35dB, for higher isolation there + is not need to pass this command). + (not implemented) + */ +}POSTPACK WMI_SET_BTCOEX_FE_ANT_CMD; + +/* -------------WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID ----------------*/ +/* Indicate the bluetooth chip to the firmware. Firmware can have different algorithm based + * bluetooth chip type.Based on bluetooth device, different coexistence protocol would be used. + */ +typedef PREPACK struct { + A_UINT8 btcoexCoLocatedBTdev; /*1 - Qcom BT (3 -wire PTA) + 2 - CSR BT (3 wire PTA) + 3 - Atheros 3001 BT (3 wire PTA) + 4 - STE bluetooth (4-wire ePTA) + 5 - Atheros 3002 BT (4-wire MCI) + defaults= 3 (Atheros 3001 BT ) + */ +}POSTPACK WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD; + +/* -------------WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID ------------*/ +/* Configuration parameters during bluetooth inquiry and page. Page configuration + * is applicable only on interfaces which can distinguish page (applicable only for ePTA - + * STE bluetooth). + * Bluetooth inquiry start and end is indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID. + * During this the station will be power-save mode. + */ +typedef PREPACK struct { + A_UINT32 btInquiryDataFetchFrequency;/* The frequency of querying the AP for data + (via pspoll) is configured by this parameter. + "default = 10 ms" */ + + A_UINT32 protectBmissDurPostBtInquiry;/* The firmware will continue to be in inquiry state + for configured duration, after inquiry completion + . This is to ensure other bluetooth transactions + (RDP, SDP profiles, link key exchange ...etc) + goes through smoothly without wifi stomping. + default = 10 secs*/ + + A_UINT32 maxpageStomp; /*Applicable only for STE-BT interface. Currently not + used */ + A_UINT32 btInquiryPageFlag; /* Not used */ +}POSTPACK WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD; + +/*---------------------WMI_SET_BTCOEX_SCO_CONFIG_CMDID ---------------*/ +/* Configure SCO parameters. These parameters would be used whenever firmware is indicated + * of (e)SCO profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID). + * Configration of BTCOEX_SCO_CONFIG data structure are common configuration and applies + * ps-poll mode and opt mode. + * Ps-poll Mode - Station is in power-save and retrieves downlink data between sco gaps. + * Opt Mode - station is in awake state and access point can send data to station any time. + * BTCOEX_PSPOLLMODE_SCO_CONFIG - Configuration applied only during ps-poll mode. + * BTCOEX_OPTMODE_SCO_CONFIG - Configuration applied only during opt mode. + */ +typedef PREPACK struct { + A_UINT32 scoSlots; /* Number of SCO Tx/Rx slots. + HVx, EV3, 2EV3 = 2 */ + A_UINT32 scoIdleSlots; /* Number of Bluetooth idle slots between + consecutive SCO Tx/Rx slots + HVx, EV3 = 4 + 2EV3 = 10 + */ + A_UINT32 scoFlags; /* SCO Options Flags : + bits: meaning: + 0 Allow Close Range Optimization + 1 Is EDR capable or Not + 2 IS Co-located Bt role Master + */ + + A_UINT32 linkId; /* applicable to STE-BT - not used */ +}POSTPACK BTCOEX_SCO_CONFIG; + +typedef PREPACK struct { + A_UINT32 scoCyclesForceTrigger; /* Number SCO cycles after which + force a pspoll. default = 10 */ + A_UINT32 scoDataResponseTimeout; /* Timeout Waiting for Downlink pkt + in response for ps-poll, + default = 20 msecs */ + + A_UINT32 scoStompDutyCyleVal; /* not implemented */ + + A_UINT32 scoStompDutyCyleMaxVal; /*Not implemented */ + + A_UINT32 scoPsPollLatencyFraction; /* Fraction of idle + period, within which + additional ps-polls can be queued + 1 - 1/4 of idle duration + 2 - 1/2 of idle duration + 3 - 3/4 of idle duration + default =2 (1/2) + */ +}POSTPACK BTCOEX_PSPOLLMODE_SCO_CONFIG; + +typedef PREPACK struct { + A_UINT32 scoStompCntIn100ms;/*max number of SCO stomp in 100ms allowed in + opt mode. If exceeds the configured value, + switch to ps-poll mode + default = 3 */ + + A_UINT32 scoContStompMax; /* max number of continous stomp allowed in opt mode. + if excedded switch to pspoll mode + default = 3 */ + + A_UINT32 scoMinlowRateMbps; /* Low rate threshold */ + + A_UINT32 scoLowRateCnt; /* number of low rate pkts (< scoMinlowRateMbps) allowed in 100 ms. + If exceeded switch/stay to ps-poll mode, lower stay in opt mode. + default = 36 + */ + + A_UINT32 scoHighPktRatio; /*(Total Rx pkts in 100 ms + 1)/ + ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms, + if exceeded switch/stay in opt mode and if lower switch/stay in pspoll mode. + default = 5 (80% of high rates) + */ + + A_UINT32 scoMaxAggrSize; /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates + max number of aggregates if it was negogiated to higher value + default = 1 + Recommended value Basic rate headsets = 1, EDR (2-EV3) =4. + */ +}POSTPACK BTCOEX_OPTMODE_SCO_CONFIG; + +typedef PREPACK struct { + BTCOEX_SCO_CONFIG scoConfig; + BTCOEX_PSPOLLMODE_SCO_CONFIG scoPspollConfig; + BTCOEX_OPTMODE_SCO_CONFIG scoOptModeConfig; +}POSTPACK WMI_SET_BTCOEX_SCO_CONFIG_CMD; + +/* ------------------WMI_SET_BTCOEX_A2DP_CONFIG_CMDID -------------------*/ +/* Configure A2DP profile parameters. These parameters would be used whenver firmware is indicated + * of A2DP profile on bluetooth ( via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID). + * Configuration of BTCOEX_A2DP_CONFIG data structure are common configuration and applies to + * ps-poll mode and opt mode. + * Ps-poll Mode - Station is in power-save and retrieves downlink data between a2dp data bursts. + * Opt Mode - station is in power save during a2dp bursts and awake in the gaps. + * BTCOEX_PSPOLLMODE_A2DP_CONFIG - Configuration applied only during ps-poll mode. + * BTCOEX_OPTMODE_A2DP_CONFIG - Configuration applied only during opt mode. + */ + +typedef PREPACK struct { + A_UINT32 a2dpFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 IS EDR capable + 2 IS Co-located Bt role Master + 3 a2dp traffic is high priority + */ + A_UINT32 linkId; /* Applicable only to STE-BT - not used */ + +}POSTPACK BTCOEX_A2DP_CONFIG; + +typedef PREPACK struct { + A_UINT32 a2dpWlanMaxDur; /* MAX time firmware uses the medium for + wlan, after it identifies the idle time + default (30 msecs) */ + + A_UINT32 a2dpMinBurstCnt; /* Minimum number of bluetooth data frames + to replenish Wlan Usage limit (default 3) */ + + A_UINT32 a2dpDataRespTimeout; /* Max duration firmware waits for downlink + by stomping on bluetooth + after ps-poll is acknowledged. + default = 20 ms + */ +}POSTPACK BTCOEX_PSPOLLMODE_A2DP_CONFIG; + +typedef PREPACK struct { + A_UINT32 a2dpMinlowRateMbps; /* Low rate threshold */ + + A_UINT32 a2dpLowRateCnt; /* number of low rate pkts (< a2dpMinlowRateMbps) allowed in 100 ms. + If exceeded switch/stay to ps-poll mode, lower stay in opt mode. + default = 36 + */ + + A_UINT32 a2dpHighPktRatio; /*(Total Rx pkts in 100 ms + 1)/ + ((Total tx pkts in 100 ms - No of high rate pkts in 100 ms) + 1) in 100 ms, + if exceeded switch/stay in opt mode and if lower switch/stay in pspoll mode. + default = 5 (80% of high rates) + */ + + A_UINT32 a2dpMaxAggrSize; /* Max number of Rx subframes allowed in this mode. (Firmware re-negogiates + max number of aggregates if it was negogiated to higher value + default = 1 + Recommended value Basic rate headsets = 1, EDR (2-EV3) =8. + */ + A_UINT32 a2dpPktStompCnt; /*number of a2dp pkts that can be stomped per burst. + default = 6*/ + +}POSTPACK BTCOEX_OPTMODE_A2DP_CONFIG; + +typedef PREPACK struct { + BTCOEX_A2DP_CONFIG a2dpConfig; + BTCOEX_PSPOLLMODE_A2DP_CONFIG a2dppspollConfig; + BTCOEX_OPTMODE_A2DP_CONFIG a2dpOptConfig; +}POSTPACK WMI_SET_BTCOEX_A2DP_CONFIG_CMD; + +/*------------ WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID---------------------*/ +/* Configure non-A2dp ACL profile parameters.The starts of ACL profile can either be + * indicated via WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID orenabled via firmware detection + * which is configured via "aclCoexFlags". + * Configration of BTCOEX_ACLCOEX_CONFIG data structure are common configuration and applies + * ps-poll mode and opt mode. + * Ps-poll Mode - Station is in power-save and retrieves downlink data during wlan medium. + * Opt Mode - station is in power save during bluetooth medium time and awake during wlan duration. + * (Not implemented yet) + * + * BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG - Configuration applied only during ps-poll mode. + * BTCOEX_OPTMODE_ACLCOEX_CONFIG - Configuration applied only during opt mode. + */ + +typedef PREPACK struct { + A_UINT32 aclWlanMediumDur; /* Wlan usage time during Acl (non-a2dp) + coexistence (default 30 msecs) + */ + + A_UINT32 aclBtMediumDur; /* Bt usage time during acl coexistence + (default 30 msecs) + */ + + A_UINT32 aclDetectTimeout; /* ACL coexistence enabled if we get + 10 Pkts in X msec(default 100 msecs) + */ + + A_UINT32 aclmaxPktCnt; /* No of ACL pkts to receive before + enabling ACL coex + default = 9 + */ + + A_UINT32 aclCoexFlags; /* A2DP Option flags: + bits: meaning: + 0 Allow Close Range Optimization + 1 disable Firmware detection + (Currently supported configuration is aclCoexFlags =0) + */ + A_UINT32 linkId; /* Applicable only for STE-BT - not used */ + +}POSTPACK BTCOEX_ACLCOEX_CONFIG; + +typedef PREPACK struct { + A_UINT32 aclDataRespTimeout; /* Max duration firmware waits for downlink + by stomping on bluetooth + after ps-poll is acknowledged. + default = 20 ms */ + +}POSTPACK BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG; + + +/* Not implemented yet*/ +typedef PREPACK struct { + A_UINT32 aclCoexMinlowRateMbps; + A_UINT32 aclCoexLowRateCnt; + A_UINT32 aclCoexHighPktRatio; + A_UINT32 aclCoexMaxAggrSize; + A_UINT32 aclPktStompCnt; +}POSTPACK BTCOEX_OPTMODE_ACLCOEX_CONFIG; + +typedef PREPACK struct { + BTCOEX_ACLCOEX_CONFIG aclCoexConfig; + BTCOEX_PSPOLLMODE_ACLCOEX_CONFIG aclCoexPspollConfig; + BTCOEX_OPTMODE_ACLCOEX_CONFIG aclCoexOptConfig; +}POSTPACK WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD; + +/* -----------WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID ------------------*/ +typedef enum { + WMI_BTCOEX_BT_PROFILE_SCO =1, + WMI_BTCOEX_BT_PROFILE_A2DP, + WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE, + WMI_BTCOEX_BT_PROFILE_ACLCOEX, +}WMI_BTCOEX_BT_PROFILE; + +typedef PREPACK struct { + A_UINT32 btProfileType; + A_UINT32 btOperatingStatus; + A_UINT32 btLinkId; +}WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD; + +/*--------------------- WMI_SET_BTCOEX_DEBUG_CMDID ---------------------*/ +/* Used for firmware development and debugging */ +typedef PREPACK struct { + A_UINT32 btcoexDbgParam1; + A_UINT32 btcoexDbgParam2; + A_UINT32 btcoexDbgParam3; + A_UINT32 btcoexDbgParam4; + A_UINT32 btcoexDbgParam5; +}WMI_SET_BTCOEX_DEBUG_CMD; + +/*---------------------WMI_GET_BTCOEX_CONFIG_CMDID --------------------- */ +/* Command to firmware to get configuration parameters of the bt profile + * reported via WMI_BTCOEX_CONFIG_EVENTID */ +typedef PREPACK struct { + A_UINT32 btProfileType; /* 1 - SCO + 2 - A2DP + 3 - INQUIRY_PAGE + 4 - ACLCOEX + */ + A_UINT32 linkId; /* not used */ +}WMI_GET_BTCOEX_CONFIG_CMD; + +/*------------------WMI_REPORT_BTCOEX_CONFIG_EVENTID------------------- */ +/* Event from firmware to host, sent in response to WMI_GET_BTCOEX_CONFIG_CMDID + * */ +typedef PREPACK struct { + A_UINT32 btProfileType; + A_UINT32 linkId; /* not used */ + PREPACK union { + WMI_SET_BTCOEX_SCO_CONFIG_CMD scoConfigCmd; + WMI_SET_BTCOEX_A2DP_CONFIG_CMD a2dpConfigCmd; + WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD aclcoexConfig; + WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD btinquiryPageConfigCmd; + } POSTPACK info; +} POSTPACK WMI_BTCOEX_CONFIG_EVENT; + +/*------------- WMI_REPORT_BTCOEX_BTCOEX_STATS_EVENTID--------------------*/ +/* Used for firmware development and debugging*/ +typedef PREPACK struct { + A_UINT32 highRatePktCnt; + A_UINT32 firstBmissCnt; + A_UINT32 psPollFailureCnt; + A_UINT32 nullFrameFailureCnt; + A_UINT32 optModeTransitionCnt; +}BTCOEX_GENERAL_STATS; + +typedef PREPACK struct { + A_UINT32 scoStompCntAvg; + A_UINT32 scoStompIn100ms; + A_UINT32 scoMaxContStomp; + A_UINT32 scoAvgNoRetries; + A_UINT32 scoMaxNoRetriesIn100ms; +}BTCOEX_SCO_STATS; + +typedef PREPACK struct { + A_UINT32 a2dpBurstCnt; + A_UINT32 a2dpMaxBurstCnt; + A_UINT32 a2dpAvgIdletimeIn100ms; + A_UINT32 a2dpAvgStompCnt; +}BTCOEX_A2DP_STATS; + +typedef PREPACK struct { + A_UINT32 aclPktCntInBtTime; + A_UINT32 aclStompCntInWlanTime; + A_UINT32 aclPktCntIn100ms; +}BTCOEX_ACLCOEX_STATS; + +typedef PREPACK struct { + BTCOEX_GENERAL_STATS coexStats; + BTCOEX_SCO_STATS scoStats; + BTCOEX_A2DP_STATS a2dpStats; + BTCOEX_ACLCOEX_STATS aclCoexStats; +}WMI_BTCOEX_STATS_EVENT; + + + +/*--------------------------END OF BTCOEX -------------------------------------*/ +typedef enum { + DISCONN_EVT_IN_RECONN = 0, /* default */ + NO_DISCONN_EVT_IN_RECONN +} TARGET_EVENT_REPORT_CONFIG; + +typedef PREPACK struct { + A_UINT32 evtConfig; +} POSTPACK WMI_SET_TARGET_EVENT_REPORT_CMD; + + +typedef PREPACK struct { + A_UINT16 cmd_buf_sz; /* HCI cmd buffer size */ + A_UINT8 buf[1]; /* Absolute HCI cmd */ +} POSTPACK WMI_HCI_CMD; + +/* + * Command Replies + */ + +/* + * WMI_GET_CHANNEL_LIST_CMDID reply + */ +typedef PREPACK struct { + A_UINT8 reserved1; + A_UINT8 numChannels; /* number of channels in reply */ + A_UINT16 channelList[1]; /* channel in Mhz */ +} POSTPACK WMI_CHANNEL_LIST_REPLY; + +typedef enum { + A_SUCCEEDED = A_OK, + A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250, + A_SUCCEEDED_MODIFY_STREAM=251, + A_FAILED_INVALID_STREAM = 252, + A_FAILED_MAX_THINSTREAMS = 253, + A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254, +} PSTREAM_REPLY_STATUS; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficClass; + A_UINT8 trafficDirection; /* DIR_TYPE */ +} POSTPACK WMI_CRE_PRIORITY_STREAM_REPLY; + +typedef PREPACK struct { + A_UINT8 status; /* PSTREAM_REPLY_STATUS */ + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; /* DIR_TYPE */ + A_UINT8 trafficClass; +} POSTPACK WMI_DEL_PRIORITY_STREAM_REPLY; + +/* + * List of Events (target to host) + */ +typedef enum { + WMI_READY_EVENTID = 0x1001, + WMI_CONNECT_EVENTID, + WMI_DISCONNECT_EVENTID, + WMI_BSSINFO_EVENTID, + WMI_CMDERROR_EVENTID, + WMI_REGDOMAIN_EVENTID, + WMI_PSTREAM_TIMEOUT_EVENTID, + WMI_NEIGHBOR_REPORT_EVENTID, + WMI_TKIP_MICERR_EVENTID, + WMI_SCAN_COMPLETE_EVENTID, /* 0x100a */ + WMI_REPORT_STATISTICS_EVENTID, + WMI_RSSI_THRESHOLD_EVENTID, + WMI_ERROR_REPORT_EVENTID, + WMI_OPT_RX_FRAME_EVENTID, + WMI_REPORT_ROAM_TBL_EVENTID, + WMI_EXTENSION_EVENTID, + WMI_CAC_EVENTID, + WMI_SNR_THRESHOLD_EVENTID, + WMI_LQ_THRESHOLD_EVENTID, + WMI_TX_RETRY_ERR_EVENTID, /* 0x1014 */ + WMI_REPORT_ROAM_DATA_EVENTID, + WMI_TEST_EVENTID, + WMI_APLIST_EVENTID, + WMI_GET_WOW_LIST_EVENTID, + WMI_GET_PMKID_LIST_EVENTID, + WMI_CHANNEL_CHANGE_EVENTID, + WMI_PEER_NODE_EVENTID, + WMI_PSPOLL_EVENTID, + WMI_DTIMEXPIRY_EVENTID, + WMI_WLAN_VERSION_EVENTID, + WMI_SET_PARAMS_REPLY_EVENTID, + WMI_ADDBA_REQ_EVENTID, /*0x1020 */ + WMI_ADDBA_RESP_EVENTID, + WMI_DELBA_REQ_EVENTID, + WMI_TX_COMPLETE_EVENTID, + WMI_HCI_EVENT_EVENTID, + WMI_ACL_DATA_EVENTID, +#ifdef WAPI_ENABLE + WMI_WAPI_REKEY_EVENTID, +#endif + WMI_REPORT_BTCOEX_STATS_EVENTID, + WMI_REPORT_BTCOEX_CONFIG_EVENTID, + + WMI_THIN_RESERVED_START_EVENTID = 0x8000, + /* Events in this range are reserved for thinmode + * See wmi_thin.h for actual definitions */ + WMI_THIN_RESERVED_END_EVENTID = 0x8fff, + +} WMI_EVENT_ID; + + +typedef enum { + WMI_11A_CAPABILITY = 1, + WMI_11G_CAPABILITY = 2, + WMI_11AG_CAPABILITY = 3, + WMI_11NA_CAPABILITY = 4, + WMI_11NG_CAPABILITY = 5, + WMI_11NAG_CAPABILITY = 6, + // END CAPABILITY + WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY), +} WMI_PHY_CAPABILITY; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_1; + +typedef PREPACK struct { + A_UINT32 version; + A_UINT8 macaddr[ATH_MAC_LEN]; + A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */ +} POSTPACK WMI_READY_EVENT_2; + +#if defined(ATH_TARGET) +#ifdef AR6002_REV2 +#define WMI_READY_EVENT WMI_READY_EVENT_1 /* AR6002_REV2 target code */ +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* AR6002_REV4 and AR6001 */ +#endif +#else +#define WMI_READY_EVENT WMI_READY_EVENT_2 /* host code */ +#endif + + +/* + * Connect Event + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 listenInterval; + A_UINT16 beaconInterval; + A_UINT32 networkType; + A_UINT8 beaconIeLen; + A_UINT8 assocReqLen; + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_CONNECT_EVENT; + +/* + * Disconnect Event + */ +typedef enum { + NO_NETWORK_AVAIL = 0x01, + LOST_LINK = 0x02, /* bmiss */ + DISCONNECT_CMD = 0x03, + BSS_DISCONNECTED = 0x04, + AUTH_FAILED = 0x05, + ASSOC_FAILED = 0x06, + NO_RESOURCES_AVAIL = 0x07, + CSERV_DISCONNECT = 0x08, + INVALID_PROFILE = 0x0a, + DOT11H_CHANNEL_SWITCH = 0x0b, + PROFILE_MISMATCH = 0x0c, + CONNECTION_EVICTED = 0x0d, +} WMI_DISCONNECT_REASON; + +typedef PREPACK struct { + A_UINT16 protocolReasonStatus; /* reason code, see 802.11 spec. */ + A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */ + A_UINT8 disconnectReason ; /* see WMI_DISCONNECT_REASON */ + A_UINT8 assocRespLen; + A_UINT8 assocInfo[1]; +} POSTPACK WMI_DISCONNECT_EVENT; + +/* + * BSS Info Event. + * Mechanism used to inform host of the presence and characteristic of + * wireless networks present. Consists of bss info header followed by + * the beacon or probe-response frame body. The 802.11 header is not included. + */ +typedef enum { + BEACON_FTYPE = 0x1, + PROBERESP_FTYPE, + ACTION_MGMT_FTYPE, + PROBEREQ_FTYPE, +} WMI_BI_FTYPE; + +enum { + BSS_ELEMID_CHANSWITCH = 0x01, + BSS_ELEMID_ATHEROS = 0x02, +}; + +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_BI_FTYPE */ + A_UINT8 snr; + A_INT16 rssi; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT32 ieMask; +} POSTPACK WMI_BSS_INFO_HDR; + +/* + * BSS INFO HDR version 2.0 + * With 6 bytes HTC header and 6 bytes of WMI header + * WMI_BSS_INFO_HDR cannot be accomodated in the removed 802.11 management + * header space. + * - Reduce the ieMask to 2 bytes as only two bit flags are used + * - Remove rssi and compute it on the host. rssi = snr - 95 + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_BI_FTYPE */ + A_UINT8 snr; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 ieMask; +} POSTPACK WMI_BSS_INFO_HDR2; + +/* + * Command Error Event + */ +typedef enum { + INVALID_PARAM = 0x01, + ILLEGAL_STATE = 0x02, + INTERNAL_ERROR = 0x03, +} WMI_ERROR_CODE; + +typedef PREPACK struct { + A_UINT16 commandId; + A_UINT8 errorCode; +} POSTPACK WMI_CMD_ERROR_EVENT; + +/* + * New Regulatory Domain Event + */ +typedef PREPACK struct { + A_UINT32 regDomain; +} POSTPACK WMI_REG_DOMAIN_EVENT; + +typedef PREPACK struct { + A_UINT8 txQueueNumber; + A_UINT8 rxQueueNumber; + A_UINT8 trafficDirection; + A_UINT8 trafficClass; +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT; + +/* + * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform + * the host of BSS's it has found that matches the current profile. + * It can be used by the host to cache PMKs and/to initiate pre-authentication + * if the BSS supports it. The first bssid is always the current associated + * BSS. + * The bssid and bssFlags information repeats according to the number + * or APs reported. + */ +typedef enum { + WMI_DEFAULT_BSS_FLAGS = 0x00, + WMI_PREAUTH_CAPABLE_BSS = 0x01, + WMI_PMKID_VALID_BSS = 0x02, +} WMI_BSS_FLAGS; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */ +} POSTPACK WMI_NEIGHBOR_INFO; + +typedef PREPACK struct { + A_INT8 numberOfAps; + WMI_NEIGHBOR_INFO neighbor[1]; +} POSTPACK WMI_NEIGHBOR_REPORT_EVENT; + +/* + * TKIP MIC Error Event + */ +typedef PREPACK struct { + A_UINT8 keyid; + A_UINT8 ismcast; +} POSTPACK WMI_TKIP_MICERR_EVENT; + +/* + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new) + */ +typedef PREPACK struct { + A_INT32 status; +} POSTPACK WMI_SCAN_COMPLETE_EVENT; + +#define MAX_OPT_DATA_LEN 1400 + +/* + * WMI_SET_ADHOC_BSSID_CMDID + */ +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_SET_ADHOC_BSSID_CMD; + +/* + * WMI_SET_OPT_MODE_CMDID + */ +typedef enum { + SPECIAL_OFF, + SPECIAL_ON, +} OPT_MODE_TYPE; + +typedef PREPACK struct { + A_UINT8 optMode; +} POSTPACK WMI_SET_OPT_MODE_CMD; + +/* + * WMI_TX_OPT_FRAME_CMDID + */ +typedef enum { + OPT_PROBE_REQ = 0x01, + OPT_PROBE_RESP = 0x02, + OPT_CPPP_START = 0x03, + OPT_CPPP_STOP = 0x04, +} WMI_OPT_FTYPE; + +typedef PREPACK struct { + A_UINT16 optIEDataLen; + A_UINT8 frmType; + A_UINT8 dstAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT8 reserved; /* For alignment */ + A_UINT8 optIEData[1]; +} POSTPACK WMI_OPT_TX_FRAME_CMD; + +/* + * Special frame receive Event. + * Mechanism used to inform host of the receiption of the special frames. + * Consists of special frame info header followed by special frame body. + * The 802.11 header is not included. + */ +typedef PREPACK struct { + A_UINT16 channel; + A_UINT8 frameType; /* see WMI_OPT_FTYPE */ + A_INT8 snr; + A_UINT8 srcAddr[ATH_MAC_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_OPT_RX_INFO_HDR; + +/* + * Reporting statistics. + */ +typedef PREPACK struct { + A_UINT32 tx_packets; + A_UINT32 tx_bytes; + A_UINT32 tx_unicast_pkts; + A_UINT32 tx_unicast_bytes; + A_UINT32 tx_multicast_pkts; + A_UINT32 tx_multicast_bytes; + A_UINT32 tx_broadcast_pkts; + A_UINT32 tx_broadcast_bytes; + A_UINT32 tx_rts_success_cnt; + A_UINT32 tx_packet_per_ac[4]; + A_UINT32 tx_errors_per_ac[4]; + + A_UINT32 tx_errors; + A_UINT32 tx_failed_cnt; + A_UINT32 tx_retry_cnt; + A_UINT32 tx_mult_retry_cnt; + A_UINT32 tx_rts_fail_cnt; + A_INT32 tx_unicast_rate; +}POSTPACK tx_stats_t; + +typedef PREPACK struct { + A_UINT32 rx_packets; + A_UINT32 rx_bytes; + A_UINT32 rx_unicast_pkts; + A_UINT32 rx_unicast_bytes; + A_UINT32 rx_multicast_pkts; + A_UINT32 rx_multicast_bytes; + A_UINT32 rx_broadcast_pkts; + A_UINT32 rx_broadcast_bytes; + A_UINT32 rx_fragment_pkt; + + A_UINT32 rx_errors; + A_UINT32 rx_crcerr; + A_UINT32 rx_key_cache_miss; + A_UINT32 rx_decrypt_err; + A_UINT32 rx_duplicate_frames; + A_INT32 rx_unicast_rate; +}POSTPACK rx_stats_t; + +typedef PREPACK struct { + A_UINT32 tkip_local_mic_failure; + A_UINT32 tkip_counter_measures_invoked; + A_UINT32 tkip_replays; + A_UINT32 tkip_format_errors; + A_UINT32 ccmp_format_errors; + A_UINT32 ccmp_replays; +}POSTPACK tkip_ccmp_stats_t; + +typedef PREPACK struct { + A_UINT32 power_save_failure_cnt; + A_UINT16 stop_tx_failure_cnt; + A_UINT16 atim_tx_failure_cnt; + A_UINT16 atim_rx_failure_cnt; + A_UINT16 bcn_rx_failure_cnt; +}POSTPACK pm_stats_t; + +typedef PREPACK struct { + A_UINT32 cs_bmiss_cnt; + A_UINT32 cs_lowRssi_cnt; + A_UINT16 cs_connect_cnt; + A_UINT16 cs_disconnect_cnt; + A_INT16 cs_aveBeacon_rssi; + A_UINT16 cs_roam_count; + A_INT16 cs_rssi; + A_UINT8 cs_snr; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; +} POSTPACK cserv_stats_t; + +typedef PREPACK struct { + tx_stats_t tx_stats; + rx_stats_t rx_stats; + tkip_ccmp_stats_t tkipCcmpStats; +}POSTPACK wlan_net_stats_t; + +typedef PREPACK struct { + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +} POSTPACK arp_stats_t; + +typedef PREPACK struct { + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; +} POSTPACK wlan_wow_stats_t; + +typedef PREPACK struct { + A_UINT32 lqVal; + A_INT32 noise_floor_calibation; + pm_stats_t pmStats; + wlan_net_stats_t txrxStats; + wlan_wow_stats_t wowStats; + arp_stats_t arpStats; + cserv_stats_t cservStats; +} POSTPACK WMI_TARGET_STATS; + +/* + * WMI_RSSI_THRESHOLD_EVENTID. + * Indicate the RSSI events to host. Events are indicated when we breach a + * thresold value. + */ +typedef enum{ + WMI_RSSI_THRESHOLD1_ABOVE = 0, + WMI_RSSI_THRESHOLD2_ABOVE, + WMI_RSSI_THRESHOLD3_ABOVE, + WMI_RSSI_THRESHOLD4_ABOVE, + WMI_RSSI_THRESHOLD5_ABOVE, + WMI_RSSI_THRESHOLD6_ABOVE, + WMI_RSSI_THRESHOLD1_BELOW, + WMI_RSSI_THRESHOLD2_BELOW, + WMI_RSSI_THRESHOLD3_BELOW, + WMI_RSSI_THRESHOLD4_BELOW, + WMI_RSSI_THRESHOLD5_BELOW, + WMI_RSSI_THRESHOLD6_BELOW +}WMI_RSSI_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT16 rssi; + A_UINT8 range; +}POSTPACK WMI_RSSI_THRESHOLD_EVENT; + +/* + * WMI_ERROR_REPORT_EVENTID + */ +typedef enum{ + WMI_TARGET_PM_ERR_FAIL = 0x00000001, + WMI_TARGET_KEY_NOT_FOUND = 0x00000002, + WMI_TARGET_DECRYPTION_ERR = 0x00000004, + WMI_TARGET_BMISS = 0x00000008, + WMI_PSDISABLE_NODE_JOIN = 0x00000010, + WMI_TARGET_COM_ERR = 0x00000020, + WMI_TARGET_FATAL_ERR = 0x00000040 +} WMI_TARGET_ERROR_VAL; + +typedef PREPACK struct { + A_UINT32 errorVal; +}POSTPACK WMI_TARGET_ERROR_REPORT_EVENT; + +typedef PREPACK struct { + A_UINT8 retrys; +}POSTPACK WMI_TX_RETRY_ERR_EVENT; + +typedef enum{ + WMI_SNR_THRESHOLD1_ABOVE = 1, + WMI_SNR_THRESHOLD1_BELOW, + WMI_SNR_THRESHOLD2_ABOVE, + WMI_SNR_THRESHOLD2_BELOW, + WMI_SNR_THRESHOLD3_ABOVE, + WMI_SNR_THRESHOLD3_BELOW, + WMI_SNR_THRESHOLD4_ABOVE, + WMI_SNR_THRESHOLD4_BELOW +} WMI_SNR_THRESHOLD_VAL; + +typedef PREPACK struct { + A_UINT8 range; /* WMI_SNR_THRESHOLD_VAL */ + A_UINT8 snr; +}POSTPACK WMI_SNR_THRESHOLD_EVENT; + +typedef enum{ + WMI_LQ_THRESHOLD1_ABOVE = 1, + WMI_LQ_THRESHOLD1_BELOW, + WMI_LQ_THRESHOLD2_ABOVE, + WMI_LQ_THRESHOLD2_BELOW, + WMI_LQ_THRESHOLD3_ABOVE, + WMI_LQ_THRESHOLD3_BELOW, + WMI_LQ_THRESHOLD4_ABOVE, + WMI_LQ_THRESHOLD4_BELOW +} WMI_LQ_THRESHOLD_VAL; + +typedef PREPACK struct { + A_INT32 lq; + A_UINT8 range; /* WMI_LQ_THRESHOLD_VAL */ +}POSTPACK WMI_LQ_THRESHOLD_EVENT; +/* + * WMI_REPORT_ROAM_TBL_EVENTID + */ +#define MAX_ROAM_TBL_CAND 5 + +typedef PREPACK struct { + A_INT32 roam_util; + A_UINT8 bssid[ATH_MAC_LEN]; + A_INT8 rssi; + A_INT8 rssidt; + A_INT8 last_rssi; + A_INT8 util; + A_INT8 bias; + A_UINT8 reserved; /* For alignment */ +} POSTPACK WMI_BSS_ROAM_INFO; + + +typedef PREPACK struct { + A_UINT16 roamMode; + A_UINT16 numEntries; + WMI_BSS_ROAM_INFO bssRoamInfo[1]; +} POSTPACK WMI_TARGET_ROAM_TBL; + +/* + * WMI_HCI_EVENT_EVENTID + */ +typedef PREPACK struct { + A_UINT16 evt_buf_sz; /* HCI event buffer size */ + A_UINT8 buf[1]; /* HCI event */ +} POSTPACK WMI_HCI_EVENT; + +/* + * WMI_CAC_EVENTID + */ +typedef enum { + CAC_INDICATION_ADMISSION = 0x00, + CAC_INDICATION_ADMISSION_RESP = 0x01, + CAC_INDICATION_DELETE = 0x02, + CAC_INDICATION_NO_RESP = 0x03, +}CAC_INDICATION; + +#define WMM_TSPEC_IE_LEN 63 + +typedef PREPACK struct { + A_UINT8 ac; + A_UINT8 cac_indication; + A_UINT8 statusCode; + A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN]; +}POSTPACK WMI_CAC_EVENT; + +/* + * WMI_APLIST_EVENTID + */ + +typedef enum { + APLIST_VER1 = 1, +} APLIST_VER; + +typedef PREPACK struct { + A_UINT8 bssid[ATH_MAC_LEN]; + A_UINT16 channel; +} POSTPACK WMI_AP_INFO_V1; + +typedef PREPACK union { + WMI_AP_INFO_V1 apInfoV1; +} POSTPACK WMI_AP_INFO; + +typedef PREPACK struct { + A_UINT8 apListVer; + A_UINT8 numAP; + WMI_AP_INFO apList[1]; +} POSTPACK WMI_APLIST_EVENT; + +/* + * developer commands + */ + +/* + * WMI_SET_BITRATE_CMDID + * + * Get bit rate cmd uses same definition as set bit rate cmd + */ +typedef enum { + RATE_AUTO = -1, + RATE_1Mb = 0, + RATE_2Mb = 1, + RATE_5_5Mb = 2, + RATE_11Mb = 3, + RATE_6Mb = 4, + RATE_9Mb = 5, + RATE_12Mb = 6, + RATE_18Mb = 7, + RATE_24Mb = 8, + RATE_36Mb = 9, + RATE_48Mb = 10, + RATE_54Mb = 11, + RATE_MCS_0_20 = 12, + RATE_MCS_1_20 = 13, + RATE_MCS_2_20 = 14, + RATE_MCS_3_20 = 15, + RATE_MCS_4_20 = 16, + RATE_MCS_5_20 = 17, + RATE_MCS_6_20 = 18, + RATE_MCS_7_20 = 19, + RATE_MCS_0_40 = 20, + RATE_MCS_1_40 = 21, + RATE_MCS_2_40 = 22, + RATE_MCS_3_40 = 23, + RATE_MCS_4_40 = 24, + RATE_MCS_5_40 = 25, + RATE_MCS_6_40 = 26, + RATE_MCS_7_40 = 27, +} WMI_BIT_RATE; + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ + A_INT8 mgmtRateIndex; + A_INT8 ctlRateIndex; +} POSTPACK WMI_BIT_RATE_CMD; + + +typedef PREPACK struct { + A_INT8 rateIndex; /* see WMI_BIT_RATE */ +} POSTPACK WMI_BIT_RATE_REPLY; + + +/* + * WMI_SET_FIXRATES_CMDID + * + * Get fix rates cmd uses same definition as set fix rates cmd + */ +#define FIX_RATE_1Mb ((A_UINT32)0x1) +#define FIX_RATE_2Mb ((A_UINT32)0x2) +#define FIX_RATE_5_5Mb ((A_UINT32)0x4) +#define FIX_RATE_11Mb ((A_UINT32)0x8) +#define FIX_RATE_6Mb ((A_UINT32)0x10) +#define FIX_RATE_9Mb ((A_UINT32)0x20) +#define FIX_RATE_12Mb ((A_UINT32)0x40) +#define FIX_RATE_18Mb ((A_UINT32)0x80) +#define FIX_RATE_24Mb ((A_UINT32)0x100) +#define FIX_RATE_36Mb ((A_UINT32)0x200) +#define FIX_RATE_48Mb ((A_UINT32)0x400) +#define FIX_RATE_54Mb ((A_UINT32)0x800) +#define FIX_RATE_MCS_0_20 ((A_UINT32)0x1000) +#define FIX_RATE_MCS_1_20 ((A_UINT32)0x2000) +#define FIX_RATE_MCS_2_20 ((A_UINT32)0x4000) +#define FIX_RATE_MCS_3_20 ((A_UINT32)0x8000) +#define FIX_RATE_MCS_4_20 ((A_UINT32)0x10000) +#define FIX_RATE_MCS_5_20 ((A_UINT32)0x20000) +#define FIX_RATE_MCS_6_20 ((A_UINT32)0x40000) +#define FIX_RATE_MCS_7_20 ((A_UINT32)0x80000) +#define FIX_RATE_MCS_0_40 ((A_UINT32)0x100000) +#define FIX_RATE_MCS_1_40 ((A_UINT32)0x200000) +#define FIX_RATE_MCS_2_40 ((A_UINT32)0x400000) +#define FIX_RATE_MCS_3_40 ((A_UINT32)0x800000) +#define FIX_RATE_MCS_4_40 ((A_UINT32)0x1000000) +#define FIX_RATE_MCS_5_40 ((A_UINT32)0x2000000) +#define FIX_RATE_MCS_6_40 ((A_UINT32)0x4000000) +#define FIX_RATE_MCS_7_40 ((A_UINT32)0x8000000) + +typedef PREPACK struct { + A_UINT32 fixRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY; + +typedef PREPACK struct { + A_UINT8 bEnableMask; + A_UINT8 frameType; /*type and subtype*/ + A_UINT32 frameRateMask; /* see WMI_BIT_RATE */ +} POSTPACK WMI_FRAME_RATES_CMD, WMI_FRAME_RATES_REPLY; + +/* + * WMI_SET_RECONNECT_AUTH_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + RECONN_DO_AUTH = 0x00, + RECONN_NOT_AUTH = 0x01 +} WMI_AUTH_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +} POSTPACK WMI_SET_AUTH_MODE_CMD; + +/* + * WMI_SET_REASSOC_MODE_CMDID + * + * Set authentication mode + */ +typedef enum { + REASSOC_DO_DISASSOC = 0x00, + REASSOC_DONOT_DISASSOC = 0x01 +} WMI_REASSOC_MODE; + +typedef PREPACK struct { + A_UINT8 mode; +}POSTPACK WMI_SET_REASSOC_MODE_CMD; + +typedef enum { + ROAM_DATA_TIME = 1, /* Get The Roam Time Data */ +} ROAM_DATA_TYPE; + +typedef PREPACK struct { + A_UINT32 disassoc_time; + A_UINT32 no_txrx_time; + A_UINT32 assoc_time; + A_UINT32 allow_txrx_time; + A_UINT8 disassoc_bssid[ATH_MAC_LEN]; + A_INT8 disassoc_bss_rssi; + A_UINT8 assoc_bssid[ATH_MAC_LEN]; + A_INT8 assoc_bss_rssi; +} POSTPACK WMI_TARGET_ROAM_TIME; + +typedef PREPACK struct { + PREPACK union { + WMI_TARGET_ROAM_TIME roamTime; + } POSTPACK u; + A_UINT8 roamDataType ; +} POSTPACK WMI_TARGET_ROAM_DATA; + +typedef enum { + WMI_WMM_DISABLED = 0, + WMI_WMM_ENABLED +} WMI_WMM_STATUS; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_WMM_CMD; + +typedef PREPACK struct { + A_UINT8 status; +}POSTPACK WMI_SET_QOS_SUPP_CMD; + +typedef enum { + WMI_TXOP_DISABLED = 0, + WMI_TXOP_ENABLED +} WMI_TXOP_CFG; + +typedef PREPACK struct { + A_UINT8 txopEnable; +}POSTPACK WMI_SET_WMM_TXOP_CMD; + +typedef PREPACK struct { + A_UINT8 keepaliveInterval; +} POSTPACK WMI_SET_KEEPALIVE_CMD; + +typedef PREPACK struct { + A_BOOL configured; + A_UINT8 keepaliveInterval; +} POSTPACK WMI_GET_KEEPALIVE_CMD; + +/* + * Add Application specified IE to a management frame + */ +#define WMI_MAX_IE_LEN 255 + +typedef PREPACK struct { + A_UINT8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */ + A_UINT8 ieLen; /* Length of the IE that should be added to the MGMT frame */ + A_UINT8 ieInfo[1]; +} POSTPACK WMI_SET_APPIE_CMD; + +/* + * Notify the WSC registration status to the target + */ +#define WSC_REG_ACTIVE 1 +#define WSC_REG_INACTIVE 0 +/* Generic Hal Interface for setting hal paramters. */ +/* Add new Set HAL Param cmdIds here for newer params */ +typedef enum { + WHAL_SETCABTO_CMDID = 1, +}WHAL_CMDID; + +typedef PREPACK struct { + A_UINT8 cabTimeOut; +} POSTPACK WHAL_SETCABTO_PARAM; + +typedef PREPACK struct { + A_UINT8 whalCmdId; + A_UINT8 data[1]; +} POSTPACK WHAL_PARAMCMD; + + +#define WOW_MAX_FILTER_LISTS 1 /*4*/ +#define WOW_MAX_FILTERS_PER_LIST 4 +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + +#define MAC_MAX_FILTERS_PER_LIST 4 + +typedef PREPACK struct { + A_UINT8 wow_valid_filter; + A_UINT8 wow_filter_id; + A_UINT8 wow_filter_size; + A_UINT8 wow_filter_offset; + A_UINT8 wow_filter_mask[WOW_MASK_SIZE]; + A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE]; +} POSTPACK WOW_FILTER; + + +typedef PREPACK struct { + A_UINT8 wow_valid_list; + A_UINT8 wow_list_id; + A_UINT8 wow_num_filters; + A_UINT8 wow_total_list_size; + WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST]; +} POSTPACK WOW_FILTER_LIST; + +typedef PREPACK struct { + A_UINT8 valid_filter; + A_UINT8 mac_addr[ATH_MAC_LEN]; +} POSTPACK MAC_FILTER; + + +typedef PREPACK struct { + A_UINT8 total_list_size; + A_UINT8 enable; + MAC_FILTER list[MAC_MAX_FILTERS_PER_LIST]; +} POSTPACK MAC_FILTER_LIST; + +#define MAX_IP_ADDRS 2 +typedef PREPACK struct { + A_UINT32 ips[MAX_IP_ADDRS]; /* IP in Network Byte Order */ +} POSTPACK WMI_SET_IP_CMD; + +typedef PREPACK struct { + A_BOOL awake; + A_BOOL asleep; +} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD; + +typedef enum { + WOW_FILTER_SSID = 0x1 +} WMI_WOW_FILTER; + +typedef PREPACK struct { + A_BOOL enable_wow; + WMI_WOW_FILTER filter; +} POSTPACK WMI_SET_WOW_MODE_CMD; + +typedef PREPACK struct { + A_UINT8 filter_list_id; +} POSTPACK WMI_GET_WOW_LIST_CMD; + +/* + * WMI_GET_WOW_LIST_CMD reply + */ +typedef PREPACK struct { + A_UINT8 num_filters; /* number of patterns in reply */ + A_UINT8 this_filter_num; /* this is filter # x of total num_filters */ + A_UINT8 wow_mode; + A_UINT8 host_mode; + WOW_FILTER wow_filters[1]; +} POSTPACK WMI_GET_WOW_LIST_REPLY; + +typedef PREPACK struct { + A_UINT8 filter_list_id; + A_UINT8 filter_size; + A_UINT8 filter_offset; + A_UINT8 filter[1]; +} POSTPACK WMI_ADD_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT16 filter_list_id; + A_UINT16 filter_id; +} POSTPACK WMI_DEL_WOW_PATTERN_CMD; + +typedef PREPACK struct { + A_UINT8 macaddr[ATH_MAC_LEN]; +} POSTPACK WMI_SET_MAC_ADDRESS_CMD; + +/* + * WMI_SET_AKMP_PARAMS_CMD + */ + +#define WMI_AKMP_MULTI_PMKID_EN 0x000001 + +typedef PREPACK struct { + A_UINT32 akmpInfo; +} POSTPACK WMI_SET_AKMP_PARAMS_CMD; + +typedef PREPACK struct { + A_UINT8 pmkid[WMI_PMKID_LEN]; +} POSTPACK WMI_PMKID; + +/* + * WMI_SET_PMKID_LIST_CMD + */ +#define WMI_MAX_PMKID_CACHE 8 + +typedef PREPACK struct { + A_UINT32 numPMKID; + WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; +} POSTPACK WMI_SET_PMKID_LIST_CMD; + +/* + * WMI_GET_PMKID_LIST_CMD Reply + * Following the Number of PMKIDs is the list of PMKIDs + */ +typedef PREPACK struct { + A_UINT32 numPMKID; + A_UINT8 bssidList[ATH_MAC_LEN][1]; + WMI_PMKID pmkidList[1]; +} POSTPACK WMI_PMKID_LIST_REPLY; + +typedef PREPACK struct { + A_UINT16 oldChannel; + A_UINT32 newChannel; +} POSTPACK WMI_CHANNEL_CHANGE_EVENT; + +typedef PREPACK struct { + A_UINT32 version; +} POSTPACK WMI_WLAN_VERSION_EVENT; + + +/* WMI_ADDBA_REQ_EVENTID */ +typedef PREPACK struct { + A_UINT8 tid; + A_UINT8 win_sz; + A_UINT16 st_seq_no; + A_UINT8 status; /* f/w response for ADDBA Req; OK(0) or failure(!=0) */ +} POSTPACK WMI_ADDBA_REQ_EVENT; + +/* WMI_ADDBA_RESP_EVENTID */ +typedef PREPACK struct { + A_UINT8 tid; + A_UINT8 status; /* OK(0), failure (!=0) */ + A_UINT16 amsdu_sz; /* Three values: Not supported(0), 3839, 8k */ +} POSTPACK WMI_ADDBA_RESP_EVENT; + +/* WMI_DELBA_EVENTID + * f/w received a DELBA for peer and processed it. + * Host is notified of this + */ +typedef PREPACK struct { + A_UINT8 tid; + A_UINT8 is_peer_initiator; + A_UINT16 reason_code; +} POSTPACK WMI_DELBA_EVENT; + + +#ifdef WAPI_ENABLE +#define WAPI_REKEY_UCAST 1 +#define WAPI_REKEY_MCAST 2 +typedef PREPACK struct { + A_UINT8 type; + A_UINT8 macAddr[ATH_MAC_LEN]; +} POSTPACK WMI_WAPIREKEY_EVENT; +#endif + + +/* WMI_ALLOW_AGGR_CMDID + * Configures tid's to allow ADDBA negotiations + * on each tid, in each direction + */ +typedef PREPACK struct { + A_UINT16 tx_allow_aggr; /* 16-bit mask to allow uplink ADDBA negotiation - bit position indicates tid*/ + A_UINT16 rx_allow_aggr; /* 16-bit mask to allow donwlink ADDBA negotiation - bit position indicates tid*/ +} POSTPACK WMI_ALLOW_AGGR_CMD; + +/* WMI_ADDBA_REQ_CMDID + * f/w starts performing ADDBA negotiations with peer + * on the given tid + */ +typedef PREPACK struct { + A_UINT8 tid; +} POSTPACK WMI_ADDBA_REQ_CMD; + +/* WMI_DELBA_REQ_CMDID + * f/w would teardown BA with peer. + * is_send_initiator indicates if it's or tx or rx side + */ +typedef PREPACK struct { + A_UINT8 tid; + A_UINT8 is_sender_initiator; + +} POSTPACK WMI_DELBA_REQ_CMD; + +#define PEER_NODE_JOIN_EVENT 0x00 +#define PEER_NODE_LEAVE_EVENT 0x01 +#define PEER_FIRST_NODE_JOIN_EVENT 0x10 +#define PEER_LAST_NODE_LEAVE_EVENT 0x11 +typedef PREPACK struct { + A_UINT8 eventCode; + A_UINT8 peerMacAddr[ATH_MAC_LEN]; +} POSTPACK WMI_PEER_NODE_EVENT; + +#define IEEE80211_FRAME_TYPE_MGT 0x00 +#define IEEE80211_FRAME_TYPE_CTL 0x04 + +/* + * Transmit complete event data structure(s) + */ + + +typedef PREPACK struct { +#define TX_COMPLETE_STATUS_SUCCESS 0 +#define TX_COMPLETE_STATUS_RETRIES 1 +#define TX_COMPLETE_STATUS_NOLINK 2 +#define TX_COMPLETE_STATUS_TIMEOUT 3 +#define TX_COMPLETE_STATUS_OTHER 4 + + A_UINT8 status; /* one of TX_COMPLETE_STATUS_... */ + A_UINT8 pktID; /* packet ID to identify parent packet */ + A_UINT8 rateIdx; /* rate index on successful transmission */ + A_UINT8 ackFailures; /* number of ACK failures in tx attempt */ +#if 0 /* optional params currently ommitted. */ + A_UINT32 queueDelay; // usec delay measured Tx Start time - host delivery time + A_UINT32 mediaDelay; // usec delay measured ACK rx time - host delivery time +#endif +} POSTPACK TX_COMPLETE_MSG_V1; /* version 1 of tx complete msg */ + +typedef PREPACK struct { + A_UINT8 numMessages; /* number of tx comp msgs following this struct */ + A_UINT8 msgLen; /* length in bytes for each individual msg following this struct */ + A_UINT8 msgType; /* version of tx complete msg data following this struct */ + A_UINT8 reserved; /* individual messages follow this header */ +} POSTPACK WMI_TX_COMPLETE_EVENT; + +#define WMI_TXCOMPLETE_VERSION_1 (0x01) + + +/* + * ------- AP Mode definitions -------------- + */ + +/* + * !!! Warning !!! + * -Changing the following values needs compilation of both driver and firmware + */ +#ifdef AR6002_REV2 +#define AP_MAX_NUM_STA 4 +#else +#define AP_MAX_NUM_STA 8 +#endif +#define AP_ACL_SIZE 10 +#define IEEE80211_MAX_IE 256 +#define MCAST_AID 0xFF /* Spl. AID used to set DTIM flag in the beacons */ +#define DEF_AP_COUNTRY_CODE "US " +#define DEF_AP_WMODE_G WMI_11G_MODE +#define DEF_AP_WMODE_AG WMI_11AG_MODE +#define DEF_AP_DTIM 5 +#define DEF_BEACON_INTERVAL 100 + +/* AP mode disconnect reasons */ +#define AP_DISCONNECT_STA_LEFT 101 +#define AP_DISCONNECT_FROM_HOST 102 +#define AP_DISCONNECT_COMM_TIMEOUT 103 + +/* + * Used with WMI_AP_HIDDEN_SSID_CMDID + */ +#define HIDDEN_SSID_FALSE 0 +#define HIDDEN_SSID_TRUE 1 +typedef PREPACK struct { + A_UINT8 hidden_ssid; +} POSTPACK WMI_AP_HIDDEN_SSID_CMD; + +/* + * Used with WMI_AP_ACL_POLICY_CMDID + */ +#define AP_ACL_DISABLE 0x00 +#define AP_ACL_ALLOW_MAC 0x01 +#define AP_ACL_DENY_MAC 0x02 +#define AP_ACL_RETAIN_LIST_MASK 0x80 +typedef PREPACK struct { + A_UINT8 policy; +} POSTPACK WMI_AP_ACL_POLICY_CMD; + +/* + * Used with WMI_AP_ACL_MAC_LIST_CMDID + */ +#define ADD_MAC_ADDR 1 +#define DEL_MAC_ADDR 2 +typedef PREPACK struct { + A_UINT8 action; + A_UINT8 index; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 wildcard; +} POSTPACK WMI_AP_ACL_MAC_CMD; + +typedef PREPACK struct { + A_UINT16 index; + A_UINT8 acl_mac[AP_ACL_SIZE][ATH_MAC_LEN]; + A_UINT8 wildcard[AP_ACL_SIZE]; + A_UINT8 policy; +} POSTPACK WMI_AP_ACL; + +/* + * Used with WMI_AP_SET_NUM_STA_CMDID + */ +typedef PREPACK struct { + A_UINT8 num_sta; +} POSTPACK WMI_AP_SET_NUM_STA_CMD; + +/* + * Used with WMI_AP_SET_MLME_CMDID + */ +typedef PREPACK struct { + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT16 reason; /* 802.11 reason code */ + A_UINT8 cmd; /* operation to perform */ +#define WMI_AP_MLME_ASSOC 1 /* associate station */ +#define WMI_AP_DISASSOC 2 /* disassociate station */ +#define WMI_AP_DEAUTH 3 /* deauthenticate station */ +#define WMI_AP_MLME_AUTHORIZE 4 /* authorize station */ +#define WMI_AP_MLME_UNAUTHORIZE 5 /* unauthorize station */ +} POSTPACK WMI_AP_SET_MLME_CMD; + +typedef PREPACK struct { + A_UINT32 period; +} POSTPACK WMI_AP_CONN_INACT_CMD; + +typedef PREPACK struct { + A_UINT32 period_min; + A_UINT32 dwell_ms; +} POSTPACK WMI_AP_PROT_SCAN_TIME_CMD; + +typedef PREPACK struct { + A_BOOL flag; + A_UINT16 aid; +} POSTPACK WMI_AP_SET_PVB_CMD; + +#define WMI_DISABLE_REGULATORY_CODE "FF" + +typedef PREPACK struct { + A_UCHAR countryCode[3]; +} POSTPACK WMI_AP_SET_COUNTRY_CMD; + +typedef PREPACK struct { + A_UINT8 dtim; +} POSTPACK WMI_AP_SET_DTIM_CMD; + +typedef PREPACK struct { + A_UINT8 band; /* specifies which band to apply these values */ + A_UINT8 enable; /* allows 11n to be disabled on a per band basis */ + A_UINT8 chan_width_40M_supported; + A_UINT8 short_GI_20MHz; + A_UINT8 short_GI_40MHz; + A_UINT8 intolerance_40MHz; + A_UINT8 max_ampdu_len_exp; +} POSTPACK WMI_SET_HT_CAP_CMD; + +typedef PREPACK struct { + A_UINT8 sta_chan_width; +} POSTPACK WMI_SET_HT_OP_CMD; + +typedef PREPACK struct { + A_UINT32 rateMasks[8]; +} POSTPACK WMI_SET_TX_SELECT_RATES_CMD; + +typedef PREPACK struct { + A_UINT32 sgiMask; + A_UINT8 sgiPERThreshold; +} POSTPACK WMI_SET_TX_SGI_PARAM_CMD; + + +typedef PREPACK struct { + A_UINT32 rateField; /* 1 bit per rate corresponding to index */ + A_UINT8 id; + A_UINT8 shortTrys; + A_UINT8 longTrys; + A_UINT8 reserved; /* padding */ +} POSTPACK WMI_SET_RATE_POLICY_CMD; + +typedef PREPACK struct { + A_UINT8 metaVersion; /* version of meta data for rx packets <0 = default> (0-7 = valid) */ + A_UINT8 dot11Hdr; /* 1 == leave .11 header intact , 0 == replace .11 header with .3 */ + A_UINT8 defragOnHost; /* 1 == defragmentation is performed by host, 0 == performed by target */ + A_UINT8 reserved[1]; /* alignment */ +} POSTPACK WMI_RX_FRAME_FORMAT_CMD; + + +typedef PREPACK struct { + A_UINT8 enable; // 1 == device operates in thin mode , 0 == normal mode */ + A_UINT8 reserved[3]; +} POSTPACK WMI_SET_THIN_MODE_CMD; + +/* AP mode events */ +/* WMI_PS_POLL_EVENT */ +typedef PREPACK struct { + A_UINT16 aid; +} POSTPACK WMI_PSPOLL_EVENT; + +typedef PREPACK struct { + A_UINT32 tx_bytes; + A_UINT32 tx_pkts; + A_UINT32 tx_error; + A_UINT32 tx_discard; + A_UINT32 rx_bytes; + A_UINT32 rx_pkts; + A_UINT32 rx_error; + A_UINT32 rx_discard; + A_UINT32 aid; +} POSTPACK WMI_PER_STA_STAT; + +#define AP_GET_STATS 0 +#define AP_CLEAR_STATS 1 + +typedef PREPACK struct { + A_UINT32 action; + WMI_PER_STA_STAT sta[AP_MAX_NUM_STA+1]; +} POSTPACK WMI_AP_MODE_STAT; +#define WMI_AP_MODE_STAT_SIZE(numSta) (sizeof(A_UINT32) + ((numSta + 1) * sizeof(WMI_PER_STA_STAT))) + +#define AP_11BG_RATESET1 1 +#define AP_11BG_RATESET2 2 +#define DEF_AP_11BG_RATESET AP_11BG_RATESET1 +typedef PREPACK struct { + A_UINT8 rateset; +} POSTPACK WMI_AP_SET_11BG_RATESET_CMD; +/* + * End of AP mode definitions + */ + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/wmi_api.h b/drivers/net/wireless/ath6kl/include/wmi_api.h new file mode 100644 index 000000000000..446c56eab0ed --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/wmi_api.h @@ -0,0 +1,435 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the definitions for the Wireless Module Interface (WMI). +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_API_H_ +#define _WMI_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + /* WMI converts a dix frame with an ethernet payload (up to 1500 bytes) + * to an 802.3 frame (adds SNAP header) and adds on a WMI data header */ +#define WMI_MAX_TX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR)) + + /* A normal WMI data frame */ +#define WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH (1500 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR)) + + /* An AMSDU frame */ +#define WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH (4096 + sizeof(WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + sizeof(ATH_LLC_SNAP_HDR)) + +/* + * IP QoS Field definitions according to 802.1p + */ +#define BEST_EFFORT_PRI 0 +#define BACKGROUND_PRI 1 +#define EXCELLENT_EFFORT_PRI 3 +#define CONTROLLED_LOAD_PRI 4 +#define VIDEO_PRI 5 +#define VOICE_PRI 6 +#define NETWORK_CONTROL_PRI 7 +#define MAX_NUM_PRI 8 + +#define UNDEFINED_PRI (0xff) + +#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */ + +#define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) + +typedef enum { + ATHEROS_COMPLIANCE = 0x1, +}TSPEC_PARAM_COMPLIANCE; + +struct wmi_t; + +void *wmi_init(void *devt); + +void wmi_qos_state_init(struct wmi_t *wmip); +void wmi_shutdown(struct wmi_t *wmip); +HTC_ENDPOINT_ID wmi_get_control_ep(struct wmi_t * wmip); +void wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid); +A_UINT16 wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8); +A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData, WMI_DATA_HDR_DATA_TYPE data_type,A_UINT8 metaVersion, void *pTxMetaS); +A_STATUS wmi_dot3_2_dix(void *osbuf); + +A_STATUS wmi_dot11_hdr_remove (struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_dot11_hdr_add(struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode); + +A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf); +A_STATUS wmi_syncpoint(struct wmi_t *wmip); +A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip); +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled); + +A_UINT8 wmi_determine_userPriority (A_UINT8 *pkt, A_UINT32 layer2Pri); + +A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf); +void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg); +void wmi_free_allnodes(struct wmi_t *wmip); +bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr); +void wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr); + + +typedef enum { + NO_SYNC_WMIFLAG = 0, + SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */ + SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */ + SYNC_BOTH_WMIFLAG, + END_WMIFLAG /* end marker */ +} WMI_SYNC_FLAG; + +A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG flag); + +A_STATUS wmi_connect_cmd(struct wmi_t *wmip, + NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, + AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, + A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, + A_UINT8 groupCryptoLen, + int ssidLength, + A_UCHAR *ssid, + A_UINT8 *bssid, + A_UINT16 channel, + A_UINT32 ctrl_flags); + +A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip, + A_UINT8 *bssid, + A_UINT16 channel); +A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip); +A_STATUS wmi_getrev_cmd(struct wmi_t *wmip); +A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList); +A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, + A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time, + A_UINT16 maxact_scan_per_ssid); +A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask); +A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid); +A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons); +A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons); +A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo); +A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode); +A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value); +A_STATUS wmi_apps_cmd(struct wmi_t *wmip, A_UINT8 psType, A_UINT32 idle_time, + A_UINT32 ps_period, A_UINT8 sleep_period); +A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy, + A_UINT16 wakup_tx_policy, A_UINT16 num_tx_to_wakeup, + A_UINT16 ps_fail_event_policy); +A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout); +A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber); +A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream); +A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID); +A_STATUS wmi_set_framerate_cmd(struct wmi_t *wmip, A_UINT8 bEnable, A_UINT8 type, A_UINT8 subType, A_UINT16 rateMask); +A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate); +A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip); +A_INT8 wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate); +A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList); + +A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip); +A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd); +A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold); +A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status, A_UINT8 preamblePolicy); + +A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask); + +A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, + A_UINT32 source); + +A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid); + +A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip); + +A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, + CRYPTO_TYPE keyType, A_UINT8 keyUsage, + A_UINT8 keyLength,A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *mac, + WMI_SYNC_FLAG sync_flag); +A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk); +A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip); +A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex); +A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams); +A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo); +A_STATUS wmi_abort_scan_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM); +A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip); +A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid); +A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex); +A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en); +A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set); +A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT8 ac, A_UINT16 txop, + A_UINT8 eCWmin, A_UINT8 eCWmax, + A_UINT8 aifsn); +A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify); + +void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid); + +A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip); +A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType); +A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size); +A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size); + +A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode); +A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData); + +A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl); +A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize); +A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen); +A_UINT8 convert_userPriority_to_trafficClass(A_UINT8 userPriority); +A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip); +A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance); + +#ifdef CONFIG_HOST_TCMD_SUPPORT +A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len); +#endif + +A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status); +A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd); + +A_STATUS wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd); + +A_STATUS wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd); + +A_STATUS wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *cmd); + +A_STATUS wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd); + +A_STATUS wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_A2DP_CONFIG_CMD* cmd); + + +A_STATUS wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD* cmd); + +A_STATUS wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd); + +A_STATUS wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip, + WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd); + +A_STATUS wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd); + +A_STATUS wmi_get_btcoex_stats_cmd(struct wmi_t * wmip); + +/* + * This function is used to configure the fix rates mask to the target. + */ +A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask); +A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip); + +A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode); + +A_STATUS wmi_set_qos_supp_cmd(struct wmi_t *wmip,A_UINT8 status); +A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status); +A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable); +A_STATUS wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode); + +A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip); +A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip); +A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval); + +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, + A_UINT8 ieLen,A_UINT8 *ieInfo); + +A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen); + +A_INT32 wmi_get_rate(A_INT8 rateindex); + +A_STATUS wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *cmd); + +/*Wake on Wireless WMI commands*/ +A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd); +A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd); +A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd); +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size); +A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *cmd); +A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status); + +A_STATUS +wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer); + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4); + +A_STATUS +wmi_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 enable); + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID); + + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss); + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge); + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS wmi_prof_cfg_cmd(struct wmi_t *wmip, A_UINT32 period, A_UINT32 nbins); +A_STATUS wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr); +A_STATUS wmi_prof_start_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_stop_cmd(struct wmi_t *wmip); +A_STATUS wmi_prof_count_get_cmd(struct wmi_t *wmip); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ +#ifdef OS_ROAM_MANAGEMENT +void wmi_scan_indication (struct wmi_t *wmip); +#endif + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd); + +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id); +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss); + + +/* + * AP mode + */ +A_STATUS +wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p); + +A_STATUS +wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid); + +A_STATUS +wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta); + +A_STATUS +wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy); + +A_STATUS +wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *a); + +A_UINT8 +acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl); + +A_STATUS +wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason); + +A_STATUS +wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag); + +A_STATUS +wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period); + +A_STATUS +wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell); + +A_STATUS +wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim); + +A_STATUS +wmi_ap_set_rateset(struct wmi_t *wmip, A_UINT8 rateset); + +A_STATUS +wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd); + +A_STATUS +wmi_set_ht_op_cmd(struct wmi_t *wmip, A_UINT8 sta_chan_width); + +A_STATUS +wmi_send_hci_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT16 sz); + +A_STATUS +wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray); + +A_STATUS +wmi_setup_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid); + +A_STATUS +wmi_delete_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid, A_BOOL uplink); + +A_STATUS +wmi_allow_aggr_cmd(struct wmi_t *wmip, A_UINT16 tx_tidmask, A_UINT16 rx_tidmask); + +A_STATUS +wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, A_UINT8 rxMetaVersion, A_BOOL rxDot11Hdr, A_BOOL defragOnHost); + +A_STATUS +wmi_set_thin_mode_cmd(struct wmi_t *wmip, A_BOOL bThinMode); + +A_STATUS +wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence); + +A_STATUS +wmi_set_pmk_cmd(struct wmi_t *wmip, A_UINT8 *pmk); + +A_UINT16 +wmi_ieee2freq (int chan); + +A_UINT32 +wmi_freq2ieee (A_UINT16 freq); + +bss_t * +wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, + A_UINT32 dot11AuthMode, A_UINT32 authMode, + A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_API_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/wmi_thin.h b/drivers/net/wireless/ath6kl/include/wmi_thin.h new file mode 100644 index 000000000000..1e300d1c6563 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/wmi_thin.h @@ -0,0 +1,343 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to WMI commands + * belongs to the host driver and the WM is not required to validate + * parameters for value, proper range, or any other checking. + * + */ + +#ifndef _WMI_THIN_H_ +#define _WMI_THIN_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef enum { + WMI_THIN_CONFIG_CMDID = 0x8000, // WMI_THIN_RESERVED_START + WMI_THIN_SET_MIB_CMDID, + WMI_THIN_GET_MIB_CMDID, + WMI_THIN_JOIN_CMDID, + /* add new CMDID's here */ + WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END +} WMI_THIN_COMMAND_ID; + +typedef enum{ + TEMPLATE_FRM_FIRST = 0, + TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST, + TEMPLATE_FRM_BEACON, + TEMPLATE_FRM_PROBE_RESP, + TEMPLATE_FRM_NULL, + TEMPLATE_FRM_QOS_NULL, + TEMPLATE_FRM_PSPOLL, + TEMPLATE_FRM_MAX +}WMI_TEMPLATE_FRM_TYPE; + +/* TEMPLATE_FRM_LEN... represent the maximum allowable + * data lengths (bytes) for each frame type */ +#define TEMPLATE_FRM_LEN_PROBE_REQ (256) /* Symbian dictates a minimum of 256 for these 3 frame types */ +#define TEMPLATE_FRM_LEN_BEACON (256) +#define TEMPLATE_FRM_LEN_PROBE_RESP (256) +#define TEMPLATE_FRM_LEN_NULL (32) +#define TEMPLATE_FRM_LEN_QOS_NULL (32) +#define TEMPLATE_FRM_LEN_PSPOLL (32) +#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \ + TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL) + + +/* MAC Header Build Rules */ +/* These values allow the host to configure the + * target code that is responsible for constructing + * the MAC header. In cases where the MAC header + * is provided by the host framework, the target + * has a diminished responsibility over what fields + * it must write. This will vary from framework to framework. + * Symbian requires different behavior from MAC80211 which + * requires different behavior from MS Native Wifi. */ +#define WMI_WRT_VER_TYPE 0x00000001 +#define WMI_WRT_DURATION 0x00000002 +#define WMI_WRT_DIRECTION 0x00000004 +#define WMI_WRT_POWER 0x00000008 +#define WMI_WRT_WEP 0x00000010 +#define WMI_WRT_MORE 0x00000020 +#define WMI_WRT_BSSID 0x00000040 +#define WMI_WRT_QOS 0x00000080 +#define WMI_WRT_SEQNO 0x00000100 +#define WMI_GUARD_TX 0x00000200 /* prevents TX ops that are not allowed for a current state */ +#define WMI_WRT_DEFAULT_CONFIG (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \ + WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \ + WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX) + +/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for + * TX Complete messages the will come from the Target. these messages are + * disabled by default but can be enabled using this structure and the + * WMI_THIN_CONFIG_CMDID. */ +typedef PREPACK struct { + A_UINT8 version; /* the versioned type of messages to use or 0 to disable */ + A_UINT8 countThreshold; /* msg count threshold triggering a tx complete message */ + A_UINT16 timeThreshold; /* timeout interval in MSEC triggering a tx complete message */ +} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE; + +/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames + * that have decryption errors. The default behavior is to discard the frame + * without notification. Alternately, the MAC Header is forwarded to the host + * with the failed status. */ +typedef PREPACK struct { + A_UINT8 enable; /* 1 == send decrypt errors to the host, 0 == don't */ + A_UINT8 reserved[3]; /* align padding */ +} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR; + +/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted + * frames that require partial MAC header construction. These rules + * are used by the target to indicate which fields need to be written. */ +typedef PREPACK struct { + A_UINT32 rules; /* combination of WMI_WRT_... values */ +} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES; + +/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received + * frames as to which frames should get forwarded to the host and which + * should get processed internally. */ +typedef PREPACK struct { + A_UINT32 rules; /* combination of WMI_FILT_... values */ +} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES; + +/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above + * WMI_THIN_CONFIG_... structures. The actual combination is indicated + * by the value of cfgField. Each bit in this field corresponds to + * one of the above structures. */ +typedef PREPACK struct { +#define WMI_THIN_CFG_TXCOMP 0x00000001 +#define WMI_THIN_CFG_DECRYPT 0x00000002 +#define WMI_THIN_CFG_MAC_RULES 0x00000004 +#define WMI_THIN_CFG_FILTER_RULES 0x00000008 + A_UINT32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */ + A_UINT16 length; /* length in bytes of appended sub-commands */ + A_UINT8 reserved[2]; /* align padding */ +} POSTPACK WMI_THIN_CONFIG_CMD; + +/* MIB Access Identifiers tailored for Symbian. */ +enum { + MIB_ID_STA_MAC = 1, // [READONLY] + MIB_ID_RX_LIFE_TIME, // [NOT IMPLEMENTED] + MIB_ID_SLOT_TIME, // [READ/WRITE] + MIB_ID_RTS_THRESHOLD, // [READ/WRITE] + MIB_ID_CTS_TO_SELF, // [READ/WRITE] + MIB_ID_TEMPLATE_FRAME, // [WRITE ONLY] + MIB_ID_RXFRAME_FILTER, // [READ/WRITE] + MIB_ID_BEACON_FILTER_TABLE, // [WRITE ONLY] + MIB_ID_BEACON_FILTER, // [READ/WRITE] + MIB_ID_BEACON_LOST_COUNT, // [WRITE ONLY] + MIB_ID_RSSI_THRESHOLD, // [WRITE ONLY] + MIB_ID_HT_CAP, // [NOT IMPLEMENTED] + MIB_ID_HT_OP, // [NOT IMPLEMENTED] + MIB_ID_HT_2ND_BEACON, // [NOT IMPLEMENTED] + MIB_ID_HT_BLOCK_ACK, // [NOT IMPLEMENTED] + MIB_ID_PREAMBLE, // [READ/WRITE] + /*MIB_ID_GROUP_ADDR_TABLE,*/ + /*MIB_ID_WEP_DEFAULT_KEY_ID */ + /*MIB_ID_TX_POWER */ + /*MIB_ID_ARP_IP_TABLE */ + /*MIB_ID_SLEEP_MODE */ + /*MIB_ID_WAKE_INTERVAL*/ + /*MIB_ID_STAT_TABLE*/ + /*MIB_ID_IBSS_PWR_SAVE*/ + /*MIB_ID_COUNTERS_TABLE*/ + /*MIB_ID_ETHERTYPE_FILTER*/ + /*MIB_ID_BC_UDP_FILTER*/ + +}; + +typedef PREPACK struct { + A_UINT8 addr[ATH_MAC_LEN]; +} POSTPACK WMI_THIN_MIB_STA_MAC; + +typedef PREPACK struct { + A_UINT32 time; // units == msec +} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME; + +typedef PREPACK struct { + A_UINT8 enable; //1 = on, 0 = off +} POSTPACK WMI_THIN_MIB_CTS_TO_SELF; + +typedef PREPACK struct { + A_UINT32 time; // units == usec +} POSTPACK WMI_THIN_MIB_SLOT_TIME; + +typedef PREPACK struct { + A_UINT16 length; //units == bytes +} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD; + +typedef PREPACK struct { + A_UINT8 type; // type of frame + A_UINT8 rate; // tx rate to be used (one of WMI_BIT_RATE) + A_UINT16 length; // num bytes following this structure as the template data +} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME; + +typedef PREPACK struct { +#define FRAME_FILTER_PROMISCUOUS 0x00000001 +#define FRAME_FILTER_BSSID 0x00000002 + A_UINT32 filterMask; +} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER; + + +#define IE_FILTER_TREATMENT_CHANGE 1 +#define IE_FILTER_TREATMENT_APPEAR 2 + +typedef PREPACK struct { + A_UINT8 ie; + A_UINT8 treatment; +} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE; + +typedef PREPACK struct { + A_UINT8 ie; + A_UINT8 treatment; + A_UINT8 oui[3]; + A_UINT8 type; + A_UINT16 version; +} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI; + +typedef PREPACK struct { + A_UINT16 numElements; + A_UINT8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4 + A_UINT8 reserved; +} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER; + +typedef PREPACK struct { + A_UINT32 count; /* num beacons between deliveries */ + A_UINT8 enable; + A_UINT8 reserved[3]; +} POSTPACK WMI_THIN_MIB_BEACON_FILTER; + +typedef PREPACK struct { + A_UINT32 count; /* num consec lost beacons after which send event */ +} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT; + +typedef PREPACK struct { + A_UINT8 rssi; /* the low threshold which can trigger an event warning */ + A_UINT8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */ + A_UINT8 count; /* the sample count of consecutive frames necessary to trigger an event. */ + A_UINT8 reserved[1]; /* padding */ +} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD; + + +typedef PREPACK struct { + A_UINT32 cap; + A_UINT32 rxRateField; + A_UINT32 beamForming; + A_UINT8 addr[ATH_MAC_LEN]; + A_UINT8 enable; + A_UINT8 stbc; + A_UINT8 maxAMPDU; + A_UINT8 msduSpacing; + A_UINT8 mcsFeedback; + A_UINT8 antennaSelCap; +} POSTPACK WMI_THIN_MIB_HT_CAP; + +typedef PREPACK struct { + A_UINT32 infoField; + A_UINT32 basicRateField; + A_UINT8 protection; + A_UINT8 secondChanneloffset; + A_UINT8 channelWidth; + A_UINT8 reserved; +} POSTPACK WMI_THIN_MIB_HT_OP; + +typedef PREPACK struct { +#define SECOND_BEACON_PRIMARY 1 +#define SECOND_BEACON_EITHER 2 +#define SECOND_BEACON_SECONDARY 3 + A_UINT8 cfg; + A_UINT8 reserved[3]; /* padding */ +} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON; + +typedef PREPACK struct { + A_UINT8 txTIDField; + A_UINT8 rxTIDField; + A_UINT8 reserved[2]; /* padding */ +} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK; + +typedef PREPACK struct { + A_UINT8 enableLong; // 1 == long preamble, 0 == short preamble + A_UINT8 reserved[3]; +} POSTPACK WMI_THIN_MIB_PREAMBLE; + +typedef PREPACK struct { + A_UINT16 length; /* the length in bytes of the appended MIB data */ + A_UINT8 mibID; /* the ID of the MIB element being set */ + A_UINT8 reserved; /* align padding */ +} POSTPACK WMI_THIN_SET_MIB_CMD; + +typedef PREPACK struct { + A_UINT8 mibID; /* the ID of the MIB element being set */ + A_UINT8 reserved[3]; /* align padding */ +} POSTPACK WMI_THIN_GET_MIB_CMD; + +typedef PREPACK struct { + A_UINT32 basicRateMask; /* bit mask of basic rates */ + A_UINT32 beaconIntval; /* TUs */ + A_UINT16 atimWindow; /* TUs */ + A_UINT16 channel; /* frequency in Mhz */ + A_UINT8 networkType; /* INFRA_NETWORK | ADHOC_NETWORK */ + A_UINT8 ssidLength; /* 0 - 32 */ + A_UINT8 probe; /* != 0 : issue probe req at start */ + A_UINT8 reserved; /* alignment */ + A_UCHAR ssid[WMI_MAX_SSID_LEN]; + A_UINT8 bssid[ATH_MAC_LEN]; +} POSTPACK WMI_THIN_JOIN_CMD; + +typedef PREPACK struct { + A_UINT16 dtim; /* dtim interval in num beacons */ + A_UINT16 aid; /* 80211 AID from Assoc resp */ +} POSTPACK WMI_THIN_POST_ASSOC_CMD; + +typedef enum { + WMI_THIN_EVENTID_RESERVED_START = 0x8000, + WMI_THIN_GET_MIB_EVENTID, + WMI_THIN_JOIN_EVENTID, + + /* Add new THIN EVENTID's here */ + WMI_THIN_EVENTID_RESERVED_END = 0x8fff +} WMI_THIN_EVENT_ID; + +/* Possible values for WMI_THIN_JOIN_EVENT.result */ +typedef enum { + WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network + WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason + WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit + WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param. +}WMI_THIN_JOIN_RESULT; + +typedef PREPACK struct { + A_UINT8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */ + A_UINT8 reserved[3]; /* alignment */ +} POSTPACK WMI_THIN_JOIN_EVENT; + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_THIN_H_ */ diff --git a/drivers/net/wireless/ath6kl/include/wmix.h b/drivers/net/wireless/ath6kl/include/wmix.h new file mode 100644 index 000000000000..7db5560f41f0 --- /dev/null +++ b/drivers/net/wireless/ath6kl/include/wmix.h @@ -0,0 +1,275 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +/* + * This file contains extensions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all + * extended commands and events. Extensions include useful commands + * that are not directly related to wireless activities. They may + * be hardware-specific, and they might not be supported on all + * implementations. + * + * Extended WMIX commands are encapsulated in a WMI message with + * cmd=WMI_EXTENSION_CMD. + */ + +#ifndef _WMIX_H_ +#define _WMIX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ATH_TARGET +#include "athstartpack.h" +#endif + +#include "dbglog.h" + +/* + * Extended WMI commands are those that are needed during wireless + * operation, but which are not really wireless commands. This allows, + * for instance, platform-specific commands. Extended WMI commands are + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID. + * Extended WMI events are similarly embedded in a WMI event message with + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID. + */ +typedef PREPACK struct { + A_UINT32 commandId; +} POSTPACK WMIX_CMD_HDR; + +typedef enum { + WMIX_DSETOPEN_REPLY_CMDID = 0x2001, + WMIX_DSETDATA_REPLY_CMDID, + WMIX_GPIO_OUTPUT_SET_CMDID, + WMIX_GPIO_INPUT_GET_CMDID, + WMIX_GPIO_REGISTER_SET_CMDID, + WMIX_GPIO_REGISTER_GET_CMDID, + WMIX_GPIO_INTR_ACK_CMDID, + WMIX_HB_CHALLENGE_RESP_CMDID, + WMIX_DBGLOG_CFG_MODULE_CMDID, + WMIX_PROF_CFG_CMDID, /* 0x200a */ + WMIX_PROF_ADDR_SET_CMDID, + WMIX_PROF_START_CMDID, + WMIX_PROF_STOP_CMDID, + WMIX_PROF_COUNT_GET_CMDID, +} WMIX_COMMAND_ID; + +typedef enum { + WMIX_DSETOPENREQ_EVENTID = 0x3001, + WMIX_DSETCLOSE_EVENTID, + WMIX_DSETDATAREQ_EVENTID, + WMIX_GPIO_INTR_EVENTID, + WMIX_GPIO_DATA_EVENTID, + WMIX_GPIO_ACK_EVENTID, + WMIX_HB_CHALLENGE_RESP_EVENTID, + WMIX_DBGLOG_EVENTID, + WMIX_PROF_COUNT_EVENTID, +} WMIX_EVENT_ID; + +/* + * =============DataSet support================= + */ + +/* + * WMIX_DSETOPENREQ_EVENTID + * DataSet Open Request Event + */ +typedef PREPACK struct { + A_UINT32 dset_id; + A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETOPENREQ_EVENT; + +/* + * WMIX_DSETCLOSE_EVENTID + * DataSet Close Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; +} POSTPACK WMIX_DSETCLOSE_EVENT; + +/* + * WMIX_DSETDATAREQ_EVENTID + * DataSet Data Request Event + */ +typedef PREPACK struct { + A_UINT32 access_cookie; + A_UINT32 offset; + A_UINT32 length; + A_UINT32 targ_buf; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */ + A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */ +} POSTPACK WMIX_DSETDATAREQ_EVENT; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_dset_handle; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 access_cookie; + A_UINT32 size; + A_UINT32 version; +} POSTPACK WMIX_DSETOPEN_REPLY_CMD; + +typedef PREPACK struct { + A_UINT32 status; + A_UINT32 targ_buf; + A_UINT32 targ_reply_fn; + A_UINT32 targ_reply_arg; + A_UINT32 length; + A_UINT8 buf[1]; +} POSTPACK WMIX_DSETDATA_REPLY_CMD; + + +/* + * =============GPIO support================= + * All masks are 18-bit masks with bit N operating on GPIO pin N. + */ + +#include "gpio.h" + +/* + * Set GPIO pin output state. + * In order for output to be driven, a pin must be enabled for output. + * This can be done during initialization through the GPIO Configuration + * DataSet, or during operation with the enable_mask. + * + * If a request is made to simultaneously set/clear or set/disable or + * clear/disable or disable/enable, results are undefined. + */ +typedef PREPACK struct { + A_UINT32 set_mask; /* pins to set */ + A_UINT32 clear_mask; /* pins to clear */ + A_UINT32 enable_mask; /* pins to enable for output */ + A_UINT32 disable_mask; /* pins to disable/tristate */ +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD; + +/* + * Set a GPIO register. For debug/exceptional cases. + * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a + * platform-dependent header. + */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register ID */ + A_UINT32 value; /* value to write */ +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD; + +/* Get a GPIO register. For debug/exceptional cases. */ +typedef PREPACK struct { + A_UINT32 gpioreg_id; /* GPIO register to read */ +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD; + +/* + * Host acknowledges and re-arms GPIO interrupts. A single + * message should be used to acknowledge all interrupts that + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message. + */ +typedef PREPACK struct { + A_UINT32 ack_mask; /* interrupts to acknowledge */ +} POSTPACK WMIX_GPIO_INTR_ACK_CMD; + +/* + * Target informs Host of GPIO interrupts that have ocurred since the + * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information -- + * the current GPIO input values is provided -- in order to support + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins. + */ +typedef PREPACK struct { + A_UINT32 intr_mask; /* pending GPIO interrupts */ + A_UINT32 input_values; /* recent GPIO input values */ +} POSTPACK WMIX_GPIO_INTR_EVENT; + +/* + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the mask of GPIO pin inputs and + * reg_id set to GPIO_ID_NONE + * + * + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request + * using a GPIO_DATA_EVENT with + * value set to the value of the requested register and + * reg_id identifying the register (reflects the original request) + * NB: reg_id supports the future possibility of unsolicited + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may + * simplify Host GPIO support. + */ +typedef PREPACK struct { + A_UINT32 value; + A_UINT32 reg_id; +} POSTPACK WMIX_GPIO_DATA_EVENT; + +/* + * =============Error Detection support================= + */ + +/* + * WMIX_HB_CHALLENGE_RESP_CMDID + * Heartbeat Challenge Response command + */ +typedef PREPACK struct { + A_UINT32 cookie; + A_UINT32 source; +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD; + +/* + * WMIX_HB_CHALLENGE_RESP_EVENTID + * Heartbeat Challenge Response Event + */ +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD + +typedef PREPACK struct { + struct dbglog_config_s config; +} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD; + +/* + * =============Target Profiling support================= + */ + +typedef PREPACK struct { + A_UINT32 period; /* Time (in 30.5us ticks) between samples */ + A_UINT32 nbins; +} POSTPACK WMIX_PROF_CFG_CMD; + +typedef PREPACK struct { + A_UINT32 addr; +} POSTPACK WMIX_PROF_ADDR_SET_CMD; + +/* + * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request + * using a WMIX_PROF_COUNT_EVENT with + * addr set to the next address + * count set to the corresponding count + */ +typedef PREPACK struct { + A_UINT32 addr; + A_UINT32 count; +} POSTPACK WMIX_PROF_COUNT_EVENT; + +#ifndef ATH_TARGET +#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMIX_H_ */ diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c new file mode 100644 index 000000000000..44ae924ef134 --- /dev/null +++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kconfig.c @@ -0,0 +1,432 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// AR3K configuration implementation +// +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#define ATH_MODULE_NAME misc +#include "a_debug.h" +#include "common_drv.h" +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +#include "export_hci_transport.h" +#else +#include "hci_transport_api.h" +#endif +#include "ar3kconfig.h" + +#define BAUD_CHANGE_COMMAND_STATUS_OFFSET 5 +#define HCI_EVENT_RESP_TIMEOUTMS 3000 +#define HCI_CMD_OPCODE_BYTE_LOW_OFFSET 0 +#define HCI_CMD_OPCODE_BYTE_HI_OFFSET 1 +#define HCI_EVENT_OPCODE_BYTE_LOW 3 +#define HCI_EVENT_OPCODE_BYTE_HI 4 +#define HCI_CMD_COMPLETE_EVENT_CODE 0xE +#define HCI_MAX_EVT_RECV_LENGTH 257 +#define EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET 5 + +A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev); + +static A_STATUS SendHCICommand(AR3K_CONFIG_INFO *pConfig, + A_UINT8 *pBuffer, + int Length) +{ + HTC_PACKET *pPacket = NULL; + A_STATUS status = A_OK; + + do { + + pPacket = (HTC_PACKET *)A_MALLOC(sizeof(HTC_PACKET)); + if (NULL == pPacket) { + status = A_NO_MEMORY; + break; + } + + A_MEMZERO(pPacket,sizeof(HTC_PACKET)); + SET_HTC_PACKET_INFO_TX(pPacket, + NULL, + pBuffer, + Length, + HCI_COMMAND_TYPE, + AR6K_CONTROL_PKT_TAG); + + /* issue synchronously */ + status = HCI_TransportSendPkt(pConfig->pHCIDev,pPacket,TRUE); + + } while (FALSE); + + if (pPacket != NULL) { + A_FREE(pPacket); + } + + return status; +} + +static A_STATUS RecvHCIEvent(AR3K_CONFIG_INFO *pConfig, + A_UINT8 *pBuffer, + int *pLength) +{ + A_STATUS status = A_OK; + HTC_PACKET *pRecvPacket = NULL; + + do { + + pRecvPacket = (HTC_PACKET *)A_MALLOC(sizeof(HTC_PACKET)); + if (NULL == pRecvPacket) { + status = A_NO_MEMORY; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n")); + break; + } + + A_MEMZERO(pRecvPacket,sizeof(HTC_PACKET)); + + SET_HTC_PACKET_INFO_RX_REFILL(pRecvPacket,NULL,pBuffer,*pLength,HCI_EVENT_TYPE); + + status = HCI_TransportRecvHCIEventSync(pConfig->pHCIDev, + pRecvPacket, + HCI_EVENT_RESP_TIMEOUTMS); + if (A_FAILED(status)) { + break; + } + + *pLength = pRecvPacket->ActualLength; + + } while (FALSE); + + if (pRecvPacket != NULL) { + A_FREE(pRecvPacket); + } + + return status; +} + +A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig, + A_UINT8 *pHCICommand, + int CmdLength, + A_UINT8 **ppEventBuffer, + A_UINT8 **ppBufferToFree) +{ + A_STATUS status = A_OK; + A_UINT8 *pBuffer = NULL; + A_UINT8 *pTemp; + int length; + A_BOOL commandComplete = FALSE; + A_UINT8 opCodeBytes[2]; + + do { + + length = max(HCI_MAX_EVT_RECV_LENGTH,CmdLength); + length += pConfig->pHCIProps->HeadRoom + pConfig->pHCIProps->TailRoom; + length += pConfig->pHCIProps->IOBlockPad; + + pBuffer = (A_UINT8 *)A_MALLOC(length); + if (NULL == pBuffer) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to allocate bt buffer \n")); + status = A_NO_MEMORY; + break; + } + + /* get the opcodes to check the command complete event */ + opCodeBytes[0] = pHCICommand[HCI_CMD_OPCODE_BYTE_LOW_OFFSET]; + opCodeBytes[1] = pHCICommand[HCI_CMD_OPCODE_BYTE_HI_OFFSET]; + + /* copy HCI command */ + A_MEMCPY(pBuffer + pConfig->pHCIProps->HeadRoom,pHCICommand,CmdLength); + /* send command */ + status = SendHCICommand(pConfig, + pBuffer + pConfig->pHCIProps->HeadRoom, + CmdLength); + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Failed to send HCI Command (%d) \n", status)); + AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command"); + break; + } + + /* reuse buffer to capture command complete event */ + A_MEMZERO(pBuffer,length); + status = RecvHCIEvent(pConfig,pBuffer,&length); + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI event recv failed \n")); + AR_DEBUG_PRINTBUF(pHCICommand,CmdLength,"HCI Bridge Failed HCI Command"); + break; + } + + pTemp = pBuffer + pConfig->pHCIProps->HeadRoom; + if (pTemp[0] == HCI_CMD_COMPLETE_EVENT_CODE) { + if ((pTemp[HCI_EVENT_OPCODE_BYTE_LOW] == opCodeBytes[0]) && + (pTemp[HCI_EVENT_OPCODE_BYTE_HI] == opCodeBytes[1])) { + commandComplete = TRUE; + } + } + + if (!commandComplete) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Unexpected HCI event : %d \n",pTemp[0])); + AR_DEBUG_PRINTBUF(pTemp,pTemp[1],"Unexpected HCI event"); + status = A_ECOMM; + break; + } + + if (ppEventBuffer != NULL) { + /* caller wants to look at the event */ + *ppEventBuffer = pTemp; + if (ppBufferToFree == NULL) { + status = A_EINVAL; + break; + } + /* caller must free the buffer */ + *ppBufferToFree = pBuffer; + pBuffer = NULL; + } + + } while (FALSE); + + if (pBuffer != NULL) { + A_FREE(pBuffer); + } + + return status; +} + +static A_STATUS AR3KConfigureHCIBaud(AR3K_CONFIG_INFO *pConfig) +{ + A_STATUS status = A_OK; + A_UINT8 hciBaudChangeCommand[] = {0x0c,0xfc,0x2,0,0}; + A_UINT16 baudVal; + A_UINT8 *pEvent = NULL; + A_UINT8 *pBufferToFree = NULL; + + do { + + if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR3K_BAUD) { + baudVal = (A_UINT16)(pConfig->AR3KBaudRate / 100); + hciBaudChangeCommand[3] = (A_UINT8)baudVal; + hciBaudChangeCommand[4] = (A_UINT8)(baudVal >> 8); + + status = SendHCICommandWaitCommandComplete(pConfig, + hciBaudChangeCommand, + sizeof(hciBaudChangeCommand), + &pEvent, + &pBufferToFree); + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: Baud rate change failed! \n")); + break; + } + + if (pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET] != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("AR3K Config: Baud change command event status failed: %d \n", + pEvent[BAUD_CHANGE_COMMAND_STATUS_OFFSET])); + status = A_ECOMM; + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("AR3K Config: Baud Changed to %d \n",pConfig->AR3KBaudRate)); + } + + if (pConfig->Flags & AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY) { + /* some versions of AR3K do not switch baud immediately, up to 300MS */ + A_MDELAY(325); + } + + if (pConfig->Flags & AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP) { + /* Tell target to change UART baud rate for AR6K */ + status = HCI_TransportSetBaudRate(pConfig->pHCIDev, pConfig->AR3KBaudRate); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("AR3K Config: failed to set scale and step values: %d \n", status)); + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ANY, + ("AR3K Config: Baud changed to %d for AR6K\n", pConfig->AR3KBaudRate)); + } + + } while (FALSE); + + if (pBufferToFree != NULL) { + A_FREE(pBufferToFree); + } + + return status; +} + +static A_STATUS AR3KExitMinBoot(AR3K_CONFIG_INFO *pConfig) +{ + A_STATUS status; + A_CHAR exitMinBootCmd[] = {0x25,0xFC,0x0c,0x03,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00}; + A_UINT8 *pEvent = NULL; + A_UINT8 *pBufferToFree = NULL; + + status = SendHCICommandWaitCommandComplete(pConfig, + exitMinBootCmd, + sizeof(exitMinBootCmd), + &pEvent, + &pBufferToFree); + + if (A_SUCCESS(status)) { + if (pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET] != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("AR3K Config: MinBoot exit command event status failed: %d \n", + pEvent[EXIT_MIN_BOOT_COMMAND_STATUS_OFFSET])); + status = A_ECOMM; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("AR3K Config: MinBoot Exit Command Complete (Success) \n")); + A_MDELAY(1); + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: MinBoot Exit Failed! \n")); + } + + if (pBufferToFree != NULL) { + A_FREE(pBufferToFree); + } + + return status; +} + +static A_STATUS AR3KConfigureSendHCIReset(AR3K_CONFIG_INFO *pConfig) +{ + A_STATUS status = A_OK; + A_UINT8 hciResetCommand[] = {0x03,0x0c,0x0}; + A_UINT8 *pEvent = NULL; + A_UINT8 *pBufferToFree = NULL; + + status = SendHCICommandWaitCommandComplete( pConfig, + hciResetCommand, + sizeof(hciResetCommand), + &pEvent, + &pBufferToFree ); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR3K Config: HCI reset failed! \n")); + } + + if (pBufferToFree != NULL) { + A_FREE(pBufferToFree); + } + + return status; +} + +A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfig) +{ + A_STATUS status = A_OK; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuring AR3K ...\n")); + + do { + + if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) { + status = A_EINVAL; + break; + } + + /* disable asynchronous recv while we issue commands and receive events synchronously */ + status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,FALSE); + if (A_FAILED(status)) { + break; + } + + if (pConfig->Flags & AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT) { + status = AR3KExitMinBoot(pConfig); + if (A_FAILED(status)) { + break; + } + } + + if (pConfig->Flags & + (AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) { + status = AR3KConfigureHCIBaud(pConfig); + if (A_FAILED(status)) { + break; + } + } + + /* Load patching and PST file if available*/ + if (A_OK != AthPSInitialize(pConfig)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Patch Download Failed!\n")); + } + + /* Send HCI reset to make PS tags take effect*/ + AR3KConfigureSendHCIReset(pConfig); + + /* re-enable asynchronous recv */ + status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,TRUE); + if (A_FAILED(status)) { + break; + } + + + } while (FALSE); + + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Configuration Complete (status = %d) \n",status)); + + return status; +} + +A_STATUS AR3KConfigureExit(void *config) +{ + A_STATUS status = A_OK; + AR3K_CONFIG_INFO *pConfig = (AR3K_CONFIG_INFO *)config; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleaning up AR3K ...\n")); + + do { + + if ((pConfig->pHCIDev == NULL) || (pConfig->pHCIProps == NULL) || (pConfig->pHIFDevice == NULL)) { + status = A_EINVAL; + break; + } + + /* disable asynchronous recv while we issue commands and receive events synchronously */ + status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,FALSE); + if (A_FAILED(status)) { + break; + } + + if (pConfig->Flags & + (AR3K_CONFIG_FLAG_SET_AR3K_BAUD | AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP)) { + status = AR3KConfigureHCIBaud(pConfig); + if (A_FAILED(status)) { + break; + } + } + + /* re-enable asynchronous recv */ + status = HCI_TransportEnableDisableAsyncRecv(pConfig->pHCIDev,TRUE); + if (A_FAILED(status)) { + break; + } + + + } while (FALSE); + + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR3K Config: Cleanup Complete (status = %d) \n",status)); + + return status; +} + diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c new file mode 100644 index 000000000000..d4048c8efd0c --- /dev/null +++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2004-2008 Atheros Communications Inc. + * All rights reserved. + * + * This file implements the Atheros PS and patch downloaded for HCI UART Transport driver. + * This file can be used for HCI SDIO transport implementation for AR6002 with HCI_TRANSPORT_SDIO + * defined. + * + * + * ar3kcpsconfig.c + * + * + * + * The software source and binaries included in this development package are + * licensed, not sold. You, or your company, received the package under one + * or more license agreements. The rights granted to you are specifically + * listed in these license agreement(s). All other rights remain with Atheros + * Communications, Inc., its subsidiaries, or the respective owner including + * those listed on the included copyright notices.. Distribution of any + * portion of this package must be in strict compliance with the license + * agreement(s) terms. + * + * + * + */ + + + +#include "ar3kpsconfig.h" +#ifndef HCI_TRANSPORT_SDIO +#include "hci_ath.h" +#include "hci_uart.h" +#endif /* #ifndef HCI_TRANSPORT_SDIO */ + +/* + * Structure used to send HCI packet, hci packet length and device info + * together as parameter to PSThread. + */ +typedef struct { + + PSCmdPacket *HciCmdList; + A_UINT32 num_packets; + AR3K_CONFIG_INFO *dev; +}HciCommandListParam; + +A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig, + A_UINT8 *pHCICommand, + int CmdLength, + A_UINT8 **ppEventBuffer, + A_UINT8 **ppBufferToFree); + +A_UINT32 Rom_Version; +A_UINT32 Build_Version; + +A_STATUS getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code); +A_STATUS ReadVersionInfo(AR3K_CONFIG_INFO *pConfig); +#ifndef HCI_TRANSPORT_SDIO + +DECLARE_WAIT_QUEUE_HEAD(PsCompleteEvent); +DECLARE_WAIT_QUEUE_HEAD(HciEvent); +A_UCHAR *HciEventpacket; +rwlock_t syncLock; +wait_queue_t Eventwait; + +int PSHciWritepacket(struct hci_dev*,A_UCHAR* Data, A_UINT32 len); +extern char *bdaddr; +#endif /* HCI_TRANSPORT_SDIO */ + +A_STATUS write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr); + +int PSSendOps(void *arg); + +#ifdef BT_PS_DEBUG +void Hci_log(A_UCHAR * log_string,A_UCHAR *data,A_UINT32 len) +{ + int i; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s : ",log_string)); + for (i = 0; i < len; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("0x%02x ", data[i])); + } + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n...................................\n")); +} +#else +#define Hci_log(string,data,len) +#endif /* BT_PS_DEBUG */ + + + + +A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev) +{ + A_STATUS status = A_OK; + if(hdev == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Device handle received\n")); + return A_ERROR; + } + +#ifndef HCI_TRANSPORT_SDIO + DECLARE_WAITQUEUE(wait, current); +#endif /* HCI_TRANSPORT_SDIO */ + + +#ifdef HCI_TRANSPORT_SDIO + status = PSSendOps((void*)hdev); +#else + if(InitPSState(hdev) == -1) { + return A_ERROR; + } + allow_signal(SIGKILL); + add_wait_queue(&PsCompleteEvent,&wait); + set_current_state(TASK_INTERRUPTIBLE); + if(!kernel_thread(PSSendOps,(void*)hdev,CLONE_FS|CLONE_FILES|CLONE_SIGHAND|SIGCHLD)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Kthread Failed\n")); + remove_wait_queue(&PsCompleteEvent,&wait); + return A_ERROR; + } + wait_event_interruptible(PsCompleteEvent,(PSTagMode == FALSE)); + set_current_state(TASK_RUNNING); + remove_wait_queue(&PsCompleteEvent,&wait); + +#endif /* HCI_TRANSPORT_SDIO */ + + + return status; + +} + +int PSSendOps(void *arg) +{ + int i; + int status = 0; + PSCmdPacket *HciCmdList; /* List storing the commands */ + const struct firmware* firmware; + A_UINT32 numCmds; + A_UINT8 *event; + A_UINT8 *bufferToFree; + struct hci_dev *device; + A_UCHAR *buffer; + A_UINT32 len; + A_UINT32 DevType; + A_UCHAR *PsFileName; + A_UCHAR *patchFileName; + AR3K_CONFIG_INFO *hdev = (AR3K_CONFIG_INFO*)arg; + struct device *firmwareDev = NULL; + status = 0; + HciCmdList = NULL; +#ifdef HCI_TRANSPORT_SDIO + device = hdev->pBtStackHCIDev; + firmwareDev = device->parent; +#else + device = hdev; + firmwareDev = &device->dev; + AthEnableSyncCommandOp(TRUE); +#endif /* HCI_TRANSPORT_SDIO */ + /* First verify if the controller is an FPGA or ASIC, so depending on the device type the PS file to be written will be different. + */ + if(A_ERROR == getDeviceType(hdev,&DevType)) { + status = 1; + goto complete; + } + if(A_ERROR == ReadVersionInfo(hdev)) { + status = 1; + goto complete; + } + patchFileName = PATCH_FILE; + if(DevType){ + if(DevType == 0xdeadc0de){ + PsFileName = PS_ASIC_FILE; + } else{ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" FPGA Test Image : %x %x \n",Rom_Version,Build_Version)); + if((Rom_Version == 0x99999999) && (Build_Version == 1)){ + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("FPGA Test Image : Skipping Patch File load\n")); + patchFileName = NULL; + } + PsFileName = PS_FPGA_FILE; + } + } + else{ + PsFileName = PS_ASIC_FILE; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%x: FPGA/ASIC PS File Name %s\n", DevType,PsFileName)); + /* Read the PS file to a dynamically allocated buffer */ + if(request_firmware(&firmware,PsFileName,firmwareDev) < 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ )); + status = 1; + goto complete; + + } + if(NULL == firmware || firmware->size == 0) { + status = 1; + goto complete; + } + buffer = (A_UCHAR *)A_MALLOC(firmware->size); + if(buffer != NULL) { + /* Copy the read file to a local Dynamic buffer */ + memcpy(buffer,firmware->data,firmware->size); + len = firmware->size; + release_firmware(firmware); + /* Parse the PS buffer to a global variable */ + status = AthDoParsePS(buffer,len); + A_FREE(buffer); + } else { + release_firmware(firmware); + } + + + /* Read the patch file to a dynamically allocated buffer */ + if((patchFileName == NULL) || (request_firmware(&firmware,patchFileName,firmwareDev) < 0)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: firmware file open error\n", __FUNCTION__ )); + /* + * It is not necessary that Patch file be available, continue with PS Operations if. + * failed. + */ + status = 0; + + } else { + if(NULL == firmware || firmware->size == 0) { + status = 0; + } else { + buffer = (A_UCHAR *)A_MALLOC(firmware->size); + if(buffer != NULL) { + /* Copy the read file to a local Dynamic buffer */ + memcpy(buffer,firmware->data,firmware->size); + len = firmware->size; + release_firmware(firmware); + /* parse and store the Patch file contents to a global variables */ + status = AthDoParsePatch(buffer,len); + A_FREE(buffer); + } else { + release_firmware(firmware); + } + } + } + + /* Create an HCI command list from the parsed PS and patch information */ + AthCreateCommandList(&HciCmdList,&numCmds); + + /* Form the parameter for PSSendOps() API */ + + + /* + * First Send the CRC packet, + * We have to continue with the PS operations only if the CRC packet has been replied with + * a Command complete event with status Error. + */ + + if(SendHCICommandWaitCommandComplete + (hdev, + HciCmdList[0].Hcipacket, + HciCmdList[0].packetLen, + &event, + &bufferToFree) == A_OK) { + if(ReadPSEvent(event) == A_OK) { /* Exit if the status is success */ + if(bufferToFree != NULL) { + A_FREE(bufferToFree); + } +#ifndef HCI_TRANSPORT_SDIO + if(bdaddr[0] !='\0') { + write_bdaddr(hdev,bdaddr); + } +#endif + status = 1; + goto complete; + } + if(bufferToFree != NULL) { + A_FREE(bufferToFree); + } + } else { + status = 0; + goto complete; + } + + for(i = 1; i size == 0) { + status = 1; + goto complete; + } + write_bdaddr(hdev,(A_UCHAR *)firmware->data); + release_firmware(firmware); + } +complete: +#ifndef HCI_TRANSPORT_SDIO + AthEnableSyncCommandOp(FALSE); + PSTagMode = FALSE; + wake_up_interruptible(&PsCompleteEvent); +#endif /* HCI_TRANSPORT_SDIO */ + if(NULL != HciCmdList) { + AthFreeCommandList(&HciCmdList,numCmds); + } + return status; +} +#ifndef HCI_TRANSPORT_SDIO +/* + * This API is used to send the HCI command to controller and return + * with a HCI Command Complete event. + * For HCI SDIO transport, this will be internally defined. + */ +A_STATUS SendHCICommandWaitCommandComplete(AR3K_CONFIG_INFO *pConfig, + A_UINT8 *pHCICommand, + int CmdLength, + A_UINT8 **ppEventBuffer, + A_UINT8 **ppBufferToFree) +{ + if(CmdLength == 0) { + return A_ERROR; + } + Hci_log("COM Write -->",pHCICommand,CmdLength); + PSAcked = FALSE; + if(PSHciWritepacket(pConfig,pHCICommand,CmdLength) == 0) { + /* If the controller is not available, return Error */ + return A_ERROR; + } + //add_timer(&psCmdTimer); + wait_event_interruptible(HciEvent,(PSAcked == TRUE)); + if(NULL != HciEventpacket) { + *ppEventBuffer = HciEventpacket; + *ppBufferToFree = HciEventpacket; + } else { + /* Did not get an event from controller. return error */ + *ppBufferToFree = NULL; + return A_ERROR; + } + + return A_OK; +} +#endif /* HCI_TRANSPORT_SDIO */ + +A_STATUS ReadPSEvent(A_UCHAR* Data){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" PS Event %x %x %x\n",Data[4],Data[5],Data[3])); + + if(Data[4] == 0xFC && Data[5] == 0x00) + { + switch(Data[3]){ + case 0x0B: + return A_OK; + break; + case 0x0C: + /* Change Baudrate */ + return A_OK; + break; + case 0x04: + return A_OK; + break; + case 0x1E: + Rom_Version = Data[9]; + Rom_Version = ((Rom_Version << 8) |Data[8]); + Rom_Version = ((Rom_Version << 8) |Data[7]); + Rom_Version = ((Rom_Version << 8) |Data[6]); + + Build_Version = Data[13]; + Build_Version = ((Build_Version << 8) |Data[12]); + Build_Version = ((Build_Version << 8) |Data[11]); + Build_Version = ((Build_Version << 8) |Data[10]); + return A_OK; + break; + + + } + } + + return A_ERROR; +} +int str2ba(unsigned char *str_bdaddr,unsigned char *bdaddr) +{ + unsigned char bdbyte[3]; + unsigned char *str_byte = str_bdaddr; + int i,j; + unsigned char colon_present = 0; + + if(NULL != strstr(str_bdaddr,":")) { + colon_present = 1; + } + + + bdbyte[2] = '\0'; + + for( i = 0,j = 5; i < 6; i++, j--) { + bdbyte[0] = str_byte[0]; + bdbyte[1] = str_byte[1]; + bdaddr[j] = A_STRTOL(bdbyte,NULL,16); + if(colon_present == 1) { + str_byte+=3; + } else { + str_byte+=2; + } + } + return 0; +} + +A_STATUS write_bdaddr(AR3K_CONFIG_INFO *pConfig,A_UCHAR *bdaddr) +{ + A_UCHAR bdaddr_cmd[] = { 0x0B, 0xFC, 0x0A, 0x01, 0x01, + 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + A_UINT8 *event; + A_UINT8 *bufferToFree = NULL; + A_STATUS result = A_ERROR; + + str2ba(bdaddr,&bdaddr_cmd[7]); + + if(A_OK == SendHCICommandWaitCommandComplete(pConfig,bdaddr_cmd, + sizeof(bdaddr_cmd), + &event,&bufferToFree)) { + + if(event[4] == 0xFC && event[5] == 0x00){ + if(event[3] == 0x0B){ + result = A_OK; + } + } + + } + if(bufferToFree != NULL) { + A_FREE(bufferToFree); + } + return result; + +} +A_STATUS ReadVersionInfo(AR3K_CONFIG_INFO *pConfig) +{ + A_UINT8 hciCommand[] = {0x1E,0xfc,0x00}; + A_UINT8 *event; + A_UINT8 *bufferToFree = NULL; + A_STATUS result = A_ERROR; + if(A_OK == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) { + result = ReadPSEvent(event); + + } + if(bufferToFree != NULL) { + A_FREE(bufferToFree); + } + return result; +} +A_STATUS getDeviceType(AR3K_CONFIG_INFO *pConfig, A_UINT32 * code) +{ + A_UINT8 hciCommand[] = {0x05,0xfc,0x05,0x00,0x00,0x00,0x00,0x04}; + A_UINT8 *event; + A_UINT8 *bufferToFree = NULL; + A_UINT32 reg; + A_STATUS result = A_ERROR; + *code = 0; + hciCommand[3] = (A_UINT8)(FPGA_REGISTER & 0xFF); + hciCommand[4] = (A_UINT8)((FPGA_REGISTER >> 8) & 0xFF); + hciCommand[5] = (A_UINT8)((FPGA_REGISTER >> 16) & 0xFF); + hciCommand[6] = (A_UINT8)((FPGA_REGISTER >> 24) & 0xFF); + if(A_OK == SendHCICommandWaitCommandComplete(pConfig,hciCommand,sizeof(hciCommand),&event,&bufferToFree)) { + + if(event[4] == 0xFC && event[5] == 0x00){ + switch(event[3]){ + case 0x05: + reg = event[9]; + reg = ((reg << 8) |event[8]); + reg = ((reg << 8) |event[7]); + reg = ((reg << 8) |event[6]); + *code = reg; + result = A_OK; + + break; + case 0x06: + //Sleep(500); + break; + } + } + + } + if(bufferToFree != NULL) { + A_FREE(bufferToFree); + } + return result; +} + + diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h new file mode 100644 index 000000000000..2dd664e47798 --- /dev/null +++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsconfig.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2004-2008 Atheros Communications Inc. + * All rights reserved. + * + * This file defines the symbols exported by Atheros PS and patch download module. + * define the constant HCI_TRANSPORT_SDIO if the module is being used for HCI SDIO transport. + * defined. + * + * + * ar3kcpsconfig.h + * + * + * + * The software source and binaries included in this development package are + * licensed, not sold. You, or your company, received the package under one + * or more license agreements. The rights granted to you are specifically + * listed in these license agreement(s). All other rights remain with Atheros + * Communications, Inc., its subsidiaries, or the respective owner including + * those listed on the included copyright notices.. Distribution of any + * portion of this package must be in strict compliance with the license + * agreement(s) terms. + * + * + * + */ + + + +#ifndef __AR3KPSCONFIG_H +#define __AR3KPSCONFIG_H + +/* + * Define the flag HCI_TRANSPORT_SDIO and undefine HCI_TRANSPORT_UART if the transport being used is SDIO. + */ +#undef HCI_TRANSPORT_UART + +#include +#include +#include +#include +#include + + +#include +#include +#include +#include + + +#include +#include + +#include "ar3kpsparser.h" + +#define FPGA_REGISTER 0x4FFC + + +#define PS_ASIC_FILE "PS_ASIC.pst" +#define PS_FPGA_FILE "PS_FPGA.pst" + +#define PATCH_FILE "RamPatch.txt" +#define BDADDR_FILE "ar3kbdaddr.pst" + + +#ifndef HCI_TRANSPORT_SDIO +#define AR3K_CONFIG_INFO struct hci_dev +extern wait_queue_head_t HciEvent; +extern wait_queue_t Eventwait; +extern A_UCHAR *HciEventpacket; +#endif /* #ifndef HCI_TRANSPORT_SDIO */ + +A_STATUS AthPSInitialize(AR3K_CONFIG_INFO *hdev); +A_STATUS ReadPSEvent(A_UCHAR* Data); +#endif /* __AR3KPSCONFIG_H */ diff --git a/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c new file mode 100644 index 000000000000..8392777512ec --- /dev/null +++ b/drivers/net/wireless/ath6kl/miscdrv/ar3kps/ar3kpsparser.c @@ -0,0 +1,972 @@ +/* + * Copyright (c) 2004-2008 Atheros Communications Inc. + * All rights reserved. + * + * This file implements the Atheros PS and patch parser. + * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands. + * + * + * + * ar3kpsparser.c + * + * + * + * The software source and binaries included in this development package are + * licensed, not sold. You, or your company, received the package under one + * or more license agreements. The rights granted to you are specifically + * listed in these license agreement(s). All other rights remain with Atheros + * Communications, Inc., its subsidiaries, or the respective owner including + * those listed on the included copyright notices.. Distribution of any + * portion of this package must be in strict compliance with the license + * agreement(s) terms. + * + * + * + */ + + +#include "ar3kpsparser.h" + +#define BD_ADDR_SIZE 6 +#define WRITE_PATCH 8 +#define ENABLE_PATCH 11 +#define PS_RESET 2 +#define PS_WRITE 1 +#define PS_VERIFY_CRC 9 +#define CHANGE_BDADDR 15 + +#define HCI_COMMAND_HEADER 7 + +#define HCI_EVENT_SIZE 7 + +#define WRITE_PATCH_COMMAND_STATUS_OFFSET 5 + +#define RAM_PS_REGION (1<<0) +#define RAM_PATCH_REGION (1<<1) +#define RAMPS_MAX_PS_DATA_PER_TAG 20000 +#define MAX_RADIO_CFG_TABLE_SIZE 244 +#define RAMPS_MAX_PS_TAGS_PER_FILE 50 + +#define PS_MAX_LEN 500 +#define LINE_SIZE_MAX (PS_MAX_LEN *2) + +/* Constant values used by parser */ +#define BYTES_OF_PS_DATA_PER_LINE 16 +#define RAMPS_MAX_PS_DATA_PER_TAG 20000 + + +/* Number pf PS/Patch entries in an HCI packet */ +#define MAX_BYTE_LENGTH 244 + +#define SKIP_BLANKS(str) while (*str == ' ') str++ +#define MIN(x, y) (((x) <= (y))? (x):(y)) +#define MAX(x, y) (((x) >= (y))? (x):(y)) + +#define UNUSED(x) (x=x) + +#define IS_BETWEEN(x, lower, upper) (((lower) <= (x)) && ((x) <= (upper))) +#define IS_DIGIT(c) (IS_BETWEEN((c), '0', '9')) +#define IS_HEX(c) (IS_BETWEEN((c), '0', '9') || IS_BETWEEN((c), 'a', 'f') || IS_BETWEEN((c), 'A', 'F')) +#define TO_LOWER(c) (IS_BETWEEN((c), 'A', 'Z') ? ((c) - 'A' + 'a') : (c)) +#define IS_BLANK(c) ((c) == ' ') +#define CONV_DEC_DIGIT_TO_VALUE(c) ((c) - '0') +#define CONV_HEX_DIGIT_TO_VALUE(c) (IS_DIGIT(c) ? ((c) - '0') : (IS_BETWEEN((c), 'A', 'Z') ? ((c) - 'A' + 10) : ((c) - 'a' + 10))) +#define CONV_VALUE_TO_HEX(v) ((A_UINT8)( ((v & 0x0F) <= 9) ? ((v & 0x0F) + '0') : ((v & 0x0F) - 10 + 'A') ) ) + + +enum MinBootFileFormatE +{ + MB_FILEFORMAT_RADIOTBL, + MB_FILEFORMAT_PATCH, + MB_FILEFORMAT_COEXCONFIG +}; + +enum RamPsSection +{ + RAM_PS_SECTION, + RAM_PATCH_SECTION, + RAM_DYN_MEM_SECTION +}; + +enum eType { + eHex, + edecimal +}; + + +typedef struct tPsTagEntry +{ + A_UINT32 TagId; + A_UINT32 TagLen; + A_UINT8 *TagData; +} tPsTagEntry, *tpPsTagEntry; + +typedef struct tRamPatch +{ + A_UINT16 Len; + A_UINT8 * Data; +} tRamPatch, *ptRamPatch; + + + +typedef struct ST_PS_DATA_FORMAT { + enum eType eDataType; + A_BOOL bIsArray; +}ST_PS_DATA_FORMAT; + +typedef struct ST_READ_STATUS { + unsigned uTagID; + unsigned uSection; + unsigned uLineCount; + unsigned uCharCount; + unsigned uByteCount; +}ST_READ_STATUS; + + +/* Stores the number of PS Tags */ +static A_UINT32 Tag_Count = 0; + +/* Stores the number of patch commands */ +static A_UINT32 Patch_Count = 0; +static A_UINT32 Total_tag_lenght = 0; +static A_BOOL BDADDR = FALSE; +A_UINT32 StartTagId; + +tPsTagEntry PsTagEntry[RAMPS_MAX_PS_TAGS_PER_FILE]; +tRamPatch RamPatch[MAX_NUM_PATCH_ENTRY]; + + +A_STATUS AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat); +char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos); +char * AthGetLine(char * buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos); +static A_STATUS AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index); + +/* Function to reads the next character from the input buffer */ +char AthReadChar(A_UCHAR *buffer, A_UINT32 len,A_UINT32 *pos) +{ + char Ch; + if(buffer == NULL || *pos >=len ) + { + return '\0'; + } else { + Ch = buffer[*pos]; + (*pos)++; + return Ch; + } +} +/* PS parser helper function */ +unsigned int uGetInputDataFormat(char* pCharLine, ST_PS_DATA_FORMAT *pstFormat) +{ + if(pCharLine[0] != '[') { + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + return 0; + } + switch(pCharLine[1]) { + case 'H': + case 'h': + if(pCharLine[2]==':') { + if((pCharLine[3]== 'a') || (pCharLine[3]== 'A')) { + if(pCharLine[4] == ']') { + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 5; + return 0; + } + else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A + return 1; + } + } + if((pCharLine[3]== 'S') || (pCharLine[3]== 's')) { + if(pCharLine[4] == ']') { + pstFormat->eDataType = eHex; + pstFormat->bIsArray = false; + pCharLine += 5; + return 0; + } + else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); //[H:A + return 1; + } + } + else if(pCharLine[3] == ']') { //[H:] + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 4; + return 0; + } + else { //[H: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); + return 1; + } + } + else if(pCharLine[2]==']') { //[H] + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 3; + return 0; + } + else { //[H + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format\n")); + return 1; + } + break; + + case 'A': + case 'a': + if(pCharLine[2]==':') { + if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) { + if(pCharLine[4] == ']') { + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 5; + return 0; + } + else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 1\n")); //[A:H + return 1; + } + } + else if(pCharLine[3]== ']') { //[A:] + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 4; + return 0; + } + else { //[A: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 2\n")); + return 1; + } + } + else if(pCharLine[2]==']') { //[H] + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 3; + return 0; + } + else { //[H + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 3\n")); + return 1; + } + break; + + case 'S': + case 's': + if(pCharLine[2]==':') { + if((pCharLine[3]== 'h') || (pCharLine[3]== 'H')) { + if(pCharLine[4] == ']') { + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 5; + return 0; + } + else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 5\n")); //[A:H + return 1; + } + } + else if(pCharLine[3]== ']') { //[A:] + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 4; + return 0; + } + else { //[A: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 6\n")); + return 1; + } + } + else if(pCharLine[2]==']') { //[H] + pstFormat->eDataType = eHex; + pstFormat->bIsArray = true; + pCharLine += 3; + return 0; + } + else { //[H + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 7\n")); + return 1; + } + break; + + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Illegal Data format 8\n")); + return 1; + } +} + +unsigned int uReadDataInSection(char *pCharLine, ST_PS_DATA_FORMAT stPS_DataFormat) +{ + char *pTokenPtr = pCharLine; + + if(pTokenPtr[0] == '[') { + while(pTokenPtr[0] != ']' && pTokenPtr[0] != '\0') { + pTokenPtr++; + } + if(pTokenPtr[0] == '\0') { + return (0x0FFF); + } + pTokenPtr++; + + + } + if(stPS_DataFormat.eDataType == eHex) { + if(stPS_DataFormat.bIsArray == true) { + //Not implemented + return (0x0FFF); + } + else { + return (A_STRTOL(pTokenPtr, NULL, 16)); + } + } + else { + //Not implemented + return (0x0FFF); + } +} +A_STATUS AthParseFilesUnified(A_UCHAR *srcbuffer,A_UINT32 srclen, int FileFormat) +{ + char *Buffer; + char *pCharLine; + A_UINT8 TagCount; + A_UINT16 ByteCount; + A_UINT8 ParseSection=RAM_PS_SECTION; + A_UINT32 pos; + + + + int uReadCount; + ST_PS_DATA_FORMAT stPS_DataFormat; + ST_READ_STATUS stReadStatus = {0, 0, 0,0}; + pos = 0; + Buffer = NULL; + + if (srcbuffer == NULL || srclen == 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Could not open .\n")); + return A_ERROR; + } + TagCount = 0; + ByteCount = 0; + Buffer = A_MALLOC(LINE_SIZE_MAX + 1); + if(NULL == Buffer) { + return A_ERROR; + } + if (FileFormat == MB_FILEFORMAT_PATCH) + { + int LineRead = 0; + while((pCharLine = AthGetLine(Buffer, LINE_SIZE_MAX, srcbuffer,srclen,&pos)) != NULL) + { + + SKIP_BLANKS(pCharLine); + + // Comment line or empty line + if ((pCharLine[0] == '/') && (pCharLine[1] == '/')) + { + continue; + } + + if ((pCharLine[0] == '#')) { + if (stReadStatus.uSection != 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("error\n")); + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_ERROR; + } + else { + stReadStatus.uSection = 1; + continue; + } + } + if ((pCharLine[0] == '/') && (pCharLine[1] == '*')) + { + pCharLine+=2; + SKIP_BLANKS(pCharLine); + + if(!strncmp(pCharLine,"PA",2)||!strncmp(pCharLine,"Pa",2)||!strncmp(pCharLine,"pa",2)) + ParseSection=RAM_PATCH_SECTION; + + if(!strncmp(pCharLine,"DY",2)||!strncmp(pCharLine,"Dy",2)||!strncmp(pCharLine,"dy",2)) + ParseSection=RAM_DYN_MEM_SECTION; + + if(!strncmp(pCharLine,"PS",2)||!strncmp(pCharLine,"Ps",2)||!strncmp(pCharLine,"ps",2)) + ParseSection=RAM_PS_SECTION; + + LineRead = 0; + stReadStatus.uSection = 0; + + continue; + } + + switch(ParseSection) + { + case RAM_PS_SECTION: + { + if (stReadStatus.uSection == 1) //TagID + { + SKIP_BLANKS(pCharLine); + if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail\n")); + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_ERROR; + } + //pCharLine +=5; + PsTagEntry[TagCount].TagId = uReadDataInSection(pCharLine, stPS_DataFormat); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG ID %d \n",PsTagEntry[TagCount].TagId)); + + //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag # %x\n", PsTagEntry[TagCount].TagId); + if (TagCount == 0) + { + StartTagId = PsTagEntry[TagCount].TagId; + } + stReadStatus.uSection = 2; + } + else if (stReadStatus.uSection == 2) //TagLength + { + + if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail \n")); + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_ERROR; + } + //pCharLine +=5; + ByteCount = uReadDataInSection(pCharLine, stPS_DataFormat); + + //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("tag length %x\n", ByteCount)); + if (ByteCount > LINE_SIZE_MAX/2) + { + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_ERROR; + } + PsTagEntry[TagCount].TagLen = ByteCount; + PsTagEntry[TagCount].TagData = (A_UINT8*)A_MALLOC(ByteCount); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" TAG Length %d Tag Index %d \n",PsTagEntry[TagCount].TagLen,TagCount)); + stReadStatus.uSection = 3; + stReadStatus.uLineCount = 0; + } + else if( stReadStatus.uSection == 3) { //Data + + if(stReadStatus.uLineCount == 0) { + if(uGetInputDataFormat(pCharLine,&stPS_DataFormat)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat Fail\n")); + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_ERROR; + } + //pCharLine +=5; + } + SKIP_BLANKS(pCharLine); + stReadStatus.uCharCount = 0; + if(pCharLine[stReadStatus.uCharCount] == '[') { + while(pCharLine[stReadStatus.uCharCount] != ']' && pCharLine[stReadStatus.uCharCount] != '\0' ) { + stReadStatus.uCharCount++; + } + if(pCharLine[stReadStatus.uCharCount] == ']' ) { + stReadStatus.uCharCount++; + } else { + stReadStatus.uCharCount = 0; + } + } + uReadCount = (ByteCount > BYTES_OF_PS_DATA_PER_LINE)? BYTES_OF_PS_DATA_PER_LINE: ByteCount; + //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ")); + if((stPS_DataFormat.eDataType == eHex) && stPS_DataFormat.bIsArray == true) { + while(uReadCount > 0) { + PsTagEntry[TagCount].TagData[stReadStatus.uByteCount] = + (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount]) << 4) + | (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 1])); + + PsTagEntry[TagCount].TagData[stReadStatus.uByteCount+1] = + (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 3]) << 4) + | (A_UINT8)(CONV_HEX_DIGIT_TO_VALUE(pCharLine[stReadStatus.uCharCount + 4])); + + stReadStatus.uCharCount += 6; // read two bytes, plus a space; + stReadStatus.uByteCount += 2; + uReadCount -= 2; + } + if(ByteCount > BYTES_OF_PS_DATA_PER_LINE) { + ByteCount -= BYTES_OF_PS_DATA_PER_LINE; + } + else { + ByteCount = 0; + } + } + else { + //to be implemented + } + + stReadStatus.uLineCount++; + + if(ByteCount == 0) { + stReadStatus.uSection = 0; + stReadStatus.uCharCount = 0; + stReadStatus.uLineCount = 0; + stReadStatus.uByteCount = 0; + } + else { + stReadStatus.uCharCount = 0; + } + + if((stReadStatus.uSection == 0)&&(++TagCount == RAMPS_MAX_PS_TAGS_PER_FILE)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n Buffer over flow PS File too big!!!")); + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_ERROR; + //Sleep (3000); + //exit(1); + } + + } + } + + break; + default: + { + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_ERROR; + } + break; + } + LineRead++; + } + Tag_Count = TagCount; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Number of Tags %d\n", Tag_Count)); + } + + + if (TagCount > RAMPS_MAX_PS_TAGS_PER_FILE) + { + + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_ERROR; + } + + if(Buffer != NULL) { + A_FREE(Buffer); + } + return A_OK; + +} + + + +/********************/ + + +A_STATUS GetNextTwoChar(A_UCHAR *srcbuffer,A_UINT32 len, A_UINT32 *pos, char * buffer) +{ + unsigned char ch; + + ch = AthReadChar(srcbuffer,len,pos); + if(ch != '\0' && IS_HEX(ch)) { + buffer[0] = ch; + } else + { + return A_ERROR; + } + ch = AthReadChar(srcbuffer,len,pos); + if(ch != '\0' && IS_HEX(ch)) { + buffer[1] = ch; + } else + { + return A_ERROR; + } + return A_OK; +} + +A_STATUS AthDoParsePatch(A_UCHAR *patchbuffer, A_UINT32 patchlen) +{ + + char Byte[3]; + char Line[MAX_BYTE_LENGTH + 1]; + int ByteCount,ByteCount_Org; + int count; + int i,j,k; + int data; + A_UINT32 filepos; + Byte[2] = '\0'; + j = 0; + filepos = 0; + + while(NULL != AthGetLine(Line,MAX_BYTE_LENGTH,patchbuffer,patchlen,&filepos)) { + if(strlen(Line) <= 1 || !IS_HEX(Line[0])) { + continue; + } else { + break; + } + } + ByteCount = A_STRTOL(Line, NULL, 16); + ByteCount_Org = ByteCount; + + while(ByteCount > MAX_BYTE_LENGTH){ + + /* Handle case when the number of patch buffer is more than the 20K */ + if(MAX_NUM_PATCH_ENTRY == Patch_Count) { + for(i = 0; i < Patch_Count; i++) { + A_FREE(RamPatch[i].Data); + } + return A_ERROR; + } + RamPatch[Patch_Count].Len= MAX_BYTE_LENGTH; + RamPatch[Patch_Count].Data = (A_UINT8*)A_MALLOC(MAX_BYTE_LENGTH); + Patch_Count ++; + + + ByteCount= ByteCount - MAX_BYTE_LENGTH; + } + + RamPatch[Patch_Count].Len= (ByteCount & 0xFF); + if(ByteCount != 0) { + RamPatch[Patch_Count].Data = (A_UINT8*)A_MALLOC(ByteCount); + Patch_Count ++; + } + count = 0; + while(ByteCount_Org > MAX_BYTE_LENGTH){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j)); + for (i = 0,k=0; i < MAX_BYTE_LENGTH*2; i += 2,k++,count +=2) { + if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) { + return A_ERROR; + } + data = A_STRTOUL(&Byte[0], NULL, 16); + RamPatch[j].Data[k] = (data & 0xFF); + + + } + j++; + ByteCount_Org = ByteCount_Org - MAX_BYTE_LENGTH; + } + if(j == 0){ + j++; + } + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Index [%d]\n",j)); + for (k=0; k < ByteCount_Org; i += 2,k++,count+=2) { + if(GetNextTwoChar(patchbuffer,patchlen,&filepos,Byte) == A_ERROR) { + return A_ERROR; + } + data = A_STRTOUL(Byte, NULL, 16); + RamPatch[j].Data[k] = (data & 0xFF); + + + } + return A_OK; +} + + +/********************/ +A_STATUS AthDoParsePS(A_UCHAR *srcbuffer, A_UINT32 srclen) +{ + A_STATUS status; + int i; + A_BOOL BDADDR_Present = A_ERROR; + + + + status = A_ERROR; + + if(NULL != srcbuffer && srclen != 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("File Open Operation Successful\n")); + + status = AthParseFilesUnified(srcbuffer,srclen,MB_FILEFORMAT_PATCH); + } + + + + if(Tag_Count == 0){ + Total_tag_lenght = 10; + + } + else{ + for(i=0; i 0 && !BDADDR_Present){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR is not present adding 10 extra bytes \r\n")); + Total_tag_lenght=Total_tag_lenght + 10; + } + Total_tag_lenght = Total_tag_lenght+ 10 + (Tag_Count*4); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("** Total Length %d\n",Total_tag_lenght)); + + + return status; +} +char * AthGetLine(char * buffer, int maxlen, A_UCHAR *srcbuffer,A_UINT32 len,A_UINT32 *pos) +{ + + int count; + static short flag; + char CharRead; + count = 0; + flag = A_ERROR; + + do + { + CharRead = AthReadChar(srcbuffer,len,pos); + if( CharRead == '\0' ) { + buffer[count+1] = '\0'; + if(count == 0) { + return NULL; + } + else { + return buffer; + } + } + + if(CharRead == 13) { + } else if(CharRead == 10) { + buffer[count] ='\0'; + flag = A_ERROR; + return buffer; + }else { + buffer[count++] = CharRead; + } + + } + while(count < maxlen-1 && CharRead != '\0'); + buffer[count] = '\0'; + + return buffer; +} + +static void LoadHeader(A_UCHAR *HCI_PS_Command,A_UCHAR opcode,int length,int index){ + + HCI_PS_Command[0]= 0x0B; + HCI_PS_Command[1]= 0xFC; + HCI_PS_Command[2]= length + 4; + HCI_PS_Command[3]= opcode; + HCI_PS_Command[4]= (index & 0xFF); + HCI_PS_Command[5]= ((index>>8) & 0xFF); + HCI_PS_Command[6]= length; +} + +///////////////////////// +// +int AthCreateCommandList(PSCmdPacket **HciPacketList, A_UINT32 *numPackets) +{ + + A_UINT8 count; + A_UINT32 NumcmdEntry = 0; + + A_UINT32 Crc = 0; + *numPackets = 0; + + + if(Patch_Count > 0) + Crc |= RAM_PATCH_REGION; + if(Tag_Count > 0) + Crc |= RAM_PS_REGION; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("PS Thread Started CRC %x Patch Count %d Tag Count %d \n",Crc,Patch_Count,Tag_Count)); + + if(Patch_Count || Tag_Count ){ + NumcmdEntry+=(2 + Patch_Count + Tag_Count); /* CRC Packet + PS Reset Packet + Patch List + PS List*/ + if(Patch_Count > 0) { + NumcmdEntry++; /* Patch Enable Command */ + } + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Num Cmd Entries %d Size %d \r\n",NumcmdEntry,sizeof(PSCmdPacket) * NumcmdEntry)); + (*HciPacketList) = A_MALLOC(sizeof(PSCmdPacket) * NumcmdEntry); + if(NULL == *HciPacketList) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("memory allocation failed \r\n")); + } + AthPSCreateHCICommand(PS_VERIFY_CRC,Crc,*HciPacketList,numPackets); + if(Patch_Count > 0){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Write Patch**** \r\n")); + AthPSCreateHCICommand(WRITE_PATCH,Patch_Count,*HciPacketList,numPackets); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** Enable Patch**** \r\n")); + AthPSCreateHCICommand(ENABLE_PATCH,0,*HciPacketList,numPackets); + } + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Reset**** \r\n")); + AthPSCreateHCICommand(PS_RESET,Total_tag_lenght,*HciPacketList,numPackets); + if(Tag_Count > 0){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("*** PS Write**** \r\n")); + AthPSCreateHCICommand(PS_WRITE,Tag_Count,*HciPacketList,numPackets); + } + } + if(!BDADDR){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BD ADDR not present \r\n")); + + } + for(count = 0; count < Patch_Count; count++) { + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing Patch Buffer %d \r\n",count)); + A_FREE(RamPatch[Patch_Count].Data); + } + + for(count = 0; count < Tag_Count; count++) { + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing PS Buffer %d \r\n",count)); + A_FREE(PsTagEntry[count].TagData); + } + +/* + * SDIO Transport uses synchronous mode of data transfer + * So, AthPSOperations() call returns only after receiving the + * command complete event. + */ + return *numPackets; +} + + +//////////////////////// + +///////////// +static A_STATUS AthPSCreateHCICommand(A_UCHAR Opcode, A_UINT32 Param1,PSCmdPacket *PSPatchPacket,A_UINT32 *index) +{ + A_UCHAR *HCI_PS_Command; + A_UINT32 Length; + int i,j; + + switch(Opcode) + { + case WRITE_PATCH: + + + for(i=0;i< Param1;i++){ + + HCI_PS_Command = (A_UCHAR *) A_MALLOC(RamPatch[i].Len+HCI_COMMAND_HEADER); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Allocated Buffer Size %d\n",RamPatch[i].Len+HCI_COMMAND_HEADER)); + if(HCI_PS_Command == NULL){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n")); + return A_ERROR; + } + memset (HCI_PS_Command, 0, RamPatch[i].Len+HCI_COMMAND_HEADER); + LoadHeader(HCI_PS_Command,Opcode,RamPatch[i].Len,i); + for(j=0;j> 8) & 0xFF); + PSPatchPacket[*index].Hcipacket = HCI_PS_Command; + PSPatchPacket[*index].packetLen = Length+HCI_COMMAND_HEADER; + (*index)++; + + break; + + case PS_WRITE: + for(i=0;i< Param1;i++){ + if(PsTagEntry[i].TagId ==1) + BDADDR = TRUE; + + HCI_PS_Command = (A_UCHAR *) A_MALLOC(PsTagEntry[i].TagLen+HCI_COMMAND_HEADER); + if(HCI_PS_Command == NULL){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("MALLOC Failed\r\n")); + return A_ERROR; + } + + memset (HCI_PS_Command, 0, PsTagEntry[i].TagLen+HCI_COMMAND_HEADER); + LoadHeader(HCI_PS_Command,Opcode,PsTagEntry[i].TagLen,PsTagEntry[i].TagId); + + for(j=0;j + * Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + *------------------------------------------------------------------------------ + * + * + * + * This file is the include file for Atheros PS and patch parser. + * It implements APIs to parse data buffer with patch and PS information and convert it to HCI commands. + * + * + * + * + * + */ +#ifndef __AR3KPSPARSER_H +#define __AR3KPSPARSER_H + + + + +#include +#include +#include "athdefs.h" +#ifdef HCI_TRANSPORT_SDIO +#include "a_config.h" +#include "a_types.h" +#include "a_osapi.h" +#define ATH_MODULE_NAME misc +#include "a_debug.h" +#include "common_drv.h" +#include "hci_transport_api.h" +#include "ar3kconfig.h" +#else +#ifndef A_PRINTF +#define A_PRINTF(args...) printk(KERN_ALERT args) +#endif /* A_PRINTF */ +#include "debug_linux.h" + +/* Helper data type declaration */ + +#ifndef A_UINT32 +#define A_UCHAR unsigned char +#define A_UINT32 unsigned long +#define A_UINT16 unsigned short +#define A_UINT8 unsigned char +#define A_BOOL unsigned char +#endif /* A_UINT32 */ + +#define ATH_DEBUG_ERR (1 << 0) +#define ATH_DEBUG_WARN (1 << 1) +#define ATH_DEBUG_INFO (1 << 2) + + + +#define FALSE 0 +#define TRUE 1 + +#ifndef A_MALLOC +#define A_MALLOC(size) kmalloc((size),GFP_KERNEL) +#endif /* A_MALLOC */ + + +#ifndef A_FREE +#define A_FREE(addr) kfree((addr)) +#endif /* A_MALLOC */ +#endif /* HCI_TRANSPORT_UART */ + +/* String manipulation APIs */ +#ifndef A_STRTOUL +#define A_STRTOUL simple_strtoul +#endif /* A_STRTOL */ + +#ifndef A_STRTOL +#define A_STRTOL simple_strtol +#endif /* A_STRTOL */ + + +/* The maximum number of bytes possible in a patch entry */ +#define MAX_PATCH_SIZE 20000 + +/* Maximum HCI packets that will be formed from the Patch file */ +#define MAX_NUM_PATCH_ENTRY (MAX_PATCH_SIZE/MAX_BYTE_LENGTH) + 1 + + + + + + + +typedef struct PSCmdPacket +{ + A_UCHAR *Hcipacket; + int packetLen; +} PSCmdPacket; + +/* Parses a Patch information buffer and store it in global structure */ +A_STATUS AthDoParsePatch(A_UCHAR *, A_UINT32); + +/* parses a PS information buffer and stores it in a global structure */ +A_STATUS AthDoParsePS(A_UCHAR *, A_UINT32); + +/* + * Uses the output of Both AthDoParsePS and AthDoParsePatch APIs to form HCI command array with + * all the PS and patch commands. + * The list will have the below mentioned commands in order. + * CRC command packet + * Download patch command(s) + * Enable patch Command + * PS Reset Command + * PS Tag Command(s) + * + */ +int AthCreateCommandList(PSCmdPacket **, A_UINT32 *); + +/* Cleanup the dynamically allicated HCI command list */ +A_STATUS AthFreeCommandList(PSCmdPacket **HciPacketList, A_UINT32 numPackets); +#endif /* __AR3KPSPARSER_H */ diff --git a/drivers/net/wireless/ath6kl/miscdrv/common_drv.c b/drivers/net/wireless/ath6kl/miscdrv/common_drv.c new file mode 100644 index 000000000000..0a318c3c8de4 --- /dev/null +++ b/drivers/net/wireless/ath6kl/miscdrv/common_drv.c @@ -0,0 +1,973 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" + +#include "AR6002/hw/mbox_host_reg.h" +#include "AR6002/hw/apb_map.h" +#include "AR6002/hw/si_reg.h" +#include "AR6002/hw/gpio_reg.h" +#include "AR6002/hw/rtc_reg.h" +#include "AR6002/hw/vmc_reg.h" +#include "AR6002/hw/mbox_reg.h" + +#include "targaddrs.h" +#include "a_osapi.h" +#include "hif.h" +#include "htc_api.h" +#include "wmi.h" +#include "bmi.h" +#include "bmi_msg.h" +#include "common_drv.h" +#define ATH_MODULE_NAME misc +#include "a_debug.h" +#include "ar6000_diag.h" + +static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL; +static A_MUTEX_T g_ModuleListLock; +static A_BOOL g_ModuleDebugInit = FALSE; + +#ifdef DEBUG + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc, + "misc", + "Common and misc APIs", + ATH_DEBUG_MASK_DEFAULTS, + 0, + NULL); + +#endif + +#define HOST_INTEREST_ITEM_ADDRESS(target, item) \ + (((target) == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))) + + +#define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080 +#define AR6002_LOCAL_COUNT_ADDRESS 0x00018080 +#define AR6003_LOCAL_COUNT_ADDRESS 0x00018080 +#define CPU_DBG_SEL_ADDRESS 0x00000483 +#define CPU_DBG_ADDRESS 0x00000484 + +/* Compile the 4BYTE version of the window register setup routine, + * This mitigates host interconnect issues with non-4byte aligned bus requests, some + * interconnects use bus adapters that impose strict limitations. + * Since diag window access is not intended for performance critical operations, the 4byte mode should + * be satisfactory even though it generates 4X the bus activity. */ + +#ifdef USE_4BYTE_REGISTER_ACCESS + + /* set the window address register (using 4-byte register access ). */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + A_UINT8 addrValue[4]; + A_INT32 i; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + + for (i = 1; i <= 3; i++) { + /* fill the buffer with the address byte value we want to hit 4 times*/ + addrValue[0] = ((A_UINT8 *)&Address)[i]; + addrValue[1] = addrValue[0]; + addrValue[2] = addrValue[0]; + addrValue[3] = addrValue[0]; + + /* hit each byte of the register address with a 4-byte write operation to the same address, + * this is a harmless operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr+i, + addrValue, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + if (status != A_OK) { + break; + } + } + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + Address, RegisterAddr)); + return status; + } + + /* write the address register again, this time write the whole 4-byte value. + * The effect here is that the LSB write causes the cycle to start, the extra + * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + 4, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + Address, RegisterAddr)); + return status; + } + + return A_OK; + + + +} + + +#else + + /* set the window address register */ +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address) +{ + A_STATUS status; + + /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written + * last to initiate the access cycle */ + status = HIFReadWrite(hifDevice, + RegisterAddr+1, /* write upper 3 bytes */ + ((A_UCHAR *)(&Address))+1, + sizeof(A_UINT32)-1, + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + /* write the LSB of the register, this initiates the operation */ + status = HIFReadWrite(hifDevice, + RegisterAddr, + (A_UCHAR *)(&Address), + sizeof(A_UINT8), + HIF_WR_SYNC_BYTE_INC, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n", + RegisterAddr, Address)); + return status; + } + + return A_OK; +} + +#endif + +/* + * Read from the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set window register to start read cycle */ + status = ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_READ_ADDR_ADDRESS, + *address); + + if (status != A_OK) { + return status; + } + + /* read the data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_RD_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n")); + return status; + } + + return status; +} + + +/* + * Write to the AR6000 through its diagnostic window. + * No cooperation from the Target is required for this. + */ +A_STATUS +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data) +{ + A_STATUS status; + + /* set write data */ + status = HIFReadWrite(hifDevice, + WINDOW_DATA_ADDRESS, + (A_UCHAR *)data, + sizeof(A_UINT32), + HIF_WR_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data)); + return status; + } + + /* set window register, which starts the write cycle */ + return ar6000_SetAddressWindowRegister(hifDevice, + WINDOW_WRITE_ADDR_ADDRESS, + *address); + } + +A_STATUS +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_ReadRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +A_STATUS +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, + A_UCHAR *data, A_UINT32 length) +{ + A_UINT32 count; + A_STATUS status = A_OK; + + for (count = 0; count < length; count += 4, address += 4) { + if ((status = ar6000_WriteRegDiag(hifDevice, &address, + (A_UINT32 *)&data[count])) != A_OK) + { + break; + } + } + + return status; +} + +A_STATUS +ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval) +{ + A_STATUS status; + A_UCHAR vals[4]; + A_UCHAR register_selection[4]; + + register_selection[0] = register_selection[1] = register_selection[2] = register_selection[3] = (regsel & 0xff); + status = HIFReadWrite(hifDevice, + CPU_DBG_SEL_ADDRESS, + register_selection, + 4, + HIF_WR_SYNC_BYTE_FIX, + NULL); + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write CPU_DBG_SEL (%d)\n", regsel)); + return status; + } + + status = HIFReadWrite(hifDevice, + CPU_DBG_ADDRESS, + (A_UCHAR *)vals, + sizeof(vals), + HIF_RD_SYNC_BYTE_INC, + NULL); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from CPU_DBG_ADDRESS\n")); + return status; + } + + *regval = vals[0]<<0 | vals[1]<<8 | vals[2]<<16 | vals[3]<<24; + + return status; +} + +void +ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs) +{ + int i; + A_UINT32 val; + + for (i=0; i REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6001 too large" +#endif +#if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6002 too large" +#endif +#if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX +#error "REG_DUMP_COUNT_AR6003 too large" +#endif + + +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType) +{ + A_UINT32 address; + A_UINT32 regDumpArea = 0; + A_STATUS status; + A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX]; + A_UINT32 regDumpCount = 0; + A_UINT32 i; + + do { + + /* the reg dump pointer is copied to the host interest area */ + address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state); + address = TARG_VTOP(TargetType, address); + + if (TargetType == TARGET_TYPE_AR6001) { + /* for AR6001, this is a fixed location because the ptr is actually stuck in cache, + * this may be fixed in later firmware versions */ + address = 0x18a0; + regDumpCount = REG_DUMP_COUNT_AR6001; + } else if (TargetType == TARGET_TYPE_AR6002) { + regDumpCount = REG_DUMP_COUNT_AR6002; + } else if (TargetType == TARGET_TYPE_AR6003) { + regDumpCount = REG_DUMP_COUNT_AR6003; + } else { + A_ASSERT(0); + } + + /* read RAM location through diagnostic window */ + status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea)); + + if (regDumpArea == 0) { + /* no reg dump */ + break; + } + + regDumpArea = TARG_VTOP(TargetType, regDumpArea); + + /* fetch register dump data */ + status = ar6000_ReadDataDiag(hifDevice, + regDumpArea, + (A_UCHAR *)®DumpValues[0], + regDumpCount * (sizeof(A_UINT32))); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n")); + break; + } + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n")); + + for (i = 0; i < regDumpCount; i++) { + //ATHR_DISPLAY_MSG (_T(" %d : 0x%8.8X \n"), i, regDumpValues[i]); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d : 0x%8.8X \n",i, regDumpValues[i])); + +#ifdef UNDER_CE + /* + * For Every logPrintf() Open the File so that in case of Crashes + * We will have until the Last Message Flushed on to the File + * So use logPrintf Sparingly..!! + */ + tgtassertPrintf (ATH_DEBUG_TRC," %d: 0x%8.8X \n",i, regDumpValues[i]); +#endif + } + + } while (FALSE); + +} + +/* set HTC/Mbox operational parameters, this can only be called when the target is in the + * BMI phase */ +A_STATUS ar6000_set_htc_params(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 MboxIsrYieldValue, + A_UINT8 HtcControlBuffers) +{ + A_STATUS status; + A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX]; + + do { + /* get the block sizes */ + status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE, + blocksizes, sizeof(blocksizes)); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n")); + break; + } + /* note: we actually get the block size for mailbox 1, for SDIO the block + * size on mailbox 0 is artificially set to 1 */ + /* must be a power of 2 */ + A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0); + + if (HtcControlBuffers != 0) { + /* set override for number of control buffers to use */ + blocksizes[1] |= ((A_UINT32)HtcControlBuffers) << 16; + } + + /* set the host interest area for the block size */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz), + (A_UCHAR *)&blocksizes[1], + 4); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n")); + break; + } + + AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n", + blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz))); + + if (MboxIsrYieldValue != 0) { + /* set the host interest area for the mbox ISR yield limit */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit), + (A_UCHAR *)&MboxIsrYieldValue, + 4); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n")); + break; + } + } + + } while (FALSE); + + return status; +} + + +static A_STATUS prepare_ar6002(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion) +{ + A_STATUS status = A_OK; + + /* placeholder */ + + return status; +} + +static A_STATUS prepare_ar6003(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion) +{ + A_STATUS status = A_OK; + + /* placeholder */ + + return status; +} + +/* this function assumes the caller has already initialized the BMI APIs */ +A_STATUS ar6000_prepare_target(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 TargetVersion) +{ + if (TargetType == TARGET_TYPE_AR6002) { + /* do any preparations for AR6002 devices */ + return prepare_ar6002(hifDevice,TargetVersion); + } else if (TargetType == TARGET_TYPE_AR6003) { + return prepare_ar6003(hifDevice,TargetVersion); + } + + return A_OK; +} + +#if defined(CONFIG_AR6002_REV1_FORCE_HOST) +/* + * Call this function just before the call to BMIInit + * in order to force* AR6002 rev 1.x firmware to detect a Host. + * THIS IS FOR USE ONLY WITH AR6002 REV 1.x. + * TBDXXX: Remove this function when REV 1.x is desupported. + */ +A_STATUS +ar6002_REV1_reset_force_host (HIF_DEVICE *hifDevice) +{ + A_INT32 i; + struct forceROM_s { + A_UINT32 addr; + A_UINT32 data; + }; + struct forceROM_s *ForceROM; + A_INT32 szForceROM; + A_STATUS status = A_OK; + A_UINT32 address; + A_UINT32 data; + + /* Force AR6002 REV1.x to recognize Host presence. + * + * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0 + * so that this workaround functions with AR6002.war1.sh. We + * could fold that entire workaround into this one, but it's not + * worth the effort at this point. This workaround cannot be + * merged into the other workaround because this must be done + * before BMI. + */ + + static struct forceROM_s ForceROM_NEW[] = { + {0x52df80, 0x20f31c07}, + {0x52df84, 0x92374420}, + {0x52df88, 0x1d120c03}, + {0x52df8c, 0xff8216f0}, + {0x52df90, 0xf01d120c}, + {0x52df94, 0x81004136}, + {0x52df98, 0xbc9100bd}, + {0x52df9c, 0x00bba100}, + + {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */ + {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380}, + {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000}, + {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001}, + + {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */ + + {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK}, + }; + + address = 0x004ed4b0; /* REV1 target software ID is stored here */ + status = ar6000_ReadRegDiag(hifDevice, &address, &data); + if (A_FAILED(status) || (data != AR6002_VERSION_REV1)) { + return A_ERROR; /* Not AR6002 REV1 */ + } + + ForceROM = ForceROM_NEW; + szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM); + + ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n")); + for (i = 0; i < szForceROM; i++) + { + if (ar6000_WriteRegDiag(hifDevice, + &ForceROM[i].addr, + &ForceROM[i].data) != A_OK) + { + ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n")); + return A_ERROR; + } + } + + A_MDELAY(1000); + + return A_OK; +} + +#endif /* CONFIG_AR6002_REV1_FORCE_HOST */ + +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription) +{ + A_CHAR stream[60]; + A_CHAR byteOffsetStr[10]; + A_UINT32 i; + A_UINT16 offset, count, byteOffset; + + A_PRINTF("<---------Dumping %d Bytes : %s ------>\n", length, pDescription); + + count = 0; + offset = 0; + byteOffset = 0; + for(i = 0; i < length; i++) { + A_SPRINTF(stream + offset, "%2.2X ", buffer[i]); + count ++; + offset += 3; + + if(count == 16) { + count = 0; + offset = 0; + A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset); + A_PRINTF("[%s]: %s\n", byteOffsetStr, stream); + A_MEMZERO(stream, 60); + byteOffset += 16; + } + } + + if(offset != 0) { + A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset); + A_PRINTF("[%s]: %s\n", byteOffsetStr, stream); + } + + A_PRINTF("<------------------------------------------------->\n"); +} + +void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo) +{ + int i; + ATH_DEBUG_MASK_DESCRIPTION *pDesc; + + if (pInfo == NULL) { + return; + } + + pDesc = pInfo->pMaskDescriptions; + + A_PRINTF("========================================================\n\n"); + A_PRINTF("Module Debug Info => Name : %s \n", pInfo->ModuleName); + A_PRINTF(" => Descr. : %s \n", pInfo->ModuleDescription); + A_PRINTF("\n Current mask => 0x%8.8X \n", pInfo->CurrentMask); + A_PRINTF("\n Avail. Debug Masks :\n\n"); + + for (i = 0; i < pInfo->MaxDescriptions; i++,pDesc++) { + A_PRINTF(" => 0x%8.8X -- %s \n", pDesc->Mask, pDesc->Description); + } + + if (0 == i) { + A_PRINTF(" => * none defined * \n"); + } + + A_PRINTF("\n Standard Debug Masks :\n\n"); + /* print standard masks */ + A_PRINTF(" => 0x%8.8X -- Errors \n", ATH_DEBUG_ERR); + A_PRINTF(" => 0x%8.8X -- Warnings \n", ATH_DEBUG_WARN); + A_PRINTF(" => 0x%8.8X -- Informational \n", ATH_DEBUG_INFO); + A_PRINTF(" => 0x%8.8X -- Tracing \n", ATH_DEBUG_TRC); + A_PRINTF("\n========================================================\n"); + +} + + +static ATH_DEBUG_MODULE_DBG_INFO *FindModule(A_CHAR *module_name) +{ + ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead; + + if (!g_ModuleDebugInit) { + return NULL; + } + + while (pInfo != NULL) { + /* TODO: need to use something other than strlen */ + if (A_MEMCMP(pInfo->ModuleName,module_name,strlen(module_name)) == 0) { + break; + } + pInfo = pInfo->pNext; + } + + return pInfo; +} + + +void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo) +{ + if (!g_ModuleDebugInit) { + return; + } + + A_MUTEX_LOCK(&g_ModuleListLock); + + if (!(pInfo->Flags & ATH_DEBUG_INFO_FLAGS_REGISTERED)) { + if (g_pModuleInfoHead == NULL) { + g_pModuleInfoHead = pInfo; + } else { + pInfo->pNext = g_pModuleInfoHead; + g_pModuleInfoHead = pInfo; + } + pInfo->Flags |= ATH_DEBUG_INFO_FLAGS_REGISTERED; + } + + A_MUTEX_UNLOCK(&g_ModuleListLock); +} + +void a_dump_module_debug_info_by_name(A_CHAR *module_name) +{ + ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead; + + if (!g_ModuleDebugInit) { + return; + } + + if (A_MEMCMP(module_name,"all",3) == 0) { + /* dump all */ + while (pInfo != NULL) { + a_dump_module_debug_info(pInfo); + pInfo = pInfo->pNext; + } + return; + } + + pInfo = FindModule(module_name); + + if (pInfo != NULL) { + a_dump_module_debug_info(pInfo); + } + +} + +A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask) +{ + ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name); + + if (NULL == pInfo) { + return A_ERROR; + } + + *pMask = pInfo->CurrentMask; + return A_OK; +} + +A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask) +{ + ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name); + + if (NULL == pInfo) { + return A_ERROR; + } + + pInfo->CurrentMask = Mask; + A_PRINTF("Module %s, new mask: 0x%8.8X \n",module_name,pInfo->CurrentMask); + return A_OK; +} + + +void a_module_debug_support_init(void) +{ + if (g_ModuleDebugInit) { + return; + } + A_MUTEX_INIT(&g_ModuleListLock); + g_pModuleInfoHead = NULL; + g_ModuleDebugInit = TRUE; + A_REGISTER_MODULE_DEBUG_INFO(misc); +} + +void a_module_debug_support_cleanup(void) +{ + ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead; + ATH_DEBUG_MODULE_DBG_INFO *pCur; + + if (!g_ModuleDebugInit) { + return; + } + + g_ModuleDebugInit = FALSE; + + A_MUTEX_LOCK(&g_ModuleListLock); + + while (pInfo != NULL) { + pCur = pInfo; + pInfo = pInfo->pNext; + pCur->pNext = NULL; + /* clear registered flag */ + pCur->Flags &= ~ATH_DEBUG_INFO_FLAGS_REGISTERED; + } + + A_MUTEX_UNLOCK(&g_ModuleListLock); + + A_MUTEX_DELETE(&g_ModuleListLock); + g_pModuleInfoHead = NULL; +} + + /* can only be called during bmi init stage */ +A_STATUS ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice, + A_UINT32 TargetType, + A_UINT32 Flags) +{ + A_STATUS status = A_OK; + + do { + + if (TargetType != TARGET_TYPE_AR6003) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Target Type:%d, does not support HCI bridging! \n", + TargetType)); + break; + } + + /* set hci bridge flags */ + status = BMIWriteMemory(hifDevice, + HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_bridge_flags), + (A_UCHAR *)&Flags, + 4); + + + } while (FALSE); + + return status; +} + diff --git a/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c b/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c new file mode 100644 index 000000000000..74426b8f710a --- /dev/null +++ b/drivers/net/wireless/ath6kl/miscdrv/credit_dist.c @@ -0,0 +1,375 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#define ATH_MODULE_NAME misc +#include "a_debug.h" +#include "htc_api.h" +#include "common_drv.h" + +/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/ + +#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */ + +#ifdef NO_VO_SERVICE +#define DATA_SVCS_USED 3 +#else +#define DATA_SVCS_USED 4 +#endif + +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList); + +/* reduce an ep's credits back to a set limit */ +static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEpDist, + int Limit) +{ + int credits; + + /* set the new limit */ + pEpDist->TxCreditsAssigned = Limit; + + if (pEpDist->TxCredits <= Limit) { + return; + } + + /* figure out how much to take away */ + credits = pEpDist->TxCredits - Limit; + /* take them away */ + pEpDist->TxCredits -= credits; + pCredInfo->CurrentFreeCredits += credits; +} + +/* give an endpoint some credits from the free credit pool */ +#define GiveCredits(pCredInfo,pEpDist,credits) \ +{ \ + (pEpDist)->TxCredits += (credits); \ + (pEpDist)->TxCreditsAssigned += (credits); \ + (pCredInfo)->CurrentFreeCredits -= (credits); \ +} + + +/* default credit init callback. + * This function is called in the context of HTCStart() to setup initial (application-specific) + * credit distributions */ +static void ar6000_credit_init(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPList, + int TotalCredits) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int count; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + pCredInfo->CurrentFreeCredits = TotalCredits; + pCredInfo->TotalAvailableCredits = TotalCredits; + + pCurEpDist = pEPList; + + /* run through the list and initialize */ + while (pCurEpDist != NULL) { + + /* set minimums for each endpoint */ + pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg; + + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* give control service some credits */ + GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin); + /* control service is always marked active, it never goes inactive EVER */ + SET_EP_ACTIVE(pCurEpDist); + } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) { + /* this is the lowest priority data endpoint, save this off for easy access */ + pCredInfo->pLowestPriEpDist = pCurEpDist; + } + + /* Streams have to be created (explicit | implicit)for all kinds + * of traffic. BE endpoints are also inactive in the beginning. + * When BE traffic starts it creates implicit streams that + * redistributes credits. + */ + + /* note, all other endpoints have minimums set but are initially given NO credits. + * Credits will be distributed as traffic activity demands */ + pCurEpDist = pCurEpDist->pNext; + } + + if (pCredInfo->CurrentFreeCredits <= 0) { + AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits)); + A_ASSERT(FALSE); + return; + } + + /* reset list */ + pCurEpDist = pEPList; + /* now run through the list and set max operating credit limits for everyone */ + while (pCurEpDist != NULL) { + if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) { + /* control service max is just 1 max message */ + pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg; + } else { + /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are + * the same. + * We use a simple calculation here, we take the remaining credits and + * determine how many max messages this can cover and then set each endpoint's + * normal value equal to 3/4 this amount. + * */ + count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg; + count = (count * 3) >> 2; + count = max(count,pCurEpDist->TxCreditsPerMaxMsg); + /* set normal */ + pCurEpDist->TxCreditsNorm = count; + + } + pCurEpDist = pCurEpDist->pNext; + } + +} + + +/* default credit distribution callback + * This callback is invoked whenever endpoints require credit distributions. + * A lock is held while this function is invoked, this function shall NOT block. + * The pEPDistList is a list of distribution structures in prioritized order as + * defined by the call to the HTCSetCreditDistribution() api. + * + */ +static void ar6000_credit_distribute(void *Context, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList, + HTC_CREDIT_DIST_REASON Reason) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context; + + switch (Reason) { + case HTC_CREDIT_DIST_SEND_COMPLETE : + pCurEpDist = pEPDistList; + /* we are given the start of the endpoint distribution list. + * There may be one or more endpoints to service. + * Run through the list and distribute credits */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->TxCreditsToDist > 0) { + /* return the credits back to the endpoint */ + pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist; + /* always zero out when we are done */ + pCurEpDist->TxCreditsToDist = 0; + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) { + /* reduce to the assigned limit, previous credit reductions + * could have caused the limit to change */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned); + } + + if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) { + /* oversubscribed endpoints need to reduce back to normal */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm); + } + + if (!IS_EP_ACTIVE(pCurEpDist)) { + /* endpoint is inactive, now check for messages waiting for credits */ + if (pCurEpDist->TxQueueDepth == 0) { + /* EP is inactive and there are no pending messages, + * reduce credits back to zero to recover credits */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } + } + } + + pCurEpDist = pCurEpDist->pNext; + } + + break; + + case HTC_CREDIT_DIST_ACTIVITY_CHANGE : + RedistributeCredits(pCredInfo,pEPDistList); + break; + case HTC_CREDIT_DIST_SEEK_CREDITS : + SeekCredits(pCredInfo,pEPDistList); + break; + case HTC_DUMP_CREDIT_STATE : + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Credit Distribution, total : %d, free : %d\n", + pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits)); + break; + default: + break; + + } + + /* sanity checks done after each distribution action */ + A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits); + A_ASSERT(pCredInfo->CurrentFreeCredits >= 0); + +} + +/* redistribute credits based on activity change */ +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDistList) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList; + + /* walk through the list and remove credits from inactive endpoints */ + while (pCurEpDist != NULL) { + + if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) { + if (!IS_EP_ACTIVE(pCurEpDist)) { + if (pCurEpDist->TxQueueDepth == 0) { + /* EP is inactive and there are no pending messages, reduce credits back to zero */ + ReduceCredits(pCredInfo, pCurEpDist, 0); + } else { + /* we cannot zero the credits assigned to this EP, but to keep + * the credits available for these leftover packets, reduce to + * a minimum */ + ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsMin); + } + } + } + + /* NOTE in the active case, we do not need to do anything further, + * when an EP goes active and needs credits, HTC will call into + * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS */ + + pCurEpDist = pCurEpDist->pNext; + } + +} + +/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */ +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo, + HTC_ENDPOINT_CREDIT_DIST *pEPDist) +{ + HTC_ENDPOINT_CREDIT_DIST *pCurEpDist; + int credits = 0; + int need; + + do { + + if (pEPDist->ServiceID == WMI_CONTROL_SVC) { + /* we never oversubscribe on the control service, this is not + * a high performance path and the target never holds onto control + * credits for too long */ + break; + } + + if (pEPDist->ServiceID == WMI_DATA_VI_SVC) { + if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) || + (pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) { + /* limit VI service from oversubscribing */ + /* at least one free credit will not be used by VI */ + break; + } + } + + if (pEPDist->ServiceID == WMI_DATA_VO_SVC) { + if ((pEPDist->TxCreditsAssigned >= pEPDist->TxCreditsNorm) || + (pCredInfo->CurrentFreeCredits <= pEPDist->TxCreditsPerMaxMsg)) { + /* limit VO service from oversubscribing */ + /* at least one free credit will not be used by VO */ + break; + } + } + + /* for all other services, we follow a simple algorithm of + * 1. checking the free pool for credits + * 2. checking lower priority endpoints for credits to take */ + + /* give what we can */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + if (credits >= pEPDist->TxCreditsSeek) { + /* we found some to fullfill the seek request */ + break; + } + + /* we don't have enough in the free pool, try taking away from lower priority services + * + * The rule for taking away credits: + * 1. Only take from lower priority endpoints + * 2. Only take what is allocated above the minimum (never starve an endpoint completely) + * 3. Only take what you need. + * + * */ + + /* starting at the lowest priority */ + pCurEpDist = pCredInfo->pLowestPriEpDist; + + /* work backwards until we hit the endpoint again */ + while (pCurEpDist != pEPDist) { + /* calculate how many we need so far */ + need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits; + + if ((pCurEpDist->TxCreditsAssigned - need) >= pCurEpDist->TxCreditsMin) { + /* the current one has been allocated more than it's minimum and it + * has enough credits assigned above it's minimum to fullfill our need + * try to take away just enough to fullfill our need */ + ReduceCredits(pCredInfo, + pCurEpDist, + pCurEpDist->TxCreditsAssigned - need); + + if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) { + /* we have enough */ + break; + } + } + + pCurEpDist = pCurEpDist->pPrev; + } + + /* return what we can get */ + credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek); + + } while (FALSE); + + /* did we find some credits? */ + if (credits) { + /* give what we can */ + GiveCredits(pCredInfo, pEPDist, credits); + } + +} + +/* initialize and setup credit distribution */ +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo) +{ + HTC_SERVICE_ID servicepriority[5]; + + A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO)); + + servicepriority[0] = WMI_CONTROL_SVC; /* highest */ + servicepriority[1] = WMI_DATA_VO_SVC; + servicepriority[2] = WMI_DATA_VI_SVC; + servicepriority[3] = WMI_DATA_BE_SVC; + servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(HTCHandle, + pCredInfo, + ar6000_credit_distribute, + ar6000_credit_init, + servicepriority, + 5); + + return A_OK; +} + diff --git a/drivers/net/wireless/ath6kl/miscdrv/makefile b/drivers/net/wireless/ath6kl/miscdrv/makefile new file mode 100644 index 000000000000..6e53a111b67f --- /dev/null +++ b/drivers/net/wireless/ath6kl/miscdrv/makefile @@ -0,0 +1,22 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation; +# +# Software distributed under the License is distributed on an "AS +# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# +#------------------------------------------------------------------------------ +#============================================================================== +# Author(s): ="Atheros" +#============================================================================== +!INCLUDE $(_MAKEENVROOT)\makefile.def + + + diff --git a/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h b/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h new file mode 100644 index 000000000000..c72f116dbe04 --- /dev/null +++ b/drivers/net/wireless/ath6kl/miscdrv/miscdrv.h @@ -0,0 +1,40 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _MISCDRV_H +#define _MISCDRV_H + + +#define HOST_INTEREST_ITEM_ADDRESS(target, item) \ +(((target) == TARGET_TYPE_AR6001) ? \ + AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + +A_UINT32 ar6kRev2Array[][128] = { + {0xFFFF, 0xFFFF}, // No Patches + }; + +#define CFG_REV2_ITEMS 0 // no patches so far +#define AR6K_RESET_ADDR 0x4000 +#define AR6K_RESET_VAL 0x100 + +#define EEPROM_SZ 768 +#define EEPROM_WAIT_LIMIT 4 + +#endif + diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c new file mode 100644 index 000000000000..9d0c3773d4d7 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_android.c @@ -0,0 +1,621 @@ +/* + * + * Copyright (c) 2004-2010 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ +#include "ar6000_drv.h" +#include "htc.h" +#include + +#include +#ifdef CONFIG_PM + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) +#include +#endif +enum { + WLAN_PWR_CTRL_UP = 0, + WLAN_PWR_CTRL_CUT_PWR, + WLAN_PWR_CTRL_DEEP_SLEEP, + WLAN_PWR_CTRL_WOW +}; +#include +#include + +#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0) +#define MAX_BUF (8*1024) + +#ifdef DEBUG + +#define ATH_DEBUG_DBG_LOG ATH_DEBUG_MAKE_MODULE_MASK(0) + +static ATH_DEBUG_MASK_DESCRIPTION android_debug_desc[] = { + { ATH_DEBUG_DBG_LOG , "Android Debug Logs"}, +}; + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(android, + "android", + "Android Driver Interface", + ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_DBG_LOG, + ATH_DEBUG_DESCRIPTION_COUNT(android_debug_desc), + android_debug_desc); + +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +char fwpath[256] = "/lib/firmware/ath6k/AR6102"; +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ +int buspm = WLAN_PWR_CTRL_CUT_PWR; +int wow2mode = WLAN_PWR_CTRL_CUT_PWR; +#define HAVE_WLAN_PWR_IMPL 0 +#if HAVE_WLAN_PWR_IMPL +/** @brief Disable SDIO clock source and mask all interrupt */ +extern void plat_disable_wlan_slot(void); +/** @brief Enable SDIO clock source and unmask all interrupt */ +extern void plat_enable_wlan_slot(void); +#else +#define plat_disable_wlan_slot() +#define plat_enable_wlan_slot() +#endif + +#endif /* CONFIG_PM */ +extern int bmienable; +extern int wlaninitmode; +extern unsigned int wmitimeout; +extern wait_queue_head_t arEvent; +extern struct net_device *ar6000_devices[]; +#ifdef CONFIG_HOST_TCMD_SUPPORT +extern unsigned int testmode; +#endif +extern char ifname[]; + +const char def_ifname[] = "wlan0"; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_string(fwpath, fwpath, sizeof(fwpath), 0644); +module_param(buspm, int, 0644); +#else +#define __user +/* for linux 2.4 and lower */ +MODULE_PARM(buspm,"i"); +#endif + +struct wake_lock ar6k_init_wake_lock; +struct wake_lock ar6k_wow_wake_lock; +static A_STATUS (*ar6000_avail_ev_p)(void *, void *); + +extern int ar6000_init(struct net_device *dev); +extern A_STATUS ar6000_configure_target(AR_SOFTC_T *ar); +extern void ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile); +extern A_STATUS ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode); +extern void ar6000_destroy(struct net_device *dev, unsigned int unregister); + +static void ar6000_enable_mmchost_detect_change(int enable); +static void ar6000_restart_endpoint(struct net_device *dev); + +#if defined(CONFIG_PM) +static A_STATUS ar6000_suspend_ev(void *context); + +static A_STATUS ar6000_resume_ev(void *context); +#endif + +int android_request_firmware(const struct firmware **firmware_p, const char *name, + struct device *device) +{ + struct file *filp = (struct file *)-ENOENT; + int ret = 0; + mm_segment_t oldfs; + struct firmware *firmware; + char filename[2048]; +#if 0 + const char *raw_filename = strrchr(name, '/'); +#else + const char *raw_filename = NULL; +#endif + *firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL); + if (!firmware) + return -ENOMEM; + if (raw_filename) + ++raw_filename; + else + raw_filename = name; + sprintf(filename, "%s/%s", fwpath, raw_filename); + // Open file + oldfs = get_fs(); + set_fs(KERNEL_DS); + do { + size_t length, bufsize, bmisize; + struct inode *inode; + filp = filp_open(filename, O_RDONLY, S_IRUSR); + if (IS_ERR(filp) || !filp->f_op) { + printk("%s: file %s filp_open error\n", __FUNCTION__, filename); + ret = -1; + break; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + ret = -1; + break; + } + length = i_size_read(inode->i_mapping->host); + bufsize = ALIGN(length, PAGE_SIZE); + bmisize = A_ROUND_UP(length, 4); + bufsize = max(bmisize, bufsize); + firmware->data = vmalloc(bufsize); + firmware->size = bmisize; + if (!firmware->data) { + printk("Cannot allocate buffer for firmware\n"); + ret = -ENOMEM; + break; + } + if (filp->f_op->read(filp, (char*)firmware->data, length, &filp->f_pos) != length) { + printk("%s: file read error, remaining=%d\n", __FUNCTION__, length); + ret = -1; + break; + } + } while (0); + + if (!IS_ERR(filp)) { + filp_close(filp, NULL); + } + set_fs(oldfs); + + if (ret!=0) { + if (firmware) { + if (firmware->data) + vfree(firmware->data); + kfree(firmware); + } + *firmware_p = NULL; + } + return ret; +} + +void android_release_firmware(const struct firmware *firmware) +{ + if (firmware) { + if (firmware->data) + vfree(firmware->data); + kfree(firmware); + } +} + +#if defined(CONFIG_PM) +static void ar6k_send_asleep_event_to_app(AR_SOFTC_T *ar, A_BOOL asleep) +{ + char buf[128]; + union iwreq_data wrqu; + + snprintf(buf, sizeof(buf), "HOST_ASLEEP=%s", asleep ? "asleep" : "awake"); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); +} + +static void ar6000_wow_resume(AR_SOFTC_T *ar) +{ + if (ar->arWowState) { + WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode = {TRUE, FALSE}; + ar->arWowState = 0; + wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode); + wmi_scanparams_cmd(ar->arWmi, 0,0,60,0,0,0,0,0,0,0); + //wmi_set_keepalive_cmd(ar->arWmi, 0); + +#if 1 /* we don't do it if the power consumption is already good enough. */ + if (wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0) == A_OK) { + } +#endif + ar6k_send_asleep_event_to_app(ar, FALSE); + if (ar->arTxPending[ar->arControlEp]) { + long timeleft = wait_event_interruptible_timeout(arEvent, + ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ); + if (!timeleft || signal_pending(current)) { + printk("Failed to Resume Wow!!!!!!!!!!!!!!!!!!!!\n"); + } else { + printk("Resume WoW successfully\n"); + } + } + } else { + printk("WoW does not invoked. skip resume"); + } +} + +static void ar6000_wow_suspend(AR_SOFTC_T *ar) +{ +#define ANDROID_WOW_LIST_ID 1 + if (ar->arNetworkType != AP_NETWORK) { + /* Setup WoW for unicast & Aarp request for our own IP + disable background scan. Set listen interval into 1000 TUs + Enable keepliave for 110 seconds + */ + struct in_ifaddr **ifap = NULL; + struct in_ifaddr *ifa = NULL; + struct in_device *in_dev; + A_UINT8 macMask[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + A_STATUS status; + WMI_ADD_WOW_PATTERN_CMD addWowCmd = { .filter = { 0 } }; + WMI_DEL_WOW_PATTERN_CMD delWowCmd; + WMI_SET_HOST_SLEEP_MODE_CMD hostSleepMode = {FALSE, TRUE}; + WMI_SET_WOW_MODE_CMD wowMode = { .enable_wow = TRUE }; + + ar6000_TxDataCleanup(ar); /* IMPORTANT, otherwise there will be 11mA after listen interval as 1000*/ + +#if 1 /* we don't do it if the power consumption is already good enough. */ + if (wmi_listeninterval_cmd(ar->arWmi, A_MAX_WOW_LISTEN_INTERVAL, 0) == A_OK) { + } +#endif + +// wmi_set_keepalive_cmd(ar->arWmi, 110); /* keepalive otherwise, we will be disconnected*/ + status = wmi_scanparams_cmd(ar->arWmi, 0,0,0xffff,0,0,0,0,0,0,0); + wmi_set_wow_mode_cmd(ar->arWmi, &wowMode); + + /* clear up our WoW pattern first */ + delWowCmd.filter_list_id = ANDROID_WOW_LIST_ID; + delWowCmd.filter_id = 0; + wmi_del_wow_pattern_cmd(ar->arWmi, &delWowCmd); + + /* setup unicast packet pattern for WoW */ + if (ar->arNetDev->dev_addr[1]) { + addWowCmd.filter_list_id = ANDROID_WOW_LIST_ID; + addWowCmd.filter_size = 6; /* MAC address */ + addWowCmd.filter_offset = 2; + status = wmi_add_wow_pattern_cmd(ar->arWmi, &addWowCmd, ar->arNetDev->dev_addr, macMask, addWowCmd.filter_size); + } + /* setup ARP request for our own IP */ + if ((in_dev = __in_dev_get_rtnl(ar->arNetDev)) != NULL) { + for (ifap = &in_dev->ifa_list; (ifa = *ifap) != NULL; ifap = &ifa->ifa_next) { + if (!strcmp(ar->arNetDev->name, ifa->ifa_label)) { + break; /* found */ + } + } + } + if (ifa && ifa->ifa_local) { + WMI_SET_IP_CMD ipCmd; + memset(&ipCmd, 0, sizeof(ipCmd)); + ipCmd.ips[0] = ifa->ifa_local; + status = wmi_set_ip_cmd(ar->arWmi, &ipCmd); + } + ar6k_send_asleep_event_to_app(ar, TRUE); + wmi_set_host_sleep_mode_cmd(ar->arWmi, &hostSleepMode); + if (ar->arTxPending[ar->arControlEp]) { + long timeleft = wait_event_interruptible_timeout(arEvent, + ar->arTxPending[ar->arControlEp] == 0, wmitimeout * HZ); + if (!timeleft || signal_pending(current)) { + /* what can I do? wow resume at once */ + printk("Fail to setup WoW\n"); + } else { + ar->arWowState = 1; + printk("Setup WoW successfully\n"); + } + } + mdelay(10); + } else { + printk("Not allowed to go to WOW at this moment.\n"); + } +} + +static void ar6000_pwr_on(AR_SOFTC_T *ar) +{ + if (ar == NULL) { + /* turn on for all cards */ + } + printk("%s --enter\n", __func__); + +} + +static void ar6000_pwr_down(AR_SOFTC_T *ar) +{ + if (ar == NULL) { + /* shutdown for all cards */ + } + printk("%s --enter\n", __func__); + +} + +static A_STATUS ar6000_suspend_ev(void *context) +{ + int pmmode = buspm; + AR_SOFTC_T *ar = (AR_SOFTC_T *)context; + printk("%s: enter ar %p devices %p\n", __func__, ar, ar6000_devices[0]? netdev_priv(ar6000_devices[0]) : NULL); + +wow_not_connected: + + switch (pmmode) { + case WLAN_PWR_CTRL_DEEP_SLEEP: + ar6000_set_wlan_state(ar, WLAN_DISABLED); + ar->arOsPowerCtrl = WLAN_PWR_CTRL_DEEP_SLEEP; + return A_EBUSY; + case WLAN_PWR_CTRL_WOW: + if (ar->arWmiReady && ar->arWlanState==WLAN_ENABLED && ar->arConnected) { + ar->arOsPowerCtrl = WLAN_PWR_CTRL_WOW; + /* leave for pm_device to setup wow */ + return A_EBUSY; + } else { + pmmode = wow2mode; + goto wow_not_connected; + } + break; + case WLAN_PWR_CTRL_CUT_PWR: + /* fall through */ + default: + ar->arOsPowerCtrl = WLAN_PWR_CTRL_CUT_PWR; + ar6000_stop_endpoint(ar->arNetDev, TRUE); + ar->arWlanState = WLAN_DISABLED; + break; + } + return A_OK; +} + +static A_STATUS ar6000_resume_ev(void *context) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)context; + A_UINT16 powerCtrl = ar->arOsPowerCtrl; + wake_lock(&ar6k_init_wake_lock); + printk("%s: enter\n", __func__); + ar->arOsPowerCtrl = WLAN_PWR_CTRL_UP; + switch (powerCtrl) { + case WLAN_PWR_CTRL_WOW: + printk("Warning! resume but osPowerCtl is not clear\n"); + break; + case WLAN_PWR_CTRL_CUT_PWR: + ar6000_restart_endpoint(ar->arNetDev); + break; + case WLAN_PWR_CTRL_DEEP_SLEEP: + ar6000_set_wlan_state(ar, WLAN_ENABLED); + break; + default: + printk("Strange SDIO bus power mode!!\n"); + break; + } + wake_unlock(&ar6k_init_wake_lock); + return A_OK; +} + +static A_STATUS ar6000_android_avail_ev(void *context, void *hif_handle) +{ + A_STATUS ret; + wake_lock(&ar6k_init_wake_lock); + ret = ar6000_avail_ev_p(context, hif_handle); + wake_unlock(&ar6k_init_wake_lock); + return ret; +} + + +static int ar6000_pm_suspend(struct platform_device *dev, pm_message_t state) +{ + int i; + for (i = 0; i < MAX_AR6000; i++) { + AR_SOFTC_T *ar; + + if (ar6000_devices[i] == NULL) + continue; + ar = (AR_SOFTC_T*)netdev_priv(ar6000_devices[i]); + printk("%s: enter\n", __func__); + switch (ar->arOsPowerCtrl) { + case WLAN_PWR_CTRL_CUT_PWR: + ar6000_pwr_down(ar); + break; + case WLAN_PWR_CTRL_WOW: + ar6000_wow_suspend(ar); + plat_disable_wlan_slot(); + break; + case WLAN_PWR_CTRL_DEEP_SLEEP: + /* nothing to do. keep the power on */ + break; + default: + printk("Something is strange for ar6000_pm_suspend %d\n", ar->arOsPowerCtrl); + break; + } + } + return 0; +} + +static int ar6000_pm_resume(struct platform_device *dev) +{ + int i; + for (i = 0; i < MAX_AR6000; i++) { + AR_SOFTC_T *ar; + + if (ar6000_devices[i] == NULL) + continue; + printk("%s: enter\n", __func__); + ar = (AR_SOFTC_T*)netdev_priv(ar6000_devices[i]); + switch (ar->arOsPowerCtrl) { + case WLAN_PWR_CTRL_CUT_PWR: + ar6000_pwr_on(ar); + break; + case WLAN_PWR_CTRL_WOW: + wake_lock_timeout(&ar6k_wow_wake_lock, 3*HZ); + plat_enable_wlan_slot(); + ar6000_wow_resume(ar); + ar->arOsPowerCtrl = WLAN_PWR_CTRL_UP; + break; + case WLAN_PWR_CTRL_DEEP_SLEEP: + /* nothing to do. keep the power on */ + break; + default: + printk("Something is strange for ar6000_pm_resume %d\n", ar->arOsPowerCtrl); + break; + } + } + return 0; +} + +static int ar6000_pm_probe(struct platform_device *pdev) +{ + ar6000_pwr_on(NULL); + return 0; +} + +static int ar6000_pm_remove(struct platform_device *pdev) +{ + ar6000_pwr_down(NULL); + return 0; +} + +static struct platform_driver ar6000_pm_device = { + .probe = ar6000_pm_probe, + .remove = ar6000_pm_remove, + .suspend = ar6000_pm_suspend, + .resume = ar6000_pm_resume, + .driver = { + .name = "wlan_ar6000_pm_dev", + }, +}; +#endif /* CONFIG_PM */ + +/* Useful for qualcom platform to detect our wlan card for mmc stack */ +static void ar6000_enable_mmchost_detect_change(int enable) +{ +#ifdef CONFIG_MMC_MSM + mm_segment_t oldfs; + struct file *filp = (struct file*)-ENOENT; + int length; + oldfs = get_fs(); + set_fs(KERNEL_DS); + do { + char buf[3]; + filp = filp_open("/sys/devices/platform/msm_sdcc.2/detect_change", O_RDWR, S_IRUSR); + if (IS_ERR(filp) || !filp->f_op) + break; + length = snprintf(buf, sizeof(buf), "%d\n", enable ? 1 : 0); + if (filp->f_op->write(filp, buf, length, &filp->f_pos) != length) { + break; + } + } while (0); + if (!IS_ERR(filp)) { + filp_close(filp, NULL); + } + set_fs(oldfs); +#endif +} + +static void +ar6000_restart_endpoint(struct net_device *dev) +{ + A_STATUS status = A_OK; + AR_SOFTC_T *ar = (AR_SOFTC_T*)netdev_priv(dev); + if (down_interruptible(&ar->arSem)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s(): down_interruptible failed \n", __func__)); + return ; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return; + } + BMIInit(); + do { + A_BOOL rtnl_lock_held_on_entry; + if ( (status=ar6000_configure_target(ar))!=A_OK) + break; + if ( (status=ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n")); + break; + } + rtnl_lock_held_on_entry = rtnl_trylock(); + status = (ar6000_init(dev)==0) ? A_OK : A_ERROR; + if (rtnl_lock_held_on_entry) { + rtnl_unlock(); + } + if (status!=A_OK) { + break; + } + ar->arWlanState = WLAN_ENABLED; + if (ar->arSsidLen) { + ar6000_connect_to_ap(ar); + } + } while (0); + + up(&ar->arSem); + if (status==A_OK) { + return; + } + + ar6000_devices[ar->arDeviceIndex] = NULL; + ar6000_destroy(ar->arNetDev, 1); +} + +void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks) +{ + ar6000_enable_mmchost_detect_change(1); + bmienable = 1; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + if (ifname[0] == '\0') + strcpy(ifname, def_ifname); +#endif + if (wow2mode!=WLAN_PWR_CTRL_CUT_PWR && wow2mode!=WLAN_PWR_CTRL_DEEP_SLEEP) { + wow2mode=WLAN_PWR_CTRL_CUT_PWR; + } + + wake_lock_init(&ar6k_init_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_init"); + wake_lock_init(&ar6k_wow_wake_lock, WAKE_LOCK_SUSPEND, "ar6k_wow"); + +#if defined(CONFIG_PM) + osdrvCallbacks->deviceSuspendHandler = ar6000_suspend_ev; + osdrvCallbacks->deviceResumeHandler = ar6000_resume_ev; +#endif + ar6000_avail_ev_p = osdrvCallbacks->deviceInsertedHandler; + osdrvCallbacks->deviceInsertedHandler = ar6000_android_avail_ev; + +#if defined(CONFIG_PM) + /* Register ar6000_pm_device into system. + * We should also add platform_device into the first item of array devices[] in + * file arch/xxx/mach-xxx/board-xxxx.c + * Otherwise, WoW may not work properly since we may trigger WoW GPIO before system suspend + */ + if (platform_driver_register(&ar6000_pm_device)) + printk("ar6000: fail to register the power control driver.\n"); +#endif +} + +void android_module_exit(void) +{ + wake_lock_destroy(&ar6k_wow_wake_lock); + wake_lock_destroy(&ar6k_init_wake_lock); + +#ifdef CONFIG_PM + platform_driver_unregister(&ar6000_pm_device); +#endif + ar6000_enable_mmchost_detect_change(1); +} + +A_BOOL android_ar6k_endpoint_is_stop(AR_SOFTC_T *ar) +{ +#ifdef CONFIG_PM + return ar->arOsPowerCtrl == WLAN_PWR_CTRL_CUT_PWR; +#else + return FALSE; +#endif +} + +void android_ar6k_check_wow_status(AR_SOFTC_T *ar) +{ +#ifdef CONFIG_PM + if (ar->arWowState) { + ar6000_wow_resume(ar); + } +#endif /* CONFIG_PM */ +} + +A_STATUS android_ar6k_start(AR_SOFTC_T *ar) +{ + return A_OK; +} diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c new file mode 100644 index 000000000000..33e13064c43f --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_drv.c @@ -0,0 +1,6311 @@ +/* + * + * Copyright (c) 2004-2010 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +/* + * This driver is a pseudo ethernet driver to access the Atheros AR6000 + * WLAN Device + */ + +#include "ar6000_drv.h" +#ifdef ATH6K_CONFIG_CFG80211 +#include "cfg80211.h" +#endif /* ATH6K_CONFIG_CFG80211 */ +#include "htc.h" +#include "wmi_filter_linux.h" +#include "epping_test.h" +#include "wlan_config.h" +#include "ar3kconfig.h" + + +/* LINUX_HACK_FUDGE_FACTOR -- this is used to provide a workaround for linux behavior. When + * the meta data was added to the header it was found that linux did not correctly provide + * enough headroom. However when more headroom was requested beyond what was truly needed + * Linux gave the requested headroom. Therefore to get the necessary headroom from Linux + * the driver requests more than is needed by the amount = LINUX_HACK_FUDGE_FACTOR */ +#define LINUX_HACK_FUDGE_FACTOR 16 + +A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + +#ifdef DEBUG + +#define ATH_DEBUG_DBG_LOG ATH_DEBUG_MAKE_MODULE_MASK(0) +#define ATH_DEBUG_WLAN_CONNECT ATH_DEBUG_MAKE_MODULE_MASK(1) +#define ATH_DEBUG_WLAN_SCAN ATH_DEBUG_MAKE_MODULE_MASK(2) +#define ATH_DEBUG_WLAN_TX ATH_DEBUG_MAKE_MODULE_MASK(3) +#define ATH_DEBUG_WLAN_RX ATH_DEBUG_MAKE_MODULE_MASK(4) +#define ATH_DEBUG_HTC_RAW ATH_DEBUG_MAKE_MODULE_MASK(5) +#define ATH_DEBUG_HCI_BRIDGE ATH_DEBUG_MAKE_MODULE_MASK(6) + +static ATH_DEBUG_MASK_DESCRIPTION driver_debug_desc[] = { + { ATH_DEBUG_DBG_LOG , "Target Debug Logs"}, + { ATH_DEBUG_WLAN_CONNECT , "WLAN connect"}, + { ATH_DEBUG_WLAN_SCAN , "WLAN scan"}, + { ATH_DEBUG_WLAN_TX , "WLAN Tx"}, + { ATH_DEBUG_WLAN_RX , "WLAN Rx"}, + { ATH_DEBUG_HTC_RAW , "HTC Raw IF tracing"}, + { ATH_DEBUG_HCI_BRIDGE , "HCI Bridge Setup"}, + { ATH_DEBUG_HCI_RECV , "HCI Recv tracing"}, + { ATH_DEBUG_HCI_SEND , "HCI Send tracing"}, + { ATH_DEBUG_HCI_DUMP , "HCI Packet dumps"}, +}; + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(driver, + "driver", + "Linux Driver Interface", + ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_WLAN_SCAN | + ATH_DEBUG_HCI_BRIDGE, + ATH_DEBUG_DESCRIPTION_COUNT(driver_debug_desc), + driver_debug_desc); + +#endif + + +#define IS_MAC_NULL(mac) (mac[0]==0 && mac[1]==0 && mac[2]==0 && mac[3]==0 && mac[4]==0 && mac[5]==0) +#define IS_MAC_BCAST(mac) (*mac==0xff) + +MODULE_LICENSE("GPL and additional rights"); + +#ifndef REORG_APTC_HEURISTICS +#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#endif /* REORG_APTC_HEURISTICS */ + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +#define APTC_TRAFFIC_SAMPLING_INTERVAL 100 /* msec */ +#define APTC_UPPER_THROUGHPUT_THRESHOLD 3000 /* Kbps */ +#define APTC_LOWER_THROUGHPUT_THRESHOLD 2000 /* Kbps */ + +typedef struct aptc_traffic_record { + A_BOOL timerScheduled; + struct timeval samplingTS; + unsigned long bytesReceived; + unsigned long bytesTransmitted; +} APTC_TRAFFIC_RECORD; + +A_TIMER aptcTimer; +APTC_TRAFFIC_RECORD aptcTR; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +// callbacks registered by HCI transport driver +HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks = { NULL }; +#endif + +unsigned int processDot11Hdr = 0; +int bmienable = BMIENABLE_DEFAULT; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +char ifname[IFNAMSIZ] = "wlan%d"; +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ + +int wlaninitmode = WLAN_INIT_MODE_DEFAULT; +unsigned int bypasswmi = 0; +unsigned int debuglevel = 0; +int tspecCompliance = ATHEROS_COMPLIANCE; +unsigned int busspeedlow = 0; +unsigned int onebitmode = 0; +unsigned int skipflash = 0; +unsigned int wmitimeout = 2; +unsigned int wlanNodeCaching = 1; +unsigned int enableuartprint = ENABLEUARTPRINT_DEFAULT; +unsigned int logWmiRawMsgs = 0; +unsigned int enabletimerwar = 0; +unsigned int fwmode = 1; +unsigned int mbox_yield_limit = 99; +unsigned int enablerssicompensation = 0; +int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF; +int allow_trace_signal = 0; +#ifdef CONFIG_HOST_TCMD_SUPPORT +unsigned int testmode =0; +#endif + +unsigned int irqprocmode = HIF_DEVICE_IRQ_SYNC_ONLY;//HIF_DEVICE_IRQ_ASYNC_SYNC; +unsigned int panic_on_assert = 1; +unsigned int nohifscattersupport = NOHIFSCATTERSUPPORT_DEFAULT; + +unsigned int setuphci = SETUPHCI_DEFAULT; +unsigned int loghci = 0; +unsigned int setupbtdev = SETUPBTDEV_DEFAULT; +#ifndef EXPORT_HCI_BRIDGE_INTERFACE +unsigned int ar3khcibaud = AR3KHCIBAUD_DEFAULT; +unsigned int hciuartscale = HCIUARTSCALE_DEFAULT; +unsigned int hciuartstep = HCIUARTSTEP_DEFAULT; +#endif +#ifdef CONFIG_CHECKSUM_OFFLOAD +unsigned int csumOffload=0; +unsigned int csumOffloadTest=0; +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_string(ifname, ifname, sizeof(ifname), 0644); +module_param(wlaninitmode, int, 0644); +module_param(bmienable, int, 0644); +module_param(bypasswmi, uint, 0644); +module_param(debuglevel, uint, 0644); +module_param(tspecCompliance, int, 0644); +module_param(onebitmode, uint, 0644); +module_param(busspeedlow, uint, 0644); +module_param(skipflash, uint, 0644); +module_param(wmitimeout, uint, 0644); +module_param(wlanNodeCaching, uint, 0644); +module_param(logWmiRawMsgs, uint, 0644); +module_param(enableuartprint, uint, 0644); +module_param(enabletimerwar, uint, 0644); +module_param(fwmode, uint, 0644); +module_param(mbox_yield_limit, uint, 0644); +module_param(reduce_credit_dribble, int, 0644); +module_param(allow_trace_signal, int, 0644); +module_param(enablerssicompensation, uint, 0644); +module_param(processDot11Hdr, uint, 0644); +#ifdef CONFIG_CHECKSUM_OFFLOAD +module_param(csumOffload, uint, 0644); +#endif +#ifdef CONFIG_HOST_TCMD_SUPPORT +module_param(testmode, uint, 0644); +#endif +module_param(irqprocmode, uint, 0644); +module_param(nohifscattersupport, uint, 0644); +module_param(panic_on_assert, uint, 0644); +module_param(setuphci, uint, 0644); +module_param(loghci, uint, 0644); +module_param(setupbtdev, uint, 0644); +#ifndef EXPORT_HCI_BRIDGE_INTERFACE +module_param(ar3khcibaud, uint, 0644); +module_param(hciuartscale, uint, 0644); +module_param(hciuartstep, uint, 0644); +#endif +#else + +#define __user +/* for linux 2.4 and lower */ +MODULE_PARM(bmienable,"i"); +MODULE_PARM(wlaninitmode,"i"); +MODULE_PARM(bypasswmi,"i"); +MODULE_PARM(debuglevel, "i"); +MODULE_PARM(onebitmode,"i"); +MODULE_PARM(busspeedlow, "i"); +MODULE_PARM(skipflash, "i"); +MODULE_PARM(wmitimeout, "i"); +MODULE_PARM(wlanNodeCaching, "i"); +MODULE_PARM(enableuartprint,"i"); +MODULE_PARM(logWmiRawMsgs, "i"); +MODULE_PARM(enabletimerwar,"i"); +MODULE_PARM(fwmode,"i"); +MODULE_PARM(mbox_yield_limit,"i"); +MODULE_PARM(reduce_credit_dribble,"i"); +MODULE_PARM(allow_trace_signal,"i"); +MODULE_PARM(enablerssicompensation,"i"); +MODULE_PARM(processDot11Hdr,"i"); +#ifdef CONFIG_CHECKSUM_OFFLOAD +MODULE_PARM(csumOffload,"i"); +#endif +#ifdef CONFIG_HOST_TCMD_SUPPORT +MODULE_PARM(testmode, "i"); +#endif +MODULE_PARM(irqprocmode, "i"); +MODULE_PARM(nohifscattersupport, "i"); +MODULE_PARM(panic_on_assert, "i"); +MODULE_PARM(setuphci, "i"); +MODULE_PARM(loghci, "i"); +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) +/* in 2.6.10 and later this is now a pointer to a uint */ +unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX; +#define mboxnum &_mboxnum +#else +unsigned int mboxnum = HTC_MAILBOX_NUM_MAX; +#endif + +#ifdef DEBUG +A_UINT32 g_dbg_flags = DBG_DEFAULTS; +unsigned int debugflags = 0; +int debugdriver = 0; +unsigned int debughtc = 0; +unsigned int debugbmi = 0; +unsigned int debughif = 0; +unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0}; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(debugflags, uint, 0644); +module_param(debugdriver, int, 0644); +module_param(debughtc, uint, 0644); +module_param(debugbmi, uint, 0644); +module_param(debughif, uint, 0644); +module_param_array(txcreditsavailable, uint, mboxnum, 0644); +module_param_array(txcreditsconsumed, uint, mboxnum, 0644); +module_param_array(txcreditintrenable, uint, mboxnum, 0644); +module_param_array(txcreditintrenableaggregate, uint, mboxnum, 0644); +#else +/* linux 2.4 and lower */ +MODULE_PARM(debugflags,"i"); +MODULE_PARM(debugdriver, "i"); +MODULE_PARM(debughtc, "i"); +MODULE_PARM(debugbmi, "i"); +MODULE_PARM(debughif, "i"); +MODULE_PARM(txcreditsavailable, "0-3i"); +MODULE_PARM(txcreditsconsumed, "0-3i"); +MODULE_PARM(txcreditintrenable, "0-3i"); +MODULE_PARM(txcreditintrenableaggregate, "0-3i"); +#endif + +#endif /* DEBUG */ + +unsigned int resetok = 1; +unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0}; +unsigned int hifBusRequestNumMax = 40; +unsigned int war23838_disabled = 0; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +unsigned int enableAPTCHeuristics = 1; +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param_array(tx_attempt, uint, mboxnum, 0644); +module_param_array(tx_post, uint, mboxnum, 0644); +module_param_array(tx_complete, uint, mboxnum, 0644); +module_param(hifBusRequestNumMax, uint, 0644); +module_param(war23838_disabled, uint, 0644); +module_param(resetok, uint, 0644); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +module_param(enableAPTCHeuristics, uint, 0644); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#else +MODULE_PARM(tx_attempt, "0-3i"); +MODULE_PARM(tx_post, "0-3i"); +MODULE_PARM(tx_complete, "0-3i"); +MODULE_PARM(hifBusRequestNumMax, "i"); +MODULE_PARM(war23838_disabled, "i"); +MODULE_PARM(resetok, "i"); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +MODULE_PARM(enableAPTCHeuristics, "i"); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ +#endif + +#ifdef BLOCK_TX_PATH_FLAG +int blocktx = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(blocktx, int, 0644); +#else +MODULE_PARM(blocktx, "i"); +#endif +#endif /* BLOCK_TX_PATH_FLAG */ + +typedef struct user_rssi_compensation_t { + A_UINT16 a_enable; + A_INT16 a_param_a; + A_INT16 a_param_b; + A_UINT16 bg_enable; + A_INT16 bg_param_a; + A_INT16 bg_param_b; +} USER_RSSI_CPENSATION; + +static USER_RSSI_CPENSATION rssi_compensation_param; + +static A_INT16 rssi_compensation_table[96]; + +int reconnect_flag = 0; + +/* Function declarations */ +static int ar6000_init_module(void); +static void ar6000_cleanup_module(void); + +int ar6000_init(struct net_device *dev); +static int ar6000_open(struct net_device *dev); +static int ar6000_close(struct net_device *dev); +static void ar6000_init_control_info(AR_SOFTC_T *ar); +static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev); + +void ar6000_destroy(struct net_device *dev, unsigned int unregister); +static void ar6000_detect_error(unsigned long ptr); +static struct net_device_stats *ar6000_get_stats(struct net_device *dev); +static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev); + +static void disconnect_timer_handler(unsigned long ptr); + +void read_rssi_compensation_param(AR_SOFTC_T *ar); + + /* for android builds we call external APIs that handle firmware download and configuration */ +#ifdef ANDROID_ENV +/* !!!! Interim android support to make it easier to patch the default driver for + * android use. You must define an external source file ar6000_android.c that handles the following + * APIs */ +extern A_STATUS android_ar6k_start(AR_SOFTC_T *ar); +extern void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks); +extern void android_module_exit(void); +extern A_BOOL android_ar6k_endpoint_is_stop(AR_SOFTC_T *ar); +extern void android_ar6k_check_wow_status(AR_SOFTC_T *ar); +#endif +/* + * HTC service connection handlers + */ +static A_STATUS ar6000_avail_ev(void *context, void *hif_handle); + +static A_STATUS ar6000_unavail_ev(void *context, void *hif_handle); + +A_STATUS ar6000_configure_target(AR_SOFTC_T *ar); + +void ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile); + +static void ar6000_target_failure(void *Instance, A_STATUS Status); + +static void ar6000_rx(void *Context, HTC_PACKET *pPacket); + +static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint); + +static void ar6000_tx_complete(void *Context, HTC_PACKET_QUEUE *pPackets); + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket); + +#ifdef ATH_AR6K_11N_SUPPORT +static void ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, A_UINT16 num); +#endif +static void ar6000_deliver_frames_to_nw_stack(void * dev, void *osbuf); +//static void ar6000_deliver_frames_to_bt_stack(void * dev, void *osbuf); + +static HTC_PACKET *ar6000_alloc_amsdu_rxbuf(void *Context, HTC_ENDPOINT_ID Endpoint, int Length); + +static void ar6000_refill_amsdu_rxbufs(AR_SOFTC_T *ar, int Count); + +static void ar6000_cleanup_amsdu_rxbufs(AR_SOFTC_T *ar); + +static ssize_t +ar6000_sysfs_bmi_read(struct kobject *kobj, struct bin_attribute *bin_attr, + char *buf, loff_t pos, size_t count); + +static ssize_t +ar6000_sysfs_bmi_write(struct kobject *kobj, struct bin_attribute *bin_attr, + char *buf, loff_t pos, size_t count); + +static A_STATUS +ar6000_sysfs_bmi_init(AR_SOFTC_T *ar); + +static void +ar6000_sysfs_bmi_deinit(AR_SOFTC_T *ar); + +A_STATUS +ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode); + +/* + * Static variables + */ + +struct net_device *ar6000_devices[MAX_AR6000]; +extern struct iw_handler_def ath_iw_handler_def; +DECLARE_WAIT_QUEUE_HEAD(arEvent); +static void ar6000_cookie_init(AR_SOFTC_T *ar); +static void ar6000_cookie_cleanup(AR_SOFTC_T *ar); +static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie); +static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar); + +#ifdef USER_KEYS +static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl); +#endif + + +static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM]; + +#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \ + (((ar)->arTargetType == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((ar)->arTargetType == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ + (((ar)->arTargetType == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0))) + + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) +static struct net_device_ops ar6000_netdev_ops = { + .ndo_init = NULL, + .ndo_open = ar6000_open, + .ndo_stop = ar6000_close, + .ndo_get_stats = ar6000_get_stats, + .ndo_do_ioctl = ar6000_ioctl, + .ndo_start_xmit = ar6000_data_tx, +}; +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) */ + +/* Debug log support */ + +/* + * Flag to govern whether the debug logs should be parsed in the kernel + * or reported to the application. + */ +#define REPORT_DEBUG_LOGS_TO_APP + +A_STATUS +ar6000_set_host_app_area(AR_SOFTC_T *ar) +{ + A_UINT32 address, data; + struct host_app_area_s host_app_area; + + /* Fetch the address of the host_app_area_s instance in the host interest area */ + address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest)); + if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) { + return A_ERROR; + } + address = TARG_VTOP(ar->arTargetType, data); + host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION; + if (ar6000_WriteDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&host_app_area, + sizeof(struct host_app_area_s)) != A_OK) + { + return A_ERROR; + } + + return A_OK; +} + +A_UINT32 +dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar) +{ + A_UINT32 param; + A_UINT32 address; + A_STATUS status; + + address = TARG_VTOP(ar->arTargetType, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr)); + if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)¶m, 4)) != A_OK) + { + param = 0; + } + + return param; +} + +/* + * The dbglog module has been initialized. Its ok to access the relevant + * data stuctures over the diagnostic window. + */ +void +ar6000_dbglog_init_done(AR_SOFTC_T *ar) +{ + ar->dbglog_init_done = TRUE; +} + +A_UINT32 +dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 numargs; + A_UINT32 length; + A_UINT32 fraglen; + + count = fraglen = 0; + buffer = (A_INT32 *)datap; + length = (limit >> 2); + + if (len <= limit) { + fraglen = len; + } else { + while (count < length) { + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + fraglen = (count << 2); + count += numargs + 1; + } + } + + return fraglen; +} + +void +dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len) +{ + A_INT32 *buffer; + A_UINT32 count; + A_UINT32 timestamp; + A_UINT32 debugid; + A_UINT32 moduleid; + A_UINT32 numargs; + A_UINT32 length; + + count = 0; + buffer = (A_INT32 *)datap; + length = (len >> 2); + while (count < length) { + debugid = DBGLOG_GET_DBGID(buffer[count]); + moduleid = DBGLOG_GET_MODULEID(buffer[count]); + numargs = DBGLOG_GET_NUMARGS(buffer[count]); + timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]); + switch (numargs) { + case 0: + AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d)\n", moduleid, debugid, timestamp)); + break; + + case 1: + AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d): 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1])); + break; + + case 2: + AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid, + timestamp, buffer[count+1], buffer[count+2])); + break; + + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid args: %d\n", numargs)); + } + count += numargs + 1; + } +} + +int +ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar) +{ + struct dbglog_hdr_s debug_hdr; + struct dbglog_buf_s debug_buf; + A_UINT32 address; + A_UINT32 length; + A_UINT32 dropped; + A_UINT32 firstbuf; + A_UINT32 debug_hdr_ptr; + + if (!ar->dbglog_init_done) return A_ERROR; + + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->dbgLogFetchInProgress) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return A_EBUSY; + } + + /* block out others */ + ar->dbgLogFetchInProgress = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar); + printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr); + + /* Get the contents of the ring buffer */ + if (debug_hdr_ptr) { + address = TARG_VTOP(ar->arTargetType, debug_hdr_ptr); + length = sizeof(struct dbglog_hdr_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_hdr, length); + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_hdr.dbuf); + firstbuf = address; + dropped = debug_hdr.dropped; + length = sizeof(struct dbglog_buf_s); + ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length); + + do { + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.buffer); + length = debug_buf.length; + if ((length) && (debug_buf.length <= debug_buf.bufsize)) { + /* Rewind the index if it is about to overrun the buffer */ + if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) { + ar->log_cnt = 0; + } + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length)) + { + break; + } + ar6000_dbglog_event(ar, dropped, (A_INT8*)&ar->log_buffer[ar->log_cnt], length); + ar->log_cnt += length; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_DBG_LOG,("Length: %d (Total size: %d)\n", + debug_buf.length, debug_buf.bufsize)); + } + + address = TARG_VTOP(ar->arTargetType, (A_UINT32)debug_buf.next); + length = sizeof(struct dbglog_buf_s); + if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address, + (A_UCHAR *)&debug_buf, length)) + { + break; + } + + } while (address != firstbuf); + } + + ar->dbgLogFetchInProgress = FALSE; + + return A_OK; +} + +void +ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length) +{ +#ifdef REPORT_DEBUG_LOGS_TO_APP + #define MAX_WIRELESS_EVENT_SIZE 252 + /* + * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages. + * There seems to be a limitation on the length of message that could be + * transmitted to the user app via this mechanism. + */ + A_UINT32 send, sent; + + sent = 0; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + while (send) { + ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, (A_UINT8*)&buffer[sent], send); + sent += send; + send = dbglog_get_debug_fragment(&buffer[sent], length - sent, + MAX_WIRELESS_EVENT_SIZE); + } +#else + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Dropped logs: 0x%x\nDebug info length: %d\n", + dropped, length)); + + /* Interpret the debug logs */ + dbglog_parse_debug_logs((A_INT8*)buffer, length); +#endif /* REPORT_DEBUG_LOGS_TO_APP */ +} + + +static int __init +ar6000_init_module(void) +{ + static int probed = 0; + A_STATUS status; + OSDRV_CALLBACKS osdrvCallbacks; + + a_module_debug_support_init(); + +#ifdef DEBUG + /* check for debug mask overrides */ + if (debughtc != 0) { + ATH_DEBUG_SET_DEBUG_MASK(htc,debughtc); + } + if (debugbmi != 0) { + ATH_DEBUG_SET_DEBUG_MASK(bmi,debugbmi); + } + if (debughif != 0) { + ATH_DEBUG_SET_DEBUG_MASK(hif,debughif); + } + if (debugdriver != 0) { + ATH_DEBUG_SET_DEBUG_MASK(driver,debugdriver); + } + +#endif + + A_REGISTER_MODULE_DEBUG_INFO(driver); + + A_MEMZERO(&osdrvCallbacks,sizeof(osdrvCallbacks)); + osdrvCallbacks.deviceInsertedHandler = ar6000_avail_ev; + osdrvCallbacks.deviceRemovedHandler = ar6000_unavail_ev; + +#ifdef ANDROID_ENV + android_module_init(&osdrvCallbacks); +#endif + +#ifdef DEBUG + /* Set the debug flags if specified at load time */ + if(debugflags != 0) + { + g_dbg_flags = debugflags; + } +#endif + + if (probed) { + return -ENODEV; + } + probed++; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD)); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + ar6000_gpio_init(); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + status = HIFInit(&osdrvCallbacks); + if(status != A_OK) + return -ENODEV; + + return 0; +} + +static void __exit +ar6000_cleanup_module(void) +{ + int i = 0; + struct net_device *ar6000_netdev; + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + /* Delete the Adaptive Power Control timer */ + if (timer_pending(&aptcTimer)) { + del_timer_sync(&aptcTimer); + } +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] != NULL) { + ar6000_netdev = ar6000_devices[i]; + ar6000_devices[i] = NULL; + ar6000_destroy(ar6000_netdev, 1); + } + } + + HIFShutDownDevice(NULL); + + a_module_debug_support_cleanup(); + +#ifdef ANDROID_ENV + android_module_exit(); +#endif + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_cleanup: success\n")); +} + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +void +aptcTimerHandler(unsigned long arg) +{ + A_UINT32 numbytes; + A_UINT32 throughput; + AR_SOFTC_T *ar; + A_STATUS status; + + ar = (AR_SOFTC_T *)arg; + A_ASSERT(ar != NULL); + A_ASSERT(!timer_pending(&aptcTimer)); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + /* Get the number of bytes transferred */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */ + if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) { + /* Enable Sleep and delete the timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, REC_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_ASSERT(status == A_OK); + aptcTR.timerScheduled = FALSE; + } else { + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +#ifdef ATH_AR6K_11N_SUPPORT +static void +ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, A_UINT16 num) +{ + void * osbuf; + + while(num) { + if((osbuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE))) { + A_NETBUF_ENQUEUE(q, osbuf); + } else { + break; + } + num--; + } + + if(num) { + A_PRINTF("%s(), allocation of netbuf failed", __func__); + } +} +#endif + +static struct bin_attribute bmi_attr = { + .attr = {.name = "bmi", .mode = 0600}, + .read = ar6000_sysfs_bmi_read, + .write = ar6000_sysfs_bmi_write, +}; + +static ssize_t +ar6000_sysfs_bmi_read(struct kobject *kobj, struct bin_attribute *bin_attr, + char *buf, loff_t pos, size_t count) +{ + int index; + AR_SOFTC_T *ar; + HIF_DEVICE_OS_DEVICE_INFO *osDevInfo; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Read %d bytes\n", count)); + for (index=0; index < MAX_AR6000; index++) { + ar = (AR_SOFTC_T *)ar6k_priv(ar6000_devices[index]); + osDevInfo = &ar->osDevInfo; + if (kobj == (&(((struct device *)osDevInfo->pOSDevice)->kobj))) { + break; + } + } + + if (index == MAX_AR6000) return 0; + + if ((BMIRawRead(ar->arHifDevice, (A_UCHAR*)buf, count, TRUE)) != A_OK) { + return 0; + } + + return count; +} + +static ssize_t +ar6000_sysfs_bmi_write(struct kobject *kobj, struct bin_attribute *bin_attr, + char *buf, loff_t pos, size_t count) +{ + int index; + AR_SOFTC_T *ar; + HIF_DEVICE_OS_DEVICE_INFO *osDevInfo; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Write %d bytes\n", count)); + for (index=0; index < MAX_AR6000; index++) { + ar = (AR_SOFTC_T *)ar6k_priv(ar6000_devices[index]); + osDevInfo = &ar->osDevInfo; + if (kobj == (&(((struct device *)osDevInfo->pOSDevice)->kobj))) { + break; + } + } + + if (index == MAX_AR6000) return 0; + + if ((BMIRawWrite(ar->arHifDevice, (A_UCHAR*)buf, count)) != A_OK) { + return 0; + } + + return count; +} + +static A_STATUS +ar6000_sysfs_bmi_init(AR_SOFTC_T *ar) +{ + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Creating sysfs entry\n")); + A_MEMZERO(&ar->osDevInfo, sizeof(HIF_DEVICE_OS_DEVICE_INFO)); + + /* Get the underlying OS device */ + status = HIFConfigureDevice(ar->arHifDevice, + HIF_DEVICE_GET_OS_DEVICE, + &ar->osDevInfo, + sizeof(HIF_DEVICE_OS_DEVICE_INFO)); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI: Failed to get OS device info from HIF\n")); + return A_ERROR; + } + + /* Create a bmi entry in the sysfs filesystem */ + if ((sysfs_create_bin_file(&(((struct device *)ar->osDevInfo.pOSDevice)->kobj), &bmi_attr)) < 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMI: Failed to create entry for bmi in sysfs filesystem\n")); + return A_ERROR; + } + + return A_OK; +} + +static void +ar6000_sysfs_bmi_deinit(AR_SOFTC_T *ar) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Deleting sysfs entry\n")); + + sysfs_remove_bin_file(&(((struct device *)ar->osDevInfo.pOSDevice)->kobj), &bmi_attr); +} + +#define bmifn(fn) do { \ + if ((fn) < A_OK) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__)); \ + return A_ERROR; \ + } \ +} while(0) + +#ifdef INIT_MODE_DRV_ENABLED + +#ifdef SOFTMAC_FILE_USED +#define AR6001_MAC_ADDRESS_OFFSET 0x06 +#define AR6002_MAC_ADDRESS_OFFSET 0x0A +#define AR6003_MAC_ADDRESS_OFFSET 0x16 +static +void calculate_crc(A_UINT32 TargetType, A_UCHAR *eeprom_data) +{ + A_UINT16 *ptr_crc; + A_UINT16 *ptr16_eeprom; + A_UINT16 checksum; + A_UINT32 i; + A_UINT32 eeprom_size; + + if (TargetType == TARGET_TYPE_AR6001) + { + eeprom_size = 512; + ptr_crc = (A_UINT16 *)eeprom_data; + } + else if (TargetType == TARGET_TYPE_AR6003) + { + eeprom_size = 1024; + ptr_crc = (A_UINT16 *)((A_UCHAR *)eeprom_data + 0x04); + } + else + { + eeprom_size = 768; + ptr_crc = (A_UINT16 *)((A_UCHAR *)eeprom_data + 0x04); + } + + + // Clear the crc + *ptr_crc = 0; + + // Recalculate new CRC + checksum = 0; + ptr16_eeprom = (A_UINT16 *)eeprom_data; + for (i = 0;i < eeprom_size; i += 2) + { + checksum = checksum ^ (*ptr16_eeprom); + ptr16_eeprom++; + } + checksum = 0xFFFF ^ checksum; + *ptr_crc = checksum; +} + +static void +ar6000_softmac_update(AR_SOFTC_T *ar, A_UCHAR *eeprom_data, size_t size) +{ + const char *source = "random generated"; + const struct firmware *softmac_entry; + A_UCHAR *ptr_mac; + switch (ar->arTargetType) { + case TARGET_TYPE_AR6001: + ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6001_MAC_ADDRESS_OFFSET); + break; + case TARGET_TYPE_AR6002: + ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6002_MAC_ADDRESS_OFFSET); + break; + case TARGET_TYPE_AR6003: + ptr_mac = (A_UINT8 *)((A_UCHAR *)eeprom_data + AR6003_MAC_ADDRESS_OFFSET); + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Target Type \n")); + return; + } + printk("MAC from EEPROM %02X:%02X:%02X:%02X:%02X:%02X\n", + ptr_mac[0], ptr_mac[1], ptr_mac[2], + ptr_mac[3], ptr_mac[4], ptr_mac[5]); + + /* create a random MAC in case we cannot read file from system */ + ptr_mac[0] = 0; + ptr_mac[1] = 0x03; + ptr_mac[2] = 0x7F; + ptr_mac[3] = random32() & 0xff; + ptr_mac[4] = random32() & 0xff; + ptr_mac[5] = random32() & 0xff; + if ((A_REQUEST_FIRMWARE(&softmac_entry, "softmac", ((struct device *)ar->osDevInfo.pOSDevice))) == 0) + { + A_CHAR *macbuf = A_MALLOC_NOWAIT(softmac_entry->size+1); + if (macbuf) { + unsigned int softmac[6]; + memcpy(macbuf, softmac_entry->data, softmac_entry->size); + macbuf[softmac_entry->size] = '\0'; + if (sscanf(macbuf, "%02x:%02x:%02x:%02x:%02x:%02x", + &softmac[0], &softmac[1], &softmac[2], + &softmac[3], &softmac[4], &softmac[5])==6) { + int i; + for (i=0; i<6; ++i) { + ptr_mac[i] = softmac[i] & 0xff; + } + source = "softmac file"; + } + A_FREE(macbuf); + } + A_RELEASE_FIRMWARE(softmac_entry); + } + printk("MAC from %s %02X:%02X:%02X:%02X:%02X:%02X\n", source, + ptr_mac[0], ptr_mac[1], ptr_mac[2], + ptr_mac[3], ptr_mac[4], ptr_mac[5]); + calculate_crc(ar->arTargetType, eeprom_data); +} +#endif /* SOFTMAC_FILE_USED */ + +static A_STATUS +ar6000_transfer_bin_file(AR_SOFTC_T *ar, AR6K_BIN_FILE file, A_UINT32 address, A_BOOL compressed) +{ + A_STATUS status; + const char *filename; + const struct firmware *fw_entry; + + switch (file) { + case AR6K_OTP_FILE: + if (ar->arVersion.target_ver == AR6003_REV1_VERSION) { + filename = AR6003_REV1_OTP_FILE; + } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) { + filename = AR6003_REV2_OTP_FILE; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver)); + return A_ERROR; + } + break; + + case AR6K_FIRMWARE_FILE: + if (ar->arVersion.target_ver == AR6003_REV1_VERSION) { + filename = AR6003_REV1_FIRMWARE_FILE; + } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) { + filename = AR6003_REV2_FIRMWARE_FILE; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver)); + return A_ERROR; + } +#ifdef CONFIG_HOST_TCMD_SUPPORT + if(testmode) { + if (ar->arVersion.target_ver == AR6003_REV1_VERSION) { + filename = AR6003_REV1_TCMD_FIRMWARE_FILE; + } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) { + filename = AR6003_REV2_TCMD_FIRMWARE_FILE; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver)); + return A_ERROR; + } + compressed = 0; + } +#endif +#ifdef HTC_RAW_INTERFACE + if (bypasswmi) { + if (ar->arVersion.target_ver == AR6003_REV1_VERSION) { + filename = AR6003_REV1_ART_FIRMWARE_FILE; + } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) { + filename = AR6003_REV2_ART_FIRMWARE_FILE; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver)); + return A_ERROR; + } + compressed = 0; + } +#endif + break; + + case AR6K_PATCH_FILE: + if (ar->arVersion.target_ver == AR6003_REV1_VERSION) { + filename = AR6003_REV1_PATCH_FILE; + } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) { + filename = AR6003_REV2_PATCH_FILE; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver)); + return A_ERROR; + } + break; + + case AR6K_BOARD_DATA_FILE: + if (ar->arVersion.target_ver == AR6003_REV1_VERSION) { + filename = AR6003_REV1_BOARD_DATA_FILE; + } else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) { + filename = AR6003_REV2_BOARD_DATA_FILE; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver)); + return A_ERROR; + } + break; + + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown file type: %d\n", file)); + return A_ERROR; + } + if ((A_REQUEST_FIRMWARE(&fw_entry, filename, ((struct device *)ar->osDevInfo.pOSDevice))) != 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to get %s\n", filename)); + return A_ENOENT; + } + +#ifdef SOFTMAC_FILE_USED + if (file==AR6K_BOARD_DATA_FILE && fw_entry->data) { + ar6000_softmac_update(ar, (A_UCHAR *)fw_entry->data, fw_entry->size); + } +#endif + + if (compressed) { + status = BMIFastDownload(ar->arHifDevice, address, (A_UCHAR *)fw_entry->data, fw_entry->size); + } else { + status = BMIWriteMemory(ar->arHifDevice, address, (A_UCHAR *)fw_entry->data, fw_entry->size); + } + + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI operation failed: %d\n", __LINE__)); + A_RELEASE_FIRMWARE(fw_entry); + return A_ERROR; + } + A_RELEASE_FIRMWARE(fw_entry); + return A_OK; +} +#endif /* INIT_MODE_DRV_ENABLED */ + +A_STATUS +ar6000_sysfs_bmi_get_config(AR_SOFTC_T *ar, A_UINT32 mode) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("BMI: Requesting device specific configuration\n")); + + if (mode == WLAN_INIT_MODE_UDEV) { + A_CHAR version[16]; + const struct firmware *fw_entry; + + /* Get config using udev through a script in user space */ + sprintf(version, "%2.2x", ar->arVersion.target_ver); + if ((A_REQUEST_FIRMWARE(&fw_entry, version, ((struct device *)ar->osDevInfo.pOSDevice))) != 0) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI: Failure to get configuration for target version: %s\n", version)); + return A_ERROR; + } + + A_RELEASE_FIRMWARE(fw_entry); +#ifdef INIT_MODE_DRV_ENABLED + } else { + /* The config is contained within the driver itself */ + A_STATUS status; + A_UINT32 param, options, sleep, address; + + /* Temporarily disable system sleep */ + address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; + bmifn(BMIReadSOCRegister(ar->arHifDevice, address, ¶m)); + options = param; + param |= AR6K_OPTION_SLEEP_DISABLE; + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + + address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; + bmifn(BMIReadSOCRegister(ar->arHifDevice, address, ¶m)); + sleep = param; + param |= WLAN_SYSTEM_SLEEP_DISABLE_SET(1); + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("old options: %d, old sleep: %d\n", options, sleep)); + + if (ar->arTargetType == TARGET_TYPE_AR6003) { + /* Run at 80/88MHz by default */ + param = CPU_CLOCK_STANDARD_SET(1); + } else { + /* Run at 40/44MHz by default */ + param = CPU_CLOCK_STANDARD_SET(0); + } + address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + + param = 0; + if (ar->arTargetType == TARGET_TYPE_AR6002) { + bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_ext_clk_detected), (A_UCHAR *)¶m, 4)); + } + + /* LPO_CAL.ENABLE = 1 if no external clk is detected */ + if (param != 1) { + address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; + param = LPO_CAL_ENABLE_SET(1); + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + } + + /* Venus2.0: Lower SDIO pad drive strength, + * temporary WAR to avoid SDIO CRC error */ + if (ar->arVersion.target_ver == AR6003_REV2_VERSION) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6K: Temporary WAR to avoid SDIO CRC error\n")); + param = 0x20; + address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + + address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + + address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + + address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + } + +#ifdef FORCE_INTERNAL_CLOCK + /* Ignore external clock, if any, and force use of internal clock */ + if (ar->arTargetType == TARGET_TYPE_AR6003) { + /* hi_ext_clk_detected = 0 */ + param = 0; + bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_ext_clk_detected), (A_UCHAR *)¶m, 4)); + + /* CLOCK_CONTROL &= ~LF_CLK32 */ + address = RTC_BASE_ADDRESS + CLOCK_CONTROL_ADDRESS; + bmifn(BMIReadSOCRegister(ar->arHifDevice, address, ¶m)); + param &= (~CLOCK_CONTROL_LF_CLK32_SET(1)); + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + } +#endif /* FORCE_INTERNAL_CLOCK */ + + /* Transfer Board Data from Target EEPROM to Target RAM */ + if (ar->arTargetType == TARGET_TYPE_AR6003) { + /* Determine where in Target RAM to write Board Data */ + bmifn(BMIReadMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data), (A_UCHAR *)&address, 4)); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("Board Data download address: 0x%x\n", address)); + + /* Write EEPROM data to Target RAM */ + if ((ar6000_transfer_bin_file(ar, AR6K_BOARD_DATA_FILE, address, FALSE)) != A_OK) { + return A_ERROR; + } + + /* Record the fact that Board Data IS initialized */ + param = 1; + bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data_initialized), (A_UCHAR *)¶m, 4)); + + /* Transfer One time Programmable data */ + AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver); + status = ar6000_transfer_bin_file(ar, AR6K_OTP_FILE, address, TRUE); + if (status == A_OK) { + /* Execute the OTP code */ + param = 0; + AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver); + bmifn(BMIExecute(ar->arHifDevice, address, ¶m)); + } else if (status != A_ENOENT) { + return A_ERROR; + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Programming of board data for chip %d not supported\n", ar->arTargetType)); + return A_ERROR; + } + + /* Download Target firmware */ + AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver); + if ((ar6000_transfer_bin_file(ar, AR6K_FIRMWARE_FILE, address, TRUE)) != A_OK) { + return A_ERROR; + } + + /* Set starting address for firmware */ + AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver); + bmifn(BMISetAppStart(ar->arHifDevice, address)); + + /* Apply the patches */ + AR6K_PATCH_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver); + if ((ar6000_transfer_bin_file(ar, AR6K_PATCH_FILE, address, FALSE)) != A_OK) { + return A_ERROR; + } + + param = address; + bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dset_list_head), (A_UCHAR *)¶m, 4)); + + if (ar->arTargetType == TARGET_TYPE_AR6003) { + if (ar->arVersion.target_ver == AR6003_REV1_VERSION) { + /* Reserve 5.5K of RAM */ + param = 5632; + } else { /* AR6003_REV2_VERSION */ + /* Reserve 6K of RAM */ + param = 6144; + } + bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), (A_UCHAR *)¶m, 4)); + } + + /* Restore system sleep */ + address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, sleep)); + + address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; + param = options | 0x20; + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + + if (ar->arTargetType == TARGET_TYPE_AR6003) { + /* Configure GPIO AR6003 UART */ +#ifndef CONFIG_AR600x_DEBUG_UART_TX_PIN +#define CONFIG_AR600x_DEBUG_UART_TX_PIN 8 +#endif + param = CONFIG_AR600x_DEBUG_UART_TX_PIN; + bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbg_uart_txpin), (A_UCHAR *)¶m, 4)); + +#if (CONFIG_AR600x_DEBUG_UART_TX_PIN == 23) + { + address = GPIO_BASE_ADDRESS + CLOCK_GPIO_ADDRESS; + bmifn(BMIReadSOCRegister(ar->arHifDevice, address, ¶m)); + param |= CLOCK_GPIO_BT_CLK_OUT_EN_SET(1); + bmifn(BMIWriteSOCRegister(ar->arHifDevice, address, param)); + } +#endif + + /* Configure GPIO for BT Reset */ +#ifdef ATH6KL_CONFIG_GPIO_BT_RESET + param = CONFIG_AR600x_BT_RESET_PIN; + bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_hci_uart_support_pins), (A_UCHAR *)¶m, 4)); +#endif /* ATH6KL_CONFIG_GPIO_BT_RESET */ + } +#ifdef HTC_RAW_INTERFACE + if (bypasswmi) { + /* Don't run BMIDone for ART mode and force resetok=0 */ + resetok = 0; + msleep(1000); + return A_OK; + } +#endif /* HTC_RAW_INTERFACE */ + /* Tell Target to execute loaded firmware */ + bmifn(BMIDone(ar->arHifDevice)); +#endif /* INIT_MODE_DRV_ENABLED */ + } + + return A_OK; +} + +A_STATUS +ar6000_configure_target(AR_SOFTC_T *ar) +{ + A_UINT32 param; + if (enableuartprint) { + param = 1; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for enableuartprint failed \n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Serial console prints enabled\n")); + } + + /* Tell target which HTC version it is used*/ + param = HTC_PROTOCOL_VERSION; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for htc version failed \n")); + return A_ERROR; + } + +#ifdef CONFIG_HOST_TCMD_SUPPORT + if(testmode) { + ar->arTargetMode = AR6000_TCMD_MODE; + }else { + ar->arTargetMode = AR6000_WLAN_MODE; + } +#endif + if (enabletimerwar) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for enabletimerwar failed \n")); + return A_ERROR; + } + + param |= HI_OPTION_TIMER_WAR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for enabletimerwar failed \n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Timer WAR enabled\n")); + } + + /* set the firmware mode to STA/IBSS/AP */ + { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for setting fwmode failed \n")); + return A_ERROR; + } + + param |= (fwmode << HI_OPTION_FW_MODE_SHIFT); + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for setting fwmode failed \n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Firmware mode set\n")); + } +#if 0 /* HOST_INTEREST is no longer used to configure dot11 processing rule */ + if (processDot11Hdr) { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for processDot11Hdr failed \n")); + return A_ERROR; + } + + param |= HI_OPTION_RELAY_DOT11_HDR; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for processDot11Hdr failed \n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("processDot11Hdr enabled\n")); + } +#endif + +#ifdef ATH6KL_DISABLE_TARGET_DBGLOGS + { + A_UINT32 param; + + if (BMIReadMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4)!= A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIReadMemory for disabling debug logs failed\n")); + return A_ERROR; + } + + param |= HI_OPTION_DISABLE_DBGLOG; + + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for HI_OPTION_DISABLE_DBGLOG\n")); + return A_ERROR; + } + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Firmware mode set\n")); + } +#endif /* ATH6KL_DISABLE_TARGET_DBGLOGS */ + + // No need to reserve RAM space for patch as AR6001 is flash based + if (ar->arTargetType == TARGET_TYPE_AR6001) { + param = 0; + if (BMIWriteMemory(ar->arHifDevice, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), + (A_UCHAR *)¶m, + 4) != A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for hi_end_RAM_reserve_sz failed \n")); + return A_ERROR; + } + } + + + /* since BMIInit is called in the driver layer, we have to set the block + * size here for the target */ + + if (A_FAILED(ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + mbox_yield_limit, + 0 /* use default number of control buffers */ + ))) { + return A_ERROR; + } + + if (setupbtdev != 0) { + if (A_FAILED(ar6000_set_hci_bridge_flags(ar->arHifDevice, + ar->arTargetType, + setupbtdev))) { + return A_ERROR; + } + } + return A_OK; +} + +/* + * HTC Event handlers + */ +static A_STATUS +ar6000_avail_ev(void *context, void *hif_handle) +{ + int i; + struct net_device *dev; + void *ar_netif; + AR_SOFTC_T *ar; + int device_index = 0; + HTC_INIT_INFO htcInfo; +#ifdef ATH6K_CONFIG_CFG80211 + struct wireless_dev *wdev; +#endif /* ATH6K_CONFIG_CFG80211 */ + A_STATUS init_status = A_OK; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_available\n")); + + for (i=0; i < MAX_AR6000; i++) { + if (ar6000_devices[i] == NULL) { + break; + } + } + + if (i == MAX_AR6000) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: max devices reached\n")); + return A_ERROR; + } + + /* Save this. It gives a bit better readability especially since */ + /* we use another local "i" variable below. */ + device_index = i; + +#ifdef ATH6K_CONFIG_CFG80211 + wdev = ar6k_cfg80211_init(NULL); + if (IS_ERR(wdev)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ar6k_cfg80211_init failed\n", __func__)); + return A_ERROR; + } + ar_netif = wdev_priv(wdev); +#else + dev = alloc_etherdev(sizeof(AR_SOFTC_T)); + if (dev == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: can't alloc etherdev\n")); + return A_ERROR; + } + ether_setup(dev); + ar_netif = ar6k_priv(dev); +#endif /* ATH6K_CONFIG_CFG80211 */ + + if (ar_netif == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Can't allocate ar6k priv memory\n", __func__)); + return A_ERROR; + } + + A_MEMZERO(ar_netif, sizeof(AR_SOFTC_T)); + ar = (AR_SOFTC_T *)ar_netif; + +#ifdef ATH6K_CONFIG_CFG80211 + ar->wdev = wdev; + wdev->iftype = NL80211_IFTYPE_STATION; + + dev = alloc_netdev_mq(0, "wlan%d", ether_setup, 1); + if (!dev) { + printk(KERN_CRIT "AR6K: no memory for network device instance\n"); + ar6k_cfg80211_deinit(ar); + return A_ERROR; + } + + dev->ieee80211_ptr = wdev; + SET_NETDEV_DEV(dev, wiphy_dev(wdev->wiphy)); + wdev->netdev = dev; + ar->arNetworkType = INFRA_NETWORK; +#endif /* ATH6K_CONFIG_CFG80211 */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + if (ifname[0]) + { + strcpy(dev->name, ifname); + } +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) */ + +#ifdef SET_MODULE_OWNER + SET_MODULE_OWNER(dev); +#endif + +#ifdef SET_NETDEV_DEV + if (ar_netif) { + HIF_DEVICE_OS_DEVICE_INFO osDevInfo; + A_MEMZERO(&osDevInfo, sizeof(osDevInfo)); + if ( A_SUCCESS( HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_OS_DEVICE, + &osDevInfo, sizeof(osDevInfo))) ) { + SET_NETDEV_DEV(dev, osDevInfo.pOSDevice); + } + } +#endif + + ar->arNetDev = dev; + ar->arHifDevice = hif_handle; + ar->arWlanState = WLAN_ENABLED; + ar->arDeviceIndex = device_index; + + A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev); + ar->arHBChallengeResp.seqNum = 0; + ar->arHBChallengeResp.outstanding = FALSE; + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT; + ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT; + + ar6000_init_control_info(ar); + init_waitqueue_head(&arEvent); + sema_init(&ar->arSem, 1); + ar->bIsDestroyProgress = FALSE; + + INIT_HTC_PACKET_QUEUE(&ar->amsdu_rx_buffer_queue); + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + A_INIT_TIMER(&ar->disconnect_timer, disconnect_timer_handler, dev); + + /* + * If requested, perform some magic which requires no cooperation from + * the Target. It causes the Target to ignore flash and execute to the + * OS from ROM. + * + * This is intended to support recovery from a corrupted flash on Targets + * that support flash. + */ + if (skipflash) + { + //ar6000_reset_device_skipflash(ar->arHifDevice); + } + + BMIInit(); + + if (bmienable) { + ar6000_sysfs_bmi_init(ar); + } + + { + struct bmi_target_info targ_info; + + if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) { + init_status = A_ERROR; + goto avail_ev_failed; + } + + ar->arVersion.target_ver = targ_info.target_ver; + ar->arTargetType = targ_info.target_type; + + /* do any target-specific preparation that can be done through BMI */ + if (ar6000_prepare_target(ar->arHifDevice, + targ_info.target_type, + targ_info.target_ver) != A_OK) { + init_status = A_ERROR; + goto avail_ev_failed; + } + + } + + if (ar6000_configure_target(ar) != A_OK) { + init_status = A_ERROR; + goto avail_ev_failed; + } + + A_MEMZERO(&htcInfo,sizeof(htcInfo)); + htcInfo.pContext = ar; + htcInfo.TargetFailure = ar6000_target_failure; + + ar->arHtcTarget = HTCCreate(ar->arHifDevice,&htcInfo); + + if (ar->arHtcTarget == NULL) { + init_status = A_ERROR; + goto avail_ev_failed; + } + + spin_lock_init(&ar->arLock); + +#ifdef WAPI_ENABLE + ar->arWapiEnable = 0; +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) + dev->open = &ar6000_open; + dev->stop = &ar6000_close; + dev->hard_start_xmit = &ar6000_data_tx; + dev->get_stats = &ar6000_get_stats; + + /* dev->tx_timeout = ar6000_tx_timeout; */ + dev->do_ioctl = &ar6000_ioctl; +#else + dev->netdev_ops = &ar6000_netdev_ops; +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) */ + dev->watchdog_timeo = AR6000_TX_TIMEOUT; + dev->wireless_handlers = &ath_iw_handler_def; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + dev->get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#else + ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */ +#endif +#ifdef CONFIG_CHECKSUM_OFFLOAD + if(csumOffload){ + + dev->features |= NETIF_F_IP_CSUM;/*advertise kernel capability + to do TCP/UDP CSUM offload for IPV4*/ + ar->rxMetaVersion=WMI_META_VERSION_2;/*if external frame work is also needed, change and use an extended rxMetaVerion*/ + } +#endif + if (processDot11Hdr) { + dev->hard_header_len = sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN + WMI_MAX_TX_META_SZ + LINUX_HACK_FUDGE_FACTOR; + } else { + /* + * We need the OS to provide us with more headroom in order to + * perform dix to 802.3, WMI header encap, and the HTC header + */ + dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) + + sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN + WMI_MAX_TX_META_SZ + LINUX_HACK_FUDGE_FACTOR; + } + +#ifdef ATH_AR6K_11N_SUPPORT + if((ar->aggr_cntxt = aggr_init(ar6000_alloc_netbufs)) == NULL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize aggr.\n", __func__)); + init_status = A_ERROR; + goto avail_ev_failed; + } + + aggr_register_rx_dispatcher(ar->aggr_cntxt, (void *)dev, ar6000_deliver_frames_to_nw_stack); +#endif + + HIFClaimDevice(ar->arHifDevice, ar); + + /* We only register the device in the global list if we succeed. */ + /* If the device is in the global list, it will be destroyed */ + /* when the module is unloaded. */ + ar6000_devices[device_index] = dev; + + /* Don't install the init function if BMI is requested */ + if (!bmienable) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) + dev->init = ar6000_init; +#else + ar6000_netdev_ops.ndo_init = ar6000_init; +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) */ + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("BMI enabled: %d\n", wlaninitmode)); + if ((wlaninitmode == WLAN_INIT_MODE_UDEV) || + (wlaninitmode == WLAN_INIT_MODE_DRV)) + { + A_STATUS status = A_OK; + do { + A_BOOL rtnl_lock_grabbed; + if ((status = ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n")); + break; + } +#ifdef HTC_RAW_INTERFACE + if (bypasswmi) { + A_UINT32 param = 1; + status = BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data_initialized), + (A_UCHAR *)¶m, 4); + break; + } +#endif + rtnl_lock_grabbed = rtnl_trylock(); + status = (ar6000_init(dev)==0) ? A_OK : A_ERROR; + if (rtnl_lock_grabbed) { + rtnl_unlock(); /* we locked it above, so unlock it here */ + } + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_init\n")); + } + } while (FALSE); + + if (status != A_OK) { + init_status = status; + goto avail_ev_failed; + } + } + } + + /* This runs the init function if registered */ + if (register_netdev(dev)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: register_netdev failed\n")); + ar6000_destroy(dev, 0); + return A_ERROR; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_avail: name=%s hifdevice=0x%x, dev=0x%x (%d), ar=0x%x\n", + dev->name, (A_UINT32)ar->arHifDevice, (A_UINT32)dev, device_index, + (A_UINT32)ar)); + +avail_ev_failed : + if (A_FAILED(init_status)) { + if (bmienable) { + ar6000_sysfs_bmi_deinit(ar); + } + } + + return init_status; +} + +static void ar6000_target_failure(void *Instance, A_STATUS Status) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance; + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + static A_BOOL sip = FALSE; + + if (Status != A_OK) { + + printk(KERN_ERR "ar6000_target_failure: target asserted \n"); + + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + + /* try dumping target assertion information (if any) */ + ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType); + + /* + * Fetch the logs from the target via the diagnostic + * window. + */ + ar6000_dbglog_get_debug_logs(ar); + + /* Report the error only once */ + if (!sip) { + sip = TRUE; + errEvent.errorVal = WMI_TARGET_COM_ERR | + WMI_TARGET_FATAL_ERR; + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + } + } +} + +static A_STATUS +ar6000_unavail_ev(void *context, void *hif_handle) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)context; + /* NULL out it's entry in the global list */ + ar6000_devices[ar->arDeviceIndex] = NULL; + ar6000_destroy(ar->arNetDev, 1); + + return A_OK; +} + +void +ar6000_stop_endpoint(struct net_device *dev, A_BOOL keepprofile) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T*)netdev_priv(dev); + /* Stop the transmit queues */ + netif_stop_queue(dev); + + /* Disable the target and the interrupts associated with it */ + if (ar->arWmiReady == TRUE) + { + if (!bypasswmi) + { + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): Disconnect\n", __func__)); +#ifdef ANDROID_ENV + if (keepprofile) { + wmi_disconnect_cmd(ar->arWmi); + } else +#endif /* ANDROID_ENV */ + { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar6000_init_profile_info(ar); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } + } + A_UNTIMEOUT(&ar->disconnect_timer); + ar->arWmiReady = FALSE; + ar->arConnected = FALSE; + ar->arConnectPending = FALSE; + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + ar->arWlanState = WLAN_ENABLED; +#ifdef USER_KEYS + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; +#endif + } + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI stopped\n", __func__)); + } + else + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI not ready 0x%08x 0x%08x\n", + __func__, (unsigned int) ar, (unsigned int) ar->arWmi)); + + /* Shut down WMI if we have started it */ + if(ar->arWmiEnabled == TRUE) + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): Shut down WMI\n", __func__)); + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + } + + if (ar->arHtcTarget != NULL) { +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + if (NULL != ar6kHciTransCallbacks.cleanupTransport) { + ar6kHciTransCallbacks.cleanupTransport(NULL); + } +#else + // FIXME: workaround to reset BT's UART baud rate to default + if (NULL != ar->exitCallback) { + AR3K_CONFIG_INFO ar3kconfig; + A_STATUS status; + + A_MEMZERO(&ar3kconfig,sizeof(ar3kconfig)); + ar6000_set_default_ar3kconfig(ar, (void *)&ar3kconfig); + status = ar->exitCallback(&ar3kconfig); + if (A_OK != status) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to reset AR3K baud rate! \n")); + } + } + // END workaround + ar6000_cleanup_hci(ar); +#endif + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Shutting down HTC .... \n")); + /* stop HTC */ + HTCStop(ar->arHtcTarget); + } + + if (resetok) { + /* try to reset the device if we can + * The driver may have been configure NOT to reset the target during + * a debug session */ + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Attempting to reset target on instance destroy.... \n")); + if (ar->arHifDevice != NULL) { + /* WAR for AR6003 cannot do without cold reset */ + A_BOOL coldReset = (ar->arTargetType==TARGET_TYPE_AR6003) ? TRUE : FALSE; + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE, coldReset); + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Host does not want target reset. \n")); + } + /* Done with cookies */ + ar6000_cookie_cleanup(ar); +} +/* + * We need to differentiate between the surprise and planned removal of the + * device because of the following consideration: + * - In case of surprise removal, the hcd already frees up the pending + * for the device and hence there is no need to unregister the function + * driver inorder to get these requests. For planned removal, the function + * driver has to explictly unregister itself to have the hcd return all the + * pending requests before the data structures for the devices are freed up. + * Note that as per the current implementation, the function driver will + * end up releasing all the devices since there is no API to selectively + * release a particular device. + * - Certain commands issued to the target can be skipped for surprise + * removal since they will anyway not go through. + */ +void +ar6000_destroy(struct net_device *dev, unsigned int unregister) +{ + AR_SOFTC_T *ar; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("+ar6000_destroy \n")); + + if((dev == NULL) || ((ar = ar6k_priv(dev)) == NULL)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s(): Failed to get device structure.\n", __func__)); + return; + } + + ar->bIsDestroyProgress = TRUE; + + if (down_interruptible(&ar->arSem)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s(): down_interruptible failed \n", __func__)); + return; + } + if (ar->arWmiReady && !bypasswmi) { + ar6000_dbglog_get_debug_logs(ar); + } +#ifdef ANDROID_ENV + if (!android_ar6k_endpoint_is_stop(ar)) { +#else + if (1) { +#endif + /* only stop endpoint if we are not stop it in suspend_ev */ + ar6000_stop_endpoint(dev, FALSE); + } + if (ar->arHtcTarget != NULL) { + /* destroy HTC */ + HTCDestroy(ar->arHtcTarget); + } + if (ar->arHifDevice != NULL) { + /*release the device so we do not get called back on remove incase we + * we're explicity destroyed by module unload */ + HIFReleaseDevice(ar->arHifDevice); + HIFShutDownDevice(ar->arHifDevice); + } +#ifdef ATH_AR6K_11N_SUPPORT + aggr_module_destroy(ar->aggr_cntxt); +#endif + + /* Done with cookies */ + ar6000_cookie_cleanup(ar); + + /* cleanup any allocated AMSDU buffers */ + ar6000_cleanup_amsdu_rxbufs(ar); + + if (bmienable) { + ar6000_sysfs_bmi_deinit(ar); + } + + /* Cleanup BMI */ + BMIInit(); + + /* Clear the tx counters */ + memset(tx_attempt, 0, sizeof(tx_attempt)); + memset(tx_post, 0, sizeof(tx_post)); + memset(tx_complete, 0, sizeof(tx_complete)); + +#ifdef HTC_RAW_INTERFACE + if (ar->arRawHtc) { + A_FREE(ar->arRawHtc); + ar->arRawHtc = NULL; + } +#endif + /* Free up the device data structure */ + if( unregister ) + unregister_netdev(dev); +#ifndef free_netdev + kfree(dev); +#else + free_netdev(dev); +#endif + +#ifdef ATH6K_CONFIG_CFG80211 + ar6k_cfg80211_deinit(ar); +#endif /* ATH6K_CONFIG_CFG80211 */ + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("-ar6000_destroy \n")); +} + +static void disconnect_timer_handler(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + A_UNTIMEOUT(&ar->disconnect_timer); + + ar6000_init_profile_info(ar); + wmi_disconnect_cmd(ar->arWmi); +} + +static void ar6000_detect_error(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *)ptr; + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_TARGET_ERROR_REPORT_EVENT errEvent; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (ar->arHBChallengeResp.outstanding) { + ar->arHBChallengeResp.missCnt++; + } else { + ar->arHBChallengeResp.missCnt = 0; + } + + if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) { + /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */ + ar->arHBChallengeResp.missCnt = 0; + ar->arHBChallengeResp.seqNum = 0; + errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID, + (A_UINT8 *)&errEvent, + sizeof(WMI_TARGET_ERROR_REPORT_EVENT)); + return; + } + + /* Generate the sequence number for the next challenge */ + ar->arHBChallengeResp.seqNum++; + ar->arHBChallengeResp.outstanding = TRUE; + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to send heart beat challenge\n")); + } + + + /* Reschedule the timer for the next challenge */ + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); +} + +void ar6000_init_profile_info(AR_SOFTC_T *ar) +{ + ar->arSsidLen = 0; + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + + switch(fwmode) { + case HI_OPTION_FW_MODE_IBSS: + ar->arNetworkType = ar->arNextMode = ADHOC_NETWORK; + break; + case HI_OPTION_FW_MODE_BSS_STA: + ar->arNetworkType = ar->arNextMode = INFRA_NETWORK; + break; + case HI_OPTION_FW_MODE_AP: + ar->arNetworkType = ar->arNextMode = AP_NETWORK; + break; + } + + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arConnected = FALSE; +} + +static void +ar6000_init_control_info(AR_SOFTC_T *ar) +{ + ar->arWmiEnabled = FALSE; + ar6000_init_profile_info(ar); + ar->arDefTxKeyIndex = 0; + A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList)); + ar->arChannelHint = 0; + ar->arListenInterval = A_DEFAULT_LISTEN_INTERVAL; + ar->arVersion.host_ver = AR6K_SW_VERSION; + ar->arRssi = 0; + ar->arTxPwr = 0; + ar->arTxPwrSet = FALSE; + ar->arSkipScan = 0; + ar->arBeaconInterval = 0; + ar->arBitRate = 0; + ar->arMaxRetries = 0; + ar->arWmmEnabled = TRUE; + ar->intra_bss = 1; + ar->scan_complete = 1; + A_MEMZERO(&ar->scParams, sizeof(ar->scParams)); + ar->scParams.shortScanRatio = WMI_SHORTSCANRATIO_DEFAULT; + ar->scParams.scanCtrlFlags = DEFAULT_SCAN_CTRL_FLAGS; + + /* Initialize the AP mode state info */ + { + A_UINT8 ctr; + A_MEMZERO((A_UINT8 *)ar->sta_list, AP_MAX_NUM_STA * sizeof(sta_t)); + + /* init the Mutexes */ + A_MUTEX_INIT(&ar->mcastpsqLock); + + /* Init the PS queues */ + for (ctr=0; ctr < AP_MAX_NUM_STA ; ctr++) { + A_MUTEX_INIT(&ar->sta_list[ctr].psqLock); + A_NETBUF_QUEUE_INIT(&ar->sta_list[ctr].psq); + } + + ar->ap_profile_flag = 0; + A_NETBUF_QUEUE_INIT(&ar->mcastpsq); + + A_MEMCPY(ar->ap_country_code, DEF_AP_COUNTRY_CODE, 3); + ar->ap_wmode = DEF_AP_WMODE_G; + ar->ap_dtim_period = DEF_AP_DTIM; + ar->ap_beacon_interval = DEF_BEACON_INTERVAL; + } +} + +static int +ar6000_open(struct net_device *dev) +{ + unsigned long flags; + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + spin_lock_irqsave(&ar->arLock, flags); + +#ifndef ANDROID_ENV + if(ar->arWlanState == WLAN_DISABLED) { + ar->arWlanState = WLAN_ENABLED; + } +#endif + + if( ar->arConnected || bypasswmi) { + netif_carrier_on(dev); + /* Wake up the queues */ + netif_wake_queue(dev); + } + else + netif_carrier_off(dev); + + spin_unlock_irqrestore(&ar->arLock, flags); + return 0; +} + +static int +ar6000_close(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + netif_stop_queue(dev); + +#ifdef ANDROID_ENV + (void)ar; /* do nothing. Android SDK will handle it */ +#else + AR6000_SPIN_LOCK(&ar->arLock, 0); + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } else { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + if(ar->arWmiReady == TRUE) { + if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, + 0, 0, 0, 0, 0, 0, 0, 0) != A_OK) { + return -EIO; + } + ar->arWlanState = WLAN_DISABLED; + } +#endif + return 0; +} + +/* connect to a service */ +static A_STATUS ar6000_connectservice(AR_SOFTC_T *ar, + HTC_SERVICE_CONNECT_REQ *pConnect, + char *pDesc) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + + do { + + A_MEMZERO(&response,sizeof(response)); + + status = HTCConnectService(ar->arHtcTarget, + pConnect, + &response); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" Failed to connect to %s service status:%d \n", + pDesc, status)); + break; + } + switch (pConnect->ServiceID) { + case WMI_CONTROL_SVC : + if (ar->arWmiEnabled) { + /* set control endpoint for WMI use */ + wmi_set_control_ep(ar->arWmi, response.Endpoint); + } + /* save EP for fast lookup */ + ar->arControlEp = response.Endpoint; + break; + case WMI_DATA_BE_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BE, response.Endpoint); + break; + case WMI_DATA_BK_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_BK, response.Endpoint); + break; + case WMI_DATA_VI_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VI, response.Endpoint); + break; + case WMI_DATA_VO_SVC : + arSetAc2EndpointIDMap(ar, WMM_AC_VO, response.Endpoint); + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ServiceID not mapped %d\n", pConnect->ServiceID)); + status = A_EINVAL; + break; + } + + } while (FALSE); + + return status; +} + +void ar6000_TxDataCleanup(AR_SOFTC_T *ar) +{ + /* flush all the data (non-control) streams + * we only flush packets that are tagged as data, we leave any control packets that + * were in the TX queues alone */ + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BE), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_BK), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VI), + AR6K_DATA_PKT_TAG); + HTCFlushEndpoint(ar->arHtcTarget, + arAc2EndpointID(ar, WMM_AC_VO), + AR6K_DATA_PKT_TAG); +} + +HTC_ENDPOINT_ID +ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arAc2EndpointID(ar, ac)); +} + +A_UINT8 +ar6000_endpoint_id2_ac(void * devt, HTC_ENDPOINT_ID ep ) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *) devt; + return(arEndpoint2Ac(ar, ep )); +} + +/* This function does one time initialization for the lifetime of the device */ +int ar6000_init(struct net_device *dev) +{ + AR_SOFTC_T *ar; + A_STATUS status; + A_INT32 timeleft; + A_INT16 i; + int ret = 0; +#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE) + WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD sbcb_cmd; + WMI_SET_BTCOEX_FE_ANT_CMD sbfa_cmd; +#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */ + + dev_hold(dev); + rtnl_unlock(); + + if((ar = ar6k_priv(dev)) == NULL) + { + ret = -EIO; + goto ar6000_init_done; + } + + if (enablerssicompensation) { + read_rssi_compensation_param(ar); + for (i=-95; i<=0; i++) { + rssi_compensation_table[0-i] = rssi_compensation_calc(ar,i); + } + } + + /* Do we need to finish the BMI phase */ + if ((wlaninitmode == WLAN_INIT_MODE_USR) && (BMIDone(ar->arHifDevice) != A_OK)) + { + ret = -EIO; + goto ar6000_init_done; + } + + if (!bypasswmi) + { +#if 0 /* TBDXXX */ + if (ar->arVersion.host_ver != ar->arVersion.target_ver) { + A_PRINTF("WARNING: Host version 0x%x does not match Target " + " version 0x%x!\n", + ar->arVersion.host_ver, ar->arVersion.target_ver); + } +#endif + + /* Indicate that WMI is enabled (although not ready yet) */ + ar->arWmiEnabled = TRUE; + if ((ar->arWmi = wmi_init((void *) ar)) == NULL) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize WMI.\n", __func__)); + ret = -EIO; + goto ar6000_init_done; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Got WMI @ 0x%08x.\n", __func__, + (unsigned int) ar->arWmi)); + } + + do { + HTC_SERVICE_CONNECT_REQ connect; + + /* the reason we have to wait for the target here is that the driver layer + * has to init BMI in order to set the host block size, + */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + break; + } + + A_MEMZERO(&connect,sizeof(connect)); + /* meta data is unused for now */ + connect.pMetaData = NULL; + connect.MetaDataLength = 0; + /* these fields are the same for all service endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxCompleteMultiple = ar6000_tx_complete; + connect.EpCallbacks.EpRecv = ar6000_rx; + connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill; + connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full; + /* set the max queue depth so that our ar6000_tx_queue_full handler gets called. + * Linux has the peculiarity of not providing flow control between the + * NIC and the network stack. There is no API to indicate that a TX packet + * was sent which could provide some back pressure to the network stack. + * Under linux you would have to wait till the network stack consumed all sk_buffs + * before any back-flow kicked in. Which isn't very friendly. + * So we have to manage this ourselves */ + connect.MaxSendQueueDepth = MAX_DEFAULT_SEND_QUEUE_DEPTH; + connect.EpCallbacks.RecvRefillWaterMark = AR6000_MAX_RX_BUFFERS / 4; /* set to 25 % */ + if (0 == connect.EpCallbacks.RecvRefillWaterMark) { + connect.EpCallbacks.RecvRefillWaterMark++; + } + /* connect to control service */ + connect.ServiceID = WMI_CONTROL_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI CONTROL"); + if (A_FAILED(status)) { + break; + } + + connect.LocalConnectionFlags |= HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING; + /* limit the HTC message size on the send path, although we can receive A-MSDU frames of + * 4K, we will only send ethernet-sized (802.3) frames on the send path. */ + connect.MaxSendMsgSize = WMI_MAX_TX_DATA_FRAME_LENGTH; + + /* to reduce the amount of committed memory for larger A_MSDU frames, use the recv-alloc threshold + * mechanism for larger packets */ + connect.EpCallbacks.RecvAllocThreshold = AR6000_BUFFER_SIZE; + connect.EpCallbacks.EpRecvAllocThresh = ar6000_alloc_amsdu_rxbuf; + + /* for the remaining data services set the connection flag to reduce dribbling, + * if configured to do so */ + if (reduce_credit_dribble) { + connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE; + /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value + * of 0-3 */ + connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + connect.ConnectionFlags |= + ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK; + } + /* connect to best-effort service */ + connect.ServiceID = WMI_DATA_BE_SVC; + + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BE"); + if (A_FAILED(status)) { + break; + } + + /* connect to back-ground + * map this to WMI LOW_PRI */ + connect.ServiceID = WMI_DATA_BK_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA BK"); + if (A_FAILED(status)) { + break; + } + + /* connect to Video service, map this to + * to HI PRI */ + connect.ServiceID = WMI_DATA_VI_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VI"); + if (A_FAILED(status)) { + break; + } + + /* connect to VO service, this is currently not + * mapped to a WMI priority stream due to historical reasons. + * WMI originally defined 3 priorities over 3 mailboxes + * We can change this when WMI is reworked so that priorities are not + * dependent on mailboxes */ + connect.ServiceID = WMI_DATA_VO_SVC; + status = ar6000_connectservice(ar, + &connect, + "WMI DATA VO"); + if (A_FAILED(status)) { + break; + } + + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BE) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_BK) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VI) != 0); + A_ASSERT(arAc2EndpointID(ar,WMM_AC_VO) != 0); + + /* setup access class priority mappings */ + ar->arAcStreamPriMap[WMM_AC_BK] = 0; /* lowest */ + ar->arAcStreamPriMap[WMM_AC_BE] = 1; /* */ + ar->arAcStreamPriMap[WMM_AC_VI] = 2; /* */ + ar->arAcStreamPriMap[WMM_AC_VO] = 3; /* highest */ + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + if (setuphci && (NULL != ar6kHciTransCallbacks.setupTransport)) { + HCI_TRANSPORT_MISC_HANDLES hciHandles; + + hciHandles.netDevice = ar->arNetDev; + hciHandles.hifDevice = ar->arHifDevice; + hciHandles.htcHandle = ar->arHtcTarget; + status = (A_STATUS)(ar6kHciTransCallbacks.setupTransport(&hciHandles)); + } +#else + if (setuphci) { + /* setup HCI */ + status = ar6000_setup_hci(ar); + } +#endif + + } while (FALSE); + + if (A_FAILED(status)) { + ret = -EIO; + goto ar6000_init_done; + } + + /* + * give our connected endpoints some buffers + */ + + ar6000_rx_refill(ar, ar->arControlEp); + ar6000_rx_refill(ar, arAc2EndpointID(ar,WMM_AC_BE)); + + /* + * We will post the receive buffers only for SPE or endpoint ping testing so we are + * making it conditional on the 'bypasswmi' flag. + */ + if (bypasswmi) { + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_BK)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VI)); + ar6000_rx_refill(ar,arAc2EndpointID(ar,WMM_AC_VO)); + } + + /* allocate some buffers that handle larger AMSDU frames */ + ar6000_refill_amsdu_rxbufs(ar,AR6000_MAX_AMSDU_RX_BUFFERS); + + /* setup credit distribution */ + ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo); + + /* Since cookies are used for HTC transports, they should be */ + /* initialized prior to enabling HTC. */ + ar6000_cookie_init(ar); + + /* start HTC */ + status = HTCStart(ar->arHtcTarget); + + if (status != A_OK) { + if (ar->arWmiEnabled == TRUE) { + wmi_shutdown(ar->arWmi); + ar->arWmiEnabled = FALSE; + ar->arWmi = NULL; + } + ar6000_cookie_cleanup(ar); + ret = -EIO; + goto ar6000_init_done; + } + + if (!bypasswmi) { + /* Wait for Wmi event to be ready */ + timeleft = wait_event_interruptible_timeout(arEvent, + (ar->arWmiReady == TRUE), wmitimeout * HZ); + + if(!timeleft || signal_pending(current)) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI is not ready or wait was interrupted\n")); + ret = -EIO; + goto ar6000_init_done; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() WMI is ready\n", __func__)); + + /* Communicate the wmi protocol verision to the target */ + if ((ar6000_set_host_app_area(ar)) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set the host app area\n")); + } + + /* configure the device for rx dot11 header rules 0,0 are the default values + * therefore this command can be skipped if the inputs are 0,FALSE,FALSE.Required + if checksum offload is needed. Set RxMetaVersion to 2*/ + if ((wmi_set_rx_frame_format_cmd(ar->arWmi,ar->rxMetaVersion, processDot11Hdr, processDot11Hdr)) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set the rx frame format.\n")); + } + +#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE) + /* Configure the type of BT collocated with WLAN */ + A_MEMZERO(&sbcb_cmd, sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD)); +#ifdef CONFIG_AR600x_BT_QCOM + sbcb_cmd.btcoexCoLocatedBTdev = 1; +#elif defined(CONFIG_AR600x_BT_CSR) + sbcb_cmd.btcoexCoLocatedBTdev = 2; +#elif defined(CONFIG_AR600x_BT_AR3001) + sbcb_cmd.btcoexCoLocatedBTdev = 3; +#else +#error Unsupported Bluetooth Type +#endif /* Collocated Bluetooth Type */ + + if ((wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &sbcb_cmd)) != A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set collocated BT type\n")); + } + + /* Configure the type of BT collocated with WLAN */ + A_MEMZERO(&sbfa_cmd, sizeof(WMI_SET_BTCOEX_FE_ANT_CMD)); +#ifdef CONFIG_AR600x_DUAL_ANTENNA + sbfa_cmd.btcoexFeAntType = 2; +#elif defined(CONFIG_AR600x_SINGLE_ANTENNA) + sbfa_cmd.btcoexFeAntType = 1; +#else +#error Unsupported Front-End Antenna Configuration +#endif /* AR600x Front-End Antenna Configuration */ + + if ((wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &sbfa_cmd)) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set fornt end antenna configuration\n")); + } +#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */ + } + + ar->arNumDataEndPts = 1; + + if (bypasswmi) { + /* for tests like endpoint ping, the MAC address needs to be non-zero otherwise + * the data path through a raw socket is disabled */ + dev->dev_addr[0] = 0x00; + dev->dev_addr[1] = 0x01; + dev->dev_addr[2] = 0x02; + dev->dev_addr[3] = 0xAA; + dev->dev_addr[4] = 0xBB; + dev->dev_addr[5] = 0xCC; + } + +#ifdef ANDROID_ENV + android_ar6k_start(ar); +#endif + +ar6000_init_done: + rtnl_lock(); + dev_put(dev); + + return ret; +} + + +void +ar6000_bitrate_rx(void *devt, A_INT32 rateKbps) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arBitRate = rateKbps; + wake_up(&arEvent); +} + +void +ar6000_ratemask_rx(void *devt, A_UINT32 ratemask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arRateMask = ratemask; + wake_up(&arEvent); +} + +void +ar6000_txPwr_rx(void *devt, A_UINT8 txPwr) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arTxPwr = txPwr; + wake_up(&arEvent); +} + + +void +ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16)); + ar->arNumChannels = numChan; + + wake_up(&arEvent); +} + +A_UINT8 +ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_UINT8 *datap; + ATH_MAC_HDR *macHdr; + A_UINT32 i, eptMap; + + (*mapNo) = 0; + datap = A_NETBUF_DATA(skb); + macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR)); + if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) { + return ENDPOINT_2; + } + + eptMap = -1; + for (i = 0; i < ar->arNodeNum; i ++) { + if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) { + (*mapNo) = i + 1; + ar->arNodeMap[i].txPending ++; + return ar->arNodeMap[i].epId; + } + + if ((eptMap == -1) && !ar->arNodeMap[i].txPending) { + eptMap = i; + } + } + + if (eptMap == -1) { + eptMap = ar->arNodeNum; + ar->arNodeNum ++; + A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM); + } + + A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN); + + for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) { + if (!ar->arTxPending[i]) { + ar->arNodeMap[eptMap].epId = i; + break; + } + // No free endpoint is available, start redistribution on the inuse endpoints. + if (i == ENDPOINT_5) { + ar->arNodeMap[eptMap].epId = ar->arNexEpId; + ar->arNexEpId ++; + if (ar->arNexEpId > ENDPOINT_5) { + ar->arNexEpId = ENDPOINT_2; + } + } + } + + (*mapNo) = eptMap + 1; + ar->arNodeMap[eptMap].txPending ++; + + return ar->arNodeMap[eptMap].epId; +} + +#ifdef DEBUG +static void ar6000_dump_skb(struct sk_buff *skb) +{ + u_char *ch; + for (ch = A_NETBUF_DATA(skb); + (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) + + A_NETBUF_LEN(skb)); ch++) + { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("%2.2x ", *ch)); + } + AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("\n")); +} +#endif + +#ifdef HTC_TEST_SEND_PKTS +static void DoHTCSendPktsTest(AR_SOFTC_T *ar, int MapNo, HTC_ENDPOINT_ID eid, struct sk_buff *skb); +#endif + +static int +ar6000_data_tx(struct sk_buff *skb, struct net_device *dev) +{ +#define AC_NOT_MAPPED 99 + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_UINT8 ac = AC_NOT_MAPPED; + HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED; + A_UINT32 mapNo = 0; + int len; + struct ar_cookie *cookie; + A_BOOL checkAdHocPsMapping = FALSE,bMoreData = FALSE; + HTC_TX_TAG htc_tag = AR6K_DATA_PKT_TAG; + A_UINT8 dot11Hdr = processDot11Hdr; +#ifdef CONFIG_PM + if (ar->arWowState) { + A_NETBUF_FREE(skb); + return 0; + } +#endif /* CONFIG_PM */ +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13) + skb->list = NULL; +#endif + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n", + (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb))); + + /* If target is not associated */ + if( (!ar->arConnected && !bypasswmi) +#ifdef CONFIG_HOST_TCMD_SUPPORT + /* TCMD doesnt support any data, free the buf and return */ + || (ar->arTargetMode == AR6000_TCMD_MODE) +#endif + ) { + A_NETBUF_FREE(skb); + return 0; + } + + do { + + if (ar->arWmiReady == FALSE && bypasswmi == 0) { + break; + } + +#ifdef BLOCK_TX_PATH_FLAG + if (blocktx) { + break; + } +#endif /* BLOCK_TX_PATH_FLAG */ + + /* AP mode Power save processing */ + /* If the dst STA is in sleep state, queue the pkt in its PS queue */ + + if (ar->arNetworkType == AP_NETWORK) { + ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb); + sta_t *conn = NULL; + + /* If the dstMac is a Multicast address & atleast one of the + * associated STA is in PS mode, then queue the pkt to the + * mcastq + */ + if (IEEE80211_IS_MULTICAST(datap->dstMac)) { + A_UINT8 ctr=0; + A_BOOL qMcast=FALSE; + + + for (ctr=0; ctrsta_list[ctr]))) { + qMcast = TRUE; + } + } + if(qMcast) { + + /* If this transmit is not because of a Dtim Expiry q it */ + if (ar->DTIMExpired == FALSE) { + A_BOOL isMcastqEmpty = FALSE; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + isMcastqEmpty = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq); + A_NETBUF_ENQUEUE(&ar->mcastpsq, skb); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* If this is the first Mcast pkt getting queued + * indicate to the target to set the BitmapControl LSB + * of the TIM IE. + */ + if (isMcastqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 1); + } + return 0; + } else { + /* This transmit is because of Dtim expiry. Determine if + * MoreData bit has to be set. + */ + A_MUTEX_LOCK(&ar->mcastpsqLock); + if(!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + bMoreData = TRUE; + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + } + } else { + conn = ieee80211_find_conn(ar, datap->dstMac); + if (conn) { + if (STA_IS_PWR_SLEEP(conn)) { + /* If this transmit is not because of a PsPoll q it*/ + if (!STA_IS_PS_POLLED(conn)) { + A_BOOL isPsqEmpty = FALSE; + /* Queue the frames if the STA is sleeping */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_NETBUF_ENQUEUE(&conn->psq, skb); + A_MUTEX_UNLOCK(&conn->psqLock); + + /* If this is the first pkt getting queued + * for this STA, update the PVB for this STA + */ + if (isPsqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 1); + } + + return 0; + } else { + /* This tx is because of a PsPoll. Determine if + * MoreData bit has to be set + */ + A_MUTEX_LOCK(&conn->psqLock); + if (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) { + bMoreData = TRUE; + } + A_MUTEX_UNLOCK(&conn->psqLock); + } + } + } else { + + /* non existent STA. drop the frame */ + A_NETBUF_FREE(skb); + return 0; + } + } + } + + if (ar->arWmiEnabled) { +#ifdef CONFIG_CHECKSUM_OFFLOAD + A_UINT8 csumStart=0; + A_UINT8 csumDest=0; + A_UINT8 csum=skb->ip_summed; + if(csumOffload && (csum==CHECKSUM_PARTIAL)){ + csumStart=skb->csum_start-(skb->network_header-skb->head)+sizeof(ATH_LLC_SNAP_HDR); + csumDest=skb->csum_offset+csumStart; + } +#endif + if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len - LINUX_HACK_FUDGE_FACTOR) { + struct sk_buff *newbuf; + + /* + * We really should have gotten enough headroom but sometimes + * we still get packets with not enough headroom. Copy the packet. + */ + len = A_NETBUF_LEN(skb); + newbuf = A_NETBUF_ALLOC(len); + if (newbuf == NULL) { + break; + } + A_NETBUF_PUT(newbuf, len); + A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len); + A_NETBUF_FREE(skb); + skb = newbuf; + /* fall through and assemble header */ + } + + if (dot11Hdr) { + if (wmi_dot11_hdr_add(ar->arWmi,skb,ar->arNetworkType) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx-wmi_dot11_hdr_add failed\n")); + break; + } + } else { + if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_dix_2_dot3 failed\n")); + break; + } + } +#ifdef CONFIG_CHECKSUM_OFFLOAD + if(csumOffload && (csum ==CHECKSUM_PARTIAL)){ + WMI_TX_META_V2 metaV2; + metaV2.csumStart =csumStart; + metaV2.csumDest = csumDest; + metaV2.csumFlags = 0x1;/*instruct target to calculate checksum*/ + if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr, + WMI_META_VERSION_2,&metaV2) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n")); + break; + } + + } + else +#endif + { + if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr,0,NULL) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n")); + break; + } + } + + + if ((ar->arNetworkType == ADHOC_NETWORK) && + ar->arIbssPsEnable && ar->arConnected) { + /* flag to check adhoc mapping once we take the lock below: */ + checkAdHocPsMapping = TRUE; + + } else { + /* get the stream mapping */ + ac = wmi_implicit_create_pstream(ar->arWmi, skb, 0, ar->arWmmEnabled); + } + + } else { + EPPING_HEADER *eppingHdr; + + eppingHdr = A_NETBUF_DATA(skb); + + if (IS_EPPING_PACKET(eppingHdr)) { + /* the stream ID is mapped to an access class */ + ac = eppingHdr->StreamNo_h; + /* some EPPING packets cannot be dropped no matter what access class it was + * sent on. We can change the packet tag to guarantee it will not get dropped */ + if (IS_EPING_PACKET_NO_DROP(eppingHdr)) { + htc_tag = AR6K_CONTROL_PKT_TAG; + } + + if (ac == HCI_TRANSPORT_STREAM_NUM) { + /* pass this to HCI */ +#ifndef EXPORT_HCI_BRIDGE_INTERFACE + if (A_SUCCESS(hci_test_send(ar,skb))) { + return 0; + } +#endif + /* set AC to discard this skb */ + ac = AC_NOT_MAPPED; + } else { + /* a quirk of linux, the payload of the frame is 32-bit aligned and thus the addition + * of the HTC header will mis-align the start of the HTC frame, so we add some + * padding which will be stripped off in the target */ + if (EPPING_ALIGNMENT_PAD > 0) { + A_NETBUF_PUSH(skb, EPPING_ALIGNMENT_PAD); + } + } + + } else { + /* not a ping packet, drop it */ + ac = AC_NOT_MAPPED; + } + } + + } while (FALSE); + + /* did we succeed ? */ + if ((ac == AC_NOT_MAPPED) && !checkAdHocPsMapping) { + /* cleanup and exit */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + return 0; + } + + cookie = NULL; + + /* take the lock to protect driver data */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + if (checkAdHocPsMapping) { + eid = ar6000_ibss_map_epid(skb, dev, &mapNo); + }else { + eid = arAc2EndpointID (ar, ac); + } + /* validate that the endpoint is connected */ + if (eid == 0 || eid == ENDPOINT_UNUSED ) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" eid %d is NOT mapped!\n", eid)); + break; + } + /* allocate resource for this packet */ + cookie = ar6000_alloc_cookie(ar); + + if (cookie != NULL) { + /* update counts while the lock is held */ + ar->arTxPending[eid]++; + ar->arTotalTxDataPending++; + } + + } while (FALSE); + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)skb; + cookie->arc_bp[1] = mapNo; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb), + eid, + htc_tag); + +#ifdef DEBUG + if (debugdriver >= 3) { + ar6000_dump_skb(skb); + } +#endif +#ifdef HTC_TEST_SEND_PKTS + DoHTCSendPktsTest(ar,mapNo,eid,skb); +#endif + /* HTC interface is asynchronous, if this fails, cleanup will happen in + * the ar6000_tx_complete callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + } else { + /* no packet to send, cleanup */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + } + + return 0; +} + +int +ar6000_acl_data_tx(struct sk_buff *skb, struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + struct ar_cookie *cookie; + HTC_ENDPOINT_ID eid = ENDPOINT_UNUSED; + + cookie = NULL; + AR6000_SPIN_LOCK(&ar->arLock, 0); + + /* For now we send ACL on BE endpoint: We can also have a dedicated EP */ + eid = arAc2EndpointID (ar, 0); + /* allocate resource for this packet */ + cookie = ar6000_alloc_cookie(ar); + + if (cookie != NULL) { + /* update counts while the lock is held */ + ar->arTxPending[eid]++; + ar->arTotalTxDataPending++; + } + + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)skb; + cookie->arc_bp[1] = 0; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(skb), + A_NETBUF_LEN(skb), + eid, + AR6K_DATA_PKT_TAG); + + /* HTC interface is asynchronous, if this fails, cleanup will happen in + * the ar6000_tx_complete callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + } else { + /* no packet to send, cleanup */ + A_NETBUF_FREE(skb); + AR6000_STAT_INC(ar, tx_dropped); + AR6000_STAT_INC(ar, tx_aborted_errors); + } + return 0; +} + + +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL +static void +tvsub(register struct timeval *out, register struct timeval *in) +{ + if((out->tv_usec -= in->tv_usec) < 0) { + out->tv_sec--; + out->tv_usec += 1000000; + } + out->tv_sec -= in->tv_sec; +} + +void +applyAPTCHeuristics(AR_SOFTC_T *ar) +{ + A_UINT32 duration; + A_UINT32 numbytes; + A_UINT32 throughput; + struct timeval ts; + A_STATUS status; + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) { + do_gettimeofday(&ts); + tvsub(&ts, &aptcTR.samplingTS); + duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */ + numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived; + + if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) { + /* Initialize the time stamp and byte count */ + aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0; + do_gettimeofday(&aptcTR.samplingTS); + + /* Calculate and decide based on throughput thresholds */ + throughput = ((numbytes * 8) / duration); + if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) { + /* Disable Sleep and schedule a timer */ + A_ASSERT(ar->arWmiReady == TRUE); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER); + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0); + aptcTR.timerScheduled = TRUE; + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); +} +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + +static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + HTC_SEND_FULL_ACTION action = HTC_SEND_FULL_KEEP; + A_BOOL stopNet = FALSE; + HTC_ENDPOINT_ID Endpoint = HTC_GET_ENDPOINT_FROM_PKT(pPacket); + + do { + + if (bypasswmi) { + int accessClass; + + if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) { + /* don't drop special control packets */ + break; + } + + accessClass = arEndpoint2Ac(ar,Endpoint); + /* for endpoint ping testing drop Best Effort and Background */ + if ((accessClass == WMM_AC_BE) || (accessClass == WMM_AC_BK)) { + action = HTC_SEND_FULL_DROP; + stopNet = FALSE; + } else { + /* keep but stop the netqueues */ + stopNet = TRUE; + } + break; + } + + if (Endpoint == ar->arControlEp) { + /* under normal WMI if this is getting full, then something is running rampant + * the host should not be exhausting the WMI queue with too many commands + * the only exception to this is during testing using endpointping */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* set flag to handle subsequent messages */ + ar->arWMIControlEpFull = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI Control Endpoint is FULL!!! \n")); + /* no need to stop the network */ + stopNet = FALSE; + break; + } + + /* if we get here, we are dealing with data endpoints getting full */ + + if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_CONTROL_PKT_TAG) { + /* don't drop control packets issued on ANY data endpoint */ + break; + } + + if (ar->arNetworkType == ADHOC_NETWORK) { + /* in adhoc mode, we cannot differentiate traffic priorities so there is no need to + * continue, however we should stop the network */ + stopNet = TRUE; + break; + } + /* the last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for the highest + * active stream */ + if (ar->arAcStreamPriMap[arEndpoint2Ac(ar,Endpoint)] < ar->arHiAcStreamActivePri && + ar->arCookieCount <= MAX_HI_COOKIE_NUM) { + /* this stream's priority is less than the highest active priority, we + * give preference to the highest priority stream by directing + * HTC to drop the packet that overflowed */ + action = HTC_SEND_FULL_DROP; + /* since we are dropping packets, no need to stop the network */ + stopNet = FALSE; + break; + } + + } while (FALSE); + + if (stopNet) { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arNetQueueStopped = TRUE; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + /* one of the data endpoints queues is getting full..need to stop network stack + * the queue will resume in ar6000_tx_complete() */ + netif_stop_queue(ar->arNetDev); + } + + return action; +} + + +static void +ar6000_tx_complete(void *Context, HTC_PACKET_QUEUE *pPacketQueue) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + A_UINT32 mapNo = 0; + A_STATUS status; + struct ar_cookie * ar_cookie; + HTC_ENDPOINT_ID eid; + A_BOOL wakeEvent = FALSE; + struct sk_buff_head skb_queue; + HTC_PACKET *pPacket; + struct sk_buff *pktSkb; + A_BOOL flushing = FALSE; + + skb_queue_head_init(&skb_queue); + + /* lock the driver as we update internal state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + /* reap completed packets */ + while (!HTC_QUEUE_EMPTY(pPacketQueue)) { + + pPacket = HTC_PACKET_DEQUEUE(pPacketQueue); + + ar_cookie = (struct ar_cookie *)pPacket->pPktContext; + A_ASSERT(ar_cookie); + + status = pPacket->Status; + pktSkb = (struct sk_buff *)ar_cookie->arc_bp[0]; + eid = pPacket->Endpoint; + mapNo = ar_cookie->arc_bp[1]; + + A_ASSERT(pktSkb); + A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(pktSkb)); + + /* add this to the list, use faster non-lock API */ + __skb_queue_tail(&skb_queue,pktSkb); + + if (A_SUCCESS(status)) { + A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(pktSkb)); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x eid=%d ", + (A_UINT32)pktSkb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength, + eid)); + + ar->arTxPending[eid]--; + + if ((eid != ar->arControlEp) || bypasswmi) { + ar->arTotalTxDataPending--; + } + + if (eid == ar->arControlEp) + { + if (ar->arWMIControlEpFull) { + /* since this packet completed, the WMI EP is no longer full */ + ar->arWMIControlEpFull = FALSE; + } + + if (ar->arTxPending[eid] == 0) { + wakeEvent = TRUE; + } + } + + if (A_FAILED(status)) { + if (status == A_ECANCELED) { + /* a packet was flushed */ + flushing = TRUE; + } + AR6000_STAT_INC(ar, tx_errors); + if (status != A_NO_RESOURCE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() -TX ERROR, status: 0x%x\n", __func__, + status)); + } + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("OK\n")); + flushing = FALSE; + AR6000_STAT_INC(ar, tx_packets); + ar->arNetStats.tx_bytes += A_NETBUF_LEN(pktSkb); +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesTransmitted += a_netbuf_to_len(pktSkb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + } + + // TODO this needs to be looked at + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable + && (eid != ar->arControlEp) && mapNo) + { + mapNo --; + ar->arNodeMap[mapNo].txPending --; + + if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) { + A_UINT32 i; + for (i = ar->arNodeNum; i > 0; i --) { + if (!ar->arNodeMap[i - 1].txPending) { + A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping)); + ar->arNodeNum --; + } else { + break; + } + } + } + } + + ar6000_free_cookie(ar, ar_cookie); + + if (ar->arNetQueueStopped) { + ar->arNetQueueStopped = FALSE; + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + /* lock is released, we can freely call other kernel APIs */ + + /* free all skbs in our local list */ + while (!skb_queue_empty(&skb_queue)) { + /* use non-lock version */ + pktSkb = __skb_dequeue(&skb_queue); + A_NETBUF_FREE(pktSkb); + } + + if ((ar->arConnected == TRUE) || (bypasswmi)) { + if (!flushing) { + /* don't wake the queue if we are flushing, other wise it will just + * keep queueing packets, which will keep failing */ + netif_wake_queue(ar->arNetDev); + } + } + + if (wakeEvent) { + wake_up(&arEvent); + } + +} + +sta_t * +ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr) +{ + sta_t *conn = NULL; + A_UINT8 i, max_conn; + + switch(ar->arNetworkType) { + case AP_NETWORK: + max_conn = AP_MAX_NUM_STA; + break; + default: + max_conn=0; + break; + } + + for (i = 0; i < max_conn; i++) { + if (IEEE80211_ADDR_EQ(node_addr, ar->sta_list[i].mac)) { + conn = &ar->sta_list[i]; + break; + } + } + + return conn; +} + +sta_t *ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid) +{ + sta_t *conn = NULL; + A_UINT8 ctr; + + for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { + if (ar->sta_list[ctr].aid == aid) { + conn = &ar->sta_list[ctr]; + break; + } + } + return conn; +} + +/* + * Receive event handler. This is called by HTC when a packet is received + */ +int pktcount; +static void +ar6000_rx(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext; + int minHdrLen; + A_UINT8 containsDot11Hdr = 0; + A_STATUS status = pPacket->Status; + HTC_ENDPOINT_ID ept = pPacket->Endpoint; + + A_ASSERT((status != A_OK) || + (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN))); + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_rx ar=0x%x eid=%d, skb=0x%x, data=0x%x, len=0x%x status:%d", + (A_UINT32)ar, ept, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer, + pPacket->ActualLength, status)); + if (status != A_OK) { + if (status != A_ECANCELED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("RX ERR (%d) \n",status)); + } + } + + /* take lock to protect buffer counts + * and adaptive power throughput state */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + if (A_SUCCESS(status)) { + AR6000_STAT_INC(ar, rx_packets); + ar->arNetStats.rx_bytes += pPacket->ActualLength; +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL + aptcTR.bytesReceived += a_netbuf_to_len(skb); + applyAPTCHeuristics(ar); +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */ + + A_NETBUF_PUT(skb, pPacket->ActualLength + HTC_HEADER_LEN); + A_NETBUF_PULL(skb, HTC_HEADER_LEN); + +#ifdef DEBUG + if (debugdriver >= 2) { + ar6000_dump_skb(skb); + } +#endif /* DEBUG */ + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + skb->dev = ar->arNetDev; + if (status != A_OK) { + AR6000_STAT_INC(ar, rx_errors); + A_NETBUF_FREE(skb); + } else if (ar->arWmiEnabled == TRUE) { + if (ept == ar->arControlEp) { + /* + * this is a wmi control msg + */ +#ifdef ANDROID_ENV + android_ar6k_check_wow_status(ar); +#endif /* ANDROID_ENV */ + wmi_control_rx(ar->arWmi, skb); + } else { + WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(skb); + A_UINT8 is_amsdu, tid, is_acl_data_frame; + is_acl_data_frame = WMI_DATA_HDR_GET_DATA_TYPE(dhdr) == WMI_DATA_HDR_DATA_TYPE_ACL; + + /* + * this is a wmi data packet + */ + // NWF + + if (processDot11Hdr) { + minHdrLen = sizeof(WMI_DATA_HDR) + sizeof(struct ieee80211_frame) + sizeof(ATH_LLC_SNAP_HDR); + } else { + minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR); + } + + /* In the case of AP mode we may receive NULL data frames + * that do not have LLC hdr. They are 16 bytes in size. + * Allow these frames in the AP mode. + * ACL data frames don't follow ethernet frame bounds for + * min length + */ + if (ar->arNetworkType != AP_NETWORK && !is_acl_data_frame && + ((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE))) + { + /* + * packet is too short or too long + */ + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("TOO SHORT or TOO LONG\n")); + AR6000_STAT_INC(ar, rx_errors); + AR6000_STAT_INC(ar, rx_length_errors); + A_NETBUF_FREE(skb); + } else { + A_UINT16 seq_no; + A_UINT8 meta_type; + +#if 0 + /* Access RSSI values here */ + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("RSSI %d\n", + ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi)); +#endif + /* Get the Power save state of the STA */ + if (ar->arNetworkType == AP_NETWORK) { + sta_t *conn = NULL; + A_UINT8 psState=0,prevPsState; + ATH_MAC_HDR *datap=NULL; + A_UINT16 offset; + + meta_type = WMI_DATA_HDR_GET_META(dhdr); + + psState = (((WMI_DATA_HDR *)A_NETBUF_DATA(skb))->info + >> WMI_DATA_HDR_PS_SHIFT) & WMI_DATA_HDR_PS_MASK; + + offset = sizeof(WMI_DATA_HDR); + + switch (meta_type) { + case 0: + break; + case WMI_META_VERSION_1: + offset += sizeof(WMI_RX_META_V1); + break; +#ifdef CONFIG_CHECKSUM_OFFLOAD + case WMI_META_VERSION_2: + offset += sizeof(WMI_RX_META_V2); + break; +#endif + default: + break; + } + + datap = (ATH_MAC_HDR *)(A_NETBUF_DATA(skb)+offset); + conn = ieee80211_find_conn(ar, datap->srcMac); + + if (conn) { + /* if there is a change in PS state of the STA, + * take appropriate steps. + * 1. If Sleep-->Awake, flush the psq for the STA + * Clear the PVB for the STA. + * 2. If Awake-->Sleep, Starting queueing frames + * the STA. + */ + prevPsState = STA_IS_PWR_SLEEP(conn); + if (psState) { + STA_SET_PWR_SLEEP(conn); + } else { + STA_CLR_PWR_SLEEP(conn); + } + + if (prevPsState ^ STA_IS_PWR_SLEEP(conn)) { + + if (!STA_IS_PWR_SLEEP(conn)) { + + A_MUTEX_LOCK(&conn->psqLock); + while (!A_NETBUF_QUEUE_EMPTY(&conn->psq)) { + struct sk_buff *skb=NULL; + + skb = A_NETBUF_DEQUEUE(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + ar6000_data_tx(skb,ar->arNetDev); + A_MUTEX_LOCK(&conn->psqLock); + } + A_MUTEX_UNLOCK(&conn->psqLock); + /* Clear the PVB for this STA */ + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0); + } + } + } else { + /* This frame is from a STA that is not associated*/ + A_ASSERT(FALSE); + } + + /* Drop NULL data frames here */ + if((pPacket->ActualLength < minHdrLen) || + (pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE)) { + A_NETBUF_FREE(skb); + goto rx_done; + } + } + + is_amsdu = WMI_DATA_HDR_IS_AMSDU(dhdr); + tid = WMI_DATA_HDR_GET_UP(dhdr); + seq_no = WMI_DATA_HDR_GET_SEQNO(dhdr); + meta_type = WMI_DATA_HDR_GET_META(dhdr); + containsDot11Hdr = WMI_DATA_HDR_GET_DOT11(dhdr); + + wmi_data_hdr_remove(ar->arWmi, skb); + + switch (meta_type) { + case WMI_META_VERSION_1: + { + WMI_RX_META_V1 *pMeta = (WMI_RX_META_V1 *)A_NETBUF_DATA(skb); + A_PRINTF("META %d %d %d %d %x\n", pMeta->status, pMeta->rix, pMeta->rssi, pMeta->channel, pMeta->flags); + A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V1)); + break; + } +#ifdef CONFIG_CHECKSUM_OFFLOAD + case WMI_META_VERSION_2: + { + WMI_RX_META_V2 *pMeta = (WMI_RX_META_V2 *)A_NETBUF_DATA(skb); + if(pMeta->csumFlags & 0x1){ + skb->ip_summed=CHECKSUM_COMPLETE; + skb->csum=(pMeta->csum); + } + A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V2)); + break; + } +#endif + default: + break; + } + + A_ASSERT(status == A_OK); + + /* NWF: print the 802.11 hdr bytes */ + if(containsDot11Hdr) { + status = wmi_dot11_hdr_remove(ar->arWmi,skb); + } else if(!is_amsdu && !is_acl_data_frame) { + status = wmi_dot3_2_dix(skb); + } + + if (status != A_OK) { + /* Drop frames that could not be processed (lack of memory, etc.) */ + A_NETBUF_FREE(skb); + goto rx_done; + } + + if (is_acl_data_frame) { + A_NETBUF_PUSH(skb, sizeof(int)); + *((short *)A_NETBUF_DATA(skb)) = WMI_ACL_DATA_EVENTID; + } +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + /* + * extra push and memcpy, for eth_type_trans() of 2.4 kernel + * will pull out hard_header_len bytes of the skb. + */ + A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN); + A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) + + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR)); +#endif + if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) { + if (ar->arNetworkType == AP_NETWORK) { + struct sk_buff *skb1 = NULL; + ATH_MAC_HDR *datap; + + datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb); + if (IEEE80211_IS_MULTICAST(datap->dstMac)) { + /* Bcast/Mcast frames should be sent to the OS + * stack as well as on the air. + */ + skb1 = skb_copy(skb,GFP_ATOMIC); + } else { + /* Search for a connected STA with dstMac as + * the Mac address. If found send the frame to + * it on the air else send the frame up the + * stack + */ + sta_t *conn = NULL; + conn = ieee80211_find_conn(ar, datap->dstMac); + + if (conn && ar->intra_bss) { + skb1 = skb; + skb = NULL; + } else if(conn && !ar->intra_bss) { + A_NETBUF_FREE(skb); + skb = NULL; + } + } + if (skb1) { + ar6000_data_tx(skb1, ar->arNetDev); + } + } + } +#ifdef ATH_AR6K_11N_SUPPORT + aggr_process_recv_frm(ar->aggr_cntxt, tid, seq_no, is_amsdu, (void **)&skb); +#endif + ar6000_deliver_frames_to_nw_stack((void *) ar->arNetDev, (void *)skb); + } + } + } else { + if (EPPING_ALIGNMENT_PAD > 0) { + A_NETBUF_PULL(skb, EPPING_ALIGNMENT_PAD); + } + ar6000_deliver_frames_to_nw_stack((void *)ar->arNetDev, (void *)skb); + } + +rx_done: + + return; +} + +static void +ar6000_deliver_frames_to_nw_stack(void *dev, void *osbuf) +{ + struct sk_buff *skb = (struct sk_buff *)osbuf; + + if(skb) { + skb->dev = dev; + if ((skb->dev->flags & IFF_UP) == IFF_UP) { + skb->protocol = eth_type_trans(skb, skb->dev); + /* + * If this routine is called on a ISR (Hard IRQ) or DSR (Soft IRQ) + * or tasklet use the netif_rx to deliver the packet to the stack + * netif_rx will queue the packet onto the receive queue and mark + * the softirq thread has a pending action to complete. Kernel will + * schedule the softIrq kernel thread after processing the DSR. + * + * If this routine is called on a process context, use netif_rx_ni + * which will schedle the softIrq kernel thread after queuing the packet. + */ + if (in_interrupt()) { + netif_rx(skb); + } else { + netif_rx_ni(skb); + } + } else { + A_NETBUF_FREE(skb); + } + } +} + +#if 0 +static void +ar6000_deliver_frames_to_bt_stack(void *dev, void *osbuf) +{ + struct sk_buff *skb = (struct sk_buff *)osbuf; + + if(skb) { + skb->dev = dev; + if ((skb->dev->flags & IFF_UP) == IFF_UP) { + skb->protocol = htons(ETH_P_CONTROL); + netif_rx(skb); + } else { + A_NETBUF_FREE(skb); + } + } +} +#endif + +static void +ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + void *osBuf; + int RxBuffers; + int buffersToRefill; + HTC_PACKET *pPacket; + HTC_PACKET_QUEUE queue; + + buffersToRefill = (int)AR6000_MAX_RX_BUFFERS - + HTCGetNumRecvBuffers(ar->arHtcTarget, Endpoint); + + if (buffersToRefill <= 0) { + /* fast return, nothing to fill */ + return; + } + + INIT_HTC_PACKET_QUEUE(&queue); + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n", + buffersToRefill, Endpoint)); + + for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) { + osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE); + if (NULL == osBuf) { + break; + } + /* the HTC packet wrapper is at the head of the reserved area + * in the skb */ + pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf)); + /* set re-fill info */ + SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint); + /* add to queue */ + HTC_PACKET_ENQUEUE(&queue,pPacket); + } + + if (!HTC_QUEUE_EMPTY(&queue)) { + /* add packets */ + HTCAddReceivePktMultiple(ar->arHtcTarget, &queue); + } + +} + + /* clean up our amsdu buffer list */ +static void ar6000_cleanup_amsdu_rxbufs(AR_SOFTC_T *ar) +{ + HTC_PACKET *pPacket; + void *osBuf; + + /* empty AMSDU buffer queue and free OS bufs */ + while (TRUE) { + + AR6000_SPIN_LOCK(&ar->arLock, 0); + pPacket = HTC_PACKET_DEQUEUE(&ar->amsdu_rx_buffer_queue); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (NULL == pPacket) { + break; + } + + osBuf = pPacket->pPktContext; + if (NULL == osBuf) { + A_ASSERT(FALSE); + break; + } + + A_NETBUF_FREE(osBuf); + } + +} + + + /* refill the amsdu buffer list */ +static void ar6000_refill_amsdu_rxbufs(AR_SOFTC_T *ar, int Count) +{ + HTC_PACKET *pPacket; + void *osBuf; + + while (Count > 0) { + osBuf = A_NETBUF_ALLOC(AR6000_AMSDU_BUFFER_SIZE); + if (NULL == osBuf) { + break; + } + /* the HTC packet wrapper is at the head of the reserved area + * in the skb */ + pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf)); + /* set re-fill info */ + SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_AMSDU_BUFFER_SIZE,0); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* put it in the list */ + HTC_PACKET_ENQUEUE(&ar->amsdu_rx_buffer_queue,pPacket); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + Count--; + } + +} + + /* callback to allocate a large receive buffer for a pending packet. This function is called when + * an HTC packet arrives whose length exceeds a threshold value + * + * We use a pre-allocated list of buffers of maximum AMSDU size (4K). Under linux it is more optimal to + * keep the allocation size the same to optimize cached-slab allocations. + * + * */ +static HTC_PACKET *ar6000_alloc_amsdu_rxbuf(void *Context, HTC_ENDPOINT_ID Endpoint, int Length) +{ + HTC_PACKET *pPacket = NULL; + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + int refillCount = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_RX,("ar6000_alloc_amsdu_rxbuf: eid=%d, Length:%d\n",Endpoint,Length)); + + do { + + if (Length <= AR6000_BUFFER_SIZE) { + /* shouldn't be getting called on normal sized packets */ + A_ASSERT(FALSE); + break; + } + + if (Length > AR6000_AMSDU_BUFFER_SIZE) { + A_ASSERT(FALSE); + break; + } + + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* allocate a packet from the list */ + pPacket = HTC_PACKET_DEQUEUE(&ar->amsdu_rx_buffer_queue); + /* see if we need to refill again */ + refillCount = AR6000_MAX_AMSDU_RX_BUFFERS - HTC_PACKET_QUEUE_DEPTH(&ar->amsdu_rx_buffer_queue); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (NULL == pPacket) { + break; + } + /* set actual endpoint ID */ + pPacket->Endpoint = Endpoint; + + } while (FALSE); + + if (refillCount >= AR6000_AMSDU_REFILL_THRESHOLD) { + ar6000_refill_amsdu_rxbufs(ar,refillCount); + } + + return pPacket; +} + + +static struct net_device_stats * +ar6000_get_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + return &ar->arNetStats; +} + +static struct iw_statistics * +ar6000_get_iwstats(struct net_device * dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + TARGET_STATS *pStats = &ar->arTargetStats; + struct iw_statistics * pIwStats = &ar->arIwStats; + int rtnllocked; + + if (ar->bIsDestroyProgress || ar->arWmiReady == FALSE) + { + pIwStats->status = 0; + pIwStats->qual.qual = 0; + pIwStats->qual.level =0; + pIwStats->qual.noise = 0; + pIwStats->discard.code =0; + pIwStats->discard.retries=0; + pIwStats->miss.beacon =0; + return pIwStats; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) + /* + * The in_atomic function is used to determine if the scheduling is + * allowed in the current context or not. This was introduced in 2.6 + * From what I have read on the differences between 2.4 and 2.6, the + * 2.4 kernel did not support preemption and so this check might not + * be required for 2.4 kernels. + */ + if (in_atomic()) + { + wmi_get_stats_cmd(ar->arWmi); + + pIwStats->status = 1 ; + pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161; + pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */ + pIwStats->qual.noise = pStats->noise_floor_calibation; + pIwStats->discard.code = pStats->rx_decrypt_err; + pIwStats->discard.retries = pStats->tx_retry_cnt; + pIwStats->miss.beacon = pStats->cs_bmiss_cnt; + return pIwStats; + } +#endif /* LINUX_VERSION_CODE */ + + if (down_interruptible(&ar->arSem)) { + pIwStats->status = 0; + return pIwStats; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + + dev_hold(dev); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + rtnllocked = rtnl_is_locked(); +#else + rtnllocked = TRUE; +#endif + if (rtnllocked) { + rtnl_unlock(); + } + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + if (rtnllocked) { + rtnl_lock(); + } + dev_put(dev); + + if (signal_pending(current)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : WMI get stats timeout \n")); + up(&ar->arSem); + pIwStats->status = 0; + return pIwStats; + } + pIwStats->status = 1 ; + pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161; + pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */ + pIwStats->qual.noise = pStats->noise_floor_calibation; + pIwStats->discard.code = pStats->rx_decrypt_err; + pIwStats->discard.retries = pStats->tx_retry_cnt; + pIwStats->miss.beacon = pStats->cs_bmiss_cnt; + up(&ar->arSem); + return pIwStats; +} + +void +ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, A_UINT32 vers) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + struct net_device *dev = ar->arNetDev; + + ar->arWmiReady = TRUE; + wake_up(&arEvent); + A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + dev->dev_addr[0], dev->dev_addr[1], + dev->dev_addr[2], dev->dev_addr[3], + dev->dev_addr[4], dev->dev_addr[5])); + + ar->arPhyCapability = phyCap; + ar->arVersion.wlan_ver = vers; + +#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN + wmi_pmparams_cmd(ar->arWmi, 0, 1, 0, 0, 1, IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN); +#endif +#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP + wmi_set_lpreamble_cmd(ar->arWmi, 0, WMI_DONOT_IGNORE_BARKER_IN_ERP); +#endif + wmi_set_keepalive_cmd(ar->arWmi, WLAN_CONFIG_KEEP_ALIVE_INTERVAL); +} + +A_UINT8 +add_new_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 aid, A_UINT8 *wpaie, + A_UINT8 ielen, A_UINT8 keymgmt, A_UINT8 ucipher, A_UINT8 auth) +{ + A_INT8 free_slot=-1, i; + + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) { + /* it is already available */ + return 0; + } + + if(!((1 << i) & ar->sta_list_index)) { + free_slot = i; + break; + } + } + + if(free_slot >= 0) { + A_MEMCPY(ar->sta_list[free_slot].mac, mac, ATH_MAC_LEN); + A_MEMCPY(ar->sta_list[free_slot].wpa_ie, wpaie, ielen); + ar->sta_list[free_slot].aid = aid; + ar->sta_list[free_slot].keymgmt = keymgmt; + ar->sta_list[free_slot].ucipher = ucipher; + ar->sta_list[free_slot].auth = auth; + ar->sta_list_index = ar->sta_list_index | (1 << free_slot); + ar->arAPStats.sta[aid-1].aid = aid; + return 1; + } + return 0; /* not added */ +} + +void +ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid, + A_UINT16 listenInterval, A_UINT16 beaconInterval, + NETWORK_TYPE networkType, A_UINT8 beaconIeLen, + A_UINT8 assocReqLen, A_UINT8 assocRespLen, + A_UINT8 *assocInfo) +{ + union iwreq_data wrqu; + int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos; + static const char *tag1 = "ASSOCINFO(ReqIEs="; + static const char *tag2 = "ASSOCRESPIE="; + static const char *beaconIetag = "BEACONIE="; + char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + strlen(tag1) + 1]; + char *pos; + A_UINT8 key_op_ctrl; + unsigned long flags; + struct ieee80211req_key *ik; + CRYPTO_TYPE keyType = NONE_CRYPT; + + if(ar->arNetworkType & AP_NETWORK) { + struct net_device *dev = ar->arNetDev; + if(A_MEMCMP(dev->dev_addr, bssid, ATH_MAC_LEN)==0) { + ar->arACS = channel; + ik = &ar->ap_mode_bkey; + + switch(ar->arAuthMode) { + case NONE_AUTH: + if(ar->arPairwiseCrypto == WEP_CRYPT) { + ar6000_install_static_wep_keys(ar); + } +#ifdef WAPI_ENABLE + else if(ar->arPairwiseCrypto == WAPI_CRYPT) { + ap_set_wapi_key(ar, ik); + } +#endif + break; + case WPA_PSK_AUTH: + case WPA2_PSK_AUTH: + case (WPA_PSK_AUTH|WPA2_PSK_AUTH): + switch (ik->ik_type) { + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + goto skip_key; + } + wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, GROUP_USAGE, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + break; + } +skip_key: + ar->arConnected = TRUE; + return; + } + + A_PRINTF("NEW STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x \n " + " AID=%d \n", bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], channel); + switch ((listenInterval>>8)&0xFF) { + case OPEN_AUTH: + A_PRINTF("AUTH: OPEN\n"); + break; + case SHARED_AUTH: + A_PRINTF("AUTH: SHARED\n"); + break; + default: + A_PRINTF("AUTH: Unknown\n"); + break; + }; + switch (listenInterval&0xFF) { + case WPA_PSK_AUTH: + A_PRINTF("KeyMgmt: WPA-PSK\n"); + break; + case WPA2_PSK_AUTH: + A_PRINTF("KeyMgmt: WPA2-PSK\n"); + break; + default: + A_PRINTF("KeyMgmt: NONE\n"); + break; + }; + switch (beaconInterval) { + case AES_CRYPT: + A_PRINTF("Cipher: AES\n"); + break; + case TKIP_CRYPT: + A_PRINTF("Cipher: TKIP\n"); + break; + case WEP_CRYPT: + A_PRINTF("Cipher: WEP\n"); + break; +#ifdef WAPI_ENABLE + case WAPI_CRYPT: + A_PRINTF("Cipher: WAPI\n"); + break; +#endif + default: + A_PRINTF("Cipher: NONE\n"); + break; + }; + + add_new_sta(ar, bssid, channel /*aid*/, + assocInfo /* WPA IE */, assocRespLen /* IE len */, + listenInterval&0xFF /* Keymgmt */, beaconInterval /* cipher */, + (listenInterval>>8)&0xFF /* auth alg */); + + /* Send event to application */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN); + wireless_send_event(ar->arNetDev, IWEVREGISTERED, &wrqu, NULL); + /* In case the queue is stopped when we switch modes, this will + * wake it up + */ + netif_wake_queue(ar->arNetDev); + return; + } + +#ifdef ATH6K_CONFIG_CFG80211 + ar6k_cfg80211_connect_event(ar, channel, bssid, + listenInterval, beaconInterval, + networkType, beaconIeLen, + assocReqLen, assocRespLen, + assocInfo); +#endif /* ATH6K_CONFIG_CFG80211 */ + + A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid)); + ar->arBssChannel = channel; + + A_PRINTF("AR6000 connected event on freq %d ", channel); + A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d" + " assocRespLen =%d\n", + bssid[0], bssid[1], bssid[2], + bssid[3], bssid[4], bssid[5], + listenInterval, beaconInterval, + beaconIeLen, assocReqLen, assocRespLen); + if (networkType & ADHOC_NETWORK) { + if (networkType & ADHOC_CREATOR) { + A_PRINTF("Network: Adhoc (Creator)\n"); + } else { + A_PRINTF("Network: Adhoc (Joiner)\n"); + } + } else { + A_PRINTF("Network: Infrastructure\n"); + } + + if ((ar->arNetworkType == INFRA_NETWORK)) { + wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0); + } + + if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nBeaconIEs= ")); + + beacon_ie_pos = 0; + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", beaconIetag); + pos = buf + 9; + for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i])); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n")); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2)))) + { + assoc_resp_ie_pos = beaconIeLen + assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag2); + pos = buf + 12; + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nAssocRespIEs= ")); + /* + * The Association Response Frame w.o. the WLAN header is delivered to + * the host, so skip over to the IEs + */ + for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++) + { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i])); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2; + } + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n")); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + + if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) { + /* + * assoc Request includes capability and listen interval. Skip these. + */ + assoc_req_ie_pos = beaconIeLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16); /* listen interval */ + + A_MEMZERO(buf, sizeof(buf)); + sprintf(buf, "%s", tag1); + pos = buf + 17; + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AssocReqIEs= ")); + for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i])); + sprintf(pos, "%2.2x", assocInfo[i]); + pos += 2;; + } + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n")); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + } + +#ifdef USER_KEYS + if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN && + ar->user_saved_keys.keyOk == TRUE) + { + key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC; + + if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) { + key_op_ctrl &= ~KEY_OP_INIT_RSC; + } else { + key_op_ctrl |= KEY_OP_INIT_RSC; + } + ar6000_reinstall_keys(ar, key_op_ctrl); + } +#endif /* USER_KEYS */ + + netif_wake_queue(ar->arNetDev); + + if ((networkType & ADHOC_NETWORK) && + (OPEN_AUTH == ar->arDot11AuthMode) && + (NONE_AUTH == ar->arAuthMode) && + (WEP_CRYPT == ar->arPairwiseCrypto)) + { + if (!ar->arConnected) { + wmi_addKey_cmd(ar->arWmi, + ar->arDefTxKeyIndex, + WEP_CRYPT, + GROUP_USAGE | TX_USAGE, + ar->arWepKeyList[ar->arDefTxKeyIndex].arKeyLen, + NULL, + ar->arWepKeyList[ar->arDefTxKeyIndex].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } + + /* Update connect & link status atomically */ + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = TRUE; + ar->arConnectPending = FALSE; + netif_carrier_on(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + /* reset the rx aggr state */ + aggr_reset_state(ar->aggr_cntxt); + reconnect_flag = 0; + + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN); + wrqu.addr.sa_family = ARPHRD_ETHER; + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) { + A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap)); + ar->arNodeNum = 0; + ar->arNexEpId = ENDPOINT_2; + } + if (!ar->arUserBssFilter) { + wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0); + } + +} + +void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num) +{ + A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1)); + ar->arNumDataEndPts = num; +} + +void +sta_cleanup(AR_SOFTC_T *ar, A_UINT8 i) +{ + struct sk_buff *skb; + + /* empty the queued pkts in the PS queue if any */ + A_MUTEX_LOCK(&ar->sta_list[i].psqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->sta_list[i].psq)) { + skb = A_NETBUF_DEQUEUE(&ar->sta_list[i].psq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->sta_list[i].psqLock); + + /* Zero out the state fields */ + A_MEMZERO(&ar->arAPStats.sta[ar->sta_list[i].aid-1], sizeof(WMI_PER_STA_STAT)); + A_MEMZERO(&ar->sta_list[i].mac, ATH_MAC_LEN); + A_MEMZERO(&ar->sta_list[i].wpa_ie, IEEE80211_MAX_IE); + ar->sta_list[i].aid = 0; + ar->sta_list[i].flags = 0; + + ar->sta_list_index = ar->sta_list_index & ~(1 << i); + +} + +A_UINT8 +remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason) +{ + A_UINT8 i, removed=0; + + if(IS_MAC_NULL(mac)) { + return removed; + } + + if(IS_MAC_BCAST(mac)) { + A_PRINTF("DEL ALL STA\n"); + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(!IS_MAC_NULL(ar->sta_list[i].mac)) { + sta_cleanup(ar, i); + removed = 1; + } + } + } else { + for(i=0; i < AP_MAX_NUM_STA; i++) { + if(A_MEMCMP(ar->sta_list[i].mac, mac, ATH_MAC_LEN)==0) { + A_PRINTF("DEL STA %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x " + " aid=%d REASON=%d\n", mac[0], mac[1], mac[2], + mac[3], mac[4], mac[5], ar->sta_list[i].aid, reason); + + sta_cleanup(ar, i); + removed = 1; + break; + } + } + } + return removed; +} + +void +ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid, + A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus) +{ + A_UINT8 i; + unsigned long flags; + + if(ar->arNetworkType & AP_NETWORK) { + union iwreq_data wrqu; + struct sk_buff *skb; + + if(!remove_sta(ar, bssid, protocolReasonStatus)) { + return; + } + + /* If there are no more associated STAs, empty the mcast PS q */ + if (ar->sta_list_index == 0) { + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* Clear the LSB of the BitMapCtl field of the TIM IE */ + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0); + } + + if(!IS_MAC_BCAST(bssid)) { + /* Send event to application */ + A_MEMZERO(&wrqu, sizeof(wrqu)); + A_MEMCPY(wrqu.addr.sa_data, bssid, ATH_MAC_LEN); + wireless_send_event(ar->arNetDev, IWEVEXPIRED, &wrqu, NULL); + } + return; + } + +#ifdef ATH6K_CONFIG_CFG80211 + ar6k_cfg80211_disconnect_event(ar, reason, bssid, + assocRespLen, assocInfo, + protocolReasonStatus); +#endif /* ATH6K_CONFIG_CFG80211 */ + + if (NO_NETWORK_AVAIL != reason) + { + union iwreq_data wrqu; + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.addr.sa_family = ARPHRD_ETHER; + + /* Send disconnect event to supplicant */ + wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL); + } + /* it is necessary to clear the host-side rx aggregation state */ + + aggr_reset_state(ar->aggr_cntxt); + + A_UNTIMEOUT(&ar->disconnect_timer); + + A_PRINTF("AR6000 disconnected"); + if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) { + A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nDisconnect Reason is %d", reason)); + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nProtocol Reason/Status Code is %d", protocolReasonStatus)); + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\nAssocResp Frame = %s", + assocRespLen ? " " : "NULL")); + for (i = 0; i < assocRespLen; i++) { + if (!(i % 0x10)) { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n")); + } + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("%2.2x ", assocInfo[i])); + } + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("\n")); + /* + * If the event is due to disconnect cmd from the host, only they the target + * would stop trying to connect. Under any other condition, target would + * keep trying to connect. + * + */ + if( reason == DISCONNECT_CMD) + { + ar->arConnectPending = FALSE; + if (!ar->arUserBssFilter) { + wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0); + } + } else { + ar->arConnectPending = TRUE; + if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) || + ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) { + ar->arConnected = TRUE; + return; + } + } + + if (reason == NO_NETWORK_AVAIL) + { + bss_t *pWmiSsidnode = NULL; + + /* remove the current associated bssid node */ + wmi_free_node (ar->arWmi, bssid); + + /* + * In case any other same SSID nodes are present + * remove it, since those nodes also not available now + */ + do + { + /* + * Find the nodes based on SSID and remove it + * NOTE :: This case will not work out for Hidden-SSID + */ + pWmiSsidnode = wmi_find_Ssidnode (ar->arWmi, ar->arSsid, ar->arSsidLen, FALSE, TRUE); + + if (pWmiSsidnode) + { + wmi_free_node (ar->arWmi, pWmiSsidnode->ni_macaddr); + } + + }while (pWmiSsidnode); + +#if 0 + /* + * Issuing a disconnect cmd prevent the firmware from + * continuing the scan and connect to the AP, if the AP + * cannot be found in 10 seconds. The user has to issue + * the iwconfig command again to connect to the AP. + * This change came in CL#575412 (EV# 59469) has to + * be fixed in a different way + */ + ar6000_init_profile_info(ar); + wmi_disconnect_cmd(ar->arWmi); +#endif + } + + /* Update connect & link status atomically */ + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = FALSE; + netif_carrier_off(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + + if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) { + reconnect_flag = 0; + } + +#ifdef USER_KEYS + if (reason != CSERV_DISCONNECT) + { + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + } +#endif /* USER_KEYS */ + + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + ar6000_TxDataCleanup(ar); +} + +void +ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode) +{ + A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode); + ar->arRegCode = regCode; +} + +#ifdef ATH_AR6K_11N_SUPPORT +void +ar6000_aggr_rcv_addba_req_evt(AR_SOFTC_T *ar, WMI_ADDBA_REQ_EVENT *evt) +{ + if(evt->status == 0) { + aggr_recv_addba_req_evt(ar->aggr_cntxt, evt->tid, evt->st_seq_no, evt->win_sz); + } +} + +void +ar6000_aggr_rcv_addba_resp_evt(AR_SOFTC_T *ar, WMI_ADDBA_RESP_EVENT *evt) +{ + A_PRINTF("ADDBA RESP. tid %d status %d, sz %d\n", evt->tid, evt->status, evt->amsdu_sz); + if(evt->status == 0) { + } +} + +void +ar6000_aggr_rcv_delba_req_evt(AR_SOFTC_T *ar, WMI_DELBA_EVENT *evt) +{ + aggr_recv_delba_req_evt(ar->aggr_cntxt, evt->tid); +} +#endif + +void +ar6000_hci_event_rcv_evt(struct ar6_softc *ar, WMI_HCI_EVENT *cmd) +{ + void *osbuf = NULL; + A_INT8 i; + A_UINT8 size, *buf; + A_STATUS ret = A_OK; + + size = cmd->evt_buf_sz + 4; + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + ret = A_NO_MEMORY; + A_PRINTF("Error in allocating netbuf \n"); + return; + } + + A_NETBUF_PUT(osbuf, size); + buf = (A_UINT8 *)A_NETBUF_DATA(osbuf); + /* First 2-bytes carry HCI event/ACL data type + * the next 2 are free + */ + *((short *)buf) = WMI_HCI_EVENT_EVENTID; + buf += sizeof(int); + A_MEMCPY(buf, cmd->buf, cmd->evt_buf_sz); + + ar6000_deliver_frames_to_nw_stack(ar->arNetDev, osbuf); + if(loghci) { + A_PRINTF_LOG("HCI Event From PAL <-- \n"); + for(i = 0; i < cmd->evt_buf_sz; i++) { + A_PRINTF_LOG("0x%02x ", cmd->buf[i]); + if((i % 10) == 0) { + A_PRINTF_LOG("\n"); + } + } + A_PRINTF_LOG("\n"); + A_PRINTF_LOG("==================================\n"); + } +} + +void +ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info) +{ +#if WIRELESS_EXT >= 18 + struct iw_pmkid_cand *pmkcand; +#else /* WIRELESS_EXT >= 18 */ + static const char *tag = "PRE-AUTH"; + char buf[128]; +#endif /* WIRELESS_EXT >= 18 */ + + union iwreq_data wrqu; + int i; + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("AR6000 Neighbor Report Event\n")); + for (i=0; i < numAps; info++, i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5])); + if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("preauth-cap")); + } + if (info->bssFlags & WMI_PMKID_VALID_BSS) { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,(" pmkid-valid\n")); + continue; /* we skip bss if the pmkid is already valid */ + } + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("\n")); + A_MEMZERO(&wrqu, sizeof(wrqu)); +#if WIRELESS_EXT >= 18 + pmkcand = A_MALLOC_NOWAIT(sizeof(struct iw_pmkid_cand)); + A_MEMZERO(pmkcand, sizeof(struct iw_pmkid_cand)); + pmkcand->index = i; + pmkcand->flags = info->bssFlags; + A_MEMCPY(pmkcand->bssid.sa_data, info->bssid, ATH_MAC_LEN); + wrqu.data.length = sizeof(struct iw_pmkid_cand); + wireless_send_event(ar->arNetDev, IWEVPMKIDCAND, &wrqu, (char *)pmkcand); + A_FREE(pmkcand); +#else /* WIRELESS_EXT >= 18 */ + snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x", + tag, + info->bssid[0], info->bssid[1], info->bssid[2], + info->bssid[3], info->bssid[4], info->bssid[5], + i, info->bssFlags); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); +#endif /* WIRELESS_EXT >= 18 */ + } +} + +void +ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast) +{ + static const char *tag = "MLME-MICHAELMICFAILURE.indication"; + char buf[128]; + union iwreq_data wrqu; + + /* + * For AP case, keyid will have aid of STA which sent pkt with + * MIC error. Use this aid to get MAC & send it to hostapd. + */ + if (ar->arNetworkType == AP_NETWORK) { + sta_t *s = ieee80211_find_conn_for_aid(ar, (keyid >> 2)); + if(!s){ + A_PRINTF("AP TKIP MIC error received from Invalid aid / STA not found =%d\n", keyid); + return; + } + A_PRINTF("AP TKIP MIC error received from aid=%d\n", keyid); + snprintf(buf,sizeof(buf), "%s addr=%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x", + tag, s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]); + } else { + +#ifdef ATH6K_CONFIG_CFG80211 + ar6k_cfg80211_tkip_micerr_event(ar, keyid, ismcast); +#endif /* ATH6K_CONFIG_CFG80211 */ + + A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n", + keyid & 0x3, ismcast ? "multi": "uni"); + snprintf(buf, sizeof(buf), "%s(keyid=%d %sicast)", tag, keyid & 0x3, + ismcast ? "mult" : "un"); + } + + memset(&wrqu, 0, sizeof(wrqu)); + wrqu.data.length = strlen(buf); + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); +} + +void +ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status) +{ + +#ifdef ATH6K_CONFIG_CFG80211 + ar6k_cfg80211_scanComplete_event(ar, status); +#endif /* ATH6K_CONFIG_CFG80211 */ + + if (!ar->arUserBssFilter) { + wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0); + } + if (!ar->scan_complete) { + if (status==A_OK) { + union iwreq_data wrqu; + A_MEMZERO(&wrqu, sizeof(wrqu)); + wireless_send_event(ar->arNetDev, SIOCGIWSCAN, &wrqu, NULL); + ar->scan_complete = 1; + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,( "AR6000 scan complete: %d\n", status)); +} + +void +ar6000_targetStats_event(AR_SOFTC_T *ar, A_UINT8 *ptr, A_UINT32 len) +{ + A_UINT8 ac; + + if(ar->arNetworkType == AP_NETWORK) { + WMI_AP_MODE_STAT *p = (WMI_AP_MODE_STAT *)ptr; + WMI_AP_MODE_STAT *ap = &ar->arAPStats; + + if (len < sizeof(*p)) { + return; + } + + for(ac=0;acsta[ac].tx_bytes += p->sta[ac].tx_bytes; + ap->sta[ac].tx_pkts += p->sta[ac].tx_pkts; + ap->sta[ac].tx_error += p->sta[ac].tx_error; + ap->sta[ac].tx_discard += p->sta[ac].tx_discard; + ap->sta[ac].rx_bytes += p->sta[ac].rx_bytes; + ap->sta[ac].rx_pkts += p->sta[ac].rx_pkts; + ap->sta[ac].rx_error += p->sta[ac].rx_error; + ap->sta[ac].rx_discard += p->sta[ac].rx_discard; + } + + } else { + WMI_TARGET_STATS *pTarget = (WMI_TARGET_STATS *)ptr; + TARGET_STATS *pStats = &ar->arTargetStats; + + if (len < sizeof(*pTarget)) { + return; + } + + // Update the RSSI of the connected bss. + if (ar->arConnected) { + bss_t *pConnBss = NULL; + + pConnBss = wmi_find_node(ar->arWmi,ar->arBssid); + if (pConnBss) + { + pConnBss->ni_rssi = pTarget->cservStats.cs_aveBeacon_rssi; + pConnBss->ni_snr = pTarget->cservStats.cs_aveBeacon_snr; + wmi_node_return(ar->arWmi, pConnBss); + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 updating target stats\n")); + pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets; + pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes; + pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts; + pStats->tx_unicast_bytes += pTarget->txrxStats.tx_stats.tx_unicast_bytes; + pStats->tx_multicast_pkts += pTarget->txrxStats.tx_stats.tx_multicast_pkts; + pStats->tx_multicast_bytes += pTarget->txrxStats.tx_stats.tx_multicast_bytes; + pStats->tx_broadcast_pkts += pTarget->txrxStats.tx_stats.tx_broadcast_pkts; + pStats->tx_broadcast_bytes += pTarget->txrxStats.tx_stats.tx_broadcast_bytes; + pStats->tx_rts_success_cnt += pTarget->txrxStats.tx_stats.tx_rts_success_cnt; + for(ac = 0; ac < WMM_NUM_AC; ac++) + pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac]; + pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors; + pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt; + pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt; + pStats->tx_mult_retry_cnt += pTarget->txrxStats.tx_stats.tx_mult_retry_cnt; + pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt; + pStats->tx_unicast_rate = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate); + + pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets; + pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes; + pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts; + pStats->rx_unicast_bytes += pTarget->txrxStats.rx_stats.rx_unicast_bytes; + pStats->rx_multicast_pkts += pTarget->txrxStats.rx_stats.rx_multicast_pkts; + pStats->rx_multicast_bytes += pTarget->txrxStats.rx_stats.rx_multicast_bytes; + pStats->rx_broadcast_pkts += pTarget->txrxStats.rx_stats.rx_broadcast_pkts; + pStats->rx_broadcast_bytes += pTarget->txrxStats.rx_stats.rx_broadcast_bytes; + pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt; + pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors; + pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr; + pStats->rx_key_cache_miss += pTarget->txrxStats.rx_stats.rx_key_cache_miss; + pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err; + pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames; + pStats->rx_unicast_rate = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate); + + + pStats->tkip_local_mic_failure + += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure; + pStats->tkip_counter_measures_invoked + += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked; + pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays; + pStats->tkip_format_errors += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors; + pStats->ccmp_format_errors += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors; + pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays; + + pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt; + pStats->noise_floor_calibation = pTarget->noise_floor_calibation; + + pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt; + pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt; + pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt; + pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt; + pStats->cs_aveBeacon_snr = pTarget->cservStats.cs_aveBeacon_snr; + pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi; + + if (enablerssicompensation) { + pStats->cs_aveBeacon_rssi = + rssi_compensation_calc(ar, pStats->cs_aveBeacon_rssi); + } + pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec; + pStats->cs_snr = pTarget->cservStats.cs_snr; + pStats->cs_rssi = pTarget->cservStats.cs_rssi; + + pStats->lq_val = pTarget->lqVal; + + pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped; + pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups; + pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups; + pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded; + pStats->arp_received += pTarget->arpStats.arp_received; + pStats->arp_matched += pTarget->arpStats.arp_matched; + pStats->arp_replied += pTarget->arpStats.arp_replied; + + if (ar->statsUpdatePending) { + ar->statsUpdatePending = FALSE; + wake_up(&arEvent); + } + } +} + +void +ar6000_rssiThreshold_event(AR_SOFTC_T *ar, WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi) +{ + USER_RSSI_THOLD userRssiThold; + + rssi = rssi + SIGNAL_QUALITY_NOISE_FLOOR; + + if (enablerssicompensation) { + rssi = rssi_compensation_calc(ar, rssi); + } + + /* Send an event to the app */ + userRssiThold.tag = ar->rssi_map[newThreshold].tag; + userRssiThold.rssi = rssi; + A_PRINTF("rssi Threshold range = %d tag = %d rssi = %d\n", newThreshold, + userRssiThold.tag, userRssiThold.rssi); + + ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD)); +} + + +void +ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source) +{ + if (source == APP_HB_CHALLENGE) { + /* Report it to the app in case it wants a positive acknowledgement */ + ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID, + (A_UINT8 *)&cookie, sizeof(cookie)); + } else { + /* This would ignore the replys that come in after their due time */ + if (cookie == ar->arHBChallengeResp.seqNum) { + ar->arHBChallengeResp.outstanding = FALSE; + } + } +} + + +void +ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal) +{ + char *errString[] = { + [WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL", + [WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND", + [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR", + [WMI_TARGET_BMISS] "WMI_TARGET_BMISS", + [WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN" + }; + + A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal); + + /* One error is reported at a time, and errorval is a bitmask */ + if(errorVal & (errorVal - 1)) + return; + + A_PRINTF("AR6000 Error type = "); + switch(errorVal) + { + case WMI_TARGET_PM_ERR_FAIL: + case WMI_TARGET_KEY_NOT_FOUND: + case WMI_TARGET_DECRYPTION_ERR: + case WMI_TARGET_BMISS: + case WMI_PSDISABLE_NODE_JOIN: + A_PRINTF("%s\n", errString[errorVal]); + break; + default: + A_PRINTF("INVALID\n"); + break; + } + +} + + +void +ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion) +{ + WMM_TSPEC_IE *tspecIe; + + /* + * This is the TSPEC IE suggestion from AP. + * Suggestion provided by AP under some error + * cases, could be helpful for the host app. + * Check documentation. + */ + tspecIe = (WMM_TSPEC_IE *)tspecSuggestion; + + /* + * What do we do, if we get TSPEC rejection? One thought + * that comes to mind is implictly delete the pstream... + */ + A_PRINTF("AR6000 CAC notification. " + "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n", + ac, cacIndication, statusCode); +} + +void +ar6000_channel_change_event(AR_SOFTC_T *ar, A_UINT16 oldChannel, + A_UINT16 newChannel) +{ + A_PRINTF("Channel Change notification\nOld Channel: %d, New Channel: %d\n", + oldChannel, newChannel); +} + +#define AR6000_PRINT_BSSID(_pBss) do { \ + A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\ + (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\ + (_pBss)[4],(_pBss)[5]); \ +} while(0) + +void +ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl) +{ + A_UINT8 i; + + A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n", + pTbl->numEntries, pTbl->roamMode); + for (i= 0; i < pTbl->numEntries; i++) { + A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i, + pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1], + pTbl->bssRoamInfo[i].bssid[2], + pTbl->bssRoamInfo[i].bssid[3], + pTbl->bssRoamInfo[i].bssid[4], + pTbl->bssRoamInfo[i].bssid[5]); + A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d" + " BIAS %d\n", + pTbl->bssRoamInfo[i].rssi, + pTbl->bssRoamInfo[i].rssidt, + pTbl->bssRoamInfo[i].last_rssi, + pTbl->bssRoamInfo[i].util, + pTbl->bssRoamInfo[i].roam_util, + pTbl->bssRoamInfo[i].bias); + } +} + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply) +{ + A_UINT8 i,j; + + /*Each event now contains exactly one filter, see bug 26613*/ + A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num, wow_reply->num_filters); + A_PRINTF("wow mode = %s host mode = %s\n", + (wow_reply->wow_mode == 0? "disabled":"enabled"), + (wow_reply->host_mode == 1 ? "awake":"asleep")); + + + /*If there are no patterns, the reply will only contain generic + WoW information. Pattern information will exist only if there are + patterns present. Bug 26716*/ + + /* If this event contains pattern information, display it*/ + if (wow_reply->this_filter_num) { + i=0; + A_PRINTF("id=%d size=%d offset=%d\n", + wow_reply->wow_filters[i].wow_filter_id, + wow_reply->wow_filters[i].wow_filter_size, + wow_reply->wow_filters[i].wow_filter_offset); + A_PRINTF("wow pattern = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]); + } + + A_PRINTF("\nwow mask = "); + for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) { + A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]); + } + A_PRINTF("\n"); + } +} + +/* + * Report the Roaming related data collected on the target + */ +void +ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p) +{ + A_PRINTF("Disconnect Data : BSSID: "); + AR6000_PRINT_BSSID(p->disassoc_bssid); + A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n", + p->disassoc_bss_rssi,p->disassoc_time, + p->no_txrx_time); + A_PRINTF("Connect Data: BSSID: "); + AR6000_PRINT_BSSID(p->assoc_bssid); + A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n", + p->assoc_bss_rssi,p->assoc_time, + p->allow_txrx_time); +} + +void +ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p) +{ + switch (p->roamDataType) { + case ROAM_DATA_TIME: + ar6000_display_roam_time(&p->u.roamTime); + break; + default: + break; + } +} + +void +ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len) +{ + struct sk_buff *skb; + WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap; + + + if (!ar->arMgmtFilter) { + return; + } + if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) && + (bih->frameType != BEACON_FTYPE)) || + ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) && + (bih->frameType != PROBERESP_FTYPE))) + { + return; + } + + if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) { + + A_NETBUF_PUT(skb, len); + A_MEMCPY(A_NETBUF_DATA(skb), datap, len); + skb->dev = ar->arNetDev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) + A_MEMCPY(skb_mac_header(skb), A_NETBUF_DATA(skb), 6); +#else + skb->mac.raw = A_NETBUF_DATA(skb); +#endif + skb->ip_summed = CHECKSUM_NONE; + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = __constant_htons(0x0019); + netif_rx(skb); + } +} + +A_UINT32 wmiSendCmdNum; + +A_STATUS +ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + A_STATUS status = A_OK; + struct ar_cookie *cookie = NULL; + int i; +#ifdef CONFIG_PM + if (ar->arWowState) { + A_NETBUF_FREE(osbuf); + return A_EACCES; + } +#endif /* CONFIG_PM */ + /* take lock to protect ar6000_alloc_cookie() */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + + do { + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x eid =%d\n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), eid)); + + if (ar->arWMIControlEpFull && (eid == ar->arControlEp)) { + /* control endpoint is full, don't allocate resources, we + * are just going to drop this packet */ + cookie = NULL; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" WMI Control EP full, dropping packet : 0x%X, len:%d \n", + (A_UINT32)osbuf, A_NETBUF_LEN(osbuf))); + } else { + cookie = ar6000_alloc_cookie(ar); + } + + if (cookie == NULL) { + status = A_NO_MEMORY; + break; + } + + if(logWmiRawMsgs) { + A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum); + for(i = 0; i < a_netbuf_to_len(osbuf); i++) + A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]); + A_PRINTF("\n"); + } + + wmiSendCmdNum++; + + } while (FALSE); + + if (cookie != NULL) { + /* got a structure to send it out on */ + ar->arTxPending[eid]++; + + if (eid != ar->arControlEp) { + ar->arTotalTxDataPending++; + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (cookie != NULL) { + cookie->arc_bp[0] = (A_UINT32)osbuf; + cookie->arc_bp[1] = 0; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(osbuf), + A_NETBUF_LEN(osbuf), + eid, + AR6K_CONTROL_PKT_TAG); + /* this interface is asynchronous, if there is an error, cleanup will happen in the + * TX completion callback */ + HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt); + status = A_OK; + } + + if (status != A_OK) { + A_NETBUF_FREE(osbuf); + } + return status; +} + +/* indicate tx activity or inactivity on a WMI stream */ +void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + HTC_ENDPOINT_ID eid ; + int i; + + if (ar->arWmiEnabled) { + eid = arAc2EndpointID(ar, TrafficClass); + + AR6000_SPIN_LOCK(&ar->arLock, 0); + + ar->arAcStreamActive[TrafficClass] = Active; + + if (Active) { + /* when a stream goes active, keep track of the active stream with the highest priority */ + + if (ar->arAcStreamPriMap[TrafficClass] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[TrafficClass]; + } + + } else { + /* when a stream goes inactive, we may have to search for the next active stream + * that is the highest priority */ + + if (ar->arHiAcStreamActivePri == ar->arAcStreamPriMap[TrafficClass]) { + + /* the highest priority stream just went inactive */ + + /* reset and search for the "next" highest "active" priority stream */ + ar->arHiAcStreamActivePri = 0; + for (i = 0; i < WMM_NUM_AC; i++) { + if (ar->arAcStreamActive[i]) { + if (ar->arAcStreamPriMap[i] > ar->arHiAcStreamActivePri) { + /* set the new highest active priority */ + ar->arHiAcStreamActivePri = ar->arAcStreamPriMap[i]; + } + } + } + } + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + } else { + /* for mbox ping testing, the traffic class is mapped directly as a stream ID, + * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */ + eid = (HTC_ENDPOINT_ID)TrafficClass; + } + + /* notify HTC, this may cause credit distribution changes */ + + HTCIndicateActivityChange(ar->arHtcTarget, + eid, + Active); + +} + +void +ar6000_btcoex_config_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len) +{ + + WMI_BTCOEX_CONFIG_EVENT *pBtcoexConfig = (WMI_BTCOEX_CONFIG_EVENT *)ptr; + WMI_BTCOEX_CONFIG_EVENT *pArbtcoexConfig =&ar->arBtcoexConfig; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 BTCOEX CONFIG EVENT \n")); + + A_PRINTF("received config event\n"); + pArbtcoexConfig->btProfileType = pBtcoexConfig->btProfileType; + pArbtcoexConfig->linkId = pBtcoexConfig->linkId; + + switch (pBtcoexConfig->btProfileType) { + case WMI_BTCOEX_BT_PROFILE_SCO: + A_MEMCPY(&pArbtcoexConfig->info.scoConfigCmd, &pBtcoexConfig->info.scoConfigCmd, + sizeof(WMI_SET_BTCOEX_SCO_CONFIG_CMD)); + break; + case WMI_BTCOEX_BT_PROFILE_A2DP: + A_MEMCPY(&pArbtcoexConfig->info.a2dpConfigCmd, &pBtcoexConfig->info.a2dpConfigCmd, + sizeof(WMI_SET_BTCOEX_A2DP_CONFIG_CMD)); + break; + case WMI_BTCOEX_BT_PROFILE_ACLCOEX: + A_MEMCPY(&pArbtcoexConfig->info.aclcoexConfig, &pBtcoexConfig->info.aclcoexConfig, + sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD)); + break; + case WMI_BTCOEX_BT_PROFILE_INQUIRY_PAGE: + A_MEMCPY(&pArbtcoexConfig->info.btinquiryPageConfigCmd, &pBtcoexConfig->info.btinquiryPageConfigCmd, + sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD)); + break; + } + if (ar->statsUpdatePending) { + ar->statsUpdatePending = FALSE; + wake_up(&arEvent); + } +} + +void +ar6000_btcoex_stats_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len) +{ + WMI_BTCOEX_STATS_EVENT *pBtcoexStats = (WMI_BTCOEX_STATS_EVENT *)ptr; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("AR6000 BTCOEX CONFIG EVENT \n")); + + A_MEMCPY(&ar->arBtcoexStats, pBtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT)); + + if (ar->statsUpdatePending) { + ar->statsUpdatePending = FALSE; + wake_up(&arEvent); + } + +} +module_init(ar6000_init_module); +module_exit(ar6000_cleanup_module); + +/* Init cookie queue */ +static void +ar6000_cookie_init(AR_SOFTC_T *ar) +{ + A_UINT32 i; + + ar->arCookieList = NULL; + ar->arCookieCount = 0; + + A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem)); + + for (i = 0; i < MAX_COOKIE_NUM; i++) { + ar6000_free_cookie(ar, &s_ar_cookie_mem[i]); + } +} + +/* cleanup cookie queue */ +static void +ar6000_cookie_cleanup(AR_SOFTC_T *ar) +{ + /* It is gone .... */ + ar->arCookieList = NULL; + ar->arCookieCount = 0; +} + +/* Init cookie queue */ +static void +ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie) +{ + /* Insert first */ + A_ASSERT(ar != NULL); + A_ASSERT(cookie != NULL); + + cookie->arc_list_next = ar->arCookieList; + ar->arCookieList = cookie; + ar->arCookieCount++; +} + +/* cleanup cookie queue */ +static struct ar_cookie * +ar6000_alloc_cookie(AR_SOFTC_T *ar) +{ + struct ar_cookie *cookie; + + cookie = ar->arCookieList; + if(cookie != NULL) + { + ar->arCookieList = cookie->arc_list_next; + ar->arCookieCount--; + } + + return cookie; +} + +#ifdef SEND_EVENT_TO_APP +/* + * This function is used to send event which come from taget to + * the application. The buf which send to application is include + * the event ID and event content. + */ +#define EVENT_ID_LEN 2 +void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId, + A_UINT8 *datap, int len) +{ + +#if (WIRELESS_EXT >= 15) + +/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */ + + char *buf; + A_UINT16 size; + union iwreq_data wrqu; + + size = len + EVENT_ID_LEN; + + if (size > IW_CUSTOM_MAX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n", + eventId, size, IW_CUSTOM_MAX)); + return; + } + + buf = A_MALLOC_NOWAIT(size); + if (NULL == buf){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size)); + return; + } + + A_MEMZERO(buf, size); + A_MEMCPY(buf, &eventId, EVENT_ID_LEN); + A_MEMCPY(buf+EVENT_ID_LEN, datap, len); + + //AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("event ID = %d,len = %d\n",*(A_UINT16*)buf, size)); + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = size; + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + + A_FREE(buf); +#endif + + +} + +/* + * This function is used to send events larger than 256 bytes + * to the application. The buf which is sent to application + * includes the event ID and event content. + */ +void ar6000_send_generic_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId, + A_UINT8 *datap, int len) +{ + +#if (WIRELESS_EXT >= 18) + +/* IWEVGENIE exists in wireless extensions version 18 onwards */ + + char *buf; + A_UINT16 size; + union iwreq_data wrqu; + + size = len + EVENT_ID_LEN; + + if (size > IW_GENERIC_IE_MAX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVGENIE (max=%d) \n", + eventId, size, IW_GENERIC_IE_MAX)); + return; + } + + buf = A_MALLOC_NOWAIT(size); + if (NULL == buf){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size)); + return; + } + + A_MEMZERO(buf, size); + A_MEMCPY(buf, &eventId, EVENT_ID_LEN); + A_MEMCPY(buf+EVENT_ID_LEN, datap, len); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = size; + wireless_send_event(ar->arNetDev, IWEVGENIE, &wrqu, buf); + + A_FREE(buf); + +#endif /* (WIRELESS_EXT >= 18) */ + +} +#endif /* SEND_EVENT_TO_APP */ + + +void +ar6000_tx_retry_err_event(void *devt) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Tx retries reach maximum!\n")); +} + +void +ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr) +{ + WMI_SNR_THRESHOLD_EVENT event; + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + event.range = newThreshold; + event.snr = snr; + + ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (A_UINT8 *)&event, + sizeof(WMI_SNR_THRESHOLD_EVENT)); +} + +void +ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("lq threshold range %d, lq %d\n", newThreshold, lq)); +} + + + +A_UINT32 +a_copy_to_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_to_user(to, from, n)); +} + +A_UINT32 +a_copy_from_user(void *to, const void *from, A_UINT32 n) +{ + return(copy_from_user(to, from, n)); +} + + +A_STATUS +ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result) +{ + + A_STATUS ret = 0; + + switch(cfgParam) + { + case AR6000_DRIVER_CFG_GET_WLANNODECACHING: + *((A_UINT32 *)result) = wlanNodeCaching; + break; + case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS: + *((A_UINT32 *)result) = logWmiRawMsgs; + break; + default: + ret = EINVAL; + break; + } + + return ret; +} + +void +ar6000_keepalive_rx(void *devt, A_UINT8 configured) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + + ar->arKeepaliveConfigured = configured; + wake_up(&arEvent); +} + +void +ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList, + A_UINT8 *bssidList) +{ + A_UINT8 i, j; + + A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID); + + for (i = 0; i < numPMKID; i++) { + A_PRINTF("\nBSSID %d ", i); + for (j = 0; j < ATH_MAC_LEN; j++) { + A_PRINTF("%2.2x", bssidList[j]); + } + bssidList += (ATH_MAC_LEN + WMI_PMKID_LEN); + A_PRINTF("\nPMKID %d ", i); + for (j = 0; j < WMI_PMKID_LEN; j++) { + A_PRINTF("%2.2x", pmkidList->pmkid[j]); + } + pmkidList = (WMI_PMKID *)((A_UINT8 *)pmkidList + ATH_MAC_LEN + + WMI_PMKID_LEN); + } +} + +void ar6000_pspoll_event(AR_SOFTC_T *ar,A_UINT8 aid) +{ + sta_t *conn=NULL; + A_BOOL isPsqEmpty = FALSE; + + conn = ieee80211_find_conn_for_aid(ar, aid); + + /* If the PS q for this STA is not empty, dequeue and send a pkt from + * the head of the q. Also update the More data bit in the WMI_DATA_HDR + * if there are more pkts for this STA in the PS q. If there are no more + * pkts for this STA, update the PVB for this STA. + */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + + if (isPsqEmpty) { + /* TODO:No buffered pkts for this STA. Send out a NULL data frame */ + } else { + struct sk_buff *skb = NULL; + + A_MUTEX_LOCK(&conn->psqLock); + skb = A_NETBUF_DEQUEUE(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + /* Set the STA flag to PSPolled, so that the frame will go out */ + STA_SET_PS_POLLED(conn); + ar6000_data_tx(skb, ar->arNetDev); + STA_CLR_PS_POLLED(conn); + + /* Clear the PVB for this STA if the queue has become empty */ + A_MUTEX_LOCK(&conn->psqLock); + isPsqEmpty = A_NETBUF_QUEUE_EMPTY(&conn->psq); + A_MUTEX_UNLOCK(&conn->psqLock); + + if (isPsqEmpty) { + wmi_set_pvb_cmd(ar->arWmi, conn->aid, 0); + } + } +} + +void ar6000_dtimexpiry_event(AR_SOFTC_T *ar) +{ + A_BOOL isMcastQueued = FALSE; + struct sk_buff *skb = NULL; + + /* If there are no associated STAs, ignore the DTIM expiry event. + * There can be potential race conditions where the last associated + * STA may disconnect & before the host could clear the 'Indicate DTIM' + * request to the firmware, the firmware would have just indicated a DTIM + * expiry event. The race is between 'clear DTIM expiry cmd' going + * from the host to the firmware & the DTIM expiry event happening from + * the firmware to the host. + */ + if (ar->sta_list_index == 0) { + return; + } + + A_MUTEX_LOCK(&ar->mcastpsqLock); + isMcastQueued = A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + A_ASSERT(isMcastQueued == FALSE); + + /* Flush the mcast psq to the target */ + /* Set the STA flag to DTIMExpired, so that the frame will go out */ + ar->DTIMExpired = TRUE; + + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + ar6000_data_tx(skb, ar->arNetDev); + + A_MUTEX_LOCK(&ar->mcastpsqLock); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + + /* Reset the DTIMExpired flag back to 0 */ + ar->DTIMExpired = FALSE; + + /* Clear the LSB of the BitMapCtl field of the TIM IE */ + wmi_set_pvb_cmd(ar->arWmi, MCAST_AID, 0); +} + +void +read_rssi_compensation_param(AR_SOFTC_T *ar) +{ + HIF_DEVICE *device= ar->arHifDevice; + A_UINT32 rssicomp; + A_UINT32 param; + + if (BMIReadMemory(device, + HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data), + (A_UCHAR *)&rssicomp, + 4)!= A_OK) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadMemory for reading board data address failed \n")); + return; + } + + rssicomp += 0x40; + if (BMIReadSOCRegister(device, rssicomp, ¶m)!= A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n")); + return ; + } + rssi_compensation_param.a_enable = (A_INT16) (param & 0xffff); + rssi_compensation_param.a_param_a = (A_INT16) (param >> 16); + + rssicomp += 4; + if (BMIReadSOCRegister(device, rssicomp, ¶m)!= A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n")); + return ; + } + rssi_compensation_param.a_param_b = (A_INT16) (param & 0xffff); + rssi_compensation_param.bg_enable = (A_INT16) (param >> 16); + + rssicomp += 4; + if (BMIReadSOCRegister(device, rssicomp, ¶m)!= A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n")); + return ; + } + rssi_compensation_param.bg_param_a = (A_INT16) (param & 0xffff); + rssi_compensation_param.bg_param_b = (A_INT16) (param >> 16); + + if (rssi_compensation_param.bg_enable != 0x1) + rssi_compensation_param.bg_enable = 0; + + if (rssi_compensation_param.a_enable != 0x1) + rssi_compensation_param.a_enable = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("compensation flag = %d a = %d b = %d\n",\ + rssi_compensation_param.bg_enable, + rssi_compensation_param.bg_param_a, + rssi_compensation_param.bg_param_b)); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("compensation flag = %d a = %d b = %d\n",\ + rssi_compensation_param.a_enable, + rssi_compensation_param.a_param_a, + rssi_compensation_param.a_param_b)); + + return ; +} + +A_INT32 +rssi_compensation_calc_tcmd(A_UINT32 freq, A_INT32 rssi, A_UINT32 totalPkt) +{ + + if (freq > 5000) + { + if (rssi_compensation_param.a_enable) + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n")); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation = %d, totalPkt = %d\n", rssi,totalPkt)); + rssi = rssi * rssi_compensation_param.a_param_a + totalPkt * rssi_compensation_param.a_param_b; + rssi = (rssi-50) /100; + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi)); + } + } + else + { + if (rssi_compensation_param.bg_enable) + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n")); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation = %d, totalPkt = %d\n", rssi,totalPkt)); + rssi = rssi * rssi_compensation_param.bg_param_a + totalPkt * rssi_compensation_param.bg_param_b; + rssi = (rssi-50) /100; + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi)); + } + } + + return rssi; +} + +A_INT16 +rssi_compensation_calc(AR_SOFTC_T *ar, A_INT16 rssi) +{ + if (ar->arBssChannel > 5000) + { + if (rssi_compensation_param.a_enable) + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n")); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation = %d\n", rssi)); + rssi = rssi * rssi_compensation_param.a_param_a + rssi_compensation_param.a_param_b; + rssi = (rssi-50) /100; + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi)); + } + } + else + { + if (rssi_compensation_param.bg_enable) + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n")); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before compensation = %d\n", rssi)); + rssi = rssi * rssi_compensation_param.bg_param_a + rssi_compensation_param.bg_param_b; + rssi = (rssi-50) /100; + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after compensation = %d\n", rssi)); + } + } + + return rssi; +} + +A_INT16 +rssi_compensation_reverse_calc(AR_SOFTC_T *ar, A_INT16 rssi, A_BOOL Above) +{ + A_INT16 i; + + if (ar->arBssChannel > 5000) + { + if (rssi_compensation_param.a_enable) + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11a\n")); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before rev compensation = %d\n", rssi)); + rssi = rssi * 100; + rssi = (rssi - rssi_compensation_param.a_param_b) / rssi_compensation_param.a_param_a; + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after rev compensation = %d\n", rssi)); + } + } + else + { + if (rssi_compensation_param.bg_enable) + { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, (">>> 11bg\n")); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi before rev compensation = %d\n", rssi)); + + if (Above) { + for (i=95; i>=0; i--) { + if (rssi <= rssi_compensation_table[i]) { + rssi = 0 - i; + break; + } + } + } else { + for (i=0; i<=95; i++) { + if (rssi >= rssi_compensation_table[i]) { + rssi = 0 - i; + break; + } + } + } + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("rssi after rev compensation = %d\n", rssi)); + } + } + + return rssi; +} + +#ifdef WAPI_ENABLE +void ap_wapi_rekey_event(AR_SOFTC_T *ar, A_UINT8 type, A_UINT8 *mac) +{ + union iwreq_data wrqu; + A_CHAR buf[20]; + + A_MEMZERO(buf, sizeof(buf)); + + strcpy(buf, "WAPI_REKEY"); + buf[10] = type; + A_MEMCPY(&buf[11], mac, ATH_MAC_LEN); + + A_MEMZERO(&wrqu, sizeof(wrqu)); + wrqu.data.length = 10+1+ATH_MAC_LEN; + wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf); + + A_PRINTF("WAPI REKEY - %d - %02x:%02x\n", type, mac[4], mac[5]); +} +#endif + +#ifdef USER_KEYS +static A_STATUS + +ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl) +{ + A_STATUS status = A_OK; + struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik; + struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik; + CRYPTO_TYPE keyType = ar->user_saved_keys.keyType; + + if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (uik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix, + ar->user_saved_keys.keyType, PAIRWISE_USAGE, + uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc, + uik->ik_keydata, key_op_ctrl, uik->ik_macaddr, SYNC_BEFORE_WMIFLAG); + } + + } else { + status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata); + } + + if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) { + if (NONE_CRYPT == keyType) { + goto _reinstall_keys_out; + } + + if (bik->ik_keylen) { + status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix, + ar->user_saved_keys.keyType, GROUP_USAGE, + bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc, + bik->ik_keydata, key_op_ctrl, bik->ik_macaddr, NO_SYNC_WMIFLAG); + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata); + } + +_reinstall_keys_out: + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT; + ar->user_key_ctrl = 0; + + return status; +} +#endif /* USER_KEYS */ + + +void +ar6000_dset_open_req( + void *context, + A_UINT32 id, + A_UINT32 targHandle, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +void +ar6000_dset_close( + void *context, + A_UINT32 access_cookie) +{ + return; +} + +void +ar6000_dset_data_req( + void *context, + A_UINT32 accessCookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targBuf, + A_UINT32 targReplyFn, + A_UINT32 targReplyArg) +{ +} + +int +ar6000_ap_mode_profile_commit(struct ar6_softc *ar) +{ + WMI_CONNECT_CMD p; + unsigned long flags; + + /* No change in AP's profile configuration */ + if(ar->ap_profile_flag==0) { + A_PRINTF("COMMIT: No change in profile!!!\n"); + return -ENODATA; + } + + if(!ar->arSsidLen) { + A_PRINTF("SSID not set!!!\n"); + return -ECHRNG; + } + + switch(ar->arAuthMode) { + case NONE_AUTH: + if((ar->arPairwiseCrypto != NONE_CRYPT) && +#ifdef WAPI_ENABLE + (ar->arPairwiseCrypto != WAPI_CRYPT) && +#endif + (ar->arPairwiseCrypto != WEP_CRYPT)) { + A_PRINTF("Cipher not supported in AP mode Open auth\n"); + return -EOPNOTSUPP; + } + break; + case WPA_PSK_AUTH: + case WPA2_PSK_AUTH: + case (WPA_PSK_AUTH|WPA2_PSK_AUTH): + break; + default: + A_PRINTF("This key mgmt type not supported in AP mode\n"); + return -EOPNOTSUPP; + } + + /* Update the arNetworkType */ + ar->arNetworkType = ar->arNextMode; + + A_MEMZERO(&p,sizeof(p)); + p.ssidLength = ar->arSsidLen; + A_MEMCPY(p.ssid,ar->arSsid,p.ssidLength); + p.channel = ar->arChannelHint; + p.networkType = ar->arNetworkType; + + p.dot11AuthMode = ar->arDot11AuthMode; + p.authMode = ar->arAuthMode; + p.pairwiseCryptoType = ar->arPairwiseCrypto; + p.pairwiseCryptoLen = ar->arPairwiseCryptoLen; + p.groupCryptoType = ar->arGroupCrypto; + p.groupCryptoLen = ar->arGroupCryptoLen; + p.ctrl_flags = ar->arConnectCtrlFlags; + + ar->arConnected = FALSE; + + wmi_ap_profile_commit(ar->arWmi, &p); + spin_lock_irqsave(&ar->arLock, flags); + ar->arConnected = TRUE; + netif_carrier_on(ar->arNetDev); + spin_unlock_irqrestore(&ar->arLock, flags); + ar->ap_profile_flag = 0; + return 0; +} + + +A_STATUS +ar6000_connect_to_ap(struct ar6_softc *ar) +{ + /* The ssid length check prevents second "essid off" from the user, + to be treated as a connect cmd. The second "essid off" is ignored. + */ + if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) && ar->arNetworkType!=AP_NETWORK) + { + A_STATUS status; + if((ADHOC_NETWORK != ar->arNetworkType) && + (NONE_AUTH==ar->arAuthMode) && + (WEP_CRYPT==ar->arPairwiseCrypto)) { + ar6000_install_static_wep_keys(ar); + } + + if (!ar->arUserBssFilter) { + if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) { + return -EIO; + } + } +#ifdef WAPI_ENABLE + if (ar->arWapiEnable) { + ar->arPairwiseCrypto = WAPI_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = WAPI_CRYPT; + ar->arGroupCryptoLen = 0; + ar->arAuthMode = NONE_AUTH; + ar->arConnectCtrlFlags |= CONNECT_IGNORE_WPAx_GROUP_CIPHER; + } +#endif + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Connect called with authmode %d dot11 auth %d"\ + " PW crypto %d PW crypto Len %d GRP crypto %d"\ + " GRP crypto Len %d\n", + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen)); + reconnect_flag = 0; + /* Set the listen interval into 1000TUs. This value will be indicated to Ap in the conn. + later set it back locally at the STA to 100/1000 TUs depending on the power mode */ + if ((ar->arNetworkType == INFRA_NETWORK)) { + wmi_listeninterval_cmd(ar->arWmi, A_MAX_WOW_LISTEN_INTERVAL, 0); + } + status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto,ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags); + if (status != A_OK) { + wmi_listeninterval_cmd(ar->arWmi, ar->arListenInterval, 0); + if (!ar->arUserBssFilter) { + wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0); + } + return status; + } + + if ((!(ar->arConnectCtrlFlags & CONNECT_DO_WPA_OFFLOAD)) && + ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode))) + { + A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0); + } + + ar->arConnectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD; + + ar->arConnectPending = TRUE; + return status; + } + return A_ERROR; +} + +A_STATUS +ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state) +{ + A_STATUS status = A_OK; + AR6000_WLAN_STATE oldstate = ar->arWlanState; + if (ar->arWmiReady == FALSE || + (state!=WLAN_DISABLED && state!=WLAN_ENABLED)) { + return A_ERROR; + } + if (state == ar->arWlanState) { + return A_OK; + } + ar->arWlanState = state; + do { + if (ar->arWlanState == WLAN_ENABLED) { + /* Enable foreground scanning */ + if (wmi_scanparams_cmd(ar->arWmi, ar->scParams.fg_start_period, + ar->scParams.fg_end_period, + ar->scParams.bg_period, + ar->scParams.minact_chdwell_time, + ar->scParams.maxact_chdwell_time, + ar->scParams.pas_chdwell_time, + ar->scParams.shortScanRatio, + ar->scParams.scanCtrlFlags, + ar->scParams.max_dfsch_act_time, + ar->scParams.maxact_scan_per_ssid) != A_OK) { + status = A_ERROR; + break; + } + if (ar->arSsidLen) { + if (ar6000_connect_to_ap(ar) != A_OK) { + status = A_ERROR; + break; + } + } + } else { + /* Disconnect from the AP and disable foreground scanning */ + AR6000_SPIN_LOCK(&ar->arLock, 0); + if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + wmi_disconnect_cmd(ar->arWmi); + } else { + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0, 0, 0) != A_OK) { + status = A_ERROR; + break; + } + } + } while (0); + if (status!=A_OK) { + ar->arWlanState = oldstate; + } + return status; +} + +A_STATUS +ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie) +{ + sta_t *conn = NULL; + conn = ieee80211_find_conn(ar, wpaie->wpa_macaddr); + + A_MEMZERO(wpaie->wpa_ie, IEEE80211_MAX_IE); + A_MEMZERO(wpaie->rsn_ie, IEEE80211_MAX_IE); + + if(conn) { + A_MEMCPY(wpaie->wpa_ie, conn->wpa_ie, IEEE80211_MAX_IE); + } + + return 0; +} + +A_STATUS +is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd) +{ + if(cmd >= SIOCSIWCOMMIT && cmd <= SIOCGIWPOWER) { + cmd -= SIOCSIWCOMMIT; + if(sioctl_filter[cmd] == 0xFF) return A_OK; + if(sioctl_filter[cmd] & mode) return A_OK; + } else if(cmd >= SIOCIWFIRSTPRIV && cmd <= (SIOCIWFIRSTPRIV+30)) { + cmd -= SIOCIWFIRSTPRIV; + if(pioctl_filter[cmd] == 0xFF) return A_OK; + if(pioctl_filter[cmd] & mode) return A_OK; + } else { + return A_ERROR; + } + return A_ENOTSUP; +} + +A_STATUS +is_xioctl_allowed(A_UINT8 mode, int cmd) +{ + if(sizeof(xioctl_filter)-1 < cmd) { + A_PRINTF("Filter for this cmd=%d not defined\n",cmd); + return 0; + } + if(xioctl_filter[cmd] == 0xFF) return A_OK; + if(xioctl_filter[cmd] & mode) return A_OK; + return A_ERROR; +} + +#ifdef WAPI_ENABLE +int +ap_set_wapi_key(struct ar6_softc *ar, void *ikey) +{ + struct ieee80211req_key *ik = (struct ieee80211req_key *)ikey; + KEY_USAGE keyUsage = 0; + A_STATUS status; + + if (A_MEMCMP(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN) == 0) { + keyUsage = GROUP_USAGE; + } else { + keyUsage = PAIRWISE_USAGE; + } + A_PRINTF("WAPI_KEY: Type:%d ix:%d mac:%02x:%02x len:%d\n", + keyUsage, ik->ik_keyix, ik->ik_macaddr[4], ik->ik_macaddr[5], + ik->ik_keylen); + + status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, WAPI_CRYPT, keyUsage, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + if (A_OK != status) { + return -EIO; + } + return 0; +} +#endif + +void ar6000_peer_event( + void *context, + A_UINT8 eventCode, + A_UINT8 *macAddr) +{ + A_UINT8 pos; + + for (pos=0;pos<6;pos++) + printk("%02x: ",*(macAddr+pos)); + printk("\n"); +} + +#ifdef HTC_TEST_SEND_PKTS +#define HTC_TEST_DUPLICATE 8 +static void DoHTCSendPktsTest(AR_SOFTC_T *ar, int MapNo, HTC_ENDPOINT_ID eid, struct sk_buff *dupskb) +{ + struct ar_cookie *cookie; + struct ar_cookie *cookieArray[HTC_TEST_DUPLICATE]; + struct sk_buff *new_skb; + int i; + int pkts = 0; + HTC_PACKET_QUEUE pktQueue; + EPPING_HEADER *eppingHdr; + + eppingHdr = A_NETBUF_DATA(dupskb); + + if (eppingHdr->Cmd_h == EPPING_CMD_NO_ECHO) { + /* skip test if this is already a tx perf test */ + return; + } + + for (i = 0; i < HTC_TEST_DUPLICATE; i++,pkts++) { + AR6000_SPIN_LOCK(&ar->arLock, 0); + cookie = ar6000_alloc_cookie(ar); + if (cookie != NULL) { + ar->arTxPending[eid]++; + ar->arTotalTxDataPending++; + } + + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + + if (NULL == cookie) { + break; + } + + new_skb = A_NETBUF_ALLOC(A_NETBUF_LEN(dupskb)); + + if (new_skb == NULL) { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar6000_free_cookie(ar,cookie); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + break; + } + + A_NETBUF_PUT_DATA(new_skb, A_NETBUF_DATA(dupskb), A_NETBUF_LEN(dupskb)); + cookie->arc_bp[0] = (A_UINT32)new_skb; + cookie->arc_bp[1] = MapNo; + SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt, + cookie, + A_NETBUF_DATA(new_skb), + A_NETBUF_LEN(new_skb), + eid, + AR6K_DATA_PKT_TAG); + + cookieArray[i] = cookie; + + { + EPPING_HEADER *pHdr = (EPPING_HEADER *)A_NETBUF_DATA(new_skb); + pHdr->Cmd_h = EPPING_CMD_NO_ECHO; /* do not echo the packet */ + } + } + + if (pkts == 0) { + return; + } + + INIT_HTC_PACKET_QUEUE(&pktQueue); + + for (i = 0; i < pkts; i++) { + HTC_PACKET_ENQUEUE(&pktQueue,&cookieArray[i]->HtcPkt); + } + + HTCSendPktsMultiple(ar->arHtcTarget, &pktQueue); + +} + +#endif + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +EXPORT_SYMBOL(setupbtdev); +#endif diff --git a/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c b/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c new file mode 100644 index 000000000000..62f5f2158c18 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/ar6000_raw_if.c @@ -0,0 +1,455 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#include "ar6000_drv.h" + +#ifdef HTC_RAW_INTERFACE + +static void +ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *busy; + HTC_RAW_STREAM_ID streamID; + AR_RAW_HTC_T *arRaw = ar->arRawHtc; + + busy = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(busy != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&arRaw->raw_htc_read_sem[streamID])) { +#else + if (down_interruptible(&arRaw->raw_htc_read_sem[streamID])) { +#endif /* CF */ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to down the semaphore\n")); + } + + A_ASSERT((pPacket->Status != A_OK) || + (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN))); + + busy->length = pPacket->ActualLength + HTC_HEADER_LEN; + busy->currPtr = HTC_HEADER_LEN; + arRaw->read_buffer_available[streamID] = TRUE; + //AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("raw read cb: 0x%X 0x%X \n", busy->currPtr,busy->length); + up(&arRaw->raw_htc_read_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Waking up the StreamID(%d) read process\n", streamID)); + wake_up_interruptible(&arRaw->raw_htc_read_queue[streamID]); +} + +static void +ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)Context; + raw_htc_buffer *free; + HTC_RAW_STREAM_ID streamID; + AR_RAW_HTC_T *arRaw = ar->arRawHtc; + + free = (raw_htc_buffer *)pPacket->pPktContext; + A_ASSERT(free != NULL); + + if (pPacket->Status == A_ECANCELED) { + /* + * HTC provides A_ECANCELED status when it doesn't want to be refilled + * (probably due to a shutdown) + */ + return; + } + + streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint); + A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED); + +#ifdef CF + if (down_trylock(&arRaw->raw_htc_write_sem[streamID])) { +#else + if (down_interruptible(&arRaw->raw_htc_write_sem[streamID])) { +#endif + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to down the semaphore\n")); + } + + A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN)); + + free->length = 0; + arRaw->write_buffer_available[streamID] = TRUE; + up(&arRaw->raw_htc_write_sem[streamID]); + + /* Signal the waiting process */ + AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Waking up the StreamID(%d) write process\n", streamID)); + wake_up_interruptible(&arRaw->raw_htc_write_queue[streamID]); +} + +/* connect to a service */ +static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID) +{ + A_STATUS status; + HTC_SERVICE_CONNECT_RESP response; + A_UINT8 streamNo; + HTC_SERVICE_CONNECT_REQ connect; + + do { + + A_MEMZERO(&connect,sizeof(connect)); + /* pass the stream ID as meta data to the RAW streams service */ + streamNo = (A_UINT8)StreamID; + connect.pMetaData = &streamNo; + connect.MetaDataLength = sizeof(A_UINT8); + /* these fields are the same for all endpoints */ + connect.EpCallbacks.pContext = ar; + connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb; + connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb; + /* simple interface, we don't need these optional callbacks */ + connect.EpCallbacks.EpRecvRefill = NULL; + connect.EpCallbacks.EpSendFull = NULL; + connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM; + + /* connect to the raw streams service, we may be able to get 1 or more + * connections, depending on WHAT is running on the target */ + connect.ServiceID = HTC_RAW_STREAMS_SVC; + + A_MEMZERO(&response,sizeof(response)); + + /* try to connect to the raw stream, it is okay if this fails with + * status HTC_SERVICE_NO_MORE_EP */ + status = HTCConnectService(ar->arHtcTarget, + &connect, + &response); + + if (A_FAILED(status)) { + if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HTC RAW , No more streams allowed \n")); + status = A_OK; + } + break; + } + + /* set endpoint mapping for the RAW HTC streams */ + arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint); + + AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("HTC RAW : stream ID: %d, endpoint: %d\n", + StreamID, arRawStream2EndpointID(ar,StreamID))); + + } while (FALSE); + + return status; +} + +int ar6000_htc_raw_open(AR_SOFTC_T *ar) +{ + A_STATUS status; + int streamID, endPt, count2; + raw_htc_buffer *buffer; + HTC_SERVICE_ID servicepriority; + AR_RAW_HTC_T *arRaw = ar->arRawHtc; + if (!arRaw) { + arRaw = ar->arRawHtc = A_MALLOC(sizeof(AR_RAW_HTC_T)); + if (arRaw) { + A_MEMZERO(arRaw, sizeof(AR_RAW_HTC_T)); + } + } + A_ASSERT(ar->arHtcTarget != NULL); + if (!arRaw) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Faile to allocate memory for HTC RAW interface\n")); + return -ENOMEM; + } + /* wait for target */ + status = HTCWaitTarget(ar->arHtcTarget); + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HTCWaitTarget failed (%d)\n", status)); + return -ENODEV; + } + + for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) { + arRaw->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED; + } + + for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) { + /* Initialize the data structures */ + init_MUTEX(&arRaw->raw_htc_read_sem[streamID]); + init_MUTEX(&arRaw->raw_htc_write_sem[streamID]); + init_waitqueue_head(&arRaw->raw_htc_read_queue[streamID]); + init_waitqueue_head(&arRaw->raw_htc_write_queue[streamID]); + + /* try to connect to the raw service */ + status = ar6000_connect_raw_service(ar,streamID); + + if (A_FAILED(status)) { + break; + } + + if (arRawStream2EndpointID(ar,streamID) == 0) { + break; + } + + for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = &arRaw->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + buffer = &arRaw->raw_htc_read_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + + SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket, + buffer, + buffer->data, + HTC_RAW_BUFFER_SIZE, + arRawStream2EndpointID(ar,streamID)); + + /* Queue buffers to HTC for receive */ + if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK) + { + BMIInit(); + return -EIO; + } + } + + for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) { + /* Initialize the receive buffers */ + buffer = &arRaw->raw_htc_write_buffer[streamID][count2]; + memset(buffer, 0, sizeof(raw_htc_buffer)); + } + + arRaw->read_buffer_available[streamID] = FALSE; + arRaw->write_buffer_available[streamID] = TRUE; + } + + if (A_FAILED(status)) { + return -EIO; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("HTC RAW, number of streams the target supports: %d \n", streamID)); + + servicepriority = HTC_RAW_STREAMS_SVC; /* only 1 */ + + /* set callbacks and priority list */ + HTCSetCreditDistribution(ar->arHtcTarget, + ar, + NULL, /* use default */ + NULL, /* use default */ + &servicepriority, + 1); + + /* Start the HTC component */ + if ((status = HTCStart(ar->arHtcTarget)) != A_OK) { + BMIInit(); + return -EIO; + } + + (ar)->arRawIfInit = TRUE; + + return 0; +} + +int ar6000_htc_raw_close(AR_SOFTC_T *ar) +{ + A_PRINTF("ar6000_htc_raw_close called \n"); + HTCStop(ar->arHtcTarget); + + /* reset the device */ + ar6000_reset_device(ar->arHifDevice, ar->arTargetType, TRUE, FALSE); + /* Initialize the BMI component */ + BMIInit(); + + if (ar->arRawHtc) { + A_FREE(ar->arRawHtc); + ar->arRawHtc = NULL; + } + return 0; +} + +raw_htc_buffer * +get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID) +{ + int count; + raw_htc_buffer *busy; + AR_RAW_HTC_T *arRaw = ar->arRawHtc; + + /* Check for data */ + for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) { + busy = &arRaw->raw_htc_read_buffer[StreamID][count]; + if (busy->length) { + break; + } + } + if (busy->length) { + arRaw->read_buffer_available[StreamID] = TRUE; + } else { + arRaw->read_buffer_available[StreamID] = FALSE; + } + + return busy; +} + +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int readPtr; + raw_htc_buffer *busy; + AR_RAW_HTC_T *arRaw = ar->arRawHtc; + + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("StreamID(%d) not connected! \n", StreamID)); + return -EFAULT; + } + + if (down_interruptible(&arRaw->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + + busy = get_filled_buffer(ar,StreamID); + while (!arRaw->read_buffer_available[StreamID]) { + up(&arRaw->raw_htc_read_sem[StreamID]); + + /* Wait for the data */ + AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Sleeping StreamID(%d) read process\n", StreamID)); + if (wait_event_interruptible(arRaw->raw_htc_read_queue[StreamID], + arRaw->read_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&arRaw->raw_htc_read_sem[StreamID])) { + return -ERESTARTSYS; + } + busy = get_filled_buffer(ar,StreamID); + } + + /* Read the data */ + readPtr = busy->currPtr; + if (length > busy->length - HTC_HEADER_LEN) { + length = busy->length - HTC_HEADER_LEN; + } + if (copy_to_user(buffer, &busy->data[readPtr], length)) { + up(&arRaw->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + busy->currPtr += length; + + if (busy->currPtr == busy->length) + { + busy->currPtr = 0; + busy->length = 0; + HTC_PACKET_RESET_RX(&busy->HTCPacket); + //AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("raw read ioctl: ep for packet:%d \n", busy->HTCPacket.Endpoint)); + HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket); + } + arRaw->read_buffer_available[StreamID] = FALSE; + up(&arRaw->raw_htc_read_sem[StreamID]); + + return length; +} + +static raw_htc_buffer * +get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID) +{ + int count; + raw_htc_buffer *free; + AR_RAW_HTC_T *arRaw = ar->arRawHtc; + + free = NULL; + for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) { + free = &arRaw->raw_htc_write_buffer[StreamID][count]; + if (free->length == 0) { + break; + } + } + if (!free->length) { + arRaw->write_buffer_available[StreamID] = TRUE; + } else { + arRaw->write_buffer_available[StreamID] = FALSE; + } + + return free; +} + +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t length) +{ + int writePtr; + raw_htc_buffer *free; + AR_RAW_HTC_T *arRaw = ar->arRawHtc; + if (arRawStream2EndpointID(ar,StreamID) == 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("StreamID(%d) not connected! \n", StreamID)); + return -EFAULT; + } + + if (down_interruptible(&arRaw->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + + /* Search for a free buffer */ + free = get_free_buffer(ar,StreamID); + + /* Check if there is space to write else wait */ + while (!arRaw->write_buffer_available[StreamID]) { + up(&arRaw->raw_htc_write_sem[StreamID]); + + /* Wait for buffer to become free */ + AR_DEBUG_PRINTF(ATH_DEBUG_HTC_RAW,("Sleeping StreamID(%d) write process\n", StreamID)); + if (wait_event_interruptible(arRaw->raw_htc_write_queue[StreamID], + arRaw->write_buffer_available[StreamID])) + { + return -EINTR; + } + if (down_interruptible(&arRaw->raw_htc_write_sem[StreamID])) { + return -ERESTARTSYS; + } + free = get_free_buffer(ar,StreamID); + } + + /* Send the data */ + writePtr = HTC_HEADER_LEN; + if (length > (HTC_RAW_BUFFER_SIZE - HTC_HEADER_LEN)) { + length = HTC_RAW_BUFFER_SIZE - HTC_HEADER_LEN; + } + + if (copy_from_user(&free->data[writePtr], buffer, length)) { + up(&arRaw->raw_htc_read_sem[StreamID]); + return -EFAULT; + } + + free->length = length; + + SET_HTC_PACKET_INFO_TX(&free->HTCPacket, + free, + &free->data[writePtr], + length, + arRawStream2EndpointID(ar,StreamID), + AR6K_DATA_PKT_TAG); + + HTCSendPkt(ar->arHtcTarget,&free->HTCPacket); + + arRaw->write_buffer_available[StreamID] = FALSE; + up(&arRaw->raw_htc_write_sem[StreamID]); + + return length; +} +#endif /* HTC_RAW_INTERFACE */ diff --git a/drivers/net/wireless/ath6kl/os/linux/cfg80211.c b/drivers/net/wireless/ath6kl/os/linux/cfg80211.c new file mode 100644 index 000000000000..402f98931b46 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/cfg80211.c @@ -0,0 +1,1467 @@ +/* + * + * Copyright (c) 2004-2010 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + + +#include +#include +#include +#include +#include + +#include "ar6000_drv.h" + + +extern A_WAITQUEUE_HEAD arEvent; +extern unsigned int wmitimeout; +extern int reconnect_flag; + + +#define RATETAB_ENT(_rate, _rateid, _flags) { \ + .bitrate = (_rate), \ + .flags = (_flags), \ + .hw_value = (_rateid), \ +} + +#define CHAN2G(_channel, _freq, _flags) { \ + .band = IEEE80211_BAND_2GHZ, \ + .hw_value = (_channel), \ + .center_freq = (_freq), \ + .flags = (_flags), \ + .max_antenna_gain = 0, \ + .max_power = 30, \ +} + +#define CHAN5G(_channel, _flags) { \ + .band = IEEE80211_BAND_5GHZ, \ + .hw_value = (_channel), \ + .center_freq = 5000 + (5 * (_channel)), \ + .flags = (_flags), \ + .max_antenna_gain = 0, \ + .max_power = 30, \ +} + +static struct +ieee80211_rate ar6k_rates[] = { + RATETAB_ENT(10, 0x1, 0), + RATETAB_ENT(20, 0x2, 0), + RATETAB_ENT(55, 0x4, 0), + RATETAB_ENT(110, 0x8, 0), + RATETAB_ENT(60, 0x10, 0), + RATETAB_ENT(90, 0x20, 0), + RATETAB_ENT(120, 0x40, 0), + RATETAB_ENT(180, 0x80, 0), + RATETAB_ENT(240, 0x100, 0), + RATETAB_ENT(360, 0x200, 0), + RATETAB_ENT(480, 0x400, 0), + RATETAB_ENT(540, 0x800, 0), +}; + +#define ar6k_a_rates (ar6k_rates + 4) +#define ar6k_a_rates_size 8 +#define ar6k_g_rates (ar6k_rates + 0) +#define ar6k_g_rates_size 12 + +static struct +ieee80211_channel ar6k_2ghz_channels[] = { + CHAN2G(1, 2412, 0), + CHAN2G(2, 2417, 0), + CHAN2G(3, 2422, 0), + CHAN2G(4, 2427, 0), + CHAN2G(5, 2432, 0), + CHAN2G(6, 2437, 0), + CHAN2G(7, 2442, 0), + CHAN2G(8, 2447, 0), + CHAN2G(9, 2452, 0), + CHAN2G(10, 2457, 0), + CHAN2G(11, 2462, 0), + CHAN2G(12, 2467, 0), + CHAN2G(13, 2472, 0), + CHAN2G(14, 2484, 0), +}; + +static struct +ieee80211_channel ar6k_5ghz_a_channels[] = { + CHAN5G(34, 0), CHAN5G(36, 0), + CHAN5G(38, 0), CHAN5G(40, 0), + CHAN5G(42, 0), CHAN5G(44, 0), + CHAN5G(46, 0), CHAN5G(48, 0), + CHAN5G(52, 0), CHAN5G(56, 0), + CHAN5G(60, 0), CHAN5G(64, 0), + CHAN5G(100, 0), CHAN5G(104, 0), + CHAN5G(108, 0), CHAN5G(112, 0), + CHAN5G(116, 0), CHAN5G(120, 0), + CHAN5G(124, 0), CHAN5G(128, 0), + CHAN5G(132, 0), CHAN5G(136, 0), + CHAN5G(140, 0), CHAN5G(149, 0), + CHAN5G(153, 0), CHAN5G(157, 0), + CHAN5G(161, 0), CHAN5G(165, 0), + CHAN5G(184, 0), CHAN5G(188, 0), + CHAN5G(192, 0), CHAN5G(196, 0), + CHAN5G(200, 0), CHAN5G(204, 0), + CHAN5G(208, 0), CHAN5G(212, 0), + CHAN5G(216, 0), +}; + +static struct +ieee80211_supported_band ar6k_band_2ghz = { + .n_channels = ARRAY_SIZE(ar6k_2ghz_channels), + .channels = ar6k_2ghz_channels, + .n_bitrates = ar6k_g_rates_size, + .bitrates = ar6k_g_rates, +}; + +static struct +ieee80211_supported_band ar6k_band_5ghz = { + .n_channels = ARRAY_SIZE(ar6k_5ghz_a_channels), + .channels = ar6k_5ghz_a_channels, + .n_bitrates = ar6k_a_rates_size, + .bitrates = ar6k_a_rates, +}; + +static int +ar6k_set_wpa_version(AR_SOFTC_T *ar, enum nl80211_wpa_versions wpa_version) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: %u\n", __func__, wpa_version)); + + if (!wpa_version) { + ar->arAuthMode = NONE_AUTH; + } else if (wpa_version & NL80211_WPA_VERSION_1) { + ar->arAuthMode = WPA_AUTH; + } else if (wpa_version & NL80211_WPA_VERSION_2) { + ar->arAuthMode = WPA2_AUTH; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("%s: %u not spported\n", __func__, wpa_version)); + return -ENOTSUPP; + } + + return A_OK; +} + +static int +ar6k_set_auth_type(AR_SOFTC_T *ar, enum nl80211_auth_type auth_type) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, auth_type)); + + switch (auth_type) { + case NL80211_AUTHTYPE_OPEN_SYSTEM: + ar->arDot11AuthMode = OPEN_AUTH; + break; + case NL80211_AUTHTYPE_SHARED_KEY: + ar->arDot11AuthMode = SHARED_AUTH; + break; + case NL80211_AUTHTYPE_NETWORK_EAP: + ar->arDot11AuthMode = LEAP_AUTH; + break; + default: + ar->arDot11AuthMode = OPEN_AUTH; + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: 0x%x not spported\n", __func__, auth_type)); + return -ENOTSUPP; + } + + return A_OK; +} + +static int +ar6k_set_cipher(AR_SOFTC_T *ar, A_UINT32 cipher, A_BOOL ucast) +{ + A_UINT8 *ar_cipher = ucast ? &ar->arPairwiseCrypto : + &ar->arGroupCrypto; + A_UINT8 *ar_cipher_len = ucast ? &ar->arPairwiseCryptoLen : + &ar->arGroupCryptoLen; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: cipher 0x%x, ucast %u\n", __func__, cipher, ucast)); + + switch (cipher) { + case 0: + case IW_AUTH_CIPHER_NONE: + *ar_cipher = NONE_CRYPT; + *ar_cipher_len = 0; + break; + case WLAN_CIPHER_SUITE_WEP40: + *ar_cipher = WEP_CRYPT; + *ar_cipher_len = 5; + break; + case WLAN_CIPHER_SUITE_WEP104: + *ar_cipher = WEP_CRYPT; + *ar_cipher_len = 13; + break; + case WLAN_CIPHER_SUITE_TKIP: + *ar_cipher = TKIP_CRYPT; + *ar_cipher_len = 0; + break; + case WLAN_CIPHER_SUITE_CCMP: + *ar_cipher = AES_CRYPT; + *ar_cipher_len = 0; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("%s: cipher 0x%x not supported\n", __func__, cipher)); + return -ENOTSUPP; + } + + return A_OK; +} + +static void +ar6k_set_key_mgmt(AR_SOFTC_T *ar, A_UINT32 key_mgmt) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: 0x%x\n", __func__, key_mgmt)); + + if (WLAN_AKM_SUITE_PSK == key_mgmt) { + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + } + } else if (WLAN_AKM_SUITE_8021X != key_mgmt) { + ar->arAuthMode = NONE_AUTH; + } +} + +static int +ar6k_cfg80211_connect(struct wiphy *wiphy, struct net_device *dev, + struct cfg80211_connect_params *sme) +{ + AR_SOFTC_T *ar = ar6k_priv(dev); + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready yet\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if(ar->bIsDestroyProgress) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: destroy in progress\n", __func__)); + return -EBUSY; + } + + if(!sme->ssid_len || IEEE80211_MAX_SSID_LEN < sme->ssid_len) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ssid invalid\n", __func__)); + return -EINVAL; + } + + if(ar->arSkipScan == TRUE && + ((sme->channel && sme->channel->center_freq == 0) || + (sme->bssid && !sme->bssid[0] && !sme->bssid[1] && !sme->bssid[2] && + !sme->bssid[3] && !sme->bssid[4] && !sme->bssid[5]))) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s:SkipScan: channel or bssid invalid\n", __func__)); + return -EINVAL; + } + + if(down_interruptible(&ar->arSem)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__)); + return -ERESTARTSYS; + } + + if(ar->bIsDestroyProgress) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, destroy in progress\n", __func__)); + up(&ar->arSem); + return -EBUSY; + } + + if(ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) { + /* + * sleep until the command queue drains + */ + wait_event_interruptible_timeout(arEvent, + ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ); + if (signal_pending(current)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: cmd queue drain timeout\n", __func__)); + up(&ar->arSem); + return -EINTR; + } + } + + if(ar->arConnected == TRUE && + ar->arSsidLen == sme->ssid_len && + !A_MEMCMP(ar->arSsid, sme->ssid, ar->arSsidLen)) { + reconnect_flag = TRUE; + status = wmi_reconnect_cmd(ar->arWmi, + ar->arReqBssid, + ar->arChannelHint); + + up(&ar->arSem); + if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_reconnect_cmd failed\n", __func__)); + return -EIO; + } + return 0; + } + + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = sme->ssid_len; + A_MEMCPY(ar->arSsid, sme->ssid, sme->ssid_len); + + if(sme->channel){ + ar->arChannelHint = sme->channel->center_freq; + } + + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + if(sme->bssid){ + if(A_MEMCMP(&sme->bssid, bcast_mac, AR6000_ETH_ADDR_LEN)) { + A_MEMCPY(ar->arReqBssid, sme->bssid, sizeof(ar->arReqBssid)); + } + } + + ar6k_set_wpa_version(ar, sme->crypto.wpa_versions); + ar6k_set_auth_type(ar, sme->auth_type); + + if(sme->crypto.n_ciphers_pairwise) { + ar6k_set_cipher(ar, sme->crypto.ciphers_pairwise[0], true); + } + ar6k_set_cipher(ar, sme->crypto.cipher_group, false); + + if(sme->crypto.n_akm_suites) { + ar6k_set_key_mgmt(ar, sme->crypto.akm_suites[0]); + } + + ar->arNetworkType = INFRA_NETWORK; + + if((sme->key_len) && + (NONE_AUTH == ar->arAuthMode) && + (WEP_CRYPT == ar->arPairwiseCrypto)) { + struct ar_key *key = NULL; + + if(sme->key_idx < WMI_MIN_KEY_INDEX || sme->key_idx > WMI_MAX_KEY_INDEX) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("%s: key index %d out of bounds\n", __func__, sme->key_idx)); + up(&ar->arSem); + return -ENOENT; + } + + key = &ar->keys[sme->key_idx]; + key->key_len = sme->key_len; + A_MEMCPY(key->key, sme->key, key->key_len); + key->cipher = ar->arPairwiseCrypto; + ar->arDefTxKeyIndex = sme->key_idx; + + wmi_addKey_cmd(ar->arWmi, sme->key_idx, + ar->arPairwiseCrypto, + GROUP_USAGE | TX_USAGE, + key->key_len, + NULL, + key->key, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + + if (!ar->arUserBssFilter) { + if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Couldn't set bss filtering\n", __func__)); + up(&ar->arSem); + return -EIO; + } + } + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Connect called with authmode %d dot11 auth %d"\ + " PW crypto %d PW crypto Len %d GRP crypto %d"\ + " GRP crypto Len %d channel hint %u\n", + __func__, ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arChannelHint)); + + reconnect_flag = 0; + status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto,ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags); + + up(&ar->arSem); + + if (A_EINVAL == status) { + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Invalid request\n", __func__)); + return -ENOENT; + } else if (status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_connect_cmd failed\n", __func__)); + return -EIO; + } + + if ((!(ar->arConnectCtrlFlags & CONNECT_DO_WPA_OFFLOAD)) && + ((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode))) + { + A_TIMEOUT_MS(&ar->disconnect_timer, A_DISCONNECT_TIMER_INTERVAL, 0); + } + + ar->arConnectCtrlFlags &= ~CONNECT_DO_WPA_OFFLOAD; + ar->arConnectPending = TRUE; + + return 0; +} + +void +ar6k_cfg80211_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, + A_UINT8 *bssid, A_UINT16 listenInterval, + A_UINT16 beaconInterval,NETWORK_TYPE networkType, + A_UINT8 beaconIeLen, A_UINT8 assocReqLen, + A_UINT8 assocRespLen, A_UINT8 *assocInfo) +{ + A_UINT16 size = 0; + A_UINT16 capability = 0; + struct cfg80211_bss *bss = NULL; + struct ieee80211_mgmt *mgmt = NULL; + struct ieee80211_channel *ibss_channel = NULL; + s32 signal = 50 * 100; + A_UINT8 ie_buf_len = 0; + unsigned char ie_buf[256]; + unsigned char *ptr_ie_buf = ie_buf; + unsigned char *ieeemgmtbuf = NULL; + A_UINT8 source_mac[ATH_MAC_LEN]; + + A_UINT8 assocReqIeOffset = sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16); /* listen interval */ + A_UINT8 assocRespIeOffset = sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16); /* associd */ + A_UINT8 *assocReqIe = assocInfo + beaconIeLen + assocReqIeOffset; + A_UINT8 *assocRespIe = assocInfo + beaconIeLen + assocReqLen + assocRespIeOffset; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__)); + + assocReqLen -= assocReqIeOffset; + assocRespLen -= assocRespIeOffset; + + if((ADHOC_NETWORK & networkType)) { + if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: ath6k not in ibss mode\n", __func__)); + return; + } + } + + /* Before informing the join/connect event, make sure that + * bss entry is present in scan list, if it not present + * construct and insert into scan list, otherwise that + * event will be dropped on the way by cfg80211, due to + * this keys will not be plumbed in case of WEP and + * application will not be aware of join/connect status. */ + bss = cfg80211_get_bss(ar->wdev->wiphy, NULL, bssid, + ar->wdev->ssid, ar->wdev->ssid_len, + ((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS), + ((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS)); + + if(!bss) { + if (ADHOC_NETWORK & networkType) { + /* construct 802.11 mgmt beacon */ + if(ptr_ie_buf) { + *ptr_ie_buf++ = WLAN_EID_SSID; + *ptr_ie_buf++ = ar->arSsidLen; + A_MEMCPY(ptr_ie_buf, ar->arSsid, ar->arSsidLen); + ptr_ie_buf +=ar->arSsidLen; + + *ptr_ie_buf++ = WLAN_EID_IBSS_PARAMS; + *ptr_ie_buf++ = 2; /* length */ + *ptr_ie_buf++ = 0; /* ATIM window */ + *ptr_ie_buf++ = 0; /* ATIM window */ + + /* TODO: update ibss params and include supported rates, + * DS param set, extened support rates, wmm. */ + + ie_buf_len = ptr_ie_buf - ie_buf; + } + + capability |= IEEE80211_CAPINFO_IBSS; + if(WEP_CRYPT == ar->arPairwiseCrypto) { + capability |= IEEE80211_CAPINFO_PRIVACY; + } + A_MEMCPY(source_mac, ar->arNetDev->dev_addr, ATH_MAC_LEN); + ptr_ie_buf = ie_buf; + } else { + capability = *(A_UINT16 *)(&assocInfo[beaconIeLen]); + A_MEMCPY(source_mac, bssid, ATH_MAC_LEN); + ptr_ie_buf = assocReqIe; + ie_buf_len = assocReqLen; + } + + size = offsetof(struct ieee80211_mgmt, u) + + sizeof(mgmt->u.beacon) + + ie_buf_len; + + ieeemgmtbuf = A_MALLOC_NOWAIT(size); + if(!ieeemgmtbuf) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("%s: ieeeMgmtbuf alloc error\n", __func__)); + return; + } + + A_MEMZERO(ieeemgmtbuf, size); + mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf; + mgmt->frame_control = (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON); + A_MEMCPY(mgmt->da, bcast_mac, ATH_MAC_LEN); + A_MEMCPY(mgmt->sa, source_mac, ATH_MAC_LEN); + A_MEMCPY(mgmt->bssid, bssid, ATH_MAC_LEN); + mgmt->u.beacon.beacon_int = beaconInterval; + mgmt->u.beacon.capab_info = capability; + A_MEMCPY(mgmt->u.beacon.variable, ptr_ie_buf, ie_buf_len); + + ibss_channel = ieee80211_get_channel(ar->wdev->wiphy, (int)channel); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: inform bss with bssid %02x:%02x:%02x:%02x:%02x:%02x "\ + "channel %d beaconInterval %d capability 0x%x\n", + __func__, + mgmt->bssid[0], mgmt->bssid[1], mgmt->bssid[2], + mgmt->bssid[3], mgmt->bssid[4], mgmt->bssid[5], + ibss_channel->hw_value, beaconInterval, capability)); + + bss = cfg80211_inform_bss_frame(ar->wdev->wiphy, + ibss_channel, mgmt, + le16_to_cpu(size), + signal, GFP_KERNEL); + A_FREE(ieeemgmtbuf); + cfg80211_put_bss(bss); + } + + if((ADHOC_NETWORK & networkType)) { + cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL); + return; + } + + if (FALSE == ar->arConnected) { + /* inform connect result to cfg80211 */ + cfg80211_connect_result(ar->arNetDev, bssid, + assocReqIe, assocReqLen, + assocRespIe, assocRespLen, + WLAN_STATUS_SUCCESS, GFP_KERNEL); + } else { + /* inform roam event to cfg80211 */ + cfg80211_roamed(ar->arNetDev, bssid, + assocReqIe, assocReqLen, + assocRespIe, assocRespLen, + GFP_KERNEL); + } +} + +static int +ar6k_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *dev, + A_UINT16 reason_code) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason_code)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if(ar->bIsDestroyProgress) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, destroy in progress\n", __func__)); + return -EBUSY; + } + + if(down_interruptible(&ar->arSem)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__)); + return -ERESTARTSYS; + } + + reconnect_flag = 0; + wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + + up(&ar->arSem); + + return 0; +} + +void +ar6k_cfg80211_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, + A_UINT8 *bssid, A_UINT8 assocRespLen, + A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason)); + + if((ADHOC_NETWORK & ar->arNetworkType)) { + if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: ath6k not in ibss mode\n", __func__)); + return; + } + A_MEMZERO(bssid, ETH_ALEN); + cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL); + return; + } + + if(FALSE == ar->arConnected) { + if(NO_NETWORK_AVAIL == reason) { + /* connect cmd failed */ + cfg80211_connect_result(ar->arNetDev, bssid, + NULL, 0, + NULL, 0, + WLAN_STATUS_UNSPECIFIED_FAILURE, + GFP_KERNEL); + } + } else { + /* connection loss due to disconnect cmd or low rssi */ + cfg80211_disconnected(ar->arNetDev, reason, NULL, 0, GFP_KERNEL); + } +} + +void +ar6k_cfg80211_scan_node(void *arg, bss_t *ni) +{ + struct wiphy *wiphy = (struct wiphy *)arg; + A_UINT16 size; + unsigned char *ieeemgmtbuf = NULL; + struct ieee80211_mgmt *mgmt; + struct ieee80211_channel *channel; + struct ieee80211_supported_band *band; + struct ieee80211_common_ie *cie; + s32 signal; + int freq; + + cie = &ni->ni_cie; + +#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484))) + if(CHAN_IS_11A(cie->ie_chan)) { + /* 11a */ + band = wiphy->bands[IEEE80211_BAND_5GHZ]; + } else if((cie->ie_erp) || (cie->ie_xrates)) { + /* 11g */ + band = wiphy->bands[IEEE80211_BAND_2GHZ]; + } else { + /* 11b */ + band = wiphy->bands[IEEE80211_BAND_2GHZ]; + } + + size = ni->ni_framelen + offsetof(struct ieee80211_mgmt, u); + ieeemgmtbuf = A_MALLOC_NOWAIT(size); + if(!ieeemgmtbuf) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ieeeMgmtbuf alloc error\n", __func__)); + return; + } + + /* Note: + TODO: Update target to include 802.11 mac header while sending bss info. + Target removes 802.11 mac header while sending the bss info to host, + cfg80211 needs it, for time being just filling the da, sa and bssid fields alone. + */ + mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf; + A_MEMCPY(mgmt->da, bcast_mac, ATH_MAC_LEN); + A_MEMCPY(mgmt->sa, ni->ni_macaddr, ATH_MAC_LEN); + A_MEMCPY(mgmt->bssid, ni->ni_macaddr, ATH_MAC_LEN); + A_MEMCPY(ieeemgmtbuf + offsetof(struct ieee80211_mgmt, u), + ni->ni_buf, ni->ni_framelen); + + freq = cie->ie_chan; + channel = ieee80211_get_channel(wiphy, freq); + signal = ni->ni_snr * 100; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: bssid %02x:%02x:%02x:%02x:%02x:%02x channel %d freq %d size %d\n", + __func__, + mgmt->bssid[0], mgmt->bssid[1], mgmt->bssid[2], + mgmt->bssid[3], mgmt->bssid[4], mgmt->bssid[5], + channel->hw_value, freq, size)); + cfg80211_inform_bss_frame(wiphy, channel, mgmt, + le16_to_cpu(size), + signal, GFP_KERNEL); + + A_FREE (ieeemgmtbuf); +} + +static int +ar6k_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_scan_request *request) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev); + int ret = 0; + A_BOOL forceFgScan = FALSE; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if (!ar->arUserBssFilter) { + if (wmi_bssfilter_cmd(ar->arWmi, + (ar->arConnected ? ALL_BUT_BSS_FILTER : ALL_BSS_FILTER), + 0) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Couldn't set bss filtering\n", __func__)); + return -EIO; + } + } + + if(request->n_ssids && + request->ssids[0].ssid_len) { + A_UINT8 i; + + if(request->n_ssids > MAX_PROBED_SSID_INDEX) { + request->n_ssids = MAX_PROBED_SSID_INDEX; + } + + for (i = 0; i < request->n_ssids; i++) { + wmi_probedSsid_cmd(ar->arWmi, i, SPECIFIC_SSID_FLAG, + request->ssids[i].ssid_len, + request->ssids[i].ssid); + } + } + + if(ar->arConnected) { + forceFgScan = TRUE; + } + + if(wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, forceFgScan, FALSE, \ + 0, 0, 0, NULL) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_startscan_cmd failed\n", __func__)); + ret = -EIO; + } + + ar->scan_request = request; + + return ret; +} + +void +ar6k_cfg80211_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: status %d\n", __func__, status)); + + if(ar->scan_request) + { + /* Translate data to cfg80211 mgmt format */ + wmi_iterate_nodes(ar->arWmi, ar6k_cfg80211_scan_node, ar->wdev->wiphy); + + cfg80211_scan_done(ar->scan_request, + (status & A_ECANCELED) ? true : false); + + if(ar->scan_request->n_ssids && + ar->scan_request->ssids[0].ssid_len) { + A_UINT8 i; + + for (i = 0; i < ar->scan_request->n_ssids; i++) { + wmi_probedSsid_cmd(ar->arWmi, i, DISABLE_SSID_FLAG, + 0, NULL); + } + } + ar->scan_request = NULL; + } +} + +static int +ar6k_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev, + A_UINT8 key_index, const A_UINT8 *mac_addr, + struct key_params *params) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev); + struct ar_key *key = NULL; + A_UINT8 key_usage; + A_UINT8 key_type; + A_STATUS status = 0; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s:\n", __func__)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: key index %d out of bounds\n", __func__, key_index)); + return -ENOENT; + } + + key = &ar->keys[key_index]; + A_MEMZERO(key, sizeof(struct ar_key)); + + if(!mac_addr || is_broadcast_ether_addr(mac_addr)) { + key_usage = GROUP_USAGE; + } else { + key_usage = PAIRWISE_USAGE; + } + + if(params) { + if(params->key_len > WLAN_MAX_KEY_LEN || + params->seq_len > IW_ENCODE_SEQ_MAX_SIZE) + return -EINVAL; + + key->key_len = params->key_len; + A_MEMCPY(key->key, params->key, key->key_len); + key->seq_len = params->seq_len; + A_MEMCPY(key->seq, params->seq, key->seq_len); + key->cipher = params->cipher; + } + + switch (key->cipher) { + case WLAN_CIPHER_SUITE_WEP40: + case WLAN_CIPHER_SUITE_WEP104: + key_type = WEP_CRYPT; + if(key_index == ar->arDefTxKeyIndex) { + key_usage = GROUP_USAGE | TX_USAGE; + } + break; + + case WLAN_CIPHER_SUITE_TKIP: + key_type = TKIP_CRYPT; + break; + + case WLAN_CIPHER_SUITE_CCMP: + key_type = AES_CRYPT; + break; + + default: + return -ENOTSUPP; + } + + if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) && + (GROUP_USAGE & key_usage)) + { + A_UNTIMEOUT(&ar->disconnect_timer); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: index %d, key_len %d, key_type 0x%x,"\ + " key_usage 0x%x, seq_len %d\n", + __func__, key_index, key->key_len, key_type, + key_usage, key->seq_len)); + + status = wmi_addKey_cmd(ar->arWmi, key_index, key_type, key_usage, + key->key_len, key->seq, key->key, KEY_OP_INIT_VAL, + (A_UINT8*)mac_addr, SYNC_BOTH_WMIFLAG); + + + if(status != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6k_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev, + A_UINT8 key_index, const A_UINT8 *mac_addr) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: key index %d out of bounds\n", __func__, key_index)); + return -ENOENT; + } + + if(!ar->keys[key_index].key_len) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d is empty\n", __func__, key_index)); + return 0; + } + + ar->keys[key_index].key_len = 0; + + return wmi_deleteKey_cmd(ar->arWmi, key_index); +} + + +static int +ar6k_cfg80211_get_key(struct wiphy *wiphy, struct net_device *ndev, + A_UINT8 key_index, const A_UINT8 *mac_addr, void *cookie, + void (*callback)(void *cookie, struct key_params*)) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev); + struct ar_key *key = NULL; + struct key_params params; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: key index %d out of bounds\n", __func__, key_index)); + return -ENOENT; + } + + key = &ar->keys[key_index]; + A_MEMZERO(¶ms, sizeof(params)); + params.cipher = key->cipher; + params.key_len = key->key_len; + params.seq_len = key->seq_len; + params.seq = key->seq; + params.key = key->key; + + callback(cookie, ¶ms); + + return key->key_len ? 0 : -ENOENT; +} + + +static int +ar6k_cfg80211_set_default_key(struct wiphy *wiphy, struct net_device *ndev, + A_UINT8 key_index) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if(key_index < WMI_MIN_KEY_INDEX || key_index > WMI_MAX_KEY_INDEX) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: key index %d out of bounds\n", + __func__, key_index)); + return -ENOENT; + } + + if(!ar->keys[key_index].key_len) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: invalid key index %d\n", + __func__, key_index)); + return -EINVAL; + } + + ar->arDefTxKeyIndex = key_index; + + return 0; +} + +static int +ar6k_cfg80211_set_default_mgmt_key(struct wiphy *wiphy, struct net_device *ndev, + A_UINT8 key_index) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(ndev); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: index %d\n", __func__, key_index)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__)); + return -ENOTSUPP; +} + +void +ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, + ("%s: keyid %d, ismcast %d\n", __func__, keyid, ismcast)); + + cfg80211_michael_mic_failure(ar->arNetDev, ar->arBssid, + (ismcast ? NL80211_KEYTYPE_GROUP : NL80211_KEYTYPE_PAIRWISE), + keyid, NULL, GFP_KERNEL); +} + +static int +ar6k_cfg80211_set_wiphy_params(struct wiphy *wiphy, A_UINT32 changed) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: changed 0x%x\n", __func__, changed)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if (changed & WIPHY_PARAM_RTS_THRESHOLD) { + if (wmi_set_rts_cmd(ar->arWmi,wiphy->rts_threshold) != A_OK){ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_set_rts_cmd failed\n", __func__)); + return -EIO; + } + } + + return 0; +} + +static int +ar6k_cfg80211_set_bitrate_mask(struct wiphy *wiphy, struct net_device *dev, + const A_UINT8 *peer, + const struct cfg80211_bitrate_mask *mask) +{ + AR_SOFTC_T *ar = ar6k_priv(dev); + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: mask 0x%x\n", __func__, mask->fixed)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + status = wmi_set_fixrates_cmd(ar->arWmi, mask->fixed); + + if(status == A_EINVAL) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: invalid params\n", __func__)); + return -EINVAL; + } else if(status != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_set_fixrates_cmd failed\n", __func__)); + return -EIO; + } + + return 0; +} + +static int +ar6k_cfg80211_set_txpower(struct wiphy *wiphy, enum tx_power_setting type, int dbm) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy); + A_UINT8 ar_dbm; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type 0x%x, dbm %d\n", __func__, type, dbm)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + ar->arTxPwrSet = FALSE; + switch(type) { + case TX_POWER_AUTOMATIC: + return 0; + case TX_POWER_LIMITED: + ar->arTxPwr = ar_dbm = dbm; + ar->arTxPwrSet = TRUE; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type 0x%x not supported\n", __func__, type)); + return -EOPNOTSUPP; + } + + wmi_set_txPwr_cmd(ar->arWmi, ar_dbm); + + return 0; +} + +static int +ar6k_cfg80211_get_txpower(struct wiphy *wiphy, int *dbm) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)wiphy_priv(wiphy); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if((ar->arConnected == TRUE)) { + ar->arTxPwr = 0; + + if(wmi_get_txPwr_cmd(ar->arWmi) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_get_txPwr_cmd failed\n", __func__)); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, 5 * HZ); + + if(signal_pending(current)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Target did not respond\n", __func__)); + return -EINTR; + } + } + + *dbm = ar->arTxPwr; + return 0; +} + +static int +ar6k_cfg80211_set_power_mgmt(struct wiphy *wiphy, + struct net_device *dev, + bool pmgmt, int timeout) +{ + AR_SOFTC_T *ar = ar6k_priv(dev); + WMI_POWER_MODE_CMD pwrMode; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: pmgmt %d, timeout %d\n", __func__, pmgmt, timeout)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if(pmgmt) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Max Perf\n", __func__)); + pwrMode.powerMode = MAX_PERF_POWER; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Rec Power\n", __func__)); + pwrMode.powerMode = REC_POWER; + } + + if(wmi_powermode_cmd(ar->arWmi, pwrMode.powerMode) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: wmi_powermode_cmd failed\n", __func__)); + return -EIO; + } + + return 0; +} + +static int +ar6k_cfg80211_add_virtual_intf(struct wiphy *wiphy, char *name, + enum nl80211_iftype type, u32 *flags, + struct vif_params *params) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__)); + + /* Multiple virtual interface is not supported. + * The default interface supports STA and IBSS type + */ + return -EOPNOTSUPP; +} + +static int +ar6k_cfg80211_del_virtual_intf(struct wiphy *wiphy, struct net_device *dev) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: not supported\n", __func__)); + + /* Multiple virtual interface is not supported. + * The default interface supports STA and IBSS type + */ + return -EOPNOTSUPP; +} + +static int +ar6k_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev, + enum nl80211_iftype type, u32 *flags, + struct vif_params *params) +{ + AR_SOFTC_T *ar = ar6k_priv(ndev); + struct wireless_dev *wdev = ar->wdev; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: type %u\n", __func__, type)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + switch (type) { + case NL80211_IFTYPE_STATION: + ar->arNetworkType = INFRA_NETWORK; + break; + case NL80211_IFTYPE_ADHOC: + ar->arNetworkType = ADHOC_NETWORK; + break; + default: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: type %u\n", __func__, type)); + return -EOPNOTSUPP; + } + + wdev->iftype = type; + + return 0; +} + +static int +ar6k_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev, + struct cfg80211_ibss_params *ibss_param) +{ + AR_SOFTC_T *ar = ar6k_priv(dev); + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + if(!ibss_param->ssid_len || IEEE80211_MAX_SSID_LEN < ibss_param->ssid_len) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ssid invalid\n", __func__)); + return -EINVAL; + } + + ar->arSsidLen = ibss_param->ssid_len; + A_MEMCPY(ar->arSsid, ibss_param->ssid, ar->arSsidLen); + + if(ibss_param->channel) { + ar->arChannelHint = ibss_param->channel->center_freq; + } + + if(ibss_param->channel_fixed) { + /* TODO: channel_fixed: The channel should be fixed, do not search for + * IBSSs to join on other channels. Target firmware does not support this + * feature, needs to be updated.*/ + } + + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + if(ibss_param->bssid) { + if(A_MEMCMP(&ibss_param->bssid, bcast_mac, AR6000_ETH_ADDR_LEN)) { + A_MEMCPY(ar->arReqBssid, ibss_param->bssid, sizeof(ar->arReqBssid)); + } + } + + ar6k_set_wpa_version(ar, 0); + ar6k_set_auth_type(ar, NL80211_AUTHTYPE_OPEN_SYSTEM); + + if(ibss_param->privacy) { + ar6k_set_cipher(ar, WLAN_CIPHER_SUITE_WEP40, true); + ar6k_set_cipher(ar, WLAN_CIPHER_SUITE_WEP40, false); + } else { + ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, true); + ar6k_set_cipher(ar, IW_AUTH_CIPHER_NONE, false); + } + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Connect called with authmode %d dot11 auth %d"\ + " PW crypto %d PW crypto Len %d GRP crypto %d"\ + " GRP crypto Len %d channel hint %u\n", + __func__, ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto, ar->arGroupCryptoLen, ar->arChannelHint)); + + status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType, + ar->arDot11AuthMode, ar->arAuthMode, + ar->arPairwiseCrypto, ar->arPairwiseCryptoLen, + ar->arGroupCrypto,ar->arGroupCryptoLen, + ar->arSsidLen, ar->arSsid, + ar->arReqBssid, ar->arChannelHint, + ar->arConnectCtrlFlags); + + return 0; +} + +static int +ar6k_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__)); + + if(ar->arWmiReady == FALSE) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wmi not ready\n", __func__)); + return -EIO; + } + + if(ar->arWlanState == WLAN_DISABLED) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Wlan disabled\n", __func__)); + return -EIO; + } + + wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + + return 0; +} + + +static const +A_UINT32 cipher_suites[] = { + WLAN_CIPHER_SUITE_WEP40, + WLAN_CIPHER_SUITE_WEP104, + WLAN_CIPHER_SUITE_TKIP, + WLAN_CIPHER_SUITE_CCMP, +}; + +static struct +cfg80211_ops ar6k_cfg80211_ops = { + .change_virtual_intf = ar6k_cfg80211_change_iface, + .add_virtual_intf = ar6k_cfg80211_add_virtual_intf, + .del_virtual_intf = ar6k_cfg80211_del_virtual_intf, + .scan = ar6k_cfg80211_scan, + .connect = ar6k_cfg80211_connect, + .disconnect = ar6k_cfg80211_disconnect, + .add_key = ar6k_cfg80211_add_key, + .get_key = ar6k_cfg80211_get_key, + .del_key = ar6k_cfg80211_del_key, + .set_default_key = ar6k_cfg80211_set_default_key, + .set_default_mgmt_key = ar6k_cfg80211_set_default_mgmt_key, + .set_wiphy_params = ar6k_cfg80211_set_wiphy_params, + .set_bitrate_mask = ar6k_cfg80211_set_bitrate_mask, + .set_tx_power = ar6k_cfg80211_set_txpower, + .get_tx_power = ar6k_cfg80211_get_txpower, + .set_power_mgmt = ar6k_cfg80211_set_power_mgmt, + .join_ibss = ar6k_cfg80211_join_ibss, + .leave_ibss = ar6k_cfg80211_leave_ibss, +}; + +struct wireless_dev * +ar6k_cfg80211_init(struct device *dev) +{ + int ret = 0; + struct wireless_dev *wdev; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__)); + + wdev = kzalloc(sizeof(struct wireless_dev), GFP_KERNEL); + if(!wdev) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("%s: Couldn't allocate wireless device\n", __func__)); + return ERR_PTR(-ENOMEM); + } + + /* create a new wiphy for use with cfg80211 */ + wdev->wiphy = wiphy_new(&ar6k_cfg80211_ops, sizeof(AR_SOFTC_T)); + if(!wdev->wiphy) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("%s: Couldn't allocate wiphy device\n", __func__)); + kfree(wdev); + return ERR_PTR(-ENOMEM); + } + + /* set device pointer for wiphy */ + set_wiphy_dev(wdev->wiphy, dev); + + wdev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | + BIT(NL80211_IFTYPE_ADHOC); + /* max num of ssids that can be probed during scanning */ + wdev->wiphy->max_scan_ssids = MAX_PROBED_SSID_INDEX; + wdev->wiphy->bands[IEEE80211_BAND_2GHZ] = &ar6k_band_2ghz; + wdev->wiphy->bands[IEEE80211_BAND_5GHZ] = &ar6k_band_5ghz; + wdev->wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM; + + wdev->wiphy->cipher_suites = cipher_suites; + wdev->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites); + + ret = wiphy_register(wdev->wiphy); + if(ret < 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("%s: Couldn't register wiphy device\n", __func__)); + wiphy_free(wdev->wiphy); + return ERR_PTR(ret); + } + + return wdev; +} + +void +ar6k_cfg80211_deinit(AR_SOFTC_T *ar) +{ + struct wireless_dev *wdev = ar->wdev; + + AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: \n", __func__)); + + if(ar->scan_request) { + cfg80211_scan_done(ar->scan_request, true); + ar->scan_request = NULL; + } + + if(!wdev) + return; + + wiphy_unregister(wdev->wiphy); + wiphy_free(wdev->wiphy); + kfree(wdev); +} + + + + + + + diff --git a/drivers/net/wireless/ath6kl/os/linux/eeprom.c b/drivers/net/wireless/ath6kl/os/linux/eeprom.c new file mode 100644 index 000000000000..1c182751a939 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/eeprom.c @@ -0,0 +1,581 @@ +/* + * + * Copyright (c) 2004-2009 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + + +#include "ar6000_drv.h" +#include "htc.h" +#include + +#include "AR6002/hw2.0/hw/gpio_reg.h" +#include "AR6002/hw2.0/hw/si_reg.h" + +// +// defines +// + +#define MAX_FILENAME 1023 +#define EEPROM_WAIT_LIMIT 16 + +#define HOST_INTEREST_ITEM_ADDRESS(item) \ + (AR6002_HOST_INTEREST_ITEM_ADDRESS(item)) + +#define EEPROM_SZ 768 + +/* soft mac */ +#define ATH_MAC_LEN 6 +#define ATH_SOFT_MAC_TMP_BUF_LEN 64 +unsigned char mac_addr[ATH_MAC_LEN]; +unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN]; +char *p_mac = NULL; +/* soft mac */ + +// +// static variables +// + +static A_UCHAR eeprom_data[EEPROM_SZ]; +static A_UINT32 sys_sleep_reg; +static HIF_DEVICE *p_bmi_device; + +// +// Functions +// + +/* soft mac */ +static int +wmic_ether_aton(const char *orig, A_UINT8 *eth) +{ + const char *bufp; + int i; + + i = 0; + for(bufp = orig; *bufp != '\0'; ++bufp) { + unsigned int val; + unsigned char c = *bufp++; + if (c >= '0' && c <= '9') val = c - '0'; + else if (c >= 'a' && c <= 'f') val = c - 'a' + 10; + else if (c >= 'A' && c <= 'F') val = c - 'A' + 10; + else { + printk("%s: MAC value is invalid\n", __FUNCTION__); + break; + } + + val <<= 4; + c = *bufp++; + if (c >= '0' && c <= '9') val |= c - '0'; + else if (c >= 'a' && c <= 'f') val |= c - 'a' + 10; + else if (c >= 'A' && c <= 'F') val |= c - 'A' + 10; + else { + printk("%s: MAC value is invalid\n", __FUNCTION__); + break; + } + + eth[i] = (unsigned char) (val & 0377); + if(++i == ATH_MAC_LEN) { + /* That's it. Any trailing junk? */ + if (*bufp != '\0') { + return 0; + } + return 1; + } + if (*bufp != ':') + break; + } + return 0; +} + +static void +update_mac(unsigned char* eeprom, int size, unsigned char* macaddr) +{ + int i; + A_UINT16* ptr = (A_UINT16*)(eeprom+4); + A_UINT16 checksum = 0; + + memcpy(eeprom+10,macaddr,6); + + *ptr = 0; + ptr = (A_UINT16*)eeprom; + + for (i=0; i>7)); + + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval); + + regval = SI_CS_START_SET(1) | + SI_CS_RX_CNT_SET(8) | + SI_CS_TX_CNT_SET(3); + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval); +} + +/* + * Tell the Target to start a 4-byte write to EEPROM, + * writing values from Target TX_DATA registers. + */ +static void +request_4byte_write(int offset, A_UINT32 data) +{ + A_UINT32 regval; + + printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset); + + /* SI_TX_DATA0 = write data to offset */ + regval = ((data & 0xffff) <<16) | + ((offset & 0xff)<<8) | + (0xa0 | ((offset & 0xff00)>>7)); + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval); + + regval = data >> 16; + BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval); + + regval = SI_CS_START_SET(1) | + SI_CS_RX_CNT_SET(0) | + SI_CS_TX_CNT_SET(6); + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval); +} + +/* + * Check whether or not an EEPROM request that was started + * earlier has completed yet. + */ +static A_BOOL +request_in_progress(void) +{ + A_UINT32 regval; + + /* Wait for DONE_INT in SI_CS */ + BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val); + +// printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval); + if (regval & SI_CS_DONE_ERR_MASK) { + printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval); + } + + return (!(regval & SI_CS_DONE_INT_MASK)); +} + +/* + * try to detect the type of EEPROM,16bit address or 8bit address + */ + +static void eeprom_type_detect(void) +{ + A_UINT32 regval; + A_UINT8 i = 0; + + request_8byte_read(0x100); + /* Wait for DONE_INT in SI_CS */ + do{ + BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val); + if (regval & SI_CS_DONE_ERR_MASK) { + printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__); + break; + } + if (i++ == EEPROM_WAIT_LIMIT) { + printk("%s: EEPROM not responding\n", __FUNCTION__); + } + } while(!(regval & SI_CS_DONE_INT_MASK)); +} + +/* + * Extract the results of a completed EEPROM Read request + * and return them to the caller. + */ +inline void +read_8byte_results(A_UINT32 *data) +{ + /* Read SI_RX_DATA0 and SI_RX_DATA1 */ + BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]); + BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]); +} + + +/* + * Wait for a previously started command to complete. + * Timeout if the command is takes "too long". + */ +static void +wait_for_eeprom_completion(void) +{ + int i=0; + + while (request_in_progress()) { + if (i++ == EEPROM_WAIT_LIMIT) { + printk("%s: EEPROM not responding\n", __FUNCTION__); + } + } +} + +/* + * High-level function which starts an 8-byte read, + * waits for it to complete, and returns the result. + */ +static void +fetch_8bytes(int offset, A_UINT32 *data) +{ + request_8byte_read(offset); + wait_for_eeprom_completion(); + read_8byte_results(data); + + /* Clear any pending intr */ + BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK); +} + +/* + * High-level function which starts a 4-byte write, + * and waits for it to complete. + */ +inline void +commit_4bytes(int offset, A_UINT32 data) +{ + request_4byte_write(offset, data); + wait_for_eeprom_completion(); +} +/* ATHENV */ +#ifdef ANDROID_ENV +void eeprom_ar6000_transfer(HIF_DEVICE *device, char *fake_file, char *p_mac) +{ + A_UINT32 first_word; + A_UINT32 board_data_addr; + int i; + + printk("%s: Enter\n", __FUNCTION__); + + enable_SI(device); + eeprom_type_detect(); + + if (fake_file) { + /* + * Transfer from file to Target RAM. + * Fetch source data from file. + */ + mm_segment_t oldfs; + struct file *filp; + struct inode *inode = NULL; + int length; + + /* open file */ + oldfs = get_fs(); + set_fs(KERNEL_DS); + filp = filp_open(fake_file, O_RDONLY, S_IRUSR); + + if (IS_ERR(filp)) { + printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file); + set_fs(oldfs); + return; + } + + if (!filp->f_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + /* file's size */ + length = i_size_read(inode->i_mapping->host); + printk("%s: length=%d\n", __FUNCTION__, length); + if (length != EEPROM_SZ) { + printk("%s: The file's size is not as expected\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data */ + if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) { + printk("%s: file read error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data out successfully */ + filp_close(filp, NULL); + set_fs(oldfs); + } else { + /* + * Read from EEPROM to file OR transfer from EEPROM to Target RAM. + * Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time. + */ + + fetch_8bytes(0, (A_UINT32 *)(&eeprom_data[0])); + + /* Check the first word of EEPROM for validity */ + first_word = *((A_UINT32 *)eeprom_data); + + if ((first_word == 0) || (first_word == 0xffffffff)) { + printk("Did not find EEPROM with valid Board Data.\n"); + } + + for (i=8; if_op) { + printk("%s: File Operation Method Error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + inode = filp->f_path.dentry->d_inode; +#else + inode = filp->f_dentry->d_inode; +#endif + if (!inode) { + printk("%s: Get inode from filp failed\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos); + + /* file's size */ + length = i_size_read(inode->i_mapping->host); + printk("%s: length=%d\n", __FUNCTION__, length); + if (length > ATH_SOFT_MAC_TMP_BUF_LEN) { + printk("%s: MAC file's size is not as expected\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + + /* read data */ + if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) { + printk("%s: file read error\n", __FUNCTION__); + filp_close(filp, NULL); + set_fs(oldfs); + return; + } + +#if 0 + /* the data we just read */ + printk("%s: mac address from the file:\n", __FUNCTION__); + for (i = 0; i < length; i++) + printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]); + printk("\n"); +#endif + + /* read data out successfully */ + filp_close(filp, NULL); + set_fs(oldfs); + + /* convert mac address */ + if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) { + printk("%s: convert mac value fail\n", __FUNCTION__); + return; + } + +#if 0 + /* the converted mac address */ + printk("%s: the converted mac value\n", __FUNCTION__); + for (i = 0; i < ATH_MAC_LEN; i++) + printk("[0x%x],", mac_addr[i]); + printk("\n"); +#endif + } + /* soft mac */ + + /* Determine where in Target RAM to write Board Data */ + BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr); + if (board_data_addr == 0) { + printk("hi_board_data is zero\n"); + } + + /* soft mac */ +#if 1 + /* Update MAC address in RAM */ + if (p_mac) { + update_mac(eeprom_data, EEPROM_SZ, mac_addr); + } +#endif +#if 0 + /* mac address in eeprom array */ + printk("%s: mac values in eeprom array\n", __FUNCTION__); + for (i = 10; i < 10 + 6; i++) + printk("[0x%x],", eeprom_data[i]); + printk("\n"); +#endif + /* soft mac */ + + /* Write EEPROM data to Target RAM */ + BMI_write_mem(board_data_addr, ((A_UINT8 *)eeprom_data), EEPROM_SZ); + + /* Record the fact that Board Data IS initialized */ + { + A_UINT32 one = 1; + BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized), + (A_UINT8 *)&one, sizeof(A_UINT32)); + } + + disable_SI(); +} +#endif +/* ATHENV */ + diff --git a/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c b/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c new file mode 100644 index 000000000000..29b7fac80949 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/export_hci_transport.c @@ -0,0 +1,119 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HCI bridge implementation +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include "a_types.h" +#include "a_osapi.h" +#include "htc_api.h" +#include "a_drv.h" +#include "hif.h" +#include "common_drv.h" +#include "a_debug.h" +#include "hci_transport_api.h" + +#include "AR6002/hw4.0/hw/apb_athr_wlan_map.h" +#include "AR6002/hw4.0/hw/uart_reg.h" +#include "AR6002/hw4.0/hw/rtc_wlan_reg.h" + +HCI_TRANSPORT_HANDLE (*_HCI_TransportAttach)(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo); +void (*_HCI_TransportDetach)(HCI_TRANSPORT_HANDLE HciTrans); +A_STATUS (*_HCI_TransportAddReceivePkts)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue); +A_STATUS (*_HCI_TransportSendPkt)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous); +void (*_HCI_TransportStop)(HCI_TRANSPORT_HANDLE HciTrans); +A_STATUS (*_HCI_TransportStart)(HCI_TRANSPORT_HANDLE HciTrans); +A_STATUS (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable); +A_STATUS (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans, + HTC_PACKET *pPacket, + int MaxPollMS); +A_STATUS (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud); + +extern HCI_TRANSPORT_CALLBACKS ar6kHciTransCallbacks; + +A_STATUS ar6000_register_hci_transport(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks) +{ + ar6kHciTransCallbacks = *hciTransCallbacks; + + _HCI_TransportAttach = HCI_TransportAttach; + _HCI_TransportDetach = HCI_TransportDetach; + _HCI_TransportAddReceivePkts = HCI_TransportAddReceivePkts; + _HCI_TransportSendPkt = HCI_TransportSendPkt; + _HCI_TransportStop = HCI_TransportStop; + _HCI_TransportStart = HCI_TransportStart; + _HCI_TransportEnableDisableAsyncRecv = HCI_TransportEnableDisableAsyncRecv; + _HCI_TransportRecvHCIEventSync = HCI_TransportRecvHCIEventSync; + _HCI_TransportSetBaudRate = HCI_TransportSetBaudRate; + + return A_OK; +} + +A_STATUS +ar6000_get_hif_dev(HIF_DEVICE *device, void *config) +{ + A_STATUS status; + + status = HIFConfigureDevice(device, + HIF_DEVICE_GET_OS_DEVICE, + (HIF_DEVICE_OS_DEVICE_INFO *)config, + sizeof(HIF_DEVICE_OS_DEVICE_INFO)); + return status; +} + +A_STATUS ar6000_set_uart_config(HIF_DEVICE *hifDevice, + A_UINT32 scale, + A_UINT32 step) +{ + A_UINT32 regAddress; + A_UINT32 regVal; + A_STATUS status; + + regAddress = WLAN_UART_BASE_ADDRESS | UART_CLKDIV_ADDRESS; + regVal = ((A_UINT32)scale << 16) | step; + /* change the HCI UART scale/step values through the diagnostic window */ + status = ar6000_WriteRegDiag(hifDevice, ®Address, ®Val); + + return status; +} + +A_STATUS ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data) +{ + A_UINT32 regAddress; + A_STATUS status; + + regAddress = WLAN_RTC_BASE_ADDRESS | WLAN_CPU_CLOCK_ADDRESS; + /* read CPU clock settings*/ + status = ar6000_ReadRegDiag(hifDevice, ®Address, data); + + return status; +} + +EXPORT_SYMBOL(ar6000_register_hci_transport); +EXPORT_SYMBOL(ar6000_get_hif_dev); +EXPORT_SYMBOL(ar6000_set_uart_config); +EXPORT_SYMBOL(ar6000_get_core_clock_config); +EXPORT_SYMBOL(_HCI_TransportAttach); +EXPORT_SYMBOL(_HCI_TransportDetach); +EXPORT_SYMBOL(_HCI_TransportAddReceivePkts); +EXPORT_SYMBOL(_HCI_TransportSendPkt); +EXPORT_SYMBOL(_HCI_TransportStop); +EXPORT_SYMBOL(_HCI_TransportStart); +EXPORT_SYMBOL(_HCI_TransportEnableDisableAsyncRecv); +EXPORT_SYMBOL(_HCI_TransportRecvHCIEventSync); +EXPORT_SYMBOL(_HCI_TransportSetBaudRate); diff --git a/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c b/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c new file mode 100644 index 000000000000..3cbf5849e8fb --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/hci_bridge.c @@ -0,0 +1,1126 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HCI bridge implementation +// +// Author(s): ="Atheros" +//============================================================================== + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +#include +#include +#include +#include "a_types.h" +#include "a_osapi.h" +#include "htc_api.h" +#include "wmi.h" +#include "a_drv.h" +#include "hif.h" +#include "common_drv.h" +#include "a_debug.h" +#define ATH_DEBUG_HCI_BRIDGE ATH_DEBUG_MAKE_MODULE_MASK(6) +#define ATH_DEBUG_HCI_RECV ATH_DEBUG_MAKE_MODULE_MASK(7) +#define ATH_DEBUG_HCI_SEND ATH_DEBUG_MAKE_MODULE_MASK(8) +#define ATH_DEBUG_HCI_DUMP ATH_DEBUG_MAKE_MODULE_MASK(9) +#else +#include "ar6000_drv.h" +#endif /* EXPORT_HCI_BRIDGE_INTERFACE */ + +#ifdef ATH_AR6K_ENABLE_GMBOX +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +#include "export_hci_transport.h" +#else +#include "hci_transport_api.h" +#endif +#include "epping_test.h" +#include "gmboxif.h" +#include "ar3kconfig.h" +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25) + /* only build on newer kernels which have BT configured */ +#if defined(CONFIG_BT_MODULE) || defined(CONFIG_BT) +#define CONFIG_BLUEZ_HCI_BRIDGE +#endif +#endif + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +unsigned int ar3khcibaud = 0; +unsigned int hciuartscale = 0; +unsigned int hciuartstep = 0; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +module_param(ar3khcibaud, int, 0644); +module_param(hciuartscale, int, 0644); +module_param(hciuartstep, int, 0644); +#else + +#define __user +/* for linux 2.4 and lower */ +MODULE_PARM(ar3khcibaud, "i"); +MODULE_PARM(hciuartscale, "i"); +MODULE_PARM(hciuartstep, "i"); +#endif +#else +extern unsigned int ar3khcibaud; +extern unsigned int hciuartscale; +extern unsigned int hciuartstep; +#endif /* EXPORT_HCI_BRIDGE_INTERFACE */ + +typedef struct { + void *pHCIDev; /* HCI bridge device */ + HCI_TRANSPORT_PROPERTIES HCIProps; /* HCI bridge props */ + struct hci_dev *pBtStackHCIDev; /* BT Stack HCI dev */ + A_BOOL HciNormalMode; /* Actual HCI mode enabled (non-TEST)*/ + A_BOOL HciRegistered; /* HCI device registered with stack */ + HTC_PACKET_QUEUE HTCPacketStructHead; + A_UINT8 *pHTCStructAlloc; + spinlock_t BridgeLock; +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + HCI_TRANSPORT_MISC_HANDLES HCITransHdl; +#else + AR_SOFTC_T *ar; +#endif /* EXPORT_HCI_BRIDGE_INTERFACE */ +} AR6K_HCI_BRIDGE_INFO; + +#define MAX_ACL_RECV_BUFS 16 +#define MAX_EVT_RECV_BUFS 8 +#define MAX_HCI_WRITE_QUEUE_DEPTH 32 +#define MAX_ACL_RECV_LENGTH 1200 +#define MAX_EVT_RECV_LENGTH 257 +#define TX_PACKET_RSV_OFFSET 32 +#define NUM_HTC_PACKET_STRUCTS ((MAX_ACL_RECV_BUFS + MAX_EVT_RECV_BUFS + MAX_HCI_WRITE_QUEUE_DEPTH) * 2) + +#define HCI_GET_OP_CODE(p) (((A_UINT16)((p)[1])) << 8) | ((A_UINT16)((p)[0])) + +extern unsigned int setupbtdev; + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +AR6K_HCI_BRIDGE_INFO *g_pHcidevInfo; +#endif + +static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo); +static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo); +static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo); +static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, + HCI_TRANSPORT_PACKET_TYPE Type, + struct sk_buff *skb); +static struct sk_buff *bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length); +static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb); + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +A_STATUS ar6000_setup_hci(void *ar); +void ar6000_cleanup_hci(void *ar); +A_STATUS hci_test_send(void *ar, struct sk_buff *skb); +#else +A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar); +void ar6000_cleanup_hci(AR_SOFTC_T *ar); +/* HCI bridge testing */ +A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb); +#endif /* EXPORT_HCI_BRIDGE_INTERFACE */ + +#define LOCK_BRIDGE(dev) spin_lock_bh(&(dev)->BridgeLock) +#define UNLOCK_BRIDGE(dev) spin_unlock_bh(&(dev)->BridgeLock) + +static inline void FreeBtOsBuf(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, void *osbuf) +{ + if (pHcidevInfo->HciNormalMode) { + bt_free_buffer(pHcidevInfo, (struct sk_buff *)osbuf); + } else { + /* in test mode, these are just ordinary netbuf allocations */ + A_NETBUF_FREE(osbuf); + } +} + +static void FreeHTCStruct(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, HTC_PACKET *pPacket) +{ + LOCK_BRIDGE(pHcidevInfo); + HTC_PACKET_ENQUEUE(&pHcidevInfo->HTCPacketStructHead,pPacket); + UNLOCK_BRIDGE(pHcidevInfo); +} + +static HTC_PACKET * AllocHTCStruct(AR6K_HCI_BRIDGE_INFO *pHcidevInfo) +{ + HTC_PACKET *pPacket = NULL; + LOCK_BRIDGE(pHcidevInfo); + pPacket = HTC_PACKET_DEQUEUE(&pHcidevInfo->HTCPacketStructHead); + UNLOCK_BRIDGE(pHcidevInfo); + return pPacket; +} + +#define BLOCK_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1)) + +static void RefillRecvBuffers(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, + HCI_TRANSPORT_PACKET_TYPE Type, + int NumBuffers) +{ + int length, i; + void *osBuf = NULL; + HTC_PACKET_QUEUE queue; + HTC_PACKET *pPacket; + + INIT_HTC_PACKET_QUEUE(&queue); + + if (Type == HCI_ACL_TYPE) { + if (pHcidevInfo->HciNormalMode) { + length = HCI_MAX_FRAME_SIZE; + } else { + length = MAX_ACL_RECV_LENGTH; + } + } else { + length = MAX_EVT_RECV_LENGTH; + } + + /* add on transport head and tail room */ + length += pHcidevInfo->HCIProps.HeadRoom + pHcidevInfo->HCIProps.TailRoom; + /* round up to the required I/O padding */ + length = BLOCK_ROUND_UP_PWR2(length,pHcidevInfo->HCIProps.IOBlockPad); + + for (i = 0; i < NumBuffers; i++) { + + if (pHcidevInfo->HciNormalMode) { + osBuf = bt_alloc_buffer(pHcidevInfo,length); + } else { + osBuf = A_NETBUF_ALLOC(length); + } + + if (NULL == osBuf) { + break; + } + + pPacket = AllocHTCStruct(pHcidevInfo); + if (NULL == pPacket) { + FreeBtOsBuf(pHcidevInfo,osBuf); + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc HTC struct \n")); + break; + } + + SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),length,Type); + /* add to queue */ + HTC_PACKET_ENQUEUE(&queue,pPacket); + } + + if (i > 0) { + HCI_TransportAddReceivePkts(pHcidevInfo->pHCIDev, &queue); + } +} + +static A_STATUS ar6000_hci_transport_ready(HCI_TRANSPORT_HANDLE HCIHandle, + HCI_TRANSPORT_PROPERTIES *pProps, + void *pContext) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext; + A_STATUS status; + AR3K_CONFIG_INFO ar3kconfig; + + pHcidevInfo->pHCIDev = HCIHandle; + + A_MEMCPY(&pHcidevInfo->HCIProps,pProps,sizeof(*pProps)); + + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE,("HCI ready (hci:0x%X, headroom:%d, tailroom:%d blockpad:%d) \n", + (A_UINT32)HCIHandle, + pHcidevInfo->HCIProps.HeadRoom, + pHcidevInfo->HCIProps.TailRoom, + pHcidevInfo->HCIProps.IOBlockPad)); + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + A_ASSERT((pProps->HeadRoom + pProps->TailRoom) <= (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice)->hard_header_len); +#else + A_ASSERT((pProps->HeadRoom + pProps->TailRoom) <= pHcidevInfo->ar->arNetDev->hard_header_len); +#endif + + /* provide buffers */ + RefillRecvBuffers(pHcidevInfo, HCI_ACL_TYPE, MAX_ACL_RECV_BUFS); + RefillRecvBuffers(pHcidevInfo, HCI_EVENT_TYPE, MAX_EVT_RECV_BUFS); + + do { + /* start transport */ + status = HCI_TransportStart(pHcidevInfo->pHCIDev); + + if (A_FAILED(status)) { + break; + } + + if (!pHcidevInfo->HciNormalMode) { + /* in test mode, no need to go any further */ + break; + } + + // The delay is required when AR6K is driving the BT reset line + // where time is needed after the BT chip is out of reset (HCI_TransportStart) + // and before the first HCI command is issued (AR3KConfigure) + // FIXME + // The delay should be configurable and be only applied when AR6K driving the BT + // reset line. This could be done by some module parameter or based on some HW config + // info. For now apply 100ms delay blindly + A_MDELAY(100); + + A_MEMZERO(&ar3kconfig,sizeof(ar3kconfig)); + ar3kconfig.pHCIDev = pHcidevInfo->pHCIDev; + ar3kconfig.pHCIProps = &pHcidevInfo->HCIProps; +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + ar3kconfig.pHIFDevice = (HIF_DEVICE *)(pHcidevInfo->HCITransHdl.hifDevice); +#else + ar3kconfig.pHIFDevice = pHcidevInfo->ar->arHifDevice; +#endif + ar3kconfig.pBtStackHCIDev = pHcidevInfo->pBtStackHCIDev; + + if (ar3khcibaud != 0) { + /* user wants ar3k baud rate change */ + ar3kconfig.Flags |= AR3K_CONFIG_FLAG_SET_AR3K_BAUD; + ar3kconfig.Flags |= AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY; + ar3kconfig.AR3KBaudRate = ar3khcibaud; + } + + if ((hciuartscale != 0) || (hciuartstep != 0)) { + /* user wants to tune HCI bridge UART scale/step values */ + ar3kconfig.AR6KScale = (A_UINT16)hciuartscale; + ar3kconfig.AR6KStep = (A_UINT16)hciuartstep; + ar3kconfig.Flags |= AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP; + } + + /* configure the AR3K device */ + status = AR3KConfigure(&ar3kconfig); + if (A_FAILED(status)) { + break; + } + + status = bt_register_hci(pHcidevInfo); + + } while (FALSE); + + return status; +} + +static void ar6000_hci_transport_failure(void *pContext, A_STATUS Status) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext; + + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: transport failure! \n")); + + if (pHcidevInfo->HciNormalMode) { + /* TODO .. */ + } +} + +static void ar6000_hci_transport_removed(void *pContext) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext; + + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: transport removed. \n")); + + A_ASSERT(pHcidevInfo->pHCIDev != NULL); + + HCI_TransportDetach(pHcidevInfo->pHCIDev); + bt_cleanup_hci(pHcidevInfo); + pHcidevInfo->pHCIDev = NULL; +} + +static void ar6000_hci_send_complete(void *pContext, HTC_PACKET *pPacket) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext; + void *osbuf = pPacket->pPktContext; + A_ASSERT(osbuf != NULL); + A_ASSERT(pHcidevInfo != NULL); + + if (A_FAILED(pPacket->Status)) { + if ((pPacket->Status != A_ECANCELED) && (pPacket->Status != A_NO_RESOURCE)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: Send Packet Failed: %d \n",pPacket->Status)); + } + } + + FreeHTCStruct(pHcidevInfo,pPacket); + FreeBtOsBuf(pHcidevInfo,osbuf); + +} + +static void ar6000_hci_pkt_recv(void *pContext, HTC_PACKET *pPacket) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext; + struct sk_buff *skb; + + A_ASSERT(pHcidevInfo != NULL); + skb = (struct sk_buff *)pPacket->pPktContext; + A_ASSERT(skb != NULL); + + do { + + if (A_FAILED(pPacket->Status)) { + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, + ("HCI Bridge, packet received type : %d len:%d \n", + HCI_GET_PACKET_TYPE(pPacket),pPacket->ActualLength)); + + /* set the actual buffer position in the os buffer, HTC recv buffers posted to HCI are set + * to fill the front of the buffer */ + A_NETBUF_PUT(skb,pPacket->ActualLength + pHcidevInfo->HCIProps.HeadRoom); + A_NETBUF_PULL(skb,pHcidevInfo->HCIProps.HeadRoom); + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("<<< Recv HCI %s packet len:%d \n", + (HCI_GET_PACKET_TYPE(pPacket) == HCI_EVENT_TYPE) ? "EVENT" : "ACL", + skb->len)); + AR_DEBUG_PRINTBUF(skb->data, skb->len,"BT HCI RECV Packet Dump"); + } + + if (pHcidevInfo->HciNormalMode) { + /* indicate the packet */ + if (bt_indicate_recv(pHcidevInfo,HCI_GET_PACKET_TYPE(pPacket),skb)) { + /* bt stack accepted the packet */ + skb = NULL; + } + break; + } + + /* for testing, indicate packet to the network stack */ +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + skb->dev = (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice); + if ((((struct net_device *)pHcidevInfo->HCITransHdl.netDevice)->flags & IFF_UP) == IFF_UP) { + skb->protocol = eth_type_trans(skb, (struct net_device *)(pHcidevInfo->HCITransHdl.netDevice)); +#else + skb->dev = pHcidevInfo->ar->arNetDev; + if ((pHcidevInfo->ar->arNetDev->flags & IFF_UP) == IFF_UP) { + skb->protocol = eth_type_trans(skb, pHcidevInfo->ar->arNetDev); +#endif + netif_rx(skb); + skb = NULL; + } + + } while (FALSE); + + FreeHTCStruct(pHcidevInfo,pPacket); + + if (skb != NULL) { + /* packet was not accepted, free it */ + FreeBtOsBuf(pHcidevInfo,skb); + } + +} + +static void ar6000_hci_pkt_refill(void *pContext, HCI_TRANSPORT_PACKET_TYPE Type, int BuffersAvailable) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext; + int refillCount; + + if (Type == HCI_ACL_TYPE) { + refillCount = MAX_ACL_RECV_BUFS - BuffersAvailable; + } else { + refillCount = MAX_EVT_RECV_BUFS - BuffersAvailable; + } + + if (refillCount > 0) { + RefillRecvBuffers(pHcidevInfo,Type,refillCount); + } + +} + +static HCI_SEND_FULL_ACTION ar6000_hci_pkt_send_full(void *pContext, HTC_PACKET *pPacket) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)pContext; + HCI_SEND_FULL_ACTION action = HCI_SEND_FULL_KEEP; + + if (!pHcidevInfo->HciNormalMode) { + /* for epping testing, check packet tag, some epping packets are + * special and cannot be dropped */ + if (HTC_GET_TAG_FROM_PKT(pPacket) == AR6K_DATA_PKT_TAG) { + action = HCI_SEND_FULL_DROP; + } + } + + return action; +} + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +A_STATUS ar6000_setup_hci(void *ar) +#else +A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar) +#endif +{ + HCI_TRANSPORT_CONFIG_INFO config; + A_STATUS status = A_OK; + int i; + HTC_PACKET *pPacket; + AR6K_HCI_BRIDGE_INFO *pHcidevInfo; + + + do { + + pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)A_MALLOC(sizeof(AR6K_HCI_BRIDGE_INFO)); + + if (NULL == pHcidevInfo) { + status = A_NO_MEMORY; + break; + } + + A_MEMZERO(pHcidevInfo, sizeof(AR6K_HCI_BRIDGE_INFO)); +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + g_pHcidevInfo = pHcidevInfo; + pHcidevInfo->HCITransHdl = *(HCI_TRANSPORT_MISC_HANDLES *)ar; +#else + ar->hcidev_info = pHcidevInfo; + pHcidevInfo->ar = ar; +#endif + spin_lock_init(&pHcidevInfo->BridgeLock); + INIT_HTC_PACKET_QUEUE(&pHcidevInfo->HTCPacketStructHead); + + ar->exitCallback = AR3KConfigureExit; + + status = bt_setup_hci(pHcidevInfo); + if (A_FAILED(status)) { + break; + } + + if (pHcidevInfo->HciNormalMode) { + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: running in normal mode... \n")); + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: running in test mode... \n")); + } + + pHcidevInfo->pHTCStructAlloc = (A_UINT8 *)A_MALLOC((sizeof(HTC_PACKET)) * NUM_HTC_PACKET_STRUCTS); + + if (NULL == pHcidevInfo->pHTCStructAlloc) { + status = A_NO_MEMORY; + break; + } + + pPacket = (HTC_PACKET *)pHcidevInfo->pHTCStructAlloc; + for (i = 0; i < NUM_HTC_PACKET_STRUCTS; i++,pPacket++) { + FreeHTCStruct(pHcidevInfo,pPacket); + } + + A_MEMZERO(&config,sizeof(HCI_TRANSPORT_CONFIG_INFO)); + config.ACLRecvBufferWaterMark = MAX_ACL_RECV_BUFS / 2; + config.EventRecvBufferWaterMark = MAX_EVT_RECV_BUFS / 2; + config.MaxSendQueueDepth = MAX_HCI_WRITE_QUEUE_DEPTH; + config.pContext = pHcidevInfo; + config.TransportFailure = ar6000_hci_transport_failure; + config.TransportReady = ar6000_hci_transport_ready; + config.TransportRemoved = ar6000_hci_transport_removed; + config.pHCISendComplete = ar6000_hci_send_complete; + config.pHCIPktRecv = ar6000_hci_pkt_recv; + config.pHCIPktRecvRefill = ar6000_hci_pkt_refill; + config.pHCISendFull = ar6000_hci_pkt_send_full; + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + pHcidevInfo->pHCIDev = HCI_TransportAttach(pHcidevInfo->HCITransHdl.htcHandle, &config); +#else + pHcidevInfo->pHCIDev = HCI_TransportAttach(ar->arHtcTarget, &config); +#endif + + if (NULL == pHcidevInfo->pHCIDev) { + status = A_ERROR; + } + + } while (FALSE); + + if (A_FAILED(status)) { + if (pHcidevInfo != NULL) { + if (NULL == pHcidevInfo->pHCIDev) { + /* GMBOX may not be present in older chips */ + /* just return success */ + status = A_OK; + } + } + ar6000_cleanup_hci(ar); + } + + return status; +} + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +void ar6000_cleanup_hci(void *ar) +#else +void ar6000_cleanup_hci(AR_SOFTC_T *ar) +#endif +{ +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = g_pHcidevInfo; +#else + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info; +#endif + + if (pHcidevInfo != NULL) { + bt_cleanup_hci(pHcidevInfo); + + if (pHcidevInfo->pHCIDev != NULL) { + HCI_TransportStop(pHcidevInfo->pHCIDev); + HCI_TransportDetach(pHcidevInfo->pHCIDev); + pHcidevInfo->pHCIDev = NULL; + } + + if (pHcidevInfo->pHTCStructAlloc != NULL) { + A_FREE(pHcidevInfo->pHTCStructAlloc); + pHcidevInfo->pHTCStructAlloc = NULL; + } + + A_FREE(pHcidevInfo); +#ifndef EXPORT_HCI_BRIDGE_INTERFACE + ar->hcidev_info = NULL; +#endif + } + + +} + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +A_STATUS hci_test_send(void *ar, struct sk_buff *skb) +#else +A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb) +#endif +{ + int status = A_OK; + int length; + EPPING_HEADER *pHeader; + HTC_PACKET *pPacket; + HTC_TX_TAG htc_tag = AR6K_DATA_PKT_TAG; +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = g_pHcidevInfo; +#else + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info; +#endif + + do { + + if (NULL == pHcidevInfo) { + status = A_ERROR; + break; + } + + if (NULL == pHcidevInfo->pHCIDev) { + status = A_ERROR; + break; + } + + if (pHcidevInfo->HciNormalMode) { + /* this interface cannot run when normal WMI is running */ + status = A_ERROR; + break; + } + + pHeader = (EPPING_HEADER *)A_NETBUF_DATA(skb); + + if (!IS_EPPING_PACKET(pHeader)) { + status = A_EINVAL; + break; + } + + if (IS_EPING_PACKET_NO_DROP(pHeader)) { + htc_tag = AR6K_CONTROL_PKT_TAG; + } + + length = sizeof(EPPING_HEADER) + pHeader->DataLength; + + pPacket = AllocHTCStruct(pHcidevInfo); + if (NULL == pPacket) { + status = A_NO_MEMORY; + break; + } + + SET_HTC_PACKET_INFO_TX(pPacket, + skb, + A_NETBUF_DATA(skb), + length, + HCI_ACL_TYPE, /* send every thing out as ACL */ + htc_tag); + + HCI_TransportSendPkt(pHcidevInfo->pHCIDev,pPacket,FALSE); + pPacket = NULL; + + } while (FALSE); + + return status; +} + +void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)ar->hcidev_info; + AR3K_CONFIG_INFO *config = (AR3K_CONFIG_INFO *)ar3kconfig; + + config->pHCIDev = pHcidevInfo->pHCIDev; + config->pHCIProps = &pHcidevInfo->HCIProps; + config->pHIFDevice = ar->arHifDevice; + config->pBtStackHCIDev = pHcidevInfo->pBtStackHCIDev; + config->Flags |= AR3K_CONFIG_FLAG_SET_AR3K_BAUD; + config->AR3KBaudRate = 115200; +} + +#ifdef CONFIG_BLUEZ_HCI_BRIDGE +/*** BT Stack Entrypoints *******/ + +/* + * bt_open - open a handle to the device +*/ +static int bt_open(struct hci_dev *hdev) +{ + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_open - enter - x\n")); + set_bit(HCI_RUNNING, &hdev->flags); + set_bit(HCI_UP, &hdev->flags); + set_bit(HCI_INIT, &hdev->flags); + return 0; +} + +/* + * bt_close - close handle to the device +*/ +static int bt_close(struct hci_dev *hdev) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_close - enter\n")); + clear_bit(HCI_RUNNING, &hdev->flags); + return 0; +} + +/* + * bt_send_frame - send data frames +*/ +static int bt_send_frame(struct sk_buff *skb) +{ + struct hci_dev *hdev = (struct hci_dev *)skb->dev; + HCI_TRANSPORT_PACKET_TYPE type; + AR6K_HCI_BRIDGE_INFO *pHcidevInfo; + A_UINT8 *pTemp; + HTC_PACKET *pPacket; + A_STATUS status = A_OK; + struct sk_buff *txSkb = NULL; + + if (!hdev) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HCI Bridge: bt_send_frame - no device\n")); + return -ENODEV; + } + + if (!test_bit(HCI_RUNNING, &hdev->flags)) { + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_send_frame - not open\n")); + return -EBUSY; + } + + pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)hdev->driver_data; + A_ASSERT(pHcidevInfo != NULL); + + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("+bt_send_frame type: %d \n",bt_cb(skb)->pkt_type)); + type = HCI_COMMAND_TYPE; + + switch (bt_cb(skb)->pkt_type) { + case HCI_COMMAND_PKT: + type = HCI_COMMAND_TYPE; + hdev->stat.cmd_tx++; + break; + + case HCI_ACLDATA_PKT: + type = HCI_ACL_TYPE; + hdev->stat.acl_tx++; + break; + + case HCI_SCODATA_PKT: + /* we don't support SCO over the bridge */ + kfree_skb(skb); + return 0; + default: + A_ASSERT(FALSE); + kfree_skb(skb); + return 0; + } + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(">>> Send HCI %s packet len: %d\n", + (type == HCI_COMMAND_TYPE) ? "COMMAND" : "ACL", + skb->len)); + if (type == HCI_COMMAND_TYPE) { + A_UINT16 opcode = HCI_GET_OP_CODE(skb->data); + AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(" HCI Command: OGF:0x%X OCF:0x%X \r\n", + opcode >> 10, opcode & 0x3FF)); + } + AR_DEBUG_PRINTBUF(skb->data,skb->len,"BT HCI SEND Packet Dump"); + } + + do { + + txSkb = bt_skb_alloc(TX_PACKET_RSV_OFFSET + pHcidevInfo->HCIProps.HeadRoom + + pHcidevInfo->HCIProps.TailRoom + skb->len, + GFP_ATOMIC); + + if (txSkb == NULL) { + status = A_NO_MEMORY; + break; + } + + bt_cb(txSkb)->pkt_type = bt_cb(skb)->pkt_type; + txSkb->dev = (void *)pHcidevInfo->pBtStackHCIDev; + skb_reserve(txSkb, TX_PACKET_RSV_OFFSET + pHcidevInfo->HCIProps.HeadRoom); + A_MEMCPY(txSkb->data, skb->data, skb->len); + skb_put(txSkb,skb->len); + + /* push on header transport space */ + pTemp = (A_UINT8 *)skb_push(txSkb, pHcidevInfo->HCIProps.HeadRoom); + pPacket = AllocHTCStruct(pHcidevInfo); + if (NULL == pPacket) { + status = A_NO_MEMORY; + break; + } + + SET_HTC_PACKET_INFO_TX(pPacket, + txSkb, + pTemp + pHcidevInfo->HCIProps.HeadRoom, + txSkb->len, + type, + AR6K_CONTROL_PKT_TAG); /* HCI packets cannot be dropped */ + + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("HCI Bridge: bt_send_frame skb:0x%X \n",(A_UINT32)txSkb)); + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("HCI Bridge: type:%d, Total Length:%d Bytes \n", + type, txSkb->len)); + + status = HCI_TransportSendPkt(pHcidevInfo->pHCIDev,pPacket,FALSE); + pPacket = NULL; + txSkb = NULL; + + } while (FALSE); + + if (txSkb != NULL) { + kfree_skb(txSkb); + } + + kfree_skb(skb); + + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_SEND, ("-bt_send_frame \n")); + return 0; +} + +/* + * bt_ioctl - ioctl processing +*/ +static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_ioctl - enter\n")); + return -ENOIOCTLCMD; +} + +/* + * bt_flush - flush outstandingbpackets +*/ +static int bt_flush(struct hci_dev *hdev) +{ + AR6K_HCI_BRIDGE_INFO *pHcidevInfo; + + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_flush - enter\n")); + + pHcidevInfo = (AR6K_HCI_BRIDGE_INFO *)hdev->driver_data; + + /* TODO??? */ + + return 0; +} + + +/* + * bt_destruct - +*/ +static void bt_destruct(struct hci_dev *hdev) +{ + AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HCI Bridge: bt_destruct - enter\n")); + /* nothing to do here */ +} + +static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo) +{ + A_STATUS status = A_OK; + struct hci_dev *pHciDev = NULL; + HIF_DEVICE_OS_DEVICE_INFO osDevInfo; + + if (!setupbtdev) { + return A_OK; + } + + do { + + A_MEMZERO(&osDevInfo,sizeof(osDevInfo)); + /* get the underlying OS device */ +#ifdef EXPORT_HCI_BRIDGE_INTERFACE + status = ar6000_get_hif_dev((HIF_DEVICE *)(pHcidevInfo->HCITransHdl.hifDevice), + &osDevInfo); +#else + status = HIFConfigureDevice(pHcidevInfo->ar->arHifDevice, + HIF_DEVICE_GET_OS_DEVICE, + &osDevInfo, + sizeof(osDevInfo)); +#endif + + if (A_FAILED(status)) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to OS device info from HIF\n")); + break; + } + + /* allocate a BT HCI struct for this device */ + pHciDev = hci_alloc_dev(); + if (NULL == pHciDev) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge - failed to allocate bt struct \n")); + status = A_NO_MEMORY; + break; + } + /* save the device, we'll register this later */ + pHcidevInfo->pBtStackHCIDev = pHciDev; + SET_HCIDEV_DEV(pHciDev,osDevInfo.pOSDevice); + pHciDev->type = HCI_VIRTUAL; + pHciDev->driver_data = pHcidevInfo; + pHciDev->open = bt_open; + pHciDev->close = bt_close; + pHciDev->send = bt_send_frame; + pHciDev->ioctl = bt_ioctl; + pHciDev->flush = bt_flush; + pHciDev->destruct = bt_destruct; + pHciDev->owner = THIS_MODULE; + /* driver is running in normal BT mode */ + pHcidevInfo->HciNormalMode = TRUE; + + } while (FALSE); + + if (A_FAILED(status)) { + bt_cleanup_hci(pHcidevInfo); + } + + return status; +} + +static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo) +{ + int err; + + if (pHcidevInfo->HciRegistered) { + pHcidevInfo->HciRegistered = FALSE; + clear_bit(HCI_RUNNING, &pHcidevInfo->pBtStackHCIDev->flags); + clear_bit(HCI_UP, &pHcidevInfo->pBtStackHCIDev->flags); + clear_bit(HCI_INIT, &pHcidevInfo->pBtStackHCIDev->flags); + A_ASSERT(pHcidevInfo->pBtStackHCIDev != NULL); + /* unregister */ + if ((err = hci_unregister_dev(pHcidevInfo->pBtStackHCIDev)) < 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to unregister with bluetooth %d\n",err)); + } + } + + if (pHcidevInfo->pBtStackHCIDev != NULL) { + kfree(pHcidevInfo->pBtStackHCIDev); + pHcidevInfo->pBtStackHCIDev = NULL; + } +} + +static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo) +{ + int err; + A_STATUS status = A_OK; + + do { + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: registering HCI... \n")); + A_ASSERT(pHcidevInfo->pBtStackHCIDev != NULL); + /* mark that we are registered */ + pHcidevInfo->HciRegistered = TRUE; + if ((err = hci_register_dev(pHcidevInfo->pBtStackHCIDev)) < 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: failed to register with bluetooth %d\n",err)); + pHcidevInfo->HciRegistered = FALSE; + status = A_ERROR; + break; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_BRIDGE, ("HCI Bridge: HCI registered \n")); + + } while (FALSE); + + return status; +} + +static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, + HCI_TRANSPORT_PACKET_TYPE Type, + struct sk_buff *skb) +{ + A_UINT8 btType; + int len; + A_BOOL success = FALSE; + BT_HCI_EVENT_HEADER *pEvent; + + do { + + if (!test_bit(HCI_RUNNING, &pHcidevInfo->pBtStackHCIDev->flags)) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("HCI Bridge: bt_indicate_recv - not running\n")); + break; + } + + switch (Type) { + case HCI_ACL_TYPE: + btType = HCI_ACLDATA_PKT; + break; + case HCI_EVENT_TYPE: + btType = HCI_EVENT_PKT; + break; + default: + btType = 0; + A_ASSERT(FALSE); + break; + } + + if (0 == btType) { + break; + } + + /* set the final type */ + bt_cb(skb)->pkt_type = btType; + /* set dev */ + skb->dev = (void *)pHcidevInfo->pBtStackHCIDev; + len = skb->len; + + if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_RECV)) { + if (bt_cb(skb)->pkt_type == HCI_EVENT_PKT) { + pEvent = (BT_HCI_EVENT_HEADER *)skb->data; + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, ("BT HCI EventCode: %d, len:%d \n", + pEvent->EventCode, pEvent->ParamLength)); + } + } + + /* pass receive packet up the stack */ + if (hci_recv_frame(skb) != 0) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HCI Bridge: hci_recv_frame failed \n")); + break; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_HCI_RECV, + ("HCI Bridge: Indicated RCV of type:%d, Length:%d \n",btType,len)); + } + + success = TRUE; + + } while (FALSE); + + return success; +} + +static struct sk_buff* bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length) +{ + struct sk_buff *skb; + /* in normal HCI mode we need to alloc from the bt core APIs */ + skb = bt_skb_alloc(Length, GFP_ATOMIC); + if (NULL == skb) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to alloc bt sk_buff \n")); + } + return skb; +} + +static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb) +{ + kfree_skb(skb); +} + +#else // { CONFIG_BLUEZ_HCI_BRIDGE + + /* stubs when we only want to test the HCI bridging Interface without the HT stack */ +static A_STATUS bt_setup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo) +{ + return A_OK; +} +static void bt_cleanup_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo) +{ + +} +static A_STATUS bt_register_hci(AR6K_HCI_BRIDGE_INFO *pHcidevInfo) +{ + A_ASSERT(FALSE); + return A_ERROR; +} + +static A_BOOL bt_indicate_recv(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, + HCI_TRANSPORT_PACKET_TYPE Type, + struct sk_buff *skb) +{ + A_ASSERT(FALSE); + return FALSE; +} + +static struct sk_buff* bt_alloc_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, int Length) +{ + A_ASSERT(FALSE); + return NULL; +} +static void bt_free_buffer(AR6K_HCI_BRIDGE_INFO *pHcidevInfo, struct sk_buff *skb) +{ + A_ASSERT(FALSE); +} + +#endif // } CONFIG_BLUEZ_HCI_BRIDGE + +#else // { ATH_AR6K_ENABLE_GMBOX + + /* stubs when GMBOX support is not needed */ + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +A_STATUS ar6000_setup_hci(void *ar) +#else +A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar) +#endif +{ + return A_OK; +} + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +void ar6000_cleanup_hci(void *ar) +#else +void ar6000_cleanup_hci(AR_SOFTC_T *ar) +#endif +{ + return; +} + +#ifndef EXPORT_HCI_BRIDGE_INTERFACE +void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig) +{ + return; +} +#endif + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +int hci_test_send(void *ar, struct sk_buff *skb) +#else +int hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb) +#endif +{ + return -EOPNOTSUPP; +} + +#endif // } ATH_AR6K_ENABLE_GMBOX + + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +static int __init +hcibridge_init_module(void) +{ + A_STATUS status; + HCI_TRANSPORT_CALLBACKS hciTransCallbacks; + + hciTransCallbacks.setupTransport = ar6000_setup_hci; + hciTransCallbacks.cleanupTransport = ar6000_cleanup_hci; + + status = ar6000_register_hci_transport(&hciTransCallbacks); + if(status != A_OK) + return -ENODEV; + + return 0; +} + +static void __exit +hcibridge_cleanup_module(void) +{ +} + +module_init(hcibridge_init_module); +module_exit(hcibridge_cleanup_module); +MODULE_LICENSE("GPL and additional rights"); +#endif diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h b/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h new file mode 100644 index 000000000000..3df15b71133a --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/ar6000_drv.h @@ -0,0 +1,694 @@ +/* + * + * Copyright (c) 2004-2010 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef _AR6000_H_ +#define _AR6000_H_ + +#include + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) +#include +#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) +#include +#else +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) +#include +#else +#include +#endif +#include +#ifdef ATH6K_CONFIG_CFG80211 +#include +#endif /* ATH6K_CONFIG_CFG80211 */ +#include +#include + +#include +#include +#include "a_types.h" +#include "a_osapi.h" +#include "htc_api.h" +#include "wmi.h" +#include "a_drv.h" +#include "bmi.h" +#include +#include +#include +#include +#include "gpio_api.h" +#include "gpio.h" +#include "pkt_log.h" +#include "aggr_recv_api.h" +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#include +#else +#include +#include +#endif +#include "ar6000_api.h" +#ifdef CONFIG_HOST_TCMD_SUPPORT +#include +#endif +#include + +#include "targaddrs.h" +#include "dbglog_api.h" +#include "ar6000_diag.h" +#include "common_drv.h" +#include "roaming.h" +#include "hci_transport_api.h" +#define ATH_MODULE_NAME driver +#include "a_debug.h" +#include "hw/apb_map.h" +#include "hw/rtc_reg.h" +#include "hw/mbox_reg.h" +#include "hw/gpio_reg.h" + +#define ATH_DEBUG_DBG_LOG ATH_DEBUG_MAKE_MODULE_MASK(0) +#define ATH_DEBUG_WLAN_CONNECT ATH_DEBUG_MAKE_MODULE_MASK(1) +#define ATH_DEBUG_WLAN_SCAN ATH_DEBUG_MAKE_MODULE_MASK(2) +#define ATH_DEBUG_WLAN_TX ATH_DEBUG_MAKE_MODULE_MASK(3) +#define ATH_DEBUG_WLAN_RX ATH_DEBUG_MAKE_MODULE_MASK(4) +#define ATH_DEBUG_HTC_RAW ATH_DEBUG_MAKE_MODULE_MASK(5) +#define ATH_DEBUG_HCI_BRIDGE ATH_DEBUG_MAKE_MODULE_MASK(6) +#define ATH_DEBUG_HCI_RECV ATH_DEBUG_MAKE_MODULE_MASK(7) +#define ATH_DEBUG_HCI_SEND ATH_DEBUG_MAKE_MODULE_MASK(8) +#define ATH_DEBUG_HCI_DUMP ATH_DEBUG_MAKE_MODULE_MASK(9) + +#ifndef __dev_put +#define __dev_put(dev) dev_put(dev) +#endif + + +#ifdef USER_KEYS + +#define USER_SAVEDKEYS_STAT_INIT 0 +#define USER_SAVEDKEYS_STAT_RUN 1 + +// TODO this needs to move into the AR_SOFTC struct +struct USER_SAVEDKEYS { + struct ieee80211req_key ucast_ik; + struct ieee80211req_key bcast_ik; + CRYPTO_TYPE keyType; + A_BOOL keyOk; +}; +#endif + +#define DBG_INFO 0x00000001 +#define DBG_ERROR 0x00000002 +#define DBG_WARNING 0x00000004 +#define DBG_SDIO 0x00000008 +#define DBG_HIF 0x00000010 +#define DBG_HTC 0x00000020 +#define DBG_WMI 0x00000040 +#define DBG_WMI2 0x00000080 +#define DBG_DRIVER 0x00000100 + +#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING) + + +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data); + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_AR6000 1 +#define AR6000_MAX_RX_BUFFERS 16 +#define AR6000_BUFFER_SIZE 1664 +#define AR6000_MAX_AMSDU_RX_BUFFERS 4 +#define AR6000_AMSDU_REFILL_THRESHOLD 3 +#define AR6000_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128) +#define AR6000_MAX_RX_MESSAGE_SIZE (max(WMI_MAX_NORMAL_RX_DATA_FRAME_LENGTH,WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH)) + +#define AR6000_TX_TIMEOUT 10 +#define AR6000_ETH_ADDR_LEN 6 +#define AR6000_MAX_ENDPOINTS 4 +#define MAX_NODE_NUM 15 +/* MAX_HI_COOKIE_NUM are reserved for high priority traffic */ +#define MAX_DEF_COOKIE_NUM 150 +#define MAX_HI_COOKIE_NUM 15 /* 10% of MAX_COOKIE_NUM */ +#define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM) + +/* MAX_DEFAULT_SEND_QUEUE_DEPTH is used to set the default queue depth for the + * WMM send queues. If a queue exceeds this depth htc will query back to the + * OS specific layer by calling EpSendFull(). This gives the OS layer the + * opportunity to drop the packet if desired. Therefore changing + * MAX_DEFAULT_SEND_QUEUE_DEPTH does not affect resource utilization but + * does impact the threshold used to identify if a packet should be + * dropped. */ +#define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC) + +#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT 1 +#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT 1 +#define A_DISCONNECT_TIMER_INTERVAL 10 * 1000 +#define A_DEFAULT_LISTEN_INTERVAL 100 +#define A_MAX_WOW_LISTEN_INTERVAL 1000 + +enum { + DRV_HB_CHALLENGE = 0, + APP_HB_CHALLENGE +}; + +enum { + WLAN_INIT_MODE_NONE = 0, + WLAN_INIT_MODE_USR, + WLAN_INIT_MODE_UDEV, + WLAN_INIT_MODE_DRV +}; + +typedef enum _AR6K_BIN_FILE { + AR6K_OTP_FILE, + AR6K_FIRMWARE_FILE, + AR6K_PATCH_FILE, + AR6K_BOARD_DATA_FILE, +} AR6K_BIN_FILE; + +#ifdef SETUPHCI_ENABLED +#define SETUPHCI_DEFAULT 1 +#else +#define SETUPHCI_DEFAULT 0 +#endif /* SETUPHCI_ENABLED */ + +#ifdef SETUPBTDEV_ENABLED +#define SETUPBTDEV_DEFAULT 1 +#else +#define SETUPBTDEV_DEFAULT 0 +#endif /* SETUPBTDEV_ENABLED */ + +#ifdef BMIENABLE_SET +#define BMIENABLE_DEFAULT 1 +#else +#define BMIENABLE_DEFAULT 0 +#endif /* BMIENABLE_SET */ + +#ifdef ENABLEUARTPRINT_SET +#define ENABLEUARTPRINT_DEFAULT 1 +#else +#define ENABLEUARTPRINT_DEFAULT 0 +#endif /* ENABLEARTPRINT_SET */ + +#ifdef ATH6K_CONFIG_HIF_VIRTUAL_SCATTER +#define NOHIFSCATTERSUPPORT_DEFAULT 1 +#else /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */ +#define NOHIFSCATTERSUPPORT_DEFAULT 0 +#endif /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */ + +#ifdef AR600x_BT_AR3001 +#define AR3KHCIBAUD_DEFAULT 3000000 +#define HCIUARTSCALE_DEFAULT 1 +#define HCIUARTSTEP_DEFAULT 8937 +#else +#define AR3KHCIBAUD_DEFAULT 0 +#define HCIUARTSCALE_DEFAULT 0 +#define HCIUARTSTEP_DEFAULT 0 +#endif /* AR600x_BT_AR3001 */ + +#ifdef INIT_MODE_DRV_ENABLED +#define WLAN_INIT_MODE_DEFAULT WLAN_INIT_MODE_DRV +#else +#define WLAN_INIT_MODE_DEFAULT WLAN_INIT_MODE_USR +#endif /* INIT_MODE_DRV_ENABLED */ + +#define AR6K_PATCH_DOWNLOAD_ADDRESS(_param, _ver) do { \ + if ((_ver) == AR6003_REV1_VERSION) { \ + (_param) = AR6003_REV1_PATCH_DOWNLOAD_ADDRESS; \ + } else if ((_ver) == AR6003_REV2_VERSION) { \ + (_param) = AR6003_REV2_PATCH_DOWNLOAD_ADDRESS; \ + } else { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \ + A_ASSERT(0); \ + } \ +} while (0) + +#define AR6K_DATA_DOWNLOAD_ADDRESS(_param, _ver) do { \ + if ((_ver) == AR6003_REV1_VERSION) { \ + (_param) = AR6003_REV1_DATA_DOWNLOAD_ADDRESS; \ + } else if ((_ver) == AR6003_REV2_VERSION) { \ + (_param) = AR6003_REV2_DATA_DOWNLOAD_ADDRESS; \ + } else { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \ + A_ASSERT(0); \ + } \ +} while (0) + +#define AR6K_APP_START_OVERRIDE_ADDRESS(_param, _ver) do { \ + if ((_ver) == AR6003_REV1_VERSION) { \ + (_param) = AR6003_REV1_APP_START_OVERRIDE; \ + } else if ((_ver) == AR6003_REV2_VERSION) { \ + (_param) = AR6003_REV2_APP_START_OVERRIDE; \ + } else { \ + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \ + A_ASSERT(0); \ + } \ +} while (0) + +/* AR6003 1.0 definitions */ +#define AR6003_REV1_VERSION 0x300002ba +#define AR6003_REV1_DATA_DOWNLOAD_ADDRESS AR6003_REV1_OTP_DATA_ADDRESS +#define AR6003_REV1_PATCH_DOWNLOAD_ADDRESS 0x57ea6c +#define AR6003_REV1_OTP_FILE "ath6k/AR6003/hw1.0/otp.bin.z77" +#define AR6003_REV1_FIRMWARE_FILE "ath6k/AR6003/hw1.0/athwlan.bin.z77" +#define AR6003_REV1_TCMD_FIRMWARE_FILE "ath6k/AR6003/hw1.0/athtcmd_ram.bin" +#define AR6003_REV1_ART_FIRMWARE_FILE "ath6k/AR6003/hw1.0/device.bin" +#define AR6003_REV1_PATCH_FILE "ath6k/AR6003/hw1.0/data.patch.bin" +#ifdef AR600x_SD31_XXX +#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.SD31.bin" +#elif defined(AR600x_SD32_XXX) +#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.SD32.bin" +#elif defined(AR600x_WB31_XXX) +#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.WB31.bin" +#else +#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.CUSTOM.bin" +#endif /* Board Data File */ + +/* AR6003 2.0 definitions */ +#define AR6003_REV2_VERSION 0x30000384 +#define AR6003_REV2_DATA_DOWNLOAD_ADDRESS AR6003_REV2_OTP_DATA_ADDRESS +#define AR6003_REV2_PATCH_DOWNLOAD_ADDRESS 0x57e918 +#define AR6003_REV2_OTP_FILE "ath6k/AR6003/hw2.0/otp.bin.z77" +#define AR6003_REV2_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athwlan.bin.z77" +#define AR6003_REV2_TCMD_FIRMWARE_FILE "ath6k/AR6003/hw2.0/athtcmd_ram.bin" +#define AR6003_REV2_ART_FIRMWARE_FILE "ath6k/AR6003/hw2.0/device.bin" +#define AR6003_REV2_PATCH_FILE "ath6k/AR6003/hw2.0/data.patch.bin" +#ifdef AR600x_SD31_XXX +#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.SD31.bin" +#elif defined(AR600x_SD32_XXX) +#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.SD32.bin" +#elif defined(AR600x_WB31_XXX) +#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.WB31.bin" +#else +#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.CUSTOM.bin" +#endif /* Board Data File */ + +/* HTC RAW streams */ +typedef enum _HTC_RAW_STREAM_ID { + HTC_RAW_STREAM_NOT_MAPPED = -1, + HTC_RAW_STREAM_0 = 0, + HTC_RAW_STREAM_1 = 1, + HTC_RAW_STREAM_2 = 2, + HTC_RAW_STREAM_3 = 3, + HTC_RAW_STREAM_NUM_MAX +} HTC_RAW_STREAM_ID; + +#define RAW_HTC_READ_BUFFERS_NUM 4 +#define RAW_HTC_WRITE_BUFFERS_NUM 4 + +#define HTC_RAW_BUFFER_SIZE 1664 + +typedef struct { + int currPtr; + int length; + unsigned char data[HTC_RAW_BUFFER_SIZE]; + HTC_PACKET HTCPacket; +} raw_htc_buffer; + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* + * add TCMD_MODE besides wmi and bypasswmi + * in TCMD_MODE, only few TCMD releated wmi commands + * counld be hanlder + */ +enum { + AR6000_WMI_MODE = 0, + AR6000_BYPASS_MODE, + AR6000_TCMD_MODE, + AR6000_WLAN_MODE +}; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +struct ar_wep_key { + A_UINT8 arKeyIndex; + A_UINT8 arKeyLen; + A_UINT8 arKey[64]; +} ; + +#ifdef ATH6K_CONFIG_CFG80211 +struct ar_key { + A_UINT8 key[WLAN_MAX_KEY_LEN]; + A_UINT8 key_len; + A_UINT8 seq[IW_ENCODE_SEQ_MAX_SIZE]; + A_UINT8 seq_len; + A_UINT32 cipher; +}; +#endif /* ATH6K_CONFIG_CFG80211 */ + + +struct ar_node_mapping { + A_UINT8 macAddress[6]; + A_UINT8 epId; + A_UINT8 txPending; +}; + +struct ar_cookie { + A_UINT32 arc_bp[2]; /* Must be first field */ + HTC_PACKET HtcPkt; /* HTC packet wrapper */ + struct ar_cookie *arc_list_next; +}; + +struct ar_hb_chlng_resp { + A_TIMER timer; + A_UINT32 frequency; + A_UINT32 seqNum; + A_BOOL outstanding; + A_UINT8 missCnt; + A_UINT8 missThres; +}; + +/* Per STA data, used in AP mode */ +/*TODO: All this should move to OS independent dir */ + +#define STA_PWR_MGMT_MASK 0x1 +#define STA_PWR_MGMT_SHIFT 0x0 +#define STA_PWR_MGMT_AWAKE 0x0 +#define STA_PWR_MGMT_SLEEP 0x1 + +#define STA_SET_PWR_SLEEP(sta) (sta->flags |= (STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT)) +#define STA_CLR_PWR_SLEEP(sta) (sta->flags &= ~(STA_PWR_MGMT_MASK << STA_PWR_MGMT_SHIFT)) +#define STA_IS_PWR_SLEEP(sta) ((sta->flags >> STA_PWR_MGMT_SHIFT) & STA_PWR_MGMT_MASK) + +#define STA_PS_POLLED_MASK 0x1 +#define STA_PS_POLLED_SHIFT 0x1 +#define STA_SET_PS_POLLED(sta) (sta->flags |= (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) +#define STA_CLR_PS_POLLED(sta) (sta->flags &= ~(STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) +#define STA_IS_PS_POLLED(sta) (sta->flags & (STA_PS_POLLED_MASK << STA_PS_POLLED_SHIFT)) + +typedef struct { + A_UINT16 flags; + A_UINT8 mac[ATH_MAC_LEN]; + A_UINT8 aid; + A_UINT8 keymgmt; + A_UINT8 ucipher; + A_UINT8 auth; + A_UINT8 wpa_ie[IEEE80211_MAX_IE]; + A_NETBUF_QUEUE_T psq; /* power save q */ + A_MUTEX_T psqLock; +} sta_t; + +typedef struct ar6_raw_htc { + HTC_ENDPOINT_ID arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX]; + HTC_RAW_STREAM_ID arEp2RawMapping[ENDPOINT_MAX]; + struct semaphore raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX]; + struct semaphore raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX]; + wait_queue_head_t raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX]; + raw_htc_buffer raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM]; + raw_htc_buffer raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM]; + A_BOOL write_buffer_available[HTC_RAW_STREAM_NUM_MAX]; + A_BOOL read_buffer_available[HTC_RAW_STREAM_NUM_MAX]; +} AR_RAW_HTC_T; + +typedef struct ar6_softc { + struct net_device *arNetDev; /* net_device pointer */ + void *arWmi; + int arTxPending[ENDPOINT_MAX]; + int arTotalTxDataPending; + A_UINT8 arNumDataEndPts; + A_BOOL arWmiEnabled; + A_BOOL arWmiReady; + A_BOOL arConnected; + HTC_HANDLE arHtcTarget; + void *arHifDevice; + spinlock_t arLock; + struct semaphore arSem; + int arSsidLen; + u_char arSsid[32]; + A_UINT8 arNextMode; + A_UINT8 arNetworkType; + A_UINT8 arDot11AuthMode; + A_UINT8 arAuthMode; + A_UINT8 arPairwiseCrypto; + A_UINT8 arPairwiseCryptoLen; + A_UINT8 arGroupCrypto; + A_UINT8 arGroupCryptoLen; + A_UINT8 arDefTxKeyIndex; + struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1]; + A_UINT8 arBssid[6]; + A_UINT8 arReqBssid[6]; + A_UINT16 arChannelHint; + A_UINT16 arBssChannel; + A_UINT16 arListenInterval; + struct ar6000_version arVersion; + A_UINT32 arTargetType; + A_INT8 arRssi; + A_UINT8 arTxPwr; + A_BOOL arTxPwrSet; + A_INT32 arBitRate; + struct net_device_stats arNetStats; + struct iw_statistics arIwStats; + A_INT8 arNumChannels; + A_UINT16 arChannelList[32]; + A_UINT32 arRegCode; + A_BOOL statsUpdatePending; + TARGET_STATS arTargetStats; + A_INT8 arMaxRetries; + A_UINT8 arPhyCapability; +#ifdef CONFIG_HOST_TCMD_SUPPORT + A_UINT8 tcmdRxReport; + A_UINT32 tcmdRxTotalPkt; + A_INT32 tcmdRxRssi; + A_UINT32 tcmdPm; + A_UINT32 arTargetMode; + A_UINT32 tcmdRxcrcErrPkt; + A_UINT32 tcmdRxsecErrPkt; + A_UINT16 tcmdRateCnt[TCMD_MAX_RATES]; + A_UINT16 tcmdRateCntShortGuard[TCMD_MAX_RATES]; +#endif + AR6000_WLAN_STATE arWlanState; + struct ar_node_mapping arNodeMap[MAX_NODE_NUM]; + A_UINT8 arIbssPsEnable; + A_UINT8 arNodeNum; + A_UINT8 arNexEpId; + struct ar_cookie *arCookieList; + A_UINT32 arCookieCount; + A_UINT32 arRateMask; + A_UINT8 arSkipScan; + A_UINT16 arBeaconInterval; + A_BOOL arConnectPending; + A_BOOL arWmmEnabled; + struct ar_hb_chlng_resp arHBChallengeResp; + A_UINT8 arKeepaliveConfigured; + A_UINT32 arMgmtFilter; + HTC_ENDPOINT_ID arAc2EpMapping[WMM_NUM_AC]; + A_BOOL arAcStreamActive[WMM_NUM_AC]; + A_UINT8 arAcStreamPriMap[WMM_NUM_AC]; + A_UINT8 arHiAcStreamActivePri; + A_UINT8 arEp2AcMapping[ENDPOINT_MAX]; + HTC_ENDPOINT_ID arControlEp; +#ifdef HTC_RAW_INTERFACE + AR_RAW_HTC_T *arRawHtc; +#endif + A_BOOL arNetQueueStopped; + A_BOOL arRawIfInit; + int arDeviceIndex; + COMMON_CREDIT_STATE_INFO arCreditStateInfo; + A_BOOL arWMIControlEpFull; + A_BOOL dbgLogFetchInProgress; + A_UCHAR log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE]; + A_UINT32 log_cnt; + A_UINT32 dbglog_init_done; + A_UINT32 arConnectCtrlFlags; +#ifdef USER_KEYS + A_INT32 user_savedkeys_stat; + A_UINT32 user_key_ctrl; + struct USER_SAVEDKEYS user_saved_keys; +#endif + USER_RSSI_THOLD rssi_map[12]; + A_UINT8 arUserBssFilter; + A_UINT16 ap_profile_flag; /* AP mode */ + WMI_AP_ACL g_acl; /* AP mode */ + sta_t sta_list[AP_MAX_NUM_STA]; /* AP mode */ + A_UINT8 sta_list_index; /* AP mode */ + struct ieee80211req_key ap_mode_bkey; /* AP mode */ + A_NETBUF_QUEUE_T mcastpsq; /* power save q for Mcast frames */ + A_MUTEX_T mcastpsqLock; + A_BOOL DTIMExpired; /* flag to indicate DTIM expired */ + A_UINT8 intra_bss; /* enable/disable intra bss data forward */ + void *aggr_cntxt; +#ifndef EXPORT_HCI_BRIDGE_INTERFACE + void *hcidev_info; +#endif + WMI_AP_MODE_STAT arAPStats; + A_UINT8 ap_hidden_ssid; + A_UINT8 ap_country_code[3]; + A_UINT8 ap_wmode; + A_UINT8 ap_dtim_period; + A_UINT16 ap_beacon_interval; + A_UINT16 arRTS; + A_UINT16 arACS; /* AP mode - Auto Channel Selection */ + HTC_PACKET_QUEUE amsdu_rx_buffer_queue; + A_BOOL bIsDestroyProgress; /* flag to indicate ar6k destroy is in progress */ + A_TIMER disconnect_timer; + A_UINT8 rxMetaVersion; +#ifdef WAPI_ENABLE + A_UINT8 arWapiEnable; +#endif + WMI_BTCOEX_CONFIG_EVENT arBtcoexConfig; + WMI_BTCOEX_STATS_EVENT arBtcoexStats; + A_INT32 (*exitCallback)(void *config); /* generic callback at AR6K exit */ + HIF_DEVICE_OS_DEVICE_INFO osDevInfo; +#ifdef ATH6K_CONFIG_CFG80211 + struct wireless_dev *wdev; + struct cfg80211_scan_request *scan_request; + struct ar_key keys[WMI_MAX_KEY_INDEX + 1]; +#endif /* ATH6K_CONFIG_CFG80211 */ +#if CONFIG_PM + A_UINT16 arOsPowerCtrl; + A_UINT16 arWowState; +#endif + A_BOOL scan_complete; + WMI_SCAN_PARAMS_CMD scParams; +} AR_SOFTC_T; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +/* Looks like we need this for 2.4 kernels */ +static inline void *ar6k_priv(struct net_device *dev) +{ + return(dev->priv); +} +#else +#ifdef ATH6K_CONFIG_CFG80211 +static inline void *ar6k_priv(struct net_device *dev) +{ + return (wdev_priv(dev->ieee80211_ptr)); +} +#else +#define ar6k_priv netdev_priv +#endif /* ATH6K_CONFIG_CFG80211 */ +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) */ + +#define arAc2EndpointID(ar,ac) (ar)->arAc2EpMapping[(ac)] +#define arSetAc2EndpointIDMap(ar,ac,ep) \ +{ (ar)->arAc2EpMapping[(ac)] = (ep); \ + (ar)->arEp2AcMapping[(ep)] = (ac); } +#define arEndpoint2Ac(ar,ep) (ar)->arEp2AcMapping[(ep)] + +#define arRawIfEnabled(ar) (ar)->arRawIfInit +#define arRawStream2EndpointID(ar,raw) (ar)->arRawHtc->arRaw2EpMapping[(raw)] +#define arSetRawStream2EndpointIDMap(ar,raw,ep) \ +{ (ar)->arRawHtc->arRaw2EpMapping[(raw)] = (ep); \ + (ar)->arRawHtc->arEp2RawMapping[(ep)] = (raw); } +#define arEndpoint2RawStreamID(ar,ep) (ar)->arRawHtc->arEp2RawMapping[(ep)] + +struct ar_giwscan_param { + char *current_ev; + char *end_buf; + A_UINT32 bytes_needed; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + struct iw_request_info *info; +#endif +}; + +#define AR6000_STAT_INC(ar, stat) (ar->arNetStats.stat++) + +#define AR6000_SPIN_LOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("IRQs disabled:AR6000_LOCK\n")); \ + } \ + spin_lock_bh(lock); \ +} while (0) + +#define AR6000_SPIN_UNLOCK(lock, param) do { \ + if (irqs_disabled()) { \ + AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("IRQs disabled: AR6000_UNLOCK\n")); \ + } \ + spin_unlock_bh(lock); \ +} while (0) + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd); +void ar6000_gpio_init(void); +void ar6000_init_profile_info(AR_SOFTC_T *ar); +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar); +int ar6000_init(struct net_device *dev); +int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar); +void ar6000_TxDataCleanup(AR_SOFTC_T *ar); +int ar6000_acl_data_tx(struct sk_buff *skb, struct net_device *dev); + +#ifdef HTC_RAW_INTERFACE + +#ifndef __user +#define __user +#endif + +int ar6000_htc_raw_open(AR_SOFTC_T *ar); +int ar6000_htc_raw_close(AR_SOFTC_T *ar); +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, + HTC_RAW_STREAM_ID StreamID, + char __user *buffer, size_t count); + +#endif /* HTC_RAW_INTERFACE */ + +/* AP mode */ +/*TODO: These routines should be moved to a file that is common across OS */ +sta_t * +ieee80211_find_conn(AR_SOFTC_T *ar, A_UINT8 *node_addr); + +sta_t * +ieee80211_find_conn_for_aid(AR_SOFTC_T *ar, A_UINT8 aid); + +A_UINT8 +remove_sta(AR_SOFTC_T *ar, A_UINT8 *mac, A_UINT16 reason); + +/* HCI support */ + +#ifndef EXPORT_HCI_BRIDGE_INTERFACE +A_STATUS ar6000_setup_hci(AR_SOFTC_T *ar); +void ar6000_cleanup_hci(AR_SOFTC_T *ar); +void ar6000_set_default_ar3kconfig(AR_SOFTC_T *ar, void *ar3kconfig); + +/* HCI bridge testing */ +A_STATUS hci_test_send(AR_SOFTC_T *ar, struct sk_buff *skb); +#endif + +ATH_DEBUG_DECLARE_EXTERN(htc); +ATH_DEBUG_DECLARE_EXTERN(wmi); +ATH_DEBUG_DECLARE_EXTERN(bmi); +ATH_DEBUG_DECLARE_EXTERN(hif); +ATH_DEBUG_DECLARE_EXTERN(wlan); +ATH_DEBUG_DECLARE_EXTERN(misc); + +extern A_UINT8 bcast_mac[]; +extern A_UINT8 null_mac[]; + +#ifdef __cplusplus +} +#endif + +#endif /* _AR6000_H_ */ diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h new file mode 100644 index 000000000000..fc5c363f9936 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/ar6xapi_linux.h @@ -0,0 +1,175 @@ +#ifndef _AR6XAPI_LINUX_H +#define _AR6XAPI_LINUX_H +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +struct ar6_softc; + +void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap, + A_UINT32 ver); +A_STATUS ar6000_control_tx(void *devt, void *osbuf, HTC_ENDPOINT_ID eid); +void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel, + A_UINT8 *bssid, A_UINT16 listenInterval, + A_UINT16 beaconInterval, NETWORK_TYPE networkType, + A_UINT8 beaconIeLen, A_UINT8 assocReqLen, + A_UINT8 assocRespLen,A_UINT8 *assocInfo); +void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason, + A_UINT8 *bssid, A_UINT8 assocRespLen, + A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus); +void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid, + A_BOOL ismcast); +void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps); +void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList); +void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode); +void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr); +void ar6000_keepalive_rx(void *devt, A_UINT8 configured); +void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps, + WMI_NEIGHBOR_INFO *info); +void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num); +void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status); +void ar6000_targetStats_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len); +void ar6000_rssiThreshold_event(struct ar6_softc *ar, + WMI_RSSI_THRESHOLD_VAL newThreshold, + A_INT16 rssi); +void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal); +void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication, + A_UINT8 statusCode, A_UINT8 *tspecSuggestion); +void ar6000_channel_change_event(struct ar6_softc *ar, A_UINT16 oldChannel, A_UINT16 newChannel); +void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source); +void +ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl); + +void +ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p); + +void +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, + WMI_GET_WOW_LIST_REPLY *wow_reply); + +void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, + WMI_PMKID *pmkidList, A_UINT8 *bssidList); + +void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values); +void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value); +void ar6000_gpio_ack_rx(void); + +A_INT32 rssi_compensation_calc_tcmd(A_UINT32 freq, A_INT32 rssi, A_UINT32 totalPkt); +A_INT16 rssi_compensation_calc(struct ar6_softc *ar, A_INT16 rssi); +A_INT16 rssi_compensation_reverse_calc(struct ar6_softc *ar, A_INT16 rssi, A_BOOL Above); + +void ar6000_dbglog_init_done(struct ar6_softc *ar); + +#ifdef SEND_EVENT_TO_APP +void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len); +void ar6000_send_generic_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len); +#endif + +#ifdef CONFIG_HOST_TCMD_SUPPORT +void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len); +#endif + +void ar6000_tx_retry_err_event(void *devt); + +void ar6000_snrThresholdEvent_rx(void *devt, + WMI_SNR_THRESHOLD_VAL newThreshold, + A_UINT8 snr); + +void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal); + + +void ar6000_ratemask_rx(void *devt, A_UINT32 ratemask); + +A_STATUS ar6000_get_driver_cfg(struct net_device *dev, + A_UINT16 cfgParam, + void *result); +void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len); + +void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped, + A_INT8 *buffer, A_UINT32 length); + +int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar); + +void ar6000_peer_event(void *devt, A_UINT8 eventCode, A_UINT8 *bssid); + +void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active); +HTC_ENDPOINT_ID ar6000_ac2_endpoint_id ( void * devt, A_UINT8 ac); +A_UINT8 ar6000_endpoint_id2_ac (void * devt, HTC_ENDPOINT_ID ep ); + +void ar6000_btcoex_config_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len); + +void ar6000_btcoex_stats_event(struct ar6_softc *ar, A_UINT8 *ptr, A_UINT32 len) ; + +void ar6000_dset_open_req(void *devt, + A_UINT32 id, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); +void ar6000_dset_close(void *devt, A_UINT32 access_cookie); +void ar6000_dset_data_req(void *devt, + A_UINT32 access_cookie, + A_UINT32 offset, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg); + + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +void prof_count_rx(unsigned int addr, unsigned int count); +#endif + +A_UINT32 ar6000_getnodeAge (void); + +A_UINT32 ar6000_getclkfreq (void); + +int ar6000_ap_mode_profile_commit(struct ar6_softc *ar); + +struct ieee80211req_wpaie; +A_STATUS +ar6000_ap_mode_get_wpa_ie(struct ar6_softc *ar, struct ieee80211req_wpaie *wpaie); + +A_STATUS is_iwioctl_allowed(A_UINT8 mode, A_UINT16 cmd); + +A_STATUS is_xioctl_allowed(A_UINT8 mode, int cmd); + +void ar6000_pspoll_event(struct ar6_softc *ar,A_UINT8 aid); + +void ar6000_dtimexpiry_event(struct ar6_softc *ar); + +void ar6000_aggr_rcv_addba_req_evt(struct ar6_softc *ar, WMI_ADDBA_REQ_EVENT *cmd); +void ar6000_aggr_rcv_addba_resp_evt(struct ar6_softc *ar, WMI_ADDBA_RESP_EVENT *cmd); +void ar6000_aggr_rcv_delba_req_evt(struct ar6_softc *ar, WMI_DELBA_EVENT *cmd); +void ar6000_hci_event_rcv_evt(struct ar6_softc *ar, WMI_HCI_EVENT *cmd); + +#ifdef WAPI_ENABLE +int ap_set_wapi_key(struct ar6_softc *ar, void *ik); +void ap_wapi_rekey_event(struct ar6_softc *ar, A_UINT8 type, A_UINT8 *mac); +#endif + +A_STATUS ar6000_connect_to_ap(struct ar6_softc *ar); +A_STATUS ar6000_set_wlan_state(struct ar6_softc *ar, AR6000_WLAN_STATE state); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h new file mode 100644 index 000000000000..e661741f3b9e --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/athdrv_linux.h @@ -0,0 +1,1202 @@ +/* + * Copyright (c) 2004-2009 Atheros Communications Inc. + * All rights reserved. + * + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef _ATHDRV_LINUX_H +#define _ATHDRV_LINUX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* + * There are two types of ioctl's here: Standard ioctls and + * eXtended ioctls. All extended ioctls (XIOCTL) are multiplexed + * off of the single ioctl command, AR6000_IOCTL_EXTENDED. The + * arguments for every XIOCTL starts with a 32-bit command word + * that is used to select which extended ioctl is in use. After + * the command word are command-specific arguments. + */ + +/* Linux standard Wireless Extensions, private ioctl interfaces */ +#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) +#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) +#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) +#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) +#define IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) +#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) +//#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+6) +//#define IEEE80211_IOCTL_SETWMMPARAMS (SIOCIWFIRSTPRIV+7) +//#define IEEE80211_IOCTL_GETWMMPARAMS (SIOCIWFIRSTPRIV+8) +//#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+9) +//#define IEEE80211_IOCTL_SETAUTHALG (SIOCIWFIRSTPRIV+10) +#define IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) + + + +/* ====WMI Ioctls==== */ +/* + * + * Many ioctls simply provide WMI services to application code: + * an application makes such an ioctl call with a set of arguments + * that are packaged into the corresponding WMI message, and sent + * to the Target. + */ + +#define AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) +/* + * arguments: + * ar6000_version *revision + */ + +#define AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) +/* + * arguments: + * WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h) + * uses: WMI_SET_POWER_MODE_CMDID + */ + +#define AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) +/* + * arguments: + * WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h) + * uses: WMI_SET_SCAN_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) +/* + * arguments: + * UINT32 listenInterval + * uses: WMI_SET_LISTEN_INT_CMDID + */ + +#define AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) +/* + * arguments: + * WMI_BSS_FILTER filter (see include/wmi.h) + * uses: WMI_SET_BSS_FILTER_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) +/* + * arguments: + * WMI_CHANNEL_PARAMS_CMD chParams + * uses: WMI_SET_CHANNEL_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) +/* + * arguments: + * WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h) + * uses: WMI_SETPROBED_SSID_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) +/* + * arguments: + * WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h) + * uses: WMI_SET_POWER_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) +/* + * arguments: + * WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h) + * uses: WMI_ADD_BAD_AP_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) +/* + * arguments: + * ar6000_queuereq queueRequest (see below) + */ + +#define AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) +/* + * arguments: + * WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h) + * uses: WMI_CREATE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) +/* + * arguments: + * WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h) + * uses: WMI_DELETE_PSTREAM_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) +/* + * arguments: + * WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24) +/* + * arguments: + * WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h) + * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID + */ + +#define AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) +/* + * arguments: + * TARGET_STATS *targetStats (see below) + * uses: WMI_GET_STATISTICS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) +/* + * arguments: + * WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd + * uses: WMI_SET_ASSOC_INFO_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) +/* + * arguments: + * WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h) + * uses: WMI_SET_ACCESS_PARAMS_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) +/* + * arguments: + * UINT32 beaconMissTime + * uses: WMI_SET_BMISS_TIME_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) +/* + * arguments: + * WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h) + * uses: WMI_SET_DISC_TIMEOUT_CMDID + */ + +#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30) +/* + * arguments: + * WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd + * uses: WMI_SET_IBSS_PM_CAPS_CMDID + */ + +/* + * There is a very small space available for driver-private + * wireless ioctls. In order to circumvent this limitation, + * we multiplex a bunch of ioctls (XIOCTLs) on top of a + * single AR6000_IOCTL_EXTENDED ioctl. + */ +#define AR6000_IOCTL_EXTENDED (SIOCIWFIRSTPRIV+31) + + +/* ====BMI Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_DONE 1 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_DONE) + * uses: BMI_DONE + */ + +#define AR6000_XIOCTL_BMI_READ_MEMORY 2 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY) + * UINT32 address + * UINT32 length + * } + * char results[length] + * } + * uses: BMI_READ_MEMORY + */ + +#define AR6000_XIOCTL_BMI_WRITE_MEMORY 3 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY) + * UINT32 address + * UINT32 length + * char data[length] + * uses: BMI_WRITE_MEMORY + */ + +#define AR6000_XIOCTL_BMI_EXECUTE 4 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE) + * UINT32 TargetAddress + * UINT32 parameter + * uses: BMI_EXECUTE + */ + +#define AR6000_XIOCTL_BMI_SET_APP_START 5 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START) + * UINT32 TargetAddress + * uses: BMI_SET_APP_START + */ + +#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * } + * UINT32 result + * } + * uses: BMI_READ_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER) + * UINT32 TargetAddress, 32-bit aligned + * UINT32 newValue + * } + * uses: BMI_WRITE_SOC_REGISTER + */ + +#define AR6000_XIOCTL_BMI_TEST 8 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_TEST) + * UINT32 address + * UINT32 length + * UINT32 count + */ + + + +/* Historical Host-side DataSet support */ +#define AR6000_XIOCTL_UNUSED9 9 +#define AR6000_XIOCTL_UNUSED10 10 +#define AR6000_XIOCTL_UNUSED11 11 + +/* ====Misc Extended Ioctls==== */ + +#define AR6000_XIOCTL_FORCE_TARGET_RESET 12 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET) + */ + + +#ifdef HTC_RAW_INTERFACE +/* HTC Raw Interface Ioctls */ +#define AR6000_XIOCTL_HTC_RAW_OPEN 13 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN) + */ + +#define AR6000_XIOCTL_HTC_RAW_CLOSE 14 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE) + */ + +#define AR6000_XIOCTL_HTC_RAW_READ 15 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ) + * UINT32 mailboxID + * UINT32 length + * } + * results[length] + * } + */ + +#define AR6000_XIOCTL_HTC_RAW_WRITE 16 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE) + * UINT32 mailboxID + * UINT32 length + * char buffer[length] + */ +#endif /* HTC_RAW_INTERFACE */ + +#define AR6000_XIOCTL_CHECK_TARGET_READY 17 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY) + */ + + + +/* ====GPIO (General Purpose I/O) Extended Ioctls==== */ + +#define AR6000_XIOCTL_GPIO_OUTPUT_SET 18 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET) + * ar6000_gpio_output_set_cmd_s (see below) + * uses: WMIX_GPIO_OUTPUT_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INPUT_GET 19 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET) + * uses: WMIX_GPIO_INPUT_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_SET 20 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_SET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_REGISTER_GET 21 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET) + * ar6000_gpio_register_cmd_s (see below) + * uses: WMIX_GPIO_REGISTER_GET_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_ACK 22 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK) + * ar6000_cpio_intr_ack_cmd_s (see below) + * uses: WMIX_GPIO_INTR_ACK_CMDID + */ + +#define AR6000_XIOCTL_GPIO_INTR_WAIT 23 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT) + */ + + + +/* ====more wireless commands==== */ + +#define AR6000_XIOCTL_SET_ADHOC_BSSID 24 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID) + * WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h) + */ + +#define AR6000_XIOCTL_SET_OPT_MODE 25 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE) + * WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h) + * uses: WMI_SET_OPT_MODE_CMDID + */ + +#define AR6000_XIOCTL_OPT_SEND_FRAME 26 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME) + * WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h) + * uses: WMI_OPT_TX_FRAME_CMDID + */ + +#define AR6000_XIOCTL_SET_BEACON_INTVAL 27 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_BEACON_INTVAL) + * WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h) + * uses: WMI_SET_BEACON_INT_CMDID + */ + + +#define IEEE80211_IOCTL_SETAUTHALG 28 + + +#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE) + * WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h) + * uses: WMI_SET_VOICE_PKT_SIZE_CMDID + */ + + +#define AR6000_XIOCTL_SET_MAX_SP 30 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP) + * WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h) + * uses: WMI_SET_MAX_SP_LEN_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 + +#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 + +#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 + + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS) + * WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h) + * WMI_SET_POWERSAVE_TIMERS_CMDID + */ + +#define AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE) + */ + +#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 +typedef enum { + WLAN_DISABLED, + WLAN_ENABLED +} AR6000_WLAN_STATE; +/* + * arguments: + * enable/disable + */ + +#define AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 + +#define AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 +/* + * arguments: + * WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd + * uses: WMI_SET_RETRY_LIMITS_CMDID + */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* ====extended commands for radio test ==== */ + +#define AR6000_XIOCTL_TCMD_CONT_TX 38 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX) + * WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_TX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_CONT_RX 39 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX) + * WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h) + * uses: WMI_TCMD_CONT_RX_CMDID + */ + +#define AR6000_XIOCTL_TCMD_PM 40 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TCMD_PM) + * WMI_TCMD_PM_CMD pmCmd (see include/wmi.h) + * uses: WMI_TCMD_PM_CMDID + */ + +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + +#define AR6000_XIOCTL_WMI_STARTSCAN 41 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN) + * UINT8 scanType + * UINT8 scanConnected + * A_BOOL forceFgScan + * uses: WMI_START_SCAN_CMDID + */ + +#define AR6000_XIOCTL_WMI_SETFIXRATES 42 + +#define AR6000_XIOCTL_WMI_GETFIXRATES 43 + + +#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 +/* + * arguments: + * WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_CLR_RSSISNR 45 +/* + * arguments: + * WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h) + * uses: WMI_CLR_RSSISNR_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 +/* + * arguments: + * WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h) + * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_RTS 47 +/* + * arguments: + * WMI_SET_RTS_MODE_CMD (see include/wmi.h) + * uses: WMI_SET_RTS_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 + +#define AR6000_XIOCTL_WMI_SET_AUTHMODE 49 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE) + * UINT8 mode + * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID + */ + +#define AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM) + * UINT8 mode + * uses: WMI_SET_WMM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_WMM 51 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS) + * UINT32 frequency + * UINT8 threshold + */ +#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP) + * UINT32 cookie + */ +#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 + +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD) + * UINT32 regDomain + */ +#define AR6000_XIOCTL_WMI_GET_RD 54 + +#define AR6000_XIOCTL_DIAG_READ 55 + +#define AR6000_XIOCTL_DIAG_WRITE 56 + +/* + * arguments cmd (AR6000_XIOCTL_SET_TXOP) + * WMI_TXOP_CFG txopEnable + */ +#define AR6000_XIOCTL_WMI_SET_TXOP 57 + +#ifdef USER_KEYS +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS) + * UINT32 keyOpCtrl + * uses AR6000_USER_SETKEYS_INFO + */ +#define AR6000_XIOCTL_USER_SETKEYS 58 +#endif /* USER_KEYS */ + +#define AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE) + * UINT8 keepaliveInterval + * uses: WMI_SET_KEEPALIVE_CMDID + */ + +#define AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 +/* + * arguments: + * UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE) + * UINT8 keepaliveInterval + * A_BOOL configured + * uses: WMI_GET_KEEPALIVE_CMDID + */ + +/* ====ROM Patching Extended Ioctls==== */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 +/* + * arguments: + * union { + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL) + * UINT32 ROM Address + * UINT32 RAM Address + * UINT32 number of bytes + * UINT32 activate? (0 or 1) + * } + * A_UINT32 resulting rompatch ID + * } + * uses: BMI_ROMPATCH_INSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL) + * UINT32 rompatch ID + * } + * uses: BMI_ROMPATCH_UNINSTALL + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_ACTIVATE + */ + +#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE) + * UINT32 rompatch count + * UINT32 rompatch IDs[rompatch count] + * } + * uses: BMI_ROMPATCH_DEACTIVATE + */ + +#define AR6000_XIOCTL_WMI_SET_APPIE 65 +/* + * arguments: + * struct { + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE) + * UINT32 app_frmtype; + * UINT32 app_buflen; + * UINT8 app_buf[]; + * } + */ +#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 +/* + * arguments: + * A_UINT32 filter_type; + */ + +#define AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 + +#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 + +#define AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 +/* + * arguments: + * A_UINT32 wsc_status; + * (WSC_REG_INACTIVE or WSC_REG_ACTIVE) + */ + +/* + * arguments: + * struct { + * A_UINT8 streamType; + * A_UINT8 status; + * } + * uses: WMI_SET_BT_STATUS_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_STATUS 71 + +/* + * arguments: + * struct { + * A_UINT8 paramType; + * union { + * A_UINT8 noSCOPkts; + * BT_PARAMS_A2DP a2dpParams; + * BT_COEX_REGS regs; + * }; + * } + * uses: WMI_SET_BT_PARAM_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 + +#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 +#define AR6000_XIOCTL_WMI_SET_WOW_MODE 74 +#define AR6000_XIOCTL_WMI_GET_WOW_LIST 75 +#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 +#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 + + + +#define AR6000_XIOCTL_TARGET_INFO 78 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_TARGET_INFO) + * A_UINT32 TargetVersion (returned) + * A_UINT32 TargetType (returned) + * (See also bmi_msg.h target_ver and target_type) + */ + +#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 +/* + * arguments: + * none + */ + +#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 +/* + * This ioctl is used to emulate traffic activity + * timeouts. Activity/inactivity will trigger the driver + * to re-balance credits. + * + * arguments: + * ar6000_traffic_activity_change + */ + +#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 +/* + * This ioctl is used to set the connect control flags + * + * arguments: + * A_UINT32 connectCtrlFlags + */ + +#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 +/* + * This IOCTL sets any Authentication,Key Management and Protection + * related parameters. This is used along with the information set in + * Connect Command. + * Currently this enables Multiple PMKIDs to an AP. + * + * arguments: + * struct { + * A_UINT32 akmpInfo; + * } + * uses: WMI_SET_AKMP_PARAMS_CMD + */ + +#define AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 + +#define AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 +/* + * This IOCTL is used to set a list of PMKIDs. This list of + * PMKIDs is used in the [Re]AssocReq Frame. This list is used + * only if the MultiPMKID option is enabled via the + * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS IOCTL. + * + * arguments: + * struct { + * A_UINT32 numPMKID; + * WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE]; + * } + * uses: WMI_SET_PMKIDLIST_CMD + */ + +#define AR6000_XIOCTL_WMI_SET_PARAMS 85 +#define AR6000_XIOCTL_WMI_SET_MCAST_FILTER 86 +#define AR6000_XIOCTL_WMI_DEL_MCAST_FILTER 87 + + +/* Historical DSETPATCH support for INI patches */ +#define AR6000_XIOCTL_UNUSED90 90 + + +/* Support LZ-compressed firmware download */ +#define AR6000_XIOCTL_BMI_LZ_STREAM_START 91 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_STREAM_START) + * UINT32 address + * uses: BMI_LZ_STREAM_START + */ + +#define AR6000_XIOCTL_BMI_LZ_DATA 92 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_BMI_LZ_DATA) + * UINT32 length + * char data[length] + * uses: BMI_LZ_DATA + */ + +#define AR6000_XIOCTL_PROF_CFG 93 +/* + * arguments: + * A_UINT32 period + * A_UINT32 nbins + */ + +#define AR6000_XIOCTL_PROF_ADDR_SET 94 +/* + * arguments: + * A_UINT32 Target address + */ + +#define AR6000_XIOCTL_PROF_START 95 + +#define AR6000_XIOCTL_PROF_STOP 96 + +#define AR6000_XIOCTL_PROF_COUNT_GET 97 + +#define AR6000_XIOCTL_WMI_ABORT_SCAN 98 + +/* + * AP mode + */ +#define AR6000_XIOCTL_AP_GET_STA_LIST 99 + +#define AR6000_XIOCTL_AP_HIDDEN_SSID 100 + +#define AR6000_XIOCTL_AP_SET_NUM_STA 101 + +#define AR6000_XIOCTL_AP_SET_ACL_MAC 102 + +#define AR6000_XIOCTL_AP_GET_ACL_LIST 103 + +#define AR6000_XIOCTL_AP_COMMIT_CONFIG 104 + +#define IEEE80211_IOCTL_GETWPAIE 105 + +#define AR6000_XIOCTL_AP_CONN_INACT_TIME 106 + +#define AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 + +#define AR6000_XIOCTL_AP_SET_COUNTRY 108 + +#define AR6000_XIOCTL_AP_SET_DTIM 109 + + + + +#define AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 + +#define AR6000_XIOCTL_SET_IP 111 + +#define AR6000_XIOCTL_AP_SET_ACL_POLICY 112 + +#define AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 + +#define AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO 114 + +#define AR6000_XIOCTL_MODULE_DEBUG_SET_MASK 115 + +#define AR6000_XIOCTL_MODULE_DEBUG_GET_MASK 116 + +#define AR6000_XIOCTL_DUMP_RCV_AGGR_STATS 117 + +#define AR6000_XIOCTL_SET_HT_CAP 118 + +#define AR6000_XIOCTL_SET_HT_OP 119 + +#define AR6000_XIOCTL_AP_GET_STAT 120 + +#define AR6000_XIOCTL_SET_TX_SELECT_RATES 121 + +#define AR6000_XIOCTL_SETUP_AGGR 122 + +#define AR6000_XIOCTL_ALLOW_AGGR 123 + +#define AR6000_XIOCTL_AP_GET_HIDDEN_SSID 124 + +#define AR6000_XIOCTL_AP_GET_COUNTRY 125 + +#define AR6000_XIOCTL_AP_GET_WMODE 126 + +#define AR6000_XIOCTL_AP_GET_DTIM 127 + +#define AR6000_XIOCTL_AP_GET_BINTVL 128 + +#define AR6000_XIOCTL_AP_GET_RTS 129 + +#define AR6000_XIOCTL_DELE_AGGR 130 + +#define AR6000_XIOCTL_FETCH_TARGET_REGS 131 + +#define AR6000_XIOCTL_HCI_CMD 132 + +#define AR6000_XIOCTL_ACL_DATA 133 + +#define AR6000_XIOCTL_WLAN_CONN_PRECEDENCE 134 + +#define AR6000_XIOCTL_AP_SET_11BG_RATESET 135 + +#define AR6000_XIOCTL_WMI_SET_AP_PS 136 + +#define AR6000_XIOCTL_WMI_MCAST_FILTER 137 + +#define AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT 138 + +#define AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV 139 + +#define AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG 140 + +#define AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG 141 + +#define AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG 142 + +#define AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG 143 + +#define AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG 144 + +#define AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS 145 + +#define AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG 146 + +#define AR6000_XIOCTL_WMI_GET_BTCOEX_STATS 147 +/* + * arguments: + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_QOS_SUPP) + * UINT8 mode + * uses: WMI_SET_QOS_SUPP_CMDID + */ +#define AR6000_XIOCTL_WMI_SET_QOS_SUPP 148 + + +/* + * arguments: + * WMI_AP_PS_CMD apPsCmd + * uses: WMI_AP_PS_CMDID + */ + +/* used by AR6000_IOCTL_WMI_GETREV */ +struct ar6000_version { + A_UINT32 host_ver; + A_UINT32 target_ver; + A_UINT32 wlan_ver; +}; + +/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */ +struct ar6000_queuereq { + A_UINT8 trafficClass; + A_UINT16 activeTsids; +}; + +/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */ +typedef struct targetStats_t { + A_UINT64 tx_packets; + A_UINT64 tx_bytes; + A_UINT64 tx_unicast_pkts; + A_UINT64 tx_unicast_bytes; + A_UINT64 tx_multicast_pkts; + A_UINT64 tx_multicast_bytes; + A_UINT64 tx_broadcast_pkts; + A_UINT64 tx_broadcast_bytes; + A_UINT64 tx_rts_success_cnt; + A_UINT64 tx_packet_per_ac[4]; + + A_UINT64 tx_errors; + A_UINT64 tx_failed_cnt; + A_UINT64 tx_retry_cnt; + A_UINT64 tx_mult_retry_cnt; + A_UINT64 tx_rts_fail_cnt; + + A_UINT64 rx_packets; + A_UINT64 rx_bytes; + A_UINT64 rx_unicast_pkts; + A_UINT64 rx_unicast_bytes; + A_UINT64 rx_multicast_pkts; + A_UINT64 rx_multicast_bytes; + A_UINT64 rx_broadcast_pkts; + A_UINT64 rx_broadcast_bytes; + A_UINT64 rx_fragment_pkt; + + A_UINT64 rx_errors; + A_UINT64 rx_crcerr; + A_UINT64 rx_key_cache_miss; + A_UINT64 rx_decrypt_err; + A_UINT64 rx_duplicate_frames; + + A_UINT64 tkip_local_mic_failure; + A_UINT64 tkip_counter_measures_invoked; + A_UINT64 tkip_replays; + A_UINT64 tkip_format_errors; + A_UINT64 ccmp_format_errors; + A_UINT64 ccmp_replays; + + A_UINT64 power_save_failure_cnt; + + A_UINT64 cs_bmiss_cnt; + A_UINT64 cs_lowRssi_cnt; + A_UINT64 cs_connect_cnt; + A_UINT64 cs_disconnect_cnt; + + A_INT32 tx_unicast_rate; + A_INT32 rx_unicast_rate; + + A_UINT32 lq_val; + + A_UINT32 wow_num_pkts_dropped; + A_UINT16 wow_num_events_discarded; + + A_INT16 noise_floor_calibation; + A_INT16 cs_rssi; + A_INT16 cs_aveBeacon_rssi; + A_UINT8 cs_aveBeacon_snr; + A_UINT8 cs_lastRoam_msec; + A_UINT8 cs_snr; + + A_UINT8 wow_num_host_pkt_wakeups; + A_UINT8 wow_num_host_event_wakeups; + + A_UINT32 arp_received; + A_UINT32 arp_matched; + A_UINT32 arp_replied; +}TARGET_STATS; + +typedef struct targetStats_cmd_t { + TARGET_STATS targetStats; + int clearStats; +} TARGET_STATS_CMD; + +/* used by AR6000_XIOCTL_USER_SETKEYS */ + +/* + * Setting this bit to 1 doesnot initialize the RSC on the firmware + */ +#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL 1 +#define AR6000_USER_SETKEYS_RSC_UNCHANGED 0x00000002 + +typedef struct { + A_UINT32 keyOpCtrl; /* Bit Map of Key Mgmt Ctrl Flags */ +} AR6000_USER_SETKEYS_INFO; + + +/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */ +struct ar6000_gpio_output_set_cmd_s { + A_UINT32 set_mask; + A_UINT32 clear_mask; + A_UINT32 enable_mask; + A_UINT32 disable_mask; +}; + +/* + * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET + */ +struct ar6000_gpio_register_cmd_s { + A_UINT32 gpioreg_id; + A_UINT32 value; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_ACK */ +struct ar6000_gpio_intr_ack_cmd_s { + A_UINT32 ack_mask; +}; + +/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */ +struct ar6000_gpio_intr_wait_cmd_s { + A_UINT32 intr_mask; + A_UINT32 input_values; +}; + +/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */ +typedef struct ar6000_dbglog_module_config_s { + A_UINT32 valid; + A_UINT16 mmask; + A_UINT16 tsr; + A_BOOL rep; + A_UINT16 size; +} DBGLOG_MODULE_CONFIG; + +typedef struct user_rssi_thold_t { + A_INT16 tag; + A_INT16 rssi; +} USER_RSSI_THOLD; + +typedef struct user_rssi_params_t { + A_UINT8 weight; + A_UINT32 pollTime; + USER_RSSI_THOLD tholds[12]; +} USER_RSSI_PARAMS; + +typedef struct ar6000_get_btcoex_config_cmd_t{ + A_UINT32 btProfileType; + A_UINT32 linkId; + }AR6000_GET_BTCOEX_CONFIG_CMD; + +typedef struct ar6000_btcoex_config_t { + AR6000_GET_BTCOEX_CONFIG_CMD configCmd; + A_UINT32 * configEvent; +} AR6000_BTCOEX_CONFIG; + +typedef struct ar6000_btcoex_stats_t { + A_UINT32 * statsEvent; + }AR6000_BTCOEX_STATS; +/* + * Host driver may have some config parameters. Typically, these + * config params are one time config parameters. These could + * correspond to any of the underlying modules. Host driver exposes + * an api for the underlying modules to get this config. + */ +#define AR6000_DRIVER_CFG_BASE 0x8000 + +/* Should driver perform wlan node caching? */ +#define AR6000_DRIVER_CFG_GET_WLANNODECACHING 0x8001 +/*Should we log raw WMI msgs */ +#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS 0x8002 + +/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */ +struct ar6000_diag_window_cmd_s { + unsigned int addr; + unsigned int value; +}; + + +struct ar6000_traffic_activity_change { + A_UINT32 StreamID; /* stream ID to indicate activity change */ + A_UINT32 Active; /* active (1) or inactive (0) */ +}; + +/* Used with AR6000_XIOCTL_PROF_COUNT_GET */ +struct prof_count_s { + A_UINT32 addr; /* bin start address */ + A_UINT32 count; /* hit count */ +}; + + +/* used by AR6000_XIOCTL_MODULE_DEBUG_SET_MASK */ +/* AR6000_XIOCTL_MODULE_DEBUG_GET_MASK */ +/* AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO */ +struct drv_debug_module_s { + A_CHAR modulename[128]; /* name of module */ + A_UINT32 mask; /* new mask to set .. or .. current mask */ +}; + + +/* All HCI related rx events are sent up to the host app + * via a wmi event id. It can contain ACL data or HCI event, + * based on which it will be de-multiplexed. + */ +typedef enum { + PAL_HCI_EVENT = 0, + PAL_HCI_RX_DATA, +} WMI_PAL_EVENT_INFO; + + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h new file mode 100644 index 000000000000..a2bd9e953cd2 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/athtypes_linux.h @@ -0,0 +1,47 @@ +/* + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef _ATHTYPES_LINUX_H_ +#define _ATHTYPES_LINUX_H_ + +#ifdef __KERNEL__ +#include +#else +#include +#endif + +typedef int8_t A_INT8; +typedef int16_t A_INT16; +typedef int32_t A_INT32; +typedef int64_t A_INT64; + +typedef u_int8_t A_UINT8; +typedef u_int16_t A_UINT16; +typedef u_int32_t A_UINT32; +typedef u_int64_t A_UINT64; + +typedef int A_BOOL; +typedef char A_CHAR; +typedef unsigned char A_UCHAR; +typedef unsigned long A_ATH_TIMER; + + +#endif /* _ATHTYPES_LINUX_H_ */ diff --git a/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h b/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h new file mode 100644 index 000000000000..2fac60b8a589 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/cfg80211.h @@ -0,0 +1,46 @@ +/* + * + * Copyright (c) 2004-2010 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef _AR6K_CFG80211_H_ +#define _AR6K_CFG80211_H_ + +struct wireless_dev *ar6k_cfg80211_init(struct device *dev); +void ar6k_cfg80211_deinit(AR_SOFTC_T *ar); + +void ar6k_cfg80211_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status); + +void ar6k_cfg80211_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, + A_UINT8 *bssid, A_UINT16 listenInterval, + A_UINT16 beaconInterval,NETWORK_TYPE networkType, + A_UINT8 beaconIeLen, A_UINT8 assocReqLen, + A_UINT8 assocRespLen, A_UINT8 *assocInfo); + +void ar6k_cfg80211_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, + A_UINT8 *bssid, A_UINT8 assocRespLen, + A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus); + +void ar6k_cfg80211_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast); + +#endif /* _AR6K_CFG80211_H_ */ + + + + + + diff --git a/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h new file mode 100644 index 000000000000..78b95bf7faa4 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/config_linux.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef _CONFIG_LINUX_H_ +#define _CONFIG_LINUX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* + * Host-side GPIO support is optional. + * If run-time access to GPIO pins is not required, then + * this should be changed to #undef. + */ +#define CONFIG_HOST_GPIO_SUPPORT + +/* + * Host side Test Command support + */ +#define CONFIG_HOST_TCMD_SUPPORT + +#define USE_4BYTE_REGISTER_ACCESS + +/* Host-side support for Target-side profiling */ +#undef CONFIG_TARGET_PROFILE_SUPPORT + +/* IP/TCP checksum offload */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25) +#define CONFIG_CHECKSUM_OFFLOAD +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h new file mode 100644 index 000000000000..6ef4cb6953d9 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/debug_linux.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef _DEBUG_LINUX_H_ +#define _DEBUG_LINUX_H_ + + /* macro to remove parens */ +#define ATH_PRINTX_ARG(arg...) arg + +#ifdef DEBUG + /* NOTE: the AR_DEBUG_PRINTF macro is defined here to handle special handling of variable arg macros + * which may be compiler dependent. */ +#define AR_DEBUG_PRINTF(mask, args) do { \ + if (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (mask)) { \ + A_PRINTF(ATH_PRINTX_ARG args); \ + } \ +} while (0) +#else + /* on non-debug builds, keep in error and warning messages in the driver, all other + * message tracing will get compiled out */ +#define AR_DEBUG_PRINTF(mask, args) \ + if ((mask) & (ATH_DEBUG_ERR | ATH_DEBUG_WARN)) { A_PRINTF(ATH_PRINTX_ARG args); } + +#endif + + /* compile specific macro to get the function name string */ +#define _A_FUNCNAME_ __func__ + + +#endif /* _DEBUG_LINUX_H_ */ diff --git a/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h b/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h new file mode 100644 index 000000000000..b3d51b44906a --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/export_hci_transport.h @@ -0,0 +1,70 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2009 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// HCI bridge implementation +// +// Author(s): ="Atheros" +//============================================================================== + +#include "hci_transport_api.h" +#include "common_drv.h" + +extern HCI_TRANSPORT_HANDLE (*_HCI_TransportAttach)(void *HTCHandle, HCI_TRANSPORT_CONFIG_INFO *pInfo); +extern void (*_HCI_TransportDetach)(HCI_TRANSPORT_HANDLE HciTrans); +extern A_STATUS (*_HCI_TransportAddReceivePkts)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET_QUEUE *pQueue); +extern A_STATUS (*_HCI_TransportSendPkt)(HCI_TRANSPORT_HANDLE HciTrans, HTC_PACKET *pPacket, A_BOOL Synchronous); +extern void (*_HCI_TransportStop)(HCI_TRANSPORT_HANDLE HciTrans); +extern A_STATUS (*_HCI_TransportStart)(HCI_TRANSPORT_HANDLE HciTrans); +extern A_STATUS (*_HCI_TransportEnableDisableAsyncRecv)(HCI_TRANSPORT_HANDLE HciTrans, A_BOOL Enable); +extern A_STATUS (*_HCI_TransportRecvHCIEventSync)(HCI_TRANSPORT_HANDLE HciTrans, + HTC_PACKET *pPacket, + int MaxPollMS); +extern A_STATUS (*_HCI_TransportSetBaudRate)(HCI_TRANSPORT_HANDLE HciTrans, A_UINT32 Baud); + + +#define HCI_TransportAttach(HTCHandle, pInfo) \ + _HCI_TransportAttach((HTCHandle), (pInfo)) +#define HCI_TransportDetach(HciTrans) \ + _HCI_TransportDetach(HciTrans) +#define HCI_TransportAddReceivePkts(HciTrans, pQueue) \ + _HCI_TransportAddReceivePkts((HciTrans), (pQueue)) +#define HCI_TransportSendPkt(HciTrans, pPacket, Synchronous) \ + _HCI_TransportSendPkt((HciTrans), (pPacket), (Synchronous)) +#define HCI_TransportStop(HciTrans) \ + _HCI_TransportStop((HciTrans)) +#define HCI_TransportStart(HciTrans) \ + _HCI_TransportStart((HciTrans)) +#define HCI_TransportEnableDisableAsyncRecv(HciTrans, Enable) \ + _HCI_TransportEnableDisableAsyncRecv((HciTrans), (Enable)) +#define HCI_TransportRecvHCIEventSync(HciTrans, pPacket, MaxPollMS) \ + _HCI_TransportRecvHCIEventSync((HciTrans), (pPacket), (MaxPollMS)) +#define HCI_TransportSetBaudRate(HciTrans, Baud) \ + _HCI_TransportSetBaudRate((HciTrans), (Baud)) + + +extern A_STATUS ar6000_register_hci_transport(HCI_TRANSPORT_CALLBACKS *hciTransCallbacks); + +extern A_STATUS ar6000_get_hif_dev(HIF_DEVICE *device, void *config); + +extern A_STATUS ar6000_set_uart_config(HIF_DEVICE *hifDevice, A_UINT32 scale, A_UINT32 step); + +/* get core clock register settings + * data: 0 - 40/44MHz + * 1 - 80/88MHz + * where (5G band/2.4G band) + * assume 2.4G band for now + */ +extern A_STATUS ar6000_get_core_clock_config(HIF_DEVICE *hifDevice, A_UINT32 *data); diff --git a/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h b/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h new file mode 100644 index 000000000000..29c68886d92e --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/ieee80211_ioctl.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2004-2005 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef _IEEE80211_IOCTL_H_ +#define _IEEE80211_IOCTL_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Extracted from the MADWIFI net80211/ieee80211_ioctl.h + */ + +/* + * WPA/RSN get/set key request. Specify the key/cipher + * type and whether the key is to be used for sending and/or + * receiving. The key index should be set only when working + * with global keys (use IEEE80211_KEYIX_NONE for ``no index''). + * Otherwise a unicast/pairwise key is specified by the bssid + * (on a station) or mac address (on an ap). They key length + * must include any MIC key data; otherwise it should be no + more than IEEE80211_KEYBUF_SIZE. + */ +struct ieee80211req_key { + u_int8_t ik_type; /* key/cipher type */ + u_int8_t ik_pad; + u_int16_t ik_keyix; /* key index */ + u_int8_t ik_keylen; /* key length in bytes */ + u_int8_t ik_flags; +#define IEEE80211_KEY_XMIT 0x01 +#define IEEE80211_KEY_RECV 0x02 +#define IEEE80211_KEY_DEFAULT 0x80 /* default xmit key */ + u_int8_t ik_macaddr[IEEE80211_ADDR_LEN]; + u_int64_t ik_keyrsc; /* key receive sequence counter */ + u_int64_t ik_keytsc; /* key transmit sequence counter */ + u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE]; +}; +/* + * Delete a key either by index or address. Set the index + * to IEEE80211_KEYIX_NONE when deleting a unicast key. + */ +struct ieee80211req_del_key { + u_int8_t idk_keyix; /* key index */ + u_int8_t idk_macaddr[IEEE80211_ADDR_LEN]; +}; +/* + * MLME state manipulation request. IEEE80211_MLME_ASSOC + * only makes sense when operating as a station. The other + * requests can be used when operating as a station or an + * ap (to effect a station). + */ +struct ieee80211req_mlme { + u_int8_t im_op; /* operation to perform */ +#define IEEE80211_MLME_ASSOC 1 /* associate station */ +#define IEEE80211_MLME_DISASSOC 2 /* disassociate station */ +#define IEEE80211_MLME_DEAUTH 3 /* deauthenticate station */ +#define IEEE80211_MLME_AUTHORIZE 4 /* authorize station */ +#define IEEE80211_MLME_UNAUTHORIZE 5 /* unauthorize station */ + u_int16_t im_reason; /* 802.11 reason code */ + u_int8_t im_macaddr[IEEE80211_ADDR_LEN]; +}; + +struct ieee80211req_addpmkid { + u_int8_t pi_bssid[IEEE80211_ADDR_LEN]; + u_int8_t pi_enable; + u_int8_t pi_pmkid[16]; +}; + +#define AUTH_ALG_OPEN_SYSTEM 0x01 +#define AUTH_ALG_SHARED_KEY 0x02 +#define AUTH_ALG_LEAP 0x04 + +struct ieee80211req_authalg { + u_int8_t auth_alg; +}; + +/* + * Request to add an IE to a Management Frame + */ +enum{ + IEEE80211_APPIE_FRAME_BEACON = 0, + IEEE80211_APPIE_FRAME_PROBE_REQ = 1, + IEEE80211_APPIE_FRAME_PROBE_RESP = 2, + IEEE80211_APPIE_FRAME_ASSOC_REQ = 3, + IEEE80211_APPIE_FRAME_ASSOC_RESP = 4, + IEEE80211_APPIE_NUM_OF_FRAME = 5 +}; + +/* + * The Maximum length of the IE that can be added to a Management frame + */ +#define IEEE80211_APPIE_FRAME_MAX_LEN 200 + +struct ieee80211req_getset_appiebuf { + u_int32_t app_frmtype; /* management frame type for which buffer is added */ + u_int32_t app_buflen; /*application supplied buffer length */ + u_int8_t app_buf[]; +}; + +/* + * The following definitions are used by an application to set filter + * for receiving management frames + */ +enum { + IEEE80211_FILTER_TYPE_BEACON = 0x1, + IEEE80211_FILTER_TYPE_PROBE_REQ = 0x2, + IEEE80211_FILTER_TYPE_PROBE_RESP = 0x4, + IEEE80211_FILTER_TYPE_ASSOC_REQ = 0x8, + IEEE80211_FILTER_TYPE_ASSOC_RESP = 0x10, + IEEE80211_FILTER_TYPE_AUTH = 0x20, + IEEE80211_FILTER_TYPE_DEAUTH = 0x40, + IEEE80211_FILTER_TYPE_DISASSOC = 0x80, + IEEE80211_FILTER_TYPE_ALL = 0xFF /* used to check the valid filter bits */ +}; + +struct ieee80211req_set_filter { + u_int32_t app_filterype; /* management frame filter type */ +}; + +enum { + IEEE80211_PARAM_AUTHMODE = 3, /* Authentication Mode */ + IEEE80211_PARAM_MCASTCIPHER = 5, + IEEE80211_PARAM_MCASTKEYLEN = 6, /* multicast key length */ + IEEE80211_PARAM_UCASTCIPHER = 8, + IEEE80211_PARAM_UCASTKEYLEN = 9, /* unicast key length */ + IEEE80211_PARAM_WPA = 10, /* WPA mode (0,1,2) */ + IEEE80211_PARAM_ROAMING = 12, /* roaming mode */ + IEEE80211_PARAM_PRIVACY = 13, /* privacy invoked */ + IEEE80211_PARAM_COUNTERMEASURES = 14, /* WPA/TKIP countermeasures */ + IEEE80211_PARAM_DROPUNENCRYPTED = 15, /* discard unencrypted frames */ + IEEE80211_PARAM_WAPI = 16, /* WAPI policy from wapid */ +}; + +/* + * Values for IEEE80211_PARAM_WPA + */ +#define WPA_MODE_WPA1 1 +#define WPA_MODE_WPA2 2 +#define WPA_MODE_AUTO 3 +#define WPA_MODE_NONE 4 + +struct ieee80211req_wpaie { + u_int8_t wpa_macaddr[IEEE80211_ADDR_LEN]; + u_int8_t wpa_ie[IEEE80211_MAX_IE]; + u_int8_t rsn_ie[IEEE80211_MAX_IE]; +}; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) +#define IW_ENCODE_ALG_PMK 4 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _IEEE80211_IOCTL_H_ */ diff --git a/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h new file mode 100644 index 000000000000..23d81c2bc3da --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/osapi_linux.h @@ -0,0 +1,361 @@ +/* + * This file contains the definitions of the basic atheros data types. + * It is used to map the data types in atheros files to a platform specific + * type. + * + * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef _OSAPI_LINUX_H_ +#define _OSAPI_LINUX_H_ + +#ifdef __KERNEL__ + +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#include +#endif +#include +#include +#include +#ifdef KERNEL_2_4 +#include +#include +#endif + +#include + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +/* + * Endianes macros + */ +#define A_BE2CPU8(x) ntohb(x) +#define A_BE2CPU16(x) ntohs(x) +#define A_BE2CPU32(x) ntohl(x) + +#define A_LE2CPU8(x) (x) +#define A_LE2CPU16(x) (x) +#define A_LE2CPU32(x) (x) + +#define A_CPU2BE8(x) htonb(x) +#define A_CPU2BE16(x) htons(x) +#define A_CPU2BE32(x) htonl(x) + +#define A_MEMCPY(dst, src, len) memcpy((A_UINT8 *)(dst), (src), (len)) +#define A_MEMZERO(addr, len) memset(addr, 0, len) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) kmalloc((size), GFP_KERNEL) +#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC) +#define A_FREE(addr) kfree(addr) +#define A_PRINTF(args...) printk(KERN_ALERT args) +#define A_PRINTF_LOG(args...) printk(args) +#define A_SPRINTF(buf, args...) sprintf (buf, args) + +/* Mutual Exclusion */ +typedef spinlock_t A_MUTEX_T; +#define A_MUTEX_INIT(mutex) spin_lock_init(mutex) +#define A_MUTEX_LOCK(mutex) spin_lock_bh(mutex) +#define A_MUTEX_UNLOCK(mutex) spin_unlock_bh(mutex) +#define A_IS_MUTEX_VALID(mutex) TRUE /* okay to return true, since A_MUTEX_DELETE does nothing */ +#define A_MUTEX_DELETE(mutex) /* spin locks are not kernel resources so nothing to free.. */ + +/* Get current time in ms adding a constant offset (in ms) */ +#define A_GET_MS(offset) \ + (jiffies + ((offset) / 1000) * HZ) + +/* + * Timer Functions + */ +#define A_MDELAY(msecs) mdelay(msecs) +typedef struct timer_list A_TIMER; + +#define A_INIT_TIMER(pTimer, pFunction, pArg) do { \ + init_timer(pTimer); \ + (pTimer)->function = (pFunction); \ + (pTimer)->data = (unsigned long)(pArg); \ +} while (0) + +/* + * Start a Timer that elapses after 'periodMSec' milli-seconds + * Support is provided for a one-shot timer. The 'repeatFlag' is + * ignored. + */ +#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do { \ + if (repeatFlag) { \ + printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__); \ + panic("Timer Repeat"); \ + } \ + mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000); \ +} while (0) + +/* + * Cancel the Timer. + */ +#define A_UNTIMEOUT(pTimer) do { \ + del_timer((pTimer)); \ +} while (0) + +#define A_DELETE_TIMER(pTimer) do { \ +} while (0) + +/* + * Wait Queue related functions + */ +typedef wait_queue_head_t A_WAITQUEUE_HEAD; +#define A_INIT_WAITQUEUE_HEAD(head) init_waitqueue_head(head) +#ifndef wait_event_interruptible_timeout +#define __wait_event_interruptible_timeout(wq, condition, ret) \ +do { \ + wait_queue_t __wait; \ + init_waitqueue_entry(&__wait, current); \ + \ + add_wait_queue(&wq, &__wait); \ + for (;;) { \ + set_current_state(TASK_INTERRUPTIBLE); \ + if (condition) \ + break; \ + if (!signal_pending(current)) { \ + ret = schedule_timeout(ret); \ + if (!ret) \ + break; \ + continue; \ + } \ + ret = -ERESTARTSYS; \ + break; \ + } \ + current->state = TASK_RUNNING; \ + remove_wait_queue(&wq, &__wait); \ +} while (0) + +#define wait_event_interruptible_timeout(wq, condition, timeout) \ +({ \ + long __ret = timeout; \ + if (!(condition)) \ + __wait_event_interruptible_timeout(wq, condition, __ret); \ + __ret; \ +}) +#endif /* wait_event_interruptible_timeout */ + +#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \ + wait_event_interruptible_timeout(head, condition, timeout); \ +} while (0) + +#define A_WAKE_UP(head) wake_up(head) + +#ifdef DEBUG +extern unsigned int panic_on_assert; +#define A_ASSERT(expr) \ + if (!(expr)) { \ + printk(KERN_ALERT"Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#expr); \ + if (panic_on_assert) panic(#expr); \ + } +#else +#define A_ASSERT(expr) +#endif /* DEBUG */ + +#ifdef ANDROID_ENV +struct firmware; +int android_request_firmware(const struct firmware **firmware_p, const char *filename, + struct device *device); +void android_release_firmware(const struct firmware *firmware); +#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) android_request_firmware(_ppf, _pfile, _dev) +#define A_RELEASE_FIRMWARE(_pf) android_release_firmware(_pf) +#else +#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) request_firmware(_ppf, _pfile, _dev) +#define A_RELEASE_FIRMWARE(_pf) release_firmware(_pf) +#endif + +/* + * Initialization of the network buffer subsystem + */ +#define A_NETBUF_INIT() + +/* + * Network buffer queue support + */ +typedef struct sk_buff_head A_NETBUF_QUEUE_T; + +#define A_NETBUF_QUEUE_INIT(q) \ + a_netbuf_queue_init(q) + +#define A_NETBUF_ENQUEUE(q, pkt) \ + a_netbuf_enqueue((q), (pkt)) +#define A_NETBUF_PREQUEUE(q, pkt) \ + a_netbuf_prequeue((q), (pkt)) +#define A_NETBUF_DEQUEUE(q) \ + (a_netbuf_dequeue(q)) +#define A_NETBUF_QUEUE_SIZE(q) \ + a_netbuf_queue_size(q) +#define A_NETBUF_QUEUE_EMPTY(q) \ + a_netbuf_queue_empty(q) + +/* + * Network buffer support + */ +#define A_NETBUF_ALLOC(size) \ + a_netbuf_alloc(size) +#define A_NETBUF_ALLOC_RAW(size) \ + a_netbuf_alloc_raw(size) +#define A_NETBUF_FREE(bufPtr) \ + a_netbuf_free(bufPtr) +#define A_NETBUF_DATA(bufPtr) \ + a_netbuf_to_data(bufPtr) +#define A_NETBUF_LEN(bufPtr) \ + a_netbuf_to_len(bufPtr) +#define A_NETBUF_PUSH(bufPtr, len) \ + a_netbuf_push(bufPtr, len) +#define A_NETBUF_PUT(bufPtr, len) \ + a_netbuf_put(bufPtr, len) +#define A_NETBUF_TRIM(bufPtr,len) \ + a_netbuf_trim(bufPtr, len) +#define A_NETBUF_PULL(bufPtr, len) \ + a_netbuf_pull(bufPtr, len) +#define A_NETBUF_HEADROOM(bufPtr)\ + a_netbuf_headroom(bufPtr) +#define A_NETBUF_SETLEN(bufPtr,len) \ + a_netbuf_setlen(bufPtr, len) + +/* Add data to end of a buffer */ +#define A_NETBUF_PUT_DATA(bufPtr, srcPtr, len) \ + a_netbuf_put_data(bufPtr, srcPtr, len) + +/* Add data to start of the buffer */ +#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr, len) \ + a_netbuf_push_data(bufPtr, srcPtr, len) + +/* Remove data at start of the buffer */ +#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \ + a_netbuf_pull_data(bufPtr, dstPtr, len) + +/* Remove data from the end of the buffer */ +#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \ + a_netbuf_trim_data(bufPtr, dstPtr, len) + +/* View data as "size" contiguous bytes of type "t" */ +#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \ + (t )( ((struct skbuf *)(bufPtr))->data) + +/* return the beginning of the headroom for the buffer */ +#define A_NETBUF_HEAD(bufPtr) \ + ((((struct sk_buff *)(bufPtr))->head)) + +/* + * OS specific network buffer access routines + */ +void *a_netbuf_alloc(int size); +void *a_netbuf_alloc_raw(int size); +void a_netbuf_free(void *bufPtr); +void *a_netbuf_to_data(void *bufPtr); +A_UINT32 a_netbuf_to_len(void *bufPtr); +A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len); +A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len); +A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len); +A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len); +A_INT32 a_netbuf_headroom(void *bufPtr); +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt); +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt); +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q); +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q); + +/* + * Kernel v.s User space functions + */ +A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n); +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n); + +/* In linux, WLAN Rx and Tx run in different contexts, so no need to check + * for any commands/data queued for WLAN */ +#define A_CHECK_DRV_TX() + +#define A_GET_CACHE_LINE_BYTES() L1_CACHE_BYTES + +static inline void *A_ALIGN_TO_CACHE_LINE(void *ptr) { + return (void *)L1_CACHE_ALIGN((A_UINT32)ptr); +} + +#else /* __KERNEL__ */ + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#ifndef INLINE +#define INLINE __inline__ +#endif +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#ifndef INLINE +#define INLINE __inline +#endif +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +#define A_MEMCPY(dst, src, len) memcpy((dst), (src), (len)) +#define A_MEMZERO(addr, len) memset((addr), 0, (len)) +#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len)) +#define A_MALLOC(size) malloc(size) +#define A_FREE(addr) free(addr) + +#ifdef ANDROID +#ifndef err +#include +#define err(_s, args...) do { \ + fprintf(stderr, "%s: line %d ", __FILE__, __LINE__); \ + fprintf(stderr, args); fprintf(stderr, ": %d\n", errno); \ + exit(_s); } while (0) +#endif +#else +#include +#endif + +#endif /* __KERNEL__ */ + +#endif /* _OSAPI_LINUX_H_ */ diff --git a/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h b/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h new file mode 100644 index 000000000000..97e090f95481 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/wlan_config.h @@ -0,0 +1,50 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains the tunable configuration items for the WLAN module +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _HOST_WLAN_CONFIG_H_ +#define _HOST_WLAN_CONFIG_H_ + +/* Include definitions here that can be used to tune the WLAN module behavior. + * Different customers can tune the behavior as per their needs, here. + */ + +/* This configuration item when defined will consider the barker preamble + * mentioned in the ERP IE of the beacons from the AP to determine the short + * preamble support sent in the (Re)Assoc request frames. + */ +#define WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP 0 + +/* This config item when defined will not send the power module state transition + * failure events that happen during scan, to the host. + */ +#define WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN 0 + +/* + * This configuration item enable/disable keepalive support. + * Keepalive support: In the absence of any data traffic to AP, null + * frames will be sent to the AP at periodic interval, to keep the association + * active. This configuration item defines the periodic interval. + * Use value of zero to disable keepalive support + * Default: 60 seconds + */ +#define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 + + +#endif /* _HOST_WLAN_CONFIG_H_ */ diff --git a/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h b/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h new file mode 100644 index 000000000000..ab9a9fc0d0fd --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/include/wmi_filter_linux.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2008-2009 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + */ + +#ifndef _WMI_FILTER_LINUX_H_ +#define _WMI_FILTER_LINUX_H_ + +/* + * sioctl_filter - Standard ioctl + * pioctl_filter - Priv ioctl + * xioctl_filter - eXtended ioctl + * + * ---- Possible values for the WMI filter --------------- + * (0) - Block this cmd always (or) not implemented + * (INFRA_NETWORK) - Allow this cmd only in STA mode + * (ADHOC_NETWORK) - Allow this cmd only in IBSS mode + * (AP_NETWORK) - Allow this cmd only in AP mode + * (INFRA_NETWORK | ADHOC_NETWORK) - Block this cmd in AP mode + * (ADHOC_NETWORK | AP_NETWORK) - Block this cmd in STA mode + * (INFRA_NETWORK | AP_NETWORK) - Block this cmd in IBSS mode + * (INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK)- allow only when mode is set + * (0xFF) - Allow this cmd always irrespective of mode + */ + +A_UINT8 sioctl_filter[] = { +(AP_NETWORK), /* SIOCSIWCOMMIT 0x8B00 */ +(0xFF), /* SIOCGIWNAME 0x8B01 */ +(0), /* SIOCSIWNWID 0x8B02 */ +(0), /* SIOCGIWNWID 0x8B03 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWFREQ 0x8B04 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWFREQ 0x8B05 */ +(0xFF), /* SIOCSIWMODE 0x8B06 */ +(0xFF), /* SIOCGIWMODE 0x8B07 */ +(0), /* SIOCSIWSENS 0x8B08 */ +(0), /* SIOCGIWSENS 0x8B09 */ +(0), /* SIOCSIWRANGE 0x8B0A */ +(0xFF), /* SIOCGIWRANGE 0x8B0B */ +(0), /* SIOCSIWPRIV 0x8B0C */ +(0), /* SIOCGIWPRIV 0x8B0D */ +(0), /* SIOCSIWSTATS 0x8B0E */ +(0), /* SIOCGIWSTATS 0x8B0F */ +(0), /* SIOCSIWSPY 0x8B10 */ +(0), /* SIOCGIWSPY 0x8B11 */ +(0), /* SIOCSIWTHRSPY 0x8B12 */ +(0), /* SIOCGIWTHRSPY 0x8B13 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWAP 0x8B14 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWAP 0x8B15 */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWMLME 0X8B16 */ +#else +(0), /* Dummy 0 */ +#endif /* LINUX_VERSION_CODE */ +(0), /* SIOCGIWAPLIST 0x8B17 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWSCAN 0x8B18 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWSCAN 0x8B19 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWESSID 0x8B1A */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWESSID 0x8B1B */ +(0), /* SIOCSIWNICKN 0x8B1C */ +(0), /* SIOCGIWNICKN 0x8B1D */ +(0), /* Dummy 0 */ +(0), /* Dummy 0 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWRATE 0x8B20 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWRATE 0x8B21 */ +(0), /* SIOCSIWRTS 0x8B22 */ +(0), /* SIOCGIWRTS 0x8B23 */ +(0), /* SIOCSIWFRAG 0x8B24 */ +(0), /* SIOCGIWFRAG 0x8B25 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWTXPOW 0x8B26 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWTXPOW 0x8B27 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCSIWRETRY 0x8B28 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* SIOCGIWRETRY 0x8B29 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWENCODE 0x8B2A */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWENCODE 0x8B2B */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCSIWPOWER 0x8B2C */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* SIOCGIWPOWER 0x8B2D */ +}; + + + +A_UINT8 pioctl_filter[] = { +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+1) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+2) */ +(AP_NETWORK), /* IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+3) */ +(INFRA_NETWORK), /* IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+4) */ +(0), /* IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+5) */ +(0), /* (SIOCIWFIRSTPRIV+6) */ +(0), /* (SIOCIWFIRSTPRIV+7) */ +(0), /* (SIOCIWFIRSTPRIV+8) */ +(0), /* (SIOCIWFIRSTPRIV+9) */ +(0), /* IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+10) */ +(0xFF), /* AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+11) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+12) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+13) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+14) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+15) */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18) */ +(INFRA_NETWORK), /* AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)*/ +(0xFF), /* AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28) */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29) */ +(ADHOC_NETWORK), /* AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30) */ +}; + + + +A_UINT8 xioctl_filter[] = { +(0xFF), /* Dummy 0 */ +(0xFF), /* AR6000_XIOCTL_BMI_DONE 1 */ +(0xFF), /* AR6000_XIOCTL_BMI_READ_MEMORY 2 */ +(0xFF), /* AR6000_XIOCTL_BMI_WRITE_MEMORY 3 */ +(0xFF), /* AR6000_XIOCTL_BMI_EXECUTE 4 */ +(0xFF), /* AR6000_XIOCTL_BMI_SET_APP_START 5 */ +(0xFF), /* AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6 */ +(0xFF), /* AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7 */ +(0xFF), /* AR6000_XIOCTL_BMI_TEST 8 */ +(0xFF), /* AR6000_XIOCTL_UNUSED9 9 */ +(0xFF), /* AR6000_XIOCTL_UNUSED10 10 */ +(0xFF), /* AR6000_XIOCTL_UNUSED11 11 */ +(0xFF), /* AR6000_XIOCTL_FORCE_TARGET_RESET 12 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_OPEN 13 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_CLOSE 14 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_READ 15 */ +(0xFF), /* AR6000_XIOCTL_HTC_RAW_WRITE 16 */ +(0xFF), /* AR6000_XIOCTL_CHECK_TARGET_READY 17 */ +(0xFF), /* AR6000_XIOCTL_GPIO_OUTPUT_SET 18 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INPUT_GET 19 */ +(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_SET 20 */ +(0xFF), /* AR6000_XIOCTL_GPIO_REGISTER_GET 21 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INTR_ACK 22 */ +(0xFF), /* AR6000_XIOCTL_GPIO_INTR_WAIT 23 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_ADHOC_BSSID 24 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_OPT_MODE 25 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_OPT_SEND_FRAME 26 */ +(ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_SET_BEACON_INTVAL 27 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* IEEE80211_IOCTL_SETAUTHALG 28 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_MAX_SP 30 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_TBL 31 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTRL_WMI_GET_POWER_MODE 34 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_ROAM_DATA 36 */ +(0xFF), /* AR6000_XIOCTL_WMI_SETRETRYLIMITS 37 */ +(0xFF), /* AR6000_XIOCTL_TCMD_CONT_TX 38 */ +(0xFF), /* AR6000_XIOCTL_TCMD_CONT_RX 39 */ +(0xFF), /* AR6000_XIOCTL_TCMD_PM 40 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_STARTSCAN 41 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SETFIXRATES 42 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GETFIXRATES 43 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_CLR_RSSISNR 45 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_RTS 47 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_LPREAMBLE 48 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_AUTHMODE 49 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_REASSOCMODE 50 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WMM 51 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53 */ +(INFRA_NETWORK | ADHOC_NETWORK | AP_NETWORK), /* AR6000_XIOCTL_WMI_GET_RD 54 */ +(0xFF), /* AR6000_XIOCTL_DIAG_READ 55 */ +(0xFF), /* AR6000_XIOCTL_DIAG_WRITE 56 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_TXOP 57 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_USER_SETKEYS 58 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_SET_KEEPALIVE 59 */ +(INFRA_NETWORK), /* AR6000_XIOCTL_WMI_GET_KEEPALIVE 60 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63 */ +(0xFF), /* AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64 */ +(0xFF), /* AR6000_XIOCTL_WMI_SET_APPIE 65 */ +(0xFF), /* AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66 */ +(0xFF), /* AR6000_XIOCTL_DBGLOG_CFG_MODULE 67 */ +(0xFF), /* AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68 */ +(0xFF), /* Dummy 69 */ +(0xFF), /* AR6000_XIOCTL_WMI_SET_WSC_STATUS 70 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_STATUS 71 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_PARAMS 72 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_WOW_MODE 74 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_WOW_LIST 75 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77 */ +(0xFF), /* AR6000_XIOCTL_TARGET_INFO 78 */ +(0xFF), /* AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79 */ +(0xFF), /* AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_PMKID_LIST 83 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_PMKID_LIST 84 */ +(0xFF), /* Dummy 85 */ +(0xFF), /* Dummy 86 */ +(0xFF), /* Dummy 87 */ +(0xFF), /* Dummy 88 */ +(0xFF), /* Dummy 89 */ +(0xFF), /* AR6000_XIOCTL_UNUSED90 90 */ +(0xFF), /* AR6000_XIOCTL_BMI_LZ_STREAM_START 91 */ +(0xFF), /* AR6000_XIOCTL_BMI_LZ_DATA 92 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_CFG 93 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_ADDR_SET 94 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_START 95 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_STOP 96 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_PROF_COUNT_GET 97 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_ABORT_SCAN 98 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_STA_LIST 99 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_HIDDEN_SSID 100 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_NUM_STA 101 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_MAC 102 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_ACL_LIST 103 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_COMMIT_CONFIG 104 */ +(AP_NETWORK), /* IEEE80211_IOCTL_GETWPAIE 105 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_CONN_INACT_TIME 106 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_PROT_SCAN_TIME 107 */ +(AP_NETWORK), /* AR6000_XIOCTL_WMI_SET_COUNTRY 108 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_DTIM 109 */ +(0xFF), /* AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT 110 */ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_SET_IP 111 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_ACL_POLICY 112 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_INTRA_BSS_COMM 113 */ +(0xFF), /* AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO 114 */ +(0xFF), /* AR6000_XIOCTL_MODULE_DEBUG_SET_MASK 115 */ +(0xFF), /* AR6000_XIOCTL_MODULE_DEBUG_GET_MASK 116 */ +(0xFF), /* AR6000_XIOCTL_DUMP_RCV_AGGR_STATS 117 */ +(0xFF), /* AR6000_XIOCTL_SET_HT_CAP 118 */ +(0xFF), /* AR6000_XIOCTL_SET_HT_OP 119 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_STAT 120 */ +(0xFF), /* AR6000_XIOCTL_SET_TX_SELECT_RATES 121 */ +(0xFF), /* AR6000_XIOCTL_SETUP_AGGR 122 */ +(0xFF), /* AR6000_XIOCTL_ALLOW_AGGR 123 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_HIDDEN_SSID 124 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_COUNTRY 125 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_WMODE 126 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_GET_DTIM 127 */ +(AP_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_AP_GET_BINTVL 128 */ +(0xFF), /* AR6000_XIOCTL_AP_GET_RTS 129 */ +(0xFF), /* AR6000_XIOCTL_DELE_AGGR 130 */ +(0xFF), /* AR6000_XIOCTL_FETCH_TARGET_REGS 131 */ +(0xFF), /* AR6000_XIOCTL_HCI_CMD 132 */ +(0xFF), /* AR6000_XIOCTL_ACL_DATA 133 */ +(0xFF), /* AR6000_XIOCTL_WLAN_CONN_PRECEDENCE 134 */ +(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_11BG_RATESET 135 */ +(0xFF), +(0xFF), +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT 138*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV 139*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG 140*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG 141*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG 142*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG 143*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG 144*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS 145*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG 146*/ +(INFRA_NETWORK | ADHOC_NETWORK), /* AR6000_XIOCTL_WMI_GET_BTCOEX_GET_STATS 147*/ + +}; + +#endif /*_WMI_FILTER_LINUX_H_*/ diff --git a/drivers/net/wireless/ath6kl/os/linux/ioctl.c b/drivers/net/wireless/ath6kl/os/linux/ioctl.c new file mode 100644 index 000000000000..902f0701dabd --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/ioctl.c @@ -0,0 +1,4559 @@ +/* + * + * Copyright (c) 2004-2010 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#include "ar6000_drv.h" +#include "ieee80211_ioctl.h" +#include "ar6kap_common.h" +#include "targaddrs.h" +#include "a_hci.h" +#include "wlan_config.h" + +extern int enablerssicompensation; +A_UINT32 tcmdRxFreq; +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; +extern int tspecCompliance; +extern int bmienable; +extern int bypasswmi; +extern int loghci; + +static int +ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + /* currently assume only roam times are required */ + if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) { + return -EIO; + } + + + return 0; +} + +static int +ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_ROAM_CTRL_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) { + if (cmd.info.bssBiasInfo.numBss > 1) { + size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS); + } + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_POWERSAVE_TIMERS_POLICY_CMD cmd; + A_UINT8 size = sizeof(cmd); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if (copy_from_user(&cmd, userdata, size)) { + return -EFAULT; + } + + if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) { + return -EIO; + } + + return 0; +} + +static int +ar6000_ioctl_set_qos_supp(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_QOS_SUPP_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ret = wmi_set_qos_supp_cmd(ar->arWmi, cmd.status); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_WMM_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + if (cmd.status == WMI_WMM_ENABLED) { + ar->arWmmEnabled = TRUE; + } else { + ar->arWmmEnabled = FALSE; + } + + ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_WMM_TXOP_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_STATUS ret = 0; + + if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) { + return -EIO; + } + + if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1), + &ar->arRegCode, sizeof(ar->arRegCode))) + ret = -EFAULT; + + return ret; +} + +static int +ar6000_ioctl_set_country(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_AP_SET_COUNTRY_CMD cmd; + A_STATUS ret; + + if ((dev->flags & IFF_UP) != IFF_UP) { + return -EIO; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + + ar->ap_profile_flag = 1; /* There is a change in profile */ + + ret = wmi_set_country(ar->arWmi, cmd.countryCode); + A_MEMCPY(ar->ap_country_code, cmd.countryCode, 3); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + + +/* Get power mode command */ +static int +ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_POWER_MODE_CMD power_mode; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi); + if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) { + ret = -EFAULT; + } + + return ret; +} + + +static int +ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_CHANNEL_PARAMS_CMD cmd, *cmdp; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( (ar->arNextMode == AP_NETWORK) && (cmd.numChannels || cmd.scanParam) ) { + A_PRINTF("ERROR: Only wmode is allowed in AP mode\n"); + return -EIO; + } + + if (cmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, rq->ifr_data, + sizeof (*cmdp) + + ((cmd.numChannels - 1) * sizeof(A_UINT16)))) + { + kfree(cmdp); + return -EFAULT; + } + } else { + cmdp = &cmd; + } + + if ((ar->arPhyCapability == WMI_11G_CAPABILITY) && + ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE))) + { + ret = -EINVAL; + } + + if (!ret && + (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode, + cmdp->numChannels, cmdp->channelList) + != A_OK)) + { + ret = -EIO; + } + + if (cmd.numChannels > 1) { + kfree(cmdp); + } + + ar->ap_wmode = cmdp->phyMode; + /* Set the profile change flag to allow a commit cmd */ + ar->ap_profile_flag = 1; + + return ret; +} + + +static int +ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq) +{ +#define SWAP_THOLD(thold1, thold2) do { \ + USER_RSSI_THOLD tmpThold; \ + tmpThold.tag = thold1.tag; \ + tmpThold.rssi = thold1.rssi; \ + thold1.tag = thold2.tag; \ + thold1.rssi = thold2.rssi; \ + thold2.tag = tmpThold.tag; \ + thold2.rssi = tmpThold.rssi; \ +} while (0) + + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + USER_RSSI_PARAMS rssiParams; + A_INT32 i, j; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) { + return -EFAULT; + } + cmd.weight = rssiParams.weight; + cmd.pollTime = rssiParams.pollTime; + + A_MEMCPY(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map)); + /* + * only 6 elements, so use bubble sorting, in ascending order + */ + for (i = 5; i > 0; i--) { + for (j = 0; j < i; j++) { /* above tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + for (i = 11; i > 6; i--) { + for (j = 6; j < i; j++) { /* below tholds */ + if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) { + SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]); + } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) { + return EFAULT; + } + } + } + +#ifdef DEBUG + for (i = 0; i < 12; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("thold[%d].tag: %d, thold[%d].rssi: %d \n", + i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi)); + } +#endif + + if (enablerssicompensation) { + for (i = 0; i < 6; i++) + ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, TRUE); + for (i = 6; i < 12; i++) + ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, FALSE); + } + + cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi; + cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi; + cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi; + cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi; + cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi; + cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi; + cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi; + cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi; + cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi; + cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi; + cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi; + cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi; + + if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_LQ_THRESHOLD_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) { + return -EFAULT; + } + + if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) { + ret = -EIO; + } + + return ret; +} + + +static int +ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_PROBED_SSID_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength, + cmd.ssid) != A_OK) + { + ret = -EIO; + } + + return ret; +} + +static int +ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_ADD_BAD_AP_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) { + return -EIO; + } + + if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) { + /* + * This is a delete badAP. + */ + if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) { + ret = -EIO; + } + } else { + if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) { + ret = -EIO; + } + } + + return ret; +} + +static int +ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_CREATE_PSTREAM_CMD cmd; + A_STATUS ret; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_verify_tspec_params(&cmd, tspecCompliance); + if (ret == A_OK) + ret = wmi_create_pstream_cmd(ar->arWmi, &cmd); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_DELETE_PSTREAM_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid); + + switch (ret) { + case A_OK: + return 0; + case A_EBUSY : + return -EBUSY; + case A_NO_MEMORY: + return -ENOMEM; + case A_EINVAL: + default: + return -EFAULT; + } +} + +static int +ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + struct ar6000_queuereq qreq; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if( copy_from_user(&qreq, rq->ifr_data, + sizeof(struct ar6000_queuereq))) + return -EFAULT; + + qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass); + + if (copy_to_user(rq->ifr_data, &qreq, + sizeof(struct ar6000_queuereq))) + { + ret = -EFAULT; + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev, + struct ifreq *rq, A_UINT8 *data, A_UINT32 len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_UINT32 buf[4+TCMD_MAX_RATES]; + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->tcmdRxReport = 0; + if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + buf[0] = ar->tcmdRxTotalPkt; + buf[1] = ar->tcmdRxRssi; + buf[2] = ar->tcmdRxcrcErrPkt; + buf[3] = ar->tcmdRxsecErrPkt; + A_MEMCPY(((A_UCHAR *)buf)+(4*sizeof(A_UINT32)), ar->tcmdRateCnt, sizeof(ar->tcmdRateCnt)); + A_MEMCPY(((A_UCHAR *)buf)+(4*sizeof(A_UINT32))+(TCMD_MAX_RATES *sizeof(A_UINT16)), ar->tcmdRateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard)); + + if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) { + ret = -EFAULT; + } + + up(&ar->arSem); + + return ret; +} + +void +ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)devt; + TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results; + + if (enablerssicompensation) { + rx_rep->u.report.rssiInDBm = rssi_compensation_calc_tcmd(tcmdRxFreq, rx_rep->u.report.rssiInDBm,rx_rep->u.report.totalPkt); + } + + + ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt; + ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm; + ar->tcmdRxcrcErrPkt = rx_rep->u.report.crcErrPkt; + ar->tcmdRxsecErrPkt = rx_rep->u.report.secErrPkt; + ar->tcmdRxReport = 1; + A_MEMZERO(ar->tcmdRateCnt, sizeof(ar->tcmdRateCnt)); + A_MEMZERO(ar->tcmdRateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard)); + A_MEMCPY(ar->tcmdRateCnt, rx_rep->u.report.rateCnt, sizeof(ar->tcmdRateCnt)); + A_MEMCPY(ar->tcmdRateCntShortGuard, rx_rep->u.report.rateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard)); + + wake_up(&arEvent); +} +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +static int +ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_TARGET_ERROR_REPORT_BITMASK cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask); + + return (ret==0 ? ret : -EINVAL); +} + +static int +ar6000_clear_target_stats(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + A_MEMZERO(pStats, sizeof(TARGET_STATS)); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return ret; +} + +static int +ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + TARGET_STATS_CMD cmd; + TARGET_STATS *pStats = &ar->arTargetStats; + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) { + ret = -EFAULT; + } + + if (cmd.clearStats == 1) { + ret = ar6000_clear_target_stats(dev); + } + + up(&ar->arSem); + + return ret; +} + +static int +ar6000_ioctl_get_ap_stats(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_AP_MODE_STAT cmd; + WMI_AP_MODE_STAT *pStats = &ar->arAPStats; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1), + sizeof(cmd))) + { + return -EFAULT; + } + if (cmd.action == AP_CLEAR_STATS) { + A_UINT8 i; + AR6000_SPIN_LOCK(&ar->arLock, 0); + for(i = 0; i < AP_MAX_NUM_STA; i++) { + pStats->sta[i].tx_bytes = 0; + pStats->sta[i].tx_pkts = 0; + pStats->sta[i].tx_error = 0; + pStats->sta[i].tx_discard = 0; + pStats->sta[i].rx_bytes = 0; + pStats->sta[i].rx_pkts = 0; + pStats->sta[i].rx_error = 0; + pStats->sta[i].rx_discard = 0; + } + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + return ret; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + ar->statsUpdatePending = TRUE; + + if(wmi_get_stats_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) { + ret = -EFAULT; + } + + up(&ar->arSem); + + return ret; +} + +static int +ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_ACCESS_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_access_params_cmd(ar->arWmi, cmd.ac, cmd.txop, cmd.eCWmin, cmd.eCWmax, + cmd.aifsn) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_DISC_TIMEOUT_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_VOICE_PKT_SIZE_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + + return (ret); +} + +static int +ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_MAX_SP_LEN_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + + +static int +ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BT_STATUS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BT_PARAMS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return (ret); +} + +static int +ar6000_xioctl_set_btcoex_fe_ant_cmd(struct net_device * dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BTCOEX_FE_ANT_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return(ret); +} + +static int +ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(struct net_device * dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return(ret); +} + +static int +ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(struct net_device * dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_btcoex_btinquiry_page_config_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return(ret); +} + +static int +ar6000_xioctl_set_btcoex_sco_config_cmd(struct net_device * dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BTCOEX_SCO_CONFIG_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_btcoex_sco_config_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return(ret); +} + +static int +ar6000_xioctl_set_btcoex_a2dp_config_cmd(struct net_device * dev, + char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BTCOEX_A2DP_CONFIG_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_btcoex_a2dp_config_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return(ret); +} + +static int +ar6000_xioctl_set_btcoex_aclcoex_config_cmd(struct net_device * dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_btcoex_aclcoex_config_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return(ret); +} + +static int +ar60000_xioctl_set_btcoex_debug_cmd(struct net_device * dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BTCOEX_DEBUG_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_btcoex_debug_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + + return(ret); +} + +static int +ar6000_xioctl_set_btcoex_bt_operating_status_cmd(struct net_device * dev, char * userdata) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD cmd; + int ret = 0; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + return -EFAULT; + } + + if (wmi_set_btcoex_bt_operating_status_cmd(ar->arWmi, &cmd) == A_OK) + { + ret = 0; + } else { + ret = -EINVAL; + } + return(ret); +} + +static int +ar6000_xioctl_get_btcoex_config_cmd(struct net_device * dev, char * userdata, + struct ifreq *rq) +{ + + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + AR6000_BTCOEX_CONFIG btcoexConfig; + WMI_BTCOEX_CONFIG_EVENT *pbtcoexConfigEv = &ar->arBtcoexConfig; + + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + if (copy_from_user(&btcoexConfig.configCmd, userdata, sizeof(AR6000_BTCOEX_CONFIG))) { + return -EFAULT; + } + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (wmi_get_btcoex_config_cmd(ar->arWmi, (WMI_GET_BTCOEX_CONFIG_CMD *)&btcoexConfig.configCmd) != A_OK) + { + up(&ar->arSem); + return -EIO; + } + + ar->statsUpdatePending = TRUE; + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret && copy_to_user(btcoexConfig.configEvent, pbtcoexConfigEv, sizeof(WMI_BTCOEX_CONFIG_EVENT))) { + ret = -EFAULT; + } + up(&ar->arSem); + return ret; +} + +static int +ar6000_xioctl_get_btcoex_stats_cmd(struct net_device * dev, char * userdata, struct ifreq *rq) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + AR6000_BTCOEX_STATS btcoexStats; + WMI_BTCOEX_STATS_EVENT *pbtcoexStats = &ar->arBtcoexStats; + int ret = 0; + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (copy_from_user(&btcoexStats.statsEvent, userdata, sizeof(AR6000_BTCOEX_CONFIG))) { + return -EFAULT; + } + + if (wmi_get_btcoex_stats_cmd(ar->arWmi) != A_OK) + { + up(&ar->arSem); + return -EIO; + } + + ar->statsUpdatePending = TRUE; + + wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret && copy_to_user(btcoexStats.statsEvent, pbtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT))) { + ret = -EFAULT; + } + + + up(&ar->arSem); + + return(ret); +} + + +#ifdef CONFIG_HOST_GPIO_SUPPORT +struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results; +/* gpio_reg_results and gpio_data_available are protected by arSem */ +static struct ar6000_gpio_register_cmd_s gpio_reg_results; +static A_BOOL gpio_data_available; /* Requested GPIO data available */ +static A_BOOL gpio_intr_available; /* GPIO interrupt info available */ +static A_BOOL gpio_ack_received; /* GPIO ack was received */ + +/* Host-side initialization for General Purpose I/O support */ +void ar6000_gpio_init(void) +{ + gpio_intr_available = FALSE; + gpio_data_available = FALSE; + gpio_ack_received = FALSE; +} + +/* + * Called when a GPIO interrupt is received from the Target. + * intr_values shows which GPIO pins have interrupted. + * input_values shows a recent value of GPIO pins. + */ +void +ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values) +{ + gpio_intr_results.intr_mask = intr_mask; + gpio_intr_results.input_values = input_values; + *((volatile A_BOOL *)&gpio_intr_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when a response is received from the Target + * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get + * call. + */ +void +ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value) +{ + gpio_reg_results.gpioreg_id = reg_id; + gpio_reg_results.value = value; + *((volatile A_BOOL *)&gpio_data_available) = TRUE; + wake_up(&arEvent); +} + +/* + * This is called when an acknowledgement is received from the Target + * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set + * call. + */ +void +ar6000_gpio_ack_rx(void) +{ + gpio_ack_received = TRUE; + wake_up(&arEvent); +} + +A_STATUS +ar6000_gpio_output_set(struct net_device *dev, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + gpio_ack_received = FALSE; + return wmi_gpio_output_set(ar->arWmi, + set_mask, clear_mask, enable_mask, disable_mask); +} + +static A_STATUS +ar6000_gpio_input_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_input_get(ar->arWmi); +} + +static A_STATUS +ar6000_gpio_register_set(struct net_device *dev, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + gpio_ack_received = FALSE; + return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value); +} + +static A_STATUS +ar6000_gpio_register_get(struct net_device *dev, + A_UINT32 gpioreg_id) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + *((volatile A_BOOL *)&gpio_data_available) = FALSE; + return wmi_gpio_register_get(ar->arWmi, gpioreg_id); +} + +static A_STATUS +ar6000_gpio_intr_ack(struct net_device *dev, + A_UINT32 ack_mask) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + gpio_intr_available = FALSE; + return wmi_gpio_intr_ack(ar->arWmi, ack_mask); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static struct prof_count_s prof_count_results; +static A_BOOL prof_count_available; /* Requested GPIO data available */ + +static A_STATUS +prof_count_get(struct net_device *dev) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + *((volatile A_BOOL *)&prof_count_available) = FALSE; + return wmi_prof_count_get_cmd(ar->arWmi); +} + +/* + * This is called when a response is received from the Target + * for a previous prof_count_get call. + */ +void +prof_count_rx(A_UINT32 addr, A_UINT32 count) +{ + prof_count_results.addr = addr; + prof_count_results.count = count; + *((volatile A_BOOL *)&prof_count_available) = TRUE; + wake_up(&arEvent); +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + + +static A_STATUS +ar6000_create_acl_data_osbuf(struct net_device *dev, A_UINT8 *userdata, void **p_osbuf) +{ + void *osbuf = NULL; + A_UINT8 tmp_space[8]; + HCI_ACL_DATA_PKT *acl; + A_UINT8 hdr_size, *datap=NULL; + A_STATUS ret = A_OK; + + /* ACL is in data path. There is a need to create pool + * mechanism for allocating and freeing NETBUFs - ToDo later. + */ + + *p_osbuf = NULL; + acl = (HCI_ACL_DATA_PKT *)tmp_space; + hdr_size = sizeof(acl->hdl_and_flags) + sizeof(acl->data_len); + + do { + if (a_copy_from_user(acl, userdata, hdr_size)) { + ret = A_EFAULT; + break; + } + + osbuf = A_NETBUF_ALLOC(hdr_size + acl->data_len); + if (osbuf == NULL) { + ret = A_NO_MEMORY; + break; + } + A_NETBUF_PUT(osbuf, hdr_size + acl->data_len); + datap = (A_UINT8 *)A_NETBUF_DATA(osbuf); + + /* Real copy to osbuf */ + acl = (HCI_ACL_DATA_PKT *)(datap); + A_MEMCPY(acl, tmp_space, hdr_size); + if (a_copy_from_user(acl->data, userdata + hdr_size, acl->data_len)) { + ret = A_EFAULT; + break; + } + } while(FALSE); + + if (ret == A_OK) { + *p_osbuf = osbuf; + } else { + A_NETBUF_FREE(osbuf); + } + return ret; +} + + + +int +ar6000_ioctl_ap_setparam(AR_SOFTC_T *ar, int param, int value) +{ + int ret=0; + + switch(param) { + case IEEE80211_PARAM_WPA: + switch (value) { + case WPA_MODE_WPA1: + ar->arAuthMode = WPA_AUTH; + break; + case WPA_MODE_WPA2: + ar->arAuthMode = WPA2_AUTH; + break; + case WPA_MODE_AUTO: + ar->arAuthMode = WPA_AUTH | WPA2_AUTH; + break; + case WPA_MODE_NONE: + ar->arAuthMode = NONE_AUTH; + break; + } + break; + case IEEE80211_PARAM_AUTHMODE: + if(value == IEEE80211_AUTH_WPA_PSK) { + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + } else if ((WPA_AUTH | WPA2_AUTH) == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH | WPA2_PSK_AUTH; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error - Setting PSK "\ + "mode when WPA param was set to %d\n", + ar->arAuthMode)); + ret = -EIO; + } + } + break; + case IEEE80211_PARAM_UCASTCIPHER: + ar->arPairwiseCrypto = 0; + if(value & (1<arPairwiseCrypto |= AES_CRYPT; + } + if(value & (1<arPairwiseCrypto |= TKIP_CRYPT; + } + if(!ar->arPairwiseCrypto) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR, + ("Error - Invalid cipher in WPA \n")); + ret = -EIO; + } + break; + case IEEE80211_PARAM_PRIVACY: + if(value == 0) { + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + } + break; +#ifdef WAPI_ENABLE + case IEEE80211_PARAM_WAPI: + A_PRINTF("WAPI Policy: %d\n", value); + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + if(value & 0x1) { + ar->arPairwiseCrypto = WAPI_CRYPT; + ar->arGroupCrypto = WAPI_CRYPT; + } else { + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + } + break; +#endif + } + return ret; +} + +int +ar6000_ioctl_setparam(AR_SOFTC_T *ar, int param, int value) +{ + A_BOOL profChanged = FALSE; + int ret=0; + + if(ar->arNextMode == AP_NETWORK) { + ar->ap_profile_flag = 1; /* There is a change in profile */ + switch (param) { + case IEEE80211_PARAM_WPA: + case IEEE80211_PARAM_AUTHMODE: + case IEEE80211_PARAM_UCASTCIPHER: + case IEEE80211_PARAM_PRIVACY: + case IEEE80211_PARAM_WAPI: + ret = ar6000_ioctl_ap_setparam(ar, param, value); + return ret; + } + } + + switch (param) { + case IEEE80211_PARAM_WPA: + switch (value) { + case WPA_MODE_WPA1: + ar->arAuthMode = WPA_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_WPA2: + ar->arAuthMode = WPA2_AUTH; + profChanged = TRUE; + break; + case WPA_MODE_NONE: + ar->arAuthMode = NONE_AUTH; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_AUTHMODE: + switch(value) { + case IEEE80211_AUTH_WPA_PSK: + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + profChanged = TRUE; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + profChanged = TRUE; + } else { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error - Setting PSK "\ + "mode when WPA param was set to %d\n", + ar->arAuthMode)); + ret = -EIO; + } + break; + case IEEE80211_AUTH_WPA_CCKM: + if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_AUTH_CCKM; + } else { + ar->arAuthMode = WPA_AUTH_CCKM; + } + break; + default: + break; + } + break; + case IEEE80211_PARAM_UCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arPairwiseCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arPairwiseCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arPairwiseCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arPairwiseCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_UCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arPairwiseCryptoLen = value; + } + break; + case IEEE80211_PARAM_MCASTCIPHER: + switch (value) { + case IEEE80211_CIPHER_AES_CCM: + ar->arGroupCrypto = AES_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_TKIP: + ar->arGroupCrypto = TKIP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_WEP: + ar->arGroupCrypto = WEP_CRYPT; + profChanged = TRUE; + break; + case IEEE80211_CIPHER_NONE: + ar->arGroupCrypto = NONE_CRYPT; + profChanged = TRUE; + break; + } + break; + case IEEE80211_PARAM_MCASTKEYLEN: + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) { + ret = -EIO; + } else { + ar->arGroupCryptoLen = value; + } + break; + case IEEE80211_PARAM_COUNTERMEASURES: + if (ar->arWmiReady == FALSE) { + return -EIO; + } + wmi_set_tkip_countermeasures_cmd(ar->arWmi, value); + break; + default: + break; + } + if ((ar->arNextMode != AP_NETWORK) && (profChanged == TRUE)) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + } + + return ret; +} + +int +ar6000_ioctl_setkey(AR_SOFTC_T *ar, struct ieee80211req_key *ik) +{ + KEY_USAGE keyUsage; + A_STATUS status; + CRYPTO_TYPE keyType = NONE_CRYPT; + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif + if ( (0 == memcmp(ik->ik_macaddr, null_mac, IEEE80211_ADDR_LEN)) || + (0 == memcmp(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN)) ) { + keyUsage = GROUP_USAGE; + if(ar->arNextMode == AP_NETWORK) { + A_MEMCPY(&ar->ap_mode_bkey, ik, + sizeof(struct ieee80211req_key)); +#ifdef WAPI_ENABLE + if(ar->arPairwiseCrypto == WAPI_CRYPT) { + return ap_set_wapi_key(ar, ik); + } +#endif + } +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif + } else { + keyUsage = PAIRWISE_USAGE; +#ifdef USER_KEYS + A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik, + sizeof(struct ieee80211req_key)); +#endif +#ifdef WAPI_ENABLE + if(ar->arNextMode == AP_NETWORK) { + if(ar->arPairwiseCrypto == WAPI_CRYPT) { + return ap_set_wapi_key(ar, ik); + } + } +#endif + } + + switch (ik->ik_type) { + case IEEE80211_CIPHER_WEP: + keyType = WEP_CRYPT; + break; + case IEEE80211_CIPHER_TKIP: + keyType = TKIP_CRYPT; + break; + case IEEE80211_CIPHER_AES_CCM: + keyType = AES_CRYPT; + break; + default: + break; + } +#ifdef USER_KEYS + ar->user_saved_keys.keyType = keyType; +#endif + if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) { + if (NONE_CRYPT == keyType) { + return -EIO; + } + + if (WEP_CRYPT == keyType) { + int index = ik->ik_keyix; + + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(ik->ik_keylen)) { + return -EIO; + } + + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, ik->ik_keydata, ik->ik_keylen); + ar->arWepKeyList[index].arKeyLen = ik->ik_keylen; + + if(ik->ik_flags & IEEE80211_KEY_DEFAULT){ + ar->arDefTxKeyIndex = index; + } + + return 0; + } + + if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) && + (GROUP_USAGE & keyUsage)) + { + A_UNTIMEOUT(&ar->disconnect_timer); + } + + status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage, + ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc, + ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr, + SYNC_BOTH_WMIFLAG); + + if (status != A_OK) { + return -EIO; + } + } else { + status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata); + } + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = TRUE; +#endif + + return 0; +} + +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + HIF_DEVICE *hifDevice = ar->arHifDevice; + int ret = 0, param; + unsigned int address = 0; + unsigned int length = 0; + unsigned char *buffer; + char *userdata; + A_UINT32 connectCtrlFlags; + + + WMI_SET_AKMP_PARAMS_CMD akmpParams; + WMI_SET_PMKID_LIST_CMD pmkidInfo; + + WMI_SET_HT_CAP_CMD htCap; + WMI_SET_HT_OP_CMD htOp; + + /* + * ioctl operations may have to wait for the Target, so we cannot hold rtnl. + * Prevent the device from disappearing under us and release the lock during + * the ioctl operation. + */ + dev_hold(dev); + rtnl_unlock(); + + if (cmd == AR6000_IOCTL_EXTENDED) { + /* + * This allows for many more wireless ioctls than would otherwise + * be available. Applications embed the actual ioctl command in + * the first word of the parameter block, and use the command + * AR6000_IOCTL_EXTENDED_CMD on the ioctl call. + */ + get_user(cmd, (int *)rq->ifr_data); + userdata = (char *)(((unsigned int *)rq->ifr_data)+1); + if(is_xioctl_allowed(ar->arNextMode, cmd) != A_OK) { + A_PRINTF("xioctl: cmd=%d not allowed in this mode\n",cmd); + ret = -EOPNOTSUPP; + goto ioctl_done; + } + } else { + A_STATUS ret = is_iwioctl_allowed(ar->arNextMode, cmd); + if(ret == A_ENOTSUP) { + A_PRINTF("iwioctl: cmd=0x%x not allowed in this mode\n", cmd); + ret = -EOPNOTSUPP; + goto ioctl_done; + } else if (ret == A_ERROR) { + /* It is not our ioctl (out of range ioctl) */ + ret = -EOPNOTSUPP; + goto ioctl_done; + } + userdata = (char *)rq->ifr_data; + } + + if ((ar->arWlanState == WLAN_DISABLED) && + ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) && + (cmd != AR6000_XIOCTL_DIAG_READ) && + (cmd != AR6000_XIOCTL_DIAG_WRITE))) + { + ret = -EIO; + goto ioctl_done; + } + + ret = 0; + switch(cmd) + { + case IEEE80211_IOCTL_SETPARAM: + { + int param, value; + int *ptr = (int *)rq->ifr_ifru.ifru_newname; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + param = *ptr++; + value = *ptr; + ret = ar6000_ioctl_setparam(ar,param,value); + } + break; + } + case IEEE80211_IOCTL_SETKEY: + { + struct ieee80211req_key keydata; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&keydata, userdata, + sizeof(struct ieee80211req_key))) { + ret = -EFAULT; + } else { + ar6000_ioctl_setkey(ar, &keydata); + } + break; + } + case IEEE80211_IOCTL_DELKEY: + case IEEE80211_IOCTL_SETOPTIE: + { + //ret = -EIO; + break; + } + case IEEE80211_IOCTL_SETMLME: + { + struct ieee80211req_mlme mlme; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&mlme, userdata, + sizeof(struct ieee80211req_mlme))) { + ret = -EFAULT; + } else { + switch (mlme.im_op) { + case IEEE80211_MLME_AUTHORIZE: + A_PRINTF("setmlme AUTHORIZE %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + break; + case IEEE80211_MLME_UNAUTHORIZE: + A_PRINTF("setmlme UNAUTHORIZE %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + break; + case IEEE80211_MLME_DEAUTH: + A_PRINTF("setmlme DEAUTH %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + //remove_sta(ar, mlme.im_macaddr); + break; + case IEEE80211_MLME_DISASSOC: + A_PRINTF("setmlme DISASSOC %02X:%02X\n", + mlme.im_macaddr[4], mlme.im_macaddr[5]); + //remove_sta(ar, mlme.im_macaddr); + break; + default: + ret = 0; + goto ioctl_done; + } + + wmi_ap_set_mlme(ar->arWmi, mlme.im_op, mlme.im_macaddr, + mlme.im_reason); + } + break; + } + case IEEE80211_IOCTL_ADDPMKID: + { + struct ieee80211req_addpmkid req; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, sizeof(struct ieee80211req_addpmkid))) { + ret = -EFAULT; + } else { + A_STATUS status; + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n", + req.pi_bssid[0], req.pi_bssid[1], req.pi_bssid[2], + req.pi_bssid[3], req.pi_bssid[4], req.pi_bssid[5], + req.pi_enable)); + + status = wmi_setPmkid_cmd(ar->arWmi, req.pi_bssid, req.pi_pmkid, + req.pi_enable); + + if (status != A_OK) { + ret = -EIO; + goto ioctl_done; + } + } + break; + } +#ifdef CONFIG_HOST_TCMD_SUPPORT + case AR6000_XIOCTL_TCMD_CONT_TX: + { + TCMD_CONT_TX txCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send tx tcmd when target is asleep! \n"); + ret = -EFAULT; + goto ioctl_done; + } + + if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) { + ret = -EFAULT; + goto ioctl_done; + } else { + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX)); + } + } + break; + case AR6000_XIOCTL_TCMD_CONT_RX: + { + TCMD_CONT_RX rxCmd; + + if (ar->tcmdPm == TCMD_PM_SLEEP) { + A_PRINTF("Can NOT send rx tcmd when target is asleep! \n"); + ret = -EFAULT; + goto ioctl_done; + } + if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) { + ret = -EFAULT; + goto ioctl_done; + } + + switch(rxCmd.act) + { + case TCMD_CONT_RX_PROMIS: + case TCMD_CONT_RX_FILTER: + case TCMD_CONT_RX_SETMAC: + case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE: + wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd, + sizeof(TCMD_CONT_RX)); + tcmdRxFreq = rxCmd.u.para.freq; + break; + case TCMD_CONT_RX_REPORT: + ar6000_ioctl_tcmd_get_rx_report(dev, rq, + (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX)); + break; + default: + A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act); + ret = -EINVAL; + goto ioctl_done; + } + } + break; + case AR6000_XIOCTL_TCMD_PM: + { + TCMD_PM pmCmd; + + if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) { + ret = -EFAULT; + goto ioctl_done; + } + ar->tcmdPm = pmCmd.mode; + wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM)); + } + break; +#endif /* CONFIG_HOST_TCMD_SUPPORT */ + + case AR6000_XIOCTL_BMI_DONE: + if(bmienable) + { + rtnl_lock(); /* ar6000_init expects to be called holding rtnl lock */ + ret = ar6000_init(dev); + rtnl_unlock(); + } + else + { + ret = BMIDone(hifDevice); + } + break; + + case AR6000_XIOCTL_BMI_READ_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Read Memory (address: 0x%x, length: %d)\n", + address, length)); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + ret = BMIReadMemory(hifDevice, address, buffer, length); + if (copy_to_user(rq->ifr_data, buffer, length)) { + ret = -EFAULT; + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_WRITE_MEMORY: + get_user(address, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Write Memory (address: 0x%x, length: %d)\n", + address, length)); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(address) + + sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMIWriteMemory(hifDevice, address, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + + case AR6000_XIOCTL_BMI_TEST: + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("No longer supported\n")); + ret = -EOPNOTSUPP; + break; + + case AR6000_XIOCTL_BMI_EXECUTE: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Execute (address: 0x%x, param: %d)\n", + address, param)); + ret = BMIExecute(hifDevice, address, (A_UINT32*)¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_SET_APP_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Set App Start (address: 0x%x)\n", address)); + ret = BMISetAppStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_READ_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + ret = BMIReadSOCRegister(hifDevice, address, (A_UINT32*)¶m); + put_user(param, (unsigned int *)rq->ifr_data); /* return value */ + break; + + case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER: + get_user(address, (unsigned int *)userdata); + get_user(param, (unsigned int *)userdata + 1); + ret = BMIWriteSOCRegister(hifDevice, address, param); + break; + +#ifdef HTC_RAW_INTERFACE + case AR6000_XIOCTL_HTC_RAW_OPEN: + ret = A_OK; + if (!arRawIfEnabled(ar)) { + /* make sure block size is set in case the target was reset since last + * BMI phase (i.e. flashup downloads) */ + ret = ar6000_set_htc_params(ar->arHifDevice, + ar->arTargetType, + 0, /* use default yield */ + 0 /* use default number of HTC ctrl buffers */ + ); + if (A_FAILED(ret)) { + break; + } + /* Terminate the BMI phase */ + ret = BMIDone(hifDevice); + if (ret == A_OK) { + ret = ar6000_htc_raw_open(ar); + } + } + break; + + case AR6000_XIOCTL_HTC_RAW_CLOSE: + if (arRawIfEnabled(ar)) { + ret = ar6000_htc_raw_close(ar); + arRawIfEnabled(ar) = FALSE; + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_READ: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + buffer = rq->ifr_data + sizeof(length); + ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; + + case AR6000_XIOCTL_HTC_RAW_WRITE: + if (arRawIfEnabled(ar)) { + unsigned int streamID; + get_user(streamID, (unsigned int *)userdata); + get_user(length, (unsigned int *)userdata + 1); + buffer = userdata + sizeof(streamID) + sizeof(length); + ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID, + buffer, length); + put_user(ret, (unsigned int *)rq->ifr_data); + } else { + ret = A_ERROR; + } + break; +#endif /* HTC_RAW_INTERFACE */ + + case AR6000_XIOCTL_BMI_LZ_STREAM_START: + get_user(address, (unsigned int *)userdata); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Start Compressed Stream (address: 0x%x)\n", address)); + ret = BMILZStreamStart(hifDevice, address); + break; + + case AR6000_XIOCTL_BMI_LZ_DATA: + get_user(length, (unsigned int *)userdata); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Send Compressed Data (length: %d)\n", length)); + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(length)], length)) + { + ret = -EFAULT; + } else { + ret = BMILZData(hifDevice, buffer, length); + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + break; + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + /* + * Optional support for Target-side profiling. + * Not needed in production. + */ + + /* Configure Target-side profiling */ + case AR6000_XIOCTL_PROF_CFG: + { + A_UINT32 period; + A_UINT32 nbins; + get_user(period, (unsigned int *)userdata); + get_user(nbins, (unsigned int *)userdata + 1); + + if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != A_OK) { + ret = -EIO; + } + + break; + } + + /* Start a profiling bucket/bin at the specified address */ + case AR6000_XIOCTL_PROF_ADDR_SET: + { + A_UINT32 addr; + get_user(addr, (unsigned int *)userdata); + + if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != A_OK) { + ret = -EIO; + } + + break; + } + + /* START Target-side profiling */ + case AR6000_XIOCTL_PROF_START: + wmi_prof_start_cmd(ar->arWmi); + break; + + /* STOP Target-side profiling */ + case AR6000_XIOCTL_PROF_STOP: + wmi_prof_stop_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_PROF_COUNT_GET: + { + if (ar->bIsDestroyProgress) { + ret = -EBUSY; + goto ioctl_done; + } + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + if (down_interruptible(&ar->arSem)) { + ret = -ERESTARTSYS; + goto ioctl_done; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + ret = -EBUSY; + goto ioctl_done; + } + + prof_count_available = FALSE; + ret = prof_count_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + ret = -EIO; + goto ioctl_done; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, prof_count_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &prof_count_results, + sizeof(prof_count_results))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + + case AR6000_IOCTL_WMI_GETREV: + { + if (copy_to_user(rq->ifr_data, &ar->arVersion, + sizeof(ar->arVersion))) + { + ret = -EFAULT; + } + break; + } + case AR6000_IOCTL_WMI_SETPWR: + { + WMI_POWER_MODE_CMD pwrModeCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pwrModeCmd, userdata, + sizeof(pwrModeCmd))) + { + ret = -EFAULT; + } else { + if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode) + != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS: + { + WMI_IBSS_PM_CAPS_CMD ibssPmCaps; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&ibssPmCaps, userdata, + sizeof(ibssPmCaps))) + { + ret = -EFAULT; + } else { + if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl, + ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arIbssPsEnable = ibssPmCaps.power_saving; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_XIOCTL_WMI_SET_AP_PS: + { + WMI_AP_PS_CMD apPsCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&apPsCmd, userdata, + sizeof(apPsCmd))) + { + ret = -EFAULT; + } else { + if (wmi_apps_cmd(ar->arWmi, apPsCmd.psType, apPsCmd.idle_time, + apPsCmd.ps_period, apPsCmd.sleep_period) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_PMPARAMS: + { + WMI_POWER_PARAMS_CMD pmParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&pmParams, userdata, + sizeof(pmParams))) + { + ret = -EFAULT; + } else { + if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period, + pmParams.pspoll_number, + pmParams.dtim_policy, + pmParams.tx_wakeup_policy, + pmParams.num_tx_to_wakeup, +#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN + IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN +#else + SEND_POWER_SAVE_FAIL_EVENT_ALWAYS +#endif + ) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETSCAN: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&ar->scParams, userdata, + sizeof(ar->scParams))) + { + ret = -EFAULT; + } else { + if (CAN_SCAN_IN_CONNECT(ar->scParams.scanCtrlFlags)) { + ar->arSkipScan = FALSE; + } else { + ar->arSkipScan = TRUE; + } + + if (wmi_scanparams_cmd(ar->arWmi, ar->scParams.fg_start_period, + ar->scParams.fg_end_period, + ar->scParams.bg_period, + ar->scParams.minact_chdwell_time, + ar->scParams.maxact_chdwell_time, + ar->scParams.pas_chdwell_time, + ar->scParams.shortScanRatio, + ar->scParams.scanCtrlFlags, + ar->scParams.max_dfsch_act_time, + ar->scParams.maxact_scan_per_ssid) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETLISTENINT: + { + WMI_LISTEN_INT_CMD listenCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&listenCmd, userdata, + sizeof(listenCmd))) + { + ret = -EFAULT; + } else { + if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) { + ret = -EIO; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arListenInterval = param; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + + } + break; + } + case AR6000_IOCTL_WMI_SET_BMISS_TIME: + { + WMI_BMISS_TIME_CMD bmissCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bmissCmd, userdata, + sizeof(bmissCmd))) + { + ret = -EFAULT; + } else { + if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_IOCTL_WMI_SETBSSFILTER: + { + WMI_BSS_FILTER_CMD filt; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&filt, userdata, + sizeof(filt))) + { + ret = -EFAULT; + } else { + if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask) + != A_OK) { + ret = -EIO; + } else { + ar->arUserBssFilter = param; + } + } + break; + } + case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD: + { + ret = ar6000_ioctl_set_snr_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD: + { + ret = ar6000_ioctl_set_rssi_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_CLR_RSSISNR: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_clr_rssi_snr(ar->arWmi); + break; + } + case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD: + { + ret = ar6000_ioctl_set_lq_threshold(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_LPREAMBLE: + { + WMI_SET_LPREAMBLE_CMD setLpreambleCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setLpreambleCmd, userdata, + sizeof(setLpreambleCmd))) + { + ret = -EFAULT; + } else { + if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status, +#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP + WMI_DONOT_IGNORE_BARKER_IN_ERP +#else + WMI_IGNORE_BARKER_IN_ERP +#endif + ) != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_RTS: + { + WMI_SET_RTS_CMD rtsCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&rtsCmd, userdata, + sizeof(rtsCmd))) + { + ret = -EFAULT; + } else { + ar->arRTS = rtsCmd.threshold; + if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold) + != A_OK) + { + ret = -EIO; + } + } + + break; + } + case AR6000_XIOCTL_WMI_SET_WMM: + { + ret = ar6000_ioctl_set_wmm(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_QOS_SUPP: + { + ret = ar6000_ioctl_set_qos_supp(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_SET_TXOP: + { + ret = ar6000_ioctl_set_txop(dev, rq); + break; + } + case AR6000_XIOCTL_WMI_GET_RD: + { + ret = ar6000_ioctl_get_rd(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_CHANNELPARAMS: + { + ret = ar6000_ioctl_set_channelParams(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_PROBEDSSID: + { + ret = ar6000_ioctl_set_probedSsid(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_BADAP: + { + ret = ar6000_ioctl_set_badAp(dev, rq); + break; + } + case AR6000_IOCTL_WMI_CREATE_QOS: + { + ret = ar6000_ioctl_create_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_DELETE_QOS: + { + ret = ar6000_ioctl_delete_qos(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_QOS_QUEUE: + { + ret = ar6000_ioctl_get_qos_queue(dev, rq); + break; + } + case AR6000_IOCTL_WMI_GET_TARGET_STATS: + { + ret = ar6000_ioctl_get_target_stats(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK: + { + ret = ar6000_ioctl_set_error_report_bitmask(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_ASSOC_INFO: + { + WMI_SET_ASSOC_INFO_CMD cmd; + A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + get_user(cmd.ieType, userdata); + if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) { + ret = -EIO; + } else { + get_user(cmd.bufferSize, userdata + 1); + if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) { + ret = -EFAULT; + break; + } + if (copy_from_user(assocInfo, userdata + 2, + cmd.bufferSize)) + { + ret = -EFAULT; + } else { + if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType, + cmd.bufferSize, + assocInfo) != A_OK) + { + ret = -EIO; + } + } + } + } + break; + } + case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS: + { + ret = ar6000_ioctl_set_access_params(dev, rq); + break; + } + case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT: + { + ret = ar6000_ioctl_set_disconnect_timeout(dev, rq); + break; + } + case AR6000_XIOCTL_FORCE_TARGET_RESET: + { + if (ar->arHtcTarget) + { +// HTCForceReset(htcTarget); + } + else + { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("ar6000_ioctl cannot attempt reset.\n")); + } + break; + } + case AR6000_XIOCTL_TARGET_INFO: + case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */ + { + /* If we made it to here, then the Target exists and is ready. */ + + if (cmd == AR6000_XIOCTL_TARGET_INFO) { + if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver, + sizeof(ar->arVersion.target_ver))) + { + ret = -EFAULT; + } + if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType, + sizeof(ar->arTargetType))) + { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS: + { + WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam; + + if (copy_from_user(&hbparam, userdata, sizeof(hbparam))) + { + ret = -EFAULT; + } else { + AR6000_SPIN_LOCK(&ar->arLock, 0); + /* Start a cyclic timer with the parameters provided. */ + if (hbparam.frequency) { + ar->arHBChallengeResp.frequency = hbparam.frequency; + } + if (hbparam.threshold) { + ar->arHBChallengeResp.missThres = hbparam.threshold; + } + + /* Delete the pending timer and start a new one */ + if (timer_pending(&ar->arHBChallengeResp.timer)) { + A_UNTIMEOUT(&ar->arHBChallengeResp.timer); + } + A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0); + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP: + { + A_UINT32 cookie; + + if (copy_from_user(&cookie, userdata, sizeof(cookie))) { + ret = -EFAULT; + goto ioctl_done; + } + + /* Send the challenge on the control channel */ + if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) { + ret = -EIO; + goto ioctl_done; + } + break; + } +#ifdef USER_KEYS + case AR6000_XIOCTL_USER_SETKEYS: + { + + ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN; + + if (copy_from_user(&ar->user_key_ctrl, userdata, + sizeof(ar->user_key_ctrl))) + { + ret = -EFAULT; + goto ioctl_done; + } + + A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl); + break; + } +#endif /* USER_KEYS */ + +#ifdef CONFIG_HOST_GPIO_SUPPORT + case AR6000_XIOCTL_GPIO_OUTPUT_SET: + { + struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd; + + if (ar->bIsDestroyProgress) { + ret = -EBUSY; + goto ioctl_done; + } + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + if (down_interruptible(&ar->arSem)) { + ret = -ERESTARTSYS; + goto ioctl_done; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + ret = -EBUSY; + goto ioctl_done; + } + + if (copy_from_user(&gpio_output_set_cmd, userdata, + sizeof(gpio_output_set_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_output_set(dev, + gpio_output_set_cmd.set_mask, + gpio_output_set_cmd.clear_mask, + gpio_output_set_cmd.enable_mask, + gpio_output_set_cmd.disable_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INPUT_GET: + { + if (ar->bIsDestroyProgress) { + ret = -EBUSY; + goto ioctl_done; + } + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + if (down_interruptible(&ar->arSem)) { + ret = -ERESTARTSYS; + goto ioctl_done; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + ret = -EBUSY; + goto ioctl_done; + } + + ret = ar6000_gpio_input_get(dev); + if (ret != A_OK) { + up(&ar->arSem); + ret = -EIO; + goto ioctl_done; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE); + + if (copy_to_user(userdata, &gpio_reg_results.value, + sizeof(gpio_reg_results.value))) + { + ret = -EFAULT; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_SET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->bIsDestroyProgress) { + ret = -EBUSY; + goto ioctl_done; + } + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + if (down_interruptible(&ar->arSem)) { + ret = -ERESTARTSYS; + goto ioctl_done; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + ret = -EBUSY; + goto ioctl_done; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_set(dev, + gpio_register_cmd.gpioreg_id, + gpio_register_cmd.value); + if (ret != A_OK) { + ret = EIO; + } + + /* Wait for acknowledgement from Target */ + wait_event_interruptible(arEvent, gpio_ack_received); + if (signal_pending(current)) { + ret = -EINTR; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_REGISTER_GET: + { + struct ar6000_gpio_register_cmd_s gpio_register_cmd; + + if (ar->bIsDestroyProgress) { + ret = -EBUSY; + goto ioctl_done; + } + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + if (down_interruptible(&ar->arSem)) { + ret = -ERESTARTSYS; + goto ioctl_done; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + ret = -EBUSY; + goto ioctl_done; + } + + if (copy_from_user(&gpio_register_cmd, userdata, + sizeof(gpio_register_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id); + if (ret != A_OK) { + up(&ar->arSem); + ret = -EIO; + goto ioctl_done; + } + + /* Wait for Target to respond. */ + wait_event_interruptible(arEvent, gpio_data_available); + if (signal_pending(current)) { + ret = -EINTR; + } else { + A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id); + if (copy_to_user(userdata, &gpio_reg_results, + sizeof(gpio_reg_results))) + { + ret = -EFAULT; + } + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_ACK: + { + struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd; + + if (ar->bIsDestroyProgress) { + ret = -EBUSY; + goto ioctl_done; + } + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + if (down_interruptible(&ar->arSem)) { + ret = -ERESTARTSYS; + goto ioctl_done; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + ret = -EBUSY; + goto ioctl_done; + } + + if (copy_from_user(&gpio_intr_ack_cmd, userdata, + sizeof(gpio_intr_ack_cmd))) + { + ret = -EFAULT; + } else { + ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask); + if (ret != A_OK) { + ret = EIO; + } + } + up(&ar->arSem); + break; + } + case AR6000_XIOCTL_GPIO_INTR_WAIT: + { + /* Wait for Target to report an interrupt. */ + wait_event_interruptible(arEvent, gpio_intr_available); + + if (signal_pending(current)) { + ret = -EINTR; + } else { + if (copy_to_user(userdata, &gpio_intr_results, + sizeof(gpio_intr_results))) + { + ret = -EFAULT; + } + } + break; + } +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + + case AR6000_XIOCTL_DBGLOG_CFG_MODULE: + { + struct ar6000_dbglog_module_config_s config; + + if (copy_from_user(&config, userdata, sizeof(config))) { + ret = -EFAULT; + goto ioctl_done; + } + + /* Send the challenge on the control channel */ + if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask, + config.tsr, config.rep, + config.size, config.valid) != A_OK) + { + ret = -EIO; + goto ioctl_done; + } + break; + } + + case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS: + { + /* Send the challenge on the control channel */ + if (ar6000_dbglog_get_debug_logs(ar) != A_OK) + { + ret = -EIO; + goto ioctl_done; + } + break; + } + + case AR6000_XIOCTL_SET_ADHOC_BSSID: + { + WMI_SET_ADHOC_BSSID_CMD adhocBssid; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&adhocBssid, userdata, + sizeof(adhocBssid))) + { + ret = -EFAULT; + } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac, + AR6000_ETH_ADDR_LEN) == 0) + { + ret = -EFAULT; + } else { + + A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid)); + } + break; + } + + case AR6000_XIOCTL_SET_OPT_MODE: + { + WMI_SET_OPT_MODE_CMD optModeCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optModeCmd, userdata, + sizeof(optModeCmd))) + { + ret = -EFAULT; + } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) { + ret = -EFAULT; + + } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode) + != A_OK) + { + ret = -EIO; + } + break; + } + + case AR6000_XIOCTL_OPT_SEND_FRAME: + { + WMI_OPT_TX_FRAME_CMD optTxFrmCmd; + A_UINT8 data[MAX_OPT_DATA_LEN]; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&optTxFrmCmd, userdata, + sizeof(optTxFrmCmd))) + { + ret = -EFAULT; + } else if (copy_from_user(data, + userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1, + optTxFrmCmd.optIEDataLen)) + { + ret = -EFAULT; + } else { + ret = wmi_opt_tx_frame_cmd(ar->arWmi, + optTxFrmCmd.frmType, + optTxFrmCmd.dstAddr, + optTxFrmCmd.bssid, + optTxFrmCmd.optIEDataLen, + data); + } + + break; + } + case AR6000_XIOCTL_WMI_SETRETRYLIMITS: + { + WMI_SET_RETRY_LIMITS_CMD setRetryParams; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setRetryParams, userdata, + sizeof(setRetryParams))) + { + ret = -EFAULT; + } else { + if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType, + setRetryParams.trafficClass, + setRetryParams.maxRetries, + setRetryParams.enableNotify) != A_OK) + { + ret = -EIO; + } + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMaxRetries = setRetryParams.maxRetries; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + } + break; + } + + case AR6000_XIOCTL_SET_BEACON_INTVAL: + { + WMI_BEACON_INT_CMD bIntvlCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bIntvlCmd, userdata, + sizeof(bIntvlCmd))) + { + ret = -EFAULT; + } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval) + != A_OK) + { + ret = -EIO; + } + if(ret == 0) { + ar->ap_beacon_interval = bIntvlCmd.beaconInterval; + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + break; + } + case IEEE80211_IOCTL_SETAUTHALG: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + struct ieee80211req_authalg req; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&req, userdata, + sizeof(struct ieee80211req_authalg))) + { + ret = -EFAULT; + } else { + if (req.auth_alg & AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode |= OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + } + if (req.auth_alg & AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode |= SHARED_AUTH; + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + ar->arAuthMode = NONE_AUTH; + } + if (req.auth_alg == AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + } + } + break; + } + + case AR6000_XIOCTL_SET_VOICE_PKT_SIZE: + ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata); + break; + + case AR6000_XIOCTL_SET_MAX_SP: + ret = ar6000_xioctl_set_max_sp_len(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_GET_ROAM_TBL: + ret = ar6000_ioctl_get_roam_tbl(dev, rq); + break; + case AR6000_XIOCTL_WMI_SET_ROAM_CTRL: + ret = ar6000_ioctl_set_roam_ctrl(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS: + ret = ar6000_ioctl_set_powersave_timers(dev, userdata); + break; + case AR6000_XIOCTRL_WMI_GET_POWER_MODE: + ret = ar6000_ioctl_get_power_mode(dev, rq); + break; + case AR6000_XIOCTRL_WMI_SET_WLAN_STATE: + { + AR6000_WLAN_STATE state; + get_user(state, (unsigned int *)userdata); + if (ar6000_set_wlan_state(ar, state)!=A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_WMI_GET_ROAM_DATA: + ret = ar6000_ioctl_get_roam_data(dev, rq); + break; + + case AR6000_XIOCTL_WMI_SET_BT_STATUS: + ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BT_PARAMS: + ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT: + ret = ar6000_xioctl_set_btcoex_fe_ant_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV: + ret = ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG: + ret = ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG: + ret = ar6000_xioctl_set_btcoex_sco_config_cmd( dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG: + ret = ar6000_xioctl_set_btcoex_a2dp_config_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG: + ret = ar6000_xioctl_set_btcoex_aclcoex_config_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG: + ret = ar60000_xioctl_set_btcoex_debug_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS: + ret = ar6000_xioctl_set_btcoex_bt_operating_status_cmd(dev, userdata); + break; + + case AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG: + ret = ar6000_xioctl_get_btcoex_config_cmd(dev, userdata, rq); + break; + + case AR6000_XIOCTL_WMI_GET_BTCOEX_STATS: + ret = ar6000_xioctl_get_btcoex_stats_cmd(dev, userdata, rq); + break; + + case AR6000_XIOCTL_WMI_STARTSCAN: + { + WMI_START_SCAN_CMD setStartScanCmd, *cmdp; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setStartScanCmd, userdata, + sizeof(setStartScanCmd))) + { + ret = -EFAULT; + } else { + if (setStartScanCmd.numChannels > 1) { + cmdp = A_MALLOC(130); + if (copy_from_user(cmdp, userdata, + sizeof (*cmdp) + + ((setStartScanCmd.numChannels - 1) * + sizeof(A_UINT16)))) + { + kfree(cmdp); + ret = -EFAULT; + goto ioctl_done; + } + } else { + cmdp = &setStartScanCmd; + } + + if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType, + cmdp->forceFgScan, + cmdp->isLegacy, + cmdp->homeDwellTime, + cmdp->forceScanInterval, + cmdp->numChannels, + cmdp->channelList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SETFIXRATES: + { + WMI_FIX_RATES_CMD setFixRatesCmd; + A_STATUS returnStatus; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setFixRatesCmd, userdata, + sizeof(setFixRatesCmd))) + { + ret = -EFAULT; + } else { + returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask); + if (returnStatus == A_EINVAL) { + ret = -EINVAL; + } else if(returnStatus != A_OK) { + ret = -EIO; + } else { + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + } + break; + } + + case AR6000_XIOCTL_WMI_GETFIXRATES: + { + WMI_FIX_RATES_CMD getFixRatesCmd; + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + int ret = 0; + + if (ar->bIsDestroyProgress) { + ret = -EBUSY; + goto ioctl_done; + } + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + + if (down_interruptible(&ar->arSem)) { + ret = -ERESTARTSYS; + goto ioctl_done; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + ret = -EBUSY; + goto ioctl_done; + } + /* Used copy_from_user/copy_to_user to access user space data */ + if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } else { + ar->arRateMask = 0xFFFFFFFF; + + if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + ret = -EIO; + goto ioctl_done; + } + + wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFFFFFF, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getFixRatesCmd.fixRateMask = ar->arRateMask; + } + + if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) { + ret = -EFAULT; + } + + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_AUTHMODE: + { + WMI_SET_AUTH_MODE_CMD setAuthMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setAuthMode, userdata, + sizeof(setAuthMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_REASSOCMODE: + { + WMI_SET_REASSOC_MODE_CMD setReassocMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setReassocMode, userdata, + sizeof(setReassocMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DIAG_READ: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + addr = TARG_VTOP(ar->arTargetType, addr); + if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + put_user(data, (unsigned int *)userdata + 1); + break; + } + case AR6000_XIOCTL_DIAG_WRITE: + { + A_UINT32 addr, data; + get_user(addr, (unsigned int *)userdata); + get_user(data, (unsigned int *)userdata + 1); + addr = TARG_VTOP(ar->arTargetType, addr); + if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_WMI_SET_KEEPALIVE: + { + WMI_SET_KEEPALIVE_CMD setKeepAlive; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } else if (copy_from_user(&setKeepAlive, userdata, + sizeof(setKeepAlive))){ + ret = -EFAULT; + } else { + if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_PARAMS: + { + WMI_SET_PARAMS_CMD cmd; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd) + cmd.length)) + { + ret = -EFAULT; + } else { + if (wmi_set_params_cmd(ar->arWmi, cmd.opcode, cmd.length, cmd.buffer) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER: + { + WMI_SET_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0], + cmd.multicast_mac[1], + cmd.multicast_mac[2], + cmd.multicast_mac[3]) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_MCAST_FILTER: + { + WMI_MCAST_FILTER_CMD cmd; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } else if (copy_from_user(&cmd, userdata, + sizeof(cmd))){ + ret = -EFAULT; + } else { + if (wmi_mcast_filter_cmd(ar->arWmi, cmd.enable) != A_OK) { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_KEEPALIVE: + { + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_GET_KEEPALIVE_CMD getKeepAlive; + int ret = 0; + if (ar->bIsDestroyProgress) { + ret =-EBUSY; + goto ioctl_done; + } + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + if (down_interruptible(&ar->arSem)) { + ret = -ERESTARTSYS; + goto ioctl_done; + } + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + ret = -EBUSY; + goto ioctl_done; + } + if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) { + ret = -EFAULT; + } else { + getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi); + ar->arKeepaliveConfigured = 0xFF; + if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){ + up(&ar->arSem); + ret = -EIO; + goto ioctl_done; + } + wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + + if (!ret) { + getKeepAlive.configured = ar->arKeepaliveConfigured; + } + if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) { + ret = -EFAULT; + } + up(&ar->arSem); + } + break; + } + case AR6000_XIOCTL_WMI_SET_APPIE: + { + WMI_SET_APPIE_CMD appIEcmd; + A_UINT8 appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN]; + A_UINT32 fType,ieLen; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } + get_user(fType, (A_UINT32 *)userdata); + appIEcmd.mgmtFrmType = fType; + if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) { + ret = -EIO; + } else { + get_user(ieLen, (A_UINT32 *)(userdata + 4)); + appIEcmd.ieLen = ieLen; + A_PRINTF("WPSIE: Type-%d, Len-%d\n",appIEcmd.mgmtFrmType, appIEcmd.ieLen); + if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) { + ret = -EIO; + break; + } + if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) { + ret = -EFAULT; + } else { + if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType, + appIEcmd.ieLen, appIeInfo) != A_OK) + { + ret = -EIO; + } + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER: + { + WMI_BSS_FILTER_CMD cmd; + A_UINT32 filterType; + + if (copy_from_user(&filterType, userdata, sizeof(A_UINT32))) + { + ret = -EFAULT; + goto ioctl_done; + } + if (filterType & (IEEE80211_FILTER_TYPE_BEACON | + IEEE80211_FILTER_TYPE_PROBE_RESP)) + { + cmd.bssFilter = ALL_BSS_FILTER; + } else { + cmd.bssFilter = NONE_BSS_FILTER; + } + if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) { + ret = -EIO; + } else { + ar->arUserBssFilter = cmd.bssFilter; + } + + AR6000_SPIN_LOCK(&ar->arLock, 0); + ar->arMgmtFilter = filterType; + AR6000_SPIN_UNLOCK(&ar->arLock, 0); + break; + } + case AR6000_XIOCTL_WMI_SET_WSC_STATUS: + { + A_UINT32 wsc_status; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + goto ioctl_done; + } else if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32))) + { + ret = -EFAULT; + goto ioctl_done; + } + if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) { + ret = -EIO; + } + break; + } + case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL: + { + A_UINT32 ROM_addr; + A_UINT32 RAM_addr; + A_UINT32 nbytes; + A_UINT32 do_activate; + A_UINT32 rompatch_id; + + get_user(ROM_addr, (A_UINT32 *)userdata); + get_user(RAM_addr, (A_UINT32 *)userdata + 1); + get_user(nbytes, (A_UINT32 *)userdata + 2); + get_user(do_activate, (A_UINT32 *)userdata + 3); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Install rompatch from ROM: 0x%x to RAM: 0x%x length: %d\n", + ROM_addr, RAM_addr, nbytes)); + ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr, + nbytes, do_activate, &rompatch_id); + if (ret == A_OK) { + put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */ + } + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL: + { + A_UINT32 rompatch_id; + + get_user(rompatch_id, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("UNinstall rompatch_id %d\n", rompatch_id)); + ret = BMIrompatchUninstall(hifDevice, rompatch_id); + break; + } + + case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE: + case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE: + { + A_UINT32 rompatch_count; + + get_user(rompatch_count, (A_UINT32 *)userdata); + AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Change rompatch activation count=%d\n", rompatch_count)); + length = sizeof(A_UINT32) * rompatch_count; + if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) { + A_MEMZERO(buffer, length); + if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length)) + { + ret = -EFAULT; + } else { + if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) { + ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } else { + ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer); + } + } + A_FREE(buffer); + } else { + ret = -ENOMEM; + } + + break; + } + case AR6000_XIOCTL_SET_IP: + { + WMI_SET_IP_CMD setIP; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setIP, userdata, + sizeof(setIP))) + { + ret = -EFAULT; + } else { + if (wmi_set_ip_cmd(ar->arWmi, + &setIP) != A_OK) + { + ret = -EIO; + } + } + break; + } + + case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE: + { + WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setHostSleepMode, userdata, + sizeof(setHostSleepMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_host_sleep_mode_cmd(ar->arWmi, + &setHostSleepMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_SET_WOW_MODE: + { + WMI_SET_WOW_MODE_CMD setWowMode; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&setWowMode, userdata, + sizeof(setWowMode))) + { + ret = -EFAULT; + } else { + if (wmi_set_wow_mode_cmd(ar->arWmi, + &setWowMode) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_GET_WOW_LIST: + { + WMI_GET_WOW_LIST_CMD getWowList; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&getWowList, userdata, + sizeof(getWowList))) + { + ret = -EFAULT; + } else { + if (wmi_get_wow_list_cmd(ar->arWmi, + &getWowList) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN: + { +#define WOW_PATTERN_SIZE 64 +#define WOW_MASK_SIZE 64 + + WMI_ADD_WOW_PATTERN_CMD cmd; + A_UINT8 mask_data[WOW_PATTERN_SIZE]={0}; + A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0}; + + do { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + break; + } + if(copy_from_user(&cmd, userdata, + sizeof(WMI_ADD_WOW_PATTERN_CMD))) + { + ret = -EFAULT; + break; + } + if (copy_from_user(pattern_data, + userdata + 3, + cmd.filter_size)) + { + ret = -EFAULT; + break; + } + if (copy_from_user(mask_data, + (userdata + 3 + cmd.filter_size), + cmd.filter_size)) + { + ret = -EFAULT; + break; + } + if (wmi_add_wow_pattern_cmd(ar->arWmi, + &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK) + { + ret = -EIO; + } + } while(FALSE); +#undef WOW_PATTERN_SIZE +#undef WOW_MASK_SIZE + break; + } + case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN: + { + WMI_DEL_WOW_PATTERN_CMD delWowPattern; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&delWowPattern, userdata, + sizeof(delWowPattern))) + { + ret = -EFAULT; + } else { + if (wmi_del_wow_pattern_cmd(ar->arWmi, + &delWowPattern) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE: + if (ar->arHtcTarget != NULL) { + HTCDumpCreditStates(ar->arHtcTarget); +#ifdef HTC_EP_STAT_PROFILING + { + HTC_ENDPOINT_STATS stats; + int i; + + for (i = 0; i < 5; i++) { + if (HTCGetEndpointStatistics(ar->arHtcTarget, + i, + HTC_EP_STAT_SAMPLE_AND_CLEAR, + &stats)) { + A_PRINTF(KERN_ALERT"------- Profiling Endpoint : %d \n", i); + A_PRINTF(KERN_ALERT"TxCreditLowIndications : %d \n", stats.TxCreditLowIndications); + A_PRINTF(KERN_ALERT"TxIssued : %d \n", stats.TxIssued); + A_PRINTF(KERN_ALERT"TxDropped: %d \n", stats.TxDropped); + A_PRINTF(KERN_ALERT"TxPacketsBundled : %d \n", stats.TxPacketsBundled); + A_PRINTF(KERN_ALERT"TxBundles : %d \n", stats.TxBundles); + A_PRINTF(KERN_ALERT"TxCreditRpts : %d \n", stats.TxCreditRpts); + A_PRINTF(KERN_ALERT"TxCreditsRptsFromRx : %d \n", stats.TxCreditRptsFromRx); + A_PRINTF(KERN_ALERT"TxCreditsRptsFromOther : %d \n", stats.TxCreditRptsFromOther); + A_PRINTF(KERN_ALERT"TxCreditsRptsFromEp0 : %d \n", stats.TxCreditRptsFromEp0); + A_PRINTF(KERN_ALERT"TxCreditsFromRx : %d \n", stats.TxCreditsFromRx); + A_PRINTF(KERN_ALERT"TxCreditsFromOther : %d \n", stats.TxCreditsFromOther); + A_PRINTF(KERN_ALERT"TxCreditsFromEp0 : %d \n", stats.TxCreditsFromEp0); + A_PRINTF(KERN_ALERT"TxCreditsConsummed : %d \n", stats.TxCreditsConsummed); + A_PRINTF(KERN_ALERT"TxCreditsReturned : %d \n", stats.TxCreditsReturned); + A_PRINTF(KERN_ALERT"RxReceived : %d \n", stats.RxReceived); + A_PRINTF(KERN_ALERT"RxPacketsBundled : %d \n", stats.RxPacketsBundled); + A_PRINTF(KERN_ALERT"RxLookAheads : %d \n", stats.RxLookAheads); + A_PRINTF(KERN_ALERT"RxBundleLookAheads : %d \n", stats.RxBundleLookAheads); + A_PRINTF(KERN_ALERT"RxBundleIndFromHdr : %d \n", stats.RxBundleIndFromHdr); + A_PRINTF(KERN_ALERT"RxAllocThreshHit : %d \n", stats.RxAllocThreshHit); + A_PRINTF(KERN_ALERT"RxAllocThreshBytes : %d \n", stats.RxAllocThreshBytes); + A_PRINTF(KERN_ALERT"---- \n"); + + } + } + } +#endif + } + break; + case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE: + if (ar->arHtcTarget != NULL) { + struct ar6000_traffic_activity_change data; + + if (copy_from_user(&data, userdata, sizeof(data))) + { + ret = -EFAULT; + goto ioctl_done; + } + /* note, this is used for testing (mbox ping testing), indicate activity + * change using the stream ID as the traffic class */ + ar6000_indicate_tx_activity(ar, + (A_UINT8)data.StreamID, + data.Active ? TRUE : FALSE); + } + break; + case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&connectCtrlFlags, userdata, + sizeof(connectCtrlFlags))) + { + ret = -EFAULT; + } else { + ar->arConnectCtrlFlags = connectCtrlFlags; + } + break; + case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&akmpParams, userdata, + sizeof(WMI_SET_AKMP_PARAMS_CMD))) + { + ret = -EFAULT; + } else { + if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_SET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (copy_from_user(&pmkidInfo.numPMKID, userdata, + sizeof(pmkidInfo.numPMKID))) + { + ret = -EFAULT; + break; + } + if (copy_from_user(&pmkidInfo.pmkidList, + userdata + sizeof(pmkidInfo.numPMKID), + pmkidInfo.numPMKID * sizeof(WMI_PMKID))) + { + ret = -EFAULT; + break; + } + if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_GET_PMKID_LIST: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) { + ret = -EIO; + } + } + break; + case AR6000_XIOCTL_WMI_ABORT_SCAN: + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + ret = wmi_abort_scan_cmd(ar->arWmi); + break; + case AR6000_XIOCTL_AP_HIDDEN_SSID: + { + A_UINT8 hidden_ssid; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&hidden_ssid, userdata, sizeof(hidden_ssid))) { + ret = -EFAULT; + } else { + wmi_ap_set_hidden_ssid(ar->arWmi, hidden_ssid); + ar->ap_hidden_ssid = hidden_ssid; + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + break; + } + case AR6000_XIOCTL_AP_GET_STA_LIST: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else { + A_UINT8 i; + ap_get_sta_t temp; + A_MEMZERO(&temp, sizeof(temp)); + for(i=0;ista_list[i].mac, ATH_MAC_LEN); + temp.sta[i].aid = ar->sta_list[i].aid; + temp.sta[i].keymgmt = ar->sta_list[i].keymgmt; + temp.sta[i].ucipher = ar->sta_list[i].ucipher; + temp.sta[i].auth = ar->sta_list[i].auth; + } + if(copy_to_user((ap_get_sta_t *)rq->ifr_data, &temp, + sizeof(ar->sta_list))) { + ret = -EFAULT; + } + } + break; + } + case AR6000_XIOCTL_AP_SET_NUM_STA: + { + A_UINT8 num_sta; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&num_sta, userdata, sizeof(num_sta))) { + ret = -EFAULT; + } else if(num_sta > AP_MAX_NUM_STA) { + /* value out of range */ + ret = -EINVAL; + } else { + wmi_ap_set_num_sta(ar->arWmi, num_sta); + } + break; + } + case AR6000_XIOCTL_AP_SET_ACL_POLICY: + { + A_UINT8 policy; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&policy, userdata, sizeof(policy))) { + ret = -EFAULT; + } else if(policy == ar->g_acl.policy) { + /* No change in policy */ + } else { + if(!(policy & AP_ACL_RETAIN_LIST_MASK)) { + /* clear ACL list */ + memset(&ar->g_acl,0,sizeof(WMI_AP_ACL)); + } + ar->g_acl.policy = policy; + wmi_ap_set_acl_policy(ar->arWmi, policy); + } + break; + } + case AR6000_XIOCTL_AP_SET_ACL_MAC: + { + WMI_AP_ACL_MAC_CMD acl; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&acl, userdata, sizeof(acl))) { + ret = -EFAULT; + } else { + if(acl_add_del_mac(&ar->g_acl, &acl)) { + wmi_ap_acl_mac_list(ar->arWmi, &acl); + } else { + A_PRINTF("ACL list error\n"); + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_AP_GET_ACL_LIST: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_AP_ACL *)rq->ifr_data, &ar->g_acl, + sizeof(WMI_AP_ACL))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_COMMIT_CONFIG: + { + ret = ar6000_ap_mode_profile_commit(ar); + break; + } + case IEEE80211_IOCTL_GETWPAIE: + { + struct ieee80211req_wpaie wpaie; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&wpaie, userdata, sizeof(wpaie))) { + ret = -EFAULT; + } else if (ar6000_ap_mode_get_wpa_ie(ar, &wpaie)) { + ret = -EFAULT; + } else if(copy_to_user(userdata, &wpaie, sizeof(wpaie))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_CONN_INACT_TIME: + { + A_UINT32 period; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&period, userdata, sizeof(period))) { + ret = -EFAULT; + } else { + wmi_ap_conn_inact_time(ar->arWmi, period); + } + break; + } + case AR6000_XIOCTL_AP_PROT_SCAN_TIME: + { + WMI_AP_PROT_SCAN_TIME_CMD bgscan; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&bgscan, userdata, sizeof(bgscan))) { + ret = -EFAULT; + } else { + wmi_ap_bgscan_time(ar->arWmi, bgscan.period_min, bgscan.dwell_ms); + } + break; + } + case AR6000_XIOCTL_AP_SET_COUNTRY: + { + ret = ar6000_ioctl_set_country(dev, rq); + break; + } + case AR6000_XIOCTL_AP_SET_DTIM: + { + WMI_AP_SET_DTIM_CMD d; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&d, userdata, sizeof(d))) { + ret = -EFAULT; + } else { + if(d.dtim > 0 && d.dtim < 11) { + ar->ap_dtim_period = d.dtim; + wmi_ap_set_dtim(ar->arWmi, d.dtim); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } else { + A_PRINTF("DTIM out of range. Valid range is [1-10]\n"); + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT: + { + WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } + if (copy_from_user(&evtCfgCmd, userdata, + sizeof(evtCfgCmd))) { + ret = -EFAULT; + break; + } + ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd); + break; + } + case AR6000_XIOCTL_AP_INTRA_BSS_COMM: + { + A_UINT8 intra=0; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&intra, userdata, sizeof(intra))) { + ret = -EFAULT; + } else { + ar->intra_bss = (intra?1:0); + } + break; + } + case AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO: + { + struct drv_debug_module_s moduleinfo; + + if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) { + ret = -EFAULT; + break; + } + + a_dump_module_debug_info_by_name(moduleinfo.modulename); + ret = 0; + break; + } + case AR6000_XIOCTL_MODULE_DEBUG_SET_MASK: + { + struct drv_debug_module_s moduleinfo; + + if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) { + ret = -EFAULT; + break; + } + + if (A_FAILED(a_set_module_mask(moduleinfo.modulename, moduleinfo.mask))) { + ret = -EFAULT; + } + + break; + } + case AR6000_XIOCTL_MODULE_DEBUG_GET_MASK: + { + struct drv_debug_module_s moduleinfo; + + if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) { + ret = -EFAULT; + break; + } + + if (A_FAILED(a_get_module_mask(moduleinfo.modulename, &moduleinfo.mask))) { + ret = -EFAULT; + break; + } + + if (copy_to_user(userdata, &moduleinfo, sizeof(moduleinfo))) { + ret = -EFAULT; + break; + } + + break; + } +#ifdef ATH_AR6K_11N_SUPPORT + case AR6000_XIOCTL_DUMP_RCV_AGGR_STATS: + { + PACKET_LOG *copy_of_pkt_log; + + aggr_dump_stats(ar->aggr_cntxt, ©_of_pkt_log); + if (copy_to_user(rq->ifr_data, copy_of_pkt_log, sizeof(PACKET_LOG))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_SETUP_AGGR: + { + WMI_ADDBA_REQ_CMD cmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + ret = -EFAULT; + } else { + wmi_setup_aggr_cmd(ar->arWmi, cmd.tid); + } + } + break; + + case AR6000_XIOCTL_DELE_AGGR: + { + WMI_DELBA_REQ_CMD cmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + ret = -EFAULT; + } else { + wmi_delete_aggr_cmd(ar->arWmi, cmd.tid, cmd.is_sender_initiator); + } + } + break; + + case AR6000_XIOCTL_ALLOW_AGGR: + { + WMI_ALLOW_AGGR_CMD cmd; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + ret = -EFAULT; + } else { + wmi_allow_aggr_cmd(ar->arWmi, cmd.tx_allow_aggr, cmd.rx_allow_aggr); + } + } + break; + + case AR6000_XIOCTL_SET_HT_CAP: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&htCap, userdata, + sizeof(htCap))) + { + ret = -EFAULT; + } else { + + if (wmi_set_ht_cap_cmd(ar->arWmi, &htCap) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_SET_HT_OP: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&htOp, userdata, + sizeof(htOp))) + { + ret = -EFAULT; + } else { + + if (wmi_set_ht_op_cmd(ar->arWmi, htOp.sta_chan_width) != A_OK) + { + ret = -EIO; + } + } + break; + } +#endif + case AR6000_XIOCTL_ACL_DATA: + { + void *osbuf = NULL; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (ar6000_create_acl_data_osbuf(dev, (A_UINT8*)userdata, &osbuf) != A_OK) { + ret = -EIO; + } else { + if (wmi_data_hdr_add(ar->arWmi, osbuf, DATA_MSGTYPE, 0, WMI_DATA_HDR_DATA_TYPE_ACL,0,NULL) != A_OK) { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("XIOCTL_ACL_DATA - wmi_data_hdr_add failed\n")); + } else { + /* Send data buffer over HTC */ + ar6000_acl_data_tx(osbuf, ar->arNetDev); + } + } + break; + } + case AR6000_XIOCTL_HCI_CMD: + { + char tmp_buf[512]; + A_INT8 i; + WMI_HCI_CMD *cmd = (WMI_HCI_CMD *)tmp_buf; + A_UINT8 size; + + size = sizeof(cmd->cmd_buf_sz); + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(cmd, userdata, size)) { + ret = -EFAULT; + } else if(copy_from_user(cmd->buf, userdata + size, cmd->cmd_buf_sz)) { + ret = -EFAULT; + } else { + if (wmi_send_hci_cmd(ar->arWmi, cmd->buf, cmd->cmd_buf_sz) != A_OK) { + ret = -EIO; + }else if(loghci) { + A_PRINTF_LOG("HCI Command To PAL --> \n"); + for(i = 0; i < cmd->cmd_buf_sz; i++) { + A_PRINTF_LOG("0x%02x ",cmd->buf[i]); + if((i % 10) == 0) { + A_PRINTF_LOG("\n"); + } + } + A_PRINTF_LOG("\n"); + A_PRINTF_LOG("==================================\n"); + } + } + break; + } + case AR6000_XIOCTL_WLAN_CONN_PRECEDENCE: + { + WMI_SET_BT_WLAN_CONN_PRECEDENCE cmd; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) { + ret = -EFAULT; + } else { + if (cmd.precedence == BT_WLAN_CONN_PRECDENCE_WLAN || + cmd.precedence == BT_WLAN_CONN_PRECDENCE_PAL) { + if ( wmi_set_wlan_conn_precedence_cmd(ar->arWmi, cmd.precedence) != A_OK) { + ret = -EIO; + } + } else { + ret = -EINVAL; + } + } + break; + } + case AR6000_XIOCTL_AP_GET_STAT: + { + ret = ar6000_ioctl_get_ap_stats(dev, rq); + break; + } + case AR6000_XIOCTL_SET_TX_SELECT_RATES: + { + WMI_SET_TX_SELECT_RATES_CMD masks; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&masks, userdata, + sizeof(masks))) + { + ret = -EFAULT; + } else { + + if (wmi_set_tx_select_rates_cmd(ar->arWmi, masks.rateMasks) != A_OK) + { + ret = -EIO; + } + } + break; + } + case AR6000_XIOCTL_AP_GET_HIDDEN_SSID: + { + WMI_AP_HIDDEN_SSID_CMD ssid; + ssid.hidden_ssid = ar->ap_hidden_ssid; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_AP_HIDDEN_SSID_CMD *)rq->ifr_data, + &ssid, sizeof(WMI_AP_HIDDEN_SSID_CMD))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_GET_COUNTRY: + { + WMI_AP_SET_COUNTRY_CMD cty; + A_MEMCPY(cty.countryCode, ar->ap_country_code, 3); + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_AP_SET_COUNTRY_CMD *)rq->ifr_data, + &cty, sizeof(WMI_AP_SET_COUNTRY_CMD))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_GET_WMODE: + { + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((A_UINT8 *)rq->ifr_data, + &ar->ap_wmode, sizeof(A_UINT8))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_GET_DTIM: + { + WMI_AP_SET_DTIM_CMD dtim; + dtim.dtim = ar->ap_dtim_period; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_AP_SET_DTIM_CMD *)rq->ifr_data, + &dtim, sizeof(WMI_AP_SET_DTIM_CMD))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_GET_BINTVL: + { + WMI_BEACON_INT_CMD bi; + bi.beaconInterval = ar->ap_beacon_interval; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_BEACON_INT_CMD *)rq->ifr_data, + &bi, sizeof(WMI_BEACON_INT_CMD))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_AP_GET_RTS: + { + WMI_SET_RTS_CMD rts; + rts.threshold = ar->arRTS; + + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if(copy_to_user((WMI_SET_RTS_CMD *)rq->ifr_data, + &rts, sizeof(WMI_SET_RTS_CMD))) { + ret = -EFAULT; + } + break; + } + case AR6000_XIOCTL_FETCH_TARGET_REGS: + { + A_UINT32 targregs[AR6003_FETCH_TARG_REGS_COUNT]; + + if (ar->arTargetType == TARGET_TYPE_AR6003) { + ar6k_FetchTargetRegs(hifDevice, targregs); + if (copy_to_user((A_UINT32 *)rq->ifr_data, &targregs, sizeof(targregs))) + { + ret = -EFAULT; + } + } else { + ret = -EOPNOTSUPP; + } + break; + } + case AR6000_XIOCTL_AP_SET_11BG_RATESET: + { + WMI_AP_SET_11BG_RATESET_CMD rate; + if (ar->arWmiReady == FALSE) { + ret = -EIO; + } else if (copy_from_user(&rate, userdata, sizeof(rate))) { + ret = -EFAULT; + } else { + wmi_ap_set_rateset(ar->arWmi, rate.rateset); + } + break; + } + default: + ret = -EOPNOTSUPP; + } + +ioctl_done: + rtnl_lock(); /* restore rtnl state */ + dev_put(dev); + + return ret; +} + +A_UINT8 mac_cmp_wild(A_UINT8 *mac, A_UINT8 *new_mac, A_UINT8 wild, A_UINT8 new_wild) +{ + A_UINT8 i; + + for(i=0;i=0;i--) + { + if(mac_cmp_wild(a->acl_mac[i], acl->mac, a->wildcard[i], + acl->wildcard)==0) + already_avail = i; + + if(!((1 << i) & a->index)) + free_slot = i; + } + + if(acl->action == ADD_MAC_ADDR) + { + /* Dont add mac if it is already available */ + if((already_avail >= 0) || (free_slot == -1)) + return 0; + + A_MEMCPY(a->acl_mac[free_slot], acl->mac, ATH_MAC_LEN); + a->index = a->index | (1 << free_slot); + acl->index = free_slot; + a->wildcard[free_slot] = acl->wildcard; + return 1; + } + else if(acl->action == DEL_MAC_ADDR) + { + if(acl->index > AP_ACL_SIZE) + return 0; + + if(!(a->index & (1 << acl->index))) + return 0; + + A_MEMZERO(a->acl_mac[acl->index],ATH_MAC_LEN); + a->index = a->index & ~(1 << acl->index); + a->wildcard[acl->index] = 0; + return 1; + } + + return 0; +} diff --git a/drivers/net/wireless/ath6kl/os/linux/netbuf.c b/drivers/net/wireless/ath6kl/os/linux/netbuf.c new file mode 100644 index 000000000000..62b26c540449 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/netbuf.c @@ -0,0 +1,233 @@ + +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ +#include +#include +#include +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include "htc_packet.h" + +#define AR6000_DATA_OFFSET 64 + +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt) +{ + skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt); +} + +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q) +{ + return((void *) skb_dequeue((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_len((struct sk_buff_head *) q)); +} + +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q) +{ + return(skb_queue_empty((struct sk_buff_head *) q)); +} + +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q) +{ + skb_queue_head_init((struct sk_buff_head *) q); +} + +void * +a_netbuf_alloc(int size) +{ + struct sk_buff *skb; + size += 2 * (A_GET_CACHE_LINE_BYTES()); /* add some cacheline space at front and back of buffer */ + skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size); + skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + A_GET_CACHE_LINE_BYTES()); + return ((void *)skb); +} + +/* + * Allocate an SKB w.o. any encapsulation requirement. + */ +void * +a_netbuf_alloc_raw(int size) +{ + struct sk_buff *skb; + + skb = dev_alloc_skb(size); + + return ((void *)skb); +} + +void +a_netbuf_free(void *bufPtr) +{ + struct sk_buff *skb = (struct sk_buff *)bufPtr; + + dev_kfree_skb(skb); +} + +A_UINT32 +a_netbuf_to_len(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->len); +} + +void * +a_netbuf_to_data(void *bufPtr) +{ + return (((struct sk_buff *)bufPtr)->data); +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_push(void *bufPtr, A_INT32 len) +{ + skb_push((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the beginning of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + skb_push((struct sk_buff *) bufPtr, len); + A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr + */ +A_STATUS +a_netbuf_put(void *bufPtr, A_INT32 len) +{ + skb_put((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Add len # of bytes to the end of the network buffer + * pointed to by bufPtr and also fill with data + */ +A_STATUS +a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len) +{ + char *start = (char*)(((struct sk_buff *)bufPtr)->data + + ((struct sk_buff *)bufPtr)->len); + skb_put((struct sk_buff *)bufPtr, len); + A_MEMCPY(start, srcPtr, len); + + return A_OK; +} + + +/* + * Trim the network buffer pointed to by bufPtr to len # of bytes + */ +A_STATUS +a_netbuf_setlen(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer. + */ +A_STATUS +a_netbuf_trim(void *bufPtr, A_INT32 len) +{ + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + +/* + * Chop of len # of bytes from the end of the buffer and return the data. + */ +A_STATUS +a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + char *start = (char*)(((struct sk_buff *)bufPtr)->data + + (((struct sk_buff *)bufPtr)->len - len)); + + A_MEMCPY(dstPtr, start, len); + skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len); + + return A_OK; +} + + +/* + * Returns the number of bytes available to a a_netbuf_push() + */ +A_INT32 +a_netbuf_headroom(void *bufPtr) +{ + return (skb_headroom((struct sk_buff *)bufPtr)); +} + +/* + * Removes specified number of bytes from the beginning of the buffer + */ +A_STATUS +a_netbuf_pull(void *bufPtr, A_INT32 len) +{ + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +/* + * Removes specified number of bytes from the beginning of the buffer + * and return the data + */ +A_STATUS +a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len) +{ + A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len); + skb_pull((struct sk_buff *)bufPtr, len); + + return A_OK; +} + +#ifdef EXPORT_HCI_BRIDGE_INTERFACE +EXPORT_SYMBOL(a_netbuf_to_data); +EXPORT_SYMBOL(a_netbuf_put); +EXPORT_SYMBOL(a_netbuf_pull); +EXPORT_SYMBOL(a_netbuf_alloc); +EXPORT_SYMBOL(a_netbuf_free); +#endif diff --git a/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c b/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c new file mode 100644 index 000000000000..9d17574aef09 --- /dev/null +++ b/drivers/net/wireless/ath6kl/os/linux/wireless_ext.c @@ -0,0 +1,2703 @@ +/* + * + * Copyright (c) 2004-2010 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#include "ar6000_drv.h" + +static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi); +extern unsigned int wmitimeout; +extern A_WAITQUEUE_HEAD arEvent; + +#if WIRELESS_EXT > 14 +/* + * Encode a WPA or RSN information element as a custom + * element using the hostap format. + */ +static u_int +encode_ie(void *buf, size_t bufsize, + const u_int8_t *ie, size_t ielen, + const char *leader, size_t leader_len) +{ + u_int8_t *p; + int i; + + if (bufsize < leader_len) + return 0; + p = buf; + memcpy(p, leader, leader_len); + bufsize -= leader_len; + p += leader_len; + for (i = 0; i < ielen && bufsize > 2; i++) + { + p += sprintf((char*)p, "%02x", ie[i]); + bufsize -= 2; + } + return (i == ielen ? p - (u_int8_t *)buf : 0); +} +#endif /* WIRELESS_EXT > 14 */ + +void +ar6000_scan_node(void *arg, bss_t *ni) +{ + struct iw_event iwe; +#if WIRELESS_EXT > 14 + char buf[256]; +#endif + struct ar_giwscan_param *param; + A_CHAR *current_ev; + A_CHAR *end_buf; + struct ieee80211_common_ie *cie; + A_CHAR *current_val; + A_INT32 j; + A_UINT32 rate_len, data_len = 0; + + param = (struct ar_giwscan_param *)arg; + + current_ev = param->current_ev; + end_buf = param->end_buf; + + cie = &ni->ni_cie; + + if ((end_buf - current_ev) > IW_EV_ADDR_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6); + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_ADDR_LEN); + } + param->bytes_needed += IW_EV_ADDR_LEN; + + data_len = cie->ie_ssid[1] + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWESSID; + iwe.u.data.flags = 1; + iwe.u.data.length = cie->ie_ssid[1]; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + (char*)&cie->ie_ssid[2]); + } + param->bytes_needed += data_len; + + if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) { + if ((end_buf - current_ev) > IW_EV_UINT_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWMODE; + iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ? + IW_MODE_MASTER : IW_MODE_ADHOC; + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_UINT_LEN); + } + param->bytes_needed += IW_EV_UINT_LEN; + } + + if ((end_buf - current_ev) > IW_EV_FREQ_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWFREQ; + iwe.u.freq.m = cie->ie_chan * 100000; + iwe.u.freq.e = 1; + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_FREQ_LEN); + } + param->bytes_needed += IW_EV_FREQ_LEN; + + if ((end_buf - current_ev) > IW_EV_QUAL_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + ar6000_set_quality(&iwe.u.qual, ni->ni_snr); + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, + IW_EV_QUAL_LEN); + } + param->bytes_needed += IW_EV_QUAL_LEN; + + if ((end_buf - current_ev) > IW_EV_POINT_LEN) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWENCODE; + if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) { + iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + } else { + iwe.u.data.flags = IW_ENCODE_DISABLED; + } + iwe.u.data.length = 0; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, ""); + } + param->bytes_needed += IW_EV_POINT_LEN; + + /* supported bit rate */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWRATE; + iwe.u.bitrate.fixed = 0; + iwe.u.bitrate.disabled = 0; + iwe.u.bitrate.value = 0; + current_val = current_ev + IW_EV_LCP_LEN; + param->bytes_needed += IW_EV_LCP_LEN; + + if (cie->ie_rates != NULL) { + rate_len = cie->ie_rates[1]; + data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN)); + if ((end_buf - current_ev) > data_len) + { + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_rates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_xrates != NULL) { + rate_len = cie->ie_xrates[1]; + data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN)); + if ((end_buf - current_ev) > data_len) + { + for (j = 0; j < rate_len; j++) { + unsigned char val; + val = cie->ie_xrates[2 + j]; + iwe.u.bitrate.value = + (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000); + current_val = iwe_stream_add_value( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, + current_val, + end_buf, + &iwe, + IW_EV_PARAM_LEN); + } + } + param->bytes_needed += data_len; + } + /* remove fixed header if no rates were added */ + if ((current_val - current_ev) > IW_EV_LCP_LEN) + current_ev = current_val; + +#if WIRELESS_EXT >= 18 + /* IE */ + if (cie->ie_wpa != NULL) { + data_len = cie->ie_wpa[1] + 2 + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wpa[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, (char*)cie->ie_wpa); + } + param->bytes_needed += data_len; + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + data_len = cie->ie_rsn[1] + 2 + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_rsn[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, (char*)cie->ie_rsn); + } + param->bytes_needed += data_len; + } + +#endif /* WIRELESS_EXT >= 18 */ + + if ((end_buf - current_ev) > IW_EV_CHAR_LEN) + { + /* protocol */ + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = SIOCGIWNAME; +#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484))) + if (CHAN_IS_11A(cie->ie_chan)) { + if (cie->ie_htcap) { + /* 11na */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11na"); + } + else { + /* 11a */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); + } + } else if ((cie->ie_erp) || (cie->ie_xrates)) { + if (cie->ie_htcap) { + /* 11ng */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11ng"); + } + else { + /* 11g */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); + } + } else { + /* 11b */ + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); + } + current_ev = iwe_stream_add_event( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, IW_EV_CHAR_LEN); + } + param->bytes_needed += IW_EV_CHAR_LEN; + +#if WIRELESS_EXT > 14 + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt); + data_len = iwe.u.data.length + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + param->bytes_needed += data_len; + +#if WIRELESS_EXT < 18 + if (cie->ie_wpa != NULL) { + static const char wpa_leader[] = "wpa_ie="; + data_len = (sizeof(wpa_leader) - 1) + ((cie->ie_wpa[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa, + cie->ie_wpa[1]+2, + wpa_leader, sizeof(wpa_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) { + static const char rsn_leader[] = "rsn_ie="; + data_len = (sizeof(rsn_leader) - 1) + ((cie->ie_rsn[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn, + cie->ie_rsn[1]+2, + rsn_leader, sizeof(rsn_leader)-1); + + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } +#endif /* WIRELESS_EXT < 18 */ + + if (cie->ie_wmm != NULL) { + static const char wmm_leader[] = "wmm_ie="; + data_len = (sizeof(wmm_leader) - 1) + ((cie->ie_wmm[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm, + cie->ie_wmm[1]+2, + wmm_leader, sizeof(wmm_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + + if (cie->ie_ath != NULL) { + static const char ath_leader[] = "ath_ie="; + data_len = (sizeof(ath_leader) - 1) + ((cie->ie_ath[1]+2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath, + cie->ie_ath[1]+2, + ath_leader, sizeof(ath_leader)-1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } + +#ifdef WAPI_ENABLE + if (cie->ie_wapi != NULL) { + static const char wapi_leader[] = "wapi_ie="; + data_len = (sizeof(wapi_leader) - 1) + ((cie->ie_wapi[1] + 2) * 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wapi, + cie->ie_wapi[1] + 2, + wapi_leader, sizeof(wapi_leader) - 1); + if (iwe.u.data.length != 0) { + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, buf); + } + } + param->bytes_needed += data_len; + } +#endif /* WAPI_ENABLE */ + +#endif /* WIRELESS_EXT > 14 */ + +#if WIRELESS_EXT >= 18 + if (cie->ie_wsc != NULL) { + data_len = (cie->ie_wsc[1] + 2) + IW_EV_POINT_LEN; + if ((end_buf - current_ev) > data_len) + { + A_MEMZERO(&iwe, sizeof(iwe)); + iwe.cmd = IWEVGENIE; + iwe.u.data.length = cie->ie_wsc[1] + 2; + current_ev = iwe_stream_add_point( +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param->info, +#endif + current_ev, end_buf, &iwe, (char*)cie->ie_wsc); + } + param->bytes_needed += data_len; + } +#endif /* WIRELESS_EXT >= 18 */ + + param->current_ev = current_ev; +} + +int +ar6000_ioctl_giwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + struct ar_giwscan_param param; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + param.current_ev = extra; + param.end_buf = extra + data->length; + param.bytes_needed = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) + param.info = info; +#endif + + /* Translate data to WE format */ + wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, ¶m); + + /* check if bytes needed is greater than bytes consumed */ + if (param.bytes_needed > (param.current_ev - extra)) + { + /* Request one byte more than needed, because when "data->length" equals bytes_needed, + it is not possible to add the last event data as all iwe_stream_add_xxxxx() functions + checks whether (cur_ptr + ev_len) < end_ptr, due to this one more retry would happen*/ + data->length = param.bytes_needed + 1; + + return -E2BIG; + } + + return 0; +} + +extern int reconnect_flag; +/* SIOCSIWESSID */ +static int +ar6000_ioctl_siwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *ssid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_STATUS status; + A_UINT8 arNetworkType; + A_UINT8 prevMode = ar->arNetworkType; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + +#if defined(WIRELESS_EXT) + if (WIRELESS_EXT >= 20) { + data->length += 1; + } +#endif + + /* + * iwconfig passes a null terminated string with length including this + * so we need to account for this + */ + if (data->flags && (!data->length || (data->length == 1) || + ((data->length - 1) > sizeof(ar->arSsid)))) + { + /* + * ssid is invalid + */ + return -EINVAL; + } + + if (ar->arNextMode == AP_NETWORK) { + /* SSID change for AP network - Will take effect on commit */ + if(A_MEMCMP(ar->arSsid,ssid,32) != 0) { + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + ar->ap_profile_flag = 1; /* There is a change in profile */ + } + return 0; + } else if(ar->arNetworkType == AP_NETWORK) { + A_UINT8 ctr; + struct sk_buff *skb; + + /* We are switching from AP to STA | IBSS mode, cleanup the AP state */ + for (ctr=0; ctr < AP_MAX_NUM_STA; ctr++) { + remove_sta(ar, ar->sta_list[ctr].mac, 0); + } + A_MUTEX_LOCK(&ar->mcastpsqLock); + while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) { + skb = A_NETBUF_DEQUEUE(&ar->mcastpsq); + A_NETBUF_FREE(skb); + } + A_MUTEX_UNLOCK(&ar->mcastpsqLock); + } + + /* Added for bug 25178, return an IOCTL error instead of target returning + Illegal parameter error when either the BSSID or channel is missing + and we cannot scan during connect. + */ + if (data->flags) { + if (ar->arSkipScan == TRUE && + (ar->arChannelHint == 0 || + (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] && + !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5]))) + { + return -EINVAL; + } + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) { + /* + * sleep until the command queue drains + */ + wait_event_interruptible_timeout(arEvent, + ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ); + if (signal_pending(current)) { + return -EINTR; + } + } + + if (!data->flags) { + arNetworkType = ar->arNetworkType; + ar6000_init_profile_info(ar); + ar->arNetworkType = arNetworkType; + } + + /* Update the arNetworkType */ + ar->arNetworkType = ar->arNextMode; + + + if ((prevMode != AP_NETWORK) && + ((ar->arSsidLen) || ((ar->arSsidLen == 0) && ar->arConnected) || (!data->flags))) + { + if ((!data->flags) || + (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) || + (ar->arSsidLen != (data->length - 1))) + { + /* + * SSID set previously or essid off has been issued. + * + * Disconnect Command is issued in two cases after wmi is ready + * (1) ssid is different from the previous setting + * (2) essid off has been issued + * + */ + if (ar->arWmiReady == TRUE) { + reconnect_flag = 0; + status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0); + status = wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + if (!data->flags) { + up(&ar->arSem); + return 0; + } + } else { + up(&ar->arSem); + } + } + else + { + /* + * SSID is same, so we assume profile hasn't changed. + * If the interface is up and wmi is ready, we issue + * a reconnect cmd. Issue a reconnect only we are already + * connected. + */ + if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE)) + { + reconnect_flag = TRUE; + status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid, + ar->arChannelHint); + up(&ar->arSem); + if (status != A_OK) { + return -EIO; + } + return 0; + } + else{ + /* + * Dont return if connect is pending. + */ + if(!(ar->arConnectPending)) { + up(&ar->arSem); + return 0; + } + } + } + } + + ar->arSsidLen = data->length - 1; + A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen); + + if (ar6000_connect_to_ap(ar)!= A_OK) { + up(&ar->arSem); + return -EIO; + }else{ + up(&ar->arSem); + } + return 0; +} + +/* SIOCGIWESSID */ +static int +ar6000_ioctl_giwessid(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *essid) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (!ar->arSsidLen) { + return -EINVAL; + } + + data->flags = 1; + data->length = ar->arSsidLen; + A_MEMCPY(essid, ar->arSsid, ar->arSsidLen); + + return 0; +} + + +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar) +{ + A_UINT8 index; + A_UINT8 keyUsage; + + for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) { + if (ar->arWepKeyList[index].arKeyLen) { + keyUsage = GROUP_USAGE; + if (index == ar->arDefTxKeyIndex) { + keyUsage |= TX_USAGE; + } + wmi_addKey_cmd(ar->arWmi, + index, + WEP_CRYPT, + keyUsage, + ar->arWepKeyList[index].arKeyLen, + NULL, + ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } +} + +/* + * SIOCSIWRATE + */ +int +ar6000_ioctl_siwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_UINT32 kbps; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + kbps = rrq->value / 1000; /* rrq->value is in bps */ + } else { + kbps = -1; /* -1 indicates auto rate */ + } + if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL) + { + AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BitRate is not Valid %d\n", kbps)); + return -EINVAL; + } + ar->arBitRate = kbps; + if(ar->arWmiReady == TRUE) + { + if (wmi_set_bitrate_cmd(ar->arWmi, kbps, -1, -1) != A_OK) { + return -EINVAL; + } + } + return 0; +} + +/* + * SIOCGIWRATE + */ +int +ar6000_ioctl_giwrate(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if(ar->arWmiReady == TRUE) + { + ar->arBitRate = 0xFFFF; + if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ); + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interface is down or wmi is not ready or the target is not + connected - return the value stored in the device structure */ + if (!ret) { + if (ar->arBitRate == -1) { + rrq->fixed = TRUE; + rrq->value = 0; + } else { + rrq->value = ar->arBitRate * 1000; + } + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWTXPOW + */ +static int +ar6000_ioctl_siwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_UINT8 dbM; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if (rrq->fixed) { + if (rrq->flags != IW_TXPOW_DBM) { + return -EOPNOTSUPP; + } + ar->arTxPwr= dbM = rrq->value; + ar->arTxPwrSet = TRUE; + } else { + ar->arTxPwr = dbM = 0; + ar->arTxPwrSet = FALSE; + } + if(ar->arWmiReady == TRUE) + { + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("Set tx pwr cmd %d dbM\n", dbM)); + wmi_set_txPwr_cmd(ar->arWmi, dbM); + } + return 0; +} + +/* + * SIOCGIWTXPOW + */ +int +ar6000_ioctl_giwtxpow(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE)) + { + ar->arTxPwr = 0; + + if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ); + + if (signal_pending(current)) { + ret = -EINTR; + } + } + /* If the interace is down or wmi is not ready or target is not connected + then return value stored in the device structure */ + + if (!ret) { + if (ar->arTxPwrSet == TRUE) { + rrq->fixed = TRUE; + } + rrq->value = ar->arTxPwr; + rrq->flags = IW_TXPOW_DBM; + // + // IWLIST need this flag to get TxPower + // + rrq->disabled = 0; + } + + up(&ar->arSem); + + return ret; +} + +/* + * SIOCSIWRETRY + * since iwconfig only provides us with one max retry value, we use it + * to apply to data frames of the BE traffic class. + */ +static int +ar6000_ioctl_siwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (rrq->disabled) { + return -EOPNOTSUPP; + } + + if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) { + return -EOPNOTSUPP; + } + + if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) { + return - EINVAL; + } + if(ar->arWmiReady == TRUE) + { + if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE, + rrq->value, 0) != A_OK){ + return -EINVAL; + } + } + ar->arMaxRetries = rrq->value; + return 0; +} + +/* + * SIOCGIWRETRY + */ +static int +ar6000_ioctl_giwretry(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *rrq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + rrq->disabled = 0; + switch (rrq->flags & IW_RETRY_TYPE) { + case IW_RETRY_LIFETIME: + return -EOPNOTSUPP; + break; + case IW_RETRY_LIMIT: + rrq->flags = IW_RETRY_LIMIT; + switch (rrq->flags & IW_RETRY_MODIFIER) { + case IW_RETRY_MIN: + rrq->flags |= IW_RETRY_MIN; + rrq->value = WMI_MIN_RETRIES; + break; + case IW_RETRY_MAX: + rrq->flags |= IW_RETRY_MAX; + rrq->value = ar->arMaxRetries; + break; + } + break; + } + return 0; +} + +/* + * SIOCSIWENCODE + */ +static int +ar6000_ioctl_siwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *keybuf) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + int index; + A_INT32 auth = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if(ar->arNextMode != AP_NETWORK) { + /* + * Static WEP Keys should be configured before setting the SSID + */ + if (ar->arSsid[0] && erq->length) { + return -EIO; + } + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + index = erq->flags & IW_ENCODE_INDEX; + + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) + { + return -EIO; + } + + if (erq->flags & IW_ENCODE_DISABLED) { + /* + * Encryption disabled + */ + if (index) { + /* + * If key index was specified then clear the specified key + */ + index--; + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + ar->arWepKeyList[index].arKeyLen = 0; + } + ar->arDot11AuthMode = OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arGroupCrypto = NONE_CRYPT; + ar->arAuthMode = NONE_AUTH; + } else { + /* + * Enabling WEP encryption + */ + if (index) { + index--; /* keyindex is off base 1 in iwconfig */ + } + + if (erq->flags & IW_ENCODE_OPEN) { + auth |= OPEN_AUTH; + ar->arDefTxKeyIndex = index; + } + if (erq->flags & IW_ENCODE_RESTRICTED) { + auth |= SHARED_AUTH; + } + + if (!auth) { + auth = OPEN_AUTH; + } + + if (erq->length) { + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) { + return -EIO; + } + + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length); + ar->arWepKeyList[index].arKeyLen = erq->length; + ar->arDot11AuthMode = auth; + } else { + if (ar->arWepKeyList[index].arKeyLen == 0) { + return -EIO; + } + ar->arDefTxKeyIndex = index; + + if(ar->arSsidLen && ar->arWepKeyList[index].arKeyLen) { + wmi_addKey_cmd(ar->arWmi, + index, + WEP_CRYPT, + GROUP_USAGE | TX_USAGE, + ar->arWepKeyList[index].arKeyLen, + NULL, + ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL, + NO_SYNC_WMIFLAG); + } + } + + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arGroupCrypto = WEP_CRYPT; + ar->arAuthMode = NONE_AUTH; + } + + if(ar->arNextMode != AP_NETWORK) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + } + ar->ap_profile_flag = 1; /* There is a change in profile */ + return 0; +} + +static int +ar6000_ioctl_giwencode(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *key) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_UINT8 keyIndex; + struct ar_wep_key *wk; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arPairwiseCrypto == NONE_CRYPT) { + erq->length = 0; + erq->flags = IW_ENCODE_DISABLED; + } else { + if (ar->arPairwiseCrypto == WEP_CRYPT) { + /* get the keyIndex */ + keyIndex = erq->flags & IW_ENCODE_INDEX; + if (0 == keyIndex) { + keyIndex = ar->arDefTxKeyIndex; + } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) || + (keyIndex - 1 > WMI_MAX_KEY_INDEX)) + { + keyIndex = WMI_MIN_KEY_INDEX; + } else { + keyIndex--; + } + erq->flags = keyIndex + 1; + erq->flags &= ~IW_ENCODE_DISABLED; + wk = &ar->arWepKeyList[keyIndex]; + if (erq->length > wk->arKeyLen) { + erq->length = wk->arKeyLen; + } + if (wk->arKeyLen) { + A_MEMCPY(key, wk->arKey, erq->length); + } + } else { + erq->flags &= ~IW_ENCODE_DISABLED; + if (ar->user_saved_keys.keyOk) { + erq->length = ar->user_saved_keys.ucast_ik.ik_keylen; + if (erq->length) { + A_MEMCPY(key, ar->user_saved_keys.ucast_ik.ik_keydata, erq->length); + } + } else { + erq->length = 1; // not really printing any key but let iwconfig know enc is on + } + } + + if (ar->arDot11AuthMode & OPEN_AUTH) { + erq->flags |= IW_ENCODE_OPEN; + } + if (ar->arDot11AuthMode & SHARED_AUTH) { + erq->flags |= IW_ENCODE_RESTRICTED; + } + } + + return 0; +} + +#if WIRELESS_EXT >= 18 +/* + * SIOCSIWGENIE + */ +static int +ar6000_ioctl_siwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + +#ifdef WAPI_ENABLE + A_UINT8 *ie = erq->pointer; + A_UINT8 ie_type = ie[0]; + A_UINT16 ie_length = erq->length; + A_UINT8 wapi_ie[128]; +#endif + + if (ar->arWmiReady == FALSE) { + return -EIO; + } +#ifdef WAPI_ENABLE + if (ie_type == IEEE80211_ELEMID_WAPI) { + if(copy_from_user(wapi_ie, ie, ie_length)) + return -EIO; + wmi_set_appie_cmd(ar->arWmi, WMI_FRAME_ASSOC_REQ, ie_length, wapi_ie); + } +#endif + return 0; +} + + +/* + * SIOCGIWGENIE + */ +static int +ar6000_ioctl_giwgenie(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + erq->length = 0; + erq->flags = 0; + + return 0; +} + +/* + * SIOCSIWAUTH + */ +static int +ar6000_ioctl_siwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + A_BOOL profChanged; + A_UINT16 param; + A_INT32 ret; + A_INT32 value; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + param = data->flags & IW_AUTH_INDEX; + value = data->value; + profChanged = TRUE; + ret = 0; + + switch (param) { + case IW_AUTH_WPA_VERSION: + if (value & IW_AUTH_WPA_VERSION_DISABLED) { + ar->arAuthMode = NONE_AUTH; + } else if (value & IW_AUTH_WPA_VERSION_WPA) { + ar->arAuthMode = WPA_AUTH; + } else if (value & IW_AUTH_WPA_VERSION_WPA2) { + ar->arAuthMode = WPA2_AUTH; + } else { + ret = -1; + profChanged = FALSE; + } + break; + case IW_AUTH_CIPHER_PAIRWISE: + if (value & IW_AUTH_CIPHER_NONE) { + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_WEP40) { + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arPairwiseCryptoLen = 5; + } else if (value & IW_AUTH_CIPHER_TKIP) { + ar->arPairwiseCrypto = TKIP_CRYPT; + ar->arPairwiseCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_CCMP) { + ar->arPairwiseCrypto = AES_CRYPT; + ar->arPairwiseCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_WEP104) { + ar->arPairwiseCrypto = WEP_CRYPT; + ar->arPairwiseCryptoLen = 13; + } else { + ret = -1; + profChanged = FALSE; + } + break; + case IW_AUTH_CIPHER_GROUP: + if (value & IW_AUTH_CIPHER_NONE) { + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_WEP40) { + ar->arGroupCrypto = WEP_CRYPT; + ar->arGroupCryptoLen = 5; + } else if (value & IW_AUTH_CIPHER_TKIP) { + ar->arGroupCrypto = TKIP_CRYPT; + ar->arGroupCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_CCMP) { + ar->arGroupCrypto = AES_CRYPT; + ar->arGroupCryptoLen = 0; + } else if (value & IW_AUTH_CIPHER_WEP104) { + ar->arGroupCrypto = WEP_CRYPT; + ar->arGroupCryptoLen = 13; + } else { + ret = -1; + profChanged = FALSE; + } + break; + case IW_AUTH_KEY_MGMT: + if (value & IW_AUTH_KEY_MGMT_PSK) { + if (WPA_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA_PSK_AUTH; + } else if (WPA2_AUTH == ar->arAuthMode) { + ar->arAuthMode = WPA2_PSK_AUTH; + } else { + ret = -1; + } + } else if (!(value & IW_AUTH_KEY_MGMT_802_1X)) { + ar->arAuthMode = NONE_AUTH; + } + break; + case IW_AUTH_TKIP_COUNTERMEASURES: + wmi_set_tkip_countermeasures_cmd(ar->arWmi, value); + profChanged = FALSE; + break; + case IW_AUTH_DROP_UNENCRYPTED: + profChanged = FALSE; + break; + case IW_AUTH_80211_AUTH_ALG: + ar->arDot11AuthMode = 0; + if (value & IW_AUTH_ALG_OPEN_SYSTEM) { + ar->arDot11AuthMode |= OPEN_AUTH; + } + if (value & IW_AUTH_ALG_SHARED_KEY) { + ar->arDot11AuthMode |= SHARED_AUTH; + } + if (value & IW_AUTH_ALG_LEAP) { + ar->arDot11AuthMode = LEAP_AUTH; + } + if(ar->arDot11AuthMode == 0) { + ret = -1; + profChanged = FALSE; + } + break; + case IW_AUTH_WPA_ENABLED: + if (!value) { + ar->arAuthMode = NONE_AUTH; + /* when the supplicant is stopped, it calls this + * handler with value=0. The followings need to be + * reset if the STA were to connect again + * without security + */ + ar->arDot11AuthMode = OPEN_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + } + break; + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + profChanged = FALSE; + break; + case IW_AUTH_ROAMING_CONTROL: + profChanged = FALSE; + break; + case IW_AUTH_PRIVACY_INVOKED: + if (!value) { + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + } + break; +#ifdef WAPI_ENABLE + case IW_AUTH_WAPI_ENABLED: + ar->arWapiEnable = value; + break; +#endif + default: + ret = -1; + profChanged = FALSE; + break; + } + + if (profChanged == TRUE) { + /* + * profile has changed. Erase ssid to signal change + */ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + } + + return ret; +} + + +/* + * SIOCGIWAUTH + */ +static int +ar6000_ioctl_giwauth(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_UINT16 param; + A_INT32 ret; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + param = data->flags & IW_AUTH_INDEX; + ret = 0; + data->value = 0; + + + switch (param) { + case IW_AUTH_WPA_VERSION: + if (ar->arAuthMode == NONE_AUTH) { + data->value |= IW_AUTH_WPA_VERSION_DISABLED; + } else if (ar->arAuthMode == WPA_AUTH) { + data->value |= IW_AUTH_WPA_VERSION_WPA; + } else if (ar->arAuthMode == WPA2_AUTH) { + data->value |= IW_AUTH_WPA_VERSION_WPA2; + } else { + ret = -1; + } + break; + case IW_AUTH_CIPHER_PAIRWISE: + if (ar->arPairwiseCrypto == NONE_CRYPT) { + data->value |= IW_AUTH_CIPHER_NONE; + } else if (ar->arPairwiseCrypto == WEP_CRYPT) { + if (ar->arPairwiseCryptoLen == 13) { + data->value |= IW_AUTH_CIPHER_WEP104; + } else { + data->value |= IW_AUTH_CIPHER_WEP40; + } + } else if (ar->arPairwiseCrypto == TKIP_CRYPT) { + data->value |= IW_AUTH_CIPHER_TKIP; + } else if (ar->arPairwiseCrypto == AES_CRYPT) { + data->value |= IW_AUTH_CIPHER_CCMP; + } else { + ret = -1; + } + break; + case IW_AUTH_CIPHER_GROUP: + if (ar->arGroupCrypto == NONE_CRYPT) { + data->value |= IW_AUTH_CIPHER_NONE; + } else if (ar->arGroupCrypto == WEP_CRYPT) { + if (ar->arGroupCryptoLen == 13) { + data->value |= IW_AUTH_CIPHER_WEP104; + } else { + data->value |= IW_AUTH_CIPHER_WEP40; + } + } else if (ar->arGroupCrypto == TKIP_CRYPT) { + data->value |= IW_AUTH_CIPHER_TKIP; + } else if (ar->arGroupCrypto == AES_CRYPT) { + data->value |= IW_AUTH_CIPHER_CCMP; + } else { + ret = -1; + } + break; + case IW_AUTH_KEY_MGMT: + if ((ar->arAuthMode == WPA_PSK_AUTH) || + (ar->arAuthMode == WPA2_PSK_AUTH)) { + data->value |= IW_AUTH_KEY_MGMT_PSK; + } else if ((ar->arAuthMode == WPA_AUTH) || + (ar->arAuthMode == WPA2_AUTH)) { + data->value |= IW_AUTH_KEY_MGMT_802_1X; + } + break; + case IW_AUTH_TKIP_COUNTERMEASURES: + // TODO. Save countermeassure enable/disable + data->value = 0; + break; + case IW_AUTH_DROP_UNENCRYPTED: + break; + case IW_AUTH_80211_AUTH_ALG: + if (ar->arDot11AuthMode == OPEN_AUTH) { + data->value |= IW_AUTH_ALG_OPEN_SYSTEM; + } else if (ar->arDot11AuthMode == SHARED_AUTH) { + data->value |= IW_AUTH_ALG_SHARED_KEY; + } else if (ar->arDot11AuthMode == LEAP_AUTH) { + data->value |= IW_AUTH_ALG_LEAP; + } else { + ret = -1; + } + break; + case IW_AUTH_WPA_ENABLED: + if (ar->arAuthMode == NONE_AUTH) { + data->value = 0; + } else { + data->value = 1; + } + break; + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + break; + case IW_AUTH_ROAMING_CONTROL: + break; + case IW_AUTH_PRIVACY_INVOKED: + if (ar->arPairwiseCrypto == NONE_CRYPT) { + data->value = 0; + } else { + data->value = 1; + } + break; +#ifdef WAPI_ENABLE + case IW_AUTH_WAPI_ENABLED: + data->value = ar->arWapiEnable; + break; +#endif + default: + ret = -1; + break; + } + + return 0; +} + +/* + * SIOCSIWPMKSA + */ +static int +ar6000_ioctl_siwpmksa(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_INT32 ret; + A_STATUS status; + struct iw_pmksa *pmksa; + + pmksa = (struct iw_pmksa *)extra; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + ret = 0; + status = A_OK; + + switch (pmksa->cmd) { + case IW_PMKSA_ADD: + status = wmi_setPmkid_cmd(ar->arWmi, (A_UINT8*)pmksa->bssid.sa_data, pmksa->pmkid, TRUE); + break; + case IW_PMKSA_REMOVE: + status = wmi_setPmkid_cmd(ar->arWmi, (A_UINT8*)pmksa->bssid.sa_data, pmksa->pmkid, FALSE); + break; + case IW_PMKSA_FLUSH: + if (ar->arConnected == TRUE) { + status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0); + } + break; + default: + ret=-1; + break; + } + if (status != A_OK) { + ret = -1; + } + + return ret; +} + +#ifdef WAPI_ENABLE + +#define PN_INIT 0x5c365c36 + +static int ar6000_set_wapi_key(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; + KEY_USAGE keyUsage = 0; + A_INT32 keyLen; + A_UINT8 *keyData; + A_INT32 index; + A_UINT32 *PN; + A_INT32 i; + A_STATUS status; + A_UINT8 wapiKeyRsc[16]; + CRYPTO_TYPE keyType = WAPI_CRYPT; + const A_UINT8 broadcastMac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + index = erq->flags & IW_ENCODE_INDEX; + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) { + return -EIO; + } + + index--; + if (index < 0 || index > 4) { + return -EIO; + } + keyData = (A_UINT8 *)(ext + 1); + keyLen = erq->length - sizeof(struct iw_encode_ext); + A_MEMCPY(wapiKeyRsc, ext->tx_seq, sizeof(wapiKeyRsc)); + + if (A_MEMCMP(ext->addr.sa_data, broadcastMac, sizeof(broadcastMac)) == 0) { + keyUsage |= GROUP_USAGE; + PN = (A_UINT32 *)wapiKeyRsc; + for (i = 0; i < 4; i++) { + PN[i] = PN_INIT; + } + } else { + keyUsage |= PAIRWISE_USAGE; + } + status = wmi_addKey_cmd(ar->arWmi, + index, + keyType, + keyUsage, + keyLen, + wapiKeyRsc, + keyData, + KEY_OP_INIT_WAPIPN, + NULL, + SYNC_BEFORE_WMIFLAG); + if (A_OK != status) { + return -EIO; + } + return 0; +} + +#endif + +/* + * SIOCSIWENCODEEXT + */ +static int +ar6000_ioctl_siwencodeext(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + A_INT32 index; + struct iw_encode_ext *ext; + KEY_USAGE keyUsage; + A_INT32 keyLen; + A_UINT8 *keyData; + A_UINT8 keyRsc[8]; + A_STATUS status; + CRYPTO_TYPE keyType; +#ifdef USER_KEYS + struct ieee80211req_key ik; +#endif /* USER_KEYS */ + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + +#ifdef USER_KEYS + ar->user_saved_keys.keyOk = FALSE; +#endif /* USER_KEYS */ + + index = erq->flags & IW_ENCODE_INDEX; + + if (index && (((index - 1) < WMI_MIN_KEY_INDEX) || + ((index - 1) > WMI_MAX_KEY_INDEX))) + { + return -EIO; + } + + ext = (struct iw_encode_ext *)extra; + if (erq->flags & IW_ENCODE_DISABLED) { + /* + * Encryption disabled + */ + if (index) { + /* + * If key index was specified then clear the specified key + */ + index--; + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + ar->arWepKeyList[index].arKeyLen = 0; + } + } else { + /* + * Enabling WEP encryption + */ + if (index) { + index--; /* keyindex is off base 1 in iwconfig */ + } + + keyUsage = 0; + keyLen = erq->length - sizeof(struct iw_encode_ext); + + if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) { + keyUsage = TX_USAGE; + ar->arDefTxKeyIndex = index; + // Just setting the key index + if (keyLen == 0) { + return 0; + } + } + + if (keyLen <= 0) { + return -EIO; + } + + /* key follows iw_encode_ext */ + keyData = (A_UINT8 *)(ext + 1); + + switch (ext->alg) { + case IW_ENCODE_ALG_WEP: + keyType = WEP_CRYPT; +#ifdef USER_KEYS + ik.ik_type = IEEE80211_CIPHER_WEP; +#endif /* USER_KEYS */ + if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(keyLen)) { + return -EIO; + } + + /* Check whether it is static wep. */ + if (!ar->arConnected) { + A_MEMZERO(ar->arWepKeyList[index].arKey, + sizeof(ar->arWepKeyList[index].arKey)); + A_MEMCPY(ar->arWepKeyList[index].arKey, keyData, keyLen); + ar->arWepKeyList[index].arKeyLen = keyLen; + + return 0; + } + break; + case IW_ENCODE_ALG_TKIP: + keyType = TKIP_CRYPT; +#ifdef USER_KEYS + ik.ik_type = IEEE80211_CIPHER_TKIP; +#endif /* USER_KEYS */ + break; + case IW_ENCODE_ALG_CCMP: + keyType = AES_CRYPT; +#ifdef USER_KEYS + ik.ik_type = IEEE80211_CIPHER_AES_CCM; +#endif /* USER_KEYS */ + break; +#ifdef WAPI_ENABLE + case IW_ENCODE_ALG_SM4: + if (ar->arWapiEnable) { + return ar6000_set_wapi_key(dev, info, erq, extra); + } else { + return -EIO; + } +#endif + case IW_ENCODE_ALG_PMK: + ar->arConnectCtrlFlags |= CONNECT_DO_WPA_OFFLOAD; + return wmi_set_pmk_cmd(ar->arWmi, keyData); + default: + return -EIO; + } + + + if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { + keyUsage |= GROUP_USAGE; + } else { + keyUsage |= PAIRWISE_USAGE; + } + + if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) { + A_MEMCPY(keyRsc, ext->rx_seq, sizeof(keyRsc)); + } else { + A_MEMZERO(keyRsc, sizeof(keyRsc)); + } + + if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) && + (GROUP_USAGE & keyUsage)) + { + A_UNTIMEOUT(&ar->disconnect_timer); + } + + status = wmi_addKey_cmd(ar->arWmi, index, keyType, keyUsage, + keyLen, keyRsc, + keyData, KEY_OP_INIT_VAL, + (A_UINT8*)ext->addr.sa_data, + SYNC_BOTH_WMIFLAG); + if (status != A_OK) { + return -EIO; + } + +#ifdef USER_KEYS + ik.ik_keyix = index; + ik.ik_keylen = keyLen; + memcpy(ik.ik_keydata, keyData, keyLen); + memcpy(&ik.ik_keyrsc, keyRsc, sizeof(keyRsc)); + memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN); + if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) { + memcpy(&ar->user_saved_keys.bcast_ik, &ik, + sizeof(struct ieee80211req_key)); + } else { + memcpy(&ar->user_saved_keys.ucast_ik, &ik, + sizeof(struct ieee80211req_key)); + } + ar->user_saved_keys.keyOk = TRUE; +#endif /* USER_KEYS */ + } + + + return 0; +} + +/* + * SIOCGIWENCODEEXT + */ +static int +ar6000_ioctl_giwencodeext(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *erq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arPairwiseCrypto == NONE_CRYPT) { + erq->length = 0; + erq->flags = IW_ENCODE_DISABLED; + } else { + erq->length = 0; + } + + return 0; +} +#endif // WIRELESS_EXT >= 18 + +#if WIRELESS_EXT > 20 +static int ar6000_ioctl_siwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_POWER_MODE power_mode; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (wrqu->power.disabled) + power_mode = MAX_PERF_POWER; + else + power_mode = REC_POWER; + + if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0) + return -EIO; + return 0; +} + +static int ar6000_ioctl_giwpower(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + WMI_POWER_MODE power_mode; + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + power_mode = wmi_get_power_mode_cmd(ar->arWmi); + + if (power_mode == MAX_PERF_POWER) + wrqu->power.disabled = 1; + else + wrqu->power.disabled = 0; + + return 0; +} +#endif // WIRELESS_EXT > 20 + +/* + * SIOCGIWNAME + */ +int +ar6000_ioctl_giwname(struct net_device *dev, + struct iw_request_info *info, + char *name, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arPhyCapability) { + case (WMI_11A_CAPABILITY): + strncpy(name, "AR6000 802.11a", IFNAMSIZ); + break; + case (WMI_11G_CAPABILITY): + strncpy(name, "AR6000 802.11g", IFNAMSIZ); + break; + case (WMI_11AG_CAPABILITY): + strncpy(name, "AR6000 802.11ag", IFNAMSIZ); + break; + case (WMI_11NA_CAPABILITY): + strncpy(name, "AR6000 802.11na", IFNAMSIZ); + break; + case (WMI_11NG_CAPABILITY): + strncpy(name, "AR6000 802.11ng", IFNAMSIZ); + break; + case (WMI_11NAG_CAPABILITY): + strncpy(name, "AR6000 802.11nag", IFNAMSIZ); + break; + default: + strncpy(name, "AR6000 802.11", IFNAMSIZ); + break; + } + + return 0; +} + +/* + * SIOCSIWFREQ + */ +int +ar6000_ioctl_siwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* + * We support limiting the channels via wmiconfig. + * + * We use this command to configure the channel hint for the connect cmd + * so it is possible the target will end up connecting to a different + * channel. + */ + if (freq->e > 1) { + return -EINVAL; + } else if (freq->e == 1) { + ar->arChannelHint = freq->m / 100000; + } else { + if(freq->m) { + ar->arChannelHint = wlan_ieee2freq(freq->m); + } else { + /* Auto Channel Selection */ + ar->arChannelHint = 0; + } + } + + ar->ap_profile_flag = 1; /* There is a change in profile */ + + A_PRINTF("channel hint set to %d\n", ar->arChannelHint); + return 0; +} + +/* + * SIOCGIWFREQ + */ +int +ar6000_ioctl_giwfreq(struct net_device *dev, + struct iw_request_info *info, + struct iw_freq *freq, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arNetworkType == AP_NETWORK) { + if(ar->arChannelHint) { + freq->m = ar->arChannelHint * 100000; + } else if(ar->arACS) { + freq->m = ar->arACS * 100000; + } else { + return -EINVAL; + } + } else { + if (ar->arConnected != TRUE) { + return -EINVAL; + } else { + freq->m = ar->arBssChannel * 100000; + } + } + + freq->e = 1; + + return 0; +} + +/* + * SIOCSIWMODE + */ +int +ar6000_ioctl_siwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + /* + * clear SSID during mode switch in connected state + */ + if(!(ar->arNetworkType == (((*mode) == IW_MODE_INFRA) ? INFRA_NETWORK : ADHOC_NETWORK)) && (ar->arConnected == TRUE) ){ + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + } + + switch (*mode) { + case IW_MODE_INFRA: + ar->arNextMode = INFRA_NETWORK; + break; + case IW_MODE_ADHOC: + ar->arNextMode = ADHOC_NETWORK; + break; + case IW_MODE_MASTER: + ar->arNextMode = AP_NETWORK; + break; + default: + return -EINVAL; + } + + /* clear all shared parameters between AP and STA|IBSS modes when we + * switch between them. Switch between STA & IBSS modes does'nt clear + * the shared profile. This is as per the original design for switching + * between STA & IBSS. + */ + if (ar->arNetworkType == AP_NETWORK || ar->arNextMode == AP_NETWORK) { + ar->arDot11AuthMode = OPEN_AUTH; + ar->arAuthMode = NONE_AUTH; + ar->arPairwiseCrypto = NONE_CRYPT; + ar->arPairwiseCryptoLen = 0; + ar->arGroupCrypto = NONE_CRYPT; + ar->arGroupCryptoLen = 0; + ar->arChannelHint = 0; + ar->arBssChannel = 0; + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + } + + /* SSID has to be cleared to trigger a profile change while switching + * between STA & IBSS modes having the same SSID + */ + if (ar->arNetworkType != ar->arNextMode) { + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + } + + return 0; +} + +/* + * SIOCGIWMODE + */ +int +ar6000_ioctl_giwmode(struct net_device *dev, + struct iw_request_info *info, + __u32 *mode, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + switch (ar->arNetworkType) { + case INFRA_NETWORK: + *mode = IW_MODE_INFRA; + break; + case ADHOC_NETWORK: + *mode = IW_MODE_ADHOC; + break; + case AP_NETWORK: + *mode = IW_MODE_MASTER; + break; + default: + return -EIO; + } + return 0; +} + +/* + * SIOCSIWSENS + */ +int +ar6000_ioctl_siwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + return 0; +} + +/* + * SIOCGIWSENS + */ +int +ar6000_ioctl_giwsens(struct net_device *dev, + struct iw_request_info *info, + struct iw_param *sens, char *extra) +{ + sens->value = 0; + sens->fixed = 1; + + return 0; +} + +/* + * SIOCGIWRANGE + */ +int +ar6000_ioctl_giwrange(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + struct iw_range *range = (struct iw_range *) extra; + int i, ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (ar->bIsDestroyProgress) { + up(&ar->arSem); + return -EBUSY; + } + + ar->arNumChannels = -1; + A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList)); + + if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) { + up(&ar->arSem); + return -EIO; + } + + wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ); + + if (signal_pending(current)) { + up(&ar->arSem); + return -EINTR; + } + + data->length = sizeof(struct iw_range); + A_MEMZERO(range, sizeof(struct iw_range)); + + range->txpower_capa = 0; + + range->min_pmp = 1 * 1024; + range->max_pmp = 65535 * 1024; + range->min_pmt = 1 * 1024; + range->max_pmt = 1000 * 1024; + range->pmp_flags = IW_POWER_PERIOD; + range->pmt_flags = IW_POWER_TIMEOUT; + range->pm_capa = 0; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 13; + + range->retry_capa = IW_RETRY_LIMIT; + range->retry_flags = IW_RETRY_LIMIT; + range->min_retry = 0; + range->max_retry = 255; + + range->num_frequency = range->num_channels = ar->arNumChannels; + for (i = 0; i < ar->arNumChannels; i++) { + range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]); + range->freq[i].m = ar->arChannelList[i] * 100000; + range->freq[i].e = 1; + /* + * Linux supports max of 32 channels, bail out once you + * reach the max. + */ + if (i == IW_MAX_FREQUENCIES) { + break; + } + } + + /* Max quality is max field value minus noise floor */ + range->max_qual.qual = 0xff - 161; + + /* + * In order to use dBm measurements, 'level' must be lower + * than any possible measurement (see iw_print_stats() in + * wireless tools). It's unclear how this is meant to be + * done, but setting zero in these values forces dBm and + * the actual numbers are not used. + */ + range->max_qual.level = 0; + range->max_qual.noise = 0; + + range->sensitivity = 3; + + range->max_encoding_tokens = 4; + /* XXX query driver to find out supported key sizes */ + range->num_encoding_sizes = 3; + range->encoding_size[0] = 5; /* 40-bit */ + range->encoding_size[1] = 13; /* 104-bit */ + range->encoding_size[2] = 16; /* 128-bit */ + + range->num_bitrates = 0; + + /* estimated maximum TCP throughput values (bps) */ + range->throughput = 22000000; + + range->min_rts = 0; + range->max_rts = 2347; + range->min_frag = 256; + range->max_frag = 2346; + + up(&ar->arSem); + + return ret; +} + + +/* + * SIOCSIWAP + * This ioctl is used to set the desired bssid for the connect command. + */ +int +ar6000_ioctl_siwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ap_addr->sa_family != ARPHRD_ETHER) { + return -EIO; + } + + if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } else { + A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid)); + } + + return 0; +} + +/* + * SIOCGIWAP + */ +int +ar6000_ioctl_giwap(struct net_device *dev, + struct iw_request_info *info, + struct sockaddr *ap_addr, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arNetworkType == AP_NETWORK) { + A_MEMCPY(&ap_addr->sa_data, dev->dev_addr, ATH_MAC_LEN); + ap_addr->sa_family = ARPHRD_ETHER; + return 0; + } + + if (ar->arConnected != TRUE) { + return -EINVAL; + } + + A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid)); + ap_addr->sa_family = ARPHRD_ETHER; + + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) +/* + * SIOCSIWMLME + */ +int +ar6000_ioctl_siwmlme(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->bIsDestroyProgress) { + return -EBUSY; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (down_interruptible(&ar->arSem)) { + return -ERESTARTSYS; + } + + if (data->pointer && data->length == sizeof(struct iw_mlme)) { + + A_UINT8 arNetworkType; + struct iw_mlme mlme; + + if (copy_from_user(&mlme, data->pointer, sizeof(struct iw_mlme))) + return -EIO; + + switch (mlme.cmd) { + + case IW_MLME_DEAUTH: + /* fall through */ + case IW_MLME_DISASSOC: + if ((ar->arConnected != TRUE) || + (memcmp(ar->arBssid, mlme.addr.sa_data, 6) != 0)) { + + up(&ar->arSem); + return -EINVAL; + } + wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0); + arNetworkType = ar->arNetworkType; + ar6000_init_profile_info(ar); + ar->arNetworkType = arNetworkType; + reconnect_flag = 0; + wmi_disconnect_cmd(ar->arWmi); + A_MEMZERO(ar->arSsid, sizeof(ar->arSsid)); + ar->arSsidLen = 0; + if (ar->arSkipScan == FALSE) { + A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid)); + } + break; + + case IW_MLME_AUTH: + /* fall through */ + case IW_MLME_ASSOC: + /* fall through */ + default: + up(&ar->arSem); + return -EOPNOTSUPP; + } + } + + up(&ar->arSem); + return 0; +} +#endif /* LINUX_VERSION_CODE */ + +/* + * SIOCGIWAPLIST + */ +int +ar6000_ioctl_iwaplist(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + return -EIO; /* for now */ +} + +/* + * SIOCSIWSCAN + */ +int +ar6000_ioctl_siwscan(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ +#define ACT_DWELLTIME_DEFAULT 105 +#define HOME_TXDRAIN_TIME 100 +#define SCAN_INT HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + int ret = 0; + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + if (!ar->arUserBssFilter) { + if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) { + return -EIO; + } + } + + if (ar->arConnected) { + if (wmi_get_stats_cmd(ar->arWmi) != A_OK) { + return -EIO; + } + } + +#ifdef ANDROID_ENV +#if WIRELESS_EXT >= 18 + if (data->pointer && (data->length == sizeof(struct iw_scan_req))) + { + if ((data->flags & IW_SCAN_THIS_ESSID) == IW_SCAN_THIS_ESSID) + { + struct iw_scan_req req; + if (copy_from_user(&req, data->pointer, sizeof(struct iw_scan_req))) + return -EIO; + if (wmi_probedSsid_cmd(ar->arWmi, 1, SPECIFIC_SSID_FLAG, req.essid_len, req.essid) != A_OK) + return -EIO; + } + else + { + if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK) + return -EIO; + } + } + else + { + if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != A_OK) + return -EIO; + } +#endif +#endif /* ANDROID_ENV */ + + if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \ + 0, 0, 0, NULL) != A_OK) { + ret = -EIO; + } + + if (ret == 0) { + ar->scan_complete = 0; + } + + return ret; +#undef ACT_DWELLTIME_DEFAULT +#undef HOME_TXDRAIN_TIME +#undef SCAN_INT +} + + +/* + * Units are in db above the noise floor. That means the + * rssi values reported in the tx/rx descriptors in the + * driver are the SNR expressed in db. + * + * If you assume that the noise floor is -95, which is an + * excellent assumption 99.5 % of the time, then you can + * derive the absolute signal level (i.e. -95 + rssi). + * There are some other slight factors to take into account + * depending on whether the rssi measurement is from 11b, + * 11g, or 11a. These differences are at most 2db and + * can be documented. + * + * NB: various calculations are based on the orinoco/wavelan + * drivers for compatibility + */ +static void +ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi) +{ + if (rssi < 0) { + iq->qual = 0; + } else { + iq->qual = rssi; + } + + /* NB: max is 94 because noise is hardcoded to 161 */ + if (iq->qual > 94) + iq->qual = 94; + + iq->noise = 161; /* -95dBm */ + iq->level = iq->noise + iq->qual; + iq->updated = 7; +} + + +int +ar6000_ioctl_siwcommit(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *data, char *extra) +{ + AR_SOFTC_T *ar = (AR_SOFTC_T *)ar6k_priv(dev); + + if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != A_OK) { + A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd); + return -EOPNOTSUPP; + } + + if (ar->arWmiReady == FALSE) { + return -EIO; + } + + if (ar->arWlanState == WLAN_DISABLED) { + return -EIO; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AP: SSID %s freq %d authmode %d dot11 auth %d"\ + " PW crypto %d GRP crypto %d\n", + ar->arSsid, ar->arChannelHint, + ar->arAuthMode, ar->arDot11AuthMode, + ar->arPairwiseCrypto, ar->arGroupCrypto)); + + ar6000_ap_mode_profile_commit(ar); + + /* if there is a profile switch from STA|IBSS mode to AP mode, + * update the host driver association state for the STA|IBSS mode. + */ + if (ar->arNetworkType != AP_NETWORK && ar->arNextMode == AP_NETWORK) { + ar->arConnectPending = FALSE; + ar->arConnected = FALSE; + /* Stop getting pkts from upper stack */ + netif_stop_queue(ar->arNetDev); + A_MEMZERO(ar->arBssid, sizeof(ar->arBssid)); + ar->arBssChannel = 0; + ar->arBeaconInterval = 0; + + /* Flush the Tx queues */ + ar6000_TxDataCleanup(ar); + + /* Start getting pkts from upper stack */ + netif_wake_queue(ar->arNetDev); + } + + return 0; +} + +/* Structures to export the Wireless Handlers */ +static const iw_handler ath_handlers[] = { + (iw_handler) ar6000_ioctl_siwcommit, /* SIOCSIWCOMMIT */ + (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */ + (iw_handler) NULL, /* SIOCSIWNWID */ + (iw_handler) NULL, /* SIOCGIWNWID */ + (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */ + (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */ + (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */ + (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */ + (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */ + (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */ + (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */ + (iw_handler) ar6000_ioctl_giwrange, /* SIOCGIWRANGE */ + (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */ + (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */ + (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */ + (iw_handler) NULL, /* SIOCSIWSPY */ + (iw_handler) NULL, /* SIOCGIWSPY */ + (iw_handler) NULL, /* SIOCSIWTHRSPY */ + (iw_handler) NULL, /* SIOCGIWTHRSPY */ + (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */ + (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,13) + (iw_handler) ar6000_ioctl_siwmlme, /* SIOCSIWMLME */ +#else + (iw_handler) NULL, /* -- hole -- */ +#endif /* LINUX_VERSION_CODE */ + (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */ + (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */ + (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */ + (iw_handler) ar6000_ioctl_siwessid, /* SIOCSIWESSID */ + (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */ + (iw_handler) NULL, /* SIOCSIWNICKN */ + (iw_handler) NULL, /* SIOCGIWNICKN */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */ + (iw_handler) ar6000_ioctl_giwrate, /* SIOCGIWRATE */ + (iw_handler) NULL, /* SIOCSIWRTS */ + (iw_handler) NULL, /* SIOCGIWRTS */ + (iw_handler) NULL, /* SIOCSIWFRAG */ + (iw_handler) NULL, /* SIOCGIWFRAG */ + (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */ + (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */ + (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */ + (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */ + (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */ + (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */ +#if WIRELESS_EXT > 20 + (iw_handler) ar6000_ioctl_siwpower, /* SIOCSIWPOWER */ + (iw_handler) ar6000_ioctl_giwpower, /* SIOCGIWPOWER */ +#endif // WIRELESS_EXT > 20 +#if WIRELESS_EXT >= 18 + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) NULL, /* -- hole -- */ + (iw_handler) ar6000_ioctl_siwgenie, /* SIOCSIWGENIE */ + (iw_handler) ar6000_ioctl_giwgenie, /* SIOCGIWGENIE */ + (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */ + (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */ + (iw_handler) ar6000_ioctl_siwencodeext, /* SIOCSIWENCODEEXT */ + (iw_handler) ar6000_ioctl_giwencodeext, /* SIOCGIWENCODEEXT */ + (iw_handler) ar6000_ioctl_siwpmksa, /* SIOCSIWPMKSA */ +#endif // WIRELESS_EXT >= 18 +}; + +struct iw_handler_def ath_iw_handler_def = { + .standard = (iw_handler *)ath_handlers, + .num_standard = ARRAY_SIZE(ath_handlers), + .private = NULL, + .num_private = 0, +}; diff --git a/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h b/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h new file mode 100644 index 000000000000..567a3ff185ca --- /dev/null +++ b/drivers/net/wireless/ath6kl/reorder/aggr_rx_internal.h @@ -0,0 +1,112 @@ +/* + * + * Copyright (c) 2004-2007 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifndef __AGGR_RX_INTERNAL_H__ +#define __AGGR_RX_INTERNAL_H__ + +#include "a_osapi.h" +#include "aggr_recv_api.h" + +#define AGGR_WIN_IDX(x, y) ((x) % (y)) +#define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x)+1), (y)) +#define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x)-1), (y)) +#define IEEE80211_MAX_SEQ_NO 0xFFF +#define IEEE80211_NEXT_SEQ_NO(x) (((x) + 1) & IEEE80211_MAX_SEQ_NO) + + +#define NUM_OF_TIDS 8 +#define AGGR_SZ_DEFAULT 8 + +#define AGGR_WIN_SZ_MIN 2 +#define AGGR_WIN_SZ_MAX 8 +/* TID Window sz is double of what is negotiated. Derive TID_WINDOW_SZ from win_sz, per tid */ +#define TID_WINDOW_SZ(_x) ((_x) << 1) + +#define AGGR_NUM_OF_FREE_NETBUFS 16 + +#define AGGR_GET_RXTID_STATS(_p, _x) (&(_p->stat[(_x)])) +#define AGGR_GET_RXTID(_p, _x) (&(_p->RxTid[(_x)])) + +/* Hold q is a function of win_sz, which is negotiated per tid */ +#define HOLD_Q_SZ(_x) (TID_WINDOW_SZ((_x))*sizeof(OSBUF_HOLD_Q)) +/* AGGR_RX_TIMEOUT value is important as a (too) small value can cause frames to be + * delivered out of order and a (too) large value can cause undesirable latency in + * certain situations. */ +#define AGGR_RX_TIMEOUT 400 /* Timeout(in ms) for delivery of frames, if they are stuck */ + +typedef enum { + ALL_SEQNO = 0, + CONTIGUOUS_SEQNO = 1, +}DELIVERY_ORDER; + +typedef struct { + void *osbuf; + A_BOOL is_amsdu; + A_UINT16 seq_no; +}OSBUF_HOLD_Q; + + +#if 0 +typedef struct { + A_UINT16 seqno_st; + A_UINT16 seqno_end; +}WINDOW_SNAPSHOT; +#endif + +typedef struct { + A_BOOL aggr; /* is it ON or OFF */ + A_BOOL progress; /* TRUE when frames have arrived after a timer start */ + A_BOOL timerMon; /* TRUE if the timer started for the sake of this TID */ + A_UINT16 win_sz; /* negotiated window size */ + A_UINT16 seq_next; /* Next seq no, in current window */ + A_UINT32 hold_q_sz; /* Num of frames that can be held in hold q */ + OSBUF_HOLD_Q *hold_q; /* Hold q for re-order */ +#if 0 + WINDOW_SNAPSHOT old_win; /* Sliding window snapshot - for timeout */ +#endif + A_NETBUF_QUEUE_T q; /* q head for enqueuing frames for dispatch */ + A_MUTEX_T lock; +}RXTID; + +typedef struct { + A_UINT32 num_into_aggr; /* hitting at the input of this module */ + A_UINT32 num_dups; /* duplicate */ + A_UINT32 num_oow; /* out of window */ + A_UINT32 num_mpdu; /* single payload 802.3/802.11 frame */ + A_UINT32 num_amsdu; /* AMSDU */ + A_UINT32 num_delivered; /* frames delivered to IP stack */ + A_UINT32 num_timeouts; /* num of timeouts, during which frames delivered */ + A_UINT32 num_hole; /* frame not present, when window moved over */ + A_UINT32 num_bar; /* num of resets of seq_num, via BAR */ +}RXTID_STATS; + +typedef struct { + A_UINT8 aggr_sz; /* config value of aggregation size */ + A_UINT8 timerScheduled; + A_TIMER timer; /* timer for returning held up pkts in re-order que */ + void *dev; /* dev handle */ + RX_CALLBACK rx_fn; /* callback function to return frames; to upper layer */ + RXTID RxTid[NUM_OF_TIDS]; /* Per tid window */ + ALLOC_NETBUFS netbuf_allocator; /* OS netbuf alloc fn */ + A_NETBUF_QUEUE_T freeQ; /* pre-allocated buffers - for A_MSDU slicing */ + RXTID_STATS stat[NUM_OF_TIDS]; /* Tid based statistics */ + PACKET_LOG pkt_log; /* Log info of the packets */ +}AGGR_INFO; + +#endif /* __AGGR_RX_INTERNAL_H__ */ diff --git a/drivers/net/wireless/ath6kl/reorder/makefile b/drivers/net/wireless/ath6kl/reorder/makefile new file mode 100644 index 000000000000..6e53a111b67f --- /dev/null +++ b/drivers/net/wireless/ath6kl/reorder/makefile @@ -0,0 +1,22 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation; +# +# Software distributed under the License is distributed on an "AS +# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# +#------------------------------------------------------------------------------ +#============================================================================== +# Author(s): ="Atheros" +#============================================================================== +!INCLUDE $(_MAKEENVROOT)\makefile.def + + + diff --git a/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c b/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c new file mode 100644 index 000000000000..3bfba4fbc051 --- /dev/null +++ b/drivers/net/wireless/ath6kl/reorder/rcv_aggr.c @@ -0,0 +1,662 @@ +/* + * + * Copyright (c) 2010 Atheros Communications Inc. + * All rights reserved. + * + * +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// + * + */ + +#ifdef ATH_AR6K_11N_SUPPORT + +#include +#include +#include +#include +#include +#include "pkt_log.h" +#include "aggr_recv_api.h" +#include "aggr_rx_internal.h" +#include "wmi.h" + +extern A_STATUS +wmi_dot3_2_dix(void *osbuf); + +static void +aggr_slice_amsdu(AGGR_INFO *p_aggr, RXTID *rxtid, void **osbuf); + +static void +aggr_timeout(A_ATH_TIMER arg); + +static void +aggr_deque_frms(AGGR_INFO *p_aggr, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 order); + +static void +aggr_dispatch_frames(AGGR_INFO *p_aggr, A_NETBUF_QUEUE_T *q); + +static void * +aggr_get_osbuf(AGGR_INFO *p_aggr); + +void * +aggr_init(ALLOC_NETBUFS netbuf_allocator) +{ + AGGR_INFO *p_aggr = NULL; + RXTID *rxtid; + A_UINT8 i; + A_STATUS status = A_OK; + + A_PRINTF("In aggr_init..\n"); + + do { + p_aggr = A_MALLOC(sizeof(AGGR_INFO)); + if(!p_aggr) { + A_PRINTF("Failed to allocate memory for aggr_node\n"); + status = A_ERROR; + break; + } + + /* Init timer and data structures */ + A_MEMZERO(p_aggr, sizeof(AGGR_INFO)); + p_aggr->aggr_sz = AGGR_SZ_DEFAULT; + A_INIT_TIMER(&p_aggr->timer, aggr_timeout, p_aggr); + p_aggr->timerScheduled = FALSE; + A_NETBUF_QUEUE_INIT(&p_aggr->freeQ); + + p_aggr->netbuf_allocator = netbuf_allocator; + p_aggr->netbuf_allocator(&p_aggr->freeQ, AGGR_NUM_OF_FREE_NETBUFS); + + for(i = 0; i < NUM_OF_TIDS; i++) { + rxtid = AGGR_GET_RXTID(p_aggr, i); + rxtid->aggr = FALSE; + rxtid->progress = FALSE; + rxtid->timerMon = FALSE; + A_NETBUF_QUEUE_INIT(&rxtid->q); + A_MUTEX_INIT(&rxtid->lock); + } + }while(FALSE); + + A_PRINTF("going out of aggr_init..status %s\n", + (status == A_OK) ? "OK":"Error"); + + if(status != A_OK) { + /* Cleanup */ + aggr_module_destroy(p_aggr); + } + return ((status == A_OK) ? p_aggr : NULL); +} + +/* utility function to clear rx hold_q for a tid */ +static void +aggr_delete_tid_state(AGGR_INFO *p_aggr, A_UINT8 tid) +{ + RXTID *rxtid; + RXTID_STATS *stats; + + A_ASSERT(tid < NUM_OF_TIDS && p_aggr); + + rxtid = AGGR_GET_RXTID(p_aggr, tid); + stats = AGGR_GET_RXTID_STATS(p_aggr, tid); + + if(rxtid->aggr) { + aggr_deque_frms(p_aggr, tid, 0, ALL_SEQNO); + } + + rxtid->aggr = FALSE; + rxtid->progress = FALSE; + rxtid->timerMon = FALSE; + rxtid->win_sz = 0; + rxtid->seq_next = 0; + rxtid->hold_q_sz = 0; + + if(rxtid->hold_q) { + A_FREE(rxtid->hold_q); + rxtid->hold_q = NULL; + } + + A_MEMZERO(stats, sizeof(RXTID_STATS)); +} + +void +aggr_module_destroy(void *cntxt) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + RXTID *rxtid; + A_UINT8 i, k; + A_PRINTF("%s(): aggr = %p\n",_A_FUNCNAME_, p_aggr); + A_ASSERT(p_aggr); + + if(p_aggr) { + if(p_aggr->timerScheduled) { + A_UNTIMEOUT(&p_aggr->timer); + p_aggr->timerScheduled = FALSE; + } + + for(i = 0; i < NUM_OF_TIDS; i++) { + rxtid = AGGR_GET_RXTID(p_aggr, i); + /* Free the hold q contents and hold_q*/ + if(rxtid->hold_q) { + for(k = 0; k< rxtid->hold_q_sz; k++) { + if(rxtid->hold_q[k].osbuf) { + A_NETBUF_FREE(rxtid->hold_q[k].osbuf); + } + } + A_FREE(rxtid->hold_q); + } + /* Free the dispatch q contents*/ + while(A_NETBUF_QUEUE_SIZE(&rxtid->q)) { + A_NETBUF_FREE(A_NETBUF_DEQUEUE(&rxtid->q)); + } + if (A_IS_MUTEX_VALID(&rxtid->lock)) { + A_MUTEX_DELETE(&rxtid->lock); + } + } + /* free the freeQ and its contents*/ + while(A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) { + A_NETBUF_FREE(A_NETBUF_DEQUEUE(&p_aggr->freeQ)); + } + A_FREE(p_aggr); + } + A_PRINTF("out aggr_module_destroy\n"); +} + + +void +aggr_register_rx_dispatcher(void *cntxt, void * dev, RX_CALLBACK fn) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + + A_ASSERT(p_aggr && fn && dev); + + p_aggr->rx_fn = fn; + p_aggr->dev = dev; +} + + +void +aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + RXTID_STATS *stats; + + A_ASSERT(p_aggr); + stats = AGGR_GET_RXTID_STATS(p_aggr, tid); + stats->num_bar++; + + aggr_deque_frms(p_aggr, tid, seq_no, ALL_SEQNO); +} + + +void +aggr_recv_addba_req_evt(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + RXTID *rxtid; + RXTID_STATS *stats; + + A_ASSERT(p_aggr); + rxtid = AGGR_GET_RXTID(p_aggr, tid); + stats = AGGR_GET_RXTID_STATS(p_aggr, tid); + + A_PRINTF("%s(): win_sz = %d aggr %d\n", _A_FUNCNAME_, win_sz, rxtid->aggr); + if(win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX) { + A_PRINTF("win_sz %d, tid %d\n", win_sz, tid); + } + + if(rxtid->aggr) { + /* Just go and deliver all the frames up from this + * queue, as if we got DELBA and re-initialize the queue + */ + aggr_delete_tid_state(p_aggr, tid); + } + + rxtid->seq_next = seq_no; + /* create these queues, only upon receiving of ADDBA for a + * tid, reducing memory requirement + */ + rxtid->hold_q = A_MALLOC(HOLD_Q_SZ(win_sz)); + if((rxtid->hold_q == NULL)) { + A_PRINTF("Failed to allocate memory, tid = %d\n", tid); + A_ASSERT(0); + } + A_MEMZERO(rxtid->hold_q, HOLD_Q_SZ(win_sz)); + + /* Update rxtid for the window sz */ + rxtid->win_sz = win_sz; + /* hold_q_sz inicates the depth of holding q - which is + * a factor of win_sz. Compute once, as it will be used often + */ + rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz); + /* There should be no frames on q - even when second ADDBA comes in. + * If aggr was previously ON on this tid, we would have cleaned up + * the q + */ + if(A_NETBUF_QUEUE_SIZE(&rxtid->q) != 0) { + A_PRINTF("ERROR: Frames still on queue ?\n"); + A_ASSERT(0); + } + + rxtid->aggr = TRUE; +} + +void +aggr_recv_delba_req_evt(void *cntxt, A_UINT8 tid) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + RXTID *rxtid; + + A_ASSERT(p_aggr); + A_PRINTF("%s(): tid %d\n", _A_FUNCNAME_, tid); + + rxtid = AGGR_GET_RXTID(p_aggr, tid); + + if(rxtid->aggr) { + aggr_delete_tid_state(p_aggr, tid); + } +} + +static void +aggr_deque_frms(AGGR_INFO *p_aggr, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 order) +{ + RXTID *rxtid; + OSBUF_HOLD_Q *node; + A_UINT16 idx, idx_end, seq_end; + RXTID_STATS *stats; + + A_ASSERT(p_aggr); + rxtid = AGGR_GET_RXTID(p_aggr, tid); + stats = AGGR_GET_RXTID_STATS(p_aggr, tid); + + /* idx is absolute location for first frame */ + idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); + + /* idx_end is typically the last possible frame in the window, + * but changes to 'the' seq_no, when BAR comes. If seq_no + * is non-zero, we will go up to that and stop. + * Note: last seq no in current window will occupy the same + * index position as index that is just previous to start. + * An imp point : if win_sz is 7, for seq_no space of 4095, + * then, there would be holes when sequence wrap around occurs. + * Target should judiciously choose the win_sz, based on + * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz + * 2, 4, 8, 16 win_sz works fine). + * We must deque from "idx" to "idx_end", including both. + */ + seq_end = (seq_no) ? seq_no : rxtid->seq_next; + idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz); + + /* Critical section begins */ + A_MUTEX_LOCK(&rxtid->lock); + do { + + node = &rxtid->hold_q[idx]; + + if((order == CONTIGUOUS_SEQNO) && (!node->osbuf)) + break; + + /* chain frames and deliver frames bcos: + * 1. either the frames are in order and window is contiguous, OR + * 2. we need to deque frames, irrespective of holes + */ + if(node->osbuf) { + if(node->is_amsdu) { + aggr_slice_amsdu(p_aggr, rxtid, &node->osbuf); + } else { + A_NETBUF_ENQUEUE(&rxtid->q, node->osbuf); + } + node->osbuf = NULL; + } else { + stats->num_hole++; + } + + /* window is moving */ + rxtid->seq_next = IEEE80211_NEXT_SEQ_NO(rxtid->seq_next); + idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); + } while(idx != idx_end); + /* Critical section ends */ + A_MUTEX_UNLOCK(&rxtid->lock); + + stats->num_delivered += A_NETBUF_QUEUE_SIZE(&rxtid->q); + aggr_dispatch_frames(p_aggr, &rxtid->q); +} + +static void * +aggr_get_osbuf(AGGR_INFO *p_aggr) +{ + void *buf = NULL; + + /* Starving for buffers? get more from OS + * check for low netbuffers( < 1/4 AGGR_NUM_OF_FREE_NETBUFS) : + * re-allocate bufs if so + * allocate a free buf from freeQ + */ + if (A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ) < (AGGR_NUM_OF_FREE_NETBUFS >> 2)) { + p_aggr->netbuf_allocator(&p_aggr->freeQ, AGGR_NUM_OF_FREE_NETBUFS); + } + + if (A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) { + buf = A_NETBUF_DEQUEUE(&p_aggr->freeQ); + } + + return buf; +} + + +static void +aggr_slice_amsdu(AGGR_INFO *p_aggr, RXTID *rxtid, void **osbuf) +{ + void *new_buf; + A_UINT16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len; + A_UINT8 *framep; + + /* Frame format at this point: + * [DIX hdr | 802.3 | 802.3 | ... | 802.3] + * + * Strip the DIX header. + * Iterate through the osbuf and do: + * grab a free netbuf from freeQ + * find the start and end of a frame + * copy it to netbuf(Vista can do better here) + * convert all msdu's(802.3) frames to upper layer format - os routine + * -for now lets convert from 802.3 to dix + * enque this to dispatch q of tid + * repeat + * free the osbuf - to OS. It's been sliced. + */ + + mac_hdr_len = sizeof(ATH_MAC_HDR); + framep = A_NETBUF_DATA(*osbuf) + mac_hdr_len; + amsdu_len = A_NETBUF_LEN(*osbuf) - mac_hdr_len; + + while(amsdu_len > mac_hdr_len) { + /* Begin of a 802.3 frame */ + payload_8023_len = A_BE2CPU16(((ATH_MAC_HDR *)framep)->typeOrLen); +#define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508 +#define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46 + if(payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN || payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) { + A_PRINTF("802.3 AMSDU frame bound check failed. len %d\n", payload_8023_len); + break; + } + frame_8023_len = payload_8023_len + mac_hdr_len; + new_buf = aggr_get_osbuf(p_aggr); + if(new_buf == NULL) { + A_PRINTF("No buffer available \n"); + break; + } + + A_MEMCPY(A_NETBUF_DATA(new_buf), framep, frame_8023_len); + A_NETBUF_PUT(new_buf, frame_8023_len); + if (wmi_dot3_2_dix(new_buf) != A_OK) { + A_PRINTF("dot3_2_dix err..\n"); + A_NETBUF_FREE(new_buf); + break; + } + + A_NETBUF_ENQUEUE(&rxtid->q, new_buf); + + /* Is this the last subframe within this aggregate ? */ + if ((amsdu_len - frame_8023_len) == 0) { + break; + } + + /* Add the length of A-MSDU subframe padding bytes - + * Round to nearest word. + */ + frame_8023_len = ((frame_8023_len + 3) & ~3); + + framep += frame_8023_len; + amsdu_len -= frame_8023_len; + } + + A_NETBUF_FREE(*osbuf); + *osbuf = NULL; +} + +void +aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + RXTID *rxtid; + RXTID_STATS *stats; + A_UINT16 idx, st, cur, end; + A_UINT16 *log_idx; + OSBUF_HOLD_Q *node; + PACKET_LOG *log; + + A_ASSERT(p_aggr); + A_ASSERT(tid < NUM_OF_TIDS); + + rxtid = AGGR_GET_RXTID(p_aggr, tid); + stats = AGGR_GET_RXTID_STATS(p_aggr, tid); + + stats->num_into_aggr++; + + if(!rxtid->aggr) { + if(is_amsdu) { + aggr_slice_amsdu(p_aggr, rxtid, osbuf); + stats->num_amsdu++; + aggr_dispatch_frames(p_aggr, &rxtid->q); + } + return; + } + + /* Check the incoming sequence no, if it's in the window */ + st = rxtid->seq_next; + cur = seq_no; + end = (st + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO; + /* Log the pkt info for future analysis */ + log = &p_aggr->pkt_log; + log_idx = &log->last_idx; + log->info[*log_idx].cur = cur; + log->info[*log_idx].st = st; + log->info[*log_idx].end = end; + *log_idx = IEEE80211_NEXT_SEQ_NO(*log_idx); + + if(((st < end) && (cur < st || cur > end)) || + ((st > end) && (cur > end) && (cur < st))) { + /* the cur frame is outside the window. Since we know + * our target would not do this without reason it must + * be assumed that the window has moved for some valid reason. + * Therefore, we dequeue all frames and start fresh. + */ + A_UINT16 extended_end; + + extended_end = (end + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO; + + if(((end < extended_end) && (cur < end || cur > extended_end)) || + ((end > extended_end) && (cur > extended_end) && (cur < end))) { + // dequeue all frames in queue and shift window to new frame + aggr_deque_frms(p_aggr, tid, 0, ALL_SEQNO); + //set window start so that new frame is last frame in window + if(cur >= rxtid->hold_q_sz-1) { + rxtid->seq_next = cur - (rxtid->hold_q_sz-1); + }else{ + rxtid->seq_next = IEEE80211_MAX_SEQ_NO - (rxtid->hold_q_sz-2 - cur); + } + } else { + // dequeue only those frames that are outside the new shifted window + if(cur >= rxtid->hold_q_sz-1) { + st = cur - (rxtid->hold_q_sz-1); + }else{ + st = IEEE80211_MAX_SEQ_NO - (rxtid->hold_q_sz-2 - cur); + } + + aggr_deque_frms(p_aggr, tid, st, ALL_SEQNO); + } + + stats->num_oow++; + } + + idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz); + + /*enque the frame, in hold_q */ + node = &rxtid->hold_q[idx]; + + A_MUTEX_LOCK(&rxtid->lock); + if(node->osbuf) { + /* Is the cur frame duplicate or something beyond our + * window(hold_q -> which is 2x, already)? + * 1. Duplicate is easy - drop incoming frame. + * 2. Not falling in current sliding window. + * 2a. is the frame_seq_no preceding current tid_seq_no? + * -> drop the frame. perhaps sender did not get our ACK. + * this is taken care of above. + * 2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ); + * -> Taken care of it above, by moving window forward. + * + */ + A_NETBUF_FREE(node->osbuf); + stats->num_dups++; + } + + node->osbuf = *osbuf; + node->is_amsdu = is_amsdu; + node->seq_no = seq_no; + if(node->is_amsdu) { + stats->num_amsdu++; + } else { + stats->num_mpdu++; + } + A_MUTEX_UNLOCK(&rxtid->lock); + + *osbuf = NULL; + aggr_deque_frms(p_aggr, tid, 0, CONTIGUOUS_SEQNO); + + if(p_aggr->timerScheduled) { + rxtid->progress = TRUE; + }else{ + for(idx=0 ; idxhold_q_sz ; idx++) { + if(rxtid->hold_q[idx].osbuf) { + /* there is a frame in the queue and no timer so + * start a timer to ensure that the frame doesn't remain + * stuck forever. */ + p_aggr->timerScheduled = TRUE; + A_TIMEOUT_MS(&p_aggr->timer, AGGR_RX_TIMEOUT, 0); + rxtid->progress = FALSE; + rxtid->timerMon = TRUE; + break; + } + } + } +} + +/* + * aggr_reset_state -- Called when it is deemed necessary to clear the aggregate + * hold Q state. Examples include when a Connect event or disconnect event is + * received. + */ +void +aggr_reset_state(void *cntxt) +{ + A_UINT8 tid; + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + + A_ASSERT(p_aggr); + + for(tid=0 ; tidaggr == FALSE || + rxtid->timerMon == FALSE || + rxtid->progress == TRUE) { + continue; + } + // dequeue all frames in for this tid + stats->num_timeouts++; + A_PRINTF("TO: st %d end %d\n", rxtid->seq_next, ((rxtid->seq_next + rxtid->hold_q_sz-1) & IEEE80211_MAX_SEQ_NO)); + aggr_deque_frms(p_aggr, i, 0, ALL_SEQNO); + } + + p_aggr->timerScheduled = FALSE; + // determine whether a new timer should be started. + for(i = 0; i < NUM_OF_TIDS; i++) { + rxtid = AGGR_GET_RXTID(p_aggr, i); + + if(rxtid->aggr == TRUE && rxtid->hold_q) { + for(j = 0 ; j < rxtid->hold_q_sz ; j++) + { + if(rxtid->hold_q[j].osbuf) + { + p_aggr->timerScheduled = TRUE; + rxtid->timerMon = TRUE; + rxtid->progress = FALSE; + break; + } + } + + if(j >= rxtid->hold_q_sz) { + rxtid->timerMon = FALSE; + } + } + } + + if(p_aggr->timerScheduled) { + /* Rearm the timer*/ + A_TIMEOUT_MS(&p_aggr->timer, AGGR_RX_TIMEOUT, 0); + } + +} + +static void +aggr_dispatch_frames(AGGR_INFO *p_aggr, A_NETBUF_QUEUE_T *q) +{ + void *osbuf; + + while((osbuf = A_NETBUF_DEQUEUE(q))) { + p_aggr->rx_fn(p_aggr->dev, osbuf); + } +} + +void +aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf) +{ + AGGR_INFO *p_aggr = (AGGR_INFO *)cntxt; + RXTID *rxtid; + RXTID_STATS *stats; + A_UINT8 i; + + *log_buf = &p_aggr->pkt_log; + A_PRINTF("\n\n================================================\n"); + A_PRINTF("tid: num_into_aggr, dups, oow, mpdu, amsdu, delivered, timeouts, holes, bar, seq_next\n"); + for(i = 0; i < NUM_OF_TIDS; i++) { + stats = AGGR_GET_RXTID_STATS(p_aggr, i); + rxtid = AGGR_GET_RXTID(p_aggr, i); + A_PRINTF("%d: %d %d %d %d %d %d %d %d %d : %d\n", i, stats->num_into_aggr, stats->num_dups, + stats->num_oow, stats->num_mpdu, + stats->num_amsdu, stats->num_delivered, stats->num_timeouts, + stats->num_hole, stats->num_bar, + rxtid->seq_next); + } + A_PRINTF("================================================\n\n"); + +} + +#endif /* ATH_AR6K_11N_SUPPORT */ diff --git a/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h b/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h new file mode 100644 index 000000000000..708b6b044d27 --- /dev/null +++ b/drivers/net/wireless/ath6kl/wlan/include/ieee80211.h @@ -0,0 +1,397 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _NET80211_IEEE80211_H_ +#define _NET80211_IEEE80211_H_ + +#include "athstartpack.h" + +/* + * 802.11 protocol definitions. + */ +#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ +#define IEEE80211_WEP_IVLEN 3 /* 24bit */ +#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ +#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ +#define IEEE80211_WEP_NKID 4 /* number of key ids */ + +/* + * 802.11i defines an extended IV for use with non-WEP ciphers. + * When the EXTIV bit is set in the key id byte an additional + * 4 bytes immediately follow the IV for TKIP. For CCMP the + * EXTIV bit is likewise set but the 8 bytes represent the + * CCMP header rather than IV+extended-IV. + */ +#define IEEE80211_WEP_EXTIV 0x20 +#define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */ +#define IEEE80211_WEP_MICLEN 8 /* trailing MIC */ + +#define IEEE80211_CRC_LEN 4 + +#ifdef WAPI_ENABLE +#define IEEE80211_WAPI_EXTIVLEN 10 /* extended IV length */ +#endif /* WAPI ENABLE */ + + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +/* is 802.11 address multicast/broadcast? */ +#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01) +#define IEEE80211_IS_BROADCAST(_a) (*(_a) == 0xFF) +#define WEP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN) +#define WEP_TRAILER IEEE80211_WEP_CRCLEN +#define CCMP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_EXTIVLEN) +#define CCMP_TRAILER IEEE80211_WEP_MICLEN +#define TKIP_HEADER (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + \ + IEEE80211_WEP_EXTIVLEN) +#define TKIP_TRAILER IEEE80211_WEP_CRCLEN +#define TKIP_MICLEN IEEE80211_WEP_MICLEN + + +#define IEEE80211_ADDR_EQ(addr1, addr2) \ + (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0) + +#define IEEE80211_ADDR_COPY(dst,src) A_MEMCPY(dst,src,IEEE80211_ADDR_LEN) + +#define IEEE80211_KEYBUF_SIZE 16 +#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx and rx */ + +/* + * NB: these values are ordered carefully; there are lots of + * of implications in any reordering. In particular beware + * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY. + */ +#define IEEE80211_CIPHER_WEP 0 +#define IEEE80211_CIPHER_TKIP 1 +#define IEEE80211_CIPHER_AES_OCB 2 +#define IEEE80211_CIPHER_AES_CCM 3 +#define IEEE80211_CIPHER_CKIP 5 +#define IEEE80211_CIPHER_CCKM_KRK 6 +#define IEEE80211_CIPHER_NONE 7 /* pseudo value */ + +#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE+1) + +#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \ + (((len) == 5) || ((len) == 13) || ((len) == 16)) + + + +/* + * generic definitions for IEEE 802.11 frames + */ +PREPACK struct ieee80211_frame { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} POSTPACK; + +PREPACK struct ieee80211_qosframe { + A_UINT8 i_fc[2]; + A_UINT8 i_dur[2]; + A_UINT8 i_addr1[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr2[IEEE80211_ADDR_LEN]; + A_UINT8 i_addr3[IEEE80211_ADDR_LEN]; + A_UINT8 i_seq[2]; + A_UINT8 i_qos[2]; +} POSTPACK; + +#define IEEE80211_FC0_VERSION_MASK 0x03 +#define IEEE80211_FC0_VERSION_SHIFT 0 +#define IEEE80211_FC0_VERSION_0 0x00 +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_SHIFT 2 +#define IEEE80211_FC0_TYPE_MGT 0x00 +#define IEEE80211_FC0_TYPE_CTL 0x04 +#define IEEE80211_FC0_TYPE_DATA 0x08 + +#define IEEE80211_FC0_SUBTYPE_MASK 0xf0 +#define IEEE80211_FC0_SUBTYPE_SHIFT 4 +/* for TYPE_MGT */ +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50 +#define IEEE80211_FC0_SUBTYPE_BEACON 0x80 +#define IEEE80211_FC0_SUBTYPE_ATIM 0x90 +#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0 +#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0 +#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0 +/* for TYPE_CTL */ +#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0 +#define IEEE80211_FC0_SUBTYPE_RTS 0xb0 +#define IEEE80211_FC0_SUBTYPE_CTS 0xc0 +#define IEEE80211_FC0_SUBTYPE_ACK 0xd0 +#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0 +/* for TYPE_DATA (bit combination) */ +#define IEEE80211_FC0_SUBTYPE_DATA 0x00 +#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10 +#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30 +#define IEEE80211_FC0_SUBTYPE_NODATA 0x40 +#define IEEE80211_FC0_SUBTYPE_CFACK 0x50 +#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0 + +#define IEEE80211_FC1_DIR_MASK 0x03 +#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ +#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ +#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ +#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ + +#define IEEE80211_FC1_MORE_FRAG 0x04 +#define IEEE80211_FC1_RETRY 0x08 +#define IEEE80211_FC1_PWR_MGT 0x10 +#define IEEE80211_FC1_MORE_DATA 0x20 +#define IEEE80211_FC1_WEP 0x40 +#define IEEE80211_FC1_ORDER 0x80 + +#define IEEE80211_SEQ_FRAG_MASK 0x000f +#define IEEE80211_SEQ_FRAG_SHIFT 0 +#define IEEE80211_SEQ_SEQ_MASK 0xfff0 +#define IEEE80211_SEQ_SEQ_SHIFT 4 + +#define IEEE80211_NWID_LEN 32 + +/* + * 802.11 rate set. + */ +#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */ +#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */ + +#define WMM_NUM_AC 4 /* 4 AC categories */ + +#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */ +#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */ +#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */ +#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */ +#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */ +#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */ +#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */ +#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */ + +#define WMM_AC_TO_TID(_ac) ( \ + ((_ac) == WMM_AC_VO) ? 6 : \ + ((_ac) == WMM_AC_VI) ? 5 : \ + ((_ac) == WMM_AC_BK) ? 1 : \ + 0) + +#define TID_TO_WMM_AC(_tid) ( \ + ((_tid) < 1) ? WMM_AC_BE : \ + ((_tid) < 3) ? WMM_AC_BK : \ + ((_tid) < 6) ? WMM_AC_VI : \ + WMM_AC_VO) +/* + * Management information element payloads. + */ + +enum { + IEEE80211_ELEMID_SSID = 0, + IEEE80211_ELEMID_RATES = 1, + IEEE80211_ELEMID_FHPARMS = 2, + IEEE80211_ELEMID_DSPARMS = 3, + IEEE80211_ELEMID_CFPARMS = 4, + IEEE80211_ELEMID_TIM = 5, + IEEE80211_ELEMID_IBSSPARMS = 6, + IEEE80211_ELEMID_COUNTRY = 7, + IEEE80211_ELEMID_CHALLENGE = 16, + /* 17-31 reserved for challenge text extension */ + IEEE80211_ELEMID_PWRCNSTR = 32, + IEEE80211_ELEMID_PWRCAP = 33, + IEEE80211_ELEMID_TPCREQ = 34, + IEEE80211_ELEMID_TPCREP = 35, + IEEE80211_ELEMID_SUPPCHAN = 36, + IEEE80211_ELEMID_CHANSWITCH = 37, + IEEE80211_ELEMID_MEASREQ = 38, + IEEE80211_ELEMID_MEASREP = 39, + IEEE80211_ELEMID_QUIET = 40, + IEEE80211_ELEMID_IBSSDFS = 41, + IEEE80211_ELEMID_ERP = 42, + IEEE80211_ELEMID_HTCAP_ANA = 45, /* Address ANA, and non-ANA story, for interop. CL#171733 */ + IEEE80211_ELEMID_RSN = 48, + IEEE80211_ELEMID_XRATES = 50, + IEEE80211_ELEMID_HTINFO_ANA = 61, +#ifdef WAPI_ENABLE + IEEE80211_ELEMID_WAPI = 68, +#endif + IEEE80211_ELEMID_TPC = 150, + IEEE80211_ELEMID_CCKM = 156, + IEEE80211_ELEMID_VENDOR = 221, /* vendor private */ +}; + +#define ATH_OUI 0x7f0300 /* Atheros OUI */ +#define ATH_OUI_TYPE 0x01 +#define ATH_OUI_SUBTYPE 0x01 +#define ATH_OUI_VERSION 0x00 + +#define WPA_OUI 0xf25000 +#define WPA_OUI_TYPE 0x01 +#define WPA_VERSION 1 /* current supported version */ + +#define WPA_CSE_NULL 0x00 +#define WPA_CSE_WEP40 0x01 +#define WPA_CSE_TKIP 0x02 +#define WPA_CSE_CCMP 0x04 +#define WPA_CSE_WEP104 0x05 + +#define WPA_ASE_NONE 0x00 +#define WPA_ASE_8021X_UNSPEC 0x01 +#define WPA_ASE_8021X_PSK 0x02 + +#define RSN_OUI 0xac0f00 +#define RSN_VERSION 1 /* current supported version */ + +#define RSN_CSE_NULL 0x00 +#define RSN_CSE_WEP40 0x01 +#define RSN_CSE_TKIP 0x02 +#define RSN_CSE_WRAP 0x03 +#define RSN_CSE_CCMP 0x04 +#define RSN_CSE_WEP104 0x05 + +#define RSN_ASE_NONE 0x00 +#define RSN_ASE_8021X_UNSPEC 0x01 +#define RSN_ASE_8021X_PSK 0x02 + +#define RSN_CAP_PREAUTH 0x01 + +#define WMM_OUI 0xf25000 +#define WMM_OUI_TYPE 0x02 +#define WMM_INFO_OUI_SUBTYPE 0x00 +#define WMM_PARAM_OUI_SUBTYPE 0x01 +#define WMM_VERSION 1 + +/* WMM stream classes */ +#define WMM_NUM_AC 4 +#define WMM_AC_BE 0 /* best effort */ +#define WMM_AC_BK 1 /* background */ +#define WMM_AC_VI 2 /* video */ +#define WMM_AC_VO 3 /* voice */ + +/* TSPEC related */ +#define ACTION_CATEGORY_CODE_TSPEC 17 +#define ACTION_CODE_TSPEC_ADDTS 0 +#define ACTION_CODE_TSPEC_ADDTS_RESP 1 +#define ACTION_CODE_TSPEC_DELTS 2 + +typedef enum { + TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0, + TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1, + TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3, + TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8, + TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9, + TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA, + TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB, + TSPEC_STATUS_CODE_DELTS_SENT = 0x30, + TSPEC_STATUS_CODE_DELTS_RECV = 0x31, +} TSPEC_STATUS_CODE; + +#define TSPEC_TSID_MASK 0xF +#define TSPEC_TSID_S 1 + +/* + * WMM/802.11e Tspec Element + */ +typedef PREPACK struct wmm_tspec_ie_t { + A_UINT8 elementId; + A_UINT8 len; + A_UINT8 oui[3]; + A_UINT8 ouiType; + A_UINT8 ouiSubType; + A_UINT8 version; + A_UINT16 tsInfo_info; + A_UINT8 tsInfo_reserved; + A_UINT16 nominalMSDU; + A_UINT16 maxMSDU; + A_UINT32 minServiceInt; + A_UINT32 maxServiceInt; + A_UINT32 inactivityInt; + A_UINT32 suspensionInt; + A_UINT32 serviceStartTime; + A_UINT32 minDataRate; + A_UINT32 meanDataRate; + A_UINT32 peakDataRate; + A_UINT32 maxBurstSize; + A_UINT32 delayBound; + A_UINT32 minPhyRate; + A_UINT16 sba; + A_UINT16 mediumTime; +} POSTPACK WMM_TSPEC_IE; + + +/* + * BEACON management packets + * + * octet timestamp[8] + * octet beacon interval[2] + * octet capability information[2] + * information element + * octet elemid + * octet length + * octet information[length] + */ + +#define IEEE80211_BEACON_INTERVAL(beacon) \ + ((beacon)[8] | ((beacon)[9] << 8)) +#define IEEE80211_BEACON_CAPABILITY(beacon) \ + ((beacon)[10] | ((beacon)[11] << 8)) + +#define IEEE80211_CAPINFO_ESS 0x0001 +#define IEEE80211_CAPINFO_IBSS 0x0002 +#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004 +#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008 +#define IEEE80211_CAPINFO_PRIVACY 0x0010 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020 +#define IEEE80211_CAPINFO_PBCC 0x0040 +#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080 +/* bits 8-9 are reserved */ +#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400 +#define IEEE80211_CAPINFO_APSD 0x0800 +/* bit 12 is reserved */ +#define IEEE80211_CAPINFO_DSSSOFDM 0x2000 +/* bits 14-15 are reserved */ + +/* + * Authentication Modes + */ + +enum ieee80211_authmode { + IEEE80211_AUTH_NONE = 0, + IEEE80211_AUTH_OPEN = 1, + IEEE80211_AUTH_SHARED = 2, + IEEE80211_AUTH_8021X = 3, + IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */ + /* NB: these are used only for ioctls */ + IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */ + IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */ + IEEE80211_AUTH_WPA_CCKM = 7, /* WPA/RSN IE w/ CCKM */ +}; + +#define IEEE80211_PS_MAX_QUEUE 50 /*Maximum no of buffers that can be queues for PS*/ + +#include "athendpack.h" + +#endif /* _NET80211_IEEE80211_H_ */ diff --git a/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h b/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h new file mode 100644 index 000000000000..faa1d653509e --- /dev/null +++ b/drivers/net/wireless/ath6kl/wlan/include/ieee80211_node.h @@ -0,0 +1,81 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// Author(s): ="Atheros" +//============================================================================== +#ifndef _IEEE80211_NODE_H_ +#define _IEEE80211_NODE_H_ + +/* + * Node locking definitions. + */ +#define IEEE80211_NODE_LOCK_INIT(_nt) A_MUTEX_INIT(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_DESTROY(_nt) if (A_IS_MUTEX_VALID(&(_nt)->nt_nodelock)) { \ + A_MUTEX_DELETE(&(_nt)->nt_nodelock); } + +#define IEEE80211_NODE_LOCK(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_BH(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_UNLOCK_BH(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock) +#define IEEE80211_NODE_LOCK_ASSERT(_nt) + +/* + * Node reference counting definitions. + * + * ieee80211_node_initref initialize the reference count to 1 + * ieee80211_node_incref add a reference + * ieee80211_node_decref remove a reference + * ieee80211_node_dectestref remove a reference and return 1 if this + * is the last reference, otherwise 0 + * ieee80211_node_refcnt reference count for printing (only) + */ +#define ieee80211_node_initref(_ni) ((_ni)->ni_refcnt = 1) +#define ieee80211_node_incref(_ni) ((_ni)->ni_refcnt++) +#define ieee80211_node_decref(_ni) ((_ni)->ni_refcnt--) +#define ieee80211_node_dectestref(_ni) (((_ni)->ni_refcnt--) == 1) +#define ieee80211_node_refcnt(_ni) ((_ni)->ni_refcnt) + +#define IEEE80211_NODE_HASHSIZE 32 +/* simple hash is enough for variation of macaddr */ +#define IEEE80211_NODE_HASH(addr) \ + (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \ + IEEE80211_NODE_HASHSIZE) + +/* + * Table of ieee80211_node instances. Each ieee80211com + * has at least one for holding the scan candidates. + * When operating as an access point or in ibss mode there + * is a second table for associated stations or neighbors. + */ +struct ieee80211_node_table { + void *nt_wmip; /* back reference */ + A_MUTEX_T nt_nodelock; /* on node table */ + struct bss *nt_node_first; /* information of all nodes */ + struct bss *nt_node_last; /* information of all nodes */ + struct bss *nt_hash[IEEE80211_NODE_HASHSIZE]; + const char *nt_name; /* for debugging */ + A_UINT32 nt_scangen; /* gen# for timeout scan */ + A_TIMER nt_inact_timer; + A_UINT8 isTimerArmed; /* is the node timer armed */ + A_UINT32 nt_nodeAge; /* node aging time */ +#ifdef OS_ROAM_MANAGEMENT + A_UINT32 nt_si_gen; /* gen# for scan indication*/ +#endif +}; + +#define WLAN_NODE_INACT_TIMEOUT_MSEC 120000 + +#endif /* _IEEE80211_NODE_H_ */ diff --git a/drivers/net/wireless/ath6kl/wlan/src/makefile b/drivers/net/wireless/ath6kl/wlan/src/makefile new file mode 100644 index 000000000000..6e53a111b67f --- /dev/null +++ b/drivers/net/wireless/ath6kl/wlan/src/makefile @@ -0,0 +1,22 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation; +# +# Software distributed under the License is distributed on an "AS +# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# +#------------------------------------------------------------------------------ +#============================================================================== +# Author(s): ="Atheros" +#============================================================================== +!INCLUDE $(_MAKEENVROOT)\makefile.def + + + diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c new file mode 100644 index 000000000000..4f87d031459c --- /dev/null +++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_node.c @@ -0,0 +1,569 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 node handling support. +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include +#define ATH_MODULE_NAME wlan +#include +#include "htc.h" +#include "htc_api.h" +#include +#include +#include +#include +#include + +#define ATH_DEBUG_WLAN ATH_DEBUG_MAKE_MODULE_MASK(0) + +#ifdef DEBUG + +static ATH_DEBUG_MASK_DESCRIPTION wlan_debug_desc[] = { + { ATH_DEBUG_WLAN , "General WLAN Node Tracing"}, +}; + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(wlan, + "wlan", + "WLAN Node Management", + ATH_DEBUG_MASK_DEFAULTS, + ATH_DEBUG_DESCRIPTION_COUNT(wlan_debug_desc), + wlan_debug_desc); + +#endif + +static void wlan_node_timeout(A_ATH_TIMER arg); + +static bss_t * _ieee80211_find_node (struct ieee80211_node_table *nt, + const A_UINT8 *macaddr); + +bss_t * +wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size) +{ + bss_t *ni; + + ni = A_MALLOC_NOWAIT(sizeof(bss_t)); + + if (ni != NULL) { + if (wh_size) + { + ni->ni_buf = A_MALLOC_NOWAIT(wh_size); + if (ni->ni_buf == NULL) { + A_FREE(ni); + ni = NULL; + return ni; + } + } + } else { + return ni; + } + + /* Make sure our lists are clean */ + ni->ni_list_next = NULL; + ni->ni_list_prev = NULL; + ni->ni_hash_next = NULL; + ni->ni_hash_prev = NULL; + + // + // ni_scangen never initialized before and during suspend/resume of winmobile, + // that some junk has been stored in this, due to this scan list didn't properly updated + // + ni->ni_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + ni->ni_si_gen = 0; +#endif + + return ni; +} + +void +wlan_node_free(bss_t *ni) +{ + if (ni->ni_buf != NULL) { + A_FREE(ni->ni_buf); + } + A_FREE(ni); +} + +void +wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni, + const A_UINT8 *macaddr) +{ + int hash; + A_UINT32 timeoutValue = 0; + + A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN); + hash = IEEE80211_NODE_HASH (macaddr); + ieee80211_node_initref (ni); /* mark referenced */ + + timeoutValue = nt->nt_nodeAge; + + ni->ni_tstamp = A_GET_MS (timeoutValue); + + IEEE80211_NODE_LOCK_BH(nt); + + /* Insert at the end of the node list */ + ni->ni_list_next = NULL; + ni->ni_list_prev = nt->nt_node_last; + if(nt->nt_node_last != NULL) + { + nt->nt_node_last->ni_list_next = ni; + } + nt->nt_node_last = ni; + if(nt->nt_node_first == NULL) + { + nt->nt_node_first = ni; + } + + /* Insert into the hash list i.e. the bucket */ + if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL) + { + nt->nt_hash[hash]->ni_hash_prev = ni; + } + ni->ni_hash_prev = NULL; + nt->nt_hash[hash] = ni; + + if (!nt->isTimerArmed) { + A_TIMEOUT_MS(&nt->nt_inact_timer, timeoutValue, 0); + nt->isTimerArmed = TRUE; + } + + IEEE80211_NODE_UNLOCK_BH(nt); +} + +static bss_t * +_ieee80211_find_node(struct ieee80211_node_table *nt, + const A_UINT8 *macaddr) +{ + bss_t *ni; + int hash; + + IEEE80211_NODE_LOCK_ASSERT(nt); + + hash = IEEE80211_NODE_HASH(macaddr); + for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) { + if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) { + ieee80211_node_incref(ni); /* mark referenced */ + return ni; + } + } + return NULL; +} + +bss_t * +wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr) +{ + bss_t *ni; + + IEEE80211_NODE_LOCK(nt); + ni = _ieee80211_find_node(nt, macaddr); + IEEE80211_NODE_UNLOCK(nt); + return ni; +} + +/* + * Reclaim a node. If this is the last reference count then + * do the normal free work. Otherwise remove it from the node + * table and mark it gone by clearing the back-reference. + */ +void +wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK(nt); + + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } + wlan_node_free(ni); + + IEEE80211_NODE_UNLOCK(nt); +} + +static void +wlan_node_dec_free(bss_t *ni) +{ + if (ieee80211_node_dectestref(ni)) { + wlan_node_free(ni); + } +} + +void +wlan_free_allnodes(struct ieee80211_node_table *nt) +{ + bss_t *ni; + + while ((ni = nt->nt_node_first) != NULL) { + wlan_node_reclaim(nt, ni); + } +} + +void +wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f, + void *arg) +{ + bss_t *ni; + A_UINT32 gen; + + gen = ++nt->nt_scangen; + + IEEE80211_NODE_LOCK(nt); + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + if (ni->ni_scangen != gen) { + ni->ni_scangen = gen; + (void) ieee80211_node_incref(ni); + (*f)(arg, ni); + wlan_node_dec_free(ni); + } + } + IEEE80211_NODE_UNLOCK(nt); +} + +/* + * Node table support. + */ +void +wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt) +{ + int i; + + AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt)); + IEEE80211_NODE_LOCK_INIT(nt); + + A_REGISTER_MODULE_DEBUG_INFO(wlan); + + nt->nt_node_first = nt->nt_node_last = NULL; + for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++) + { + nt->nt_hash[i] = NULL; + } + + A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt); + nt->isTimerArmed = FALSE; + nt->nt_wmip = wmip; + nt->nt_nodeAge = WLAN_NODE_INACT_TIMEOUT_MSEC; + + // + // nt_scangen never initialized before and during suspend/resume of winmobile, + // that some junk has been stored in this, due to this scan list didn't properly updated + // + nt->nt_scangen = 0; + +#ifdef OS_ROAM_MANAGEMENT + nt->nt_si_gen = 0; +#endif +} + +void +wlan_set_nodeage(struct ieee80211_node_table *nt, A_UINT32 nodeAge) +{ + nt->nt_nodeAge = nodeAge; + return; +} +static void +wlan_node_timeout (A_ATH_TIMER arg) +{ + struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg; + bss_t *bss, *nextBss; + A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE; + A_UINT32 timeoutValue = 0; + + timeoutValue = nt->nt_nodeAge; + + wmi_get_current_bssid(nt->nt_wmip, myBssid); + + bss = nt->nt_node_first; + while (bss != NULL) + { + nextBss = bss->ni_list_next; + if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0) + { + + if (bss->ni_tstamp <= A_GET_MS(0)) + { + /* + * free up all but the current bss - if set + */ + wlan_node_reclaim(nt, bss); + } + else + { + /* + * Re-arm timer, only when we have a bss other than + * current bss AND it is not aged-out. + */ + reArmTimer = TRUE; + } + } + bss = nextBss; + } + + if (reArmTimer) + A_TIMEOUT_MS (&nt->nt_inact_timer, timeoutValue, 0); + + nt->isTimerArmed = reArmTimer; +} + +void +wlan_node_table_cleanup(struct ieee80211_node_table *nt) +{ + A_UNTIMEOUT(&nt->nt_inact_timer); + A_DELETE_TIMER(&nt->nt_inact_timer); + wlan_free_allnodes(nt); + IEEE80211_NODE_LOCK_DESTROY(nt); +} + +bss_t * +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *ni = NULL; + A_UCHAR *pIESsid = NULL; + + IEEE80211_NODE_LOCK (nt); + + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + pIESsid = ni->ni_cie.ie_ssid; + if (pIESsid[1] <= 32) { + + // Step 1 : Check SSID + if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) { + + // + // Step 2.1 : Check MatchSSID is TRUE, if so, return Matched SSID + // Profile, otherwise check whether WPA2 or WPA + // + if (TRUE == bMatchSSID) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + + // Step 2 : if SSID matches, check WPA or WPA2 + if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) { + ieee80211_node_incref (ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) { + ieee80211_node_incref(ni); /* mark referenced */ + IEEE80211_NODE_UNLOCK (nt); + return ni; + } + } + } + } + + IEEE80211_NODE_UNLOCK (nt); + + return NULL; +} + +void +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni) +{ + IEEE80211_NODE_LOCK (nt); + wlan_node_dec_free (ni); + IEEE80211_NODE_UNLOCK (nt); +} + +void +wlan_node_remove_core (struct ieee80211_node_table *nt, bss_t *ni) +{ + if(ni->ni_list_prev == NULL) + { + /* First in list so fix the list head */ + nt->nt_node_first = ni->ni_list_next; + } + else + { + ni->ni_list_prev->ni_list_next = ni->ni_list_next; + } + + if(ni->ni_list_next == NULL) + { + /* Last in list so fix list tail */ + nt->nt_node_last = ni->ni_list_prev; + } + else + { + ni->ni_list_next->ni_list_prev = ni->ni_list_prev; + } + + if(ni->ni_hash_prev == NULL) + { + /* First in list so fix the list head */ + int hash; + hash = IEEE80211_NODE_HASH(ni->ni_macaddr); + nt->nt_hash[hash] = ni->ni_hash_next; + } + else + { + ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next; + } + + if(ni->ni_hash_next != NULL) + { + ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev; + } +} + +bss_t * +wlan_node_remove(struct ieee80211_node_table *nt, A_UINT8 *bssid) +{ + bss_t *bss, *nextBss; + + IEEE80211_NODE_LOCK(nt); + + bss = nt->nt_node_first; + + while (bss != NULL) + { + nextBss = bss->ni_list_next; + + if (A_MEMCMP(bssid, bss->ni_macaddr, 6) == 0) + { + wlan_node_remove_core (nt, bss); + IEEE80211_NODE_UNLOCK(nt); + return bss; + } + + bss = nextBss; + } + + IEEE80211_NODE_UNLOCK(nt); + return NULL; +} + +bss_t * +wlan_find_matching_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_UINT32 dot11AuthMode, A_UINT32 authMode, + A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp) +{ + bss_t *ni = NULL; + bss_t *best_ni = NULL; + A_UCHAR *pIESsid = NULL; + + IEEE80211_NODE_LOCK (nt); + + for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) { + pIESsid = ni->ni_cie.ie_ssid; + if (pIESsid[1] <= 32) { + + // Step 1 : Check SSID + if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) { + + if (ni->ni_cie.ie_capInfo & 0x10) + { + + if ((NULL != ni->ni_cie.ie_rsn) && (WPA2_PSK_AUTH == authMode)) + { + /* WPA2 */ + if (NULL == best_ni) + { + best_ni = ni; + } + else if (ni->ni_rssi > best_ni->ni_rssi) + { + best_ni = ni; + } + } + else if ((NULL != ni->ni_cie.ie_wpa) && (WPA_PSK_AUTH == authMode)) + { + /* WPA */ + if (NULL == best_ni) + { + best_ni = ni; + } + else if (ni->ni_rssi > best_ni->ni_rssi) + { + best_ni = ni; + } + } + else if (WEP_CRYPT == pairwiseCryptoType) + { + /* WEP */ + if (NULL == best_ni) + { + best_ni = ni; + } + else if (ni->ni_rssi > best_ni->ni_rssi) + { + best_ni = ni; + } + } + } + else + { + /* open AP */ + if ((OPEN_AUTH == authMode) && (NONE_CRYPT == pairwiseCryptoType)) + { + if (NULL == best_ni) + { + best_ni = ni; + } + else if (ni->ni_rssi > best_ni->ni_rssi) + { + best_ni = ni; + } + } + } + } + } + } + + IEEE80211_NODE_UNLOCK (nt); + + return best_ni; +} + diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c new file mode 100644 index 000000000000..0d5bce78165f --- /dev/null +++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_recv_beacon.c @@ -0,0 +1,196 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// IEEE 802.11 input handling. +// +// Author(s): ="Atheros" +//============================================================================== + +#include "a_config.h" +#include "athdefs.h" +#include "a_types.h" +#include "a_osapi.h" +#include +#include +#include + +#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do { \ + if ((_len) < (_minlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + +#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do { \ + if ((__elem) == NULL) { \ + return A_EINVAL; \ + } \ + if ((__elem)[1] > (__maxlen)) { \ + return A_EINVAL; \ + } \ +} while (0) + + +/* unaligned little endian access */ +#define LE_READ_2(p) \ + ((A_UINT16) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8))) + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + + +static int __inline +iswpaoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI); +} + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +/* unused functions for now */ +#if 0 +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + +static int __inline +iswmminfo(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE; +} +#endif + +static int __inline +isatherosoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI); +} + +static int __inline +iswscoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI); +} + +A_STATUS +wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie) +{ + A_UINT8 *frm, *efrm; + A_UINT8 elemid_ssid = FALSE; + + frm = buf; + efrm = (A_UINT8 *) (frm + framelen); + + /* + * beacon/probe response frame format + * [8] time stamp + * [2] beacon interval + * [2] capability information + * [tlv] ssid + * [tlv] supported rates + * [tlv] country information + * [tlv] parameter set (FH/DS) + * [tlv] erp information + * [tlv] extended supported rates + * [tlv] WMM + * [tlv] WPA or RSN + * [tlv] Atheros Advanced Capabilities + */ + IEEE80211_VERIFY_LENGTH(efrm - frm, 12); + A_MEMZERO(cie, sizeof(*cie)); + + cie->ie_tstamp = frm; frm += 8; + cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2; + cie->ie_chan = 0; + + while (frm < efrm) { + switch (*frm) { + case IEEE80211_ELEMID_SSID: + if (!elemid_ssid) { + cie->ie_ssid = frm; + elemid_ssid = TRUE; + } + break; + case IEEE80211_ELEMID_RATES: + cie->ie_rates = frm; + break; + case IEEE80211_ELEMID_COUNTRY: + cie->ie_country = frm; + break; + case IEEE80211_ELEMID_FHPARMS: + break; + case IEEE80211_ELEMID_DSPARMS: + cie->ie_chan = frm[2]; + break; + case IEEE80211_ELEMID_TIM: + cie->ie_tim = frm; + break; + case IEEE80211_ELEMID_IBSSPARMS: + break; + case IEEE80211_ELEMID_XRATES: + cie->ie_xrates = frm; + break; + case IEEE80211_ELEMID_ERP: + if (frm[1] != 1) { + //A_PRINTF("Discarding ERP Element - Bad Len\n"); + return A_EINVAL; + } + cie->ie_erp = frm[2]; + break; + case IEEE80211_ELEMID_RSN: + cie->ie_rsn = frm; + break; + case IEEE80211_ELEMID_HTCAP_ANA: + cie->ie_htcap = frm; + break; + case IEEE80211_ELEMID_HTINFO_ANA: + cie->ie_htop = frm; + break; +#ifdef WAPI_ENABLE + case IEEE80211_ELEMID_WAPI: + cie->ie_wapi = frm; + break; +#endif + case IEEE80211_ELEMID_VENDOR: + if (iswpaoui(frm)) { + cie->ie_wpa = frm; + } else if (iswmmoui(frm)) { + cie->ie_wmm = frm; + } else if (isatherosoui(frm)) { + cie->ie_ath = frm; + } else if(iswscoui(frm)) { + cie->ie_wsc = frm; + } + break; + default: + break; + } + frm += frm[1] + 2; + } + IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE); + IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN); + + return A_OK; +} diff --git a/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c b/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c new file mode 100644 index 000000000000..0d1c24ec1ca6 --- /dev/null +++ b/drivers/net/wireless/ath6kl/wlan/src/wlan_utils.c @@ -0,0 +1,57 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements frequently used wlan utilies +// +// Author(s): ="Atheros" +//============================================================================== +#include +#include +#include +#include + +/* + * converts ieee channel number to frequency + */ +A_UINT16 +wlan_ieee2freq(int chan) +{ + if (chan == 14) { + return 2484; + } + if (chan < 14) { /* 0-13 */ + return (2407 + (chan*5)); + } + if (chan < 27) { /* 15-26 */ + return (2512 + ((chan-15)*20)); + } + return (5000 + (chan*5)); +} + +/* + * Converts MHz frequency to IEEE channel number. + */ +A_UINT32 +wlan_freq2ieee(A_UINT16 freq) +{ + if (freq == 2484) + return 14; + if (freq < 2484) + return (freq - 2407) / 5; + if (freq < 5000) + return 15 + ((freq - 2512) / 20); + return (freq - 5000) / 5; +} diff --git a/drivers/net/wireless/ath6kl/wmi/makefile b/drivers/net/wireless/ath6kl/wmi/makefile new file mode 100644 index 000000000000..6e53a111b67f --- /dev/null +++ b/drivers/net/wireless/ath6kl/wmi/makefile @@ -0,0 +1,22 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2005-2007 Atheros Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation; +# +# Software distributed under the License is distributed on an "AS +# IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# +#------------------------------------------------------------------------------ +#============================================================================== +# Author(s): ="Atheros" +#============================================================================== +!INCLUDE $(_MAKEENVROOT)\makefile.def + + + diff --git a/drivers/net/wireless/ath6kl/wmi/wmi.c b/drivers/net/wireless/ath6kl/wmi/wmi.c new file mode 100644 index 000000000000..3a7667d2c39e --- /dev/null +++ b/drivers/net/wireless/ath6kl/wmi/wmi.c @@ -0,0 +1,6536 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This module implements the hardware independent layer of the +// Wireless Module Interface (WMI) protocol. +// +// Author(s): ="Atheros" +//============================================================================== + +#include +#include +#include +#include +#include "htc.h" +#include "htc_api.h" +#include "wmi.h" +#include +#include +#include +#include +#include "dset_api.h" +#include "gpio_api.h" +#include "wmi_host.h" +#include "a_drv.h" +#include "a_drv_api.h" +#define ATH_MODULE_NAME wmi +#include "a_debug.h" +#include "dbglog_api.h" +#include "roaming.h" + +#define ATH_DEBUG_WMI ATH_DEBUG_MAKE_MODULE_MASK(0) + +#ifdef DEBUG + +static ATH_DEBUG_MASK_DESCRIPTION wmi_debug_desc[] = { + { ATH_DEBUG_WMI , "General WMI Tracing"}, +}; + +ATH_DEBUG_INSTANTIATE_MODULE_VAR(wmi, + "wmi", + "Wireless Module Interface", + ATH_DEBUG_MASK_DEFAULTS, + ATH_DEBUG_DESCRIPTION_COUNT(wmi_debug_desc), + wmi_debug_desc); + +#endif + +#ifndef REXOS +#define DBGARG _A_FUNCNAME_ +#define DBGFMT "%s() : " +#define DBG_WMI ATH_DEBUG_WMI +#define DBG_ERROR ATH_DEBUG_ERR +#define DBG_WMI2 ATH_DEBUG_WMI +#define A_DPRINTF AR_DEBUG_PRINTF +#endif + +static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_sync_point(struct wmi_t *wmip); + +static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#endif /* CONFIG_HOST_DSET_SUPPORT */ + + +static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +static A_STATUS +wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len); + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex); + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); + +A_STATUS wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag); + +A_UINT8 ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); +A_UINT8 ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, A_UINT32 size); + +void wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +void wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +static A_STATUS wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd); +static A_STATUS wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd); +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +static A_STATUS wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +static A_STATUS wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); + +static A_STATUS wmi_peer_node_event_rx (struct wmi_t *wmip, A_UINT8 *datap, + int len); +#ifdef ATH_AR6K_11N_SUPPORT +static A_STATUS wmi_addba_req_event_rx(struct wmi_t *, A_UINT8 *, int); +static A_STATUS wmi_addba_resp_event_rx(struct wmi_t *, A_UINT8 *, int); +static A_STATUS wmi_delba_req_event_rx(struct wmi_t *, A_UINT8 *, int); +static A_STATUS wmi_btcoex_config_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +static A_STATUS wmi_btcoex_stats_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len); +#endif +static A_STATUS wmi_hci_event_rx(struct wmi_t *, A_UINT8 *, int); + +#ifdef WAPI_ENABLE +static A_STATUS wmi_wapi_rekey_event_rx(struct wmi_t *wmip, A_UINT8 *datap, + int len); +#endif + +#if defined(UNDER_CE) +#if defined(NDIS51_MINIPORT) +unsigned int processDot11Hdr = 0; +#else +unsigned int processDot11Hdr = 1; +#endif +#else +extern unsigned int processDot11Hdr; +#endif + +int wps_enable; +static const A_INT32 wmi_rateTable[][2] = { + //{W/O SGI, with SGI} + {1000, 1000}, + {2000, 2000}, + {5500, 5500}, + {11000, 11000}, + {6000, 6000}, + {9000, 9000}, + {12000, 12000}, + {18000, 18000}, + {24000, 24000}, + {36000, 36000}, + {48000, 48000}, + {54000, 54000}, + {6500, 7200}, + {13000, 14400}, + {19500, 21700}, + {26000, 28900}, + {39000, 43300}, + {52000, 57800}, + {58500, 65000}, + {65000, 72200}, + {13500, 15000}, + {27000, 30000}, + {40500, 45000}, + {54000, 60000}, + {81000, 90000}, + {108000, 120000}, + {121500, 135000}, + {135000, 150000}, + {0, 0}}; + +#define MODE_A_SUPPORT_RATE_START ((A_INT32) 4) +#define MODE_A_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START +#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP + +#define MODE_B_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_B_SUPPORT_RATE_STOP ((A_INT32) 3) + +#define MODE_G_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_G_SUPPORT_RATE_STOP ((A_INT32) 11) + +#define MODE_GHT20_SUPPORT_RATE_START ((A_INT32) 0) +#define MODE_GHT20_SUPPORT_RATE_STOP ((A_INT32) 19) + +#define MAX_NUMBER_OF_SUPPORT_RATES (MODE_GHT20_SUPPORT_RATE_STOP + 1) + +/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */ +const A_UINT8 up_to_ac[]= { + WMM_AC_BE, + WMM_AC_BK, + WMM_AC_BK, + WMM_AC_BE, + WMM_AC_VI, + WMM_AC_VI, + WMM_AC_VO, + WMM_AC_VO, + }; + +#include "athstartpack.h" + +/* This stuff is used when we want a simple layer-3 visibility */ +typedef PREPACK struct _iphdr { + A_UINT8 ip_ver_hdrlen; /* version and hdr length */ + A_UINT8 ip_tos; /* type of service */ + A_UINT16 ip_len; /* total length */ + A_UINT16 ip_id; /* identification */ + A_INT16 ip_off; /* fragment offset field */ +#define IP_DF 0x4000 /* dont fragment flag */ +#define IP_MF 0x2000 /* more fragments flag */ +#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ + A_UINT8 ip_ttl; /* time to live */ + A_UINT8 ip_p; /* protocol */ + A_UINT16 ip_sum; /* checksum */ + A_UINT8 ip_src[4]; /* source and dest address */ + A_UINT8 ip_dst[4]; +} POSTPACK iphdr; + +#include "athendpack.h" + +A_INT16 rssi_event_value = 0; +A_INT16 snr_event_value = 0; + +A_BOOL is_probe_ssid = FALSE; + +void * +wmi_init(void *devt) +{ + struct wmi_t *wmip; + + A_REGISTER_MODULE_DEBUG_INFO(wmi); + + wmip = A_MALLOC(sizeof(struct wmi_t)); + if (wmip == NULL) { + return (NULL); + } + A_MEMZERO(wmip, sizeof(*wmip)); + A_MUTEX_INIT(&wmip->wmi_lock); + wmip->wmi_devt = devt; + wlan_node_table_init(wmip, &wmip->wmi_scan_table); + wmi_qos_state_init(wmip); + + wmip->wmi_powerMode = REC_POWER; + wmip->wmi_phyMode = WMI_11G_MODE; + + wmip->wmi_pair_crypto_type = NONE_CRYPT; + wmip->wmi_grp_crypto_type = NONE_CRYPT; + + return (wmip); +} + +void +wmi_qos_state_init(struct wmi_t *wmip) +{ + A_UINT8 i; + + if (wmip == NULL) { + return; + } + LOCK_WMI(wmip); + + /* Initialize QoS States */ + wmip->wmi_numQoSStream = 0; + + wmip->wmi_fatPipeExists = 0; + + for (i=0; i < WMM_NUM_AC; i++) { + wmip->wmi_streamExistsForAC[i]=0; + } + + UNLOCK_WMI(wmip); + + A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1); +} + +void +wmi_set_control_ep(struct wmi_t * wmip, HTC_ENDPOINT_ID eid) +{ + A_ASSERT( eid != ENDPOINT_UNUSED); + wmip->wmi_endpoint_id = eid; +} + +HTC_ENDPOINT_ID +wmi_get_control_ep(struct wmi_t * wmip) +{ + return(wmip->wmi_endpoint_id); +} + +void +wmi_shutdown(struct wmi_t *wmip) +{ + if (wmip != NULL) { + wlan_node_table_cleanup(&wmip->wmi_scan_table); + if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) { + A_MUTEX_DELETE(&wmip->wmi_lock); + } + A_FREE(wmip); + } +} + +/* + * performs DIX to 802.3 encapsulation for transmit packets. + * uses passed in buffer. Returns buffer or NULL if failed. + * Assumes the entire DIX header is contigous and that there is + * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers. + */ +A_STATUS +wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { + /* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + return (A_OK); + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + + return (A_OK); +} + +A_STATUS wmi_meta_add(struct wmi_t *wmip, void *osbuf, A_UINT8 *pVersion,void *pTxMetaS) +{ + switch(*pVersion){ + case 0: + return (A_OK); + case WMI_META_VERSION_1: + { + WMI_TX_META_V1 *pV1= NULL; + A_ASSERT(osbuf != NULL); + if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) { + return A_NO_MEMORY; + } + + pV1 = (WMI_TX_META_V1 *)A_NETBUF_DATA(osbuf); + /* the pktID is used in conjunction with txComplete messages + * allowing the target to notify which tx requests have been + * completed and how. */ + pV1->pktID = 0; + /* the ratePolicyID allows the host to specify which rate policy + * to use for transmitting this packet. 0 means use default behavior. */ + pV1->ratePolicyID = 0; + A_ASSERT(pVersion != NULL); + /* the version must be used to populate the meta field of the WMI_DATA_HDR */ + *pVersion = WMI_META_VERSION_1; + return (A_OK); + } +#ifdef CONFIG_CHECKSUM_OFFLOAD + case WMI_META_VERSION_2: + { + WMI_TX_META_V2 *pV2 ; + A_ASSERT(osbuf != NULL); + if (A_NETBUF_PUSH(osbuf, WMI_MAX_TX_META_SZ) != A_OK) { + return A_NO_MEMORY; + } + pV2 = (WMI_TX_META_V2 *)A_NETBUF_DATA(osbuf); + A_MEMCPY(pV2,(WMI_TX_META_V2 *)pTxMetaS,sizeof(WMI_TX_META_V2)); + return (A_OK); + } +#endif + default: + return (A_OK); + } +} + +/* Adds a WMI data header */ +A_STATUS +wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType, A_BOOL bMoreData, + WMI_DATA_HDR_DATA_TYPE data_type,A_UINT8 metaVersion, void *pTxMetaS) +{ + WMI_DATA_HDR *dtHdr; +// A_UINT8 metaVersion = 0; + A_STATUS status; + + A_ASSERT(osbuf != NULL); + + /* adds the meta data field after the wmi data hdr. If metaVersion + * is returns 0 then no meta field was added. */ + if ((status = wmi_meta_add(wmip, osbuf, &metaVersion,pTxMetaS)) != A_OK) { + return status; + } + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + A_MEMZERO(dtHdr, sizeof(WMI_DATA_HDR)); + + WMI_DATA_HDR_SET_MSG_TYPE(dtHdr, msgType); + WMI_DATA_HDR_SET_DATA_TYPE(dtHdr, data_type); + + if (bMoreData) { + WMI_DATA_HDR_SET_MORE_BIT(dtHdr); + } + + WMI_DATA_HDR_SET_META(dtHdr, metaVersion); + //dtHdr->rssi = 0; + + return (A_OK); +} + + +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT32 layer2Priority, A_BOOL wmmEnabled) +{ + A_UINT8 *datap; + A_UINT8 trafficClass = WMM_AC_BE; + A_UINT16 ipType = IP_ETHERTYPE; + WMI_DATA_HDR *dtHdr; + A_BOOL streamExists = FALSE; + A_UINT8 userPriority; + A_UINT32 hdrsize, metasize; + ATH_LLC_SNAP_HDR *llcHdr; + + WMI_CREATE_PSTREAM_CMD cmd; + + A_ASSERT(osbuf != NULL); + + // + // Initialize header size + // + hdrsize = 0; + + datap = A_NETBUF_DATA(osbuf); + dtHdr = (WMI_DATA_HDR *)datap; + metasize = (WMI_DATA_HDR_GET_META(dtHdr))? WMI_MAX_TX_META_SZ : 0; + + if (!wmmEnabled) + { + /* If WMM is disabled all traffic goes as BE traffic */ + userPriority = 0; + } + else + { + if (processDot11Hdr) + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize + + hdrsize); + + + } + else + { + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) + metasize + + sizeof(ATH_MAC_HDR)); + } + + if (llcHdr->etherType == A_CPU2BE16(ipType)) + { + /* Extract the endpoint info from the TOS field in the IP header */ + + userPriority = wmi_determine_userPriority (((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR),layer2Priority); + } + else + { + userPriority = layer2Priority & 0x7; + } + } + + trafficClass = convert_userPriority_to_trafficClass(userPriority); + + WMI_DATA_HDR_SET_UP(dtHdr, userPriority); + //dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT; /* lower 3-bits are 802.1d priority */ + + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + if (!(streamExists & (1 << trafficClass))) + { + + A_MEMZERO(&cmd, sizeof(cmd)); + cmd.trafficClass = trafficClass; + cmd.userPriority = userPriority; + cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT; + /* Implicit streams are created with TSID 0xFF */ + + cmd.tsid = WMI_IMPLICIT_PSTREAM; + wmi_create_pstream_cmd(wmip, &cmd); + } + + return trafficClass; +} + +A_STATUS +wmi_dot11_hdr_add (struct wmi_t *wmip, void *osbuf, NETWORK_TYPE mode) +{ + A_UINT8 *datap; + A_UINT16 typeorlen; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + struct ieee80211_frame *wh; + A_UINT32 hdrsize; + + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_HEADROOM(osbuf) < + (sizeof(struct ieee80211_qosframe) + sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR))) + { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN); + + if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) { +/* + * packet is already in 802.3 format - return success + */ + A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG)); + goto AddDot11Hdr; + } + + /* + * Save mac fields and length to be inserted later + */ + A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN); + A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN); + macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) + + sizeof(ATH_LLC_SNAP_HDR)); + + // Remove the Ethernet hdr + A_NETBUF_PULL(osbuf, sizeof(ATH_MAC_HDR)); + /* + * Make room for LLC+SNAP headers + */ + if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + datap = A_NETBUF_DATA(osbuf); + + llcHdr = (ATH_LLC_SNAP_HDR *)(datap); + llcHdr->dsap = 0xAA; + llcHdr->ssap = 0xAA; + llcHdr->cntl = 0x03; + llcHdr->orgCode[0] = 0x0; + llcHdr->orgCode[1] = 0x0; + llcHdr->orgCode[2] = 0x0; + llcHdr->etherType = typeorlen; + +AddDot11Hdr: + /* Make room for 802.11 hdr */ + if (wmip->wmi_is_wmm_enabled) + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK) + { + return A_NO_MEMORY; + } + wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf); + wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_QOS; + } + else + { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_frame),sizeof(A_UINT32)); + if (A_NETBUF_PUSH(osbuf, hdrsize) != A_OK) + { + return A_NO_MEMORY; + } + wh = (struct ieee80211_frame *) A_NETBUF_DATA(osbuf); + wh->i_fc[0] = IEEE80211_FC0_SUBTYPE_DATA; + } + /* Setup the SA & DA */ + IEEE80211_ADDR_COPY(wh->i_addr2, macHdr.srcMac); + + if (mode == INFRA_NETWORK) { + IEEE80211_ADDR_COPY(wh->i_addr3, macHdr.dstMac); + } + else if (mode == ADHOC_NETWORK) { + IEEE80211_ADDR_COPY(wh->i_addr1, macHdr.dstMac); + } + + return (A_OK); +} + +A_STATUS +wmi_dot11_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_UINT8 *datap; + struct ieee80211_frame *pwh,wh; + A_UINT8 type,subtype; + ATH_LLC_SNAP_HDR *llcHdr; + ATH_MAC_HDR macHdr; + A_UINT32 hdrsize; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + pwh = (struct ieee80211_frame *)datap; + type = pwh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; + subtype = pwh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; + + A_MEMCPY((A_UINT8 *)&wh, datap, sizeof(struct ieee80211_frame)); + + /* strip off the 802.11 hdr*/ + if (subtype == IEEE80211_FC0_SUBTYPE_QOS) { + hdrsize = A_ROUND_UP(sizeof(struct ieee80211_qosframe),sizeof(A_UINT32)); + A_NETBUF_PULL(osbuf, hdrsize); + } else if (subtype == IEEE80211_FC0_SUBTYPE_DATA) { + A_NETBUF_PULL(osbuf, sizeof(struct ieee80211_frame)); + } + + datap = A_NETBUF_DATA(osbuf); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap); + + macHdr.typeOrLen = llcHdr->etherType; + + switch (wh.i_fc[1] & IEEE80211_FC1_DIR_MASK) { + case IEEE80211_FC1_DIR_NODS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2); + break; + case IEEE80211_FC1_DIR_TODS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr3); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr2); + break; + case IEEE80211_FC1_DIR_FROMDS: + IEEE80211_ADDR_COPY(macHdr.dstMac, wh.i_addr1); + IEEE80211_ADDR_COPY(macHdr.srcMac, wh.i_addr3); + break; + case IEEE80211_FC1_DIR_DSTODS: + break; + } + + // Remove the LLC Hdr. + A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)); + + // Insert the ATH MAC hdr. + + A_NETBUF_PUSH(osbuf, sizeof(ATH_MAC_HDR)); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY (datap, &macHdr, sizeof(ATH_MAC_HDR)); + + return A_OK; +} + +/* + * performs 802.3 to DIX encapsulation for received packets. + * Assumes the entire 802.3 header is contigous. + */ +A_STATUS +wmi_dot3_2_dix(void *osbuf) +{ + A_UINT8 *datap; + ATH_MAC_HDR macHdr; + ATH_LLC_SNAP_HDR *llcHdr; + + A_ASSERT(osbuf != NULL); + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR)); + llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR)); + macHdr.typeOrLen = llcHdr->etherType; + + if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + datap = A_NETBUF_DATA(osbuf); + + A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR)); + + return (A_OK); +} + +/* + * Removes a WMI data header + */ +A_STATUS +wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf) +{ + A_ASSERT(osbuf != NULL); + + return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR))); +} + +void +wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg) +{ + wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg); +} + +/* + * WMI Extended Event received from Target. + */ +A_STATUS +wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf) +{ + WMIX_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len; + A_STATUS status = A_OK; + + if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + return A_ERROR; + } + + cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + switch (id) { + case (WMIX_DSETOPENREQ_EVENTID): + status = wmi_dset_open_req_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_DSET_SUPPORT + case (WMIX_DSETCLOSE_EVENTID): + status = wmi_dset_close_rx(wmip, datap, len); + break; + case (WMIX_DSETDATAREQ_EVENTID): + status = wmi_dset_data_req_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_DSET_SUPPORT */ +#ifdef CONFIG_HOST_GPIO_SUPPORT + case (WMIX_GPIO_INTR_EVENTID): + wmi_gpio_intr_rx(wmip, datap, len); + break; + case (WMIX_GPIO_DATA_EVENTID): + wmi_gpio_data_rx(wmip, datap, len); + break; + case (WMIX_GPIO_ACK_EVENTID): + wmi_gpio_ack_rx(wmip, datap, len); + break; +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + case (WMIX_HB_CHALLENGE_RESP_EVENTID): + wmi_hbChallengeResp_rx(wmip, datap, len); + break; + case (WMIX_DBGLOG_EVENTID): + wmi_dbglog_event_rx(wmip, datap, len); + break; +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) + case (WMIX_PROF_COUNT_EVENTID): + wmi_prof_count_rx(wmip, datap, len); + break; +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + return status; +} + +/* + * Control Path + */ +A_UINT32 cmdRecvNum; + +A_STATUS +wmi_control_rx(struct wmi_t *wmip, void *osbuf) +{ + WMI_CMD_HDR *cmd; + A_UINT16 id; + A_UINT8 *datap; + A_UINT32 len, i, loggingReq; + A_STATUS status = A_OK; + + A_ASSERT(osbuf != NULL); + if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) { + A_NETBUF_FREE(osbuf); + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + return A_ERROR; + } + + cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + id = cmd->commandId; + + if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + A_NETBUF_FREE(osbuf); + A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG)); + wmip->wmi_stats.cmd_len_err++; + return A_ERROR; + } + + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + + loggingReq = 0; + + ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS, + &loggingReq); + + if(loggingReq) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id)); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum)); + for(i = 0; i < len; i++) + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i])); + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n")); + } + + LOCK_WMI(wmip); + cmdRecvNum++; + UNLOCK_WMI(wmip); + + switch (id) { + case (WMI_GET_BITRATE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG)); + status = wmi_bitrate_reply_rx(wmip, datap, len); + break; + case (WMI_GET_CHANNEL_LIST_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG)); + status = wmi_channelList_reply_rx(wmip, datap, len); + break; + case (WMI_GET_TX_PWR_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG)); + status = wmi_txPwr_reply_rx(wmip, datap, len); + break; + case (WMI_READY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG)); + status = wmi_ready_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt); + break; + case (WMI_CONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG)); + status = wmi_connect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_DISCONNECT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG)); + status = wmi_disconnect_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_PEER_NODE_EVENTID): + A_DPRINTF (DBG_WMI, (DBGFMT "WMI_PEER_NODE_EVENTID\n", DBGARG)); + status = wmi_peer_node_event_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_TKIP_MICERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG)); + status = wmi_tkip_micerr_event_rx(wmip, datap, len); + break; + case (WMI_BSSINFO_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG)); + { + /* + * convert WMI_BSS_INFO_HDR2 to WMI_BSS_INFO_HDR + * Take a local copy of the WMI_BSS_INFO_HDR2 from the wmi buffer + * and reconstruct the WMI_BSS_INFO_HDR in its place + */ + WMI_BSS_INFO_HDR2 bih2; + WMI_BSS_INFO_HDR *bih; + A_MEMCPY(&bih2, datap, sizeof(WMI_BSS_INFO_HDR2)); + + A_NETBUF_PUSH(osbuf, 4); + datap = A_NETBUF_DATA(osbuf); + len = A_NETBUF_LEN(osbuf); + bih = (WMI_BSS_INFO_HDR *)datap; + + bih->channel = bih2.channel; + bih->frameType = bih2.frameType; + bih->snr = bih2.snr; + bih->rssi = bih2.snr - 95; + bih->ieMask = bih2.ieMask; + A_MEMCPY(bih->bssid, bih2.bssid, ATH_MAC_LEN); + + status = wmi_bssInfo_event_rx(wmip, datap, len); + A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + } + break; + case (WMI_REGDOMAIN_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG)); + status = wmi_regDomain_event_rx(wmip, datap, len); + break; + case (WMI_PSTREAM_TIMEOUT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG)); + status = wmi_pstream_timeout_event_rx(wmip, datap, len); + /* pstreams are fatpipe abstractions that get implicitly created. + * User apps only deal with thinstreams. creation of a thinstream + * by the user or data traffic flow in an AC triggers implicit + * pstream creation. Do we need to send this event to App..? + * no harm in sending it. + */ + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_NEIGHBOR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG)); + status = wmi_neighborReport_event_rx(wmip, datap, len); + break; + case (WMI_SCAN_COMPLETE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG)); + status = wmi_scanComplete_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_CMDERROR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG)); + status = wmi_errorEvent_rx(wmip, datap, len); + break; + case (WMI_REPORT_STATISTICS_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG)); + status = wmi_statsEvent_rx(wmip, datap, len); + break; + case (WMI_RSSI_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_rssiThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_ERROR_REPORT_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG)); + status = wmi_reportErrorEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_OPT_RX_FRAME_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG)); + status = wmi_opt_frame_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_TBL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG)); + status = wmi_roam_tbl_event_rx(wmip, datap, len); + break; + case (WMI_EXTENSION_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG)); + status = wmi_control_rx_xtnd(wmip, osbuf); + break; + case (WMI_CAC_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG)); + status = wmi_cac_event_rx(wmip, datap, len); + break; + case (WMI_CHANNEL_CHANGE_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CHANNEL_CHANGE_EVENTID\n", DBGARG)); + status = wmi_channel_change_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_ROAM_DATA_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG)); + status = wmi_roam_data_event_rx(wmip, datap, len); + break; +#ifdef CONFIG_HOST_TCMD_SUPPORT + case (WMI_TEST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG)); + status = wmi_tcmd_test_report_rx(wmip, datap, len); + break; +#endif + case (WMI_GET_FIXRATES_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG)); + status = wmi_ratemask_reply_rx(wmip, datap, len); + break; + case (WMI_TX_RETRY_ERR_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG)); + status = wmi_txRetryErrEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_SNR_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_snrThresholdEvent_rx(wmip, datap, len); + break; + case (WMI_LQ_THRESHOLD_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG)); + status = wmi_lqThresholdEvent_rx(wmip, datap, len); + A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len); + break; + case (WMI_APLIST_EVENTID): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n")); + status = wmi_aplistEvent_rx(wmip, datap, len); + break; + case (WMI_GET_KEEPALIVE_CMDID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG)); + status = wmi_keepalive_reply_rx(wmip, datap, len); + break; + case (WMI_GET_WOW_LIST_EVENTID): + status = wmi_get_wow_list_event_rx(wmip, datap, len); + break; + case (WMI_GET_PMKID_LIST_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG)); + status = wmi_get_pmkid_list_event_rx(wmip, datap, len); + break; + case (WMI_PSPOLL_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSPOLL_EVENT\n", DBGARG)); + status = wmi_pspoll_event_rx(wmip, datap, len); + break; + case (WMI_DTIMEXPIRY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DTIMEXPIRY_EVENT\n", DBGARG)); + status = wmi_dtimexpiry_event_rx(wmip, datap, len); + break; + case (WMI_SET_PARAMS_REPLY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG)); + status = wmi_set_params_event_rx(wmip, datap, len); + break; +#ifdef ATH_AR6K_11N_SUPPORT + case (WMI_ADDBA_REQ_EVENTID): + status = wmi_addba_req_event_rx(wmip, datap, len); + break; + case (WMI_ADDBA_RESP_EVENTID): + status = wmi_addba_resp_event_rx(wmip, datap, len); + break; + case (WMI_DELBA_REQ_EVENTID): + status = wmi_delba_req_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_BTCOEX_CONFIG_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_CONFIG_EVENTID", DBGARG)); + status = wmi_btcoex_config_event_rx(wmip, datap, len); + break; + case (WMI_REPORT_BTCOEX_STATS_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_STATS_EVENTID", DBGARG)); + status = wmi_btcoex_stats_event_rx(wmip, datap, len); + break; +#endif + case (WMI_TX_COMPLETE_EVENTID): + { + int index; + TX_COMPLETE_MSG_V1 *pV1; + WMI_TX_COMPLETE_EVENT *pEv = (WMI_TX_COMPLETE_EVENT *)datap; + A_PRINTF("comp: %d %d %d\n", pEv->numMessages, pEv->msgLen, pEv->msgType); + + for(index = 0 ; index < pEv->numMessages ; index++) { + pV1 = (TX_COMPLETE_MSG_V1 *)(datap + sizeof(WMI_TX_COMPLETE_EVENT) + index*sizeof(TX_COMPLETE_MSG_V1)); + A_PRINTF("msg: %d %d %d %d\n", pV1->status, pV1->pktID, pV1->rateIdx, pV1->ackFailures); + } + } + break; + case (WMI_HCI_EVENT_EVENTID): + status = wmi_hci_event_rx(wmip, datap, len); + break; +#ifdef WAPI_ENABLE + case (WMI_WAPI_REKEY_EVENTID): + A_DPRINTF(DBG_WMI, (DBGFMT "WMI_WAPI_REKEY_EVENTID", DBGARG)); + status = wmi_wapi_rekey_event_rx(wmip, datap, len); + break; +#endif + default: + A_DPRINTF(DBG_WMI|DBG_ERROR, + (DBGFMT "Unknown id 0x%x\n", DBGARG, id)); + wmip->wmi_stats.cmd_id_err++; + status = A_ERROR; + break; + } + + A_NETBUF_FREE(osbuf); + + return status; +} + +/* Send a "simple" wmi command -- one with no arguments */ +static A_STATUS +wmi_simple_cmd(struct wmi_t *wmip, WMI_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} + +/* Send a "simple" extended wmi command -- one with no arguments. + Enabling this command only if GPIO or profiling support is enabled. + This is to suppress warnings on some platforms */ +#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT) +static A_STATUS +wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(0); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, cmdid, NO_SYNC_WMIFLAG)); +} +#endif + +static A_STATUS +wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap; + + if (len < sizeof(WMI_READY_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + wmip->wmi_ready = TRUE; + A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability, + ev->version); + + return A_OK; +} + +#define LE_READ_4(p) \ + ((A_UINT32) \ + ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + +static int __inline +iswmmoui(const A_UINT8 *frm) +{ + return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI); +} + +static int __inline +iswmmparam(const A_UINT8 *frm) +{ + return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE; +} + + +static A_STATUS +wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CONNECT_EVENT *ev; + A_UINT8 *pie,*peie; + + if (len < sizeof(WMI_CONNECT_EVENT)) + { + return A_EINVAL; + } + ev = (WMI_CONNECT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + DBGARG, ev->channel, + ev->bssid[0], ev->bssid[1], ev->bssid[2], + ev->bssid[3], ev->bssid[4], ev->bssid[5])); + + A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN); + + /* initialize pointer to start of assoc rsp IEs */ + pie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + + sizeof(A_UINT16) + /* capinfo*/ + sizeof(A_UINT16) + /* status Code */ + sizeof(A_UINT16) ; /* associd */ + + /* initialize pointer to end of assoc rsp IEs */ + peie = ev->assocInfo + ev->beaconIeLen + ev->assocReqLen + ev->assocRespLen; + + while (pie < peie) + { + switch (*pie) + { + case IEEE80211_ELEMID_VENDOR: + if (iswmmoui(pie)) + { + if(iswmmparam (pie)) + { + wmip->wmi_is_wmm_enabled = TRUE; + } + } + break; + } + + if (wmip->wmi_is_wmm_enabled) + { + break; + } + pie += pie[1] + 2; + } + + A_WMI_CONNECT_EVENT(wmip->wmi_devt, ev->channel, ev->bssid, + ev->listenInterval, ev->beaconInterval, + (NETWORK_TYPE) ev->networkType, ev->beaconIeLen, + ev->assocReqLen, ev->assocRespLen, + ev->assocInfo); + + return A_OK; +} + +static A_STATUS +wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_REG_DOMAIN_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_REG_DOMAIN_EVENT *)datap; + + A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain); + + return A_OK; +} + +static A_STATUS +wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_NEIGHBOR_REPORT_EVENT *ev; + int numAps; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap; + numAps = ev->numberOfAps; + + if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) { + return A_EINVAL; + } + + A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor); + + return A_OK; +} + +static A_STATUS +wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_DISCONNECT_EVENT *ev; + + if (len < sizeof(WMI_DISCONNECT_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_DISCONNECT_EVENT *)datap; + + A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid)); + + wmip->wmi_is_wmm_enabled = FALSE; + wmip->wmi_pair_crypto_type = NONE_CRYPT; + wmip->wmi_grp_crypto_type = NONE_CRYPT; + + A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid, + ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus); + + return A_OK; +} + +static A_STATUS +wmi_peer_node_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PEER_NODE_EVENT *ev; + + if (len < sizeof(WMI_PEER_NODE_EVENT)) { + return A_EINVAL; + } + ev = (WMI_PEER_NODE_EVENT *)datap; + if (ev->eventCode == PEER_NODE_JOIN_EVENT) { + A_DPRINTF (DBG_WMI, (DBGFMT "Joined node with Macaddr: ", DBGARG)); + } else if(ev->eventCode == PEER_NODE_LEAVE_EVENT) { + A_DPRINTF (DBG_WMI, (DBGFMT "left node with Macaddr: ", DBGARG)); + } + + A_WMI_PEER_EVENT (wmip->wmi_devt, ev->eventCode, ev->peerMacAddr); + + return A_OK; +} + +static A_STATUS +wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TKIP_MICERR_EVENT *ev; + + if (len < sizeof(*ev)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + ev = (WMI_TKIP_MICERR_EVENT *)datap; + A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast); + + return A_OK; +} + +static A_STATUS +wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss = NULL; + WMI_BSS_INFO_HDR *bih; + A_UINT8 *buf; + A_UINT32 nodeCachingAllowed = 1; + A_UCHAR cached_ssid_len = 0; + A_UCHAR cached_ssid_buf[IEEE80211_NWID_LEN] = {0}; + A_UINT8 beacon_ssid_len = 0; + + if (len <= sizeof(WMI_BSS_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_BSS_INFO_HDR *)datap; + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + + if (bih->rssi > 0) { + if (NULL == bss) + return A_OK; //no node found in the table, just drop the node with incorrect RSSI + else + bih->rssi = bss->ni_rssi; //Adjust RSSI in datap in case it is used in A_WMI_BSSINFO_EVENT_RX + } + + A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len); + /* What is driver config for wlan node caching? */ + if(ar6000_get_driver_cfg(wmip->wmi_devt, + AR6000_DRIVER_CFG_GET_WLANNODECACHING, + &nodeCachingAllowed) != A_OK) { + return A_EINVAL; + } + + if(!nodeCachingAllowed) { + return A_OK; + } + + buf = datap + sizeof(WMI_BSS_INFO_HDR); + len -= sizeof(WMI_BSS_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, " + "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG, + bih->channel, (unsigned char) bih->rssi, bih->bssid[0], + bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4], + bih->bssid[5])); + + if(wps_enable && (bih->frameType == PROBERESP_FTYPE) ) + return A_OK; + + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + + /* In case of hidden AP, beacon will not have ssid, + * but a directed probe response will have it, + * so cache the probe-resp-ssid if already present. */ + if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType)) + { + A_UCHAR *ie_ssid; + + ie_ssid = bss->ni_cie.ie_ssid; + if(ie_ssid && (ie_ssid[1] <= IEEE80211_NWID_LEN) && (ie_ssid[2] != 0)) + { + cached_ssid_len = ie_ssid[1]; + memcpy(cached_ssid_buf, ie_ssid + 2, cached_ssid_len); + } + } + + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + /* beacon/probe response frame format + * [8] time stamp + * [2] beacon interval + * [2] capability information + * [tlv] ssid */ + beacon_ssid_len = buf[SSID_IE_LEN_INDEX]; + + /* If ssid is cached for this hidden AP, then change buffer len accordingly. */ + if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType) && + (0 != cached_ssid_len) && + (0 == beacon_ssid_len || (cached_ssid_len > beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1]))) + { + len += (cached_ssid_len - beacon_ssid_len); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_rssi = bih->rssi; + A_ASSERT(bss->ni_buf != NULL); + + /* In case of hidden AP, beacon will not have ssid, + * but a directed probe response will have it, + * so place the cached-ssid(probe-resp) in the bssinfo. */ + if ((TRUE == is_probe_ssid) && (BEACON_FTYPE == bih->frameType) && + (0 != cached_ssid_len) && + (0 == beacon_ssid_len || (beacon_ssid_len && 0 == buf[SSID_IE_LEN_INDEX + 1]))) + { + A_UINT8 *ni_buf = bss->ni_buf; + int buf_len = len; + + /* copy the first 14 bytes such as + * time-stamp(8), beacon-interval(2), cap-info(2), ssid-id(1), ssid-len(1). */ + A_MEMCPY(ni_buf, buf, SSID_IE_LEN_INDEX + 1); + + ni_buf[SSID_IE_LEN_INDEX] = cached_ssid_len; + ni_buf += (SSID_IE_LEN_INDEX + 1); + + buf += (SSID_IE_LEN_INDEX + 1); + buf_len -= (SSID_IE_LEN_INDEX + 1); + + /* copy the cached ssid */ + A_MEMCPY(ni_buf, cached_ssid_buf, cached_ssid_len); + ni_buf += cached_ssid_len; + + buf += beacon_ssid_len; + buf_len -= beacon_ssid_len; + + if (cached_ssid_len > beacon_ssid_len) + buf_len -= (cached_ssid_len - beacon_ssid_len); + + /* now copy the rest of bytes */ + A_MEMCPY(ni_buf, buf, buf_len); + } + else + A_MEMCPY(bss->ni_buf, buf, len); + + bss->ni_framelen = len; + if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) { + wlan_node_free(bss); + return A_EINVAL; + } + + /* + * Update the frequency in ie_chan, overwriting of channel number + * which is done in wlan_parse_beacon + */ + bss->ni_cie.ie_chan = bih->channel; + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + +static A_STATUS +wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + bss_t *bss; + WMI_OPT_RX_INFO_HDR *bih; + A_UINT8 *buf; + + if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) { + return A_EINVAL; + } + + bih = (WMI_OPT_RX_INFO_HDR *)datap; + buf = datap + sizeof(WMI_OPT_RX_INFO_HDR); + len -= sizeof(WMI_OPT_RX_INFO_HDR); + + A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG, + bih->bssid[4], bih->bssid[5])); + + bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid); + if (bss != NULL) { + /* + * Free up the node. Not the most efficient process given + * we are about to allocate a new node but it is simple and should be + * adequate. + */ + wlan_node_reclaim(&wmip->wmi_scan_table, bss); + } + + bss = wlan_node_alloc(&wmip->wmi_scan_table, len); + if (bss == NULL) { + return A_NO_MEMORY; + } + + bss->ni_snr = bih->snr; + bss->ni_cie.ie_chan = bih->channel; + A_ASSERT(bss->ni_buf != NULL); + A_MEMCPY(bss->ni_buf, buf, len); + wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid); + + return A_OK; +} + + /* This event indicates inactivity timeout of a fatpipe(pstream) + * at the target + */ +static A_STATUS +wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSTREAM_TIMEOUT_EVENT *ev; + + if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) { + return A_EINVAL; + } + + A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG)); + + ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap; + + /* When the pstream (fat pipe == AC) timesout, it means there were no + * thinStreams within this pstream & it got implicitly created due to + * data flow on this AC. We start the inactivity timer only for + * implicitly created pstream. Just reset the host state. + */ + /* Set the activeTsids for this AC to 0 */ + LOCK_WMI(wmip); + wmip->wmi_streamExistsForAC[ev->trafficClass]=0; + wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass); + UNLOCK_WMI(wmip); + + /*Indicate inactivity to driver layer for this fatpipe (pstream)*/ + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass); + + return A_OK; +} + +static A_STATUS +wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_BIT_RATE_REPLY *reply; + A_INT32 rate; + A_UINT32 sgi,index; + /* 54149: + * WMI_BIT_RATE_CMD structure is changed to WMI_BIT_RATE_REPLY. + * since there is difference in the length and to avoid returning + * error value. + */ + if (len < sizeof(WMI_BIT_RATE_REPLY)) { + return A_EINVAL; + } + reply = (WMI_BIT_RATE_REPLY *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex)); + + if (reply->rateIndex == (A_INT8) RATE_AUTO) { + rate = RATE_AUTO; + } else { + // the SGI state is stored as the MSb of the rateIndex + index = reply->rateIndex & 0x7f; + sgi = (reply->rateIndex & 0x80)? 1:0; + rate = wmi_rateTable[index][sgi]; + } + + A_WMI_BITRATE_RX(wmip->wmi_devt, rate); + return A_OK; +} + +static A_STATUS +wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_FIX_RATES_REPLY *reply; + + if (len < sizeof(WMI_FIX_RATES_REPLY)) { + return A_EINVAL; + } + reply = (WMI_FIX_RATES_REPLY *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask)); + + A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask); + + return A_OK; +} + +static A_STATUS +wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_LIST_REPLY *reply; + + if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_LIST_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels, + reply->channelList); + + return A_OK; +} + +static A_STATUS +wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TX_PWR_REPLY *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TX_PWR_REPLY *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM); + + return A_OK; +} +static A_STATUS +wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_KEEPALIVE_CMD *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_GET_KEEPALIVE_CMD *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured); + + return A_OK; +} + + +static A_STATUS +wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETOPENREQ_EVENT *dsetopenreq; + + if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) { + return A_EINVAL; + } + dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap; + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id)); + A_WMI_DSET_OPEN_REQ(wmip->wmi_devt, + dsetopenreq->dset_id, + dsetopenreq->targ_dset_handle, + dsetopenreq->targ_reply_fn, + dsetopenreq->targ_reply_arg); + + return A_OK; +} + +#ifdef CONFIG_HOST_DSET_SUPPORT +static A_STATUS +wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETCLOSE_EVENT *dsetclose; + + if (len < sizeof(WMIX_DSETCLOSE_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetclose = (WMIX_DSETCLOSE_EVENT *)datap; + A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie); + + return A_OK; +} + +static A_STATUS +wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_DSETDATAREQ_EVENT *dsetdatareq; + + if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap; + A_WMI_DSET_DATA_REQ(wmip->wmi_devt, + dsetdatareq->access_cookie, + dsetdatareq->offset, + dsetdatareq->length, + dsetdatareq->targ_buf, + dsetdatareq->targ_reply_fn, + dsetdatareq->targ_reply_arg); + + return A_OK; +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +static A_STATUS +wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SCAN_COMPLETE_EVENT *ev; + + ev = (WMI_SCAN_COMPLETE_EVENT *)datap; + A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, (A_STATUS) ev->status); + is_probe_ssid = FALSE; + + return A_OK; +} + +/* + * Target is reporting a programming error. This is for + * developer aid only. Target only checks a few common violations + * and it is responsibility of host to do all error checking. + * Behavior of target after wmi error event is undefined. + * A reset is recommended. + */ +static A_STATUS +wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CMD_ERROR_EVENT *ev; + + ev = (WMI_CMD_ERROR_EVENT *)datap; + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId)); + switch (ev->errorCode) { + case (INVALID_PARAM): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n")); + break; + case (ILLEGAL_STATE): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n")); + break; + case (INTERNAL_ERROR): + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n")); + break; + } + + return A_OK; +} + + +static A_STATUS +wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, datap, len); + + return A_OK; +} + +static A_STATUS +wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_RSSI_THRESHOLD_EVENT *reply; + WMI_RSSI_THRESHOLD_VAL newThreshold; + WMI_RSSI_THRESHOLD_PARAMS_CMD cmd; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + A_UINT8 upper_rssi_threshold, lower_rssi_threshold; + A_INT16 rssi; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_RSSI_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + newThreshold = (WMI_RSSI_THRESHOLD_VAL) reply->range; + rssi = reply->rssi; + + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (rssi < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper RSSI threshold event: " + " %d\n", DBGARG, rssi)); + } else if ((rssi < sq_thresh->upper_threshold[1]) && + (rssi >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD1_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[2]) && + (rssi >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD2_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[3]) && + (rssi >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD3_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[4]) && + (rssi >= sq_thresh->upper_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD4_ABOVE; + } else if ((rssi < sq_thresh->upper_threshold[5]) && + (rssi >= sq_thresh->upper_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD5_ABOVE; + } else if (rssi >= sq_thresh->upper_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD6_ABOVE; + } + } else { + /* Lower threshold breached */ + if (rssi > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower RSSI threshold event: " + "%d %d\n", DBGARG, rssi, sq_thresh->lower_threshold[0])); + } else if ((rssi > sq_thresh->lower_threshold[1]) && + (rssi <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_RSSI_THRESHOLD6_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[2]) && + (rssi <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_RSSI_THRESHOLD5_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[3]) && + (rssi <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_RSSI_THRESHOLD4_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[4]) && + (rssi <= sq_thresh->lower_threshold[3])) + { + newThreshold = WMI_RSSI_THRESHOLD3_BELOW; + } else if ((rssi > sq_thresh->lower_threshold[5]) && + (rssi <= sq_thresh->lower_threshold[4])) + { + newThreshold = WMI_RSSI_THRESHOLD2_BELOW; + } else if (rssi <= sq_thresh->lower_threshold[5]) { + newThreshold = WMI_RSSI_THRESHOLD1_BELOW; + } + } + /* Calculate and install the next set of thresholds */ + lower_rssi_threshold = ar6000_get_lower_threshold(rssi, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_rssi_threshold = ar6000_get_upper_threshold(rssi, sq_thresh, + sq_thresh->upper_threshold_valid_count); + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_rssi_threshold; + cmd.thresholdBelow1_Val = lower_rssi_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + rssi_event_value = rssi; + + if (wmi_send_rssi_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the RSSI thresholds\n", + DBGARG)); + } + + A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, newThreshold, reply->rssi); + + return A_OK; +} + + +static A_STATUS +wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ERROR_REPORT_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, (WMI_TARGET_ERROR_VAL) reply->errorVal); + + return A_OK; +} + +static A_STATUS +wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CAC_EVENT *reply; + WMM_TSPEC_IE *tspec_ie; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CAC_EVENT *)datap; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + if ((reply->cac_indication == CAC_INDICATION_ADMISSION_RESP) && + (reply->statusCode != TSPEC_STATUS_CODE_ADMISSION_ACCEPTED)) { + tspec_ie = (WMM_TSPEC_IE *) &(reply->tspecSuggestion); + + wmi_delete_pstream_cmd(wmip, reply->ac, + (tspec_ie->tsInfo_info >> TSPEC_TSID_S) & TSPEC_TSID_MASK); + } + else if (reply->cac_indication == CAC_INDICATION_NO_RESP) { + A_UINT16 activeTsids; + A_UINT8 i; + + /* following assumes that there is only one outstanding ADDTS request + when this event is received */ + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[reply->ac]; + UNLOCK_WMI(wmip); + + for (i = 0; i < sizeof(activeTsids) * 8; i++) { + if ((activeTsids >> i) & 1) { + break; + } + } + if (i < (sizeof(activeTsids) * 8)) { + wmi_delete_pstream_cmd(wmip, reply->ac, i); + } + } + + A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac, + reply->cac_indication, reply->statusCode, + reply->tspecSuggestion); + + return A_OK; +} + +static A_STATUS +wmi_channel_change_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_CHANNEL_CHANGE_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_CHANNEL_CHANGE_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_CHANNEL_CHANGE_EVENT(wmip->wmi_devt, reply->oldChannel, + reply->newChannel); + + return A_OK; +} + +static A_STATUS +wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_HB_CHALLENGE_RESP_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG)); + + A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source); + + return A_OK; +} + +static A_STATUS +wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_TBL *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_TBL *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_TARGET_ROAM_DATA *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_TARGET_ROAM_DATA *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply); + + return A_OK; +} + +static A_STATUS +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + if (len < sizeof(WMI_TX_RETRY_ERR_EVENT)) { + return A_EINVAL; + } + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt); + + return A_OK; +} + +static A_STATUS +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_SNR_THRESHOLD_EVENT *reply; + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + WMI_SNR_THRESHOLD_VAL newThreshold; + WMI_SNR_THRESHOLD_PARAMS_CMD cmd; + A_UINT8 upper_snr_threshold, lower_snr_threshold; + A_INT16 snr; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_SNR_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + newThreshold = (WMI_SNR_THRESHOLD_VAL) reply->range; + snr = reply->snr; + /* + * Identify the threshold breached and communicate that to the app. After + * that install a new set of thresholds based on the signal quality + * reported by the target + */ + if (newThreshold) { + /* Upper threshold breached */ + if (snr < sq_thresh->upper_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious upper SNR threshold event: " + "%d\n", DBGARG, snr)); + } else if ((snr < sq_thresh->upper_threshold[1]) && + (snr >= sq_thresh->upper_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD1_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[2]) && + (snr >= sq_thresh->upper_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD2_ABOVE; + } else if ((snr < sq_thresh->upper_threshold[3]) && + (snr >= sq_thresh->upper_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD3_ABOVE; + } else if (snr >= sq_thresh->upper_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD4_ABOVE; + } + } else { + /* Lower threshold breached */ + if (snr > sq_thresh->lower_threshold[0]) { + A_DPRINTF(DBG_WMI, (DBGFMT "Spurious lower SNR threshold event: " + "%d %d\n", DBGARG, snr, sq_thresh->lower_threshold[0])); + } else if ((snr > sq_thresh->lower_threshold[1]) && + (snr <= sq_thresh->lower_threshold[0])) + { + newThreshold = WMI_SNR_THRESHOLD4_BELOW; + } else if ((snr > sq_thresh->lower_threshold[2]) && + (snr <= sq_thresh->lower_threshold[1])) + { + newThreshold = WMI_SNR_THRESHOLD3_BELOW; + } else if ((snr > sq_thresh->lower_threshold[3]) && + (snr <= sq_thresh->lower_threshold[2])) + { + newThreshold = WMI_SNR_THRESHOLD2_BELOW; + } else if (snr <= sq_thresh->lower_threshold[3]) { + newThreshold = WMI_SNR_THRESHOLD1_BELOW; + } + } + + /* Calculate and install the next set of thresholds */ + lower_snr_threshold = ar6000_get_lower_threshold(snr, sq_thresh, + sq_thresh->lower_threshold_valid_count); + upper_snr_threshold = ar6000_get_upper_threshold(snr, sq_thresh, + sq_thresh->upper_threshold_valid_count); + + /* Issue a wmi command to install the thresholds */ + cmd.thresholdAbove1_Val = upper_snr_threshold; + cmd.thresholdBelow1_Val = lower_snr_threshold; + cmd.weight = sq_thresh->weight; + cmd.pollTime = sq_thresh->polling_interval; + + A_DPRINTF(DBG_WMI, (DBGFMT "snr: %d, threshold: %d, lower: %d, upper: %d\n" + ,DBGARG, snr, newThreshold, lower_snr_threshold, + upper_snr_threshold)); + + snr_event_value = snr; + + if (wmi_send_snr_threshold_params(wmip, &cmd) != A_OK) { + A_DPRINTF(DBG_WMI, (DBGFMT "Unable to configure the SNR thresholds\n", + DBGARG)); + } + A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, newThreshold, reply->snr); + + return A_OK; +} + +static A_STATUS +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_LQ_THRESHOLD_EVENT *reply; + + if (len < sizeof(*reply)) { + return A_EINVAL; + } + reply = (WMI_LQ_THRESHOLD_EVENT *)datap; + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt, + (WMI_LQ_THRESHOLD_VAL) reply->range, + reply->lq); + + return A_OK; +} + +static A_STATUS +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT16 ap_info_entry_size; + WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap; + WMI_AP_INFO_V1 *ap_info_v1; + A_UINT8 i; + + if (len < sizeof(WMI_APLIST_EVENT)) { + return A_EINVAL; + } + + if (ev->apListVer == APLIST_VER1) { + ap_info_entry_size = sizeof(WMI_AP_INFO_V1); + ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList; + } else { + return A_EINVAL; + } + + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP)); + if (len < (int)(sizeof(WMI_APLIST_EVENT) + + (ev->numAP - 1) * ap_info_entry_size)) + { + return A_EINVAL; + } + + /* + * AP List Ver1 Contents + */ + for (i = 0; i < ev->numAP; i++) { + AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\ + "Channel %d\n", i, + ap_info_v1->bssid[0], ap_info_v1->bssid[1], + ap_info_v1->bssid[2], ap_info_v1->bssid[3], + ap_info_v1->bssid[4], ap_info_v1->bssid[5], + ap_info_v1->channel)); + ap_info_v1++; + } + return A_OK; +} + +static A_STATUS +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_UINT32 dropped; + + dropped = *((A_UINT32 *)datap); + datap += sizeof(dropped); + len -= sizeof(dropped); + A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, (A_INT8*)datap, len); + return A_OK; +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +static A_STATUS +wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG, + gpio_intr->intr_mask, gpio_intr->input_values)); + + A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values); + + return A_OK; +} + +static A_STATUS +wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, + gpio_data->reg_id, gpio_data->value)); + + A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value); + + return A_OK; +} + +static A_STATUS +wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_GPIO_ACK_RX(); + + return A_OK; +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +/* + * Called to send a wmi command. Command specific data is already built + * on osbuf and current osbuf->data points to it. + */ +A_STATUS +wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ + A_STATUS status; +#define IS_OPT_TX_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID)) + WMI_CMD_HDR *cHdr; + HTC_ENDPOINT_ID eid = wmip->wmi_endpoint_id; + + A_ASSERT(osbuf != NULL); + + if (syncflag >= END_WMIFLAG) { + A_NETBUF_FREE(osbuf); + return A_EINVAL; + } + + if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all data currently queued is transmitted before + * the cmd execution. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) { + A_NETBUF_FREE(osbuf); + return A_NO_MEMORY; + } + + cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT16) cmdId; + cHdr->info1 = 0; // added for virtual interface + + /* + * Only for OPT_TX_CMD, use BE endpoint. + */ + if (IS_OPT_TX_CMD(cmdId)) { + if ((status=wmi_data_hdr_add(wmip, osbuf, OPT_MSGTYPE, FALSE, FALSE,0,NULL)) != A_OK) { + A_NETBUF_FREE(osbuf); + return status; + } + eid = A_WMI_Ac2EndpointID(wmip->wmi_devt, WMM_AC_BE); + } + A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid); + + if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) { + /* + * We want to make sure all new data queued waits for the command to + * execute. Establish a new sync point. + */ + wmi_sync_point(wmip); + } + return (A_OK); +#undef IS_OPT_TX_CMD +} + +A_STATUS +wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMIX_COMMAND_ID cmdId, + WMI_SYNC_FLAG syncflag) +{ + WMIX_CMD_HDR *cHdr; + + if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) { + A_NETBUF_FREE(osbuf); + return A_NO_MEMORY; + } + + cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf); + cHdr->commandId = (A_UINT32) cmdId; + + return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag); +} + +A_STATUS +wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType, + DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode, + CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen, + CRYPTO_TYPE groupCrypto, A_UINT8 groupCryptoLen, + int ssidLength, A_UCHAR *ssid, + A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags) +{ + void *osbuf; + WMI_CONNECT_CMD *cc; + + if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) { + return A_EINVAL; + } + if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD)); + + cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + if (ssidLength) + { + A_MEMCPY(cc->ssid, ssid, ssidLength); + } + + cc->ssidLength = ssidLength; + cc->networkType = netType; + cc->dot11AuthMode = dot11AuthMode; + cc->authMode = authMode; + cc->pairwiseCryptoType = pairwiseCrypto; + cc->pairwiseCryptoLen = pairwiseCryptoLen; + cc->groupCryptoType = groupCrypto; + cc->groupCryptoLen = groupCryptoLen; + cc->channel = channel; + cc->ctrl_flags = ctrl_flags; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + + wmip->wmi_pair_crypto_type = pairwiseCrypto; + wmip->wmi_grp_crypto_type = groupCrypto; + + return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel) +{ + void *osbuf; + WMI_RECONNECT_CMD *cc; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD)); + + cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cc, sizeof(*cc)); + + cc->channel = channel; + + if (bssid != NULL) { + A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disconnect_cmd(struct wmi_t *wmip) +{ + A_STATUS status; + + /* Bug fix for 24817(elevator bug) - the disconnect command does not + need to do a SYNC before.*/ + status = wmi_simple_cmd(wmip, WMI_DISCONNECT_CMDID); + + return status; +} + +A_STATUS +wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType, + A_BOOL forceFgScan, A_BOOL isLegacy, + A_UINT32 homeDwellTime, A_UINT32 forceScanInterval, + A_INT8 numChan, A_UINT16 *channelList) +{ + void *osbuf; + WMI_START_SCAN_CMD *sc; + A_INT8 size; + + size = sizeof (*sc); + + if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) { + return A_EINVAL; + } + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf)); + sc->scanType = scanType; + sc->forceFgScan = forceFgScan; + sc->isLegacy = isLegacy; + sc->homeDwellTime = homeDwellTime; + sc->forceScanInterval = forceScanInterval; + sc->numChannels = numChan; + if (numChan) { + A_MEMCPY(sc->channelList, channelList, numChan * sizeof(A_UINT16)); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec, + A_UINT16 fg_end_sec, A_UINT16 bg_sec, + A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec, + A_UINT16 pas_chdw_msec, + A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags, + A_UINT32 max_dfsch_act_time, A_UINT16 maxact_scan_per_ssid) +{ + void *osbuf; + WMI_SCAN_PARAMS_CMD *sc; + + osbuf = A_NETBUF_ALLOC(sizeof(*sc)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*sc)); + + sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(sc, sizeof(*sc)); + sc->fg_start_period = fg_start_sec; + sc->fg_end_period = fg_end_sec; + sc->bg_period = bg_sec; + sc->minact_chdwell_time = minact_chdw_msec; + sc->maxact_chdwell_time = maxact_chdw_msec; + sc->pas_chdwell_time = pas_chdw_msec; + sc->shortScanRatio = shScanRatio; + sc->scanCtrlFlags = scanCtrlFlags; + sc->max_dfsch_act_time = max_dfsch_act_time; + sc->maxact_scan_per_ssid = maxact_scan_per_ssid; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask) +{ + void *osbuf; + WMI_BSS_FILTER_CMD *cmd; + + if (filter >= LAST_BSS_FILTER) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bssFilter = filter; + cmd->ieMask = ieMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag, + A_UINT8 ssidLength, A_UCHAR *ssid) +{ + void *osbuf; + WMI_PROBED_SSID_CMD *cmd; + + if (index > MAX_PROBED_SSID_INDEX) { + return A_EINVAL; + } + if (ssidLength > sizeof(cmd->ssid)) { + return A_EINVAL; + } + if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) { + return A_EINVAL; + } + if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) { + return A_EINVAL; + } + + if (flag & SPECIFIC_SSID_FLAG) { + is_probe_ssid = TRUE; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->entryIndex = index; + cmd->flag = flag; + cmd->ssidLength = ssidLength; + A_MEMCPY(cmd->ssid, ssid, ssidLength); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons) +{ + void *osbuf; + WMI_LISTEN_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->listenInterval = listenInterval; + cmd->numBeacons = listenBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons) +{ + void *osbuf; + WMI_BMISS_TIME_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->bmissTime = bmissTime; + cmd->numBeacons = bmissBeacons; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType, + A_UINT8 ieLen, A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_ASSOC_INFO_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + cmd->ieType = ieType; + cmd->bufferSize = ieLen; + A_MEMCPY(cmd->assocInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode) +{ + void *osbuf; + WMI_POWER_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->powerMode = powerMode; + wmip->wmi_powerMode = powerMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl, + A_UINT16 atim_windows, A_UINT16 timeout_value) +{ + void *osbuf; + WMI_IBSS_PM_CAPS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->power_saving = pmEnable; + cmd->ttl = ttl; + cmd->atim_windows = atim_windows; + cmd->timeout_value = timeout_value; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_apps_cmd(struct wmi_t *wmip, A_UINT8 psType, A_UINT32 idle_time, + A_UINT32 ps_period, A_UINT8 sleep_period) +{ + void *osbuf; + WMI_AP_PS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_AP_PS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->psType = psType; + cmd->idle_time = idle_time; + cmd->ps_period = ps_period; + cmd->sleep_period = sleep_period; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AP_PS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod, + A_UINT16 psPollNum, A_UINT16 dtimPolicy, + A_UINT16 tx_wakeup_policy, A_UINT16 num_tx_to_wakeup, + A_UINT16 ps_fail_event_policy) +{ + void *osbuf; + WMI_POWER_PARAMS_CMD *pm; + + osbuf = A_NETBUF_ALLOC(sizeof(*pm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*pm)); + + pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(pm, sizeof(*pm)); + pm->idle_period = idlePeriod; + pm->pspoll_number = psPollNum; + pm->dtim_policy = dtimPolicy; + pm->tx_wakeup_policy = tx_wakeup_policy; + pm->num_tx_to_wakeup = num_tx_to_wakeup; + pm->ps_fail_event_policy = ps_fail_event_policy; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout) +{ + void *osbuf; + WMI_DISC_TIMEOUT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->disconnectTimeout = timeout; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType, + A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC, + A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl, A_UINT8 *macAddr, + WMI_SYNC_FLAG sync_flag) +{ + void *osbuf; + WMI_ADD_CIPHER_KEY_CMD *cmd; + + if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) || + (keyMaterial == NULL)) + { + return A_EINVAL; + } + + if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + cmd->keyType = keyType; + cmd->keyUsage = keyUsage; + cmd->keyLength = keyLength; + A_MEMCPY(cmd->key, keyMaterial, keyLength); +#ifdef WAPI_ENABLE + if (NULL != keyRSC && key_op_ctrl != KEY_OP_INIT_WAPIPN) { +#else + if (NULL != keyRSC) { +#endif // WAPI_ENABLE + A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC)); + } + cmd->key_op_ctrl = key_op_ctrl; + + if(macAddr) { + A_MEMCPY(cmd->key_macaddr,macAddr,IEEE80211_ADDR_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag)); +} + +A_STATUS +wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk) +{ + void *osbuf; + WMI_ADD_KRK_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_krk_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_DELETE_KRK_CMDID); +} + +A_STATUS +wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex) +{ + void *osbuf; + WMI_DELETE_CIPHER_KEY_CMD *cmd; + + if (keyIndex > WMI_MAX_KEY_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keyIndex = keyIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId, + A_BOOL set) +{ + void *osbuf; + WMI_SET_PMKID_CMD *cmd; + + if (bssid == NULL) { + return A_EINVAL; + } + + if ((set == TRUE) && (pmkId == NULL)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + if (set == TRUE) { + A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid)); + cmd->enable = PMKID_ENABLE; + } else { + A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid)); + cmd->enable = PMKID_DISABLE; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en) +{ + void *osbuf; + WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_akmp_params_cmd(struct wmi_t *wmip, + WMI_SET_AKMP_PARAMS_CMD *akmpParams) +{ + void *osbuf; + WMI_SET_AKMP_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->akmpInfo = akmpParams->akmpInfo; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pmkid_list_cmd(struct wmi_t *wmip, + WMI_SET_PMKID_LIST_CMD *pmkInfo) +{ + void *osbuf; + WMI_SET_PMKID_LIST_CMD *cmd; + A_UINT16 cmdLen; + A_UINT8 i; + + cmdLen = sizeof(pmkInfo->numPMKID) + + pmkInfo->numPMKID * sizeof(WMI_PMKID); + + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->numPMKID = pmkInfo->numPMKID; + + for (i = 0; i < cmd->numPMKID; i++) { + A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i], + WMI_PMKID_LEN); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_pmkid_list_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_PMKID_LIST_CMDID); +} + +A_STATUS +wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, HTC_ENDPOINT_ID eid) +{ + WMI_DATA_HDR *dtHdr; + + A_ASSERT( eid != wmip->wmi_endpoint_id); + A_ASSERT(osbuf != NULL); + + if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) { + return A_NO_MEMORY; + } + + dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf); + dtHdr->info = + (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid)); + + return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid)); +} + +typedef struct _WMI_DATA_SYNC_BUFS { + A_UINT8 trafficClass; + void *osbuf; +}WMI_DATA_SYNC_BUFS; + +static A_STATUS +wmi_sync_point(struct wmi_t *wmip) +{ + void *cmd_osbuf; + WMI_SYNC_CMD *cmd; + WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC]; + A_UINT8 i,numPriStreams=0; + A_STATUS status = A_OK; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + memset(dataSyncBufs,0,sizeof(dataSyncBufs)); + + /* lock out while we walk through the priority list and assemble our local array */ + LOCK_WMI(wmip); + + for (i=0; i < WMM_NUM_AC ; i++) { + if (wmip->wmi_fatPipeExists & (1 << i)) { + numPriStreams++; + dataSyncBufs[numPriStreams-1].trafficClass = i; + } + } + + UNLOCK_WMI(wmip); + + /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */ + + do { + /* + * We allocate all network buffers needed so we will be able to + * send all required frames. + */ + cmd_osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (cmd_osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + + A_NETBUF_PUT(cmd_osbuf, sizeof(*cmd)); + + cmd = (WMI_SYNC_CMD *)(A_NETBUF_DATA(cmd_osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + /* In the SYNC cmd sent on the control Ep, send a bitmap of the data + * eps on which the Data Sync will be sent + */ + cmd->dataSyncMap = wmip->wmi_fatPipeExists; + + for (i=0; i < numPriStreams ; i++) { + dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0); + if (dataSyncBufs[i].osbuf == NULL) { + status = A_NO_MEMORY; + break; + } + } //end for + + /* if Buffer allocation for any of the dataSync fails, then do not + * send the Synchronize cmd on the control ep + */ + if (A_FAILED(status)) { + break; + } + + /* + * Send sync cmd followed by sync data messages on all endpoints being + * used + */ + status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID, + NO_SYNC_WMIFLAG); + + if (A_FAILED(status)) { + break; + } + /* cmd buffer sent, we no longer own it */ + cmd_osbuf = NULL; + + for(i=0; i < numPriStreams; i++) { + A_ASSERT(dataSyncBufs[i].osbuf != NULL); + status = wmi_dataSync_send(wmip, + dataSyncBufs[i].osbuf, + A_WMI_Ac2EndpointID(wmip->wmi_devt, + dataSyncBufs[i]. + trafficClass) + ); + + if (A_FAILED(status)) { + break; + } + /* we don't own this buffer anymore, NULL it out of the array so it + * won't get cleaned up */ + dataSyncBufs[i].osbuf = NULL; + } //end for + + } while(FALSE); + + /* free up any resources left over (possibly due to an error) */ + + if (cmd_osbuf != NULL) { + A_NETBUF_FREE(cmd_osbuf); + } + + for (i = 0; i < numPriStreams; i++) { + if (dataSyncBufs[i].osbuf != NULL) { + A_NETBUF_FREE(dataSyncBufs[i].osbuf); + } + } + + return (status); +} + +A_STATUS +wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params) +{ + void *osbuf; + WMI_CREATE_PSTREAM_CMD *cmd; + A_UINT8 fatPipeExistsForAC=0; + A_INT32 minimalPHY = 0; + A_INT32 nominalPHY = 0; + + /* Validate all the parameters. */ + if( !((params->userPriority < 8) && + (params->userPriority <= 0x7) && + (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass) && + (params->trafficDirection == UPLINK_TRAFFIC || + params->trafficDirection == DNLINK_TRAFFIC || + params->trafficDirection == BIDIR_TRAFFIC) && + (params->trafficType == TRAFFIC_TYPE_APERIODIC || + params->trafficType == TRAFFIC_TYPE_PERIODIC ) && + (params->voicePSCapability == DISABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_THIS_AC || + params->voicePSCapability == ENABLE_FOR_ALL_AC) && + (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) ) + { + return A_EINVAL; + } + + // + // check nominal PHY rate is >= minimalPHY, so that DUT + // can allow TSRS IE + // + + // get the physical rate + minimalPHY = ((params->minPhyRate / 1000)/1000); // unit of bps + + // check minimal phy < nominal phy rate + // + if (params->nominalPHY >= minimalPHY) + { + nominalPHY = (params->nominalPHY * 1000)/500; // unit of 500 kbps + A_DPRINTF(DBG_WMI, + (DBGFMT "TSRS IE Enabled::MinPhy %x->NominalPhy ===> %x\n", DBGARG, + minimalPHY, nominalPHY)); + + params->nominalPHY = nominalPHY; + } + else + { + params->nominalPHY = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Sending create_pstream_cmd: ac=%d tsid:%d\n", DBGARG, + params->trafficClass, params->tsid)); + + cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd, params, sizeof(*cmd)); + + /* this is an implicitly created Fat pipe */ + if ((A_UINT32)params->tsid == (A_UINT32)WMI_IMPLICIT_PSTREAM) { + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } else { + /* this is an explicitly created thin stream within a fat pipe */ + LOCK_WMI(wmip); + fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass)); + wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<tsid); + /* if a thinstream becomes active, the fat pipe automatically + * becomes active + */ + wmip->wmi_fatPipeExists |= (1<trafficClass); + UNLOCK_WMI(wmip); + } + + /* Indicate activty change to driver layer only if this is the + * first TSID to get created in this AC explicitly or an implicit + * fat pipe is getting created. + */ + if (!fatPipeExistsForAC) { + A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass); + } + + /* mike: should be SYNC_BEFORE_WMIFLAG */ + return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid) +{ + void *osbuf; + WMI_DELETE_PSTREAM_CMD *cmd; + A_STATUS status; + A_UINT16 activeTsids=0; + + /* validate the parameters */ + if (trafficClass > 3) { + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid trafficClass: %d\n", DBGARG, trafficClass)); + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->trafficClass = trafficClass; + cmd->tsid = tsid; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + /* Check if the tsid was created & exists */ + if (!(activeTsids & (1<wmi_streamExistsForAC[trafficClass] &= ~(1<wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + + /* Indicate stream inactivity to driver layer only if all tsids + * within this AC are deleted. + */ + if(!activeTsids) { + A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass); + wmip->wmi_fatPipeExists &= ~(1< 15)){ + + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FRAME_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + frameType = (A_UINT8)((subType << 4) | type); + + cmd->bEnableMask = bEnable; + cmd->frameType = frameType; + cmd->frameRateMask = rateMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FRAMERATES_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * used to set the bit rate. rate is in Kbps. If rate == -1 + * then auto selection is used. + */ +A_STATUS +wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 dataRate, A_INT32 mgmtRate, A_INT32 ctlRate) +{ + void *osbuf; + WMI_BIT_RATE_CMD *cmd; + A_INT8 drix, mrix, crix; + + if (dataRate != -1) { + drix = wmi_validate_bitrate(wmip, dataRate); + if(drix == A_EINVAL){ + return A_EINVAL; + } + } else { + drix = -1; + } + + if (mgmtRate != -1) { + mrix = wmi_validate_bitrate(wmip, mgmtRate); + if(mrix == A_EINVAL){ + return A_EINVAL; + } + } else { + mrix = -1; + } + if (ctlRate != -1) { + crix = wmi_validate_bitrate(wmip, ctlRate); + if(crix == A_EINVAL){ + return A_EINVAL; + } + } else { + crix = -1; + } + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->rateIndex = drix; + cmd->mgmtRateIndex = mrix; + cmd->ctlRateIndex = crix; + + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_bitrate_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_BITRATE_CMDID); +} + +/* + * Returns TRUE iff the given rate index is legal in the current PHY mode. + */ +A_BOOL +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_INT32 rateIndex) +{ + WMI_PHY_MODE phyMode = (WMI_PHY_MODE) wmip->wmi_phyMode; + A_BOOL isValid = TRUE; + switch(phyMode) { + case WMI_11A_MODE: + if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11B_MODE: + if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11GONLY_MODE: + if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + + case WMI_11G_MODE: + case WMI_11AG_MODE: + if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) { + isValid = FALSE; + } + break; + default: + A_ASSERT(FALSE); + break; + } + + return isValid; +} + +A_INT8 +wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate) +{ + A_INT8 i; + if (rate != -1) + { + for (i=0;;i++) + { + if (wmi_rateTable[(A_UINT32) i][0] == 0) { + return A_EINVAL; + } + if (wmi_rateTable[(A_UINT32) i][0] == rate) { + break; + } + } + } + else{ + i = -1; + } + + if(wmi_is_bitrate_index_valid(wmip, (A_INT32) i) != TRUE) { + return A_EINVAL; + } + + return i; +} + +A_STATUS +wmi_set_fixrates_cmd(struct wmi_t *wmip, A_UINT32 fixRatesMask) +{ + void *osbuf; + WMI_FIX_RATES_CMD *cmd; +#if 0 + A_INT32 rateIndex; +/* This check does not work for AR6003 as the HT modes are enabled only when + * the STA is connected to a HT_BSS and is not based only on channel. It is + * safe to skip this check however because rate control will only use rates + * that are permitted by the valid rate mask and the fix rate mask. Meaning + * the fix rate mask is not sufficient by itself to cause an invalid rate + * to be used. */ + /* Make sure all rates in the mask are valid in the current PHY mode */ + for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) { + if((1 << rateIndex) & (A_UINT32)fixRatesMask) { + if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) { + A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG)); + return A_EINVAL; + } + } + } +#endif + + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->fixRateMask = fixRatesMask; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_ratemask_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_FIXRATES_CMDID); +} + +A_STATUS +wmi_get_channelList_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_CHANNEL_LIST_CMDID); +} + +/* + * used to generate a wmi sey channel Parameters cmd. + * mode should always be specified and corresponds to the phy mode of the + * wlan. + * numChan should alway sbe specified. If zero indicates that all available + * channels should be used. + * channelList is an array of channel frequencies (in Mhz) which the radio + * should limit its operation to. It should be NULL if numChan == 0. Size of + * array should correspond to numChan entries. + */ +A_STATUS +wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam, + WMI_PHY_MODE mode, A_INT8 numChan, + A_UINT16 *channelList) +{ + void *osbuf; + WMI_CHANNEL_PARAMS_CMD *cmd; + A_INT8 size; + + size = sizeof (*cmd); + + if (numChan) { + if (numChan > WMI_MAX_CHANNELS) { + return A_EINVAL; + } + size += sizeof(A_UINT16) * (numChan - 1); + } + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + wmip->wmi_phyMode = mode; + cmd->scanParam = scanParam; + cmd->phyMode = mode; + cmd->numChannels = numChan; + A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_cache_configure_rssithreshold(struct wmi_t *wmip, WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_RSSI]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = rssiCmd->weight; + sq_thresh->polling_interval = rssiCmd->pollTime; + + sq_thresh->upper_threshold[0] = rssiCmd->thresholdAbove1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[1] = rssiCmd->thresholdAbove2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[2] = rssiCmd->thresholdAbove3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[3] = rssiCmd->thresholdAbove4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[4] = rssiCmd->thresholdAbove5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold[5] = rssiCmd->thresholdAbove6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->upper_threshold_valid_count = 6; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = rssiCmd->thresholdBelow6_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[1] = rssiCmd->thresholdBelow5_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[2] = rssiCmd->thresholdBelow4_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[3] = rssiCmd->thresholdBelow3_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[4] = rssiCmd->thresholdBelow2_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold[5] = rssiCmd->thresholdBelow1_Val - SIGNAL_QUALITY_NOISE_FLOOR; + sq_thresh->lower_threshold_valid_count = 6; + + if (!rssi_event_value) { + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + rssiCmd->thresholdAbove1_Val = sq_thresh->upper_threshold[0]; + rssiCmd->thresholdBelow1_Val = sq_thresh->lower_threshold[0]; + } else { + /* + * In case the user issues multiple times of rssi_threshold_setting, + * we should not use the extreames anymore, the target does not expect that. + */ + rssiCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(rssi_event_value, sq_thresh, + sq_thresh->upper_threshold_valid_count); + rssiCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(rssi_event_value, sq_thresh, + sq_thresh->lower_threshold_valid_count); +} +} + +A_STATUS +wmi_set_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + + /* Check these values are in ascending order */ + if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val || + rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val || + rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val || + rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val || + rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val || + rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val || + rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val || + rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val || + rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val || + rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + + wmi_cache_configure_rssithreshold(wmip, rssiCmd); + + return (wmi_send_rssi_threshold_params(wmip, rssiCmd)); +} + +A_STATUS +wmi_set_ip_cmd(struct wmi_t *wmip, WMI_SET_IP_CMD *ipCmd) +{ + void *osbuf; + WMI_SET_IP_CMD *cmd; + + /* Multicast address are not valid */ + if((*((A_UINT8*)&ipCmd->ips[0]) >= 0xE0) || + (*((A_UINT8*)&ipCmd->ips[1]) >= 0xE0)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_IP_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_SET_IP_CMD)); + cmd = (WMI_SET_IP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(cmd, ipCmd, sizeof(WMI_SET_IP_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_IP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, + WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_HOST_SLEEP_MODE_CMD *cmd; + A_UINT16 activeTsids=0; + A_UINT8 streamExists=0; + A_UINT8 i; + + if( hostModeCmd->awake == hostModeCmd->asleep) { + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD)); + + if(hostModeCmd->asleep) { + /* + * Relinquish credits from all implicitly created pstreams since when we + * go to sleep. If user created explicit thinstreams exists with in a + * fatpipe leave them intact for the user to delete + */ + LOCK_WMI(wmip); + streamExists = wmip->wmi_fatPipeExists; + UNLOCK_WMI(wmip); + + for(i=0;i< WMM_NUM_AC;i++) { + if (streamExists & (1<wmi_streamExistsForAC[i]; + UNLOCK_WMI(wmip); + /* If there are no user created thin streams delete the fatpipe */ + if(!activeTsids) { + streamExists &= ~(1<wmi_devt,i); + } + } + } + + /* Update the fatpipes that exists*/ + LOCK_WMI(wmip); + wmip->wmi_fatPipeExists = streamExists; + UNLOCK_WMI(wmip); + } + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wow_mode_cmd(struct wmi_t *wmip, + WMI_SET_WOW_MODE_CMD *wowModeCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SET_WOW_MODE_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_get_wow_list_cmd(struct wmi_t *wmip, + WMI_GET_WOW_LIST_CMD *wowListCmd) +{ + void *osbuf; + A_INT8 size; + WMI_GET_WOW_LIST_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID, + NO_SYNC_WMIFLAG)); + +} + +static A_STATUS +wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_GET_WOW_LIST_REPLY *reply; + + if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_GET_WOW_LIST_REPLY *)datap; + + A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters, + reply); + + return A_OK; +} + +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip, + WMI_ADD_WOW_PATTERN_CMD *addWowCmd, + A_UINT8* pattern, A_UINT8* mask, + A_UINT8 pattern_size) +{ + void *osbuf; + A_INT8 size; + WMI_ADD_WOW_PATTERN_CMD *cmd; + A_UINT8 *filter_mask = NULL; + + size = sizeof (*cmd); + + size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8)); + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->filter_list_id = addWowCmd->filter_list_id; + cmd->filter_offset = addWowCmd->filter_offset; + cmd->filter_size = addWowCmd->filter_size; + + A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size); + + filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size); + A_MEMCPY(filter_mask, mask, addWowCmd->filter_size); + + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_del_wow_pattern_cmd(struct wmi_t *wmip, + WMI_DEL_WOW_PATTERN_CMD *delWowCmd) +{ + void *osbuf; + A_INT8 size; + WMI_DEL_WOW_PATTERN_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID, + NO_SYNC_WMIFLAG)); + +} + +void +wmi_cache_configure_snrthreshold(struct wmi_t *wmip, WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + SQ_THRESHOLD_PARAMS *sq_thresh = + &wmip->wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_SNR]; + /* + * Parse the command and store the threshold values here. The checks + * for valid values can be put here + */ + sq_thresh->weight = snrCmd->weight; + sq_thresh->polling_interval = snrCmd->pollTime; + + sq_thresh->upper_threshold[0] = snrCmd->thresholdAbove1_Val; + sq_thresh->upper_threshold[1] = snrCmd->thresholdAbove2_Val; + sq_thresh->upper_threshold[2] = snrCmd->thresholdAbove3_Val; + sq_thresh->upper_threshold[3] = snrCmd->thresholdAbove4_Val; + sq_thresh->upper_threshold_valid_count = 4; + + /* List sorted in descending order */ + sq_thresh->lower_threshold[0] = snrCmd->thresholdBelow4_Val; + sq_thresh->lower_threshold[1] = snrCmd->thresholdBelow3_Val; + sq_thresh->lower_threshold[2] = snrCmd->thresholdBelow2_Val; + sq_thresh->lower_threshold[3] = snrCmd->thresholdBelow1_Val; + sq_thresh->lower_threshold_valid_count = 4; + + if (!snr_event_value) { + /* + * Configuring the thresholds to their extremes allows the host to get an + * event from the target which is used for the configuring the correct + * thresholds + */ + snrCmd->thresholdAbove1_Val = (A_UINT8)sq_thresh->upper_threshold[0]; + snrCmd->thresholdBelow1_Val = (A_UINT8)sq_thresh->lower_threshold[0]; + } else { + /* + * In case the user issues multiple times of snr_threshold_setting, + * we should not use the extreames anymore, the target does not expect that. + */ + snrCmd->thresholdAbove1_Val = ar6000_get_upper_threshold(snr_event_value, sq_thresh, + sq_thresh->upper_threshold_valid_count); + snrCmd->thresholdBelow1_Val = ar6000_get_lower_threshold(snr_event_value, sq_thresh, + sq_thresh->lower_threshold_valid_count); + } + +} +A_STATUS +wmi_set_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val || + snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val || + snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val || + snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val || + snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val || + snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val) + { + return A_EINVAL; + } + wmi_cache_configure_snrthreshold(wmip, snrCmd); + return (wmi_send_snr_threshold_params(wmip, snrCmd)); +} + +A_STATUS +wmi_clr_rssi_snr(struct wmi_t *wmip) +{ + void *osbuf; + + osbuf = A_NETBUF_ALLOC(sizeof(int)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lq_threshold_params(struct wmi_t *wmip, + WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd) +{ + void *osbuf; + A_INT8 size; + WMI_LQ_THRESHOLD_PARAMS_CMD *cmd; + /* These values are in ascending order */ + if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val || + lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val || + lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val || + lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val || + lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val || + lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) { + + return A_EINVAL; + } + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask) +{ + void *osbuf; + A_INT8 size; + WMI_TARGET_ERROR_REPORT_BITMASK *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + cmd->bitmask = mask; + + return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source) +{ + void *osbuf; + WMIX_HB_CHALLENGE_RESP_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->cookie = cookie; + cmd->source = source; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask, + A_UINT16 tsr, A_BOOL rep, A_UINT16 size, + A_UINT32 valid) +{ + void *osbuf; + WMIX_DBGLOG_CFG_MODULE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->config.cfgmmask = mmask; + cmd->config.cfgtsr = tsr; + cmd->config.cfgrep = rep; + cmd->config.cfgsize = size; + cmd->config.cfgvalid = valid; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_stats_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_STATISTICS_CMDID); +} + +A_STATUS +wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid) +{ + void *osbuf; + WMI_ADD_BAD_AP_CMD *cmd; + + if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + + return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, SYNC_BEFORE_WMIFLAG)); +} + +A_STATUS +wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex) +{ + void *osbuf; + WMI_DELETE_BAD_AP_CMD *cmd; + + if (apIndex > WMI_MAX_BAD_AP_INDEX) { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->badApIndex = apIndex; + + return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_abort_scan_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_ABORT_SCAN_CMDID); +} + +A_STATUS +wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM) +{ + void *osbuf; + WMI_SET_TX_PWR_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->dbM = dbM; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_get_txPwr_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_TX_PWR_CMDID); +} + +A_UINT16 +wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass) +{ + A_UINT16 activeTsids=0; + + LOCK_WMI(wmip); + activeTsids = wmip->wmi_streamExistsForAC[trafficClass]; + UNLOCK_WMI(wmip); + + return activeTsids; +} + +A_STATUS +wmi_get_roam_tbl_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd(wmip, WMI_GET_ROAM_TBL_CMDID); +} + +A_STATUS +wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType) +{ + void *osbuf; + A_UINT32 size = sizeof(A_UINT8); + WMI_TARGET_ROAM_DATA *cmd; + + osbuf = A_NETBUF_ALLOC(size); /* no payload */ + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf)); + cmd->roamDataType = roamDataType; + + return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p, + A_UINT8 size) +{ + void *osbuf; + WMI_SET_ROAM_CTRL_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, p, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_powersave_timers_cmd(struct wmi_t *wmip, + WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd, + A_UINT8 size) +{ + void *osbuf; + WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd; + + /* These timers can't be zero */ + if(!pCmd->psPollTimeout || !pCmd->triggerTimeout || + !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD || + pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) || + !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD || + pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD)) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + + A_MEMCPY(cmd, pCmd, size); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_GPIO_SUPPORT +/* Send a command to Target to change GPIO output pins. */ +A_STATUS +wmi_gpio_output_set(struct wmi_t *wmip, + A_UINT32 set_mask, + A_UINT32 clear_mask, + A_UINT32 enable_mask, + A_UINT32 disable_mask) +{ + void *osbuf; + WMIX_GPIO_OUTPUT_SET_CMD *output_set; + int size; + + size = sizeof(*output_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG, + set_mask, clear_mask, enable_mask, disable_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + output_set->set_mask = set_mask; + output_set->clear_mask = clear_mask; + output_set->enable_mask = enable_mask; + output_set->disable_mask = disable_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target requesting state of the GPIO input pins */ +A_STATUS +wmi_gpio_input_get(struct wmi_t *wmip) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID); +} + +/* Send a command to the Target that changes the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_set(struct wmi_t *wmip, + A_UINT32 gpioreg_id, + A_UINT32 value) +{ + void *osbuf; + WMIX_GPIO_REGISTER_SET_CMD *register_set; + int size; + + size = sizeof(*register_set); + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_set->gpioreg_id = gpioreg_id; + register_set->value = value; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target to fetch the value of a GPIO register. */ +A_STATUS +wmi_gpio_register_get(struct wmi_t *wmip, + A_UINT32 gpioreg_id) +{ + void *osbuf; + WMIX_GPIO_REGISTER_GET_CMD *register_get; + int size; + + size = sizeof(*register_get); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf)); + + register_get->gpioreg_id = gpioreg_id; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID, + NO_SYNC_WMIFLAG)); +} + +/* Send a command to the Target acknowledging some GPIO interrupts. */ +A_STATUS +wmi_gpio_intr_ack(struct wmi_t *wmip, + A_UINT32 ack_mask) +{ + void *osbuf; + WMIX_GPIO_INTR_ACK_CMD *intr_ack; + int size; + + size = sizeof(*intr_ack); + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf)); + + intr_ack->ack_mask = ack_mask; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_GPIO_SUPPORT */ + +A_STATUS +wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT8 ac, A_UINT16 txop, A_UINT8 eCWmin, + A_UINT8 eCWmax, A_UINT8 aifsn) +{ + void *osbuf; + WMI_SET_ACCESS_PARAMS_CMD *cmd; + + if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) || + (aifsn > WMI_MAX_AIFSN_ACPARAM) || (ac >= WMM_NUM_AC)) + { + return A_EINVAL; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->txop = txop; + cmd->eCWmin = eCWmin; + cmd->eCWmax = eCWmax; + cmd->aifsn = aifsn; + cmd->ac = ac; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType, + A_UINT8 trafficClass, A_UINT8 maxRetries, + A_UINT8 enableNotify) +{ + void *osbuf; + WMI_SET_RETRY_LIMITS_CMD *cmd; + + if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) && + (frameType != DATA_FRAMETYPE)) + { + return A_EINVAL; + } + + if (maxRetries > WMI_MAX_RETRIES) { + return A_EINVAL; + } + + if (frameType != DATA_FRAMETYPE) { + trafficClass = 0; + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->frameType = frameType; + cmd->trafficClass = trafficClass; + cmd->maxRetries = maxRetries; + cmd->enableNotify = enableNotify; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID, + NO_SYNC_WMIFLAG)); +} + +void +wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid) +{ + if (bssid != NULL) { + A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN); + } +} + +A_STATUS +wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode) +{ + void *osbuf; + WMI_SET_OPT_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->optMode = optMode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID, + SYNC_BOTH_WMIFLAG)); +} + +A_STATUS +wmi_opt_tx_frame_cmd(struct wmi_t *wmip, + A_UINT8 frmType, + A_UINT8 *dstMacAddr, + A_UINT8 *bssid, + A_UINT16 optIEDataLen, + A_UINT8 *optIEData) +{ + void *osbuf; + WMI_OPT_TX_FRAME_CMD *cmd; + osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd))); + + cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1)); + + cmd->frmType = frmType; + cmd->optIEDataLen = optIEDataLen; + //cmd->optIEData = (A_UINT8 *)((int)cmd + sizeof(*cmd)); + A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid)); + A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr)); + A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl) +{ + void *osbuf; + WMI_BEACON_INT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->beaconInterval = intvl; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize) +{ + void *osbuf; + WMI_SET_VOICE_PKT_SIZE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->voicePktSize = voicePktSize; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen) +{ + void *osbuf; + WMI_SET_MAX_SP_LEN_CMD *cmd; + + /* maxSPLen is a two-bit value. If user trys to set anything + * other than this, then its invalid + */ + if(maxSPLen & ~0x03) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->maxSPLen = maxSPLen; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_determine_userPriority( + A_UINT8 *pkt, + A_UINT32 layer2Pri) +{ + A_UINT8 ipPri; + iphdr *ipHdr = (iphdr *)pkt; + + /* Determine IPTOS priority */ + /* + * IP Tos format : + * (Refer Pg 57 WMM-test-plan-v1.2) + * IP-TOS - 8bits + * : DSCP(6-bits) ECN(2-bits) + * : DSCP - P2 P1 P0 X X X + * where (P2 P1 P0) form 802.1D + */ + ipPri = ipHdr->ip_tos >> 5; + ipPri &= 0x7; + + if ((layer2Pri & 0x7) > ipPri) + return ((A_UINT8)layer2Pri & 0x7); + else + return ipPri; +} + +A_UINT8 +convert_userPriority_to_trafficClass(A_UINT8 userPriority) +{ + return (up_to_ac[userPriority & 0x7]); +} + +A_UINT8 +wmi_get_power_mode_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_powerMode; +} + +A_STATUS +wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance) +{ + A_STATUS ret = A_OK; + +#define TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF (~0) +#define TSPEC_SERVICE_START_TIME_ATHEROS_DEF 0 +#define TSPEC_MAX_BURST_SIZE_ATHEROS_DEF 0 +#define TSPEC_DELAY_BOUND_ATHEROS_DEF 0 +#define TSPEC_MEDIUM_TIME_ATHEROS_DEF 0 +#define TSPEC_SBA_ATHEROS_DEF 0x2000 /* factor is 1 */ + + /* Verify TSPEC params for ATHEROS compliance */ + if(tspecCompliance == ATHEROS_COMPLIANCE) { + if ((pCmd->suspensionInt != TSPEC_SUSPENSION_INTERVAL_ATHEROS_DEF) || + (pCmd->serviceStartTime != TSPEC_SERVICE_START_TIME_ATHEROS_DEF) || + (pCmd->minDataRate != pCmd->meanDataRate) || + (pCmd->minDataRate != pCmd->peakDataRate) || + (pCmd->maxBurstSize != TSPEC_MAX_BURST_SIZE_ATHEROS_DEF) || + (pCmd->delayBound != TSPEC_DELAY_BOUND_ATHEROS_DEF) || + (pCmd->sba != TSPEC_SBA_ATHEROS_DEF) || + (pCmd->mediumTime != TSPEC_MEDIUM_TIME_ATHEROS_DEF)) { + + A_DPRINTF(DBG_WMI, (DBGFMT "Invalid TSPEC params\n", DBGARG)); + //A_PRINTF("%s: Invalid TSPEC params\n", __func__); + ret = A_EINVAL; + } + } + + return ret; +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +static A_STATUS +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len); + + return A_OK; +} + +#endif /* CONFIG_HOST_TCMD_SUPPORT*/ + +A_STATUS +wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_AUTH_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode) +{ + void *osbuf; + WMI_SET_REASSOC_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->mode = mode; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status, A_UINT8 preamblePolicy) +{ + void *osbuf; + WMI_SET_LPREAMBLE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + cmd->preamblePolicy = preamblePolicy; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold) +{ + void *osbuf; + WMI_SET_RTS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->threshold = threshold; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status) +{ + void *osbuf; + WMI_SET_WMM_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_qos_supp_cmd(struct wmi_t *wmip, A_UINT8 status) +{ + void *osbuf; + WMI_SET_QOS_SUPP_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_QOS_SUPP_CMD*)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->status = status; + return (wmi_cmd_send(wmip, osbuf, WMI_SET_QOS_SUPP_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg) +{ + void *osbuf; + WMI_SET_WMM_TXOP_CMD *cmd; + + if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) ) + return A_EINVAL; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->txopEnable = cfg; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_country(struct wmi_t *wmip, A_UCHAR *countryCode) +{ + void *osbuf; + WMI_AP_SET_COUNTRY_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_AP_SET_COUNTRY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + A_MEMCPY(cmd->countryCode,countryCode,3); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_COUNTRY_CMDID, + NO_SYNC_WMIFLAG)); +} + +#ifdef CONFIG_HOST_TCMD_SUPPORT +/* WMI layer doesn't need to know the data type of the test cmd. + This would be beneficial for customers like Qualcomm, who might + have different test command requirements from differnt manufacturers + */ +A_STATUS +wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len) +{ + void *osbuf; + char *data; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + osbuf= A_NETBUF_ALLOC(len); + if(osbuf == NULL) + { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, len); + data = A_NETBUF_DATA(osbuf); + A_MEMCPY(data, buf, len); + + return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID, + NO_SYNC_WMIFLAG)); +} + +#endif + +A_STATUS +wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status) +{ + void *osbuf; + WMI_SET_BT_STATUS_CMD *cmd; + + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Enter - streamType=%d, status=%d\n", streamType, status)); + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->streamType = streamType; + cmd->status = status; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd) +{ + void *osbuf; + WMI_SET_BT_PARAMS_CMD* alloc_cmd; + + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("cmd params is %d\n", cmd->paramType)); + + if (cmd->paramType == BT_PARAM_SCO) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("sco params %d %d %d %d %d %d %d %d %d %d %d %d\n", cmd->info.scoParams.numScoCyclesForceTrigger, + cmd->info.scoParams.dataResponseTimeout, + cmd->info.scoParams.stompScoRules, + cmd->info.scoParams.scoOptFlags, + cmd->info.scoParams.stompDutyCyleVal, + cmd->info.scoParams.stompDutyCyleMaxVal, + cmd->info.scoParams.psPollLatencyFraction, + cmd->info.scoParams.noSCOSlots, + cmd->info.scoParams.noIdleSlots, + cmd->info.scoParams.scoOptOffRssi, + cmd->info.scoParams.scoOptOnRssi, + cmd->info.scoParams.scoOptRtsCount)); + } + else if (cmd->paramType == BT_PARAM_A2DP) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("A2DP params %d %d %d %d %d %d %d %d\n", cmd->info.a2dpParams.a2dpWlanUsageLimit, + cmd->info.a2dpParams.a2dpBurstCntMin, + cmd->info.a2dpParams.a2dpDataRespTimeout, + cmd->info.a2dpParams.a2dpOptFlags, + cmd->info.a2dpParams.isCoLocatedBtRoleMaster, + cmd->info.a2dpParams.a2dpOptOffRssi, + cmd->info.a2dpParams.a2dpOptOnRssi, + cmd->info.a2dpParams.a2dpOptRtsCount)); + } + else if (cmd->paramType == BT_PARAM_ANTENNA_CONFIG) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Ant config %d\n", cmd->info.antType)); + } + else if (cmd->paramType == BT_PARAM_COLOCATED_BT_DEVICE) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("co-located BT %d\n", cmd->info.coLocatedBtDev)); + } + else if (cmd->paramType == BT_PARAM_ACLCOEX) { + AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("ACL params %d %d %d\n", cmd->info.aclCoexParams.aclWlanMediumUsageTime, + cmd->info.aclCoexParams.aclBtMediumUsageTime, + cmd->info.aclCoexParams.aclDataRespTimeout)); + } + else if (cmd->paramType == BT_PARAM_11A_SEPARATE_ANT) { + A_DPRINTF(DBG_WMI, (DBGFMT "11A ant\n", DBGARG)); + } + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_btcoex_fe_ant_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_FE_ANT_CMD * cmd) +{ + void *osbuf; + WMI_SET_BTCOEX_FE_ANT_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_SET_BTCOEX_FE_ANT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_FE_ANT_CMD)); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_FE_ANT_CMDID, + NO_SYNC_WMIFLAG)); + +} + + +A_STATUS +wmi_set_btcoex_colocated_bt_dev_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD * cmd) +{ + void *osbuf; + WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD)); + A_PRINTF("colocated bt = %d\n", alloc_cmd->btcoexCoLocatedBTdev); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_btcoex_btinquiry_page_config_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD* cmd) +{ + void *osbuf; + WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD)); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMDID, + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_btcoex_sco_config_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_SCO_CONFIG_CMD * cmd) +{ + void *osbuf; + WMI_SET_BTCOEX_SCO_CONFIG_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_SET_BTCOEX_SCO_CONFIG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_SCO_CONFIG_CMD)); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_SCO_CONFIG_CMDID , + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_btcoex_a2dp_config_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_A2DP_CONFIG_CMD * cmd) +{ + void *osbuf; + WMI_SET_BTCOEX_A2DP_CONFIG_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_SET_BTCOEX_A2DP_CONFIG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_A2DP_CONFIG_CMD)); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_A2DP_CONFIG_CMDID , + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_btcoex_aclcoex_config_cmd(struct wmi_t *wmip, + WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD * cmd) +{ + void *osbuf; + WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD)); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMDID , + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_btcoex_debug_cmd(struct wmi_t *wmip, WMI_SET_BTCOEX_DEBUG_CMD * cmd) +{ + void *osbuf; + WMI_SET_BTCOEX_DEBUG_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_SET_BTCOEX_DEBUG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_DEBUG_CMD)); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_DEBUG_CMDID , + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_set_btcoex_bt_operating_status_cmd(struct wmi_t * wmip, + WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD * cmd) +{ + void *osbuf; + WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD)); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID , + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_get_btcoex_config_cmd(struct wmi_t * wmip, WMI_GET_BTCOEX_CONFIG_CMD * cmd) +{ + void *osbuf; + WMI_GET_BTCOEX_CONFIG_CMD *alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + alloc_cmd = (WMI_GET_BTCOEX_CONFIG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd,cmd,sizeof(WMI_GET_BTCOEX_CONFIG_CMD)); + return (wmi_cmd_send(wmip, osbuf, WMI_GET_BTCOEX_CONFIG_CMDID , + NO_SYNC_WMIFLAG)); + +} + +A_STATUS +wmi_get_btcoex_stats_cmd(struct wmi_t *wmip) +{ + + return wmi_simple_cmd(wmip, WMI_GET_BTCOEX_STATS_CMDID); + +} + +A_STATUS +wmi_get_keepalive_configured(struct wmi_t *wmip) +{ + void *osbuf; + WMI_GET_KEEPALIVE_CMD *cmd; + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_UINT8 +wmi_get_keepalive_cmd(struct wmi_t *wmip) +{ + return wmip->wmi_keepaliveInterval; +} + +A_STATUS +wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval) +{ + void *osbuf; + WMI_SET_KEEPALIVE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->keepaliveInterval = keepaliveInterval; + wmip->wmi_keepaliveInterval = keepaliveInterval; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_params_cmd(struct wmi_t *wmip, A_UINT32 opcode, A_UINT32 length, A_CHAR* buffer) +{ + void *osbuf; + WMI_SET_PARAMS_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + length); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd) + length); + + cmd = (WMI_SET_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->opcode = opcode; + cmd->length = length; + A_MEMCPY(cmd->buffer, buffer, length); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_del_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 dot1, A_UINT8 dot2, A_UINT8 dot3, A_UINT8 dot4) +{ + void *osbuf; + WMI_SET_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->multicast_mac[0] = 0x01; + cmd->multicast_mac[1] = 0x00; + cmd->multicast_mac[2] = 0x5e; + cmd->multicast_mac[3] = dot2&0x7F; + cmd->multicast_mac[4] = dot3; + cmd->multicast_mac[5] = dot4; + + return (wmi_cmd_send(wmip, osbuf, WMI_DEL_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_mcast_filter_cmd(struct wmi_t *wmip, A_UINT8 enable) +{ + void *osbuf; + WMI_MCAST_FILTER_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_MCAST_FILTER_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->enable = enable; + + return (wmi_cmd_send(wmip, osbuf, WMI_MCAST_FILTER_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen, + A_UINT8 *ieInfo) +{ + void *osbuf; + WMI_SET_APPIE_CMD *cmd; + A_UINT16 cmdLen; + + cmdLen = sizeof(*cmd) + ieLen - 1; + osbuf = A_NETBUF_ALLOC(cmdLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, cmdLen); + + cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, cmdLen); + + cmd->mgmtFrmType = mgmtFrmType; + cmd->ieLen = ieLen; + A_MEMCPY(cmd->ieInfo, ieInfo, ieLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen) +{ + void *osbuf; + A_UINT8 *data; + + osbuf = A_NETBUF_ALLOC(dataLen); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, dataLen); + + data = A_NETBUF_DATA(osbuf); + + A_MEMCPY(data, cmd, dataLen); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG)); +} + +A_INT32 +wmi_get_rate(A_INT8 rateindex) +{ + if (rateindex == RATE_AUTO) { + return 0; + } else { + return(wmi_rateTable[(A_UINT32) rateindex][0]); + } +} + +void +wmi_node_return (struct wmi_t *wmip, bss_t *bss) +{ + if (NULL != bss) + { + wlan_node_return (&wmip->wmi_scan_table, bss); + } +} + +void +wmi_set_nodeage(struct wmi_t *wmip, A_UINT32 nodeAge) +{ + wlan_set_nodeage(&wmip->wmi_scan_table,nodeAge); +} + +bss_t * +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, A_BOOL bIsWPA2, A_BOOL bMatchSSID) +{ + bss_t *node = NULL; + node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid, + ssidLength, bIsWPA2, bMatchSSID); + return node; +} + + +void +wmi_free_allnodes(struct wmi_t *wmip) +{ + wlan_free_allnodes(&wmip->wmi_scan_table); +} + +bss_t * +wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + return ni; +} + +void +wmi_free_node(struct wmi_t *wmip, const A_UINT8 *macaddr) +{ + bss_t *ni=NULL; + + ni=wlan_find_node(&wmip->wmi_scan_table,macaddr); + if (ni != NULL) { + wlan_node_reclaim(&wmip->wmi_scan_table, ni); + } + + return; +} + +A_STATUS +wmi_dset_open_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT32 access_cookie, + A_UINT32 dset_size, + A_UINT32 dset_version, + A_UINT32 targ_handle, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETOPEN_REPLY_CMD *open_reply; + + A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip)); + + osbuf = A_NETBUF_ALLOC(sizeof(*open_reply)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*open_reply)); + open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + open_reply->status = status; + open_reply->targ_dset_handle = targ_handle; + open_reply->targ_reply_fn = targ_reply_fn; + open_reply->targ_reply_arg = targ_reply_arg; + open_reply->access_cookie = access_cookie; + open_reply->size = dset_size; + open_reply->version = dset_version; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_PMKID_LIST_REPLY *reply; + A_UINT32 expected_len; + + if (len < sizeof(WMI_PMKID_LIST_REPLY)) { + return A_EINVAL; + } + reply = (WMI_PMKID_LIST_REPLY *)datap; + expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN; + + if (len < expected_len) { + return A_EINVAL; + } + + A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID, + reply->pmkidList, reply->bssidList[0]); + + return A_OK; +} + + +static A_STATUS +wmi_set_params_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len) +{ + WMI_SET_PARAMS_REPLY *reply; + + if (len < sizeof(WMI_SET_PARAMS_REPLY)) { + return A_EINVAL; + } + reply = (WMI_SET_PARAMS_REPLY *)datap; + + if (A_OK == reply->status) + { + + } + else + { + + } + + return A_OK; +} + + + +#ifdef CONFIG_HOST_DSET_SUPPORT +A_STATUS +wmi_dset_data_reply(struct wmi_t *wmip, + A_UINT32 status, + A_UINT8 *user_buf, + A_UINT32 length, + A_UINT32 targ_buf, + A_UINT32 targ_reply_fn, + A_UINT32 targ_reply_arg) +{ + void *osbuf; + WMIX_DSETDATA_REPLY_CMD *data_reply; + A_UINT32 size; + + size = sizeof(*data_reply) + length; + + if (size <= length) { + return A_ERROR; + } + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status)); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + A_NETBUF_PUT(osbuf, size); + data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf)); + + data_reply->status = status; + data_reply->targ_buf = targ_buf; + data_reply->targ_reply_fn = targ_reply_fn; + data_reply->targ_reply_arg = targ_reply_arg; + data_reply->length = length; + + if (status == A_OK) { + if (a_copy_from_user(data_reply->buf, user_buf, length)) { + A_NETBUF_FREE(osbuf); + return A_ERROR; + } + } + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif /* CONFIG_HOST_DSET_SUPPORT */ + +A_STATUS +wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status) +{ + void *osbuf; + char *cmd; + + wps_enable = status; + + osbuf = a_netbuf_alloc(sizeof(1)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + a_netbuf_put(osbuf, sizeof(1)); + + cmd = (char *)(a_netbuf_to_data(osbuf)); + + A_MEMZERO(cmd, sizeof(*cmd)); + cmd[0] = (status?1:0); + return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID, + NO_SYNC_WMIFLAG)); +} + +#if defined(CONFIG_TARGET_PROFILE_SUPPORT) +A_STATUS +wmi_prof_cfg_cmd(struct wmi_t *wmip, + A_UINT32 period, + A_UINT32 nbins) +{ + void *osbuf; + WMIX_PROF_CFG_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_CFG_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->period = period; + cmd->nbins = nbins; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_CFG_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_addr_set_cmd(struct wmi_t *wmip, A_UINT32 addr) +{ + void *osbuf; + WMIX_PROF_ADDR_SET_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMIX_PROF_ADDR_SET_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->addr = addr; + + return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_PROF_ADDR_SET_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_prof_start_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_START_CMDID); +} + +A_STATUS +wmi_prof_stop_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_STOP_CMDID); +} + +A_STATUS +wmi_prof_count_get_cmd(struct wmi_t *wmip) +{ + return wmi_simple_cmd_xtnd(wmip, WMIX_PROF_COUNT_GET_CMDID); +} + +/* Called to handle WMIX_PROF_CONT_EVENTID */ +static A_STATUS +wmi_prof_count_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMIX_PROF_COUNT_EVENT *prof_data = (WMIX_PROF_COUNT_EVENT *)datap; + + A_DPRINTF(DBG_WMI, + (DBGFMT "Enter - addr=0x%x count=%d\n", DBGARG, + prof_data->addr, prof_data->count)); + + A_WMI_PROF_COUNT_RX(prof_data->addr, prof_data->count); + + return A_OK; +} +#endif /* CONFIG_TARGET_PROFILE_SUPPORT */ + +#ifdef OS_ROAM_MANAGEMENT + +#define ETHERNET_MAC_ADDRESS_LENGTH 6 + +void +wmi_scan_indication (struct wmi_t *wmip) +{ + struct ieee80211_node_table *nt; + A_UINT32 gen; + A_UINT32 size; + A_UINT32 bsssize; + bss_t *bss; + A_UINT32 numbss; + PNDIS_802_11_BSSID_SCAN_INFO psi; + PBYTE pie; + NDIS_802_11_FIXED_IEs *pFixed; + NDIS_802_11_VARIABLE_IEs *pVar; + A_UINT32 RateSize; + + struct ar6kScanIndication + { + NDIS_802_11_STATUS_INDICATION ind; + NDIS_802_11_BSSID_SCAN_INFO_LIST slist; + } *pAr6kScanIndEvent; + + nt = &wmip->wmi_scan_table; + + ++nt->nt_si_gen; + + + gen = nt->nt_si_gen; + + size = offsetof(struct ar6kScanIndication, slist) + + offsetof(NDIS_802_11_BSSID_SCAN_INFO_LIST, BssidScanInfo); + + numbss = 0; + + IEEE80211_NODE_LOCK(nt); + + //calc size + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + bsssize = offsetof(NDIS_802_11_BSSID_SCAN_INFO, Bssid) + offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + size += bsssize; + + numbss++; + } + } + + if (0 == numbss) + { +// RETAILMSG(1, (L"AR6K: scan indication: 0 bss\n")); + ar6000_scan_indication (wmip->wmi_devt, NULL, 0); + IEEE80211_NODE_UNLOCK (nt); + return; + } + + pAr6kScanIndEvent = A_MALLOC(size); + + if (NULL == pAr6kScanIndEvent) + { + IEEE80211_NODE_UNLOCK(nt); + return; + } + + A_MEMZERO(pAr6kScanIndEvent, size); + + //copy data + pAr6kScanIndEvent->ind.StatusType = Ndis802_11StatusType_BssidScanInfoList; + pAr6kScanIndEvent->slist.Version = 1; + pAr6kScanIndEvent->slist.NumItems = numbss; + + psi = &pAr6kScanIndEvent->slist.BssidScanInfo[0]; + + for (bss = nt->nt_node_first; bss; bss = bss->ni_list_next) { + if (bss->ni_si_gen != gen) { + + bss->ni_si_gen = gen; + + //Set scan time + psi->ScanTime = bss->ni_tstamp - WLAN_NODE_INACT_TIMEOUT_MSEC; + + // Copy data to bssid_ex + bsssize = offsetof(NDIS_WLAN_BSSID_EX, IEs); + bsssize = bsssize + sizeof(NDIS_802_11_FIXED_IEs); + +#ifdef SUPPORT_WPA2 + if (bss->ni_cie.ie_rsn) { + bsssize = bsssize + bss->ni_cie.ie_rsn[1] + 2; + } +#endif + if (bss->ni_cie.ie_wpa) { + bsssize = bsssize + bss->ni_cie.ie_wpa[1] + 2; + } + + // bsssize must be a multiple of 4 to maintain alignment. + bsssize = (bsssize + 3) & ~3; + + psi->Bssid.Length = bsssize; + + memcpy (psi->Bssid.MacAddress, bss->ni_macaddr, ETHERNET_MAC_ADDRESS_LENGTH); + + +//if (((bss->ni_macaddr[3] == 0xCE) && (bss->ni_macaddr[4] == 0xF0) && (bss->ni_macaddr[5] == 0xE7)) || +// ((bss->ni_macaddr[3] == 0x03) && (bss->ni_macaddr[4] == 0xE2) && (bss->ni_macaddr[5] == 0x70))) +// RETAILMSG (1, (L"%x\n",bss->ni_macaddr[5])); + + psi->Bssid.Ssid.SsidLength = 0; + pie = bss->ni_cie.ie_ssid; + + if (pie) { + // Format of SSID IE is: + // Type (1 octet) + // Length (1 octet) + // SSID (Length octets) + // + // Validation of the IE should have occurred within WMI. + // + if (pie[1] <= 32) { + psi->Bssid.Ssid.SsidLength = pie[1]; + memcpy(psi->Bssid.Ssid.Ssid, &pie[2], psi->Bssid.Ssid.SsidLength); + } + } + psi->Bssid.Privacy = (bss->ni_cie.ie_capInfo & 0x10) ? 1 : 0; + + //Post the RSSI value relative to the Standard Noise floor value. + psi->Bssid.Rssi = bss->ni_rssi; + + if (bss->ni_cie.ie_chan >= 2412 && bss->ni_cie.ie_chan <= 2484) { + + if (bss->ni_cie.ie_rates && bss->ni_cie.ie_xrates) { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM24; + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11DS; + } + } + else { + psi->Bssid.NetworkTypeInUse = Ndis802_11OFDM5; + } + + psi->Bssid.Configuration.Length = sizeof(psi->Bssid.Configuration); + psi->Bssid.Configuration.BeaconPeriod = bss->ni_cie.ie_beaconInt; // Units are Kmicroseconds (1024 us) + psi->Bssid.Configuration.ATIMWindow = 0; + psi->Bssid.Configuration.DSConfig = bss->ni_cie.ie_chan * 1000; + psi->Bssid.InfrastructureMode = ((bss->ni_cie.ie_capInfo & 0x03) == 0x01 ) ? Ndis802_11Infrastructure : Ndis802_11IBSS; + + RateSize = 0; + pie = bss->ni_cie.ie_rates; + if (pie) { + RateSize = (pie[1] < NDIS_802_11_LENGTH_RATES_EX) ? pie[1] : NDIS_802_11_LENGTH_RATES_EX; + memcpy(psi->Bssid.SupportedRates, &pie[2], RateSize); + } + pie = bss->ni_cie.ie_xrates; + if (pie && RateSize < NDIS_802_11_LENGTH_RATES_EX) { + memcpy(psi->Bssid.SupportedRates + RateSize, &pie[2], + (pie[1] < (NDIS_802_11_LENGTH_RATES_EX - RateSize)) ? pie[1] : (NDIS_802_11_LENGTH_RATES_EX - RateSize)); + } + + // Copy the fixed IEs + psi->Bssid.IELength = sizeof(NDIS_802_11_FIXED_IEs); + + pFixed = (NDIS_802_11_FIXED_IEs *)psi->Bssid.IEs; + memcpy(pFixed->Timestamp, bss->ni_cie.ie_tstamp, sizeof(pFixed->Timestamp)); + pFixed->BeaconInterval = bss->ni_cie.ie_beaconInt; + pFixed->Capabilities = bss->ni_cie.ie_capInfo; + + // Copy selected variable IEs + + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pFixed + sizeof(NDIS_802_11_FIXED_IEs)); + +#ifdef SUPPORT_WPA2 + // Copy the WPAv2 IE + if (bss->ni_cie.ie_rsn) { + pie = bss->ni_cie.ie_rsn; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } +#endif + // Copy the WPAv1 IE + if (bss->ni_cie.ie_wpa) { + pie = bss->ni_cie.ie_wpa; + psi->Bssid.IELength += pie[1] + 2; + memcpy(pVar, pie, pie[1] + 2); + pVar = (NDIS_802_11_VARIABLE_IEs *)((PBYTE)pVar + pie[1] + 2); + } + + // Advance buffer pointer + psi = (PNDIS_802_11_BSSID_SCAN_INFO)((BYTE*)psi + bsssize + FIELD_OFFSET(NDIS_802_11_BSSID_SCAN_INFO, Bssid)); + } + } + + IEEE80211_NODE_UNLOCK(nt); + +// wmi_free_allnodes(wmip); + +// RETAILMSG(1, (L"AR6K: scan indication: %u bss\n", numbss)); + + ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size); + + A_FREE(pAr6kScanIndEvent); +} +#endif + +A_UINT8 +ar6000_get_upper_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->upper_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi < sq_thresh->upper_threshold[index]) { + threshold = (A_UINT8)sq_thresh->upper_threshold[index]; + break; + } + } + + return threshold; +} + +A_UINT8 +ar6000_get_lower_threshold(A_INT16 rssi, SQ_THRESHOLD_PARAMS *sq_thresh, + A_UINT32 size) +{ + A_UINT32 index; + A_UINT8 threshold = (A_UINT8)sq_thresh->lower_threshold[size - 1]; + + /* The list is already in sorted order. Get the next lower value */ + for (index = 0; index < size; index ++) { + if (rssi > sq_thresh->lower_threshold[index]) { + threshold = (A_UINT8)sq_thresh->lower_threshold[index]; + break; + } + } + + return threshold; +} +static A_STATUS +wmi_send_rssi_threshold_params(struct wmi_t *wmip, + WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd) +{ + void *osbuf; + A_INT8 size; + WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + + cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} +static A_STATUS +wmi_send_snr_threshold_params(struct wmi_t *wmip, + WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd) +{ + void *osbuf; + A_INT8 size; + WMI_SNR_THRESHOLD_PARAMS_CMD *cmd; + + size = sizeof (*cmd); + + osbuf = A_NETBUF_ALLOC(size); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, size); + cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, size); + A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_target_event_report_cmd(struct wmi_t *wmip, WMI_SET_TARGET_EVENT_REPORT_CMD* cmd) +{ + void *osbuf; + WMI_SET_TARGET_EVENT_REPORT_CMD* alloc_cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + alloc_cmd = (WMI_SET_TARGET_EVENT_REPORT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(alloc_cmd, sizeof(*cmd)); + A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TARGET_EVENT_REPORT_CMDID, + NO_SYNC_WMIFLAG)); +} + +bss_t *wmi_rm_current_bss (struct wmi_t *wmip, A_UINT8 *id) +{ + wmi_get_current_bssid (wmip, id); + return wlan_node_remove (&wmip->wmi_scan_table, id); +} + +A_STATUS wmi_add_current_bss (struct wmi_t *wmip, A_UINT8 *id, bss_t *bss) +{ + wlan_setup_node (&wmip->wmi_scan_table, bss, id); + return A_OK; +} + +#ifdef ATH_AR6K_11N_SUPPORT +static A_STATUS +wmi_addba_req_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_ADDBA_REQ_EVENT *cmd = (WMI_ADDBA_REQ_EVENT *)datap; + + A_WMI_AGGR_RECV_ADDBA_REQ_EVT(wmip->wmi_devt, cmd); + + return A_OK; +} + + +static A_STATUS +wmi_addba_resp_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_ADDBA_RESP_EVENT *cmd = (WMI_ADDBA_RESP_EVENT *)datap; + + A_WMI_AGGR_RECV_ADDBA_RESP_EVT(wmip->wmi_devt, cmd); + + return A_OK; +} + +static A_STATUS +wmi_delba_req_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_DELBA_EVENT *cmd = (WMI_DELBA_EVENT *)datap; + + A_WMI_AGGR_RECV_DELBA_REQ_EVT(wmip->wmi_devt, cmd); + + return A_OK; +} + +A_STATUS +wmi_btcoex_config_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_BTCOEX_CONFIG_EVENT(wmip->wmi_devt, datap, len); + + return A_OK; +} + + +A_STATUS +wmi_btcoex_stats_event_rx(struct wmi_t * wmip,A_UINT8 * datap,int len) +{ + A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG)); + + A_WMI_BTCOEX_STATS_EVENT(wmip->wmi_devt, datap, len); + + return A_OK; + +} +#endif + +static A_STATUS +wmi_hci_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_HCI_EVENT *cmd = (WMI_HCI_EVENT *)datap; + A_WMI_HCI_EVENT_EVT(wmip->wmi_devt, cmd); + + return A_OK; +} + +//////////////////////////////////////////////////////////////////////////////// +//// //// +//// AP mode functions //// +//// //// +//////////////////////////////////////////////////////////////////////////////// +/* + * IOCTL: AR6000_XIOCTL_AP_COMMIT_CONFIG + * + * When AR6K in AP mode, This command will be called after + * changing ssid, channel etc. It will pass the profile to + * target with a flag which will indicate which parameter changed, + * also if this flag is 0, there was no change in parametes, so + * commit cmd will not be sent to target. Without calling this IOCTL + * the changes will not take effect. + */ +A_STATUS +wmi_ap_profile_commit(struct wmi_t *wmip, WMI_CONNECT_CMD *p) +{ + void *osbuf; + WMI_CONNECT_CMD *cm; + + osbuf = A_NETBUF_ALLOC(sizeof(*cm)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cm)); + cm = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cm, sizeof(*cm)); + + A_MEMCPY(cm,p,sizeof(*cm)); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONFIG_COMMIT_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_HIDDEN_SSID + * + * This command will be used to enable/disable hidden ssid functioanlity of + * beacon. If it is enabled, ssid will be NULL in beacon. + */ +A_STATUS +wmi_ap_set_hidden_ssid(struct wmi_t *wmip, A_UINT8 hidden_ssid) +{ + void *osbuf; + WMI_AP_HIDDEN_SSID_CMD *hs; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_HIDDEN_SSID_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_HIDDEN_SSID_CMD)); + hs = (WMI_AP_HIDDEN_SSID_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(hs, sizeof(*hs)); + + hs->hidden_ssid = hidden_ssid; + + A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_HIDDEN_SSID %d\n", DBGARG , hidden_ssid)); + return (wmi_cmd_send(wmip, osbuf, WMI_AP_HIDDEN_SSID_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_MAX_NUM_STA + * + * This command is used to limit max num of STA that can connect + * with this AP. This value should not exceed AP_MAX_NUM_STA (this + * is max num of STA supported by AP). Value was already validated + * in ioctl.c + */ +A_STATUS +wmi_ap_set_num_sta(struct wmi_t *wmip, A_UINT8 num_sta) +{ + void *osbuf; + WMI_AP_SET_NUM_STA_CMD *ns; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_NUM_STA_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_NUM_STA_CMD)); + ns = (WMI_AP_SET_NUM_STA_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(ns, sizeof(*ns)); + + ns->num_sta = num_sta; + + A_DPRINTF(DBG_WMI, (DBGFMT "AR6000_XIOCTL_AP_SET_MAX_NUM_STA %d\n", DBGARG , num_sta)); + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_NUM_STA_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_ACL_MAC + * + * This command is used to send list of mac of STAs which will + * be allowed to connect with this AP. When this list is empty + * firware will allow all STAs till the count reaches AP_MAX_NUM_STA. + */ +A_STATUS +wmi_ap_acl_mac_list(struct wmi_t *wmip, WMI_AP_ACL_MAC_CMD *acl) +{ + void *osbuf; + WMI_AP_ACL_MAC_CMD *a; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_MAC_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_MAC_CMD)); + a = (WMI_AP_ACL_MAC_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(a, sizeof(*a)); + A_MEMCPY(a,acl,sizeof(*acl)); + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_MAC_LIST_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_MLME + * + * This command is used to send list of mac of STAs which will + * be allowed to connect with this AP. When this list is empty + * firware will allow all STAs till the count reaches AP_MAX_NUM_STA. + */ +A_STATUS +wmi_ap_set_mlme(struct wmi_t *wmip, A_UINT8 cmd, A_UINT8 *mac, A_UINT16 reason) +{ + void *osbuf; + WMI_AP_SET_MLME_CMD *mlme; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_MLME_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_MLME_CMD)); + mlme = (WMI_AP_SET_MLME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(mlme, sizeof(*mlme)); + + mlme->cmd = cmd; + A_MEMCPY(mlme->mac, mac, ATH_MAC_LEN); + mlme->reason = reason; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_MLME_CMDID, NO_SYNC_WMIFLAG)); +} + +static A_STATUS +wmi_pspoll_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len) +{ + WMI_PSPOLL_EVENT *ev; + + if (len < sizeof(WMI_PSPOLL_EVENT)) { + return A_EINVAL; + } + ev = (WMI_PSPOLL_EVENT *)datap; + + A_WMI_PSPOLL_EVENT(wmip->wmi_devt, ev->aid); + return A_OK; +} + +static A_STATUS +wmi_dtimexpiry_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len) +{ + A_WMI_DTIMEXPIRY_EVENT(wmip->wmi_devt); + return A_OK; +} + +#ifdef WAPI_ENABLE +static A_STATUS +wmi_wapi_rekey_event_rx(struct wmi_t *wmip, A_UINT8 *datap,int len) +{ + A_UINT8 *ev; + + if (len < 7) { + return A_EINVAL; + } + ev = (A_UINT8 *)datap; + + A_WMI_WAPI_REKEY_EVENT(wmip->wmi_devt, *ev, &ev[1]); + return A_OK; +} +#endif + +A_STATUS +wmi_set_pvb_cmd(struct wmi_t *wmip, A_UINT16 aid, A_BOOL flag) +{ + WMI_AP_SET_PVB_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_PVB_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_PVB_CMD)); + cmd = (WMI_AP_SET_PVB_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->aid = aid; + cmd->flag = flag; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_PVB_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_conn_inact_time(struct wmi_t *wmip, A_UINT32 period) +{ + WMI_AP_CONN_INACT_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_CONN_INACT_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_CONN_INACT_CMD)); + cmd = (WMI_AP_CONN_INACT_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->period = period; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_CONN_INACT_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_bgscan_time(struct wmi_t *wmip, A_UINT32 period, A_UINT32 dwell) +{ + WMI_AP_PROT_SCAN_TIME_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_PROT_SCAN_TIME_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_PROT_SCAN_TIME_CMD)); + cmd = (WMI_AP_PROT_SCAN_TIME_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->period_min = period; + cmd->dwell_ms = dwell; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_PROT_SCAN_TIME_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_set_dtim(struct wmi_t *wmip, A_UINT8 dtim) +{ + WMI_AP_SET_DTIM_CMD *cmd; + void *osbuf = NULL; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_DTIM_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_DTIM_CMD)); + cmd = (WMI_AP_SET_DTIM_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + + cmd->dtim = dtim; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_DTIM_CMDID, NO_SYNC_WMIFLAG)); +} + +/* + * IOCTL: AR6000_XIOCTL_AP_SET_ACL_POLICY + * + * This command is used to set ACL policay. While changing policy, if you + * want to retain the existing MAC addresses in the ACL list, policy should be + * OR with AP_ACL_RETAIN_LIST_MASK, else the existing list will be cleared. + * If there is no chage in policy, the list will be intact. + */ +A_STATUS +wmi_ap_set_acl_policy(struct wmi_t *wmip, A_UINT8 policy) +{ + void *osbuf; + WMI_AP_ACL_POLICY_CMD *po; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_ACL_POLICY_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; +} + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_ACL_POLICY_CMD)); + po = (WMI_AP_ACL_POLICY_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(po, sizeof(*po)); + + po->policy = policy; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_ACL_POLICY_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_ap_set_rateset(struct wmi_t *wmip, A_UINT8 rateset) +{ + void *osbuf; + WMI_AP_SET_11BG_RATESET_CMD *rs; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_AP_SET_11BG_RATESET_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_AP_SET_11BG_RATESET_CMD)); + rs = (WMI_AP_SET_11BG_RATESET_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(rs, sizeof(*rs)); + + rs->rateset = rateset; + + return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_11BG_RATESET_CMDID, NO_SYNC_WMIFLAG)); +} + +#ifdef ATH_AR6K_11N_SUPPORT +A_STATUS +wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd) +{ + void *osbuf; + WMI_SET_HT_CAP_CMD *htCap; + + osbuf = A_NETBUF_ALLOC(sizeof(*htCap)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*htCap)); + + htCap = (WMI_SET_HT_CAP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(htCap, sizeof(*htCap)); + A_MEMCPY(htCap, cmd, sizeof(*htCap)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_CAP_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_ht_op_cmd(struct wmi_t *wmip, A_UINT8 sta_chan_width) +{ + void *osbuf; + WMI_SET_HT_OP_CMD *htInfo; + + osbuf = A_NETBUF_ALLOC(sizeof(*htInfo)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*htInfo)); + + htInfo = (WMI_SET_HT_OP_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(htInfo, sizeof(*htInfo)); + htInfo->sta_chan_width = sta_chan_width; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_OP_CMDID, + NO_SYNC_WMIFLAG)); +} +#endif + +A_STATUS +wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, A_UINT32 *pMaskArray) +{ + void *osbuf; + WMI_SET_TX_SELECT_RATES_CMD *pData; + + osbuf = A_NETBUF_ALLOC(sizeof(*pData)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*pData)); + + pData = (WMI_SET_TX_SELECT_RATES_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMCPY(pData, pMaskArray, sizeof(*pData)); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_SELECT_RATES_CMDID, + NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_send_hci_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT16 sz) +{ + void *osbuf; + WMI_HCI_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd) + sz); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd) + sz); + cmd = (WMI_HCI_CMD *)(A_NETBUF_DATA(osbuf)); + + cmd->cmd_buf_sz = sz; + A_MEMCPY(cmd->buf, buf, sz); + return (wmi_cmd_send(wmip, osbuf, WMI_HCI_CMD_CMDID, NO_SYNC_WMIFLAG)); +} + +#ifdef ATH_AR6K_11N_SUPPORT +A_STATUS +wmi_allow_aggr_cmd(struct wmi_t *wmip, A_UINT16 tx_tidmask, A_UINT16 rx_tidmask) +{ + void *osbuf; + WMI_ALLOW_AGGR_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ALLOW_AGGR_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->tx_allow_aggr = tx_tidmask; + cmd->rx_allow_aggr = rx_tidmask; + + return (wmi_cmd_send(wmip, osbuf, WMI_ALLOW_AGGR_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_setup_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid) +{ + void *osbuf; + WMI_ADDBA_REQ_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_ADDBA_REQ_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->tid = tid; + + return (wmi_cmd_send(wmip, osbuf, WMI_ADDBA_REQ_CMDID, NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_delete_aggr_cmd(struct wmi_t *wmip, A_UINT8 tid, A_BOOL uplink) +{ + void *osbuf; + WMI_DELBA_REQ_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_DELBA_REQ_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->tid = tid; + cmd->is_sender_initiator = uplink; /* uplink =1 - uplink direction, 0=downlink direction */ + + /* Delete the local aggr state, on host */ + return (wmi_cmd_send(wmip, osbuf, WMI_DELBA_REQ_CMDID, NO_SYNC_WMIFLAG)); +} +#endif + +A_STATUS +wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, A_UINT8 rxMetaVersion, + A_BOOL rxDot11Hdr, A_BOOL defragOnHost) +{ + void *osbuf; + WMI_RX_FRAME_FORMAT_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_RX_FRAME_FORMAT_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->dot11Hdr = (rxDot11Hdr==TRUE)? 1:0; + cmd->defragOnHost = (defragOnHost==TRUE)? 1:0; + cmd->metaVersion = rxMetaVersion; /* */ + + /* Delete the local aggr state, on host */ + return (wmi_cmd_send(wmip, osbuf, WMI_RX_FRAME_FORMAT_CMDID, NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_thin_mode_cmd(struct wmi_t *wmip, A_BOOL bThinMode) +{ + void *osbuf; + WMI_SET_THIN_MODE_CMD *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_THIN_MODE_CMD *)(A_NETBUF_DATA(osbuf)); + cmd->enable = (bThinMode==TRUE)? 1:0; + + /* Delete the local aggr state, on host */ + return (wmi_cmd_send(wmip, osbuf, WMI_SET_THIN_MODE_CMDID, NO_SYNC_WMIFLAG)); +} + + +A_STATUS +wmi_set_wlan_conn_precedence_cmd(struct wmi_t *wmip, BT_WLAN_CONN_PRECEDENCE precedence) +{ + void *osbuf; + WMI_SET_BT_WLAN_CONN_PRECEDENCE *cmd; + + osbuf = A_NETBUF_ALLOC(sizeof(*cmd)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(*cmd)); + + cmd = (WMI_SET_BT_WLAN_CONN_PRECEDENCE *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(cmd, sizeof(*cmd)); + cmd->precedence = precedence; + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_WLAN_CONN_PRECEDENCE_CMDID, + NO_SYNC_WMIFLAG)); +} + +A_STATUS +wmi_set_pmk_cmd(struct wmi_t *wmip, A_UINT8 *pmk) +{ + void *osbuf; + WMI_SET_PMK_CMD *p; + + osbuf = A_NETBUF_ALLOC(sizeof(WMI_SET_PMK_CMD)); + if (osbuf == NULL) { + return A_NO_MEMORY; + } + + A_NETBUF_PUT(osbuf, sizeof(WMI_SET_PMK_CMD)); + + p = (WMI_SET_PMK_CMD *)(A_NETBUF_DATA(osbuf)); + A_MEMZERO(p, sizeof(*p)); + + A_MEMCPY(p->pmk, pmk, WMI_PMK_LEN); + + return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMK_CMDID, NO_SYNC_WMIFLAG)); +} + +bss_t * +wmi_find_matching_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid, + A_UINT32 ssidLength, + A_UINT32 dot11AuthMode, A_UINT32 authMode, + A_UINT32 pairwiseCryptoType, A_UINT32 grpwiseCryptoTyp) +{ + bss_t *node = NULL; + node = wlan_find_matching_Ssidnode (&wmip->wmi_scan_table, pSsid, + ssidLength, dot11AuthMode, authMode, pairwiseCryptoType, grpwiseCryptoTyp); + + return node; +} + +A_UINT16 +wmi_ieee2freq (int chan) +{ + A_UINT16 freq = 0; + freq = wlan_ieee2freq (chan); + return freq; + +} + +A_UINT32 +wmi_freq2ieee (A_UINT16 freq) +{ + A_UINT16 chan = 0; + chan = wlan_freq2ieee (freq); + return chan; +} diff --git a/drivers/net/wireless/ath6kl/wmi/wmi_host.h b/drivers/net/wireless/ath6kl/wmi/wmi_host.h new file mode 100644 index 000000000000..474e239e316c --- /dev/null +++ b/drivers/net/wireless/ath6kl/wmi/wmi_host.h @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License version 2 as +// published by the Free Software Foundation; +// +// Software distributed under the License is distributed on an "AS +// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +// implied. See the License for the specific language governing +// rights and limitations under the License. +// +// +//------------------------------------------------------------------------------ +//============================================================================== +// This file contains local definitios for the wmi host module. +// +// Author(s): ="Atheros" +//============================================================================== +#ifndef _WMI_HOST_H_ +#define _WMI_HOST_H_ + +#include "roaming.h" +#ifdef __cplusplus +extern "C" { +#endif + +struct wmi_stats { + A_UINT32 cmd_len_err; + A_UINT32 cmd_id_err; +}; + +#define SSID_IE_LEN_INDEX 13 + +/* Host side link management data structures */ +#define SIGNAL_QUALITY_THRESHOLD_LEVELS 6 +#define SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +#define SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS SIGNAL_QUALITY_THRESHOLD_LEVELS +typedef struct sq_threshold_params_s { + A_INT16 upper_threshold[SIGNAL_QUALITY_UPPER_THRESHOLD_LEVELS]; + A_INT16 lower_threshold[SIGNAL_QUALITY_LOWER_THRESHOLD_LEVELS]; + A_UINT32 upper_threshold_valid_count; + A_UINT32 lower_threshold_valid_count; + A_UINT32 polling_interval; + A_UINT8 weight; + A_UINT8 last_rssi; //normally you would expect this to be bss specific but we keep only one instance because its only valid when the device is in a connected state. Not sure if it belongs to host or target. + A_UINT8 last_rssi_poll_event; //Not sure if it belongs to host or target +} SQ_THRESHOLD_PARAMS; +struct wmi_t { + A_BOOL wmi_ready; + A_BOOL wmi_numQoSStream; + A_UINT16 wmi_streamExistsForAC[WMM_NUM_AC]; + A_UINT8 wmi_fatPipeExists; + void *wmi_devt; + struct wmi_stats wmi_stats; + struct ieee80211_node_table wmi_scan_table; + A_UINT8 wmi_bssid[ATH_MAC_LEN]; + A_UINT8 wmi_powerMode; + A_UINT8 wmi_phyMode; + A_UINT8 wmi_keepaliveInterval; + A_MUTEX_T wmi_lock; + HTC_ENDPOINT_ID wmi_endpoint_id; + SQ_THRESHOLD_PARAMS wmi_SqThresholdParams[SIGNAL_QUALITY_METRICS_NUM_MAX]; + CRYPTO_TYPE wmi_pair_crypto_type; + CRYPTO_TYPE wmi_grp_crypto_type; + A_BOOL wmi_is_wmm_enabled; +}; + + +#define LOCK_WMI(w) A_MUTEX_LOCK(&(w)->wmi_lock); +#define UNLOCK_WMI(w) A_MUTEX_UNLOCK(&(w)->wmi_lock); + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_HOST_H_ */ diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index d0f5ad306078..d41e74acf785 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -290,6 +290,14 @@ config AT91_CF Say Y here to support the CompactFlash controller on AT91 chips. Or choose M to compile the driver as a module named "at91_cf". +config PCMCIA_MX31ADS + tristate "MX31ADS PCMCIA support" + depends on ARM && MACH_MX31ADS && PCMCIA + help + Say Y here to include support for the Freescale i.MX31 PCMCIA controller. + + This driver is also available as a module called mx31ads_pcmcia. + config ELECTRA_CF tristate "Electra CompactFlash Controller" depends on PCMCIA && PPC_PASEMI diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index d006e8beab9c..2eebf736d600 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_BFIN_CFPCMCIA) += bfin_cf_pcmcia.o obj-$(CONFIG_AT91_CF) += at91_cf.o obj-$(CONFIG_ELECTRA_CF) += electra_cf.o obj-$(CONFIG_PCMCIA_ALCHEMY_DEVBOARD) += db1xxx_ss.o +obj-$(CONFIG_PCMCIA_MX31ADS) += mx31ads-pcmcia.o au1x00_ss-y += au1000_generic.o au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o diff --git a/drivers/pcmcia/mx31ads-pcmcia.c b/drivers/pcmcia/mx31ads-pcmcia.c new file mode 100644 index 000000000000..1f7c8ec2c7e0 --- /dev/null +++ b/drivers/pcmcia/mx31ads-pcmcia.c @@ -0,0 +1,1293 @@ +/*====================================================================== + drivers/pcmcia/mx31ads-pcmica.c + + Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + + Device driver for the PCMCIA control functionality of i.Mx31 + microprocessors. + + The contents of this file are subject to the Mozilla Public + License Version 1.1 (the "License"); you may not use this file + except in compliance with the License. You may obtain a copy of + the License at http://www.mozilla.org/MPL/ + + Software distributed under the License is distributed on an "AS + IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or + implied. See the License for the specific language governing + rights and limitations under the License. + + The initial developer of the original code is John G. Dorsey + . Portions created by John G. Dorsey are + Copyright (C) 1999 John G. Dorsey. All Rights Reserved. + + Alternatively, the contents of this file may be used under the + terms of the GNU Public License version 2 (the "GPL"), in which + case the provisions of the GPL are applicable instead of the + above. If you wish to allow the use of your version of this file + only under the terms of the GPL and not to allow others to use + your version of this file under the MPL, indicate your decision + by deleting the provisions above and replace them with the notice + and other provisions required by the GPL. If you do not delete + the provisions above, a recipient may use your version of this + file under either the MPL or the GPL. + +======================================================================*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "mx31ads-pcmcia.h" +#include + +#define MX31ADS_PCMCIA_IRQ MXC_INT_PCMCIA + +/* + * The mapping of window size to bank size value + */ +static bsize_map_t bsize_map[] = { + /* Window size Bank size */ + {POR_1, POR_BSIZE_1}, + {POR_2, POR_BSIZE_2}, + {POR_4, POR_BSIZE_4}, + {POR_8, POR_BSIZE_8}, + {POR_16, POR_BSIZE_16}, + {POR_32, POR_BSIZE_32}, + {POR_64, POR_BSIZE_64}, + {POR_128, POR_BSIZE_128}, + {POR_256, POR_BSIZE_256}, + {POR_512, POR_BSIZE_512}, + + {POR_1K, POR_BSIZE_1K}, + {POR_2K, POR_BSIZE_2K}, + {POR_4K, POR_BSIZE_4K}, + {POR_8K, POR_BSIZE_8K}, + {POR_16K, POR_BSIZE_16K}, + {POR_32K, POR_BSIZE_32K}, + {POR_64K, POR_BSIZE_64K}, + {POR_128K, POR_BSIZE_128K}, + {POR_256K, POR_BSIZE_256K}, + {POR_512K, POR_BSIZE_512K}, + + {POR_1M, POR_BSIZE_1M}, + {POR_2M, POR_BSIZE_2M}, + {POR_4M, POR_BSIZE_4M}, + {POR_8M, POR_BSIZE_8M}, + {POR_16M, POR_BSIZE_16M}, + {POR_32M, POR_BSIZE_32M}, + {POR_64M, POR_BSIZE_64M} +}; + +#define to_mx31ads_pcmcia_socket(x) container_of(x, struct mx31ads_pcmcia_socket, socket) + +/* mx31ads_pcmcia_find_bsize() + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * Find the bsize according to the window size passed in + * + * Return: + */ +static int mx31ads_pcmcia_find_bsize(unsigned long win_size) +{ + int i, nr = sizeof(bsize_map) / sizeof(bsize_map_t); + int bsize = -1; + + for (i = 0; i < nr; i++) { + if (bsize_map[i].win_size == win_size) { + bsize = bsize_map[i].bsize; + break; + } + } + + pr_debug(KERN_INFO "nr = %d bsize = 0x%0x\n", nr, bsize); + if (bsize < 0 || i > nr) { + pr_debug(KERN_INFO "No such bsize\n"); + return -ENODEV; + } + + return bsize; +} + +/* mx31ads_common_pcmcia_sock_init() + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * (Re-)Initialise the socket, turning on status interrupts + * and PCMCIA bus. This must wait for power to stabilise + * so that the card status signals report correctly. + * + * Returns: 0 + */ +static int mx31ads_common_pcmcia_sock_init(struct pcmcia_socket *sock) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + + pr_debug(KERN_INFO "initializing socket\n"); + + skt->ops->socket_init(skt); + return 0; +} + +/* + * mx31ads_common_pcmcia_config_skt + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * Convert PCMCIA socket state to our socket configure structure. + */ +static int +mx31ads_common_pcmcia_config_skt(struct mx31ads_pcmcia_socket *skt, + socket_state_t *state) +{ + int ret; + + ret = skt->ops->configure_socket(skt, state); + if (ret == 0) { + /* + * This really needs a better solution. The IRQ + * may or may not be claimed by the driver. + */ + if (skt->irq_state != 1 && state->io_irq) { + skt->irq_state = 1; + set_irq_type(skt->irq, IRQF_TRIGGER_FALLING); + } else if (skt->irq_state == 1 && state->io_irq == 0) { + skt->irq_state = 0; + set_irq_type(skt->irq, IRQF_TRIGGER_RISING); + } + + skt->cs_state = *state; + } + + if (ret < 0) + pr_debug(KERN_ERR "mx31ads_common_pcmcia: unable to configure" + " socket\n"); + + return ret; +} + +/* + * mx31ads_common_pcmcia_suspend() + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * Remove power on the socket, disable IRQs from the card. + * Turn off status interrupts, and disable the PCMCIA bus. + * + * Returns: 0 + */ +static int mx31ads_common_pcmcia_suspend(struct pcmcia_socket *sock) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + int ret; + + pr_debug(KERN_INFO "suspending socket\n"); + + ret = mx31ads_common_pcmcia_config_skt(skt, &dead_socket); + if (ret == 0) + skt->ops->socket_suspend(skt); + + return ret; +} + +static unsigned int mx31ads_common_pcmcia_skt_state(struct mx31ads_pcmcia_socket + *skt) +{ + struct pcmcia_state state; + unsigned int stat; + + memset(&state, 0, sizeof(struct pcmcia_state)); + + skt->ops->socket_state(skt, &state); + + stat = state.detect ? SS_DETECT : 0; + stat |= state.ready ? SS_READY : 0; + stat |= state.wrprot ? SS_WRPROT : 0; + stat |= state.vs_3v ? SS_3VCARD : 0; + stat |= state.vs_Xv ? SS_XVCARD : 0; + + /* The power status of individual sockets is not available + * explicitly from the hardware, so we just remember the state + * and regurgitate it upon request: + */ + stat |= skt->cs_state.Vcc ? SS_POWERON : 0; + + if (skt->cs_state.flags & SS_IOCARD) + stat |= state.bvd1 ? SS_STSCHG : 0; + else { + if (state.bvd1 == 0) + stat |= SS_BATDEAD; + else if (state.bvd2 == 0) + stat |= SS_BATWARN; + } + + pr_debug(KERN_INFO "stat = 0x%08x\n", stat); + + return stat; +} + +/* + * Implements the get_status() operation for the in-kernel PCMCIA + * service (formerly SS_GetStatus in Card Services). Essentially just + * fills in bits in `status' according to internal driver state or + * the value of the voltage detect chipselect register. + * + * As a debugging note, during card startup, the PCMCIA core issues + * three set_socket() commands in a row the first with RESET deasserted, + * the second with RESET asserted, and the last with RESET deasserted + * again. Following the third set_socket(), a get_status() command will + * be issued. The kernel is looking for the SS_READY flag (see + * setup_socket(), reset_socket(), and unreset_socket() in cs.c). + * + * Returns: 0 + */ +static int mx31ads_common_pcmcia_get_status(struct pcmcia_socket *sock, + unsigned int *status) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + + skt->status = mx31ads_common_pcmcia_skt_state(skt); + *status = skt->status; + + return 0; +} + +/* + * Implements the set_socket() operation for the in-kernel PCMCIA + * service (formerly SS_SetSocket in Card Services). We more or + * less punt all of this work and let the kernel handle the details + * of power configuration, reset, &c. We also record the value of + * `state' in order to regurgitate it to the PCMCIA core later. + * + * Returns: 0 + */ +static int mx31ads_common_pcmcia_set_socket(struct pcmcia_socket *sock, + socket_state_t *state) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + + pr_debug(KERN_INFO + "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n", + (state->csc_mask == 0) ? " " : "", + (state->csc_mask & SS_DETECT) ? "DETECT " : "", + (state->csc_mask & SS_READY) ? "READY " : "", + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "", + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "", + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "", + (state->flags == 0) ? " " : "", + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "", + (state->flags & SS_IOCARD) ? "IOCARD " : "", + (state->flags & SS_RESET) ? "RESET " : "", + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "", + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "", + state->Vcc, state->Vpp, state->io_irq); + + pr_debug(KERN_INFO + "csc_mask: %08x flags: %08x Vcc: %d Vpp: %d io_irq: %d\n", + state->csc_mask, state->flags, state->Vcc, state->Vpp, + state->io_irq); + + return mx31ads_common_pcmcia_config_skt(skt, state); +} + +/* + * Set address and profile to window registers PBR, POR, POFR + */ +static int mx31ads_pcmcia_set_window_reg(ulong start, ulong end, u_int window) +{ + int bsize; + ulong size = end - start + 1; + + bsize = mx31ads_pcmcia_find_bsize(size); + if (bsize < 0) { + pr_debug("Cannot set the window register\n"); + return -1; + } + /* Disable the window */ + _reg_PCMCIA_POR(window) &= ~PCMCIA_POR_PV; + + /* Set PBR, POR, POFR */ + _reg_PCMCIA_PBR(window) = start; + _reg_PCMCIA_POR(window) &= ~(PCMCIA_POR_PRS_MASK + | PCMCIA_POR_WPEN + | PCMCIA_POR_WP + | PCMCIA_POR_BSIZE_MASK + | PCMCIA_POR_PPS_8); + _reg_PCMCIA_POR(window) |= bsize | PCMCIA_POR_PPS_16; + + switch (window) { + case IO_WINDOW: + _reg_PCMCIA_POR(window) |= PCMCIA_POR_PRS(PCMCIA_POR_PRS_IO); + break; + + case ATTRIBUTE_MEMORY_WINDOW: + _reg_PCMCIA_POR(window) |= + PCMCIA_POR_PRS(PCMCIA_POR_PRS_ATTRIBUTE); + break; + + case COMMON_MEMORY_WINDOW: + _reg_PCMCIA_POR(window) |= + PCMCIA_POR_PRS(PCMCIA_POR_PRS_COMMON); + break; + + default: + pr_debug("Window %d is not support\n", window); + return -1; + } + _reg_PCMCIA_POFR(window) = 0; + + /* Enable the window */ + _reg_PCMCIA_POR(window) |= PCMCIA_POR_PV; + + return 0; +} + +/* + * Implements the set_io_map() operation for the in-kernel PCMCIA + * service (formerly SS_SetIOMap in Card Services). We configure + * the map speed as requested, but override the address ranges + * supplied by Card Services. + * + * Returns: 0 on success, -1 on error + */ +static int +mx31ads_common_pcmcia_set_io_map(struct pcmcia_socket *sock, + struct pccard_io_map *map) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + unsigned short speed = map->speed; + + pr_debug("map %u speed %u start 0x%08x stop 0x%08x\n", + map->map, map->speed, map->start, map->stop); + pr_debug("flags: %s%s%s%s%s%s%s%s\n", + (map->flags == 0) ? "" : "", + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "", + (map->flags & MAP_16BIT) ? "16BIT " : "", + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "", + (map->flags & MAP_0WS) ? "0WS " : "", + (map->flags & MAP_WRPROT) ? "WRPROT " : "", + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "", + (map->flags & MAP_PREFETCH) ? "PREFETCH " : ""); + + if (map->map >= MAX_IO_WIN) { + pr_debug(KERN_ERR "%s(): map (%d) out of range\n", __FUNCTION__, + map->map); + return -1; + } + + if (map->flags & MAP_ACTIVE) { + if (speed == 0) + speed = PCMCIA_IO_ACCESS; + } else { + speed = 0; + } + + skt->spd_io[map->map] = speed; + skt->ops->set_timing(skt); + + if (map->stop == 1) + map->stop = PAGE_SIZE - 1; + + skt->socket.io_offset = (unsigned long)skt->virt_io; + map->stop -= map->start; + map->stop += (unsigned long)skt->virt_io; + map->start = (unsigned long)skt->virt_io; + + mx31ads_pcmcia_set_window_reg(skt->res_io.start, skt->res_io.end, + IO_WINDOW); + + pr_debug(KERN_ERR "IO window: _reg_PCMCIA_PBR(%d) = %08x\n", + IO_WINDOW, _reg_PCMCIA_PBR(IO_WINDOW)); + pr_debug(KERN_ERR "IO window: _reg_PCMCIA_POR(%d) = %08x\n", + IO_WINDOW, _reg_PCMCIA_POR(IO_WINDOW)); + + return 0; +} + +/* + * Implements the set_mem_map() operation for the in-kernel PCMCIA + * service (formerly SS_SetMemMap in Card Services). We configure + * the map speed as requested, but override the address ranges + * supplied by Card Services. + * + * Returns: 0 on success, -1 on error + */ +static int +mx31ads_common_pcmcia_set_mem_map(struct pcmcia_socket *sock, + struct pccard_mem_map *map) +{ + struct mx31ads_pcmcia_socket *skt = to_mx31ads_pcmcia_socket(sock); + struct resource *res; + unsigned short speed = map->speed; + + pr_debug + (KERN_INFO + "map %u speed %u card_start %08x flags%08x static_start %08lx\n", + map->map, map->speed, map->card_start, map->flags, + map->static_start); + pr_debug(KERN_INFO "flags: %s%s%s%s%s%s%s%s\n", + (map->flags == 0) ? "" : "", + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "", + (map->flags & MAP_16BIT) ? "16BIT " : "", + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "", + (map->flags & MAP_0WS) ? "0WS " : "", + (map->flags & MAP_WRPROT) ? "WRPROT " : "", + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "", + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : ""); + + if (map->map >= MAX_WIN) + return -EINVAL; + + if (map->flags & MAP_ACTIVE) { + if (speed == 0) + speed = 300; + } else { + speed = 0; + } + + if (map->flags & MAP_ATTRIB) { + res = &skt->res_attr; + skt->spd_attr[map->map] = speed; + skt->spd_mem[map->map] = 0; + mx31ads_pcmcia_set_window_reg(res->start, res->end, + ATTRIBUTE_MEMORY_WINDOW); + + pr_debug(KERN_INFO "Attr window: _reg_PCMCIA_PBR(%d) = %08x\n", + ATTRIBUTE_MEMORY_WINDOW, + _reg_PCMCIA_PBR(ATTRIBUTE_MEMORY_WINDOW)); + pr_debug(KERN_INFO "_reg_PCMCIA_POR(%d) = %08x\n", + ATTRIBUTE_MEMORY_WINDOW, + _reg_PCMCIA_POR(ATTRIBUTE_MEMORY_WINDOW)); + + } else { + res = &skt->res_mem; + skt->spd_attr[map->map] = 0; + skt->spd_mem[map->map] = speed; + mx31ads_pcmcia_set_window_reg(res->start, res->end, + COMMON_MEMORY_WINDOW); + + pr_debug(KERN_INFO "Com window: _reg_PCMCIA_PBR(%d) = %08x\n", + COMMON_MEMORY_WINDOW, + _reg_PCMCIA_PBR(COMMON_MEMORY_WINDOW)); + pr_debug(KERN_INFO "Com window: _reg_PCMCIA_POR(%d) = %08x\n", + COMMON_MEMORY_WINDOW, + _reg_PCMCIA_POR(COMMON_MEMORY_WINDOW)); + } + + skt->ops->set_timing(skt); + + map->static_start = res->start + map->card_start; + + return 0; +} + +static struct pccard_operations mx31ads_common_pcmcia_operations = { + .init = mx31ads_common_pcmcia_sock_init, + .suspend = mx31ads_common_pcmcia_suspend, + .get_status = mx31ads_common_pcmcia_get_status, + .set_socket = mx31ads_common_pcmcia_set_socket, + .set_io_map = mx31ads_common_pcmcia_set_io_map, + .set_mem_map = mx31ads_common_pcmcia_set_mem_map, +}; + +/* ============================================================================== */ + +static inline void mx31ads_pcmcia_irq_config(void) +{ + /* Setup irq */ + _reg_PCMCIA_PER = + (PCMCIA_PER_RDYLE | PCMCIA_PER_CDE1 | PCMCIA_PER_CDE2); +} + +static inline void mx31ads_pcmcia_invalidate_windows(void) +{ + int i; + + for (i = 0; i < PCMCIA_WINDOWS; i++) { + _reg_PCMCIA_PBR(i) = 0; + _reg_PCMCIA_POR(i) = 0; + _reg_PCMCIA_POFR(i) = 0; + } +} + +extern void gpio_pcmcia_active(void); +extern void gpio_pcmcia_inactive(void); + +static int mx31ads_pcmcia_hw_init(struct mx31ads_pcmcia_socket *skt) +{ + /* Configure the pins for PCMCIA */ + gpio_pcmcia_active(); + + /* + * enabling interrupts at this time causes a flood of interrupts + * if a card is present, so wait for configure_socket + * to enable them when requested. + * + * mx31ads_pcmcia_irq_config(); + */ + mx31ads_pcmcia_invalidate_windows(); + + /* Register interrupt. */ + skt->irq = MX31ADS_PCMCIA_IRQ; + + return 0; +} + +static void mx31ads_pcmcia_free_irq(struct mx31ads_pcmcia_socket *skt, + unsigned int irq) +{ + free_irq(irq, skt); +} + +static void mx31ads_pcmcia_hw_shutdown(struct mx31ads_pcmcia_socket *skt) +{ + mx31ads_pcmcia_invalidate_windows(); + mx31ads_pcmcia_free_irq(skt, MX31ADS_PCMCIA_IRQ); + + /* Disable the pins */ + gpio_pcmcia_inactive(); +} + +/* + * Get the socket state + */ +static void +mx31ads_pcmcia_socket_state(struct mx31ads_pcmcia_socket *skt, + struct pcmcia_state *state) +{ + unsigned long pins; + + pins = _reg_PCMCIA_PIPR; + pr_debug(KERN_INFO "_reg_PCMCIA_PIPR = 0x%08lx\n", pins); + + state->ready = (pins & PCMCIA_PIPR_RDY) ? 1 : 0; + state->bvd2 = (pins & PCMCIA_PIPR_BVD2) ? 1 : 0; + state->bvd1 = (pins & PCMCIA_PIPR_BVD1) ? 1 : 0; + + if ((pins & PCMCIA_PIPR_CD) == PCMCIA_PIPR_CD) { + state->detect = 0; + skt->cs_state.csc_mask |= SS_INSERTION; + } else { + state->detect = 1; + } + state->detect = (pins & PCMCIA_PIPR_CD) ? 0 : 1; + state->wrprot = (pins & PCMCIA_PIPR_WP) ? 1 : 0; + state->poweron = (pins & PCMCIA_PIPR_POWERON) ? 1 : 0; +#if 0 + if ((pins & PCMCIA_PIPR_CD) == PCMCIA_PIPR_CD) { + state->detect = 0; + skt->cs_state.csc_mask |= SS_INSERTION; + } else { + state->detect = 1; + } + if (pins & PCMCIA_PIPR_VS_5V) { + state->vs_3v = 0; + skt->cs_state.Vcc = 33; + } else { + state->vs_3v = 1; + skt->cs_state.Vcc = 50; + } +#endif + state->vs_3v = (pins & PCMCIA_PIPR_VS_5V) ? 0 : 1; + state->vs_Xv = 0; +} + +static __inline__ void mx31ads_pcmcia_low_power(bool enable) +{ + if (enable) + _reg_PCMCIA_PGCR |= PCMCIA_PGCR_LPMEN; + else + _reg_PCMCIA_PGCR &= ~PCMCIA_PGCR_LPMEN; +} + +static __inline__ void mx31ads_pcmcia_soft_reset(void) +{ + _reg_PCMCIA_PGCR |= PCMCIA_PGCR_RESET; + msleep(2); + + _reg_PCMCIA_PGCR &= ~(PCMCIA_PGCR_RESET | PCMCIA_PGCR_LPMEN); + _reg_PCMCIA_PGCR |= PCMCIA_PGCR_POE; + msleep(2); + pr_debug(KERN_INFO "_reg_PCMCIA_PGCR = %08x\n", _reg_PCMCIA_PGCR); +} + +static int +mx31ads_pcmcia_configure_socket(struct mx31ads_pcmcia_socket *skt, + const socket_state_t *state) +{ + int ret = 0; + + if (state->Vcc != 0 && state->Vcc != 33 && state->Vcc != 50) { + pr_debug(KERN_ERR "mx31ads-pcmcia: unrecognized Vcc %d\n", + state->Vcc); + return -1; + } + + pr_debug(KERN_INFO "PIPR = %x, desired Vcc = %d.%dV\n", + _reg_PCMCIA_PIPR, state->Vcc / 10, state->Vcc % 10); + + if (!(skt->socket.state & SOCKET_PRESENT) && (skt->pre_stat == 1)) { + pr_debug(KERN_INFO "Socket enter low power mode\n"); + skt->pre_stat = 0; + mx31ads_pcmcia_low_power(1); + } + + if (state->flags & SS_RESET) { + mx31ads_pcmcia_soft_reset(); + + /* clean out previous tenant's trash */ + _reg_PCMCIA_PGSR = (PCMCIA_PGSR_NWINE + | PCMCIA_PGSR_LPE + | PCMCIA_PGSR_SE + | PCMCIA_PGSR_CDE | PCMCIA_PGSR_WPE); + } + /* enable interrupts if requested, else turn 'em off */ + if (skt->irq) + mx31ads_pcmcia_irq_config(); + else + _reg_PCMCIA_PER = 0; + + if (skt->socket.state & SOCKET_PRESENT) { + skt->pre_stat = 1; + } + return ret; +} + +static void mx31ads_pcmcia_enable_irq(struct mx31ads_pcmcia_socket *skt, + unsigned int irq) +{ + set_irq_type(irq, IRQF_TRIGGER_RISING); + set_irq_type(irq, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING); +} + +static void mx31ads_pcmcia_disable_irq(struct mx31ads_pcmcia_socket *skt, + unsigned int irq) +{ + set_irq_type(irq, IRQF_TRIGGER_NONE); +} + +/* + * Enable card status IRQs on (re-)initialisation. This can + * be called at initialisation, power management event, or + * pcmcia event. + */ +static void mx31ads_pcmcia_socket_init(struct mx31ads_pcmcia_socket *skt) +{ + mx31ads_pcmcia_soft_reset(); + + mx31ads_pcmcia_enable_irq(skt, MX31ADS_PCMCIA_IRQ); +} + +/* + * Disable card status IRQ on suspend. + */ +static void mx31ads_pcmcia_socket_suspend(struct mx31ads_pcmcia_socket *skt) +{ + mx31ads_pcmcia_disable_irq(skt, MX31ADS_PCMCIA_IRQ); + mx31ads_pcmcia_low_power(1); +} + +/* ==================================================================================== */ + +/* + * PCMCIA strobe hold time + */ +static inline u_int mx31ads_pcmcia_por_psht(u_int pcmcia_cycle_ns, + u_int hclk_cycle_ns) +{ + u_int psht; + + return psht = pcmcia_cycle_ns / hclk_cycle_ns; +} + +/* + * PCMCIA strobe set up time + */ +static inline u_int mx31ads_pcmcia_por_psst(u_int pcmcia_cycle_ns, + u_int hclk_cycle_ns) +{ + u_int psst; + + return psst = pcmcia_cycle_ns / hclk_cycle_ns; +} + +/* + * PCMCIA strobe length time + */ +static inline u_int mx31ads_pcmcia_por_pslt(u_int pcmcia_cycle_ns, + u_int hclk_cycle_ns) +{ + u_int pslt; + + return pslt = pcmcia_cycle_ns / hclk_cycle_ns + 2; +} + +/* + * mx31ads_pcmcia_default_mecr_timing + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * Calculate MECR clock wait states for given CPU clock + * speed and command wait state. This function can be over- + * written by a board specific version. + * + * The default is to simply calculate the BS values as specified in + * the INTEL SA1100 development manual + * "Expansion Memory (PCMCIA) Configuration Register (MECR)" + * that's section 10.2.5 in _my_ version of the manual ;) + */ +static unsigned int mx31ads_pcmcia_default_mecr_timing(struct + mx31ads_pcmcia_socket + *skt, + unsigned int cpu_speed, + unsigned int cmd_time) +{ + return 0; +} + +/* + * Calculate the timing code + */ +static u_int mx31ads_pcmcia_cal_code(u_int speed_ns, u_int clk_ns) +{ + u_int code; + + code = PCMCIA_POR_PSHT(mx31ads_pcmcia_por_psht(speed_ns, clk_ns)) + | PCMCIA_POR_PSST(mx31ads_pcmcia_por_psst(speed_ns, clk_ns)) + | PCMCIA_POR_PSL(mx31ads_pcmcia_por_pslt(speed_ns, clk_ns)); + + return code; +} + +/* + * set MECR value for socket based on this sockets + * io, mem and attribute space access speed. + * Call board specific BS value calculation to allow boards + * to tweak the BS values. + */ +static int mx31ads_pcmcia_set_window_timing(u_int speed_ns, u_int window, + u_int clk_ns) +{ + u_int code = 0; + + switch (window) { + case IO_WINDOW: + code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns); + break; + case COMMON_MEMORY_WINDOW: + code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns); + break; + case ATTRIBUTE_MEMORY_WINDOW: + code = mx31ads_pcmcia_cal_code(speed_ns, clk_ns); + break; + default: + break; + } + + /* Disable the window */ + _reg_PCMCIA_POR(window) &= ~PCMCIA_POR_PV; + + /* Clear the register fisrt */ + _reg_PCMCIA_POR(window) &= ~(PCMCIA_POR_PSST_MASK + | PCMCIA_POR_PSL_MASK + | PCMCIA_POR_PSHT_MASK); + /* And then set the register */ + _reg_PCMCIA_POR(window) |= code; + + /* Enable the window */ + _reg_PCMCIA_POR(window) |= PCMCIA_POR_PV; + + return 0; +} + +static unsigned short calc_speed(unsigned short *spds, int num, + unsigned short dflt) +{ + unsigned short speed = 0; + int i; + + for (i = 0; i < num; i++) + if (speed < spds[i]) + speed = spds[i]; + if (speed == 0) + speed = dflt; + + return speed; +} + +static void +mx31ads_common_pcmcia_get_timing(struct mx31ads_pcmcia_socket *skt, + struct mx31ads_pcmcia_timing *timing) +{ + timing->io = calc_speed(skt->spd_io, MAX_IO_WIN, PCMCIA_IO_ACCESS); + timing->mem = calc_speed(skt->spd_mem, MAX_WIN, PCMCIA_3V_MEM_ACCESS); + timing->attr = + calc_speed(skt->spd_attr, MAX_WIN, PCMCIA_ATTR_MEM_ACCESS); +} + +static int mx31ads_pcmcia_set_timing(struct mx31ads_pcmcia_socket *skt) +{ + u_int clk_ns; + struct mx31ads_pcmcia_timing timing; + + /* How many nanoseconds */ + clk_ns = (1000 * 1000 * 1000) / clk_get_rate(skt->clk); + pr_debug(KERN_INFO "clk_ns = %d\n", clk_ns); + + mx31ads_common_pcmcia_get_timing(skt, &timing); + pr_debug(KERN_INFO "timing: io %d, mem %d, attr %d\n", timing.io, + timing.mem, timing.attr); + + mx31ads_pcmcia_set_window_timing(timing.io, IO_WINDOW, clk_ns); + mx31ads_pcmcia_set_window_timing(timing.mem, COMMON_MEMORY_WINDOW, + clk_ns); + mx31ads_pcmcia_set_window_timing(timing.attr, ATTRIBUTE_MEMORY_WINDOW, + clk_ns); + + return 0; +} + +static int mx31ads_pcmcia_show_timing(struct mx31ads_pcmcia_socket *skt, + char *buf) +{ + return 0; +} + +static struct pcmcia_low_level mx31ads_pcmcia_ops = { + .owner = THIS_MODULE, + .hw_init = mx31ads_pcmcia_hw_init, + .hw_shutdown = mx31ads_pcmcia_hw_shutdown, + .socket_state = mx31ads_pcmcia_socket_state, + .configure_socket = mx31ads_pcmcia_configure_socket, + + .socket_init = mx31ads_pcmcia_socket_init, + .socket_suspend = mx31ads_pcmcia_socket_suspend, + + .get_timing = mx31ads_pcmcia_default_mecr_timing, + .set_timing = mx31ads_pcmcia_set_timing, + .show_timing = mx31ads_pcmcia_show_timing, +}; + +/* =================================================================================== */ + +LIST_HEAD(mx31ads_pcmcia_sockets); +DECLARE_MUTEX(mx31ads_pcmcia_sockets_lock); + +static DEFINE_SPINLOCK(status_lock); + +struct bittbl { + unsigned int mask; + const char *name; +}; + +static struct bittbl status_bits[] = { + {SS_WRPROT, "SS_WRPROT"}, + {SS_BATDEAD, "SS_BATDEAD"}, + {SS_BATWARN, "SS_BATWARN"}, + {SS_READY, "SS_READY"}, + {SS_DETECT, "SS_DETECT"}, + {SS_POWERON, "SS_POWERON"}, + {SS_STSCHG, "SS_STSCHG"}, + {SS_3VCARD, "SS_3VCARD"}, + {SS_XVCARD, "SS_XVCARD"}, +}; + +static struct bittbl conf_bits[] = { + {SS_PWR_AUTO, "SS_PWR_AUTO"}, + {SS_IOCARD, "SS_IOCARD"}, + {SS_RESET, "SS_RESET"}, + {SS_DMA_MODE, "SS_DMA_MODE"}, + {SS_SPKR_ENA, "SS_SPKR_ENA"}, + {SS_OUTPUT_ENA, "SS_OUTPUT_ENA"}, +}; + +static void +dump_bits(char **p, const char *prefix, unsigned int val, struct bittbl *bits, + int sz) +{ + char *b = *p; + int i; + + b += sprintf(b, "%-9s:", prefix); + for (i = 0; i < sz; i++) + if (val & bits[i].mask) + b += sprintf(b, " %s", bits[i].name); + *b++ = '\n'; + *p = b; +} + +/* + * Implements the /sys/class/pcmcia_socket/??/status file. + * + * Returns: the number of characters added to the buffer + */ +static ssize_t show_status(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mx31ads_pcmcia_socket *skt = + container_of(dev, struct mx31ads_pcmcia_socket, socket.dev); + char *p = buf; + + p += sprintf(p, "slot : %d\n", skt->nr); + + dump_bits(&p, "status", skt->status, + status_bits, ARRAY_SIZE(status_bits)); + dump_bits(&p, "csc_mask", skt->cs_state.csc_mask, + status_bits, ARRAY_SIZE(status_bits)); + dump_bits(&p, "cs_flags", skt->cs_state.flags, + conf_bits, ARRAY_SIZE(conf_bits)); + + p += sprintf(p, "Vcc : %d\n", skt->cs_state.Vcc); + p += sprintf(p, "Vpp : %d\n", skt->cs_state.Vpp); + p += sprintf(p, "IRQ : %d (%d)\n", skt->cs_state.io_irq, skt->irq); + if (skt->ops->show_timing) + p += skt->ops->show_timing(skt, p); + + return p - buf; +} + +static DEVICE_ATTR(status, S_IRUGO, show_status, NULL); + +static void mx31ads_common_check_status(struct mx31ads_pcmcia_socket *skt) +{ + unsigned int events; + + pr_debug(KERN_INFO "entering PCMCIA monitoring thread\n"); + + do { + unsigned int status; + unsigned long flags; + + status = mx31ads_common_pcmcia_skt_state(skt); + + spin_lock_irqsave(&status_lock, flags); + events = (status ^ skt->status) & skt->cs_state.csc_mask; + skt->status = status; + spin_unlock_irqrestore(&status_lock, flags); + + pr_debug(KERN_INFO "events: %s%s%s%s%s%s\n", + events == 0 ? "" : "", + events & SS_DETECT ? "DETECT " : "", + events & SS_READY ? "READY " : "", + events & SS_BATDEAD ? "BATDEAD " : "", + events & SS_BATWARN ? "BATWARN " : "", + events & SS_STSCHG ? "STSCHG " : ""); + + if (events) + pcmcia_parse_events(&skt->socket, events); + } while (events); +} + +/* + * Service routine for socket driver interrupts (requested by the + * low-level PCMCIA init() operation via mx31ads_common_pcmcia_thread()). + * The actual interrupt-servicing work is performed by + * mx31ads_common_pcmcia_thread(), largely because the Card Services event- + * handling code performs scheduling operations which cannot be + * executed from within an interrupt context. + */ +static irqreturn_t mx31ads_common_pcmcia_interrupt(int irq, void *dev) +{ + struct mx31ads_pcmcia_socket *skt = dev; + volatile u32 pscr, pgsr; + + dev_dbg(dev, "servicing IRQ %d\n", irq); + + /* clear interrupt states */ + pscr = _reg_PCMCIA_PSCR; + _reg_PCMCIA_PSCR = pscr; + + pgsr = _reg_PCMCIA_PGSR; + _reg_PCMCIA_PGSR = pgsr; + + mx31ads_common_check_status(skt); + + return IRQ_HANDLED; +} + +/* Let's poll for events in addition to IRQs since IRQ only is unreliable... */ +static void mx31ads_common_pcmcia_poll_event(unsigned long dummy) +{ + struct mx31ads_pcmcia_socket *skt = + (struct mx31ads_pcmcia_socket *)dummy; + pr_debug(KERN_INFO "polling for events\n"); + + mod_timer(&skt->poll_timer, jiffies + PCMCIA_POLL_PERIOD); + + mx31ads_common_check_status(skt); +} + +#define mx31ads_pcmcia_cpufreq_register() +#define mx31ads_pcmcia_cpufreq_unregister() + +static int mx31ads_common_drv_pcmcia_probe(struct platform_device *pdev, + struct pcmcia_low_level *ops) +{ + struct mx31ads_pcmcia_socket *skt; + int vs, value, ret; + struct pccard_io_map map; + + down(&mx31ads_pcmcia_sockets_lock); + + skt = kzalloc(sizeof(struct mx31ads_pcmcia_socket), GFP_KERNEL); + if (!skt) { + ret = -ENOMEM; + goto out; + } + + /* + * Initialise the socket structure. + */ + skt->socket.ops = &mx31ads_common_pcmcia_operations; + skt->socket.owner = ops->owner; + skt->socket.driver_data = skt; + + init_timer(&skt->poll_timer); + skt->poll_timer.function = mx31ads_common_pcmcia_poll_event; + skt->poll_timer.data = (unsigned long)skt; + skt->poll_timer.expires = jiffies + PCMCIA_POLL_PERIOD; + + skt->irq = MX31ADS_PCMCIA_IRQ; + skt->socket.dev.parent = &pdev->dev; + skt->ops = ops; + + skt->clk = clk_get(NULL, "ahb_clk"); + + skt->res_skt.start = _PCMCIA(0); + skt->res_skt.end = _PCMCIA(0) + PCMCIASp - 1; + skt->res_skt.name = MX31ADS_PCMCIA; + skt->res_skt.flags = IORESOURCE_MEM; + + ret = request_resource(&iomem_resource, &skt->res_skt); + if (ret) + goto out_err_1; + + skt->res_io.start = _PCMCIAIO(0); + skt->res_io.end = _PCMCIAIO(0) + PCMCIAIOSp - 1; + skt->res_io.name = "io"; + skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + + ret = request_resource(&skt->res_skt, &skt->res_io); + if (ret) + goto out_err_2; + + skt->res_mem.start = _PCMCIAMem(0); + skt->res_mem.end = _PCMCIAMem(0) + PCMCIAMemSp - 1; + skt->res_mem.name = "memory"; + skt->res_mem.flags = IORESOURCE_MEM; + + ret = request_resource(&skt->res_skt, &skt->res_mem); + if (ret) + goto out_err_3; + + skt->res_attr.start = _PCMCIAAttr(0); + skt->res_attr.end = _PCMCIAAttr(0) + PCMCIAAttrSp - 1; + skt->res_attr.name = "attribute"; + skt->res_attr.flags = IORESOURCE_MEM; + + ret = request_resource(&skt->res_skt, &skt->res_attr); + if (ret) + goto out_err_4; + + skt->virt_io = ioremap(skt->res_io.start, 0x10000); + if (skt->virt_io == NULL) { + ret = -ENOMEM; + goto out_err_5; + } + + if (list_empty(&mx31ads_pcmcia_sockets)) + mx31ads_pcmcia_cpufreq_register(); + + list_add(&skt->node, &mx31ads_pcmcia_sockets); + + /* + * We initialize default socket timing here, because + * we are not guaranteed to see a SetIOMap operation at + * runtime. + */ + ops->set_timing(skt); + + ret = ops->hw_init(skt); + if (ret) + goto out_err_6; + + ret = request_irq(skt->irq, mx31ads_common_pcmcia_interrupt, + IRQF_SHARED | IRQF_DISABLED, "PCMCIA IRQ", skt); + if (ret) + goto out_err_6; + + skt->socket.features = SS_CAP_STATIC_MAP | SS_CAP_PCCARD; + skt->socket.resource_ops = &pccard_static_ops; + skt->socket.irq_mask = 0; + skt->socket.map_size = PCMCIAPrtSp; + skt->socket.pci_irq = skt->irq; + skt->socket.io_offset = (unsigned long)skt->virt_io; + + skt->status = mx31ads_common_pcmcia_skt_state(skt); + skt->pre_stat = 0; + ret = pcmcia_register_socket(&skt->socket); + if (ret) + goto out_err_7; + /* FIXED ME workaround for binding with ide-cs. ide usage io port 0x100~0x107 and 0x10e */ + map.map = 0; + map.flags = MAP_ACTIVE | MAP_16BIT; + map.start = 0; + map.stop = PCMCIAIOSp - 1; + map.speed = 0; + mx31ads_common_pcmcia_set_io_map(&skt->socket, &map); + + vs = _reg_PCMCIA_PIPR & PCMCIA_PIPR_VS; + value = vs & PCMCIA_PIPR_VS_5V ? 50 : 33; + dev_dbg(&pdev->dev, "PCMCIA: Voltage the card supports: %d.%dV\n", + value / 10, value % 10); + + add_timer(&skt->poll_timer); + + ret = device_create_file(&skt->socket.dev, &dev_attr_status); + if (ret < 0) + goto out_err_8; + + platform_set_drvdata(pdev, skt); + ret = 0; + goto out; + + out_err_8: + del_timer_sync(&skt->poll_timer); + pcmcia_unregister_socket(&skt->socket); + + out_err_7: + flush_scheduled_work(); + free_irq(skt->irq, skt); + ops->hw_shutdown(skt); + out_err_6: + list_del(&skt->node); + iounmap(skt->virt_io); + out_err_5: + release_resource(&skt->res_attr); + out_err_4: + release_resource(&skt->res_mem); + out_err_3: + release_resource(&skt->res_io); + out_err_2: + release_resource(&skt->res_skt); + out_err_1: + + kfree(skt); + out: + up(&mx31ads_pcmcia_sockets_lock); + return ret; +} + +static int mx31ads_drv_pcmcia_remove(struct platform_device *pdev) +{ + struct mx31ads_pcmcia_socket *skt = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + down(&mx31ads_pcmcia_sockets_lock); + + del_timer_sync(&skt->poll_timer); + + pcmcia_unregister_socket(&skt->socket); + + flush_scheduled_work(); + + skt->ops->hw_shutdown(skt); + + mx31ads_common_pcmcia_config_skt(skt, &dead_socket); + + list_del(&skt->node); + iounmap(skt->virt_io); + skt->virt_io = NULL; + release_resource(&skt->res_attr); + release_resource(&skt->res_mem); + release_resource(&skt->res_io); + release_resource(&skt->res_skt); + + if (list_empty(&mx31ads_pcmcia_sockets)) + mx31ads_pcmcia_cpufreq_unregister(); + + up(&mx31ads_pcmcia_sockets_lock); + + kfree(skt); + + return 0; +} + +static int mx31ads_drv_pcmcia_probe(struct platform_device *pdev) +{ + if (!machine_is_mx31ads()) + return -ENODEV; + + return mx31ads_common_drv_pcmcia_probe(pdev, &mx31ads_pcmcia_ops); +} + +static int mx31ads_drv_pcmcia_suspend(struct platform_device *pdev, + pm_message_t state) +{ + return pcmcia_socket_dev_suspend(&pdev->dev, state); +} + +static int mx31ads_drv_pcmcia_resume(struct platform_device *pdev) +{ + return pcmcia_socket_dev_resume(&pdev->dev); +} + +/* + * Low level functions + */ +static struct platform_driver mx31ads_pcmcia_driver = { + .driver = { + .name = MX31ADS_PCMCIA, + }, + .probe = mx31ads_drv_pcmcia_probe, + .remove = mx31ads_drv_pcmcia_remove, + .suspend = mx31ads_drv_pcmcia_suspend, + .resume = mx31ads_drv_pcmcia_resume, +}; + +/* mx31ads_pcmcia_init() + * + */ +static int __init mx31ads_pcmcia_init(void) +{ + int ret; + + ret = platform_driver_register(&mx31ads_pcmcia_driver); + if (ret) + return ret; + pr_debug(KERN_INFO "PCMCIA: Initialize i.Mx31 pcmcia socket\n"); + + return ret; +} + +/* mx31ads_pcmcia_exit() + * + */ +static void __exit mx31ads_pcmcia_exit(void) +{ + platform_driver_unregister(&mx31ads_pcmcia_driver); +} + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("i.MX31 PCMCIA Socket Controller"); +MODULE_LICENSE("GPL"); + +module_init(mx31ads_pcmcia_init); +module_exit(mx31ads_pcmcia_exit); diff --git a/drivers/pcmcia/mx31ads-pcmcia.h b/drivers/pcmcia/mx31ads-pcmcia.h new file mode 100644 index 000000000000..5d7d71f421ac --- /dev/null +++ b/drivers/pcmcia/mx31ads-pcmcia.h @@ -0,0 +1,155 @@ +/* + * linux/drivers/pcmcia/mx31ads-pcmcia.h + * + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This file contains definitions for the PCMCIA support code common to + * integrated SOCs like the i.Mx31 microprocessors. + */ +#ifndef _ASM_ARCH_PCMCIA +#define _ASM_ARCH_PCMCIA + +/* include the world */ +#include +#include +#include +#include +#include +#include "cs_internal.h" + +#define MX31ADS_PCMCIA "Mx31ads_pcmcia_socket" + +struct device; +struct pcmcia_low_level; + +/* + * This structure encapsulates per-socket state which we might need to + * use when responding to a Card Services query of some kind. + */ +struct mx31ads_pcmcia_socket { + struct pcmcia_socket socket; + + /* + * Info from low level handler + */ + struct device *dev; + unsigned int nr; + unsigned int irq; + + struct clk *clk; + + /* + * Core PCMCIA state + */ + struct pcmcia_low_level *ops; + + unsigned int status; + unsigned int pre_stat; + socket_state_t cs_state; + + unsigned short spd_io[MAX_IO_WIN]; + unsigned short spd_mem[MAX_WIN]; + unsigned short spd_attr[MAX_WIN]; + + struct resource res_skt; + struct resource res_io; + struct resource res_mem; + struct resource res_attr; + void *virt_io; + + unsigned int irq_state; + + struct timer_list poll_timer; + struct list_head node; +}; + +struct pcmcia_state { + unsigned detect:1, + ready:1, bvd1:1, bvd2:1, wrprot:1, vs_3v:1, vs_Xv:1, poweron:1; +}; + +struct pcmcia_low_level { + struct module *owner; + + /* first socket in system */ + int first; + /* nr of sockets */ + int nr; + + int (*hw_init) (struct mx31ads_pcmcia_socket *); + void (*hw_shutdown) (struct mx31ads_pcmcia_socket *); + + void (*socket_state) (struct mx31ads_pcmcia_socket *, + struct pcmcia_state *); + int (*configure_socket) (struct mx31ads_pcmcia_socket *, + const socket_state_t *); + + /* + * Enable card status IRQs on (re-)initialisation. This can + * be called at initialisation, power management event, or + * pcmcia event. + */ + void (*socket_init) (struct mx31ads_pcmcia_socket *); + + /* + * Disable card status IRQs and PCMCIA bus on suspend. + */ + void (*socket_suspend) (struct mx31ads_pcmcia_socket *); + + /* + * Hardware specific timing routines. + * If provided, the get_timing routine overrides the SOC default. + */ + unsigned int (*get_timing) (struct mx31ads_pcmcia_socket *, + unsigned int, unsigned int); + int (*set_timing) (struct mx31ads_pcmcia_socket *); + int (*show_timing) (struct mx31ads_pcmcia_socket *, char *); + +#ifdef CONFIG_CPU_FREQ + /* + * CPUFREQ support. + */ + int (*frequency_change) (struct mx31ads_pcmcia_socket *, unsigned long, + struct cpufreq_freqs *); +#endif +}; + +struct mx31ads_pcmcia_timing { + unsigned short io; + unsigned short mem; + unsigned short attr; +}; + +typedef struct { + ulong win_size; + int bsize; +} bsize_map_t; + +/* + * The PC Card Standard, Release 7, section 4.13.4, says that twIORD + * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has + * a minimum value of 165ns, as well. Section 4.7.2 (describing + * common and attribute memory write timing) says that twWE has a + * minimum value of 150ns for a 250ns cycle time (for 5V operation; + * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V + * operation, also section 4.7.4). Section 4.7.3 says that taOE + * has a maximum value of 150ns for a 300ns cycle time (for 5V + * operation), or 300ns for a 600ns cycle time (for 3.3V operation). + * + * When configuring memory maps, Card Services appears to adopt the policy + * that a memory access time of "0" means "use the default." The default + * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute + * and memory command width time is 150ns; the PCMCIA 3.3V attribute and + * memory command width time is 300ns. + */ +#define PCMCIA_IO_ACCESS (165) +#define PCMCIA_5V_MEM_ACCESS (150) +#define PCMCIA_3V_MEM_ACCESS (300) +#define PCMCIA_ATTR_MEM_ACCESS (300) + +/* + * The socket driver actually works nicely in interrupt-driven form, + * so the (relatively infrequent) polling is "just to be sure." + */ +#define PCMCIA_POLL_PERIOD (2*HZ) +#endif diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 8e9ba177d817..20d0cd22f606 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -122,6 +122,15 @@ config BATTERY_DA9030 Say Y here to enable support for batteries charger integrated into DA9030 PMIC. +config BATTERY_DA9052 + tristate "Dialog DA9052 Battery" + depends on PMIC_DA9052 + help + Say Y here to enable support for batteries charger integrated into + DA9052 PMIC. + + To compile this driver as a module, choose M here. + config BATTERY_MAX17040 tristate "Maxim MAX17040 Fuel Gauge" depends on I2C @@ -142,4 +151,31 @@ config CHARGER_PCF50633 help Say Y to include support for NXP PCF50633 Main Battery Charger. +config BATTERY_STMP3XXX + tristate "Sigmatel STMP3xxx SoC battery charger driver" + depends on ARCH_STMP3XXX + help + Say Y to enable support for the battery charger state machine + for the Sigmatel STMP3xxx based SoC's. + +config BATTERY_MXS + tristate "MXS SoC battery charger driver" + depends on ARCH_MXS + help + Say Y to enable support for the battery charger state machine + for the Sigmatel MXS based SoC's. + +config MXS_VBUS_CURRENT_DRAW + tristate "MXS SoC USB2.0 VBUS Current Limitation" + depends on ARCH_MXS + help + Say Y to enable 100mA limitation when USB vbus power on system + before enumeration to match USB2.0 requirement. + +config BATTERY_DS2438 + tristate "DS2438 battery driver" + select W1 + select W1_SLAVE_DS2438 + help + Say Y here to enable support for batteries with ds2438 chip. endif # POWER_SUPPLY diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 00050809a6c7..d20c49bd29ff 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_TEST_POWER) += test_power.o obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o obj-$(CONFIG_BATTERY_DS2782) += ds2782_battery.o +obj-$(CONFIG_BATTERY_DA9052) += da9052-battery.o obj-$(CONFIG_BATTERY_PMU) += pmu_battery.o obj-$(CONFIG_BATTERY_OLPC) += olpc_battery.o obj-$(CONFIG_BATTERY_TOSA) += tosa_battery.o @@ -34,3 +35,5 @@ obj-$(CONFIG_BATTERY_DA9030) += da9030_battery.o obj-$(CONFIG_BATTERY_MAX17040) += max17040_battery.o obj-$(CONFIG_BATTERY_Z2) += z2_battery.o obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o +obj-$(CONFIG_BATTERY_MXS) += mxs/ +obj-$(CONFIG_BATTERY_DS2438) += ds2438_battery.o diff --git a/drivers/power/da9052-battery.c b/drivers/power/da9052-battery.c new file mode 100644 index 000000000000..c6a344389c34 --- /dev/null +++ b/drivers/power/da9052-battery.c @@ -0,0 +1,1579 @@ +/* + * da9052-battery.c -- Batttery Driver for Dialog DA9052 + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * Author: Dialog Semiconductor Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define DA9052_BAT_DEVICE_NAME "da9052-bat" + +static const char __initdata banner[] = KERN_INFO "DA9052 BAT, (c) \ +2009 Dialog semiconductor Ltd.\n"; + +static struct da9052_bat_device bat_info; +static struct da9052_bat_status bat_status; +static struct da9052_bat_hysteresis bat_hysteresis; +static struct da9052_bat_event_registration event_status; +static struct monitoring_state monitoring_status; +struct power_supply_info battery_info; + +struct da9052_charger_device charger; + +static u16 bat_target_voltage; +u8 tbat_event_occur; +static int da9052_bat_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val); + +s32 monitoring_thread_pid; +u8 monitoring_thread_state = ACTIVE; +struct completion monitoring_thread_notifier; + +static u16 array_hys_batvoltage[2]; +static u16 bat_volt_arr[3]; +static u8 hys_flag = FALSE; + +static enum power_supply_property da902_bat_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_AVG, + POWER_SUPPLY_PROP_CURRENT_AVG, + POWER_SUPPLY_PROP_CAPACITY, +#if 0 + /* Not supported in 2.6.28 kernel */ + POWER_SUPPLY_PROP_CAPACITY_LEVEL, +#endif + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_MANUFACTURER, +}; + +static int da9052_read(struct da9052 *da9052, u8 reg_address, u8 *reg_data) +{ + struct da9052_ssc_msg msg; + int ret; + + msg.addr = reg_address; + msg.data = 0; + + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret) + goto ssc_comm_err; + da9052_unlock(da9052); + + *reg_data = msg.data; + return 0; +ssc_comm_err: + da9052_unlock(da9052); + return ret; +} + +static int da9052_write(struct da9052 *da9052, u8 reg_address, u8 reg_data) +{ + struct da9052_ssc_msg msg; + int ret; + + msg.addr = reg_address; + msg.data = reg_data; + + da9052_lock(da9052); + ret = da9052->write(da9052, &msg); + if (ret) + goto ssc_comm_err; + da9052_unlock(da9052); + + return 0; +ssc_comm_err: + da9052_unlock(da9052); + return ret; +} + + +static s32 da9052_adc_read_ich(struct da9052 *da9052, u16 *data) +{ + struct da9052_ssc_msg msg; + da9052_lock(da9052); + /* Read charging conversion register */ + msg.addr = DA9052_ICHGAV_REG; + msg.data = 0; + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return DA9052_SSC_FAIL; + } + da9052_unlock(da9052); + + *data = (u16)msg.data; + DA9052_DEBUG( + "In function: %s, ICHGAV_REG value read (1)= 0x%X \n", + __func__, msg.data); + return SUCCESS; +} + +static s32 da9052_adc_read_vddout(struct da9052 *da9052, u16 *data) +{ + u8 reg_data; + s32 ret; + + ret = da9052_read(da9052, DA9052_ADCCONT_REG, ®_data); + if (ret) + return ret; + + if (!(reg_data & DA9052_ADCCONT_AUTOVDDEN)) { + reg_data = (reg_data | DA9052_ADCCONT_AUTOVDDEN); + + ret = da9052_write(da9052, DA9052_INPUTCONT_REG, reg_data); + if (ret) + return ret; + reg_data = 0x0; + + ret = da9052_read(da9052, DA9052_ADCCONT_REG, ®_data); + if (ret) + return ret; + + if (reg_data & DA9052_ADCCONT_ADCMODE) + msleep(1); + else + msleep(10); + + ret = da9052_read(da9052, DA9052_VDDRES_REG, ®_data); + if (ret) + return ret; + + *data = (u16)reg_data; + + ret = da9052_read(da9052, DA9052_ADCCONT_REG, ®_data); + if (ret) + return ret; + + reg_data = reg_data & ~(DA9052_ADCCONT_AUTOVDDEN); + ret = da9052_write(da9052, DA9052_ADCCONT_REG, reg_data); + if (ret) + return ret; + } else { + ret = da9052_read(da9052, DA9052_VDDRES_REG, ®_data); + if (ret) + return ret; + + *data = (u16)reg_data; + } + return 0; +} + + +static s32 da9052_adc_read_tbat(struct da9052 *da9052, u16 *data) +{ + s32 ret; + u8 reg_data; + + ret = da9052_read(da9052, DA9052_TBATRES_REG, ®_data); + if (ret) + return ret; + *data = (u16)reg_data; + + /*printk(KERN_INFO "BAT_LOG:\t Bat Temperature in adc_read_tbat= + %d\n", reg_data);*/ + + DA9052_DEBUG("In function: %s, TBATRES_REG value read (1)= 0x%X \n", + __func__, msg.data); + return SUCCESS; +} + +s32 da9052_adc_read_tjunc(struct da9052 *da9052, u16 *data) +{ + struct da9052_ssc_msg msg; + u16 temp; + + da9052_lock(da9052); + + /* Read TJunction conversion result */ + msg.addr = DA9052_TJUNCRES_REG; + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return DA9052_SSC_FAIL; + } + temp = msg.data; + /* Read calibration for junction temperature */ + msg.addr = DA9052_TOFFSET_REG; + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return DA9052_SSC_FAIL; + } + + da9052_unlock(da9052); + /* Calculate Junction temperature */ + *data = temp - (u16)msg.data; + + DA9052_DEBUG("In function: %s, Calc JUNC TEMP value (1)= 0x%X \n", + __func__, *data); + return 0; +} + +s32 da9052_adc_read_vbat(struct da9052 *da9052, u16 *data) +{ + s32 ret; + + ret = da9052_manual_read(da9052, DA9052_ADC_VBAT); + DA9052_DEBUG("In function: %s, VBAT value read (1)= 0x%X \n", + __func__, temp); + if (ret == -EIO) { + *data = 0; + return ret; + } else { + *data = ret; + return 0; + } + return 0; +} + + +static u16 filter_sample(u16 *buffer) +{ + u8 count; + u16 tempvalue = 0; + u16 ret; + + if (buffer == NULL) + return -EINVAL; + + for (count = 0; count < FILTER_SIZE; count++) + tempvalue = tempvalue + *(buffer + count); + + ret = tempvalue/FILTER_SIZE; + return ret; +} + + +static s32 da9052_bat_get_charger_vddout(struct da9052 *da9052, u16 *buffer) +{ + + u8 count; + u16 filterqueue[FILTER_SIZE]; + + if (bat_status.status != DA9052_CHARGING) + return -EIO; + + /* Measure the charger voltage using ADC function. Number + of read equal to average filter size*/ + for (count = 0; count < FILTER_SIZE; count++) + if (da9052_adc_read_vddout(da9052, &filterqueue[count])) + return -EIO; + + /*Apply average filter */ + filterqueue[0] = filter_sample(filterqueue); + /* Convert the charger voltage in terms of mV */ + bat_info.vddout = vddout_reg_to_mV(filterqueue[0]); + *buffer = bat_info.vddout; + + return SUCCESS; +} + +static s32 da9052_bat_get_battery_temperature(struct da9052 *da9052, + u16 *buffer) +{ + + u8 count; + u16 filterqueue[FILTER_SIZE]; + + /* Measure the battery temperature using ADC function. + Number of read equal to average filter size*/ + + for (count = 0; count < FILTER_SIZE; count++) + if (da9052_adc_read_tbat(da9052, &filterqueue[count])) + return -EIO; + + /* Apply Average filter */ + filterqueue[0] = filter_sample(filterqueue); + + bat_info.bat_temp = filterqueue[0]; + *buffer = bat_info.bat_temp; + + return SUCCESS; +} +static s32 da9052_bat_get_chg_current(struct da9052 *da9052, u16 *buffer) +{ + + if (bat_status.status == DA9052_DISCHARGING_WITHOUT_CHARGER) + return -EIO; + + /* Measure the Charger current using ADC function */ + if (da9052_adc_read_ich(da9052, buffer)) + return -EIO; + + /* Convert the raw value in terms of mA */ + bat_info.chg_current = ichg_reg_to_mA(*buffer); + *buffer = bat_info.chg_current; + + return 0; +} + +static s32 da9052_bat_get_chg_junc_temperature(struct da9052 *da9052, + u16 *buffer) +{ + u8 count; + u16 filterqueue[FILTER_SIZE]; + + if (bat_status.status != DA9052_CHARGING) + return -EIO; + + /* Measure the junciton temperature using ADC function. Number + of read equal to average filter size*/ + for (count = 0; count < FILTER_SIZE; count++) + if (da9052_adc_read_tjunc(da9052, &filterqueue[count])) + return -EIO; + + + /* Apply average filter */ + filterqueue[0] = filter_sample(filterqueue); + + /* Convert the junction temperature raw value in terms of C */ + bat_info.chg_junc_temp = (((1708 * + filterqueue[0])/1000) - 106); + *buffer = bat_info.chg_junc_temp; + + return 0; +} + +s32 da9052_bat_get_battery_voltage(struct da9052 *da9052, u16 *buffer) +{ + + u8 count; + u16 filterqueue[FILTER_SIZE]; + + /* Measure the battery voltage using ADC function. + Number of read equal to average filter size*/ + for (count = 0; count < FILTER_SIZE; count++) + if (da9052_adc_read_vbat(da9052, &filterqueue[count])) + return -EIO; + + /* Apply average filter */ + filterqueue[0] = filter_sample(filterqueue); + + /* Convert battery voltage raw value in terms of mV */ + bat_info.bat_voltage = volt_reg_to_mV(filterqueue[0]); + *buffer = bat_info.bat_voltage; + return 0; +} + +static void da9052_charger_status_update(struct da9052_charger_device + *chg_device) +{ + struct da9052_ssc_msg msg; + u16 current_value = 0; + u8 regvalue = 0; + + DA9052_DEBUG("FUNCTION = %s \n", __func__); + + msg.addr = DA9052_STATUSA_REG; + msg.data = 0; + da9052_lock(chg_device->da9052); + + if (chg_device->da9052->read(chg_device->da9052, &msg)) { + DA9052_DEBUG("%s : failed\n", __func__); + da9052_unlock(chg_device->da9052); + return; + } + regvalue = msg.data; + + msg.addr = DA9052_STATUSB_REG; + msg.data = 0; + if (chg_device->da9052->read(chg_device->da9052, &msg)) { + DA9052_DEBUG("%s : failed\n", __func__); + da9052_unlock(chg_device->da9052); + return; + } + da9052_unlock(chg_device->da9052); + + + if ((regvalue & DA9052_STATUSA_DCINSEL) + && (regvalue & DA9052_STATUSA_DCINDET)) { + + /*printk(KERN_INFO "BAT_LOG:\t BAT DCIN SEL/DET:\n");*/ + if ((msg.data & DA9052_STATUSB_CHGEND) != 0) { + if (da9052_bat_get_chg_current(chg_device->da9052, + ¤t_value)) { + return; + } + + if (current_value >= chg_device->chg_end_current) { + bat_status.status = DA9052_CHARGING; + bat_status.charger_type = DA9052_WALL_CHARGER; + } else { + bat_status.charger_type = DA9052_WALL_CHARGER; + bat_status.status = + DA9052_DISCHARGING_WITH_CHARGER; + } + } + /* if Charging end flag is clered then battery is charging */ + else { + bat_status.status = DA9052_CHARGING; + bat_status.charger_type = DA9052_WALL_CHARGER; + } + } else if ((regvalue & DA9052_STATUSA_VBUSSEL) + && (regvalue & DA9052_STATUSA_VBUSDET)) { + + /*printk(KERN_INFO "BAT_LOG:\t BAT VBUS SEL/DET:\n");*/ + if (regvalue & DA9052_STATUSA_VDATDET) { + bat_status.charger_type = DA9052_USB_CHARGER; + } else { + /* Else it has to be USB Host charger */ + bat_status.charger_type = DA9052_USB_HUB; + } + + + if ((msg.data & DA9052_STATUSB_CHGEND) != 0) { + if (da9052_bat_get_chg_current(chg_device->da9052, + ¤t_value)) { + return; + } + if (current_value >= chg_device->chg_end_current) { + bat_status.status = DA9052_CHARGING; + } else { + bat_status.status = + DA9052_DISCHARGING_WITH_CHARGER; + } + } + /* if Charging end flag is clered then battery is charging */ + else + bat_status.status = DA9052_CHARGING; + + } else if (regvalue & DA9052_STATUSA_DCINDET) { + + /*printk(KERN_INFO "BAT_LOG:\t BAT DCIN DET: \n");*/ + bat_status.charger_type = DA9052_WALL_CHARGER; + bat_status.status = DA9052_DISCHARGING_WITH_CHARGER; + + } else if (regvalue & DA9052_STATUSA_VBUSDET) { + + /*printk(KERN_INFO "BAT_LOG:\t BAT VBUS DET: \n");*/ + if (regvalue & DA9052_STATUSA_VDATDET) { + bat_status.charger_type = DA9052_USB_CHARGER; + bat_status.status = DA9052_DISCHARGING_WITH_CHARGER; + } else { + bat_status.charger_type = DA9052_USB_HUB; + bat_status.status = DA9052_DISCHARGING_WITH_CHARGER; + } + } else { + bat_status.charger_type = DA9052_NOCHARGER; + bat_status.status = DA9052_DISCHARGING_WITHOUT_CHARGER; + } + return; +} + +s32 da9052_get_bat_status(struct da9052_charger_device *chg_device, + struct da9052_bat_status *status_buffer) +{ + struct da9052_ssc_msg msg; + u16 buffer; + + /* If battery is in discharging mode then set charging + mode and return */ + if (bat_status.status == DA9052_DISCHARGING_WITHOUT_CHARGER) + bat_status.charging_mode = DA9052_NONE; + + if (bat_status.status == DA9052_DISCHARGING_WITH_CHARGER) { + bat_status.charging_mode = DA9052_NONE; + } else { + da9052_lock(chg_device->da9052); + msg.addr = DA9052_STATUSB_REG; + /* Read STATUS_B register */ + if (chg_device->da9052->read(chg_device->da9052, &msg)) { + da9052_unlock(chg_device->da9052); + return DA9052_SSC_FAIL; + } + da9052_unlock(chg_device->da9052); + + /* Check if the battery is in Pre-charging mode */ + if (msg.data & DA9052_STATUSB_CHGPRE) { + bat_status.charging_mode = DA9052_PRECHARGING; + bat_status.status = DA9052_CHARGING; + } else { + if (da9052_bat_get_battery_voltage + (chg_device->da9052, &buffer)) { + DA9052_DEBUG("%s : failed\n", __func__); + return -EIO; + } + if ((buffer < (chg_device->bat_target_voltage - + chg_device->charger_voltage_drop)) && + (buffer > chg_device->bat_pdata-> + bat_volt_cutoff)) { + /* Set linear charging status and return */ + bat_status.charging_mode = + DA9052_LINEARCHARGING; + } + /* Else battey is in charge termintation mode. + Set Charge end status and return */ + else if (buffer > (chg_device->bat_target_voltage - + chg_device->charger_voltage_drop)) { + bat_status.charging_mode = DA9052_CHARGEEND; + } + } + } + + status_buffer->cal_capacity = bat_status.cal_capacity; + status_buffer->charging_mode = bat_status.charging_mode; + status_buffer->charger_type = bat_status.charger_type; + status_buffer->status = bat_status.status; + status_buffer->illegalbattery = bat_status.illegalbattery; + + return 0; +} +static s32 da9052_bat_suspend_charging(struct da9052 *da9052) +{ + struct da9052_ssc_msg msg; + + if ((bat_status.status == DA9052_DISCHARGING_WITHOUT_CHARGER) || + (bat_status.status == DA9052_DISCHARGING_WITH_CHARGER)) + return 0; + + msg.addr = DA9052_INPUTCONT_REG; + msg.data = 0; + da9052_lock(da9052); + /* Read Input condition register */ + if (da9052->read(da9052, &msg)) { + da9052_unlock(da9052); + return DA9052_SSC_FAIL; + } + + /* set both Wall charger and USB charger suspend bit */ + msg.data = set_bits(msg.data, DA9052_INPUTCONT_DCINSUSP); + msg.data = set_bits(msg.data, DA9052_INPUTCONT_VBUSSUSP); + + /* Write to Input control register */ + if (da9052->write(da9052, &msg)) { + da9052_unlock(da9052); + DA9052_DEBUG("%s : failed\n", __func__); + return DA9052_SSC_FAIL; + } + da9052_unlock(da9052); + + DA9052_DEBUG("%s : Sucess\n", __func__); + return 0; +} + +static s32 monitor_current(struct da9052_charger_device *chg_device) +{ + static u8 flag1 = FALSE; + u8 count = 0; + u16 current_value = 0; + u16 tempvalue = 0; + u16 avg_value = 0; + + /* Read the charger current value from the + current measurement function */ + if (da9052_bat_get_chg_current(chg_device->da9052, ¤t_value)) { + DA9052_DEBUG("%s : failed\n", __func__); + return -EIO; + } + + /* If montoring function is called first time then set the window */ + if (flag1 == FALSE) { + for (count = 0; count < DA9052_NUMBER_OF_STORE_CURENT_READING; + count++) + bat_info.chg_current_raw[count] = 0; + + tempvalue = (CURRENT_MONITORING_WINDOW * current_value)/100; + chg_device->threshold.ichg_av_thr_min = current_value-tempvalue; + chg_device->threshold.ichg_av_thr_max = current_value+tempvalue; + flag1 = TRUE; + } + + for (count = (DA9052_NUMBER_OF_STORE_CURENT_READING-1); count > 0 ; + count--) + bat_info.chg_current_raw[count] = + bat_info.chg_current_raw[count-1]; + + bat_info.chg_current_raw[0] = current_value; + + /* Form last stored value of the charger current get + the average value */ + for (count = 0; count < DA9052_NUMBER_OF_STORE_CURENT_READING; + count++) { + if (bat_info.chg_current_raw[count] == 0) + break; + avg_value = avg_value + bat_info.chg_current_raw[count]; + } + if (count != 0) + avg_value = avg_value/count; + else + avg_value = current_value; + + /* DA9052_DEBUG("Average_Current = %d\n",avg_value);*/ + /* Window is reallign with 10% of the average measur1e value*/ + tempvalue = (CURRENT_MONITORING_WINDOW * avg_value)/100; + + /* Check measured value with surge window */ + if (((current_value < chg_device->threshold.ichg_av_thr_min) + || (current_value > chg_device->threshold.ichg_av_thr_max))) { + + monitoring_status.current_status = TRUE; + monitoring_status.current_value = current_value; + +#if DA9052_BAT_FILTER_HYS + printk(KERN_CRIT "\nBAT_LOG: Current Monitoring Failed = %d mA\n", + current_value); +#endif + chg_device->threshold.ichg_av_thr_min = avg_value - tempvalue; + chg_device->threshold.ichg_av_thr_max = avg_value + tempvalue; + return -EIO; + } else { + monitoring_status.current_status = FALSE; + monitoring_status.current_value = current_value; + } + + chg_device->threshold.ichg_av_thr_min = avg_value - tempvalue; + chg_device->threshold.ichg_av_thr_max = avg_value + tempvalue; + return 0; + +} + +static s32 monitor_junc_temperature(struct da9052_charger_device *chg_device) +{ + u16 buffer = 0; + u8 ret = 0; + + /* Measure the Junction temperature using BAT internal function */ + ret = da9052_bat_get_chg_junc_temperature(chg_device->da9052, &buffer); + if (ret) + return ret; + + if (buffer > chg_device->threshold.tjunc_thr_limit) { + /* If software monitoring is enabled then suspend charging */ + if (chg_device->sw_temp_cntr == 1) + da9052_bat_suspend_charging(chg_device->da9052); + + monitoring_status.junc_temp_status = TRUE; + monitoring_status.junc_temp_value = buffer; + return -EIO; + } else { + monitoring_status.junc_temp_status = FALSE; + monitoring_status.junc_temp_value = buffer; + } + return 0; +} + + +static s32 monitor_bat_temperature(struct da9052_charger_device *chg_device) +{ + u16 buffer; + u8 ret = 0; + + /* Measure the BAT temperature using BAT internal function */ + ret = da9052_bat_get_battery_temperature(chg_device->da9052, &buffer); + if (ret) + return ret; + + if (buffer > chg_device->threshold.tbat_thr_limit) { + /* If software monitoring is enabled then suspend charging */ + if (chg_device->sw_temp_cntr == 1) + da9052_bat_suspend_charging(chg_device->da9052); + + monitoring_status.bat_temp_status = TRUE; + monitoring_status.bat_temp_value = buffer; + return -EIO; + } else { + monitoring_status.bat_temp_status = FALSE; + monitoring_status.bat_temp_value = buffer; + } + return 0; +} + +u32 interpolated(u32 vbat_lower, u32 vbat_upper, u32 level_lower, + u32 level_upper, u32 bat_voltage) +{ + s32 temp; + /*apply formula y= yk + (x - xk) * (yk+1 -yk)/(xk+1 -xk) */ + temp = ((level_upper - level_lower) * 1000)/(vbat_upper - vbat_lower); + temp = level_lower + (((bat_voltage - vbat_lower) * temp)/1000); + + return temp; +} + + +s32 capture_first_correct_vbat_sample(struct da9052_charger_device *chg_device, +u16 *battery_voltage) +{ + static u8 count; + s32 ret = 0; + u32 temp_data = 0; + + ret = da9052_bat_get_battery_voltage(chg_device->da9052, + &bat_volt_arr[count]); + if (ret) + return ret; + count++; + + if (count < chg_device->bat_pdata->vbat_first_valid_detect_iteration) + return FAILURE; + for (count = 0; count < + (chg_device->bat_pdata->vbat_first_valid_detect_iteration - 1); + count++) { + temp_data = (bat_volt_arr[count] * + (chg_device->bat_pdata->hysteresis_window_size))/100; + bat_hysteresis.upper_limit = bat_volt_arr[count] + temp_data; + bat_hysteresis.lower_limit = bat_volt_arr[count] - temp_data; + + if ((bat_volt_arr[count + 1] < bat_hysteresis.upper_limit) && + (bat_volt_arr[count + 1] > + bat_hysteresis.lower_limit)) { + *battery_voltage = (bat_volt_arr[count] + + bat_volt_arr[count+1]) / 2; + hys_flag = TRUE; + return 0; + } + } + + for (count = 0; count < + (chg_device->bat_pdata->vbat_first_valid_detect_iteration - 1); + count++) + bat_volt_arr[count] = bat_volt_arr[count + 1]; + + return FAILURE; +} + +s32 check_hystersis(struct da9052_charger_device *chg_device, u16 *bat_voltage) +{ + u8 ret = 0; + u32 offset = 0; + + /* Measure battery voltage using BAT internal function*/ + if (hys_flag == FALSE) { + ret = capture_first_correct_vbat_sample + (chg_device, &array_hys_batvoltage[0]); + if (ret) + return ret; + } + + ret = da9052_bat_get_battery_voltage + (chg_device->da9052, &array_hys_batvoltage[1]); + if (ret) + return ret; + *bat_voltage = array_hys_batvoltage[1]; + +#if DA9052_BAT_FILTER_HYS + printk(KERN_CRIT "\nBAT_LOG: Previous Battery Voltage = %d mV\n", + array_hys_batvoltage[0]); + printk(KERN_CRIT "\nBAT_LOG:Battery Voltage Before Filter = %d mV\n", + array_hys_batvoltage[1]); +#endif + /* Check if measured battery voltage value is within the hysteresis + window limit using measured battey votlage value */ + if ((bat_hysteresis.upper_limit < *bat_voltage) || + (bat_hysteresis.lower_limit > *bat_voltage)) { + + bat_hysteresis.index++; + + if (bat_hysteresis.index == + chg_device->bat_pdata->hysteresis_no_of_reading) { + /* Hysteresis Window is set to +- of + HYSTERESIS_WINDOW_SIZE percentage of current VBAT */ + bat_hysteresis.index = 0; + offset = ((*bat_voltage) * + chg_device->bat_pdata->hysteresis_window_size)/ + 100; + bat_hysteresis.upper_limit = (*bat_voltage) + offset; + bat_hysteresis.lower_limit = (*bat_voltage) - offset; + + } else { +#if DA9052_BAT_FILTER_HYS + printk(KERN_CRIT "CheckHystersis: Failed\n"); +#endif + return -EIO; + } + } else { + bat_hysteresis.index = 0; + offset = ((*bat_voltage) * + chg_device->bat_pdata->hysteresis_window_size)/100; + bat_hysteresis.upper_limit = (*bat_voltage) + offset; + bat_hysteresis.lower_limit = (*bat_voltage) - offset; + } + + /* Digital C Filter, formula Yn = k Yn-1 + (1-k) Xn */ + *bat_voltage = ((chg_device->bat_pdata->chg_hysteresis_const * + array_hys_batvoltage[0])/100) + + (((100 - chg_device->bat_pdata->chg_hysteresis_const) * + array_hys_batvoltage[1])/100); + + if ((bat_status.status == DA9052_DISCHARGING_WITHOUT_CHARGER) && + (*bat_voltage > array_hys_batvoltage[0])) { + *bat_voltage = array_hys_batvoltage[0]; + } + + /*DA9052_DEBUG("Voltage Final =%d \n",*bat_voltage);*/ + array_hys_batvoltage[0] = *bat_voltage; + +#if DA9052_BAT_FILTER_HYS + printk(KERN_CRIT "\nBAT_LOG:Battery Voltage After Filter = %d mV\n",\ + *bat_voltage); +#endif + return 0; +} + +u8 select_temperature(u8 temp_index, u16 bat_temperature) +{ + u16 temp_temperature = 0; + temp_temperature = (temperature_lookup_ref[temp_index] + + temperature_lookup_ref[temp_index+1]) / 2; + + if (bat_temperature >= temp_temperature) { + temp_index += 1; + return temp_index; + } else + return temp_index; +} + +s32 da9052_get_bat_level(struct da9052_charger_device *chg_device) +{ + u16 bat_temperature; + u16 bat_voltage; + u32 vbat_lower, vbat_upper, level_upper, level_lower, level; + u8 access_index = 0; + u8 index = 0, ret; + u8 flag = FALSE; + + ret = 0; + vbat_lower = 0; + vbat_upper = 0; + level_upper = 0; + level_lower = 0; + + ret = check_hystersis(chg_device, &bat_voltage); + if (ret) + return ret; + + ret = da9052_bat_get_battery_temperature(chg_device->da9052, + &bat_temperature); + if (ret) + return ret; + + for (index = 0; index < (DA9052_NO_OF_LOOKUP_TABLE-1); index++) { + if (bat_temperature <= temperature_lookup_ref[0]) { + access_index = 0; + break; + } else if (bat_temperature > + temperature_lookup_ref[DA9052_NO_OF_LOOKUP_TABLE]){ + access_index = DA9052_NO_OF_LOOKUP_TABLE - 1; + break; + } else if ((bat_temperature >= temperature_lookup_ref[index]) && + (bat_temperature >= temperature_lookup_ref[index+1])) { + access_index = select_temperature(index, + bat_temperature); + break; + } + } + if (bat_voltage >= vbat_vs_capacity_look_up[access_index][0][0]) { + bat_status.cal_capacity = 100; + return 0; + } + if (bat_voltage <= vbat_vs_capacity_look_up[access_index] + [DA9052_LOOK_UP_TABLE_SIZE-1][0]){ + bat_status.cal_capacity = 0; + return 0; + } + flag = FALSE; + + for (index = 0; index < (DA9052_LOOK_UP_TABLE_SIZE-1); index++) { + if ((bat_voltage <= + vbat_vs_capacity_look_up[access_index][index][0]) && + (bat_voltage >= + vbat_vs_capacity_look_up[access_index][index+1][0])) { + vbat_upper = + vbat_vs_capacity_look_up[access_index][index][0]; + vbat_lower = + vbat_vs_capacity_look_up[access_index][index+1][0]; + level_upper = + vbat_vs_capacity_look_up[access_index][index][1]; + level_lower = + vbat_vs_capacity_look_up[access_index][index+1][1]; + flag = TRUE; + break; + } + } + if (!flag) + return -EIO; + + level = interpolated(vbat_lower, vbat_upper, level_lower, + level_upper, bat_voltage); + bat_status.cal_capacity = level; + DA9052_DEBUG(" TOTAl_BAT_CAPACITY : %d\n", bat_status.cal_capacity); + return 0; +} + +void da9052_bat_vddlow_handler(struct da9052_eh_nb *eh_data, unsigned int event) +{ u16 buffer = 0; + struct da9052_charger_device *charger = + container_of(eh_data, struct da9052_charger_device, + vddlow_eh_data/*da9052_eh_nb*/); + + if (!monitoring_status.vddout_status) { + /* Measure VDDOUT to update the Monitoring status*/ + monitoring_status.vddout_status = TRUE; + if (da9052_bat_get_charger_vddout(charger->da9052, &buffer)) { + DA9052_DEBUG("%s : VDDOUT Measurement Fails.\n", + __func__); + } + monitoring_status.vddout_value = buffer; + } +} + +void da9052_bat_tbat_handler(struct da9052_eh_nb *eh_data, unsigned int event) +{ + if (!tbat_event_occur) { + bat_status.health = POWER_SUPPLY_HEALTH_OVERHEAT; + tbat_event_occur = TRUE; + /* update the TBAt value */ + monitoring_status.bat_temp_status = TRUE; + monitoring_status.bat_temp_value = bat_info.bat_temp; + } +} + +static s32 da9052_bat_register_event(struct da9052_charger_device *chg_device, + u8 event_type) +{ + s32 ret; + switch (event_type) { + case VDD_LOW_EVE: + if (event_status.da9052_event_vddlow == FALSE) { + chg_device->vddlow_eh_data.eve_type = event_type; + chg_device->vddlow_eh_data.call_back = + da9052_bat_vddlow_handler; + DA9052_DEBUG("events = %d\n", event_type); + ret = chg_device->da9052->register_event_notifier + (chg_device->da9052, + &chg_device->vddlow_eh_data); + if (ret) + return -EIO; + event_status.da9052_event_vddlow = TRUE; + } + break; + case TBAT_EVE: + if (event_status.da9052_event_tbat == FALSE) { + chg_device->tbat_eh_data.eve_type = event_type; + chg_device->tbat_eh_data.call_back = + da9052_bat_tbat_handler; + DA9052_DEBUG("events = %d\n", event_type); + ret = chg_device->da9052->register_event_notifier + (chg_device->da9052, &chg_device->tbat_eh_data); + if (ret) + return -EIO; + event_status.da9052_event_tbat = TRUE; + } + break; + default: + return -EIO; + } + return 0; +} + +static s32 da9052_bat_unregister_event(struct da9052_charger_device *chg_device, + u8 event_type) +{ + s32 ret; + switch (event_type) { + case VDD_LOW_EVE: + if (event_status.da9052_event_vddlow) { + ret = + chg_device->da9052->unregister_event_notifier + (chg_device->da9052, + &chg_device->vddlow_eh_data); + if (ret) + return -EIO; + event_status.da9052_event_vddlow = FALSE; + } + break; + case TBAT_EVE: + if (event_status.da9052_event_tbat) { + ret = + chg_device->da9052->unregister_event_notifier + (chg_device->da9052, &chg_device->tbat_eh_data); + if (ret) + return -EIO; + event_status.da9052_event_tbat = FALSE; + } + break; + default: + return -EIO; + } + return 0; +} + +static s32 monitoring_thread(void *data) +{ + u8 mon_count = 0; + s32 ret = 0; +#if DA9052_BAT_PROFILE + u8 mon_times = 0; + u32 jiffies_count = 0; + u32 msec_time_bat_Level = 0; +#endif + + struct da9052_charger_device *chg_device = + (struct da9052_charger_device *)data; + + set_freezable(); + + while (monitoring_thread_state == ACTIVE) { + /* Make this thread friendly to system suspend and resume */ + try_to_freeze(); + + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(chg_device->monitoring_interval); + +#if DA9052_BAT_PROFILE + jiffies_count = jiffies; +#endif + da9052_charger_status_update(chg_device); + /* check if battery is in charging mode */ + if (bat_status.status == DA9052_CHARGING) { + /* If battery is in charging mode then only call + charger current and bat temperature monitoring */ + if (mon_count == 0) { + if (-EIO == monitor_current(chg_device)) { + DA9052_DEBUG("charging Current\ + Monitoring failed, %d\n", mon_count); + } + } + /* call junction temperature monitoring */ + else if (mon_count == 1) { + if (-EIO == + monitor_junc_temperature(chg_device)) + DA9052_DEBUG("Charger Junction\ + Temperature Monitoring failed\n"); + } + } + + if (mon_count == 2) { + ret = da9052_get_bat_level(chg_device); + if (!ret) { + /* BAT Capacity is low then + update the monitoring status*/ + if (bat_status.cal_capacity < + chg_device->bat_pdata->bat_capacity_limit_low) { + monitoring_status.bat_level_status = + TRUE; + monitoring_status.bat_level = + bat_status.cal_capacity; + } else { + monitoring_status.bat_level_status = 0; + monitoring_status.bat_level = + bat_status.cal_capacity; + } + } else + DA9052_DEBUG("Battery Measurement Fails =\ + %d\n", ret); + } + + if (mon_count == 3) + if (-EIO == monitor_bat_temperature(chg_device)) + DA9052_DEBUG("BAT Temperature\ + Monitoring failed\n"); +#if DA9052_BAT_PROFILE + jiffies_count = jiffies - jiffies_count; + + if (mon_count == 2) { + mon_times++; + msec_time_bat_Level = msec_time_bat_Level + + jiffies_to_msecs(jiffies_count); + + if (mon_times == 5) { + mon_times = 0; + msec_time_bat_Level = 0; + } + } +#endif + mon_count++; + if (mon_count == 4) + mon_count = 0; + } + + complete_and_exit(&monitoring_thread_notifier, 0); + + return 0; +} + +#if (DA9052_ILLEGAL_BATTERY_DETECT) +static s32 detect_illegal_battery(struct da9052_charger_device *chg_device) +{ + u16 buffer = 0; + s32 ret = 0; + + /* Measure battery temeperature */ + ret = da9052_bat_get_battery_temperature(chg_device->da9052, &buffer); + if (ret) { + DA9052_DEBUG("%s: Battery temperature measurement failed \n", + __func__); + return ret; + } + + if (buffer > chg_device->bat_pdata->bat_with_no_resistor) + bat_status.illegalbattery = TRUE; + else + bat_status.illegalbattery = FALSE; + + + /* suspend charging of battery if illegal battey is detected */ + if (bat_status.illegalbattery) + da9052_bat_suspend_charging(chg_device->da9052); + + return SUCCESS; +} +#endif + +static int da9052_bat_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + s32 ret = 0; + + struct da9052_charger_device *chg_device = + container_of(psy, struct da9052_charger_device, psy); + + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + if (bat_status.status == DA9052_CHARGING) + val->intval = POWER_SUPPLY_STATUS_CHARGING; + + else if (bat_status.status == + DA9052_DISCHARGING_WITH_CHARGER) + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + + else if (bat_status.status == + DA9052_DISCHARGING_WITHOUT_CHARGER) + val->intval = POWER_SUPPLY_STATUS_DISCHARGING; + + else if (bat_status.status == DA9052_CHARGEEND) + val->intval = POWER_SUPPLY_STATUS_FULL; + + break; + case POWER_SUPPLY_PROP_ONLINE: + if (bat_status.charger_type == DA9052_NOCHARGER) + val->intval = 0; + else + val->intval = 1; + break; + case POWER_SUPPLY_PROP_PRESENT: + if (bat_status.illegalbattery) + val->intval = 0; + else + val->intval = 1; + break; + case POWER_SUPPLY_PROP_HEALTH: + if (bat_status.health != POWER_SUPPLY_HEALTH_OVERHEAT) { + if (bat_status.illegalbattery) + bat_status.health = POWER_SUPPLY_HEALTH_UNKNOWN; + + else if (bat_status.cal_capacity < + chg_device->bat_pdata->bat_capacity_limit_low) + bat_status.health = POWER_SUPPLY_HEALTH_DEAD; + + else + bat_status.health = POWER_SUPPLY_HEALTH_GOOD; + } + val->intval = bat_status.health; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: + val->intval = (bat_target_voltage * 1000); + break; + case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: + val->intval = (chg_device->bat_pdata->bat_volt_cutoff * 1000); + break; + case POWER_SUPPLY_PROP_VOLTAGE_AVG: + val->intval = (bat_info.bat_voltage * 1000); + break; + case POWER_SUPPLY_PROP_CURRENT_AVG: + val->intval = (bat_info.chg_current * 1000); + break; + case POWER_SUPPLY_PROP_CAPACITY: + val->intval = bat_status.cal_capacity; + break; +#if 0 + /* Following properties are not supported in 2.6.28 kernel */ + case POWER_SUPPLY_PROP_CAPACITY_LEVEL: + if (bat_status.illegalbattery) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN; + + else if (bat_status.cal_capacity < + chg_device->bat_pdata->bat_capacity_limit_low) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; + + else if (bat_status.cal_capacity < + chg_device->bat_pdata->bat_capacity_limit_high) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; + + else if (bat_status.cal_capacity == + chg_device->bat_pdata->bat_capacity_full) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_FULL; + + else if (bat_status.cal_capacity > + chg_device->bat_pdata->bat_capacity_limit_high) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_HIGH; + + else + val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; +#endif + break; + case POWER_SUPPLY_PROP_TEMP: + val->intval = bat_temp_reg_to_C(bat_info.bat_temp); + break; + case POWER_SUPPLY_PROP_MANUFACTURER: + val->strval = BAT_MANUFACTURER; + break; + case POWER_SUPPLY_PROP_TECHNOLOGY: + val->intval = BAT_TYPE; + break; + default: + ret = -EINVAL; + break; + } + return 0; +} + +static void da9052_battery_setup_psy(struct da9052_charger_device *chg_device) +{ + battery_info.name = DA9052_BAT_DEVICE_NAME; + battery_info.technology = BAT_TYPE; + battery_info.voltage_max_design = + (chg_device->bat_target_voltage*1000); + battery_info.voltage_min_design = + (chg_device->bat_pdata->bat_volt_cutoff*1000); + battery_info.energy_full_design = + chg_device->bat_pdata->bat_capacity_full; + battery_info.energy_empty_design = + chg_device->bat_pdata->bat_capacity_limit_low; + battery_info.use_for_apm = 1; + + chg_device->psy.name = DA9052_BAT_DEVICE_NAME; + chg_device->psy.use_for_apm = 1; + chg_device->psy.type = POWER_SUPPLY_TYPE_BATTERY; + chg_device->psy.get_property = da9052_bat_get_property; + + chg_device->psy.properties = da902_bat_props; + chg_device->psy.num_properties = ARRAY_SIZE(da902_bat_props); + +}; + +void get_bat_mode(u8 mode_num, char *temp_name) +{ + if (mode_num == DA9052_NONE) + sprintf(temp_name, "NONE"); + else if (mode_num == DA9052_CHARGING) + sprintf(temp_name, "CHARGING"); + else if (mode_num == DA9052_DISCHARGING_WITH_CHARGER) + sprintf(temp_name, "DISCHARGING_WITH_CHARGER"); + else if (mode_num == DA9052_DISCHARGING_WITHOUT_CHARGER) + sprintf(temp_name, "DISCHARGING_WITHOUT_CHARGER"); +} + +void get_charging_mode(u8 mode, char *temp_name) +{ + if (mode == DA9052_NONE) + sprintf(temp_name, "NONE"); + else if (mode == DA9052_PRECHARGING) + sprintf(temp_name, "PRECHARGING"); + else if (mode == DA9052_LINEARCHARGING) + sprintf(temp_name, "LINEARCHARGING"); + else if (mode == DA9052_CHARGEEND) + sprintf(temp_name, "CHARGEEND"); +} + +void get_charger_type(u8 type, char *temp_name) +{ + if (type == DA9052_USB_HUB) + sprintf(temp_name, "USB_HUB"); + else if (type == DA9052_NOCHARGER) + sprintf(temp_name, "NOCHARGER"); + else if (type == DA9052_USB_CHARGER) + sprintf(temp_name, "USB_CHARGER"); + else if (type == DA9052_WALL_CHARGER) + sprintf(temp_name, "WALL_CHARGER"); +} + +#if (DA9052_BAT_STATUS == 1) +static ssize_t da9052_bat_print_status(void *ptr) +{ + s32 result; + struct da9052_bat_status bat_status; + struct da9052_charger_device *chg_device = + (struct da9052_charger_device *)ptr; + struct da9052_ssc_msg msg; + u8 regvalue = 0; + + + set_freezable(); + + while (chg_device->print_bat_status.state == ACTIVE) { + + try_to_freeze(); + + set_current_state(TASK_INTERRUPTIBLE); + schedule_timeout(msecs_to_jiffies((40*1000))); + + #if 1 + + msg.addr = DA9052_STATUSA_REG; + msg.data = 0; + da9052_lock(chg_device->da9052); + if (0 != chg_device->da9052->read(chg_device->da9052, &msg)) { + DA9052_DEBUG("%s : failed\n", __func__); + da9052_unlock(chg_device->da9052); + } else { + da9052_unlock(chg_device->da9052); + + regvalue = msg.data; + + if ((regvalue & DA9052_STATUSA_DCINSEL) + && (regvalue & DA9052_STATUSA_DCINDET)) + printk(KERN_INFO "BAT_LOG:\t BAT DCIN SEL/DET: \n"); + else if ((regvalue & DA9052_STATUSA_VBUSSEL) + && (regvalue & DA9052_STATUSA_VBUSDET)) + printk(KERN_INFO "BAT_LOG:\t BAT VBUS SEL/DET: \n"); + else if (regvalue & DA9052_STATUSA_DCINDET) + printk(KERN_INFO "BAT_LOG:\t BAT DCIN DET: \n"); + else if (regvalue & DA9052_STATUSA_VBUSDET) + printk(KERN_INFO "BAT_LOG:\t BAT VBUS DET: \n"); + } + + #endif + + result = da9052_get_bat_status(chg_device, &bat_status); + if (result) + goto end_monitoring_thread; + + switch (bat_status.illegalbattery) { + case 1: + printk(KERN_INFO "BAT_LOG:\t Illegal Battery Detected \n"); + break; + default: + printk(KERN_INFO "BAT_LOG:\t Valid Battery Detected\n"); + break; + } + + switch (bat_status.charger_type) { + case 1: + printk(KERN_INFO "BAT_LOG:\t Charger_Type= DA9052_NOCHARGER\n"); + break; + case 2: + printk(KERN_INFO "BAT_LOG:\t Charging_Type= DA9052_USB_HUB\n"); + break; + case 3: + printk(KERN_INFO "BAT_LOG:\t Charging_Type= DA9052_USB_CHARGER\n"); + break; + case 4: + printk(KERN_INFO "BAT_LOG:\t Charging_Type= DA9052_WALL_CHARGER \n"); + default: + printk(KERN_INFO "BAT_LOG:\t Charging_Type= INVALID_CHARGER \n"); + break; + } + switch (bat_status.charging_mode) { + case 1: + printk(KERN_INFO "BAT_LOG:\t Charging_Mode = DA9052_NONE \n"); + break; + case 2: + printk(KERN_INFO "BAT_LOG:\t Charging_Mode = DA9052_CHARGING \n"); + break; + case 3: + printk(KERN_INFO "BAT_LOG:\t Charging_Mode =DA9052_DISCHARGING_WITH_CHARGER\n"); + break; + case 4: + printk(KERN_INFO "BAT_LOG:\t Charging_Mode =DA9052_DISCHARGING_WITHOUT_CHARGER \n"); + break; + case 5: + printk(KERN_INFO "BAT_LOG:\t Charging_Mode = DA9052_PRECHARGING\n"); + break; + case 6: + printk(KERN_INFO "BAT_LOG:\t Charging_Mode = DA9052_LINEAR_CHARGING\n"); + break; + case 7: + printk(KERN_INFO "BAT_LOG:\t Charging_Mode = DA9052_CHARGE_END\n"); + break; + default: + printk(KERN_INFO "BAT_LOG:\t Charging_Mode =\ + DA9052_INVALID_MODE \n"); + break; + } + printk(KERN_INFO "BAT_LOG:\t BAT Level Value: %d percent\n", + bat_status.cal_capacity); + printk(KERN_INFO "BAT_LOG:\t BAT Voltage: %d \n", + bat_info.bat_voltage); + printk(KERN_INFO "BAT_LOG:\t BAT Temperture: %d \n", + bat_info.bat_temp); + printk(KERN_INFO "BAT_LOG:\t Junction Temperture: %d \n", + bat_info.chg_junc_temp); + printk(KERN_INFO "BAT_LOG:\t Charging Current: %d \n\n", + bat_info.chg_current); + } +end_monitoring_thread: + complete_and_exit(&chg_device->print_bat_status.notifier, 0); + return SUCCESS; +} +#endif + +static s32 __devinit da9052_bat_probe(struct platform_device *pdev) +{ + struct da9052_bat_platform_data *pdata = pdev->dev.platform_data; + struct da9052_charger_device *chg_device; + u8 reg_data; + int ret; + + chg_device = kzalloc(sizeof(*chg_device), GFP_KERNEL); + if (!chg_device) + return -ENOMEM; + + chg_device->da9052 = dev_get_drvdata(pdev->dev.parent); + + chg_device->bat_pdata = pdata; + + platform_set_drvdata(pdev, chg_device); + + chg_device->monitoring_interval = + msecs_to_jiffies(chg_device->bat_pdata->monitoring_interval); + chg_device->sw_temp_cntr = chg_device->bat_pdata->sw_temp_control_en; + chg_device->usb_charger_current = 0; + + ret = da9052_read(chg_device->da9052, DA9052_CHGCONT_REG, ®_data); + if (ret) + goto err_charger_init; + chg_device->charger_voltage_drop = bat_drop_reg_to_mV(reg_data && + DA9052_CHGCONT_TCTR); + chg_device->bat_target_voltage = + bat_reg_to_mV(reg_data && DA9052_CHGCONT_VCHGBAT); + bat_target_voltage = chg_device->bat_target_voltage; + + reg_data = 0; + ret = da9052_read(chg_device->da9052, DA9052_ICHGEND_REG, ®_data); + if (ret) + goto err_charger_init; + + chg_device->chg_end_current = ichg_reg_to_mA(reg_data); + + chg_device->threshold.tbat_thr_limit = + chg_device->bat_pdata->sw_bat_temp_threshold; + chg_device->threshold.tjunc_thr_limit = + chg_device->bat_pdata->sw_junc_temp_threshold; + + sprintf(bat_info.manufacture, BAT_MANUFACTURER); + bat_status.illegalbattery = 0; + + bat_hysteresis.upper_limit = 0; + bat_hysteresis.lower_limit = 0; + bat_hysteresis.hys_flag = 0; + + bat_status.charger_type = DA9052_NOCHARGER; + bat_status.status = DA9052_CHARGING; + bat_status.charging_mode = DA9052_NONE; + tbat_event_occur = 0; +#if (DA9052_ILLEGAL_BATTERY_DETECT) + detect_illegal_battery(chg_device); +#endif + da9052_charger_status_update(chg_device); + + da9052_battery_setup_psy(chg_device); + + ret = da9052_bat_register_event(chg_device, VDD_LOW_EVE); + if (ret) + goto err_charger_init; + da9052_bat_register_event(chg_device, TBAT_EVE); + if (ret) + goto err_charger_init; + + ret = power_supply_register(&pdev->dev, &chg_device->psy); + if (ret) + goto err_charger_init; + + monitoring_thread_state = ACTIVE; + init_completion(&monitoring_thread_notifier); + monitoring_thread_pid = kernel_thread(monitoring_thread, chg_device, + CLONE_KERNEL | SIGCHLD); + if (monitoring_thread_pid > 0) { + printk(KERN_ERR "Monitoring thread is successfully started,\ + pid = %d\n", monitoring_thread_pid); + } +#if (DA9052_BAT_STATUS == 1) + init_completion(&chg_device->print_bat_status.notifier); + chg_device->print_bat_status.state = ACTIVE; + chg_device->print_bat_status.pid = + kernel_thread(da9052_bat_print_status, chg_device, + CLONE_KERNEL | SIGCHLD); +#endif + + printk(KERN_INFO "Exiting DA9052 battery probe \n"); + return 0; + +err_charger_init: + platform_set_drvdata(pdev, NULL); + kfree(chg_device); + return ret; +} +static int __devexit da9052_bat_remove(struct platform_device *dev) +{ + struct da9052_charger_device *chg_device = platform_get_drvdata(dev); + s32 ret; + + monitoring_thread_state = INACTIVE; + wait_for_completion(&monitoring_thread_notifier); + +#if (DA9052_BAT_STATUS == 1) + /* stop and delete monitoring timer */ + chg_device->print_bat_status.state = INACTIVE; + wait_for_completion(&chg_device->print_bat_status.notifier); +#endif + + /* unregister the events.*/ + ret = da9052_bat_unregister_event(chg_device, VDD_LOW_EVE); + ret = da9052_bat_unregister_event(chg_device, TBAT_EVE); + return 0; +} + +static struct platform_driver da9052_bat_driver = { + .probe = da9052_bat_probe, + .remove = __devexit_p(da9052_bat_remove), + .driver = { + .name = DA9052_BAT_DEVICE_NAME, + .owner = THIS_MODULE, + }, +}; + +static s32 __init da9052_bat_init(void) +{ + printk(banner); + return platform_driver_register(&da9052_bat_driver); +} +module_init(da9052_bat_init); + +static void __exit da9052_bat_exit(void) +{ + printk("DA9052: Unregistering BAT device.\n"); + platform_driver_unregister(&da9052_bat_driver); +} +module_exit(da9052_bat_exit); + +MODULE_AUTHOR("Dialog Semiconductor Ltd"); +MODULE_DESCRIPTION("DA9052 BAT Device Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/ds2438_battery.c b/drivers/power/ds2438_battery.c new file mode 100644 index 000000000000..03fa9b29cd1f --- /dev/null +++ b/drivers/power/ds2438_battery.c @@ -0,0 +1,567 @@ +/* +* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. +*/ + +/* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. + +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. + +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../w1/w1.h" +#include "../w1/slaves/w1_ds2438.h" + +struct ds2438_device_info { + struct device *dev; + /* DS2438 data, valid after calling ds2438_battery_read_status() */ + unsigned long update_time; /* jiffies when data read */ + char raw[DS2438_PAGE_SIZE]; /* raw DS2438 data */ + int voltage_uV; + int current_uA; + int accum_current_uAh; + int temp_C; + int charge_status; + u8 init:1; + u8 setup:1; + u8 calibrate:1; + u8 input_src:1; + u8 ee_flg:1; + u8 resv_bit:3; + u8 threshold:8; + u16 resv_bytes; + u32 senser; + + struct power_supply bat; + struct device *w1_dev; + struct ds2438_ops ops; + struct workqueue_struct *monitor_wqueue; + struct delayed_work monitor_work; +}; + +#define DS2438_SENSER 25 +#define to_ds2438_device_info(x) container_of((x), struct ds2438_device_info, \ + bat); + + +static enum power_supply_property ds2438_battery_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_CHARGE_NOW, +}; + +static char ds2438_sensers_title[] = "DS2438 senserin thousands of resister:"; +static unsigned int cache_time = 1000; +module_param(cache_time, uint, 0644); +MODULE_PARM_DESC(cache_time, "cache time in milliseconds"); + +static ssize_t ds2438_show_input(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + return sprintf(buf, "%s\n", di->input_src ? "1:VDD" : "0:VAD"); +} + +static ssize_t ds2438_show_senser(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len; + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + len = sprintf(buf, "%s\n", ds2438_sensers_title); + len += sprintf(buf + len, "%d\n", di->senser); + return len; +} + +static ssize_t ds2438_show_ee(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + return sprintf(buf, "%d\n", di->ee_flg); +} + +static ssize_t ds2438_show_threshold(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + return sprintf(buf, "%d\n", di->threshold); +} + +static ssize_t ds2438_set_input(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + di->input_src = !!simple_strtoul(buf, NULL, 0); + return count; +} + +static ssize_t ds2438_set_senser(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + u32 resister; + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + resister = simple_strtoul(buf, NULL, 0); + if (resister) + di->senser = resister; + return count; +} + +static ssize_t ds2438_set_ee(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + di->ee_flg = !!simple_strtoul(buf, NULL, 0); + di->setup = 1; + return count; +} + +static ssize_t ds2438_set_threshold(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int threshold; + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + threshold = simple_strtoul(buf, NULL, 0); + if (threshold < 256) { + di->threshold = threshold; + di->setup = 1; + return count; + } + return -EINVAL; +} + +static ssize_t ds2438_set_calibrate(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct power_supply *psy = dev_get_drvdata(dev); + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + di->calibrate = !!simple_strtoul(buf, NULL, 0); + return count; +} + +static struct device_attribute ds2438_dev_attr[] = { + __ATTR(input_src, 0664, ds2438_show_input, ds2438_set_input), + __ATTR(senser, 0664, ds2438_show_senser, ds2438_set_senser), + __ATTR(ee_flg, 0664, ds2438_show_ee, ds2438_set_ee), + __ATTR(threshold, 0664, ds2438_show_threshold, ds2438_set_threshold), + __ATTR(calibrate, 0220, NULL, ds2438_set_calibrate), +}; + +static void ds2438_setup(struct ds2438_device_info *di) +{ + di->ops.load_sram(di->w1_dev, PAGE0_CONTROL); + di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw); + if (di->init && di->setup) { + if (di->ee_flg) + di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_EE; + else + di->raw[PAGE0_STAT_CTRL] &= ~DS2438_CTRL_EE; + if (di->input_src) + di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_AD; + else + di->raw[PAGE0_STAT_CTRL] &= ~DS2438_CTRL_AD; + di->raw[PAGE0_THRESHOLD] = di->threshold; + } else { + di->ee_flg = !!(di->raw[PAGE0_STAT_CTRL] & DS2438_CTRL_EE); + di->input_src = !!(di->raw[PAGE0_STAT_CTRL] & DS2438_CTRL_AD); + di->threshold = di->raw[PAGE0_THRESHOLD]; + di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_IAD | DS2438_CTRL_CA; + } + di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL); + if (!di->init) { + di->calibrate = 1; + di->init = 1; + } + di->setup = 0; +} + +static void ds2438_calibrate(struct ds2438_device_info *di) +{ + int current_raw; + /* disable ICA */ + di->ops.load_sram(di->w1_dev, PAGE0_CONTROL); + di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->raw[PAGE0_STAT_CTRL] &= ~DS2438_CTRL_IAD; + di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL); + + /* Zero offset */ + di->ops.load_sram(di->w1_dev, PAGE1_ETM); + di->ops.read_page(di->w1_dev, PAGE1_ETM, di->raw); + ds2438_writew(di->raw + PAGE1_OFFSET_LSB, 0); + di->ops.drain_sram(di->w1_dev, PAGE1_ETM_BYTE0); + + /* enable ICA & read current */ + di->ops.load_sram(di->w1_dev, PAGE0_CONTROL); + di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_IAD; + di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL); + /*wait current convert about 36HZ */ + mdelay(30); + /* disable ICA */ + di->ops.load_sram(di->w1_dev, PAGE0_CONTROL); + di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->raw[PAGE0_STAT_CTRL] &= ~DS2438_CTRL_IAD; + di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL); + /* read current value */ + current_raw = ds2438_readw(di->raw + PAGE0_CURRENT_LSB); + /* write offset by current value */ + di->ops.load_sram(di->w1_dev, PAGE1_ETM); + di->ops.read_page(di->w1_dev, PAGE1_ETM, di->raw); + ds2438_writew(di->raw + PAGE1_OFFSET_LSB, current_raw << 8); + di->ops.write_page(di->w1_dev, PAGE1_ETM, di->raw); + di->ops.drain_sram(di->w1_dev, PAGE1_ETM); + + /*enable ICA again */ + di->ops.load_sram(di->w1_dev, PAGE0_CONTROL); + di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->raw[PAGE0_STAT_CTRL] |= DS2438_CTRL_IAD; + di->ops.write_page(di->w1_dev, PAGE0_CONTROL, di->raw); + di->ops.drain_sram(di->w1_dev, PAGE0_CONTROL); + di->calibrate = 0; +} + +/* + * power supply temperture is in tenths of degree. + */ +static inline int ds2438_get_temp(u16 raw) +{ + int degree, s; + s = !!(raw & 0x8000); + + if (s) + raw = ((~raw & 0x7FFF) + 1); + degree = ((raw >> 8) * 10) + (((raw & 0xFF) * 5) + 63) / 128; + return s ? -degree : degree; +} + +/* + * power supply current is in uA. + */ +static inline int ds2438_get_current(u32 senser, u16 raw) +{ + int s, current_uA; + s = !!(raw & 0xFC00); + /* (x * 1000 * 1000)uA / (4096 * (Rsens / 1000)) */ + raw &= 0x3FF; + current_uA = raw * 125 * 125 * 125; + current_uA /= (senser << 3); + return s ? -current_uA : current_uA; +} + +/* + * power supply current is in uAh. + */ +static inline int ds2438_get_ica(u32 senser, u8 raw) +{ + int charge_uAh; + /* (x * 1000 * 1000)uA / (2048 * (Rsens / 1000)) */ + charge_uAh = (raw * 125 * 125 * 125) >> 4; + charge_uAh /= (senser << 4); + return charge_uAh; +} + +static int ds2438_battery_update_page1(struct ds2438_device_info *di) +{ + int ica_raw; + di->ops.load_sram(di->w1_dev, PAGE1_ETM); + di->ops.read_page(di->w1_dev, PAGE1_ETM, di->raw); + ica_raw = di->raw[PAGE1_ICA]; + di->accum_current_uAh = ds2438_get_ica(di->senser, ica_raw); + return 0; +} + +static int ds2438_battery_read_status(struct ds2438_device_info *di) +{ + u8 status; + int temp_raw, voltage_raw, current_raw; + + if (!(di->init) || di->setup) + ds2438_setup(di); + + if (di->calibrate) + ds2438_calibrate(di); + + if (di->update_time && time_before(jiffies, di->update_time + + msecs_to_jiffies(cache_time))) + return 0; + + di->ops.load_sram(di->w1_dev, PAGE0_CONTROL); + di->ops.read_page(di->w1_dev, PAGE0_CONTROL, di->raw); + status = di->raw[PAGE0_STAT_CTRL]; + temp_raw = ds2438_readw(di->raw + PAGE0_TEMP_LSB); + voltage_raw = ds2438_readw(di->raw + PAGE0_VOLTAGE_LSB); + current_raw = ds2438_readw(di->raw + PAGE0_CURRENT_LSB); + di->temp_C = ds2438_get_temp(temp_raw); + di->voltage_uV = voltage_raw * 10000; + di->current_uA = ds2438_get_current(di->senser, current_raw); + + ds2438_battery_update_page1(di); + + if (!(status & DS2438_STAT_TB)) + di->ops.command(di->w1_dev, DS2438_CONVERT_TEMP, 0); + if (!(status & DS2438_STAT_ADB)) + di->ops.command(di->w1_dev, DS2438_CONVERT_VOLT, 0); + di->update_time = jiffies; + return 0; +} + +static void ds2438_battery_update_status(struct ds2438_device_info *di) +{ + int old_charge_status = di->charge_status; + + ds2438_battery_read_status(di); + + if (di->charge_status != old_charge_status) + power_supply_changed(&di->bat); +} + +static void ds2438_battery_work(struct work_struct *work) +{ + struct ds2438_device_info *di = container_of(work, + struct ds2438_device_info, + monitor_work.work); + const int interval = HZ * 60; + + dev_dbg(di->w1_dev, "%s\n", __func__); + + ds2438_battery_update_status(di); + queue_delayed_work(di->monitor_wqueue, &di->monitor_work, interval); +} + +static void ds2438_battery_external_power_changed(struct power_supply *psy) +{ + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + dev_dbg(di->w1_dev, "%s\n", __func__); + + cancel_delayed_work(&di->monitor_work); + queue_delayed_work(di->monitor_wqueue, &di->monitor_work, HZ / 10); +} + +static int ds2438_battery_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct ds2438_device_info *di = to_ds2438_device_info(psy); + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + val->intval = di->charge_status; + return 0; + default: + break; + } + + ds2438_battery_read_status(di); + + switch (psp) { + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + val->intval = di->voltage_uV; + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + val->intval = di->current_uA; + break; + case POWER_SUPPLY_PROP_TEMP: + val->intval = di->temp_C; + break; + case POWER_SUPPLY_PROP_CHARGE_NOW: + val->intval = di->accum_current_uAh; + break; + default: + return -EINVAL; + } + + return 0; +} + +static inline void ds2438_defaut_ops(struct ds2438_ops *ops) +{ + ops->read_page = w1_ds2438_read_page; + ops->write_page = w1_ds2438_write_page; + ops->drain_sram = w1_ds2438_drain_sram; + ops->load_sram = w1_ds2438_load_sram; + ops->command = w1_ds2438_command; +} + + +static int ds2438_battery_probe(struct platform_device *pdev) +{ + int i, retval = 0; + struct ds2438_device_info *di; + + di = kzalloc(sizeof(*di), GFP_KERNEL); + if (!di) { + retval = -ENOMEM; + goto di_alloc_failed; + } + + di->dev = &pdev->dev; + di->w1_dev = pdev->dev.parent; + di->bat.name = dev_name(&pdev->dev); + di->bat.type = POWER_SUPPLY_TYPE_BATTERY; + di->bat.properties = ds2438_battery_props; + di->bat.num_properties = ARRAY_SIZE(ds2438_battery_props); + di->bat.get_property = ds2438_battery_get_property; + di->bat.external_power_changed = ds2438_battery_external_power_changed; + ds2438_defaut_ops(&di->ops); + di->senser = DS2438_SENSER; + di->charge_status = POWER_SUPPLY_STATUS_UNKNOWN; + + retval = power_supply_register(&pdev->dev, &di->bat); + if (retval) { + dev_err(&pdev->dev, "failed to register battery\n"); + goto batt_failed; + } + + for (i = 0; i < ARRAY_SIZE(ds2438_dev_attr); i++) { + if (device_create_file(di->bat.dev, ds2438_dev_attr + i)) { + printk(KERN_ERR "Customize attribute file fail!\n"); + break; + } + } + + if (i != ARRAY_SIZE(ds2438_dev_attr)) { + for (; i >= 0; i++) + device_remove_file(di->bat.dev, ds2438_dev_attr + i); + goto workqueue_failed; + } + INIT_DELAYED_WORK(&di->monitor_work, ds2438_battery_work); + di->monitor_wqueue = create_singlethread_workqueue( + dev_name(&pdev->dev)); + if (!di->monitor_wqueue) { + retval = -ESRCH; + goto workqueue_failed; + } + + platform_set_drvdata(pdev, di); + queue_delayed_work(di->monitor_wqueue, &di->monitor_work, HZ / 2); + + goto success; + +workqueue_failed: + power_supply_unregister(&di->bat); +batt_failed: + kfree(di); +di_alloc_failed: +success: + return retval; +} + +static int ds2438_battery_remove(struct platform_device *pdev) +{ + struct ds2438_device_info *di = platform_get_drvdata(pdev); + + cancel_rearming_delayed_workqueue(di->monitor_wqueue, + &di->monitor_work); + destroy_workqueue(di->monitor_wqueue); + power_supply_unregister(&di->bat); + return 0; +} + +#ifdef CONFIG_PM +static int ds2438_battery_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct ds2438_device_info *di = platform_get_drvdata(pdev); + + di->charge_status = POWER_SUPPLY_STATUS_UNKNOWN; + + return 0; +} + +static int ds2438_battery_resume(struct platform_device *pdev) +{ + struct ds2438_device_info *di = platform_get_drvdata(pdev); + + di->charge_status = POWER_SUPPLY_STATUS_UNKNOWN; + power_supply_changed(&di->bat); + + cancel_delayed_work(&di->monitor_work); + queue_delayed_work(di->monitor_wqueue, &di->monitor_work, HZ); + + return 0; +} + +#else + +#define ds2438_battery_suspend NULL +#define ds2438_battery_resume NULL + +#endif /* CONFIG_PM */ +static struct platform_driver ds2438_battery_driver = { + .driver = { + .name = DS2438_DEV_NAME, + }, + .probe = ds2438_battery_probe, + .remove = ds2438_battery_remove, + .suspend = ds2438_battery_suspend, + .resume = ds2438_battery_resume, +}; + +static int __init ds2438_battery_init(void) +{ + pr_info("ds2438 battery driver\n"); + return platform_driver_register(&ds2438_battery_driver); +} + +static void __exit ds2438_battery_exit(void) +{ + platform_driver_unregister(&ds2438_battery_driver); +} + +module_init(ds2438_battery_init); +module_exit(ds2438_battery_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductors Inc"); +MODULE_DESCRIPTION("DS2438 battery driver."); diff --git a/drivers/power/mxs/Makefile b/drivers/power/mxs/Makefile new file mode 100644 index 000000000000..c7675a9ec52b --- /dev/null +++ b/drivers/power/mxs/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the MXS battery charger driver +# + +obj-$(CONFIG_BATTERY_MXS) += mxs-battery.o + +mxs-battery-objs := ddi_bc_api.o ddi_bc_hw.o ddi_bc_init.o \ + ddi_bc_ramp.o ddi_bc_sm.o ddi_power_battery.o linux.o fiq.o + diff --git a/drivers/power/mxs/ddi_bc_api.c b/drivers/power/mxs/ddi_bc_api.c new file mode 100644 index 000000000000..26d064bff9a2 --- /dev/null +++ b/drivers/power/mxs/ddi_bc_api.c @@ -0,0 +1,559 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/* Includes */ + + +#include +#include "ddi_bc_internal.h" + + +/* Variables */ + + +/* This structure holds the current Battery Charger configuration. */ + +ddi_bc_Cfg_t g_ddi_bc_Configuration; + +extern uint32_t g_ddi_bc_u32StateTimer; +extern ddi_bc_BrokenReason_t ddi_bc_gBrokenReason; +extern bool bRestartChargeCycle; + + +/* Code */ + + + + +/* brief Report the Battery Charger configuration. */ + +/* fntype Function */ + +/* This function reports the Battery Charger configuration. */ + +/* Note that, if the Battery Charger has not yet been initialized, the data */ +/* returned by this function is unknown. */ + +/* param[in,out] pCfg A pointer to a structure that will receive the data. */ + + +void ddi_bc_QueryCfg(ddi_bc_Cfg_t *pCfg) +{ + + /* -------------------------------------------------------------------------- */ + /* Return the current configuration. */ + /* -------------------------------------------------------------------------- */ + + *pCfg = g_ddi_bc_Configuration; + +} + + + +/* brief Shut down the Battery Charger. */ + +/* fntype Function */ + +/* This function immediately shuts down the Battery Charger hardware and */ +/* returns the state machine to the Uninitialized state. Use this function to */ +/* safely mummify the battery charger before retiring it from memory. */ + + +void ddi_bc_ShutDown() +{ + + /* -------------------------------------------------------------------------- */ + /* Reset the current ramp. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampReset(); + + /* -------------------------------------------------------------------------- */ + /* Move to the Uninitialized state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_UNINITIALIZED; + +} + + + +/* brief Advances the state machine. */ + +/* fntype Function */ + +/* This function advances the state machine. */ + +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_BROKEN If the battery violated a time-out */ +/* and has been declared broken. */ + + +ddi_bc_Status_t ddi_bc_StateMachine() +{ + int ret, state; + + /* -------------------------------------------------------------------------- */ + /* Check if we've been initialized yet. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) { + return DDI_BC_STATUS_NOT_INITIALIZED; + } + /* -------------------------------------------------------------------------- */ + /* Execute the function for the current state. */ + /* -------------------------------------------------------------------------- */ + + state = g_ddi_bc_State; + ret = (stateFunctionTable[g_ddi_bc_State] ()); + if (state != g_ddi_bc_State) + pr_debug("Charger: transit from state %d to %d\n", + state, g_ddi_bc_State); + return ret; + +} + + + +/* brief Get the Battery Charger's current state. */ + +/* fntype Function */ + +/* This function returns the current state. */ + +/* retval The current state. */ + + +ddi_bc_State_t ddi_bc_GetState() +{ + /* -------------------------------------------------------------------------- */ + /* Return the current state. */ + /* -------------------------------------------------------------------------- */ + + return g_ddi_bc_State; + +} + + + +/* brief Disable the Battery Charger. */ + +/* fntype Function */ + +/* This function forces the Battery Charger into the Disabled state. */ + +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ + + +ddi_bc_Status_t ddi_bc_SetDisable() +{ + + /* -------------------------------------------------------------------------- */ + /* Check if we've been initialized yet. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) { + return DDI_BC_STATUS_NOT_INITIALIZED; + } + /* -------------------------------------------------------------------------- */ + /* Check if we've been initialized yet. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State == DDI_BC_STATE_BROKEN) { + return DDI_BC_STATUS_BROKEN; + } + /* -------------------------------------------------------------------------- */ + /* Reset the current ramp. This will jam the current to zero and power off */ + /* the charging hardware. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampReset(); + + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + + /* -------------------------------------------------------------------------- */ + /* Move to the Disabled state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_DISABLED; + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + + +/* brief Enable the Battery Charger. */ + +/* fntype Function */ + +/* If the Battery Charger is in the Disabled state, this function moves it to */ +/* the Waiting to Charge state. */ + +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_NOT_DISABLED If the Battery Charger is not */ +/* disabled. */ + + +ddi_bc_Status_t ddi_bc_SetEnable() +{ + + /* -------------------------------------------------------------------------- */ + /* Check if we've been initialized yet. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) { + return DDI_BC_STATUS_NOT_INITIALIZED; + } + /* -------------------------------------------------------------------------- */ + /* If we're not in the Disabled state, this is pointless. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State != DDI_BC_STATE_DISABLED) { + return DDI_BC_STATUS_NOT_DISABLED; + } + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + /* -------------------------------------------------------------------------- */ + /* Move to the Waiting to Charge state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_WAITING_TO_CHARGE; + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + + +/* brief Declare the battery to be broken. */ + +/* fntype Function */ + +/* This function forces the Battery Charger into the Broken state. */ + +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ + + +ddi_bc_Status_t ddi_bc_SetBroken() +{ + + /* -------------------------------------------------------------------------- */ + /* Check if we've been initialized yet. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) { + return DDI_BC_STATUS_NOT_INITIALIZED; + } + /* -------------------------------------------------------------------------- */ + /* Reset the current ramp. This will jam the current to zero and power off */ + /* the charging hardware. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampReset(); + + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + + /* -------------------------------------------------------------------------- */ + /* Move to the Broken state. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT; + + g_ddi_bc_State = DDI_BC_STATE_BROKEN; + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + + +/* brief Declare the battery to be fixed. */ + +/* fntype Function */ + +/* If the Battery Charger is in the Broken state, this function moves it to */ +/* the Disabled state. */ + +/* retval DDI_BC_STATUS_SUCCESS If all goes well */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* retval DDI_BC_STATUS_NOT_BROKEN If the Battery Charger is not broken. */ + + +ddi_bc_Status_t ddi_bc_SetFixed() +{ + + /* -------------------------------------------------------------------------- */ + /* Check if we've been initialized yet. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) { + return DDI_BC_STATUS_NOT_INITIALIZED; + } + /* -------------------------------------------------------------------------- */ + /* If we're not in the Broken state, this is pointless. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State != DDI_BC_STATE_BROKEN) { + return DDI_BC_STATUS_NOT_BROKEN; + } + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + + /* -------------------------------------------------------------------------- */ + /* Unitialize the Broken Reason */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_gBrokenReason = DDI_BC_BROKEN_UNINITIALIZED; + + /* -------------------------------------------------------------------------- */ + /* Move to the Disabled state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_DISABLED; + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + + +/* brief Set the current limit. */ + +/* fntype Function */ + +/* This function applies a limit to the current that the Battery Charger can */ +/* draw. */ + +/* param[in] u16Limit The maximum current the Battery Charger can draw */ +/* (in mA). */ + +/* retval The expressible version of the limit. */ + + +uint16_t ddi_bc_SetCurrentLimit(uint16_t u16Limit) +{ + + /* -------------------------------------------------------------------------- */ + /* Set the limit and return what is actually expressible. */ + /* -------------------------------------------------------------------------- */ + + return ddi_bc_RampSetLimit(u16Limit); + +} + + + +/* brief Report the current limit. */ + +/* fntype Function */ + +/* This function reports the limit to the current that the Battery Charger can */ +/* draw. */ + +/* retval The current limit. */ + + +uint16_t ddi_bc_GetCurrentLimit(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Set the limit and return what is actually expressible. */ + /* -------------------------------------------------------------------------- */ + + return ddi_bc_RampGetLimit(); + +} + + + +/* brief Set the battery charger state machine period. */ + +/* fntype Function */ + +/* This function sets a new state machine period. The Period and Slope should */ +/* be coordinated to achieve the minimal ramp step current which will minimize */ +/* transients on the system. */ + +/* param[in] u32StateMachinePeriod (in milliseconds) */ +/* param[in] u16CurrentRampSlope (in mA/s) */ + +/* retval SUCCESS If all goes well */ +/* retval ERROR_DDI_BCM_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ + + +ddi_bc_Status_t ddi_bc_SetNewPeriodAndSlope(uint32_t u32StateMachinePeriod, + uint16_t u16CurrentRampSlope) +{ + /* -------------------------------------------------------------------------- */ + /* Check if we've been initialized yet. */ + /* -------------------------------------------------------------------------- */ + bool bDisableRequired; + + if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) { + return DDI_BC_STATUS_NOT_INITIALIZED; + } + + if (g_ddi_bc_State == DDI_BC_STATE_DISABLED) + bDisableRequired = false; + else { + bDisableRequired = true; + ddi_bc_SetDisable(); + } + + /* Looking at the code, changing the period while the battery charger is running */ + /* doesn't seem to have a negative affect. One could wrap this in the mutex */ + /* or implement further coordination if it did. */ + g_ddi_bc_Configuration.u32StateMachinePeriod = u32StateMachinePeriod; + g_ddi_bc_Configuration.u16CurrentRampSlope = u16CurrentRampSlope; + + if (bDisableRequired) + ddi_bc_SetEnable(); + + return DDI_BC_STATUS_SUCCESS; + +} + + + +/* brief Report the state machine period. */ + +/* fntype Function */ + +/* This function reports the battery charger period. */ + +/* retval The battery charger period (in milliseconds). */ + + +uint32_t ddi_bc_GetStateMachinePeriod() +{ + return g_ddi_bc_Configuration.u32StateMachinePeriod; +} + + + +/* brief Report the current ramp slope. */ + +/* fntype Function */ + +/* This function reports the current ramp slope. */ + +/* retval The current ramp slope (in mA/s). */ + + +uint32_t ddi_bc_GetCurrentRampSlope() +{ + return g_ddi_bc_Configuration.u16CurrentRampSlope; +} + + + +/* brief Report the time spent in the present state (milliseconds) */ + +/* fntype Function */ + +/* This function reports the time spent in the present charging state. Note that */ +/* for the states that actually charge the battery, this time does not include the */ +/* time spent under alarm conditions such as die termperature alarm or battery */ +/* temperature alarm. */ + +/* retval The time spent in the current state in milliseconds. */ + + +uint32_t ddi_bc_GetStateTime(void) +{ + return g_ddi_bc_u32StateTimer; +} + + + +/* brief Report the reason for being in the broken state */ + +/* fntype Function */ + + +/* retval ddi_bc_BrokenReason_t enumeration */ + + +ddi_bc_BrokenReason_t ddi_bc_GetBrokenReason(void) +{ + return ddi_bc_gBrokenReason; +} + + + +/* brief Restart the charge cycle */ + +/* fntype Function */ + + +/* retval SUCCESS */ + + +ddi_bc_Status_t ddi_bc_ForceChargingToStart(void) +{ + static int16_t restarts; + + if (restarts < DDI_BC_MAX_RESTART_CYCLES) { + restarts++; + bRestartChargeCycle = true; + } + + return DDI_BC_STATUS_SUCCESS; +} + + +/* End of file */ + +/* @} */ diff --git a/drivers/power/mxs/ddi_bc_hw.c b/drivers/power/mxs/ddi_bc_hw.c new file mode 100644 index 000000000000..f1fdb6f2b065 --- /dev/null +++ b/drivers/power/mxs/ddi_bc_hw.c @@ -0,0 +1,397 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "ddi_bc_internal.h" + + +/* Includes and external references */ + + + +/* Variables */ + + + +/* Code */ + + + +/* */ +/* brief Report if the battery charging hardware is available. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports if the battery charging hardware is available by */ +/* reading the corresponding laser fuse bit. */ +/* */ +/* retval Zero if the battery charging hardware is not available. Non-zero */ +/* otherwise. */ +/* */ + +int ddi_bc_hwBatteryChargerIsEnabled(void) +{ + /* TODO: replace ddi_bc_hwBatteryChargerIsEnabled with the function below in the code */ + return (int)ddi_power_GetBatteryChargerEnabled(); +} + + +/* */ +/* brief Report the battery configuration. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the hardware battery configuration. */ +/* */ +/* retval A value that indicates the battery configuration. */ +/* */ + +ddi_bc_BatteryMode_t ddi_bc_hwGetBatteryMode(void) +{ + /* TODO: replace ddi_bc_hwGetBatteryMode() with the function below. */ + return (ddi_bc_BatteryMode_t) ddi_power_GetBatteryMode(); +} + + + +/* */ +/* brief Report the voltage across the battery. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the voltage across the battery. */ +/* */ +/* retval The voltage across the battery, in mV. */ +/* */ + +uint16_t ddi_bc_hwGetBatteryVoltage(void) +{ + /* TODO: replace ddi_bc_hwGetBattery with function below */ + return ddi_power_GetBattery(); +} + + +/* */ +/* brief Report on the presence of the power supply. */ +/* */ +/* fntype Function */ +/* */ +/* This function repots on whether or not the 5V power supply is present. */ +/* */ +/* retval Zero if the power supply is not present. Non-zero otherwise. */ +/* */ + +int ddi_bc_hwPowerSupplyIsPresent(void) +{ + /* TODO: replace ddi_bc_hwPowerSupplyIsPresent with the functino below. */ + return (int)ddi_power_Get5vPresentFlag(); +} + + +/* */ +/* brief Report the maximum charging current. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the maximum charging current that will be offered to */ +/* the battery, as currently set in the hardware. */ +/* */ +/* retval The maximum current setting in the hardware. */ +/* */ + +uint16_t ddi_bc_hwGetMaxCurrent(void) +{ + /* TODO: replace ddi_bc_hwGetMaxCurrent() with the below function */ + return (uint16_t) ddi_power_GetMaxBatteryChargeCurrent(); +} + + +/* */ +/* brief Set the maximum charging current. */ +/* */ +/* fntype Function */ +/* */ +/* This function sets the maximum charging current that will be offered to the */ +/* battery. */ +/* */ +/* Note that the hardware has a minimum resolution of 10mA and a maximum */ +/* expressible value of 780mA (see the data sheet for details). If the given */ +/* current cannot be expressed exactly, then the largest expressible smaller */ +/* value will be used. The return reports the actual value that was effected. */ +/* */ +/* param[in] u16Limit The maximum charging current, in mA. */ +/* */ +/* retval The actual value that was effected. */ +/* */ + +uint16_t ddi_bc_hwSetMaxCurrent(uint16_t u16Limit) +{ + /* TODO: replace ddi_bc_hwSetMaxChargeCurrent */ + return ddi_power_SetMaxBatteryChargeCurrent(u16Limit); +} + + +/* */ +/* brief Set the charging current threshold. */ +/* */ +/* fntype Function */ +/* */ +/* This function sets the charging current threshold. When the actual current */ +/* flow to the battery is less than this threshold, the HW_POWER_STS.CHRGSTS */ +/* flag is clear. */ +/* */ +/* Note that the hardware has a minimum resolution of 10mA and a maximum */ +/* expressible value of 180mA (see the data sheet for details). If the given */ +/* current cannot be expressed exactly, then the largest expressible smaller */ +/* value will be used. The return reports the actual value that was effected. */ +/* */ +/* param[in] u16Threshold The charging current threshold, in mA. */ +/* */ +/* retval The actual value that was effected. */ +/* */ + +uint16_t ddi_bc_hwSetCurrentThreshold(uint16_t u16Threshold) +{ + /* TODO: replace calls to ddi_bc_hwSetCurrentThreshold with the one below */ + return ddi_power_SetBatteryChargeCurrentThreshold(u16Threshold); + +} + + +/* */ +/* brief Report the charging current threshold. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the charging current threshold. When the actual */ +/* current flow to the battery is less than this threshold, the */ +/* HW_POWER_STS.CHRGSTS flag is clear. */ +/* */ +/* Note that the hardware has a minimum resolution of 10mA and a maximum */ +/* expressible value of 180mA (see the data sheet for details). */ +/* */ +/* retval The charging current threshold, in mA. */ +/* */ + +uint16_t ddi_bc_hwGetCurrentThreshold(void) +{ + /* TODO: replace calls to ddi_bc_hwGetCurrentThreshold with function below */ + return ddi_power_GetBatteryChargeCurrentThreshold(); +} + + +/* */ +/* brief Report if the charger hardware power is on. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports if the charger hardware power is on. */ +/* */ +/* retval Zero if the charger hardware is not powered. Non-zero otherwise. */ +/* */ + +int ddi_bc_hwChargerPowerIsOn(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD" */ + /* stands for "power down". Thus, when the bit is set, the battery charger */ + /* hardware is POWERED DOWN. */ + /* -------------------------------------------------------------------------- */ + + /* -------------------------------------------------------------------------- */ + /* Read the register and return the result. */ + /* -------------------------------------------------------------------------- */ + + /* TODO: replace ddi_bc_hwChargerPowerIsOn with function below */ + return ddi_power_GetChargerPowered(); +} + + +/* */ +/* brief Turn the charging hardware on or off. */ +/* */ +/* fntype Function */ +/* */ +/* This function turns the charging hardware on or off. */ +/* */ +/* param[in] on Indicates whether the charging hardware should be on or off. */ +/* */ + +void ddi_bc_hwSetChargerPower(int on) +{ + + /* -------------------------------------------------------------------------- */ + /* Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD" */ + /* stands for "power down". Thus, when the bit is set, the battery charger */ + /* hardware is POWERED DOWN. */ + /* -------------------------------------------------------------------------- */ + + /* -------------------------------------------------------------------------- */ + /* Hit the power switch. */ + /* -------------------------------------------------------------------------- */ + + /* TODO: replace ddi_bc_hwSetChargerPower with functino below */ + ddi_power_SetChargerPowered(on); +} + + +/* */ +/* brief Reports if the charging current has fallen below the threshold. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports if the charging current that the battery is accepting */ +/* has fallen below the threshold. */ +/* */ +/* Note that this bit is regarded by the hardware guys as very slightly */ +/* unreliable. They recommend that you don't believe a value of zero until */ +/* you've sampled it twice. */ +/* */ +/* retval Zero if the battery is accepting less current than indicated by the */ +/* charging threshold. Non-zero otherwise. */ +/* */ + +int ddi_bc_hwGetChargeStatus(void) +{ + return ddi_power_GetChargeStatus(); +} + + +/* */ +/* brief Report on the die temperature. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports on the die temperature. */ +/* */ +/* param[out] pLow The low end of the temperature range. */ +/* param[out] pHigh The high end of the temperature range. */ +/* */ + +void ddi_bc_hwGetDieTemp(int16_t *pLow, int16_t *pHigh) +{ + /* TODO: replace ddi_bc_hwGetDieTemp with function below */ + ddi_power_GetDieTemp(pLow, pHigh); +} + + +/* */ +/* brief Report the battery temperature reading. */ +/* */ +/* fntype Function */ +/* */ +/* This function examines the configured LRADC channel and reports the battery */ +/* temperature reading. */ +/* */ +/* param[out] pReading A pointer to a variable that will receive the */ +/* temperature reading. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If the operation succeeded. */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* */ + +ddi_bc_Status_t ddi_bc_hwGetBatteryTemp(uint16_t *pReading) +{ + return (ddi_bc_Status_t)DDI_BC_STATUS_HARDWARE_DISABLED; +} + + +/* */ +/* brief Convert a current in mA to a hardware setting. */ +/* */ +/* fntype Function */ +/* */ +/* This function converts a current measurement in mA to a hardware setting */ +/* used by HW_POWER_BATTCHRG.STOP_ILIMIT or HW_POWER_BATTCHRG.BATTCHRG_I. */ +/* */ +/* Note that the hardware has a minimum resolution of 10mA and a maximum */ +/* expressible value of 780mA (see the data sheet for details). If the given */ +/* current cannot be expressed exactly, then the largest expressible smaller */ +/* value will be used. */ +/* */ +/* param[in] u16Current The current of interest. */ +/* */ +/* retval The corresponding setting. */ +/* */ + +uint8_t ddi_bc_hwCurrentToSetting(uint16_t u16Current) +{ + return ddi_power_convert_current_to_setting(u16Current); +} + + +/* */ +/* brief Convert a hardware current setting to a value in mA. */ +/* */ +/* fntype Function */ +/* */ +/* This function converts a setting used by HW_POWER_BATTCHRG.STOP_ILIMIT or */ +/* HW_POWER_BATTCHRG.BATTCHRG_I into an actual current measurement in mA. */ +/* */ +/* Note that the hardware current fields are 6 bits wide. The higher bits in */ +/* the 8-bit input parameter are ignored. */ +/* */ +/* param[in] u8Setting A hardware current setting. */ +/* */ +/* retval The corresponding current in mA. */ +/* */ + +uint16_t ddi_bc_hwSettingToCurrent(uint8_t u8Setting) +{ + return ddi_power_convert_setting_to_current(u8Setting); +} + + +/* */ +/* brief Compute the actual current expressible in the hardware. */ +/* */ +/* fntype Function */ +/* */ +/* Given a desired current, this function computes the actual current */ +/* expressible in the hardware. */ +/* */ +/* Note that the hardware has a minimum resolution of 10mA and a maximum */ +/* expressible value of 780mA (see the data sheet for details). If the given */ +/* current cannot be expressed exactly, then the largest expressible smaller */ +/* value will be used. */ +/* */ +/* param[in] u16Current The current of interest. */ +/* */ +/* retval The corresponding current in mA. */ +/* */ + +uint16_t ddi_bc_hwExpressibleCurrent(uint16_t u16Current) +{ + /* TODO: replace the bc function with this one */ + return ddi_power_ExpressibleCurrent(u16Current); +} + + +/* */ +/* brief Checks to see if the DCDC has been manually enabled */ +/* */ +/* fntype Function */ +/* */ +/* retval true if DCDC is ON, false if DCDC is OFF. */ +/* */ + +bool ddi_bc_hwIsDcdcOn(void) +{ + return ddi_power_IsDcdcOn(); +} + + +/* End of file */ + +/* @} */ diff --git a/drivers/power/mxs/ddi_bc_hw.h b/drivers/power/mxs/ddi_bc_hw.h new file mode 100644 index 000000000000..9275c5b3a7ba --- /dev/null +++ b/drivers/power/mxs/ddi_bc_hw.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DDI_BC_HW_H +#define _DDI_BC_HW_H + + +/* Definitions */ + + +/* The enumeration of battery modes. */ + +typedef enum _ddi_bc_BatteryMode { + DDI_BC_BATTERY_MODE_LI_ION_2_CELLS = 0, + DDI_BC_BATTERY_MODE_LI_ION_1_CELL = 1, + DDI_BC_BATTERY_MODE_2_CELLS = 2, + DDI_BC_BATTERY_MODE_1_CELL = 3 +} ddi_bc_BatteryMode_t; + +/* The enumeration of bias current sources. */ + +typedef enum _ddi_bc_BiasCurrentSource { + DDI_BC_EXTERNAL_BIAS_CURRENT = 0, + DDI_BC_INTERNAL_BIAS_CURRENT = 1, +} ddi_bc_BiasCurrentSource_t; + + +/* Prototypes */ + + +extern int ddi_bc_hwBatteryChargerIsEnabled(void); +extern ddi_bc_BatteryMode_t ddi_bc_hwGetBatteryMode(void); +extern ddi_bc_BiasCurrentSource_t ddi_bc_hwGetBiasCurrentSource(void); +extern ddi_bc_Status_t +ddi_bc_hwSetBiasCurrentSource(ddi_bc_BiasCurrentSource_t); +extern ddi_bc_Status_t ddi_bc_hwSetChargingVoltage(uint16_t); +extern uint16_t ddi_bc_hwGetBatteryVoltage(void); +extern int ddi_bc_hwPowerSupplyIsPresent(void); +extern uint16_t ddi_bc_hwSetMaxCurrent(uint16_t); +extern uint16_t ddi_bc_hwGetMaxCurrent(void); +extern uint16_t ddi_bc_hwSetCurrentThreshold(uint16_t); +extern uint16_t ddi_bc_hwGetCurrentThreshold(void); +extern int ddi_bc_hwChargerPowerIsOn(void); +extern void ddi_bc_hwSetChargerPower(int); +extern int ddi_bc_hwGetChargeStatus(void); +extern void ddi_bc_hwGetDieTemp(int16_t *, int16_t *); +extern ddi_bc_Status_t ddi_bc_hwGetBatteryTemp(uint16_t *); +uint8_t ddi_bc_hwCurrentToSetting(uint16_t); +uint16_t ddi_bc_hwSettingToCurrent(uint8_t); +uint16_t ddi_bc_hwExpressibleCurrent(uint16_t); + + +/* */ +/* brief Checks to see if the DCDC has been manually enabled */ +/* */ +/* fntype Function */ +/* */ +/* retval true if DCDC is ON, false if DCDC is OFF. */ +/* */ + +bool ddi_bc_hwIsDcdcOn(void); + + +/* End of file */ + +#endif /* _DDI_BC_H */ +/* @} */ diff --git a/drivers/power/mxs/ddi_bc_init.c b/drivers/power/mxs/ddi_bc_init.c new file mode 100644 index 000000000000..c93f8969f92c --- /dev/null +++ b/drivers/power/mxs/ddi_bc_init.c @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "ddi_bc_internal.h" + + +/* addtogroup ddi_bc */ +/* @{ */ +/* */ +/* Copyright (c) 2004-2005 SigmaTel, Inc. */ +/* */ +/* file ddi_bc_init.c */ +/* brief Contains the Battery Charger initialization function. */ +/* date 06/2005 */ +/* */ +/* This file contains Battery Charger initialization function. */ +/* */ + + + +/* Includes and external references */ + +#include +#include "ddi_bc_internal.h" + + +/* Code */ + + + +/* brief Initialize the Battery Charger. */ +/* */ +/* fntype Function */ +/* */ +/* This function initializes the Battery Charger. */ +/* */ +/* param[in] pCfg A pointer to the new configuration. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS */ +/* If the operation succeeded. */ +/* retval DDI_BC_STATUS_ALREADY_INITIALIZED */ +/* If the Battery Charger is already initialized. */ +/* retval DDI_BC_STATUS_HARDWARE_DISABLED */ +/* If the Battery Charger hardware is disabled by a laser fuse. */ +/* retval DDI_BC_STATUS_BAD_BATTERY_MODE */ +/* If the power supply is set up for a non-rechargeable battery. */ +/* retval DDI_BC_STATUS_CLOCK_GATE_CLOSED */ +/* If the clock gate for the power supply registers is closed. */ +/* retval DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE */ +/* If the charging voltage is not either 4100 or 4200. */ +/* retval DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL */ +/* If the LRADC channel number for monitoring battery temperature */ +/* is bad. */ +/* */ + +ddi_bc_Status_t ddi_bc_Init(ddi_bc_Cfg_t *pCfg) +{ + + /* -------------------------------------------------------------------------- */ + /* We can only be initialized if we're in the Uninitialized state. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State != DDI_BC_STATE_UNINITIALIZED) { + return DDI_BC_STATUS_ALREADY_INITIALIZED; + } + /* -------------------------------------------------------------------------- */ + /* Check if the battery charger hardware has been disabled by laser fuse. */ + /* -------------------------------------------------------------------------- */ + + if (!ddi_power_GetBatteryChargerEnabled()) + return DDI_BC_STATUS_HARDWARE_DISABLED; + + /* -------------------------------------------------------------------------- */ + /* Check if the power supply has been set up for a non-rechargeable battery. */ + /* -------------------------------------------------------------------------- */ + + switch (ddi_power_GetBatteryMode()) { + + case DDI_POWER_BATT_MODE_LIION: + break; + + /* TODO: we'll need to do NiMH also */ + default: + return DDI_BC_STATUS_BAD_BATTERY_MODE; + /* break; */ + + } + + /* -------------------------------------------------------------------------- */ + /* Make sure that the clock gate has been opened for the power supply */ + /* registers. If not, then none of our writes to those registers will */ + /* succeed, which will kind of slow us down... */ + /* -------------------------------------------------------------------------- */ + + if (ddi_power_GetPowerClkGate()) { + return DDI_BC_STATUS_CLOCK_GATE_CLOSED; + } + /* -------------------------------------------------------------------------- */ + /* Check the incoming configuration for nonsense. */ + /* -------------------------------------------------------------------------- */ + + /* */ + /* Only permitted charging voltage: 4200mV. */ + /* */ + + if (pCfg->u16ChargingVoltage != DDI_BC_LIION_CHARGING_VOLTAGE) { + return DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE; + } + /* */ + /* There are 8 LRADC channels. */ + /* */ + + if (pCfg->u8BatteryTempChannel > 7) { + return DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL; + } + /* -------------------------------------------------------------------------- */ + /* Accept the configuration. */ + /* -------------------------------------------------------------------------- */ + + /* -------------------------------------------------------------------------- */ + /* ddi_bc_Cfg_t.u16ChargingThresholdCurrent is destined for the */ + /* register field HW_POWER_BATTCHRG.STOP_ILIMIT. This 4-bit field */ + /* is unevenly quantized to provide a useful range of currents. A */ + /* side effect of the quantization is that the field can only be */ + /* set to certain unevenly-spaced values. */ + /* */ + /* Here, we use the two functions that manipulate the register field */ + /* to adjust u16ChargingThresholdCurrent to match the quantized value. */ + /* -------------------------------------------------------------------------- */ + pCfg->u16ChargingThresholdCurrent = + ddi_power_ExpressibleCurrent(pCfg->u16ChargingThresholdCurrent); + + /* -------------------------------------------------------------------------- */ + /* ...similar situation with ddi_bc_Cfg_t.u16BatteryTempSafeCurrent and */ + /* u16DieTempSafeCurrent. */ + /* -------------------------------------------------------------------------- */ + pCfg->u16BatteryTempSafeCurrent = + ddi_power_ExpressibleCurrent(pCfg->u16BatteryTempSafeCurrent); + pCfg->u16DieTempSafeCurrent = + ddi_power_ExpressibleCurrent(pCfg->u16DieTempSafeCurrent); + + g_ddi_bc_Configuration = *pCfg; + + /* -------------------------------------------------------------------------- */ + /* Turn the charger hardware off. This is a very important initial condition */ + /* because we only flip the power switch on the hardware when we make */ + /* transitions. Baseline, it needs to be off. */ + /* -------------------------------------------------------------------------- */ + + ddi_power_SetChargerPowered(0); + + /* -------------------------------------------------------------------------- */ + /* Reset the current ramp. This will jam the current to zero and power off */ + /* the charging hardware. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampReset(); + + /* -------------------------------------------------------------------------- */ + /* Move to the Disabled state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_DISABLED; + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("%s: success\n", __func__); +#endif + return DDI_BC_STATUS_SUCCESS; + +} + + +/* End of file */ + +/* @} */ diff --git a/drivers/power/mxs/ddi_bc_internal.h b/drivers/power/mxs/ddi_bc_internal.h new file mode 100644 index 000000000000..b5bceeffae98 --- /dev/null +++ b/drivers/power/mxs/ddi_bc_internal.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/* addtogroup ddi_bc */ +/* @{ */ +/* */ +/* Copyright (c) 2004-2005 SigmaTel, Inc. */ +/* */ +/* file ddi_bc_internal.h */ +/* brief Internal header file for the Battery Charger device driver. */ +/* date 06/2005 */ +/* */ +/* This file contains internal declarations for the Battery Charger device */ +/* driver. */ + + +#ifndef _DDI_BC_INTERNAL_H +#define _DDI_BC_INTERNAL_H + + +/* Includes */ + + +#include +#include "ddi_bc_hw.h" +#include "ddi_bc_ramp.h" +#include "ddi_bc_sm.h" +#include "ddi_power_battery.h" + + +/* Externs */ + +#include + +extern bool g_ddi_bc_Configured; +extern ddi_bc_Cfg_t g_ddi_bc_Configuration; + + +/* End of file */ + +#endif /* _DDI_BC_H */ +/* @} */ diff --git a/drivers/power/mxs/ddi_bc_ramp.c b/drivers/power/mxs/ddi_bc_ramp.c new file mode 100644 index 000000000000..76efc0d5c32d --- /dev/null +++ b/drivers/power/mxs/ddi_bc_ramp.c @@ -0,0 +1,724 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/* addtogroup ddi_bc */ +/* @{ */ +/* */ +/* Copyright (c) 2004-2005 SigmaTel, Inc. */ +/* */ +/* file ddi_bc_ramp.c */ +/* brief Contains the Battery Charger current ramp controller. */ +/* date 06/2005 */ +/* */ +/* This file contains Battery Charger current ramp controller. */ +/* */ + + + +/* Includes and external references */ + + +#include +#include "ddi_bc_internal.h" + + +/* Definitions */ + + +/* This is the control structure for the current ramp. */ + +typedef struct _ddi_bc_RampControl { + + uint32_t u32AccumulatedTime; + + /* < The accumulated time since we last changed the actual */ + /* < current setting in the hardware. If the time between */ + /* < steps is quite short, we may have to wait for several steps */ + /* < before we can actually change the hardware setting. */ + + uint16_t u16Target; + + /* < The target current, regardless of expressibility. */ + + uint16_t u16Limit; + + /* < The current limit, regardless of expressibility. */ + + uint8_t dieTempAlarm:1; + + /* < Indicates if we are operating under a die temperature */ + /* < alarm. */ + + uint8_t batteryTempAlarm:1; + + /* < Indicates if we are operating under a battery temperature */ + /* < alarm. */ + + uint8_t ambientTempAlarm:1; + + /* < Indicates if we are operating under an ambient temperature */ + /* < alarm. */ + +} ddi_bc_RampControl_t; + + +/* Variables */ + + +/* This structure contains control information for the current ramp. */ + +static ddi_bc_RampControl_t g_RampControl; + + +/* Code */ + + + +/* */ +/* brief Reset the current ramp. */ +/* */ +/* fntype Function */ +/* */ +/* This function resets the current ramp. */ +/* */ +/* Note that this function does NOT reset the temperature alarms or the current */ +/* limit. Those can only be changed explicitly. */ +/* */ + +void ddi_bc_RampReset() +{ + + /* -------------------------------------------------------------------------- */ + /* Reset the control structure. */ + /* -------------------------------------------------------------------------- */ + + g_RampControl.u32AccumulatedTime = 0; + g_RampControl.u16Target = 0; + + /* -------------------------------------------------------------------------- */ + /* Step the ramp. Note that we don't care if this function returns an error. */ + /* We're stepping the ramp to make sure it takes immediate effect, if */ + /* possible. But, for example, if the Battery Charger is not yet */ + /* initialized, it doesn't matter. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampStep(0); + +} + + +/* */ +/* brief Set the target current. */ +/* */ +/* fntype Function */ +/* */ +/* This function sets the target current and implements it immediately. */ +/* */ +/* Note that this function does NOT reset the temperature alarms. Those can */ +/* only be reset explicitly. */ +/* */ +/* param[in] u16Target The target current. */ +/* */ +/* retval The expressible version of the target. */ +/* */ + +uint16_t ddi_bc_RampSetTarget(uint16_t u16Target) +{ + + /* -------------------------------------------------------------------------- */ + /* Set the target. */ + /* -------------------------------------------------------------------------- */ + + g_RampControl.u16Target = u16Target; + + /* -------------------------------------------------------------------------- */ + /* Step the ramp. Note that we don't care if this function returns an error. */ + /* We're stepping the ramp to make sure it takes immediate effect, if */ + /* possible. But, for example, if the Battery Charger is not yet */ + /* initialized, it doesn't matter. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampStep(0); + + /* -------------------------------------------------------------------------- */ + /* Compute and return the expressible target. */ + /* -------------------------------------------------------------------------- */ + + return ddi_bc_hwExpressibleCurrent(u16Target); + +} + + +/* */ +/* brief Report the target. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the target. */ +/* */ +/* retval The target. */ +/* */ + +uint16_t ddi_bc_RampGetTarget(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Return the target. */ + /* -------------------------------------------------------------------------- */ + + return g_RampControl.u16Target; + +} + + +/* */ +/* brief Set the current limit. */ +/* */ +/* fntype Function */ +/* */ +/* This function sets the current limit and implements it immediately. */ +/* */ +/* param[in] u16Limit The current limit. */ +/* */ +/* retval The expressible version of the limit. */ +/* */ + +uint16_t ddi_bc_RampSetLimit(uint16_t u16Limit) +{ + + /* -------------------------------------------------------------------------- */ + /* Set the limit. */ + /* -------------------------------------------------------------------------- */ + + g_RampControl.u16Limit = u16Limit; + + /* -------------------------------------------------------------------------- */ + /* Step the ramp. Note that we don't care if this function returns an error. */ + /* We're stepping the ramp to make sure it takes immediate effect, if */ + /* possible. But, for example, if the Battery Charger is not yet */ + /* initialized, it doesn't matter. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampStep(0); + + /* -------------------------------------------------------------------------- */ + /* Compute and return the expressible limit. */ + /* -------------------------------------------------------------------------- */ + + return ddi_bc_hwExpressibleCurrent(u16Limit); + +} + + +/* */ +/* brief Report the current limit. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the current limit. */ +/* */ +/* retval The current limit. */ +/* */ + +uint16_t ddi_bc_RampGetLimit(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Return the current limit. */ + /* -------------------------------------------------------------------------- */ + + return g_RampControl.u16Limit; + +} + + +/* */ +/* brief Update alarms. */ +/* */ +/* fntype Function */ +/* */ +/* This function checks for all alarms and updates the current ramp */ +/* accordingly. */ +/* */ + +void ddi_bc_RampUpdateAlarms() +{ + + /* Set to true if something changed and we need to step the ramp right away. */ + + int iStepTheRamp = 0; + + /* -------------------------------------------------------------------------- */ + /* Are we monitoring die temperature? */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_Configuration.monitorDieTemp) { + + /* ---------------------------------------------------------------------- */ + /* Get the die temperature range. */ + /* ---------------------------------------------------------------------- */ + + int16_t i16Low; + int16_t i16High; + + ddi_bc_hwGetDieTemp(&i16Low, &i16High); + + /* ---------------------------------------------------------------------- */ + /* Now we need to decide if it's time to raise or lower the alarm. The */ + /* first question to ask is: Were we already under an alarm? */ + /* ---------------------------------------------------------------------- */ + + if (g_RampControl.dieTempAlarm) { + + /* ------------------------------------------------------------------ */ + /* If control arrives here, we were already under an alarm. We'll */ + /* change that if the high end of the temperature range drops below */ + /* the low temperature mark. */ + /* ------------------------------------------------------------------ */ + + if (i16High < g_ddi_bc_Configuration.u8DieTempLow) { + + /* -------------------------------------------------------------- */ + /* If control arrives here, we're safe now. Drop the alarm. */ + /* -------------------------------------------------------------- */ + + g_RampControl.dieTempAlarm = 0; + + iStepTheRamp = !0; + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: releasing " + "die temp alarm: [%d, %d] < %d\r\n", + (int32_t) i16Low, (int32_t) i16High, + (int32_t) g_ddi_bc_Configuration. + u8DieTempLow); +#endif + + } + + } else { + + /* ------------------------------------------------------------------ */ + /* If control arrives here, we were not under an alarm. We'll change */ + /* that if the high end of the temperature range rises above the */ + /* high temperature mark. */ + /* ------------------------------------------------------------------ */ + + if (i16High >= g_ddi_bc_Configuration.u8DieTempHigh) { + + /* -------------------------------------------------------------- */ + /* If control arrives here, we're running too hot. Raise the */ + /* alarm. */ + /* -------------------------------------------------------------- */ + + g_RampControl.dieTempAlarm = 1; + + iStepTheRamp = !0; + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: declaring " + "die temp alarm: [%d, %d] >= %d\r\n", + (int32_t) i16Low, (int32_t) i16High, + (int32_t) g_ddi_bc_Configuration. + u8DieTempLow); +#endif + } + + } + + } + /* -------------------------------------------------------------------------- */ + /* Are we monitoring battery temperature? */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_Configuration.monitorBatteryTemp) { + + ddi_bc_Status_t status; + + /* ---------------------------------------------------------------------- */ + /* Get the battery temperature reading. */ + /* ---------------------------------------------------------------------- */ + + uint16_t u16Reading; + + status = ddi_bc_hwGetBatteryTemp(&u16Reading); + + /* ---------------------------------------------------------------------- */ + /* If there was a problem, then we ignore the reading. Otherwise, let's */ + /* have a look. */ + /* ---------------------------------------------------------------------- */ + + if (status == DDI_BC_STATUS_SUCCESS) { + + /* ------------------------------------------------------------------ */ + /* Now we need to decide if it's time to raise or lower the alarm. */ + /* The first question to ask is: Were we already under an alarm? */ + /* ------------------------------------------------------------------ */ + + if (g_RampControl.batteryTempAlarm) { + + /* -------------------------------------------------------------- */ + /* If control arrives here, we were already under an alarm. */ + /* We'll change that if the reading drops below the low mark. */ + /* -------------------------------------------------------------- */ + + if (u16Reading < + g_ddi_bc_Configuration.u16BatteryTempLow) { + + /* ---------------------------------------------------------- */ + /* If control arrives here, we're safe now. Drop the alarm. */ + /* ---------------------------------------------------------- */ + + g_RampControl.batteryTempAlarm = 0; + + iStepTheRamp = !0; + + } + + } else { + + /* -------------------------------------------------------------- */ + /* If control arrives here, we were not under an alarm. We'll */ + /* change that if the reading rises above the high mark. */ + /* -------------------------------------------------------------- */ + + if (u16Reading >= + g_ddi_bc_Configuration.u16BatteryTempHigh) { + + /* ---------------------------------------------------------- */ + /* If control arrives here, we're running too hot. Raise the */ + /* alarm. */ + /* ---------------------------------------------------------- */ + + g_RampControl.batteryTempAlarm = 1; + + iStepTheRamp = !0; + + } + + } + + } + + } + /* -------------------------------------------------------------------------- */ + /* Do we need to step the ramp? */ + /* -------------------------------------------------------------------------- */ + + if (iStepTheRamp) + ddi_bc_RampStep(0); + +} + + +/* */ +/* brief Reports the state of the die temperature alarm. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the state of the die temperature alarm. */ +/* */ +/* retval The state of the die temperature alarm. */ +/* */ + +int ddi_bc_RampGetDieTempAlarm(void) +{ + return g_RampControl.dieTempAlarm; +} + + +/* */ +/* brief Reports the state of the battery temperature alarm. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the state of the battery temperature alarm. */ +/* */ +/* retval The state of the battery temperature alarm. */ +/* */ + +int ddi_bc_RampGetBatteryTempAlarm(void) +{ + return g_RampControl.batteryTempAlarm; +} + + +/* */ +/* brief Reports the state of the ambient temperature alarm. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the state of the ambient temperature alarm. */ +/* */ +/* retval The state of the ambient temperature alarm. */ +/* */ + +int ddi_bc_RampGetAmbientTempAlarm(void) +{ + return g_RampControl.ambientTempAlarm; +} + + +/* */ +/* brief Step the current ramp. */ +/* */ +/* fntype Function */ +/* */ +/* This function steps the current ramp forward through the given amount of time. */ +/* */ +/* param[in] u32Time The time increment to add. */ +/* */ +/* retval DDI_BC_STATUS_SUCCESS If the operation succeeded. */ +/* retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet */ +/* initialized. */ +/* */ + +ddi_bc_Status_t ddi_bc_RampStep(uint32_t u32Time) +{ + + uint16_t u16MaxNow; + uint16_t u16Target; + uint16_t u16Cart; + int32_t i32Delta; + + /* -------------------------------------------------------------------------- */ + /* Make sure the Battery Charger is initialized. */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_State == DDI_BC_STATE_UNINITIALIZED) { + return DDI_BC_STATUS_NOT_INITIALIZED; + } + /* -------------------------------------------------------------------------- */ + /* Figure out how much current the hardware is set to draw right now. */ + /* -------------------------------------------------------------------------- */ + + u16MaxNow = ddi_bc_hwGetMaxCurrent(); + + /* -------------------------------------------------------------------------- */ + /* Start with the target. */ + /* -------------------------------------------------------------------------- */ + + u16Target = g_RampControl.u16Target; + + /* -------------------------------------------------------------------------- */ + /* Check the target against the hard limit. */ + /* -------------------------------------------------------------------------- */ + + if (u16Target > g_RampControl.u16Limit) + u16Target = g_RampControl.u16Limit; + + /* -------------------------------------------------------------------------- */ + /* Check if the die temperature alarm is active. */ + /* -------------------------------------------------------------------------- */ + + if (g_RampControl.dieTempAlarm) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, we are under a die temperature alarm. Clamp */ + /* the target current. */ + /* ---------------------------------------------------------------------- */ + + if (u16Target > g_ddi_bc_Configuration.u16DieTempSafeCurrent) { + u16Target = + g_ddi_bc_Configuration.u16DieTempSafeCurrent; + } + + } + /* -------------------------------------------------------------------------- */ + /* Check if the battery temperature alarm is active. */ + /* -------------------------------------------------------------------------- */ + + if (g_RampControl.batteryTempAlarm) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, we are under a battery temperature alarm. */ + /* Clamp the target current. */ + /* ---------------------------------------------------------------------- */ + + if (u16Target > + g_ddi_bc_Configuration.u16BatteryTempSafeCurrent) { + u16Target = + g_ddi_bc_Configuration.u16BatteryTempSafeCurrent; + } + + } + /* -------------------------------------------------------------------------- */ + /* Now we know the target current. Figure out what is actually expressible */ + /* in the hardware. */ + /* -------------------------------------------------------------------------- */ + + u16Target = ddi_bc_hwExpressibleCurrent(u16Target); + + /* -------------------------------------------------------------------------- */ + /* Compute the difference between the expressible target and what's actually */ + /* set in the hardware right now. */ + /* -------------------------------------------------------------------------- */ + + i32Delta = ((int32_t) u16Target) - ((int32_t) u16MaxNow); + + /* -------------------------------------------------------------------------- */ + /* Check if the delta is zero. */ + /* -------------------------------------------------------------------------- */ + + if (i32Delta == 0) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, there is no difference between what we want */ + /* and what's set in the hardware. */ + /* */ + /* Before we leave, though, we don't want to leave any accumulated time */ + /* laying around for the next ramp up. Zero it out. */ + /* ---------------------------------------------------------------------- */ + + g_RampControl.u32AccumulatedTime = 0; + + /* ---------------------------------------------------------------------- */ + /* Return success. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + + } + /* -------------------------------------------------------------------------- */ + /* Check if the delta is negative. */ + /* -------------------------------------------------------------------------- */ + + if (i32Delta < 0) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, the new target is lower than what's */ + /* currently set in the hardware. Since that means we're *reducing* the */ + /* current draw, we can do it right now. Just gimme a sec here... */ + /* ---------------------------------------------------------------------- */ + + ddi_bc_hwSetMaxCurrent(u16Target); + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: setting max charge " + "current to: %hdmA\r\n", u16Target); +#endif + + /* ---------------------------------------------------------------------- */ + /* Flip the power switch on the charging hardware according to the new */ + /* current setting. */ + /* ---------------------------------------------------------------------- */ + + ddi_bc_hwSetChargerPower(u16Target != 0); + + /* ---------------------------------------------------------------------- */ + /* We don't want to leave any accumulated time laying around for the */ + /* next ramp up. Zero it out. */ + /* ---------------------------------------------------------------------- */ + + g_RampControl.u32AccumulatedTime = 0; + + /* ---------------------------------------------------------------------- */ + /* Return success. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + + } + /* -------------------------------------------------------------------------- */ + /* If control arrives here, the target current is higher than what's set in */ + /* the hardware right now. That means we're going to ramp it up. To do that, */ + /* we're going to "buy" more milliamps by "spending" milliseconds of time. */ + /* Add the time we've "banked" to the time we've been credited in this call. */ + /* -------------------------------------------------------------------------- */ + + u32Time += g_RampControl.u32AccumulatedTime; + + /* -------------------------------------------------------------------------- */ + /* Now we know how much we can spend. How much current will it buy? */ + /* -------------------------------------------------------------------------- */ + + u16Cart = (g_ddi_bc_Configuration.u16CurrentRampSlope * u32Time) / 1000; + + /* -------------------------------------------------------------------------- */ + /* Check how the current we can afford stacks up against the target we want. */ + /* -------------------------------------------------------------------------- */ + + if ((u16MaxNow + u16Cart) < u16Target) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, we can't afford to buy all the current we */ + /* want. Compute the maximum we can afford, and then figure out what we */ + /* can actually express in the hardware. */ + /* ---------------------------------------------------------------------- */ + + u16Target = ddi_bc_hwExpressibleCurrent(u16MaxNow + u16Cart); + + /* ---------------------------------------------------------------------- */ + /* Check if the result isn't actually different from what's set in the */ + /* the hardware right now. */ + /* ---------------------------------------------------------------------- */ + + if (u16Target == u16MaxNow) { + + /* ------------------------------------------------------------------ */ + /* If control arrives here, we are so poor that we can't yet afford */ + /* to buy enough current to make a change in the expressible */ + /* hardware setting. Since we didn't spend any of our time, put the */ + /* new balance back in the bank. */ + /* ------------------------------------------------------------------ */ + + g_RampControl.u32AccumulatedTime = u32Time; + + /* ------------------------------------------------------------------ */ + /* Leave dispiritedly. */ + /* ------------------------------------------------------------------ */ + + return DDI_BC_STATUS_SUCCESS; + + } + + } + /* -------------------------------------------------------------------------- */ + /* If control arrives here, we can afford to buy enough current to get us */ + /* all the way to the target. Set it. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_hwSetMaxCurrent(u16Target); + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: setting max charge" + "current to: %hdmA\r\n", u16Target); +#endif + + /* -------------------------------------------------------------------------- */ + /* Flip the power switch on the charging hardware according to the new */ + /* current setting. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_hwSetChargerPower(u16Target != 0); + + /* -------------------------------------------------------------------------- */ + /* We're at the target, so we're finished buying current. Zero out the */ + /* account. */ + /* -------------------------------------------------------------------------- */ + + g_RampControl.u32AccumulatedTime = 0; + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + +/* End of file */ + +/* @} */ diff --git a/drivers/power/mxs/ddi_bc_ramp.h b/drivers/power/mxs/ddi_bc_ramp.h new file mode 100644 index 000000000000..b43db8147f52 --- /dev/null +++ b/drivers/power/mxs/ddi_bc_ramp.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/* addtogroup ddi_bc */ +/* ! @{ */ +/* */ +/* Copyright (c) 2004-2005 SigmaTel, Inc. */ +/* */ +/* file ddi_bc_ramp.h */ +/* brief Internal header file for Battery Charger current ramp controller. */ +/* date 06/2005 */ +/* ! */ +/* ! This file contains internal declarations for Battery current ramp */ +/* ! controller. */ + + +#ifndef _DDI_BC_RAMP_H +#define _DDI_BC_RAMP_H + + +/* Prototypes */ + + +extern void ddi_bc_RampReset(void); +extern uint16_t ddi_bc_RampSetTarget(uint16_t); +extern uint16_t ddi_bc_RampGetTarget(void); +extern uint16_t ddi_bc_RampSetLimit(uint16_t); +extern uint16_t ddi_bc_RampGetLimit(void); +extern void ddi_bc_RampUpdateAlarms(void); +extern int ddi_bc_RampGetDieTempAlarm(void); +extern int ddi_bc_RampGetBatteryTempAlarm(void); +extern int ddi_bc_RampGetAmbientTempAlarm(void); +extern ddi_bc_Status_t ddi_bc_RampStep(uint32_t); + + +/* End of file */ + +#endif /* _DDI_BC_H */ +/* ! @} */ diff --git a/drivers/power/mxs/ddi_bc_sm.c b/drivers/power/mxs/ddi_bc_sm.c new file mode 100644 index 000000000000..6626ed82c192 --- /dev/null +++ b/drivers/power/mxs/ddi_bc_sm.c @@ -0,0 +1,918 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/* addtogroup ddi_bc */ +/* @{ */ +/* */ +/* Copyright (c) 2004-2005 SigmaTel, Inc. */ +/* */ +/* file ddi_bc_sm.c */ +/* brief Contains the Battery Charger state machine. */ + + + +/* Includes */ + + +#include +#include "ddi_bc_internal.h" + +#include + + +/* Definitions */ + + +/* This is the minimum time we must charge before we transition from */ +/* the charging state to the topping off. If we reach the */ +/* u16ChargingThresholdCurrent charge curent before then, the battery was */ +/* already full so we can avoid the risk of charging it past .1C for */ +/* too long. */ + +#define TRANSITION_TO_TOPOFF_MINIMUM_CHARGE_TIME_mS (1 * 60 * 1000) /* 1 minute */ + + +/* Variables */ + + +/* The current state. */ + +ddi_bc_State_t g_ddi_bc_State = DDI_BC_STATE_UNINITIALIZED; + +/* This table contains pointers to the functions that implement states. The */ +/* table is indexed by state. Note that it's critically important for this */ +/* table to agree with the state enumeration in ddi_bc.h. */ + +static ddi_bc_Status_t ddi_bc_Uninitialized(void); +static ddi_bc_Status_t ddi_bc_Broken(void); +static ddi_bc_Status_t ddi_bc_Disabled(void); +static ddi_bc_Status_t ddi_bc_WaitingToCharge(void); +static ddi_bc_Status_t ddi_bc_Conditioning(void); +static ddi_bc_Status_t ddi_bc_Charging(void); +static ddi_bc_Status_t ddi_bc_ToppingOff(void); + + +ddi_bc_Status_t(*const (stateFunctionTable[])) (void) = { +ddi_bc_Uninitialized, + ddi_bc_Broken, + ddi_bc_Disabled, + ddi_bc_WaitingToCharge, + ddi_bc_Conditioning, + ddi_bc_Charging, ddi_bc_ToppingOff}; + +/* Used by states that need to watch the time. */ +uint32_t g_ddi_bc_u32StateTimer; + +/* Always attempt to charge on first 5V connection */ +bool bRestartChargeCycle = true; + +#ifdef CONFIG_POWER_SUPPLY_DEBUG +static uint16_t u16ExternalBatteryPowerVoltageCheck; +#endif + +ddi_bc_BrokenReason_t ddi_bc_gBrokenReason = DDI_BC_BROKEN_UNINITIALIZED; + + +/* Code */ + + + +/* */ +/* brief Transition to the Waiting to Charge state. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the transition to the Waiting to Charge state. */ +/* */ + +static void TransitionToWaitingToCharge(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + + /* -------------------------------------------------------------------------- */ + /* Reset the current ramp. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampReset(); + + /* -------------------------------------------------------------------------- */ + /* Move to the Waiting to Charge state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_WAITING_TO_CHARGE; + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: now waiting to charge\n"); +#endif + +} + + +/* */ +/* brief Transition to the Conditioning state. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the transition to the Conditioning state. */ +/* */ + +static void TransitionToConditioning(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + + /* -------------------------------------------------------------------------- */ + /* Set up the current ramp for conditioning. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ConditioningCurrent); + + /* -------------------------------------------------------------------------- */ + /* Move to the Conditioning state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_CONDITIONING; + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: now conditioning\n"); +#endif + +} + + +/* */ +/* brief Transition to the Charging state. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the transition to the Charging state. */ +/* */ + +static void TransitionToCharging(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + + /* -------------------------------------------------------------------------- */ + /* Set up the current ramp for charging. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ChargingCurrent); + + /* -------------------------------------------------------------------------- */ + /* We'll be finished charging when the current flow drops below this level. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_hwSetCurrentThreshold(g_ddi_bc_Configuration. + u16ChargingThresholdCurrent); + + /* -------------------------------------------------------------------------- */ + /* Move to the Charging state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_CHARGING; +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: now charging\n"); +#endif +} + + +/* */ +/* brief Transition to the Topping Off state. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the transition to the Topping Off state. */ +/* */ + +static void TransitionToToppingOff(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + + /* -------------------------------------------------------------------------- */ + /* Set up the current ramp for topping off. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampSetTarget(g_ddi_bc_Configuration.u16ChargingCurrent); + + /* -------------------------------------------------------------------------- */ + /* Move to the Topping Off state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_TOPPING_OFF; + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: now topping off\n"); +#endif + +} + + +/* */ +/* brief Transition to the Broken state. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the transition to the Broken state. */ +/* */ + +static void TransitionToBroken(void) +{ + + /* -------------------------------------------------------------------------- */ + /* Reset the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer = 0; + + /* -------------------------------------------------------------------------- */ + /* Reset the current ramp. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampReset(); + + /* -------------------------------------------------------------------------- */ + /* Move to the Broken state. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_State = DDI_BC_STATE_BROKEN; + + pr_info("charger------ ddi_bc_gBrokenReason=%d\n", + ddi_bc_gBrokenReason); +#ifdef CONFIG_POWER_SUPPLY_DEBUG + printk("Battery charger: declaring a broken battery\n"); +#endif + +} + + +/* */ +/* brief Uninitialized state function. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the Uninitialized state. */ +/* */ + +static ddi_bc_Status_t ddi_bc_Uninitialized(void) +{ + + /* -------------------------------------------------------------------------- */ + /* The first order of business is to update alarms. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampUpdateAlarms(); + + /* -------------------------------------------------------------------------- */ + /* Increment the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod; + + /* -------------------------------------------------------------------------- */ + /* The only way to leave this state is with a call to ddi_bc_Initialize. So, */ + /* calling this state function does nothing. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + +/* */ +/* brief Broken state function. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the Broken state. */ +/* */ + +static ddi_bc_Status_t ddi_bc_Broken(void) +{ + + /* -------------------------------------------------------------------------- */ + /* The first order of business is to update alarms. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampUpdateAlarms(); + + /* -------------------------------------------------------------------------- */ + /* Increment the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod; + + /* -------------------------------------------------------------------------- */ + /* The only way to leave this state is with a call to ddi_bc_SetFixed. So, */ + /* calling this state function does nothing. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + +/* */ +/* brief Disabled state function. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the Disabled state. */ +/* */ + +static ddi_bc_Status_t ddi_bc_Disabled(void) +{ + + /* -------------------------------------------------------------------------- */ + /* The first order of business is to update alarms. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampUpdateAlarms(); + + /* -------------------------------------------------------------------------- */ + /* Increment the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod; + + /* -------------------------------------------------------------------------- */ + /* The only way to leave this state is with a call to ddi_bc_SetEnable. So, */ + /* calling this state function does nothing. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + +/* */ +/* brief Waitin to Charge state function. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the Waiting to Charge state. */ +/* */ + +static ddi_bc_Status_t ddi_bc_WaitingToCharge(void) +{ + uint16_t u16BatteryVoltage; + /* -------------------------------------------------------------------------- */ + /* The first order of business is to update alarms. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampUpdateAlarms(); + + /* -------------------------------------------------------------------------- */ + /* Increment the state timer. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod; + + /* -------------------------------------------------------------------------- */ + /* Check if the power supply is present. If not, we're not going anywhere. */ + /* -------------------------------------------------------------------------- */ + + if (!ddi_bc_hwPowerSupplyIsPresent()) { +#ifdef CONFIG_POWER_SUPPLY_DEBUG + u16ExternalBatteryPowerVoltageCheck = 0; +#endif + return DDI_BC_STATUS_SUCCESS; + } + /* -------------------------------------------------------------------------- */ + /* If control arrives here, we're connected to a power supply. Have a look */ + /* at the battery voltage. */ + /* -------------------------------------------------------------------------- */ + + u16BatteryVoltage = ddi_bc_hwGetBatteryVoltage(); + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + if (u16ExternalBatteryPowerVoltageCheck) { + if ((u16ExternalBatteryPowerVoltageCheck - u16BatteryVoltage) > + 300) { + /* + * If control arrives here, battery voltage has + * dropped too quickly after the first charge + * cycle. We think an external voltage regulator is + * connected. + */ + + ddi_bc_gBrokenReason = + DDI_BC_BROKEN_EXTERNAL_BATTERY_VOLTAGE_DETECTED; + + TransitionToBroken(); + + /* ---------------------------------------------------------------------- */ + /* Tell our caller the battery appears to be broken. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_BROKEN; + } else { + /* reset this check */ + u16ExternalBatteryPowerVoltageCheck = 0; + } + + } +#endif + + + /* -------------------------------------------------------------------------- */ + /* If the battery voltage isn't low, we don't need to be charging it. We */ + /* use a 5% margin to decide. */ + /* -------------------------------------------------------------------------- */ + + if (!bRestartChargeCycle) { + uint16_t x; + + x = u16BatteryVoltage + (u16BatteryVoltage / 20); + + if (x >= g_ddi_bc_Configuration.u16ChargingVoltage) + return DDI_BC_STATUS_SUCCESS; + + } + + bRestartChargeCycle = false; + /* -------------------------------------------------------------------------- */ + /* If control arrives here, the battery is low. How low? */ + /* -------------------------------------------------------------------------- */ + + if (u16BatteryVoltage < + g_ddi_bc_Configuration.u16ConditioningThresholdVoltage) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, the battery is very low and it needs to be */ + /* conditioned. */ + /* ---------------------------------------------------------------------- */ + + TransitionToConditioning(); + + } else { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, the battery isn't too terribly low. */ + /* ---------------------------------------------------------------------- */ + + TransitionToCharging(); + + } + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + +/* */ +/* brief Conditioning state function. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the Conditioning state. */ +/* */ + +static ddi_bc_Status_t ddi_bc_Conditioning(void) +{ + + /* -------------------------------------------------------------------------- */ + /* The first order of business is to update alarms. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampUpdateAlarms(); + + /* -------------------------------------------------------------------------- */ + /* If we're not under an alarm, increment the state timer. */ + /* -------------------------------------------------------------------------- */ + + if (!ddi_bc_RampGetDieTempAlarm() && !ddi_bc_RampGetBatteryTempAlarm()) { + g_ddi_bc_u32StateTimer += + g_ddi_bc_Configuration.u32StateMachinePeriod; + } + /* -------------------------------------------------------------------------- */ + /* Check if the power supply is still around. */ + /* -------------------------------------------------------------------------- */ + + if (!ddi_bc_hwPowerSupplyIsPresent()) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, the power supply has been removed. Go back */ + /* and wait. */ + /* ---------------------------------------------------------------------- */ + + TransitionToWaitingToCharge(); + + /* ---------------------------------------------------------------------- */ + /* Return success. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + + } + + /* -------------------------------------------------------------------------- */ + /* If control arrives here, we're still connected to a power supply. */ + /* Check if a battery is connected. If the voltage rises to high with only */ + /* conditioning charge current, we determine that a battery is not connected. */ + /* If that is not the case and a battery is connected, check */ + /* if the battery voltage indicates it still needs conditioning. */ + /* -------------------------------------------------------------------------- */ + +/* if (ddi_bc_hwGetBatteryVoltage() >= 3900) { */ + if ((ddi_bc_hwGetBatteryVoltage() > + g_ddi_bc_Configuration.u16ConditioningMaxVoltage) && + (ddi_power_GetMaxBatteryChargeCurrent() < + g_ddi_bc_Configuration.u16ConditioningCurrent)) { + /* ---------------------------------------------------------------------- */ + /* If control arrives here, voltage has risen too quickly for so */ + /* little charge being applied so their must be no battery connected. */ + /* ---------------------------------------------------------------------- */ + + ddi_bc_gBrokenReason = DDI_BC_BROKEN_NO_BATTERY_DETECTED; + + TransitionToBroken(); + + /* ---------------------------------------------------------------------- */ + /* Tell our caller the battery appears to be broken. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_BROKEN; + + } + + if (ddi_bc_hwGetBatteryVoltage() >= + g_ddi_bc_Configuration.u16ConditioningMaxVoltage) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, this battery no longer needs conditioning. */ + /* ---------------------------------------------------------------------- */ + + TransitionToCharging(); + + /* ---------------------------------------------------------------------- */ + /* Return success. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + + } + /* -------------------------------------------------------------------------- */ + /* Have we been in this state too long? */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_u32StateTimer >= + g_ddi_bc_Configuration.u32ConditioningTimeout) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, we've been here too long. */ + /* ---------------------------------------------------------------------- */ + + ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT; + + TransitionToBroken(); + + /* ---------------------------------------------------------------------- */ + /* Tell our caller the battery appears to be broken. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_BROKEN; + + } + /* -------------------------------------------------------------------------- */ + /* If control arrives here, we're staying in this state. Step the current */ + /* ramp. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod); + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + +/* */ +/* brief Charging state function. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the Charging state. */ +/* */ + +static ddi_bc_Status_t ddi_bc_Charging(void) +{ + + /* -------------------------------------------------------------------------- */ + /* This variable counts the number of times we've seen the charging status */ + /* bit cleared. */ + /* -------------------------------------------------------------------------- */ + + static int iStatusCount; + /* -------------------------------------------------------------------------- */ + /* The first order of business is to update alarms. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampUpdateAlarms(); + + /* -------------------------------------------------------------------------- */ + /* If we're not under an alarm, increment the state timer. */ + /* -------------------------------------------------------------------------- */ + + if (!ddi_bc_RampGetDieTempAlarm() && !ddi_bc_RampGetBatteryTempAlarm()) { + g_ddi_bc_u32StateTimer += + g_ddi_bc_Configuration.u32StateMachinePeriod; + } + /* Check if the power supply is still around. */ + + + if (!ddi_bc_hwPowerSupplyIsPresent()) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, the power supply has been removed. Go back */ + /* and wait. */ + /* ---------------------------------------------------------------------- */ + + TransitionToWaitingToCharge(); + + /* ---------------------------------------------------------------------- */ + /* Return success. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + + } + /* -------------------------------------------------------------------------- */ + /* If control arrives here, we're still connected to a power supply. We need */ + /* to decide now if the battery is still charging, or if it's nearly full. */ + /* If it's still charging, we'll stay in this state. Otherwise, we'll move */ + /* to the Topping Off state. */ + /* */ + /* Most of the time, we decide that the battery is still charging simply by */ + /* checking if the the actual current flow is above the charging threshold */ + /* current (as indicated by the charge status bit). However, if we're */ + /* still ramping up to full charging current, the hardware may still be set */ + /* to deliver an amount that's less than the threshold. In that case, the */ + /* charging status bit would *definitely* show a low charging current, but */ + /* that doesn't mean the battery is ready for topping off. */ + /* */ + /* So, in summary, we will move to the Topping Off state if both of the */ + /* following are true: */ + /* */ + /* 1) The maximum current set in the hardware is greater than the charging */ + /* threshold. */ + /* -AND- */ + /* 2) The actual current flow is also higher than the threshold (as */ + /* indicated by the charge status bit). */ + /* */ + /* -------------------------------------------------------------------------- */ + + + + ddi_bc_hwSetCurrentThreshold(g_ddi_bc_Configuration. + u16ChargingThresholdCurrent); + + + { + uint16_t u16ActualProgrammedCurrent = ddi_bc_hwGetMaxCurrent(); + + /* ---------------------------------------------------------------------- */ + /* Get the Maximum current that we will ramp to. */ + /* ---------------------------------------------------------------------- */ + + /* ---------------------------------------------------------------------- */ + /* Not all possible values are expressible by the BATTCHRG_I bitfield. */ + /* The following coverts the max current value into the the closest hardware */ + /* expressible bitmask equivalent. Then, it converts this back to the actual */ + /* decimal current value that this bitmask represents. */ + /* ---------------------------------------------------------------------- */ + + uint16_t u16CurrentRampTarget = ddi_bc_RampGetTarget(); + + if (u16CurrentRampTarget > ddi_bc_RampGetLimit()) + u16CurrentRampTarget = ddi_bc_RampGetLimit(); + + /* ---------------------------------------------------------------------- */ + /* Not all possible values are expressible by the BATTCHRG_I bitfield. */ + /* The following coverts the max current value into the the closest hardware */ + /* expressible bitmask equivalent. Then, it converts this back to the actual */ + /* decimal current value that this bitmask represents. */ + /* ---------------------------------------------------------------------- */ + + u16CurrentRampTarget = + ddi_bc_hwExpressibleCurrent(u16CurrentRampTarget); + + /* ---------------------------------------------------------------------- */ + /* We want to wait before we check the charge status bit until the ramping */ + /* up is complete. Because the charge status bit is noisy, we want to */ + /* disregard it until the programmed charge currint in BATTCHRG_I is well */ + /* beyond the STOP_ILIMIT value. */ + /* ---------------------------------------------------------------------- */ + if ((u16ActualProgrammedCurrent >= u16CurrentRampTarget) && + !ddi_bc_hwGetChargeStatus()) { + uint8_t u8IlimitThresholdLimit; + /* ---------------------------------------------------------------------- */ + /* If control arrives here, the hardware flag is telling us that the */ + /* charging current has fallen below the threshold. We need to see this */ + /* happen twice consecutively before we believe it. Increment the count. */ + /* ---------------------------------------------------------------------- */ + + iStatusCount++; + + + u8IlimitThresholdLimit = 10; + + /* ---------------------------------------------------------------------- */ + /* How many times in a row have we seen this status bit low? */ + /* ---------------------------------------------------------------------- */ + + if (iStatusCount >= u8IlimitThresholdLimit) { + + /* + * If control arrives here, we've seen the + * CHRGSTS bit low too many times. This means + * it's time to move to the Topping Off state. + * First, reset the status count for the next + * time we're in this state. + */ + + iStatusCount = 0; + +#ifdef CONFIG_POWER_SUPPLY_DEBUG + u16ExternalBatteryPowerVoltageCheck = + ddi_bc_hwGetBatteryVoltage(); +#endif + + + + /* Move to the Topping Off state */ + + + TransitionToToppingOff(); + + /* ------------------------------------------------------------------ */ + /* Return success. */ + /* ------------------------------------------------------------------ */ + + return DDI_BC_STATUS_SUCCESS; + + } + + } else { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, the battery is still charging. Clear the */ + /* status count. */ + /* ---------------------------------------------------------------------- */ + + iStatusCount = 0; + + } + + } + + /* -------------------------------------------------------------------------- */ + /* Have we been in this state too long? */ + /* -------------------------------------------------------------------------- */ + + if (g_ddi_bc_u32StateTimer >= g_ddi_bc_Configuration.u32ChargingTimeout) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, we've been here too long. */ + /* ---------------------------------------------------------------------- */ + + ddi_bc_gBrokenReason = DDI_BC_BROKEN_CHARGING_TIMEOUT; + + TransitionToBroken(); + + /* ---------------------------------------------------------------------- */ + /* Tell our caller the battery appears to be broken. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_BROKEN; + + } + /* -------------------------------------------------------------------------- */ + /* If control arrives here, we're staying in this state. Step the current */ + /* ramp. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod); + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + +/* */ +/* brief Topping Off state function. */ +/* */ +/* fntype Function */ +/* */ +/* This function implements the Topping Off state. */ +/* */ + +static ddi_bc_Status_t ddi_bc_ToppingOff(void) +{ + + /* -------------------------------------------------------------------------- */ + /* The first order of business is to update alarms. */ + + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampUpdateAlarms(); + + /* -------------------------------------------------------------------------- */ + /* Increment the state timer. Notice that, unlike other states, we increment */ + /* the state timer whether or not we're under an alarm. */ + /* -------------------------------------------------------------------------- */ + + g_ddi_bc_u32StateTimer += g_ddi_bc_Configuration.u32StateMachinePeriod; + + /* -------------------------------------------------------------------------- */ + /* Check if the power supply is still around. */ + /* -------------------------------------------------------------------------- */ + + if (!ddi_bc_hwPowerSupplyIsPresent()) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, the power supply has been removed. Go back */ + /* and wait. */ + /* --------------------------------------------------------------------- */ + + TransitionToWaitingToCharge(); + + /* ---------------------------------------------------------------------- */ + /* Return success. */ + /* ---------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + + } + + /* -------------------------------------------------------------------------- */ + /* Are we done topping off? */ + /* -------------------------------------------------------------------------- */ + if (g_ddi_bc_u32StateTimer >= g_ddi_bc_Configuration.u32TopOffPeriod) { + + /* ---------------------------------------------------------------------- */ + /* If control arrives here, we're done topping off. */ + /* ---------------------------------------------------------------------- */ + + TransitionToWaitingToCharge(); + + } + /* -------------------------------------------------------------------------- */ + /* If control arrives here, we're staying in this state. Step the current */ + /* ramp. */ + /* -------------------------------------------------------------------------- */ + + ddi_bc_RampStep(g_ddi_bc_Configuration.u32StateMachinePeriod); + + /* -------------------------------------------------------------------------- */ + /* Return success. */ + /* -------------------------------------------------------------------------- */ + + return DDI_BC_STATUS_SUCCESS; + +} + + +/* End of file */ + +/* @} */ diff --git a/drivers/power/mxs/ddi_bc_sm.h b/drivers/power/mxs/ddi_bc_sm.h new file mode 100644 index 000000000000..40bd4a494fb3 --- /dev/null +++ b/drivers/power/mxs/ddi_bc_sm.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/* addtogroup ddi_bc */ +/* @{ */ +/* */ +/* Copyright (c) 2004-2005 SigmaTel, Inc. */ +/* */ +/* file ddi_bc_sm.h */ +/* brief Header file for the Battery Charger state machine. */ +/* date 06/2005 */ +/* */ +/* This file contains declarations for the Battery Charger state machine. */ + + +#ifndef _DDI_BC_SM_H +#define _DDI_BC_SM_H + + +/* Externs */ + + +/* The current state. */ + +extern ddi_bc_State_t g_ddi_bc_State; + +/* The state function table. */ + +extern ddi_bc_Status_t(*const (stateFunctionTable[])) (void); + + +/* End of file */ + +#endif /* _DDI_BC_H */ +/* @} */ diff --git a/drivers/power/mxs/ddi_power_battery.c b/drivers/power/mxs/ddi_power_battery.c new file mode 100644 index 000000000000..762f29bd784e --- /dev/null +++ b/drivers/power/mxs/ddi_power_battery.c @@ -0,0 +1,1908 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +/* addtogroup ddi_power */ +/* @{ */ +/* */ +/* Copyright(C) 2005 SigmaTel, Inc. */ +/* */ +/* file ddi_power_battery.c */ +/* brief Implementation file for the power driver battery charger. */ +/* */ + +/* Includes and external references */ + +#include +#include +#include +#include +#include /* cpu_relax */ +#include +#include +#include +#include +#include +#include +#include "ddi_bc_internal.h" + +/* brief Base voltage to start battery calculations for LiIon */ +#define BATT_BRWNOUT_LIION_BASE_MV 2800 +/* brief Constant to help with determining whether to round up or */ +/* not during calculation */ +#define BATT_BRWNOUT_LIION_CEILING_OFFSET_MV 39 +/* brief Number of mV to add if rounding up in LiIon mode */ +#define BATT_BRWNOUT_LIION_LEVEL_STEP_MV 40 +/* brief Constant value to be calculated by preprocessing */ +#define BATT_BRWNOUT_LIION_EQN_CONST \ + (BATT_BRWNOUT_LIION_BASE_MV - BATT_BRWNOUT_LIION_CEILING_OFFSET_MV) +/* brief Base voltage to start battery calculations for Alkaline/NiMH */ +#define BATT_BRWNOUT_ALKAL_BASE_MV 800 +/* brief Constant to help with determining whether to round up or */ +/* not during calculation */ +#define BATT_BRWNOUT_ALKAL_CEILING_OFFSET_MV 19 +/* brief Number of mV to add if rounding up in Alkaline/NiMH mode */ +#define BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV 20 +/* brief Constant value to be calculated by preprocessing */ +#define BATT_BRWNOUT_ALKAL_EQN_CONST \ + (BATT_BRWNOUT_ALKAL_BASE_MV - BATT_BRWNOUT_ALKAL_CEILING_OFFSET_MV) + +#define GAIN_CORRECTION 1012 /* 1.012 */ + +#define VBUSVALID_THRESH_2_90V 0x0 +#define VBUSVALID_THRESH_4_00V 0x1 +#define VBUSVALID_THRESH_4_10V 0x2 +#define VBUSVALID_THRESH_4_20V 0x3 +#define VBUSVALID_THRESH_4_30V 0x4 +#define VBUSVALID_THRESH_4_40V 0x5 +#define VBUSVALID_THRESH_4_50V 0x6 +#define VBUSVALID_THRESH_4_60V 0x7 + +#define LINREG_OFFSET_STEP_BELOW 0x2 +#define BP_POWER_BATTMONITOR_BATT_VAL 16 +#define BP_POWER_CHARGE_BATTCHRG_I 0 +#define BP_POWER_CHARGE_STOP_ILIMIT 8 + +#define VDD4P2_ENABLED + +#define DDI_POWER_BATTERY_XFER_THRESHOLD_MV 3200 + + +#ifndef BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV +#define BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV 4000 +#endif + +#ifndef BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV +#define BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV 3800 +#endif + +/* #define DEBUG_IRQS */ + +/* to be re-enabled once FIQ functionality is added */ +#define DISABLE_VDDIO_BO_PROTECTION + +#ifdef CONFIG_ARCH_MX28 +#define BM_POWER_STS_VBUSVALID BM_POWER_STS_VBUSVALID0 +#endif + +/* Globals & Variables */ + + + +/* Select your 5V Detection method */ + +static ddi_power_5vDetection_t DetectionMethod = + DDI_POWER_5V_VDD5V_GT_VDDIO; +/* static ddi_power_5vDetection_t DetectionMethod = DDI_POWER_5V_VBUSVALID; */ + + +/* Code */ + + +#if 0 +static void dump_regs(void) +{ + printk("HW_POWER_CHARGE 0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE)); + printk("HW_POWER_STS 0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_STS)); + printk("HW_POWER_BATTMONITOR 0x%08x\n", __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR)); +} +#endif + +/* This array maps bit numbers to current increments, as used in the register */ +/* fields HW_POWER_CHARGE.STOP_ILIMIT and HW_POWER_CHARGE.BATTCHRG_I. */ +static const uint16_t currentPerBit[] = { 10, 20, 50, 100, 200, 400 }; + +uint16_t ddi_power_convert_current_to_setting(uint16_t u16Current) +{ + int i; + uint16_t u16Mask; + uint16_t u16Setting = 0; + + /* Scan across the bit field, adding in current increments. */ + u16Mask = (0x1 << 5); + + for (i = 5; (i >= 0) && (u16Current > 0); i--, u16Mask >>= 1) { + if (u16Current >= currentPerBit[i]) { + u16Current -= currentPerBit[i]; + u16Setting |= u16Mask; + } + } + + /* Return the result. */ + return u16Setting; +} + + +/* See hw_power.h for details. */ + +uint16_t ddi_power_convert_setting_to_current(uint16_t u16Setting) +{ + int i; + uint16_t u16Mask; + uint16_t u16Current = 0; + + /* Scan across the bit field, adding in current increments. */ + u16Mask = (0x1 << 5); + + for (i = 5; i >= 0; i--, u16Mask >>= 1) { + if (u16Setting & u16Mask) + u16Current += currentPerBit[i]; + } + + /* Return the result. */ + return u16Current; +} + +void ddi_power_Enable5vDetection(void) +{ + u32 val; + /* Disable hardware power down when 5V is inserted or removed */ + __raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + /* Enabling VBUSVALID hardware detection even if VDD5V_GT_VDDIO + * is the detection method being used for 5V status (hardware + * or software). This is in case any other drivers (such as + * USB) are specifically monitoring VBUSVALID status + */ + __raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); + + /* Set 5V detection threshold to 4.3V for VBUSVALID. */ + __raw_writel( + BF_POWER_5VCTRL_VBUSVALID_TRSH(VBUSVALID_THRESH_4_30V), + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); + + /* gotta set LINREG_OFFSET to STEP_BELOW according to manual */ + val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + val &= ~(BM_POWER_VDDIOCTRL_LINREG_OFFSET); + val |= BF_POWER_VDDIOCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW); + __raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + + val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL); + val &= ~(BM_POWER_VDDACTRL_LINREG_OFFSET); + val |= BF_POWER_VDDACTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW); + __raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDACTRL); + + val = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL); + val &= ~(BM_POWER_VDDDCTRL_LINREG_OFFSET); + val |= BF_POWER_VDDDCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW); + __raw_writel(val, REGS_POWER_BASE + HW_POWER_VDDDCTRL); + + /* Clear vbusvalid interrupt flag */ + __raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + /* enable vbusvalid irq */ + + + /* enable 5V Detection interrupt vbusvalid irq */ + switch (DetectionMethod) { + case DDI_POWER_5V_VBUSVALID: + /* Check VBUSVALID for 5V present */ + __raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + break; + case DDI_POWER_5V_VDD5V_GT_VDDIO: + /* Check VDD5V_GT_VDDIO for 5V present */ + __raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + break; + } +} + +/* + * This function prepares the hardware for a 5V-to-battery handoff. It assumes + * the current configuration is using 5V as the power source. The 5V + * interrupt will be set up for a 5V removal. + */ +void ddi_power_enable_5v_to_battery_handoff(void) +{ + /* Clear vbusvalid interrupt flag */ + __raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + /* detect 5v unplug */ + __raw_writel(BM_POWER_CTRL_POLARITY_VBUSVALID, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + +#ifndef VDD4P2_ENABLED + /* Enable automatic transition to DCDC */ + __raw_writel(BM_POWER_5VCTRL_DCDC_XFER, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); +#endif +} + +/* + * This function will handle all the power rail transitions necesarry to power + * the chip from the battery when it was previously powered from the 5V power + * source. + */ +void ddi_power_execute_5v_to_battery_handoff(void) +{ + int val; +#ifdef VDD4P2_ENABLED + val = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2); + val &= ~(BM_POWER_DCDC4P2_ENABLE_DCDC | BM_POWER_DCDC4P2_ENABLE_4P2); + __raw_writel(val, REGS_POWER_BASE + HW_POWER_DCDC4P2); + + __raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); + + /* make VBUSVALID_TRSH 4400mV and set PWD_CHARGE_4P2 */ + __raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + __raw_writel(BF_POWER_5VCTRL_VBUSVALID_TRSH(VBUSVALID_THRESH_4_40V), + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); + +#else + /* VDDD has different configurations depending on the battery type */ + /* and battery level. */ + + /* For LiIon battery, we will use the DCDC to power VDDD. */ + /* Use LinReg offset for DCDC mode. */ + __raw_writel(BF_POWER_VDDDCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW), + HW_POWER_BASE + HW_POWER_VDDDCTRL_SET); + /* Turn on the VDDD DCDC output and turn off the VDDD LinReg output. */ + __raw_writel(BM_POWER_VDDDCTRL_DISABLE_FET, + HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR); + + __raw_writel(BM_POWER_VDDDCTRL_ENABLE_LINREG, + HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR); + /* Make sure stepping is enabled when using DCDC. */ + __raw_writel(BM_POWER_VDDDCTRL_DISABLE_STEPPING, + HW_POWER_BASE + HW_POWER_VDDDCTRL_CLR); + + /* Power VDDA and VDDIO from the DCDC. */ + + /* Use LinReg offset for DCDC mode. */ + __raw_writel(BF_POWER_VDDACTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW), + HW_POWER_BASE + HW_POWER_VDDACTRL_SET); + /* Turn on the VDDA DCDC converter output and turn off LinReg output. */ + __raw_writel(BM_POWER_VDDACTRL_DISABLE_FET, + HW_POWER_BASE + HW_POWER_VDDACTRL_CLR); + __raw_writel(BM_POWER_VDDACTRL_ENABLE_LINREG, + HW_POWER_BASE + HW_POWER_VDDACTRL_CLR); + + /* Make sure stepping is enabled when using DCDC. */ + __raw_writel(BM_POWER_VDDACTRL_DISABLE_STEPPING, + HW_POWER_BASE + HW_POWER_VDDACTRL_CLR); + + /* Use LinReg offset for DCDC mode. */ + __raw_writel(BF_POWER_VDDIOCTRL_LINREG_OFFSET( + LINREG_OFFSET_STEP_BELOW + ), + HW_POWER_BASE + HW_POWER_VDDIOCTRL_SET); + + /* Turn on the VDDIO DCDC output and turn on the LinReg output.*/ + __raw_writel(BM_POWER_VDDIOCTRL_DISABLE_FET, + HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR); + + __raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO, + HW_POWER_BASE + HW_POWER_5VCTRL_CLR_CLR); + + /* Make sure stepping is enabled when using DCDC. */ + __raw_writel(BM_POWER_VDDIOCTRL_DISABLE_STEPPING, + HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR); +#endif + +} + +/* + * This function sets up battery-to-5V handoff. The power switch from + * battery to 5V is automatic. This funtion enables the 5V present detection + * such that the 5V interrupt can be generated if it is enabled. (The interrupt + * handler can inform software the 5V present event.) To deal with noise or + * a high current, this function enables DCDC1/2 based on the battery mode. + */ +void ddi_power_enable_battery_to_5v_handoff(void) +{ + /* Clear vbusvalid interrupt flag */ + __raw_writel(BM_POWER_CTRL_VBUSVALID_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + /* detect 5v plug-in */ + __raw_writel(BM_POWER_CTRL_POLARITY_VBUSVALID, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + __raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + +#ifndef VDD4P2_ENABLED + /* Force current from 5V to be zero by disabling its entry source. */ + __raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); +#endif + /* Allow DCDC be to active when 5V is present. */ + __raw_writel(BM_POWER_5VCTRL_ENABLE_DCDC, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); +} + +/* This function handles the transitions on each of theVDD5V_GT_VDDIO power + * rails necessary to power the chip from the 5V power supply when it was + * previously powered from the battery power supply. + */ +void ddi_power_execute_battery_to_5v_handoff(void) +{ + +#ifdef VDD4P2_ENABLED + ddi_power_Enable4p2(450); +#else + /* Disable the DCDC during 5V connections. */ + __raw_writel(BM_POWER_5VCTRL_ENABLE_DCDC, + HW_POWER_BAE + HW_POWER_5VCTRL_CLR); + + /* Power the VDDD/VDDA/VDDIO rail from the linear regulator. The DCDC */ + /* is ready to automatically power the chip when 5V is removed. */ + /* Use this configuration when powering from 5V */ + + /* Use LinReg offset for LinReg mode */ + __raw_writel(BF_POWER_VDDDCTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW), + HW_POWER_BAE + HW_POWER_VDDDCTRL_SET); + + /* Turn on the VDDD LinReg and turn on the VDDD DCDC output. The */ + /* ENABLE_DCDC must be cleared to avoid LinReg and DCDC conflict. */ + __raw_writel(BM_POWER_VDDDCTRL_ENABLE_LINREG, + HW_POWER_BAE + HW_POWER_VDDDCTRL_SET); + __raw_writel(BM_POWER_VDDDCTRL_DISABLE_FET, + HW_POWER_BAE + HW_POWER_VDDDCTRL_CLR); + + /* Make sure stepping is disabled when using linear regulators */ + __raw_writel(BM_POWER_VDDDCTRL_DISABLE_STEPPING, + HW_POWER_BAE + HW_POWER_VDDDCTRL_SET); + + /* Use LinReg offset for LinReg mode */ + __raw_writel(BM_POWER_VDDACTRL_LINREG_OFFSET(LINREG_OFFSET_STEP_BELOW), + HW_POWER_BAE + HW_POWER_VDDACTRL_SET); + + + /* Turn on the VDDA LinReg output and prepare the DCDC for transfer. */ + /* ENABLE_DCDC must be clear to avoid DCDC and LinReg conflict. */ + stmp3xxx_set(BM_POWER_VDDACTRL_ENABLE_LINREG, + HW_POWER_BASE + HW_POWER_VDDACTRL_SET); + __raw_writel(BM_POWER_VDDACTRL_DISABLE_FET, + HW_POWER_BASE + HW_POWER_VDDACTRL_CLR); + + /* Make sure stepping is disabled when using linear regulators */ + __raw_writel(BM_POWER_VDDACTRL_DISABLE_STEPPING, + HW_POWER_BASE + HW_POWER_VDDACTRL_SET); + + /* Use LinReg offset for LinReg mode. */ + __raw_writel(BF_POWER_VDDIOCTRL_LINREG_OFFSET( + LINREG_OFFSET_STEP_BELOW), + HW_POWER_BASE + HW_POWER_VDDIOCTRL_SET); + + /* Turn on the VDDIO LinReg output and prepare the VDDIO DCDC output. */ + /* ENABLE_DCDC must be cleared to prevent DCDC and LinReg conflict. */ + __raw_writel(BM_POWER_VDDIOCTRL_DISABLE_FET, + HW_POWER_BASE + HW_POWER_VDDIOCTRL_CLR); + __raw_writel(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + /* Make sure stepping is disabled when using DCDC. */ + __raw_writel(BM_POWER_VDDIOCTRL_DISABLE_STEPPING, + REGS_POWER_BASE + HW_POWER_VDDIOCTRL_SET); +#endif +} + + +void ddi_power_Start4p2Dcdc(bool battery_ready) +{ + uint32_t temp_reg, old_values; + bool vdda_pwdn = false, vddd_pwdn = false, vddio_pwdn = false; + +#ifndef CONFIG_ARCH_MX28 + /* set vbusvalid threshold to 2.9V because of errata */ + __raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); +#endif + +#if 0 + if (battery_ready) + ddi_power_EnableBatteryIrq(); + else + enable_4p2_fiq_shutdown(); +#endif + + /* enable hardware shutdown on battery brownout */ + __raw_writel( + BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT | + __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR), + REGS_POWER_BASE + HW_POWER_BATTMONITOR); + + /* set VBUS DROOP threshold to 4.3V */ + __raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + /* turn of vbus valid detection. Part of errate + * workaround. */ + __raw_writel(BM_POWER_5VCTRL_PWRUP_VBUS_CMPS, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); + + __raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + if (__raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) + & BM_POWER_VDDIOCTRL_PWDN_BRNOUT) + vddio_pwdn = true; + + if (__raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL) + & BM_POWER_VDDDCTRL_PWDN_BRNOUT) + vddd_pwdn = true; + + if (__raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL) + & BM_POWER_VDDACTRL_PWDN_BRNOUT) + vdda_pwdn = true; + + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL) + & (~BM_POWER_VDDACTRL_PWDN_BRNOUT), + REGS_POWER_BASE + HW_POWER_VDDACTRL); + + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL) + & (~BM_POWER_VDDDCTRL_PWDN_BRNOUT), + REGS_POWER_BASE + HW_POWER_VDDDCTRL); + + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) + & (~BM_POWER_VDDIOCTRL_PWDN_BRNOUT), + REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) + & BM_POWER_STS_VDDIO_BO) == 0) + __raw_writel(BM_POWER_CTRL_VDDIO_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) + & BM_POWER_STS_VDDD_BO) == 0) + __raw_writel(BM_POWER_CTRL_VDDD_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) + & BM_POWER_STS_VDDA_BO) == 0) + __raw_writel(BM_POWER_CTRL_VDDA_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + temp_reg = (BM_POWER_CTRL_ENIRQ_VDDD_BO | + BM_POWER_CTRL_ENIRQ_VDDA_BO | + BM_POWER_CTRL_ENIRQ_VDDIO_BO | + BM_POWER_CTRL_ENIRQ_VDD5V_DROOP | + BM_POWER_CTRL_ENIRQ_VBUS_VALID); + + /* save off old brownout enable values */ + old_values = __raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + temp_reg; + + /* disable irqs affected by errata */ + __raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + /* Enable DCDC from 4P2 */ + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2) | + BM_POWER_DCDC4P2_ENABLE_DCDC, + REGS_POWER_BASE + HW_POWER_DCDC4P2); + + /* give a delay to check for errate noise problem */ + mdelay(1); + + temp_reg = (BM_POWER_CTRL_VDDD_BO_IRQ | + BM_POWER_CTRL_VDDA_BO_IRQ | + BM_POWER_CTRL_VDDIO_BO_IRQ | + BM_POWER_CTRL_VDD5V_DROOP_IRQ | + BM_POWER_CTRL_VBUSVALID_IRQ); + + __raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_CTRL_CLR); + /* stay in this loop until the false brownout indciations + * no longer occur or until 5V actually goes away + */ + while ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & temp_reg) && + !(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ)) { + __raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + mdelay(1); + } + /* revert to previous enable irq values */ + __raw_writel(old_values, REGS_POWER_BASE + HW_POWER_CTRL_SET); + + if (vdda_pwdn) + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL) + | BM_POWER_VDDACTRL_PWDN_BRNOUT, + REGS_POWER_BASE + HW_POWER_VDDACTRL); + + if (vddd_pwdn) + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL) + | BM_POWER_VDDDCTRL_PWDN_BRNOUT, + REGS_POWER_BASE + HW_POWER_VDDDCTRL); + + if (vddio_pwdn) + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) + | BM_POWER_VDDIOCTRL_PWDN_BRNOUT, + REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + + if (DetectionMethod == DDI_POWER_5V_VBUSVALID) + __raw_writel(BM_POWER_5VCTRL_VBUSVALID_5VDETECT, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); +} + + +/* set the optimal CMPTRIP for the best possible 5V + * disconnection handling but without drawing power + * from the power on a stable 4p2 rails (at 4.2V). + */ +void ddi_power_handle_cmptrip(void) +{ + enum ddi_power_5v_status pmu_5v_status; + uint32_t temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2); + temp &= ~(BM_POWER_DCDC4P2_CMPTRIP); + + pmu_5v_status = ddi_power_GetPmu5vStatus(); + + /* CMPTRIP should remain at 31 when 5v is disconnected + * or 5v is connected but hasn't been handled yet + */ + if (pmu_5v_status != existing_5v_connection) + temp |= (31 << BP_POWER_DCDC4P2_CMPTRIP); + else if (ddi_power_GetBattery() > + BATTERY_VOLTAGE_CMPTRIP100_THRESHOLD_MV) + temp |= (1 << BP_POWER_DCDC4P2_CMPTRIP); + else if (ddi_power_GetBattery() > + BATTERY_VOLTAGE_CMPTRIP105_THRESHOLD_MV) + temp |= (24 << BP_POWER_DCDC4P2_CMPTRIP); + else + temp |= (31 << BP_POWER_DCDC4P2_CMPTRIP); + + + __raw_writel(temp, REGS_POWER_BASE + HW_POWER_DCDC4P2); +} + +void ddi_power_Init4p2Params(void) +{ + uint32_t temp; + + ddi_power_handle_cmptrip(); + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2); + + /* DROPOUT CTRL to 10, TRG to 0 */ + temp &= ~(BM_POWER_DCDC4P2_TRG | BM_POWER_DCDC4P2_DROPOUT_CTRL); + temp |= (0xa << BP_POWER_DCDC4P2_DROPOUT_CTRL); + + __raw_writel(temp, REGS_POWER_BASE + HW_POWER_DCDC4P2); + + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL); + + /* HEADROOM_ADJ to 4, CHARGE_4P2_ILIMIT to 0 */ + temp &= ~(BM_POWER_5VCTRL_HEADROOM_ADJ | + BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT); + temp |= (4 << BP_POWER_5VCTRL_HEADROOM_ADJ); + +} + +bool ddi_power_IsBattRdyForXfer(void) +{ + uint16_t u16BatteryVoltage = ddi_power_GetBattery(); + + if (u16BatteryVoltage > DDI_POWER_BATTERY_XFER_THRESHOLD_MV) + return true; + else + return false; +} + +void ddi_power_EnableVbusDroopIrq(void) +{ + + __raw_writel(BM_POWER_CTRL_VDD5V_DROOP_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + __raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + +} + + +void ddi_power_Enable4p2(uint16_t target_current_limit_ma) +{ + + uint16_t u16BatteryVoltage; + uint32_t temp_reg; + + ddi_power_Init4p2Params(); + /* disable 4p2 rail brownouts for now. (they + * should have already been off at this point) */ + __raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + u16BatteryVoltage = ddi_power_GetBattery(); + + if (ddi_power_IsBattRdyForXfer()) { + + /* PWD_CHARGE_4P2 should already be set but just in case... */ + __raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); + + /* set CMPTRIP to DCDC_4P2 pin >= BATTERY pin */ + temp_reg = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2); + temp_reg &= ~(BM_POWER_DCDC4P2_CMPTRIP); + temp_reg |= (31 << BP_POWER_DCDC4P2_CMPTRIP); + __raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_DCDC4P2); + + /* since we have a good battery, we can go ahead + * and turn on the Dcdcing from the 4p2 source. + * This is helpful in working around the chip + * errata. + */ + ddi_power_Start4p2Dcdc(true); + + /* Enable VbusDroopIrq to handle errata */ + + /* set vbus droop detection level to 4.3V */ + __raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + ddi_power_EnableVbusDroopIrq(); + /* now that the DCDC4P2 problems are cleared, + * turn on and ramp up the 4p2 regulator + */ + temp_reg = ddi_power_BringUp4p2Regulator( + target_current_limit_ma, true); + + /* if we still have our 5V connection, we can disable + * battery brownout interrupt. This is because the + * VDD5V DROOP IRQ handler will also shutdown if battery + * is browned out and it will enable the battery brownout + * and bring VBUSVALID_TRSH level back to a normal level + * which caused the hardware battery brownout shutdown + * to be enabled. The benefit of this is that device + * that have detachable batteries (or devices going through + * the assembly line and running this firmware to test + * with) can avoid shutting down if 5V is present and + * battery voltage goes away. + */ + if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + (BM_POWER_CTRL_VBUSVALID_IRQ | + BM_POWER_CTRL_VDD5V_DROOP_IRQ))) { + ddi_power_EnableBatteryBoInterrupt(false); + } + + + + printk(KERN_DEBUG "4P2 rail started. 5V current limit\ + set to %dmA\n", temp_reg); + + } else { + + printk(KERN_ERR "4P2 rail was attempted to be started \ + from a system\ + with a very low battery voltage. This is not\ + yet handled by the kernel driver, only by the\ + bootlets. Remaining on battery power.\n"); + + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) && + BM_POWER_5VCTRL_ENABLE_DCDC)) + ddi_power_EnableBatteryBoInterrupt(true); + +#if 0 + /* enable hardware shutdown (if 5v disconnected) + * on battery brownout */ + __raw_writel( + BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT | + __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR), + REGS_POWER_BASE + HW_POWER_BATTMONITOR); + + /* turn on and ramp up the 4p2 regulator */ + temp_reg = ddi_power_BringUp4p2Regulator( + target_current_limit_ma, false); + + Configure4p2FiqShutdown(); + + SetVbusValidThresh(0); +#endif + } + +} + +/* enable and ramp up 4p2 regulator */ +uint16_t ddi_power_BringUp4p2Regulator( + uint16_t target_current_limit_ma, + bool b4p2_dcdc_enabled) +{ + uint32_t temp_reg; + uint16_t charge_4p2_ilimit = 0; + + /* initial current limit to 0 */ + __raw_writel(BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2) | + BM_POWER_DCDC4P2_ENABLE_4P2, + REGS_POWER_BASE + HW_POWER_DCDC4P2); + + /* set 4p2 target voltage to zero */ + temp_reg = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2); + temp_reg &= (~BM_POWER_DCDC4P2_TRG); + __raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_DCDC4P2); + + /* Enable 4P2 regulator*/ + __raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + if (target_current_limit_ma > 780) + target_current_limit_ma = 780; + + ddi_power_Set4p2BoLevel(4150); + + /* possibly not necessary but recommended for unloaded + * 4p2 rail + */ + __raw_writel(BM_POWER_CHARGE_ENABLE_LOAD, + REGS_POWER_BASE + HW_POWER_CHARGE_SET); + + while (charge_4p2_ilimit < target_current_limit_ma) { + + if (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + (BM_POWER_CTRL_VBUSVALID_IRQ | + BM_POWER_CTRL_VDD5V_DROOP_IRQ)) + break; + + + charge_4p2_ilimit += 100; + if (charge_4p2_ilimit > target_current_limit_ma) + charge_4p2_ilimit = target_current_limit_ma; + + ddi_power_set_4p2_ilimit(charge_4p2_ilimit); + + /* dcdc4p2 enable_dcdc must be enabled for + * 4p2 bo indication to function. If not enabled, + * skip using bo level detection + */ + if (!(b4p2_dcdc_enabled)) + msleep(1); + else if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BM_POWER_STS_DCDC_4P2_BO) + msleep(1); + else { + charge_4p2_ilimit = target_current_limit_ma; + ddi_power_set_4p2_ilimit(charge_4p2_ilimit); + } + } + + ddi_power_Set4p2BoLevel(3600); + + __raw_writel(BM_POWER_CTRL_DCDC4P2_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + /* rail should now be up and loaded. Extra + * internal load is not necessary. + */ + __raw_writel(BM_POWER_CHARGE_ENABLE_LOAD, + REGS_POWER_BASE + HW_POWER_CHARGE_CLR); + + return charge_4p2_ilimit; + +} + + +void ddi_power_Set4p2BoLevel(uint16_t bo_voltage_mv) +{ + uint16_t bo_reg_value; + uint32_t temp; + + if (bo_voltage_mv < 3600) + bo_voltage_mv = 3600; + else if (bo_voltage_mv > 4375) + bo_voltage_mv = 4375; + + bo_reg_value = (bo_voltage_mv - 3600) / 25; + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2); + temp &= (~BM_POWER_DCDC4P2_BO); + temp |= (bo_reg_value << BP_POWER_DCDC4P2_BO); + __raw_writel(temp, REGS_POWER_BASE + HW_POWER_DCDC4P2); +} + + + +void ddi_power_init_handoff(void) +{ + int val; + /* The following settings give optimal power supply capability */ + + /* enable 5v presence detection */ + ddi_power_Enable5vDetection(); + + if (ddi_power_Get5vPresentFlag()) + /* It's 5V mode, enable 5V-to-battery handoff */ + ddi_power_enable_5v_to_battery_handoff(); + else + /* It's battery mode, enable battery-to-5V handoff */ + ddi_power_enable_battery_to_5v_handoff(); + + /* Finally enable the battery adjust */ + val = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR); + val |= BM_POWER_BATTMONITOR_EN_BATADJ; + __raw_writel(val, REGS_POWER_BASE + HW_POWER_BATTMONITOR); +} + + +void ddi_power_EnableBatteryInterrupt(bool enable) +{ + + __raw_writel(BM_POWER_CTRL_BATT_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + __raw_writel(BM_POWER_CTRL_ENIRQBATT_BO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + +} + + +#define REGS_LRADC_BASE IO_ADDRESS(LRADC_PHYS_ADDR) + +int ddi_power_init_battery(void) +{ + + int ret = 0; + + if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) && + BM_POWER_5VCTRL_ENABLE_DCDC)) { + printk(KERN_ERR "WARNING: Power Supply not\ + initialized correctly by \ + pre-kernel bootlets. HW_POWER_5VCTRL \ + ENABLE_DCDC should already be set. Kernel \ + power driver behavior may not be reliable \n"); + ret = 1; + } + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR) & + BM_POWER_BATTMONITOR_BATT_VAL) == 0) { + ret = 1; + printk(KERN_INFO "WARNING : No battery connected !\r\n"); + return ret; + } + + /* the following code to enable automatic battery measurement + * should have already been enabled in the boot prep files. Not + * sure if this is necessary or possibly susceptible to + * mis-coordination + */ + + + ret = !hw_lradc_present(BATTERY_VOLTAGE_CH); + + if (ret) { + printk(KERN_ERR "%s: hw_lradc_present failed\n", __func__); + return -ENODEV; + } else { + uint16_t wait_time = 0; + + hw_lradc_configure_channel(BATTERY_VOLTAGE_CH, 0 /* div2 */ , + 0 /* acc */ , + 0 /* num_samples */); + + /* Setup the trigger loop forever */ + hw_lradc_set_delay_trigger(LRADC_DELAY_TRIGGER_BATTERY, + 1 << BATTERY_VOLTAGE_CH, + 1 << LRADC_DELAY_TRIGGER_BATTERY, + 0, 200); + + /* Clear the accumulator & NUM_SAMPLES */ + __raw_writel(0xFFFFFFFF, + REGS_LRADC_BASE + HW_LRADC_CHn_CLR(BATTERY_VOLTAGE_CH)); + + /* clear previous "measurement performed" status */ + __raw_writel(1 << BATTERY_VOLTAGE_CH, + REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR); + + /* set to LiIon scale factor */ + __raw_writel(BM_LRADC_CONVERSION_SCALE_FACTOR, + REGS_LRADC_BASE + HW_LRADC_CONVERSION_SET); + + /* kick off the trigger */ + hw_lradc_set_delay_trigger_kick( + LRADC_DELAY_TRIGGER_BATTERY, 1); + + + /* wait for 1st converstion to be complete before + * enabling automatic copy to power supply + * peripheral + */ + while (!(__raw_readl(REGS_LRADC_BASE + HW_LRADC_CTRL1) & + 1 << BATTERY_VOLTAGE_CH) && + (wait_time < 10)) { + wait_time++; + mdelay(1); + } + + __raw_writel(BM_LRADC_CONVERSION_AUTOMATIC, + REGS_LRADC_BASE + HW_LRADC_CONVERSION_SET); +#ifdef CONFIG_ARCH_MX28 + /* workaround for mx28 lradc result incorrect in the + first several ms */ + for (wait_time = 0; wait_time < 20; wait_time++) + if (ddi_bc_hwGetBatteryVoltage() < 1000) { + pr_info("ddi_bc_hwGetBatteryVoltage=%u\n", + ddi_bc_hwGetBatteryVoltage()); + mdelay(100); + } else + break; +#endif + } + +#ifndef VDD4P2_ENABLED + /* prepare handoff */ + ddi_power_init_handoff(); +#endif + return ret; +} + +/* + * Use the the lradc channel + * get the die temperature from on-chip sensor. + */ +uint16_t MeasureInternalDieTemperature(void) +{ + uint32_t ch8Value, ch9Value, lradc_irq_mask, channel; + + channel = g_ddi_bc_Configuration.u8BatteryTempChannel; + lradc_irq_mask = 1 << channel; + + /* power up internal tep sensor block */ + __raw_writel(BM_LRADC_CTRL2_TEMPSENSE_PWD, + REGS_LRADC_BASE + HW_LRADC_CTRL2_CLR); + + /* mux to the lradc 8th temp channel */ + __raw_writel((0xF << (4 * channel)), + REGS_LRADC_BASE + HW_LRADC_CTRL4_CLR); + __raw_writel((8 << (4 * channel)), + REGS_LRADC_BASE + HW_LRADC_CTRL4_SET); + + /* Clear the interrupt flag */ + __raw_writel(lradc_irq_mask, + REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR); + __raw_writel(BF_LRADC_CTRL0_SCHEDULE(1 << channel), + REGS_LRADC_BASE + HW_LRADC_CTRL0_SET); + + /* Wait for conversion complete*/ + while (!(__raw_readl(REGS_LRADC_BASE + HW_LRADC_CTRL1) + & lradc_irq_mask)) + cpu_relax(); + + /* Clear the interrupt flag again */ + __raw_writel(lradc_irq_mask, + REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR); + + /* read temperature value and clr lradc */ + ch8Value = __raw_readl(REGS_LRADC_BASE + + HW_LRADC_CHn(channel)) & BM_LRADC_CHn_VALUE; + + + __raw_writel(BM_LRADC_CHn_VALUE, + REGS_LRADC_BASE + HW_LRADC_CHn_CLR(channel)); + + /* mux to the lradc 9th temp channel */ + __raw_writel((0xF << (4 * channel)), + REGS_LRADC_BASE + HW_LRADC_CTRL4_CLR); + __raw_writel((9 << (4 * channel)), + REGS_LRADC_BASE + HW_LRADC_CTRL4_SET); + + /* Clear the interrupt flag */ + __raw_writel(lradc_irq_mask, + REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR); + __raw_writel(BF_LRADC_CTRL0_SCHEDULE(1 << channel), + REGS_LRADC_BASE + HW_LRADC_CTRL0_SET); + /* Wait for conversion complete */ + while (!(__raw_readl(REGS_LRADC_BASE + HW_LRADC_CTRL1) + & lradc_irq_mask)) + cpu_relax(); + + /* Clear the interrupt flag */ + __raw_writel(lradc_irq_mask, + REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR); + /* read temperature value */ + ch9Value = __raw_readl( + REGS_LRADC_BASE + HW_LRADC_CHn(channel)) + & BM_LRADC_CHn_VALUE; + + + __raw_writel(BM_LRADC_CHn_VALUE, + REGS_LRADC_BASE + HW_LRADC_CHn_CLR(channel)); + + /* power down temp sensor block */ + __raw_writel(BM_LRADC_CTRL2_TEMPSENSE_PWD, + REGS_LRADC_BASE + HW_LRADC_CTRL2_SET); + + + return (uint16_t)((ch9Value-ch8Value)*GAIN_CORRECTION/4000); +} + + + +/* Name: ddi_power_GetBatteryMode */ +/* */ +/* brief */ + +ddi_power_BatteryMode_t ddi_power_GetBatteryMode(void) +{ + return DDI_POWER_BATT_MODE_LIION; +} + + +/* Name: ddi_power_GetBatteryChargerEnabled */ +/* */ +/* brief */ + +bool ddi_power_GetBatteryChargerEnabled(void) +{ +#if 0 + return (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_BATT_CHRG_PRESENT) ? 1 : 0; +#endif + return 1; +} + + +/* */ +/* brief Report if the charger hardware power is on. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports if the charger hardware power is on. */ +/* */ +/* retval Zero if the charger hardware is not powered. Non-zero otherwise. */ +/* */ +/* Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD" */ +/* stands for "power down". Thus, when the bit is set, the battery charger */ +/* hardware is POWERED DOWN. */ + +bool ddi_power_GetChargerPowered(void) +{ + return (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_PWD_BATTCHRG) ? 0 : 1; +} + + +/* */ +/* brief Turn the charging hardware on or off. */ +/* */ +/* fntype Function */ +/* */ +/* This function turns the charging hardware on or off. */ +/* */ +/* param[in] on Indicates whether the charging hardware should be on or off. */ +/* */ +/* Note that the bit we're looking at is named PWD_BATTCHRG. The "PWD" */ +/* stands for "power down". Thus, when the bit is set, the battery charger */ +/* hardware is POWERED DOWN. */ + +void ddi_power_SetChargerPowered(bool bPowerOn) +{ + /* Hit the battery charge power switch. */ + if (bPowerOn) { + __raw_writel(BM_POWER_CHARGE_PWD_BATTCHRG, + REGS_POWER_BASE + HW_POWER_CHARGE_CLR); + __raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + } else { + __raw_writel(BM_POWER_CHARGE_PWD_BATTCHRG, + REGS_POWER_BASE + HW_POWER_CHARGE_SET); +#ifndef VDD4P2_ENABLED + __raw_writel(BM_POWER_5VCTRL_PWD_CHARGE_4P2, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); +#endif + } + +/* #ifdef CONFIG_POWER_SUPPLY_DEBUG */ +#if 0 + printk("Battery charger: charger %s\n", bPowerOn ? "ON!" : "OFF"); + dump_regs(); +#endif +} + + +/* */ +/* brief Reports if the charging current has fallen below the threshold. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports if the charging current that the battery is accepting */ +/* has fallen below the threshold. */ +/* */ +/* Note that this bit is regarded by the hardware guys as very slightly */ +/* unreliable. They recommend that you don't believe a value of zero until */ +/* you've sampled it twice. */ +/* */ +/* retval Zero if the battery is accepting less current than indicated by the */ +/* charging threshold. Non-zero otherwise. */ +/* */ + +int ddi_power_GetChargeStatus(void) +{ + return (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_CHRGSTS) ? 1 : 0; +} + + +/* Battery Voltage */ + + + +/* */ +/* brief Report the voltage across the battery. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the voltage across the battery. Should return a */ +/* value in range ~3000 - 4200 mV. */ +/* */ +/* retval The voltage across the battery, in mV. */ +/* */ + + +/* brief Constant value for 8mV steps used in battery translation */ +#define BATT_VOLTAGE_8_MV 8 + +uint16_t ddi_power_GetBattery(void) +{ + uint32_t u16BattVolt; + + /* Get the raw result of battery measurement */ + u16BattVolt = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR); + u16BattVolt &= BM_POWER_BATTMONITOR_BATT_VAL; + u16BattVolt >>= BP_POWER_BATTMONITOR_BATT_VAL; + + /* Adjust for 8-mV LSB resolution and return */ + u16BattVolt *= BATT_VOLTAGE_8_MV; + +/* #ifdef CONFIG_POWER_SUPPLY_DEBUG */ +#if 0 + printk("Battery charger: %u mV\n", u16BattVolt); +#endif + + return u16BattVolt; +} + +#if 0 + +/* */ +/* brief Report the voltage across the battery. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports the voltage across the battery. */ +/* */ +/* retval The voltage across the battery, in mV. */ +/* */ + +uint16_t ddi_power_GetBatteryBrownout(void) +{ + uint32_t u16BatteryBrownoutLevel; + + /* Get battery brownout level */ + u16BatteryBrownoutLevel = __raw_readl(REGS_POWER_BASE + HW_POWER_BATTMONITOR); + u16BatteryBrownoutLevel &= BM_POWER_BATTMONITOR_BRWNOUT_LVL; + u16BatteryBrownoutLevel >>= BP_POWER_BATTMONITOR_BRWNOUT_LVL; + + /* Calculate battery brownout level */ + switch (ddi_power_GetBatteryMode()) { + case DDI_POWER_BATT_MODE_LIION: + u16BatteryBrownoutLevel *= BATT_BRWNOUT_LIION_LEVEL_STEP_MV; + u16BatteryBrownoutLevel += BATT_BRWNOUT_LIION_BASE_MV; + break; + case DDI_POWER_BATT_MODE_ALKALINE_NIMH: + u16BatteryBrownoutLevel *= BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV; + u16BatteryBrownoutLevel += BATT_BRWNOUT_ALKAL_BASE_MV; + break; + default: + u16BatteryBrownoutLevel = 0; + break; + } + return u16BatteryBrownoutLevel; +} + + +/* */ +/* brief Set battery brownout level */ +/* */ +/* fntype Reentrant Function */ +/* */ +/* This function sets the battery brownout level in millivolt. It transforms the */ +/* input brownout value from millivolts to the hardware register bit field value */ +/* taking the ceiling value in the calculation. */ +/* */ +/* param[in] u16BattBrownout_mV Battery battery brownout level in mV */ +/* */ +/* return SUCCESS */ +/* */ + +int ddi_power_SetBatteryBrownout(uint16_t u16BattBrownout_mV) +{ + int16_t i16BrownoutLevel; + int ret = 0; + + /* Calculate battery brownout level */ + switch (ddi_power_GetBatteryMode()) { + case DDI_POWER_BATT_MODE_LIION: + i16BrownoutLevel = u16BattBrownout_mV - + BATT_BRWNOUT_LIION_EQN_CONST; + i16BrownoutLevel /= BATT_BRWNOUT_LIION_LEVEL_STEP_MV; + break; + case DDI_POWER_BATT_MODE_ALKALINE_NIMH: + i16BrownoutLevel = u16BattBrownout_mV - + BATT_BRWNOUT_ALKAL_EQN_CONST; + i16BrownoutLevel /= BATT_BRWNOUT_ALKAL_LEVEL_STEP_MV; + break; + default: + return -EINVAL; + } + + /* Do a check to make sure nothing went wrong. */ + if (i16BrownoutLevel <= 0x0f) { + /* Write the battery brownout level */ + __raw_writel( + BF_POWER_BATTMONITOR_BRWNOUT_LVL(i16BrownoutLevel), + REGS_POWER_BASE + HW_POWER_BATTMONITOR_SET); + } else + ret = -EINVAL; + + return ret; +} +#endif + + +/* Currents */ + + + + +/* Name: ddi_power_SetMaxBatteryChargeCurrent */ +/* */ +/* brief */ + +uint16_t ddi_power_SetMaxBatteryChargeCurrent(uint16_t u16MaxCur) +{ + uint32_t u16OldSetting; + uint32_t u16NewSetting; + uint32_t u16ToggleMask; + + /* Get the old setting. */ + u16OldSetting = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_BATTCHRG_I) >> + BP_POWER_CHARGE_BATTCHRG_I; + + /* Convert the new threshold into a setting. */ + u16NewSetting = ddi_power_convert_current_to_setting(u16MaxCur); + + /* Compute the toggle mask. */ + u16ToggleMask = u16OldSetting ^ u16NewSetting; + + /* Write to the toggle register.*/ + __raw_writel(u16ToggleMask << BP_POWER_CHARGE_BATTCHRG_I, + REGS_POWER_BASE + HW_POWER_CHARGE_TOG); + + /* Tell the caller what current we're set at now. */ + return ddi_power_convert_setting_to_current(u16NewSetting); +} + + +/* Name: ddi_power_GetMaxBatteryChargeCurrent */ +/* */ +/* brief */ + +uint16_t ddi_power_GetMaxBatteryChargeCurrent(void) +{ + uint32_t u8Bits; + + /* Get the raw data from register */ + u8Bits = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_BATTCHRG_I) >> + BP_POWER_CHARGE_BATTCHRG_I; + + /* Translate raw data to current (in mA) and return it */ + return ddi_power_convert_setting_to_current(u8Bits); +} + + +/* Name: ddi_power_GetMaxChargeCurrent */ +/* */ +/* brief */ + +uint16_t ddi_power_SetBatteryChargeCurrentThreshold(uint16_t u16Thresh) +{ + uint32_t u16OldSetting; + uint32_t u16NewSetting; + uint32_t u16ToggleMask; + + /* ------------------------------------------------------------------- */ + /* See ddi_power_SetMaxBatteryChargeCurrent for an explanation of */ + /* why we're using the toggle register here. */ + /* */ + /* Since this function doesn't have any major hardware effect, */ + /* we could use the usual macros for writing to this bit field. But, */ + /* for the sake of parallel construction and any potentially odd */ + /* effects on the status bit, we use the toggle register in the same */ + /* way as ddi_bc_hwSetMaxCurrent. */ + /* ------------------------------------------------------------------- */ + + /* ------------------------------------------------------------------- */ + /* The threshold hardware can't express as large a range as the max */ + /* current setting, but we can use the same functions as long as we */ + /* add an extra check here. */ + /* */ + /* Thresholds larger than 180mA can't be expressed. */ + /* ------------------------------------------------------------------- */ + + if (u16Thresh > 180) + u16Thresh = 180; + + + /* Create the mask */ + + + /* Get the old setting. */ + u16OldSetting = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_STOP_ILIMIT) >> + BP_POWER_CHARGE_STOP_ILIMIT; + + /* Convert the new threshold into a setting. */ + u16NewSetting = ddi_power_convert_current_to_setting(u16Thresh); + + /* Compute the toggle mask. */ + u16ToggleMask = u16OldSetting ^ u16NewSetting; + + + /* Write to the register */ + + + /* Write to the toggle register. */ + __raw_writel(BF_POWER_CHARGE_STOP_ILIMIT(u16ToggleMask), + REGS_POWER_BASE + HW_POWER_CHARGE_TOG); + + /* Tell the caller what current we're set at now. */ + return ddi_power_convert_setting_to_current(u16NewSetting); +} + + +/* Name: ddi_power_GetBatteryChargeCurrentThreshold */ +/* */ +/* brief */ + +uint16_t ddi_power_GetBatteryChargeCurrentThreshold(void) +{ + uint32_t u16Threshold; + + u16Threshold = (__raw_readl(REGS_POWER_BASE + HW_POWER_CHARGE) & BM_POWER_CHARGE_STOP_ILIMIT) >> + BP_POWER_CHARGE_STOP_ILIMIT; + + return ddi_power_convert_setting_to_current(u16Threshold); +} + + +/* Conversion */ + + + +/* */ +/* brief Compute the actual current expressible in the hardware. */ +/* */ +/* fntype Function */ +/* */ +/* Given a desired current, this function computes the actual current */ +/* expressible in the hardware. */ +/* */ +/* Note that the hardware has a minimum resolution of 10mA and a maximum */ +/* expressible value of 780mA (see the data sheet for details). If the given */ +/* current cannot be expressed exactly, then the largest expressible smaller */ +/* value will be used. */ +/* */ +/* param[in] u16Current The current of interest. */ +/* */ +/* retval The corresponding current in mA. */ +/* */ + +uint16_t ddi_power_ExpressibleCurrent(uint16_t u16Current) +{ + return ddi_power_convert_setting_to_current( + ddi_power_convert_current_to_setting(u16Current)); +} + + +/* Name: ddi_power_Get5VPresent */ +/* */ +/* brief */ + + +bool ddi_power_Get5vPresentFlag(void) +{ + switch (DetectionMethod) { + case DDI_POWER_5V_VBUSVALID: + /* Check VBUSVALID for 5V present */ + return ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BM_POWER_STS_VBUSVALID) != 0); + case DDI_POWER_5V_VDD5V_GT_VDDIO: + /* Check VDD5V_GT_VDDIO for 5V present */ + return ((__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BM_POWER_STS_VDD5V_GT_VDDIO) != 0); + default: + break; + } + + return 0; +} + + + + +/* */ +/* brief Report on the die temperature. */ +/* */ +/* fntype Function */ +/* */ +/* This function reports on the die temperature. */ +/* */ +/* param[out] pLow The low end of the temperature range. */ +/* param[out] pHigh The high end of the temperature range. */ +/* */ + +/* Temperature constant */ +#define TEMP_READING_ERROR_MARGIN 5 +#define KELVIN_TO_CELSIUS_CONST 273 + +void ddi_power_GetDieTemp(int16_t *pLow, int16_t *pHigh) +{ + int16_t i16High, i16Low; + uint16_t u16Reading; + + /* Get the reading in Kelvins */ + u16Reading = MeasureInternalDieTemperature(); + + /* Adjust for error margin */ + i16High = u16Reading + TEMP_READING_ERROR_MARGIN; + i16Low = u16Reading - TEMP_READING_ERROR_MARGIN; + + /* Convert to Celsius */ + i16High -= KELVIN_TO_CELSIUS_CONST; + i16Low -= KELVIN_TO_CELSIUS_CONST; + +/* #ifdef CONFIG_POWER_SUPPLY_DEBUG */ +#if 0 + printk("Battery charger: Die temp %d to %d C\n", i16Low, i16High); +#endif + /* Return the results */ + *pHigh = i16High; + *pLow = i16Low; +} + + +/* */ +/* brief Checks to see if the DCDC has been manually enabled */ +/* */ +/* fntype Function */ +/* */ +/* retval true if DCDC is ON, false if DCDC is OFF. */ +/* */ + +bool ddi_power_IsDcdcOn(void) +{ + return (__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) & BM_POWER_5VCTRL_ENABLE_DCDC) ? 1 : 0; +} + + + +/* See hw_power.h for details. */ + +void ddi_power_SetPowerClkGate(bool bGate) +{ + /* Gate/Ungate the clock to the power block */ +#ifndef CONFIG_ARCH_MX28 + if (bGate) { + __raw_writel(BM_POWER_CTRL_CLKGATE, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + } else { + __raw_writel(BM_POWER_CTRL_CLKGATE, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + } +#endif +} + + +/* See hw_power.h for details. */ + +bool ddi_power_GetPowerClkGate(void) +{ +#ifdef CONFIG_ARCH_MX28 + return 0; +#else + return (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & BM_POWER_CTRL_CLKGATE) ? 1 : 0; +#endif +} + + +enum ddi_power_5v_status ddi_power_GetPmu5vStatus(void) +{ + + if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) { + + if (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO) { + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ) || + ddi_power_Get5vPresentFlag()) + return new_5v_connection; + else + return existing_5v_disconnection; + } else { + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ) || + !ddi_power_Get5vPresentFlag() || + ddi_power_Get5vDroopFlag()) + return new_5v_disconnection; + else + return existing_5v_connection; + } + } else { + + if (__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_POLARITY_VBUSVALID) { + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_VBUSVALID_IRQ) || + ddi_power_Get5vPresentFlag()) + return new_5v_connection; + else + return existing_5v_disconnection; + } else { + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_VBUSVALID_IRQ) || + !ddi_power_Get5vPresentFlag() || + ddi_power_Get5vDroopFlag()) + return new_5v_disconnection; + else + return existing_5v_connection; + } + + } +} + +void ddi_power_disable_5v_connection_irq(void) +{ + + __raw_writel((BM_POWER_CTRL_ENIRQ_VBUS_VALID | + BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO), + REGS_POWER_BASE + HW_POWER_CTRL_CLR); +} + +void ddi_power_enable_5v_disconnect_detection(void) +{ + __raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO | + BM_POWER_CTRL_POLARITY_VBUSVALID, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + __raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ | + BM_POWER_CTRL_VBUSVALID_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) { + __raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + } else { + __raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + } +} + +void ddi_power_enable_5v_connect_detection(void) +{ + __raw_writel(BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO | + BM_POWER_CTRL_POLARITY_VBUSVALID, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + + __raw_writel(BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ | + BM_POWER_CTRL_VBUSVALID_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + if (DetectionMethod == DDI_POWER_5V_VDD5V_GT_VDDIO) { + __raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + } else { + __raw_writel(BM_POWER_CTRL_ENIRQ_VBUS_VALID, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + } +} + +void ddi_power_EnableBatteryBoInterrupt(bool bEnable) +{ + if (bEnable) { + + __raw_writel(BM_POWER_CTRL_BATT_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_ENIRQBATT_BO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + /* todo: make sure the battery brownout comparator + * is enabled in HW_POWER_BATTMONITOR + */ + } else { + __raw_writel(BM_POWER_CTRL_ENIRQBATT_BO, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + } +} + +void ddi_power_EnableDcdc4p2BoInterrupt(bool bEnable) +{ + if (bEnable) { + + __raw_writel(BM_POWER_CTRL_DCDC4P2_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + } else { + __raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + } +} + +void ddi_power_EnableVdd5vDroopInterrupt(bool bEnable) +{ + if (bEnable) { + + __raw_writel(BM_POWER_CTRL_VDD5V_DROOP_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + } else { + __raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_DROOP, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + } +} + + +void ddi_power_Enable5vDisconnectShutdown(bool bEnable) +{ + if (bEnable) { + __raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT, + REGS_POWER_BASE + HW_POWER_5VCTRL_SET); + } else { + __raw_writel(BM_POWER_5VCTRL_PWDN_5VBRNOUT, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + } +} + + +void ddi_power_enable_5v_to_battery_xfer(bool bEnable) +{ + if (bEnable) { + /* order matters */ + + /* we can enable this in in vbus droop or 4p2 fiq handler + * ddi_power_EnableBatteryBoInterrupt(true); + */ + ddi_power_Enable5vDisconnectShutdown(false); + } else { + /* order matters */ + ddi_power_Enable5vDisconnectShutdown(true); + ddi_power_EnableBatteryBoInterrupt(false); + } +} + + +void ddi_power_init_4p2_protection(void) +{ + /* set vbus droop detection level to 4.3V */ + __raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + /* VBUSDROOP THRESHOLD to 4.3V */ + __raw_writel(BM_POWER_5VCTRL_VBUSDROOP_TRSH, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + ddi_power_EnableVbusDroopIrq(); + +#ifndef CONFIG_ARCH_MX28 + /* VBUSVALID THRESH = 2.9V */ + __raw_writel(BM_POWER_5VCTRL_VBUSVALID_TRSH, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); +#endif + +} + +/* determine if all the bits are in a 'DCDC 4P2 Enabled' state. */ +bool ddi_power_check_4p2_bits(void) +{ + + + uint32_t temp; + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) & + BM_POWER_5VCTRL_PWD_CHARGE_4P2; + + /* if PWD_CHARGE_4P2 = 1, 4p2 is disabled */ + if (temp) + return false; + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2) & + BM_POWER_DCDC4P2_ENABLE_DCDC; + + if (!temp) + return false; + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2) & + BM_POWER_DCDC4P2_ENABLE_4P2; + + if (temp) + return true; + else + return false; + +} + +uint16_t ddi_power_set_4p2_ilimit(uint16_t ilimit) +{ + uint32_t temp_reg; + + if (ilimit > 780) + ilimit = 780; + temp_reg = __raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL); + temp_reg &= (~BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT); + temp_reg |= BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT( + ddi_power_convert_current_to_setting( + ilimit)); + __raw_writel(temp_reg, REGS_POWER_BASE + HW_POWER_5VCTRL); + + return ilimit; +} + +void ddi_power_shutdown(void) +{ + __raw_writel(0x3e770001, REGS_POWER_BASE + HW_POWER_RESET); +} + +void ddi_power_handle_dcdc4p2_bo(void) +{ + ddi_power_EnableBatteryBoInterrupt(true); + ddi_power_EnableDcdc4p2BoInterrupt(false); +} + +void ddi_power_enable_vddio_interrupt(bool enable) +{ + if (enable) { + __raw_writel(BM_POWER_CTRL_VDDIO_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); +#ifndef DISABLE_VDDIO_BO_PROTECTION + __raw_writel(BM_POWER_CTRL_ENIRQ_VDDIO_BO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); +#endif + } else { + __raw_writel(BM_POWER_CTRL_ENIRQ_VDDIO_BO, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + } + +} + + +void ddi_power_handle_vddio_brnout(void) +{ + if (ddi_power_GetPmu5vStatus() == new_5v_connection || + (ddi_power_GetPmu5vStatus() == new_5v_disconnection)) { + ddi_power_enable_vddio_interrupt(false); + } else { +#ifdef DEBUG_IRQS + ddi_power_enable_vddio_interrupt(false); + printk(KERN_ALERT "VDDIO BO TRIED TO SHUTDOWN!!!\n"); + return; +#else + ddi_power_shutdown(); +#endif + } +} + +void ddi_power_handle_vdd5v_droop(void) +{ + uint32_t temp; + + /* handle errata */ + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_DCDC4P2); + temp |= (BF_POWER_DCDC4P2_CMPTRIP(31) | BM_POWER_DCDC4P2_TRG); + __raw_writel(temp, REGS_POWER_BASE + HW_POWER_DCDC4P2); + + + /* if battery is below brownout level, shutdown asap */ + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_BATT_BO) + ddi_power_shutdown(); + + /* due to 5v connect vddio bo chip bug, we need to + * disable vddio interrupts until we reset the 5v + * detection for 5v connect detect. We want to allow + * some debounce time before enabling connect detection. + */ + ddi_power_enable_vddio_interrupt(false); + + ddi_power_EnableBatteryBoInterrupt(true); + ddi_power_EnableDcdc4p2BoInterrupt(false); + ddi_power_EnableVdd5vDroopInterrupt(false); + +} + +void ddi_power_InitOutputBrownouts(void) +{ + uint32_t temp; + + __raw_writel(BM_POWER_CTRL_VDDD_BO_IRQ | + BM_POWER_CTRL_VDDA_BO_IRQ | + BM_POWER_CTRL_VDDIO_BO_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + + __raw_writel(BM_POWER_CTRL_ENIRQ_VDDD_BO | + BM_POWER_CTRL_ENIRQ_VDDA_BO | + BM_POWER_CTRL_ENIRQ_VDDIO_BO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL); + temp &= ~BM_POWER_VDDDCTRL_PWDN_BRNOUT; + __raw_writel(temp, REGS_POWER_BASE + HW_POWER_VDDDCTRL); + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL); + temp &= ~BM_POWER_VDDACTRL_PWDN_BRNOUT; + __raw_writel(temp, REGS_POWER_BASE + HW_POWER_VDDACTRL); + + temp = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL); + temp &= ~BM_POWER_VDDIOCTRL_PWDN_BRNOUT; + __raw_writel(temp, REGS_POWER_BASE + HW_POWER_VDDIOCTRL); +} + +/* used for debugging purposes only */ +void ddi_power_disable_power_interrupts(void) +{ + __raw_writel(BM_POWER_CTRL_ENIRQ_DCDC4P2_BO | + BM_POWER_CTRL_ENIRQ_VDD5V_DROOP | + BM_POWER_CTRL_ENIRQ_PSWITCH | + BM_POWER_CTRL_ENIRQ_DC_OK | + BM_POWER_CTRL_ENIRQBATT_BO | + BM_POWER_CTRL_ENIRQ_VDDIO_BO | + BM_POWER_CTRL_ENIRQ_VDDA_BO | + BM_POWER_CTRL_ENIRQ_VDDD_BO | + BM_POWER_CTRL_ENIRQ_VBUS_VALID | + BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + +} + +bool ddi_power_Get5vDroopFlag(void) +{ + if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & + BM_POWER_STS_VDD5V_DROOP) + return true; + else + return false; +} + + +/* End of file */ + +/* @} */ diff --git a/drivers/power/mxs/ddi_power_battery.h b/drivers/power/mxs/ddi_power_battery.h new file mode 100644 index 000000000000..6a25569f25d3 --- /dev/null +++ b/drivers/power/mxs/ddi_power_battery.h @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* brief Battery modes */ +typedef enum { + /* 37xx battery modes */ + /* brief LiIon battery powers the player */ + DDI_POWER_BATT_MODE_LIION = 0, + /* brief Alkaline/NiMH battery powers the player */ + DDI_POWER_BATT_MODE_ALKALINE_NIMH = 1, +} ddi_power_BatteryMode_t; + + +/* brief Possible 5V detection methods */ +typedef enum { + /* brief Use VBUSVALID comparator for detection */ + DDI_POWER_5V_VBUSVALID, + /* brief Use VDD5V_GT_VDDIO comparison for detection */ + DDI_POWER_5V_VDD5V_GT_VDDIO +} ddi_power_5vDetection_t; + + +enum ddi_power_5v_status { + new_5v_connection, + existing_5v_connection, + new_5v_disconnection, + existing_5v_disconnection, +} ; + + +uint16_t ddi_power_convert_current_to_setting(uint16_t u16Current); +uint16_t ddi_power_convert_setting_to_current(uint16_t u16Setting); +void ddi_power_enable_5v_to_battery_handoff(void); +void ddi_power_execute_5v_to_battery_handoff(void); +void ddi_power_enable_battery_to_5v_handoff(void); +void ddi_power_execute_battery_to_5v_handoff(void); +int ddi_power_init_battery(void); +ddi_power_BatteryMode_t ddi_power_GetBatteryMode(void); +bool ddi_power_GetBatteryChargerEnabled(void); +bool ddi_power_GetChargerPowered(void); +void ddi_power_SetChargerPowered(bool bPowerOn); +int ddi_power_GetChargeStatus(void); +uint16_t ddi_power_GetBattery(void); +uint16_t ddi_power_GetBatteryBrownout(void); +int ddi_power_SetBatteryBrownout(uint16_t u16BattBrownout_mV); +uint16_t ddi_power_SetMaxBatteryChargeCurrent(uint16_t u16MaxCur); +uint16_t ddi_power_GetMaxBatteryChargeCurrent(void); +uint16_t ddi_power_SetBatteryChargeCurrentThreshold(uint16_t u16Thresh); +uint16_t ddi_power_GetBatteryChargeCurrentThreshold(void); +uint16_t ddi_power_ExpressibleCurrent(uint16_t u16Current); +bool ddi_power_Get5vPresentFlag(void); +void ddi_power_GetDieTemp(int16_t *pLow, int16_t *pHigh); +bool ddi_power_IsDcdcOn(void); +void ddi_power_SetPowerClkGate(bool bGate); +bool ddi_power_GetPowerClkGate(void); +enum ddi_power_5v_status ddi_power_GetPmu5vStatus(void); +void ddi_power_EnableBatteryBoFiq(bool bEnable); +void ddi_power_disable_5v_connection_irq(void); +void ddi_power_enable_5v_disconnect_detection(void); +void ddi_power_enable_5v_connect_detection(void); +void ddi_power_Enable5vDisconnectShutdown(bool bEnable); +void ddi_power_enable_5v_to_battery_xfer(bool bEnable); +void ddi_power_init_4p2_protection(void); +bool ddi_power_check_4p2_bits(void); +void ddi_power_Start4p2Dcdc(bool battery_ready); +void ddi_power_Init4p2Params(void); +bool ddi_power_IsBattRdyForXfer(void); +void ddi_power_EnableVbusDroopIrq(void); +void ddi_power_Enable4p2(uint16_t target_current_limit_ma); +uint16_t ddi_power_BringUp4p2Regulator( + uint16_t target_current_limit_ma, + bool b4p2_dcdc_enabled); +void ddi_power_Set4p2BoLevel(uint16_t bo_voltage_mv); +void ddi_power_EnableBatteryBoInterrupt(bool bEnable); +void ddi_power_handle_cmptrip(void); +uint16_t ddi_power_set_4p2_ilimit(uint16_t ilimit); +void ddi_power_shutdown(void); +void ddi_power_handle_dcdc4p2_bo(void); +void ddi_power_enable_vddio_interrupt(bool enable); +void ddi_power_handle_vddio_brnout(void); +void ddi_power_EnableDcdc4p2BoInterrupt(bool bEnable); +void ddi_power_handle_vdd5v_droop(void); +void ddi_power_InitOutputBrownouts(void); +void ddi_power_disable_power_interrupts(void); +bool ddi_power_Get5vDroopFlag(void); diff --git a/drivers/power/mxs/fiq.S b/drivers/power/mxs/fiq.S new file mode 100644 index 000000000000..1ad380d07efd --- /dev/null +++ b/drivers/power/mxs/fiq.S @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include +#include +#include +#include +#include +#include +#include + + .align 5 + .globl power_fiq_start + .globl power_fiq_end + .globl power_fiq_count + .globl lock_vector_tlb + +power_fiq_start: + ldr r8,power_reg + ldr r9,[r8,#HW_POWER_CTRL ] + ldr r10,power_off + + @ when VDDIO_BO_IRQ, + @ disabled, handled in IRQ for now + @tst r9, #BM_POWER_CTRL_VDDIO_BO_IRQ + + + @ when BATT_BO_IRQ, VDDD_BO_IRQ, VDDA_BO_IRQ, power off chip + ldr r11,power_bo + tst r9, r11 + strne r10,[r8,#HW_POWER_RESET] + + @VDD5V_DROOP_IRQ + tst r9, #BM_POWER_CTRL_VDD5V_DROOP_IRQ + beq check_dcdc4p2 + + @ handle errata + ldr r10, [r8, #HW_POWER_DCDC4P2] + orr r10,r10,#(BM_POWER_DCDC4P2_TRG) + orr r10,r10,#(BF_POWER_DCDC4P2_CMPTRIP(31)) + str r10,[r8, #(HW_POWER_DCDC4P2)] + + @ if battery is below brownout level, shutdown asap + ldr r10, [r8, #HW_POWER_STS] + tst r10, #BM_POWER_STS_BATT_BO + ldr r10, power_off + strne r10, [r8, #HW_POWER_RESET] + + @ disable viddio irq + mov r11, #BM_POWER_CTRL_ENIRQ_VDDIO_BO + str r11, [r8, #HW_POWER_CTRL_CLR] + + @ enable battery BO irq + mov r11, #BM_POWER_CTRL_BATT_BO_IRQ + str r11, [r8, #HW_POWER_CTRL_CLR] + mov r11, #BM_POWER_CTRL_ENIRQBATT_BO + str r11, [r8, #HW_POWER_CTRL_SET] + + @ disable dcdc4p2 interrupt + mov r11, #BM_POWER_CTRL_ENIRQ_DCDC4P2_BO + str r11, [r8, #HW_POWER_CTRL_CLR] + + @ disable vdd5v_droop interrupt + mov r11, #BM_POWER_CTRL_ENIRQ_VDD5V_DROOP + str r11, [r8, #HW_POWER_CTRL_CLR] + +check_dcdc4p2: + @ when DCDC4P2_BO_IRQ, + tst r9, #BM_POWER_CTRL_DCDC4P2_BO_IRQ + + mov r11, #BM_POWER_CTRL_BATT_BO_IRQ + strne r11, [r8, #HW_POWER_CTRL_CLR] + + mov r11, #BM_POWER_CTRL_ENIRQBATT_BO + strne r11, [r8, #HW_POWER_CTRL_SET] + + mov r11, #BM_POWER_CTRL_ENIRQ_DCDC4P2_BO + strne r11, [r8, #HW_POWER_CTRL_CLR] + + + + @return from fiq + subs pc,lr, #4 + +power_reg: + .long IO_ADDRESS(POWER_PHYS_ADDR) +power_off: + .long 0x3e770001 +power_bo: + .long BM_POWER_CTRL_BATT_BO_IRQ | \ + BM_POWER_CTRL_VDDA_BO_IRQ | BM_POWER_CTRL_VDDD_BO_IRQ +power_fiq_count: + .long 0 +power_fiq_end: + +lock_vector_tlb: + + mov r1, r0 @ set r1 to the value of the address to be locked down + mcr p15,0,r1,c8,c7,1 @ invalidate TLB single entry to ensure that + @ LockAddr is not already in the TLB + mrc p15,0,r0,c10,c0,0 @ read the lockdown register + orr r0,r0,#1 @ set the preserve bit + mcr p15,0,r0,c10,c0,0 @ write to the lockdown register + ldr r1,[r1] @ TLB will miss, and entry will be loaded + mrc p15,0,r0,c10,c0,0 @ read the lockdown register (victim will have + @ incremented) + bic r0,r0,#1 @ clear preserve bit + mcr p15,0,r0,c10,c0,0 @ write to the lockdown registerADR r1,LockAddr + mov pc,lr @ diff --git a/drivers/power/mxs/linux.c b/drivers/power/mxs/linux.c new file mode 100644 index 000000000000..33883075e50c --- /dev/null +++ b/drivers/power/mxs/linux.c @@ -0,0 +1,1213 @@ +/* + * Linux glue to MXS battery state machine. + * + * Author: Steve Longerbeam + * + * Copyright (C) 2008 EmbeddedAlley Solutions Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2, as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddi_bc_internal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum application_5v_status{ + _5v_connected_verified, + _5v_connected_unverified, + _5v_disconnected_unverified, + _5v_disconnected_verified, +}; + +struct mxs_info { + struct device *dev; + struct regulator *regulator; + struct regulator *onboard_vbus5v; + + struct power_supply bat; + struct power_supply ac; + struct power_supply usb; + + ddi_bc_Cfg_t *sm_cfg; + struct mutex sm_lock; + struct timer_list sm_timer; + struct work_struct sm_work; + struct resource *irq_vdd5v; + struct resource *irq_dcdc4p2_bo; + struct resource *irq_batt_brnout; + struct resource *irq_vddd_brnout; + struct resource *irq_vdda_brnout; + struct resource *irq_vddio_brnout; + struct resource *irq_vdd5v_droop; + int is_ac_online; + int source_protection_mode; + uint32_t sm_new_5v_connection_jiffies; + uint32_t sm_new_5v_disconnection_jiffies; + enum application_5v_status sm_5v_connection_status; + + + + +#define USB_ONLINE 0x01 +#define USB_REG_SET 0x02 +#define USB_SM_RESTART 0x04 +#define USB_SHUTDOWN 0x08 +#define USB_N_SEND 0x10 + int is_usb_online; + int onboard_vbus5v_online; +}; + +#define to_mxs_info(x) container_of((x), struct mxs_info, bat) + +#ifndef NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA +#define NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA 780 +#endif + +#ifndef POWERED_USB_5V_CURRENT_LIMIT_MA +#define POWERED_USB_5V_CURRENT_LIMIT_MA 450 +#endif + +#ifndef UNPOWERED_USB_5V_CURRENT_LIMIT_MA +#define UNPOWERED_USB_5V_CURRENT_LIMIT_MA 80 +#endif + +#ifndef _5V_DEBOUNCE_TIME_MS +#define _5V_DEBOUNCE_TIME_MS 500 +#endif + +#ifndef OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV +#define OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV 3350 +#endif + +#ifdef CONFIG_ARCH_MX23 +#define IRQ_DCDC4P2_BRNOUT IRQ_DCDC4P2_BO +#endif + +#define POWER_FIQ + +/* #define DEBUG_IRQS */ + +/* There is no direct way to detect wall power presence, so assume the AC + * power source is valid if 5V presents and USB device is disconnected. + * If USB device is connected then assume that AC is offline and USB power + * is online. + */ + + +#define is_ac_online() \ + (ddi_power_Get5vPresentFlag() ? (!fsl_is_usb_plugged()) : 0) +#define is_usb_online() \ + (ddi_power_Get5vPresentFlag() ? (!!fsl_is_usb_plugged()) : 0) + + + +void init_protection(struct mxs_info *info) +{ + enum ddi_power_5v_status pmu_5v_status; + uint16_t battery_voltage; + + pmu_5v_status = ddi_power_GetPmu5vStatus(); + battery_voltage = ddi_power_GetBattery(); + + /* InitializeFiqSystem(); */ + ddi_power_InitOutputBrownouts(); + + + /* if we start the kernel with 4p2 already started + * by the bootlets, we need to hand off from this + * state to the kernel 4p2 enabled state. + */ + if ((pmu_5v_status == existing_5v_connection) && + ddi_power_check_4p2_bits()) { + ddi_power_enable_5v_disconnect_detection(); + + /* includes VBUS DROOP workaround for errata */ + ddi_power_init_4p2_protection(); + + /* if we still have our 5V connection, we can disable + * battery brownout interrupt. This is because the + * VDD5V DROOP IRQ handler will also shutdown if battery + * is browned out and it will enable the battery brownout + * and bring VBUSVALID_TRSH level back to a normal level + * which caused the hardware battery brownout shutdown + * to be enabled. The benefit of this is that device + * that have detachable batteries (or devices going through + * the assembly line and running this firmware to test + * with) can avoid shutting down if 5V is present and + * battery voltage goes away. + */ + ddi_power_EnableBatteryBoInterrupt(false); + + info->sm_5v_connection_status = _5v_connected_verified; + } else { +#ifdef DEBUG_IRQS + if (battery_voltage < + OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV) { + printk(KERN_CRIT "Polled battery voltage measurement is\ + less than %dmV. Kernel should be halted/\ + shutdown\n", + OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV); + + return; + } +#endif + info->sm_5v_connection_status = _5v_disconnected_verified; + ddi_power_EnableBatteryBoInterrupt(true); + + } + + + /* all brownouts are now handled software fiqs. We + * can now disable the hardware protection mechanisms + * because leaving them on yields ~2kV ESD level + * versus ~4kV ESD levels when they are off. This + * difference is suspected to be cause by the fast + * falling edge pswitch functionality being tripped + * by ESD events. This functionality is disabled + * when PWD_OFF is disabled. + */ +#ifdef DISABLE_HARDWARE_PROTECTION_MECHANISMS + __raw_writel(BM_POWER_RESET_PWD_OFF, + HW_POWER_RESET_SET_ADDR); +#endif + + + + +} + + + +static void check_and_handle_5v_connection(struct mxs_info *info) +{ + + switch (ddi_power_GetPmu5vStatus()) { + + case new_5v_connection: + ddi_power_enable_5v_disconnect_detection(); + info->sm_5v_connection_status = _5v_connected_unverified; + + case existing_5v_connection: + if (info->sm_5v_connection_status != _5v_connected_verified) { + /* we allow some time to pass before considering + * the 5v connection to be ready to use. This + * will give the USB system time to enumerate + * (coordination with USB driver to be added + * in the future). + */ + + /* handle jiffies rollover case */ + if ((jiffies - info->sm_new_5v_connection_jiffies) + < 0) { + info->sm_new_5v_connection_jiffies = jiffies; + break; + } + + if ((jiffies_to_msecs(jiffies - + info->sm_new_5v_connection_jiffies)) > + _5V_DEBOUNCE_TIME_MS) { + info->sm_5v_connection_status = + _5v_connected_verified; + dev_dbg(info->dev, + "5v connection verified\n"); + if (info->onboard_vbus5v) { + if (regulator_is_enabled( + info->onboard_vbus5v) > 0) { + info->onboard_vbus5v_online = 1; + pr_debug("When supply from \ + onboard vbus 5v ,\ + DO NOT switch to 4p2 \n"); + break; + } + } +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + #ifdef CONFIG_USB_GADGET + /* if there is USB 2.0 current limitation requirement, + * waiting for USB enum done. + */ + if ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) + & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == + (0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT)) { + dev_info(info->dev, "waiting USB enum done...\r\n"); + } + while ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) + & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) + == (0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT)) { + msleep(50); + } + #endif +#endif + ddi_power_Enable4p2(450); + + /* part of handling for errata. It is + * now "somewhat" safe to + * turn on vddio interrupts again + */ + ddi_power_enable_vddio_interrupt(true); + } + } + break; + + case new_5v_disconnection: + + ddi_bc_SetDisable(); + ddi_bc_SetCurrentLimit(0); + if (info->regulator) + regulator_set_current_limit(info->regulator, 0, 0); + info->is_usb_online = 0; + info->is_ac_online = 0; + info->onboard_vbus5v_online = 0; + + info->sm_5v_connection_status = _5v_disconnected_unverified; + + case existing_5v_disconnection: + + if (info->sm_5v_connection_status != + _5v_disconnected_verified) { + if ((jiffies - info->sm_new_5v_disconnection_jiffies) + < 0) { + info->sm_new_5v_connection_jiffies = jiffies; + break; + } + + if ((jiffies_to_msecs(jiffies - + info->sm_new_5v_disconnection_jiffies)) > + _5V_DEBOUNCE_TIME_MS) { + info->sm_5v_connection_status = + _5v_disconnected_verified; + ddi_power_execute_5v_to_battery_handoff(); + ddi_power_enable_5v_connect_detection(); + + /* part of handling for errata. + * It is now safe to + * turn on vddio interrupts again + */ + ddi_power_enable_vddio_interrupt(true); + dev_dbg(info->dev, + "5v disconnection handled\n"); + + __raw_writel(__raw_readl(REGS_POWER_BASE + + HW_POWER_5VCTRL) & + (~BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) + | (0x20 << BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT), + REGS_POWER_BASE + HW_POWER_5VCTRL); + + } + } + + break; + } +} + + +static void handle_battery_voltage_changes(struct mxs_info *info) +{ +#if 0 + uint16_t battery_voltage; + + battery_voltage = ddi_power_GetBattery(); + + if (info->sm_5v_connection_status != _5v_connected_verified) { + if (battery_voltage < + OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV) { + printk(KERN_CRIT "Polled battery voltage measurement is\ + less than %dmV. Shutting down the \ + system\n", + OS_SHUTDOWN_BATTERY_VOLTAGE_THRESHOLD_MV); + + shutdown_os(); + return; + } + } else +#endif + { + ddi_power_handle_cmptrip(); + + if (ddi_power_IsBattRdyForXfer()) + ddi_power_enable_5v_to_battery_xfer(true); + else + ddi_power_enable_5v_to_battery_xfer(false); + + } +} + + +/* + * Power properties + */ +static enum power_supply_property mxs_power_props[] = { + POWER_SUPPLY_PROP_ONLINE, +}; + +static int mxs_power_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct mxs_info *info; + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + if (psy->type == POWER_SUPPLY_TYPE_MAINS) { + /* ac online */ + info = container_of(psy, struct mxs_info, ac); + val->intval = info->onboard_vbus5v_online ? + 0 : is_ac_online(); + } else { + /* usb online */ + info = container_of(psy, struct mxs_info, usb); + val->intval = info->onboard_vbus5v_online ? + 0 : is_usb_online(); + } + break; + default: + return -EINVAL; + } + + return 0; +} +/* + * Battery properties + */ +static enum power_supply_property mxs_bat_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_HEALTH, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_TEMP, +}; + +static int mxs_bat_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct mxs_info *info = to_mxs_info(psy); + ddi_bc_State_t state; + ddi_bc_BrokenReason_t reason; + int temp_alarm; + int16_t temp_lo, temp_hi; + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + state = ddi_bc_GetState(); + switch (state) { + case DDI_BC_STATE_CONDITIONING: + case DDI_BC_STATE_CHARGING: + case DDI_BC_STATE_TOPPING_OFF: + val->intval = POWER_SUPPLY_STATUS_CHARGING; + break; + case DDI_BC_STATE_DISABLED: + val->intval = (ddi_power_Get5vPresentFlag() + && !info->onboard_vbus5v_online) ? + POWER_SUPPLY_STATUS_NOT_CHARGING : + POWER_SUPPLY_STATUS_DISCHARGING; + break; + default: + /* TODO: detect full */ + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + break; + } + break; + case POWER_SUPPLY_PROP_PRESENT: + /* is battery present */ + state = ddi_bc_GetState(); + switch (state) { + case DDI_BC_STATE_WAITING_TO_CHARGE: + case DDI_BC_STATE_DCDC_MODE_WAITING_TO_CHARGE: + case DDI_BC_STATE_CONDITIONING: + case DDI_BC_STATE_CHARGING: + case DDI_BC_STATE_TOPPING_OFF: + case DDI_BC_STATE_DISABLED: + val->intval = 1; + break; + case DDI_BC_STATE_BROKEN: + val->intval = !(ddi_bc_GetBrokenReason() == + DDI_BC_BROKEN_NO_BATTERY_DETECTED); + break; + default: + val->intval = 0; + break; + } + break; + case POWER_SUPPLY_PROP_HEALTH: + temp_alarm = ddi_bc_RampGetDieTempAlarm(); + if (temp_alarm) { + val->intval = POWER_SUPPLY_HEALTH_OVERHEAT; + } else { + state = ddi_bc_GetState(); + switch (state) { + case DDI_BC_STATE_BROKEN: + reason = ddi_bc_GetBrokenReason(); + val->intval = + (reason == DDI_BC_BROKEN_CHARGING_TIMEOUT) ? + POWER_SUPPLY_HEALTH_DEAD : + POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; + break; + case DDI_BC_STATE_UNINITIALIZED: + val->intval = POWER_SUPPLY_HEALTH_UNKNOWN; + break; + default: + val->intval = POWER_SUPPLY_HEALTH_GOOD; + break; + } + } + break; + case POWER_SUPPLY_PROP_TECHNOLOGY: + val->intval = POWER_SUPPLY_TECHNOLOGY_LION; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + /* uV */ + val->intval = ddi_power_GetBattery() * 1000; + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + /* uA */ + val->intval = ddi_power_GetMaxBatteryChargeCurrent() * 1000; + break; + case POWER_SUPPLY_PROP_TEMP: + mutex_lock(&info->sm_lock); + ddi_power_GetDieTemp(&temp_lo, &temp_hi); + mutex_unlock(&info->sm_lock); + val->intval = temp_lo + (temp_hi - temp_lo) / 2; + + break; + default: + return -EINVAL; + } + + return 0; +} + +static void state_machine_timer(unsigned long data) +{ + struct mxs_info *info = (struct mxs_info *)data; + ddi_bc_Cfg_t *cfg = info->sm_cfg; + int ret; + + /* schedule next call to state machine */ + mod_timer(&info->sm_timer, + jiffies + msecs_to_jiffies(cfg->u32StateMachinePeriod)); + + ret = schedule_work(&info->sm_work); + if (!ret) + dev_dbg(info->dev, "state machine failed to schedule\n"); + +} +/* + * Assumption: + * AC power can't be switched to USB w/o system reboot + * and vice-versa + */ +static void state_machine_work(struct work_struct *work) +{ + struct mxs_info *info = + container_of(work, struct mxs_info, sm_work); + + mutex_lock(&info->sm_lock); + + handle_battery_voltage_changes(info); + + check_and_handle_5v_connection(info); + + if ((info->sm_5v_connection_status != _5v_connected_verified) || + !(info->regulator)) { + mod_timer(&info->sm_timer, jiffies + msecs_to_jiffies(100)); + goto out; + } + + /* if we made it here, we have a verified 5v connection */ +#ifndef CONFIG_MXS_VBUS_CURRENT_DRAW + if (info->is_ac_online || info->onboard_vbus5v_online) + goto done; + /* ac supply connected */ + dev_dbg(info->dev, "changed power connection to ac/5v.\n)"); + dev_dbg(info->dev, "5v current limit set to %u.\n", + NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA); + + info->is_ac_online = 1; + info->is_usb_online = 0; + + ddi_power_set_4p2_ilimit( + NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA); + ddi_bc_SetCurrentLimit( + NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA /*mA*/); + if (regulator_set_current_limit(info->regulator, + 0, + NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA*1000)) { + dev_err(info->dev, "reg_set_current(%duA) failed\n", + NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA*1000); + } + ddi_bc_SetEnable(); + goto done; +#else + + if (!is_usb_online()) + goto out; + + if (info->is_usb_online & USB_REG_SET) + goto done; + + info->is_ac_online = 0; + info->is_usb_online |= USB_ONLINE; + + + + if (!(info->is_usb_online & USB_N_SEND)) { + info->is_usb_online |= USB_N_SEND; + } + + + dev_dbg(info->dev, "%s: charge current set to %dmA\n", __func__, + POWERED_USB_5V_CURRENT_LIMIT_MA); + + if (regulator_set_current_limit(info->regulator, + 0, + POWERED_USB_5V_CURRENT_LIMIT_MA*1000)) { + dev_err(info->dev, "reg_set_current(%duA) failed\n", + POWERED_USB_5V_CURRENT_LIMIT_MA*1000); + } else { + + if (info->onboard_vbus5v_online == 0) { + ddi_bc_SetCurrentLimit( + POWERED_USB_5V_CURRENT_LIMIT_MA/*mA*/); + ddi_bc_SetEnable(); + } else + pr_debug("DO NOT charge from onboard 5v"); + } + + if (info->is_usb_online & USB_SM_RESTART) { + info->is_usb_online &= ~USB_SM_RESTART; + ddi_bc_SetEnable(); + } + + info->is_usb_online |= USB_REG_SET; + +#endif + dev_dbg(info->dev, "changed power connection to usb/5v present\n"); + +done: + ddi_bc_StateMachine(); +out: + mutex_unlock(&info->sm_lock); +} + + + +static int bc_sm_restart(struct mxs_info *info) +{ + ddi_bc_Status_t bcret; + int ret = 0; + + mutex_lock(&info->sm_lock); + + /* ungate power clk */ + ddi_power_SetPowerClkGate(0); + + /* + * config battery charger state machine and move it to the Disabled + * state. This must be done before starting the state machine. + */ + bcret = ddi_bc_Init(info->sm_cfg); + if (bcret != DDI_BC_STATUS_SUCCESS) { + dev_err(info->dev, "battery charger init failed: %d\n", bcret); + ret = -EIO; + goto out; + } else { + + if (!info->regulator) { + info->regulator = regulator_get(NULL, "charger-1"); + if (!info->regulator || IS_ERR(info->regulator)) { + dev_err(info->dev, + "%s: failed to get regulator\n", __func__); + info->regulator = NULL; + } else { + regulator_set_current_limit( + info->regulator, 0, 0); + regulator_set_mode(info->regulator, + REGULATOR_MODE_FAST); + } + } + } + + + + /* schedule first call to state machine */ + mod_timer(&info->sm_timer, jiffies + 1); +out: + mutex_unlock(&info->sm_lock); + return ret; +} + +#ifndef POWER_FIQ + +static irqreturn_t mxs_irq_dcdc4p2_bo(int irq, void *cookie) +{ +#ifdef DEBUG_IRQS + struct mxs_info *info = (struct mxs_info *)cookie; + dev_info(info->dev, "dcdc4p2 brownout interrupt occurred\n"); + +#endif + ddi_power_handle_dcdc4p2_bo(); + return IRQ_HANDLED; +} + +static irqreturn_t mxs_irq_batt_brnout(int irq, void *cookie) +{ +#ifdef DEBUG_IRQS + struct mxs_info *info = (struct mxs_info *)cookie; + dev_info(info->dev, "battery brownout interrupt occurred\n"); + ddi_power_disable_power_interrupts(); +#else + ddi_power_shutdown(); +#endif + return IRQ_HANDLED; +} + + +static irqreturn_t mxs_irq_vddd_brnout(int irq, void *cookie) +{ +#ifdef DEBUG_IRQS + struct mxs_info *info = (struct mxs_info *)cookie; + dev_info(info->dev, "vddd brownout interrupt occurred\n"); + ddi_power_disable_power_interrupts(); +#else + ddi_power_shutdown(); +#endif + return IRQ_HANDLED; +} +static irqreturn_t mxs_irq_vdda_brnout(int irq, void *cookie) +{ +#ifdef DEBUG_IRQS + struct mxs_info *info = (struct mxs_info *)cookie; + dev_info(info->dev, "vdda brownout interrupt occurred\n"); + ddi_power_disable_power_interrupts(); +#else + ddi_power_shutdown(); +#endif + return IRQ_HANDLED; +} + +static irqreturn_t mxs_irq_vdd5v_droop(int irq, void *cookie) +{ +#ifdef DEBUG_IRQS + struct mxs_info *info = (struct mxs_info *)cookie; + dev_info(info->dev, "vdd5v droop interrupt occurred\n"); +#endif + ddi_power_handle_vdd5v_droop(); + + return IRQ_HANDLED; +} + +#endif /* if POWER_FIQ */ + +static irqreturn_t mxs_irq_vddio_brnout(int irq, void *cookie) +{ +#ifdef DEBUG_IRQS + struct mxs_info *info = (struct mxs_info *)cookie; + dev_info(info->dev, "vddio brownout interrupt occurred\n"); + ddi_power_disable_power_interrupts(); +#else + ddi_power_handle_vddio_brnout(); +#endif + return IRQ_HANDLED; +} + +static irqreturn_t mxs_irq_vdd5v(int irq, void *cookie) +{ + struct mxs_info *info = (struct mxs_info *)cookie; + + switch (ddi_power_GetPmu5vStatus()) { + + case new_5v_connection: + + ddi_power_disable_5v_connection_irq(); + dev_dbg(info->dev, "new 5v connection detected\n"); + info->sm_new_5v_connection_jiffies = jiffies; + mod_timer(&info->sm_timer, jiffies + 1); + break; + + case new_5v_disconnection: + + /* due to 5v connect vddio bo chip bug, we need to + * disable vddio interrupts until we reset the 5v + * detection for 5v connect detect. We want to allow + * some debounce time before enabling connect detection. + * This is handled in the vdd5v_droop interrupt for now. + */ + /* ddi_power_enable_vddio_interrupt(false); */ + + ddi_power_disable_5v_connection_irq(); + dev_dbg(info->dev, "new 5v disconnection detected\n"); + info->sm_new_5v_disconnection_jiffies = jiffies; + mod_timer(&info->sm_timer, jiffies + 1); + break; + + default: + + break; + + } + + return IRQ_HANDLED; +} + +static int mxs_bat_probe(struct platform_device *pdev) +{ + struct mxs_info *info; + int ret = 0; + + + /* enable usb device presence detection */ + fsl_enable_usb_plugindetect(); + + ret = ddi_power_init_battery(); + if (ret) { + printk(KERN_ERR "Aborting power driver initialization\n"); + return 1; + } + + + if (!pdev->dev.platform_data) { + printk(KERN_ERR "%s: missing platform data\n", __func__); + return -ENODEV; + } + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->irq_vdd5v = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (info->irq_vdd5v == NULL) { + printk(KERN_ERR "%s: failed to get irq resouce\n", __func__); + goto free_info; + } + + info->irq_vddio_brnout = platform_get_resource( + pdev, IORESOURCE_IRQ, 5); + if (info->irq_vddio_brnout == NULL) { + printk(KERN_ERR "%s: failed to get irq resouce\n", __func__); + goto free_info; + } + +#ifndef POWER_FIQ + info->irq_dcdc4p2_bo = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + if (info->irq_dcdc4p2_bo == NULL) { + printk(KERN_ERR "%s: failed to get irq resouce\n", __func__); + goto free_info; + } + + info->irq_batt_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 2); + if (info->irq_batt_brnout == NULL) { + printk(KERN_ERR "%s: failed to get irq resouce\n", __func__); + goto free_info; + } + + info->irq_vddd_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 3); + if (info->irq_vddd_brnout == NULL) { + printk(KERN_ERR "%s: failed to get irq resouce\n", __func__); + goto free_info; + } + + info->irq_vdda_brnout = platform_get_resource(pdev, IORESOURCE_IRQ, 4); + if (info->irq_vdda_brnout == NULL) { + printk(KERN_ERR "%s: failed to get irq resouce\n", __func__); + goto free_info; + } + + + info->irq_vdd5v_droop = platform_get_resource(pdev, IORESOURCE_IRQ, 6); + if (info->irq_vdd5v_droop == NULL) { + printk(KERN_ERR "%s: failed to get irq resouce\n", __func__); + goto free_info; + } +#endif + + + platform_set_drvdata(pdev, info); + + info->dev = &pdev->dev; + info->sm_cfg = pdev->dev.platform_data; + + /* initialize bat power_supply struct */ + info->bat.name = "battery"; + info->bat.type = POWER_SUPPLY_TYPE_BATTERY; + info->bat.properties = mxs_bat_props; + info->bat.num_properties = ARRAY_SIZE(mxs_bat_props); + info->bat.get_property = mxs_bat_get_property; + + /* initialize ac power_supply struct */ + info->ac.name = "ac"; + info->ac.type = POWER_SUPPLY_TYPE_MAINS; + info->ac.properties = mxs_power_props; + info->ac.num_properties = ARRAY_SIZE(mxs_power_props); + info->ac.get_property = mxs_power_get_property; + + /* initialize usb power_supply struct */ + info->usb.name = "usb"; + info->usb.type = POWER_SUPPLY_TYPE_USB; + info->usb.properties = mxs_power_props; + info->usb.num_properties = ARRAY_SIZE(mxs_power_props); + info->usb.get_property = mxs_power_get_property; + + init_timer(&info->sm_timer); + info->sm_timer.data = (unsigned long)info; + info->sm_timer.function = state_machine_timer; + + mutex_init(&info->sm_lock); + INIT_WORK(&info->sm_work, state_machine_work); + + /* init LRADC channels to measure battery voltage and die temp */ + + __raw_writel(BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT, + REGS_POWER_BASE + HW_POWER_5VCTRL_CLR); + + ret = bc_sm_restart(info); + if (ret) + goto free_info; + + + ret = request_irq(info->irq_vdd5v->start, + mxs_irq_vdd5v, IRQF_DISABLED | IRQF_SHARED, + pdev->name, info); + if (ret) { + dev_err(info->dev, "failed to request irq\n"); + goto stop_sm; + } + + ret = request_irq(info->irq_vddio_brnout->start, + mxs_irq_vddio_brnout, IRQF_DISABLED, + pdev->name, info); + if (ret) { + dev_err(info->dev, "failed to request irq\n"); + goto stop_sm; + } + +#ifndef POWER_FIQ + ret = request_irq(info->irq_dcdc4p2_bo->start, + mxs_irq_dcdc4p2_bo, IRQF_DISABLED, + pdev->name, info); + if (ret) { + dev_err(info->dev, "failed to request irq\n"); + goto stop_sm; + } + + ret = request_irq(info->irq_batt_brnout->start, + mxs_irq_batt_brnout, IRQF_DISABLED, + pdev->name, info); + if (ret) { + dev_err(info->dev, "failed to request irq\n"); + goto stop_sm; + } + + ret = request_irq(info->irq_vddd_brnout->start, + mxs_irq_vddd_brnout, IRQF_DISABLED, + pdev->name, info); + if (ret) { + dev_err(info->dev, "failed to request irq\n"); + goto stop_sm; + } + + ret = request_irq(info->irq_vdda_brnout->start, + mxs_irq_vdda_brnout, IRQF_DISABLED, + pdev->name, info); + if (ret) { + dev_err(info->dev, "failed to request irq\n"); + goto stop_sm; + } + + + ret = request_irq(info->irq_vdd5v_droop->start, + mxs_irq_vdd5v_droop, IRQF_DISABLED, + pdev->name, info); + if (ret) { + dev_err(info->dev, "failed to request irq\n"); + goto stop_sm; + } +#endif + + ret = power_supply_register(&pdev->dev, &info->bat); + if (ret) { + dev_err(info->dev, "failed to register battery\n"); + goto free_irq; + } + + ret = power_supply_register(&pdev->dev, &info->ac); + if (ret) { + dev_err(info->dev, "failed to register ac power supply\n"); + goto unregister_bat; + } + + ret = power_supply_register(&pdev->dev, &info->usb); + if (ret) { + dev_err(info->dev, "failed to register usb power supply\n"); + goto unregister_ac; + } + + /* handoff protection handling from bootlets protection method + * to kernel protection method + */ + init_protection(info); + + + info->onboard_vbus5v = regulator_get(NULL, "vbus5v"); + if (IS_ERR(info->regulator)) { + + pr_debug("No onboard vbus 5v reg provided\n"); + info->onboard_vbus5v = NULL; + } + return 0; + +unregister_ac: + power_supply_unregister(&info->ac); +unregister_bat: + power_supply_unregister(&info->bat); +free_irq: + free_irq(info->irq_vdd5v->start, pdev); + free_irq(info->irq_vddio_brnout->start, pdev); +#ifndef POWER_FIQ + free_irq(info->irq_dcdc4p2_bo->start, pdev); + free_irq(info->irq_batt_brnout->start, pdev); + free_irq(info->irq_vddd_brnout->start, pdev); + free_irq(info->irq_vdda_brnout->start, pdev); + free_irq(info->irq_vdd5v_droop->start, pdev); +#endif + +stop_sm: + ddi_bc_ShutDown(); +free_info: + kfree(info); + return ret; +} + +static int mxs_bat_remove(struct platform_device *pdev) +{ + struct mxs_info *info = platform_get_drvdata(pdev); + + if (info->regulator) + regulator_put(info->regulator); + free_irq(info->irq_vdd5v->start, pdev); + free_irq(info->irq_vddio_brnout->start, pdev); +#ifndef POWER_FIQ + free_irq(info->irq_dcdc4p2_bo->start, pdev); + free_irq(info->irq_batt_brnout->start, pdev); + free_irq(info->irq_vddd_brnout->start, pdev); + free_irq(info->irq_vdda_brnout->start, pdev); + free_irq(info->irq_vdd5v_droop->start, pdev); +#endif + ddi_bc_ShutDown(); + power_supply_unregister(&info->usb); + power_supply_unregister(&info->ac); + power_supply_unregister(&info->bat); + return 0; +} + +static void mxs_bat_shutdown(struct platform_device *pdev) +{ + ddi_bc_ShutDown(); +} + + +#ifdef CONFIG_PM + +static int mxs_bat_suspend(struct platform_device *pdev, pm_message_t msg) +{ + struct mxs_info *info = platform_get_drvdata(pdev); + + mutex_lock(&info->sm_lock); + + /* enable USB 5v wake up so don't disable irq here*/ + + ddi_bc_SetDisable(); + /* cancel state machine timer */ + del_timer_sync(&info->sm_timer); + + mutex_unlock(&info->sm_lock); + return 0; +} + +static int mxs_bat_resume(struct platform_device *pdev) +{ + struct mxs_info *info = platform_get_drvdata(pdev); + ddi_bc_Cfg_t *cfg = info->sm_cfg; + + mutex_lock(&info->sm_lock); + + if (is_ac_online()) { + /* ac supply connected */ + dev_dbg(info->dev, "ac/5v present, enabling state machine\n"); + + info->is_ac_online = 1; + info->is_usb_online = 0; + ddi_bc_SetCurrentLimit( + NON_USB_5V_SUPPLY_CURRENT_LIMIT_MA /*mA*/); + ddi_bc_SetEnable(); + } else if (is_usb_online()) { + /* usb supply connected */ + dev_dbg(info->dev, "usb/5v present, enabling state machine\n"); + + info->is_ac_online = 0; + info->is_usb_online = 1; + ddi_bc_SetCurrentLimit(POWERED_USB_5V_CURRENT_LIMIT_MA /*mA*/); + ddi_bc_SetEnable(); + } else { + /* not powered */ + dev_dbg(info->dev, "%s: 5v not present\n", __func__); + + info->is_ac_online = 0; + info->is_usb_online = 0; + } + + /* enable 5v irq */ + __raw_writel(BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + + /* reschedule calls to state machine */ + mod_timer(&info->sm_timer, + jiffies + msecs_to_jiffies(cfg->u32StateMachinePeriod)); + + mutex_unlock(&info->sm_lock); + return 0; +} + +#else +#define mxs_bat_suspend NULL +#define mxs_bat_resume NULL +#endif + +static struct platform_driver mxs_batdrv = { + .probe = mxs_bat_probe, + .remove = mxs_bat_remove, + .shutdown = mxs_bat_shutdown, + .suspend = mxs_bat_suspend, + .resume = mxs_bat_resume, + .driver = { + .name = "mxs-battery", + .owner = THIS_MODULE, + }, +}; + +#ifdef POWER_FIQ +static int power_relinquish(void *data, int relinquish) +{ + return -1; +} + +static struct fiq_handler power_fiq = { + .name = "mxs-battery", + .fiq_op = power_relinquish +}; + +static struct pt_regs fiq_regs; +extern char power_fiq_start[], power_fiq_end[]; +extern void lock_vector_tlb(void *); +extern long power_fiq_count; +static struct proc_dir_entry *power_fiq_proc; +#endif + +static int __init mxs_bat_init(void) +{ + struct clk *cpu, *pll0; + +#ifdef POWER_FIQ + int ret; + ret = claim_fiq(&power_fiq); + if (ret) { + pr_err("Can't claim fiq"); + } else { + get_fiq_regs(&fiq_regs); + set_fiq_handler(power_fiq_start, power_fiq_end-power_fiq_start); + lock_vector_tlb((void *)0xffff0000); + lock_vector_tlb(REGS_POWER_BASE); + + /* disable interrupts to be configured as FIQs */ + disable_irq(IRQ_DCDC4P2_BRNOUT); + disable_irq(IRQ_BATT_BRNOUT); + disable_irq(IRQ_VDDD_BRNOUT); +#ifndef CONFIG_ARCH_MX28 + disable_irq(IRQ_VDD18_BRNOUT); +#endif + disable_irq(IRQ_VDD5V_DROOP); + + + /* Enable these interrupts as FIQs */ + mxs_set_irq_fiq(IRQ_DCDC4P2_BRNOUT, 1); + mxs_set_irq_fiq(IRQ_BATT_BRNOUT, 1); + mxs_set_irq_fiq(IRQ_VDDD_BRNOUT, 1); +#ifndef CONFIG_ARCH_MX28 + mxs_set_irq_fiq(IRQ_VDD18_BRNOUT, 1); +#endif + mxs_set_irq_fiq(IRQ_VDD5V_DROOP, 1); + + + /* enable FIQ functionality */ + mxs_enable_fiq_functionality(1); + + enable_irq(IRQ_DCDC4P2_BRNOUT); + enable_irq(IRQ_BATT_BRNOUT); + enable_irq(IRQ_VDDD_BRNOUT); +#ifndef CONFIG_ARCH_MX28 + enable_irq(IRQ_VDD18_BRNOUT); +#endif + enable_irq(IRQ_VDD5V_DROOP); + + } +#endif + +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + if (((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) & + BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x20000) + && ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) & + BM_POWER_5VCTRL_PWD_CHARGE_4P2) == 0)) { +#ifdef CONFIG_USB_GADGET + printk(KERN_INFO "USB GADGET exist,wait USB enum done...\r\n"); + while (((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) + & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x20000) && + ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) & + BM_POWER_5VCTRL_PWD_CHARGE_4P2) == 0)) + ; +#else + printk(KERN_INFO "USB GADGET not exist,\ + release current limit and let CPU clock up...\r\n"); +#endif + } + cpu = clk_get(NULL, "cpu"); + pll0 = clk_get(NULL, "ref_cpu"); + clk_set_parent(cpu, pll0); +#endif + return platform_driver_register(&mxs_batdrv); +} + +static void __exit mxs_bat_exit(void) +{ + platform_driver_unregister(&mxs_batdrv); +} +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + fs_initcall(mxs_bat_init); +#else + module_init(mxs_bat_init); +#endif +module_exit(mxs_bat_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Steve Longerbeam "); +MODULE_DESCRIPTION("Linux glue to MXS battery state machine"); diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 04f2e085116a..694c2e6e539d 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -201,5 +201,42 @@ config REGULATOR_88PM8607 help This driver supports 88PM8607 voltage regulator chips. +config REGULATOR_MC13892 + tristate "MC13892 Regulator Support" + depends on MXC_PMIC_MC13892 + default y + +config REGULATOR_MC34704 + tristate "MC34704 Regulator Support" + depends on MXC_PMIC_MC34704 + default y + +config REGULATOR_LTC3589 + tristate "LTC3589 Regulator Support" + depends on MFD_LTC3589_I2C + depends on REGULATOR + default n + +config REGULATOR_MXS + tristate "MXS Regulator Support" + depends on ARCH_MXS + default y + +config REGULATOR_MC9S08DZ60 + tristate "mc9s08dz60 Regulator Support" + depends on MXC_PMIC_MC9S08DZ60 + default y + +config REGULATOR_MAX17135 + tristate "Maxim MAX17135 Regulator Support" + depends on MFD_MAX17135 + default n + +config REGULATOR_DA9052 + tristate "Dialog DA9052 regulators" + depends on PMIC_DA9052 + help + Say y here to support the BUCKs and LDOs regulators found on + Dialog Semiconductor DA9052 PMIC. endif diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 4e7feece22d5..850fdd8d45fa 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -2,7 +2,6 @@ # Makefile for regulator drivers. # - obj-$(CONFIG_REGULATOR) += core.o obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o @@ -32,4 +31,16 @@ obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o +obj-$(CONFIG_REGULATOR_DA9052) += da9052-regulator.o + +obj-$(CONFIG_REGULATOR_MAX17135) += max17135-regulator.o + +obj-$(CONFIG_REGULATOR_MC13892) += reg-mc13892.o +obj-$(CONFIG_REGULATOR_MC34704) += reg-mc34704.o +obj-$(CONFIG_REGULATOR_STMP3XXX) += stmp3xxx.o +obj-$(CONFIG_REGULATOR_MXS) += mxs-regulator.o +obj-$(CONFIG_REGULATOR_LTC3589) += ltc3589-regulator.o + +obj-$(CONFIG_REGULATOR_MC9S08DZ60) += reg-mc9s08dz60.o + ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 2248087b9be2..af6ebc027884 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -1108,6 +1108,11 @@ static struct regulator *_regulator_get(struct device *dev, const char *id, goto found; } } + list_for_each_entry(rdev, ®ulator_list, list) { + if (strcmp(rdev->desc->name, id) == 0) { + goto found; + } + } #ifdef CONFIG_REGULATOR_DUMMY if (!devname) diff --git a/drivers/regulator/da9052-regulator.c b/drivers/regulator/da9052-regulator.c new file mode 100644 index 000000000000..34452839570c --- /dev/null +++ b/drivers/regulator/da9052-regulator.c @@ -0,0 +1,547 @@ +/* + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * da9052-regulator.c: Regulator driver for DA9052 + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static struct regulator_ops da9052_ldo_buck_ops; + + +struct regulator { + struct device *dev; + struct list_head list; + int uA_load; + int min_uV; + int max_uV; + int enabled; /* client has called enabled */ + char *supply_name; + struct device_attribute dev_attr; + struct regulator_dev *rdev; +}; + + + + +#define DA9052_LDO(_id, max, min, step_v, reg, mbits, cbits) \ +{\ + .reg_desc = {\ + .name = #_id,\ + .ops = &da9052_ldo_buck_ops,\ + .type = REGULATOR_VOLTAGE,\ + .id = _id,\ + .owner = THIS_MODULE,\ + },\ + .reg_const = {\ + .max_uV = (max) * 1000,\ + .min_uV = (min) * 1000,\ + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE\ + | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE,\ + .valid_modes_mask = REGULATOR_MODE_NORMAL,\ + },\ + .step_uV = (step_v) * 1000,\ + .reg_add = (reg),\ + .mask_bits = (mbits),\ + .en_bit_mask = (cbits),\ +} + +struct regulator_info { + struct regulator_desc reg_desc; + struct regulation_constraints reg_const; + int step_uV; + unsigned char reg_add; + unsigned char mask_bits; + unsigned char en_bit_mask; +}; + +struct da9052_regulator_priv { + struct da9052 *da9052; + struct regulator_dev *regulators[]; +}; + +struct regulator_info da9052_regulators[] = { + /* LD01 - LDO10*/ + DA9052_LDO(DA9052_LDO1, DA9052_LDO1_VOLT_UPPER, DA9052_LDO1_VOLT_LOWER, + DA9052_LDO1_VOLT_STEP, DA9052_LDO1_REG, + DA9052_LDO1_VLDO1, DA9052_LDO1_LDO1EN), + + DA9052_LDO(DA9052_LDO2, + DA9052_LDO2_VOLT_UPPER, DA9052_LDO2_VOLT_LOWER, + DA9052_LDO2_VOLT_STEP, DA9052_LDO2_REG, + DA9052_LDO2_VLDO2, + DA9052_LDO2_LDO2EN), + + DA9052_LDO(DA9052_LDO3, DA9052_LDO34_VOLT_UPPER, + DA9052_LDO34_VOLT_LOWER, + DA9052_LDO34_VOLT_STEP, DA9052_LDO3_REG, + DA9052_LDO3_VLDO3, DA9052_LDO3_LDO3EN), + + DA9052_LDO(DA9052_LDO4, DA9052_LDO34_VOLT_UPPER, + DA9052_LDO34_VOLT_LOWER, + DA9052_LDO34_VOLT_STEP, DA9052_LDO4_REG, + DA9052_LDO4_VLDO4, DA9052_LDO4_LDO4EN), + + DA9052_LDO(DA9052_LDO5, DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, + DA9052_LDO567810_VOLT_STEP, DA9052_LDO5_REG, + DA9052_LDO5_VLDO5, DA9052_LDO5_LDO5EN), + + DA9052_LDO(DA9052_LDO6, DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, + DA9052_LDO567810_VOLT_STEP, DA9052_LDO6_REG, + DA9052_LDO6_VLDO6, DA9052_LDO6_LDO6EN), + + DA9052_LDO(DA9052_LDO7, DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, + DA9052_LDO567810_VOLT_STEP, DA9052_LDO7_REG, + DA9052_LDO7_VLDO7, DA9052_LDO7_LDO7EN), + + DA9052_LDO(DA9052_LDO8, DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, + DA9052_LDO567810_VOLT_STEP, DA9052_LDO8_REG, + DA9052_LDO8_VLDO8, DA9052_LDO8_LDO8EN), + + DA9052_LDO(DA9052_LDO9, DA9052_LDO9_VOLT_UPPER, + DA9052_LDO9_VOLT_LOWER, + DA9052_LDO9_VOLT_STEP, + DA9052_LDO9_REG, DA9052_LDO9_VLDO9, + DA9052_LDO9_LDO9EN), + + DA9052_LDO(DA9052_LDO10, DA9052_LDO567810_VOLT_UPPER, + DA9052_LDO567810_VOLT_LOWER, + DA9052_LDO567810_VOLT_STEP, DA9052_LDO10_REG, + DA9052_LDO10_VLDO10, DA9052_LDO10_LDO10EN), + + /* BUCKS */ + DA9052_LDO(DA9052_BUCK_CORE, DA9052_BUCK_CORE_PRO_VOLT_UPPER, + DA9052_BUCK_CORE_PRO_VOLT_LOWER, + DA9052_BUCK_CORE_PRO_STEP, DA9052_BUCKCORE_REG, + DA9052_BUCKCORE_VBCORE, DA9052_BUCKCORE_BCOREEN), + + DA9052_LDO(DA9052_BUCK_PRO, DA9052_BUCK_CORE_PRO_VOLT_UPPER, + DA9052_BUCK_CORE_PRO_VOLT_LOWER, + DA9052_BUCK_CORE_PRO_STEP, DA9052_BUCKPRO_REG, + DA9052_BUCKPRO_VBPRO, DA9052_BUCKPRO_BPROEN), + + DA9052_LDO(DA9052_BUCK_MEM, DA9052_BUCK_MEM_VOLT_UPPER, + DA9052_BUCK_MEM_VOLT_LOWER, + DA9052_BUCK_MEM_STEP, DA9052_BUCKMEM_REG, + DA9052_BUCKMEM_VBMEM, DA9052_BUCKMEM_BMEMEN), + + DA9052_LDO(DA9052_BUCK_PERI, DA9052_BUCK_PERI_VOLT_UPPER, + DA9052_BUCK_PERI_VOLT_LOWER, + DA9052_BUCK_PERI_STEP_BELOW_3000, DA9052_BUCKPERI_REG, + DA9052_BUCKPERI_VBPERI, DA9052_BUCKPERI_BPERIEN), +}; + +int da9052_ldo_buck_enable(struct regulator_dev *rdev) +{ + struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev); + int id = rdev_get_id(rdev); + int ret = 0; + struct da9052_ssc_msg ssc_msg; + + ssc_msg.addr = da9052_regulators[id].reg_add; + ssc_msg.data = 0; + + da9052_lock(priv->da9052); + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + + ssc_msg.data = (ssc_msg.data | da9052_regulators[id].en_bit_mask); + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + da9052_unlock(priv->da9052); + + return 0; +} +EXPORT_SYMBOL_GPL(da9052_ldo_buck_enable); +/* Code added by KPIT to support additional attribure in sysfs - changestate */ + + + +int da9052_ldo_buck_disable(struct regulator_dev *rdev) +{ + struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev); + int id = rdev_get_id(rdev); + int ret; + struct da9052_ssc_msg ssc_msg; + + ssc_msg.addr = da9052_regulators[id].reg_add; + ssc_msg.data = 0; + + da9052_lock(priv->da9052); + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + + ssc_msg.data = (ssc_msg.data & ~(da9052_regulators[id].en_bit_mask)); + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + da9052_unlock(priv->da9052); + + return 0; +} +EXPORT_SYMBOL_GPL(da9052_ldo_buck_disable); +/* Code added by KPIT to support additional attribure in sysfs - changestate */ + +static int da9052_ldo_buck_is_enabled(struct regulator_dev *rdev) +{ + struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev); + int id = rdev_get_id(rdev); + int ret; + struct da9052_ssc_msg ssc_msg; + ssc_msg.addr = da9052_regulators[id].reg_add; + ssc_msg.data = 0; + + da9052_lock(priv->da9052); + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + da9052_unlock(priv->da9052); + return (ssc_msg.data & da9052_regulators[id].en_bit_mask) != 0; +} + +int da9052_ldo_buck_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV) +{ + struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev); + struct da9052_ssc_msg ssc_msg; + int id = rdev_get_id(rdev); + int ret; + int ldo_volt = 0; + + /* KPIT - Below if condition is there for added setvoltage attribute + in sysfs */ + if (0 == max_uV) + max_uV = da9052_regulators[id].reg_const.max_uV; + + /* Compare voltage range */ + if (min_uV > max_uV) + return -EINVAL; + + /* Check Minimum/ Maximum voltage range */ + if (min_uV < da9052_regulators[id].reg_const.min_uV || + min_uV > da9052_regulators[id].reg_const.max_uV) + return -EINVAL; + if (max_uV < da9052_regulators[id].reg_const.min_uV || + max_uV > da9052_regulators[id].reg_const.max_uV) + return -EINVAL; + + /* Get the ldo register value */ + /* Varying step size for BUCK PERI */ + if ((da9052_regulators[id].reg_desc.id == DA9052_BUCK_PERI) && + (min_uV >= DA9052_BUCK_PERI_VALUES_3000)) { + ldo_volt = (DA9052_BUCK_PERI_VALUES_3000 - + da9052_regulators[id].reg_const.min_uV)/ + (da9052_regulators[id].step_uV); + ldo_volt += (min_uV - DA9052_BUCK_PERI_VALUES_3000)/ + (DA9052_BUCK_PERI_STEP_ABOVE_3000); + } else{ + ldo_volt = (min_uV - da9052_regulators[id].reg_const.min_uV)/ + (da9052_regulators[id].step_uV); + /* Check for maximum value */ + if ((ldo_volt * da9052_regulators[id].step_uV) + + da9052_regulators[id].reg_const.min_uV > max_uV) + return -EINVAL; + } + + /* Configure LDO Voltage, CONF bits */ + ssc_msg.addr = da9052_regulators[id].reg_add; + ssc_msg.data = 0; + + /* Read register */ + da9052_lock(priv->da9052); + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + + ssc_msg.data = (ssc_msg.data & ~(da9052_regulators[id].mask_bits)); + ssc_msg.data |= ldo_volt; + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + + /* Set the GO LDO/BUCk bits so that the voltage changes */ + ssc_msg.addr = DA9052_SUPPLY_REG; + ssc_msg.data = 0; + + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + + switch (id) { + case DA9052_LDO2: + ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VLDO2GO); + break; + case DA9052_LDO3: + ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VLDO3GO); + break; + case DA9052_BUCK_CORE: + ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VBCOREGO); + break; + case DA9052_BUCK_PRO: + ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VBPROGO); + break; + case DA9052_BUCK_MEM: + ssc_msg.data = (ssc_msg.data | DA9052_SUPPLY_VBMEMGO); + break; + default: + da9052_unlock(priv->da9052); + return -EINVAL; + } + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + + da9052_unlock(priv->da9052); + + return 0; +} +EXPORT_SYMBOL_GPL(da9052_ldo_buck_set_voltage); +/* Code added by KPIT to support additional attributes in sysfs - setvoltage */ + + +int da9052_ldo_buck_get_voltage(struct regulator_dev *rdev) +{ + struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev); + struct da9052_ssc_msg ssc_msg; + int id = rdev_get_id(rdev); + int ldo_volt = 0; + int ldo_volt_uV = 0; + int ret; + + ssc_msg.addr = da9052_regulators[id].reg_add; + ssc_msg.data = 0; + /* Read register */ + da9052_lock(priv->da9052); + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + da9052_unlock(priv->da9052); + + ldo_volt = ssc_msg.data & da9052_regulators[id].mask_bits; + if (da9052_regulators[id].reg_desc.id == DA9052_BUCK_PERI) { + if (ldo_volt >= DA9052_BUCK_PERI_VALUES_UPTO_3000) { + ldo_volt_uV = ((DA9052_BUCK_PERI_VALUES_UPTO_3000 * + da9052_regulators[id].step_uV) + + da9052_regulators[id].reg_const.min_uV); + ldo_volt_uV = (ldo_volt_uV + + (ldo_volt - DA9052_BUCK_PERI_VALUES_UPTO_3000) + * (DA9052_BUCK_PERI_STEP_ABOVE_3000)); + } else { + ldo_volt_uV = + (ldo_volt * da9052_regulators[id].step_uV) + + da9052_regulators[id].reg_const.min_uV; + } + } else { + ldo_volt_uV = (ldo_volt * da9052_regulators[id].step_uV) + + da9052_regulators[id].reg_const.min_uV; + } + return ldo_volt_uV; +} +EXPORT_SYMBOL_GPL(da9052_ldo_buck_get_voltage); +/* Code added by KPIT to support additional attributes in sysfs - setvoltage */ + +static int da9052_set_suspend_voltage(struct regulator_dev *rdev, int uV) +{ + struct da9052_regulator_priv *priv = rdev_get_drvdata(rdev); + struct da9052_ssc_msg ssc_msg; + int id = rdev_get_id(rdev); + int ret; + int ldo_volt = 0; + + + /* Check Minimum/ Maximum voltage range */ + if (uV < da9052_regulators[id].reg_const.min_uV || + uV > da9052_regulators[id].reg_const.max_uV) + return -EINVAL; + + /* Get the ldo register value */ + /* Varying step size for BUCK PERI */ + if ((da9052_regulators[id].reg_desc.id == DA9052_BUCK_PERI) && + (uV >= DA9052_BUCK_PERI_VALUES_3000)) { + ldo_volt = (DA9052_BUCK_PERI_VALUES_3000 - + da9052_regulators[id].reg_const.min_uV)/ + (da9052_regulators[id].step_uV); + ldo_volt += (uV - DA9052_BUCK_PERI_VALUES_3000)/ + (DA9052_BUCK_PERI_STEP_ABOVE_3000); + } else{ + ldo_volt = (uV - da9052_regulators[id].reg_const.min_uV)/ + (da9052_regulators[id].step_uV); + } + ldo_volt |= 0x80; + dev_info(&rdev->dev, "preset to %d %x\n", uV, ldo_volt); + + /* Configure LDO Voltage, CONF bits */ + ssc_msg.addr = da9052_regulators[id].reg_add; + ssc_msg.data = 0; + + /* Read register */ + da9052_lock(priv->da9052); + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + + ssc_msg.data = (ssc_msg.data & ~(da9052_regulators[id].mask_bits)); + ssc_msg.data |= ldo_volt; + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret) { + da9052_unlock(priv->da9052); + return -EIO; + } + + da9052_unlock(priv->da9052); + + return 0; +} + +static int da9052_ldo_buck_stby_enable(struct regulator_dev *reg) +{ + return 0; +} + +static int da9052_ldo_buck_stby_disable(struct regulator_dev *reg) +{ + return 0; +} + +static int da9052_ldo_buck_stby_set_mode(struct regulator_dev *reg, + unsigned int mode) +{ + return 0; +} + + +static struct regulator_ops da9052_ldo_buck_ops = { + .is_enabled = da9052_ldo_buck_is_enabled, + .enable = da9052_ldo_buck_enable, + .disable = da9052_ldo_buck_disable, + .get_voltage = da9052_ldo_buck_get_voltage, + .set_voltage = da9052_ldo_buck_set_voltage, + .set_suspend_voltage = da9052_set_suspend_voltage, + .set_suspend_enable = da9052_ldo_buck_stby_enable, + .set_suspend_disable = da9052_ldo_buck_stby_disable, + .set_suspend_mode = da9052_ldo_buck_stby_set_mode, +}; + + +static int __devinit da9052_regulator_probe(struct platform_device *pdev) +{ + struct da9052_regulator_priv *priv; + struct da9052_regulator_platform_data *pdata = + (pdev->dev.platform_data); + struct da9052 *da9052 = dev_get_drvdata(pdev->dev.parent); + struct regulator_init_data *init_data; + int i, ret = 0; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + priv->da9052 = da9052; + for (i = 0; i < 14; i++) { + + init_data = &pdata->regulators[i]; + init_data->driver_data = da9052; + pdev->dev.platform_data = init_data; + priv->regulators[i] = regulator_register( + &da9052_regulators[i].reg_desc, + &pdev->dev, init_data, + priv); + if (IS_ERR(priv->regulators[i])) { + ret = PTR_ERR(priv->regulators[i]); + goto err; + } + } + platform_set_drvdata(pdev, priv); + return 0; +err: + while (--i >= 0) + regulator_unregister(priv->regulators[i]); + kfree(priv); + return ret; +} + +static int __devexit da9052_regulator_remove(struct platform_device *pdev) +{ + struct da9052_regulator_priv *priv = platform_get_drvdata(pdev); + struct da9052_platform_data *pdata = pdev->dev.platform_data; + int i; + + for (i = 0; i < pdata->num_regulators; i++) + regulator_unregister(priv->regulators[i]); + + return 0; +} + +static struct platform_driver da9052_regulator_driver = { + .probe = da9052_regulator_probe, + .remove = __devexit_p(da9052_regulator_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init da9052_regulator_init(void) +{ + return platform_driver_register(&da9052_regulator_driver); +} +subsys_initcall(da9052_regulator_init); + +static void __exit da9052_regulator_exit(void) +{ + platform_driver_unregister(&da9052_regulator_driver); +} +module_exit(da9052_regulator_exit); + +MODULE_AUTHOR("David Dajun Chen "); +MODULE_DESCRIPTION("Power Regulator driver for Dialog DA9052 PMIC"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/regulator/ltc3589-regulator.c b/drivers/regulator/ltc3589-regulator.c new file mode 100644 index 000000000000..b81552e94316 --- /dev/null +++ b/drivers/regulator/ltc3589-regulator.c @@ -0,0 +1,1052 @@ + /* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file ltc3589-regulator.c + * @brief This is the main file for the Linear PMIC regulator driver. i2c + * should be providing the interface between the PMIC and the MCU. + * + * @ingroup PMIC_CORE + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register definitions */ +#define LTC3589_REG_IRSTAT 0x02 +#define LTC3589_REG_SCR1 0x07 +#define LTC3589_REG_OVEN 0x10 +#define LTC3589_REG_SCR2 0x12 +#define LTC3589_REG_PGSTAT 0x13 +#define LTC3589_REG_VCCR 0x20 +#define LTC3589_REG_CLIRQ 0x21 +#define LTC3589_REG_B1DTV1 0x23 +#define LTC3589_REG_B1DTV2 0x24 +#define LTC3589_REG_VRRCR 0x25 +#define LTC3589_REG_B2DTV1 0x26 +#define LTC3589_REG_B2DTV2 0x27 +#define LTC3589_REG_B3DTV1 0x29 +#define LTC3589_REG_B3DTV2 0x2A +#define LTC3589_REG_L2DTV1 0x32 +#define LTC3589_REG_L2DTV2 0x33 + +/* SCR1 bitfields */ +#define LTC3589_SCR1_ BIT(7) +#define LTC3589_PGOODZ_LOWBATTZ BIT(6) +#define LTC3589_PGOODZ_VDCDC1 BIT(5) +#define LTC3589_PGOODZ_VDCDC2 BIT(4) +#define LTC3589_PGOODZ_VDCDC3 BIT(3) +#define LTC3589_PGOODZ_LDO2 BIT(2) +#define LTC3589_PGOODZ_LDO1 BIT(1) + +/* MASK bitfields */ +#define LTC3589_MASK_PWRFAILZ BIT(7) +#define LTC3589_MASK_LOWBATTZ BIT(6) +#define LTC3589_MASK_VDCDC1 BIT(5) +#define LTC3589_MASK_VDCDC2 BIT(4) +#define LTC3589_MASK_VDCDC3 BIT(3) +#define LTC3589_MASK_LDO2 BIT(2) +#define LTC3589_MASK_LDO1 BIT(1) + +/* REG_CTRL bitfields */ +#define LTC3589_REG_CTRL_VDCDC1_EN BIT(5) +#define LTC3589_REG_CTRL_VDCDC2_EN BIT(4) +#define LTC3589_REG_CTRL_VDCDC3_EN BIT(3) +#define LTC3589_REG_CTRL_LDO2_EN BIT(2) +#define LTC3589_REG_CTRL_LDO1_EN BIT(1) + +/* LDO_CTRL bitfields */ +#define LTC3589_LDO_CTRL_LDOx_SHIFT(ldo_id) ((ldo_id)*4) +#define LTC3589_LDO_CTRL_LDOx_MASK(ldo_id) (0xF0 >> ((ldo_id)*4)) + +/* Number of step-down converters available */ +#define LTC3589_NUM_DCDC 4 +/* Number of LDO voltage regulators available */ +#define LTC3589_NUM_LDO 4 +/* Number of total regulators available */ +#define LTC3589_NUM_REGULATOR (LTC3589_NUM_DCDC + LTC3589_NUM_LDO) + +/* DCDCs */ +#define LTC3589_DCDC_1 0 +#define LTC3589_DCDC_2 1 +#define LTC3589_DCDC_3 2 +#define LTC3589_DCDC_4 3 +/* LDOs */ +#define LTC3589_LDO_1 4 +#define LTC3589_LDO_2 5 +#define LTC3589_LDO_3 6 +#define LTC3589_LDO_4 7 +/* Resistorss */ +#define LTC3589_LDO2_R1 180 +#define LTC3589_LDO2_R2_TO1 232 +#define LTC3589_LDO2_R2_TO2 191 +#define LTC3589_SW1_R1 100 +#define LTC3589_SW1_R2 180 +#define LTC3589_SW2_R1 180 +#define LTC3589_SW2_R2_TO1 232 +#define LTC3589_SW2_R2_TO2 191 +#define LTC3589_SW3_R1 270 +#define LTC3589_SW3_R2 100 + +#define LTC3589_MAX_REG_ID LTC3589_LDO_4 + +/* Supported voltage values for regulators */ +static const u16 LDO4_VSEL_table[] = { + 2800, 2500, 1800, 3300, +}; + +struct i2c_client *ltc3589_client; + +/* Regulator specific details */ +struct ltc_info { + const char *name; + unsigned min_uV; + unsigned max_uV; + bool fixed; + u8 table_len; + const u16 *table; +}; + +/* PMIC details */ +struct ltc_pmic { + struct regulator_desc desc[LTC3589_NUM_REGULATOR]; + struct i2c_client *client; + struct regulator_dev *rdev[LTC3589_NUM_REGULATOR]; + const struct ltc_info *info[LTC3589_NUM_REGULATOR]; + struct mutex io_lock; +}; + +static int ltc3589_ldo2_r2; +static int ltc3589_sw2_r2; + +/* + * LTC3589 Device IO + */ +static DEFINE_MUTEX(io_mutex); + +static int ltc_3589_set_bits(struct ltc3589 *ltc, u8 reg, u8 mask) +{ + int err, data; + + mutex_lock(&io_mutex); + + data = ltc->read_dev(ltc, reg); + if (data < 0) { + dev_err(<c->i2c_client->dev, + "Read from reg 0x%x failed\n", reg); + err = data; + goto out; + } + + data |= mask; + err = ltc->write_dev(ltc, reg, data); + if (err) + dev_err(<c->i2c_client->dev, + "Write for reg 0x%x failed\n", reg); + +out: + mutex_unlock(&io_mutex); + return err; +} + +static int ltc_3589_clear_bits(struct ltc3589 *ltc, u8 reg, u8 mask) +{ + int err, data; + + mutex_lock(&io_mutex); + + data = ltc->read_dev(ltc, reg); + if (data < 0) { + dev_err(<c->i2c_client->dev, + "Read from reg 0x%x failed\n", reg); + err = data; + goto out; + } + + data &= ~mask; + + err = ltc->write_dev(ltc, reg, data); + if (err) + dev_err(<c->i2c_client->dev, + "Write for reg 0x%x failed\n", reg); + +out: + mutex_unlock(&io_mutex); + return err; + +} + +static int ltc_3589_reg_read(struct ltc3589 *ltc, u8 reg) +{ + int data; + + mutex_lock(&io_mutex); + + data = ltc->read_dev(ltc, reg); + if (data < 0) + dev_err(<c->i2c_client->dev, + "Read from reg 0x%x failed\n", reg); + + mutex_unlock(&io_mutex); + return data; +} + +static int ltc_3589_reg_write(struct ltc3589 *ltc, u8 reg, u8 val) +{ + int err; + + mutex_lock(&io_mutex); + + err = ltc->write_dev(ltc, reg, val); + if (err < 0) + dev_err(<c->i2c_client->dev, + "Write for reg 0x%x failed\n", reg); + + mutex_unlock(&io_mutex); + return err; +} + +int ltc3589_set_slew_rate(struct regulator_dev *dev, int rate) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int data, dcdc = rdev_get_id(dev); + + if (dcdc == LTC3589_DCDC_4 || dcdc == LTC3589_LDO_1 || + dcdc == LTC3589_LDO_3 || dcdc == LTC3589_LDO_4) + return 0; + + if (rate > 0x3) + return -EINVAL; + + data = ltc_3589_reg_read(ltc, LTC3589_REG_VRRCR); + if (data < 0) + return data; + + if (dcdc == LTC3589_LDO_2) + dcdc = 3; + + data &= ~(3 << (2 * dcdc)); + data |= (3 << (2 * dcdc)); + + ltc_3589_reg_write(ltc, LTC3589_REG_VRRCR, data); + + return 0; +} + +static int ltc3589_dcdc_is_enabled(struct regulator_dev *dev) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int data, dcdc = rdev_get_id(dev); + u8 shift; + + if (dcdc < LTC3589_DCDC_1 || dcdc > LTC3589_DCDC_4) + return -EINVAL; + + shift = dcdc; + data = ltc_3589_reg_read(ltc, LTC3589_REG_OVEN); + + if (data < 0) + return data; + else + return (data & 1< LTC3589_LDO_4) + return -EINVAL; + + if (ldo == LTC3589_LDO_1) + return 1; + + shift = ldo - 1; + data = ltc_3589_reg_read(ltc, LTC3589_REG_OVEN); + + if (data < 0) + return data; + else + return (data & 1< LTC3589_DCDC_4) + return -EINVAL; + + shift = dcdc; + return ltc_3589_set_bits(ltc, LTC3589_REG_OVEN, 1 << shift); +} + +static int ltc3589_dcdc_disable(struct regulator_dev *dev) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int dcdc = rdev_get_id(dev); + u8 shift; + + if (dcdc < LTC3589_DCDC_1 || dcdc > LTC3589_DCDC_4) + return -EINVAL; + + shift = dcdc; + return ltc_3589_clear_bits(ltc, LTC3589_REG_OVEN, 1 << shift); +} + +static int ltc3589_ldo_enable(struct regulator_dev *dev) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int ldo = rdev_get_id(dev); + u8 shift; + + if (ldo < LTC3589_LDO_1 || ldo > LTC3589_LDO_4) + return -EINVAL; + + if (ldo == LTC3589_LDO_1) { + printk(KERN_ERR "LDO1 is always enabled\n"); + return 0; + } + + shift = (ldo - 1); + return ltc_3589_set_bits(ltc, LTC3589_REG_OVEN, 1 << shift); +} + +static int ltc3589_ldo_disable(struct regulator_dev *dev) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int ldo = rdev_get_id(dev); + u8 shift; + + if (ldo < LTC3589_LDO_1 || ldo > LTC3589_LDO_4) + return -EINVAL; + + if (ldo == LTC3589_LDO_1) { + printk(KERN_ERR "LDO1 can not be disabled\n"); + return 0; + } + + shift = (ldo - 1); + return ltc_3589_clear_bits(ltc, LTC3589_REG_OVEN, 1 << shift); +} + +static int ltc3589_dcdc_set_mode(struct regulator_dev *dev, + unsigned int mode) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int dcdc = rdev_get_id(dev); + u16 val; + int data; + + if (dcdc < LTC3589_DCDC_1 || dcdc > LTC3589_DCDC_4) + return -EINVAL; + + val = 1 << (dcdc - LTC3589_DCDC_1); + data = ltc_3589_reg_read(ltc, LTC3589_REG_SCR1); + if (data < 0) + return data; + + data &= ~(3 << (2 * dcdc)); + + switch (mode) { + case REGULATOR_MODE_FAST: + /* burst mode */ + data |= (1 << (2 * dcdc)); + break; + case REGULATOR_MODE_NORMAL: + /* active / pulse skipping */ + data |= (0 << (2 * dcdc)); + break; + case REGULATOR_MODE_IDLE: + case REGULATOR_MODE_STANDBY: + /* force continuous mode */ + data |= (2 << (2 * dcdc)); + } + + return ltc_3589_reg_write(ltc, LTC3589_REG_SCR1, data);; +} + +static unsigned int ltc3589_dcdc_get_mode(struct regulator_dev *dev) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int dcdc = rdev_get_id(dev); + int data; + + data = ltc_3589_reg_read(ltc, LTC3589_REG_VCCR); + if (data < 0) + return data; + + if (dcdc == LTC3589_DCDC_4) { + data >>= (2 * dcdc); + data &= 0x01; + + if (data == 1) + return REGULATOR_MODE_FAST; + else + return REGULATOR_MODE_NORMAL; + } else { + data >>= (2 * dcdc); + data &= 0x03; + + switch (data) { + case 0: + return REGULATOR_MODE_NORMAL; + case 1: + return REGULATOR_MODE_FAST; + case 2: + return REGULATOR_MODE_IDLE; + } + } + + return 0; +} + +static int ltc3589_dcdc_get_voltage(struct regulator_dev *dev) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int volt_reg, data, dcdc = rdev_get_id(dev); + int shift, mask, r1, r2; + int uV; + + r1 = 0; + r2 = 1; + + if (dcdc < LTC3589_DCDC_1 || dcdc > LTC3589_DCDC_3) + return -EINVAL; + + data = ltc_3589_reg_read(ltc, LTC3589_REG_VCCR); + if (data < 0) + return data; + + switch (dcdc) { + case LTC3589_DCDC_1: + r1 = LTC3589_SW1_R1; + r2 = LTC3589_SW1_R2; + shift = LTC3589_B1DTV2_REG1_REF_INPUT_V2_SHIFT; + mask = LTC3589_B1DTV2_REG1_REF_INPUT_V2_MASK; + if (data & LTC3589_VCCR_REG1_REF_SELECT) + volt_reg = LTC3589_REG_B1DTV2; + else + volt_reg = LTC3589_REG_B1DTV1; + break; + case LTC3589_DCDC_2: + r1 = LTC3589_SW2_R1; + r2 = ltc3589_sw2_r2; + shift = LTC3589_B2DTV2_REG2_REF_INPUT_V2_SHIFT; + mask = LTC3589_B2DTV2_REG2_REF_INPUT_V2_MASK; + if (data & LTC3589_VCCR_REG2_REF_SELECT) + volt_reg = LTC3589_REG_B2DTV2; + else + volt_reg = LTC3589_REG_B2DTV1; + break; + case LTC3589_DCDC_3: + r1 = LTC3589_SW3_R1; + r2 = LTC3589_SW3_R2; + shift = LTC3589_B3DTV2_REG3_REF_INPUT_V2_SHIFT; + mask = LTC3589_B3DTV2_REG3_REF_INPUT_V2_MASK; + if (data & LTC3589_VCCR_REG3_REF_SELECT) + volt_reg = LTC3589_REG_B3DTV2; + else + volt_reg = LTC3589_REG_B3DTV1; + break; + default: + return -EINVAL; + } + + data = ltc_3589_reg_read(ltc, volt_reg); + if (data < 0) + return data; + + data >>= shift; + data &= mask; + uV = (((r1 + r2) * (362500 + data * 12500)) / r2); + return uV; +} + +static int ltc3589_dcdc_set_voltage(struct regulator_dev *dev, + int min_uV, int max_uV) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int dcdc = rdev_get_id(dev); + int volt_reg1; + int volt_reg2; + int shift, mask; + int r1, r2; + int dac_vol, data, slew_val; + + r1 = 0; + r2 = 1; + if (dcdc < LTC3589_DCDC_1 || dcdc > LTC3589_DCDC_3) + return -EINVAL; + + switch (dcdc) { + case LTC3589_DCDC_1: + r1 = LTC3589_SW1_R1; + r2 = LTC3589_SW1_R2; + volt_reg1 = 0; + volt_reg2 = LTC3589_REG_B1DTV1; + slew_val = 1; + shift = LTC3589_B1DTV2_REG1_REF_INPUT_V2_SHIFT; + mask = LTC3589_B1DTV2_REG1_REF_INPUT_V2_MASK; + break; + case LTC3589_DCDC_2: + r1 = LTC3589_SW2_R1; + r2 = ltc3589_sw2_r2; + volt_reg1 = 0; + volt_reg2 = LTC3589_REG_B2DTV1; + slew_val = 1; + shift = LTC3589_B2DTV2_REG2_REF_INPUT_V2_SHIFT; + mask = LTC3589_B2DTV2_REG2_REF_INPUT_V2_MASK; + break; + case LTC3589_DCDC_3: + r1 = LTC3589_SW3_R1; + r2 = LTC3589_SW3_R2; + volt_reg1 = 0; + volt_reg2 = LTC3589_REG_B3DTV1; + slew_val = 1; + shift = LTC3589_B3DTV2_REG3_REF_INPUT_V2_SHIFT; + mask = LTC3589_B3DTV2_REG3_REF_INPUT_V2_MASK; + break; + default: + return -EINVAL; + } + + dac_vol = ((min_uV * r2 - 362500 * (r1 + r2)) / (12500 * (r1 + r2))); + if ((dac_vol > 0x1F) || (dac_vol < 0)) + return -EINVAL; + + /* Set voltage */ + if (volt_reg1 != 0) { + data = ltc_3589_reg_read(ltc, volt_reg1); + if (data < 0) + return data; + + data >>= shift; + data &= ~mask; + data |= dac_vol; + ltc_3589_reg_write(ltc, volt_reg1, data); + } + + if (volt_reg2 != 0) { + data = ltc_3589_reg_read(ltc, volt_reg2); + if (data < 0) + return data; + + data >>= shift; + data &= ~mask; + data |= dac_vol; + ltc_3589_reg_write(ltc, volt_reg2, data); + } + + /* Set slew config */ + data = ltc_3589_reg_read(ltc, LTC3589_REG_VCCR); + if (data < 0) + return data; + + data &= ~(3 << (2 * dcdc)); + data |= (slew_val << (2 * dcdc)); + + ltc_3589_reg_write(ltc, LTC3589_REG_VCCR, data); + + data = ltc_3589_reg_read(ltc, LTC3589_REG_SCR2); + if (data < 0) + return data; + + data &= ~(1 << dcdc); + data |= (1 << dcdc); + + ltc_3589_reg_write(ltc, LTC3589_REG_SCR2, data); + + data = ltc_3589_reg_read(ltc, LTC3589_REG_OVEN); + if (data < 0) + return data; + + data &= ~(1 << dcdc); + data |= (1 << dcdc); + + ltc_3589_reg_write(ltc, LTC3589_REG_OVEN, data); + + mdelay(10); + + return 0; +} + +static int ltc3589_set_suspend_voltage(struct regulator_dev *dev, + int uV) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int dcdc = rdev_get_id(dev); + int volt_reg1; + int shift, mask; + int r1, r2; + int dac_vol, data; + + r1 = 0; + r2 = 1; + if (dcdc < LTC3589_DCDC_1 || dcdc > LTC3589_DCDC_3) + return -EINVAL; + + switch (dcdc) { + case LTC3589_DCDC_1: + r1 = LTC3589_SW1_R1; + r2 = LTC3589_SW1_R2; + volt_reg1 = LTC3589_REG_B1DTV2; + shift = LTC3589_B1DTV2_REG1_REF_INPUT_V2_SHIFT; + mask = LTC3589_B1DTV2_REG1_REF_INPUT_V2_MASK; + break; + case LTC3589_DCDC_2: + r1 = LTC3589_SW2_R1; + r2 = ltc3589_sw2_r2; + volt_reg1 = LTC3589_REG_B2DTV2; + shift = LTC3589_B2DTV2_REG2_REF_INPUT_V2_SHIFT; + mask = LTC3589_B2DTV2_REG2_REF_INPUT_V2_MASK; + break; + default: + return 0; + } + + dac_vol = ((uV * r2 - 362500 * (r1 + r2)) / (12500 * (r1 + r2))); + if ((dac_vol > 0x1F) || (dac_vol < 0)) + return -EINVAL; + + data = ltc_3589_reg_read(ltc, volt_reg1); + if (data < 0) + return data; + + data >>= shift; + data &= ~mask; + data |= dac_vol; + ltc_3589_reg_write(ltc, volt_reg1, data); + return 0; +} + +static int ltc3589_set_suspend_enable(struct regulator_dev *rdev) +{ + return 0; +} + +static int ltc3589_set_suspend_disable(struct regulator_dev *rdev) +{ + return 0; +} + +static int ltc3589_set_suspend_mode(struct regulator_dev *rdev, + unsigned int mode) +{ + return 0; +} + +static int ltc3589_ldo_get_voltage(struct regulator_dev *dev) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int data, ldo = rdev_get_id(dev); + int uV; + + if (ldo < LTC3589_LDO_1 || ldo > LTC3589_LDO_4) + return -EINVAL; + + if (ldo == LTC3589_LDO_1 || ldo == LTC3589_LDO_3) + return -EINVAL; + + if (ldo == LTC3589_LDO_4) { + data = ltc_3589_reg_read(ltc, LTC3589_REG_L2DTV2); + if (data < 0) + return data; + + data >>= LTC3589_L2DTV2_LDO4_OUTPUT_VOLTAGE_SHIFT; + data &= LTC3589_L2DTV2_LDO4_OUTPUT_VOLTAGE_MASK; + switch (data) { + case 0: + return 1800000; + case 1: + return 2500000; + case 2: + return 3000000; + case 3: + return 3300000; + default: + return -EINVAL; + } + } else { + data = ltc_3589_reg_read(ltc, LTC3589_REG_VCCR); + if (data < 0) + return data; + + if (data & LTC3589_VCCR_LDO2_REF_SELECT) + data = ltc_3589_reg_read(ltc, LTC3589_REG_L2DTV2); + else + data = ltc_3589_reg_read(ltc, LTC3589_REG_L2DTV1); + + if (data < 0) + return data; + + data >>= LTC3589_L2DTV2_LDO2_REF_INPUT_V2_SHIFT; + data &= LTC3589_L2DTV2_LDO2_REF_INPUT_V2_MASK; + uV = (((LTC3589_LDO2_R1 + ltc3589_ldo2_r2) + * (362500 + data * 12500)) / ltc3589_ldo2_r2); + return uV; + } + + return -EINVAL; +} + +static int ltc3589_ldo_set_voltage(struct regulator_dev *dev, + int min_uV, int max_uV) +{ + struct ltc3589 *ltc = rdev_get_drvdata(dev); + int data, vsel, ldo = rdev_get_id(dev); + + if (ldo < LTC3589_LDO_1 || ldo > LTC3589_LDO_4) + return -EINVAL; + + if (ldo == LTC3589_LDO_1 || ldo == LTC3589_LDO_3) + return -EINVAL; + + if (ldo == LTC3589_LDO_4) { + for (vsel = 0; vsel < 4; vsel++) { + int mV = LDO4_VSEL_table[vsel]; + int uV = mV * 1000; + + /* Break at the first in-range value */ + if (min_uV <= uV && uV <= max_uV) + break; + } + + if (vsel == 4) + return -EINVAL; + + data = ltc_3589_reg_read(ltc, LTC3589_REG_L2DTV2); + if (data < 0) + return data; + + data &= ~(0x3 << LTC3589_L2DTV2_LDO4_OUTPUT_VOLTAGE_SHIFT); + data |= (vsel << LTC3589_L2DTV2_LDO4_OUTPUT_VOLTAGE_SHIFT); + data &= ~(1 << LTC3589_L2DTV2_LDO4_CONTROL_MODE_SHIFT); + data |= (1 << LTC3589_L2DTV2_LDO4_CONTROL_MODE_SHIFT); + ltc_3589_reg_write(ltc, LTC3589_REG_L2DTV2, data); + + + data = ltc_3589_reg_read(ltc, LTC3589_REG_SCR2); + if (data < 0) + return data; + + data &= ~(1 << LTC3589_SCR2_LDO4_STARTUP_SHIFT); + data |= (1 << LTC3589_SCR2_LDO4_STARTUP_SHIFT); + + ltc_3589_reg_write(ltc, LTC3589_REG_SCR2, data); + + data = ltc_3589_reg_read(ltc, LTC3589_REG_OVEN); + if (data < 0) + return data; + + data &= ~(LTC3589_OVEN_EN_LDO4); + data |= LTC3589_OVEN_EN_LDO4; + + ltc_3589_reg_write(ltc, LTC3589_REG_OVEN, data); + + mdelay(10); + } else { + int dac_vol; + + dac_vol = ((min_uV * ltc3589_ldo2_r2 - + 362500 * (LTC3589_LDO2_R1 + ltc3589_ldo2_r2)) + / (12500 * (LTC3589_LDO2_R1 + ltc3589_ldo2_r2))); + if ((dac_vol > 0x1F) || (dac_vol < 0)) + return -EINVAL; + + data = ltc_3589_reg_read(ltc, LTC3589_REG_L2DTV1); + if (data < 0) + return data; + + data &= ~LTC3589_L2DTV2_LDO2_REF_INPUT_V2_MASK; + data |= dac_vol; + ltc_3589_reg_write(ltc, LTC3589_REG_L2DTV1, data); + + /* Set slew config */ + data = ltc_3589_reg_read(ltc, LTC3589_REG_VCCR); + if (data < 0) + return data; + + data &= ~(LTC3589_VCCR_LDO2_SLEW | + LTC3589_VCCR_LDO2_REF_SELECT); + data |= LTC3589_VCCR_LDO2_SLEW; + + ltc_3589_reg_write(ltc, LTC3589_REG_VCCR, data); + + data = ltc_3589_reg_read(ltc, LTC3589_REG_SCR2); + if (data < 0) + return data; + + data &= ~(1 << LTC3589_SCR2_LDO2_STARTUP_SHIFT); + data |= (1 << LTC3589_SCR2_LDO2_STARTUP_SHIFT); + + ltc_3589_reg_write(ltc, LTC3589_REG_SCR2, data); + + data = ltc_3589_reg_read(ltc, LTC3589_REG_OVEN); + if (data < 0) + return data; + + data &= ~(LTC3589_OVEN_EN_LDO2); + data |= (LTC3589_OVEN_EN_LDO2); + + ltc_3589_reg_write(ltc, LTC3589_REG_OVEN, data); + + mdelay(10); + } + return 0; +} + +static int ltc3589_ldo4_list_voltage(struct regulator_dev *dev, + unsigned selector) +{ + int ldo = rdev_get_id(dev); + + if (ldo != LTC3589_LDO_4) + return -EINVAL; + + if (selector >= 4) + return -EINVAL; + else + return LDO4_VSEL_table[selector] * 1000; +} + +/* Operations permitted on SWx */ +static struct regulator_ops ltc3589_sw_ops = { + .is_enabled = ltc3589_dcdc_is_enabled, + .enable = ltc3589_dcdc_enable, + .disable = ltc3589_dcdc_disable, + .get_mode = ltc3589_dcdc_get_mode, + .set_mode = ltc3589_dcdc_set_mode, + .get_voltage = ltc3589_dcdc_get_voltage, + .set_voltage = ltc3589_dcdc_set_voltage, + .set_suspend_voltage = ltc3589_set_suspend_voltage, + .set_suspend_enable = ltc3589_set_suspend_enable, + .set_suspend_disable = ltc3589_set_suspend_disable, + .set_suspend_mode = ltc3589_set_suspend_mode, +}; + +/* Operations permitted on SW4 Buck-Boost */ +static struct regulator_ops ltc3589_sw4_ops = { + .is_enabled = ltc3589_dcdc_is_enabled, + .enable = ltc3589_dcdc_enable, + .disable = ltc3589_dcdc_disable, + .get_mode = ltc3589_dcdc_get_mode, + .set_mode = ltc3589_dcdc_set_mode, +}; + +/* Operations permitted on LDO1_STBY, LDO3 */ +static struct regulator_ops ltc3589_ldo13_ops = { + .is_enabled = ltc3589_ldo_is_enabled, + .enable = ltc3589_ldo_enable, + .disable = ltc3589_ldo_disable, +}; + +/* Operations permitted on LDO2 */ +static struct regulator_ops ltc3589_ldo2_ops = { + .is_enabled = ltc3589_ldo_is_enabled, + .enable = ltc3589_ldo_enable, + .disable = ltc3589_ldo_disable, + .get_voltage = ltc3589_ldo_get_voltage, + .set_voltage = ltc3589_ldo_set_voltage, +}; + +/* Operations permitted on LDO4 */ +static struct regulator_ops ltc3589_ldo4_ops = { + .is_enabled = ltc3589_ldo_is_enabled, + .enable = ltc3589_ldo_enable, + .disable = ltc3589_ldo_disable, + .get_voltage = ltc3589_ldo_get_voltage, + .set_voltage = ltc3589_ldo_set_voltage, + .list_voltage = ltc3589_ldo4_list_voltage, +}; + +static struct regulator_desc ltc3589_reg[] = { + { + .name = "SW1", + .id = LTC3589_SW1, + .ops = <c3589_sw_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = 0x1F + 1, + .owner = THIS_MODULE, + }, + { + .name = "SW2", + .id = LTC3589_SW2, + .ops = <c3589_sw_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = 0x1F + 1, + .owner = THIS_MODULE, + }, + { + .name = "SW3", + .id = LTC3589_SW3, + .ops = <c3589_sw_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = 0x1F + 1, + .owner = THIS_MODULE, + }, + { + .name = "SW4", + .id = LTC3589_SW4, + .ops = <c3589_sw4_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + }, + { + .name = "LDO1_STBY", + .id = LTC3589_LDO1, + .ops = <c3589_ldo13_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + }, + { + .name = "LDO2", + .id = LTC3589_LDO2, + .ops = <c3589_ldo2_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = 0x1F + 1, + .owner = THIS_MODULE, + }, + { + .name = "LDO3", + .id = LTC3589_LDO3, + .ops = <c3589_ldo13_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + }, + { + .name = "LDO4", + .id = LTC3589_LDO4, + .ops = <c3589_ldo4_ops, + .type = REGULATOR_VOLTAGE, + .n_voltages = ARRAY_SIZE(LDO4_VSEL_table), + .owner = THIS_MODULE, + }, +}; + +static int ltc3589_regulator_probe(struct platform_device *pdev) +{ + struct regulator_dev *rdev; + + if (pdev->id < LTC3589_DCDC_1 || pdev->id > LTC3589_LDO4) + return -ENODEV; + + if (cpu_is_mx53_rev(CHIP_REV_2_0) >= 1) { + ltc3589_ldo2_r2 = LTC3589_LDO2_R2_TO2; + ltc3589_sw2_r2 = LTC3589_SW2_R2_TO2; + } else { + ltc3589_ldo2_r2 = LTC3589_LDO2_R2_TO1; + ltc3589_sw2_r2 = LTC3589_SW2_R2_TO1; + } + + /* register regulator */ + rdev = regulator_register(<c3589_reg[pdev->id], &pdev->dev, + pdev->dev.platform_data, + dev_get_drvdata(&pdev->dev)); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + ltc3589_reg[pdev->id].name); + return PTR_ERR(rdev); + } + + ltc3589_set_slew_rate(rdev, LTC3589_VRRCR_SLEW_RATE_7P00MV_US); + + return 0; +} + +static int ltc3589_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + + regulator_unregister(rdev); + + return 0; +} + +int ltc3589_register_regulator(struct ltc3589 *ltc3589, int reg, + struct regulator_init_data *initdata) +{ + struct platform_device *pdev; + int ret; + + if (ltc3589->pmic.pdev[reg]) + return -EBUSY; + if (reg < LTC3589_DCDC_1 || reg > LTC3589_LDO_4) + return -ENODEV; + pdev = platform_device_alloc("ltc3589-regulator", reg); + if (!pdev) + return -ENOMEM; + ltc3589->pmic.pdev[reg] = pdev; + + initdata->driver_data = ltc3589; + + pdev->dev.platform_data = initdata; + pdev->dev.parent = ltc3589->dev; + platform_set_drvdata(pdev, ltc3589); + + ret = platform_device_add(pdev); + + if (ret != 0) { + dev_err(ltc3589->dev, "Failed to register regulator %d: %d\n", + reg, ret); + platform_device_del(pdev); + ltc3589->pmic.pdev[reg] = NULL; + } + + return ret; +} +EXPORT_SYMBOL_GPL(ltc3589_register_regulator); + +static struct platform_driver ltc3589_regulator_driver = { + .driver = { + .name = "ltc3589-regulator", + }, + .probe = ltc3589_regulator_probe, + .remove = ltc3589_regulator_remove, +}; + +static int __init ltc3589_regulator_init(void) +{ + return platform_driver_register(<c3589_regulator_driver); + +} +subsys_initcall_sync(ltc3589_regulator_init); + +static void __exit ltc3589_regulator_exit(void) +{ + platform_driver_unregister(<c3589_regulator_driver); +} +module_exit(ltc3589_regulator_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("LTC3589 Regulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/max17135-regulator.c b/drivers/regulator/max17135-regulator.c new file mode 100644 index 000000000000..2d4cbcc1667c --- /dev/null +++ b/drivers/regulator/max17135-regulator.c @@ -0,0 +1,640 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Regulator definitions + * *_MIN_uV - minimum microvolt for regulator + * *_MAX_uV - maximum microvolt for regulator + * *_STEP_uV - microvolts between regulator output levels + * *_MIN_VAL - minimum register field value for regulator + * *_MAX_VAL - maximum register field value for regulator + */ +#define MAX17135_HVINP_MIN_uV 5000000 +#define MAX17135_HVINP_MAX_uV 20000000 +#define MAX17135_HVINP_STEP_uV 1000000 +#define MAX17135_HVINP_MIN_VAL 0 +#define MAX17135_HVINP_MAX_VAL 1 + +#define MAX17135_HVINN_MIN_uV 5000000 +#define MAX17135_HVINN_MAX_uV 20000000 +#define MAX17135_HVINN_STEP_uV 1000000 +#define MAX17135_HVINN_MIN_VAL 0 +#define MAX17135_HVINN_MAX_VAL 1 + +#define MAX17135_GVDD_MIN_uV 5000000 +#define MAX17135_GVDD_MAX_uV 20000000 +#define MAX17135_GVDD_STEP_uV 1000000 +#define MAX17135_GVDD_MIN_VAL 0 +#define MAX17135_GVDD_MAX_VAL 1 + +#define MAX17135_GVEE_MIN_uV 5000000 +#define MAX17135_GVEE_MAX_uV 20000000 +#define MAX17135_GVEE_STEP_uV 1000000 +#define MAX17135_GVEE_MIN_VAL 0 +#define MAX17135_GVEE_MAX_VAL 1 + +#define MAX17135_VCOM_MIN_VAL 0 +#define MAX17135_VCOM_MAX_VAL 255 + +#define MAX17135_VNEG_MIN_uV 5000000 +#define MAX17135_VNEG_MAX_uV 20000000 +#define MAX17135_VNEG_STEP_uV 1000000 +#define MAX17135_VNEG_MIN_VAL 0 +#define MAX17135_VNEG_MAX_VAL 1 + +#define MAX17135_VPOS_MIN_uV 5000000 +#define MAX17135_VPOS_MAX_uV 20000000 +#define MAX17135_VPOS_STEP_uV 1000000 +#define MAX17135_VPOS_MIN_VAL 0 +#define MAX17135_VPOS_MAX_VAL 1 + +struct max17135_vcom_programming_data { + int vcom_min_uV; + int vcom_max_uV; + int vcom_step_uV; +}; + +static int max17135_pass_num = { 1 }; +static int max17135_vcom = { -1250000 }; + +struct max17135_vcom_programming_data vcom_data[2] = { + { + -4325000, + -500000, + 15000, + }, + { + -3050000, + -500000, + 10000, + }, +}; + +static int max17135_is_power_good(struct max17135 *max17135); + +/* + * Regulator operations + */ +static int max17135_hvinp_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int reg_val; + unsigned int fld_val; + + if ((uV >= MAX17135_HVINP_MIN_uV) && + (uV <= MAX17135_HVINP_MAX_uV)) + fld_val = (uV - MAX17135_HVINP_MIN_uV) / + MAX17135_HVINP_STEP_uV; + else + return -EINVAL; + + max17135_reg_read(REG_MAX17135_HVINP, ®_val); + + reg_val &= ~BITFMASK(HVINP); + reg_val |= BITFVAL(HVINP, fld_val); /* shift to correct bit */ + + return max17135_reg_write(REG_MAX17135_HVINP, reg_val); +} + +static int max17135_hvinp_get_voltage(struct regulator_dev *reg) +{ + unsigned int reg_val; + unsigned int fld_val; + int volt; + + max17135_reg_read(REG_MAX17135_HVINP, ®_val); + + fld_val = (reg_val & BITFMASK(HVINP)) >> HVINP_LSH; + + if ((fld_val >= MAX17135_HVINP_MIN_VAL) && + (fld_val <= MAX17135_HVINP_MAX_VAL)) { + volt = (fld_val * MAX17135_HVINP_STEP_uV) + + MAX17135_HVINP_MIN_uV; + } else { + printk(KERN_ERR "MAX17135: HVINP voltage is out of range\n"); + volt = 0; + } + return volt; +} + +static int max17135_hvinp_enable(struct regulator_dev *reg) +{ + return 0; +} + +static int max17135_hvinp_disable(struct regulator_dev *reg) +{ + return 0; +} + +/* Convert uV to the VCOM register bitfield setting */ +static inline int vcom_uV_to_rs(int uV, int pass_num) +{ + return (vcom_data[pass_num].vcom_max_uV - uV) + / vcom_data[pass_num].vcom_step_uV; +} + +/* Convert the VCOM register bitfield setting to uV */ +static inline int vcom_rs_to_uV(int rs, int pass_num) +{ + return vcom_data[pass_num].vcom_max_uV + - (vcom_data[pass_num].vcom_step_uV * rs); +} + +static int max17135_vcom_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + unsigned int reg_val; + int vcom_read; + + if ((uV < vcom_data[max17135->pass_num-1].vcom_min_uV) + || (uV > vcom_data[max17135->pass_num-1].vcom_max_uV)) + return -EINVAL; + + max17135_reg_read(REG_MAX17135_DVR, ®_val); + + /* + * Only program VCOM if it is not set to the desired value. + * Programming VCOM excessively degrades ability to keep + * DVR register value persistent. + */ + vcom_read = vcom_rs_to_uV(reg_val, max17135->pass_num-1); + if (vcom_read != max17135->vcom_uV) { + reg_val &= ~BITFMASK(DVR); + reg_val |= BITFVAL(DVR, vcom_uV_to_rs(uV, + max17135->pass_num-1)); + max17135_reg_write(REG_MAX17135_DVR, reg_val); + + reg_val = BITFVAL(CTRL_DVR, true); /* shift to correct bit */ + return max17135_reg_write(REG_MAX17135_PRGM_CTRL, reg_val); + } + + return 0; +} + +static int max17135_vcom_get_voltage(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + unsigned int reg_val; + + max17135_reg_read(REG_MAX17135_DVR, ®_val); + return vcom_rs_to_uV(BITFEXT(reg_val, DVR), max17135->pass_num-1); +} + +static int max17135_vcom_enable(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + + /* + * Check to see if we need to set the VCOM voltage. + * Should only be done one time. And, we can + * only change vcom voltage if we have been enabled. + */ + if (!max17135->vcom_setup && max17135_is_power_good(max17135)) { + max17135_vcom_set_voltage(reg, + max17135->vcom_uV, + max17135->vcom_uV); + max17135->vcom_setup = true; + } + + /* enable VCOM regulator output */ + if (max17135->pass_num == 1) + gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 1); + else { + unsigned int reg_val; + + max17135_reg_read(REG_MAX17135_ENABLE, ®_val); + reg_val &= ~BITFMASK(VCOM_ENABLE); + reg_val |= BITFVAL(VCOM_ENABLE, 1); /* shift to correct bit */ + max17135_reg_write(REG_MAX17135_ENABLE, reg_val); + } + + return 0; +} + +static int max17135_vcom_disable(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + + if (max17135->pass_num == 1) + gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 0); + else { + unsigned int reg_val; + + max17135_reg_read(REG_MAX17135_ENABLE, ®_val); + reg_val &= ~BITFMASK(VCOM_ENABLE); + max17135_reg_write(REG_MAX17135_ENABLE, reg_val); + } + + return 0; +} + +static int max17135_vcom_is_enabled(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + + /* read VCOM regulator enable setting */ + if (max17135->pass_num == 1) { + int gpio = gpio_get_value(max17135->gpio_pmic_vcom_ctrl); + if (gpio == 0) + return 0; + else + return 1; + } else { + unsigned int reg_val; + + max17135_reg_read(REG_MAX17135_ENABLE, ®_val); + reg_val &= BITFMASK(VCOM_ENABLE); + if (reg_val != 0) + return 1; + else + return 0; + } +} + +static int max17135_is_power_good(struct max17135 *max17135) +{ + /* + * XOR of polarity (starting value) and current + * value yields whether power is good. + */ + return gpio_get_value(max17135->gpio_pmic_pwrgood) ^ + max17135->pwrgood_polarity; +} + +static int max17135_wait_power_good(struct max17135 *max17135) +{ + int i; + + for (i = 0; i < max17135->max_wait * 3; i++) { + if (max17135_is_power_good(max17135)) + return 0; + + msleep(1); + } + return -ETIMEDOUT; +} + +static int max17135_display_enable(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + + /* The Pass 1 parts cannot turn on the PMIC via I2C. */ + if (max17135->pass_num == 1) + gpio_set_value(max17135->gpio_pmic_wakeup, 1); + else { + unsigned int reg_val; + + max17135_reg_read(REG_MAX17135_ENABLE, ®_val); + reg_val &= ~BITFMASK(ENABLE); + reg_val |= BITFVAL(ENABLE, 1); + max17135_reg_write(REG_MAX17135_ENABLE, reg_val); + } + + return max17135_wait_power_good(max17135); +} + +static int max17135_display_disable(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + + if (max17135->pass_num == 1) + gpio_set_value(max17135->gpio_pmic_wakeup, 0); + else { + unsigned int reg_val; + + max17135_reg_read(REG_MAX17135_ENABLE, ®_val); + reg_val &= ~BITFMASK(ENABLE); + max17135_reg_write(REG_MAX17135_ENABLE, reg_val); + } + + msleep(max17135->max_wait); + + return 0; +} + +static int max17135_display_is_enabled(struct regulator_dev *reg) +{ + struct max17135 *max17135 = rdev_get_drvdata(reg); + int gpio = gpio_get_value(max17135->gpio_pmic_wakeup); + + if (gpio == 0) + return 0; + else + return 1; +} + +/* + * Regulator operations + */ + +static struct regulator_ops max17135_display_ops = { + .enable = max17135_display_enable, + .disable = max17135_display_disable, + .is_enabled = max17135_display_is_enabled, +}; + +static struct regulator_ops max17135_gvdd_ops = { +}; + +static struct regulator_ops max17135_gvee_ops = { +}; + +static struct regulator_ops max17135_hvinn_ops = { +}; + +static struct regulator_ops max17135_hvinp_ops = { + .enable = max17135_hvinp_enable, + .disable = max17135_hvinp_disable, + .get_voltage = max17135_hvinp_get_voltage, + .set_voltage = max17135_hvinp_set_voltage, +}; + +static struct regulator_ops max17135_vcom_ops = { + .enable = max17135_vcom_enable, + .disable = max17135_vcom_disable, + .get_voltage = max17135_vcom_get_voltage, + .set_voltage = max17135_vcom_set_voltage, + .is_enabled = max17135_vcom_is_enabled, +}; + +static struct regulator_ops max17135_vneg_ops = { +}; + +static struct regulator_ops max17135_vpos_ops = { +}; + +/* + * Regulator descriptors + */ +static struct regulator_desc max17135_reg[MAX17135_NUM_REGULATORS] = { +{ + .name = "DISPLAY", + .id = MAX17135_DISPLAY, + .ops = &max17135_display_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "GVDD", + .id = MAX17135_GVDD, + .ops = &max17135_gvdd_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "GVEE", + .id = MAX17135_GVEE, + .ops = &max17135_gvee_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "HVINN", + .id = MAX17135_HVINN, + .ops = &max17135_hvinn_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "HVINP", + .id = MAX17135_HVINP, + .ops = &max17135_hvinp_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "VCOM", + .id = MAX17135_VCOM, + .ops = &max17135_vcom_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "VNEG", + .id = MAX17135_VNEG, + .ops = &max17135_vneg_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +{ + .name = "VPOS", + .id = MAX17135_VPOS, + .ops = &max17135_vpos_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, +}, +}; + +static void max17135_setup_timings(struct max17135 *max17135) +{ + unsigned int reg_val; + + int timing1, timing2, timing3, timing4, + timing5, timing6, timing7, timing8; + + max17135_reg_read(REG_MAX17135_TIMING1, &timing1); + max17135_reg_read(REG_MAX17135_TIMING2, &timing2); + max17135_reg_read(REG_MAX17135_TIMING3, &timing3); + max17135_reg_read(REG_MAX17135_TIMING4, &timing4); + max17135_reg_read(REG_MAX17135_TIMING5, &timing5); + max17135_reg_read(REG_MAX17135_TIMING6, &timing6); + max17135_reg_read(REG_MAX17135_TIMING7, &timing7); + max17135_reg_read(REG_MAX17135_TIMING8, &timing8); + + if ((timing1 != max17135->gvee_pwrup) || + (timing2 != max17135->vneg_pwrup) || + (timing3 != max17135->vpos_pwrup) || + (timing4 != max17135->gvdd_pwrup) || + (timing5 != max17135->gvdd_pwrdn) || + (timing6 != max17135->vpos_pwrdn) || + (timing7 != max17135->vneg_pwrdn) || + (timing8 != max17135->gvee_pwrdn)) { + max17135_reg_write(REG_MAX17135_TIMING1, max17135->gvee_pwrup); + max17135_reg_write(REG_MAX17135_TIMING2, max17135->vneg_pwrup); + max17135_reg_write(REG_MAX17135_TIMING3, max17135->vpos_pwrup); + max17135_reg_write(REG_MAX17135_TIMING4, max17135->gvdd_pwrup); + max17135_reg_write(REG_MAX17135_TIMING5, max17135->gvdd_pwrdn); + max17135_reg_write(REG_MAX17135_TIMING6, max17135->vpos_pwrdn); + max17135_reg_write(REG_MAX17135_TIMING7, max17135->vneg_pwrdn); + max17135_reg_write(REG_MAX17135_TIMING8, max17135->gvee_pwrdn); + + reg_val = BITFVAL(CTRL_TIMING, true); /* shift to correct bit */ + max17135_reg_write(REG_MAX17135_PRGM_CTRL, reg_val); + } +} + + +/* + * Regulator init/probing/exit functions + */ +static int max17135_regulator_probe(struct platform_device *pdev) +{ + struct regulator_dev *rdev; + + rdev = regulator_register(&max17135_reg[pdev->id], &pdev->dev, + pdev->dev.platform_data, + dev_get_drvdata(&pdev->dev)); + + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + max17135_reg[pdev->id].name); + return PTR_ERR(rdev); + } + + return 0; +} + +static int max17135_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + regulator_unregister(rdev); + return 0; +} + +static struct platform_driver max17135_regulator_driver = { + .probe = max17135_regulator_probe, + .remove = max17135_regulator_remove, + .driver = { + .name = "max17135-reg", + }, +}; + +int max17135_register_regulator(struct max17135 *max17135, int reg, + struct regulator_init_data *initdata) +{ + struct platform_device *pdev; + int ret; + + struct i2c_client *client = max17135->i2c_client; + /* If we can't find PMIC via I2C, we should not register regulators */ + if (i2c_smbus_read_byte_data(client, + REG_MAX17135_PRODUCT_REV) != 0) { + dev_err(max17135->dev, + "Max17135 PMIC not found!\n"); + return -ENXIO; + } + + if (max17135->pdev[reg]) + return -EBUSY; + + pdev = platform_device_alloc("max17135-reg", reg); + if (!pdev) + return -ENOMEM; + + max17135->pdev[reg] = pdev; + + initdata->driver_data = max17135; + + pdev->dev.platform_data = initdata; + pdev->dev.parent = max17135->dev; + platform_set_drvdata(pdev, max17135); + + ret = platform_device_add(pdev); + + if (ret != 0) { + dev_err(max17135->dev, + "Failed to register regulator %d: %d\n", + reg, ret); + platform_device_del(pdev); + max17135->pdev[reg] = NULL; + } + + if (!max17135->init_done) { + max17135->pass_num = max17135_pass_num; + max17135->vcom_uV = max17135_vcom; + + /* + * Set up PMIC timing values. + * Should only be done one time! Timing values may only be + * changed a limited number of times according to spec. + */ + max17135_setup_timings(max17135); + + max17135->pwrgood_polarity = + gpio_get_value(max17135->gpio_pmic_pwrgood); + + max17135->init_done = true; + } + + return ret; +} + +static int __init max17135_regulator_init(void) +{ + return platform_driver_register(&max17135_regulator_driver); +} +subsys_initcall(max17135_regulator_init); + +static void __exit max17135_regulator_exit(void) +{ + platform_driver_unregister(&max17135_regulator_driver); +} +module_exit(max17135_regulator_exit); + + +/* + * Parse user specified options (`max17135:') + * example: + * max17135:pass=2,vcom=-1250000 + */ +static int __init max17135_setup(char *options) +{ + int ret; + char *opt; + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + if (!strncmp(opt, "pass=", 5)) { + ret = strict_strtoul(opt + 5, 0, &max17135_pass_num); + if (ret < 0) + return ret; + } + if (!strncmp(opt, "vcom=", 5)) { + int offs = 5; + if (opt[5] == '-') + offs = 6; + ret = strict_strtoul(opt + offs, 0, &max17135_vcom); + if (ret < 0) + return ret; + max17135_vcom = -max17135_vcom; + } + } + + return 1; +} + +__setup("max17135:", max17135_setup); + +/* Module information */ +MODULE_DESCRIPTION("MAX17135 regulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/mxs-regulator.c b/drivers/regulator/mxs-regulator.c new file mode 100644 index 000000000000..34930776a90c --- /dev/null +++ b/drivers/regulator/mxs-regulator.c @@ -0,0 +1,302 @@ +/* + * Freescale STMP378X voltage regulators + * + * Embedded Alley Solutions, Inc + * + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int mxs_set_voltage(struct regulator_dev *reg, int MiniV, int uv) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + if (mxs_reg->rdata->set_voltage) + return mxs_reg->rdata->set_voltage(mxs_reg, uv); + else + return -ENOTSUPP; +} + + +static int mxs_get_voltage(struct regulator_dev *reg) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + if (mxs_reg->rdata->get_voltage) + return mxs_reg->rdata->get_voltage(mxs_reg); + else + return -ENOTSUPP; +} + +static int mxs_set_current(struct regulator_dev *reg, int min_uA, int uA) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + if (mxs_reg->rdata->set_current) + return mxs_reg->rdata->set_current(mxs_reg, uA); + else + return -ENOTSUPP; +} + +static int mxs_get_current(struct regulator_dev *reg) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + if (mxs_reg->rdata->get_current) + return mxs_reg->rdata->get_current(mxs_reg); + else + return -ENOTSUPP; +} + +static int mxs_enable(struct regulator_dev *reg) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + return mxs_reg->rdata->enable(mxs_reg); +} + +static int mxs_disable(struct regulator_dev *reg) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + return mxs_reg->rdata->disable(mxs_reg); +} + +static int mxs_is_enabled(struct regulator_dev *reg) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + return mxs_reg->rdata->is_enabled(mxs_reg); +} + +static int mxs_set_mode(struct regulator_dev *reg, unsigned int mode) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + return mxs_reg->rdata->set_mode(mxs_reg, mode); +} + +static unsigned int mxs_get_mode(struct regulator_dev *reg) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + return mxs_reg->rdata->get_mode(mxs_reg); +} + +static unsigned int mxs_get_optimum_mode(struct regulator_dev *reg, + int input_uV, int output_uV, int load_uA) +{ + struct mxs_regulator *mxs_reg = rdev_get_drvdata(reg); + + if (mxs_reg->rdata->get_optimum_mode) + return mxs_reg->rdata->get_optimum_mode(mxs_reg, input_uV, + output_uV, load_uA); + else + return -ENOTSUPP; +} + +static struct regulator_ops mxs_rops = { + .set_voltage = mxs_set_voltage, + .get_voltage = mxs_get_voltage, + .set_current_limit = mxs_set_current, + .get_current_limit = mxs_get_current, + .enable = mxs_enable, + .disable = mxs_disable, + .is_enabled = mxs_is_enabled, + .set_mode = mxs_set_mode, + .get_mode = mxs_get_mode, + .get_optimum_mode = mxs_get_optimum_mode, +}; + +static struct regulator_desc mxs_reg_desc[] = { + { + .name = "vddd", + .id = MXS_VDDD, + .ops = &mxs_rops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "vdda", + .id = MXS_VDDA, + .ops = &mxs_rops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "vddio", + .id = MXS_VDDIO, + .ops = &mxs_rops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "vddd_bo", + .id = MXS_VDDDBO, + .ops = &mxs_rops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "overall_current", + .id = MXS_OVERALL_CUR, + .ops = &mxs_rops, + .irq = 0, + .type = REGULATOR_CURRENT, + .owner = THIS_MODULE + }, +}; + +static int reg_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + unsigned long flags; + struct mxs_regulator *sreg = + container_of(self, struct mxs_regulator , nb); + + switch (event) { + case MXS_REG5V_IS_USB: + spin_lock_irqsave(&sreg->lock, flags); + sreg->rdata->max_current = 500000; + spin_unlock_irqrestore(&sreg->lock, flags); + break; + case MXS_REG5V_NOT_USB: + spin_lock_irqsave(&sreg->lock, flags); + sreg->rdata->max_current = 0x7fffffff; + spin_unlock_irqrestore(&sreg->lock, flags); + break; + } + + return 0; +} + +int mxs_regulator_probe(struct platform_device *pdev) +{ + struct regulator_desc *rdesc; + struct regulator_dev *rdev; + struct mxs_regulator *sreg; + struct regulator_init_data *initdata; + + sreg = platform_get_drvdata(pdev); + initdata = pdev->dev.platform_data; + sreg->cur_current = 0; + sreg->next_current = 0; + sreg->cur_voltage = 0; + + init_waitqueue_head(&sreg->wait_q); + spin_lock_init(&sreg->lock); + + if (pdev->id > MXS_OVERALL_CUR) { + rdesc = kzalloc(sizeof(struct regulator_desc), GFP_KERNEL); + memcpy(rdesc, &mxs_reg_desc[MXS_OVERALL_CUR], + sizeof(struct regulator_desc)); + rdesc->name = kstrdup(sreg->rdata->name, GFP_KERNEL); + } else + rdesc = &mxs_reg_desc[pdev->id]; + + pr_debug("probing regulator %s %s %d\n", + sreg->rdata->name, + rdesc->name, + pdev->id); + + /* register regulator */ + rdev = regulator_register(rdesc, &pdev->dev, + initdata, sreg); + + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + rdesc->name); + return PTR_ERR(rdev); + } + + if (sreg->rdata->max_current) { + struct regulator *regu; + regu = regulator_get(NULL, sreg->rdata->name); + sreg->nb.notifier_call = reg_callback; + regulator_register_notifier(regu, &sreg->nb); + } + + return 0; +} + + +int mxs_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + + regulator_unregister(rdev); + + return 0; + +} + +int mxs_register_regulator( + struct mxs_regulator *reg_data, int reg, + struct regulator_init_data *initdata) +{ + struct platform_device *pdev; + int ret; + + pdev = platform_device_alloc("mxs_reg", reg); + if (!pdev) + return -ENOMEM; + + pdev->dev.platform_data = initdata; + + platform_set_drvdata(pdev, reg_data); + ret = platform_device_add(pdev); + + if (ret != 0) { + pr_debug("Failed to register regulator %d: %d\n", + reg, ret); + platform_device_del(pdev); + } + pr_debug("register regulator %s, %d: %d\n", + reg_data->rdata->name, reg, ret); + + return ret; +} +EXPORT_SYMBOL_GPL(mxs_register_regulator); + +struct platform_driver mxs_reg = { + .driver = { + .name = "mxs_reg", + }, + .probe = mxs_regulator_probe, + .remove = mxs_regulator_remove, +}; + +int mxs_regulator_init(void) +{ + return platform_driver_register(&mxs_reg); +} + +void mxs_regulator_exit(void) +{ + platform_driver_unregister(&mxs_reg); +} + +postcore_initcall(mxs_regulator_init); +module_exit(mxs_regulator_exit); diff --git a/drivers/regulator/reg-mc13783.c b/drivers/regulator/reg-mc13783.c new file mode 100644 index 000000000000..da20907ba087 --- /dev/null +++ b/drivers/regulator/reg-mc13783.c @@ -0,0 +1,2662 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +/*! + * @enum regulator_voltage_sw + * @brief PMIC regulator SW output voltage. + */ +enum { + SW_0_9V = 0, /*!< 0.900 V */ + SW_0_925V, /*!< 0.925 V */ + SW_0_95V, /*!< 0.950 V */ + SW_0_975V, /*!< 0.975 V */ + SW_1V, /*!< 1.000 V */ + SW_1_025V, /*!< 1.025 V */ + SW_1_05V, /*!< 1.050 V */ + SW_1_075V, /*!< 1.075 V */ + SW_1_1V, /*!< 1.100 V */ + SW_1_125V, /*!< 1.125 V */ + SW_1_15V, /*!< 1.150 V */ + SW_1_175V, /*!< 1.175 V */ + SW_1_2V, /*!< 1.200 V */ + SW_1_225V, /*!< 1.225 V */ + SW_1_25V, /*!< 1.250 V */ + SW_1_275V, /*!< 1.275 V */ + SW_1_3V, /*!< 1.300 V */ + SW_1_325V, /*!< 1.325 V */ + SW_1_35V, /*!< 1.350 V */ + SW_1_375V, /*!< 1.375 V */ + SW_1_4V, /*!< 1.400 V */ + SW_1_425V, /*!< 1.425 V */ + SW_1_45V, /*!< 1.450 V */ + SW_1_475V, /*!< 1.475 V */ + SW_1_5V, /*!< 1.500 V */ + SW_1_525V, /*!< 1.525 V */ + SW_1_55V, /*!< 1.550 V */ + SW_1_575V, /*!< 1.575 V */ + SW_1_6V, /*!< 1.600 V */ + SW_1_625V, /*!< 1.625 V */ + SW_1_65V, /*!< 1.650 V */ + SW_1_675V, /*!< 1.675 V */ + SW_1_7V, /*!< 1.700 V */ + SW_1_8V = 36, /*!< 1.800 V */ + SW_1_85V = 40, /*!< 1.850 V */ + SW_2V = 44, /*!< 2_000 V */ + SW_2_1V = 48, /*!< 2_100 V */ + SW_2_2V = 52, /*!< 2_200 V */ +} regulator_voltage_sw; + +/*! + * @enum regulator_voltage_violo + * @brief PMIC regulator VIOLO output voltage. + */ +enum { + VIOLO_1_2V = 0, /*!< 1.2 V */ + VIOLO_1_3V, /*!< 1.3 V */ + VIOLO_1_5V, /*!< 1.5 V */ + VIOLO_1_8V, /*!< 1.8 V */ +} regulator_voltage_violo; + +/*! + * @enum regulator_voltage_vdig + * @brief PMIC regulator VDIG output voltage. + */ +enum { + VDIG_1_2V = 0, /*!< 1.2 V */ + VDIG_1_3V, /*!< 1.3 V */ + VDIG_1_5V, /*!< 1.5 V */ + VDIG_1_8V, /*!< 1.8 V */ +} regulator_voltage_vdig; + +/*! + * @enum regulator_voltage_vgen + * @brief PMIC regulator VGEN output voltage. + */ +enum { + VGEN_1_2V = 0, /*!< 1.2 V */ + VGEN_1_3V, /*!< 1.3 V */ + VGEN_1_5V, /*!< 1.5 V */ + VGEN_1_8V, /*!< 1.8 V */ + VGEN_1_1V, /*!< 1.1 V */ + VGEN_2V, /*!< 2 V */ + VGEN_2_775V, /*!< 2.775 V */ + VGEN_2_4V, /*!< 2.4 V */ +} regulator_voltage_vgen; + +/*! + * @enum regulator_voltage_vrfdig + * @brief PMIC regulator VRFDIG output voltage. + */ +enum { + VRFDIG_1_2V = 0, /*!< 1.2 V */ + VRFDIG_1_5V, /*!< 1.5 V */ + VRFDIG_1_8V, /*!< 1.8 V */ + VRFDIG_1_875V, /*!< 1.875 V */ +} regulator_voltage_vrfdig; + +/*! + * @enum regulator_voltage_vrfref + * @brief PMIC regulator VRFREF output voltage. + */ +enum { + VRFREF_2_475V = 0, /*!< 2.475 V */ + VRFREF_2_6V, /*!< 2.600 V */ + VRFREF_2_7V, /*!< 2.700 V */ + VRFREF_2_775V, /*!< 2.775 V */ +} regulator_voltage_vrfref; + +/*! + * @enum regulator_voltage_vrfcp + * @brief PMIC regulator VRFCP output voltage. + */ +enum { + VRFCP_2_7V = 0, /*!< 2.700 V */ + VRFCP_2_775V, /*!< 2.775 V */ +} regulator_voltage_vrfcp; + +/*! + * @enum regulator_voltage_vsim + * @brief PMIC linear regulator VSIM output voltage. + */ +enum { + VSIM_1_8V = 0, /*!< 1.8 V */ + VSIM_2_9V, /*!< 2.90 V */ + VSIM_3V = 1, /*!< 3 V */ +} regulator_voltage_vsim; + +/*! + * @enum regulator_voltage_vesim + * @brief PMIC regulator VESIM output voltage. + */ +enum { + VESIM_1_8V = 0, /*!< 1.80 V */ + VESIM_2_9V, /*!< 2.90 V */ +} regulator_voltage_vesim; + +/*! + * @enum regulator_voltage_vcam + * @brief PMIC regulator VCAM output voltage. + */ +enum { + VCAM_1_5V = 0, /*!< 1.50 V */ + VCAM_1_8V, /*!< 1.80 V */ + VCAM_2_5V, /*!< 2.50 V */ + VCAM_2_55V, /*!< 2.55 V */ + VCAM_2_6V, /*!< 2.60 V */ + VCAM_2_75V, /*!< 2.75 V */ + VCAM_2_8V, /*!< 2.80 V */ + VCAM_3V, /*!< 3.00 V */ +} regulator_voltage_vcam; + +/*! + * @enum regulator_voltage_vvib + * @brief PMIC linear regulator V_VIB output voltage. + */ +enum { + VVIB_1_3V = 0, /*!< 1.30 V */ + VVIB_1_8V, /*!< 1.80 V */ + VVIB_2V, /*!< 2 V */ + VVIB_3V, /*!< 3 V */ +} regulator_voltage_vvib; + +/*! + * @enum regulator_voltage_vmmc + * @brief MC13783 PMIC regulator VMMC output voltage. + */ +enum { + VMMC_1_6V = 0, /*!< 1.60 V */ + VMMC_1_8V, /*!< 1.80 V */ + VMMC_2V, /*!< 2.00 V */ + VMMC_2_6V, /*!< 2.60 V */ + VMMC_2_7V, /*!< 2.70 V */ + VMMC_2_8V, /*!< 2.80 V */ + VMMC_2_9V, /*!< 2.90 V */ + VMMC_3V, /*!< 3.00 V */ +} regulator_voltage_vmmc; + +/*! + * @enum regulator_voltage_vrf + * @brief PMIC regulator VRF output voltage. + */ +enum { + VRF_1_5V = 0, /*!< 1.500 V */ + VRF_1_875V, /*!< 1.875 V */ + VRF_2_7V, /*!< 2.700 V */ + VRF_2_775V, /*!< 2.775 V */ +} regulator_voltage_vrf; + +/*! + * @enum regulator_voltage_sw3 + * @brief PMIC Switch mode regulator SW3 output voltages. + */ +enum { + SW3_5V = 0, /*!< 5.0 V */ + SW3_5_5V = 3, /*!< 5.5 V */ +} regulator_voltage_sw3; + +/*! + * The \b TPmicDVSTransitionSpeed enum defines the rate with which the + * voltage transition occurs. + */ +enum { + ESysDependent, + E25mVEach4us, + E25mVEach8us, + E25mvEach16us +} DVS_transition_speed; + +/* + * Reg Regulator Mode 0 + */ +#define VAUDIO_EN_LSH 0 +#define VAUDIO_EN_WID 1 +#define VAUDIO_EN_ENABLE 1 +#define VAUDIO_EN_DISABLE 0 +#define VIOHI_EN_LSH 3 +#define VIOHI_EN_WID 1 +#define VIOHI_EN_ENABLE 1 +#define VIOHI_EN_DISABLE 0 +#define VIOLO_EN_LSH 6 +#define VIOLO_EN_WID 1 +#define VIOLO_EN_ENABLE 1 +#define VIOLO_EN_DISABLE 0 +#define VDIG_EN_LSH 9 +#define VDIG_EN_WID 1 +#define VDIG_EN_ENABLE 1 +#define VDIG_EN_DISABLE 0 +#define VGEN_EN_LSH 12 +#define VGEN_EN_WID 1 +#define VGEN_EN_ENABLE 1 +#define VGEN_EN_DISABLE 0 +#define VRFDIG_EN_LSH 15 +#define VRFDIG_EN_WID 1 +#define VRFDIG_EN_ENABLE 1 +#define VRFDIG_EN_DISABLE 0 +#define VRFREF_EN_LSH 18 +#define VRFREF_EN_WID 1 +#define VRFREF_EN_ENABLE 1 +#define VRFREF_EN_DISABLE 0 +#define VRFCP_EN_LSH 21 +#define VRFCP_EN_WID 1 +#define VRFCP_EN_ENABLE 1 +#define VRFCP_EN_DISABLE 0 + +/* + * Reg Regulator Mode 1 + */ +#define VSIM_EN_LSH 0 +#define VSIM_EN_WID 1 +#define VSIM_EN_ENABLE 1 +#define VSIM_EN_DISABLE 0 +#define VESIM_EN_LSH 3 +#define VESIM_EN_WID 1 +#define VESIM_EN_ENABLE 1 +#define VESIM_EN_DISABLE 0 +#define VCAM_EN_LSH 6 +#define VCAM_EN_WID 1 +#define VCAM_EN_ENABLE 1 +#define VCAM_EN_DISABLE 0 +#define VRFBG_EN_LSH 9 +#define VRFBG_EN_WID 1 +#define VRFBG_EN_ENABLE 1 +#define VRFBG_EN_DISABLE 0 +#define VVIB_EN_LSH 11 +#define VVIB_EN_WID 1 +#define VVIB_EN_ENABLE 1 +#define VVIB_EN_DISABLE 0 +#define VRF1_EN_LSH 12 +#define VRF1_EN_WID 1 +#define VRF1_EN_ENABLE 1 +#define VRF1_EN_DISABLE 0 +#define VRF2_EN_LSH 15 +#define VRF2_EN_WID 1 +#define VRF2_EN_ENABLE 1 +#define VRF2_EN_DISABLE 0 +#define VMMC1_EN_LSH 18 +#define VMMC1_EN_WID 1 +#define VMMC1_EN_ENABLE 1 +#define VMMC1_EN_DISABLE 0 +#define VMMC2_EN_LSH 21 +#define VMMC2_EN_WID 1 +#define VMMC2_EN_ENABLE 1 +#define VMMC2_EN_DISABLE 0 + +/* + * Reg Regulator Setting 0 + */ +#define VIOLO_LSH 2 +#define VIOLO_WID 2 +#define VDIG_LSH 4 +#define VDIG_WID 2 +#define VGEN_LSH 6 +#define VGEN_WID 3 +#define VRFDIG_LSH 9 +#define VRFDIG_WID 2 +#define VRFREF_LSH 11 +#define VRFREF_WID 2 +#define VRFCP_LSH 13 +#define VRFCP_WID 1 +#define VSIM_LSH 14 +#define VSIM_WID 1 +#define VESIM_LSH 15 +#define VESIM_WID 1 +#define VCAM_LSH 16 +#define VCAM_WID 3 + +/* + * Reg Regulator Setting 1 + */ +#define VVIB_LSH 0 +#define VVIB_WID 2 +#define VRF1_LSH 2 +#define VRF1_WID 2 +#define VRF2_LSH 4 +#define VRF2_WID 2 +#define VMMC1_LSH 6 +#define VMMC1_WID 3 +#define VMMC2_LSH 9 +#define VMMC2_WID 3 + +/* + * Reg Switcher 0 + */ +#define SW1A_LSH 0 +#define SW1A_WID 6 +#define SW1A_DVS_LSH 6 +#define SW1A_DVS_WID 6 +#define SW1A_STDBY_LSH 12 +#define SW1A_STDBY_WID 6 + +/* + * Reg Switcher 1 + */ +#define SW1B_LSH 0 +#define SW1B_WID 6 +#define SW1B_DVS_LSH 6 +#define SW1B_DVS_WID 6 +#define SW1B_STDBY_LSH 12 +#define SW1B_STDBY_WID 6 + +/* + * Reg Switcher 2 + */ +#define SW2A_LSH 0 +#define SW2A_WID 6 +#define SW2A_DVS_LSH 6 +#define SW2A_DVS_WID 6 +#define SW2A_STDBY_LSH 12 +#define SW2A_STDBY_WID 6 + +/* + * Reg Switcher 3 + */ +#define SW2B_LSH 0 +#define SW2B_WID 6 +#define SW2B_DVS_LSH 6 +#define SW2B_DVS_WID 6 +#define SW2B_STDBY_LSH 12 +#define SW2B_STDBY_WID 6 + +/* + * Reg Switcher 4 + */ +#define SW1A_MODE_LSH 0 +#define SW1A_MODE_WID 2 +#define SW1A_STBY_MODE_LSH 2 +#define SW1A_STBY_MODE_WID 2 +#define SW1A_DVS_SPEED_LSH 6 +#define SW1A_DVS_SPEED_WID 2 +#define SW1B_MODE_LSH 10 +#define SW1B_MODE_WID 2 +#define SW1B_STBY_MODE_LSH 12 +#define SW1B_STBY_MODE_WID 2 +#define SW1B_DVS_SPEED_LSH 14 +#define SW1B_DVS_SPEED_WID 2 + +/* + * Reg Switcher 5 + */ +#define SW2A_MODE_LSH 0 +#define SW2A_MODE_WID 2 +#define SW2A_STBY_MODE_LSH 2 +#define SW2A_STBY_MODE_WID 2 +#define SW2A_DVS_SPEED_LSH 6 +#define SW2A_DVS_SPEED_WID 2 +#define SW2B_MODE_LSH 10 +#define SW2B_MODE_WID 2 +#define SW2B_STBY_MODE_LSH 12 +#define SW2B_STBY_MODE_WID 2 +#define SW2B_DVS_SPEED_LSH 14 +#define SW2B_DVS_SPEED_WID 2 +#define SW3_LSH 18 +#define SW3_WID 2 +#define SW3_EN_LSH 20 +#define SW3_EN_WID 2 +#define SW3_EN_ENABLE 1 +#define SW3_EN_DISABLE 0 + +/* + * Reg Regulator Misc. + */ +#define GPO1_EN_LSH 6 +#define GPO1_EN_WID 1 +#define GPO1_EN_ENABLE 1 +#define GPO1_EN_DISABLE 0 +#define GPO2_EN_LSH 8 +#define GPO2_EN_WID 1 +#define GPO2_EN_ENABLE 1 +#define GPO2_EN_DISABLE 0 +#define GPO3_EN_LSH 10 +#define GPO3_EN_WID 1 +#define GPO3_EN_ENABLE 1 +#define GPO3_EN_DISABLE 0 +#define GPO4_EN_LSH 12 +#define GPO4_EN_WID 1 +#define GPO4_EN_ENABLE 1 +#define GPO4_EN_DISABLE 0 + +/* + * Switcher mode configuration + */ +#define SW_MODE_SYNC_RECT_EN 0 +#define SW_MODE_PULSE_NO_SKIP_EN 1 +#define SW_MODE_PULSE_SKIP_EN 2 +#define SW_MODE_LOW_POWER_EN 3 + +#define dvs_speed E25mvEach16us + +static int mc13783_vaudio_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_ENABLE); + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vaudio_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_DISABLE); + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_viohi_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOHI_EN, VIOHI_EN_ENABLE); + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_viohi_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOHI_EN, VIOHI_EN_DISABLE); + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_violo_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0, register1 = 0; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1300)) + voltage = VIOLO_1_2V; + else if ((mV >= 1300) && (mV < 1500)) + voltage = VIOLO_1_3V; + else if ((mV >= 1500) && (mV < 1800)) + voltage = VIOLO_1_5V; + else + voltage = VIOLO_1_8V; + + register_val = BITFVAL(VIOLO, voltage); + register_mask = BITFMASK(VIOLO); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_violo_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VIOLO); + + switch (voltage) { + case VIOLO_1_2V: + mV = 1200; + break; + case VIOLO_1_3V: + mV = 1300; + break; + case VIOLO_1_5V: + mV = 1500; + break; + case VIOLO_1_8V: + mV = 1800; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_violo_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOLO_EN, VIOLO_EN_ENABLE); + register_mask = BITFMASK(VIOLO_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_violo_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOLO_EN, VIOLO_EN_DISABLE); + register_mask = BITFMASK(VIOLO_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vdig_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1300)) + voltage = VDIG_1_2V; + else if ((mV >= 1300) && (mV < 1500)) + voltage = VDIG_1_3V; + else if ((mV >= 1500) && (mV < 1800)) + voltage = VDIG_1_5V; + else + voltage = VDIG_1_8V; + + register_val = BITFVAL(VDIG, voltage); + register_mask = BITFMASK(VDIG); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vdig_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VDIG); + + switch (voltage) { + case VDIG_1_2V: + mV = 1200; + break; + case VDIG_1_3V: + mV = 1300; + break; + case VDIG_1_5V: + mV = 1500; + break; + case VDIG_1_8V: + mV = 1800; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vdig_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VDIG_EN, VDIG_EN_ENABLE); + register_mask = BITFMASK(VDIG_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vdig_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VDIG_EN, VDIG_EN_DISABLE); + register_mask = BITFMASK(VDIG_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vgen_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + int vgenid = rdev_get_id(reg); + + printk(KERN_INFO "VGEN ID is %d\n", vgenid); + + if ((mV >= 1100) && (mV < 1200)) + voltage = VGEN_1_1V; + else if ((mV >= 1200) && (mV < 1300)) + voltage = VGEN_1_2V; + else if ((mV >= 1300) && (mV < 1500)) + voltage = VGEN_1_3V; + else if ((mV >= 1500) && (mV < 1800)) + voltage = VGEN_1_5V; + else if ((mV >= 1800) && (mV < 2000)) + voltage = VGEN_1_8V; + else if ((mV >= 2000) && (mV < 2400)) + voltage = VGEN_2V; + else if ((mV >= 2400) && (mV < 2775)) + voltage = VGEN_2_4V; + else + voltage = VGEN_2_775V; + + register_val = BITFVAL(VGEN, voltage); + register_mask = BITFMASK(VGEN); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vgen_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VGEN); + + switch (voltage) { + case VGEN_1_2V: + mV = 1200; + break; + case VGEN_1_3V: + mV = 1300; + break; + case VGEN_1_5V: + mV = 1500; + break; + case VGEN_1_8V: + mV = 1800; + break; + case VGEN_1_1V: + mV = 1100; + break; + case VGEN_2V: + mV = 2000; + break; + case VGEN_2_775V: + mV = 2775; + break; + case VGEN_2_4V: + mV = 2400; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vgen_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN_EN, VGEN_EN_ENABLE); + register_mask = BITFMASK(VGEN_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vgen_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN_EN, VGEN_EN_DISABLE); + register_mask = BITFMASK(VGEN_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfdig_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1500)) + voltage = VRFDIG_1_2V; + else if ((mV >= 1500) && (mV < 1300)) + voltage = VRFDIG_1_5V; + else if ((mV >= 1800) && (mV < 1875)) + voltage = VRFDIG_1_8V; + else + voltage = VRFDIG_1_875V; + + register_val = BITFVAL(VRFDIG, voltage); + register_mask = BITFMASK(VRFDIG); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfdig_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VRFDIG); + + switch (voltage) { + case VRFDIG_1_2V: + mV = 1200; + break; + case VRFDIG_1_5V: + mV = 1500; + break; + case VRFDIG_1_8V: + mV = 1800; + break; + case VRFDIG_1_875V: + mV = 1875; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vrfdig_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFDIG_EN, VRFDIG_EN_ENABLE); + register_mask = BITFMASK(VRFDIG_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfdig_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFDIG_EN, VRFDIG_EN_DISABLE); + register_mask = BITFMASK(VRFDIG_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfref_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2475) && (mV < 2600)) + voltage = VRFREF_2_475V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VRFREF_2_6V; + else if ((mV >= 2700) && (mV < 2775)) + voltage = VRFREF_2_7V; + else + voltage = VRFREF_2_775V; + + register_val = BITFVAL(VRFREF, voltage); + register_mask = BITFMASK(VRFREF); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfref_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VRFREF); + + switch (voltage) { + case VRFREF_2_475V: + mV = 2475; + break; + case VRFREF_2_6V: + mV = 2600; + break; + case VRFREF_2_7V: + mV = 2700; + break; + case VRFREF_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vrfref_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFREF_EN, VRFREF_EN_ENABLE); + register_mask = BITFMASK(VRFREF_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfref_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFREF_EN, VRFREF_EN_DISABLE); + register_mask = BITFMASK(VRFREF_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfcp_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2700) && (mV < 2775)) + voltage = VRFCP_2_7V; + else + voltage = VRFCP_2_775V; + + register_val = BITFVAL(VRFCP, voltage); + register_mask = BITFMASK(VRFCP); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfcp_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VRFCP); + + switch (voltage) { + case VRFCP_2_7V: + mV = 2700; + break; + case VRFCP_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vrfcp_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFCP_EN, VRFCP_EN_ENABLE); + register_mask = BITFMASK(VRFCP_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrfcp_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VRFCP_EN, VRFCP_EN_DISABLE); + register_mask = BITFMASK(VRFCP_EN); + register1 = REG_REGULATOR_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vsim_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1800) && (mV < 2900)) + voltage = VSIM_1_8V; + else + voltage = VSIM_2_9V; + + register_val = BITFVAL(VSIM, voltage); + register_mask = BITFMASK(VSIM); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vsim_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VSIM); + + switch (voltage) { + case VSIM_1_8V: + mV = 1800; + break; + case VSIM_2_9V: + mV = 1900; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vsim_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VSIM_EN, VSIM_EN_ENABLE); + register_mask = BITFMASK(VSIM_EN); + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vsim_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VSIM_EN, VSIM_EN_DISABLE); + register_mask = BITFMASK(VSIM_EN); + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vesim_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1800) && (mV < 2900)) + voltage = VESIM_1_8V; + else + voltage = VESIM_2_9V; + + register_val = BITFVAL(VESIM, voltage); + register_mask = BITFMASK(VESIM); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vesim_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VESIM); + + switch (voltage) { + case VESIM_1_8V: + mV = 1800; + break; + case VESIM_2_9V: + mV = 1900; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vesim_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VESIM_EN, VESIM_EN_ENABLE); + register_mask = BITFMASK(VESIM_EN); + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vesim_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VESIM_EN, VESIM_EN_DISABLE); + register_mask = BITFMASK(VESIM_EN); + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vcam_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1500) && (mV < 1800)) + voltage = VCAM_1_5V; + else if ((mV >= 1800) && (mV < 2500)) + voltage = VCAM_1_8V; + else if ((mV >= 2500) && (mV < 2550)) + voltage = VCAM_2_5V; + else if ((mV >= 2550) && (mV < 2600)) + voltage = VCAM_2_55V; + if ((mV >= 2600) && (mV < 2750)) + voltage = VCAM_2_6V; + else if ((mV >= 2750) && (mV < 2800)) + voltage = VCAM_2_75V; + else if ((mV >= 2800) && (mV < 3000)) + voltage = VCAM_2_8V; + else + voltage = VCAM_3V; + + register_val = BITFVAL(VCAM, voltage); + register_mask = BITFMASK(VCAM); + register1 = REG_REGULATOR_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vcam_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VCAM); + + switch (voltage) { + case VCAM_1_5V: + mV = 1500; + break; + case VCAM_1_8V: + mV = 1800; + break; + case VCAM_2_5V: + mV = 2500; + break; + case VCAM_2_55V: + mV = 2550; + break; + case VCAM_2_6V: + mV = 2600; + break; + case VCAM_2_75V: + mV = 2750; + break; + case VCAM_2_8V: + mV = 2800; + break; + case VCAM_3V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vcam_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VCAM_EN, VCAM_EN_ENABLE); + register_mask = BITFMASK(VCAM_EN); + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vcam_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VCAM_EN, VCAM_EN_DISABLE); + register_mask = BITFMASK(VCAM_EN); + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vvib_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1300) && (mV < 1800)) + voltage = VVIB_1_3V; + else if ((mV >= 1800) && (mV < 2000)) + voltage = VVIB_1_8V; + else if ((mV >= 2000) && (mV < 3000)) + voltage = VVIB_2V; + else + voltage = VVIB_3V; + + register_val = BITFVAL(VVIB, voltage); + register_mask = BITFMASK(VVIB); + register1 = REG_REGULATOR_SETTING_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vvib_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VVIB); + + switch (voltage) { + case VVIB_1_3V: + mV = 1300; + break; + case VVIB_1_8V: + mV = 1800; + break; + case VVIB_2V: + mV = 2000; + break; + case VVIB_3V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vvib_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VVIB_EN, VVIB_EN_ENABLE); + register_mask = BITFMASK(VVIB_EN); + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vvib_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VVIB_EN, VVIB_EN_DISABLE); + register_mask = BITFMASK(VVIB_EN); + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrf_set_voltage(struct regulator_dev *reg, int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, rf = rdev_get_id(reg), mV = uV / 1000; + + if ((mV >= 1500) && (mV < 1875)) + voltage = VRF_1_5V; + else if ((mV >= 1875) && (mV < 2700)) + voltage = VRF_1_875V; + else if ((mV >= 2700) && (mV < 2775)) + voltage = VRF_2_7V; + else + voltage = VRF_2_775V; + + switch (rf) { + case MC13783_VRF1: + register_val = BITFVAL(VRF1, voltage); + register_mask = BITFMASK(VRF1); + break; + case MC13783_VRF2: + register_val = BITFVAL(VRF2, voltage); + register_mask = BITFMASK(VRF2); + break; + default: + return -EINVAL; + } + + register1 = REG_REGULATOR_SETTING_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrf_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, rf = rdev_get_id(reg), mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1, + ®ister_val, PMIC_ALL_BITS)); + + switch (rf) { + case MC13783_VRF1: + voltage = BITFEXT(register_val, VRF1); + break; + case MC13783_VRF2: + voltage = BITFEXT(register_val, VRF2); + break; + default: + return -EINVAL; + }; + + switch (voltage) { + case VRF_1_5V: + mV = 1500; + break; + case VRF_1_875V: + mV = 1875; + break; + case VRF_2_7V: + mV = 2700; + break; + case VRF_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vrf_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int vrf = rdev_get_id(reg); + + switch (vrf) { + case MC13783_VRF1: + register_val = BITFVAL(VRF1_EN, VRF1_EN_ENABLE); + register_mask = BITFMASK(VRF1_EN); + break; + case MC13783_VRF2: + register_val = BITFVAL(VRF2_EN, VRF2_EN_ENABLE); + register_mask = BITFMASK(VRF2_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vrf_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int vrf = rdev_get_id(reg); + + switch (vrf) { + case MC13783_VRF1: + register_val = BITFVAL(VRF1_EN, VRF1_EN_DISABLE); + register_mask = BITFMASK(VRF1_EN); + break; + case MC13783_VRF2: + register_val = BITFVAL(VRF2_EN, VRF2_EN_DISABLE); + register_mask = BITFMASK(VRF2_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vmmc_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mmc = rdev_get_id(reg), mV = uV / 1000; + + printk(KERN_INFO "VMMC ID is %d\n", mmc); + + if ((mV >= 1600) && (mV < 1800)) + voltage = VMMC_1_6V; + else if ((mV >= 1800) && (mV < 2000)) + voltage = VMMC_1_8V; + else if ((mV >= 2000) && (mV < 2600)) + voltage = VMMC_2V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VMMC_2_6V; + else if ((mV >= 2700) && (mV < 2800)) + voltage = VMMC_2_7V; + else if ((mV >= 2800) && (mV < 2900)) + voltage = VMMC_2_8V; + else if ((mV >= 2900) && (mV < 3000)) + voltage = VMMC_2_9V; + else + voltage = VMMC_3V; + + switch (mmc) { + case MC13783_VMMC1: + register_val = BITFVAL(VMMC1, voltage); + register_mask = BITFMASK(VMMC1); + break; + case MC13783_VMMC2: + register_val = BITFVAL(VMMC2, voltage); + register_mask = BITFMASK(VMMC2); + break; + default: + return -EINVAL; + } + + register1 = REG_REGULATOR_SETTING_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vmmc_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mmc = rdev_get_id(reg), mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_REGULATOR_SETTING_1, + ®ister_val, PMIC_ALL_BITS)); + + switch (mmc) { + case MC13783_VMMC1: + voltage = BITFEXT(register_val, VMMC1); + break; + case MC13783_VMMC2: + voltage = BITFEXT(register_val, VMMC2); + break; + default: + return -EINVAL; + } + + switch (voltage) { + case VMMC_1_6V: + mV = 1600; + break; + case VMMC_1_8V: + mV = 1800; + break; + case VMMC_2V: + mV = 2000; + break; + case VMMC_2_6V: + mV = 2600; + break; + case VMMC_2_7V: + mV = 2700; + break; + case VMMC_2_8V: + mV = 2800; + break; + case VMMC_2_9V: + mV = 2900; + break; + case VMMC_3V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_vmmc_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int vmmc = rdev_get_id(reg); + + switch (vmmc) { + case MC13783_VMMC1: + register_val = BITFVAL(VMMC1_EN, VMMC1_EN_ENABLE); + register_mask = BITFMASK(VMMC1_EN); + break; + case MC13783_VMMC2: + register_val = BITFVAL(VMMC2_EN, VMMC2_EN_ENABLE); + register_mask = BITFMASK(VMMC2_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_vmmc_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int vmmc = rdev_get_id(reg); + + switch (vmmc) { + case MC13783_VMMC1: + register_val = BITFVAL(VMMC1_EN, VMMC1_EN_DISABLE); + register_mask = BITFMASK(VMMC1_EN); + break; + case MC13783_VMMC2: + register_val = BITFVAL(VMMC2_EN, VMMC2_EN_DISABLE); + register_mask = BITFMASK(VMMC2_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_REGULATOR_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_gpo_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = rdev_get_id(reg); + + switch (gpo) { + case MC13783_GPO1: + register_val = BITFVAL(GPO1_EN, GPO1_EN_ENABLE); + register_mask = BITFMASK(GPO1_EN); + break; + case MC13783_GPO2: + register_val = BITFVAL(GPO2_EN, GPO2_EN_ENABLE); + register_mask = BITFMASK(GPO2_EN); + break; + case MC13783_GPO3: + register_val = BITFVAL(GPO3_EN, GPO3_EN_ENABLE); + register_mask = BITFMASK(GPO3_EN); + break; + case MC13783_GPO4: + register_val = BITFVAL(GPO4_EN, GPO4_EN_ENABLE); + register_mask = BITFMASK(GPO4_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISCELLANEOUS; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_gpo_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = rdev_get_id(reg); + + switch (gpo) { + case MC13783_GPO1: + register_val = BITFVAL(GPO1_EN, GPO1_EN_DISABLE); + register_mask = BITFMASK(GPO1_EN); + break; + case MC13783_GPO2: + register_val = BITFVAL(GPO2_EN, GPO2_EN_DISABLE); + register_mask = BITFMASK(GPO2_EN); + break; + case MC13783_GPO3: + register_val = BITFVAL(GPO3_EN, GPO3_EN_DISABLE); + register_mask = BITFMASK(GPO3_EN); + break; + case MC13783_GPO4: + register_val = BITFVAL(GPO4_EN, GPO4_EN_DISABLE); + register_mask = BITFMASK(GPO4_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISCELLANEOUS; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_sw3_set_voltage(struct regulator_dev *reg, int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0, register1 = 0; + int voltage, mV = uV / 1000; + + if ((mV >= 5000) && (mV < 5500)) + voltage = SW3_5V; + else + voltage = SW3_5_5V; + + register_val = BITFVAL(SW3, voltage); + register_mask = BITFMASK(SW3); + register1 = REG_SWITCHERS_5; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_sw3_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_5, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW3); + + if (voltage == SW3_5_5V) + mV = 5500; + else + mV = 5000; + + return mV * 1000; +} + +static int mc13783_sw3_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(SW3_EN, SW3_EN_ENABLE); + register_mask = BITFMASK(SW3_EN); + register1 = REG_SWITCHERS_5; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_sw3_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(SW3_EN, SW3_EN_DISABLE); + register_mask = BITFMASK(SW3_EN); + register1 = REG_SWITCHERS_5; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_sw_set_normal_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage, sw = rdev_get_id(reg), mV = uV / 1000; + + if ((mV >= 900) && (mV < 925)) + voltage = SW_0_9V; + else if ((mV >= 925) && (mV < 950)) + voltage = SW_0_925V; + else if ((mV >= 950) && (mV < 975)) + voltage = SW_0_95V; + else if ((mV >= 975) && (mV < 1000)) + voltage = SW_0_975V; + else if ((mV >= 1000) && (mV < 1025)) + voltage = SW_1V; + else if ((mV >= 1025) && (mV < 1050)) + voltage = SW_1_025V; + else if ((mV >= 1050) && (mV < 1075)) + voltage = SW_1_05V; + else if ((mV >= 1075) && (mV < 1100)) + voltage = SW_1_075V; + else if ((mV >= 1100) && (mV < 1125)) + voltage = SW_1_1V; + else if ((mV >= 1125) && (mV < 1150)) + voltage = SW_1_125V; + else if ((mV >= 1150) && (mV < 1175)) + voltage = SW_1_15V; + else if ((mV >= 1175) && (mV < 1200)) + voltage = SW_1_175V; + else if ((mV >= 1200) && (mV < 1225)) + voltage = SW_1_2V; + else if ((mV >= 1225) && (mV < 1250)) + voltage = SW_1_225V; + else if ((mV >= 1250) && (mV < 1275)) + voltage = SW_1_25V; + else if ((mV >= 1275) && (mV < 1300)) + voltage = SW_1_275V; + else if ((mV >= 1300) && (mV < 1325)) + voltage = SW_1_3V; + else if ((mV >= 1325) && (mV < 1350)) + voltage = SW_1_325V; + else if ((mV >= 1350) && (mV < 1375)) + voltage = SW_1_35V; + else if ((mV >= 1375) && (mV < 1400)) + voltage = SW_1_375V; + else if ((mV >= 1400) && (mV < 1425)) + voltage = SW_1_4V; + else if ((mV >= 1425) && (mV < 1450)) + voltage = SW_1_425V; + else if ((mV >= 1450) && (mV < 1475)) + voltage = SW_1_45V; + else if ((mV >= 1475) && (mV < 1500)) + voltage = SW_1_475V; + else if ((mV >= 1500) && (mV < 1525)) + voltage = SW_1_5V; + else if ((mV >= 1525) && (mV < 1550)) + voltage = SW_1_525V; + else if ((mV >= 1550) && (mV < 1575)) + voltage = SW_1_55V; + else if ((mV >= 1575) && (mV < 1600)) + voltage = SW_1_575V; + else if ((mV >= 1600) && (mV < 1625)) + voltage = SW_1_6V; + else if ((mV >= 1625) && (mV < 1650)) + voltage = SW_1_625V; + else if ((mV >= 1650) && (mV < 1675)) + voltage = SW_1_65V; + else if ((mV >= 1675) && (mV < 1700)) + voltage = SW_1_675V; + else if ((mV >= 1700) && (mV < 1800)) + voltage = SW_1_7V; + else if ((mV >= 1800) && (mV < 1850)) + voltage = SW_1_8V; + else if ((mV >= 1850) && (mV < 2000)) + voltage = SW_1_85V; + else if ((mV >= 2000) && (mV < 2100)) + voltage = SW_2V; + else if ((mV >= 2100) && (mV < 2200)) + voltage = SW_2_1V; + else + voltage = SW_2_2V; + + switch (sw) { + case MC13783_SW1A: + register1 = REG_SWITCHERS_0; + register_val = BITFVAL(SW1A, voltage); + register_mask = BITFMASK(SW1A); + break; + case MC13783_SW1B: + register1 = REG_SWITCHERS_1; + register_val = BITFVAL(SW1B, voltage); + register_mask = BITFMASK(SW1B); + break; + case MC13783_SW2A: + register1 = REG_SWITCHERS_2; + register_val = BITFVAL(SW2A, voltage); + register_mask = BITFMASK(SW2A); + break; + case MC13783_SW2B: + register1 = REG_SWITCHERS_3; + register_val = BITFVAL(SW2B, voltage); + register_mask = BITFMASK(SW2B); + break; + default: + return -EINVAL; + } + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_sw_get_normal_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0, sw = rdev_get_id(reg); + + switch (sw) { + case MC13783_SW1A: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1A); + break; + case MC13783_SW1B: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1B); + break; + case MC13783_SW2A: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_2, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2A); + break; + case MC13783_SW2B: + CHECK_ERROR(pmic_read_reg(REG_SWITCHERS_3, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2B); + break; + default: + return -EINVAL; + } + + switch (voltage) { + case SW_0_9V: + mV = 900; + break; + case SW_0_925V: + mV = 925; + break; + case SW_0_95V: + mV = 950; + break; + case SW_0_975V: + mV = 975; + break; + case SW_1V: + mV = 1000; + break; + case SW_1_025V: + mV = 1025; + break; + case SW_1_05V: + mV = 1050; + break; + case SW_1_075V: + mV = 1075; + break; + case SW_1_1V: + mV = 1100; + break; + case SW_1_125V: + mV = 1125; + break; + case SW_1_15V: + mV = 1150; + break; + case SW_1_175V: + mV = 1175; + break; + case SW_1_2V: + mV = 1200; + break; + case SW_1_225V: + mV = 1225; + break; + case SW_1_25V: + mV = 1250; + break; + case SW_1_275V: + mV = 1275; + break; + case SW_1_3V: + mV = 1300; + break; + case SW_1_325V: + mV = 1325; + break; + case SW_1_35V: + mV = 1350; + break; + case SW_1_375V: + mV = 1375; + break; + case SW_1_4V: + mV = 1400; + break; + case SW_1_425V: + mV = 1425; + break; + case SW_1_45V: + mV = 1450; + break; + case SW_1_475V: + mV = 1475; + break; + case SW_1_5V: + mV = 1500; + break; + case SW_1_525V: + mV = 1525; + break; + case SW_1_55V: + mV = 1550; + break; + case SW_1_575V: + mV = 1575; + break; + case SW_1_6V: + mV = 1600; + break; + case SW_1_625V: + mV = 1625; + break; + case SW_1_65V: + mV = 1650; + break; + case SW_1_675V: + mV = 1675; + break; + case SW_1_7V: + mV = 1700; + break; + case SW_1_8V: + mV = 1800; + break; + case SW_1_85V: + mV = 1850; + break; + case SW_2V: + mV = 2000; + break; + case SW_2_1V: + mV = 2100; + break; + case SW_2_2V: + mV = 2200; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13783_sw_normal_enable(struct regulator_dev *reg) +{ + return 0; +} + +static int mc13783_sw_normal_disable(struct regulator_dev *reg) +{ + return 0; +} + +static int mc13783_sw_stby_enable(struct regulator_dev *reg) +{ + return 0; +} + +static int mc13783_sw_stby_disable(struct regulator_dev *reg) +{ + return 0; +} + +static int mc13783_sw_set_stby_voltage(struct regulator_dev *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage, sw = rdev_get_id(reg), mV = uV / 1000; + + if ((mV >= 900) && (mV < 925)) + voltage = SW_0_9V; + else if ((mV >= 925) && (mV < 950)) + voltage = SW_0_925V; + else if ((mV >= 950) && (mV < 975)) + voltage = SW_0_95V; + else if ((mV >= 975) && (mV < 1000)) + voltage = SW_0_975V; + else if ((mV >= 1000) && (mV < 1025)) + voltage = SW_1V; + else if ((mV >= 1025) && (mV < 1050)) + voltage = SW_1_025V; + else if ((mV >= 1050) && (mV < 1075)) + voltage = SW_1_05V; + else if ((mV >= 1075) && (mV < 1100)) + voltage = SW_1_075V; + else if ((mV >= 1100) && (mV < 1125)) + voltage = SW_1_1V; + else if ((mV >= 1125) && (mV < 1150)) + voltage = SW_1_125V; + else if ((mV >= 1150) && (mV < 1175)) + voltage = SW_1_15V; + else if ((mV >= 1175) && (mV < 1200)) + voltage = SW_1_175V; + else if ((mV >= 1200) && (mV < 1225)) + voltage = SW_1_2V; + else if ((mV >= 1225) && (mV < 1250)) + voltage = SW_1_225V; + else if ((mV >= 1250) && (mV < 1275)) + voltage = SW_1_25V; + else if ((mV >= 1275) && (mV < 1300)) + voltage = SW_1_275V; + else if ((mV >= 1300) && (mV < 1325)) + voltage = SW_1_3V; + else if ((mV >= 1325) && (mV < 1350)) + voltage = SW_1_325V; + else if ((mV >= 1350) && (mV < 1375)) + voltage = SW_1_35V; + else if ((mV >= 1375) && (mV < 1400)) + voltage = SW_1_375V; + else if ((mV >= 1400) && (mV < 1425)) + voltage = SW_1_4V; + else if ((mV >= 1425) && (mV < 1450)) + voltage = SW_1_425V; + else if ((mV >= 1450) && (mV < 1475)) + voltage = SW_1_45V; + else if ((mV >= 1475) && (mV < 1500)) + voltage = SW_1_475V; + else if ((mV >= 1500) && (mV < 1525)) + voltage = SW_1_5V; + else if ((mV >= 1525) && (mV < 1550)) + voltage = SW_1_525V; + else if ((mV >= 1550) && (mV < 1575)) + voltage = SW_1_55V; + else if ((mV >= 1575) && (mV < 1600)) + voltage = SW_1_575V; + else if ((mV >= 1600) && (mV < 1625)) + voltage = SW_1_6V; + else if ((mV >= 1625) && (mV < 1650)) + voltage = SW_1_625V; + else if ((mV >= 1650) && (mV < 1675)) + voltage = SW_1_65V; + else if ((mV >= 1675) && (mV < 1700)) + voltage = SW_1_675V; + else if ((mV >= 1700) && (mV < 1800)) + voltage = SW_1_7V; + else if ((mV >= 1800) && (mV < 1850)) + voltage = SW_1_8V; + else if ((mV >= 1850) && (mV < 2000)) + voltage = SW_1_85V; + else if ((mV >= 2000) && (mV < 2100)) + voltage = SW_2V; + else if ((mV >= 2100) && (mV < 2200)) + voltage = SW_2_1V; + else + voltage = SW_2_2V; + + switch (sw) { + case MC13783_SW1A: + register1 = REG_SWITCHERS_0; + register_val = BITFVAL(SW1A_STDBY, voltage); + register_mask = BITFMASK(SW1A_STDBY); + break; + case MC13783_SW1B: + register1 = REG_SWITCHERS_1; + register_val = BITFVAL(SW1B_STDBY, voltage); + register_mask = BITFMASK(SW1B_STDBY); + break; + case MC13783_SW2A: + register1 = REG_SWITCHERS_2; + register_val = BITFVAL(SW2A_STDBY, voltage); + register_mask = BITFMASK(SW2A_STDBY); + break; + case MC13783_SW2B: + register1 = REG_SWITCHERS_3; + register_val = BITFVAL(SW2B_STDBY, voltage); + register_mask = BITFMASK(SW2B_STDBY); + break; + default: + return -EINVAL; + } + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13783_sw_set_normal_mode(struct regulator_dev *reg, + unsigned int mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int register1 = 0; + unsigned int l_mode; + int sw = rdev_get_id(reg); + + switch (mode) { + case REGULATOR_MODE_FAST: + /* SYNC RECT mode */ + l_mode = SW_MODE_SYNC_RECT_EN; + break; + case REGULATOR_MODE_NORMAL: + /* PULSE SKIP mode */ + l_mode = SW_MODE_PULSE_SKIP_EN; + break; + case REGULATOR_MODE_IDLE: + /* LOW POWER mode */ + l_mode = SW_MODE_LOW_POWER_EN; + break; + case REGULATOR_MODE_STANDBY: + /* NO PULSE SKIP mode */ + l_mode = SW_MODE_PULSE_NO_SKIP_EN; + break; + default: + return -EINVAL; + } + + switch (sw) { + case MC13783_SW1A: + reg_val = BITFVAL(SW1A_MODE, l_mode); + reg_mask = BITFMASK(SW1A_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW1B: + reg_val = BITFVAL(SW1B_MODE, l_mode); + reg_mask = BITFMASK(SW1B_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW2A: + reg_val = BITFVAL(SW2A_MODE, l_mode); + reg_mask = BITFMASK(SW2A_MODE); + register1 = REG_SWITCHERS_5; + break; + case MC13783_SW2B: + reg_val = BITFVAL(SW2B_MODE, l_mode); + reg_mask = BITFMASK(SW2B_MODE); + register1 = REG_SWITCHERS_5; + break; + default: + return -EINVAL; + } + + return pmic_write_reg(register1, reg_val, reg_mask); +} + +static unsigned int mc13783_sw_get_normal_mode(struct regulator_dev *reg) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int register1 = 0; + unsigned int l_mode = 0; + int sw = rdev_get_id(reg); + int ret = 0; + + switch (sw) { + case MC13783_SW1A: + reg_mask = BITFMASK(SW1A_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW1B: + reg_mask = BITFMASK(SW1B_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW2A: + reg_mask = BITFMASK(SW2A_MODE); + register1 = REG_SWITCHERS_5; + break; + case MC13783_SW2B: + reg_mask = BITFMASK(SW2B_MODE); + register1 = REG_SWITCHERS_5; + break; + default: + return -EINVAL; + } + + ret = pmic_read_reg(register1, ®_val, reg_mask); + if (ret != 0) + return ret; + + switch (sw) { + case MC13783_SW1A: + l_mode = BITFEXT(reg_val, SW1A_MODE); + break; + case MC13783_SW1B: + l_mode = BITFEXT(reg_val, SW1B_MODE); + break; + case MC13783_SW2A: + l_mode = BITFEXT(reg_val, SW2A_MODE); + break; + case MC13783_SW2B: + l_mode = BITFEXT(reg_val, SW2B_MODE); + break; + default: + return -EINVAL; + } + + if (l_mode == SW_MODE_SYNC_RECT_EN) { + return REGULATOR_MODE_FAST; + } else if (l_mode == SW_MODE_PULSE_NO_SKIP_EN) { + return REGULATOR_MODE_STANDBY; + } else if (l_mode == SW_MODE_PULSE_SKIP_EN) { + return REGULATOR_MODE_NORMAL; + } else if (l_mode == SW_MODE_LOW_POWER_EN) { + return REGULATOR_MODE_IDLE; + } else { + return -EINVAL; + } +} + +static int mc13783_sw_set_stby_mode(struct regulator_dev *reg, + unsigned int mode) +{ + unsigned int reg_val = 0, reg_mask = 0; + unsigned int register1 = 0; + unsigned int l_mode; + int sw = rdev_get_id(reg); + + switch (mode) { + case REGULATOR_MODE_FAST: + /* SYNC RECT mode */ + l_mode = SW_MODE_SYNC_RECT_EN; + break; + case REGULATOR_MODE_NORMAL: + /* PULSE SKIP mode */ + l_mode = SW_MODE_PULSE_SKIP_EN; + break; + case REGULATOR_MODE_IDLE: + /* LOW POWER mode */ + l_mode = SW_MODE_LOW_POWER_EN; + break; + case REGULATOR_MODE_STANDBY: + /* NO PULSE SKIP mode */ + l_mode = SW_MODE_PULSE_NO_SKIP_EN; + break; + default: + return -EINVAL; + } + + switch (sw) { + case MC13783_SW1A: + reg_val = BITFVAL(SW1A_STBY_MODE, l_mode); + reg_mask = BITFMASK(SW1A_STBY_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW1B: + reg_val = BITFVAL(SW1B_STBY_MODE, l_mode); + reg_mask = BITFMASK(SW1B_STBY_MODE); + register1 = REG_SWITCHERS_4; + break; + case MC13783_SW2A: + reg_val = BITFVAL(SW2A_STBY_MODE, l_mode); + reg_mask = BITFMASK(SW2A_STBY_MODE); + register1 = REG_SWITCHERS_5; + break; + case MC13783_SW2B: + reg_val = BITFVAL(SW2B_STBY_MODE, l_mode); + reg_mask = BITFMASK(SW2B_STBY_MODE); + register1 = REG_SWITCHERS_5; + break; + default: + return -EINVAL; + } + + return pmic_write_reg(register1, reg_val, reg_mask); +} + +static struct regulator_ops mc13783_vaudio_ops = { + .enable = mc13783_vaudio_enable, + .disable = mc13783_vaudio_disable, +}; + +static struct regulator_ops mc13783_viohi_ops = { + .enable = mc13783_viohi_enable, + .disable = mc13783_viohi_disable, +}; + +static struct regulator_ops mc13783_violo_ops = { + .set_voltage = mc13783_violo_set_voltage, + .get_voltage = mc13783_violo_get_voltage, + .enable = mc13783_violo_enable, + .disable = mc13783_violo_disable, +}; + +static struct regulator_ops mc13783_vdig_ops = { + .set_voltage = mc13783_vdig_set_voltage, + .get_voltage = mc13783_vdig_get_voltage, + .enable = mc13783_vdig_enable, + .disable = mc13783_vdig_disable, +}; + +static struct regulator_ops mc13783_vgen_ops = { + .set_voltage = mc13783_vgen_set_voltage, + .get_voltage = mc13783_vgen_get_voltage, + .enable = mc13783_vgen_enable, + .disable = mc13783_vgen_disable, +}; + +static struct regulator_ops mc13783_vrfdig_ops = { + .set_voltage = mc13783_vrfdig_set_voltage, + .get_voltage = mc13783_vrfdig_get_voltage, + .enable = mc13783_vrfdig_enable, + .disable = mc13783_vrfdig_disable, +}; + +static struct regulator_ops mc13783_vrfref_ops = { + .set_voltage = mc13783_vrfref_set_voltage, + .get_voltage = mc13783_vrfref_get_voltage, + .enable = mc13783_vrfref_enable, + .disable = mc13783_vrfref_disable, +}; + +static struct regulator_ops mc13783_vrfcp_ops = { + .set_voltage = mc13783_vrfcp_set_voltage, + .get_voltage = mc13783_vrfcp_get_voltage, + .enable = mc13783_vrfcp_enable, + .disable = mc13783_vrfcp_disable, +}; + +static struct regulator_ops mc13783_vsim_ops = { + .set_voltage = mc13783_vsim_set_voltage, + .get_voltage = mc13783_vsim_get_voltage, + .enable = mc13783_vsim_enable, + .disable = mc13783_vsim_disable, +}; + +static struct regulator_ops mc13783_vesim_ops = { + .set_voltage = mc13783_vesim_set_voltage, + .get_voltage = mc13783_vesim_get_voltage, + .enable = mc13783_vesim_enable, + .disable = mc13783_vesim_disable, +}; + +static struct regulator_ops mc13783_vcam_ops = { + .set_voltage = mc13783_vcam_set_voltage, + .get_voltage = mc13783_vcam_get_voltage, + .enable = mc13783_vcam_enable, + .disable = mc13783_vcam_disable, +}; + +static struct regulator_ops mc13783_vvib_ops = { + .set_voltage = mc13783_vvib_set_voltage, + .get_voltage = mc13783_vvib_get_voltage, + .enable = mc13783_vvib_enable, + .disable = mc13783_vvib_disable, +}; + +static struct regulator_ops mc13783_vrf_ops = { + .set_voltage = mc13783_vrf_set_voltage, + .get_voltage = mc13783_vrf_get_voltage, + .enable = mc13783_vrf_enable, + .disable = mc13783_vrf_disable, +}; + +static struct regulator_ops mc13783_vmmc_ops = { + .set_voltage = mc13783_vmmc_set_voltage, + .get_voltage = mc13783_vmmc_get_voltage, + .enable = mc13783_vmmc_enable, + .disable = mc13783_vmmc_disable, +}; + +static struct regulator_ops mc13783_gpo_ops = { + .enable = mc13783_gpo_enable, + .disable = mc13783_gpo_disable, +}; + +static struct regulator_ops mc13783_sw3_ops = { + .set_voltage = mc13783_sw3_set_voltage, + .get_voltage = mc13783_sw3_get_voltage, + .enable = mc13783_sw3_enable, + .disable = mc13783_sw3_disable, +}; + +static struct regulator_ops mc13783_sw1_ops = { + .set_voltage = mc13783_sw_set_normal_voltage, + .get_voltage = mc13783_sw_get_normal_voltage, + .get_mode = mc13783_sw_get_normal_mode, + .set_mode = mc13783_sw_set_normal_mode, + .set_suspend_voltage = mc13783_sw_set_stby_voltage, + .set_suspend_enable = mc13783_sw_stby_enable, + .set_suspend_disable = mc13783_sw_stby_disable, + .set_suspend_mode = mc13783_sw_set_stby_mode, +}; + +static struct regulator_ops mc13783_sw_normal_ops = { + .set_voltage = mc13783_sw_set_normal_voltage, + .get_voltage = mc13783_sw_get_normal_voltage, + .get_mode = mc13783_sw_get_normal_mode, + .set_mode = mc13783_sw_set_normal_mode, + .enable = mc13783_sw_normal_enable, + .disable = mc13783_sw_normal_disable, +}; + +static struct regulator_desc reg_mc13783[] = { + { + .name = "SW1A", + .id = MC13783_SW1A, + .ops = &mc13783_sw1_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SW1B", + .id = MC13783_SW1B, + .ops = &mc13783_sw_normal_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SW2A", + .id = MC13783_SW2A, + .ops = &mc13783_sw_normal_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SW2B", + .id = MC13783_SW2B, + .ops = &mc13783_sw_normal_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SW3", + .id = MC13783_SW3, + .ops = &mc13783_sw3_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VAUDIO", + .id = MC13783_VAUDIO, + .ops = &mc13783_vaudio_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VIOHI", + .id = MC13783_VIOHI, + .ops = &mc13783_viohi_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VIOLO", + .id = MC13783_VIOLO, + .ops = &mc13783_violo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VDIG", + .id = MC13783_VDIG, + .ops = &mc13783_vdig_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VGEN", + .id = MC13783_VGEN, + .ops = &mc13783_vgen_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VRFDIG", + .id = MC13783_VRFDIG, + .ops = &mc13783_vrfdig_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VRFREF", + .id = MC13783_VRFREF, + .ops = &mc13783_vrfref_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VRFCP", + .id = MC13783_VRFCP, + .ops = &mc13783_vrfcp_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VSIM", + .id = MC13783_VSIM, + .ops = &mc13783_vsim_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VESIM", + .id = MC13783_VESIM, + .ops = &mc13783_vesim_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VCAM", + .id = MC13783_VCAM, + .ops = &mc13783_vcam_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VRFBG", + .id = MC13783_VRFBG, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VVIB", + .id = MC13783_VVIB, + .ops = &mc13783_vvib_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VRF1", + .id = MC13783_VRF1, + .ops = &mc13783_vrf_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VRF2", + .id = MC13783_VRF2, + .ops = &mc13783_vrf_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VMMC1", + .id = MC13783_VMMC1, + .ops = &mc13783_vmmc_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VMMC2", + .id = MC13783_VMMC2, + .ops = &mc13783_vmmc_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPO1", + .id = MC13783_GPO1, + .ops = &mc13783_gpo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPO2", + .id = MC13783_GPO2, + .ops = &mc13783_gpo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPO3", + .id = MC13783_GPO3, + .ops = &mc13783_gpo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPO4", + .id = MC13783_GPO4, + .ops = &mc13783_gpo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, +}; + +/* + * Init and Exit + */ + +static int reg_mc13783_probe(struct platform_device *pdev) +{ + struct regulator_dev *rdev; + + /* register regulator */ + rdev = regulator_register(®_mc13783[pdev->id], &pdev->dev, + pdev->dev.platform_data, + dev_get_drvdata(&pdev->dev)); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + reg_mc13783[pdev->id].name); + return PTR_ERR(rdev); + } + platform_set_drvdata(pdev, rdev); + + return 0; +} + +static int mc13783_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + + regulator_unregister(rdev); + + return 0; +} + +int mc13783_register_regulator(struct mc13783 *mc13783, int reg, + struct regulator_init_data *initdata) +{ + struct platform_device *pdev; + int ret; + + if (mc13783->pmic.pdev[reg]) + return -EBUSY; + + pdev = platform_device_alloc("mc13783-regulatr", reg); + if (!pdev) + return -ENOMEM; + + mc13783->pmic.pdev[reg] = pdev; + + initdata->driver_data = mc13783; + + pdev->dev.platform_data = initdata; + pdev->dev.parent = mc13783->dev; + ret = platform_device_add(pdev); + + if (ret != 0) { + dev_err(mc13783->dev, "Failed to register regulator %d: %d\n", + reg, ret); + platform_device_del(pdev); + mc13783->pmic.pdev[reg] = NULL; + } + + return ret; +} +EXPORT_SYMBOL_GPL(mc13783_register_regulator); + +static struct platform_driver mc13783_regulator_driver = { + .probe = reg_mc13783_probe, + .remove = mc13783_regulator_remove, + .driver = { + .name = "mc13783-regulatr", + /* o left out due to string length */ + }, +}; + +static int __init mc13783_regulator_subsys_init(void) +{ + return platform_driver_register(&mc13783_regulator_driver); +} +subsys_initcall(mc13783_regulator_subsys_init); + +static void __exit mc13783_regulator_exit(void) +{ + platform_driver_unregister(&mc13783_regulator_driver); +} +module_exit(mc13783_regulator_exit); + + +/* Module information */ +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC13783 Regulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/reg-mc13892.c b/drivers/regulator/reg-mc13892.c new file mode 100644 index 000000000000..e3c6ab36426d --- /dev/null +++ b/drivers/regulator/reg-mc13892.c @@ -0,0 +1,1956 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +enum { + VDIG_1_05V = 0, + VDIG_1_25V, + VDIG_1_65V, + VDIG_1_80V, +} regulator_voltage_vdig; + +enum { + VPLL_1_05V = 0, + VPLL_1_25V, + VPLL_1_65V, + VPLL_1_80V, +} regulator_voltage_vpll; + +enum { + VGEN1_1_2V = 0, + VGEN1_1_5V, + VGEN1_2_775V, + VGEN1_3_15V, +} regulator_voltage_vgen1; + +enum { + VGEN2_1_2V = 0, + VGEN2_1_5V, + VGEN2_1_6V, + VGEN2_1_8V, + VGEN2_2_7V, + VGEN2_2_8V, + VGEN2_3_0V, + VGEN2_3_15V, +} regulator_voltage_vgen2; + +enum { + VGEN3_1_8V = 0, + VGEN3_2_9V, +} regulator_voltage_vgen3; + +enum { + VSD_1_8V = 0, + VSD_2_0V, + VSD_2_6V, + VSD_2_7V, + VSD_2_8V, + VSD_2_9V, + VSD_3_0V, + VSD_3_15V, +} regulator_voltage_vsd; + +enum { + VCAM_2_5V, + VCAM_2_6V, + VCAM_2_75V, + VCAM_3_0V, +} regulator_voltage_vcam; + +enum { + VAUDIO_2_3V, + VAUDIO_2_5V, + VAUDIO_2_775V, + VAUDIO_3V, +} regulator_voltage_vaudio; + +enum { + VUSB2_2_4V, + VUSB2_2_6V, + VUSB2_2_7V, + VUSB2_2_775V, +} regulator_voltage_vusb2; + +enum { + VVIDEO_2_7V, + VVIDEO_2_775V, + VVIDEO_2_5V, + VVIDEO_2_6V, +} regulator_voltage_vvideo; + +#define VAUDIO_LSH 4 +#define VAUDIO_WID 2 +#define VAUDIO_EN_LSH 15 +#define VAUDIO_EN_WID 1 +#define VAUDIO_EN_ENABLE 1 +#define VAUDIO_EN_DISABLE 0 + +#define VUSB2_LSH 11 +#define VUSB2_WID 2 +#define VUSB2_EN_LSH 18 +#define VUSB2_EN_WID 1 +#define VUSB2_EN_ENABLE 1 +#define VUSB2_EN_DISABLE 0 + +#define VVIDEO_LSH 2 +#define VVIDEO_WID 2 +#define VVIDEO_EN_LSH 12 +#define VVIDEO_EN_WID 1 +#define VVIDEO_EN_ENABLE 1 +#define VVIDEO_EN_DISABLE 0 + +#define SWBST_EN_LSH 20 +#define SWBST_EN_WID 1 +#define SWBST_EN_ENABLE 1 +#define SWBST_EN_DISABLE 0 + +#define VIOHI_EN_LSH 3 +#define VIOHI_EN_WID 1 +#define VIOHI_EN_ENABLE 1 +#define VIOHI_EN_DISABLE 0 + +#define VDIG_LSH 4 +#define VDIG_WID 2 +#define VDIG_EN_LSH 9 +#define VDIG_EN_WID 1 +#define VDIG_EN_ENABLE 1 +#define VDIG_EN_DISABLE 0 + +#define VPLL_LSH 9 +#define VPLL_WID 2 +#define VPLL_EN_LSH 15 +#define VPLL_EN_WID 1 +#define VPLL_EN_ENABLE 1 +#define VPLL_EN_DISABLE 0 + +#define VGEN1_LSH 0 +#define VGEN1_WID 2 +#define VGEN1_EN_LSH 0 +#define VGEN1_EN_WID 1 +#define VGEN1_EN_ENABLE 1 +#define VGEN1_EN_DISABLE 0 + +#define VGEN2_LSH 6 +#define VGEN2_WID 3 +#define VGEN2_EN_LSH 12 +#define VGEN2_EN_WID 1 +#define VGEN2_EN_ENABLE 1 +#define VGEN2_EN_DISABLE 0 + +#define VGEN3_LSH 14 +#define VGEN3_WID 1 +#define VGEN3_EN_LSH 0 +#define VGEN3_EN_WID 1 +#define VGEN3_EN_ENABLE 1 +#define VGEN3_EN_DISABLE 0 + +#define VSD_LSH 6 +#define VSD_WID 3 +#define VSD_EN_LSH 18 +#define VSD_EN_WID 1 +#define VSD_EN_ENABLE 1 +#define VSD_EN_DISABLE 0 + +#define VCAM_LSH 16 +#define VCAM_WID 2 +#define VCAM_EN_LSH 6 +#define VCAM_EN_WID 1 +#define VCAM_EN_ENABLE 1 +#define VCAM_EN_DISABLE 0 +#define VCAM_CONFIG_LSH 9 +#define VCAM_CONFIG_WID 1 +#define VCAM_CONFIG_EXT 1 +#define VCAM_CONFIG_INT 0 + +#define SW1_LSH 0 +#define SW1_WID 5 +#define SW1_DVS_LSH 5 +#define SW1_DVS_WID 5 +#define SW1_STDBY_LSH 10 +#define SW1_STDBY_WID 5 + +#define SW2_LSH 0 +#define SW2_WID 5 +#define SW2_DVS_LSH 5 +#define SW2_DVS_WID 5 +#define SW2_STDBY_LSH 10 +#define SW2_STDBY_WID 5 + +#define SW3_LSH 0 +#define SW3_WID 5 +#define SW3_STDBY_LSH 10 +#define SW3_STDBY_WID 5 + +#define SW4_LSH 0 +#define SW4_WID 5 +#define SW4_STDBY_LSH 10 +#define SW4_STDBY_WID 5 + +#define VUSB_EN_LSH 3 +#define VUSB_EN_WID 1 +#define VUSB_EN_ENABLE 1 +#define VUSB_EN_DISABLE 0 + +#define GPO1_EN_LSH 6 +#define GPO1_EN_WID 1 +#define GPO1_EN_ENABLE 1 +#define GPO1_EN_DISABLE 0 + +#define GPO2_EN_LSH 8 +#define GPO2_EN_WID 1 +#define GPO2_EN_ENABLE 1 +#define GPO2_EN_DISABLE 0 + +#define GPO3_EN_LSH 10 +#define GPO3_EN_WID 1 +#define GPO3_EN_ENABLE 1 +#define GPO3_EN_DISABLE 0 + +#define GPO4_EN_LSH 12 +#define GPO4_EN_WID 1 +#define GPO4_EN_ENABLE 1 +#define GPO4_EN_DISABLE 0 + +#define GPO4_ADIN_LSH 21 +#define GPO4_ADIN_WID 1 +#define GPO4_ADIN_ENABLE 1 +#define GPO4_ADIN_DISABLE 0 + +#define PWGT1SPI_EN_LSH 15 +#define PWGT1SPI_EN_WID 1 +#define PWGT1SPI_EN_ENABLE 0 +#define PWGT1SPI_EN_DISABLE 1 + +#define PWGT2SPI_EN_LSH 16 +#define PWGT2SPI_EN_WID 1 +#define PWGT2SPI_EN_ENABLE 0 +#define PWGT2SPI_EN_DISABLE 1 + +#define SWXHI_LSH 23 +#define SWXHI_WID 1 +#define SWXHI_ON 1 +#define SWXHI_OFF 0 + +static int mc13892_get_sw_hi_bit(int sw) +{ + unsigned int register_val = 0; + unsigned int reg = 0; + + switch (sw) { + case MC13892_SW1: + reg = REG_SW_0; + break; + case MC13892_SW2: + reg = REG_SW_1; + break; + case MC13892_SW3: + reg = REG_SW_2; + break; + case MC13892_SW4: + reg = REG_SW_3; + break; + default: + return -EINVAL; + } + + CHECK_ERROR(pmic_read_reg(reg, ®ister_val, PMIC_ALL_BITS)); + return (register_val & 0x800000) >> SWXHI_LSH; +} + +static int mc13892_get_voltage_value(int *hi, int mV) +{ + int voltage; + + if (mV < 600) + mV = 600; + if (mV > 1850) + mV = 1850; + + if (mV > 1375) + *hi = 1; + if (mV < 1100) + *hi = 0; + + if (*hi == 0) + voltage = (mV - 600) / 25; + else + voltage = (mV - 1100) / 25; + + return voltage; +} + +static int mc13892_get_voltage_mV(int hi, int voltage) +{ + int mV; + + if (hi == 0) + mV = voltage * 25 + 600; + else + mV = voltage * 25 + 1100; + + return mV; +} + +static int mc13892_sw_set_voltage(struct regulator_dev *reg, int MiniV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage; + int sw = rdev_get_id(reg); + int mV = uV / 1000; + int hi; + + hi = mc13892_get_sw_hi_bit(sw); + voltage = mc13892_get_voltage_value(&hi, mV); + + switch (sw) { + case MC13892_SW1: + register1 = REG_SW_0; + register_val = BITFVAL(SW1, voltage); + register_mask = BITFMASK(SW1); + break; + case MC13892_SW2: + register1 = REG_SW_1; + register_val = BITFVAL(SW2, voltage); + register_mask = BITFMASK(SW2); + break; + case MC13892_SW3: + register1 = REG_SW_2; + register_val = BITFVAL(SW3, voltage); + register_mask = BITFMASK(SW3); + break; + case MC13892_SW4: + register1 = REG_SW_3; + register_val = BITFVAL(SW4, voltage); + register_mask = BITFMASK(SW4); + break; + default: + return -EINVAL; + } + + register_val |= (hi << SWXHI_LSH); + register_mask |= (1 << SWXHI_LSH); + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_sw_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0; + int mV = 0; + int sw = rdev_get_id(reg); + int hi; + + switch (sw) { + case MC13892_SW1: + CHECK_ERROR(pmic_read_reg(REG_SW_0, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW1); + break; + case MC13892_SW2: + CHECK_ERROR(pmic_read_reg(REG_SW_1, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW2); + break; + case MC13892_SW3: + CHECK_ERROR(pmic_read_reg(REG_SW_2, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW3); + break; + case MC13892_SW4: + CHECK_ERROR(pmic_read_reg(REG_SW_3, + ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, SW4); + break; + default: + return -EINVAL; + } + + hi = mc13892_get_sw_hi_bit(sw); + mV = mc13892_get_voltage_mV(hi, voltage); + + return mV * 1000; +} + +static int mc13892_sw_stby_enable(struct regulator_dev *reg) +{ + return 0; +} + +static int mc13892_sw_stby_disable(struct regulator_dev *reg) +{ + return 0; +} + +static int mc13892_sw_stby_set_mode(struct regulator_dev *reg, unsigned int mode) +{ + return 0; +} + +static int mc13892_sw_stby_set_voltage(struct regulator_dev *reg, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1 = 0; + int voltage, mV = uV / 1000, hi; + int sw = rdev_get_id(reg); + + hi = mc13892_get_sw_hi_bit(sw); + voltage = mc13892_get_voltage_value(&hi, mV); + + switch (sw) { + case MC13892_SW1: + register1 = REG_SW_0; + register_val = BITFVAL(SW1_STDBY, voltage); + register_mask = BITFMASK(SW1_STDBY); + break; + case MC13892_SW2: + register1 = REG_SW_1; + register_val = BITFVAL(SW2_STDBY, voltage); + register_mask = BITFMASK(SW2_STDBY); + break; + case MC13892_SW3: + register1 = REG_SW_2; + register_val = BITFVAL(SW3_STDBY, voltage); + register_mask = BITFMASK(SW3_STDBY); + break; + case MC13892_SW4: + register1 = REG_SW_3; + register_val = BITFVAL(SW4_STDBY, voltage); + register_mask = BITFMASK(SW4_STDBY); + break; + default: + return -EINVAL; + } + + register_val |= (hi << SWXHI_LSH); + register_mask |= (1 << SWXHI_LSH); + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_swbst_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(SWBST_EN, SWBST_EN_ENABLE); + register_mask = BITFMASK(SWBST_EN); + register1 = REG_SW_5; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_swbst_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(SWBST_EN, SWBST_EN_DISABLE); + register_mask = BITFMASK(SWBST_EN); + register1 = REG_SW_5; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_viohi_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOHI_EN, VIOHI_EN_ENABLE); + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_viohi_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VIOHI_EN, VIOHI_EN_DISABLE); + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vusb_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VUSB_EN, VUSB_EN_ENABLE); + register_mask = BITFMASK(VUSB_EN); + register1 = REG_USB1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vusb_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VUSB_EN, VUSB_EN_DISABLE); + register_mask = BITFMASK(VUSB_EN); + register1 = REG_USB1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vdig_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1050) && (mV < 1250)) + voltage = VDIG_1_05V; + else if ((mV >= 1250) && (mV < 1650)) + voltage = VDIG_1_25V; + else if ((mV >= 1650) && (mV < 1800)) + voltage = VDIG_1_65V; + else + voltage = VDIG_1_80V; + + register_val = BITFVAL(VDIG, voltage); + register_mask = BITFMASK(VDIG); + register1 = REG_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vdig_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VDIG); + + switch (voltage) { + case VDIG_1_05V: + mV = 1050; + break; + case VDIG_1_25V: + mV = 1250; + break; + case VDIG_1_65V: + mV = 1650; + break; + case VDIG_1_80V: + mV = 1800; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vdig_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VDIG_EN, VDIG_EN_ENABLE); + register_mask = BITFMASK(VDIG_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vdig_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VDIG_EN, VDIG_EN_DISABLE); + register_mask = BITFMASK(VDIG_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vpll_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1050) && (mV < 1250)) + voltage = VPLL_1_05V; + else if ((mV >= 1250) && (mV < 1650)) + voltage = VPLL_1_25V; + else if ((mV >= 1650) && (mV < 1800)) + voltage = VPLL_1_65V; + else + voltage = VPLL_1_80V; + + register_val = BITFVAL(VPLL, voltage); + register_mask = BITFMASK(VPLL); + register1 = REG_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vpll_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VPLL); + + switch (voltage) { + case VPLL_1_05V: + mV = 1050; + break; + case VPLL_1_25V: + mV = 1250; + break; + case VPLL_1_65V: + mV = 1650; + break; + case VPLL_1_80V: + mV = 1800; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vpll_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VPLL_EN, VPLL_EN_ENABLE); + register_mask = BITFMASK(VPLL_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vpll_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VPLL_EN, VPLL_EN_DISABLE); + register_mask = BITFMASK(VPLL_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vaudio_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2300) && (mV < 2500)) + voltage = VAUDIO_2_3V; + else if ((mV >= 2500) && (mV < 2775)) + voltage = VAUDIO_2_5V; + else if ((mV >= 2775) && (mV < 3000)) + voltage = VAUDIO_2_775V; + else + voltage = VAUDIO_3V; + + register_val = BITFVAL(VAUDIO, voltage); + register_mask = BITFMASK(VAUDIO); + register1 = REG_SETTING_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vaudio_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_1, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VAUDIO); + + switch (voltage) { + case VAUDIO_2_3V: + mV = 2300; + break; + case VAUDIO_2_5V: + mV = 2500; + break; + case VAUDIO_2_775V: + mV = 2775; + break; + case VAUDIO_3V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vaudio_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_ENABLE); + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vaudio_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VAUDIO_EN, VAUDIO_EN_DISABLE); + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vusb2_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2400) && (mV < 2600)) + voltage = VUSB2_2_4V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VUSB2_2_6V; + else if ((mV >= 2700) && (mV < 2775)) + voltage = VUSB2_2_7V; + else + voltage = VUSB2_2_775V; + + register_val = BITFVAL(VUSB2, voltage); + register_mask = BITFMASK(VUSB2); + register1 = REG_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vusb2_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VUSB2); + + switch (voltage) { + case VUSB2_2_4V: + mV = 2400; + break; + case VUSB2_2_6V: + mV = 2600; + break; + case VUSB2_2_7V: + mV = 2700; + break; + case VUSB2_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vusb2_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VUSB2_EN, VUSB2_EN_ENABLE); + register_mask = BITFMASK(VUSB2_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vusb2_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VUSB2_EN, VUSB2_EN_DISABLE); + register_mask = BITFMASK(VUSB2_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vvideo_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2500) && (mV < 2600)) + voltage = VVIDEO_2_5V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VVIDEO_2_6V; + else if ((mV >= 2700) && (mV < 2775)) + voltage = VVIDEO_2_7V; + else + voltage = VVIDEO_2_775V; + + register_val = BITFVAL(VVIDEO, voltage); + register_mask = BITFMASK(VVIDEO); + register1 = REG_SETTING_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vvideo_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_1, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VVIDEO); + + switch (voltage) { + case VVIDEO_2_5V: + mV = 2500; + break; + case VVIDEO_2_6V: + mV = 2600; + break; + case VVIDEO_2_7V: + mV = 2700; + break; + case VVIDEO_2_775V: + mV = 2775; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vvideo_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VVIDEO_EN, VVIDEO_EN_ENABLE); + register_mask = BITFMASK(VVIDEO_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vvideo_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VVIDEO_EN, VVIDEO_EN_DISABLE); + register_mask = BITFMASK(VVIDEO_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vsd_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1800) && (mV < 2000)) + voltage = VSD_1_8V; + else if ((mV >= 2000) && (mV < 2600)) + voltage = VSD_2_0V; + else if ((mV >= 2600) && (mV < 2700)) + voltage = VSD_2_6V; + else if ((mV >= 2700) && (mV < 2800)) + voltage = VSD_2_7V; + else if ((mV >= 2800) && (mV < 2900)) + voltage = VSD_2_8V; + else if ((mV >= 2900) && (mV < 3000)) + voltage = VSD_2_9V; + else if ((mV >= 3000) && (mV < 3150)) + voltage = VSD_3_0V; + else + voltage = VSD_3_15V; + + register_val = BITFVAL(VSD, voltage); + register_mask = BITFMASK(VSD); + register1 = REG_SETTING_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vsd_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_1, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VSD); + + switch (voltage) { + case VSD_1_8V: + mV = 1800; + break; + case VSD_2_0V: + mV = 2000; + break; + case VSD_2_6V: + mV = 2600; + break; + case VSD_2_7V: + mV = 2700; + break; + case VSD_2_8V: + mV = 2800; + break; + case VSD_2_9V: + mV = 2900; + break; + case VSD_3_0V: + mV = 3000; + break; + case VSD_3_15V: + mV = 3150; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vsd_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VSD_EN, VSD_EN_ENABLE); + register_mask = BITFMASK(VSD_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vsd_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VSD_EN, VSD_EN_DISABLE); + register_mask = BITFMASK(VSD_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vcam_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 2500) && (mV < 2600)) + voltage = VCAM_2_5V; + else if ((mV >= 2600) && (mV < 2750)) + voltage = VCAM_2_6V; + else if ((mV >= 2750) && (mV < 3000)) + voltage = VCAM_2_75V; + else + voltage = VCAM_3_0V; + + register_val = BITFVAL(VCAM, voltage); + register_mask = BITFMASK(VCAM); + register1 = REG_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vcam_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VCAM); + + switch (voltage) { + case VCAM_2_5V: + mV = 2500; + break; + case VCAM_2_6V: + mV = 2600; + break; + case VCAM_2_75V: + mV = 2750; + break; + case VCAM_3_0V: + mV = 3000; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vcam_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VCAM_EN, VCAM_EN_ENABLE); + register_mask = BITFMASK(VCAM_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vcam_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VCAM_EN, VCAM_EN_DISABLE); + register_mask = BITFMASK(VCAM_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vcam_set_mode(struct regulator_dev *reg, unsigned int mode) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + switch (mode) { + case REGULATOR_MODE_FAST: + register_val = BITFVAL(VCAM_CONFIG, VCAM_CONFIG_EXT); + break; + case REGULATOR_MODE_NORMAL: + register_val = BITFVAL(VCAM_CONFIG, VCAM_CONFIG_INT); + break; + default: + return -EINVAL; + } + register_mask = BITFMASK(VCAM_CONFIG); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +unsigned int mc13892_vcam_get_mode(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int config = 0, mode = VCAM_CONFIG_INT; + + CHECK_ERROR(pmic_read_reg(REG_MODE_1, ®ister_val, PMIC_ALL_BITS)); + config = BITFEXT(register_val, VCAM_CONFIG); + + switch (config) { + case VCAM_CONFIG_EXT: + mode = REGULATOR_MODE_FAST; + break; + case VCAM_CONFIG_INT: + mode = REGULATOR_MODE_NORMAL; + break; + default: + return -EINVAL; + } + return mode; +} + +static int mc13892_vgen1_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1500)) + voltage = VGEN1_1_2V; + else if ((mV >= 1500) && (mV < 2775)) + voltage = VGEN1_1_5V; + else if ((mV >= 2775) && (mV < 3150)) + voltage = VGEN1_2_775V; + else + voltage = VGEN1_3_15V; + + register_val = BITFVAL(VGEN1, voltage); + register_mask = BITFMASK(VGEN1); + register1 = REG_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vgen1_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VGEN1); + + switch (voltage) { + case VGEN1_1_2V: + mV = 1200; + break; + case VGEN1_1_5V: + mV = 1500; + break; + case VGEN1_2_775V: + mV = 2775; + break; + case VGEN1_3_15V: + mV = 3150; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vgen1_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN1_EN, VGEN1_EN_ENABLE); + register_mask = BITFMASK(VGEN1_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vgen1_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN1_EN, VGEN1_EN_DISABLE); + register_mask = BITFMASK(VGEN1_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vgen2_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1200) && (mV < 1500)) + voltage = VGEN2_1_2V; + else if ((mV >= 1500) && (mV < 1600)) + voltage = VGEN2_1_5V; + else if ((mV >= 1600) && (mV < 1800)) + voltage = VGEN2_1_6V; + else if ((mV >= 1800) && (mV < 2700)) + voltage = VGEN2_1_8V; + else if ((mV >= 2700) && (mV < 2800)) + voltage = VGEN2_2_7V; + else if ((mV >= 2800) && (mV < 3000)) + voltage = VGEN2_2_8V; + else if ((mV >= 3000) && (mV < 3150)) + voltage = VGEN2_3_0V; + else + voltage = VGEN2_3_15V; + + register_val = BITFVAL(VGEN2, voltage); + register_mask = BITFMASK(VGEN2); + register1 = REG_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vgen2_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VGEN2); + + switch (voltage) { + case VGEN2_1_2V: + mV = 1200; + break; + case VGEN2_1_5V: + mV = 1500; + break; + case VGEN2_1_6V: + mV = 1600; + break; + case VGEN2_1_8V: + mV = 1800; + break; + case VGEN2_2_7V: + mV = 2700; + break; + case VGEN2_2_8V: + mV = 2800; + break; + case VGEN2_3_0V: + mV = 3000; + break; + case VGEN2_3_15V: + mV = 3150; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vgen2_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN2_EN, VGEN2_EN_ENABLE); + register_mask = BITFMASK(VGEN2_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vgen2_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN2_EN, VGEN2_EN_DISABLE); + register_mask = BITFMASK(VGEN2_EN); + register1 = REG_MODE_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vgen3_set_voltage(struct regulator_dev *reg, + int minuV, int uV) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int voltage, mV = uV / 1000; + + if ((mV >= 1800) && (mV < 2900)) + voltage = VGEN3_1_8V; + else + voltage = VGEN3_2_9V; + + register_val = BITFVAL(VGEN3, voltage); + register_mask = BITFMASK(VGEN3); + register1 = REG_SETTING_0; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vgen3_get_voltage(struct regulator_dev *reg) +{ + unsigned int register_val = 0; + int voltage = 0, mV = 0; + + CHECK_ERROR(pmic_read_reg(REG_SETTING_0, ®ister_val, PMIC_ALL_BITS)); + voltage = BITFEXT(register_val, VGEN3); + + switch (voltage) { + case VGEN3_1_8V: + mV = 1800; + break; + case VGEN3_2_9V: + mV = 2900; + break; + default: + return -EINVAL; + } + + return mV * 1000; +} + +static int mc13892_vgen3_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN3_EN, VGEN3_EN_ENABLE); + register_mask = BITFMASK(VGEN3_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_vgen3_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + + register_val = BITFVAL(VGEN3_EN, VGEN3_EN_DISABLE); + register_mask = BITFMASK(VGEN3_EN); + register1 = REG_MODE_1; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_gpo_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = rdev_get_id(reg); + + switch (gpo) { + case MC13892_GPO1: + register_val = BITFVAL(GPO1_EN, GPO1_EN_ENABLE); + register_mask = BITFMASK(GPO1_EN); + break; + case MC13892_GPO2: + register_val = BITFVAL(GPO2_EN, GPO2_EN_ENABLE); + register_mask = BITFMASK(GPO2_EN); + break; + case MC13892_GPO3: + register_val = BITFVAL(GPO3_EN, GPO3_EN_ENABLE); + register_mask = BITFMASK(GPO3_EN); + break; + case MC13892_GPO4: + register_val = BITFVAL(GPO4_EN, GPO4_EN_ENABLE) + + BITFVAL(GPO4_ADIN, GPO4_ADIN_DISABLE); + register_mask = BITFMASK(GPO4_EN) + BITFMASK(GPO4_ADIN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISC; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_gpo_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = rdev_get_id(reg); + + switch (gpo) { + case MC13892_GPO1: + register_val = BITFVAL(GPO1_EN, GPO1_EN_DISABLE); + register_mask = BITFMASK(GPO1_EN); + break; + case MC13892_GPO2: + register_val = BITFVAL(GPO2_EN, GPO2_EN_DISABLE); + register_mask = BITFMASK(GPO2_EN); + break; + case MC13892_GPO3: + register_val = BITFVAL(GPO3_EN, GPO3_EN_DISABLE); + register_mask = BITFMASK(GPO3_EN); + break; + case MC13892_GPO4: + register_val = BITFVAL(GPO4_EN, GPO4_EN_DISABLE); + register_mask = BITFMASK(GPO4_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISC; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_power_gating_enable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = rdev_get_id(reg); + + switch (gpo) { + case MC13892_PWGT1: + register_val = BITFVAL(PWGT1SPI_EN, PWGT1SPI_EN_ENABLE); + register_mask = BITFMASK(PWGT1SPI_EN); + break; + case MC13892_PWGT2: + register_val = BITFVAL(PWGT2SPI_EN, PWGT2SPI_EN_ENABLE); + register_mask = BITFMASK(PWGT2SPI_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISC; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_power_gating_disable(struct regulator_dev *reg) +{ + unsigned int register_val = 0, register_mask = 0; + unsigned int register1; + int gpo = rdev_get_id(reg); + + switch (gpo) { + case MC13892_PWGT1: + register_val = BITFVAL(PWGT1SPI_EN, PWGT1SPI_EN_DISABLE); + register_mask = BITFMASK(PWGT1SPI_EN); + break; + case MC13892_PWGT2: + register_val = BITFVAL(PWGT2SPI_EN, PWGT2SPI_EN_DISABLE); + register_mask = BITFMASK(PWGT2SPI_EN); + break; + default: + return -EINVAL; + }; + + register1 = REG_POWER_MISC; + + return pmic_write_reg(register1, register_val, register_mask); +} + +static int mc13892_regulator_is_enabled(struct regulator_dev *rdev) +{ + unsigned int register1; + unsigned int register_mask; + int id = rdev_get_id(rdev); + unsigned int register_val = 0; + + switch (id) { + case MC13892_SWBST: + register_mask = BITFMASK(SWBST_EN); + register1 = REG_SW_5; + break; + case MC13892_VIOHI: + register_mask = BITFMASK(VIOHI_EN); + register1 = REG_MODE_0; + break; + case MC13892_VPLL: + register_mask = BITFMASK(VPLL_EN); + register1 = REG_MODE_0; + break; + case MC13892_VDIG: + register_mask = BITFMASK(VDIG_EN); + register1 = REG_MODE_0; + break; + case MC13892_VSD: + register_mask = BITFMASK(VSD_EN); + register1 = REG_MODE_1; + break; + case MC13892_VUSB2: + register_mask = BITFMASK(VUSB2_EN); + register1 = REG_MODE_0; + break; + case MC13892_VVIDEO: + register_mask = BITFMASK(VVIDEO_EN); + register1 = REG_MODE_1; + break; + case MC13892_VAUDIO: + register_mask = BITFMASK(VAUDIO_EN); + register1 = REG_MODE_1; + break; + case MC13892_VCAM: + register_mask = BITFMASK(VCAM_EN); + register1 = REG_MODE_1; + break; + case MC13892_VGEN1: + register_mask = BITFMASK(VGEN1_EN); + register1 = REG_MODE_0; + break; + case MC13892_VGEN2: + register_mask = BITFMASK(VGEN2_EN); + register1 = REG_MODE_0; + break; + case MC13892_VGEN3: + register_mask = BITFMASK(VGEN3_EN); + register1 = REG_MODE_1; + break; + case MC13892_VUSB: + register_mask = BITFMASK(VUSB_EN); + register1 = REG_USB1; + break; + case MC13892_GPO1: + register_mask = BITFMASK(GPO1_EN); + register1 = REG_POWER_MISC; + break; + case MC13892_GPO2: + register_mask = BITFMASK(GPO2_EN); + register1 = REG_POWER_MISC; + break; + case MC13892_GPO3: + register_mask = BITFMASK(GPO3_EN); + register1 = REG_POWER_MISC; + break; + case MC13892_GPO4: + register_mask = BITFMASK(GPO4_EN); + register1 = REG_POWER_MISC; + break; + case MC13892_PWGT1: + register_mask = BITFMASK(PWGT1SPI_EN); + register1 = REG_POWER_MISC; + break; + case MC13892_PWGT2: + register_mask = BITFMASK(PWGT2SPI_EN); + register1 = REG_POWER_MISC; + break; + default: + return 1; + } + CHECK_ERROR(pmic_read_reg(register1, ®ister_val, register_mask)); + return (register_val != 0); +} + +static struct regulator_ops mc13892_sw_ops = { + .enable = mc13892_sw_stby_enable, + .disable = mc13892_sw_stby_disable, + .set_voltage = mc13892_sw_set_voltage, + .get_voltage = mc13892_sw_get_voltage, + .set_suspend_voltage = mc13892_sw_stby_set_voltage, + .set_suspend_enable = mc13892_sw_stby_enable, + .set_suspend_disable = mc13892_sw_stby_disable, + .set_suspend_mode = mc13892_sw_stby_set_mode, +}; + +static struct regulator_ops mc13892_swbst_ops = { + .enable = mc13892_swbst_enable, + .disable = mc13892_swbst_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_viohi_ops = { + .enable = mc13892_viohi_enable, + .disable = mc13892_viohi_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vusb_ops = { + .enable = mc13892_vusb_enable, + .disable = mc13892_vusb_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vdig_ops = { + .set_voltage = mc13892_vdig_set_voltage, + .get_voltage = mc13892_vdig_get_voltage, + .enable = mc13892_vdig_enable, + .disable = mc13892_vdig_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vpll_ops = { + .set_voltage = mc13892_vpll_set_voltage, + .get_voltage = mc13892_vpll_get_voltage, + .enable = mc13892_vpll_enable, + .disable = mc13892_vpll_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vusb2_ops = { + .set_voltage = mc13892_vusb2_set_voltage, + .get_voltage = mc13892_vusb2_get_voltage, + .enable = mc13892_vusb2_enable, + .disable = mc13892_vusb2_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vvideo_ops = { + .set_voltage = mc13892_vvideo_set_voltage, + .get_voltage = mc13892_vvideo_get_voltage, + .enable = mc13892_vvideo_enable, + .disable = mc13892_vvideo_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vaudio_ops = { + .set_voltage = mc13892_vaudio_set_voltage, + .get_voltage = mc13892_vaudio_get_voltage, + .enable = mc13892_vaudio_enable, + .disable = mc13892_vaudio_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vsd_ops = { + .set_voltage = mc13892_vsd_set_voltage, + .get_voltage = mc13892_vsd_get_voltage, + .enable = mc13892_vsd_enable, + .disable = mc13892_vsd_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vcam_ops = { + .set_voltage = mc13892_vcam_set_voltage, + .get_voltage = mc13892_vcam_get_voltage, + .enable = mc13892_vcam_enable, + .disable = mc13892_vcam_disable, + .is_enabled = mc13892_regulator_is_enabled, + .set_mode = mc13892_vcam_set_mode, + .get_mode = mc13892_vcam_get_mode, +}; + +static struct regulator_ops mc13892_vgen1_ops = { + .set_voltage = mc13892_vgen1_set_voltage, + .get_voltage = mc13892_vgen1_get_voltage, + .enable = mc13892_vgen1_enable, + .disable = mc13892_vgen1_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vgen2_ops = { + .set_voltage = mc13892_vgen2_set_voltage, + .get_voltage = mc13892_vgen2_get_voltage, + .enable = mc13892_vgen2_enable, + .disable = mc13892_vgen2_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_vgen3_ops = { + .set_voltage = mc13892_vgen3_set_voltage, + .get_voltage = mc13892_vgen3_get_voltage, + .enable = mc13892_vgen3_enable, + .disable = mc13892_vgen3_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_gpo_ops = { + .enable = mc13892_gpo_enable, + .disable = mc13892_gpo_disable, + .is_enabled = mc13892_regulator_is_enabled, +}; + +static struct regulator_ops mc13892_power_gating_ops = { + .enable = mc13892_power_gating_enable, + .disable = mc13892_power_gating_disable, + .is_enabled = mc13892_regulator_is_enabled, + +}; + +static struct regulator_desc mc13892_reg[] = { + { + .name = "SW1", + .id = MC13892_SW1, + .ops = &mc13892_sw_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SW2", + .id = MC13892_SW2, + .ops = &mc13892_sw_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SW3", + .id = MC13892_SW3, + .ops = &mc13892_sw_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SW4", + .id = MC13892_SW4, + .ops = &mc13892_sw_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SWBST", + .id = MC13892_SWBST, + .ops = &mc13892_swbst_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VIOHI", + .id = MC13892_VIOHI, + .ops = &mc13892_viohi_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VPLL", + .id = MC13892_VPLL, + .ops = &mc13892_vpll_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VDIG", + .id = MC13892_VDIG, + .ops = &mc13892_vdig_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VSD", + .id = MC13892_VSD, + .ops = &mc13892_vsd_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VUSB2", + .id = MC13892_VUSB2, + .ops = &mc13892_vusb2_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VVIDEO", + .id = MC13892_VVIDEO, + .ops = &mc13892_vvideo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VAUDIO", + .id = MC13892_VAUDIO, + .ops = &mc13892_vaudio_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VCAM", + .id = MC13892_VCAM, + .ops = &mc13892_vcam_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VGEN1", + .id = MC13892_VGEN1, + .ops = &mc13892_vgen1_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VGEN2", + .id = MC13892_VGEN2, + .ops = &mc13892_vgen2_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VGEN3", + .id = MC13892_VGEN3, + .ops = &mc13892_vgen3_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "VUSB", + .id = MC13892_VUSB, + .ops = &mc13892_vusb_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPO1", + .id = MC13892_GPO1, + .ops = &mc13892_gpo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPO2", + .id = MC13892_GPO2, + .ops = &mc13892_gpo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPO3", + .id = MC13892_GPO3, + .ops = &mc13892_gpo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPO4", + .id = MC13892_GPO4, + .ops = &mc13892_gpo_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "PWGT1", + .id = MC13892_PWGT1, + .ops = &mc13892_power_gating_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "PWGT2", + .id = MC13892_PWGT2, + .ops = &mc13892_power_gating_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, +}; + +static int mc13892_regulator_probe(struct platform_device *pdev) +{ + struct regulator_dev *rdev; + + /* register regulator */ + rdev = regulator_register(&mc13892_reg[pdev->id], &pdev->dev, + pdev->dev.platform_data, + dev_get_drvdata(&pdev->dev)); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mc13892_reg[pdev->id].name); + return PTR_ERR(rdev); + } + + return 0; +} + + +static int mc13892_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + + regulator_unregister(rdev); + + return 0; +} + +int mc13892_register_regulator(struct mc13892 *mc13892, int reg, + struct regulator_init_data *initdata) +{ + struct platform_device *pdev; + int ret; + + if (mc13892->pmic.pdev[reg]) + return -EBUSY; + + pdev = platform_device_alloc("mc13892-regulatr", reg); + if (!pdev) + return -ENOMEM; + + mc13892->pmic.pdev[reg] = pdev; + + initdata->driver_data = mc13892; + + pdev->dev.platform_data = initdata; + pdev->dev.parent = mc13892->dev; + platform_set_drvdata(pdev, mc13892); + ret = platform_device_add(pdev); + + if (ret != 0) { + dev_err(mc13892->dev, "Failed to register regulator %d: %d\n", + reg, ret); + platform_device_del(pdev); + mc13892->pmic.pdev[reg] = NULL; + } + + return ret; +} +EXPORT_SYMBOL_GPL(mc13892_register_regulator); + +static struct platform_driver mc13892_regulator_driver = { + .probe = mc13892_regulator_probe, + .remove = mc13892_regulator_remove, + .driver = { + .name = "mc13892-regulatr", + }, +}; + +static int __init mc13892_regulator_init(void) +{ + return platform_driver_register(&mc13892_regulator_driver); +} +subsys_initcall(mc13892_regulator_init); + +static void __exit mc13892_regulator_exit(void) +{ + platform_driver_unregister(&mc13892_regulator_driver); +} +module_exit(mc13892_regulator_exit); + + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC13892 Regulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/reg-mc34704.c b/drivers/regulator/reg-mc34704.c new file mode 100644 index 000000000000..7fb3732b9e03 --- /dev/null +++ b/drivers/regulator/reg-mc34704.c @@ -0,0 +1,289 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MC34704_ONOFFA 0x8 +#define MC34704_ONOFFC 0x4 +#define MC34704_ONOFFD 0x2 +#define MC34704_ONOFFE 0x1 + +/* Private data for MC34704 regulators */ + +struct reg_mc34704_priv { + short enable; /* enable bit, if available */ + short v_default; /* default regulator voltage in mV */ + int dvs_min; /* minimum voltage change in units of 2.5% */ + int dvs_max; /* maximum voltage change in units of 2.5% */ + char i2c_dvs; /* i2c DVS register number */ + char i2c_stat; /* i2c status register number */ +}; +struct reg_mc34704_priv mc34704_reg_priv[] = { + { + .v_default = REG1_V_MV, + .dvs_min = REG1_DVS_MIN_PCT / 2.5, + .dvs_max = REG1_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0x4, + .i2c_stat = 0x5, + .enable = MC34704_ONOFFA, + }, + { + .v_default = REG2_V_MV, + .dvs_min = REG2_DVS_MIN_PCT / 2.5, + .dvs_max = REG2_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0x6, + .i2c_stat = 0x7, + }, + { + .v_default = REG3_V_MV, + .dvs_min = REG3_DVS_MIN_PCT / 2.5, + .dvs_max = REG3_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0x8, + .i2c_stat = 0x9, + }, + { + .v_default = REG4_V_MV, + .dvs_min = REG4_DVS_MIN_PCT / 2.5, + .dvs_max = REG4_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0xA, + .i2c_stat = 0xB, + }, + { + .v_default = REG5_V_MV, + .dvs_min = REG5_DVS_MIN_PCT / 2.5, + .dvs_max = REG5_DVS_MAX_PCT / 2.5, + .i2c_dvs = 0xC, + .i2c_stat = 0xE, + .enable = MC34704_ONOFFE, + }, +}; + +static int mc34704_set_voltage(struct regulator_dev *reg, int MiniV, int uV) +{ + struct reg_mc34704_priv *priv = rdev_get_drvdata(reg); + int mV = uV / 1000; + int dV = mV - priv->v_default; + + /* compute dynamic voltage scaling value */ + int dvs = 1000 * dV / priv->v_default / 25; + + /* clip to regulator limits */ + if (dvs > priv->dvs_max) + dvs = priv->dvs_max; + if (dvs < priv->dvs_min) + dvs = priv->dvs_min; + + return pmic_write_reg(priv->i2c_dvs, dvs << 1, 0x1E); +} + +static int mc34704_get_voltage(struct regulator_dev *reg) +{ + int mV; + struct reg_mc34704_priv *priv = rdev_get_drvdata(reg); + int val, dvs; + + CHECK_ERROR(pmic_read_reg(priv->i2c_dvs, &val, 0xF)); + + dvs = (val >> 1) & 0xF; + + /* dvs is 4-bit 2's complement; sign-extend it */ + if (dvs & 8) + dvs |= -1 & ~0xF; + + /* Regulator voltage is adjusted by (dvs * 2.5%) */ + mV = priv->v_default * (1000 + 25 * dvs) / 1000; + + return 1000 * mV; +} + +static int mc34704_enable_reg(struct regulator_dev *reg) +{ + struct reg_mc34704_priv *priv = rdev_get_drvdata(reg); + + if (priv->enable) + return pmic_write_reg(REG_MC34704_GENERAL2, -1, priv->enable); + + return PMIC_ERROR; +} + +static int mc34704_disable_reg(struct regulator_dev *reg) +{ + struct reg_mc34704_priv *priv = rdev_get_drvdata(reg); + + if (priv->enable) + return pmic_write_reg(REG_MC34704_GENERAL2, 0, priv->enable); + + return PMIC_ERROR; +} + +static int mc34704_is_reg_enabled(struct regulator_dev *reg) +{ + struct reg_mc34704_priv *priv = rdev_get_drvdata(reg); + int val; + + if (priv->enable) { + CHECK_ERROR(pmic_read_reg(REG_MC34704_GENERAL2, &val, + priv->enable)); + return val ? 1 : 0; + } else { + return PMIC_ERROR; + } +} + +static struct regulator_ops mc34704_full_ops = { + .set_voltage = mc34704_set_voltage, + .get_voltage = mc34704_get_voltage, + .enable = mc34704_enable_reg, + .disable = mc34704_disable_reg, + .is_enabled = mc34704_is_reg_enabled, +}; + +static struct regulator_ops mc34704_partial_ops = { + .set_voltage = mc34704_set_voltage, + .get_voltage = mc34704_get_voltage, +}; + +static struct regulator_desc reg_mc34704[] = { + { + .name = "REG1_BKLT", + .id = MC34704_BKLT, + .ops = &mc34704_full_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE}, + { + .name = "REG2_CPU", + .id = MC34704_CPU, + .ops = &mc34704_partial_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE}, + { + .name = "REG3_CORE", + .id = MC34704_CORE, + .ops = &mc34704_partial_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE}, + { + .name = "REG4_DDR", + .id = MC34704_DDR, + .ops = &mc34704_partial_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE}, + { + .name = "REG5_PERS", + .id = MC34704_PERS, + .ops = &mc34704_full_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE}, +}; + +static int mc34704_regulator_probe(struct platform_device *pdev) +{ + struct regulator_dev *rdev; + + /* register regulator */ + rdev = regulator_register(®_mc34704[pdev->id], &pdev->dev, + pdev->dev.platform_data, + (void *)&mc34704_reg_priv[pdev->id]); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + reg_mc34704[pdev->id].name); + return PTR_ERR(rdev); + } + + return 0; +} + +static int mc34704_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + + regulator_unregister(rdev); + + return 0; +} + +int mc34704_register_regulator(struct mc34704 *mc34704, int reg, + struct regulator_init_data *initdata) +{ + struct platform_device *pdev; + int ret; + + if (mc34704->pmic.pdev[reg]) + return -EBUSY; + + pdev = platform_device_alloc("mc34704-regulatr", reg); + if (!pdev) + return -ENOMEM; + + mc34704->pmic.pdev[reg] = pdev; + + initdata->driver_data = mc34704; + + pdev->dev.platform_data = initdata; + + pdev->dev.parent = mc34704->dev; + platform_set_drvdata(pdev, mc34704); + ret = platform_device_add(pdev); + + if (ret != 0) { + dev_err(mc34704->dev, "Failed to register regulator %d: %d\n", + reg, ret); + platform_device_del(pdev); + mc34704->pmic.pdev[reg] = NULL; + } + + return ret; +} +EXPORT_SYMBOL_GPL(mc34704_register_regulator); + +static struct platform_driver mc34704_regulator_driver = { + .probe = mc34704_regulator_probe, + .remove = mc34704_regulator_remove, + .driver = { + .name = "mc34704-regulatr", + }, +}; + +static int __init mc34704_regulator_init(void) +{ + return platform_driver_register(&mc34704_regulator_driver); +} +subsys_initcall(mc34704_regulator_init); + +static void __exit mc34704_regulator_exit(void) +{ + platform_driver_unregister(&mc34704_regulator_driver); +} +module_exit(mc34704_regulator_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC34704 Regulator Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/reg-mc9s08dz60.c b/drivers/regulator/reg-mc9s08dz60.c new file mode 100644 index 000000000000..f2748e99fd80 --- /dev/null +++ b/drivers/regulator/reg-mc9s08dz60.c @@ -0,0 +1,236 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* lcd */ +static int mc9s08dz60_lcd_enable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 6, 1); +} + +static int mc9s08dz60_lcd_disable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 6, 0); +} + +static struct regulator_ops mc9s08dz60_lcd_ops = { + .enable = mc9s08dz60_lcd_enable, + .disable = mc9s08dz60_lcd_disable, +}; + +/* wifi */ +static int mc9s08dz60_wifi_enable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 1); +} + +static int mc9s08dz60_wifi_disable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 5, 0); +} + +static struct regulator_ops mc9s08dz60_wifi_ops = { + .enable = mc9s08dz60_wifi_enable, + .disable = mc9s08dz60_wifi_disable, +}; + +/* hdd */ +static int mc9s08dz60_hdd_enable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 1); +} + +static int mc9s08dz60_hdd_disable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 4, 0); +} + +static struct regulator_ops mc9s08dz60_hdd_ops = { + .enable = mc9s08dz60_hdd_enable, + .disable = mc9s08dz60_hdd_disable, +}; + +/* gps */ +static int mc9s08dz60_gps_enable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 1); +} + +static int mc9s08dz60_gps_disable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 0, 0); +} + +static struct regulator_ops mc9s08dz60_gps_ops = { + .enable = mc9s08dz60_gps_enable, + .disable = mc9s08dz60_gps_disable, +}; + +/* speaker */ +static int mc9s08dz60_speaker_enable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 0, 1); +} + +static int mc9s08dz60_speaker_disable(struct regulator_dev *reg) +{ + return pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 0, 0); +} + +static struct regulator_ops mc9s08dz60_speaker_ops = { + .enable = mc9s08dz60_speaker_enable, + .disable = mc9s08dz60_speaker_disable, +}; + +static struct regulator_desc mc9s08dz60_reg[] = { + { + .name = "LCD", + .id = MC9S08DZ60_LCD, + .ops = &mc9s08dz60_lcd_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "WIFI", + .id = MC9S08DZ60_WIFI, + .ops = &mc9s08dz60_wifi_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "HDD", + .id = MC9S08DZ60_HDD, + .ops = &mc9s08dz60_hdd_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "GPS", + .id = MC9S08DZ60_GPS, + .ops = &mc9s08dz60_gps_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + { + .name = "SPKR", + .id = MC9S08DZ60_SPKR, + .ops = &mc9s08dz60_speaker_ops, + .irq = 0, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE + }, + +}; + +static int mc9s08dz60_regulator_probe(struct platform_device *pdev) +{ + struct regulator_dev *rdev; + + /* register regulator */ + rdev = regulator_register(&mc9s08dz60_reg[pdev->id], &pdev->dev, + pdev->dev.platform_data, + dev_get_drvdata(&pdev->dev)); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mc9s08dz60_reg[pdev->id].name); + return PTR_ERR(rdev); + } + + return 0; +} + + +static int mc9s08dz60_regulator_remove(struct platform_device *pdev) +{ + struct regulator_dev *rdev = platform_get_drvdata(pdev); + + regulator_unregister(rdev); + + return 0; +} + +int mc9s08dz60_register_regulator(struct mc9s08dz60 *mc9s08dz60, int reg, + struct regulator_init_data *initdata) +{ + struct platform_device *pdev; + int ret; + + if (mc9s08dz60->pmic.pdev[reg]) + return -EBUSY; + + pdev = platform_device_alloc("mc9s08dz60-regu", reg); + if (!pdev) + return -ENOMEM; + + mc9s08dz60->pmic.pdev[reg] = pdev; + + initdata->driver_data = mc9s08dz60; + + pdev->dev.platform_data = initdata; + pdev->dev.parent = mc9s08dz60->dev; + platform_set_drvdata(pdev, mc9s08dz60); + ret = platform_device_add(pdev); + + if (ret != 0) { + dev_err(mc9s08dz60->dev, + "Failed to register regulator %d: %d\n", + reg, ret); + platform_device_del(pdev); + mc9s08dz60->pmic.pdev[reg] = NULL; + } + + return ret; +} +EXPORT_SYMBOL_GPL(mc9s08dz60_register_regulator); + +static struct platform_driver mc9s08dz60_regulator_driver = { + .probe = mc9s08dz60_regulator_probe, + .remove = mc9s08dz60_regulator_remove, + .driver = { + .name = "mc9s08dz60-regu", + }, +}; + +static int __init mc9s08dz60_regulator_init(void) +{ + return platform_driver_register(&mc9s08dz60_regulator_driver); +} +subsys_initcall(mc9s08dz60_regulator_init); + +static void __exit mc9s08dz60_regulator_exit(void) +{ + platform_driver_unregister(&mc9s08dz60_regulator_driver); +} +module_exit(mc9s08dz60_regulator_exit); + + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC9S08DZ60 Regulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 10ba12c8c5e0..9987e3765989 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -433,6 +433,14 @@ config RTC_DRV_CMOS This driver can also be built as a module. If so, the module will be called rtc-cmos. +config RTC_DRV_DA9052 + tristate "Dialog DA9052 RTC" + depends on PMIC_DA9052 + help + Say y here to support the RTC found on + Dialog Semiconductor DA9052 PMIC. + + config RTC_DRV_DS1216 tristate "Dallas DS1216" depends on SNI_RM @@ -818,6 +826,52 @@ config RTC_DRV_PXA This RTC driver uses PXA RTC registers available since pxa27x series (RDxR, RYxR) instead of legacy RCNR, RTAR. +config RTC_MXC + tristate "Freescale MXC Real Time Clock" + depends on ARCH_MXC + depends on RTC_CLASS + help + Support for Freescale RTC MXC + +config RTC_DRV_MXC_V2 + tristate "Freescale MXC Secure Real Time Clock" + depends on ARCH_MXC + depends on RTC_CLASS + help + Support for Freescale SRTC MXC + +config RTC_DRV_IMXDI + tristate "Freescale IMX DryIce Real Time Clock" + depends on ARCH_MXC + depends on RTC_CLASS + help + Support for Freescale IMX DryIce RTC + +config RTC_MC13892 + tristate "Freescale MC13892 Real Time Clock" + depends on ARCH_MXC && MXC_PMIC_MC13892 + depends on RTC_CLASS + help + Support for Freescale MC13892 RTC + +config RTC_DRV_STMP3XXX + tristate "Sigmatel STMP3xxx series SoC RTC" + depends on ARCH_STMP3XXX && RTC_CLASS + help + Say Y here to get support for the real-time clock peripheral + on Sigmatel STMP3xxx series SoCs (tested on STMP3700). + + This driver can also be build as a module. If so, the module + will be called rtc-stmp3xxx. + +config RTC_DRV_MXS + tristate "Freescale MXS series SoC RTC" + depends on ARCH_MXS && RTC_CLASS + help + Say Y here to get support for the real-time clock peripheral + on Freescale MXS series SoCs + This driver can also be build as a module. If so, the module + will be called rtc-mxs. config RTC_DRV_SUN4V bool "SUN4V Hypervisor RTC" diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 5adbba7cf89c..e58c0868eb7e 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -94,3 +94,10 @@ obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o +obj-$(CONFIG_RTC_MXC) += rtc-mxc.o +obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o +obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o +obj-$(CONFIG_RTC_MC13892) += rtc-mc13892.o +obj-$(CONFIG_RTC_DRV_MXS) += rtc-mxs.o +obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o + diff --git a/drivers/rtc/rtc-da9052.c b/drivers/rtc/rtc-da9052.c new file mode 100644 index 000000000000..8f4d26fbc23b --- /dev/null +++ b/drivers/rtc/rtc-da9052.c @@ -0,0 +1,694 @@ +/* + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * rtc-da9052.c: RTC driver for DA9052 + */ + +#include +#include +#include +#include +#include + +#define DRIVER_NAME "da9052-rtc" +#define ENABLE 1 +#define DISABLE 0 + +struct da9052_rtc { + struct rtc_device *rtc; + struct da9052 *da9052; + struct da9052_eh_nb eh_data; + unsigned char is_min_alarm; + unsigned char enable_tick_alarm; + unsigned char enable_clk_buffer; + unsigned char set_osc_trim_freq; +}; + +static int da9052_rtc_enable_alarm(struct da9052 *da9052, unsigned char flag); + +void da9052_rtc_notifier(struct da9052_eh_nb *eh_data, unsigned int event) +{ + struct da9052_rtc *rtc = + container_of(eh_data, struct da9052_rtc, eh_data); + struct da9052_ssc_msg msg; + unsigned int ret; + + /* Check the alarm type - TIMER or TICK */ + msg.addr = DA9052_ALARMMI_REG; + + da9052_lock(rtc->da9052); + ret = rtc->da9052->read(rtc->da9052, &msg); + if (ret != 0) { + da9052_unlock(rtc->da9052); + return; + } + + da9052_unlock(rtc->da9052); + + + if (msg.data & DA9052_ALARMMI_ALARMTYPE) { + da9052_rtc_enable_alarm(rtc->da9052, 0); + printk(KERN_INFO "RTC: TIMER ALARM\n"); + } else { + kobject_uevent(&rtc->rtc->dev.kobj, KOBJ_CHANGE); + printk(KERN_INFO "RTC: TICK ALARM\n"); + } +} + +static int da9052_rtc_validate_parameters(struct rtc_time *rtc_tm) +{ + + if (rtc_tm->tm_sec > DA9052_RTC_SECONDS_LIMIT) + return DA9052_RTC_INVALID_SECONDS; + + if (rtc_tm->tm_min > DA9052_RTC_MINUTES_LIMIT) + return DA9052_RTC_INVALID_MINUTES; + + if (rtc_tm->tm_hour > DA9052_RTC_HOURS_LIMIT) + return DA9052_RTC_INVALID_HOURS; + + if (rtc_tm->tm_mday == 0) + return DA9052_RTC_INVALID_DAYS; + + if ((rtc_tm->tm_mon > DA9052_RTC_MONTHS_LIMIT) || + (rtc_tm->tm_mon == 0)) + return DA9052_RTC_INVALID_MONTHS; + + if (rtc_tm->tm_year > DA9052_RTC_YEARS_LIMIT) + return DA9052_RTC_INVALID_YEARS; + + if ((rtc_tm->tm_mon == FEBRUARY)) { + if (((rtc_tm->tm_year % 4 == 0) && + (rtc_tm->tm_year % 100 != 0)) || + (rtc_tm->tm_year % 400 == 0)) { + if (rtc_tm->tm_mday > 29) + return DA9052_RTC_INVALID_DAYS; + } else if (rtc_tm->tm_mday > 28) { + return DA9052_RTC_INVALID_DAYS; + } + } + + if (((rtc_tm->tm_mon == APRIL) || (rtc_tm->tm_mon == JUNE) || + (rtc_tm->tm_mon == SEPTEMBER) || (rtc_tm->tm_mon == NOVEMBER)) + && (rtc_tm->tm_mday == 31)) { + return DA9052_RTC_INVALID_DAYS; + } + + + return 0; +} + +static int da9052_rtc_settime(struct da9052 *da9052, struct rtc_time *rtc_tm) +{ + + struct da9052_ssc_msg msg_arr[6]; + int validate_param = 0; + unsigned char loop_index = 0; + int ret = 0; + + + /* System compatability */ + rtc_tm->tm_year -= 100; + rtc_tm->tm_mon += 1; + + validate_param = da9052_rtc_validate_parameters(rtc_tm); + if (validate_param) + return validate_param; + + msg_arr[loop_index].addr = DA9052_COUNTS_REG; + msg_arr[loop_index++].data = DA9052_COUNTS_MONITOR | rtc_tm->tm_sec; + + msg_arr[loop_index].addr = DA9052_COUNTMI_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = rtc_tm->tm_min; + + msg_arr[loop_index].addr = DA9052_COUNTH_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = rtc_tm->tm_hour; + + msg_arr[loop_index].addr = DA9052_COUNTD_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = rtc_tm->tm_mday; + + msg_arr[loop_index].addr = DA9052_COUNTMO_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = rtc_tm->tm_mon; + + msg_arr[loop_index].addr = DA9052_COUNTY_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = rtc_tm->tm_year; + + da9052_lock(da9052); + ret = da9052->write_many(da9052, msg_arr, loop_index); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + da9052_unlock(da9052); + return 0; +} + +static int da9052_rtc_gettime(struct da9052 *da9052, struct rtc_time *rtc_tm) +{ + + struct da9052_ssc_msg msg[6]; + unsigned char loop_index = 0; + int validate_param = 0; + int ret = 0; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_COUNTS_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_COUNTMI_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_COUNTH_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_COUNTD_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_COUNTMO_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_COUNTY_REG; + + da9052_lock(da9052); + ret = da9052->read_many(da9052, msg, loop_index); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + da9052_unlock(da9052); + + rtc_tm->tm_year = msg[--loop_index].data & DA9052_COUNTY_COUNTYEAR; + rtc_tm->tm_mon = msg[--loop_index].data & DA9052_COUNTMO_COUNTMONTH; + rtc_tm->tm_mday = msg[--loop_index].data & DA9052_COUNTD_COUNTDAY; + rtc_tm->tm_hour = msg[--loop_index].data & DA9052_COUNTH_COUNTHOUR; + rtc_tm->tm_min = msg[--loop_index].data & DA9052_COUNTMI_COUNTMIN; + rtc_tm->tm_sec = msg[--loop_index].data & DA9052_COUNTS_COUNTSEC; + + validate_param = da9052_rtc_validate_parameters(rtc_tm); + if (validate_param) + return validate_param; + + /* System compatability */ + rtc_tm->tm_year += 100; + rtc_tm->tm_mon -= 1; + return 0; +} + +static int da9052_alarm_gettime(struct da9052 *da9052, struct rtc_time *rtc_tm) +{ + struct da9052_ssc_msg msg[5]; + unsigned char loop_index = 0; + int validate_param = 0; + int ret = 0; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_ALARMMI_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_ALARMH_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_ALARMD_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_ALARMMO_REG; + + msg[loop_index].data = 0; + msg[loop_index++].addr = DA9052_ALARMY_REG; + + da9052_lock(da9052); + ret = da9052->read_many(da9052, msg, loop_index); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + da9052_unlock(da9052); + + rtc_tm->tm_year = msg[--loop_index].data & DA9052_ALARMY_ALARMYEAR; + rtc_tm->tm_mon = msg[--loop_index].data & DA9052_ALARMMO_ALARMMONTH; + rtc_tm->tm_mday = msg[--loop_index].data & DA9052_ALARMD_ALARMDAY; + rtc_tm->tm_hour = msg[--loop_index].data & DA9052_ALARMH_ALARMHOUR; + rtc_tm->tm_min = msg[--loop_index].data & DA9052_ALARMMI_ALARMMIN; + + validate_param = da9052_rtc_validate_parameters(rtc_tm); + if (validate_param) + return validate_param; + + /* System compatability */ + rtc_tm->tm_year += 100; + rtc_tm->tm_mon -= 1; + + return 0; +} + +static int da9052_alarm_settime(struct da9052 *da9052, struct rtc_time *rtc_tm) +{ + + struct da9052_ssc_msg msg_arr[5]; + struct da9052_ssc_msg msg; + int validate_param = 0; + unsigned char loop_index = 0; + int ret = 0; + + rtc_tm->tm_sec = 0; + + /* System compatability */ + rtc_tm->tm_year -= 100; + rtc_tm->tm_mon += 1; + + validate_param = da9052_rtc_validate_parameters(rtc_tm); + if (validate_param) + return validate_param; + + msg.addr = DA9052_ALARMMI_REG; + msg.data = 0; + + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + msg.data = msg.data & ~(DA9052_ALARMMI_ALARMMIN); + msg.data |= rtc_tm->tm_min; + + msg_arr[loop_index].addr = DA9052_ALARMMI_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = msg.data; + + msg_arr[loop_index].addr = DA9052_ALARMH_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = rtc_tm->tm_hour; + + msg_arr[loop_index].addr = DA9052_ALARMD_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = rtc_tm->tm_mday; + + msg_arr[loop_index].addr = DA9052_ALARMMO_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = rtc_tm->tm_mon; + + msg.addr = DA9052_ALARMY_REG; + msg.data = 0; + ret = da9052->read(da9052, &msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + msg.data = msg.data & ~(DA9052_ALARMY_ALARMYEAR); + + + msg.data |= rtc_tm->tm_year; + msg_arr[loop_index].addr = DA9052_ALARMY_REG; + msg_arr[loop_index].data = 0; + msg_arr[loop_index++].data = msg.data; + + ret = da9052->write_many(da9052, msg_arr, loop_index); + if (ret) { + da9052_unlock(da9052); + return ret; + } + + da9052_unlock(da9052); + return 0; +} + +static int da9052_rtc_get_alarm_status(struct da9052 *da9052) +{ + struct da9052_ssc_msg msg; + int ret = 0; + + msg.addr = DA9052_ALARMY_REG; + msg.data = 0; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + da9052_unlock(da9052); + msg.data &= DA9052_ALARMY_ALARMON; + + return (msg.data > 0) ? 1 : 0; +} + + +static int da9052_rtc_enable_alarm(struct da9052 *da9052, unsigned char flag) +{ + struct da9052_ssc_msg msg; + int ret = 0; + + msg.addr = DA9052_ALARMY_REG; + da9052_lock(da9052); + ret = da9052->read(da9052, &msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + if (flag) + msg.data = msg.data | DA9052_ALARMY_ALARMON; + else + msg.data = msg.data & ~(DA9052_ALARMY_ALARMON); + + ret = da9052->write(da9052, &msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + da9052_unlock(da9052); + + return 0; +} + + +static ssize_t da9052_rtc_mask_irq(struct da9052 *da9052) + { + unsigned char data = 0; + ssize_t ret = 0; + struct da9052_ssc_msg ssc_msg; + + ssc_msg.addr = DA9052_IRQMASKA_REG; + ssc_msg.data = 0; + + da9052_lock(da9052); + ret = da9052->read(da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + data = ret; + ssc_msg.data = data |= DA9052_IRQMASKA_MALRAM; + + ret = da9052->write(da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + da9052_unlock(da9052); + return 0; +} + + +static ssize_t da9052_rtc_unmask_irq(struct da9052 *da9052) +{ + unsigned char data = 0; + ssize_t ret = 0; + struct da9052_ssc_msg ssc_msg; + + ssc_msg.addr = DA9052_IRQMASKA_REG; + ssc_msg.data = 0; + + da9052_lock(da9052); + ret = da9052->read(da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + data = ret; + ssc_msg.data = data &= ~DA9052_IRQMASKA_MALRAM; + + ret = da9052->write(da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(da9052); + return ret; + } + + da9052_unlock(da9052); + return 0; + +} + +static int da9052_rtc_class_ops_gettime + (struct device *dev, struct rtc_time *rtc_tm) +{ + int ret; + struct da9052 *da9052 = dev_get_drvdata(dev->parent); + ret = da9052_rtc_gettime(da9052, rtc_tm); + if (ret) + return ret; + return 0; +} + + +static int da9052_rtc_class_ops_settime(struct device *dev, struct rtc_time *tm) +{ + int ret; + struct da9052 *da9052 = dev_get_drvdata(dev->parent); + ret = da9052_rtc_settime(da9052, tm); + + return ret; +} + +static int da9052_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + int ret; + struct rtc_time *tm = &alrm->time; + struct da9052 *da9052 = dev_get_drvdata(dev->parent); + ret = da9052_alarm_gettime(da9052, tm); + + if (ret) + return ret; + + alrm->enabled = da9052_rtc_get_alarm_status(da9052); + + return 0; + +} + +static int da9052_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + int ret = 0; + struct rtc_time *tm = &alrm->time; + struct da9052 *da9052 = dev_get_drvdata(dev->parent); + + ret = da9052_alarm_settime(da9052, tm); + + if (ret) + return ret; + + ret = da9052_rtc_enable_alarm(da9052, 1); + + return ret; +} + +static int da9052_rtc_update_irq_enable(struct device *dev, + unsigned int enabled) +{ + struct da9052_rtc *priv = dev_get_drvdata(dev); + int ret = -ENODATA; + + da9052_lock(priv->da9052); + + ret = (enabled ? da9052_rtc_unmask_irq : da9052_rtc_mask_irq) + (priv->da9052); + + da9052_unlock(priv->da9052); + + return ret; +} + +static int da9052_rtc_alarm_irq_enable(struct device *dev, + unsigned int enabled) +{ + struct da9052_rtc *priv = dev_get_drvdata(dev); + + if (enabled) + return da9052_rtc_enable_alarm(priv->da9052, enabled); + else + return da9052_rtc_enable_alarm(priv->da9052, enabled); +} + +static const struct rtc_class_ops da9052_rtc_ops = { + .read_time = da9052_rtc_class_ops_gettime, + .set_time = da9052_rtc_class_ops_settime, + .read_alarm = da9052_rtc_readalarm, + .set_alarm = da9052_rtc_setalarm, +#if 0 + .update_irq_enable = da9052_rtc_update_irq_enable, + .alarm_irq_enable = da9052_rtc_alarm_irq_enable, +#endif +}; + + +static int __devinit da9052_rtc_probe(struct platform_device *pdev) +{ + int ret; + struct da9052_rtc *priv; + struct da9052_ssc_msg ssc_msg; + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->da9052 = dev_get_drvdata(pdev->dev.parent); + platform_set_drvdata(pdev, priv); + + /* KPIT added to support sysfs wakealarm attribute */ + pdev->dev.power.can_wakeup = 1; + /* KPIT added to support sysfs wakealarm attribute */ + + /* Set the EH structure */ + priv->eh_data.eve_type = ALARM_EVE; + priv->eh_data.call_back = &da9052_rtc_notifier; + ret = priv->da9052->register_event_notifier(priv->da9052, + &priv->eh_data); + if (ret) + goto err_register_alarm; + + priv->is_min_alarm = 1; + priv->enable_tick_alarm = 1; + priv->enable_clk_buffer = 1; + priv->set_osc_trim_freq = 5; + /* Enable/Disable TICK Alarm */ + /* Read ALARM YEAR register */ + ssc_msg.addr = DA9052_ALARMY_REG; + ssc_msg.data = 0; + + da9052_lock(priv->da9052); + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(priv->da9052); + goto err_ssc_comm; + } + + if (priv->enable_tick_alarm) + ssc_msg.data = (ssc_msg.data | DA9052_ALARMY_TICKON); + else + ssc_msg.data = + ((ssc_msg.data & ~(DA9052_ALARMY_TICKON))); + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(priv->da9052); + goto err_ssc_comm; + } + + /* Set TICK Alarm to 1 minute or 1 sec */ + /* Read ALARM MINUTES register */ + ssc_msg.addr = DA9052_ALARMMI_REG; + ssc_msg.data = 0; + + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(priv->da9052); + goto err_ssc_comm; + } + + if (priv->is_min_alarm) + /* Set 1 minute tick type */ + ssc_msg.data = (ssc_msg.data | DA9052_ALARMMI_TICKTYPE); + else + /* Set 1 sec tick type */ + ssc_msg.data = (ssc_msg.data & ~(DA9052_ALARMMI_TICKTYPE)); + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(priv->da9052); + goto err_ssc_comm; + } + + /* Enable/Disable Clock buffer in Power Down Mode */ + ssc_msg.addr = DA9052_PDDIS_REG; + ssc_msg.data = 0; + + ret = priv->da9052->read(priv->da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(priv->da9052); + goto err_ssc_comm; + } + + if (priv->enable_clk_buffer) + ssc_msg.data = (ssc_msg.data | DA9052_PDDIS_OUT32KPD); + else + ssc_msg.data = (ssc_msg.data & ~(DA9052_PDDIS_OUT32KPD)); + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(priv->da9052); + goto err_ssc_comm; + } + + /* Set clock trim frequency value */ + ssc_msg.addr = DA9052_OSCTRIM_REG; + ssc_msg.data = priv->set_osc_trim_freq; + + ret = priv->da9052->write(priv->da9052, &ssc_msg); + if (ret != 0) { + da9052_unlock(priv->da9052); + goto err_ssc_comm; + } + da9052_unlock(priv->da9052); + + priv->rtc = rtc_device_register(pdev->name, + &pdev->dev, &da9052_rtc_ops, THIS_MODULE); + if (IS_ERR(priv->rtc)) { + ret = PTR_ERR(priv->rtc); + goto err_ssc_comm; + } + return 0; + +err_ssc_comm: + priv->da9052->unregister_event_notifier + (priv->da9052, &priv->eh_data); +err_register_alarm: + platform_set_drvdata(pdev, NULL); + kfree(priv); + + return ret; +} + +static int __devexit da9052_rtc_remove(struct platform_device *pdev) +{ + struct da9052_rtc *priv = platform_get_drvdata(pdev); + rtc_device_unregister(priv->rtc); + da9052_lock(priv->da9052); + priv->da9052->unregister_event_notifier(priv->da9052, &priv->eh_data); + da9052_unlock(priv->da9052); + platform_set_drvdata(pdev, NULL); + kfree(priv); + return 0; +} + +static struct platform_driver da9052_rtc_driver = { + .probe = da9052_rtc_probe, + .remove = __devexit_p(da9052_rtc_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + + +static int __init da9052_rtc_init(void) +{ + return platform_driver_register(&da9052_rtc_driver); +} +module_init(da9052_rtc_init); + +static void __exit da9052_rtc_exit(void) +{ + platform_driver_unregister(&da9052_rtc_driver); +} +module_exit(da9052_rtc_exit); + +MODULE_AUTHOR("Dialog Semiconductor Ltd "); +MODULE_DESCRIPTION("RTC driver for Dialog DA9052 PMIC"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c new file mode 100644 index 000000000000..599c525a9f66 --- /dev/null +++ b/drivers/rtc/rtc-imxdi.c @@ -0,0 +1,581 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* based on rtc-mc13892.c */ + +/* + * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block + * to implement a Linux RTC. Times and alarms are truncated to seconds. + * Since the RTC framework performs API locking via rtc->ops_lock the + * only simultaneous accesses we need to deal with is updating DryIce + * registers while servicing an alarm. + * + * Note that reading the DSR (DryIce Status Register) automatically clears + * the WCF (Write Complete Flag). All DryIce writes are synchronized to the + * LP (Low Power) domain and set the WCF upon completion. Writes to the + * DIER (DryIce Interrupt Enable Register) are the only exception. These + * occur at normal bus speeds and do not set WCF. Periodic interrupts are + * not supported by the hardware. + */ + +/* #define DEBUG */ +/* #define DI_DEBUG_REGIO */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* DryIce Register Definitions */ + +#define DTCMR 0x00 /* Time Counter MSB Reg */ +#define DTCLR 0x04 /* Time Counter LSB Reg */ + +#define DCAMR 0x08 /* Clock Alarm MSB Reg */ +#define DCALR 0x0c /* Clock Alarm LSB Reg */ +#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ + +#define DCR 0x10 /* Control Reg */ +#define DCR_TCE (1 << 3) /* Time Counter Enable */ + +#define DSR 0x14 /* Status Reg */ +#define DSR_WBF (1 << 10) /* Write Busy Flag */ +#define DSR_WNF (1 << 9) /* Write Next Flag */ +#define DSR_WCF (1 << 8) /* Write Complete Flag */ +#define DSR_WEF (1 << 7) /* Write Error Flag */ +#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ +#define DSR_NVF (1 << 1) /* Non-Valid Flag */ +#define DSR_SVF (1 << 0) /* Security Violation Flag */ + +#define DIER 0x18 /* Interrupt Enable Reg */ +#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ +#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ +#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ +#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ + +#ifndef DI_DEBUG_REGIO +/* dryice read register */ +#define di_read(pdata, reg) __raw_readl((pdata)->ioaddr + (reg)) + +/* dryice write register */ +#define di_write(pdata, val, reg) __raw_writel((val), (pdata)->ioaddr + (reg)) +#else +/* dryice read register - debug version */ +static inline u32 di_read(struct rtc_drv_data *pdata, int reg) +{ + u32 val = __raw_readl(pdata->ioaddr + reg); + pr_info("di_read(0x%02x) = 0x%08x\n", reg, val); + return val; +} + +/* dryice write register - debug version */ +static inline void di_write(struct rtc_drv_data *pdata, u32 val, int reg) +{ + printk(KERN_INFO "di_write(0x%08x, 0x%02x)\n", val, reg); + __raw_writel(val, pdata->ioaddr + reg); +} +#endif + +/* + * dryice write register with wait and error handling. + * all registers, except for DIER, should use this method. + */ +#define di_write_wait_err(pdata, val, reg, rc, label) \ + do { \ + if (di_write_wait((pdata), (val), (reg))) { \ + rc = -EIO; \ + goto label; \ + } \ + } while (0) + +struct rtc_drv_data { + struct platform_device *pdev; /* pointer to platform dev */ + struct rtc_device *rtc; /* pointer to rtc struct */ + unsigned long baseaddr; /* physical bass address */ + void __iomem *ioaddr; /* virtual base address */ + int size; /* size of register region */ + int irq; /* dryice normal irq */ + struct clk *clk; /* dryice clock control */ + u32 dsr; /* copy of dsr reg from isr */ + spinlock_t irq_lock; /* irq resource lock */ + wait_queue_head_t write_wait; /* write-complete queue */ + struct mutex write_mutex; /* force reg writes to be sequential */ + struct work_struct work; /* schedule alarm work */ +}; + +/* + * enable a dryice interrupt + */ +static inline void di_int_enable(struct rtc_drv_data *pdata, u32 intr) +{ + unsigned long flags; + + spin_lock_irqsave(&pdata->irq_lock, flags); + di_write(pdata, di_read(pdata, DIER) | intr, DIER); + spin_unlock_irqrestore(&pdata->irq_lock, flags); +} + +/* + * disable a dryice interrupt + */ +static inline void di_int_disable(struct rtc_drv_data *pdata, u32 intr) +{ + unsigned long flags; + + spin_lock_irqsave(&pdata->irq_lock, flags); + di_write(pdata, di_read(pdata, DIER) & ~intr, DIER); + spin_unlock_irqrestore(&pdata->irq_lock, flags); +} + +/* + * This function attempts to clear the dryice write-error flag. + * + * A dryice write error is similar to a bus fault and should not occur in + * normal operation. Clearing the flag requires another write, so the root + * cause of the problem may need to be fixed before the flag can be cleared. + */ +static void clear_write_error(struct rtc_drv_data *pdata) +{ + int cnt; + + dev_warn(&pdata->pdev->dev, "WARNING: Register write error!\n"); + + for (;;) { + /* clear the write error flag */ + di_write(pdata, DSR_WEF, DSR); + + /* wait for it to take effect */ + for (cnt = 0; cnt < 100; cnt++) { + if ((di_read(pdata, DSR) & DSR_WEF) == 0) + return; + udelay(10); + } + dev_err(&pdata->pdev->dev, + "ERROR: Cannot clear write-error flag!\n"); + } +} + +/* + * Write a dryice register and wait until it completes. + * + * This function uses interrupts to determine when the + * write has completed. + */ +static int di_write_wait(struct rtc_drv_data *pdata, u32 val, int reg) +{ + int ret; + int rc = 0; + + /* serialize register writes */ + mutex_lock(&pdata->write_mutex); + + /* enable the write-complete interrupt */ + di_int_enable(pdata, DIER_WCIE); + + pdata->dsr = 0; + + /* do the register write */ + di_write(pdata, val, reg); + + /* wait for the write to finish */ + ret = wait_event_interruptible_timeout(pdata->write_wait, + pdata->dsr & (DSR_WCF | DSR_WEF), + 1 * HZ); + if (ret == 0) + dev_warn(&pdata->pdev->dev, "Write-wait timeout\n"); + + /* check for write error */ + if (pdata->dsr & DSR_WEF) { + clear_write_error(pdata); + rc = -EIO; + } + mutex_unlock(&pdata->write_mutex); + return rc; +} + +/* + * rtc device ioctl + * + * The rtc framework handles the basic rtc ioctls on behalf + * of the driver by calling the functions registered in the + * rtc_ops structure. + */ +static int dryice_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + + dev_dbg(dev, "%s(0x%x)\n", __func__, cmd); + switch (cmd) { + case RTC_AIE_OFF: /* alarm disable */ + di_int_disable(pdata, DIER_CAIE); + return 0; + + case RTC_AIE_ON: /* alarm enable */ + di_int_enable(pdata, DIER_CAIE); + return 0; + } + return -ENOIOCTLCMD; +} + +/* + * read the seconds portion of the current time from the dryice time counter + */ +static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + unsigned long now; + + dev_dbg(dev, "%s\n", __func__); + now = di_read(pdata, DTCMR); + rtc_time_to_tm(now, tm); + + return 0; +} + +/* + * set the seconds portion of dryice time counter and clear the + * fractional part. + */ +static int dryice_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + unsigned long now; + int rc; + + dev_dbg(dev, "%s\n", __func__); + rc = rtc_tm_to_time(tm, &now); + if (rc == 0) { + /* zero the fractional part first */ + di_write_wait_err(pdata, 0, DTCLR, rc, err); + di_write_wait_err(pdata, now, DTCMR, rc, err); + } +err: + return rc; +} + +/* + * read the seconds portion of the alarm register. + * the fractional part of the alarm register is always zero. + */ +static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + u32 dcamr; + + dev_dbg(dev, "%s\n", __func__); + dcamr = di_read(pdata, DCAMR); + rtc_time_to_tm(dcamr, &alarm->time); + + /* alarm is enabled if the interrupt is enabled */ + alarm->enabled = (di_read(pdata, DIER) & DIER_CAIE) != 0; + + /* don't allow the DSR read to mess up DSR_WCF */ + mutex_lock(&pdata->write_mutex); + + /* alarm is pending if the alarm flag is set */ + alarm->pending = (di_read(pdata, DSR) & DSR_CAF) != 0; + + mutex_unlock(&pdata->write_mutex); + + return 0; +} + +/* + * set the seconds portion of dryice alarm register + */ +static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + unsigned long now; + unsigned long alarm_time; + int rc; + + dev_dbg(dev, "%s\n", __func__); + rc = rtc_tm_to_time(&alarm->time, &alarm_time); + if (rc) + return rc; + + /* don't allow setting alarm in the past */ + now = di_read(pdata, DTCMR); + if (alarm_time < now) + return -EINVAL; + + /* write the new alarm time */ + di_write_wait_err(pdata, (u32)alarm_time, DCAMR, rc, err); + + if (alarm->enabled) + di_int_enable(pdata, DIER_CAIE); /* enable alarm intr */ + else + di_int_disable(pdata, DIER_CAIE); /* disable alarm intr */ +err: + return rc; +} + +static struct rtc_class_ops dryice_rtc_ops = { + .ioctl = dryice_rtc_ioctl, + .read_time = dryice_rtc_read_time, + .set_time = dryice_rtc_set_time, + .read_alarm = dryice_rtc_read_alarm, + .set_alarm = dryice_rtc_set_alarm, +}; + +/* + * dryice "normal" interrupt handler + */ +static irqreturn_t dryice_norm_irq(int irq, void *dev_id) +{ + struct rtc_drv_data *pdata = dev_id; + u32 dsr, dier; + irqreturn_t rc = IRQ_NONE; + + dier = di_read(pdata, DIER); + + /* handle write complete and write error cases */ + if ((dier & DIER_WCIE)) { + /*If the write wait queue is empty then there is no pending + operations. It means the interrupt is for DryIce -Security. + IRQ must be returned as none.*/ + if (list_empty_careful(&pdata->write_wait.task_list)) + return rc; + + /* DSR_WCF clears itself on DSR read */ + dsr = di_read(pdata, DSR); + if ((dsr & (DSR_WCF | DSR_WEF))) { + /* mask the interrupt */ + di_int_disable(pdata, DIER_WCIE); + + /* save the dsr value for the wait queue */ + pdata->dsr |= dsr; + + wake_up_interruptible(&pdata->write_wait); + rc = IRQ_HANDLED; + } + } + + /* handle the alarm case */ + if ((dier & DIER_CAIE)) { + /* DSR_WCF clears itself on DSR read */ + dsr = di_read(pdata, DSR); + if (dsr & DSR_CAF) { + /* mask the interrupt */ + di_int_disable(pdata, DIER_CAIE); + + /* finish alarm in user context */ + schedule_work(&pdata->work); + rc = IRQ_HANDLED; + } + } + return rc; +} + +/* + * post the alarm event from user context so it can sleep + * on the write completion. + */ +static void dryice_work(struct work_struct *work) +{ + struct rtc_drv_data *pdata = container_of(work, struct rtc_drv_data, + work); + int rc; + + /* dismiss the interrupt (ignore error) */ + di_write_wait_err(pdata, DSR_CAF, DSR, rc, err); +err: + /* + * pass the alarm event to the rtc framework. note that + * rtc_update_irq expects to be called with interrupts off. + */ + local_irq_disable(); + rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF); + local_irq_enable(); +} + +/* + * probe for dryice rtc device + */ +static int dryice_rtc_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc; + struct resource *res; + struct rtc_drv_data *pdata = NULL; + void __iomem *ioaddr = NULL; + int rc = 0; + + dev_dbg(&pdev->dev, "%s\n", __func__); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->pdev = pdev; + pdata->irq = -1; + pdata->size = res->end - res->start + 1; + + if (!request_mem_region(res->start, pdata->size, pdev->name)) { + rc = -EBUSY; + goto err; + } + pdata->baseaddr = res->start; + ioaddr = ioremap(pdata->baseaddr, pdata->size); + if (!ioaddr) { + rc = -ENOMEM; + goto err; + } + pdata->ioaddr = ioaddr; + pdata->irq = platform_get_irq(pdev, 0); + + init_waitqueue_head(&pdata->write_wait); + + INIT_WORK(&pdata->work, dryice_work); + + mutex_init(&pdata->write_mutex); + + pdata->clk = clk_get(NULL, "dryice_clk"); + clk_enable(pdata->clk); + + if (pdata->irq >= 0) { + if (request_irq(pdata->irq, dryice_norm_irq, IRQF_SHARED, + pdev->name, pdata) < 0) { + dev_warn(&pdev->dev, "interrupt not available.\n"); + pdata->irq = -1; + goto err; + } + } + + /* + * Initialize dryice hardware + */ + + /* put dryice into valid state */ + if (di_read(pdata, DSR) & DSR_NVF) + di_write_wait_err(pdata, DSR_NVF | DSR_SVF, DSR, rc, err); + + /* mask alarm interrupt */ + di_int_disable(pdata, DIER_CAIE); + + /* initialize alarm */ + di_write_wait_err(pdata, DCAMR_UNSET, DCAMR, rc, err); + di_write_wait_err(pdata, 0, DCALR, rc, err); + + /* clear alarm flag */ + if (di_read(pdata, DSR) & DSR_CAF) + di_write_wait_err(pdata, DSR_CAF, DSR, rc, err); + + /* the timer won't count if it has never been written to */ + if (!di_read(pdata, DTCMR)) + di_write_wait_err(pdata, 0, DTCMR, rc, err); + + /* start keeping time */ + if (!(di_read(pdata, DCR) & DCR_TCE)) + di_write_wait_err(pdata, di_read(pdata, DCR) | DCR_TCE, DCR, + rc, err); + + rtc = rtc_device_register(pdev->name, &pdev->dev, + &dryice_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + rc = PTR_ERR(rtc); + goto err; + } + pdata->rtc = rtc; + platform_set_drvdata(pdev, pdata); + + return 0; +err: + if (pdata->rtc) + rtc_device_unregister(pdata->rtc); + + if (pdata->irq >= 0) + free_irq(pdata->irq, pdata); + + if (pdata->clk) { + clk_disable(pdata->clk); + clk_put(pdata->clk); + } + + if (pdata->ioaddr) + iounmap(pdata->ioaddr); + + if (pdata->baseaddr) + release_mem_region(pdata->baseaddr, pdata->size); + + kfree(pdata); + + return rc; +} + +static int __exit dryice_rtc_remove(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + + flush_scheduled_work(); + + if (pdata->rtc) + rtc_device_unregister(pdata->rtc); + + /* mask alarm interrupt */ + di_int_disable(pdata, DIER_CAIE); + + if (pdata->irq >= 0) + free_irq(pdata->irq, pdata); + + if (pdata->clk) { + clk_disable(pdata->clk); + clk_put(pdata->clk); + } + + if (pdata->ioaddr) + iounmap(pdata->ioaddr); + + if (pdata->baseaddr) + release_mem_region(pdata->baseaddr, pdata->size); + + kfree(pdata); + + return 0; +} + +static struct platform_driver dryice_rtc_driver = { + .driver = { + .name = "imxdi_rtc", + .owner = THIS_MODULE, + }, + .probe = dryice_rtc_probe, + .remove = __exit_p(dryice_rtc_remove), +}; + +static int __init dryice_rtc_init(void) +{ + pr_info("IMXDI Realtime Clock Driver (RTC)\n"); + return platform_driver_register(&dryice_rtc_driver); +} + +static void __exit dryice_rtc_exit(void) +{ + platform_driver_unregister(&dryice_rtc_driver); +} + +module_init(dryice_rtc_init); +module_exit(dryice_rtc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("IMXDI Realtime Clock Driver (RTC)"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/rtc-mc13892.c b/drivers/rtc/rtc-mc13892.c new file mode 100644 index 000000000000..8abe1ba02bc0 --- /dev/null +++ b/drivers/rtc/rtc-mc13892.c @@ -0,0 +1,257 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include + +#include +#include + +#define RTC_TIME_LSH 0 +#define RTC_DAY_LSH 0 +#define RTCALARM_TIME_LSH 0 +#define RTCALARM_DAY_LSH 0 + +#define RTC_TIME_WID 17 +#define RTC_DAY_WID 15 +#define RTCALARM_TIME_WID 17 +#define RTCALARM_DAY_WID 15 + +static unsigned long rtc_status; + +static int mxc_rtc_open(struct device *dev) +{ + if (test_and_set_bit(1, &rtc_status)) + return -EBUSY; + return 0; +} + +static void mxc_rtc_release(struct device *dev) +{ + clear_bit(1, &rtc_status); +} + +static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + switch (cmd) { + case RTC_AIE_OFF: + pr_debug("alarm off\n"); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, 0x100000, 0x100000)); + return 0; + case RTC_AIE_ON: + pr_debug("alarm on\n"); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, 0, 0x100000)); + return 0; + } + + return -ENOIOCTLCMD; +} + +static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0, day_reg_val2; + unsigned int mask, value; + unsigned long time; + + do { + mask = BITFMASK(RTC_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val = BITFEXT(value, RTC_DAY); + + mask = BITFMASK(RTC_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_TIME, &value, mask)); + tod_reg_val = BITFEXT(value, RTC_TIME); + + mask = BITFMASK(RTC_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val2 = BITFEXT(value, RTC_DAY); + } while (day_reg_val != day_reg_val2); + + time = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * 86400)); + + rtc_time_to_tm(time, tm); + + return 0; +} + +static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val, day_reg_val2 = 0; + unsigned int mask, value; + unsigned long time; + + if (rtc_valid_tm(tm)) + return -1; + + rtc_tm_to_time(tm, &time); + + tod_reg_val = time % 86400; + day_reg_val = time / 86400; + + do { + mask = BITFMASK(RTC_DAY); + value = BITFVAL(RTC_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY, value, mask)); + + mask = BITFMASK(RTC_TIME); + value = BITFVAL(RTC_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_TIME, value, mask)); + + mask = BITFMASK(RTC_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY, &value, mask)); + day_reg_val2 = BITFEXT(value, RTC_DAY); + } while (day_reg_val != day_reg_val2); + + return 0; +} + +static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + unsigned long time; + + mask = BITFMASK(RTCALARM_TIME); + CHECK_ERROR(pmic_read_reg(REG_RTC_ALARM, &value, mask)); + tod_reg_val = BITFEXT(value, RTCALARM_TIME); + + mask = BITFMASK(RTCALARM_DAY); + CHECK_ERROR(pmic_read_reg(REG_RTC_DAY_ALARM, &value, mask)); + day_reg_val = BITFEXT(value, RTCALARM_DAY); + + time = (unsigned long)((unsigned long)(tod_reg_val & + 0x0001FFFF) + + (unsigned long)(day_reg_val * 86400)); + rtc_time_to_tm(time, &(alrm->time)); + + return 0; +} + +static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + unsigned int tod_reg_val = 0; + unsigned int day_reg_val = 0; + unsigned int mask, value; + unsigned long time; + + if (rtc_valid_tm(&alrm->time)) + return -1; + + rtc_tm_to_time(&alrm->time, &time); + + tod_reg_val = time % 86400; + day_reg_val = time / 86400; + + mask = BITFMASK(RTCALARM_TIME); + value = BITFVAL(RTCALARM_TIME, tod_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_ALARM, value, mask)); + + mask = BITFMASK(RTCALARM_DAY); + value = BITFVAL(RTCALARM_DAY, day_reg_val); + CHECK_ERROR(pmic_write_reg(REG_RTC_DAY_ALARM, value, mask)); + + return 0; +} + +struct rtc_drv_data { + struct rtc_device *rtc; + pmic_event_callback_t event; +}; + +static struct rtc_class_ops mxc_rtc_ops = { + .open = mxc_rtc_open, + .release = mxc_rtc_release, + .ioctl = mxc_rtc_ioctl, + .read_time = mxc_rtc_read_time, + .set_time = mxc_rtc_set_time, + .read_alarm = mxc_rtc_read_alarm, + .set_alarm = mxc_rtc_set_alarm, +}; + +static void mxc_rtc_alarm_int(void *data) +{ + struct rtc_drv_data *pdata = data; + + rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF); +} + +static int mxc_rtc_probe(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = NULL; + + printk(KERN_INFO "mc13892 rtc probe start\n"); + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + + if (!pdata) + return -ENOMEM; + + pdata->event.func = mxc_rtc_alarm_int; + pdata->event.param = pdata; + CHECK_ERROR(pmic_event_subscribe(EVENT_TODAI, pdata->event)); + + device_init_wakeup(&pdev->dev, 1); + pdata->rtc = rtc_device_register(pdev->name, &pdev->dev, + &mxc_rtc_ops, THIS_MODULE); + + platform_set_drvdata(pdev, pdata); + if (IS_ERR(pdata->rtc)) + return -1; + + printk(KERN_INFO "mc13892 rtc probe succeed\n"); + return 0; +} + +static int __exit mxc_rtc_remove(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + + rtc_device_unregister(pdata->rtc); + CHECK_ERROR(pmic_event_unsubscribe(EVENT_TODAI, pdata->event)); + + return 0; +} + +static struct platform_driver mxc_rtc_driver = { + .driver = { + .name = "pmic_rtc", + }, + .probe = mxc_rtc_probe, + .remove = __exit_p(mxc_rtc_remove), +}; + +static int __init mxc_rtc_init(void) +{ + return platform_driver_register(&mxc_rtc_driver); +} + +static void __exit mxc_rtc_exit(void) +{ + platform_driver_unregister(&mxc_rtc_driver); + +} + +module_init(mxc_rtc_init); +module_exit(mxc_rtc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MC13892 Realtime Clock Driver (RTC)"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c index 25ec921db07c..850be4842d4f 100644 --- a/drivers/rtc/rtc-mxc.c +++ b/drivers/rtc/rtc-mxc.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -17,8 +17,6 @@ #include #include -#include - #define RTC_INPUT_CLK_32768HZ (0x00 << 5) #define RTC_INPUT_CLK_32000HZ (0x01 << 5) #define RTC_INPUT_CLK_38400HZ (0x02 << 5) diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c new file mode 100644 index 000000000000..4d2317bd706d --- /dev/null +++ b/drivers/rtc/rtc-mxc_v2.c @@ -0,0 +1,754 @@ +/* + * Copyright (C) 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* + * Implementation based on rtc-ds1553.c + */ + +/*! + * @defgroup RTC Real Time Clock (RTC) Driver + */ +/*! + * @file rtc-mxc_v2.c + * @brief Real Time Clock interface + * + * This file contains Real Time Clock interface for Linux. + * + * @ingroup RTC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SRTC_LPSCLR_LLPSC_LSH 17 /* start bit for LSB time value */ + +#define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */ + +#define SRTC_LPCR_SWR_LP (1 << 0) /* lp software reset */ +#define SRTC_LPCR_EN_LP (1 << 3) /* lp enable */ +#define SRTC_LPCR_WAE (1 << 4) /* lp wakeup alarm enable */ +#define SRTC_LPCR_SAE (1 << 5) /* lp security alarm enable */ +#define SRTC_LPCR_SI (1 << 6) /* lp security interrupt enable */ +#define SRTC_LPCR_ALP (1 << 7) /* lp alarm flag */ +#define SRTC_LPCR_LTC (1 << 8) /* lp lock time counter */ +#define SRTC_LPCR_LMC (1 << 9) /* lp lock monotonic counter */ +#define SRTC_LPCR_SV (1 << 10) /* lp security violation */ +#define SRTC_LPCR_NSA (1 << 11) /* lp non secure access */ +#define SRTC_LPCR_NVEIE (1 << 12) /* lp non valid state exit int en */ +#define SRTC_LPCR_IEIE (1 << 13) /* lp init state exit int enable */ +#define SRTC_LPCR_NVE (1 << 14) /* lp non valid state exit bit */ +#define SRTC_LPCR_IE (1 << 15) /* lp init state exit bit */ + +#define SRTC_LPCR_ALL_INT_EN (SRTC_LPCR_WAE | SRTC_LPCR_SAE | \ + SRTC_LPCR_SI | SRTC_LPCR_ALP | \ + SRTC_LPCR_NVEIE | SRTC_LPCR_IEIE) + +#define SRTC_LPSR_TRI (1 << 0) /* lp time read invalidate */ +#define SRTC_LPSR_PGD (1 << 1) /* lp power supply glitc detected */ +#define SRTC_LPSR_CTD (1 << 2) /* lp clock tampering detected */ +#define SRTC_LPSR_ALP (1 << 3) /* lp alarm flag */ +#define SRTC_LPSR_MR (1 << 4) /* lp monotonic counter rollover */ +#define SRTC_LPSR_TR (1 << 5) /* lp time rollover */ +#define SRTC_LPSR_EAD (1 << 6) /* lp external alarm detected */ +#define SRTC_LPSR_IT0 (1 << 7) /* lp IIM throttle */ +#define SRTC_LPSR_IT1 (1 << 8) +#define SRTC_LPSR_IT2 (1 << 9) +#define SRTC_LPSR_SM0 (1 << 10) /* lp security mode */ +#define SRTC_LPSR_SM1 (1 << 11) +#define SRTC_LPSR_STATE_LP0 (1 << 12) /* lp state */ +#define SRTC_LPSR_STATE_LP1 (1 << 13) +#define SRTC_LPSR_NVES (1 << 14) /* lp non-valid state exit status */ +#define SRTC_LPSR_IES (1 << 15) /* lp init state exit status */ + +#define MAX_PIE_NUM 15 +#define MAX_PIE_FREQ 32768 +#define MIN_PIE_FREQ 1 + +#define SRTC_PI0 (1 << 0) +#define SRTC_PI1 (1 << 1) +#define SRTC_PI2 (1 << 2) +#define SRTC_PI3 (1 << 3) +#define SRTC_PI4 (1 << 4) +#define SRTC_PI5 (1 << 5) +#define SRTC_PI6 (1 << 6) +#define SRTC_PI7 (1 << 7) +#define SRTC_PI8 (1 << 8) +#define SRTC_PI9 (1 << 9) +#define SRTC_PI10 (1 << 10) +#define SRTC_PI11 (1 << 11) +#define SRTC_PI12 (1 << 12) +#define SRTC_PI13 (1 << 13) +#define SRTC_PI14 (1 << 14) +#define SRTC_PI15 (1 << 15) + +#define PIT_ALL_ON (SRTC_PI1 | SRTC_PI2 | SRTC_PI3 | \ + SRTC_PI4 | SRTC_PI5 | SRTC_PI6 | SRTC_PI7 | \ + SRTC_PI8 | SRTC_PI9 | SRTC_PI10 | SRTC_PI11 | \ + SRTC_PI12 | SRTC_PI13 | SRTC_PI14 | SRTC_PI15) + +#define SRTC_SWR_HP (1 << 0) /* hp software reset */ +#define SRTC_EN_HP (1 << 3) /* hp enable */ +#define SRTC_TS (1 << 4) /* time syncronize hp with lp */ + +#define SRTC_IE_AHP (1 << 16) /* Alarm HP Interrupt Enable bit */ +#define SRTC_IE_WDHP (1 << 18) /* Write Done HP Interrupt Enable bit */ +#define SRTC_IE_WDLP (1 << 19) /* Write Done LP Interrupt Enable bit */ + +#define SRTC_ISR_AHP (1 << 16) /* interrupt status: alarm hp */ +#define SRTC_ISR_WDHP (1 << 18) /* interrupt status: write done hp */ +#define SRTC_ISR_WDLP (1 << 19) /* interrupt status: write done lp */ +#define SRTC_ISR_WPHP (1 << 20) /* interrupt status: write pending hp */ +#define SRTC_ISR_WPLP (1 << 21) /* interrupt status: write pending lp */ + +#define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */ +#define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */ +#define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */ +#define SRTC_LPSMCR 0x0C /* LP Secure Monotonic Counter Reg */ +#define SRTC_LPCR 0x10 /* LP Control Reg */ +#define SRTC_LPSR 0x14 /* LP Status Reg */ +#define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */ +#define SRTC_LPGR 0x1C /* LP General Purpose Reg */ +#define SRTC_HPCMR 0x20 /* HP Counter MSB Reg */ +#define SRTC_HPCLR 0x24 /* HP Counter LSB Reg */ +#define SRTC_HPAMR 0x28 /* HP Alarm MSB Reg */ +#define SRTC_HPALR 0x2C /* HP Alarm LSB Reg */ +#define SRTC_HPCR 0x30 /* HP Control Reg */ +#define SRTC_HPISR 0x34 /* HP Interrupt Status Reg */ +#define SRTC_HPIENR 0x38 /* HP Interrupt Enable Reg */ + +#define SRTC_SECMODE_MASK 0x3 /* the mask of SRTC security mode */ +#define SRTC_SECMODE_LOW 0x0 /* Low Security */ +#define SRTC_SECMODE_MED 0x1 /* Medium Security */ +#define SRTC_SECMODE_HIGH 0x2 /* High Security */ +#define SRTC_SECMODE_RESERVED 0x3 /* Reserved */ + +struct rtc_drv_data { + struct rtc_device *rtc; + void __iomem *ioaddr; + unsigned long baseaddr; + int irq; + struct clk *clk; + bool irq_enable; +}; + + +/* completion event for implementing RTC_WAIT_FOR_TIME_SET ioctl */ +DECLARE_COMPLETION(srtc_completion); +/* global to save difference of 47-bit counter value */ +static int64_t time_diff; + +/*! + * @defgroup RTC Real Time Clock (RTC) Driver + */ +/*! + * @file rtc-mxc.c + * @brief Real Time Clock interface + * + * This file contains Real Time Clock interface for Linux. + * + * @ingroup RTC + */ + +static unsigned long rtc_status; + +static DEFINE_SPINLOCK(rtc_lock); + +/*! + * This function does write synchronization for writes to the lp srtc block. + * To take care of the asynchronous CKIL clock, all writes from the IP domain + * will be synchronized to the CKIL domain. + */ +static inline void rtc_write_sync_lp(void __iomem *ioaddr) +{ + unsigned int i, count; + /* Wait for 3 CKIL cycles */ + for (i = 0; i < 3; i++) { + count = __raw_readl(ioaddr + SRTC_LPSCLR); + while + ((__raw_readl(ioaddr + SRTC_LPSCLR)) == count); + } +} + +/*! + * This function updates the RTC alarm registers and then clears all the + * interrupt status bits. + * + * @param alrm the new alarm value to be updated in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + struct rtc_time alarm_tm, now_tm; + unsigned long now, time; + int ret; + + now = __raw_readl(ioaddr + SRTC_LPSCMR); + rtc_time_to_tm(now, &now_tm); + + alarm_tm.tm_year = now_tm.tm_year; + alarm_tm.tm_mon = now_tm.tm_mon; + alarm_tm.tm_mday = now_tm.tm_mday; + + alarm_tm.tm_hour = alrm->tm_hour; + alarm_tm.tm_min = alrm->tm_min; + alarm_tm.tm_sec = alrm->tm_sec; + + rtc_tm_to_time(&now_tm, &now); + rtc_tm_to_time(&alarm_tm, &time); + + if (time < now) { + time += 60 * 60 * 24; + rtc_time_to_tm(time, &alarm_tm); + } + ret = rtc_tm_to_time(&alarm_tm, &time); + + __raw_writel(time, ioaddr + SRTC_LPSAR); + + /* clear alarm interrupt status bit */ + __raw_writel(SRTC_LPSR_ALP, ioaddr + SRTC_LPSR); + + return ret; +} + +/*! + * This function is the RTC interrupt service routine. + * + * @param irq RTC IRQ number + * @param dev_id device ID which is not used + * + * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file. + */ +static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) +{ + struct platform_device *pdev = dev_id; + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + u32 lp_status, lp_cr; + u32 events = 0; + + lp_status = __raw_readl(ioaddr + SRTC_LPSR); + lp_cr = __raw_readl(ioaddr + SRTC_LPCR); + + /* update irq data & counter */ + if (lp_status & SRTC_LPSR_ALP) { + if (lp_cr & SRTC_LPCR_ALP) + events |= (RTC_AF | RTC_IRQF); + + /* disable further lp alarm interrupts */ + lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE); + } + + /* Update interrupt enables */ + __raw_writel(lp_cr, ioaddr + SRTC_LPCR); + + /* If no interrupts are enabled, turn off interrupts in kernel */ + if (((lp_cr & SRTC_LPCR_ALL_INT_EN) == 0) && (pdata->irq_enable)) { + disable_irq_nosync(pdata->irq); + pdata->irq_enable = false; + } + + /* clear interrupt status */ + __raw_writel(lp_status, ioaddr + SRTC_LPSR); + + rtc_update_irq(pdata->rtc, 1, events); + return IRQ_HANDLED; +} + +/*! + * This function is used to open the RTC driver. + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_open(struct device *dev) +{ + if (test_and_set_bit(1, &rtc_status)) + return -EBUSY; + return 0; +} + +/*! + * clear all interrupts and release the IRQ + */ +static void mxc_rtc_release(struct device *dev) +{ + rtc_status = 0; +} + +/*! + * This function is used to support some ioctl calls directly. + * Other ioctl calls are supported indirectly through the + * arm/common/rtctime.c file. + * + * @param cmd ioctl command as defined in include/linux/rtc.h + * @param arg value for the ioctl command + * + * @return 0 if successful or negative value otherwise. + */ +static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + unsigned long lock_flags = 0; + u32 lp_cr; + u64 time_47bit; + int retVal; + + switch (cmd) { + case RTC_AIE_OFF: + spin_lock_irqsave(&rtc_lock, lock_flags); + lp_cr = __raw_readl(ioaddr + SRTC_LPCR); + lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE); + if (((lp_cr & SRTC_LPCR_ALL_INT_EN) == 0) + && (pdata->irq_enable)) { + disable_irq(pdata->irq); + pdata->irq_enable = false; + } + __raw_writel(lp_cr, ioaddr + SRTC_LPCR); + spin_unlock_irqrestore(&rtc_lock, lock_flags); + return 0; + + case RTC_AIE_ON: + spin_lock_irqsave(&rtc_lock, lock_flags); + if (!pdata->irq_enable) { + enable_irq(pdata->irq); + pdata->irq_enable = true; + } + lp_cr = __raw_readl(ioaddr + SRTC_LPCR); + lp_cr |= SRTC_LPCR_ALP | SRTC_LPCR_WAE; + __raw_writel(lp_cr, ioaddr + SRTC_LPCR); + spin_unlock_irqrestore(&rtc_lock, lock_flags); + return 0; + + case RTC_READ_TIME_47BIT: + time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 | + ((u64) __raw_readl(ioaddr + SRTC_LPSCLR))); + time_47bit >>= SRTC_LPSCLR_LLPSC_LSH; + + if (arg && copy_to_user((u64 *) arg, &time_47bit, sizeof(u64))) + return -EFAULT; + + return 0; + + /* This IOCTL to be used by processes to be notified of time changes */ + case RTC_WAIT_TIME_SET: + + /* don't block without releasing mutex first */ + mutex_unlock(&pdata->rtc->ops_lock); + + /* sleep until awakened by SRTC driver when LPSCMR is changed */ + wait_for_completion(&srtc_completion); + + /* relock mutex because rtc_dev_ioctl will unlock again */ + retVal = mutex_lock_interruptible(&pdata->rtc->ops_lock); + + /* copy the new time difference = new time - previous time + * to the user param. The difference is a signed value */ + if (arg && copy_to_user((int64_t *) arg, &time_diff, + sizeof(int64_t))) + return -EFAULT; + + return retVal; + + } + + return -ENOIOCTLCMD; +} + +/*! + * This function reads the current RTC time into tm in Gregorian date. + * + * @param tm contains the RTC time value upon return + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + + rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSCMR), tm); + return 0; +} + +/*! + * This function sets the internal RTC time based on tm in Gregorian date. + * + * @param tm the time value to be set in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + unsigned long time; + u64 old_time_47bit, new_time_47bit; + int ret; + ret = rtc_tm_to_time(tm, &time); + if (ret != 0) + return ret; + + old_time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 | + ((u64) __raw_readl(ioaddr + SRTC_LPSCLR))); + old_time_47bit >>= SRTC_LPSCLR_LLPSC_LSH; + + __raw_writel(time, ioaddr + SRTC_LPSCMR); + rtc_write_sync_lp(ioaddr); + + new_time_47bit = (((u64) __raw_readl(ioaddr + SRTC_LPSCMR)) << 32 | + ((u64) __raw_readl(ioaddr + SRTC_LPSCLR))); + new_time_47bit >>= SRTC_LPSCLR_LLPSC_LSH; + + /* update the difference between previous time and new time */ + time_diff = new_time_47bit - old_time_47bit; + + /* signal all waiting threads that time changed */ + complete_all(&srtc_completion); + + /* allow signalled threads to handle the time change notification */ + schedule(); + + /* reinitialize completion variable */ + INIT_COMPLETION(srtc_completion); + + return 0; +} + +/*! + * This function reads the current alarm value into the passed in \b alrm + * argument. It updates the \b alrm's pending field value based on the whether + * an alarm interrupt occurs or not. + * + * @param alrm contains the RTC alarm value upon return + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + + rtc_time_to_tm(__raw_readl(ioaddr + SRTC_LPSAR), &alrm->time); + alrm->pending = + ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP) != 0) ? 1 : 0; + + return 0; +} + +/*! + * This function sets the RTC alarm based on passed in alrm. + * + * @param alrm the alarm value to be set in the RTC + * + * @return 0 if successful; non-zero otherwise. + */ +static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + unsigned long lock_flags = 0; + u32 lp_cr; + int ret; + + if (rtc_valid_tm(&alrm->time)) { + if (alrm->time.tm_sec > 59 || + alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) { + return -EINVAL; + } + } + + spin_lock_irqsave(&rtc_lock, lock_flags); + lp_cr = __raw_readl(ioaddr + SRTC_LPCR); + + ret = rtc_update_alarm(dev, &alrm->time); + if (ret) + goto out; + + if (alrm->enabled) + lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE); + else + lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE); + + if (lp_cr & SRTC_LPCR_ALL_INT_EN) { + if (!pdata->irq_enable) { + enable_irq(pdata->irq); + pdata->irq_enable = true; + } + } else { + if (pdata->irq_enable) { + disable_irq(pdata->irq); + pdata->irq_enable = false; + } + } + + __raw_writel(lp_cr, ioaddr + SRTC_LPCR); + +out: + spin_unlock_irqrestore(&rtc_lock, lock_flags); + rtc_write_sync_lp(ioaddr); + return ret; +} + +/*! + * This function is used to provide the content for the /proc/driver/rtc + * file. + * + * @param seq buffer to hold the information that the driver wants to write + * + * @return The number of bytes written into the rtc file. + */ +static int mxc_rtc_proc(struct device *dev, struct seq_file *seq) +{ + struct rtc_drv_data *pdata = dev_get_drvdata(dev); + void __iomem *ioaddr = pdata->ioaddr; + + seq_printf(seq, "alarm_IRQ\t: %s\n", + (((__raw_readl(ioaddr + SRTC_LPCR)) & SRTC_LPCR_ALP) != + 0) ? "yes" : "no"); + + return 0; +} + +/*! + * The RTC driver structure + */ +static struct rtc_class_ops mxc_rtc_ops = { + .open = mxc_rtc_open, + .release = mxc_rtc_release, + .ioctl = mxc_rtc_ioctl, + .read_time = mxc_rtc_read_time, + .set_time = mxc_rtc_set_time, + .read_alarm = mxc_rtc_read_alarm, + .set_alarm = mxc_rtc_set_alarm, + .proc = mxc_rtc_proc, +}; + +/*! MXC RTC Power management control */ +static int mxc_rtc_probe(struct platform_device *pdev) +{ + struct clk *clk; + struct timespec tv; + struct resource *res; + struct rtc_device *rtc; + struct rtc_drv_data *pdata = NULL; + void __iomem *ioaddr; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->clk = clk_get(&pdev->dev, "rtc_clk"); + clk_enable(pdata->clk); + pdata->baseaddr = res->start; + pdata->ioaddr = ioremap(pdata->baseaddr, 0x40); + ioaddr = pdata->ioaddr; + + /* Configure and enable the RTC */ + pdata->irq = platform_get_irq(pdev, 0); + if (pdata->irq >= 0) { + if (request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED, + pdev->name, pdev) < 0) { + dev_warn(&pdev->dev, "interrupt not available.\n"); + pdata->irq = -1; + } else { + disable_irq(pdata->irq); + pdata->irq_enable = false; + } + } + + clk = clk_get(&pdev->dev, "rtc_clk"); + if (clk_get_rate(clk) != 32768) { + printk(KERN_ALERT "rtc clock is not valid"); + ret = -EINVAL; + clk_put(clk); + goto err_out; + } + clk_put(clk); + + /* initialize glitch detect */ + __raw_writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR); + udelay(100); + + /* clear lp interrupt status */ + __raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR); + udelay(100); + + /* move out of init state */ + __raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), + ioaddr + SRTC_LPCR); + + udelay(100); + + while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_IES) == 0) + ; + + /* move out of non-valid state */ + __raw_writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA | + SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR); + + udelay(100); + + while ((__raw_readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_NVES) == 0) + ; + + __raw_writel(0xFFFFFFFF, ioaddr + SRTC_LPSR); + udelay(100); + + rtc = rtc_device_register(pdev->name, &pdev->dev, + &mxc_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto err_out; + } + + pdata->rtc = rtc; + platform_set_drvdata(pdev, pdata); + + tv.tv_nsec = 0; + tv.tv_sec = __raw_readl(ioaddr + SRTC_LPSCMR); + + /* By default, devices should wakeup if they can */ + /* So srtc is set as "should wakeup" as it can */ + device_init_wakeup(&pdev->dev, 1); + + return ret; + +err_out: + clk_disable(pdata->clk); + iounmap(ioaddr); + if (pdata->irq >= 0) + free_irq(pdata->irq, pdev); + kfree(pdata); + return ret; +} + +static int __exit mxc_rtc_remove(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + rtc_device_unregister(pdata->rtc); + if (pdata->irq >= 0) + free_irq(pdata->irq, pdev); + + clk_disable(pdata->clk); + clk_put(pdata->clk); + kfree(pdata); + return 0; +} + +/*! + * This function is called to save the system time delta relative to + * the MXC RTC when enterring a low power state. This time delta is + * then used on resume to adjust the system time to account for time + * loss while suspended. + * + * @param pdev not used + * @param state Power state to enter. + * + * @return The function always returns 0. + */ +static int mxc_rtc_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + + if (device_may_wakeup(&pdev->dev)) { + enable_irq_wake(pdata->irq); + } else { + if (pdata->irq_enable) + disable_irq(pdata->irq); + } + + return 0; +} + +/*! + * This function is called to correct the system time based on the + * current MXC RTC time relative to the time delta saved during + * suspend. + * + * @param pdev not used + * + * @return The function always returns 0. + */ +static int mxc_rtc_resume(struct platform_device *pdev) +{ + struct rtc_drv_data *pdata = platform_get_drvdata(pdev); + + if (device_may_wakeup(&pdev->dev)) { + disable_irq_wake(pdata->irq); + } else { + if (pdata->irq_enable) + enable_irq(pdata->irq); + } + + return 0; +} + +/*! + * Contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_rtc_driver = { + .driver = { + .name = "mxc_rtc", + }, + .probe = mxc_rtc_probe, + .remove = __exit_p(mxc_rtc_remove), + .suspend = mxc_rtc_suspend, + .resume = mxc_rtc_resume, +}; + +/*! + * This function creates the /proc/driver/rtc file and registers the device RTC + * in the /dev/misc directory. It also reads the RTC value from external source + * and setup the internal RTC properly. + * + * @return -1 if RTC is failed to initialize; 0 is successful. + */ +static int __init mxc_rtc_init(void) +{ + return platform_driver_register(&mxc_rtc_driver); +} + +/*! + * This function removes the /proc/driver/rtc file and un-registers the + * device RTC from the /dev/misc directory. + */ +static void __exit mxc_rtc_exit(void) +{ + platform_driver_unregister(&mxc_rtc_driver); + +} + +module_init(mxc_rtc_init); +module_exit(mxc_rtc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Realtime Clock Driver (RTC)"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/rtc-mxs.c b/drivers/rtc/rtc-mxs.c new file mode 100644 index 000000000000..02fcfccd8e9d --- /dev/null +++ b/drivers/rtc/rtc-mxs.c @@ -0,0 +1,322 @@ +/* + * Freescale STMP37XX/STMP378X Real Time Clock driver + * + * Copyright (c) 2007 Sigmatel, Inc. + * Peter Hartley, + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct mxs_rtc_data { + struct rtc_device *rtc; + unsigned int base; + int irq_alarm; + int irq_sample; + unsigned irq_count; +}; + +/* Time read/write */ +static int mxs_rtc_gettime(struct device *pdev, struct rtc_time *rtc_tm) +{ + struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev); + + while (__raw_readl(rtc_data->base + HW_RTC_STAT) & + BF_RTC_STAT_STALE_REGS(0x80)) + cpu_relax(); + + rtc_time_to_tm(__raw_readl(rtc_data->base + HW_RTC_SECONDS), rtc_tm); + return 0; +} + +static int mxs_rtc_settime(struct device *pdev, struct rtc_time *rtc_tm) +{ + unsigned long t; + int rc = rtc_tm_to_time(rtc_tm, &t); + struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev); + + if (rc == 0) { + __raw_writel(t, rtc_data->base + HW_RTC_SECONDS); + + /* The datasheet doesn't say which way round the + * NEW_REGS/STALE_REGS bitfields go. In fact it's 0x1=P0, + * 0x2=P1, .., 0x20=P5, 0x40=ALARM, 0x80=SECONDS, + */ + while (__raw_readl(rtc_data->base + HW_RTC_STAT) & + BF_RTC_STAT_NEW_REGS(0x80)) + cpu_relax(); + } + return rc; +} + +static irqreturn_t mxs_rtc_interrupt(int irq, void *dev_id) +{ + struct mxs_rtc_data *rtc_data = dev_get_drvdata(dev_id); + u32 status; + u32 events = 0; + + status = __raw_readl(rtc_data->base + HW_RTC_CTRL) & + (BM_RTC_CTRL_ALARM_IRQ | BM_RTC_CTRL_ONEMSEC_IRQ); + if (status & BM_RTC_CTRL_ALARM_IRQ) { + __raw_writel(BM_RTC_CTRL_ALARM_IRQ, + rtc_data->base + HW_RTC_CTRL_CLR); + events |= RTC_AF | RTC_IRQF; + } + if (status & BM_RTC_CTRL_ONEMSEC_IRQ) { + __raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ, + rtc_data->base + HW_RTC_CTRL_CLR); + if (++rtc_data->irq_count % 1000 == 0) { + events |= RTC_UF | RTC_IRQF; + rtc_data->irq_count = 0; + } + } + + if (events) + rtc_update_irq(rtc_data->rtc, 1, events); + + return IRQ_HANDLED; +} + +static int mxs_rtc_open(struct device *pdev) +{ + int r; + struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev); + + r = request_irq(rtc_data->irq_alarm, mxs_rtc_interrupt, + IRQF_DISABLED, "RTC alarm", pdev); + if (r) { + dev_err(pdev, "Cannot claim IRQ%d\n", rtc_data->irq_alarm); + goto fail_1; + } + r = request_irq(rtc_data->irq_sample, mxs_rtc_interrupt, + IRQF_DISABLED, "RTC tick", pdev); + if (r) { + dev_err(pdev, "Cannot claim IRQ%d\n", rtc_data->irq_sample); + goto fail_2; + } + + return 0; +fail_2: + free_irq(rtc_data->irq_alarm, pdev); +fail_1: + return r; +} + +static void mxs_rtc_release(struct device *pdev) +{ + struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev); + + __raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN | BM_RTC_CTRL_ONEMSEC_IRQ_EN, + rtc_data->base + HW_RTC_CTRL_CLR); + free_irq(rtc_data->irq_alarm, pdev); + free_irq(rtc_data->irq_sample, pdev); +} + +static int mxs_rtc_ioctl(struct device *pdev, unsigned int cmd, + unsigned long arg) +{ + struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev); + + switch (cmd) { + case RTC_AIE_OFF: + __raw_writel(BM_RTC_PERSISTENT0_ALARM_EN | + BM_RTC_PERSISTENT0_ALARM_WAKE_EN, + rtc_data->base + HW_RTC_PERSISTENT0_CLR); + __raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN, + rtc_data->base + HW_RTC_CTRL_CLR); + break; + case RTC_AIE_ON: + __raw_writel(BM_RTC_PERSISTENT0_ALARM_EN | + BM_RTC_PERSISTENT0_ALARM_WAKE_EN, + rtc_data->base + HW_RTC_PERSISTENT0_SET); + + __raw_writel(BM_RTC_CTRL_ALARM_IRQ_EN, + rtc_data->base + HW_RTC_CTRL_SET); + break; + case RTC_UIE_ON: + rtc_data->irq_count = 0; + __raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ_EN, + rtc_data->base + HW_RTC_CTRL_SET); + break; + case RTC_UIE_OFF: + __raw_writel(BM_RTC_CTRL_ONEMSEC_IRQ_EN, + rtc_data->base + HW_RTC_CTRL_CLR); + break; + default: + return -ENOIOCTLCMD; + } + + return 0; +} +static int mxs_rtc_read_alarm(struct device *pdev, struct rtc_wkalrm *alm) +{ + u32 t; + struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev); + + t = __raw_readl(rtc_data->base + HW_RTC_ALARM); + rtc_time_to_tm(t, &alm->time); + return 0; +} + +static int mxs_rtc_set_alarm(struct device *pdev, struct rtc_wkalrm *alm) +{ + unsigned long t; + struct mxs_rtc_data *rtc_data = dev_get_drvdata(pdev); + + rtc_tm_to_time(&alm->time, &t); + __raw_writel(t, rtc_data->base + HW_RTC_ALARM); + return 0; +} + +static struct rtc_class_ops mxs_rtc_ops = { + .open = mxs_rtc_open, + .release = mxs_rtc_release, + .ioctl = mxs_rtc_ioctl, + .read_time = mxs_rtc_gettime, + .set_time = mxs_rtc_settime, + .read_alarm = mxs_rtc_read_alarm, + .set_alarm = mxs_rtc_set_alarm, +}; + +static int mxs_rtc_probe(struct platform_device *pdev) +{ + u32 hwversion; + u32 rtc_stat; + struct resource *res; + struct mxs_rtc_data *rtc_data; + + rtc_data = kzalloc(sizeof(*rtc_data), GFP_KERNEL); + + if (!rtc_data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + kfree(rtc_data); + return -ENODEV; + } + rtc_data->base = (unsigned int)IO_ADDRESS(res->start); + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + kfree(rtc_data); + return -ENODEV; + } + rtc_data->irq_alarm = res->start; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + if (res == NULL) { + kfree(rtc_data); + return -ENODEV; + } + rtc_data->irq_sample = res->start; + + __raw_writel(BM_RTC_PERSISTENT0_ALARM_EN | + BM_RTC_PERSISTENT0_ALARM_WAKE_EN | + BM_RTC_PERSISTENT0_ALARM_WAKE, + rtc_data->base + HW_RTC_PERSISTENT0_CLR); + + hwversion = __raw_readl(rtc_data->base + HW_RTC_VERSION); + rtc_stat = __raw_readl(rtc_data->base + HW_RTC_STAT); + printk(KERN_INFO "MXS RTC driver v1.0 hardware v%u.%u.%u\n", + (hwversion >> 24), + (hwversion >> 16) & 0xFF, + hwversion & 0xFFFF); + + rtc_data->rtc = rtc_device_register(pdev->name, &pdev->dev, + &mxs_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc_data->rtc)) { + kfree(rtc_data); + return PTR_ERR(rtc_data->rtc); + } + + platform_set_drvdata(pdev, rtc_data); + + device_init_wakeup(&pdev->dev, 1); + + return 0; +} + +static int mxs_rtc_remove(struct platform_device *dev) +{ + struct mxs_rtc_data *rtc_data = platform_get_drvdata(dev); + + if (rtc_data) { + rtc_device_unregister(rtc_data->rtc); + kfree(rtc_data); + } + + return 0; +} + +#ifdef CONFIG_PM +static int mxs_rtc_suspend(struct platform_device *dev, pm_message_t state) +{ + return 0; +} + +static int mxs_rtc_resume(struct platform_device *dev) +{ + struct mxs_rtc_data *rtc_data = platform_get_drvdata(dev); + + __raw_writel(BM_RTC_PERSISTENT0_ALARM_EN | + BM_RTC_PERSISTENT0_ALARM_WAKE_EN | + BM_RTC_PERSISTENT0_ALARM_WAKE, + rtc_data->base + HW_RTC_PERSISTENT0_CLR); + return 0; +} +#else +#define mxs_rtc_suspend NULL +#define mxs_rtc_resume NULL +#endif + +static struct platform_driver mxs_rtcdrv = { + .probe = mxs_rtc_probe, + .remove = mxs_rtc_remove, + .suspend = mxs_rtc_suspend, + .resume = mxs_rtc_resume, + .driver = { + .name = "mxs-rtc", + .owner = THIS_MODULE, + }, +}; + +static int __init mxs_rtc_init(void) +{ + return platform_driver_register(&mxs_rtcdrv); +} + +static void __exit mxs_rtc_exit(void) +{ + platform_driver_unregister(&mxs_rtcdrv); +} + +module_init(mxs_rtc_init); +module_exit(mxs_rtc_exit); + +MODULE_DESCRIPTION("MXS RTC Driver"); +MODULE_AUTHOR("dmitry pervushin "); +MODULE_LICENSE("GPL"); diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b23165bc5dc..17cbbd3e9408 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -304,6 +304,110 @@ config SERIAL_AMBA_PL010_CONSOLE your boot loader (lilo or loadlin) about how to pass options to the kernel at boot time.) +config SERIAL_MXC + tristate "MXC Internal serial port support" + depends on ARCH_MXC + select SERIAL_CORE + help + This selects the Freescale Semiconductor MXC Internal UART driver. + If unsure, say N. + +config SERIAL_MXC_CONSOLE + bool "Support for console on a MXC/MX27/MX21 Internal serial port" + depends on SERIAL_MXC=y + select SERIAL_CORE_CONSOLE + help + Say Y here if you wish to use an MXC Internal UART as the system + console (the system console is the device which receives all kernel + messages and warnings and which allows logins in single user mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttymxc". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_STMP_DBG + tristate "STMP debug serial port support" + depends on ARCH_STMP3XXX + select SERIAL_CORE + help + Driver for Sigmatel 36XX/37XX internal debug serial port + +config SERIAL_STMP_DBG_CONSOLE + bool "Support for console on STMP37XX DBG serial port" + depends on SERIAL_STMP_DBG=y + select SERIAL_CORE_CONSOLE + ---help--- + Say Y here if you wish to use the STMP36XX/37XX debug serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyAM0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + +config SERIAL_STMP_APP + tristate "STMP app serial port support" + depends on ARCH_STMP3XXX + select SERIAL_CORE + help + Driver for Sigmatel 36XX/37XX internal application serial port + +config SERIAL_MXS_DUART + tristate "i.MXS debug serial port support" + depends on ARCH_MXS + select SERIAL_CORE + help + Driver for Freescale i.MXS internal debug serial port + +config SERIAL_MXS_AUART + tristate "i.MXS Application serial port support" + depends on ARCH_MXS + select SERIAL_CORE + help + Driver for Freescale i.MXS internal application serial port + +config SERIAL_MXS_AUART_CONSOLE + bool "Support for console on i.MXS application serial port" + depends on SERIAL_MXS_AUART=y + select SERIAL_CORE_CONSOLE + ---help--- + Say Y here if you wish to use the i.MXS app serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttySP1". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + + +config SERIAL_MXS_DUART_CONSOLE + bool "Support for console on i.MXS debug serial port" + depends on SERIAL_MXS_DUART=y + select SERIAL_CORE_CONSOLE + ---help--- + Say Y here if you wish to use the i.MXS debug serial port as the + system console (the system console is the device which receives all + kernel messages and warnings and which allows logins in single user + mode). + + Even if you say Y here, the currently visible framebuffer console + (/dev/tty0) will still be used as the system console by default, but + you can alter that using a kernel command line option such as + "console=ttyAM0". (Try "man bootparam" or see the documentation of + your boot loader (lilo or loadlin) about how to pass options to the + kernel at boot time.) + config SERIAL_AMBA_PL011 tristate "ARM AMBA PL011 serial port support" depends on ARM_AMBA diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 208a85572c32..2ed31d54c6c6 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -75,6 +75,10 @@ obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o obj-$(CONFIG_SERIAL_MSM) += msm_serial.o obj-$(CONFIG_SERIAL_NETX) += netx-serial.o +obj-$(CONFIG_SERIAL_MXC) += mxc_uart.o +obj-$(CONFIG_SERIAL_MXC_CONSOLE) += mxc_uart_early.o +obj-$(CONFIG_SERIAL_MXS_DUART) += mxs-duart.o +obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o diff --git a/drivers/serial/mxc_uart.c b/drivers/serial/mxc_uart.c new file mode 100644 index 000000000000..347a7462c396 --- /dev/null +++ b/drivers/serial/mxc_uart.c @@ -0,0 +1,1957 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/serial/mxc_uart.c + * + * @brief Driver for the Freescale Semiconductor MXC serial ports based on + * drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * @ingroup UART + */ + +/* + * Include Files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SERIAL_MXC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif +#define SERIAL_MXC_MAJOR 207 +#define SERIAL_MXC_MINOR 16 +#define MXC_ISR_PASS_LIMIT 256 +#define UART_CREAD_BIT 256 + +#define MXC_UART_NR 8 + +/* IRDA minimum pulse duration in micro seconds */ +#define MIN_PULSE_DUR 2 +/* + * Transmit DMA buffer size is set to 1024 bytes, this is limited + * by UART_XMIT_SIZE. + */ +#define TXDMA_BUFF_SIZE UART_XMIT_SIZE +/* + * Receive DMA sub-buffer size + */ +#define RXDMA_BUFF_SIZE 128 + +/*! + * This structure is used to store the information for DMA data transfer. + */ +typedef struct { + /*! + * Holds the read channel number. + */ + int rd_channel; + /*! + * Holds the write channel number. + */ + int wr_channel; + /*! + * UART Transmit Event ID + */ + int tx_event_id; + /*! + * UART Receive Event ID + */ + int rx_event_id; + /*! + * DMA Transmit tasklet + */ + struct tasklet_struct dma_tx_tasklet; + /*! + * Flag indicates if the channel is in use + */ + int dma_txchnl_inuse; +} dma_info; + +/*! + * This is used to indicate if we want echo cancellation in the Irda mode. + */ +static int echo_cancel; +extern void gpio_uart_active(int port, int no_irda); +extern void gpio_uart_inactive(int port, int no_irda); +extern void config_uartdma_event(int port); + +static uart_mxc_port *mxc_ports[MXC_UART_NR]; + +/*! + * This array holds the DMA channel information for each MXC UART + */ +static dma_info dma_list[MXC_UART_NR]; + +/*! + * This function is called by the core driver to stop UART transmission. + * This might be due to the TTY layer indicating that the user wants to stop + * transmission. + * + * @param port the port structure for the UART passed in by the core + * driver + */ +static void mxcuart_stop_tx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1; + + cr1 = readl(port->membase + MXC_UARTUCR1); + /* Disable Transmitter rdy interrupt */ + if (umxc->dma_enabled == 1) { + cr1 &= ~MXC_UARTUCR1_TXDMAEN; + } else { + cr1 &= ~MXC_UARTUCR1_TRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * DMA Transmit tasklet method is scheduled on completion of a DMA transmit + * to send out any more data that is available in the UART xmit buffer. + * + * @param arg driver private data + */ +static void dma_tx_do_tasklet(unsigned long arg) +{ + uart_mxc_port *umxc = (uart_mxc_port *) arg; + struct circ_buf *xmit = &umxc->port.state->xmit; + mxc_dma_requestbuf_t writechnl_request; + int tx_num; + unsigned long flags; + + spin_lock_irqsave(&umxc->port.lock, flags); + tx_num = uart_circ_chars_pending(xmit); + if (tx_num > 0) { + if (xmit->tail > xmit->head) { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + UART_XMIT_SIZE - xmit->tail); + memcpy(umxc->tx_buf + (UART_XMIT_SIZE - xmit->tail), + xmit->buf, xmit->head); + } else { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, tx_num); + } + umxc->tx_handle = dma_map_single(umxc->port.dev, umxc->tx_buf, + TXDMA_BUFF_SIZE, + DMA_TO_DEVICE); + + writechnl_request.dst_addr = umxc->port.mapbase + MXC_UARTUTXD; + writechnl_request.src_addr = umxc->tx_handle; + writechnl_request.num_of_bytes = tx_num; + + if ((mxc_dma_config(dma_list[umxc->port.line].wr_channel, + &writechnl_request, 1, + MXC_DMA_MODE_WRITE)) == 0) { + mxc_dma_enable(dma_list[umxc->port.line].wr_channel); + } + } else { + /* No more data available in the xmit queue, clear the flag */ + dma_list[umxc->port.line].dma_txchnl_inuse = 0; + } + spin_unlock_irqrestore(&umxc->port.lock, flags); +} + +/*! + * DMA Write callback is called by the SDMA controller after it has sent out all + * the data from the user buffer. This function updates the xmit buffer pointers. + * + * @param arg driver private data + * @param error any DMA error + * @param count amount of data that was transferred + */ +static void mxcuart_dma_writecallback(void *arg, int error, unsigned int count) +{ + uart_mxc_port *umxc = arg; + struct circ_buf *xmit = &umxc->port.state->xmit; + int tx_num; + + if (error != MXC_DMA_TRANSFER_ERROR) { + tx_num = count; + umxc->port.icount.tx += tx_num; + xmit->tail = (xmit->tail + tx_num) & (UART_XMIT_SIZE - 1); + } + + dma_unmap_single(umxc->port.dev, umxc->tx_handle, TXDMA_BUFF_SIZE, + DMA_TO_DEVICE); + tx_num = uart_circ_chars_pending(xmit); + /* Schedule a tasklet to send out the pending characters */ + if (tx_num > 0) { + tasklet_schedule(&dma_list[umxc->port.line].dma_tx_tasklet); + } else { + dma_list[umxc->port.line].dma_txchnl_inuse = 0; + } + if (tx_num < WAKEUP_CHARS) { + uart_write_wakeup(&umxc->port); + } +} + +/*! + * This function is called by the core driver to start transmitting characters. + * This function enables the transmit interrupts. + * + * @param port the port structure for the UART passed in by the core + * driver + */ +static void mxcuart_start_tx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + struct circ_buf *xmit = &umxc->port.state->xmit; + volatile unsigned int cr1; + mxc_dma_requestbuf_t writechnl_request; + int tx_num; + + cr1 = readl(port->membase + MXC_UARTUCR1); + /* Enable Transmitter rdy interrupt */ + if (umxc->dma_enabled == 1) { + /* + * If the channel is in use then return immediately and use + * the dma_tx tasklet to transfer queued data when current DMA + * transfer is complete + */ + if (dma_list[umxc->port.line].dma_txchnl_inuse == 1) { + return; + } + tx_num = uart_circ_chars_pending(xmit); + if (tx_num > 0) { + dma_list[umxc->port.line].dma_txchnl_inuse = 1; + if (xmit->tail > xmit->head) { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + UART_XMIT_SIZE - xmit->tail); + memcpy(umxc->tx_buf + + (UART_XMIT_SIZE - xmit->tail), xmit->buf, + xmit->head); + } else { + memcpy(umxc->tx_buf, xmit->buf + xmit->tail, + tx_num); + } + umxc->tx_handle = + dma_map_single(umxc->port.dev, umxc->tx_buf, + TXDMA_BUFF_SIZE, DMA_TO_DEVICE); + + writechnl_request.dst_addr = + umxc->port.mapbase + MXC_UARTUTXD; + writechnl_request.src_addr = umxc->tx_handle; + writechnl_request.num_of_bytes = tx_num; + if ((mxc_dma_config + (dma_list[umxc->port.line].wr_channel, + &writechnl_request, 1, + MXC_DMA_MODE_WRITE)) == 0) { + mxc_dma_enable(dma_list[umxc->port.line]. + wr_channel); + } + cr1 |= MXC_UARTUCR1_TXDMAEN; + } + } else { + cr1 |= MXC_UARTUCR1_TRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * This function is called by the core driver to stop receiving characters; the + * port is in the process of being closed. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_stop_rx(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1; + + cr1 = readl(port->membase + MXC_UARTUCR1); + if (umxc->dma_enabled == 1) { + cr1 &= ~MXC_UARTUCR1_RXDMAEN; + } else { + cr1 &= ~MXC_UARTUCR1_RRDYEN; + } + writel(cr1, port->membase + MXC_UARTUCR1); +} + +/*! + * This function is called by the core driver to enable the modem status + * interrupts. If the port is configured to be in DTE mode then it enables the + * DCDDELT and RIDELT interrupts in addition to the DTRDEN interrupt. The RTSDEN + * interrupt is enabled only for interrupt-driven hardware flow control. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_enable_ms(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr1, cr3; + + /* + * RTS interrupt is enabled only if we are using interrupt-driven + * software controlled hardware flow control + */ + if (umxc->hardware_flow == 0) { + cr1 = readl(umxc->port.membase + MXC_UARTUCR1); + cr1 |= MXC_UARTUCR1_RTSDEN; + writel(cr1, umxc->port.membase + MXC_UARTUCR1); + } + cr3 = readl(umxc->port.membase + MXC_UARTUCR3); + cr3 |= MXC_UARTUCR3_DTRDEN; + if (umxc->mode == MODE_DTE) { + cr3 |= MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI; + } + writel(cr3, umxc->port.membase + MXC_UARTUCR3); +} + +/*! + * This function is called from the interrupt service routine if the status bit + * indicates that the receive fifo data level is above the set threshold. The + * function reads the character and queues them into the TTY layers read + * buffer. The function also looks for break characters, parity and framing + * errors in the received character and sets the appropriate flag in the TTY + * receive buffer. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_rx_chars(uart_mxc_port *umxc) +{ + volatile unsigned int ch, sr2; + unsigned int status, flag, max_count = 256; + + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + while (((sr2 & MXC_UARTUSR2_RDR) == 1) && (max_count-- > 0)) { + ch = readl(umxc->port.membase + MXC_UARTURXD); + + flag = TTY_NORMAL; + status = ch | UART_CREAD_BIT; + ch &= 0xFF; /* Clear the upper bits */ + umxc->port.icount.rx++; + + /* + * Check to see if there is an error in the received + * character. Perform the appropriate actions based on the + * error bit that was set. + */ + if (status & MXC_UARTURXD_ERR) { + if (status & MXC_UARTURXD_BRK) { + /* + * Clear the frame and parity error bits + * as these always get set on receiving a + * break character + */ + status &= ~(MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR); + umxc->port.icount.brk++; + if (uart_handle_break(&umxc->port)) { + goto ignore_char; + } + } else if (status & MXC_UARTURXD_FRMERR) { + umxc->port.icount.frame++; + } else if (status & MXC_UARTURXD_PRERR) { + umxc->port.icount.parity++; + } + if (status & MXC_UARTURXD_OVRRUN) { + umxc->port.icount.overrun++; + } + + status &= umxc->port.read_status_mask; + + if (status & MXC_UARTURXD_BRK) { + flag = TTY_BREAK; + } else if (status & MXC_UARTURXD_FRMERR) { + flag = TTY_FRAME; + } else if (status & MXC_UARTURXD_PRERR) { + flag = TTY_PARITY; + } + } + + if (uart_handle_sysrq_char(&umxc->port, ch)) { + goto ignore_char; + } + + uart_insert_char(&umxc->port, status, MXC_UARTURXD_OVRRUN, ch, + flag); + ignore_char: + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + } + tty_flip_buffer_push(umxc->port.state->port.tty); +} + +/*! + * This function is called from the interrupt service routine if the status bit + * indicates that the transmit fifo is emptied below its set threshold and + * requires data. The function pulls characters from the TTY layers write + * buffer and writes it out to the UART transmit fifo. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_tx_chars(uart_mxc_port *umxc) +{ + struct circ_buf *xmit = &umxc->port.state->xmit; + int count; + + /* + * Transmit the XON/XOFF character if required + */ + if (umxc->port.x_char) { + writel(umxc->port.x_char, umxc->port.membase + MXC_UARTUTXD); + umxc->port.icount.tx++; + umxc->port.x_char = 0; + return; + } + + /* + * Check to see if there is any data to be sent and that the + * port has not been currently stopped by anything. + */ + if (uart_circ_empty(xmit) || uart_tx_stopped(&umxc->port)) { + mxcuart_stop_tx(&umxc->port); + return; + } + + count = umxc->port.fifosize - umxc->tx_threshold; + do { + writel(xmit->buf[xmit->tail], + umxc->port.membase + MXC_UARTUTXD); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + umxc->port.icount.tx++; + if (uart_circ_empty(xmit)) { + break; + } + } while (--count > 0); + + /* + * Check to see if we have flushed enough characters to ask for more + * to be sent to us, if so, we notify the user space that we can + * accept more data + */ + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { + uart_write_wakeup(&umxc->port); + } + + if (uart_circ_empty(xmit)) { + mxcuart_stop_tx(&umxc->port); + } +} + +/*! + * This function is called from the interrupt service routine if there is a + * change in the modem signals. This function handles these signal changes and + * also clears the appropriate status register bits. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * @param sr1 contents of status register 1 + * @param sr2 contents of status register 2 + */ +static void mxcuart_modem_status(uart_mxc_port *umxc, unsigned int sr1, + unsigned int sr2) +{ + if (umxc->mode == MODE_DTE) { + if (sr2 & MXC_UARTUSR2_DCDDELT) { + uart_handle_dcd_change(&umxc->port, + !(sr2 & MXC_UARTUSR2_DCDIN)); + } + if (sr2 & MXC_UARTUSR2_RIDELT) { + umxc->port.icount.rng++; + } + } + if (sr1 & MXC_UARTUSR1_DTRD) { + umxc->port.icount.dsr++; + } + if ((umxc->hardware_flow == 0) && (sr1 & MXC_UARTUSR1_RTSD)) { + uart_handle_cts_change(&umxc->port, sr1 & MXC_UARTUSR1_RTSS); + } + + wake_up_interruptible(&umxc->port.state->port.delta_msr_wait); +} + +/*! + * Interrupt service routine registered to handle the muxed ANDed interrupts. + * This routine is registered only in the case where the UART interrupts are + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in \b include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + volatile unsigned int sr1, sr2, cr1, cr; + unsigned int pass_counter = MXC_ISR_PASS_LIMIT; + unsigned int term_cond = 0; + int handled = 0; + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + cr1 = readl(umxc->port.membase + MXC_UARTUCR1); + + do { + /* Clear the bits that triggered the interrupt */ + writel(sr1, umxc->port.membase + MXC_UARTUSR1); + writel(sr2, umxc->port.membase + MXC_UARTUSR2); + /* + * Read if there is data available + */ + if (sr2 & MXC_UARTUSR2_RDR) { + mxcuart_rx_chars(umxc); + } + + if ((sr1 & (MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD)) || + (sr2 & (MXC_UARTUSR2_DCDDELT | MXC_UARTUSR2_RIDELT))) { + mxcuart_modem_status(umxc, sr1, sr2); + } + + /* + * Send data if there is data to be sent + */ + if ((cr1 & MXC_UARTUCR1_TRDYEN) && (sr1 & MXC_UARTUSR1_TRDY)) { + /* Echo cancellation for IRDA Transmit chars */ + if (umxc->ir_mode == IRDA && echo_cancel) { + /* Disable the receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr &= ~MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Enable Transmit complete intr to reenable RX */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr |= MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + mxcuart_tx_chars(umxc); + } + + if (pass_counter-- == 0) { + break; + } + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + + /* Is the transmit complete to reenable the receiver? */ + if (umxc->ir_mode == IRDA && echo_cancel) { + if (sr2 & MXC_UARTUSR2_TXDC) { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr |= MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Disable the Transmit complete interrupt bit */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr &= ~MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + } + + /* + * If there is no data to send or receive and if there is no + * change in the modem status signals then quit the routine + */ + term_cond = sr1 & (MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD); + term_cond |= sr2 & (MXC_UARTUSR2_RDR | MXC_UARTUSR2_DCDDELT); + term_cond |= !(sr2 & MXC_UARTUSR2_TXFE); + } while (term_cond > 0); + + handled = 1; + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the transmit interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_tx_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + volatile unsigned int sr2, cr; + + /* Echo cancellation for IRDA Transmit chars */ + if (umxc->ir_mode == IRDA && echo_cancel) { + /* Disable the receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr &= ~MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Enable Transmit complete to reenable receiver */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr |= MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + + mxcuart_tx_chars(umxc); + + /* Is the transmit complete to reenable the receiver? */ + if (umxc->ir_mode == IRDA && echo_cancel) { + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + if (sr2 & MXC_UARTUSR2_TXDC) { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + cr |= MXC_UARTUCR2_RXEN; + writel(cr, umxc->port.membase + MXC_UARTUCR2); + /* Disable the Transmit complete interrupt bit */ + cr = readl(umxc->port.membase + MXC_UARTUCR4); + cr &= ~MXC_UARTUCR4_TCEN; + writel(cr, umxc->port.membase + MXC_UARTUCR4); + } + } + + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the receive interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_rx_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + + /* Clear the aging timer bit */ + writel(MXC_UARTUSR1_AGTIM, umxc->port.membase + MXC_UARTUSR1); + mxcuart_rx_chars(umxc); + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * Interrupt service routine registered to handle the master interrupts. This + * routine is registered only in the case where the UART interrupts are not + * muxed. + * + * @param irq the interrupt number + * @param dev_id driver private data + * + * @return The function returns \b IRQ_RETVAL(1) if interrupt was handled, + * returns \b IRQ_RETVAL(0) if the interrupt was not handled. + * \b IRQ_RETVAL is defined in include/linux/interrupt.h. + */ +static irqreturn_t mxcuart_mint_int(int irq, void *dev_id) +{ + uart_mxc_port *umxc = dev_id; + int handled = 0; + volatile unsigned int sr1, sr2; + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + /* Clear the modem status interrupt bits */ + writel(MXC_UARTUSR1_RTSD | MXC_UARTUSR1_DTRD, + umxc->port.membase + MXC_UARTUSR1); + writel(MXC_UARTUSR2_DCDDELT | MXC_UARTUSR2_RIDELT, + umxc->port.membase + MXC_UARTUSR2); + mxcuart_modem_status(umxc, sr1, sr2); + handled = 1; + + return IRQ_RETVAL(handled); +} + +/*! + * This function is called by the core driver to test whether the transmitter + * fifo and shift register for the UART port are empty. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns TIOCSER_TEMT if it is empty, else returns 0. + */ +static unsigned int mxcuart_tx_empty(struct uart_port *port) +{ + volatile unsigned int sr2; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + sr2 = readl(port->membase + MXC_UARTUSR2); + spin_unlock_irqrestore(&port->lock, flags); + + return sr2 & MXC_UARTUSR2_TXDC ? TIOCSER_TEMT : 0; +} + +/*! + * This function is called by the core driver to get the current status of the + * modem input signals. The state of the output signals is not collected. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns an integer that contains the ORed value of the + * status of all the modem input signals or error. + */ +static unsigned int mxcuart_get_mctrl(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + unsigned int result = 0; + volatile unsigned int sr1, sr2; + + sr1 = readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = readl(umxc->port.membase + MXC_UARTUSR2); + + if (sr1 & MXC_UARTUSR1_RTSS) { + result |= TIOCM_CTS; + } + if (umxc->mode == MODE_DTE) { + if (!(sr2 & MXC_UARTUSR2_DCDIN)) { + result |= TIOCM_CAR; + } + if (!(sr2 & MXC_UARTUSR2_RIIN)) { + result |= TIOCM_RI; + } + } + return result; +} + +/*! + * This function is called by the core driver to set the state of the modem + * control lines. + * + * @param port the port structure for the UART passed in by the core driver + * @param mctrl the state that the modem control lines should be changed to + */ +static void mxcuart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr2 = 0, cr3 = 0, uts = 0; + + cr2 = readl(port->membase + MXC_UARTUCR2); + cr3 = readl(port->membase + MXC_UARTUCR3); + uts = readl(port->membase + MXC_UARTUTS); + + if (mctrl & TIOCM_RTS) { + /* + * Return to hardware-driven hardware flow control if the + * option is enabled + */ + if (umxc->hardware_flow == 1) { + cr2 |= MXC_UARTUCR2_CTSC; + } else { + cr2 |= MXC_UARTUCR2_CTS; + cr2 &= ~MXC_UARTUCR2_CTSC; + } + } else { + cr2 &= ~(MXC_UARTUCR2_CTS | MXC_UARTUCR2_CTSC); + } + writel(cr2, port->membase + MXC_UARTUCR2); + + if (mctrl & TIOCM_DTR) { + cr3 |= MXC_UARTUCR3_DSR; + } else { + cr3 &= ~MXC_UARTUCR3_DSR; + } + writel(cr3, port->membase + MXC_UARTUCR3); + + if (mctrl & TIOCM_LOOP) { + if (umxc->ir_mode == IRDA) { + echo_cancel = 0; + } else { + uts |= MXC_UARTUTS_LOOP; + } + } else { + if (umxc->ir_mode == IRDA) { + echo_cancel = 1; + } else { + uts &= ~MXC_UARTUTS_LOOP; + } + } + writel(uts, port->membase + MXC_UARTUTS); +} + +/*! + * This function is called by the core driver to control the transmission of + * the break signal. If break_state is non-zero, the break signal is + * transmitted, the signal is terminated when another call is made with + * break_state set to 0. + * + * @param port the port structure for the UART passed in by the core + * driver + * @param break_state the requested state of the break signal + */ +static void mxcuart_break_ctl(struct uart_port *port, int break_state) +{ + volatile unsigned int cr1; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + cr1 = readl(port->membase + MXC_UARTUCR1); + if (break_state == -1) { + cr1 |= MXC_UARTUCR1_SNDBRK; + } else { + cr1 &= ~MXC_UARTUCR1_SNDBRK; + } + writel(cr1, port->membase + MXC_UARTUCR1); + spin_unlock_irqrestore(&port->lock, flags); +} + +/*! + * The read DMA callback, this method is called when the DMA buffer has received its + * data. This functions copies the data to the tty buffer and updates the tty buffer + * pointers. It also queues the DMA buffer back to the DMA system. + * + * @param arg driver private data + * @param error any DMA error + * @param cnt amount of data that was transferred + */ +static void mxcuart_dmaread_callback(void *arg, int error, unsigned int cnt) +{ + uart_mxc_port *umxc = arg; + struct tty_struct *tty = umxc->port.state->port.tty; + int buff_id, flip_cnt, num_bufs; + mxc_dma_requestbuf_t readchnl_request; + mxc_uart_rxdmamap *rx_buf_elem = NULL; + unsigned int sr1, sr2; + char flag; + + num_bufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + /* Clear the aging timer bit */ + writel(MXC_UARTUSR1_AGTIM, umxc->port.membase + MXC_UARTUSR1); + + buff_id = umxc->dma_rxbuf_id; + flag = TTY_NORMAL; + + umxc->dma_rxbuf_id += 1; + if (umxc->dma_rxbuf_id >= num_bufs) { + umxc->dma_rxbuf_id = 0; + } + + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + buff_id); + + if (error == MXC_DMA_TRANSFER_ERROR) { + + sr1 = __raw_readl(umxc->port.membase + MXC_UARTUSR1); + sr2 = __raw_readl(umxc->port.membase + MXC_UARTUSR2); + + if (sr2 & MXC_UARTUSR2_BRCD) { + umxc->port.icount.brk++; + if (uart_handle_break(&umxc->port)) { + goto drop_data; + } + } else if (sr1 & MXC_UARTUSR1_PARITYERR) { + umxc->port.icount.parity++; + } else if (sr1 & MXC_UARTUSR1_FRAMERR) { + umxc->port.icount.frame++; + } else if (sr2 & MXC_UARTUSR2_ORE) { + umxc->port.icount.overrun++; + + } + + if (umxc->port.read_status_mask & MXC_UARTURXD_BRK) { + if (sr2 & MXC_UARTUSR2_BRCD) + flag = TTY_BREAK; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_PRERR) { + if (sr1 & MXC_UARTUSR1_PARITYERR) + flag = TTY_PARITY; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_FRMERR) { + if (sr1 & MXC_UARTUSR1_FRAMERR) + flag = TTY_FRAME; + } else if (umxc->port.read_status_mask & MXC_UARTURXD_OVRRUN) { + if (sr2 & MXC_UARTUSR2_ORE) + flag = TTY_OVERRUN; + } +/* By default clearing all error bits in status reg */ + __raw_writel((MXC_UARTUSR2_BRCD | MXC_UARTUSR2_ORE), + umxc->port.membase + MXC_UARTUSR2); + __raw_writel((MXC_UARTUSR1_PARITYERR | MXC_UARTUSR1_FRAMERR), + umxc->port.membase + MXC_UARTUSR1); + } + + flip_cnt = tty_buffer_request_room(tty, cnt); + + /* Check for space availability in the TTY Flip buffer */ + if (flip_cnt <= 0) { + goto drop_data; + } + umxc->port.icount.rx += flip_cnt; + + tty_insert_flip_string(tty, rx_buf_elem->rx_buf, flip_cnt); + + if (flag != TTY_NORMAL) { + tty_insert_flip_char(tty, 0, flag); + } + + tty_flip_buffer_push(tty); + umxc->port.state->port.tty->real_raw = 1; + + drop_data: + readchnl_request.src_addr = umxc->port.mapbase; + readchnl_request.dst_addr = rx_buf_elem->rx_handle; + readchnl_request.num_of_bytes = RXDMA_BUFF_SIZE; + mxc_dma_config(dma_list[umxc->port.line].rd_channel, &readchnl_request, + 1, MXC_DMA_MODE_READ); + mxc_dma_enable(dma_list[umxc->port.line].rd_channel); +} + +/*! + * Allocates DMA read and write channels, creates DMA read and write buffers and + * sets the channel specific parameters. + * + * @param d_info the structure that holds all the DMA information for a + * particular MXC UART + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int mxcuart_initdma(dma_info *d_info, uart_mxc_port *umxc) +{ + int ret = 0, rxbufs, i, j; + mxc_dma_requestbuf_t *readchnl_reqelem; + mxc_uart_rxdmamap *rx_buf_elem; + + /* Request for the read and write channels */ + d_info->rd_channel = mxc_dma_request(umxc->dma_rx_id, "MXC UART Read"); + if (d_info->rd_channel < 0) { + printk(KERN_ERR "MXC UART: Cannot allocate DMA read channel\n"); + return -1; + } else { + d_info->wr_channel = + mxc_dma_request(umxc->dma_tx_id, "MXC UART Write"); + if (d_info->wr_channel < 0) { + mxc_dma_free(d_info->rd_channel); + printk(KERN_ERR + "MXC UART: Cannot allocate DMA write channel\n"); + return -1; + } + } + + /* Allocate the DMA Transmit Buffer */ + umxc->tx_buf = kmalloc(TXDMA_BUFF_SIZE, GFP_KERNEL); + if (umxc->tx_buf == NULL) { + ret = -1; + goto err_dma_tx_buff; + } + rxbufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + /* Allocate the DMA Virtual Receive Buffer */ + umxc->rx_dmamap = kmalloc(rxbufs * sizeof(mxc_uart_rxdmamap), GFP_KERNEL); + if (umxc->rx_dmamap == NULL) { + ret = -1; + goto err_dma_rx_buff; + } + + /* Allocate the DMA Receive Request structures */ + readchnl_reqelem = kmalloc(rxbufs * sizeof(mxc_dma_requestbuf_t), + GFP_KERNEL); + if (readchnl_reqelem == NULL) { + ret = -1; + goto err_request; + } + + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + rx_buf_elem->rx_buf = + dma_alloc_coherent(NULL, RXDMA_BUFF_SIZE, + &rx_buf_elem->rx_handle, GFP_DMA); + if (rx_buf_elem->rx_buf == NULL) { + for (j = 0; j < i; j++) { + rx_buf_elem = + (mxc_uart_rxdmamap *) (umxc->rx_dmamap + j); + dma_free_coherent(NULL, RXDMA_BUFF_SIZE, + rx_buf_elem->rx_buf, + rx_buf_elem->rx_handle); + } + ret = -1; + goto cleanup; + } + } + + umxc->dma_rxbuf_id = 0; + /* Setup the DMA read request structures */ + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + (readchnl_reqelem + i)->src_addr = umxc->port.mapbase; + (readchnl_reqelem + i)->dst_addr = rx_buf_elem->rx_handle; + (readchnl_reqelem + i)->num_of_bytes = RXDMA_BUFF_SIZE; + } + mxc_dma_config(d_info->rd_channel, readchnl_reqelem, rxbufs, + MXC_DMA_MODE_READ); + mxc_dma_callback_set(d_info->rd_channel, mxcuart_dmaread_callback, + umxc); + mxc_dma_callback_set(d_info->wr_channel, mxcuart_dma_writecallback, + umxc); + + /* Start the read channel */ + mxc_dma_enable(d_info->rd_channel); + kfree(readchnl_reqelem); + tasklet_init(&d_info->dma_tx_tasklet, dma_tx_do_tasklet, + (unsigned long)umxc); + d_info->dma_txchnl_inuse = 0; + return ret; + cleanup: + kfree(readchnl_reqelem); + err_request: + kfree(umxc->rx_dmamap); + err_dma_rx_buff: + kfree(umxc->tx_buf); + err_dma_tx_buff: + mxc_dma_free(d_info->rd_channel); + mxc_dma_free(d_info->wr_channel); + + return ret; +} + +/*! + * Stops DMA and frees the DMA resources + * + * @param d_info the structure that holds all the DMA information for a + * particular MXC UART + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_freedma(dma_info *d_info, uart_mxc_port *umxc) +{ + int i, rxbufs; + mxc_uart_rxdmamap *rx_buf_elem; + + rxbufs = umxc->dma_rxbuf_size / RXDMA_BUFF_SIZE; + + for (i = 0; i < rxbufs; i++) { + rx_buf_elem = (mxc_uart_rxdmamap *) (umxc->rx_dmamap + i); + dma_free_coherent(NULL, RXDMA_BUFF_SIZE, + rx_buf_elem->rx_buf, rx_buf_elem->rx_handle); + } + kfree(umxc->rx_dmamap); + kfree(umxc->tx_buf); + mxc_dma_free(d_info->rd_channel); + mxc_dma_free(d_info->wr_channel); +} + +/*! + * This function is called to free the interrupts. + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + */ +static void mxcuart_free_interrupts(uart_mxc_port *umxc) +{ + free_irq(umxc->port.irq, umxc); + if (umxc->ints_muxed == 0) { + free_irq(umxc->irqs[0], umxc); + free_irq(umxc->irqs[1], umxc); + } +} + +/*! + * Calculate and set the UART port clock value + * + * @param umxc the MXC UART port structure, this includes the \b uart_port + * structure and other members that are specific to MXC UARTs + * @param per_clk peripheral clock coming into the MXC UART module + * @param req_baud current baudrate requested + * @param div returns the reference frequency divider value + */ +static void mxcuart_set_ref_freq(uart_mxc_port *umxc, unsigned long per_clk, + unsigned int req_baud, int *div) +{ + unsigned int d = 1; + + /* + * Choose the smallest possible prescaler to maximize + * the chance of using integer scaling. Ensure that + * the calculation won't overflow. Limit the denom + * to 15 bits since a 16-bit denom doesn't work. + */ + if (req_baud < (1 << (31 - (4 + 15)))) + d = per_clk / (req_baud << (4 + 15)) + 1; + + umxc->port.uartclk = per_clk / d; + + /* + * Set the ONEMS register that is used by IR special case bit and + * the Escape character detect logic + */ + writel(umxc->port.uartclk / 1000, umxc->port.membase + MXC_UARTONEMS); + *div = d; +} + +/*! + * This function is called by the core driver to initialize the low-level + * driver. The function grabs the interrupt resources and registers its + * interrupt service routines. It then initializes the IOMUX registers to + * configure the pins for UART signals and finally initializes the various + * UART registers and enables the port for reception. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int mxcuart_startup(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + int retval; + volatile unsigned int cr, cr1 = 0, cr2 = 0, ufcr = 0; + + /* + * Some UARTs need separate registrations for the interrupts as + * they do not take the muxed interrupt output to the ARM core + */ + if (umxc->ints_muxed == 1) { + retval = request_irq(umxc->port.irq, mxcuart_int, 0, + "mxcintuart", umxc); + if (retval != 0) { + return retval; + } + } else { + retval = request_irq(umxc->port.irq, mxcuart_tx_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + return retval; + } else { + retval = request_irq(umxc->irqs[0], mxcuart_rx_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + free_irq(umxc->port.irq, umxc); + return retval; + } else { + retval = + request_irq(umxc->irqs[1], mxcuart_mint_int, + 0, "mxcintuart", umxc); + if (retval != 0) { + free_irq(umxc->port.irq, umxc); + free_irq(umxc->irqs[0], umxc); + return retval; + } + } + } + } + + /* Initialize the DMA if we need SDMA data transfer */ + if (umxc->dma_enabled == 1) { + retval = mxcuart_initdma(dma_list + umxc->port.line, umxc); + if (retval != 0) { + printk + (KERN_ERR + "MXC UART: Failed to initialize DMA for UART %d\n", + umxc->port.line); + mxcuart_free_interrupts(umxc); + return retval; + } + /* Configure the GPR register to receive SDMA events */ + config_uartdma_event(umxc->port.line); + } + + /* + * Clear Status Registers 1 and 2 + */ + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR1); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR2); + + /* Configure the IOMUX for the UART */ + gpio_uart_active(umxc->port.line, umxc->ir_mode); + + /* + * Set the transceiver invert bits if required + */ + if (umxc->ir_mode == IRDA) { + echo_cancel = 1; + writel(umxc->ir_rx_inv | MXC_UARTUCR4_IRSC, umxc->port.membase + + MXC_UARTUCR4); + writel(umxc->rxd_mux | umxc->ir_tx_inv, + umxc->port.membase + MXC_UARTUCR3); + } else { + writel(umxc->rxd_mux, umxc->port.membase + MXC_UARTUCR3); + } + + /* + * Initialize UCR1,2 and UFCR registers + */ + if (umxc->dma_enabled == 1) { + cr2 = (MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN); + } else { + cr2 = + (MXC_UARTUCR2_ATEN | MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN); + } + + writel(cr2, umxc->port.membase + MXC_UARTUCR2); + /* Wait till we are out of software reset */ + do { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + } while (!(cr & MXC_UARTUCR2_SRST)); + + if (umxc->mode == MODE_DTE) { + ufcr |= ((umxc->tx_threshold << MXC_UARTUFCR_TXTL_OFFSET) | + MXC_UARTUFCR_DCEDTE | MXC_UARTUFCR_RFDIV | umxc-> + rx_threshold); + } else { + ufcr |= ((umxc->tx_threshold << MXC_UARTUFCR_TXTL_OFFSET) | + MXC_UARTUFCR_RFDIV | umxc->rx_threshold); + } + writel(ufcr, umxc->port.membase + MXC_UARTUFCR); + + /* + * Finally enable the UART and the Receive interrupts + */ + if (umxc->ir_mode == IRDA) { + cr1 |= MXC_UARTUCR1_IREN; + } + if (umxc->dma_enabled == 1) { + cr1 |= (MXC_UARTUCR1_RXDMAEN | MXC_UARTUCR1_ATDMAEN | + MXC_UARTUCR1_UARTEN); + } else { + cr1 |= (MXC_UARTUCR1_RRDYEN | MXC_UARTUCR1_UARTEN); + } + writel(cr1, umxc->port.membase + MXC_UARTUCR1); + + return 0; +} + +/*! + * This function is called by the core driver for the low-level driver to free + * its resources. The function frees all its interrupts and disables the UART. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_shutdown(struct uart_port *port) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + + /* Disable the IOMUX for the UART */ + gpio_uart_inactive(umxc->port.line, umxc->ir_mode); + mxcuart_free_interrupts(umxc); + /* Disable all interrupts, port and break condition */ + writel(0, umxc->port.membase + MXC_UARTUCR1); + writel(0, umxc->port.membase + MXC_UARTUCR3); + if (umxc->dma_enabled == 1) { + mxcuart_freedma(dma_list + umxc->port.line, umxc); + } +} + +/*! + * This function is called by the core driver to change the UART parameters, + * including baudrate, word length, parity, stop bits. The function also updates + * the port structures mask registers to indicate the types of events the user is + * interested in receiving. + * + * @param port the port structure for the UART passed in by the core driver + * @param termios the desired termios settings + * @param old old termios + */ +static void mxcuart_set_termios(struct uart_port *port, + struct ktermios *termios, struct ktermios *old) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + volatile unsigned int cr4 = 0, cr2 = 0, ufcr; + u_int num, denom, baud; + u_int cr2_mask; /* Used to add the changes to CR2 */ + unsigned long flags, per_clk; + int div; + + cr2_mask = ~(MXC_UARTUCR2_IRTS | MXC_UARTUCR2_CTSC | MXC_UARTUCR2_PREN | + MXC_UARTUCR2_PROE | MXC_UARTUCR2_STPB | MXC_UARTUCR2_WS); + + per_clk = clk_get_rate(umxc->clk); + + /* + * Ask the core to get the baudrate, if requested baudrate is not + * between max and min, then either use the baudrate in old termios + * setting. If it's still invalid, we try 9600 baud. + */ + baud = uart_get_baud_rate(&umxc->port, termios, old, 0, per_clk / 16); + /* Set the Reference frequency divider */ + mxcuart_set_ref_freq(umxc, per_clk, baud, &div); + + /* Byte size, default is 8-bit mode */ + switch (termios->c_cflag & CSIZE) { + case CS7: + cr2 = 0; + break; + default: + cr2 = MXC_UARTUCR2_WS; + break; + } + /* Check to see if we need 2 Stop bits */ + if (termios->c_cflag & CSTOPB) { + cr2 |= MXC_UARTUCR2_STPB; + } + + /* Check to see if we need Parity checking */ + if (termios->c_cflag & PARENB) { + cr2 |= MXC_UARTUCR2_PREN; + if (termios->c_cflag & PARODD) { + cr2 |= MXC_UARTUCR2_PROE; + } + } + spin_lock_irqsave(&umxc->port.lock, flags); + + ufcr = readl(umxc->port.membase + MXC_UARTUFCR); + ufcr = (ufcr & (~MXC_UARTUFCR_RFDIV_MASK)) | + ((6 - div) << MXC_UARTUFCR_RFDIV_OFFSET); + writel(ufcr, umxc->port.membase + MXC_UARTUFCR); + + /* + * Update the per-port timeout + */ + uart_update_timeout(&umxc->port, termios->c_cflag, baud); + + umxc->port.read_status_mask = MXC_UARTURXD_OVRRUN; + /* + * Enable appropriate events to be passed to the TTY layer + */ + if (termios->c_iflag & INPCK) { + umxc->port.read_status_mask |= MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR; + } + if (termios->c_iflag & (BRKINT | PARMRK)) { + umxc->port.read_status_mask |= MXC_UARTURXD_BRK; + } + + /* + * Characters to ignore + */ + umxc->port.ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_FRMERR | + MXC_UARTURXD_PRERR; + } + if (termios->c_iflag & IGNBRK) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_BRK; + /* + * If we are ignoring parity and break indicators, + * ignore overruns too (for real raw support) + */ + if (termios->c_iflag & IGNPAR) { + umxc->port.ignore_status_mask |= MXC_UARTURXD_OVRRUN; + } + } + + /* + * Ignore all characters if CREAD is not set, still receive characters + * from the port, but throw them away. + */ + if ((termios->c_cflag & CREAD) == 0) { + umxc->port.ignore_status_mask |= UART_CREAD_BIT; + } + + /* Hardware flow control should controled by userspace */ + umxc->hardware_flow = (termios->c_cflag & CRTSCTS) ? 1 : 0; + + cr4 = readl(umxc->port.membase + MXC_UARTUCR4); + if (UART_ENABLE_MS(port, termios->c_cflag)) { + mxcuart_enable_ms(port); + if (umxc->hardware_flow == 1) { + cr4 = (cr4 & (~MXC_UARTUCR4_CTSTL_MASK)) | + (umxc->cts_threshold << MXC_UARTUCR4_CTSTL_OFFSET); + cr2 |= MXC_UARTUCR2_CTSC; + umxc->port.state->port.tty->hw_stopped = 0; + } else { + cr2 |= MXC_UARTUCR2_IRTS; + } + } else { + cr2 |= MXC_UARTUCR2_IRTS; + } + + /* Add Parity, character length and stop bits information */ + cr2 |= (readl(umxc->port.membase + MXC_UARTUCR2) & cr2_mask); + writel(cr2, umxc->port.membase + MXC_UARTUCR2); + /* + if (umxc->ir_mode == IRDA) { + ret = mxcuart_setir_special(baud); + if (ret == 0) { + cr4 &= ~MXC_UARTUCR4_IRSC; + } else { + cr4 |= MXC_UARTUCR4_IRSC; + } + } */ + writel(cr4, umxc->port.membase + MXC_UARTUCR4); + + /* + * Set baud rate + */ + + /* Use integer scaling, if possible. Limit the denom to 15 bits. */ + num = 0; + denom = (umxc->port.uartclk + 8 * baud) / (16 * baud) - 1; + + /* Use fractional scaling if needed to limit the max error to 0.5% */ + if (denom < 100) { + u64 n64 = (u64) 16 * 0x8000 * baud + (umxc->port.uartclk / 2); + do_div(n64, umxc->port.uartclk); + num = (u_int) n64 - 1; + denom = 0x7fff; + } + writel(num, umxc->port.membase + MXC_UARTUBIR); + writel(denom, umxc->port.membase + MXC_UARTUBMR); + + spin_unlock_irqrestore(&umxc->port.lock, flags); +} + +/*! + * This function is called by the core driver to know the UART type. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns a pointer to a string describing the UART port. + */ +static const char *mxcuart_type(struct uart_port *port) +{ + return port->type == PORT_IMX ? "Freescale i.MX" : NULL; +} + +/*! + * This function is called by the core driver to release the memory resources + * currently in use by the UART port. + * + * @param port the port structure for the UART passed in by the core driver + */ +static void mxcuart_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, SZ_4K); +} + +/*! + * This function is called by the core driver to request memory resources for + * the UART port. + * + * @param port the port structure for the UART passed in by the core driver + * + * @return The function returns \b -EBUSY on failure, else it returns 0. + */ +static int mxcuart_request_port(struct uart_port *port) +{ + struct platform_device *pdev = to_platform_device(port->dev); + struct resource *mmres; + void *ret; + + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mmres) + return -ENODEV; + + ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1, + "serial_mxc"); + + return ret ? 0 : -EBUSY; +} + +/*! + * This function is called by the core driver to perform any autoconfiguration + * steps required for the UART port. This function sets the port->type field. + * + * @param port the port structure for the UART passed in by the core driver + * @param flags bit mask of the required configuration + */ +static void mxcuart_config_port(struct uart_port *port, int flags) +{ + if ((flags & UART_CONFIG_TYPE) && (mxcuart_request_port(port) == 0)) { + port->type = PORT_IMX; + } +} + +/*! + * This function is called by the core driver to verify that the new serial + * port information contained within \a ser is suitable for this UART port type. + * The function checks to see if the UART port type specified by the user + * application while setting the UART port information matches what is stored + * in the define \b PORT_MXC found in the header file include/linux/serial_core.h + * + * @param port the port structure for the UART passed in by the core driver + * @param ser the new serial port information + * + * @return The function returns 0 on success or \b -EINVAL if the port type + * specified is not equal to \b PORT_MXC. + */ +static int mxcuart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) { + ret = -EINVAL; + } + return ret; +} + +/*! + * This function is used to send a high priority XON/XOFF character + * + * @param port the port structure for the UART passed in by the core driver + * @param ch the character to send + */ +static void mxcuart_send_xchar(struct uart_port *port, char ch) +{ + unsigned long flags; + + port->x_char = ch; + if (port->state->port.tty->hw_stopped) { + return; + } + + if (ch) { + spin_lock_irqsave(&port->lock, flags); + port->ops->start_tx(port); + spin_unlock_irqrestore(&port->lock, flags); + } +} + +/*! + * This function is used enable/disable the MXC UART clocks + * + * @param port the port structure for the UART passed in by the core driver + * @param state New PM state + * @param oldstate Current PM state + */ +static void +mxcuart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) +{ + uart_mxc_port *umxc = (uart_mxc_port *) port; + + if (state) + clk_disable(umxc->clk); + else + clk_enable(umxc->clk); +} + +/*! + * This structure contains the pointers to the control functions that are + * invoked by the core serial driver to access the UART hardware. The + * structure is passed to serial_core.c file during registration. + */ +static struct uart_ops mxc_ops = { + .tx_empty = mxcuart_tx_empty, + .set_mctrl = mxcuart_set_mctrl, + .get_mctrl = mxcuart_get_mctrl, + .stop_tx = mxcuart_stop_tx, + .start_tx = mxcuart_start_tx, + .stop_rx = mxcuart_stop_rx, + .enable_ms = mxcuart_enable_ms, + .break_ctl = mxcuart_break_ctl, + .startup = mxcuart_startup, + .shutdown = mxcuart_shutdown, + .set_termios = mxcuart_set_termios, + .type = mxcuart_type, + .pm = mxcuart_pm, + .release_port = mxcuart_release_port, + .request_port = mxcuart_request_port, + .config_port = mxcuart_config_port, + .verify_port = mxcuart_verify_port, + .send_xchar = mxcuart_send_xchar, +}; + +#ifdef CONFIG_SERIAL_MXC_CONSOLE + +/* + * Write out a character once the UART is ready + */ +static inline void mxcuart_console_write_char(struct uart_port *port, char ch) +{ + volatile unsigned int status; + + do { + status = readl(port->membase + MXC_UARTUSR1); + } while ((status & MXC_UARTUSR1_TRDY) == 0); + writel(ch, port->membase + MXC_UARTUTXD); +} + +/*! + * This function is called to write the console messages through the UART port. + * + * @param co the console structure + * @param s the log message to be written to the UART + * @param count length of the message + */ +static void mxcuart_console_write(struct console *co, const char *s, + u_int count) +{ + struct uart_port *port = &mxc_ports[co->index]->port; + volatile unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3; + int i; + + /* + * First save the control registers and then disable the interrupts + */ + oldcr1 = readl(port->membase + MXC_UARTUCR1); + oldcr2 = readl(port->membase + MXC_UARTUCR2); + oldcr3 = readl(port->membase + MXC_UARTUCR3); + cr2 = + oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN | + MXC_UARTUCR2_ESCI); + cr3 = + oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI | + MXC_UARTUCR3_DTRDEN); + writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1); + writel(cr2, port->membase + MXC_UARTUCR2); + writel(cr3, port->membase + MXC_UARTUCR3); + /* + * Do each character + */ + for (i = 0; i < count; i++) { + mxcuart_console_write_char(port, s[i]); + if (s[i] == '\n') { + mxcuart_console_write_char(port, '\r'); + } + } + /* + * Finally, wait for the transmitter to become empty + */ + do { + status = readl(port->membase + MXC_UARTUSR2); + } while (!(status & MXC_UARTUSR2_TXDC)); + + /* + * Restore the control registers + */ + writel(oldcr1, port->membase + MXC_UARTUCR1); + writel(oldcr2, port->membase + MXC_UARTUCR2); + writel(oldcr3, port->membase + MXC_UARTUCR3); +} + +/*! + * Initializes the UART port to be used to print console message with the + * options specified. If no options are specified, then the function + * initializes the UART with the default options of baudrate=115200, 8 bit + * word size, no parity, no flow control. + * + * @param co The console structure + * @param options Any console options passed in from the command line + * + * @return The function returns 0 on success or error. + */ +static int __init mxcuart_console_setup(struct console *co, char *options) +{ + uart_mxc_port *umxc; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + volatile unsigned int cr = 0; + + /* + * Check whether an invalid uart number had been specified, and if + * so, search for the first available port that does have console + * support + */ + if (co->index >= MXC_UART_NR) { + co->index = 0; + } + umxc = mxc_ports[co->index]; + + if (umxc == NULL) { + return -ENODEV; + } + + clk_enable(umxc->clk); + + /* initialize port.lock else oops */ + spin_lock_init(&umxc->port.lock); + + /* + * Initialize the UART registers + */ + writel(MXC_UARTUCR1_UARTEN, umxc->port.membase + MXC_UARTUCR1); + /* Enable the transmitter and do a software reset */ + writel(MXC_UARTUCR2_TXEN, umxc->port.membase + MXC_UARTUCR2); + /* Wait till we are out of software reset */ + do { + cr = readl(umxc->port.membase + MXC_UARTUCR2); + } while (!(cr & MXC_UARTUCR2_SRST)); + + writel(0x0, umxc->port.membase + MXC_UARTUCR3); + writel(0x0, umxc->port.membase + MXC_UARTUCR4); + /* Set TXTL to 2, RXTL to 1 and RFDIV to 2 */ + cr = 0x0800 | MXC_UARTUFCR_RFDIV | 0x1; + if (umxc->mode == MODE_DTE) { + cr |= MXC_UARTUFCR_DCEDTE; + } + writel(cr, umxc->port.membase + MXC_UARTUFCR); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR1); + writel(0xFFFF, umxc->port.membase + MXC_UARTUSR2); + + if (options != NULL) { + uart_parse_options(options, &baud, &parity, &bits, &flow); + } + gpio_uart_active(umxc->port.line, umxc->ir_mode); + return uart_set_options(&umxc->port, co, baud, parity, bits, flow); +} + +static struct uart_driver mxc_reg; + +/*! + * This structure contains the pointers to the UART console functions. It is + * passed as an argument when registering the console. + */ +static struct console mxc_console = { + .name = "ttymxc", + .write = mxcuart_console_write, + .device = uart_console_device, + .setup = mxcuart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &mxc_reg, +}; + +/*! + * This function registers the console callback functions with the kernel. + */ +static int __init mxcuart_console_init(void) +{ + register_console(&mxc_console); + return 0; +} + +console_initcall(mxcuart_console_init); + +static int __init find_port(struct uart_port *p) +{ + int line; + struct uart_port *port; + for (line = 0; line < MXC_UART_NR; line++) { + if (!mxc_ports[line]) + continue; + port = &mxc_ports[line]->port; + if (uart_match_port(p, port)) + return line; + } + return -ENODEV; +} + +int __init mxc_uart_start_console(struct uart_port *port, char *options) +{ + int line; + line = find_port(port); + if (line < 0) + return -ENODEV; + + add_preferred_console("ttymxc", line, options); + printk("Switching Console to ttymxc%d at %s 0x%lx (options '%s')\n", + line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port", + port->iotype == + UPIO_MEM ? (unsigned long)port->mapbase : (unsigned long)port-> + iobase, options); + + if (!(mxc_console.flags & CON_ENABLED)) { + mxc_console.flags &= ~CON_PRINTBUFFER; + register_console(&mxc_console); + } + return 0; +} + +#define MXC_CONSOLE (&mxc_console) +#else +#define MXC_CONSOLE NULL +#endif /* CONFIG_SERIAL_MXC_CONSOLE */ + +/*! + * This structure contains the information such as the name of the UART driver + * that appears in the /dev folder, major and minor numbers etc. This structure + * is passed to the serial_core.c file. + */ +static struct uart_driver mxc_reg = { + .owner = THIS_MODULE, + .driver_name = "ttymxc", + .dev_name = "ttymxc", + .major = SERIAL_MXC_MAJOR, + .minor = SERIAL_MXC_MINOR, + .nr = MXC_UART_NR, + .cons = MXC_CONSOLE, +}; + +/*! + * This function is called to put the UART in a low power state. Refer to the + * document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which UART + * to suspend + * @param state the power state the device is entering + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcuart_suspend(struct platform_device *pdev, pm_message_t state) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + if (umxc == NULL) + return 0; /* skip disabled ports */ + + if (umxc && umxc->port.flags & ASYNC_INITIALIZED) + uart_suspend_port(&mxc_reg, &umxc->port); + + if (umxc && umxc->port.flags & ASYNC_SUSPENDED) + umxc->port.state->port.tty->hw_stopped = 1; + + return 0; +} + +/*! + * This function is called to bring the UART back from a low power state. Refer + * to the document driver-model/driver.txt in the kernel source tree for more + * information. + * + * @param pdev the device structure used to give information on which UART + * to resume + * + * @return The function returns 0 on success and -1 on failure + */ +static int mxcuart_resume(struct platform_device *pdev) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + if (umxc == NULL) + return 0; /* skip disabled ports */ + + if (umxc && umxc->port.flags & ASYNC_SUSPENDED) { + umxc->port.state->port.tty->hw_stopped = 0; + uart_resume_port(&mxc_reg, &umxc->port); + } + + return 0; +} + +/*! + * This function is called during the driver binding process. Based on the UART + * that is being probed this function adds the appropriate UART port structure + * in the core driver. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions + * + * @return The function returns 0 if successful; -1 otherwise. + */ +static int mxcuart_probe(struct platform_device *pdev) +{ + int id = pdev->id; + struct resource *res; + void __iomem *base; + + mxc_ports[id] = pdev->dev.platform_data; + mxc_ports[id]->port.ops = &mxc_ops; + + /* Do not use UARTs that are disabled during integration */ + if (mxc_ports[id]->enabled == 1) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + base = ioremap(res->start, res->end - res->start + 1); + if (!base) + return -ENOMEM; + + mxc_ports[id]->port.membase = base; + mxc_ports[id]->port.mapbase = res->start; + mxc_ports[id]->port.dev = &pdev->dev; + mxc_ports[id]->port.irq = platform_get_irq(pdev, 0); + mxc_ports[id]->irqs[0] = platform_get_irq(pdev, 1); + mxc_ports[id]->irqs[1] = platform_get_irq(pdev, 2); + spin_lock_init(&mxc_ports[id]->port.lock); + /* Enable the low latency flag for DMA UART ports */ + if (mxc_ports[id]->dma_enabled == 1) { + mxc_ports[id]->port.flags |= ASYNC_LOW_LATENCY; + } + + mxc_ports[id]->clk = clk_get(&pdev->dev, NULL); + if (mxc_ports[id]->clk == NULL) + return -1; + + uart_add_one_port(&mxc_reg, &mxc_ports[id]->port); + platform_set_drvdata(pdev, mxc_ports[id]); + } + return 0; +} + +/*! + * Dissociates the driver from the UART device. Removes the appropriate UART + * port structure from the core driver. + * + * @param pdev the device structure used to give information on which UART + * to remove + * + * @return The function always returns 0. + */ +static int mxcuart_remove(struct platform_device *pdev) +{ + uart_mxc_port *umxc = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + if (umxc) { + uart_remove_one_port(&mxc_reg, &umxc->port); + iounmap(umxc->port.membase); + } + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcuart_driver = { + .driver = { + .name = "mxcintuart", + }, + .probe = mxcuart_probe, + .remove = mxcuart_remove, + .suspend = mxcuart_suspend, + .resume = mxcuart_resume, +}; + +/*! + * This function is used to initialize the UART driver module. The function + * registers the power management callback functions with the kernel and also + * registers the UART callback functions with the core serial driver. + * + * @return The function returns 0 on success and a non-zero value on failure. + */ +static int __init mxcuart_init(void) +{ + int ret = 0; + + printk(KERN_INFO "Serial: MXC Internal UART driver\n"); + ret = uart_register_driver(&mxc_reg); + if (ret == 0) { + /* Register the device driver structure. */ + ret = platform_driver_register(&mxcuart_driver); + if (ret != 0) { + uart_unregister_driver(&mxc_reg); + } + } + return ret; +} + +/*! + * This function is used to cleanup all resources before the driver exits. + */ +static void __exit mxcuart_exit(void) +{ + platform_driver_unregister(&mxcuart_driver); + uart_unregister_driver(&mxc_reg); +} + +module_init(mxcuart_init); +module_exit(mxcuart_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC serial port driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/serial/mxc_uart_early.c b/drivers/serial/mxc_uart_early.c new file mode 100644 index 000000000000..f4b6493a9a64 --- /dev/null +++ b/drivers/serial/mxc_uart_early.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file drivers/serial/mxc_uart_early.c + * + * @brief Driver for the Freescale Semiconductor MXC serial ports based on + * drivers/char/8250_early.c, Copyright 2004 Hewlett-Packard Development Company, + * L.P. by Bjorn Helgaasby. + * + * Early serial console for MXC UARTS. + * + * This is for use before the serial driver has initialized, in + * particular, before the UARTs have been discovered and named. + * Instead of specifying the console device as, e.g., "ttymxc0", + * we locate the device directly by its MMIO or I/O port address. + * + * The user can specify the device directly, e.g., + * console=mxcuart,0x43f90000,115200n8 + * or platform code can call early_uart_console_init() to set + * the early UART device. + * + * After the normal serial driver starts, we try to locate the + * matching ttymxc device and start a console there. + */ + +/* + * Include Files + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct mxc_early_uart_device { + struct uart_port port; + char options[16]; /* e.g., 115200n8 */ + unsigned int baud; + struct clk *clk; +}; +static struct mxc_early_uart_device mxc_early_device __initdata; + +/* + * Write out a character once the UART is ready + */ +static void __init mxcuart_console_write_char(struct uart_port *port, int ch) +{ + unsigned int status; + + do { + status = readl(port->membase + MXC_UARTUSR2); + } while ((status & MXC_UARTUSR2_TXFE) == 0); + writel(ch, port->membase + MXC_UARTUTXD); +} + +/*! + * This function is called to write the console messages through the UART port. + * + * @param co the console structure + * @param s the log message to be written to the UART + * @param count length of the message + */ +void __init early_mxcuart_console_write(struct console *co, const char *s, + u_int count) +{ + struct uart_port *port = &mxc_early_device.port; + volatile unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3; + + /* + * First save the control registers and then disable the interrupts + */ + oldcr1 = readl(port->membase + MXC_UARTUCR1); + oldcr2 = readl(port->membase + MXC_UARTUCR2); + oldcr3 = readl(port->membase + MXC_UARTUCR3); + cr2 = + oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN | + MXC_UARTUCR2_ESCI); + cr3 = + oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI | + MXC_UARTUCR3_DTRDEN); + writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1); + writel(cr2, port->membase + MXC_UARTUCR2); + writel(cr3, port->membase + MXC_UARTUCR3); + + /* Transmit string */ + uart_console_write(port, s, count, mxcuart_console_write_char); + + /* + * Finally, wait for the transmitter to become empty + */ + do { + status = readl(port->membase + MXC_UARTUSR2); + } while (!(status & MXC_UARTUSR2_TXDC)); + + /* + * Restore the control registers + */ + writel(oldcr1, port->membase + MXC_UARTUCR1); + writel(oldcr2, port->membase + MXC_UARTUCR2); + writel(oldcr3, port->membase + MXC_UARTUCR3); +} + +static unsigned int __init probe_baud(struct uart_port *port) +{ + /* FIXME Return Default Baud Rate */ + return 115200; +} + +static int __init mxc_early_uart_setup(struct console *console, char *options) +{ + struct mxc_early_uart_device *device = &mxc_early_device; + struct uart_port *port = &device->port; + int length; + + if (device->port.membase || device->port.iobase) + return -ENODEV; + + /* Enable Early MXC UART Clock */ + clk_enable(device->clk); + + port->uartclk = 5600000; + port->iotype = UPIO_MEM; + port->membase = ioremap(port->mapbase, SZ_4K); + + if (options) { + device->baud = simple_strtoul(options, NULL, 0); + length = min(strlen(options), sizeof(device->options)); + strncpy(device->options, options, length); + } else { + device->baud = probe_baud(port); + snprintf(device->options, sizeof(device->options), "%u", + device->baud); + } + printk(KERN_INFO + "MXC_Early serial console at MMIO 0x%x (options '%s')\n", + port->mapbase, device->options); + return 0; +} + +static struct console mxc_early_uart_console __initdata = { + .name = "ttymxc", + .write = early_mxcuart_console_write, + .setup = mxc_early_uart_setup, + .flags = CON_PRINTBUFFER | CON_BOOT, + .index = -1, +}; + +int __init mxc_early_serial_console_init(unsigned long base, struct clk *clk) +{ + mxc_early_device.clk = clk; + mxc_early_device.port.mapbase = base; + + register_console(&mxc_early_uart_console); + return 0; +} + +int __init mxc_early_uart_console_disable(void) +{ + struct mxc_early_uart_device *device = &mxc_early_device; + struct uart_port *port = &device->port; + + if (mxc_early_uart_console.index >= 0) { + iounmap(port->membase); + clk_disable(device->clk); + clk_put(device->clk); + } + return 0; +} +late_initcall(mxc_early_uart_console_disable); diff --git a/drivers/serial/mxc_uart_reg.h b/drivers/serial/mxc_uart_reg.h new file mode 100644 index 000000000000..dcdcbdb476c1 --- /dev/null +++ b/drivers/serial/mxc_uart_reg.h @@ -0,0 +1,128 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXC_UART_REG_H__ +#define __MXC_UART_REG_H__ + +/* Address offsets of the UART registers */ +#define MXC_UARTURXD 0x000 /* Receive reg */ +#define MXC_UARTUTXD 0x040 /* Transmitter reg */ +#define MXC_UARTUCR1 0x080 /* Control reg 1 */ +#define MXC_UARTUCR2 0x084 /* Control reg 2 */ +#define MXC_UARTUCR3 0x088 /* Control reg 3 */ +#define MXC_UARTUCR4 0x08C /* Control reg 4 */ +#define MXC_UARTUFCR 0x090 /* FIFO control reg */ +#define MXC_UARTUSR1 0x094 /* Status reg 1 */ +#define MXC_UARTUSR2 0x098 /* Status reg 2 */ +#define MXC_UARTUESC 0x09C /* Escape character reg */ +#define MXC_UARTUTIM 0x0A0 /* Escape timer reg */ +#define MXC_UARTUBIR 0x0A4 /* BRM incremental reg */ +#define MXC_UARTUBMR 0x0A8 /* BRM modulator reg */ +#define MXC_UARTUBRC 0x0AC /* Baud rate count reg */ +#define MXC_UARTONEMS 0x0B0 /* One millisecond reg */ +#define MXC_UARTUTS 0x0B4 /* Test reg */ + +/* Bit definations of UCR1 */ +#define MXC_UARTUCR1_ADEN 0x8000 +#define MXC_UARTUCR1_ADBR 0x4000 +#define MXC_UARTUCR1_TRDYEN 0x2000 +#define MXC_UARTUCR1_IDEN 0x1000 +#define MXC_UARTUCR1_RRDYEN 0x0200 +#define MXC_UARTUCR1_RXDMAEN 0x0100 +#define MXC_UARTUCR1_IREN 0x0080 +#define MXC_UARTUCR1_TXMPTYEN 0x0040 +#define MXC_UARTUCR1_RTSDEN 0x0020 +#define MXC_UARTUCR1_SNDBRK 0x0010 +#define MXC_UARTUCR1_TXDMAEN 0x0008 +#define MXC_UARTUCR1_ATDMAEN 0x0004 +#define MXC_UARTUCR1_DOZE 0x0002 +#define MXC_UARTUCR1_UARTEN 0x0001 + +/* Bit definations of UCR2 */ +#define MXC_UARTUCR2_ESCI 0x8000 +#define MXC_UARTUCR2_IRTS 0x4000 +#define MXC_UARTUCR2_CTSC 0x2000 +#define MXC_UARTUCR2_CTS 0x1000 +#define MXC_UARTUCR2_PREN 0x0100 +#define MXC_UARTUCR2_PROE 0x0080 +#define MXC_UARTUCR2_STPB 0x0040 +#define MXC_UARTUCR2_WS 0x0020 +#define MXC_UARTUCR2_RTSEN 0x0010 +#define MXC_UARTUCR2_ATEN 0x0008 +#define MXC_UARTUCR2_TXEN 0x0004 +#define MXC_UARTUCR2_RXEN 0x0002 +#define MXC_UARTUCR2_SRST 0x0001 + +/* Bit definations of UCR3 */ +#define MXC_UARTUCR3_DTREN 0x2000 +#define MXC_UARTUCR3_PARERREN 0x1000 +#define MXC_UARTUCR3_FRAERREN 0x0800 +#define MXC_UARTUCR3_DSR 0x0400 +#define MXC_UARTUCR3_DCD 0x0200 +#define MXC_UARTUCR3_RI 0x0100 +#define MXC_UARTUCR3_RXDSEN 0x0040 +#define MXC_UARTUCR3_AWAKEN 0x0010 +#define MXC_UARTUCR3_DTRDEN 0x0008 +#define MXC_UARTUCR3_RXDMUXSEL 0x0004 +#define MXC_UARTUCR3_INVT 0x0002 + +/* Bit definations of UCR4 */ +#define MXC_UARTUCR4_CTSTL_OFFSET 10 +#define MXC_UARTUCR4_CTSTL_MASK (0x3F << 10) +#define MXC_UARTUCR4_INVR 0x0200 +#define MXC_UARTUCR4_ENIRI 0x0100 +#define MXC_UARTUCR4_REF16 0x0040 +#define MXC_UARTUCR4_IRSC 0x0020 +#define MXC_UARTUCR4_TCEN 0x0008 +#define MXC_UARTUCR4_OREN 0x0002 +#define MXC_UARTUCR4_DREN 0x0001 + +/* Bit definations of UFCR */ +#define MXC_UARTUFCR_RFDIV 0x0200 /* Ref freq div is set to 2 */ +#define MXC_UARTUFCR_RFDIV_OFFSET 7 +#define MXC_UARTUFCR_RFDIV_MASK (0x7 << 7) +#define MXC_UARTUFCR_TXTL_OFFSET 10 +#define MXC_UARTUFCR_DCEDTE 0x0040 + +/* Bit definations of URXD */ +#define MXC_UARTURXD_ERR 0x4000 +#define MXC_UARTURXD_OVRRUN 0x2000 +#define MXC_UARTURXD_FRMERR 0x1000 +#define MXC_UARTURXD_BRK 0x0800 +#define MXC_UARTURXD_PRERR 0x0400 + +/* Bit definations of USR1 */ +#define MXC_UARTUSR1_PARITYERR 0x8000 +#define MXC_UARTUSR1_RTSS 0x4000 +#define MXC_UARTUSR1_TRDY 0x2000 +#define MXC_UARTUSR1_RTSD 0x1000 +#define MXC_UARTUSR1_FRAMERR 0x0400 +#define MXC_UARTUSR1_RRDY 0x0200 +#define MXC_UARTUSR1_AGTIM 0x0100 +#define MXC_UARTUSR1_DTRD 0x0080 +#define MXC_UARTUSR1_AWAKE 0x0010 + +/* Bit definations of USR2 */ +#define MXC_UARTUSR2_TXFE 0x4000 +#define MXC_UARTUSR2_IDLE 0x1000 +#define MXC_UARTUSR2_RIDELT 0x0400 +#define MXC_UARTUSR2_RIIN 0x0200 +#define MXC_UARTUSR2_DCDDELT 0x0040 +#define MXC_UARTUSR2_DCDIN 0x0020 +#define MXC_UARTUSR2_TXDC 0x0008 +#define MXC_UARTUSR2_ORE 0x0002 +#define MXC_UARTUSR2_RDR 0x0001 + +/* Bit definations of UTS */ +#define MXC_UARTUTS_LOOP 0x1000 + +#endif /* __MXC_UART_REG_H__ */ diff --git a/drivers/serial/mxs-auart.c b/drivers/serial/mxs-auart.c new file mode 100644 index 000000000000..be79f0e8bf11 --- /dev/null +++ b/drivers/serial/mxs-auart.c @@ -0,0 +1,1108 @@ +/* + * Freescale STMP37XX/STMP378X Application UART driver + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include "regs-uartapp.h" + +#define MXS_AUART_MAJOR 242 +#define MXS_AUART_RX_THRESHOLD 16 + +static struct uart_driver auart_driver; + +struct mxs_auart_port { + struct uart_port port; + + unsigned int flags; +#define MXS_AUART_PORT_OPEN 0x80000000 +#define MXS_AUART_PORT_DMA_MODE 0x80000000 + unsigned int ctrl; + + unsigned int irq[3]; + + struct clk *clk; + struct device *dev; + unsigned int dma_rx_chan; + unsigned int dma_tx_chan; + unsigned int dma_rx_buffer_size; + struct list_head rx_done; + struct list_head free; + struct mxs_dma_desc *tx; + struct tasklet_struct rx_task; +}; + +static void mxs_auart_stop_tx(struct uart_port *u); +static void mxs_auart_submit_tx(struct mxs_auart_port *s, int size); +static void mxs_auart_submit_rx(struct mxs_auart_port *s); + +static inline struct mxs_auart_port *to_auart_port(struct uart_port *u) +{ + return container_of(u, struct mxs_auart_port, port); +} + +static inline void mxs_auart_tx_chars(struct mxs_auart_port *s) +{ + struct circ_buf *xmit = &s->port.state->xmit; + + if (s->flags & MXS_AUART_PORT_DMA_MODE) { + int i = 0, size; + char *buffer = s->tx->buffer; + + if (mxs_dma_desc_pending(s->tx)) + return; + while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { + if (i >= PAGE_SIZE) + break; + if (s->port.x_char) { + buffer[i++] = s->port.x_char; + s->port.x_char = 0; + continue; + } + size = min_t(u32, PAGE_SIZE - i, + CIRC_CNT_TO_END(xmit->head, + xmit->tail, + UART_XMIT_SIZE)); + memcpy(buffer + i, xmit->buf + xmit->tail, size); + xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&s->port); + i += size; + } + if (i) + mxs_auart_submit_tx(s, i); + else { + if (uart_tx_stopped(&s->port)) + mxs_auart_stop_tx(&s->port); + } + return; + } + + while (!(__raw_readl(s->port.membase + HW_UARTAPP_STAT) & + BM_UARTAPP_STAT_TXFF)) { + if (s->port.x_char) { + __raw_writel(s->port.x_char, + s->port.membase + HW_UARTAPP_DATA); + s->port.x_char = 0; + continue; + } + if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { + __raw_writel(xmit->buf[xmit->tail], + s->port.membase + HW_UARTAPP_DATA); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&s->port); + } else + break; + } + if (uart_circ_empty(&(s->port.state->xmit))) + __raw_writel(BM_UARTAPP_INTR_TXIEN, + s->port.membase + HW_UARTAPP_INTR_CLR); + else + __raw_writel(BM_UARTAPP_INTR_TXIEN, + s->port.membase + HW_UARTAPP_INTR_SET); + + if (uart_tx_stopped(&s->port)) + mxs_auart_stop_tx(&s->port); +} + +static inline unsigned int +mxs_auart_rx_char(struct mxs_auart_port *s, unsigned int stat, u8 c) +{ + int flag; + + flag = TTY_NORMAL; + if (stat & BM_UARTAPP_STAT_BERR) { + stat &= ~BM_UARTAPP_STAT_BERR; + s->port.icount.brk++; + if (uart_handle_break(&s->port)) + return stat; + flag = TTY_BREAK; + } else if (stat & BM_UARTAPP_STAT_PERR) { + stat &= ~BM_UARTAPP_STAT_PERR; + s->port.icount.parity++; + flag = TTY_PARITY; + } else if (stat & BM_UARTAPP_STAT_FERR) { + stat &= ~BM_UARTAPP_STAT_FERR; + s->port.icount.frame++; + flag = TTY_FRAME; + } + + if (stat & BM_UARTAPP_STAT_OERR) + s->port.icount.overrun++; + + if (uart_handle_sysrq_char(&s->port, c)) + return stat; + + uart_insert_char(&s->port, stat, BM_UARTAPP_STAT_OERR, c, flag); + return stat; +} + +static void mxs_auart_rx_chars(struct mxs_auart_port *s) +{ + u8 c; + struct tty_struct *tty = s->port.state->port.tty; + u32 stat = 0; + + if (s->flags & MXS_AUART_PORT_DMA_MODE) { + int i, count; + struct list_head *p, *q; + LIST_HEAD(list); + struct mxs_dma_desc *pdesc; + mxs_dma_cooked(s->dma_rx_chan, &list); + stat = __raw_readl(s->port.membase + HW_UARTAPP_STAT); + list_for_each_safe(p, q, &list) { + u8 *buffer; + list_del(p); + pdesc = list_entry(p, struct mxs_dma_desc, node); + count = stat & BM_UARTAPP_STAT_RXCOUNT; + buffer = pdesc->buffer; + for (i = 0; i < count; i++) + stat = mxs_auart_rx_char(s, stat, buffer[i]); + list_add(p, &s->free); + stat = __raw_readl(s->port.membase + HW_UARTAPP_STAT); + } + mxs_auart_submit_rx(s); + goto out; + } + for (;;) { + stat = __raw_readl(s->port.membase + HW_UARTAPP_STAT); + if (stat & BM_UARTAPP_STAT_RXFE) + break; + c = __raw_readl(s->port.membase + HW_UARTAPP_DATA); + stat = mxs_auart_rx_char(s, stat, c); + __raw_writel(stat, s->port.membase + HW_UARTAPP_STAT); + } +out: + __raw_writel(stat, s->port.membase + HW_UARTAPP_STAT); + tty_flip_buffer_push(tty); +} + +/* Allocate and initialize rx and tx DMA chains */ +static int mxs_auart_dma_init(struct mxs_auart_port *s) +{ + int ret, i; + struct list_head *p, *n; + struct mxs_dma_desc *pdesc; + + ret = mxs_dma_request(s->dma_rx_chan, s->dev, dev_name(s->dev)); + if (ret) + goto fail_get_dma_rx; + ret = mxs_dma_request(s->dma_tx_chan, s->dev, dev_name(s->dev)); + if (ret) + goto fail_get_dma_tx; + ret = -ENOMEM; + INIT_LIST_HEAD(&s->rx_done); + INIT_LIST_HEAD(&s->free); + s->tx = NULL; + + + for (i = 0; i < 5; i++) { + pdesc = mxs_dma_alloc_desc(); + if (pdesc == NULL || IS_ERR(pdesc)) + goto fail_alloc_desc; + + if (s->tx == NULL) { + pdesc->buffer = dma_alloc_coherent(s->dev, PAGE_SIZE, + &pdesc->cmd.address, + GFP_DMA); + if (pdesc->buffer == NULL) + goto fail_alloc_desc; + s->tx = pdesc; + } else { + pdesc->buffer = dma_alloc_coherent(s->dev, + s->dma_rx_buffer_size, + &pdesc->cmd.address, + GFP_DMA); + if (pdesc->buffer == NULL) + goto fail_alloc_desc; + list_add_tail(&pdesc->node, &s->free); + } + } + /* + Tell DMA to select UART. + Both DMA channels are shared between app UART and IrDA. + Target id of 0 means UART, 1 means IrDA + */ + mxs_dma_set_target(s->dma_rx_chan, 0); + mxs_dma_set_target(s->dma_tx_chan, 0); + + mxs_dma_enable_irq(s->dma_rx_chan, 1); + mxs_dma_enable_irq(s->dma_tx_chan, 1); + + return 0; +fail_alloc_desc: + if (s->tx) { + if (s->tx->buffer) + dma_free_coherent(s->dev, + PAGE_SIZE, + s->tx->buffer, + s->tx->cmd.address); + s->tx->buffer = NULL; + mxs_dma_free_desc(s->tx); + s->tx = NULL; + } + list_for_each_safe(p, n, &s->free) { + list_del(p); + pdesc = list_entry(p, struct mxs_dma_desc, node); + if (pdesc->buffer) + dma_free_coherent(s->dev, + s->dma_rx_buffer_size, + pdesc->buffer, + pdesc->cmd.address); + pdesc->buffer = NULL; + mxs_dma_free_desc(pdesc); + } + mxs_dma_release(s->dma_tx_chan, s->dev); +fail_get_dma_tx: + mxs_dma_release(s->dma_rx_chan, s->dev); +fail_get_dma_rx: + WARN_ON(ret); + return ret; +} + +static void mxs_auart_dma_exit(struct mxs_auart_port *s) +{ + struct list_head *p, *n; + LIST_HEAD(list); + struct mxs_dma_desc *pdesc; + + mxs_dma_enable_irq(s->dma_rx_chan, 0); + mxs_dma_enable_irq(s->dma_tx_chan, 0); + + mxs_dma_disable(s->dma_tx_chan); + mxs_dma_disable(s->dma_rx_chan); + + mxs_dma_get_cooked(s->dma_tx_chan, &list); + mxs_dma_get_cooked(s->dma_rx_chan, &s->free); + + mxs_dma_release(s->dma_tx_chan, s->dev); + mxs_dma_release(s->dma_rx_chan, s->dev); + + if (s->tx) { + if (s->tx->buffer) + dma_free_coherent(s->dev, + PAGE_SIZE, + s->tx->buffer, + s->tx->cmd.address); + s->tx->buffer = NULL; + mxs_dma_free_desc(s->tx); + s->tx = NULL; + } + list_for_each_safe(p, n, &s->free) { + list_del(p); + pdesc = list_entry(p, struct mxs_dma_desc, node); + if (pdesc->buffer) + dma_free_coherent(s->dev, + s->dma_rx_buffer_size, + pdesc->buffer, + pdesc->cmd.address); + pdesc->buffer = NULL; + mxs_dma_free_desc(pdesc); + } +} + +static void mxs_auart_submit_rx(struct mxs_auart_port *s) +{ + int ret; + unsigned int pio_value; + struct list_head *p, *n; + struct mxs_dma_desc *pdesc; + + pio_value = BM_UARTAPP_CTRL0_RXTO_ENABLE | + BF_UARTAPP_CTRL0_RXTIMEOUT(0x80) | + BF_UARTAPP_CTRL0_XFER_COUNT(s->dma_rx_buffer_size); + + list_for_each_safe(p, n, &s->free) { + list_del(p); + pdesc = list_entry(p, struct mxs_dma_desc, node); + pdesc->cmd.cmd.bits.bytes = s->dma_rx_buffer_size; + pdesc->cmd.cmd.bits.terminate_flush = 1; + pdesc->cmd.cmd.bits.pio_words = 1; + pdesc->cmd.cmd.bits.wait4end = 1; + pdesc->cmd.cmd.bits.dec_sem = 1; + pdesc->cmd.cmd.bits.irq = 1; + pdesc->cmd.cmd.bits.chain = 1; + pdesc->cmd.cmd.bits.command = DMA_WRITE; + pdesc->cmd.pio_words[0] = pio_value; + ret = mxs_dma_desc_append(s->dma_rx_chan, pdesc); + if (ret) + pr_info("%s append dma desc, %d\n", __func__, ret); + } + ret = mxs_dma_enable(s->dma_rx_chan); + if (ret) + pr_info("%s enable dma desc, %d\n", __func__, ret); +} + +static irqreturn_t mxs_auart_irq_dma_rx(int irq, void *context) +{ + struct mxs_auart_port *s = context; + + mxs_dma_ack_irq(s->dma_rx_chan); + mxs_auart_rx_chars(s); + return IRQ_HANDLED; +} + +static void mxs_auart_submit_tx(struct mxs_auart_port *s, int size) +{ + int ret; + struct mxs_dma_desc *d = s->tx; + + d->cmd.pio_words[0] = BF_UARTAPP_CTRL1_XFER_COUNT(size); + d->cmd.cmd.bits.bytes = size; + d->cmd.cmd.bits.pio_words = 1; + d->cmd.cmd.bits.wait4end = 1; + d->cmd.cmd.bits.dec_sem = 1; + d->cmd.cmd.bits.irq = 1; + d->cmd.cmd.bits.command = DMA_READ; + ret = mxs_dma_desc_append(s->dma_tx_chan, s->tx); + if (ret) + pr_info("append dma desc, %d\n", ret); + + ret = mxs_dma_enable(s->dma_tx_chan); + if (ret) + pr_info("enable dma desc, %d\n", ret); +} + +static irqreturn_t mxs_auart_irq_dma_tx(int irq, void *context) +{ + struct mxs_auart_port *s = context; + + LIST_HEAD(list); + mxs_dma_ack_irq(s->dma_tx_chan); + mxs_dma_cooked(s->dma_tx_chan, &list); + mxs_auart_tx_chars(s); + return IRQ_HANDLED; +} + +static int mxs_auart_request_port(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + if (!request_mem_region((u32)u->mapbase, SZ_4K, dev_name(s->dev))) + return -EBUSY; + return 0; + +} + +static int mxs_auart_verify_port(struct uart_port *u, + struct serial_struct *ser) +{ + if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) + return -EINVAL; + return 0; +} + +static void mxs_auart_config_port(struct uart_port *u, int flags) +{ +} + +static const char *mxs_auart_type(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + return dev_name(s->dev); +} + +static void mxs_auart_release_port(struct uart_port *u) +{ + release_mem_region(u->mapbase, SZ_4K); +} + +static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) +{ + struct mxs_auart_port *s = to_auart_port(u); + + u32 ctrl = __raw_readl(u->membase + HW_UARTAPP_CTRL2); + + ctrl &= ~BM_UARTAPP_CTRL2_RTS; + if (mctrl & TIOCM_RTS) + ctrl |= BM_UARTAPP_CTRL2_RTS; + s->ctrl = mctrl; + __raw_writel(ctrl, u->membase + HW_UARTAPP_CTRL2); +} + +static u32 mxs_auart_get_mctrl(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + u32 stat = __raw_readl(u->membase + HW_UARTAPP_STAT); + int ctrl2 = __raw_readl(u->membase + HW_UARTAPP_CTRL2); + u32 mctrl = s->ctrl; + + mctrl &= ~TIOCM_CTS; + if (stat & BM_UARTAPP_STAT_CTS) + mctrl |= TIOCM_CTS; + + if (ctrl2 & BM_UARTAPP_CTRL2_RTS) + mctrl |= TIOCM_RTS; + + return mctrl; +} + +static void mxs_auart_settermios(struct uart_port *u, + struct ktermios *termios, + struct ktermios *old) +{ + u32 bm, ctrl, ctrl2, div; + unsigned int cflag, baud; + + if (termios == NULL) { + printk(KERN_ERR "Empty ktermios setting:!\n"); + return; + } + + cflag = termios->c_cflag; + + ctrl = BM_UARTAPP_LINECTRL_FEN; + ctrl2 = __raw_readl(u->membase + HW_UARTAPP_CTRL2); + + /* byte size */ + switch (cflag & CSIZE) { + case CS5: + bm = 0; + break; + case CS6: + bm = 1; + break; + case CS7: + bm = 2; + break; + case CS8: + bm = 3; + break; + default: + return; + } + + ctrl |= BF_UARTAPP_LINECTRL_WLEN(bm); + + /* parity */ + if (cflag & PARENB) { + ctrl |= BM_UARTAPP_LINECTRL_PEN; + if ((cflag & PARODD) == 0) + ctrl |= BM_UARTAPP_LINECTRL_EPS; + } + + /* figure out the stop bits requested */ + if (cflag & CSTOPB) + ctrl |= BM_UARTAPP_LINECTRL_STP2; + + /* figure out the hardware flow control settings */ + if (cflag & CRTSCTS) + ctrl2 |= BM_UARTAPP_CTRL2_CTSEN /* | BM_UARTAPP_CTRL2_RTSEN */ ; + else + ctrl2 &= ~BM_UARTAPP_CTRL2_CTSEN; + + /* set baud rate */ + baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); + div = u->uartclk * 32 / baud; + ctrl |= BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(div & 0x3F); + ctrl |= BF_UARTAPP_LINECTRL_BAUD_DIVINT(div >> 6); + + if ((cflag & CREAD) != 0) + ctrl2 |= BM_UARTAPP_CTRL2_RXE; + + __raw_writel(ctrl, u->membase + HW_UARTAPP_LINECTRL); + __raw_writel(ctrl2, u->membase + HW_UARTAPP_CTRL2); +} + +static irqreturn_t mxs_auart_irq_handle(int irq, void *context) +{ + u32 istatus, istat; + struct mxs_auart_port *s = context; + u32 stat = __raw_readl(s->port.membase + HW_UARTAPP_STAT); + + istatus = istat = __raw_readl(s->port.membase + HW_UARTAPP_INTR); + + if (istat & BM_UARTAPP_INTR_CTSMIS) { + uart_handle_cts_change(&s->port, stat & BM_UARTAPP_STAT_CTS); + __raw_writel(BM_UARTAPP_INTR_CTSMIS, + s->port.membase + HW_UARTAPP_INTR_CLR); + istat &= ~BM_UARTAPP_INTR_CTSMIS; + } + if (istat & (BM_UARTAPP_INTR_RTIS | BM_UARTAPP_INTR_RXIS)) { + mxs_auart_rx_chars(s); + istat &= ~(BM_UARTAPP_INTR_RTIS | BM_UARTAPP_INTR_RXIS); + } + + if (istat & BM_UARTAPP_INTR_TXIS) { + mxs_auart_tx_chars(s); + istat &= ~BM_UARTAPP_INTR_TXIS; + } + /* modem status interrupt bits are undefined + after reset,and the hardware do not support + DSRMIS,DCDMIS and RIMIS bit,so we should ingore + them when they are pending. */ + if (istat & (BM_UARTAPP_INTR_ABDIS + | BM_UARTAPP_INTR_OEIS + | BM_UARTAPP_INTR_BEIS + | BM_UARTAPP_INTR_PEIS + | BM_UARTAPP_INTR_FEIS + | BM_UARTAPP_INTR_RTIS + | BM_UARTAPP_INTR_TXIS + | BM_UARTAPP_INTR_RXIS + | BM_UARTAPP_INTR_CTSMIS)) { + dev_info(s->dev, "Unhandled status %x\n", istat); + } + __raw_writel(istatus & (BM_UARTAPP_INTR_ABDIS + | BM_UARTAPP_INTR_OEIS + | BM_UARTAPP_INTR_BEIS + | BM_UARTAPP_INTR_PEIS + | BM_UARTAPP_INTR_FEIS + | BM_UARTAPP_INTR_RTIS + | BM_UARTAPP_INTR_TXIS + | BM_UARTAPP_INTR_RXIS + | BM_UARTAPP_INTR_DSRMIS + | BM_UARTAPP_INTR_DCDMIS + | BM_UARTAPP_INTR_CTSMIS + | BM_UARTAPP_INTR_RIMIS), + s->port.membase + HW_UARTAPP_INTR_CLR); + + return IRQ_HANDLED; +} + +static int mxs_auart_free_irqs(struct mxs_auart_port *s) +{ + int irqn = 0; + + for (irqn = 0; irqn < ARRAY_SIZE(s->irq); irqn++) + free_irq(s->irq[irqn], s); + return 0; +} + +static int mxs_auart_request_irqs(struct mxs_auart_port *s) +{ + int err = 0; + + /* + * order counts. resources should be listed in the same order + */ + irq_handler_t handlers[] = { + mxs_auart_irq_handle, + mxs_auart_irq_dma_rx, + mxs_auart_irq_dma_tx, + }; + char *handlers_names[] = { + "auart internal", + "auart dma rx", + "auart dma tx", + }; + int irqn; + + for (irqn = 0; irqn < ARRAY_SIZE(handlers); irqn++) { + err = request_irq(s->irq[irqn], handlers[irqn], + 0, handlers_names[irqn], s); + if (err) + goto out; + } + return 0; +out: + mxs_auart_free_irqs(s); + return err; +} + +static inline void mxs_auart_reset(struct uart_port *u) +{ + int i; + unsigned int reg; + + __raw_writel(BM_UARTAPP_CTRL0_SFTRST, + u->membase + HW_UARTAPP_CTRL0_CLR); + + for (i = 0; i < 10000; i++) { + reg = __raw_readl(u->membase + HW_UARTAPP_CTRL0); + if (!(reg & BM_UARTAPP_CTRL0_SFTRST)) + break; + udelay(3); + } + + __raw_writel(BM_UARTAPP_CTRL0_CLKGATE, + u->membase + HW_UARTAPP_CTRL0_CLR); +} + +static int mxs_auart_startup(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + mxs_auart_reset(u); + + __raw_writel(BM_UARTAPP_CTRL2_UARTEN, + s->port.membase + HW_UARTAPP_CTRL2_SET); + + /* Enable the Application UART DMA bits. */ + if (s->flags & MXS_AUART_PORT_DMA_MODE) { + int ret; + ret = mxs_auart_dma_init(s); + if (ret) { + __raw_writel(BM_UARTAPP_CTRL2_UARTEN, + s->port.membase + HW_UARTAPP_CTRL2_CLR); + return ret; + } + __raw_writel(BM_UARTAPP_CTRL2_TXDMAE | BM_UARTAPP_CTRL2_RXDMAE + | BM_UARTAPP_CTRL2_DMAONERR, + s->port.membase + HW_UARTAPP_CTRL2_SET); + /* clear any pending interrupts */ + __raw_writel(0, s->port.membase + HW_UARTAPP_INTR); + + /* reset all dma channels */ + mxs_dma_reset(s->dma_tx_chan); + mxs_dma_reset(s->dma_rx_chan); + } else + __raw_writel(BM_UARTAPP_INTR_RXIEN | BM_UARTAPP_INTR_RTIEN, + s->port.membase + HW_UARTAPP_INTR); + + __raw_writel(BM_UARTAPP_INTR_CTSMIEN, + s->port.membase + HW_UARTAPP_INTR_SET); + + /* + * Enable fifo so all four bytes of a DMA word are written to + * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) + */ + __raw_writel(BM_UARTAPP_LINECTRL_FEN, + s->port.membase + HW_UARTAPP_LINECTRL_SET); + + if (s->flags & MXS_AUART_PORT_DMA_MODE) + mxs_auart_submit_rx(s); + return mxs_auart_request_irqs(s); +} + +static void mxs_auart_shutdown(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + __raw_writel(BM_UARTAPP_CTRL0_SFTRST, + s->port.membase + HW_UARTAPP_CTRL0_SET); + + if (s->flags & MXS_AUART_PORT_DMA_MODE) + mxs_auart_dma_exit(s); + else + __raw_writel(BM_UARTAPP_INTR_RXIEN | BM_UARTAPP_INTR_RTIEN | + BM_UARTAPP_INTR_CTSMIEN, + s->port.membase + HW_UARTAPP_INTR_CLR); + mxs_auart_free_irqs(s); +} + +static unsigned int mxs_auart_tx_empty(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + if (s->flags & MXS_AUART_PORT_DMA_MODE) + return mxs_dma_desc_pending(s->tx) ? 0 : TIOCSER_TEMT; + + if (__raw_readl(u->membase + HW_UARTAPP_STAT) & + BM_UARTAPP_STAT_TXFE) + return TIOCSER_TEMT; + else + return 0; +} + +static void mxs_auart_start_tx(struct uart_port *u) +{ + struct mxs_auart_port *s = to_auart_port(u); + + /* enable transmitter */ + __raw_writel(BM_UARTAPP_CTRL2_TXE, u->membase + HW_UARTAPP_CTRL2_SET); + + mxs_auart_tx_chars(s); +} + +static void mxs_auart_stop_tx(struct uart_port *u) +{ + __raw_writel(BM_UARTAPP_CTRL2_TXE, u->membase + HW_UARTAPP_CTRL2_CLR); +} + +static void mxs_auart_stop_rx(struct uart_port *u) +{ + __raw_writel(BM_UARTAPP_CTRL2_RXE, u->membase + HW_UARTAPP_CTRL2_CLR); +} + +static void mxs_auart_break_ctl(struct uart_port *u, int ctl) +{ + if (ctl) + __raw_writel(BM_UARTAPP_LINECTRL_BRK, + u->membase + HW_UARTAPP_LINECTRL_SET); + else + __raw_writel(BM_UARTAPP_LINECTRL_BRK, + u->membase + HW_UARTAPP_LINECTRL_CLR); +} + +static void mxs_auart_enable_ms(struct uart_port *port) +{ + /* just empty */ +} + +static struct uart_ops mxs_auart_ops = { + .tx_empty = mxs_auart_tx_empty, + .start_tx = mxs_auart_start_tx, + .stop_tx = mxs_auart_stop_tx, + .stop_rx = mxs_auart_stop_rx, + .enable_ms = mxs_auart_enable_ms, + .break_ctl = mxs_auart_break_ctl, + .set_mctrl = mxs_auart_set_mctrl, + .get_mctrl = mxs_auart_get_mctrl, + .startup = mxs_auart_startup, + .shutdown = mxs_auart_shutdown, + .set_termios = mxs_auart_settermios, + .type = mxs_auart_type, + .release_port = mxs_auart_release_port, + .request_port = mxs_auart_request_port, + .config_port = mxs_auart_config_port, + .verify_port = mxs_auart_verify_port, +}; +#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE +static struct mxs_auart_port auart_port[CONFIG_MXS_AUART_PORTS] = {}; + +static void +auart_console_write(struct console *co, const char *s, unsigned int count) +{ + struct uart_port *port; + unsigned int status, old_cr; + int i; + + if (co->index > CONFIG_MXS_AUART_PORTS || co->index < 0) + return; + + port = &auart_port[co->index].port; + + /* First save the CR then disable the interrupts */ + old_cr = __raw_readl(port->membase + HW_UARTAPP_CTRL2); + __raw_writel(BM_UARTAPP_CTRL2_UARTEN | BM_UARTAPP_CTRL2_TXE, + port->membase + HW_UARTAPP_CTRL2_SET); + + /* Now, do each character */ + for (i = 0; i < count; i++) { + do { + status = __raw_readl(port->membase + HW_UARTAPP_STAT); + } while (status & BM_UARTAPP_STAT_TXFF); + + __raw_writel(s[i], port->membase + HW_UARTAPP_DATA); + if (s[i] == '\n') { + do { + status = __raw_readl(port->membase + + HW_UARTAPP_STAT); + } while (status & BM_UARTAPP_STAT_TXFF); + __raw_writel('\r', port->membase + HW_UARTAPP_DATA); + } + } + + /* + * Finally, wait for transmitter to become empty + * and restore the TCR + */ + do { + status = __raw_readl(port->membase + HW_UARTAPP_STAT); + } while (status & BM_UARTAPP_STAT_BUSY); + __raw_writel(old_cr, port->membase + HW_UARTAPP_CTRL2); +} + +static void __init +auart_console_get_options(struct uart_port *port, int *baud, + int *parity, int *bits) +{ + if (__raw_readl(port->membase + HW_UARTAPP_CTRL2) + & BM_UARTAPP_CTRL2_UARTEN) { + unsigned int lcr_h, quot; + lcr_h = __raw_readl(port->membase + HW_UARTAPP_LINECTRL); + + *parity = 'n'; + if (lcr_h & BM_UARTAPP_LINECTRL_PEN) { + if (lcr_h & BM_UARTAPP_LINECTRL_EPS) + *parity = 'e'; + else + *parity = 'o'; + } + + if ((lcr_h & BM_UARTAPP_LINECTRL_WLEN) + == BF_UARTAPP_LINECTRL_WLEN(2)) + *bits = 7; + else + *bits = 8; + + quot = (((__raw_readl(port->membase + HW_UARTAPP_LINECTRL) + & BM_UARTAPP_LINECTRL_BAUD_DIVINT)) + >> (BP_UARTAPP_LINECTRL_BAUD_DIVINT - 6)) + | (((__raw_readl(port->membase + HW_UARTAPP_LINECTRL) + & BM_UARTAPP_LINECTRL_BAUD_DIVFRAC)) + >> BP_UARTAPP_LINECTRL_BAUD_DIVFRAC); + if (quot == 0) + quot = 1; + *baud = (port->uartclk << 2) / quot; + } +} + +static int __init auart_console_setup(struct console *co, char *options) +{ + struct mxs_auart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index > CONFIG_MXS_AUART_PORTS || co->index < 0) + return -EINVAL; + + port = &auart_port[co->index].port; + + if (port->port.membase == 0) { + if (cpu_is_mx23()) { + if (co->index == 1) { + port->port.membase = IO_ADDRESS(0x8006C000); + port->port.mapbase = 0x8006C000; + } else { + port->port.membase = IO_ADDRESS(0x8006E000); + port->port.mapbase = 0x8006E000; + } + } + + port->port.fifosize = 16; + port->port.ops = &mxs_auart_ops; + port->port.flags = ASYNC_BOOT_AUTOCONF; + port->port.line = 0; + } + mxs_auart_reset(port); + + __raw_writel(BM_UARTAPP_CTRL2_UARTEN, + port->port.membase + HW_UARTAPP_CTRL2_SET); + + if (port->clk == NULL || IS_ERR(port->clk)) { + port->clk = clk_get(NULL, "uart"); + if (port->clk == NULL || IS_ERR(port->clk)) + return -ENODEV; + port->port.uartclk = clk_get_rate(port->clk); + } + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + else + auart_console_get_options(port, &baud, &parity, &bits); + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console auart_console = { + .name = "ttySP", + .write = auart_console_write, + .device = uart_console_device, + .setup = auart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &auart_driver, +}; + +#ifdef CONFIG_MXS_EARLY_CONSOLE +static int __init auart_console_init(void) +{ + register_console(&auart_console); + return 0; +} + +console_initcall(auart_console_init); +#endif + +#endif +static struct uart_driver auart_driver = { + .owner = THIS_MODULE, + .driver_name = "auart", + .dev_name = "ttySP", + .major = MXS_AUART_MAJOR, + .minor = 0, + .nr = CONFIG_MXS_AUART_PORTS, +#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE + .cons = &auart_console, +#endif +}; + +static int __devinit mxs_auart_probe(struct platform_device *pdev) +{ + struct mxs_auart_plat_data *plat; + struct mxs_auart_port *s; + u32 version; + int i, ret = 0; + struct resource *r; + + s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); + if (!s) { + ret = -ENOMEM; + goto out; + } + + plat = pdev->dev.platform_data; + if (plat == NULL) { + ret = -ENOMEM; + goto out_free; + } + + if (plat && plat->clk) + s->clk = clk_get(NULL, plat->clk); + else + s->clk = clk_get(NULL, "uart"); + if (IS_ERR(s->clk)) { + ret = PTR_ERR(s->clk); + goto out_free; + } + + clk_enable(s->clk); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + ret = -ENXIO; + goto out_free_clk; + } + s->port.mapbase = r->start; + s->port.membase = (void __iomem *)IO_ADDRESS(r->start); + s->port.ops = &mxs_auart_ops; + s->port.iotype = UPIO_MEM; + s->port.line = pdev->id < 0 ? 0 : pdev->id; + s->port.fifosize = plat->fifo_size; + s->port.timeout = plat->timeout ? plat->timeout : (HZ / 10); + s->port.uartclk = clk_get_rate(s->clk); + s->port.type = PORT_IMX; + s->port.dev = s->dev = get_device(&pdev->dev); + + s->flags = plat->dma_mode ? MXS_AUART_PORT_DMA_MODE : 0; + s->ctrl = 0; + s->dma_rx_buffer_size = plat->dma_rx_buffer_size; + + for (i = 0; i < ARRAY_SIZE(s->irq); i++) { + s->irq[i] = platform_get_irq(pdev, i); + if (s->irq[i] < 0) { + ret = s->irq[i]; + goto out_free_clk; + } + } + s->port.irq = s->irq[0]; + + r = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!r) { + ret = -ENXIO; + goto out_free_clk; + } + s->dma_rx_chan = r->start; + + r = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (!r) { + ret = -ENXIO; + goto out_free_clk; + } + s->dma_tx_chan = r->start; + + platform_set_drvdata(pdev, s); + + device_init_wakeup(&pdev->dev, 1); + +#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE + memcpy(&auart_port[pdev->id], s, sizeof(struct mxs_auart_port)); +#endif + + ret = uart_add_one_port(&auart_driver, &s->port); + if (ret) + goto out_free_clk; + + version = __raw_readl(s->port.membase + HW_UARTAPP_VERSION); + printk(KERN_INFO "Found APPUART %d.%d.%d\n", + (version >> 24) & 0xFF, + (version >> 16) & 0xFF, version & 0xFFFF); + return 0; + +out_free_clk: + if (!IS_ERR(s->clk)) + clk_put(s->clk); +out_free: + kfree(s); +out: + return ret; +} + +static int __devexit mxs_auart_remove(struct platform_device *pdev) +{ + struct mxs_auart_port *s; + + s = platform_get_drvdata(pdev); + if (s) { + put_device(s->dev); + clk_disable(s->clk); + clk_put(s->clk); + uart_remove_one_port(&auart_driver, &s->port); + kfree(s); + } + return 0; +} + +static struct platform_driver mxs_auart_driver = { + .probe = mxs_auart_probe, + .remove = __devexit_p(mxs_auart_remove), + .driver = { + .name = "mxs-auart", + .owner = THIS_MODULE, + }, +}; + +static int __init mxs_auart_init(void) +{ + int r; + + r = uart_register_driver(&auart_driver); + if (r) + goto out; + r = platform_driver_register(&mxs_auart_driver); + if (r) + goto out_err; + return 0; +out_err: + uart_unregister_driver(&auart_driver); +out: + return r; +} + +static void __exit mxs_auart_exit(void) +{ + platform_driver_unregister(&mxs_auart_driver); + uart_unregister_driver(&auart_driver); +} + +module_init(mxs_auart_init) +module_exit(mxs_auart_exit) +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Freescale MXS application uart driver"); diff --git a/drivers/serial/mxs-duart.c b/drivers/serial/mxs-duart.c new file mode 100644 index 000000000000..64e5057344e1 --- /dev/null +++ b/drivers/serial/mxs-duart.c @@ -0,0 +1,803 @@ +/* + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#if defined(CONFIG_SERIAL_MXS_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "regs-duart.h" + +/* treated as variable unless submitted to open-source */ +#define PORT_DUART 100 +#define SERIAL_DUART_MAJOR 204 +#define SERIAL_DUART_MINOR 16 +#define SERIAL_RX_LIMIT 256 +#define ISR_PASS_LIMIT 256 + +#define DUART_DEVID "DebugUART" + +static int force_cd = 1; +static struct uart_driver duart_drv; + +/* + * We wrap our port structure around the generic uart_port. + */ +struct duart_port { + struct uart_port port; + struct clk *clk; + unsigned int im; /* interrupt mask */ + unsigned int old_status; + int suspended; +}; + +static void duart_stop_tx(struct uart_port *port) +{ + struct duart_port *dp = container_of(port, struct duart_port, port); + + dp->im &= ~BM_UARTDBGIMSC_TXIM; + __raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC); +} + +static void duart_start_tx(struct uart_port *port) +{ + struct duart_port *dp = container_of(port, struct duart_port, port); + + dp->im |= BM_UARTDBGIMSC_TXIM; + __raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC); +} + +static void duart_stop_rx(struct uart_port *port) +{ + struct duart_port *dp = container_of(port, struct duart_port, port); + + dp->im &= ~(BM_UARTDBGIMSC_OEIM | BM_UARTDBGIMSC_BEIM | + BM_UARTDBGIMSC_PEIM | BM_UARTDBGIMSC_FEIM | + BM_UARTDBGIMSC_RTIM | BM_UARTDBGIMSC_RXIM); + __raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC); +} + +static void duart_enable_ms(struct uart_port *port) +{ + struct duart_port *dp = container_of(port, struct duart_port, port); + + dp->im |= BM_UARTDBGIMSC_RIMIM | BM_UARTDBGIMSC_CTSMIM | + BM_UARTDBGIMSC_DCDMIM | BM_UARTDBGIMSC_DSRMIM; + __raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC); +} + +static void duart_rx_chars(struct duart_port *dp) +{ + struct tty_struct *tty = dp->port.state->port.tty; + unsigned int status, ch, flag, rsr, max_count = SERIAL_RX_LIMIT; + + status = __raw_readl(dp->port.membase + HW_UARTDBGFR); + while ((status & BM_UARTDBGFR_RXFE) == 0 && max_count--) { + ch = __raw_readl(dp->port.membase + HW_UARTDBGDR); + flag = TTY_NORMAL; + dp->port.icount.rx++; + + /* + * Note that the error handling code is + * out of the main execution path + */ + rsr = __raw_readl(dp->port.membase + HW_UARTDBGRSR_ECR); + if (unlikely(rsr & (BM_UARTDBGRSR_ECR_OE | + BM_UARTDBGRSR_ECR_BE | + BM_UARTDBGRSR_ECR_PE | + BM_UARTDBGRSR_ECR_FE))) { + if (rsr & BM_UARTDBGRSR_ECR_BE) { + rsr &= ~(BM_UARTDBGRSR_ECR_FE | + BM_UARTDBGRSR_ECR_PE); + dp->port.icount.brk++; + if (uart_handle_break(&dp->port)) + goto ignore_char; + } else if (rsr & BM_UARTDBGRSR_ECR_PE) + dp->port.icount.parity++; + else if (rsr & BM_UARTDBGRSR_ECR_FE) + dp->port.icount.frame++; + if (rsr & BM_UARTDBGRSR_ECR_OE) + dp->port.icount.overrun++; + + rsr &= dp->port.read_status_mask; + + if (rsr & BM_UARTDBGRSR_ECR_BE) + flag = TTY_BREAK; + else if (rsr & BM_UARTDBGRSR_ECR_PE) + flag = TTY_PARITY; + else if (rsr & BM_UARTDBGRSR_ECR_FE) + flag = TTY_FRAME; + } + + if (uart_handle_sysrq_char(&dp->port, ch)) + goto ignore_char; + + uart_insert_char(&dp->port, rsr, BM_UARTDBGRSR_ECR_OE, ch, + flag); + +ignore_char: + status = __raw_readl(dp->port.membase + HW_UARTDBGFR); + } + tty_flip_buffer_push(tty); + return; +} + +static void duart_tx_chars(struct duart_port *dp) +{ + int count; + struct circ_buf *xmit = &dp->port.state->xmit; + + if (dp->port.x_char) { + __raw_writel(dp->port.x_char, dp->port.membase + HW_UARTDBGDR); + dp->port.icount.tx++; + dp->port.x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(&dp->port)) { + duart_stop_tx(&dp->port); + return; + } + + count = dp->port.fifosize >> 1; + do { + __raw_writel(xmit->buf[xmit->tail], + dp->port.membase + HW_UARTDBGDR); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + dp->port.icount.tx++; + if (uart_circ_empty(xmit)) + break; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&dp->port); + + if (uart_circ_empty(xmit)) + duart_stop_tx(&dp->port); +} + +static void duart_modem_status(struct duart_port *dp) +{ + unsigned int status, delta; + status = __raw_readl(dp->port.membase + HW_UARTDBGFR) & + (BM_UARTDBGFR_DCD | BM_UARTDBGFR_DSR | BM_UARTDBGFR_CTS); + + delta = status ^ dp->old_status; + dp->old_status = status; + + if (!delta) + return; + + if (delta & BM_UARTDBGFR_DCD) + uart_handle_dcd_change(&dp->port, status & BM_UARTDBGFR_DCD); + + if (delta & BM_UARTDBGFR_DSR) + dp->port.icount.dsr++; + + if (delta & BM_UARTDBGFR_CTS) + uart_handle_cts_change(&dp->port, status & BM_UARTDBGFR_CTS); + + wake_up_interruptible(&dp->port.state->port.delta_msr_wait); +} + +static irqreturn_t duart_int(int irq, void *dev_id) +{ + int handled = 0; + struct duart_port *dp = dev_id; + unsigned int status, pass_counter = ISR_PASS_LIMIT; + + spin_lock(&dp->port.lock); + + status = __raw_readl(dp->port.membase + HW_UARTDBGMIS); + while (status) { + handled = 1; + + __raw_writel(status & ~(BM_UARTDBGMIS_TXMIS | + BM_UARTDBGMIS_RTMIS | + BM_UARTDBGMIS_RXMIS), + dp->port.membase + HW_UARTDBGICR); + + if (status & (BM_UARTDBGMIS_RTMIS | BM_UARTDBGMIS_RXMIS)) + duart_rx_chars(dp); + if (status & (BM_UARTDBGMIS_DSRMMIS | + BM_UARTDBGMIS_DCDMMIS | + BM_UARTDBGMIS_CTSMMIS | BM_UARTDBGMIS_RIMMIS)) + duart_modem_status(dp); + if (status & BM_UARTDBGMIS_TXMIS) + duart_tx_chars(dp); + + if (pass_counter-- == 0) + break; + + status = __raw_readl(dp->port.membase + HW_UARTDBGMIS); + }; + + spin_unlock(&dp->port.lock); + + return IRQ_RETVAL(handled); +} + +static unsigned int duart_tx_empty(struct uart_port *port) +{ + struct duart_port *dp = (struct duart_port *)port; + unsigned int status = __raw_readl(dp->port.membase + HW_UARTDBGFR); + return status & (BM_UARTDBGFR_BUSY | BM_UARTDBGFR_TXFF) ? + 0 : TIOCSER_TEMT; +} + +static unsigned int duart_get_mctrl(struct uart_port *port) +{ + unsigned int result = 0; + struct duart_port *dp = (struct duart_port *)port; + unsigned int status = __raw_readl(dp->port.membase + HW_UARTDBGFR); + +#define TEST_AND_SET_BIT(uartbit, tiocmbit) do { \ + if (status & uartbit) \ + result |= tiocmbit; \ + } while (0) + + TEST_AND_SET_BIT(BM_UARTDBGFR_DCD, TIOCM_CAR); + TEST_AND_SET_BIT(BM_UARTDBGFR_DSR, TIOCM_DSR); + TEST_AND_SET_BIT(BM_UARTDBGFR_CTS, TIOCM_CTS); + TEST_AND_SET_BIT(BM_UARTDBGFR_RI, TIOCM_RNG); +#undef TEST_AND_SET_BIT + if (force_cd) + result |= TIOCM_CAR; + return result; +} + +static void duart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + unsigned int cr; + struct duart_port *dp = (struct duart_port *)port; + + cr = __raw_readl(dp->port.membase + HW_UARTDBGCR); + +#define TEST_AND_SET_BIT(tiocmbit, uartbit) do { \ + if (mctrl & tiocmbit) \ + cr |= uartbit; \ + else \ + cr &= ~uartbit; \ + } while (0) + + TEST_AND_SET_BIT(TIOCM_RTS, BM_UARTDBGCR_RTS); + TEST_AND_SET_BIT(TIOCM_DTR, BM_UARTDBGCR_DTR); + TEST_AND_SET_BIT(TIOCM_OUT1, BM_UARTDBGCR_OUT1); + TEST_AND_SET_BIT(TIOCM_OUT2, BM_UARTDBGCR_OUT2); + TEST_AND_SET_BIT(TIOCM_LOOP, BM_UARTDBGCR_LBE); +#undef TEST_AND_SET_BIT + + __raw_writel(cr, dp->port.membase + HW_UARTDBGCR); +} + +static void duart_break_ctl(struct uart_port *port, int break_state) +{ + unsigned long flags; + unsigned int lcr_h; + struct duart_port *dp = (struct duart_port *)port; + + spin_lock_irqsave(&dp->port.lock, flags); + lcr_h = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H); + if (break_state == -1) + lcr_h |= BM_UARTDBGLCR_H_BRK; + else + lcr_h &= ~BM_UARTDBGLCR_H_BRK; + __raw_writel(lcr_h, dp->port.membase + HW_UARTDBGLCR_H); + spin_unlock_irqrestore(&dp->port.lock, flags); +} + +static int duart_startup(struct uart_port *port) +{ + u32 cr, lcr; + int retval; + struct duart_port *dp = (struct duart_port *)port; + + /* + * Allocate the IRQ + */ + retval = request_irq(dp->port.irq, duart_int, 0, DUART_DEVID, dp); + if (retval) + return retval; + + /* wake up the UART */ + __raw_writel(0, dp->port.membase + HW_UARTDBGDR); + + __raw_writel(BF_UARTDBGIFLS_TXIFLSEL(BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF) + | + BF_UARTDBGIFLS_RXIFLSEL(BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF), + dp->port.membase + HW_UARTDBGIFLS); + + /* + * Provoke TX FIFO interrupt into asserting. + */ + cr = BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_RXE | BM_UARTDBGCR_TXE; + __raw_writel(cr, dp->port.membase + HW_UARTDBGCR); + + lcr = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H); + lcr |= BM_UARTDBGLCR_H_FEN; + __raw_writel(lcr, dp->port.membase + HW_UARTDBGLCR_H); + + /* + * initialise the old status of the modem signals + */ + dp->old_status = __raw_readl(dp->port.membase + HW_UARTDBGFR) & + (BM_UARTDBGFR_DCD | BM_UARTDBGFR_DSR | BM_UARTDBGFR_CTS); + /* + * Finally, enable interrupts + */ + dp->im = BM_UARTDBGIMSC_RXIM | BM_UARTDBGIMSC_RTIM; + __raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC); + + return 0; +} + +static void duart_shutdown(struct uart_port *port) +{ + unsigned long flags; + unsigned int val; + struct duart_port *dp = (struct duart_port *)port; + + /* + * disable all interrupts + */ + spin_lock_irqsave(&dp->port.lock, flags); + dp->im = 0; + __raw_writel(dp->im, dp->port.membase + HW_UARTDBGIMSC); + __raw_writel(0xffff, dp->port.membase + HW_UARTDBGICR); + spin_unlock_irqrestore(&dp->port.lock, flags); + + free_irq(dp->port.irq, dp); + + /* + * disable the port + */ + __raw_writel(BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_TXE, + dp->port.membase + HW_UARTDBGCR); + /* + * disable break condition and fifos + */ + val = __raw_readl(dp->port.membase + HW_UARTDBGLCR_H); + val &= ~(BM_UARTDBGLCR_H_BRK | BM_UARTDBGLCR_H_FEN); + __raw_writel(val, dp->port.membase + HW_UARTDBGLCR_H); +} + +static void +duart_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + unsigned int lcr_h, old_cr; + unsigned long flags; + unsigned int baud, quot; + + /* + * Ask the core to calculate the divisor for us. + */ + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); + quot = (port->uartclk << 2) / baud; + + switch (termios->c_cflag & CSIZE) { + case CS5: + lcr_h = BF_UARTDBGLCR_H_WLEN(0); + break; + case CS6: + lcr_h = BF_UARTDBGLCR_H_WLEN(1); + break; + case CS7: + lcr_h = BF_UARTDBGLCR_H_WLEN(2); + break; + default: /* CS8 */ + lcr_h = BF_UARTDBGLCR_H_WLEN(3); + break; + } + if (termios->c_cflag & CSTOPB) + lcr_h |= BM_UARTDBGLCR_H_STP2; + if (termios->c_cflag & PARENB) { + lcr_h |= BM_UARTDBGLCR_H_PEN; + if (!(termios->c_cflag & PARODD)) + lcr_h |= BM_UARTDBGLCR_H_EPS; + } + lcr_h |= BM_UARTDBGLCR_H_FEN; + + spin_lock_irqsave(&port->lock, flags); + + /* + * Update the per-port timeout. + */ + uart_update_timeout(port, termios->c_cflag, baud); + + port->read_status_mask = BM_UARTDBGRSR_ECR_OE; + if (termios->c_iflag & INPCK) + port->read_status_mask |= BM_UARTDBGRSR_ECR_FE | + BM_UARTDBGRSR_ECR_PE; + if (termios->c_iflag & (BRKINT | PARMRK)) + port->read_status_mask |= BM_UARTDBGRSR_ECR_BE; + + /* + * Characters to ignore + */ + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= BM_UARTDBGRSR_ECR_FE | + BM_UARTDBGRSR_ECR_PE; + if (termios->c_iflag & IGNBRK) { + port->ignore_status_mask |= BM_UARTDBGRSR_ECR_BE; + /* + * If we're ignoring parity and break indicators, + * ignore overruns too (for real raw support). + */ + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= BM_UARTDBGRSR_ECR_OE; + } + + if (UART_ENABLE_MS(port, termios->c_cflag)) + duart_enable_ms(port); + + /* first, disable everything */ + old_cr = __raw_readl(port->membase + HW_UARTDBGCR); + __raw_writel(0, port->membase + HW_UARTDBGCR); + + /* Set baud rate */ + __raw_writel(quot & 0x3f, port->membase + HW_UARTDBGFBRD); + __raw_writel(quot >> 6, port->membase + HW_UARTDBGIBRD); + /* + * ----------v----------v----------v----------v----- + * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L + * ----------^----------^----------^----------^----- + */ + __raw_writel(lcr_h, port->membase + HW_UARTDBGLCR_H); + __raw_writel(old_cr, port->membase + HW_UARTDBGCR); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *duart_type(struct uart_port *port) +{ + return port->type == PORT_DUART ? DUART_DEVID : NULL; +} + +/* + * Release the memory region(s) being used by 'port' + */ +static void duart_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, PAGE_SIZE); +} + +/* + * Request the memory region(s) being used by 'port' + */ +static int duart_request_port(struct uart_port *port) +{ + return request_mem_region(port->mapbase, PAGE_SIZE, DUART_DEVID) + != NULL ? 0 : -EBUSY; +} + +/* + * Configure/autoconfigure the port. + */ +static void duart_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) { + port->type = PORT_DUART; + duart_request_port(port); + } +} + +/* + * verify the new serial_struct (for TIOCSSERIAL). + */ +static int duart_verify_port(struct uart_port *port, struct serial_struct *ser) +{ + int ret = 0; + if (ser->type != PORT_UNKNOWN && ser->type != PORT_DUART) + ret = -EINVAL; + if (ser->irq < 0 || ser->irq >= NR_IRQS) + ret = -EINVAL; + if (ser->baud_base < 9600) + ret = -EINVAL; + return ret; +} + +static struct uart_ops duart_pops = { + .tx_empty = duart_tx_empty, + .set_mctrl = duart_set_mctrl, + .get_mctrl = duart_get_mctrl, + .stop_tx = duart_stop_tx, + .start_tx = duart_start_tx, + .stop_rx = duart_stop_rx, + .enable_ms = duart_enable_ms, + .break_ctl = duart_break_ctl, + .startup = duart_startup, + .shutdown = duart_shutdown, + .set_termios = duart_set_termios, + .type = duart_type, + .release_port = duart_release_port, + .request_port = duart_request_port, + .config_port = duart_config_port, + .verify_port = duart_verify_port, +}; + +static struct duart_port duart_port = { + .port = { + .iotype = SERIAL_IO_MEM, +#ifdef CONFIG_MXS_EARLY_CONSOLE + .membase = MXS_DEBUG_CONSOLE_VIRT, + .mapbase = MXS_DEBUG_CONSOLE_PHYS, +#endif + .fifosize = 16, + .ops = &duart_pops, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 0, + }, +}; + +#ifdef CONFIG_SERIAL_MXS_DUART_CONSOLE + +static void +duart_console_write(struct console *co, const char *s, unsigned int count) +{ + struct uart_port *port = &duart_port.port; + unsigned int status, old_cr; + int i; + /* + * First save the CR then disable the interrupts + */ + old_cr = __raw_readl(port->membase + HW_UARTDBGCR); + __raw_writel(BM_UARTDBGCR_UARTEN | BM_UARTDBGCR_TXE, + port->membase + HW_UARTDBGCR); + /* + * Now, do each character + */ + for (i = 0; i < count; i++) { + do { + status = __raw_readl(port->membase + HW_UARTDBGFR); + } while (status & BM_UARTDBGFR_TXFF); + + __raw_writel(s[i], port->membase + HW_UARTDBGDR); + if (s[i] == '\n') { + do { + status = __raw_readl(port->membase + + HW_UARTDBGFR); + } while (status & BM_UARTDBGFR_TXFF); + __raw_writel('\r', port->membase + HW_UARTDBGDR); + } + } + + /* + * Finally, wait for transmitter to become empty + * and restore the TCR + */ + do { + status = __raw_readl(port->membase + HW_UARTDBGFR); + } while (status & BM_UARTDBGFR_BUSY); + __raw_writel(old_cr, port->membase + HW_UARTDBGCR); +} + +static void __init +duart_console_get_options(struct uart_port *port, int *baud, + int *parity, int *bits) +{ + if (__raw_readl(port->membase + HW_UARTDBGCR) & BM_UARTDBGCR_UARTEN) { + unsigned int lcr_h, quot; + lcr_h = __raw_readl(port->membase + HW_UARTDBGLCR_H); + + *parity = 'n'; + if (lcr_h & BM_UARTDBGLCR_H_PEN) { + if (lcr_h & BM_UARTDBGLCR_H_EPS) + *parity = 'e'; + else + *parity = 'o'; + } + + if ((lcr_h & BM_UARTDBGLCR_H_WLEN) == BF_UARTDBGLCR_H_WLEN(2)) + *bits = 7; + else + *bits = 8; + + quot = (__raw_readl(port->membase + HW_UARTDBGFBRD) & 0x3F) | + __raw_readl(port->membase + HW_UARTDBGIBRD) << 6; + if (quot == 0) + quot = 1; + *baud = (port->uartclk << 2) / quot; + } +} + +static int __init duart_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + /* + * Check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index) + return -EINVAL; + + port = &duart_port.port; + + if (duart_port.clk == NULL || IS_ERR(duart_port.clk)) { + duart_port.clk = clk_get(NULL, "uart"); + if (duart_port.clk == NULL || IS_ERR(duart_port.clk)) + return -ENODEV; + duart_port.port.uartclk = clk_get_rate(duart_port.clk); + } + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + else + duart_console_get_options(port, &baud, &parity, &bits); + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct console duart_console = { + .name = "ttyAM", + .write = duart_console_write, + .device = uart_console_device, + .setup = duart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &duart_drv, +}; + +#ifdef CONFIG_MXS_EARLY_CONSOLE +static int __init duart_console_init(void) +{ + register_console(&duart_console); + return 0; +} + +console_initcall(duart_console_init); +#endif + +#endif + +static struct uart_driver duart_drv = { + .owner = THIS_MODULE, + .driver_name = "ttyAM", + .dev_name = "ttyAM", + .major = SERIAL_DUART_MAJOR, + .minor = SERIAL_DUART_MINOR, + .nr = 1, +#ifdef CONFIG_SERIAL_MXS_DUART_CONSOLE + .cons = &duart_console, +#endif +}; + +static int __devinit duart_probe(struct platform_device *pdev) +{ + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOMEM; + /* + * Will use mapbase and membase here if !CONFIG_MXS_EARLY_CONSOLE, + * or use the overridden values later if CONFIG_MXS_EARLY_CONSOLE + */ + duart_port.port.mapbase = res->start; + duart_port.port.membase = + (unsigned char __iomem *)IO_ADDRESS(res->start); + + duart_port.port.irq = platform_get_irq(pdev, 0); + if (duart_port.port.irq < 0) + return -EINVAL; + device_init_wakeup(&pdev->dev, 1); + + duart_port.clk = clk_get(NULL, "uart"); + if (duart_port.clk == NULL || IS_ERR(duart_port.clk)) + return -ENODEV; + duart_port.suspended = 0; + duart_port.port.dev = &pdev->dev; + duart_port.port.uartclk = clk_get_rate(duart_port.clk); + uart_add_one_port(&duart_drv, &duart_port.port); + return 0; +} + +static int __devexit duart_remove(struct platform_device *pdev) +{ + clk_put(duart_port.clk); + uart_remove_one_port(&duart_drv, &duart_port.port); + return 0; +} + +#ifdef CONFIG_PM +static int duart_suspend(struct platform_device *pdev, + pm_message_t state) +{ + int ret = 0; + if (!duart_port.suspended) { + ret = uart_suspend_port(&duart_drv, &duart_port.port); + if (!ret) + duart_port.suspended = 1; + } + return ret; +} + +static int duart_resume(struct platform_device *pdev, + pm_message_t state) +{ + int ret = 0; + if (duart_port.suspended) { + ret = uart_resume_port(&duart_drv, &duart_port.port); + if (!ret) + duart_port.suspended = 0; + } + return ret; +} +#else +#define duart_suspend NULL +#define duart_resume NULL +#endif + +static struct platform_driver duart_driver = { + .probe = duart_probe, + .remove = __devexit_p(duart_remove), + .suspend = duart_suspend, + .resume = duart_resume, + .driver = { + .name = "mxs-duart", + .owner = THIS_MODULE, + }, +}; + +static int __init duart_init(void) +{ + int ret; + ret = uart_register_driver(&duart_drv); + if (ret) + return ret; + + ret = platform_driver_register(&duart_driver); + if (ret) + uart_unregister_driver(&duart_drv); + + return ret; +} + +static void __exit duart_exit(void) +{ + platform_driver_unregister(&duart_driver); + uart_unregister_driver(&duart_drv); +} + +module_init(duart_init); +module_exit(duart_exit); +module_param(force_cd, int, 0644); +MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd/Freescale Inc"); +MODULE_DESCRIPTION("i.MXS debug uart"); +MODULE_LICENSE("GPL"); diff --git a/drivers/serial/regs-duart.h b/drivers/serial/regs-duart.h new file mode 100644 index 000000000000..0b5932c79a55 --- /dev/null +++ b/drivers/serial/regs-duart.h @@ -0,0 +1,301 @@ +/* + * Freescale UARTDBG Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.21 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___UARTDBG_H +#define __ARCH_ARM___UARTDBG_H + + +#define HW_UARTDBGDR (0x00000000) + +#define BP_UARTDBGDR_UNAVAILABLE 16 +#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGDR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) +#define BP_UARTDBGDR_RESERVED 12 +#define BM_UARTDBGDR_RESERVED 0x0000F000 +#define BF_UARTDBGDR_RESERVED(v) \ + (((v) << 12) & BM_UARTDBGDR_RESERVED) +#define BM_UARTDBGDR_OE 0x00000800 +#define BM_UARTDBGDR_BE 0x00000400 +#define BM_UARTDBGDR_PE 0x00000200 +#define BM_UARTDBGDR_FE 0x00000100 +#define BP_UARTDBGDR_DATA 0 +#define BM_UARTDBGDR_DATA 0x000000FF +#define BF_UARTDBGDR_DATA(v) \ + (((v) << 0) & BM_UARTDBGDR_DATA) + +#define HW_UARTDBGRSR_ECR (0x00000004) + +#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 +#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 +#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ + (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) +#define BP_UARTDBGRSR_ECR_EC 4 +#define BM_UARTDBGRSR_ECR_EC 0x000000F0 +#define BF_UARTDBGRSR_ECR_EC(v) \ + (((v) << 4) & BM_UARTDBGRSR_ECR_EC) +#define BM_UARTDBGRSR_ECR_OE 0x00000008 +#define BM_UARTDBGRSR_ECR_BE 0x00000004 +#define BM_UARTDBGRSR_ECR_PE 0x00000002 +#define BM_UARTDBGRSR_ECR_FE 0x00000001 + +#define HW_UARTDBGFR (0x00000018) + +#define BP_UARTDBGFR_UNAVAILABLE 16 +#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGFR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) +#define BP_UARTDBGFR_RESERVED 9 +#define BM_UARTDBGFR_RESERVED 0x0000FE00 +#define BF_UARTDBGFR_RESERVED(v) \ + (((v) << 9) & BM_UARTDBGFR_RESERVED) +#define BM_UARTDBGFR_RI 0x00000100 +#define BM_UARTDBGFR_TXFE 0x00000080 +#define BM_UARTDBGFR_RXFF 0x00000040 +#define BM_UARTDBGFR_TXFF 0x00000020 +#define BM_UARTDBGFR_RXFE 0x00000010 +#define BM_UARTDBGFR_BUSY 0x00000008 +#define BM_UARTDBGFR_DCD 0x00000004 +#define BM_UARTDBGFR_DSR 0x00000002 +#define BM_UARTDBGFR_CTS 0x00000001 + +#define HW_UARTDBGILPR (0x00000020) + +#define BP_UARTDBGILPR_UNAVAILABLE 8 +#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 +#define BF_UARTDBGILPR_UNAVAILABLE(v) \ + (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) +#define BP_UARTDBGILPR_ILPDVSR 0 +#define BM_UARTDBGILPR_ILPDVSR 0x000000FF +#define BF_UARTDBGILPR_ILPDVSR(v) \ + (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) + +#define HW_UARTDBGIBRD (0x00000024) + +#define BP_UARTDBGIBRD_UNAVAILABLE 16 +#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) +#define BP_UARTDBGIBRD_BAUD_DIVINT 0 +#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF +#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ + (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) + +#define HW_UARTDBGFBRD (0x00000028) + +#define BP_UARTDBGFBRD_UNAVAILABLE 8 +#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 +#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ + (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) +#define BP_UARTDBGFBRD_RESERVED 6 +#define BM_UARTDBGFBRD_RESERVED 0x000000C0 +#define BF_UARTDBGFBRD_RESERVED(v) \ + (((v) << 6) & BM_UARTDBGFBRD_RESERVED) +#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 +#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F +#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ + (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) + +#define HW_UARTDBGLCR_H (0x0000002c) + +#define BP_UARTDBGLCR_H_UNAVAILABLE 16 +#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) +#define BP_UARTDBGLCR_H_RESERVED 8 +#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 +#define BF_UARTDBGLCR_H_RESERVED(v) \ + (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) +#define BM_UARTDBGLCR_H_SPS 0x00000080 +#define BP_UARTDBGLCR_H_WLEN 5 +#define BM_UARTDBGLCR_H_WLEN 0x00000060 +#define BF_UARTDBGLCR_H_WLEN(v) \ + (((v) << 5) & BM_UARTDBGLCR_H_WLEN) +#define BM_UARTDBGLCR_H_FEN 0x00000010 +#define BM_UARTDBGLCR_H_STP2 0x00000008 +#define BM_UARTDBGLCR_H_EPS 0x00000004 +#define BM_UARTDBGLCR_H_PEN 0x00000002 +#define BM_UARTDBGLCR_H_BRK 0x00000001 + +#define HW_UARTDBGCR (0x00000030) + +#define BP_UARTDBGCR_UNAVAILABLE 16 +#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGCR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) +#define BM_UARTDBGCR_CTSEN 0x00008000 +#define BM_UARTDBGCR_RTSEN 0x00004000 +#define BM_UARTDBGCR_OUT2 0x00002000 +#define BM_UARTDBGCR_OUT1 0x00001000 +#define BM_UARTDBGCR_RTS 0x00000800 +#define BM_UARTDBGCR_DTR 0x00000400 +#define BM_UARTDBGCR_RXE 0x00000200 +#define BM_UARTDBGCR_TXE 0x00000100 +#define BM_UARTDBGCR_LBE 0x00000080 +#define BP_UARTDBGCR_RESERVED 3 +#define BM_UARTDBGCR_RESERVED 0x00000078 +#define BF_UARTDBGCR_RESERVED(v) \ + (((v) << 3) & BM_UARTDBGCR_RESERVED) +#define BM_UARTDBGCR_SIRLP 0x00000004 +#define BM_UARTDBGCR_SIREN 0x00000002 +#define BM_UARTDBGCR_UARTEN 0x00000001 + +#define HW_UARTDBGIFLS (0x00000034) + +#define BP_UARTDBGIFLS_UNAVAILABLE 16 +#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) +#define BP_UARTDBGIFLS_RESERVED 6 +#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 +#define BF_UARTDBGIFLS_RESERVED(v) \ + (((v) << 6) & BM_UARTDBGIFLS_RESERVED) +#define BP_UARTDBGIFLS_RXIFLSEL 3 +#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 +#define BF_UARTDBGIFLS_RXIFLSEL(v) \ + (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) +#define BV_UARTDBGIFLS_RXIFLSEL__ONE_EIGHT 0x0 +#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 +#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 +#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 +#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 +#define BP_UARTDBGIFLS_TXIFLSEL 0 +#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 +#define BF_UARTDBGIFLS_TXIFLSEL(v) \ + (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) +#define BV_UARTDBGIFLS_TXIFLSEL__ONE_EIGHT 0x0 +#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 +#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 +#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 +#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 + +#define HW_UARTDBGIMSC (0x00000038) + +#define BP_UARTDBGIMSC_UNAVAILABLE 16 +#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) +#define BP_UARTDBGIMSC_RESERVED 11 +#define BM_UARTDBGIMSC_RESERVED 0x0000F800 +#define BF_UARTDBGIMSC_RESERVED(v) \ + (((v) << 11) & BM_UARTDBGIMSC_RESERVED) +#define BM_UARTDBGIMSC_OEIM 0x00000400 +#define BM_UARTDBGIMSC_BEIM 0x00000200 +#define BM_UARTDBGIMSC_PEIM 0x00000100 +#define BM_UARTDBGIMSC_FEIM 0x00000080 +#define BM_UARTDBGIMSC_RTIM 0x00000040 +#define BM_UARTDBGIMSC_TXIM 0x00000020 +#define BM_UARTDBGIMSC_RXIM 0x00000010 +#define BM_UARTDBGIMSC_DSRMIM 0x00000008 +#define BM_UARTDBGIMSC_DCDMIM 0x00000004 +#define BM_UARTDBGIMSC_CTSMIM 0x00000002 +#define BM_UARTDBGIMSC_RIMIM 0x00000001 + +#define HW_UARTDBGRIS (0x0000003c) + +#define BP_UARTDBGRIS_UNAVAILABLE 16 +#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGRIS_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) +#define BP_UARTDBGRIS_RESERVED 11 +#define BM_UARTDBGRIS_RESERVED 0x0000F800 +#define BF_UARTDBGRIS_RESERVED(v) \ + (((v) << 11) & BM_UARTDBGRIS_RESERVED) +#define BM_UARTDBGRIS_OERIS 0x00000400 +#define BM_UARTDBGRIS_BERIS 0x00000200 +#define BM_UARTDBGRIS_PERIS 0x00000100 +#define BM_UARTDBGRIS_FERIS 0x00000080 +#define BM_UARTDBGRIS_RTRIS 0x00000040 +#define BM_UARTDBGRIS_TXRIS 0x00000020 +#define BM_UARTDBGRIS_RXRIS 0x00000010 +#define BM_UARTDBGRIS_DSRRMIS 0x00000008 +#define BM_UARTDBGRIS_DCDRMIS 0x00000004 +#define BM_UARTDBGRIS_CTSRMIS 0x00000002 +#define BM_UARTDBGRIS_RIRMIS 0x00000001 + +#define HW_UARTDBGMIS (0x00000040) + +#define BP_UARTDBGMIS_UNAVAILABLE 16 +#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGMIS_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) +#define BP_UARTDBGMIS_RESERVED 11 +#define BM_UARTDBGMIS_RESERVED 0x0000F800 +#define BF_UARTDBGMIS_RESERVED(v) \ + (((v) << 11) & BM_UARTDBGMIS_RESERVED) +#define BM_UARTDBGMIS_OEMIS 0x00000400 +#define BM_UARTDBGMIS_BEMIS 0x00000200 +#define BM_UARTDBGMIS_PEMIS 0x00000100 +#define BM_UARTDBGMIS_FEMIS 0x00000080 +#define BM_UARTDBGMIS_RTMIS 0x00000040 +#define BM_UARTDBGMIS_TXMIS 0x00000020 +#define BM_UARTDBGMIS_RXMIS 0x00000010 +#define BM_UARTDBGMIS_DSRMMIS 0x00000008 +#define BM_UARTDBGMIS_DCDMMIS 0x00000004 +#define BM_UARTDBGMIS_CTSMMIS 0x00000002 +#define BM_UARTDBGMIS_RIMMIS 0x00000001 + +#define HW_UARTDBGICR (0x00000044) + +#define BP_UARTDBGICR_UNAVAILABLE 16 +#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGICR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) +#define BP_UARTDBGICR_RESERVED 11 +#define BM_UARTDBGICR_RESERVED 0x0000F800 +#define BF_UARTDBGICR_RESERVED(v) \ + (((v) << 11) & BM_UARTDBGICR_RESERVED) +#define BM_UARTDBGICR_OEIC 0x00000400 +#define BM_UARTDBGICR_BEIC 0x00000200 +#define BM_UARTDBGICR_PEIC 0x00000100 +#define BM_UARTDBGICR_FEIC 0x00000080 +#define BM_UARTDBGICR_RTIC 0x00000040 +#define BM_UARTDBGICR_TXIC 0x00000020 +#define BM_UARTDBGICR_RXIC 0x00000010 +#define BM_UARTDBGICR_DSRMIC 0x00000008 +#define BM_UARTDBGICR_DCDMIC 0x00000004 +#define BM_UARTDBGICR_CTSMIC 0x00000002 +#define BM_UARTDBGICR_RIMIC 0x00000001 + +#define HW_UARTDBGDMACR (0x00000048) + +#define BP_UARTDBGDMACR_UNAVAILABLE 16 +#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 +#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ + (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) +#define BP_UARTDBGDMACR_RESERVED 3 +#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 +#define BF_UARTDBGDMACR_RESERVED(v) \ + (((v) << 3) & BM_UARTDBGDMACR_RESERVED) +#define BM_UARTDBGDMACR_DMAONERR 0x00000004 +#define BM_UARTDBGDMACR_TXDMAE 0x00000002 +#define BM_UARTDBGDMACR_RXDMAE 0x00000001 +#endif /* __ARCH_ARM___UARTDBG_H */ diff --git a/drivers/serial/regs-uartapp.h b/drivers/serial/regs-uartapp.h new file mode 100644 index 000000000000..aad9a7866556 --- /dev/null +++ b/drivers/serial/regs-uartapp.h @@ -0,0 +1,307 @@ +/* + * Freescale UARTAPP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.42 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___UARTAPP_H +#define __ARCH_ARM___UARTAPP_H + + +#define HW_UARTAPP_CTRL0 (0x00000000) +#define HW_UARTAPP_CTRL0_SET (0x00000004) +#define HW_UARTAPP_CTRL0_CLR (0x00000008) +#define HW_UARTAPP_CTRL0_TOG (0x0000000c) + +#define BM_UARTAPP_CTRL0_SFTRST 0x80000000 +#define BM_UARTAPP_CTRL0_CLKGATE 0x40000000 +#define BM_UARTAPP_CTRL0_RUN 0x20000000 +#define BM_UARTAPP_CTRL0_RX_SOURCE 0x10000000 +#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 +#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 +#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 +#define BF_UARTAPP_CTRL0_RXTIMEOUT(v) \ + (((v) << 16) & BM_UARTAPP_CTRL0_RXTIMEOUT) +#define BP_UARTAPP_CTRL0_XFER_COUNT 0 +#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_UARTAPP_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_UARTAPP_CTRL0_XFER_COUNT) + +#define HW_UARTAPP_CTRL1 (0x00000010) +#define HW_UARTAPP_CTRL1_SET (0x00000014) +#define HW_UARTAPP_CTRL1_CLR (0x00000018) +#define HW_UARTAPP_CTRL1_TOG (0x0000001c) + +#define BP_UARTAPP_CTRL1_RSVD2 29 +#define BM_UARTAPP_CTRL1_RSVD2 0xE0000000 +#define BF_UARTAPP_CTRL1_RSVD2(v) \ + (((v) << 29) & BM_UARTAPP_CTRL1_RSVD2) +#define BM_UARTAPP_CTRL1_RUN 0x10000000 +#define BP_UARTAPP_CTRL1_RSVD1 16 +#define BM_UARTAPP_CTRL1_RSVD1 0x0FFF0000 +#define BF_UARTAPP_CTRL1_RSVD1(v) \ + (((v) << 16) & BM_UARTAPP_CTRL1_RSVD1) +#define BP_UARTAPP_CTRL1_XFER_COUNT 0 +#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF +#define BF_UARTAPP_CTRL1_XFER_COUNT(v) \ + (((v) << 0) & BM_UARTAPP_CTRL1_XFER_COUNT) + +#define HW_UARTAPP_CTRL2 (0x00000020) +#define HW_UARTAPP_CTRL2_SET (0x00000024) +#define HW_UARTAPP_CTRL2_CLR (0x00000028) +#define HW_UARTAPP_CTRL2_TOG (0x0000002c) + +#define BM_UARTAPP_CTRL2_INVERT_RTS 0x80000000 +#define BM_UARTAPP_CTRL2_INVERT_CTS 0x40000000 +#define BM_UARTAPP_CTRL2_INVERT_TX 0x20000000 +#define BM_UARTAPP_CTRL2_INVERT_RX 0x10000000 +#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE 0x08000000 +#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 +#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 +#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 +#define BM_UARTAPP_CTRL2_RSVD2 0x00800000 +#define BP_UARTAPP_CTRL2_RXIFLSEL 20 +#define BM_UARTAPP_CTRL2_RXIFLSEL 0x00700000 +#define BF_UARTAPP_CTRL2_RXIFLSEL(v) \ + (((v) << 20) & BM_UARTAPP_CTRL2_RXIFLSEL) +#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 +#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7 +#define BM_UARTAPP_CTRL2_RSVD3 0x00080000 +#define BP_UARTAPP_CTRL2_TXIFLSEL 16 +#define BM_UARTAPP_CTRL2_TXIFLSEL 0x00070000 +#define BF_UARTAPP_CTRL2_TXIFLSEL(v) \ + (((v) << 16) & BM_UARTAPP_CTRL2_TXIFLSEL) +#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY 0x0 +#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF 0x2 +#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5 0x5 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6 0x6 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7 0x7 +#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 +#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 +#define BM_UARTAPP_CTRL2_OUT2 0x00002000 +#define BM_UARTAPP_CTRL2_OUT1 0x00001000 +#define BM_UARTAPP_CTRL2_RTS 0x00000800 +#define BM_UARTAPP_CTRL2_DTR 0x00000400 +#define BM_UARTAPP_CTRL2_RXE 0x00000200 +#define BM_UARTAPP_CTRL2_TXE 0x00000100 +#define BM_UARTAPP_CTRL2_LBE 0x00000080 +#define BM_UARTAPP_CTRL2_USE_LCR2 0x00000040 +#define BP_UARTAPP_CTRL2_RSVD4 3 +#define BM_UARTAPP_CTRL2_RSVD4 0x00000038 +#define BF_UARTAPP_CTRL2_RSVD4(v) \ + (((v) << 3) & BM_UARTAPP_CTRL2_RSVD4) +#define BM_UARTAPP_CTRL2_SIRLP 0x00000004 +#define BM_UARTAPP_CTRL2_SIREN 0x00000002 +#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 + +#define HW_UARTAPP_LINECTRL (0x00000030) +#define HW_UARTAPP_LINECTRL_SET (0x00000034) +#define HW_UARTAPP_LINECTRL_CLR (0x00000038) +#define HW_UARTAPP_LINECTRL_TOG (0x0000003c) + +#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 +#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 +#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) \ + (((v) << 16) & BM_UARTAPP_LINECTRL_BAUD_DIVINT) +#define BP_UARTAPP_LINECTRL_RSVD 14 +#define BM_UARTAPP_LINECTRL_RSVD 0x0000C000 +#define BF_UARTAPP_LINECTRL_RSVD(v) \ + (((v) << 14) & BM_UARTAPP_LINECTRL_RSVD) +#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 +#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 +#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) \ + (((v) << 8) & BM_UARTAPP_LINECTRL_BAUD_DIVFRAC) +#define BM_UARTAPP_LINECTRL_SPS 0x00000080 +#define BP_UARTAPP_LINECTRL_WLEN 5 +#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 +#define BF_UARTAPP_LINECTRL_WLEN(v) \ + (((v) << 5) & BM_UARTAPP_LINECTRL_WLEN) +#define BM_UARTAPP_LINECTRL_FEN 0x00000010 +#define BM_UARTAPP_LINECTRL_STP2 0x00000008 +#define BM_UARTAPP_LINECTRL_EPS 0x00000004 +#define BM_UARTAPP_LINECTRL_PEN 0x00000002 +#define BM_UARTAPP_LINECTRL_BRK 0x00000001 + +#define HW_UARTAPP_LINECTRL2 (0x00000040) +#define HW_UARTAPP_LINECTRL2_SET (0x00000044) +#define HW_UARTAPP_LINECTRL2_CLR (0x00000048) +#define HW_UARTAPP_LINECTRL2_TOG (0x0000004c) + +#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT 16 +#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT 0xFFFF0000 +#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v) \ + (((v) << 16) & BM_UARTAPP_LINECTRL2_BAUD_DIVINT) +#define BP_UARTAPP_LINECTRL2_RSVD 14 +#define BM_UARTAPP_LINECTRL2_RSVD 0x0000C000 +#define BF_UARTAPP_LINECTRL2_RSVD(v) \ + (((v) << 14) & BM_UARTAPP_LINECTRL2_RSVD) +#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC 8 +#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC 0x00003F00 +#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v) \ + (((v) << 8) & BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC) +#define BM_UARTAPP_LINECTRL2_SPS 0x00000080 +#define BP_UARTAPP_LINECTRL2_WLEN 5 +#define BM_UARTAPP_LINECTRL2_WLEN 0x00000060 +#define BF_UARTAPP_LINECTRL2_WLEN(v) \ + (((v) << 5) & BM_UARTAPP_LINECTRL2_WLEN) +#define BM_UARTAPP_LINECTRL2_FEN 0x00000010 +#define BM_UARTAPP_LINECTRL2_STP2 0x00000008 +#define BM_UARTAPP_LINECTRL2_EPS 0x00000004 +#define BM_UARTAPP_LINECTRL2_PEN 0x00000002 +#define BM_UARTAPP_LINECTRL2_RSVD1 0x00000001 + +#define HW_UARTAPP_INTR (0x00000050) +#define HW_UARTAPP_INTR_SET (0x00000054) +#define HW_UARTAPP_INTR_CLR (0x00000058) +#define HW_UARTAPP_INTR_TOG (0x0000005c) + +#define BP_UARTAPP_INTR_RSVD1 28 +#define BM_UARTAPP_INTR_RSVD1 0xF0000000 +#define BF_UARTAPP_INTR_RSVD1(v) \ + (((v) << 28) & BM_UARTAPP_INTR_RSVD1) +#define BM_UARTAPP_INTR_ABDIEN 0x08000000 +#define BM_UARTAPP_INTR_OEIEN 0x04000000 +#define BM_UARTAPP_INTR_BEIEN 0x02000000 +#define BM_UARTAPP_INTR_PEIEN 0x01000000 +#define BM_UARTAPP_INTR_FEIEN 0x00800000 +#define BM_UARTAPP_INTR_RTIEN 0x00400000 +#define BM_UARTAPP_INTR_TXIEN 0x00200000 +#define BM_UARTAPP_INTR_RXIEN 0x00100000 +#define BM_UARTAPP_INTR_DSRMIEN 0x00080000 +#define BM_UARTAPP_INTR_DCDMIEN 0x00040000 +#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 +#define BM_UARTAPP_INTR_RIMIEN 0x00010000 +#define BP_UARTAPP_INTR_RSVD2 12 +#define BM_UARTAPP_INTR_RSVD2 0x0000F000 +#define BF_UARTAPP_INTR_RSVD2(v) \ + (((v) << 12) & BM_UARTAPP_INTR_RSVD2) +#define BM_UARTAPP_INTR_ABDIS 0x00000800 +#define BM_UARTAPP_INTR_OEIS 0x00000400 +#define BM_UARTAPP_INTR_BEIS 0x00000200 +#define BM_UARTAPP_INTR_PEIS 0x00000100 +#define BM_UARTAPP_INTR_FEIS 0x00000080 +#define BM_UARTAPP_INTR_RTIS 0x00000040 +#define BM_UARTAPP_INTR_TXIS 0x00000020 +#define BM_UARTAPP_INTR_RXIS 0x00000010 +#define BM_UARTAPP_INTR_DSRMIS 0x00000008 +#define BM_UARTAPP_INTR_DCDMIS 0x00000004 +#define BM_UARTAPP_INTR_CTSMIS 0x00000002 +#define BM_UARTAPP_INTR_RIMIS 0x00000001 + +#define HW_UARTAPP_DATA (0x00000060) + +#define BP_UARTAPP_DATA_DATA 0 +#define BM_UARTAPP_DATA_DATA 0xFFFFFFFF +#define BF_UARTAPP_DATA_DATA(v) (v) + +#define HW_UARTAPP_STAT (0x00000070) + +#define BM_UARTAPP_STAT_PRESENT 0x80000000 +#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_UARTAPP_STAT_PRESENT__AVAILABLE 0x1 +#define BM_UARTAPP_STAT_HISPEED 0x40000000 +#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0 +#define BV_UARTAPP_STAT_HISPEED__AVAILABLE 0x1 +#define BM_UARTAPP_STAT_BUSY 0x20000000 +#define BM_UARTAPP_STAT_CTS 0x10000000 +#define BM_UARTAPP_STAT_TXFE 0x08000000 +#define BM_UARTAPP_STAT_RXFF 0x04000000 +#define BM_UARTAPP_STAT_TXFF 0x02000000 +#define BM_UARTAPP_STAT_RXFE 0x01000000 +#define BP_UARTAPP_STAT_RXBYTE_INVALID 20 +#define BM_UARTAPP_STAT_RXBYTE_INVALID 0x00F00000 +#define BF_UARTAPP_STAT_RXBYTE_INVALID(v) \ + (((v) << 20) & BM_UARTAPP_STAT_RXBYTE_INVALID) +#define BM_UARTAPP_STAT_OERR 0x00080000 +#define BM_UARTAPP_STAT_BERR 0x00040000 +#define BM_UARTAPP_STAT_PERR 0x00020000 +#define BM_UARTAPP_STAT_FERR 0x00010000 +#define BP_UARTAPP_STAT_RXCOUNT 0 +#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF +#define BF_UARTAPP_STAT_RXCOUNT(v) \ + (((v) << 0) & BM_UARTAPP_STAT_RXCOUNT) + +#define HW_UARTAPP_DEBUG (0x00000080) + +#define BP_UARTAPP_DEBUG_RXIBAUD_DIV 16 +#define BM_UARTAPP_DEBUG_RXIBAUD_DIV 0xFFFF0000 +#define BF_UARTAPP_DEBUG_RXIBAUD_DIV(v) \ + (((v) << 16) & BM_UARTAPP_DEBUG_RXIBAUD_DIV) +#define BP_UARTAPP_DEBUG_RXFBAUD_DIV 10 +#define BM_UARTAPP_DEBUG_RXFBAUD_DIV 0x0000FC00 +#define BF_UARTAPP_DEBUG_RXFBAUD_DIV(v) \ + (((v) << 10) & BM_UARTAPP_DEBUG_RXFBAUD_DIV) +#define BP_UARTAPP_DEBUG_RSVD1 6 +#define BM_UARTAPP_DEBUG_RSVD1 0x000003C0 +#define BF_UARTAPP_DEBUG_RSVD1(v) \ + (((v) << 6) & BM_UARTAPP_DEBUG_RSVD1) +#define BM_UARTAPP_DEBUG_TXDMARUN 0x00000020 +#define BM_UARTAPP_DEBUG_RXDMARUN 0x00000010 +#define BM_UARTAPP_DEBUG_TXCMDEND 0x00000008 +#define BM_UARTAPP_DEBUG_RXCMDEND 0x00000004 +#define BM_UARTAPP_DEBUG_TXDMARQ 0x00000002 +#define BM_UARTAPP_DEBUG_RXDMARQ 0x00000001 + +#define HW_UARTAPP_VERSION (0x00000090) + +#define BP_UARTAPP_VERSION_MAJOR 24 +#define BM_UARTAPP_VERSION_MAJOR 0xFF000000 +#define BF_UARTAPP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_UARTAPP_VERSION_MAJOR) +#define BP_UARTAPP_VERSION_MINOR 16 +#define BM_UARTAPP_VERSION_MINOR 0x00FF0000 +#define BF_UARTAPP_VERSION_MINOR(v) \ + (((v) << 16) & BM_UARTAPP_VERSION_MINOR) +#define BP_UARTAPP_VERSION_STEP 0 +#define BM_UARTAPP_VERSION_STEP 0x0000FFFF +#define BF_UARTAPP_VERSION_STEP(v) \ + (((v) << 0) & BM_UARTAPP_VERSION_STEP) + +#define HW_UARTAPP_AUTOBAUD (0x000000a0) + +#define BP_UARTAPP_AUTOBAUD_REFCHAR1 24 +#define BM_UARTAPP_AUTOBAUD_REFCHAR1 0xFF000000 +#define BF_UARTAPP_AUTOBAUD_REFCHAR1(v) \ + (((v) << 24) & BM_UARTAPP_AUTOBAUD_REFCHAR1) +#define BP_UARTAPP_AUTOBAUD_REFCHAR0 16 +#define BM_UARTAPP_AUTOBAUD_REFCHAR0 0x00FF0000 +#define BF_UARTAPP_AUTOBAUD_REFCHAR0(v) \ + (((v) << 16) & BM_UARTAPP_AUTOBAUD_REFCHAR0) +#define BP_UARTAPP_AUTOBAUD_RSVD1 5 +#define BM_UARTAPP_AUTOBAUD_RSVD1 0x0000FFE0 +#define BF_UARTAPP_AUTOBAUD_RSVD1(v) \ + (((v) << 5) & BM_UARTAPP_AUTOBAUD_RSVD1) +#define BM_UARTAPP_AUTOBAUD_UPDATE_TX 0x00000010 +#define BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS 0x00000008 +#define BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT 0x00000004 +#define BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT 0x00000002 +#define BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE 0x00000001 +#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c index 7f2830709512..4087aff757bb 100644 --- a/drivers/serial/serial_core.c +++ b/drivers/serial/serial_core.c @@ -2092,7 +2092,7 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport) */ if (uart_console(uport)) { uart_change_pm(state, 0); - uport->ops->set_termios(uport, &termios, NULL); + uport->ops->set_termios(uport, port->tty->termios, NULL); console_start(uport->cons); } diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 91c2f4f3af10..7248cb14cb5f 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -337,6 +337,18 @@ config SPI_NUC900 help SPI driver for Nuvoton NUC900 series ARM SoCs +config SPI_MXC + tristate "Freescale MXC CSPI controller" + depends on ARCH_MXC && SPI_MASTER + help + SPI driver for Freescale MXC CSPI interface + +config SPI_MXS + tristate "Freescale MXS SPI/SSP controller" + depends on ARCH_MXS && SPI_MASTER + help + SPI driver for Freescale MXS SoC SSP interface + # # Add new SPI master controllers in alphabetical order above this line # diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index e9cbd18217a0..ac1fb109a48c 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -47,6 +47,8 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o +obj-$(CONFIG_SPI_MXS) += spi_mxs.o +obj-$(CONFIG_SPI_MXC) += mxc_spi.o # special build for s3c24xx spi driver with fiq support spi_s3c24xx_hw-y := spi_s3c24xx.o diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c new file mode 100644 index 000000000000..8e255f48bd7a --- /dev/null +++ b/drivers/spi/mxc_spi.c @@ -0,0 +1,1316 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-licensisr_locke.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup SPI Configurable Serial Peripheral Interface (CSPI) Driver + */ + +/*! + * @file mxc_spi.c + * @brief This file contains the implementation of the SPI master controller services + * + * + * @ingroup SPI + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_CSPIRXDATA 0x00 +#define MXC_CSPITXDATA 0x04 +#define MXC_CSPICTRL 0x08 +#define MXC_CSPICONFIG 0x08 +#define MXC_CSPIINT 0x0C + +#define MXC_CSPICTRL_DISABLE 0x0 +#define MXC_CSPICTRL_SLAVE 0x0 +#define MXC_CSPICTRL_CSMASK 0x3 +#define MXC_CSPICTRL_SMC (1 << 3) + +#define MXC_CSPIINT_TEEN_SHIFT 0 +#define MXC_CSPIINT_THEN_SHIFT 1 +#define MXC_CSPIINT_TFEN_SHIFT 2 +#define MXC_CSPIINT_RREN_SHIFT 3 +#define MXC_CSPIINT_RHEN_SHIFT 4 +#define MXC_CSPIINT_RFEN_SHIFT 5 +#define MXC_CSPIINT_ROEN_SHIFT 6 + +#define MXC_HIGHPOL 0x0 +#define MXC_NOPHA 0x0 +#define MXC_LOWSSPOL 0x0 + +#define MXC_CSPISTAT_TE 0 +#define MXC_CSPISTAT_TH 1 +#define MXC_CSPISTAT_TF 2 +#define MXC_CSPISTAT_RR 3 +#define MXC_CSPISTAT_RH 4 +#define MXC_CSPISTAT_RF 5 +#define MXC_CSPISTAT_RO 6 + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) + +/*! + * @struct mxc_spi_unique_def + * @brief This structure contains information that differs with + * SPI master controller hardware version + */ +struct mxc_spi_unique_def { + /* Width of valid bits in MXC_CSPIINT */ + unsigned int intr_bit_shift; + /* Chip Select shift */ + unsigned int cs_shift; + /* Bit count shift */ + unsigned int bc_shift; + /* Bit count mask */ + unsigned int bc_mask; + /* Data Control shift */ + unsigned int drctrl_shift; + /* Transfer Complete shift */ + unsigned int xfer_complete; + /* Bit counnter overflow shift */ + unsigned int bc_overflow; + /* FIFO Size */ + unsigned int fifo_size; + /* Control reg address */ + unsigned int ctrl_reg_addr; + /* Status reg address */ + unsigned int stat_reg_addr; + /* Period reg address */ + unsigned int period_reg_addr; + /* Test reg address */ + unsigned int test_reg_addr; + /* Reset reg address */ + unsigned int reset_reg_addr; + /* SPI mode mask */ + unsigned int mode_mask; + /* SPI enable */ + unsigned int spi_enable; + /* XCH bit */ + unsigned int xch; + /* Spi mode shift */ + unsigned int mode_shift; + /* Spi master mode enable */ + unsigned int master_enable; + /* TX interrupt enable diff */ + unsigned int tx_inten_dif; + /* RX interrupt enable bit diff */ + unsigned int rx_inten_dif; + /* Interrupt status diff */ + unsigned int int_status_dif; + /* Low pol shift */ + unsigned int low_pol_shift; + /* Phase shift */ + unsigned int pha_shift; + /* SS control shift */ + unsigned int ss_ctrl_shift; + /* SS pol shift */ + unsigned int ss_pol_shift; + /* Maximum data rate */ + unsigned int max_data_rate; + /* Data mask */ + unsigned int data_mask; + /* Data shift */ + unsigned int data_shift; + /* Loopback control */ + unsigned int lbc; + /* RX count off */ + unsigned int rx_cnt_off; + /* RX count mask */ + unsigned int rx_cnt_mask; + /* Reset start */ + unsigned int reset_start; + /* SCLK control inactive state shift */ + unsigned int sclk_ctl_shift; +}; + +struct mxc_spi; + +/*! + * Structure to group together all the data buffers and functions + * used in data transfers. + */ +struct mxc_spi_xfer { + /* Transmit buffer */ + const void *tx_buf; + /* Receive buffer */ + void *rx_buf; + /* Data transfered count */ + unsigned int count; + /* Data received count, descending sequence, zero means no more data to + be received */ + unsigned int rx_count; + /* Function to read the FIFO data to rx_buf */ + void (*rx_get) (struct mxc_spi *, u32 val); + /* Function to get the data to be written to FIFO */ + u32(*tx_get) (struct mxc_spi *); +}; + +/*! + * This structure is a way for the low level driver to define their own + * \b spi_master structure. This structure includes the core \b spi_master + * structure that is provided by Linux SPI Framework/driver as an + * element and has other elements that are specifically required by this + * low-level driver. + */ +struct mxc_spi { + /* SPI Master and a simple I/O queue runner */ + struct spi_bitbang mxc_bitbang; + /* Completion flags used in data transfers */ + struct completion xfer_done; + /* Data transfer structure */ + struct mxc_spi_xfer transfer; + /* Resource structure, which will maintain base addresses and IRQs */ + struct resource *res; + /* Base address of CSPI, used in readl and writel */ + void *base; + /* CSPI IRQ number */ + int irq; + /* CSPI Clock id */ + struct clk *clk; + /* CSPI input clock SCLK */ + unsigned long spi_ipg_clk; + /* CSPI registers' bit pattern */ + struct mxc_spi_unique_def *spi_ver_def; + /* Control reg address */ + void *ctrl_addr; + /* Status reg address */ + void *stat_addr; + /* Period reg address */ + void *period_addr; + /* Test reg address */ + void *test_addr; + /* Reset reg address */ + void *reset_addr; + /* Chipselect active function */ + void (*chipselect_active) (int cspi_mode, int status, int chipselect); + /* Chipselect inactive function */ + void (*chipselect_inactive) (int cspi_mode, int status, int chipselect); +}; + +#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK +struct spi_chip_info { + int lb_enable; +}; + +static struct spi_chip_info lb_chip_info = { + .lb_enable = 1, +}; + +static struct spi_board_info loopback_info[] = { +#ifdef CONFIG_SPI_MXC_SELECT1 + { + .modalias = "spidev", + .controller_data = &lb_chip_info, + .irq = 0, + .max_speed_hz = 4000000, + .bus_num = 1, + .chip_select = 4, + }, +#endif +#ifdef CONFIG_SPI_MXC_SELECT2 + { + .modalias = "spidev", + .controller_data = &lb_chip_info, + .irq = 0, + .max_speed_hz = 4000000, + .bus_num = 2, + .chip_select = 4, + }, +#endif +#ifdef CONFIG_SPI_MXC_SELECT3 + { + .modalias = "spidev", + .controller_data = &lb_chip_info, + .irq = 0, + .max_speed_hz = 4000000, + .bus_num = 3, + .chip_select = 4, + }, +#endif +}; +#endif + +static struct mxc_spi_unique_def spi_ver_2_3 = { + .intr_bit_shift = 8, + .cs_shift = 18, + .bc_shift = 20, + .bc_mask = 0xFFF, + .drctrl_shift = 16, + .xfer_complete = (1 << 7), + .bc_overflow = 0, + .fifo_size = 64, + .ctrl_reg_addr = 4, + .stat_reg_addr = 0x18, + .period_reg_addr = 0x1C, + .test_reg_addr = 0x20, + .reset_reg_addr = 0x8, + .mode_mask = 0xF, + .spi_enable = 0x1, + .xch = (1 << 2), + .mode_shift = 4, + .master_enable = 0, + .tx_inten_dif = 0, + .rx_inten_dif = 0, + .int_status_dif = 0, + .low_pol_shift = 4, + .pha_shift = 0, + .ss_ctrl_shift = 8, + .ss_pol_shift = 12, + .max_data_rate = 0xF, + .data_mask = 0xFF, + .data_shift = 8, + .lbc = (1 << 31), + .rx_cnt_off = 8, + .rx_cnt_mask = (0x7F << 8), + .reset_start = 0, + .sclk_ctl_shift = 20, +}; + +static struct mxc_spi_unique_def spi_ver_0_7 = { + .intr_bit_shift = 8, + .cs_shift = 12, + .bc_shift = 20, + .bc_mask = 0xFFF, + .drctrl_shift = 8, + .xfer_complete = (1 << 7), + .bc_overflow = 0, + .fifo_size = 8, + .ctrl_reg_addr = 0, + .stat_reg_addr = 0x14, + .period_reg_addr = 0x18, + .test_reg_addr = 0x1C, + .reset_reg_addr = 0x0, + .mode_mask = 0x1, + .spi_enable = 0x1, + .xch = (1 << 2), + .mode_shift = 1, + .master_enable = 1 << 1, + .tx_inten_dif = 0, + .rx_inten_dif = 0, + .int_status_dif = 0, + .low_pol_shift = 4, + .pha_shift = 5, + .ss_ctrl_shift = 6, + .ss_pol_shift = 7, + .max_data_rate = 0x7, + .data_mask = 0x7, + .data_shift = 16, + .lbc = (1 << 14), + .rx_cnt_off = 4, + .rx_cnt_mask = (0xF << 4), + .reset_start = 1, +}; + +static struct mxc_spi_unique_def spi_ver_0_5 = { + .intr_bit_shift = 9, + .cs_shift = 12, + .bc_shift = 20, + .bc_mask = 0xFFF, + .drctrl_shift = 8, + .xfer_complete = (1 << 8), + .bc_overflow = (1 << 7), + .fifo_size = 8, + .ctrl_reg_addr = 0, + .stat_reg_addr = 0x14, + .period_reg_addr = 0x18, + .test_reg_addr = 0x1C, + .reset_reg_addr = 0x0, + .mode_mask = 0x1, + .spi_enable = 0x1, + .xch = (1 << 2), + .mode_shift = 1, + .master_enable = 1 << 1, + .tx_inten_dif = 0, + .rx_inten_dif = 0, + .int_status_dif = 0, + .low_pol_shift = 4, + .pha_shift = 5, + .ss_ctrl_shift = 6, + .ss_pol_shift = 7, + .max_data_rate = 0x7, + .data_mask = 0x7, + .data_shift = 16, + .lbc = (1 << 14), + .rx_cnt_off = 4, + .rx_cnt_mask = (0xF << 4), + .reset_start = 1, +}; + +static struct mxc_spi_unique_def spi_ver_0_4 = { + .intr_bit_shift = 9, + .cs_shift = 24, + .bc_shift = 8, + .bc_mask = 0x1F, + .drctrl_shift = 20, + .xfer_complete = (1 << 8), + .bc_overflow = (1 << 7), + .fifo_size = 8, + .ctrl_reg_addr = 0, + .stat_reg_addr = 0x14, + .period_reg_addr = 0x18, + .test_reg_addr = 0x1C, + .reset_reg_addr = 0x0, + .mode_mask = 0x1, + .spi_enable = 0x1, + .xch = (1 << 2), + .mode_shift = 1, + .master_enable = 1 << 1, + .tx_inten_dif = 0, + .rx_inten_dif = 0, + .int_status_dif = 0, + .low_pol_shift = 4, + .pha_shift = 5, + .ss_ctrl_shift = 6, + .ss_pol_shift = 7, + .max_data_rate = 0x7, + .data_mask = 0x7, + .data_shift = 16, + .lbc = (1 << 14), + .rx_cnt_off = 4, + .rx_cnt_mask = (0xF << 4), + .reset_start = 1, +}; + +static struct mxc_spi_unique_def spi_ver_0_0 = { + .intr_bit_shift = 18, + .cs_shift = 19, + .bc_shift = 0, + .bc_mask = 0x1F, + .drctrl_shift = 12, + .xfer_complete = (1 << 3), + .bc_overflow = (1 << 8), + .fifo_size = 8, + .ctrl_reg_addr = 0, + .stat_reg_addr = 0x0C, + .period_reg_addr = 0x14, + .test_reg_addr = 0x10, + .reset_reg_addr = 0x1C, + .mode_mask = 0x1, + .spi_enable = (1 << 10), + .xch = (1 << 9), + .mode_shift = 11, + .master_enable = 1 << 11, + .tx_inten_dif = 9, + .rx_inten_dif = 10, + .int_status_dif = 1, + .low_pol_shift = 5, + .pha_shift = 6, + .ss_ctrl_shift = 7, + .ss_pol_shift = 8, + .max_data_rate = 0x10, + .data_mask = 0x1F, + .data_shift = 14, + .lbc = (1 << 14), + .rx_cnt_off = 4, + .rx_cnt_mask = (0xF << 4), + .reset_start = 1, +}; + +extern void gpio_spi_active(int cspi_mod); +extern void gpio_spi_inactive(int cspi_mod); + +#define MXC_SPI_BUF_RX(type) \ +void mxc_spi_buf_rx_##type(struct mxc_spi *master_drv_data, u32 val)\ +{\ + type *rx = master_drv_data->transfer.rx_buf;\ + *rx++ = (type)val;\ + master_drv_data->transfer.rx_buf = rx;\ +} + +#define MXC_SPI_BUF_TX(type) \ +u32 mxc_spi_buf_tx_##type(struct mxc_spi *master_drv_data)\ +{\ + u32 val;\ + const type *tx = master_drv_data->transfer.tx_buf;\ + val = *tx++;\ + master_drv_data->transfer.tx_buf = tx;\ + return val;\ +} + +MXC_SPI_BUF_RX(u8) + MXC_SPI_BUF_TX(u8) + MXC_SPI_BUF_RX(u16) + MXC_SPI_BUF_TX(u16) + MXC_SPI_BUF_RX(u32) + MXC_SPI_BUF_TX(u32) + +/*! + * This function enables CSPI interrupt(s) + * + * @param master_data the pointer to mxc_spi structure + * @param irqs the irq(s) to set (can be a combination) + * + * @return This function returns 0 if successful, -1 otherwise. + */ +static int spi_enable_interrupt(struct mxc_spi *master_data, unsigned int irqs) +{ + if (irqs & ~((1 << master_data->spi_ver_def->intr_bit_shift) - 1)) { + return -1; + } + + __raw_writel((irqs | __raw_readl(MXC_CSPIINT + master_data->ctrl_addr)), + MXC_CSPIINT + master_data->ctrl_addr); + return 0; +} + +/*! + * This function disables CSPI interrupt(s) + * + * @param master_data the pointer to mxc_spi structure + * @param irqs the irq(s) to reset (can be a combination) + * + * @return This function returns 0 if successful, -1 otherwise. + */ +static int spi_disable_interrupt(struct mxc_spi *master_data, unsigned int irqs) +{ + if (irqs & ~((1 << master_data->spi_ver_def->intr_bit_shift) - 1)) { + return -1; + } + + __raw_writel((~irqs & + __raw_readl(MXC_CSPIINT + master_data->ctrl_addr)), + MXC_CSPIINT + master_data->ctrl_addr); + return 0; +} + +/*! + * This function sets the baud rate for the SPI module. + * + * @param master_data the pointer to mxc_spi structure + * @param baud the baud rate + * + * @return This function returns the baud rate divisor. + */ +static unsigned int spi_find_baudrate(struct mxc_spi *master_data, + unsigned int baud) +{ + unsigned int divisor; + unsigned int shift = 0; + + /* Calculate required divisor (rounded) */ + divisor = (master_data->spi_ipg_clk + baud / 2) / baud; + while (divisor >>= 1) + shift++; + + if (master_data->spi_ver_def == &spi_ver_0_0) { + shift = (shift - 1) * 2; + } else if (master_data->spi_ver_def == &spi_ver_2_3) { + shift = shift; + } else { + shift -= 2; + } + + if (shift > master_data->spi_ver_def->max_data_rate) + shift = master_data->spi_ver_def->max_data_rate; + + return shift << master_data->spi_ver_def->data_shift; +} + +/*! + * This function loads the transmit fifo. + * + * @param base the CSPI base address + * @param count number of words to put in the TxFIFO + * @param master_drv_data spi master structure + */ +static void spi_put_tx_data(void *base, unsigned int count, + struct mxc_spi *master_drv_data) +{ + unsigned int ctrl_reg; + unsigned int data; + int i = 0; + + /* Perform Tx transaction */ + for (i = 0; i < count; i++) { + data = master_drv_data->transfer.tx_get(master_drv_data); + __raw_writel(data, base + MXC_CSPITXDATA); + } + + ctrl_reg = __raw_readl(base + MXC_CSPICTRL); + + ctrl_reg |= master_drv_data->spi_ver_def->xch; + + __raw_writel(ctrl_reg, base + MXC_CSPICTRL); + + return; +} + +/*! + * This function configures the hardware CSPI for the current SPI device. + * It sets the word size, transfer mode, data rate for this device. + * + * @param spi the current SPI device + * @param is_active indicates whether to active/deactivate the current device + */ +void mxc_spi_chipselect(struct spi_device *spi, int is_active) +{ + struct mxc_spi *master_drv_data; + struct mxc_spi_xfer *ptransfer; + struct mxc_spi_unique_def *spi_ver_def; + unsigned int ctrl_reg = 0; + unsigned int config_reg = 0; + unsigned int xfer_len; + unsigned int cs_value; + + if (is_active == BITBANG_CS_INACTIVE) { + /*Need to deselect the slave */ + return; + } + + /* Get the master controller driver data from spi device's master */ + + master_drv_data = spi_master_get_devdata(spi->master); + clk_enable(master_drv_data->clk); + spi_ver_def = master_drv_data->spi_ver_def; + + xfer_len = spi->bits_per_word; + + if (spi_ver_def == &spi_ver_2_3) { + /* Control Register Settings for transfer to this slave */ + ctrl_reg = master_drv_data->spi_ver_def->spi_enable; + ctrl_reg |= + ((spi->chip_select & MXC_CSPICTRL_CSMASK) << spi_ver_def-> + cs_shift); + ctrl_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << spi_ver_def->mode_shift); + ctrl_reg |= + spi_find_baudrate(master_drv_data, spi->max_speed_hz); + ctrl_reg |= + (((xfer_len - + 1) & spi_ver_def->bc_mask) << spi_ver_def->bc_shift); + + if (spi->mode & SPI_CPHA) + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << + spi_ver_def->pha_shift); + + if ((spi->mode & SPI_CPOL)) { + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << + spi_ver_def->low_pol_shift); + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << + spi_ver_def->sclk_ctl_shift); + } + cs_value = (__raw_readl(MXC_CSPICONFIG + + master_drv_data->ctrl_addr) >> + spi_ver_def->ss_pol_shift) & spi_ver_def->mode_mask; + if (spi->mode & SPI_CS_HIGH) { + config_reg |= + ((((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) | cs_value) << + spi_ver_def->ss_pol_shift); + } else + config_reg |= + ((~((1 << (spi->chip_select & + MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) & cs_value) << + spi_ver_def->ss_pol_shift); + config_reg |= + (((1 << (spi->chip_select & MXC_CSPICTRL_CSMASK)) & + spi_ver_def->mode_mask) << spi_ver_def->ss_ctrl_shift); + __raw_writel(0, master_drv_data->base + MXC_CSPICTRL); + __raw_writel(ctrl_reg, master_drv_data->base + MXC_CSPICTRL); + __raw_writel(config_reg, + MXC_CSPICONFIG + master_drv_data->ctrl_addr); + } else { + /* Control Register Settings for transfer to this slave */ + ctrl_reg = master_drv_data->spi_ver_def->spi_enable; + ctrl_reg |= + (((spi->chip_select & MXC_CSPICTRL_CSMASK) << spi_ver_def-> + cs_shift) | spi_ver_def->mode_mask << + spi_ver_def->mode_shift); + ctrl_reg |= + spi_find_baudrate(master_drv_data, spi->max_speed_hz); + ctrl_reg |= + (((xfer_len - + 1) & spi_ver_def->bc_mask) << spi_ver_def->bc_shift); + if (spi->mode & SPI_CPHA) + ctrl_reg |= + spi_ver_def->mode_mask << spi_ver_def->pha_shift; + if (spi->mode & SPI_CPOL) + ctrl_reg |= + spi_ver_def->mode_mask << spi_ver_def-> + low_pol_shift; + if (spi->mode & SPI_CS_HIGH) + ctrl_reg |= + spi_ver_def->mode_mask << spi_ver_def->ss_pol_shift; + if (spi_ver_def == &spi_ver_0_7) + ctrl_reg |= + spi_ver_def->mode_mask << spi_ver_def-> + ss_ctrl_shift; + + __raw_writel(ctrl_reg, master_drv_data->base + MXC_CSPICTRL); + } + + /* Initialize the functions for transfer */ + ptransfer = &master_drv_data->transfer; + if (xfer_len <= 8) { + ptransfer->rx_get = mxc_spi_buf_rx_u8; + ptransfer->tx_get = mxc_spi_buf_tx_u8; + } else if (xfer_len <= 16) { + ptransfer->rx_get = mxc_spi_buf_rx_u16; + ptransfer->tx_get = mxc_spi_buf_tx_u16; + } else { + ptransfer->rx_get = mxc_spi_buf_rx_u32; + ptransfer->tx_get = mxc_spi_buf_tx_u32; + } +#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK + { + struct spi_chip_info *lb_chip = + (struct spi_chip_info *)spi->controller_data; + if (!lb_chip) + __raw_writel(0, master_drv_data->test_addr); + else if (lb_chip->lb_enable) + __raw_writel(spi_ver_def->lbc, + master_drv_data->test_addr); + } +#endif + clk_disable(master_drv_data->clk); + return; +} + +/*! + * This function is called when an interrupt occurs on the SPI modules. + * It is the interrupt handler for the SPI modules. + * + * @param irq the irq number + * @param dev_id the pointer on the device + * + * @return The function returns IRQ_HANDLED when handled. + */ +static irqreturn_t mxc_spi_isr(int irq, void *dev_id) +{ + struct mxc_spi *master_drv_data = dev_id; + irqreturn_t ret = IRQ_NONE; + unsigned int status; + int fifo_size; + unsigned int pass_counter; + + fifo_size = master_drv_data->spi_ver_def->fifo_size; + pass_counter = fifo_size; + + /* Read the interrupt status register to determine the source */ + status = __raw_readl(master_drv_data->stat_addr); + do { + u32 rx_tmp = + __raw_readl(master_drv_data->base + MXC_CSPIRXDATA); + + if (master_drv_data->transfer.rx_buf) + master_drv_data->transfer.rx_get(master_drv_data, + rx_tmp); + (master_drv_data->transfer.count)--; + (master_drv_data->transfer.rx_count)--; + ret = IRQ_HANDLED; + if (pass_counter-- == 0) { + break; + } + status = __raw_readl(master_drv_data->stat_addr); + } while (status & + (1 << + (MXC_CSPISTAT_RR + + master_drv_data->spi_ver_def->int_status_dif))); + + if (master_drv_data->transfer.rx_count) + return ret; + + if (master_drv_data->transfer.count) { + if (master_drv_data->transfer.tx_buf) { + u32 count = (master_drv_data->transfer.count > + fifo_size) ? fifo_size : + master_drv_data->transfer.count; + master_drv_data->transfer.rx_count = count; + spi_put_tx_data(master_drv_data->base, count, + master_drv_data); + } + } else { + complete(&master_drv_data->xfer_done); + } + + return ret; +} + +/*! + * This function initialize the current SPI device. + * + * @param spi the current SPI device. + * + */ +int mxc_spi_setup(struct spi_device *spi) +{ + if (spi->max_speed_hz < 0) { + return -EINVAL; + } + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + pr_debug("%s: mode %d, %u bpw, %d hz\n", __FUNCTION__, + spi->mode, spi->bits_per_word, spi->max_speed_hz); + + return 0; +} + +static int mxc_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) +{ + return 0; +} + +/*! + * This function is called when the data has to transfer from/to the + * current SPI device in poll mode + * + * @param spi the current spi device + * @param t the transfer request - read/write buffer pairs + * + * @return Returns 0 on success. + */ +int mxc_spi_poll_transfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct mxc_spi *master_drv_data = NULL; + int count, i; + volatile unsigned int status; + u32 rx_tmp; + u32 fifo_size; + int chipselect_status; + + mxc_spi_chipselect(spi, BITBANG_CS_ACTIVE); + + /* Get the master controller driver data from spi device's master */ + master_drv_data = spi_master_get_devdata(spi->master); + + chipselect_status = __raw_readl(MXC_CSPICONFIG + + master_drv_data->ctrl_addr); + chipselect_status >>= master_drv_data->spi_ver_def->ss_pol_shift & + master_drv_data->spi_ver_def->mode_mask; + if (master_drv_data->chipselect_active) + master_drv_data->chipselect_active(spi->master->bus_num, + chipselect_status, + (spi->chip_select & + MXC_CSPICTRL_CSMASK) + 1); + + clk_enable(master_drv_data->clk); + + /* Modify the Tx, Rx, Count */ + master_drv_data->transfer.tx_buf = t->tx_buf; + master_drv_data->transfer.rx_buf = t->rx_buf; + master_drv_data->transfer.count = t->len; + fifo_size = master_drv_data->spi_ver_def->fifo_size; + + count = (t->len > fifo_size) ? fifo_size : t->len; + spi_put_tx_data(master_drv_data->base, count, master_drv_data); + + while ((((status = __raw_readl(master_drv_data->test_addr)) & + master_drv_data->spi_ver_def->rx_cnt_mask) >> master_drv_data-> + spi_ver_def->rx_cnt_off) != count) + ; + + for (i = 0; i < count; i++) { + rx_tmp = __raw_readl(master_drv_data->base + MXC_CSPIRXDATA); + master_drv_data->transfer.rx_get(master_drv_data, rx_tmp); + } + + clk_disable(master_drv_data->clk); + if (master_drv_data->chipselect_inactive) + master_drv_data->chipselect_inactive(spi->master->bus_num, + chipselect_status, + (spi->chip_select & + MXC_CSPICTRL_CSMASK) + 1); + return 0; +} + +/*! + * This function is called when the data has to transfer from/to the + * current SPI device. It enables the Rx interrupt, initiates the transfer. + * When Rx interrupt occurs, the completion flag is set. It then disables + * the Rx interrupt. + * + * @param spi the current spi device + * @param t the transfer request - read/write buffer pairs + * + * @return Returns 0 on success -1 on failure. + */ +int mxc_spi_transfer(struct spi_device *spi, struct spi_transfer *t) +{ + struct mxc_spi *master_drv_data = NULL; + int count; + int chipselect_status; + u32 fifo_size; + + /* Get the master controller driver data from spi device's master */ + + master_drv_data = spi_master_get_devdata(spi->master); + + chipselect_status = __raw_readl(MXC_CSPICONFIG + + master_drv_data->ctrl_addr); + chipselect_status >>= master_drv_data->spi_ver_def->ss_pol_shift & + master_drv_data->spi_ver_def->mode_mask; + if (master_drv_data->chipselect_active) + master_drv_data->chipselect_active(spi->master->bus_num, + chipselect_status, + (spi->chip_select & + MXC_CSPICTRL_CSMASK) + 1); + + clk_enable(master_drv_data->clk); + /* Modify the Tx, Rx, Count */ + master_drv_data->transfer.tx_buf = t->tx_buf; + master_drv_data->transfer.rx_buf = t->rx_buf; + master_drv_data->transfer.count = t->len; + fifo_size = master_drv_data->spi_ver_def->fifo_size; + INIT_COMPLETION(master_drv_data->xfer_done); + + /* Enable the Rx Interrupts */ + + spi_enable_interrupt(master_drv_data, + 1 << (MXC_CSPIINT_RREN_SHIFT + + master_drv_data->spi_ver_def->rx_inten_dif)); + count = (t->len > fifo_size) ? fifo_size : t->len; + + /* Perform Tx transaction */ + master_drv_data->transfer.rx_count = count; + spi_put_tx_data(master_drv_data->base, count, master_drv_data); + + /* Wait for transfer completion */ + wait_for_completion(&master_drv_data->xfer_done); + + /* Disable the Rx Interrupts */ + + spi_disable_interrupt(master_drv_data, + 1 << (MXC_CSPIINT_RREN_SHIFT + + master_drv_data->spi_ver_def-> + rx_inten_dif)); + + clk_disable(master_drv_data->clk); + if (master_drv_data->chipselect_inactive) + master_drv_data->chipselect_inactive(spi->master->bus_num, + chipselect_status, + (spi->chip_select & + MXC_CSPICTRL_CSMASK) + 1); + return t->len - master_drv_data->transfer.count; +} + +/*! + * This function releases the current SPI device's resources. + * + * @param spi the current SPI device. + * + */ +void mxc_spi_cleanup(struct spi_device *spi) +{ +} + +/*! + * This function is called during the driver binding process. Based on the CSPI + * hardware module that is being probed this function adds the appropriate SPI module + * structure in the SPI core driver. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration and initialization + * of CSPI module. Otherwise returns specific error code. + */ +static int mxc_spi_probe(struct platform_device *pdev) +{ + struct mxc_spi_master *mxc_platform_info; + struct spi_master *master; + struct mxc_spi *master_drv_data = NULL; + unsigned int spi_ver; + int ret = -ENODEV; + + /* Get the platform specific data for this master device */ + + mxc_platform_info = (struct mxc_spi_master *)pdev->dev.platform_data; + if (!mxc_platform_info) { + dev_err(&pdev->dev, "can't get the platform data for CSPI\n"); + return -EINVAL; + } + + /* Allocate SPI master controller */ + + master = spi_alloc_master(&pdev->dev, sizeof(struct mxc_spi)); + if (!master) { + dev_err(&pdev->dev, "can't alloc for spi_master\n"); + return -ENOMEM; + } + + /* Set this device's driver data to master */ + + platform_set_drvdata(pdev, master); + + /* Set this master's data from platform_info */ + + master->bus_num = pdev->id + 1; + master->num_chipselect = mxc_platform_info->maxchipselect; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; +#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK + master->num_chipselect += 1; +#endif + /* Set the master controller driver data for this master */ + + master_drv_data = spi_master_get_devdata(master); + master_drv_data->mxc_bitbang.master = spi_master_get(master); + if (mxc_platform_info->chipselect_active) + master_drv_data->chipselect_active = + mxc_platform_info->chipselect_active; + if (mxc_platform_info->chipselect_inactive) + master_drv_data->chipselect_inactive = + mxc_platform_info->chipselect_inactive; + + /* Identify SPI version */ + + spi_ver = mxc_platform_info->spi_version; + if (spi_ver == 7) { + master_drv_data->spi_ver_def = &spi_ver_0_7; + } else if (spi_ver == 5) { + master_drv_data->spi_ver_def = &spi_ver_0_5; + } else if (spi_ver == 4) { + master_drv_data->spi_ver_def = &spi_ver_0_4; + } else if (spi_ver == 0) { + master_drv_data->spi_ver_def = &spi_ver_0_0; + } else if (spi_ver == 23) { + master_drv_data->spi_ver_def = &spi_ver_2_3; + } + + dev_dbg(&pdev->dev, "SPI_REV 0.%d\n", spi_ver); + + /* Set the master bitbang data */ + + master_drv_data->mxc_bitbang.chipselect = mxc_spi_chipselect; + master_drv_data->mxc_bitbang.txrx_bufs = mxc_spi_transfer; + master_drv_data->mxc_bitbang.master->setup = mxc_spi_setup; + master_drv_data->mxc_bitbang.master->cleanup = mxc_spi_cleanup; + master_drv_data->mxc_bitbang.setup_transfer = mxc_spi_setup_transfer; + + /* Initialize the completion object */ + + init_completion(&master_drv_data->xfer_done); + + /* Set the master controller register addresses and irqs */ + + master_drv_data->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!master_drv_data->res) { + dev_err(&pdev->dev, "can't get platform resource for CSPI%d\n", + master->bus_num); + ret = -ENOMEM; + goto err; + } + + if (!request_mem_region(master_drv_data->res->start, + master_drv_data->res->end - + master_drv_data->res->start + 1, pdev->name)) { + dev_err(&pdev->dev, "request_mem_region failed for CSPI%d\n", + master->bus_num); + ret = -ENOMEM; + goto err; + } + + master_drv_data->base = ioremap(master_drv_data->res->start, + master_drv_data->res->end - master_drv_data->res->start + 1); + if (!master_drv_data->base) { + dev_err(&pdev->dev, "invalid base address for CSPI%d\n", + master->bus_num); + ret = -EINVAL; + goto err1; + } + + master_drv_data->irq = platform_get_irq(pdev, 0); + if (master_drv_data->irq < 0) { + dev_err(&pdev->dev, "can't get IRQ for CSPI%d\n", + master->bus_num); + ret = -EINVAL; + goto err1; + } + + /* Register for SPI Interrupt */ + + ret = request_irq(master_drv_data->irq, mxc_spi_isr, + 0, "CSPI_IRQ", master_drv_data); + if (ret != 0) { + dev_err(&pdev->dev, "request_irq failed for CSPI%d\n", + master->bus_num); + goto err1; + } + + /* Setup any GPIO active */ + + gpio_spi_active(master->bus_num - 1); + + /* Enable the CSPI Clock, CSPI Module, set as a master */ + + master_drv_data->ctrl_addr = + master_drv_data->base + master_drv_data->spi_ver_def->ctrl_reg_addr; + master_drv_data->stat_addr = + master_drv_data->base + master_drv_data->spi_ver_def->stat_reg_addr; + master_drv_data->period_addr = + master_drv_data->base + + master_drv_data->spi_ver_def->period_reg_addr; + master_drv_data->test_addr = + master_drv_data->base + master_drv_data->spi_ver_def->test_reg_addr; + master_drv_data->reset_addr = + master_drv_data->base + + master_drv_data->spi_ver_def->reset_reg_addr; + + master_drv_data->clk = clk_get(&pdev->dev, "cspi_clk"); + clk_enable(master_drv_data->clk); + master_drv_data->spi_ipg_clk = clk_get_rate(master_drv_data->clk); + + __raw_writel(master_drv_data->spi_ver_def->reset_start, + master_drv_data->reset_addr); + udelay(1); + __raw_writel((master_drv_data->spi_ver_def->spi_enable + + master_drv_data->spi_ver_def->master_enable), + master_drv_data->base + MXC_CSPICTRL); + __raw_writel(MXC_CSPIPERIOD_32KHZ, master_drv_data->period_addr); + __raw_writel(0, MXC_CSPIINT + master_drv_data->ctrl_addr); + + /* Start the SPI Master Controller driver */ + + ret = spi_bitbang_start(&master_drv_data->mxc_bitbang); + + if (ret != 0) + goto err2; + + printk(KERN_INFO "CSPI: %s-%d probed\n", pdev->name, pdev->id); + +#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK + { + int i; + struct spi_board_info *bi = &loopback_info[0]; + for (i = 0; i < ARRAY_SIZE(loopback_info); i++, bi++) { + if (bi->bus_num != master->bus_num) + continue; + + dev_info(&pdev->dev, + "registering loopback device '%s'\n", + bi->modalias); + + spi_new_device(master, bi); + } + } +#endif + clk_disable(master_drv_data->clk); + return ret; + + err2: + gpio_spi_inactive(master->bus_num - 1); + clk_disable(master_drv_data->clk); + clk_put(master_drv_data->clk); + free_irq(master_drv_data->irq, master_drv_data); + err1: + iounmap(master_drv_data->base); + release_mem_region(pdev->resource[0].start, + pdev->resource[0].end - pdev->resource[0].start + 1); + err: + spi_master_put(master); + kfree(master); + platform_set_drvdata(pdev, NULL); + return ret; +} + +/*! + * Dissociates the driver from the SPI master controller. Disables the CSPI module. + * It handles the release of SPI resources like IRQ, memory,..etc. + * + * @param pdev the device structure used to give information on which SPI + * to remove + * + * @return The function always returns 0. + */ +static int mxc_spi_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + + if (master) { + struct mxc_spi *master_drv_data = + spi_master_get_devdata(master); + + gpio_spi_inactive(master->bus_num - 1); + + /* Disable the CSPI module */ + clk_enable(master_drv_data->clk); + __raw_writel(MXC_CSPICTRL_DISABLE, + master_drv_data->base + MXC_CSPICTRL); + clk_disable(master_drv_data->clk); + /* Unregister for SPI Interrupt */ + + free_irq(master_drv_data->irq, master_drv_data); + + iounmap(master_drv_data->base); + release_mem_region(master_drv_data->res->start, + master_drv_data->res->end - + master_drv_data->res->start + 1); + + /* Stop the SPI Master Controller driver */ + + spi_bitbang_stop(&master_drv_data->mxc_bitbang); + + spi_master_put(master); + } + + printk(KERN_INFO "CSPI: %s-%d removed\n", pdev->name, pdev->id); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int spi_bitbang_suspend(struct spi_bitbang *bitbang) +{ + unsigned long flags; + unsigned limit = 500; + + spin_lock_irqsave(&bitbang->lock, flags); + while (!list_empty(&bitbang->queue) && limit--) { + spin_unlock_irqrestore(&bitbang->lock, flags); + + dev_dbg(&bitbang->master->dev, "wait for queue\n"); + msleep(10); + + spin_lock_irqsave(&bitbang->lock, flags); + } + if (!list_empty(&bitbang->queue)) { + dev_err(&bitbang->master->dev, "queue didn't empty\n"); + spin_unlock_irqrestore(&bitbang->lock, flags); + return -EBUSY; + } + spin_unlock_irqrestore(&bitbang->lock, flags); + + return 0; +} + +static void spi_bitbang_resume(struct spi_bitbang *bitbang) +{ + spin_lock_init(&bitbang->lock); + INIT_LIST_HEAD(&bitbang->queue); + + bitbang->busy = 0; +} + +/*! + * This function puts the SPI master controller in low-power mode/state. + * + * @param pdev the device structure used to give information on which SDHC + * to suspend + * @param state the power state the device is entering + * + * @return The function always returns 0. + */ +static int mxc_spi_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct mxc_spi *master_drv_data = spi_master_get_devdata(master); + int ret = 0; + + spi_bitbang_suspend(&master_drv_data->mxc_bitbang); + clk_enable(master_drv_data->clk); + __raw_writel(MXC_CSPICTRL_DISABLE, + master_drv_data->base + MXC_CSPICTRL); + clk_disable(master_drv_data->clk); + gpio_spi_inactive(master->bus_num - 1); + + return ret; +} + +/*! + * This function brings the SPI master controller back from low-power state. + * + * @param pdev the device structure used to give information on which SDHC + * to resume + * + * @return The function always returns 0. + */ +static int mxc_spi_resume(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct mxc_spi *master_drv_data = spi_master_get_devdata(master); + + gpio_spi_active(master->bus_num - 1); + + spi_bitbang_resume(&master_drv_data->mxc_bitbang); + clk_enable(master_drv_data->clk); + __raw_writel((master_drv_data->spi_ver_def->spi_enable + + master_drv_data->spi_ver_def->master_enable), + master_drv_data->base + MXC_CSPICTRL); + clk_disable(master_drv_data->clk); + + return 0; +} +#else +#define mxc_spi_suspend NULL +#define mxc_spi_resume NULL +#endif /* CONFIG_PM */ + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxc_spi_driver = { + .driver = { + .name = "mxc_spi", + .owner = THIS_MODULE, + }, + .probe = mxc_spi_probe, + .remove = mxc_spi_remove, + .suspend = mxc_spi_suspend, + .resume = mxc_spi_resume, +}; + +/*! + * This function implements the init function of the SPI device. + * It is called when the module is loaded. It enables the required + * clocks to CSPI module(if any) and activates necessary GPIO pins. + * + * @return This function returns 0. + */ +static int __init mxc_spi_init(void) +{ + pr_debug("Registering the SPI Controller Driver\n"); + return platform_driver_register(&mxc_spi_driver); +} + +/*! + * This function implements the exit function of the SPI device. + * It is called when the module is unloaded. It deactivates the + * the GPIO pin associated with CSPI hardware modules. + * + */ +static void __exit mxc_spi_exit(void) +{ + pr_debug("Unregistering the SPI Controller Driver\n"); + platform_driver_unregister(&mxc_spi_driver); +} + +subsys_initcall(mxc_spi_init); +module_exit(mxc_spi_exit); + +MODULE_DESCRIPTION("SPI Master Controller driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi_mxs.c b/drivers/spi/spi_mxs.c new file mode 100644 index 000000000000..c6e66fd9a711 --- /dev/null +++ b/drivers/spi/spi_mxs.c @@ -0,0 +1,750 @@ +/* + * Freescale MXS SPI master driver + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "spi_mxs.h" + +#ifndef BF_SSP_CTRL0_XFER_COUNT +#define BF_SSP_CTRL0_XFER_COUNT(len) HW_SSP_VERSION +#endif +#ifndef BM_SSP_CTRL0_XFER_COUNT +#define BM_SSP_CTRL0_XFER_COUNT HW_SSP_VERSION +#endif + +#ifndef BF_SSP_XFER_SIZE_XFER_COUNT +#define BF_SSP_XFER_SIZE_XFER_COUNT(len) HW_SSP_VERSION +#endif +#ifndef BM_SSP_XFER_SIZE_XFER_COUNT +#define BM_SSP_XFER_SIZE_XFER_COUNT HW_SSP_VERSION +#endif + +#ifndef HW_SSP_XFER_SIZE +#define HW_SSP_XFER_SIZE HW_SSP_VERSION +#endif + +/* 0 means DMA modei(recommended, default), !0 - PIO mode */ +static int pio /* = 0 */ ; +static int debug; + +/** + * mxs_spi_init_hw + * + * Initialize the SSP port + */ +static int mxs_spi_init_hw(struct mxs_spi *ss) +{ + struct mxs_spi_platform_data *pdata; + int err; + + pdata = ss->master_dev->platform_data; + + if (!pdata->clk) { + dev_err(ss->master_dev, "unknown clock\n"); + err = -EINVAL; + goto out; + } + ss->clk = clk_get(ss->master_dev, pdata->clk); + if (IS_ERR(ss->clk)) { + err = PTR_ERR(ss->clk); + goto out; + } + clk_enable(ss->clk); + + mxs_reset_block((void *)ss->regs, 0); + mxs_dma_reset(ss->dma); + + return 0; + +out: + return err; +} + +static void mxs_spi_release_hw(struct mxs_spi *ss) +{ + if (ss->clk && !IS_ERR(ss->clk)) { + clk_disable(ss->clk); + clk_put(ss->clk); + } +} + +static int mxs_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) +{ + u8 bits_per_word; + u32 hz; + struct mxs_spi *ss /* = spi_master_get_devdata(spi->master) */ ; + u16 rate; + + ss = spi_master_get_devdata(spi->master); + + bits_per_word = spi->bits_per_word; + if (t && t->bits_per_word) + bits_per_word = t->bits_per_word; + + /* + Calculate speed: + - by default, use maximum speed from ssp clk + - if device overrides it, use it + - if transfer specifies other speed, use transfer's one + */ + hz = 1000 * ss->speed_khz / ss->divider; + if (spi->max_speed_hz) + hz = min(hz, spi->max_speed_hz); + if (t && t->speed_hz) + hz = min(hz, t->speed_hz); + + if (hz == 0) { + dev_err(&spi->dev, "Cannot continue with zero clock\n"); + return -EINVAL; + } + + if (bits_per_word != 8) { + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", + __func__, bits_per_word); + return -EINVAL; + } + + dev_dbg(&spi->dev, "Requested clk rate = %uHz, max = %ukHz/%d = %uHz\n", + hz, ss->speed_khz, ss->divider, + ss->speed_khz * 1000 / ss->divider); + + if (ss->speed_khz * 1000 / ss->divider < hz) { + dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n", + __func__, hz); + return -EINVAL; + } + + rate = 1000 * ss->speed_khz / ss->divider / hz; + + __raw_writel(BF_SSP_TIMING_CLOCK_DIVIDE(ss->divider) | + BF_SSP_TIMING_CLOCK_RATE(rate - 1), + ss->regs + HW_SSP_TIMING); + + __raw_writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | + BF_SSP_CTRL1_WORD_LENGTH + (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) | + ((spi->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | + ((spi->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0) | + (pio ? 0 : BM_SSP_CTRL1_DMA_ENABLE), + ss->regs + HW_SSP_CTRL1); + + __raw_writel(0x00, ss->regs + HW_SSP_CMD0_SET); + + return 0; +} + +static void mxs_spi_cleanup(struct spi_device *spi) +{ + return; +} + +/* the spi->mode bits understood by this driver: */ +#define MODEBITS (SPI_CPOL | SPI_CPHA) +static int mxs_spi_setup(struct spi_device *spi) +{ + struct mxs_spi *ss; + int err = 0; + + ss = spi_master_get_devdata(spi->master); + + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + if (spi->mode & ~MODEBITS) { + dev_err(&spi->dev, "%s: unsupported mode bits %x\n", + __func__, spi->mode & ~MODEBITS); + err = -EINVAL; + goto out; + } + + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w\n", + __func__, spi->mode & MODEBITS, spi->bits_per_word); + + err = mxs_spi_setup_transfer(spi, NULL); + if (err) + goto out; + return 0; + +out: + dev_err(&spi->dev, "Failed to setup transfer, error = %d\n", err); + return err; +} + +static inline u32 mxs_spi_cs(unsigned cs) +{ + return ((cs & 1) ? BM_SSP_CTRL0_WAIT_FOR_CMD : 0) | + ((cs & 2) ? BM_SSP_CTRL0_WAIT_FOR_IRQ : 0); +} + +static int mxs_spi_txrx_dma(struct mxs_spi *ss, int cs, + unsigned char *buf, dma_addr_t dma_buf, int len, + int *first, int *last, int write) +{ + u32 c0 = 0, xfer_size = 0; + dma_addr_t spi_buf_dma = dma_buf; + int count, status = 0; + enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; + + c0 |= (*first ? BM_SSP_CTRL0_LOCK_CS : 0); + c0 |= (*last ? BM_SSP_CTRL0_IGNORE_CRC : 0); + c0 |= (write ? 0 : BM_SSP_CTRL0_READ); + c0 |= BM_SSP_CTRL0_DATA_XFER; + + c0 |= mxs_spi_cs(cs); + + if (ss->ver_major > 3) { + xfer_size = BF_SSP_XFER_SIZE_XFER_COUNT(len); + __raw_writel(xfer_size, ss->regs + HW_SSP_XFER_SIZE); + } else { + c0 |= BF_SSP_CTRL0_XFER_COUNT(len); + } + + if (!dma_buf) + spi_buf_dma = dma_map_single(ss->master_dev, buf, len, dir); + + ss->pdesc->cmd.cmd.bits.bytes = len; + ss->pdesc->cmd.cmd.bits.pio_words = 1; + ss->pdesc->cmd.cmd.bits.wait4end = 1; + ss->pdesc->cmd.cmd.bits.dec_sem = 1; + ss->pdesc->cmd.cmd.bits.irq = 1; + ss->pdesc->cmd.cmd.bits.command = write ? DMA_READ : DMA_WRITE; + ss->pdesc->cmd.address = spi_buf_dma; + ss->pdesc->cmd.pio_words[0] = c0; + mxs_dma_desc_append(ss->dma, ss->pdesc); + + mxs_dma_reset(ss->dma); + mxs_dma_ack_irq(ss->dma); + mxs_dma_enable_irq(ss->dma, 1); + init_completion(&ss->done); + mxs_dma_enable(ss->dma); + wait_for_completion(&ss->done); + count = 10000; + while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN) + && count--) + continue; + if (count <= 0) { + printk(KERN_ERR "%c: timeout on line %s:%d\n", + write ? 'W' : 'C', __func__, __LINE__); + status = -ETIMEDOUT; + } + + if (!dma_buf) + dma_unmap_single(ss->master_dev, spi_buf_dma, len, dir); + + return status; +} + +static inline void mxs_spi_enable(struct mxs_spi *ss) +{ + __raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_SET); + __raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_CLR); +} + +static inline void mxs_spi_disable(struct mxs_spi *ss) +{ + __raw_writel(BM_SSP_CTRL0_LOCK_CS, ss->regs + HW_SSP_CTRL0_CLR); + __raw_writel(BM_SSP_CTRL0_IGNORE_CRC, ss->regs + HW_SSP_CTRL0_SET); +} + +static int mxs_spi_txrx_pio(struct mxs_spi *ss, int cs, + unsigned char *buf, int len, + int *first, int *last, int write) +{ + int count; + + if (*first) { + mxs_spi_enable(ss); + *first = 0; + } + + __raw_writel(mxs_spi_cs(cs), ss->regs + HW_SSP_CTRL0_SET); + + while (len--) { + if (*last && len == 0) { + mxs_spi_disable(ss); + *last = 0; + } + + /* byte-by-byte */ + if (ss->ver_major > 3) { + __raw_writel(1, ss->regs + HW_SSP_XFER_SIZE); + } else { + __raw_writel(BM_SSP_CTRL0_XFER_COUNT, + ss->regs + HW_SSP_CTRL0_CLR); + __raw_writel(1, ss->regs + HW_SSP_CTRL0_SET); + } + + if (write) + __raw_writel(BM_SSP_CTRL0_READ, + ss->regs + HW_SSP_CTRL0_CLR); + else + __raw_writel(BM_SSP_CTRL0_READ, + ss->regs + HW_SSP_CTRL0_SET); + + /* Run! */ + __raw_writel(BM_SSP_CTRL0_RUN, ss->regs + HW_SSP_CTRL0_SET); + count = 10000; + while (((__raw_readl(ss->regs + HW_SSP_CTRL0) & + BM_SSP_CTRL0_RUN) == 0) && count--) + continue; + if (count <= 0) { + printk(KERN_ERR "%c: timeout on line %s:%d\n", + write ? 'W' : 'C', __func__, __LINE__); + break; + } + + if (write) + __raw_writel(*buf, ss->regs + HW_SSP_DATA); + + /* Set TRANSFER */ + __raw_writel(BM_SSP_CTRL0_DATA_XFER, + ss->regs + HW_SSP_CTRL0_SET); + + if (!write) { + count = 10000; + while (count-- && + (__raw_readl(ss->regs + HW_SSP_STATUS) & + BM_SSP_STATUS_FIFO_EMPTY)) + continue; + if (count <= 0) { + printk(KERN_ERR "%c: timeout on line %s:%d\n", + write ? 'W' : 'C', __func__, __LINE__); + break; + } + *buf = (__raw_readl(ss->regs + HW_SSP_DATA) & 0xFF); + } + + count = 10000; + while ((__raw_readl(ss->regs + HW_SSP_CTRL0) & BM_SSP_CTRL0_RUN) + && count--) + continue; + if (count <= 0) { + printk(KERN_ERR "%c: timeout on line %s:%d\n", + write ? 'W' : 'C', __func__, __LINE__); + break; + } + + /* advance to the next byte */ + buf++; + } + return len < 0 ? 0 : -ETIMEDOUT; +} + +static int mxs_spi_handle_message(struct mxs_spi *ss, struct spi_message *m) +{ + int first, last; + struct spi_transfer *t, *tmp_t; + int status = 0; + int cs; + + first = last = 0; + + cs = m->spi->chip_select; + + list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) { + + mxs_spi_setup_transfer(m->spi, t); + + if (&t->transfer_list == m->transfers.next) + first = !0; + if (&t->transfer_list == m->transfers.prev) + last = !0; + if (t->rx_buf && t->tx_buf) { + pr_debug("%s: cannot send and receive simultaneously\n", + __func__); + return -EINVAL; + } + + /* + REVISIT: + here driver completely ignores setting of t->cs_change + */ + if (t->tx_buf) { + status = pio ? + mxs_spi_txrx_pio(ss, cs, (void *)t->tx_buf, + t->len, &first, &last, 1) : + mxs_spi_txrx_dma(ss, cs, (void *)t->tx_buf, + t->tx_dma, t->len, &first, &last, + 1); + if (debug) { + if (t->len < 0x10) + print_hex_dump_bytes("Tx ", + DUMP_PREFIX_OFFSET, + t->tx_buf, t->len); + else + pr_debug("Tx: %d bytes\n", t->len); + } + } + if (t->rx_buf) { + status = pio ? + mxs_spi_txrx_pio(ss, cs, t->rx_buf, + t->len, &first, &last, 0) : + mxs_spi_txrx_dma(ss, cs, t->rx_buf, + t->rx_dma, t->len, &first, &last, + 0); + if (debug) { + if (t->len < 0x10) + print_hex_dump_bytes("Rx ", + DUMP_PREFIX_OFFSET, + t->rx_buf, t->len); + else + pr_debug("Rx: %d bytes\n", t->len); + } + } + + m->actual_length += t->len; + if (status) + break; + + first = last = 0; + + } + return status; +} + +/** + * mxs_spi_handle + * + * The workhorse of the driver - it handles messages from the list + * + **/ +static void mxs_spi_handle(struct work_struct *w) +{ + struct mxs_spi *ss = container_of(w, struct mxs_spi, work); + unsigned long flags; + struct spi_message *m; + + BUG_ON(w == NULL); + + spin_lock_irqsave(&ss->lock, flags); + while (!list_empty(&ss->queue)) { + m = list_entry(ss->queue.next, struct spi_message, queue); + list_del_init(&m->queue); + spin_unlock_irqrestore(&ss->lock, flags); + + m->status = mxs_spi_handle_message(ss, m); + if (m->complete) + m->complete(m->context); + + spin_lock_irqsave(&ss->lock, flags); + } + spin_unlock_irqrestore(&ss->lock, flags); + + return; +} + +/** + * mxs_spi_transfer + * + * Called indirectly from spi_async, queues all the messages to + * spi_handle_message + * + * @spi: spi device + * @m: message to be queued +**/ +static int mxs_spi_transfer(struct spi_device *spi, struct spi_message *m) +{ + struct mxs_spi *ss = spi_master_get_devdata(spi->master); + unsigned long flags; + + m->actual_length = 0; + m->status = -EINPROGRESS; + spin_lock_irqsave(&ss->lock, flags); + list_add_tail(&m->queue, &ss->queue); + queue_work(ss->workqueue, &ss->work); + spin_unlock_irqrestore(&ss->lock, flags); + return 0; +} + +static irqreturn_t mxs_spi_irq_dma(int irq, void *dev_id) +{ + struct mxs_spi *ss = dev_id; + + mxs_dma_ack_irq(ss->dma); + mxs_dma_cooked(ss->dma, NULL); + complete(&ss->done); + return IRQ_HANDLED; +} + +static irqreturn_t mxs_spi_irq_err(int irq, void *dev_id) +{ + struct mxs_spi *ss = dev_id; + u32 c1, st; + + c1 = __raw_readl(ss->regs + HW_SSP_CTRL1); + st = __raw_readl(ss->regs + HW_SSP_STATUS); + printk(KERN_ERR "IRQ - ERROR!, status = 0x%08X, c1 = 0x%08X\n", st, c1); + __raw_writel(c1 & 0xCCCC0000, ss->regs + HW_SSP_CTRL1_CLR); + + return IRQ_HANDLED; +} + +static int __init mxs_spi_probe(struct platform_device *dev) +{ + struct mxs_spi_platform_data *pdata; + int err = 0; + struct spi_master *master; + struct mxs_spi *ss; + struct resource *r; + u32 mem; + + pdata = dev->dev.platform_data; + + if (pdata && pdata->hw_pin_init) { + err = pdata->hw_pin_init(); + if (err) + goto out0; + } + + /* Get resources(memory, IRQ) associated with the device */ + master = spi_alloc_master(&dev->dev, sizeof(struct mxs_spi)); + + if (master == NULL) { + err = -ENOMEM; + goto out0; + } + + platform_set_drvdata(dev, master); + + r = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (r == NULL) { + err = -ENODEV; + goto out_put_master; + } + + ss = spi_master_get_devdata(master); + ss->master_dev = &dev->dev; + + INIT_WORK(&ss->work, mxs_spi_handle); + INIT_LIST_HEAD(&ss->queue); + spin_lock_init(&ss->lock); + ss->workqueue = create_singlethread_workqueue(dev_name(&dev->dev)); + master->transfer = mxs_spi_transfer; + master->setup = mxs_spi_setup; + master->cleanup = mxs_spi_cleanup; + + if (!request_mem_region(r->start, + resource_size(r), dev_name(&dev->dev))) { + err = -ENXIO; + goto out_put_master; + } + mem = r->start; + + ss->regs = IO_ADDRESS(r->start); + + ss->irq_dma = platform_get_irq(dev, 0); + if (ss->irq_dma < 0) { + err = -ENXIO; + goto out_put_master; + } + ss->irq_err = platform_get_irq(dev, 1); + if (ss->irq_err < 0) { + err = -ENXIO; + goto out_put_master; + } + + r = platform_get_resource(dev, IORESOURCE_DMA, 0); + if (r == NULL) { + err = -ENODEV; + goto out_put_master; + } + + ss->dma = r->start; + err = mxs_dma_request(ss->dma, &dev->dev, (char *)dev_name(&dev->dev)); + if (err) + goto out_put_master; + + ss->pdesc = mxs_dma_alloc_desc(); + if (ss->pdesc == NULL || IS_ERR(ss->pdesc)) { + err = -ENOMEM; + goto out_free_dma; + } + + master->bus_num = dev->id + 1; + master->num_chipselect = 1; + + /* SPI controller initializations */ + err = mxs_spi_init_hw(ss); + if (err) { + dev_dbg(&dev->dev, "cannot initialize hardware\n"); + goto out_free_dma_desc; + } + + clk_set_rate(ss->clk, 120 * 1000 * 1000); + ss->speed_khz = clk_get_rate(ss->clk) / 1000; + ss->divider = 2; + dev_info(&dev->dev, "Max possible speed %d = %ld/%d kHz\n", + ss->speed_khz, clk_get_rate(ss->clk), ss->divider); + + ss->ver_major = __raw_readl(ss->regs + HW_SSP_VERSION) >> 24; + + /* Register for SPI Interrupt */ + err = request_irq(ss->irq_dma, mxs_spi_irq_dma, 0, + dev_name(&dev->dev), ss); + if (err) { + dev_dbg(&dev->dev, "request_irq failed, %d\n", err); + goto out_release_hw; + } + err = request_irq(ss->irq_err, mxs_spi_irq_err, IRQF_SHARED, + dev_name(&dev->dev), ss); + if (err) { + dev_dbg(&dev->dev, "request_irq(error) failed, %d\n", err); + goto out_free_irq; + } + + err = spi_register_master(master); + if (err) { + dev_dbg(&dev->dev, "cannot register spi master, %d\n", err); + goto out_free_irq_2; + } + dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d, bus %d, %s ver_major %d\n", + mem, (u32) ss->regs, ss->irq_dma, + master->bus_num, pio ? "PIO" : "DMA", ss->ver_major); + return 0; + +out_free_irq_2: + free_irq(ss->irq_err, ss); +out_free_irq: + free_irq(ss->irq_dma, ss); +out_free_dma_desc: + mxs_dma_free_desc(ss->pdesc); +out_free_dma: + mxs_dma_release(ss->dma, &dev->dev); +out_release_hw: + mxs_spi_release_hw(ss); +out_put_master: + spi_master_put(master); +out0: + return err; +} + +static int __devexit mxs_spi_remove(struct platform_device *dev) +{ + struct mxs_spi *ss; + struct spi_master *master; + struct mxs_spi_platform_data *pdata = dev->dev.platform_data; + + if (pdata && pdata->hw_pin_release) + pdata->hw_pin_release(); + + master = platform_get_drvdata(dev); + if (master == NULL) + goto out0; + ss = spi_master_get_devdata(master); + if (ss == NULL) + goto out1; + free_irq(ss->irq_err, ss); + free_irq(ss->irq_dma, ss); + if (ss->workqueue) + destroy_workqueue(ss->workqueue); + mxs_dma_free_desc(ss->pdesc); + mxs_dma_release(ss->dma, &dev->dev); + mxs_spi_release_hw(ss); + platform_set_drvdata(dev, 0); +out1: + spi_master_put(master); +out0: + return 0; +} + +#ifdef CONFIG_PM +static int mxs_spi_suspend(struct platform_device *pdev, pm_message_t pmsg) +{ + struct mxs_spi *ss; + struct spi_master *master; + + master = platform_get_drvdata(pdev); + ss = spi_master_get_devdata(master); + + ss->saved_timings = __raw_readl(ss->regs + HW_SSP_TIMING); + clk_disable(ss->clk); + + return 0; +} + +static int mxs_spi_resume(struct platform_device *pdev) +{ + struct mxs_spi *ss; + struct spi_master *master; + + master = platform_get_drvdata(pdev); + ss = spi_master_get_devdata(master); + + clk_enable(ss->clk); + __raw_writel(BM_SSP_CTRL0_SFTRST | BM_SSP_CTRL0_CLKGATE, + ss->regs + HW_SSP_CTRL0_CLR); + __raw_writel(ss->saved_timings, ss->regs + HW_SSP_TIMING); + + return 0; +} + +#else +#define mxs_spi_suspend NULL +#define mxs_spi_resume NULL +#endif + +static struct platform_driver mxs_spi_driver = { + .probe = mxs_spi_probe, + .remove = __devexit_p(mxs_spi_remove), + .driver = { + .name = "mxs-spi", + .owner = THIS_MODULE, + }, + .suspend = mxs_spi_suspend, + .resume = mxs_spi_resume, +}; + +static int __init mxs_spi_init(void) +{ + return platform_driver_register(&mxs_spi_driver); +} + +static void __exit mxs_spi_exit(void) +{ + platform_driver_unregister(&mxs_spi_driver); +} + +module_init(mxs_spi_init); +module_exit(mxs_spi_exit); +module_param(pio, int, S_IRUGO); +module_param(debug, int, S_IRUGO); +MODULE_AUTHOR("dmitry pervushin "); +MODULE_DESCRIPTION("MXS SPI/SSP"); +MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi_mxs.h b/drivers/spi/spi_mxs.h new file mode 100644 index 000000000000..c9e271e92f8b --- /dev/null +++ b/drivers/spi/spi_mxs.h @@ -0,0 +1,54 @@ +/* + * Freescale MXS SPI master driver + * + * Author: dmitry pervushin + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __SPI_STMP_H +#define __SPI_STMP_H + +#include + +struct mxs_spi { + void __iomem *regs; /* vaddr of the control registers */ + + u32 irq_dma; + u32 irq_err; + u32 dma; + struct mxs_dma_desc *pdesc; + + u32 speed_khz; + u32 saved_timings; + u32 divider; + + struct clk *clk; + struct device *master_dev; + + struct work_struct work; + struct workqueue_struct *workqueue; + spinlock_t lock; + struct list_head queue; + + u32 ver_major; + + struct completion done; +}; + +#endif /* __SPI_STMP_H */ diff --git a/drivers/spi/spi_sam.c b/drivers/spi/spi_sam.c new file mode 100644 index 000000000000..a67a01368010 --- /dev/null +++ b/drivers/spi/spi_sam.c @@ -0,0 +1,1161 @@ +/* + * spi_sam.c - Samsung SOC SPI controller driver. + * By -- Jaswinder Singh + * + * Copyright (C) 2009 Samsung Electronics Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spi_sam.h" + +//#define DEBUGSPI + +#ifdef DEBUGSPI + +#define dbg_printk(x...) printk(x) + +static void dump_regs(struct samspi_bus *sspi) +{ + u32 val; + + val = readl(sspi->regs + SAMSPI_CH_CFG); + printk("CHN-%x\t", val); + val = readl(sspi->regs + SAMSPI_CLK_CFG); + printk("CLK-%x\t", val); + val = readl(sspi->regs + SAMSPI_MODE_CFG); + printk("MOD-%x\t", val); + val = readl(sspi->regs + SAMSPI_SLAVE_SEL); + printk("SLVSEL-%x\t", val); + val = readl(sspi->regs + SAMSPI_SPI_STATUS); + if(val & SPI_STUS_TX_DONE) + printk("TX_done\t"); + if(val & SPI_STUS_TRAILCNT_ZERO) + printk("TrailZ\t"); + if(val & SPI_STUS_RX_OVERRUN_ERR) + printk("RX_Ovrn\t"); + if(val & SPI_STUS_RX_UNDERRUN_ERR) + printk("Rx_Unrn\t"); + if(val & SPI_STUS_TX_OVERRUN_ERR) + printk("Tx_Ovrn\t"); + if(val & SPI_STUS_TX_UNDERRUN_ERR) + printk("Tx_Unrn\t"); + if(val & SPI_STUS_RX_FIFORDY) + printk("Rx_Rdy\t"); + if(val & SPI_STUS_TX_FIFORDY) + printk("Tx_Rdy\t"); + printk("Rx/TxLvl=%d,%d\n", (val>>13)&0x7f, (val>>6)&0x7f); +} + +static void dump_spidevice_info(struct spi_device *spi) +{ + dbg_printk("Modalias = %s\n", spi->modalias); + dbg_printk("Slave-%d on Bus-%d\n", spi->chip_select, spi->master->bus_num); + dbg_printk("max_speed_hz = %d\n", spi->max_speed_hz); + dbg_printk("bits_per_word = %d\n", spi->bits_per_word); + dbg_printk("irq = %d\n", spi->irq); + dbg_printk("Clk Phs = %d\n", spi->mode & SPI_CPHA); + dbg_printk("Clk Pol = %d\n", spi->mode & SPI_CPOL); + dbg_printk("ActiveCS = %s\n", (spi->mode & (1<<2)) ? "high" : "low" ); + dbg_printk("Our Mode = %s\n", (spi->mode & SPI_SLAVE) ? "Slave" : "Master"); +} + +#else + +#define dbg_printk(x...) /**/ +#define dump_regs(sspi) /**/ +#define dump_spidevice_info(spi) /**/ + +#endif + +static void dump_spi_regs(struct samspi_bus *sspi) +{ + printk(KERN_CRIT "Reg Info \n"); + printk(KERN_CRIT "CH_CFG = 0x%8.8x\n", readl(sspi->regs + SAMSPI_CH_CFG)); + printk(KERN_CRIT "CLK_CFG = 0x%8.8x\n", readl(sspi->regs + SAMSPI_CLK_CFG)); + printk(KERN_CRIT "MODE_CFG = 0x%8.8x\n", readl(sspi->regs + SAMSPI_MODE_CFG)); + printk(KERN_CRIT "CS_REG = 0x%8.8x\n", readl(sspi->regs + SAMSPI_SLAVE_SEL)); + printk(KERN_CRIT "SPI_INT_EN = 0x%8.8x\n", readl(sspi->regs + SAMSPI_SPI_INT_EN)); + printk(KERN_CRIT "SPI_STATUS = 0x%8.8x\n", readl(sspi->regs + SAMSPI_SPI_STATUS)); +// printk(KERN_CRIT "SAMSPI_SPI_RX_DATA = 0x%8.8x\n", readl(sspi->regs + SAMSPI_SPI_RX_DATA)); +// printk(KERN_CRIT "SAMSPI_SPI_TX_DATA = 0x%8.8x\n", readl(sspi->regs + SAMSPI_SPI_TX_DATA)); +} + +static struct s3c2410_dma_client samspi_dma_client = { + .name = "samspi-dma", +}; + +static int sspi_getclcks(struct samspi_bus *sspi) +{ + struct clk *cspi, *cp, *cm, *cf; + + cp = NULL; + cm = NULL; + cf = NULL; + cspi = sspi->clk; + + if(cspi == NULL){ + cspi = clk_get(&sspi->pdev->dev, "spi"); + if(IS_ERR(cspi)){ + printk("Unable to get spi!\n"); + return -EBUSY; + } + } + dbg_printk("%s:%d Got clk=spi\n", __func__, __LINE__); + +#if defined(CONFIG_SPICLK_SRC_SCLK48M) || defined(CONFIG_SPICLK_SRC_EPLL) || defined(CONFIG_SPICLK_SRC_SPIEXT) + cp = clk_get(&sspi->pdev->dev, spiclk_src); + if(IS_ERR(cp)){ + printk("Unable to get parent clock(%s)!\n", spiclk_src); + if(sspi->clk == NULL){ + clk_disable(cspi); + clk_put(cspi); + } + return -EBUSY; + } + dbg_printk("%s:%d Got clk=%s\n", __func__, __LINE__, spiclk_src); + +#if defined(CONFIG_SPICLK_SRC_EPLL) || defined(CONFIG_SPICLK_SRC_SPIEXT) + cm = clk_get(&sspi->pdev->dev, spisclk_src); + if(IS_ERR(cm)){ + printk("Unable to get %s\n", spisclk_src); + clk_put(cp); + return -EBUSY; + } + dbg_printk("%s:%d Got clk=%s\n", __func__, __LINE__, spisclk_src); + if(clk_set_parent(cp, cm)){ + printk("failed to set %s as the parent of %s\n", spisclk_src, spiclk_src); + clk_put(cm); + clk_put(cp); + return -EBUSY; + } + dbg_printk("Set %s as the parent of %s\n", spisclk_src, spiclk_src); + +#if defined(CONFIG_SPICLK_EPLL_MOUTEPLL) /* MOUTepll through EPLL */ + cf = clk_get(&sspi->pdev->dev, "fout_epll"); + if(IS_ERR(cf)){ + printk("Unable to get fout_epll\n"); + clk_put(cm); + clk_put(cp); + return -EBUSY; + } + dbg_printk("Got fout_epll\n"); + if(clk_set_parent(cm, cf)){ + printk("failed to set FOUTepll as parent of %s\n", spisclk_src); + clk_put(cf); + clk_put(cm); + clk_put(cp); + return -EBUSY; + } + dbg_printk("Set FOUTepll as parent of %s\n", spisclk_src); + clk_put(cf); +#endif + clk_put(cm); +#endif + + sspi->prnt_clk = cp; +#endif + + sspi->clk = cspi; + return 0; +} + +static void sspi_putclcks(struct samspi_bus *sspi) +{ + if(sspi->prnt_clk != NULL) + clk_put(sspi->prnt_clk); + + clk_put(sspi->clk); +} + +static int sspi_enclcks(struct samspi_bus *sspi) +{ + if(sspi->prnt_clk != NULL) + clk_enable(sspi->prnt_clk); + + return clk_enable(sspi->clk); +} + +static void sspi_disclcks(struct samspi_bus *sspi) +{ + if(sspi->prnt_clk != NULL) + clk_disable(sspi->prnt_clk); + + clk_disable(sspi->clk); +} + +static unsigned long sspi_getrate(struct samspi_bus *sspi) +{ + if(sspi->prnt_clk != NULL) + return clk_get_rate(sspi->prnt_clk); + else + return clk_get_rate(sspi->clk); +} + +static int sspi_setrate(struct samspi_bus *sspi, unsigned long r) +{ + /* We don't take charge of the Src Clock, yet */ + return 0; +} + +static inline void enable_spidma(struct samspi_bus *sspi, struct spi_transfer *xfer) +{ + u32 val; + + val = readl(sspi->regs + SAMSPI_MODE_CFG); + val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); + if(xfer->tx_buf != NULL) + val |= SPI_MODE_TXDMA_ON; + if(xfer->rx_buf != NULL) + val |= SPI_MODE_RXDMA_ON; + writel(val, sspi->regs + SAMSPI_MODE_CFG); +} + +static inline void flush_dma(struct samspi_bus *sspi, struct spi_transfer *xfer) +{ + if(xfer->tx_buf != NULL) + s3c2410_dma_ctrl(sspi->tx_dmach, S3C2410_DMAOP_FLUSH); + if(xfer->rx_buf != NULL) + s3c2410_dma_ctrl(sspi->rx_dmach, S3C2410_DMAOP_FLUSH); +} + +static inline void flush_spi(struct samspi_bus *sspi) +{ + u32 val; + + val = readl(sspi->regs + SAMSPI_CH_CFG); + val |= SPI_CH_SW_RST; + val &= ~SPI_CH_HS_EN; + if((sspi->cur_speed > 30000000UL) && !(sspi->cur_mode & SPI_SLAVE)) /* TODO ??? */ + val |= SPI_CH_HS_EN; + writel(val, sspi->regs + SAMSPI_CH_CFG); + + /* Flush TxFIFO*/ + do{ + val = readl(sspi->regs + SAMSPI_SPI_STATUS); + val = (val>>6) & 0x7f; + }while(val); + + /* Flush RxFIFO*/ + val = readl(sspi->regs + SAMSPI_SPI_STATUS); + val = (val>>13) & 0x7f; + while(val){ + readl(sspi->regs + SAMSPI_SPI_RX_DATA); + val = readl(sspi->regs + SAMSPI_SPI_STATUS); + val = (val>>13) & 0x7f; + } + + val = readl(sspi->regs + SAMSPI_CH_CFG); + val &= ~SPI_CH_SW_RST; + writel(val, sspi->regs + SAMSPI_CH_CFG); +} + +static inline void enable_spichan(struct samspi_bus *sspi, struct spi_transfer *xfer) +{ + u32 val; + + //printk(KERN_CRIT "@@@@@@@@ enable_spichan() \n"); + + val = readl(sspi->regs + SAMSPI_CH_CFG); + val &= ~(SPI_CH_RXCH_ON | SPI_CH_TXCH_ON); + if(xfer->tx_buf != NULL){ + val |= SPI_CH_TXCH_ON; + } + if(xfer->rx_buf != NULL){ + if(!(sspi->cur_mode & SPI_SLAVE)){ + writel((xfer->len & 0xffff) | SPI_PACKET_CNT_EN, + sspi->regs + SAMSPI_PACKET_CNT); /* XXX TODO Bytes or number of SPI-Words? */ + } + val |= SPI_CH_RXCH_ON; + } + writel(val, sspi->regs + SAMSPI_CH_CFG); +} + +static inline void enable_spiintr(struct samspi_bus *sspi, struct spi_transfer *xfer) +{ + u32 val = 0; + + if(xfer->tx_buf != NULL){ + val |= SPI_INT_TX_OVERRUN_EN; + if(!(sspi->cur_mode & SPI_SLAVE)) + val |= SPI_INT_TX_UNDERRUN_EN; + } + if(xfer->rx_buf != NULL){ + val |= (SPI_INT_RX_UNDERRUN_EN | SPI_INT_RX_OVERRUN_EN | SPI_INT_TRAILING_EN); + } + writel(val, sspi->regs + SAMSPI_SPI_INT_EN); +} + +static inline void enable_spienqueue(struct samspi_bus *sspi, struct spi_transfer *xfer) +{ + if(xfer->rx_buf != NULL){ + sspi->rx_done = BUSY; + s3c2410_dma_config(sspi->rx_dmach, sspi->cur_bpw/8, 0); + s3c2410_dma_enqueue(sspi->rx_dmach, (void *)sspi, xfer->rx_dma, xfer->len); + } + if(xfer->tx_buf != NULL){ + sspi->tx_done = BUSY; + s3c2410_dma_config(sspi->tx_dmach, sspi->cur_bpw/8, 0); + s3c2410_dma_enqueue(sspi->tx_dmach, (void *)sspi, xfer->tx_dma, xfer->len); + } +} + +static inline void enable_cs(struct samspi_bus *sspi, struct spi_device *spi) +{ + u32 val; + struct sam_spi_pdata *spd = (struct sam_spi_pdata *)spi->controller_data; + + val = readl(sspi->regs + SAMSPI_SLAVE_SEL); + + if(sspi->cur_mode & SPI_SLAVE){ + val |= SPI_SLAVE_AUTO; /* Auto Mode */ + val |= SPI_SLAVE_SIG_INACT; + }else{ /* Master Mode */ + val &= ~SPI_SLAVE_AUTO; /* Manual Mode */ + val &= ~SPI_SLAVE_SIG_INACT; /* Activate CS */ + if(spi->mode & SPI_CS_HIGH){ // spd->cs_act_high){ + spd->cs_set(spd->cs_pin, CS_HIGH); + spd->cs_level = CS_HIGH; + }else{ + spd->cs_set(spd->cs_pin, CS_LOW); + spd->cs_level = CS_LOW; + } + } + + writel(val, sspi->regs + SAMSPI_SLAVE_SEL); +} + +static inline void disable_cs(struct samspi_bus *sspi, struct spi_device *spi) +{ + u32 val; + struct sam_spi_pdata *spd = (struct sam_spi_pdata *)spi->controller_data; + + if(!(spi->mode & SPI_CS_HIGH) && spd->cs_act_high){ + dbg_printk("%s:%s:%d Slave supports SPI_CS_HIGH, but not requested by Master!\n", __FILE__, __func__, __LINE__); + } + + val = readl(sspi->regs + SAMSPI_SLAVE_SEL); + + if(sspi->cur_mode & SPI_SLAVE){ + val |= SPI_SLAVE_AUTO; /* Auto Mode */ + }else{ /* Master Mode */ + val &= ~SPI_SLAVE_AUTO; /* Manual Mode */ + val |= SPI_SLAVE_SIG_INACT; /* DeActivate CS */ + if(spi->mode & SPI_CS_HIGH){ // spd->cs_act_high){ + spd->cs_set(spd->cs_pin, CS_LOW); + spd->cs_level = CS_LOW; + }else{ + spd->cs_set(spd->cs_pin, CS_HIGH); + spd->cs_level = CS_HIGH; + } + } + + writel(val, sspi->regs + SAMSPI_SLAVE_SEL); +} + +static inline void set_polarity(struct samspi_bus *sspi) +{ + u32 val; + + val = readl(sspi->regs + SAMSPI_CH_CFG); + val &= ~(SPI_CH_SLAVE | SPI_CPOL_L | SPI_CPHA_B); + if(sspi->cur_mode & SPI_SLAVE) + val |= SPI_CH_SLAVE; + if(!(sspi->cur_mode & SPI_CPOL)) + val |= SPI_CPOL_L; + if(sspi->cur_mode & SPI_CPHA) + val |= SPI_CPHA_B; + writel(val, sspi->regs + SAMSPI_CH_CFG); +} + +static inline void set_clock(struct samspi_bus *sspi) +{ + u32 val; + + val = readl(sspi->regs + SAMSPI_CLK_CFG); + val &= ~(SPI_CLKSEL_SRCMSK | SPI_ENCLK_ENABLE | 0xff); + val |= SPI_CLKSEL_SRC; + if(!(sspi->cur_mode & SPI_SLAVE)){ + val |= ((sspi_getrate(sspi) / sspi->cur_speed / 2 - 1) << 0); // PCLK and PSR + val |= SPI_ENCLK_ENABLE; + } + writel(val, sspi->regs + SAMSPI_CLK_CFG); +} + +static inline void set_dmachan(struct samspi_bus *sspi) +{ + u32 val; + + val = readl(sspi->regs + SAMSPI_MODE_CFG); + val &= ~((0x3<<17) | (0x3<<29)); + if(sspi->cur_bpw == 8){ + val |= SPI_MODE_CH_TSZ_BYTE; + val |= SPI_MODE_BUS_TSZ_BYTE; + }else if(sspi->cur_bpw == 16){ + val |= SPI_MODE_CH_TSZ_HALFWORD; + val |= SPI_MODE_BUS_TSZ_HALFWORD; + }else if(sspi->cur_bpw == 32){ + val |= SPI_MODE_CH_TSZ_WORD; + val |= SPI_MODE_BUS_TSZ_WORD; + }else{ + printk("Invalid Bits/Word!\n"); + } + val &= ~(SPI_MODE_4BURST | SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); + writel(val, sspi->regs + SAMSPI_MODE_CFG); +} + +static void config_sspi(struct samspi_bus *sspi) +{ + /* Set Polarity and Phase */ + set_polarity(sspi); + + /* Set Channel & DMA Mode */ + set_dmachan(sspi); +} + +static void samspi_hwinit(struct samspi_bus *sspi, int channel) +{ + unsigned int val; + + writel(SPI_SLAVE_SIG_INACT, sspi->regs + SAMSPI_SLAVE_SEL); + + /* Disable Interrupts */ + writel(0, sspi->regs + SAMSPI_SPI_INT_EN); + +#ifdef CONFIG_CPU_S3C6410 + writel((readl(S3C64XX_SPC_BASE) & ~(3<<28)) | (3<<28), S3C64XX_SPC_BASE); + writel((readl(S3C64XX_SPC_BASE) & ~(3<<18)) | (3<<18), S3C64XX_SPC_BASE); +#elif defined (CONFIG_CPU_S5P6440) + writel((readl(S5P64XX_SPC_BASE) & ~(3<<28)) | (3<<28), S5P64XX_SPC_BASE); + writel((readl(S5P64XX_SPC_BASE) & ~(3<<18)) | (3<<18), S5P64XX_SPC_BASE); +#elif defined (CONFIG_CPU_S5P6440) + /* How to control drive strength, if we must? */ +#endif + + writel(SPI_CLKSEL_SRC, sspi->regs + SAMSPI_CLK_CFG); + writel(0, sspi->regs + SAMSPI_MODE_CFG); + writel(SPI_SLAVE_SIG_INACT, sspi->regs + SAMSPI_SLAVE_SEL); + writel(0, sspi->regs + SAMSPI_PACKET_CNT); + writel(readl(sspi->regs + SAMSPI_PENDING_CLR), sspi->regs + SAMSPI_PENDING_CLR); + writel(SPI_FBCLK_0NS, sspi->regs + SAMSPI_FB_CLK); + + flush_spi(sspi); + + writel(0, sspi->regs + SAMSPI_SWAP_CFG); + writel(SPI_FBCLK_9NS, sspi->regs + SAMSPI_FB_CLK); + + val = readl(sspi->regs + SAMSPI_MODE_CFG); + val &= ~(SPI_MAX_TRAILCNT << SPI_TRAILCNT_OFF); + if(channel == 0) + SET_MODECFG(val, 0); + else + SET_MODECFG(val, 1); + val |= (SPI_TRAILCNT << SPI_TRAILCNT_OFF); + writel(val, sspi->regs + SAMSPI_MODE_CFG); +} + +static irqreturn_t samspi_interrupt(int irq, void *dev_id) +{ + u32 val; + struct samspi_bus *sspi = (struct samspi_bus *)dev_id; + + dump_regs(sspi); + val = readl(sspi->regs + SAMSPI_PENDING_CLR); + dbg_printk("PENDING=%x\n", val); + writel(val, sspi->regs + SAMSPI_PENDING_CLR); + + /* We get interrupted only for bad news */ + if(sspi->tx_done != PASS){ + printk(KERN_CRIT "TX FAILED \n"); + sspi->tx_done = FAIL; + } + if(sspi->rx_done != PASS){ + printk(KERN_CRIT "RX FAILED \n"); + sspi->rx_done = FAIL; + } + sspi->state = STOPPED; + complete(&sspi->xfer_completion); + + return IRQ_HANDLED; +} + +void samspi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id, int size, enum s3c2410_dma_buffresult res) +{ + struct samspi_bus *sspi = (struct samspi_bus *)buf_id; + + if(res == S3C2410_RES_OK){ + sspi->rx_done = PASS; + dbg_printk("DmaRx-%d ", size); + }else{ + sspi->rx_done = FAIL; + dbg_printk("DmaAbrtRx-%d ", size); + } + + if(sspi->tx_done != BUSY && sspi->state != STOPPED) /* If other done and all OK */ + complete(&sspi->xfer_completion); +} + +void samspi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id, int size, enum s3c2410_dma_buffresult res) +{ + struct samspi_bus *sspi = (struct samspi_bus *)buf_id; + + if(res == S3C2410_RES_OK){ + sspi->tx_done = PASS; + dbg_printk("DmaTx-%d ", size); + }else{ + sspi->tx_done = FAIL; + dbg_printk("DmaAbrtTx-%d ", size); + } + + if(sspi->rx_done != BUSY && sspi->state != STOPPED) /* If other done and all OK */ + complete(&sspi->xfer_completion); +} + +static int wait_for_txshiftout(struct samspi_bus *sspi, unsigned long t) +{ + unsigned long timeout; + + timeout = jiffies + t; + while((__raw_readl(sspi->regs + SAMSPI_SPI_STATUS) >> 6) & 0x7f){ + if(time_after(jiffies, timeout)) + return -1; + cpu_relax(); + } + return 0; +} + +static int wait_for_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) +{ + int status; + u32 val; + + val = msecs_to_jiffies(xfer->len / (sspi->min_speed / 8 / 1000)); /* time to xfer data at min. speed */ + if(sspi->cur_mode & SPI_SLAVE) + val += msecs_to_jiffies(5000); /* 5secs to switch on the Master */ + else + val += msecs_to_jiffies(10); /* just some more */ + status = wait_for_completion_interruptible_timeout(&sspi->xfer_completion, val); + + //printk(KERN_CRIT "Return from waitforcompletion = %d \n", status); + + if(status == 0) + status = -ETIMEDOUT; + else if(status == -ERESTARTSYS) + status = -EINTR; + else if((sspi->tx_done != PASS) || (sspi->rx_done != PASS)) /* Some Xfer failed */ + status = -EIO; + else + status = 0; /* All OK */ + + /* When TxLen <= SPI-FifoLen in Slave mode, DMA returns naively */ + if(!status && (sspi->cur_mode & SPI_SLAVE) && (xfer->tx_buf != NULL)){ + val = msecs_to_jiffies(xfer->len / (sspi->min_speed / 8 / 1000)); /* Be lenient */ + val += msecs_to_jiffies(5000); /* 5secs to switch on the Master */ + status = wait_for_txshiftout(sspi, val); + if(status == -1) + status = -ETIMEDOUT; + else + status = 0; + } + + return status; +} + +#define INVALID_DMA_ADDRESS 0xffffffff +/* First, try to map buf onto phys addr as such. + * If xfer->r/tx_buf was not on contiguous memory, + * allocate from our preallocated DMA buffer. + */ +static int samspi_map_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) +{ + struct device *dev = &sspi->pdev->dev; + + sspi->rx_tmp = NULL; + sspi->tx_tmp = NULL; + + xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; + if(xfer->tx_buf != NULL){ + xfer->tx_dma = dma_map_single(dev, + (void *) xfer->tx_buf, xfer->len, + DMA_TO_DEVICE); + if(dma_mapping_error(dev, xfer->tx_dma)) + goto alloc_from_buffer; + } + if(xfer->rx_buf != NULL){ + xfer->rx_dma = dma_map_single(dev, + xfer->rx_buf, xfer->len, + DMA_FROM_DEVICE); + if(dma_mapping_error(dev, xfer->rx_dma)){ + if(xfer->tx_buf) + dma_unmap_single(dev, + xfer->tx_dma, xfer->len, + DMA_TO_DEVICE); + goto alloc_from_buffer; + } + } + return 0; + +alloc_from_buffer: /* If the xfer->[r/t]x_buf was not on contiguous memory */ + + printk(KERN_CRIT "############ Allocating from buffer...\n"); + + if(xfer->len <= SAMSPI_DMABUF_LEN){ + if(xfer->rx_buf != NULL){ + xfer->rx_dma = sspi->rx_dma_phys; + sspi->rx_tmp = (void *)sspi->rx_dma_cpu; + } + if(xfer->tx_buf != NULL){ + xfer->tx_dma = sspi->tx_dma_phys; + sspi->tx_tmp = (void *)sspi->tx_dma_cpu; + } + }else{ + dbg_printk("If you plan to use this Xfer size often, increase SAMSPI_DMABUF_LEN\n"); + if(xfer->rx_buf != NULL){ + sspi->rx_tmp = dma_alloc_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, + &xfer->rx_dma, GFP_KERNEL | GFP_DMA); + if(sspi->rx_tmp == NULL) + return -ENOMEM; + } + if(xfer->tx_buf != NULL){ + sspi->tx_tmp = dma_alloc_coherent(&sspi->pdev->dev, + SAMSPI_DMABUF_LEN, &xfer->tx_dma, GFP_KERNEL | GFP_DMA); + if(sspi->tx_tmp == NULL){ + if(xfer->rx_buf != NULL) + dma_free_coherent(&sspi->pdev->dev, + SAMSPI_DMABUF_LEN, sspi->rx_tmp, xfer->rx_dma); + return -ENOMEM; + } + } + } + + if(xfer->tx_buf != NULL) + memcpy(sspi->tx_tmp, xfer->tx_buf, xfer->len); + + return 0; +} + +static void samspi_unmap_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) +{ + if((sspi->rx_tmp == NULL) && (sspi->tx_tmp == NULL)) /* if map_single'd */ + return; + + if((xfer->rx_buf != NULL) && (sspi->rx_tmp != NULL)) + memcpy(xfer->rx_buf, sspi->rx_tmp, xfer->len); + + if(xfer->len > SAMSPI_DMABUF_LEN){ + if(xfer->rx_buf != NULL) + dma_free_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_tmp, xfer->rx_dma); + if(xfer->tx_buf != NULL) + dma_free_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_tmp, xfer->tx_dma); + }else{ + sspi->rx_tmp = NULL; + sspi->tx_tmp = NULL; + } +} + +static void handle_msg(struct samspi_bus *sspi, struct spi_message *msg) +{ + u8 bpw; + u32 speed, val; + int status = 0; + struct spi_transfer *xfer; + struct spi_device *spi = msg->spi; + + config_sspi(sspi); + + list_for_each_entry (xfer, &msg->transfers, transfer_list) { + + if(!msg->is_dma_mapped && samspi_map_xfer(sspi, xfer)){ + dev_err(&spi->dev, "Xfer: Unable to allocate DMA buffer!\n"); + status = -ENOMEM; + goto out; + } + + INIT_COMPLETION(sspi->xfer_completion); + + /* Only BPW and Speed may change across transfers */ + bpw = xfer->bits_per_word ? : spi->bits_per_word; + speed = xfer->speed_hz ? : spi->max_speed_hz; + + if(sspi->cur_bpw != bpw || sspi->cur_speed != speed){ + sspi->cur_bpw = bpw; + sspi->cur_speed = speed; + config_sspi(sspi); + } + + /* Pending only which is to be done */ + sspi->rx_done = PASS; + sspi->tx_done = PASS; + sspi->state = RUNNING; + + /* Configure Clock */ + set_clock(sspi); + + /* Enable Interrupts */ + enable_spiintr(sspi, xfer); + + if(!(sspi->cur_mode & SPI_SLAVE)) + flush_spi(sspi); + + /* Enqueue data on DMA */ + enable_spienqueue(sspi, xfer); + + /* Enable DMA */ + enable_spidma(sspi, xfer); + + /* Enable TX/RX */ + enable_spichan(sspi, xfer); + + /* Slave Select */ + enable_cs(sspi, spi); + + status = wait_for_xfer(sspi, xfer); + + /************** + * Block Here * + **************/ + + if(status == -ETIMEDOUT){ + dev_err(&spi->dev, "Xfer: Timeout!\n"); + dump_regs(sspi); + sspi->state = STOPPED; + /* DMA Disable*/ + val = readl(sspi->regs + SAMSPI_MODE_CFG); + val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); + writel(val, sspi->regs + SAMSPI_MODE_CFG); + flush_dma(sspi, xfer); + flush_spi(sspi); + if(!msg->is_dma_mapped) + samspi_unmap_xfer(sspi, xfer); + goto out; + } + if(status == -EINTR){ + dev_err(&spi->dev, "Xfer: Interrupted!\n"); + dump_regs(sspi); + sspi->state = STOPPED; + /* DMA Disable*/ + val = readl(sspi->regs + SAMSPI_MODE_CFG); + val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); + writel(val, sspi->regs + SAMSPI_MODE_CFG); + flush_dma(sspi, xfer); + flush_spi(sspi); + if(!msg->is_dma_mapped) + samspi_unmap_xfer(sspi, xfer); + goto out; + } + if(status == -EIO){ /* Some Xfer failed */ + dev_err(&spi->dev, "Xfer: Failed!\n"); + dump_regs(sspi); + sspi->state = STOPPED; + /* DMA Disable*/ + val = readl(sspi->regs + SAMSPI_MODE_CFG); + val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); + writel(val, sspi->regs + SAMSPI_MODE_CFG); + flush_dma(sspi, xfer); + flush_spi(sspi); + if(!msg->is_dma_mapped) + samspi_unmap_xfer(sspi, xfer); + goto out; + } + + if(xfer->delay_usecs){ + udelay(xfer->delay_usecs); + dbg_printk("%s:%s:%d Unverified Control Flow Path!\n", __FILE__, __func__, __LINE__); + } + + if(xfer->cs_change && !(sspi->cur_mode & SPI_SLAVE)){ + disable_cs(sspi, spi); + dbg_printk("%s:%s:%d Unverified Control Flow Path!\n", __FILE__, __func__, __LINE__); + } + + msg->actual_length += xfer->len; + + if(!msg->is_dma_mapped) + samspi_unmap_xfer(sspi, xfer); + + } + +out: + /* Slave Deselect */ + if(!(sspi->cur_mode & SPI_SLAVE)) + disable_cs(sspi, spi); + + /* Disable Interrupts */ + writel(0, sspi->regs + SAMSPI_SPI_INT_EN); + + /* Tx/Rx Disable */ + val = readl(sspi->regs + SAMSPI_CH_CFG); + val &= ~(SPI_CH_RXCH_ON | SPI_CH_TXCH_ON); + writel(val, sspi->regs + SAMSPI_CH_CFG); + + /* DMA Disable*/ + val = readl(sspi->regs + SAMSPI_MODE_CFG); + val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); + writel(val, sspi->regs + SAMSPI_MODE_CFG); + + msg->status = status; + if(msg->complete) + msg->complete(msg->context); +} + +static void samspi_work(struct work_struct *work) +{ + struct samspi_bus *sspi = container_of(work, struct samspi_bus, work); + unsigned long flags; + + spin_lock_irqsave(&sspi->lock, flags); + while (!list_empty(&sspi->queue)) { + struct spi_message *msg; + + msg = container_of(sspi->queue.next, struct spi_message, queue); + list_del_init(&msg->queue); + spin_unlock_irqrestore(&sspi->lock, flags); + + handle_msg(sspi, msg); + + spin_lock_irqsave(&sspi->lock, flags); + } + spin_unlock_irqrestore(&sspi->lock, flags); +} + +static void samspi_cleanup(struct spi_device *spi) +{ + dbg_printk("%s:%s:%d\n", __FILE__, __func__, __LINE__); +} + +static int samspi_transfer(struct spi_device *spi, struct spi_message *msg) +{ + struct spi_master *master = spi->master; + struct samspi_bus *sspi = spi_master_get_devdata(master); + unsigned long flags; + + spin_lock_irqsave(&sspi->lock, flags); + msg->actual_length = 0; + list_add_tail(&msg->queue, &sspi->queue); + queue_work(sspi->workqueue, &sspi->work); + spin_unlock_irqrestore(&sspi->lock, flags); + + return 0; +} + +/* the spi->mode bits understood by this driver: */ +#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_SLAVE | (spd->cs_act_high ? SPI_CS_HIGH : 0) ) +/* + * Here we only check the validity of requested configuration and + * save the configuration in a local data-structure. + * The controller is actually configured only just before + * we get a message to transfer _and_ if no other message is pending(already configured). + */ +static int samspi_setup(struct spi_device *spi) +{ + unsigned long flags; + unsigned int psr; + struct samspi_bus *sspi = spi_master_get_devdata(spi->master); + struct sam_spi_pdata *spd = (struct sam_spi_pdata *)spi->controller_data; + + spin_lock_irqsave(&sspi->lock, flags); + if(!list_empty(&sspi->queue)){ /* Any pending message? */ + spin_unlock_irqrestore(&sspi->lock, flags); + dev_dbg(&spi->dev, "setup: attempt while messages in queue!\n"); + return -EBUSY; + } + spin_unlock_irqrestore(&sspi->lock, flags); + + if (spi->chip_select > spi->master->num_chipselect) { + dev_dbg(&spi->dev, "setup: invalid chipselect %u (%u defined)\n", + spi->chip_select, spi->master->num_chipselect); + return -EINVAL; + } + + spi->bits_per_word = spi->bits_per_word ? : 8; + + if((spi->bits_per_word != 8) && + (spi->bits_per_word != 16) && + (spi->bits_per_word != 32)){ + dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n", spi->bits_per_word); + return -EINVAL; + } + + spi->max_speed_hz = spi->max_speed_hz ? : sspi->max_speed; + + /* Round-off max_speed_hz */ + psr = sspi_getrate(sspi) / spi->max_speed_hz / 2 - 1; + psr &= 0xff; + if(spi->max_speed_hz < sspi_getrate(sspi) / 2 / (psr + 1)) + psr = (psr+1) & 0xff; + + spi->max_speed_hz = sspi_getrate(sspi) / 2 / (psr + 1); + + if (spi->max_speed_hz > sspi->max_speed + || spi->max_speed_hz < sspi->min_speed){ + dev_err(&spi->dev, "setup: req speed(%u) out of range[%u-%u]\n", + spi->max_speed_hz, sspi->min_speed, sspi->max_speed); + return -EINVAL; + } + + if (spi->mode & ~MODEBITS) { + dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", spi->mode & ~MODEBITS); + return -EINVAL; + } + + if(!(spi->mode & SPI_SLAVE) && (spd->cs_level == CS_FLOAT)){ + spd->cs_config(spd->cs_pin, spd->cs_mode, (spi->mode & SPI_CS_HIGH)/*spd->cs_act_high*/ ? CS_LOW : CS_HIGH); + disable_cs(sspi, spi); + } + + if((sspi->cur_bpw == spi->bits_per_word) && + (sspi->cur_speed == spi->max_speed_hz) && + (sspi->cur_mode == spi->mode)) /* If no change in configuration, do nothing */ + return 0; + + sspi->cur_bpw = spi->bits_per_word; + sspi->cur_speed = spi->max_speed_hz; + sspi->cur_mode = spi->mode; + + SAM_SETGPIOPULL(sspi); + return 0; +} + +static int __init samspi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct samspi_bus *sspi; + int ret = -ENODEV; + + dbg_printk("%s:%s:%d ID=%d\n", __FILE__, __func__, __LINE__, pdev->id); + master = spi_alloc_master(&pdev->dev, sizeof(struct samspi_bus)); /* Allocate contiguous SPI controller */ + if (master == NULL) + return ret; + sspi = spi_master_get_devdata(master); + sspi->pdev = pdev; + sspi->spi_mstinfo = (struct sam_spi_mstr_info *)pdev->dev.platform_data; + sspi->master = master; + platform_set_drvdata(pdev, master); + + INIT_WORK(&sspi->work, samspi_work); + spin_lock_init(&sspi->lock); + INIT_LIST_HEAD(&sspi->queue); + init_completion(&sspi->xfer_completion); + + ret = sspi_getclcks(sspi); + if(ret){ + dev_err(&pdev->dev, "cannot acquire clock \n"); + ret = -EBUSY; + goto lb1; + } + ret = sspi_enclcks(sspi); + if(ret){ + dev_err(&pdev->dev, "cannot enable clock \n"); + ret = -EBUSY; + goto lb2; + } + + sspi->max_speed = sspi_getrate(sspi) / 2 / (0x0 + 1); + sspi->min_speed = sspi_getrate(sspi) / 2 / (0xff + 1); + + sspi->cur_bpw = 8; + sspi->cur_mode = SPI_SLAVE; /* Start in Slave mode */ + sspi->cur_speed = sspi->min_speed; + + /* Get and Map Resources */ + sspi->iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (sspi->iores == NULL) { + dev_err(&pdev->dev, "cannot find IO resource\n"); + ret = -ENOENT; + goto lb3; + } + + sspi->ioarea = request_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1, pdev->name); + if (sspi->ioarea == NULL) { + dev_err(&pdev->dev, "cannot request IO\n"); + ret = -ENXIO; + goto lb4; + } + + sspi->regs = ioremap(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); + if (sspi->regs == NULL) { + dev_err(&pdev->dev, "cannot map IO\n"); + ret = -ENXIO; + goto lb5; + } + + sspi->tx_dma_cpu = dma_alloc_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, &sspi->tx_dma_phys, GFP_KERNEL | GFP_DMA); + if(sspi->tx_dma_cpu == NULL){ + dev_err(&pdev->dev, "Unable to allocate TX DMA buffers\n"); + ret = -ENOMEM; + goto lb6; + } + + sspi->rx_dma_cpu = dma_alloc_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, &sspi->rx_dma_phys, GFP_KERNEL | GFP_DMA); + if(sspi->rx_dma_cpu == NULL){ + dev_err(&pdev->dev, "Unable to allocate RX DMA buffers\n"); + ret = -ENOMEM; + goto lb7; + } + + sspi->irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if(sspi->irqres == NULL){ + dev_err(&pdev->dev, "cannot find IRQ\n"); + ret = -ENOENT; + goto lb8; + } + + ret = request_irq(sspi->irqres->start, samspi_interrupt, IRQF_DISABLED, + pdev->name, sspi); + if(ret){ + dev_err(&pdev->dev, "cannot acquire IRQ\n"); + ret = -EBUSY; + goto lb9; + } + + sspi->workqueue = create_singlethread_workqueue(master->dev.parent->bus_id); + if(!sspi->workqueue){ + dev_err(&pdev->dev, "cannot create workqueue\n"); + ret = -EBUSY; + goto lb10; + } + + master->bus_num = pdev->id; + master->setup = samspi_setup; + master->transfer = samspi_transfer; + master->cleanup = samspi_cleanup; + master->num_chipselect = sspi->spi_mstinfo->num_slaves; + + if(spi_register_master(master)){ + dev_err(&pdev->dev, "cannot register SPI master\n"); + ret = -EBUSY; + goto lb11; + } + + /* Configure GPIOs */ + if(pdev->id == 0) + SETUP_SPI(sspi, 0); + else if(pdev->id == 1) + SETUP_SPI(sspi, 1); + SAM_SETGPIOPULL(sspi); + + if(s3c2410_dma_request(sspi->rx_dmach, &samspi_dma_client, NULL)){ + dev_err(&pdev->dev, "cannot get RxDMA\n"); + ret = -EBUSY; + goto lb12; + } + s3c2410_dma_set_buffdone_fn(sspi->rx_dmach, samspi_dma_rxcb); + s3c2410_dma_devconfig(sspi->rx_dmach, S3C2410_DMASRC_HW, 0, sspi->sfr_phyaddr + SAMSPI_SPI_RX_DATA); + s3c2410_dma_config(sspi->rx_dmach, sspi->cur_bpw/8, 0); + s3c2410_dma_setflags(sspi->rx_dmach, S3C2410_DMAF_AUTOSTART); + + if(s3c2410_dma_request(sspi->tx_dmach, &samspi_dma_client, NULL)){ + dev_err(&pdev->dev, "cannot get TxDMA\n"); + ret = -EBUSY; + goto lb13; + } + s3c2410_dma_set_buffdone_fn(sspi->tx_dmach, samspi_dma_txcb); + s3c2410_dma_devconfig(sspi->tx_dmach, S3C2410_DMASRC_MEM, 0, sspi->sfr_phyaddr + SAMSPI_SPI_TX_DATA); + s3c2410_dma_config(sspi->tx_dmach, sspi->cur_bpw/8, 0); + s3c2410_dma_setflags(sspi->tx_dmach, S3C2410_DMAF_AUTOSTART); + + /* Setup Deufult Mode */ + samspi_hwinit(sspi, pdev->id); + + printk("Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", pdev->id, master->num_chipselect); + printk("\tMax,Min-Speed [%d, %d]Hz\n", sspi->max_speed, sspi->min_speed); + printk("\tIrq=%d\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", + sspi->irqres->start, + sspi->iores->end, sspi->iores->start, + sspi->rx_dmach, sspi->tx_dmach); + + return 0; + +lb13: + s3c2410_dma_free(sspi->rx_dmach, &samspi_dma_client); +lb12: + spi_unregister_master(master); +lb11: + destroy_workqueue(sspi->workqueue); +lb10: + free_irq(sspi->irqres->start, sspi); +lb9: +lb8: + dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_dma_cpu, sspi->rx_dma_phys); +lb7: + dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_dma_cpu, sspi->tx_dma_phys); +lb6: + iounmap((void *) sspi->regs); +lb5: + release_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); +lb4: +lb3: + sspi_disclcks(sspi); +lb2: + sspi_putclcks(sspi); +lb1: + platform_set_drvdata(pdev, NULL); + spi_master_put(master); + + return ret; +} + +static int __exit samspi_remove(struct platform_device *pdev) +{ + struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); + struct samspi_bus *sspi = spi_master_get_devdata(master); + + s3c2410_dma_free(sspi->tx_dmach, &samspi_dma_client); + s3c2410_dma_free(sspi->rx_dmach, &samspi_dma_client); + spi_unregister_master(master); + destroy_workqueue(sspi->workqueue); + free_irq(sspi->irqres->start, sspi); + dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_dma_cpu, sspi->rx_dma_phys); + dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_dma_cpu, sspi->tx_dma_phys); + iounmap((void *) sspi->regs); + release_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); + sspi_disclcks(sspi); + sspi_putclcks(sspi); + platform_set_drvdata(pdev, NULL); + spi_master_put(master); + + return 0; +} + +static struct platform_driver sam_spi_driver = { + .driver = { + .name = "sam-spi", + .owner = THIS_MODULE, + .bus = &platform_bus_type, + }, +// .remove = sam_spi_remove, +// .shutdown = sam_spi_shutdown, +// .suspend = sam_spi_suspend, +// .resume = sam_spi_resume, +}; + +static int __init sam_spi_init(void) +{ + dbg_printk("%s:%s:%d\n", __FILE__, __func__, __LINE__); + return platform_driver_probe(&sam_spi_driver, samspi_probe); +} +//module_init(sam_spi_init); +subsys_initcall(sam_spi_init); + +static void __exit sam_spi_exit(void) +{ + platform_driver_unregister(&sam_spi_driver); +} +module_exit(sam_spi_exit); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Jaswinder Singh Brar "); +MODULE_DESCRIPTION("Samsung SOC SPI Controller"); diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 984a75440710..9e2e49bcf1cc 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -147,5 +147,7 @@ source "drivers/staging/mrst-touchscreen/Kconfig" source "drivers/staging/msm/Kconfig" +source "drivers/staging/android/Kconfig" + endif # !STAGING_EXCLUDE_BUILD endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 9fa25133874a..afa125135ba4 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_ADIS16255) += adis16255/ obj-$(CONFIG_FB_XGI) += xgifb/ obj-$(CONFIG_TOUCHSCREEN_MRSTOUCH) += mrst-touchscreen/ obj-$(CONFIG_MSM_STAGING) += msm/ +obj-$(CONFIG_ANDROID) += android/ diff --git a/drivers/staging/android/Kconfig b/drivers/staging/android/Kconfig new file mode 100644 index 000000000000..2574d37c9892 --- /dev/null +++ b/drivers/staging/android/Kconfig @@ -0,0 +1,27 @@ +menu "Android" + +config ANDROID + bool "Android Drivers" + default n + ---help--- + Enable support for various drivers needed on the Android platform + +if ANDROID + +config ANDROID_BINDER_IPC + bool "Android Binder IPC Driver" + default y + +config ANDROID_LOGGER + tristate "Android log driver" + default y + +config ANDROID_LOW_MEMORY_KILLER + bool "Android Low Memory Killer" + default y + ---help--- + Register processes to be killed when memory is low + +endif # if ANDROID + +endmenu diff --git a/drivers/staging/android/Makefile b/drivers/staging/android/Makefile new file mode 100644 index 000000000000..e4e300c2c092 --- /dev/null +++ b/drivers/staging/android/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ANDROID_BINDER_IPC) += binder.o +obj-$(CONFIG_ANDROID_LOGGER) += logger.o +obj-$(CONFIG_ANDROID_LOW_MEMORY_KILLER) += lowmemorykiller.o diff --git a/drivers/staging/android/TODO b/drivers/staging/android/TODO new file mode 100644 index 000000000000..e59c5be4be2b --- /dev/null +++ b/drivers/staging/android/TODO @@ -0,0 +1,10 @@ +TODO: + - checkpatch.pl cleanups + - sparse fixes + - rename files to be not so "generic" + - make sure things build as modules properly + - add proper arch dependancies as needed + - audit userspace interfaces to make sure they are sane + +Please send patches to Greg Kroah-Hartman and Cc: +Brian Swetland diff --git a/drivers/staging/android/binder.c b/drivers/staging/android/binder.c new file mode 100644 index 000000000000..e13b4c483407 --- /dev/null +++ b/drivers/staging/android/binder.c @@ -0,0 +1,3600 @@ +/* binder.c + * + * Android IPC Subsystem + * + * Copyright (C) 2007-2008 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "binder.h" + +static DEFINE_MUTEX(binder_lock); +static DEFINE_MUTEX(binder_deferred_lock); + +static HLIST_HEAD(binder_procs); +static HLIST_HEAD(binder_deferred_list); +static HLIST_HEAD(binder_dead_nodes); + +static struct dentry *binder_debugfs_dir_entry_root; +static struct dentry *binder_debugfs_dir_entry_proc; +static struct binder_node *binder_context_mgr_node; +static uid_t binder_context_mgr_uid = -1; +static int binder_last_id; +static struct workqueue_struct *binder_deferred_workqueue; + +#define BINDER_DEBUG_ENTRY(name) \ +static int binder_##name##_open(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, binder_##name##_show, inode->i_private); \ +} \ +\ +static const struct file_operations binder_##name##_fops = { \ + .owner = THIS_MODULE, \ + .open = binder_##name##_open, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = single_release, \ +} + +static int binder_proc_show(struct seq_file *m, void *unused); +BINDER_DEBUG_ENTRY(proc); + +/* This is only defined in include/asm-arm/sizes.h */ +#ifndef SZ_1K +#define SZ_1K 0x400 +#endif + +#ifndef SZ_4M +#define SZ_4M 0x400000 +#endif + +#define FORBIDDEN_MMAP_FLAGS (VM_WRITE) + +#define BINDER_SMALL_BUF_SIZE (PAGE_SIZE * 64) + +enum { + BINDER_DEBUG_USER_ERROR = 1U << 0, + BINDER_DEBUG_FAILED_TRANSACTION = 1U << 1, + BINDER_DEBUG_DEAD_TRANSACTION = 1U << 2, + BINDER_DEBUG_OPEN_CLOSE = 1U << 3, + BINDER_DEBUG_DEAD_BINDER = 1U << 4, + BINDER_DEBUG_DEATH_NOTIFICATION = 1U << 5, + BINDER_DEBUG_READ_WRITE = 1U << 6, + BINDER_DEBUG_USER_REFS = 1U << 7, + BINDER_DEBUG_THREADS = 1U << 8, + BINDER_DEBUG_TRANSACTION = 1U << 9, + BINDER_DEBUG_TRANSACTION_COMPLETE = 1U << 10, + BINDER_DEBUG_FREE_BUFFER = 1U << 11, + BINDER_DEBUG_INTERNAL_REFS = 1U << 12, + BINDER_DEBUG_BUFFER_ALLOC = 1U << 13, + BINDER_DEBUG_PRIORITY_CAP = 1U << 14, + BINDER_DEBUG_BUFFER_ALLOC_ASYNC = 1U << 15, +}; +static uint32_t binder_debug_mask = BINDER_DEBUG_USER_ERROR | + BINDER_DEBUG_FAILED_TRANSACTION | BINDER_DEBUG_DEAD_TRANSACTION; +module_param_named(debug_mask, binder_debug_mask, uint, S_IWUSR | S_IRUGO); + +static int binder_debug_no_lock; +module_param_named(proc_no_lock, binder_debug_no_lock, bool, S_IWUSR | S_IRUGO); + +static DECLARE_WAIT_QUEUE_HEAD(binder_user_error_wait); +static int binder_stop_on_user_error; + +static int binder_set_stop_on_user_error(const char *val, + struct kernel_param *kp) +{ + int ret; + ret = param_set_int(val, kp); + if (binder_stop_on_user_error < 2) + wake_up(&binder_user_error_wait); + return ret; +} +module_param_call(stop_on_user_error, binder_set_stop_on_user_error, + param_get_int, &binder_stop_on_user_error, S_IWUSR | S_IRUGO); + +#define binder_debug(mask, x...) \ + do { \ + if (binder_debug_mask & mask) \ + printk(KERN_INFO x); \ + } while (0) + +#define binder_user_error(x...) \ + do { \ + if (binder_debug_mask & BINDER_DEBUG_USER_ERROR) \ + printk(KERN_INFO x); \ + if (binder_stop_on_user_error) \ + binder_stop_on_user_error = 2; \ + } while (0) + +enum binder_stat_types { + BINDER_STAT_PROC, + BINDER_STAT_THREAD, + BINDER_STAT_NODE, + BINDER_STAT_REF, + BINDER_STAT_DEATH, + BINDER_STAT_TRANSACTION, + BINDER_STAT_TRANSACTION_COMPLETE, + BINDER_STAT_COUNT +}; + +struct binder_stats { + int br[_IOC_NR(BR_FAILED_REPLY) + 1]; + int bc[_IOC_NR(BC_DEAD_BINDER_DONE) + 1]; + int obj_created[BINDER_STAT_COUNT]; + int obj_deleted[BINDER_STAT_COUNT]; +}; + +static struct binder_stats binder_stats; + +static inline void binder_stats_deleted(enum binder_stat_types type) +{ + binder_stats.obj_deleted[type]++; +} + +static inline void binder_stats_created(enum binder_stat_types type) +{ + binder_stats.obj_created[type]++; +} + +struct binder_transaction_log_entry { + int debug_id; + int call_type; + int from_proc; + int from_thread; + int target_handle; + int to_proc; + int to_thread; + int to_node; + int data_size; + int offsets_size; +}; +struct binder_transaction_log { + int next; + int full; + struct binder_transaction_log_entry entry[32]; +}; +static struct binder_transaction_log binder_transaction_log; +static struct binder_transaction_log binder_transaction_log_failed; + +static struct binder_transaction_log_entry *binder_transaction_log_add( + struct binder_transaction_log *log) +{ + struct binder_transaction_log_entry *e; + e = &log->entry[log->next]; + memset(e, 0, sizeof(*e)); + log->next++; + if (log->next == ARRAY_SIZE(log->entry)) { + log->next = 0; + log->full = 1; + } + return e; +} + +struct binder_work { + struct list_head entry; + enum { + BINDER_WORK_TRANSACTION = 1, + BINDER_WORK_TRANSACTION_COMPLETE, + BINDER_WORK_NODE, + BINDER_WORK_DEAD_BINDER, + BINDER_WORK_DEAD_BINDER_AND_CLEAR, + BINDER_WORK_CLEAR_DEATH_NOTIFICATION, + } type; +}; + +struct binder_node { + int debug_id; + struct binder_work work; + union { + struct rb_node rb_node; + struct hlist_node dead_node; + }; + struct binder_proc *proc; + struct hlist_head refs; + int internal_strong_refs; + int local_weak_refs; + int local_strong_refs; + void __user *ptr; + void __user *cookie; + unsigned has_strong_ref:1; + unsigned pending_strong_ref:1; + unsigned has_weak_ref:1; + unsigned pending_weak_ref:1; + unsigned has_async_transaction:1; + unsigned accept_fds:1; + unsigned min_priority:8; + struct list_head async_todo; +}; + +struct binder_ref_death { + struct binder_work work; + void __user *cookie; +}; + +struct binder_ref { + /* Lookups needed: */ + /* node + proc => ref (transaction) */ + /* desc + proc => ref (transaction, inc/dec ref) */ + /* node => refs + procs (proc exit) */ + int debug_id; + struct rb_node rb_node_desc; + struct rb_node rb_node_node; + struct hlist_node node_entry; + struct binder_proc *proc; + struct binder_node *node; + uint32_t desc; + int strong; + int weak; + struct binder_ref_death *death; +}; + +struct binder_buffer { + struct list_head entry; /* free and allocated entries by addesss */ + struct rb_node rb_node; /* free entry by size or allocated entry */ + /* by address */ + unsigned free:1; + unsigned allow_user_free:1; + unsigned async_transaction:1; + unsigned debug_id:29; + + struct binder_transaction *transaction; + + struct binder_node *target_node; + size_t data_size; + size_t offsets_size; + uint8_t data[0]; +}; + +enum binder_deferred_state { + BINDER_DEFERRED_PUT_FILES = 0x01, + BINDER_DEFERRED_FLUSH = 0x02, + BINDER_DEFERRED_RELEASE = 0x04, +}; + +struct binder_proc { + struct hlist_node proc_node; + struct rb_root threads; + struct rb_root nodes; + struct rb_root refs_by_desc; + struct rb_root refs_by_node; + int pid; + struct vm_area_struct *vma; + struct task_struct *tsk; + struct files_struct *files; + struct hlist_node deferred_work_node; + int deferred_work; + void *buffer; + ptrdiff_t user_buffer_offset; + + struct list_head buffers; + struct rb_root free_buffers; + struct rb_root allocated_buffers; + size_t free_async_space; + + struct page **pages; + size_t buffer_size; + uint32_t buffer_free; + struct list_head todo; + wait_queue_head_t wait; + struct binder_stats stats; + struct list_head delivered_death; + int max_threads; + int requested_threads; + int requested_threads_started; + int ready_threads; + long default_priority; + struct dentry *debugfs_entry; +}; + +enum { + BINDER_LOOPER_STATE_REGISTERED = 0x01, + BINDER_LOOPER_STATE_ENTERED = 0x02, + BINDER_LOOPER_STATE_EXITED = 0x04, + BINDER_LOOPER_STATE_INVALID = 0x08, + BINDER_LOOPER_STATE_WAITING = 0x10, + BINDER_LOOPER_STATE_NEED_RETURN = 0x20 +}; + +struct binder_thread { + struct binder_proc *proc; + struct rb_node rb_node; + int pid; + int looper; + struct binder_transaction *transaction_stack; + struct list_head todo; + uint32_t return_error; /* Write failed, return error code in read buf */ + uint32_t return_error2; /* Write failed, return error code in read */ + /* buffer. Used when sending a reply to a dead process that */ + /* we are also waiting on */ + wait_queue_head_t wait; + struct binder_stats stats; +}; + +struct binder_transaction { + int debug_id; + struct binder_work work; + struct binder_thread *from; + struct binder_transaction *from_parent; + struct binder_proc *to_proc; + struct binder_thread *to_thread; + struct binder_transaction *to_parent; + unsigned need_reply:1; + /* unsigned is_dead:1; */ /* not used at the moment */ + + struct binder_buffer *buffer; + unsigned int code; + unsigned int flags; + long priority; + long saved_priority; + uid_t sender_euid; +}; + +static void +binder_defer_work(struct binder_proc *proc, enum binder_deferred_state defer); + +/* + * copied from get_unused_fd_flags + */ +int task_get_unused_fd_flags(struct binder_proc *proc, int flags) +{ + struct files_struct *files = proc->files; + int fd, error; + struct fdtable *fdt; + unsigned long rlim_cur; + unsigned long irqs; + + if (files == NULL) + return -ESRCH; + + error = -EMFILE; + spin_lock(&files->file_lock); + +repeat: + fdt = files_fdtable(files); + fd = find_next_zero_bit(fdt->open_fds->fds_bits, fdt->max_fds, + files->next_fd); + + /* + * N.B. For clone tasks sharing a files structure, this test + * will limit the total number of files that can be opened. + */ + rlim_cur = 0; + if (lock_task_sighand(proc->tsk, &irqs)) { + rlim_cur = proc->tsk->signal->rlim[RLIMIT_NOFILE].rlim_cur; + unlock_task_sighand(proc->tsk, &irqs); + } + if (fd >= rlim_cur) + goto out; + + /* Do we need to expand the fd array or fd set? */ + error = expand_files(files, fd); + if (error < 0) + goto out; + + if (error) { + /* + * If we needed to expand the fs array we + * might have blocked - try again. + */ + error = -EMFILE; + goto repeat; + } + + FD_SET(fd, fdt->open_fds); + if (flags & O_CLOEXEC) + FD_SET(fd, fdt->close_on_exec); + else + FD_CLR(fd, fdt->close_on_exec); + files->next_fd = fd + 1; +#if 1 + /* Sanity check */ + if (fdt->fd[fd] != NULL) { + printk(KERN_WARNING "get_unused_fd: slot %d not NULL!\n", fd); + fdt->fd[fd] = NULL; + } +#endif + error = fd; + +out: + spin_unlock(&files->file_lock); + return error; +} + +/* + * copied from fd_install + */ +static void task_fd_install( + struct binder_proc *proc, unsigned int fd, struct file *file) +{ + struct files_struct *files = proc->files; + struct fdtable *fdt; + + if (files == NULL) + return; + + spin_lock(&files->file_lock); + fdt = files_fdtable(files); + BUG_ON(fdt->fd[fd] != NULL); + rcu_assign_pointer(fdt->fd[fd], file); + spin_unlock(&files->file_lock); +} + +/* + * copied from __put_unused_fd in open.c + */ +static void __put_unused_fd(struct files_struct *files, unsigned int fd) +{ + struct fdtable *fdt = files_fdtable(files); + __FD_CLR(fd, fdt->open_fds); + if (fd < files->next_fd) + files->next_fd = fd; +} + +/* + * copied from sys_close + */ +static long task_close_fd(struct binder_proc *proc, unsigned int fd) +{ + struct file *filp; + struct files_struct *files = proc->files; + struct fdtable *fdt; + int retval; + + if (files == NULL) + return -ESRCH; + + spin_lock(&files->file_lock); + fdt = files_fdtable(files); + if (fd >= fdt->max_fds) + goto out_unlock; + filp = fdt->fd[fd]; + if (!filp) + goto out_unlock; + rcu_assign_pointer(fdt->fd[fd], NULL); + FD_CLR(fd, fdt->close_on_exec); + __put_unused_fd(files, fd); + spin_unlock(&files->file_lock); + retval = filp_close(filp, files); + + /* can't restart close syscall because file table entry was cleared */ + if (unlikely(retval == -ERESTARTSYS || + retval == -ERESTARTNOINTR || + retval == -ERESTARTNOHAND || + retval == -ERESTART_RESTARTBLOCK)) + retval = -EINTR; + + return retval; + +out_unlock: + spin_unlock(&files->file_lock); + return -EBADF; +} + +static void binder_set_nice(long nice) +{ + long min_nice; + if (can_nice(current, nice)) { + set_user_nice(current, nice); + return; + } + min_nice = 20 - current->signal->rlim[RLIMIT_NICE].rlim_cur; + binder_debug(BINDER_DEBUG_PRIORITY_CAP, + "binder: %d: nice value %ld not allowed use " + "%ld instead\n", current->pid, nice, min_nice); + set_user_nice(current, min_nice); + if (min_nice < 20) + return; + binder_user_error("binder: %d RLIMIT_NICE not set\n", current->pid); +} + +static size_t binder_buffer_size(struct binder_proc *proc, + struct binder_buffer *buffer) +{ + if (list_is_last(&buffer->entry, &proc->buffers)) + return proc->buffer + proc->buffer_size - (void *)buffer->data; + else + return (size_t)list_entry(buffer->entry.next, + struct binder_buffer, entry) - (size_t)buffer->data; +} + +static void binder_insert_free_buffer(struct binder_proc *proc, + struct binder_buffer *new_buffer) +{ + struct rb_node **p = &proc->free_buffers.rb_node; + struct rb_node *parent = NULL; + struct binder_buffer *buffer; + size_t buffer_size; + size_t new_buffer_size; + + BUG_ON(!new_buffer->free); + + new_buffer_size = binder_buffer_size(proc, new_buffer); + + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: add free buffer, size %zd, " + "at %p\n", proc->pid, new_buffer_size, new_buffer); + + while (*p) { + parent = *p; + buffer = rb_entry(parent, struct binder_buffer, rb_node); + BUG_ON(!buffer->free); + + buffer_size = binder_buffer_size(proc, buffer); + + if (new_buffer_size < buffer_size) + p = &parent->rb_left; + else + p = &parent->rb_right; + } + rb_link_node(&new_buffer->rb_node, parent, p); + rb_insert_color(&new_buffer->rb_node, &proc->free_buffers); +} + +static void binder_insert_allocated_buffer(struct binder_proc *proc, + struct binder_buffer *new_buffer) +{ + struct rb_node **p = &proc->allocated_buffers.rb_node; + struct rb_node *parent = NULL; + struct binder_buffer *buffer; + + BUG_ON(new_buffer->free); + + while (*p) { + parent = *p; + buffer = rb_entry(parent, struct binder_buffer, rb_node); + BUG_ON(buffer->free); + + if (new_buffer < buffer) + p = &parent->rb_left; + else if (new_buffer > buffer) + p = &parent->rb_right; + else + BUG(); + } + rb_link_node(&new_buffer->rb_node, parent, p); + rb_insert_color(&new_buffer->rb_node, &proc->allocated_buffers); +} + +static struct binder_buffer *binder_buffer_lookup(struct binder_proc *proc, + void __user *user_ptr) +{ + struct rb_node *n = proc->allocated_buffers.rb_node; + struct binder_buffer *buffer; + struct binder_buffer *kern_ptr; + + kern_ptr = user_ptr - proc->user_buffer_offset + - offsetof(struct binder_buffer, data); + + while (n) { + buffer = rb_entry(n, struct binder_buffer, rb_node); + BUG_ON(buffer->free); + + if (kern_ptr < buffer) + n = n->rb_left; + else if (kern_ptr > buffer) + n = n->rb_right; + else + return buffer; + } + return NULL; +} + +static int binder_update_page_range(struct binder_proc *proc, int allocate, + void *start, void *end, + struct vm_area_struct *vma) +{ + void *page_addr; + unsigned long user_page_addr; + struct vm_struct tmp_area; + struct page **page; + struct mm_struct *mm; + + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: %s pages %p-%p\n", proc->pid, + allocate ? "allocate" : "free", start, end); + + if (end <= start) + return 0; + + if (vma) + mm = NULL; + else + mm = get_task_mm(proc->tsk); + + if (mm) { + down_write(&mm->mmap_sem); + vma = proc->vma; + } + + if (allocate == 0) + goto free_range; + + if (vma == NULL) { + printk(KERN_ERR "binder: %d: binder_alloc_buf failed to " + "map pages in userspace, no vma\n", proc->pid); + goto err_no_vma; + } + + for (page_addr = start; page_addr < end; page_addr += PAGE_SIZE) { + int ret; + struct page **page_array_ptr; + page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE]; + + BUG_ON(*page); + *page = alloc_page(GFP_KERNEL | __GFP_ZERO); + if (*page == NULL) { + printk(KERN_ERR "binder: %d: binder_alloc_buf failed " + "for page at %p\n", proc->pid, page_addr); + goto err_alloc_page_failed; + } + tmp_area.addr = page_addr; + tmp_area.size = PAGE_SIZE + PAGE_SIZE /* guard page? */; + page_array_ptr = page; + ret = map_vm_area(&tmp_area, PAGE_KERNEL, &page_array_ptr); + if (ret) { + printk(KERN_ERR "binder: %d: binder_alloc_buf failed " + "to map page at %p in kernel\n", + proc->pid, page_addr); + goto err_map_kernel_failed; + } + user_page_addr = + (uintptr_t)page_addr + proc->user_buffer_offset; + ret = vm_insert_page(vma, user_page_addr, page[0]); + if (ret) { + printk(KERN_ERR "binder: %d: binder_alloc_buf failed " + "to map page at %lx in userspace\n", + proc->pid, user_page_addr); + goto err_vm_insert_page_failed; + } + /* vm_insert_page does not seem to increment the refcount */ + } + if (mm) { + up_write(&mm->mmap_sem); + mmput(mm); + } + return 0; + +free_range: + for (page_addr = end - PAGE_SIZE; page_addr >= start; + page_addr -= PAGE_SIZE) { + page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE]; + if (vma) + zap_page_range(vma, (uintptr_t)page_addr + + proc->user_buffer_offset, PAGE_SIZE, NULL); +err_vm_insert_page_failed: + unmap_kernel_range((unsigned long)page_addr, PAGE_SIZE); +err_map_kernel_failed: + __free_page(*page); + *page = NULL; +err_alloc_page_failed: + ; + } +err_no_vma: + if (mm) { + up_write(&mm->mmap_sem); + mmput(mm); + } + return -ENOMEM; +} + +static struct binder_buffer *binder_alloc_buf(struct binder_proc *proc, + size_t data_size, + size_t offsets_size, int is_async) +{ + struct rb_node *n = proc->free_buffers.rb_node; + struct binder_buffer *buffer; + size_t buffer_size; + struct rb_node *best_fit = NULL; + void *has_page_addr; + void *end_page_addr; + size_t size; + + if (proc->vma == NULL) { + printk(KERN_ERR "binder: %d: binder_alloc_buf, no vma\n", + proc->pid); + return NULL; + } + + size = ALIGN(data_size, sizeof(void *)) + + ALIGN(offsets_size, sizeof(void *)); + + if (size < data_size || size < offsets_size) { + binder_user_error("binder: %d: got transaction with invalid " + "size %zd-%zd\n", proc->pid, data_size, offsets_size); + return NULL; + } + + if (is_async && + proc->free_async_space < size + sizeof(struct binder_buffer)) { + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: binder_alloc_buf size %zd" + "failed, no async space left\n", proc->pid, size); + return NULL; + } + + while (n) { + buffer = rb_entry(n, struct binder_buffer, rb_node); + BUG_ON(!buffer->free); + buffer_size = binder_buffer_size(proc, buffer); + + if (size < buffer_size) { + best_fit = n; + n = n->rb_left; + } else if (size > buffer_size) + n = n->rb_right; + else { + best_fit = n; + break; + } + } + if (best_fit == NULL) { + printk(KERN_ERR "binder: %d: binder_alloc_buf size %zd failed, " + "no address space\n", proc->pid, size); + return NULL; + } + if (n == NULL) { + buffer = rb_entry(best_fit, struct binder_buffer, rb_node); + buffer_size = binder_buffer_size(proc, buffer); + } + + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: binder_alloc_buf size %zd got buff" + "er %p size %zd\n", proc->pid, size, buffer, buffer_size); + + has_page_addr = + (void *)(((uintptr_t)buffer->data + buffer_size) & PAGE_MASK); + if (n == NULL) { + if (size + sizeof(struct binder_buffer) + 4 >= buffer_size) + buffer_size = size; /* no room for other buffers */ + else + buffer_size = size + sizeof(struct binder_buffer); + } + end_page_addr = + (void *)PAGE_ALIGN((uintptr_t)buffer->data + buffer_size); + if (end_page_addr > has_page_addr) + end_page_addr = has_page_addr; + if (binder_update_page_range(proc, 1, + (void *)PAGE_ALIGN((uintptr_t)buffer->data), end_page_addr, NULL)) + return NULL; + + rb_erase(best_fit, &proc->free_buffers); + buffer->free = 0; + binder_insert_allocated_buffer(proc, buffer); + if (buffer_size != size) { + struct binder_buffer *new_buffer = (void *)buffer->data + size; + list_add(&new_buffer->entry, &buffer->entry); + new_buffer->free = 1; + binder_insert_free_buffer(proc, new_buffer); + } + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: binder_alloc_buf size %zd got " + "%p\n", proc->pid, size, buffer); + buffer->data_size = data_size; + buffer->offsets_size = offsets_size; + buffer->async_transaction = is_async; + if (is_async) { + proc->free_async_space -= size + sizeof(struct binder_buffer); + binder_debug(BINDER_DEBUG_BUFFER_ALLOC_ASYNC, + "binder: %d: binder_alloc_buf size %zd " + "async free %zd\n", proc->pid, size, + proc->free_async_space); + } + + return buffer; +} + +static void *buffer_start_page(struct binder_buffer *buffer) +{ + return (void *)((uintptr_t)buffer & PAGE_MASK); +} + +static void *buffer_end_page(struct binder_buffer *buffer) +{ + return (void *)(((uintptr_t)(buffer + 1) - 1) & PAGE_MASK); +} + +static void binder_delete_free_buffer(struct binder_proc *proc, + struct binder_buffer *buffer) +{ + struct binder_buffer *prev, *next = NULL; + int free_page_end = 1; + int free_page_start = 1; + + BUG_ON(proc->buffers.next == &buffer->entry); + prev = list_entry(buffer->entry.prev, struct binder_buffer, entry); + BUG_ON(!prev->free); + if (buffer_end_page(prev) == buffer_start_page(buffer)) { + free_page_start = 0; + if (buffer_end_page(prev) == buffer_end_page(buffer)) + free_page_end = 0; + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: merge free, buffer %p " + "share page with %p\n", proc->pid, buffer, prev); + } + + if (!list_is_last(&buffer->entry, &proc->buffers)) { + next = list_entry(buffer->entry.next, + struct binder_buffer, entry); + if (buffer_start_page(next) == buffer_end_page(buffer)) { + free_page_end = 0; + if (buffer_start_page(next) == + buffer_start_page(buffer)) + free_page_start = 0; + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: merge free, buffer" + " %p share page with %p\n", proc->pid, + buffer, prev); + } + } + list_del(&buffer->entry); + if (free_page_start || free_page_end) { + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: merge free, buffer %p do " + "not share page%s%s with with %p or %p\n", + proc->pid, buffer, free_page_start ? "" : " end", + free_page_end ? "" : " start", prev, next); + binder_update_page_range(proc, 0, free_page_start ? + buffer_start_page(buffer) : buffer_end_page(buffer), + (free_page_end ? buffer_end_page(buffer) : + buffer_start_page(buffer)) + PAGE_SIZE, NULL); + } +} + +static void binder_free_buf(struct binder_proc *proc, + struct binder_buffer *buffer) +{ + size_t size, buffer_size; + + buffer_size = binder_buffer_size(proc, buffer); + + size = ALIGN(buffer->data_size, sizeof(void *)) + + ALIGN(buffer->offsets_size, sizeof(void *)); + + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder: %d: binder_free_buf %p size %zd buffer" + "_size %zd\n", proc->pid, buffer, size, buffer_size); + + BUG_ON(buffer->free); + BUG_ON(size > buffer_size); + BUG_ON(buffer->transaction != NULL); + BUG_ON((void *)buffer < proc->buffer); + BUG_ON((void *)buffer > proc->buffer + proc->buffer_size); + + if (buffer->async_transaction) { + proc->free_async_space += size + sizeof(struct binder_buffer); + + binder_debug(BINDER_DEBUG_BUFFER_ALLOC_ASYNC, + "binder: %d: binder_free_buf size %zd " + "async free %zd\n", proc->pid, size, + proc->free_async_space); + } + + binder_update_page_range(proc, 0, + (void *)PAGE_ALIGN((uintptr_t)buffer->data), + (void *)(((uintptr_t)buffer->data + buffer_size) & PAGE_MASK), + NULL); + rb_erase(&buffer->rb_node, &proc->allocated_buffers); + buffer->free = 1; + if (!list_is_last(&buffer->entry, &proc->buffers)) { + struct binder_buffer *next = list_entry(buffer->entry.next, + struct binder_buffer, entry); + if (next->free) { + rb_erase(&next->rb_node, &proc->free_buffers); + binder_delete_free_buffer(proc, next); + } + } + if (proc->buffers.next != &buffer->entry) { + struct binder_buffer *prev = list_entry(buffer->entry.prev, + struct binder_buffer, entry); + if (prev->free) { + binder_delete_free_buffer(proc, buffer); + rb_erase(&prev->rb_node, &proc->free_buffers); + buffer = prev; + } + } + binder_insert_free_buffer(proc, buffer); +} + +static struct binder_node *binder_get_node(struct binder_proc *proc, + void __user *ptr) +{ + struct rb_node *n = proc->nodes.rb_node; + struct binder_node *node; + + while (n) { + node = rb_entry(n, struct binder_node, rb_node); + + if (ptr < node->ptr) + n = n->rb_left; + else if (ptr > node->ptr) + n = n->rb_right; + else + return node; + } + return NULL; +} + +static struct binder_node *binder_new_node(struct binder_proc *proc, + void __user *ptr, + void __user *cookie) +{ + struct rb_node **p = &proc->nodes.rb_node; + struct rb_node *parent = NULL; + struct binder_node *node; + + while (*p) { + parent = *p; + node = rb_entry(parent, struct binder_node, rb_node); + + if (ptr < node->ptr) + p = &(*p)->rb_left; + else if (ptr > node->ptr) + p = &(*p)->rb_right; + else + return NULL; + } + + node = kzalloc(sizeof(*node), GFP_KERNEL); + if (node == NULL) + return NULL; + binder_stats_created(BINDER_STAT_NODE); + rb_link_node(&node->rb_node, parent, p); + rb_insert_color(&node->rb_node, &proc->nodes); + node->debug_id = ++binder_last_id; + node->proc = proc; + node->ptr = ptr; + node->cookie = cookie; + node->work.type = BINDER_WORK_NODE; + INIT_LIST_HEAD(&node->work.entry); + INIT_LIST_HEAD(&node->async_todo); + binder_debug(BINDER_DEBUG_INTERNAL_REFS, + "binder: %d:%d node %d u%p c%p created\n", + proc->pid, current->pid, node->debug_id, + node->ptr, node->cookie); + return node; +} + +static int binder_inc_node(struct binder_node *node, int strong, int internal, + struct list_head *target_list) +{ + if (strong) { + if (internal) { + if (target_list == NULL && + node->internal_strong_refs == 0 && + !(node == binder_context_mgr_node && + node->has_strong_ref)) { + printk(KERN_ERR "binder: invalid inc strong " + "node for %d\n", node->debug_id); + return -EINVAL; + } + node->internal_strong_refs++; + } else + node->local_strong_refs++; + if (!node->has_strong_ref && target_list) { + list_del_init(&node->work.entry); + list_add_tail(&node->work.entry, target_list); + } + } else { + if (!internal) + node->local_weak_refs++; + if (!node->has_weak_ref && list_empty(&node->work.entry)) { + if (target_list == NULL) { + printk(KERN_ERR "binder: invalid inc weak node " + "for %d\n", node->debug_id); + return -EINVAL; + } + list_add_tail(&node->work.entry, target_list); + } + } + return 0; +} + +static int binder_dec_node(struct binder_node *node, int strong, int internal) +{ + if (strong) { + if (internal) + node->internal_strong_refs--; + else + node->local_strong_refs--; + if (node->local_strong_refs || node->internal_strong_refs) + return 0; + } else { + if (!internal) + node->local_weak_refs--; + if (node->local_weak_refs || !hlist_empty(&node->refs)) + return 0; + } + if (node->proc && (node->has_strong_ref || node->has_weak_ref)) { + if (list_empty(&node->work.entry)) { + list_add_tail(&node->work.entry, &node->proc->todo); + wake_up_interruptible(&node->proc->wait); + } + } else { + if (hlist_empty(&node->refs) && !node->local_strong_refs && + !node->local_weak_refs) { + list_del_init(&node->work.entry); + if (node->proc) { + rb_erase(&node->rb_node, &node->proc->nodes); + binder_debug(BINDER_DEBUG_INTERNAL_REFS, + "binder: refless node %d deleted\n", + node->debug_id); + } else { + hlist_del(&node->dead_node); + binder_debug(BINDER_DEBUG_INTERNAL_REFS, + "binder: dead node %d deleted\n", + node->debug_id); + } + kfree(node); + binder_stats_deleted(BINDER_STAT_NODE); + } + } + + return 0; +} + + +static struct binder_ref *binder_get_ref(struct binder_proc *proc, + uint32_t desc) +{ + struct rb_node *n = proc->refs_by_desc.rb_node; + struct binder_ref *ref; + + while (n) { + ref = rb_entry(n, struct binder_ref, rb_node_desc); + + if (desc < ref->desc) + n = n->rb_left; + else if (desc > ref->desc) + n = n->rb_right; + else + return ref; + } + return NULL; +} + +static struct binder_ref *binder_get_ref_for_node(struct binder_proc *proc, + struct binder_node *node) +{ + struct rb_node *n; + struct rb_node **p = &proc->refs_by_node.rb_node; + struct rb_node *parent = NULL; + struct binder_ref *ref, *new_ref; + + while (*p) { + parent = *p; + ref = rb_entry(parent, struct binder_ref, rb_node_node); + + if (node < ref->node) + p = &(*p)->rb_left; + else if (node > ref->node) + p = &(*p)->rb_right; + else + return ref; + } + new_ref = kzalloc(sizeof(*ref), GFP_KERNEL); + if (new_ref == NULL) + return NULL; + binder_stats_created(BINDER_STAT_REF); + new_ref->debug_id = ++binder_last_id; + new_ref->proc = proc; + new_ref->node = node; + rb_link_node(&new_ref->rb_node_node, parent, p); + rb_insert_color(&new_ref->rb_node_node, &proc->refs_by_node); + + new_ref->desc = (node == binder_context_mgr_node) ? 0 : 1; + for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) { + ref = rb_entry(n, struct binder_ref, rb_node_desc); + if (ref->desc > new_ref->desc) + break; + new_ref->desc = ref->desc + 1; + } + + p = &proc->refs_by_desc.rb_node; + while (*p) { + parent = *p; + ref = rb_entry(parent, struct binder_ref, rb_node_desc); + + if (new_ref->desc < ref->desc) + p = &(*p)->rb_left; + else if (new_ref->desc > ref->desc) + p = &(*p)->rb_right; + else + BUG(); + } + rb_link_node(&new_ref->rb_node_desc, parent, p); + rb_insert_color(&new_ref->rb_node_desc, &proc->refs_by_desc); + if (node) { + hlist_add_head(&new_ref->node_entry, &node->refs); + + binder_debug(BINDER_DEBUG_INTERNAL_REFS, + "binder: %d new ref %d desc %d for " + "node %d\n", proc->pid, new_ref->debug_id, + new_ref->desc, node->debug_id); + } else { + binder_debug(BINDER_DEBUG_INTERNAL_REFS, + "binder: %d new ref %d desc %d for " + "dead node\n", proc->pid, new_ref->debug_id, + new_ref->desc); + } + return new_ref; +} + +static void binder_delete_ref(struct binder_ref *ref) +{ + binder_debug(BINDER_DEBUG_INTERNAL_REFS, + "binder: %d delete ref %d desc %d for " + "node %d\n", ref->proc->pid, ref->debug_id, + ref->desc, ref->node->debug_id); + + rb_erase(&ref->rb_node_desc, &ref->proc->refs_by_desc); + rb_erase(&ref->rb_node_node, &ref->proc->refs_by_node); + if (ref->strong) + binder_dec_node(ref->node, 1, 1); + hlist_del(&ref->node_entry); + binder_dec_node(ref->node, 0, 1); + if (ref->death) { + binder_debug(BINDER_DEBUG_DEAD_BINDER, + "binder: %d delete ref %d desc %d " + "has death notification\n", ref->proc->pid, + ref->debug_id, ref->desc); + list_del(&ref->death->work.entry); + kfree(ref->death); + binder_stats_deleted(BINDER_STAT_DEATH); + } + kfree(ref); + binder_stats_deleted(BINDER_STAT_REF); +} + +static int binder_inc_ref(struct binder_ref *ref, int strong, + struct list_head *target_list) +{ + int ret; + if (strong) { + if (ref->strong == 0) { + ret = binder_inc_node(ref->node, 1, 1, target_list); + if (ret) + return ret; + } + ref->strong++; + } else { + if (ref->weak == 0) { + ret = binder_inc_node(ref->node, 0, 1, target_list); + if (ret) + return ret; + } + ref->weak++; + } + return 0; +} + + +static int binder_dec_ref(struct binder_ref *ref, int strong) +{ + if (strong) { + if (ref->strong == 0) { + binder_user_error("binder: %d invalid dec strong, " + "ref %d desc %d s %d w %d\n", + ref->proc->pid, ref->debug_id, + ref->desc, ref->strong, ref->weak); + return -EINVAL; + } + ref->strong--; + if (ref->strong == 0) { + int ret; + ret = binder_dec_node(ref->node, strong, 1); + if (ret) + return ret; + } + } else { + if (ref->weak == 0) { + binder_user_error("binder: %d invalid dec weak, " + "ref %d desc %d s %d w %d\n", + ref->proc->pid, ref->debug_id, + ref->desc, ref->strong, ref->weak); + return -EINVAL; + } + ref->weak--; + } + if (ref->strong == 0 && ref->weak == 0) + binder_delete_ref(ref); + return 0; +} + +static void binder_pop_transaction(struct binder_thread *target_thread, + struct binder_transaction *t) +{ + if (target_thread) { + BUG_ON(target_thread->transaction_stack != t); + BUG_ON(target_thread->transaction_stack->from != target_thread); + target_thread->transaction_stack = + target_thread->transaction_stack->from_parent; + t->from = NULL; + } + t->need_reply = 0; + if (t->buffer) + t->buffer->transaction = NULL; + kfree(t); + binder_stats_deleted(BINDER_STAT_TRANSACTION); +} + +static void binder_send_failed_reply(struct binder_transaction *t, + uint32_t error_code) +{ + struct binder_thread *target_thread; + BUG_ON(t->flags & TF_ONE_WAY); + while (1) { + target_thread = t->from; + if (target_thread) { + if (target_thread->return_error != BR_OK && + target_thread->return_error2 == BR_OK) { + target_thread->return_error2 = + target_thread->return_error; + target_thread->return_error = BR_OK; + } + if (target_thread->return_error == BR_OK) { + binder_debug(BINDER_DEBUG_FAILED_TRANSACTION, + "binder: send failed reply for " + "transaction %d to %d:%d\n", + t->debug_id, target_thread->proc->pid, + target_thread->pid); + + binder_pop_transaction(target_thread, t); + target_thread->return_error = error_code; + wake_up_interruptible(&target_thread->wait); + } else { + printk(KERN_ERR "binder: reply failed, target " + "thread, %d:%d, has error code %d " + "already\n", target_thread->proc->pid, + target_thread->pid, + target_thread->return_error); + } + return; + } else { + struct binder_transaction *next = t->from_parent; + + binder_debug(BINDER_DEBUG_FAILED_TRANSACTION, + "binder: send failed reply " + "for transaction %d, target dead\n", + t->debug_id); + + binder_pop_transaction(target_thread, t); + if (next == NULL) { + binder_debug(BINDER_DEBUG_DEAD_BINDER, + "binder: reply failed," + " no target thread at root\n"); + return; + } + t = next; + binder_debug(BINDER_DEBUG_DEAD_BINDER, + "binder: reply failed, no target " + "thread -- retry %d\n", t->debug_id); + } + } +} + +static void binder_transaction_buffer_release(struct binder_proc *proc, + struct binder_buffer *buffer, + size_t *failed_at) +{ + size_t *offp, *off_end; + int debug_id = buffer->debug_id; + + binder_debug(BINDER_DEBUG_TRANSACTION, + "binder: %d buffer release %d, size %zd-%zd, failed at %p\n", + proc->pid, buffer->debug_id, + buffer->data_size, buffer->offsets_size, failed_at); + + if (buffer->target_node) + binder_dec_node(buffer->target_node, 1, 0); + + offp = (size_t *)(buffer->data + ALIGN(buffer->data_size, sizeof(void *))); + if (failed_at) + off_end = failed_at; + else + off_end = (void *)offp + buffer->offsets_size; + for (; offp < off_end; offp++) { + struct flat_binder_object *fp; + if (*offp > buffer->data_size - sizeof(*fp) || + buffer->data_size < sizeof(*fp) || + !IS_ALIGNED(*offp, sizeof(void *))) { + printk(KERN_ERR "binder: transaction release %d bad" + "offset %zd, size %zd\n", debug_id, + *offp, buffer->data_size); + continue; + } + fp = (struct flat_binder_object *)(buffer->data + *offp); + switch (fp->type) { + case BINDER_TYPE_BINDER: + case BINDER_TYPE_WEAK_BINDER: { + struct binder_node *node = binder_get_node(proc, fp->binder); + if (node == NULL) { + printk(KERN_ERR "binder: transaction release %d" + " bad node %p\n", debug_id, fp->binder); + break; + } + binder_debug(BINDER_DEBUG_TRANSACTION, + " node %d u%p\n", + node->debug_id, node->ptr); + binder_dec_node(node, fp->type == BINDER_TYPE_BINDER, 0); + } break; + case BINDER_TYPE_HANDLE: + case BINDER_TYPE_WEAK_HANDLE: { + struct binder_ref *ref = binder_get_ref(proc, fp->handle); + if (ref == NULL) { + printk(KERN_ERR "binder: transaction release %d" + " bad handle %ld\n", debug_id, + fp->handle); + break; + } + binder_debug(BINDER_DEBUG_TRANSACTION, + " ref %d desc %d (node %d)\n", + ref->debug_id, ref->desc, ref->node->debug_id); + binder_dec_ref(ref, fp->type == BINDER_TYPE_HANDLE); + } break; + + case BINDER_TYPE_FD: + binder_debug(BINDER_DEBUG_TRANSACTION, + " fd %ld\n", fp->handle); + if (failed_at) + task_close_fd(proc, fp->handle); + break; + + default: + printk(KERN_ERR "binder: transaction release %d bad " + "object type %lx\n", debug_id, fp->type); + break; + } + } +} + +static void binder_transaction(struct binder_proc *proc, + struct binder_thread *thread, + struct binder_transaction_data *tr, int reply) +{ + struct binder_transaction *t; + struct binder_work *tcomplete; + size_t *offp, *off_end; + struct binder_proc *target_proc; + struct binder_thread *target_thread = NULL; + struct binder_node *target_node = NULL; + struct list_head *target_list; + wait_queue_head_t *target_wait; + struct binder_transaction *in_reply_to = NULL; + struct binder_transaction_log_entry *e; + uint32_t return_error; + + e = binder_transaction_log_add(&binder_transaction_log); + e->call_type = reply ? 2 : !!(tr->flags & TF_ONE_WAY); + e->from_proc = proc->pid; + e->from_thread = thread->pid; + e->target_handle = tr->target.handle; + e->data_size = tr->data_size; + e->offsets_size = tr->offsets_size; + + if (reply) { + in_reply_to = thread->transaction_stack; + if (in_reply_to == NULL) { + binder_user_error("binder: %d:%d got reply transaction " + "with no transaction stack\n", + proc->pid, thread->pid); + return_error = BR_FAILED_REPLY; + goto err_empty_call_stack; + } + binder_set_nice(in_reply_to->saved_priority); + if (in_reply_to->to_thread != thread) { + binder_user_error("binder: %d:%d got reply transaction " + "with bad transaction stack," + " transaction %d has target %d:%d\n", + proc->pid, thread->pid, in_reply_to->debug_id, + in_reply_to->to_proc ? + in_reply_to->to_proc->pid : 0, + in_reply_to->to_thread ? + in_reply_to->to_thread->pid : 0); + return_error = BR_FAILED_REPLY; + in_reply_to = NULL; + goto err_bad_call_stack; + } + thread->transaction_stack = in_reply_to->to_parent; + target_thread = in_reply_to->from; + if (target_thread == NULL) { + return_error = BR_DEAD_REPLY; + goto err_dead_binder; + } + if (target_thread->transaction_stack != in_reply_to) { + binder_user_error("binder: %d:%d got reply transaction " + "with bad target transaction stack %d, " + "expected %d\n", + proc->pid, thread->pid, + target_thread->transaction_stack ? + target_thread->transaction_stack->debug_id : 0, + in_reply_to->debug_id); + return_error = BR_FAILED_REPLY; + in_reply_to = NULL; + target_thread = NULL; + goto err_dead_binder; + } + target_proc = target_thread->proc; + } else { + if (tr->target.handle) { + struct binder_ref *ref; + ref = binder_get_ref(proc, tr->target.handle); + if (ref == NULL) { + binder_user_error("binder: %d:%d got " + "transaction to invalid handle\n", + proc->pid, thread->pid); + return_error = BR_FAILED_REPLY; + goto err_invalid_target_handle; + } + target_node = ref->node; + } else { + target_node = binder_context_mgr_node; + if (target_node == NULL) { + return_error = BR_DEAD_REPLY; + goto err_no_context_mgr_node; + } + } + e->to_node = target_node->debug_id; + target_proc = target_node->proc; + if (target_proc == NULL) { + return_error = BR_DEAD_REPLY; + goto err_dead_binder; + } + if (!(tr->flags & TF_ONE_WAY) && thread->transaction_stack) { + struct binder_transaction *tmp; + tmp = thread->transaction_stack; + if (tmp->to_thread != thread) { + binder_user_error("binder: %d:%d got new " + "transaction with bad transaction stack" + ", transaction %d has target %d:%d\n", + proc->pid, thread->pid, tmp->debug_id, + tmp->to_proc ? tmp->to_proc->pid : 0, + tmp->to_thread ? + tmp->to_thread->pid : 0); + return_error = BR_FAILED_REPLY; + goto err_bad_call_stack; + } + while (tmp) { + if (tmp->from && tmp->from->proc == target_proc) + target_thread = tmp->from; + tmp = tmp->from_parent; + } + } + } + if (target_thread) { + e->to_thread = target_thread->pid; + target_list = &target_thread->todo; + target_wait = &target_thread->wait; + } else { + target_list = &target_proc->todo; + target_wait = &target_proc->wait; + } + e->to_proc = target_proc->pid; + + /* TODO: reuse incoming transaction for reply */ + t = kzalloc(sizeof(*t), GFP_KERNEL); + if (t == NULL) { + return_error = BR_FAILED_REPLY; + goto err_alloc_t_failed; + } + binder_stats_created(BINDER_STAT_TRANSACTION); + + tcomplete = kzalloc(sizeof(*tcomplete), GFP_KERNEL); + if (tcomplete == NULL) { + return_error = BR_FAILED_REPLY; + goto err_alloc_tcomplete_failed; + } + binder_stats_created(BINDER_STAT_TRANSACTION_COMPLETE); + + t->debug_id = ++binder_last_id; + e->debug_id = t->debug_id; + + if (reply) + binder_debug(BINDER_DEBUG_TRANSACTION, + "binder: %d:%d BC_REPLY %d -> %d:%d, " + "data %p-%p size %zd-%zd\n", + proc->pid, thread->pid, t->debug_id, + target_proc->pid, target_thread->pid, + tr->data.ptr.buffer, tr->data.ptr.offsets, + tr->data_size, tr->offsets_size); + else + binder_debug(BINDER_DEBUG_TRANSACTION, + "binder: %d:%d BC_TRANSACTION %d -> " + "%d - node %d, data %p-%p size %zd-%zd\n", + proc->pid, thread->pid, t->debug_id, + target_proc->pid, target_node->debug_id, + tr->data.ptr.buffer, tr->data.ptr.offsets, + tr->data_size, tr->offsets_size); + + if (!reply && !(tr->flags & TF_ONE_WAY)) + t->from = thread; + else + t->from = NULL; + t->sender_euid = proc->tsk->cred->euid; + t->to_proc = target_proc; + t->to_thread = target_thread; + t->code = tr->code; + t->flags = tr->flags; + t->priority = task_nice(current); + t->buffer = binder_alloc_buf(target_proc, tr->data_size, + tr->offsets_size, !reply && (t->flags & TF_ONE_WAY)); + if (t->buffer == NULL) { + return_error = BR_FAILED_REPLY; + goto err_binder_alloc_buf_failed; + } + t->buffer->allow_user_free = 0; + t->buffer->debug_id = t->debug_id; + t->buffer->transaction = t; + t->buffer->target_node = target_node; + if (target_node) + binder_inc_node(target_node, 1, 0, NULL); + + offp = (size_t *)(t->buffer->data + ALIGN(tr->data_size, sizeof(void *))); + + if (copy_from_user(t->buffer->data, tr->data.ptr.buffer, tr->data_size)) { + binder_user_error("binder: %d:%d got transaction with invalid " + "data ptr\n", proc->pid, thread->pid); + return_error = BR_FAILED_REPLY; + goto err_copy_data_failed; + } + if (copy_from_user(offp, tr->data.ptr.offsets, tr->offsets_size)) { + binder_user_error("binder: %d:%d got transaction with invalid " + "offsets ptr\n", proc->pid, thread->pid); + return_error = BR_FAILED_REPLY; + goto err_copy_data_failed; + } + if (!IS_ALIGNED(tr->offsets_size, sizeof(size_t))) { + binder_user_error("binder: %d:%d got transaction with " + "invalid offsets size, %zd\n", + proc->pid, thread->pid, tr->offsets_size); + return_error = BR_FAILED_REPLY; + goto err_bad_offset; + } + off_end = (void *)offp + tr->offsets_size; + for (; offp < off_end; offp++) { + struct flat_binder_object *fp; + if (*offp > t->buffer->data_size - sizeof(*fp) || + t->buffer->data_size < sizeof(*fp) || + !IS_ALIGNED(*offp, sizeof(void *))) { + binder_user_error("binder: %d:%d got transaction with " + "invalid offset, %zd\n", + proc->pid, thread->pid, *offp); + return_error = BR_FAILED_REPLY; + goto err_bad_offset; + } + fp = (struct flat_binder_object *)(t->buffer->data + *offp); + switch (fp->type) { + case BINDER_TYPE_BINDER: + case BINDER_TYPE_WEAK_BINDER: { + struct binder_ref *ref; + struct binder_node *node = binder_get_node(proc, fp->binder); + if (node == NULL) { + node = binder_new_node(proc, fp->binder, fp->cookie); + if (node == NULL) { + return_error = BR_FAILED_REPLY; + goto err_binder_new_node_failed; + } + node->min_priority = fp->flags & FLAT_BINDER_FLAG_PRIORITY_MASK; + node->accept_fds = !!(fp->flags & FLAT_BINDER_FLAG_ACCEPTS_FDS); + } + if (fp->cookie != node->cookie) { + binder_user_error("binder: %d:%d sending u%p " + "node %d, cookie mismatch %p != %p\n", + proc->pid, thread->pid, + fp->binder, node->debug_id, + fp->cookie, node->cookie); + goto err_binder_get_ref_for_node_failed; + } + ref = binder_get_ref_for_node(target_proc, node); + if (ref == NULL) { + return_error = BR_FAILED_REPLY; + goto err_binder_get_ref_for_node_failed; + } + if (fp->type == BINDER_TYPE_BINDER) + fp->type = BINDER_TYPE_HANDLE; + else + fp->type = BINDER_TYPE_WEAK_HANDLE; + fp->handle = ref->desc; + binder_inc_ref(ref, fp->type == BINDER_TYPE_HANDLE, + &thread->todo); + + binder_debug(BINDER_DEBUG_TRANSACTION, + " node %d u%p -> ref %d desc %d\n", + node->debug_id, node->ptr, ref->debug_id, + ref->desc); + } break; + case BINDER_TYPE_HANDLE: + case BINDER_TYPE_WEAK_HANDLE: { + struct binder_ref *ref = binder_get_ref(proc, fp->handle); + if (ref == NULL) { + binder_user_error("binder: %d:%d got " + "transaction with invalid " + "handle, %ld\n", proc->pid, + thread->pid, fp->handle); + return_error = BR_FAILED_REPLY; + goto err_binder_get_ref_failed; + } + if (ref->node->proc == target_proc) { + if (fp->type == BINDER_TYPE_HANDLE) + fp->type = BINDER_TYPE_BINDER; + else + fp->type = BINDER_TYPE_WEAK_BINDER; + fp->binder = ref->node->ptr; + fp->cookie = ref->node->cookie; + binder_inc_node(ref->node, fp->type == BINDER_TYPE_BINDER, 0, NULL); + binder_debug(BINDER_DEBUG_TRANSACTION, + " ref %d desc %d -> node %d u%p\n", + ref->debug_id, ref->desc, ref->node->debug_id, + ref->node->ptr); + } else { + struct binder_ref *new_ref; + new_ref = binder_get_ref_for_node(target_proc, ref->node); + if (new_ref == NULL) { + return_error = BR_FAILED_REPLY; + goto err_binder_get_ref_for_node_failed; + } + fp->handle = new_ref->desc; + binder_inc_ref(new_ref, fp->type == BINDER_TYPE_HANDLE, NULL); + binder_debug(BINDER_DEBUG_TRANSACTION, + " ref %d desc %d -> ref %d desc %d (node %d)\n", + ref->debug_id, ref->desc, new_ref->debug_id, + new_ref->desc, ref->node->debug_id); + } + } break; + + case BINDER_TYPE_FD: { + int target_fd; + struct file *file; + + if (reply) { + if (!(in_reply_to->flags & TF_ACCEPT_FDS)) { + binder_user_error("binder: %d:%d got reply with fd, %ld, but target does not allow fds\n", + proc->pid, thread->pid, fp->handle); + return_error = BR_FAILED_REPLY; + goto err_fd_not_allowed; + } + } else if (!target_node->accept_fds) { + binder_user_error("binder: %d:%d got transaction with fd, %ld, but target does not allow fds\n", + proc->pid, thread->pid, fp->handle); + return_error = BR_FAILED_REPLY; + goto err_fd_not_allowed; + } + + file = fget(fp->handle); + if (file == NULL) { + binder_user_error("binder: %d:%d got transaction with invalid fd, %ld\n", + proc->pid, thread->pid, fp->handle); + return_error = BR_FAILED_REPLY; + goto err_fget_failed; + } + target_fd = task_get_unused_fd_flags(target_proc, O_CLOEXEC); + if (target_fd < 0) { + fput(file); + return_error = BR_FAILED_REPLY; + goto err_get_unused_fd_failed; + } + task_fd_install(target_proc, target_fd, file); + binder_debug(BINDER_DEBUG_TRANSACTION, + " fd %ld -> %d\n", fp->handle, target_fd); + /* TODO: fput? */ + fp->handle = target_fd; + } break; + + default: + binder_user_error("binder: %d:%d got transactio" + "n with invalid object type, %lx\n", + proc->pid, thread->pid, fp->type); + return_error = BR_FAILED_REPLY; + goto err_bad_object_type; + } + } + if (reply) { + BUG_ON(t->buffer->async_transaction != 0); + binder_pop_transaction(target_thread, in_reply_to); + } else if (!(t->flags & TF_ONE_WAY)) { + BUG_ON(t->buffer->async_transaction != 0); + t->need_reply = 1; + t->from_parent = thread->transaction_stack; + thread->transaction_stack = t; + } else { + BUG_ON(target_node == NULL); + BUG_ON(t->buffer->async_transaction != 1); + if (target_node->has_async_transaction) { + target_list = &target_node->async_todo; + target_wait = NULL; + } else + target_node->has_async_transaction = 1; + } + t->work.type = BINDER_WORK_TRANSACTION; + list_add_tail(&t->work.entry, target_list); + tcomplete->type = BINDER_WORK_TRANSACTION_COMPLETE; + list_add_tail(&tcomplete->entry, &thread->todo); + if (target_wait) + wake_up_interruptible(target_wait); + return; + +err_get_unused_fd_failed: +err_fget_failed: +err_fd_not_allowed: +err_binder_get_ref_for_node_failed: +err_binder_get_ref_failed: +err_binder_new_node_failed: +err_bad_object_type: +err_bad_offset: +err_copy_data_failed: + binder_transaction_buffer_release(target_proc, t->buffer, offp); + t->buffer->transaction = NULL; + binder_free_buf(target_proc, t->buffer); +err_binder_alloc_buf_failed: + kfree(tcomplete); + binder_stats_deleted(BINDER_STAT_TRANSACTION_COMPLETE); +err_alloc_tcomplete_failed: + kfree(t); + binder_stats_deleted(BINDER_STAT_TRANSACTION); +err_alloc_t_failed: +err_bad_call_stack: +err_empty_call_stack: +err_dead_binder: +err_invalid_target_handle: +err_no_context_mgr_node: + binder_debug(BINDER_DEBUG_FAILED_TRANSACTION, + "binder: %d:%d transaction failed %d, size %zd-%zd\n", + proc->pid, thread->pid, return_error, + tr->data_size, tr->offsets_size); + + { + struct binder_transaction_log_entry *fe; + fe = binder_transaction_log_add(&binder_transaction_log_failed); + *fe = *e; + } + + BUG_ON(thread->return_error != BR_OK); + if (in_reply_to) { + thread->return_error = BR_TRANSACTION_COMPLETE; + binder_send_failed_reply(in_reply_to, return_error); + } else + thread->return_error = return_error; +} + +int binder_thread_write(struct binder_proc *proc, struct binder_thread *thread, + void __user *buffer, int size, signed long *consumed) +{ + uint32_t cmd; + void __user *ptr = buffer + *consumed; + void __user *end = buffer + size; + + while (ptr < end && thread->return_error == BR_OK) { + if (get_user(cmd, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.bc)) { + binder_stats.bc[_IOC_NR(cmd)]++; + proc->stats.bc[_IOC_NR(cmd)]++; + thread->stats.bc[_IOC_NR(cmd)]++; + } + switch (cmd) { + case BC_INCREFS: + case BC_ACQUIRE: + case BC_RELEASE: + case BC_DECREFS: { + uint32_t target; + struct binder_ref *ref; + const char *debug_string; + + if (get_user(target, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + if (target == 0 && binder_context_mgr_node && + (cmd == BC_INCREFS || cmd == BC_ACQUIRE)) { + ref = binder_get_ref_for_node(proc, + binder_context_mgr_node); + if (ref->desc != target) { + binder_user_error("binder: %d:" + "%d tried to acquire " + "reference to desc 0, " + "got %d instead\n", + proc->pid, thread->pid, + ref->desc); + } + } else + ref = binder_get_ref(proc, target); + if (ref == NULL) { + binder_user_error("binder: %d:%d refcou" + "nt change on invalid ref %d\n", + proc->pid, thread->pid, target); + break; + } + switch (cmd) { + case BC_INCREFS: + debug_string = "IncRefs"; + binder_inc_ref(ref, 0, NULL); + break; + case BC_ACQUIRE: + debug_string = "Acquire"; + binder_inc_ref(ref, 1, NULL); + break; + case BC_RELEASE: + debug_string = "Release"; + binder_dec_ref(ref, 1); + break; + case BC_DECREFS: + default: + debug_string = "DecRefs"; + binder_dec_ref(ref, 0); + break; + } + binder_debug(BINDER_DEBUG_USER_REFS, + "binder: %d:%d %s ref %d desc %d s %d w %d for node %d\n", + proc->pid, thread->pid, debug_string, ref->debug_id, + ref->desc, ref->strong, ref->weak, ref->node->debug_id); + break; + } + case BC_INCREFS_DONE: + case BC_ACQUIRE_DONE: { + void __user *node_ptr; + void *cookie; + struct binder_node *node; + + if (get_user(node_ptr, (void * __user *)ptr)) + return -EFAULT; + ptr += sizeof(void *); + if (get_user(cookie, (void * __user *)ptr)) + return -EFAULT; + ptr += sizeof(void *); + node = binder_get_node(proc, node_ptr); + if (node == NULL) { + binder_user_error("binder: %d:%d " + "%s u%p no match\n", + proc->pid, thread->pid, + cmd == BC_INCREFS_DONE ? + "BC_INCREFS_DONE" : + "BC_ACQUIRE_DONE", + node_ptr); + break; + } + if (cookie != node->cookie) { + binder_user_error("binder: %d:%d %s u%p node %d" + " cookie mismatch %p != %p\n", + proc->pid, thread->pid, + cmd == BC_INCREFS_DONE ? + "BC_INCREFS_DONE" : "BC_ACQUIRE_DONE", + node_ptr, node->debug_id, + cookie, node->cookie); + break; + } + if (cmd == BC_ACQUIRE_DONE) { + if (node->pending_strong_ref == 0) { + binder_user_error("binder: %d:%d " + "BC_ACQUIRE_DONE node %d has " + "no pending acquire request\n", + proc->pid, thread->pid, + node->debug_id); + break; + } + node->pending_strong_ref = 0; + } else { + if (node->pending_weak_ref == 0) { + binder_user_error("binder: %d:%d " + "BC_INCREFS_DONE node %d has " + "no pending increfs request\n", + proc->pid, thread->pid, + node->debug_id); + break; + } + node->pending_weak_ref = 0; + } + binder_dec_node(node, cmd == BC_ACQUIRE_DONE, 0); + binder_debug(BINDER_DEBUG_USER_REFS, + "binder: %d:%d %s node %d ls %d lw %d\n", + proc->pid, thread->pid, + cmd == BC_INCREFS_DONE ? "BC_INCREFS_DONE" : "BC_ACQUIRE_DONE", + node->debug_id, node->local_strong_refs, node->local_weak_refs); + break; + } + case BC_ATTEMPT_ACQUIRE: + printk(KERN_ERR "binder: BC_ATTEMPT_ACQUIRE not supported\n"); + return -EINVAL; + case BC_ACQUIRE_RESULT: + printk(KERN_ERR "binder: BC_ACQUIRE_RESULT not supported\n"); + return -EINVAL; + + case BC_FREE_BUFFER: { + void __user *data_ptr; + struct binder_buffer *buffer; + + if (get_user(data_ptr, (void * __user *)ptr)) + return -EFAULT; + ptr += sizeof(void *); + + buffer = binder_buffer_lookup(proc, data_ptr); + if (buffer == NULL) { + binder_user_error("binder: %d:%d " + "BC_FREE_BUFFER u%p no match\n", + proc->pid, thread->pid, data_ptr); + break; + } + if (!buffer->allow_user_free) { + binder_user_error("binder: %d:%d " + "BC_FREE_BUFFER u%p matched " + "unreturned buffer\n", + proc->pid, thread->pid, data_ptr); + break; + } + binder_debug(BINDER_DEBUG_FREE_BUFFER, + "binder: %d:%d BC_FREE_BUFFER u%p found buffer %d for %s transaction\n", + proc->pid, thread->pid, data_ptr, buffer->debug_id, + buffer->transaction ? "active" : "finished"); + + if (buffer->transaction) { + buffer->transaction->buffer = NULL; + buffer->transaction = NULL; + } + if (buffer->async_transaction && buffer->target_node) { + BUG_ON(!buffer->target_node->has_async_transaction); + if (list_empty(&buffer->target_node->async_todo)) + buffer->target_node->has_async_transaction = 0; + else + list_move_tail(buffer->target_node->async_todo.next, &thread->todo); + } + binder_transaction_buffer_release(proc, buffer, NULL); + binder_free_buf(proc, buffer); + break; + } + + case BC_TRANSACTION: + case BC_REPLY: { + struct binder_transaction_data tr; + + if (copy_from_user(&tr, ptr, sizeof(tr))) + return -EFAULT; + ptr += sizeof(tr); + binder_transaction(proc, thread, &tr, cmd == BC_REPLY); + break; + } + + case BC_REGISTER_LOOPER: + binder_debug(BINDER_DEBUG_THREADS, + "binder: %d:%d BC_REGISTER_LOOPER\n", + proc->pid, thread->pid); + if (thread->looper & BINDER_LOOPER_STATE_ENTERED) { + thread->looper |= BINDER_LOOPER_STATE_INVALID; + binder_user_error("binder: %d:%d ERROR:" + " BC_REGISTER_LOOPER called " + "after BC_ENTER_LOOPER\n", + proc->pid, thread->pid); + } else if (proc->requested_threads == 0) { + thread->looper |= BINDER_LOOPER_STATE_INVALID; + binder_user_error("binder: %d:%d ERROR:" + " BC_REGISTER_LOOPER called " + "without request\n", + proc->pid, thread->pid); + } else { + proc->requested_threads--; + proc->requested_threads_started++; + } + thread->looper |= BINDER_LOOPER_STATE_REGISTERED; + break; + case BC_ENTER_LOOPER: + binder_debug(BINDER_DEBUG_THREADS, + "binder: %d:%d BC_ENTER_LOOPER\n", + proc->pid, thread->pid); + if (thread->looper & BINDER_LOOPER_STATE_REGISTERED) { + thread->looper |= BINDER_LOOPER_STATE_INVALID; + binder_user_error("binder: %d:%d ERROR:" + " BC_ENTER_LOOPER called after " + "BC_REGISTER_LOOPER\n", + proc->pid, thread->pid); + } + thread->looper |= BINDER_LOOPER_STATE_ENTERED; + break; + case BC_EXIT_LOOPER: + binder_debug(BINDER_DEBUG_THREADS, + "binder: %d:%d BC_EXIT_LOOPER\n", + proc->pid, thread->pid); + thread->looper |= BINDER_LOOPER_STATE_EXITED; + break; + + case BC_REQUEST_DEATH_NOTIFICATION: + case BC_CLEAR_DEATH_NOTIFICATION: { + uint32_t target; + void __user *cookie; + struct binder_ref *ref; + struct binder_ref_death *death; + + if (get_user(target, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + if (get_user(cookie, (void __user * __user *)ptr)) + return -EFAULT; + ptr += sizeof(void *); + ref = binder_get_ref(proc, target); + if (ref == NULL) { + binder_user_error("binder: %d:%d %s " + "invalid ref %d\n", + proc->pid, thread->pid, + cmd == BC_REQUEST_DEATH_NOTIFICATION ? + "BC_REQUEST_DEATH_NOTIFICATION" : + "BC_CLEAR_DEATH_NOTIFICATION", + target); + break; + } + + binder_debug(BINDER_DEBUG_DEATH_NOTIFICATION, + "binder: %d:%d %s %p ref %d desc %d s %d w %d for node %d\n", + proc->pid, thread->pid, + cmd == BC_REQUEST_DEATH_NOTIFICATION ? + "BC_REQUEST_DEATH_NOTIFICATION" : + "BC_CLEAR_DEATH_NOTIFICATION", + cookie, ref->debug_id, ref->desc, + ref->strong, ref->weak, ref->node->debug_id); + + if (cmd == BC_REQUEST_DEATH_NOTIFICATION) { + if (ref->death) { + binder_user_error("binder: %d:%" + "d BC_REQUEST_DEATH_NOTI" + "FICATION death notific" + "ation already set\n", + proc->pid, thread->pid); + break; + } + death = kzalloc(sizeof(*death), GFP_KERNEL); + if (death == NULL) { + thread->return_error = BR_ERROR; + binder_debug(BINDER_DEBUG_FAILED_TRANSACTION, + "binder: %d:%d " + "BC_REQUEST_DEATH_NOTIFICATION failed\n", + proc->pid, thread->pid); + break; + } + binder_stats_created(BINDER_STAT_DEATH); + INIT_LIST_HEAD(&death->work.entry); + death->cookie = cookie; + ref->death = death; + if (ref->node->proc == NULL) { + ref->death->work.type = BINDER_WORK_DEAD_BINDER; + if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) { + list_add_tail(&ref->death->work.entry, &thread->todo); + } else { + list_add_tail(&ref->death->work.entry, &proc->todo); + wake_up_interruptible(&proc->wait); + } + } + } else { + if (ref->death == NULL) { + binder_user_error("binder: %d:%" + "d BC_CLEAR_DEATH_NOTIFI" + "CATION death notificat" + "ion not active\n", + proc->pid, thread->pid); + break; + } + death = ref->death; + if (death->cookie != cookie) { + binder_user_error("binder: %d:%" + "d BC_CLEAR_DEATH_NOTIFI" + "CATION death notificat" + "ion cookie mismatch " + "%p != %p\n", + proc->pid, thread->pid, + death->cookie, cookie); + break; + } + ref->death = NULL; + if (list_empty(&death->work.entry)) { + death->work.type = BINDER_WORK_CLEAR_DEATH_NOTIFICATION; + if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) { + list_add_tail(&death->work.entry, &thread->todo); + } else { + list_add_tail(&death->work.entry, &proc->todo); + wake_up_interruptible(&proc->wait); + } + } else { + BUG_ON(death->work.type != BINDER_WORK_DEAD_BINDER); + death->work.type = BINDER_WORK_DEAD_BINDER_AND_CLEAR; + } + } + } break; + case BC_DEAD_BINDER_DONE: { + struct binder_work *w; + void __user *cookie; + struct binder_ref_death *death = NULL; + if (get_user(cookie, (void __user * __user *)ptr)) + return -EFAULT; + + ptr += sizeof(void *); + list_for_each_entry(w, &proc->delivered_death, entry) { + struct binder_ref_death *tmp_death = container_of(w, struct binder_ref_death, work); + if (tmp_death->cookie == cookie) { + death = tmp_death; + break; + } + } + binder_debug(BINDER_DEBUG_DEAD_BINDER, + "binder: %d:%d BC_DEAD_BINDER_DONE %p found %p\n", + proc->pid, thread->pid, cookie, death); + if (death == NULL) { + binder_user_error("binder: %d:%d BC_DEAD" + "_BINDER_DONE %p not found\n", + proc->pid, thread->pid, cookie); + break; + } + + list_del_init(&death->work.entry); + if (death->work.type == BINDER_WORK_DEAD_BINDER_AND_CLEAR) { + death->work.type = BINDER_WORK_CLEAR_DEATH_NOTIFICATION; + if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) { + list_add_tail(&death->work.entry, &thread->todo); + } else { + list_add_tail(&death->work.entry, &proc->todo); + wake_up_interruptible(&proc->wait); + } + } + } break; + + default: + printk(KERN_ERR "binder: %d:%d unknown command %d\n", + proc->pid, thread->pid, cmd); + return -EINVAL; + } + *consumed = ptr - buffer; + } + return 0; +} + +void binder_stat_br(struct binder_proc *proc, struct binder_thread *thread, + uint32_t cmd) +{ + if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.br)) { + binder_stats.br[_IOC_NR(cmd)]++; + proc->stats.br[_IOC_NR(cmd)]++; + thread->stats.br[_IOC_NR(cmd)]++; + } +} + +static int binder_has_proc_work(struct binder_proc *proc, + struct binder_thread *thread) +{ + return !list_empty(&proc->todo) || + (thread->looper & BINDER_LOOPER_STATE_NEED_RETURN); +} + +static int binder_has_thread_work(struct binder_thread *thread) +{ + return !list_empty(&thread->todo) || thread->return_error != BR_OK || + (thread->looper & BINDER_LOOPER_STATE_NEED_RETURN); +} + +static int binder_thread_read(struct binder_proc *proc, + struct binder_thread *thread, + void __user *buffer, int size, + signed long *consumed, int non_block) +{ + void __user *ptr = buffer + *consumed; + void __user *end = buffer + size; + + int ret = 0; + int wait_for_proc_work; + + if (*consumed == 0) { + if (put_user(BR_NOOP, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + } + +retry: + wait_for_proc_work = thread->transaction_stack == NULL && + list_empty(&thread->todo); + + if (thread->return_error != BR_OK && ptr < end) { + if (thread->return_error2 != BR_OK) { + if (put_user(thread->return_error2, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + if (ptr == end) + goto done; + thread->return_error2 = BR_OK; + } + if (put_user(thread->return_error, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + thread->return_error = BR_OK; + goto done; + } + + + thread->looper |= BINDER_LOOPER_STATE_WAITING; + if (wait_for_proc_work) + proc->ready_threads++; + mutex_unlock(&binder_lock); + if (wait_for_proc_work) { + if (!(thread->looper & (BINDER_LOOPER_STATE_REGISTERED | + BINDER_LOOPER_STATE_ENTERED))) { + binder_user_error("binder: %d:%d ERROR: Thread waiting " + "for process work before calling BC_REGISTER_" + "LOOPER or BC_ENTER_LOOPER (state %x)\n", + proc->pid, thread->pid, thread->looper); + wait_event_interruptible(binder_user_error_wait, + binder_stop_on_user_error < 2); + } + binder_set_nice(proc->default_priority); + if (non_block) { + if (!binder_has_proc_work(proc, thread)) + ret = -EAGAIN; + } else + ret = wait_event_interruptible_exclusive(proc->wait, binder_has_proc_work(proc, thread)); + } else { + if (non_block) { + if (!binder_has_thread_work(thread)) + ret = -EAGAIN; + } else + ret = wait_event_interruptible(thread->wait, binder_has_thread_work(thread)); + } + mutex_lock(&binder_lock); + if (wait_for_proc_work) + proc->ready_threads--; + thread->looper &= ~BINDER_LOOPER_STATE_WAITING; + + if (ret) + return ret; + + while (1) { + uint32_t cmd; + struct binder_transaction_data tr; + struct binder_work *w; + struct binder_transaction *t = NULL; + + if (!list_empty(&thread->todo)) + w = list_first_entry(&thread->todo, struct binder_work, entry); + else if (!list_empty(&proc->todo) && wait_for_proc_work) + w = list_first_entry(&proc->todo, struct binder_work, entry); + else { + if (ptr - buffer == 4 && !(thread->looper & BINDER_LOOPER_STATE_NEED_RETURN)) /* no data added */ + goto retry; + break; + } + + if (end - ptr < sizeof(tr) + 4) + break; + + switch (w->type) { + case BINDER_WORK_TRANSACTION: { + t = container_of(w, struct binder_transaction, work); + } break; + case BINDER_WORK_TRANSACTION_COMPLETE: { + cmd = BR_TRANSACTION_COMPLETE; + if (put_user(cmd, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + + binder_stat_br(proc, thread, cmd); + binder_debug(BINDER_DEBUG_TRANSACTION_COMPLETE, + "binder: %d:%d BR_TRANSACTION_COMPLETE\n", + proc->pid, thread->pid); + + list_del(&w->entry); + kfree(w); + binder_stats_deleted(BINDER_STAT_TRANSACTION_COMPLETE); + } break; + case BINDER_WORK_NODE: { + struct binder_node *node = container_of(w, struct binder_node, work); + uint32_t cmd = BR_NOOP; + const char *cmd_name; + int strong = node->internal_strong_refs || node->local_strong_refs; + int weak = !hlist_empty(&node->refs) || node->local_weak_refs || strong; + if (weak && !node->has_weak_ref) { + cmd = BR_INCREFS; + cmd_name = "BR_INCREFS"; + node->has_weak_ref = 1; + node->pending_weak_ref = 1; + node->local_weak_refs++; + } else if (strong && !node->has_strong_ref) { + cmd = BR_ACQUIRE; + cmd_name = "BR_ACQUIRE"; + node->has_strong_ref = 1; + node->pending_strong_ref = 1; + node->local_strong_refs++; + } else if (!strong && node->has_strong_ref) { + cmd = BR_RELEASE; + cmd_name = "BR_RELEASE"; + node->has_strong_ref = 0; + } else if (!weak && node->has_weak_ref) { + cmd = BR_DECREFS; + cmd_name = "BR_DECREFS"; + node->has_weak_ref = 0; + } + if (cmd != BR_NOOP) { + if (put_user(cmd, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + if (put_user(node->ptr, (void * __user *)ptr)) + return -EFAULT; + ptr += sizeof(void *); + if (put_user(node->cookie, (void * __user *)ptr)) + return -EFAULT; + ptr += sizeof(void *); + + binder_stat_br(proc, thread, cmd); + binder_debug(BINDER_DEBUG_USER_REFS, + "binder: %d:%d %s %d u%p c%p\n", + proc->pid, thread->pid, cmd_name, node->debug_id, node->ptr, node->cookie); + } else { + list_del_init(&w->entry); + if (!weak && !strong) { + binder_debug(BINDER_DEBUG_INTERNAL_REFS, + "binder: %d:%d node %d u%p c%p deleted\n", + proc->pid, thread->pid, node->debug_id, + node->ptr, node->cookie); + rb_erase(&node->rb_node, &proc->nodes); + kfree(node); + binder_stats_deleted(BINDER_STAT_NODE); + } else { + binder_debug(BINDER_DEBUG_INTERNAL_REFS, + "binder: %d:%d node %d u%p c%p state unchanged\n", + proc->pid, thread->pid, node->debug_id, node->ptr, + node->cookie); + } + } + } break; + case BINDER_WORK_DEAD_BINDER: + case BINDER_WORK_DEAD_BINDER_AND_CLEAR: + case BINDER_WORK_CLEAR_DEATH_NOTIFICATION: { + struct binder_ref_death *death; + uint32_t cmd; + + death = container_of(w, struct binder_ref_death, work); + if (w->type == BINDER_WORK_CLEAR_DEATH_NOTIFICATION) + cmd = BR_CLEAR_DEATH_NOTIFICATION_DONE; + else + cmd = BR_DEAD_BINDER; + if (put_user(cmd, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + if (put_user(death->cookie, (void * __user *)ptr)) + return -EFAULT; + ptr += sizeof(void *); + binder_debug(BINDER_DEBUG_DEATH_NOTIFICATION, + "binder: %d:%d %s %p\n", + proc->pid, thread->pid, + cmd == BR_DEAD_BINDER ? + "BR_DEAD_BINDER" : + "BR_CLEAR_DEATH_NOTIFICATION_DONE", + death->cookie); + + if (w->type == BINDER_WORK_CLEAR_DEATH_NOTIFICATION) { + list_del(&w->entry); + kfree(death); + binder_stats_deleted(BINDER_STAT_DEATH); + } else + list_move(&w->entry, &proc->delivered_death); + if (cmd == BR_DEAD_BINDER) + goto done; /* DEAD_BINDER notifications can cause transactions */ + } break; + } + + if (!t) + continue; + + BUG_ON(t->buffer == NULL); + if (t->buffer->target_node) { + struct binder_node *target_node = t->buffer->target_node; + tr.target.ptr = target_node->ptr; + tr.cookie = target_node->cookie; + t->saved_priority = task_nice(current); + if (t->priority < target_node->min_priority && + !(t->flags & TF_ONE_WAY)) + binder_set_nice(t->priority); + else if (!(t->flags & TF_ONE_WAY) || + t->saved_priority > target_node->min_priority) + binder_set_nice(target_node->min_priority); + cmd = BR_TRANSACTION; + } else { + tr.target.ptr = NULL; + tr.cookie = NULL; + cmd = BR_REPLY; + } + tr.code = t->code; + tr.flags = t->flags; + tr.sender_euid = t->sender_euid; + + if (t->from) { + struct task_struct *sender = t->from->proc->tsk; + tr.sender_pid = task_tgid_nr_ns(sender, + current->nsproxy->pid_ns); + } else { + tr.sender_pid = 0; + } + + tr.data_size = t->buffer->data_size; + tr.offsets_size = t->buffer->offsets_size; + tr.data.ptr.buffer = (void *)t->buffer->data + + proc->user_buffer_offset; + tr.data.ptr.offsets = tr.data.ptr.buffer + + ALIGN(t->buffer->data_size, + sizeof(void *)); + + if (put_user(cmd, (uint32_t __user *)ptr)) + return -EFAULT; + ptr += sizeof(uint32_t); + if (copy_to_user(ptr, &tr, sizeof(tr))) + return -EFAULT; + ptr += sizeof(tr); + + binder_stat_br(proc, thread, cmd); + binder_debug(BINDER_DEBUG_TRANSACTION, + "binder: %d:%d %s %d %d:%d, cmd %d" + "size %zd-%zd ptr %p-%p\n", + proc->pid, thread->pid, + (cmd == BR_TRANSACTION) ? "BR_TRANSACTION" : + "BR_REPLY", + t->debug_id, t->from ? t->from->proc->pid : 0, + t->from ? t->from->pid : 0, cmd, + t->buffer->data_size, t->buffer->offsets_size, + tr.data.ptr.buffer, tr.data.ptr.offsets); + + list_del(&t->work.entry); + t->buffer->allow_user_free = 1; + if (cmd == BR_TRANSACTION && !(t->flags & TF_ONE_WAY)) { + t->to_parent = thread->transaction_stack; + t->to_thread = thread; + thread->transaction_stack = t; + } else { + t->buffer->transaction = NULL; + kfree(t); + binder_stats_deleted(BINDER_STAT_TRANSACTION); + } + break; + } + +done: + + *consumed = ptr - buffer; + if (proc->requested_threads + proc->ready_threads == 0 && + proc->requested_threads_started < proc->max_threads && + (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | + BINDER_LOOPER_STATE_ENTERED)) /* the user-space code fails to */ + /*spawn a new thread if we leave this out */) { + proc->requested_threads++; + binder_debug(BINDER_DEBUG_THREADS, + "binder: %d:%d BR_SPAWN_LOOPER\n", + proc->pid, thread->pid); + if (put_user(BR_SPAWN_LOOPER, (uint32_t __user *)buffer)) + return -EFAULT; + } + return 0; +} + +static void binder_release_work(struct list_head *list) +{ + struct binder_work *w; + while (!list_empty(list)) { + w = list_first_entry(list, struct binder_work, entry); + list_del_init(&w->entry); + switch (w->type) { + case BINDER_WORK_TRANSACTION: { + struct binder_transaction *t; + + t = container_of(w, struct binder_transaction, work); + if (t->buffer->target_node && !(t->flags & TF_ONE_WAY)) + binder_send_failed_reply(t, BR_DEAD_REPLY); + } break; + case BINDER_WORK_TRANSACTION_COMPLETE: { + kfree(w); + binder_stats_deleted(BINDER_STAT_TRANSACTION_COMPLETE); + } break; + default: + break; + } + } + +} + +static struct binder_thread *binder_get_thread(struct binder_proc *proc) +{ + struct binder_thread *thread = NULL; + struct rb_node *parent = NULL; + struct rb_node **p = &proc->threads.rb_node; + + while (*p) { + parent = *p; + thread = rb_entry(parent, struct binder_thread, rb_node); + + if (current->pid < thread->pid) + p = &(*p)->rb_left; + else if (current->pid > thread->pid) + p = &(*p)->rb_right; + else + break; + } + if (*p == NULL) { + thread = kzalloc(sizeof(*thread), GFP_KERNEL); + if (thread == NULL) + return NULL; + binder_stats_created(BINDER_STAT_THREAD); + thread->proc = proc; + thread->pid = current->pid; + init_waitqueue_head(&thread->wait); + INIT_LIST_HEAD(&thread->todo); + rb_link_node(&thread->rb_node, parent, p); + rb_insert_color(&thread->rb_node, &proc->threads); + thread->looper |= BINDER_LOOPER_STATE_NEED_RETURN; + thread->return_error = BR_OK; + thread->return_error2 = BR_OK; + } + return thread; +} + +static int binder_free_thread(struct binder_proc *proc, + struct binder_thread *thread) +{ + struct binder_transaction *t; + struct binder_transaction *send_reply = NULL; + int active_transactions = 0; + + rb_erase(&thread->rb_node, &proc->threads); + t = thread->transaction_stack; + if (t && t->to_thread == thread) + send_reply = t; + while (t) { + active_transactions++; + binder_debug(BINDER_DEBUG_DEAD_TRANSACTION, + "binder: release %d:%d transaction %d " + "%s, still active\n", proc->pid, thread->pid, + t->debug_id, + (t->to_thread == thread) ? "in" : "out"); + + if (t->to_thread == thread) { + t->to_proc = NULL; + t->to_thread = NULL; + if (t->buffer) { + t->buffer->transaction = NULL; + t->buffer = NULL; + } + t = t->to_parent; + } else if (t->from == thread) { + t->from = NULL; + t = t->from_parent; + } else + BUG(); + } + if (send_reply) + binder_send_failed_reply(send_reply, BR_DEAD_REPLY); + binder_release_work(&thread->todo); + kfree(thread); + binder_stats_deleted(BINDER_STAT_THREAD); + return active_transactions; +} + +static unsigned int binder_poll(struct file *filp, + struct poll_table_struct *wait) +{ + struct binder_proc *proc = filp->private_data; + struct binder_thread *thread = NULL; + int wait_for_proc_work; + + mutex_lock(&binder_lock); + thread = binder_get_thread(proc); + + wait_for_proc_work = thread->transaction_stack == NULL && + list_empty(&thread->todo) && thread->return_error == BR_OK; + mutex_unlock(&binder_lock); + + if (wait_for_proc_work) { + if (binder_has_proc_work(proc, thread)) + return POLLIN; + poll_wait(filp, &proc->wait, wait); + if (binder_has_proc_work(proc, thread)) + return POLLIN; + } else { + if (binder_has_thread_work(thread)) + return POLLIN; + poll_wait(filp, &thread->wait, wait); + if (binder_has_thread_work(thread)) + return POLLIN; + } + return 0; +} + +static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + int ret; + struct binder_proc *proc = filp->private_data; + struct binder_thread *thread; + unsigned int size = _IOC_SIZE(cmd); + void __user *ubuf = (void __user *)arg; + + /*printk(KERN_INFO "binder_ioctl: %d:%d %x %lx\n", proc->pid, current->pid, cmd, arg);*/ + + ret = wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2); + if (ret) + return ret; + + mutex_lock(&binder_lock); + thread = binder_get_thread(proc); + if (thread == NULL) { + ret = -ENOMEM; + goto err; + } + + switch (cmd) { + case BINDER_WRITE_READ: { + struct binder_write_read bwr; + if (size != sizeof(struct binder_write_read)) { + ret = -EINVAL; + goto err; + } + if (copy_from_user(&bwr, ubuf, sizeof(bwr))) { + ret = -EFAULT; + goto err; + } + binder_debug(BINDER_DEBUG_READ_WRITE, + "binder: %d:%d write %ld at %08lx, read %ld at %08lx\n", + proc->pid, thread->pid, bwr.write_size, bwr.write_buffer, + bwr.read_size, bwr.read_buffer); + + if (bwr.write_size > 0) { + ret = binder_thread_write(proc, thread, (void __user *)bwr.write_buffer, bwr.write_size, &bwr.write_consumed); + if (ret < 0) { + bwr.read_consumed = 0; + if (copy_to_user(ubuf, &bwr, sizeof(bwr))) + ret = -EFAULT; + goto err; + } + } + if (bwr.read_size > 0) { + ret = binder_thread_read(proc, thread, (void __user *)bwr.read_buffer, bwr.read_size, &bwr.read_consumed, filp->f_flags & O_NONBLOCK); + if (!list_empty(&proc->todo)) + wake_up_interruptible(&proc->wait); + if (ret < 0) { + if (copy_to_user(ubuf, &bwr, sizeof(bwr))) + ret = -EFAULT; + goto err; + } + } + binder_debug(BINDER_DEBUG_READ_WRITE, + "binder: %d:%d wrote %ld of %ld, read return %ld of %ld\n", + proc->pid, thread->pid, bwr.write_consumed, bwr.write_size, + bwr.read_consumed, bwr.read_size); + if (copy_to_user(ubuf, &bwr, sizeof(bwr))) { + ret = -EFAULT; + goto err; + } + break; + } + case BINDER_SET_MAX_THREADS: + if (copy_from_user(&proc->max_threads, ubuf, sizeof(proc->max_threads))) { + ret = -EINVAL; + goto err; + } + break; + case BINDER_SET_CONTEXT_MGR: + if (binder_context_mgr_node != NULL) { + printk(KERN_ERR "binder: BINDER_SET_CONTEXT_MGR already set\n"); + ret = -EBUSY; + goto err; + } + if (binder_context_mgr_uid != -1) { + if (binder_context_mgr_uid != current->cred->euid) { + printk(KERN_ERR "binder: BINDER_SET_" + "CONTEXT_MGR bad uid %d != %d\n", + current->cred->euid, + binder_context_mgr_uid); + ret = -EPERM; + goto err; + } + } else + binder_context_mgr_uid = current->cred->euid; + binder_context_mgr_node = binder_new_node(proc, NULL, NULL); + if (binder_context_mgr_node == NULL) { + ret = -ENOMEM; + goto err; + } + binder_context_mgr_node->local_weak_refs++; + binder_context_mgr_node->local_strong_refs++; + binder_context_mgr_node->has_strong_ref = 1; + binder_context_mgr_node->has_weak_ref = 1; + break; + case BINDER_THREAD_EXIT: + binder_debug(BINDER_DEBUG_THREADS, "binder: %d:%d exit\n", + proc->pid, thread->pid); + binder_free_thread(proc, thread); + thread = NULL; + break; + case BINDER_VERSION: + if (size != sizeof(struct binder_version)) { + ret = -EINVAL; + goto err; + } + if (put_user(BINDER_CURRENT_PROTOCOL_VERSION, &((struct binder_version *)ubuf)->protocol_version)) { + ret = -EINVAL; + goto err; + } + break; + default: + ret = -EINVAL; + goto err; + } + ret = 0; +err: + if (thread) + thread->looper &= ~BINDER_LOOPER_STATE_NEED_RETURN; + mutex_unlock(&binder_lock); + wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2); + if (ret && ret != -ERESTARTSYS) + printk(KERN_INFO "binder: %d:%d ioctl %x %lx returned %d\n", proc->pid, current->pid, cmd, arg, ret); + return ret; +} + +static void binder_vma_open(struct vm_area_struct *vma) +{ + struct binder_proc *proc = vma->vm_private_data; + binder_debug(BINDER_DEBUG_OPEN_CLOSE, + "binder: %d open vm area %lx-%lx (%ld K) vma %lx pagep %lx\n", + proc->pid, vma->vm_start, vma->vm_end, + (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, + (unsigned long)pgprot_val(vma->vm_page_prot)); + dump_stack(); +} + +static void binder_vma_close(struct vm_area_struct *vma) +{ + struct binder_proc *proc = vma->vm_private_data; + binder_debug(BINDER_DEBUG_OPEN_CLOSE, + "binder: %d close vm area %lx-%lx (%ld K) vma %lx pagep %lx\n", + proc->pid, vma->vm_start, vma->vm_end, + (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, + (unsigned long)pgprot_val(vma->vm_page_prot)); + proc->vma = NULL; + binder_defer_work(proc, BINDER_DEFERRED_PUT_FILES); +} + +static struct vm_operations_struct binder_vm_ops = { + .open = binder_vma_open, + .close = binder_vma_close, +}; + +static int binder_mmap(struct file *filp, struct vm_area_struct *vma) +{ + int ret; + struct vm_struct *area; + struct binder_proc *proc = filp->private_data; + const char *failure_string; + struct binder_buffer *buffer; + + if ((vma->vm_end - vma->vm_start) > SZ_4M) + vma->vm_end = vma->vm_start + SZ_4M; + + binder_debug(BINDER_DEBUG_OPEN_CLOSE, + "binder_mmap: %d %lx-%lx (%ld K) vma %lx pagep %lx\n", + proc->pid, vma->vm_start, vma->vm_end, + (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, + (unsigned long)pgprot_val(vma->vm_page_prot)); + + if (vma->vm_flags & FORBIDDEN_MMAP_FLAGS) { + ret = -EPERM; + failure_string = "bad vm_flags"; + goto err_bad_arg; + } + vma->vm_flags = (vma->vm_flags | VM_DONTCOPY) & ~VM_MAYWRITE; + + if (proc->buffer) { + ret = -EBUSY; + failure_string = "already mapped"; + goto err_already_mapped; + } + + area = get_vm_area(vma->vm_end - vma->vm_start, VM_IOREMAP); + if (area == NULL) { + ret = -ENOMEM; + failure_string = "get_vm_area"; + goto err_get_vm_area_failed; + } + proc->buffer = area->addr; + proc->user_buffer_offset = vma->vm_start - (uintptr_t)proc->buffer; + +#ifdef CONFIG_CPU_CACHE_VIPT + if (cache_is_vipt_aliasing()) { + while (CACHE_COLOUR((vma->vm_start ^ (uint32_t)proc->buffer))) { + printk(KERN_INFO "binder_mmap: %d %lx-%lx maps %p bad alignment\n", proc->pid, vma->vm_start, vma->vm_end, proc->buffer); + vma->vm_start += PAGE_SIZE; + } + } +#endif + proc->pages = kzalloc(sizeof(proc->pages[0]) * ((vma->vm_end - vma->vm_start) / PAGE_SIZE), GFP_KERNEL); + if (proc->pages == NULL) { + ret = -ENOMEM; + failure_string = "alloc page array"; + goto err_alloc_pages_failed; + } + proc->buffer_size = vma->vm_end - vma->vm_start; + + vma->vm_ops = &binder_vm_ops; + vma->vm_private_data = proc; + + if (binder_update_page_range(proc, 1, proc->buffer, proc->buffer + PAGE_SIZE, vma)) { + ret = -ENOMEM; + failure_string = "alloc small buf"; + goto err_alloc_small_buf_failed; + } + buffer = proc->buffer; + INIT_LIST_HEAD(&proc->buffers); + list_add(&buffer->entry, &proc->buffers); + buffer->free = 1; + binder_insert_free_buffer(proc, buffer); + proc->free_async_space = proc->buffer_size / 2; + barrier(); + proc->files = get_files_struct(current); + proc->vma = vma; + + /*printk(KERN_INFO "binder_mmap: %d %lx-%lx maps %p\n", + proc->pid, vma->vm_start, vma->vm_end, proc->buffer);*/ + return 0; + +err_alloc_small_buf_failed: + kfree(proc->pages); + proc->pages = NULL; +err_alloc_pages_failed: + vfree(proc->buffer); + proc->buffer = NULL; +err_get_vm_area_failed: +err_already_mapped: +err_bad_arg: + printk(KERN_ERR "binder_mmap: %d %lx-%lx %s failed %d\n", + proc->pid, vma->vm_start, vma->vm_end, failure_string, ret); + return ret; +} + +static int binder_open(struct inode *nodp, struct file *filp) +{ + struct binder_proc *proc; + + binder_debug(BINDER_DEBUG_OPEN_CLOSE, "binder_open: %d:%d\n", + current->group_leader->pid, current->pid); + + proc = kzalloc(sizeof(*proc), GFP_KERNEL); + if (proc == NULL) + return -ENOMEM; + get_task_struct(current); + proc->tsk = current; + INIT_LIST_HEAD(&proc->todo); + init_waitqueue_head(&proc->wait); + proc->default_priority = task_nice(current); + mutex_lock(&binder_lock); + binder_stats_created(BINDER_STAT_PROC); + hlist_add_head(&proc->proc_node, &binder_procs); + proc->pid = current->group_leader->pid; + INIT_LIST_HEAD(&proc->delivered_death); + filp->private_data = proc; + mutex_unlock(&binder_lock); + + if (binder_debugfs_dir_entry_proc) { + char strbuf[11]; + snprintf(strbuf, sizeof(strbuf), "%u", proc->pid); + proc->debugfs_entry = debugfs_create_file(strbuf, S_IRUGO, + binder_debugfs_dir_entry_proc, proc, &binder_proc_fops); + } + + return 0; +} + +static int binder_flush(struct file *filp, fl_owner_t id) +{ + struct binder_proc *proc = filp->private_data; + + binder_defer_work(proc, BINDER_DEFERRED_FLUSH); + + return 0; +} + +static void binder_deferred_flush(struct binder_proc *proc) +{ + struct rb_node *n; + int wake_count = 0; + for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n)) { + struct binder_thread *thread = rb_entry(n, struct binder_thread, rb_node); + thread->looper |= BINDER_LOOPER_STATE_NEED_RETURN; + if (thread->looper & BINDER_LOOPER_STATE_WAITING) { + wake_up_interruptible(&thread->wait); + wake_count++; + } + } + wake_up_interruptible_all(&proc->wait); + + binder_debug(BINDER_DEBUG_OPEN_CLOSE, + "binder_flush: %d woke %d threads\n", proc->pid, + wake_count); +} + +static int binder_release(struct inode *nodp, struct file *filp) +{ + struct binder_proc *proc = filp->private_data; + debugfs_remove(proc->debugfs_entry); + binder_defer_work(proc, BINDER_DEFERRED_RELEASE); + + return 0; +} + +static void binder_deferred_release(struct binder_proc *proc) +{ + struct hlist_node *pos; + struct binder_transaction *t; + struct rb_node *n; + int threads, nodes, incoming_refs, outgoing_refs, buffers, active_transactions, page_count; + + BUG_ON(proc->vma); + BUG_ON(proc->files); + + hlist_del(&proc->proc_node); + if (binder_context_mgr_node && binder_context_mgr_node->proc == proc) { + binder_debug(BINDER_DEBUG_DEAD_BINDER, + "binder_release: %d context_mgr_node gone\n", + proc->pid); + binder_context_mgr_node = NULL; + } + + threads = 0; + active_transactions = 0; + while ((n = rb_first(&proc->threads))) { + struct binder_thread *thread = rb_entry(n, struct binder_thread, rb_node); + threads++; + active_transactions += binder_free_thread(proc, thread); + } + nodes = 0; + incoming_refs = 0; + while ((n = rb_first(&proc->nodes))) { + struct binder_node *node = rb_entry(n, struct binder_node, rb_node); + + nodes++; + rb_erase(&node->rb_node, &proc->nodes); + list_del_init(&node->work.entry); + if (hlist_empty(&node->refs)) { + kfree(node); + binder_stats_deleted(BINDER_STAT_NODE); + } else { + struct binder_ref *ref; + int death = 0; + + node->proc = NULL; + node->local_strong_refs = 0; + node->local_weak_refs = 0; + hlist_add_head(&node->dead_node, &binder_dead_nodes); + + hlist_for_each_entry(ref, pos, &node->refs, node_entry) { + incoming_refs++; + if (ref->death) { + death++; + if (list_empty(&ref->death->work.entry)) { + ref->death->work.type = BINDER_WORK_DEAD_BINDER; + list_add_tail(&ref->death->work.entry, &ref->proc->todo); + wake_up_interruptible(&ref->proc->wait); + } else + BUG(); + } + } + binder_debug(BINDER_DEBUG_DEAD_BINDER, + "binder: node %d now dead, " + "refs %d, death %d\n", node->debug_id, + incoming_refs, death); + } + } + outgoing_refs = 0; + while ((n = rb_first(&proc->refs_by_desc))) { + struct binder_ref *ref = rb_entry(n, struct binder_ref, + rb_node_desc); + outgoing_refs++; + binder_delete_ref(ref); + } + binder_release_work(&proc->todo); + buffers = 0; + + while ((n = rb_first(&proc->allocated_buffers))) { + struct binder_buffer *buffer = rb_entry(n, struct binder_buffer, + rb_node); + t = buffer->transaction; + if (t) { + t->buffer = NULL; + buffer->transaction = NULL; + printk(KERN_ERR "binder: release proc %d, " + "transaction %d, not freed\n", + proc->pid, t->debug_id); + /*BUG();*/ + } + binder_free_buf(proc, buffer); + buffers++; + } + + binder_stats_deleted(BINDER_STAT_PROC); + + page_count = 0; + if (proc->pages) { + int i; + for (i = 0; i < proc->buffer_size / PAGE_SIZE; i++) { + if (proc->pages[i]) { + void *page_addr = proc->buffer + i * PAGE_SIZE; + binder_debug(BINDER_DEBUG_BUFFER_ALLOC, + "binder_release: %d: " + "page %d at %p not freed\n", + proc->pid, i, + page_addr); + unmap_kernel_range((unsigned long)page_addr, + PAGE_SIZE); + __free_page(proc->pages[i]); + page_count++; + } + } + kfree(proc->pages); + vfree(proc->buffer); + } + + put_task_struct(proc->tsk); + + binder_debug(BINDER_DEBUG_OPEN_CLOSE, + "binder_release: %d threads %d, nodes %d (ref %d), " + "refs %d, active transactions %d, buffers %d, " + "pages %d\n", + proc->pid, threads, nodes, incoming_refs, outgoing_refs, + active_transactions, buffers, page_count); + + kfree(proc); +} + +static void binder_deferred_func(struct work_struct *work) +{ + struct binder_proc *proc; + struct files_struct *files; + + int defer; + do { + mutex_lock(&binder_lock); + mutex_lock(&binder_deferred_lock); + if (!hlist_empty(&binder_deferred_list)) { + proc = hlist_entry(binder_deferred_list.first, + struct binder_proc, deferred_work_node); + hlist_del_init(&proc->deferred_work_node); + defer = proc->deferred_work; + proc->deferred_work = 0; + } else { + proc = NULL; + defer = 0; + } + mutex_unlock(&binder_deferred_lock); + + files = NULL; + if (defer & BINDER_DEFERRED_PUT_FILES) { + files = proc->files; + if (files) + proc->files = NULL; + } + + if (defer & BINDER_DEFERRED_FLUSH) + binder_deferred_flush(proc); + + if (defer & BINDER_DEFERRED_RELEASE) + binder_deferred_release(proc); /* frees proc */ + + mutex_unlock(&binder_lock); + if (files) + put_files_struct(files); + } while (proc); +} +static DECLARE_WORK(binder_deferred_work, binder_deferred_func); + +static void +binder_defer_work(struct binder_proc *proc, enum binder_deferred_state defer) +{ + mutex_lock(&binder_deferred_lock); + proc->deferred_work |= defer; + if (hlist_unhashed(&proc->deferred_work_node)) { + hlist_add_head(&proc->deferred_work_node, + &binder_deferred_list); + queue_work(binder_deferred_workqueue, &binder_deferred_work); + } + mutex_unlock(&binder_deferred_lock); +} + +static void print_binder_transaction(struct seq_file *m, const char *prefix, + struct binder_transaction *t) +{ + seq_printf(m, + "%s %d: %p from %d:%d to %d:%d code %x flags %x pri %ld r%d", + prefix, t->debug_id, t, + t->from ? t->from->proc->pid : 0, + t->from ? t->from->pid : 0, + t->to_proc ? t->to_proc->pid : 0, + t->to_thread ? t->to_thread->pid : 0, + t->code, t->flags, t->priority, t->need_reply); + if (t->buffer == NULL) { + seq_puts(m, " buffer free\n"); + return; + } + if (t->buffer->target_node) + seq_printf(m, " node %d", + t->buffer->target_node->debug_id); + seq_printf(m, " size %zd:%zd data %p\n", + t->buffer->data_size, t->buffer->offsets_size, + t->buffer->data); +} + +static void print_binder_buffer(struct seq_file *m, const char *prefix, + struct binder_buffer *buffer) +{ + seq_printf(m, "%s %d: %p size %zd:%zd %s\n", + prefix, buffer->debug_id, buffer->data, + buffer->data_size, buffer->offsets_size, + buffer->transaction ? "active" : "delivered"); +} + +static void print_binder_work(struct seq_file *m, const char *prefix, + const char *transaction_prefix, + struct binder_work *w) +{ + struct binder_node *node; + struct binder_transaction *t; + + switch (w->type) { + case BINDER_WORK_TRANSACTION: + t = container_of(w, struct binder_transaction, work); + print_binder_transaction(m, transaction_prefix, t); + break; + case BINDER_WORK_TRANSACTION_COMPLETE: + seq_printf(m, "%stransaction complete\n", prefix); + break; + case BINDER_WORK_NODE: + node = container_of(w, struct binder_node, work); + seq_printf(m, "%snode work %d: u%p c%p\n", + prefix, node->debug_id, node->ptr, node->cookie); + break; + case BINDER_WORK_DEAD_BINDER: + seq_printf(m, "%shas dead binder\n", prefix); + break; + case BINDER_WORK_DEAD_BINDER_AND_CLEAR: + seq_printf(m, "%shas cleared dead binder\n", prefix); + break; + case BINDER_WORK_CLEAR_DEATH_NOTIFICATION: + seq_printf(m, "%shas cleared death notification\n", prefix); + break; + default: + seq_printf(m, "%sunknown work: type %d\n", prefix, w->type); + break; + } +} + +static void print_binder_thread(struct seq_file *m, + struct binder_thread *thread, + int print_always) +{ + struct binder_transaction *t; + struct binder_work *w; + size_t start_pos = m->count; + size_t header_pos; + + seq_printf(m, " thread %d: l %02x\n", thread->pid, thread->looper); + header_pos = m->count; + t = thread->transaction_stack; + while (t) { + if (t->from == thread) { + print_binder_transaction(m, + " outgoing transaction", t); + t = t->from_parent; + } else if (t->to_thread == thread) { + print_binder_transaction(m, + " incoming transaction", t); + t = t->to_parent; + } else { + print_binder_transaction(m, " bad transaction", t); + t = NULL; + } + } + list_for_each_entry(w, &thread->todo, entry) { + print_binder_work(m, " ", " pending transaction", w); + } + if (!print_always && m->count == header_pos) + m->count = start_pos; +} + +static void print_binder_node(struct seq_file *m, struct binder_node *node) +{ + struct binder_ref *ref; + struct hlist_node *pos; + struct binder_work *w; + int count; + + count = 0; + hlist_for_each_entry(ref, pos, &node->refs, node_entry) + count++; + + seq_printf(m, " node %d: u%p c%p hs %d hw %d ls %d lw %d is %d iw %d", + node->debug_id, node->ptr, node->cookie, + node->has_strong_ref, node->has_weak_ref, + node->local_strong_refs, node->local_weak_refs, + node->internal_strong_refs, count); + if (count) { + seq_puts(m, " proc"); + hlist_for_each_entry(ref, pos, &node->refs, node_entry) + seq_printf(m, " %d", ref->proc->pid); + } + seq_puts(m, "\n"); + list_for_each_entry(w, &node->async_todo, entry) + print_binder_work(m, " ", + " pending async transaction", w); +} + +static void print_binder_ref(struct seq_file *m, struct binder_ref *ref) +{ + seq_printf(m, " ref %d: desc %d %snode %d s %d w %d d %p\n", + ref->debug_id, ref->desc, ref->node->proc ? "" : "dead ", + ref->node->debug_id, ref->strong, ref->weak, ref->death); +} + +static void print_binder_proc(struct seq_file *m, + struct binder_proc *proc, int print_all) +{ + struct binder_work *w; + struct rb_node *n; + size_t start_pos = m->count; + size_t header_pos; + + seq_printf(m, "proc %d\n", proc->pid); + header_pos = m->count; + + for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n)) + print_binder_thread(m, rb_entry(n, struct binder_thread, + rb_node), print_all); + for (n = rb_first(&proc->nodes); n != NULL; n = rb_next(n)) { + struct binder_node *node = rb_entry(n, struct binder_node, + rb_node); + if (print_all || node->has_async_transaction) + print_binder_node(m, node); + } + if (print_all) { + for (n = rb_first(&proc->refs_by_desc); + n != NULL; + n = rb_next(n)) + print_binder_ref(m, rb_entry(n, struct binder_ref, + rb_node_desc)); + } + for (n = rb_first(&proc->allocated_buffers); n != NULL; n = rb_next(n)) + print_binder_buffer(m, " buffer", + rb_entry(n, struct binder_buffer, rb_node)); + list_for_each_entry(w, &proc->todo, entry) + print_binder_work(m, " ", " pending transaction", w); + list_for_each_entry(w, &proc->delivered_death, entry) { + seq_puts(m, " has delivered dead binder\n"); + break; + } + if (!print_all && m->count == header_pos) + m->count = start_pos; +} + +static const char *binder_return_strings[] = { + "BR_ERROR", + "BR_OK", + "BR_TRANSACTION", + "BR_REPLY", + "BR_ACQUIRE_RESULT", + "BR_DEAD_REPLY", + "BR_TRANSACTION_COMPLETE", + "BR_INCREFS", + "BR_ACQUIRE", + "BR_RELEASE", + "BR_DECREFS", + "BR_ATTEMPT_ACQUIRE", + "BR_NOOP", + "BR_SPAWN_LOOPER", + "BR_FINISHED", + "BR_DEAD_BINDER", + "BR_CLEAR_DEATH_NOTIFICATION_DONE", + "BR_FAILED_REPLY" +}; + +static const char *binder_command_strings[] = { + "BC_TRANSACTION", + "BC_REPLY", + "BC_ACQUIRE_RESULT", + "BC_FREE_BUFFER", + "BC_INCREFS", + "BC_ACQUIRE", + "BC_RELEASE", + "BC_DECREFS", + "BC_INCREFS_DONE", + "BC_ACQUIRE_DONE", + "BC_ATTEMPT_ACQUIRE", + "BC_REGISTER_LOOPER", + "BC_ENTER_LOOPER", + "BC_EXIT_LOOPER", + "BC_REQUEST_DEATH_NOTIFICATION", + "BC_CLEAR_DEATH_NOTIFICATION", + "BC_DEAD_BINDER_DONE" +}; + +static const char *binder_objstat_strings[] = { + "proc", + "thread", + "node", + "ref", + "death", + "transaction", + "transaction_complete" +}; + +static void print_binder_stats(struct seq_file *m, const char *prefix, + struct binder_stats *stats) +{ + int i; + + BUILD_BUG_ON(ARRAY_SIZE(stats->bc) != + ARRAY_SIZE(binder_command_strings)); + for (i = 0; i < ARRAY_SIZE(stats->bc); i++) { + if (stats->bc[i]) + seq_printf(m, "%s%s: %d\n", prefix, + binder_command_strings[i], stats->bc[i]); + } + + BUILD_BUG_ON(ARRAY_SIZE(stats->br) != + ARRAY_SIZE(binder_return_strings)); + for (i = 0; i < ARRAY_SIZE(stats->br); i++) { + if (stats->br[i]) + seq_printf(m, "%s%s: %d\n", prefix, + binder_return_strings[i], stats->br[i]); + } + + BUILD_BUG_ON(ARRAY_SIZE(stats->obj_created) != + ARRAY_SIZE(binder_objstat_strings)); + BUILD_BUG_ON(ARRAY_SIZE(stats->obj_created) != + ARRAY_SIZE(stats->obj_deleted)); + for (i = 0; i < ARRAY_SIZE(stats->obj_created); i++) { + if (stats->obj_created[i] || stats->obj_deleted[i]) + seq_printf(m, "%s%s: active %d total %d\n", prefix, + binder_objstat_strings[i], + stats->obj_created[i] - stats->obj_deleted[i], + stats->obj_created[i]); + } +} + +static void print_binder_proc_stats(struct seq_file *m, + struct binder_proc *proc) +{ + struct binder_work *w; + struct rb_node *n; + int count, strong, weak; + + seq_printf(m, "proc %d\n", proc->pid); + count = 0; + for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n)) + count++; + seq_printf(m, " threads: %d\n", count); + seq_printf(m, " requested threads: %d+%d/%d\n" + " ready threads %d\n" + " free async space %zd\n", proc->requested_threads, + proc->requested_threads_started, proc->max_threads, + proc->ready_threads, proc->free_async_space); + count = 0; + for (n = rb_first(&proc->nodes); n != NULL; n = rb_next(n)) + count++; + seq_printf(m, " nodes: %d\n", count); + count = 0; + strong = 0; + weak = 0; + for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) { + struct binder_ref *ref = rb_entry(n, struct binder_ref, + rb_node_desc); + count++; + strong += ref->strong; + weak += ref->weak; + } + seq_printf(m, " refs: %d s %d w %d\n", count, strong, weak); + + count = 0; + for (n = rb_first(&proc->allocated_buffers); n != NULL; n = rb_next(n)) + count++; + seq_printf(m, " buffers: %d\n", count); + + count = 0; + list_for_each_entry(w, &proc->todo, entry) { + switch (w->type) { + case BINDER_WORK_TRANSACTION: + count++; + break; + default: + break; + } + } + seq_printf(m, " pending transactions: %d\n", count); + + print_binder_stats(m, " ", &proc->stats); +} + + +static int binder_state_show(struct seq_file *m, void *unused) +{ + struct binder_proc *proc; + struct hlist_node *pos; + struct binder_node *node; + int do_lock = !binder_debug_no_lock; + + if (do_lock) + mutex_lock(&binder_lock); + + seq_puts(m, "binder state:\n"); + + if (!hlist_empty(&binder_dead_nodes)) + seq_puts(m, "dead nodes:\n"); + hlist_for_each_entry(node, pos, &binder_dead_nodes, dead_node) + print_binder_node(m, node); + + hlist_for_each_entry(proc, pos, &binder_procs, proc_node) + print_binder_proc(m, proc, 1); + if (do_lock) + mutex_unlock(&binder_lock); + return 0; +} + +static int binder_stats_show(struct seq_file *m, void *unused) +{ + struct binder_proc *proc; + struct hlist_node *pos; + int do_lock = !binder_debug_no_lock; + + if (do_lock) + mutex_lock(&binder_lock); + + seq_puts(m, "binder stats:\n"); + + print_binder_stats(m, "", &binder_stats); + + hlist_for_each_entry(proc, pos, &binder_procs, proc_node) + print_binder_proc_stats(m, proc); + if (do_lock) + mutex_unlock(&binder_lock); + return 0; +} + +static int binder_transactions_show(struct seq_file *m, void *unused) +{ + struct binder_proc *proc; + struct hlist_node *pos; + int do_lock = !binder_debug_no_lock; + + if (do_lock) + mutex_lock(&binder_lock); + + seq_puts(m, "binder transactions:\n"); + hlist_for_each_entry(proc, pos, &binder_procs, proc_node) + print_binder_proc(m, proc, 0); + if (do_lock) + mutex_unlock(&binder_lock); + return 0; +} + +static int binder_proc_show(struct seq_file *m, void *unused) +{ + struct binder_proc *proc = m->private; + int do_lock = !binder_debug_no_lock; + + if (do_lock) + mutex_lock(&binder_lock); + seq_puts(m, "binder proc state:\n"); + print_binder_proc(m, proc, 1); + if (do_lock) + mutex_unlock(&binder_lock); + return 0; +} + +static void print_binder_transaction_log_entry(struct seq_file *m, + struct binder_transaction_log_entry *e) +{ + seq_printf(m, + "%d: %s from %d:%d to %d:%d node %d handle %d size %d:%d\n", + e->debug_id, (e->call_type == 2) ? "reply" : + ((e->call_type == 1) ? "async" : "call "), e->from_proc, + e->from_thread, e->to_proc, e->to_thread, e->to_node, + e->target_handle, e->data_size, e->offsets_size); +} + +static int binder_transaction_log_show(struct seq_file *m, void *unused) +{ + struct binder_transaction_log *log = m->private; + int i; + + if (log->full) { + for (i = log->next; i < ARRAY_SIZE(log->entry); i++) + print_binder_transaction_log_entry(m, &log->entry[i]); + } + for (i = 0; i < log->next; i++) + print_binder_transaction_log_entry(m, &log->entry[i]); + return 0; +} + +static const struct file_operations binder_fops = { + .owner = THIS_MODULE, + .poll = binder_poll, + .unlocked_ioctl = binder_ioctl, + .mmap = binder_mmap, + .open = binder_open, + .flush = binder_flush, + .release = binder_release, +}; + +static struct miscdevice binder_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "binder", + .fops = &binder_fops +}; + +BINDER_DEBUG_ENTRY(state); +BINDER_DEBUG_ENTRY(stats); +BINDER_DEBUG_ENTRY(transactions); +BINDER_DEBUG_ENTRY(transaction_log); + +static int __init binder_init(void) +{ + int ret; + + binder_deferred_workqueue = create_singlethread_workqueue("binder"); + if (!binder_deferred_workqueue) + return -ENOMEM; + + binder_debugfs_dir_entry_root = debugfs_create_dir("binder", NULL); + if (binder_debugfs_dir_entry_root) + binder_debugfs_dir_entry_proc = debugfs_create_dir("proc", + binder_debugfs_dir_entry_root); + ret = misc_register(&binder_miscdev); + if (binder_debugfs_dir_entry_root) { + debugfs_create_file("state", + S_IRUGO, + binder_debugfs_dir_entry_root, + NULL, + &binder_state_fops); + debugfs_create_file("stats", + S_IRUGO, + binder_debugfs_dir_entry_root, + NULL, + &binder_stats_fops); + debugfs_create_file("transactions", + S_IRUGO, + binder_debugfs_dir_entry_root, + NULL, + &binder_transactions_fops); + debugfs_create_file("transaction_log", + S_IRUGO, + binder_debugfs_dir_entry_root, + &binder_transaction_log, + &binder_transaction_log_fops); + debugfs_create_file("failed_transaction_log", + S_IRUGO, + binder_debugfs_dir_entry_root, + &binder_transaction_log_failed, + &binder_transaction_log_fops); + } + return ret; +} + +device_initcall(binder_init); + +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/android/binder.h b/drivers/staging/android/binder.h new file mode 100644 index 000000000000..863ae1ad5d55 --- /dev/null +++ b/drivers/staging/android/binder.h @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2008 Google, Inc. + * + * Based on, but no longer compatible with, the original + * OpenBinder.org binder driver interface, which is: + * + * Copyright (c) 2005 Palmsource, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_BINDER_H +#define _LINUX_BINDER_H + +#include + +#define B_PACK_CHARS(c1, c2, c3, c4) \ + ((((c1)<<24)) | (((c2)<<16)) | (((c3)<<8)) | (c4)) +#define B_TYPE_LARGE 0x85 + +enum { + BINDER_TYPE_BINDER = B_PACK_CHARS('s', 'b', '*', B_TYPE_LARGE), + BINDER_TYPE_WEAK_BINDER = B_PACK_CHARS('w', 'b', '*', B_TYPE_LARGE), + BINDER_TYPE_HANDLE = B_PACK_CHARS('s', 'h', '*', B_TYPE_LARGE), + BINDER_TYPE_WEAK_HANDLE = B_PACK_CHARS('w', 'h', '*', B_TYPE_LARGE), + BINDER_TYPE_FD = B_PACK_CHARS('f', 'd', '*', B_TYPE_LARGE), +}; + +enum { + FLAT_BINDER_FLAG_PRIORITY_MASK = 0xff, + FLAT_BINDER_FLAG_ACCEPTS_FDS = 0x100, +}; + +/* + * This is the flattened representation of a Binder object for transfer + * between processes. The 'offsets' supplied as part of a binder transaction + * contains offsets into the data where these structures occur. The Binder + * driver takes care of re-writing the structure type and data as it moves + * between processes. + */ +struct flat_binder_object { + /* 8 bytes for large_flat_header. */ + unsigned long type; + unsigned long flags; + + /* 8 bytes of data. */ + union { + void *binder; /* local object */ + signed long handle; /* remote object */ + }; + + /* extra data associated with local object */ + void *cookie; +}; + +/* + * On 64-bit platforms where user code may run in 32-bits the driver must + * translate the buffer (and local binder) addresses apropriately. + */ + +struct binder_write_read { + signed long write_size; /* bytes to write */ + signed long write_consumed; /* bytes consumed by driver */ + unsigned long write_buffer; + signed long read_size; /* bytes to read */ + signed long read_consumed; /* bytes consumed by driver */ + unsigned long read_buffer; +}; + +/* Use with BINDER_VERSION, driver fills in fields. */ +struct binder_version { + /* driver protocol version -- increment with incompatible change */ + signed long protocol_version; +}; + +/* This is the current protocol version. */ +#define BINDER_CURRENT_PROTOCOL_VERSION 7 + +#define BINDER_WRITE_READ _IOWR('b', 1, struct binder_write_read) +#define BINDER_SET_IDLE_TIMEOUT _IOW('b', 3, int64_t) +#define BINDER_SET_MAX_THREADS _IOW('b', 5, size_t) +#define BINDER_SET_IDLE_PRIORITY _IOW('b', 6, int) +#define BINDER_SET_CONTEXT_MGR _IOW('b', 7, int) +#define BINDER_THREAD_EXIT _IOW('b', 8, int) +#define BINDER_VERSION _IOWR('b', 9, struct binder_version) + +/* + * NOTE: Two special error codes you should check for when calling + * in to the driver are: + * + * EINTR -- The operation has been interupted. This should be + * handled by retrying the ioctl() until a different error code + * is returned. + * + * ECONNREFUSED -- The driver is no longer accepting operations + * from your process. That is, the process is being destroyed. + * You should handle this by exiting from your process. Note + * that once this error code is returned, all further calls to + * the driver from any thread will return this same code. + */ + +enum transaction_flags { + TF_ONE_WAY = 0x01, /* this is a one-way call: async, no return */ + TF_ROOT_OBJECT = 0x04, /* contents are the component's root object */ + TF_STATUS_CODE = 0x08, /* contents are a 32-bit status code */ + TF_ACCEPT_FDS = 0x10, /* allow replies with file descriptors */ +}; + +struct binder_transaction_data { + /* The first two are only used for bcTRANSACTION and brTRANSACTION, + * identifying the target and contents of the transaction. + */ + union { + size_t handle; /* target descriptor of command transaction */ + void *ptr; /* target descriptor of return transaction */ + } target; + void *cookie; /* target object cookie */ + unsigned int code; /* transaction command */ + + /* General information about the transaction. */ + unsigned int flags; + pid_t sender_pid; + uid_t sender_euid; + size_t data_size; /* number of bytes of data */ + size_t offsets_size; /* number of bytes of offsets */ + + /* If this transaction is inline, the data immediately + * follows here; otherwise, it ends with a pointer to + * the data buffer. + */ + union { + struct { + /* transaction data */ + const void *buffer; + /* offsets from buffer to flat_binder_object structs */ + const void *offsets; + } ptr; + uint8_t buf[8]; + } data; +}; + +struct binder_ptr_cookie { + void *ptr; + void *cookie; +}; + +struct binder_pri_desc { + int priority; + int desc; +}; + +struct binder_pri_ptr_cookie { + int priority; + void *ptr; + void *cookie; +}; + +enum BinderDriverReturnProtocol { + BR_ERROR = _IOR('r', 0, int), + /* + * int: error code + */ + + BR_OK = _IO('r', 1), + /* No parameters! */ + + BR_TRANSACTION = _IOR('r', 2, struct binder_transaction_data), + BR_REPLY = _IOR('r', 3, struct binder_transaction_data), + /* + * binder_transaction_data: the received command. + */ + + BR_ACQUIRE_RESULT = _IOR('r', 4, int), + /* + * not currently supported + * int: 0 if the last bcATTEMPT_ACQUIRE was not successful. + * Else the remote object has acquired a primary reference. + */ + + BR_DEAD_REPLY = _IO('r', 5), + /* + * The target of the last transaction (either a bcTRANSACTION or + * a bcATTEMPT_ACQUIRE) is no longer with us. No parameters. + */ + + BR_TRANSACTION_COMPLETE = _IO('r', 6), + /* + * No parameters... always refers to the last transaction requested + * (including replies). Note that this will be sent even for + * asynchronous transactions. + */ + + BR_INCREFS = _IOR('r', 7, struct binder_ptr_cookie), + BR_ACQUIRE = _IOR('r', 8, struct binder_ptr_cookie), + BR_RELEASE = _IOR('r', 9, struct binder_ptr_cookie), + BR_DECREFS = _IOR('r', 10, struct binder_ptr_cookie), + /* + * void *: ptr to binder + * void *: cookie for binder + */ + + BR_ATTEMPT_ACQUIRE = _IOR('r', 11, struct binder_pri_ptr_cookie), + /* + * not currently supported + * int: priority + * void *: ptr to binder + * void *: cookie for binder + */ + + BR_NOOP = _IO('r', 12), + /* + * No parameters. Do nothing and examine the next command. It exists + * primarily so that we can replace it with a BR_SPAWN_LOOPER command. + */ + + BR_SPAWN_LOOPER = _IO('r', 13), + /* + * No parameters. The driver has determined that a process has no + * threads waiting to service incomming transactions. When a process + * receives this command, it must spawn a new service thread and + * register it via bcENTER_LOOPER. + */ + + BR_FINISHED = _IO('r', 14), + /* + * not currently supported + * stop threadpool thread + */ + + BR_DEAD_BINDER = _IOR('r', 15, void *), + /* + * void *: cookie + */ + BR_CLEAR_DEATH_NOTIFICATION_DONE = _IOR('r', 16, void *), + /* + * void *: cookie + */ + + BR_FAILED_REPLY = _IO('r', 17), + /* + * The the last transaction (either a bcTRANSACTION or + * a bcATTEMPT_ACQUIRE) failed (e.g. out of memory). No parameters. + */ +}; + +enum BinderDriverCommandProtocol { + BC_TRANSACTION = _IOW('c', 0, struct binder_transaction_data), + BC_REPLY = _IOW('c', 1, struct binder_transaction_data), + /* + * binder_transaction_data: the sent command. + */ + + BC_ACQUIRE_RESULT = _IOW('c', 2, int), + /* + * not currently supported + * int: 0 if the last BR_ATTEMPT_ACQUIRE was not successful. + * Else you have acquired a primary reference on the object. + */ + + BC_FREE_BUFFER = _IOW('c', 3, int), + /* + * void *: ptr to transaction data received on a read + */ + + BC_INCREFS = _IOW('c', 4, int), + BC_ACQUIRE = _IOW('c', 5, int), + BC_RELEASE = _IOW('c', 6, int), + BC_DECREFS = _IOW('c', 7, int), + /* + * int: descriptor + */ + + BC_INCREFS_DONE = _IOW('c', 8, struct binder_ptr_cookie), + BC_ACQUIRE_DONE = _IOW('c', 9, struct binder_ptr_cookie), + /* + * void *: ptr to binder + * void *: cookie for binder + */ + + BC_ATTEMPT_ACQUIRE = _IOW('c', 10, struct binder_pri_desc), + /* + * not currently supported + * int: priority + * int: descriptor + */ + + BC_REGISTER_LOOPER = _IO('c', 11), + /* + * No parameters. + * Register a spawned looper thread with the device. + */ + + BC_ENTER_LOOPER = _IO('c', 12), + BC_EXIT_LOOPER = _IO('c', 13), + /* + * No parameters. + * These two commands are sent as an application-level thread + * enters and exits the binder loop, respectively. They are + * used so the binder can have an accurate count of the number + * of looping threads it has available. + */ + + BC_REQUEST_DEATH_NOTIFICATION = _IOW('c', 14, struct binder_ptr_cookie), + /* + * void *: ptr to binder + * void *: cookie + */ + + BC_CLEAR_DEATH_NOTIFICATION = _IOW('c', 15, struct binder_ptr_cookie), + /* + * void *: ptr to binder + * void *: cookie + */ + + BC_DEAD_BINDER_DONE = _IOW('c', 16, void *), + /* + * void *: cookie + */ +}; + +#endif /* _LINUX_BINDER_H */ + diff --git a/drivers/staging/android/logger.c b/drivers/staging/android/logger.c new file mode 100644 index 000000000000..531bdbeede89 --- /dev/null +++ b/drivers/staging/android/logger.c @@ -0,0 +1,616 @@ +/* + * drivers/misc/logger.c + * + * A Logging Subsystem + * + * Copyright (C) 2007-2008 Google, Inc. + * + * Robert Love + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "logger.h" + +#include + +/* + * struct logger_log - represents a specific log, such as 'main' or 'radio' + * + * This structure lives from module insertion until module removal, so it does + * not need additional reference counting. The structure is protected by the + * mutex 'mutex'. + */ +struct logger_log { + unsigned char *buffer;/* the ring buffer itself */ + struct miscdevice misc; /* misc device representing the log */ + wait_queue_head_t wq; /* wait queue for readers */ + struct list_head readers; /* this log's readers */ + struct mutex mutex; /* mutex protecting buffer */ + size_t w_off; /* current write head offset */ + size_t head; /* new readers start here */ + size_t size; /* size of the log */ +}; + +/* + * struct logger_reader - a logging device open for reading + * + * This object lives from open to release, so we don't need additional + * reference counting. The structure is protected by log->mutex. + */ +struct logger_reader { + struct logger_log *log; /* associated log */ + struct list_head list; /* entry in logger_log's list */ + size_t r_off; /* current read head offset */ +}; + +/* logger_offset - returns index 'n' into the log via (optimized) modulus */ +#define logger_offset(n) ((n) & (log->size - 1)) + +/* + * file_get_log - Given a file structure, return the associated log + * + * This isn't aesthetic. We have several goals: + * + * 1) Need to quickly obtain the associated log during an I/O operation + * 2) Readers need to maintain state (logger_reader) + * 3) Writers need to be very fast (open() should be a near no-op) + * + * In the reader case, we can trivially go file->logger_reader->logger_log. + * For a writer, we don't want to maintain a logger_reader, so we just go + * file->logger_log. Thus what file->private_data points at depends on whether + * or not the file was opened for reading. This function hides that dirtiness. + */ +static inline struct logger_log *file_get_log(struct file *file) +{ + if (file->f_mode & FMODE_READ) { + struct logger_reader *reader = file->private_data; + return reader->log; + } else + return file->private_data; +} + +/* + * get_entry_len - Grabs the length of the payload of the next entry starting + * from 'off'. + * + * Caller needs to hold log->mutex. + */ +static __u32 get_entry_len(struct logger_log *log, size_t off) +{ + __u16 val; + + switch (log->size - off) { + case 1: + memcpy(&val, log->buffer + off, 1); + memcpy(((char *) &val) + 1, log->buffer, 1); + break; + default: + memcpy(&val, log->buffer + off, 2); + } + + return sizeof(struct logger_entry) + val; +} + +/* + * do_read_log_to_user - reads exactly 'count' bytes from 'log' into the + * user-space buffer 'buf'. Returns 'count' on success. + * + * Caller must hold log->mutex. + */ +static ssize_t do_read_log_to_user(struct logger_log *log, + struct logger_reader *reader, + char __user *buf, + size_t count) +{ + size_t len; + + /* + * We read from the log in two disjoint operations. First, we read from + * the current read head offset up to 'count' bytes or to the end of + * the log, whichever comes first. + */ + len = min(count, log->size - reader->r_off); + if (copy_to_user(buf, log->buffer + reader->r_off, len)) + return -EFAULT; + + /* + * Second, we read any remaining bytes, starting back at the head of + * the log. + */ + if (count != len) + if (copy_to_user(buf + len, log->buffer, count - len)) + return -EFAULT; + + reader->r_off = logger_offset(reader->r_off + count); + + return count; +} + +/* + * logger_read - our log's read() method + * + * Behavior: + * + * - O_NONBLOCK works + * - If there are no log entries to read, blocks until log is written to + * - Atomically reads exactly one log entry + * + * Optimal read size is LOGGER_ENTRY_MAX_LEN. Will set errno to EINVAL if read + * buffer is insufficient to hold next entry. + */ +static ssize_t logger_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + struct logger_reader *reader = file->private_data; + struct logger_log *log = reader->log; + ssize_t ret; + DEFINE_WAIT(wait); + +start: + while (1) { + prepare_to_wait(&log->wq, &wait, TASK_INTERRUPTIBLE); + + mutex_lock(&log->mutex); + ret = (log->w_off == reader->r_off); + mutex_unlock(&log->mutex); + if (!ret) + break; + + if (file->f_flags & O_NONBLOCK) { + ret = -EAGAIN; + break; + } + + if (signal_pending(current)) { + ret = -EINTR; + break; + } + + schedule(); + } + + finish_wait(&log->wq, &wait); + if (ret) + return ret; + + mutex_lock(&log->mutex); + + /* is there still something to read or did we race? */ + if (unlikely(log->w_off == reader->r_off)) { + mutex_unlock(&log->mutex); + goto start; + } + + /* get the size of the next entry */ + ret = get_entry_len(log, reader->r_off); + if (count < ret) { + ret = -EINVAL; + goto out; + } + + /* get exactly one entry from the log */ + ret = do_read_log_to_user(log, reader, buf, ret); + +out: + mutex_unlock(&log->mutex); + + return ret; +} + +/* + * get_next_entry - return the offset of the first valid entry at least 'len' + * bytes after 'off'. + * + * Caller must hold log->mutex. + */ +static size_t get_next_entry(struct logger_log *log, size_t off, size_t len) +{ + size_t count = 0; + + do { + size_t nr = get_entry_len(log, off); + off = logger_offset(off + nr); + count += nr; + } while (count < len); + + return off; +} + +/* + * clock_interval - is a < c < b in mod-space? Put another way, does the line + * from a to b cross c? + */ +static inline int clock_interval(size_t a, size_t b, size_t c) +{ + if (b < a) { + if (a < c || b >= c) + return 1; + } else { + if (a < c && b >= c) + return 1; + } + + return 0; +} + +/* + * fix_up_readers - walk the list of all readers and "fix up" any who were + * lapped by the writer; also do the same for the default "start head". + * We do this by "pulling forward" the readers and start head to the first + * entry after the new write head. + * + * The caller needs to hold log->mutex. + */ +static void fix_up_readers(struct logger_log *log, size_t len) +{ + size_t old = log->w_off; + size_t new = logger_offset(old + len); + struct logger_reader *reader; + + if (clock_interval(old, new, log->head)) + log->head = get_next_entry(log, log->head, len); + + list_for_each_entry(reader, &log->readers, list) + if (clock_interval(old, new, reader->r_off)) + reader->r_off = get_next_entry(log, reader->r_off, len); +} + +/* + * do_write_log - writes 'len' bytes from 'buf' to 'log' + * + * The caller needs to hold log->mutex. + */ +static void do_write_log(struct logger_log *log, const void *buf, size_t count) +{ + size_t len; + + len = min(count, log->size - log->w_off); + memcpy(log->buffer + log->w_off, buf, len); + + if (count != len) + memcpy(log->buffer, buf + len, count - len); + + log->w_off = logger_offset(log->w_off + count); + +} + +/* + * do_write_log_user - writes 'len' bytes from the user-space buffer 'buf' to + * the log 'log' + * + * The caller needs to hold log->mutex. + * + * Returns 'count' on success, negative error code on failure. + */ +static ssize_t do_write_log_from_user(struct logger_log *log, + const void __user *buf, size_t count) +{ + size_t len; + + len = min(count, log->size - log->w_off); + if (len && copy_from_user(log->buffer + log->w_off, buf, len)) + return -EFAULT; + + if (count != len) + if (copy_from_user(log->buffer, buf + len, count - len)) + return -EFAULT; + + log->w_off = logger_offset(log->w_off + count); + + return count; +} + +/* + * logger_aio_write - our write method, implementing support for write(), + * writev(), and aio_write(). Writes are our fast path, and we try to optimize + * them above all else. + */ +ssize_t logger_aio_write(struct kiocb *iocb, const struct iovec *iov, + unsigned long nr_segs, loff_t ppos) +{ + struct logger_log *log = file_get_log(iocb->ki_filp); + size_t orig = log->w_off; + struct logger_entry header; + struct timespec now; + ssize_t ret = 0; + + now = current_kernel_time(); + + header.pid = current->tgid; + header.tid = current->pid; + header.sec = now.tv_sec; + header.nsec = now.tv_nsec; + header.len = min_t(size_t, iocb->ki_left, LOGGER_ENTRY_MAX_PAYLOAD); + + /* null writes succeed, return zero */ + if (unlikely(!header.len)) + return 0; + + mutex_lock(&log->mutex); + + /* + * Fix up any readers, pulling them forward to the first readable + * entry after (what will be) the new write offset. We do this now + * because if we partially fail, we can end up with clobbered log + * entries that encroach on readable buffer. + */ + fix_up_readers(log, sizeof(struct logger_entry) + header.len); + + do_write_log(log, &header, sizeof(struct logger_entry)); + + while (nr_segs-- > 0) { + size_t len; + ssize_t nr; + + /* figure out how much of this vector we can keep */ + len = min_t(size_t, iov->iov_len, header.len - ret); + + /* write out this segment's payload */ + nr = do_write_log_from_user(log, iov->iov_base, len); + if (unlikely(nr < 0)) { + log->w_off = orig; + mutex_unlock(&log->mutex); + return nr; + } + + iov++; + ret += nr; + } + + mutex_unlock(&log->mutex); + + /* wake up any blocked readers */ + wake_up_interruptible(&log->wq); + + return ret; +} + +static struct logger_log *get_log_from_minor(int); + +/* + * logger_open - the log's open() file operation + * + * Note how near a no-op this is in the write-only case. Keep it that way! + */ +static int logger_open(struct inode *inode, struct file *file) +{ + struct logger_log *log; + int ret; + + ret = nonseekable_open(inode, file); + if (ret) + return ret; + + log = get_log_from_minor(MINOR(inode->i_rdev)); + if (!log) + return -ENODEV; + + if (file->f_mode & FMODE_READ) { + struct logger_reader *reader; + + reader = kmalloc(sizeof(struct logger_reader), GFP_KERNEL); + if (!reader) + return -ENOMEM; + + reader->log = log; + INIT_LIST_HEAD(&reader->list); + + mutex_lock(&log->mutex); + reader->r_off = log->head; + list_add_tail(&reader->list, &log->readers); + mutex_unlock(&log->mutex); + + file->private_data = reader; + } else + file->private_data = log; + + return 0; +} + +/* + * logger_release - the log's release file operation + * + * Note this is a total no-op in the write-only case. Keep it that way! + */ +static int logger_release(struct inode *ignored, struct file *file) +{ + if (file->f_mode & FMODE_READ) { + struct logger_reader *reader = file->private_data; + list_del(&reader->list); + kfree(reader); + } + + return 0; +} + +/* + * logger_poll - the log's poll file operation, for poll/select/epoll + * + * Note we always return POLLOUT, because you can always write() to the log. + * Note also that, strictly speaking, a return value of POLLIN does not + * guarantee that the log is readable without blocking, as there is a small + * chance that the writer can lap the reader in the interim between poll() + * returning and the read() request. + */ +static unsigned int logger_poll(struct file *file, poll_table *wait) +{ + struct logger_reader *reader; + struct logger_log *log; + unsigned int ret = POLLOUT | POLLWRNORM; + + if (!(file->f_mode & FMODE_READ)) + return ret; + + reader = file->private_data; + log = reader->log; + + poll_wait(file, &log->wq, wait); + + mutex_lock(&log->mutex); + if (log->w_off != reader->r_off) + ret |= POLLIN | POLLRDNORM; + mutex_unlock(&log->mutex); + + return ret; +} + +static long logger_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct logger_log *log = file_get_log(file); + struct logger_reader *reader; + long ret = -ENOTTY; + + mutex_lock(&log->mutex); + + switch (cmd) { + case LOGGER_GET_LOG_BUF_SIZE: + ret = log->size; + break; + case LOGGER_GET_LOG_LEN: + if (!(file->f_mode & FMODE_READ)) { + ret = -EBADF; + break; + } + reader = file->private_data; + if (log->w_off >= reader->r_off) + ret = log->w_off - reader->r_off; + else + ret = (log->size - reader->r_off) + log->w_off; + break; + case LOGGER_GET_NEXT_ENTRY_LEN: + if (!(file->f_mode & FMODE_READ)) { + ret = -EBADF; + break; + } + reader = file->private_data; + if (log->w_off != reader->r_off) + ret = get_entry_len(log, reader->r_off); + else + ret = 0; + break; + case LOGGER_FLUSH_LOG: + if (!(file->f_mode & FMODE_WRITE)) { + ret = -EBADF; + break; + } + list_for_each_entry(reader, &log->readers, list) + reader->r_off = log->w_off; + log->head = log->w_off; + ret = 0; + break; + } + + mutex_unlock(&log->mutex); + + return ret; +} + +static const struct file_operations logger_fops = { + .owner = THIS_MODULE, + .read = logger_read, + .aio_write = logger_aio_write, + .poll = logger_poll, + .unlocked_ioctl = logger_ioctl, + .compat_ioctl = logger_ioctl, + .open = logger_open, + .release = logger_release, +}; + +/* + * Defines a log structure with name 'NAME' and a size of 'SIZE' bytes, which + * must be a power of two, greater than LOGGER_ENTRY_MAX_LEN, and less than + * LONG_MAX minus LOGGER_ENTRY_MAX_LEN. + */ +#define DEFINE_LOGGER_DEVICE(VAR, NAME, SIZE) \ +static unsigned char _buf_ ## VAR[SIZE]; \ +static struct logger_log VAR = { \ + .buffer = _buf_ ## VAR, \ + .misc = { \ + .minor = MISC_DYNAMIC_MINOR, \ + .name = NAME, \ + .fops = &logger_fops, \ + .parent = NULL, \ + }, \ + .wq = __WAIT_QUEUE_HEAD_INITIALIZER(VAR .wq), \ + .readers = LIST_HEAD_INIT(VAR .readers), \ + .mutex = __MUTEX_INITIALIZER(VAR .mutex), \ + .w_off = 0, \ + .head = 0, \ + .size = SIZE, \ +}; + +DEFINE_LOGGER_DEVICE(log_main, LOGGER_LOG_MAIN, 64*1024) +DEFINE_LOGGER_DEVICE(log_events, LOGGER_LOG_EVENTS, 256*1024) +DEFINE_LOGGER_DEVICE(log_radio, LOGGER_LOG_RADIO, 64*1024) +DEFINE_LOGGER_DEVICE(log_system, LOGGER_LOG_SYSTEM, 64*1024) + +static struct logger_log *get_log_from_minor(int minor) +{ + if (log_main.misc.minor == minor) + return &log_main; + if (log_events.misc.minor == minor) + return &log_events; + if (log_radio.misc.minor == minor) + return &log_radio; + if (log_system.misc.minor == minor) + return &log_system; + return NULL; +} + +static int __init init_log(struct logger_log *log) +{ + int ret; + + ret = misc_register(&log->misc); + if (unlikely(ret)) { + printk(KERN_ERR "logger: failed to register misc " + "device for log '%s'!\n", log->misc.name); + return ret; + } + + printk(KERN_INFO "logger: created %luK log '%s'\n", + (unsigned long) log->size >> 10, log->misc.name); + + return 0; +} + +static int __init logger_init(void) +{ + int ret; + + ret = init_log(&log_main); + if (unlikely(ret)) + goto out; + + ret = init_log(&log_events); + if (unlikely(ret)) + goto out; + + ret = init_log(&log_radio); + if (unlikely(ret)) + goto out; + + ret = init_log(&log_system); + if (unlikely(ret)) + goto out; + +out: + return ret; +} +device_initcall(logger_init); diff --git a/drivers/staging/android/logger.h b/drivers/staging/android/logger.h new file mode 100644 index 000000000000..2cb06e9d8f98 --- /dev/null +++ b/drivers/staging/android/logger.h @@ -0,0 +1,49 @@ +/* include/linux/logger.h + * + * Copyright (C) 2007-2008 Google, Inc. + * Author: Robert Love + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_LOGGER_H +#define _LINUX_LOGGER_H + +#include +#include + +struct logger_entry { + __u16 len; /* length of the payload */ + __u16 __pad; /* no matter what, we get 2 bytes of padding */ + __s32 pid; /* generating process's pid */ + __s32 tid; /* generating process's tid */ + __s32 sec; /* seconds since Epoch */ + __s32 nsec; /* nanoseconds */ + char msg[0]; /* the entry's payload */ +}; + +#define LOGGER_LOG_RADIO "log_radio" /* radio-related messages */ +#define LOGGER_LOG_EVENTS "log_events" /* system/hardware events */ +#define LOGGER_LOG_SYSTEM "log_system" /* system/framework messages */ +#define LOGGER_LOG_MAIN "log_main" /* everything else */ + +#define LOGGER_ENTRY_MAX_LEN (4*1024) +#define LOGGER_ENTRY_MAX_PAYLOAD \ + (LOGGER_ENTRY_MAX_LEN - sizeof(struct logger_entry)) + +#define __LOGGERIO 0xAE + +#define LOGGER_GET_LOG_BUF_SIZE _IO(__LOGGERIO, 1) /* size of log */ +#define LOGGER_GET_LOG_LEN _IO(__LOGGERIO, 2) /* used log len */ +#define LOGGER_GET_NEXT_ENTRY_LEN _IO(__LOGGERIO, 3) /* next entry len */ +#define LOGGER_FLUSH_LOG _IO(__LOGGERIO, 4) /* flush log */ + +#endif /* _LINUX_LOGGER_H */ diff --git a/drivers/staging/android/lowmemorykiller.c b/drivers/staging/android/lowmemorykiller.c new file mode 100644 index 000000000000..c242bb348f1a --- /dev/null +++ b/drivers/staging/android/lowmemorykiller.c @@ -0,0 +1,220 @@ +/* drivers/misc/lowmemorykiller.c + * + * The lowmemorykiller driver lets user-space specify a set of memory thresholds + * where processes with a range of oom_adj values will get killed. Specify the + * minimum oom_adj values in /sys/module/lowmemorykiller/parameters/adj and the + * number of free pages in /sys/module/lowmemorykiller/parameters/minfree. Both + * files take a comma separated list of numbers in ascending order. + * + * For example, write "0,8" to /sys/module/lowmemorykiller/parameters/adj and + * "1024,4096" to /sys/module/lowmemorykiller/parameters/minfree to kill processes + * with a oom_adj value of 8 or higher when the free memory drops below 4096 pages + * and kill processes with a oom_adj value of 0 or higher when the free memory + * drops below 1024 pages. + * + * The driver considers memory used for caches to be free, but if a large + * percentage of the cached memory is locked this can be very inaccurate + * and processes may not get killed until the normal oom killer is triggered. + * + * Copyright (C) 2007-2008 Google, Inc. + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static uint32_t lowmem_debug_level = 2; +static int lowmem_adj[6] = { + 0, + 1, + 6, + 12, +}; +static int lowmem_adj_size = 4; +static size_t lowmem_minfree[6] = { + 3 * 512, /* 6MB */ + 2 * 1024, /* 8MB */ + 4 * 1024, /* 16MB */ + 16 * 1024, /* 64MB */ +}; +static int lowmem_minfree_size = 4; + +static struct task_struct *lowmem_deathpending; + +#define lowmem_print(level, x...) \ + do { \ + if (lowmem_debug_level >= (level)) \ + printk(x); \ + } while (0) + +static int +task_notify_func(struct notifier_block *self, unsigned long val, void *data); + +static struct notifier_block task_nb = { + .notifier_call = task_notify_func, +}; + +static int +task_notify_func(struct notifier_block *self, unsigned long val, void *data) +{ + struct task_struct *task = data; + if (task == lowmem_deathpending) { + lowmem_deathpending = NULL; + task_free_unregister(&task_nb); + } + return NOTIFY_OK; +} + +static int lowmem_shrink(struct shrinker *s, int nr_to_scan, gfp_t gfp_mask) +{ + struct task_struct *p; + struct task_struct *selected = NULL; + int rem = 0; + int tasksize; + int i; + int min_adj = OOM_ADJUST_MAX + 1; + int selected_tasksize = 0; + int selected_oom_adj; + int array_size = ARRAY_SIZE(lowmem_adj); + int other_free = global_page_state(NR_FREE_PAGES); + int other_file = global_page_state(NR_FILE_PAGES); + int node; + + for_each_node_state(node, N_HIGH_MEMORY) { + struct zone *z = + &NODE_DATA(node)->node_zones[ZONE_DMA]; + + other_free -= zone_page_state(z, NR_FREE_PAGES); + other_file -= zone_page_state(z, NR_FILE_PAGES); + } + + /* + * If we already have a death outstanding, then + * bail out right away; indicating to vmscan + * that we have nothing further to offer on + * this pass. + * + */ + if (lowmem_deathpending) + return 0; + + if (lowmem_adj_size < array_size) + array_size = lowmem_adj_size; + if (lowmem_minfree_size < array_size) + array_size = lowmem_minfree_size; + for (i = 0; i < array_size; i++) { + if (other_free < lowmem_minfree[i] && + other_file < lowmem_minfree[i]) { + min_adj = lowmem_adj[i]; + break; + } + } + if (nr_to_scan > 0) + lowmem_print(3, "lowmem_shrink %d, %x, ofree %d %d, ma %d\n", + nr_to_scan, gfp_mask, other_free, other_file, + min_adj); + rem = global_page_state(NR_ACTIVE_ANON) + + global_page_state(NR_ACTIVE_FILE) + + global_page_state(NR_INACTIVE_ANON) + + global_page_state(NR_INACTIVE_FILE); + if (nr_to_scan <= 0 || min_adj == OOM_ADJUST_MAX + 1) { + lowmem_print(5, "lowmem_shrink %d, %x, return %d\n", + nr_to_scan, gfp_mask, rem); + return rem; + } + selected_oom_adj = min_adj; + + read_lock(&tasklist_lock); + for_each_process(p) { + struct mm_struct *mm; + struct signal_struct *sig; + int oom_adj; + + task_lock(p); + mm = p->mm; + sig = p->signal; + if (!mm || !sig) { + task_unlock(p); + continue; + } + oom_adj = sig->oom_adj; + if (oom_adj < min_adj) { + task_unlock(p); + continue; + } + tasksize = get_mm_rss(mm); + task_unlock(p); + if (tasksize <= 0) + continue; + if (selected) { + if (oom_adj < selected_oom_adj) + continue; + if (oom_adj == selected_oom_adj && + tasksize <= selected_tasksize) + continue; + } + selected = p; + selected_tasksize = tasksize; + selected_oom_adj = oom_adj; + lowmem_print(2, "select %d (%s), adj %d, size %d, to kill\n", + p->pid, p->comm, oom_adj, tasksize); + } + if (selected) { + lowmem_print(1, "send sigkill to %d (%s), adj %d, size %d\n", + selected->pid, selected->comm, + selected_oom_adj, selected_tasksize); + lowmem_deathpending = selected; + task_free_register(&task_nb); + force_sig(SIGKILL, selected); + rem -= selected_tasksize; + } + lowmem_print(4, "lowmem_shrink %d, %x, return %d\n", + nr_to_scan, gfp_mask, rem); + read_unlock(&tasklist_lock); + return rem; +} + +static struct shrinker lowmem_shrinker = { + .shrink = lowmem_shrink, + .seeks = DEFAULT_SEEKS * 16 +}; + +static int __init lowmem_init(void) +{ + register_shrinker(&lowmem_shrinker); + return 0; +} + +static void __exit lowmem_exit(void) +{ + unregister_shrinker(&lowmem_shrinker); +} + +module_param_named(cost, lowmem_shrinker.seeks, int, S_IRUGO | S_IWUSR); +module_param_array_named(adj, lowmem_adj, int, &lowmem_adj_size, + S_IRUGO | S_IWUSR); +module_param_array_named(minfree, lowmem_minfree, uint, &lowmem_minfree_size, + S_IRUGO | S_IWUSR); +module_param_named(debug_level, lowmem_debug_level, uint, S_IRUGO | S_IWUSR); + +module_init(lowmem_init); +module_exit(lowmem_exit); + +MODULE_LICENSE("GPL"); + diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 7e0be8d00dc3..10a82ef30215 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -113,7 +113,7 @@ int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) if (!priv->phydev) return -EINVAL; - return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); + return phy_mii_ioctl(priv->phydev, rq, cmd); } static void cvm_oct_adjust_link(struct net_device *dev) diff --git a/drivers/uio/uio_pdrv_genirq.c b/drivers/uio/uio_pdrv_genirq.c index 61e569df2bba..e9db6c98e489 100644 --- a/drivers/uio/uio_pdrv_genirq.c +++ b/drivers/uio/uio_pdrv_genirq.c @@ -190,6 +190,12 @@ static int uio_pdrv_genirq_remove(struct platform_device *pdev) uio_unregister_device(priv->uioinfo); pm_runtime_disable(&pdev->dev); + + priv->uioinfo->irq_flags = 0; + priv->uioinfo->handler = NULL; + priv->uioinfo->irqcontrol = NULL; + priv->uioinfo->priv = NULL; + kfree(priv); return 0; } diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c index 162c95a088ed..40f6d8575e0b 100644 --- a/drivers/usb/class/cdc-acm.c +++ b/drivers/usb/class/cdc-acm.c @@ -596,6 +596,7 @@ static int acm_tty_open(struct tty_struct *tty, struct file *filp) acm->throttle = 0; + tasklet_schedule(&acm->urb_task); set_bit(ASYNCB_INITIALIZED, &acm->port.flags); rv = tty_port_block_til_ready(&acm->port, tty, filp); tasklet_schedule(&acm->urb_task); diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c index a6bd53ace035..babc9a2da20f 100644 --- a/drivers/usb/core/driver.c +++ b/drivers/usb/core/driver.c @@ -1337,7 +1337,7 @@ int usb_resume(struct device *dev, pm_message_t msg) /* Avoid PM error messages for devices disconnected while suspended * as we'll display regular disconnect messages just a bit later. */ - if (status == -ENODEV) + if (status == -ENODEV || status == -ESHUTDOWN) status = 0; return status; } diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index ffc80e3241e1..46a5ad535aad 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -38,6 +38,24 @@ #endif #endif +#ifdef CONFIG_ARCH_STMP3XXX +#define STMP3XXX_USB_HOST_HACK +#endif + +#ifdef CONFIG_ARCH_MXS +#define MXS_USB_HOST_HACK + +#include +extern void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata, + bool enable); +#endif + +#ifdef STMP3XXX_USB_HOST_HACK +#include +#include +#include +#endif + struct usb_hub { struct device *intfdev; /* the "interface" device */ struct usb_device *hdev; @@ -2850,6 +2868,21 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1, break; } } + +#ifdef MXS_USB_HOST_HACK + { /*Must enable HOSTDISCONDETECT after second reset*/ + if (port1 == 1) { + if (udev->speed == USB_SPEED_HIGH) { + struct device *dev = hcd->self.controller; + struct fsl_usb2_platform_data *pdata; + pdata = (struct fsl_usb2_platform_data *) + dev->platform_data; + fsl_platform_set_usb_phy_dis(pdata, 1); + } + } + } +#endif + if (retval) goto fail; @@ -2977,6 +3010,25 @@ static void hub_port_connect_change(struct usb_hub *hub, int port1, "port %d, status %04x, change %04x, %s\n", port1, portstatus, portchange, portspeed (portstatus)); +#ifdef MXS_USB_HOST_HACK + { + struct device *dev = hcd->self.controller; + struct fsl_usb2_platform_data *pdata; + + pdata = (struct fsl_usb2_platform_data *)dev->platform_data; + if (dev->parent && dev->type) { + if (port1 == 1 && pdata->platform_init) + pdata->platform_init(NULL); + } + if (port1 == 1) { + if (!(portstatus&USB_PORT_STAT_CONNECTION)) { + /* Must clear HOSTDISCONDETECT when disconnect*/ + fsl_platform_set_usb_phy_dis(pdata, 0); + } + } + } +#endif + if (hub->has_indicators) { set_port_led(hub, port1, HUB_LED_AUTO); hub->indicator[port1-1] = INDICATOR_AUTO; diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 591ae9fde199..5b6b913d66b6 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -209,17 +209,6 @@ config USB_OMAP default USB_GADGET select USB_GADGET_SELECTED -config USB_OTG - boolean "OTG Support" - depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD - help - The most notable feature of USB OTG is support for a - "Dual-Role" device, which can act as either a device - or a host. The initial role choice can be changed - later, when two dual-role devices talk to each other. - - Select this only if your OMAP board has a Mini-AB connector. - config USB_GADGET_PXA25X boolean "PXA 25x or IXP 4xx" depends on (ARCH_PXA && PXA25x) || ARCH_IXP4XX @@ -484,6 +473,39 @@ config USB_GOKU default USB_GADGET select USB_GADGET_SELECTED +config USB_GADGET_ARC + boolean "Freescale USB Device Controller" + depends on ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS + select USB_GADGET_DUALSPEED + select USB_OTG_UTILS + help + Some Freescale processors have a USBOTG controller, + which supports device mode. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "arc_udc" and force all + gadget drivers to also be dynamically linked. + +config USB_STATIC_IRAM_PPH + bool "Apply static IRAM patch" + depends on USB_GADGET_ARC && (ARCH_MX37 || ARCH_MX3 || ARCH_MX25 || ARCH_MX51) + help + Apply static IRAM patch to peripheral driver. + +config USB_ARC + tristate + depends on USB_GADGET_ARC + default USB_GADGET + select USB_GADGET_SELECTED + +config WORKAROUND_ARCUSB_REG_RW + bool "work around mx28 arch register write" + depends on ARCH_MX28 && USB_ARC + default ARCH_MX28 + help + MX28 require read ARC register before write. Use SWP intructure to + implement this requirement. + config USB_GADGET_LANGWELL boolean "Intel Langwell USB Device Controller" depends on PCI @@ -552,6 +574,18 @@ config USB_GADGET_DUALSPEED Means that gadget drivers should include extra descriptors and code to handle dual-speed controllers. +config USB_OTG + boolean "OTG Support" + depends on (USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD) || \ + (USB_GADGET_ARC && (ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS) && USB_EHCI_HCD && MXC_OTG) + help + The most notable feature of USB OTG is support for a + "Dual-Role" device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + + Select this only if your OMAP board has a Mini-AB connector. + # # USB Gadget Drivers # @@ -760,6 +794,12 @@ config USB_FILE_STORAGE Say "y" to link the driver statically, or "m" to build a dynamically linked module called "g_file_storage". +config FSL_UTP + bool "UTP over Storage Gadget" + depends on USB_FILE_STORAGE + help + Freescale's extension to MSC protocol + config USB_FILE_STORAGE_TEST bool "File-backed Storage Gadget testing version" depends on USB_FILE_STORAGE diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 9bcde110feb1..7f2d86c431aa 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o +obj-$(CONFIG_USB_ARC) += arcotg_udc.o # # USB gadget drivers diff --git a/drivers/usb/gadget/arcotg_udc.c b/drivers/usb/gadget/arcotg_udc.c new file mode 100644 index 000000000000..36ea75ee858a --- /dev/null +++ b/drivers/usb/gadget/arcotg_udc.c @@ -0,0 +1,3307 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#undef DEBUG +#undef VERBOSE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arcotg_udc.h" +#include +#include + +#define DRIVER_DESC "ARC USBOTG Device Controller driver" +#define DRIVER_AUTHOR "Freescale Semiconductor" +#define DRIVER_VERSION "1 August 2005" + +#ifdef CONFIG_PPC_MPC512x +#define BIG_ENDIAN_DESC +#endif + +#ifdef BIG_ENDIAN_DESC +#define cpu_to_hc32(x) (x) +#define hc32_to_cpu(x) (x) +#else +#define cpu_to_hc32(x) cpu_to_le32((x)) +#define hc32_to_cpu(x) le32_to_cpu((x)) +#endif + +#define DMA_ADDR_INVALID (~(dma_addr_t)0) +DEFINE_MUTEX(udc_resume_mutex); +extern void usb_debounce_id_vbus(void); +static const char driver_name[] = "fsl-usb2-udc"; +static const char driver_desc[] = DRIVER_DESC; + +volatile static struct usb_dr_device *dr_regs; +volatile static struct usb_sys_interface *usb_sys_regs; + +/* it is initialized in probe() */ +static struct fsl_udc *udc_controller; + +#ifdef POSTPONE_FREE_LAST_DTD +static struct ep_td_struct *last_free_td; +#endif +static const struct usb_endpoint_descriptor +fsl_ep0_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, + .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD, +}; +static const size_t g_iram_size = IRAM_TD_PPH_SIZE; +static unsigned long g_iram_base; +static __iomem void *g_iram_addr; + +typedef int (*dev_sus)(struct device *dev, pm_message_t state); +typedef int (*dev_res) (struct device *dev); +static int udc_suspend(struct fsl_udc *udc); +static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state); +static int fsl_udc_resume(struct platform_device *pdev); +static void fsl_ep_fifo_flush(struct usb_ep *_ep); + +#ifdef CONFIG_USB_OTG +/* Get platform resource from OTG driver */ +extern struct resource *otg_get_resources(void); +#endif + +extern void fsl_platform_set_test_mode(struct fsl_usb2_platform_data *pdata, enum usb_test_mode mode); + +#ifdef CONFIG_WORKAROUND_ARCUSB_REG_RW +static void safe_writel(u32 val32, volatile u32 *addr) +{ + __asm__ ("swp %0, %0, [%1]" : : "r"(val32), "r"(addr)); +} +#endif + +#ifdef CONFIG_PPC32 +#define fsl_readl(addr) in_le32((addr)) +#define fsl_writel(addr, val32) out_le32((val32), (addr)) +#elif defined (CONFIG_WORKAROUND_ARCUSB_REG_RW) +#define fsl_readl(addr) readl((addr)) +#define fsl_writel(val32, addr) safe_writel(val32, addr) +#else +#define fsl_readl(addr) readl((addr)) +#define fsl_writel(addr, val32) writel((addr), (val32)) +#endif + +/******************************************************************** + * Internal Used Function +********************************************************************/ + +#ifdef DUMP_QUEUES +static void dump_ep_queue(struct fsl_ep *ep) +{ + int ep_index; + struct fsl_req *req; + struct ep_td_struct *dtd; + + if (list_empty(&ep->queue)) { + pr_debug("udc: empty\n"); + return; + } + + ep_index = ep_index(ep) * 2 + ep_is_in(ep); + pr_debug("udc: ep=0x%p index=%d\n", ep, ep_index); + + list_for_each_entry(req, &ep->queue, queue) { + pr_debug("udc: req=0x%p dTD count=%d\n", req, req->dtd_count); + pr_debug("udc: dTD head=0x%p tail=0x%p\n", req->head, + req->tail); + + dtd = req->head; + + while (dtd) { + if (le32_to_cpu(dtd->next_td_ptr) & DTD_NEXT_TERMINATE) + break; /* end of dTD list */ + + dtd = dtd->next_td_virt; + } + } +} +#else +static inline void dump_ep_queue(struct fsl_ep *ep) +{ +} +#endif + +#if (defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25) +/* + * The Phy at MX35 and MX25 have bugs, it must disable, and re-eable phy + * if the phy clock is disabled before + */ +static void reset_phy(void) +{ + u32 phyctrl; + phyctrl = fsl_readl(&dr_regs->phyctrl1); + phyctrl &= ~PHY_CTRL0_USBEN; + fsl_writel(phyctrl, &dr_regs->phyctrl1); + + phyctrl = fsl_readl(&dr_regs->phyctrl1); + phyctrl |= PHY_CTRL0_USBEN; + fsl_writel(phyctrl, &dr_regs->phyctrl1); +} +#else +static void reset_phy(void){; } +#endif +/*----------------------------------------------------------------- + * done() - retire a request; caller blocked irqs + * @status : request status to be set, only works when + * request is still in progress. + *--------------------------------------------------------------*/ +static void done(struct fsl_ep *ep, struct fsl_req *req, int status) +{ + struct fsl_udc *udc = NULL; + unsigned char stopped = ep->stopped; + struct ep_td_struct *curr_td, *next_td; + int j; + + udc = (struct fsl_udc *)ep->udc; + /* Removed the req from fsl_ep->queue */ + list_del_init(&req->queue); + + /* req.status should be set as -EINPROGRESS in ep_queue() */ + if (req->req.status == -EINPROGRESS) + req->req.status = status; + else + status = req->req.status; + + /* Free dtd for the request */ + next_td = req->head; + for (j = 0; j < req->dtd_count; j++) { + curr_td = next_td; + if (j != req->dtd_count - 1) { + next_td = curr_td->next_td_virt; +#ifdef POSTPONE_FREE_LAST_DTD + dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma); + } else { + if (last_free_td != NULL) + dma_pool_free(udc->td_pool, last_free_td, + last_free_td->td_dma); + last_free_td = curr_td; + } +#else + } + + dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma); +#endif + } + + if (USE_MSC_WR(req->req.length)) { + req->req.dma -= 1; + memmove(req->req.buf, req->req.buf + 1, MSC_BULK_CB_WRAP_LEN); + } + + if (req->mapped) { + dma_unmap_single(ep->udc->gadget.dev.parent, + req->req.dma, req->req.length, + ep_is_in(ep) + ? DMA_TO_DEVICE + : DMA_FROM_DEVICE); + req->req.dma = DMA_ADDR_INVALID; + req->mapped = 0; + } else + dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, + req->req.dma, req->req.length, + ep_is_in(ep) + ? DMA_TO_DEVICE + : DMA_FROM_DEVICE); + + if (status && (status != -ESHUTDOWN)) + VDBG("complete %s req %p stat %d len %u/%u", + ep->ep.name, &req->req, status, + req->req.actual, req->req.length); + + ep->stopped = 1; + + spin_unlock(&ep->udc->lock); + /* complete() is from gadget layer, + * eg fsg->bulk_in_complete() */ + if (req->req.complete) + req->req.complete(&ep->ep, &req->req); + + spin_lock(&ep->udc->lock); + ep->stopped = stopped; +} + +/*----------------------------------------------------------------- + * nuke(): delete all requests related to this ep + * called with spinlock held + *--------------------------------------------------------------*/ +static void nuke(struct fsl_ep *ep, int status) +{ + ep->stopped = 1; + /* + * At udc stop mode, the clock is already off + * So flush fifo, should be done at clock on mode. + */ + if (!ep->udc->stopped) + fsl_ep_fifo_flush(&ep->ep); + + /* Whether this eq has request linked */ + while (!list_empty(&ep->queue)) { + struct fsl_req *req = NULL; + + req = list_entry(ep->queue.next, struct fsl_req, queue); + done(ep, req, status); + } + dump_ep_queue(ep); +} + +/*------------------------------------------------------------------ + Internal Hardware related function + ------------------------------------------------------------------*/ +static inline void +dr_wake_up_enable(struct fsl_udc *udc, bool enable) +{ + struct fsl_usb2_platform_data *pdata; + pdata = udc->pdata; + + if (pdata && pdata->wake_up_enable) + pdata->wake_up_enable(pdata, enable); +} + +static inline void dr_clk_gate(bool on) +{ + struct fsl_usb2_platform_data *pdata = udc_controller->pdata; + + if (!pdata || !pdata->usb_clock_for_pm) + return; + pdata->usb_clock_for_pm(on); + if (on) + reset_phy(); +} + +static void dr_phy_low_power_mode(struct fsl_udc *udc, bool enable) +{ + struct fsl_usb2_platform_data *pdata = udc->pdata; + u32 portsc; + + if (pdata && pdata->phy_lowpower_suspend) { + pdata->phy_lowpower_suspend(pdata, enable); + } else { + if (enable) { + portsc = fsl_readl(&dr_regs->portsc1); + portsc |= PORTSCX_PHY_LOW_POWER_SPD; + fsl_writel(portsc, &dr_regs->portsc1); + } else { + portsc = fsl_readl(&dr_regs->portsc1); + portsc &= ~PORTSCX_PHY_LOW_POWER_SPD; + fsl_writel(portsc, &dr_regs->portsc1); + } + } + pdata->lowpower = enable; +} + + +/* workaroud for some boards, maybe there is a large capacitor between the ground and the Vbus + * that will cause the vbus dropping very slowly when device is detached, + * may cost 2-3 seconds to below 0.8V */ +static void udc_wait_b_session_low(void) +{ + u32 temp; + u32 wait = 5000/jiffies_to_msecs(1); /* max wait time is 5000 ms */ + /* if we are in host mode, don't need to care the B session */ + if ((fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID) == 0) + return; + /* if the udc is dettached , there will be a suspend irq */ + if (udc_controller->usb_state != USB_STATE_SUSPENDED) + return; + temp = fsl_readl(&dr_regs->otgsc); + temp &= ~OTGSC_B_SESSION_VALID_IRQ_EN; + fsl_writel(temp, &dr_regs->otgsc); + + do { + if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_B_SESSION_VALID)) + break; + msleep(jiffies_to_msecs(1)); + wait -= 1; + } while (wait); + if (!wait) + printk(KERN_ERR "ERROR!!!!!: the vbus can not be lower \ + then 0.8V for 5 seconds, Pls Check your HW design\n"); + temp = fsl_readl(&dr_regs->otgsc); + temp |= OTGSC_B_SESSION_VALID_IRQ_EN; + fsl_writel(temp, &dr_regs->otgsc); +} + +static int dr_controller_setup(struct fsl_udc *udc) +{ + unsigned int tmp = 0, portctrl = 0; + unsigned int __attribute((unused)) ctrl = 0; + unsigned long timeout; + struct fsl_usb2_platform_data *pdata; + +#define FSL_UDC_RESET_TIMEOUT 1000 + + /* before here, make sure dr_regs has been initialized */ + if (!udc) + return -EINVAL; + pdata = udc->pdata; + + /* Stop and reset the usb controller */ + tmp = fsl_readl(&dr_regs->usbcmd); + tmp &= ~USB_CMD_RUN_STOP; + fsl_writel(tmp, &dr_regs->usbcmd); + + tmp = fsl_readl(&dr_regs->usbcmd); + tmp |= USB_CMD_CTRL_RESET; + fsl_writel(tmp, &dr_regs->usbcmd); + + /* Wait for reset to complete */ + timeout = jiffies + FSL_UDC_RESET_TIMEOUT; + while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) { + if (time_after(jiffies, timeout)) { + ERR("udc reset timeout! \n"); + return -ETIMEDOUT; + } + cpu_relax(); + } + + /* Set the controller as device mode */ + tmp = fsl_readl(&dr_regs->usbmode); + tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */ + tmp |= USB_MODE_CTRL_MODE_DEVICE; + /* Disable Setup Lockout */ + tmp |= USB_MODE_SETUP_LOCK_OFF; + if (pdata->es) + tmp |= USB_MODE_ES; + fsl_writel(tmp, &dr_regs->usbmode); + + fsl_platform_set_device_mode(pdata); + + /* Clear the setup status */ + fsl_writel(0xffffffff, &dr_regs->usbsts); + + tmp = udc->ep_qh_dma; + tmp &= USB_EP_LIST_ADDRESS_MASK; + fsl_writel(tmp, &dr_regs->endpointlistaddr); + + VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x", + (int)udc->ep_qh, (int)tmp, + fsl_readl(&dr_regs->endpointlistaddr)); + + /* Config PHY interface */ + portctrl = fsl_readl(&dr_regs->portsc1); + portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH); + switch (udc->phy_mode) { + case FSL_USB2_PHY_ULPI: + portctrl |= PORTSCX_PTS_ULPI; + break; + case FSL_USB2_PHY_UTMI_WIDE: + portctrl |= PORTSCX_PTW_16BIT; + /* fall through */ + case FSL_USB2_PHY_UTMI: + portctrl |= PORTSCX_PTS_UTMI; + break; + case FSL_USB2_PHY_SERIAL: + portctrl |= PORTSCX_PTS_FSLS; + break; + default: + return -EINVAL; + } + fsl_writel(portctrl, &dr_regs->portsc1); + + if (pdata->change_ahb_burst) { + /* if usb should not work in default INCRx mode */ + tmp = fsl_readl(&dr_regs->sbuscfg); + tmp = (tmp & ~0x07) | pdata->ahb_burst_mode; + fsl_writel(tmp, &dr_regs->sbuscfg); + } + + if (pdata->have_sysif_regs) { + /* Config control enable i/o output, cpu endian register */ + ctrl = __raw_readl(&usb_sys_regs->control); + ctrl |= USB_CTRL_IOENB; + __raw_writel(ctrl, &usb_sys_regs->control); + } + +#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) + /* Turn on cache snooping hardware, since some PowerPC platforms + * wholly rely on hardware to deal with cache coherent. */ + + if (pdata->have_sysif_regs) { + /* Setup Snooping for all the 4GB space */ + tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */ + __raw_writel(tmp, &usb_sys_regs->snoop1); + tmp |= 0x80000000; /* starts from 0x8000000, size 2G */ + __raw_writel(tmp, &usb_sys_regs->snoop2); + } +#endif + + return 0; +} + +/* Enable DR irq and set controller to run state */ +static void dr_controller_run(struct fsl_udc *udc) +{ + u32 temp; + + fsl_platform_pullup_enable(udc->pdata); + + /* Enable DR irq reg */ + temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN + | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN + | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN; + + fsl_writel(temp, &dr_regs->usbintr); + + /* enable BSV irq */ + temp = fsl_readl(&dr_regs->otgsc); + temp |= OTGSC_B_SESSION_VALID_IRQ_EN; + fsl_writel(temp, &dr_regs->otgsc); + + /* If vbus not on and used low power mode */ + if (!(temp & OTGSC_B_SESSION_VALID)) { + /* Set stopped before low power mode */ + udc->stopped = 1; + /* enable wake up */ + dr_wake_up_enable(udc, true); + /* enter lower power mode */ + dr_phy_low_power_mode(udc, true); + printk(KERN_DEBUG "%s: udc enter low power mode \n", __func__); + } else { +#ifdef CONFIG_ARCH_MX37 + /* + add some delay for USB timing issue. USB may be + recognize as FS device + during USB gadget remote wake up function + */ + mdelay(100); +#endif + /* Clear stopped bit */ + udc->stopped = 0; + + /* The usb line has already been connected to pc */ + temp = fsl_readl(&dr_regs->usbcmd); + temp |= USB_CMD_RUN_STOP; + fsl_writel(temp, &dr_regs->usbcmd); + printk(KERN_DEBUG "%s: udc out low power mode\n", __func__); + } + + return; +} + +static void dr_controller_stop(struct fsl_udc *udc) +{ + unsigned int tmp; + + pr_debug("%s\n", __func__); + + /* if we're in OTG mode, and the Host is currently using the port, + * stop now and don't rip the controller out from under the + * ehci driver + */ + if (udc->gadget.is_otg) { + if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) { + pr_debug("udc: Leaving early\n"); + return; + } + } + + /* disable all INTR */ + fsl_writel(0, &dr_regs->usbintr); + + /* disable wake up */ + dr_wake_up_enable(udc, false); + /* disable BSV irq */ + tmp = fsl_readl(&dr_regs->otgsc); + tmp &= ~OTGSC_B_SESSION_VALID_IRQ_EN; + fsl_writel(tmp, &dr_regs->otgsc); + + /* Set stopped bit for isr */ + udc->stopped = 1; + + /* disable IO output */ +/* usb_sys_regs->control = 0; */ + + fsl_platform_pullup_disable(udc->pdata); + + /* set controller to Stop */ + tmp = fsl_readl(&dr_regs->usbcmd); + tmp &= ~USB_CMD_RUN_STOP; + fsl_writel(tmp, &dr_regs->usbcmd); + + return; +} + +void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type) +{ + unsigned int tmp_epctrl = 0; + + tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (dir) { + if (ep_num) + tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; + tmp_epctrl |= EPCTRL_TX_ENABLE; + tmp_epctrl |= ((unsigned int)(ep_type) + << EPCTRL_TX_EP_TYPE_SHIFT); + } else { + if (ep_num) + tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; + tmp_epctrl |= EPCTRL_RX_ENABLE; + tmp_epctrl |= ((unsigned int)(ep_type) + << EPCTRL_RX_EP_TYPE_SHIFT); + } + + fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); +} + +static void +dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value) +{ + u32 tmp_epctrl = 0; + + tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + + if (value) { + /* set the stall bit */ + if (dir) + tmp_epctrl |= EPCTRL_TX_EP_STALL; + else + tmp_epctrl |= EPCTRL_RX_EP_STALL; + } else { + /* clear the stall bit and reset data toggle */ + if (dir) { + tmp_epctrl &= ~EPCTRL_TX_EP_STALL; + tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; + } else { + tmp_epctrl &= ~EPCTRL_RX_EP_STALL; + tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; + } + } + fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); +} + +/* Get stall status of a specific ep + Return: 0: not stalled; 1:stalled */ +static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir) +{ + u32 epctrl; + + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (dir) + return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0; + else + return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0; +} + +/******************************************************************** + Internal Structure Build up functions +********************************************************************/ + +/*------------------------------------------------------------------ +* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH + * @zlt: Zero Length Termination Select (1: disable; 0: enable) + * @mult: Mult field + ------------------------------------------------------------------*/ +static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num, + unsigned char dir, unsigned char ep_type, + unsigned int max_pkt_len, + unsigned int zlt, unsigned char mult) +{ + struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir]; + unsigned int tmp = 0; + + /* set the Endpoint Capabilites in QH */ + switch (ep_type) { + case USB_ENDPOINT_XFER_CONTROL: + /* Interrupt On Setup (IOS). for control ep */ + tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) + | EP_QUEUE_HEAD_IOS; + break; + case USB_ENDPOINT_XFER_ISOC: + tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) + | (mult << EP_QUEUE_HEAD_MULT_POS); + break; + case USB_ENDPOINT_XFER_BULK: + case USB_ENDPOINT_XFER_INT: + tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS; + break; + default: + VDBG("error ep type is %d", ep_type); + return; + } + if (zlt) + tmp |= EP_QUEUE_HEAD_ZLT_SEL; + p_QH->max_pkt_length = cpu_to_hc32(tmp); + + return; +} + +/* Setup qh structure and ep register for ep0. */ +static void ep0_setup(struct fsl_udc *udc) +{ + /* the intialization of an ep includes: fields in QH, Regs, + * fsl_ep struct */ + struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL, + USB_MAX_CTRL_PAYLOAD, 0, 0); + struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL, + USB_MAX_CTRL_PAYLOAD, 0, 0); + dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL); + dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL); + + return; + +} + +/*********************************************************************** + Endpoint Management Functions +***********************************************************************/ + +/*------------------------------------------------------------------------- + * when configurations are set, or when interface settings change + * for example the do_set_interface() in gadget layer, + * the driver will enable or disable the relevant endpoints + * ep0 doesn't use this routine. It is always enabled. +-------------------------------------------------------------------------*/ +static int fsl_ep_enable(struct usb_ep *_ep, + const struct usb_endpoint_descriptor *desc) +{ + struct fsl_udc *udc = NULL; + struct fsl_ep *ep = NULL; + unsigned short max = 0; + unsigned char mult = 0, zlt; + int retval = -EINVAL; + unsigned long flags = 0; + + ep = container_of(_ep, struct fsl_ep, ep); + + pr_debug("udc: %s ep.name=%s\n", __func__, ep->ep.name); + /* catch various bogus parameters */ + if (!_ep || !desc || ep->desc + || (desc->bDescriptorType != USB_DT_ENDPOINT)) + return -EINVAL; + + udc = ep->udc; + + if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) + return -ESHUTDOWN; + + max = le16_to_cpu(desc->wMaxPacketSize); + + /* Disable automatic zlp generation. Driver is reponsible to indicate + * explicitly through req->req.zero. This is needed to enable multi-td + * request. */ + zlt = 1; + + /* Assume the max packet size from gadget is always correct */ + switch (desc->bmAttributes & 0x03) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + case USB_ENDPOINT_XFER_INT: + /* mult = 0. Execute N Transactions as demonstrated by + * the USB variable length packet protocol where N is + * computed using the Maximum Packet Length (dQH) and + * the Total Bytes field (dTD) */ + mult = 0; + break; + case USB_ENDPOINT_XFER_ISOC: + /* Calculate transactions needed for high bandwidth iso */ + mult = (unsigned char)(1 + ((max >> 11) & 0x03)); + max = max & 0x7ff; /* bit 0~10 */ + /* 3 transactions at most */ + if (mult > 3) + goto en_done; + break; + default: + goto en_done; + } + + spin_lock_irqsave(&udc->lock, flags); + ep->ep.maxpacket = max; + ep->desc = desc; + ep->stopped = 0; + + /* Controller related setup */ + /* Init EPx Queue Head (Ep Capabilites field in QH + * according to max, zlt, mult) */ + struct_ep_qh_setup(udc, (unsigned char) ep_index(ep), + (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) + ? USB_SEND : USB_RECV), + (unsigned char) (desc->bmAttributes + & USB_ENDPOINT_XFERTYPE_MASK), + max, zlt, mult); + + /* Init endpoint ctrl register */ + dr_ep_setup((unsigned char) ep_index(ep), + (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) + ? USB_SEND : USB_RECV), + (unsigned char) (desc->bmAttributes + & USB_ENDPOINT_XFERTYPE_MASK)); + + spin_unlock_irqrestore(&udc->lock, flags); + retval = 0; + + VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name, + ep->desc->bEndpointAddress & 0x0f, + (desc->bEndpointAddress & USB_DIR_IN) + ? "in" : "out", max); +en_done: + return retval; +} + +/*--------------------------------------------------------------------- + * @ep : the ep being unconfigured. May not be ep0 + * Any pending and uncomplete req will complete with status (-ESHUTDOWN) +*---------------------------------------------------------------------*/ +static int fsl_ep_disable(struct usb_ep *_ep) +{ + struct fsl_udc *udc = NULL; + struct fsl_ep *ep = NULL; + unsigned long flags = 0; + u32 epctrl; + int ep_num; + + ep = container_of(_ep, struct fsl_ep, ep); + if (!_ep || !ep->desc) { + VDBG("%s not enabled", _ep ? ep->ep.name : NULL); + return -EINVAL; + } + + spin_lock_irqsave(&udc->lock, flags); + udc = (struct fsl_udc *)ep->udc; + if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { + spin_unlock_irqrestore(&udc->lock, flags); + return -ESHUTDOWN; + } + + /* disable ep on controller */ + ep_num = ep_index(ep); + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (ep_is_in(ep)) + epctrl &= ~EPCTRL_TX_ENABLE; + else + epctrl &= ~EPCTRL_RX_ENABLE; + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); + + /* nuke all pending requests (does flush) */ + nuke(ep, -ESHUTDOWN); + + ep->desc = 0; + ep->stopped = 1; + spin_unlock_irqrestore(&udc->lock, flags); + + VDBG("disabled %s OK", _ep->name); + return 0; +} + +/*--------------------------------------------------------------------- + * allocate a request object used by this endpoint + * the main operation is to insert the req->queue to the eq->queue + * Returns the request, or null if one could not be allocated +*---------------------------------------------------------------------*/ +static struct usb_request * +fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) +{ + struct fsl_req *req = NULL; + + req = kzalloc(sizeof *req, gfp_flags); + if (!req) + return NULL; + + req->req.dma = DMA_ADDR_INVALID; + pr_debug("udc: req=0x%p set req.dma=0x%x\n", req, req->req.dma); + INIT_LIST_HEAD(&req->queue); + + return &req->req; +} + +static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req) +{ + struct fsl_req *req = NULL; + + req = container_of(_req, struct fsl_req, req); + + if (_req) + kfree(req); +} + +static void update_qh(struct fsl_req *req) +{ + struct fsl_ep *ep = req->ep; + int i = ep_index(ep) * 2 + ep_is_in(ep); + u32 temp; + struct ep_queue_head *dQH = &ep->udc->ep_qh[i]; + + /* Write dQH next pointer and terminate bit to 0 */ + temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK; + if (NEED_IRAM(req->ep)) { + /* set next dtd stop bit,ensure only one dtd in this list */ + req->cur->next_td_ptr |= cpu_to_hc32(DTD_NEXT_TERMINATE); + temp = req->cur->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK; + } + dQH->next_dtd_ptr = cpu_to_hc32(temp); + /* Clear active and halt bit */ + temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE + | EP_QUEUE_HEAD_STATUS_HALT)); + dQH->size_ioc_int_sts &= temp; + + /* Prime endpoint by writing 1 to ENDPTPRIME */ + temp = ep_is_in(ep) + ? (1 << (ep_index(ep) + 16)) + : (1 << (ep_index(ep))); + fsl_writel(temp, &dr_regs->endpointprime); +} + +/*-------------------------------------------------------------------------*/ +static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) +{ + u32 temp, bitmask, tmp_stat; + + /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr); + VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */ + + bitmask = ep_is_in(ep) + ? (1 << (ep_index(ep) + 16)) + : (1 << (ep_index(ep))); + + /* check if the pipe is empty */ + if (!(list_empty(&ep->queue))) { + /* Add td to the end */ + struct fsl_req *lastreq; + lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); + if (NEED_IRAM(ep)) { + /* only one dtd in dqh */ + lastreq->tail->next_td_ptr = + cpu_to_hc32(req->head->td_dma | DTD_NEXT_TERMINATE); + goto out; + } else { + lastreq->tail->next_td_ptr = + cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK); + } + /* Read prime bit, if 1 goto done */ + if (fsl_readl(&dr_regs->endpointprime) & bitmask) + goto out; + do { + /* Set ATDTW bit in USBCMD */ + temp = fsl_readl(&dr_regs->usbcmd); + fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd); + + /* Read correct status bit */ + tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask; + + } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW)); + + /* Write ATDTW bit to 0 */ + temp = fsl_readl(&dr_regs->usbcmd); + fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd); + + if (tmp_stat) + goto out; + } + update_qh(req); +out: + return 0; +} + +/* Fill in the dTD structure + * @req: request that the transfer belongs to + * @length: return actually data length of the dTD + * @dma: return dma address of the dTD + * @is_last: return flag if it is the last dTD of the request + * return: pointer to the built dTD */ +static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length, + dma_addr_t *dma, int *is_last) +{ + u32 swap_temp; + struct ep_td_struct *dtd; + + /* how big will this transfer be? */ + *length = min(req->req.length - req->req.actual, + (unsigned)EP_MAX_LENGTH_TRANSFER); + if (NEED_IRAM(req->ep)) + *length = min(*length, g_iram_size); + dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma); + if (dtd == NULL) + return dtd; + + dtd->td_dma = *dma; + /* Clear reserved field */ + swap_temp = hc32_to_cpu(dtd->size_ioc_sts); + swap_temp &= ~DTD_RESERVED_FIELDS; + dtd->size_ioc_sts = cpu_to_hc32(swap_temp); + + /* Init all of buffer page pointers */ + swap_temp = (u32) (req->req.dma + req->req.actual); + if (NEED_IRAM(req->ep)) + swap_temp = (u32) (req->req.dma); + dtd->buff_ptr0 = cpu_to_hc32(swap_temp); + dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000); + dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000); + dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000); + dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000); + + req->req.actual += *length; + + /* zlp is needed if req->req.zero is set */ + if (req->req.zero) { + if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) + *is_last = 1; + else + *is_last = 0; + } else if (req->req.length == req->req.actual) + *is_last = 1; + else + *is_last = 0; + + if ((*is_last) == 0) + VDBG("multi-dtd request!\n"); + /* Fill in the transfer size; set active bit */ + swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE); + + /* Enable interrupt for the last dtd of a request */ + if (*is_last && !req->req.no_interrupt) + swap_temp |= DTD_IOC; + if (NEED_IRAM(req->ep)) + swap_temp |= DTD_IOC; + + dtd->size_ioc_sts = cpu_to_hc32(swap_temp); + + mb(); + + VDBG("length = %d address= 0x%x", *length, (int)*dma); + + return dtd; +} + +/* Generate dtd chain for a request */ +static int fsl_req_to_dtd(struct fsl_req *req) +{ + unsigned count; + int is_last; + int is_first = 1; + struct ep_td_struct *last_dtd = NULL, *dtd; + dma_addr_t dma; + + if (NEED_IRAM(req->ep)) { + req->oridma = req->req.dma; + /* here, replace user buffer to iram buffer */ + if (ep_is_in(req->ep)) { + req->req.dma = req->ep->udc->iram_buffer[1]; + if ((list_empty(&req->ep->queue))) { + /* copy data only when no bulk in transfer is + running */ + memcpy((char *)req->ep->udc->iram_buffer_v[1], + req->req.buf, min(req->req.length, + g_iram_size)); + } + } else { + req->req.dma = req->ep->udc->iram_buffer[0]; + } + } + + if (USE_MSC_WR(req->req.length)) + req->req.dma += 1; + + do { + dtd = fsl_build_dtd(req, &count, &dma, &is_last); + if (dtd == NULL) + return -ENOMEM; + + if (is_first) { + is_first = 0; + req->head = dtd; + } else { + last_dtd->next_td_ptr = cpu_to_hc32(dma); + last_dtd->next_td_virt = dtd; + } + last_dtd = dtd; + + req->dtd_count++; + } while (!is_last); + + dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE); + req->cur = req->head; + req->tail = dtd; + + return 0; +} + +/* queues (submits) an I/O request to an endpoint */ +static int +fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) +{ + struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); + struct fsl_req *req = container_of(_req, struct fsl_req, req); + struct fsl_udc *udc; + unsigned long flags; + int is_iso = 0; + + spin_lock_irqsave(&udc->lock, flags); + + if (!_ep || !ep->desc) { + VDBG("%s, bad ep\n", __func__); + spin_unlock_irqrestore(&udc->lock, flags); + return -EINVAL; + } + /* catch various bogus parameters */ + if (!_req || !req->req.buf || (ep_index(ep) + && !list_empty(&req->queue))) { + VDBG("%s, bad params\n", __func__); + spin_unlock_irqrestore(&udc->lock, flags); + return -EINVAL; + } + if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { + if (req->req.length > ep->ep.maxpacket) { + spin_unlock_irqrestore(&udc->lock, flags); + return -EMSGSIZE; + } + is_iso = 1; + } + + udc = ep->udc; + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { + spin_unlock_irqrestore(&udc->lock, flags); + return -ESHUTDOWN; + } + req->ep = ep; + + /* map virtual address to hardware */ + if (req->req.dma == DMA_ADDR_INVALID) { + req->req.dma = dma_map_single(ep->udc->gadget.dev.parent, + req->req.buf, + req->req.length, ep_is_in(ep) + ? DMA_TO_DEVICE + : DMA_FROM_DEVICE); + req->mapped = 1; + } else { + dma_sync_single_for_device(ep->udc->gadget.dev.parent, + req->req.dma, req->req.length, + ep_is_in(ep) + ? DMA_TO_DEVICE + : DMA_FROM_DEVICE); + req->mapped = 0; + } + + req->req.status = -EINPROGRESS; + req->req.actual = 0; + req->dtd_count = 0; + if (NEED_IRAM(ep)) { + req->last_one = 0; + req->buffer_offset = 0; + } + + /* build dtds and push them to device queue */ + if (!fsl_req_to_dtd(req)) { + fsl_queue_td(ep, req); + } else { + spin_unlock_irqrestore(&udc->lock, flags); + return -ENOMEM; + } + + /* irq handler advances the queue */ + if (req != NULL) + list_add_tail(&req->queue, &ep->queue); + spin_unlock_irqrestore(&udc->lock, flags); + + return 0; +} + +/* dequeues (cancels, unlinks) an I/O request from an endpoint */ +static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) +{ + struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); + struct fsl_req *req; + unsigned long flags; + int ep_num, stopped, ret = 0; + struct fsl_udc *udc = NULL; + u32 epctrl; + + if (!_ep || !_req) + return -EINVAL; + + spin_lock_irqsave(&ep->udc->lock, flags); + stopped = ep->stopped; + udc = ep->udc; + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { + spin_unlock_irqrestore(&ep->udc->lock, flags); + return -ESHUTDOWN; + } + + /* Stop the ep before we deal with the queue */ + ep->stopped = 1; + ep_num = ep_index(ep); + epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (ep_is_in(ep)) + epctrl &= ~EPCTRL_TX_ENABLE; + else + epctrl &= ~EPCTRL_RX_ENABLE; + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); + + /* make sure it's actually queued on this endpoint */ + list_for_each_entry(req, &ep->queue, queue) { + if (&req->req == _req) + break; + } + if (&req->req != _req) { + ret = -EINVAL; + goto out; + } + + /* The request is in progress, or completed but not dequeued */ + if (ep->queue.next == &req->queue) { + _req->status = -ECONNRESET; + fsl_ep_fifo_flush(_ep); /* flush current transfer */ + + /* The request isn't the last request in this ep queue */ + if (req->queue.next != &ep->queue) { + struct ep_queue_head *qh; + struct fsl_req *next_req; + + qh = ep->qh; + next_req = list_entry(req->queue.next, struct fsl_req, + queue); + + /* Point the QH to the first TD of next request */ + fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr); + } + + /* The request hasn't been processed, patch up the TD chain */ + } else { + struct fsl_req *prev_req; + + prev_req = list_entry(req->queue.prev, struct fsl_req, queue); + fsl_writel(fsl_readl(&req->tail->next_td_ptr), + &prev_req->tail->next_td_ptr); + + } + + done(ep, req, -ECONNRESET); + + /* Enable EP */ +out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); + if (ep_is_in(ep)) + epctrl |= EPCTRL_TX_ENABLE; + else + epctrl |= EPCTRL_RX_ENABLE; + fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); + ep->stopped = stopped; + + spin_unlock_irqrestore(&ep->udc->lock, flags); + return ret; +} + +/*-------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------- + * modify the endpoint halt feature + * @ep: the non-isochronous endpoint being stalled + * @value: 1--set halt 0--clear halt + * Returns zero, or a negative error code. +*----------------------------------------------------------------*/ +static int fsl_ep_set_halt(struct usb_ep *_ep, int value) +{ + struct fsl_ep *ep = NULL; + unsigned long flags = 0; + int status = -EOPNOTSUPP; /* operation not supported */ + unsigned char ep_dir = 0, ep_num = 0; + struct fsl_udc *udc = NULL; + + ep = container_of(_ep, struct fsl_ep, ep); + udc = ep->udc; + if (!_ep || !ep->desc) { + status = -EINVAL; + goto out; + } + if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { + status = -ESHUTDOWN; + goto out; + } + + if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { + status = -EOPNOTSUPP; + goto out; + } + + /* Attempt to halt IN ep will fail if any transfer requests + * are still queue */ + if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { + status = -EAGAIN; + goto out; + } + + status = 0; + ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; + ep_num = (unsigned char)(ep_index(ep)); + spin_lock_irqsave(&ep->udc->lock, flags); + dr_ep_change_stall(ep_num, ep_dir, value); + spin_unlock_irqrestore(&ep->udc->lock, flags); + + if (ep_index(ep) == 0) { + udc->ep0_dir = 0; + } +out: + VDBG(" %s %s halt stat %d", ep->ep.name, + value ? "set" : "clear", status); + + return status; +} + +static int arcotg_fifo_status(struct usb_ep *_ep) +{ + struct fsl_ep *ep; + struct fsl_udc *udc; + int size = 0; + u32 bitmask; + struct ep_queue_head *d_qh; + + ep = container_of(_ep, struct fsl_ep, ep); + if (!_ep || (!ep->desc && ep_index(ep) != 0)) + return -ENODEV; + + udc = (struct fsl_udc *)ep->udc; + + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) + return -ESHUTDOWN; + + d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)]; + + bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) : + (1 << (ep_index(ep))); + + if (fsl_readl(&dr_regs->endptstatus) & bitmask) + size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE) + >> DTD_LENGTH_BIT_POS; + + pr_debug("%s %u\n", __func__, size); + return size; +} + +static void fsl_ep_fifo_flush(struct usb_ep *_ep) +{ + struct fsl_ep *ep; + int ep_num, ep_dir; + u32 bits; + unsigned long timeout; +#define FSL_UDC_FLUSH_TIMEOUT 1000 + + if (!_ep) { + return; + } else { + ep = container_of(_ep, struct fsl_ep, ep); + if (!ep->desc) + return; + } + ep_num = ep_index(ep); + ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; + + if (ep_num == 0) + bits = (1 << 16) | 1; + else if (ep_dir == USB_SEND) + bits = 1 << (16 + ep_num); + else + bits = 1 << ep_num; + + timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT; + do { + fsl_writel(bits, &dr_regs->endptflush); + + /* Wait until flush complete */ + while (fsl_readl(&dr_regs->endptflush)) { + if (time_after(jiffies, timeout)) { + ERR("ep flush timeout\n"); + return; + } + cpu_relax(); + } + /* See if we need to flush again */ + } while (fsl_readl(&dr_regs->endptstatus) & bits); +} + +static struct usb_ep_ops fsl_ep_ops = { + .enable = fsl_ep_enable, + .disable = fsl_ep_disable, + + .alloc_request = fsl_alloc_request, + .free_request = fsl_free_request, + + .queue = fsl_ep_queue, + .dequeue = fsl_ep_dequeue, + + .set_halt = fsl_ep_set_halt, + .fifo_status = arcotg_fifo_status, + .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */ +}; + +/*------------------------------------------------------------------------- + Gadget Driver Layer Operations +-------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------- + * Get the current frame number (from DR frame_index Reg ) + *----------------------------------------------------------------------*/ +static int fsl_get_frame(struct usb_gadget *gadget) +{ + return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS); +} + +/*----------------------------------------------------------------------- + * Tries to wake up the host connected to this gadget + -----------------------------------------------------------------------*/ +static int fsl_wakeup(struct usb_gadget *gadget) +{ + struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget); + u32 portsc; + + /* Remote wakeup feature not enabled by host */ + if (!udc->remote_wakeup) + return -ENOTSUPP; + + portsc = fsl_readl(&dr_regs->portsc1); + /* not suspended? */ + if (!(portsc & PORTSCX_PORT_SUSPEND)) + return 0; + /* trigger force resume */ + portsc |= PORTSCX_PORT_FORCE_RESUME; + fsl_writel(portsc, &dr_regs->portsc1); + return 0; +} + +static int can_pullup(struct fsl_udc *udc) +{ + return udc->driver && udc->softconnect && udc->vbus_active; +} + +/* Notify controller that VBUS is powered, Called by whatever + detects VBUS sessions */ +static int fsl_vbus_session(struct usb_gadget *gadget, int is_active) +{ + struct fsl_udc *udc; + unsigned long flags; + + udc = container_of(gadget, struct fsl_udc, gadget); + spin_lock_irqsave(&udc->lock, flags); + VDBG("VBUS %s\n", is_active ? "on" : "off"); + udc->vbus_active = (is_active != 0); + if (can_pullup(udc)) + fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), + &dr_regs->usbcmd); + else + fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), + &dr_regs->usbcmd); + spin_unlock_irqrestore(&udc->lock, flags); + return 0; +} + +/* constrain controller's VBUS power usage + * This call is used by gadget drivers during SET_CONFIGURATION calls, + * reporting how much power the device may consume. For example, this + * could affect how quickly batteries are recharged. + * + * Returns zero on success, else negative errno. + */ +static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA) +{ + struct fsl_udc *udc; + struct fsl_usb2_platform_data *pdata; + + udc = container_of(gadget, struct fsl_udc, gadget); + if (udc->transceiver) + return otg_set_power(udc->transceiver, mA); + pdata = udc->pdata; + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_draw) { + pdata->xcvr_ops->set_vbus_draw(pdata->xcvr_ops, pdata, mA); + return 0; + } + return -ENOTSUPP; +} + +/* Change Data+ pullup status + * this func is used by usb_gadget_connect/disconnet + */ +static int fsl_pullup(struct usb_gadget *gadget, int is_on) +{ + struct fsl_udc *udc; + + udc = container_of(gadget, struct fsl_udc, gadget); + udc->softconnect = (is_on != 0); + if (can_pullup(udc)) + fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), + &dr_regs->usbcmd); + else + fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), + &dr_regs->usbcmd); + + return 0; +} + +/* defined in gadget.h */ +static struct usb_gadget_ops fsl_gadget_ops = { + .get_frame = fsl_get_frame, + .wakeup = fsl_wakeup, +/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */ + .vbus_session = fsl_vbus_session, + .vbus_draw = fsl_vbus_draw, + .pullup = fsl_pullup, +}; + +/* Set protocol stall on ep0, protocol stall will automatically be cleared + on new transaction */ +static void ep0stall(struct fsl_udc *udc) +{ + u32 tmp; + + /* must set tx and rx to stall at the same time */ + tmp = fsl_readl(&dr_regs->endptctrl[0]); + tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL; + fsl_writel(tmp, &dr_regs->endptctrl[0]); + udc->ep0_dir = 0; +} + +/* Prime a status phase for ep0 */ +static int ep0_prime_status(struct fsl_udc *udc, int direction) +{ + struct fsl_req *req = udc->status_req; + struct fsl_ep *ep; + int status = 0; + + if (direction == EP_DIR_IN) + udc->ep0_dir = USB_DIR_IN; + else + udc->ep0_dir = USB_DIR_OUT; + + ep = &udc->eps[0]; + + req->ep = ep; + req->req.length = 0; + req->req.status = -EINPROGRESS; + + status = fsl_ep_queue(&ep->ep, &req->req, GFP_ATOMIC); + return status; +} + +static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe) +{ + struct fsl_ep *ep = get_ep_by_pipe(udc, pipe); + + if (!ep->name) + return 0; + + nuke(ep, -ESHUTDOWN); + + return 0; +} + +/* + * ch9 Set address + */ +static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length) +{ + /* Save the new address to device struct */ + udc->device_address = (u8) value; + /* Update usb state */ + udc->usb_state = USB_STATE_ADDRESS; + /* Status phase */ + if (ep0_prime_status(udc, EP_DIR_IN)) + ep0stall(udc); +} + +/* + * ch9 Get status + */ +static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value, + u16 index, u16 length) +{ + u16 tmp = 0; /* Status, cpu endian */ + + struct fsl_req *req; + struct fsl_ep *ep; + int status = 0; + + ep = &udc->eps[0]; + + if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { + /* Get device status */ + tmp = 1 << USB_DEVICE_SELF_POWERED; + tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; + } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { + /* Get interface status */ + /* We don't have interface information in udc driver */ + tmp = 0; + } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { + /* Get endpoint status */ + struct fsl_ep *target_ep; + + target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index)); + + /* stall if endpoint doesn't exist */ + if (!target_ep->desc) + goto stall; + tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep)) + << USB_ENDPOINT_HALT; + } + + udc->ep0_dir = USB_DIR_IN; + /* Borrow the per device data_req */ + /* status_req had been used to prime status */ + req = udc->data_req; + /* Fill in the reqest structure */ + *((u16 *) req->req.buf) = cpu_to_le16(tmp); + req->ep = ep; + req->req.length = 2; + + status = fsl_ep_queue(&ep->ep, &req->req, GFP_ATOMIC); + if (status) { + udc_reset_ep_queue(udc, 0); + ERR("Can't respond to getstatus request \n"); + goto stall; + } + return; +stall: + ep0stall(udc); + +} + +static void setup_received_irq(struct fsl_udc *udc, + struct usb_ctrlrequest *setup) +{ + u16 wValue = le16_to_cpu(setup->wValue); + u16 wIndex = le16_to_cpu(setup->wIndex); + u16 wLength = le16_to_cpu(setup->wLength); + struct usb_gadget *gadget = &(udc->gadget); + unsigned mA = 500; + udc_reset_ep_queue(udc, 0); + + if (wLength) { + int dir; + dir = EP_DIR_IN; + if (setup->bRequestType & USB_DIR_IN) { + dir = EP_DIR_OUT; + } + if (ep0_prime_status(udc, dir)) + ep0stall(udc); + } + /* We process some stardard setup requests here */ + switch (setup->bRequest) { + case USB_REQ_GET_STATUS: + /* Data+Status phase from udc */ + if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK)) + != (USB_DIR_IN | USB_TYPE_STANDARD)) + break; + ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength); + return; + + case USB_REQ_SET_ADDRESS: + /* Status phase from udc */ + if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD + | USB_RECIP_DEVICE)) + break; + ch9setaddress(udc, wValue, wIndex, wLength); + return; + case USB_REQ_SET_CONFIGURATION: + fsl_vbus_draw(gadget, mA); + break; + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + /* Status phase from udc */ + { + int rc = -EOPNOTSUPP; + u16 ptc = 0; + + if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) + == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) { + int pipe = get_pipe_by_windex(wIndex); + struct fsl_ep *ep; + + if (wValue != 0 || wLength != 0 || pipe > udc->max_ep) + break; + ep = get_ep_by_pipe(udc, pipe); + + spin_unlock(&udc->lock); + rc = fsl_ep_set_halt(&ep->ep, + (setup->bRequest == USB_REQ_SET_FEATURE) + ? 1 : 0); + spin_lock(&udc->lock); + + } else if ((setup->bRequestType & (USB_RECIP_MASK + | USB_TYPE_MASK)) == (USB_RECIP_DEVICE + | USB_TYPE_STANDARD)) { + /* Note: The driver has not include OTG support yet. + * This will be set when OTG support is added */ + if (setup->wValue == USB_DEVICE_TEST_MODE) + ptc = setup->wIndex >> 8; + else if (gadget_is_otg(&udc->gadget)) { + if (setup->bRequest == + USB_DEVICE_B_HNP_ENABLE) + udc->gadget.b_hnp_enable = 1; + else if (setup->bRequest == + USB_DEVICE_A_HNP_SUPPORT) + udc->gadget.a_hnp_support = 1; + else if (setup->bRequest == + USB_DEVICE_A_ALT_HNP_SUPPORT) + udc->gadget.a_alt_hnp_support = 1; + } + rc = 0; + } else + break; + + if (rc == 0) { + if (ep0_prime_status(udc, EP_DIR_IN)) + ep0stall(udc); + } + if (ptc) { + u32 tmp; + + mdelay(10); + fsl_platform_set_test_mode(udc->pdata, ptc); + tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16); + fsl_writel(tmp, &dr_regs->portsc1); + printk(KERN_INFO "udc: switch to test mode 0x%x.\n", ptc); + } + + return; + } + + default: + break; + } + + /* Requests handled by gadget */ + if (wLength) { + /* Data phase from gadget, status phase from udc */ + udc->ep0_dir = (setup->bRequestType & USB_DIR_IN) + ? USB_DIR_IN : USB_DIR_OUT; + spin_unlock(&udc->lock); + if (udc->driver->setup(&udc->gadget, + &udc->local_setup_buff) < 0) { + /* cancel status phase */ + udc_reset_ep_queue(udc, 0); + ep0stall(udc); + } + } else { + /* No data phase, IN status from gadget */ + udc->ep0_dir = USB_DIR_IN; + spin_unlock(&udc->lock); + if (udc->driver->setup(&udc->gadget, + &udc->local_setup_buff) < 0) + ep0stall(udc); + } + spin_lock(&udc->lock); +} + +/* Process request for Data or Status phase of ep0 + * prime status phase if needed */ +static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0, + struct fsl_req *req) +{ + if (udc->usb_state == USB_STATE_ADDRESS) { + /* Set the new address */ + u32 new_address = (u32) udc->device_address; + fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS, + &dr_regs->deviceaddr); + } + + done(ep0, req, 0); +} + +/* Tripwire mechanism to ensure a setup packet payload is extracted without + * being corrupted by another incoming setup packet */ +static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr) +{ + u32 temp; + struct ep_queue_head *qh; + struct fsl_usb2_platform_data *pdata = udc->pdata; + + qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT]; + + /* Clear bit in ENDPTSETUPSTAT */ + temp = fsl_readl(&dr_regs->endptsetupstat); + fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat); + + /* while a hazard exists when setup package arrives */ + do { + /* Set Setup Tripwire */ + temp = fsl_readl(&dr_regs->usbcmd); + fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd); + + /* Copy the setup packet to local buffer */ + if (pdata->le_setup_buf) { + u32 *p = (u32 *)buffer_ptr; + u32 *s = (u32 *)qh->setup_buffer; + + /* Convert little endian setup buffer to CPU endian */ + *p++ = le32_to_cpu(*s++); + *p = le32_to_cpu(*s); + } else { + memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8); + } + } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW)); + + /* Clear Setup Tripwire */ + temp = fsl_readl(&dr_regs->usbcmd); + fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd); +} + +static void iram_process_ep_complete(struct fsl_req *curr_req, + int cur_transfer) +{ + char *buf; + u32 len; + int in = ep_is_in(curr_req->ep); + + if (in) + buf = (char *)udc_controller->iram_buffer_v[1]; + else + buf = (char *)udc_controller->iram_buffer_v[0]; + + if (curr_req->cur->next_td_ptr == cpu_to_hc32(DTD_NEXT_TERMINATE) + || (cur_transfer < g_iram_size) + || (curr_req->req.length == curr_req->req.actual)) + curr_req->last_one = 1; + + if (curr_req->last_one) { + /* the last transfer */ + if (!in) { + memcpy(curr_req->req.buf + curr_req->buffer_offset, buf, + cur_transfer); + } + if (curr_req->tail->next_td_ptr != + cpu_to_hc32(DTD_NEXT_TERMINATE)) { + /* have next request,queue it */ + struct fsl_req *next_req; + next_req = + list_entry(curr_req->queue.next, + struct fsl_req, queue); + if (in) + memcpy(buf, next_req->req.buf, + min(g_iram_size, next_req->req.length)); + update_qh(next_req); + } + curr_req->req.dma = curr_req->oridma; + } else { + /* queue next dtd */ + /* because had next dtd, so should finish */ + /* tranferring g_iram_size data */ + curr_req->buffer_offset += g_iram_size; + /* pervious set stop bit,now clear it */ + curr_req->cur->next_td_ptr &= ~cpu_to_hc32(DTD_NEXT_TERMINATE); + curr_req->cur = curr_req->cur->next_td_virt; + if (in) { + len = + min(curr_req->req.length - curr_req->buffer_offset, + g_iram_size); + memcpy(buf, curr_req->req.buf + curr_req->buffer_offset, + len); + } else { + memcpy(curr_req->req.buf + curr_req->buffer_offset - + g_iram_size, buf, g_iram_size); + } + update_qh(curr_req); + } +} + +/* process-ep_req(): free the completed Tds for this req */ +static int process_ep_req(struct fsl_udc *udc, int pipe, + struct fsl_req *curr_req) +{ + struct ep_td_struct *curr_td; + int td_complete, actual, remaining_length, j, tmp; + int status = 0; + int errors = 0; + struct ep_queue_head *curr_qh = &udc->ep_qh[pipe]; + int direction = pipe % 2; + int total = 0, real_len; + + curr_td = curr_req->head; + td_complete = 0; + actual = curr_req->req.length; + real_len = curr_req->req.length; + + for (j = 0; j < curr_req->dtd_count; j++) { + remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts) + & DTD_PACKET_SIZE) + >> DTD_LENGTH_BIT_POS; + if (NEED_IRAM(curr_req->ep)) { + if (real_len >= g_iram_size) { + actual = g_iram_size; + real_len -= g_iram_size; + } else { /* the last packet */ + actual = real_len; + curr_req->last_one = 1; + } + } + actual -= remaining_length; + total += actual; + + errors = hc32_to_cpu(curr_td->size_ioc_sts) & DTD_ERROR_MASK; + if (errors) { + if (errors & DTD_STATUS_HALTED) { + ERR("dTD error %08x QH=%d\n", errors, pipe); + /* Clear the errors and Halt condition */ + tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts); + tmp &= ~errors; + curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp); + status = -EPIPE; + /* FIXME: continue with next queued TD? */ + + break; + } + if (errors & DTD_STATUS_DATA_BUFF_ERR) { + VDBG("Transfer overflow"); + status = -EPROTO; + break; + } else if (errors & DTD_STATUS_TRANSACTION_ERR) { + VDBG("ISO error"); + status = -EILSEQ; + break; + } else + ERR("Unknown error has occured (0x%x)!\r\n", + errors); + + } else if (hc32_to_cpu(curr_td->size_ioc_sts) + & DTD_STATUS_ACTIVE) { + VDBG("Request not complete"); + status = REQ_UNCOMPLETE; + return status; + } else if (remaining_length) { + if (direction) { + VDBG("Transmit dTD remaining length not zero"); + status = -EPROTO; + break; + } else { + td_complete++; + break; + } + } else { + td_complete++; + VDBG("dTD transmitted successful "); + } + if (NEED_IRAM(curr_req->ep)) + if (curr_td-> + next_td_ptr & cpu_to_hc32(DTD_NEXT_TERMINATE)) + break; + if (j != curr_req->dtd_count - 1) + curr_td = (struct ep_td_struct *)curr_td->next_td_virt; + } + + if (status) + return status; + curr_req->req.actual = total; + if (NEED_IRAM(curr_req->ep)) + iram_process_ep_complete(curr_req, actual); + return 0; +} + +/* Process a DTD completion interrupt */ +static void dtd_complete_irq(struct fsl_udc *udc) +{ + u32 bit_pos; + int i, ep_num, direction, bit_mask, status; + struct fsl_ep *curr_ep; + struct fsl_req *curr_req, *temp_req; + + /* Clear the bits in the register */ + bit_pos = fsl_readl(&dr_regs->endptcomplete); + fsl_writel(bit_pos, &dr_regs->endptcomplete); + + if (!bit_pos) + return; + + for (i = 0; i < udc->max_ep * 2; i++) { + ep_num = i >> 1; + direction = i % 2; + + bit_mask = 1 << (ep_num + 16 * direction); + + if (!(bit_pos & bit_mask)) + continue; + + curr_ep = get_ep_by_pipe(udc, i); + + /* If the ep is configured */ + if (curr_ep->name == NULL) { + INFO("Invalid EP?"); + continue; + } + + /* process the req queue until an uncomplete request */ + list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue, + queue) { + status = process_ep_req(udc, i, curr_req); + + VDBG("status of process_ep_req= %d, ep = %d", + status, ep_num); + if (status == REQ_UNCOMPLETE) + break; + /* write back status to req */ + curr_req->req.status = status; + + if (ep_num == 0) { + ep0_req_complete(udc, curr_ep, curr_req); + break; + } else { + if (NEED_IRAM(curr_ep)) { + if (curr_req->last_one) + done(curr_ep, curr_req, status); + /* only check the 1th req */ + break; + } else + done(curr_ep, curr_req, status); + } + } + dump_ep_queue(curr_ep); + } +} + +static void fsl_udc_speed_update(struct fsl_udc *udc) +{ + u32 speed = 0; + u32 loop = 0; + + /* Wait for port reset finished */ + while ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) + && (loop++ < 1000)) + ; + + speed = (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SPEED_MASK); + switch (speed) { + case PORTSCX_PORT_SPEED_HIGH: + udc->gadget.speed = USB_SPEED_HIGH; + break; + case PORTSCX_PORT_SPEED_FULL: + udc->gadget.speed = USB_SPEED_FULL; + break; + case PORTSCX_PORT_SPEED_LOW: + udc->gadget.speed = USB_SPEED_LOW; + break; + default: + udc->gadget.speed = USB_SPEED_UNKNOWN; + break; + } +} + +/* Process a port change interrupt */ +static void port_change_irq(struct fsl_udc *udc) +{ + if (udc->bus_reset) + udc->bus_reset = 0; + + /* Update port speed */ + fsl_udc_speed_update(udc); + + /* Update USB state */ + if (!udc->resume_state) + udc->usb_state = USB_STATE_DEFAULT; +} + +/* Process suspend interrupt */ +static void suspend_irq(struct fsl_udc *udc) +{ + u32 otgsc = 0; + + pr_debug("%s\n", __func__); + + udc->resume_state = udc->usb_state; + udc->usb_state = USB_STATE_SUSPENDED; + + /* Set discharge vbus */ + otgsc = fsl_readl(&dr_regs->otgsc); + otgsc &= ~(OTGSC_INTSTS_MASK); + otgsc |= OTGSC_CTRL_VBUS_DISCHARGE; + fsl_writel(otgsc, &dr_regs->otgsc); + + /* discharge in work queue */ + cancel_delayed_work(&udc->gadget_delay_work); + schedule_delayed_work(&udc->gadget_delay_work, msecs_to_jiffies(20)); + + /* report suspend to the driver, serial.c does not support this */ + if (udc->driver->suspend) + udc->driver->suspend(&udc->gadget); +} + +static void bus_resume(struct fsl_udc *udc) +{ + udc->usb_state = udc->resume_state; + udc->resume_state = 0; + + /* report resume to the driver, serial.c does not support this */ + if (udc->driver->resume) + udc->driver->resume(&udc->gadget); +} + +/* Clear up all ep queues */ +static int reset_queues(struct fsl_udc *udc) +{ + u8 pipe; + + for (pipe = 0; pipe < udc->max_pipes; pipe++) + udc_reset_ep_queue(udc, pipe); + + /* report disconnect; the driver is already quiesced */ + udc->driver->disconnect(&udc->gadget); + + return 0; +} + +/* Process reset interrupt */ +static void reset_irq(struct fsl_udc *udc) +{ + u32 temp; + + /* Clear the device address */ + temp = fsl_readl(&dr_regs->deviceaddr); + fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr); + + udc->device_address = 0; + + /* Clear usb state */ + udc->resume_state = 0; + udc->ep0_dir = 0; + udc->remote_wakeup = 0; /* default to 0 on reset */ + udc->gadget.b_hnp_enable = 0; + udc->gadget.a_hnp_support = 0; + udc->gadget.a_alt_hnp_support = 0; + + /* Clear all the setup token semaphores */ + temp = fsl_readl(&dr_regs->endptsetupstat); + fsl_writel(temp, &dr_regs->endptsetupstat); + + /* Clear all the endpoint complete status bits */ + temp = fsl_readl(&dr_regs->endptcomplete); + fsl_writel(temp, &dr_regs->endptcomplete); + + /* Write 1s to the flush register */ + fsl_writel(0xffffffff, &dr_regs->endptflush); + + /* Bus is reseting */ + udc->bus_reset = 1; + /* Reset all the queues, include XD, dTD, EP queue + * head and TR Queue */ + reset_queues(udc); + udc->usb_state = USB_STATE_DEFAULT; +} + +static void fsl_gadget_event(struct work_struct *work) +{ + struct fsl_udc *udc = udc_controller; + unsigned long flags; + + spin_lock_irqsave(&udc->lock, flags); + /* update port status */ + fsl_udc_speed_update(udc); + spin_unlock_irqrestore(&udc->lock, flags); + + /* close dr controller clock */ + dr_clk_gate(false); +} + +static void fsl_gadget_delay_event(struct work_struct *work) +{ + u32 otgsc = 0; + + dr_clk_gate(true); + otgsc = fsl_readl(&dr_regs->otgsc); + /* clear vbus discharge */ + if (otgsc & OTGSC_CTRL_VBUS_DISCHARGE) { + otgsc &= ~(OTGSC_INTSTS_MASK | OTGSC_CTRL_VBUS_DISCHARGE); + fsl_writel(otgsc, &dr_regs->otgsc); + } + dr_clk_gate(false); +} + +/* if wakup udc, return true; else return false*/ +bool try_wake_up_udc(struct fsl_udc *udc) +{ + struct fsl_usb2_platform_data *pdata; + u32 irq_src; + + pdata = udc->pdata; + + /* check if Vbus change irq */ + irq_src = fsl_readl(&dr_regs->otgsc) & (~OTGSC_ID_CHANGE_IRQ_STS); + if (irq_src & OTGSC_B_SESSION_VALID_IRQ_STS) { + u32 tmp; + fsl_writel(irq_src, &dr_regs->otgsc); + /* only handle device interrupt event */ + if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) + return false; + + tmp = fsl_readl(&dr_regs->usbcmd); + /* check BSV bit to see if fall or rise */ + if (irq_src & OTGSC_B_SESSION_VALID) { + if (udc->suspended) /*let the system pm resume the udc */ + return true; + udc->stopped = 0; + fsl_writel(tmp | USB_CMD_RUN_STOP, &dr_regs->usbcmd); + printk(KERN_DEBUG "%s: udc out low power mode\n", __func__); + } else { + if (udc->driver) + udc->driver->disconnect(&udc->gadget); + fsl_writel(tmp & ~USB_CMD_RUN_STOP, &dr_regs->usbcmd); + udc->stopped = 1; + /* enable wake up */ + dr_wake_up_enable(udc, true); + /* close USB PHY clock */ + dr_phy_low_power_mode(udc, true); + schedule_work(&udc->gadget_work); + printk(KERN_DEBUG "%s: udc enter low power mode\n", __func__); + return false; + } + } + + return true; +} +/* + * USB device controller interrupt handler + */ +static irqreturn_t fsl_udc_irq(int irq, void *_udc) +{ + struct fsl_udc *udc = _udc; + u32 irq_src; + irqreturn_t status = IRQ_NONE; + unsigned long flags; + struct fsl_usb2_platform_data *pdata = udc->pdata; + + if (pdata->irq_delay) + return status; + + spin_lock_irqsave(&udc->lock, flags); + + if (try_wake_up_udc(udc) == false) { + goto irq_end; + } +#ifdef CONFIG_USB_OTG + /* if no gadget register in this driver, we need do noting */ + if (udc->transceiver->gadget == NULL) { + goto irq_end; + } + /* only handle device interrupt event */ + if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) { + goto irq_end; + } +#endif + irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr); + /* Clear notification bits */ + fsl_writel(irq_src, &dr_regs->usbsts); + + VDBG("0x%x\n", irq_src); + + /* Need to resume? */ + if (udc->usb_state == USB_STATE_SUSPENDED) + if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0) + bus_resume(udc); + + /* USB Interrupt */ + if (irq_src & USB_STS_INT) { + VDBG("Packet int"); + /* Setup package, we only support ep0 as control ep */ + if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) { + tripwire_handler(udc, 0, + (u8 *) (&udc->local_setup_buff)); + setup_received_irq(udc, &udc->local_setup_buff); + status = IRQ_HANDLED; + } + + /* completion of dtd */ + if (fsl_readl(&dr_regs->endptcomplete)) { + dtd_complete_irq(udc); + status = IRQ_HANDLED; + } + } + + /* SOF (for ISO transfer) */ + if (irq_src & USB_STS_SOF) { + status = IRQ_HANDLED; + } + + /* Port Change */ + if (irq_src & USB_STS_PORT_CHANGE) { + port_change_irq(udc); + status = IRQ_HANDLED; + } + + /* Reset Received */ + if (irq_src & USB_STS_RESET) { + VDBG("reset int"); + reset_irq(udc); + status = IRQ_HANDLED; + } + + /* Sleep Enable (Suspend) */ + if (irq_src & USB_STS_SUSPEND) { + VDBG("suspend int"); + suspend_irq(udc); + status = IRQ_HANDLED; + } + + if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) { + VDBG("Error IRQ %x ", irq_src); + } + +irq_end: + spin_unlock_irqrestore(&udc->lock, flags); + return status; +} + +/*----------------------------------------------------------------* + * Hook to gadget drivers + * Called by initialization code of gadget drivers +*----------------------------------------------------------------*/ +int usb_gadget_register_driver(struct usb_gadget_driver *driver) +{ + int retval = -ENODEV; + unsigned long flags = 0; + + if (!udc_controller) + return -ENODEV; + + if (!driver || (driver->speed != USB_SPEED_FULL + && driver->speed != USB_SPEED_HIGH) + || !driver->bind || !driver->disconnect + || !driver->setup) + return -EINVAL; + + if (udc_controller->driver) + return -EBUSY; + + /* lock is needed but whether should use this lock or another */ + spin_lock_irqsave(&udc_controller->lock, flags); + + driver->driver.bus = 0; + udc_controller->pdata->port_enables = 1; + /* hook up the driver */ + udc_controller->driver = driver; + udc_controller->gadget.dev.driver = &driver->driver; + spin_unlock_irqrestore(&udc_controller->lock, flags); + dr_clk_gate(true); + /* It doesn't need to switch usb from low power mode to normal mode + * at otg mode + */ + if (!udc_controller->transceiver) + dr_phy_low_power_mode(udc_controller, false); + + /* bind udc driver to gadget driver */ + retval = driver->bind(&udc_controller->gadget); + if (retval) { + VDBG("bind to %s --> %d", driver->driver.name, retval); + udc_controller->gadget.dev.driver = 0; + udc_controller->driver = 0; + dr_clk_gate(false); + goto out; + } + + if (udc_controller->transceiver) { + /* Suspend the controller until OTG enable it */ + udc_controller->suspended = 1;/* let the otg resume it */ + printk(KERN_DEBUG "Suspend udc for OTG auto detect\n"); + dr_wake_up_enable(udc_controller, true); + dr_clk_gate(false); + /* export udc suspend/resume call to OTG */ + udc_controller->gadget.dev.driver->suspend = (dev_sus)fsl_udc_suspend; + udc_controller->gadget.dev.driver->resume = (dev_res)fsl_udc_resume; + + /* connect to bus through transceiver */ + retval = otg_set_peripheral(udc_controller->transceiver, + &udc_controller->gadget); + if (retval < 0) { + ERR("can't bind to transceiver\n"); + driver->unbind(&udc_controller->gadget); + udc_controller->gadget.dev.driver = 0; + udc_controller->driver = 0; + return retval; + } + } else { + /* Enable DR IRQ reg and Set usbcmd reg Run bit */ + dr_controller_run(udc_controller); + if (udc_controller->stopped) + dr_clk_gate(false); + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_dir = 0; + } + printk(KERN_INFO "%s: bind to driver %s \n", + udc_controller->gadget.name, driver->driver.name); + +out: + if (retval) { + printk(KERN_DEBUG "retval %d \n", retval); + udc_controller->pdata->port_enables = 0; + } + return retval; +} +EXPORT_SYMBOL(usb_gadget_register_driver); + +/* Disconnect from gadget driver */ +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) +{ + struct fsl_ep *loop_ep; + unsigned long flags; + + if (!udc_controller) + return -ENODEV; + + if (!driver || driver != udc_controller->driver || !driver->unbind) + return -EINVAL; + + if (udc_controller->stopped) + dr_clk_gate(true); + + if (udc_controller->transceiver) + (void)otg_set_peripheral(udc_controller->transceiver, 0); + + /* stop DR, disable intr */ + dr_controller_stop(udc_controller); + + udc_controller->pdata->port_enables = 0; + /* in fact, no needed */ + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_dir = 0; + + /* stand operation */ + spin_lock_irqsave(&udc_controller->lock, flags); + udc_controller->gadget.speed = USB_SPEED_UNKNOWN; + nuke(&udc_controller->eps[0], -ESHUTDOWN); + list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list, + ep.ep_list) + nuke(loop_ep, -ESHUTDOWN); + spin_unlock_irqrestore(&udc_controller->lock, flags); + + /* disconnect gadget before unbinding */ + driver->disconnect(&udc_controller->gadget); + + /* unbind gadget and unhook driver. */ + driver->unbind(&udc_controller->gadget); + udc_controller->gadget.dev.driver = 0; + udc_controller->driver = 0; + + if (udc_controller->gadget.is_otg) { + dr_wake_up_enable(udc_controller, true); + } + + dr_phy_low_power_mode(udc_controller, true); + + printk(KERN_INFO "unregistered gadget driver '%s'\r\n", + driver->driver.name); + return 0; +} +EXPORT_SYMBOL(usb_gadget_unregister_driver); + +/*------------------------------------------------------------------------- + PROC File System Support +-------------------------------------------------------------------------*/ +#ifdef CONFIG_USB_GADGET_DEBUG_FILES + +#include + +static const char proc_filename[] = "driver/fsl_usb2_udc"; + +static int fsl_proc_read(char *page, char **start, off_t off, int count, + int *eof, void *_dev) +{ + char *buf = page; + char *next = buf; + unsigned size = count; + unsigned long flags; + int t, i; + u32 tmp_reg; + struct fsl_ep *ep = NULL; + struct fsl_req *req; + struct fsl_usb2_platform_data *pdata; + + struct fsl_udc *udc = udc_controller; + pdata = udc->pdata; + if (off != 0) + return 0; + + dr_clk_gate(true); + spin_lock_irqsave(&udc->lock, flags); + + /* ------basic driver infomation ---- */ + t = scnprintf(next, size, + DRIVER_DESC "\n" + "%s version: %s\n" + "Gadget driver: %s\n\n", + driver_name, DRIVER_VERSION, + udc->driver ? udc->driver->driver.name : "(none)"); + size -= t; + next += t; + + /* ------ DR Registers ----- */ + tmp_reg = fsl_readl(&dr_regs->usbcmd); + t = scnprintf(next, size, + "USBCMD reg:\n" + "SetupTW: %d\n" + "Run/Stop: %s\n\n", + (tmp_reg & USB_CMD_SUTW) ? 1 : 0, + (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop"); + size -= t; + next += t; + + tmp_reg = fsl_readl(&dr_regs->usbsts); + t = scnprintf(next, size, + "USB Status Reg:\n" + "Dr Suspend: %d" "Reset Received: %d" "System Error: %s" + "USB Error Interrupt: %s\n\n", + (tmp_reg & USB_STS_SUSPEND) ? 1 : 0, + (tmp_reg & USB_STS_RESET) ? 1 : 0, + (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal", + (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err"); + size -= t; + next += t; + + tmp_reg = fsl_readl(&dr_regs->usbintr); + t = scnprintf(next, size, + "USB Intrrupt Enable Reg:\n" + "Sleep Enable: %d" "SOF Received Enable: %d" + "Reset Enable: %d\n" + "System Error Enable: %d" + "Port Change Dectected Enable: %d\n" + "USB Error Intr Enable: %d" "USB Intr Enable: %d\n\n", + (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0, + (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0, + (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0, + (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0, + (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0, + (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0, + (tmp_reg & USB_INTR_INT_EN) ? 1 : 0); + size -= t; + next += t; + + tmp_reg = fsl_readl(&dr_regs->frindex); + t = scnprintf(next, size, + "USB Frame Index Reg:" "Frame Number is 0x%x\n\n", + (tmp_reg & USB_FRINDEX_MASKS)); + size -= t; + next += t; + + tmp_reg = fsl_readl(&dr_regs->deviceaddr); + t = scnprintf(next, size, + "USB Device Address Reg:" "Device Addr is 0x%x\n\n", + (tmp_reg & USB_DEVICE_ADDRESS_MASK)); + size -= t; + next += t; + + tmp_reg = fsl_readl(&dr_regs->endpointlistaddr); + t = scnprintf(next, size, + "USB Endpoint List Address Reg:" + "Device Addr is 0x%x\n\n", + (tmp_reg & USB_EP_LIST_ADDRESS_MASK)); + size -= t; + next += t; + + tmp_reg = fsl_readl(&dr_regs->portsc1); + t = scnprintf(next, size, + "USB Port Status&Control Reg:\n" + "Port Transceiver Type : %s" "Port Speed: %s \n" + "PHY Low Power Suspend: %s" "Port Reset: %s" + "Port Suspend Mode: %s \n" "Over-current Change: %s" + "Port Enable/Disable Change: %s\n" + "Port Enabled/Disabled: %s" + "Current Connect Status: %s\n\n", ({ + char *s; + switch (tmp_reg & PORTSCX_PTS_FSLS) { + case PORTSCX_PTS_UTMI: + s = "UTMI"; break; + case PORTSCX_PTS_ULPI: + s = "ULPI "; break; + case PORTSCX_PTS_FSLS: + s = "FS/LS Serial"; break; + default: + s = "None"; break; + } + s; }), ({ + char *s; + switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) { + case PORTSCX_PORT_SPEED_FULL: + s = "Full Speed"; break; + case PORTSCX_PORT_SPEED_LOW: + s = "Low Speed"; break; + case PORTSCX_PORT_SPEED_HIGH: + s = "High Speed"; break; + default: + s = "Undefined"; break; + } + s; + }), + (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ? + "Normal PHY mode" : "Low power mode", + (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" : + "Not in Reset", + (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in", + (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" : + "No", + (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" : + "Not change", + (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" : + "Not correct", + (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ? + "Attached" : "Not-Att"); + size -= t; + next += t; + + tmp_reg = fsl_readl(&dr_regs->usbmode); + t = scnprintf(next, size, + "USB Mode Reg:" "Controller Mode is : %s\n\n", ({ + char *s; + switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) { + case USB_MODE_CTRL_MODE_IDLE: + s = "Idle"; break; + case USB_MODE_CTRL_MODE_DEVICE: + s = "Device Controller"; break; + case USB_MODE_CTRL_MODE_HOST: + s = "Host Controller"; break; + default: + s = "None"; break; + } + s; + })); + size -= t; + next += t; + + tmp_reg = fsl_readl(&dr_regs->endptsetupstat); + t = scnprintf(next, size, + "Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n", + (tmp_reg & EP_SETUP_STATUS_MASK)); + size -= t; + next += t; + + for (i = 0; i < udc->max_ep / 2; i++) { + tmp_reg = fsl_readl(&dr_regs->endptctrl[i]); + t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n", + i, tmp_reg); + size -= t; + next += t; + } + tmp_reg = fsl_readl(&dr_regs->endpointprime); + t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n", tmp_reg); + size -= t; + next += t; + + if (pdata->have_sysif_regs) { + tmp_reg = usb_sys_regs->snoop1; + t = scnprintf(next, size, "\nSnoop1 Reg = [0x%x]\n\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = usb_sys_regs->control; + t = scnprintf(next, size, "General Control Reg = [0x%x]\n\n", + tmp_reg); + size -= t; + next += t; + } + + /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */ + ep = &udc->eps[0]; + t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n", + ep->ep.name, ep_maxpacket(ep), ep_index(ep)); + size -= t; + next += t; + + if (list_empty(&ep->queue)) { + t = scnprintf(next, size, "its req queue is empty\n\n"); + size -= t; + next += t; + } else { + list_for_each_entry(req, &ep->queue, queue) { + t = scnprintf(next, size, + "req %p actual 0x%x length 0x%x buf %p\n", + &req->req, req->req.actual, + req->req.length, req->req.buf); + size -= t; + next += t; + } + } + /* other gadget->eplist ep */ + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { + if (ep->desc) { + t = scnprintf(next, size, + "\nFor %s Maxpkt is 0x%x " + "index is 0x%x\n", + ep->ep.name, ep_maxpacket(ep), + ep_index(ep)); + size -= t; + next += t; + + if (list_empty(&ep->queue)) { + t = scnprintf(next, size, + "its req queue is empty\n\n"); + size -= t; + next += t; + } else { + list_for_each_entry(req, &ep->queue, queue) { + t = scnprintf(next, size, + "req %p actual 0x%x length" + "0x%x buf %p\n", + &req->req, req->req.actual, + req->req.length, req->req.buf); + size -= t; + next += t; + } /* end for each_entry of ep req */ + } /* end for else */ + } /* end for if(ep->queue) */ + } /* end (ep->desc) */ + + spin_unlock_irqrestore(&udc->lock, flags); + dr_clk_gate(false); + + *eof = 1; + return count - size; +} + +#define create_proc_file() create_proc_read_entry(proc_filename, \ + 0, NULL, fsl_proc_read, NULL) + +#define remove_proc_file() remove_proc_entry(proc_filename, NULL) + +#else /* !CONFIG_USB_GADGET_DEBUG_FILES */ + +#define create_proc_file() do {} while (0) +#define remove_proc_file() do {} while (0) + +#endif /* CONFIG_USB_GADGET_DEBUG_FILES */ + +/*-------------------------------------------------------------------------*/ + +/* Release udc structures */ +static void fsl_udc_release(struct device *dev) +{ + complete(udc_controller->done); + dma_free_coherent(dev, udc_controller->ep_qh_size, + udc_controller->ep_qh, udc_controller->ep_qh_dma); + kfree(udc_controller); +} + +/****************************************************************** + Internal structure setup functions +*******************************************************************/ +/*------------------------------------------------------------------ + * init resource for globle controller + * Return the udc handle on success or NULL on failure + ------------------------------------------------------------------*/ +static int __init struct_udc_setup(struct fsl_udc *udc, + struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata; + size_t size; + + pdata = pdev->dev.platform_data; + udc->phy_mode = pdata->phy_mode; + + udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL); + if (!udc->eps) { + ERR("malloc fsl_ep failed\n"); + return -1; + } + + /* initialized QHs, take care of alignment */ + size = udc->max_ep * sizeof(struct ep_queue_head); + if (size < QH_ALIGNMENT) + size = QH_ALIGNMENT; + else if ((size % QH_ALIGNMENT) != 0) { + size += QH_ALIGNMENT + 1; + size &= ~(QH_ALIGNMENT - 1); + } + udc->ep_qh = dma_alloc_coherent(&pdev->dev, size, + &udc->ep_qh_dma, GFP_KERNEL); + if (!udc->ep_qh) { + ERR("malloc QHs for udc failed\n"); + kfree(udc->eps); + return -1; + } + + udc->ep_qh_size = size; + + /* Initialize ep0 status request structure */ + /* FIXME: fsl_alloc_request() ignores ep argument */ + udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL), + struct fsl_req, req); + /* allocate a small amount of memory to get valid address */ + udc->status_req->req.buf = kmalloc(8, GFP_KERNEL); + udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf); + /* Initialize ep0 data request structure */ + udc->data_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL), + struct fsl_req, req); + udc->data_req->req.buf = kmalloc(8, GFP_KERNEL); + udc->data_req->req.dma = virt_to_phys(udc->data_req->req.buf); + + udc->resume_state = USB_STATE_NOTATTACHED; + udc->usb_state = USB_STATE_POWERED; + udc->ep0_dir = 0; + udc->remote_wakeup = 0; /* default to 0 on reset */ + spin_lock_init(&udc->lock); + + return 0; +} + +/*---------------------------------------------------------------- + * Setup the fsl_ep struct for eps + * Link fsl_ep->ep to gadget->ep_list + * ep0out is not used so do nothing here + * ep0in should be taken care + *--------------------------------------------------------------*/ +static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index, + char *name, int link) +{ + struct fsl_ep *ep = &udc->eps[index]; + + ep->udc = udc; + strcpy(ep->name, name); + ep->ep.name = ep->name; + + ep->ep.ops = &fsl_ep_ops; + ep->stopped = 0; + + /* for ep0: maxP defined in desc + * for other eps, maxP is set by epautoconfig() called by gadget layer + */ + ep->ep.maxpacket = (unsigned short) ~0; + + /* the queue lists any req for this ep */ + INIT_LIST_HEAD(&ep->queue); + + /* gagdet.ep_list used for ep_autoconfig so no ep0 */ + if (link) + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); + ep->gadget = &udc->gadget; + ep->qh = &udc->ep_qh[index]; + + return 0; +} + +/* Driver probe function + * all intialization operations implemented here except enabling usb_intr reg + * board setup should have been done in the platform code + */ +static int __init fsl_udc_probe(struct platform_device *pdev) +{ + struct resource *res; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + int ret = -ENODEV; + unsigned int i; + u32 dccparams; + + udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL); + if (udc_controller == NULL) { + ERR("malloc udc failed\n"); + return -ENOMEM; + } + udc_controller->pdata = pdata; + +#ifdef CONFIG_USB_OTG + /* Memory and interrupt resources will be passed from OTG */ + udc_controller->transceiver = otg_get_transceiver(); + if (!udc_controller->transceiver) { + printk(KERN_ERR "Can't find OTG driver!\n"); + ret = -ENODEV; + goto err1a; + } + udc_controller->gadget.is_otg = 1; +#endif + + if ((pdev->dev.parent) && + (to_platform_device(pdev->dev.parent)->resource)) { + pdev->resource = + to_platform_device(pdev->dev.parent)->resource; + pdev->num_resources = + to_platform_device(pdev->dev.parent)->num_resources; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENXIO; + goto err1a; + } + +#ifndef CONFIG_USB_OTG + if (!request_mem_region(res->start, resource_size(res), + driver_name)) { + ERR("request mem region for %s failed \n", pdev->name); + ret = -EBUSY; + goto err1a; + } +#endif + + dr_regs = ioremap(res->start, resource_size(res)); + if (!dr_regs) { + ret = -ENOMEM; + goto err1; + } + pdata->regs = (void *)dr_regs; + /* + * do platform specific init: check the clock, grab/config pins, etc. + */ + if (pdata->platform_init && pdata->platform_init(pdev)) { + ret = -ENODEV; + goto err2a; + } + + /* Due to mx35/mx25's phy's bug */ + reset_phy(); + + if (pdata->have_sysif_regs) + usb_sys_regs = (struct usb_sys_interface *) + ((u32)dr_regs + USB_DR_SYS_OFFSET); + + /* Read Device Controller Capability Parameters register */ + dccparams = fsl_readl(&dr_regs->dccparams); + if (!(dccparams & DCCPARAMS_DC)) { + ERR("This SOC doesn't support device role\n"); + ret = -ENODEV; + goto err2; + } + /* Get max device endpoints */ + /* DEN is bidirectional ep number, max_ep doubles the number */ + udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2; + + udc_controller->irq = platform_get_irq(pdev, 0); + if (!udc_controller->irq) { + ret = -ENODEV; + goto err2; + } + + ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED, + driver_name, udc_controller); + if (ret != 0) { + ERR("cannot request irq %d err %d \n", + udc_controller->irq, ret); + goto err2; + } + + /* Initialize the udc structure including QH member and other member */ + if (struct_udc_setup(udc_controller, pdev)) { + ERR("Can't initialize udc data structure\n"); + ret = -ENOMEM; + goto err3; + } + + if (!udc_controller->transceiver) { + /* initialize usb hw reg except for regs for EP, + * leave usbintr reg untouched */ + dr_controller_setup(udc_controller); + } + + /* Setup gadget structure */ + udc_controller->gadget.ops = &fsl_gadget_ops; + udc_controller->gadget.is_dualspeed = 1; + udc_controller->gadget.ep0 = &udc_controller->eps[0].ep; + INIT_LIST_HEAD(&udc_controller->gadget.ep_list); + udc_controller->gadget.speed = USB_SPEED_UNKNOWN; + udc_controller->gadget.name = driver_name; + + /* Setup gadget.dev and register with kernel */ + dev_set_name(&udc_controller->gadget.dev, "gadget"); + udc_controller->gadget.dev.release = fsl_udc_release; + udc_controller->gadget.dev.parent = &pdev->dev; + ret = device_register(&udc_controller->gadget.dev); + if (ret < 0) + goto err3; + + /* setup QH and epctrl for ep0 */ + ep0_setup(udc_controller); + + /* setup udc->eps[] for ep0 */ + struct_ep_setup(udc_controller, 0, "ep0", 0); + /* for ep0: the desc defined here; + * for other eps, gadget layer called ep_enable with defined desc + */ + udc_controller->eps[0].desc = &fsl_ep0_desc; + udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD; + + /* setup the udc->eps[] for non-control endpoints and link + * to gadget.ep_list */ + for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) { + char name[14]; + + sprintf(name, "ep%dout", i); + struct_ep_setup(udc_controller, i * 2, name, 1); + sprintf(name, "ep%din", i); + struct_ep_setup(udc_controller, i * 2 + 1, name, 1); + } + + /* use dma_pool for TD management */ + udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev, + sizeof(struct ep_td_struct), + DTD_ALIGNMENT, UDC_DMA_BOUNDARY); + if (udc_controller->td_pool == NULL) { + ret = -ENOMEM; + goto err4; + } + if (g_iram_size) { + g_iram_addr = iram_alloc(USB_IRAM_SIZE, &g_iram_base); + for (i = 0; i < IRAM_PPH_NTD; i++) { + udc_controller->iram_buffer[i] = + g_iram_base + i * g_iram_size; + udc_controller->iram_buffer_v[i] = + g_iram_addr + i * g_iram_size; + } + } + + INIT_WORK(&udc_controller->gadget_work, fsl_gadget_event); + INIT_DELAYED_WORK(&udc_controller->gadget_delay_work, + fsl_gadget_delay_event); +#ifdef POSTPONE_FREE_LAST_DTD + last_free_td = NULL; +#endif + + /* disable all INTR */ +#ifndef CONFIG_USB_OTG + fsl_writel(0, &dr_regs->usbintr); + dr_wake_up_enable(udc_controller, false); +#else + dr_wake_up_enable(udc_controller, true); +#endif + +/* + * As mx25/mx35 does not implement clk_gate, should not let phy to low + * power mode due to IC bug + */ +#if !(defined CONFIG_ARCH_MX35 || defined CONFIG_ARCH_MX25) +{ + dr_phy_low_power_mode(udc_controller, true); +} +#endif + udc_controller->stopped = 1; + + /* let the gadget register function open the clk */ + dr_clk_gate(false); + + create_proc_file(); + return 0; + +err4: + device_unregister(&udc_controller->gadget.dev); +err3: + free_irq(udc_controller->irq, udc_controller); +err2: + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); +err2a: + iounmap((u8 __iomem *)dr_regs); +err1: + if (!udc_controller->transceiver) + release_mem_region(res->start, resource_size(res)); +err1a: + kfree(udc_controller); + udc_controller = NULL; + return ret; +} + +/* Driver removal function + * Free resources and finish pending transactions + */ +static int __exit fsl_udc_remove(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + + DECLARE_COMPLETION(done); + + if (!udc_controller) + return -ENODEV; + udc_controller->done = &done; + /* open USB PHY clock */ + if (udc_controller->stopped) + dr_clk_gate(true); + + /* DR has been stopped in usb_gadget_unregister_driver() */ + remove_proc_file(); + + /* Free allocated memory */ + if (g_iram_size) + iram_free(g_iram_base, IRAM_PPH_NTD * g_iram_size); + kfree(udc_controller->status_req->req.buf); + kfree(udc_controller->status_req); + kfree(udc_controller->data_req->req.buf); + kfree(udc_controller->data_req); + kfree(udc_controller->eps); +#ifdef POSTPONE_FREE_LAST_DTD + if (last_free_td != NULL) + dma_pool_free(udc_controller->td_pool, last_free_td, + last_free_td->td_dma); +#endif + dma_pool_destroy(udc_controller->td_pool); + free_irq(udc_controller->irq, udc_controller); + iounmap((u8 __iomem *)dr_regs); + +#ifndef CONFIG_USB_OTG +{ + struct resource *res; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); +} +#endif + + device_unregister(&udc_controller->gadget.dev); + /* free udc --wait for the release() finished */ + wait_for_completion(&done); + + /* + * do platform specific un-initialization: + * release iomux pins, etc. + */ + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); + + if (udc_controller->stopped) + dr_clk_gate(false); + return 0; +} + +static bool udc_can_wakeup_system(void) +{ + struct fsl_usb2_platform_data *pdata = udc_controller->pdata; + + if (pdata->operating_mode == FSL_USB2_DR_OTG) + if (device_may_wakeup(udc_controller->transceiver->dev)) + return true; + else + return false; + else + if (device_may_wakeup(udc_controller->gadget.dev.parent)) + return true; + else + return false; +} + +static int udc_suspend(struct fsl_udc *udc) +{ + u32 mode, usbcmd; + + /* + * When it is the PM suspend routine and the device has no + * abilities to wakeup system, it should not set wakeup enable. + * Otherwise, the system will wakeup even the user only wants to + * charge using usb + */ + printk(KERN_DEBUG "udc suspend begins\n"); + if (udc_controller->gadget.dev.parent->power.status + == DPM_SUSPENDING) { + if (!udc_can_wakeup_system()) + dr_wake_up_enable(udc, false); + else + dr_wake_up_enable(udc, true); + } + mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK; + usbcmd = fsl_readl(&dr_regs->usbcmd); + + /* + * If the controller is already stopped, then this must be a + * PM suspend. Remember this fact, so that we will leave the + * controller stopped at PM resume time. + */ + if (udc->suspended) { + printk(KERN_DEBUG "gadget already suspended, leaving early\n"); + goto out; + } + + if (mode != USB_MODE_CTRL_MODE_DEVICE) { + printk(KERN_DEBUG "gadget not in device mode, leaving early\n"); + goto out; + } + + /* Comment udc_wait_b_session_low, uncomment it at below two + * situations: + * 1. the user wants to debug some problems about vbus + * 2. the vbus discharges very slow at user's board + */ + + /* For some buggy hardware designs, see comment of this function for detail */ + /* udc_wait_b_session_low(); */ + + udc->stopped = 1; + + /* stop the controller */ + usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP; + fsl_writel(usbcmd, &dr_regs->usbcmd); + + dr_phy_low_power_mode(udc, true); + printk(KERN_DEBUG "USB Gadget suspend ends\n"); +out: + udc->suspended++; + if (udc->suspended > 2) + printk(KERN_ERR "ERROR: suspended times > 2\n"); + + return 0; +} + +/*----------------------------------------------------------------- + * Modify Power management attributes + * Used by OTG statemachine to disable gadget temporarily + -----------------------------------------------------------------*/ +static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state) +{ + int ret; +#ifdef CONFIG_USB_OTG + if (udc_controller->transceiver->gadget == NULL) + return 0; +#endif + if (udc_controller->stopped) + dr_clk_gate(true); + if (((!(udc_controller->gadget.is_otg)) || + (fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) && + (udc_controller->usb_state > USB_STATE_POWERED) && + (udc_controller->usb_state < USB_STATE_SUSPENDED)) { + return -EBUSY;/* keep the clk on */ + } else + ret = udc_suspend(udc_controller); + dr_clk_gate(false); + + return ret; +} + +/*----------------------------------------------------------------- + * Invoked on USB resume. May be called in_interrupt. + * Here we start the DR controller and enable the irq + *-----------------------------------------------------------------*/ +static int fsl_udc_resume(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = udc_controller->pdata; + struct fsl_usb2_wakeup_platform_data *wake_up_pdata = pdata->wakeup_pdata; + printk(KERN_DEBUG "USB Gadget resume begins\n"); + + if (pdev->dev.power.status == DPM_RESUMING) { + printk(KERN_DEBUG "%s, Wait for wakeup thread finishes\n", __func__); + wait_event_interruptible(wake_up_pdata->wq, !wake_up_pdata->usb_wakeup_is_pending); + } + +#ifdef CONFIG_USB_OTG + if (udc_controller->transceiver->gadget == NULL) { + return 0; + } +#endif + mutex_lock(&udc_resume_mutex); + + pr_debug("%s(): stopped %d suspended %d\n", __func__, + udc_controller->stopped, udc_controller->suspended); + /* Do noop if the udc is already at resume state */ + if (udc_controller->suspended == 0) { + mutex_unlock(&udc_resume_mutex); + return 0; + } + + /* + * If the controller was stopped at suspend time, then + * don't resume it now. + */ + + if (udc_controller->suspended > 1) { + printk(KERN_DEBUG "gadget was already stopped, leaving early\n"); + if (udc_controller->stopped) { + dr_clk_gate(true); + } + goto end; + } + + /* Enable DR irq reg and set controller Run */ + if (udc_controller->stopped) { + /* the clock is already on at usb wakeup routine */ + if (pdata->lowpower) + dr_clk_gate(true); + dr_wake_up_enable(udc_controller, false); + dr_phy_low_power_mode(udc_controller, false); + usb_debounce_id_vbus(); + /* if in host mode, we need to do nothing */ + if ((fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID) == 0) { + dr_phy_low_power_mode(udc_controller, true); + dr_wake_up_enable(udc_controller, true); + goto end; + } + dr_controller_setup(udc_controller); + dr_controller_run(udc_controller); + } + udc_controller->usb_state = USB_STATE_ATTACHED; + udc_controller->ep0_dir = 0; + +end: + /* if udc is resume by otg id change and no device + * connecting to the otg, otg will enter low power mode*/ + if (udc_controller->stopped) { + /* + * If it is PM resume routine, the udc is at low power mode, + * and the udc has no abilities to wakeup system, it should + * set the abilities to wakeup itself. Otherwise, the usb + * subsystem will not leave from low power mode. + */ + if (!udc_can_wakeup_system() && + udc_controller->gadget.dev.parent->power.status + == DPM_RESUMING){ + dr_wake_up_enable(udc_controller, true); + } + + dr_clk_gate(false); + } + --udc_controller->suspended; + mutex_unlock(&udc_resume_mutex); + printk(KERN_DEBUG "USB Gadget resume ends\n"); + return 0; +} + +/*------------------------------------------------------------------------- + Register entry point for the peripheral controller driver +--------------------------------------------------------------------------*/ + +static struct platform_driver udc_driver = { + .remove = __exit_p(fsl_udc_remove), + /* these suspend and resume are not usb suspend and resume */ + .suspend = fsl_udc_suspend, + .resume = fsl_udc_resume, + .probe = fsl_udc_probe, + .driver = { + .name = driver_name, + .owner = THIS_MODULE, + }, +}; + +static int __init udc_init(void) +{ + printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION); + return platform_driver_register(&udc_driver); +} +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + fs_initcall(udc_init); +#else + module_init(udc_init); +#endif +static void __exit udc_exit(void) +{ + platform_driver_unregister(&udc_driver); + printk(KERN_INFO "%s unregistered \n", driver_desc); +} + +module_exit(udc_exit); + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_LICENSE("GPL"); diff --git a/drivers/usb/gadget/arcotg_udc.h b/drivers/usb/gadget/arcotg_udc.h new file mode 100644 index 000000000000..bc88afb360c3 --- /dev/null +++ b/drivers/usb/gadget/arcotg_udc.h @@ -0,0 +1,712 @@ +/* + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file arcotg_udc.h + * @brief Freescale USB device/endpoint management registers + * @ingroup USB + */ + +#ifndef __ARCOTG_UDC_H +#define __ARCOTG_UDC_H + +#define TRUE 1 +#define FALSE 0 + +#define MSC_BULK_CB_WRAP_LEN 31 +#define USE_MSC_WR(len) false + +/* Iram patch */ +#ifdef CONFIG_USB_STATIC_IRAM_PPH +/* size of 1 qTD's buffer,one is for BULK IN and other is BULK OUT */ +#define USB_IRAM_SIZE SZ_8K +#define IRAM_TD_PPH_SIZE (USB_IRAM_SIZE / 2) +#define IRAM_PPH_NTD 2 /* number of TDs in IRAM */ +#else +#define USB_IRAM_SIZE 0 +#define IRAM_TD_PPH_SIZE 0 +#define IRAM_PPH_NTD 0 +#endif + +#define NEED_IRAM(ep) ((g_iram_size) && \ + ((ep)->desc->bmAttributes == USB_ENDPOINT_XFER_BULK)) + +#ifdef CONFIG_ARCH_MX5 +#define POSTPONE_FREE_LAST_DTD +#else +#undef POSTPONE_FREE_LAST_DTD +#endif + +/* ### define USB registers here + */ +#define USB_MAX_ENDPOINTS 8 +#define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2) +#define USB_MAX_CTRL_PAYLOAD 64 +#define USB_DR_SYS_OFFSET 0x400 + +#define USB_DR_OFFSET 0x3100 + +struct usb_dr_device { + /* Capability register */ + u32 id; + u32 res1[35]; + u32 sbuscfg; /* sbuscfg ahb burst */ + u32 res11[27]; + u16 caplength; /* Capability Register Length */ + u16 hciversion; /* Host Controller Interface Version */ + u32 hcsparams; /* Host Controller Structual Parameters */ + u32 hccparams; /* Host Controller Capability Parameters */ + u32 res2[5]; + u32 dciversion; /* Device Controller Interface Version */ + u32 dccparams; /* Device Controller Capability Parameters */ + u32 res3[6]; + /* Operation register */ + u32 usbcmd; /* USB Command Register */ + u32 usbsts; /* USB Status Register */ + u32 usbintr; /* USB Interrupt Enable Register */ + u32 frindex; /* Frame Index Register */ + u32 res4; + u32 deviceaddr; /* Device Address */ + u32 endpointlistaddr; /* Endpoint List Address Register */ + u32 res5; + u32 burstsize; /* Master Interface Data Burst Size Register */ + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ + u32 res6[6]; + u32 configflag; /* Configure Flag Register */ + u32 portsc1; /* Port 1 Status and Control Register */ + u32 res7[7]; + u32 otgsc; /* On-The-Go Status and Control */ + u32 usbmode; /* USB Mode Register */ + u32 endptsetupstat; /* Endpoint Setup Status Register */ + u32 endpointprime; /* Endpoint Initialization Register */ + u32 endptflush; /* Endpoint Flush Register */ + u32 endptstatus; /* Endpoint Status Register */ + u32 endptcomplete; /* Endpoint Complete Register */ + u32 endptctrl[8 * 2]; /* Endpoint Control Registers */ + u32 res8[256]; +#ifdef CONFIG_ARCH_MX5 + u32 res9[128]; /* i.MX51 start from 0x800 */ +#endif + u32 usbctrl; + u32 otgmirror; + u32 phyctrl0; + u32 phyctrl1; + u32 ctrl1; + u32 uh2ctrl; +}; + + /* non-EHCI USB system interface registers (Big Endian) */ +struct usb_sys_interface { + u32 snoop1; + u32 snoop2; + u32 age_cnt_thresh; /* Age Count Threshold Register */ + u32 pri_ctrl; /* Priority Control Register */ + u32 si_ctrl; /* System Interface Control Register */ + u8 res[236]; + u32 control; /* General Purpose Control Register */ +}; + +/* ep0 transfer state */ +#define WAIT_FOR_SETUP 0 +#define DATA_STATE_XMIT 1 +#define DATA_STATE_NEED_ZLP 2 +#define WAIT_FOR_OUT_STATUS 3 +#define DATA_STATE_RECV 4 + +/* Device Controller Capability Parameter register */ +#define DCCPARAMS_DC 0x00000080 +#define DCCPARAMS_DEN_MASK 0x0000001f + +/* Frame Index Register Bit Masks */ +#define USB_FRINDEX_MASKS (0x3fff) +/* USB CMD Register Bit Masks */ +#define USB_CMD_RUN_STOP (0x00000001) +#define USB_CMD_CTRL_RESET (0x00000002) +#define USB_CMD_PERIODIC_SCHEDULE_EN (0x00000010) +#define USB_CMD_ASYNC_SCHEDULE_EN (0x00000020) +#define USB_CMD_INT_AA_DOORBELL (0x00000040) +#define USB_CMD_ASP (0x00000300) +#define USB_CMD_ASYNC_SCH_PARK_EN (0x00000800) +#define USB_CMD_SUTW (0x00002000) +#define USB_CMD_ATDTW (0x00004000) +#define USB_CMD_ITC (0x00FF0000) + +/* bit 15,3,2 are frame list size */ +#define USB_CMD_FRAME_SIZE_1024 (0x00000000) +#define USB_CMD_FRAME_SIZE_512 (0x00000004) +#define USB_CMD_FRAME_SIZE_256 (0x00000008) +#define USB_CMD_FRAME_SIZE_128 (0x0000000C) +#define USB_CMD_FRAME_SIZE_64 (0x00008000) +#define USB_CMD_FRAME_SIZE_32 (0x00008004) +#define USB_CMD_FRAME_SIZE_16 (0x00008008) +#define USB_CMD_FRAME_SIZE_8 (0x0000800C) + +/* bit 9-8 are async schedule park mode count */ +#define USB_CMD_ASP_00 (0x00000000) +#define USB_CMD_ASP_01 (0x00000100) +#define USB_CMD_ASP_10 (0x00000200) +#define USB_CMD_ASP_11 (0x00000300) +#define USB_CMD_ASP_BIT_POS (8) + +/* bit 23-16 are interrupt threshold control */ +#define USB_CMD_ITC_NO_THRESHOLD (0x00000000) +#define USB_CMD_ITC_1_MICRO_FRM (0x00010000) +#define USB_CMD_ITC_2_MICRO_FRM (0x00020000) +#define USB_CMD_ITC_4_MICRO_FRM (0x00040000) +#define USB_CMD_ITC_8_MICRO_FRM (0x00080000) +#define USB_CMD_ITC_16_MICRO_FRM (0x00100000) +#define USB_CMD_ITC_32_MICRO_FRM (0x00200000) +#define USB_CMD_ITC_64_MICRO_FRM (0x00400000) +#define USB_CMD_ITC_BIT_POS (16) + +/* USB STS Register Bit Masks */ +#define USB_STS_INT (0x00000001) +#define USB_STS_ERR (0x00000002) +#define USB_STS_PORT_CHANGE (0x00000004) +#define USB_STS_FRM_LST_ROLL (0x00000008) +#define USB_STS_SYS_ERR (0x00000010) +#define USB_STS_IAA (0x00000020) +#define USB_STS_RESET (0x00000040) +#define USB_STS_SOF (0x00000080) +#define USB_STS_SUSPEND (0x00000100) +#define USB_STS_HC_HALTED (0x00001000) +#define USB_STS_RCL (0x00002000) +#define USB_STS_PERIODIC_SCHEDULE (0x00004000) +#define USB_STS_ASYNC_SCHEDULE (0x00008000) + +/* USB INTR Register Bit Masks */ +#define USB_INTR_INT_EN (0x00000001) +#define USB_INTR_ERR_INT_EN (0x00000002) +#define USB_INTR_PTC_DETECT_EN (0x00000004) +#define USB_INTR_FRM_LST_ROLL_EN (0x00000008) +#define USB_INTR_SYS_ERR_EN (0x00000010) +#define USB_INTR_ASYN_ADV_EN (0x00000020) +#define USB_INTR_RESET_EN (0x00000040) +#define USB_INTR_SOF_EN (0x00000080) +#define USB_INTR_DEVICE_SUSPEND (0x00000100) + +/* Device Address bit masks */ +#define USB_DEVICE_ADDRESS_MASK (0xFE000000) +#define USB_DEVICE_ADDRESS_BIT_POS (25) + +/* endpoint list address bit masks */ +#define USB_EP_LIST_ADDRESS_MASK (0xfffff800) + +/* PORTSCX Register Bit Masks */ +#define PORTSCX_CURRENT_CONNECT_STATUS (0x00000001) +#define PORTSCX_CONNECT_STATUS_CHANGE (0x00000002) +#define PORTSCX_PORT_ENABLE (0x00000004) +#define PORTSCX_PORT_EN_DIS_CHANGE (0x00000008) +#define PORTSCX_OVER_CURRENT_ACT (0x00000010) +#define PORTSCX_OVER_CURRENT_CHG (0x00000020) +#define PORTSCX_PORT_FORCE_RESUME (0x00000040) +#define PORTSCX_PORT_SUSPEND (0x00000080) +#define PORTSCX_PORT_RESET (0x00000100) +#define PORTSCX_LINE_STATUS_BITS (0x00000C00) +#define PORTSCX_PORT_POWER (0x00001000) +#define PORTSCX_PORT_INDICTOR_CTRL (0x0000C000) +#define PORTSCX_PORT_TEST_CTRL (0x000F0000) +#define PORTSCX_WAKE_ON_CONNECT_EN (0x00100000) +#define PORTSCX_WAKE_ON_CONNECT_DIS (0x00200000) +#define PORTSCX_WAKE_ON_OVER_CURRENT (0x00400000) +#define PORTSCX_PHY_LOW_POWER_SPD (0x00800000) +#define PORTSCX_PORT_FORCE_FULL_SPEED (0x01000000) +#define PORTSCX_PORT_SPEED_MASK (0x0C000000) +#define PORTSCX_PORT_WIDTH (0x10000000) +#define PORTSCX_PHY_TYPE_SEL (0xC0000000) + +/* bit 11-10 are line status */ +#define PORTSCX_LINE_STATUS_SE0 (0x00000000) +#define PORTSCX_LINE_STATUS_JSTATE (0x00000400) +#define PORTSCX_LINE_STATUS_KSTATE (0x00000800) +#define PORTSCX_LINE_STATUS_UNDEF (0x00000C00) +#define PORTSCX_LINE_STATUS_BIT_POS (10) + +/* bit 15-14 are port indicator control */ +#define PORTSCX_PIC_OFF (0x00000000) +#define PORTSCX_PIC_AMBER (0x00004000) +#define PORTSCX_PIC_GREEN (0x00008000) +#define PORTSCX_PIC_UNDEF (0x0000C000) +#define PORTSCX_PIC_BIT_POS (14) + +/* bit 19-16 are port test control */ +#define PORTSCX_PTC_DISABLE (0x00000000) +#define PORTSCX_PTC_JSTATE (0x00010000) +#define PORTSCX_PTC_KSTATE (0x00020000) +#define PORTSCX_PTC_SEQNAK (0x00030000) +#define PORTSCX_PTC_PACKET (0x00040000) +#define PORTSCX_PTC_FORCE_EN (0x00050000) +#define PORTSCX_PTC_BIT_POS (16) + +/* bit 27-26 are port speed */ +#define PORTSCX_PORT_SPEED_FULL (0x00000000) +#define PORTSCX_PORT_SPEED_LOW (0x04000000) +#define PORTSCX_PORT_SPEED_HIGH (0x08000000) +#define PORTSCX_PORT_SPEED_UNDEF (0x0C000000) +#define PORTSCX_SPEED_BIT_POS (26) + +/* OTGSC Register Bit Masks */ +#define OTGSC_ID_CHANGE_IRQ_STS (1 << 16) +#define OTGSC_B_SESSION_VALID_IRQ_EN (1 << 27) +#define OTGSC_B_SESSION_VALID_IRQ_STS (1 << 19) +#define OTGSC_B_SESSION_VALID (1 << 11) + +/* bit 28 is parallel transceiver width for UTMI interface */ +#define PORTSCX_PTW (0x10000000) +#define PORTSCX_PTW_8BIT (0x00000000) +#define PORTSCX_PTW_16BIT (0x10000000) + +/* bit 31-30 are port transceiver select */ +#define PORTSCX_PTS_UTMI (0x00000000) +#define PORTSCX_PTS_ULPI (0x80000000) +#define PORTSCX_PTS_FSLS (0xC0000000) +#define PORTSCX_PTS_BIT_POS (30) + +/* USB MODE Register Bit Masks */ +#define USB_MODE_CTRL_MODE_IDLE (0x00000000) +#define USB_MODE_CTRL_MODE_DEVICE (0x00000002) +#define USB_MODE_CTRL_MODE_HOST (0x00000003) +#define USB_MODE_CTRL_MODE_MASK 0x00000003 +#define USB_MODE_CTRL_MODE_RSV (0x00000001) +#define USB_MODE_ES 0x00000004 /* (big) Endian Sel */ +#define USB_MODE_SETUP_LOCK_OFF (0x00000008) +#define USB_MODE_STREAM_DISABLE (0x00000010) +/* Endpoint Flush Register */ +#define EPFLUSH_TX_OFFSET (0x00010000) +#define EPFLUSH_RX_OFFSET (0x00000000) + +/* Endpoint Setup Status bit masks */ +#define EP_SETUP_STATUS_MASK (0x0000003F) +#define EP_SETUP_STATUS_EP0 (0x00000001) + +/* ENDPOINTCTRLx Register Bit Masks */ +#define EPCTRL_TX_ENABLE (0x00800000) +#define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000) /* Not EP0 */ +#define EPCTRL_TX_DATA_TOGGLE_INH (0x00200000) /* Not EP0 */ +#define EPCTRL_TX_TYPE (0x000C0000) +#define EPCTRL_TX_DATA_SOURCE (0x00020000) /* Not EP0 */ +#define EPCTRL_TX_EP_STALL (0x00010000) +#define EPCTRL_RX_ENABLE (0x00000080) +#define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040) /* Not EP0 */ +#define EPCTRL_RX_DATA_TOGGLE_INH (0x00000020) /* Not EP0 */ +#define EPCTRL_RX_TYPE (0x0000000C) +#define EPCTRL_RX_DATA_SINK (0x00000002) /* Not EP0 */ +#define EPCTRL_RX_EP_STALL (0x00000001) + +/* bit 19-18 and 3-2 are endpoint type */ +#define EPCTRL_EP_TYPE_CONTROL (0) +#define EPCTRL_EP_TYPE_ISO (1) +#define EPCTRL_EP_TYPE_BULK (2) +#define EPCTRL_EP_TYPE_INTERRUPT (3) +#define EPCTRL_TX_EP_TYPE_SHIFT (18) +#define EPCTRL_RX_EP_TYPE_SHIFT (2) + +/* SNOOPn Register Bit Masks */ +#define SNOOP_ADDRESS_MASK (0xFFFFF000) +#define SNOOP_SIZE_ZERO (0x00) /* snooping disable */ +#define SNOOP_SIZE_4KB (0x0B) /* 4KB snoop size */ +#define SNOOP_SIZE_8KB (0x0C) +#define SNOOP_SIZE_16KB (0x0D) +#define SNOOP_SIZE_32KB (0x0E) +#define SNOOP_SIZE_64KB (0x0F) +#define SNOOP_SIZE_128KB (0x10) +#define SNOOP_SIZE_256KB (0x11) +#define SNOOP_SIZE_512KB (0x12) +#define SNOOP_SIZE_1MB (0x13) +#define SNOOP_SIZE_2MB (0x14) +#define SNOOP_SIZE_4MB (0x15) +#define SNOOP_SIZE_8MB (0x16) +#define SNOOP_SIZE_16MB (0x17) +#define SNOOP_SIZE_32MB (0x18) +#define SNOOP_SIZE_64MB (0x19) +#define SNOOP_SIZE_128MB (0x1A) +#define SNOOP_SIZE_256MB (0x1B) +#define SNOOP_SIZE_512MB (0x1C) +#define SNOOP_SIZE_1GB (0x1D) +#define SNOOP_SIZE_2GB (0x1E) /* 2GB snoop size */ + +/* pri_ctrl Register Bit Masks */ +#define PRI_CTRL_PRI_LVL1 (0x0000000C) +#define PRI_CTRL_PRI_LVL0 (0x00000003) + +/* si_ctrl Register Bit Masks */ +#define SI_CTRL_ERR_DISABLE (0x00000010) +#define SI_CTRL_IDRC_DISABLE (0x00000008) +#define SI_CTRL_RD_SAFE_EN (0x00000004) +#define SI_CTRL_RD_PREFETCH_DISABLE (0x00000002) +#define SI_CTRL_RD_PREFEFETCH_VAL (0x00000001) + +/* control Register Bit Masks */ +#define USB_CTRL_IOENB (0x00000004) +#define USB_CTRL_ULPI_INT0EN (0x00000001) +#define USB_CTRL_OTG_WUIR (0x80000000) +#define USB_CTRL_OTG_WUIE (0x08000000) +#define USB_CTRL_OTG_VWUE (0x00001000) +#define USB_CTRL_OTG_IWUE (0x00100000) + +/* PHY control0 Register Bit Masks */ +#define PHY_CTRL0_CONF2 (1 << 26) +#define PHY_CTRL0_USBEN (1 << 24) /* USB UTMI PHY Enable */ + +/* USB UH2 CTRL Register Bits */ +#define USB_UH2_OVBWK_EN (1 << 6) /* OTG VBUS Wakeup Enable */ +#define USB_UH2_OIDWK_EN (1 << 5) /* OTG ID Wakeup Enable */ +/*! + * Endpoint Queue Head data struct + * Rem: all the variables of qh are LittleEndian Mode + * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr + */ +struct ep_queue_head { + /*! + * Mult(31-30) , Zlt(29) , Max Pkt len and IOS(15) + */ + u32 max_pkt_length; + + /*! + * Current dTD Pointer(31-5) + */ + u32 curr_dtd_ptr; + + /*! + * Next dTD Pointer(31-5), T(0) + */ + u32 next_dtd_ptr; + + /*! + * Total bytes (30-16), IOC (15), MultO(11-10), STS (7-0) + */ + u32 size_ioc_int_sts; + + /*! + * Buffer pointer Page 0 (31-12) + */ + u32 buff_ptr0; + + /*! + * Buffer pointer Page 1 (31-12) + */ + u32 buff_ptr1; + + /*! + * Buffer pointer Page 2 (31-12) + */ + u32 buff_ptr2; + + /*! + * Buffer pointer Page 3 (31-12) + */ + u32 buff_ptr3; + + /*! + * Buffer pointer Page 4 (31-12) + */ + u32 buff_ptr4; + + /*! + * reserved field 1 + */ + u32 res1; + /*! + * Setup data 8 bytes + */ + u8 setup_buffer[8]; /* Setup data 8 bytes */ + + /*! + * reserved field 2,pad out to 64 bytes + */ + u32 res2[4]; +}; + +/* Endpoint Queue Head Bit Masks */ +#define EP_QUEUE_HEAD_MULT_POS (30) +#define EP_QUEUE_HEAD_ZLT_SEL (0x20000000) +#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS (16) +#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff) +#define EP_QUEUE_HEAD_IOS (0x00008000) +#define EP_QUEUE_HEAD_NEXT_TERMINATE (0x00000001) +#define EP_QUEUE_HEAD_IOC (0x00008000) +#define EP_QUEUE_HEAD_MULTO (0x00000C00) +#define EP_QUEUE_HEAD_STATUS_HALT (0x00000040) +#define EP_QUEUE_HEAD_STATUS_ACTIVE (0x00000080) +#define EP_QUEUE_CURRENT_OFFSET_MASK (0x00000FFF) +#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0 +#define EP_QUEUE_FRINDEX_MASK (0x000007FF) +#define EP_MAX_LENGTH_TRANSFER (0x4000) + +/*! + * Endpoint Transfer Descriptor data struct + * Rem: all the variables of td are LittleEndian Mode + * must be 32-byte aligned + */ +struct ep_td_struct { + /*! + * Next TD pointer(31-5), T(0) set indicate invalid + */ + u32 next_td_ptr; + + /*! + * Total bytes (30-16), IOC (15),MultO(11-10), STS (7-0) + */ + u32 size_ioc_sts; + + /*! + * Buffer pointer Page 0 + */ + u32 buff_ptr0; + + /*! + * Buffer pointer Page 1 + */ + u32 buff_ptr1; + + /*! + * Buffer pointer Page 2 + */ + u32 buff_ptr2; + + /*! + * Buffer pointer Page 3 + */ + u32 buff_ptr3; + + /*! + * Buffer pointer Page 4 + */ + u32 buff_ptr4; + + /*! + * dma address of this td + * */ + dma_addr_t td_dma; + + /*! + * virtual address of next td + * */ + struct ep_td_struct *next_td_virt; + + /*! + * make it an even 16 words + * */ + u32 res[7]; +}; + +/*! + * Endpoint Transfer Descriptor bit Masks + */ +#define DTD_NEXT_TERMINATE (0x00000001) +#define DTD_IOC (0x00008000) +#define DTD_STATUS_ACTIVE (0x00000080) +#define DTD_STATUS_HALTED (0x00000040) +#define DTD_STATUS_DATA_BUFF_ERR (0x00000020) +#define DTD_STATUS_TRANSACTION_ERR (0x00000008) +#define DTD_RESERVED_FIELDS (0x80007300) +#define DTD_ADDR_MASK 0xFFFFFFE0 +#define DTD_PACKET_SIZE (0x7FFF0000) +#define DTD_LENGTH_BIT_POS (16) +#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ + DTD_STATUS_DATA_BUFF_ERR | \ + DTD_STATUS_TRANSACTION_ERR) +/* Alignment requirements; must be a power of two */ +#define DTD_ALIGNMENT 0x20 +#define QH_ALIGNMENT 2048 + +/* Controller dma boundary */ +#define UDC_DMA_BOUNDARY 0x1000 + +/* -----------------------------------------------------------------------*/ +/* ##### enum data +*/ +typedef enum { + e_ULPI, + e_UTMI_8BIT, + e_UTMI_16BIT, + e_SERIAL +} e_PhyInterface; + +/*-------------------------------------------------------------------------*/ + +struct fsl_req { + struct usb_request req; + struct list_head queue; + /* ep_queue() func will add + a request->queue into a udc_ep->queue 'd tail */ + struct fsl_ep *ep; + unsigned mapped; + + struct ep_td_struct *head, *tail; /* For dTD List + this is a BigEndian Virtual addr */ + unsigned int dtd_count; + /* just for IRAM patch */ + dma_addr_t oridma; /* original dma */ + size_t buffer_offset; /* offset of user buffer */ + int last_one; /* mark if reach to last packet */ + struct ep_td_struct *cur; /* current tranfer dtd */ +}; + +#define REQ_UNCOMPLETE (1) + +struct fsl_ep { + struct usb_ep ep; + struct list_head queue; + struct fsl_udc *udc; + struct ep_queue_head *qh; + const struct usb_endpoint_descriptor *desc; + struct usb_gadget *gadget; + + char name[14]; + unsigned stopped:1; +}; + +#define EP_DIR_IN 1 +#define EP_DIR_OUT 0 + +struct fsl_udc { + struct usb_gadget gadget; + struct usb_gadget_driver *driver; + struct fsl_usb2_platform_data *pdata; + struct fsl_ep *eps; + unsigned int max_ep; + unsigned int irq; + + struct usb_ctrlrequest local_setup_buff; + spinlock_t lock; + u32 xcvr_type; + struct otg_transceiver *transceiver; + unsigned softconnect:1; + unsigned vbus_active:1; + unsigned remote_wakeup:1; + /* we must distinguish the stopped and suspended state, + * stopped means the udc enter lowpower mode, suspended + * means the udc is suspended by system pm or by otg + * switching to host mode.if the udc in suspended state + * it also in the stopped state, while if the udc in + * stopped state,it may not be in the suspended state*/ + unsigned stopped:1; + int suspended; + + struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */ + struct fsl_req *status_req; /* ep0 status request */ + struct fsl_req *data_req; /* ep0 data request */ + struct dma_pool *td_pool; /* dma pool for DTD */ + enum fsl_usb2_phy_modes phy_mode; + + size_t ep_qh_size; /* size after alignment adjustment*/ + dma_addr_t ep_qh_dma; /* dma address of QH */ + + u32 max_pipes; /* Device max pipes */ + u32 max_use_endpts; /* Max endpointes to be used */ + u32 bus_reset; /* Device is bus reseting */ + u32 resume_state; /* USB state to resume */ + u32 usb_state; /* USB current state */ + u32 usb_next_state; /* USB next state */ + u32 ep0_dir; /* Endpoint zero direction: can be + USB_DIR_IN or USB_DIR_OUT */ + u32 usb_sof_count; /* SOF count */ + u32 errors; /* USB ERRORs count */ + u8 device_address; /* Device USB address */ + + struct completion *done; /* to make sure release() is done */ + u32 iram_buffer[IRAM_PPH_NTD]; + void *iram_buffer_v[IRAM_PPH_NTD]; + struct work_struct gadget_work; + struct delayed_work gadget_delay_work; +}; + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \ + __func__, ## args) +#else +#define DBG(fmt, args...) do {} while (0) +#endif + +#if 0 +static void dump_msg(const char *label, const u8 * buf, unsigned int length) +{ + unsigned int start, num, i; + char line[52], *p; + + if (length >= 512) + return; + pr_debug("udc: %s, length %u:\n", label, length); + start = 0; + while (length > 0) { + num = min(length, 16u); + p = line; + for (i = 0; i < num; ++i) { + if (i == 8) + *p++ = ' '; + sprintf(p, " %02x", buf[i]); + p += 3; + } + *p = 0; + printk(KERN_DEBUG "%6x: %s\n", start, line); + buf += num; + start += num; + length -= num; + } +} +#endif + +#ifdef VERBOSE +#define VDBG DBG +#else +#define VDBG(stuff...) do {} while (0) +#endif + +#define ERR(stuff...) printk(KERN_ERR "udc: " stuff) +#define INFO(stuff...) printk(KERN_INFO "udc: " stuff) + +/*-------------------------------------------------------------------------*/ + +/* ### Add board specific defines here + */ + +/* + * ### pipe direction macro from device view + */ +#define USB_RECV (0) /* OUT EP */ +#define USB_SEND (1) /* IN EP */ + +/* + * ### internal used help routines. + */ +#define ep_index(EP) ((EP)->desc->bEndpointAddress&0xF) +#define ep_maxpacket(EP) ((EP)->ep.maxpacket) + +#define ep_is_in(EP) ((ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ + USB_DIR_IN) : ((EP)->desc->bEndpointAddress \ + & USB_DIR_IN) == USB_DIR_IN) + +#define get_ep_by_pipe(udc, pipe) ((pipe == 1) ? &udc->eps[0] : \ + &udc->eps[pipe]) +#define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \ + * 2 + ((windex & USB_DIR_IN) ? 1 : 0)) + +/* Bulk only class request */ +#define USB_BULK_RESET_REQUEST 0xff + +#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_STMP3XXX) || \ + defined(CONFIG_ARCH_MXS) +#include +#elif defined (CONFIG_PPC32) +#include +#endif + +#endif /* __ARCOTG_UDC_H */ diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c index b49d86e3e45b..526abbecc3ce 100644 --- a/drivers/usb/gadget/file_storage.c +++ b/drivers/usb/gadget/file_storage.c @@ -324,7 +324,11 @@ static struct { } mod_data = { // Default values .transport_parm = "BBB", .protocol_parm = "SCSI", +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + .removable = 1, +#else .removable = 0, +#endif .can_stall = 1, .cdrom = 0, .vendor = FSG_VENDOR_ID, @@ -477,8 +481,16 @@ struct fsg_dev { unsigned int nluns; struct fsg_lun *luns; struct fsg_lun *curlun; + +#ifdef CONFIG_FSL_UTP + void *utp; +#endif }; +#ifdef CONFIG_FSL_UTP +#include "fsl_updater.h" +#endif +static int do_set_interface(struct fsg_dev *fsg, int altsetting); typedef void (*fsg_routine_t)(struct fsg_dev *); static int exception_in_progress(struct fsg_dev *fsg) @@ -546,7 +558,11 @@ device_desc = { .iManufacturer = FSG_STRING_MANUFACTURER, .iProduct = FSG_STRING_PRODUCT, +#ifdef CONFIG_FSL_UTP + .iSerialNumber = 0, +#else .iSerialNumber = FSG_STRING_SERIAL, +#endif .bNumConfigurations = 1, }; @@ -653,6 +669,15 @@ static void fsg_disconnect(struct usb_gadget *gadget) struct fsg_dev *fsg = get_gadget_data(gadget); DBG(fsg, "disconnect or port reset\n"); + /* + * The disconnect exception will call do_set_config, and therefore will + * visit controller registers. However it is a delayed event, and will be + * handled at another process, so the controller maybe have already closed the + * usb clock. + */ + if (fsg->new_config) + do_set_interface(fsg, -1);/* disable the interface */ + raise_exception(fsg, FSG_STATE_DISCONNECT); } @@ -1610,6 +1635,13 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) } #endif +#ifdef CONFIG_FSL_UTP + if (utp_get_sense(fsg) == 0) { /* got the sense from the UTP */ + sd = UTP_CTX(fsg)->sd; + sdinfo = UTP_CTX(fsg)->sdinfo; + valid = 0; + } else +#endif if (!curlun) { // Unsupported LUNs are okay fsg->bad_lun_okay = 1; sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; @@ -1631,6 +1663,9 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) buf[7] = 18 - 8; // Additional sense length buf[12] = ASC(sd); buf[13] = ASCQ(sd); +#ifdef CONFIG_FSL_UTP + put_unaligned_be32(UTP_CTX(fsg)->sdinfo_h, &buf[8]); +#endif return 18; } @@ -2373,6 +2408,13 @@ static int do_scsi_command(struct fsg_dev *fsg) fsg->phase_error = 0; fsg->short_packet_received = 0; +#ifdef CONFIG_FSL_UTP + reply = utp_handle_message(fsg, fsg->cmnd, reply); + + if (reply != -EINVAL) + return reply; +#endif + down_read(&fsg->filesem); // We're using the backing file switch (fsg->cmnd[0]) { @@ -3065,10 +3107,12 @@ static int fsg_main_thread(void *fsg_) /* Allow the thread to be frozen */ set_freezable(); +#ifndef CONFIG_FSL_UTP /* Arrange for userspace references to be interpreted as kernel * pointers. That way we can pass a kernel pointer to a routine * that expects a __user pointer and it will work okay. */ set_fs(get_ds()); +#endif /* The main loop */ while (fsg->state != FSG_STATE_TERMINATED) { @@ -3190,6 +3234,9 @@ static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget) } set_gadget_data(gadget, NULL); +#ifdef CONFIG_FSL_UTP + utp_exit(fsg); +#endif } @@ -3224,6 +3271,17 @@ static int __init check_parameters(struct fsg_dev *fsg) prot = simple_strtol(mod_data.protocol_parm, NULL, 0); +#ifdef CONFIG_FSL_UTP + mod_data.can_stall = 0; + mod_data.removable = 1; + mod_data.nluns = 1; + mod_data.file[0] = NULL; + mod_data.vendor = 0x066F; + mod_data.product = 0x37FF; + pr_info("%s:UTP settings are in place now, overriding defaults\n", + __func__); +#endif + #ifdef CONFIG_USB_FILE_STORAGE_TEST if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) { ; // Use default setting @@ -3276,8 +3334,9 @@ static int __init check_parameters(struct fsg_dev *fsg) return 0; } - - +#ifdef CONFIG_FSL_UTP +#include "fsl_updater.c" +#endif static int __init fsg_bind(struct usb_gadget *gadget) { struct fsg_dev *fsg = the_fsg; @@ -3305,6 +3364,10 @@ static int __init fsg_bind(struct usb_gadget *gadget) } } +#ifdef CONFIG_FSL_UTP + utp_init(fsg); +#endif + /* Find out how many LUNs there should be */ i = mod_data.nluns; if (i == 0) @@ -3579,7 +3642,6 @@ static int __init fsg_init(void) { int rc; struct fsg_dev *fsg; - if ((rc = fsg_alloc()) != 0) return rc; fsg = the_fsg; @@ -3587,8 +3649,12 @@ static int __init fsg_init(void) kref_put(&fsg->ref, fsg_release); return rc; } -module_init(fsg_init); +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + fs_initcall(fsg_init); +#else + module_init(fsg_init); +#endif static void __exit fsg_cleanup(void) { diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c index 08a9a62a39e3..7d0e7fbceabf 100644 --- a/drivers/usb/gadget/fsl_udc_core.c +++ b/drivers/usb/gadget/fsl_udc_core.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2004-2010 Freescale Semicondutor, Inc. All rights reserved. * * Author: Li Yang * Jiang Bo @@ -2475,8 +2475,11 @@ static int __init udc_init(void) return platform_driver_probe(&udc_driver, fsl_udc_probe); } -module_init(udc_init); - +#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW + fs_initcall(udc_init); +#else + module_init(udc_init); +#endif static void __exit udc_exit(void) { platform_driver_unregister(&udc_driver); diff --git a/drivers/usb/gadget/fsl_updater.c b/drivers/usb/gadget/fsl_updater.c new file mode 100644 index 000000000000..cd8ba2480f6e --- /dev/null +++ b/drivers/usb/gadget/fsl_updater.c @@ -0,0 +1,586 @@ +/* + * Freescale UUT driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +static u64 get_be64(u8 *buf) +{ + return ((u64)get_unaligned_be32(buf) << 32) | + get_unaligned_be32(buf + 4); +} + +static int utp_init(struct fsg_dev *fsg) +{ + init_waitqueue_head(&utp_context.wq); + init_waitqueue_head(&utp_context.list_full_wq); + + INIT_LIST_HEAD(&utp_context.read); + INIT_LIST_HEAD(&utp_context.write); + mutex_init(&utp_context.lock); + + /* the max message is 64KB */ + utp_context.buffer = vmalloc(0x10000); + if (!utp_context.buffer) + return -EIO; + utp_context.utp_version = 0x1ull; + fsg->utp = &utp_context; + return misc_register(&utp_dev); +} + +static void utp_exit(struct fsg_dev *fsg) +{ + vfree(utp_context.buffer); + misc_deregister(&utp_dev); +} + +static struct utp_user_data *utp_user_data_alloc(size_t size) +{ + struct utp_user_data *uud; + + uud = kzalloc(size + sizeof(*uud), GFP_KERNEL); + if (!uud) + return uud; + uud->data.size = size + sizeof(uud->data); + INIT_LIST_HEAD(&uud->link); + return uud; +} + +static void utp_user_data_free(struct utp_user_data *uud) +{ + mutex_lock(&utp_context.lock); + list_del(&uud->link); + mutex_unlock(&utp_context.lock); + kfree(uud); +} + +/* Get the number of element for list */ +static u32 count_list(struct list_head *l) +{ + u32 count = 0; + struct list_head *tmp; + + list_for_each(tmp, l) { + count++; + } + + return count; +} +/* The routine will not go on if utp_context.queue is empty */ +#define WAIT_ACTIVITY(queue) \ + wait_event_interruptible(utp_context.wq, !list_empty(&utp_context.queue)) + +/* Called by userspace program (uuc) */ +static ssize_t utp_file_read(struct file *file, + char __user *buf, + size_t size, + loff_t *off) +{ + struct utp_user_data *uud; + size_t size_to_put; + int free = 0; + + WAIT_ACTIVITY(read); + + mutex_lock(&utp_context.lock); + uud = list_first_entry(&utp_context.read, struct utp_user_data, link); + mutex_unlock(&utp_context.lock); + size_to_put = uud->data.size; + + if (size >= size_to_put) + free = !0; + if (copy_to_user(buf, &uud->data, size_to_put)) + return -EACCES; + if (free) + utp_user_data_free(uud); + else { + pr_info("sizeof = %d, size = %d\n", + sizeof(uud->data), + uud->data.size); + + pr_err("Will not free utp_user_data, because buffer size = %d," + "need to put %d\n", size, size_to_put); + } + + /* + * The user program has already finished data process, + * go on getting data from the host + */ + wake_up(&utp_context.list_full_wq); + + return size_to_put; +} + +static ssize_t utp_file_write(struct file *file, const char __user *buf, + size_t size, loff_t *off) +{ + struct utp_user_data *uud; + + if (size < sizeof(uud->data)) + return -EINVAL; + uud = utp_user_data_alloc(size); + if (copy_from_user(&uud->data, buf, size)) + return -EACCES; + mutex_lock(&utp_context.lock); + list_add_tail(&uud->link, &utp_context.write); + /* Go on EXEC routine process */ + wake_up(&utp_context.wq); + mutex_unlock(&utp_context.lock); + return size; +} + +static int +utp_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int cpu_id = 0; + switch (cmd) { + case UTP_GET_CPU_ID: +/* Currently, it only supports below SoC for manufacture tool + * The naming rule + * 1. The numberic for SoC string + * 2. If there is next SoC version, and the corresponding utp + * operation will be differ, then, need to add '1' next to SoC + * name. Such as the next 50 SoC version is: cpu_is = 501 + */ +#ifdef CONFIG_ARCH_MXS + if (cpu_is_mx23()) + cpu_id = 23; + else if (cpu_is_mx28()) + cpu_id = 28; +#endif +#ifdef CONFIG_ARCH_MXC + if (cpu_is_mx25()) + cpu_id = 25; + else if (cpu_is_mx35()) + cpu_id = 35; + else if (cpu_is_mx51()) + cpu_id = 51; + else if (cpu_is_mx53()) + cpu_id = 53; + else if (cpu_is_mx50()) + cpu_id = 50; +#endif + return put_user(cpu_id, (int __user *)arg); + default: + return -ENOIOCTLCMD; + } +} + +/* Will be called when the host wants to get the sense data */ +static int utp_get_sense(struct fsg_dev *fsg) +{ + if (UTP_CTX(fsg)->processed == 0) + return -1; + + UTP_CTX(fsg)->processed = 0; + return 0; +} + +static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size) +{ + struct fsg_buffhd *bh; + int rc; + u32 amount_left; + unsigned int amount; + + /* Get the starting Logical Block Address and check that it's + * not too big */ + + amount_left = size; + if (unlikely(amount_left == 0)) + return -EIO; /* No default reply*/ + + pr_debug("%s: sending %d\n", __func__, size); + for (;;) { + /* Figure out how much we need to read: + * Try to read the remaining amount. + * But don't read more than the buffer size. + * And don't try to read past the end of the file. + * Finally, if we're not at a page boundary, don't read past + * the next page. + * If this means reading 0 then we were asked to read past + * the end of file. */ + amount = min((unsigned int) amount_left, mod_data.buflen); + + /* Wait for the next buffer to become available */ + bh = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + /* If we were asked to read past the end of file, + * end with an empty buffer. */ + if (amount == 0) { + bh->inreq->length = 0; + bh->state = BUF_STATE_FULL; + break; + } + + /* Perform the read */ + pr_info("Copied to %p, %d bytes started from %d\n", + bh->buf, amount, size - amount_left); + /* from upt buffer to file_storeage buffer */ + memcpy(bh->buf, data + size - amount_left, amount); + amount_left -= amount; + fsg->residue -= amount; + + bh->inreq->length = amount; + bh->state = BUF_STATE_FULL; + + /* Send this buffer and go read some more */ + bh->inreq->zero = 0; + + /* USB Physical transfer: Data from device to host */ + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + + fsg->next_buffhd_to_fill = bh->next; + + if (amount_left <= 0) + break; + } + + return size - amount_left; +} + +static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size) +{ + struct fsg_buffhd *bh; + int get_some_more; + u32 amount_left_to_req, amount_left_to_write; + unsigned int amount; + int rc; + loff_t offset; + + /* Carry out the file writes */ + get_some_more = 1; + amount_left_to_req = amount_left_to_write = size; + + if (unlikely(amount_left_to_write == 0)) + return -EIO; + + offset = 0; + while (amount_left_to_write > 0) { + + /* Queue a request for more data from the host */ + bh = fsg->next_buffhd_to_fill; + if (bh->state == BUF_STATE_EMPTY && get_some_more) { + + /* Figure out how much we want to get: + * Try to get the remaining amount. + * But don't get more than the buffer size. + * And don't try to go past the end of the file. + * If we're not at a page boundary, + * don't go past the next page. + * If this means getting 0, then we were asked + * to write past the end of file. + * Finally, round down to a block boundary. */ + amount = min(amount_left_to_req, mod_data.buflen); + + if (amount == 0) { + get_some_more = 0; + /* cry now */ + continue; + } + + /* Get the next buffer */ + amount_left_to_req -= amount; + if (amount_left_to_req == 0) + get_some_more = 0; + + /* amount is always divisible by 512, hence by + * the bulk-out maxpacket size */ + bh->outreq->length = bh->bulk_out_intended_length = + amount; + bh->outreq->short_not_ok = 1; + start_transfer(fsg, fsg->bulk_out, bh->outreq, + &bh->outreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; + continue; + } + + /* Write the received data to the backing file */ + bh = fsg->next_buffhd_to_drain; + if (bh->state == BUF_STATE_EMPTY && !get_some_more) + break; /* We stopped early */ + if (bh->state == BUF_STATE_FULL) { + smp_rmb(); + fsg->next_buffhd_to_drain = bh->next; + bh->state = BUF_STATE_EMPTY; + + /* Did something go wrong with the transfer? */ + if (bh->outreq->status != 0) + /* cry again, COMMUNICATION_FAILURE */ + break; + + amount = bh->outreq->actual; + + /* Perform the write */ + memcpy(data + offset, bh->buf, amount); + + offset += amount; + if (signal_pending(current)) + return -EINTR; /* Interrupted!*/ + amount_left_to_write -= amount; + fsg->residue -= amount; + + /* Did the host decide to stop early? */ + if (bh->outreq->actual != bh->outreq->length) { + fsg->short_packet_received = 1; + break; + } + continue; + } + + /* Wait for something to happen */ + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + return -EIO; +} + +static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply) +{ + UTP_CTX(fsg)->processed = true; + UTP_CTX(fsg)->sdinfo = reply & 0xFFFFFFFF; + UTP_CTX(fsg)->sdinfo_h = (reply >> 32) & 0xFFFFFFFF; + UTP_CTX(fsg)->sd = (UTP_SENSE_KEY << 16) | code; +} + +static void utp_poll(struct fsg_dev *fsg) +{ + struct utp_context *ctx = UTP_CTX(fsg); + struct utp_user_data *uud = NULL; + + mutex_lock(&ctx->lock); + if (!list_empty(&ctx->write)) + uud = list_first_entry(&ctx->write, struct utp_user_data, link); + mutex_unlock(&ctx->lock); + + if (uud) { + if (uud->data.flags & UTP_FLAG_STATUS) { + printk(KERN_WARNING "%s: exit with status %d\n", + __func__, uud->data.status); + UTP_SS_EXIT(fsg, uud->data.status); + } else { + pr_debug("%s: pass\n", __func__); + UTP_SS_PASS(fsg); + } + utp_user_data_free(uud); + } else { + pr_debug("%s: still busy...\n", __func__); + UTP_SS_BUSY(fsg, --ctx->counter); + } +} + +static int utp_exec(struct fsg_dev *fsg, + char *command, + int cmdsize, + unsigned long long payload) +{ + struct utp_user_data *uud = NULL, *uud2r; + struct utp_context *ctx = UTP_CTX(fsg); + + uud2r = utp_user_data_alloc(cmdsize + 1); + uud2r->data.flags = UTP_FLAG_COMMAND; + uud2r->data.payload = payload; + strncpy(uud2r->data.command, command, cmdsize); + + mutex_lock(&ctx->lock); + list_add_tail(&uud2r->link, &ctx->read); + mutex_unlock(&ctx->lock); + /* wake up the read routine */ + wake_up(&ctx->wq); + + if (command[0] == '!') /* there will be no response */ + return 0; + + /* + * the user program (uuc) will return utp_message + * and add list to write list + */ + WAIT_ACTIVITY(write); + + mutex_lock(&ctx->lock); + if (!list_empty(&ctx->write)) { + uud = list_first_entry(&ctx->write, struct utp_user_data, link); +#ifdef DEBUG + pr_info("UUD:\n\tFlags = %02X\n", uud->data.flags); + if (uud->data.flags & UTP_FLAG_DATA) { + pr_info("\tbufsize = %d\n", uud->data.bufsize); + print_hex_dump(KERN_DEBUG, "\t", DUMP_PREFIX_NONE, + 16, 2, uud->data.data, uud->data.bufsize, true); + } + if (uud->data.flags & UTP_FLAG_REPORT_BUSY) + pr_info("\tBUSY\n"); +#endif + } + mutex_unlock(&ctx->lock); + + if (uud->data.flags & UTP_FLAG_DATA) { + memcpy(ctx->buffer, uud->data.data, uud->data.bufsize); + UTP_SS_SIZE(fsg, uud->data.bufsize); + } else if (uud->data.flags & UTP_FLAG_REPORT_BUSY) { + ctx->counter = 0xFFFF; + UTP_SS_BUSY(fsg, ctx->counter); + } else if (uud->data.flags & UTP_FLAG_STATUS) { + printk(KERN_WARNING "%s: exit with status %d\n", __func__, + uud->data.status); + UTP_SS_EXIT(fsg, uud->data.status); + } else { + pr_debug("%s: pass\n", __func__); + UTP_SS_PASS(fsg); + } + utp_user_data_free(uud); + return 0; +} + +static int utp_send_status(struct fsg_dev *fsg) +{ + struct fsg_buffhd *bh; + u8 status = USB_STATUS_PASS; + struct bulk_cs_wrap *csw; + int rc; + + /* Wait for the next buffer to become available */ + bh = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + if (fsg->phase_error) { + DBG(fsg, "sending phase-error status\n"); + status = USB_STATUS_PHASE_ERROR; + + } else if ((UTP_CTX(fsg)->sd & 0xFFFF) != UTP_REPLY_PASS) { + status = USB_STATUS_FAIL; + } + + csw = bh->buf; + + /* Store and send the Bulk-only CSW */ + csw->Signature = __constant_cpu_to_le32(USB_BULK_CS_SIG); + csw->Tag = fsg->tag; + csw->Residue = cpu_to_le32(fsg->residue); + csw->Status = status; + + bh->inreq->length = USB_BULK_CS_WRAP_LEN; + bh->inreq->zero = 0; + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; + return 0; +} + +static int utp_handle_message(struct fsg_dev *fsg, + char *cdb_data, + int default_reply) +{ + struct utp_msg *m = (struct utp_msg *)cdb_data; + void *data = NULL; + int r; + struct utp_user_data *uud2r; + unsigned long long param; + unsigned long tag; + + if (m->f0 != 0xF0) + return default_reply; + + tag = get_unaligned_be32((void *)&m->utp_msg_tag); + param = get_be64((void *)&m->param); + pr_debug("Type 0x%x, tag 0x%08lx, param %llx\n", + m->utp_msg_type, tag, param); + + switch ((enum utp_msg_type)m->utp_msg_type) { + + case UTP_POLL: + if (get_be64((void *)&m->param) == 1) { + pr_debug("%s: version request\n", __func__); + UTP_SS_EXIT(fsg, UTP_CTX(fsg)->utp_version); + break; + } + utp_poll(fsg); + break; + case UTP_EXEC: + pr_debug("%s: EXEC\n", __func__); + data = kzalloc(fsg->data_size, GFP_KERNEL); + /* copy data from usb buffer to utp buffer */ + utp_do_write(fsg, data, fsg->data_size); + utp_exec(fsg, data, fsg->data_size, param); + kfree(data); + break; + case UTP_GET: /* data from device to host */ + pr_debug("%s: GET, %d bytes\n", __func__, fsg->data_size); + r = utp_do_read(fsg, UTP_CTX(fsg)->buffer, fsg->data_size); + UTP_SS_PASS(fsg); + break; + case UTP_PUT: /* data from host to device */ + pr_debug("%s: PUT, %d bytes\n", __func__, fsg->data_size); + uud2r = utp_user_data_alloc(fsg->data_size); + uud2r->data.bufsize = fsg->data_size; + uud2r->data.flags = UTP_FLAG_DATA; + utp_do_write(fsg, uud2r->data.data, fsg->data_size); + /* don't know what will be written */ + mutex_lock(&UTP_CTX(fsg)->lock); + list_add_tail(&uud2r->link, &UTP_CTX(fsg)->read); + mutex_unlock(&UTP_CTX(fsg)->lock); + wake_up(&UTP_CTX(fsg)->wq); + /* + * Return PASS or FAIL according to uuc's status + * Please open it if need to check uuc's status + * and use another version uuc + */ +#if 0 + struct utp_user_data *uud = NULL; + struct utp_context *ctx; + WAIT_ACTIVITY(write); + ctx = UTP_CTX(fsg); + mutex_lock(&ctx->lock); + + if (!list_empty(&ctx->write)) + uud = list_first_entry(&ctx->write, + struct utp_user_data, link); + + mutex_unlock(&ctx->lock); + if (uud) { + if (uud->data.flags & UTP_FLAG_STATUS) { + printk(KERN_WARNING "%s: exit with status %d\n", + __func__, uud->data.status); + UTP_SS_EXIT(fsg, uud->data.status); + } else { + pr_debug("%s: pass\n", __func__); + UTP_SS_PASS(fsg); + } + utp_user_data_free(uud); + } else{ + UTP_SS_PASS(fsg); + } +#endif + UTP_SS_PASS(fsg); + + wait_event_interruptible(UTP_CTX(fsg)->list_full_wq, + count_list(&UTP_CTX(fsg)->read) < 7); + break; + } + + utp_send_status(fsg); + return -1; +} + diff --git a/drivers/usb/gadget/fsl_updater.h b/drivers/usb/gadget/fsl_updater.h new file mode 100644 index 000000000000..1662f9d83ec6 --- /dev/null +++ b/drivers/usb/gadget/fsl_updater.h @@ -0,0 +1,148 @@ +/* + * Freescale UUT driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __FSL_UPDATER_H +#define __FSL_UPDATER_H + +#include +#include +#include +#include +#include + +static int utp_init(struct fsg_dev *fsg); +static void utp_exit(struct fsg_dev *fsg); +static ssize_t utp_file_read(struct file *file, + char __user *buf, + size_t size, + loff_t *off); + +static ssize_t utp_file_write(struct file *file, + const char __user *buf, + size_t size, + loff_t *off); + +static int utp_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg); +static struct utp_user_data *utp_user_data_alloc(size_t size); +static void utp_user_data_free(struct utp_user_data *uud); +static int utp_get_sense(struct fsg_dev *fsg); +static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size); +static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size); +static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply); +static int utp_handle_message(struct fsg_dev *fsg, + char *cdb_data, + int default_reply); + +#define UTP_REPLY_PASS 0 +#define UTP_REPLY_EXIT 0x8001 +#define UTP_REPLY_BUSY 0x8002 +#define UTP_REPLY_SIZE 0x8003 +#define UTP_SENSE_KEY 9 + +#define UTP_MINOR 222 +/* MISC_DYNAMIC_MINOR would be better, but... */ + +#define UTP_COMMAND_SIZE 80 + +#define UTP_SS_EXIT(fsg, r) utp_set_sense(fsg, UTP_REPLY_EXIT, (u64)r) +#define UTP_SS_PASS(fsg) utp_set_sense(fsg, UTP_REPLY_PASS, 0) +#define UTP_SS_BUSY(fsg, r) utp_set_sense(fsg, UTP_REPLY_BUSY, (u64)r) +#define UTP_SS_SIZE(fsg, r) utp_set_sense(fsg, UTP_REPLY_SIZE, (u64)r) + +#define UTP_IOCTL_BASE 'U' +#define UTP_GET_CPU_ID _IOR(UTP_IOCTL_BASE, 0, int) +/* the structure of utp message which is mapped to 16-byte SCSI CBW's CDB */ +#pragma pack(1) +struct utp_msg { + u8 f0; + u8 utp_msg_type; + u32 utp_msg_tag; + union { + struct { + u32 param_lsb; + u32 param_msb; + }; + u64 param; + }; +}; + +enum utp_msg_type { + UTP_POLL = 0, + UTP_EXEC, + UTP_GET, + UTP_PUT, +}; + +static struct utp_context { + wait_queue_head_t wq; + wait_queue_head_t list_full_wq; + struct mutex lock; + struct list_head read; + struct list_head write; + u32 sd, sdinfo, sdinfo_h; /* sense data */ + int processed; + u8 *buffer; + u32 counter; + u64 utp_version; +} utp_context; + +static const struct file_operations utp_fops = { + .open = nonseekable_open, + .read = utp_file_read, + .write = utp_file_write, + .ioctl = utp_ioctl, +}; + +static struct miscdevice utp_dev = { + .minor = UTP_MINOR, + .name = "utp", + .fops = &utp_fops, +}; + +#define UTP_FLAG_COMMAND 0x00000001 +#define UTP_FLAG_DATA 0x00000002 +#define UTP_FLAG_STATUS 0x00000004 +#define UTP_FLAG_REPORT_BUSY 0x10000000 +struct utp_message { + u32 flags; + size_t size; + union { + struct { + u64 payload; + char command[1]; + }; + struct { + size_t bufsize; + u8 data[1]; + }; + u32 status; + }; +}; + +struct utp_user_data { + struct list_head link; + struct utp_message data; +}; +#pragma pack() + +static inline struct utp_context *UTP_CTX(struct fsg_dev *fsg) +{ + return (struct utp_context *)fsg->utp; +} + +#endif /* __FSL_UPDATER_H */ + diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index e511fec9f26d..9820bf0955f1 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -142,6 +142,12 @@ #define gadget_is_s3c_hsotg(g) 0 #endif +#ifdef CONFIG_USB_GADGET_ARC +#define gadget_is_arcotg(g) (!strcmp("fsl-usb2-udc", (g)->name)) +#else +#define gadget_is_arcotg(g) 0 +#endif + /** * usb_gadget_controller_number - support bcdDevice id convention @@ -200,6 +206,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x25; else if (gadget_is_s3c_hsotg(gadget)) return 0x26; + else if (gadget_is_arcotg(gadget)) + return 0x26; return -ENOENT; } diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c index de8a83803505..946507e2527a 100644 --- a/drivers/usb/gadget/inode.c +++ b/drivers/usb/gadget/inode.c @@ -41,6 +41,8 @@ #include #include +#include +#include /* * The gadgetfs API maps each endpoint to a file descriptor so that you @@ -82,6 +84,9 @@ MODULE_DESCRIPTION (DRIVER_DESC); MODULE_AUTHOR ("David Brownell"); MODULE_LICENSE ("GPL"); +/* Cancel IO, To store the bulkin and bulkout ep data. */ +static struct ep_data *gp_ep_bulkin_data; +static struct ep_data *gp_ep_bulkout_data; /*----------------------------------------------------------------------*/ @@ -266,6 +271,10 @@ static const char *CHIP; #define INFO(dev,fmt,args...) \ xprintk(dev , KERN_INFO , fmt , ## args) +/* Cancel IO */ +static int mtp_ctrl_cmd; +static int gbCancelFlag; +static unsigned long mtptimestamp; /*----------------------------------------------------------------------*/ @@ -276,6 +285,17 @@ static const char *CHIP; * precise FIFO status when recovering from cancellation. */ +/* Cancel IO */ +static void cancel_io_process(struct work_struct *work) +{ + if (gp_ep_bulkout_data->req->status == -EINPROGRESS) + usb_ep_dequeue(gp_ep_bulkout_data->ep, gp_ep_bulkout_data->req); + + if (gp_ep_bulkin_data->req->status == -EINPROGRESS) + usb_ep_dequeue(gp_ep_bulkin_data->ep, gp_ep_bulkin_data->req); +} +static DECLARE_DELAYED_WORK(cancel_work, cancel_io_process); + static void epio_complete (struct usb_ep *ep, struct usb_request *req) { struct ep_data *epdata = ep->driver_data; @@ -872,6 +892,8 @@ ep_open (struct inode *inode, struct file *fd) { struct ep_data *data = inode->i_private; int value = -EBUSY; + char *epin = "ep1in"; + char *epout = "ep1out"; if (mutex_lock_interruptible(&data->lock) != 0) return -EINTR; @@ -884,6 +906,12 @@ ep_open (struct inode *inode, struct file *fd) get_ep (data); fd->private_data = data; VDEBUG (data->dev, "%s ready\n", data->name); + /* Cancel IO */ + if (0 == strcmp(data->name, epin)) + gp_ep_bulkin_data = fd->private_data; + + if (0 == strcmp(data->name, epout)) + gp_ep_bulkout_data = fd->private_data; } else DBG (data->dev, "%s state %d\n", data->name, data->state); @@ -1047,8 +1075,12 @@ ep0_read (struct file *fd, char __user *buf, size_t len, loff_t *ptr) // FIXME don't call this with the spinlock held ... if (copy_to_user (buf, dev->req->buf, len)) retval = -EFAULT; + else + /* Bug of Cancel IO 6 bytes read. */ + retval = len; clean_req (dev->gadget->ep0, dev->req); /* NOTE userspace can't yet choose to stall */ + dev->state = STATE_DEV_CONNECTED; /* Cancel IO */ } } goto done; @@ -1062,6 +1094,12 @@ ep0_read (struct file *fd, char __user *buf, size_t len, loff_t *ptr) len -= len % sizeof (struct usb_gadgetfs_event); dev->usermode_setup = 1; + /* Cancel IO, signal abort blocked IO. */ + if (mtp_ctrl_cmd == 1) { + mtp_ctrl_cmd = 0; + schedule_delayed_work(&cancel_work, HZ / 100); + } + scan: /* return queued events right away */ if (dev->ev_next != 0) { @@ -1388,6 +1426,16 @@ gadgetfs_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) struct usb_gadgetfs_event *event; u16 w_value = le16_to_cpu(ctrl->wValue); u16 w_length = le16_to_cpu(ctrl->wLength); + struct timeval tv; + + /* Cancel IO */ + if (0x67 == ctrl->bRequest && 1 == gbCancelFlag + && dev->state == STATE_DEV_SETUP) + dev->state = STATE_DEV_CONNECTED; + + if (0x67 == ctrl->bRequest && 2 == mtp_ctrl_cmd + && dev->state == STATE_DEV_SETUP) + dev->state = STATE_DEV_CONNECTED; spin_lock (&dev->lock); dev->setup_abort = 0; @@ -1415,6 +1463,11 @@ gadgetfs_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) */ } else if (dev->state == STATE_DEV_SETUP) dev->setup_abort = 1; + /*Cancel IO */ + if (mtp_ctrl_cmd == 1 && gbCancelFlag == 1 && dev->setup_abort == 1) { + INFO(dev, "0x64->setup\n"); + dev->setup_abort = 0; + } req->buf = dev->rbuf; req->dma = DMA_ADDR_INVALID; @@ -1547,11 +1600,63 @@ delegate: /* we can't currently stall these */ dev->setup_can_stall = 0; } + /* Cancel IO */ + if (0x67 == ctrl->bRequest && 1 == gbCancelFlag) { + gbCancelFlag = 0; + + setup_req(gadget->ep0, dev->req, 4); + *(unsigned long *)dev->req->buf = 0x20190004; + usb_ep_queue(gadget->ep0, dev->req, GFP_ATOMIC); + + spin_unlock(&dev->lock); + return 0; + } + if (ctrl->bRequest == 0x67 && mtp_ctrl_cmd == 2) { + /* get status */ + mtp_ctrl_cmd = 0; + } /* state changes when reader collects event */ event = next_event (dev, GADGETFS_SETUP); event->u.setup = *ctrl; + /* Cancel IO */ + if (0x64 == ctrl->bRequest) { + mtp_ctrl_cmd = 1; + gbCancelFlag = 1; + + /* get the timestamp */ + do_gettimeofday(&tv); + mtptimestamp = tv.tv_usec; + event->u.setup.wValue = + (unsigned short)tv.tv_usec; + } + if (0x66 == ctrl->bRequest) { + /* get the timestamp */ + do_gettimeofday(&tv); + mtptimestamp = tv.tv_usec; + event->u.setup.wValue = + (unsigned short)tv.tv_usec; + } + ep0_readable (dev); + /* Reset request. */ + if (ctrl->bRequest == 0x66) { /* reset ,send ZLP */ + mtp_ctrl_cmd = 2; + + if (gp_ep_bulkout_data->req->status == + -EINPROGRESS) { + usb_ep_dequeue(gp_ep_bulkout_data->ep, + gp_ep_bulkout_data->req); + } + if (gp_ep_bulkin_data->req->status == + -EINPROGRESS) { + usb_ep_dequeue(gp_ep_bulkin_data->ep, + gp_ep_bulkin_data->req); + } + } + if (ctrl->bRequest == 0x65) + pr_debug("i:0x65,not supported\n"); + spin_unlock (&dev->lock); return 0; } diff --git a/drivers/usb/gadget/stmp_updater.c b/drivers/usb/gadget/stmp_updater.c new file mode 100644 index 000000000000..63c22f98eacf --- /dev/null +++ b/drivers/usb/gadget/stmp_updater.c @@ -0,0 +1,504 @@ +/* + * Freescale STMP378X UUT driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include + +static u64 get_be64(u8 *buf) +{ + return ((u64)get_unaligned_be32(buf) << 32) | get_unaligned_be32(buf + 4); +} + +static int utp_init(struct fsg_dev *fsg) +{ + init_waitqueue_head(&utp_context.wq); + init_waitqueue_head(&utp_context.list_full_wq); + + INIT_LIST_HEAD(&utp_context.read); + INIT_LIST_HEAD(&utp_context.write); + mutex_init(&utp_context.lock); + + utp_context.buffer = vmalloc(0x10000); + if (!utp_context.buffer) + return -EIO; + utp_context.utp_version = 0x1ull; + fsg->utp = &utp_context; + return misc_register(&utp_dev); +} + +static void utp_exit(struct fsg_dev *fsg) +{ + vfree(utp_context.buffer); + misc_deregister(&utp_dev); +} + +static struct utp_user_data *utp_user_data_alloc(size_t size) +{ + struct utp_user_data *uud; + + uud = kzalloc(size + sizeof(*uud), GFP_KERNEL); + if (!uud) + return uud; + uud->data.size = size + sizeof(uud->data); + INIT_LIST_HEAD(&uud->link); + return uud; +} + +static void utp_user_data_free(struct utp_user_data *uud) +{ + mutex_lock(&utp_context.lock); + list_del(&uud->link); + mutex_unlock(&utp_context.lock); + kfree(uud); +} + +static u32 count_list(struct list_head *l) +{ + u32 count = 0; + struct list_head *tmp; + + list_for_each(tmp, l) { + count++; + } + + return count; +} + +#define WAIT_ACTIVITY(queue) \ + wait_event_interruptible(utp_context.wq, !list_empty(&utp_context.queue)) + +static ssize_t utp_file_read(struct file *file, + char __user *buf, + size_t size, + loff_t *off) +{ + struct utp_user_data *uud; + size_t size_to_put; + int free = 0; + + WAIT_ACTIVITY(read); + + mutex_lock(&utp_context.lock); + uud = list_first_entry(&utp_context.read, struct utp_user_data, link); + mutex_unlock(&utp_context.lock); + size_to_put = uud->data.size; + + if (size >= size_to_put) + free = !0; + if (copy_to_user(buf, &uud->data, size_to_put)) + return -EACCES; + if (free) + utp_user_data_free(uud); + else { + pr_info("sizeof = %d, size = %d\n", + sizeof(uud->data), + uud->data.size); + + pr_err("Will not free utp_user_data, because buffer size = %d," + "need to put %d\n", size, size_to_put); + } + + wake_up(&utp_context.list_full_wq); + + return size_to_put; +} + + +static ssize_t utp_file_write(struct file *file, const char __user *buf, + size_t size, loff_t *off) +{ + struct utp_user_data *uud; + + if (size < sizeof(uud->data)) + return -EINVAL; + uud = utp_user_data_alloc(size); + if (copy_from_user(&uud->data, buf, size)) + return -EACCES; + mutex_lock(&utp_context.lock); + list_add_tail(&uud->link, &utp_context.write); + wake_up(&utp_context.wq); + mutex_unlock(&utp_context.lock); + return size; +} + +static int utp_get_sense(struct fsg_dev *fsg) +{ + if (UTP_CTX(fsg)->processed == 0) + return -1; + + UTP_CTX(fsg)->processed = 0; + return 0; +} + +static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size) +{ + struct fsg_buffhd *bh; + int rc; + u32 amount_left; + unsigned int amount; + + /* Get the starting Logical Block Address and check that it's + * not too big */ + + amount_left = size; + if (unlikely(amount_left == 0)) + return -EIO; /* No default reply*/ + + pr_debug("%s: sending %d\n", __func__, size); + for (;;) { + /* Figure out how much we need to read: + * Try to read the remaining amount. + * But don't read more than the buffer size. + * And don't try to read past the end of the file. + * Finally, if we're not at a page boundary, don't read past + * the next page. + * If this means reading 0 then we were asked to read past + * the end of file. */ + amount = min((unsigned int) amount_left, mod_data.buflen); + + /* Wait for the next buffer to become available */ + bh = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + /* If we were asked to read past the end of file, + * end with an empty buffer. */ + if (amount == 0) { + bh->inreq->length = 0; + bh->state = BUF_STATE_FULL; + break; + } + + /* Perform the read */ + pr_info("Copied to %p, %d bytes started from %d\n", + bh->buf, amount, size - amount_left); + memcpy(bh->buf, data + size - amount_left, amount); + amount_left -= amount; + fsg->residue -= amount; + + bh->inreq->length = amount; + bh->state = BUF_STATE_FULL; + + /* Send this buffer and go read some more */ + bh->inreq->zero = 0; + + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + + fsg->next_buffhd_to_fill = bh->next; + + if (amount_left <= 0) + break; + } + + return size - amount_left; +} + +static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size) +{ + struct fsg_buffhd *bh; + int get_some_more; + u32 amount_left_to_req, amount_left_to_write; + unsigned int amount; + int rc; + loff_t offset; + + /* Carry out the file writes */ + get_some_more = 1; + amount_left_to_req = amount_left_to_write = size; + + if (unlikely(amount_left_to_write == 0)) + return -EIO; + + offset = 0; + while (amount_left_to_write > 0) { + + /* Queue a request for more data from the host */ + bh = fsg->next_buffhd_to_fill; + if (bh->state == BUF_STATE_EMPTY && get_some_more) { + + /* Figure out how much we want to get: + * Try to get the remaining amount. + * But don't get more than the buffer size. + * And don't try to go past the end of the file. + * If we're not at a page boundary, + * don't go past the next page. + * If this means getting 0, then we were asked + * to write past the end of file. + * Finally, round down to a block boundary. */ + amount = min(amount_left_to_req, mod_data.buflen); + + if (amount == 0) { + get_some_more = 0; + /* cry now */ + continue; + } + + /* Get the next buffer */ + amount_left_to_req -= amount; + if (amount_left_to_req == 0) + get_some_more = 0; + + /* amount is always divisible by 512, hence by + * the bulk-out maxpacket size */ + bh->outreq->length = bh->bulk_out_intended_length = + amount; + bh->outreq->short_not_ok = 1; + start_transfer(fsg, fsg->bulk_out, bh->outreq, + &bh->outreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; + continue; + } + + /* Write the received data to the backing file */ + bh = fsg->next_buffhd_to_drain; + if (bh->state == BUF_STATE_EMPTY && !get_some_more) + break; /* We stopped early */ + if (bh->state == BUF_STATE_FULL) { + smp_rmb(); + fsg->next_buffhd_to_drain = bh->next; + bh->state = BUF_STATE_EMPTY; + + /* Did something go wrong with the transfer? */ + if (bh->outreq->status != 0) + /* cry again, COMMUNICATION_FAILURE */ + break; + + amount = bh->outreq->actual; + + /* Perform the write */ + memcpy(data + offset, bh->buf, amount); + + offset += amount; + if (signal_pending(current)) + return -EINTR; /* Interrupted!*/ + amount_left_to_write -= amount; + fsg->residue -= amount; + + /* Did the host decide to stop early? */ + if (bh->outreq->actual != bh->outreq->length) { + fsg->short_packet_received = 1; + break; + } + continue; + } + + /* Wait for something to happen */ + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + return -EIO; +} + +static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply) +{ + UTP_CTX(fsg)->processed = true; + UTP_CTX(fsg)->sdinfo = reply & 0xFFFFFFFF; + UTP_CTX(fsg)->sdinfo_h = (reply >> 32) & 0xFFFFFFFF; + UTP_CTX(fsg)->sd = (UTP_SENSE_KEY << 16) | code; +} + +static void utp_poll(struct fsg_dev *fsg) +{ + struct utp_context *ctx = UTP_CTX(fsg); + struct utp_user_data *uud = NULL; + + mutex_lock(&ctx->lock); + if (!list_empty(&ctx->write)) + uud = list_first_entry(&ctx->write, struct utp_user_data, link); + mutex_unlock(&ctx->lock); + + if (uud) { + if (uud->data.flags & UTP_FLAG_STATUS) { + pr_debug("%s: exit with status %d\n", __func__, + uud->data.status); + UTP_SS_EXIT(fsg, uud->data.status); + } else { + pr_debug("%s: pass\n", __func__); + UTP_SS_PASS(fsg); + } + utp_user_data_free(uud); + } else { + pr_debug("%s: still busy...\n", __func__); + UTP_SS_BUSY(fsg, --ctx->counter); + } +} + +static int utp_exec(struct fsg_dev *fsg, + char *command, + int cmdsize, + unsigned long long payload) +{ + struct utp_user_data *uud = NULL, *uud2r; + struct utp_context *ctx = UTP_CTX(fsg); + + uud2r = utp_user_data_alloc(cmdsize + 1); + uud2r->data.flags = UTP_FLAG_COMMAND; + uud2r->data.payload = payload; + strncpy(uud2r->data.command, command, cmdsize); + + mutex_lock(&ctx->lock); + list_add_tail(&uud2r->link, &ctx->read); + mutex_unlock(&ctx->lock); + wake_up(&ctx->wq); + + if (command[0] == '!') /* there will be no response */ + return 0; + + WAIT_ACTIVITY(write); + + mutex_lock(&ctx->lock); + if (!list_empty(&ctx->write)) { + uud = list_first_entry(&ctx->write, struct utp_user_data, link); +#ifdef DEBUG + pr_info("UUD:\n\tFlags = %02X\n", uud->data.flags); + if (uud->data.flags & UTP_FLAG_DATA) { + pr_info("\tbufsize = %d\n", uud->data.bufsize); + print_hex_dump(KERN_DEBUG, "\t", DUMP_PREFIX_NONE, + 16, 2, uud->data.data, uud->data.bufsize, true); + } + if (uud->data.flags & UTP_FLAG_REPORT_BUSY) + pr_info("\tBUSY\n"); +#endif + } + mutex_unlock(&ctx->lock); + + if (uud->data.flags & UTP_FLAG_DATA) { + memcpy(ctx->buffer, uud->data.data, uud->data.bufsize); + UTP_SS_SIZE(fsg, uud->data.bufsize); + utp_user_data_free(uud); + return 0; + } + + if (uud->data.flags & UTP_FLAG_REPORT_BUSY) { + utp_user_data_free(uud); + ctx->counter = 0xFFFF; + UTP_SS_BUSY(fsg, ctx->counter); + return 0; + } + + utp_user_data_free(uud); + UTP_SS_PASS(fsg); + + return -1; +} + +static int utp_send_status(struct fsg_dev *fsg) +{ + struct fsg_buffhd *bh; + u8 status = USB_STATUS_PASS; + struct bulk_cs_wrap *csw; + int rc; + + /* Wait for the next buffer to become available */ + bh = fsg->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg); + if (rc) + return rc; + } + + if (fsg->phase_error) { + DBG(fsg, "sending phase-error status\n"); + status = USB_STATUS_PHASE_ERROR; + + } else if ((UTP_CTX(fsg)->sd & 0xFFFF) != UTP_REPLY_PASS) { + status = USB_STATUS_FAIL; + } + + csw = bh->buf; + + /* Store and send the Bulk-only CSW */ + csw->Signature = __constant_cpu_to_le32(USB_BULK_CS_SIG); + csw->Tag = fsg->tag; + csw->Residue = cpu_to_le32(fsg->residue); + csw->Status = status; + + bh->inreq->length = USB_BULK_CS_WRAP_LEN; + bh->inreq->zero = 0; + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + fsg->next_buffhd_to_fill = bh->next; + return 0; +} + +static int utp_handle_message(struct fsg_dev *fsg, + char *cdb_data, + int default_reply) +{ + struct utp_msg *m = (struct utp_msg *)cdb_data; + void *data = NULL; + int r; + struct utp_user_data *uud2r; + unsigned long long param; + unsigned long tag; + + if (m->f0 != 0xF0) + return default_reply; + + tag = get_unaligned_be32((void *)&m->utp_msg_tag); + param = get_be64((void *)&m->param); + pr_debug("Type 0x%x, tag 0x%08lx, param %llx\n", + m->utp_msg_type, tag, param); + + switch ((enum utp_msg_type)m->utp_msg_type) { + + case UTP_POLL: + if (get_be64((void *)&m->param) == 1) { + pr_debug("%s: version request\n", __func__); + UTP_SS_EXIT(fsg, UTP_CTX(fsg)->utp_version); + break; + } + utp_poll(fsg); + break; + case UTP_EXEC: + pr_debug("%s: EXEC\n", __func__); + data = kzalloc(fsg->data_size, GFP_KERNEL); + utp_do_write(fsg, data, fsg->data_size); + utp_exec(fsg, data, fsg->data_size, param); + kfree(data); + break; + case UTP_GET: + pr_debug("%s: GET, %d bytes\n", __func__, fsg->data_size); + r = utp_do_read(fsg, UTP_CTX(fsg)->buffer, fsg->data_size); + UTP_SS_PASS(fsg); + break; + case UTP_PUT: + pr_debug("%s: PUT, %d bytes\n", __func__, fsg->data_size); + uud2r = utp_user_data_alloc(fsg->data_size); + uud2r->data.bufsize = fsg->data_size; + uud2r->data.flags = UTP_FLAG_DATA; + utp_do_write(fsg, uud2r->data.data, fsg->data_size); + /* don't know what will be written */ + mutex_lock(&UTP_CTX(fsg)->lock); + list_add_tail(&uud2r->link, &UTP_CTX(fsg)->read); + mutex_unlock(&UTP_CTX(fsg)->lock); + wake_up(&UTP_CTX(fsg)->wq); + UTP_SS_PASS(fsg); + + wait_event_interruptible(UTP_CTX(fsg)->list_full_wq, + count_list(&UTP_CTX(fsg)->read) < 7); + break; + } + + utp_send_status(fsg); + return -1; +} + diff --git a/drivers/usb/gadget/stmp_updater.h b/drivers/usb/gadget/stmp_updater.h new file mode 100644 index 000000000000..810e5f92aeb8 --- /dev/null +++ b/drivers/usb/gadget/stmp_updater.h @@ -0,0 +1,140 @@ +/* + * Freescale STMP378X UUT driver + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __STMP_UPDATER_H +#define __STMP_UPDATER_H + +#include +#include +#include + +static int utp_init(struct fsg_dev *fsg); +static void utp_exit(struct fsg_dev *fsg); +static ssize_t utp_file_read(struct file *file, + char __user *buf, + size_t size, + loff_t *off); + +static ssize_t utp_file_write(struct file *file, + const char __user *buf, + size_t size, + loff_t *off); + +static struct utp_user_data *utp_user_data_alloc(size_t size); +static void utp_user_data_free(struct utp_user_data *uud); +static int utp_get_sense(struct fsg_dev *fsg); +static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size); +static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size); +static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply); +static int utp_handle_message(struct fsg_dev *fsg, + char *cdb_data, + int default_reply); + +#define UTP_REPLY_PASS 0 +#define UTP_REPLY_EXIT 0x8001 +#define UTP_REPLY_BUSY 0x8002 +#define UTP_REPLY_SIZE 0x8003 +#define UTP_SENSE_KEY 9 + +#define UTP_MINOR 222 +/* MISC_DYNAMIC_MINOR would be better, but... */ + +#define UTP_COMMAND_SIZE 80 + +#define UTP_SS_EXIT(fsg, r) utp_set_sense(fsg, UTP_REPLY_EXIT, (u64)r) +#define UTP_SS_PASS(fsg) utp_set_sense(fsg, UTP_REPLY_PASS, 0) +#define UTP_SS_BUSY(fsg, r) utp_set_sense(fsg, UTP_REPLY_BUSY, (u64)r) +#define UTP_SS_SIZE(fsg, r) utp_set_sense(fsg, UTP_REPLY_SIZE, (u64)r) + +#pragma pack(1) +struct utp_msg { + u8 f0; + u8 utp_msg_type; + u32 utp_msg_tag; + union { + struct { + u32 param_lsb; + u32 param_msb; + }; + u64 param; + }; +}; + +enum utp_msg_type { + UTP_POLL = 0, + UTP_EXEC, + UTP_GET, + UTP_PUT, +}; + +static struct utp_context { + wait_queue_head_t wq; + wait_queue_head_t list_full_wq; + struct mutex lock; + struct list_head read; + struct list_head write; + u32 sd, sdinfo, sdinfo_h; /* sense data */ + int processed; + u8 *buffer; + u32 counter; + u64 utp_version; +} utp_context; + +static const struct file_operations utp_fops = { + .open = nonseekable_open, + .read = utp_file_read, + .write = utp_file_write, +}; + +static struct miscdevice utp_dev = { + .minor = UTP_MINOR, + .name = "utp", + .fops = &utp_fops, +}; + +#define UTP_FLAG_COMMAND 0x00000001 +#define UTP_FLAG_DATA 0x00000002 +#define UTP_FLAG_STATUS 0x00000004 +#define UTP_FLAG_REPORT_BUSY 0x10000000 +struct utp_message { + u32 flags; + size_t size; + union { + struct { + u64 payload; + char command[1]; + }; + struct { + size_t bufsize; + u8 data[1]; + }; + u32 status; + }; +}; + +struct utp_user_data { + struct list_head link; + struct utp_message data; +}; +#pragma pack() + +static inline struct utp_context *UTP_CTX(struct fsg_dev *fsg) +{ + return (struct utp_context *)fsg->utp; +} + +#endif /* __STMP_UPDATER_H */ + diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index f865be2276d4..f90afd30a70c 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -59,9 +59,101 @@ config USB_EHCI_HCD To compile this driver as a module, choose M here: the module will be called ehci-hcd. +config USB_EHCI_ARC + bool "Support for Freescale controller" + depends on USB_EHCI_HCD && (ARCH_MXC || ARCH_STMP3XXX || ARCH_MXS) + select USB_OTG_UTILS + ---help--- + Some Freescale processors have an integrated High Speed + USBOTG controller, which supports EHCI host mode. + + Say "y" here to add support for this controller + to the EHCI HCD driver. + +config USB_EHCI_ARC_H1 + bool "Support for Host1 port on Freescale controller" + depends on USB_EHCI_ARC && (ARCH_MX27 || ARCH_MX3 || ARCH_MX28) + ---help--- + Enable support for the USB Host1 port. + +config USB_EHCI_ARC_H2 + bool "Support for Host2 port on Freescale controller" + depends on USB_EHCI_ARC && \ + (ARCH_MX25 || ARCH_MX27 || ARCH_MX3 || ARCH_MX35) + ---help--- + Enable support for the USB Host2 port. + +config USB_EHCI_ARC_OTG + bool "Support for DR host port on Freescale controller" + depends on USB_EHCI_ARC + default y + ---help--- + Enable support for the USB OTG port in HS/FS Host mode. + +config USB_STATIC_IRAM + bool "Use IRAM for USB" + depends on USB_EHCI_ARC + ---help--- + Enable this option to use IRAM instead of DRAM for USB + structures and buffers. This option will reduce bus + contention on systems with large (VGA+) framebuffer + devices and heavy USB activity. There are performance + penalties and usage restrictions when using this option. + + If in doubt, say N. + +choice + prompt "Select transceiver for DR port" + depends on USB_EHCI_ARC_OTG + default USB_EHCI_FSL_1504 if ARCH_MX3 + default USB_EHCI_FSL_1301 if ARCH_MX27 + default USB_EHCI_FSL_UTMI if (ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX51 || ARCH_STMP3XXX || ARCH_MXS) + ---help--- + Choose the transceiver to use with the Freescale DR port. + +config USB_EHCI_FSL_MC13783 + bool "Freescale MC13783" + depends on !MACH_MX25_3DS + ---help--- + Enable support for the Full Speed Freescale MC13783 transceiver. + + The mx27ads, mx31ads and mx32ads boards require modifications + to support this transceiver. + +config USB_EHCI_FSL_1301 + bool "Philips ISP1301" + depends on !MACH_MX25_3DS + ---help--- + Enable support for the Full Speed Philips ISP1301 transceiver. + + This is the factory default for the mx27ads board. + The mx31ads and mx32ads boards require modifications + to support this transceiver. + +config USB_EHCI_FSL_1504 + bool "Philips ISP1504" + depends on MACH_MX27ADS || MACH_MX31ADS || MACH_MX32ADS ||MACH_MX31_3DS + ---help--- + Enable support for the High Speed Philips ISP1504 transceiver. + + This is the factory default for the mx31ads and mx32ads boards. + The mx27ads board requires modifications to support this transceiver. + +config USB_EHCI_FSL_UTMI + bool "Internal UTMI" + depends on (ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX51 || ARCH_STMP3XXX || ARCH_MXS) + ---help--- + Enable support for the on-chip High Speed UTMI transceiver. + + This is the factory default for the mx35ads board. + +endchoice + + config USB_EHCI_ROOT_HUB_TT bool "Root Hub Transaction Translators" depends on USB_EHCI_HCD + default y if USB_EHCI_ARC ---help--- Some EHCI chips have vendor-specific extensions to integrate transaction translators, so that no OHCI or UHCI companion diff --git a/drivers/usb/host/ehci-arc.c b/drivers/usb/host/ehci-arc.c new file mode 100644 index 000000000000..af86a962826c --- /dev/null +++ b/drivers/usb/host/ehci-arc.c @@ -0,0 +1,737 @@ +/* + * Copyright (c) 2005 MontaVista Software + * Copyright (C) 2011 Freescale Semiconductor + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Ported to 834x by Randy Vinson using code provided + * by Hunter Wu. + */ + +#include +#include +#include +#include + +#include "../core/usb.h" +#include "ehci-fsl.h" +#include + +extern int usb_host_wakeup_irq(struct device *wkup_dev); +extern void usb_host_set_wakeup(struct device *wkup_dev, bool para); +static void fsl_usb_lowpower_mode(struct fsl_usb2_platform_data *pdata, bool enable) +{ + if (enable) { + if (pdata->phy_lowpower_suspend) + pdata->phy_lowpower_suspend(pdata, true); + } else { + if (pdata->phy_lowpower_suspend) + pdata->phy_lowpower_suspend(pdata, false); + } + pdata->lowpower = enable; +} + +static void fsl_usb_clk_gate(struct fsl_usb2_platform_data *pdata, bool enable) +{ + if (pdata->usb_clock_for_pm) + pdata->usb_clock_for_pm(enable); +} +#undef EHCI_PROC_PTC +#ifdef EHCI_PROC_PTC /* /proc PORTSC:PTC support */ +/* + * write a PORTSC:PTC value to /proc/driver/ehci-ptc + * to put the controller into test mode. + */ +#include +#include +#define EFPSL 3 /* ehci fsl proc string length */ + +static int ehci_fsl_proc_read(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + return 0; +} + +static int ehci_fsl_proc_write(struct file *file, const char __user *buffer, + unsigned long count, void *data) +{ + int ptc; + u32 portsc; + struct ehci_hcd *ehci = (struct ehci_hcd *) data; + char str[EFPSL] = {0}; + + if (count > EFPSL-1) + return -EINVAL; + + if (copy_from_user(str, buffer, count)) + return -EFAULT; + + str[count] = '\0'; + + ptc = simple_strtoul(str, NULL, 0); + + portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); + portsc &= ~(0xf << 16); + portsc |= (ptc << 16); + printk(KERN_INFO "PTC %x portsc %08x\n", ptc, portsc); + + ehci_writel(ehci, portsc, &ehci->regs->port_status[0]); + + return count; +} + +static int ehci_testmode_init(struct ehci_hcd *ehci) +{ + struct proc_dir_entry *entry; + + entry = create_proc_read_entry("driver/ehci-ptc", 0644, NULL, + ehci_fsl_proc_read, ehci); + if (!entry) + return -ENODEV; + + entry->write_proc = ehci_fsl_proc_write; + return 0; +} +#else +static int ehci_testmode_init(struct ehci_hcd *ehci) +{ + return 0; +} +#endif /* /proc PORTSC:PTC support */ + +/** + * The hcd operation need to be done during the wakeup irq + */ +void fsl_usb_recover_hcd(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + u32 cmd = 0; + + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + /* After receive remote wakeup signaling. Must restore + * CMDRUN bit in 20ms to keep port status. + */ + cmd = ehci_readl(ehci, &ehci->regs->command); + if (!(cmd & CMD_RUN)) { + ehci_writel(ehci, ehci->command, &ehci->regs->command); + /* Resume root hub here? */ + usb_hcd_resume_root_hub(hcd); + } +} + +/** + * usb_hcd_fsl_probe - initialize FSL-based HCDs + * @drvier: Driver to be used for this HCD + * @pdev: USB Host Controller being probed + * Context: !in_interrupt() + * + * Allocates basic resources for this USB host controller. + * + */ +int usb_hcd_fsl_probe(const struct hc_driver *driver, + struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata; + struct usb_hcd *hcd; + struct resource *res; + int irq; + int retval; + + pr_debug("initializing FSL-SOC USB Controller\n"); + + /* Need platform data for setup */ + pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, + "No platform data for %s.\n", dev_name(&pdev->dev)); + return -ENODEV; + } + + /* + * This is a host mode driver, verify that we're supposed to be + * in host mode. + */ + if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || + (pdata->operating_mode == FSL_USB2_MPH_HOST) || + (pdata->operating_mode == FSL_USB2_DR_OTG))) { + dev_err(&pdev->dev, + "Non Host Mode configured for %s. Wrong driver linked.\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) { + retval = -ENOMEM; + goto err1; + } + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + hcd->rsrc_start = res->start; + hcd->rsrc_len = resource_size(res); + + if (pdata->operating_mode != FSL_USB2_DR_OTG) { + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + retval = -EBUSY; + goto err2; + } + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + + if (hcd->regs == NULL) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + retval = -EFAULT; + goto err3; + } + pdata->regs = hcd->regs; + + /* + * do platform specific init: check the clock, grab/config pins, etc. + */ + if (pdata->platform_init && pdata->platform_init(pdev)) { + retval = -ENODEV; + goto err3; + } + + fsl_platform_set_host_mode(hcd); + hcd->power_budget = pdata->power_budget; + + retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); + if (retval != 0) + goto err4; + + if (pdata->operating_mode == FSL_USB2_DR_OTG) { + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + + dbg("pdev=0x%p hcd=0x%p ehci=0x%p\n", pdev, hcd, ehci); + + ehci->transceiver = otg_get_transceiver(); + dbg("ehci->transceiver=0x%p\n", ehci->transceiver); + + if (!ehci->transceiver) { + printk(KERN_ERR "can't find transceiver\n"); + retval = -ENODEV; + goto err5; + } + + retval = otg_set_host(ehci->transceiver, &ehci_to_hcd(ehci)->self); + if (retval) + otg_put_transceiver(ehci->transceiver); + } else if ((pdata->operating_mode == FSL_USB2_MPH_HOST) || \ + (pdata->operating_mode == FSL_USB2_DR_HOST)) + fsl_platform_set_vbus_power(pdata, 1); + + if (pdata->suspended) { + pdata->suspended = 0; + if (pdata->already_suspended) + pdata->already_suspended = 0; + } + + fsl_platform_set_ahb_burst(hcd); + ehci_testmode_init(hcd_to_ehci(hcd)); + return retval; +err5: + usb_remove_hcd(hcd); +err4: + iounmap(hcd->regs); +err3: + if (pdata->operating_mode != FSL_USB2_DR_OTG) + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err2: + usb_put_hcd(hcd); +err1: + dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); + return retval; +} + +/** + * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs + * @dev: USB Host Controller being removed + * Context: !in_interrupt() + * + * Reverses the effect of usb_hcd_fsl_probe(). + * + */ +static void usb_hcd_fsl_remove(struct usb_hcd *hcd, + struct platform_device *pdev) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + u32 tmp; + + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + /* Need open clock for register access */ + if (pdata->usb_clock_for_pm) + pdata->usb_clock_for_pm(true); + + tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); + if (tmp & PORT_PTS_PHCD) { + tmp &= ~PORT_PTS_PHCD; + ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); + msleep(100); + + if (pdata->usb_clock_for_pm) + pdata->usb_clock_for_pm(false); + } + } + + /* DDD shouldn't we turn off the power here? */ + fsl_platform_set_vbus_power(pdata, 0); + + if (ehci->transceiver) { + (void)otg_set_host(ehci->transceiver, 0); + otg_put_transceiver(ehci->transceiver); + } else { + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + } + + usb_remove_hcd(hcd); + usb_put_hcd(hcd); + + /* + * do platform specific un-initialization: + * release iomux pins, etc. + */ + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); + + iounmap(hcd->regs); +} + +static void fsl_setup_phy(struct ehci_hcd *ehci, + enum fsl_usb2_phy_modes phy_mode, int port_offset) +{ + u32 portsc; + + portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); + portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); + + switch (phy_mode) { + case FSL_USB2_PHY_ULPI: + portsc |= PORT_PTS_ULPI; + break; + case FSL_USB2_PHY_SERIAL: + portsc |= PORT_PTS_SERIAL; + break; + case FSL_USB2_PHY_UTMI_WIDE: + portsc |= PORT_PTS_PTW; + /* fall through */ + case FSL_USB2_PHY_UTMI: + portsc |= PORT_PTS_UTMI; + break; + case FSL_USB2_PHY_NONE: + break; + } + ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); +} + +/* called after powerup, by probe or system-pm "wakeup" */ +static int ehci_fsl_reinit(struct ehci_hcd *ehci) +{ + fsl_platform_usb_setup(ehci); + ehci_port_power(ehci, 0); + + return 0; +} + +static int ehci_fsl_bus_suspend(struct usb_hcd *hcd) +{ + int ret = 0; + struct fsl_usb2_platform_data *pdata; + + pdata = hcd->self.controller->platform_data; + printk(KERN_DEBUG "%s, %s\n", __func__, pdata->name); + + /* the host is already at low power mode */ + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + return 0; + } + + ret = ehci_bus_suspend(hcd); + if (ret != 0) + return ret; + + if (pdata->platform_suspend) + pdata->platform_suspend(pdata); + + usb_host_set_wakeup(hcd->self.controller, true); + fsl_usb_lowpower_mode(pdata, true); + fsl_usb_clk_gate(hcd->self.controller->platform_data, false); + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + + return ret; +} + +static int ehci_fsl_bus_resume(struct usb_hcd *hcd) +{ + int ret = 0; + struct fsl_usb2_platform_data *pdata; + + pdata = hcd->self.controller->platform_data; + printk(KERN_DEBUG "%s, %s\n", __func__, pdata->name); + + /* + * At otg mode, it should not call host resume for usb gadget device + * Otherwise, this usb device can't be recognized as a gadget + */ + if (hcd->self.is_b_host) { + return -ESHUTDOWN; + } + + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + fsl_usb_clk_gate(hcd->self.controller->platform_data, true); + usb_host_set_wakeup(hcd->self.controller, false); + fsl_usb_lowpower_mode(pdata, false); + } + + if (pdata->platform_resume) + pdata->platform_resume(pdata); + + ret = ehci_bus_resume(hcd); + if (ret) + return ret; + + return ret; +} + +static void ehci_fsl_shutdown(struct usb_hcd *hcd) +{ + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + fsl_usb_clk_gate(hcd->self.controller->platform_data, true); + } + /* Disable wakeup event first */ + usb_host_set_wakeup(hcd->self.controller, false); + + ehci_shutdown(hcd); + if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + fsl_usb_clk_gate(hcd->self.controller->platform_data, false); + } +} + +/* called during probe() after chip reset completes */ +static int ehci_fsl_setup(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval; + + /* EHCI registers start at offset 0x100 */ + ehci->caps = hcd->regs + 0x100; + ehci->regs = hcd->regs + 0x100 + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + dbg_hcs_params(ehci, "reset"); + dbg_hcc_params(ehci, "reset"); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + + retval = ehci_halt(ehci); + if (retval) + return retval; + + /* data structure init */ + retval = ehci_init(hcd); + if (retval) + return retval; + + hcd->has_tt = 1; + + ehci->sbrn = 0x20; + + ehci_reset(ehci); + + retval = ehci_fsl_reinit(ehci); + return retval; +} + +static const struct hc_driver ehci_fsl_hc_driver = { + .description = hcd_name, + .product_desc = "Freescale On-Chip EHCI Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = HCD_USB2, + + /* + * basic lifecycle operations + */ + .reset = ehci_fsl_setup, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_fsl_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_fsl_bus_suspend, + .bus_resume = ehci_fsl_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int ehci_fsl_drv_probe(struct platform_device *pdev) +{ + if (usb_disabled()) + return -ENODEV; + + /* FIXME we only want one one probe() not two */ + return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev); +} + +static int ehci_fsl_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + /* FIXME we only want one one remove() not two */ + usb_hcd_fsl_remove(hcd, pdev); + return 0; +} + +#ifdef CONFIG_PM + +static bool host_can_wakeup_system(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + + if (pdata->operating_mode == FSL_USB2_DR_OTG) + if (device_may_wakeup(ehci->transceiver->dev)) + return true; + else + return false; + else + if (device_may_wakeup(&(pdev->dev))) + return true; + else + return false; +} + +/* suspend/resume, section 4.3 */ + +/* These routines rely on the bus (pci, platform, etc) + * to handle powerdown and wakeup, and currently also on + * transceivers that don't need any software attention to set up + * the right sort of wakeup. + * + * They're also used for turning on/off the port when doing OTG. + */ +static int ehci_fsl_drv_suspend(struct platform_device *pdev, + pm_message_t message) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct usb_device *roothub = hcd->self.root_hub; + u32 port_status; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + + printk(KERN_DEBUG "USB Host suspend begins\n"); + /* Only handles OTG mode switch event, system suspend event will be done in bus suspend */ + if (pdev->dev.power.status == DPM_SUSPENDING) { + printk(KERN_DEBUG "%s, pm event \n", __func__); + if (!host_can_wakeup_system(pdev)) { + int mask; + /* Need open clock for register access */ + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) + fsl_usb_clk_gate(hcd->self.controller->platform_data, true); + + mask = ehci_readl(ehci, &ehci->regs->intr_enable); + mask &= ~STS_PCD; + ehci_writel(ehci, mask, &ehci->regs->intr_enable); + + usb_host_set_wakeup(hcd->self.controller, false); + fsl_usb_clk_gate(hcd->self.controller->platform_data, false); + } + return 0; + } + + /* only the otg host can go here */ + /* wait for all usb device on the hcd dettached */ + usb_lock_device(roothub); + if (roothub->children[0] != NULL) { + int old = hcd->self.is_b_host; + printk(KERN_DEBUG "will resume roothub and its children\n"); + hcd->self.is_b_host = 0; + /* resume the roothub, so that it can test the children is disconnected */ + if (roothub->state == USB_STATE_SUSPENDED) + usb_resume(&roothub->dev, PMSG_USER_SUSPEND); + /* we must do unlock here, the hubd thread will hold the same lock + * here release the lock, so that the hubd thread can process the usb + * disconnect event and set the children[0] be NULL, or there will be + * a deadlock */ + usb_unlock_device(roothub); + while (roothub->children[0] != NULL) + msleep(1); + usb_lock_device(roothub); + hcd->self.is_b_host = old; + } + usb_unlock_device(roothub); + + if (!(hcd->state & HC_STATE_SUSPENDED)) { + printk(KERN_DEBUG "will suspend roothub and its children\n"); + usb_lock_device(roothub); + usb_suspend(&roothub->dev, PMSG_USER_SUSPEND); + usb_unlock_device(roothub); + } + + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + fsl_usb_clk_gate(hcd->self.controller->platform_data, true); + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + } + + port_status = ehci_readl(ehci, &ehci->regs->port_status[0]); + /* save EHCI registers */ + pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); + pdata->pm_command &= ~CMD_RUN; + pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); + pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); + pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); + pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); + pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); + pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); + pdata->pm_configured_flag = + ehci_readl(ehci, &ehci->regs->configured_flag); + pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); + + /* clear the W1C bits */ + pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); + + /* clear PHCD bit */ + pdata->pm_portsc &= ~PORT_PTS_PHCD; + + usb_host_set_wakeup(hcd->self.controller, true); + fsl_usb_lowpower_mode(pdata, true); + + if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + fsl_usb_clk_gate(hcd->self.controller->platform_data, false); + } + printk(KERN_DEBUG "host suspend ends\n"); + return 0; +} + +static int ehci_fsl_drv_resume(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + struct usb_device *roothub = hcd->self.root_hub; + u32 tmp; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + struct fsl_usb2_wakeup_platform_data *wake_up_pdata = pdata->wakeup_pdata; + /* Only handles OTG mode switch event */ + printk(KERN_DEBUG "ehci fsl drv resume begins: %s\n", pdata->name); + if (pdev->dev.power.status == DPM_RESUMING) { + printk(KERN_DEBUG "%s,pm event, wait for wakeup irq if needed\n", __func__); + wait_event_interruptible(wake_up_pdata->wq, !wake_up_pdata->usb_wakeup_is_pending); + if (!host_can_wakeup_system(pdev)) { + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + fsl_usb_clk_gate(hcd->self.controller->platform_data, true); + } + usb_host_set_wakeup(hcd->self.controller, true); + + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + fsl_usb_clk_gate(hcd->self.controller->platform_data, false); + } + } + return 0; + } + if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + fsl_usb_clk_gate(hcd->self.controller->platform_data, true); + usb_host_set_wakeup(hcd->self.controller, false); + fsl_usb_lowpower_mode(pdata, false); + } + + /* set host mode */ + fsl_platform_set_host_mode(hcd); + + /* restore EHCI registers */ + ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); + ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); + ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); + ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); + ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); + ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); + ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); + ehci_writel(ehci, pdata->pm_configured_flag, + &ehci->regs->configured_flag); + + + tmp = ehci_readl(ehci, &ehci->regs->command); + tmp |= CMD_RUN; + ehci_writel(ehci, tmp, &ehci->regs->command); + + if ((hcd->state & HC_STATE_SUSPENDED)) { + printk(KERN_DEBUG "will resume roothub and its children\n"); + usb_lock_device(roothub); + usb_resume(&roothub->dev, PMSG_USER_RESUME); + usb_unlock_device(roothub); + } + + printk(KERN_DEBUG "ehci fsl drv resume ends: %s\n", pdata->name); + return 0; +} +#endif +MODULE_ALIAS("platform:fsl-ehci"); + +static struct platform_driver ehci_fsl_driver = { + .probe = ehci_fsl_drv_probe, + .remove = ehci_fsl_drv_remove, + .shutdown = usb_hcd_platform_shutdown, +#ifdef CONFIG_PM + .suspend = ehci_fsl_drv_suspend, + .resume = ehci_fsl_drv_resume, +#endif + .driver = { + .name = "fsl-ehci", + }, +}; diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h index b5e59db53347..8a12eec68a90 100644 --- a/drivers/usb/host/ehci-fsl.h +++ b/drivers/usb/host/ehci-fsl.h @@ -19,6 +19,9 @@ #define _EHCI_FSL_H /* offsets for the non-ehci registers in the FSL SOC USB controller */ +#define FSL_SOC_USB_SBUSCFG 0x90 +#define FSL_SOC_USB_BURSTSIZE 0x160 +#define FSL_SOC_USB_TXFILLTUNING 0x164 #define FSL_SOC_USB_ULPIVP 0x170 #define FSL_SOC_USB_PORTSC1 0x184 #define PORT_PTS_MSK (3<<30) @@ -26,8 +29,12 @@ #define PORT_PTS_ULPI (2<<30) #define PORT_PTS_SERIAL (3<<30) #define PORT_PTS_PTW (1<<28) +#define PORT_PTS_PHCD (1<<23) #define FSL_SOC_USB_PORTSC2 0x188 #define FSL_SOC_USB_USBMODE 0x1a8 +#define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ +#define USBMODE_ES (1 << 2) /* (Big) Endian Select */ + #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index a3ef2a9d9dc2..ea0145411ce1 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -304,8 +304,13 @@ static void end_unlink_async(struct ehci_hcd *ehci); static void ehci_work(struct ehci_hcd *ehci); #include "ehci-hub.c" +#ifdef CONFIG_USB_STATIC_IRAM +#include "ehci-mem-iram.c" +#include "ehci-q-iram.c" +#else #include "ehci-mem.c" #include "ehci-q.c" +#endif #include "ehci-sched.c" /*-------------------------------------------------------------------------*/ @@ -1123,6 +1128,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_hcd_omap_driver #endif +#ifdef CONFIG_USB_EHCI_ARC +#include "ehci-arc.c" +#define PLATFORM_DRIVER ehci_fsl_driver +#endif + #ifdef CONFIG_PPC_PS3 #include "ehci-ps3.c" #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver diff --git a/drivers/usb/host/ehci-mem-iram.c b/drivers/usb/host/ehci-mem-iram.c new file mode 100644 index 000000000000..fd7b42b22758 --- /dev/null +++ b/drivers/usb/host/ehci-mem-iram.c @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2001 by David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* this file is part of ehci-hcd.c */ + +/*-------------------------------------------------------------------------*/ + +/* + * There's basically three types of memory: + * - data used only by the HCD ... kmalloc is fine + * - async and periodic schedules, shared by HC and HCD ... these + * need to use dma_pool or dma_alloc_coherent + * - driver buffers, read/written by HC ... single shot DMA mapped + * + * There's also "register" data (e.g. PCI or SOC), which is memory mapped. + * No memory seen by this driver is pageable. + */ + +/*-------------------------------------------------------------------------*/ + +/* Allocate the key transfer structures from the previously allocated pool */ +#include +#include + +bool use_iram_qtd; + +struct memDesc { + u32 start; + u32 end; + struct memDesc *next; +} ; + +static u32 g_usb_pool_start; +static s32 g_usb_pool_count; +static u32 g_total_pages; +static u32 g_alignment = 32; +struct memDesc *g_allocated_desc; +static spinlock_t g_usb_sema; +static u32 g_debug_qtd_allocated; +static u32 g_debug_qH_allocated; +static int g_alloc_map; +static unsigned long g_iram_base; +static __iomem void *g_iram_addr; + +/*! + * usb_pool_initialize + * + * @param memPool start address of the pool + * @param poolSize memory pool size + * @param alignment alignment for example page alignmnet will be 4K + * + * @return 0 for success -1 for errors + */ +static int usb_pool_initialize(u32 memPool, u32 poolSize, u32 alignment) +{ + if (g_usb_pool_count) { + printk(KERN_INFO "usb_pool_initialize : already initialzed.\n"); + return 0; + } + + g_alignment = alignment; + if (g_alignment == 0) { + printk(KERN_INFO + "usb_pool_initialize : g_alignment can not be zero.\n"); + g_alignment = 32; + } + + g_total_pages = poolSize / g_alignment; + g_usb_pool_start = (u32) memPool; + + g_allocated_desc = kmalloc(sizeof(struct memDesc), GFP_KERNEL); + if (!g_allocated_desc) { + printk(KERN_ALERT "usb_pool_initialize : kmalloc failed \n"); + return (-1); + } + + g_allocated_desc->start = 0; + g_allocated_desc->end = 0; + g_allocated_desc->next = NULL; + + spin_lock_init(&g_usb_sema); + g_usb_pool_count++; + return (0); +} + +static void usb_pool_deinit() +{ + if (--g_usb_pool_count < 0) + g_usb_pool_count = 0; +} + +/*! + * usb_malloc + * + * @param size memory pool size + * + * @return physical address, 0 for error + */ +static u32 usb_malloc(u32 size, gfp_t mem_flags) +{ + unsigned long flags; + struct memDesc *prevDesc = NULL; + struct memDesc *nextDesc = NULL; + struct memDesc *currentDesc = NULL; + u32 pages = (size + g_alignment - 1) / g_alignment; + + if ((size == 0) || (pages > g_total_pages)) + return 0; + + currentDesc = kmalloc(sizeof(struct memDesc), mem_flags); + if (!currentDesc) { + printk(KERN_ALERT "usb_malloc: kmalloc failed \n"); + return 0; + } + + spin_lock_irqsave(&g_usb_sema, flags); + + /* Create the first Allocated descriptor */ + if (!g_allocated_desc->next) { + g_allocated_desc->next = currentDesc; + currentDesc->start = 0; + currentDesc->end = pages; + currentDesc->next = NULL; + spin_unlock_irqrestore(&g_usb_sema, flags); + return (g_usb_pool_start + currentDesc->start * g_alignment); + } + + /* Find the free spot */ + prevDesc = g_allocated_desc; + while (prevDesc->next) { + nextDesc = prevDesc->next; + if (pages <= nextDesc->start - prevDesc->end) { + currentDesc->start = prevDesc->end; + currentDesc->end = currentDesc->start + pages; + currentDesc->next = nextDesc; + prevDesc->next = currentDesc; + break; + } + prevDesc = nextDesc; + } + + /* Do not find the free spot inside the chain, append to the end */ + if (!prevDesc->next) { + if (pages > (g_total_pages - prevDesc->end)) { + spin_unlock_irqrestore(&g_usb_sema, flags); + kfree(currentDesc); + return 0; + } else { + currentDesc->start = prevDesc->end; + currentDesc->end = currentDesc->start + pages; + currentDesc->next = NULL; + prevDesc->next = currentDesc; + } + } + + spin_unlock_irqrestore(&g_usb_sema, flags); + return (g_usb_pool_start + currentDesc->start * g_alignment); +} + +/*! + * usb_free + * + * @param physical physical address try to free + * + */ +static void usb_free(u32 physical) +{ + unsigned long flags; + struct memDesc *prevDesc = NULL; + struct memDesc *nextDesc = NULL; + u32 pages = (physical - g_usb_pool_start) / g_alignment; + + /* Protect the memory pool data structures. */ + spin_lock_irqsave(&g_usb_sema, flags); + + prevDesc = g_allocated_desc; + while (prevDesc->next) { + nextDesc = prevDesc->next; + if (nextDesc->start == pages) { + prevDesc->next = nextDesc->next; + kfree(nextDesc); + break; + } + prevDesc = prevDesc->next; + } + /* All done with memory pool data structures. */ + spin_unlock_irqrestore(&g_usb_sema, flags); +} + +static int address_to_buffer(struct ehci_hcd *ehci, int address) +{ + int i; + + for (i = 0; i < IRAM_NTD; i++) { + if (ehci->usb_address[i] == address) + return i; + } + return IRAM_NTD; +} + +static void use_buffer(struct ehci_hcd *ehci, int address) +{ + int i; + + for (i = 0; i < IRAM_NTD; i++) { + if (ehci->usb_address[i] == address) + return; + } + + if (ehci->usb_address[0] == 0) { + ehci->usb_address[0] = address; + printk(KERN_INFO "usb_address[0] %x\n", address); + return; + } else if (ehci->usb_address[1] == 0) { + ehci->usb_address[1] = address; + printk(KERN_INFO "usb_address[1] %x\n", address); + return; + } else + printk(KERN_ALERT "qh_make run out of iRAM, already be used"); +} + +static u32 alloc_iram_buf(void) +{ + int i; + + for (i = 0; i < IRAM_NTD; i++) { + if (!(g_alloc_map & (1 << i))) { + g_alloc_map |= (1 << i); + return g_iram_base + i * (IRAM_TD_SIZE * 2); + } + } + panic("Out of IRAM buffers\n"); +} + +void free_iram_buf(u32 buf) +{ + int i = (buf - g_iram_base) / (IRAM_TD_SIZE * 2); + + g_alloc_map &= ~(1 << i); +} + +static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd, + dma_addr_t dma) +{ + memset(qtd, 0, sizeof *qtd); + qtd->qtd_dma = dma; + qtd->hw_token = cpu_to_le32(QTD_STS_HALT); + qtd->hw_next = EHCI_LIST_END(ehci); + qtd->hw_alt_next = EHCI_LIST_END(ehci); + INIT_LIST_HEAD(&qtd->qtd_list); +} + +static struct ehci_qtd *ehci_qtd_alloc(struct ehci_hcd *ehci, gfp_t flags) +{ + struct ehci_qtd *qtd; + dma_addr_t dma; + + if (use_iram_qtd) { + dma = usb_malloc(sizeof(struct ehci_qtd), flags); + if (dma != 0) + qtd = (struct ehci_qtd *)(g_iram_addr + (dma - g_iram_base)); + else + qtd = dma_pool_alloc(ehci->qtd_pool, flags, &dma); + } + else + qtd = dma_pool_alloc(ehci->qtd_pool, flags, &dma); + + if (qtd != NULL) { + ehci_qtd_init(ehci, qtd, dma); + ++g_debug_qtd_allocated; + } else { + panic + ("out of i-ram for qtd allocation g_debug_qtd_allocated %d \ + size%d \n", g_debug_qtd_allocated, + sizeof(struct ehci_qtd)); + } + return qtd; +} + +static inline void ehci_qtd_free(struct ehci_hcd *ehci, struct ehci_qtd *qtd) +{ + if ((qtd->qtd_dma & (g_iram_base & 0xFFF00000)) == + (g_iram_base & 0xFFF00000)) + usb_free(qtd->qtd_dma); + else + dma_pool_free(ehci->qtd_pool, qtd, qtd->qtd_dma); + --g_debug_qtd_allocated; +} + +static void qh_destroy(struct ehci_qh *qh) +{ + struct ehci_hcd *ehci = qh->ehci; + + /* clean qtds first, and know this is not linked */ + if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) { + ehci_dbg(ehci, "unused qh not empty!\n"); + BUG(); + } + if (qh->dummy) + ehci_qtd_free(ehci, qh->dummy); + int i; + for (i = 0; i < IRAM_NTD; i++) { + if (ehci->usb_address[i] == (qh->hw_info1 & 0x7F)) + ehci->usb_address[i] = 0; + } + + if ((qh->qh_dma & (g_iram_base & 0xFFF00000)) == + (g_iram_base & 0xFFF00000)) + usb_free(qh->qh_dma); + else + dma_pool_free(ehci->qh_pool, qh, qh->qh_dma); + --g_debug_qH_allocated; +} + +static struct ehci_qh *ehci_qh_alloc(struct ehci_hcd *ehci, gfp_t flags) +{ + struct ehci_qh *qh; + dma_addr_t dma; + + dma = usb_malloc(sizeof(struct ehci_qh), flags); + if (dma != 0) + qh = (struct ehci_qh *)(g_iram_addr + (dma - g_iram_base)); + else + qh = (struct ehci_qh *) + dma_pool_alloc(ehci->qh_pool, flags, &dma); + ++g_debug_qH_allocated; + if (qh == NULL) { + panic("run out of i-ram for qH allocation\n"); + return qh; + } + + memset(qh, 0, sizeof *qh); + qh->refcount = 1; + qh->ehci = ehci; + qh->qh_dma = dma; + INIT_LIST_HEAD(&qh->qtd_list); + + /* dummy td enables safe urb queuing */ + qh->dummy = ehci_qtd_alloc(ehci, flags); + if (qh->dummy == NULL) { + ehci_dbg(ehci, "no dummy td\n"); + dma_pool_free(ehci->qh_pool, qh, qh->qh_dma); + qh = NULL; + } + return qh; +} + +/* to share a qh (cpu threads, or hc) */ +static inline struct ehci_qh *qh_get(struct ehci_qh *qh) +{ + WARN_ON(!qh->refcount); + qh->refcount++; + return qh; +} + +static inline void qh_put(struct ehci_qh *qh) +{ + if (!--qh->refcount) + qh_destroy(qh); +} + +/*-------------------------------------------------------------------------*/ + +/* The queue heads and transfer descriptors are managed from pools tied + * to each of the "per device" structures. + * This is the initialisation and cleanup code. + */ + +static void ehci_mem_cleanup(struct ehci_hcd *ehci) +{ + if (ehci->async) + qh_put(ehci->async); + ehci->async = NULL; + + /* DMA consistent memory and pools */ + if (ehci->qtd_pool) + dma_pool_destroy(ehci->qtd_pool); + ehci->qtd_pool = NULL; + + if (ehci->qh_pool) { + dma_pool_destroy(ehci->qh_pool); + ehci->qh_pool = NULL; + } + + if (ehci->itd_pool) + dma_pool_destroy(ehci->itd_pool); + ehci->itd_pool = NULL; + + if (ehci->sitd_pool) + dma_pool_destroy(ehci->sitd_pool); + ehci->sitd_pool = NULL; + + if (ehci->periodic) + dma_free_coherent(ehci_to_hcd(ehci)->self.controller, + ehci->periodic_size * sizeof(u32), + ehci->periodic, ehci->periodic_dma); + ehci->periodic = NULL; + + if (ehci->iram_buffer[0]) + free_iram_buf(ehci->iram_buffer[0]); + if (ehci->iram_buffer[1]) + free_iram_buf(ehci->iram_buffer[1]); + + iounmap(g_iram_addr); + iram_free(g_iram_base, USB_IRAM_SIZE); + + /* shadow periodic table */ + kfree(ehci->pshadow); + ehci->pshadow = NULL; + usb_pool_deinit(); +} + +/* remember to add cleanup code (above) if you add anything here */ +static int ehci_mem_init(struct ehci_hcd *ehci, gfp_t flags) +{ + int i; + g_usb_pool_count = 0; + g_debug_qtd_allocated = 0; + g_debug_qH_allocated = 0; + g_alloc_map = 0; + + if (cpu_is_mx37()) + use_iram_qtd = 0; + else + use_iram_qtd = 1; + + g_iram_addr = iram_alloc(USB_IRAM_SIZE, &g_iram_base); + + usb_pool_initialize(g_iram_base + IRAM_TD_SIZE * IRAM_NTD * 2, + USB_IRAM_SIZE - IRAM_TD_SIZE * IRAM_NTD * 2, 32); + + if (!ehci->iram_buffer[0]) { + ehci->iram_buffer[0] = alloc_iram_buf(); + ehci->iram_buffer_v[0] = g_iram_addr + (ehci->iram_buffer[0] - g_iram_base); + ehci->iram_buffer[1] = alloc_iram_buf(); + ehci->iram_buffer_v[1] = g_iram_addr + (ehci->iram_buffer[1] - g_iram_base); + } + + /* QTDs for control/bulk/intr transfers */ + ehci->qtd_pool = dma_pool_create("ehci_qtd", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_qtd), + 32/* byte alignment (for hw parts) */ + , 4096 /* can't cross 4K */); + if (!ehci->qtd_pool) + goto fail; + + /* QHs for control/bulk/intr transfers */ + ehci->qh_pool = dma_pool_create("ehci_qh", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_qh), + 32 /* byte alignment (for hw parts) */ , + 4096 /* can't cross 4K */); + if (!ehci->qh_pool) + goto fail; + + ehci->async = ehci_qh_alloc(ehci, flags); + if (!ehci->async) + goto fail; + + /* ITD for high speed ISO transfers */ + ehci->itd_pool = dma_pool_create("ehci_itd", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_itd), + 32/* byte alignment (for hw parts) */ + , 4096 /* can't cross 4K */); + if (!ehci->itd_pool) + goto fail; + + /* SITD for full/low speed split ISO transfers */ + ehci->sitd_pool = dma_pool_create("ehci_sitd", + ehci_to_hcd(ehci)->self.controller, + sizeof(struct ehci_sitd), + 32/* byte alignment (for hw parts) */ + , 4096 /* can't cross 4K */); + if (!ehci->sitd_pool) + goto fail; + + ehci->periodic = (__le32 *) + dma_alloc_coherent(ehci_to_hcd(ehci)->self.controller, + ehci->periodic_size * sizeof(__le32), + &ehci->periodic_dma, 0); + + if (ehci->periodic == NULL) + goto fail; + + for (i = 0; i < ehci->periodic_size; i++) + ehci->periodic[i] = EHCI_LIST_END(ehci); + + /* software shadow of hardware table */ + ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags); + if (ehci->pshadow != NULL) + return 0; + +fail: + ehci_dbg(ehci, "couldn't init memory\n"); + ehci_mem_cleanup(ehci); + return -ENOMEM; +} diff --git a/drivers/usb/host/ehci-q-iram.c b/drivers/usb/host/ehci-q-iram.c new file mode 100644 index 000000000000..318888563380 --- /dev/null +++ b/drivers/usb/host/ehci-q-iram.c @@ -0,0 +1,1345 @@ +/* + * Copyright (C) 2001-2004 by David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#undef EHCI_NO_ERR_COUNT +static size_t g_iram_size = IRAM_TD_SIZE; + +/* this file is part of ehci-hcd.c */ + +/*-------------------------------------------------------------------------*/ + +/* + * EHCI hardware queue manipulation ... the core. QH/QTD manipulation. + * + * Control, bulk, and interrupt traffic all use "qh" lists. They list "qtd" + * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned + * buffers needed for the larger number). We use one QH per endpoint, queue + * multiple urbs (all three types) per endpoint. URBs may need several qtds. + * + * ISO traffic uses "ISO TD" (itd, and sitd) records, and (along with + * interrupts) needs careful scheduling. Performance improvements can be + * an ongoing challenge. That's in "ehci-sched.c". + * + * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs, + * or otherwise through transaction translators (TTs) in USB 2.0 hubs using + * (b) special fields in qh entries or (c) split iso entries. TTs will + * buffer low/full speed data so the host collects it at high speed. + */ + +/*-------------------------------------------------------------------------*/ +/* fill a qtd, returning how much of the buffer we were able to queue up */ +static int qtd_fill(struct ehci_hcd *ehci, struct ehci_qtd *qtd, dma_addr_t buf, + size_t len, int token, int maxpacket) +{ + int i, count; + u64 addr = buf; + struct urb *urb = qtd->urb; + + if (usb_pipebulk(urb->pipe) && + (address_to_buffer(ehci, usb_pipedevice(urb->pipe)) != 2)) { + urb->use_iram = 1; + qtd->buffer_offset = (size_t) (buf - urb->transfer_dma); + token |= QTD_IOC; + if (usb_pipeout(urb->pipe)) { + addr = ehci->iram_buffer[address_to_buffer(ehci, + usb_pipedevice(urb->pipe))]; + } else if (usb_pipein(urb->pipe)) { + addr = ehci->iram_buffer[address_to_buffer(ehci, + usb_pipedevice(urb->pipe))] + + g_iram_size; + } + } else { + urb->use_iram = 0; + addr = buf; + } + len = min(g_iram_size, len); + + /* one buffer entry per 4K ... first might be short or unaligned */ + qtd->hw_buf[0] = cpu_to_hc32(ehci, (u32) addr); + qtd->hw_buf_hi[0] = cpu_to_hc32(ehci, (u32) (addr >> 32)); + count = 0x1000 - (buf & 0x0fff); /* rest of that page */ + if (likely(len < count)) /* ... iff needed */ + count = len; + else { + buf += 0x1000; + buf &= ~0x0fff; + + /* per-qtd limit: from 16K to 20K (best alignment) */ + for (i = 1; count < len && i < 5; i++) { + addr = buf; + qtd->hw_buf[i] = cpu_to_hc32(ehci, (u32) addr); + qtd->hw_buf_hi[i] = + cpu_to_hc32(ehci, (u32) (addr >> 32)); + buf += 0x1000; + if ((count + 0x1000) < len) + count += 0x1000; + else + count = len; + } + + /* short packets may only terminate transfers */ + if (count != len) + count -= (count % maxpacket); + } + qtd->hw_token = cpu_to_hc32(ehci, (count << 16) | token); + qtd->length = count; + + return count; +} + +/*-------------------------------------------------------------------------*/ + +static inline void +qh_update(struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd) +{ + /* writes to an active overlay are unsafe */ + BUG_ON(qh->qh_state != QH_STATE_IDLE); + + qh->hw_qtd_next = QTD_NEXT(ehci, qtd->qtd_dma); + qh->hw_alt_next = EHCI_LIST_END(ehci); + + /* Except for control endpoints, we make hardware maintain data + * toggle (like OHCI) ... here (re)initialize the toggle in the QH, + * and set the pseudo-toggle in udev. Only usb_clear_halt() will + * ever clear it. + */ + if (!(qh->hw_info1 & cpu_to_hc32(ehci, 1 << 14))) { + unsigned is_out, epnum; + + is_out = !(qtd->hw_token & cpu_to_hc32(ehci, 1 << 8)); + epnum = (hc32_to_cpup(ehci, &qh->hw_info1) >> 8) & 0x0f; + if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) { + qh->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE); + usb_settoggle(qh->dev, epnum, is_out, 1); + } + } + + /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */ + wmb(); + qh->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING); +} + +/* if it weren't for a common silicon quirk (writing the dummy into the qh + * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault + * recovery (including urb dequeue) would need software changes to a QH... + */ +static void qh_refresh(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + struct ehci_qtd *qtd; + + if (list_empty(&qh->qtd_list)) + qtd = qh->dummy; + else { + qtd = list_entry(qh->qtd_list.next, struct ehci_qtd, qtd_list); + /* first qtd may already be partially processed */ + if (cpu_to_hc32(ehci, qtd->qtd_dma) == qh->hw_current) + qtd = NULL; + } + + if (qtd) + qh_update(ehci, qh, qtd); +} + +/*-------------------------------------------------------------------------*/ + +static int qtd_copy_status(struct ehci_hcd *ehci, + struct urb *urb, size_t length, u32 token) +{ + int status = -EINPROGRESS; + + /* count IN/OUT bytes, not SETUP (even short packets) */ + if (likely(QTD_PID(token) != 2)) + urb->actual_length += length - QTD_LENGTH(token); + + /* don't modify error codes */ + if (unlikely(urb->unlinked)) + return status; + + /* force cleanup after short read; not always an error */ + if (unlikely(IS_SHORT_READ(token))) + status = -EREMOTEIO; + + /* serious "can't proceed" faults reported by the hardware */ + if (token & QTD_STS_HALT) { + if (token & QTD_STS_BABBLE) { + /* FIXME "must" disable babbling device's port too */ + status = -EOVERFLOW; + } else if (token & QTD_STS_MMF) { + /* fs/ls interrupt xfer missed the complete-split */ + status = -EPROTO; + } else if (token & QTD_STS_DBE) { + status = (QTD_PID(token) == 1) /* IN ? */ + ? -ENOSR /* hc couldn't read data */ + : -ECOMM; /* hc couldn't write data */ + } else if (token & QTD_STS_XACT) { + /* timeout, bad crc, wrong PID, etc; retried */ + if (QTD_CERR(token)) + status = -EPIPE; + else { + ehci_dbg(ehci, "devpath %s ep%d%s 3strikes\n", + urb->dev->devpath, + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "in" : "out"); + status = -EPROTO; + } + /* CERR nonzero + no errors + halt --> stall */ + } else if (QTD_CERR(token)) + status = -EPIPE; + else /* unknown */ + status = -EPROTO; + + ehci_vdbg(ehci, + "dev%d ep%d%s qtd token %08x --> status %d\n", + usb_pipedevice(urb->pipe), + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "in" : "out", token, status); + + /* if async CSPLIT failed, try cleaning out the TT buffer */ + if (status != -EPIPE && urb->dev->tt && !usb_pipeint(urb->pipe) + && ((token & QTD_STS_MMF) != 0 || QTD_CERR(token) == 0) + && (!ehci_is_TDI(ehci) + || urb->dev->tt->hub != + ehci_to_hcd(ehci)->self.root_hub)) { +#ifdef DEBUG + struct usb_device *tt = urb->dev->tt->hub; + dev_dbg(&tt->dev, + "clear tt buffer port %d, a%d ep%d t%08x\n", + urb->dev->ttport, urb->dev->devnum, + usb_pipeendpoint(urb->pipe), token); +#endif /* DEBUG */ + /* REVISIT ARC-derived cores don't clear the root + * hub TT buffer in this way... + */ + usb_hub_tt_clear_buffer(urb->dev, urb->pipe); + } + } + + return status; +} + +static void +ehci_urb_done(struct ehci_hcd *ehci, struct urb *urb, int status) +__releases(ehci->lock) __acquires(ehci->lock) +{ + if (likely(urb->hcpriv != NULL)) { + struct ehci_qh *qh = (struct ehci_qh *)urb->hcpriv; + + /* S-mask in a QH means it's an interrupt urb */ + if ((qh->hw_info2 & cpu_to_hc32(ehci, QH_SMASK)) != 0) { + + /* ... update hc-wide periodic stats (for usbfs) */ + ehci_to_hcd(ehci)->self.bandwidth_int_reqs--; + } + qh_put(qh); + } + + if (unlikely(urb->unlinked)) { + COUNT(ehci->stats.unlink); + } else { + /* report non-error and short read status as zero */ + if (status == -EINPROGRESS || status == -EREMOTEIO) + status = 0; + COUNT(ehci->stats.complete); + } + +#ifdef EHCI_URB_TRACE + ehci_dbg(ehci, + "%s %s urb %p ep%d%s status %d len %d/%d\n", + __func__, urb->dev->devpath, urb, + usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "in" : "out", + status, urb->actual_length, urb->transfer_buffer_length); +#endif + + /* complete() can reenter this HCD */ + usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); + spin_unlock(&ehci->lock); + usb_hcd_giveback_urb(ehci_to_hcd(ehci), urb, status); + spin_lock(&ehci->lock); +} + +static void start_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh); +static void unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh); + +static void intr_deschedule(struct ehci_hcd *ehci, struct ehci_qh *qh); +static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh); + +/* + * Process and free completed qtds for a qh, returning URBs to drivers. + * Chases up to qh->hw_current. Returns number of completions called, + * indicating how much "real" work we did. + */ +static unsigned qh_completions(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + struct ehci_qtd *last = NULL, *end = qh->dummy; + struct list_head *entry, *tmp; + int last_status = -EINPROGRESS; + int stopped; + unsigned count = 0; + u8 state; + __le32 halt = HALT_BIT(ehci); + __hc32 temp_hw_qtd_next = 0; + + if (unlikely(list_empty(&qh->qtd_list))) + return count; + + /* completions (or tasks on other cpus) must never clobber HALT + * till we've gone through and cleaned everything up, even when + * they add urbs to this qh's queue or mark them for unlinking. + * + * NOTE: unlinking expects to be done in queue order. + */ + state = qh->qh_state; + qh->qh_state = QH_STATE_COMPLETING; + stopped = (state == QH_STATE_IDLE); + + /* remove de-activated QTDs from front of queue. + * after faults (including short reads), cleanup this urb + * then let the queue advance. + * if queue is stopped, handles unlinks. + */ + list_for_each_safe(entry, tmp, &qh->qtd_list) { + struct ehci_qtd *qtd; + struct urb *urb; + struct ehci_qtd *qtd2; + struct urb *urb2; + + u32 token = 0; + + qtd = list_entry(entry, struct ehci_qtd, qtd_list); + urb = qtd->urb; + + /* clean up any state from previous QTD ... */ + if (last) { + if (likely(last->urb != urb)) { + ehci_urb_done(ehci, last->urb, last_status); + count++; + last_status = -EINPROGRESS; + } + ehci_qtd_free(ehci, last); + last = NULL; + } + + /* ignore urbs submitted during completions we reported */ + if (qtd == end) + break; + + /* hardware copies qtd out of qh overlay */ + rmb(); + token = hc32_to_cpu(ehci, qtd->hw_token); + + /* always clean up qtds the hc de-activated */ + if ((token & QTD_STS_ACTIVE) == 0) { + + /* on STALL, error, and short reads this urb must + * complete and all its qtds must be recycled. + */ + if ((token & QTD_STS_HALT) != 0) { + stopped = 1; + + /* magic dummy for some short reads; qh won't advance. + * that silicon quirk can kick in with this dummy too. + * + * other short reads won't stop the queue, including + * control transfers (status stage handles that) or + * most other single-qtd reads ... the queue stops if + * URB_SHORT_NOT_OK was set so the driver submitting + * the urbs could clean it up. + */ + } else if (IS_SHORT_READ(token) + && !(qtd->hw_alt_next & EHCI_LIST_END(ehci))) { + if (urb->use_iram && usb_pipein(urb->pipe)) { + if (urb->transfer_buffer == NULL) { + memcpy(phys_to_virt + (urb->transfer_dma) + + qtd->buffer_offset, + ehci-> + iram_buffer_v + [address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] + + g_iram_size, + min(g_iram_size, + qtd->length)); + } else { + memcpy(urb->transfer_buffer + + qtd->buffer_offset, + ehci-> + iram_buffer_v + [address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] + + g_iram_size, + min(g_iram_size, + qtd->length)); + } + } + stopped = 1; + goto halt; + } else if (urb->use_iram && (!qtd->last_one) + && usb_pipeout(urb->pipe)) { + ehci-> + iram_in_use[address_to_buffer + (ehci, + usb_pipedevice(urb->pipe))] = + 1; + qtd2 = + list_entry(tmp, struct ehci_qtd, qtd_list); + if (urb->transfer_buffer == NULL) { + memcpy(ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))], + phys_to_virt(urb->transfer_dma) + + qtd->buffer_offset + qtd->length, + min(g_iram_size, qtd2->length)); + } else { + memcpy(ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))], + urb->transfer_buffer + + qtd->buffer_offset + qtd->length, + min(g_iram_size, qtd2->length)); + } + temp_hw_qtd_next = + QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE; + } else if (urb->use_iram && (qtd->last_one) + && usb_pipeout(urb->pipe)) { + urb->use_iram = 0; + qtd2 = + list_entry(tmp, struct ehci_qtd, qtd_list); + if (tmp != &qh->qtd_list) { + urb2 = qtd2->urb; + if (urb2 && urb2->use_iram == 1) { + ehci-> + iram_in_use + [address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] = + 1; + if (urb2->transfer_buffer == + NULL) { + memcpy(ehci-> + iram_buffer_v + [address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))], + phys_to_virt + (urb2-> + transfer_dma), + min(g_iram_size, + qtd2-> + length)); + } else { + memcpy(ehci-> + iram_buffer_v + [address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))], + urb2-> + transfer_buffer, + min(g_iram_size, + qtd2-> + length)); + } + } else { + ehci-> + iram_in_use + [address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] = + 0; + } + } else { + ehci-> + iram_in_use[address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))] + = 0; + } + temp_hw_qtd_next = + QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE; + } else if (urb->use_iram && usb_pipein(urb->pipe)) { + if (urb->transfer_buffer == NULL) { + memcpy(phys_to_virt(urb->transfer_dma) + + qtd->buffer_offset, + ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))] + + g_iram_size, min(g_iram_size, + qtd->length)); + } else { + memcpy(urb->transfer_buffer + + qtd->buffer_offset, + ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice + (urb->pipe))] + + g_iram_size, min(g_iram_size, + qtd->length)); + } + temp_hw_qtd_next = + QTD_NEXT(ehci, qtd->hw_next) & 0xFFFFFFFE; + } + /* stop scanning when we reach qtds the hc is using */ + } else if (likely(!stopped + && HC_IS_RUNNING(ehci_to_hcd(ehci)->state))) { + break; + + /* scan the whole queue for unlinks whenever it stops */ + } else { + stopped = 1; + + /* cancel everything if we halt, suspend, etc */ + if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) + last_status = -ESHUTDOWN; + + /* this qtd is active; skip it unless a previous qtd + * for its urb faulted, or its urb was canceled. + */ + else if (last_status == -EINPROGRESS && !urb->unlinked) + continue; + + /* qh unlinked; token in overlay may be most current */ + if (state == QH_STATE_IDLE + && cpu_to_hc32(ehci, qtd->qtd_dma) + == qh->hw_current) + token = hc32_to_cpu(ehci, qh->hw_token); + + /* qh unlinked; token in overlay may be most current */ + if (state == QH_STATE_IDLE + && cpu_to_hc32(ehci, qtd->qtd_dma) + == qh->hw_current) + token = hc32_to_cpu(ehci, qh->hw_token); + + /* force halt for unlinked or blocked qh, so we'll + * patch the qh later and so that completions can't + * activate it while we "know" it's stopped. + */ + if ((halt & qh->hw_token) == 0) { +halt: + qh->hw_token |= halt; + wmb(); + } + } + + /* unless we already know the urb's status, collect qtd status + * and update count of bytes transferred. in common short read + * cases with only one data qtd (including control transfers), + * queue processing won't halt. but with two or more qtds (for + * example, with a 32 KB transfer), when the first qtd gets a + * short read the second must be removed by hand. + */ + if (last_status == -EINPROGRESS) { + last_status = qtd_copy_status(ehci, urb, + qtd->length, token); + if (last_status == -EREMOTEIO + && (qtd->hw_alt_next + & EHCI_LIST_END(ehci))) + last_status = -EINPROGRESS; + } + + /* if we're removing something not at the queue head, + * patch the hardware queue pointer. + */ + + if (stopped && qtd->qtd_list.prev != &qh->qtd_list) { + last = list_entry(qtd->qtd_list.prev, + struct ehci_qtd, qtd_list); + last->hw_next = qtd->hw_next; + } + +/* remove qtd; it's recycled after possible urb completion */ + list_del(&qtd->qtd_list); + last = qtd; + } + + /* last urb's completion might still need calling */ + if (likely(last != NULL)) { + ehci_urb_done(ehci, last->urb, last_status); + count++; + ehci_qtd_free(ehci, last); + } + + /* restore original state; caller must unlink or relink */ + qh->qh_state = state; + + /* be sure the hardware's done with the qh before refreshing + * it after fault cleanup, or recovering from silicon wrongly + * overlaying the dummy qtd (which reduces DMA chatter). + */ + if ((stopped != 0) || (qh->hw_qtd_next == EHCI_LIST_END(ehci)) + && (temp_hw_qtd_next == 0)) { + switch (state) { + case QH_STATE_IDLE: + qh_refresh(ehci, qh); + break; + case QH_STATE_LINKED: + /* We won't refresh a QH that's linked (after the HC + * stopped the queue). That avoids a race: + * - HC reads first part of QH; + * - CPU updates that first part and the token; + * - HC reads rest of that QH, including token + * Result: HC gets an inconsistent image, and then + * DMAs to/from the wrong memory (corrupting it). + * + * That should be rare for interrupt transfers, + * except maybe high bandwidth ... + */ + if ((cpu_to_hc32(ehci, QH_SMASK) + & qh->hw_info2) != 0) { + intr_deschedule(ehci, qh); + (void)qh_schedule(ehci, qh); + } else + unlink_async(ehci, qh); + break; + /* otherwise, unlink already started */ + } + } + if (temp_hw_qtd_next) + qh->hw_qtd_next = temp_hw_qtd_next; + + return count; +} + +/*-------------------------------------------------------------------------*/ + +/* high bandwidth multiplier, as encoded in highspeed endpoint descriptors */ +#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) +/* ... and packet size, for any kind of endpoint descriptor */ +#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) + +/* + * reverse of qh_urb_transaction: free a list of TDs. + * used for cleanup after errors, before HC sees an URB's TDs. + */ +static void qtd_list_free(struct ehci_hcd *ehci, + struct urb *urb, struct list_head *qtd_list) +{ + struct list_head *entry, *temp; + + list_for_each_safe(entry, temp, qtd_list) { + struct ehci_qtd *qtd; + + qtd = list_entry(entry, struct ehci_qtd, qtd_list); + list_del(&qtd->qtd_list); + ehci_qtd_free(ehci, qtd); + } +} + +/* + * create a list of filled qtds for this URB; won't link into qh. + */ +static struct list_head *qh_urb_transaction(struct ehci_hcd *ehci, + struct urb *urb, + struct list_head *head, gfp_t flags) +{ + struct ehci_qtd *qtd, *qtd_prev; + dma_addr_t buf; + int len, maxpacket; + int is_input; + u32 token; + + /* + * URBs map to sequences of QTDs: one logical transaction + */ + qtd = ehci_qtd_alloc(ehci, flags); + if (unlikely(!qtd)) + return NULL; + list_add_tail(&qtd->qtd_list, head); + qtd->urb = urb; + + token = QTD_STS_ACTIVE; + token |= (EHCI_TUNE_CERR << 10); + /* for split transactions, SplitXState initialized to zero */ + + len = urb->transfer_buffer_length; + is_input = usb_pipein(urb->pipe); + if (usb_pipecontrol(urb->pipe)) { + /* SETUP pid */ + qtd_fill(ehci, qtd, urb->setup_dma, + sizeof(struct usb_ctrlrequest), + token | (2 /* "setup" */ << 8), 8); + + /* ... and always at least one more pid */ + token ^= QTD_TOGGLE; + qtd_prev = qtd; + qtd = ehci_qtd_alloc(ehci, flags); + if (unlikely(!qtd)) + goto cleanup; + qtd->urb = urb; + qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); + list_add_tail(&qtd->qtd_list, head); + + /* for zero length DATA stages, STATUS is always IN */ + if (len == 0) + token |= (1 /* "in" */ << 8); + } + + /* + * data transfer stage: buffer setup + */ + buf = urb->transfer_dma; + + if (is_input) + token |= (1 /* "in" */ << 8); + /* else it's already initted to "out" pid (0 << 8) */ + + maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); + + /* + * buffer gets wrapped in one or more qtds; + * last one may be "short" (including zero len) + * and may serve as a control status ack + */ + for (;;) { + int this_qtd_len; + this_qtd_len = qtd_fill(ehci, qtd, buf, len, token, maxpacket); + if (urb->use_iram && (!qtd->buffer_offset) + && usb_pipeout(urb->pipe) + && (ehci-> + iram_in_use[address_to_buffer + (ehci, usb_pipedevice(urb->pipe))] == 0)) { + ehci-> + iram_in_use[address_to_buffer + (ehci, usb_pipedevice(urb->pipe))] = 1; + if (urb->transfer_buffer == NULL) { + memcpy(ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))], + phys_to_virt(urb->transfer_dma), + min((int)g_iram_size, len)); + } else { + memcpy(ehci-> + iram_buffer_v[address_to_buffer + (ehci, + usb_pipedevice(urb-> + pipe))], + urb->transfer_buffer, + min((int)g_iram_size, len)); + } + } + len -= this_qtd_len; + buf += this_qtd_len; + + /* + * short reads advance to a "magic" dummy instead of the next + * qtd ... that forces the queue to stop, for manual cleanup. + * (this will usually be overridden later.) + */ + if (is_input) + qtd->hw_alt_next = ehci->async->hw_alt_next; + + /* qh makes control packets use qtd toggle; maybe switch it */ + if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) + token ^= QTD_TOGGLE; + + if (likely(len <= 0)) { + qtd->last_one = 1; + break; + } + qtd_prev = qtd; + qtd = ehci_qtd_alloc(ehci, flags); + if (unlikely(!qtd)) + goto cleanup; + qtd->urb = urb; + if (urb->use_iram) + qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma) | 0x1; + else + qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); + + list_add_tail(&qtd->qtd_list, head); + } + + /* + * unless the caller requires manual cleanup after short reads, + * have the alt_next mechanism keep the queue running after the + * last data qtd (the only one, for control and most other cases). + */ + if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 + || usb_pipecontrol(urb->pipe))) + qtd->hw_alt_next = EHCI_LIST_END(ehci); + + /* + * control requests may need a terminating data "status" ack; + * bulk ones may need a terminating short packet (zero length). + */ + if (likely(urb->transfer_buffer_length != 0)) { + int one_more = 0; + + if (usb_pipecontrol(urb->pipe)) { + one_more = 1; + token ^= 0x0100; /* "in" <--> "out" */ + token |= QTD_TOGGLE; /* force DATA1 */ + } else if (usb_pipebulk(urb->pipe) + && (urb->transfer_flags & URB_ZERO_PACKET) + && !(urb->transfer_buffer_length % maxpacket)) + one_more = 1; + if (one_more) { + qtd_prev = qtd; + qtd = ehci_qtd_alloc(ehci, flags); + if (unlikely(!qtd)) + goto cleanup; + qtd->urb = urb; + qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); + list_add_tail(&qtd->qtd_list, head); + + /* never any data in such packets */ + qtd_fill(ehci, qtd, 0, 0, token, 0); + } + } + + /* by default, enable interrupt on urb completion */ + if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT))) + qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC); + return head; + +cleanup: + qtd_list_free(ehci, urb, head); + return NULL; +} + +/*-------------------------------------------------------------------------*/ + +/* Would be best to create all qh's from config descriptors, + * when each interface/altsetting is established. Unlink + * any previous qh and cancel its urbs first; endpoints are + * implicitly reset then (data toggle too). + * That'd mean updating how usbcore talks to HCDs. (2.7?) + */ + +/* + * Each QH holds a qtd list; a QH is used for everything except iso. + * + * For interrupt urbs, the scheduler must set the microframe scheduling + * mask(s) each time the QH gets scheduled. For highspeed, that's + * just one microframe in the s-mask. For split interrupt transactions + * there are additional complications: c-mask, maybe FSTNs. + */ +static struct ehci_qh *qh_make(struct ehci_hcd *ehci, + struct urb *urb, gfp_t flags) +{ + struct ehci_qh *qh = ehci_qh_alloc(ehci, flags); + u32 info1 = 0, info2 = 0; + int is_input, type; + int maxp = 0; + struct usb_tt *tt = urb->dev->tt; + + if (!qh) + return qh; + + /* + * init endpoint/device data for this QH + */ + info1 |= usb_pipeendpoint(urb->pipe) << 8; + info1 |= usb_pipedevice(urb->pipe) << 0; + + is_input = usb_pipein(urb->pipe); + type = usb_pipetype(urb->pipe); + maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input); + + /* 1024 byte maxpacket is a hardware ceiling. High bandwidth + * acts like up to 3KB, but is built from smaller packets. + */ + if (max_packet(maxp) > 1024) { + ehci_dbg(ehci, "bogus qh maxpacket %d\n", max_packet(maxp)); + goto done; + } + + /* Compute interrupt scheduling parameters just once, and save. + * - allowing for high bandwidth, how many nsec/uframe are used? + * - split transactions need a second CSPLIT uframe; same question + * - splits also need a schedule gap (for full/low speed I/O) + * - qh has a polling interval + * + * For control/bulk requests, the HC or TT handles these. + */ + if (type == PIPE_INTERRUPT) { + qh->usecs = + NS_TO_US(usb_calc_bus_time + (USB_SPEED_HIGH, is_input, 0, + hb_mult(maxp) * max_packet(maxp))); + qh->start = NO_FRAME; + + if (urb->dev->speed == USB_SPEED_HIGH) { + qh->c_usecs = 0; + qh->gap_uf = 0; + + qh->period = urb->interval >> 3; + if (qh->period == 0 && urb->interval != 1) { + /* NOTE interval 2 or 4 uframes could work. + * But interval 1 scheduling is simpler, and + * includes high bandwidth. + */ + dbg("intr period %d uframes, NYET!", + urb->interval); + goto done; + } + } else { + int think_time; + + /* gap is f(FS/LS transfer times) */ + qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed, + is_input, 0, + maxp) / (125 * 1000); + + /* FIXME this just approximates SPLIT/CSPLIT times */ + if (is_input) { + qh->c_usecs = qh->usecs + HS_USECS(0); + qh->usecs = HS_USECS(1); + } else { + qh->usecs += HS_USECS(1); + qh->c_usecs = HS_USECS(0); + } + + think_time = tt ? tt->think_time : 0; + qh->tt_usecs = NS_TO_US(think_time + + usb_calc_bus_time(urb->dev-> + speed, + is_input, 0, + max_packet + (maxp))); + qh->period = urb->interval; + } + } + + /* support for tt scheduling, and access to toggles */ + qh->dev = urb->dev; + + /* using TT? */ + switch (urb->dev->speed) { + case USB_SPEED_LOW: + info1 |= (1 << 12); /* EPS "low" */ + /* FALL THROUGH */ + + case USB_SPEED_FULL: + /* EPS 0 means "full" */ + if (type != PIPE_INTERRUPT) + info1 |= (EHCI_TUNE_RL_TT << 28); + if (type == PIPE_CONTROL) { + info1 |= (1 << 27); /* for TT */ + info1 |= 1 << 14; /* toggle from qtd */ + } + info1 |= maxp << 16; + + info2 |= (EHCI_TUNE_MULT_TT << 30); + + /* Some Freescale processors have an erratum in which the + * port number in the queue head was 0..N-1 instead of 1..N. + */ + if (ehci_has_fsl_portno_bug(ehci)) + info2 |= (urb->dev->ttport - 1) << 23; + else + info2 |= urb->dev->ttport << 23; + + /* set the address of the TT; for TDI's integrated + * root hub tt, leave it zeroed. + */ + if (tt && tt->hub != ehci_to_hcd(ehci)->self.root_hub) + info2 |= tt->hub->devnum << 16; + + /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */ + + break; + + case USB_SPEED_HIGH: /* no TT involved */ + info1 |= (2 << 12); /* EPS "high" */ + if (type == PIPE_CONTROL) { + info1 |= (EHCI_TUNE_RL_HS << 28); + info1 |= 64 << 16; /* usb2 fixed maxpacket */ + info1 |= 1 << 14; /* toggle from qtd */ + info2 |= (EHCI_TUNE_MULT_HS << 30); + } else if (type == PIPE_BULK) { + info1 |= (EHCI_TUNE_RL_HS << 28); + /* The USB spec says that high speed bulk endpoints + * always use 512 byte maxpacket. But some device + * vendors decided to ignore that, and MSFT is happy + * to help them do so. So now people expect to use + * such nonconformant devices with Linux too; sigh. + */ + info1 |= max_packet(maxp) << 16; + info2 |= (EHCI_TUNE_MULT_HS << 30); + use_buffer(ehci, usb_pipedevice(urb->pipe)); + } else { /* PIPE_INTERRUPT */ + info1 |= max_packet(maxp) << 16; + info2 |= hb_mult(maxp) << 30; + } + break; + default: + dbg("bogus dev %p speed %d", urb->dev, urb->dev->speed); +done: + qh_put(qh); + return NULL; + } + + /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */ + + /* init as live, toggle clear, advance to dummy */ + qh->qh_state = QH_STATE_IDLE; + qh->hw_info1 = cpu_to_hc32(ehci, info1); + qh->hw_info2 = cpu_to_hc32(ehci, info2); + usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1); + qh_refresh(ehci, qh); + return qh; +} + +/*-------------------------------------------------------------------------*/ + +/* move qh (and its qtds) onto async queue; maybe enable queue. */ + +static void qh_link_async(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + __hc32 dma = QH_NEXT(ehci, qh->qh_dma); + struct ehci_qh *head; + + /* (re)start the async schedule? */ + head = ehci->async; + timer_action_done(ehci, TIMER_ASYNC_OFF); + if (!head->qh_next.qh) { + u32 cmd = ehci_readl(ehci, &ehci->regs->command); + + if (!(cmd & CMD_ASE)) { + /* in case a clear of CMD_ASE didn't take yet */ + (void)handshake(ehci, &ehci->regs->status, + STS_ASS, 0, 150); + cmd |= CMD_ASE | CMD_RUN; + ehci_writel(ehci, cmd, &ehci->regs->command); + ehci_to_hcd(ehci)->state = HC_STATE_RUNNING; + /* posted write need not be known to HC yet ... */ + } + } + + /* clear halt and/or toggle; and maybe recover from silicon quirk */ + if (qh->qh_state == QH_STATE_IDLE) + qh_refresh(ehci, qh); + + /* splice right after start */ + qh->qh_next = head->qh_next; + qh->hw_next = head->hw_next; + wmb(); + + head->qh_next.qh = qh; + head->hw_next = dma; + + qh->qh_state = QH_STATE_LINKED; + /* qtd completions reported later by interrupt */ +} + +/*-------------------------------------------------------------------------*/ + +/* + * For control/bulk/interrupt, return QH with these TDs appended. + * Allocates and initializes the QH if necessary. + * Returns null if it can't allocate a QH it needs to. + * If the QH has TDs (urbs) already, that's great. + */ +static struct ehci_qh *qh_append_tds(struct ehci_hcd *ehci, + struct urb *urb, + struct list_head *qtd_list, + int epnum, void **ptr) +{ + struct ehci_qh *qh = NULL; + __hc32 qh_addr_mask = cpu_to_hc32(ehci, 0x7f); + + qh = (struct ehci_qh *)*ptr; + if (unlikely(qh == NULL)) { + /* can't sleep here, we have ehci->lock... */ + qh = qh_make(ehci, urb, GFP_ATOMIC); + *ptr = qh; + } + if (likely(qh != NULL)) { + struct ehci_qtd *qtd; + + if (unlikely(list_empty(qtd_list))) + qtd = NULL; + else + qtd = list_entry(qtd_list->next, struct ehci_qtd, + qtd_list); + + /* control qh may need patching ... */ + if (unlikely(epnum == 0)) { + + /* usb_reset_device() briefly reverts to address 0 */ + if (usb_pipedevice(urb->pipe) == 0) + qh->hw_info1 &= ~qh_addr_mask; + } + + /* just one way to queue requests: swap with the dummy qtd. + * only hc or qh_refresh() ever modify the overlay. + */ + if (likely(qtd != NULL)) { + struct ehci_qtd *dummy; + dma_addr_t dma; + __hc32 token; + + /* to avoid racing the HC, use the dummy td instead of + * the first td of our list (becomes new dummy). both + * tds stay deactivated until we're done, when the + * HC is allowed to fetch the old dummy (4.10.2). + */ + token = qtd->hw_token; + qtd->hw_token = HALT_BIT(ehci); + wmb(); + dummy = qh->dummy; + + dma = dummy->qtd_dma; + *dummy = *qtd; + dummy->qtd_dma = dma; + + list_del(&qtd->qtd_list); + list_add(&dummy->qtd_list, qtd_list); + __list_splice(qtd_list, qh->qtd_list.prev); + + ehci_qtd_init(ehci, qtd, qtd->qtd_dma); + qh->dummy = qtd; + + /* hc must see the new dummy at list end */ + dma = qtd->qtd_dma; + qtd = list_entry(qh->qtd_list.prev, + struct ehci_qtd, qtd_list); + if (urb->use_iram) + qtd->hw_next = QTD_NEXT(ehci, dma) | 0x1; + else + qtd->hw_next = QTD_NEXT(ehci, dma); + + /* let the hc process these next qtds */ + wmb(); + dummy->hw_token = token; + + urb->hcpriv = qh_get(qh); + } + } + return qh; +} + +/*-------------------------------------------------------------------------*/ + +static int +submit_async(struct ehci_hcd *ehci, + struct urb *urb, struct list_head *qtd_list, gfp_t mem_flags) +{ + struct ehci_qtd *qtd; + int epnum; + unsigned long flags; + struct ehci_qh *qh = NULL; + int rc; + + qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list); + epnum = urb->ep->desc.bEndpointAddress; + +#ifdef EHCI_URB_TRACE + ehci_dbg(ehci, + "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", + __func__, urb->dev->devpath, urb, + epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", + urb->transfer_buffer_length, qtd, urb->ep->hcpriv); +#endif + + spin_lock_irqsave(&ehci->lock, flags); + if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, + &ehci_to_hcd(ehci)->flags))) { + rc = -ESHUTDOWN; + goto done; + } + rc = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); + if (unlikely(rc)) + goto done; + + qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); + if (unlikely(qh == NULL)) { + usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); + rc = -ENOMEM; + goto done; + } + + /* Control/bulk operations through TTs don't need scheduling, + * the HC and TT handle it when the TT has a buffer ready. + */ + if (likely(qh->qh_state == QH_STATE_IDLE)) + qh_link_async(ehci, qh_get(qh)); +done: + spin_unlock_irqrestore(&ehci->lock, flags); + if (unlikely(qh == NULL)) + qtd_list_free(ehci, urb, qtd_list); + return rc; +} + +/*-------------------------------------------------------------------------*/ + +/* the async qh for the qtds being reclaimed are now unlinked from the HC */ + +static void end_unlink_async(struct ehci_hcd *ehci) +{ + struct ehci_qh *qh = ehci->reclaim; + struct ehci_qh *next; + + iaa_watchdog_done(ehci); + + qh->qh_state = QH_STATE_IDLE; + qh->qh_next.qh = NULL; + qh_put(qh); /* refcount from reclaim */ + + /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */ + next = qh->reclaim; + ehci->reclaim = next; + qh->reclaim = NULL; + + qh_completions(ehci, qh); + + if (!list_empty(&qh->qtd_list) + && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) + qh_link_async(ehci, qh); + else { + qh_put(qh); /* refcount from async list */ + + /* it's not free to turn the async schedule on/off; leave it + * active but idle for a while once it empties. + */ + if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state) + && ehci->async->qh_next.qh == NULL) + timer_action(ehci, TIMER_ASYNC_OFF); + } + + if (next) { + ehci->reclaim = NULL; + start_unlink_async(ehci, next); + } +} + +/* makes sure the async qh will become idle */ +/* caller must own ehci->lock */ + +static void start_unlink_async(struct ehci_hcd *ehci, struct ehci_qh *qh) +{ + int cmd = ehci_readl(ehci, &ehci->regs->command); + struct ehci_qh *prev; + +#ifdef DEBUG + assert_spin_locked(&ehci->lock); + if (ehci->reclaim + || (qh->qh_state != QH_STATE_LINKED + && qh->qh_state != QH_STATE_UNLINK_WAIT) + ) + BUG(); +#endif + + /* stop async schedule right now? */ + if (unlikely(qh == ehci->async)) { + /* can't get here without STS_ASS set */ + if (ehci_to_hcd(ehci)->state != HC_STATE_HALT && + !ehci->reclaim) { + /* ... and CMD_IAAD clear */ + ehci_writel(ehci, cmd & ~CMD_ASE, &ehci->regs->command); + wmb(); + /* handshake later, if we need to */ + timer_action_done(ehci, TIMER_ASYNC_OFF); + } + return; + } + + qh->qh_state = QH_STATE_UNLINK; + ehci->reclaim = qh = qh_get(qh); + + prev = ehci->async; + while (prev->qh_next.qh != qh) + prev = prev->qh_next.qh; + + prev->hw_next = qh->hw_next; + prev->qh_next = qh->qh_next; + wmb(); + + if (unlikely(ehci_to_hcd(ehci)->state == HC_STATE_HALT)) { + /* if (unlikely (qh->reclaim != 0)) + * this will recurse, probably not much + */ + end_unlink_async(ehci); + return; + } + + cmd |= CMD_IAAD; + ehci_writel(ehci, cmd, &ehci->regs->command); + (void)ehci_readl(ehci, &ehci->regs->command); + iaa_watchdog_start(ehci); +} + +/*-------------------------------------------------------------------------*/ + +static void scan_async(struct ehci_hcd *ehci) +{ + struct ehci_qh *qh; + enum ehci_timer_action action = TIMER_IO_WATCHDOG; + + if (!++(ehci->stamp)) + ehci->stamp++; + timer_action_done(ehci, TIMER_ASYNC_SHRINK); +rescan: + qh = ehci->async->qh_next.qh; + if (likely(qh != NULL)) { + do { + /* clean any finished work for this qh */ + if (!list_empty(&qh->qtd_list) + && qh->stamp != ehci->stamp) { + int temp; + + /* unlinks could happen here; completion + * reporting drops the lock. rescan using + * the latest schedule, but don't rescan + * qhs we already finished (no looping). + */ + qh = qh_get(qh); + qh->stamp = ehci->stamp; + temp = qh_completions(ehci, qh); + qh_put(qh); + if (temp != 0) + goto rescan; + } + + /* unlink idle entries, reducing HC PCI usage as well + * as HCD schedule-scanning costs. delay for any qh + * we just scanned, there's a not-unusual case that it + * doesn't stay idle for long. + * (plus, avoids some kind of re-activation race.) + */ + if (list_empty(&qh->qtd_list)) { + if (qh->stamp == ehci->stamp) + action = TIMER_ASYNC_SHRINK; + else if (!ehci->reclaim + && qh->qh_state == QH_STATE_LINKED) + start_unlink_async(ehci, qh); + } + + qh = qh->qh_next.qh; + } while (qh); + } + if (action == TIMER_ASYNC_SHRINK) + timer_action(ehci, TIMER_ASYNC_SHRINK); +} diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 8b3d9c8f33ef..57358229aed3 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -144,6 +144,18 @@ struct ehci_hcd { /* one per controller */ u8 sbrn; /* packed release number */ + /* + * OTG controllers and transceivers need software interaction; + * other external transceivers should be software-transparent + */ + struct otg_transceiver *transceiver; +#ifdef CONFIG_USB_STATIC_IRAM + u32 iram_buffer[2]; + u32 iram_buffer_v[2]; + int iram_in_use[2]; + int usb_address[2]; +#endif + /* irq statistics */ #ifdef EHCI_STATS struct ehci_stats stats; @@ -246,6 +258,10 @@ struct ehci_qtd { struct list_head qtd_list; /* sw qtd list */ struct urb *urb; /* qtd's urb */ size_t length; /* length of buffer */ +#ifdef CONFIG_USB_STATIC_IRAM + size_t buffer_offset; + int last_one; +#endif } __attribute__ ((aligned (32))); /* mask NakCnt+T in qh->hw_alt_next */ @@ -729,6 +745,10 @@ static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) #define STUB_DEBUG_FILES #endif /* DEBUG */ +#ifdef CONFIG_USB_STATIC_IRAM +#define IRAM_TD_SIZE 1024 /* size of 1 qTD's buffer */ +#define IRAM_NTD 2 /* number of TDs in IRAM */ +#endif /*-------------------------------------------------------------------------*/ #endif /* __LINUX_EHCI_HCD_H */ diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig index 3d2d3e549bd1..d061b1c7eaea 100644 --- a/drivers/usb/otg/Kconfig +++ b/drivers/usb/otg/Kconfig @@ -69,4 +69,12 @@ config NOP_USB_XCEIV built-in with usb ip or which are autonomous and doesn't require any phy programming such as ISP1x04 etc. +config MXC_OTG + tristate "USB OTG pin detect support" + select USB_OTG + select USB_OTG_UTILS + depends on USB_GADGET_ARC && USB_EHCI_HCD + help + Support for USB OTG PIN detect on MXC platforms. + endif # USB || OTG diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile index aeb49a8ec412..7b18165652dc 100644 --- a/drivers/usb/otg/Makefile +++ b/drivers/usb/otg/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_ISP1301_OMAP) += isp1301_omap.o obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o obj-$(CONFIG_NOP_USB_XCEIV) += nop-usb-xceiv.o obj-$(CONFIG_USB_ULPI) += ulpi.o +fsl_otg_arc-objs := fsl_otg.o otg_fsm.o +obj-$(CONFIG_MXC_OTG) += fsl_otg_arc.o ccflags-$(CONFIG_USB_DEBUG) += -DDEBUG ccflags-$(CONFIG_USB_GADGET_DEBUG) += -DDEBUG diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c new file mode 100644 index 000000000000..b52f57708fc1 --- /dev/null +++ b/drivers/usb/otg/fsl_otg.c @@ -0,0 +1,1376 @@ +/* + * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Author: Li Yang + * Jerry Huang + * + * Initialization based on code from Shlomi Gridish. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fsl_otg.h" + +#define CONFIG_USB_OTG_DEBUG_FILES +#define DRIVER_VERSION "$Revision: 1.55 $" +#define DRIVER_AUTHOR "Jerry Huang/Li Yang" +#define DRIVER_DESC "Freescale USB OTG Driver" +#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC + +#define TIMER_FREQ 1000 /* 1000 ms */ +#define IDLE_TIME 5000 /* 5000 ms */ + +MODULE_DESCRIPTION("Freescale USB OTG Driver"); + +static const char driver_name[] = "fsl-usb2-otg"; + +const pm_message_t otg_suspend_state = { + .event = 1, +}; + +#define HA_DATA_PULSE 1 + +volatile static struct usb_dr_mmap *usb_dr_regs; +static struct fsl_otg *fsl_otg_dev; +static int srp_wait_done; +static int gpio_id; +/* FSM timers */ +struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr, + *b_ase0_brst_tmr, *b_se0_srp_tmr; + +/* Driver specific timers */ +struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr, + *b_srp_wait_tmr, *a_wait_enum_tmr; + +static struct list_head active_timers; + +static struct fsl_otg_config fsl_otg_initdata = { + .otg_port = 1, +}; + +/* the timer is used to monitor the otg loading, if idle for some times + * we will close the otg clk + */ +static unsigned long last_busy; +static bool clk_stopped; +static struct timer_list monitor_timer; +static struct workqueue_struct *otg_queue; + +static void schedule_otg_work(struct delayed_work *dwork, unsigned long delay) +{ + queue_delayed_work(otg_queue, dwork, delay); +} + +int write_ulpi(u8 addr, u8 data) +{ + u32 temp; + temp = 0x60000000 | (addr << 16) | data; + temp = cpu_to_le32(temp); + usb_dr_regs->ulpiview = temp; + return 0; +} + +/* prototype declaration */ +void fsl_otg_add_timer(void *timer); +void fsl_otg_del_timer(void *timer); +static void fsl_otg_clk_gate(bool on); + +/* -------------------------------------------------------------*/ +/* Operations that will be called from OTG Finite State Machine */ + +/* Charge vbus for vbus pulsing in SRP */ +void fsl_otg_chrg_vbus(int on) +{ + if (on) + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK & + ~OTGSC_CTRL_VBUS_DISCHARGE) | + OTGSC_CTRL_VBUS_CHARGE); + else + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK & ~OTGSC_CTRL_VBUS_CHARGE)); +} + +/* Discharge vbus through a resistor to ground */ +void fsl_otg_dischrg_vbus(int on) +{ + if (on) + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK) + | OTGSC_CTRL_VBUS_DISCHARGE); + else + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK & + ~OTGSC_CTRL_VBUS_DISCHARGE)); +} + +/* Wait for VBUS discharge after set VBUS lower */ +static void fsl_otg_wait_dischrg_vbus(void) +{ + fsl_otg_clk_gate(true); + fsl_otg_dischrg_vbus(1); + msleep(5); + fsl_otg_dischrg_vbus(0); + fsl_otg_clk_gate(false); +} + +/* A-device driver vbus, controlled through PP bit in PORTSC */ +void fsl_otg_drv_vbus(struct fsl_usb2_platform_data *pdata, int on) +{ + if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power) + pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on); +} + +/* + * Pull-up D+, signalling connect by periperal. Also used in + * data-line pulsing in SRP + */ +void fsl_otg_loc_conn(int on) +{ + if (on) + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK) | OTGSC_CTRL_DATA_PULSING); + else + usb_dr_regs->otgsc = + cpu_to_le32(le32_to_cpu(usb_dr_regs->otgsc) & + ~OTGSC_INTSTS_MASK & ~OTGSC_CTRL_DATA_PULSING); +} + +/* Generate SOF by host. This is controlled through suspend/resume the + * port. In host mode, controller will automatically send SOF. + * Suspend will block the data on the port. + */ +void fsl_otg_loc_sof(int on) +{ + u32 tmpval; + + tmpval = readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS; + if (on) + tmpval |= PORTSC_PORT_FORCE_RESUME; + else + tmpval |= PORTSC_PORT_SUSPEND; + writel(tmpval, &fsl_otg_dev->dr_mem_map->portsc); + +} + +/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */ +void fsl_otg_start_pulse(void) +{ + srp_wait_done = 0; +#ifdef HA_DATA_PULSE + usb_dr_regs->otgsc = + cpu_to_le32((le32_to_cpu(usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK) + | OTGSC_HA_DATA_PULSE); +#else + fsl_otg_loc_conn(1); +#endif + + fsl_otg_add_timer(b_data_pulse_tmr); +} + +void fsl_otg_pulse_vbus(void); + +void b_data_pulse_end(unsigned long foo) +{ +#ifdef HA_DATA_PULSE +#else + fsl_otg_loc_conn(0); +#endif + + /* Do VBUS pulse after data pulse */ + fsl_otg_pulse_vbus(); +} + +void fsl_otg_pulse_vbus(void) +{ + srp_wait_done = 0; + fsl_otg_chrg_vbus(1); + /* start the timer to end vbus charge */ + fsl_otg_add_timer(b_vbus_pulse_tmr); +} + +void b_vbus_pulse_end(unsigned long foo) +{ + fsl_otg_chrg_vbus(0); + + /* As USB3300 using the same a_sess_vld and b_sess_vld voltage + * we need to discharge the bus for a while to distinguish + * residual voltage of vbus pulsing and A device pull up */ + fsl_otg_dischrg_vbus(1); + fsl_otg_add_timer(b_srp_wait_tmr); +} + +void b_srp_end(unsigned long foo) +{ + fsl_otg_dischrg_vbus(0); + srp_wait_done = 1; + + if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) && + fsl_otg_dev->fsm.b_sess_vld) + fsl_otg_dev->fsm.b_srp_done = 1; +} + +/* Workaround for a_host suspending too fast. When a_bus_req=0, + * a_host will start by SRP. It needs to set b_hnp_enable before + * actually suspending to start HNP + */ +void a_wait_enum(unsigned long foo) +{ + VDBG("a_wait_enum timeout\n"); + if (!fsl_otg_dev->otg.host->b_hnp_enable) + fsl_otg_add_timer(a_wait_enum_tmr); + else + otg_statemachine(&fsl_otg_dev->fsm); +} + +/* ------------------------------------------------------*/ + +/* The timeout callback function to set time out bit */ +void set_tmout(unsigned long indicator) +{ + *(int *)indicator = 1; +} + +/* Initialize timers */ +int fsl_otg_init_timers(struct otg_fsm *fsm) +{ + /* FSM used timers */ + a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE, + (unsigned long)&fsm->a_wait_vrise_tmout); + if (a_wait_vrise_tmr == NULL) + return -ENOMEM; + + a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON, + (unsigned long)&fsm->a_wait_bcon_tmout); + if (a_wait_bcon_tmr == NULL) + return -ENOMEM; + + a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS, + (unsigned long)&fsm->a_aidl_bdis_tmout); + if (a_aidl_bdis_tmr == NULL) + return -ENOMEM; + + b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST, + (unsigned long)&fsm->b_ase0_brst_tmout); + if (b_ase0_brst_tmr == NULL) + return -ENOMEM; + + b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP, + (unsigned long)&fsm->b_se0_srp); + if (b_se0_srp_tmr == NULL) + return -ENOMEM; + + b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL, + (unsigned long)&fsm->b_srp_done); + if (b_srp_fail_tmr == NULL) + return -ENOMEM; + + a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10, + (unsigned long)&fsm); + if (a_wait_enum_tmr == NULL) + return -ENOMEM; + + /* device driver used timers */ + b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0); + if (b_srp_wait_tmr == NULL) + return -ENOMEM; + + b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end, + TB_DATA_PLS, 0); + if (b_data_pulse_tmr == NULL) + return -ENOMEM; + + b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end, + TB_VBUS_PLS, 0); + if (b_vbus_pulse_tmr == NULL) + return -ENOMEM; + + return 0; +} + +/* Uninitialize timers */ +void fsl_otg_uninit_timers(void) +{ + /* FSM used timers */ + if (a_wait_vrise_tmr != NULL) + kfree(a_wait_vrise_tmr); + if (a_wait_bcon_tmr != NULL) + kfree(a_wait_bcon_tmr); + if (a_aidl_bdis_tmr != NULL) + kfree(a_aidl_bdis_tmr); + if (b_ase0_brst_tmr != NULL) + kfree(b_ase0_brst_tmr); + if (b_se0_srp_tmr != NULL) + kfree(b_se0_srp_tmr); + if (b_srp_fail_tmr != NULL) + kfree(b_srp_fail_tmr); + if (a_wait_enum_tmr != NULL) + kfree(a_wait_enum_tmr); + + /* device driver used timers */ + if (b_srp_wait_tmr != NULL) + kfree(b_srp_wait_tmr); + if (b_data_pulse_tmr != NULL) + kfree(b_data_pulse_tmr); + if (b_vbus_pulse_tmr != NULL) + kfree(b_vbus_pulse_tmr); +} + +/* Add timer to timer list */ +void fsl_otg_add_timer(void *gtimer) +{ + struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer; + struct fsl_otg_timer *tmp_timer; + + /* Check if the timer is already in the active list, + * if so update timer count + */ + list_for_each_entry(tmp_timer, &active_timers, list) + if (tmp_timer == timer) { + timer->count = timer->expires; + return; + } + timer->count = timer->expires; + list_add_tail(&timer->list, &active_timers); +} + +/* Remove timer from the timer list; clear timeout status */ +void fsl_otg_del_timer(void *gtimer) +{ + struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer; + struct fsl_otg_timer *tmp_timer, *del_tmp; + + list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) + if (tmp_timer == timer) + list_del(&timer->list); +} + +/* Reduce timer count by 1, and find timeout conditions. + * Called by fsl_otg 1ms timer interrupt + */ +int fsl_otg_tick_timer(void) +{ + struct fsl_otg_timer *tmp_timer, *del_tmp; + int expired = 0; + + list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) { + tmp_timer->count--; + /* check if timer expires */ + if (!tmp_timer->count) { + list_del(&tmp_timer->list); + tmp_timer->function(tmp_timer->data); + expired = 1; + } + } + + return expired; +} + +static void fsl_otg_clk_gate(bool on) +{ + struct device *dev = fsl_otg_dev->otg.dev; + struct fsl_usb2_platform_data *pdata; + + if (dev) { + pdata = dev->platform_data; + if (pdata && pdata->usb_clock_for_pm) + pdata->usb_clock_for_pm(on); + } +} + +static void fsl_otg_clk_ctl(void) +{ + if (clk_stopped) { + fsl_otg_clk_gate(true); + clk_stopped = false; + } + last_busy = jiffies; +} + +static void fsl_otg_loading_monitor(unsigned long data) +{ + unsigned long now = jiffies; + if (!clk_stopped) { + if (time_after(now, last_busy + msecs_to_jiffies(IDLE_TIME))) { + clk_stopped = true; + fsl_otg_clk_gate(false); + } + } + mod_timer(&monitor_timer, jiffies + msecs_to_jiffies(TIMER_FREQ)); +} + +/** + * Enable vbus interrupt + * The otg cares USB_ID interrupt + * The device cares B Session Valid + */ +static void b_session_irq_enable(bool enable) +{ + u32 osc; + fsl_otg_clk_gate(true); + if (le32_to_cpu(usb_dr_regs->portsc) & PORTSC_PHY_LOW_POWER_SPD) { + pr_debug("%s: the usb is in low power mode, vbus should not changed \n", __func__); + fsl_otg_clk_gate(false); + return; + } + + osc = le32_to_cpu(usb_dr_regs->otgsc); + pr_debug("%s:otgsc=0x%x", __func__, osc); + /* The other interrupts' status should not be cleared */ + osc &= ~(OTGSC_INTSTS_USB_ID | OTGSC_INTSTS_A_VBUS_VALID + | OTGSC_INTSTS_A_SESSION_VALID | OTGSC_INTSTS_B_SESSION_VALID); + osc |= OTGSC_INTSTS_B_SESSION_VALID; + if (enable) + osc |= OTGSC_INTR_B_SESSION_VALID_EN; + else + osc &= ~OTGSC_INTR_B_SESSION_VALID_EN; + usb_dr_regs->otgsc = cpu_to_le32(osc); + fsl_otg_clk_gate(false); +} + +/* Reset controller, not reset the bus */ +void otg_reset_controller(void) +{ + u32 command; + + command = readl(&usb_dr_regs->usbcmd); + command |= (1 << 1); + writel(command, &usb_dr_regs->usbcmd); + while (readl(&usb_dr_regs->usbcmd) & (1 << 1)) + ; +} + +/* Call suspend/resume routines in host driver */ +int fsl_otg_start_host(struct otg_fsm *fsm, int on) +{ + struct otg_transceiver *xceiv = fsm->transceiver; + struct device *dev; + struct fsl_otg *otg_dev = container_of(xceiv, struct fsl_otg, otg); + struct platform_driver *host_pdrv; + struct platform_device *host_pdev; + u32 retval = 0; + + if (!xceiv->host) + return -ENODEV; + dev = xceiv->host->controller; + host_pdrv = container_of((dev->driver), struct platform_driver, driver); + host_pdev = to_platform_device(dev); + + /* Update a_vbus_vld state as a_vbus_vld int is disabled + * in device mode + */ + fsl_otg_clk_gate(true); + fsm->a_vbus_vld = + (le32_to_cpu(usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID) ? 1 : 0; + fsl_otg_clk_gate(false); + + if (on) { + /* start fsl usb host controller */ + if (otg_dev->host_working) + goto end; + else { + otg_reset_controller(); + VDBG("host on......\n"); + if (host_pdrv->resume) { + retval = host_pdrv->resume(host_pdev); + if (fsm->id) { + /* default-b */ + fsl_otg_drv_vbus(dev->platform_data, 1); + /* Workaround: b_host can't driver + * vbus, but PP in PORTSC needs to + * be 1 for host to work. + * So we set drv_vbus bit in + * transceiver to 0 thru ULPI. */ +#if defined(CONFIG_ISP1504_MXC) + write_ulpi(0x0c, 0x20); +#endif + } + } + + otg_dev->host_working = 1; + } + } else { + /* stop fsl usb host controller */ + if (!otg_dev->host_working) + goto end; + else { + VDBG("host off......\n"); + if (host_pdrv->suspend) { + retval = host_pdrv->suspend(host_pdev, + otg_suspend_state); + if (fsm->id) + /* default-b */ + fsl_otg_drv_vbus(dev->platform_data, 0); + } + otg_dev->host_working = 0; + } + } +end: + return retval; +} + +/* Call suspend and resume function in udc driver + * to stop and start udc driver. + */ +int fsl_otg_start_gadget(struct otg_fsm *fsm, int on) +{ + struct otg_transceiver *xceiv = fsm->transceiver; + struct device *dev; + struct platform_driver *gadget_pdrv; + struct platform_device *gadget_pdev; + if (!xceiv->gadget || !xceiv->gadget->dev.parent) + return -ENODEV; + + VDBG("gadget %s \n", on ? "on" : "off"); + dev = xceiv->gadget->dev.parent; + + gadget_pdrv = container_of((dev->driver), + struct platform_driver, driver); + gadget_pdev = to_platform_device(dev); + + if (on) + gadget_pdrv->resume(gadget_pdev); + else + gadget_pdrv->suspend(gadget_pdev, otg_suspend_state); + + return 0; +} + +/* Called by initialization code of host driver. Register host controller + * to the OTG. Suspend host for OTG role detection. + */ +static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host) +{ + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + + if (!otg_p || otg_dev != fsl_otg_dev) + return -ENODEV; + + otg_p->host = host; + + otg_dev->fsm.a_bus_drop = 0; + otg_dev->fsm.a_bus_req = 1; + + if (host) { + VDBG("host off......\n"); + otg_p->host->otg_port = fsl_otg_initdata.otg_port; + otg_p->host->is_b_host = otg_dev->fsm.id; + /* must leave time for khubd to finish its thing + * before yanking the host driver out from under it, + * so suspend the host after a short delay. + */ + otg_dev->host_working = 1; + schedule_otg_work(&otg_dev->otg_event, 100); + return 0; + } else { /* host driver going away */ + + if (!(le32_to_cpu(otg_dev->dr_mem_map->otgsc) & + OTGSC_STS_USB_ID)) { + /* Mini-A cable connected */ + struct otg_fsm *fsm = &otg_dev->fsm; + + otg_p->state = OTG_STATE_UNDEFINED; + fsm->protocol = PROTO_UNDEF; + } + if (gpio_id) { + if (gpio_get_value(gpio_id)) { + struct otg_fsm *fsm = &otg_dev->fsm; + otg_p->state = OTG_STATE_UNDEFINED; + fsm->protocol = PROTO_UNDEF; + } + } + } + + otg_dev->host_working = 0; + + otg_statemachine(&otg_dev->fsm); + + return 0; +} + +/* Called by initialization code of udc. Register udc to OTG.*/ +static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p, + struct usb_gadget *gadget) +{ + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + + VDBG("otg_dev 0x%x\n", (int)otg_dev); + VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev); + + if (!otg_p || otg_dev != fsl_otg_dev) + return -ENODEV; + + if (!gadget) { + if (!otg_dev->otg.default_a) + otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0); + usb_gadget_vbus_disconnect(otg_dev->otg.gadget); + otg_dev->otg.gadget = 0; + otg_dev->fsm.b_bus_req = 0; + otg_statemachine(&otg_dev->fsm); + return 0; + } + + otg_p->gadget = gadget; + otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id; + + otg_dev->fsm.b_bus_req = 1; + + /* start the gadget right away if the ID pin says Mini-B */ + DBG("ID pin=%d\n", otg_dev->fsm.id); + if (otg_dev->fsm.id == 1) { + fsl_otg_start_host(&otg_dev->fsm, 0); + otg_drv_vbus(&otg_dev->fsm, 0); + fsl_otg_wait_dischrg_vbus(); + fsl_otg_start_gadget(&otg_dev->fsm, 1); + } + + return 0; +} + +/* Set OTG port power, only for B-device */ +static int fsl_otg_set_power(struct otg_transceiver *otg_p, unsigned mA) +{ + if (!fsl_otg_dev) + return -ENODEV; + if (otg_p->state == OTG_STATE_B_PERIPHERAL) + printk(KERN_INFO "FSL OTG:Draw %d mA\n", mA); + + return 0; +} + +/* Delayed pin detect interrupt processing. + * + * When the Mini-A cable is disconnected from the board, + * the pin-detect interrupt happens before the disconnnect + * interrupts for the connected device(s). In order to + * process the disconnect interrupt(s) prior to switching + * roles, the pin-detect interrupts are delayed, and handled + * by this routine. + */ +static void fsl_otg_event(struct work_struct *work) +{ + struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work); + struct otg_fsm *fsm = &og->fsm; + struct otg_transceiver *otg = &og->otg; + + mutex_lock(&pm_mutex); + b_session_irq_enable(false); + otg->default_a = (fsm->id == 0); + /* clear conn information */ + if (fsm->id) + fsm->b_conn = 0; + else + fsm->a_conn = 0; + + if (fsm->id) { /* switch to gadget */ + fsl_otg_start_host(fsm, 0); + otg_drv_vbus(fsm, 0); + fsl_otg_wait_dischrg_vbus(); + b_session_irq_enable(false); + fsl_otg_start_gadget(fsm, 1); + } else { /* switch to host */ + fsl_otg_start_gadget(fsm, 0); + otg_drv_vbus(fsm, 1); + b_session_irq_enable(false); + fsl_otg_start_host(fsm, 1); + } + mutex_unlock(&pm_mutex); +} + +/* B-device start SRP */ +static int fsl_otg_start_srp(struct otg_transceiver *otg_p) +{ + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + + if (!otg_p || otg_dev != fsl_otg_dev + || otg_p->state != OTG_STATE_B_IDLE) + return -ENODEV; + + otg_dev->fsm.b_bus_req = 1; + otg_statemachine(&otg_dev->fsm); + + return 0; +} + +/* A_host suspend will call this function to start hnp */ +static int fsl_otg_start_hnp(struct otg_transceiver *otg_p) +{ + struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg); + + if (!otg_p || otg_dev != fsl_otg_dev) + return -ENODEV; + + /* printk("start_hnp.............\n"); */ + /* clear a_bus_req to enter a_suspend state */ + otg_dev->fsm.a_bus_req = 0; + otg_statemachine(&otg_dev->fsm); + + return 0; +} +/* Interrupt handler for gpio id pin */ +irqreturn_t fsl_otg_isr_gpio(int irq, void *dev_id) +{ + struct otg_fsm *fsm; + struct fsl_usb2_platform_data *pdata = + (struct fsl_usb2_platform_data *)dev_id; + struct fsl_otg *f_otg; + struct otg_transceiver *otg_trans = otg_get_transceiver(); + int value; + f_otg = container_of(otg_trans, struct fsl_otg, otg); + fsm = &f_otg->fsm; + + if (pdata->id_gpio == 0) + return IRQ_NONE; + + value = gpio_get_value(pdata->id_gpio) ? 1 : 0; + + if (value) + set_irq_type(gpio_to_irq(pdata->id_gpio), IRQ_TYPE_LEVEL_LOW); + else + set_irq_type(gpio_to_irq(pdata->id_gpio), IRQ_TYPE_LEVEL_HIGH); + + + if (value == f_otg->fsm.id) + return IRQ_HANDLED; + + f_otg->fsm.id = value; + + cancel_delayed_work(&f_otg->otg_event); + schedule_otg_work(&f_otg->otg_event, msecs_to_jiffies(10)); + + return IRQ_HANDLED; +} + +/* Interrupt handler. OTG/host/peripheral share the same int line. + * OTG driver clears OTGSC interrupts and leaves USB interrupts + * intact. It needs to have knowledge of some USB interrupts + * such as port change. + */ +irqreturn_t fsl_otg_isr(int irq, void *dev_id) +{ + struct fsl_otg *fotg = (struct fsl_otg *)dev_id; + struct otg_transceiver *otg = &fotg->otg; + u32 otg_int_src, otg_sc; + irqreturn_t ret = IRQ_NONE; + struct fsl_usb2_platform_data *pdata; + if (fotg && fotg->otg.dev) { + pdata = fotg->otg.dev->platform_data; + if (pdata->irq_delay) + return ret; + } + otg_sc = le32_to_cpu(usb_dr_regs->otgsc); + otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8); + + /* Only clear otg interrupts, expect B_SESSION_VALID, + * Leave it to be handled by arcotg_udc */ + usb_dr_regs->otgsc = ((usb_dr_regs->otgsc | cpu_to_le32(otg_sc & OTGSC_INTSTS_MASK))& + (~OTGSC_INTSTS_B_SESSION_VALID)); + + /*FIXME: ID change not generate when init to 0 */ + fotg->fsm.id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0; + otg->default_a = (fotg->fsm.id == 0); + + /* is_b_host, is_a_peripheral may be used at host/gadget driver + * so, assign them at irq, the otg event is scheduled too late + */ + if (otg->host) + otg->host->is_b_host = fotg->fsm.id; + if (otg->gadget) + otg->gadget->is_a_peripheral = !(fotg->fsm.id); + + /* process OTG interrupts */ + if (otg_int_src) { + if (otg_int_src & OTGSC_INTSTS_USB_ID) { + fotg->fsm.id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0; + + printk(KERN_DEBUG "ID int (ID is %d)\n", fotg->fsm.id); + + cancel_delayed_work(&fotg->otg_event); + schedule_otg_work(&fotg->otg_event, msecs_to_jiffies(10)); + ret = IRQ_HANDLED; + } + } + + return ret; +} + +static void fsl_otg_fsm_drv_vbus(int on) +{ + struct otg_fsm *fsm = &(fsl_otg_dev->fsm); + struct otg_transceiver *xceiv = fsm->transceiver; + struct device *dev; + /* + * The host is assigned at otg_set_host + */ + if (!xceiv->host) + return; + /* + * The dev is assigned at usb_create_hcd which is called earlier + * than otg_set_host at host driver's probe + */ + dev = xceiv->host->controller; + fsl_otg_drv_vbus(dev->platform_data, on); +} + +static struct otg_fsm_ops fsl_otg_ops = { + .chrg_vbus = fsl_otg_chrg_vbus, + .drv_vbus = fsl_otg_fsm_drv_vbus, + .loc_conn = fsl_otg_loc_conn, + .loc_sof = fsl_otg_loc_sof, + .start_pulse = fsl_otg_start_pulse, + + .add_timer = fsl_otg_add_timer, + .del_timer = fsl_otg_del_timer, + + .start_host = fsl_otg_start_host, + .start_gadget = fsl_otg_start_gadget, +}; + +/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */ +static int fsl_otg_conf(struct platform_device *pdev) +{ + int status; + struct fsl_otg *fsl_otg_tc; + struct fsl_usb2_platform_data *pdata; + + pdata = pdev->dev.platform_data; + + DBG(); + + if (fsl_otg_dev) + return 0; + + /* allocate space to fsl otg device */ + fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL); + if (!fsl_otg_tc) + return -ENODEV; + otg_queue = create_workqueue("otg_switch"); + if (otg_queue == NULL) { + printk(KERN_ERR "Coulndn't create work queue\n"); + return -ENOMEM; + } + INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event); + + INIT_LIST_HEAD(&active_timers); + status = fsl_otg_init_timers(&fsl_otg_tc->fsm); + if (status) { + printk(KERN_INFO "Couldn't init OTG timers\n"); + fsl_otg_uninit_timers(); + kfree(fsl_otg_tc); + return status; + } + spin_lock_init(&fsl_otg_tc->fsm.lock); + + /* Set OTG state machine operations */ + fsl_otg_tc->fsm.ops = &fsl_otg_ops; + + /* initialize the otg structure */ + fsl_otg_tc->otg.label = DRIVER_DESC; + fsl_otg_tc->otg.set_host = fsl_otg_set_host; + fsl_otg_tc->otg.set_peripheral = fsl_otg_set_peripheral; + fsl_otg_tc->otg.set_power = fsl_otg_set_power; + fsl_otg_tc->otg.start_hnp = fsl_otg_start_hnp; + fsl_otg_tc->otg.start_srp = fsl_otg_start_srp; + fsl_otg_tc->otg.dev = &pdev->dev; + + fsl_otg_dev = fsl_otg_tc; + + /* Store the otg transceiver */ + status = otg_set_transceiver(&fsl_otg_tc->otg); + if (status) { + printk(KERN_WARNING ": unable to register OTG transceiver.\n"); + return status; + } + + return 0; +} + +/* OTG Initialization*/ +int usb_otg_start(struct platform_device *pdev) +{ + struct fsl_otg *p_otg; + struct otg_transceiver *otg_trans = otg_get_transceiver(); + struct otg_fsm *fsm; + volatile unsigned long *p; + int status; + struct resource *res; + u32 temp; + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + + p_otg = container_of(otg_trans, struct fsl_otg, otg); + fsm = &p_otg->fsm; + + /* Initialize the state machine structure with default values */ + SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED); + fsm->transceiver = &p_otg->otg; + + /* We don't require predefined MEM/IRQ resource index */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENXIO; + + /* We don't request_mem_region here to enable resource sharing + * with host/device */ + + usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap)); + p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs; + pdata->regs = (void *)usb_dr_regs; + + if (pdata->platform_init && pdata->platform_init(pdev) != 0) + return -EINVAL; + + gpio_id = pdata->id_gpio; + /* request irq */ + if (pdata->id_gpio == 0) { + p_otg->irq = platform_get_irq(pdev, 0); + status = request_irq(p_otg->irq, fsl_otg_isr, + IRQF_SHARED, driver_name, p_otg); + } else { + status = request_irq(gpio_to_irq(pdata->id_gpio), + fsl_otg_isr_gpio, + IRQF_SHARED, driver_name, pdata); + } + if (status) { + dev_dbg(p_otg->otg.dev, "can't get IRQ %d, error %d\n", + p_otg->irq, status); + iounmap(p_otg->dr_mem_map); + kfree(p_otg); + return status; + } + + clk_stopped = false; /* platform_init will open the otg clk */ + + /* stop the controller */ + temp = readl(&p_otg->dr_mem_map->usbcmd); + temp &= ~USB_CMD_RUN_STOP; + writel(temp, &p_otg->dr_mem_map->usbcmd); + + /* reset the controller */ + temp = readl(&p_otg->dr_mem_map->usbcmd); + temp |= USB_CMD_CTRL_RESET; + writel(temp, &p_otg->dr_mem_map->usbcmd); + + /* wait reset completed */ + while (readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET) + ; + + /* configure the VBUSHS as IDLE(both host and device) */ + temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0); + writel(temp, &p_otg->dr_mem_map->usbmode); + + /* configure PHY interface */ + temp = readl(&p_otg->dr_mem_map->portsc); + temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW); + switch (pdata->phy_mode) { + case FSL_USB2_PHY_ULPI: + temp |= PORTSC_PTS_ULPI; + break; + case FSL_USB2_PHY_UTMI_WIDE: + temp |= PORTSC_PTW_16BIT; + /* fall through */ + case FSL_USB2_PHY_UTMI: + temp |= PORTSC_PTS_UTMI; + /* fall through */ + default: + break; + } + writel(temp, &p_otg->dr_mem_map->portsc); + + if (pdata->have_sysif_regs) { + /* configure control enable IO output, big endian register */ + p = (volatile unsigned long *)(&p_otg->dr_mem_map->control); + temp = *p; + temp |= USB_CTRL_IOENB; + *p = temp; + } + + /* disable all interrupt and clear all OTGSC status */ + temp = readl(&p_otg->dr_mem_map->otgsc); + temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK; + temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE; + writel(temp, &p_otg->dr_mem_map->otgsc); + + + /* + * The identification (id) input is FALSE when a Mini-A plug is inserted + * in the devices Mini-AB receptacle. Otherwise, this input is TRUE. + * Also: record initial state of ID pin + */ + if (le32_to_cpu(p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) { + p_otg->fsm.id = 1; + } else { + p_otg->fsm.id = 0; + } + + if (pdata->id_gpio != 0) { + p_otg->fsm.id = gpio_get_value(pdata->id_gpio) ? 1 : 0; + if (p_otg->fsm.id) + set_irq_type(gpio_to_irq(pdata->id_gpio), + IRQ_TYPE_LEVEL_LOW); + else + set_irq_type(gpio_to_irq(pdata->id_gpio), + IRQ_TYPE_LEVEL_HIGH); + } + p_otg->otg.state = p_otg->fsm.id ? OTG_STATE_UNDEFINED : + OTG_STATE_A_IDLE; + + DBG("initial ID pin=%d\n", p_otg->fsm.id); + + /* enable OTG ID pin interrupt */ + temp = readl(&p_otg->dr_mem_map->otgsc); + if (!pdata->id_gpio) + temp |= OTGSC_INTR_USB_ID_EN; + temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN); + + writel(temp, &p_otg->dr_mem_map->otgsc); + + return 0; +} + +/*------------------------------------------------------------------------- + PROC File System Support +-------------------------------------------------------------------------*/ +#ifdef CONFIG_USB_OTG_DEBUG_FILES + +#include + +static const char proc_filename[] = "driver/isp1504_otg"; + +static int otg_proc_read(char *page, char **start, off_t off, int count, + int *eof, void *_dev) +{ + struct otg_fsm *fsm = &fsl_otg_dev->fsm; + char *buf = page; + char *next = buf; + unsigned size = count; + unsigned long flags; + int t; + u32 tmp_reg; + + if (off != 0) + return 0; + + fsl_otg_clk_gate(true); + spin_lock_irqsave(&fsm->lock, flags); + + /* ------basic driver infomation ---- */ + t = scnprintf(next, size, + DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n", + DRIVER_VERSION); + size -= t; + next += t; + + /* ------ Registers ----- */ + tmp_reg = le32_to_cpu(usb_dr_regs->otgsc); + t = scnprintf(next, size, "OTGSC reg: %08x\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = le32_to_cpu(usb_dr_regs->portsc); + t = scnprintf(next, size, "PORTSC reg: %08x\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = le32_to_cpu(usb_dr_regs->usbmode); + t = scnprintf(next, size, "USBMODE reg: %08x\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = le32_to_cpu(usb_dr_regs->usbcmd); + t = scnprintf(next, size, "USBCMD reg: %08x\n", tmp_reg); + size -= t; + next += t; + + tmp_reg = le32_to_cpu(usb_dr_regs->usbsts); + t = scnprintf(next, size, "USBSTS reg: %08x\n", tmp_reg); + size -= t; + next += t; + + /* ------ State ----- */ + t = scnprintf(next, size, + "OTG state: %s\n\n", + state_string(fsl_otg_dev->otg.state)); + size -= t; + next += t; + +#if 1 || defined DEBUG + /* ------ State Machine Variables ----- */ + t = scnprintf(next, size, "a_bus_req: %d\n", fsm->a_bus_req); + size -= t; + next += t; + + t = scnprintf(next, size, "b_bus_req: %d\n", fsm->b_bus_req); + size -= t; + next += t; + + t = scnprintf(next, size, "a_bus_resume: %d\n", fsm->a_bus_resume); + size -= t; + next += t; + + t = scnprintf(next, size, "a_bus_suspend: %d\n", fsm->a_bus_suspend); + size -= t; + next += t; + + t = scnprintf(next, size, "a_conn: %d\n", fsm->a_conn); + size -= t; + next += t; + + t = scnprintf(next, size, "a_sess_vld: %d\n", fsm->a_sess_vld); + size -= t; + next += t; + + t = scnprintf(next, size, "a_srp_det: %d\n", fsm->a_srp_det); + size -= t; + next += t; + + t = scnprintf(next, size, "a_vbus_vld: %d\n", fsm->a_vbus_vld); + size -= t; + next += t; + + t = scnprintf(next, size, "b_bus_resume: %d\n", fsm->b_bus_resume); + size -= t; + next += t; + + t = scnprintf(next, size, "b_bus_suspend: %d\n", fsm->b_bus_suspend); + size -= t; + next += t; + + t = scnprintf(next, size, "b_conn: %d\n", fsm->b_conn); + size -= t; + next += t; + + t = scnprintf(next, size, "b_se0_srp: %d\n", fsm->b_se0_srp); + size -= t; + next += t; + + t = scnprintf(next, size, "b_sess_end: %d\n", fsm->b_sess_end); + size -= t; + next += t; + + t = scnprintf(next, size, "b_sess_vld: %d\n", fsm->b_sess_vld); + size -= t; + next += t; + + t = scnprintf(next, size, "id: %d\n", fsm->id); + size -= t; + next += t; +#endif + spin_unlock_irqrestore(&fsm->lock, flags); + fsl_otg_clk_gate(false); + + *eof = 1; + return count - size; +} + +#define create_proc_file() create_proc_read_entry(proc_filename, \ + 0, NULL, otg_proc_read, NULL) + +#define remove_proc_file() remove_proc_entry(proc_filename, NULL) + +#else /* !CONFIG_USB_OTG_DEBUG_FILES */ + +#define create_proc_file() do {} while (0) +#define remove_proc_file() do {} while (0) + +#endif /*CONFIG_USB_OTG_DEBUG_FILES */ + +/*----------------------------------------------------------*/ +/* Char driver interface to control some OTG input */ + +/* This function handle some ioctl command,such as get otg + * status and set host suspend + */ +static int fsl_otg_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + u32 retval = 0; + + switch (cmd) { + case GET_OTG_STATUS: + retval = fsl_otg_dev->host_working; + break; + + case SET_A_SUSPEND_REQ: + fsl_otg_dev->fsm.a_suspend_req = arg; + break; + + case SET_A_BUS_DROP: + fsl_otg_dev->fsm.a_bus_drop = arg; + break; + + case SET_A_BUS_REQ: + fsl_otg_dev->fsm.a_bus_req = arg; + break; + + case SET_B_BUS_REQ: + fsl_otg_dev->fsm.b_bus_req = arg; + break; + + default: + break; + } + + otg_statemachine(&fsl_otg_dev->fsm); + + return retval; +} + +static int fsl_otg_open(struct inode *inode, struct file *file) +{ + + return 0; +} + +static int fsl_otg_release(struct inode *inode, struct file *file) +{ + + return 0; +} + +static struct file_operations otg_fops = { + .owner = THIS_MODULE, + .llseek = NULL, + .read = NULL, + .write = NULL, + .ioctl = fsl_otg_ioctl, + .open = fsl_otg_open, + .release = fsl_otg_release, +}; + +static int __init fsl_otg_probe(struct platform_device *pdev) +{ + int status; + struct fsl_usb2_platform_data *pdata; + + DBG("pdev=0x%p\n", pdev); + + if (!pdev) + return -ENODEV; + + if (!pdev->dev.platform_data) + return -ENOMEM; + + pdata = pdev->dev.platform_data; + + /* configure the OTG */ + status = fsl_otg_conf(pdev); + if (status) { + printk(KERN_INFO "Couldn't init OTG module\n"); + return -status; + } + + /* start OTG */ + status = usb_otg_start(pdev); + + if (register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops)) { + printk(KERN_WARNING FSL_OTG_NAME + ": unable to register FSL OTG device\n"); + return -EIO; + } + + last_busy = jiffies; + create_proc_file(); + fsl_otg_clk_gate(false); + return status; +} + +static int fsl_otg_remove(struct platform_device *pdev) +{ + struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data; + + otg_set_transceiver(NULL); + free_irq(fsl_otg_dev->irq, fsl_otg_dev); + + iounmap((void *)usb_dr_regs); + + kfree(fsl_otg_dev); + + remove_proc_file(); + + unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME); + + if (pdata->platform_uninit) + pdata->platform_uninit(pdata); + + return 0; +} + +struct platform_driver fsl_otg_driver = { + .probe = fsl_otg_probe, + .remove = fsl_otg_remove, + .driver = { + .name = driver_name, + .owner = THIS_MODULE, + }, +}; + +/*-------------------------------------------------------------------------*/ + +static int __init fsl_usb_otg_init(void) +{ + printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION); + return platform_driver_register(&fsl_otg_driver); +} + +static void __exit fsl_usb_otg_exit(void) +{ + platform_driver_unregister(&fsl_otg_driver); + printk(KERN_INFO DRIVER_DESC " unloaded\n"); +} + +subsys_initcall(fsl_usb_otg_init); +module_exit(fsl_usb_otg_exit); + +MODULE_DESCRIPTION(DRIVER_INFO); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_LICENSE("GPL"); diff --git a/drivers/usb/otg/fsl_otg.h b/drivers/usb/otg/fsl_otg.h new file mode 100644 index 000000000000..0857a53e6fad --- /dev/null +++ b/drivers/usb/otg/fsl_otg.h @@ -0,0 +1,412 @@ +/* Copyright (C) 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "otg_fsm.h" +#include +#include + + /* USB Command Register Bit Masks */ +#define USB_CMD_RUN_STOP (0x1<<0) +#define USB_CMD_CTRL_RESET (0x1<<1) +#define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4) +#define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5) +#define USB_CMD_INT_AA_DOORBELL (0x1<<6) +#define USB_CMD_ASP (0x3<<8) +#define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11) +#define USB_CMD_SUTW (0x1<<13) +#define USB_CMD_ATDTW (0x1<<14) +#define USB_CMD_ITC (0xFF<<16) + +/* bit 15,3,2 are frame list size */ +#define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2) +#define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2) +#define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2) +#define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2) +#define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2) +#define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2) +#define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2) +#define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2) + +/* bit 9-8 are async schedule park mode count */ +#define USB_CMD_ASP_00 (0x0<<8) +#define USB_CMD_ASP_01 (0x1<<8) +#define USB_CMD_ASP_10 (0x2<<8) +#define USB_CMD_ASP_11 (0x3<<8) +#define USB_CMD_ASP_BIT_POS (8) + +/* bit 23-16 are interrupt threshold control */ +#define USB_CMD_ITC_NO_THRESHOLD (0x00<<16) +#define USB_CMD_ITC_1_MICRO_FRM (0x01<<16) +#define USB_CMD_ITC_2_MICRO_FRM (0x02<<16) +#define USB_CMD_ITC_4_MICRO_FRM (0x04<<16) +#define USB_CMD_ITC_8_MICRO_FRM (0x08<<16) +#define USB_CMD_ITC_16_MICRO_FRM (0x10<<16) +#define USB_CMD_ITC_32_MICRO_FRM (0x20<<16) +#define USB_CMD_ITC_64_MICRO_FRM (0x40<<16) +#define USB_CMD_ITC_BIT_POS (16) + +/* USB Status Register Bit Masks */ +#define USB_STS_INT (0x1<<0) +#define USB_STS_ERR (0x1<<1) +#define USB_STS_PORT_CHANGE (0x1<<2) +#define USB_STS_FRM_LST_ROLL (0x1<<3) +#define USB_STS_SYS_ERR (0x1<<4) +#define USB_STS_IAA (0x1<<5) +#define USB_STS_RESET_RECEIVED (0x1<<6) +#define USB_STS_SOF (0x1<<7) +#define USB_STS_DCSUSPEND (0x1<<8) +#define USB_STS_HC_HALTED (0x1<<12) +#define USB_STS_RCL (0x1<<13) +#define USB_STS_PERIODIC_SCHEDULE (0x1<<14) +#define USB_STS_ASYNC_SCHEDULE (0x1<<15) + +/* USB Interrupt Enable Register Bit Masks */ +#define USB_INTR_INT_EN (0x1<<0) +#define USB_INTR_ERR_INT_EN (0x1<<1) +#define USB_INTR_PC_DETECT_EN (0x1<<2) +#define USB_INTR_FRM_LST_ROLL_EN (0x1<<3) +#define USB_INTR_SYS_ERR_EN (0x1<<4) +#define USB_INTR_ASYN_ADV_EN (0x1<<5) +#define USB_INTR_RESET_EN (0x1<<6) +#define USB_INTR_SOF_EN (0x1<<7) +#define USB_INTR_DEVICE_SUSPEND (0x1<<8) + +/* Device Address bit masks */ +#define USB_DEVICE_ADDRESS_MASK (0x7F<<25) +#define USB_DEVICE_ADDRESS_BIT_POS (25) +/* PORTSC Register Bit Masks,Only one PORT in OTG mode*/ +#define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0) +#define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1) +#define PORTSC_PORT_ENABLE (0x1<<2) +#define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3) +#define PORTSC_OVER_CURRENT_ACT (0x1<<4) +#define PORTSC_OVER_CUURENT_CHG (0x1<<5) +#define PORTSC_PORT_FORCE_RESUME (0x1<<6) +#define PORTSC_PORT_SUSPEND (0x1<<7) +#define PORTSC_PORT_RESET (0x1<<8) +#define PORTSC_LINE_STATUS_BITS (0x3<<10) +#define PORTSC_PORT_POWER (0x1<<12) +#define PORTSC_PORT_INDICTOR_CTRL (0x3<<14) +#define PORTSC_PORT_TEST_CTRL (0xF<<16) +#define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20) +#define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21) +#define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22) +#define PORTSC_PHY_LOW_POWER_SPD (0x1<<23) +#define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24) +#define PORTSC_PORT_SPEED_MASK (0x3<<26) +#define PORTSC_TRANSCEIVER_WIDTH (0x1<<28) +#define PORTSC_PHY_TYPE_SEL (0x3<<30) +/* bit 11-10 are line status */ +#define PORTSC_LINE_STATUS_SE0 (0x0<<10) +#define PORTSC_LINE_STATUS_JSTATE (0x1<<10) +#define PORTSC_LINE_STATUS_KSTATE (0x2<<10) +#define PORTSC_LINE_STATUS_UNDEF (0x3<<10) +#define PORTSC_LINE_STATUS_BIT_POS (10) + +/* bit 15-14 are port indicator control */ +#define PORTSC_PIC_OFF (0x0<<14) +#define PORTSC_PIC_AMBER (0x1<<14) +#define PORTSC_PIC_GREEN (0x2<<14) +#define PORTSC_PIC_UNDEF (0x3<<14) +#define PORTSC_PIC_BIT_POS (14) + +/* bit 19-16 are port test control */ +#define PORTSC_PTC_DISABLE (0x0<<16) +#define PORTSC_PTC_JSTATE (0x1<<16) +#define PORTSC_PTC_KSTATE (0x2<<16) +#define PORTSC_PTC_SEQNAK (0x3<<16) +#define PORTSC_PTC_PACKET (0x4<<16) +#define PORTSC_PTC_FORCE_EN (0x5<<16) +#define PORTSC_PTC_BIT_POS (16) + +/* bit 27-26 are port speed */ +#define PORTSC_PORT_SPEED_FULL (0x0<<26) +#define PORTSC_PORT_SPEED_LOW (0x1<<26) +#define PORTSC_PORT_SPEED_HIGH (0x2<<26) +#define PORTSC_PORT_SPEED_UNDEF (0x3<<26) +#define PORTSC_SPEED_BIT_POS (26) + +/* bit 28 is parallel transceiver width for UTMI interface */ +#define PORTSC_PTW (0x1<<28) +#define PORTSC_PTW_8BIT (0x0<<28) +#define PORTSC_PTW_16BIT (0x1<<28) + +/* bit 31-30 are port transceiver select */ +#define PORTSC_PTS_UTMI (0x0<<30) +#define PORTSC_PTS_ULPI (0x2<<30) +#define PORTSC_PTS_FSLS_SERIAL (0x3<<30) +#define PORTSC_PTS_BIT_POS (30) + +#define PORTSC_W1C_BITS \ + (PORTSC_CONNECT_STATUS_CHANGE | \ + PORTSC_PORT_EN_DIS_CHANGE | \ + PORTSC_OVER_CUURENT_CHG) + +/* OTG Status Control Register Bit Masks */ +#define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0) +#define OTGSC_CTRL_VBUS_CHARGE (0x1<<1) +#define OTGSC_CTRL_OTG_TERMINATION (0x1<<3) +#define OTGSC_CTRL_DATA_PULSING (0x1<<4) +#define OTGSC_CTRL_ID_PULL_EN (0x1<<5) +#define OTGSC_HA_DATA_PULSE (0x1<<6) +#define OTGSC_HA_BA (0x1<<7) +#define OTGSC_STS_USB_ID (0x1<<8) +#define OTGSC_STS_A_VBUS_VALID (0x1<<9) +#define OTGSC_STS_A_SESSION_VALID (0x1<<10) +#define OTGSC_STS_B_SESSION_VALID (0x1<<11) +#define OTGSC_STS_B_SESSION_END (0x1<<12) +#define OTGSC_STS_1MS_TOGGLE (0x1<<13) +#define OTGSC_STS_DATA_PULSING (0x1<<14) +#define OTGSC_INTSTS_USB_ID (0x1<<16) +#define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17) +#define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18) +#define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19) +#define OTGSC_INTSTS_B_SESSION_END (0x1<<20) +#define OTGSC_INTSTS_1MS (0x1<<21) +#define OTGSC_INTSTS_DATA_PULSING (0x1<<22) +#define OTGSC_INTR_USB_ID_EN (0x1<<24) +#define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25) +#define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26) +#define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27) +#define OTGSC_INTR_B_SESSION_END_EN (0x1<<28) +#define OTGSC_INTR_1MS_TIMER_EN (0x1<<29) +#define OTGSC_INTR_DATA_PULSING_EN (0x1<<30) +#define OTGSC_INTSTS_MASK (0x00ff0000) + +/* USB MODE Register Bit Masks */ +#define USB_MODE_CTRL_MODE_IDLE (0x0<<0) +#define USB_MODE_CTRL_MODE_DEVICE (0x2<<0) +#define USB_MODE_CTRL_MODE_HOST (0x3<<0) +#define USB_MODE_CTRL_MODE_RSV (0x1<<0) +#define USB_MODE_SETUP_LOCK_OFF (0x1<<3) +#define USB_MODE_STREAM_DISABLE (0x1<<4) +#define USB_MODE_ES (0x1<<2) /* (big) Endian Select */ + +#define MPC8349_OTG_IRQ (38) +#define CFG_IMMR_BASE (0xfe000000) +#define MPC83xx_USB_DR_BASE (CFG_IMMR_BASE + 0x23000) + +/* control Register Bit Masks */ +#define USB_CTRL_IOENB (0x1<<2) +#define USB_CTRL_ULPI_INT0EN (0x1<<0) + +/* BCSR5 */ +#define BCSR5_INT_USB (0x02) + +/* USB module clk cfg */ +#define SCCR_OFFS (0xA08) +#define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */ +#define SCCR_USB_MPHCM_11 (0x00c00000) +#define SCCR_USB_MPHCM_01 (0x00400000) +#define SCCR_USB_MPHCM_10 (0x00800000) +#define SCCR_USB_DRCM_11 (0x00300000) +#define SCCR_USB_DRCM_01 (0x00100000) +#define SCCR_USB_DRCM_10 (0x00200000) + +#define SICRL_OFFS (0x114) +#define SICRL_USB0 (0x40000000) +#define SICRL_USB1 (0x20000000) + +#define SICRH_OFFS (0x118) +#define SICRH_USB_UTMI (0x00020000) + +/* OTG interrupt enable bit masks */ +#define OTGSC_INTERRUPT_ENABLE_BITS_MASK \ + (OTGSC_INTR_USB_ID_EN | \ + OTGSC_INTR_1MS_TIMER_EN | \ + OTGSC_INTR_A_VBUS_VALID_EN | \ + OTGSC_INTR_A_SESSION_VALID_EN | \ + OTGSC_INTR_B_SESSION_VALID_EN | \ + OTGSC_INTR_B_SESSION_END_EN | \ + OTGSC_INTR_DATA_PULSING_EN) + +/* OTG interrupt status bit masks */ +#define OTGSC_INTERRUPT_STATUS_BITS_MASK \ + (OTGSC_INTSTS_USB_ID | \ + OTGSC_INTR_1MS_TIMER_EN | \ + OTGSC_INTSTS_A_VBUS_VALID | \ + OTGSC_INTSTS_A_SESSION_VALID | \ + OTGSC_INTSTS_B_SESSION_VALID | \ + OTGSC_INTSTS_B_SESSION_END | \ + OTGSC_INTSTS_DATA_PULSING) + +/* + * A-DEVICE timing constants + */ + +/* Wait for VBUS Rise */ +#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */ + +/* Wait for B-Connect */ +#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2 + * This is only used to get out of + * OTG_STATE_A_WAIT_BCON state if there was + * no connection for these many milliseconds + */ + +/* A-Idle to B-Disconnect */ +/* It is necessary for this timer to be more than 750 ms because of a bug in OPT + * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated + * in the test description + */ +#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */ + +/* B-Idle to A-Disconnect */ +#define TA_BIDL_ADIS (12) /* 3 to 200 ms */ + +/* B-device timing constants */ + + +/* Data-Line Pulse Time*/ +#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */ +#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */ +#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */ + +/* SRP Initiate Time */ +#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */ + +/* SRP Fail Time */ +#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/ + +/* SRP result wait time */ +#define TB_SRP_WAIT (60) + +/* VBus time */ +#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */ + +/* Discharge time */ +/* This time should be less than 10ms. It varies from system to system. */ +#define TB_VBUS_DSCHRG (8) + +/* A-SE0 to B-Reset */ +#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */ + +/* A bus suspend timer before we can switch to b_wait_aconn */ +#define TB_A_SUSPEND (7) +#define TB_BUS_RESUME (12) + +/* SE0 Time Before SRP */ +#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */ + + +#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate) + +struct usb_dr_mmap { + /* Capability register */ + u8 res1[256]; + u16 caplength; /* Capability Register Length */ + u16 hciversion; /* Host Controller Interface Version */ + u32 hcsparams; /* Host Controller Structual Parameters */ + u32 hccparams; /* Host Controller Capability Parameters */ + u8 res2[20]; + u32 dciversion; /* Device Controller Interface Version */ + u32 dccparams; /* Device Controller Capability Parameters */ + u8 res3[24]; + /* Operation register */ + u32 usbcmd; /* USB Command Register */ + u32 usbsts; /* USB Status Register */ + u32 usbintr; /* USB Interrupt Enable Register */ + u32 frindex; /* Frame Index Register */ + u8 res4[4]; + u32 deviceaddr; /* Device Address */ + u32 endpointlistaddr; /* Endpoint List Address Register */ + u8 res5[4]; + u32 burstsize; /* Master Interface Data Burst Size Register */ + u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ + u8 res6[8]; + u32 ulpiview; /* ULPI register access */ + u8 res7[12]; + u32 configflag; /* Configure Flag Register */ + u32 portsc; /* Port 1 Status and Control Register */ + u8 res8[28]; + u32 otgsc; /* On-The-Go Status and Control */ + u32 usbmode; /* USB Mode Register */ + u32 endptsetupstat; /* Endpoint Setup Status Register */ + u32 endpointprime; /* Endpoint Initialization Register */ + u32 endptflush; /* Endpoint Flush Register */ + u32 endptstatus; /* Endpoint Status Register */ + u32 endptcomplete; /* Endpoint Complete Register */ + u32 endptctrl[6]; /* Endpoint Control Registers */ + u8 res9[552]; + u32 snoop1; + u32 snoop2; + u32 age_cnt_thresh; /* Age Count Threshold Register */ + u32 pri_ctrl; /* Priority Control Register */ + u32 si_ctrl; /* System Interface Control Register */ + u8 res10[236]; +#ifdef CONFIG_ARCH_MX5 + u32 res11[128]; +#endif + u32 control; /* General Purpose Control Register */ +}; + + +struct fsl_otg_timer { + unsigned long expires; /* Number of count increase to timeout */ + unsigned long count; /* Tick counter */ + void (*function)(unsigned long); /* Timeout function */ + unsigned long data; /* Data passed to function */ + struct list_head list; +}; + +inline struct fsl_otg_timer *otg_timer_initializer +(void (*function)(unsigned long), unsigned long expires, unsigned long data) +{ + struct fsl_otg_timer *timer; + timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL); + if (timer == NULL) + return NULL; + timer->function = function; + timer->expires = expires; + timer->data = data; + return timer; +} + +struct fsl_otg { + struct otg_transceiver otg; + struct otg_fsm fsm; + struct usb_dr_mmap *dr_mem_map; + struct delayed_work otg_event; + + /*used for usb host */ + struct work_struct work_wq; + u8 host_working; + + int irq; +}; + +struct fsl_otg_config { + u8 otg_port; +}; + +/*For SRP and HNP handle*/ +#define FSL_OTG_MAJOR 66 +#define FSL_OTG_NAME "fsl-usb2-otg" +/*Command to OTG driver(ioctl)*/ +#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR +/*if otg work as host,it should return 1,otherwise it return 0*/ +#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int) +#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int) +#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int) +#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int) +#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int) +#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int) +#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int) +#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int) +#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int) + +extern const char *state_string(enum usb_otg_state state); diff --git a/drivers/usb/otg/otg_fsm.c b/drivers/usb/otg/otg_fsm.c new file mode 100644 index 000000000000..cfd2a404f0bd --- /dev/null +++ b/drivers/usb/otg/otg_fsm.c @@ -0,0 +1,371 @@ +/* OTG Finite State Machine from OTG spec + * + * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. + * + * Author: Li Yang + * Jerry Huang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "otg_fsm.h" + + +/* Defined by device specific driver, for different timer implementation */ +extern void *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr, + *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr, *a_wait_enum_tmr; + +const char *state_string(enum usb_otg_state state) +{ + switch (state) { + case OTG_STATE_A_IDLE: return "a_idle"; + case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; + case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; + case OTG_STATE_A_HOST: return "a_host"; + case OTG_STATE_A_SUSPEND: return "a_suspend"; + case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; + case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; + case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; + case OTG_STATE_B_IDLE: return "b_idle"; + case OTG_STATE_B_SRP_INIT: return "b_srp_init"; + case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; + case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; + case OTG_STATE_B_HOST: return "b_host"; + default: return "UNDEFINED"; + } +} + +/* Change USB protocol when there is a protocol change */ +static int otg_set_protocol(struct otg_fsm *fsm, int protocol) +{ + int ret = 0; + + if (fsm->protocol != protocol) { + VDBG("Changing role fsm->protocol= %d; new protocol= %d\n", + fsm->protocol, protocol); + /* stop old protocol */ + if (fsm->protocol == PROTO_HOST) + ret = fsm->ops->start_host(fsm, 0); + else if (fsm->protocol == PROTO_GADGET) + ret = fsm->ops->start_gadget(fsm, 0); + if (ret) + return ret; + + /* start new protocol */ + if (protocol == PROTO_HOST) + ret = fsm->ops->start_host(fsm, 1); + else if (protocol == PROTO_GADGET) + ret = fsm->ops->start_gadget(fsm, 1); + if (ret) + return ret; + + fsm->protocol = protocol; + return 0; + } + + return 0; +} + +static int state_changed; + +/* Called when leaving a state. Do state clean up jobs here */ +void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state) +{ + switch (old_state) { + case OTG_STATE_B_IDLE: + otg_del_timer(fsm, b_se0_srp_tmr); + fsm->b_se0_srp = 0; + break; + case OTG_STATE_B_SRP_INIT: + fsm->b_srp_done = 0; + break; + case OTG_STATE_B_PERIPHERAL: + break; + case OTG_STATE_B_WAIT_ACON: + otg_del_timer(fsm, b_ase0_brst_tmr); + fsm->b_ase0_brst_tmout = 0; + break; + case OTG_STATE_B_HOST: + break; + case OTG_STATE_A_IDLE: + break; + case OTG_STATE_A_WAIT_VRISE: + otg_del_timer(fsm, a_wait_vrise_tmr); + fsm->a_wait_vrise_tmout = 0; + break; + case OTG_STATE_A_WAIT_BCON: + otg_del_timer(fsm, a_wait_bcon_tmr); + fsm->a_wait_bcon_tmout = 0; + break; + case OTG_STATE_A_HOST: + otg_del_timer(fsm, a_wait_enum_tmr); + break; + case OTG_STATE_A_SUSPEND: + otg_del_timer(fsm, a_aidl_bdis_tmr); + fsm->a_aidl_bdis_tmout = 0; + fsm->a_suspend_req = 0; + break; + case OTG_STATE_A_PERIPHERAL: + break; + case OTG_STATE_A_WAIT_VFALL: + otg_del_timer(fsm, a_wait_vrise_tmr); + break; + case OTG_STATE_A_VBUS_ERR: + break; + default: + break; + } +} + +/* Called when entering a state */ +int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state) +{ + state_changed = 1; + if (fsm->transceiver->state == new_state) + return 0; + VDBG("Set state: %s \n", state_string(new_state)); + otg_leave_state(fsm, fsm->transceiver->state); + switch (new_state) { + case OTG_STATE_B_IDLE: + otg_drv_vbus(fsm, 0); + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_UNDEF); + otg_add_timer(fsm, b_se0_srp_tmr); + break; + case OTG_STATE_B_SRP_INIT: + otg_start_pulse(fsm); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_UNDEF); + otg_add_timer(fsm, b_srp_fail_tmr); + break; + case OTG_STATE_B_PERIPHERAL: + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 1); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_GADGET); + break; + case OTG_STATE_B_WAIT_ACON: + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + otg_add_timer(fsm, b_ase0_brst_tmr); + fsm->a_bus_suspend = 0; + break; + case OTG_STATE_B_HOST: + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 1); + otg_set_protocol(fsm, PROTO_HOST); + usb_bus_start_enum(fsm->transceiver->host, + fsm->transceiver->host->otg_port); + break; + case OTG_STATE_A_IDLE: + otg_drv_vbus(fsm, 0); + otg_chrg_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + break; + case OTG_STATE_A_WAIT_VRISE: + otg_drv_vbus(fsm, 1); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + otg_add_timer(fsm, a_wait_vrise_tmr); + break; + case OTG_STATE_A_WAIT_BCON: + otg_drv_vbus(fsm, 1); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + otg_add_timer(fsm, a_wait_bcon_tmr); + break; + case OTG_STATE_A_HOST: + otg_drv_vbus(fsm, 1); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 1); + otg_set_protocol(fsm, PROTO_HOST); + /* When HNP is triggered while a_bus_req = 0, a_host will + * suspend too fast to complete a_set_b_hnp_en */ + if (!fsm->a_bus_req || fsm->a_suspend_req) + otg_add_timer(fsm, a_wait_enum_tmr); + break; + case OTG_STATE_A_SUSPEND: + otg_drv_vbus(fsm, 1); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + otg_add_timer(fsm, a_aidl_bdis_tmr); + + break; + case OTG_STATE_A_PERIPHERAL: + otg_loc_conn(fsm, 1); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_GADGET); + otg_drv_vbus(fsm, 1); + break; + case OTG_STATE_A_WAIT_VFALL: + otg_drv_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_HOST); + break; + case OTG_STATE_A_VBUS_ERR: + otg_drv_vbus(fsm, 0); + otg_loc_conn(fsm, 0); + otg_loc_sof(fsm, 0); + otg_set_protocol(fsm, PROTO_UNDEF); + break; + default: + break; + } + + fsm->transceiver->state = new_state; + return 0; +} + +/* State change judgement */ +int otg_statemachine(struct otg_fsm *fsm) +{ + enum usb_otg_state state; + unsigned long flags; + + spin_lock_irqsave(&fsm->lock, flags); + + state = fsm->transceiver->state; + state_changed = 0; + /* State machine state change judgement */ + + switch (state) { + case OTG_STATE_UNDEFINED: + VDBG("fsm->id = %d \n", fsm->id); + if (fsm->id) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else + otg_set_state(fsm, OTG_STATE_A_IDLE); + break; + case OTG_STATE_B_IDLE: + if (!fsm->id) + otg_set_state(fsm, OTG_STATE_A_IDLE); + else if (fsm->b_sess_vld && fsm->transceiver->gadget) + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); + else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp) + otg_set_state(fsm, OTG_STATE_B_SRP_INIT); + break; + case OTG_STATE_B_SRP_INIT: + if (!fsm->id || fsm->b_srp_done) + otg_set_state(fsm, OTG_STATE_B_IDLE); + break; + case OTG_STATE_B_PERIPHERAL: + if (!fsm->id || !fsm->b_sess_vld) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else if (fsm->b_bus_req && fsm->transceiver-> + gadget->b_hnp_enable && fsm->a_bus_suspend) + otg_set_state(fsm, OTG_STATE_B_WAIT_ACON); + break; + case OTG_STATE_B_WAIT_ACON: + if (fsm->a_conn) + otg_set_state(fsm, OTG_STATE_B_HOST); + else if (!fsm->id || !fsm->b_sess_vld) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) { + fsm->b_ase0_brst_tmout = 0; + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); + } + break; + case OTG_STATE_B_HOST: + if (!fsm->id || !fsm->b_sess_vld) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else if (!fsm->b_bus_req || !fsm->a_conn) + otg_set_state(fsm, OTG_STATE_B_PERIPHERAL); + break; + case OTG_STATE_A_IDLE: + if (fsm->id) + otg_set_state(fsm, OTG_STATE_B_IDLE); + else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det)) + otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE); + break; + case OTG_STATE_A_WAIT_VRISE: + if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld || + fsm->a_wait_vrise_tmout) { + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); + } + break; + case OTG_STATE_A_WAIT_BCON: + if (!fsm->a_vbus_vld) + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); + else if (fsm->b_conn) + otg_set_state(fsm, OTG_STATE_A_HOST); + else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout) + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); + break; + case OTG_STATE_A_HOST: + if ((!fsm->a_bus_req || fsm->a_suspend_req) && + fsm->transceiver->host->b_hnp_enable) + otg_set_state(fsm, OTG_STATE_A_SUSPEND); + else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop) + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); + else if (!fsm->a_vbus_vld) + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); + break; + case OTG_STATE_A_SUSPEND: + if (!fsm->b_conn && fsm->transceiver->host->b_hnp_enable) + otg_set_state(fsm, OTG_STATE_A_PERIPHERAL); + else if (!fsm->b_conn && !fsm->transceiver->host->b_hnp_enable) + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); + else if (fsm->a_bus_req || fsm->b_bus_resume) + otg_set_state(fsm, OTG_STATE_A_HOST); + else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout) + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); + else if (!fsm->a_vbus_vld) + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); + break; + case OTG_STATE_A_PERIPHERAL: + if (fsm->id || fsm->a_bus_drop) + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); + else if (fsm->b_bus_suspend) + otg_set_state(fsm, OTG_STATE_A_WAIT_BCON); + else if (!fsm->a_vbus_vld) + otg_set_state(fsm, OTG_STATE_A_VBUS_ERR); + break; + case OTG_STATE_A_WAIT_VFALL: + if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld && + !fsm->b_conn)) + otg_set_state(fsm, OTG_STATE_A_IDLE); + break; + case OTG_STATE_A_VBUS_ERR: + if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err) + otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL); + break; + default: + break; + } + spin_unlock_irqrestore(&fsm->lock, flags); + + /* VDBG("quit statemachine, changed = %d \n", state_changed); */ + return state_changed; +} diff --git a/drivers/usb/otg/otg_fsm.h b/drivers/usb/otg/otg_fsm.h new file mode 100644 index 000000000000..8fb6764b959e --- /dev/null +++ b/drivers/usb/otg/otg_fsm.h @@ -0,0 +1,151 @@ +/* Copyright (C) 2006-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#if 0 +#define DEBUG 1 +#define VERBOSE 1 +#endif + +#ifdef DEBUG +#define DBG(fmt, args...) printk(KERN_DEBUG "j=%lu [%s] " fmt "\n", jiffies, \ + __func__, ## args) +#else +#define DBG(fmt, args...) do {} while (0) +#endif + +#ifdef VERBOSE +#define VDBG DBG +#else +#define VDBG(stuff...) do {} while (0) +#endif + +#ifdef VERBOSE +#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__) +#else +#define MPC_LOC do {} while (0) +#endif + +#define PROTO_UNDEF (0) +#define PROTO_HOST (1) +#define PROTO_GADGET (2) + +/* OTG state machine according to the OTG spec */ +struct otg_fsm { + /* Input */ + int a_bus_resume; + int a_bus_suspend; + int a_conn; + int a_sess_vld; + int a_srp_det; + int a_vbus_vld; + int b_bus_resume; + int b_bus_suspend; + int b_conn; + int b_se0_srp; + int b_sess_end; + int b_sess_vld; + int id; + + /* Internal variables */ + int a_set_b_hnp_en; + int b_srp_done; + int b_hnp_enable; + + /* Timeout indicator for timers */ + int a_wait_vrise_tmout; + int a_wait_bcon_tmout; + int a_aidl_bdis_tmout; + int b_ase0_brst_tmout; + + /* Informative variables */ + int a_bus_drop; + int a_bus_req; + int a_clr_err; + int a_suspend_req; + int b_bus_req; + + /* Output */ + int drv_vbus; + int loc_conn; + int loc_sof; + + struct otg_fsm_ops *ops; + struct otg_transceiver *transceiver; + + /* Current usb protocol used: 0:undefine; 1:host; 2:client */ + int protocol; + spinlock_t lock; +}; + +struct otg_fsm_ops { + void (*chrg_vbus)(int on); + void (*drv_vbus)(int on); + void (*loc_conn)(int on); + void (*loc_sof)(int on); + void (*start_pulse)(void); + void (*add_timer)(void *timer); + void (*del_timer)(void *timer); + int (*start_host)(struct otg_fsm *fsm, int on); + int (*start_gadget)(struct otg_fsm *fsm, int on); +}; + + +static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on) +{ + fsm->ops->chrg_vbus(on); +} + +static inline void otg_drv_vbus(struct otg_fsm *fsm, int on) +{ + if (fsm->drv_vbus != on) { + fsm->drv_vbus = on; + fsm->ops->drv_vbus(on); + } +} + +static inline void otg_loc_conn(struct otg_fsm *fsm, int on) +{ + if (fsm->loc_conn != on) { + fsm->loc_conn = on; + fsm->ops->loc_conn(on); + } +} + +static inline void otg_loc_sof(struct otg_fsm *fsm, int on) +{ + if (fsm->loc_sof != on) { + fsm->loc_sof = on; + fsm->ops->loc_sof(on); + } +} + +static inline void otg_start_pulse(struct otg_fsm *fsm) +{ + fsm->ops->start_pulse(); +} + +static inline void otg_add_timer(struct otg_fsm *fsm, void *timer) +{ + fsm->ops->add_timer(timer); +} + +static inline void otg_del_timer(struct otg_fsm *fsm, void *timer) +{ + fsm->ops->del_timer(timer); +} + +int otg_statemachine(struct otg_fsm *fsm); diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c index a7d0bf9d92a7..dd9ec0bd6aa3 100644 --- a/drivers/usb/storage/usb.c +++ b/drivers/usb/storage/usb.c @@ -334,8 +334,11 @@ static int usb_stor_control_thread(void * __us) /* we've got a command, let's do it! */ else { - US_DEBUG(usb_stor_show_command(us->srb)); - us->proto_handler(us->srb, us); + US_DEBUGP(usb_stor_show_command(us->srb)); +#ifdef CONFIG_MACH_MX51_BABBAGE + if (us->srb->cmnd[0] != 0x85) +#endif + us->proto_handler(us->srb, us); } /* lock access to the state */ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 3d94a1471724..cff7be3ca1b1 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -389,6 +389,14 @@ config FB_CLPS711X Say Y to enable the Framebuffer driver for the CLPS7111 and EP7212 processors. +if ARCH_MXC +source "drivers/video/mxc/Kconfig" +endif + +if ARCH_MXS +source "drivers/video/mxs/Kconfig" +endif + config FB_SA1100 bool "SA-1100 LCD support" depends on (FB = y) && ARM && ARCH_SA1100 diff --git a/drivers/video/Makefile b/drivers/video/Makefile index ddc2af2ba45b..2d95727f0415 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -119,6 +119,8 @@ obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ +obj-$(CONFIG_FB_MXC) += mxc/ +obj-$(CONFIG_FB_MXS) += mxs/ obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o obj-$(CONFIG_FB_PS3) += ps3fb.o obj-$(CONFIG_FB_SM501) += sm501fb.o diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index e54a337227ea..78c4649a48f8 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -168,6 +168,14 @@ config BACKLIGHT_GENERIC known as the Corgi backlight driver. If you have a Sharp Zaurus SL-C7xx, SL-Cxx00 or SL-6000x say y. +config BACKLIGHT_DA9052 + tristate "Dialog DA9052 WLED" + depends on PMIC_DA9052 + help + Enable the DA9052 Backlight Driver + + To compile this driver as a module, choose M here. + config BACKLIGHT_LOCOMO tristate "Sharp LOCOMO LCD/Backlight Driver" depends on SHARP_LOCOMO @@ -307,6 +315,39 @@ config BACKLIGHT_PCF50633 If you have a backlight driven by a NXP PCF50633 MFD, say Y here to enable its driver. +config BACKLIGHT_MXC_IPU + tristate "IPU PWM Backlight Driver" + depends on MXC_IPU_V1 + default y + +config BACKLIGHT_MXC_LCDC + tristate "LCDC PWM Backlight Driver" + depends on (ARCH_MX21 || ARCH_MX27 || ARCH_MX25) + default y + +config BACKLIGHT_MXC_PMIC + tristate "PMIC Backlight Driver" + depends on MXC_MC13783_LIGHT + depends on MXC_MC13783_POWER + default y + +config BACKLIGHT_MXC_MC13892 + tristate "Mc13892 Backlight Driver" + depends on MXC_MC13892_LIGHT + default y + +config BACKLIGHT_MXS + tristate "Freescale MXS Backlight Driver" + depends on ARCH_MXS + default y + help + If you have a MXS, say y to enable the backlight driver. + +config BACKLIGHT_WM8350 + tristate "WM8350 Backlight Driver" + depends on REGULATOR_WM8350 + default y + endif # BACKLIGHT_CLASS_DEVICE endif # BACKLIGHT_LCD_SUPPORT diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index 44c0f81ad85d..1c67fdedc17e 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_LCD_CLASS_DEVICE) += lcd.o obj-$(CONFIG_LCD_CORGI) += corgi_lcd.o +obj-$(CONFIG_BACKLIGHT_DA9052) += da9052_bl.o obj-$(CONFIG_LCD_HP700) += jornada720_lcd.o obj-$(CONFIG_LCD_L4F00242T03) += l4f00242t03.o obj-$(CONFIG_LCD_LMS283GF05) += lms283gf05.o @@ -36,3 +37,9 @@ obj-$(CONFIG_BACKLIGHT_ADP8860) += adp8860_bl.o obj-$(CONFIG_BACKLIGHT_88PM860X) += 88pm860x_bl.o obj-$(CONFIG_BACKLIGHT_PCF50633) += pcf50633-backlight.o +obj-$(CONFIG_BACKLIGHT_MXC_LCDC) += mxc_lcdc_bl.o +obj-$(CONFIG_BACKLIGHT_MXC_IPU) += mxc_ipu_bl.o +obj-$(CONFIG_BACKLIGHT_MXC_PMIC) += mxc_pmic_bl.o +obj-$(CONFIG_BACKLIGHT_WM8350) += wm8350_bl.o +obj-$(CONFIG_BACKLIGHT_MXC_MC13892) += mxc_mc13892_bl.o +obj-$(CONFIG_BACKLIGHT_MXS) += mxs_bl.o diff --git a/drivers/video/backlight/da9052_bl.c b/drivers/video/backlight/da9052_bl.c new file mode 100644 index 000000000000..5cfcb471d337 --- /dev/null +++ b/drivers/video/backlight/da9052_bl.c @@ -0,0 +1,439 @@ +/* + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * da9052_bl.c: Backlight driver for DA9052 + */ + +#include +#include +#include + +#include +#include +#include + + +#define DRIVER_NAME "da9052-backlight" +#define DRIVER_NAME1 "WLED-1" +#define DRIVER_NAME2 "WLED-2" +#define DRIVER_NAME3 "WLED-3" + +/* These flags define if Backlight LEDs are present */ +/* Set the following macros to 1, if LEDs are present. Otherwise set to 0 */ +#define DA9052_LED1_PRESENT 1 +#define DA9052_LED2_PRESENT 1 +#define DA9052_LED3_PRESENT 1 + +#define DA9052_MAX_BRIGHTNESS 0xA0/*0xFF*/ + +struct da9052_backlight_data { + struct device *da9052_dev; + int current_brightness; + struct da9052 *da9052; + + int is_led1_present; + int is_led2_present; + int is_led3_present; +}; + +enum da9052_led_number { + LED1 = 1, + LED2, + LED3, +}; + +static int da9052_backlight_brightness_set(struct da9052_backlight_data *data, + int brightness, enum da9052_led_number led) +{ + /* + * Mechanism for brightness control: + * For brightness control, current is used. + * PWM feature is not used. + * To use PWM feature, a fixed value of current should be defined. + */ + + int ret = 0; + + unsigned int led_ramp_bit; + unsigned int led_current_register; + unsigned int led_current_sink_bit; + unsigned int led_boost_en_bit; + + struct da9052_ssc_msg msg; + + switch (led) { + case LED1: + led_ramp_bit = DA9052_LEDCONT_LED1RAMP; + led_current_register = DA9052_LED1CONF_REG; + led_current_sink_bit = DA9052_LEDCONT_LED1EN; + led_boost_en_bit = DA9052_BOOST_LED1INEN; + break; + case LED2: + led_ramp_bit = DA9052_LEDCONT_LED2RAMP; + led_current_register = DA9052_LED2CONF_REG; + led_current_sink_bit = DA9052_LEDCONT_LED2EN; + led_boost_en_bit = DA9052_BOOST_LED2INEN; + break; + case LED3: + led_ramp_bit = DA9052_LEDCONT_LED3RAMP; + led_current_register = DA9052_LED3CONF_REG; + led_current_sink_bit = DA9052_LEDCONT_LED3EN; + led_boost_en_bit = DA9052_BOOST_LED3INEN; + break; + default: + return -EIO; + } + + /* + * 3 registers to be written + * 1. LED current for brightness + * 2. LED enable/disable depending on the brightness + * 3. BOOST enable/disable depending on the brightness + */ + + /* Configure LED current i.e. brightness */ + msg.addr = led_current_register; + msg.data = brightness; + /* Write to the DA9052 register */ + da9052_lock(data->da9052); + ret = data->da9052->write(data->da9052, &msg); + if (ret) { + da9052_unlock(data->da9052); + return ret; + } + da9052_unlock(data->da9052); + + /* + * Check if brightness = 0 + * and decide if led to be disabled + */ + msg.addr = DA9052_LEDCONT_REG; + msg.data = 0; + + /* Read LED_CONT register */ + da9052_lock(data->da9052); + ret = data->da9052->read(data->da9052, &msg); + if (ret) { + da9052_unlock(data->da9052); + return ret; + } + da9052_unlock(data->da9052); + + /* Set/Clear the LED current sink bit */ + msg.data = brightness ? (msg.data | led_current_sink_bit) : + (msg.data & ~(led_current_sink_bit)); + /* Disable current ramping */ + msg.data = (msg.data & ~(led_ramp_bit)); + + /* Write to the DA9052 register */ + da9052_lock(data->da9052); + ret = data->da9052->write(data->da9052, &msg); + if (ret) { + da9052_unlock(data->da9052); + return ret; + } + da9052_unlock(data->da9052); + + /* Configure BOOST */ + msg.addr = DA9052_BOOST_REG; + msg.data = 0; + + /* Read LED_CONT register */ + da9052_lock(data->da9052); + ret = data->da9052->read(data->da9052, &msg); + if (ret) { + da9052_unlock(data->da9052); + return ret; + } + da9052_unlock(data->da9052); + + /* Set/Clear the LED BOOST enable bit */ + msg.data = brightness ? (msg.data | led_boost_en_bit) : + (msg.data & ~(led_boost_en_bit)); + /* Set/Clear the BOOST converter enable bit */ + + if (0 == (data->is_led1_present | data->is_led2_present | + data->is_led3_present)) { + msg.data = msg.data & ~(DA9052_BOOST_BOOSTEN); + } else + msg.data = (msg.data | DA9052_BOOST_BOOSTEN); + + /* Write to the DA9052 register */ + da9052_lock(data->da9052); + ret = data->da9052->write(data->da9052, &msg); + if (ret) { + da9052_unlock(data->da9052); + return ret; + } + da9052_unlock(data->da9052); + + return 0; +} + +static int da9052_backlight_set(struct backlight_device *bl, int brightness) +{ + struct da9052_backlight_data *data = bl_get_data(bl); + int ret = 0; + /* Check for LED1 */ + if (1 == data->is_led1_present) { + ret = da9052_backlight_brightness_set(data, brightness, LED1); + if (ret) + return ret; + } + /* Check for LED2 */ + if (1 == data->is_led2_present) { + ret = da9052_backlight_brightness_set(data, brightness, LED2); + if (ret) + return ret; + } + /* Check for LED3 */ + if (1 == data->is_led3_present) { + ret = da9052_backlight_brightness_set(data, brightness, LED3); + if (ret) + return ret; + } + + data->current_brightness = brightness; + return 0; +} + +static int da9052_backlight_update_status(struct backlight_device *bl) +{ + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK) + brightness = 0; + + if (bl->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + return da9052_backlight_set(bl, brightness); +} + +static int da9052_backlight_get_brightness(struct backlight_device *bl) +{ + struct da9052_backlight_data *data = bl_get_data(bl); + return data->current_brightness; +} + +struct backlight_ops da9052_backlight_ops = { + .update_status = da9052_backlight_update_status, + .get_brightness = da9052_backlight_get_brightness, +}; + +static int da9052_backlight_probe1(struct platform_device *pdev) +{ + struct da9052_backlight_data *data; + struct backlight_device *bl; + struct backlight_properties props; + struct da9052 *da9052 = dev_get_drvdata(pdev->dev.parent); + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + data->da9052_dev = pdev->dev.parent; + data->da9052 = da9052; + data->current_brightness = 0; + + data->is_led1_present = DA9052_LED1_PRESENT; + + bl = backlight_device_register(pdev->name, data->da9052_dev, + data, &da9052_backlight_ops, &props); +#if 0 /* Commented to be integrated with 2.6.28 kernel */ + bl = backlight_device_register(pdev->name, data->da9052_dev, + data, &da9052_backlight_ops); +#endif + if (IS_ERR(bl)) { + dev_err(&pdev->dev, "failed to register backlight\n"); + kfree(data); + return PTR_ERR(bl); + } + + bl->props.max_brightness = DA9052_MAX_BRIGHTNESS; + bl->props.brightness = 0; + bl->props.power = FB_BLANK_UNBLANK; + bl->props.fb_blank = FB_BLANK_UNBLANK; + platform_set_drvdata(pdev, bl); + + backlight_update_status(bl); + + /* + * NOTE: + * The default settings for DA9052 registers depends upon OTP values. + * E.g. The configuration of BOOST register, minimum value for LED + * current etc. are taken from OTP + */ + + return 0; +} +static int da9052_backlight_probe2(struct platform_device *pdev) +{ + struct da9052_backlight_data *data; + struct backlight_device *bl; + struct backlight_properties props; + struct da9052 *da9052 = dev_get_drvdata(pdev->dev.parent); + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + data->da9052_dev = pdev->dev.parent; + data->da9052 = da9052; + data->current_brightness = 0; + + data->is_led2_present = DA9052_LED2_PRESENT; + bl = backlight_device_register(pdev->name, data->da9052_dev, + data, &da9052_backlight_ops, &props); + if (IS_ERR(bl)) { + dev_err(&pdev->dev, "failed to register backlight\n"); + kfree(data); + return PTR_ERR(bl); + } + + bl->props.max_brightness = DA9052_MAX_BRIGHTNESS; + bl->props.brightness = 0; + bl->props.power = FB_BLANK_UNBLANK; + bl->props.fb_blank = FB_BLANK_UNBLANK; + platform_set_drvdata(pdev, bl); + + backlight_update_status(bl); + + /* + * NOTE: + * The default settings for DA9052 registers depends upon OTP values. + * E.g. The configuration of BOOST register, minimum value for LED + * current etc. are taken from OTP + */ + + return 0; +} +static int da9052_backlight_probe3(struct platform_device *pdev) +{ + struct da9052_backlight_data *data; + struct backlight_device *bl; + struct backlight_properties props; + + struct da9052 *da9052 = dev_get_drvdata(pdev->dev.parent); + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + data->da9052_dev = pdev->dev.parent; + data->da9052 = da9052; + data->current_brightness = 0; + + data->is_led3_present = DA9052_LED3_PRESENT; + bl = backlight_device_register(pdev->name, data->da9052_dev, + data, &da9052_backlight_ops, &props); + if (IS_ERR(bl)) { + dev_err(&pdev->dev, "failed to register backlight\n"); + kfree(data); + return PTR_ERR(bl); + } + + bl->props.max_brightness = DA9052_MAX_BRIGHTNESS; + bl->props.brightness = 0; + bl->props.power = FB_BLANK_UNBLANK; + bl->props.fb_blank = FB_BLANK_UNBLANK; + platform_set_drvdata(pdev, bl); + + backlight_update_status(bl); + + /* + * NOTE: + * The default settings for DA9052 registers depends upon OTP values. + * E.g. The configuration of BOOST register, minimum value for LED + * current etc. are taken from OTP + */ + + return 0; +} + +static int da9052_backlight_remove1(struct platform_device *pdev) +{ + struct backlight_device *bl = platform_get_drvdata(pdev); + struct da9052_backlight_data *data = bl_get_data(bl); + + backlight_device_unregister(bl); + kfree(data); + return 0; +} + +static int da9052_backlight_remove2(struct platform_device *pdev) +{ + struct backlight_device *bl = platform_get_drvdata(pdev); + struct da9052_backlight_data *data = bl_get_data(bl); + + backlight_device_unregister(bl); + kfree(data); + return 0; +} +static int da9052_backlight_remove3(struct platform_device *pdev) +{ + struct backlight_device *bl = platform_get_drvdata(pdev); + struct da9052_backlight_data *data = bl_get_data(bl); + + backlight_device_unregister(bl); + kfree(data); + return 0; +} + +static struct platform_driver da9052_backlight_driver1 = { + .driver = { + .name = DRIVER_NAME1, + .owner = THIS_MODULE, + }, + .probe = da9052_backlight_probe1, + .remove = da9052_backlight_remove1, +}; +static struct platform_driver da9052_backlight_driver2 = { + .driver = { + .name = DRIVER_NAME2, + .owner = THIS_MODULE, + }, + .probe = da9052_backlight_probe2, + .remove = da9052_backlight_remove2, +}; +static struct platform_driver da9052_backlight_driver3 = { + .driver = { + .name = DRIVER_NAME3, + .owner = THIS_MODULE, + }, + .probe = da9052_backlight_probe3, + .remove = da9052_backlight_remove3, +}; + +static int __init da9052_backlight_init(void) +{ + s32 ret; + ret = platform_driver_register(&da9052_backlight_driver1); + if (ret) + return ret; + ret = platform_driver_register(&da9052_backlight_driver2); + if (ret) + return ret; + + ret = platform_driver_register(&da9052_backlight_driver3); + if (ret) + return ret; + + return ret; +} +module_init(da9052_backlight_init); + +static void __exit da9052_backlight_exit(void) +{ + platform_driver_unregister(&da9052_backlight_driver1); + platform_driver_unregister(&da9052_backlight_driver2); + platform_driver_unregister(&da9052_backlight_driver3); +} +module_exit(da9052_backlight_exit); + +MODULE_AUTHOR("Dialog Semiconductor Ltd "); +MODULE_DESCRIPTION("Backlight driver for Dialog DA9052 PMIC"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); + diff --git a/drivers/video/backlight/mxc_ipu_bl.c b/drivers/video/backlight/mxc_ipu_bl.c new file mode 100644 index 000000000000..fd6ea227989f --- /dev/null +++ b/drivers/video/backlight/mxc_ipu_bl.c @@ -0,0 +1,158 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @defgroup IPU_BL MXC IPU Backlight Driver + */ +/*! + * @file mxc_ipu_bl.c + * + * @brief Backlight Driver for IPU PWM on Freescale MXC/i.MX platforms. + * + * This file contains API defined in include/linux/clk.h for setting up and + * retrieving clocks. + * + * Based on Sharp's Corgi Backlight Driver + * + * @ingroup IPU_BL + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_MAX_INTENSITY 255 +#define MXC_DEFAULT_INTENSITY 127 +#define MXC_INTENSITY_OFF 0 + +struct mxcbl_dev_data { + int intensity; +}; + +static int fb_id; + +static int mxcbl_send_intensity(struct backlight_device *bd) +{ + int intensity = bd->props.brightness; + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + + ipu_sdc_set_brightness(intensity); + + devdata->intensity = intensity; + return 0; +} + +static int mxcbl_get_intensity(struct backlight_device *bd) +{ + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + return devdata->intensity; +} + +static int mxcbl_check_fb(struct backlight_device *bldev, struct fb_info *info) +{ + int id = info->fix.id[4] - '0'; + if (id == fb_id) { + if ((id == 3) && !strcmp(info->fix.id, "DISP3 FG")) { + return 0; + } + return 1; + } + return 0; +} + +static struct backlight_ops mxcbl_ops = { + .get_brightness = mxcbl_get_intensity, + .update_status = mxcbl_send_intensity, + .check_fb = mxcbl_check_fb, +}; + +static int __init mxcbl_probe(struct platform_device *pdev) +{ + struct backlight_device *bd; + struct mxcbl_dev_data *devdata; + struct backlight_properties props; + int ret = 0; + + devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL); + if (!devdata) + return -ENOMEM; + fb_id = (int)pdev->dev.platform_data; + + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = MXC_MAX_INTENSITY; + bd = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, devdata, + &mxcbl_ops, &props); + if (IS_ERR(bd)) { + ret = PTR_ERR(bd); + goto err0; + } + platform_set_drvdata(pdev, bd); + + bd->props.brightness = MXC_DEFAULT_INTENSITY; + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + backlight_update_status(bd); + + printk("MXC Backlight Device %s Initialized.\n", dev_name(&pdev->dev)); + return 0; + err0: + kfree(devdata); + return ret; +} + +static int mxcbl_remove(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + + bd->props.brightness = MXC_INTENSITY_OFF; + backlight_update_status(bd); + + backlight_device_unregister(bd); + + return 0; +} + +static struct platform_driver mxcbl_driver = { + .probe = mxcbl_probe, + .remove = mxcbl_remove, + .driver = { + .name = "mxc_ipu_bl", + }, +}; + +static int __init mxcbl_init(void) +{ + return platform_driver_register(&mxcbl_driver); +} + +static void __exit mxcbl_exit(void) +{ + platform_driver_unregister(&mxcbl_driver); +} + +late_initcall(mxcbl_init); +module_exit(mxcbl_exit); + +MODULE_DESCRIPTION("Freescale MXC/i.MX IPU PWM Backlight Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/backlight/mxc_lcdc_bl.c b/drivers/video/backlight/mxc_lcdc_bl.c new file mode 100644 index 000000000000..e49d72632290 --- /dev/null +++ b/drivers/video/backlight/mxc_lcdc_bl.c @@ -0,0 +1,164 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @defgroup LCDC_BL MXC LCDC Backlight Driver + */ +/*! + * @file mxc_lcdc_bl.c + * + * @brief Backlight Driver for LCDC PWM on Freescale MXC/i.MX platforms. + * + * This file contains API defined in include/linux/clk.h for setting up and + * retrieving clocks. + * + * Based on Sharp's Corgi Backlight Driver + * + * @ingroup LCDC_BL + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MXC_MAX_INTENSITY 255 +#define MXC_DEFAULT_INTENSITY 127 +#define MXC_INTENSITY_OFF 0 + +extern void mx2fb_set_brightness(uint8_t); + +struct mxcbl_dev_data { + struct clk *clk; + int intensity; +}; + +static int mxcbl_send_intensity(struct backlight_device *bd) +{ + int intensity = bd->props.brightness; + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + + if ((devdata->intensity == 0) && (intensity != 0)) + clk_enable(devdata->clk); + + /* PWM contrast control register */ + mx2fb_set_brightness(intensity); + + if ((devdata->intensity != 0) && (intensity == 0)) + clk_disable(devdata->clk); + + devdata->intensity = intensity; + return 0; +} + +static int mxcbl_get_intensity(struct backlight_device *bd) +{ + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + return devdata->intensity; +} + +static int mxcbl_check_fb(struct backlight_device *bd, struct fb_info *info) +{ + if (strcmp(info->fix.id, "DISP0 BG") == 0) { + return 1; + } + return 0; +} + +static struct backlight_ops mxcbl_ops = { + .get_brightness = mxcbl_get_intensity, + .update_status = mxcbl_send_intensity, + .check_fb = mxcbl_check_fb, +}; + +static int __init mxcbl_probe(struct platform_device *pdev) +{ + struct backlight_device *bd; + struct mxcbl_dev_data *devdata; + struct backlight_properties props; + int ret = 0; + + devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL); + if (!devdata) + return -ENOMEM; + + devdata->clk = clk_get(NULL, "lcdc_clk"); + + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = MXC_MAX_INTENSITY; + + bd = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, devdata, + &mxcbl_ops, &props); + if (IS_ERR(bd)) { + ret = PTR_ERR(bd); + goto err0; + } + platform_set_drvdata(pdev, bd); + + bd->props.brightness = MXC_DEFAULT_INTENSITY; + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + mx2fb_set_brightness(MXC_DEFAULT_INTENSITY); + + printk("MXC Backlight Device %s Initialized.\n", dev_name(&pdev->dev)); + return 0; + err0: + kfree(devdata); + return ret; +} + +static int mxcbl_remove(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + + bd->props.brightness = MXC_INTENSITY_OFF; + backlight_update_status(bd); + + backlight_device_unregister(bd); + + return 0; +} + +static struct platform_driver mxcbl_driver = { + .probe = mxcbl_probe, + .remove = mxcbl_remove, + .driver = { + .name = "mxc_lcdc_bl", + }, +}; + +static int __init mxcbl_init(void) +{ + return platform_driver_register(&mxcbl_driver); +} + +static void __exit mxcbl_exit(void) +{ + platform_driver_unregister(&mxcbl_driver); +} + +module_init(mxcbl_init); +module_exit(mxcbl_exit); + +MODULE_DESCRIPTION("Freescale MXC/i.MX LCDC PWM Backlight Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/backlight/mxc_mc13892_bl.c b/drivers/video/backlight/mxc_mc13892_bl.c new file mode 100644 index 000000000000..752cae445c5a --- /dev/null +++ b/drivers/video/backlight/mxc_mc13892_bl.c @@ -0,0 +1,180 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* +#define MXC_MAX_INTENSITY 255 +#define MXC_DEFAULT_INTENSITY 127 +*/ +/* workaround for atlas hot issue */ +#define MXC_MAX_INTENSITY 128 +#define MXC_DEFAULT_INTENSITY 64 + +#define MXC_INTENSITY_OFF 0 + +struct mxcbl_dev_data { + int intensity; + int suspend; +}; + +static int mxcbl_set_intensity(struct backlight_device *bd) +{ + int brightness = bd->props.brightness; + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + if (bd->props.power != FB_BLANK_UNBLANK) + brightness = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + brightness = 0; + if (devdata->suspend) + brightness = 0; + + brightness = brightness / 4; + mc13892_bklit_set_dutycycle(LIT_MAIN, brightness); + devdata->intensity = brightness; + + return 0; +} + +static int mxcbl_get_intensity(struct backlight_device *bd) +{ + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + return devdata->intensity; +} + +static int mxcbl_check_fb(struct backlight_device *bldev, struct fb_info *info) +{ + char *id = info->fix.id; + + if (!strcmp(id, "DISP3 BG")) + return 1; + else + return 0; +} + +static struct backlight_ops bl_ops; + +static int __init mxcbl_probe(struct platform_device *pdev) +{ + int ret = 0; + struct backlight_device *bd; + struct mxcbl_dev_data *devdata; + struct backlight_properties props; + pmic_version_t pmic_version; + + pr_debug("mc13892 backlight start probe\n"); + + devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL); + if (!devdata) + return -ENOMEM; + + bl_ops.check_fb = mxcbl_check_fb; + bl_ops.get_brightness = mxcbl_get_intensity; + bl_ops.update_status = mxcbl_set_intensity; + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = MXC_MAX_INTENSITY; + bd = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, devdata, + &bl_ops, &props); + if (IS_ERR(bd)) { + ret = PTR_ERR(bd); + goto err0; + } + + platform_set_drvdata(pdev, bd); + + /* according to LCD spec, current should be 18mA */ + /* workaround for MC13892 TO1.1 crash issue, set current 6mA */ + pmic_version = pmic_get_version(); + if (pmic_version.revision < 20) + mc13892_bklit_set_current(LIT_MAIN, LIT_CURR_6); + else + mc13892_bklit_set_current(LIT_MAIN, LIT_CURR_18); + bd->props.brightness = MXC_DEFAULT_INTENSITY; + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + backlight_update_status(bd); + pr_debug("mc13892 backlight probed successfully\n"); + return 0; + + err0: + kfree(devdata); + return ret; +} + +static int mxcbl_remove(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + kfree(devdata); + backlight_device_unregister(bd); + return 0; +} + +static int mxcbl_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + devdata->suspend = 1; + backlight_update_status(bd); + return 0; +} + +static int mxcbl_resume(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + devdata->suspend = 0; + backlight_update_status(bd); + return 0; +} + +static struct platform_driver mxcbl_driver = { + .probe = mxcbl_probe, + .remove = mxcbl_remove, + .suspend = mxcbl_suspend, + .resume = mxcbl_resume, + .driver = { + .name = "mxc_mc13892_bl", + }, +}; + +static int __init mxcbl_init(void) +{ + return platform_driver_register(&mxcbl_driver); +} + +static void __exit mxcbl_exit(void) +{ + platform_driver_unregister(&mxcbl_driver); +} + +module_init(mxcbl_init); +module_exit(mxcbl_exit); + +MODULE_DESCRIPTION("Freescale MXC/i.MX PMIC Backlight Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/backlight/mxc_pmic_bl.c b/drivers/video/backlight/mxc_pmic_bl.c new file mode 100644 index 000000000000..b8ac44132bfa --- /dev/null +++ b/drivers/video/backlight/mxc_pmic_bl.c @@ -0,0 +1,200 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/*! + * @defgroup PMIC_BL MXC PMIC Backlight Driver + */ +/*! + * @file mxc_pmic_bl.c + * + * @brief PMIC Backlight Driver for Freescale MXC/i.MX platforms. + * + * This file contains API defined in include/linux/clk.h for setting up and + * retrieving clocks. + * + * Based on Sharp's Corgi Backlight Driver + * + * @ingroup PMIC_BL + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MXC_MAX_INTENSITY 255 +#define MXC_DEFAULT_INTENSITY 127 +#define MXC_INTENSITY_OFF 0 + +struct mxcbl_dev_data { + int bl_id; + int intensity; + struct backlight_ops bl_ops; +}; + +static int pmic_bl_use_count; +static int main_fb_id; +static int sec_fb_id; + +static int mxcbl_send_intensity(struct backlight_device *bd) +{ + int intensity = bd->props.brightness; + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + + intensity = intensity / 16; + pmic_bklit_set_dutycycle(devdata->bl_id, intensity); + + devdata->intensity = intensity; + return 0; +} + +static int mxcbl_get_intensity(struct backlight_device *bd) +{ + struct mxcbl_dev_data *devdata = dev_get_drvdata(&bd->dev); + return devdata->intensity; +} + +static int mxcbl_check_main_fb(struct fb_info *info) +{ + int id = info->fix.id[4] - '0'; + + if (id == main_fb_id) { + return 1; + } else { + return 0; + } +} + +static int mxcbl_check_sec_fb(struct backlight_device *bldev, struct fb_info *info) +{ + int id = info->fix.id[4] - '0'; + + if (id == sec_fb_id) { + return 1; + } else { + return 0; + } +} + +static int __init mxcbl_probe(struct platform_device *pdev) +{ + int ret = 0; + struct backlight_device *bd; + struct mxcbl_dev_data *devdata; + struct backlight_properties props; + + devdata = kzalloc(sizeof(struct mxcbl_dev_data), GFP_KERNEL); + if (!devdata) + return -ENOMEM; + devdata->bl_id = pdev->id; + + if (pdev->id == 0) { + devdata->bl_ops.check_fb = mxcbl_check_main_fb; + main_fb_id = (int)pdev->dev.platform_data; + } else { + devdata->bl_ops.check_fb = mxcbl_check_sec_fb; + sec_fb_id = (int)pdev->dev.platform_data; + } + + devdata->bl_ops.get_brightness = mxcbl_get_intensity; + devdata->bl_ops.update_status = mxcbl_send_intensity, + memset(&props, 0, sizeof(struct backlight_properties)); + props.max_brightness = MXC_MAX_INTENSITY; + bd = + backlight_device_register(dev_name(&pdev->dev), &pdev->dev, devdata, + &devdata->bl_ops, &props); + if (IS_ERR(bd)) { + ret = PTR_ERR(bd); + goto err0; + } + + platform_set_drvdata(pdev, bd); + + if (pmic_bl_use_count++ == 0) { + pmic_power_regulator_on(SW_SW3); + pmic_power_regulator_set_lp_mode(SW_SW3, LOW_POWER_CTRL_BY_PIN); + + pmic_bklit_tcled_master_enable(); + pmic_bklit_enable_edge_slow(); + pmic_bklit_set_cycle_time(0); + } + + pmic_bklit_set_current(devdata->bl_id, 7); + bd->props.brightness = MXC_DEFAULT_INTENSITY; + bd->props.power = FB_BLANK_UNBLANK; + bd->props.fb_blank = FB_BLANK_UNBLANK; + backlight_update_status(bd); + + printk("MXC Backlight Device %s Initialized.\n", dev_name(&pdev->dev)); + return 0; + err0: + kfree(devdata); + return ret; +} + +static int mxcbl_remove(struct platform_device *pdev) +{ + struct backlight_device *bd = platform_get_drvdata(pdev); + + bd->props.brightness = MXC_INTENSITY_OFF; + backlight_update_status(bd); + + if (--pmic_bl_use_count == 0) { + pmic_bklit_tcled_master_disable(); + + pmic_power_regulator_off(SW_SW3); + pmic_power_regulator_set_lp_mode(SW_SW3, LOW_POWER_CTRL_BY_PIN); + } + + backlight_device_unregister(bd); + + printk("MXC Backlight Driver Unloaded\n"); + + return 0; +} + +static struct platform_driver mxcbl_driver = { + .probe = mxcbl_probe, + .remove = mxcbl_remove, + .driver = { + .name = "mxc_pmic_bl", + }, +}; + +static int __init mxcbl_init(void) +{ + return platform_driver_register(&mxcbl_driver); +} + +static void __exit mxcbl_exit(void) +{ + platform_driver_unregister(&mxcbl_driver); +} + +module_init(mxcbl_init); +module_exit(mxcbl_exit); + +MODULE_DESCRIPTION("Freescale MXC/i.MX PMIC Backlight Driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/backlight/mxs_bl.c b/drivers/video/backlight/mxs_bl.c new file mode 100644 index 000000000000..271fd2907f59 --- /dev/null +++ b/drivers/video/backlight/mxs_bl.c @@ -0,0 +1,387 @@ +/* + * Backlight Driver for Freescale MXS + * + * Embedded Alley Solutions, Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct mxs_bl_data { + struct notifier_block nb; + struct notifier_block reg_nb; + struct notifier_block reg_init_nb; + struct backlight_device *bd; + struct mxs_platform_bl_data *pdata; + int current_intensity; + int saved_intensity; + int mxsbl_suspended; + int mxsbl_constrained; +}; + +static int mxsbl_do_probe(struct mxs_bl_data *data, + struct mxs_platform_bl_data *pdata); +static int mxsbl_set_intensity(struct backlight_device *bd); +static inline void bl_register_reg(struct mxs_platform_bl_data *pdata, + struct mxs_bl_data *data); + + +/* + * If we got here init is done + */ +static int bl_init_reg_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct mxs_bl_data *bdata; + struct mxs_platform_bl_data *pdata; + struct regulator *r = regulator_get(NULL, "mxs-bl-1"); + + bdata = container_of(self, struct mxs_bl_data, reg_init_nb); + pdata = bdata->pdata; + + if (r && !IS_ERR(r)) + regulator_put(r); + else + goto out; + + bl_register_reg(pdata, bdata); + + if (pdata->regulator) { + + printk(KERN_NOTICE"%s: setting intensity\n", __func__); + + bus_unregister_notifier(&platform_bus_type, + &bdata->reg_init_nb); + mutex_lock(&bdata->bd->ops_lock); + mxsbl_set_intensity(bdata->bd); + mutex_unlock(&bdata->bd->ops_lock); + } + +out: + return 0; +} + +static int bl_reg_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct mxs_bl_data *bdata; + struct mxs_platform_bl_data *pdata; + bdata = container_of(self, struct mxs_bl_data, reg_nb); + pdata = bdata->pdata; + + mutex_lock(&bdata->bd->ops_lock); + + switch (event) { + case MXS_REG5V_IS_USB: + bdata->bd->props.max_brightness = pdata->bl_cons_intensity; + bdata->bd->props.brightness = pdata->bl_cons_intensity; + bdata->saved_intensity = bdata->current_intensity; + bdata->mxsbl_constrained = 1; + break; + case MXS_REG5V_NOT_USB: + bdata->bd->props.max_brightness = pdata->bl_max_intensity; + bdata->bd->props.brightness = bdata->saved_intensity; + bdata->mxsbl_constrained = 0; + break; + } + + mxsbl_set_intensity(bdata->bd); + mutex_unlock(&bdata->bd->ops_lock); + return 0; +} + +static inline void bl_unregister_reg(struct mxs_platform_bl_data *pdata, + struct mxs_bl_data *data) +{ + if (!pdata) + return; + if (pdata->regulator) + regulator_unregister_notifier(pdata->regulator, + &data->reg_nb); + if (pdata->regulator) + regulator_put(pdata->regulator); + pdata->regulator = NULL; +} + +static inline void bl_register_reg(struct mxs_platform_bl_data *pdata, + struct mxs_bl_data *data) +{ + pdata->regulator = regulator_get(NULL, "mxs-bl-1"); + if (pdata->regulator && !IS_ERR(pdata->regulator)) { + regulator_set_mode(pdata->regulator, REGULATOR_MODE_FAST); + if (pdata->regulator) { + data->reg_nb.notifier_call = bl_reg_callback; + regulator_register_notifier(pdata->regulator, + &data->reg_nb); + } + } else{ + printk(KERN_ERR "%s: failed to get regulator\n", __func__); + pdata->regulator = NULL; + } + +} + +static int bl_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct mxs_platform_fb_entry *pentry = data; + struct mxs_bl_data *bdata; + struct mxs_platform_bl_data *pdata; + + switch (event) { + case MXS_LCDIF_PANEL_INIT: + bdata = container_of(self, struct mxs_bl_data, nb); + pdata = pentry->bl_data; + bdata->pdata = pdata; + if (pdata) { + bl_register_reg(pdata, bdata); + if (!pdata->regulator) { + /* wait for regulator to appear */ + bdata->reg_init_nb.notifier_call = + bl_init_reg_callback; + bus_register_notifier(&platform_bus_type, + &bdata->reg_init_nb); + } + return mxsbl_do_probe(bdata, pdata); + } + break; + + case MXS_LCDIF_PANEL_RELEASE: + bdata = container_of(self, struct mxs_bl_data, nb); + pdata = pentry->bl_data; + if (pdata) { + bus_unregister_notifier(&platform_bus_type, + &bdata->reg_init_nb); + bl_unregister_reg(pdata, bdata); + pdata->free_bl(pdata); + } + bdata->pdata = NULL; + break; + } + return 0; +} + +#ifdef CONFIG_PM +static int mxsbl_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mxs_bl_data *data = platform_get_drvdata(pdev); + struct mxs_platform_bl_data *pdata = data->pdata; + + data->mxsbl_suspended = 1; + if (pdata) { + dev_dbg(&pdev->dev, "real suspend\n"); + mxsbl_set_intensity(data->bd); + } + return 0; +} + +static int mxsbl_resume(struct platform_device *pdev) +{ + struct mxs_bl_data *data = platform_get_drvdata(pdev); + struct mxs_platform_bl_data *pdata = data->pdata; + int ret = 0; + + data->mxsbl_suspended = 0; + if (pdata) { + dev_dbg(&pdev->dev, "real resume\n"); + pdata->free_bl(pdata); + ret = pdata->init_bl(pdata); + if (ret) + goto out; + mxsbl_set_intensity(data->bd); + } +out: + return ret; +} +#else +#define mxsbl_suspend NULL +#define mxsbl_resume NULL +#endif +/* + * This function should be called with bd->ops_lock held + * Suspend/resume ? + */ +static int mxsbl_set_intensity(struct backlight_device *bd) +{ + struct platform_device *pdev = dev_get_drvdata(&bd->dev); + struct mxs_bl_data *data = platform_get_drvdata(pdev); + struct mxs_platform_bl_data *pdata = data->pdata; + + if (pdata) { + int ret; + + ret = pdata->set_bl_intensity(pdata, bd, + data->mxsbl_suspended); + if (ret) + bd->props.brightness = data->current_intensity; + else + data->current_intensity = bd->props.brightness; + return ret; + } else + return -ENODEV; +} + +static int mxsbl_get_intensity(struct backlight_device *bd) +{ + struct platform_device *pdev = dev_get_drvdata(&bd->dev); + struct mxs_bl_data *data = platform_get_drvdata(pdev); + + return data->current_intensity; +} + +static struct backlight_ops mxsbl_ops = { + .get_brightness = mxsbl_get_intensity, + .update_status = mxsbl_set_intensity, +}; + +static int mxsbl_do_probe(struct mxs_bl_data *data, + struct mxs_platform_bl_data *pdata) +{ + int ret = pdata->init_bl(pdata); + + if (ret) + goto out; + + data->bd->props.power = FB_BLANK_UNBLANK; + data->bd->props.fb_blank = FB_BLANK_UNBLANK; + + if (!data->mxsbl_suspended) + if (data->mxsbl_constrained) { + data->bd->props.max_brightness = pdata->bl_cons_intensity; + data->bd->props.brightness = pdata->bl_cons_intensity; + } else { + data->bd->props.max_brightness = pdata->bl_max_intensity; + data->bd->props.brightness = pdata->bl_default_intensity; + } + + data->pdata = pdata; + mxsbl_set_intensity(data->bd); + +out: + return ret; +} + +static int __init mxsbl_probe(struct platform_device *pdev) +{ + struct mxs_bl_data *data; + struct mxs_platform_bl_data *pdata = pdev->dev.platform_data; + int ret = 0; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) { + ret = -ENOMEM; + goto out; + } + data->bd = backlight_device_register(pdev->name, &pdev->dev, pdev, + &mxsbl_ops, NULL); + if (IS_ERR(data->bd)) { + ret = PTR_ERR(data->bd); + goto out_1; + } + + get_device(&pdev->dev); + + data->nb.notifier_call = bl_callback; + mxs_lcdif_register_client(&data->nb); + platform_set_drvdata(pdev, data); + + if (pdata) { + ret = mxsbl_do_probe(data, pdata); + if (ret) + goto out_2; + } + + goto out; + +out_2: + put_device(&pdev->dev); +out_1: + kfree(data); +out: + return ret; +} + +static int mxsbl_remove(struct platform_device *pdev) +{ + struct mxs_platform_bl_data *pdata = pdev->dev.platform_data; + struct mxs_bl_data *data = platform_get_drvdata(pdev); + struct backlight_device *bd = data->bd; + + bd->props.power = FB_BLANK_POWERDOWN; + bd->props.fb_blank = FB_BLANK_POWERDOWN; + bd->props.brightness = 0; + data->current_intensity = bd->props.brightness; + + if (pdata) { + pdata->set_bl_intensity(pdata, bd, data->mxsbl_suspended); + if (pdata->free_bl) + pdata->free_bl(pdata); + } + backlight_device_unregister(bd); + if (pdata->regulator) + regulator_put(pdata->regulator); + put_device(&pdev->dev); + platform_set_drvdata(pdev, NULL); + mxs_lcdif_unregister_client(&data->nb); + kfree(data); + + return 0; +} + +static struct platform_driver mxsbl_driver = { + .probe = mxsbl_probe, + .remove = __devexit_p(mxsbl_remove), + .suspend = mxsbl_suspend, + .resume = mxsbl_resume, + .driver = { + .name = "mxs-bl", + .owner = THIS_MODULE, + }, +}; + +static int __init mxs_init(void) +{ + return platform_driver_register(&mxsbl_driver); +} + +static void __exit mxs_exit(void) +{ + platform_driver_unregister(&mxsbl_driver); +} + +module_init(mxs_init); +module_exit(mxs_exit); + +MODULE_AUTHOR("Embedded Alley Solutions, Inc "); +MODULE_DESCRIPTION("MXS Backlight Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c index 550443518891..3c14c923a3c7 100644 --- a/drivers/video/backlight/pwm_bl.c +++ b/drivers/video/backlight/pwm_bl.c @@ -59,9 +59,19 @@ static int pwm_backlight_get_brightness(struct backlight_device *bl) return bl->props.brightness; } +static int pwm_backlight_check_fb(struct fb_info *info) +{ + char *id = info->fix.id; + if (!strcmp(id, "DISP3 BG")) + return 1; + else + return 0; +} + static const struct backlight_ops pwm_backlight_ops = { .update_status = pwm_backlight_update_status, .get_brightness = pwm_backlight_get_brightness, + .check_fb = pwm_backlight_check_fb, }; static int pwm_backlight_probe(struct platform_device *pdev) diff --git a/drivers/video/backlight/wm8350_bl.c b/drivers/video/backlight/wm8350_bl.c new file mode 100644 index 000000000000..6865b753d8ce --- /dev/null +++ b/drivers/video/backlight/wm8350_bl.c @@ -0,0 +1,299 @@ +/* + * Backlight driver for DCDC2 on i.MX32ADS board + * + * Copyright(C) 2007 Wolfson Microelectronics PLC. + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct wm8350_backlight { + struct backlight_properties props; + struct backlight_device *device; + struct regulator *dcdc; + struct regulator *isink; + struct notifier_block notifier; + struct work_struct work; + struct mutex mutex; + int intensity; + int suspend; + int retries; +}; + +/* hundredths of uA, 405 = 4.05 uA */ +static const int intensity_huA[] = { + 405, 482, 573, 681, 810, 963, 1146, 1362, 1620, 1927, 2291, 2725, + 3240, 3853, 4582, 5449, 6480, 7706, 9164, 10898, 12960, 15412, 18328, + 21796, 25920, 30824, 36656, 43592, 51840, 61648, 73313, 87184, + 103680, 123297, 146626, 174368, 207360, 246594, 293251, 348737, + 414720, 493188, 586503, 697473, 829440, 986376, 1173005, 1394946, + 1658880, 1972752, 2346011, 2789892, 3317760, 3945504, 4692021, + 5579785, 6635520, 7891008, 9384042, 11159570, 13271040, 15782015, + 18768085, 22319140, +}; + +static void bl_work(struct work_struct *work) +{ + struct wm8350_backlight *bl = + container_of(work, struct wm8350_backlight, work); + struct regulator *isink = bl->isink; + + mutex_lock(&bl->mutex); + if (bl->intensity >= 0 && + bl->intensity < ARRAY_SIZE(intensity_huA)) { + bl->retries = 0; + regulator_set_current_limit(isink, + 0, intensity_huA[bl->intensity] / 100); + } else + printk(KERN_ERR "wm8350: Backlight intensity error\n"); + mutex_unlock(&bl->mutex); +} + +static int wm8350_bl_notifier(struct notifier_block *self, + unsigned long event, void *data) +{ + struct wm8350_backlight *bl = + container_of(self, struct wm8350_backlight, notifier); + struct regulator *isink = bl->isink; + + if (event & REGULATOR_EVENT_UNDER_VOLTAGE) + printk(KERN_ERR "wm8350: BL DCDC undervoltage\n"); + if (event & REGULATOR_EVENT_REGULATION_OUT) + printk(KERN_ERR "wm8350: BL ISINK out of regulation\n"); + + mutex_lock(&bl->mutex); + if (bl->retries) { + bl->retries--; + regulator_disable(isink); + regulator_set_current_limit(isink, 0, bl->intensity); + regulator_enable(isink); + } else { + printk(KERN_ERR + "wm8350: BL regulation retry failure - disable\n"); + bl->intensity = 0; + regulator_disable(isink); + } + mutex_unlock(&bl->mutex); + return 0; +} + +static int wm8350_bl_send_intensity(struct backlight_device *bd) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)dev_get_drvdata(&bd->dev); + int intensity = bd->props.brightness; + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + if (bl->suspend) + intensity = 0; + + mutex_lock(&bl->mutex); + bl->intensity = intensity; + mutex_unlock(&bl->mutex); + schedule_work(&bl->work); + + return 0; +} + +#ifdef CONFIG_PM +static int wm8350_bl_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)platform_get_drvdata(pdev); + + bl->suspend = 1; + backlight_update_status(bl->device); + return 0; +} + +static int wm8350_bl_resume(struct platform_device *pdev) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)platform_get_drvdata(pdev); + + bl->suspend = 0; + backlight_update_status(bl->device); + return 0; +} +#else +#define wm8350_bl_suspend NULL +#define wm8350_bl_resume NULL +#endif + +static int wm8350_bl_get_intensity(struct backlight_device *bd) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)dev_get_drvdata(&bd->dev); + return bl->intensity; +} + +static struct backlight_ops wm8350_bl_ops = { + .get_brightness = wm8350_bl_get_intensity, + .update_status = wm8350_bl_send_intensity, +}; + +static int wm8350_bl_probe(struct platform_device *pdev) +{ + struct regulator *isink, *dcdc; + struct wm8350_backlight *bl; + struct wm8350_bl_platform_data *pdata = pdev->dev.platform_data; + struct wm8350 *pmic; + int ret; + + if (pdata == NULL) { + printk(KERN_ERR "%s: no platform data\n", __func__); + return -ENODEV; + } + + if (pdata->isink != WM8350_ISINK_A && pdata->isink != WM8350_ISINK_B) { + printk(KERN_ERR "%s: invalid ISINK\n", __func__); + return -EINVAL; + } + if (pdata->dcdc != WM8350_DCDC_2 && pdata->dcdc != WM8350_DCDC_5) { + printk(KERN_ERR "%s: invalid DCDC\n", __func__); + return -EINVAL; + } + + printk(KERN_INFO "wm8350: backlight using %s and %s\n", + pdata->isink == WM8350_ISINK_A ? "ISINKA" : "ISINKB", + pdata->dcdc == WM8350_DCDC_2 ? "DCDC2" : "DCDC5"); + + isink = regulator_get(&pdev->dev, + pdata->isink == WM8350_ISINK_A ? "ISINKA" : "ISINKB"); + if (IS_ERR(isink) || isink == NULL) { + printk(KERN_ERR "%s: cant get ISINK\n", __func__); + return PTR_ERR(isink); + } + + dcdc = regulator_get(&pdev->dev, + pdata->dcdc == WM8350_DCDC_2 ? "DCDC2" : "DCDC5"); + if (IS_ERR(dcdc) || dcdc == NULL) { + printk(KERN_ERR "%s: cant get DCDC\n", __func__); + regulator_put(isink); + return PTR_ERR(dcdc); + } + + bl = kzalloc(sizeof(*bl), GFP_KERNEL); + if (bl == NULL) { + regulator_put(isink); + regulator_put(dcdc); + return -ENOMEM; + } + + mutex_init(&bl->mutex); + INIT_WORK(&bl->work, bl_work); + bl->props.max_brightness = pdata->max_brightness; + bl->props.power = pdata->power; + bl->props.brightness = pdata->brightness; + bl->retries = pdata->retries; + bl->dcdc = dcdc; + bl->isink = isink; + platform_set_drvdata(pdev, bl); + pmic = regulator_get_drvdata(bl->isink); + + wm8350_bl_ops.check_fb = pdata->check_fb; + + bl->device = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, + bl, &wm8350_bl_ops); + if (IS_ERR(bl->device)) { + ret = PTR_ERR(bl->device); + regulator_put(dcdc); + regulator_put(isink); + kfree(bl); + return ret; + } + + bl->notifier.notifier_call = wm8350_bl_notifier; + regulator_register_notifier(dcdc, &bl->notifier); + regulator_register_notifier(isink, &bl->notifier); + bl->device->props = bl->props; + + regulator_set_current_limit(isink, 0, 20000); + + wm8350_isink_set_flash(pmic, pdata->isink, + WM8350_ISINK_FLASH_DISABLE, + WM8350_ISINK_FLASH_TRIG_BIT, + WM8350_ISINK_FLASH_DUR_32MS, + WM8350_ISINK_FLASH_ON_1_00S, + WM8350_ISINK_FLASH_OFF_1_00S, + WM8350_ISINK_FLASH_MODE_EN); + + wm8350_dcdc25_set_mode(pmic, pdata->dcdc, + WM8350_ISINK_MODE_BOOST, WM8350_ISINK_ILIM_NORMAL, + pdata->voltage_ramp, pdata->isink == WM8350_ISINK_A ? + WM8350_DC5_FBSRC_ISINKA : WM8350_DC5_FBSRC_ISINKB); + + wm8350_dcdc_set_slot(pmic, pdata->dcdc, 15, 0, + pdata->dcdc == WM8350_DCDC_2 ? + WM8350_DC2_ERRACT_SHUTDOWN_CONV : WM8350_DC5_ERRACT_NONE); + + regulator_enable(isink); + backlight_update_status(bl->device); + return 0; +} + +static int wm8350_bl_remove(struct platform_device *pdev) +{ + struct wm8350_backlight *bl = + (struct wm8350_backlight *)platform_get_drvdata(pdev); + struct regulator *isink = bl->isink, *dcdc = bl->dcdc; + + bl->intensity = 0; + backlight_update_status(bl->device); + schedule_work(&bl->work); + flush_scheduled_work(); + backlight_device_unregister(bl->device); + + regulator_set_current_limit(isink, 0, 0); + regulator_disable(isink); + regulator_unregister_notifier(isink, &bl->notifier); + regulator_unregister_notifier(dcdc, &bl->notifier); + regulator_put(isink); + regulator_put(dcdc); + return 0; +} + +struct platform_driver imx32ads_backlight_driver = { + .driver = { + .name = "wm8350-bl", + .owner = THIS_MODULE, + }, + .probe = wm8350_bl_probe, + .remove = wm8350_bl_remove, + .suspend = wm8350_bl_suspend, + .resume = wm8350_bl_resume, +}; + +static int __devinit imx32ads_backlight_init(void) +{ + return platform_driver_register(&imx32ads_backlight_driver); +} + +static void imx32ads_backlight_exit(void) +{ + platform_driver_unregister(&imx32ads_backlight_driver); +} + +device_initcall_sync(imx32ads_backlight_init); +module_exit(imx32ads_backlight_exit); + +MODULE_AUTHOR("Liam Girdwood "); +MODULE_DESCRIPTION("WM8350 Backlight driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/Kconfig b/drivers/video/mxc/Kconfig new file mode 100644 index 000000000000..e2b79faeaf35 --- /dev/null +++ b/drivers/video/mxc/Kconfig @@ -0,0 +1,111 @@ +config FB_MXC + tristate "MXC Framebuffer support" + depends on FB && (MXC_IPU || ARCH_MX21 || ARCH_MX27 || ARCH_MX25) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MODE_HELPERS + default y + help + This is a framebuffer device for the MXC LCD Controller. + See for information on framebuffer + devices. + + If you plan to use the LCD display with your MXC system, say + Y here. + +config FB_MXC_SYNC_PANEL + depends on FB_MXC + tristate "Synchronous Panel Framebuffer" + default y + +config FB_MXC_EPSON_VGA_SYNC_PANEL + depends on FB_MXC_SYNC_PANEL + tristate "Epson VGA Panel" + default n + +config FB_MXC_TVOUT_TVE + tristate "MXC TVE TV Out Encoder" + depends on FB_MXC_SYNC_PANEL + depends on MXC_IPU_V3 + +config FB_MXC_LDB + tristate "MXC LDB" + depends on FB_MXC_SYNC_PANEL + depends on MXC_IPU_V3 + +config FB_MXC_CLAA_WVGA_SYNC_PANEL + depends on FB_MXC_SYNC_PANEL + tristate "CLAA WVGA Panel" + +config FB_MXC_SEIKO_WVGA_SYNC_PANEL + depends on FB_MXC_SYNC_PANEL + tristate "SEIKO WVGA Panel" + +config FB_MXC_SII902X + depends on FB_MXC_SYNC_PANEL + tristate "Si Image SII9022 DVI/HDMI Interface Chip" + +config FB_MXC_CH7026 + depends on FB_MXC_SYNC_PANEL + tristate "Chrontel CH7026 VGA Interface Chip" + +config FB_MXC_TVOUT_CH7024 + tristate "CH7024 TV Out Encoder" + depends on FB_MXC_SYNC_PANEL + +config FB_MXC_LOW_PWR_DISPLAY + bool "Low Power Display Refresh Mode" + depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM + default y + +config FB_MXC_INTERNAL_MEM + bool "Framebuffer in Internal RAM" + depends on FB_MXC_SYNC_PANEL && MXC_FB_IRAM + default y + +config FB_MXC_ASYNC_PANEL + depends on FB_MXC + bool "Asynchronous Panels" + default n + +menu "Asynchronous Panel Type" + depends on FB_MXC_ASYNC_PANEL && FB_MXC + +config FB_MXC_EPSON_PANEL + depends on FB_MXC_ASYNC_PANEL + default n + bool "Epson 176x220 Panel" + +endmenu + +config FB_MXC_EINK_PANEL + depends on FB_MXC + depends on DMA_ENGINE + select FB_DEFERRED_IO + tristate "E-Ink Panel Framebuffer" + +config FB_MXC_EINK_AUTO_UPDATE_MODE + bool "E-Ink Auto-update Mode Support" + default n + depends on FB_MXC_EINK_PANEL + +config FB_MXC_ELCDIF_FB + depends on FB && ARCH_MXC + tristate "Support MXC ELCDIF framebuffer" + +choice + prompt "Async Panel Interface Type" + depends on FB_MXC_ASYNC_PANEL && FB_MXC + default FB_MXC_ASYNC_PANEL_IFC_16_BIT + +config FB_MXC_ASYNC_PANEL_IFC_8_BIT + bool "8-bit Parallel Bus Interface" + +config FB_MXC_ASYNC_PANEL_IFC_16_BIT + bool "16-bit Parallel Bus Interface" + +config FB_MXC_ASYNC_PANEL_IFC_SERIAL + bool "Serial Bus Interface" + +endchoice diff --git a/drivers/video/mxc/Makefile b/drivers/video/mxc/Makefile new file mode 100644 index 000000000000..1b1a1dc73aef --- /dev/null +++ b/drivers/video/mxc/Makefile @@ -0,0 +1,26 @@ +obj-$(CONFIG_FB_MXC_TVOUT_TVE) += tve.o +obj-$(CONFIG_FB_MODE_HELPERS) += mxc_edid.o +obj-$(CONFIG_FB_MXC_SII902X) += mxcfb_sii902x.o +ifeq ($(CONFIG_ARCH_MX21)$(CONFIG_ARCH_MX27)$(CONFIG_ARCH_MX25),y) + obj-$(CONFIG_FB_MXC_TVOUT) += fs453.o + obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mx2fb.o mxcfb_modedb.o + obj-$(CONFIG_FB_MXC_EPSON_PANEL) += mx2fb_epson.o +else +ifeq ($(CONFIG_MXC_IPU_V1),y) + obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxcfb.o mxcfb_modedb.o +else + obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_ipuv3_fb.o +endif + obj-$(CONFIG_FB_MXC_EPSON_PANEL) += mxcfb_epson.o + obj-$(CONFIG_FB_MXC_EPSON_QVGA_PANEL) += mxcfb_epson_qvga.o + obj-$(CONFIG_FB_MXC_TOSHIBA_QVGA_PANEL) += mxcfb_toshiba_qvga.o + obj-$(CONFIG_FB_MXC_SHARP_128_PANEL) += mxcfb_sharp_128x128.o +endif +obj-$(CONFIG_FB_MXC_LDB) += ldb.o +obj-$(CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL) += mxcfb_epson_vga.o +obj-$(CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL) += mxcfb_claa_wvga.o +obj-$(CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL) += mxcfb_seiko_wvga.o +obj-$(CONFIG_FB_MXC_TVOUT_CH7024) += ch7024.o +obj-$(CONFIG_FB_MXC_CH7026) += mxcfb_ch7026.o +obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o +obj-$(CONFIG_FB_MXC_ELCDIF_FB) += mxc_elcdif_fb.o diff --git a/drivers/video/mxc/ch7024.c b/drivers/video/mxc/ch7024.c new file mode 100644 index 000000000000..48e6b09feecb --- /dev/null +++ b/drivers/video/mxc/ch7024.c @@ -0,0 +1,866 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ch7024.c + * @brief Driver for CH7024 TV encoder + * + * @ingroup Framebuffer + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*! + * CH7024 registers + */ +#define CH7024_DEVID 0x00 +#define CH7024_REVID 0x01 +#define CH7024_PG 0x02 + +#define CH7024_RESET 0x03 +#define CH7024_POWER 0x04 +#define CH7024_TVHUE 0x05 +#define CH7024_TVSAT 0x06 +#define CH7024_TVCTA 0x07 +#define CH7024_TVBRI 0x08 +#define CH7024_TVSHARP 0x09 +#define CH7024_OUT_FMT 0x0A +#define CH7024_XTAL 0x0B +#define CH7024_IDF1 0x0C +#define CH7024_IDF2 0x0D +#define CH7024_SYNC 0x0E +#define CH7024_TVFILTER1 0x0F +#define CH7024_TVFILTER2 0x10 +#define CH7024_IN_TIMING1 0x11 +#define CH7024_IN_TIMING2 0x12 +#define CH7024_IN_TIMING3 0x13 +#define CH7024_IN_TIMING4 0x14 +#define CH7024_IN_TIMING5 0x15 +#define CH7024_IN_TIMING6 0x16 +#define CH7024_IN_TIMING7 0x17 +#define CH7024_IN_TIMING8 0x18 +#define CH7024_IN_TIMING9 0x19 +#define CH7024_IN_TIMING10 0x1A +#define CH7024_IN_TIMING11 0x1B +#define CH7024_ACIV 0x1C +#define CH7024_CLK_TREE 0x1D +#define CH7024_OUT_TIMING1 0x1E +#define CH7024_OUT_TIMING2 0x1F +#define CH7024_V_POS1 0x20 +#define CH7024_V_POS2 0x21 +#define CH7024_H_POS1 0x22 +#define CH7024_H_POS2 0x23 +#define CH7024_PCLK_A1 0x24 +#define CH7024_PCLK_A2 0x25 +#define CH7024_PCLK_A3 0x26 +#define CH7024_PCLK_A4 0x27 +#define CH7024_CLK_P1 0x28 +#define CH7024_CLK_P2 0x29 +#define CH7024_CLK_P3 0x2A +#define CH7024_CLK_N1 0x2B +#define CH7024_CLK_N2 0x2C +#define CH7024_CLK_N3 0x2D +#define CH7024_CLK_T 0x2E +#define CH7024_PLL1 0x2F +#define CH7024_PLL2 0x30 +#define CH7024_PLL3 0x31 +#define CH7024_SC_FREQ1 0x34 +#define CH7024_SC_FREQ2 0x35 +#define CH7024_SC_FREQ3 0x36 +#define CH7024_SC_FREQ4 0x37 +#define CH7024_DAC_TRIM 0x62 +#define CH7024_DATA_IO 0x63 +#define CH7024_ATT_DISP 0x7E + +/*! + * CH7024 register values + */ +/* video output formats */ +#define CH7024_VOS_NTSC_M 0x0 +#define CH7024_VOS_NTSC_J 0x1 +#define CH7024_VOS_NTSC_443 0x2 +#define CH7024_VOS_PAL_BDGHKI 0x3 +#define CH7024_VOS_PAL_M 0x4 +#define CH7024_VOS_PAL_N 0x5 +#define CH7024_VOS_PAL_NC 0x6 +#define CH7024_VOS_PAL_60 0x7 +/* crystal predefined */ +#define CH7024_XTAL_13MHZ 0x4 +#define CH7024_XTAL_26MHZ 0xB + +/* chip ID */ +#define CH7024_DEVICE_ID 0x45 + +/* clock source define */ +#define CLK_HIGH 0 +#define CLK_LOW 1 + +/* CH7024 presets structs */ +struct ch7024_clock { + u32 A; + u32 P; + u32 N; + u32 T; + u8 PLLN1; + u8 PLLN2; + u8 PLLN3; +}; + +struct ch7024_input_timing { + u32 HTI; + u32 VTI; + u32 HAI; + u32 VAI; + u32 HW; + u32 HO; + u32 VW; + u32 VO; + u32 VOS; +}; + +#define TVOUT_FMT_OFF 0 +#define TVOUT_FMT_NTSC 1 +#define TVOUT_FMT_PAL 2 + +static int enabled; /* enable power on or not */ +static int pm_status; /* status before suspend */ + +static struct i2c_client *ch7024_client; +static struct fb_info *ch7024_fbi; +static int ch7024_cur_mode; +static u32 detect_gpio; +static struct regulator *io_reg; +static struct regulator *core_reg; +static struct regulator *analog_reg; + +static void hp_detect_wq_handler(struct work_struct *); +DECLARE_DELAYED_WORK(ch7024_wq, hp_detect_wq_handler); + +static inline int ch7024_read_reg(u8 reg) +{ + return i2c_smbus_read_byte_data(ch7024_client, reg); +} + +static inline int ch7024_write_reg(u8 reg, u8 word) +{ + return i2c_smbus_write_byte_data(ch7024_client, reg, word); +} + +/** + * PAL B/D/G/H/K/I clock and timting structures + */ +static struct ch7024_clock ch7024_clk_pal = { + .A = 0x0, + .P = 0x36b00, + .N = 0x41eb00, + .T = 0x3f, + .PLLN1 = 0x0, + .PLLN2 = 0x1b, + .PLLN3 = 0x12, +}; + +static struct ch7024_input_timing ch7024_timing_pal = { + .HTI = 950, + .VTI = 560, + .HAI = 640, + .VAI = 480, + .HW = 60, + .HO = 250, + .VW = 40, + .VO = 40, + .VOS = CH7024_VOS_PAL_BDGHKI, +}; + +/** + * NTSC_M clock and timting structures + * TODO: change values to work well. + */ +static struct ch7024_clock ch7024_clk_ntsc = { + .A = 0x0, + .P = 0x2ac90, + .N = 0x36fc90, + .T = 0x3f, + .PLLN1 = 0x0, + .PLLN2 = 0x1b, + .PLLN3 = 0x12, +}; + +static struct ch7024_input_timing ch7024_timing_ntsc = { + .HTI = 801, + .VTI = 554, + .HAI = 640, + .VAI = 480, + .HW = 60, + .HO = 101, + .VW = 20, + .VO = 54, + .VOS = CH7024_VOS_NTSC_M, +}; + +static struct fb_videomode video_modes[] = { + { + /* NTSC TV output */ + "TV-NTSC", 60, 640, 480, 37594, + 0, 101, + 0, 54, + 60, 20, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* PAL TV output */ + "TV-PAL", 50, 640, 480, 37594, + 0, 250, + 0, 40, + 60, 40, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +/** + * ch7024_setup + * initial the CH7024 chipset by setting register + * @param: + * vos: output video format + * @return: + * 0 successful + * otherwise failed + */ +static int ch7024_setup(int vos) +{ + struct ch7024_input_timing *ch_timing; + struct ch7024_clock *ch_clk; +#ifdef DEBUG_CH7024 + int i, val; +#endif + + /* select output video format */ + if (vos == TVOUT_FMT_PAL) { + ch_timing = &ch7024_timing_pal; + ch_clk = &ch7024_clk_pal; + pr_debug("CH7024: change to PAL video\n"); + } else if (vos == TVOUT_FMT_NTSC) { + ch_timing = &ch7024_timing_ntsc; + ch_clk = &ch7024_clk_ntsc; + pr_debug("CH7024: change to NTSC video\n"); + } else { + + pr_debug("CH7024: no such video format.\n"); + return -EINVAL; + } + ch7024_write_reg(CH7024_RESET, 0x0); + ch7024_write_reg(CH7024_RESET, 0x3); + + ch7024_write_reg(CH7024_POWER, 0x0C); /* power on, disable DAC */ + ch7024_write_reg(CH7024_XTAL, CH7024_XTAL_26MHZ); + ch7024_write_reg(CH7024_SYNC, 0x0D); /* SLAVE mode, and TTL */ + ch7024_write_reg(CH7024_IDF1, 0x00); + ch7024_write_reg(CH7024_TVFILTER1, 0x00); /* set XCH=0 */ + ch7024_write_reg(CH7024_CLK_TREE, 0x9E); /* Invert input clk */ + + /* set input clock and divider */ + /* set PLL */ + ch7024_write_reg(CH7024_PLL1, ch_clk->PLLN1); + ch7024_write_reg(CH7024_PLL2, ch_clk->PLLN2); + ch7024_write_reg(CH7024_PLL3, ch_clk->PLLN3); + /* set A register */ + ch7024_write_reg(CH7024_PCLK_A1, (ch_clk->A >> 24) & 0xFF); + ch7024_write_reg(CH7024_PCLK_A2, (ch_clk->A >> 16) & 0xFF); + ch7024_write_reg(CH7024_PCLK_A3, (ch_clk->A >> 8) & 0xFF); + ch7024_write_reg(CH7024_PCLK_A4, ch_clk->A & 0xFF); + /* set P register */ + ch7024_write_reg(CH7024_CLK_P1, (ch_clk->P >> 16) & 0xFF); + ch7024_write_reg(CH7024_CLK_P2, (ch_clk->P >> 8) & 0xFF); + ch7024_write_reg(CH7024_CLK_P3, ch_clk->P & 0xFF); + /* set N register */ + ch7024_write_reg(CH7024_CLK_N1, (ch_clk->N >> 16) & 0xFF); + ch7024_write_reg(CH7024_CLK_N2, (ch_clk->N >> 8) & 0xFF); + ch7024_write_reg(CH7024_CLK_N3, ch_clk->N & 0xFF); + /* set T register */ + ch7024_write_reg(CH7024_CLK_T, ch_clk->T & 0xFF); + + /* set sub-carrier frequency generation method */ + ch7024_write_reg(CH7024_ACIV, 0x00); /* ACIV = 0, automatical SCF */ + /* TV out pattern and DAC switch */ + ch7024_write_reg(CH7024_OUT_FMT, (0x10 | ch_timing->VOS) & 0xFF); + + /* input settings */ + /* input format, RGB666 */ + ch7024_write_reg(CH7024_IDF2, 0x02); + /* HAI/HTI VAI */ + ch7024_write_reg(CH7024_IN_TIMING1, ((ch_timing->HTI >> 5) & 0x38) | + ((ch_timing->HAI >> 8) & 0x07)); + ch7024_write_reg(CH7024_IN_TIMING2, ch_timing->HAI & 0xFF); + ch7024_write_reg(CH7024_IN_TIMING8, ch_timing->VAI & 0xFF); + /* HTI VTI */ + ch7024_write_reg(CH7024_IN_TIMING3, ch_timing->HTI & 0xFF); + ch7024_write_reg(CH7024_IN_TIMING9, ch_timing->VTI & 0xFF); + /* HW/HO(h) VW */ + ch7024_write_reg(CH7024_IN_TIMING4, ((ch_timing->HW >> 5) & 0x18) | + ((ch_timing->HO >> 8) & 0x7)); + ch7024_write_reg(CH7024_IN_TIMING6, ch_timing->HW & 0xFF); + ch7024_write_reg(CH7024_IN_TIMING11, ch_timing->VW & 0x3F); + /* HO(l) VO/VAI/VTI */ + ch7024_write_reg(CH7024_IN_TIMING5, ch_timing->HO & 0xFF); + ch7024_write_reg(CH7024_IN_TIMING7, ((ch_timing->VO >> 4) & 0x30) | + ((ch_timing->VTI >> 6) & 0x0C) | + ((ch_timing->VAI >> 8) & 0x03)); + ch7024_write_reg(CH7024_IN_TIMING10, ch_timing->VO & 0xFF); + + /* adjust the brightness */ + ch7024_write_reg(CH7024_TVBRI, 0x90); + + ch7024_write_reg(CH7024_OUT_TIMING1, 0x4); + ch7024_write_reg(CH7024_OUT_TIMING2, 0xe0); + + if (vos == TVOUT_FMT_PAL) { + ch7024_write_reg(CH7024_V_POS1, 0x03); + ch7024_write_reg(CH7024_V_POS2, 0x7d); + } else { + ch7024_write_reg(CH7024_V_POS1, 0x02); + ch7024_write_reg(CH7024_V_POS2, 0x7b); + } + + ch7024_write_reg(CH7024_POWER, 0x00); + +#ifdef DEBUG_CH7024 + for (i = 0; i < CH7024_SC_FREQ4; i++) { + + val = ch7024_read_reg(i); + pr_debug("CH7024, reg[0x%x] = %x\n", i, val); + } +#endif + return 0; +} + +/** + * ch7024_enable + * Enable the ch7024 Power to begin TV encoder + */ +static int ch7024_enable(void) +{ + int en = enabled; + + if (!enabled) { + regulator_enable(core_reg); + regulator_enable(io_reg); + regulator_enable(analog_reg); + msleep(200); + enabled = 1; + ch7024_write_reg(CH7024_POWER, 0x00); + pr_debug("CH7024 power on.\n"); + } + return en; +} + +/** + * ch7024_disable + * Disable the ch7024 Power to stop TV encoder + */ +static void ch7024_disable(void) +{ + if (enabled) { + enabled = 0; + ch7024_write_reg(CH7024_POWER, 0x0D); + regulator_disable(analog_reg); + regulator_disable(io_reg); + regulator_disable(core_reg); + pr_debug("CH7024 power off.\n"); + } +} + +static int ch7024_detect(void) +{ + int en; + int detect = 0; + + if (gpio_get_value(detect_gpio) == 1) { + set_irq_type(ch7024_client->irq, IRQF_TRIGGER_FALLING); + + en = ch7024_enable(); + + ch7024_write_reg(CH7024_DAC_TRIM, 0xB4); + msleep(50); + detect = ch7024_read_reg(CH7024_ATT_DISP) & 0x3; + ch7024_write_reg(CH7024_DAC_TRIM, 0x34); + + if (!en) + ch7024_disable(); + } else { + set_irq_type(ch7024_client->irq, IRQF_TRIGGER_RISING); + } + dev_dbg(&ch7024_client->dev, "detect = %d\n", detect); + return detect; +} + +static irqreturn_t hp_detect_handler(int irq, void *data) +{ + disable_irq(irq); + schedule_delayed_work(&ch7024_wq, 50); + + return IRQ_HANDLED; +} + +static void hp_detect_wq_handler(struct work_struct *work) +{ + int detect; + struct mxc_hw_event event = { HWE_PHONEJACK_PLUG, 0 }; + + detect = ch7024_detect(); + + enable_irq(ch7024_client->irq); + + sysfs_notify(&ch7024_client->dev.kobj, NULL, "headphone"); + + /* send hw event by netlink */ + event.args = detect; + hw_event_send(1, &event); +} + +int ch7024_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + struct fb_info *fbi = event->info; + + switch (val) { + case FB_EVENT_FB_REGISTERED: + if ((ch7024_fbi != NULL) || strcmp(fbi->fix.id, "DISP3 BG")) + break; + + ch7024_fbi = fbi; + fb_add_videomode(&video_modes[0], &ch7024_fbi->modelist); + fb_add_videomode(&video_modes[1], &ch7024_fbi->modelist); + break; + case FB_EVENT_MODE_CHANGE: + if (ch7024_fbi != fbi) + break; + + if (!fbi->mode) { + ch7024_disable(); + ch7024_cur_mode = TVOUT_FMT_OFF; + return 0; + } + + if (fb_mode_is_equal(fbi->mode, &video_modes[0])) { + ch7024_cur_mode = TVOUT_FMT_NTSC; + ch7024_enable(); + ch7024_setup(TVOUT_FMT_NTSC); + } else if (fb_mode_is_equal(fbi->mode, &video_modes[1])) { + ch7024_cur_mode = TVOUT_FMT_PAL; + ch7024_enable(); + ch7024_setup(TVOUT_FMT_PAL); + } else { + ch7024_disable(); + ch7024_cur_mode = TVOUT_FMT_OFF; + return 0; + } + break; + case FB_EVENT_BLANK: + if ((ch7024_fbi != fbi) || (ch7024_cur_mode == TVOUT_FMT_OFF)) + return 0; + + if (*((int *)event->data) == FB_BLANK_UNBLANK) { + ch7024_enable(); + ch7024_setup(ch7024_cur_mode); + } else { + ch7024_disable(); + } + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = ch7024_fb_event, +}; + +static ssize_t show_headphone(struct device_driver *dev, char *buf) +{ + int detect; + + detect = ch7024_detect(); + + if (detect == 0) { + strcpy(buf, "none\n"); + } else if (detect == 1) { + strcpy(buf, "cvbs\n"); + } else { + strcpy(buf, "headset\n"); + } + + return strlen(buf); +} + +DRIVER_ATTR(headphone, 0644, show_headphone, NULL); + +static ssize_t show_brightness(struct device_driver *dev, char *buf) +{ + u32 reg; + reg = ch7024_read_reg(CH7024_TVBRI); + return snprintf(buf, PAGE_SIZE, "%u", reg); +} + +static ssize_t store_brightness(struct device_driver *dev, const char *buf, + size_t count) +{ + char *endp; + int brightness = simple_strtoul(buf, &endp, 0); + size_t size = endp - buf; + + if (*endp && isspace(*endp)) + size++; + if (size != count) + return -EINVAL; + + if (brightness > 255) + brightness = 255; + + ch7024_write_reg(CH7024_TVBRI, brightness); + + return count; +} + +DRIVER_ATTR(brightness, 0644, show_brightness, store_brightness); + +static ssize_t show_contrast(struct device_driver *dev, char *buf) +{ + u32 reg; + reg = ch7024_read_reg(CH7024_TVCTA); + + reg *= 2; /* Scale to 0 - 255 */ + + return snprintf(buf, PAGE_SIZE, "%u", reg); +} + +static ssize_t store_contrast(struct device_driver *dev, const char *buf, + size_t count) +{ + char *endp; + int contrast = simple_strtoul(buf, &endp, 0); + size_t size = endp - buf; + + if (*endp && isspace(*endp)) + size++; + if (size != count) + return -EINVAL; + + contrast /= 2; + if (contrast > 127) + contrast = 127; + + ch7024_write_reg(CH7024_TVCTA, contrast); + + return count; +} + +DRIVER_ATTR(contrast, 0644, show_contrast, store_contrast); + +static ssize_t show_hue(struct device_driver *dev, char *buf) +{ + u32 reg; + reg = ch7024_read_reg(CH7024_TVHUE); + + reg *= 2; /* Scale to 0 - 255 */ + + return snprintf(buf, PAGE_SIZE, "%u", reg); +} + +static ssize_t store_hue(struct device_driver *dev, const char *buf, + size_t count) +{ + char *endp; + int hue = simple_strtoul(buf, &endp, 0); + size_t size = endp - buf; + + if (*endp && isspace(*endp)) + size++; + if (size != count) + return -EINVAL; + + hue /= 2; + if (hue > 127) + hue = 127; + + ch7024_write_reg(CH7024_TVHUE, hue); + + return count; +} + +DRIVER_ATTR(hue, 0644, show_hue, store_hue); + +static ssize_t show_saturation(struct device_driver *dev, char *buf) +{ + u32 reg; + reg = ch7024_read_reg(CH7024_TVSAT); + + reg *= 2; /* Scale to 0 - 255 */ + + return snprintf(buf, PAGE_SIZE, "%u", reg); +} + +static ssize_t store_saturation(struct device_driver *dev, const char *buf, + size_t count) +{ + char *endp; + int saturation = simple_strtoul(buf, &endp, 0); + size_t size = endp - buf; + + if (*endp && isspace(*endp)) + size++; + if (size != count) + return -EINVAL; + + saturation /= 2; + if (saturation > 127) + saturation = 127; + + ch7024_write_reg(CH7024_TVSAT, saturation); + + return count; +} + +DRIVER_ATTR(saturation, 0644, show_saturation, store_saturation); + +static ssize_t show_sharpness(struct device_driver *dev, char *buf) +{ + u32 reg; + reg = ch7024_read_reg(CH7024_TVSHARP); + + reg *= 32; /* Scale to 0 - 255 */ + + return snprintf(buf, PAGE_SIZE, "%u", reg); +} + +static ssize_t store_sharpness(struct device_driver *dev, const char *buf, + size_t count) +{ + char *endp; + int sharpness = simple_strtoul(buf, &endp, 0); + size_t size = endp - buf; + + if (*endp && isspace(*endp)) + size++; + if (size != count) + return -EINVAL; + + sharpness /= 32; /* Scale to 0 - 7 */ + if (sharpness > 7) + sharpness = 7; + + ch7024_write_reg(CH7024_TVSHARP, sharpness); + + return count; +} + +DRIVER_ATTR(sharpness, 0644, show_sharpness, store_sharpness); + +static int ch7024_probe(struct i2c_client *client, const struct i2c_device_id *dev_id) +{ + int ret, i; + u32 id; + u32 irqtype; + struct mxc_tvout_platform_data *plat_data = client->dev.platform_data; + + ch7024_client = client; + + io_reg = regulator_get(&client->dev, plat_data->io_reg); + core_reg = regulator_get(&client->dev, plat_data->core_reg); + analog_reg = regulator_get(&client->dev, plat_data->analog_reg); + + regulator_enable(io_reg); + regulator_enable(core_reg); + regulator_enable(analog_reg); + msleep(200); + + id = ch7024_read_reg(CH7024_DEVID); + + regulator_disable(core_reg); + regulator_disable(io_reg); + regulator_disable(analog_reg); + + if (id < 0 || id != CH7024_DEVICE_ID) { + printk(KERN_ERR + "ch7024: TV encoder not present: id = %x\n", id); + return -ENODEV; + } + printk(KERN_ERR "ch7024: TV encoder present: id = %x\n", id); + + detect_gpio = plat_data->detect_line; + + if (client->irq > 0) { + if (ch7024_detect() == 0) + irqtype = IRQF_TRIGGER_RISING; + else + irqtype = IRQF_TRIGGER_FALLING; + + ret = request_irq(client->irq, hp_detect_handler, irqtype, + client->name, client); + if (ret < 0) + goto err0; + + ret = driver_create_file(&client->driver->driver, + &driver_attr_headphone); + if (ret < 0) + goto err1; + } + + ret = driver_create_file(&client->driver->driver, + &driver_attr_brightness); + if (ret) + goto err2; + + ret = driver_create_file(&client->driver->driver, + &driver_attr_contrast); + if (ret) + goto err3; + ret = driver_create_file(&client->driver->driver, &driver_attr_hue); + if (ret) + goto err4; + ret = driver_create_file(&client->driver->driver, + &driver_attr_saturation); + if (ret) + goto err5; + ret = driver_create_file(&client->driver->driver, + &driver_attr_sharpness); + if (ret) + goto err6; + + for (i = 0; i < num_registered_fb; i++) { + if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0) { + ch7024_fbi = registered_fb[i]; + break; + } + } + if (ch7024_fbi != NULL) { + fb_add_videomode(&video_modes[0], &ch7024_fbi->modelist); + fb_add_videomode(&video_modes[1], &ch7024_fbi->modelist); + } + fb_register_client(&nb); + + return 0; + err6: + driver_remove_file(&client->driver->driver, &driver_attr_saturation); + err5: + driver_remove_file(&client->driver->driver, &driver_attr_hue); + err4: + driver_remove_file(&client->driver->driver, &driver_attr_contrast); + err3: + driver_remove_file(&client->driver->driver, &driver_attr_brightness); + err2: + driver_remove_file(&client->driver->driver, &driver_attr_headphone); + err1: + free_irq(client->irq, client); + err0: + return ret; +} + +static int ch7024_remove(struct i2c_client *client) +{ + free_irq(client->irq, client); + + regulator_put(io_reg); + regulator_put(core_reg); + regulator_put(analog_reg); + + driver_remove_file(&client->driver->driver, &driver_attr_headphone); + driver_remove_file(&client->driver->driver, &driver_attr_brightness); + driver_remove_file(&client->driver->driver, &driver_attr_contrast); + driver_remove_file(&client->driver->driver, &driver_attr_hue); + driver_remove_file(&client->driver->driver, &driver_attr_saturation); + driver_remove_file(&client->driver->driver, &driver_attr_sharpness); + + fb_unregister_client(&nb); + + ch7024_client = 0; + + return 0; +} + +#ifdef CONFIG_PM +/*! + * PM suspend/resume routing + */ +static int ch7024_suspend(struct i2c_client *client, pm_message_t state) +{ + pr_debug("Ch7024 suspend routing..\n"); + if (enabled) { + ch7024_disable(); + pm_status = 1; + } else { + pm_status = 0; + } + return 0; +} + +static int ch7024_resume(struct i2c_client *client) +{ + pr_debug("Ch7024 resume routing..\n"); + if (pm_status) { + ch7024_enable(); + ch7024_setup(ch7024_cur_mode); + } + return 0; +} +#else +#define ch7024_suspend NULL +#define ch7024_resume NULL +#endif + +static const struct i2c_device_id ch7024_id[] = { + { "ch7024", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, ch7024_id); + +static struct i2c_driver ch7024_driver = { + .driver = { + .name = "ch7024", + }, + .probe = ch7024_probe, + .remove = ch7024_remove, + .suspend = ch7024_suspend, + .resume = ch7024_resume, + .id_table = ch7024_id, +}; + +static int __init ch7024_init(void) +{ + return i2c_add_driver(&ch7024_driver); +} + +static void __exit ch7024_exit(void) +{ + i2c_del_driver(&ch7024_driver); +} + +module_init(ch7024_init); +module_exit(ch7024_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("CH7024 TV encoder driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/elcdif_regs.h b/drivers/video/mxc/elcdif_regs.h new file mode 100644 index 000000000000..2eceba5864e0 --- /dev/null +++ b/drivers/video/mxc/elcdif_regs.h @@ -0,0 +1,678 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +/* + * Based on arch/arm/mach-mx28/include/mach/regs-lcdif.h. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#ifndef __ELCDIF_REGS_INCLUDED_ +#define __ELCDIF_REGS_INCLUDED_ + +#define HW_ELCDIF_CTRL (0x00000000) +#define HW_ELCDIF_CTRL_SET (0x00000004) +#define HW_ELCDIF_CTRL_CLR (0x00000008) +#define HW_ELCDIF_CTRL_TOG (0x0000000c) + +#define BM_ELCDIF_CTRL_SFTRST 0x80000000 +#define BM_ELCDIF_CTRL_CLKGATE 0x40000000 +#define BM_ELCDIF_CTRL_YCBCR422_INPUT 0x20000000 +#define BM_ELCDIF_CTRL_READ_WRITEB 0x10000000 +#define BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 +#define BM_ELCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 +#define BV_ELCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 +#define BV_ELCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 +#define BP_ELCDIF_CTRL_SHIFT_NUM_BITS 21 +#define BM_ELCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 +#define BF_ELCDIF_CTRL_SHIFT_NUM_BITS(v) \ + (((v) << 21) & BM_ELCDIF_CTRL_SHIFT_NUM_BITS) +#define BM_ELCDIF_CTRL_DVI_MODE 0x00100000 +#define BM_ELCDIF_CTRL_BYPASS_COUNT 0x00080000 +#define BM_ELCDIF_CTRL_VSYNC_MODE 0x00040000 +#define BM_ELCDIF_CTRL_DOTCLK_MODE 0x00020000 +#define BM_ELCDIF_CTRL_DATA_SELECT 0x00010000 +#define BV_ELCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 +#define BV_ELCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 +#define BP_ELCDIF_CTRL_INPUT_DATA_SWIZZLE 14 +#define BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 +#define BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \ + (((v) << 14) & BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE) +#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_ELCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_ELCDIF_CTRL_CSC_DATA_SWIZZLE 12 +#define BM_ELCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000 +#define BF_ELCDIF_CTRL_CSC_DATA_SWIZZLE(v) \ + (((v) << 12) & BM_ELCDIF_CTRL_CSC_DATA_SWIZZLE) +#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_ELCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_ELCDIF_CTRL_LCD_DATABUS_WIDTH 10 +#define BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 +#define BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(v) \ + (((v) << 10) & BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH) +#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0 +#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1 +#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2 +#define BV_ELCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3 +#define BP_ELCDIF_CTRL_WORD_LENGTH 8 +#define BM_ELCDIF_CTRL_WORD_LENGTH 0x00000300 +#define BF_ELCDIF_CTRL_WORD_LENGTH(v) \ + (((v) << 8) & BM_ELCDIF_CTRL_WORD_LENGTH) +#define BV_ELCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 +#define BV_ELCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 +#define BV_ELCDIF_CTRL_WORD_LENGTH__18_BIT 0x2 +#define BV_ELCDIF_CTRL_WORD_LENGTH__24_BIT 0x3 +#define BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 +#define BM_ELCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040 +#define BM_ELCDIF_CTRL_ELCDIF_MASTER 0x00000020 +#define BM_ELCDIF_CTRL_RSRVD0 0x00000010 +#define BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008 +#define BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004 +#define BV_ELCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0 +#define BV_ELCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1 +#define BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002 +#define BV_ELCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0 +#define BV_ELCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1 +#define BM_ELCDIF_CTRL_RUN 0x00000001 + +#define HW_ELCDIF_CTRL1 (0x00000010) +#define HW_ELCDIF_CTRL1_SET (0x00000014) +#define HW_ELCDIF_CTRL1_CLR (0x00000018) +#define HW_ELCDIF_CTRL1_TOG (0x0000001c) + +#define BP_ELCDIF_CTRL1_RSRVD1 28 +#define BM_ELCDIF_CTRL1_RSRVD1 0xF0000000 +#define BF_ELCDIF_CTRL1_RSRVD1(v) \ + (((v) << 28) & BM_ELCDIF_CTRL1_RSRVD1) +#define BM_ELCDIF_CTRL1_COMBINE_MPU_WR_STRB 0x08000000 +#define BM_ELCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000 +#define BM_ELCDIF_CTRL1_BM_ERROR_IRQ 0x02000000 +#define BV_ELCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0 +#define BV_ELCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1 +#define BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 +#define BM_ELCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 +#define BM_ELCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000 +#define BM_ELCDIF_CTRL1_FIFO_CLEAR 0x00200000 +#define BM_ELCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000 +#define BP_ELCDIF_CTRL1_BYTE_PACKING_FORMAT 16 +#define BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 +#define BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \ + (((v) << 16) & BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT) +#define BM_ELCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000 +#define BM_ELCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000 +#define BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000 +#define BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 +#define BM_ELCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 +#define BV_ELCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_ELCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 +#define BM_ELCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 +#define BV_ELCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_ELCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 +#define BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 +#define BV_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 +#define BV_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 +#define BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 +#define BV_ELCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 +#define BV_ELCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 +#define BP_ELCDIF_CTRL1_RSRVD0 3 +#define BM_ELCDIF_CTRL1_RSRVD0 0x000000F8 +#define BF_ELCDIF_CTRL1_RSRVD0(v) \ + (((v) << 3) & BM_ELCDIF_CTRL1_RSRVD0) +#define BM_ELCDIF_CTRL1_BUSY_ENABLE 0x00000004 +#define BV_ELCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 +#define BV_ELCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 +#define BM_ELCDIF_CTRL1_MODE86 0x00000002 +#define BV_ELCDIF_CTRL1_MODE86__8080_MODE 0x0 +#define BV_ELCDIF_CTRL1_MODE86__6800_MODE 0x1 +#define BM_ELCDIF_CTRL1_RESET 0x00000001 +#define BV_ELCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 +#define BV_ELCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 + +#define HW_ELCDIF_CTRL2 (0x00000020) +#define HW_ELCDIF_CTRL2_SET (0x00000024) +#define HW_ELCDIF_CTRL2_CLR (0x00000028) +#define HW_ELCDIF_CTRL2_TOG (0x0000002c) + +#define BP_ELCDIF_CTRL2_RSRVD5 24 +#define BM_ELCDIF_CTRL2_RSRVD5 0xFF000000 +#define BF_ELCDIF_CTRL2_RSRVD5(v) \ + (((v) << 24) & BM_ELCDIF_CTRL2_RSRVD5) +#define BP_ELCDIF_CTRL2_OUTSTANDING_REQS 21 +#define BM_ELCDIF_CTRL2_OUTSTANDING_REQS 0x00E00000 +#define BF_ELCDIF_CTRL2_OUTSTANDING_REQS(v) \ + (((v) << 21) & BM_ELCDIF_CTRL2_OUTSTANDING_REQS) +#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_1 0x0 +#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_2 0x1 +#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_4 0x2 +#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8 0x3 +#define BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_16 0x4 +#define BM_ELCDIF_CTRL2_BURST_LEN_8 0x00100000 +#define BM_ELCDIF_CTRL2_RSRVD4 0x00080000 +#define BP_ELCDIF_CTRL2_ODD_LINE_PATTERN 16 +#define BM_ELCDIF_CTRL2_ODD_LINE_PATTERN 0x00070000 +#define BF_ELCDIF_CTRL2_ODD_LINE_PATTERN(v) \ + (((v) << 16) & BM_ELCDIF_CTRL2_ODD_LINE_PATTERN) +#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__RGB 0x0 +#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__RBG 0x1 +#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__GBR 0x2 +#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__GRB 0x3 +#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__BRG 0x4 +#define BV_ELCDIF_CTRL2_ODD_LINE_PATTERN__BGR 0x5 +#define BM_ELCDIF_CTRL2_RSRVD3 0x00008000 +#define BP_ELCDIF_CTRL2_EVEN_LINE_PATTERN 12 +#define BM_ELCDIF_CTRL2_EVEN_LINE_PATTERN 0x00007000 +#define BF_ELCDIF_CTRL2_EVEN_LINE_PATTERN(v) \ + (((v) << 12) & BM_ELCDIF_CTRL2_EVEN_LINE_PATTERN) +#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__RGB 0x0 +#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__RBG 0x1 +#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__GBR 0x2 +#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__GRB 0x3 +#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__BRG 0x4 +#define BV_ELCDIF_CTRL2_EVEN_LINE_PATTERN__BGR 0x5 +#define BM_ELCDIF_CTRL2_RSRVD2 0x00000800 +#define BM_ELCDIF_CTRL2_READ_PACK_DIR 0x00000400 +#define BM_ELCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT 0x00000200 +#define BM_ELCDIF_CTRL2_READ_MODE_6_BIT_INPUT 0x00000100 +#define BM_ELCDIF_CTRL2_RSRVD1 0x00000080 +#define BP_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 4 +#define BM_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS 0x00000070 +#define BF_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(v) \ + (((v) << 4) & BM_ELCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS) +#define BP_ELCDIF_CTRL2_INITIAL_DUMMY_READ 1 +#define BM_ELCDIF_CTRL2_INITIAL_DUMMY_READ 0x0000000E +#define BF_ELCDIF_CTRL2_INITIAL_DUMMY_READ(v) \ + (((v) << 1) & BM_ELCDIF_CTRL2_INITIAL_DUMMY_READ) +#define BM_ELCDIF_CTRL2_RSRVD0 0x00000001 + +#define HW_ELCDIF_TRANSFER_COUNT (0x00000030) + +#define BP_ELCDIF_TRANSFER_COUNT_V_COUNT 16 +#define BM_ELCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 +#define BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v) \ + (((v) << 16) & BM_ELCDIF_TRANSFER_COUNT_V_COUNT) +#define BP_ELCDIF_TRANSFER_COUNT_H_COUNT 0 +#define BM_ELCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF +#define BF_ELCDIF_TRANSFER_COUNT_H_COUNT(v) \ + (((v) << 0) & BM_ELCDIF_TRANSFER_COUNT_H_COUNT) + +#define HW_ELCDIF_CUR_BUF (0x00000040) + +#define BP_ELCDIF_CUR_BUF_ADDR 0 +#define BM_ELCDIF_CUR_BUF_ADDR 0xFFFFFFFF +#define BF_ELCDIF_CUR_BUF_ADDR(v) (v) + +#define HW_ELCDIF_NEXT_BUF (0x00000050) + +#define BP_ELCDIF_NEXT_BUF_ADDR 0 +#define BM_ELCDIF_NEXT_BUF_ADDR 0xFFFFFFFF +#define BF_ELCDIF_NEXT_BUF_ADDR(v) (v) + +#define HW_ELCDIF_TIMING (0x00000060) + +#define BP_ELCDIF_TIMING_CMD_HOLD 24 +#define BM_ELCDIF_TIMING_CMD_HOLD 0xFF000000 +#define BF_ELCDIF_TIMING_CMD_HOLD(v) \ + (((v) << 24) & BM_ELCDIF_TIMING_CMD_HOLD) +#define BP_ELCDIF_TIMING_CMD_SETUP 16 +#define BM_ELCDIF_TIMING_CMD_SETUP 0x00FF0000 +#define BF_ELCDIF_TIMING_CMD_SETUP(v) \ + (((v) << 16) & BM_ELCDIF_TIMING_CMD_SETUP) +#define BP_ELCDIF_TIMING_DATA_HOLD 8 +#define BM_ELCDIF_TIMING_DATA_HOLD 0x0000FF00 +#define BF_ELCDIF_TIMING_DATA_HOLD(v) \ + (((v) << 8) & BM_ELCDIF_TIMING_DATA_HOLD) +#define BP_ELCDIF_TIMING_DATA_SETUP 0 +#define BM_ELCDIF_TIMING_DATA_SETUP 0x000000FF +#define BF_ELCDIF_TIMING_DATA_SETUP(v) \ + (((v) << 0) & BM_ELCDIF_TIMING_DATA_SETUP) + +#define HW_ELCDIF_VDCTRL0 (0x00000070) +#define HW_ELCDIF_VDCTRL0_SET (0x00000074) +#define HW_ELCDIF_VDCTRL0_CLR (0x00000078) +#define HW_ELCDIF_VDCTRL0_TOG (0x0000007c) + +#define BP_ELCDIF_VDCTRL0_RSRVD2 30 +#define BM_ELCDIF_VDCTRL0_RSRVD2 0xC0000000 +#define BF_ELCDIF_VDCTRL0_RSRVD2(v) \ + (((v) << 30) & BM_ELCDIF_VDCTRL0_RSRVD2) +#define BM_ELCDIF_VDCTRL0_VSYNC_OEB 0x20000000 +#define BV_ELCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 +#define BV_ELCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 +#define BM_ELCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 +#define BM_ELCDIF_VDCTRL0_VSYNC_POL 0x08000000 +#define BM_ELCDIF_VDCTRL0_HSYNC_POL 0x04000000 +#define BM_ELCDIF_VDCTRL0_DOTCLK_POL 0x02000000 +#define BM_ELCDIF_VDCTRL0_ENABLE_POL 0x01000000 +#define BP_ELCDIF_VDCTRL0_RSRVD1 22 +#define BM_ELCDIF_VDCTRL0_RSRVD1 0x00C00000 +#define BF_ELCDIF_VDCTRL0_RSRVD1(v) \ + (((v) << 22) & BM_ELCDIF_VDCTRL0_RSRVD1) +#define BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 +#define BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 +#define BM_ELCDIF_VDCTRL0_HALF_LINE 0x00080000 +#define BM_ELCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000 +#define BP_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 +#define BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF +#define BF_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \ + (((v) << 0) & BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH) + +#define HW_ELCDIF_VDCTRL1 (0x00000080) + +#define BP_ELCDIF_VDCTRL1_VSYNC_PERIOD 0 +#define BM_ELCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF +#define BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v) (v) + +#define HW_ELCDIF_VDCTRL2 (0x00000090) + +#define BP_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 18 +#define BM_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFFFC0000 +#define BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \ + (((v) << 18) & BM_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH) +#define BP_ELCDIF_VDCTRL2_HSYNC_PERIOD 0 +#define BM_ELCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF +#define BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(v) \ + (((v) << 0) & BM_ELCDIF_VDCTRL2_HSYNC_PERIOD) + +#define HW_ELCDIF_VDCTRL3 (0x000000a0) + +#define BP_ELCDIF_VDCTRL3_RSRVD0 30 +#define BM_ELCDIF_VDCTRL3_RSRVD0 0xC0000000 +#define BF_ELCDIF_VDCTRL3_RSRVD0(v) \ + (((v) << 30) & BM_ELCDIF_VDCTRL3_RSRVD0) +#define BM_ELCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000 +#define BM_ELCDIF_VDCTRL3_VSYNC_ONLY 0x10000000 +#define BP_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 +#define BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 +#define BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \ + (((v) << 16) & BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT) +#define BP_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 +#define BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF +#define BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \ + (((v) << 0) & BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT) + +#define HW_ELCDIF_VDCTRL4 (0x000000b0) + +#define BP_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL 29 +#define BM_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL 0xE0000000 +#define BF_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL(v) \ + (((v) << 29) & BM_ELCDIF_VDCTRL4_DOTCLK_DLY_SEL) +#define BP_ELCDIF_VDCTRL4_RSRVD0 19 +#define BM_ELCDIF_VDCTRL4_RSRVD0 0x1FF80000 +#define BF_ELCDIF_VDCTRL4_RSRVD0(v) \ + (((v) << 19) & BM_ELCDIF_VDCTRL4_RSRVD0) +#define BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 +#define BP_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 +#define BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF +#define BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \ + (((v) << 0) & BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT) + +#define HW_ELCDIF_DVICTRL0 (0x000000c0) + +#define BP_ELCDIF_DVICTRL0_RSRVD1 28 +#define BM_ELCDIF_DVICTRL0_RSRVD1 0xF0000000 +#define BF_ELCDIF_DVICTRL0_RSRVD1(v) \ + (((v) << 28) & BM_ELCDIF_DVICTRL0_RSRVD1) +#define BP_ELCDIF_DVICTRL0_H_ACTIVE_CNT 16 +#define BM_ELCDIF_DVICTRL0_H_ACTIVE_CNT 0x0FFF0000 +#define BF_ELCDIF_DVICTRL0_H_ACTIVE_CNT(v) \ + (((v) << 16) & BM_ELCDIF_DVICTRL0_H_ACTIVE_CNT) +#define BP_ELCDIF_DVICTRL0_RSRVD0 12 +#define BM_ELCDIF_DVICTRL0_RSRVD0 0x0000F000 +#define BF_ELCDIF_DVICTRL0_RSRVD0(v) \ + (((v) << 12) & BM_ELCDIF_DVICTRL0_RSRVD0) +#define BP_ELCDIF_DVICTRL0_H_BLANKING_CNT 0 +#define BM_ELCDIF_DVICTRL0_H_BLANKING_CNT 0x00000FFF +#define BF_ELCDIF_DVICTRL0_H_BLANKING_CNT(v) \ + (((v) << 0) & BM_ELCDIF_DVICTRL0_H_BLANKING_CNT) + +#define HW_ELCDIF_DVICTRL1 (0x000000d0) + +#define BP_ELCDIF_DVICTRL1_RSRVD0 30 +#define BM_ELCDIF_DVICTRL1_RSRVD0 0xC0000000 +#define BF_ELCDIF_DVICTRL1_RSRVD0(v) \ + (((v) << 30) & BM_ELCDIF_DVICTRL1_RSRVD0) +#define BP_ELCDIF_DVICTRL1_F1_START_LINE 20 +#define BM_ELCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 +#define BF_ELCDIF_DVICTRL1_F1_START_LINE(v) \ + (((v) << 20) & BM_ELCDIF_DVICTRL1_F1_START_LINE) +#define BP_ELCDIF_DVICTRL1_F1_END_LINE 10 +#define BM_ELCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 +#define BF_ELCDIF_DVICTRL1_F1_END_LINE(v) \ + (((v) << 10) & BM_ELCDIF_DVICTRL1_F1_END_LINE) +#define BP_ELCDIF_DVICTRL1_F2_START_LINE 0 +#define BM_ELCDIF_DVICTRL1_F2_START_LINE 0x000003FF +#define BF_ELCDIF_DVICTRL1_F2_START_LINE(v) \ + (((v) << 0) & BM_ELCDIF_DVICTRL1_F2_START_LINE) + +#define HW_ELCDIF_DVICTRL2 (0x000000e0) + +#define BP_ELCDIF_DVICTRL2_RSRVD0 30 +#define BM_ELCDIF_DVICTRL2_RSRVD0 0xC0000000 +#define BF_ELCDIF_DVICTRL2_RSRVD0(v) \ + (((v) << 30) & BM_ELCDIF_DVICTRL2_RSRVD0) +#define BP_ELCDIF_DVICTRL2_F2_END_LINE 20 +#define BM_ELCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 +#define BF_ELCDIF_DVICTRL2_F2_END_LINE(v) \ + (((v) << 20) & BM_ELCDIF_DVICTRL2_F2_END_LINE) +#define BP_ELCDIF_DVICTRL2_V1_BLANK_START_LINE 10 +#define BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 +#define BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \ + (((v) << 10) & BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE) +#define BP_ELCDIF_DVICTRL2_V1_BLANK_END_LINE 0 +#define BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF +#define BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \ + (((v) << 0) & BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE) + +#define HW_ELCDIF_DVICTRL3 (0x000000f0) + +#define BP_ELCDIF_DVICTRL3_RSRVD0 30 +#define BM_ELCDIF_DVICTRL3_RSRVD0 0xC0000000 +#define BF_ELCDIF_DVICTRL3_RSRVD0(v) \ + (((v) << 30) & BM_ELCDIF_DVICTRL3_RSRVD0) +#define BP_ELCDIF_DVICTRL3_V2_BLANK_START_LINE 20 +#define BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE 0x3FF00000 +#define BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \ + (((v) << 20) & BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE) +#define BP_ELCDIF_DVICTRL3_V2_BLANK_END_LINE 10 +#define BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000FFC00 +#define BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \ + (((v) << 10) & BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE) +#define BP_ELCDIF_DVICTRL3_V_LINES_CNT 0 +#define BM_ELCDIF_DVICTRL3_V_LINES_CNT 0x000003FF +#define BF_ELCDIF_DVICTRL3_V_LINES_CNT(v) \ + (((v) << 0) & BM_ELCDIF_DVICTRL3_V_LINES_CNT) + +#define HW_ELCDIF_DVICTRL4 (0x00000100) + +#define BP_ELCDIF_DVICTRL4_Y_FILL_VALUE 24 +#define BM_ELCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 +#define BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(v) \ + (((v) << 24) & BM_ELCDIF_DVICTRL4_Y_FILL_VALUE) +#define BP_ELCDIF_DVICTRL4_CB_FILL_VALUE 16 +#define BM_ELCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 +#define BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(v) \ + (((v) << 16) & BM_ELCDIF_DVICTRL4_CB_FILL_VALUE) +#define BP_ELCDIF_DVICTRL4_CR_FILL_VALUE 8 +#define BM_ELCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 +#define BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(v) \ + (((v) << 8) & BM_ELCDIF_DVICTRL4_CR_FILL_VALUE) +#define BP_ELCDIF_DVICTRL4_H_FILL_CNT 0 +#define BM_ELCDIF_DVICTRL4_H_FILL_CNT 0x000000FF +#define BF_ELCDIF_DVICTRL4_H_FILL_CNT(v) \ + (((v) << 0) & BM_ELCDIF_DVICTRL4_H_FILL_CNT) + +#define HW_ELCDIF_CSC_COEFF0 (0x00000110) + +#define BP_ELCDIF_CSC_COEFF0_RSRVD1 26 +#define BM_ELCDIF_CSC_COEFF0_RSRVD1 0xFC000000 +#define BF_ELCDIF_CSC_COEFF0_RSRVD1(v) \ + (((v) << 26) & BM_ELCDIF_CSC_COEFF0_RSRVD1) +#define BP_ELCDIF_CSC_COEFF0_C0 16 +#define BM_ELCDIF_CSC_COEFF0_C0 0x03FF0000 +#define BF_ELCDIF_CSC_COEFF0_C0(v) \ + (((v) << 16) & BM_ELCDIF_CSC_COEFF0_C0) +#define BP_ELCDIF_CSC_COEFF0_RSRVD0 2 +#define BM_ELCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC +#define BF_ELCDIF_CSC_COEFF0_RSRVD0(v) \ + (((v) << 2) & BM_ELCDIF_CSC_COEFF0_RSRVD0) +#define BP_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 +#define BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 +#define BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \ + (((v) << 0) & BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER) +#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0 +#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1 +#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2 +#define BV_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3 + +#define HW_ELCDIF_CSC_COEFF1 (0x00000120) + +#define BP_ELCDIF_CSC_COEFF1_RSRVD1 26 +#define BM_ELCDIF_CSC_COEFF1_RSRVD1 0xFC000000 +#define BF_ELCDIF_CSC_COEFF1_RSRVD1(v) \ + (((v) << 26) & BM_ELCDIF_CSC_COEFF1_RSRVD1) +#define BP_ELCDIF_CSC_COEFF1_C2 16 +#define BM_ELCDIF_CSC_COEFF1_C2 0x03FF0000 +#define BF_ELCDIF_CSC_COEFF1_C2(v) \ + (((v) << 16) & BM_ELCDIF_CSC_COEFF1_C2) +#define BP_ELCDIF_CSC_COEFF1_RSRVD0 10 +#define BM_ELCDIF_CSC_COEFF1_RSRVD0 0x0000FC00 +#define BF_ELCDIF_CSC_COEFF1_RSRVD0(v) \ + (((v) << 10) & BM_ELCDIF_CSC_COEFF1_RSRVD0) +#define BP_ELCDIF_CSC_COEFF1_C1 0 +#define BM_ELCDIF_CSC_COEFF1_C1 0x000003FF +#define BF_ELCDIF_CSC_COEFF1_C1(v) \ + (((v) << 0) & BM_ELCDIF_CSC_COEFF1_C1) + +#define HW_ELCDIF_CSC_COEFF2 (0x00000130) + +#define BP_ELCDIF_CSC_COEFF2_RSRVD1 26 +#define BM_ELCDIF_CSC_COEFF2_RSRVD1 0xFC000000 +#define BF_ELCDIF_CSC_COEFF2_RSRVD1(v) \ + (((v) << 26) & BM_ELCDIF_CSC_COEFF2_RSRVD1) +#define BP_ELCDIF_CSC_COEFF2_C4 16 +#define BM_ELCDIF_CSC_COEFF2_C4 0x03FF0000 +#define BF_ELCDIF_CSC_COEFF2_C4(v) \ + (((v) << 16) & BM_ELCDIF_CSC_COEFF2_C4) +#define BP_ELCDIF_CSC_COEFF2_RSRVD0 10 +#define BM_ELCDIF_CSC_COEFF2_RSRVD0 0x0000FC00 +#define BF_ELCDIF_CSC_COEFF2_RSRVD0(v) \ + (((v) << 10) & BM_ELCDIF_CSC_COEFF2_RSRVD0) +#define BP_ELCDIF_CSC_COEFF2_C3 0 +#define BM_ELCDIF_CSC_COEFF2_C3 0x000003FF +#define BF_ELCDIF_CSC_COEFF2_C3(v) \ + (((v) << 0) & BM_ELCDIF_CSC_COEFF2_C3) + +#define HW_ELCDIF_CSC_COEFF3 (0x00000140) + +#define BP_ELCDIF_CSC_COEFF3_RSRVD1 26 +#define BM_ELCDIF_CSC_COEFF3_RSRVD1 0xFC000000 +#define BF_ELCDIF_CSC_COEFF3_RSRVD1(v) \ + (((v) << 26) & BM_ELCDIF_CSC_COEFF3_RSRVD1) +#define BP_ELCDIF_CSC_COEFF3_C6 16 +#define BM_ELCDIF_CSC_COEFF3_C6 0x03FF0000 +#define BF_ELCDIF_CSC_COEFF3_C6(v) \ + (((v) << 16) & BM_ELCDIF_CSC_COEFF3_C6) +#define BP_ELCDIF_CSC_COEFF3_RSRVD0 10 +#define BM_ELCDIF_CSC_COEFF3_RSRVD0 0x0000FC00 +#define BF_ELCDIF_CSC_COEFF3_RSRVD0(v) \ + (((v) << 10) & BM_ELCDIF_CSC_COEFF3_RSRVD0) +#define BP_ELCDIF_CSC_COEFF3_C5 0 +#define BM_ELCDIF_CSC_COEFF3_C5 0x000003FF +#define BF_ELCDIF_CSC_COEFF3_C5(v) \ + (((v) << 0) & BM_ELCDIF_CSC_COEFF3_C5) + +#define HW_ELCDIF_CSC_COEFF4 (0x00000150) + +#define BP_ELCDIF_CSC_COEFF4_RSRVD1 26 +#define BM_ELCDIF_CSC_COEFF4_RSRVD1 0xFC000000 +#define BF_ELCDIF_CSC_COEFF4_RSRVD1(v) \ + (((v) << 26) & BM_ELCDIF_CSC_COEFF4_RSRVD1) +#define BP_ELCDIF_CSC_COEFF4_C8 16 +#define BM_ELCDIF_CSC_COEFF4_C8 0x03FF0000 +#define BF_ELCDIF_CSC_COEFF4_C8(v) \ + (((v) << 16) & BM_ELCDIF_CSC_COEFF4_C8) +#define BP_ELCDIF_CSC_COEFF4_RSRVD0 10 +#define BM_ELCDIF_CSC_COEFF4_RSRVD0 0x0000FC00 +#define BF_ELCDIF_CSC_COEFF4_RSRVD0(v) \ + (((v) << 10) & BM_ELCDIF_CSC_COEFF4_RSRVD0) +#define BP_ELCDIF_CSC_COEFF4_C7 0 +#define BM_ELCDIF_CSC_COEFF4_C7 0x000003FF +#define BF_ELCDIF_CSC_COEFF4_C7(v) \ + (((v) << 0) & BM_ELCDIF_CSC_COEFF4_C7) + +#define HW_ELCDIF_CSC_OFFSET (0x00000160) + +#define BP_ELCDIF_CSC_OFFSET_RSRVD1 25 +#define BM_ELCDIF_CSC_OFFSET_RSRVD1 0xFE000000 +#define BF_ELCDIF_CSC_OFFSET_RSRVD1(v) \ + (((v) << 25) & BM_ELCDIF_CSC_OFFSET_RSRVD1) +#define BP_ELCDIF_CSC_OFFSET_CBCR_OFFSET 16 +#define BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 +#define BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(v) \ + (((v) << 16) & BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET) +#define BP_ELCDIF_CSC_OFFSET_RSRVD0 9 +#define BM_ELCDIF_CSC_OFFSET_RSRVD0 0x0000FE00 +#define BF_ELCDIF_CSC_OFFSET_RSRVD0(v) \ + (((v) << 9) & BM_ELCDIF_CSC_OFFSET_RSRVD0) +#define BP_ELCDIF_CSC_OFFSET_Y_OFFSET 0 +#define BM_ELCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF +#define BF_ELCDIF_CSC_OFFSET_Y_OFFSET(v) \ + (((v) << 0) & BM_ELCDIF_CSC_OFFSET_Y_OFFSET) + +#define HW_ELCDIF_CSC_LIMIT (0x00000170) + +#define BP_ELCDIF_CSC_LIMIT_CBCR_MIN 24 +#define BM_ELCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 +#define BF_ELCDIF_CSC_LIMIT_CBCR_MIN(v) \ + (((v) << 24) & BM_ELCDIF_CSC_LIMIT_CBCR_MIN) +#define BP_ELCDIF_CSC_LIMIT_CBCR_MAX 16 +#define BM_ELCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 +#define BF_ELCDIF_CSC_LIMIT_CBCR_MAX(v) \ + (((v) << 16) & BM_ELCDIF_CSC_LIMIT_CBCR_MAX) +#define BP_ELCDIF_CSC_LIMIT_Y_MIN 8 +#define BM_ELCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 +#define BF_ELCDIF_CSC_LIMIT_Y_MIN(v) \ + (((v) << 8) & BM_ELCDIF_CSC_LIMIT_Y_MIN) +#define BP_ELCDIF_CSC_LIMIT_Y_MAX 0 +#define BM_ELCDIF_CSC_LIMIT_Y_MAX 0x000000FF +#define BF_ELCDIF_CSC_LIMIT_Y_MAX(v) \ + (((v) << 0) & BM_ELCDIF_CSC_LIMIT_Y_MAX) + +#define HW_ELCDIF_DATA (0x00000180) + +#define BP_ELCDIF_DATA_DATA_THREE 24 +#define BM_ELCDIF_DATA_DATA_THREE 0xFF000000 +#define BF_ELCDIF_DATA_DATA_THREE(v) \ + (((v) << 24) & BM_ELCDIF_DATA_DATA_THREE) +#define BP_ELCDIF_DATA_DATA_TWO 16 +#define BM_ELCDIF_DATA_DATA_TWO 0x00FF0000 +#define BF_ELCDIF_DATA_DATA_TWO(v) \ + (((v) << 16) & BM_ELCDIF_DATA_DATA_TWO) +#define BP_ELCDIF_DATA_DATA_ONE 8 +#define BM_ELCDIF_DATA_DATA_ONE 0x0000FF00 +#define BF_ELCDIF_DATA_DATA_ONE(v) \ + (((v) << 8) & BM_ELCDIF_DATA_DATA_ONE) +#define BP_ELCDIF_DATA_DATA_ZERO 0 +#define BM_ELCDIF_DATA_DATA_ZERO 0x000000FF +#define BF_ELCDIF_DATA_DATA_ZERO(v) \ + (((v) << 0) & BM_ELCDIF_DATA_DATA_ZERO) + +#define HW_ELCDIF_BM_ERROR_STAT (0x00000190) + +#define BP_ELCDIF_BM_ERROR_STAT_ADDR 0 +#define BM_ELCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF +#define BF_ELCDIF_BM_ERROR_STAT_ADDR(v) (v) + +#define HW_ELCDIF_CRC_STAT (0x000001a0) + +#define BP_ELCDIF_CRC_STAT_CRC_VALUE 0 +#define BM_ELCDIF_CRC_STAT_CRC_VALUE 0xFFFFFFFF +#define BF_ELCDIF_CRC_STAT_CRC_VALUE(v) (v) + +#define HW_ELCDIF_STAT (0x000001b0) + +#define BM_ELCDIF_STAT_PRESENT 0x80000000 +#define BM_ELCDIF_STAT_DMA_REQ 0x40000000 +#define BM_ELCDIF_STAT_LFIFO_FULL 0x20000000 +#define BM_ELCDIF_STAT_LFIFO_EMPTY 0x10000000 +#define BM_ELCDIF_STAT_TXFIFO_FULL 0x08000000 +#define BM_ELCDIF_STAT_TXFIFO_EMPTY 0x04000000 +#define BM_ELCDIF_STAT_BUSY 0x02000000 +#define BM_ELCDIF_STAT_DVI_CURRENT_FIELD 0x01000000 +#define BP_ELCDIF_STAT_RSRVD0 9 +#define BM_ELCDIF_STAT_RSRVD0 0x00FFFE00 +#define BF_ELCDIF_STAT_RSRVD0(v) \ + (((v) << 9) & BM_ELCDIF_STAT_RSRVD0) +#define BP_ELCDIF_STAT_LFIFO_COUNT 0 +#define BM_ELCDIF_STAT_LFIFO_COUNT 0x000001FF +#define BF_ELCDIF_STAT_LFIFO_COUNT(v) \ + (((v) << 0) & BM_ELCDIF_STAT_LFIFO_COUNT) + +#define HW_ELCDIF_VERSION (0x000001c0) + +#define BP_ELCDIF_VERSION_MAJOR 24 +#define BM_ELCDIF_VERSION_MAJOR 0xFF000000 +#define BF_ELCDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ELCDIF_VERSION_MAJOR) +#define BP_ELCDIF_VERSION_MINOR 16 +#define BM_ELCDIF_VERSION_MINOR 0x00FF0000 +#define BF_ELCDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_ELCDIF_VERSION_MINOR) +#define BP_ELCDIF_VERSION_STEP 0 +#define BM_ELCDIF_VERSION_STEP 0x0000FFFF +#define BF_ELCDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_ELCDIF_VERSION_STEP) + +#define HW_ELCDIF_DEBUG0 (0x000001d0) + +#define BM_ELCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 +#define BM_ELCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 +#define BM_ELCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 +#define BM_ELCDIF_DEBUG0_DMACMDKICK 0x10000000 +#define BM_ELCDIF_DEBUG0_ENABLE 0x08000000 +#define BM_ELCDIF_DEBUG0_HSYNC 0x04000000 +#define BM_ELCDIF_DEBUG0_VSYNC 0x02000000 +#define BM_ELCDIF_DEBUG0_CUR_FRAME_TX 0x01000000 +#define BM_ELCDIF_DEBUG0_EMPTY_WORD 0x00800000 +#define BP_ELCDIF_DEBUG0_CUR_STATE 16 +#define BM_ELCDIF_DEBUG0_CUR_STATE 0x007F0000 +#define BF_ELCDIF_DEBUG0_CUR_STATE(v) \ + (((v) << 16) & BM_ELCDIF_DEBUG0_CUR_STATE) +#define BM_ELCDIF_DEBUG0_PXP_ELCDIF_B0_READY 0x00008000 +#define BM_ELCDIF_DEBUG0_ELCDIF_PXP_B0_DONE 0x00004000 +#define BM_ELCDIF_DEBUG0_PXP_ELCDIF_B1_READY 0x00002000 +#define BM_ELCDIF_DEBUG0_ELCDIF_PXP_B1_DONE 0x00001000 +#define BP_ELCDIF_DEBUG0_CUR_REQ_STATE 10 +#define BM_ELCDIF_DEBUG0_CUR_REQ_STATE 0x00000C00 +#define BF_ELCDIF_DEBUG0_CUR_REQ_STATE(v) \ + (((v) << 10) & BM_ELCDIF_DEBUG0_CUR_REQ_STATE) +#define BM_ELCDIF_DEBUG0_MST_AVALID 0x00000200 +#define BP_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS 4 +#define BM_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS 0x000001F0 +#define BF_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS(v) \ + (((v) << 4) & BM_ELCDIF_DEBUG0_MST_OUTSTANDING_REQS) +#define BP_ELCDIF_DEBUG0_MST_WORDS 0 +#define BM_ELCDIF_DEBUG0_MST_WORDS 0x0000000F +#define BF_ELCDIF_DEBUG0_MST_WORDS(v) \ + (((v) << 0) & BM_ELCDIF_DEBUG0_MST_WORDS) + +#define HW_ELCDIF_DEBUG1 (0x000001e0) + +#define BP_ELCDIF_DEBUG1_H_DATA_COUNT 16 +#define BM_ELCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000 +#define BF_ELCDIF_DEBUG1_H_DATA_COUNT(v) \ + (((v) << 16) & BM_ELCDIF_DEBUG1_H_DATA_COUNT) +#define BP_ELCDIF_DEBUG1_V_DATA_COUNT 0 +#define BM_ELCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF +#define BF_ELCDIF_DEBUG1_V_DATA_COUNT(v) \ + (((v) << 0) & BM_ELCDIF_DEBUG1_V_DATA_COUNT) + +#define HW_ELCDIF_DEBUG2 (0x000001f0) + +#define BP_ELCDIF_DEBUG2_MST_ADDRESS 0 +#define BM_ELCDIF_DEBUG2_MST_ADDRESS 0xFFFFFFFF +#define BF_ELCDIF_DEBUG2_MST_ADDRESS(v) (v) +#endif /* __ELCDIF_REGS_INCLUDED_ */ diff --git a/drivers/video/mxc/epdc_regs.h b/drivers/video/mxc/epdc_regs.h new file mode 100644 index 000000000000..f9232d8a9a51 --- /dev/null +++ b/drivers/video/mxc/epdc_regs.h @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __EPDC_REGS_INCLUDED__ +#define __EPDC_REGS_INCLUDED__ + +extern void __iomem *epdc_base; + +/************************************* + * Register addresses + **************************************/ + +#define EPDC_CTRL (epdc_base + 0x000) +#define EPDC_CTRL_SET (epdc_base + 0x004) +#define EPDC_CTRL_CLEAR (epdc_base + 0x008) +#define EPDC_CTRL_TOGGLE (epdc_base + 0x00C) +#define EPDC_WVADDR (epdc_base + 0x020) +#define EPDC_WB_ADDR (epdc_base + 0x030) +#define EPDC_RES (epdc_base + 0x040) +#define EPDC_FORMAT (epdc_base + 0x050) +#define EPDC_FORMAT_SET (epdc_base + 0x054) +#define EPDC_FORMAT_CLEAR (epdc_base + 0x058) +#define EPDC_FORMAT_TOGGLE (epdc_base + 0x05C) +#define EPDC_FIFOCTRL (epdc_base + 0x0A0) +#define EPDC_FIFOCTRL_SET (epdc_base + 0x0A4) +#define EPDC_FIFOCTRL_CLEAR (epdc_base + 0x0A8) +#define EPDC_FIFOCTRL_TOGGLE (epdc_base + 0x0AC) +#define EPDC_UPD_ADDR (epdc_base + 0x100) +#define EPDC_UPD_CORD (epdc_base + 0x120) +#define EPDC_UPD_SIZE (epdc_base + 0x140) +#define EPDC_UPD_CTRL (epdc_base + 0x160) +#define EPDC_UPD_FIXED (epdc_base + 0x180) +#define EPDC_TEMP (epdc_base + 0x1A0) +#define EPDC_TCE_CTRL (epdc_base + 0x200) +#define EPDC_TCE_SDCFG (epdc_base + 0x220) +#define EPDC_TCE_GDCFG (epdc_base + 0x240) +#define EPDC_TCE_HSCAN1 (epdc_base + 0x260) +#define EPDC_TCE_HSCAN2 (epdc_base + 0x280) +#define EPDC_TCE_VSCAN (epdc_base + 0x2A0) +#define EPDC_TCE_OE (epdc_base + 0x2C0) +#define EPDC_TCE_POLARITY (epdc_base + 0x2E0) +#define EPDC_TCE_TIMING1 (epdc_base + 0x300) +#define EPDC_TCE_TIMING2 (epdc_base + 0x310) +#define EPDC_TCE_TIMING3 (epdc_base + 0x320) +#define EPDC_IRQ_MASK (epdc_base + 0x400) +#define EPDC_IRQ_MASK_SET (epdc_base + 0x404) +#define EPDC_IRQ_MASK_CLEAR (epdc_base + 0x408) +#define EPDC_IRQ_MASK_TOGGLE (epdc_base + 0x40C) +#define EPDC_IRQ (epdc_base + 0x420) +#define EPDC_IRQ_SET (epdc_base + 0x424) +#define EPDC_IRQ_CLEAR (epdc_base + 0x428) +#define EPDC_IRQ_TOGGLE (epdc_base + 0x42C) +#define EPDC_STATUS_LUTS (epdc_base + 0x440) +#define EPDC_STATUS_LUTS_SET (epdc_base + 0x444) +#define EPDC_STATUS_LUTS_CLEAR (epdc_base + 0x448) +#define EPDC_STATUS_LUTS_TOGGLE (epdc_base + 0x44C) +#define EPDC_STATUS_NEXTLUT (epdc_base + 0x460) +#define EPDC_STATUS_COL (epdc_base + 0x480) +#define EPDC_STATUS (epdc_base + 0x4A0) +#define EPDC_STATUS_SET (epdc_base + 0x4A4) +#define EPDC_STATUS_CLEAR (epdc_base + 0x4A8) +#define EPDC_STATUS_TOGGLE (epdc_base + 0x4AC) +#define EPDC_DEBUG (epdc_base + 0x500) +#define EPDC_DEBUG_LUT0 (epdc_base + 0x540) +#define EPDC_DEBUG_LUT1 (epdc_base + 0x550) +#define EPDC_DEBUG_LUT2 (epdc_base + 0x560) +#define EPDC_DEBUG_LUT3 (epdc_base + 0x570) +#define EPDC_DEBUG_LUT4 (epdc_base + 0x580) +#define EPDC_DEBUG_LUT5 (epdc_base + 0x590) +#define EPDC_DEBUG_LUT6 (epdc_base + 0x5A0) +#define EPDC_DEBUG_LUT7 (epdc_base + 0x5B0) +#define EPDC_DEBUG_LUT8 (epdc_base + 0x5C0) +#define EPDC_DEBUG_LUT9 (epdc_base + 0x5D0) +#define EPDC_DEBUG_LUT10 (epdc_base + 0x5E0) +#define EPDC_DEBUG_LUT11 (epdc_base + 0x5F0) +#define EPDC_DEBUG_LUT12 (epdc_base + 0x600) +#define EPDC_DEBUG_LUT13 (epdc_base + 0x610) +#define EPDC_DEBUG_LUT14 (epdc_base + 0x620) +#define EPDC_DEBUG_LUT15 (epdc_base + 0x630) +#define EPDC_GPIO (epdc_base + 0x700) +#define EPDC_VERSION (epdc_base + 0x7F0) + +/* + * Register field definitions + */ + +enum { +/* EPDC_CTRL field values */ + EPDC_CTRL_SFTRST = 0x80000000, + EPDC_CTRL_CLKGATE = 0x40000000, + EPDC_CTRL_SRAM_POWERDOWN = 0x100, + EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0, + EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0, + EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40, + EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80, + EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0, + EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30, + EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0, + EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10, + EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20, + EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30, + EPDC_CTRL_BURST_LEN_8_8 = 0x1, + EPDC_CTRL_BURST_LEN_8_16 = 0, + +/* EPDC_RES field values */ + EPDC_RES_VERTICAL_MASK = 0x1FFF0000, + EPDC_RES_VERTICAL_OFFSET = 16, + EPDC_RES_HORIZONTAL_MASK = 0x1FFF, + EPDC_RES_HORIZONTAL_OFFSET = 0, + +/* EPDC_FORMAT field values */ + EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000, + EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000, + EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500, + EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0, + EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1, + EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2, + EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3, + +/* EPDC_FIFOCTRL field values */ + EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000, + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000, + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16, + EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00, + EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8, + EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF, + EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0, + +/* EPDC_UPD_CORD field values */ + EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000, + EPDC_UPD_CORD_YCORD_OFFSET = 16, + EPDC_UPD_CORD_XCORD_MASK = 0x1FFF, + EPDC_UPD_CORD_XCORD_OFFSET = 0, + +/* EPDC_UPD_SIZE field values */ + EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000, + EPDC_UPD_SIZE_HEIGHT_OFFSET = 16, + EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF, + EPDC_UPD_SIZE_WIDTH_OFFSET = 0, + +/* EPDC_UPD_CTRL field values */ + EPDC_UPD_CTRL_USE_FIXED = 0x80000000, + EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000, + EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16, + EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00, + EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8, + EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1, + +/* EPDC_UPD_FIXED field values */ + EPDC_UPD_FIXED_FIXNP_EN = 0x80000000, + EPDC_UPD_FIXED_FIXCP_EN = 0x40000000, + EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00, + EPDC_UPD_FIXED_FIXNP_OFFSET = 8, + EPDC_UPD_FIXED_FIXCP_MASK = 0xFF, + EPDC_UPD_FIXED_FIXCP_OFFSET = 0, + +/* EPDC_TCE_CTRL field values */ + EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000, + EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16, + EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00, + EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10, + EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200, + EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000, + EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100, + EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80, + EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40, + EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20, + EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10, + EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8, + EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3, + +/* EPDC_TCE_SDCFG field values */ + EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000, + EPDC_TCE_SDCFG_SDSHR = 0x100000, + EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000, + EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16, + EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0, + EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000, + EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000, + EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF, + EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0, + +/* EPDC_TCE_GDCFG field values */ + EPDC_TCE_SDCFG_GDRL = 0x10, + EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2, + EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1, + EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0, + +/* EPDC_TCE_HSCAN1 field values */ + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000, + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16, + EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF, + EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0, + +/* EPDC_TCE_HSCAN2 field values */ + EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000, + EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16, + EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF, + EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0, + +/* EPDC_TCE_VSCAN field values */ + EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000, + EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16, + EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00, + EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8, + EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF, + EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0, + +/* EPDC_TCE_OE field values */ + EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000, + EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24, + EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000, + EPDC_TCE_OE_SDOED_DLY_OFFSET = 16, + EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00, + EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8, + EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF, + EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0, + +/* EPDC_TCE_POLARITY field values */ + EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10, + EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8, + EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4, + EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2, + EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1, + +/* EPDC_TCE_TIMING1 field values */ + EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00, + EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10, + EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20, + EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30, + EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8, + EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0, + EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1, + EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2, + EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3, + +/* EPDC_TCE_TIMING2 field values */ + EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000, + EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16, + EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF, + EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0, + +/* EPDC_TCE_TIMING3 field values */ + EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000, + EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16, + EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF, + EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0, + +/* EPDC_IRQ_MASK/EPDC_IRQ field values */ + EPDC_IRQ_WB_CMPLT_IRQ = 0x10000, + EPDC_IRQ_LUT_COL_IRQ = 0x20000, + EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000, + EPDC_IRQ_FRAME_END_IRQ = 0x80000, + EPDC_IRQ_BUS_ERROR_IRQ = 0x100000, + EPDC_IRQ_TCE_IDLE_IRQ = 0x200000, + +/* EPDC_STATUS_NEXTLUT field values */ + EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100, + EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0xF, + EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0, + +/* EPDC_STATUS field values */ + EPDC_STATUS_LUTS_UNDERRUN = 0x4, + EPDC_STATUS_LUTS_BUSY = 0x2, + EPDC_STATUS_WB_BUSY = 0x1, + +/* EPDC_DEBUG field values */ + EPDC_DEBUG_UNDERRUN_RECOVER = 0x2, + EPDC_DEBUG_COLLISION_OFF = 0x1, + +/* EPDC_GPIO field values */ + EPDC_GPIO_PWRCOM = 0x40, + EPDC_GPIO_PWRCTRL_MASK = 0x3C, + EPDC_GPIO_PWRCTRL_OFFSET = 2, + EPDC_GPIO_BDR_MASK = 0x3, + EPDC_GPIO_BDR_OFFSET = 0, +}; + +#endif /* __EPDC_REGS_INCLUDED__ */ diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c new file mode 100644 index 000000000000..258c51985b67 --- /dev/null +++ b/drivers/video/mxc/ldb.c @@ -0,0 +1,1458 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file mxc_ldb.c + * + * @brief This file contains the LDB driver device interface and fops + * functions. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LDB_BGREF_RMODE_MASK 0x00008000 +#define LDB_BGREF_RMODE_INT 0x00008000 +#define LDB_BGREF_RMODE_EXT 0x0 + +#define LDB_DI1_VS_POL_MASK 0x00000400 +#define LDB_DI1_VS_POL_ACT_LOW 0x00000400 +#define LDB_DI1_VS_POL_ACT_HIGH 0x0 +#define LDB_DI0_VS_POL_MASK 0x00000200 +#define LDB_DI0_VS_POL_ACT_LOW 0x00000200 +#define LDB_DI0_VS_POL_ACT_HIGH 0x0 + +#define LDB_BIT_MAP_CH1_MASK 0x00000100 +#define LDB_BIT_MAP_CH1_JEIDA 0x00000100 +#define LDB_BIT_MAP_CH1_SPWG 0x0 +#define LDB_BIT_MAP_CH0_MASK 0x00000040 +#define LDB_BIT_MAP_CH0_JEIDA 0x00000040 +#define LDB_BIT_MAP_CH0_SPWG 0x0 + +#define LDB_DATA_WIDTH_CH1_MASK 0x00000080 +#define LDB_DATA_WIDTH_CH1_24 0x00000080 +#define LDB_DATA_WIDTH_CH1_18 0x0 +#define LDB_DATA_WIDTH_CH0_MASK 0x00000020 +#define LDB_DATA_WIDTH_CH0_24 0x00000020 +#define LDB_DATA_WIDTH_CH0_18 0x0 + +#define LDB_CH1_MODE_MASK 0x0000000C +#define LDB_CH1_MODE_EN_TO_DI1 0x0000000C +#define LDB_CH1_MODE_EN_TO_DI0 0x00000004 +#define LDB_CH1_MODE_DISABLE 0x0 +#define LDB_CH0_MODE_MASK 0x00000003 +#define LDB_CH0_MODE_EN_TO_DI1 0x00000003 +#define LDB_CH0_MODE_EN_TO_DI0 0x00000001 +#define LDB_CH0_MODE_DISABLE 0x0 + +#define LDB_SPLIT_MODE_EN 0x00000010 + +enum ldb_chan_mode_opt { + LDB_SIN_DI0 = 0, + LDB_SIN_DI1 = 1, + LDB_SEP = 2, + LDB_DUL_DI0 = 3, + LDB_DUL_DI1 = 4, + LDB_SPL_DI0 = 5, + LDB_SPL_DI1 = 6, +}; + +static struct ldb_data { + struct fb_info *fbi[2]; + bool ch_working[2]; + uint32_t chan_mode_opt; + uint32_t chan_bit_map[2]; + uint32_t bgref_rmode; + uint32_t base_addr; + uint32_t *control_reg; + struct clk *ldb_di_clk[2]; + struct regulator *lvds_bg_reg; + struct list_head modelist; +} ldb; + +static struct device *g_ldb_dev; +static u32 *ldb_reg; +static bool enabled[2]; +static int g_chan_mode_opt; +static int g_chan_bit_map[2]; +static bool g_enable_ldb; +static bool g_boot_cmd; + +DEFINE_SPINLOCK(ldb_lock); + +struct fb_videomode mxcfb_ldb_modedb[] = { + { + "1080P60", 60, 1920, 1080, 7692, + 100, 40, + 30, 3, + 10, 2, + 0, + FB_VMODE_NONINTERLACED, + 0,}, + { + "XGA", 60, 1024, 768, 15385, + 220, 40, + 21, 7, + 60, 10, + 0, + FB_VMODE_NONINTERLACED, + 0,}, +}; +int mxcfb_ldb_modedb_sz = ARRAY_SIZE(mxcfb_ldb_modedb); + +static int bits_per_pixel(int pixel_fmt) +{ + switch (pixel_fmt) { + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + return 24; + break; + case IPU_PIX_FMT_BGR666: + case IPU_PIX_FMT_RGB666: + case IPU_PIX_FMT_LVDS666: + return 18; + break; + default: + break; + } + return 0; +} + +static int valid_mode(int pixel_fmt) +{ + return ((pixel_fmt == IPU_PIX_FMT_RGB24) || + (pixel_fmt == IPU_PIX_FMT_BGR24) || + (pixel_fmt == IPU_PIX_FMT_LVDS666) || + (pixel_fmt == IPU_PIX_FMT_RGB666) || + (pixel_fmt == IPU_PIX_FMT_BGR666)); +} + +static void ldb_disable(int ipu_di) +{ + uint32_t reg; + int i = 0; + + spin_lock(&ldb_lock); + + switch (ldb.chan_mode_opt) { + case LDB_SIN_DI0: + if (ipu_di != 0 || !ldb.ch_working[0] || !enabled[0]) { + spin_unlock(&ldb_lock); + return; + } + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_DISABLE, + ldb.control_reg); + + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + clk_disable(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[0]); + + ldb.ch_working[0] = false; + enabled[0] = false; + break; + case LDB_SIN_DI1: + if (ipu_di != 1 || !ldb.ch_working[1] || !enabled[1]) { + spin_unlock(&ldb_lock); + return; + } + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~LDB_CH1_MODE_MASK) | + LDB_CH1_MODE_DISABLE, + ldb.control_reg); + + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + clk_disable(ldb.ldb_di_clk[1]); + clk_put(ldb.ldb_di_clk[1]); + + ldb.ch_working[1] = false; + enabled[1] = false; + break; + case LDB_SPL_DI0: + case LDB_DUL_DI0: + if (ipu_di != 0 || !enabled[0]) { + spin_unlock(&ldb_lock); + return; + } + + for (i = 0; i < 2; i++) { + if (ldb.ch_working[i]) { + reg = __raw_readl(ldb.control_reg); + if (i == 0) + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_DISABLE, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH1_MODE_DISABLE, + ldb.control_reg); + + if (ldb.chan_mode_opt == LDB_SPL_DI0) { + reg = __raw_readl(ldb.control_reg); + __raw_writel(reg & ~LDB_SPLIT_MODE_EN, + ldb.control_reg); + } + + ldb.ldb_di_clk[i] = clk_get(NULL, i ? + "ldb_di1_clk" : + "ldb_di0_clk"); + clk_disable(ldb.ldb_di_clk[i]); + clk_put(ldb.ldb_di_clk[i]); + + ldb.ch_working[i] = false; + } + } + enabled[0] = false; + break; + case LDB_SPL_DI1: + case LDB_DUL_DI1: + if (ipu_di != 1 || !enabled[1]) { + spin_unlock(&ldb_lock); + return; + } + + for (i = 0; i < 2; i++) { + if (ldb.ch_working[i]) { + reg = __raw_readl(ldb.control_reg); + if (i == 0) + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_DISABLE, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH1_MODE_DISABLE, + ldb.control_reg); + + if (ldb.chan_mode_opt == LDB_SPL_DI1) { + reg = __raw_readl(ldb.control_reg); + __raw_writel(reg & ~LDB_SPLIT_MODE_EN, + ldb.control_reg); + } + + ldb.ldb_di_clk[i] = clk_get(NULL, i ? + "ldb_di1_clk" : + "ldb_di0_clk"); + clk_disable(ldb.ldb_di_clk[i]); + clk_put(ldb.ldb_di_clk[i]); + + ldb.ch_working[i] = false; + } + } + enabled[1] = false; + break; + case LDB_SEP: + if (ldb.ch_working[ipu_di] && enabled[ipu_di]) { + reg = __raw_readl(ldb.control_reg); + if (ipu_di == 0) + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_DISABLE, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_CH1_MODE_MASK) | + LDB_CH1_MODE_DISABLE, + ldb.control_reg); + + ldb.ldb_di_clk[ipu_di] = clk_get(NULL, ipu_di ? + "ldb_di1_clk" : + "ldb_di0_clk"); + clk_disable(ldb.ldb_di_clk[ipu_di]); + clk_put(ldb.ldb_di_clk[ipu_di]); + + ldb.ch_working[ipu_di] = false; + enabled[ipu_di] = false; + } + break; + default: + break; + } + + spin_unlock(&ldb_lock); + return; +} + +static void ldb_enable(int ipu_di) +{ + uint32_t reg; + + spin_lock(&ldb_lock); + + reg = __raw_readl(ldb.control_reg); + switch (ldb.chan_mode_opt) { + case LDB_SIN_DI0: + if (ldb.ch_working[0] || ipu_di != 0 || enabled[0]) { + spin_unlock(&ldb_lock); + return; + } + + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + clk_enable(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[0]); + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_EN_TO_DI0, ldb.control_reg); + ldb.ch_working[0] = true; + enabled[0] = true; + break; + case LDB_SIN_DI1: + if (ldb.ch_working[1] || ipu_di != 1 || enabled[1]) { + spin_unlock(&ldb_lock); + return; + } + + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + clk_enable(ldb.ldb_di_clk[1]); + clk_put(ldb.ldb_di_clk[1]); + __raw_writel((reg & ~LDB_CH1_MODE_MASK) | + LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg); + ldb.ch_working[1] = true; + enabled[1] = true; + break; + case LDB_SEP: + if (ldb.ch_working[ipu_di] || enabled[ipu_di]) { + spin_unlock(&ldb_lock); + return; + } + + if (ipu_di == 0) { + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + clk_enable(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[0]); + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_EN_TO_DI0, + ldb.control_reg); + ldb.ch_working[0] = true; + } else { + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + clk_enable(ldb.ldb_di_clk[1]); + clk_put(ldb.ldb_di_clk[1]); + __raw_writel((reg & ~LDB_CH1_MODE_MASK) | + LDB_CH1_MODE_EN_TO_DI1, + ldb.control_reg); + ldb.ch_working[1] = true; + } + enabled[ipu_di] = true; + break; + case LDB_DUL_DI0: + case LDB_SPL_DI0: + if (ipu_di != 0 || enabled[0]) + return; + else + goto proc; + case LDB_DUL_DI1: + case LDB_SPL_DI1: + if (ipu_di != 1 || enabled[1]) + return; +proc: + if (ldb.ch_working[0] || ldb.ch_working[1]) { + spin_unlock(&ldb_lock); + return; + } + + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + clk_enable(ldb.ldb_di_clk[0]); + clk_enable(ldb.ldb_di_clk[1]); + clk_put(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[1]); + + if (ldb.chan_mode_opt == LDB_DUL_DI0 || + ldb.chan_mode_opt == LDB_SPL_DI0) { + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_EN_TO_DI0, + ldb.control_reg); + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~LDB_CH1_MODE_MASK) | + LDB_CH1_MODE_EN_TO_DI0, + ldb.control_reg); + } else if (ldb.chan_mode_opt == LDB_DUL_DI1 || + ldb.chan_mode_opt == LDB_SPL_DI1) { + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_EN_TO_DI1, + ldb.control_reg); + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~LDB_CH1_MODE_MASK) | + LDB_CH1_MODE_EN_TO_DI1, + ldb.control_reg); + } + if (ldb.chan_mode_opt == LDB_SPL_DI0 || + ldb.chan_mode_opt == LDB_SPL_DI1) { + reg = __raw_readl(ldb.control_reg); + __raw_writel(reg | LDB_SPLIT_MODE_EN, + ldb.control_reg); + } + ldb.ch_working[0] = true; + ldb.ch_working[1] = true; + enabled[ipu_di] = true; + break; + default: + break; + } + spin_unlock(&ldb_lock); + return; +} + +int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + struct fb_info *fbi = event->info; + mm_segment_t old_fs; + int ipu_di = 0; + + switch (val) { + case FB_EVENT_BLANK: + if (ldb.fbi[0] != fbi && ldb.fbi[1] != fbi) + return 0; + + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, + MXCFB_GET_FB_IPU_DI, + (unsigned long)&ipu_di); + set_fs(old_fs); + } else + return 0; + + if (*((int *)event->data) == FB_BLANK_UNBLANK) + ldb_enable(ipu_di); + else + ldb_disable(ipu_di); + break; + default: + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = ldb_fb_event, +}; + +static int mxc_ldb_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int ret = 0; + uint32_t reg; + + switch (cmd) { + case LDB_BGREF_RMODE: + { + ldb_bgref_parm parm; + + if (copy_from_user(&parm, (ldb_bgref_parm *) arg, + sizeof(ldb_bgref_parm))) + return -EFAULT; + + spin_lock(&ldb_lock); + reg = __raw_readl(ldb.control_reg); + if (parm.bgref_mode == LDB_EXT_REF) + __raw_writel((reg & ~LDB_BGREF_RMODE_MASK) | + LDB_BGREF_RMODE_EXT, ldb.control_reg); + else if (parm.bgref_mode == LDB_INT_REF) + __raw_writel((reg & ~LDB_BGREF_RMODE_MASK) | + LDB_BGREF_RMODE_INT, ldb.control_reg); + spin_unlock(&ldb_lock); + break; + } + case LDB_VSYNC_POL: + { + ldb_vsync_parm parm; + + if (copy_from_user(&parm, (ldb_vsync_parm *) arg, + sizeof(ldb_vsync_parm))) + return -EFAULT; + + spin_lock(&ldb_lock); + reg = __raw_readl(ldb.control_reg); + if (parm.vsync_mode == LDB_VS_ACT_H) { + if (parm.di == 0) + __raw_writel((reg & + ~LDB_DI0_VS_POL_MASK) | + LDB_DI0_VS_POL_ACT_HIGH, + ldb.control_reg); + else + __raw_writel((reg & + ~LDB_DI1_VS_POL_MASK) | + LDB_DI1_VS_POL_ACT_HIGH, + ldb.control_reg); + } else if (parm.vsync_mode == LDB_VS_ACT_L) { + if (parm.di == 0) + __raw_writel((reg & + ~LDB_DI0_VS_POL_MASK) | + LDB_DI0_VS_POL_ACT_LOW, + ldb.control_reg); + else + __raw_writel((reg & + ~LDB_DI1_VS_POL_MASK) | + LDB_DI1_VS_POL_ACT_LOW, + ldb.control_reg); + + } + spin_unlock(&ldb_lock); + break; + } + case LDB_BIT_MAP: + { + ldb_bitmap_parm parm; + + if (copy_from_user(&parm, (ldb_bitmap_parm *) arg, + sizeof(ldb_bitmap_parm))) + return -EFAULT; + + spin_lock(&ldb_lock); + reg = __raw_readl(ldb.control_reg); + if (parm.bitmap_mode == LDB_BIT_MAP_SPWG) { + if (parm.channel == 0) + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH1_SPWG, + ldb.control_reg); + } else if (parm.bitmap_mode == LDB_BIT_MAP_JEIDA) { + if (parm.channel == 0) + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_JEIDA, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH1_JEIDA, + ldb.control_reg); + } + spin_unlock(&ldb_lock); + break; + } + case LDB_DATA_WIDTH: + { + ldb_data_width_parm parm; + + if (copy_from_user(&parm, (ldb_data_width_parm *) arg, + sizeof(ldb_data_width_parm))) + return -EFAULT; + + spin_lock(&ldb_lock); + reg = __raw_readl(ldb.control_reg); + if (parm.data_width == 24) { + if (parm.channel == 0) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) | + LDB_DATA_WIDTH_CH0_24, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) | + LDB_DATA_WIDTH_CH1_24, + ldb.control_reg); + } else if (parm.data_width == 18) { + if (parm.channel == 0) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) | + LDB_DATA_WIDTH_CH0_18, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) | + LDB_DATA_WIDTH_CH1_18, + ldb.control_reg); + } + spin_unlock(&ldb_lock); + break; + } + case LDB_CHAN_MODE: + { + ldb_chan_mode_parm parm; + struct clk *pll4_clk; + unsigned long pll4_rate = 0; + + if (copy_from_user(&parm, (ldb_chan_mode_parm *) arg, + sizeof(ldb_chan_mode_parm))) + return -EFAULT; + + spin_lock(&ldb_lock); + + /* TODO:Set the correct pll4 rate for all situations */ + pll4_clk = clk_get(NULL, "pll4"); + pll4_rate = clk_get_rate(pll4_clk); + pll4_rate = 455000000; + clk_set_rate(pll4_clk, pll4_rate); + clk_put(pll4_clk); + + reg = __raw_readl(ldb.control_reg); + switch (parm.channel_mode) { + case LDB_CHAN_MODE_SIN: + if (parm.di == 0) { + ldb.chan_mode_opt = LDB_SIN_DI0; + + ldb.ldb_di_clk[0] = clk_get(NULL, + "ldb_di0_clk"); + clk_set_rate(ldb.ldb_di_clk[0], pll4_rate/7); + clk_put(ldb.ldb_di_clk[0]); + + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_EN_TO_DI0, + ldb.control_reg); + } else { + ldb.chan_mode_opt = LDB_SIN_DI1; + + ldb.ldb_di_clk[1] = clk_get(NULL, + "ldb_di1_clk"); + clk_set_rate(ldb.ldb_di_clk[1], pll4_rate/7); + clk_put(ldb.ldb_di_clk[1]); + + __raw_writel((reg & ~LDB_CH1_MODE_MASK) | + LDB_CH1_MODE_EN_TO_DI1, + ldb.control_reg); + } + break; + case LDB_CHAN_MODE_SEP: + ldb.chan_mode_opt = LDB_SEP; + + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + clk_set_rate(ldb.ldb_di_clk[0], pll4_rate/7); + clk_put(ldb.ldb_di_clk[0]); + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + clk_set_rate(ldb.ldb_di_clk[1], pll4_rate/7); + clk_put(ldb.ldb_di_clk[1]); + + __raw_writel((reg & ~(LDB_CH0_MODE_MASK | + LDB_CH1_MODE_MASK)) | + LDB_CH0_MODE_EN_TO_DI0 | + LDB_CH1_MODE_EN_TO_DI1, + ldb.control_reg); + break; + case LDB_CHAN_MODE_DUL: + case LDB_CHAN_MODE_SPL: + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + if (parm.di == 0) { + if (parm.channel_mode == LDB_CHAN_MODE_DUL) { + ldb.chan_mode_opt = LDB_DUL_DI0; + clk_set_rate(ldb.ldb_di_clk[0], + pll4_rate/7); + } else { + ldb.chan_mode_opt = LDB_SPL_DI0; + clk_set_rate(ldb.ldb_di_clk[0], + 2*pll4_rate/7); + clk_set_rate(ldb.ldb_di_clk[1], + 2*pll4_rate/7); + reg = __raw_readl(ldb.control_reg); + __raw_writel(reg | LDB_SPLIT_MODE_EN, + ldb.control_reg); + } + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~(LDB_CH0_MODE_MASK | + LDB_CH1_MODE_MASK)) | + LDB_CH0_MODE_EN_TO_DI0 | + LDB_CH1_MODE_EN_TO_DI0, + ldb.control_reg); + } else { + if (parm.channel_mode == LDB_CHAN_MODE_DUL) { + ldb.chan_mode_opt = LDB_DUL_DI1; + clk_set_rate(ldb.ldb_di_clk[1], + pll4_rate/7); + } else { + ldb.chan_mode_opt = LDB_SPL_DI1; + clk_set_rate(ldb.ldb_di_clk[0], + 2*pll4_rate/7); + clk_set_rate(ldb.ldb_di_clk[1], + 2*pll4_rate/7); + reg = __raw_readl(ldb.control_reg); + __raw_writel(reg | LDB_SPLIT_MODE_EN, + ldb.control_reg); + } + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~(LDB_CH0_MODE_MASK | + LDB_CH1_MODE_MASK)) | + LDB_CH0_MODE_EN_TO_DI1 | + LDB_CH1_MODE_EN_TO_DI1, + ldb.control_reg); + } + clk_put(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[1]); + break; + default: + ret = -EINVAL; + break; + } + spin_unlock(&ldb_lock); + break; + } + case LDB_ENABLE: + { + int ipu_di; + + if (copy_from_user(&ipu_di, (int *) arg, sizeof(int))) + return -EFAULT; + + ldb_enable(ipu_di); + break; + } + case LDB_DISABLE: + { + int ipu_di; + + if (copy_from_user(&ipu_di, (int *) arg, sizeof(int))) + return -EFAULT; + + ldb_disable(ipu_di); + break; + } + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int mxc_ldb_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int mxc_ldb_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static int mxc_ldb_mmap(struct file *file, struct vm_area_struct *vma) +{ + return 0; +} + +static const struct file_operations mxc_ldb_fops = { + .owner = THIS_MODULE, + .open = mxc_ldb_open, + .mmap = mxc_ldb_mmap, + .release = mxc_ldb_release, + .ioctl = mxc_ldb_ioctl +}; + +/*! + * This function is called by the driver framework to initialize the LDB + * device. + * + * @param dev The device structure for the LDB passed in by the + * driver framework. + * + * @return Returns 0 on success or negative error code on error + */ +static int ldb_probe(struct platform_device *pdev) +{ + int ret = 0, i, ipu_di, ipu_di_pix_fmt[2]; + bool primary = false, find_1080p = false; + struct resource *res; + struct ldb_platform_data *plat_data = pdev->dev.platform_data; + mm_segment_t old_fs; + struct clk *ldb_clk_parent; + unsigned long ldb_clk_prate = 455000000; + struct fb_var_screeninfo *var[2]; + uint32_t reg; + struct device *temp; + int mxc_ldb_major; + const struct fb_videomode *mode; + struct class *mxc_ldb_class; + + if (g_enable_ldb == false) + return -ENODEV; + + spin_lock_init(&ldb_lock); + + g_ldb_dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) + return -ENODEV; + + memset(&ldb, 0, sizeof(struct ldb_data)); + enabled[0] = enabled[1] = false; + var[0] = var[1] = NULL; + if (g_boot_cmd) { + ldb.chan_mode_opt = g_chan_mode_opt; + ldb.chan_bit_map[0] = g_chan_bit_map[0]; + ldb.chan_bit_map[1] = g_chan_bit_map[1]; + } + + ldb.base_addr = res->start; + ldb_reg = ioremap(ldb.base_addr, res->end - res->start + 1); + ldb.control_reg = ldb_reg + 2; + + INIT_LIST_HEAD(&ldb.modelist); + for (i = 0; i < mxcfb_ldb_modedb_sz; i++) + fb_add_videomode(&mxcfb_ldb_modedb[i], &ldb.modelist); + + for (i = 0; i < num_registered_fb; i++) { + if (registered_fb[i]->var.vmode == FB_VMODE_NONINTERLACED) { + mode = fb_match_mode(®istered_fb[i]->var, + &ldb.modelist); + if (mode) { + dev_dbg(g_ldb_dev, "fb mode found\n"); + ldb.fbi[i] = registered_fb[i]; + fb_videomode_to_var(&ldb.fbi[i]->var, mode); + } else if (i == 0 && ldb.chan_mode_opt != LDB_SEP) { + continue; + } else { + dev_warn(g_ldb_dev, + "can't find video mode\n"); + goto err0; + } + /* + * Default ldb mode: + * 1080p: DI0 split, SPWG or DI1 split, SPWG + * others: single, SPWG + */ + if (g_boot_cmd == false) { + if (fb_mode_is_equal(mode, &mxcfb_ldb_modedb[0])) { + if (strcmp(ldb.fbi[i]->fix.id, + "DISP3 BG") == 0) { + ldb.chan_mode_opt = LDB_SPL_DI0; + dev_warn(g_ldb_dev, + "default di0 split mode\n"); + } else if (strcmp(ldb.fbi[i]->fix.id, + "DISP3 BG - DI1") == 0) { + ldb.chan_mode_opt = LDB_SPL_DI1; + dev_warn(g_ldb_dev, + "default di1 split mode\n"); + } + ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG; + ldb.chan_bit_map[1] = LDB_BIT_MAP_SPWG; + find_1080p = true; + } else if (!find_1080p) { + if (strcmp(ldb.fbi[i]->fix.id, + "DISP3 BG") == 0) { + ldb.chan_mode_opt = LDB_SIN_DI0; + ldb.chan_bit_map[0] = LDB_BIT_MAP_SPWG; + dev_warn(g_ldb_dev, + "default di0 single mode\n"); + } else if (strcmp(ldb.fbi[i]->fix.id, + "DISP3 BG - DI1") == 0) { + ldb.chan_mode_opt = LDB_SIN_DI1; + ldb.chan_bit_map[1] = LDB_BIT_MAP_SPWG; + dev_warn(g_ldb_dev, + "default di1 single mode\n"); + } + } + } + + acquire_console_sem(); + fb_blank(ldb.fbi[i], FB_BLANK_POWERDOWN); + release_console_sem(); + + if (i == 0) + primary = true; + + if (ldb.fbi[1] != NULL || ldb.chan_mode_opt != LDB_SEP) + break; + } + } + + /* + * We cannot support two LVDS panel with different pixel clock rates + * except that one's pixel clock rate is two times of the others'. + */ + if (ldb.fbi[1] && ldb.fbi[0] != NULL) { + if (ldb.fbi[0]->var.pixclock != ldb.fbi[1]->var.pixclock && + ldb.fbi[0]->var.pixclock != 2 * ldb.fbi[1]->var.pixclock && + ldb.fbi[1]->var.pixclock != 2 * ldb.fbi[0]->var.pixclock) + return -EINVAL; + } + + ldb.bgref_rmode = plat_data->ext_ref; + ldb.lvds_bg_reg = regulator_get(&pdev->dev, plat_data->lvds_bg_reg); + if (!IS_ERR(ldb.lvds_bg_reg)) { + regulator_set_voltage(ldb.lvds_bg_reg, 2500000, 2500000); + regulator_enable(ldb.lvds_bg_reg); + } + + for (i = 0; i < 2; i++) { + if (ldb.fbi[i] != NULL) { + if (strcmp(ldb.fbi[i]->fix.id, "DISP3 BG") == 0) + ipu_di = 0; + else if (strcmp(ldb.fbi[i]->fix.id, "DISP3 BG - DI1") + == 0) + ipu_di = 1; + else { + dev_err(g_ldb_dev, "Wrong framebuffer\n"); + goto err0; + } + + var[ipu_di] = &ldb.fbi[i]->var; + if (ldb.fbi[i]->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + ldb.fbi[i]->fbops->fb_ioctl(ldb.fbi[i], + MXCFB_GET_DIFMT, + (unsigned long)&(ipu_di_pix_fmt[ipu_di])); + set_fs(old_fs); + } else { + dev_err(g_ldb_dev, "Can't get framebuffer " + "information\n"); + goto err0; + } + + if (!valid_mode(ipu_di_pix_fmt[ipu_di])) { + dev_err(g_ldb_dev, "Unsupport pixel format " + "for ldb input\n"); + goto err0; + } + + reg = __raw_readl(ldb.control_reg); + if (var[ipu_di]->sync & FB_SYNC_VERT_HIGH_ACT) { + if (ipu_di == 0) + __raw_writel((reg & + ~LDB_DI0_VS_POL_MASK) | + LDB_DI0_VS_POL_ACT_HIGH, + ldb.control_reg); + else + __raw_writel((reg & + ~LDB_DI1_VS_POL_MASK) | + LDB_DI1_VS_POL_ACT_HIGH, + ldb.control_reg); + } else { + if (ipu_di == 0) + __raw_writel((reg & + ~LDB_DI0_VS_POL_MASK) | + LDB_DI0_VS_POL_ACT_LOW, + ldb.control_reg); + else + __raw_writel((reg & + ~LDB_DI1_VS_POL_MASK) | + LDB_DI1_VS_POL_ACT_LOW, + ldb.control_reg); + } + + /* TODO:Set the correct pll4 rate for all situations */ + if (ipu_di == 1) { + ldb.ldb_di_clk[1] = + clk_get(&pdev->dev, "ldb_di1_clk"); + ldb_clk_parent = + clk_get_parent(ldb.ldb_di_clk[1]); + clk_set_rate(ldb_clk_parent, ldb_clk_prate); + clk_put(ldb.ldb_di_clk[1]); + } else { + ldb.ldb_di_clk[0] = + clk_get(&pdev->dev, "ldb_di0_clk"); + ldb_clk_parent = + clk_get_parent(ldb.ldb_di_clk[0]); + clk_set_rate(ldb_clk_parent, ldb_clk_prate); + clk_put(ldb.ldb_di_clk[0]); + } + } + } + + reg = __raw_readl(ldb.control_reg); + if (ldb.bgref_rmode == LDB_EXT_REF) + __raw_writel((reg & ~LDB_BGREF_RMODE_MASK) | + LDB_BGREF_RMODE_EXT, ldb.control_reg); + else + __raw_writel((reg & ~LDB_BGREF_RMODE_MASK) | + LDB_BGREF_RMODE_INT, ldb.control_reg); + + switch (ldb.chan_mode_opt) { + case LDB_SIN_DI0: + if (var[0] == NULL) { + dev_err(g_ldb_dev, "Can't find framebuffer on DI0\n"); + break; + } + + reg = __raw_readl(ldb.control_reg); + if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) | + LDB_DATA_WIDTH_CH0_24, + ldb.control_reg); + else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) | + LDB_DATA_WIDTH_CH0_18, + ldb.control_reg); + + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG) + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_JEIDA, + ldb.control_reg); + + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7); + clk_enable(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[0]); + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~LDB_CH0_MODE_MASK) | + LDB_CH0_MODE_EN_TO_DI0, ldb.control_reg); + ldb.ch_working[0] = true; + break; + case LDB_SIN_DI1: + if (var[1] == NULL) { + dev_err(g_ldb_dev, "Can't find framebuffer on DI1\n"); + break; + } + + reg = __raw_readl(ldb.control_reg); + if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) | + LDB_DATA_WIDTH_CH1_24, + ldb.control_reg); + else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) | + LDB_DATA_WIDTH_CH1_18, + ldb.control_reg); + + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG) + __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) | + LDB_BIT_MAP_CH1_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) | + LDB_BIT_MAP_CH1_JEIDA, + ldb.control_reg); + + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7); + clk_enable(ldb.ldb_di_clk[1]); + clk_put(ldb.ldb_di_clk[1]); + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~LDB_CH1_MODE_MASK) | + LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg); + ldb.ch_working[1] = true; + break; + case LDB_SEP: + if (var[0] == NULL || var[1] == NULL) { + dev_err(g_ldb_dev, "Can't find framebuffers on DI0/1\n"); + break; + } + + reg = __raw_readl(ldb.control_reg); + if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) | + LDB_DATA_WIDTH_CH0_24, + ldb.control_reg); + else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH0_MASK) | + LDB_DATA_WIDTH_CH0_18, + ldb.control_reg); + reg = __raw_readl(ldb.control_reg); + if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) | + LDB_DATA_WIDTH_CH1_24, + ldb.control_reg); + else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18) + __raw_writel((reg & ~LDB_DATA_WIDTH_CH1_MASK) | + LDB_DATA_WIDTH_CH1_18, + ldb.control_reg); + + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG) + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_JEIDA, + ldb.control_reg); + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG) + __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) | + LDB_BIT_MAP_CH1_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) | + LDB_BIT_MAP_CH1_JEIDA, + ldb.control_reg); + + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7); + clk_enable(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[0]); + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7); + clk_enable(ldb.ldb_di_clk[1]); + clk_put(ldb.ldb_di_clk[1]); + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~(LDB_CH0_MODE_MASK | + LDB_CH1_MODE_MASK)) | + LDB_CH0_MODE_EN_TO_DI0 | + LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg); + ldb.ch_working[0] = true; + ldb.ch_working[1] = true; + break; + case LDB_DUL_DI0: + case LDB_SPL_DI0: + if (var[0] == NULL) { + dev_err(g_ldb_dev, "Can't find framebuffer on DI0\n"); + break; + } + + reg = __raw_readl(ldb.control_reg); + if (bits_per_pixel(ipu_di_pix_fmt[0]) == 24) + __raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK | + LDB_DATA_WIDTH_CH1_MASK)) | + LDB_DATA_WIDTH_CH0_24 | + LDB_DATA_WIDTH_CH1_24, + ldb.control_reg); + else if (bits_per_pixel(ipu_di_pix_fmt[0]) == 18) + __raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK | + LDB_DATA_WIDTH_CH1_MASK)) | + LDB_DATA_WIDTH_CH0_18 | + LDB_DATA_WIDTH_CH1_18, + ldb.control_reg); + + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG) + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_JEIDA, + ldb.control_reg); + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG) + __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) | + LDB_BIT_MAP_CH1_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) | + LDB_BIT_MAP_CH1_JEIDA, + ldb.control_reg); + + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_mode_opt == LDB_SPL_DI0) + __raw_writel(reg | LDB_SPLIT_MODE_EN, + ldb.control_reg); + + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + if (ldb.chan_mode_opt == LDB_DUL_DI0) { + clk_set_rate(ldb.ldb_di_clk[0], ldb_clk_prate/7); + } else { + clk_set_rate(ldb.ldb_di_clk[0], 2*ldb_clk_prate/7); + clk_set_rate(ldb.ldb_di_clk[1], 2*ldb_clk_prate/7); + } + clk_enable(ldb.ldb_di_clk[0]); + clk_enable(ldb.ldb_di_clk[1]); + clk_put(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[1]); + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~(LDB_CH0_MODE_MASK | + LDB_CH1_MODE_MASK)) | + LDB_CH0_MODE_EN_TO_DI0 | + LDB_CH1_MODE_EN_TO_DI0, ldb.control_reg); + ldb.ch_working[0] = true; + ldb.ch_working[1] = true; + break; + case LDB_DUL_DI1: + case LDB_SPL_DI1: + if (var[1] == NULL) { + dev_err(g_ldb_dev, "Can't find framebuffer on DI1\n"); + break; + } + + reg = __raw_readl(ldb.control_reg); + if (bits_per_pixel(ipu_di_pix_fmt[1]) == 24) + __raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK | + LDB_DATA_WIDTH_CH1_MASK)) | + LDB_DATA_WIDTH_CH0_24 | + LDB_DATA_WIDTH_CH1_24, + ldb.control_reg); + else if (bits_per_pixel(ipu_di_pix_fmt[1]) == 18) + __raw_writel((reg & ~(LDB_DATA_WIDTH_CH0_MASK | + LDB_DATA_WIDTH_CH1_MASK)) | + LDB_DATA_WIDTH_CH0_18 | + LDB_DATA_WIDTH_CH1_18, + ldb.control_reg); + + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_bit_map[0] == LDB_BIT_MAP_SPWG) + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH0_MASK) | + LDB_BIT_MAP_CH0_JEIDA, + ldb.control_reg); + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_bit_map[1] == LDB_BIT_MAP_SPWG) + __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) | + LDB_BIT_MAP_CH1_SPWG, + ldb.control_reg); + else + __raw_writel((reg & ~LDB_BIT_MAP_CH1_MASK) | + LDB_BIT_MAP_CH1_JEIDA, + ldb.control_reg); + + reg = __raw_readl(ldb.control_reg); + if (ldb.chan_mode_opt == LDB_SPL_DI1) + __raw_writel(reg | LDB_SPLIT_MODE_EN, + ldb.control_reg); + + ldb.ldb_di_clk[0] = clk_get(NULL, "ldb_di0_clk"); + ldb.ldb_di_clk[1] = clk_get(NULL, "ldb_di1_clk"); + if (ldb.chan_mode_opt == LDB_DUL_DI1) { + clk_set_rate(ldb.ldb_di_clk[1], ldb_clk_prate/7); + } else { + clk_set_rate(ldb.ldb_di_clk[0], 2*ldb_clk_prate/7); + clk_set_rate(ldb.ldb_di_clk[1], 2*ldb_clk_prate/7); + } + clk_enable(ldb.ldb_di_clk[0]); + clk_enable(ldb.ldb_di_clk[1]); + clk_put(ldb.ldb_di_clk[0]); + clk_put(ldb.ldb_di_clk[1]); + + reg = __raw_readl(ldb.control_reg); + __raw_writel((reg & ~(LDB_CH0_MODE_MASK | + LDB_CH1_MODE_MASK)) | + LDB_CH0_MODE_EN_TO_DI1 | + LDB_CH1_MODE_EN_TO_DI1, ldb.control_reg); + ldb.ch_working[0] = true; + ldb.ch_working[1] = true; + break; + default: + break; + } + + mxc_ldb_major = register_chrdev(0, "mxc_ldb", &mxc_ldb_fops); + if (mxc_ldb_major < 0) { + dev_err(g_ldb_dev, "Unable to register MXC LDB as a char " + "device\n"); + ret = mxc_ldb_major; + goto err0; + } + + mxc_ldb_class = class_create(THIS_MODULE, "mxc_ldb"); + if (IS_ERR(mxc_ldb_class)) { + dev_err(g_ldb_dev, "Unable to create class for MXC LDB\n"); + ret = PTR_ERR(mxc_ldb_class); + goto err1; + } + + temp = device_create(mxc_ldb_class, NULL, MKDEV(mxc_ldb_major, 0), + NULL, "mxc_ldb"); + if (IS_ERR(temp)) { + dev_err(g_ldb_dev, "Unable to create class device for " + "MXC LDB\n"); + ret = PTR_ERR(temp); + goto err2; + } + + ret = fb_register_client(&nb); + if (ret < 0) + goto err2; + + if (primary && ldb.fbi[0] != NULL) { + acquire_console_sem(); + fb_blank(ldb.fbi[0], FB_BLANK_UNBLANK); + release_console_sem(); + fb_show_logo(ldb.fbi[0], 0); + } + + return ret; +err2: + class_destroy(mxc_ldb_class); +err1: + unregister_chrdev(mxc_ldb_major, "mxc_ldb"); +err0: + iounmap(ldb_reg); + return ret; +} + +static int ldb_remove(struct platform_device *pdev) +{ + int i; + + __raw_writel(0, ldb.control_reg); + + for (i = 0; i < 2; i++) { + if (ldb.ch_working[i]) { + ldb.ldb_di_clk[i] = clk_get(NULL, + i ? "ldb_di1_clk" : "ldb_di0_clk"); + clk_disable(ldb.ldb_di_clk[i]); + clk_put(ldb.ldb_di_clk[i]); + ldb.ch_working[i] = false; + } + } + + fb_unregister_client(&nb); + return 0; +} + +static int ldb_suspend(struct platform_device *pdev, pm_message_t state) +{ + switch (ldb.chan_mode_opt) { + case LDB_SIN_DI0: + case LDB_DUL_DI0: + case LDB_SPL_DI0: + ldb_disable(0); + break; + case LDB_SIN_DI1: + case LDB_DUL_DI1: + case LDB_SPL_DI1: + ldb_disable(1); + break; + case LDB_SEP: + ldb_disable(0); + ldb_disable(1); + break; + default: + break; + } + return 0; +} + +static int ldb_resume(struct platform_device *pdev) +{ + switch (ldb.chan_mode_opt) { + case LDB_SIN_DI0: + case LDB_DUL_DI0: + case LDB_SPL_DI0: + ldb_enable(0); + break; + case LDB_SIN_DI1: + case LDB_DUL_DI1: + case LDB_SPL_DI1: + ldb_enable(1); + break; + case LDB_SEP: + ldb_enable(0); + ldb_enable(1); + break; + default: + break; + } + return 0; +} + +static struct platform_driver mxcldb_driver = { + .driver = { + .name = "mxc_ldb", + }, + .probe = ldb_probe, + .remove = ldb_remove, + .suspend = ldb_suspend, + .resume = ldb_resume, +}; + +/* + * Parse user specified options (`ldb=') + * example: + * ldb=single(separate, dual or split),(di=0 or di=1), + * ch0_map=SPWG or JEIDA,ch1_map=SPWG or JEIDA + * + */ +static int __init ldb_setup(char *options) +{ + g_enable_ldb = true; + + if (!strlen(options)) + return 1; + else if (!strsep(&options, "=")) + return 1; + + if (!strncmp(options, "single", 6)) { + strsep(&options, ","); + if (!strncmp(options, "di=0", 4)) + g_chan_mode_opt = LDB_SIN_DI0; + else + g_chan_mode_opt = LDB_SIN_DI1; + } else if (!strncmp(options, "separate", 8)) { + g_chan_mode_opt = LDB_SEP; + } else if (!strncmp(options, "dual", 4)) { + strsep(&options, ","); + if (!strncmp(options, "di=", 3)) { + if (simple_strtoul(options + 3, NULL, 0) == 0) + g_chan_mode_opt = LDB_DUL_DI0; + else + g_chan_mode_opt = LDB_DUL_DI1; + } + } else if (!strncmp(options, "split", 5)) { + strsep(&options, ","); + if (!strncmp(options, "di=", 3)) { + if (simple_strtoul(options + 3, NULL, 0) == 0) + g_chan_mode_opt = LDB_SPL_DI0; + else + g_chan_mode_opt = LDB_SPL_DI1; + } + } else + return 1; + + if ((strsep(&options, ",") != NULL) && + !strncmp(options, "ch0_map=", 8)) { + if (!strncmp(options + 8, "SPWG", 4)) + g_chan_bit_map[0] = LDB_BIT_MAP_SPWG; + else + g_chan_bit_map[0] = LDB_BIT_MAP_JEIDA; + } + + if (!(g_chan_mode_opt == LDB_SIN_DI0 || + g_chan_mode_opt == LDB_SIN_DI1) && + (strsep(&options, ",") != NULL) && + !strncmp(options, "ch1_map=", 8)) { + if (!strncmp(options + 8, "SPWG", 4)) + g_chan_bit_map[1] = LDB_BIT_MAP_SPWG; + else + g_chan_bit_map[1] = LDB_BIT_MAP_JEIDA; + } + + g_boot_cmd = true; + + return 1; +} +__setup("ldb", ldb_setup); + +static int __init ldb_init(void) +{ + int ret; + + ret = platform_driver_register(&mxcldb_driver); + return 0; +} + +static void __exit ldb_uninit(void) +{ + platform_driver_unregister(&mxcldb_driver); +} + +module_init(ldb_init); +module_exit(ldb_uninit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC LDB driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/mx2fb.c b/drivers/video/mxc/mx2fb.c new file mode 100644 index 000000000000..d1daf9d1ea16 --- /dev/null +++ b/drivers/video/mxc/mx2fb.c @@ -0,0 +1,1349 @@ +/* + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer_MX27 Framebuffer Driver for MX27. + */ + +/*! + * @file mx2fb.c + * + * @brief Frame buffer driver for MX27 ADS. + * + * @ingroup Framebuffer_MX27 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mx2fb.h" + +#define MX2FB_TYPE_BG 0 +#define MX2FB_TYPE_GW 1 + +extern void gpio_lcdc_active(void); +extern void gpio_lcdc_inactive(void); +extern void board_power_lcd(int on); + +static char *fb_mode; +static int fb_enabled; +static unsigned long default_bpp = 16; +static ATOMIC_NOTIFIER_HEAD(mx2fb_notifier_list); +static struct clk *lcdc_clk; +/*! + * @brief Structure containing the MX2 specific framebuffer information. + */ +struct mx2fb_info { + int type; + char *id; + int registered; + int blank; + unsigned long pseudo_palette[16]; +}; + +/* Framebuffer APIs */ +static int mx2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info); +static int mx2fb_set_par(struct fb_info *info); +static int mx2fb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info); +static int mx2fb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info); +static int mx2fb_blank(int blank_mode, struct fb_info *info); +static int mx2fb_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg); + +/* Driver entries */ +int __init mx2fb_init(void); +void __exit mx2fb_exit(void); +#ifndef MODULE +static int __init mx2fb_setup(char *); +#endif + +/* Internal functions */ +static int __init _init_fbinfo(struct fb_info *info, + struct platform_device *pdev); +static int __init _install_fb(struct fb_info *info, + struct platform_device *pdev); +static void __exit _uninstall_fb(struct fb_info *info); +static int _map_video_memory(struct fb_info *info); +static void _unmap_video_memory(struct fb_info *info); +static void _set_fix(struct fb_info *info); +static void _enable_lcdc(struct fb_info *info); +static void _disable_lcdc(struct fb_info *info); +static void _enable_graphic_window(struct fb_info *info); +static void _disable_graphic_window(struct fb_info *info); +static void _update_lcdc(struct fb_info *info); +static void _request_irq(void); +static void _free_irq(void); + +#ifdef CONFIG_PM +static int mx2fb_suspend(struct platform_device *pdev, pm_message_t state); +static int mx2fb_resume(struct platform_device *pdev); +#else +#define mx2fb_suspend 0 +#define mx2fb_resume 0 +#endif + +static int mx2fb_probe(struct platform_device *pdev); + +#ifdef CONFIG_FB_MXC_TVOUT +#include +/* + * FIXME: VGA mode is not defined by video_encoder.h + * while FS453 supports VGA output. + */ +#ifndef VIDEO_ENCODER_VGA +#define VIDEO_ENCODER_VGA 32 +#endif + +#define MODE_PAL "TV-PAL" +#define MODE_NTSC "TV-NTSC" +#define MODE_VGA "TV-VGA" + +extern int fs453_ioctl(unsigned int cmd, void *arg); +#endif + +struct mx2fb_info mx2fbi_bg = { + .type = MX2FB_TYPE_BG, + .id = "DISP0 BG", + .registered = 0, +}; + +static struct mx2fb_info mx2fbi_gw = { + .type = MX2FB_TYPE_GW, + .id = "DISP0 FG", + .registered = 0, +}; + +/*! Current graphic window information */ +static struct fb_gwinfo g_gwinfo = { + .enabled = 0, + .alpha_value = 255, + .ck_enabled = 0, + .ck_red = 0, + .ck_green = 0, + .ck_blue = 0, + .xpos = 0, + .ypos = 0, +}; + +/*! + * @brief Framebuffer information structures. + * There are up to 3 framebuffers: background, TVout, and graphic window. + * If graphic window is configured, it must be the last framebuffer. + */ +static struct fb_info mx2fb_info[] = { + {.par = &mx2fbi_bg}, + {.par = &mx2fbi_gw}, +}; + +/*! + * @brief This structure contains pointers to the power management + * callback functions. + */ +static struct platform_driver mx2fb_driver = { + .driver = { + .name = "mxc_sdc_fb", + .owner = THIS_MODULE, + .bus = &platform_bus_type, + }, + .probe = mx2fb_probe, + .suspend = mx2fb_suspend, + .resume = mx2fb_resume, +}; + +/*! + * @brief Framebuffer file operations + */ +static struct fb_ops mx2fb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mx2fb_check_var, + .fb_set_par = mx2fb_set_par, + .fb_setcolreg = mx2fb_setcolreg, + .fb_blank = mx2fb_blank, + .fb_pan_display = mx2fb_pan_display, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_ioctl = mx2fb_ioctl, +}; + +/*! + * @brief Validates a var passed in. + * + * @param var Frame buffer variable screen structure + * @param info Frame buffer structure that represents a single frame buffer + * + * @return Negative errno on error, or zero on success. + * + * Checks to see if the hardware supports the state requested by var passed + * in. This function does not alter the hardware state! If the var passed in + * is slightly off by what the hardware can support then we alter the var + * PASSED in to what we can do. If the hardware doesn't support mode change + * a -EINVAL will be returned by the upper layers. + * + */ +static int mx2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + unsigned long htotal, vtotal; + + if (var->xres_virtual < var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if (var->xoffset < 0) + var->xoffset = 0; + + if (var->yoffset < 0) + var->yoffset = 0; + + if (var->xoffset + info->var.xres > info->var.xres_virtual) + var->xoffset = info->var.xres_virtual - info->var.xres; + + if (var->yoffset + info->var.yres > info->var.yres_virtual) + var->yoffset = info->var.yres_virtual - info->var.yres; + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16)) { + var->bits_per_pixel = default_bpp; + } + + switch (var->bits_per_pixel) { + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + if (var->pixclock < 1000) { + htotal = var->xres + var->right_margin + var->hsync_len + + var->left_margin; + vtotal = var->yres + var->lower_margin + var->vsync_len + + var->upper_margin; + var->pixclock = (vtotal * htotal * 6UL) / 100UL; + var->pixclock = KHZ2PICOS(var->pixclock); + dev_dbg(info->device, + "pixclock set for 60Hz refresh = %u ps\n", + var->pixclock); + } + + var->height = -1; + var->width = -1; + var->grayscale = 0; + + /* Copy nonstd field to/from sync for fbset usage */ + var->sync |= var->nonstd; + var->nonstd |= var->sync; + + return 0; +} + +/*! + * @brief Alters the hardware state. + * + * @param info Frame buffer structure that represents a single frame buffer + * + * @return Zero on success others on failure + * + * Using the fb_var_screeninfo in fb_info we set the resolution of this + * particular framebuffer. This function alters the fb_fix_screeninfo stored + * in fb_info. It doesn't not alter var in fb_info since we are using that + * data. This means we depend on the data in var inside fb_info to be + * supported by the hardware. mx2fb_check_var is always called before + * mx2fb_set_par to ensure this. + */ +static int mx2fb_set_par(struct fb_info *info) +{ + unsigned long len; + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + _set_fix(info); + + len = info->var.yres_virtual * info->fix.line_length; + if (len > info->fix.smem_len) { + if (info->fix.smem_start) + _unmap_video_memory(info); + + /* Memory allocation for framebuffer */ + if (_map_video_memory(info)) { + dev_err(info->device, "Unable to allocate fb memory\n"); + return -ENOMEM; + } + } + + _update_lcdc(info); + if (info->fbops->fb_blank) + info->fbops->fb_blank(mx2fbi->blank, info); + + return 0; +} + +/*! + * @brief Sets a color register. + * + * @param regno Which register in the CLUT we are programming + * @param red The red value which can be up to 16 bits wide + * @param green The green value which can be up to 16 bits wide + * @param blue The blue value which can be up to 16 bits wide. + * @param transp If supported the alpha value which can be up to + * 16 bits wide. + * @param info Frame buffer info structure + * + * @return Negative errno on error, or zero on success. + * + * Set a single color register. The values supplied have a 16 bit magnitude + * which needs to be scaled in this function for the hardware. Things to take + * into consideration are how many color registers, if any, are supported with + * the current color visual. With truecolor mode no color palettes are + * supported. Here a psuedo palette is created which we store the value in + * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited + * color palette. + */ +static int mx2fb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, struct fb_info *info) +{ + int ret = 1; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (info->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + switch (info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = info->pseudo_palette; + u32 v; + +#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16) + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); +#undef CNVT_TOHW + + v = (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + + pal[regno] = v; + ret = 0; + } + break; + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + + return ret; +} + +/*! + * @brief Pans the display. + * + * @param var Frame buffer variable screen structure + * @param info Frame buffer structure that represents a single frame buffer + * + * @return Negative errno on error, or zero on success. + * + * Pan (or wrap, depending on the `vmode' field) the display using the + * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values + * don't fit, return -EINVAL. + */ +static int mx2fb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + if ((info->var.xoffset == var->xoffset) && + (info->var.yoffset == var->yoffset)) { + return 0; /* No change, do nothing */ + } + + if (var->xoffset < 0 || var->yoffset < 0 + || var->xoffset + info->var.xres > info->var.xres_virtual + || var->yoffset + info->var.yres > info->var.yres_virtual) + return -EINVAL; + + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + + _update_lcdc(info); + + if (var->vmode & FB_VMODE_YWRAP) + info->var.vmode |= FB_VMODE_YWRAP; + else + info->var.vmode &= ~FB_VMODE_YWRAP; + + return 0; +} + +/*! + * @brief Blanks the display. + * + * @param blank_mode The blank mode we want. + * @param info Frame buffer structure that represents a single frame buffer + * + * @return Negative errno on error, or zero on success. + * + * Blank the screen if blank_mode != 0, else unblank. Return 0 if blanking + * succeeded, != 0 if un-/blanking failed. + * blank_mode == 2: suspend vsync + * blank_mode == 3: suspend hsync + * blank_mode == 4: powerdown + */ +static int mx2fb_blank(int blank_mode, struct fb_info *info) +{ + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + dev_dbg(info->device, "blank mode = %d\n", blank_mode); + + mx2fbi->blank = blank_mode; + + switch (blank_mode) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + _disable_lcdc(info); + break; + case FB_BLANK_UNBLANK: + _enable_lcdc(info); + break; + } + + return 0; +} + +/*! + * @brief Ioctl function to support customized ioctl operations. + * + * @param info Framebuffer structure that represents a single frame buffer + * @param cmd The command number + * @param arg Argument which depends on cmd + * + * @return Negative errno on error, or zero on success. + */ +static int mx2fb_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg) +{ + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + struct mx2fb_gbl_alpha ga; + struct mx2fb_color_key ck; + + switch (cmd) { + case MX2FB_SET_GBL_ALPHA: + if (mx2fbi->type != MX2FB_TYPE_GW) + return -ENODEV; + + if (!arg) + return -EINVAL; + + /* set graphic window information */ + if (copy_from_user((void *)&ga, (void *)arg, sizeof(ga))) + return -EFAULT; + + g_gwinfo.alpha_value = ga.alpha; + + if (g_gwinfo.enabled) + _enable_graphic_window(info); + else + _disable_graphic_window(info); + break; + case MX2FB_SET_CLR_KEY: + if (mx2fbi->type != MX2FB_TYPE_GW) + return -ENODEV; + + if (!arg) + return -EINVAL; + + /* set graphic window information */ + if (copy_from_user((void *)&ck, (void *)arg, sizeof(ck))) + return -EFAULT; + + g_gwinfo.ck_enabled = ck.enable; + g_gwinfo.ck_red = (ck.color_key & 0x003F0000) >> 16; + g_gwinfo.ck_green = (ck.color_key & 0x00003F00) >> 8; + g_gwinfo.ck_blue = ck.color_key & 0x0000003F; + + if (g_gwinfo.enabled) + _enable_graphic_window(info); + else + _disable_graphic_window(info); + break; + case FBIOGET_GWINFO: + if (mx2fbi->type != MX2FB_TYPE_GW) + return -ENODEV; + + if (!arg) + return -EINVAL; + + /* get graphic window information */ + if (copy_to_user((void *)arg, (void *)&g_gwinfo, + sizeof(g_gwinfo))) + return -EFAULT; + break; + case FBIOPUT_GWINFO: + if (mx2fbi->type != MX2FB_TYPE_GW) + return -ENODEV; + + if (!arg) + return -EINVAL; + + /* set graphic window information */ + if (copy_from_user((void *)&g_gwinfo, (void *)arg, + sizeof(g_gwinfo))) + return -EFAULT; + + if (g_gwinfo.enabled) + _enable_graphic_window(info); + else + _disable_graphic_window(info); + break; +#ifdef CONFIG_FB_MXC_TVOUT + case ENCODER_GET_CAPABILITIES:{ + int ret; + struct video_encoder_capability cap; + + if (mx2fbi->type != MX2FB_TYPE_BG) + return -ENODEV; + + ret = fs453_ioctl(cmd, &cap); + if (ret) + return ret; + + if (copy_to_user((void *)arg, &cap, sizeof(cap))) + return -EFAULT; + break; + } + case ENCODER_SET_NORM:{ + int ret; + unsigned long mode; + char *smode; + struct fb_var_screeninfo var; + + if (mx2fbi->type != MX2FB_TYPE_BG) + return -ENODEV; + + if (copy_from_user(&mode, (void *)arg, sizeof(mode))) + return -EFAULT; + ret = fs453_ioctl(cmd, &mode); + if (ret) + return ret; + + if (mode == VIDEO_ENCODER_PAL) + smode = MODE_PAL; + else if (mode == VIDEO_ENCODER_NTSC) + smode = MODE_NTSC; + else + smode = MODE_VGA; + + var = info->var; + var.nonstd = 0; + ret = fb_find_mode(&var, info, smode, mxcfb_modedb, + mxcfb_modedb_sz, NULL, default_bpp); + /* check for specified mode not found */ + if ((ret != 1) && (ret != 2)) + return -ENODEV; + + info->var = var; + fb_mode = smode; + return mx2fb_set_par(info); + } + case ENCODER_SET_INPUT: + case ENCODER_SET_OUTPUT: + case ENCODER_ENABLE_OUTPUT:{ + unsigned long varg; + + if (mx2fbi->type != MX2FB_TYPE_BG) + return -ENODEV; + + if (copy_from_user(&varg, (void *)arg, sizeof(varg))) + return -EFAULT; + return fs453_ioctl(cmd, &varg); + } +#endif + default: + dev_dbg(info->device, "Unknown ioctl command (0x%08X)\n", cmd); + return -EINVAL; + } + + return 0; +} + +/*! + * @brief Set fixed framebuffer parameters based on variable settings. + * + * @param info framebuffer information pointer + * @return Negative errno on error, or zero on success. + */ +static void _set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + strncpy(fix->id, mx2fbi->id, strlen(mx2fbi->id)); + fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 1; + fix->ypanstep = 1; +} + +/*! + * @brief Initialize framebuffer information structure. + * + * @param info framebuffer information pointer + * @param pdev pointer to struct device + * @return Negative errno on error, or zero on success. + */ +static int __init _init_fbinfo(struct fb_info *info, + struct platform_device *pdev) +{ + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + info->device = &pdev->dev; + info->var.activate = FB_ACTIVATE_NOW; + info->fbops = &mx2fb_ops; + info->flags = FBINFO_FLAG_DEFAULT; + info->pseudo_palette = &mx2fbi->pseudo_palette; + + /* Allocate colormap */ + fb_alloc_cmap(&info->cmap, 16, 0); + + return 0; +} + +/*! + * @brief Install framebuffer into the system. + * + * @param info framebuffer information pointer + * @param pdev pointer to struct device + * @return Negative errno on error, or zero on success. + */ +static int __init _install_fb(struct fb_info *info, + struct platform_device *pdev) +{ + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + if (_init_fbinfo(info, pdev)) + return -EINVAL; + + if (fb_mode == 0) + fb_mode = pdev->dev.platform_data; + + if (!fb_find_mode(&info->var, info, fb_mode, mxcfb_modedb, + mxcfb_modedb_sz, NULL, default_bpp)) { + fb_dealloc_cmap(&info->cmap); + return -EBUSY; + } + + /* Default Y virtual size is 2x panel size */ + /* info->var.yres_virtual = info->var.yres << 1; */ + + if (mx2fbi->type == MX2FB_TYPE_GW) + mx2fbi->blank = FB_BLANK_NORMAL; + else + mx2fbi->blank = FB_BLANK_UNBLANK; + + if (mx2fb_set_par(info)) { + fb_dealloc_cmap(&info->cmap); + return -EINVAL; + } + + if (register_framebuffer(info) < 0) { + _unmap_video_memory(info); + fb_dealloc_cmap(&info->cmap); + return -EINVAL; + } + + mx2fbi->registered = 1; + dev_info(info->device, "fb%d: %s fb device registered successfully.\n", + info->node, info->fix.id); + + return 0; +} + +/*! + * @brief Uninstall framebuffer from the system. + * + * @param info framebuffer information pointer + */ +static void __exit _uninstall_fb(struct fb_info *info) +{ + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + if (!mx2fbi->registered) + return; + + unregister_framebuffer(info); + _unmap_video_memory(info); + if (&info->cmap) + fb_dealloc_cmap(&info->cmap); + + mx2fbi->registered = 0; +} + +/*! + * @brief Allocate memory for framebuffer. + * + * @param info framebuffer information pointer + * @return Negative errno on error, or zero on success. + */ +static int _map_video_memory(struct fb_info *info) +{ + info->fix.smem_len = info->fix.line_length * info->var.yres_virtual; + info->screen_base = dma_alloc_coherent(0, + info->fix.smem_len, + (dma_addr_t *) &info->fix.smem_start, + GFP_DMA | GFP_KERNEL); + + if (info->screen_base == 0) { + dev_err(info->device, "Unable to allocate fb memory\n"); + return -EBUSY; + } + dev_dbg(info->device, "Allocated fb @ paddr=0x%08lX, size=%d.\n", + info->fix.smem_start, info->fix.smem_len); + + info->screen_size = info->fix.smem_len; + + /* Clear the screen */ + memset((char *)info->screen_base, 0, info->fix.smem_len); + + return 0; +} + +/*! + * @brief Release memory for framebuffer. + * @param info framebuffer information pointer + */ +static void _unmap_video_memory(struct fb_info *info) +{ + dma_free_coherent(0, info->fix.smem_len, info->screen_base, + (dma_addr_t) info->fix.smem_start); + + info->screen_base = 0; + info->fix.smem_start = 0; + info->fix.smem_len = 0; +} + +/*! + * @brief Enable LCD controller. + * @param info framebuffer information pointer + */ +static void _enable_lcdc(struct fb_info *info) +{ + static int first_enable = 1; + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + /* + * Graphic window can only be enabled while the HCLK to the LCDC + * is disabled. Once enabled it can subsequently be disabled and + * enabled without turning off the HCLK. + * The graphic window is enabled and then disabled here. So next + * time to enable graphic window the HCLK to LCDC does not need + * to be disabled, and the flicker (due to disabling of HCLK to + * LCDC) is avoided. + */ + if (first_enable) { + _enable_graphic_window(info); + _disable_graphic_window(info); + first_enable = 0; + } + + if (mx2fbi->type == MX2FB_TYPE_GW) + _enable_graphic_window(info); + else if (!fb_enabled) { + clk_enable(lcdc_clk); + gpio_lcdc_active(); + board_power_lcd(1); + fb_enabled++; +#ifdef CONFIG_FB_MXC_TVOUT + if (fb_mode) { + unsigned long mode = 0; + + if (strcmp(fb_mode, MODE_VGA) == 0) + mode = VIDEO_ENCODER_VGA; + else if (strcmp(fb_mode, MODE_NTSC) == 0) + mode = VIDEO_ENCODER_NTSC; + else if (strcmp(fb_mode, MODE_PAL) == 0) + mode = VIDEO_ENCODER_PAL; + if (mode) + fs453_ioctl(ENCODER_SET_NORM, &mode); + } +#endif + } +} + +/*! + * @brief Disable LCD controller. + * @param info framebuffer information pointer + */ +static void _disable_lcdc(struct fb_info *info) +{ + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + if (mx2fbi->type == MX2FB_TYPE_GW) + _disable_graphic_window(info); + else { + if (fb_enabled) { + gpio_lcdc_inactive(); + board_power_lcd(0); + clk_disable(lcdc_clk); + fb_enabled = 0; + } +#ifdef CONFIG_FB_MXC_TVOUT + if (fb_mode) { + int enable = 0; + + if ((strcmp(fb_mode, MODE_VGA) == 0) + || (strcmp(fb_mode, MODE_NTSC) == 0) + || (strcmp(fb_mode, MODE_PAL) == 0)) + fs453_ioctl(ENCODER_ENABLE_OUTPUT, &enable); + } +#endif + } +} + +/*! + * @brief Enable graphic window. + * @param info framebuffer information pointer + */ +static void _enable_graphic_window(struct fb_info *info) +{ + struct fb_var_screeninfo *var = &info->var; + + g_gwinfo.enabled = 1; + + g_gwinfo.base = (var->yoffset * var->xres_virtual + var->xoffset); + g_gwinfo.base *= (var->bits_per_pixel) / 8; + g_gwinfo.base += info->fix.smem_start; + + g_gwinfo.xres = var->xres; + g_gwinfo.yres = var->yres; + g_gwinfo.xres_virtual = var->xres_virtual; + + mx2_gw_set(&g_gwinfo); +} + +/*! + * @brief Disable graphic window. + * @param info framebuffer information pointer + */ +static void _disable_graphic_window(struct fb_info *info) +{ + unsigned long i = 0; + + g_gwinfo.enabled = 0; + + /* + * Set alpha value to zero and reduce gw size, otherwise the graphic + * window will not be able to be enabled again. + */ + __raw_writel(__raw_readl(LCDC_REG(LCDC_LGWCR)) & 0x00FFFFFF, + LCDC_REG(LCDC_LGWCR)); + __raw_writel(((16 >> 4) << 20) + 16, LCDC_REG(LCDC_LGWSR)); + while (i < 1000) + i++; + + /* Now disable graphic window */ + __raw_writel(__raw_readl(LCDC_REG(LCDC_LGWCR)) & ~0x00400000, + LCDC_REG(LCDC_LGWCR)); + + dev_dbg(info->device, "Graphic window disabled.\n"); +} + +/*! + * @brief Setup graphic window properties. + * @param gwinfo graphic window information pointer + */ +void mx2_gw_set(struct fb_gwinfo *gwinfo) +{ + int width, height, xpos, ypos; + int width_bg, height_bg; + /* Graphic window control register */ + unsigned long lgwcr = 0x00400000; + + if (!gwinfo->enabled) { + _disable_graphic_window(0); + return; + } + + /* Graphic window start address register */ + __raw_writel(gwinfo->base, LCDC_REG(LCDC_LGWSAR)); + + /* + * The graphic window width, height, x position and y position + * must be synced up width the background window, otherwise there + * may be flickering. + */ + width_bg = (__raw_readl(LCDC_REG(LCDC_LSR)) & 0x03F00000) >> 16; + height_bg = __raw_readl(LCDC_REG(LCDC_LSR)) & 0x000003FF; + + width = (gwinfo->xres > width_bg) ? width_bg : gwinfo->xres; + height = (gwinfo->yres > height_bg) ? height_bg : gwinfo->yres; + + xpos = gwinfo->xpos; + ypos = gwinfo->ypos; + + if (xpos + width > width_bg) + xpos = width_bg - width; + if (ypos + height > height_bg) + ypos = height_bg - height; + + /* Graphic window size register */ + __raw_writel(((width >> 4) << 20) + height, LCDC_REG(LCDC_LGWSR)); + + /* Graphic window virtual page width register */ + __raw_writel(gwinfo->xres_virtual >> 1, LCDC_REG(LCDC_LGWVPWR)); + + /* Graphic window position register */ + __raw_writel(((xpos & 0x000003FF) << 16) | (ypos & 0x000003FF), + LCDC_REG(LCDC_LGWPR)); + + /* Graphic window panning offset register */ + __raw_writel(0, LCDC_REG(LCDC_LGWPOR)); + + /* Graphic window DMA control register */ + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) + __raw_writel(0x00040060, LCDC_REG(LCDC_LGWDCR)); + else + __raw_writel(0x00020010, LCDC_REG(LCDC_LGWDCR)); + + /* Graphic window control register */ + lgwcr |= (gwinfo->alpha_value & 0x000000FF) << 24; + lgwcr |= gwinfo->ck_enabled ? 0x00800000 : 0; + lgwcr |= gwinfo->vs_reversed ? 0x00200000 : 0; + + /* + * Color keying value + * Todo: assume always use RGB565 + */ + lgwcr |= (gwinfo->ck_red & 0x0000003F) << 12; + lgwcr |= (gwinfo->ck_green & 0x0000003F) << 6; + lgwcr |= gwinfo->ck_blue & 0x0000003F; + + __raw_writel(lgwcr, LCDC_REG(LCDC_LGWCR)); + + pr_debug("Graphic window enabled.\n"); +} +EXPORT_SYMBOL(mx2_gw_set); + +/*! + * @brief Update LCDC registers + * @param info framebuffer information pointer + */ +static void _update_lcdc(struct fb_info *info) +{ + unsigned long base; + unsigned long perclk, pcd, pcr; + struct fb_var_screeninfo *var = &info->var; + struct mx2fb_info *mx2fbi = (struct mx2fb_info *)info->par; + + if (mx2fbi->type == MX2FB_TYPE_GW) { + _enable_graphic_window(info); + return; + } + + base = (var->yoffset * var->xres_virtual + var->xoffset); + base *= (var->bits_per_pixel) / 8; + base += info->fix.smem_start; + + /* Screen start address register */ + __raw_writel(base, LCDC_REG(LCDC_LSSAR)); + + /* Size register */ + dev_dbg(info->device, "xres = %d, yres = %d\n", + info->var.xres, info->var.yres); + __raw_writel(((info->var.xres >> 4) << 20) + info->var.yres, + LCDC_REG(LCDC_LSR)); + + /* Virtual page width register */ + __raw_writel(info->var.xres_virtual >> 1, LCDC_REG(LCDC_LVPWR)); + + /* To setup LCDC pixel clock */ + perclk = clk_round_rate(lcdc_clk, 134000000); + if (clk_set_rate(lcdc_clk, perclk)) { + printk(KERN_INFO "mx2fb: Unable to set clock to %lu\n", perclk); + perclk = clk_get_rate(lcdc_clk); + } + + /* Calculate pixel clock divider, and round to the nearest integer */ + pcd = (perclk * 8 / (PICOS2KHZ(var->pixclock) * 1000UL) + 4) / 8; + if (--pcd > 0x3F) + pcd = 0x3F; + + /* Panel configuration register */ + pcr = 0xFA008B80 | pcd; + pcr |= (var->sync & FB_SYNC_CLK_LAT_FALL) ? 0x00200000 : 0; + pcr |= (var->sync & FB_SYNC_DATA_INVERT) ? 0x01000000 : 0; + pcr |= (var->sync & FB_SYNC_SHARP_MODE) ? 0x00000040 : 0; + pcr |= (var->sync & FB_SYNC_OE_LOW_ACT) ? 0x00100000 : 0; + __raw_writel(pcr, LCDC_REG(LCDC_LPCR)); + + /* Horizontal and vertical configuration register */ + __raw_writel(((var->hsync_len - 1) << 26) + + ((var->right_margin - 1) << 8) + + (var->left_margin - 3), LCDC_REG(LCDC_LHCR)); + __raw_writel((var->vsync_len << 26) + + (var->lower_margin << 8) + + var->upper_margin, LCDC_REG(LCDC_LVCR)); + + /* Sharp configuration register */ + __raw_writel(0x00120300, LCDC_REG(LCDC_LSCR)); + + /* Refresh mode control reigster */ + __raw_writel(0x00000000, LCDC_REG(LCDC_LRMCR)); + + /* DMA control register */ + if (cpu_is_mx27_rev(CHIP_REV_2_0) > 0) + __raw_writel(0x00040060, LCDC_REG(LCDC_LDCR)); + else + __raw_writel(0x00020010, LCDC_REG(LCDC_LDCR)); +} + +/*! + * @brief Set LCD brightness + * @param level brightness level + */ +void mx2fb_set_brightness(uint8_t level) +{ + /* Set LCDC PWM contract control register */ + __raw_writel(0x00A90300 | level, LCDC_REG(LCDC_LPCCR)); +} +EXPORT_SYMBOL(mx2fb_set_brightness); + +/* + * @brief LCDC interrupt handler + */ +static irqreturn_t mx2fb_isr(int irq, void *dev_id) +{ + struct fb_event event; + unsigned long status = __raw_readl(LCDC_REG(LCDC_LISR)); + + if (status & MX2FB_INT_EOF) { + event.info = &mx2fb_info[0]; + atomic_notifier_call_chain(&mx2fb_notifier_list, + FB_EVENT_MXC_EOF, &event); + } + + if (status & MX2FB_INT_GW_EOF) { + event.info = &mx2fb_info[1]; + atomic_notifier_call_chain(&mx2fb_notifier_list, + FB_EVENT_MXC_EOF, &event); + } + + return IRQ_HANDLED; +} + +/*! + * @brief Config and request LCDC interrupt + */ +static void _request_irq(void) +{ + unsigned long status; + unsigned long flags; + + /* Read to clear the status */ + status = __raw_readl(LCDC_REG(LCDC_LISR)); + + if (request_irq(MXC_INT_LCDC, mx2fb_isr, 0, "LCDC", 0)) + pr_info("Request LCDC IRQ failed.\n"); + else { + spin_lock_irqsave(&mx2fb_notifier_list.lock, flags); + + /* Enable interrupt in case client has registered */ + if (mx2fb_notifier_list.head != NULL) { + unsigned long status; + unsigned long ints = MX2FB_INT_EOF; + + ints |= MX2FB_INT_GW_EOF; + + /* Read to clear the status */ + status = __raw_readl(LCDC_REG(LCDC_LISR)); + + /* Configure interrupt condition for EOF */ + __raw_writel(0x0, LCDC_REG(LCDC_LICR)); + + /* Enable EOF and graphic window EOF interrupt */ + __raw_writel(ints, LCDC_REG(LCDC_LIER)); + } + + spin_unlock_irqrestore(&mx2fb_notifier_list.lock, flags); + } +} + +/*! + * @brief Free LCDC interrupt handler + */ +static void _free_irq(void) +{ + /* Disable all LCDC interrupt */ + __raw_writel(0x0, LCDC_REG(LCDC_LIER)); + + free_irq(MXC_INT_LCDC, 0); +} + +/*! + * @brief Register a client notifier + * @param nb notifier block to callback on events + */ +int mx2fb_register_client(struct notifier_block *nb) +{ + unsigned long flags; + int ret; + + ret = atomic_notifier_chain_register(&mx2fb_notifier_list, nb); + + spin_lock_irqsave(&mx2fb_notifier_list.lock, flags); + + /* Enable interrupt in case client has registered */ + if (mx2fb_notifier_list.head != NULL) { + unsigned long status; + unsigned long ints = MX2FB_INT_EOF; + + ints |= MX2FB_INT_GW_EOF; + + /* Read to clear the status */ + status = __raw_readl(LCDC_REG(LCDC_LISR)); + + /* Configure interrupt condition for EOF */ + __raw_writel(0x0, LCDC_REG(LCDC_LICR)); + + /* Enable EOF and graphic window EOF interrupt */ + __raw_writel(ints, LCDC_REG(LCDC_LIER)); + } + + spin_unlock_irqrestore(&mx2fb_notifier_list.lock, flags); + + return ret; +} +EXPORT_SYMBOL(mx2fb_register_client); + +/*! + * @brief Unregister a client notifier + * @param nb notifier block to callback on events + */ +int mx2fb_unregister_client(struct notifier_block *nb) +{ + unsigned long flags; + int ret; + + ret = atomic_notifier_chain_unregister(&mx2fb_notifier_list, nb); + + spin_lock_irqsave(&mx2fb_notifier_list.lock, flags); + + /* Mask interrupt in case no client registered */ + if (mx2fb_notifier_list.head == NULL) + __raw_writel(0x0, LCDC_REG(LCDC_LIER)); + + spin_unlock_irqrestore(&mx2fb_notifier_list.lock, flags); + + return ret; +} +EXPORT_SYMBOL(mx2fb_unregister_client); + +#ifdef CONFIG_PM +/* + * Power management hooks. Note that we won't be called from IRQ context, + * unlike the blank functions above, so we may sleep. + */ + +/*! + * @brief Suspends the framebuffer and blanks the screen. + * Power management support + */ +static int mx2fb_suspend(struct platform_device *pdev, pm_message_t state) +{ + _disable_lcdc(&mx2fb_info[0]); + + return 0; +} + +/*! + * @brief Resumes the framebuffer and unblanks the screen. + * Power management support + */ +static int mx2fb_resume(struct platform_device *pdev) +{ + _enable_lcdc(&mx2fb_info[0]); + + return 0; +} + +#endif /* CONFIG_PM */ + +/*! + * @brief Probe routine for the framebuffer driver. It is called during the + * driver binding process. + * + * @return Appropriate error code to the kernel common code + */ +static int mx2fb_probe(struct platform_device *pdev) +{ + int ret, i; + + lcdc_clk = clk_get(&pdev->dev, "lcdc_clk"); + + for (i = 0; i < sizeof(mx2fb_info) / sizeof(struct fb_info); i++) { + ret = _install_fb(&mx2fb_info[i], pdev); + if (ret) { + dev_err(&pdev->dev, + "Failed to register framebuffer %d\n", i); + return ret; + } + } + _request_irq(); + + return 0; +} + +/*! + * @brief Initialization + */ +int __init mx2fb_init(void) +{ + /* + * For kernel boot options (in 'video=xxxfb:' format) + */ +#ifndef MODULE + { + char *option; + + if (fb_get_options("mxcfb", &option)) + return -ENODEV; + mx2fb_setup(option); + } +#endif + return platform_driver_register(&mx2fb_driver); +} + +/*! + * @brief Cleanup + */ +void __exit mx2fb_exit(void) +{ + int i; + + _free_irq(); + for (i = sizeof(mx2fb_info) / sizeof(struct fb_info); i > 0; i--) + _uninstall_fb(&mx2fb_info[i - 1]); + + platform_driver_unregister(&mx2fb_driver); +} + +#ifndef MODULE +/*! + * @brief Setup + * Parse user specified options + * Example: video=mxcfb:240x320,bpp=16,Sharp-QVGA + */ +static int __init mx2fb_setup(char *options) +{ + char *opt; + + if (!options || !*options) + return 0; + + fb_mode = 0; + fb_enabled = 0; + + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + + if (!strncmp(opt, "bpp=", 4)) + default_bpp = simple_strtoul(opt + 4, NULL, 0); + else + fb_mode = opt; + } + + return 0; +} +#endif + +/* Modularization */ +module_init(mx2fb_init); +module_exit(mx2fb_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MX2 framebuffer driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/mx2fb.h b/drivers/video/mxc/mx2fb.h new file mode 100644 index 000000000000..25f5c0d5404e --- /dev/null +++ b/drivers/video/mxc/mx2fb.h @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx2fb.h + * + * @brief Header file for the MX27 Frame buffer + * + * @ingroup Framebuffer + */ +#ifndef __MX2FB_H__ +#define __MX2FB_H__ + +/*! @brief MX27 LCDC graphic window information */ +struct fb_gwinfo { + /*! Non-zero if graphic window is enabled */ + __u32 enabled; + + /* The fields below are valid only when graphic window is enabled */ + + /*! Graphic window alpha value from 0 to 255 */ + __u32 alpha_value; + + /*! Non-zero if graphic window color keying is enabled. */ + __u32 ck_enabled; + + /* + * The fields ck_red, ck_green and ck_blue are valid only when + * graphic window and the color keying are enabled. They are the + * color component of graphic window color keying. + */ + + /*! Color keying red component */ + __u32 ck_red; + + /*! Color keying green component */ + __u32 ck_green; + + /*! Color keying blue component */ + __u32 ck_blue; + + /*! Graphic window x position */ + __u32 xpos; + + /*! Graphic window y position */ + __u32 ypos; + + /*! Non-zero if graphic window vertical scan in reverse direction. */ + __u32 vs_reversed; + + /* + * The following fields are valid for FBIOGET_GWINFO and + * mx2_gw_set(). FBIOPUT_GWINFO ignores these fields. + */ + __u32 base; /* Graphic window start address */ + __u32 xres; /* Visible x resolution */ + __u32 yres; /* Visible y resolution */ + __u32 xres_virtual; /* Virtual x resolution */ +}; + +/* 0x46E0-0x46FF are reserved for MX27 */ +#define FBIOGET_GWINFO 0x46E0 /*!< Get graphic window information */ +#define FBIOPUT_GWINFO 0x46E1 /*!< Set graphic window information */ + +struct mx2fb_gbl_alpha { + int enable; + int alpha; +}; + +struct mx2fb_color_key { + int enable; + __u32 color_key; +}; + +#define MX2FB_SET_GBL_ALPHA _IOW('M', 0, struct mx2fb_gbl_alpha) +#define MX2FB_SET_CLR_KEY _IOW('M', 1, struct mx2fb_color_key) +#define MX2FB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t) + +#ifdef __KERNEL__ + +/* + * LCDC register definitions + */ +#define LCDC_LSSAR 0x00 +#define LCDC_LSR 0x04 +#define LCDC_LVPWR 0x08 +#define LCDC_LCPR 0x0C +#define LCDC_LCWHBR 0x10 +#define LCDC_LCCMR 0x14 +#define LCDC_LPCR 0x18 +#define LCDC_LHCR 0x1C +#define LCDC_LVCR 0x20 +#define LCDC_LPOR 0x24 +#define LCDC_LSCR 0x28 +#define LCDC_LPCCR 0x2C +#define LCDC_LDCR 0x30 +#define LCDC_LRMCR 0x34 +#define LCDC_LICR 0x38 +#define LCDC_LIER 0x3C +#define LCDC_LISR 0x40 +#define LCDC_LGWSAR 0x50 +#define LCDC_LGWSR 0x54 +#define LCDC_LGWVPWR 0x58 +#define LCDC_LGWPOR 0x5C +#define LCDC_LGWPR 0x60 +#define LCDC_LGWCR 0x64 +#define LCDC_LGWDCR 0x68 +#define LCDC_LAUSCR 0x80 +#define LCDC_LAUSCCR 0x84 + +#define LCDC_REG(reg) (IO_ADDRESS(LCDC_BASE_ADDR) + reg) + +#define MX2FB_INT_BOF 0x0001 /* Beginning of Frame */ +#define MX2FB_INT_EOF 0x0002 /* End of Frame */ +#define MX2FB_INT_ERR_RES 0x0004 /* Error Response */ +#define MX2FB_INT_UDR_ERR 0x0008 /* Under Run Error */ +#define MX2FB_INT_GW_BOF 0x0010 /* Graphic Window BOF */ +#define MX2FB_INT_GW_EOF 0x0020 /* Graphic Window EOF */ +#define MX2FB_INT_GW_ERR_RES 0x0040 /* Graphic Window ERR_RES */ +#define MX2FB_INT_GW_UDR_ERR 0x0080 /* Graphic Window UDR_ERR */ + +#define FB_EVENT_MXC_EOF 0x8001 /* End of Frame event */ + +int mx2fb_register_client(struct notifier_block *nb); +int mx2fb_unregister_client(struct notifier_block *nb); + +void mx2_gw_set(struct fb_gwinfo *gwinfo); + +#endif /* __KERNEL__ */ + +#endif /* __MX2FB_H__ */ diff --git a/drivers/video/mxc/mxc_edid.c b/drivers/video/mxc/mxc_edid.c new file mode 100644 index 000000000000..0289c5253ad7 --- /dev/null +++ b/drivers/video/mxc/mxc_edid.c @@ -0,0 +1,319 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxc_edid.c + * + * @brief MXC EDID tools + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include "../edid.h" + +#undef DEBUG /* define this for verbose EDID parsing output */ + +#ifdef DEBUG +#define DPRINTK(fmt, args...) printk(fmt, ## args) +#else +#define DPRINTK(fmt, args...) +#endif + +const struct fb_videomode cea_modes[64] = { + /* #1: 640x480p@59.94/60Hz */ + [1] = { + NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0, + FB_VMODE_NONINTERLACED, 0, + }, + /* #3: 720x480p@59.94/60Hz */ + [3] = { + NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0, + FB_VMODE_NONINTERLACED, 0, + }, + /* #5: 1920x1080i@59.94/60Hz */ + [5] = { + NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_INTERLACED, 0, + }, + /* #7: 720(1440)x480iH@59.94/60Hz */ + [7] = { + NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0, + FB_VMODE_INTERLACED, 0, + }, + /* #9: 720(1440)x240pH@59.94/60Hz */ + [9] = { + NULL, 60, 1440, 240, 18554, 114, 38, 16, 4, 124, 3, 0, + FB_VMODE_NONINTERLACED, 0, + }, + /* #18: 720x576pH@50Hz */ + [18] = { + NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0, + FB_VMODE_NONINTERLACED, 0, + }, + /* #19: 1280x720p@50Hz */ + [19] = { + NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, 0, + }, + /* #20: 1920x1080i@50Hz */ + [20] = { + NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_INTERLACED, 0, + }, + /* #32: 1920x1080p@23.98/24Hz */ + [32] = { + NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, 0, + }, + /* #35: (2880)x480p4x@59.94/60Hz */ + [35] = { + NULL, 60, 2880, 480, 9250, 240, 64, 30, 9, 248, 6, 0, + FB_VMODE_NONINTERLACED, 0, + }, +}; + +static void get_detailed_timing(unsigned char *block, + struct fb_videomode *mode) +{ + mode->xres = H_ACTIVE; + mode->yres = V_ACTIVE; + mode->pixclock = PIXEL_CLOCK; + mode->pixclock /= 1000; + mode->pixclock = KHZ2PICOS(mode->pixclock); + mode->right_margin = H_SYNC_OFFSET; + mode->left_margin = (H_ACTIVE + H_BLANKING) - + (H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH); + mode->upper_margin = V_BLANKING - V_SYNC_OFFSET - + V_SYNC_WIDTH; + mode->lower_margin = V_SYNC_OFFSET; + mode->hsync_len = H_SYNC_WIDTH; + mode->vsync_len = V_SYNC_WIDTH; + if (HSYNC_POSITIVE) + mode->sync |= FB_SYNC_HOR_HIGH_ACT; + if (VSYNC_POSITIVE) + mode->sync |= FB_SYNC_VERT_HIGH_ACT; + mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) * + (V_ACTIVE + V_BLANKING)); + if (INTERLACED) { + mode->yres *= 2; + mode->upper_margin *= 2; + mode->lower_margin *= 2; + mode->vsync_len *= 2; + mode->vmode |= FB_VMODE_INTERLACED; + } + mode->flag = FB_MODE_IS_DETAILED; + + DPRINTK(" %d MHz ", PIXEL_CLOCK/1000000); + DPRINTK("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET, + H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING); + DPRINTK("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET, + V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING); + DPRINTK("%sHSync %sVSync\n\n", (HSYNC_POSITIVE) ? "+" : "-", + (VSYNC_POSITIVE) ? "+" : "-"); +} + +int mxc_edid_parse_ext_blk(unsigned char *edid, + struct mxc_edid_cfg *cfg, + struct fb_monspecs *specs) +{ + char detail_timming_desc_offset; + struct fb_videomode *mode, *m; + unsigned char index = 0x0; + unsigned char *block; + int i, num = 0; + + if (edid[index++] != 0x2) /* only support cea ext block now */ + return -1; + if (edid[index++] != 0x3) /* only support version 3*/ + return -1; + mode = kzalloc(50 * sizeof(struct fb_videomode), GFP_KERNEL); + if (mode == NULL) + return -1; + + detail_timming_desc_offset = edid[index++]; + + cfg->cea_underscan = (edid[index] >> 7) & 0x1; + cfg->cea_basicaudio = (edid[index] >> 6) & 0x1; + cfg->cea_ycbcr444 = (edid[index] >> 5) & 0x1; + cfg->cea_ycbcr422 = (edid[index] >> 4) & 0x1; + + /* short desc */ + DPRINTK("CEA Short desc timmings\n"); + index++; + while (index < detail_timming_desc_offset) { + unsigned char tagcode, blklen; + + tagcode = (edid[index] >> 5) & 0x7; + blklen = (edid[index]) & 0x1f; + + DPRINTK("Tagcode %x Len %d\n", tagcode, blklen); + + switch (tagcode) { + case 0x2: /*Video data block*/ + { + int cea_idx; + i = 0; + while (i < blklen) { + index++; + cea_idx = edid[index] & 0x7f; + if (cea_idx < ARRAY_SIZE(cea_modes) && + (cea_modes[cea_idx].xres)) { + DPRINTK("Support CEA Format #%d\n", cea_idx); + mode[num] = cea_modes[cea_idx]; + mode[num].flag |= FB_MODE_IS_STANDARD; + num++; + } + i++; + } + break; + } + case 0x3: /*Vendor specific data*/ + { + unsigned char IEEE_reg_iden[3]; + IEEE_reg_iden[0] = edid[index+1]; + IEEE_reg_iden[1] = edid[index+2]; + IEEE_reg_iden[2] = edid[index+3]; + + if ((IEEE_reg_iden[0] == 0x03) && + (IEEE_reg_iden[1] == 0x0c) && + (IEEE_reg_iden[2] == 0x00)) + cfg->hdmi_cap = 1; + index += blklen; + break; + } + case 0x1: /*Audio data block*/ + case 0x4: /*Speaker allocation block*/ + case 0x7: /*User extended block*/ + default: + /* skip */ + index += blklen; + break; + } + + index++; + } + + /* long desc */ + DPRINTK("CEA long desc timmings\n"); + index = detail_timming_desc_offset; + block = edid + index; + while (index < (EDID_LENGTH - DETAILED_TIMING_DESCRIPTION_SIZE)) { + if (!(block[0] == 0x00 && block[1] == 0x00)) { + get_detailed_timing(block, &mode[num]); + num++; + } + block += DETAILED_TIMING_DESCRIPTION_SIZE; + index += DETAILED_TIMING_DESCRIPTION_SIZE; + } + + if (!num) { + kfree(mode); + return 0; + } + + m = kmalloc((num + specs->modedb_len) * + sizeof(struct fb_videomode), GFP_KERNEL); + if (!m) + return 0; + + if (specs->modedb_len) { + memmove(m, specs->modedb, + specs->modedb_len * sizeof(struct fb_videomode)); + kfree(specs->modedb); + } + memmove(m+specs->modedb_len, mode, + num * sizeof(struct fb_videomode)); + kfree(mode); + + specs->modedb_len += num; + specs->modedb = m; + + return 0; +} + +/* make sure edid has 256 bytes*/ +int mxc_edid_read(struct i2c_adapter *adp, unsigned char *edid, + struct mxc_edid_cfg *cfg, struct fb_info *fbi) +{ + u8 buf0[2] = {0, 0}; + int dat = 0; + u16 addr = 0x50; + struct i2c_msg msg[2] = { + { + .addr = addr, + .flags = 0, + .len = 1, + .buf = buf0, + }, { + .addr = addr, + .flags = I2C_M_RD, + .len = EDID_LENGTH, + .buf = edid, + }, + }; + + if (adp == NULL) + return -EINVAL; + + memset(edid, 0, 256); + memset(cfg, 0, sizeof(struct mxc_edid_cfg)); + + buf0[0] = 0x00; + dat = i2c_transfer(adp, msg, 2); + + /* If 0x50 fails, try 0x37. */ + if (edid[1] == 0x00) { + msg[0].addr = msg[1].addr = 0x37; + dat = i2c_transfer(adp, msg, 2); + if (dat < 0) + return dat; + } + + if (edid[1] == 0x00) + return -ENOENT; + + /* edid first block parsing */ + memset(&fbi->monspecs, 0, sizeof(fbi->monspecs)); + fb_edid_to_monspecs(edid, &fbi->monspecs); + + /* need read ext block? Only support one more blk now*/ + if (edid[0x7E]) { + if (edid[0x7E] > 1) + DPRINTK("Edid has %d ext block, \ + but now only support 1 ext blk\n", edid[0x7E]); + buf0[0] = 0x80; + msg[1].buf = edid + EDID_LENGTH; + dat = i2c_transfer(adp, msg, 2); + if (dat < 0) + return dat; + + /* edid ext block parsing */ + mxc_edid_parse_ext_blk(edid + 128, cfg, &fbi->monspecs); + } + + return 0; +} diff --git a/drivers/video/mxc/mxc_elcdif_fb.c b/drivers/video/mxc/mxc_elcdif_fb.c new file mode 100644 index 000000000000..90dfe55ece42 --- /dev/null +++ b/drivers/video/mxc/mxc_elcdif_fb.c @@ -0,0 +1,1466 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +/* + * Based on drivers/video/mxc/mxc_ipuv3_fb.c, drivers/video/mxs/lcdif.c + * and arch/arm/mach-mx28/include/mach/lcdif.h. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "elcdif_regs.h" + +/* ELCDIF Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#define fourcc(a, b, c, d) \ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/* + * ELCDIF RGB Formats + */ +#define ELCDIF_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') +#define ELCDIF_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') +#define ELCDIF_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') +#define ELCDIF_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') +#define ELCDIF_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') +#define ELCDIF_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') +#define ELCDIF_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') +#define ELCDIF_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') +#define ELCDIF_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') +#define ELCDIF_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') +#define ELCDIF_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') +#define ELCDIF_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') + +struct mxc_elcdif_fb_data { + int cur_blank; + int next_blank; + int output_pix_fmt; + int dma_irq; + bool wait4vsync; + bool wait4framedone; + bool panning; + struct completion vsync_complete; + struct completion frame_done_complete; + struct semaphore flip_sem; + u32 pseudo_palette[16]; +}; + +struct elcdif_signal_cfg { + unsigned clk_pol:1; /* true = falling edge */ + unsigned enable_pol:1; /* true = active high */ + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; /* true = active high */ +}; + +static int mxc_elcdif_fb_blank(int blank, struct fb_info *info); +static int mxc_elcdif_fb_map_video_memory(struct fb_info *info); +static int mxc_elcdif_fb_unmap_video_memory(struct fb_info *info); +static char *fb_mode; +static unsigned long default_bpp = 16; +static void __iomem *elcdif_base; +static struct device *g_elcdif_dev; +static bool g_elcdif_axi_clk_enable; +static bool g_elcdif_pix_clk_enable; +static struct clk *g_elcdif_axi_clk; +static struct clk *g_elcdif_pix_clk; + +static inline void setup_dotclk_panel(u32 pixel_clk, + u16 v_pulse_width, + u16 v_period, + u16 v_wait_cnt, + u16 v_active, + u16 h_pulse_width, + u16 h_period, + u16 h_wait_cnt, + u16 h_active, + int in_pixel_format, + int out_pixel_format, + struct elcdif_signal_cfg sig_cfg, + int enable_present) +{ + u32 val, rounded_pixel_clk; + + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + dev_dbg(g_elcdif_dev, "pixel clk = %d\n", pixel_clk); + rounded_pixel_clk = clk_round_rate(g_elcdif_pix_clk, pixel_clk); + clk_set_rate(g_elcdif_pix_clk, rounded_pixel_clk); + + __raw_writel(BM_ELCDIF_CTRL_DATA_SHIFT_DIR, + elcdif_base + HW_ELCDIF_CTRL_CLR); + + __raw_writel(BM_ELCDIF_CTRL_SHIFT_NUM_BITS, + elcdif_base + HW_ELCDIF_CTRL_CLR); + + __raw_writel(BF_ELCDIF_CTRL2_OUTSTANDING_REQS + (BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8), + elcdif_base + HW_ELCDIF_CTRL2_SET); + + /* Recover on underflow */ + __raw_writel(BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + elcdif_base + HW_ELCDIF_CTRL1_SET); + + /* Configure the input pixel format */ + __raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH | + BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT | + BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT | + BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT, + elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + switch (in_pixel_format) { + case ELCDIF_PIX_FMT_RGB565: + __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF), + elcdif_base + HW_ELCDIF_CTRL1_SET); + __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(0) | + BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0), + elcdif_base + HW_ELCDIF_CTRL_SET); + break; + case ELCDIF_PIX_FMT_RGB24: + __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF), + elcdif_base + HW_ELCDIF_CTRL1_SET); + __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) | + BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0), + elcdif_base + HW_ELCDIF_CTRL_SET); + break; + case ELCDIF_PIX_FMT_RGB32: + __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7), + elcdif_base + HW_ELCDIF_CTRL1_SET); + __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) | + BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0), + elcdif_base + HW_ELCDIF_CTRL_SET); + break; + default: + dev_err(g_elcdif_dev, "ELCDIF unsupported input pixel format " + "%d\n", in_pixel_format); + break; + } + + /* Configure the output pixel format */ + __raw_writel(BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH, + elcdif_base + HW_ELCDIF_CTRL_CLR); + switch (out_pixel_format) { + case ELCDIF_PIX_FMT_RGB565: + __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(0), + elcdif_base + HW_ELCDIF_CTRL_SET); + break; + case ELCDIF_PIX_FMT_RGB666: + __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(2), + elcdif_base + HW_ELCDIF_CTRL_SET); + break; + case ELCDIF_PIX_FMT_RGB24: + __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(3), + elcdif_base + HW_ELCDIF_CTRL_SET); + break; + default: + dev_err(g_elcdif_dev, "ELCDIF unsupported output pixel format " + "%d\n", out_pixel_format); + break; + } + + val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT); + val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT | + BM_ELCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT); + + __raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(BM_ELCDIF_CTRL_DVI_MODE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE, + elcdif_base + HW_ELCDIF_CTRL_SET); + __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT, + elcdif_base + HW_ELCDIF_CTRL_SET); + + val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0); + val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_POL | + BM_ELCDIF_VDCTRL0_HSYNC_POL | + BM_ELCDIF_VDCTRL0_ENABLE_POL | + BM_ELCDIF_VDCTRL0_DOTCLK_POL); + if (sig_cfg.Vsync_pol) + val |= BM_ELCDIF_VDCTRL0_VSYNC_POL; + if (sig_cfg.Hsync_pol) + val |= BM_ELCDIF_VDCTRL0_HSYNC_POL; + if (sig_cfg.clk_pol) + val |= BM_ELCDIF_VDCTRL0_DOTCLK_POL; + if (sig_cfg.enable_pol) + val |= BM_ELCDIF_VDCTRL0_ENABLE_POL; + __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0); + + /* vsync is output */ + val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0); + val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_OEB); + __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0); + + /* + * need enable sig for true RGB i/f. Or, if not true RGB, leave it + * zero. + */ + if (enable_present) { + val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0); + val |= BM_ELCDIF_VDCTRL0_ENABLE_PRESENT; + __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0); + } + + /* + * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines + */ + val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0); + val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT); + val |= BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; + __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0); + + __raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH, + elcdif_base + HW_ELCDIF_VDCTRL0_CLR); + __raw_writel(v_pulse_width, elcdif_base + HW_ELCDIF_VDCTRL0_SET); + + __raw_writel(BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v_period), + elcdif_base + HW_ELCDIF_VDCTRL1); + + __raw_writel(BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) | + BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(h_period), + elcdif_base + HW_ELCDIF_VDCTRL2); + + val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4); + val &= ~BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT; + val |= BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active); + __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4); + + val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL3); + val &= ~(BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT | + BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT); + val |= BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) | + BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt); + __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL3); + + val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4); + val |= BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON; + __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4); + + return; +} + +static inline void release_dotclk_panel(void) +{ + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + __raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL0); + __raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL1); + __raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL2); + __raw_writel(0, elcdif_base + HW_ELCDIF_VDCTRL3); + + return; +} + +static inline void setup_dvi_panel(u16 h_active, u16 v_active, + u16 h_blanking, u16 v_lines, + u16 v1_blank_start, u16 v1_blank_end, + u16 v2_blank_start, u16 v2_blank_end, + u16 f1_start, u16 f1_end, + u16 f2_start, u16 f2_end) +{ + u32 val; + + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + /* 32bit packed format (RGB) */ + __raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7) | + BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + elcdif_base + HW_ELCDIF_CTRL1_SET); + + val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT); + val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT | + BM_ELCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT); + + /* set elcdif to DVI mode */ + __raw_writel(BM_ELCDIF_CTRL_DVI_MODE, + elcdif_base + HW_ELCDIF_CTRL_SET); + __raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + + __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT, + elcdif_base + HW_ELCDIF_CTRL_SET); + /* convert input RGB -> YCbCr */ + __raw_writel(BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC, + elcdif_base + HW_ELCDIF_CTRL_SET); + /* interlace odd and even fields */ + __raw_writel(BM_ELCDIF_CTRL1_INTERLACE_FIELDS, + elcdif_base + HW_ELCDIF_CTRL1_SET); + + __raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH | + BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH, + elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ + BM_ELCDIF_CTRL_DATA_SELECT | /* data mode */ + BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ + BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(1), /* 8 bit */ + elcdif_base + HW_ELCDIF_CTRL_SET); + + /* ELCDIF_DVI */ + /* set frame size */ + val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL0); + __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL0); + + /* set start/end of field-1 and start of field-2 */ + val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL1); + val &= ~(BM_ELCDIF_DVICTRL1_F1_START_LINE | + BM_ELCDIF_DVICTRL1_F1_END_LINE | + BM_ELCDIF_DVICTRL1_F2_START_LINE); + val |= BF_ELCDIF_DVICTRL1_F1_START_LINE(f1_start) | + BF_ELCDIF_DVICTRL1_F1_END_LINE(f1_end) | + BF_ELCDIF_DVICTRL1_F2_START_LINE(f2_start); + __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL1); + + /* set first vertical blanking interval and end of filed-2 */ + val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL2); + val &= ~(BM_ELCDIF_DVICTRL2_F2_END_LINE | + BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE | + BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE); + val |= BF_ELCDIF_DVICTRL2_F2_END_LINE(f2_end) | + BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v1_blank_start) | + BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v1_blank_end); + __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL2); + + /* set second vertical blanking interval */ + val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL3); + val &= ~(BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE | + BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE); + val |= BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v2_blank_start) | + BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v2_blank_end); + __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL3); + + /* fill the rest area black color if the input frame + * is not 720 pixels/line + */ + if (h_active != 720) { + /* the input frame can't be less then (720-256) pixels/line */ + if (720 - h_active > 0xff) + h_active = 720 - 0xff; + + val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL4); + val &= ~(BM_ELCDIF_DVICTRL4_H_FILL_CNT | + BM_ELCDIF_DVICTRL4_Y_FILL_VALUE | + BM_ELCDIF_DVICTRL4_CB_FILL_VALUE | + BM_ELCDIF_DVICTRL4_CR_FILL_VALUE); + val |= BF_ELCDIF_DVICTRL4_H_FILL_CNT(720 - h_active) | + BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(16) | + BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(128) | + BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(128); + __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL4); + } + + /* Color Space Conversion RGB->YCbCr */ + val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF0); + val &= ~(BM_ELCDIF_CSC_COEFF0_C0 | + BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER); + val |= BF_ELCDIF_CSC_COEFF0_C0(0x41) | + BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(3); + __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF0); + + val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF1); + val &= ~(BM_ELCDIF_CSC_COEFF1_C1 | BM_ELCDIF_CSC_COEFF1_C2); + val |= BF_ELCDIF_CSC_COEFF1_C1(0x81) | + BF_ELCDIF_CSC_COEFF1_C2(0x19); + __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF1); + + val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF2); + val &= ~(BM_ELCDIF_CSC_COEFF2_C3 | BM_ELCDIF_CSC_COEFF2_C4); + val |= BF_ELCDIF_CSC_COEFF2_C3(0x3DB) | + BF_ELCDIF_CSC_COEFF2_C4(0x3B6); + __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF2); + + val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF3); + val &= ~(BM_ELCDIF_CSC_COEFF3_C5 | BM_ELCDIF_CSC_COEFF3_C6); + val |= BF_ELCDIF_CSC_COEFF3_C5(0x70) | + BF_ELCDIF_CSC_COEFF3_C6(0x70); + __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF3); + + val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF4); + val &= ~(BM_ELCDIF_CSC_COEFF4_C7 | BM_ELCDIF_CSC_COEFF4_C8); + val |= BF_ELCDIF_CSC_COEFF4_C7(0x3A2) | + BF_ELCDIF_CSC_COEFF4_C8(0x3EE); + __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF4); + + val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_OFFSET); + val &= ~(BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET | + BM_ELCDIF_CSC_OFFSET_Y_OFFSET); + val |= BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(0x80) | + BF_ELCDIF_CSC_OFFSET_Y_OFFSET(0x10); + __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_OFFSET); + + val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_LIMIT); + val &= ~(BM_ELCDIF_CSC_LIMIT_CBCR_MIN | + BM_ELCDIF_CSC_LIMIT_CBCR_MAX | + BM_ELCDIF_CSC_LIMIT_Y_MIN | + BM_ELCDIF_CSC_LIMIT_Y_MAX); + val |= BF_ELCDIF_CSC_LIMIT_CBCR_MIN(16) | + BF_ELCDIF_CSC_LIMIT_CBCR_MAX(240) | + BF_ELCDIF_CSC_LIMIT_Y_MIN(16) | + BF_ELCDIF_CSC_LIMIT_Y_MAX(235); + __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_LIMIT); + + return; +} + +static inline void release_dvi_panel(void) +{ + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + __raw_writel(BM_ELCDIF_CTRL_DVI_MODE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + return; +} + +static inline void mxc_init_elcdif(void) +{ + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + __raw_writel(BM_ELCDIF_CTRL_CLKGATE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + /* Reset controller */ + __raw_writel(BM_ELCDIF_CTRL_SFTRST, + elcdif_base + HW_ELCDIF_CTRL_SET); + udelay(10); + + /* Take controller out of reset */ + __raw_writel(BM_ELCDIF_CTRL_SFTRST | BM_ELCDIF_CTRL_CLKGATE, + elcdif_base + HW_ELCDIF_CTRL_CLR); + + /* Setup the bus protocol */ + __raw_writel(BM_ELCDIF_CTRL1_MODE86, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + __raw_writel(BM_ELCDIF_CTRL1_BUSY_ENABLE, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + + /* Take display out of reset */ + __raw_writel(BM_ELCDIF_CTRL1_RESET, + elcdif_base + HW_ELCDIF_CTRL1_SET); + + /* VSYNC is an input by default */ + __raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_OEB, + elcdif_base + HW_ELCDIF_VDCTRL0_SET); + + /* Reset display */ + __raw_writel(BM_ELCDIF_CTRL1_RESET, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + udelay(10); + __raw_writel(BM_ELCDIF_CTRL1_RESET, + elcdif_base + HW_ELCDIF_CTRL1_SET); + udelay(10); + + return; +} + +int mxc_elcdif_frame_addr_setup(dma_addr_t phys) +{ + int ret = 0; + + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + __raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER, + elcdif_base + HW_ELCDIF_CTRL_SET); + + __raw_writel(phys, elcdif_base + HW_ELCDIF_CUR_BUF); + __raw_writel(phys, elcdif_base + HW_ELCDIF_NEXT_BUF); + return ret; +} + +static inline void mxc_elcdif_dma_release(void) +{ + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + __raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER, + elcdif_base + HW_ELCDIF_CTRL_CLR); + return; +} + +static inline void mxc_elcdif_run(void) +{ + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + __raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER, + elcdif_base + HW_ELCDIF_CTRL_SET); + __raw_writel(BM_ELCDIF_CTRL_RUN, + elcdif_base + HW_ELCDIF_CTRL_SET); + return; +} + +static inline void mxc_elcdif_stop(void) +{ + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + __raw_writel(BM_ELCDIF_CTRL_RUN, + elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(BM_ELCDIF_CTRL_ELCDIF_MASTER, + elcdif_base + HW_ELCDIF_CTRL_CLR); + msleep(1); + __raw_writel(BM_ELCDIF_CTRL_CLKGATE, elcdif_base + HW_ELCDIF_CTRL_SET); + return; +} + +static int mxc_elcdif_blank_panel(int blank) +{ + int ret = 0, count; + + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + switch (blank) { + case FB_BLANK_NORMAL: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_POWERDOWN: + __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT, + elcdif_base + HW_ELCDIF_CTRL_CLR); + for (count = 10000; count; count--) { + if (__raw_readl(elcdif_base + HW_ELCDIF_STAT) & + BM_ELCDIF_STAT_TXFIFO_EMPTY) + break; + msleep(1); + } + break; + + case FB_BLANK_UNBLANK: + __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT, + elcdif_base + HW_ELCDIF_CTRL_SET); + break; + + default: + dev_err(g_elcdif_dev, "unknown blank parameter\n"); + ret = -EINVAL; + break; + } + return ret; +} + +static int mxc_elcdif_init_panel(void) +{ + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + + /* + * Make sure we do a high-to-low transition to reset the panel. + * First make it low for 100 msec, hi for 10 msec, low for 10 msec, + * then hi. + */ + __raw_writel(BM_ELCDIF_CTRL1_RESET, + elcdif_base + HW_ELCDIF_CTRL1_CLR); /* low */ + msleep(100); + __raw_writel(BM_ELCDIF_CTRL1_RESET, + elcdif_base + HW_ELCDIF_CTRL1_SET); /* high */ + msleep(10); + __raw_writel(BM_ELCDIF_CTRL1_RESET, + elcdif_base + HW_ELCDIF_CTRL1_CLR); /* low */ + + /* For the Samsung, Reset must be held low at least 30 uSec + * Therefore, we'll hold it low for about 10 mSec just to be sure. + * Then we'll wait 1 mSec afterwards. + */ + msleep(10); + __raw_writel(BM_ELCDIF_CTRL1_RESET, + elcdif_base + HW_ELCDIF_CTRL1_SET); /* high */ + msleep(1); + + return 0; +} + +static uint32_t bpp_to_pixfmt(struct fb_info *fbi) +{ + uint32_t pixfmt = 0; + + if (fbi->var.nonstd) + return fbi->var.nonstd; + + switch (fbi->var.bits_per_pixel) { + case 32: + pixfmt = ELCDIF_PIX_FMT_RGB32; + break; + case 24: + pixfmt = ELCDIF_PIX_FMT_RGB24; + break; + case 18: + pixfmt = ELCDIF_PIX_FMT_RGB666; + break; + case 16: + pixfmt = ELCDIF_PIX_FMT_RGB565; + break; + case 8: + pixfmt = ELCDIF_PIX_FMT_RGB332; + break; + } + return pixfmt; +} + +static int mxc_elcdif_fb_set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + + fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; + + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 1; + fix->ypanstep = 1; + + return 0; +} + +static irqreturn_t lcd_irq_handler(int irq, void *dev_id) +{ + struct mxc_elcdif_fb_data *data = dev_id; + u32 status_lcd = __raw_readl(elcdif_base + HW_ELCDIF_CTRL1); + dev_dbg(g_elcdif_dev, "%s: irq %d\n", __func__, irq); + + if ((status_lcd & BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ) && + data->wait4vsync) { + dev_dbg(g_elcdif_dev, "%s: VSYNC irq\n", __func__); + __raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + data->wait4vsync = 0; + complete(&data->vsync_complete); + } + if ((status_lcd & BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ) && + data->wait4framedone) { + dev_dbg(g_elcdif_dev, "%s: frame done irq\n", __func__); + __raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + if (data->panning) { + up(&data->flip_sem); + data->panning = 0; + } + data->wait4framedone = 0; + complete(&data->frame_done_complete); + } + if (status_lcd & BM_ELCDIF_CTRL1_UNDERFLOW_IRQ) { + dev_dbg(g_elcdif_dev, "%s: underflow irq\n", __func__); + __raw_writel(BM_ELCDIF_CTRL1_UNDERFLOW_IRQ, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + } + if (status_lcd & BM_ELCDIF_CTRL1_OVERFLOW_IRQ) { + dev_dbg(g_elcdif_dev, "%s: overflow irq\n", __func__); + __raw_writel(BM_ELCDIF_CTRL1_OVERFLOW_IRQ, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + } + return IRQ_HANDLED; +} + +static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int mxc_elcdif_fb_setcolreg(u_int regno, u_int red, u_int green, + u_int blue, u_int transp, + struct fb_info *fbi) +{ + unsigned int val; + int ret = 1; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (fbi->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + switch (fbi->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = fbi->pseudo_palette; + + val = _chan_to_field(red, &fbi->var.red); + val |= _chan_to_field(green, &fbi->var.green); + val |= _chan_to_field(blue, &fbi->var.blue); + + pal[regno] = val; + ret = 0; + } + break; + + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + return ret; +} + +/* + * This routine actually sets the video mode. It's in here where we + * the hardware state info->par and fix which can be affected by the + * change in par. For this driver it doesn't do much. + * + */ +static int mxc_elcdif_fb_set_par(struct fb_info *fbi) +{ + struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par; + struct elcdif_signal_cfg sig_cfg; + int mem_len; + + dev_dbg(fbi->device, "Reconfiguring framebuffer\n"); + + sema_init(&data->flip_sem, 1); + + /* release prev panel */ + if (!g_elcdif_pix_clk_enable) { + clk_enable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = true; + } + mxc_elcdif_blank_panel(FB_BLANK_POWERDOWN); + mxc_elcdif_stop(); + release_dotclk_panel(); + mxc_elcdif_dma_release(); + mxc_elcdif_fb_set_fix(fbi); + if (g_elcdif_pix_clk_enable) { + clk_disable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = false; + } + + mem_len = fbi->var.yres_virtual * fbi->fix.line_length; + if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) { + if (fbi->fix.smem_start) + mxc_elcdif_fb_unmap_video_memory(fbi); + + if (mxc_elcdif_fb_map_video_memory(fbi) < 0) + return -ENOMEM; + } + + if (data->next_blank != FB_BLANK_UNBLANK) + return 0; + + /* init next panel */ + if (!g_elcdif_pix_clk_enable) { + clk_enable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = true; + } + mxc_init_elcdif(); + mxc_elcdif_init_panel(); + + dev_dbg(fbi->device, "pixclock = %ul Hz\n", + (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); + + memset(&sig_cfg, 0, sizeof(sig_cfg)); + if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) + sig_cfg.Hsync_pol = true; + if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) + sig_cfg.Vsync_pol = true; + if (fbi->var.sync & FB_SYNC_CLK_LAT_FALL) + sig_cfg.clk_pol = true; + if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT)) + sig_cfg.enable_pol = true; + + setup_dotclk_panel((PICOS2KHZ(fbi->var.pixclock)) * 1000UL, + fbi->var.vsync_len, + fbi->var.upper_margin + + fbi->var.yres + fbi->var.lower_margin, + fbi->var.upper_margin, + fbi->var.yres, + fbi->var.hsync_len, + fbi->var.left_margin + + fbi->var.xres + fbi->var.right_margin, + fbi->var.left_margin, + fbi->var.xres, + bpp_to_pixfmt(fbi), + data->output_pix_fmt, + sig_cfg, + 1); + mxc_elcdif_frame_addr_setup(fbi->fix.smem_start); + mxc_elcdif_run(); + mxc_elcdif_blank_panel(FB_BLANK_UNBLANK); + + fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var, + &fbi->modelist); + return 0; +} + +static int mxc_elcdif_fb_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + if (var->xres_virtual < var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8)) + var->bits_per_pixel = default_bpp; + + switch (var->bits_per_pixel) { + case 8: + var->red.length = 3; + var->red.offset = 5; + var->red.msb_right = 0; + + var->green.length = 3; + var->green.offset = 2; + var->green.msb_right = 0; + + var->blue.length = 2; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + var->height = -1; + var->width = -1; + var->grayscale = 0; + + return 0; +} + +static int mxc_elcdif_fb_wait_for_vsync(struct fb_info *info) +{ + struct mxc_elcdif_fb_data *data = + (struct mxc_elcdif_fb_data *)info->par; + int ret = 0; + + if (data->cur_blank != FB_BLANK_UNBLANK) { + dev_err(info->device, "can't wait for VSYNC when fb " + "is blank\n"); + return -EINVAL; + } + + init_completion(&data->vsync_complete); + + __raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + data->wait4vsync = 1; + __raw_writel(BM_ELCDIF_CTRL1_VSYNC_EDGE_IRQ_EN, + elcdif_base + HW_ELCDIF_CTRL1_SET); + ret = wait_for_completion_interruptible_timeout( + &data->vsync_complete, 1 * HZ); + if (ret == 0) { + dev_err(info->device, + "MXC ELCDIF wait for vsync timeout\n"); + data->wait4vsync = 0; + ret = -ETIME; + } else if (ret > 0) { + ret = 0; + } + return ret; +} + +static int mxc_elcdif_fb_wait_for_frame_done(struct fb_info *info) +{ + struct mxc_elcdif_fb_data *data = + (struct mxc_elcdif_fb_data *)info->par; + int ret = 0; + + if (data->cur_blank != FB_BLANK_UNBLANK) { + dev_err(info->device, "can't wait for frame done when fb " + "is blank\n"); + return -EINVAL; + } + + init_completion(&data->frame_done_complete); + + __raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ, + elcdif_base + HW_ELCDIF_CTRL1_CLR); + data->wait4framedone = 1; + __raw_writel(BM_ELCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN, + elcdif_base + HW_ELCDIF_CTRL1_SET); + ret = wait_for_completion_interruptible_timeout( + &data->frame_done_complete, 1 * HZ); + if (ret == 0) { + dev_err(info->device, + "MXC ELCDIF wait for frame done timeout\n"); + data->wait4framedone = 0; + ret = -ETIME; + } else if (ret > 0) { + ret = 0; + } + return ret; +} + +static int mxc_elcdif_fb_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg) +{ + int ret = -EINVAL; + + switch (cmd) { + case MXCFB_WAIT_FOR_VSYNC: + ret = mxc_elcdif_fb_wait_for_vsync(info); + break; + case MXCFB_GET_FB_BLANK: + { + struct mxc_elcdif_fb_data *data = + (struct mxc_elcdif_fb_data *)info->par; + + if (put_user(data->cur_blank, (__u32 __user *)arg)) + return -EFAULT; + break; + } + default: + break; + } + return ret; +} + +static int mxc_elcdif_fb_blank(int blank, struct fb_info *info) +{ + struct mxc_elcdif_fb_data *data = + (struct mxc_elcdif_fb_data *)info->par; + int ret = 0; + + if (data->cur_blank == blank) + return ret; + + data->next_blank = blank; + + if (!g_elcdif_pix_clk_enable) { + clk_enable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = true; + } + ret = mxc_elcdif_blank_panel(blank); + if (ret == 0) + data->cur_blank = blank; + else + return ret; + + if (blank == FB_BLANK_UNBLANK) { + ret = mxc_elcdif_fb_set_par(info); + if (ret) + return ret; + } + + if (data->cur_blank != FB_BLANK_UNBLANK) { + if (g_elcdif_axi_clk_enable) { + clk_disable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = false; + } + if (g_elcdif_pix_clk_enable) { + clk_disable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = false; + } + } else { + if (!g_elcdif_axi_clk_enable) { + clk_enable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = true; + } + if (!g_elcdif_pix_clk_enable) { + clk_enable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = true; + } + } + + return ret; +} + +static int mxc_elcdif_fb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct mxc_elcdif_fb_data *data = + (struct mxc_elcdif_fb_data *)info->par; + unsigned long base = 0; + + if (data->cur_blank != FB_BLANK_UNBLANK) { + dev_err(info->device, "can't do pan display when fb " + "is blank\n"); + return -EINVAL; + } + + if (var->xoffset > 0) { + dev_dbg(info->device, "x panning not supported\n"); + return -EINVAL; + } + + if ((var->yoffset + var->yres > var->yres_virtual)) { + dev_err(info->device, "y panning exceeds\n"); + return -EINVAL; + } + + /* update framebuffer visual */ + base = (var->yoffset * var->xres_virtual + var->xoffset); + base = (var->bits_per_pixel) * base / 8; + base += info->fix.smem_start; + + down(&data->flip_sem); + + __raw_writel(base, elcdif_base + HW_ELCDIF_NEXT_BUF); + + data->panning = 1; + return mxc_elcdif_fb_wait_for_frame_done(info); +} + +static struct fb_ops mxc_elcdif_fb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mxc_elcdif_fb_check_var, + .fb_set_par = mxc_elcdif_fb_set_par, + .fb_setcolreg = mxc_elcdif_fb_setcolreg, + .fb_ioctl = mxc_elcdif_fb_ioctl, + .fb_blank = mxc_elcdif_fb_blank, + .fb_pan_display = mxc_elcdif_fb_pan_display, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +/*! + * Allocates the DRAM memory for the frame buffer. This buffer is remapped + * into a non-cached, non-buffered, memory region to allow palette and pixel + * writes to occur without flushing the cache. Once this area is remapped, + * all virtual memory access to the video memory should occur at the new region. + * + * @param fbi framebuffer information pointer + * + * @return Error code indicating success or failure + */ +static int mxc_elcdif_fb_map_video_memory(struct fb_info *fbi) +{ + if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) + fbi->fix.smem_len = fbi->var.yres_virtual * + fbi->fix.line_length; + + fbi->screen_base = dma_alloc_writecombine(fbi->device, + fbi->fix.smem_len, + (dma_addr_t *)&fbi->fix.smem_start, + GFP_DMA); + if (fbi->screen_base == 0) { + dev_err(fbi->device, "Unable to allocate framebuffer memory\n"); + fbi->fix.smem_len = 0; + fbi->fix.smem_start = 0; + return -EBUSY; + } + + dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n", + (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len); + + fbi->screen_size = fbi->fix.smem_len; + + /* Clear the screen */ + memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); + + return 0; +} + +/*! + * De-allocates the DRAM memory for the frame buffer. + * + * @param fbi framebuffer information pointer + * + * @return Error code indicating success or failure + */ +static int mxc_elcdif_fb_unmap_video_memory(struct fb_info *fbi) +{ + dma_free_writecombine(fbi->device, fbi->fix.smem_len, + fbi->screen_base, fbi->fix.smem_start); + fbi->screen_base = 0; + fbi->fix.smem_start = 0; + fbi->fix.smem_len = 0; + return 0; +} + +static int mxc_elcdif_fb_probe(struct platform_device *pdev) +{ + int ret = 0; + struct mxc_elcdif_fb_data *data; + struct resource *res; + struct fb_info *fbi; + struct mxc_fb_platform_data *pdata = pdev->dev.platform_data; + + fbi = framebuffer_alloc(sizeof(struct mxc_elcdif_fb_data), &pdev->dev); + if (fbi == NULL) { + ret = -ENOMEM; + goto out; + } + + data = (struct mxc_elcdif_fb_data *)fbi->par; + data->cur_blank = data->next_blank = FB_BLANK_UNBLANK; + + fbi->var.activate = FB_ACTIVATE_NOW; + fbi->fbops = &mxc_elcdif_fb_ops; + fbi->flags = FBINFO_FLAG_DEFAULT; + fbi->pseudo_palette = data->pseudo_palette; + + ret = fb_alloc_cmap(&fbi->cmap, 16, 0); + if (ret) + goto out; + + g_elcdif_dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&pdev->dev, "cannot get IRQ resource\n"); + ret = -ENODEV; + goto err0; + } + data->dma_irq = res->start; + + ret = request_irq(data->dma_irq, lcd_irq_handler, 0, + "mxc_elcdif_fb", data); + if (ret) { + dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n", + data->dma_irq, ret); + goto err0; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto err1; + } + elcdif_base = ioremap(res->start, SZ_4K); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + fbi->fix.smem_len = res->end - res->start + 1; + fbi->fix.smem_start = res->start; + fbi->screen_base = ioremap(fbi->fix.smem_start, + fbi->fix.smem_len); + } + + strcpy(fbi->fix.id, "mxc_elcdif_fb"); + + fbi->var.xres = 800; + fbi->var.yres = 480; + + if (pdata && !data->output_pix_fmt) + data->output_pix_fmt = pdata->interface_pix_fmt; + + if (pdata && pdata->mode && pdata->num_modes) + fb_videomode_to_modelist(pdata->mode, pdata->num_modes, + &fbi->modelist); + + if (!fb_mode && pdata && pdata->mode_str) + fb_mode = pdata->mode_str; + + if (fb_mode) { + ret = fb_find_mode(&fbi->var, fbi, fb_mode, NULL, 0, NULL, + default_bpp); + if ((!ret || (ret > 2)) && pdata && pdata->mode && + pdata->num_modes) + fb_find_mode(&fbi->var, fbi, fb_mode, pdata->mode, + pdata->num_modes, NULL, default_bpp); + } + + mxc_elcdif_fb_check_var(&fbi->var, fbi); + + fbi->var.xres_virtual = fbi->var.xres; + fbi->var.yres_virtual = fbi->var.yres * 3; + + mxc_elcdif_fb_set_fix(fbi); + + if (!res || !res->end) + if (mxc_elcdif_fb_map_video_memory(fbi) < 0) { + ret = -ENOMEM; + goto err2; + } + + g_elcdif_axi_clk = clk_get(g_elcdif_dev, "elcdif_axi"); + if (g_elcdif_axi_clk == NULL) { + dev_err(&pdev->dev, "can't get ELCDIF axi clk\n"); + ret = -ENODEV; + goto err3; + } + g_elcdif_pix_clk = clk_get(g_elcdif_dev, "elcdif_pix"); + if (g_elcdif_pix_clk == NULL) { + dev_err(&pdev->dev, "can't get ELCDIF pix clk\n"); + ret = -ENODEV; + goto err3; + } + /* + * Set an appropriate pixel clk rate first, so that we can + * access ELCDIF registers. + */ + clk_set_rate(g_elcdif_pix_clk, 25000000); + + ret = register_framebuffer(fbi); + if (ret) + goto err3; + + platform_set_drvdata(pdev, fbi); + + return 0; +err3: + mxc_elcdif_fb_unmap_video_memory(fbi); +err2: + iounmap(elcdif_base); +err1: + free_irq(data->dma_irq, data); +err0: + fb_dealloc_cmap(&fbi->cmap); + framebuffer_release(fbi); +out: + return ret; +} + +static int mxc_elcdif_fb_remove(struct platform_device *pdev) +{ + struct fb_info *fbi = platform_get_drvdata(pdev); + struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par; + + mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi); + mxc_elcdif_stop(); + release_dotclk_panel(); + mxc_elcdif_dma_release(); + + if (g_elcdif_axi_clk_enable) { + clk_disable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = false; + } + if (g_elcdif_pix_clk_enable) { + clk_disable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = false; + } + clk_put(g_elcdif_axi_clk); + clk_put(g_elcdif_pix_clk); + + free_irq(data->dma_irq, data); + mxc_elcdif_fb_unmap_video_memory(fbi); + + if (&fbi->cmap) + fb_dealloc_cmap(&fbi->cmap); + + unregister_framebuffer(fbi); + framebuffer_release(fbi); + + platform_set_drvdata(pdev, NULL); + return 0; +} + +#ifdef CONFIG_PM +static int mxc_elcdif_fb_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct fb_info *fbi = platform_get_drvdata(pdev); + struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par; + int saved_blank; + + acquire_console_sem(); + fb_set_suspend(fbi, 1); + saved_blank = data->cur_blank; + mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi); + data->next_blank = saved_blank; + if (!g_elcdif_pix_clk_enable) { + clk_enable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = true; + } + mxc_elcdif_stop(); + mxc_elcdif_dma_release(); + if (g_elcdif_pix_clk_enable) { + clk_disable(g_elcdif_pix_clk); + g_elcdif_pix_clk_enable = false; + } + if (g_elcdif_axi_clk_enable) { + clk_disable(g_elcdif_axi_clk); + g_elcdif_axi_clk_enable = false; + } + release_console_sem(); + return 0; +} + +static int mxc_elcdif_fb_resume(struct platform_device *pdev) +{ + struct fb_info *fbi = platform_get_drvdata(pdev); + struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par; + + acquire_console_sem(); + mxc_elcdif_fb_blank(data->next_blank, fbi); + fb_set_suspend(fbi, 0); + release_console_sem(); + + return 0; +} +#else +#define mxc_elcdif_fb_suspend NULL +#define mxc_elcdif_fb_resume NULL +#endif + +static struct platform_driver mxc_elcdif_fb_driver = { + .probe = mxc_elcdif_fb_probe, + .remove = mxc_elcdif_fb_remove, + .suspend = mxc_elcdif_fb_suspend, + .resume = mxc_elcdif_fb_resume, + .driver = { + .name = "mxc_elcdif_fb", + .owner = THIS_MODULE, + }, +}; + +/* + * Parse user specified options (`video=trident:') + * example: + * video=trident:800x600,bpp=16,noaccel + */ +int mxc_elcdif_fb_setup(char *options) +{ + char *opt; + if (!options || !*options) + return 0; + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + + if (!strncmp(opt, "bpp=", 4)) + default_bpp = simple_strtoul(opt + 4, NULL, 0); + else + fb_mode = opt; + } + return 0; +} + +static int __init mxc_elcdif_fb_init(void) +{ + char *option = NULL; + + if (fb_get_options("mxc_elcdif_fb", &option)) + return -ENODEV; + mxc_elcdif_fb_setup(option); + + return platform_driver_register(&mxc_elcdif_fb_driver); +} + +static void __exit mxc_elcdif_fb_exit(void) +{ + platform_driver_unregister(&mxc_elcdif_fb_driver); +} + +module_init(mxc_elcdif_fb_init); +module_exit(mxc_elcdif_fb_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC ELCDIF Framebuffer Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/mxc_epdc_fb.c b/drivers/video/mxc/mxc_epdc_fb.c new file mode 100644 index 000000000000..9de9ffffd464 --- /dev/null +++ b/drivers/video/mxc/mxc_epdc_fb.c @@ -0,0 +1,3786 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on STMP378X LCDIF + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "epdc_regs.h" + +/* + * Enable this define to have a default panel + * loaded during driver initialization + */ +/*#define DEFAULT_PANEL_HW_INIT*/ + +#define NUM_SCREENS_MIN 2 +#define EPDC_NUM_LUTS 16 +#define EPDC_MAX_NUM_UPDATES 20 +#define INVALID_LUT -1 + +#define DEFAULT_TEMP_INDEX 0 +#define DEFAULT_TEMP 20 /* room temp in deg Celsius */ + +#define INIT_UPDATE_MARKER 0x12345678 +#define PAN_UPDATE_MARKER 0x12345679 + +#define POWER_STATE_OFF 0 +#define POWER_STATE_ON 1 + +static unsigned long default_bpp = 16; + +struct update_marker_data { + u32 update_marker; + struct completion update_completion; + int lut_num; +}; + +/* This structure represents a list node containing both + * a memory region allocated as an output buffer for the PxP + * update processing task, and the update description (mode, region, etc.) */ +struct update_data_list { + struct list_head list; + struct mxcfb_update_data upd_data;/* Update parameters */ + dma_addr_t phys_addr; /* Pointer to phys address of processed Y buf */ + void *virt_addr; + u32 epdc_offs; /* Add to buffer pointer to resolve alignment */ + u32 size; + int lut_num; /* Assigned before update is processed into working buffer */ + int collision_mask; /* Set when update results in collision */ + /* Represents other LUTs that we collide with */ + struct update_marker_data *upd_marker_data; + u32 update_order; /* Numeric ordering value for update */ + u32 fb_offset; /* FB offset associated with update */ +}; + +struct mxc_epdc_fb_data { + struct fb_info info; + struct fb_var_screeninfo epdc_fb_var; /* Internal copy of screeninfo + so we can sync changes to it */ + u32 pseudo_palette[16]; + char fw_str[24]; + struct list_head list; + struct mxc_epdc_fb_mode *cur_mode; + struct mxc_epdc_fb_platform_data *pdata; + int blank; + ssize_t map_size; + dma_addr_t phys_start; + u32 fb_offset; + int default_bpp; + int native_width; + int native_height; + int num_screens; + int epdc_irq; + struct device *dev; + int power_state; + struct clk *epdc_clk_axi; + struct clk *epdc_clk_pix; + struct regulator *display_regulator; + struct regulator *vcom_regulator; + bool fw_default_load; + + /* FB elements related to EPDC updates */ + bool in_init; + bool hw_ready; + bool waiting_for_idle; + u32 auto_mode; + u32 upd_scheme; + struct update_data_list *upd_buf_queue; + struct update_data_list *upd_buf_free_list; + struct update_data_list *upd_buf_collision_list; + struct update_data_list *cur_update; + spinlock_t queue_lock; + int trt_entries; + int temp_index; + u8 *temp_range_bounds; + struct mxcfb_waveform_modes wv_modes; + u32 *waveform_buffer_virt; + u32 waveform_buffer_phys; + u32 waveform_buffer_size; + u32 *working_buffer_virt; + u32 working_buffer_phys; + u32 working_buffer_size; + u32 order_cnt; + struct update_marker_data update_marker_array[EPDC_MAX_NUM_UPDATES]; + u32 lut_update_order[EPDC_NUM_LUTS]; + struct completion updates_done; + struct delayed_work epdc_done_work; + struct workqueue_struct *epdc_submit_workqueue; + struct work_struct epdc_submit_work; + bool waiting_for_wb; + bool waiting_for_lut; + struct completion update_res_free; + struct mutex power_mutex; + bool powering_down; + int pwrdown_delay; + + /* FB elements related to PxP DMA */ + struct completion pxp_tx_cmpl; + struct pxp_channel *pxp_chan; + struct pxp_config_data pxp_conf; + struct dma_async_tx_descriptor *txd; + dma_cookie_t cookie; + struct scatterlist sg[2]; + struct mutex pxp_mutex; /* protects access to PxP */ +}; + +struct waveform_data_header { + unsigned int wi0; + unsigned int wi1; + unsigned int wi2; + unsigned int wi3; + unsigned int wi4; + unsigned int wi5; + unsigned int wi6; + unsigned int xwia:24; + unsigned int cs1:8; + unsigned int wmta:24; + unsigned int fvsn:8; + unsigned int luts:8; + unsigned int mc:8; + unsigned int trc:8; + unsigned int reserved0_0:8; + unsigned int eb:8; + unsigned int sb:8; + unsigned int reserved0_1:8; + unsigned int reserved0_2:8; + unsigned int reserved0_3:8; + unsigned int reserved0_4:8; + unsigned int reserved0_5:8; + unsigned int cs2:8; +}; + +struct mxcfb_waveform_data_file { + struct waveform_data_header wdh; + u32 *data; /* Temperature Range Table + Waveform Data */ +}; + +void __iomem *epdc_base; + +struct mxc_epdc_fb_data *g_fb_data; + +/* forward declaration */ +static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data, + int temp); +static void mxc_epdc_fb_flush_updates(struct mxc_epdc_fb_data *fb_data); +static int mxc_epdc_fb_blank(int blank, struct fb_info *info); +static int mxc_epdc_fb_init_hw(struct fb_info *info); +static int pxp_process_update(struct mxc_epdc_fb_data *fb_data, + u32 src_width, u32 src_height, + struct mxcfb_rect *update_region, + int x_start_offs); +static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat); + +static void draw_mode0(struct mxc_epdc_fb_data *fb_data); +static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data); + + +#ifdef DEBUG +static void dump_pxp_config(struct mxc_epdc_fb_data *fb_data, + struct pxp_config_data *pxp_conf) +{ + dev_err(fb_data->dev, "S0 fmt 0x%x", + pxp_conf->s0_param.pixel_fmt); + dev_err(fb_data->dev, "S0 width 0x%x", + pxp_conf->s0_param.width); + dev_err(fb_data->dev, "S0 height 0x%x", + pxp_conf->s0_param.height); + dev_err(fb_data->dev, "S0 ckey 0x%x", + pxp_conf->s0_param.color_key); + dev_err(fb_data->dev, "S0 ckey en 0x%x", + pxp_conf->s0_param.color_key_enable); + + dev_err(fb_data->dev, "OL0 combine en 0x%x", + pxp_conf->ol_param[0].combine_enable); + dev_err(fb_data->dev, "OL0 fmt 0x%x", + pxp_conf->ol_param[0].pixel_fmt); + dev_err(fb_data->dev, "OL0 width 0x%x", + pxp_conf->ol_param[0].width); + dev_err(fb_data->dev, "OL0 height 0x%x", + pxp_conf->ol_param[0].height); + dev_err(fb_data->dev, "OL0 ckey 0x%x", + pxp_conf->ol_param[0].color_key); + dev_err(fb_data->dev, "OL0 ckey en 0x%x", + pxp_conf->ol_param[0].color_key_enable); + dev_err(fb_data->dev, "OL0 alpha 0x%x", + pxp_conf->ol_param[0].global_alpha); + dev_err(fb_data->dev, "OL0 alpha en 0x%x", + pxp_conf->ol_param[0].global_alpha_enable); + dev_err(fb_data->dev, "OL0 local alpha en 0x%x", + pxp_conf->ol_param[0].local_alpha_enable); + + dev_err(fb_data->dev, "Out fmt 0x%x", + pxp_conf->out_param.pixel_fmt); + dev_err(fb_data->dev, "Out width 0x%x", + pxp_conf->out_param.width); + dev_err(fb_data->dev, "Out height 0x%x", + pxp_conf->out_param.height); + + dev_err(fb_data->dev, + "drect left 0x%x right 0x%x width 0x%x height 0x%x", + pxp_conf->proc_data.drect.left, pxp_conf->proc_data.drect.top, + pxp_conf->proc_data.drect.width, + pxp_conf->proc_data.drect.height); + dev_err(fb_data->dev, + "srect left 0x%x right 0x%x width 0x%x height 0x%x", + pxp_conf->proc_data.srect.left, pxp_conf->proc_data.srect.top, + pxp_conf->proc_data.srect.width, + pxp_conf->proc_data.srect.height); + dev_err(fb_data->dev, "Scaling en 0x%x", pxp_conf->proc_data.scaling); + dev_err(fb_data->dev, "HFlip en 0x%x", pxp_conf->proc_data.hflip); + dev_err(fb_data->dev, "VFlip en 0x%x", pxp_conf->proc_data.vflip); + dev_err(fb_data->dev, "Rotation 0x%x", pxp_conf->proc_data.rotate); + dev_err(fb_data->dev, "BG Color 0x%x", pxp_conf->proc_data.bgcolor); +} + +static void dump_epdc_reg(void) +{ + printk(KERN_DEBUG "\n\n"); + printk(KERN_DEBUG "EPDC_CTRL 0x%x\n", __raw_readl(EPDC_CTRL)); + printk(KERN_DEBUG "EPDC_WVADDR 0x%x\n", __raw_readl(EPDC_WVADDR)); + printk(KERN_DEBUG "EPDC_WB_ADDR 0x%x\n", __raw_readl(EPDC_WB_ADDR)); + printk(KERN_DEBUG "EPDC_RES 0x%x\n", __raw_readl(EPDC_RES)); + printk(KERN_DEBUG "EPDC_FORMAT 0x%x\n", __raw_readl(EPDC_FORMAT)); + printk(KERN_DEBUG "EPDC_FIFOCTRL 0x%x\n", __raw_readl(EPDC_FIFOCTRL)); + printk(KERN_DEBUG "EPDC_UPD_ADDR 0x%x\n", __raw_readl(EPDC_UPD_ADDR)); + printk(KERN_DEBUG "EPDC_UPD_FIXED 0x%x\n", __raw_readl(EPDC_UPD_FIXED)); + printk(KERN_DEBUG "EPDC_UPD_CORD 0x%x\n", __raw_readl(EPDC_UPD_CORD)); + printk(KERN_DEBUG "EPDC_UPD_SIZE 0x%x\n", __raw_readl(EPDC_UPD_SIZE)); + printk(KERN_DEBUG "EPDC_UPD_CTRL 0x%x\n", __raw_readl(EPDC_UPD_CTRL)); + printk(KERN_DEBUG "EPDC_TEMP 0x%x\n", __raw_readl(EPDC_TEMP)); + printk(KERN_DEBUG "EPDC_TCE_CTRL 0x%x\n", __raw_readl(EPDC_TCE_CTRL)); + printk(KERN_DEBUG "EPDC_TCE_SDCFG 0x%x\n", __raw_readl(EPDC_TCE_SDCFG)); + printk(KERN_DEBUG "EPDC_TCE_GDCFG 0x%x\n", __raw_readl(EPDC_TCE_GDCFG)); + printk(KERN_DEBUG "EPDC_TCE_HSCAN1 0x%x\n", __raw_readl(EPDC_TCE_HSCAN1)); + printk(KERN_DEBUG "EPDC_TCE_HSCAN2 0x%x\n", __raw_readl(EPDC_TCE_HSCAN2)); + printk(KERN_DEBUG "EPDC_TCE_VSCAN 0x%x\n", __raw_readl(EPDC_TCE_VSCAN)); + printk(KERN_DEBUG "EPDC_TCE_OE 0x%x\n", __raw_readl(EPDC_TCE_OE)); + printk(KERN_DEBUG "EPDC_TCE_POLARITY 0x%x\n", __raw_readl(EPDC_TCE_POLARITY)); + printk(KERN_DEBUG "EPDC_TCE_TIMING1 0x%x\n", __raw_readl(EPDC_TCE_TIMING1)); + printk(KERN_DEBUG "EPDC_TCE_TIMING2 0x%x\n", __raw_readl(EPDC_TCE_TIMING2)); + printk(KERN_DEBUG "EPDC_TCE_TIMING3 0x%x\n", __raw_readl(EPDC_TCE_TIMING3)); + printk(KERN_DEBUG "EPDC_IRQ_MASK 0x%x\n", __raw_readl(EPDC_IRQ_MASK)); + printk(KERN_DEBUG "EPDC_IRQ 0x%x\n", __raw_readl(EPDC_IRQ)); + printk(KERN_DEBUG "EPDC_STATUS_LUTS 0x%x\n", __raw_readl(EPDC_STATUS_LUTS)); + printk(KERN_DEBUG "EPDC_STATUS_NEXTLUT 0x%x\n", __raw_readl(EPDC_STATUS_NEXTLUT)); + printk(KERN_DEBUG "EPDC_STATUS_COL 0x%x\n", __raw_readl(EPDC_STATUS_COL)); + printk(KERN_DEBUG "EPDC_STATUS 0x%x\n", __raw_readl(EPDC_STATUS)); + printk(KERN_DEBUG "EPDC_DEBUG 0x%x\n", __raw_readl(EPDC_DEBUG)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT0 0x%x\n", __raw_readl(EPDC_DEBUG_LUT0)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT1 0x%x\n", __raw_readl(EPDC_DEBUG_LUT1)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT2 0x%x\n", __raw_readl(EPDC_DEBUG_LUT2)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT3 0x%x\n", __raw_readl(EPDC_DEBUG_LUT3)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT4 0x%x\n", __raw_readl(EPDC_DEBUG_LUT4)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT5 0x%x\n", __raw_readl(EPDC_DEBUG_LUT5)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT6 0x%x\n", __raw_readl(EPDC_DEBUG_LUT6)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT7 0x%x\n", __raw_readl(EPDC_DEBUG_LUT7)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT8 0x%x\n", __raw_readl(EPDC_DEBUG_LUT8)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT9 0x%x\n", __raw_readl(EPDC_DEBUG_LUT9)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT10 0x%x\n", __raw_readl(EPDC_DEBUG_LUT10)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT11 0x%x\n", __raw_readl(EPDC_DEBUG_LUT11)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT12 0x%x\n", __raw_readl(EPDC_DEBUG_LUT12)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT13 0x%x\n", __raw_readl(EPDC_DEBUG_LUT13)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT14 0x%x\n", __raw_readl(EPDC_DEBUG_LUT14)); + printk(KERN_DEBUG "EPDC_DEBUG_LUT15 0x%x\n", __raw_readl(EPDC_DEBUG_LUT15)); + printk(KERN_DEBUG "EPDC_GPIO 0x%x\n", __raw_readl(EPDC_GPIO)); + printk(KERN_DEBUG "EPDC_VERSION 0x%x\n", __raw_readl(EPDC_VERSION)); + printk(KERN_DEBUG "\n\n"); +} + +static void dump_update_data(struct device *dev, + struct update_data_list *upd_data_list) +{ + dev_err(dev, + "X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, LUT = %d, Coll Mask = %d\n", + upd_data_list->upd_data.update_region.left, + upd_data_list->upd_data.update_region.top, + upd_data_list->upd_data.update_region.width, + upd_data_list->upd_data.update_region.height, + upd_data_list->upd_data.waveform_mode, upd_data_list->lut_num, + upd_data_list->collision_mask); +} + +static void dump_collision_list(struct mxc_epdc_fb_data *fb_data) +{ + struct update_data_list *plist; + + dev_err(fb_data->dev, "Collision List:\n"); + if (list_empty(&fb_data->upd_buf_collision_list->list)) + dev_err(fb_data->dev, "Empty"); + list_for_each_entry(plist, &fb_data->upd_buf_collision_list->list, list) { + dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ", + (u32)plist->virt_addr, plist->phys_addr); + dump_update_data(fb_data->dev, plist); + } +} + +static void dump_free_list(struct mxc_epdc_fb_data *fb_data) +{ + struct update_data_list *plist; + + dev_err(fb_data->dev, "Free List:\n"); + if (list_empty(&fb_data->upd_buf_free_list->list)) + dev_err(fb_data->dev, "Empty"); + list_for_each_entry(plist, &fb_data->upd_buf_free_list->list, list) { + dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ", + (u32)plist->virt_addr, plist->phys_addr); + dump_update_data(fb_data->dev, plist); + } +} + +static void dump_queue(struct mxc_epdc_fb_data *fb_data) +{ + struct update_data_list *plist; + + dev_err(fb_data->dev, "Queue:\n"); + if (list_empty(&fb_data->upd_buf_queue->list)) + dev_err(fb_data->dev, "Empty"); + list_for_each_entry(plist, &fb_data->upd_buf_queue->list, list) { + dev_err(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ", + (u32)plist->virt_addr, plist->phys_addr); + dump_update_data(fb_data->dev, plist); + } +} + +static void dump_all_updates(struct mxc_epdc_fb_data *fb_data) +{ + dump_free_list(fb_data); + dump_queue(fb_data); + dump_collision_list(fb_data); + dev_err(fb_data->dev, "Current update being processed:\n"); + if (fb_data->cur_update == NULL) + dev_err(fb_data->dev, "No current update\n"); + else + dump_update_data(fb_data->dev, fb_data->cur_update); +} +#else +static inline void dump_pxp_config(struct mxc_epdc_fb_data *fb_data, + struct pxp_config_data *pxp_conf) {} +static inline void dump_epdc_reg(void) {} +static inline void dump_update_data(struct device *dev, + struct update_data_list *upd_data_list) {} +static inline void dump_collision_list(struct mxc_epdc_fb_data *fb_data) {} +static inline void dump_free_list(struct mxc_epdc_fb_data *fb_data) {} +static inline void dump_queue(struct mxc_epdc_fb_data *fb_data) {} +static inline void dump_all_updates(struct mxc_epdc_fb_data *fb_data) {} + +#endif + + +/******************************************************** + * Start Low-Level EPDC Functions + ********************************************************/ + +static inline void epdc_lut_complete_intr(u32 lut_num, bool enable) +{ + if (enable) + __raw_writel(1 << lut_num, EPDC_IRQ_MASK_SET); + else + __raw_writel(1 << lut_num, EPDC_IRQ_MASK_CLEAR); +} + +static inline void epdc_working_buf_intr(bool enable) +{ + if (enable) + __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_SET); + else + __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_CLEAR); +} + +static inline void epdc_clear_working_buf_irq(void) +{ + __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ | EPDC_IRQ_LUT_COL_IRQ, + EPDC_IRQ_CLEAR); +} + +static inline void epdc_set_temp(u32 temp) +{ + __raw_writel(temp, EPDC_TEMP); +} + +static inline void epdc_set_screen_res(u32 width, u32 height) +{ + u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width; + __raw_writel(val, EPDC_RES); +} + +static inline void epdc_set_update_addr(u32 addr) +{ + __raw_writel(addr, EPDC_UPD_ADDR); +} + +static inline void epdc_set_update_coord(u32 x, u32 y) +{ + u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x; + __raw_writel(val, EPDC_UPD_CORD); +} + +static inline void epdc_set_update_dimensions(u32 width, u32 height) +{ + u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width; + __raw_writel(val, EPDC_UPD_SIZE); +} + +static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode, + bool use_test_mode, u32 np_val) +{ + u32 reg_val = 0; + + if (use_test_mode) { + reg_val |= + ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) & + EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN; + + __raw_writel(reg_val, EPDC_UPD_FIXED); + + reg_val = EPDC_UPD_CTRL_USE_FIXED; + } else { + __raw_writel(reg_val, EPDC_UPD_FIXED); + } + + reg_val |= + ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) & + EPDC_UPD_CTRL_LUT_SEL_MASK) | + ((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) & + EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) | + update_mode; + + __raw_writel(reg_val, EPDC_UPD_CTRL); +} + +static inline bool epdc_is_lut_complete(u32 lut_num) +{ + u32 val = __raw_readl(EPDC_IRQ); + bool is_compl = val & (1 << lut_num) ? true : false; + + return is_compl; +} + +static inline void epdc_clear_lut_complete_irq(u32 lut_num) +{ + __raw_writel(1 << lut_num, EPDC_IRQ_CLEAR); +} + +static inline bool epdc_is_lut_active(u32 lut_num) +{ + u32 val = __raw_readl(EPDC_STATUS_LUTS); + bool is_active = val & (1 << lut_num) ? true : false; + + return is_active; +} + +static inline bool epdc_any_luts_active(void) +{ + bool any_active = __raw_readl(EPDC_STATUS_LUTS) ? true : false; + + return any_active; +} + +static inline bool epdc_any_luts_available(void) +{ + bool luts_available = + (__raw_readl(EPDC_STATUS_NEXTLUT) & + EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID) ? true : false; + return luts_available; +} + +static inline int epdc_get_next_lut(void) +{ + u32 val = + __raw_readl(EPDC_STATUS_NEXTLUT) & + EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK; + return val; +} + +static inline bool epdc_is_working_buffer_busy(void) +{ + u32 val = __raw_readl(EPDC_STATUS); + bool is_busy = (val & EPDC_STATUS_WB_BUSY) ? true : false; + + return is_busy; +} + +static inline bool epdc_is_working_buffer_complete(void) +{ + u32 val = __raw_readl(EPDC_IRQ); + bool is_compl = (val & EPDC_IRQ_WB_CMPLT_IRQ) ? true : false; + + return is_compl; +} + +static inline bool epdc_is_collision(void) +{ + u32 val = __raw_readl(EPDC_IRQ); + return (val & EPDC_IRQ_LUT_COL_IRQ) ? true : false; +} + +static inline int epdc_get_colliding_luts(void) +{ + u32 val = __raw_readl(EPDC_STATUS_COL); + return val; +} + +static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end, + u32 hsync_width, u32 hsync_line_length) +{ + u32 reg_val = + ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) & + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK) + | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) & + EPDC_TCE_HSCAN1_LINE_SYNC_MASK); + __raw_writel(reg_val, EPDC_TCE_HSCAN1); + + reg_val = + ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) & + EPDC_TCE_HSCAN2_LINE_BEGIN_MASK) + | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) & + EPDC_TCE_HSCAN2_LINE_END_MASK); + __raw_writel(reg_val, EPDC_TCE_HSCAN2); +} + +static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end, + u32 vsync_width) +{ + u32 reg_val = + ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) & + EPDC_TCE_VSCAN_FRAME_BEGIN_MASK) + | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) & + EPDC_TCE_VSCAN_FRAME_END_MASK) + | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) & + EPDC_TCE_VSCAN_FRAME_SYNC_MASK); + __raw_writel(reg_val, EPDC_TCE_VSCAN); +} + +void epdc_init_settings(struct mxc_epdc_fb_data *fb_data) +{ + struct mxc_epdc_fb_mode *epdc_mode = fb_data->cur_mode; + struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var; + u32 reg_val; + int num_ce; + + /* Reset */ + __raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_SET); + while (!(__raw_readl(EPDC_CTRL) & EPDC_CTRL_CLKGATE)) + ; + __raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_CLEAR); + + /* Enable clock gating (clear to enable) */ + __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR); + while (__raw_readl(EPDC_CTRL) & (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE)) + ; + + /* EPDC_CTRL */ + reg_val = __raw_readl(EPDC_CTRL); + reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK; + reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP; + reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK; + reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP; + __raw_writel(reg_val, EPDC_CTRL_SET); + + /* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */ + reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT + | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N + | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) & + EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK); + __raw_writel(reg_val, EPDC_FORMAT); + + /* EPDC_FIFOCTRL (disabled) */ + reg_val = + ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK) + | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK) + | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK); + __raw_writel(reg_val, EPDC_FIFOCTRL); + + /* EPDC_TEMP - Use default temp to get index */ + epdc_set_temp(mxc_epdc_fb_get_temp_index(fb_data, DEFAULT_TEMP)); + + /* EPDC_RES */ + epdc_set_screen_res(epdc_mode->vmode->xres, epdc_mode->vmode->yres); + + /* + * EPDC_TCE_CTRL + * VSCAN_HOLDOFF = 4 + * VCOM_MODE = MANUAL + * VCOM_VAL = 0 + * DDR_MODE = DISABLED + * LVDS_MODE_CE = DISABLED + * LVDS_MODE = DISABLED + * DUAL_SCAN = DISABLED + * SDDO_WIDTH = 8bit + * PIXELS_PER_SDCLK = 4 + */ + reg_val = + ((epdc_mode->vscan_holdoff << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) & + EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK) + | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4; + __raw_writel(reg_val, EPDC_TCE_CTRL); + + /* EPDC_TCE_HSCAN */ + epdc_set_horizontal_timing(screeninfo->left_margin, + screeninfo->right_margin, + screeninfo->hsync_len, + screeninfo->hsync_len); + + /* EPDC_TCE_VSCAN */ + epdc_set_vertical_timing(screeninfo->upper_margin, + screeninfo->lower_margin, + screeninfo->vsync_len); + + /* EPDC_TCE_OE */ + reg_val = + ((epdc_mode->sdoed_width << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) & + EPDC_TCE_OE_SDOED_WIDTH_MASK) + | ((epdc_mode->sdoed_delay << EPDC_TCE_OE_SDOED_DLY_OFFSET) & + EPDC_TCE_OE_SDOED_DLY_MASK) + | ((epdc_mode->sdoez_width << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) & + EPDC_TCE_OE_SDOEZ_WIDTH_MASK) + | ((epdc_mode->sdoez_delay << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) & + EPDC_TCE_OE_SDOEZ_DLY_MASK); + __raw_writel(reg_val, EPDC_TCE_OE); + + /* EPDC_TCE_TIMING1 */ + __raw_writel(0x0, EPDC_TCE_TIMING1); + + /* EPDC_TCE_TIMING2 */ + reg_val = + ((epdc_mode->gdclk_hp_offs << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) & + EPDC_TCE_TIMING2_GDCLK_HP_MASK) + | ((epdc_mode->gdsp_offs << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) & + EPDC_TCE_TIMING2_GDSP_OFFSET_MASK); + __raw_writel(reg_val, EPDC_TCE_TIMING2); + + /* EPDC_TCE_TIMING3 */ + reg_val = + ((epdc_mode->gdoe_offs << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) & + EPDC_TCE_TIMING3_GDOE_OFFSET_MASK) + | ((epdc_mode->gdclk_offs << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) & + EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK); + __raw_writel(reg_val, EPDC_TCE_TIMING3); + + /* + * EPDC_TCE_SDCFG + * SDCLK_HOLD = 1 + * SDSHR = 1 + * NUM_CE = 1 + * SDDO_REFORMAT = FLIP_PIXELS + * SDDO_INVERT = DISABLED + * PIXELS_PER_CE = display horizontal resolution + */ + num_ce = epdc_mode->num_ce; + if (num_ce == 0) + num_ce = 1; + reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR + | ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & + EPDC_TCE_SDCFG_NUM_CE_MASK) + | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS + | ((epdc_mode->vmode->xres/num_ce << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) & + EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK); + __raw_writel(reg_val, EPDC_TCE_SDCFG); + + /* + * EPDC_TCE_GDCFG + * GDRL = 1 + * GDOE_MODE = 0; + * GDSP_MODE = 0; + */ + reg_val = EPDC_TCE_SDCFG_GDRL; + __raw_writel(reg_val, EPDC_TCE_GDCFG); + + /* + * EPDC_TCE_POLARITY + * SDCE_POL = ACTIVE LOW + * SDLE_POL = ACTIVE HIGH + * SDOE_POL = ACTIVE HIGH + * GDOE_POL = ACTIVE HIGH + * GDSP_POL = ACTIVE LOW + */ + reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH + | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH + | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH; + __raw_writel(reg_val, EPDC_TCE_POLARITY); + + /* EPDC_IRQ_MASK */ + __raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_MASK); + + /* + * EPDC_GPIO + * PWRCOM = ? + * PWRCTRL = ? + * BDR = ? + */ + reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK) + | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK); + __raw_writel(reg_val, EPDC_GPIO); +} + +static void epdc_powerup(struct mxc_epdc_fb_data *fb_data) +{ + int ret = 0; + mutex_lock(&fb_data->power_mutex); + + /* + * If power down request is pending, clear + * powering_down to cancel the request. + */ + if (fb_data->powering_down) + fb_data->powering_down = false; + + if (fb_data->power_state == POWER_STATE_ON) { + mutex_unlock(&fb_data->power_mutex); + return; + } + + dev_dbg(fb_data->dev, "EPDC Powerup\n"); + + /* Enable pins used by EPDC */ + if (fb_data->pdata->enable_pins) + fb_data->pdata->enable_pins(); + + /* Enable clocks to EPDC */ + clk_enable(fb_data->epdc_clk_axi); + clk_enable(fb_data->epdc_clk_pix); + + __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR); + + /* Enable power to the EPD panel */ + ret = regulator_enable(fb_data->display_regulator); + if (IS_ERR((void *)ret)) { + dev_err(fb_data->dev, "Unable to enable DISPLAY regulator." + "err = 0x%x\n", ret); + mutex_unlock(&fb_data->power_mutex); + return; + } + ret = regulator_enable(fb_data->vcom_regulator); + if (IS_ERR((void *)ret)) { + dev_err(fb_data->dev, "Unable to enable VCOM regulator." + "err = 0x%x\n", ret); + mutex_unlock(&fb_data->power_mutex); + return; + } + + fb_data->power_state = POWER_STATE_ON; + + mutex_unlock(&fb_data->power_mutex); +} + +static void epdc_powerdown(struct mxc_epdc_fb_data *fb_data) +{ + mutex_lock(&fb_data->power_mutex); + + /* If powering_down has been cleared, a powerup + * request is pre-empting this powerdown request. + */ + if (!fb_data->powering_down + || (fb_data->power_state == POWER_STATE_OFF)) { + mutex_unlock(&fb_data->power_mutex); + return; + } + + dev_dbg(fb_data->dev, "EPDC Powerdown\n"); + + /* Disable power to the EPD panel */ + regulator_disable(fb_data->vcom_regulator); + regulator_disable(fb_data->display_regulator); + + /* Disable clocks to EPDC */ + __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET); + clk_disable(fb_data->epdc_clk_pix); + clk_disable(fb_data->epdc_clk_axi); + + /* Disable pins used by EPDC (to prevent leakage current) */ + if (fb_data->pdata->disable_pins) + fb_data->pdata->disable_pins(); + + fb_data->power_state = POWER_STATE_OFF; + fb_data->powering_down = false; + + mutex_unlock(&fb_data->power_mutex); +} + +static void epdc_init_sequence(struct mxc_epdc_fb_data *fb_data) +{ + /* Initialize EPDC, passing pointer to EPDC registers */ + epdc_init_settings(fb_data); + __raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR); + __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR); + epdc_powerup(fb_data); + draw_mode0(fb_data); + epdc_powerdown(fb_data); +} + +static int mxc_epdc_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) +{ + u32 len; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + + if (offset < info->fix.smem_len) { + /* mapping framebuffer memory */ + len = info->fix.smem_len - offset; + vma->vm_pgoff = (info->fix.smem_start + offset) >> PAGE_SHIFT; + } else + return -EINVAL; + + len = PAGE_ALIGN(len); + if (vma->vm_end - vma->vm_start > len) + return -EINVAL; + + /* make buffers bufferable */ + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + vma->vm_flags |= VM_IO | VM_RESERVED; + + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) { + dev_dbg(info->device, "mmap remap_pfn_range failed\n"); + return -ENOBUFS; + } + + return 0; +} + +static int mxc_epdc_fb_setcolreg(u_int regno, u_int red, u_int green, + u_int blue, u_int transp, struct fb_info *info) +{ + if (regno >= 256) /* no. of hw registers */ + return 1; + /* + * Program hardware... do anything you want with transp + */ + + /* grayscale works only partially under directcolor */ + if (info->var.grayscale) { + /* grayscale = 0.30*R + 0.59*G + 0.11*B */ + red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; + } + +#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16) + switch (info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + case FB_VISUAL_PSEUDOCOLOR: + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); + break; + case FB_VISUAL_DIRECTCOLOR: + red = CNVT_TOHW(red, 8); /* expect 8 bit DAC */ + green = CNVT_TOHW(green, 8); + blue = CNVT_TOHW(blue, 8); + /* hey, there is bug in transp handling... */ + transp = CNVT_TOHW(transp, 8); + break; + } +#undef CNVT_TOHW + /* Truecolor has hardware independent palette */ + if (info->fix.visual == FB_VISUAL_TRUECOLOR) { + + if (regno >= 16) + return 1; + + ((u32 *) (info->pseudo_palette))[regno] = + (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + } + return 0; +} + +static void adjust_coordinates(struct mxc_epdc_fb_data *fb_data, + struct mxcfb_rect *update_region, struct mxcfb_rect *adj_update_region) +{ + struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var; + u32 rotation = fb_data->epdc_fb_var.rotate; + u32 temp; + + /* If adj_update_region == NULL, pass result back in update_region */ + /* If adj_update_region == valid, use it to pass back result */ + if (adj_update_region) + switch (rotation) { + case FB_ROTATE_UR: + adj_update_region->top = update_region->top; + adj_update_region->left = update_region->left; + adj_update_region->width = update_region->width; + adj_update_region->height = update_region->height; + break; + case FB_ROTATE_CW: + adj_update_region->top = update_region->left; + adj_update_region->left = screeninfo->yres - + (update_region->top + update_region->height); + adj_update_region->width = update_region->height; + adj_update_region->height = update_region->width; + break; + case FB_ROTATE_UD: + adj_update_region->width = update_region->width; + adj_update_region->height = update_region->height; + adj_update_region->top = screeninfo->yres - + (update_region->top + update_region->height); + adj_update_region->left = screeninfo->xres - + (update_region->left + update_region->width); + break; + case FB_ROTATE_CCW: + adj_update_region->left = update_region->top; + adj_update_region->top = screeninfo->xres - + (update_region->left + update_region->width); + adj_update_region->width = update_region->height; + adj_update_region->height = update_region->width; + break; + } + else + switch (rotation) { + case FB_ROTATE_UR: + /* No adjustment needed */ + break; + case FB_ROTATE_CW: + temp = update_region->top; + update_region->top = update_region->left; + update_region->left = screeninfo->yres - + (temp + update_region->height); + temp = update_region->width; + update_region->width = update_region->height; + update_region->height = temp; + break; + case FB_ROTATE_UD: + update_region->top = screeninfo->yres - + (update_region->top + update_region->height); + update_region->left = screeninfo->xres - + (update_region->left + update_region->width); + break; + case FB_ROTATE_CCW: + temp = update_region->left; + update_region->left = update_region->top; + update_region->top = screeninfo->xres - + (temp + update_region->width); + temp = update_region->width; + update_region->width = update_region->height; + update_region->height = temp; + break; + } +} + +/* + * Set fixed framebuffer parameters based on variable settings. + * + * @param info framebuffer information pointer + */ +static int mxc_epdc_fb_set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + + fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; + + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + if (var->grayscale) + fix->visual = FB_VISUAL_STATIC_PSEUDOCOLOR; + else + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 1; + fix->ypanstep = 1; + + return 0; +} + +/* + * This routine actually sets the video mode. It's in here where we + * the hardware state info->par and fix which can be affected by the + * change in par. For this driver it doesn't do much. + * + */ +static int mxc_epdc_fb_set_par(struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info; + struct pxp_config_data *pxp_conf = &fb_data->pxp_conf; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + struct fb_var_screeninfo *screeninfo = &fb_data->info.var; + struct mxc_epdc_fb_mode *epdc_modes = fb_data->pdata->epdc_mode; + int i; + int ret; + unsigned long flags; + + /* + * Can't change the FB parameters until current updates have completed. + * This function returns when all active updates are done. + */ + mxc_epdc_fb_flush_updates(fb_data); + + spin_lock_irqsave(&fb_data->queue_lock, flags); + fb_data->epdc_fb_var = *screeninfo; + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + + mutex_lock(&fb_data->pxp_mutex); + + /* + * Update PxP config data (used to process FB regions for updates) + * based on FB info and processing tasks required + */ + + /* Initialize non-channel-specific PxP parameters */ + proc_data->drect.left = proc_data->srect.left = 0; + proc_data->drect.top = proc_data->srect.top = 0; + proc_data->drect.width = proc_data->srect.width = screeninfo->xres; + proc_data->drect.height = proc_data->srect.height = screeninfo->yres; + proc_data->scaling = 0; + proc_data->hflip = 0; + proc_data->vflip = 0; + proc_data->rotate = screeninfo->rotate; + proc_data->bgcolor = 0; + proc_data->overlay_state = 0; + proc_data->lut_transform = PXP_LUT_NONE; + + /* + * configure S0 channel parameters + * Parameters should match FB format/width/height + */ + if (screeninfo->grayscale) + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_GREY; + else { + switch (screeninfo->bits_per_pixel) { + case 16: + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565; + break; + case 24: + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB24; + break; + case 32: + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB32; + break; + default: + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565; + break; + } + } + pxp_conf->s0_param.width = screeninfo->xres_virtual; + pxp_conf->s0_param.height = screeninfo->yres; + pxp_conf->s0_param.color_key = -1; + pxp_conf->s0_param.color_key_enable = false; + + /* + * Initialize Output channel parameters + * Output is Y-only greyscale + * Output width/height will vary based on update region size + */ + pxp_conf->out_param.width = screeninfo->xres; + pxp_conf->out_param.height = screeninfo->yres; + pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY; + + mutex_unlock(&fb_data->pxp_mutex); + + /* + * If HW not yet initialized, check to see if we are being sent + * an initialization request. + */ + if (!fb_data->hw_ready) { + struct fb_videomode mode; + bool found_match = false; + u32 xres_temp; + + fb_var_to_videomode(&mode, screeninfo); + + /* When comparing requested fb mode, + we need to use unrotated dimensions */ + if ((screeninfo->rotate == FB_ROTATE_CW) || + (screeninfo->rotate == FB_ROTATE_CCW)) { + xres_temp = mode.xres; + mode.xres = mode.yres; + mode.yres = xres_temp; + } + + /* Match videomode against epdc modes */ + for (i = 0; i < fb_data->pdata->num_modes; i++) { + if (!fb_mode_is_equal(epdc_modes[i].vmode, &mode)) + continue; + fb_data->cur_mode = &epdc_modes[i]; + found_match = true; + break; + } + + if (!found_match) { + dev_err(fb_data->dev, + "Failed to match requested video mode\n"); + return EINVAL; + } + + /* Found a match - Grab timing params */ + screeninfo->left_margin = mode.left_margin; + screeninfo->right_margin = mode.right_margin; + screeninfo->upper_margin = mode.upper_margin; + screeninfo->lower_margin = mode.lower_margin; + screeninfo->hsync_len = mode.hsync_len; + screeninfo->vsync_len = mode.vsync_len; + + /* Initialize EPDC settings and init panel */ + ret = + mxc_epdc_fb_init_hw((struct fb_info *)fb_data); + if (ret) { + dev_err(fb_data->dev, + "Failed to load panel waveform data\n"); + return ret; + } + } + + mxc_epdc_fb_set_fix(info); + + return 0; +} + +static int mxc_epdc_fb_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info; + + if (!var->xres) + var->xres = 1; + if (!var->yres) + var->yres = 1; + + if (var->xres_virtual < var->xoffset + var->xres) + var->xres_virtual = var->xoffset + var->xres; + if (var->yres_virtual < var->yoffset + var->yres) + var->yres_virtual = var->yoffset + var->yres; + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8)) + var->bits_per_pixel = default_bpp; + + switch (var->bits_per_pixel) { + case 8: + if (var->grayscale != 0) { + /* + * For 8-bit grayscale, R, G, and B offset are equal. + * + */ + var->red.length = 8; + var->red.offset = 0; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 0; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + } else { + var->red.length = 3; + var->red.offset = 5; + var->red.msb_right = 0; + + var->green.length = 3; + var->green.offset = 2; + var->green.msb_right = 0; + + var->blue.length = 2; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + } + break; + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + switch (var->rotate) { + case FB_ROTATE_UR: + case FB_ROTATE_UD: + var->xres = fb_data->native_width; + var->yres = fb_data->native_height; + break; + case FB_ROTATE_CW: + case FB_ROTATE_CCW: + var->xres = fb_data->native_height; + var->yres = fb_data->native_width; + break; + default: + /* Invalid rotation value */ + var->rotate = 0; + dev_dbg(fb_data->dev, "Invalid rotation request\n"); + return -EINVAL; + } + + var->xres_virtual = ALIGN(var->xres, 32); + var->yres_virtual = ALIGN(var->yres, 128) * fb_data->num_screens; + + var->height = -1; + var->width = -1; + + return 0; +} + +void mxc_epdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes, + struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = info ? + (struct mxc_epdc_fb_data *)info:g_fb_data; + + memcpy(&fb_data->wv_modes, modes, sizeof(modes)); +} +EXPORT_SYMBOL(mxc_epdc_fb_set_waveform_modes); + +static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data, int temp) +{ + int i; + int index = -1; + + if (fb_data->trt_entries == 0) { + dev_err(fb_data->dev, + "No TRT exists...using default temp index\n"); + return DEFAULT_TEMP_INDEX; + } + + /* Search temperature ranges for a match */ + for (i = 0; i < fb_data->trt_entries - 1; i++) { + if ((temp >= fb_data->temp_range_bounds[i]) + && (temp < fb_data->temp_range_bounds[i+1])) { + index = i; + break; + } + } + + if (index < 0) { + dev_err(fb_data->dev, + "No TRT index match...using default temp index\n"); + return DEFAULT_TEMP_INDEX; + } + + dev_dbg(fb_data->dev, "Using temperature index %d\n", index); + + return index; +} + +int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = info ? + (struct mxc_epdc_fb_data *)info:g_fb_data; + unsigned long flags; + + /* Store temp index. Used later when configuring updates. */ + spin_lock_irqsave(&fb_data->queue_lock, flags); + fb_data->temp_index = mxc_epdc_fb_get_temp_index(fb_data, temperature); + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + + return 0; +} +EXPORT_SYMBOL(mxc_epdc_fb_set_temperature); + +int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = info ? + (struct mxc_epdc_fb_data *)info:g_fb_data; + + dev_dbg(fb_data->dev, "Setting auto update mode to %d\n", auto_mode); + + if ((auto_mode == AUTO_UPDATE_MODE_AUTOMATIC_MODE) + || (auto_mode == AUTO_UPDATE_MODE_REGION_MODE)) + fb_data->auto_mode = auto_mode; + else { + dev_err(fb_data->dev, "Invalid auto update mode parameter.\n"); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(mxc_epdc_fb_set_auto_update); + +int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = info ? + (struct mxc_epdc_fb_data *)info:g_fb_data; + + dev_dbg(fb_data->dev, "Setting optimization level to %d\n", upd_scheme); + + /* + * Can't change the scheme until current updates have completed. + * This function returns when all active updates are done. + */ + mxc_epdc_fb_flush_updates(fb_data); + + if ((upd_scheme == UPDATE_SCHEME_SNAPSHOT) + || (upd_scheme == UPDATE_SCHEME_QUEUE) + || (upd_scheme == UPDATE_SCHEME_QUEUE_AND_MERGE)) + fb_data->upd_scheme = upd_scheme; + else { + dev_err(fb_data->dev, "Invalid update scheme specified.\n"); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(mxc_epdc_fb_set_upd_scheme); + +static int epdc_process_update(struct update_data_list *upd_data_list, + struct mxc_epdc_fb_data *fb_data) +{ + struct mxcfb_rect *src_upd_region; /* Region of src buffer for update */ + struct mxcfb_rect pxp_upd_region; + u32 src_width, src_height; + u32 offset_from_8, bytes_per_pixel; + u32 post_rotation_xcoord, post_rotation_ycoord, width_pxp_blocks; + u32 pxp_input_offs, pxp_output_offs, pxp_output_shift; + int x_start_offs = 0; + u32 hist_stat = 0; + + int ret; + + /* + * Gotta do a whole bunch of buffer ptr manipulation to + * work around HW restrictions for PxP & EPDC + */ + + /* + * Are we using FB or an alternate (overlay) + * buffer for source of update? + */ + if (upd_data_list->upd_data.flags & EPDC_FLAG_USE_ALT_BUFFER) { + src_width = upd_data_list->upd_data.alt_buffer_data.width; + src_height = upd_data_list->upd_data.alt_buffer_data.height; + src_upd_region = &upd_data_list->upd_data.alt_buffer_data.alt_update_region; + } else { + src_width = fb_data->epdc_fb_var.xres_virtual; + src_height = fb_data->epdc_fb_var.yres; + src_upd_region = &upd_data_list->upd_data.update_region; + } + + /* + * Compute buffer offset to account for + * PxP limitation (must read 8x8 pixel blocks) + */ + offset_from_8 = src_upd_region->left & 0x7; + bytes_per_pixel = fb_data->epdc_fb_var.bits_per_pixel/8; + if ((offset_from_8 * fb_data->epdc_fb_var.bits_per_pixel/8 % 4) != 0) { + /* Leave a gap between PxP input addr and update region pixels */ + pxp_input_offs = + (src_upd_region->top * src_width + src_upd_region->left) + * bytes_per_pixel & 0xFFFFFFFC; + /* Update region should change to reflect relative position to input ptr */ + pxp_upd_region.top = 0; + pxp_upd_region.left = (offset_from_8 & 0x3) % bytes_per_pixel; + } else { + pxp_input_offs = + (src_upd_region->top * src_width + src_upd_region->left) + * bytes_per_pixel; + /* Update region should change to reflect relative position to input ptr */ + pxp_upd_region.top = 0; + pxp_upd_region.left = 0; + } + + /* + * We want PxP processing region to start at the first pixel + * that we have to process in each row, but PxP alignment + * restricts the input mem address to be 32-bit aligned + * + * We work around this by using x_start_offs + * to offset from our starting pixel location to the + * first pixel that is in the relevant update region + * for each row. + */ + x_start_offs = pxp_upd_region.left & 0x7; + + /* Update region to meet 8x8 pixel requirement */ + pxp_upd_region.width = ALIGN(src_upd_region->width, 8); + pxp_upd_region.height = ALIGN(src_upd_region->height, 8); + pxp_upd_region.top &= ~0x7; + pxp_upd_region.left &= ~0x7; + + switch (fb_data->epdc_fb_var.rotate) { + case FB_ROTATE_UR: + default: + post_rotation_xcoord = pxp_upd_region.left; + post_rotation_ycoord = pxp_upd_region.top; + width_pxp_blocks = pxp_upd_region.width; + break; + case FB_ROTATE_CW: + width_pxp_blocks = pxp_upd_region.height; + post_rotation_xcoord = width_pxp_blocks - src_upd_region->height; + post_rotation_ycoord = pxp_upd_region.left; + break; + case FB_ROTATE_UD: + width_pxp_blocks = pxp_upd_region.width; + post_rotation_xcoord = width_pxp_blocks - src_upd_region->width - pxp_upd_region.left; + post_rotation_ycoord = pxp_upd_region.height - src_upd_region->height - pxp_upd_region.top; + break; + case FB_ROTATE_CCW: + width_pxp_blocks = pxp_upd_region.height; + post_rotation_xcoord = pxp_upd_region.top; + post_rotation_ycoord = pxp_upd_region.width - src_upd_region->width - pxp_upd_region.left; + break; + } + + pxp_output_offs = post_rotation_ycoord * width_pxp_blocks + + post_rotation_xcoord; + + pxp_output_shift = ALIGN(pxp_output_offs, 8) - pxp_output_offs; + + upd_data_list->epdc_offs = pxp_output_offs + pxp_output_shift; + + mutex_lock(&fb_data->pxp_mutex); + + /* Source address either comes from alternate buffer + provided in update data, or from the framebuffer. */ + if (upd_data_list->upd_data.flags & EPDC_FLAG_USE_ALT_BUFFER) + sg_dma_address(&fb_data->sg[0]) = + upd_data_list->upd_data.alt_buffer_data.phys_addr + + pxp_input_offs; + else { + sg_dma_address(&fb_data->sg[0]) = + fb_data->info.fix.smem_start + upd_data_list->fb_offset + + pxp_input_offs; + sg_set_page(&fb_data->sg[0], + virt_to_page(fb_data->info.screen_base), + fb_data->info.fix.smem_len, + offset_in_page(fb_data->info.screen_base)); + } + + /* Update sg[1] to point to output of PxP proc task */ + sg_dma_address(&fb_data->sg[1]) = upd_data_list->phys_addr + pxp_output_offs; + sg_set_page(&fb_data->sg[1], virt_to_page(upd_data_list->virt_addr), + upd_data_list->size, + offset_in_page(upd_data_list->virt_addr)); + + /* + * Set PxP LUT transform type based on update flags. + */ + fb_data->pxp_conf.proc_data.lut_transform = 0; + if (upd_data_list->upd_data.flags & EPDC_FLAG_ENABLE_INVERSION) + fb_data->pxp_conf.proc_data.lut_transform |= PXP_LUT_INVERT; + if (upd_data_list->upd_data.flags & EPDC_FLAG_FORCE_MONOCHROME) + fb_data->pxp_conf.proc_data.lut_transform |= + PXP_LUT_BLACK_WHITE; + + /* + * Toggle inversion processing if 8-bit + * inverted is the current pixel format. + */ + if (fb_data->epdc_fb_var.grayscale == GRAYSCALE_8BIT_INVERTED) + fb_data->pxp_conf.proc_data.lut_transform ^= PXP_LUT_INVERT; + + /* This is a blocking call, so upon return PxP tx should be done */ + ret = pxp_process_update(fb_data, src_width, src_height, + &pxp_upd_region, x_start_offs); + if (ret) { + dev_err(fb_data->dev, "Unable to submit PxP update task.\n"); + mutex_unlock(&fb_data->pxp_mutex); + return ret; + } + + mutex_unlock(&fb_data->pxp_mutex); + + /* If needed, enable EPDC HW while ePxP is processing */ + if ((fb_data->power_state == POWER_STATE_OFF) + || fb_data->powering_down) { + epdc_powerup(fb_data); + } + + mutex_lock(&fb_data->pxp_mutex); + + /* This is a blocking call, so upon return PxP tx should be done */ + ret = pxp_complete_update(fb_data, &hist_stat); + if (ret) { + dev_err(fb_data->dev, "Unable to complete PxP update task.\n"); + mutex_unlock(&fb_data->pxp_mutex); + return ret; + } + + mutex_unlock(&fb_data->pxp_mutex); + + /* Update waveform mode from PxP histogram results */ + if (upd_data_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO) { + if (hist_stat & 0x1) + upd_data_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_du; + else if (hist_stat & 0x2) + upd_data_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_gc4; + else if (hist_stat & 0x4) + upd_data_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_gc8; + else if (hist_stat & 0x8) + upd_data_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_gc16; + else + upd_data_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_gc32; + + dev_dbg(fb_data->dev, "hist_stat = 0x%x, new waveform = 0x%x\n", + hist_stat, upd_data_list->upd_data.waveform_mode); + } + + return 0; + +} + +static bool epdc_submit_merge(struct update_data_list *upd_data_list, + struct update_data_list *update_to_merge) +{ + struct mxcfb_update_data *a, *b; + struct mxcfb_rect *arect, *brect; + struct mxcfb_rect combine; + + a = &upd_data_list->upd_data; + b = &update_to_merge->upd_data; + arect = &upd_data_list->upd_data.update_region; + brect = &update_to_merge->upd_data.update_region; + + if ((a->waveform_mode != b->waveform_mode + && a->waveform_mode != WAVEFORM_MODE_AUTO) || + a->update_mode != b->update_mode || + (a->flags & EPDC_FLAG_USE_ALT_BUFFER) || + (b->flags & EPDC_FLAG_USE_ALT_BUFFER) || + arect->left > (brect->left + brect->width) || + brect->left > (arect->left + arect->width) || + arect->top > (brect->top + brect->height) || + brect->top > (arect->top + arect->height) || + (upd_data_list->fb_offset != update_to_merge->fb_offset) || + (b->update_marker != 0 && a->update_marker != 0)) + return false; + + combine.left = arect->left < brect->left ? arect->left : brect->left; + combine.top = arect->top < brect->top ? arect->top : brect->top; + combine.width = (arect->left + arect->width) > + (brect->left + brect->width) ? + (arect->left + arect->width - combine.left) : + (brect->left + brect->width - combine.left); + combine.height = (arect->top + arect->height) > + (brect->top + brect->height) ? + (arect->top + arect->height - combine.top) : + (brect->top + brect->height - combine.top); + + arect->left = combine.left; + arect->top = combine.top; + arect->width = combine.width; + arect->height = combine.height; + + /* Preserve marker value for merged update */ + if (b->update_marker != 0) { + a->update_marker = b->update_marker; + upd_data_list->upd_marker_data = + update_to_merge->upd_marker_data; + } + + /* Merged update should take on the earliest order */ + upd_data_list->update_order = + (upd_data_list->update_order > update_to_merge->update_order) ? + upd_data_list->update_order : update_to_merge->update_order; + + return true; +} + +static void epdc_submit_work_func(struct work_struct *work) +{ + int temp_index; + struct update_data_list *next_update; + struct update_data_list *temp; + unsigned long flags; + struct mxc_epdc_fb_data *fb_data = + container_of(work, struct mxc_epdc_fb_data, epdc_submit_work); + struct update_data_list *upd_data_list = NULL; + struct mxcfb_rect adj_update_region; + + /* Protect access to buffer queues and to update HW */ + spin_lock_irqsave(&fb_data->queue_lock, flags); + + /* + * Are any of our collision updates able to go now? + * Go through all updates in the collision list and check to see + * if the collision mask has been fully cleared + */ + list_for_each_entry_safe(next_update, temp, + &fb_data->upd_buf_collision_list->list, list) { + + if (next_update->collision_mask != 0) + continue; + + dev_dbg(fb_data->dev, "A collision update is ready to go!\n"); + /* + * We have a collision cleared, so select it for resubmission. + * If an update is already selected, attempt to merge. + */ + if (!upd_data_list) { + upd_data_list = next_update; + list_del_init(&next_update->list); + if (fb_data->upd_scheme == UPDATE_SCHEME_QUEUE) + /* If not merging, we have our update */ + break; + } else if (epdc_submit_merge(upd_data_list, next_update)) { + dev_dbg(fb_data->dev, + "Update merged [work queue]\n"); + list_del_init(&next_update->list); + /* Add to free buffer list */ + list_add_tail(&next_update->list, + &fb_data->upd_buf_free_list->list); + } else + dev_dbg(fb_data->dev, + "Update not merged [work queue]\n"); + } + + /* + * Skip update queue only if we found a collision + * update and we are not merging + */ + if (!((fb_data->upd_scheme == UPDATE_SCHEME_QUEUE) && + upd_data_list)) { + /* + * If we didn't find a collision update ready to go, + * we try to grab one from the update queue + */ + list_for_each_entry_safe(next_update, temp, + &fb_data->upd_buf_queue->list, list) { + + dev_dbg(fb_data->dev, "Found a pending update!\n"); + + if (!upd_data_list) { + upd_data_list = next_update; + list_del_init(&next_update->list); + if (fb_data->upd_scheme == UPDATE_SCHEME_QUEUE) + /* If not merging, we have an update */ + break; + } else if (epdc_submit_merge(upd_data_list, + next_update)) { + dev_dbg(fb_data->dev, + "Update merged [work queue]\n"); + list_del_init(&next_update->list); + /* Add to free buffer list */ + list_add_tail(&next_update->list, + &fb_data->upd_buf_free_list->list); + } else + dev_dbg(fb_data->dev, + "Update not merged [work queue]\n"); + } + } + + /* Release buffer queues */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + + /* Is update list empty? */ + if (!upd_data_list) + return; + + /* Perform PXP processing - EPDC power will also be enabled */ + if (epdc_process_update(upd_data_list, fb_data)) { + dev_dbg(fb_data->dev, "PXP processing error.\n"); + /* Protect access to buffer queues and to update HW */ + spin_lock_irqsave(&fb_data->queue_lock, flags); + /* Add to free buffer list */ + list_add_tail(&upd_data_list->list, + &fb_data->upd_buf_free_list->list); + /* Release buffer queues */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return; + } + + /* Get rotation-adjusted coordinates */ + adjust_coordinates(fb_data, &upd_data_list->upd_data.update_region, + &adj_update_region); + + /* Protect access to buffer queues and to update HW */ + spin_lock_irqsave(&fb_data->queue_lock, flags); + + /* + * Is the working buffer idle? + * If the working buffer is busy, we must wait for the resource + * to become free. The IST will signal this event. + */ + if (fb_data->cur_update != NULL) { + dev_dbg(fb_data->dev, "working buf busy!\n"); + + /* Initialize event signalling an update resource is free */ + init_completion(&fb_data->update_res_free); + + fb_data->waiting_for_wb = true; + + /* Leave spinlock while waiting for WB to complete */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + wait_for_completion(&fb_data->update_res_free); + spin_lock_irqsave(&fb_data->queue_lock, flags); + } + + /* + * If there are no LUTs available, + * then we must wait for the resource to become free. + * The IST will signal this event. + */ + if (!epdc_any_luts_available()) { + dev_dbg(fb_data->dev, "no luts available!\n"); + + /* Initialize event signalling an update resource is free */ + init_completion(&fb_data->update_res_free); + + fb_data->waiting_for_lut = true; + + /* Leave spinlock while waiting for LUT to free up */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + wait_for_completion(&fb_data->update_res_free); + spin_lock_irqsave(&fb_data->queue_lock, flags); + } + + + /* LUTs are available, so we get one here */ + fb_data->cur_update = upd_data_list; + fb_data->cur_update->lut_num = epdc_get_next_lut(); + + /* Associate LUT with update marker */ + if ((fb_data->cur_update->upd_marker_data) + && (fb_data->cur_update->upd_marker_data->update_marker != 0)) + fb_data->cur_update->upd_marker_data->lut_num = + fb_data->cur_update->lut_num; + + /* Mark LUT with order */ + fb_data->lut_update_order[fb_data->cur_update->lut_num] = + fb_data->cur_update->update_order; + + /* Enable Collision and WB complete IRQs */ + epdc_working_buf_intr(true); + epdc_lut_complete_intr(fb_data->cur_update->lut_num, true); + + /* Program EPDC update to process buffer */ + if (fb_data->cur_update->upd_data.temp != TEMP_USE_AMBIENT) { + temp_index = mxc_epdc_fb_get_temp_index(fb_data, + fb_data->cur_update->upd_data.temp); + epdc_set_temp(temp_index); + } + epdc_set_update_addr(fb_data->cur_update->phys_addr + + fb_data->cur_update->epdc_offs); + epdc_set_update_coord(adj_update_region.left, adj_update_region.top); + epdc_set_update_dimensions(adj_update_region.width, + adj_update_region.height); + epdc_submit_update(fb_data->cur_update->lut_num, + fb_data->cur_update->upd_data.waveform_mode, + fb_data->cur_update->upd_data.update_mode, false, 0); + + /* Release buffer queues */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); +} + + +int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data, + struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = info ? + (struct mxc_epdc_fb_data *)info:g_fb_data; + struct update_data_list *upd_data_list = NULL; + unsigned long flags; + int i; + struct mxcfb_rect *screen_upd_region; /* Region on screen to update */ + int temp_index; + int ret; + + /* Has EPDC HW been initialized? */ + if (!fb_data->hw_ready) { + dev_err(fb_data->dev, "Display HW not properly initialized." + " Aborting update.\n"); + return -EPERM; + } + + /* Check validity of update params */ + if ((upd_data->update_mode != UPDATE_MODE_PARTIAL) && + (upd_data->update_mode != UPDATE_MODE_FULL)) { + dev_err(fb_data->dev, + "Update mode 0x%x is invalid. Aborting update.\n", + upd_data->update_mode); + return -EINVAL; + } + if ((upd_data->waveform_mode > 255) && + (upd_data->waveform_mode != WAVEFORM_MODE_AUTO)) { + dev_err(fb_data->dev, + "Update waveform mode 0x%x is invalid." + " Aborting update.\n", + upd_data->waveform_mode); + return -EINVAL; + } + if ((upd_data->update_region.left + upd_data->update_region.width > fb_data->epdc_fb_var.xres) || + (upd_data->update_region.top + upd_data->update_region.height > fb_data->epdc_fb_var.yres)) { + dev_err(fb_data->dev, + "Update region is outside bounds of framebuffer." + "Aborting update.\n"); + return -EINVAL; + } + if ((upd_data->flags & EPDC_FLAG_USE_ALT_BUFFER) && + ((upd_data->update_region.width != upd_data->alt_buffer_data.alt_update_region.width) || + (upd_data->update_region.height != upd_data->alt_buffer_data.alt_update_region.height))) { + dev_err(fb_data->dev, + "Alternate update region dimensions must match screen update region dimensions.\n"); + return -EINVAL; + } + + spin_lock_irqsave(&fb_data->queue_lock, flags); + + /* + * If we are waiting to go into suspend, or the FB is blanked, + * we do not accept new updates + */ + if ((fb_data->waiting_for_idle) || + (fb_data->blank != FB_BLANK_UNBLANK)) { + dev_dbg(fb_data->dev, "EPDC not active." + "Update request abort.\n"); + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return -EPERM; + } + + /* + * Get available intermediate (PxP output) buffer to hold + * processed update region + */ + if (list_empty(&fb_data->upd_buf_free_list->list)) { + dev_err(fb_data->dev, + "No free intermediate buffers available.\n"); + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return -ENOMEM; + } + + /* Grab first available buffer and delete it from the free list */ + upd_data_list = + list_entry(fb_data->upd_buf_free_list->list.next, + struct update_data_list, list); + + list_del_init(&upd_data_list->list); + + /* copy update parameters to the current update data object */ + memcpy(&upd_data_list->upd_data, upd_data, + sizeof(struct mxcfb_update_data)); + memcpy(&upd_data_list->upd_data.update_region, &upd_data->update_region, + sizeof(struct mxcfb_rect)); + + upd_data_list->fb_offset = fb_data->fb_offset; + /* If marker specified, associate it with a completion */ + if (upd_data->update_marker != 0) { + /* Find available update marker and set it up */ + for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) { + /* Marker value set to 0 signifies it is not currently in use */ + if (fb_data->update_marker_array[i].update_marker == 0) { + fb_data->update_marker_array[i].update_marker = upd_data->update_marker; + init_completion(&fb_data->update_marker_array[i].update_completion); + upd_data_list->upd_marker_data = &fb_data->update_marker_array[i]; + break; + } + } + } else { + if (upd_data_list->upd_marker_data) + upd_data_list->upd_marker_data->update_marker = 0; + } + + upd_data_list->update_order = fb_data->order_cnt++; + + if (fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT) { + /* Queued update scheme processing */ + + /* Add processed Y buffer to update list */ + list_add_tail(&upd_data_list->list, + &fb_data->upd_buf_queue->list); + + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + + /* Signal workqueue to handle new update */ + queue_work(fb_data->epdc_submit_workqueue, + &fb_data->epdc_submit_work); + + return 0; + } + + /* Snapshot update scheme processing */ + + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + + /* + * Hold on to original screen update region, which we + * will ultimately use when telling EPDC where to update on panel + */ + screen_upd_region = &upd_data_list->upd_data.update_region; + + ret = epdc_process_update(upd_data_list, fb_data); + if (ret) { + mutex_unlock(&fb_data->pxp_mutex); + return ret; + } + + /* Pass selected waveform mode back to user */ + upd_data->waveform_mode = upd_data_list->upd_data.waveform_mode; + + /* Get rotation-adjusted coordinates */ + adjust_coordinates(fb_data, &upd_data_list->upd_data.update_region, + NULL); + + /* Grab lock for queue manipulation and update submission */ + spin_lock_irqsave(&fb_data->queue_lock, flags); + + /* + * Is the working buffer idle? + * If either the working buffer is busy, or there are no LUTs available, + * then we return and let the ISR handle the update later + */ + if ((fb_data->cur_update != NULL) || !epdc_any_luts_available()) { + /* Add processed Y buffer to update list */ + list_add_tail(&upd_data_list->list, + &fb_data->upd_buf_queue->list); + + /* Return and allow the update to be submitted by the ISR. */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return 0; + } + + /* Save current update */ + fb_data->cur_update = upd_data_list; + + /* LUTs are available, so we get one here */ + upd_data_list->lut_num = epdc_get_next_lut(); + + /* Associate LUT with update marker */ + if (upd_data_list->upd_marker_data) + if (upd_data_list->upd_marker_data->update_marker != 0) + upd_data_list->upd_marker_data->lut_num = upd_data_list->lut_num; + + /* Mark LUT as containing new update */ + fb_data->lut_update_order[upd_data_list->lut_num] = + upd_data_list->update_order; + + /* Clear status and Enable LUT complete and WB complete IRQs */ + epdc_working_buf_intr(true); + epdc_lut_complete_intr(fb_data->cur_update->lut_num, true); + + /* Program EPDC update to process buffer */ + epdc_set_update_addr(upd_data_list->phys_addr + upd_data_list->epdc_offs); + epdc_set_update_coord(screen_upd_region->left, screen_upd_region->top); + epdc_set_update_dimensions(screen_upd_region->width, + screen_upd_region->height); + if (upd_data_list->upd_data.temp != TEMP_USE_AMBIENT) { + temp_index = mxc_epdc_fb_get_temp_index(fb_data, + upd_data_list->upd_data.temp); + epdc_set_temp(temp_index); + } else + epdc_set_temp(fb_data->temp_index); + + epdc_submit_update(upd_data_list->lut_num, + upd_data_list->upd_data.waveform_mode, + upd_data_list->upd_data.update_mode, false, 0); + + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return 0; +} +EXPORT_SYMBOL(mxc_epdc_fb_send_update); + +int mxc_epdc_fb_wait_update_complete(u32 update_marker, struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = info ? + (struct mxc_epdc_fb_data *)info:g_fb_data; + int ret; + int i; + + /* 0 is an invalid update_marker value */ + if (update_marker == 0) + return -EINVAL; + + /* Wait for completion associated with update_marker requested */ + for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) { + if (fb_data->update_marker_array[i].update_marker == update_marker) { + dev_dbg(fb_data->dev, "Waiting for marker %d\n", update_marker); + ret = wait_for_completion_timeout(&fb_data->update_marker_array[i].update_completion, msecs_to_jiffies(5000)); + if (!ret) + dev_err(fb_data->dev, "Timed out waiting for update completion\n"); + + dev_dbg(fb_data->dev, "marker %d signalled!\n", update_marker); + + /* Reset marker so it can be reused */ + fb_data->update_marker_array[i].update_marker = 0; + + break; + } + } + + return 0; +} +EXPORT_SYMBOL(mxc_epdc_fb_wait_update_complete); + +int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay, + struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = info ? + (struct mxc_epdc_fb_data *)info:g_fb_data; + + fb_data->pwrdown_delay = pwrdown_delay; + + return 0; +} +EXPORT_SYMBOL(mxc_epdc_fb_set_pwrdown_delay); + +int mxc_epdc_get_pwrdown_delay(struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = info ? + (struct mxc_epdc_fb_data *)info:g_fb_data; + + return fb_data->pwrdown_delay; +} +EXPORT_SYMBOL(mxc_epdc_get_pwrdown_delay); + +static int mxc_epdc_fb_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg) +{ + void __user *argp = (void __user *)arg; + int ret = -EINVAL; + + switch (cmd) { + case MXCFB_SET_WAVEFORM_MODES: + { + struct mxcfb_waveform_modes modes; + if (!copy_from_user(&modes, argp, sizeof(modes))) { + mxc_epdc_fb_set_waveform_modes(&modes, info); + ret = 0; + } + break; + } + case MXCFB_SET_TEMPERATURE: + { + int temperature; + if (!get_user(temperature, (int32_t __user *) arg)) + ret = mxc_epdc_fb_set_temperature(temperature, + info); + break; + } + case MXCFB_SET_AUTO_UPDATE_MODE: + { + u32 auto_mode = 0; + if (!get_user(auto_mode, (__u32 __user *) arg)) + ret = mxc_epdc_fb_set_auto_update(auto_mode, + info); + break; + } + case MXCFB_SET_UPDATE_SCHEME: + { + u32 upd_scheme = 0; + if (!get_user(upd_scheme, (__u32 __user *) arg)) + ret = mxc_epdc_fb_set_upd_scheme(upd_scheme, + info); + break; + } + case MXCFB_SEND_UPDATE: + { + struct mxcfb_update_data upd_data; + if (!copy_from_user(&upd_data, argp, + sizeof(upd_data))) { + ret = mxc_epdc_fb_send_update(&upd_data, info); + if (ret == 0 && copy_to_user(argp, &upd_data, + sizeof(upd_data))) + ret = -EFAULT; + } else { + ret = -EFAULT; + } + + break; + } + case MXCFB_WAIT_FOR_UPDATE_COMPLETE: + { + u32 update_marker = 0; + if (!get_user(update_marker, (__u32 __user *) arg)) + ret = + mxc_epdc_fb_wait_update_complete(update_marker, + info); + break; + } + + case MXCFB_SET_PWRDOWN_DELAY: + { + int delay = 0; + if (!get_user(delay, (__u32 __user *) arg)) + ret = + mxc_epdc_fb_set_pwrdown_delay(delay, info); + break; + } + + case MXCFB_GET_PWRDOWN_DELAY: + { + int pwrdown_delay = mxc_epdc_get_pwrdown_delay(info); + if (put_user(pwrdown_delay, + (int __user *)argp)) + ret = -EFAULT; + ret = 0; + break; + } + default: + break; + } + return ret; +} + +static void mxc_epdc_fb_update_pages(struct mxc_epdc_fb_data *fb_data, + u16 y1, u16 y2) +{ + struct mxcfb_update_data update; + + /* Do partial screen update, Update full horizontal lines */ + update.update_region.left = 0; + update.update_region.width = fb_data->epdc_fb_var.xres; + update.update_region.top = y1; + update.update_region.height = y2 - y1; + update.waveform_mode = WAVEFORM_MODE_AUTO; + update.update_mode = UPDATE_MODE_FULL; + update.update_marker = 0; + update.temp = TEMP_USE_AMBIENT; + update.flags = 0; + + mxc_epdc_fb_send_update(&update, &fb_data->info); +} + +/* this is called back from the deferred io workqueue */ +static void mxc_epdc_fb_deferred_io(struct fb_info *info, + struct list_head *pagelist) +{ + struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info; + struct page *page; + unsigned long beg, end; + int y1, y2, miny, maxy; + + if (fb_data->auto_mode != AUTO_UPDATE_MODE_AUTOMATIC_MODE) + return; + + miny = INT_MAX; + maxy = 0; + list_for_each_entry(page, pagelist, lru) { + beg = page->index << PAGE_SHIFT; + end = beg + PAGE_SIZE - 1; + y1 = beg / info->fix.line_length; + y2 = end / info->fix.line_length; + if (y2 >= fb_data->epdc_fb_var.yres) + y2 = fb_data->epdc_fb_var.yres - 1; + if (miny > y1) + miny = y1; + if (maxy < y2) + maxy = y2; + } + + mxc_epdc_fb_update_pages(fb_data, miny, maxy); +} + +void mxc_epdc_fb_flush_updates(struct mxc_epdc_fb_data *fb_data) +{ + unsigned long flags; + /* Grab queue lock to prevent any new updates from being submitted */ + spin_lock_irqsave(&fb_data->queue_lock, flags); + + if (!is_free_list_full(fb_data)) { + /* Initialize event signalling updates are done */ + init_completion(&fb_data->updates_done); + fb_data->waiting_for_idle = true; + + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + /* Wait for any currently active updates to complete */ + wait_for_completion_timeout(&fb_data->updates_done, msecs_to_jiffies(2000)); + spin_lock_irqsave(&fb_data->queue_lock, flags); + fb_data->waiting_for_idle = false; + } + + spin_unlock_irqrestore(&fb_data->queue_lock, flags); +} + +static int mxc_epdc_fb_blank(int blank, struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info; + + dev_dbg(fb_data->dev, "blank = %d\n", blank); + + if (fb_data->blank == blank) + return 0; + + fb_data->blank = blank; + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + mxc_epdc_fb_flush_updates(fb_data); + break; + } + return 0; +} + +static int mxc_epdc_fb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info; + u_int y_bottom; + unsigned long flags; + + dev_dbg(info->device, "%s: var->xoffset %d, info->var.xoffset %d\n", + __func__, var->xoffset, info->var.xoffset); + /* check if var is valid; also, xpan is not supported */ + if (!var || (var->xoffset != info->var.xoffset) || + (var->yoffset + var->yres > var->yres_virtual)) { + dev_dbg(info->device, "x panning not supported\n"); + return -EINVAL; + } + + if ((fb_data->epdc_fb_var.xoffset == var->xoffset) && + (fb_data->epdc_fb_var.yoffset == var->yoffset)) + return 0; /* No change, do nothing */ + + spin_lock_irqsave(&fb_data->queue_lock, flags); + + y_bottom = var->yoffset; + + if (!(var->vmode & FB_VMODE_YWRAP)) + y_bottom += var->yres; + + if (y_bottom > info->var.yres_virtual) { + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return -EINVAL; + } + + fb_data->fb_offset = (var->yoffset * var->xres_virtual + var->xoffset) + * (var->bits_per_pixel) / 8; + + fb_data->epdc_fb_var.xoffset = var->xoffset; + fb_data->epdc_fb_var.yoffset = var->yoffset; + + if (var->vmode & FB_VMODE_YWRAP) + info->var.vmode |= FB_VMODE_YWRAP; + else + info->var.vmode &= ~FB_VMODE_YWRAP; + + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + + return 0; +} + +static struct fb_ops mxc_epdc_fb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mxc_epdc_fb_check_var, + .fb_set_par = mxc_epdc_fb_set_par, + .fb_setcolreg = mxc_epdc_fb_setcolreg, + .fb_pan_display = mxc_epdc_fb_pan_display, + .fb_ioctl = mxc_epdc_fb_ioctl, + .fb_mmap = mxc_epdc_fb_mmap, + .fb_blank = mxc_epdc_fb_blank, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +static struct fb_deferred_io mxc_epdc_fb_defio = { + .delay = HZ, + .deferred_io = mxc_epdc_fb_deferred_io, +}; + +static void epdc_done_work_func(struct work_struct *work) +{ + struct mxc_epdc_fb_data *fb_data = + container_of(work, struct mxc_epdc_fb_data, + epdc_done_work.work); + epdc_powerdown(fb_data); +} + +static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data) +{ + int count = 0; + struct update_data_list *plist; + + /* Count buffers in free buffer list */ + list_for_each_entry(plist, &fb_data->upd_buf_free_list->list, list) + count++; + + /* Check to see if all buffers are in this list */ + if (count == EPDC_MAX_NUM_UPDATES) + return true; + else + return false; +} + +static irqreturn_t mxc_epdc_irq_handler(int irq, void *dev_id) +{ + struct mxc_epdc_fb_data *fb_data = dev_id; + struct update_data_list *collision_update; + struct mxcfb_rect *next_upd_region; + unsigned long flags; + int temp_index; + u32 luts_completed_mask; + u32 temp_mask; + u32 lut; + bool ignore_collision = false; + int i, j; + + /* + * If we just completed one-time panel init, bypass + * queue handling, clear interrupt and return + */ + if (fb_data->in_init) { + if (epdc_is_working_buffer_complete()) { + epdc_working_buf_intr(false); + epdc_clear_working_buf_irq(); + dev_dbg(fb_data->dev, "Cleared WB for init update\n"); + } + + if (epdc_is_lut_complete(0)) { + epdc_lut_complete_intr(0, false); + epdc_clear_lut_complete_irq(0); + fb_data->in_init = false; + dev_dbg(fb_data->dev, "Cleared LUT complete for init update\n"); + } + + return IRQ_HANDLED; + } + + if (!(__raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ))) + return IRQ_HANDLED; + + if (__raw_readl(EPDC_IRQ) & EPDC_IRQ_TCE_UNDERRUN_IRQ) { + dev_err(fb_data->dev, "TCE underrun! Panel may lock up.\n"); + return IRQ_HANDLED; + } + + /* Protect access to buffer queues and to update HW */ + spin_lock_irqsave(&fb_data->queue_lock, flags); + + /* Free any LUTs that have completed */ + luts_completed_mask = 0; + for (i = 0; i < EPDC_NUM_LUTS; i++) { + if (!epdc_is_lut_complete(i)) + continue; + + dev_dbg(fb_data->dev, "\nLUT %d completed\n", i); + + /* Disable IRQ for completed LUT */ + epdc_lut_complete_intr(i, false); + + /* + * Go through all updates in the collision list and + * unmask any updates that were colliding with + * the completed LUT. + */ + list_for_each_entry(collision_update, + &fb_data->upd_buf_collision_list-> + list, list) { + collision_update->collision_mask = + collision_update->collision_mask & ~(1 << i); + } + + epdc_clear_lut_complete_irq(i); + + luts_completed_mask |= 1 << i; + + fb_data->lut_update_order[i] = 0; + + /* Signal completion if submit workqueue needs a LUT */ + if (fb_data->waiting_for_lut) { + complete(&fb_data->update_res_free); + fb_data->waiting_for_lut = false; + } + + /* Signal completion if anyone waiting on this LUT */ + for (j = 0; j < EPDC_MAX_NUM_UPDATES; j++) { + if (fb_data->update_marker_array[j].lut_num != i) + continue; + + /* Signal completion of update */ + dev_dbg(fb_data->dev, + "Signaling marker %d\n", + fb_data->update_marker_array[j].update_marker); + complete(&fb_data->update_marker_array[j].update_completion); + /* Ensure this doesn't get signaled again inadvertently */ + fb_data->update_marker_array[j].lut_num = INVALID_LUT; + } + } + + /* Check to see if all updates have completed */ + if (is_free_list_full(fb_data) && + (fb_data->cur_update == NULL) && + !epdc_any_luts_active()) { + + if (fb_data->pwrdown_delay != FB_POWERDOWN_DISABLE) { + /* + * Set variable to prevent overlapping + * enable/disable requests + */ + fb_data->powering_down = true; + + /* Schedule task to disable EPDC HW until next update */ + schedule_delayed_work(&fb_data->epdc_done_work, + msecs_to_jiffies(fb_data->pwrdown_delay)); + + /* Reset counter to reduce chance of overflow */ + fb_data->order_cnt = 0; + } + + if (fb_data->waiting_for_idle) + complete(&fb_data->updates_done); + } + + /* Is Working Buffer busy? */ + if (epdc_is_working_buffer_busy()) { + /* Can't submit another update until WB is done */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return IRQ_HANDLED; + } + + /* + * Were we waiting on working buffer? + * If so, update queues and check for collisions + */ + if (fb_data->cur_update != NULL) { + dev_dbg(fb_data->dev, "\nWorking buffer completed\n"); + + /* Signal completion if submit workqueue was waiting on WB */ + if (fb_data->waiting_for_wb) { + complete(&fb_data->update_res_free); + fb_data->waiting_for_lut = false; + } + + /* Was there a collision? */ + if (epdc_is_collision()) { + /* Check list of colliding LUTs, and add to our collision mask */ + fb_data->cur_update->collision_mask = + epdc_get_colliding_luts(); + + /* Clear collisions that just completed */ + fb_data->cur_update->collision_mask &= ~luts_completed_mask; + + dev_dbg(fb_data->dev, "\nCollision mask = 0x%x\n", + epdc_get_colliding_luts()); + + /* + * If we collide with newer updates, then + * we don't need to re-submit the update. The + * idea is that the newer updates should take + * precedence anyways, so we don't want to + * overwrite them. + */ + for (temp_mask = fb_data->cur_update->collision_mask, lut = 0; + temp_mask != 0; + lut++, temp_mask = temp_mask >> 1) { + if (!(temp_mask & 0x1)) + continue; + + if (fb_data->lut_update_order[lut] >= + fb_data->cur_update->update_order) { + dev_dbg(fb_data->dev, "Ignoring collision with newer update.\n"); + ignore_collision = true; + break; + } + } + + if (ignore_collision) { + /* Add to free buffer list */ + list_add_tail(&fb_data->cur_update->list, + &fb_data->upd_buf_free_list->list); + } else { + /* + * If update has a marker, clear the LUT, since we + * don't want to signal that it is complete. + */ + if (fb_data->cur_update->upd_marker_data) + if (fb_data->cur_update->upd_marker_data->update_marker != 0) + fb_data->cur_update->upd_marker_data->lut_num = INVALID_LUT; + + /* Move to collision list */ + list_add_tail(&fb_data->cur_update->list, + &fb_data->upd_buf_collision_list->list); + } + } else { + /* Add to free buffer list */ + list_add_tail(&fb_data->cur_update->list, + &fb_data->upd_buf_free_list->list); + } + /* Clear current update */ + fb_data->cur_update = NULL; + + /* Clear IRQ for working buffer */ + epdc_working_buf_intr(false); + epdc_clear_working_buf_irq(); + } + + if (fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT) { + /* Queued update scheme processing */ + + /* Schedule task to submit collision and pending update */ + if (!fb_data->powering_down) + queue_work(fb_data->epdc_submit_workqueue, + &fb_data->epdc_submit_work); + + /* Release buffer queues */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + + return IRQ_HANDLED; + } + + /* Snapshot update scheme processing */ + + /* Check to see if any LUTs are free */ + if (!epdc_any_luts_available()) { + dev_dbg(fb_data->dev, "No luts available.\n"); + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return IRQ_HANDLED; + } + + /* + * Are any of our collision updates able to go now? + * Go through all updates in the collision list and check to see + * if the collision mask has been fully cleared + */ + list_for_each_entry(collision_update, + &fb_data->upd_buf_collision_list->list, list) { + + if (collision_update->collision_mask != 0) + continue; + + dev_dbg(fb_data->dev, "A collision update is ready to go!\n"); + /* + * We have a collision cleared, so select it + * and we will retry the update + */ + fb_data->cur_update = collision_update; + list_del_init(&fb_data->cur_update->list); + break; + } + + /* + * If we didn't find a collision update ready to go, + * we try to grab one from the update queue + */ + if (fb_data->cur_update == NULL) { + /* Is update list empty? */ + if (list_empty(&fb_data->upd_buf_queue->list)) { + dev_dbg(fb_data->dev, "No pending updates.\n"); + + /* No updates pending, so we are done */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + return IRQ_HANDLED; + } else { + dev_dbg(fb_data->dev, "Found a pending update!\n"); + + /* Process next item in update list */ + fb_data->cur_update = + list_entry(fb_data->upd_buf_queue->list.next, + struct update_data_list, list); + list_del_init(&fb_data->cur_update->list); + } + } + + /* LUTs are available, so we get one here */ + fb_data->cur_update->lut_num = epdc_get_next_lut(); + + /* Associate LUT with update marker */ + if ((fb_data->cur_update->upd_marker_data) + && (fb_data->cur_update->upd_marker_data->update_marker != 0)) + fb_data->cur_update->upd_marker_data->lut_num = + fb_data->cur_update->lut_num; + + /* Mark LUT as containing new update */ + fb_data->lut_update_order[fb_data->cur_update->lut_num] = + fb_data->cur_update->update_order; + + /* Enable Collision and WB complete IRQs */ + epdc_working_buf_intr(true); + epdc_lut_complete_intr(fb_data->cur_update->lut_num, true); + + /* Program EPDC update to process buffer */ + next_upd_region = &fb_data->cur_update->upd_data.update_region; + if (fb_data->cur_update->upd_data.temp != TEMP_USE_AMBIENT) { + temp_index = mxc_epdc_fb_get_temp_index(fb_data, fb_data->cur_update->upd_data.temp); + epdc_set_temp(temp_index); + } else + epdc_set_temp(fb_data->temp_index); + epdc_set_update_addr(fb_data->cur_update->phys_addr + fb_data->cur_update->epdc_offs); + epdc_set_update_coord(next_upd_region->left, next_upd_region->top); + epdc_set_update_dimensions(next_upd_region->width, + next_upd_region->height); + epdc_submit_update(fb_data->cur_update->lut_num, + fb_data->cur_update->upd_data.waveform_mode, + fb_data->cur_update->upd_data.update_mode, false, 0); + + /* Release buffer queues */ + spin_unlock_irqrestore(&fb_data->queue_lock, flags); + + return IRQ_HANDLED; +} + +static void draw_mode0(struct mxc_epdc_fb_data *fb_data) +{ + u32 *upd_buf_ptr; + int i; + struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var; + u32 xres, yres; + + upd_buf_ptr = (u32 *)fb_data->info.screen_base; + + epdc_working_buf_intr(true); + epdc_lut_complete_intr(0, true); + fb_data->in_init = true; + + /* Use unrotated (native) width/height */ + if ((screeninfo->rotate == FB_ROTATE_CW) || + (screeninfo->rotate == FB_ROTATE_CCW)) { + xres = screeninfo->yres; + yres = screeninfo->xres; + } else { + xres = screeninfo->xres; + yres = screeninfo->yres; + } + + /* Program EPDC update to process buffer */ + epdc_set_update_addr(fb_data->phys_start); + epdc_set_update_coord(0, 0); + epdc_set_update_dimensions(xres, yres); + epdc_submit_update(0, fb_data->wv_modes.mode_init, UPDATE_MODE_FULL, true, 0xFF); + + dev_dbg(fb_data->dev, "Mode0 update - Waiting for LUT to complete...\n"); + + /* Will timeout after ~4-5 seconds */ + + for (i = 0; i < 40; i++) { + if (!epdc_is_lut_active(0)) { + dev_dbg(fb_data->dev, "Mode0 init complete\n"); + return; + } + msleep(100); + } + + dev_err(fb_data->dev, "Mode0 init failed!\n"); + + return; +} + + +static void mxc_epdc_fb_fw_handler(const struct firmware *fw, + void *context) +{ + struct mxc_epdc_fb_data *fb_data = context; + int ret; + struct mxcfb_waveform_data_file *wv_file; + int wv_data_offs; + int i; + struct mxcfb_update_data update; + struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var; + u32 xres, yres; + + if (fw == NULL) { + /* If default FW file load failed, we give up */ + if (fb_data->fw_default_load) + return; + + /* Try to load default waveform */ + dev_dbg(fb_data->dev, + "Can't find firmware. Trying fallback fw\n"); + fb_data->fw_default_load = true; + ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, + "imx/epdc.fw", fb_data->dev, GFP_KERNEL, fb_data, + mxc_epdc_fb_fw_handler); + if (ret) + dev_err(fb_data->dev, + "Failed request_firmware_nowait err %d\n", ret); + + return; + } + + wv_file = (struct mxcfb_waveform_data_file *)fw->data; + + /* Get size and allocate temperature range table */ + fb_data->trt_entries = wv_file->wdh.trc + 1; + fb_data->temp_range_bounds = kzalloc(fb_data->trt_entries, GFP_KERNEL); + + for (i = 0; i < fb_data->trt_entries; i++) + dev_dbg(fb_data->dev, "trt entry #%d = 0x%x\n", i, *((u8 *)&wv_file->data + i)); + + /* Copy TRT data */ + memcpy(fb_data->temp_range_bounds, &wv_file->data, fb_data->trt_entries); + + /* Set default temperature index using TRT and room temp */ + fb_data->temp_index = mxc_epdc_fb_get_temp_index(fb_data, DEFAULT_TEMP); + + /* Get offset and size for waveform data */ + wv_data_offs = sizeof(wv_file->wdh) + fb_data->trt_entries + 1; + fb_data->waveform_buffer_size = fw->size - wv_data_offs; + + /* Allocate memory for waveform data */ + fb_data->waveform_buffer_virt = dma_alloc_coherent(fb_data->dev, + fb_data->waveform_buffer_size, + &fb_data->waveform_buffer_phys, + GFP_DMA); + if (fb_data->waveform_buffer_virt == NULL) { + dev_err(fb_data->dev, "Can't allocate mem for waveform!\n"); + return; + } + + memcpy(fb_data->waveform_buffer_virt, (u8 *)(fw->data) + wv_data_offs, + fb_data->waveform_buffer_size); + + release_firmware(fw); + + /* Enable clocks to access EPDC regs */ + clk_enable(fb_data->epdc_clk_axi); + + /* Enable pix clk for EPDC */ + clk_enable(fb_data->epdc_clk_pix); + clk_set_rate(fb_data->epdc_clk_pix, fb_data->cur_mode->vmode->pixclock); + + epdc_init_sequence(fb_data); + + /* Disable clocks */ + clk_disable(fb_data->epdc_clk_axi); + clk_disable(fb_data->epdc_clk_pix); + + fb_data->hw_ready = true; + + /* Use unrotated (native) width/height */ + if ((screeninfo->rotate == FB_ROTATE_CW) || + (screeninfo->rotate == FB_ROTATE_CCW)) { + xres = screeninfo->yres; + yres = screeninfo->xres; + } else { + xres = screeninfo->xres; + yres = screeninfo->yres; + } + + update.update_region.left = 0; + update.update_region.width = xres; + update.update_region.top = 0; + update.update_region.height = yres; + update.update_mode = UPDATE_MODE_FULL; + update.waveform_mode = WAVEFORM_MODE_AUTO; + update.update_marker = INIT_UPDATE_MARKER; + update.temp = TEMP_USE_AMBIENT; + update.flags = 0; + + mxc_epdc_fb_send_update(&update, &fb_data->info); + + /* Block on initial update */ + ret = mxc_epdc_fb_wait_update_complete(update.update_marker, + &fb_data->info); + if (ret < 0) + dev_err(fb_data->dev, + "Wait for update complete failed. Error = 0x%x", ret); +} + +static int mxc_epdc_fb_init_hw(struct fb_info *info) +{ + struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info; + int ret; + + /* + * Create fw search string based on ID string in selected videomode. + * Format is "imx/epdc_[panel string].fw" + */ + if (fb_data->cur_mode) { + strcat(fb_data->fw_str, "imx/epdc_"); + strcat(fb_data->fw_str, fb_data->cur_mode->vmode->name); + strcat(fb_data->fw_str, ".fw"); + } + + fb_data->fw_default_load = false; + + ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, + fb_data->fw_str, fb_data->dev, GFP_KERNEL, + fb_data, mxc_epdc_fb_fw_handler); + if (ret) + dev_dbg(fb_data->dev, + "Failed request_firmware_nowait err %d\n", ret); + + return ret; +} + +static ssize_t store_update(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mxcfb_update_data update; + struct fb_info *info = dev_get_drvdata(device); + struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info; + + if (strncmp(buf, "direct", 6) == 0) + update.waveform_mode = fb_data->wv_modes.mode_du; + else if (strncmp(buf, "gc16", 4) == 0) + update.waveform_mode = fb_data->wv_modes.mode_gc16; + else if (strncmp(buf, "gc4", 3) == 0) + update.waveform_mode = fb_data->wv_modes.mode_gc4; + + /* Now, request full screen update */ + update.update_region.left = 0; + update.update_region.width = fb_data->epdc_fb_var.xres; + update.update_region.top = 0; + update.update_region.height = fb_data->epdc_fb_var.yres; + update.update_mode = UPDATE_MODE_FULL; + update.temp = TEMP_USE_AMBIENT; + update.update_marker = 0; + update.flags = 0; + + mxc_epdc_fb_send_update(&update, info); + + return count; +} + +static struct device_attribute fb_attrs[] = { + __ATTR(update, S_IRUGO|S_IWUSR, NULL, store_update), +}; + +int __devinit mxc_epdc_fb_probe(struct platform_device *pdev) +{ + int ret = 0; + struct mxc_epdc_fb_data *fb_data; + struct resource *res; + struct fb_info *info; + char *options, *opt; + char *panel_str = NULL; + char name[] = "mxcepdcfb"; + struct fb_videomode *vmode; + int xres_virt, yres_virt, buf_size; + int xres_virt_rot, yres_virt_rot, buf_size_rot; + struct fb_var_screeninfo *var_info; + struct fb_fix_screeninfo *fix_info; + struct pxp_config_data *pxp_conf; + struct pxp_proc_data *proc_data; + struct scatterlist *sg; + struct update_data_list *upd_list; + struct update_data_list *plist, *temp_list; + int i; + unsigned long x_mem_size = 0; +#ifdef CONFIG_FRAMEBUFFER_CONSOLE + struct mxcfb_update_data update; +#endif + + fb_data = (struct mxc_epdc_fb_data *)framebuffer_alloc( + sizeof(struct mxc_epdc_fb_data), &pdev->dev); + if (fb_data == NULL) { + ret = -ENOMEM; + goto out; + } + + /* Get platform data and check validity */ + fb_data->pdata = pdev->dev.platform_data; + if ((fb_data->pdata == NULL) || (fb_data->pdata->num_modes < 1) + || (fb_data->pdata->epdc_mode == NULL) + || (fb_data->pdata->epdc_mode->vmode == NULL)) { + ret = -EINVAL; + goto out_fbdata; + } + + if (fb_get_options(name, &options)) { + ret = -ENODEV; + goto out_fbdata; + } + + if (options) + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + + if (!strncmp(opt, "bpp=", 4)) + fb_data->default_bpp = + simple_strtoul(opt + 4, NULL, 0); + else if (!strncmp(opt, "x_mem=", 6)) + x_mem_size = memparse(opt + 6, NULL); + else + panel_str = opt; + } + + fb_data->dev = &pdev->dev; + + if (!fb_data->default_bpp) + fb_data->default_bpp = 16; + + /* Set default (first defined mode) before searching for a match */ + fb_data->cur_mode = &fb_data->pdata->epdc_mode[0]; + + if (panel_str) + for (i = 0; i < fb_data->pdata->num_modes; i++) + if (!strcmp(fb_data->pdata->epdc_mode[i].vmode->name, + panel_str)) { + fb_data->cur_mode = + &fb_data->pdata->epdc_mode[i]; + break; + } + + vmode = fb_data->cur_mode->vmode; + + platform_set_drvdata(pdev, fb_data); + info = &fb_data->info; + + /* Allocate color map for the FB */ + ret = fb_alloc_cmap(&info->cmap, 256, 0); + if (ret) + goto out_fbdata; + + dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n", + vmode->xres, vmode->yres, fb_data->default_bpp); + + /* + * GPU alignment restrictions dictate framebuffer parameters: + * - 32-byte alignment for buffer width + * - 128-byte alignment for buffer height + * => 4K buffer alignment for buffer start + */ + xres_virt = ALIGN(vmode->xres, 32); + yres_virt = ALIGN(vmode->yres, 128); + buf_size = PAGE_ALIGN(xres_virt * yres_virt * fb_data->default_bpp/8); + + /* + * Have to check to see if aligned buffer size when rotated + * is bigger than when not rotated, and use the max + */ + xres_virt_rot = ALIGN(vmode->yres, 32); + yres_virt_rot = ALIGN(vmode->xres, 128); + buf_size_rot = PAGE_ALIGN(xres_virt_rot * yres_virt_rot + * fb_data->default_bpp/8); + buf_size = (buf_size > buf_size_rot) ? buf_size : buf_size_rot; + + /* Compute the number of screens needed based on X memory requested */ + if (x_mem_size > 0) { + fb_data->num_screens = DIV_ROUND_UP(x_mem_size, buf_size); + if (fb_data->num_screens < NUM_SCREENS_MIN) + fb_data->num_screens = NUM_SCREENS_MIN; + else if (buf_size * fb_data->num_screens > SZ_16M) + fb_data->num_screens = SZ_16M / buf_size; + } else + fb_data->num_screens = NUM_SCREENS_MIN; + + fb_data->map_size = buf_size * fb_data->num_screens; + dev_dbg(&pdev->dev, "memory to allocate: %d\n", fb_data->map_size); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + ret = -ENODEV; + goto out_cmap; + } + + epdc_base = ioremap(res->start, SZ_4K); + if (epdc_base == NULL) { + ret = -ENOMEM; + goto out_cmap; + } + + /* Allocate FB memory */ + info->screen_base = dma_alloc_writecombine(&pdev->dev, + fb_data->map_size, + &fb_data->phys_start, + GFP_DMA); + + if (info->screen_base == NULL) { + ret = -ENOMEM; + goto out_mapregs; + } + dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", info->screen_base, + fb_data->phys_start); + + var_info = &info->var; + var_info->activate = FB_ACTIVATE_TEST; + var_info->bits_per_pixel = fb_data->default_bpp; + var_info->xres = vmode->xres; + var_info->yres = vmode->yres; + var_info->xres_virtual = xres_virt; + /* Additional screens allow for panning and buffer flipping */ + var_info->yres_virtual = yres_virt * fb_data->num_screens; + + var_info->pixclock = vmode->pixclock; + var_info->left_margin = vmode->left_margin; + var_info->right_margin = vmode->right_margin; + var_info->upper_margin = vmode->upper_margin; + var_info->lower_margin = vmode->lower_margin; + var_info->hsync_len = vmode->hsync_len; + var_info->vsync_len = vmode->vsync_len; + var_info->vmode = FB_VMODE_NONINTERLACED; + + switch (fb_data->default_bpp) { + case 32: + case 24: + var_info->red.offset = 16; + var_info->red.length = 8; + var_info->green.offset = 8; + var_info->green.length = 8; + var_info->blue.offset = 0; + var_info->blue.length = 8; + break; + + case 16: + var_info->red.offset = 11; + var_info->red.length = 5; + var_info->green.offset = 5; + var_info->green.length = 6; + var_info->blue.offset = 0; + var_info->blue.length = 5; + break; + + case 8: + /* + * For 8-bit grayscale, R, G, and B offset are equal. + * + */ + var_info->grayscale = GRAYSCALE_8BIT; + + var_info->red.length = 8; + var_info->red.offset = 0; + var_info->red.msb_right = 0; + var_info->green.length = 8; + var_info->green.offset = 0; + var_info->green.msb_right = 0; + var_info->blue.length = 8; + var_info->blue.offset = 0; + var_info->blue.msb_right = 0; + break; + + default: + dev_err(&pdev->dev, "unsupported bitwidth %d\n", + fb_data->default_bpp); + ret = -EINVAL; + goto out_dma_fb; + } + + fix_info = &info->fix; + + strcpy(fix_info->id, "mxc_epdc_fb"); + fix_info->type = FB_TYPE_PACKED_PIXELS; + fix_info->visual = FB_VISUAL_TRUECOLOR; + fix_info->xpanstep = 0; + fix_info->ypanstep = 0; + fix_info->ywrapstep = 0; + fix_info->accel = FB_ACCEL_NONE; + fix_info->smem_start = fb_data->phys_start; + fix_info->smem_len = fb_data->map_size; + fix_info->ypanstep = 0; + + fb_data->native_width = vmode->xres; + fb_data->native_height = vmode->yres; + + info->fbops = &mxc_epdc_fb_ops; + info->var.activate = FB_ACTIVATE_NOW; + info->pseudo_palette = fb_data->pseudo_palette; + info->screen_size = info->fix.smem_len; + info->flags = FBINFO_FLAG_DEFAULT; + + mxc_epdc_fb_set_fix(info); + + fb_data->auto_mode = AUTO_UPDATE_MODE_REGION_MODE; + fb_data->upd_scheme = UPDATE_SCHEME_SNAPSHOT; + + /* Initialize our internal copy of the screeninfo */ + fb_data->epdc_fb_var = *var_info; + fb_data->fb_offset = 0; + + /* Allocate head objects for our lists */ + fb_data->upd_buf_queue = + kzalloc(sizeof(struct update_data_list), GFP_KERNEL); + fb_data->upd_buf_collision_list = + kzalloc(sizeof(struct update_data_list), GFP_KERNEL); + fb_data->upd_buf_free_list = + kzalloc(sizeof(struct update_data_list), GFP_KERNEL); + if ((fb_data->upd_buf_queue == NULL) || (fb_data->upd_buf_free_list == NULL) + || (fb_data->upd_buf_collision_list == NULL)) { + ret = -ENOMEM; + goto out_dma_fb; + } + + /* + * Initialize lists for update requests, update collisions, + * and available update (PxP output) buffers + */ + INIT_LIST_HEAD(&fb_data->upd_buf_queue->list); + INIT_LIST_HEAD(&fb_data->upd_buf_free_list->list); + INIT_LIST_HEAD(&fb_data->upd_buf_collision_list->list); + + /* Allocate update buffers and add them to the list */ + for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) { + upd_list = kzalloc(sizeof(*upd_list), GFP_KERNEL); + if (upd_list == NULL) { + ret = -ENOMEM; + goto out_upd_buffers; + } + + /* Clear update data structure */ + memset(&upd_list->upd_data, 0, + sizeof(struct mxcfb_update_data)); + + /* + * Each update buffer is 1 byte per pixel, and can + * be as big as the full-screen frame buffer + */ + upd_list->size = info->var.xres * info->var.yres; + + /* Allocate memory for PxP output buffer */ + upd_list->virt_addr = + dma_alloc_coherent(fb_data->info.device, upd_list->size, + &upd_list->phys_addr, GFP_DMA); + if (upd_list->virt_addr == NULL) { + kfree(upd_list); + ret = -ENOMEM; + goto out_upd_buffers; + } + + /* Add newly allocated buffer to free list */ + list_add(&upd_list->list, &fb_data->upd_buf_free_list->list); + + dev_dbg(fb_data->info.device, "allocated %d bytes @ 0x%08X\n", + upd_list->size, upd_list->phys_addr); + } + + fb_data->working_buffer_size = vmode->yres * vmode->xres * 2; + /* Allocate memory for EPDC working buffer */ + fb_data->working_buffer_virt = + dma_alloc_coherent(&pdev->dev, fb_data->working_buffer_size, + &fb_data->working_buffer_phys, GFP_DMA); + if (fb_data->working_buffer_virt == NULL) { + dev_err(&pdev->dev, "Can't allocate mem for working buf!\n"); + ret = -ENOMEM; + goto out_upd_buffers; + } + + /* Initialize EPDC pins */ + if (fb_data->pdata->get_pins) + fb_data->pdata->get_pins(); + + fb_data->epdc_clk_axi = clk_get(fb_data->dev, "epdc_axi"); + if (IS_ERR(fb_data->epdc_clk_axi)) { + dev_err(&pdev->dev, "Unable to get EPDC AXI clk." + "err = 0x%x\n", (int)fb_data->epdc_clk_axi); + ret = -ENODEV; + goto out_upd_buffers; + } + fb_data->epdc_clk_pix = clk_get(fb_data->dev, "epdc_pix"); + if (IS_ERR(fb_data->epdc_clk_pix)) { + dev_err(&pdev->dev, "Unable to get EPDC pix clk." + "err = 0x%x\n", (int)fb_data->epdc_clk_pix); + ret = -ENODEV; + goto out_upd_buffers; + } + + fb_data->in_init = false; + + fb_data->hw_ready = false; + + /* + * Set default waveform mode values. + * Should be overwritten via ioctl. + */ + fb_data->wv_modes.mode_init = 0; + fb_data->wv_modes.mode_du = 1; + fb_data->wv_modes.mode_gc4 = 3; + fb_data->wv_modes.mode_gc8 = 2; + fb_data->wv_modes.mode_gc16 = 2; + fb_data->wv_modes.mode_gc32 = 2; + + /* Initialize markers */ + for (i = 0; i < EPDC_MAX_NUM_UPDATES; i++) { + fb_data->update_marker_array[i].update_marker = 0; + fb_data->update_marker_array[i].lut_num = INVALID_LUT; + } + + /* Initialize all LUTs to inactive */ + for (i = 0; i < EPDC_NUM_LUTS; i++) + fb_data->lut_update_order[i] = 0; + + /* Retrieve EPDC IRQ num */ + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&pdev->dev, "cannot get IRQ resource\n"); + ret = -ENODEV; + goto out_dma_work_buf; + } + fb_data->epdc_irq = res->start; + + /* Register IRQ handler */ + ret = request_irq(fb_data->epdc_irq, mxc_epdc_irq_handler, 0, + "fb_dma", fb_data); + if (ret) { + dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n", + fb_data->epdc_irq, ret); + ret = -ENODEV; + goto out_dma_work_buf; + } + + INIT_DELAYED_WORK(&fb_data->epdc_done_work, epdc_done_work_func); + fb_data->epdc_submit_workqueue = create_rt_workqueue("submit"); + INIT_WORK(&fb_data->epdc_submit_work, epdc_submit_work_func); + + info->fbdefio = &mxc_epdc_fb_defio; +#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE + fb_deferred_io_init(info); +#endif + + /* get pmic regulators */ + fb_data->display_regulator = regulator_get(NULL, "DISPLAY"); + if (IS_ERR(fb_data->display_regulator)) { + dev_err(&pdev->dev, "Unable to get display PMIC regulator." + "err = 0x%x\n", (int)fb_data->display_regulator); + ret = -ENODEV; + goto out_irq; + } + fb_data->vcom_regulator = regulator_get(NULL, "VCOM"); + if (IS_ERR(fb_data->vcom_regulator)) { + regulator_put(fb_data->display_regulator); + dev_err(&pdev->dev, "Unable to get VCOM regulator." + "err = 0x%x\n", (int)fb_data->vcom_regulator); + ret = -ENODEV; + goto out_irq; + } + + if (device_create_file(info->dev, &fb_attrs[0])) + dev_err(&pdev->dev, "Unable to create file from fb_attrs\n"); + + fb_data->cur_update = NULL; + + spin_lock_init(&fb_data->queue_lock); + + mutex_init(&fb_data->pxp_mutex); + + mutex_init(&fb_data->power_mutex); + + /* PxP DMA interface */ + dmaengine_get(); + + /* + * Fill out PxP config data structure based on FB info and + * processing tasks required + */ + pxp_conf = &fb_data->pxp_conf; + proc_data = &pxp_conf->proc_data; + + /* Initialize non-channel-specific PxP parameters */ + proc_data->drect.left = proc_data->srect.left = 0; + proc_data->drect.top = proc_data->srect.top = 0; + proc_data->drect.width = proc_data->srect.width = fb_data->info.var.xres; + proc_data->drect.height = proc_data->srect.height = fb_data->info.var.yres; + proc_data->scaling = 0; + proc_data->hflip = 0; + proc_data->vflip = 0; + proc_data->rotate = 0; + proc_data->bgcolor = 0; + proc_data->overlay_state = 0; + proc_data->lut_transform = PXP_LUT_NONE; + + /* + * We initially configure PxP for RGB->YUV conversion, + * and only write out Y component of the result. + */ + + /* + * Initialize S0 channel parameters + * Parameters should match FB format/width/height + */ + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565; + pxp_conf->s0_param.width = fb_data->info.var.xres_virtual; + pxp_conf->s0_param.height = fb_data->info.var.yres; + pxp_conf->s0_param.color_key = -1; + pxp_conf->s0_param.color_key_enable = false; + + /* + * Initialize OL0 channel parameters + * No overlay will be used for PxP operation + */ + for (i = 0; i < 8; i++) { + pxp_conf->ol_param[i].combine_enable = false; + pxp_conf->ol_param[i].width = 0; + pxp_conf->ol_param[i].height = 0; + pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565; + pxp_conf->ol_param[i].color_key_enable = false; + pxp_conf->ol_param[i].color_key = -1; + pxp_conf->ol_param[i].global_alpha_enable = false; + pxp_conf->ol_param[i].global_alpha = 0; + pxp_conf->ol_param[i].local_alpha_enable = false; + } + + /* + * Initialize Output channel parameters + * Output is Y-only greyscale + * Output width/height will vary based on update region size + */ + pxp_conf->out_param.width = fb_data->info.var.xres; + pxp_conf->out_param.height = fb_data->info.var.yres; + pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY; + + /* + * Ensure this is set to NULL here...we will initialize pxp_chan + * later in our thread. + */ + fb_data->pxp_chan = NULL; + + /* Initialize Scatter-gather list containing 2 buffer addresses. */ + sg = fb_data->sg; + sg_init_table(sg, 2); + + /* + * For use in PxP transfers: + * sg[0] holds the FB buffer pointer + * sg[1] holds the Output buffer pointer (configured before TX request) + */ + sg_dma_address(&sg[0]) = info->fix.smem_start; + sg_set_page(&sg[0], virt_to_page(info->screen_base), + info->fix.smem_len, offset_in_page(info->screen_base)); + + fb_data->order_cnt = 0; + fb_data->waiting_for_wb = false; + fb_data->waiting_for_lut = false; + fb_data->waiting_for_idle = false; + fb_data->blank = FB_BLANK_UNBLANK; + fb_data->power_state = POWER_STATE_OFF; + fb_data->powering_down = false; + fb_data->pwrdown_delay = 0; + + /* Register FB */ + ret = register_framebuffer(info); + if (ret) { + dev_err(&pdev->dev, + "register_framebuffer failed with error %d\n", ret); + goto out_dmaengine; + } + + g_fb_data = fb_data; + +#ifdef DEFAULT_PANEL_HW_INIT + ret = mxc_epdc_fb_init_hw((struct fb_info *)fb_data); + if (ret) { + dev_err(&pdev->dev, "Failed to initialize HW!\n"); + } +#endif + +#ifdef CONFIG_FRAMEBUFFER_CONSOLE + /* If FB console included, update display to show logo */ + update.update_region.left = 0; + update.update_region.width = info->var.xres; + update.update_region.top = 0; + update.update_region.height = info->var.yres; + update.update_mode = UPDATE_MODE_PARTIAL; + update.waveform_mode = WAVEFORM_MODE_AUTO; + update.update_marker = INIT_UPDATE_MARKER; + update.temp = TEMP_USE_AMBIENT; + update.flags = 0; + + mxc_epdc_fb_send_update(&update, info); + + ret = mxc_epdc_fb_wait_update_complete(update.update_marker, info); + if (ret < 0) + dev_err(fb_data->dev, + "Wait for update complete failed. Error = 0x%x", ret); +#endif + + goto out; + +out_dmaengine: + dmaengine_put(); +out_irq: + free_irq(fb_data->epdc_irq, fb_data); +out_dma_work_buf: + dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size, + fb_data->working_buffer_virt, fb_data->working_buffer_phys); + if (fb_data->pdata->put_pins) + fb_data->pdata->put_pins(); +out_upd_buffers: + list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list->list, list) { + list_del(&plist->list); + dma_free_writecombine(&pdev->dev, plist->size, plist->virt_addr, + plist->phys_addr); + kfree(plist); + } +out_dma_fb: + dma_free_writecombine(&pdev->dev, fb_data->map_size, info->screen_base, + fb_data->phys_start); + +out_mapregs: + iounmap(epdc_base); +out_cmap: + fb_dealloc_cmap(&info->cmap); +out_fbdata: + kfree(fb_data); +out: + return ret; +} + +static int mxc_epdc_fb_remove(struct platform_device *pdev) +{ + struct update_data_list *plist, *temp_list; + struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev); + + mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &fb_data->info); + + flush_workqueue(fb_data->epdc_submit_workqueue); + destroy_workqueue(fb_data->epdc_submit_workqueue); + + regulator_put(fb_data->display_regulator); + regulator_put(fb_data->vcom_regulator); + + unregister_framebuffer(&fb_data->info); + free_irq(fb_data->epdc_irq, fb_data); + + dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size, + fb_data->working_buffer_virt, + fb_data->working_buffer_phys); + if (fb_data->waveform_buffer_virt != NULL) + dma_free_writecombine(&pdev->dev, fb_data->waveform_buffer_size, + fb_data->waveform_buffer_virt, + fb_data->waveform_buffer_phys); + list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list->list, list) { + list_del(&plist->list); + dma_free_writecombine(&pdev->dev, plist->size, plist->virt_addr, + plist->phys_addr); + kfree(plist); + } +#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE + fb_deferred_io_cleanup(&fb_data->info); +#endif + + dma_free_writecombine(&pdev->dev, fb_data->map_size, fb_data->info.screen_base, + fb_data->phys_start); + + if (fb_data->pdata->put_pins) + fb_data->pdata->put_pins(); + + /* Release PxP-related resources */ + if (fb_data->pxp_chan != NULL) + dma_release_channel(&fb_data->pxp_chan->dma_chan); + + dmaengine_put(); + + iounmap(epdc_base); + + fb_dealloc_cmap(&fb_data->info.cmap); + + framebuffer_release(&fb_data->info); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int mxc_epdc_fb_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev); + int ret; + + ret = mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &data->info); + if (ret) + goto out; + +out: + return ret; +} + +static int mxc_epdc_fb_resume(struct platform_device *pdev) +{ + struct mxc_epdc_fb_data *data = platform_get_drvdata(pdev); + + mxc_epdc_fb_blank(FB_BLANK_UNBLANK, &data->info); + return 0; +} +#else +#define mxc_epdc_fb_suspend NULL +#define mxc_epdc_fb_resume NULL +#endif + +static struct platform_driver mxc_epdc_fb_driver = { + .probe = mxc_epdc_fb_probe, + .remove = mxc_epdc_fb_remove, + .suspend = mxc_epdc_fb_suspend, + .resume = mxc_epdc_fb_resume, + .driver = { + .name = "mxc_epdc_fb", + .owner = THIS_MODULE, + }, +}; + +/* Callback function triggered after PxP receives an EOF interrupt */ +static void pxp_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + struct mxc_epdc_fb_data *fb_data = pxp_chan->client; + + /* This call will signal wait_for_completion_timeout() in send_buffer_to_pxp */ + complete(&fb_data->pxp_tx_cmpl); +} + +/* Function to request PXP DMA channel */ +static int pxp_chan_init(struct mxc_epdc_fb_data *fb_data) +{ + dma_cap_mask_t mask; + struct dma_chan *chan; + + /* + * Request a free channel + */ + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + chan = dma_request_channel(mask, NULL, NULL); + if (!chan) { + dev_err(fb_data->dev, "Unsuccessfully received channel!!!!\n"); + return -EBUSY; + } + + dev_dbg(fb_data->dev, "Successfully received channel.\n"); + + fb_data->pxp_chan = to_pxp_channel(chan); + + fb_data->pxp_chan->client = fb_data; + + init_completion(&fb_data->pxp_tx_cmpl); + + return 0; +} + +/* + * Function to call PxP DMA driver and send our latest FB update region + * through the PxP and out to an intermediate buffer. + * Note: This is a blocking call, so upon return the PxP tx should be complete. + */ +static int pxp_process_update(struct mxc_epdc_fb_data *fb_data, + u32 src_width, u32 src_height, + struct mxcfb_rect *update_region, + int x_start_offs) +{ + dma_cookie_t cookie; + struct scatterlist *sg = fb_data->sg; + struct dma_chan *dma_chan; + struct pxp_tx_desc *desc; + struct dma_async_tx_descriptor *txd; + struct pxp_config_data *pxp_conf = &fb_data->pxp_conf; + struct pxp_proc_data *proc_data = &fb_data->pxp_conf.proc_data; + int i, ret; + int length; + + dev_dbg(fb_data->dev, "Starting PxP Send Buffer\n"); + + /* First, check to see that we have acquired a PxP Channel object */ + if (fb_data->pxp_chan == NULL) { + /* + * PxP Channel has not yet been created and initialized, + * so let's go ahead and try + */ + ret = pxp_chan_init(fb_data); + if (ret) { + /* + * PxP channel init failed, and we can't use the + * PxP until the PxP DMA driver has loaded, so we abort + */ + dev_err(fb_data->dev, "PxP chan init failed\n"); + return -ENODEV; + } + } + + /* + * Init completion, so that we + * can be properly informed of the completion + * of the PxP task when it is done. + */ + init_completion(&fb_data->pxp_tx_cmpl); + + dev_dbg(fb_data->dev, "sg[0] = 0x%x, sg[1] = 0x%x\n", + sg_dma_address(&sg[0]), sg_dma_address(&sg[1])); + + dma_chan = &fb_data->pxp_chan->dma_chan; + + txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2, + DMA_TO_DEVICE, + DMA_PREP_INTERRUPT); + if (!txd) { + dev_err(fb_data->info.device, + "Error preparing a DMA transaction descriptor.\n"); + return -EIO; + } + + txd->callback_param = txd; + txd->callback = pxp_dma_done; + + /* + * Configure PxP for processing of new update region + * The rest of our config params were set up in + * probe() and should not need to be changed. + */ + pxp_conf->s0_param.width = src_width; + pxp_conf->s0_param.height = src_height; + proc_data->srect.top = update_region->top; + proc_data->srect.left = update_region->left + x_start_offs; + proc_data->srect.width = update_region->width; + proc_data->srect.height = update_region->height; + + /* + * Because only YUV/YCbCr image can be scaled, configure + * drect equivalent to srect, as such do not perform scaling. + */ + proc_data->drect.top = 0; + proc_data->drect.left = 0; + proc_data->drect.width = proc_data->srect.width; + proc_data->drect.height = proc_data->srect.height; + + /* PXP expects rotation in terms of degrees */ + proc_data->rotate = fb_data->epdc_fb_var.rotate * 90; + if (proc_data->rotate > 270) + proc_data->rotate = 0; + + pxp_conf->out_param.width = update_region->width; + pxp_conf->out_param.height = update_region->height; + + desc = to_tx_desc(txd); + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) {/* S0 */ + memcpy(&desc->proc_data, proc_data, sizeof(struct pxp_proc_data)); + pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]); + memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { + pxp_conf->out_param.paddr = sg_dma_address(&sg[1]); + memcpy(&desc->layer_param.out_param, &pxp_conf->out_param, + sizeof(struct pxp_layer_param)); + } + /* TODO: OverLay */ + + desc = desc->next; + } + + /* Submitting our TX starts the PxP processing task */ + cookie = txd->tx_submit(txd); + dev_dbg(fb_data->info.device, "%d: Submit %p #%d\n", __LINE__, txd, + cookie); + if (cookie < 0) { + dev_err(fb_data->info.device, "Error sending FB through PxP\n"); + return -EIO; + } + + fb_data->txd = txd; + + /* trigger ePxP */ + dma_async_issue_pending(dma_chan); + + return 0; +} + +static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat) +{ + int ret; + /* + * Wait for completion event, which will be set + * through our TX callback function. + */ + ret = wait_for_completion_timeout(&fb_data->pxp_tx_cmpl, HZ / 10); + if (ret <= 0) { + dev_info(fb_data->info.device, + "PxP operation failed due to %s\n", + ret < 0 ? "user interrupt" : "timeout"); + dma_release_channel(&fb_data->pxp_chan->dma_chan); + fb_data->pxp_chan = NULL; + return ret ? : -ETIMEDOUT; + } + + *hist_stat = to_tx_desc(fb_data->txd)->hist_status; + dma_release_channel(&fb_data->pxp_chan->dma_chan); + fb_data->pxp_chan = NULL; + + dev_dbg(fb_data->dev, "TX completed\n"); + + return 0; +} + +static int __init mxc_epdc_fb_init(void) +{ + return platform_driver_register(&mxc_epdc_fb_driver); +} +late_initcall(mxc_epdc_fb_init); + + +static void __exit mxc_epdc_fb_exit(void) +{ + platform_driver_unregister(&mxc_epdc_fb_driver); +} +module_exit(mxc_epdc_fb_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC EPDC framebuffer driver"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("fb"); diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c new file mode 100644 index 000000000000..1b9930a214c0 --- /dev/null +++ b/drivers/video/mxc/mxc_ipuv3_fb.c @@ -0,0 +1,2074 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxcfb.c + * + * @brief MXC Frame buffer driver for SDC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Driver name + */ +#define MXCFB_NAME "mxc_sdc_fb" + +/* Display port number */ +#define MXCFB_PORT_NUM 2 +/*! + * Structure containing the MXC specific framebuffer information. + */ +struct mxcfb_info { + char *fb_mode_str; + int default_bpp; + int cur_blank; + int next_blank; + ipu_channel_t ipu_ch; + int ipu_di; + u32 ipu_di_pix_fmt; + bool ipu_int_clk; + bool overlay; + bool alpha_chan_en; + dma_addr_t alpha_phy_addr0; + dma_addr_t alpha_phy_addr1; + void *alpha_virt_addr0; + void *alpha_virt_addr1; + uint32_t alpha_mem_len; + uint32_t ipu_ch_irq; + uint32_t ipu_alp_ch_irq; + uint32_t cur_ipu_buf; + uint32_t cur_ipu_alpha_buf; + + u32 pseudo_palette[16]; + + bool wait4vsync; + uint32_t waitcnt; + struct semaphore flip_sem; + struct semaphore alpha_flip_sem; + struct completion vsync_complete; +}; + +struct mxcfb_mode { + int dev_mode; + int num_modes; + struct fb_videomode *mode; +}; + +struct mxcfb_alloc_list { + struct list_head list; + dma_addr_t phy_addr; + void *cpu_addr; + u32 size; +}; + +enum { + BOTH_ON, + SRC_ON, + TGT_ON, + BOTH_OFF +}; + +static bool g_dp_in_use; +LIST_HEAD(fb_alloc_list); +static struct fb_info *mxcfb_info[3]; +static __initdata struct mxcfb_mode mxc_disp_mode[MXCFB_PORT_NUM]; +static __initdata int (*mxcfb_pre_setup[MXCFB_PORT_NUM])(struct fb_info *info); + +/* + * register pre-setup callback for some display + * driver which need prepare clk etc. + */ +void mxcfb_register_presetup(int disp_port, + int (*pre_setup)(struct fb_info *info)) +{ + if (pre_setup) + mxcfb_pre_setup[disp_port] = pre_setup; +} +EXPORT_SYMBOL(mxcfb_register_presetup); + +/* + * mode register from each display driver before + * primary fb setting. + */ +void mxcfb_register_mode(int disp_port, + const struct fb_videomode *modedb, + int num_modes, int dev_mode) +{ + struct fb_videomode *mode; + int mode_sum; + + if (disp_port > MXCFB_PORT_NUM) + return; + + /* + * if there is new DDC device, overwrite old modes. + * if there is old DDC device while new device is not DDC, + * just keep old DDC modes. + */ + if (dev_mode & MXC_DISP_DDC_DEV) { + if (mxc_disp_mode[disp_port].num_modes) { + kfree(mxc_disp_mode[disp_port].mode); + mxc_disp_mode[disp_port].num_modes = 0; + } + } else if (mxc_disp_mode[disp_port].dev_mode & MXC_DISP_DDC_DEV) + return; + + mode_sum = mxc_disp_mode[disp_port].num_modes + num_modes; + mode = kzalloc(mode_sum * sizeof(struct fb_videomode), GFP_KERNEL); + + if (mxc_disp_mode[disp_port].num_modes) + memcpy(mode, mxc_disp_mode[disp_port].mode, + mxc_disp_mode[disp_port].num_modes + * sizeof(struct fb_videomode)); + if (modedb) + memcpy(mode + mxc_disp_mode[disp_port].num_modes, + modedb, num_modes * sizeof(struct fb_videomode)); + + if (mxc_disp_mode[disp_port].num_modes) + kfree(mxc_disp_mode[disp_port].mode); + + mxc_disp_mode[disp_port].mode = mode; + mxc_disp_mode[disp_port].num_modes += num_modes; + mxc_disp_mode[disp_port].dev_mode = dev_mode; + + return; +} +EXPORT_SYMBOL(mxcfb_register_mode); + +static uint32_t bpp_to_pixfmt(struct fb_info *fbi) +{ + uint32_t pixfmt = 0; + + if (fbi->var.nonstd) + return fbi->var.nonstd; + + switch (fbi->var.bits_per_pixel) { + case 24: + pixfmt = IPU_PIX_FMT_BGR24; + break; + case 32: + pixfmt = IPU_PIX_FMT_BGR32; + break; + case 16: + pixfmt = IPU_PIX_FMT_RGB565; + break; + } + return pixfmt; +} + +static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id); +static int mxcfb_blank(int blank, struct fb_info *info); +static int mxcfb_map_video_memory(struct fb_info *fbi); +static int mxcfb_unmap_video_memory(struct fb_info *fbi); +static int mxcfb_option_setup(struct fb_info *info, char *options); + +/* + * Set fixed framebuffer parameters based on variable settings. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + + fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; + + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 0; + fix->ywrapstep = 1; + fix->ypanstep = 1; + + return 0; +} + +static int _setup_disp_channel1(struct fb_info *fbi) +{ + ipu_channel_params_t params; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + memset(¶ms, 0, sizeof(params)); + params.mem_dp_bg_sync.di = mxc_fbi->ipu_di; + + /* + * Assuming interlaced means yuv output, below setting also + * valid for mem_dc_sync. FG should have the same vmode as BG. + */ + if (mxc_fbi->ipu_ch == MEM_FG_SYNC) { + struct mxcfb_info *mxc_fbi_tmp; + int i; + + for (i = 0; i < num_registered_fb; i++) { + mxc_fbi_tmp = (struct mxcfb_info *) + (registered_fb[i]->par); + if (mxc_fbi_tmp->ipu_ch == MEM_BG_SYNC) { + fbi->var.vmode = + registered_fb[i]->var.vmode; + mxc_fbi->ipu_di_pix_fmt = + mxc_fbi_tmp->ipu_di_pix_fmt; + break; + } + } + } + if (mxc_fbi->ipu_ch == MEM_DC_SYNC) { + if (fbi->var.vmode & FB_VMODE_INTERLACED) { + params.mem_dc_sync.interlaced = true; + params.mem_dc_sync.out_pixel_fmt = + IPU_PIX_FMT_YUV444; + } else { + if (mxc_fbi->ipu_di_pix_fmt) + params.mem_dc_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt; + else + params.mem_dc_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666; + } + params.mem_dc_sync.in_pixel_fmt = bpp_to_pixfmt(fbi); + } else { + if (fbi->var.vmode & FB_VMODE_INTERLACED) { + params.mem_dp_bg_sync.interlaced = true; + params.mem_dp_bg_sync.out_pixel_fmt = + IPU_PIX_FMT_YUV444; + } else { + if (mxc_fbi->ipu_di_pix_fmt) + params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt; + else + params.mem_dp_bg_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666; + } + params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi); + if (mxc_fbi->alpha_chan_en) + params.mem_dp_bg_sync.alpha_chan_en = true; + } + ipu_init_channel(mxc_fbi->ipu_ch, ¶ms); + + return 0; +} + +static int _setup_disp_channel2(struct fb_info *fbi) +{ + int retval = 0; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + int fb_stride; + unsigned long base; + + switch (bpp_to_pixfmt(fbi)) { + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YVU420P: + case IPU_PIX_FMT_NV12: + case IPU_PIX_FMT_YUV422P: + case IPU_PIX_FMT_YVU422P: + case IPU_PIX_FMT_YUV420P: + fb_stride = fbi->var.xres_virtual; + break; + default: + fb_stride = fbi->fix.line_length; + } + + mxc_fbi->cur_ipu_buf = 1; + sema_init(&mxc_fbi->flip_sem, 1); + if (mxc_fbi->alpha_chan_en) { + mxc_fbi->cur_ipu_alpha_buf = 1; + sema_init(&mxc_fbi->alpha_flip_sem, 1); + } + fbi->var.xoffset = 0; + + base = (fbi->var.yoffset * fbi->var.xres_virtual + fbi->var.xoffset); + base = (fbi->var.bits_per_pixel) * base / 8; + base += fbi->fix.smem_start; + + retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi), + fbi->var.xres, fbi->var.yres, + fb_stride, + IPU_ROTATE_NONE, + base, + base, + 0, 0); + if (retval) { + dev_err(fbi->device, + "ipu_init_channel_buffer error %d\n", retval); + } + + if (mxc_fbi->alpha_chan_en) { + retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, + IPU_ALPHA_IN_BUFFER, + IPU_PIX_FMT_GENERIC, + fbi->var.xres, fbi->var.yres, + fbi->var.xres, + IPU_ROTATE_NONE, + mxc_fbi->alpha_phy_addr1, + mxc_fbi->alpha_phy_addr0, + 0, 0); + if (retval) { + dev_err(fbi->device, + "ipu_init_channel_buffer error %d\n", retval); + return retval; + } + } + + return retval; +} + +/* + * Set framebuffer parameters and change the operating mode. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_par(struct fb_info *fbi) +{ + int retval = 0; + u32 mem_len, alpha_mem_len; + ipu_di_signal_cfg_t sig_cfg; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + dev_dbg(fbi->device, "Reconfiguring framebuffer\n"); + + ipu_disable_irq(mxc_fbi->ipu_ch_irq); + ipu_disable_channel(mxc_fbi->ipu_ch, true); + ipu_uninit_channel(mxc_fbi->ipu_ch); + ipu_clear_irq(mxc_fbi->ipu_ch_irq); + mxcfb_set_fix(fbi); + + mem_len = fbi->var.yres_virtual * fbi->fix.line_length; + if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) { + if (fbi->fix.smem_start) + mxcfb_unmap_video_memory(fbi); + + if (mxcfb_map_video_memory(fbi) < 0) + return -ENOMEM; + } + if (mxc_fbi->alpha_chan_en) { + alpha_mem_len = fbi->var.xres * fbi->var.yres; + if ((!mxc_fbi->alpha_phy_addr0 && !mxc_fbi->alpha_phy_addr1) || + (alpha_mem_len > mxc_fbi->alpha_mem_len)) { + if (mxc_fbi->alpha_phy_addr0) + dma_free_coherent(fbi->device, + mxc_fbi->alpha_mem_len, + mxc_fbi->alpha_virt_addr0, + mxc_fbi->alpha_phy_addr0); + if (mxc_fbi->alpha_phy_addr1) + dma_free_coherent(fbi->device, + mxc_fbi->alpha_mem_len, + mxc_fbi->alpha_virt_addr1, + mxc_fbi->alpha_phy_addr1); + + mxc_fbi->alpha_virt_addr0 = + dma_alloc_coherent(fbi->device, + alpha_mem_len, + &mxc_fbi->alpha_phy_addr0, + GFP_DMA | GFP_KERNEL); + + mxc_fbi->alpha_virt_addr1 = + dma_alloc_coherent(fbi->device, + alpha_mem_len, + &mxc_fbi->alpha_phy_addr1, + GFP_DMA | GFP_KERNEL); + if (mxc_fbi->alpha_virt_addr0 == NULL || + mxc_fbi->alpha_virt_addr1 == NULL) { + dev_err(fbi->device, "mxcfb: dma alloc for" + " alpha buffer failed.\n"); + if (mxc_fbi->alpha_virt_addr0) + dma_free_coherent(fbi->device, + mxc_fbi->alpha_mem_len, + mxc_fbi->alpha_virt_addr0, + mxc_fbi->alpha_phy_addr0); + if (mxc_fbi->alpha_virt_addr1) + dma_free_coherent(fbi->device, + mxc_fbi->alpha_mem_len, + mxc_fbi->alpha_virt_addr1, + mxc_fbi->alpha_phy_addr1); + return -ENOMEM; + } + mxc_fbi->alpha_mem_len = alpha_mem_len; + } + } + + if (mxc_fbi->next_blank != FB_BLANK_UNBLANK) + return retval; + + _setup_disp_channel1(fbi); + + if (!mxc_fbi->overlay) { + uint32_t out_pixel_fmt; + + memset(&sig_cfg, 0, sizeof(sig_cfg)); + if (fbi->var.vmode & FB_VMODE_INTERLACED) { + sig_cfg.interlaced = true; + out_pixel_fmt = IPU_PIX_FMT_YUV444; + } else { + if (mxc_fbi->ipu_di_pix_fmt) + out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt; + else + out_pixel_fmt = IPU_PIX_FMT_RGB666; + } + if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */ + sig_cfg.odd_field_first = true; + if (mxc_fbi->ipu_int_clk) + sig_cfg.int_clk = true; + if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) + sig_cfg.Hsync_pol = true; + if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) + sig_cfg.Vsync_pol = true; + if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL)) + sig_cfg.clk_pol = true; + if (fbi->var.sync & FB_SYNC_DATA_INVERT) + sig_cfg.data_pol = true; + if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT)) + sig_cfg.enable_pol = true; + if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) + sig_cfg.clkidle_en = true; + + dev_dbg(fbi->device, "pixclock = %ul Hz\n", + (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); + + if (ipu_init_sync_panel(mxc_fbi->ipu_di, + (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, + fbi->var.xres, fbi->var.yres, + out_pixel_fmt, + fbi->var.left_margin, + fbi->var.hsync_len, + fbi->var.right_margin, + fbi->var.upper_margin, + fbi->var.vsync_len, + fbi->var.lower_margin, + 0, sig_cfg) != 0) { + dev_err(fbi->device, + "mxcfb: Error initializing panel.\n"); + return -EINVAL; + } + + fbi->mode = + (struct fb_videomode *)fb_match_mode(&fbi->var, + &fbi->modelist); + + ipu_disp_set_window_pos(mxc_fbi->ipu_ch, 0, 0); + } + + retval = _setup_disp_channel2(fbi); + if (retval) + return retval; + + ipu_enable_channel(mxc_fbi->ipu_ch); + + return retval; +} + +static int _swap_channels(struct fb_info *fbi, + struct fb_info *fbi_to, bool both_on) +{ + int retval, tmp; + ipu_channel_t old_ch; + struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi->par; + struct mxcfb_info *mxc_fbi_to = (struct mxcfb_info *)fbi_to->par; + + if (both_on) { + ipu_disable_channel(mxc_fbi_to->ipu_ch, true); + ipu_uninit_channel(mxc_fbi_to->ipu_ch); + } + + /* switch the mxc fbi parameters */ + old_ch = mxc_fbi_from->ipu_ch; + mxc_fbi_from->ipu_ch = mxc_fbi_to->ipu_ch; + mxc_fbi_to->ipu_ch = old_ch; + tmp = mxc_fbi_from->ipu_ch_irq; + mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq; + mxc_fbi_to->ipu_ch_irq = tmp; + + _setup_disp_channel1(fbi); + retval = _setup_disp_channel2(fbi); + if (retval) + return retval; + + /* switch between dp and dc, disable old idmac, enable new idmac */ + retval = ipu_swap_channel(old_ch, mxc_fbi_from->ipu_ch); + ipu_uninit_channel(old_ch); + + if (both_on) { + _setup_disp_channel1(fbi_to); + retval = _setup_disp_channel2(fbi_to); + if (retval) + return retval; + ipu_enable_channel(mxc_fbi_to->ipu_ch); + } + + return retval; +} + +static int swap_channels(struct fb_info *fbi) +{ + int i; + int swap_mode; + ipu_channel_t ch_to; + struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi->par; + struct fb_info *fbi_to = NULL; + struct mxcfb_info *mxc_fbi_to; + + /* what's the target channel? */ + if (mxc_fbi_from->ipu_ch == MEM_BG_SYNC) + ch_to = MEM_DC_SYNC; + else + ch_to = MEM_BG_SYNC; + + for (i = 0; i < num_registered_fb; i++) { + mxc_fbi_to = + (struct mxcfb_info *)mxcfb_info[i]->par; + if (mxc_fbi_to->ipu_ch == ch_to) { + fbi_to = mxcfb_info[i]; + break; + } + } + if (fbi_to == NULL) + return -1; + + ipu_clear_irq(mxc_fbi_from->ipu_ch_irq); + ipu_clear_irq(mxc_fbi_to->ipu_ch_irq); + ipu_free_irq(mxc_fbi_from->ipu_ch_irq, fbi); + ipu_free_irq(mxc_fbi_to->ipu_ch_irq, fbi_to); + + if (mxc_fbi_from->cur_blank == FB_BLANK_UNBLANK) { + if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK) + swap_mode = BOTH_ON; + else + swap_mode = SRC_ON; + } else { + if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK) + swap_mode = TGT_ON; + else + swap_mode = BOTH_OFF; + } + + /* tvout di-1: for DC use UYVY, for DP use RGB */ + if (mxc_fbi_from->ipu_di == 1 && ch_to == MEM_DC_SYNC) { + fbi->var.bits_per_pixel = 16; + fbi->var.nonstd = IPU_PIX_FMT_UYVY; + } else if (mxc_fbi_from->ipu_di == 1 && ch_to == MEM_BG_SYNC) { + fbi->var.nonstd = 0; + } else if (mxc_fbi_from->ipu_di == 0 && ch_to == MEM_DC_SYNC) { + fbi_to->var.nonstd = 0; + } else if (mxc_fbi_from->ipu_di == 0 && ch_to == MEM_BG_SYNC) { + fbi->var.bits_per_pixel = 16; + fbi->var.nonstd = IPU_PIX_FMT_UYVY; + } + + switch (swap_mode) { + case BOTH_ON: + /* disable target->switch src->enable target */ + _swap_channels(fbi, fbi_to, true); + break; + case SRC_ON: + /* just switch src */ + _swap_channels(fbi, fbi_to, false); + break; + case TGT_ON: + /* just switch target */ + _swap_channels(fbi_to, fbi, false); + break; + case BOTH_OFF: + /* switch directly, no more need to do */ + mxc_fbi_to->ipu_ch = mxc_fbi_from->ipu_ch; + mxc_fbi_from->ipu_ch = ch_to; + i = mxc_fbi_from->ipu_ch_irq; + mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq; + mxc_fbi_to->ipu_ch_irq = i; + break; + default: + break; + } + + if (ipu_request_irq(mxc_fbi_from->ipu_ch_irq, mxcfb_irq_handler, 0, + MXCFB_NAME, fbi) != 0) { + dev_err(fbi->device, "Error registering irq %d\n", + mxc_fbi_from->ipu_ch_irq); + return -EBUSY; + } + ipu_disable_irq(mxc_fbi_from->ipu_ch_irq); + if (ipu_request_irq(mxc_fbi_to->ipu_ch_irq, mxcfb_irq_handler, 0, + MXCFB_NAME, fbi_to) != 0) { + dev_err(fbi_to->device, "Error registering irq %d\n", + mxc_fbi_to->ipu_ch_irq); + return -EBUSY; + } + ipu_disable_irq(mxc_fbi_to->ipu_ch_irq); + + return 0; +} + +/* + * Check framebuffer variable parameters and adjust to valid values. + * + * @param var framebuffer variable parameters + * + * @param info framebuffer information pointer + */ +static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + u32 vtotal; + u32 htotal; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par; + + /* fg should not bigger than bg */ + if (mxc_fbi->ipu_ch == MEM_FG_SYNC) { + struct fb_info *fbi_tmp; + struct mxcfb_info *mxc_fbi_tmp; + int i, bg_xres, bg_yres; + int16_t pos_x, pos_y; + + bg_xres = var->xres; + bg_yres = var->yres; + + for (i = 0; i < num_registered_fb; i++) { + fbi_tmp = registered_fb[i]; + mxc_fbi_tmp = (struct mxcfb_info *) + (fbi_tmp->par); + if (mxc_fbi_tmp->ipu_ch == MEM_BG_SYNC) { + bg_xres = fbi_tmp->var.xres; + bg_yres = fbi_tmp->var.yres; + break; + } + } + + ipu_disp_get_window_pos(mxc_fbi->ipu_ch, &pos_x, &pos_y); + + if ((var->xres + pos_x) > bg_xres) + var->xres = bg_xres - pos_x; + if ((var->yres + pos_y) > bg_yres) + var->yres = bg_yres - pos_y; + } + + if (var->xres_virtual < var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16) && (var->bits_per_pixel != 12) && + (var->bits_per_pixel != 8)) + var->bits_per_pixel = 16; + + switch (var->bits_per_pixel) { + case 8: + var->red.length = 3; + var->red.offset = 5; + var->red.msb_right = 0; + + var->green.length = 3; + var->green.offset = 2; + var->green.msb_right = 0; + + var->blue.length = 2; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + if (var->pixclock < 1000) { + htotal = var->xres + var->right_margin + var->hsync_len + + var->left_margin; + vtotal = var->yres + var->lower_margin + var->vsync_len + + var->upper_margin; + var->pixclock = (vtotal * htotal * 6UL) / 100UL; + var->pixclock = KHZ2PICOS(var->pixclock); + dev_dbg(info->device, + "pixclock set for 60Hz refresh = %u ps\n", + var->pixclock); + } + + var->height = -1; + var->width = -1; + var->grayscale = 0; + + return 0; +} + +static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int trans, struct fb_info *fbi) +{ + unsigned int val; + int ret = 1; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (fbi->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + switch (fbi->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = fbi->pseudo_palette; + + val = _chan_to_field(red, &fbi->var.red); + val |= _chan_to_field(green, &fbi->var.green); + val |= _chan_to_field(blue, &fbi->var.blue); + + pal[regno] = val; + ret = 0; + } + break; + + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + + return ret; +} + +/* + * Function to handle custom ioctls for MXC framebuffer. + * + * @param inode inode struct + * + * @param file file struct + * + * @param cmd Ioctl command to handle + * + * @param arg User pointer to command arguments + * + * @param fbi framebuffer information pointer + */ +static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg) +{ + int retval = 0; + int __user *argp = (void __user *)arg; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + switch (cmd) { + case MXCFB_SET_GBL_ALPHA: + { + struct mxcfb_gbl_alpha ga; + + if (copy_from_user(&ga, (void *)arg, sizeof(ga))) { + retval = -EFAULT; + break; + } + + if (ipu_disp_set_global_alpha(mxc_fbi->ipu_ch, + (bool)ga.enable, + ga.alpha)) { + retval = -EINVAL; + break; + } + + if (ga.enable) + mxc_fbi->alpha_chan_en = false; + + if (ga.enable) + dev_dbg(fbi->device, + "Set global alpha of %s to %d\n", + fbi->fix.id, ga.alpha); + break; + } + case MXCFB_SET_LOC_ALPHA: + { + struct mxcfb_loc_alpha la; + int i; + char *video_plane_idstr = ""; + + if (copy_from_user(&la, (void *)arg, sizeof(la))) { + retval = -EFAULT; + break; + } + + if (ipu_disp_set_global_alpha(mxc_fbi->ipu_ch, + !(bool)la.enable, 0)) { + retval = -EINVAL; + break; + } + + if (la.enable && !la.alpha_in_pixel) { + mxc_fbi->alpha_chan_en = true; + + if (mxc_fbi->ipu_ch == MEM_FG_SYNC) + video_plane_idstr = "DISP3 BG"; + else if (mxc_fbi->ipu_ch == MEM_BG_SYNC) + video_plane_idstr = "DISP3 FG"; + + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if (strcmp(idstr, video_plane_idstr) == 0) { + ((struct mxcfb_info *)(registered_fb[i]->par))->alpha_chan_en = false; + break; + } + } + } else + mxc_fbi->alpha_chan_en = false; + + mxcfb_set_par(fbi); + + la.alpha_phy_addr0 = mxc_fbi->alpha_phy_addr0; + la.alpha_phy_addr1 = mxc_fbi->alpha_phy_addr1; + if (copy_to_user((void *)arg, &la, sizeof(la))) { + retval = -EFAULT; + break; + } + + if (la.enable) + dev_dbg(fbi->device, + "Enable DP local alpha for %s\n", + fbi->fix.id); + break; + } + case MXCFB_SET_LOC_ALP_BUF: + { + unsigned long base; + uint32_t ipu_alp_ch_irq; + + if (!(((mxc_fbi->ipu_ch == MEM_FG_SYNC) || + (mxc_fbi->ipu_ch == MEM_BG_SYNC)) && + (mxc_fbi->alpha_chan_en))) { + dev_err(fbi->device, + "Should use background or overlay " + "framebuffer to set the alpha buffer " + "number\n"); + return -EINVAL; + } + + if (get_user(base, argp)) + return -EFAULT; + + if (base != mxc_fbi->alpha_phy_addr0 && + base != mxc_fbi->alpha_phy_addr1) { + dev_err(fbi->device, + "Wrong alpha buffer physical address " + "%lu\n", base); + return -EINVAL; + } + + if (mxc_fbi->ipu_ch == MEM_FG_SYNC) + ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF; + else + ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF; + + down(&mxc_fbi->alpha_flip_sem); + + mxc_fbi->cur_ipu_alpha_buf = + !mxc_fbi->cur_ipu_alpha_buf; + if (ipu_update_channel_buffer(mxc_fbi->ipu_ch, + IPU_ALPHA_IN_BUFFER, + mxc_fbi-> + cur_ipu_alpha_buf, + base) == 0) { + ipu_select_buffer(mxc_fbi->ipu_ch, + IPU_ALPHA_IN_BUFFER, + mxc_fbi->cur_ipu_alpha_buf); + ipu_clear_irq(ipu_alp_ch_irq); + ipu_enable_irq(ipu_alp_ch_irq); + } else { + dev_err(fbi->device, + "Error updating %s SDC alpha buf %d " + "to address=0x%08lX\n", + fbi->fix.id, + mxc_fbi->cur_ipu_alpha_buf, base); + } + break; + } + case MXCFB_SET_CLR_KEY: + { + struct mxcfb_color_key key; + if (copy_from_user(&key, (void *)arg, sizeof(key))) { + retval = -EFAULT; + break; + } + retval = ipu_disp_set_color_key(mxc_fbi->ipu_ch, + key.enable, + key.color_key); + dev_dbg(fbi->device, "Set color key to 0x%08X\n", + key.color_key); + break; + } + case MXCFB_SET_GAMMA: + { + struct mxcfb_gamma gamma; + if (copy_from_user(&gamma, (void *)arg, sizeof(gamma))) { + retval = -EFAULT; + break; + } + retval = ipu_disp_set_gamma_correction(mxc_fbi->ipu_ch, + gamma.enable, + gamma.constk, + gamma.slopek); + break; + } + case MXCFB_WAIT_FOR_VSYNC: + { + if (mxc_fbi->ipu_ch == MEM_FG_SYNC) { + struct mxcfb_info *bg_mxcfbi = NULL; + int i; + for (i = 0; i < num_registered_fb; i++) { + bg_mxcfbi = + ((struct mxcfb_info *)(registered_fb[i]->par)); + + if (bg_mxcfbi->ipu_ch == MEM_BG_SYNC) + break; + } + if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK) { + retval = -EINVAL; + break; + } + } + if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK) { + retval = -EINVAL; + break; + } + + init_completion(&mxc_fbi->vsync_complete); + + ipu_clear_irq(mxc_fbi->ipu_ch_irq); + mxc_fbi->wait4vsync = 1; + ipu_enable_irq(mxc_fbi->ipu_ch_irq); + retval = wait_for_completion_interruptible_timeout( + &mxc_fbi->vsync_complete, 1 * HZ); + if (retval == 0) { + dev_err(fbi->device, + "MXCFB_WAIT_FOR_VSYNC: timeout %d\n", + retval); + mxc_fbi->wait4vsync = 0; + retval = -ETIME; + } else if (retval > 0) { + retval = 0; + } + break; + } + case FBIO_ALLOC: + { + int size; + struct mxcfb_alloc_list *mem; + + mem = kzalloc(sizeof(*mem), GFP_KERNEL); + if (mem == NULL) + return -ENOMEM; + + if (get_user(size, argp)) + return -EFAULT; + + mem->size = PAGE_ALIGN(size); + + mem->cpu_addr = dma_alloc_coherent(fbi->device, size, + &mem->phy_addr, + GFP_DMA); + if (mem->cpu_addr == NULL) { + kfree(mem); + return -ENOMEM; + } + + list_add(&mem->list, &fb_alloc_list); + + dev_dbg(fbi->device, "allocated %d bytes @ 0x%08X\n", + mem->size, mem->phy_addr); + + if (put_user(mem->phy_addr, argp)) + return -EFAULT; + + break; + } + case FBIO_FREE: + { + unsigned long offset; + struct mxcfb_alloc_list *mem; + + if (get_user(offset, argp)) + return -EFAULT; + + retval = -EINVAL; + list_for_each_entry(mem, &fb_alloc_list, list) { + if (mem->phy_addr == offset) { + list_del(&mem->list); + dma_free_coherent(fbi->device, + mem->size, + mem->cpu_addr, + mem->phy_addr); + kfree(mem); + retval = 0; + break; + } + } + + break; + } + case MXCFB_SET_OVERLAY_POS: + { + struct mxcfb_pos pos; + struct fb_info *bg_fbi = NULL; + struct mxcfb_info *bg_mxcfbi = NULL; + int i; + + if (mxc_fbi->ipu_ch != MEM_FG_SYNC) { + dev_err(fbi->device, "Should use the overlay " + "framebuffer to set the position of " + "the overlay window\n"); + retval = -EINVAL; + break; + } + + if (copy_from_user(&pos, (void *)arg, sizeof(pos))) { + retval = -EFAULT; + break; + } + + for (i = 0; i < num_registered_fb; i++) { + bg_mxcfbi = + ((struct mxcfb_info *)(registered_fb[i]->par)); + + if (bg_mxcfbi->ipu_ch == MEM_BG_SYNC) { + bg_fbi = registered_fb[i]; + break; + } + } + + if (bg_fbi == NULL) { + dev_err(fbi->device, "Cannot find the " + "background framebuffer\n"); + retval = -ENOENT; + break; + } + + if (fbi->var.xres + pos.x > bg_fbi->var.xres) { + if (bg_fbi->var.xres < fbi->var.xres) + pos.x = 0; + else + pos.x = bg_fbi->var.xres - fbi->var.xres; + } + if (fbi->var.yres + pos.y > bg_fbi->var.yres) { + if (bg_fbi->var.yres < fbi->var.yres) + pos.y = 0; + else + pos.y = bg_fbi->var.yres - fbi->var.yres; + } + + retval = ipu_disp_set_window_pos(mxc_fbi->ipu_ch, + pos.x, pos.y); + + if (copy_to_user((void *)arg, &pos, sizeof(pos))) { + retval = -EFAULT; + break; + } + break; + } + case MXCFB_GET_FB_IPU_CHAN: + { + struct mxcfb_info *mxc_fbi = + (struct mxcfb_info *)fbi->par; + + if (put_user(mxc_fbi->ipu_ch, argp)) + return -EFAULT; + break; + } + case MXCFB_GET_DIFMT: + { + struct mxcfb_info *mxc_fbi = + (struct mxcfb_info *)fbi->par; + + if (put_user(mxc_fbi->ipu_di_pix_fmt, argp)) + return -EFAULT; + break; + } + case MXCFB_GET_FB_IPU_DI: + { + struct mxcfb_info *mxc_fbi = + (struct mxcfb_info *)fbi->par; + + if (put_user(mxc_fbi->ipu_di, argp)) + return -EFAULT; + break; + } + case MXCFB_GET_FB_BLANK: + { + struct mxcfb_info *mxc_fbi = + (struct mxcfb_info *)fbi->par; + + if (put_user(mxc_fbi->cur_blank, argp)) + return -EFAULT; + break; + } + case MXCFB_SET_DIFMT: + { + struct mxcfb_info *mxc_fbi = + (struct mxcfb_info *)fbi->par; + + if (get_user(mxc_fbi->ipu_di_pix_fmt, argp)) + return -EFAULT; + + break; + } + default: + retval = -EINVAL; + } + return retval; +} + +/* + * mxcfb_blank(): + * Blank the display. + */ +static int mxcfb_blank(int blank, struct fb_info *info) +{ + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par; + + dev_dbg(info->device, "blank = %d\n", blank); + + if (mxc_fbi->cur_blank == blank) + return 0; + + mxc_fbi->next_blank = blank; + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + ipu_disable_channel(mxc_fbi->ipu_ch, true); + ipu_uninit_channel(mxc_fbi->ipu_ch); + break; + case FB_BLANK_UNBLANK: + mxcfb_set_par(info); + break; + } + mxc_fbi->cur_blank = blank; + return 0; +} + +/* + * Pan or Wrap the Display + * + * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag + * + * @param var Variable screen buffer information + * @param info Framebuffer information pointer + */ +static int +mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par, + *mxc_graphic_fbi = NULL; + u_int y_bottom; + unsigned long base, active_alpha_phy_addr = 0; + bool loc_alpha_en = false; + int i = 0; + + if (info->var.yoffset == var->yoffset) + return 0; /* No change, do nothing */ + + /* no pan display during fb blank */ + if (mxc_fbi->ipu_ch == MEM_FG_SYNC) { + struct mxcfb_info *bg_mxcfbi = NULL; + int j; + for (j = 0; j < num_registered_fb; j++) { + bg_mxcfbi = + ((struct mxcfb_info *)(registered_fb[j]->par)); + + if (bg_mxcfbi->ipu_ch == MEM_BG_SYNC) + break; + } + if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK) + return -EINVAL; + } + if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK) + return -EINVAL; + + y_bottom = var->yoffset; + + if (!(var->vmode & FB_VMODE_YWRAP)) + y_bottom += var->yres; + + if (y_bottom > info->var.yres_virtual) + return -EINVAL; + + base = (var->yoffset * var->xres_virtual + var->xoffset); + base = (var->bits_per_pixel) * base / 8; + base += info->fix.smem_start; + + /* Check if DP local alpha is enabled and find the graphic fb */ + if (mxc_fbi->ipu_ch == MEM_BG_SYNC || mxc_fbi->ipu_ch == MEM_FG_SYNC) { + for (i = 0; i < num_registered_fb; i++) { + char *idstr = registered_fb[i]->fix.id; + if ((strcmp(idstr, "DISP3 BG") == 0 || + strcmp(idstr, "DISP3 FG") == 0) && + ((struct mxcfb_info *) + (registered_fb[i]->par))->alpha_chan_en) { + loc_alpha_en = true; + mxc_graphic_fbi = (struct mxcfb_info *) + (registered_fb[i]->par); + active_alpha_phy_addr = mxc_fbi->cur_ipu_buf ? + mxc_graphic_fbi->alpha_phy_addr1 : + mxc_graphic_fbi->alpha_phy_addr0; + dev_dbg(info->device, "Updating SDC graphic " + "buf %d address=0x%08lX\n", + mxc_fbi->cur_ipu_buf, + active_alpha_phy_addr); + break; + } + } + } + + down(&mxc_fbi->flip_sem); + + mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf; + + dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n", + info->fix.id, mxc_fbi->cur_ipu_buf, base); + + if (ipu_update_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf, base) == 0) { + /* Update the DP local alpha buffer only for graphic plane */ + if (loc_alpha_en && mxc_graphic_fbi == mxc_fbi && + ipu_update_channel_buffer(mxc_graphic_fbi->ipu_ch, + IPU_ALPHA_IN_BUFFER, + mxc_fbi->cur_ipu_buf, + active_alpha_phy_addr) == 0) { + ipu_select_buffer(mxc_graphic_fbi->ipu_ch, + IPU_ALPHA_IN_BUFFER, + mxc_fbi->cur_ipu_buf); + } + + ipu_select_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf); + ipu_clear_irq(mxc_fbi->ipu_ch_irq); + ipu_enable_irq(mxc_fbi->ipu_ch_irq); + } else { + dev_err(info->device, + "Error updating SDC buf %d to address=0x%08lX\n", + mxc_fbi->cur_ipu_buf, base); + mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf; + ipu_clear_irq(mxc_fbi->ipu_ch_irq); + ipu_enable_irq(mxc_fbi->ipu_ch_irq); + return -EBUSY; + } + + dev_dbg(info->device, "Update complete\n"); + + info->var.yoffset = var->yoffset; + + return 0; +} + +/* + * Function to handle custom mmap for MXC framebuffer. + * + * @param fbi framebuffer information pointer + * + * @param vma Pointer to vm_area_struct + */ +static int mxcfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma) +{ + bool found = false; + u32 len; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + struct mxcfb_alloc_list *mem; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + if (offset < fbi->fix.smem_len) { + /* mapping framebuffer memory */ + len = fbi->fix.smem_len - offset; + vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT; + } else if ((vma->vm_pgoff == + (mxc_fbi->alpha_phy_addr0 >> PAGE_SHIFT)) || + (vma->vm_pgoff == + (mxc_fbi->alpha_phy_addr1 >> PAGE_SHIFT))) { + len = mxc_fbi->alpha_mem_len; + } else { + list_for_each_entry(mem, &fb_alloc_list, list) { + if (offset == mem->phy_addr) { + found = true; + len = mem->size; + break; + } + } + if (!found) + return -EINVAL; + } + + len = PAGE_ALIGN(len); + if (vma->vm_end - vma->vm_start > len) + return -EINVAL; + + /* make buffers bufferable */ + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + vma->vm_flags |= VM_IO | VM_RESERVED; + + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) { + dev_dbg(fbi->device, "mmap remap_pfn_range failed\n"); + return -ENOBUFS; + } + + return 0; +} + +/*! + * This structure contains the pointers to the control functions that are + * invoked by the core framebuffer driver to perform operations like + * blitting, rectangle filling, copy regions and cursor definition. + */ +static struct fb_ops mxcfb_ops = { + .owner = THIS_MODULE, + .fb_set_par = mxcfb_set_par, + .fb_check_var = mxcfb_check_var, + .fb_setcolreg = mxcfb_setcolreg, + .fb_pan_display = mxcfb_pan_display, + .fb_ioctl = mxcfb_ioctl, + .fb_mmap = mxcfb_mmap, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_blank = mxcfb_blank, +}; + +static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id) +{ + struct fb_info *fbi = dev_id; + struct mxcfb_info *mxc_fbi = fbi->par; + + if (mxc_fbi->wait4vsync) { + complete(&mxc_fbi->vsync_complete); + ipu_disable_irq(irq); + mxc_fbi->wait4vsync = 0; + } else { + if (!ipu_check_buffer_ready(mxc_fbi->ipu_ch, + IPU_INPUT_BUFFER, mxc_fbi->cur_ipu_buf) + || (mxc_fbi->waitcnt > 1)) { + /* + * This code wait for EOF irq to make sure current + * buffer showed. + * + * Buffer ready will be clear after this buffer + * begin to show. If it keep 1, it represents this + * irq come from previous buffer. If so, wait for + * EOF irq again. + * + * Normally, waitcnt will not > 1, if so, something + * is wrong, then clear it manually. + */ + if (mxc_fbi->waitcnt > 1) + ipu_clear_buffer_ready(mxc_fbi->ipu_ch, + IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf); + up(&mxc_fbi->flip_sem); + ipu_disable_irq(irq); + mxc_fbi->waitcnt = 0; + } else + mxc_fbi->waitcnt++; + } + return IRQ_HANDLED; +} + +static irqreturn_t mxcfb_alpha_irq_handler(int irq, void *dev_id) +{ + struct fb_info *fbi = dev_id; + struct mxcfb_info *mxc_fbi = fbi->par; + + up(&mxc_fbi->alpha_flip_sem); + ipu_disable_irq(irq); + return IRQ_HANDLED; +} + +/* + * Suspends the framebuffer and blanks the screen. Power management support + */ +static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct fb_info *fbi = platform_get_drvdata(pdev); + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + int saved_blank; +#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY + void *fbmem; +#endif + + acquire_console_sem(); + fb_set_suspend(fbi, 1); + saved_blank = mxc_fbi->cur_blank; + mxcfb_blank(FB_BLANK_POWERDOWN, fbi); + mxc_fbi->next_blank = saved_blank; + release_console_sem(); + + return 0; +} + +/* + * Resumes the framebuffer and unblanks the screen. Power management support + */ +static int mxcfb_resume(struct platform_device *pdev) +{ + struct fb_info *fbi = platform_get_drvdata(pdev); + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + acquire_console_sem(); + mxcfb_blank(mxc_fbi->next_blank, fbi); + fb_set_suspend(fbi, 0); + release_console_sem(); + + return 0; +} + +/* + * Main framebuffer functions + */ + +/*! + * Allocates the DRAM memory for the frame buffer. This buffer is remapped + * into a non-cached, non-buffered, memory region to allow palette and pixel + * writes to occur without flushing the cache. Once this area is remapped, + * all virtual memory access to the video memory should occur at the new region. + * + * @param fbi framebuffer information pointer + * + * @return Error code indicating success or failure + */ +static int mxcfb_map_video_memory(struct fb_info *fbi) +{ + if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) + fbi->fix.smem_len = fbi->var.yres_virtual * + fbi->fix.line_length; + + fbi->screen_base = dma_alloc_writecombine(fbi->device, + fbi->fix.smem_len, + (dma_addr_t *)&fbi->fix.smem_start, + GFP_DMA); + if (fbi->screen_base == 0) { + dev_err(fbi->device, "Unable to allocate framebuffer memory\n"); + fbi->fix.smem_len = 0; + fbi->fix.smem_start = 0; + return -EBUSY; + } + + dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n", + (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len); + + fbi->screen_size = fbi->fix.smem_len; + + /* Clear the screen */ + memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); + + return 0; +} + +/*! + * De-allocates the DRAM memory for the frame buffer. + * + * @param fbi framebuffer information pointer + * + * @return Error code indicating success or failure + */ +static int mxcfb_unmap_video_memory(struct fb_info *fbi) +{ + dma_free_writecombine(fbi->device, fbi->fix.smem_len, + fbi->screen_base, fbi->fix.smem_start); + fbi->screen_base = 0; + fbi->fix.smem_start = 0; + fbi->fix.smem_len = 0; + return 0; +} + +/*! + * Initializes the framebuffer information pointer. After allocating + * sufficient memory for the framebuffer structure, the fields are + * filled with custom information passed in from the configurable + * structures. This includes information such as bits per pixel, + * color maps, screen width/height and RGBA offsets. + * + * @return Framebuffer structure initialized with our information + */ +static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops) +{ + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + + /* + * Allocate sufficient memory for the fb structure + */ + fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev); + if (!fbi) + return NULL; + + mxcfbi = (struct mxcfb_info *)fbi->par; + + fbi->var.activate = FB_ACTIVATE_NOW; + + fbi->fbops = ops; + fbi->flags = FBINFO_FLAG_DEFAULT; + fbi->pseudo_palette = mxcfbi->pseudo_palette; + + /* + * Allocate colormap + */ + fb_alloc_cmap(&fbi->cmap, 16, 0); + + return fbi; +} + +static ssize_t show_disp_chan(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fb_info *info = dev_get_drvdata(dev); + struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par; + + if (mxcfbi->ipu_ch == MEM_BG_SYNC) + return sprintf(buf, "2-layer-fb-bg\n"); + else if (mxcfbi->ipu_ch == MEM_FG_SYNC) + return sprintf(buf, "2-layer-fb-fg\n"); + else if (mxcfbi->ipu_ch == MEM_DC_SYNC) + return sprintf(buf, "1-layer-fb\n"); + else + return sprintf(buf, "err: no display chan\n"); +} + +static ssize_t swap_disp_chan(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fb_info *info = dev_get_drvdata(dev); + struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par; + struct mxcfb_info *fg_mxcfbi = NULL; + + acquire_console_sem(); + /* swap only happen between DP-BG and DC, while DP-FG disable */ + if (((mxcfbi->ipu_ch == MEM_BG_SYNC) && + (strstr(buf, "1-layer-fb") != NULL)) || + ((mxcfbi->ipu_ch == MEM_DC_SYNC) && + (strstr(buf, "2-layer-fb-bg") != NULL))) { + int i; + + for (i = 0; i < num_registered_fb; i++) { + fg_mxcfbi = + (struct mxcfb_info *)mxcfb_info[i]->par; + if (fg_mxcfbi->ipu_ch == MEM_FG_SYNC) + break; + else + fg_mxcfbi = NULL; + } + if (!fg_mxcfbi || + fg_mxcfbi->cur_blank == FB_BLANK_UNBLANK) { + dev_err(dev, + "Can not switch while fb2(fb-fg) is on.\n"); + release_console_sem(); + return count; + } + + if (swap_channels(info) < 0) + dev_err(dev, "Swap display channel failed.\n"); + } + + release_console_sem(); + return count; +} +DEVICE_ATTR(fsl_disp_property, 644, show_disp_chan, swap_disp_chan); + +static int mxcfb_setup(struct fb_info *fbi, struct platform_device *pdev) +{ + struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par; + struct mxc_fb_platform_data *plat_data = pdev->dev.platform_data; + int ret = 0; + + /* Need dummy values until real panel is configured */ + fbi->var.xres = 240; + fbi->var.yres = 320; + + if (!mxcfbi->default_bpp) + mxcfbi->default_bpp = 16; + + if (plat_data && !mxcfbi->ipu_di_pix_fmt) + mxcfbi->ipu_di_pix_fmt = plat_data->interface_pix_fmt; + + if (!mxcfbi->fb_mode_str && plat_data && plat_data->mode_str) + mxcfbi->fb_mode_str = plat_data->mode_str; + + if (mxcfbi->fb_mode_str) { + if (mxcfbi->ipu_di >= 0) { + const struct fb_videomode *mode; + struct fb_videomode m; + int num, found = 0; + + dev_dbg(fbi->device, "Config display port %d\n", + mxcfbi->ipu_di); + + INIT_LIST_HEAD(&fbi->modelist); + + if (mxc_disp_mode[mxcfbi->ipu_di].num_modes) { + mode = mxc_disp_mode[mxcfbi->ipu_di].mode; + num = mxc_disp_mode[mxcfbi->ipu_di].num_modes; + fb_videomode_to_modelist(mode, num, &fbi->modelist); + } + + if ((mxc_disp_mode[mxcfbi->ipu_di].dev_mode + & MXC_DISP_DDC_DEV) && + !list_empty(&fbi->modelist)) { + dev_dbg(fbi->device, + "Look for video mode %s in ddc modelist\n", + mxcfbi->fb_mode_str); + /* + * For DDC mode, try to get compatible mode first. + * If get one, try to find nearest mode, otherwise, + * use first mode provide by DDC. + */ + ret = fb_find_mode(&fbi->var, fbi, + mxcfbi->fb_mode_str, NULL, 0, + NULL, mxcfbi->default_bpp); + if (ret) { + fb_var_to_videomode(&m, &fbi->var); + mode = fb_find_nearest_mode(&m, + &fbi->modelist); + fb_videomode_to_var(&fbi->var, mode); + } else { + struct list_head *pos, *head; + struct fb_modelist *modelist; + + head = &fbi->modelist; + list_for_each(pos, head) { + modelist = list_entry(pos, + struct fb_modelist, list); + m = modelist->mode; + if (m.flag & FB_MODE_IS_FIRST) + break; + } + /* if no first mode, use last one */ + mode = &m; + fb_videomode_to_var(&fbi->var, mode); + } + found = 1; + } else if (!list_empty(&fbi->modelist)) { + dev_dbg(fbi->device, + "Look for video mode %s in spec modelist\n", + mxcfbi->fb_mode_str); + /* + * For specific mode, try to get specified mode + * from fbi modelist. + */ + ret = fb_find_mode(&fbi->var, fbi, + mxcfbi->fb_mode_str, mode, num, + NULL, mxcfbi->default_bpp); + if (ret == 1) + found = 1; + + } + /* + * if no DDC mode and spec mode found, + * try plat_data mode. + */ + if (!found) { + dev_dbg(fbi->device, + "Look for video mode %s in plat modelist\n", + mxcfbi->fb_mode_str); + if (plat_data && plat_data->mode + && plat_data->num_modes) + ret = fb_find_mode(&fbi->var, fbi, + mxcfbi->fb_mode_str, + plat_data->mode, + plat_data->num_modes, + NULL, + mxcfbi->default_bpp); + else + ret = fb_find_mode(&fbi->var, fbi, + mxcfbi->fb_mode_str, NULL, 0, + NULL, mxcfbi->default_bpp); + if (ret) + found = 1; + } + + if (!found) { + dev_err(fbi->device, + "Not found any valid video mode"); + ret = -EINVAL; + goto done; + } + + /*added found mode to fbi modelist*/ + fb_var_to_videomode(&m, &fbi->var); + fb_add_videomode(&m, &fbi->modelist); + } + } + + mxcfb_check_var(&fbi->var, fbi); + + /* Default Y virtual size is 3x panel size */ + fbi->var.yres_virtual = fbi->var.yres * 3; + + mxcfb_set_fix(fbi); + + /* setup display */ + if (mxcfbi->ipu_di >= 0) + if (mxcfb_pre_setup[mxcfbi->ipu_di]) + (mxcfb_pre_setup[mxcfbi->ipu_di])(fbi); + + fbi->var.activate |= FB_ACTIVATE_FORCE; + acquire_console_sem(); + fbi->flags |= FBINFO_MISC_USEREVENT; + ret = fb_set_var(fbi, &fbi->var); + fbi->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); +done: + return ret; +} + +/*! + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxcfb_probe(struct platform_device *pdev) +{ + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + struct resource *res; + char *options; + char name[] = "mxcdi0fb"; + int ret = 0; + + /* + * Initialize FB structures + */ + fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops); + if (!fbi) { + ret = -ENOMEM; + goto err0; + } + mxcfbi = (struct mxcfb_info *)fbi->par; + + name[5] += pdev->id; + if (fb_get_options(name, &options)) { + ret = -ENODEV; + goto err1; + } + + if (options) + mxcfb_option_setup(fbi, options); + + if (!g_dp_in_use) { + mxcfbi->ipu_ch_irq = IPU_IRQ_BG_SYNC_EOF; + mxcfbi->ipu_ch = MEM_BG_SYNC; + mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK; + } else { + mxcfbi->ipu_ch_irq = IPU_IRQ_DC_SYNC_EOF; + mxcfbi->ipu_ch = MEM_DC_SYNC; + mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN; + } + + mxcfbi->ipu_di = pdev->id; + mxcfbi->ipu_alp_ch_irq = -1; + + if (pdev->id == 0) { + ipu_disp_set_global_alpha(mxcfbi->ipu_ch, true, 0x80); + ipu_disp_set_color_key(mxcfbi->ipu_ch, false, 0); + strcpy(fbi->fix.id, "DISP3 BG"); + + if (!g_dp_in_use) + mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF; + g_dp_in_use = true; + } else if (pdev->id == 1) { + strcpy(fbi->fix.id, "DISP3 BG - DI1"); + + if (!g_dp_in_use) + mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF; + g_dp_in_use = true; + } else if (pdev->id == 2) { /* Overlay */ + mxcfbi->ipu_ch_irq = IPU_IRQ_FG_SYNC_EOF; + mxcfbi->ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF; + mxcfbi->ipu_ch = MEM_FG_SYNC; + mxcfbi->ipu_di = -1; + mxcfbi->overlay = true; + mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN; + + strcpy(fbi->fix.id, "DISP3 FG"); + } + + mxcfb_info[pdev->id] = fbi; + + if (ipu_request_irq(mxcfbi->ipu_ch_irq, mxcfb_irq_handler, 0, + MXCFB_NAME, fbi) != 0) { + dev_err(&pdev->dev, "Error registering BG irq handler.\n"); + ret = -EBUSY; + goto err1; + } + ipu_disable_irq(mxcfbi->ipu_ch_irq); + + if (mxcfbi->ipu_alp_ch_irq != -1) + if (ipu_request_irq(mxcfbi->ipu_alp_ch_irq, + mxcfb_alpha_irq_handler, 0, + MXCFB_NAME, fbi) != 0) { + dev_err(&pdev->dev, "Error registering alpha irq " + "handler.\n"); + ret = -EBUSY; + goto err2; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res && res->end) { + fbi->fix.smem_len = res->end - res->start + 1; + fbi->fix.smem_start = res->start; + fbi->screen_base = ioremap(fbi->fix.smem_start, fbi->fix.smem_len); + } + + ret = mxcfb_setup(fbi, pdev); + if (ret < 0) + goto err3; + + ret = register_framebuffer(fbi); + if (ret < 0) + goto err3; + + platform_set_drvdata(pdev, fbi); + + ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_property); + if (ret) + dev_err(&pdev->dev, "Error %d on creating file\n", ret); + +#ifdef CONFIG_LOGO + fb_prepare_logo(fbi,0); + fb_show_logo(fbi, 0); +#endif + + return 0; +err3: + if (mxcfbi->ipu_alp_ch_irq != -1) + ipu_free_irq(mxcfbi->ipu_alp_ch_irq, fbi); +err2: + ipu_free_irq(mxcfbi->ipu_ch_irq, fbi); +err1: + fb_dealloc_cmap(&fbi->cmap); + framebuffer_release(fbi); +err0: + return ret; +} + +static int mxcfb_remove(struct platform_device *pdev) +{ + struct fb_info *fbi = platform_get_drvdata(pdev); + struct mxcfb_info *mxc_fbi = fbi->par; + + if (!fbi) + return 0; + + mxcfb_blank(FB_BLANK_POWERDOWN, fbi); + ipu_free_irq(mxc_fbi->ipu_ch_irq, fbi); + mxcfb_unmap_video_memory(fbi); + + if (&fbi->cmap) + fb_dealloc_cmap(&fbi->cmap); + + unregister_framebuffer(fbi); + framebuffer_release(fbi); + return 0; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcfb_driver = { + .driver = { + .name = MXCFB_NAME, + }, + .probe = mxcfb_probe, + .remove = mxcfb_remove, + .suspend = mxcfb_suspend, + .resume = mxcfb_resume, +}; + +/* + * Parse user specified options (`video=trident:') + * example: + * video=mxcdi0fb:RGB24, 1024x768M-16@60,bpp=16,noaccel + */ +static int mxcfb_option_setup(struct fb_info *info, char *options) +{ + struct mxcfb_info *mxcfbi = info->par; + char *opt; + + if (!options || !*options) + return 0; + + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + + if (!strncmp(opt, "RGB24", 5)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB24; + continue; + } + if (!strncmp(opt, "BGR24", 5)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_BGR24; + continue; + } + if (!strncmp(opt, "GBR24", 5)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_GBR24; + continue; + } + if (!strncmp(opt, "RGB565", 6)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB565; + continue; + } + if (!strncmp(opt, "RGB666", 6)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_RGB666; + continue; + } + if (!strncmp(opt, "YUV444", 6)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YUV444; + continue; + } + if (!strncmp(opt, "LVDS666", 7)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_LVDS666; + continue; + } + if (!strncmp(opt, "YUYV16", 6)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YUYV; + continue; + } + if (!strncmp(opt, "UYVY16", 6)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_UYVY; + continue; + } + if (!strncmp(opt, "YVYU16", 6)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_YVYU; + continue; + } + if (!strncmp(opt, "VYUY16", 6)) { + mxcfbi->ipu_di_pix_fmt = IPU_PIX_FMT_VYUY; + continue; + } + if (!strncmp(opt, "int_clk", 7)) { + mxcfbi->ipu_int_clk = true; + continue; + } + if (!strncmp(opt, "bpp=", 4)) + mxcfbi->default_bpp = + simple_strtoul(opt + 4, NULL, 0); + else + mxcfbi->fb_mode_str = opt; + } + + return 0; +} + +/*! + * Main entry function for the framebuffer. The function registers the power + * management callback functions with the kernel and also registers the MXCFB + * callback functions with the core Linux framebuffer driver \b fbmem.c + * + * @return Error code indicating success or failure + */ +int __init mxcfb_init(void) +{ + return platform_driver_register(&mxcfb_driver); +} + +void mxcfb_exit(void) +{ + platform_driver_unregister(&mxcfb_driver); +} + +module_init(mxcfb_init); +module_exit(mxcfb_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC framebuffer driver"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("fb"); diff --git a/drivers/video/mxc/mxcfb.c b/drivers/video/mxc/mxcfb.c new file mode 100644 index 000000000000..93ce7f664976 --- /dev/null +++ b/drivers/video/mxc/mxcfb.c @@ -0,0 +1,1372 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxcfb.c + * + * @brief MXC Frame buffer driver for SDC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Driver name + */ +#define MXCFB_NAME "mxc_sdc_fb" +/*! + * Structure containing the MXC specific framebuffer information. + */ +struct mxcfb_info { + int blank; + ipu_channel_t ipu_ch; + uint32_t ipu_ch_irq; + uint32_t cur_ipu_buf; + + u32 pseudo_palette[16]; + + struct semaphore flip_sem; + spinlock_t fb_lock; +}; + +struct mxcfb_data { + struct fb_info *fbi; + struct fb_info *fbi_ovl; + volatile int32_t vsync_flag; + wait_queue_head_t vsync_wq; + wait_queue_head_t suspend_wq; + bool suspended; + int backlight_level; +}; + +struct mxcfb_alloc_list { + struct list_head list; + dma_addr_t phy_addr; + void *cpu_addr; + u32 size; +}; + +static struct mxcfb_data mxcfb_drv_data; + +static char *fb_mode; +static unsigned long default_bpp = 16; +#ifdef CONFIG_FB_MXC_INTERNAL_MEM +static struct clk *iram_clk; +#endif +LIST_HEAD(fb_alloc_list); + +static uint32_t bpp_to_pixfmt(int bpp) +{ + uint32_t pixfmt = 0; + switch (bpp) { + case 24: + pixfmt = IPU_PIX_FMT_BGR24; + break; + case 32: + pixfmt = IPU_PIX_FMT_BGR32; + break; + case 16: + pixfmt = IPU_PIX_FMT_RGB565; + break; + } + return pixfmt; +} + +extern void gpio_lcd_active(void); +extern void gpio_lcd_inactive(void); +static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id); +static int mxcfb_blank(int blank, struct fb_info *info); +static int mxcfb_map_video_memory(struct fb_info *fbi, bool use_internal_ram); +static int mxcfb_unmap_video_memory(struct fb_info *fbi); + +/* + * Set fixed framebuffer parameters based on variable settings. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par; + + if (mxc_fbi->ipu_ch == MEM_SDC_FG) + strncpy(fix->id, "DISP3 FG", 8); + else + strncpy(fix->id, "DISP3 BG", 8); + + fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; + + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 1; + fix->ypanstep = 1; + + return 0; +} + +/* + * Set framebuffer parameters and change the operating mode. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_par(struct fb_info *fbi) +{ + int retval; + bool use_iram = false; + u32 mem_len; + ipu_di_signal_cfg_t sig_cfg; + ipu_panel_t mode = IPU_PANEL_TFT; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + ipu_disable_irq(mxc_fbi->ipu_ch_irq); + ipu_disable_channel(mxc_fbi->ipu_ch, true); + ipu_uninit_channel(mxc_fbi->ipu_ch); + ipu_clear_irq(mxc_fbi->ipu_ch_irq); + mxcfb_set_fix(fbi); + + mem_len = fbi->var.yres_virtual * fbi->fix.line_length; + if (mem_len > fbi->fix.smem_len) { + if (fbi->fix.smem_start) + mxcfb_unmap_video_memory(fbi); + +#ifdef CONFIG_FB_MXC_INTERNAL_MEM + if (mxc_fbi->ipu_ch == MEM_SDC_BG) { + use_iram = true; + } +#endif + if (mxcfb_map_video_memory(fbi, use_iram) < 0) + return -ENOMEM; + } + + ipu_init_channel(mxc_fbi->ipu_ch, NULL); + + /* Clear the screen */ + memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); + + if (mxc_fbi->ipu_ch == MEM_SDC_BG) { + memset(&sig_cfg, 0, sizeof(sig_cfg)); + if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) + sig_cfg.Hsync_pol = true; + if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) + sig_cfg.Vsync_pol = true; + if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL)) + sig_cfg.clk_pol = true; + if (fbi->var.sync & FB_SYNC_DATA_INVERT) + sig_cfg.data_pol = true; + if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT)) + sig_cfg.enable_pol = true; + if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) + sig_cfg.clkidle_en = true; + if (fbi->var.sync & FB_SYNC_SHARP_MODE) + mode = IPU_PANEL_SHARP_TFT; + + dev_dbg(fbi->device, "pixclock = %ul Hz\n", + (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); + + if (ipu_sdc_init_panel(mode, + (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, + fbi->var.xres, fbi->var.yres, + (fbi->var.sync & FB_SYNC_SWAP_RGB) ? + IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666, + fbi->var.left_margin, + fbi->var.hsync_len, + fbi->var.right_margin, + fbi->var.upper_margin, + fbi->var.vsync_len, + fbi->var.lower_margin, sig_cfg) != 0) { + dev_err(fbi->device, + "mxcfb: Error initializing panel.\n"); + return -EINVAL; + } + + fbi->mode = + (struct fb_videomode *)fb_match_mode(&fbi->var, + &fbi->modelist); + } + + ipu_disp_set_window_pos(mxc_fbi->ipu_ch, 0, 0); + + mxc_fbi->cur_ipu_buf = 1; + sema_init(&mxc_fbi->flip_sem, 1); + fbi->var.xoffset = fbi->var.yoffset = 0; + + retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi->var.bits_per_pixel), + fbi->var.xres, fbi->var.yres, + fbi->var.xres_virtual, + IPU_ROTATE_NONE, + fbi->fix.smem_start + + (fbi->fix.line_length * fbi->var.yres), + fbi->fix.smem_start, + 0, 0); + if (retval) { + dev_err(fbi->device, + "ipu_init_channel_buffer error %d\n", retval); + return retval; + } + + if (mxc_fbi->blank == FB_BLANK_UNBLANK) { + ipu_enable_channel(mxc_fbi->ipu_ch); + } + + return 0; +} + +/* + * Check framebuffer variable parameters and adjust to valid values. + * + * @param var framebuffer variable parameters + * + * @param info framebuffer information pointer + */ +static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + u32 vtotal; + u32 htotal; + + if (var->xres_virtual < var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + +#ifdef CONFIG_FB_MXC_INTERNAL_MEM + if ((info->fix.smem_start == FB_RAM_BASE_ADDR) && + ((var->yres_virtual * var->xres_virtual * var->bits_per_pixel / 8) > + FB_RAM_SIZE)) { + return -EINVAL; + } +#endif + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16)) { + var->bits_per_pixel = default_bpp; + } + + switch (var->bits_per_pixel) { + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + if (var->pixclock < 1000) { + htotal = var->xres + var->right_margin + var->hsync_len + + var->left_margin; + vtotal = var->yres + var->lower_margin + var->vsync_len + + var->upper_margin; + var->pixclock = (vtotal * htotal * 6UL) / 100UL; + var->pixclock = KHZ2PICOS(var->pixclock); + dev_dbg(info->device, + "pixclock set for 60Hz refresh = %u ps\n", + var->pixclock); + } + + var->height = -1; + var->width = -1; + var->grayscale = 0; + + /* nonstd used for YUV formats, but only RGB supported */ + var->nonstd = 0; + + return 0; +} + +static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} +static int +mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int trans, struct fb_info *fbi) +{ + unsigned int val; + int ret = 1; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (fbi->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + switch (fbi->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = fbi->pseudo_palette; + + val = _chan_to_field(red, &fbi->var.red); + val |= _chan_to_field(green, &fbi->var.green); + val |= _chan_to_field(blue, &fbi->var.blue); + + pal[regno] = val; + ret = 0; + } + break; + + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + + return ret; +} + +/* + * Function to handle custom ioctls for MXC framebuffer. + * + * @param inode inode struct + * + * @param file file struct + * + * @param cmd Ioctl command to handle + * + * @param arg User pointer to command arguments + * + * @param fbi framebuffer information pointer + */ +static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg) +{ + int retval = 0; + int __user *argp = (void __user *)arg; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == + false)); + if (retval < 0) + return retval; + + switch (cmd) { + case MXCFB_SET_GBL_ALPHA: + { + struct mxcfb_gbl_alpha ga; + if (copy_from_user(&ga, (void *)arg, sizeof(ga))) { + retval = -EFAULT; + break; + } + retval = + ipu_sdc_set_global_alpha((bool) ga.enable, + ga.alpha); + dev_dbg(fbi->device, "Set global alpha to %d\n", + ga.alpha); + break; + } + case MXCFB_SET_CLR_KEY: + { + struct mxcfb_color_key key; + if (copy_from_user(&key, (void *)arg, sizeof(key))) { + retval = -EFAULT; + break; + } + retval = ipu_sdc_set_color_key(MEM_SDC_BG, key.enable, + key.color_key); + dev_dbg(fbi->device, "Set color key to 0x%08X\n", + key.color_key); + break; + } + case MXCFB_WAIT_FOR_VSYNC: + { +#ifndef CONFIG_ARCH_MX3 + mxcfb_drv_data.vsync_flag = 0; + ipu_enable_irq(IPU_IRQ_SDC_DISP3_VSYNC); + if (!wait_event_interruptible_timeout + (mxcfb_drv_data.vsync_wq, + mxcfb_drv_data.vsync_flag != 0, 1 * HZ)) { + dev_err(fbi->device, + "MXCFB_WAIT_FOR_VSYNC: timeout\n"); + retval = -ETIME; + break; + } else if (signal_pending(current)) { + dev_err(fbi->device, + "MXCFB_WAIT_FOR_VSYNC: interrupt received\n"); + retval = -ERESTARTSYS; + break; + } +#endif + break; + } + case MXCFB_GET_FB_IPU_CHAN: + { + struct mxcfb_info *mxc_fbi = + (struct mxcfb_info *)fbi->par; + + if (put_user(mxc_fbi->ipu_ch, argp)) + return -EFAULT; + + break; + } + default: + retval = -EINVAL; + } + return retval; +} + +/* + * Function to handle custom ioctls for MXC framebuffer. + * + * @param inode inode struct + * + * @param file file struct + * + * @param cmd Ioctl command to handle + * + * @param arg User pointer to command arguments + * + * @param fbi framebuffer information pointer + */ +static int mxcfb_ioctl_ovl(struct fb_info *fbi, unsigned int cmd, + unsigned long arg) +{ + int retval = 0; + int __user *argp = (void __user *)arg; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + switch (cmd) { + case FBIO_ALLOC: + { + int size; + struct mxcfb_alloc_list *mem; + + mem = kzalloc(sizeof(*mem), GFP_KERNEL); + if (mem == NULL) + return -ENOMEM; + + if (get_user(size, argp)) + return -EFAULT; + + mem->size = PAGE_ALIGN(size); + + mem->cpu_addr = dma_alloc_coherent(fbi->device, size, + &mem->phy_addr, + GFP_DMA); + if (mem->cpu_addr == NULL) { + kfree(mem); + return -ENOMEM; + } + + list_add(&mem->list, &fb_alloc_list); + + dev_dbg(fbi->device, "allocated %d bytes @ 0x%08X\n", + mem->size, mem->phy_addr); + + if (put_user(mem->phy_addr, argp)) + return -EFAULT; + + break; + } + case FBIO_FREE: + { + unsigned long offset; + struct mxcfb_alloc_list *mem; + + if (get_user(offset, argp)) + return -EFAULT; + + retval = -EINVAL; + list_for_each_entry(mem, &fb_alloc_list, list) { + if (mem->phy_addr == offset) { + list_del(&mem->list); + dma_free_coherent(fbi->device, + mem->size, + mem->cpu_addr, + mem->phy_addr); + kfree(mem); + retval = 0; + break; + } + } + + break; + } + case MXCFB_SET_OVERLAY_POS: + { + struct mxcfb_pos pos; + if (copy_from_user(&pos, (void *)arg, sizeof(pos))) { + retval = -EFAULT; + break; + } + retval = ipu_disp_set_window_pos(mxc_fbi->ipu_ch, + pos.x, pos.y); + break; + } + case MXCFB_GET_FB_IPU_CHAN: + { + struct mxcfb_info *mxc_fbi = + (struct mxcfb_info *)fbi->par; + + if (put_user(mxc_fbi->ipu_ch, argp)) + return -EFAULT; + + break; + } + default: + retval = -EINVAL; + } + return retval; +} + +/* + * mxcfb_blank(): + * Blank the display. + */ +static int mxcfb_blank(int blank, struct fb_info *info) +{ + int retval; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par; + + dev_dbg(info->device, "blank = %d\n", blank); + + if (mxc_fbi->blank == blank) + return 0; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + mxc_fbi->blank = blank; + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + ipu_disable_channel(MEM_SDC_BG, true); + gpio_lcd_inactive(); + break; + case FB_BLANK_UNBLANK: + gpio_lcd_active(); + ipu_enable_channel(MEM_SDC_BG); + break; + } + return 0; +} + +/* + * mxcfb_blank_ovl(): + * Blank the display. + */ +static int mxcfb_blank_ovl(int blank, struct fb_info *info) +{ + int retval; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par; + + dev_dbg(info->device, "ovl blank = %d\n", blank); + + if (mxc_fbi->blank == blank) + return 0; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + mxc_fbi->blank = blank; + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + ipu_disable_channel(MEM_SDC_FG, true); + break; + case FB_BLANK_UNBLANK: + ipu_enable_channel(MEM_SDC_FG); + break; + } + return 0; +} + +/* + * Pan or Wrap the Display + * + * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag + * + * @param var Variable screen buffer information + * @param info Framebuffer information pointer + */ +static int +mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par; + unsigned long lock_flags = 0; + int retval; + u_int y_bottom; + unsigned long base; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + if (var->xoffset > 0) { + dev_dbg(info->device, "x panning not supported\n"); + return -EINVAL; + } + + if ((info->var.xoffset == var->xoffset) && + (info->var.yoffset == var->yoffset)) { + /* No change, do nothing */ + return 0; + } + + y_bottom = var->yoffset; + + if (!(var->vmode & FB_VMODE_YWRAP)) { + y_bottom += var->yres; + } + + if (y_bottom > info->var.yres_virtual) { + return -EINVAL; + } + + base = (var->yoffset * var->xres_virtual + var->xoffset); + base *= (var->bits_per_pixel) / 8; + base += info->fix.smem_start; + + down(&mxc_fbi->flip_sem); + + spin_lock_irqsave(&mxc_fbi->fb_lock, lock_flags); + + dev_dbg(info->device, "Updating SDC BG buf %d address=0x%08lX\n", + mxc_fbi->cur_ipu_buf, base); + + mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf; + if (ipu_update_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf, base) == 0) { + ipu_select_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf); + ipu_clear_irq(mxc_fbi->ipu_ch_irq); + ipu_enable_irq(mxc_fbi->ipu_ch_irq); + } else { + dev_err(info->device, + "Error updating SDC buf %d to address=0x%08lX\n", + mxc_fbi->cur_ipu_buf, base); + } + + spin_unlock_irqrestore(&mxc_fbi->fb_lock, lock_flags); + + dev_dbg(info->device, "Update complete\n"); + + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + + if (var->vmode & FB_VMODE_YWRAP) { + info->var.vmode |= FB_VMODE_YWRAP; + } else { + info->var.vmode &= ~FB_VMODE_YWRAP; + } + + return 0; +} + +/* + * Function to handle custom mmap for MXC framebuffer. + * + * @param fbi framebuffer information pointer + * + * @param vma Pointer to vm_area_struct + */ +static int mxcfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma) +{ + bool found = false; + u32 len; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + struct mxcfb_alloc_list *mem; + + if (offset < fbi->fix.smem_len) { + /* mapping framebuffer memory */ + len = fbi->fix.smem_len - offset; + vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT; + } else { + list_for_each_entry(mem, &fb_alloc_list, list) { + if (offset == mem->phy_addr) { + found = true; + len = mem->size; + break; + } + } + if (!found) { + return -EINVAL; + } + } + + len = PAGE_ALIGN(len); + if (vma->vm_end - vma->vm_start > len) { + return -EINVAL; + } + + /* make buffers write-thru cacheable */ + vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) & + ~L_PTE_BUFFERABLE); + + vma->vm_flags |= VM_IO | VM_RESERVED; + + if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) { + dev_dbg(fbi->device, "mmap remap_pfn_range failed\n"); + return -ENOBUFS; + + } + + return 0; +} + +/*! + * This structure contains the pointers to the control functions that are + * invoked by the core framebuffer driver to perform operations like + * blitting, rectangle filling, copy regions and cursor definition. + */ +static struct fb_ops mxcfb_ops = { + .owner = THIS_MODULE, + .fb_set_par = mxcfb_set_par, + .fb_check_var = mxcfb_check_var, + .fb_setcolreg = mxcfb_setcolreg, + .fb_pan_display = mxcfb_pan_display, + .fb_ioctl = mxcfb_ioctl, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_blank = mxcfb_blank, +}; + +static struct fb_ops mxcfb_ovl_ops = { + .owner = THIS_MODULE, + .fb_set_par = mxcfb_set_par, + .fb_check_var = mxcfb_check_var, + .fb_setcolreg = mxcfb_setcolreg, + .fb_pan_display = mxcfb_pan_display, + .fb_ioctl = mxcfb_ioctl_ovl, + .fb_mmap = mxcfb_mmap, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_blank = mxcfb_blank_ovl, +}; + +static irqreturn_t mxcfb_vsync_irq_handler(int irq, void *dev_id) +{ + struct mxcfb_data *fb_data = dev_id; + + ipu_disable_irq(irq); + + fb_data->vsync_flag = 1; + wake_up_interruptible(&fb_data->vsync_wq); + return IRQ_HANDLED; +} + +static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id) +{ + struct fb_info *fbi = dev_id; + struct mxcfb_info *mxc_fbi = fbi->par; + + up(&mxc_fbi->flip_sem); + ipu_disable_irq(irq); + return IRQ_HANDLED; +} + +#ifdef CONFIG_PM +/* + * Power management hooks. Note that we won't be called from IRQ context, + * unlike the blank functions above, so we may sleep. + */ + +/* + * Suspends the framebuffer and blanks the screen. Power management support + */ +static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mxcfb_data *drv_data = platform_get_drvdata(pdev); + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)drv_data->fbi->par; + struct mxcfb_info *mxc_fbi_ovl = + (struct mxcfb_info *)drv_data->fbi_ovl->par; +#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY + void *fbmem; +#endif + + drv_data->suspended = true; + + acquire_console_sem(); + fb_set_suspend(drv_data->fbi, 1); + fb_set_suspend(drv_data->fbi_ovl, 1); + release_console_sem(); + + if (mxc_fbi_ovl->blank == FB_BLANK_UNBLANK) { + ipu_disable_channel(MEM_SDC_FG, true); + } + + if (mxc_fbi->blank == FB_BLANK_UNBLANK) { +#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY + if (drv_data->fbi->fix.smem_start != FB_RAM_BASE_ADDR) { + fbmem = ioremap(FB_RAM_BASE_ADDR, FB_RAM_SIZE); + memcpy(fbmem, drv_data->fbi->screen_base, FB_RAM_SIZE); + iounmap(fbmem); + mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf; + ipu_update_channel_buffer(MEM_SDC_BG, IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf, + FB_RAM_BASE_ADDR); + ipu_select_buffer(MEM_SDC_BG, IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf); + } + ipu_lowpwr_display_enable(); +#else + ipu_disable_channel(MEM_SDC_BG, true); + gpio_lcd_inactive(); +#endif + } + return 0; +} + +/* + * Resumes the framebuffer and unblanks the screen. Power management support + */ +static int mxcfb_resume(struct platform_device *pdev) +{ + struct mxcfb_data *drv_data = platform_get_drvdata(pdev); + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)drv_data->fbi->par; + struct mxcfb_info *mxc_fbi_ovl = + (struct mxcfb_info *)drv_data->fbi_ovl->par; + + drv_data->suspended = false; + + if (mxc_fbi->blank == FB_BLANK_UNBLANK) { +#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY + ipu_lowpwr_display_disable(); + if (drv_data->fbi->fix.smem_start != FB_RAM_BASE_ADDR) { + mxc_fbi->cur_ipu_buf = !mxc_fbi->cur_ipu_buf; + ipu_update_channel_buffer(MEM_SDC_BG, IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf, + drv_data->fbi->fix. + smem_start); + ipu_select_buffer(MEM_SDC_BG, IPU_INPUT_BUFFER, + mxc_fbi->cur_ipu_buf); + } +#else + gpio_lcd_active(); + ipu_enable_channel(MEM_SDC_BG); +#endif + } + + if (mxc_fbi_ovl->blank == FB_BLANK_UNBLANK) { + ipu_enable_channel(MEM_SDC_FG); + } + + acquire_console_sem(); + fb_set_suspend(drv_data->fbi, 0); + fb_set_suspend(drv_data->fbi_ovl, 0); + release_console_sem(); + + wake_up_interruptible(&drv_data->suspend_wq); + return 0; +} +#else +#define mxcfb_suspend NULL +#define mxcfb_resume NULL +#endif + +/* + * Main framebuffer functions + */ + +/*! + * Allocates the DRAM memory for the frame buffer. This buffer is remapped + * into a non-cached, non-buffered, memory region to allow palette and pixel + * writes to occur without flushing the cache. Once this area is remapped, + * all virtual memory access to the video memory should occur at the new region. + * + * @param fbi framebuffer information pointer + * + * @param use_internal_ram flag on whether to use internal RAM for memory + * + * @return Error code indicating success or failure + */ +static int mxcfb_map_video_memory(struct fb_info *fbi, bool use_internal_ram) +{ + int retval = 0; + +#ifdef CONFIG_FB_MXC_INTERNAL_MEM + if (use_internal_ram) { + fbi->fix.smem_len = FB_RAM_SIZE; + fbi->fix.smem_start = FB_RAM_BASE_ADDR; + if (fbi->fix.smem_len < + (fbi->var.yres_virtual * fbi->fix.line_length)) { + dev_err(fbi->device, + "Not enough internal RAM for framebuffer configuration\n"); + retval = -EINVAL; + goto err0; + } + + if (request_mem_region(fbi->fix.smem_start, fbi->fix.smem_len, + fbi->device->driver->name) == NULL) { + dev_err(fbi->device, + "Unable to request internal RAM\n"); + retval = -ENOMEM; + goto err0; + } + + fbi->screen_base = ioremap(fbi->fix.smem_start, + fbi->fix.smem_len); + if (!fbi->screen_base) { + dev_err(fbi->device, + "Unable to map fb memory to virtual address\n"); + release_mem_region(fbi->fix.smem_start, + fbi->fix.smem_len); + retval = -EIO; + goto err0; + } + + iram_clk = clk_get(NULL, "iram_clk"); + clk_enable(iram_clk); + } else +#endif + { + fbi->fix.smem_len = fbi->var.yres_virtual * + fbi->fix.line_length; + fbi->screen_base = + dma_alloc_writecombine(fbi->device, + fbi->fix.smem_len, + (dma_addr_t *) &fbi->fix.smem_start, + GFP_DMA); + + if (fbi->screen_base == 0) { + dev_err(fbi->device, + "Unable to allocate framebuffer memory\n"); + retval = -EBUSY; + goto err0; + } + } + + dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n", + (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len); + + fbi->screen_size = fbi->fix.smem_len; + + /* Clear the screen */ + memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); + + return 0; + + err0: + fbi->fix.smem_len = 0; + fbi->fix.smem_start = 0; + fbi->screen_base = NULL; + return retval; +} + +/*! + * De-allocates the DRAM memory for the frame buffer. + * + * @param fbi framebuffer information pointer + * + * @return Error code indicating success or failure + */ +static int mxcfb_unmap_video_memory(struct fb_info *fbi) +{ +#ifdef CONFIG_FB_MXC_INTERNAL_MEM + if (fbi->fix.smem_start == FB_RAM_BASE_ADDR) { + iounmap(fbi->screen_base); + release_mem_region(fbi->fix.smem_start, fbi->fix.smem_len); + fbi->fix.smem_start = 0; + fbi->fix.smem_len = 0; + clk_disable(iram_clk); + } else +#endif + { + dma_free_writecombine(fbi->device, fbi->fix.smem_len, + fbi->screen_base, fbi->fix.smem_start); + } + fbi->screen_base = 0; + fbi->fix.smem_start = 0; + fbi->fix.smem_len = 0; + return 0; +} + +/*! + * Initializes the framebuffer information pointer. After allocating + * sufficient memory for the framebuffer structure, the fields are + * filled with custom information passed in from the configurable + * structures. This includes information such as bits per pixel, + * color maps, screen width/height and RGBA offsets. + * + * @return Framebuffer structure initialized with our information + */ +static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops) +{ + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + + /* + * Allocate sufficient memory for the fb structure + */ + fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev); + if (!fbi) + return NULL; + + mxcfbi = (struct mxcfb_info *)fbi->par; + + fbi->var.activate = FB_ACTIVATE_NOW; + + fbi->fbops = ops; + fbi->flags = FBINFO_FLAG_DEFAULT; + fbi->pseudo_palette = mxcfbi->pseudo_palette; + + spin_lock_init(&mxcfbi->fb_lock); + + /* + * Allocate colormap + */ + fb_alloc_cmap(&fbi->cmap, 16, 0); + + return fbi; +} + +/*! + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxcfb_probe(struct platform_device *pdev) +{ + char *mode = pdev->dev.platform_data; + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + struct fb_info *fbi_ovl; + int ret = 0; + + /* + * Initialize FB structures + */ + fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops); + if (!fbi) { + ret = -ENOMEM; + goto err0; + } + mxcfbi = (struct mxcfb_info *)fbi->par; + + mxcfbi->ipu_ch_irq = IPU_IRQ_SDC_BG_EOF; + mxcfbi->cur_ipu_buf = 0; + mxcfbi->ipu_ch = MEM_SDC_BG; + + ipu_sdc_set_global_alpha(true, 0xFF); + ipu_sdc_set_color_key(MEM_SDC_BG, false, 0); + + if (ipu_request_irq(IPU_IRQ_SDC_BG_EOF, mxcfb_irq_handler, 0, + MXCFB_NAME, fbi) != 0) { + dev_err(&pdev->dev, "Error registering BG irq handler.\n"); + ret = -EBUSY; + goto err1; + } + ipu_disable_irq(IPU_IRQ_SDC_BG_EOF); + + if (fb_mode == NULL) { + fb_mode = mode; + } + + if (!fb_find_mode(&fbi->var, fbi, fb_mode, mxcfb_modedb, + mxcfb_modedb_sz, NULL, default_bpp)) { + ret = -EBUSY; + goto err2; + } + fb_videomode_to_modelist(mxcfb_modedb, mxcfb_modedb_sz, &fbi->modelist); + + /* Default Y virtual size is 2x panel size */ +#ifndef CONFIG_FB_MXC_INTERNAL_MEM + fbi->var.yres_virtual = fbi->var.yres * 2; +#endif + + mxcfb_drv_data.fbi = fbi; + mxcfb_drv_data.backlight_level = 255; + mxcfb_drv_data.suspended = false; + init_waitqueue_head(&mxcfb_drv_data.suspend_wq); + + mxcfbi->blank = FB_BLANK_NORMAL; + ret = mxcfb_set_par(fbi); + if (ret < 0) { + goto err2; + } + mxcfb_blank(FB_BLANK_UNBLANK, fbi); + + /* + * Register framebuffer + */ + ret = register_framebuffer(fbi); + if (ret < 0) { + goto err2; + } + + /* + * Initialize Overlay FB structures + */ + fbi_ovl = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ovl_ops); + if (!fbi_ovl) { + ret = -ENOMEM; + goto err3; + } + mxcfb_drv_data.fbi_ovl = fbi_ovl; + mxcfbi = (struct mxcfb_info *)fbi_ovl->par; + + mxcfbi->ipu_ch_irq = IPU_IRQ_SDC_FG_EOF; + mxcfbi->cur_ipu_buf = 0; + mxcfbi->ipu_ch = MEM_SDC_FG; + + if (ipu_request_irq(IPU_IRQ_SDC_FG_EOF, mxcfb_irq_handler, 0, + MXCFB_NAME, fbi_ovl) != 0) { + dev_err(fbi->device, "Error registering FG irq handler.\n"); + ret = -EBUSY; + goto err4; + } + ipu_disable_irq(mxcfbi->ipu_ch_irq); + + /* Default Y virtual size is 2x panel size */ + fbi_ovl->var = fbi->var; + fbi_ovl->var.yres_virtual = fbi->var.yres * 2; + + /* Overlay is blanked by default */ + mxcfbi->blank = FB_BLANK_NORMAL; + + ret = mxcfb_set_par(fbi_ovl); + if (ret < 0) { + goto err5; + } + + /* + * Register overlay framebuffer + */ + ret = register_framebuffer(fbi_ovl); + if (ret < 0) { + goto err5; + } + + platform_set_drvdata(pdev, &mxcfb_drv_data); + + init_waitqueue_head(&mxcfb_drv_data.vsync_wq); + if (!cpu_is_mx31() && !cpu_is_mx32()) { + ret = ipu_request_irq(IPU_IRQ_SDC_DISP3_VSYNC, + mxcfb_vsync_irq_handler, + 0, MXCFB_NAME, + &mxcfb_drv_data); + if (ret < 0) + goto err6; + ipu_disable_irq(IPU_IRQ_SDC_DISP3_VSYNC); + } + + printk(KERN_INFO "mxcfb: fb registered, using mode %s\n", fb_mode); + return 0; + + err6: + unregister_framebuffer(fbi_ovl); + err5: + ipu_free_irq(IPU_IRQ_SDC_FG_EOF, fbi_ovl); + err4: + fb_dealloc_cmap(&fbi_ovl->cmap); + framebuffer_release(fbi_ovl); + err3: + unregister_framebuffer(fbi); + err2: + ipu_free_irq(IPU_IRQ_SDC_BG_EOF, fbi); + err1: + fb_dealloc_cmap(&fbi->cmap); + framebuffer_release(fbi); + err0: + printk(KERN_ERR "mxcfb: failed to register fb\n"); + return ret; +} + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcfb_driver = { + .driver = { + .name = MXCFB_NAME, + }, + .probe = mxcfb_probe, + .suspend = mxcfb_suspend, + .resume = mxcfb_resume, +}; + +/* + * Parse user specified options (`video=trident:') + * example: + * video=trident:800x600,bpp=16,noaccel + */ +int mxcfb_setup(char *options) +{ + char *opt; + if (!options || !*options) + return 0; + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + if (!strncmp(opt, "bpp=", 4)) + default_bpp = simple_strtoul(opt + 4, NULL, 0); + else + fb_mode = opt; + } + return 0; +} + +/*! + * Main entry function for the framebuffer. The function registers the power + * management callback functions with the kernel and also registers the MXCFB + * callback functions with the core Linux framebuffer driver \b fbmem.c + * + * @return Error code indicating success or failure + */ +int __init mxcfb_init(void) +{ + int ret = 0; +#ifndef MODULE + char *option = NULL; +#endif + +#ifndef MODULE + if (fb_get_options("mxcfb", &option)) + return -ENODEV; + mxcfb_setup(option); +#endif + + ret = platform_driver_register(&mxcfb_driver); + return ret; +} + +void mxcfb_exit(void) +{ + struct fb_info *fbi = mxcfb_drv_data.fbi; + + if (fbi) { + mxcfb_unmap_video_memory(fbi); + + if (&fbi->cmap) + fb_dealloc_cmap(&fbi->cmap); + + unregister_framebuffer(fbi); + framebuffer_release(fbi); + } + + fbi = mxcfb_drv_data.fbi_ovl; + if (fbi) { + mxcfb_unmap_video_memory(fbi); + + if (&fbi->cmap) + fb_dealloc_cmap(&fbi->cmap); + + unregister_framebuffer(fbi); + framebuffer_release(fbi); + } +#ifndef CONFIG_ARCH_MX3 + ipu_free_irq(IPU_IRQ_SDC_DISP3_VSYNC, &mxcfb_drv_data); +#endif + + platform_driver_unregister(&mxcfb_driver); +} + +module_init(mxcfb_init); +module_exit(mxcfb_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC framebuffer driver"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("fb"); diff --git a/drivers/video/mxc/mxcfb_ch7026.c b/drivers/video/mxc/mxcfb_ch7026.c new file mode 100644 index 000000000000..a3f508450852 --- /dev/null +++ b/drivers/video/mxc/mxcfb_ch7026.c @@ -0,0 +1,370 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxcfb_epson_vga.c + * + * @brief MXC Frame buffer driver for SDC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct i2c_client *ch7026_client; + +static int lcd_init(void); +static void lcd_poweron(struct fb_info *info); +static void lcd_poweroff(void); + +static void (*lcd_reset) (void); +static struct regulator *io_reg; +static struct regulator *core_reg; +static struct regulator *analog_reg; + + /* 8 800x600-60 VESA */ +static struct fb_videomode mode = { + NULL, 60, 800, 600, 25000, 88, 40, 23, 1, 128, 4, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA +}; + +static void lcd_init_fb(struct fb_info *info) +{ + struct fb_var_screeninfo var; + + memset(&var, 0, sizeof(var)); + + fb_videomode_to_var(&var, &mode); + + var.activate = FB_ACTIVATE_ALL; + + acquire_console_sem(); + info->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(info, &var); + fb_blank(info, FB_BLANK_UNBLANK); + info->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); +} + +static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + + if (strcmp(event->info->fix.id, "DISP3 BG - DI1")) + return 0; + + switch (val) { + case FB_EVENT_FB_REGISTERED: + lcd_init_fb(event->info); + lcd_poweron(event->info); + break; + case FB_EVENT_BLANK: + if (*((int *)event->data) == FB_BLANK_UNBLANK) + lcd_poweron(event->info); + else + lcd_poweroff(); + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = lcd_fb_event, +}; + +/*! + * This function is called whenever the SPI slave device is detected. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit lcd_probe(struct device *dev) +{ + int ret = 0; + int i; + struct mxc_lcd_platform_data *plat = dev->platform_data; + + if (plat) { + + io_reg = regulator_get(dev, plat->io_reg); + if (!IS_ERR(io_reg)) { + regulator_set_voltage(io_reg, 1800000, 1800000); + regulator_enable(io_reg); + } else { + io_reg = NULL; + } + + core_reg = regulator_get(dev, plat->core_reg); + if (!IS_ERR(core_reg)) { + regulator_set_voltage(core_reg, 2500000, 2500000); + regulator_enable(core_reg); + } else { + core_reg = NULL; + } + analog_reg = regulator_get(dev, plat->analog_reg); + if (!IS_ERR(analog_reg)) { + regulator_set_voltage(analog_reg, 2775000, 2775000); + regulator_enable(analog_reg); + } else { + analog_reg = NULL; + } + msleep(100); + + lcd_reset = plat->reset; + if (lcd_reset) + lcd_reset(); + } + + for (i = 0; i < num_registered_fb; i++) { + if (strcmp(registered_fb[i]->fix.id, "DISP3 BG - DI1") == 0) { + ret = lcd_init(); + if (ret < 0) + goto err; + + lcd_init_fb(registered_fb[i]); + fb_show_logo(registered_fb[i], 0); + lcd_poweron(registered_fb[i]); + } + } + + fb_register_client(&nb); + return 0; +err: + if (io_reg) + regulator_disable(io_reg); + if (core_reg) + regulator_disable(core_reg); + if (analog_reg) + regulator_disable(analog_reg); + + return ret; +} + +static int __devinit ch7026_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + ch7026_client = client; + + return lcd_probe(&client->dev); +} + +static int __devexit ch7026_remove(struct i2c_client *client) +{ + fb_unregister_client(&nb); + lcd_poweroff(); + regulator_put(io_reg); + regulator_put(core_reg); + regulator_put(analog_reg); + + return 0; +} + +static int ch7026_suspend(struct i2c_client *client, pm_message_t message) +{ + return 0; +} + +static int ch7026_resume(struct i2c_client *client) +{ + return 0; +} + +u8 reg_init[][2] = { + { 0x02, 0x01 }, + { 0x02, 0x03 }, + { 0x03, 0x00 }, + { 0x06, 0x6B }, + { 0x08, 0x08 }, + { 0x09, 0x80 }, + { 0x0C, 0x0A }, + { 0x0D, 0x89 }, + { 0x0F, 0x23 }, + { 0x10, 0x20 }, + { 0x11, 0x20 }, + { 0x12, 0x40 }, + { 0x13, 0x28 }, + { 0x14, 0x80 }, + { 0x15, 0x52 }, + { 0x16, 0x58 }, + { 0x17, 0x74 }, + { 0x19, 0x01 }, + { 0x1A, 0x04 }, + { 0x1B, 0x23 }, + { 0x1C, 0x20 }, + { 0x1D, 0x20 }, + { 0x1F, 0x28 }, + { 0x20, 0x80 }, + { 0x21, 0x12 }, + { 0x22, 0x58 }, + { 0x23, 0x74 }, + { 0x25, 0x01 }, + { 0x26, 0x04 }, + { 0x37, 0x20 }, + { 0x39, 0x20 }, + { 0x3B, 0x20 }, + { 0x41, 0xA2 }, + { 0x4D, 0x03 }, + { 0x4E, 0x13 }, + { 0x4F, 0xB1 }, + { 0x50, 0x3B }, + { 0x51, 0x54 }, + { 0x52, 0x12 }, + { 0x53, 0x13 }, + { 0x55, 0xE5 }, + { 0x5E, 0x80 }, + { 0x69, 0x64 }, + { 0x7D, 0x62 }, + { 0x04, 0x00 }, + { 0x06, 0x69 }, + + /* + NOTE: The following five repeated sentences are used here to wait memory initial complete, please don't remove...(you could refer to Appendix A of programming guide document (CH7025(26)B Programming Guide Rev2.03.pdf) for detailed information about memory initialization! + */ + { 0x03, 0x00 }, + { 0x03, 0x00 }, + { 0x03, 0x00 }, + { 0x03, 0x00 }, + { 0x03, 0x00 }, + + { 0x06, 0x68 }, + { 0x02, 0x02 }, + { 0x02, 0x03 }, +}; + +#define REGMAP_LENGTH (sizeof(reg_init) / (2*sizeof(u8))) + +/* + * Send init commands to L4F00242T03 + * + */ +static int lcd_init(void) +{ + int i; + int dat; + + dev_dbg(&ch7026_client->dev, "initializing CH7026\n"); + + /* read device ID */ + msleep(100); + dat = i2c_smbus_read_byte_data(ch7026_client, 0x00); + dev_dbg(&ch7026_client->dev, "read id = 0x%02X\n", dat); + if (dat != 0x54) + return -ENODEV; + + for (i = 0; i < REGMAP_LENGTH; ++i) { + if (i2c_smbus_write_byte_data + (ch7026_client, reg_init[i][0], reg_init[i][1]) < 0) + return -EIO; + } + + return 0; +} + +static int lcd_on; +/* + * Send Power On commands to L4F00242T03 + * + */ +static void lcd_poweron(struct fb_info *info) +{ + u16 data[4]; + u32 refresh; + + if (lcd_on) + return; + + dev_dbg(&ch7026_client->dev, "turning on LCD\n"); + + data[0] = PICOS2KHZ(info->var.pixclock) / 10; + data[2] = info->var.hsync_len + info->var.left_margin + + info->var.xres + info->var.right_margin; + data[3] = info->var.vsync_len + info->var.upper_margin + + info->var.yres + info->var.lower_margin; + + refresh = data[2] * data[3]; + refresh = (PICOS2KHZ(info->var.pixclock) * 1000) / refresh; + data[1] = refresh * 100; + + lcd_on = 1; +} + +/* + * Send Power Off commands to L4F00242T03 + * + */ +static void lcd_poweroff(void) +{ + if (!lcd_on) + return; + + dev_dbg(&ch7026_client->dev, "turning off LCD\n"); + + lcd_on = 0; +} + +static const struct i2c_device_id ch7026_id[] = { + {"ch7026", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ch7026_id); + +static struct i2c_driver ch7026_driver = { + .driver = { + .name = "ch7026", + }, + .probe = ch7026_probe, + .remove = ch7026_remove, + .suspend = ch7026_suspend, + .resume = ch7026_resume, + .id_table = ch7026_id, +}; + +static int __init ch7026_init(void) +{ + return i2c_add_driver(&ch7026_driver); +} + +static void __exit ch7026_exit(void) +{ + i2c_del_driver(&ch7026_driver); +} + +module_init(ch7026_init); +module_exit(ch7026_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("CH7026 VGA driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/mxcfb_claa_wvga.c b/drivers/video/mxc/mxcfb_claa_wvga.c new file mode 100644 index 000000000000..c69ee3433c68 --- /dev/null +++ b/drivers/video/mxc/mxcfb_claa_wvga.c @@ -0,0 +1,240 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxcfb_claa_wvga.c + * + * @brief MXC Frame buffer driver for SDC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void lcd_poweron(void); +static void lcd_poweroff(void); + +static struct platform_device *plcd_dev; +static struct regulator *io_reg; +static struct regulator *core_reg; +static int lcd_on; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static void lcd_init_fb(struct fb_info *info) +{ + struct fb_var_screeninfo var; + + memset(&var, 0, sizeof(var)); + + fb_videomode_to_var(&var, &video_modes[0]); + + var.activate = FB_ACTIVATE_ALL; + var.yres_virtual = var.yres * 3; + + acquire_console_sem(); + info->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(info, &var); + info->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); +} + +static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + + if (strcmp(event->info->fix.id, "DISP3 BG") && + strcmp(event->info->fix.id, "mxc_elcdif_fb")) + return 0; + + switch (val) { + case FB_EVENT_FB_REGISTERED: + lcd_init_fb(event->info); + fb_show_logo(event->info, 0); + lcd_poweron(); + break; + case FB_EVENT_BLANK: + if ((event->info->var.xres != 800) || + (event->info->var.yres != 480)) { + break; + } + if (*((int *)event->data) == FB_BLANK_UNBLANK) { + lcd_poweron(); + } else { + lcd_poweroff(); + } + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = lcd_fb_event, +}; + +/*! + * This function is called whenever the SPI slave device is detected. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit lcd_probe(struct platform_device *pdev) +{ + int i; + struct mxc_lcd_platform_data *plat = pdev->dev.platform_data; + + if (plat) { + if (plat->reset) + plat->reset(); + + io_reg = regulator_get(&pdev->dev, plat->io_reg); + if (IS_ERR(io_reg)) + io_reg = NULL; + core_reg = regulator_get(&pdev->dev, plat->core_reg); + if (!IS_ERR(core_reg)) { + regulator_set_voltage(io_reg, 1800000, 1800000); + } else { + core_reg = NULL; + } + } + + for (i = 0; i < num_registered_fb; i++) { + if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0 || + strcmp(registered_fb[i]->fix.id, "mxc_elcdif_fb") == 0) { + lcd_init_fb(registered_fb[i]); + fb_show_logo(registered_fb[i], 0); + lcd_poweron(); + } else if (strcmp(registered_fb[i]->fix.id, "DISP3 FG") == 0) { + lcd_init_fb(registered_fb[i]); + } + } + + fb_register_client(&nb); + + plcd_dev = pdev; + + return 0; +} + +static int __devexit lcd_remove(struct platform_device *pdev) +{ + fb_unregister_client(&nb); + lcd_poweroff(); + if (io_reg) + regulator_put(io_reg); + if (core_reg) + regulator_put(core_reg); + + return 0; +} + +#ifdef CONFIG_PM +static int lcd_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int lcd_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define lcd_suspend NULL +#define lcd_resume NULL +#endif + +/*! + * platform driver structure for CLAA WVGA + */ +static struct platform_driver lcd_driver = { + .driver = { + .name = "lcd_claa"}, + .probe = lcd_probe, + .remove = __devexit_p(lcd_remove), + .suspend = lcd_suspend, + .resume = lcd_resume, +}; + +/* + * Send Power On commands to L4F00242T03 + * + */ +static void lcd_poweron(void) +{ + if (lcd_on) + return; + + dev_dbg(&plcd_dev->dev, "turning on LCD\n"); + if (core_reg) + regulator_enable(core_reg); + if (io_reg) + regulator_enable(io_reg); + lcd_on = 1; +} + +/* + * Send Power Off commands to L4F00242T03 + * + */ +static void lcd_poweroff(void) +{ + lcd_on = 0; + dev_dbg(&plcd_dev->dev, "turning off LCD\n"); + if (io_reg) + regulator_disable(io_reg); + if (core_reg) + regulator_disable(core_reg); +} + +static int __init claa_lcd_init(void) +{ + return platform_driver_register(&lcd_driver); +} + +static void __exit claa_lcd_exit(void) +{ + platform_driver_unregister(&lcd_driver); +} + +module_init(claa_lcd_init); +module_exit(claa_lcd_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("CLAA WVGA LCD init driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/mxcfb_epson.c b/drivers/video/mxc/mxcfb_epson.c new file mode 100644 index 000000000000..2b9bbec8a7e4 --- /dev/null +++ b/drivers/video/mxc/mxcfb_epson.c @@ -0,0 +1,1153 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxcfb_epson.c + * + * @brief MXC Frame buffer driver for ADC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PARTIAL_REFRESH +#define MXCFB_REFRESH_DEFAULT MXCFB_REFRESH_PARTIAL +/* + * Driver name + */ +#define MXCFB_NAME "MXCFB_EPSON" + +#define MXCFB_SCREEN_TOP_OFFSET 0 +#define MXCFB_SCREEN_LEFT_OFFSET 2 +#define MXCFB_SCREEN_WIDTH 176 +#define MXCFB_SCREEN_HEIGHT 220 + +/*! + * Enum defining Epson panel commands. + */ +enum { + DISON = 0xAF, + DISOFF = 0xAE, + DISCTL = 0xCA, + SD_CSET = 0x15, + SD_PSET = 0x75, + DATCTL = 0xBC, + SLPIN = 0x95, + SLPOUT = 0x94, + DISNOR = 0xA6, + RAMWR = 0x5C, + VOLCTR = 0xC6, + GCP16 = 0xCC, + GCP64 = 0xCB, +}; + +struct mxcfb_info { + int open_count; + int blank; + uint32_t disp_num; + + u32 pseudo_palette[16]; + + int32_t cur_update_mode; + dma_addr_t alloc_start_paddr; + void *alloc_start_vaddr; + u32 alloc_size; + uint32_t snoop_window_size; +}; + +struct mxcfb_data { + struct fb_info *fbi; + volatile int32_t vsync_flag; + wait_queue_head_t vsync_wq; + wait_queue_head_t suspend_wq; + bool suspended; +}; + +static struct mxcfb_data mxcfb_drv_data; +static unsigned long default_bpp = 16; + +void slcd_gpio_config(void); +extern void gpio_lcd_active(void); +static int mxcfb_blank(int blank, struct fb_info *fbi); + +static uint32_t bpp_to_pixfmt(int bpp) +{ + uint32_t pixfmt = 0; + switch (bpp) { + case 24: + pixfmt = IPU_PIX_FMT_BGR24; + break; + case 32: + pixfmt = IPU_PIX_FMT_BGR32; + break; + case 16: + pixfmt = IPU_PIX_FMT_RGB565; + break; + } + return pixfmt; +} + +/*! + * This function sets display region in the Epson panel + * + * @param disp display panel to config + * @param x1 x-coordinate of one vertex. + * @param x2 x-coordinate of second vertex. + * @param y1 y-coordinate of one vertex. + * @param y2 y-coordinate of second vertex. + */ +void set_panel_region(int disp, uint32_t x1, uint32_t x2, + uint32_t y1, uint32_t y2) +{ + uint32_t param[8]; + + memset(param, 0, sizeof(uint32_t) * 8); + param[0] = x1; + param[2] = x2; + param[4] = y1; + param[6] = y2; + + /* SD_CSET */ + ipu_adc_write_cmd(disp, CMD, SD_CSET, param, 4); + + /* SD_PSET */ + ipu_adc_write_cmd(disp, CMD, SD_PSET, &(param[4]), 4); +} + +/*! + * Function to create and initiate template command buffer for ADC. This + * template will be written to Panel memory. + */ +static void init_channel_template(int disp) +{ + /* template command buffer for ADC is 32 */ + uint32_t tempCmd[TEMPLATE_BUF_SIZE]; + uint32_t i = 0; + + memset(tempCmd, 0, sizeof(uint32_t) * TEMPLATE_BUF_SIZE); + /* setup update display region */ + /* whole the screen during init */ + /*WRITE Y COORDINATE CMND */ + tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 0, SINGLE_STEP, SD_PSET); + /*WRITE Y START ADDRESS CMND LSB[22:8] */ + tempCmd[i++] = ipu_adc_template_gen(WR_YADDR, 1, SINGLE_STEP, 0x01); + /*WRITE Y START ADDRESS CMND MSB[22:16] */ + tempCmd[i++] = ipu_adc_template_gen(WR_YADDR, 1, SINGLE_STEP, 0x09); + /*WRITE Y STOP ADDRESS CMND LSB */ + tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP, + MXCFB_SCREEN_HEIGHT - 1); + /*WRITE Y STOP ADDRESS CMND MSB */ + tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP, 0); + /*WRITE X COORDINATE CMND */ + tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 0, SINGLE_STEP, SD_CSET); + /*WRITE X ADDRESS CMND LSB[7:0] */ + tempCmd[i++] = ipu_adc_template_gen(WR_XADDR, 1, SINGLE_STEP, 0x01); + /*WRITE X ADDRESS CMND MSB[22:8] */ + tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP, 0); + /*WRITE X STOP ADDRESS CMND LSB */ + tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP, + MXCFB_SCREEN_WIDTH + 1); + /*WRITE X STOP ADDRESS CMND MSB */ + tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 1, SINGLE_STEP, 0); + /*WRITE MEMORY CMND MSB */ + tempCmd[i++] = ipu_adc_template_gen(WR_CMND, 0, SINGLE_STEP, RAMWR); + /*WRITE DATA CMND and STP */ + tempCmd[i++] = ipu_adc_template_gen(WR_DATA, 1, STOP, 0); + + ipu_adc_write_template(disp, tempCmd, true); +} + +/*! + * Function to initialize the panel. First it resets the panel and then + * initilizes panel. + */ +static void _init_panel(int disp) +{ + uint32_t cmd_param; + uint32_t i; + + gpio_lcd_active(); + slcd_gpio_config(); + + /* DATCTL */ +#ifdef CONFIG_FB_MXC_ASYNC_PANEL_IFC_16_BIT + /* 16-bit 565 mode */ + cmd_param = 0x28; +#else + /* 8-bit 666 mode */ + cmd_param = 0x08; +#endif + ipu_adc_write_cmd(disp, CMD, DATCTL, &cmd_param, 1); + + /* Sleep OUT */ + ipu_adc_write_cmd(disp, CMD, SLPOUT, 0, 0); + + /* Set display to white + Setup page and column addresses */ + set_panel_region(disp, MXCFB_SCREEN_LEFT_OFFSET, + MXCFB_SCREEN_WIDTH + MXCFB_SCREEN_LEFT_OFFSET - 1, + 0, MXCFB_SCREEN_HEIGHT - 1); + /* Do RAM write cmd */ + ipu_adc_write_cmd(disp, CMD, RAMWR, 0, 0); +#ifdef CONFIG_FB_MXC_ASYNC_PANEL_IFC_16_BIT + for (i = 0; i < (MXCFB_SCREEN_WIDTH * MXCFB_SCREEN_HEIGHT); i++) +#else + for (i = 0; i < (MXCFB_SCREEN_WIDTH * MXCFB_SCREEN_HEIGHT * 3); i++) +#endif + ipu_adc_write_cmd(disp, DAT, 0xFFFF, 0, 0); + + /* Pause 80 ms */ + mdelay(80); + + /* Display ON */ + ipu_adc_write_cmd(disp, CMD, DISON, 0, 0); + /* Pause 200 ms */ + mdelay(200); + + pr_debug("initialized panel\n"); +} + +#ifdef PARTIAL_REFRESH +static irqreturn_t mxcfb_sys2_eof_irq_handler(int irq, void *dev_id) +{ + ipu_channel_params_t params; + struct fb_info *fbi = dev_id; + struct mxcfb_info *mxc_fbi = fbi->par; + uint32_t stat[2], seg_size; + uint32_t lsb, msb; + uint32_t update_height, start_line, start_addr, end_line, end_addr; + uint32_t stride_pixels = (fbi->fix.line_length * 8) / + fbi->var.bits_per_pixel; + + ipu_adc_get_snooping_status(&stat[0], &stat[1]); + + if (!stat[0] && !stat[1]) { + dev_err(fbi->device, "error no bus snooping bits set\n"); + return IRQ_HANDLED; + } + ipu_disable_irq(IPU_IRQ_ADC_SYS2_EOF); + + lsb = ffs(stat[0]); + if (lsb) { + lsb--; + } else { + lsb = ffs(stat[1]); + lsb += 32 - 1; + } + msb = fls(stat[1]); + if (msb) { + msb += 32; + } else { + msb = fls(stat[0]); + } + + seg_size = mxc_fbi->snoop_window_size / 64; + + start_addr = lsb * seg_size; /* starting address offset */ + start_line = start_addr / fbi->fix.line_length; + start_addr = start_line * fbi->fix.line_length; /* Addr aligned to line */ + start_addr += fbi->fix.smem_start; + + end_addr = msb * seg_size; /* ending address offset */ + end_line = end_addr / fbi->fix.line_length; + end_line++; + + if (end_line > fbi->var.yres) { + end_line = fbi->var.yres; + } + + update_height = end_line - start_line; + dev_dbg(fbi->device, "updating rows %d to %d, start addr = 0x%08X\n", + start_line, end_line, start_addr); + + ipu_uninit_channel(ADC_SYS1); + params.adc_sys1.disp = mxc_fbi->disp_num; + params.adc_sys1.ch_mode = WriteTemplateNonSeq; + params.adc_sys1.out_left = MXCFB_SCREEN_LEFT_OFFSET; + params.adc_sys1.out_top = start_line; + ipu_init_channel(ADC_SYS1, ¶ms); + + ipu_init_channel_buffer(ADC_SYS1, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi->var.bits_per_pixel), + MXCFB_SCREEN_WIDTH, + update_height, + stride_pixels, + IPU_ROTATE_NONE, (dma_addr_t) start_addr, 0, + 0, 0); + ipu_enable_channel(ADC_SYS1); + ipu_select_buffer(ADC_SYS1, IPU_INPUT_BUFFER, 0); + ipu_enable_irq(IPU_IRQ_ADC_SYS1_EOF); + + return IRQ_HANDLED; +} + +static irqreturn_t mxcfb_sys1_eof_irq_handler(int irq, void *dev_id) +{ + ipu_disable_irq(IPU_IRQ_ADC_SYS1_EOF); + ipu_disable_channel(ADC_SYS1, false); + + ipu_enable_channel(ADC_SYS2); + ipu_enable_irq(IPU_IRQ_ADC_SYS2_EOF); + + return IRQ_HANDLED; +} +#endif + +/*! + * Function to initialize Asynchronous Display Controller. It also initilizes + * the ADC System 1 channel. Configure ADC display 0 parallel interface for + * the panel. + * + * @param fbi framebuffer information pointer + */ +static void mxcfb_init_panel(struct fb_info *fbi) +{ + int msb; + int panel_stride; + ipu_channel_params_t params; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + +#ifdef CONFIG_FB_MXC_ASYNC_PANEL_IFC_16_BIT + uint32_t pix_fmt = IPU_PIX_FMT_RGB565; + ipu_adc_sig_cfg_t sig = { 0, 0, 0, 0, 0, 0, 0, 0, + IPU_ADC_BURST_WCS, + IPU_ADC_IFC_MODE_SYS80_TYPE2, + 16, 0, 0, IPU_ADC_SER_NO_RW + }; + mxc_fbi->disp_num = DISP0; +#elif defined(CONFIG_FB_MXC_ASYNC_PANEL_IFC_8_BIT) + uint32_t pix_fmt = IPU_PIX_FMT_RGB666; + ipu_adc_sig_cfg_t sig = { 0, 0, 0, 0, 0, 0, 0, 0, + IPU_ADC_BURST_WCS, + IPU_ADC_IFC_MODE_SYS80_TYPE2, + 8, 0, 0, IPU_ADC_SER_NO_RW + }; + mxc_fbi->disp_num = DISP0; +#else + uint32_t pix_fmt = IPU_PIX_FMT_RGB565; + ipu_adc_sig_cfg_t sig = { 0, 1, 0, 0, 0, 0, 0, 0, + IPU_ADC_BURST_SERIAL, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK, + 16, 0, 0, IPU_ADC_SER_NO_RW + }; + fbi->disp_num = DISP1; +#endif + +#ifdef PARTIAL_REFRESH + if (ipu_request_irq(IPU_IRQ_ADC_SYS2_EOF, mxcfb_sys2_eof_irq_handler, 0, + MXCFB_NAME, fbi) != 0) { + dev_err(fbi->device, "Error registering SYS2 irq handler.\n"); + return; + } + + if (ipu_request_irq(IPU_IRQ_ADC_SYS1_EOF, mxcfb_sys1_eof_irq_handler, 0, + MXCFB_NAME, fbi) != 0) { + dev_err(fbi->device, "Error registering SYS1 irq handler.\n"); + return; + } + ipu_disable_irq(IPU_IRQ_ADC_SYS1_EOF); + ipu_disable_irq(IPU_IRQ_ADC_SYS2_EOF); +#endif + /* Init DI interface */ + msb = fls(MXCFB_SCREEN_WIDTH); + if (!(MXCFB_SCREEN_WIDTH & ((1UL << msb) - 1))) + msb--; /* Already aligned to power 2 */ + panel_stride = 1UL << msb; + ipu_adc_init_panel(mxc_fbi->disp_num, + MXCFB_SCREEN_WIDTH + MXCFB_SCREEN_LEFT_OFFSET, + MXCFB_SCREEN_HEIGHT, + pix_fmt, panel_stride, sig, XY, 0, VsyncInternal); + + ipu_adc_init_ifc_timing(mxc_fbi->disp_num, true, + 190, 17, 104, 190, 5000000); + ipu_adc_init_ifc_timing(mxc_fbi->disp_num, false, 123, 17, 68, 0, 0); + + /* Needed to turn on ADC clock for panel init */ + memset(¶ms, 0, sizeof(params)); + params.adc_sys1.disp = mxc_fbi->disp_num; + params.adc_sys1.ch_mode = WriteTemplateNonSeq; + params.adc_sys1.out_left = MXCFB_SCREEN_LEFT_OFFSET; + params.adc_sys1.out_top = MXCFB_SCREEN_TOP_OFFSET; + ipu_init_channel(ADC_SYS1, ¶ms); + + _init_panel(mxc_fbi->disp_num); + init_channel_template(mxc_fbi->disp_num); +} + +int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode, + struct mxcfb_rect *update_region) +{ + unsigned long start_addr; + int ret_mode; + uint32_t dummy; + ipu_channel_params_t params; + struct mxcfb_rect rect; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + uint32_t stride_pixels = (fbi->fix.line_length * 8) / + fbi->var.bits_per_pixel; + uint32_t memsize = fbi->fix.smem_len; + + if (mxc_fbi->cur_update_mode == mode) + return mode; + + ret_mode = mxc_fbi->cur_update_mode; + + ipu_disable_irq(IPU_IRQ_ADC_SYS1_EOF); + ipu_adc_set_update_mode(ADC_SYS1, IPU_ADC_REFRESH_NONE, 0, 0, 0); +#ifdef PARTIAL_REFRESH + ipu_disable_irq(IPU_IRQ_ADC_SYS2_EOF); + ipu_adc_set_update_mode(ADC_SYS2, IPU_ADC_REFRESH_NONE, 0, 0, 0); +#endif + + ipu_disable_channel(ADC_SYS1, true); + ipu_clear_irq(IPU_IRQ_ADC_SYS1_EOF); +#ifdef PARTIAL_REFRESH + ipu_disable_channel(ADC_SYS2, true); + ipu_clear_irq(IPU_IRQ_ADC_SYS2_EOF); +#endif + ipu_adc_get_snooping_status(&dummy, &dummy); + + mxc_fbi->cur_update_mode = mode; + + switch (mode) { + case MXCFB_REFRESH_OFF: + if (ipu_adc_set_update_mode(ADC_SYS1, IPU_ADC_REFRESH_NONE, + 0, 0, 0) < 0) + dev_err(fbi->device, "Error enabling auto refesh.\n"); + if (ipu_adc_set_update_mode(ADC_SYS2, IPU_ADC_REFRESH_NONE, + 0, 0, 0) < 0) + dev_err(fbi->device, "Error enabling auto refesh.\n"); +#if 0 + ipu_init_channel_buffer(ADC_SYS2, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi->var.bits_per_pixel), + 1, 1, 4, + IPU_ROTATE_NONE, + fbi->fix.smem_start, + fbi->fix.smem_start, 0, 0); + ipu_enable_channel(ADC_SYS2); + ipu_select_buffer(ADC_SYS2, IPU_INPUT_BUFFER, 0); + ipu_select_buffer(ADC_SYS2, IPU_INPUT_BUFFER, 1); + msleep(10); +#endif + ipu_uninit_channel(ADC_SYS1); +#ifdef PARTIAL_REFRESH + ipu_uninit_channel(ADC_SYS2); +#endif + break; + case MXCFB_REFRESH_PARTIAL: +#ifdef PARTIAL_REFRESH + ipu_adc_get_snooping_status(&dummy, &dummy); + + params.adc_sys2.disp = DISP0; + params.adc_sys2.ch_mode = WriteTemplateNonSeq; + params.adc_sys2.out_left = 0; + params.adc_sys2.out_top = 0; + ipu_init_channel(ADC_SYS2, ¶ms); + + if (ipu_adc_set_update_mode(ADC_SYS1, IPU_ADC_REFRESH_NONE, + 0, 0, 0) < 0) { + dev_err(fbi->device, "Error enabling auto refesh.\n"); + } + if (ipu_adc_set_update_mode + (ADC_SYS2, IPU_ADC_AUTO_REFRESH_SNOOP, 30, + fbi->fix.smem_start, &memsize) < 0) { + dev_err(fbi->device, "Error enabling auto refesh.\n"); + } + mxc_fbi->snoop_window_size = memsize; + + ipu_init_channel_buffer(ADC_SYS2, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi->var.bits_per_pixel), + 1, 1, 4, + IPU_ROTATE_NONE, + fbi->fix.smem_start, 0, 0, 0); + + params.adc_sys1.disp = mxc_fbi->disp_num; + params.adc_sys1.ch_mode = WriteTemplateNonSeq; + params.adc_sys1.out_left = MXCFB_SCREEN_LEFT_OFFSET; + params.adc_sys1.out_top = MXCFB_SCREEN_TOP_OFFSET; + ipu_init_channel(ADC_SYS1, ¶ms); + + ipu_init_channel_buffer(ADC_SYS1, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi->var.bits_per_pixel), + MXCFB_SCREEN_WIDTH, MXCFB_SCREEN_HEIGHT, + stride_pixels, IPU_ROTATE_NONE, + fbi->fix.smem_start, 0, 0, 0); + ipu_enable_channel(ADC_SYS1); + ipu_select_buffer(ADC_SYS1, IPU_INPUT_BUFFER, 0); + ipu_enable_irq(IPU_IRQ_ADC_SYS1_EOF); + break; +#endif + case MXCFB_REFRESH_AUTO: + if (update_region == NULL) { + update_region = ▭ + rect.top = 0; + rect.left = 0; + rect.height = MXCFB_SCREEN_HEIGHT; + rect.width = MXCFB_SCREEN_WIDTH; + } + params.adc_sys1.disp = mxc_fbi->disp_num; + params.adc_sys1.ch_mode = WriteTemplateNonSeq; + params.adc_sys1.out_left = MXCFB_SCREEN_LEFT_OFFSET + + update_region->left; + params.adc_sys1.out_top = MXCFB_SCREEN_TOP_OFFSET + + update_region->top; + ipu_init_channel(ADC_SYS1, ¶ms); + + /* Address aligned to line */ + start_addr = update_region->top * fbi->fix.line_length; + start_addr += fbi->fix.smem_start; + start_addr += update_region->left * fbi->var.bits_per_pixel / 8; + + ipu_init_channel_buffer(ADC_SYS1, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi->var.bits_per_pixel), + update_region->width, + update_region->height, stride_pixels, + IPU_ROTATE_NONE, start_addr, 0, 0, 0); + ipu_enable_channel(ADC_SYS1); + ipu_select_buffer(ADC_SYS1, IPU_INPUT_BUFFER, 0); + + if (ipu_adc_set_update_mode + (ADC_SYS1, IPU_ADC_AUTO_REFRESH_SNOOP, 30, + fbi->fix.smem_start, &memsize) < 0) + dev_err(fbi->device, "Error enabling auto refesh.\n"); + + mxc_fbi->snoop_window_size = memsize; + + break; + } + return ret_mode; +} + +/* + * Open the main framebuffer. + * + * @param fbi framebuffer information pointer + * + * @param user Set if opened by user or clear if opened by kernel + */ +static int mxcfb_open(struct fb_info *fbi, int user) +{ + int retval = 0; + struct mxcfb_info *mxc_fbi = fbi->par; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + mxc_fbi->open_count++; + + retval = mxcfb_blank(FB_BLANK_UNBLANK, fbi); + return retval; +} + +/* + * Close the main framebuffer. + * + * @param fbi framebuffer information pointer + * + * @param user Set if opened by user or clear if opened by kernel + */ +static int mxcfb_release(struct fb_info *fbi, int user) +{ + int retval = 0; + struct mxcfb_info *mxc_fbi = fbi->par; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + --mxc_fbi->open_count; + if (mxc_fbi->open_count == 0) { + retval = mxcfb_blank(FB_BLANK_POWERDOWN, fbi); + } + return retval; +} + +/* + * Set fixed framebuffer parameters based on variable settings. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par; + + /* Set framebuffer id to IPU display number. */ + strcpy(fix->id, "DISP0 FB"); + fix->id[4] = '0' + mxc_fbi->disp_num; + + /* Init settings based on the panel size */ + fix->line_length = MXCFB_SCREEN_WIDTH * var->bits_per_pixel / 8; + + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 0; + fix->ypanstep = 0; + + return 0; +} + +/* + * Set framebuffer parameters and change the operating mode. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_par(struct fb_info *fbi) +{ + int retval = 0; + int mode; + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + mode = mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, NULL); + + mxcfb_set_fix(fbi); + + if (mode != MXCFB_REFRESH_OFF) { +#ifdef PARTIAL_REFRESH + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_PARTIAL, NULL); +#else + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_AUTO, NULL); +#endif + } + return 0; +} + +/* + * Check framebuffer variable parameters and adjust to valid values. + * + * @param var framebuffer variable parameters + * + * @param info framebuffer information pointer + */ +static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) +{ + if (var->xres > MXCFB_SCREEN_WIDTH) + var->xres = MXCFB_SCREEN_WIDTH; + if (var->yres > MXCFB_SCREEN_HEIGHT) + var->yres = MXCFB_SCREEN_HEIGHT; + if (var->xres_virtual < var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16)) { + var->bits_per_pixel = default_bpp; + } + + switch (var->bits_per_pixel) { + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + var->height = -1; + var->width = -1; + var->grayscale = 0; + var->nonstd = 0; + + var->pixclock = -1; + var->left_margin = -1; + var->right_margin = -1; + var->upper_margin = -1; + var->lower_margin = -1; + var->hsync_len = -1; + var->vsync_len = -1; + + var->vmode = FB_VMODE_NONINTERLACED; + var->sync = 0; + + return 0; +} + +static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int +mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int trans, struct fb_info *fbi) +{ + unsigned int val; + int ret = 1; + + /* + * If greyscale is true, then we convert the RGB value + * to greyscale no matter what visual we are using. + */ + if (fbi->var.grayscale) + red = green = blue = (19595 * red + 38470 * green + + 7471 * blue) >> 16; + switch (fbi->fix.visual) { + case FB_VISUAL_TRUECOLOR: + /* + * 16-bit True Colour. We encode the RGB value + * according to the RGB bitfield information. + */ + if (regno < 16) { + u32 *pal = fbi->pseudo_palette; + + val = _chan_to_field(red, &fbi->var.red); + val |= _chan_to_field(green, &fbi->var.green); + val |= _chan_to_field(blue, &fbi->var.blue); + + pal[regno] = val; + ret = 0; + } + break; + + case FB_VISUAL_STATIC_PSEUDOCOLOR: + case FB_VISUAL_PSEUDOCOLOR: + break; + } + + return ret; +} + +/* + * mxcfb_blank(): + * Blank the display. + */ +static int mxcfb_blank(int blank, struct fb_info *fbi) +{ + int retval = 0; + struct mxcfb_info *mxc_fbi = fbi->par; + + dev_dbg(fbi->device, "blank = %d\n", blank); + + retval = wait_event_interruptible(mxcfb_drv_data.suspend_wq, + (mxcfb_drv_data.suspended == false)); + if (retval < 0) + return retval; + + mxc_fbi->blank = blank; + + switch (blank) { + case FB_BLANK_POWERDOWN: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, NULL); + break; + case FB_BLANK_UNBLANK: + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_DEFAULT, NULL); + break; + } + return 0; +} + +/*! + * This structure contains the pointers to the control functions that are + * invoked by the core framebuffer driver to perform operations like + * blitting, rectangle filling, copy regions and cursor definition. + */ +static struct fb_ops mxcfb_ops = { + .owner = THIS_MODULE, + .fb_open = mxcfb_open, + .fb_release = mxcfb_release, + .fb_set_par = mxcfb_set_par, + .fb_check_var = mxcfb_check_var, + .fb_setcolreg = mxcfb_setcolreg, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_blank = mxcfb_blank, +}; + +/*! + * Allocates the DRAM memory for the frame buffer. This buffer is remapped + * into a non-cached, non-buffered, memory region to allow palette and pixel + * writes to occur without flushing the cache. Once this area is remapped, + * all virtual memory access to the video memory should occur at the new region. + * + * @param fbi framebuffer information pointer + * + * @return Error code indicating success or failure + */ +static int mxcfb_map_video_memory(struct fb_info *fbi) +{ + u32 msb; + u32 offset; + struct mxcfb_info *mxcfbi = fbi->par; + + fbi->fix.smem_len = fbi->var.xres_virtual * fbi->var.yres_virtual * 4; + + /* Set size to power of 2. */ + msb = fls(fbi->fix.smem_len); + if (!(fbi->fix.smem_len & ((1UL << msb) - 1))) + msb--; /* Already aligned to power 2 */ + if (msb < 11) + msb = 11; + mxcfbi->alloc_size = (1UL << msb) * 2; + + mxcfbi->alloc_start_vaddr = dma_alloc_coherent(fbi->device, + mxcfbi->alloc_size, + &mxcfbi-> + alloc_start_paddr, + GFP_KERNEL | GFP_DMA); + + if (mxcfbi->alloc_start_vaddr == 0) { + dev_err(fbi->device, "Unable to allocate framebuffer memory\n"); + return -ENOMEM; + } + dev_dbg(fbi->device, "allocated fb memory @ paddr=0x%08X, size=%d.\n", + (uint32_t) mxcfbi->alloc_start_paddr, mxcfbi->alloc_size); + + offset = + ((mxcfbi->alloc_size / 2) - 1) & ~((mxcfbi->alloc_size / 2) - 1); + fbi->fix.smem_start = mxcfbi->alloc_start_paddr + offset; + dev_dbg(fbi->device, "aligned fb start @ paddr=0x%08lX, size=%u.\n", + fbi->fix.smem_start, fbi->fix.smem_len); + + fbi->screen_base = mxcfbi->alloc_start_vaddr + offset; + + /* Clear the screen */ + memset(fbi->screen_base, 0, fbi->fix.smem_len); + return 0; +} + +/*! + * De-allocates the DRAM memory for the frame buffer. + * + * @param fbi framebuffer information pointer + * + * @return Error code indicating success or failure + */ +static int mxcfb_unmap_video_memory(struct fb_info *fbi) +{ + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + dma_free_coherent(fbi->device, mxc_fbi->alloc_size, + mxc_fbi->alloc_start_vaddr, + mxc_fbi->alloc_start_paddr); + return 0; +} + +/*! + * Initializes the framebuffer information pointer. After allocating + * sufficient memory for the framebuffer structure, the fields are + * filled with custom information passed in from the configurable + * structures. This includes information such as bits per pixel, + * color maps, screen width/height and RGBA offsets. + * + * @return Framebuffer structure initialized with our information + */ +static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops) +{ + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + + /* + * Allocate sufficient memory for the fb structure + */ + fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev); + if (!fbi) + return NULL; + + mxcfbi = (struct mxcfb_info *)fbi->par; + + /* + * Fill in fb_info structure information + */ + fbi->var.xres = fbi->var.xres_virtual = MXCFB_SCREEN_WIDTH; + fbi->var.yres = fbi->var.yres_virtual = MXCFB_SCREEN_HEIGHT; + fbi->var.activate = FB_ACTIVATE_NOW; + mxcfb_check_var(&fbi->var, fbi); + + mxcfb_set_fix(fbi); + + fbi->fbops = ops; + fbi->flags = FBINFO_FLAG_DEFAULT; + fbi->pseudo_palette = mxcfbi->pseudo_palette; + + /* + * Allocate colormap + */ + fb_alloc_cmap(&fbi->cmap, 16, 0); + + return fbi; +} + +/*! + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxcfb_probe(struct platform_device *pdev) +{ + struct fb_info *fbi; + struct mxcfb_info *mxc_fbi; + int ret; + + platform_set_drvdata(pdev, &mxcfb_drv_data); + + /* + * Initialize FB structures + */ + fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops); + if (!fbi) { + ret = -ENOMEM; + goto err0; + } + mxcfb_drv_data.fbi = fbi; + mxc_fbi = fbi->par; + + mxcfb_drv_data.suspended = false; + init_waitqueue_head(&mxcfb_drv_data.suspend_wq); + + /* + * Allocate memory + */ + ret = mxcfb_map_video_memory(fbi); + if (ret < 0) { + goto err1; + } + + mxcfb_init_panel(fbi); + + /* + * Register framebuffer + */ + ret = register_framebuffer(fbi); + if (ret < 0) { + goto err2; + } + + dev_info(&pdev->dev, "%s registered\n", MXCFB_NAME); + + return 0; + + err2: + mxcfb_unmap_video_memory(fbi); + err1: + if (&fbi->cmap) + fb_dealloc_cmap(&fbi->cmap); + framebuffer_release(fbi); + err0: + return ret; +} + +#ifdef CONFIG_PM +/*! + * Power management hooks. Note that we won't be called from IRQ context, + * unlike the blank functions above, so we may sleep. + */ + +/*! + * Suspends the framebuffer and blanks the screen. Power management support + * + * @param pdev pointer to device structure. + * @param state state of the device. + * + * @return success + */ +static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mxcfb_data *drv_data = platform_get_drvdata(pdev); + struct fb_info *fbi = drv_data->fbi; + struct mxcfb_info *mxc_fbi = fbi->par; + + drv_data->suspended = true; + + if (mxc_fbi->blank == FB_BLANK_UNBLANK) + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_OFF, NULL); + /* Display OFF */ + ipu_adc_write_cmd(mxc_fbi->disp_num, CMD, DISOFF, 0, 0); + + return 0; +} + +/*! + * Resumes the framebuffer and unblanks the screen. Power management support + * + * @param pdev pointer to device structure. + * + * @return success + */ +static int mxcfb_resume(struct platform_device *pdev) +{ + struct mxcfb_data *drv_data = platform_get_drvdata(pdev); + struct fb_info *fbi = drv_data->fbi; + struct mxcfb_info *mxc_fbi = fbi->par; + + /* Display ON */ + ipu_adc_write_cmd(mxc_fbi->disp_num, CMD, DISON, 0, 0); + drv_data->suspended = false; + + if (mxc_fbi->blank == FB_BLANK_UNBLANK) + mxcfb_set_refresh_mode(fbi, MXCFB_REFRESH_DEFAULT, NULL); + wake_up_interruptible(&drv_data->suspend_wq); + + return 0; +} +#else +#define mxcfb_suspend NULL +#define mxcfb_resume NULL +#endif + +/*! + * This structure contains pointers to the power management callback functions. + */ +static struct platform_driver mxcfb_driver = { + .driver = { + .name = MXCFB_NAME, + }, + .probe = mxcfb_probe, + .suspend = mxcfb_suspend, + .resume = mxcfb_resume, +}; + +/*! + * Device definition for the Framebuffer + */ +static struct platform_device mxcfb_device = { + .name = MXCFB_NAME, + .id = 0, + .dev = { + .coherent_dma_mask = 0xFFFFFFFF, + } +}; + +/*! + * Main entry function for the framebuffer. The function registers the power + * management callback functions with the kernel and also registers the MXCFB + * callback functions with the core Linux framebuffer driver \b fbmem.c + * + * @return Error code indicating success or failure + */ +static int mxcfb_init(void) +{ + int ret = 0; + + ret = platform_driver_register(&mxcfb_driver); + if (ret == 0) { + ret = platform_device_register(&mxcfb_device); + if (ret != 0) { + platform_driver_unregister(&mxcfb_driver); + } + } + return ret; +} + +static void mxcfb_exit(void) +{ + struct fb_info *fbi = dev_get_drvdata(&mxcfb_device.dev); + + if (fbi) { + mxcfb_unmap_video_memory(fbi); + + if (&fbi->cmap) + fb_dealloc_cmap(&fbi->cmap); + + unregister_framebuffer(fbi); + framebuffer_release(fbi); + } + + platform_device_unregister(&mxcfb_device); + platform_driver_unregister(&mxcfb_driver); +} + +module_init(mxcfb_init); +module_exit(mxcfb_exit); + +EXPORT_SYMBOL(mxcfb_set_refresh_mode); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC Epson framebuffer driver"); +MODULE_SUPPORTED_DEVICE("fb"); diff --git a/drivers/video/mxc/mxcfb_epson_vga.c b/drivers/video/mxc/mxcfb_epson_vga.c new file mode 100644 index 000000000000..8b5ea1a945d4 --- /dev/null +++ b/drivers/video/mxc/mxcfb_epson_vga.c @@ -0,0 +1,362 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxcfb_epson_vga.c + * + * @brief MXC Frame buffer driver for SDC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct spi_device *lcd_spi; +static struct device *lcd_dev; + +static void lcd_init(void); +static void lcd_poweron(void); +static void lcd_poweroff(void); + +static void (*lcd_reset) (void); +static struct regulator *io_reg; +static struct regulator *core_reg; + +static struct fb_videomode video_modes[] = { + { + /* 480x640 @ 60 Hz */ + "Epson-VGA", 60, 480, 640, 41701, 60, 41, 10, 5, 20, 10, + 0, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static void lcd_init_fb(struct fb_info *info) +{ + struct fb_var_screeninfo var; + + memset(&var, 0, sizeof(var)); + + fb_videomode_to_var(&var, &video_modes[0]); + + if (machine_is_mx31_3ds()) { + var.upper_margin = 0; + var.left_margin = 0; + } + + var.activate = FB_ACTIVATE_ALL; + var.yres_virtual = var.yres * 3; + + acquire_console_sem(); + info->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(info, &var); + info->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); +} + +static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + + if (strcmp(event->info->fix.id, "DISP3 BG")) { + return 0; + } + + switch (val) { + case FB_EVENT_FB_REGISTERED: + lcd_init_fb(event->info); + lcd_poweron(); + break; + case FB_EVENT_BLANK: + if ((event->info->var.xres != 480) || + (event->info->var.yres != 640)) { + break; + } + if (*((int *)event->data) == FB_BLANK_UNBLANK) { + lcd_poweron(); + } else { + lcd_poweroff(); + } + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = lcd_fb_event, +}; + +/*! + * This function is called whenever the SPI slave device is detected. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit lcd_probe(struct device *dev) +{ + int i; + struct mxc_lcd_platform_data *plat = dev->platform_data; + + lcd_dev = dev; + + if (plat) { + io_reg = regulator_get(dev, plat->io_reg); + if (!IS_ERR(io_reg)) { + regulator_set_voltage(io_reg, 1800000, 1800000); + regulator_enable(io_reg); + } + core_reg = regulator_get(dev, plat->core_reg); + if (!IS_ERR(core_reg)) { + regulator_set_voltage(core_reg, 2800000, 2800000); + regulator_enable(core_reg); + } + + lcd_reset = plat->reset; + if (lcd_reset) + lcd_reset(); + } + + lcd_init(); + + for (i = 0; i < num_registered_fb; i++) { + if (strcmp(registered_fb[i]->fix.id, "DISP3 BG") == 0) { + lcd_init_fb(registered_fb[i]); + fb_show_logo(registered_fb[i], 0); + lcd_poweron(); + } + } + + fb_register_client(&nb); + + return 0; +} + +static int __devinit lcd_plat_probe(struct platform_device *pdev) +{ + ipu_adc_sig_cfg_t sig; + ipu_channel_params_t param; + + memset(&sig, 0, sizeof(sig)); + sig.ifc_width = 9; + sig.clk_pol = 1; + ipu_init_async_panel(0, IPU_PANEL_SERIAL, 90, IPU_PIX_FMT_GENERIC, sig); + + memset(¶m, 0, sizeof(param)); + ipu_init_channel(DIRECT_ASYNC1, ¶m); + + return lcd_probe(&pdev->dev); +} + +static int __devinit lcd_spi_probe(struct spi_device *spi) +{ + lcd_spi = spi; + + spi->bits_per_word = 9; + spi_setup(spi); + + return lcd_probe(&spi->dev); +} + +static int __devexit lcd_remove(struct device *dev) +{ + fb_unregister_client(&nb); + lcd_poweroff(); + regulator_put(io_reg); + regulator_put(core_reg); + + return 0; +} + +static int __devexit lcd_spi_remove(struct spi_device *spi) +{ + int ret = lcd_remove(&spi->dev); + lcd_spi = NULL; + return ret; +} + +static int __devexit lcd_plat_remove(struct platform_device *pdev) +{ + return lcd_remove(&pdev->dev); +} + +static int lcd_suspend(struct spi_device *spi, pm_message_t message) +{ + lcd_poweroff(); + return 0; +} + +static int lcd_resume(struct spi_device *spi) +{ + if (lcd_reset) + lcd_reset(); + + lcd_init(); + lcd_poweron(); + return 0; +} + +/*! + * spi driver structure for LTV350QV + */ +static struct spi_driver lcd_spi_dev_driver = { + + .driver = { + .name = "lcd_spi", + .owner = THIS_MODULE, + }, + .probe = lcd_spi_probe, + .remove = __devexit_p(lcd_spi_remove), + .suspend = lcd_suspend, + .resume = lcd_resume, +}; + +static struct platform_driver lcd_plat_driver = { + .driver = { + .name = "lcd_spi", + .owner = THIS_MODULE, + }, + .probe = lcd_plat_probe, + .remove = __devexit_p(lcd_plat_remove), +}; + +#define param(x) ((x) | 0x100) + +/* + * Send init commands to L4F00242T03 + * + */ +static void lcd_init(void) +{ + const u16 cmd[] = { 0x36, param(0), 0x3A, param(0x60) }; + + dev_dbg(lcd_dev, "initializing LCD\n"); + if (lcd_spi) { + spi_write(lcd_spi, (const u8 *)cmd, ARRAY_SIZE(cmd)); + } else { + ipu_disp_direct_write(DIRECT_ASYNC1, 0x36, 0); + ipu_disp_direct_write(DIRECT_ASYNC1, 0x100, 0); + ipu_disp_direct_write(DIRECT_ASYNC1, 0x3A, 0); + ipu_disp_direct_write(DIRECT_ASYNC1, 0x160, 0); + msleep(1); + ipu_uninit_channel(DIRECT_ASYNC1); + } +} + +static int lcd_on; +/* + * Send Power On commands to L4F00242T03 + * + */ +static void lcd_poweron(void) +{ + const u16 slpout = 0x11; + const u16 dison = 0x29; + ipu_channel_params_t param; + if (lcd_on) + return; + + dev_dbg(lcd_dev, "turning on LCD\n"); + + if (lcd_spi) { + msleep(60); + spi_write(lcd_spi, (const u8 *)&slpout, 1); + msleep(60); + spi_write(lcd_spi, (const u8 *)&dison, 1); + } else { + memset(¶m, 0, sizeof(param)); + ipu_init_channel(DIRECT_ASYNC1, ¶m); + ipu_disp_direct_write(DIRECT_ASYNC1, slpout, 0); + msleep(60); + ipu_disp_direct_write(DIRECT_ASYNC1, dison, 0); + msleep(1); + ipu_uninit_channel(DIRECT_ASYNC1); + } + lcd_on = 1; +} + +/* + * Send Power Off commands to L4F00242T03 + * + */ +static void lcd_poweroff(void) +{ + const u16 slpin = 0x10; + const u16 disoff = 0x28; + ipu_channel_params_t param; + if (!lcd_on) + return; + + dev_dbg(lcd_dev, "turning off LCD\n"); + + if (lcd_spi) { + msleep(60); + spi_write(lcd_spi, (const u8 *)&disoff, 1); + msleep(60); + spi_write(lcd_spi, (const u8 *)&slpin, 1); + } else { + memset(¶m, 0, sizeof(param)); + ipu_init_channel(DIRECT_ASYNC1, ¶m); + ipu_disp_direct_write(DIRECT_ASYNC1, disoff, 0); + msleep(60); + ipu_disp_direct_write(DIRECT_ASYNC1, slpin, 0); + msleep(1); + ipu_uninit_channel(DIRECT_ASYNC1); + } + lcd_on = 0; +} + +static int __init epson_lcd_init(void) +{ + int ret; + + ret = platform_driver_register(&lcd_plat_driver); + if (ret) + return ret; + + return spi_register_driver(&lcd_spi_dev_driver); + +} + +static void __exit epson_lcd_exit(void) +{ + spi_unregister_driver(&lcd_spi_dev_driver); +} + +module_init(epson_lcd_init); +module_exit(epson_lcd_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Epson VGA LCD init driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/mxcfb_modedb.c b/drivers/video/mxc/mxcfb_modedb.c new file mode 100644 index 000000000000..2e73560c44b9 --- /dev/null +++ b/drivers/video/mxc/mxcfb_modedb.c @@ -0,0 +1,69 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include + +struct fb_videomode mxcfb_modedb[] = { + { + /* 240x320 @ 60 Hz */ + "Sharp-QVGA", 60, 240, 320, 185925, 9, 16, 7, 9, 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | + FB_SYNC_DATA_INVERT | FB_SYNC_CLK_IDLE_EN, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 240x33 @ 60 Hz */ + "Sharp-CLI", 60, 240, 33, 185925, 9, 16, 7, 9 + 287, 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | + FB_SYNC_DATA_INVERT | FB_SYNC_CLK_IDLE_EN, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 640x480 @ 60 Hz */ + "NEC-VGA", 60, 640, 480, 38255, 144, 0, 34, 40, 1, 1, + FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 640x480 @ 60 Hz */ + "CPT-VGA", 60, 640, 480, 39683, 45, 114, 33, 11, 1, 1, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* NTSC TV output */ + "TV-NTSC", 60, 640, 480, 37538, + 38, 858 - 640 - 38 - 3, + 36, 518 - 480 - 36 - 1, + 3, 1, + 0, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* PAL TV output */ + "TV-PAL", 50, 640, 480, 37538, + 38, 960 - 640 - 38 - 32, + 32, 555 - 480 - 32 - 3, + 32, 3, + 0, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* TV output VGA mode, 640x480 @ 65 Hz */ + "TV-VGA", 60, 640, 480, 40574, 35, 45, 9, 1, 46, 5, + 0, FB_VMODE_NONINTERLACED, 0, + }, +}; + +int mxcfb_modedb_sz = ARRAY_SIZE(mxcfb_modedb); diff --git a/drivers/video/mxc/mxcfb_seiko_wvga.c b/drivers/video/mxc/mxcfb_seiko_wvga.c new file mode 100644 index 000000000000..9b3e9fddafe7 --- /dev/null +++ b/drivers/video/mxc/mxcfb_seiko_wvga.c @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @defgroup Framebuffer Framebuffer Driver for SDC and ADC. + */ + +/*! + * @file mxcfb_seiko_wvga.c + * + * @brief MXC Frame buffer driver for SDC + * + * @ingroup Framebuffer + */ + +/*! + * Include files + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void lcd_poweron(void); +static void lcd_poweroff(void); + +static struct platform_device *plcd_dev; +static struct regulator *io_reg; +static struct regulator *core_reg; +static int lcd_on; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 32MHz */ + "SEIKO-WVGA", 60, 800, 480, 29850, 99, 164, 33, 10, 10, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static void lcd_init_fb(struct fb_info *info) +{ + struct fb_var_screeninfo var; + + memset(&var, 0, sizeof(var)); + + fb_videomode_to_var(&var, &video_modes[0]); + + var.activate = FB_ACTIVATE_ALL; + var.yres_virtual = var.yres * 3; + + acquire_console_sem(); + info->flags |= FBINFO_MISC_USEREVENT; + fb_set_var(info, &var); + info->flags &= ~FBINFO_MISC_USEREVENT; + release_console_sem(); +} + +static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + + if (strcmp(event->info->fix.id, "mxc_elcdif_fb")) + return 0; + + switch (val) { + case FB_EVENT_FB_REGISTERED: + lcd_init_fb(event->info); + fb_show_logo(event->info, 0); + lcd_poweron(); + break; + case FB_EVENT_BLANK: + if ((event->info->var.xres != 800) || + (event->info->var.yres != 480)) { + break; + } + if (*((int *)event->data) == FB_BLANK_UNBLANK) + lcd_poweron(); + else + lcd_poweroff(); + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = lcd_fb_event, +}; + +/*! + * This function is called whenever the platform device is detected. + * + * @param pdev the platform device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit lcd_probe(struct platform_device *pdev) +{ + int i; + struct mxc_lcd_platform_data *plat = pdev->dev.platform_data; + + if (plat) { + if (plat->reset) + plat->reset(); + + io_reg = regulator_get(&pdev->dev, plat->io_reg); + if (IS_ERR(io_reg)) + io_reg = NULL; + core_reg = regulator_get(&pdev->dev, plat->core_reg); + if (!IS_ERR(core_reg)) + regulator_set_voltage(io_reg, 1800000, 1800000); + else + core_reg = NULL; + } + + for (i = 0; i < num_registered_fb; i++) { + if (strcmp(registered_fb[i]->fix.id, "mxc_elcdif_fb") == 0) { + lcd_init_fb(registered_fb[i]); + fb_show_logo(registered_fb[i], 0); + lcd_poweron(); + } + } + + fb_register_client(&nb); + + plcd_dev = pdev; + + return 0; +} + +static int __devexit lcd_remove(struct platform_device *pdev) +{ + fb_unregister_client(&nb); + lcd_poweroff(); + if (io_reg) + regulator_put(io_reg); + if (core_reg) + regulator_put(core_reg); + + return 0; +} + +#ifdef CONFIG_PM +static int lcd_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int lcd_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define lcd_suspend NULL +#define lcd_resume NULL +#endif + +/*! + * platform driver structure for SEIKO WVGA + */ +static struct platform_driver lcd_driver = { + .driver = { + .name = "lcd_seiko"}, + .probe = lcd_probe, + .remove = __devexit_p(lcd_remove), + .suspend = lcd_suspend, + .resume = lcd_resume, +}; + +/* + * Send Power + * + */ +static void lcd_poweron(void) +{ + if (lcd_on) + return; + + dev_dbg(&plcd_dev->dev, "turning on LCD\n"); + if (core_reg) + regulator_enable(core_reg); + if (io_reg) + regulator_enable(io_reg); + lcd_on = 1; +} + +/* + * Send Power Off + * + */ +static void lcd_poweroff(void) +{ + lcd_on = 0; + dev_dbg(&plcd_dev->dev, "turning off LCD\n"); + if (io_reg) + regulator_disable(io_reg); + if (core_reg) + regulator_disable(core_reg); +} + +static int __init seiko_wvga_lcd_init(void) +{ + return platform_driver_register(&lcd_driver); +} + +static void __exit seiko_wvga_lcd_exit(void) +{ + platform_driver_unregister(&lcd_driver); +} + +module_init(seiko_wvga_lcd_init); +module_exit(seiko_wvga_lcd_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("SEIKO WVGA LCD init driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxc/tve.c b/drivers/video/mxc/tve.c new file mode 100644 index 000000000000..2bb532f638cf --- /dev/null +++ b/drivers/video/mxc/tve.c @@ -0,0 +1,1289 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file tve.c + * @brief Driver for i.MX TV encoder + * + * @ingroup Framebuffer + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TVE_ENABLE (1UL) +#define TVE_DAC_FULL_RATE (0UL<<1) +#define TVE_DAC_DIV2_RATE (1UL<<1) +#define TVE_DAC_DIV4_RATE (2UL<<1) +#define TVE_IPU_CLK_ENABLE (1UL<<3) + +#define CD_LM_INT 0x00000001 +#define CD_SM_INT 0x00000002 +#define CD_MON_END_INT 0x00000004 +#define CD_CH_0_LM_ST 0x00000001 +#define CD_CH_0_SM_ST 0x00000010 +#define CD_CH_1_LM_ST 0x00000002 +#define CD_CH_1_SM_ST 0x00000020 +#define CD_CH_2_LM_ST 0x00000004 +#define CD_CH_2_SM_ST 0x00000040 +#define CD_MAN_TRIG 0x00000100 + +#define TVE_STAND_MASK (0x0F<<8) +#define TVE_NTSC_STAND (0UL<<8) +#define TVE_PAL_STAND (3UL<<8) +#define TVE_HD720P60_STAND (4UL<<8) +#define TVE_HD720P50_STAND (5UL<<8) +#define TVE_HD720P30_STAND (6UL<<8) +#define TVE_HD720P25_STAND (7UL<<8) +#define TVE_HD720P24_STAND (8UL<<8) +#define TVE_HD1080I60_STAND (9UL<<8) +#define TVE_HD1080I50_STAND (10UL<<8) +#define TVE_HD1035I60_STAND (11UL<<8) +#define TVE_HD1080P30_STAND (12UL<<8) +#define TVE_HD1080P25_STAND (13UL<<8) +#define TVE_HD1080P24_STAND (14UL<<8) +#define TVE_DAC_SAMPRATE_MASK (0x3<<1) +#define TVEV2_DATA_SRC_MASK (0x3<<4) + +#define TVEV2_DATA_SRC_BUS_1 (0UL<<4) +#define TVEV2_DATA_SRC_BUS_2 (1UL<<4) +#define TVEV2_DATA_SRC_EXT (2UL<<4) + +#define TVEV2_INP_VIDEO_FORM (1UL<<6) +#define TVEV2_P2I_CONV_EN (1UL<<7) + +#define TVEV2_DAC_GAIN_MASK 0x3F +#define TVEV2_DAC_TEST_MODE_MASK 0x7 + +#define TVOUT_FMT_OFF 0 +#define TVOUT_FMT_NTSC 1 +#define TVOUT_FMT_PAL 2 +#define TVOUT_FMT_720P60 3 +#define TVOUT_FMT_720P30 4 +#define TVOUT_FMT_1080I60 5 +#define TVOUT_FMT_1080I50 6 +#define TVOUT_FMT_1080P30 7 +#define TVOUT_FMT_1080P25 8 +#define TVOUT_FMT_1080P24 9 +#define TVOUT_FMT_VGA_SVGA 10 +#define TVOUT_FMT_VGA_XGA 11 +#define TVOUT_FMT_VGA_SXGA 12 +#define TVOUT_FMT_VGA_WSXGA 13 + +#define IPU_DISP_PORT 1 + +static int enabled; /* enable power on or not */ +DEFINE_SPINLOCK(tve_lock); + +static struct fb_info *tve_fbi; +static bool g_enable_tve; +static bool g_enable_vga; + +struct tve_data { + struct platform_device *pdev; + int revision; + int cur_mode; + int output_mode; + int detect; + void *base; + int irq; + int blank; + struct clk *clk; + struct clk *di_clk; + struct regulator *dac_reg; + struct regulator *dig_reg; + struct delayed_work cd_work; +} tve; + +struct tve_reg_mapping { + u32 tve_com_conf_reg; + u32 tve_cd_cont_reg; + u32 tve_int_cont_reg; + u32 tve_stat_reg; + u32 tve_mv_cont_reg; + u32 tve_tvdac_cont_reg; + u32 tve_tst_mode_reg; +}; + +struct tve_reg_fields_mapping { + u32 cd_en; + u32 cd_trig_mode; + u32 cd_lm_int; + u32 cd_sm_int; + u32 cd_mon_end_int; + u32 cd_man_trig; + u32 sync_ch_mask; + u32 tvout_mode_mask; + u32 sync_ch_offset; + u32 tvout_mode_offset; + u32 cd_ch_stat_offset; +}; + +static struct tve_reg_mapping tve_regs_v1 = { + 0, 0x14, 0x28, 0x2C, 0x48, 0x08, 0x30 +}; + +static struct tve_reg_fields_mapping tve_reg_fields_v1 = { + 1, 2, 1, 2, 4, 0x00010000, 0x7000, 0x70, 12, 4, 8 +}; + +static struct tve_reg_mapping tve_regs_v2 = { + 0, 0x34, 0x64, 0x68, 0xDC, 0x28, 0x6c +}; + +static struct tve_reg_fields_mapping tve_reg_fields_v2 = { + 1, 2, 1, 2, 4, 0x01000000, 0x700000, 0x7000, 20, 12, 16 +}; + + +struct tve_reg_mapping *tve_regs; +struct tve_reg_fields_mapping *tve_reg_fields; + +/* For MX37 need modify some fields in tve_probe */ +static struct fb_videomode video_modes[] = { + { + /* NTSC TV output */ + "TV-NTSC", 60, 720, 480, 74074, + 122, 15, + 18, 26, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_INTERLACED, + FB_MODE_IS_DETAILED,}, + { + /* PAL TV output */ + "TV-PAL", 50, 720, 576, 74074, + 132, 11, + 22, 26, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST, + FB_MODE_IS_DETAILED,}, + { + /* 720p60 TV output */ + "TV-720P60", 60, 1280, 720, 13468, + 260, 109, + 25, 4, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, + { + /* 720p30 TV output */ + "TV-720P30", 30, 1280, 720, 13468, + 260, 1759, + 25, 4, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, + { + /* 1080i60 TV output */ + "TV-1080I60", 60, 1920, 1080, 13468, + 192, 87, + 20, 24, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST, + FB_MODE_IS_DETAILED,}, + { + /* 1080i50 TV output */ + "TV-1080I50", 50, 1920, 1080, 13468, + 192, 527, + 20, 24, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST, + FB_MODE_IS_DETAILED,}, + { + /* 1080p30 TV output */ + "TV-1080P30", 30, 1920, 1080, 13468, + 192, 87, + 38, 6, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, + { + /* 1080p25 TV output */ + "TV-1080P25", 25, 1920, 1080, 13468, + 192, 527, + 38, 6, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, + { + /* 1080p24 TV output */ + "TV-1080P24", 24, 1920, 1080, 13468, + 192, 637, + 38, 6, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, +}; + +static struct fb_videomode video_modes_vga[] = { + { + /* VGA 800x600 40M pixel clk output */ + "VGA-SVGA", 60, 800, 600, 25000, + 215, 28, + 24, 2, + 13, 2, + 0, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, + { + /* VGA 1024x768 65M pixel clk output */ + "VGA-XGA", 60, 1024, 768, 15384, + 160, 24, + 29, 3, + 136, 6, + 0, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, + { + /* VGA 1280x1024 108M pixel clk output */ + "VGA-SXGA", 60, 1280, 1024, 9259, + 358, 38, + 38, 2, + 12, 2, + 0, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, + { + /* VGA 1680x1050 294M pixel clk output */ + "VGA-WSXGA+", 60, 1680, 1050, 6796, + 288, 104, + 33, 2, + 184, 2, + 0, + FB_VMODE_NONINTERLACED, + FB_MODE_IS_DETAILED,}, +}; + +enum tvout_mode { + TV_OFF, + CVBS0, + CVBS2, + CVBS02, + SVIDEO, + SVIDEO_CVBS, + YPBPR, + TVRGB +}; + +static unsigned short tvout_mode_to_channel_map[8] = { + 0, /* TV_OFF */ + 1, /* CVBS0 */ + 4, /* CVBS2 */ + 5, /* CVBS02 */ + 1, /* SVIDEO */ + 5, /* SVIDEO_CVBS */ + 1, /* YPBPR */ + 7 /* TVRGB */ +}; + +static void tve_dump_regs(void) +{ + dev_dbg(&tve.pdev->dev, "tve_com_conf_reg 0x%x\n", + __raw_readl(tve.base + tve_regs->tve_com_conf_reg)); + dev_dbg(&tve.pdev->dev, "tve_cd_cont_reg 0x%x\n", + __raw_readl(tve.base + tve_regs->tve_cd_cont_reg)); + dev_dbg(&tve.pdev->dev, "tve_int_cont_reg 0x%x\n", + __raw_readl(tve.base + tve_regs->tve_int_cont_reg)); + dev_dbg(&tve.pdev->dev, "tve_tst_mode_reg 0x%x\n", + __raw_readl(tve.base + tve_regs->tve_tst_mode_reg)); + dev_dbg(&tve.pdev->dev, "tve_tvdac_cont_reg0 0x%x\n", + __raw_readl(tve.base + tve_regs->tve_tvdac_cont_reg)); + dev_dbg(&tve.pdev->dev, "tve_tvdac_cont_reg1 0x%x\n", + __raw_readl(tve.base + tve_regs->tve_tvdac_cont_reg + 4)); + dev_dbg(&tve.pdev->dev, "tve_tvdac_cont_reg2 0x%x\n", + __raw_readl(tve.base + tve_regs->tve_tvdac_cont_reg + 8)); +} + +static int is_vga_enabled(void) +{ + u32 reg; + + if (tve.revision == 2) { + reg = __raw_readl(tve.base + tve_regs->tve_tst_mode_reg); + if (reg & TVEV2_DAC_TEST_MODE_MASK) + return 1; + else + return 0; + } + return 0; +} + +static int inline is_vga_mode(int mode) +{ + return ((mode == TVOUT_FMT_VGA_SVGA) + || (mode == TVOUT_FMT_VGA_XGA) + || (mode == TVOUT_FMT_VGA_SXGA) + || (mode == TVOUT_FMT_VGA_WSXGA)); +} + +static int inline valid_mode(int mode) +{ + return (is_vga_mode(mode) + || (mode == TVOUT_FMT_NTSC) + || (mode == TVOUT_FMT_PAL) + || (mode == TVOUT_FMT_720P30) + || (mode == TVOUT_FMT_720P60) + || (mode == TVOUT_FMT_1080I50) + || (mode == TVOUT_FMT_1080I60) + || (mode == TVOUT_FMT_1080P24) + || (mode == TVOUT_FMT_1080P25) + || (mode == TVOUT_FMT_1080P30)); +} + +static int get_video_mode(struct fb_info *fbi, int *fmt) +{ + int mode; + + if (fb_mode_is_equal(fbi->mode, &video_modes[0])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_NTSC; + } else if (fb_mode_is_equal(fbi->mode, &video_modes[1])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_PAL; + } else if (fb_mode_is_equal(fbi->mode, &video_modes[2])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_720P60; + } else if (fb_mode_is_equal(fbi->mode, &video_modes[3])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_720P30; + } else if (fb_mode_is_equal(fbi->mode, &video_modes[4])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_1080I60; + } else if (fb_mode_is_equal(fbi->mode, &video_modes[5])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_1080I50; + } else if (fb_mode_is_equal(fbi->mode, &video_modes[6])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_1080P30; + } else if (fb_mode_is_equal(fbi->mode, &video_modes[7])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_1080P25; + } else if (fb_mode_is_equal(fbi->mode, &video_modes[8])) { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_1080P24; + } else if (fb_mode_is_equal(fbi->mode, &video_modes_vga[0])) { + *fmt = IPU_PIX_FMT_GBR24; + mode = TVOUT_FMT_VGA_SVGA; + } else if (fb_mode_is_equal(fbi->mode, &video_modes_vga[1])) { + *fmt = IPU_PIX_FMT_GBR24; + mode = TVOUT_FMT_VGA_XGA; + } else if (fb_mode_is_equal(fbi->mode, &video_modes_vga[2])) { + *fmt = IPU_PIX_FMT_GBR24; + mode = TVOUT_FMT_VGA_SXGA; + } else if (fb_mode_is_equal(fbi->mode, &video_modes_vga[3])) { + *fmt = IPU_PIX_FMT_GBR24; + mode = TVOUT_FMT_VGA_WSXGA; + } else { + *fmt = IPU_PIX_FMT_YUV444; + mode = TVOUT_FMT_OFF; + } + return mode; +} + +static void tve_disable_vga_mode(void) +{ + if (tve.revision == 2) { + u32 reg; + /* disable test mode */ + reg = __raw_readl(tve.base + tve_regs->tve_tst_mode_reg); + reg = reg & ~TVEV2_DAC_TEST_MODE_MASK; + __raw_writel(reg, tve.base + tve_regs->tve_tst_mode_reg); + } +} + +static void tve_set_tvout_mode(int mode) +{ + u32 conf_reg; + + /* clear sync_ch and tvout_mode fields */ + conf_reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + conf_reg &= ~(tve_reg_fields->sync_ch_mask | + tve_reg_fields->tvout_mode_mask); + + conf_reg = conf_reg & ~TVE_DAC_SAMPRATE_MASK; + if (tve.revision == 2) { + conf_reg = (conf_reg & ~TVEV2_DATA_SRC_MASK) | + TVEV2_DATA_SRC_BUS_1; + conf_reg = conf_reg & ~TVEV2_INP_VIDEO_FORM; + conf_reg = conf_reg & ~TVEV2_P2I_CONV_EN; + } + + conf_reg |= + mode << tve_reg_fields-> + tvout_mode_offset | tvout_mode_to_channel_map[mode] << + tve_reg_fields->sync_ch_offset; + __raw_writel(conf_reg, tve.base + tve_regs->tve_com_conf_reg); +} + +static int _is_tvout_mode_hd_compatible(void) +{ + u32 conf_reg, mode; + + conf_reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + mode = (conf_reg >> tve_reg_fields->tvout_mode_offset) & 7; + if (mode == YPBPR || mode == TVRGB) { + return 1; + } else { + return 0; + } +} + +static int tve_setup_vga(void) +{ + u32 reg; + + if (tve.revision == 2) { + /* set gain */ + reg = __raw_readl(tve.base + tve_regs->tve_tvdac_cont_reg); + reg = (reg & ~TVEV2_DAC_GAIN_MASK) | 0; + __raw_writel(reg, tve.base + tve_regs->tve_tvdac_cont_reg); + reg = __raw_readl(tve.base + tve_regs->tve_tvdac_cont_reg + 4); + reg = (reg & ~TVEV2_DAC_GAIN_MASK) | 0; + __raw_writel(reg, tve.base + tve_regs->tve_tvdac_cont_reg + 4); + reg = __raw_readl(tve.base + tve_regs->tve_tvdac_cont_reg + 8); + reg = (reg & ~TVEV2_DAC_GAIN_MASK) | 0; + __raw_writel(reg, tve.base + tve_regs->tve_tvdac_cont_reg + 8); + + /* set tve_com_conf_reg */ + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_DAC_SAMPRATE_MASK) | TVE_DAC_DIV2_RATE; + reg = (reg & ~TVEV2_DATA_SRC_MASK) | TVEV2_DATA_SRC_BUS_2; + reg = reg | TVEV2_INP_VIDEO_FORM; + reg = reg & ~TVEV2_P2I_CONV_EN; + reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080P30_STAND; + reg |= TVRGB << tve_reg_fields->tvout_mode_offset | + 1 << tve_reg_fields->sync_ch_offset; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + + /* set test mode */ + reg = __raw_readl(tve.base + tve_regs->tve_tst_mode_reg); + reg = (reg & ~TVEV2_DAC_TEST_MODE_MASK) | 1; + __raw_writel(reg, tve.base + tve_regs->tve_tst_mode_reg); + } + + return 0; +} + +/** + * tve_setup + * initial the CH7024 chipset by setting register + * @param: + * vos: output video format + * @return: + * 0 successful + * otherwise failed + */ +static int tve_setup(int mode) +{ + u32 reg; + struct clk *tve_parent_clk; + unsigned long parent_clock_rate = 216000000, di1_clock_rate = 27000000; + unsigned long tve_clock_rate = 216000000; + unsigned long lock_flags; + + if (tve.cur_mode == mode) + return 0; + + spin_lock_irqsave(&tve_lock, lock_flags); + + switch (mode) { + case TVOUT_FMT_PAL: + case TVOUT_FMT_NTSC: + parent_clock_rate = 216000000; + di1_clock_rate = 27000000; + break; + case TVOUT_FMT_720P60: + case TVOUT_FMT_1080I60: + case TVOUT_FMT_1080I50: + case TVOUT_FMT_720P30: + case TVOUT_FMT_1080P30: + case TVOUT_FMT_1080P25: + case TVOUT_FMT_1080P24: + parent_clock_rate = 297000000; + tve_clock_rate = 297000000; + di1_clock_rate = 74250000; + break; + case TVOUT_FMT_VGA_SVGA: + parent_clock_rate = 160000000; + tve_clock_rate = 80000000; + di1_clock_rate = 40000000; + break; + case TVOUT_FMT_VGA_XGA: + parent_clock_rate = 520000000; + tve_clock_rate = 130000000; + di1_clock_rate = 65000000; + break; + case TVOUT_FMT_VGA_SXGA: + parent_clock_rate = 864000000; + tve_clock_rate = 216000000; + di1_clock_rate = 108000000; + break; + case TVOUT_FMT_VGA_WSXGA: + parent_clock_rate = 588560000; + tve_clock_rate = 294280000; + di1_clock_rate = 147140000; + break; + } + if (enabled) + clk_disable(tve.clk); + + tve_parent_clk = clk_get_parent(tve.clk); + + clk_set_rate(tve_parent_clk, parent_clock_rate); + + tve_clock_rate = clk_round_rate(tve.clk, tve_clock_rate); + clk_set_rate(tve.clk, tve_clock_rate); + + clk_enable(tve.clk); + di1_clock_rate = clk_round_rate(tve.di_clk, di1_clock_rate); + clk_set_rate(tve.di_clk, di1_clock_rate); + + tve.cur_mode = mode; + + /* select output video format */ + if (mode == TVOUT_FMT_PAL) { + tve_disable_vga_mode(); + tve_set_tvout_mode(YPBPR); + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_PAL_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to PAL video\n"); + } else if (mode == TVOUT_FMT_NTSC) { + tve_disable_vga_mode(); + tve_set_tvout_mode(YPBPR); + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_NTSC_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to NTSC video\n"); + } else if (mode == TVOUT_FMT_720P60) { + tve_disable_vga_mode(); + if (!_is_tvout_mode_hd_compatible()) { + tve_set_tvout_mode(YPBPR); + pr_debug("The TV out mode is HD incompatible. Setting to YPBPR."); + } + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_HD720P60_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to 720P60 video\n"); + } else if (mode == TVOUT_FMT_720P30) { + tve_disable_vga_mode(); + if (!_is_tvout_mode_hd_compatible()) { + tve_set_tvout_mode(YPBPR); + pr_debug("The TV out mode is HD incompatible. Setting to YPBPR."); + } + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_HD720P30_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to 720P30 video\n"); + } else if (mode == TVOUT_FMT_1080I60) { + tve_disable_vga_mode(); + if (!_is_tvout_mode_hd_compatible()) { + tve_set_tvout_mode(YPBPR); + pr_debug("The TV out mode is HD incompatible. Setting to YPBPR."); + } + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080I60_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to 1080I60 video\n"); + } else if (mode == TVOUT_FMT_1080I50) { + tve_disable_vga_mode(); + if (!_is_tvout_mode_hd_compatible()) { + tve_set_tvout_mode(YPBPR); + pr_debug("The TV out mode is HD incompatible. Setting to YPBPR."); + } + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080I50_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to 1080I50 video\n"); + } else if (mode == TVOUT_FMT_1080P30) { + tve_disable_vga_mode(); + if (!_is_tvout_mode_hd_compatible()) { + tve_set_tvout_mode(YPBPR); + pr_debug("The TV out mode is HD incompatible. Setting to YPBPR."); + } + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080P30_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to 1080P30 video\n"); + } else if (mode == TVOUT_FMT_1080P25) { + tve_disable_vga_mode(); + if (!_is_tvout_mode_hd_compatible()) { + tve_set_tvout_mode(YPBPR); + pr_debug("The TV out mode is HD incompatible. Setting to YPBPR."); + } + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080P25_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to 1080P25 video\n"); + } else if (mode == TVOUT_FMT_1080P24) { + tve_disable_vga_mode(); + if (!_is_tvout_mode_hd_compatible()) { + tve_set_tvout_mode(YPBPR); + pr_debug("The TV out mode is HD incompatible. Setting to YPBPR."); + } + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + reg = (reg & ~TVE_STAND_MASK) | TVE_HD1080P24_STAND; + __raw_writel(reg, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to 1080P24 video\n"); + } else if (is_vga_mode(mode)) { + /* do not need cable detect */ + tve_setup_vga(); + pr_debug("TVE: change to VGA video\n"); + } else if (mode == TVOUT_FMT_OFF) { + __raw_writel(0x0, tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE: change to OFF video\n"); + } else { + pr_debug("TVE: no such video format.\n"); + } + + if (!enabled) + clk_disable(tve.clk); + + spin_unlock_irqrestore(&tve_lock, lock_flags); + return 0; +} + +/** + * tve_enable + * Enable the tve Power to begin TV encoder + */ +static void tve_enable(void) +{ + u32 reg; + unsigned long lock_flags; + + spin_lock_irqsave(&tve_lock, lock_flags); + if (!enabled) { + enabled = 1; + clk_enable(tve.clk); + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + __raw_writel(reg | TVE_IPU_CLK_ENABLE | TVE_ENABLE, + tve.base + tve_regs->tve_com_conf_reg); + pr_debug("TVE power on.\n"); + } + + if (is_vga_enabled()) { + /* disable interrupt */ + pr_debug("TVE VGA disable cable detect.\n"); + __raw_writel(0xffffffff, tve.base + tve_regs->tve_stat_reg); + __raw_writel(0, tve.base + tve_regs->tve_int_cont_reg); + } else { + /* enable interrupt */ + pr_debug("TVE TVE enable cable detect.\n"); + __raw_writel(0xffffffff, tve.base + tve_regs->tve_stat_reg); + __raw_writel(CD_SM_INT | CD_LM_INT | CD_MON_END_INT, + tve.base + tve_regs->tve_int_cont_reg); + } + + spin_unlock_irqrestore(&tve_lock, lock_flags); + + tve_dump_regs(); +} + +/** + * tve_disable + * Disable the tve Power to stop TV encoder + */ +static void tve_disable(void) +{ + u32 reg; + unsigned long lock_flags; + + spin_lock_irqsave(&tve_lock, lock_flags); + if (enabled) { + enabled = 0; + reg = __raw_readl(tve.base + tve_regs->tve_com_conf_reg); + __raw_writel(reg & ~TVE_ENABLE & ~TVE_IPU_CLK_ENABLE, + tve.base + tve_regs->tve_com_conf_reg); + clk_disable(tve.clk); + pr_debug("TVE power off.\n"); + } + spin_unlock_irqrestore(&tve_lock, lock_flags); +} + +static int tve_update_detect_status(void) +{ + int old_detect = tve.detect; + u32 stat_lm, stat_sm, stat; + u32 int_ctl; + u32 cd_cont_reg; + u32 timeout = 40; + unsigned long lock_flags; + + spin_lock_irqsave(&tve_lock, lock_flags); + + if (!enabled) { + pr_warning("Warning: update tve status while it disabled!\n"); + tve.detect = 0; + goto done; + } + + int_ctl = __raw_readl(tve.base + tve_regs->tve_int_cont_reg); + cd_cont_reg = __raw_readl(tve.base + tve_regs->tve_cd_cont_reg); + + if ((cd_cont_reg & 0x1) == 0) { + pr_warning("Warning: pls enable TVE CD first!\n"); + goto done; + } + + stat = __raw_readl(tve.base + tve_regs->tve_stat_reg); + while (((stat & CD_MON_END_INT) == 0) && (timeout > 0)) { + spin_unlock_irqrestore(&tve_lock, lock_flags); + msleep(2); + spin_lock_irqsave(&tve_lock, lock_flags); + timeout -= 2; + if (!enabled) { + pr_warning("Warning: update tve status while it disabled!\n"); + tve.detect = 0; + goto done; + } else + stat = __raw_readl(tve.base + tve_regs->tve_stat_reg); + } + if (((stat & CD_MON_END_INT) == 0) && (timeout <= 0)) { + pr_warning("Warning: get detect result without CD_MON_END_INT!\n"); + goto done; + } + + stat = stat >> tve_reg_fields->cd_ch_stat_offset; + stat_lm = stat & (CD_CH_0_LM_ST | CD_CH_1_LM_ST | CD_CH_2_LM_ST); + if ((stat_lm == (CD_CH_0_LM_ST | CD_CH_1_LM_ST | CD_CH_2_LM_ST)) && + ((stat & (CD_CH_0_SM_ST | CD_CH_1_SM_ST | CD_CH_2_SM_ST)) == 0) + ) { + tve.detect = 3; + tve.output_mode = YPBPR; + } else if ((stat_lm == (CD_CH_0_LM_ST | CD_CH_1_LM_ST)) && + ((stat & (CD_CH_0_SM_ST | CD_CH_1_SM_ST)) == 0)) { + tve.detect = 4; + tve.output_mode = SVIDEO; + } else if (stat_lm == CD_CH_0_LM_ST) { + stat_sm = stat & CD_CH_0_SM_ST; + if (stat_sm != 0) { + /* headset */ + tve.detect = 2; + tve.output_mode = TV_OFF; + } else { + tve.detect = 1; + tve.output_mode = CVBS0; + } + } else if (stat_lm == CD_CH_2_LM_ST) { + stat_sm = stat & CD_CH_2_SM_ST; + if (stat_sm != 0) { + /* headset */ + tve.detect = 2; + tve.output_mode = TV_OFF; + } else { + tve.detect = 1; + tve.output_mode = CVBS2; + } + } else { + /* none */ + tve.detect = 0; + tve.output_mode = TV_OFF; + } + + tve_set_tvout_mode(tve.output_mode); + + /* clear interrupt */ + __raw_writel(CD_MON_END_INT | CD_LM_INT | CD_SM_INT, + tve.base + tve_regs->tve_stat_reg); + + __raw_writel(int_ctl | CD_SM_INT | CD_LM_INT, + tve.base + tve_regs->tve_int_cont_reg); + + if (old_detect != tve.detect) + sysfs_notify(&tve.pdev->dev.kobj, NULL, "headphone"); + + dev_dbg(&tve.pdev->dev, "detect = %d mode = %d\n", + tve.detect, tve.output_mode); +done: + spin_unlock_irqrestore(&tve_lock, lock_flags); + return tve.detect; +} + +static void cd_work_func(struct work_struct *work) +{ + tve_update_detect_status(); +} +#if 0 +static int tve_man_detect(void) +{ + u32 cd_cont; + u32 int_cont; + + if (!enabled) + return -1; + + int_cont = __raw_readl(tve.base + tve_regs->tve_int_cont_reg); + __raw_writel(int_cont & + ~(tve_reg_fields->cd_sm_int | tve_reg_fields->cd_lm_int), + tve.base + tve_regs->tve_int_cont_reg); + + cd_cont = __raw_readl(tve.base + tve_regs->tve_cd_cont_reg); + __raw_writel(cd_cont | tve_reg_fields->cd_trig_mode, + tve.base + tve_regs->tve_cd_cont_reg); + + __raw_writel(tve_reg_fields->cd_sm_int | tve_reg_fields-> + cd_lm_int | tve_reg_fields-> + cd_mon_end_int | tve_reg_fields->cd_man_trig, + tve.base + tve_regs->tve_stat_reg); + + while ((__raw_readl(tve.base + tve_regs->tve_stat_reg) + & tve_reg_fields->cd_mon_end_int) == 0) + msleep(5); + + tve_update_detect_status(); + + __raw_writel(cd_cont, tve.base + tve_regs->tve_cd_cont_reg); + __raw_writel(int_cont, tve.base + tve_regs->tve_int_cont_reg); + + return tve.detect; +} +#endif + +static irqreturn_t tve_detect_handler(int irq, void *data) +{ + u32 int_ctl = __raw_readl(tve.base + tve_regs->tve_int_cont_reg); + + /* disable INT first */ + int_ctl &= ~(CD_SM_INT | CD_LM_INT | CD_MON_END_INT); + __raw_writel(int_ctl, tve.base + tve_regs->tve_int_cont_reg); + + __raw_writel(CD_MON_END_INT | CD_LM_INT | CD_SM_INT, + tve.base + tve_regs->tve_stat_reg); + + schedule_delayed_work(&tve.cd_work, msecs_to_jiffies(1000)); + + return IRQ_HANDLED; +} + +static inline void tve_set_di_fmt(struct fb_info *fbi, unsigned int fmt) +{ + mm_segment_t old_fs; + + if (fbi->fbops->fb_ioctl) { + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, MXCFB_SET_DIFMT, (unsigned long)&fmt); + set_fs(old_fs); + } +} + +/*! + * FB suspend/resume routing + */ +static int tve_suspend(void) +{ + if (enabled) { + __raw_writel(0, tve.base + tve_regs->tve_int_cont_reg); + __raw_writel(0, tve.base + tve_regs->tve_cd_cont_reg); + __raw_writel(0, tve.base + tve_regs->tve_com_conf_reg); + clk_disable(tve.clk); + } + return 0; +} + +static int tve_resume(struct fb_info *fbi) +{ + int mode; + + if (enabled) { + clk_enable(tve.clk); + + /* Setup cable detect */ + if (tve.revision == 1) + __raw_writel(0x01067701, + tve.base + tve_regs->tve_cd_cont_reg); + else + __raw_writel(0x00770601, + tve.base + tve_regs->tve_cd_cont_reg); + + if (valid_mode(tve.cur_mode)) { + mode = tve.cur_mode; + tve_disable(); + tve.cur_mode = TVOUT_FMT_OFF; + tve_setup(mode); + } + tve_enable(); + } + + return 0; +} + +int tve_fb_setup(struct fb_info *fbi) +{ + int mode, fmt; + + fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var, + &fbi->modelist); + + if (!fbi->mode) { + pr_warning("TVE: can not find mode for xres=%d, yres=%d\n", + fbi->var.xres, fbi->var.yres); + tve_disable(); + tve.cur_mode = TVOUT_FMT_OFF; + return 0; + } + + pr_debug("TVE: fb mode change event: xres=%d, yres=%d\n", + fbi->mode->xres, fbi->mode->yres); + + mode = get_video_mode(fbi, &fmt); + if (mode != TVOUT_FMT_OFF) { + tve_set_di_fmt(fbi, fmt); + tve_disable(); + tve_setup(mode); + if (tve.blank == FB_BLANK_UNBLANK) + tve_enable(); + } else { + tve_disable(); + tve_setup(mode); + } + + return 0; +} + +int tve_fb_event(struct notifier_block *nb, unsigned long val, void *v) +{ + struct fb_event *event = v; + struct fb_info *fbi = event->info; + + if (strcmp(fbi->fix.id, "DISP3 BG - DI1")) + return 0; + + switch (val) { + case FB_EVENT_FB_REGISTERED: + pr_debug("TVE: fb registered event\n"); + if (tve_fbi != NULL) + break; + + tve_fbi = fbi; + break; + case FB_EVENT_MODE_CHANGE: + { + if (tve_fbi != fbi) + break; + + tve_fb_setup(fbi); + break; + } + case FB_EVENT_BLANK: + if ((tve_fbi != fbi) || (fbi->mode == NULL)) + return 0; + + pr_debug("TVE: fb blank event\n"); + + if (*((int *)event->data) == FB_BLANK_UNBLANK) { + if (tve.blank != FB_BLANK_UNBLANK) { + int mode, fmt; + mode = get_video_mode(fbi, &fmt); + if (mode != TVOUT_FMT_OFF) { + if (tve.cur_mode != mode) { + tve_disable(); + tve_setup(mode); + } + tve_enable(); + } else + tve_setup(mode); + tve.blank = FB_BLANK_UNBLANK; + } + } else { + tve_disable(); + tve.blank = FB_BLANK_POWERDOWN; + } + break; + case FB_EVENT_SUSPEND: + tve_suspend(); + break; + case FB_EVENT_RESUME: + tve_resume(fbi); + break; + } + return 0; +} + +static struct notifier_block nb = { + .notifier_call = tve_fb_event, +}; + +static ssize_t show_headphone(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int detect; + + if (!enabled) { + strcpy(buf, "tve power off\n"); + return strlen(buf); + } + + detect = tve_update_detect_status(); + + if (detect == 0) + strcpy(buf, "none\n"); + else if (detect == 1) + strcpy(buf, "cvbs\n"); + else if (detect == 2) + strcpy(buf, "headset\n"); + else if (detect == 3) + strcpy(buf, "component\n"); + else + strcpy(buf, "svideo\n"); + + return strlen(buf); +} + +static DEVICE_ATTR(headphone, S_IRUGO | S_IWUSR, show_headphone, NULL); + +static int _tve_get_revision(void) +{ + u32 conf_reg; + u32 rev = 0; + + /* find out TVE rev based on the base addr default value + * can be used at the init/probe ONLY */ + conf_reg = __raw_readl(tve.base); + switch (conf_reg) { + case 0x00842000: + rev = 1; + break; + case 0x00100000: + rev = 2; + break; + } + return rev; +} + +int tve_fb_pre_setup(struct fb_info *fbi) +{ + if (fbi->fbops->fb_ioctl) { + mm_segment_t old_fs; + + old_fs = get_fs(); + set_fs(KERNEL_DS); + fbi->fbops->fb_ioctl(fbi, + MXCFB_GET_FB_BLANK, + (unsigned int)(&tve.blank)); + set_fs(old_fs); + } + return tve_fb_setup(fbi); +} + +static int tve_probe(struct platform_device *pdev) +{ + int ret; + struct resource *res; + struct tve_platform_data *plat_data = pdev->dev.platform_data; + u32 conf_reg; + + if (g_enable_tve == false && g_enable_vga == false) + return -EPERM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -ENOMEM; + + tve.pdev = pdev; + tve.base = ioremap(res->start, res->end - res->start); + + tve.irq = platform_get_irq(pdev, 0); + if (tve.irq < 0) { + ret = tve.irq; + goto err0; + } + + ret = request_irq(tve.irq, tve_detect_handler, 0, pdev->name, pdev); + if (ret < 0) + goto err0; + + ret = device_create_file(&pdev->dev, &dev_attr_headphone); + if (ret < 0) + goto err1; + + tve.dac_reg = regulator_get(&pdev->dev, plat_data->dac_reg); + if (!IS_ERR(tve.dac_reg)) { + regulator_set_voltage(tve.dac_reg, 2750000, 2750000); + regulator_enable(tve.dac_reg); + } + + tve.dig_reg = regulator_get(&pdev->dev, plat_data->dig_reg); + if (!IS_ERR(tve.dig_reg)) { + regulator_set_voltage(tve.dig_reg, 1250000, 1250000); + regulator_enable(tve.dig_reg); + } + + tve.clk = clk_get(&pdev->dev, "tve_clk"); + if (IS_ERR(tve.clk)) { + ret = PTR_ERR(tve.clk); + goto err2; + } + tve.di_clk = clk_get(NULL, "ipu_di1_clk"); + if (IS_ERR(tve.di_clk)) { + ret = PTR_ERR(tve.di_clk); + goto err2; + } + clk_set_rate(tve.clk, 216000000); + clk_set_parent(tve.di_clk, tve.clk); + clk_enable(tve.clk); + + tve.revision = _tve_get_revision(); + if (tve.revision == 1) { + tve_regs = &tve_regs_v1; + tve_reg_fields = &tve_reg_fields_v1; + } else { + tve_regs = &tve_regs_v2; + tve_reg_fields = &tve_reg_fields_v2; + } + + /* adjust video mode for mx37 */ + if (cpu_is_mx37()) { + video_modes[0].left_margin = 121; + video_modes[0].right_margin = 16; + video_modes[0].upper_margin = 17; + video_modes[0].lower_margin = 5; + video_modes[1].left_margin = 131; + video_modes[1].right_margin = 12; + video_modes[1].upper_margin = 21; + video_modes[1].lower_margin = 3; + } + + /* TVE is on disp port 1 */ + if (tve.revision == 1) { + if (g_enable_tve) + mxcfb_register_mode(IPU_DISP_PORT, video_modes, + 3, MXC_DISP_SPEC_DEV); + } else { + if (g_enable_tve) + mxcfb_register_mode(IPU_DISP_PORT, video_modes, + ARRAY_SIZE(video_modes), + MXC_DISP_SPEC_DEV); + + if (cpu_is_mx53() && g_enable_vga) + mxcfb_register_mode(IPU_DISP_PORT, video_modes_vga, + ARRAY_SIZE(video_modes_vga), + MXC_DISP_SPEC_DEV); + } + mxcfb_register_presetup(IPU_DISP_PORT, tve_fb_pre_setup); + + /* Setup cable detect, for YPrPb mode, default use channel#-1 for Y */ + INIT_DELAYED_WORK(&tve.cd_work, cd_work_func); + if (tve.revision == 1) + __raw_writel(0x01067701, tve.base + tve_regs->tve_cd_cont_reg); + else + __raw_writel(0x00770601, tve.base + tve_regs->tve_cd_cont_reg); + + conf_reg = 0; + __raw_writel(conf_reg, tve.base + tve_regs->tve_com_conf_reg); + + __raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4 * 5); + __raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4 * 4); + __raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4 * 3); + __raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4 * 2); + __raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg - 4); + __raw_writel(0x00000000, tve.base + tve_regs->tve_mv_cont_reg); + + clk_disable(tve.clk); + + ret = fb_register_client(&nb); + if (ret < 0) + goto err2; + + tve.blank = -1; + + return 0; +err2: + device_remove_file(&pdev->dev, &dev_attr_headphone); +err1: + free_irq(tve.irq, pdev); +err0: + iounmap(tve.base); + return ret; +} + +static int tve_remove(struct platform_device *pdev) +{ + if (enabled) { + clk_disable(tve.clk); + enabled = 0; + } + free_irq(tve.irq, pdev); + device_remove_file(&pdev->dev, &dev_attr_headphone); + fb_unregister_client(&nb); + return 0; +} + +static struct platform_driver tve_driver = { + .driver = { + .name = "tve", + }, + .probe = tve_probe, + .remove = tve_remove, +}; + +static int __init enable_tve_setup(char *options) +{ + g_enable_tve = true; + + return 1; +} +__setup("tve", enable_tve_setup); + +static int __init enable_vga_setup(char *options) +{ + g_enable_vga = true; + + return 1; +} +__setup("vga", enable_vga_setup); + +static int __init tve_init(void) +{ + return platform_driver_register(&tve_driver); +} + +static void __exit tve_exit(void) +{ + platform_driver_unregister(&tve_driver); +} + +module_init(tve_init); +module_exit(tve_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("i.MX TV encoder driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxs/Kconfig b/drivers/video/mxs/Kconfig new file mode 100644 index 000000000000..35b896e95d4f --- /dev/null +++ b/drivers/video/mxs/Kconfig @@ -0,0 +1,28 @@ +config FB_MXS + tristate "MXS Framebuffer driver" + depends on FB && ARCH_MXS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + default y + ---help--- + Say Y here to enable support for the framebuffer driver for the + Freescale MXS Board. + +config FB_MXS_LCD_43WVF1G + depends on FB_MXS + tristate "SEIKO 4.3' LCD WVGA(800x480) PANEL" + default y if ARCH_MX28 + +config FB_MXS_LCD_LMS430 + depends on FB_MXS + bool "LMS430" + default y if ARCH_MX23 + ---help--- + Use LMS430 dotclock LCD panel for MXS + +config FB_MXS_TVENC + depends on ARCH_MXS + bool "TVENC" + ---help--- + Use TVOUT encoder for MXS diff --git a/drivers/video/mxs/Makefile b/drivers/video/mxs/Makefile new file mode 100644 index 000000000000..fbab953718c7 --- /dev/null +++ b/drivers/video/mxs/Makefile @@ -0,0 +1,6 @@ +obj-$(CONFIG_ARCH_MXS) += lcdif.o +obj-$(CONFIG_FB_MXS) += mxsfb.o +obj-$(CONFIG_FB_MXS_LCD_43WVF1G) += lcd_43wvf1g.o +obj-$(CONFIG_FB_MXS_LCD_LMS430) += lcd_lms430.o +# TVOUT support +obj-$(CONFIG_FB_MXS_TVENC) += tvenc.o diff --git a/drivers/video/mxs/lcd_43wvf1g.c b/drivers/video/mxs/lcd_43wvf1g.c new file mode 100644 index 000000000000..1a8157f277a0 --- /dev/null +++ b/drivers/video/mxs/lcd_43wvf1g.c @@ -0,0 +1,289 @@ +/* + * Freescale MX28 Seiko 43WVF1G LCD panel driver + * + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define DOTCLK_H_ACTIVE 800 +#define DOTCLK_H_PULSE_WIDTH 10 +#define DOTCLK_HF_PORCH 164 +#define DOTCLK_HB_PORCH 89 +#define DOTCLK_H_WAIT_CNT (DOTCLK_H_PULSE_WIDTH + DOTCLK_HB_PORCH) +#define DOTCLK_H_PERIOD (DOTCLK_H_WAIT_CNT + DOTCLK_HF_PORCH + DOTCLK_H_ACTIVE) + +#define DOTCLK_V_ACTIVE 480 +#define DOTCLK_V_PULSE_WIDTH 10 +#define DOTCLK_VF_PORCH 10 +#define DOTCLK_VB_PORCH 23 +#define DOTCLK_V_WAIT_CNT (DOTCLK_V_PULSE_WIDTH + DOTCLK_VB_PORCH) +#define DOTCLK_V_PERIOD (DOTCLK_VF_PORCH + DOTCLK_V_ACTIVE + DOTCLK_V_WAIT_CNT) + +static struct mxs_platform_bl_data bl_data; +static struct clk *lcd_clk; + +static int init_panel(struct device *dev, dma_addr_t phys, int memsize, + struct mxs_platform_fb_entry *pentry) +{ + int ret = 0; + lcd_clk = clk_get(dev, "dis_lcdif"); + if (IS_ERR(lcd_clk)) { + ret = PTR_ERR(lcd_clk); + goto out; + } + ret = clk_enable(lcd_clk); + if (ret) { + clk_put(lcd_clk); + goto out; + } + + ret = clk_set_rate(lcd_clk, 1000000 / pentry->cycle_time_ns); /* kHz */ + if (ret) { + clk_disable(lcd_clk); + clk_put(lcd_clk); + goto out; + } + + /* + * Make sure we do a high-to-low transition to reset the panel. + * First make it low for 100 msec, hi for 10 msec, low for 10 msec, + * then hi. + */ + __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); /* low */ + mdelay(100); + __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); /* high */ + mdelay(10); + __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); /* low */ + + /* For the Samsung, Reset must be held low at least 30 uSec + * Therefore, we'll hold it low for about 10 mSec just to be sure. + * Then we'll wait 1 mSec afterwards. + */ + mdelay(10); + __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); /* high */ + mdelay(1); + + setup_dotclk_panel(DOTCLK_V_PULSE_WIDTH, DOTCLK_V_PERIOD, + DOTCLK_V_WAIT_CNT, DOTCLK_V_ACTIVE, + DOTCLK_H_PULSE_WIDTH, DOTCLK_H_PERIOD, + DOTCLK_H_WAIT_CNT, DOTCLK_H_ACTIVE, 0); + + ret = mxs_lcdif_dma_init(dev, phys, memsize); + if (ret) + goto out; + + mxs_lcd_set_bl_pdata(pentry->bl_data); + mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry); + return 0; + +out: + return ret; +} + +static void release_panel(struct device *dev, + struct mxs_platform_fb_entry *pentry) +{ + mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_RELEASE, pentry); + release_dotclk_panel(); + mxs_lcdif_dma_release(); + clk_disable(lcd_clk); + clk_put(lcd_clk); +} + +static int blank_panel(int blank) +{ + int ret = 0, count; + + switch (blank) { + case FB_BLANK_NORMAL: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_POWERDOWN: + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + for (count = 10000; count; count--) { + if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) & + BM_LCDIF_STAT_TXFIFO_EMPTY) + break; + udelay(1); + } + break; + + case FB_BLANK_UNBLANK: + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + break; + + default: + ret = -EINVAL; + } + return ret; +} + +static struct mxs_platform_fb_entry fb_entry = { + .name = "43wvf1g", + .x_res = 480, + .y_res = 800, + .bpp = 32, + .cycle_time_ns = 30, + .lcd_type = MXS_LCD_PANEL_DOTCLK, + .init_panel = init_panel, + .release_panel = release_panel, + .blank_panel = blank_panel, + .run_panel = mxs_lcdif_run, + .stop_panel = mxs_lcdif_stop, + .pan_display = mxs_lcdif_pan_display, + .bl_data = &bl_data, +}; + +static struct clk *pwm_clk; + +static int init_bl(struct mxs_platform_bl_data *data) +{ + int ret = 0; + + pwm_clk = clk_get(NULL, "pwm"); + if (IS_ERR(pwm_clk)) { + ret = PTR_ERR(pwm_clk); + return ret; + } + clk_enable(pwm_clk); + mxs_reset_block(REGS_PWM_BASE, 1); + + __raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) | + BF_PWM_ACTIVEn_ACTIVE(0), + REGS_PWM_BASE + HW_PWM_ACTIVEn(2)); + __raw_writel(BF_PWM_PERIODn_CDIV(6) | /* divide by 64 */ + BF_PWM_PERIODn_INACTIVE_STATE(2) | /* low */ + BF_PWM_PERIODn_ACTIVE_STATE(3) | /* high */ + BF_PWM_PERIODn_PERIOD(599), + REGS_PWM_BASE + HW_PWM_PERIODn(2)); + __raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_SET); + + return 0; +} + +static void free_bl(struct mxs_platform_bl_data *data) +{ + __raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) | + BF_PWM_ACTIVEn_ACTIVE(0), + REGS_PWM_BASE + HW_PWM_ACTIVEn(2)); + __raw_writel(BF_PWM_PERIODn_CDIV(6) | /* divide by 64 */ + BF_PWM_PERIODn_INACTIVE_STATE(2) | /* low */ + BF_PWM_PERIODn_ACTIVE_STATE(3) | /* high */ + BF_PWM_PERIODn_PERIOD(599), + REGS_PWM_BASE + HW_PWM_PERIODn(2)); + __raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_CLR); + + clk_disable(pwm_clk); + clk_put(pwm_clk); +} + +static int values[] = { 0, 4, 9, 14, 20, 27, 35, 45, 57, 75, 100 }; + +static int power[] = { + 0, 1500, 3600, 6100, 10300, + 15500, 74200, 114200, 155200, + 190100, 191000 +}; + +static int bl_to_power(int br) +{ + int base; + int rem; + + if (br > 100) + br = 100; + base = power[br / 10]; + rem = br % 10; + if (!rem) + return base; + else + return base + (rem * (power[br / 10 + 1]) - base) / 10; +} + +static int set_bl_intensity(struct mxs_platform_bl_data *data, + struct backlight_device *bd, int suspended) +{ + int intensity = bd->props.brightness; + int scaled_int; + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + if (suspended) + intensity = 0; + + /* + * This is not too cool but what can we do? + * Luminance changes non-linearly... + */ + if (regulator_set_current_limit + (data->regulator, bl_to_power(intensity), bl_to_power(intensity))) + return -EBUSY; + + scaled_int = values[intensity / 10]; + if (scaled_int < 100) { + int rem = intensity - 10 * (intensity / 10); /* r = i % 10; */ + scaled_int += rem * (values[intensity / 10 + 1] - + values[intensity / 10]) / 10; + } + __raw_writel(BF_PWM_ACTIVEn_INACTIVE(scaled_int) | + BF_PWM_ACTIVEn_ACTIVE(0), + REGS_PWM_BASE + HW_PWM_ACTIVEn(2)); + __raw_writel(BF_PWM_PERIODn_CDIV(6) | /* divide by 64 */ + BF_PWM_PERIODn_INACTIVE_STATE(2) | /* low */ + BF_PWM_PERIODn_ACTIVE_STATE(3) | /* high */ + BF_PWM_PERIODn_PERIOD(399), + REGS_PWM_BASE + HW_PWM_PERIODn(2)); + return 0; +} + +static struct mxs_platform_bl_data bl_data = { + .bl_max_intensity = 100, + .bl_default_intensity = 50, + .bl_cons_intensity = 50, + .init_bl = init_bl, + .free_bl = free_bl, + .set_bl_intensity = set_bl_intensity, +}; + +static int __init register_devices(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-fb", 0); + if (pdev == NULL || IS_ERR(pdev)) + return -ENODEV; + + mxs_lcd_register_entry(&fb_entry, pdev->dev.platform_data); + + return 0; +} + +subsys_initcall(register_devices); diff --git a/drivers/video/mxs/lcd_lms430.c b/drivers/video/mxs/lcd_lms430.c new file mode 100644 index 000000000000..c167774d5785 --- /dev/null +++ b/drivers/video/mxs/lcd_lms430.c @@ -0,0 +1,300 @@ +/* + * Freescale MXS Samsung LMS430 LCD panel initialization + * + * Embedded Alley Solutions, Inc + * + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define REGS_PWM_BASE IO_ADDRESS(PWM_PHYS_ADDR) + +#define DOTCLK_H_ACTIVE 480 +#define DOTCLK_H_PULSE_WIDTH 1 +#define DOTCLK_HF_PORCH 8 +#define DOTCLK_HB_PORCH 15 +#define DOTCLK_H_WAIT_CNT (DOTCLK_H_PULSE_WIDTH + (3 * DOTCLK_HB_PORCH)) +#define DOTCLK_H_PERIOD (DOTCLK_H_WAIT_CNT + DOTCLK_HF_PORCH + DOTCLK_H_ACTIVE) + +#define DOTCLK_V_ACTIVE 272 +#define DOTCLK_V_PULSE_WIDTH 1 +#define DOTCLK_VF_PORCH 4 +#define DOTCLK_VB_PORCH 12 +#define DOTCLK_V_WAIT_CNT (DOTCLK_V_PULSE_WIDTH + DOTCLK_VB_PORCH) +#define DOTCLK_V_PERIOD (DOTCLK_VF_PORCH + DOTCLK_V_ACTIVE + DOTCLK_V_WAIT_CNT) + +static struct mxs_platform_bl_data bl_data; +static struct clk *lcd_clk; + +static int init_panel(struct device *dev, dma_addr_t phys, int memsize, + struct mxs_platform_fb_entry *pentry) +{ + int ret = 0; + lcd_clk = clk_get(NULL, "lcdif"); + if (IS_ERR(lcd_clk)) { + ret = PTR_ERR(lcd_clk); + goto out; + } + ret = clk_enable(lcd_clk); + if (ret) { + clk_put(lcd_clk); + goto out; + } + + ret = clk_set_rate(lcd_clk, 1000000000 / pentry->cycle_time_ns); /* Hz */ + if (ret) { + clk_disable(lcd_clk); + clk_put(lcd_clk); + goto out; + } + + /* + * Make sure we do a high-to-low transition to reset the panel. + * First make it low for 100 msec, hi for 10 msec, low for 10 msec, + * then hi. + */ + __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); /* low */ + mdelay(100); + __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); /* high */ + mdelay(10); + __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); /* low */ + + /* For the Samsung, Reset must be held low at least 30 uSec + * Therefore, we'll hold it low for about 10 mSec just to be sure. + * Then we'll wait 1 mSec afterwards. + */ + mdelay(10); + __raw_writel(BM_LCDIF_CTRL1_RESET, REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); /* high */ + mdelay(1); + + setup_dotclk_panel(DOTCLK_V_PULSE_WIDTH, DOTCLK_V_PERIOD, + DOTCLK_V_WAIT_CNT, DOTCLK_V_ACTIVE, + DOTCLK_H_PULSE_WIDTH, DOTCLK_H_PERIOD, + DOTCLK_H_WAIT_CNT, DOTCLK_H_ACTIVE, 0); + + ret = mxs_lcdif_dma_init(dev, phys, memsize); + if (ret) + goto out; + + mxs_lcd_set_bl_pdata(pentry->bl_data); + mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry); + return 0; + +out: + return ret; +} + +static void release_panel(struct device *dev, + struct mxs_platform_fb_entry *pentry) +{ + /* Reset LCD panel signel. */ + __raw_writel(BM_LCDIF_CTRL1_RESET, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + mdelay(100); + mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_RELEASE, pentry); + release_dotclk_panel(); + mxs_lcdif_dma_release(); + clk_disable(lcd_clk); + clk_put(lcd_clk); + __raw_writel(BM_LCDIF_CTRL_CLKGATE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); +} + +static int blank_panel(int blank) +{ + int ret = 0, count; + + switch (blank) { + case FB_BLANK_NORMAL: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_POWERDOWN: + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + for (count = 10000; count; count--) { + if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) & + BM_LCDIF_STAT_TXFIFO_EMPTY) + break; + udelay(1); + } + break; + + case FB_BLANK_UNBLANK: + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + break; + + default: + ret = -EINVAL; + } + return ret; +} + +static struct mxs_platform_fb_entry fb_entry = { + .name = "lms430", + .x_res = 272, + .y_res = 480, + .bpp = 32, + .cycle_time_ns = 150, + .lcd_type = MXS_LCD_PANEL_DOTCLK, + .init_panel = init_panel, + .release_panel = release_panel, + .blank_panel = blank_panel, + .run_panel = mxs_lcdif_run, + .stop_panel = mxs_lcdif_stop, + .pan_display = mxs_lcdif_pan_display, + .bl_data = &bl_data, +}; + +static struct clk *pwm_clk; + +static int init_bl(struct mxs_platform_bl_data *data) +{ + int ret = 0; + + pwm_clk = clk_get(NULL, "pwm"); + if (IS_ERR(pwm_clk)) { + ret = PTR_ERR(pwm_clk); + return ret; + } + clk_enable(pwm_clk); + mxs_reset_block(REGS_PWM_BASE, 1); + + __raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) | + BF_PWM_ACTIVEn_ACTIVE(0), + REGS_PWM_BASE + HW_PWM_ACTIVEn(2)); + __raw_writel(BF_PWM_PERIODn_CDIV(6) | /* divide by 64 */ + BF_PWM_PERIODn_INACTIVE_STATE(2) | /* low */ + BF_PWM_PERIODn_ACTIVE_STATE(3) | /* high */ + BF_PWM_PERIODn_PERIOD(599), + REGS_PWM_BASE + HW_PWM_PERIODn(2)); + __raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_SET); + + return 0; +} + +static void free_bl(struct mxs_platform_bl_data *data) +{ + __raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) | + BF_PWM_ACTIVEn_ACTIVE(0), + REGS_PWM_BASE + HW_PWM_ACTIVEn(2)); + __raw_writel(BF_PWM_PERIODn_CDIV(6) | /* divide by 64 */ + BF_PWM_PERIODn_INACTIVE_STATE(2) | /* low */ + BF_PWM_PERIODn_ACTIVE_STATE(3) | /* high */ + BF_PWM_PERIODn_PERIOD(599), + REGS_PWM_BASE + HW_PWM_PERIODn(2)); + __raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_CLR); + + clk_disable(pwm_clk); + clk_put(pwm_clk); +} + +static int values[] = { 0, 4, 9, 14, 20, 27, 35, 45, 57, 75, 100 }; + +static int power[] = { + 0, 1500, 3600, 6100, 10300, + 15500, 74200, 114200, 155200, + 190100, 191000 +}; + +static int bl_to_power(int br) +{ + int base; + int rem; + + if (br > 100) + br = 100; + base = power[br / 10]; + rem = br % 10; + if (!rem) + return base; + else + return base + (rem * (power[br / 10 + 1]) - base) / 10; +} + +static int set_bl_intensity(struct mxs_platform_bl_data *data, + struct backlight_device *bd, int suspended) +{ + int intensity = bd->props.brightness; + int scaled_int; + + if (bd->props.power != FB_BLANK_UNBLANK) + intensity = 0; + if (bd->props.fb_blank != FB_BLANK_UNBLANK) + intensity = 0; + if (suspended) + intensity = 0; + + /* + * This is not too cool but what can we do? + * Luminance changes non-linearly... + */ + if (regulator_set_current_limit + (data->regulator, bl_to_power(intensity), bl_to_power(intensity))) + return -EBUSY; + + scaled_int = values[intensity / 10]; + if (scaled_int < 100) { + int rem = intensity - 10 * (intensity / 10); /* r = i % 10; */ + scaled_int += rem * (values[intensity / 10 + 1] - + values[intensity / 10]) / 10; + } + __raw_writel(BF_PWM_ACTIVEn_INACTIVE(scaled_int) | + BF_PWM_ACTIVEn_ACTIVE(0), + REGS_PWM_BASE + HW_PWM_ACTIVEn(2)); + __raw_writel(BF_PWM_PERIODn_CDIV(6) | /* divide by 64 */ + BF_PWM_PERIODn_INACTIVE_STATE(2) | /* low */ + BF_PWM_PERIODn_ACTIVE_STATE(3) | /* high */ + BF_PWM_PERIODn_PERIOD(399), + REGS_PWM_BASE + HW_PWM_PERIODn(2)); + return 0; +} + +static struct mxs_platform_bl_data bl_data = { + .bl_max_intensity = 100, + .bl_default_intensity = 50, + .bl_cons_intensity = 50, + .init_bl = init_bl, + .free_bl = free_bl, + .set_bl_intensity = set_bl_intensity, +}; + +static int __init register_devices(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-fb", 0); + if (pdev == NULL || IS_ERR(pdev)) + return -ENODEV; + + mxs_lcd_register_entry(&fb_entry, pdev->dev.platform_data); + + return 0; +} + +subsys_initcall(register_devices); diff --git a/drivers/video/mxs/lcdif.c b/drivers/video/mxs/lcdif.c new file mode 100644 index 000000000000..f7d48a6fb3e9 --- /dev/null +++ b/drivers/video/mxs/lcdif.c @@ -0,0 +1,136 @@ +/* + * Freescale MXS LCDIF low-level routines + * + * Author: Vitaly Wool + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include + +#include +#include +#include +#include + +#define REGS_LCDIF_BASE IO_ADDRESS(LCDIF_PHYS_ADDR) + +void mxs_init_lcdif(void) +{ + __raw_writel(BM_LCDIF_CTRL_CLKGATE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + /* Reset controller */ + __raw_writel(BM_LCDIF_CTRL_SFTRST, REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + udelay(10); + + /* Take controller out of reset */ + __raw_writel(BM_LCDIF_CTRL_SFTRST | BM_LCDIF_CTRL_CLKGATE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + /* Setup the bus protocol */ + __raw_writel(BM_LCDIF_CTRL1_MODE86, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + __raw_writel(BM_LCDIF_CTRL1_BUSY_ENABLE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + + /* Take display out of reset */ + __raw_writel(BM_LCDIF_CTRL1_RESET, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + /* VSYNC is an input by default */ + __raw_writel(BM_LCDIF_VDCTRL0_VSYNC_OEB, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET); + + /* Reset display */ + __raw_writel(BM_LCDIF_CTRL1_RESET, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + udelay(10); + __raw_writel(BM_LCDIF_CTRL1_RESET, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + udelay(10); +} +EXPORT_SYMBOL(mxs_init_lcdif); + +int mxs_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize) +{ + __raw_writel(BM_LCDIF_CTRL_LCDIF_MASTER, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + __raw_writel(phys, REGS_LCDIF_BASE + HW_LCDIF_CUR_BUF); + __raw_writel(phys, REGS_LCDIF_BASE + HW_LCDIF_NEXT_BUF); + + return 0; +} +EXPORT_SYMBOL(mxs_lcdif_dma_init); + +void mxs_lcdif_dma_release(void) +{ + __raw_writel(BM_LCDIF_CTRL_LCDIF_MASTER, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + return; +} +EXPORT_SYMBOL(mxs_lcdif_dma_release); + +void mxs_lcdif_run(void) +{ + __raw_writel(BM_LCDIF_CTRL_LCDIF_MASTER, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + __raw_writel(BM_LCDIF_CTRL_RUN, REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); +} +EXPORT_SYMBOL(mxs_lcdif_run); + +void mxs_lcdif_stop(void) +{ + __raw_writel(BM_LCDIF_CTRL_RUN, REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_LCDIF_MASTER, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + udelay(100); +} +EXPORT_SYMBOL(mxs_lcdif_stop); + +int mxs_lcdif_pan_display(dma_addr_t addr) +{ + __raw_writel(addr, REGS_LCDIF_BASE + HW_LCDIF_NEXT_BUF); + + return 0; +} + +EXPORT_SYMBOL(mxs_lcdif_pan_display); + +static BLOCKING_NOTIFIER_HEAD(lcdif_client_list); + +int mxs_lcdif_register_client(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&lcdif_client_list, nb); +} + +EXPORT_SYMBOL(mxs_lcdif_register_client); + +void mxs_lcdif_unregister_client(struct notifier_block *nb) +{ + blocking_notifier_chain_unregister(&lcdif_client_list, nb); +} +EXPORT_SYMBOL(mxs_lcdif_unregister_client); + +void mxs_lcdif_notify_clients(unsigned long event, + struct mxs_platform_fb_entry *pentry) +{ + blocking_notifier_call_chain(&lcdif_client_list, event, pentry); +} +EXPORT_SYMBOL(mxs_lcdif_notify_clients); diff --git a/drivers/video/mxs/mxsfb.c b/drivers/video/mxs/mxsfb.c new file mode 100644 index 000000000000..0e58ced83066 --- /dev/null +++ b/drivers/video/mxs/mxsfb.c @@ -0,0 +1,950 @@ +/* + * Freescale MXS framebuffer driver + * + * Author: Vitaly Wool + * + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define NUM_SCREENS 1 + +enum { + F_DISABLE = 0, + F_ENABLE, + F_REENABLE, +}; + +struct mxs_fb_data { + struct fb_info info; + struct mxs_platform_fb_data *pdata; + struct work_struct work; + struct mutex blank_mutex; + u32 state; + u32 task_state; + ssize_t mem_size; + ssize_t map_size; + dma_addr_t phys_start; + dma_addr_t cur_phys; + int irq; + unsigned long regbase; + void *virt_start; + struct device *dev; + wait_queue_head_t vsync_wait_q; + u32 vsync_count; + void *par; +}; + +/* forward declaration */ +static int mxsfb_blank(int blank, struct fb_info *info); +static unsigned char *default_panel_name; +static struct mxs_fb_data *cdata; +static void init_timings(struct mxs_fb_data *data); + +static void mxsfb_enable_controller(struct mxs_fb_data *data) +{ + struct mxs_platform_fb_entry *pentry = data->pdata->cur; + + if (!data || !data->pdata || !data->pdata->cur) + return; + + mxs_init_lcdif(); + init_timings(data); + pentry->init_panel(data->dev, data->phys_start, + data->info.fix.smem_len, data->pdata->cur); + pentry->run_panel(); + + if (pentry->blank_panel) + pentry->blank_panel(FB_BLANK_UNBLANK); +} + +static void mxsfb_disable_controller(struct mxs_fb_data *data) +{ + struct mxs_platform_fb_entry *pentry = data->pdata->cur; + + if (!data || !data->pdata || !data->pdata->cur) + return; + + if (pentry->blank_panel) + pentry->blank_panel(FB_BLANK_POWERDOWN); + + if (pentry->stop_panel) + pentry->stop_panel(); + pentry->release_panel(data->dev, pentry); +} + +static void set_controller_state(struct mxs_fb_data *data, u32 state) +{ + struct mxs_platform_fb_entry *pentry = data->pdata->cur; + struct fb_info *info = &data->info; + u32 old_state; + + mutex_lock(&data->blank_mutex); + old_state = data->state; + pr_debug("%s, old_state %d, state %d\n", __func__, old_state, state); + + switch (state) { + case F_DISABLE: + /* + * Disable controller + */ + if (old_state != F_DISABLE) { + data->state = F_DISABLE; + mxsfb_disable_controller(data); + } + break; + + case F_REENABLE: + /* + * Re-enable the controller when panel changed. + */ + if (old_state == F_ENABLE) { + mxsfb_disable_controller(data); + + pentry = data->pdata->cur = data->pdata->next; + info->fix.smem_len = pentry->y_res * pentry->x_res * + pentry->bpp / 8; + info->screen_size = info->fix.smem_len; + memset((void *)info->screen_base, 0, info->screen_size); + + mxsfb_enable_controller(data); + + data->state = F_ENABLE; + } else if (old_state == F_DISABLE) { + pentry = data->pdata->cur = data->pdata->next; + info->fix.smem_len = pentry->y_res * pentry->x_res * + pentry->bpp / 8; + info->screen_size = info->fix.smem_len; + memset((void *)info->screen_base, 0, info->screen_size); + + data->state = F_DISABLE; + } + break; + + case F_ENABLE: + if (old_state != F_ENABLE) { + data->state = F_ENABLE; + mxsfb_enable_controller(data); + } + break; + } + mutex_unlock(&data->blank_mutex); + +} + +static void mxsfb_task(struct work_struct *work) +{ + struct mxs_fb_data *data = container_of(work, struct mxs_fb_data, work); + + u32 state = xchg(&data->task_state, -1); + pr_debug("%s: state = %d, data->task_state = %d\n", + __func__, state, data->task_state); + + set_controller_state(data, state); +} + +static void mxs_schedule_work(struct mxs_fb_data *data, u32 state) +{ + unsigned long flags; + + local_irq_save(flags); + + data->task_state = state; + schedule_work(&data->work); + + local_irq_restore(flags); +} + +static irqreturn_t lcd_irq_handler(int irq, void *dev_id) +{ + struct mxs_fb_data *data = dev_id; + u32 status_lcd = __raw_readl(data->regbase + HW_LCDIF_CTRL1); + pr_debug("%s: irq %d\n", __func__, irq); + + if (status_lcd & BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ) { + pr_debug("%s: VSYNC irq\n", __func__); + data->vsync_count++; + __raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ, + data->regbase + HW_LCDIF_CTRL1_CLR); + wake_up_interruptible(&data->vsync_wait_q); + } + if (status_lcd & BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ) { + pr_debug("%s: frame done irq\n", __func__); + __raw_writel(BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ, + data->regbase + HW_LCDIF_CTRL1_CLR); + data->vsync_count++; + } + if (status_lcd & BM_LCDIF_CTRL1_UNDERFLOW_IRQ) { + pr_debug("%s: underflow irq\n", __func__); + __raw_writel(BM_LCDIF_CTRL1_UNDERFLOW_IRQ, + data->regbase + HW_LCDIF_CTRL1_CLR); + } + if (status_lcd & BM_LCDIF_CTRL1_OVERFLOW_IRQ) { + pr_debug("%s: overflow irq\n", __func__); + __raw_writel(BM_LCDIF_CTRL1_OVERFLOW_IRQ, + data->regbase + HW_LCDIF_CTRL1_CLR); + } + return IRQ_HANDLED; +} + +static struct fb_var_screeninfo mxsfb_default __devinitdata = { + .activate = FB_ACTIVATE_TEST, + .height = -1, + .width = -1, + .pixclock = 20000, + .left_margin = 64, + .right_margin = 64, + .upper_margin = 32, + .lower_margin = 32, + .hsync_len = 64, + .vsync_len = 2, + .vmode = FB_VMODE_NONINTERLACED, +}; + +static struct fb_fix_screeninfo mxsfb_fix __devinitdata = { + .id = "mxsfb", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_TRUECOLOR, + .xpanstep = 0, + .ypanstep = 0, + .ywrapstep = 0, + .accel = FB_ACCEL_NONE, +}; + +int mxsfb_get_info(struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix) +{ + if (!cdata) + return -ENODEV; + + *var = cdata->info.var; + *fix = cdata->info.fix; + return 0; +} + +void mxsfb_cfg_pxp(int enable, dma_addr_t pxp_phys) +{ + if (enable) + cdata->pdata->cur->pan_display(pxp_phys); + else + cdata->pdata->cur->pan_display(cdata->cur_phys); +} + +static int mxsfb_mmap(struct fb_info *info, struct vm_area_struct *vma) +{ + struct mxs_fb_data *data = (struct mxs_fb_data *)info; + + unsigned long off = vma->vm_pgoff << PAGE_SHIFT; + + if (off < info->fix.smem_len) + return dma_mmap_writecombine(data->dev, vma, + data->virt_start, + data->phys_start, + info->fix.smem_len); + else + return -EINVAL; +} + +static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + u_int transp, struct fb_info *info) +{ + if (regno >= 256) /* no. of hw registers */ + return 1; + /* + * Program hardware... do anything you want with transp + */ + + /* grayscale works only partially under directcolor */ + if (info->var.grayscale) { + /* grayscale = 0.30*R + 0.59*G + 0.11*B */ + red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; + } + + /* Directcolor: + * var->{color}.offset contains start of bitfield + * var->{color}.length contains length of bitfield + * {hardwarespecific} contains width of RAMDAC + * cmap[X] is programmed to + * (X << red.offset) | (X << green.offset) | (X << blue.offset) + * RAMDAC[X] is programmed to (red, green, blue) + * + * Pseudocolor: + * uses offset = 0 && length = RAMDAC register width. + * var->{color}.offset is 0 + * var->{color}.length contains widht of DAC + * cmap is not used + * RAMDAC[X] is programmed to (red, green, blue) + * Truecolor: + * does not use DAC. Usually 3 are present. + * var->{color}.offset contains start of bitfield + * var->{color}.length contains length of bitfield + * cmap is programmed to + * (red << red.offset) | (green << green.offset) | + * (blue << blue.offset) | (transp << transp.offset) + * RAMDAC does not exist + */ +#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16) + switch (info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + case FB_VISUAL_PSEUDOCOLOR: + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); + break; + case FB_VISUAL_DIRECTCOLOR: + red = CNVT_TOHW(red, 8); /* expect 8 bit DAC */ + green = CNVT_TOHW(green, 8); + blue = CNVT_TOHW(blue, 8); + /* hey, there is bug in transp handling... */ + transp = CNVT_TOHW(transp, 8); + break; + } +#undef CNVT_TOHW + /* Truecolor has hardware independent palette */ + if (info->fix.visual == FB_VISUAL_TRUECOLOR) { + + if (regno >= 16) + return 1; + + ((u32 *) (info->pseudo_palette))[regno] = + (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + } + return 0; +} + +static inline u_long get_line_length(int xres_virtual, int bpp) +{ + u_long length; + + length = xres_virtual * bpp; + length = (length + 31) & ~31; + length >>= 3; + return length; +} + +static int get_matching_pentry(struct mxs_platform_fb_entry *pentry, + void *data, int ret_prev) +{ + struct fb_var_screeninfo *info = data; + pr_debug("%s: %d:%d:%d vs %d:%d:%d\n", __func__, + pentry->x_res, pentry->y_res, pentry->bpp, + info->yres, info->xres, info->bits_per_pixel); + if (pentry->x_res == info->yres && pentry->y_res == info->xres && + pentry->bpp == info->bits_per_pixel) + ret_prev = (int)pentry; + return ret_prev; +} + +static int get_matching_pentry_by_name(struct mxs_platform_fb_entry *pentry, + void *data, int ret_prev) +{ + unsigned char *name = data; + if (!strcmp(pentry->name, name)) + ret_prev = (int)pentry; + return ret_prev; +} + +/* + * This routine actually sets the video mode. It's in here where we + * the hardware state info->par and fix which can be affected by the + * change in par. For this driver it doesn't do much. + * + * XXX: REVISIT + */ +static int mxsfb_set_par(struct fb_info *info) +{ + struct mxs_fb_data *data = (struct mxs_fb_data *)info; + struct mxs_platform_fb_data *pdata = data->pdata; + struct mxs_platform_fb_entry *pentry; + pentry = (void *)mxs_lcd_iterate_pdata(pdata, + get_matching_pentry, &info->var); + + dev_dbg(data->dev, "%s: xres %d, yres %d, bpp %d\n", + __func__, + info->var.xres, info->var.yres, info->var.bits_per_pixel); + if (!pentry) + return -EINVAL; + + info->fix.line_length = get_line_length(info->var.xres_virtual, + info->var.bits_per_pixel); + + if (pentry == pdata->cur || !pdata->cur) + return 0; + + /* init next panel */ + pdata->next = pentry; + + set_controller_state(data, F_REENABLE); + + return 0; +} + +static int mxsfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + u32 line_length; + struct mxs_fb_data *data = (struct mxs_fb_data *)info; + struct mxs_platform_fb_data *pdata = data->pdata; + + /* + * FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal! + * as FB_VMODE_SMOOTH_XPAN is only used internally + */ + + if (var->vmode & FB_VMODE_CONUPDATE) { + var->vmode |= FB_VMODE_YWRAP; + var->xoffset = info->var.xoffset; + var->yoffset = info->var.yoffset; + } + + pr_debug("%s: xres %d, yres %d, bpp %d\n", __func__, + var->xres, var->yres, var->bits_per_pixel); + /* + * Some very basic checks + */ + if (!var->xres) + var->xres = 1; + if (!var->yres) + var->yres = 1; + if (var->xres > var->xres_virtual) + var->xres_virtual = var->xres; + if (var->yres > var->yres_virtual) + var->yres_virtual = var->yres; + + if (var->xres_virtual < var->xoffset + var->xres) + var->xres_virtual = var->xoffset + var->xres; + if (var->yres_virtual < var->yoffset + var->yres) + var->yres_virtual = var->yoffset + var->yres; + + line_length = get_line_length(var->xres_virtual, var->bits_per_pixel); + dev_dbg(data->dev, + "line_length %d, var->yres_virtual %d, data->mem_size %d\n", + line_length, var->yres_virtual, data->mem_size); + if (line_length * var->yres_virtual > data->map_size) + return -ENOMEM; + + if (!mxs_lcd_iterate_pdata(pdata, get_matching_pentry, var)) + return -EINVAL; + + if (var->bits_per_pixel == 16) { + /* RGBA 5551 */ + if (var->transp.length) { + var->red.offset = 0; + var->red.length = 5; + var->green.offset = 5; + var->green.length = 5; + var->blue.offset = 10; + var->blue.length = 5; + var->transp.offset = 15; + var->transp.length = 1; + } else { /* RGB 565 */ + var->red.offset = 0; + var->red.length = 5; + var->green.offset = 5; + var->green.length = 6; + var->blue.offset = 11; + var->blue.length = 5; + var->transp.offset = 0; + var->transp.length = 0; + } + } else { + var->red.offset = 16; + var->red.length = 8; + var->green.offset = 8; + var->green.length = 8; + var->blue.offset = 0; + var->blue.length = 8; + } + + var->red.msb_right = 0; + var->green.msb_right = 0; + var->blue.msb_right = 0; + var->transp.msb_right = 0; + + return 0; +} + +static int mxsfb_wait_for_vsync(u32 channel, struct fb_info *info) +{ + struct mxs_fb_data *data = (struct mxs_fb_data *)info; + u32 count = data->vsync_count; + int ret = 0; + + __raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN, + data->regbase + HW_LCDIF_CTRL1_SET); + ret = wait_event_interruptible_timeout(data->vsync_wait_q, + count != data->vsync_count, + HZ / 10); + __raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN, + data->regbase + HW_LCDIF_CTRL1_CLR); + if (!ret) { + dev_err(data->dev, "wait for vsync timed out\n"); + ret = -ETIMEDOUT; + } + return ret; +} + +static int mxsfb_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg) +{ + u32 channel = 0; + int ret = -EINVAL; + + switch (cmd) { + case FBIO_WAITFORVSYNC: + if (!get_user(channel, (__u32 __user *) arg)) + ret = mxsfb_wait_for_vsync(channel, info); + break; + default: + break; + } + return ret; +} + +static int mxsfb_blank(int blank, struct fb_info *info) +{ + struct mxs_fb_data *data = (struct mxs_fb_data *)info; + int ret = 0; + + switch (blank) { + case FB_BLANK_NORMAL: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_POWERDOWN: + pr_debug("%s: FB_BLANK_POWERDOWN\n", __func__); + mxs_schedule_work(data, F_DISABLE); + break; + + case FB_BLANK_UNBLANK: + pr_debug("%s: FB_BLANK_UNBLANK\n", __func__); + mxs_schedule_work(data, F_ENABLE); + break; + + default: + ret = -EINVAL; + } + return ret; +} + +static int mxsfb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct mxs_fb_data *data = (struct mxs_fb_data *)info; + int ret = 0; + + pr_debug("%s: var->xoffset %d, info->var.xoffset %d\n", + __func__, var->xoffset, info->var.xoffset); + /* check if var is valid; also, xpan is not supported */ + if (!var || (var->xoffset != info->var.xoffset) || + (var->yoffset + var->yres > var->yres_virtual)) { + ret = -EINVAL; + goto out; + } + + if (!data->pdata->cur->pan_display) { + ret = -EINVAL; + goto out; + } + + /* update framebuffer visual */ + data->cur_phys = data->phys_start + + info->fix.line_length * var->yoffset; + data->pdata->cur->pan_display(data->cur_phys); +out: + return ret; +} + +static struct fb_ops mxsfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mxsfb_check_var, + .fb_set_par = mxsfb_set_par, + .fb_mmap = mxsfb_mmap, + .fb_setcolreg = mxsfb_setcolreg, + .fb_ioctl = mxsfb_ioctl, + .fb_blank = mxsfb_blank, + .fb_pan_display = mxsfb_pan_display, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +static void init_timings(struct mxs_fb_data *data) +{ + unsigned phase_time; + unsigned timings; + + /* Just use a phase_time of 1. As optimal as it gets, now. */ + phase_time = 1; + + /* Program all 4 timings the same */ + timings = phase_time; + timings |= timings << 8; + timings |= timings << 16; + __raw_writel(timings, data->regbase + HW_LCDIF_TIMING); +} + +#ifdef CONFIG_CPU_FREQ + +struct mxsfb_notifier_block { + struct mxs_fb_data *fb_data; + struct notifier_block nb; +}; + +static int mxsfb_notifier(struct notifier_block *self, + unsigned long phase, void *p) +{ + struct mxsfb_notifier_block *block = + container_of(self, struct mxsfb_notifier_block, nb); + struct mxs_fb_data *data = block->fb_data; + struct mxs_platform_fb_entry *pentry = data->pdata->cur; + u32 old_state = data->state; + + if (!data || !data->pdata || !data->pdata->cur) + return NOTIFY_BAD; + + /* REVISIT */ + switch (phase) { + case CPUFREQ_PRECHANGE: + if (old_state == F_ENABLE) + if (pentry->blank_panel) + pentry->blank_panel(FB_BLANK_POWERDOWN); + break; + + case CPUFREQ_POSTCHANGE: + if (old_state == F_ENABLE) + if (pentry->blank_panel) + pentry->blank_panel(FB_BLANK_UNBLANK); + break; + + default: + dev_dbg(data->dev, "didn't handle notify %ld\n", phase); + } + + return NOTIFY_DONE; +} + +static struct mxsfb_notifier_block mxsfb_nb = { + .nb = { + .notifier_call = mxsfb_notifier, + }, +}; +#endif /* CONFIG_CPU_FREQ */ + +static int get_max_memsize(struct mxs_platform_fb_entry *pentry, + void *data, int ret_prev) +{ + struct mxs_fb_data *fbdata = data; + int sz = pentry->x_res * pentry->y_res * pentry->bpp / 8; + fbdata->mem_size = sz < ret_prev ? ret_prev : sz; + pr_debug("%s: mem_size now %d\n", __func__, fbdata->mem_size); + return fbdata->mem_size; +} + +static int __devinit mxsfb_probe(struct platform_device *pdev) +{ + int ret = 0; + struct mxs_fb_data *data; + struct resource *res; + struct fb_info *info; + struct mxs_platform_fb_data *pdata = pdev->dev.platform_data; + struct mxs_platform_fb_entry *pentry = NULL; + + if (pdata == NULL) { + ret = -ENODEV; + goto out; + } + + if (default_panel_name) { + pentry = (void *)mxs_lcd_iterate_pdata(pdata, + get_matching_pentry_by_name, + default_panel_name); + if (pentry) { + mxs_lcd_move_pentry_up(pentry, pdata); + pdata->cur = pentry; + } + } + if (!default_panel_name || !pentry) + pentry = pdata->cur; + if (!pentry || !pentry->init_panel || !pentry->run_panel || + !pentry->release_panel) { + ret = -EINVAL; + goto out; + } + + data = + (struct mxs_fb_data *)framebuffer_alloc(sizeof(struct mxs_fb_data) + + sizeof(u32) * 256 - + sizeof(struct fb_info), + &pdev->dev); + if (data == NULL) { + ret = -ENOMEM; + goto out; + } + + cdata = data; + data->dev = &pdev->dev; + data->pdata = pdata; + platform_set_drvdata(pdev, data); + info = &data->info; + + dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n", pentry->x_res, + pentry->y_res, pentry->bpp); + + mxs_lcd_iterate_pdata(pdata, get_max_memsize, data); + + data->map_size = PAGE_ALIGN(data->mem_size) * NUM_SCREENS; + dev_dbg(&pdev->dev, "memory to allocate: %d\n", data->map_size); + + data->virt_start = dma_alloc_writecombine(&pdev->dev, + data->map_size, + &data->phys_start, + GFP_KERNEL); + + if (data->virt_start == NULL) { + ret = -ENOMEM; + goto out_dma; + } + dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", data->virt_start, + data->phys_start); + mutex_init(&data->blank_mutex); + INIT_WORK(&data->work, mxsfb_task); + data->state = F_ENABLE; + + mxsfb_default.bits_per_pixel = pentry->bpp; + /* NB: rotated */ + mxsfb_default.xres = pentry->y_res; + mxsfb_default.yres = pentry->x_res; + mxsfb_default.xres_virtual = pentry->y_res; + mxsfb_default.yres_virtual = data->map_size / + (pentry->y_res * pentry->bpp / 8); + if (mxsfb_default.yres_virtual >= mxsfb_default.yres * 2) + mxsfb_default.yres_virtual = mxsfb_default.yres * 2; + else + mxsfb_default.yres_virtual = mxsfb_default.yres; + + mxsfb_fix.smem_start = data->phys_start; + mxsfb_fix.smem_len = pentry->y_res * pentry->x_res * pentry->bpp / 8; + mxsfb_fix.ypanstep = 1; + + switch (pentry->bpp) { + case 32: + case 24: + mxsfb_default.red.offset = 16; + mxsfb_default.red.length = 8; + mxsfb_default.green.offset = 8; + mxsfb_default.green.length = 8; + mxsfb_default.blue.offset = 0; + mxsfb_default.blue.length = 8; + break; + + case 16: + mxsfb_default.red.offset = 11; + mxsfb_default.red.length = 5; + mxsfb_default.green.offset = 5; + mxsfb_default.green.length = 6; + mxsfb_default.blue.offset = 0; + mxsfb_default.blue.length = 5; + break; + + default: + dev_err(&pdev->dev, "unsupported bitwidth %d\n", pentry->bpp); + ret = -EINVAL; + goto out_dma; + } + + info->screen_base = data->virt_start; + info->fbops = &mxsfb_ops; + info->var = mxsfb_default; + info->fix = mxsfb_fix; + info->pseudo_palette = &data->par; + data->par = NULL; + info->flags = FBINFO_FLAG_DEFAULT; + + init_waitqueue_head(&data->vsync_wait_q); + data->vsync_count = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "cannot get IRQ resource\n"); + ret = -ENODEV; + goto out_dma; + } + data->regbase = (unsigned long)IO_ADDRESS(res->start); + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&pdev->dev, "cannot get IRQ resource\n"); + ret = -ENODEV; + goto out_dma; + } + data->irq = res->start; + + mxsfb_check_var(&info->var, info); + + ret = fb_alloc_cmap(&info->cmap, 256, 0); + if (ret) + goto out_cmap; + + mxsfb_set_par(info); + + mxs_init_lcdif(); + ret = pentry->init_panel(data->dev, data->phys_start, + mxsfb_fix.smem_len, pentry); + if (ret) { + dev_err(&pdev->dev, "cannot initialize LCD panel\n"); + goto out_panel; + } + dev_dbg(&pdev->dev, "LCD panel initialized\n"); + init_timings(data); + + ret = request_irq(data->irq, lcd_irq_handler, 0, "fb_irq", data); + if (ret) { + dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n", + data->irq, ret); + goto out_panel; + } + ret = register_framebuffer(info); + if (ret) + goto out_irq; + + pentry->run_panel(); + /* REVISIT: temporary workaround for MX23EVK */ + mxsfb_disable_controller(data); + mxsfb_enable_controller(data); + data->cur_phys = data->phys_start; + dev_dbg(&pdev->dev, "LCD running now\n"); + +#ifdef CONFIG_CPU_FREQ + mxsfb_nb.fb_data = data; + cpufreq_register_notifier(&mxsfb_nb.nb, CPUFREQ_TRANSITION_NOTIFIER); +#endif /* CONFIG_CPU_FREQ */ + + goto out; + +out_irq: + free_irq(data->irq, data); +out_panel: + fb_dealloc_cmap(&info->cmap); +out_cmap: + dma_free_writecombine(&pdev->dev, data->map_size, data->virt_start, + data->phys_start); +out_dma: + kfree(data); +out: + return ret; +} + +static int mxsfb_remove(struct platform_device *pdev) +{ + struct mxs_fb_data *data = platform_get_drvdata(pdev); + + set_controller_state(data, F_DISABLE); + + unregister_framebuffer(&data->info); + framebuffer_release(&data->info); + fb_dealloc_cmap(&data->info.cmap); + free_irq(data->irq, data); + dma_free_writecombine(&pdev->dev, data->map_size, data->virt_start, + data->phys_start); + kfree(data); + platform_set_drvdata(pdev, NULL); + return 0; +} + +#ifdef CONFIG_PM +static int mxsfb_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct mxs_fb_data *data = platform_get_drvdata(pdev); + + set_controller_state(data, F_DISABLE); + + return 0; +} + +static int mxsfb_resume(struct platform_device *pdev) +{ + struct mxs_fb_data *data = platform_get_drvdata(pdev); + + set_controller_state(data, F_ENABLE); + return 0; +} +#else +#define mxsfb_suspend NULL +#define mxsfb_resume NULL +#endif + +static struct platform_driver mxsfb_driver = { + .probe = mxsfb_probe, + .remove = mxsfb_remove, + .suspend = mxsfb_suspend, + .resume = mxsfb_resume, + .driver = { + .name = "mxs-fb", + .owner = THIS_MODULE, + }, +}; + +static int __init mxsfb_init(void) +{ + return platform_driver_register(&mxsfb_driver); +} + +static void __exit mxsfb_exit(void) +{ + platform_driver_unregister(&mxsfb_driver); +} + +module_init(mxsfb_init); +module_exit(mxsfb_exit); + +/* + * LCD panel select + */ +static int __init default_panel_select(char *str) +{ + default_panel_name = str; + return 0; +} + +__setup("lcd_panel=", default_panel_select); + +MODULE_AUTHOR("Vitaly Wool "); +MODULE_DESCRIPTION("MXS Framebuffer Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/mxs/regs-tvenc.h b/drivers/video/mxs/regs-tvenc.h new file mode 100644 index 000000000000..bd2493e2dee5 --- /dev/null +++ b/drivers/video/mxs/regs-tvenc.h @@ -0,0 +1,583 @@ +/* + * Freescale TVENC Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.00 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___TVENC_H +#define __ARCH_ARM___TVENC_H + + +#define HW_TVENC_CTRL (0x00000000) +#define HW_TVENC_CTRL_SET (0x00000004) +#define HW_TVENC_CTRL_CLR (0x00000008) +#define HW_TVENC_CTRL_TOG (0x0000000c) + +#define BM_TVENC_CTRL_SFTRST 0x80000000 +#define BM_TVENC_CTRL_CLKGATE 0x40000000 +#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT 0x20000000 +#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT 0x10000000 +#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT 0x08000000 +#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT 0x04000000 +#define BP_TVENC_CTRL_RSRVD1 6 +#define BM_TVENC_CTRL_RSRVD1 0x03FFFFC0 +#define BF_TVENC_CTRL_RSRVD1(v) \ + (((v) << 6) & BM_TVENC_CTRL_RSRVD1) +#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE 0x00000020 +#define BM_TVENC_CTRL_DAC_FIFO_NO_READ 0x00000010 +#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST 0x00000008 +#define BP_TVENC_CTRL_RSRVD2 1 +#define BM_TVENC_CTRL_RSRVD2 0x00000006 +#define BF_TVENC_CTRL_RSRVD2(v) \ + (((v) << 1) & BM_TVENC_CTRL_RSRVD2) +#define BM_TVENC_CTRL_DAC_MUX_MODE 0x00000001 + +#define HW_TVENC_CONFIG (0x00000010) +#define HW_TVENC_CONFIG_SET (0x00000014) +#define HW_TVENC_CONFIG_CLR (0x00000018) +#define HW_TVENC_CONFIG_TOG (0x0000001c) + +#define BP_TVENC_CONFIG_RSRVD5 28 +#define BM_TVENC_CONFIG_RSRVD5 0xF0000000 +#define BF_TVENC_CONFIG_RSRVD5(v) \ + (((v) << 28) & BM_TVENC_CONFIG_RSRVD5) +#define BM_TVENC_CONFIG_DEFAULT_PICFORM 0x08000000 +#define BP_TVENC_CONFIG_YDEL_ADJ 24 +#define BM_TVENC_CONFIG_YDEL_ADJ 0x07000000 +#define BF_TVENC_CONFIG_YDEL_ADJ(v) \ + (((v) << 24) & BM_TVENC_CONFIG_YDEL_ADJ) +#define BM_TVENC_CONFIG_RSRVD4 0x00800000 +#define BM_TVENC_CONFIG_RSRVD3 0x00400000 +#define BM_TVENC_CONFIG_ADD_YPBPR_PED 0x00200000 +#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000 +#define BM_TVENC_CONFIG_NO_PED 0x00080000 +#define BM_TVENC_CONFIG_COLOR_BAR_EN 0x00040000 +#define BP_TVENC_CONFIG_YGAIN_SEL 16 +#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000 +#define BF_TVENC_CONFIG_YGAIN_SEL(v) \ + (((v) << 16) & BM_TVENC_CONFIG_YGAIN_SEL) +#define BP_TVENC_CONFIG_CGAIN 14 +#define BM_TVENC_CONFIG_CGAIN 0x0000C000 +#define BF_TVENC_CONFIG_CGAIN(v) \ + (((v) << 14) & BM_TVENC_CONFIG_CGAIN) +#define BP_TVENC_CONFIG_CLK_PHS 12 +#define BM_TVENC_CONFIG_CLK_PHS 0x00003000 +#define BF_TVENC_CONFIG_CLK_PHS(v) \ + (((v) << 12) & BM_TVENC_CONFIG_CLK_PHS) +#define BM_TVENC_CONFIG_RSRVD2 0x00000800 +#define BM_TVENC_CONFIG_FSYNC_ENBL 0x00000400 +#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200 +#define BM_TVENC_CONFIG_HSYNC_PHS 0x00000100 +#define BM_TVENC_CONFIG_VSYNC_PHS 0x00000080 +#define BP_TVENC_CONFIG_SYNC_MODE 4 +#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070 +#define BF_TVENC_CONFIG_SYNC_MODE(v) \ + (((v) << 4) & BM_TVENC_CONFIG_SYNC_MODE) +#define BM_TVENC_CONFIG_RSRVD1 0x00000008 +#define BP_TVENC_CONFIG_ENCD_MODE 0 +#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007 +#define BF_TVENC_CONFIG_ENCD_MODE(v) \ + (((v) << 0) & BM_TVENC_CONFIG_ENCD_MODE) + +#define HW_TVENC_FILTCTRL (0x00000020) +#define HW_TVENC_FILTCTRL_SET (0x00000024) +#define HW_TVENC_FILTCTRL_CLR (0x00000028) +#define HW_TVENC_FILTCTRL_TOG (0x0000002c) + +#define BP_TVENC_FILTCTRL_RSRVD1 20 +#define BM_TVENC_FILTCTRL_RSRVD1 0xFFF00000 +#define BF_TVENC_FILTCTRL_RSRVD1(v) \ + (((v) << 20) & BM_TVENC_FILTCTRL_RSRVD1) +#define BM_TVENC_FILTCTRL_YSHARP_BW 0x00080000 +#define BM_TVENC_FILTCTRL_YD_OFFSETSEL 0x00040000 +#define BM_TVENC_FILTCTRL_SEL_YLPF 0x00020000 +#define BM_TVENC_FILTCTRL_SEL_CLPF 0x00010000 +#define BM_TVENC_FILTCTRL_SEL_YSHARP 0x00008000 +#define BM_TVENC_FILTCTRL_YLPF_COEFSEL 0x00004000 +#define BM_TVENC_FILTCTRL_COEFSEL_CLPF 0x00002000 +#define BM_TVENC_FILTCTRL_YS_GAINSGN 0x00001000 +#define BP_TVENC_FILTCTRL_YS_GAINSEL 10 +#define BM_TVENC_FILTCTRL_YS_GAINSEL 0x00000C00 +#define BF_TVENC_FILTCTRL_YS_GAINSEL(v) \ + (((v) << 10) & BM_TVENC_FILTCTRL_YS_GAINSEL) +#define BM_TVENC_FILTCTRL_RSRVD2 0x00000200 +#define BM_TVENC_FILTCTRL_RSRVD3 0x00000100 +#define BP_TVENC_FILTCTRL_RSRVD4 0 +#define BM_TVENC_FILTCTRL_RSRVD4 0x000000FF +#define BF_TVENC_FILTCTRL_RSRVD4(v) \ + (((v) << 0) & BM_TVENC_FILTCTRL_RSRVD4) + +#define HW_TVENC_SYNCOFFSET (0x00000030) +#define HW_TVENC_SYNCOFFSET_SET (0x00000034) +#define HW_TVENC_SYNCOFFSET_CLR (0x00000038) +#define HW_TVENC_SYNCOFFSET_TOG (0x0000003c) + +#define BM_TVENC_SYNCOFFSET_RSRVD1 0x80000000 +#define BP_TVENC_SYNCOFFSET_HSO 20 +#define BM_TVENC_SYNCOFFSET_HSO 0x7FF00000 +#define BF_TVENC_SYNCOFFSET_HSO(v) \ + (((v) << 20) & BM_TVENC_SYNCOFFSET_HSO) +#define BP_TVENC_SYNCOFFSET_VSO 10 +#define BM_TVENC_SYNCOFFSET_VSO 0x000FFC00 +#define BF_TVENC_SYNCOFFSET_VSO(v) \ + (((v) << 10) & BM_TVENC_SYNCOFFSET_VSO) +#define BP_TVENC_SYNCOFFSET_HLC 0 +#define BM_TVENC_SYNCOFFSET_HLC 0x000003FF +#define BF_TVENC_SYNCOFFSET_HLC(v) \ + (((v) << 0) & BM_TVENC_SYNCOFFSET_HLC) + +#define HW_TVENC_HTIMINGSYNC0 (0x00000040) +#define HW_TVENC_HTIMINGSYNC0_SET (0x00000044) +#define HW_TVENC_HTIMINGSYNC0_CLR (0x00000048) +#define HW_TVENC_HTIMINGSYNC0_TOG (0x0000004c) + +#define BP_TVENC_HTIMINGSYNC0_RSRVD2 26 +#define BM_TVENC_HTIMINGSYNC0_RSRVD2 0xFC000000 +#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v) \ + (((v) << 26) & BM_TVENC_HTIMINGSYNC0_RSRVD2) +#define BP_TVENC_HTIMINGSYNC0_SYNC_END 16 +#define BM_TVENC_HTIMINGSYNC0_SYNC_END 0x03FF0000 +#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v) \ + (((v) << 16) & BM_TVENC_HTIMINGSYNC0_SYNC_END) +#define BP_TVENC_HTIMINGSYNC0_RSRVD1 10 +#define BM_TVENC_HTIMINGSYNC0_RSRVD1 0x0000FC00 +#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGSYNC0_RSRVD1) +#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT 0 +#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT 0x000003FF +#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v) \ + (((v) << 0) & BM_TVENC_HTIMINGSYNC0_SYNC_STRT) + +#define HW_TVENC_HTIMINGSYNC1 (0x00000050) +#define HW_TVENC_HTIMINGSYNC1_SET (0x00000054) +#define HW_TVENC_HTIMINGSYNC1_CLR (0x00000058) +#define HW_TVENC_HTIMINGSYNC1_TOG (0x0000005c) + +#define BP_TVENC_HTIMINGSYNC1_RSRVD2 26 +#define BM_TVENC_HTIMINGSYNC1_RSRVD2 0xFC000000 +#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v) \ + (((v) << 26) & BM_TVENC_HTIMINGSYNC1_RSRVD2) +#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND 16 +#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND 0x03FF0000 +#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v) \ + (((v) << 16) & BM_TVENC_HTIMINGSYNC1_SYNC_EQEND) +#define BP_TVENC_HTIMINGSYNC1_RSRVD1 10 +#define BM_TVENC_HTIMINGSYNC1_RSRVD1 0x0000FC00 +#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGSYNC1_RSRVD1) +#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND 0 +#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND 0x000003FF +#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v) \ + (((v) << 0) & BM_TVENC_HTIMINGSYNC1_SYNC_SREND) + +#define HW_TVENC_HTIMINGACTIVE (0x00000060) +#define HW_TVENC_HTIMINGACTIVE_SET (0x00000064) +#define HW_TVENC_HTIMINGACTIVE_CLR (0x00000068) +#define HW_TVENC_HTIMINGACTIVE_TOG (0x0000006c) + +#define BP_TVENC_HTIMINGACTIVE_RSRVD2 26 +#define BM_TVENC_HTIMINGACTIVE_RSRVD2 0xFC000000 +#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v) \ + (((v) << 26) & BM_TVENC_HTIMINGACTIVE_RSRVD2) +#define BP_TVENC_HTIMINGACTIVE_ACTV_END 16 +#define BM_TVENC_HTIMINGACTIVE_ACTV_END 0x03FF0000 +#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v) \ + (((v) << 16) & BM_TVENC_HTIMINGACTIVE_ACTV_END) +#define BP_TVENC_HTIMINGACTIVE_RSRVD1 10 +#define BM_TVENC_HTIMINGACTIVE_RSRVD1 0x0000FC00 +#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGACTIVE_RSRVD1) +#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT 0 +#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT 0x000003FF +#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v) \ + (((v) << 0) & BM_TVENC_HTIMINGACTIVE_ACTV_STRT) + +#define HW_TVENC_HTIMINGBURST0 (0x00000070) +#define HW_TVENC_HTIMINGBURST0_SET (0x00000074) +#define HW_TVENC_HTIMINGBURST0_CLR (0x00000078) +#define HW_TVENC_HTIMINGBURST0_TOG (0x0000007c) + +#define BP_TVENC_HTIMINGBURST0_RSRVD2 26 +#define BM_TVENC_HTIMINGBURST0_RSRVD2 0xFC000000 +#define BF_TVENC_HTIMINGBURST0_RSRVD2(v) \ + (((v) << 26) & BM_TVENC_HTIMINGBURST0_RSRVD2) +#define BP_TVENC_HTIMINGBURST0_WBRST_STRT 16 +#define BM_TVENC_HTIMINGBURST0_WBRST_STRT 0x03FF0000 +#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v) \ + (((v) << 16) & BM_TVENC_HTIMINGBURST0_WBRST_STRT) +#define BP_TVENC_HTIMINGBURST0_RSRVD1 10 +#define BM_TVENC_HTIMINGBURST0_RSRVD1 0x0000FC00 +#define BF_TVENC_HTIMINGBURST0_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGBURST0_RSRVD1) +#define BP_TVENC_HTIMINGBURST0_NBRST_STRT 0 +#define BM_TVENC_HTIMINGBURST0_NBRST_STRT 0x000003FF +#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v) \ + (((v) << 0) & BM_TVENC_HTIMINGBURST0_NBRST_STRT) + +#define HW_TVENC_HTIMINGBURST1 (0x00000080) +#define HW_TVENC_HTIMINGBURST1_SET (0x00000084) +#define HW_TVENC_HTIMINGBURST1_CLR (0x00000088) +#define HW_TVENC_HTIMINGBURST1_TOG (0x0000008c) + +#define BP_TVENC_HTIMINGBURST1_RSRVD1 10 +#define BM_TVENC_HTIMINGBURST1_RSRVD1 0xFFFFFC00 +#define BF_TVENC_HTIMINGBURST1_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGBURST1_RSRVD1) +#define BP_TVENC_HTIMINGBURST1_BRST_END 0 +#define BM_TVENC_HTIMINGBURST1_BRST_END 0x000003FF +#define BF_TVENC_HTIMINGBURST1_BRST_END(v) \ + (((v) << 0) & BM_TVENC_HTIMINGBURST1_BRST_END) + +#define HW_TVENC_VTIMING0 (0x00000090) +#define HW_TVENC_VTIMING0_SET (0x00000094) +#define HW_TVENC_VTIMING0_CLR (0x00000098) +#define HW_TVENC_VTIMING0_TOG (0x0000009c) + +#define BP_TVENC_VTIMING0_RSRVD3 26 +#define BM_TVENC_VTIMING0_RSRVD3 0xFC000000 +#define BF_TVENC_VTIMING0_RSRVD3(v) \ + (((v) << 26) & BM_TVENC_VTIMING0_RSRVD3) +#define BP_TVENC_VTIMING0_VSTRT_PREEQ 16 +#define BM_TVENC_VTIMING0_VSTRT_PREEQ 0x03FF0000 +#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v) \ + (((v) << 16) & BM_TVENC_VTIMING0_VSTRT_PREEQ) +#define BP_TVENC_VTIMING0_RSRVD2 14 +#define BM_TVENC_VTIMING0_RSRVD2 0x0000C000 +#define BF_TVENC_VTIMING0_RSRVD2(v) \ + (((v) << 14) & BM_TVENC_VTIMING0_RSRVD2) +#define BP_TVENC_VTIMING0_VSTRT_ACTV 8 +#define BM_TVENC_VTIMING0_VSTRT_ACTV 0x00003F00 +#define BF_TVENC_VTIMING0_VSTRT_ACTV(v) \ + (((v) << 8) & BM_TVENC_VTIMING0_VSTRT_ACTV) +#define BP_TVENC_VTIMING0_RSRVD1 6 +#define BM_TVENC_VTIMING0_RSRVD1 0x000000C0 +#define BF_TVENC_VTIMING0_RSRVD1(v) \ + (((v) << 6) & BM_TVENC_VTIMING0_RSRVD1) +#define BP_TVENC_VTIMING0_VSTRT_SUBPH 0 +#define BM_TVENC_VTIMING0_VSTRT_SUBPH 0x0000003F +#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v) \ + (((v) << 0) & BM_TVENC_VTIMING0_VSTRT_SUBPH) + +#define HW_TVENC_VTIMING1 (0x000000a0) +#define HW_TVENC_VTIMING1_SET (0x000000a4) +#define HW_TVENC_VTIMING1_CLR (0x000000a8) +#define HW_TVENC_VTIMING1_TOG (0x000000ac) + +#define BP_TVENC_VTIMING1_RSRVD3 30 +#define BM_TVENC_VTIMING1_RSRVD3 0xC0000000 +#define BF_TVENC_VTIMING1_RSRVD3(v) \ + (((v) << 30) & BM_TVENC_VTIMING1_RSRVD3) +#define BP_TVENC_VTIMING1_VSTRT_POSTEQ 24 +#define BM_TVENC_VTIMING1_VSTRT_POSTEQ 0x3F000000 +#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v) \ + (((v) << 24) & BM_TVENC_VTIMING1_VSTRT_POSTEQ) +#define BP_TVENC_VTIMING1_RSRVD2 22 +#define BM_TVENC_VTIMING1_RSRVD2 0x00C00000 +#define BF_TVENC_VTIMING1_RSRVD2(v) \ + (((v) << 22) & BM_TVENC_VTIMING1_RSRVD2) +#define BP_TVENC_VTIMING1_VSTRT_SERRA 16 +#define BM_TVENC_VTIMING1_VSTRT_SERRA 0x003F0000 +#define BF_TVENC_VTIMING1_VSTRT_SERRA(v) \ + (((v) << 16) & BM_TVENC_VTIMING1_VSTRT_SERRA) +#define BP_TVENC_VTIMING1_RSRVD1 10 +#define BM_TVENC_VTIMING1_RSRVD1 0x0000FC00 +#define BF_TVENC_VTIMING1_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_VTIMING1_RSRVD1) +#define BP_TVENC_VTIMING1_LAST_FLD_LN 0 +#define BM_TVENC_VTIMING1_LAST_FLD_LN 0x000003FF +#define BF_TVENC_VTIMING1_LAST_FLD_LN(v) \ + (((v) << 0) & BM_TVENC_VTIMING1_LAST_FLD_LN) + +#define HW_TVENC_MISC (0x000000b0) +#define HW_TVENC_MISC_SET (0x000000b4) +#define HW_TVENC_MISC_CLR (0x000000b8) +#define HW_TVENC_MISC_TOG (0x000000bc) + +#define BP_TVENC_MISC_RSRVD3 25 +#define BM_TVENC_MISC_RSRVD3 0xFE000000 +#define BF_TVENC_MISC_RSRVD3(v) \ + (((v) << 25) & BM_TVENC_MISC_RSRVD3) +#define BP_TVENC_MISC_LPF_RST_OFF 16 +#define BM_TVENC_MISC_LPF_RST_OFF 0x01FF0000 +#define BF_TVENC_MISC_LPF_RST_OFF(v) \ + (((v) << 16) & BM_TVENC_MISC_LPF_RST_OFF) +#define BP_TVENC_MISC_RSRVD2 12 +#define BM_TVENC_MISC_RSRVD2 0x0000F000 +#define BF_TVENC_MISC_RSRVD2(v) \ + (((v) << 12) & BM_TVENC_MISC_RSRVD2) +#define BM_TVENC_MISC_NTSC_LN_CNT 0x00000800 +#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT 0x00000400 +#define BP_TVENC_MISC_FSC_PHASE_RST 8 +#define BM_TVENC_MISC_FSC_PHASE_RST 0x00000300 +#define BF_TVENC_MISC_FSC_PHASE_RST(v) \ + (((v) << 8) & BM_TVENC_MISC_FSC_PHASE_RST) +#define BP_TVENC_MISC_BRUCHB 6 +#define BM_TVENC_MISC_BRUCHB 0x000000C0 +#define BF_TVENC_MISC_BRUCHB(v) \ + (((v) << 6) & BM_TVENC_MISC_BRUCHB) +#define BP_TVENC_MISC_AGC_LVL_CTRL 4 +#define BM_TVENC_MISC_AGC_LVL_CTRL 0x00000030 +#define BF_TVENC_MISC_AGC_LVL_CTRL(v) \ + (((v) << 4) & BM_TVENC_MISC_AGC_LVL_CTRL) +#define BM_TVENC_MISC_RSRVD1 0x00000008 +#define BM_TVENC_MISC_CS_INVERT_CTRL 0x00000004 +#define BP_TVENC_MISC_Y_BLANK_CTRL 0 +#define BM_TVENC_MISC_Y_BLANK_CTRL 0x00000003 +#define BF_TVENC_MISC_Y_BLANK_CTRL(v) \ + (((v) << 0) & BM_TVENC_MISC_Y_BLANK_CTRL) + +#define HW_TVENC_COLORSUB0 (0x000000c0) +#define HW_TVENC_COLORSUB0_SET (0x000000c4) +#define HW_TVENC_COLORSUB0_CLR (0x000000c8) +#define HW_TVENC_COLORSUB0_TOG (0x000000cc) + +#define BP_TVENC_COLORSUB0_PHASE_INC 0 +#define BM_TVENC_COLORSUB0_PHASE_INC 0xFFFFFFFF +#define BF_TVENC_COLORSUB0_PHASE_INC(v) (v) + +#define HW_TVENC_COLORSUB1 (0x000000d0) +#define HW_TVENC_COLORSUB1_SET (0x000000d4) +#define HW_TVENC_COLORSUB1_CLR (0x000000d8) +#define HW_TVENC_COLORSUB1_TOG (0x000000dc) + +#define BP_TVENC_COLORSUB1_PHASE_OFFSET 0 +#define BM_TVENC_COLORSUB1_PHASE_OFFSET 0xFFFFFFFF +#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v) (v) + +#define HW_TVENC_COPYPROTECT (0x000000e0) +#define HW_TVENC_COPYPROTECT_SET (0x000000e4) +#define HW_TVENC_COPYPROTECT_CLR (0x000000e8) +#define HW_TVENC_COPYPROTECT_TOG (0x000000ec) + +#define BP_TVENC_COPYPROTECT_RSRVD1 16 +#define BM_TVENC_COPYPROTECT_RSRVD1 0xFFFF0000 +#define BF_TVENC_COPYPROTECT_RSRVD1(v) \ + (((v) << 16) & BM_TVENC_COPYPROTECT_RSRVD1) +#define BM_TVENC_COPYPROTECT_WSS_ENBL 0x00008000 +#define BM_TVENC_COPYPROTECT_CGMS_ENBL 0x00004000 +#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA 0 +#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA 0x00003FFF +#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v) \ + (((v) << 0) & BM_TVENC_COPYPROTECT_WSS_CGMS_DATA) + +#define HW_TVENC_CLOSEDCAPTION (0x000000f0) +#define HW_TVENC_CLOSEDCAPTION_SET (0x000000f4) +#define HW_TVENC_CLOSEDCAPTION_CLR (0x000000f8) +#define HW_TVENC_CLOSEDCAPTION_TOG (0x000000fc) + +#define BP_TVENC_CLOSEDCAPTION_RSRVD1 20 +#define BM_TVENC_CLOSEDCAPTION_RSRVD1 0xFFF00000 +#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v) \ + (((v) << 20) & BM_TVENC_CLOSEDCAPTION_RSRVD1) +#define BP_TVENC_CLOSEDCAPTION_CC_ENBL 18 +#define BM_TVENC_CLOSEDCAPTION_CC_ENBL 0x000C0000 +#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v) \ + (((v) << 18) & BM_TVENC_CLOSEDCAPTION_CC_ENBL) +#define BP_TVENC_CLOSEDCAPTION_CC_FILL 16 +#define BM_TVENC_CLOSEDCAPTION_CC_FILL 0x00030000 +#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v) \ + (((v) << 16) & BM_TVENC_CLOSEDCAPTION_CC_FILL) +#define BP_TVENC_CLOSEDCAPTION_CC_DATA 0 +#define BM_TVENC_CLOSEDCAPTION_CC_DATA 0x0000FFFF +#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v) \ + (((v) << 0) & BM_TVENC_CLOSEDCAPTION_CC_DATA) + +#define HW_TVENC_COLORBURST (0x00000140) +#define HW_TVENC_COLORBURST_SET (0x00000144) +#define HW_TVENC_COLORBURST_CLR (0x00000148) +#define HW_TVENC_COLORBURST_TOG (0x0000014c) + +#define BP_TVENC_COLORBURST_NBA 24 +#define BM_TVENC_COLORBURST_NBA 0xFF000000 +#define BF_TVENC_COLORBURST_NBA(v) \ + (((v) << 24) & BM_TVENC_COLORBURST_NBA) +#define BP_TVENC_COLORBURST_PBA 16 +#define BM_TVENC_COLORBURST_PBA 0x00FF0000 +#define BF_TVENC_COLORBURST_PBA(v) \ + (((v) << 16) & BM_TVENC_COLORBURST_PBA) +#define BP_TVENC_COLORBURST_RSRVD1 12 +#define BM_TVENC_COLORBURST_RSRVD1 0x0000F000 +#define BF_TVENC_COLORBURST_RSRVD1(v) \ + (((v) << 12) & BM_TVENC_COLORBURST_RSRVD1) +#define BP_TVENC_COLORBURST_RSRVD2 0 +#define BM_TVENC_COLORBURST_RSRVD2 0x00000FFF +#define BF_TVENC_COLORBURST_RSRVD2(v) \ + (((v) << 0) & BM_TVENC_COLORBURST_RSRVD2) + +#define HW_TVENC_MACROVISION0 (0x00000150) +#define HW_TVENC_MACROVISION0_SET (0x00000154) +#define HW_TVENC_MACROVISION0_CLR (0x00000158) +#define HW_TVENC_MACROVISION0_TOG (0x0000015c) + +#define BP_TVENC_MACROVISION0_DATA 0 +#define BM_TVENC_MACROVISION0_DATA 0xFFFFFFFF +#define BF_TVENC_MACROVISION0_DATA(v) (v) + +#define HW_TVENC_MACROVISION1 (0x00000160) +#define HW_TVENC_MACROVISION1_SET (0x00000164) +#define HW_TVENC_MACROVISION1_CLR (0x00000168) +#define HW_TVENC_MACROVISION1_TOG (0x0000016c) + +#define BP_TVENC_MACROVISION1_DATA 0 +#define BM_TVENC_MACROVISION1_DATA 0xFFFFFFFF +#define BF_TVENC_MACROVISION1_DATA(v) (v) + +#define HW_TVENC_MACROVISION2 (0x00000170) +#define HW_TVENC_MACROVISION2_SET (0x00000174) +#define HW_TVENC_MACROVISION2_CLR (0x00000178) +#define HW_TVENC_MACROVISION2_TOG (0x0000017c) + +#define BP_TVENC_MACROVISION2_DATA 0 +#define BM_TVENC_MACROVISION2_DATA 0xFFFFFFFF +#define BF_TVENC_MACROVISION2_DATA(v) (v) + +#define HW_TVENC_MACROVISION3 (0x00000180) +#define HW_TVENC_MACROVISION3_SET (0x00000184) +#define HW_TVENC_MACROVISION3_CLR (0x00000188) +#define HW_TVENC_MACROVISION3_TOG (0x0000018c) + +#define BP_TVENC_MACROVISION3_DATA 0 +#define BM_TVENC_MACROVISION3_DATA 0xFFFFFFFF +#define BF_TVENC_MACROVISION3_DATA(v) (v) + +#define HW_TVENC_MACROVISION4 (0x00000190) +#define HW_TVENC_MACROVISION4_SET (0x00000194) +#define HW_TVENC_MACROVISION4_CLR (0x00000198) +#define HW_TVENC_MACROVISION4_TOG (0x0000019c) + +#define BP_TVENC_MACROVISION4_RSRVD2 24 +#define BM_TVENC_MACROVISION4_RSRVD2 0xFF000000 +#define BF_TVENC_MACROVISION4_RSRVD2(v) \ + (((v) << 24) & BM_TVENC_MACROVISION4_RSRVD2) +#define BP_TVENC_MACROVISION4_MACV_TST 16 +#define BM_TVENC_MACROVISION4_MACV_TST 0x00FF0000 +#define BF_TVENC_MACROVISION4_MACV_TST(v) \ + (((v) << 16) & BM_TVENC_MACROVISION4_MACV_TST) +#define BP_TVENC_MACROVISION4_RSRVD1 11 +#define BM_TVENC_MACROVISION4_RSRVD1 0x0000F800 +#define BF_TVENC_MACROVISION4_RSRVD1(v) \ + (((v) << 11) & BM_TVENC_MACROVISION4_RSRVD1) +#define BP_TVENC_MACROVISION4_DATA 0 +#define BM_TVENC_MACROVISION4_DATA 0x000007FF +#define BF_TVENC_MACROVISION4_DATA(v) \ + (((v) << 0) & BM_TVENC_MACROVISION4_DATA) + +#define HW_TVENC_DACCTRL (0x000001a0) +#define HW_TVENC_DACCTRL_SET (0x000001a4) +#define HW_TVENC_DACCTRL_CLR (0x000001a8) +#define HW_TVENC_DACCTRL_TOG (0x000001ac) + +#define BM_TVENC_DACCTRL_TEST3 0x80000000 +#define BM_TVENC_DACCTRL_RSRVD1 0x40000000 +#define BM_TVENC_DACCTRL_RSRVD2 0x20000000 +#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN 0x10000000 +#define BM_TVENC_DACCTRL_TEST2 0x08000000 +#define BM_TVENC_DACCTRL_RSRVD3 0x04000000 +#define BM_TVENC_DACCTRL_RSRVD4 0x02000000 +#define BM_TVENC_DACCTRL_JACK1_DET_EN 0x01000000 +#define BM_TVENC_DACCTRL_TEST1 0x00800000 +#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT 0x00400000 +#define BP_TVENC_DACCTRL_JACK_DIS_ADJ 20 +#define BM_TVENC_DACCTRL_JACK_DIS_ADJ 0x00300000 +#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v) \ + (((v) << 20) & BM_TVENC_DACCTRL_JACK_DIS_ADJ) +#define BM_TVENC_DACCTRL_GAINDN 0x00080000 +#define BM_TVENC_DACCTRL_GAINUP 0x00040000 +#define BM_TVENC_DACCTRL_INVERT_CLK 0x00020000 +#define BM_TVENC_DACCTRL_SELECT_CLK 0x00010000 +#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE 0x00008000 +#define BM_TVENC_DACCTRL_RSRVD5 0x00004000 +#define BM_TVENC_DACCTRL_RSRVD6 0x00002000 +#define BM_TVENC_DACCTRL_PWRUP1 0x00001000 +#define BM_TVENC_DACCTRL_WELL_TOVDD 0x00000800 +#define BM_TVENC_DACCTRL_RSRVD7 0x00000400 +#define BM_TVENC_DACCTRL_RSRVD8 0x00000200 +#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100 +#define BM_TVENC_DACCTRL_LOWER_SIGNAL 0x00000080 +#define BP_TVENC_DACCTRL_RVAL 4 +#define BM_TVENC_DACCTRL_RVAL 0x00000070 +#define BF_TVENC_DACCTRL_RVAL(v) \ + (((v) << 4) & BM_TVENC_DACCTRL_RVAL) +#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM 0x00000008 +#define BM_TVENC_DACCTRL_HALF_CURRENT 0x00000004 +#define BP_TVENC_DACCTRL_CASC_ADJ 0 +#define BM_TVENC_DACCTRL_CASC_ADJ 0x00000003 +#define BF_TVENC_DACCTRL_CASC_ADJ(v) \ + (((v) << 0) & BM_TVENC_DACCTRL_CASC_ADJ) + +#define HW_TVENC_DACSTATUS (0x000001b0) +#define HW_TVENC_DACSTATUS_SET (0x000001b4) +#define HW_TVENC_DACSTATUS_CLR (0x000001b8) +#define HW_TVENC_DACSTATUS_TOG (0x000001bc) + +#define BP_TVENC_DACSTATUS_RSRVD1 13 +#define BM_TVENC_DACSTATUS_RSRVD1 0xFFFFE000 +#define BF_TVENC_DACSTATUS_RSRVD1(v) \ + (((v) << 13) & BM_TVENC_DACSTATUS_RSRVD1) +#define BM_TVENC_DACSTATUS_RSRVD2 0x00001000 +#define BM_TVENC_DACSTATUS_RSRVD3 0x00000800 +#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS 0x00000400 +#define BM_TVENC_DACSTATUS_RSRVD4 0x00000200 +#define BM_TVENC_DACSTATUS_RSRVD5 0x00000100 +#define BM_TVENC_DACSTATUS_JACK1_GROUNDED 0x00000080 +#define BM_TVENC_DACSTATUS_RSRVD6 0x00000040 +#define BM_TVENC_DACSTATUS_RSRVD7 0x00000020 +#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ 0x00000010 +#define BM_TVENC_DACSTATUS_RSRVD8 0x00000008 +#define BM_TVENC_DACSTATUS_RSRVD9 0x00000004 +#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ 0x00000002 +#define BM_TVENC_DACSTATUS_ENIRQ_JACK 0x00000001 + +#define HW_TVENC_VDACTEST (0x000001c0) +#define HW_TVENC_VDACTEST_SET (0x000001c4) +#define HW_TVENC_VDACTEST_CLR (0x000001c8) +#define HW_TVENC_VDACTEST_TOG (0x000001cc) + +#define BP_TVENC_VDACTEST_RSRVD1 14 +#define BM_TVENC_VDACTEST_RSRVD1 0xFFFFC000 +#define BF_TVENC_VDACTEST_RSRVD1(v) \ + (((v) << 14) & BM_TVENC_VDACTEST_RSRVD1) +#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN 0x00002000 +#define BM_TVENC_VDACTEST_BYPASS_PIX_INT 0x00001000 +#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP 0x00000800 +#define BM_TVENC_VDACTEST_TEST_FIFO_FULL 0x00000400 +#define BP_TVENC_VDACTEST_DATA 0 +#define BM_TVENC_VDACTEST_DATA 0x000003FF +#define BF_TVENC_VDACTEST_DATA(v) \ + (((v) << 0) & BM_TVENC_VDACTEST_DATA) + +#define HW_TVENC_VERSION (0x000001d0) + +#define BP_TVENC_VERSION_MAJOR 24 +#define BM_TVENC_VERSION_MAJOR 0xFF000000 +#define BF_TVENC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TVENC_VERSION_MAJOR) +#define BP_TVENC_VERSION_MINOR 16 +#define BM_TVENC_VERSION_MINOR 0x00FF0000 +#define BF_TVENC_VERSION_MINOR(v) \ + (((v) << 16) & BM_TVENC_VERSION_MINOR) +#define BP_TVENC_VERSION_STEP 0 +#define BM_TVENC_VERSION_STEP 0x0000FFFF +#define BF_TVENC_VERSION_STEP(v) \ + (((v) << 0) & BM_TVENC_VERSION_STEP) +#endif /* __ARCH_ARM___TVENC_H */ diff --git a/drivers/video/mxs/tvenc.c b/drivers/video/mxs/tvenc.c new file mode 100644 index 000000000000..7aaa1fd013b0 --- /dev/null +++ b/drivers/video/mxs/tvenc.c @@ -0,0 +1,279 @@ +/* + * Freescale STMP378X dvi panel initialization + * + * Embedded Alley Solutions, Inc + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* #define DEBUG */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "regs-tvenc.h" + +enum { + TVENC_MODE_OFF = 0, + TVENC_MODE_NTSC, + TVENC_MODE_PAL, +}; + +#define REGS_TVENC_BASE (IO_ADDRESS(TVENC_PHYS_ADDR)) + +/* NTSC 720x480 mode */ +#define NTSC_X_RES 720 +#define NTSC_Y_RES 480 +#define NTSC_H_BLANKING 262 +#define NTSC_V_LINES 525 + +/* PAL 720x576 mode */ +#define PAL_X_RES 720 +#define PAL_Y_RES 576 +#define PAL_H_BLANKING 274 +#define PAL_V_LINES 625 + +/* frame size */ +#define DVI_H_BLANKING(m) (m == TVENC_MODE_NTSC ? \ + NTSC_H_BLANKING : PAL_H_BLANKING) +#define DVI_V_LINES(m) (m == TVENC_MODE_NTSC ? \ + NTSC_V_LINES : PAL_V_LINES) +#define DVI_H_ACTIVE(m) (m == TVENC_MODE_NTSC ? NTSC_X_RES : PAL_X_RES) +#define DVI_V_ACTIVE(m) (m == TVENC_MODE_NTSC ? NTSC_Y_RES : PAL_Y_RES) +/* fileds range */ +#define DVI_F1_START(m) 1 +#define DVI_F1_END(m) (DVI_V_LINES(m) / 2) +#define DVI_F2_START(m) (DVI_F1_END(m) + 1) +#define DVI_F2_END(m) DVI_V_LINES(m) +/* blanking range */ +#define DVI_V1_BLANK_START(m) DVI_F1_END(m) +#define DVI_V1_BLANK_END(m) (DVI_V1_BLANK_START(m) + \ + (DVI_V_LINES(m) - DVI_V_ACTIVE(m)) / 2) +#define DVI_V2_BLANK_START(m) DVI_F2_END(m) +#define DVI_V2_BLANK_END(m) ((DVI_V2_BLANK_START(m) + \ + (DVI_V_LINES(m) - DVI_V_ACTIVE(m)) / 2 - 1) % \ + DVI_V_LINES(m)) + +static struct clk *lcd_clk; +static struct clk *clk_tv108M_ng; +static struct clk *clk_tv27M; + +static int tvenc_mode; + +static void init_tvenc_hw(int mode) +{ + /* Reset module */ + __raw_writel(BM_TVENC_CTRL_SFTRST, REGS_TVENC_BASE + HW_TVENC_CTRL_SET); + udelay(10); + + /* Take module out of reset */ + __raw_writel(BM_TVENC_CTRL_SFTRST | BM_TVENC_CTRL_CLKGATE, + REGS_TVENC_BASE + HW_TVENC_CTRL_CLR); + + if (mode == TVENC_MODE_NTSC) { + /* Config NTSC-M mode, 8-bit Y/C in, SYNC out */ + __raw_writel(BM_TVENC_CONFIG_SYNC_MODE | + BM_TVENC_CONFIG_PAL_SHAPE | + BM_TVENC_CONFIG_YGAIN_SEL | + BM_TVENC_CONFIG_CGAIN, + REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR); + __raw_writel(BM_TVENC_CONFIG_FSYNC_PHS | + BF_TVENC_CONFIG_SYNC_MODE(0x4), + REGS_TVENC_BASE + HW_TVENC_CONFIG_SET); + + /* 859 pixels/line for NTSC */ + __raw_writel(857, REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET); + + __raw_writel(0x21F07C1F, REGS_TVENC_BASE + HW_TVENC_COLORSUB0); + __raw_writel(BM_TVENC_COLORBURST_NBA | + BM_TVENC_COLORBURST_PBA, + REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR); + __raw_writel(BF_TVENC_COLORBURST_NBA(0xc8) | + BF_TVENC_COLORBURST_PBA(0x0), + REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET); + } else if (mode == TVENC_MODE_PAL) { + /* Config PAL-B mode, 8-bit Y/C in, SYNC out */ + __raw_writel(BM_TVENC_CONFIG_SYNC_MODE | + BM_TVENC_CONFIG_ENCD_MODE | + BM_TVENC_CONFIG_YGAIN_SEL | + BM_TVENC_CONFIG_CGAIN | + BM_TVENC_CONFIG_FSYNC_PHS, + REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR); + __raw_writel(BM_TVENC_CONFIG_PAL_SHAPE | + BF_TVENC_CONFIG_YGAIN_SEL(0x1) + | BF_TVENC_CONFIG_CGAIN(0x1) + | BF_TVENC_CONFIG_ENCD_MODE(0x1) + | BF_TVENC_CONFIG_SYNC_MODE(0x4), + REGS_TVENC_BASE + HW_TVENC_CONFIG_SET); + + /* 863 pixels/line for PAL */ + __raw_writel(863, REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET); + + __raw_writel(0x2A098ACB, REGS_TVENC_BASE + HW_TVENC_COLORSUB0); + __raw_writel(BM_TVENC_COLORBURST_NBA | + BM_TVENC_COLORBURST_PBA, + REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR); + __raw_writel(BF_TVENC_COLORBURST_NBA(0xd6) | + BF_TVENC_COLORBURST_PBA(0x2a), + REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET); + } + + /* Power up DAC */ + __raw_writel(BM_TVENC_DACCTRL_GAINDN | + BM_TVENC_DACCTRL_GAINUP | + BM_TVENC_DACCTRL_PWRUP1 | + BM_TVENC_DACCTRL_DUMP_TOVDD1 | + BF_TVENC_DACCTRL_RVAL(0x3), + REGS_TVENC_BASE + HW_TVENC_DACCTRL); + + /* set all to zero is a requirement for NTSC */ + __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION0); + __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION1); + __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION2); + __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION3); + __raw_writel(0, REGS_TVENC_BASE + HW_TVENC_MACROVISION4); +} + +static int init_panel(struct device *dev, dma_addr_t phys, int memsize, + struct mxs_platform_fb_entry *pentry) +{ + int ret = 0; + + lcd_clk = clk_get(dev, "lcdif"); + clk_enable(lcd_clk); + clk_set_rate(lcd_clk, 1000000000 / pentry->cycle_time_ns);/* kHz */ + + clk_tv108M_ng = clk_get(NULL, "tv108M_ng"); + clk_tv27M = clk_get(NULL, "tv27M"); + clk_enable(clk_tv108M_ng); + clk_enable(clk_tv27M); + + tvenc_mode = pentry->x_res == NTSC_Y_RES ? TVENC_MODE_NTSC : + TVENC_MODE_PAL; + + init_tvenc_hw(tvenc_mode); + + setup_dvi_panel(DVI_H_ACTIVE(tvenc_mode), DVI_V_ACTIVE(tvenc_mode), + DVI_H_BLANKING(tvenc_mode), DVI_V_LINES(tvenc_mode), + DVI_V1_BLANK_START(tvenc_mode), + DVI_V1_BLANK_END(tvenc_mode), + DVI_V2_BLANK_START(tvenc_mode), + DVI_V2_BLANK_END(tvenc_mode), + DVI_F1_START(tvenc_mode), DVI_F1_END(tvenc_mode), + DVI_F2_START(tvenc_mode), DVI_F2_END(tvenc_mode)); + + ret = mxs_lcdif_dma_init(dev, phys, memsize); + mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_INIT, pentry); + + return ret; +} + +static void release_panel(struct device *dev, + struct mxs_platform_fb_entry *pentry) +{ + mxs_lcdif_notify_clients(MXS_LCDIF_PANEL_RELEASE, pentry); + release_dvi_panel(); + + mxs_lcdif_dma_release(); + + clk_disable(clk_tv108M_ng); + clk_disable(clk_tv27M); + clk_disable(lcd_clk); + clk_put(clk_tv108M_ng); + clk_put(clk_tv27M); + clk_put(lcd_clk); +} + +static int blank_panel(int blank) +{ + int ret = 0, count; + + switch (blank) { + case FB_BLANK_NORMAL: + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_POWERDOWN: + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + /* Wait until current transfer is complete, max 30ms */ + for (count = 30000; count > 0; count--) { + if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) & + BM_LCDIF_STAT_TXFIFO_EMPTY) + break; + udelay(1); + } + break; + + case FB_BLANK_UNBLANK: + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + break; + + default: + ret = -EINVAL; + } + + return ret; +} + +static struct mxs_platform_fb_entry ntsc_fb_entry = { + .name = "tvenc_ntsc", + /* x/y swapped */ + .x_res = NTSC_Y_RES, + .y_res = NTSC_X_RES, + .bpp = 32, + /* the pix_clk should be near 27Mhz for proper syncronization */ + .cycle_time_ns = 37, + .lcd_type = MXS_LCD_PANEL_DVI, + .init_panel = init_panel, + .release_panel = release_panel, + .blank_panel = blank_panel, + .run_panel = mxs_lcdif_run, + .pan_display = mxs_lcdif_pan_display, +}; + +static struct mxs_platform_fb_entry pal_fb_entry = { + .name = "tvenc_pal", + /* x/y swapped */ + .x_res = PAL_Y_RES, + .y_res = PAL_X_RES, + .bpp = 32, + /* the pix_clk should be near 27Mhz for proper syncronization */ + .cycle_time_ns = 37, + .lcd_type = MXS_LCD_PANEL_DVI, + .init_panel = init_panel, + .release_panel = release_panel, + .blank_panel = blank_panel, + .run_panel = mxs_lcdif_run, + .pan_display = mxs_lcdif_pan_display, +}; + +static int __init register_devices(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-fb", 0); + if (pdev == NULL || IS_ERR(pdev)) + return -ENODEV; + + mxs_lcd_register_entry(&ntsc_fb_entry, pdev->dev.platform_data); + mxs_lcd_register_entry(&pal_fb_entry, pdev->dev.platform_data); + return 0; +} + +subsys_initcall(register_devices); diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c index a3b6a74c67a7..adc643827007 100644 --- a/drivers/w1/masters/mxc_w1.c +++ b/drivers/w1/masters/mxc_w1.c @@ -1,5 +1,5 @@ /* - * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Luotao Fu, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -24,6 +24,7 @@ #include #include #include +#include #include "../w1.h" #include "../w1_int.h" @@ -44,6 +45,8 @@ #define MXC_W1_INTERRUPT 0x0A #define MXC_W1_INTERRUPT_EN 0x0C +static DECLARE_COMPLETION(transmit_done); + struct mxc_w1_device { void __iomem *regs; unsigned int clkdiv; @@ -103,10 +106,155 @@ static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit) return ((__raw_readb(ctrl_addr)) >> 3) & 0x1; } +static void mxc_w1_ds2_write_byte(void *data, u8 byte) +{ + struct mxc_w1_device *dev = (struct mxc_w1_device *)data; + INIT_COMPLETION(transmit_done); + __raw_writeb(byte, (dev->regs + MXC_W1_TXRX)); + __raw_writeb(0x10, (dev->regs + MXC_W1_INTERRUPT_EN)); + wait_for_completion(&transmit_done); +} +static u8 mxc_w1_ds2_read_byte(void *data) +{ + volatile u8 reg_val; + struct mxc_w1_device *dev = (struct mxc_w1_device *)data; + mxc_w1_ds2_write_byte(data, 0xFF); + reg_val = __raw_readb((dev->regs + MXC_W1_TXRX)); + return reg_val; +} +static u8 mxc_w1_read_byte(void *data) +{ + volatile u8 reg_val; + struct mxc_w1_device *dev = (struct mxc_w1_device *)data; + reg_val = __raw_readb((dev->regs + MXC_W1_TXRX)); + return reg_val; +} +static irqreturn_t w1_interrupt_handler(int irq, void *data) +{ + u8 reg_val; + irqreturn_t ret = IRQ_NONE; + struct mxc_w1_device *dev = (struct mxc_w1_device *)data; + reg_val = __raw_readb((dev->regs + MXC_W1_INTERRUPT)); + if ((reg_val & 0x10)) { + complete(&transmit_done); + reg_val = __raw_readb((dev->regs + MXC_W1_TXRX)); + ret = IRQ_HANDLED; + } + return ret; +} +void search_ROM_accelerator(void *data, struct w1_master *master, u8 search_type, + w1_slave_found_callback cb) +{ + u64 rn[2], last_rn[2], rn2[2]; + u64 rn1, rom_id, temp, temp1; + int i, j, z, w, last_zero, loop; + u8 bit, reg_val, bit2; + u8 byte, byte1; + int disc, prev_disc, last_disc; + struct mxc_w1_device *dev = (struct mxc_w1_device *)data; + last_rn[0] = 0; + last_rn[1] = 0; + rom_id = 0; + prev_disc = 0; + loop = 0; + disc = -1; + last_disc = 0; + last_zero = 0; + while (!last_zero) { + /* + * Reset bus and all 1-wire device state machines + * so they can respond to our requests. + * + * Return 0 - device(s) present, 1 - no devices present. + */ + if (mxc_w1_ds2_reset_bus(data)) { + pr_debug("No devices present on the wire.\n"); + break; + } + rn[0] = 0; + rn[1] = 0; + __raw_writeb(0x80, (dev->regs + MXC_W1_CONTROL)); + mdelay(1); + mxc_w1_ds2_write_byte(data, 0xF0); + __raw_writeb(0x02, (dev->regs + MXC_W1_COMMAND)); + memcpy(rn2, last_rn, 16); + z = 0; + w = 0; + for (i = 0; i < 16; i++) { + reg_val = rn2[z] >> (8 * w); + mxc_w1_ds2_write_byte(data, reg_val); + reg_val = mxc_w1_read_byte(data); + if ((reg_val & 0x3) == 0x3) { + pr_debug("Device is Not Responding\n"); + break; + } + for (j = 0; j < 8; j += 2) { + byte = 0xFF; + byte1 = 1; + byte ^= byte1 << j; + bit = (reg_val >> j) & 0x1; + bit2 = (reg_val >> j); + if (bit) { + prev_disc = disc; + disc = 8 * i + j; + reg_val &= byte; + } + } + rn1 = 0; + rn1 = reg_val; + rn[z] |= rn1 << (8 * w); + w++; + if (i == 7) { + z++; + w = 0; + } + } + if ((disc == -1) || (disc == prev_disc)) + last_zero = 1; + if (disc == last_disc) + disc = prev_disc; + z = 0; + rom_id = 0; + for (i = 0, j = 1; i < 64; i++) { + temp = 0; + temp = (rn[z] >> j) & 0x1; + rom_id |= (temp << i); + j += 2; + if (i == 31) { + z++; + j = 1; + } + + } + if (disc > 63) { + last_rn[0] = rn[0]; + temp1 = rn[1]; + loop = disc % 64; + temp = 1; + temp1 |= (temp << (loop + 1)) - 1; + temp1 |= (temp << (loop + 1)); + last_rn[1] = temp1; + + } else { + last_rn[1] = 0; + temp1 = rn[0]; + temp = 1; + temp1 |= (temp << (loop + 1)) - 1; + temp1 |= (temp << (loop + 1)); + last_rn[0] = temp1; + } + last_disc = disc; + cb(master, rom_id); + } +} + static int __devinit mxc_w1_probe(struct platform_device *pdev) { struct mxc_w1_device *mdev; + struct mxc_w1_config *data = + (struct mxc_w1_config *)pdev->dev.platform_data; struct resource *res; + int irq = 0; int err = 0; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -144,6 +292,22 @@ static int __devinit mxc_w1_probe(struct platform_device *pdev) mdev->bus_master.data = mdev; mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus; mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit; + if (data->search_rom_accelerator) { + mdev->bus_master.write_byte = &mxc_w1_ds2_write_byte; + mdev->bus_master.read_byte = &mxc_w1_ds2_read_byte; + mdev->bus_master.search = &search_ROM_accelerator; + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + err = -ENOENT; + goto failed_irq; + } + err = request_irq(irq, w1_interrupt_handler, 0, "mxc_w1", mdev); + if (err) { + pr_debug("OWire:request_irq(%d) returned error %d\n", + irq, err); + goto failed_irq; + } + } err = w1_add_master_device(&mdev->bus_master); @@ -154,6 +318,9 @@ static int __devinit mxc_w1_probe(struct platform_device *pdev) return 0; failed_add: + if (irq) + free_irq(irq, mdev); +failed_irq: iounmap(mdev->regs); failed_ioremap: release_mem_region(res->start, resource_size(res)); @@ -171,6 +338,9 @@ static int __devexit mxc_w1_remove(struct platform_device *pdev) { struct mxc_w1_device *mdev = platform_get_drvdata(pdev); struct resource *res; + struct mxc_w1_config *data = + (struct mxc_w1_config *)pdev->dev.platform_data; + int irq; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -178,6 +348,11 @@ static int __devexit mxc_w1_remove(struct platform_device *pdev) iounmap(mdev->regs); release_mem_region(res->start, resource_size(res)); + + irq = platform_get_irq(pdev, 0); + if ((irq >= 0) && (data->search_rom_accelerator)) + free_irq(irq, mdev); + clk_disable(mdev->clk); clk_put(mdev->clk); diff --git a/drivers/w1/slaves/Kconfig b/drivers/w1/slaves/Kconfig index 1f51366417b9..58f3e64e600a 100644 --- a/drivers/w1/slaves/Kconfig +++ b/drivers/w1/slaves/Kconfig @@ -22,12 +22,35 @@ config W1_SLAVE_DS2431 Say Y here if you want to use a 1-wire 1kb EEPROM family device (DS2431) +config W1_SLAVE_DS2751 + tristate "Battery Level sensing support (DS2751)" + depends on W1 + help + Say Y here if you want to use a 1-wire + battery level sensing device (DS2751). + +config W1_SLAVE_DS2751_CRC + bool "Protect DS2751 data with a CRC16" + depends on W1_SLAVE_DS2751 + select CRC16 + help + Say Y here to protect DS2751 data with a CRC16. + Each block has 30 bytes of data and a two byte CRC16. + Full block writes are only allowed if the CRC is valid. + config W1_SLAVE_DS2433 tristate "4kb EEPROM family support (DS2433)" help Say Y here if you want to use a 1-wire 4kb EEPROM family device (DS2433). +config W1_SLAVE_DS2438 + tristate "Smart Battery Monitor (DS2438)" + depends on W1 + help + Say Y here if you want to use a 1-wire + Smart Battery Monitor family device (DS2438). + config W1_SLAVE_DS2433_CRC bool "Protect DS2433 data with a CRC16" depends on W1_SLAVE_DS2433 diff --git a/drivers/w1/slaves/Makefile b/drivers/w1/slaves/Makefile index f1f51f19b129..fd53f53d8681 100644 --- a/drivers/w1/slaves/Makefile +++ b/drivers/w1/slaves/Makefile @@ -8,3 +8,5 @@ obj-$(CONFIG_W1_SLAVE_DS2431) += w1_ds2431.o obj-$(CONFIG_W1_SLAVE_DS2433) += w1_ds2433.o obj-$(CONFIG_W1_SLAVE_DS2760) += w1_ds2760.o obj-$(CONFIG_W1_SLAVE_BQ27000) += w1_bq27000.o +obj-$(CONFIG_W1_SLAVE_DS2751) += w1_ds2751.o +obj-$(CONFIG_W1_SLAVE_DS2438) += w1_ds2438.o diff --git a/drivers/w1/slaves/w1_ds2438.c b/drivers/w1/slaves/w1_ds2438.c new file mode 100644 index 000000000000..4212117d9424 --- /dev/null +++ b/drivers/w1/slaves/w1_ds2438.c @@ -0,0 +1,204 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../w1.h" +#include "../w1_int.h" +#include "../w1_family.h" +#include "w1_ds2438.h" + +/* W1 slave DS2438 famliy operations */ +int w1_ds2438_read_page(struct device *dev, u8 page, u8 *buf) +{ + struct w1_slave *slave = container_of(dev, struct w1_slave, dev); + if ((page >= DS2438_PAGE_NUM) || (buf == NULL)) + return -EINVAL; + + mutex_lock(&slave->master->mutex); + if (!w1_reset_select_slave(slave)) { + w1_write_8(slave->master, W1_READ_SCRATCHPAD); + w1_write_8(slave->master, page); + w1_read_block(slave->master, buf, DS2438_PAGE_SIZE); + } + mutex_unlock(&slave->master->mutex); + return 0; +} +EXPORT_SYMBOL(w1_ds2438_read_page); + +int w1_ds2438_write_page(struct device *dev, u8 page, u8 *buf) +{ + struct w1_slave *slave = container_of(dev, struct w1_slave, dev); + if ((page >= DS2438_PAGE_NUM) || (buf == NULL)) + return -EINVAL; + + mutex_lock(&slave->master->mutex); + if (!w1_reset_select_slave(slave)) { + w1_write_8(slave->master, DS2438_WRITE_SCRATCHPAD); + w1_write_8(slave->master, page); + w1_write_block(slave->master, buf, DS2438_PAGE_SIZE); + } + mutex_unlock(&slave->master->mutex); + return 0; +} +EXPORT_SYMBOL(w1_ds2438_write_page); + +int w1_ds2438_command(struct device *dev, u8 command, u8 data) +{ + struct w1_slave *slave = container_of(dev, struct w1_slave, dev); + + mutex_lock(&slave->master->mutex); + if (!w1_reset_select_slave(slave)) { + w1_write_8(slave->master, command); + switch (command) { + case DS2438_COPY_SCRATCHPAD: + case DS2438_RECALL_MEMORY: + w1_write_8(slave->master, data); + } + } + mutex_unlock(&slave->master->mutex); + return 0; +} +EXPORT_SYMBOL(w1_ds2438_command); + +int w1_ds2438_drain_sram(struct device *dev, u8 page) +{ + return w1_ds2438_command(dev, DS2438_COPY_SCRATCHPAD, page); +} +EXPORT_SYMBOL(w1_ds2438_drain_sram); + +int w1_ds2438_load_sram(struct device *dev, u8 page) +{ + return w1_ds2438_command(dev, DS2438_RECALL_MEMORY, page); +} +EXPORT_SYMBOL(w1_ds2438_load_sram); + +static DEFINE_IDR(bat_idr); +static DEFINE_MUTEX(bat_idr_lock); + +static int new_bat_id(void) +{ + int ret; + + while (1) { + int id; + + ret = idr_pre_get(&bat_idr, GFP_KERNEL); + if (ret == 0) + return -ENOMEM; + + mutex_lock(&bat_idr_lock); + ret = idr_get_new(&bat_idr, NULL, &id); + mutex_unlock(&bat_idr_lock); + + if (ret == 0) { + ret = id & MAX_ID_MASK; + break; + } else if (ret == -EAGAIN) { + continue; + } else { + break; + } + } + + return ret; +} + +static void release_bat_id(int id) +{ + mutex_lock(&bat_idr_lock); + idr_remove(&bat_idr, id); + mutex_unlock(&bat_idr_lock); +} + +static int ds2438_add_slave(struct w1_slave *slave) +{ + int ret; + int id; + struct platform_device *pdev; + + id = new_bat_id(); + if (id < 0) { + ret = id; + goto noid; + } + + pdev = platform_device_alloc(DS2438_DEV_NAME, id); + if (!pdev) { + ret = -ENOMEM; + goto pdev_alloc_failed; + } + pdev->dev.parent = &slave->dev; + + ret = platform_device_add(pdev); + if (ret) + goto pdev_add_failed; + + dev_set_drvdata(&slave->dev, pdev); + goto success; + +pdev_add_failed: + platform_device_unregister(pdev); +pdev_alloc_failed: + release_bat_id(id); +noid: +success: + return ret; +} + +static void ds2438_remove_slave(struct w1_slave *slave) +{ + struct platform_device *pdev = dev_get_drvdata(&slave->dev); + int id = pdev->id; + + platform_device_unregister(pdev); + release_bat_id(id); +} + +static struct w1_family_ops w1_ds2438_fops = { + .add_slave = ds2438_add_slave, + .remove_slave = ds2438_remove_slave, +}; + +static struct w1_family w1_family_ds2438 = { + .fid = W1_FAMILY_DS2438, + .fops = &w1_ds2438_fops, +}; + +static int __init w1_ds2438_init(void) +{ + pr_info("1-wire driver for the DS2438 smart battery monitor\n"); + idr_init(&bat_idr); + return w1_register_family(&w1_family_ds2438); +} + +static void __exit w1_ds2438_fini(void) +{ + w1_unregister_family(&w1_family_ds2438); + idr_destroy(&bat_idr); +} + +module_init(w1_ds2438_init); +module_exit(w1_ds2438_fini); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductors Inc"); +MODULE_DESCRIPTION("1-wire DS2438 family, smart battery monitor."); diff --git a/drivers/w1/slaves/w1_ds2438.h b/drivers/w1/slaves/w1_ds2438.h new file mode 100644 index 000000000000..b9fb73cafea4 --- /dev/null +++ b/drivers/w1/slaves/w1_ds2438.h @@ -0,0 +1,125 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __W1_DS2438_H__ +#define __W1_DS2438_H__ + +#include + +#include +#include +#include +#include +#include + +#define DS2438_DEV_NAME "ds2438-battery" + +#define DS2438_PAGE_SIZE 8 +#define DS2438_PAGE_NUM 8 + +#define DS2438_CONVERT_TEMP 0x44 +#define DS2438_CONVERT_VOLT 0xB4 +#define DS2438_WRITE_SCRATCHPAD 0x4E +#define DS2438_COPY_SCRATCHPAD 0x48 +#define DS2438_RECALL_MEMORY 0xB8 + +enum DS2438_PAGE { + PAGE0_CONTROL = 0, + PAGE1_ETM, + PAGE2_STAMP, + PAGE3_RESV3, + PAGE4_RESV4, + PAGE5_RESV5, + PAGE6_RESV6, + PAGE7_CCA, +}; + +enum DS2438_REG { + /* PAGE 0 */ + PAGE0_STAT_CTRL = 0, + PAGE0_TEMP_LSB = 1, + PAGE0_TEMP_MSB = 2, + PAGE0_VOLTAGE_LSB = 3, + PAGE0_VOLTAGE_MSB = 4, + PAGE0_CURRENT_LSB = 5, + PAGE0_CURRENT_MSB = 6, + PAGE0_THRESHOLD = 7, + + /* PAGE 1 */ + PAGE1_ETM_BYTE0 = 0, + PAGE1_ETM_BYTE1 = 1, + PAGE1_ETM_BYTE2 = 2, + PAGE1_ETM_BYTE3 = 3, + PAGE1_ICA = 4, + PAGE1_OFFSET_LSB = 5, + PAGE1_OFFSET_MSB = 6, + + /* PAGE 2 */ + PAGE2_DISCONNECT_BYTE0 = 0, + PAGE2_DISCONNECT_BYTE1 = 1, + PAGE2_DISCONNECT_BYTE2 = 2, + PAGE2_DISCONNECT_BYTE3 = 3, + PAGE2_END_CHARGE_BYTE0 = 4, + PAGE2_END_CHARGE_BYTE1 = 5, + PAGE2_END_CHARGE_BYTE2 = 6, + PAGE2_END_CHARGE_BYTE3 = 7, + + /* PAGE 3 */ + /* PAGE 4 */ + /* PAGE 5 */ + /* PAGE 6 */ + /* PAGE 7 */ + PAGE7_CCA_LSB = 4, + PAGE7_CCA_MSB = 5, + PAGE7_DCA_LSB = 6, + PAGE7_DCA_MSB = 7, +}; + +#define DS2438_CTRL_IAD (1 << 0) +#define DS2438_CTRL_CA (1 << 1) +#define DS2438_CTRL_EE (1 << 2) +#define DS2438_CTRL_AD (1 << 3) +#define DS2438_STAT_TB (1 << 4) +#define DS2438_STAT_NVB (1 << 5) +#define DS2438_STAT_ADB (1 << 6) + +struct ds2438_ops { + int (*read_page) (struct device *, u8, u8 *); + int (*read_byte) (struct device *, u8, u8, u8 *); + int (*read_halfword) (struct device *, u8, u8, u16 *); + int (*read_word) (struct device *, u8, u8, u32 *); + int (*write_page) (struct device *, u8, u8 *); + int (*write_byte) (struct device *, u8, u8, u8); + int (*write_halfword) (struct device *, u8, u8, u16); + int (*write_word) (struct device *, u8, u8, u32); + int (*drain_sram) (struct device *, u8); + int (*load_sram) (struct device *, u8); + int (*command) (struct device *, u8, u8); +}; + +static inline u16 ds2438_readw(u8 *raw) +{ + return ((*(raw + 1)) << 8) | (*raw); +} + +static inline void ds2438_writew(u8 *raw, u16 data) +{ + *raw++ = data & 0xFF; + *raw = (data >> 8) & 0xFF; +} + +extern int w1_ds2438_read_page(struct device *dev, u8 page, u8 *buf); +extern int w1_ds2438_write_page(struct device *dev, u8 page, u8 *buf); +extern int w1_ds2438_command(struct device *dev, u8 command, u8 data); +extern int w1_ds2438_drain_sram(struct device *dev, u8 page); +extern int w1_ds2438_load_sram(struct device *dev, u8 page); +#endif /* __W1_DS2438_H__ */ diff --git a/drivers/w1/slaves/w1_ds2751.c b/drivers/w1/slaves/w1_ds2751.c new file mode 100644 index 000000000000..9e5bf6faa4cb --- /dev/null +++ b/drivers/w1/slaves/w1_ds2751.c @@ -0,0 +1,320 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +/* + * Implementation based on w1_ds2433.c + */ + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_W1_F51_CRC +#include + +#define CRC16_INIT 0 +#define CRC16_VALID 0xb001 + +#endif + +#include "../w1.h" +#include "../w1_int.h" +#include "../w1_family.h" + +#define W1_EEPROM_SIZE 32 +#define W1_PAGE_SIZE 32 +#define W1_PAGE_BITS 5 +#define W1_PAGE_MASK 0x1F + +#define W1_F51_TIME 300 + +#define W1_F51_READ_EEPROM 0xB8 +#define W1_F51_WRITE_SCRATCH 0x6C +#define W1_F51_READ_SCRATCH 0x69 +#define W1_F51_COPY_SCRATCH 0x48 +#define W1_STATUS_OFFSET 0x0001 +#define W1_EEPROM_OFFSET 0x0007 +#define W1_SPECIAL_OFFSET 0x0008 +#define W1_EEPROM_BLOCK_0 0x0020 +#define W1_EEPROM_BLOCK_1 0x0030 +#define W1_SRAM 0x0080 +struct w1_f51_data { + u8 memory[W1_EEPROM_SIZE]; + u32 validcrc; +}; + +/** + * Check the file size bounds and adjusts count as needed. + * This would not be needed if the file size didn't reset to 0 after a write. + */ +static inline size_t w1_f51_fix_count(loff_t off, size_t count, size_t size) +{ + if (off > size) + return 0; + + if ((off + count) > size) + return size - off; + + return count; +} + +#ifdef CONFIG_W1_F51_CRC +static int w1_f51_refresh_block(struct w1_slave *sl, struct w1_f51_data *data, + int block) +{ + u8 wrbuf[3]; + int off = block * W1_PAGE_SIZE; + if (data->validcrc & (1 << block)) + return 0; + + if (w1_reset_select_slave(sl)) { + data->validcrc = 0; + return -EIO; + } + wrbuf[0] = W1_F51_READ_EEPROM; + wrbuf[1] = off & 0xff; + wrbuf[2] = off >> 8; + w1_write_block(sl->master, wrbuf, 3); + w1_read_block(sl->master, &data->memory[off], W1_PAGE_SIZE); + + /* cache the block if the CRC is valid */ + if (crc16(CRC16_INIT, &data->memory[off], W1_PAGE_SIZE) == CRC16_VALID) + data->validcrc |= (1 << block); + + return 0; +} +#endif /* CONFIG_W1_F51_CRC */ + +static ssize_t w1_f51_read_bin(struct kobject *kobj, char *buf, loff_t off, + size_t count) +{ + struct w1_slave *sl = kobj_to_w1_slave(kobj); +#ifdef CONFIG_W1_F51_CRC + struct w1_f51_data *data = sl->family_data; + int i, min_page, max_page; +#else + u8 wrbuf[3]; +#endif + + count = w1_f51_fix_count(off, count, W1_EEPROM_SIZE) + if (count == 0) + return 0; + + mutex_lock(&sl->master->mutex); +#ifdef CONFIG_W1_F51_CRC + min_page = (off >> W1_PAGE_BITS); + max_page = (off + count - 1) >> W1_PAGE_BITS; + for (i = min_page; i <= max_page; i++) { + if (w1_f51_refresh_block(sl, data, i)) { + count = -EIO; + goto out_up; + } + } + memcpy(buf, &data->memory[off], count); + +#else /* CONFIG_W1_F51_CRC */ + + /* read directly from the EEPROM */ + if (w1_reset_select_slave(sl)) { + count = -EIO; + goto out_up; + } + off = (loff_t) W1_EEPROM_BLOCK_0; + wrbuf[0] = W1_F51_READ_EEPROM; + wrbuf[1] = off & 0xff; + wrbuf[2] = off >> 8; + w1_write_block(sl->master, wrbuf, 3); + if (w1_reset_select_slave(sl)) { + count = -EIO; + goto out_up; + } + + wrbuf[0] = W1_F51_READ_SCRATCH; + wrbuf[1] = off & 0xff; + wrbuf[2] = off >> 8; + w1_write_block(sl->master, wrbuf, 3); + w1_read_block(sl->master, buf, count); + +#endif /* CONFIG_W1_F51_CRC */ + + out_up: + mutex_unlock(&sl->master->mutex); + return count; +} + +/** + * Writes to the scratchpad and reads it back for verification. + * Then copies the scratchpad to EEPROM. + * The data must be on one page. + * The master must be locked. + * + * @param sl The slave structure + * @param addr Address for the write + * @param len length must be <= (W1_PAGE_SIZE - (addr & W1_PAGE_MASK)) + * @param data The data to write + * @return 0=Success -1=failure + */ +static int w1_f51_write(struct w1_slave *sl, int addr, int len, const u8 * data) +{ + u8 wrbuf[4]; + u8 rdbuf[W1_EEPROM_SIZE + 3]; + u8 es = (addr + len - 1) & 0x1f; + /* Write the data to the scratchpad */ + if (w1_reset_select_slave(sl)) + return -1; + wrbuf[0] = W1_F51_WRITE_SCRATCH; + wrbuf[1] = addr & 0xff; + wrbuf[2] = addr >> 8; + + w1_write_block(sl->master, wrbuf, 3); + w1_write_block(sl->master, data, len); + /* Read the scratchpad and verify */ + if (w1_reset_select_slave(sl)) + return -1; + wrbuf[0] = W1_F51_READ_SCRATCH; + w1_write_block(sl->master, wrbuf, 3); + w1_read_block(sl->master, rdbuf, len + 3); + /* Compare what was read against the data written */ + if (memcmp(data, &rdbuf[0], len) != 0) { + printk("Error reading the scratch Pad\n"); + return -1; + } + /* Copy the scratchpad to EEPROM */ + if (w1_reset_select_slave(sl)) + return -1; + wrbuf[0] = W1_F51_COPY_SCRATCH; + wrbuf[3] = es; + w1_write_block(sl->master, wrbuf, 4); + /* Sleep for 5 ms to wait for the write to complete */ + msleep(5); + + /* Reset the bus to wake up the EEPROM (this may not be needed) */ + w1_reset_bus(sl->master); + + return 0; +} + +static ssize_t w1_f51_write_bin(struct kobject *kobj, char *buf, loff_t off, + size_t count) +{ + struct w1_slave *sl = kobj_to_w1_slave(kobj); + int addr; + + count = w1_f51_fix_count(off, count, W1_EEPROM_SIZE); + if (count == 0) + return 0; + off = (loff_t) 0x0020; +#ifdef CONFIG_W1_F51_CRC + /* can only write full blocks in cached mode */ + if ((off & W1_PAGE_MASK) || (count & W1_PAGE_MASK)) { + dev_err(&sl->dev, "invalid offset/count off=%d cnt=%zd\n", + (int)off, count); + return -EINVAL; + } + + /* make sure the block CRCs are valid */ + for (idx = 0; idx < count; idx += W1_PAGE_SIZE) { + if (crc16(CRC16_INIT, &buf[idx], W1_PAGE_SIZE) != CRC16_VALID) { + dev_err(&sl->dev, "bad CRC at offset %d\n", (int)off); + return -EINVAL; + } + } +#endif /* CONFIG_W1_F51_CRC */ + + mutex_lock(&sl->master->mutex); + + /* Can only write data to one page at a time */ + addr = off; + if (w1_f51_write(sl, addr, count, buf) < 0) { + count = -EIO; + goto out_up; + } + + out_up: + mutex_unlock(&sl->master->mutex); + + return count; +} + +static struct bin_attribute w1_f51_bin_attr = { + .attr = { + .name = "eeprom", + .mode = S_IRUGO | S_IWUSR, + .owner = THIS_MODULE, + }, + .size = W1_EEPROM_SIZE, + .read = w1_f51_read_bin, + .write = w1_f51_write_bin, +}; + +static int w1_f51_add_slave(struct w1_slave *sl) +{ + int err; +#ifdef CONFIG_W1_F51_CRC + struct w1_f51_data *data; + data = kmalloc(sizeof(struct w1_f51_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + memset(data, 0, sizeof(struct w1_f51_data)); + sl->family_data = data; + +#endif /* CONFIG_W1_F51_CRC */ + + err = sysfs_create_bin_file(&sl->dev.kobj, &w1_f51_bin_attr); + +#ifdef CONFIG_W1_F51_CRC + if (err) + kfree(data); +#endif /* CONFIG_W1_F51_CRC */ + + return err; +} + +static void w1_f51_remove_slave(struct w1_slave *sl) +{ +#ifdef CONFIG_W1_F51_CRC + kfree(sl->family_data); + sl->family_data = NULL; +#endif /* CONFIG_W1_F51_CRC */ + sysfs_remove_bin_file(&sl->dev.kobj, &w1_f51_bin_attr); +} + +static struct w1_family_ops w1_f51_fops = { + .add_slave = w1_f51_add_slave, + .remove_slave = w1_f51_remove_slave, +}; + +static struct w1_family w1_family_51 = { + .fid = W1_EEPROM_DS2751, + .fops = &w1_f51_fops, +}; + +static int __init w1_f51_init(void) +{ + return w1_register_family(&w1_family_51); +} + +static void __exit w1_f51_fini(void) +{ + w1_unregister_family(&w1_family_51); +} + +module_init(w1_f51_init); +module_exit(w1_f51_fini); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductors Inc"); +MODULE_DESCRIPTION + ("w1 family 51 driver for DS2751, Battery Level Sensing Device"); diff --git a/drivers/w1/w1_family.h b/drivers/w1/w1_family.h index 3ca1b9298f21..c541f9215765 100644 --- a/drivers/w1/w1_family.h +++ b/drivers/w1/w1_family.h @@ -32,8 +32,10 @@ #define W1_THERM_DS18S20 0x10 #define W1_THERM_DS1822 0x22 #define W1_EEPROM_DS2433 0x23 +#define W1_EEPROM_DS2751 0x51 #define W1_THERM_DS18B20 0x28 #define W1_EEPROM_DS2431 0x2D +#define W1_FAMILY_DS2438 0x26 #define W1_FAMILY_DS2760 0x30 #define MAXNAMELEN 32 diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index afcfacc9bbe2..653d7a8783fa 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -45,6 +45,14 @@ comment "Watchdog Device Drivers" # Architecture Independent +config DA9052_WATCHDOG + tristate "Dialog DA9052 Watchdog" + depends on PMIC_DA9052 + help + Support for the watchdog in the DA9052 PMIC. + + To compile this driver as a module, choose M here. + config SOFT_WATCHDOG tristate "Software watchdog" help @@ -216,6 +224,27 @@ config PNX4008_WATCHDOG Say N if you are unsure. +config MXC_WATCHDOG + tristate "MXC watchdog" + depends on WATCHDOG && WATCHDOG_NOWAYOUT + depends on ARCH_MXC + help + Watchdog timer embedded into MXC chips. This will + reboot your system when timeout is reached. + + NOTE: once enabled, this timer cannot be disabled. + To compile this driver as a module, choose M here: the + module will be called mxc_wdt. + +config MXS_WATCHDOG + tristate "Freescale mxs watchdog" + depends on ARCH_MXS + help + Say Y here if to include support for the watchdog timer + for the Freescale mxs family SoC. + To compile this driver as a module, choose M here: the + module will be called mxs_wdt. + config IOP_WATCHDOG tristate "IOP Watchdog" depends on PLAT_IOP diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 72f3e2073f8e..30c9ffa83589 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -38,6 +38,8 @@ obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o +obj-$(CONFIG_MXC_WATCHDOG) += mxc_wdt.o +obj-$(CONFIG_MXS_WATCHDOG) += mxs-wdt.o obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o @@ -142,6 +144,7 @@ obj-$(CONFIG_WATCHDOG_CP1XXX) += cpwd.o # XTENSA Architecture # Architecture Independant +obj-$(CONFIG_DA9052_WATCHDOG) += da9052_wdt.o obj-$(CONFIG_WM831X_WATCHDOG) += wm831x_wdt.o obj-$(CONFIG_WM8350_WATCHDOG) += wm8350_wdt.o obj-$(CONFIG_MAX63XX_WATCHDOG) += max63xx_wdt.o diff --git a/drivers/watchdog/da9052_wdt.c b/drivers/watchdog/da9052_wdt.c new file mode 100644 index 000000000000..11e1d75212c3 --- /dev/null +++ b/drivers/watchdog/da9052_wdt.c @@ -0,0 +1,542 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include + +#define DRIVER_NAME "da9052-wdt" + +#define DA9052_STROBING_FILTER_ENABLE 0x0001 +#define DA9052_STROBING_FILTER_DISABLE 0x0002 +#define DA9052_SET_STROBING_MODE_MANUAL 0x0004 +#define DA9052_SET_STROBING_MODE_AUTO 0x0008 + +#define KERNEL_MODULE 0 +#define ENABLE 1 +#define DISABLE 0 + +static u8 sm_strobe_filter_flag = DISABLE; +static u8 sm_strobe_mode_flag = DA9052_STROBE_MANUAL; +static u32 sm_mon_interval = DA9052_ADC_TWDMIN_TIME; +static u8 sm_str_req = DISABLE; +static u8 da9052_sm_scale = DA9052_WDT_DISABLE; +module_param(sm_strobe_filter_flag, byte, 0); +MODULE_PARM_DESC(sm_strobe_filter_flag, + "DA9052 SM driver strobe filter flag default = DISABLE"); + +module_param(sm_strobe_mode_flag, byte, 0); +MODULE_PARM_DESC(sm_strobe_mode_flag, + "DA9052 SM driver watchdog strobing mode default\ + = DA9052_STROBE_MANUAL"); + +module_param(da9052_sm_scale, byte, 0); +MODULE_PARM_DESC(da9052_sm_scale, + "DA9052 SM driver scaling value used to calculate the\ + time for the strobing filter default = 0"); + +module_param(sm_str_req, byte, 0); +MODULE_PARM_DESC(sm_str_req, + "DA9052 SM driver strobe request flag default = DISABLE"); + +static int nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + +static struct timer_list *monitoring_timer; + +struct da9052_wdt { + struct platform_device *pdev; + struct da9052 *da9052; +}; +static struct miscdevice da9052_wdt_miscdev; +static unsigned long da9052_wdt_users; +static int da9052_wdt_expect_close; + +static struct da9052_wdt *get_wdt_da9052(void) +{ + /*return dev_get_drvdata(da9052_wdt_miscdev.parent);*/ + return platform_get_drvdata + (to_platform_device(da9052_wdt_miscdev.parent)); +} + +void start_strobing(struct work_struct *work) +{ + struct da9052_ssc_msg msg; + int ret; + struct da9052_wdt *wdt = get_wdt_da9052(); + + + if (NULL == wdt) { + mod_timer(monitoring_timer, jiffies + sm_mon_interval); + return; + } + msg.addr = DA9052_CONTROLD_REG; + msg.data = 0; + da9052_lock(wdt->da9052); + ret = wdt->da9052->read(wdt->da9052, &msg); + if (ret) { + da9052_unlock(wdt->da9052); + return; + } + da9052_unlock(wdt->da9052); + + msg.data = (msg.data | DA9052_CONTROLD_WATCHDOG); + da9052_lock(wdt->da9052); + ret = wdt->da9052->write(wdt->da9052, &msg); + if (ret) { + da9052_unlock(wdt->da9052); + return; + } + da9052_unlock(wdt->da9052); + + sm_str_req = DISABLE; + + mod_timer(monitoring_timer, jiffies + sm_mon_interval); + return; +} + + +void timer_callback(void) +{ + if (((sm_strobe_mode_flag) && + (sm_strobe_mode_flag == DA9052_STROBE_MANUAL)) || + (sm_strobe_mode_flag == DA9052_STROBE_AUTO)) { + schedule_work(&strobing_action); + } else { + if (sm_strobe_mode_flag == DA9052_STROBE_MANUAL) { + mod_timer(monitoring_timer, jiffies + + sm_mon_interval); + } + } +} + +static int da9052_sm_hw_init(struct da9052_wdt *wdt) +{ + /* Create timer structure */ + monitoring_timer = kzalloc(sizeof(struct timer_list), GFP_KERNEL); + if (!monitoring_timer) + return -ENOMEM; + + init_timer(monitoring_timer); + monitoring_timer->expires = jiffies + sm_mon_interval; + monitoring_timer->function = (void *)&timer_callback; + + sm_strobe_filter_flag = DA9052_SM_STROBE_CONF; + sm_strobe_mode_flag = DA9052_STROBE_MANUAL; + + return 0; +} + +static int da9052_sm_hw_deinit(struct da9052_wdt *wdt) +{ + struct da9052_ssc_msg msg; + int ret; + + if (monitoring_timer != NULL) + del_timer(monitoring_timer); + kfree(monitoring_timer); + + msg.addr = DA9052_CONTROLD_REG; + msg.data = 0; + + da9052_lock(wdt->da9052); + ret = wdt->da9052->read(wdt->da9052, &msg); + if (ret) + goto ssc_err; + da9052_unlock(wdt->da9052); + + msg.data = (msg.data & ~(DA9052_CONTROLD_TWDSCALE)); + da9052_lock(wdt->da9052); + ret = wdt->da9052->write(wdt->da9052, &msg); + if (ret) + goto ssc_err; + da9052_unlock(wdt->da9052); + + return 0; +ssc_err: + da9052_unlock(wdt->da9052); + return -EIO; +} + + s32 da9052_sm_set_strobing_filter(struct da9052_wdt *wdt, + u8 strobing_filter_state) + { + struct da9052_ssc_msg msg; + int ret = 0; + + msg.addr = DA9052_CONTROLD_REG; + msg.data = 0; + da9052_lock(wdt->da9052); + ret = wdt->da9052->read(wdt->da9052, &msg); + if (ret) + goto ssc_err; + da9052_unlock(wdt->da9052); + + msg.data = (msg.data & DA9052_CONTROLD_TWDSCALE); + + if (strobing_filter_state == ENABLE) { + sm_strobe_filter_flag = ENABLE; + if (DA9052_WDT_DISABLE == msg.data) { + sm_str_req = DISABLE; + del_timer(monitoring_timer); + return 0; + } + if (DA9052_SCALE_64X == msg.data) + sm_mon_interval = msecs_to_jiffies(DA9052_X64_WINDOW); + else if (DA9052_SCALE_32X == msg.data) + sm_mon_interval = msecs_to_jiffies(DA9052_X32_WINDOW); + else if (DA9052_SCALE_16X == msg.data) + sm_mon_interval = msecs_to_jiffies(DA9052_X16_WINDOW); + else if (DA9052_SCALE_8X == msg.data) + sm_mon_interval = msecs_to_jiffies(DA9052_X8_WINDOW); + else if (DA9052_SCALE_4X == msg.data) + sm_mon_interval = msecs_to_jiffies(DA9052_X4_WINDOW); + else if (DA9052_SCALE_2X == msg.data) + sm_mon_interval = msecs_to_jiffies(DA9052_X2_WINDOW); + else + sm_mon_interval = msecs_to_jiffies(DA9052_X1_WINDOW); + + } else if (strobing_filter_state == DISABLE) { + sm_strobe_filter_flag = DISABLE; + sm_mon_interval = msecs_to_jiffies(DA9052_ADC_TWDMIN_TIME); + if (DA9052_WDT_DISABLE == msg.data) { + sm_str_req = DISABLE; + del_timer(monitoring_timer); + return 0; + } + } else { + return STROBING_FILTER_ERROR; + } + mod_timer(monitoring_timer, jiffies + sm_mon_interval); + + return 0; +ssc_err: + da9052_unlock(wdt->da9052); + return -EIO; +} + +int da9052_sm_set_strobing_mode(u8 strobing_mode_state) +{ + if (strobing_mode_state == DA9052_STROBE_AUTO) + sm_strobe_mode_flag = DA9052_STROBE_AUTO; + else if (strobing_mode_state == DA9052_STROBE_MANUAL) + sm_strobe_mode_flag = DA9052_STROBE_MANUAL; + else + return STROBING_MODE_ERROR; + + return 0; +} + +int da9052_sm_strobe_wdt(void) +{ + sm_str_req = ENABLE; + return 0; +} + + s32 da9052_sm_set_wdt(struct da9052_wdt *wdt, u8 wdt_scaling) +{ + struct da9052_ssc_msg msg; + int ret = 0; + + + if (wdt_scaling > DA9052_SCALE_64X) + return INVALID_SCALING_VALUE; + + msg.addr = DA9052_CONTROLD_REG; + msg.data = 0; + da9052_lock(wdt->da9052); + ret = wdt->da9052->read(wdt->da9052, &msg); + if (ret) + goto ssc_err; + da9052_unlock(wdt->da9052); + + if (!((DA9052_WDT_DISABLE == (msg.data & DA9052_CONTROLD_TWDSCALE)) && + (DA9052_WDT_DISABLE == wdt_scaling))) { + msg.data = (msg.data & ~(DA9052_CONTROLD_TWDSCALE)); + msg.addr = DA9052_CONTROLD_REG; + + + da9052_lock(wdt->da9052); + ret = wdt->da9052->write(wdt->da9052, &msg); + if (ret) + goto ssc_err; + da9052_unlock(wdt->da9052); + + msleep(1); + da9052_lock(wdt->da9052); + ret = wdt->da9052->read(wdt->da9052, &msg); + if (ret) + goto ssc_err; + da9052_unlock(wdt->da9052); + + + msg.data |= wdt_scaling; + + da9052_lock(wdt->da9052); + ret = wdt->da9052->write(wdt->da9052, &msg); + if (ret) + goto ssc_err; + da9052_unlock(wdt->da9052); + + sm_str_req = DISABLE; + if (DA9052_WDT_DISABLE == wdt_scaling) { + del_timer(monitoring_timer); + return 0; + } + if (sm_strobe_filter_flag == ENABLE) { + if (DA9052_SCALE_64X == wdt_scaling) { + sm_mon_interval = + msecs_to_jiffies(DA9052_X64_WINDOW); + } else if (DA9052_SCALE_32X == wdt_scaling) { + sm_mon_interval = + msecs_to_jiffies(DA9052_X32_WINDOW); + } else if (DA9052_SCALE_16X == wdt_scaling) { + sm_mon_interval = + msecs_to_jiffies(DA9052_X16_WINDOW); + } else if (DA9052_SCALE_8X == wdt_scaling) { + sm_mon_interval = + msecs_to_jiffies(DA9052_X8_WINDOW); + } else if (DA9052_SCALE_4X == wdt_scaling) { + sm_mon_interval = + msecs_to_jiffies(DA9052_X4_WINDOW); + } else if (DA9052_SCALE_2X == wdt_scaling) { + sm_mon_interval = + msecs_to_jiffies(DA9052_X2_WINDOW); + } else { + sm_mon_interval = + msecs_to_jiffies(DA9052_X1_WINDOW); + } + } else { + sm_mon_interval = msecs_to_jiffies( + DA9052_ADC_TWDMIN_TIME); + } + mod_timer(monitoring_timer, jiffies + sm_mon_interval); + } + + return 0; +ssc_err: + da9052_unlock(wdt->da9052); + return -EIO; +} + +static int da9052_wdt_open(struct inode *inode, struct file *file) +{ + struct da9052_wdt *wdt = get_wdt_da9052(); + int ret; + printk(KERN_INFO"IN WDT OPEN \n"); + + if (!wdt) { + printk(KERN_INFO"Returning no device\n"); + return -ENODEV; + } + printk(KERN_INFO"IN WDT OPEN 1\n"); + + if (test_and_set_bit(0, &da9052_wdt_users)) + return -EBUSY; + + ret = da9052_sm_hw_init(wdt); + if (ret != 0) { + printk(KERN_ERR "Watchdog hw init failed\n"); + return ret; + } + + return nonseekable_open(inode, file); +} + +static int da9052_wdt_release(struct inode *inode, struct file *file) +{ + struct da9052_wdt *wdt = get_wdt_da9052(); + + if (da9052_wdt_expect_close == 42) + da9052_sm_hw_deinit(wdt); + else + da9052_sm_strobe_wdt(); + da9052_wdt_expect_close = 0; + clear_bit(0, &da9052_wdt_users); + return 0; +} + +static ssize_t da9052_wdt_write(struct file *file, + const char __user *data, size_t count, + loff_t *ppos) +{ + size_t i; + + if (count) { + if (!nowayout) { + /* In case it was set long ago */ + da9052_wdt_expect_close = 0; + for (i = 0; i != count; i++) { + char c; + if (get_user(c, data + i)) + return -EFAULT; + if (c == 'V') + da9052_wdt_expect_close = 42; + } + } + da9052_sm_strobe_wdt(); + } + return count; +} + +static struct watchdog_info da9052_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, + .identity = "DA9052_SM Watchdog", +}; + +static long da9052_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct da9052_wdt *wdt = get_wdt_da9052(); + void __user *argp = (void __user *)arg; + int __user *p = argp; + unsigned char new_value; + + switch (cmd) { + + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &da9052_wdt_info, + sizeof(da9052_wdt_info)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_SETOPTIONS: + if (get_user(new_value, p)) + return -EFAULT; + if (new_value & DA9052_STROBING_FILTER_ENABLE) + da9052_sm_set_strobing_filter(wdt, ENABLE); + if (new_value & DA9052_STROBING_FILTER_DISABLE) + da9052_sm_set_strobing_filter(wdt, DISABLE); + if (new_value & DA9052_SET_STROBING_MODE_MANUAL) + da9052_sm_set_strobing_mode(DA9052_STROBE_MANUAL); + if (new_value & DA9052_SET_STROBING_MODE_AUTO) + da9052_sm_set_strobing_mode(DA9052_STROBE_AUTO); + return 0; + case WDIOC_KEEPALIVE: + if (da9052_sm_strobe_wdt()) + return -EFAULT; + else + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_value, p)) + return -EFAULT; + da9052_sm_scale = new_value; + if (da9052_sm_set_wdt(wdt, da9052_sm_scale)) + return -EFAULT; + case WDIOC_GETTIMEOUT: + return put_user(sm_mon_interval, p); + default: + return -ENOTTY; + } + return 0; +} + +static const struct file_operations da9052_wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .unlocked_ioctl = da9052_wdt_ioctl, + .write = da9052_wdt_write, + .open = da9052_wdt_open, + .release = da9052_wdt_release, +}; + +static struct miscdevice da9052_wdt_miscdev = { + .minor = 255, + .name = "da9052-wdt", + .fops = &da9052_wdt_fops, +}; + +static int __devinit da9052_sm_probe(struct platform_device *pdev) +{ + int ret; + struct da9052_wdt *wdt; + struct da9052_ssc_msg msg; + + wdt = kzalloc(sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return -ENOMEM; + + wdt->da9052 = dev_get_drvdata(pdev->dev.parent); + platform_set_drvdata(pdev, wdt); + + msg.addr = DA9052_CONTROLD_REG; + msg.data = 0; + + da9052_lock(wdt->da9052); + ret = wdt->da9052->read(wdt->da9052, &msg); + if (ret) { + da9052_unlock(wdt->da9052); + goto err_ssc_comm; + } + printk(KERN_INFO"DA9052 SM probe - 0 \n"); + + msg.data = (msg.data & ~(DA9052_CONTROLD_TWDSCALE)); + ret = wdt->da9052->write(wdt->da9052, &msg); + if (ret) { + da9052_unlock(wdt->da9052); + goto err_ssc_comm; + } + da9052_unlock(wdt->da9052); + + da9052_wdt_miscdev.parent = &pdev->dev; + + ret = misc_register(&da9052_wdt_miscdev); + if (ret != 0) { + platform_set_drvdata(pdev, NULL); + kfree(wdt); + return -EFAULT; + } + return 0; +err_ssc_comm: + platform_set_drvdata(pdev, NULL); + kfree(wdt); + return -EIO; +} + +static int __devexit da9052_sm_remove(struct platform_device *dev) +{ + misc_deregister(&da9052_wdt_miscdev); + + return 0; +} + +static struct platform_driver da9052_sm_driver = { + .probe = da9052_sm_probe, + .remove = __devexit_p(da9052_sm_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init da9052_sm_init(void) +{ + return platform_driver_register(&da9052_sm_driver); +} +module_init(da9052_sm_init); + +static void __exit da9052_sm_exit(void) +{ + platform_driver_unregister(&da9052_sm_driver); +} +module_exit(da9052_sm_exit); + +MODULE_AUTHOR("David Dajun Chen ") +MODULE_DESCRIPTION("DA9052 SM Device Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/watchdog/mxc_wdt.c b/drivers/watchdog/mxc_wdt.c new file mode 100644 index 000000000000..eab9cecb9464 --- /dev/null +++ b/drivers/watchdog/mxc_wdt.c @@ -0,0 +1,376 @@ +/* + * linux/drivers/char/watchdog/mxc_wdt.c + * + * Watchdog driver for FSL MXC. It is based on omap1610_wdt.c + * + * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. + * 2005 (c) MontaVista Software, Inc. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * History: + * + * 20051207: + * Full rewrite based on + * linux-2.6.15-rc5/drivers/char/watchdog/omap_wdt.c + * Add platform resource support + * + */ + +/*! + * @defgroup WDOG Watchdog Timer (WDOG) Driver + */ +/*! + * @file mxc_wdt.c + * + * @brief Watchdog timer driver + * + * @ingroup WDOG + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_wdt.h" + +#define DVR_VER "2.0" + +#define WDOG_SEC_TO_COUNT(s) ((s * 2) << 8) +#define WDOG_COUNT_TO_SEC(c) ((c >> 8) / 2) + +static void __iomem *wdt_base_reg; +static int mxc_wdt_users; +static struct clk *mxc_wdt_clk; + +static unsigned timer_margin = TIMER_MARGIN_DEFAULT; +module_param(timer_margin, uint, 0); +MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); + +static unsigned dev_num; + +static void mxc_wdt_ping(void *base) +{ + /* issue the service sequence instructions */ + __raw_writew(WDT_MAGIC_1, base + MXC_WDT_WSR); + __raw_writew(WDT_MAGIC_2, base + MXC_WDT_WSR); +} + +static void mxc_wdt_config(void *base) +{ + u16 val; + + val = __raw_readw(base + MXC_WDT_WCR); + val |= 0xFF00 | WCR_WOE_BIT | WCR_WDA_BIT | WCR_SRS_BIT; + /* enable suspend WDT */ + val |= WCR_WDZST_BIT | WCR_WDBG_BIT; + /* generate reset if wdog times out */ + val &= ~WCR_WRE_BIT; + + __raw_writew(val, base + MXC_WDT_WCR); +} + +static void mxc_wdt_enable(void *base) +{ + u16 val; + + val = __raw_readw(base + MXC_WDT_WCR); + val |= WCR_WDE_BIT; + __raw_writew(val, base + MXC_WDT_WCR); +} + +static void mxc_wdt_disable(void *base) +{ + /* disable not supported by this chip */ +} + +static void mxc_wdt_adjust_timeout(unsigned new_timeout) +{ + if (new_timeout < TIMER_MARGIN_MIN) + new_timeout = TIMER_MARGIN_DEFAULT; + if (new_timeout > TIMER_MARGIN_MAX) + new_timeout = TIMER_MARGIN_MAX; + timer_margin = new_timeout; +} + +static u16 mxc_wdt_get_timeout(void *base) +{ + u16 val; + + val = __raw_readw(base + MXC_WDT_WCR); + return WDOG_COUNT_TO_SEC(val); +} + +static u16 mxc_wdt_get_bootreason(void *base) +{ + u16 val; + + val = __raw_readw(base + MXC_WDT_WRSR); + return val; +} + +static void mxc_wdt_set_timeout(void *base) +{ + u16 val; + val = __raw_readw(base + MXC_WDT_WCR); + val = (val & 0x00FF) | WDOG_SEC_TO_COUNT(timer_margin); + __raw_writew(val, base + MXC_WDT_WCR); + val = __raw_readw(base + MXC_WDT_WCR); + timer_margin = WDOG_COUNT_TO_SEC(val); +} + +/* + * Allow only one task to hold it open + */ + +static int mxc_wdt_open(struct inode *inode, struct file *file) +{ + + if (test_and_set_bit(1, (unsigned long *)&mxc_wdt_users)) + return -EBUSY; + + mxc_wdt_config(wdt_base_reg); + mxc_wdt_set_timeout(wdt_base_reg); + mxc_wdt_enable(wdt_base_reg); + mxc_wdt_ping(wdt_base_reg); + + return 0; +} + +static int mxc_wdt_release(struct inode *inode, struct file *file) +{ + /* + * Shut off the timer unless NOWAYOUT is defined. + */ +#ifndef CONFIG_WATCHDOG_NOWAYOUT + mxc_wdt_disable(wdt_base_reg); + +#else + printk(KERN_CRIT "mxc_wdt: Unexpected close, not stopping!\n"); +#endif + mxc_wdt_users = 0; + return 0; +} + +static ssize_t +mxc_wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) +{ + /* Refresh LOAD_TIME. */ + if (len) + mxc_wdt_ping(wdt_base_reg); + return len; +} + +static int +mxc_wdt_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int new_margin; + int bootr; + + static struct watchdog_info ident = { + .identity = "MXC Watchdog", + .options = WDIOF_SETTIMEOUT, + .firmware_version = 0, + }; + + switch (cmd) { + default: + return -ENOIOCTLCMD; + case WDIOC_GETSUPPORT: + return copy_to_user((struct watchdog_info __user *)arg, &ident, + sizeof(ident)); + case WDIOC_GETSTATUS: + return put_user(0, (int __user *)arg); + case WDIOC_GETBOOTSTATUS: + bootr = mxc_wdt_get_bootreason(wdt_base_reg); + return put_user(bootr, (int __user *)arg); + case WDIOC_KEEPALIVE: + mxc_wdt_ping(wdt_base_reg); + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_margin, (int __user *)arg)) + return -EFAULT; + + mxc_wdt_adjust_timeout(new_margin); + mxc_wdt_disable(wdt_base_reg); + mxc_wdt_set_timeout(wdt_base_reg); + mxc_wdt_enable(wdt_base_reg); + mxc_wdt_ping(wdt_base_reg); + return 0; + + case WDIOC_GETTIMEOUT: + mxc_wdt_ping(wdt_base_reg); + new_margin = mxc_wdt_get_timeout(wdt_base_reg); + return put_user(new_margin, (int __user *)arg); + } +} + +static struct file_operations mxc_wdt_fops = { + .owner = THIS_MODULE, + .write = mxc_wdt_write, + .ioctl = mxc_wdt_ioctl, + .open = mxc_wdt_open, + .release = mxc_wdt_release, +}; + +static struct miscdevice mxc_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &mxc_wdt_fops +}; + +static int __init mxc_wdt_probe(struct platform_device *pdev) +{ + struct resource *res, *mem; + int ret; + + /* reserve static register mappings */ + res = platform_get_resource(pdev, IORESOURCE_MEM, dev_num); + if (!res) + return -ENOENT; + + mem = request_mem_region(res->start, res->end - res->start + 1, + pdev->name); + if (mem == NULL) + return -EBUSY; + + platform_set_drvdata(pdev, mem); + + wdt_base_reg = ioremap(res->start, res->end - res->start + 1); + mxc_wdt_disable(wdt_base_reg); + mxc_wdt_adjust_timeout(timer_margin); + + mxc_wdt_users = 0; + + mxc_wdt_miscdev.this_device = &pdev->dev; + + mxc_wdt_clk = clk_get(NULL, "wdog_clk"); + clk_enable(mxc_wdt_clk); + + ret = misc_register(&mxc_wdt_miscdev); + if (ret) + goto fail; + + pr_info("MXC Watchdog # %d Timer: initial timeout %d sec\n", dev_num, + timer_margin); + + return 0; + + fail: + iounmap(wdt_base_reg); + release_resource(mem); + pr_info("MXC Watchdog Probe failed\n"); + return ret; +} + +static void mxc_wdt_shutdown(struct platform_device *pdev) +{ + mxc_wdt_disable(wdt_base_reg); + pr_info("MXC Watchdog # %d shutdown\n", dev_num); +} + +static int __exit mxc_wdt_remove(struct platform_device *pdev) +{ + struct resource *mem = platform_get_drvdata(pdev); + misc_deregister(&mxc_wdt_miscdev); + iounmap(wdt_base_reg); + release_resource(mem); + pr_info("MXC Watchdog # %d removed\n", dev_num); + return 0; +} + +#ifdef CONFIG_PM + +/* REVISIT ... not clear this is the best way to handle system suspend; and + * it's very inappropriate for selective device suspend (e.g. suspending this + * through sysfs rather than by stopping the watchdog daemon). Also, this + * may not play well enough with NOWAYOUT... + */ + +static int mxc_wdt_suspend(struct platform_device *pdev, pm_message_t state) +{ + if (mxc_wdt_users) { + mxc_wdt_disable(wdt_base_reg); + } + return 0; +} + +static int mxc_wdt_resume(struct platform_device *pdev) +{ + if (mxc_wdt_users) { + mxc_wdt_enable(wdt_base_reg); + mxc_wdt_ping(wdt_base_reg); + } + return 0; +} + +#else +#define mxc_wdt_suspend NULL +#define mxc_wdt_resume NULL +#endif + +static struct platform_driver mxc_wdt_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mxc_wdt", + }, + .probe = mxc_wdt_probe, + .shutdown = mxc_wdt_shutdown, + .remove = __exit_p(mxc_wdt_remove), + .suspend = mxc_wdt_suspend, + .resume = mxc_wdt_resume, +}; + +static int __init mxc_wdt_init(void) +{ + pr_info("MXC WatchDog Driver %s\n", DVR_VER); + + if ((timer_margin < TIMER_MARGIN_MIN) || + (timer_margin > TIMER_MARGIN_MAX)) { + pr_info("MXC watchdog error. wrong timer_margin %d\n", + timer_margin); + pr_info(" Range: %d to %d seconds\n", TIMER_MARGIN_MIN, + TIMER_MARGIN_MAX); + return -EINVAL; + } + + return platform_driver_register(&mxc_wdt_driver); +} + +static void __exit mxc_wdt_exit(void) +{ + platform_driver_unregister(&mxc_wdt_driver); + pr_info("MXC WatchDog Driver removed\n"); +} + +module_init(mxc_wdt_init); +module_exit(mxc_wdt_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); diff --git a/drivers/watchdog/mxc_wdt.h b/drivers/watchdog/mxc_wdt.h new file mode 100644 index 000000000000..061731b46b61 --- /dev/null +++ b/drivers/watchdog/mxc_wdt.h @@ -0,0 +1,37 @@ +/* + * linux/drivers/char/watchdog/mxc_wdt.h + * + * BRIEF MODULE DESCRIPTION + * MXC Watchdog timer register definitions + * + * Author: MontaVista Software, Inc. + * or + * + * 2005 (c) MontaVista Software, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __MXC_WDT_H__ +#define __MXC_WDT_H__ + +#define MXC_WDT_WCR 0x00 +#define MXC_WDT_WSR 0x02 +#define MXC_WDT_WRSR 0x04 +#define WCR_WOE_BIT (1 << 6) +#define WCR_WDA_BIT (1 << 5) +#define WCR_SRS_BIT (1 << 4) +#define WCR_WRE_BIT (1 << 3) +#define WCR_WDE_BIT (1 << 2) +#define WCR_WDBG_BIT (1 << 1) +#define WCR_WDZST_BIT (1 << 0) +#define WDT_MAGIC_1 0x5555 +#define WDT_MAGIC_2 0xAAAA + +#define TIMER_MARGIN_MAX 127 +#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */ +#define TIMER_MARGIN_MIN 1 + +#endif /* __MXC_WDT_H__ */ diff --git a/drivers/watchdog/mxs-wdt.c b/drivers/watchdog/mxs-wdt.c new file mode 100644 index 000000000000..7f3615b833f6 --- /dev/null +++ b/drivers/watchdog/mxs-wdt.c @@ -0,0 +1,303 @@ +/* + * Watchdog driver for Freescale STMP37XX/STMP378X + * + * Author: Vitaly Wool + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DEFAULT_HEARTBEAT 19 +#define MAX_HEARTBEAT (0x10000000 >> 6) + +/* missing bitmask in headers */ +#define BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER 0x80000000 + +#define WDT_IN_USE 0 +#define WDT_OK_TO_CLOSE 1 + +#define WDOG_COUNTER_RATE 1000 /* 1 kHz clock */ + +static unsigned long wdt_status; +static int heartbeat = DEFAULT_HEARTBEAT; +static unsigned long boot_status; +static unsigned long wdt_base; +static DEFINE_SPINLOCK(mxs_wdt_io_lock); + +static void wdt_enable(u32 value) +{ + spin_lock(&mxs_wdt_io_lock); + __raw_writel(value, wdt_base + HW_RTC_WATCHDOG); + __raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER, + wdt_base + HW_RTC_PERSISTENT1_SET); + __raw_writel(BM_RTC_CTRL_WATCHDOGEN, wdt_base + HW_RTC_CTRL_SET); + spin_unlock(&mxs_wdt_io_lock); +} + +static void wdt_disable(void) +{ + spin_lock(&mxs_wdt_io_lock); + __raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER, + wdt_base + HW_RTC_PERSISTENT1_CLR); + __raw_writel(BM_RTC_CTRL_WATCHDOGEN, wdt_base + HW_RTC_CTRL_CLR); + spin_unlock(&mxs_wdt_io_lock); +} + +static void wdt_ping(void) +{ + wdt_enable(heartbeat * WDOG_COUNTER_RATE); +} + +static int mxs_wdt_open(struct inode *inode, struct file *file) +{ + if (test_and_set_bit(WDT_IN_USE, &wdt_status)) + return -EBUSY; + + clear_bit(WDT_OK_TO_CLOSE, &wdt_status); + wdt_ping(); + + return nonseekable_open(inode, file); +} + +static ssize_t mxs_wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) +{ + if (len) { + if (WATCHDOG_NOWAYOUT == 0) { + size_t i; + + clear_bit(WDT_OK_TO_CLOSE, &wdt_status); + + for (i = 0; i != len; i++) { + char c; + + if (get_user(c, data + i)) + return -EFAULT; + if (c == 'V') + set_bit(WDT_OK_TO_CLOSE, &wdt_status); + } + } + wdt_ping(); + } + + return len; +} + +static struct watchdog_info ident = { + .options = WDIOF_CARDRESET | + WDIOF_MAGICCLOSE | + WDIOF_SETTIMEOUT | + WDIOF_KEEPALIVEPING, + .identity = "MXS Watchdog", +}; + +static long mxs_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + void __user *argp = (void __user *)arg; + int __user *p = argp; + int new_heartbeat, opts; + int ret = -ENOTTY; + + switch (cmd) { + case WDIOC_GETSUPPORT: + ret = copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + break; + + case WDIOC_GETSTATUS: + ret = put_user(0, p); + break; + + case WDIOC_GETBOOTSTATUS: + ret = put_user(boot_status, p); + break; + + case WDIOC_SETOPTIONS: + if (get_user(opts, p)) { + ret = -EFAULT; + break; + } + if (opts & WDIOS_DISABLECARD) + wdt_disable(); + else if (opts & WDIOS_ENABLECARD) + wdt_ping(); + else { + pr_debug("%s: unknown option 0x%x\n", __func__, opts); + ret = -EINVAL; + break; + } + ret = 0; + break; + + case WDIOC_KEEPALIVE: + wdt_ping(); + ret = 0; + break; + + case WDIOC_SETTIMEOUT: + if (get_user(new_heartbeat, p)) { + ret = -EFAULT; + break; + } + if (new_heartbeat <= 0 || new_heartbeat > MAX_HEARTBEAT) { + ret = -EINVAL; + break; + } + + heartbeat = new_heartbeat; + wdt_ping(); + /* Fall through */ + + case WDIOC_GETTIMEOUT: + ret = put_user(heartbeat, p); + break; + } + return ret; +} + +static int mxs_wdt_release(struct inode *inode, struct file *file) +{ + int ret = 0; + + if (WATCHDOG_NOWAYOUT == 0) { + if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status)) { + wdt_ping(); + pr_debug("%s: Device closed unexpectdly\n", __func__); + ret = -EINVAL; + } else { + wdt_disable(); + clear_bit(WDT_OK_TO_CLOSE, &wdt_status); + } + } + clear_bit(WDT_IN_USE, &wdt_status); + + return ret; +} + +static const struct file_operations mxs_wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = mxs_wdt_write, + .unlocked_ioctl = mxs_wdt_ioctl, + .open = mxs_wdt_open, + .release = mxs_wdt_release, +}; + +static struct miscdevice mxs_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &mxs_wdt_fops, +}; + +static int __devinit mxs_wdt_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *res; + + if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) + heartbeat = DEFAULT_HEARTBEAT; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) + return -ENODEV; + wdt_base = (unsigned long)IO_ADDRESS(res->start); + + boot_status = __raw_readl(wdt_base + HW_RTC_PERSISTENT1) & + BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER; + boot_status = !!boot_status; + __raw_writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER, + wdt_base + HW_RTC_PERSISTENT1_CLR); + + wdt_disable(); /* disable for now */ + + ret = misc_register(&mxs_wdt_miscdev); + if (ret < 0) { + dev_err(&pdev->dev, "cannot register misc device\n"); + return ret; + } + + printk(KERN_INFO "mxs watchdog: initialized, heartbeat %d sec\n", + heartbeat); + + return ret; +} + +static int __devexit mxs_wdt_remove(struct platform_device *pdev) +{ + misc_deregister(&mxs_wdt_miscdev); + return 0; +} + +#ifdef CONFIG_PM +static int wdt_suspended; +static u32 wdt_saved_time; + +static int mxs_wdt_suspend(struct platform_device *pdev, + pm_message_t state) +{ + if (__raw_readl(wdt_base + HW_RTC_CTRL) & BM_RTC_CTRL_WATCHDOGEN) { + wdt_saved_time = __raw_readl(wdt_base + HW_RTC_WATCHDOG); + wdt_disable(); + wdt_suspended = 1; + } + return 0; +} + +static int mxs_wdt_resume(struct platform_device *pdev) +{ + if (wdt_suspended) { + wdt_suspended = 0; + wdt_enable(wdt_saved_time); + } + return 0; +} +#else +#define mxs_wdt_suspend NULL +#define mxs_wdt_resume NULL +#endif + +static struct platform_driver mxs_wdt_driver = { + .driver = { + .name = "mxs-wdt", + }, + .probe = mxs_wdt_probe, + .remove = __devexit_p(mxs_wdt_remove), + .suspend = mxs_wdt_suspend, + .resume = mxs_wdt_resume, +}; + +static int __init mxs_wdt_init(void) +{ + return platform_driver_register(&mxs_wdt_driver); +} + +static void __exit mxs_wdt_exit(void) +{ + return platform_driver_unregister(&mxs_wdt_driver); +} + +module_init(mxs_wdt_init); +module_exit(mxs_wdt_exit); + +MODULE_DESCRIPTION("MXS Watchdog Driver"); +MODULE_LICENSE("GPL"); + +module_param(heartbeat, int, 0); +MODULE_PARM_DESC(heartbeat, + "Watchdog heartbeat period in seconds from 1 to " + __MODULE_STRING(MAX_HEARTBEAT) ", default " + __MODULE_STRING(DEFAULT_HEARTBEAT)); + +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); diff --git a/firmware/Makefile b/firmware/Makefile index 020e629a615c..2f1c370909bc 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -138,6 +138,9 @@ fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin +fw-shipped-$(CONFIG_FB_MXC_EINK_PANEL) += imx/epdc_E60_V110.fw \ + imx/epdc_E60_V220.fw \ + imx/epdc_E97_V110.fw \ fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) diff --git a/firmware/imx/epdc_E60_V110.fw.ihex b/firmware/imx/epdc_E60_V110.fw.ihex new file mode 100644 index 000000000000..eca54786f1c4 --- /dev/null +++ b/firmware/imx/epdc_E60_V110.fw.ihex @@ -0,0 +1,45914 @@ +:10000000C7FFA986DE9C0000E30100000003250075 +:100010000127020E3C03000000000000400000C366 +:100020004700000100030D00FFFC0000000000532A +:10003000000306090C0F1215181B1E21262B302059 +:10004000000000000000000017050000000000E0B4 +:1000500011060000000000C03509000000000090FB +:10006000000000000000009895000000000000A0C3 +:1000700016010000000000A885010000000000B08B +:10008000F2010000000000B85D020000000000C0A6 +:10009000C0020000000000C81B030000000000D0E8 +:1000A00074030000000000D8C9030000000000E055 +:1000B0001E040000000000E863040000000000F0DF +:1000C0009E040000000000F8D70400000000009526 +:1000D0000000000000000001010101010101010117 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010198 +:100850000101010101010101010101010101010188 +:100860000101010101010101010101010101010178 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010118 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000001010101010101010101010101010101D2 +:100E100001010101010101010101010101010101C2 +:100E200001010101010101010101010101010101B2 +:100E300001010101010101010101010101010101A2 +:100E40000101010101010101010101010101010192 +:100E50000101010101010101010101010101010182 +:100E60000101010101010101010101010101010172 +:100E70000101010101010101010101010101010162 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101010101010101010101E2 +:100F000001010101010101010101010101010101D1 +:100F100001010101010101010101010101010101C1 +:100F200001010101010101010101010101010101B1 +:100F300001010101010101010101010101010101A1 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000101010101010101010101010101010171 +:100F70000101010101010101010101010101010161 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101010101010101010101E1 +:1010000001010101010101010101010101010101D0 +:1010100001010101010101010101010101010101C0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000101010101010101010101010101010170 +:101070000101010101010101010101010101010160 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010101010101BF +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:10116000010101010101010101010101010101016F +:10117000010101010101010101010101010101015F +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010101010101BE +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101016E +:10127000010101010101010101010101010101015E +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101010101010101010101BD +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101016D +:10137000010101010101010101010101010101015D +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101016C +:10147000010101010101010101010101010101015C +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101018B +:10155000010101010101010101010101010101017B +:10156000010101010101010101010101010101016B +:10157000010101010101010101010101010101015B +:10158000010101010101010101010101010101014B +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010101010101010101019A +:10164000010101010101010101010101010101018A +:10165000010101010101010101010101010101017A +:10166000010101010101010101010101010101016A +:10167000010101010101010101010101010101015A +:10168000010101010101010101010101010101014A +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010101010101010101010157 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101000000000000000000FC +:101DE00000000000000000000000000000000000F3 +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E300000000000000000000000000000000000A2 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000000000000000000022 +:101EC0000000000000000000000000000000000012 +:101ED0000000000000000000000000000000000002 +:101EE00000000000000000000000000000000000F2 +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000000000000000000B1 +:101F300000000000000000000000000000000000A1 +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F80000000000000000000000000000000000051 +:101F90000000000000000000000000000000000041 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000000000000000000021 +:101FC0000000000000000000000000000000000011 +:101FD0000000000000000000000000000000000001 +:101FE00000000000000000000000000000000000F1 +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000000000000000000B0 +:1020300000000000000000000000000000000000A0 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000000000000000010 +:1020D0000000000000000000000000000000000000 +:1020E00000000000000000000000000000000000F0 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00000000000000000020202020202020202EB +:1023E00002020202020202020202020202020202CD +:1023F00002020202020202020202020202020202BD +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202020202020202020202DC +:1024E00002020202020202020202020202020202CC +:1024F00002020202020202020202020202020202BC +:1025000002020202020202020202020202020202AB +:10251000020202020202020202020202020202029B +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C00002020202020202020202020202020202EB +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020202CB +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202020202020202020202DA +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020202D3 +:102DE00002020202020202020202020202020202C3 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020202D2 +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202000000000000000000D2 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000010101010101010101CB +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101016D +:10533000010101010101010101010101010101015D +:10534000010101010101010101010101010101014D +:10535000010101010101010101010101010101013D +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101010D +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010101010101BD +:1053E00001010101010101010101010101010101AD +:1053F000010101010101010101010101010101019D +:10540000010101010101010101010101010101018C +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101016C +:10543000010101010101010101010101010101015C +:10544000010101010101010101010101010101014C +:10545000010101010101010101010101010101013C +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101010101010101010101BC +:1054E00001010101010101010101010101010101AC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:10553000010101010101010101010101010101015B +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000101010101010101010101010101010169 +:105730000101010101010101010101010101010159 +:105740000101010101010101010101010101010149 +:105750000101010101010101010101010101010139 +:105760000101010101010101010101010101010129 +:105770000101010101010101010101010101010119 +:105780000101010101010101010101010101010109 +:1057900001010101010101010101010101010101F9 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101010101010101010101B9 +:1057E00001010101010101010101010101010101A9 +:1057F0000101010101010101010101010101010199 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010187 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000101010101010101010101010101010186 +:105A10000101010101010101010101010101010176 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010101010101010101010116 +:105A80000101010101010101010101010101010106 +:105A900001010101010101010101010101010101F6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00001010101010101010101010101010101C6 +:105AD00001010101010101010101010101010101B6 +:105AE00001010101010101010101010101010101A6 +:105AF0000101010101010101010101010101010196 +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010175 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101010101010101010145 +:105B50000101010101010101010101010101010135 +:105B60000101010101010101010101010101010125 +:105B70000101010101010101010101010101010115 +:105B80000101010101010101010101010101010105 +:105B900001010101010101010101010101010101F5 +:105BA00001010101010101010101010101010101E5 +:105BB00001010101010101010101010101010101D5 +:105BC00001010101010101010101010101010101C5 +:105BD00001010101010101010101010101010101B5 +:105BE00001010101010101010101010101010101A5 +:105BF0000101010101010101010101010101010195 +:105C00000101010101010101010101010101010184 +:105C10000101010101010101010101010101010174 +:105C20000101010101010101010101010101010164 +:105C30000101010101010101010101010101010154 +:105C40000101010101010101010101010101010144 +:105C50000101010101010101010101010101010134 +:105C60000101010101010101010101010101010124 +:105C70000101010101010101010101010101010114 +:105C80000101010101010101010101010101010104 +:105C900001010101010101010101010101010101F4 +:105CA00001010101010101010101010101010101E4 +:105CB00001010101010101010101010101010101D4 +:105CC00001010101010101010101010101010101C4 +:105CD00001010101010101010101010101010101B4 +:105CE00001010101010101010101010101010101A4 +:105CF0000101010101010101010101010101010194 +:105D00000101010101010101010101010101010183 +:105D10000101010101010101010101010101010173 +:105D20000101010101010101010101010101010163 +:105D30000101010101010101010101010101010153 +:105D40000101010101010101010101010101010143 +:105D50000101010101010101010101010101010133 +:105D60000101010101010101010101010101010123 +:105D70000101010101010101010101010101010113 +:105D80000101010101010101010101010101010103 +:105D900001010101010101010101010101010101F3 +:105DA00001010101010101010101010101010101E3 +:105DB00001010101010101010101010101010101D3 +:105DC00001010101010101010101010101010101C3 +:105DD00001010101010101010101010101010101B3 +:105DE00001010101010101010101010101010101A3 +:105DF0000101010101010101010101010101010193 +:105E00000101010101010101010101010101010182 +:105E10000101010101010101010101010101010172 +:105E20000101010101010101010101010101010162 +:105E30000101010101010101010101010101010152 +:105E40000101010101010101010101010101010142 +:105E50000101010101010101010101010101010132 +:105E60000101010101010101010101010101010122 +:105E70000101010101010101010101010101010112 +:105E80000101010101010101010101010101010102 +:105E900001010101010101010101010101010101F2 +:105EA00001010101010101010101010101010101E2 +:105EB00001010101010101010101010101010101D2 +:105EC00001010101010101010101010101010101C2 +:105ED00001010101010101010101010101010101B2 +:105EE00001010101010101010101010101010101A2 +:105EF0000101010101010101010101010101010192 +:105F00000101010101010101010101010101010181 +:105F10000101010101010101010101010101010171 +:105F20000101010101010101010101010101010161 +:105F30000101010101010101010101010101010151 +:105F40000101010101010101010101010101010141 +:105F50000101010101010101010101010101010131 +:105F60000101010101010101010101010101010121 +:105F70000101010101010101010101010101010111 +:105F80000101010101010101010101010101010101 +:105F900001010101010101010101010101010101F1 +:105FA00001010101010101010101010101010101E1 +:105FB00001010101010101010101010101010101D1 +:105FC00001010101010101010101010101010101C1 +:105FD00001010101010101010101010101010101B1 +:105FE00001010101010101010101010101010101A1 +:105FF0000101010101010101010101010101010191 +:106000000101010101010101010101010101010180 +:106010000101010101010101010101010101010170 +:106020000101010101010101010101010101010160 +:106030000101010101010101010101010101010150 +:106040000101010101010101010101010101010140 +:106050000101010101010101010101010101010130 +:106060000101010101010101010101010101010120 +:106070000101010101010101010101010101010110 +:106080000101010101010101010101010101010100 +:1060900001010101010101010101010101010101F0 +:1060A00001010101010101010101010101010101E0 +:1060B00001010101010101010101010101010101D0 +:1060C00001010101010101010101010101010101C0 +:1060D00001010101010101010101010101010101B0 +:1060E00001010101010101010101010101010101A0 +:1060F0000101010101010101010101010101010190 +:10610000010101010101010101010101010101017F +:10611000010101010101010101010101010101016F +:10612000010101010101010101010101010101015F +:10613000010101010101010101010101010101014F +:10614000010101010101010101010101010101013F +:10615000010101010101010101010101010101012F +:10616000010101010101010101010101010101011F +:10617000010101010101010101010101010101010F +:1061800001010101010101010101010101010101FF +:1061900001010101010101010101010101010101EF +:1061A00001010101010101010101010101010101DF +:1061B00001010101010101010101010101010101CF +:1061C00001010101010101010101010101010101BF +:1061D00001010101010101010101010101010101AF +:1061E000010101010101010101010101010101019F +:1061F000010101010101010101010101010101018F +:10620000010101010101010101010101010101017E +:10621000010101010101010101010101010101016E +:10622000010101010101010101010101010101015E +:10623000010101010101010101010101010101014E +:10624000010101010101010101010101010101013E +:10625000010101010101010101010101010101012E +:10626000010101010101010101010101010101011E +:10627000010101010101010101010101010101010E +:1062800001010101010101010101010101010101FE +:1062900001010101010101010101010101010101EE +:1062A00001010101010101010101010101010101DE +:1062B00001010101010101010101010101010101CE +:1062C00001010101010101010101010101010101BE +:1062D00001010101010101010101010101010101AE +:1062E000010101010101010101010101010101019E +:1062F000010101010101010101010101010101018E +:10630000010101010101010101010101010101017D +:10631000010101010101010101010101010101016D +:10632000010101010101010101010101010101015D +:10633000010101010101010101010101010101014D +:10634000010101010101010101010101010101013D +:10635000010101010101010101010101010101012D +:10636000010101010101010101010101010101011D +:10637000010101010101010101010101010101010D +:1063800001010101010101010101010101010101FD +:1063900001010101010101010101010101010101ED +:1063A00001010101010101010101010101010101DD +:1063B00001010101010101010101010101010101CD +:1063C00001010101010101010101010101010101BD +:1063D00001010101010101010101010101010101AD +:1063E000010101010101010101010101010101019D +:1063F000010101010101010101010101010101018D +:10640000010101010101010101010101010101017C +:10641000010101010101010101010101010101016C +:10642000010101010101010101010101010101015C +:10643000010101010101010101010101010101014C +:10644000010101010101010101010101010101013C +:10645000010101010101010101010101010101012C +:10646000010101010101010101010101010101011C +:10647000010101010101010101010101010101010C +:1064800001010101010101010101010101010101FC +:1064900001010101010101010101010101010101EC +:1064A00001010101010101010101010101010101DC +:1064B00001010101010101010101010101010101CC +:1064C00001010101010101010101010101010101BC +:1064D00001010101010101010101010101010101AC +:1064E000010101010101010101010101010101019C +:1064F000010101010101010101010101010101018C +:10650000010101010101010101010101010101017B +:10651000010101010101010101010101010101016B +:10652000010101010101010101010101010101015B +:10653000010101010101010101010101010101014B +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010101010101010101FB +:1065900001010101010101010101010101010101EB +:1065A00001010101010101010101010101010101DB +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101018B +:10660000010101010101010101010101010101017A +:10661000010101010101010101010101010101016A +:10662000010101010101010101010101010101015A +:10663000010101010101010101010101010101014A +:10664000010101010101010101010101010101013A +:10665000010101010101010101010101010101012A +:10666000010101010101010101010101010101011A +:10667000010101010101010101010101010101010A +:1066800001010101010101010101010101010101FA +:1066900001010101010101010101010101010101EA +:1066A00001010101010101010101010101010101DA +:1066B00001010101010101010101010101010101CA +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101010101010101010101AA +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101018A +:106700000101010101010101010101010101010179 +:106710000101010101010101010101010101010169 +:106720000101010101010101010101010101010159 +:106730000101010101010101010101010101010149 +:106740000101010101010101010101010101010139 +:106750000101010101010101010101010101010129 +:106760000101010101010101010101010101010119 +:106770000101010101010101010101010101010109 +:1067800001010101010101010101010101010101F9 +:1067900001010101010101010101010101010101E9 +:1067A00001010101010101010101010101010101D9 +:1067B00001010101010101010101010101010101C9 +:1067C00001010101010101010101010101010101B9 +:1067D00001010101010101010101010101010101A9 +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010178 +:106810000101010101010101010101010101010168 +:106820000101010101010101010101010101010158 +:106830000101010101010101010101010101010148 +:106840000101010101010101010101010101010138 +:106850000101010101010101010101010101010128 +:106860000101010101010101010101010101010118 +:106870000101010101010101010101010101010108 +:1068800001010101010101010101010101010101F8 +:1068900001010101010101010101010101010101E8 +:1068A00001010101010101010101010101010101D8 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010147 +:106940000101010101010101010101010101010137 +:106950000101010101010101010101010101010127 +:106960000101010101010101010101010101010117 +:106970000101010101010101010101010101010107 +:1069800001010101010101010101010101010101F7 +:1069900001010101010101010101010101010101E7 +:1069A00001010101010101010101010101010101D7 +:1069B00001010101010101010101010101010101C7 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101000000000000000000B0 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000097 +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000000B6 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000096 +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000035 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD000000000000000000202020202020202029F +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202020286 +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020202020285 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020202B4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202020202020202020284 +:107CE0000202020202020202020202020202020274 +:107CF0000202020202020202020202020202020264 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020202020202020283 +:107DE0000202020202020202020202020202020273 +:107DF0000202020202020202020202020202020263 +:107E00000202020202020202020202020202020252 +:107E10000202020202020202020202020202020242 +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020202C2 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020202020202020202020282 +:107EE0000202020202020202020202020202020272 +:107EF0000202020202020202020202020202020262 +:107F00000202020202020202020202020202020251 +:107F10000202020202020202020202020202020241 +:107F20000202020202020202020202020202020231 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020202C1 +:107FA00002020202020202020202020202020202B1 +:107FB00002020202020202020202020202020202A1 +:107FC0000202020202020202020202020202020291 +:107FD0000202020202020202020202020202020281 +:107FE0000202020202020202020202020202020271 +:107FF0000202020202020202020202020202020261 +:108000000202020202020202020202020202020250 +:108010000202020202020202020202020202020240 +:108020000202020202020202020202020202020230 +:108030000202020202020202020202020202020220 +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202020202020202020202C0 +:1080A00002020202020202020202020202020202B0 +:1080B00002020202020202020202020202020202A0 +:1080C0000202020202020202020202020202020290 +:1080D0000202020202020202020202020202020280 +:1080E0000202020202020202020202020202020270 +:1080F0000202020202020202020202020202020260 +:10810000020202020202020202020202020202024F +:10811000020202020202020202020202020202023F +:10812000020202020202020202020202020202022F +:10813000020202020202020202020202020202021F +:10814000020202020202020202020202020202020F +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202020202020202020202BF +:1081A00002020202020202020202020202020202AF +:1081B000020202020202020202020202020202029F +:1081C000020202020202020202020202020202028F +:1081D000020202020202020202020202020202027F +:1081E000020202020202020202020202020202026F +:1081F000020202020202020202020202020202025F +:10820000020202020202020202020202020202024E +:10821000020202020202020202020202020202023E +:10822000020202020202020202020202020202022E +:10823000020202020202020202020202020202021E +:10824000020202020202020202020202020202020E +:1082500002020202020202020202020202020202FE +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202020202020202020202BE +:1082A00002020202020202020202020202020202AE +:1082B000020202020202020202020202020202029E +:1082C000020202020202020202020202020202028E +:1082D000020202020202020202020202020202027E +:1082E000020202020202020202020202020202026E +:1082F000020202020202020202020202020202025E +:10830000020202020202020202020202020202024D +:10831000020202020202020202020202020202023D +:10832000020202020202020202020202020202022D +:10833000020202020202020202020202020202021D +:10834000020202020202020202020202020202020D +:1083500002020202020202020202020202020202FD +:1083600002020202020202020202020202020202ED +:1083700002020202020202020202020202020202DD +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020202BD +:1083A00002020202020202020202020202020202AD +:1083B000020202020202020202020202020202029D +:1083C000020202020202020202020202020202028D +:1083D000020202020202020202020202020202027D +:1083E000020202020202020202020202020202026D +:1083F000020202020202020202020202020202025D +:10840000020202020202020202020202020202024C +:10841000020202020202020202020202020202023C +:10842000020202020202020202020202020202022C +:10843000020202020202020202020202020202021C +:10844000020202020202020202020202020202020C +:1084500002020202020202020202020202020202FC +:1084600002020202020202020202020202020202EC +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020202BC +:1084A00002020202020202020202020202020202AC +:1084B000020202020202020202020202020202029C +:1084C000020202020202020202020202020202028C +:1084D000020202020202020202020202020202027C +:1084E000020202020202020202020202020202026C +:1084F000020202020202020202020202020202025C +:10850000020202020202020202020202020202024B +:10851000020202020202020202020202020202023B +:10852000020202020202020202020202020202022B +:10853000020202020202020202020202020202021B +:10854000020202020202020202020202020202020B +:1085500002020202020202020202020202020202FB +:1085600002020202020202020202020202020202EB +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020202AB +:1085B000020202020202020202020202020202029B +:1085C000020202020202020202020202020202028B +:1085D000020202020202020202020202020202027B +:1085E000020202020202020202020202020202026B +:1085F000020202020202020202020202020202025B +:10860000020202020202020202020202020202024A +:10861000020202020202020202020202020202023A +:10862000020202020202020202020202020202022A +:10863000020202020202020202020202020202021A +:10864000020202020202020202020202020202020A +:1086500002020202020202020202020202020202FA +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202020202DA +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020202AA +:1086B000020202020202020202020202020202029A +:1086C000020202020202020202020202020202028A +:1086D000020202020202020202020202020202027A +:1086E000020202020202020202020202020202026A +:1086F000020202020202020202020202020202025A +:108700000202020202020202020202020202020249 +:108710000202020202020202020202020202020239 +:108720000202020202020202020202020202020229 +:108730000202020202020202020202020202020219 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020202A9 +:1087B0000202020202020202020202020202020299 +:1087C0000202020202020202020202020202020289 +:1087D0000202020202020202020202020202020279 +:1087E0000202020202020202020202020202020269 +:1087F0000202020202020202020202020202020259 +:108800000202020202020202020202020202020248 +:108810000202020202020202020202020202020238 +:108820000202020202020202020202020202020228 +:108830000202020202020202020202020202020218 +:108840000202020202020202020202020202020208 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202020202020202020202D8 +:1088800002020202020202020202020202020202C8 +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202020202A8 +:1088B0000202020202020202020202020202020298 +:1088C0000202020202020202020202020202020288 +:1088D0000202020202020202020202020202020278 +:1088E0000202020202020202020202020202020268 +:1088F0000202020202020202020202020202020258 +:108900000202020202020202020202020202020247 +:108910000202020202020202020202020202020237 +:108920000202020202020202020202020202020227 +:108930000202020202020202020202020202020217 +:108940000202020202020202020202020202020207 +:1089500002020202020202020202020202020202F7 +:1089600002020202020202020202020202020202E7 +:1089700002020202020202020202020202020202D7 +:1089800002020202020202020202020202020202C7 +:1089900002020202020202020202020202020202B7 +:1089A00002020202020202020202020202020202A7 +:1089B0000202020202020202020202020202020297 +:1089C0000202020202020202020202020202020287 +:1089D0000202020202020202020202020202020277 +:1089E0000202020202020202020202020202020267 +:1089F0000202020202020202020202020202020257 +:108A00000202020202020202020202020202020246 +:108A10000202020202020202020202020202020236 +:108A20000202020202020202020202020202020226 +:108A30000202020202020202020202020202020216 +:108A40000202020202020202020202020202020206 +:108A500002020202020202020202020202020202F6 +:108A600002020202020202020202020202020202E6 +:108A700002020202020202020202020202020202D6 +:108A800002020202020202020202020202020202C6 +:108A900002020202020202020202020202020202B6 +:108AA00002020202020202020202020202020202A6 +:108AB0000202020202020202020202020202020296 +:108AC0000202020202020202020202020202020286 +:108AD0000202020202020202020202020202020276 +:108AE0000202020202020202020202020202020266 +:108AF0000202020202020202020202020202020256 +:108B00000202020202020202020202020202020245 +:108B10000202020202020202020202020202020235 +:108B20000202020202020202020202020202020225 +:108B30000202020202020202020202020202020215 +:108B40000202020202020202020202020202020205 +:108B500002020202020202020202020202020202F5 +:108B600002020202020202020202020202020202E5 +:108B700002020202020202020202020202020202D5 +:108B800002020202020202020202020202020202C5 +:108B900002020202020202020202020202020202B5 +:108BA00002020202020202020202020202020202A5 +:108BB0000202020202020202020202020202020295 +:108BC0000202020202020202020202020202020285 +:108BD0000202020202020202020202020202020275 +:108BE0000202020202020202020202020202020265 +:108BF0000202020202020202020202020202020255 +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202020202020202020202C4 +:108C900002020202020202020202020202020202B4 +:108CA00002020202020202020202020202020202A4 +:108CB0000202020202020202020202020202020294 +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020200000000000000000086 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D0000000000000000081000000000000000109 +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010101DD +:10A3700001010101010101010101010101010101CD +:10A3800001010101010101010101010101010101BD +:10A3900001010101010101010101010101010101AD +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010101DC +:10A4700001010101010101010101010101010101CC +:10A4800001010101010101010101010101010101BC +:10A4900001010101010101010101010101010101AC +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800001010101010101010101010101010101BB +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010101010101010101010101010101BA +:10A6900001010101010101010101010101010101AA +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010101B9 +:10A7900001010101010101010101010101010101A9 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB10000101010101010101010101010101010125 +:10AB20000101010101010101010101010101010115 +:10AB30000101010101010101010101010101010105 +:10AB400001010101010101010101010101010101F5 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010101C5 +:10AB800001010101010101010101010101010101B5 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010185 +:10ABC0000101010101010101010101010101010175 +:10ABD0000101010101010101010101010101010165 +:10ABE0000101010101010101010101010101010155 +:10ABF0000101010101010101010101010101010145 +:10AC00000101010101010101010101010101010134 +:10AC10000101010101010101010101010101010124 +:10AC20000101010101010101010101010101010114 +:10AC30000101010101010101010101010101010104 +:10AC400001010101010101010101010101010101F4 +:10AC500001010101010101010101010101010101E4 +:10AC600001010101010101010101010101010101D4 +:10AC700001010101010101010101010101010101C4 +:10AC800001010101010101010101010101010101B4 +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010184 +:10ACC0000101010101010101010101010101010174 +:10ACD0000101010101010101010101010101010164 +:10ACE0000101010101010101010101010101010154 +:10ACF0000101010101010101010101010101010144 +:10AD00000101010101010101010101010101010133 +:10AD10000101010101010101010101010101010123 +:10AD20000101010101010101010101010101010113 +:10AD30000101010101010101010101010101010103 +:10AD400001010101010101010101010101010101F3 +:10AD500001010101010101010101010101010101E3 +:10AD600001010101010101010101010101010101D3 +:10AD700001010101010101010101010101010101C3 +:10AD800001010101010101010101010101010101B3 +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010183 +:10ADC0000101010101010101010101010101010173 +:10ADD0000101010101010101010101010101010163 +:10ADE0000101010101010101010101010101010153 +:10ADF0000101010101010101010101010101010143 +:10AE00000101010101010101010101010101010132 +:10AE10000101010101010101010101010101010122 +:10AE20000101010101010101010101010101010112 +:10AE30000101010101010101010101010101010102 +:10AE400001010101010101010101010101010101F2 +:10AE500001010101010101010101010101010101E2 +:10AE600001010101010101010101010101010101D2 +:10AE700001010101010101010101010101010101C2 +:10AE800001010101010101010101010101010101B2 +:10AE900001010101010101010101010101010101A2 +:10AEA0000101010101010101010101010101010192 +:10AEB0000101010101010101010101010101010182 +:10AEC0000101010101010101010101010101010172 +:10AED0000101010101010101010101010101010063 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000026A +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202020202020202020202020202EA +:10B6400002020202020202020202020202020202DA +:10B6500002020202020202020202020202020202CA +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020202020202020202020202028A +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C000020202020202020202020202020202025A +:10B6D000020202020202020202020202020202024A +:10B6E000020202020202020202020202020202023A +:10B6F000020202020202020202020202020202022A +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020202020202020202020202C5 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020255 +:10BBD0000202020202020202020202020202020245 +:10BBE0000202020202020202020202020202020235 +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020251 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202023D +:10C3E000020202020202020202020202020202022D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202023C +:10C4E000020202020202020202020202020202022C +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000020202020202020202020202020202022B +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202023A +:10C6E000020202020202020202020202020202022A +:10C6F000020202020202020202020202020202021A +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020202020202020202020202020249 +:10C7D0000202020202020202020202020202020239 +:10C7E0000202020202020202020202020202020229 +:10C7F0000202020202020202020202020202020219 +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020202020202020202020202020248 +:10C8D0000202020202020202020202020202020238 +:10C8E0000202020202020202020202020202020228 +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020257 +:10C9C0000202020202020202020202020202020247 +:10C9D0000202020202020202020202020202020237 +:10C9E0000202020202020202020202020202020227 +:10C9F0000202020202020202020202020202020217 +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020035 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000148 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010101010101010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010147 +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010101010101010101010146 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF0000101010101010101010101010101010115 +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010184 +:10DC90000101010101010101010101010101010174 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010101010101010101010114 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010101010101010101010173 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE90000101010101010101010101010101010172 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101010101010101010101DF +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101010101010101010101AF +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101010101010101DC +:10E4300001010101010101010101010101010101CC +:10E4400001010101010101010101010101010101BC +:10E4500001010101010101010101010101010101AC +:10E46000010101010101010101010101010101019C +:10E47000010101010101010101010101010101018C +:10E48000010101010101010101010101010101017C +:10E49000010101010101010101010101010101016C +:10E4A000010101010101010101010101010101015C +:10E4B000010101010101010101010101010101014C +:10E4C000010101010101010101010101010101013C +:10E4D000010101010101010101010101010101012C +:10E4E000010101010101010101010101010101011C +:10E4F000010101010101010101010101010101010C +:10E5000001010101010101010101010101010101FB +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010101DB +:10E5300001010101010101010101010101010101CB +:10E5400001010101010101010101010101010101BB +:10E5500001010101010101010101010101010101AB +:10E56000010101010101010101010101010101019B +:10E57000010101010101010101010101010101018B +:10E58000010101010101010101010101010101017B +:10E59000010101010101010101010101010101016B +:10E5A000010101010101010101010101010101015B +:10E5B000010101010101010101010101010101014B +:10E5C000010101010101010101010101010101013B +:10E5D000010101010101010101010101010101012B +:10E5E000010101010101010101010101010101011B +:10E5F000010101010101010101010101010101010B +:10E6000001010101010101010101010101010101FA +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101010101010101010101BA +:10E6500001010101010101010101010101010101AA +:10E66000010101010101010101010101010101019A +:10E67000010101010101010101010101010101018A +:10E68000010101010101010101010101010101017A +:10E69000010101010101010101010101010101016A +:10E6A000010101010101010101010101010101015A +:10E6B000010101010101010101010101010101014A +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E000010101010101010101010101010101011A +:10E6F000010101010101010101010101010101010A +:10E7000001010101010101010101010101010101F9 +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010101010101010101D9 +:10E7300001010101010101010101010101010101C9 +:10E7400001010101010101010101010101010101B9 +:10E7500001010101010101010101010101010101A9 +:10E760000101010101010101010101010101010199 +:10E770000101010101010101010101010101010189 +:10E780000101010101010101010101010101010179 +:10E790000101010101010101010101010101010169 +:10E7A0000101010101010101010101010101010159 +:10E7B0000101010101010101010101010101010149 +:10E7C0000101010101010101010101010101010139 +:10E7D0000101010101010101010101010101010129 +:10E7E0000101010101010101010101010101010119 +:10E7F0000101010101010101010101010101010109 +:10E8000001010101010101010101010101010101F8 +:10E8100001010101010101010101010101010101E8 +:10E8200001010101010101010101010101010101D8 +:10E8300001010101010101010101010101010101C8 +:10E8400001010101010101010101010101010101B8 +:10E8500001010101010101010101010101010101A8 +:10E860000101010101010101010101010101010198 +:10E870000101010101010101010101010101010188 +:10E880000101010101010101010101010101010178 +:10E890000101010101010101010101010101010168 +:10E8A0000101010101010101010101010101010158 +:10E8B0000101010101010101010101010101010148 +:10E8C0000101010101010101010101010101010138 +:10E8D0000101010101010101010101010101010128 +:10E8E0000101010101010101010101010101010118 +:10E8F0000101010101010101010101010101010108 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010101010101010101D7 +:10E9300001010101010101010101010101010101C7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010101010101010101010177 +:10E990000101010101010101010101010101010167 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010101010101010101D6 +:10EA300001010101010101010101010101010101C6 +:10EA400001010101010101010101010101010101B6 +:10EA500001010101010101010101010101010101A6 +:10EA60000101010101010101010101010101010196 +:10EA70000101010101010101010101010101010186 +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010101010101010101010166 +:10EAA0000101010101010101010101010101010156 +:10EAB0000101010101010101010101010101010146 +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101010101010101010101F5 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101010101010101010101D5 +:10EB300001010101010101010101010101010101C5 +:10EB400001010101010101010101010101010101B5 +:10EB500001010101010101010101010101010101A5 +:10EB60000101010101010101010101010101010195 +:10EB70000101010101010101010101010101010185 +:10EB80000101010101010101010101010101010175 +:10EB90000101010101010101010101010101010165 +:10EBA0000101010101010101010101010101010155 +:10EBB0000101010101010101010101010101010145 +:10EBC0000101010101010101010101010101010135 +:10EBD0000101010101010101010101010101010125 +:10EBE0000101010101010101010101010101010115 +:10EBF0000101010101010101010101010101010105 +:10EC000001010101010101010101010101010101F4 +:10EC100001010101010101010101010101010101E4 +:10EC200001010101010101010101010101010101D4 +:10EC300001010101010101010101010101010101C4 +:10EC400001010101010101010101010101010101B4 +:10EC500001010101010101010101010101010101A4 +:10EC60000101010101010101010101010101010194 +:10EC70000101010101010101010101010101010184 +:10EC80000101010101010101010101010101010174 +:10EC90000101010101010101010101010101010164 +:10ECA0000101010101010101010101010101010154 +:10ECB0000101010101010101010101010101010144 +:10ECC0000101010101010101010101010101010134 +:10ECD0000101010101010101010101010101010124 +:10ECE0000101010101010101010101010101010114 +:10ECF0000101010101010101010101010101010104 +:10ED000001010101010101010101010101010101F3 +:10ED100001010101010101010101010101010101E3 +:10ED200001010101010101010101010101010101D3 +:10ED300001010101010101010101010101010101C3 +:10ED400001010101010101010101010101010101B3 +:10ED500001010101010101010101010101010101A3 +:10ED60000101010101010101010101010101010193 +:10ED70000101010101010101010101010101010183 +:10ED80000101010101010101010101010101010173 +:10ED90000101010101010101010101010101010163 +:10EDA0000101010101010101010101010101010153 +:10EDB0000101010101010101010101010101010143 +:10EDC0000101010101010101010101010101010133 +:10EDD0000101010101010101010101010101010123 +:10EDE0000101010101010101010101010101010113 +:10EDF0000101010101010101010101010101010103 +:10EE000001010101010101010101010101010101F2 +:10EE100001010101010101010101010101010101E2 +:10EE200001010101010101010101010101010101D2 +:10EE300001010101010101010101010101010101C2 +:10EE400001010101010101010101010101010101B2 +:10EE500001010101010101010101010101010101A2 +:10EE60000101010101010101010101010101010192 +:10EE70000101010101010101010101010101010182 +:10EE80000101010101010101010101010101010172 +:10EE90000101010101010101010101010101010162 +:10EEA0000101010101010101010101010101010152 +:10EEB0000101010101010101010101010101010142 +:10EEC0000101010101010101010101010101010132 +:10EED0000101010101010101010101010101010122 +:10EEE0000101010101010101010101010101010112 +:10EEF0000101010101010101010101010101010102 +:10EF000001010101010101010101010101010101F1 +:10EF100001010101010101010101010101010101E1 +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101010101010101010101C1 +:10EF400001010101010101010101010101010101B1 +:10EF500001010101010101010101010101010101A1 +:10EF60000101010101010101010101010101010191 +:10EF70000101010101010101010101010101010181 +:10EF80000101010101010101010101010101010171 +:10EF90000101010101010101010101010101010161 +:10EFA0000101010101010101010101010101010151 +:10EFB0000101010101010101010101010101010141 +:10EFC0000101010101010101010101010101010131 +:10EFD0000101010101010101010101010101010121 +:10EFE0000101010101010101010101010101010111 +:10EFF0000101010101010101010101010101010101 +:10F0000001010101010101010101010101010101F0 +:10F0100001010101010101010101010101010101E0 +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101010101010101010101C0 +:10F0400001010101010101010101010101010101B0 +:10F0500001010101010101010101010101010101A0 +:10F060000101010101010101010101010101010190 +:10F070000101010101010101010101010101010180 +:10F080000101010101010101010101010101010170 +:10F090000101010101010101010101010101010160 +:10F0A0000101010101010101010101010101010150 +:10F0B0000101010101010101010101010101010140 +:10F0C0000101010101010101010101010101010130 +:10F0D0000101010101010101010101010101010021 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D0000000000000000000000000000000000228 +:10F6E00002020202020202020202020202020202FA +:10F6F00002020202020202020202020202020202EA +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020202020202020202020202C9 +:10F7200002020202020202020202020202020202B9 +:10F7300002020202020202020202020202020202A9 +:10F740000202020202020202020202020202020299 +:10F750000202020202020202020202020202020289 +:10F760000202020202020202020202020202020279 +:10F770000202020202020202020202020202020269 +:10F780000202020202020202020202020202020259 +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020202020202020202020202B8 +:10F8300002020202020202020202020202020202A8 +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202020202020202020202A7 +:10F940000202020202020202020202020202020297 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020277 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020202020202020202020243 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202020202020202020223 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202020202020242 +:10FEA0000202020202020202020202020202020232 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202020202020241 +:10FFA0000202020202020202020202020202020231 +:10FFB0000202020202020202020202020202020221 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:020000021000EC +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C000020202020202020202020202020202020F +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000020202020202020202020202020202023E +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C000020202020202020202020202020202020E +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202020202020202020D +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020202020202020202023C +:1004A000020202020202020202020202020202022C +:1004B000020202020202020202020202020202021C +:1004C000020202020202020202020202020202020C +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202024B +:10059000020202020202020202020202020202023B +:1005A000020202020202020202020202020202022B +:1005B000020202020202020202020202020202021B +:1005C000020202020202020202020202020202020B +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202024A +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020202020202020202021A +:1006C000020202020202020202020202020202020A +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:100770000202020202020202020202020202020259 +:100780000202020202020202020202020202020249 +:100790000202020202020202020202020202020239 +:1007A0000202020202020202020202020202020229 +:1007B0000202020202020202020202020202020219 +:1007C0000202020202020202020202020202020209 +:1007D00002020202020202020202020202020202F9 +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020248 +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B0000202020202020202020202020202020218 +:1008C0000202020202020202020202020202020208 +:1008D00002020202020202020202020202020202F8 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020247 +:100990000202020202020202020202020202020237 +:1009A0000202020202020202020202020202020227 +:1009B0000202020202020202020202020202020217 +:1009C0000202020202020202020202020202020207 +:1009D00002020202020202020202020202020202F7 +:1009E00002020202020202020202020202020202E7 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020202020202020202020226 +:100AB0000202020202020202020202020202020216 +:100AC0000202020202020202020202020202020206 +:100AD00002020202020202020202020202020202F6 +:100AE00002020202020202020202020202020202E6 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202020202020202020205 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020200F3 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000000000000000000001C +:1014D000000000000000000000000000000000000C +:1014E00000000000000000000000000000000000FC +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D0000000000000000000000000000000006F9B +:1016E00000000000000000010101010101010101F1 +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010101010101010101010157 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101014B +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:10267000010101010101010101010101010101014A +:10268000010101010101010101010101010101013A +:10269000010101010101010101010101010101012A +:1026A000010101010101010101010101010101011A +:1026B000010101010101010101010101010101010A +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101010101010101010159 +:102770000101010101010101010101010101010149 +:102780000101010101010101010101010101010139 +:102790000101010101010101010101010101010129 +:1027A0000101010101010101010101010101010119 +:1027B0000101010101010101010101010101010109 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010147 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010101010127 +:1029A0000101010101010101010101010101010117 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010146 +:102A80000101010101010101010101010101010136 +:102A90000101010101010101010101010101010126 +:102AA0000101010101010101010101010101010116 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010165 +:102B60000101010101010101010101010101010155 +:102B70000101010101010101010101010101010145 +:102B80000101010101010101010101010101010135 +:102B90000101010101010101010101010101010125 +:102BA0000101010101010101010101010101010115 +:102BB0000101010101010101010101010101010105 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101010101010101010101E5 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000101010101010101010101010101010164 +:102C60000101010101010101010101010101010154 +:102C70000101010101010101010101010101010144 +:102C80000101010101010101010101010101010134 +:102C90000101010101010101010101010101010124 +:102CA0000101010101010101010101010101010114 +:102CB0000101010101010101010101010101010104 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101000000000000000000DD +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000000E1 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000020202020202020202CE +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202029E +:10430000020202020202020202020202020202028D +:10431000020202020202020202020202020202027D +:10432000020202020202020202020202020202026D +:10433000020202020202020202020202020202025D +:10434000020202020202020202020202020202024D +:10435000020202020202020202020202020202023D +:10436000020202020202020202020202020202022D +:10437000020202020202020202020202020202021D +:10438000020202020202020202020202020202020D +:1043900002020202020202020202020202020202FD +:1043A00002020202020202020202020202020202ED +:1043B00002020202020202020202020202020202DD +:1043C00002020202020202020202020202020202CD +:1043D00002020202020202020202020202020202BD +:1043E00002020202020202020202020202020202AD +:1043F000020202020202020202020202020202029D +:10440000020202020202020202020202020202028C +:10441000020202020202020202020202020202027C +:10442000020202020202020202020202020202026C +:10443000020202020202020202020202020202025C +:10444000020202020202020202020202020202024C +:10445000020202020202020202020202020202023C +:10446000020202020202020202020202020202022C +:10447000020202020202020202020202020202021C +:10448000020202020202020202020202020202020C +:1044900002020202020202020202020202020202FC +:1044A00002020202020202020202020202020202EC +:1044B00002020202020202020202020202020202DC +:1044C00002020202020202020202020202020202CC +:1044D00002020202020202020202020202020202BC +:1044E00002020202020202020202020202020202AC +:1044F000020202020202020202020202020202029C +:10450000020202020202020202020202020202028B +:10451000020202020202020202020202020202027B +:10452000020202020202020202020202020202026B +:10453000020202020202020202020202020202025B +:10454000020202020202020202020202020202024B +:10455000020202020202020202020202020202023B +:10456000020202020202020202020202020202022B +:10457000020202020202020202020202020202021B +:10458000020202020202020202020202020202020B +:1045900002020202020202020202020202020202FB +:1045A00002020202020202020202020202020202EB +:1045B00002020202020202020202020202020202DB +:1045C00002020202020202020202020202020202CB +:1045D00002020202020202020202020202020202BB +:1045E00002020202020202020202020202020202AB +:1045F000020202020202020202020202020202029B +:10460000020202020202020202020202020202028A +:10461000020202020202020202020202020202027A +:10462000020202020202020202020202020202026A +:10463000020202020202020202020202020202025A +:10464000020202020202020202020202020202024A +:10465000020202020202020202020202020202023A +:10466000020202020202020202020202020202022A +:10467000020202020202020202020202020202021A +:10468000020202020202020202020202020202020A +:1046900002020202020202020202020202020202FA +:1046A00002020202020202020202020202020202EA +:1046B00002020202020202020202020202020202DA +:1046C00002020202020202020202020202020202CA +:1046D00002020202020202020202020202020202BA +:1046E00002020202020202000000000000000000BC +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000010101010101010101B8 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101016D +:10533000010101010101010101010101010101015D +:10534000010101010101010101010101010101014D +:10535000010101010101010101010101010101013D +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101010D +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010101010101BD +:1053E00001010101010101010101010101010101AD +:1053F000010101010101010101010101010101019D +:10540000010101010101010101010101010101018C +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101016C +:10543000010101010101010101010101010101015C +:10544000010101010101010101010101010101014C +:10545000010101010101010101010101010101013C +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101010101010101010101BC +:1054E00001010101010101010101010101010101AC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:10553000010101010101010101010101010101015B +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000101010101010101010101010101010169 +:105730000101010101010101010101010101010159 +:105740000101010101010101010101010101010149 +:105750000101010101010101010101010101010139 +:105760000101010101010101010101010101010129 +:105770000101010101010101010101010101010119 +:105780000101010101010101010101010101010109 +:1057900001010101010101010101010101010101F9 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101010101010101010101B9 +:1057E00001010101010101010101010101010101A9 +:1057F0000101010101010101010101010101010199 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010187 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000101010101010101010101010101010186 +:105A10000101010101010101010101010101010176 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010101010101010101010116 +:105A80000101010101010101010101010101010106 +:105A900001010101010101010101010101010101F6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00001010101010101010101010101010101C6 +:105AD00001010101010101010101010101010101B6 +:105AE00001010101010101010101010101010101A6 +:105AF0000101010101010101010101010101010196 +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010175 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101010101010101010145 +:105B50000101010101010101010101010101010135 +:105B60000101010101010101010101010101010125 +:105B70000101010101010101010101010101010115 +:105B80000101010101010101010101010101010105 +:105B900001010101010101010101010101010101F5 +:105BA00001010101010101010101010101010101E5 +:105BB00001010101010101010101010101010101D5 +:105BC00001010101010101010101010101010101C5 +:105BD00001010101010101010101010101010101B5 +:105BE00001010101010101010101010101010101A5 +:105BF0000101010101010101010101010101010195 +:105C00000101010101010101010101010101010184 +:105C10000101010101010101010101010101010174 +:105C20000101010101010101010101010101010164 +:105C30000101010101010101010101010101010154 +:105C40000101010101010101010101010101010144 +:105C50000101010101010101010101010101010134 +:105C60000101010101010101010101010101010124 +:105C70000101010101010101010101010101010114 +:105C80000101010101010101010101010101010104 +:105C900001010101010101010101010101010101F4 +:105CA00001010101010101010101010101010101E4 +:105CB00001010101010101010101010101010101D4 +:105CC00001010101010101010101010101010101C4 +:105CD00001010101010101010101010101010101B4 +:105CE00001010101010101010101010101010101A4 +:105CF0000101010101010101010101010101010194 +:105D00000101010101010101010101010101010183 +:105D10000101010101010101010101010101010173 +:105D20000101010101010101010101010101010163 +:105D30000101010101010101010101010101010153 +:105D40000101010101010101010101010101010143 +:105D50000101010101010101010101010101010133 +:105D60000101010101010101010101010101010123 +:105D70000101010101010101010101010101010113 +:105D80000101010101010101010101010101010103 +:105D900001010101010101010101010101010101F3 +:105DA00001010101010101010101010101010101E3 +:105DB00001010101010101010101010101010101D3 +:105DC00001010101010101010101010101010101C3 +:105DD00001010101010101010101010101010101B3 +:105DE00001010101010101010101010101010101A3 +:105DF0000101010101010101010101010101010193 +:105E00000101010101010101010101010101010182 +:105E10000101010101010101010101010101010172 +:105E20000101010101010101010101010101010162 +:105E30000101010101010101010101010101010152 +:105E40000101010101010101010101010101010142 +:105E50000101010101010101010101010101010132 +:105E60000101010101010101010101010101010122 +:105E70000101010101010101010101010101010112 +:105E80000101010101010101010101010101010102 +:105E900001010101010101010101010101010101F2 +:105EA00001010101010101010101010101010101E2 +:105EB00001010101010101010101010101010101D2 +:105EC00001010101010101010101010101010101C2 +:105ED00001010101010101010101010101010101B2 +:105EE00001010101010101010101010101010101A2 +:105EF0000101010101010101010101010101010192 +:105F00000101010101010101010101010101010181 +:105F10000101010101010101010101010101010171 +:105F20000101010101010101010101010101010161 +:105F30000101010101010101010101010101010151 +:105F40000101010101010101010101010101010141 +:105F50000101010101010101010101010101010131 +:105F60000101010101010101010101010101010121 +:105F70000101010101010101010101010101010111 +:105F80000101010101010101010101010101010101 +:105F900001010101010101010101010101010101F1 +:105FA00001010101010101010101010101010101E1 +:105FB00001010101010101010101010101010101D1 +:105FC00001010101010101010101010101010101C1 +:105FD00001010101010101010101010101010101B1 +:105FE00001010101010101010101010101010101A1 +:105FF0000101010101010101010101010101010191 +:106000000101010101010101010101010101010180 +:106010000101010101010101010101010101010170 +:106020000101010101010101010101010101010160 +:106030000101010101010101010101010101010150 +:106040000101010101010101010101010101010140 +:106050000101010101010101010101010101010130 +:106060000101010101010101010101010101010120 +:106070000101010101010101010101010101010110 +:106080000101010101010101010101010101010100 +:1060900001010101010101010101010101010101F0 +:1060A00001010101010101010101010101010101E0 +:1060B00001010101010101010101010101010101D0 +:1060C00001010101010101010101010101010101C0 +:1060D00001010101010101010101010101010101B0 +:1060E00001010101010101010101010101010101A0 +:1060F0000101010101010101010101010101010190 +:10610000010101010101010101010101010101017F +:10611000010101010101010101010101010101016F +:10612000010101010101010101010101010101015F +:10613000010101010101010101010101010101014F +:10614000010101010101010101010101010101013F +:10615000010101010101010101010101010101012F +:10616000010101010101010101010101010101011F +:10617000010101010101010101010101010101010F +:1061800001010101010101010101010101010101FF +:1061900001010101010101010101010101010101EF +:1061A00001010101010101010101010101010101DF +:1061B00001010101010101010101010101010101CF +:1061C00001010101010101010101010101010101BF +:1061D00001010101010101010101010101010101AF +:1061E000010101010101010101010101010101019F +:1061F000010101010101010101010101010101018F +:10620000010101010101010101010101010101017E +:10621000010101010101010101010101010101016E +:10622000010101010101010101010101010101015E +:10623000010101010101010101010101010101014E +:10624000010101010101010101010101010101013E +:10625000010101010101010101010101010101012E +:10626000010101010101010101010101010101011E +:10627000010101010101010101010101010101010E +:1062800001010101010101010101010101010101FE +:1062900001010101010101010101010101010101EE +:1062A00001010101010101010101010101010101DE +:1062B00001010101010101010101010101010101CE +:1062C00001010101010101010101010101010101BE +:1062D00001010101010101010101010101010101AE +:1062E000010101010101010101010101010101019E +:1062F000010101010101010101010101010101018E +:10630000010101010101010101010101010101017D +:10631000010101010101010101010101010101016D +:10632000010101010101010101010101010101015D +:10633000010101010101010101010101010101014D +:10634000010101010101010101010101010101013D +:10635000010101010101010101010101010101012D +:10636000010101010101010101010101010101011D +:10637000010101010101010101010101010101010D +:1063800001010101010101010101010101010101FD +:1063900001010101010101010101010101010101ED +:1063A00001010101010101010101010101010101DD +:1063B00001010101010101010101010101010101CD +:1063C00001010101010101010101010101010101BD +:1063D00001010101010101010101010101010101AD +:1063E000010101010101010101010101010101019D +:1063F000010101010101010101010101010101018D +:10640000010101010101010101010101010101017C +:10641000010101010101010101010101010101016C +:10642000010101010101010101010101010101015C +:10643000010101010101010101010101010101014C +:10644000010101010101010101010101010101013C +:10645000010101010101010101010101010101012C +:10646000010101010101010101010101010101011C +:10647000010101010101010101010101010101010C +:1064800001010101010101010101010101010101FC +:1064900001010101010101010101010101010101EC +:1064A00001010101010101010101010101010101DC +:1064B00001010101010101010101010101010101CC +:1064C00001010101010101010101010101010101BC +:1064D00001010101010101010101010101010101AC +:1064E000010101010101010101010101010101019C +:1064F000010101010101010101010101010101018C +:10650000010101010101010101010101010101017B +:10651000010101010101010101010101010101016B +:10652000010101010101010101010101010101015B +:10653000010101010101010101010101010101014B +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010101010101010101FB +:1065900001010101010101010101010101010101EB +:1065A00001010101010101010101010101010101DB +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E00001010101010101000000000000000000A4 +:1065F000000000000000000000000000000000009B +:10660000000000000000000000000000000000008A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000000000000000000AA +:1066F000000000000000000000000000000000009A +:106700000000000000000000000000000000000089 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000099 +:106800000000000000000000000000000000000088 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000038 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000000B8 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000098 +:106900000000000000000000000000000000000087 +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000000000000000000B7 +:1069E0000000000000000002020202020202020295 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202020286 +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020202020285 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020202B4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202020202020202020284 +:107CE0000202020202020202020202020202020274 +:107CF0000202020202020202020202020202020264 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020202020202020283 +:107DE0000202020202020202020202020202020273 +:107DF0000202020202020202020202020202020263 +:107E00000202020202020202020202020202020252 +:107E10000202020202020202020202020202020242 +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020202C2 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020202020202020202020282 +:107EE0000202020202020202020202020202020272 +:107EF0000202020202020202020202020202020262 +:107F00000202020202020202020202020202020251 +:107F10000202020202020202020202020202020241 +:107F20000202020202020202020202020202020231 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020202C1 +:107FA00002020202020202020202020202020202B1 +:107FB00002020202020202020202020202020202A1 +:107FC0000202020202020202020202020202020291 +:107FD0000202020202020202020202020202020281 +:107FE0000202020202020200000000000000000083 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000006D00000000000000011D +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010101010101010101010107 +:1089600001010101010101010101010101010101F7 +:1089700001010101010101010101010101010101E7 +:1089800001010101010101010101010101010101D7 +:1089900001010101010101010101010101010101C7 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010114 +:108C50000101010101010101010101010101010104 +:108C600001010101010101010101010101010101F4 +:108C700001010101010101010101010101010101E4 +:108C800001010101010101010101010101010101D4 +:108C900001010101010101010101010101010101C4 +:108CA00001010101010101010101010101010101B4 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010066 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE000000000000000000000000000000000026F +:109FF0000202020202020202020202020202020241 +:10A000000202020202020202020202020202020230 +:10A010000202020202020202020202020202020220 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020202020202020202020202020202D0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020202A0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020280 +:10A0C0000202020202020202020202020202020270 +:10A0D0000202020202020202020202020202020260 +:10A0E0000202020202020202020202020202020250 +:10A0F0000202020202020202020202020202020240 +:10A10000020202020202020202020202020202022F +:10A11000020202020202020202020202020202021F +:10A12000020202020202020202020202020202020F +:10A1300002020202020202020202020202020202FF +:10A1400002020202020202020202020202020202EF +:10A1500002020202020202020202020202020202DF +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A19000020202020202020202020202020202029F +:10A1A000020202020202020202020202020202028F +:10A1B000020202020202020202020202020202027F +:10A1C000020202020202020202020202020202026F +:10A1D000020202020202020202020202020202025F +:10A1E000020202020202020202020202020202024F +:10A1F000020202020202020202020202020202023F +:10A20000020202020202020202020202020202022E +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202020E +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202027E +:10A2C000020202020202020202020202020202026E +:10A2D000020202020202020202020202020202025E +:10A2E000020202020202020202020202020202024E +:10A2F000020202020202020202020202020202023E +:10A30000020202020202020202020202020202022D +:10A31000020202020202020202020202020202021D +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202024D +:10A3F000020202020202020202020202020202023D +:10A40000020202020202020202020202020202022C +:10A41000020202020202020202020202020202021C +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202027C +:10A4C000020202020202020202020202020202026C +:10A4D000020202020202020202020202020202025C +:10A4E000020202020202020202020202020202024C +:10A4F000020202020202020202020202020202023C +:10A50000020202020202020202020202020202022B +:10A51000020202020202020202020202020202021B +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E000020202020202020202020202020202024B +:10A5F000020202020202020202020202020202023B +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E000020202020202020202020202020202024A +:10A6F000020202020202020202020202020202023A +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000202020202020202020202020202020239 +:10A800000202020202020202020202020202020228 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020202A8 +:10A890000202020202020202020202020202020298 +:10A8A0000202020202020202020202020202020288 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202003D +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000152 +:10BDF0000101010101010101010101010101010133 +:10BE00000101010101010101010101010101010122 +:10BE10000101010101010101010101010101010112 +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101010101010101010101B2 +:10BE800001010101010101010101010101010101A2 +:10BE90000101010101010101010101010101010192 +:10BEA0000101010101010101010101010101010182 +:10BEB0000101010101010101010101010101010172 +:10BEC0000101010101010101010101010101010162 +:10BED0000101010101010101010101010101010152 +:10BEE0000101010101010101010101010101010142 +:10BEF0000101010101010101010101010101010132 +:10BF00000101010101010101010101010101010121 +:10BF10000101010101010101010101010101010111 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101010101010101010101B1 +:10BF800001010101010101010101010101010101A1 +:10BF90000101010101010101010101010101010191 +:10BFA0000101010101010101010101010101010181 +:10BFB0000101010101010101010101010101010171 +:10BFC0000101010101010101010101010101010161 +:10BFD0000101010101010101010101010101010151 +:10BFE0000101010101010101010101010101010141 +:10BFF0000101010101010101010101010101010131 +:10C000000101010101010101010101010101010120 +:10C010000101010101010101010101010101010110 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101010101010101010101B0 +:10C0800001010101010101010101010101010101A0 +:10C090000101010101010101010101010101010190 +:10C0A0000101010101010101010101010101010180 +:10C0B0000101010101010101010101010101010170 +:10C0C0000101010101010101010101010101010160 +:10C0D0000101010101010101010101010101010150 +:10C0E0000101010101010101010101010101010140 +:10C0F0000101010101010101010101010101010130 +:10C10000010101010101010101010101010101011F +:10C11000010101010101010101010101010101010F +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010101010101DF +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A000010101010101010101010101010101017F +:10C1B000010101010101010101010101010101016F +:10C1C000010101010101010101010101010101015F +:10C1D000010101010101010101010101010101014F +:10C1E000010101010101010101010101010101013F +:10C1F000010101010101010101010101010101012F +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101010101010101010101CE +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A000010101010101010101010101010101017E +:10C2B000010101010101010101010101010101016E +:10C2C000010101010101010101010101010101015E +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010101010101ED +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101010101010101010101CD +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010101010101010101017D +:10C3B000010101010101010101010101010101016D +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101010C +:10C4200001010101010101010101010101010101FC +:10C4300001010101010101010101010101010101EC +:10C4400001010101010101010101010101010101DC +:10C4500001010101010101010101010101010101CC +:10C4600001010101010101010101010101010101BC +:10C4700001010101010101010101010101010101AC +:10C48000010101010101010101010101010101019C +:10C49000010101010101010101010101010101018C +:10C4A000010101010101010101010101010101017C +:10C4B000010101010101010101010101010101016C +:10C4C000010101010101010101010101010101015C +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010101010101010101013C +:10C4F000010101010101010101010101010101012C +:10C50000010101010101010101010101010101011B +:10C51000010101010101010101010101010101010B +:10C5200001010101010101010101010101010101FB +:10C5300001010101010101010101010101010101EB +:10C5400001010101010101010101010101010101DB +:10C5500001010101010101010101010101010101CB +:10C5600001010101010101010101010101010101BB +:10C5700001010101010101010101010101010101AB +:10C58000010101010101010101010101010101019B +:10C59000010101010101010101010101010101018B +:10C5A000010101010101010101010101010101017B +:10C5B000010101010101010101010101010101016B +:10C5C000010101010101010101010101010101015B +:10C5D000010101010101010101010101010101014B +:10C5E000010101010101010101010101010101013B +:10C5F000010101010101010101010101010101012B +:10C60000010101010101010101010101010101011A +:10C61000010101010101010101010101010101010A +:10C6200001010101010101010101010101010101FA +:10C6300001010101010101010101010101010101EA +:10C6400001010101010101010101010101010101DA +:10C6500001010101010101010101010101010101CA +:10C6600001010101010101010101010101010101BA +:10C6700001010101010101010101010101010101AA +:10C68000010101010101010101010101010101019A +:10C69000010101010101010101010101010101018A +:10C6A000010101010101010101010101010101017A +:10C6B000010101010101010101010101010101016A +:10C6C000010101010101010101010101010101015A +:10C6D000010101010101010101010101010101014A +:10C6E000010101010101010101010101010101013A +:10C6F000010101010101010101010101010101012A +:10C700000101010101010101010101010101010119 +:10C710000101010101010101010101010101010109 +:10C7200001010101010101010101010101010101F9 +:10C7300001010101010101010101010101010101E9 +:10C7400001010101010101010101010101010101D9 +:10C7500001010101010101010101010101010101C9 +:10C7600001010101010101010101010101010101B9 +:10C7700001010101010101010101010101010101A9 +:10C780000101010101010101010101010101010199 +:10C790000101010101010101010101010101010189 +:10C7A0000101010101010101010101010101010179 +:10C7B0000101010101010101010101010101010169 +:10C7C0000101010101010101010101010101010159 +:10C7D0000101010101010101010101010101010149 +:10C7E0000101010101010101010101010101010139 +:10C7F0000101010101010101010101010101010129 +:10C800000101010101010101010101010101010118 +:10C810000101010101010101010101010101010108 +:10C8200001010101010101010101010101010101F8 +:10C8300001010101010101010101010101010101E8 +:10C8400001010101010101010101010101010101D8 +:10C8500001010101010101010101010101010101C8 +:10C8600001010101010101010101010101010101B8 +:10C8700001010101010101010101010101010101A8 +:10C880000101010101010101010101010101010198 +:10C890000101010101010101010101010101010188 +:10C8A0000101010101010101010101010101010178 +:10C8B0000101010101010101010101010101010168 +:10C8C0000101010101010101010101010101010158 +:10C8D0000101010101010101010101010101010148 +:10C8E0000101010101010101010101010101010138 +:10C8F0000101010101010101010101010101010128 +:10C900000101010101010101010101010101010117 +:10C910000101010101010101010101010101010107 +:10C9200001010101010101010101010101010101F7 +:10C9300001010101010101010101010101010101E7 +:10C9400001010101010101010101010101010101D7 +:10C9500001010101010101010101010101010101C7 +:10C9600001010101010101010101010101010101B7 +:10C9700001010101010101010101010101010101A7 +:10C980000101010101010101010101010101010197 +:10C990000101010101010101010101010101010187 +:10C9A0000101010101010101010101010101010177 +:10C9B0000101010101010101010101010101010167 +:10C9C0000101010101010101010101010101010157 +:10C9D0000101010101010101010101010101010147 +:10C9E0000101010101010101010101010101010137 +:10C9F0000101010101010101010101010101010127 +:10CA00000101010101010101010101010101010116 +:10CA10000101010101010101010101010101010106 +:10CA200001010101010101010101010101010101F6 +:10CA300001010101010101010101010101010101E6 +:10CA400001010101010101010101010101010101D6 +:10CA500001010101010101010101010101010101C6 +:10CA600001010101010101010101010101010101B6 +:10CA700001010101010101010101010101010101A6 +:10CA80000101010101010101010101010101010196 +:10CA90000101010101010101010101010101010186 +:10CAA0000101010101010101010101010101010176 +:10CAB0000101010101010101010101010101010166 +:10CAC0000101010101010101010101010101010156 +:10CAD0000101010101010101010101010101010146 +:10CAE0000101010101010101010101010101010136 +:10CAF0000101010101010101010101010101010126 +:10CB00000101010101010101010101010101010115 +:10CB10000101010101010101010101010101010105 +:10CB200001010101010101010101010101010101F5 +:10CB300001010101010101010101010101010101E5 +:10CB400001010101010101010101010101010101D5 +:10CB500001010101010101010101010101010101C5 +:10CB600001010101010101010101010101010101B5 +:10CB700001010101010101010101010101010101A5 +:10CB80000101010101010101010101010101010195 +:10CB90000101010101010101010101010101010185 +:10CBA0000101010101010101010101010101010175 +:10CBB0000101010101010101010101010101010165 +:10CBC0000101010101010101010101010101010155 +:10CBD0000101010101010101010101010101010145 +:10CBE0000101010101010101010101010101010135 +:10CBF0000101010101010101010101010101010125 +:10CC00000101010101010101010101010101010114 +:10CC10000101010101010101010101010101010104 +:10CC200001010101010101010101010101010101F4 +:10CC300001010101010101010101010101010101E4 +:10CC400001010101010101010101010101010101D4 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010101A4 +:10CC80000101010101010101010101010101010194 +:10CC90000101010101010101010101010101010184 +:10CCA0000101010101010101010101010101010174 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010101A3 +:10CD80000101010101010101010101010101010193 +:10CD90000101010101010101010101010101010183 +:10CDA0000101010101010101010101010101010173 +:10CDB0000101010101010101010101010101010163 +:10CDC0000101010101010101010101010101010153 +:10CDD0000101010101010101010101010101010143 +:10CDE0000101010101010101010101010101010133 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010101A2 +:10CE80000101010101010101010101010101010192 +:10CE90000101010101010101010101010101010182 +:10CEA0000101010101010101010101010101010172 +:10CEB0000101010101010101010101010101010162 +:10CEC0000101010101010101010101010101010152 +:10CED0000101010101010101010101010101010142 +:10CEE0000101010101010101010101010101010132 +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400001010101010101010101010101010101D1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700001010101010101010101010101010101A1 +:10CF80000101010101010101010101010101010191 +:10CF90000101010101010101010101010101010181 +:10CFA0000101010101010101010101010101010171 +:10CFB0000101010101010101010101010101010161 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010141 +:10CFE0000101010101010101010101010101010131 +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010101010101010101010110 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010101010101010101010101010101C0 +:10D0600001010101010101010101010101010101B0 +:10D0700001010101010101010101010101010101A0 +:10D080000101010101010101010101010101010190 +:10D090000101010101010101010101010101010180 +:10D0A0000101010101010101010101010101010170 +:10D0B0000101010101010101010101010101010160 +:10D0C0000101010101010101010101010101010150 +:10D0D0000101010101010101010101010101010140 +:10D0E0000101010101010101010101010101010130 +:10D0F0000101010101010101010101010101010120 +:10D10000010101010101010101010101010101010F +:10D1100001010101010101010101010101010101FF +:10D1200001010101010101010101010101010101EF +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010101010101AE +:10D27000010101010101010101010101010101019E +:10D28000010101010101010101010101010101018E +:10D29000010101010101010101010101010101017E +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101002E +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000237 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C0000202020202020202020202020202020238 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202020202020237 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202020202020236 +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020202020202020202020216 +:10DAF0000202020202020202020202020202020206 +:10DB000002020202020202020202020202020202F5 +:10DB100002020202020202020202020202020202E5 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB0000202020202020202020202020202020245 +:10DBC0000202020202020202020202020202020235 +:10DBD0000202020202020202020202020202020225 +:10DBE0000202020202020202020202020202020215 +:10DBF0000202020202020202020202020202020205 +:10DC000002020202020202020202020202020202F4 +:10DC100002020202020202020202020202020202E4 +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB0000202020202020202020202020202020244 +:10DCC0000202020202020202020202020202020234 +:10DCD0000202020202020202020202020202020224 +:10DCE0000202020202020202020202020202020214 +:10DCF0000202020202020202020202020202020204 +:10DD000002020202020202020202020202020202F3 +:10DD100002020202020202020202020202020202E3 +:10DD200002020202020202020202020202020202D3 +:10DD300002020202020202020202020202020202C3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB0000202020202020202020202020202020243 +:10DDC0000202020202020202020202020202020233 +:10DDD0000202020202020202020202020202020223 +:10DDE0000202020202020202020202020202020213 +:10DDF0000202020202020202020202020202020203 +:10DE000002020202020202020202020202020202F2 +:10DE100002020202020202020202020202020202E2 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA0000202020202020202020202020202020252 +:10DEB0000202020202020202020202020202020242 +:10DEC0000202020202020202020202020202020232 +:10DED0000202020202020202020202020202020222 +:10DEE0000202020202020202020202020202020212 +:10DEF0000202020202020202020202020202020202 +:10DF000002020202020202020202020202020202F1 +:10DF100002020202020202020202020202020202E1 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202020202020231 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020202020202020202020211 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020202020202020202020250 +:10E0B0000202020202020202020202020202020240 +:10E0C0000202020202020202020202020202020230 +:10E0D0000202020202020202020202020202020220 +:10E0E0000202020202020202020202020202020210 +:10E0F0000202020202020202020202020202020200 +:10E1000002020202020202020202020202020202EF +:10E1100002020202020202020202020202020202DF +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A000020202020202020202020202020202024F +:10E1B000020202020202020202020202020202023F +:10E1C000020202020202020202020202020202022F +:10E1D000020202020202020202020202020202021F +:10E1E000020202020202020202020202020202020F +:10E1F00002020202020202020202020202020202FF +:10E2000002020202020202020202020202020202EE +:10E2100002020202020202020202020202020202DE +:10E2200002020202020202020202020202020202CE +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E28000020202020202020202020202020202026E +:10E29000020202020202020202020202020202025E +:10E2A000020202020202020202020202020202024E +:10E2B000020202020202020202020202020202023E +:10E2C000020202020202020202020202020202022E +:10E2D000020202020202020202020202020202021E +:10E2E000020202020202020202020202020202020E +:10E2F00002020202020202020202020202020202FE +:10E3000002020202020202020202020202020202ED +:10E3100002020202020202020202020202020202DD +:10E3200002020202020202020202020202020202CD +:10E3300002020202020202020202020202020202BD +:10E3400002020202020202020202020202020202AD +:10E35000020202020202020202020202020202029D +:10E36000020202020202020202020202020202028D +:10E37000020202020202020202020202020202027D +:10E38000020202020202020202020202020202026D +:10E39000020202020202020202020202020202025D +:10E3A000020202020202020202020202020202024D +:10E3B000020202020202020202020202020202023D +:10E3C000020202020202020202020202020202022D +:10E3D000020202020202020202020202020202021D +:10E3E000020202020202020202020202020202020D +:10E3F00002020202020202020202020202020202FD +:10E4000002020202020202020202020202020202EC +:10E4100002020202020202020202020202020202DC +:10E4200002020202020202020202020202020202CC +:10E4300002020202020202020202020202020202BC +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A000020202020202020202020202020202024C +:10E4B000020202020202020202020202020202023C +:10E4C000020202020202020202020202020202022C +:10E4D000020202020202020202020202020202021C +:10E4E000020202020202020202020202020202020C +:10E4F00002020202020202020202020202020202FC +:10E5000002020202020202020202020202020202EB +:10E5100002020202020202020202020202020202DB +:10E5200002020202020202020202020202020202CB +:10E5300002020202020202020202020202020202BB +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A000020202020202020202020202020202024B +:10E5B000020202020202020202020202020202023B +:10E5C000020202020202020202020202020202022B +:10E5D000020202020202020202020202020202021B +:10E5E000020202020202020202020202020202020B +:10E5F00002020202020202020202020202020202FB +:10E6000002020202020202020202020202020202EA +:10E6100002020202020202020202020202020202DA +:10E6200002020202020202020202020202020202CA +:10E6300002020202020202020202020202020202BA +:10E6400002020202020202020202020202020202AA +:10E65000020202020202020202020202020202029A +:10E66000020202020202020202020202020202028A +:10E67000020202020202020202020202020202027A +:10E68000020202020202020202020202020202026A +:10E69000020202020202020202020202020202025A +:10E6A000020202020202020202020202020202024A +:10E6B000020202020202020202020202020202023A +:10E6C000020202020202020202020202020202022A +:10E6D000020202020202020202020202020202021A +:10E6E000020202020202020202020202020202020A +:10E6F00002020202020202020202020202020202FA +:10E7000002020202020202020202020202020202E9 +:10E7100002020202020202020202020202020202D9 +:10E7200002020202020202020202020202020202C9 +:10E7300002020202020202020202020202020202B9 +:10E7400002020202020202020202020202020202A9 +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000202020202020202020202020202020229 +:10E7D0000202020202020202020202020202020219 +:10E7E0000202020202020202020202020202020209 +:10E7F00002020202020202020202020202020202F9 +:10E8000002020202020202020202020202020202E8 +:10E8100002020202020202020202020202020202D8 +:10E8200002020202020202020202020202020202C8 +:10E8300002020202020202020202020202020202B8 +:10E8400002020202020202020202020202020202A8 +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C0000202020202020202020202020202020228 +:10E8D0000202020202020202020202020202020218 +:10E8E0000202020202020202020202020202020208 +:10E8F00002020202020202020202020202020202F8 +:10E9000002020202020202020202020202020202E7 +:10E9100002020202020202020202020202020202D7 +:10E9200002020202020202020202020202020202C7 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202020202020202020202020202F7 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020202020202020202020202020202C6 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020005 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E0000000000000000000000000000000006BB3 +:10F2F0000000000000000001010101010101010105 +:10F3000001010101010101010101010101010101ED +:10F3100001010101010101010101010101010101DD +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010101010101010101019D +:10F36000010101010101010101010101010101018D +:10F37000010101010101010101010101010101017D +:10F38000010101010101010101010101010101016D +:10F39000010101010101010101010101010101015D +:10F3A000010101010101010101010101010101014D +:10F3B000010101010101010101010101010101013D +:10F3C000010101010101010101010101010101012D +:10F3D000010101010101010101010101010101011D +:10F3E000010101010101010101010101010101010D +:10F3F00001010101010101010101010101010101FD +:10F4000001010101010101010101010101010101EC +:10F4100001010101010101010101010101010101DC +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F46000010101010101010101010101010101018C +:10F47000010101010101010101010101010101017C +:10F48000010101010101010101010101010101016C +:10F49000010101010101010101010101010101015C +:10F4A000010101010101010101010101010101014C +:10F4B000010101010101010101010101010101013C +:10F4C000010101010101010101010101010101012C +:10F4D000010101010101010101010101010101011C +:10F4E000010101010101010101010101010101010C +:10F4F00001010101010101010101010101010101FC +:10F5000001010101010101010101010101010101EB +:10F5100001010101010101010101010101010101DB +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101010101010101010101AB +:10F55000010101010101010101010101010101019B +:10F56000010101010101010101010101010101018B +:10F57000010101010101010101010101010101017B +:10F58000010101010101010101010101010101016B +:10F59000010101010101010101010101010101015B +:10F5A000010101010101010101010101010101014B +:10F5B000010101010101010101010101010101013B +:10F5C000010101010101010101010101010101012B +:10F5D000010101010101010101010101010101011B +:10F5E000010101010101010101010101010101010B +:10F5F00001010101010101010101010101010101FB +:10F6000001010101010101010101010101010101EA +:10F6100001010101010101010101010101010101DA +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010101010101010101017A +:10F68000010101010101010101010101010101016A +:10F69000010101010101010101010101010101015A +:10F6A000010101010101010101010101010101014A +:10F6B000010101010101010101010101010101013A +:10F6C000010101010101010101010101010101012A +:10F6D000010101010101010101010101010101011A +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010101010101010101010139 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101010101010101010141 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD0000101010101010101010101010101010111 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:020000022000DC +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101000000000000000000F3 +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000000000000000000000E4 +:100C100000000000000000000000000000000000D4 +:100C200000000000000000000000000000000000C4 +:100C300000000000000000000000000000000000B4 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000020202020202020202E2 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A000020202020202020202020202020202021A +:1016B000020202020202020202020202020202020A +:1016C00002020202020202020202020202020202FA +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202020202020202020202DA +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A0000202020202020202020202020202020219 +:1017B0000202020202020202020202020202020209 +:1017C00002020202020202020202020202020202F9 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202020202020202020202D9 +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A0000202020202020202020202020202020218 +:1018B0000202020202020202020202020202020208 +:1018C00002020202020202020202020202020202F8 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202020202020202020202D8 +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020202A7 +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020202020202020202020217 +:1019B0000202020202020202020202020202020207 +:1019C00002020202020202020202020202020202F7 +:1019D00002020202020202020202020202020202E7 +:1019E00002020202020202020202020202020202D7 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000202020202020202020202020202020216 +:101AB0000202020202020202020202020202020206 +:101AC00002020202020202020202020202020202F6 +:101AD00002020202020202020202020202020202E6 +:101AE00002020202020202020202020202020202D6 +:101AF00002020202020202020202020202020202C6 +:101B000002020202020202020202020202020202B5 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA0000202020202020202020202020202020215 +:101BB0000202020202020202020202020202020205 +:101BC00002020202020202020202020202020202F5 +:101BD00002020202020202020202020202020202E5 +:101BE00002020202020202020202020202020202D5 +:101BF00002020202020202020202020202020202C5 +:101C000002020202020202020202020202020202B4 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA0000202020202020202020202020202020214 +:101CB0000202020202020202020202020202020204 +:101CC00002020202020202020202020202020202F4 +:101CD00002020202020202020202020202020202E4 +:101CE00002020202020202020202020202020202D4 +:101CF00002020202020202020202020202020202C4 +:101D000002020202020202020202020202020202B3 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020202020203 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020202D3 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202020202 +:101EC00002020202020202020202020202020202F2 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020202D2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020202D0 +:1020F00002020202020202000000000000000000D2 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00000000000000000000000000000000000FD +:1023E00000000000000000000000000000000000ED +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000000E8 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000010101010101010101CE +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010146 +:102A80000101010101010101010101010101010136 +:102A90000101010101010101010101010101010126 +:102AA0000101010101010101010101010101010116 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010165 +:102B60000101010101010101010101010101010155 +:102B70000101010101010101010101010101010145 +:102B80000101010101010101010101010101010135 +:102B90000101010101010101010101010101010125 +:102BA0000101010101010101010101010101010115 +:102BB0000101010101010101010101010101010105 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101010101010101010101E5 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000101010101010101010101010101010164 +:102C60000101010101010101010101010101010154 +:102C70000101010101010101010101010101010144 +:102C80000101010101010101010101010101010134 +:102C90000101010101010101010101010101010124 +:102CA0000101010101010101010101010101010114 +:102CB0000101010101010101010101010101010104 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010173 +:102D50000101010101010101010101010101010163 +:102D60000101010101010101010101010101010153 +:102D70000101010101010101010101010101010143 +:102D80000101010101010101010101010101010133 +:102D90000101010101010101010101010101010123 +:102DA0000101010101010101010101010101010113 +:102DB0000101010101010101010101010101010103 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010132 +:102E90000101010101010101010101010101010122 +:102EA0000101010101010101010101010101010112 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010101D2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:10317000010101010101010101010101010101013F +:10318000010101010101010101010101010101012F +:10319000010101010101010101010101010101011F +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000010101010101010101010101010101014E +:10327000010101010101010101010101010101013E +:10328000010101010101010101010101010101012E +:10329000010101010101010101010101010101011E +:1032A000010101010101010101010101010101010E +:1032B00001010101010101010101010101010101FE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000010101010101010101010101010101011D +:1033A000010101010101010101010101010101010D +:1033B00001010101010101010101010101010101FD +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000010101010101010101010101010101017C +:10344000010101010101010101010101010101016C +:10345000010101010101010101010101010101015C +:10346000010101010101010101010101010101014C +:10347000010101010101010101010101010101013C +:10348000010101010101010101010101010101012C +:10349000010101010101010101010101010101011C +:1034A000010101010101010101010101010101010C +:1034B00001010101010101010101010101010101FC +:1034C00001010101010101010101010101010101EC +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101014A +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A000010101010101010101010101010101010A +:1036B00001010101010101010101010101010101FA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010101F8 +:1038C00001010101010101010101010101010101E8 +:1038D00001010101010101010101010101010101D8 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010101010101010101010167 +:103950000101010101010101010101010101010157 +:103960000101010101010101010101010101010147 +:103970000101010101010101010101010101010137 +:103980000101010101010101010101010101010127 +:103990000101010101010101010101010101010117 +:1039A0000101010101010101010101010101010107 +:1039B00001010101010101010101010101010101F7 +:1039C00001010101010101010101010101010101E7 +:1039D00001010101010101010101010101010101D7 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000101010101010101010101010101010176 +:103A40000101010101010101010101010101010166 +:103A50000101010101010101010101010101010156 +:103A60000101010101010101010101010101010146 +:103A70000101010101010101010101010101010136 +:103A80000101010101010101010101010101010126 +:103A90000101010101010101010101010101010116 +:103AA0000101010101010101010101010101010106 +:103AB00001010101010101010101010101010101F6 +:103AC00001010101010101010101010101010101E6 +:103AD00001010101010101010101010101010101D6 +:103AE00001010101010101010101010101010101C6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000101010101010101010101010101010135 +:103B80000101010101010101010101010101010125 +:103B90000101010101010101010101010101010115 +:103BA0000101010101010101010101010101010105 +:103BB00001010101010101010101010101010101F5 +:103BC00001010101010101010101010101010101E5 +:103BD00001010101010101010101010101010101D5 +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C60000101010101010101010101010101010144 +:103C70000101010101010101010101010101010134 +:103C80000101010101010101010101010101010124 +:103C90000101010101010101010101010101010114 +:103CA0000101010101010101010101010101010104 +:103CB00001010101010101010101010101010101F4 +:103CC00001010101010101010101010101010101E4 +:103CD00001010101010101010101010101010101D4 +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010101B4 +:103D000001010101010101010101010101010101A3 +:103D10000101010101010101010101010101010193 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000101010101010101010101010101010103 +:103DB00001010101010101010101010101010101F3 +:103DC00001010101010101010101010101010101E3 +:103DD00001010101010101010101010101010101D3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101000000000000000000BC +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000020202020202020202AB +:10440000020202020202020202020202020202028C +:10441000020202020202020202020202020202027C +:10442000020202020202020202020202020202026C +:10443000020202020202020202020202020202025C +:10444000020202020202020202020202020202024C +:10445000020202020202020202020202020202023C +:10446000020202020202020202020202020202022C +:10447000020202020202020202020202020202021C +:10448000020202020202020202020202020202020C +:1044900002020202020202020202020202020202FC +:1044A00002020202020202020202020202020202EC +:1044B00002020202020202020202020202020202DC +:1044C00002020202020202020202020202020202CC +:1044D00002020202020202020202020202020202BC +:1044E00002020202020202020202020202020202AC +:1044F000020202020202020202020202020202029C +:10450000020202020202020202020202020202028B +:10451000020202020202020202020202020202027B +:10452000020202020202020202020202020202026B +:10453000020202020202020202020202020202025B +:10454000020202020202020202020202020202024B +:10455000020202020202020202020202020202023B +:10456000020202020202020202020202020202022B +:10457000020202020202020202020202020202021B +:10458000020202020202020202020202020202020B +:1045900002020202020202020202020202020202FB +:1045A00002020202020202020202020202020202EB +:1045B00002020202020202020202020202020202DB +:1045C00002020202020202020202020202020202CB +:1045D00002020202020202020202020202020202BB +:1045E00002020202020202020202020202020202AB +:1045F000020202020202020202020202020202029B +:10460000020202020202020202020202020202028A +:10461000020202020202020202020202020202027A +:10462000020202020202020202020202020202026A +:10463000020202020202020202020202020202025A +:10464000020202020202020202020202020202024A +:10465000020202020202020202020202020202023A +:10466000020202020202020202020202020202022A +:10467000020202020202020202020202020202021A +:10468000020202020202020202020202020202020A +:1046900002020202020202020202020202020202FA +:1046A00002020202020202020202020202020202EA +:1046B00002020202020202020202020202020202DA +:1046C00002020202020202020202020202020202CA +:1046D00002020202020202020202020202020202BA +:1046E00002020202020202020202020202020202AA +:1046F000020202020202020202020202020202029A +:104700000202020202020202020202020202020289 +:104710000202020202020202020202020202020279 +:104720000202020202020202020202020202020269 +:104730000202020202020202020202020202020259 +:104740000202020202020202020202020202020249 +:104750000202020202020202020202020202020239 +:104760000202020202020202020202020202020229 +:104770000202020202020202020202020202020219 +:104780000202020202020202020202020202020209 +:1047900002020202020202020202020202020202F9 +:1047A00002020202020202020202020202020202E9 +:1047B00002020202020202020202020202020202D9 +:1047C00002020202020202020202020202020202C9 +:1047D00002020202020202020202020202020202B9 +:1047E00002020202020202020202020202020202A9 +:1047F0000202020202020202020202020202020299 +:104800000202020202020202020202020202020288 +:104810000202020202020202020202020202020278 +:104820000202020202020202020202020202020268 +:104830000202020202020202020202020202020258 +:104840000202020202020202020202020202020248 +:104850000202020202020202020202020202020238 +:104860000202020202020202020202020202020228 +:104870000202020202020202020202020202020218 +:104880000202020202020202020202020202020208 +:1048900002020202020202020202020202020202F8 +:1048A00002020202020202020202020202020202E8 +:1048B00002020202020202020202020202020202D8 +:1048C00002020202020202020202020202020202C8 +:1048D00002020202020202020202020202020202B8 +:1048E00002020202020202020202020202020202A8 +:1048F0000202020202020202020202020202020298 +:104900000202020202020202020202020202020287 +:104910000202020202020202020202020202020277 +:104920000202020202020202020202020202020267 +:104930000202020202020202020202020202020257 +:104940000202020202020202020202020202020247 +:104950000202020202020202020202020202020237 +:104960000202020202020202020202020202020227 +:104970000202020202020202020202020202020217 +:104980000202020202020202020202020202020207 +:1049900002020202020202020202020202020202F7 +:1049A00002020202020202020202020202020202E7 +:1049B00002020202020202020202020202020202D7 +:1049C00002020202020202020202020202020202C7 +:1049D00002020202020202020202020202020202B7 +:1049E00002020202020202020202020202020202A7 +:1049F0000202020202020202020202020202020297 +:104A00000202020202020202020202020202020286 +:104A10000202020202020202020202020202020276 +:104A20000202020202020202020202020202020266 +:104A30000202020202020202020202020202020256 +:104A40000202020202020202020202020202020246 +:104A50000202020202020202020202020202020236 +:104A60000202020202020202020202020202020226 +:104A70000202020202020202020202020202020216 +:104A80000202020202020202020202020202020206 +:104A900002020202020202020202020202020202F6 +:104AA00002020202020202020202020202020202E6 +:104AB00002020202020202020202020202020202D6 +:104AC00002020202020202020202020202020202C6 +:104AD00002020202020202020202020202020202B6 +:104AE00002020202020202020202020202020202A6 +:104AF0000202020202020202020202020202020296 +:104B00000202020202020202020202020202020285 +:104B10000202020202020202020202020202020275 +:104B20000202020202020202020202020202020265 +:104B30000202020202020202020202020202020255 +:104B40000202020202020202020202020202020245 +:104B50000202020202020202020202020202020235 +:104B60000202020202020202020202020202020225 +:104B70000202020202020202020202020202020215 +:104B80000202020202020202020202020202020205 +:104B900002020202020202020202020202020202F5 +:104BA00002020202020202020202020202020202E5 +:104BB00002020202020202020202020202020202D5 +:104BC00002020202020202020202020202020202C5 +:104BD00002020202020202020202020202020202B5 +:104BE00002020202020202020202020202020202A5 +:104BF0000202020202020202020202020202020295 +:104C00000202020202020202020202020202020284 +:104C10000202020202020202020202020202020274 +:104C20000202020202020202020202020202020264 +:104C30000202020202020202020202020202020254 +:104C40000202020202020202020202020202020244 +:104C50000202020202020202020202020202020234 +:104C60000202020202020202020202020202020224 +:104C70000202020202020202020202020202020214 +:104C80000202020202020202020202020202020204 +:104C900002020202020202020202020202020202F4 +:104CA00002020202020202020202020202020202E4 +:104CB00002020202020202020202020202020202D4 +:104CC00002020202020202020202020202020202C4 +:104CD00002020202020202020202020202020202B4 +:104CE00002020202020202020202020202020202A4 +:104CF0000202020202020202020202020202020294 +:104D00000202020202020202020202020202020283 +:104D10000202020202020202020202020202020273 +:104D20000202020202020202020202020202020263 +:104D30000202020202020202020202020202020253 +:104D40000202020202020202020202020202020243 +:104D50000202020202020202020202020202020233 +:104D60000202020202020202020202020202020223 +:104D70000202020202020202020202020202020213 +:104D80000202020202020202020202020202020203 +:104D900002020202020202020202020202020202F3 +:104DA00002020202020202020202020202020202E3 +:104DB00002020202020202020202020202020202D3 +:104DC00002020202020202020202020202020202C3 +:104DD00002020202020202020202020202020202B3 +:104DE00002020202020202020202020202020202A3 +:104DF0000202020202020202020202020202020293 +:104E00000202020202020202020202020202020282 +:104E10000202020202020202020202020202020272 +:104E20000202020202020202020202020202020262 +:104E30000202020202020202020202020202020252 +:104E40000202020202020202020202020202020242 +:104E50000202020202020202020202020202020232 +:104E60000202020202020202020202020202020222 +:104E70000202020202020202020202020202020212 +:104E80000202020202020202020202020202020202 +:104E900002020202020202020202020202020202F2 +:104EA00002020202020202020202020202020202E2 +:104EB00002020202020202020202020202020202D2 +:104EC00002020202020202020202020202020202C2 +:104ED00002020202020202020202020202020202B2 +:104EE00002020202020202020202020202020202A2 +:104EF0000202020202020202020202020202020292 +:104F00000202020202020202020202020202020281 +:104F10000202020202020202020202020202020271 +:104F20000202020202020202020202020202020261 +:104F30000202020202020202020202020202020251 +:104F40000202020202020202020202020202020241 +:104F50000202020202020202020202020202020231 +:104F60000202020202020202020202020202020221 +:104F70000202020202020202020202020202020211 +:104F80000202020202020202020202020202020201 +:104F900002020202020202020202020202020202F1 +:104FA00002020202020202020202020202020202E1 +:104FB00002020202020202020202020202020202D1 +:104FC00002020202020202020202020202020202C1 +:104FD00002020202020202020202020202020202B1 +:104FE00002020202020202020202020202020202A1 +:104FF0000202020202020202020202020202020291 +:105000000202020202020202020202020202020280 +:105010000202020202020202020202020202020270 +:105020000202020202020202020202020202020260 +:105030000202020202020202020202020202020250 +:105040000202020202020202020202020202020240 +:105050000202020202020202020202020202020230 +:105060000202020202020202020202020202020220 +:105070000202020202020202020202020202020210 +:105080000202020202020202020202020202020200 +:1050900002020202020202020202020202020202F0 +:1050A00002020202020202020202020202020202E0 +:1050B00002020202020202020202020202020202D0 +:1050C00002020202020202020202020202020202C0 +:1050D00002020202020202020202020202020202B0 +:1050E00002020202020202020202020202020202A0 +:1050F0000202020202020202020202020202020290 +:10510000020202020202020202020202020202027F +:10511000020202020202020202020202020202026F +:10512000020202020202020202020202020202025F +:10513000020202020202020202020202020202024F +:10514000020202020202020202020202020202023F +:10515000020202020202020202020202020202022F +:10516000020202020202020202020202020202021F +:10517000020202020202020202020202020202020F +:1051800002020202020202020202020202020202FF +:1051900002020202020202020202020202020202EF +:1051A00002020202020202020202020202020202DF +:1051B00002020202020202020202020202020202CF +:1051C00002020202020202020202020202020202BF +:1051D00002020202020202020202020202020202AF +:1051E000020202020202020202020202020202029F +:1051F000020202020202020202020202020202028F +:10520000020202020202020202020202020202027E +:10521000020202020202020202020202020202026E +:10522000020202020202020202020202020202025E +:10523000020202020202020202020202020202024E +:10524000020202020202020202020202020202023E +:10525000020202020202020202020202020202022E +:10526000020202020202020202020202020202021E +:10527000020202020202020202020202020202020E +:1052800002020202020202020202020202020202FE +:1052900002020202020202020202020202020202EE +:1052A00002020202020202020202020202020202DE +:1052B00002020202020202020202020202020202CE +:1052C00002020202020202020202020202020202BE +:1052D00002020202020202020202020202020202AE +:1052E000020202020202020202020202020202029E +:1052F000020202020202020202020202020202028E +:10530000020202020202020202020202020202027D +:10531000020202020202020202020202020202026D +:10532000020202020202020202020202020202025D +:10533000020202020202020202020202020202024D +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202020202020202020202020202ED +:1053A00002020202020202020202020202020202DD +:1053B00002020202020202020202020202020202CD +:1053C00002020202020202020202020202020202BD +:1053D00002020202020202020202020202020202AD +:1053E000020202020202020202020202020202029D +:1053F000020202020202020202020202020202028D +:10540000020202020202020202020202020202027C +:10541000020202020202020202020202020202026C +:10542000020202020202020202020202020202025C +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202020202020202020202EC +:1054A00002020202020202020202020202020202DC +:1054B00002020202020202020202020202020202CC +:1054C00002020202020202020202020202020202BC +:1054D00002020202020202020202020202020202AC +:1054E000020202020202020202020202020202029C +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020202020202020202020202020202DB +:1055B00002020202020202020202020202020202CB +:1055C00002020202020202020202020202020202BB +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020202020202020202020202020202027A +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020202020202020202020202020202DA +:1056B00002020202020202020202020202020202CA +:1056C00002020202020202020202020202020202BA +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F000020202020202020000000000000000009B +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000000000000000000000C8 +:1058E00000000000000000000000000000000000B8 +:1058F00000000000000000000000000000000000A8 +:105900000000000000000000000000000000000097 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000000000000000000000C7 +:1059E00000000000000000000000000000000000B7 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF000000000000000006300000000000000013F +:105E00000101010101010101010101010101010182 +:105E10000101010101010101010101010101010172 +:105E20000101010101010101010101010101010162 +:105E30000101010101010101010101010101010152 +:105E40000101010101010101010101010101010142 +:105E50000101010101010101010101010101010132 +:105E60000101010101010101010101010101010122 +:105E70000101010101010101010101010101010112 +:105E80000101010101010101010101010101010102 +:105E900001010101010101010101010101010101F2 +:105EA00001010101010101010101010101010101E2 +:105EB00001010101010101010101010101010101D2 +:105EC00001010101010101010101010101010101C2 +:105ED00001010101010101010101010101010101B2 +:105EE00001010101010101010101010101010101A2 +:105EF0000101010101010101010101010101010192 +:105F00000101010101010101010101010101010181 +:105F10000101010101010101010101010101010171 +:105F20000101010101010101010101010101010161 +:105F30000101010101010101010101010101010151 +:105F40000101010101010101010101010101010141 +:105F50000101010101010101010101010101010131 +:105F60000101010101010101010101010101010121 +:105F70000101010101010101010101010101010111 +:105F80000101010101010101010101010101010101 +:105F900001010101010101010101010101010101F1 +:105FA00001010101010101010101010101010101E1 +:105FB00001010101010101010101010101010101D1 +:105FC00001010101010101010101010101010101C1 +:105FD00001010101010101010101010101010101B1 +:105FE00001010101010101010101010101010101A1 +:105FF0000101010101010101010101010101010191 +:106000000101010101010101010101010101010180 +:106010000101010101010101010101010101010170 +:106020000101010101010101010101010101010160 +:106030000101010101010101010101010101010150 +:106040000101010101010101010101010101010140 +:106050000101010101010101010101010101010130 +:106060000101010101010101010101010101010120 +:106070000101010101010101010101010101010110 +:106080000101010101010101010101010101010100 +:1060900001010101010101010101010101010101F0 +:1060A00001010101010101010101010101010101E0 +:1060B00001010101010101010101010101010101D0 +:1060C00001010101010101010101010101010101C0 +:1060D00001010101010101010101010101010101B0 +:1060E00001010101010101010101010101010101A0 +:1060F0000101010101010101010101010101010190 +:10610000010101010101010101010101010101017F +:10611000010101010101010101010101010101016F +:10612000010101010101010101010101010101015F +:10613000010101010101010101010101010101014F +:10614000010101010101010101010101010101013F +:10615000010101010101010101010101010101012F +:10616000010101010101010101010101010101011F +:10617000010101010101010101010101010101010F +:1061800001010101010101010101010101010101FF +:1061900001010101010101010101010101010101EF +:1061A00001010101010101010101010101010101DF +:1061B00001010101010101010101010101010101CF +:1061C00001010101010101010101010101010101BF +:1061D00001010101010101010101010101010101AF +:1061E000010101010101010101010101010101019F +:1061F000010101010101010101010101010101018F +:10620000010101010101010101010101010101017E +:10621000010101010101010101010101010101016E +:10622000010101010101010101010101010101015E +:10623000010101010101010101010101010101014E +:10624000010101010101010101010101010101013E +:10625000010101010101010101010101010101012E +:10626000010101010101010101010101010101011E +:10627000010101010101010101010101010101010E +:1062800001010101010101010101010101010101FE +:1062900001010101010101010101010101010101EE +:1062A00001010101010101010101010101010101DE +:1062B00001010101010101010101010101010101CE +:1062C00001010101010101010101010101010101BE +:1062D00001010101010101010101010101010101AE +:1062E000010101010101010101010101010101019E +:1062F000010101010101010101010101010101018E +:10630000010101010101010101010101010101017D +:10631000010101010101010101010101010101016D +:10632000010101010101010101010101010101015D +:10633000010101010101010101010101010101014D +:10634000010101010101010101010101010101013D +:10635000010101010101010101010101010101012D +:10636000010101010101010101010101010101011D +:10637000010101010101010101010101010101010D +:1063800001010101010101010101010101010101FD +:1063900001010101010101010101010101010101ED +:1063A00001010101010101010101010101010101DD +:1063B00001010101010101010101010101010101CD +:1063C00001010101010101010101010101010101BD +:1063D00001010101010101010101010101010101AD +:1063E000010101010101010101010101010101019D +:1063F000010101010101010101010101010101018D +:10640000010101010101010101010101010101017C +:10641000010101010101010101010101010101016C +:10642000010101010101010101010101010101015C +:10643000010101010101010101010101010101014C +:10644000010101010101010101010101010101013C +:10645000010101010101010101010101010101012C +:10646000010101010101010101010101010101011C +:10647000010101010101010101010101010101010C +:1064800001010101010101010101010101010101FC +:1064900001010101010101010101010101010101EC +:1064A00001010101010101010101010101010101DC +:1064B00001010101010101010101010101010101CC +:1064C00001010101010101010101010101010101BC +:1064D00001010101010101010101010101010101AC +:1064E000010101010101010101010101010101019C +:1064F000010101010101010101010101010101018C +:10650000010101010101010101010101010101017B +:10651000010101010101010101010101010101016B +:10652000010101010101010101010101010101015B +:10653000010101010101010101010101010101014B +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010101010101010101FB +:1065900001010101010101010101010101010101EB +:1065A00001010101010101010101010101010101DB +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101018B +:10660000010101010101010101010101010101017A +:10661000010101010101010101010101010101016A +:10662000010101010101010101010101010101015A +:10663000010101010101010101010101010101014A +:10664000010101010101010101010101010101013A +:10665000010101010101010101010101010101012A +:10666000010101010101010101010101010101011A +:10667000010101010101010101010101010101010A +:1066800001010101010101010101010101010101FA +:1066900001010101010101010101010101010101EA +:1066A00001010101010101010101010101010101DA +:1066B00001010101010101010101010101010101CA +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101010101010101010101AA +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101018A +:106700000101010101010101010101010101010179 +:106710000101010101010101010101010101010169 +:106720000101010101010101010101010101010159 +:106730000101010101010101010101010101010149 +:106740000101010101010101010101010101010139 +:106750000101010101010101010101010101010129 +:106760000101010101010101010101010101010119 +:106770000101010101010101010101010101010109 +:1067800001010101010101010101010101010101F9 +:1067900001010101010101010101010101010101E9 +:1067A00001010101010101010101010101010101D9 +:1067B00001010101010101010101010101010101C9 +:1067C00001010101010101010101010101010101B9 +:1067D00001010101010101010101010101010101A9 +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010178 +:106810000101010101010101010101010101010168 +:106820000101010101010101010101010101010158 +:106830000101010101010101010101010101010148 +:106840000101010101010101010101010101010138 +:106850000101010101010101010101010101010128 +:106860000101010101010101010101010101010118 +:106870000101010101010101010101010101010108 +:1068800001010101010101010101010101010101F8 +:1068900001010101010101010101010101010101E8 +:1068A00001010101010101010101010101010101D8 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010147 +:106940000101010101010101010101010101010137 +:106950000101010101010101010101010101010127 +:106960000101010101010101010101010101010117 +:106970000101010101010101010101010101010107 +:1069800001010101010101010101010101010101F7 +:1069900001010101010101010101010101010101E7 +:1069A00001010101010101010101010101010101D7 +:1069B00001010101010101010101010101010101C7 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101010101010101010101A7 +:1069E0000101010101010101010101010101010197 +:1069F0000101010101010101010101010101010187 +:106A00000101010101010101010101010101010176 +:106A10000101010101010101010101010101010166 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000101010101010101010101010101010136 +:106A50000101010101010101010101010101010126 +:106A60000101010101010101010101010101010116 +:106A70000101010101010101010101010101010106 +:106A800001010101010101010101010101010101F6 +:106A900001010101010101010101010101010101E6 +:106AA00001010101010101010101010101010101D6 +:106AB00001010101010101010101010101010101C6 +:106AC00001010101010101010101010101010101B6 +:106AD00001010101010101010101010101010101A6 +:106AE0000101010101010101010101010101010196 +:106AF0000101010101010101010101010101010186 +:106B00000101010101010101010101010101010175 +:106B10000101010101010101010101010101010165 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B70000101010101010101010101010101010105 +:106B800001010101010101010101010101010101F5 +:106B900001010101010101010101010101010101E5 +:106BA00001010101010101010101010101010101D5 +:106BB00001010101010101010101010101010101C5 +:106BC00001010101010101010101010101010101B5 +:106BD00001010101010101010101010101010101A5 +:106BE0000101010101010101010101010101010195 +:106BF0000101010101010101010101010101010185 +:106C00000101010101010101010101010101010174 +:106C10000101010101010101010101010101010164 +:106C20000101010101010101010101010101010154 +:106C30000101010101010101010101010101010144 +:106C40000101010101010101010101010101010134 +:106C50000101010101010101010101010101010124 +:106C60000101010101010101010101010101010114 +:106C70000101010101010101010101010101010104 +:106C800001010101010101010101010101010101F4 +:106C900001010101010101010101010101010101E4 +:106CA00001010101010101010101010101010101D4 +:106CB00001010101010101010101010101010101C4 +:106CC00001010101010101010101010101010101B4 +:106CD00001010101010101010101010101010101A4 +:106CE0000101010101010101010101010101010194 +:106CF0000101010101010101010101010101010184 +:106D00000101010101010101010101010101010173 +:106D10000101010101010101010101010101010163 +:106D20000101010101010101010101010101010153 +:106D30000101010101010101010101010101010143 +:106D40000101010101010101010101010101010133 +:106D50000101010101010101010101010101010123 +:106D60000101010101010101010101010101010113 +:106D70000101010101010101010101010101010103 +:106D800001010101010101010101010101010101F3 +:106D900001010101010101010101010101010101E3 +:106DA00001010101010101010101010101010101D3 +:106DB00001010101010101010101010101010101C3 +:106DC00001010101010101010101010101010101B3 +:106DD00001010101010101010101010101010101A3 +:106DE0000101010101010101010101010101010193 +:106DF0000101010101010101010101010101010183 +:106E00000101010101010101010101010101010172 +:106E10000101010101010101010101010101010162 +:106E20000101010101010101010101010101010152 +:106E30000101010101010101010101010101010142 +:106E40000101010101010101010101010101010132 +:106E50000101010101010101010101010101010122 +:106E60000101010101010101010101010101010112 +:106E70000101010101010101010101010101010102 +:106E800001010101010101010101010101010101F2 +:106E900001010101010101010101010101010101E2 +:106EA00001010101010101010101010101010101D2 +:106EB00001010101010101010101010101010101C2 +:106EC00001010101010101010101010101010101B2 +:106ED00001010101010101010101010101010101A2 +:106EE0000101010101010101010101010101010192 +:106EF0000101010101010101010101010101010182 +:106F00000101010101010101010101010101010171 +:106F10000101010101010101010101010101010161 +:106F20000101010101010101010101010101010151 +:106F30000101010101010101010101010101010141 +:106F40000101010101010101010101010101010131 +:106F50000101010101010101010101010101010121 +:106F60000101010101010101010101010101010111 +:106F70000101010101010101010101010101010101 +:106F800001010101010101010101010101010101F1 +:106F900001010101010101010101010101010101E1 +:106FA00001010101010101010101010101010101D1 +:106FB00001010101010101010101010101010101C1 +:106FC00001010101010101010101010101010101B1 +:106FD00001010101010101010101010101010101A1 +:106FE0000101010101010101010101010101010191 +:106FF0000101010101010101010101010101010082 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F0000000000000000000000000000000000289 +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202020286 +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020202020285 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020202B4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202020202020202020284 +:107CE0000202020202020202020202020202020274 +:107CF0000202020202020202020202020202020264 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020202020202020283 +:107DE0000202020202020202020202020202020273 +:107DF0000202020202020202020202020202020263 +:107E00000202020202020202020202020202020252 +:107E10000202020202020202020202020202020242 +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020202C2 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020202020202020202020282 +:107EE0000202020202020202020202020202020272 +:107EF0000202020202020202020202020202020262 +:107F00000202020202020202020202020202020251 +:107F10000202020202020202020202020202020241 +:107F20000202020202020202020202020202020231 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020202C1 +:107FA00002020202020202020202020202020202B1 +:107FB00002020202020202020202020202020202A1 +:107FC0000202020202020202020202020202020291 +:107FD0000202020202020202020202020202020281 +:107FE0000202020202020202020202020202020271 +:107FF0000202020202020202020202020202020261 +:108000000202020202020202020202020202020250 +:108010000202020202020202020202020202020240 +:108020000202020202020202020202020202020230 +:108030000202020202020202020202020202020220 +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202020202020202020202C0 +:1080A00002020202020202020202020202020202B0 +:1080B00002020202020202020202020202020202A0 +:1080C0000202020202020202020202020202020290 +:1080D0000202020202020202020202020202020280 +:1080E0000202020202020202020202020202020270 +:1080F0000202020202020202020202020202020260 +:10810000020202020202020202020202020202024F +:10811000020202020202020202020202020202023F +:10812000020202020202020202020202020202022F +:10813000020202020202020202020202020202021F +:10814000020202020202020202020202020202020F +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202020202020202020202BF +:1081A00002020202020202020202020202020202AF +:1081B000020202020202020202020202020202029F +:1081C000020202020202020202020202020202028F +:1081D000020202020202020202020202020202027F +:1081E000020202020202020202020202020202026F +:1081F000020202020202020202020202020202025F +:10820000020202020202020202020202020202024E +:10821000020202020202020202020202020202023E +:10822000020202020202020202020202020202022E +:10823000020202020202020202020202020202021E +:10824000020202020202020202020202020202020E +:1082500002020202020202020202020202020202FE +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202020202020202020202BE +:1082A00002020202020202020202020202020202AE +:1082B000020202020202020202020202020202029E +:1082C000020202020202020202020202020202028E +:1082D000020202020202020202020202020202027E +:1082E000020202020202020202020202020202026E +:1082F000020202020202020202020202020202025E +:10830000020202020202020202020202020202024D +:10831000020202020202020202020202020202023D +:10832000020202020202020202020202020202022D +:10833000020202020202020202020202020202021D +:10834000020202020202020202020202020202020D +:1083500002020202020202020202020202020202FD +:1083600002020202020202020202020202020202ED +:1083700002020202020202020202020202020202DD +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020202BD +:1083A00002020202020202020202020202020202AD +:1083B000020202020202020202020202020202029D +:1083C000020202020202020202020202020202028D +:1083D000020202020202020202020202020202027D +:1083E000020202020202020202020202020202026D +:1083F000020202020202020202020202020202025D +:10840000020202020202020202020202020202024C +:10841000020202020202020202020202020202023C +:10842000020202020202020202020202020202022C +:10843000020202020202020202020202020202021C +:10844000020202020202020202020202020202020C +:1084500002020202020202020202020202020202FC +:1084600002020202020202020202020202020202EC +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020202BC +:1084A00002020202020202020202020202020202AC +:1084B000020202020202020202020202020202029C +:1084C000020202020202020202020202020202028C +:1084D000020202020202020202020202020202027C +:1084E000020202020202020202020202020202026C +:1084F000020202020202020202020202020202025C +:10850000020202020202020202020202020202024B +:10851000020202020202020202020202020202023B +:10852000020202020202020202020202020202022B +:10853000020202020202020202020202020202021B +:10854000020202020202020202020202020202020B +:1085500002020202020202020202020202020202FB +:1085600002020202020202020202020202020202EB +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020202AB +:1085B000020202020202020202020202020202029B +:1085C000020202020202020202020202020202028B +:1085D000020202020202020202020202020202027B +:1085E000020202020202020202020202020202026B +:1085F000020202020202020202020202020202025B +:10860000020202020202020202020202020202024A +:10861000020202020202020202020202020202023A +:10862000020202020202020202020202020202022A +:10863000020202020202020202020202020202021A +:10864000020202020202020202020202020202020A +:1086500002020202020202020202020202020202FA +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202020202DA +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020202AA +:1086B000020202020202020202020202020202029A +:1086C000020202020202020202020202020202028A +:1086D000020202020202020202020202020202027A +:1086E000020202020202020202020202020202026A +:1086F000020202020202020202020202020202025A +:108700000202020202020202020202020202020249 +:108710000202020202020202020202020202020239 +:108720000202020202020202020202020202020229 +:108730000202020202020202020202020202020219 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020202A9 +:1087B0000202020202020202020202020202020299 +:1087C0000202020202020202020202020202020289 +:1087D0000202020202020202020202020202020279 +:1087E0000202020202020202020202020202020269 +:1087F000020202020202020202020202020202005B +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F000000000000000000000000000000000016F +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101004F +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000256 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202020202020202020202020202EA +:10B6400002020202020202020202020202020202DA +:10B6500002020202020202020202020202020202CA +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020202020202020202020202028A +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C000020202020202020202020202020202025A +:10B6D000020202020202020202020202020202024A +:10B6E000020202020202020202020202020202023A +:10B6F000020202020202020202020202020202022A +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020028 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000005BE5 +:10C100000000000000000001010101010101010126 +:10C11000010101010101010101010101010101010F +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010101010101DF +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A000010101010101010101010101010101017F +:10C1B000010101010101010101010101010101016F +:10C1C000010101010101010101010101010101015F +:10C1D000010101010101010101010101010101014F +:10C1E000010101010101010101010101010101013F +:10C1F000010101010101010101010101010101012F +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101010101010101010101CE +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A000010101010101010101010101010101017E +:10C2B000010101010101010101010101010101016E +:10C2C000010101010101010101010101010101015E +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010101010101ED +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101010101010101010101CD +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010101010101010101017D +:10C3B000010101010101010101010101010101016D +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101010C +:10C4200001010101010101010101010101010101FC +:10C4300001010101010101010101010101010101EC +:10C4400001010101010101010101010101010101DC +:10C4500001010101010101010101010101010101CC +:10C4600001010101010101010101010101010101BC +:10C4700001010101010101010101010101010101AC +:10C48000010101010101010101010101010101019C +:10C49000010101010101010101010101010101018C +:10C4A000010101010101010101010101010101017C +:10C4B000010101010101010101010101010101016C +:10C4C000010101010101010101010101010101015C +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010101010101010101013C +:10C4F000010101010101010101010101010101012C +:10C50000010101010101010101010101010101011B +:10C51000010101010101010101010101010101010B +:10C5200001010101010101010101010101010101FB +:10C5300001010101010101010101010101010101EB +:10C5400001010101010101010101010101010101DB +:10C5500001010101010101010101010101010101CB +:10C5600001010101010101010101010101010101BB +:10C5700001010101010101010101010101010101AB +:10C58000010101010101010101010101010101019B +:10C59000010101010101010101010101010101018B +:10C5A000010101010101010101010101010101017B +:10C5B000010101010101010101010101010101016B +:10C5C000010101010101010101010101010101015B +:10C5D000010101010101010101010101010101014B +:10C5E000010101010101010101010101010101013B +:10C5F000010101010101010101010101010101012B +:10C60000010101010101010101010101010101011A +:10C61000010101010101010101010101010101010A +:10C6200001010101010101010101010101010101FA +:10C6300001010101010101010101010101010101EA +:10C6400001010101010101010101010101010101DA +:10C6500001010101010101010101010101010101CA +:10C6600001010101010101010101010101010101BA +:10C6700001010101010101010101010101010101AA +:10C68000010101010101010101010101010101019A +:10C69000010101010101010101010101010101018A +:10C6A000010101010101010101010101010101017A +:10C6B000010101010101010101010101010101016A +:10C6C000010101010101010101010101010101015A +:10C6D000010101010101010101010101010101014A +:10C6E000010101010101010101010101010101013A +:10C6F000010101010101010101010101010101012A +:10C700000101010101010101010101010101010119 +:10C710000101010101010101010101010101010109 +:10C7200001010101010101010101010101010101F9 +:10C7300001010101010101010101010101010101E9 +:10C7400001010101010101010101010101010101D9 +:10C7500001010101010101010101010101010101C9 +:10C7600001010101010101010101010101010101B9 +:10C7700001010101010101010101010101010101A9 +:10C780000101010101010101010101010101010199 +:10C790000101010101010101010101010101010189 +:10C7A0000101010101010101010101010101010179 +:10C7B0000101010101010101010101010101010169 +:10C7C0000101010101010101010101010101010159 +:10C7D0000101010101010101010101010101010149 +:10C7E0000101010101010101010101010101010139 +:10C7F0000101010101010101010101010101010129 +:10C800000101010101010101010101010101010118 +:10C810000101010101010101010101010101010108 +:10C8200001010101010101010101010101010101F8 +:10C8300001010101010101010101010101010101E8 +:10C8400001010101010101010101010101010101D8 +:10C8500001010101010101010101010101010101C8 +:10C8600001010101010101010101010101010101B8 +:10C8700001010101010101010101010101010101A8 +:10C880000101010101010101010101010101010198 +:10C890000101010101010101010101010101010188 +:10C8A0000101010101010101010101010101010178 +:10C8B0000101010101010101010101010101010168 +:10C8C0000101010101010101010101010101010158 +:10C8D0000101010101010101010101010101010148 +:10C8E0000101010101010101010101010101010138 +:10C8F0000101010101010101010101010101010128 +:10C900000101010101010101010101010101010117 +:10C910000101010101010101010101010101010107 +:10C9200001010101010101010101010101010101F7 +:10C9300001010101010101010101010101010101E7 +:10C9400001010101010101010101010101010101D7 +:10C9500001010101010101010101010101010101C7 +:10C9600001010101010101010101010101010101B7 +:10C9700001010101010101010101010101010101A7 +:10C980000101010101010101010101010101010197 +:10C990000101010101010101010101010101010187 +:10C9A0000101010101010101010101010101010177 +:10C9B0000101010101010101010101010101010167 +:10C9C0000101010101010101010101010101010157 +:10C9D0000101010101010101010101010101010147 +:10C9E0000101010101010101010101010101010137 +:10C9F0000101010101010101010101010101010127 +:10CA00000101010101010101010101010101010116 +:10CA10000101010101010101010101010101010106 +:10CA200001010101010101010101010101010101F6 +:10CA300001010101010101010101010101010101E6 +:10CA400001010101010101010101010101010101D6 +:10CA500001010101010101010101010101010101C6 +:10CA600001010101010101010101010101010101B6 +:10CA700001010101010101010101010101010101A6 +:10CA80000101010101010101010101010101010196 +:10CA90000101010101010101010101010101010186 +:10CAA0000101010101010101010101010101010176 +:10CAB0000101010101010101010101010101010166 +:10CAC0000101010101010101010101010101010156 +:10CAD0000101010101010101010101010101010146 +:10CAE0000101010101010101010101010101010136 +:10CAF0000101010101010101010101010101010126 +:10CB00000101010101010101010101010101010115 +:10CB10000101010101010101010101010101010105 +:10CB200001010101010101010101010101010101F5 +:10CB300001010101010101010101010101010101E5 +:10CB400001010101010101010101010101010101D5 +:10CB500001010101010101010101010101010101C5 +:10CB600001010101010101010101010101010101B5 +:10CB700001010101010101010101010101010101A5 +:10CB80000101010101010101010101010101010195 +:10CB90000101010101010101010101010101010185 +:10CBA0000101010101010101010101010101010175 +:10CBB0000101010101010101010101010101010165 +:10CBC0000101010101010101010101010101010155 +:10CBD0000101010101010101010101010101010145 +:10CBE0000101010101010101010101010101010135 +:10CBF0000101010101010101010101010101010125 +:10CC00000101010101010101010101010101010114 +:10CC10000101010101010101010101010101010104 +:10CC200001010101010101010101010101010101F4 +:10CC300001010101010101010101010101010101E4 +:10CC400001010101010101010101010101010101D4 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010101A4 +:10CC80000101010101010101010101010101010194 +:10CC90000101010101010101010101010101010184 +:10CCA0000101010101010101010101010101010174 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010101A3 +:10CD80000101010101010101010101010101010193 +:10CD90000101010101010101010101010101010183 +:10CDA0000101010101010101010101010101010173 +:10CDB0000101010101010101010101010101010163 +:10CDC0000101010101010101010101010101010153 +:10CDD0000101010101010101010101010101010143 +:10CDE0000101010101010101010101010101010133 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010101A2 +:10CE80000101010101010101010101010101010192 +:10CE90000101010101010101010101010101010182 +:10CEA0000101010101010101010101010101010172 +:10CEB0000101010101010101010101010101010162 +:10CEC0000101010101010101010101010101010152 +:10CED0000101010101010101010101010101010142 +:10CEE0000101010101010101010101010101010132 +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400001010101010101010101010101010101D1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700001010101010101010101010101010101A1 +:10CF80000101010101010101010101010101010191 +:10CF90000101010101010101010101010101010181 +:10CFA0000101010101010101010101010101010171 +:10CFB0000101010101010101010101010101010161 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010141 +:10CFE0000101010101010101010101010101010131 +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010100000000000000000019 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000002020202020202020207 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020202020202020202020239 +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C0000202020202020202020202020202020238 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202020202020237 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202020202020236 +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020202020202020202020216 +:10DAF0000202020202020202020202020202020206 +:10DB000002020202020202020202020202020202F5 +:10DB100002020202020202020202020202020202E5 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB0000202020202020202020202020202020245 +:10DBC0000202020202020202020202020202020235 +:10DBD0000202020202020202020202020202020225 +:10DBE0000202020202020202020202020202020215 +:10DBF0000202020202020202020202020202020205 +:10DC000002020202020202020202020202020202F4 +:10DC100002020202020202020202020202020202E4 +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB0000202020202020202020202020202020244 +:10DCC0000202020202020202020202020202020234 +:10DCD0000202020202020202020202020202020224 +:10DCE0000202020202020202020202020202020214 +:10DCF0000202020202020202020202020202020204 +:10DD000002020202020202020202020202020202F3 +:10DD100002020202020202020202020202020202E3 +:10DD200002020202020202020202020202020202D3 +:10DD300002020202020202020202020202020202C3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB0000202020202020202020202020202020243 +:10DDC0000202020202020202020202020202020233 +:10DDD0000202020202020202020202020202020223 +:10DDE0000202020202020202020202020202020213 +:10DDF0000202020202020202020202020202020203 +:10DE000002020202020202020202020202020202F2 +:10DE100002020202020202020202020202020202E2 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA0000202020202020202020202020202020252 +:10DEB0000202020202020202020202020202020242 +:10DEC0000202020202020202020202020202020232 +:10DED0000202020202020202020202020202020222 +:10DEE0000202020202020202020202020202020212 +:10DEF0000202020202020202020202020202020202 +:10DF000002020202020202020202020202020202F1 +:10DF100002020202020202020202020202020202E1 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202020202020231 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020202020202020202020211 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020202020202020202020250 +:10E0B0000202020202020202020202020202020240 +:10E0C0000202020202020202020202020202020230 +:10E0D0000202020202020202020202020202020220 +:10E0E0000202020202020202020202020202020210 +:10E0F0000202020202020202020202020202020200 +:10E1000002020202020202020202020202020202EF +:10E1100002020202020202020202020202020202DF +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A000020202020202020202020202020202024F +:10E1B000020202020202020202020202020202023F +:10E1C000020202020202020202020202020202022F +:10E1D000020202020202020202020202020202021F +:10E1E000020202020202020202020202020202020F +:10E1F00002020202020202020202020202020202FF +:10E2000002020202020202020202020202020202EE +:10E2100002020202020202020202020202020202DE +:10E2200002020202020202020202020202020202CE +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E28000020202020202020202020202020202026E +:10E29000020202020202020202020202020202025E +:10E2A000020202020202020202020202020202024E +:10E2B000020202020202020202020202020202023E +:10E2C000020202020202020202020202020202022E +:10E2D000020202020202020202020202020202021E +:10E2E000020202020202020202020202020202020E +:10E2F00002020202020202020202020202020202FE +:10E3000002020202020202020202020202020202ED +:10E3100002020202020202020202020202020202DD +:10E3200002020202020202020202020202020202CD +:10E3300002020202020202020202020202020202BD +:10E3400002020202020202020202020202020202AD +:10E35000020202020202020202020202020202029D +:10E36000020202020202020202020202020202028D +:10E37000020202020202020202020202020202027D +:10E38000020202020202020202020202020202026D +:10E39000020202020202020202020202020202025D +:10E3A000020202020202020202020202020202024D +:10E3B000020202020202020202020202020202023D +:10E3C000020202020202020202020202020202022D +:10E3D000020202020202020202020202020202021D +:10E3E000020202020202020202020202020202020D +:10E3F00002020202020202020202020202020202FD +:10E4000002020202020202020202020202020202EC +:10E4100002020202020202020202020202020202DC +:10E4200002020202020202020202020202020202CC +:10E4300002020202020202020202020202020202BC +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A000020202020202020202020202020202024C +:10E4B000020202020202020202020202020202023C +:10E4C000020202020202020202020202020202022C +:10E4D000020202020202020202020202020202021C +:10E4E000020202020202020202020202020202020C +:10E4F00002020202020202020202020202020202FC +:10E5000002020202020202020202020202020202EB +:10E5100002020202020202020202020202020202DB +:10E5200002020202020202020202020202020202CB +:10E5300002020202020202020202020202020202BB +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A000020202020202020202020202020202024B +:10E5B000020202020202020202020202020202023B +:10E5C000020202020202020202020202020202022B +:10E5D000020202020202020202020202020202021B +:10E5E000020202020202020202020202020202020B +:10E5F00002020202020202020202020202020202FB +:10E6000002020202020202000000000000000000FC +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000000000000000000000037 +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000000000000000000000036 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000000000000000000000035 +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000000000000000000000034 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F0000000000000000000010101010101010101F7 +:10F0100001010101010101010101010101010101E0 +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101010101010101010101C0 +:10F0400001010101010101010101010101010101B0 +:10F0500001010101010101010101010101010101A0 +:10F060000101010101010101010101010101010190 +:10F070000101010101010101010101010101010180 +:10F080000101010101010101010101010101010170 +:10F090000101010101010101010101010101010160 +:10F0A0000101010101010101010101010101010150 +:10F0B0000101010101010101010101010101010140 +:10F0C0000101010101010101010101010101010130 +:10F0D0000101010101010101010101010101010120 +:10F0E0000101010101010101010101010101010110 +:10F0F0000101010101010101010101010101010100 +:10F1000001010101010101010101010101010101EF +:10F1100001010101010101010101010101010101DF +:10F1200001010101010101010101010101010101CF +:10F1300001010101010101010101010101010101BF +:10F1400001010101010101010101010101010101AF +:10F15000010101010101010101010101010101019F +:10F16000010101010101010101010101010101018F +:10F17000010101010101010101010101010101017F +:10F18000010101010101010101010101010101016F +:10F19000010101010101010101010101010101015F +:10F1A000010101010101010101010101010101014F +:10F1B000010101010101010101010101010101013F +:10F1C000010101010101010101010101010101012F +:10F1D000010101010101010101010101010101011F +:10F1E000010101010101010101010101010101010F +:10F1F00001010101010101010101010101010101FF +:10F2000001010101010101010101010101010101EE +:10F2100001010101010101010101010101010101DE +:10F2200001010101010101010101010101010101CE +:10F2300001010101010101010101010101010101BE +:10F2400001010101010101010101010101010101AE +:10F25000010101010101010101010101010101019E +:10F26000010101010101010101010101010101018E +:10F27000010101010101010101010101010101017E +:10F28000010101010101010101010101010101016E +:10F29000010101010101010101010101010101015E +:10F2A000010101010101010101010101010101014E +:10F2B000010101010101010101010101010101013E +:10F2C000010101010101010101010101010101012E +:10F2D000010101010101010101010101010101011E +:10F2E000010101010101010101010101010101010E +:10F2F00001010101010101010101010101010101FE +:10F3000001010101010101010101010101010101ED +:10F3100001010101010101010101010101010101DD +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010101010101010101019D +:10F36000010101010101010101010101010101018D +:10F37000010101010101010101010101010101017D +:10F38000010101010101010101010101010101016D +:10F39000010101010101010101010101010101015D +:10F3A000010101010101010101010101010101014D +:10F3B000010101010101010101010101010101013D +:10F3C000010101010101010101010101010101012D +:10F3D000010101010101010101010101010101011D +:10F3E000010101010101010101010101010101010D +:10F3F00001010101010101010101010101010101FD +:10F4000001010101010101010101010101010101EC +:10F4100001010101010101010101010101010101DC +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F46000010101010101010101010101010101018C +:10F47000010101010101010101010101010101017C +:10F48000010101010101010101010101010101016C +:10F49000010101010101010101010101010101015C +:10F4A000010101010101010101010101010101014C +:10F4B000010101010101010101010101010101013C +:10F4C000010101010101010101010101010101012C +:10F4D000010101010101010101010101010101011C +:10F4E000010101010101010101010101010101010C +:10F4F00001010101010101010101010101010101FC +:10F5000001010101010101010101010101010101EB +:10F5100001010101010101010101010101010101DB +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101010101010101010101AB +:10F55000010101010101010101010101010101019B +:10F56000010101010101010101010101010101018B +:10F57000010101010101010101010101010101017B +:10F58000010101010101010101010101010101016B +:10F59000010101010101010101010101010101015B +:10F5A000010101010101010101010101010101014B +:10F5B000010101010101010101010101010101013B +:10F5C000010101010101010101010101010101012B +:10F5D000010101010101010101010101010101011B +:10F5E000010101010101010101010101010101010B +:10F5F00001010101010101010101010101010101FB +:10F6000001010101010101010101010101010101EA +:10F6100001010101010101010101010101010101DA +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010101010101010101017A +:10F68000010101010101010101010101010101016A +:10F69000010101010101010101010101010101015A +:10F6A000010101010101010101010101010101014A +:10F6B000010101010101010101010101010101013A +:10F6C000010101010101010101010101010101012A +:10F6D000010101010101010101010101010101011A +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010101010101010101010139 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101000000000000000000EA +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:020000023000CC +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000000000000000000000CF +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000020202020202020202D8 +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202024A +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020202020202020202021A +:1006C000020202020202020202020202020202020A +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:100770000202020202020202020202020202020259 +:100780000202020202020202020202020202020249 +:100790000202020202020202020202020202020239 +:1007A0000202020202020202020202020202020229 +:1007B0000202020202020202020202020202020219 +:1007C0000202020202020202020202020202020209 +:1007D00002020202020202020202020202020202F9 +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020248 +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B0000202020202020202020202020202020218 +:1008C0000202020202020202020202020202020208 +:1008D00002020202020202020202020202020202F8 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020247 +:100990000202020202020202020202020202020237 +:1009A0000202020202020202020202020202020227 +:1009B0000202020202020202020202020202020217 +:1009C0000202020202020202020202020202020207 +:1009D00002020202020202020202020202020202F7 +:1009E00002020202020202020202020202020202E7 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020202020202020202020226 +:100AB0000202020202020202020202020202020216 +:100AC0000202020202020202020202020202020206 +:100AD00002020202020202020202020202020202F6 +:100AE00002020202020202020202020202020202E6 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202020202020202020205 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202000000000000000000CD +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000000000000000000019 +:1017D0000000000000000000000000000000000009 +:1017E00000000000000000000000000000000000F9 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000000000000000000000F8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000000000000000000000F5 +:101BF00000000000000000000000000000000000E5 +:101C0000000000000000005900000000000000017A +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101014B +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:10267000010101010101010101010101010101014A +:10268000010101010101010101010101010101013A +:10269000010101010101010101010101010101012A +:1026A000010101010101010101010101010101011A +:1026B000010101010101010101010101010101010A +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101010101010101010159 +:102770000101010101010101010101010101010149 +:102780000101010101010101010101010101010139 +:102790000101010101010101010101010101010129 +:1027A0000101010101010101010101010101010119 +:1027B0000101010101010101010101010101010109 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010147 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010101010127 +:1029A0000101010101010101010101010101010117 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010146 +:102A80000101010101010101010101010101010136 +:102A90000101010101010101010101010101010126 +:102AA0000101010101010101010101010101010116 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010100B6 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000004 +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000000E1 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000000FF +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000002BC +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:104100000202020202020202020202020202020091 +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000001A5 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101016D +:10533000010101010101010101010101010101015D +:10534000010101010101010101010101010101014D +:10535000010101010101010101010101010101013D +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101010D +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010101010101BD +:1053E00001010101010101010101010101010101AD +:1053F000010101010101010101010101010101019D +:10540000010101010101010101010101010101018C +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101016C +:10543000010101010101010101010101010101015C +:10544000010101010101010101010101010101014C +:10545000010101010101010101010101010101013C +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101010101010101010101BC +:1054E00001010101010101010101010101010101AC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:10553000010101010101010101010101010101015B +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000101010101010101010101010101010169 +:105730000101010101010101010101010101010159 +:105740000101010101010101010101010101010149 +:105750000101010101010101010101010101010139 +:105760000101010101010101010101010101010129 +:105770000101010101010101010101010101010119 +:105780000101010101010101010101010101010109 +:1057900001010101010101010101010101010101F9 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101010101010101010101B9 +:1057E00001010101010101010101010101010101A9 +:1057F0000101010101010101010101010101010199 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010088 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000000000000000000000C7 +:1059E00000000000000000000000000000000000B7 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:10600000000000000000000000000000000000028E +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020063 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:107500000000000000000000000000000000005526 +:107510000000000000000001010101010101010162 +:10752000010101010101010101010101010101014B +:10753000010101010101010101010101010101013B +:10754000010101010101010101010101010101012B +:10755000010101010101010101010101010101011B +:10756000010101010101010101010101010101010B +:1075700001010101010101010101010101010101FB +:1075800001010101010101010101010101010101EB +:1075900001010101010101010101010101010101DB +:1075A00001010101010101010101010101010101CB +:1075B00001010101010101010101010101010101BB +:1075C00001010101010101010101010101010101AB +:1075D000010101010101010101010101010101019B +:1075E000010101010101010101010101010101018B +:1075F000010101010101010101010101010101017B +:10760000010101010101010101010101010101016A +:10761000010101010101010101010101010101015A +:10762000010101010101010101010101010101014A +:10763000010101010101010101010101010101013A +:10764000010101010101010101010101010101012A +:10765000010101010101010101010101010101011A +:10766000010101010101010101010101010101010A +:1076700001010101010101010101010101010101FA +:1076800001010101010101010101010101010101EA +:1076900001010101010101010101010101010101DA +:1076A00001010101010101010101010101010101CA +:1076B00001010101010101010101010101010101BA +:1076C00001010101010101010101010101010101AA +:1076D000010101010101010101010101010101019A +:1076E000010101010101010101010101010101018A +:1076F000010101010101010101010101010101017A +:107700000101010101010101010101010101010169 +:107710000101010101010101010101010101010159 +:107720000101010101010101010101010101010149 +:107730000101010101010101010101010101010139 +:107740000101010101010101010101010101010129 +:107750000101010101010101010101010101010119 +:107760000101010101010101010101010101010109 +:1077700001010101010101010101010101010101F9 +:1077800001010101010101010101010101010101E9 +:1077900001010101010101010101010101010101D9 +:1077A00001010101010101010101010101010101C9 +:1077B00001010101010101010101010101010101B9 +:1077C00001010101010101010101010101010101A9 +:1077D0000101010101010101010101010101010199 +:1077E0000101010101010101010101010101010189 +:1077F0000101010101010101010101010101010179 +:107800000101010101010101010101010101010168 +:107810000101010101010101010101010101010158 +:107820000101010101010101010101010101010148 +:107830000101010101010101010101010101010138 +:107840000101010101010101010101010101010128 +:107850000101010101010101010101010101010118 +:107860000101010101010101010101010101010108 +:1078700001010101010101010101010101010101F8 +:1078800001010101010101010101010101010101E8 +:1078900001010101010101010101010101010101D8 +:1078A00001010101010101010101010101010101C8 +:1078B00001010101010101010101010101010101B8 +:1078C00001010101010101010101010101010101A8 +:1078D0000101010101010101010101010101010198 +:1078E0000101010101010101010101010101010188 +:1078F0000101010101010101010101010101010178 +:107900000101010101010101010101010101010167 +:107910000101010101010101010101010101010157 +:107920000101010101010101010101010101010147 +:107930000101010101010101010101010101010137 +:107940000101010101010101010101010101010127 +:107950000101010101010101010101010101010117 +:107960000101010101010101010101010101010107 +:1079700001010101010101010101010101010101F7 +:1079800001010101010101010101010101010101E7 +:1079900001010101010101010101010101010101D7 +:1079A00001010101010101010101010101010101C7 +:1079B00001010101010101010101010101010101B7 +:1079C00001010101010101010101010101010101A7 +:1079D0000101010101010101010101010101010197 +:1079E0000101010101010101010101010101010187 +:1079F0000101010101010101010101010101010177 +:107A00000101010101010101010101010101010166 +:107A10000101010101010101010101010101010156 +:107A20000101010101010101010101010101010146 +:107A30000101010101010101010101010101010136 +:107A40000101010101010101010101010101010126 +:107A50000101010101010101010101010101010116 +:107A60000101010101010101010101010101010106 +:107A700001010101010101010101010101010101F6 +:107A800001010101010101010101010101010101E6 +:107A900001010101010101010101010101010101D6 +:107AA00001010101010101010101010101010101C6 +:107AB00001010101010101010101010101010101B6 +:107AC00001010101010101010101010101010101A6 +:107AD0000101010101010101010101010101010196 +:107AE0000101010101010101010101010101010186 +:107AF0000101010101010101010101010101010176 +:107B00000101010101010101010101010101010165 +:107B10000101010101010101010101010101010155 +:107B20000101010101010101010101010101010145 +:107B30000101010101010101010101010101010135 +:107B40000101010101010101010101010101010125 +:107B50000101010101010101010101010101010115 +:107B60000101010101010101010101010101010105 +:107B700001010101010101010101010101010101F5 +:107B800001010101010101010101010101010101E5 +:107B900001010101010101010101010101010101D5 +:107BA00001010101010101010101010101010101C5 +:107BB00001010101010101010101010101010101B5 +:107BC00001010101010101010101010101010101A5 +:107BD0000101010101010101010101010101010195 +:107BE0000101010101010101010101010101010185 +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101010101010101010134 +:107C40000101010101010101010101010101010124 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010101010101010101E4 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD0000101010101010101010101010101010194 +:107CE0000101010101010101010101010101010184 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010101010101010101010123 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010101010101010101E3 +:107D900001010101010101010101010101010101D3 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:108410000101010101010100000000000000000055 +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000002020202020202020243 +:108B20000202020202020202020202020202020225 +:108B30000202020202020202020202020202020215 +:108B40000202020202020202020202020202020205 +:108B500002020202020202020202020202020202F5 +:108B600002020202020202020202020202020202E5 +:108B700002020202020202020202020202020202D5 +:108B800002020202020202020202020202020202C5 +:108B900002020202020202020202020202020202B5 +:108BA00002020202020202020202020202020202A5 +:108BB0000202020202020202020202020202020295 +:108BC0000202020202020202020202020202020285 +:108BD0000202020202020202020202020202020275 +:108BE0000202020202020202020202020202020265 +:108BF0000202020202020202020202020202020255 +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202020202020202020202C4 +:108C900002020202020202020202020202020202B4 +:108CA00002020202020202020202020202020202A4 +:108CB0000202020202020202020202020202020294 +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020202020202020202020274 +:108CE0000202020202020202020202020202020264 +:108CF0000202020202020202020202020202020254 +:108D00000202020202020202020202020202020243 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202020202D3 +:108D800002020202020202020202020202020202C3 +:108D900002020202020202020202020202020202B3 +:108DA00002020202020202020202020202020202A3 +:108DB0000202020202020202020202020202020293 +:108DC0000202020202020202020202020202020283 +:108DD0000202020202020202020202020202020273 +:108DE0000202020202020202020202020202020263 +:108DF0000202020202020202020202020202020253 +:108E00000202020202020202020202020202020242 +:108E10000202020202020202020202020202020232 +:108E20000202020202020202020202020202020222 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202020202020202020202C2 +:108E900002020202020202020202020202020202B2 +:108EA00002020202020202020202020202020202A2 +:108EB0000202020202020202020202020202020292 +:108EC0000202020202020202020202020202020282 +:108ED0000202020202020202020202020202020272 +:108EE0000202020202020202020202020202020262 +:108EF0000202020202020202020202020202020252 +:108F00000202020202020202020202020202020241 +:108F10000202020202020202020202020202020231 +:108F20000202020202020202020202020202020221 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202020202020202020202D1 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020202020202020202A1 +:108FB0000202020202020202020202020202020291 +:108FC0000202020202020202020202020202020281 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202020202020261 +:108FF0000202020202020202020202020202020251 +:109000000202020202020202020202020202020240 +:109010000202020202020202020202020202020230 +:109020000202020202020202020202020202020220 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020202020202020202020202A0 +:1090B0000202020202020202020202020202020290 +:1090C0000202020202020202020202020202020280 +:1090D0000202020202020202020202020202020270 +:1090E0000202020202020202020202020202020260 +:1090F0000202020202020202020202020202020250 +:10910000020202020202020202020202020202023F +:10911000020202020202020202020202020202022F +:10912000020202020202020202020202020202021F +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D000020202020202020202020202020202026F +:1091E000020202020202020202020202020202025F +:1091F000020202020202020202020202020202024F +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202020202025E +:1092F000020202020202020202020202020202024E +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202029D +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202020202025D +:1093F000020202020202020202020202020202024D +:10940000020202020202020202020202020202023C +:10941000020202020202020202020202020202022C +:10942000020202020202020202020202020202021C +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020202AC +:1094A000020202020202020202020202020202029C +:1094B000020202020202020202020202020202028C +:1094C000020202020202020202020202020202027C +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202020202020202020202024C +:10950000020202020202020202020202020202023B +:10951000020202020202020202020202020202022B +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020202AB +:1095A000020202020202020202020202020202029B +:1095B000020202020202020202020202020202028B +:1095C000020202020202020202020202020202027B +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020202020202020202022A +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202020202029A +:1096B000020202020202020202020202020202028A +:1096C000020202020202020202020202020202027A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A0000202020202020202020202020202020299 +:1097B0000202020202020202020202020202020289 +:1097C0000202020202020202020202020202020279 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:109810000202020202020202020202020202020228 +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020202020298 +:1098B0000202020202020202020202020202020288 +:1098C0000202020202020202020202020202020278 +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B0000202020202020202020202020202020287 +:1099C0000202020202020202020202020202020277 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020200000000000000000038 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000000000000000000000000000000000F6 +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000000000000000000B6 +:109AB00000000000000000000000000000000000A6 +:109AC0000000000000000000000000000000000096 +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000076 +:109AF0000000000000000000000000000000000066 +:109B00000000000000000000000000000000000055 +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A110000000000000000001010101010101010136 +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010101DD +:10A3700001010101010101010101010101010101CD +:10A3800001010101010101010101010101010101BD +:10A3900001010101010101010101010101010101AD +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010101DC +:10A4700001010101010101010101010101010101CC +:10A4800001010101010101010101010101010101BC +:10A4900001010101010101010101010101010101AC +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800001010101010101010101010101010101BB +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010101010101010101010101010101BA +:10A6900001010101010101010101010101010101AA +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010101B9 +:10A7900001010101010101010101010101010101A9 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB10000101010101010101010101010101010125 +:10AB20000101010101010101010101010101010115 +:10AB30000101010101010101010101010101010105 +:10AB400001010101010101010101010101010101F5 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010101C5 +:10AB800001010101010101010101010101010101B5 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010185 +:10ABC0000101010101010101010101010101010175 +:10ABD0000101010101010101010101010101010165 +:10ABE0000101010101010101010101010101010155 +:10ABF0000101010101010101010101010101010145 +:10AC00000101010101010101010101010101010134 +:10AC10000101010101010101010101010101010124 +:10AC20000101010101010101010101010101010114 +:10AC30000101010101010101010101010101010104 +:10AC400001010101010101010101010101010101F4 +:10AC500001010101010101010101010101010101E4 +:10AC600001010101010101010101010101010101D4 +:10AC700001010101010101010101010101010101C4 +:10AC800001010101010101010101010101010101B4 +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010184 +:10ACC0000101010101010101010101010101010174 +:10ACD0000101010101010101010101010101010164 +:10ACE0000101010101010101010101010101010154 +:10ACF0000101010101010101010101010101010144 +:10AD00000101010101010101010101010101010133 +:10AD10000101010101010101010101010101010123 +:10AD20000101010101010101010101010101010113 +:10AD30000101010101010101010101010101010103 +:10AD400001010101010101010101010101010101F3 +:10AD500001010101010101010101010101010101E3 +:10AD600001010101010101010101010101010101D3 +:10AD700001010101010101010101010101010101C3 +:10AD800001010101010101010101010101010101B3 +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010183 +:10ADC0000101010101010101010101010101010173 +:10ADD0000101010101010101010101010101010163 +:10ADE0000101010101010101010101010101010153 +:10ADF0000101010101010101010101010101010143 +:10AE00000101010101010101010101010101010132 +:10AE10000101010101010101010101010101010122 +:10AE20000101010101010101010101010101010112 +:10AE30000101010101010101010101010101010102 +:10AE400001010101010101010101010101010101F2 +:10AE500001010101010101010101010101010101E2 +:10AE600001010101010101010101010101010101D2 +:10AE700001010101010101010101010101010101C2 +:10AE800001010101010101010101010101010101B2 +:10AE900001010101010101010101010101010101A2 +:10AEA0000101010101010101010101010101010192 +:10AEB0000101010101010101010101010101010182 +:10AEC0000101010101010101010101010101010172 +:10AED0000101010101010101010101010101010162 +:10AEE0000101010101010101010101010101010152 +:10AEF0000101010101010101010101010101010142 +:10AF00000101010101010101010101010101010131 +:10AF10000101010101010101010101010101010121 +:10AF20000101010101010101010101010101010111 +:10AF30000101010101010101010101010101010101 +:10AF400001010101010101010101010101010101F1 +:10AF500001010101010101010101010101010101E1 +:10AF600001010101010101010101010101010101D1 +:10AF700001010101010101010101010101010101C1 +:10AF800001010101010101010101010101010101B1 +:10AF900001010101010101010101010101010101A1 +:10AFA0000101010101010101010101010101010191 +:10AFB0000101010101010101010101010101010181 +:10AFC0000101010101010101010101010101010171 +:10AFD0000101010101010101010101010101010161 +:10AFE0000101010101010101010101010101010151 +:10AFF0000101010101010101010101010101010141 +:10B000000101010101010101010101010101010130 +:10B010000101010101010100000000000000000029 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000000000000000000000000000000000002B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000002020202020202020217 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020202020202020202020202C5 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020255 +:10BBD0000202020202020202020202020202020245 +:10BBE0000202020202020202020202020202020235 +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020251 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202023D +:10C3E000020202020202020202020202020202022D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202023C +:10C4E000020202020202020202020202020202022C +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000020202020202020202020202020202022B +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C61000020202020202020000000000000000000C +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA100000000000000000550000000000000001C0 +:10CA200001010101010101010101010101010101F6 +:10CA300001010101010101010101010101010101E6 +:10CA400001010101010101010101010101010101D6 +:10CA500001010101010101010101010101010101C6 +:10CA600001010101010101010101010101010101B6 +:10CA700001010101010101010101010101010101A6 +:10CA80000101010101010101010101010101010196 +:10CA90000101010101010101010101010101010186 +:10CAA0000101010101010101010101010101010176 +:10CAB0000101010101010101010101010101010166 +:10CAC0000101010101010101010101010101010156 +:10CAD0000101010101010101010101010101010146 +:10CAE0000101010101010101010101010101010136 +:10CAF0000101010101010101010101010101010126 +:10CB00000101010101010101010101010101010115 +:10CB10000101010101010101010101010101010105 +:10CB200001010101010101010101010101010101F5 +:10CB300001010101010101010101010101010101E5 +:10CB400001010101010101010101010101010101D5 +:10CB500001010101010101010101010101010101C5 +:10CB600001010101010101010101010101010101B5 +:10CB700001010101010101010101010101010101A5 +:10CB80000101010101010101010101010101010195 +:10CB90000101010101010101010101010101010185 +:10CBA0000101010101010101010101010101010175 +:10CBB0000101010101010101010101010101010165 +:10CBC0000101010101010101010101010101010155 +:10CBD0000101010101010101010101010101010145 +:10CBE0000101010101010101010101010101010135 +:10CBF0000101010101010101010101010101010125 +:10CC00000101010101010101010101010101010114 +:10CC10000101010101010101010101010101010104 +:10CC200001010101010101010101010101010101F4 +:10CC300001010101010101010101010101010101E4 +:10CC400001010101010101010101010101010101D4 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010101A4 +:10CC80000101010101010101010101010101010194 +:10CC90000101010101010101010101010101010184 +:10CCA0000101010101010101010101010101010174 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010101A3 +:10CD80000101010101010101010101010101010193 +:10CD90000101010101010101010101010101010183 +:10CDA0000101010101010101010101010101010173 +:10CDB0000101010101010101010101010101010163 +:10CDC0000101010101010101010101010101010153 +:10CDD0000101010101010101010101010101010143 +:10CDE0000101010101010101010101010101010133 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010101A2 +:10CE80000101010101010101010101010101010192 +:10CE90000101010101010101010101010101010182 +:10CEA0000101010101010101010101010101010172 +:10CEB0000101010101010101010101010101010162 +:10CEC0000101010101010101010101010101010152 +:10CED0000101010101010101010101010101010142 +:10CEE0000101010101010101010101010101010132 +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400001010101010101010101010101010101D1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700001010101010101010101010101010101A1 +:10CF80000101010101010101010101010101010191 +:10CF90000101010101010101010101010101010181 +:10CFA0000101010101010101010101010101010171 +:10CFB0000101010101010101010101010101010161 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010141 +:10CFE0000101010101010101010101010101010131 +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010101010101010101010110 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010101010101010101010101010101C0 +:10D0600001010101010101010101010101010101B0 +:10D0700001010101010101010101010101010101A0 +:10D080000101010101010101010101010101010190 +:10D090000101010101010101010101010101010180 +:10D0A0000101010101010101010101010101010170 +:10D0B0000101010101010101010101010101010160 +:10D0C0000101010101010101010101010101010150 +:10D0D0000101010101010101010101010101010140 +:10D0E0000101010101010101010101010101010130 +:10D0F0000101010101010101010101010101010120 +:10D10000010101010101010101010101010101010F +:10D1100001010101010101010101010101010101FF +:10D1200001010101010101010101010101010101EF +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010101010101AE +:10D27000010101010101010101010101010101019E +:10D28000010101010101010101010101010101018E +:10D29000010101010101010101010101010101017E +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010101FC +:10D4200001010101010101010101010101010101EC +:10D4300001010101010101010101010101010101DC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101017C +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010101CA +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010101AA +:10D67000010101010101010101010101010101019A +:10D68000010101010101010101010101010101018A +:10D69000010101010101010101010101010101017A +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000010101010101010101010101010101014A +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010101A9 +:10D770000101010101010101010101010101010199 +:10D780000101010101010101010101010101010189 +:10D790000101010101010101010101010101010179 +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000101010101010101010101010101010149 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010100F9 +:10D8200000000000000000000000000000000000F8 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000000000000000000F7 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF100000000000000000000000000000000002FF +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202020202020231 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020202020202020202020211 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020202020202020202020250 +:10E0B0000202020202020202020202020202020240 +:10E0C0000202020202020202020202020202020230 +:10E0D0000202020202020202020202020202020220 +:10E0E0000202020202020202020202020202020210 +:10E0F0000202020202020202020202020202020200 +:10E1000002020202020202020202020202020202EF +:10E1100002020202020202020202020202020202DF +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A000020202020202020202020202020202024F +:10E1B000020202020202020202020202020202023F +:10E1C000020202020202020202020202020202022F +:10E1D000020202020202020202020202020202021F +:10E1E000020202020202020202020202020202020F +:10E1F00002020202020202020202020202020202FF +:10E2000002020202020202020202020202020202EE +:10E2100002020202020202020202020202020202DE +:10E2200002020202020202020202020202020202CE +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E28000020202020202020202020202020202026E +:10E29000020202020202020202020202020202025E +:10E2A000020202020202020202020202020202024E +:10E2B000020202020202020202020202020202023E +:10E2C000020202020202020202020202020202022E +:10E2D000020202020202020202020202020202021E +:10E2E000020202020202020202020202020202020E +:10E2F00002020202020202020202020202020202FE +:10E3000002020202020202020202020202020202ED +:10E3100002020202020202020202020202020202DD +:10E3200002020202020202020202020202020202CD +:10E3300002020202020202020202020202020202BD +:10E3400002020202020202020202020202020202AD +:10E35000020202020202020202020202020202029D +:10E36000020202020202020202020202020202028D +:10E37000020202020202020202020202020202027D +:10E38000020202020202020202020202020202026D +:10E39000020202020202020202020202020202025D +:10E3A000020202020202020202020202020202024D +:10E3B000020202020202020202020202020202023D +:10E3C000020202020202020202020202020202022D +:10E3D000020202020202020202020202020202021D +:10E3E000020202020202020202020202020202020D +:10E3F00002020202020202020202020202020202FD +:10E4000002020202020202020202020202020202EC +:10E4100002020202020202020202020202020202DC +:10E4200002020202020202020202020202020202CC +:10E4300002020202020202020202020202020202BC +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A000020202020202020202020202020202024C +:10E4B000020202020202020202020202020202023C +:10E4C000020202020202020202020202020202022C +:10E4D000020202020202020202020202020202021C +:10E4E000020202020202020202020202020202020C +:10E4F00002020202020202020202020202020202FC +:10E5000002020202020202020202020202020202EB +:10E5100002020202020202020202020202020202DB +:10E5200002020202020202020202020202020202CB +:10E5300002020202020202020202020202020202BB +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A000020202020202020202020202020202024B +:10E5B000020202020202020202020202020202023B +:10E5C000020202020202020202020202020202022B +:10E5D000020202020202020202020202020202021B +:10E5E000020202020202020202020202020202020B +:10E5F00002020202020202020202020202020202FB +:10E6000002020202020202020202020202020202EA +:10E6100002020202020202020202020202020202DA +:10E6200002020202020202020202020202020202CA +:10E6300002020202020202020202020202020202BA +:10E6400002020202020202020202020202020202AA +:10E65000020202020202020202020202020202029A +:10E66000020202020202020202020202020202028A +:10E67000020202020202020202020202020202027A +:10E68000020202020202020202020202020202026A +:10E69000020202020202020202020202020202025A +:10E6A000020202020202020202020202020202024A +:10E6B000020202020202020202020202020202023A +:10E6C000020202020202020202020202020202022A +:10E6D000020202020202020202020202020202021A +:10E6E000020202020202020202020202020202020A +:10E6F00002020202020202020202020202020202FA +:10E7000002020202020202020202020202020202E9 +:10E7100002020202020202020202020202020202D9 +:10E7200002020202020202020202020202020202C9 +:10E7300002020202020202020202020202020202B9 +:10E7400002020202020202020202020202020202A9 +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000202020202020202020202020202020229 +:10E7D0000202020202020202020202020202020219 +:10E7E0000202020202020202020202020202020209 +:10E7F00002020202020202020202020202020202F9 +:10E8000002020202020202020202020202020202E8 +:10E8100002020202020202020202020202020202D8 +:10E8200002020202020202020202020202020202C8 +:10E8300002020202020202020202020202020202B8 +:10E8400002020202020202020202020202020202A8 +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C0000202020202020202020202020202020228 +:10E8D0000202020202020202020202020202020218 +:10E8E0000202020202020202020202020202020208 +:10E8F00002020202020202020202020202020202F8 +:10E9000002020202020202020202020202020202E7 +:10E9100002020202020202020202020202020202D7 +:10E9200002020202020202020202020202020202C7 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202020202020202020202020202F7 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020202020202020202020202020202C6 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020200D5 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000001E9 +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010101010101010101017A +:10F68000010101010101010101010101010101016A +:10F69000010101010101010101010101010101015A +:10F6A000010101010101010101010101010101014A +:10F6B000010101010101010101010101010101013A +:10F6C000010101010101010101010101010101012A +:10F6D000010101010101010101010101010101011A +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010101010101010101010139 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101010101010101010141 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD0000101010101010101010101010101010111 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:020000024000BC +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010100CD +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000002D3 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202020202020202020205 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A000020202020202020202020202020202021A +:1016B000020202020202020202020202020202020A +:1016C00002020202020202020202020202020202FA +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202020202020202020202DA +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A0000202020202020202020202020202020219 +:1017B0000202020202020202020202020202020209 +:1017C00002020202020202020202020202020202F9 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202020202020202020202D9 +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A0000202020202020202020202020202020218 +:1018B0000202020202020202020202020202020208 +:1018C00002020202020202020202020202020202F8 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202020202020202020202D8 +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020200A9 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000000000000000000000F5 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000000000000000B4 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000000000000000000000000000054 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000000000000000000000034 +:101CB0000000000000000000000000000000000024 +:101CC0000000000000000000000000000000000014 +:101CD0000000000000000000000000000000000004 +:101CE00000000000000000000000000000000000F4 +:101CF00000000000000000000000000000000000E4 +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000000C3 +:101D200000000000000000000000000000000000B3 +:101D300000000000000000000000000000000000A3 +:101D40000000000000000000000000000000000093 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000073 +:101D70000000000000000000000000000000000063 +:101D80000000000000000000000000000000000053 +:101D90000000000000000000000000000000000043 +:101DA0000000000000000000000000000000000033 +:101DB0000000000000000000000000000000000023 +:101DC0000000000000000000000000000000000013 +:101DD0000000000000000000000000000000000003 +:101DE00000000000000000000000000000000000F3 +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E300000000000000000000000000000000000A2 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000000000000000000022 +:101EC0000000000000000000000000000000000012 +:101ED0000000000000000000000000000000000002 +:101EE00000000000000000000000000000000000F2 +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F1000000000000000000000000000000000457C +:101F200000000000000000010101010101010101A8 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101014B +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:10267000010101010101010101010101010101014A +:10268000010101010101010101010101010101013A +:10269000010101010101010101010101010101012A +:1026A000010101010101010101010101010101011A +:1026B000010101010101010101010101010101010A +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101010101010101010159 +:102770000101010101010101010101010101010149 +:102780000101010101010101010101010101010139 +:102790000101010101010101010101010101010129 +:1027A0000101010101010101010101010101010119 +:1027B0000101010101010101010101010101010109 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:1029200001010101010101000000000000000000A0 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000000E6 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000004 +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000000E1 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:10302000000000000000000202020202020202028E +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020200000000000000000088 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:104320000000000000000001010101010101010184 +:10433000010101010101010101010101010101016D +:10434000010101010101010101010101010101015D +:10435000010101010101010101010101010101014D +:10436000010101010101010101010101010101013D +:10437000010101010101010101010101010101012D +:10438000010101010101010101010101010101011D +:10439000010101010101010101010101010101010D +:1043A00001010101010101010101010101010101FD +:1043B00001010101010101010101010101010101ED +:1043C00001010101010101010101010101010101DD +:1043D00001010101010101010101010101010101CD +:1043E00001010101010101010101010101010101BD +:1043F00001010101010101010101010101010101AD +:10440000010101010101010101010101010101019C +:10441000010101010101010101010101010101018C +:10442000010101010101010101010101010101017C +:10443000010101010101010101010101010101016C +:10444000010101010101010101010101010101015C +:10445000010101010101010101010101010101014C +:10446000010101010101010101010101010101013C +:10447000010101010101010101010101010101012C +:10448000010101010101010101010101010101011C +:10449000010101010101010101010101010101010C +:1044A00001010101010101010101010101010101FC +:1044B00001010101010101010101010101010101EC +:1044C00001010101010101010101010101010101DC +:1044D00001010101010101010101010101010101CC +:1044E00001010101010101010101010101010101BC +:1044F00001010101010101010101010101010101AC +:10450000010101010101010101010101010101019B +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101011B +:10459000010101010101010101010101010101010B +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101010101010101010101EB +:1045C00001010101010101010101010101010101DB +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:10468000010101010101010101010101010101011A +:10469000010101010101010101010101010101010A +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010101EA +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D2000010101010101010000000000000000007C +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000202020202020202026A +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202020202020202020202EC +:1054A00002020202020202020202020202020202DC +:1054B00002020202020202020202020202020202CC +:1054C00002020202020202020202020202020202BC +:1054D00002020202020202020202020202020202AC +:1054E000020202020202020202020202020202029C +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020202020202020202020202020202DB +:1055B00002020202020202020202020202020202CB +:1055C00002020202020202020202020202020202BB +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020202020202020202020202020202027A +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020202020202020202020202020202DA +:1056B00002020202020202020202020202020202CA +:1056C00002020202020202020202020202020202BA +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020202020202020202D8 +:1058B00002020202020202020202020202020202C8 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020202020202020202D7 +:1059B00002020202020202020202020202020202C7 +:1059C00002020202020202020202020202020202B7 +:1059D00002020202020202020202020202020202A7 +:1059E0000202020202020202020202020202020297 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A40000202020202020202020202020202020236 +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002020202020202020202020202020202E6 +:105AA00002020202020202020202020202020202D6 +:105AB00002020202020202020202020202020202C6 +:105AC00002020202020202020202020202020202B6 +:105AD00002020202020202020202020202020202A6 +:105AE0000202020202020202020202020202020296 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020202020202020202020202020202E5 +:105BA00002020202020202020202020202020202D5 +:105BB00002020202020202020202020202020202C5 +:105BC00002020202020202020202020202020202B5 +:105BD00002020202020202020202020202020202A5 +:105BE0000202020202020202020202020202020295 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020202020202020202020202020202E4 +:105CA00002020202020202020202020202020202D4 +:105CB00002020202020202020202020202020202C4 +:105CC00002020202020202020202020202020202B4 +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202020202020202020294 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020202020202020202020202E3 +:105DA00002020202020202020202020202020202D3 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020202020202020202B3 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202020202020202020293 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020200000000000000000064 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000000000000000000008F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000003B000000000000000130 +:10643000010101010101010101010101010101014C +:10644000010101010101010101010101010101013C +:10645000010101010101010101010101010101012C +:10646000010101010101010101010101010101011C +:10647000010101010101010101010101010101010C +:1064800001010101010101010101010101010101FC +:1064900001010101010101010101010101010101EC +:1064A00001010101010101010101010101010101DC +:1064B00001010101010101010101010101010101CC +:1064C00001010101010101010101010101010101BC +:1064D00001010101010101010101010101010101AC +:1064E000010101010101010101010101010101019C +:1064F000010101010101010101010101010101018C +:10650000010101010101010101010101010101017B +:10651000010101010101010101010101010101016B +:10652000010101010101010101010101010101015B +:10653000010101010101010101010101010101014B +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010101010101010101FB +:1065900001010101010101010101010101010101EB +:1065A00001010101010101010101010101010101DB +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101018B +:10660000010101010101010101010101010101017A +:10661000010101010101010101010101010101016A +:10662000010101010101010101010101010101015A +:10663000010101010101010101010101010101014A +:10664000010101010101010101010101010101013A +:10665000010101010101010101010101010101012A +:10666000010101010101010101010101010101011A +:10667000010101010101010101010101010101010A +:1066800001010101010101010101010101010101FA +:1066900001010101010101010101010101010101EA +:1066A00001010101010101010101010101010101DA +:1066B00001010101010101010101010101010101CA +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101010101010101010101AA +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101018A +:106700000101010101010101010101010101010179 +:106710000101010101010101010101010101010169 +:106720000101010101010101010101010101010159 +:106730000101010101010101010101010101010149 +:106740000101010101010101010101010101010139 +:106750000101010101010101010101010101010129 +:106760000101010101010101010101010101010119 +:106770000101010101010101010101010101010109 +:1067800001010101010101010101010101010101F9 +:1067900001010101010101010101010101010101E9 +:1067A00001010101010101010101010101010101D9 +:1067B00001010101010101010101010101010101C9 +:1067C00001010101010101010101010101010101B9 +:1067D00001010101010101010101010101010101A9 +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010178 +:106810000101010101010101010101010101010168 +:106820000101010101010101010101010101010158 +:106830000101010101010101010101010101010148 +:106840000101010101010101010101010101010138 +:106850000101010101010101010101010101010128 +:106860000101010101010101010101010101010118 +:106870000101010101010101010101010101010108 +:1068800001010101010101010101010101010101F8 +:1068900001010101010101010101010101010101E8 +:1068A00001010101010101010101010101010101D8 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010147 +:106940000101010101010101010101010101010137 +:106950000101010101010101010101010101010127 +:106960000101010101010101010101010101010117 +:106970000101010101010101010101010101010107 +:1069800001010101010101010101010101010101F7 +:1069900001010101010101010101010101010101E7 +:1069A00001010101010101010101010101010101D7 +:1069B00001010101010101010101010101010101C7 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101010101010101010101A7 +:1069E0000101010101010101010101010101010197 +:1069F0000101010101010101010101010101010187 +:106A00000101010101010101010101010101010176 +:106A10000101010101010101010101010101010166 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000101010101010101010101010101010136 +:106A50000101010101010101010101010101010126 +:106A60000101010101010101010101010101010116 +:106A70000101010101010101010101010101010106 +:106A800001010101010101010101010101010101F6 +:106A900001010101010101010101010101010101E6 +:106AA00001010101010101010101010101010101D6 +:106AB00001010101010101010101010101010101C6 +:106AC00001010101010101010101010101010101B6 +:106AD00001010101010101010101010101010101A6 +:106AE0000101010101010101010101010101010196 +:106AF0000101010101010101010101010101010186 +:106B00000101010101010101010101010101010175 +:106B10000101010101010101010101010101010165 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B70000101010101010101010101010101010105 +:106B800001010101010101010101010101010101F5 +:106B900001010101010101010101010101010101E5 +:106BA00001010101010101010101010101010101D5 +:106BB00001010101010101010101010101010101C5 +:106BC00001010101010101010101010101010101B5 +:106BD00001010101010101010101010101010101A5 +:106BE0000101010101010101010101010101010195 +:106BF0000101010101010101010101010101010185 +:106C00000101010101010101010101010101010174 +:106C10000101010101010101010101010101010164 +:106C20000101010101010101010101010101010055 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000025C +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020038 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000014C +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010101010101010101010107 +:1089600001010101010101010101010101010101F7 +:1089700001010101010101010101010101010101E7 +:1089800001010101010101010101010101010101D7 +:1089900001010101010101010101010101010101C7 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010036 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000023D +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D000020202020202020202020202020202026F +:1091E000020202020202020202020202020202025F +:1091F000020202020202020202020202020202024F +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202020202025E +:1092F000020202020202020202020202020202024E +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202029D +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202020202025D +:1093F000020202020202020202020202020202024D +:10940000020202020202020202020202020202023C +:10941000020202020202020202020202020202022C +:10942000020202020202020202020202020202021C +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020202AC +:1094A000020202020202020202020202020202029C +:1094B000020202020202020202020202020202028C +:1094C000020202020202020202020202020202027C +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202020202020202020202024C +:10950000020202020202020202020202020202023B +:10951000020202020202020202020202020202022B +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020202AB +:1095A000020202020202020202020202020202029B +:1095B000020202020202020202020202020202028B +:1095C000020202020202020202020202020202027B +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020202020202020202022A +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202020202029A +:1096B000020202020202020202020202020202028A +:1096C000020202020202020202020202020202027A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A0000202020202020202020202020202020299 +:1097B0000202020202020202020202020202020289 +:1097C0000202020202020202020202020202020279 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:109810000202020202020202020202020202020228 +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020202020298 +:1098B0000202020202020202020202020202020288 +:1098C0000202020202020202020202020202020278 +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020019 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000000B7 +:1099B00000000000000000000000000000000000A7 +:1099C0000000000000000000000000000000000097 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0000000000000000000000000000000000067 +:109A00000000000000000000000000000000000056 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000000000000000000000000000000000F6 +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000000000000000000B6 +:109AB00000000000000000000000000000000000A6 +:109AC0000000000000000000000000000000000096 +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000076 +:109AF0000000000000000000000000000000000066 +:109B00000000000000000000000000000000000055 +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F200000000000000000000000000000000039F8 +:109F30000000000000000001010101010101010118 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010101DD +:10A3700001010101010101010101010101010101CD +:10A3800001010101010101010101010101010101BD +:10A3900001010101010101010101010101010101AD +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010101DC +:10A4700001010101010101010101010101010101CC +:10A4800001010101010101010101010101010101BC +:10A4900001010101010101010101010101010101AC +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800001010101010101010101010101010101BB +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010101010101010101010101010101BA +:10A6900001010101010101010101010101010101AA +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010100000000000000000012 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000058 +:10A900000000000000000000000000000000000047 +:10A910000000000000000000000000000000000037 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000000000077 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000046 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000002020202020202020201 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202000000000000000000FD +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD300000000000000000010101010101010101FA +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101010101010101010101B3 +:10BD800001010101010101010101010101010101A3 +:10BD90000101010101010101010101010101010193 +:10BDA0000101010101010101010101010101010183 +:10BDB0000101010101010101010101010101010173 +:10BDC0000101010101010101010101010101010163 +:10BDD0000101010101010101010101010101010153 +:10BDE0000101010101010101010101010101010143 +:10BDF0000101010101010101010101010101010133 +:10BE00000101010101010101010101010101010122 +:10BE10000101010101010101010101010101010112 +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101010101010101010101B2 +:10BE800001010101010101010101010101010101A2 +:10BE90000101010101010101010101010101010192 +:10BEA0000101010101010101010101010101010182 +:10BEB0000101010101010101010101010101010172 +:10BEC0000101010101010101010101010101010162 +:10BED0000101010101010101010101010101010152 +:10BEE0000101010101010101010101010101010142 +:10BEF0000101010101010101010101010101010132 +:10BF00000101010101010101010101010101010121 +:10BF10000101010101010101010101010101010111 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101010101010101010101B1 +:10BF800001010101010101010101010101010101A1 +:10BF90000101010101010101010101010101010191 +:10BFA0000101010101010101010101010101010181 +:10BFB0000101010101010101010101010101010171 +:10BFC0000101010101010101010101010101010161 +:10BFD0000101010101010101010101010101010151 +:10BFE0000101010101010101010101010101010141 +:10BFF0000101010101010101010101010101010131 +:10C000000101010101010101010101010101010120 +:10C010000101010101010101010101010101010110 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101010101010101010101B0 +:10C0800001010101010101010101010101010101A0 +:10C090000101010101010101010101010101010190 +:10C0A0000101010101010101010101010101010180 +:10C0B0000101010101010101010101010101010170 +:10C0C0000101010101010101010101010101010160 +:10C0D0000101010101010101010101010101010150 +:10C0E0000101010101010101010101010101010140 +:10C0F0000101010101010101010101010101010130 +:10C10000010101010101010101010101010101011F +:10C11000010101010101010101010101010101010F +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010101010101DF +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A000010101010101010101010101010101017F +:10C1B000010101010101010101010101010101016F +:10C1C000010101010101010101010101010101015F +:10C1D000010101010101010101010101010101014F +:10C1E000010101010101010101010101010101013F +:10C1F000010101010101010101010101010101012F +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101010101010101010101CE +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A000010101010101010101010101010101017E +:10C2B000010101010101010101010101010101016E +:10C2C000010101010101010101010101010101015E +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010101010101ED +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101010101010101010101CD +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010101010101010101017D +:10C3B000010101010101010101010101010101016D +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101010C +:10C4200001010101010101010101010101010101FC +:10C4300001010101010101010101010101010101EC +:10C4400001010101010101010101010101010101DC +:10C4500001010101010101010101010101010101CC +:10C4600001010101010101010101010101010101BC +:10C4700001010101010101010101010101010101AC +:10C48000010101010101010101010101010101019C +:10C49000010101010101010101010101010101018C +:10C4A000010101010101010101010101010101017C +:10C4B000010101010101010101010101010101016C +:10C4C000010101010101010101010101010101015C +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010101010101010101013C +:10C4F000010101010101010101010101010101012C +:10C50000010101010101010101010101010101011B +:10C51000010101010101010101010101010101010B +:10C5200001010101010101010101010101010101FB +:10C5300001010101010101000000000000000000F4 +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000020202020202020202E3 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020233 +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202020202020202020202020213 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020202020252 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020232 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202020202020202020202020212 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020231 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202020202020202020202020211 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202020202020202020202020202020230 +:10D0E0000202020202020202020202020202020220 +:10D0F0000202020202020202020202020202020210 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D17000020202020202020202020202020202028F +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020202020202020202020202023F +:10D1D000020202020202020202020202020202022F +:10D1E000020202020202020202020202020202021F +:10D1F000020202020202020202020202020202020F +:10D2000002020202020202020202020202020202FE +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D000020202020202020202020202020202022E +:10D2E000020202020202020202020202020202021E +:10D2F000020202020202020202020202020202020E +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020202000000000000000000DF +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D810000000000000000000000000000000000008 +:10D8200000000000000000000000000000000000F8 +:10D83000000000000000003F0000000000000001A8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010101010101010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010147 +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010101010101010101010146 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF0000101010101010101010101010101010115 +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010184 +:10DC90000101010101010101010101010101010174 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010101010101010101010114 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010101010101010101010173 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE90000101010101010101010101010101010172 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010100D1 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D0000000000000000000000000000000000040 +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000002D7 +:10E7400002020202020202020202020202020202A9 +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000202020202020202020202020202020229 +:10E7D0000202020202020202020202020202020219 +:10E7E0000202020202020202020202020202020209 +:10E7F00002020202020202020202020202020202F9 +:10E8000002020202020202020202020202020202E8 +:10E8100002020202020202020202020202020202D8 +:10E8200002020202020202020202020202020202C8 +:10E8300002020202020202020202020202020202B8 +:10E8400002020202020202020202020202020202A8 +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C0000202020202020202020202020202020228 +:10E8D0000202020202020202020202020202020218 +:10E8E0000202020202020202020202020202020208 +:10E8F00002020202020202020202020202020202F8 +:10E9000002020202020202020202020202020202E7 +:10E9100002020202020202020202020202020202D7 +:10E9200002020202020202020202020202020202C7 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202020202020202020202020202F7 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020202020202020202020202020202C6 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020203 +:10EDF00002020202020202020202020202020202F3 +:10EE000002020202020202020202020202020202E2 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202020202020202020202F2 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020200B3 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000001C6 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101010101010101010141 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD0000101010101010101010101010101010111 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:020000025000AC +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010100B0 +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000002B6 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020248 +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B0000202020202020202020202020202020218 +:1008C0000202020202020202020202020202020208 +:1008D00002020202020202020202020202020202F8 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020247 +:100990000202020202020202020202020202020237 +:1009A0000202020202020202020202020202020227 +:1009B0000202020202020202020202020202020217 +:1009C0000202020202020202020202020202020207 +:1009D00002020202020202020202020202020202F7 +:1009E00002020202020202020202020202020202E7 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020202020202020202020226 +:100AB0000202020202020202020202020202020216 +:100AC0000202020202020202020202020202020206 +:100AD00002020202020202020202020202020202F6 +:100AE00002020202020202020202020202020202E6 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202020202020202020205 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020092 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000000000000000000001C +:1014D000000000000000000000000000000000000C +:1014E00000000000000000000000000000000000FC +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:101730000000000000000000000000000000007039 +:10174000170500000000007835050000000000804B +:101750004F050000000000886605000000000090B2 +:101760007D0500000000009892050000000000A028 +:10177000A5050000000000A8B6050000000000B0AC +:10178000C6050000000000B8D6050000000000C03B +:10179000E5050000000000C8F0050000000000D0D2 +:1017A000FF050000000000D8080600000000001E31 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000100000000000000000018 +:1017D0000000000000000000000000000000000009 +:1017E00000000000000000000000000000000000F9 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000002020000000000000034 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000100000000000000000017 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000000000000000000000F8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000002020001000000000032 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000010100000000000000000015 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA000000000000000000202020200010100012B +:101AB0000000000000000000000000000000000026 +:101AC0000000000000010100000000000000000014 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000002020202010101000129 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000010100000000000000000013 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000000000000000000000F5 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000000000000000B4 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000000000000000000000000000054 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000002020202020101000127 +:101CB0000001000000000000000000000000000023 +:101CC0000000000000010100000000000000000012 +:101CD0000000000000000000000000000000000004 +:101CE00000000000000000000000000000000000F4 +:101CF00000000000000000000000000000000000E4 +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000000C3 +:101D200000000000000000000000000000000000B3 +:101D300000000000000000000000000000000000A3 +:101D40000000000000000000000000000000000093 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000073 +:101D70000000000000000000000000000000000063 +:101D80000000000000000000000000000000000053 +:101D90000000000000000000000000000000000043 +:101DA0000000000000000002020202020201010124 +:101DB0000101000000000000000000000000000021 +:101DC0000000000001010100000000000000000010 +:101DD0000000000000000000000000000000000003 +:101DE00000000000000000000000000000000000F3 +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E300000000000000000000000000000000000A2 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000002020202020202010122 +:101EB0000101000000000000000000000000000020 +:101EC000000000000101010000000000000000000F +:101ED0000000000000000000000000000000000002 +:101EE00000000000000000000000000000000000F2 +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000000000000000000B1 +:101F300000000000000000000000000000000000A1 +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F80000000000000000000000000000000000051 +:101F90000000000000000000000000000000000041 +:101FA0000000000000000002020202020202010121 +:101FB000010101000000000000000000000000001E +:101FC000000000010101010000000000000000000D +:101FD0000000000000000000000000000000000001 +:101FE00000000000000000000000000000000000F1 +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000000000000000000B0 +:1020300000000000000000000000000000000000A0 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A000000000000000000202020202020202021E +:1020B000010101000000000000000000000000001D +:1020C000000000010101010000000000000000000C +:1020D0000000000000000000000000000000000000 +:1020E00000000000000000000000000000000000F0 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000202020202020202021D +:1021B000010101000000000000000000000000001C +:1021C000000001010101010000000000000000000A +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000202020202020202021C +:1022B000020101000000000000000000000000001A +:1022C0000001010101010100000000000000000008 +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000202020202020202021B +:1023B0000202010100000000000000000000000017 +:1023C0000001010101010100000000000000000007 +:1023D00000000000000000000000000000000000FD +:1023E00000000000000000000000000000000000ED +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000202020202020202021A +:1024B0000202010100000000000000000000000016 +:1024C0000001010101010100000000000000000006 +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A0000000000000000002020202020202020219 +:1025B0000202020101010000000000000000000012 +:1025C0000101010101010100000000000000000004 +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A0000000000000000002020202020202020218 +:1026B0000202020101010000000000000000000110 +:1026C0000101010101010100000000000000000003 +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000002020202020202020217 +:1027B000020202010101000000000000000000010F +:1027C0000101010101010100000000000000000002 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000002020202020202020216 +:1028B000020202020101000000000000000000010D +:1028C0000101010101010100000000000000000001 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000000E8 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000002020202020202020215 +:1029B000020202020101000000000000000001010B +:1029C0000101010101010100000000000000000000 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000002020202020202020214 +:102AB0000202020202010000000000000001010108 +:102AC00001010101010101000000000000000000FF +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000000E6 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000002020202020202020213 +:102BB0000202020202010000000000000001010107 +:102BC00001010101010101000000000000000000FE +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000002020202020202020212 +:102CB0000202020202020000000000000101010104 +:102CC00001010101010101000000000000000000FD +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000002020202020202020211 +:102DB0000202020202020000000000000101010103 +:102DC00001010101010101000000000000000000FC +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000002020202020202020210 +:102EB0000202020202020000000000000101010102 +:102EC00001010101010101000000000000000000FB +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA000000000000000000202020202020202020F +:102FB0000202020202020000000000010101010100 +:102FC00001010101010101000000000000000000FA +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000000E1 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A000000000000000000202020202020202020E +:1030B00002020202020200000000000101010101FF +:1030C00001010101010101000000000000000000F9 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000202020202020202020D +:1031B00002020202020200000000010101010101FD +:1031C00001010101010101000000000000000000F8 +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000202020202020202020C +:1032B00002020202020200000001010101010101FB +:1032C00001010101010101000000000000000000F7 +:1032D00000000000000000000000000000000000EE +:1032E00000000000000000000000000000000000DE +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000202020202020202020B +:1033B00002020202020200000001010101010101FA +:1033C00001010101010101000000000000000000F6 +:1033D00000000000000000000000000000000000ED +:1033E00000000000000000000000000000000000DD +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000202020202020202020A +:1034B0000202020202020000000000000000000000 +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000000EC +:1034E00000000000000000000000000000000000DC +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000001A0000000000000000F1 +:1035C00000000000000000000000000000000100FA +:1035D00000000000000000000000000000000000EB +:1035E00000000000000000000000000000000000DB +:1035F00000000000000000000000000000000000CB +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A0000000000000000000000000000000000218 +:1036B0000200000000000000000000000000000008 +:1036C00000000000000000000000000000000100F9 +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000217 +:1037B0000200000001000000000000000000000006 +:1037C00000000000000000000000000000000100F8 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000216 +:1038B0000202010001010000000000000000000001 +:1038C00000000000000000000000000001010100F5 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000215 +:1039B00002020200010100000000000000000000FF +:1039C00000000000000000000000000001010100F4 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000214 +:103AB00002020201010101000000000000000000FC +:103AC00000000000000000000000000001010100F3 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000213 +:103BB00002020202010101000000000000000000FA +:103BC00000000000000000000000000001010100F2 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000212 +:103CB00002020202020101000000000000000000F8 +:103CC00000000000000000000000010101010100EF +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000211 +:103DB00002020202020201010100000000000000F4 +:103DC00000000000000000000000010101010100EE +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000210 +:103EB00002020202020202010101010001000000EF +:103EC00000000000000000000001010101010100EC +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA000000000000000000000000000000000020F +:103FB00002020202020202010101010001000000EE +:103FC00000000000000000000101010101010100EA +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A000000000000000000000000000000000020E +:1040B00002020202020202020101010001000000EC +:1040C00000000000000000000101010101010100E9 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000020D +:1041B00002020202020202020201010001000000EA +:1041C00000000000000000010101010101010100E7 +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000020C +:1042B00002020202020202020202010101000000E7 +:1042C00000000000000101010101010101010100E4 +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000020B +:1043B00002020202020202020202020101000000E5 +:1043C00000000000010101010101010101010100E2 +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000020A +:1044B00002020202020202020202020101010000E3 +:1044C00000000000010101010101010101010100E1 +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A0000000000000000000000000000000000209 +:1045B00002020202020202020202020202010000E0 +:1045C00000000000010101010101010101010100E0 +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A0000000000000000000000000000000000208 +:1046B00002020202020202020202020202010000DF +:1046C00000000000010101010101010101010100DF +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000207 +:1047B00002020202020202020202020202010000DE +:1047C00000000000010101010101010101010100DE +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000206 +:1048B00002020202020202020202020202020000DC +:1048C00000000001010101010101010101010100DC +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000205 +:1049B00002020202020202020202020202020000DB +:1049C00000000001010101010101010101010100DB +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000204 +:104AB00002020202020202020202020202020000DA +:104AC00000000101010101010101010101010100D9 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000203 +:104BB00002020202020202020202020202020000D9 +:104BC00000000101010101010101010101010100D8 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000202 +:104CB00002020202020202020202020202020000D8 +:104CC00000010101010101010101010101010100D6 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000201 +:104DB00002020202020202020202020202020000D7 +:104DC00000010101010101010101010101010100D5 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000200 +:104EB00002020202020202020202020202020000D6 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000017DA +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000001000000000000000000D0 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000020000000000000000EE +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000001000000000000000000CF +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000020001000000000000EC +:1051C00000000000000000000000000000000000DF +:1051D00000000000000101000000000000000000CD +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000020201000000000000E9 +:1052C00000000000000000000000000000000000DE +:1052D00000000000010101000000000000000000CB +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000020202000000000000E7 +:1053C00000000000000000000000000000000000DD +:1053D00000000000010101000000000000000000CA +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000020202000000000000E6 +:1054C00000000000000000000000000000000000DC +:1054D00000000000010101000000000000000000C9 +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000020202020100000001E1 +:1055C00000000000000000000000000000000000DB +:1055D00000000001010101000000000000000000C7 +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000020202020200000001DF +:1056C00000000000000000000000000000000000DA +:1056D00000000101010101000000000000000000C5 +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000020202020201010101DB +:1057C00000000000010000000000000000000000D8 +:1057D00000010101010101000000000000000000C3 +:1057E00000000000000000000000000000000000B9 +:1057F00000000000000000000000000000000000A9 +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000020202020202010101D9 +:1058C00000000000010000000000000000000001D6 +:1058D00001010101010101000000000000000000C1 +:1058E00000000000000000000000000000000000B8 +:1058F00000000000000000000000000000000000A8 +:105900000000000000000000000000000000000097 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000020202020202020202D5 +:1059C00001000100010000000000000000000001D3 +:1059D00001010101010101000000000000000000C0 +:1059E00000000000000000000000000000000000B7 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000020202020202020202D4 +:105AC00001010100010100000000000000010101CE +:105AD00001010101010101000000000000000000BF +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000020202020202020202D3 +:105BC00002010100010100000000000000010101CC +:105BD00001010101010101000000000000000000BE +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000020202020202020202D2 +:105CC00002020201010100000000000001010101C7 +:105CD00001010101010101000000000000000000BD +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000020202020202020202D1 +:105DC00002020201020100000000000001010101C5 +:105DD00001010101010101000000000000000000BC +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000020202020202020202D0 +:105EC00002020202020100000000000101010101C2 +:105ED00001010101010101000000000000000000BB +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000020202020202020202CF +:105FC00002020202020200000000000101010101C0 +:105FD00001010101010101000000000000000000BA +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000020202020202020202CE +:1060C00002020202020200000001010101010101BD +:1060D00001010101010101000000000000000000B9 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000000000000000000008F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000020202020202020202CD +:1061C00002020202020200000001010101010101BC +:1061D00001010101010101000000000000000000B8 +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000020202020202020202CC +:1062C00002020202020200000001010101010101BB +:1062D00001010101010101000000000000000000B7 +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000020202020202020202CB +:1063C00002020202020200000101010101010101B9 +:1063D00001010101010101000000000000000000B6 +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000020202020202020202CA +:1064C00002020202020200000101010101010101B8 +:1064D00001010101010101000000000000000000B5 +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000000000000000000000000000000000003B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000020202020202020202C9 +:1065C00002020202020200000000000000000000BF +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:10660000000000000000000000000000000000008A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000170000000000000000B3 +:1066D00000000000000000000000000000000100B9 +:1066E00000000000000000000000000000000000AA +:1066F000000000000000000000000000000000009A +:106700000000000000000000000000000000000089 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000002D7 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000100B8 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000099 +:106800000000000000000000000000000000000088 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000038 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000002D6 +:1068C00001010000000000000000000000000000C6 +:1068D00000000000000000000000000000010100B6 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000098 +:106900000000000000000000000000000000000087 +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000002D5 +:1069C00001010000000000000000000000000000C5 +:1069D00000000000000000000000000000010100B5 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000097 +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000002D4 +:106AC00002020000000000000000000000000000C2 +:106AD00000000000000000000000000001010100B3 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000096 +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000035 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000002D3 +:106BC00002020000000000000000000000000000C1 +:106BD00000000000000000000000000101010100B1 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000002D2 +:106CC00002020200010000000000000000000000BD +:106CD00000000000000000000000010101010100AF +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000002D1 +:106DC00002020200010000000000000000000000BC +:106DD00000000000000000000101010101010100AC +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000002D0 +:106EC00002020202010100000100000000000000B7 +:106ED00000000000000000000101010101010100AB +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000002CF +:106FC00002020202020101000100000000000000B4 +:106FD00000000000000000010101010101010100A9 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000002CE +:1070C00002020202020201000100000000000000B2 +:1070D00000000000000001010101010101010100A7 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000002CD +:1071C00002020202020202000100010000010000AE +:1071D00000000000010101010101010101010100A4 +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000002CC +:1072C00002020202020202010201010100010000A9 +:1072D00000000000010101010101010101010100A3 +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000002CB +:1073C00002020202020202020201010100010000A7 +:1073D00000000000010101010101010101010100A2 +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000002CA +:1074C00002020202020202020202020100010000A4 +:1074D00000000000010101010101010101010100A1 +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000002C9 +:1075C00002020202020202020202020201010000A1 +:1075D000000000010101010101010101010101009F +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000002C8 +:1076C000020202020202020202020202010200009F +:1076D000000000010101010101010101010101009E +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000002C7 +:1077C000020202020202020202020202020200009D +:1077D000010101010101010101010101010101009A +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000002C6 +:1078C000020202020202020202020202020200009C +:1078D0000101010101010101010101010101010099 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000002C5 +:1079C000020202020202020202020202020200009B +:1079D0000101010101010101010101010101010098 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000002C4 +:107AC000020202020202020202020202020200009A +:107AD0000101010101010101010101010101010097 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000002C3 +:107BC0000202020202020202020202020202000099 +:107BD0000101010101010101010101010101010096 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000002C2 +:107CC0000202020202020202020202020202000098 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC000000000000000000000000000000000159E +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000100000000000000000092 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000020000000000000000B0 +:107ED00000000000000000000000000000000000A2 +:107EE000000000000101010000000000000000008F +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000020100000000000000AE +:107FD00000000000000000000000000000000000A1 +:107FE000000000010101010000000000000000008D +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000020100000001000000AC +:1080D00000000000000000000000000000000000A0 +:1080E000000000010101010000000000000000008C +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000020201000001000000A9 +:1081D000000000000000000000000000000000009F +:1081E000000001010101010000000000000000008A +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000020202010101000000A5 +:1082D000000000000000000000000000000000009E +:1082E0000101010101010100000000000000000087 +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000020202010101000000A4 +:1083D000000000000000000000000000000000019C +:1083E0000101010101010100000000000000000086 +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000020202020101010001A0 +:1084D0000000000100000000000000000000010199 +:1084E0000101010101010100000000000000000085 +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C000000000000000000202020202020101019C +:1085D0000100000101010000000000000101010193 +:1085E0000101010101010100000000000000000084 +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C000000000000000000202020202020101019B +:1086D0000100010101010000000000000101010191 +:1086E0000101010101010100000000000000000083 +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C0000000000000000002020202020202010199 +:1087D000010001010101000000000001010101018F +:1087E0000101010101010100000000000000000082 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C0000000000000000002020202020202020296 +:1088D000010001010101000000000001010101018E +:1088E0000101010101010100000000000000000081 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C0000000000000000002020202020202020295 +:1089D000020101010101000000000101010101018A +:1089E0000101010101010100000000000000000080 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC0000000000000000002020202020202020294 +:108AD0000201020201010000000001010101010187 +:108AE000010101010101010000000000000000007F +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC0000000000000000002020202020202020293 +:108BD0000202020202020000000001010101010183 +:108BE000010101010101010000000000000000007E +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC0000000000000000002020202020202020292 +:108CD0000202020202020000010101010101010180 +:108CE000010101010101010000000000000000007D +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC0000000000000000002020202020202020291 +:108DD000020202020202000001010101010101017F +:108DE000010101010101010000000000000000007C +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC0000000000000000002020202020202020290 +:108ED000020202020202000001010101010101017E +:108EE000010101010101010000000000000000007B +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC000000000000000000202020202020202028F +:108FD000020202020202000001010101010101017D +:108FE000010101010101010000000000000000007A +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C000000000000000000202020202020202028E +:1090D000020202020202000001010101010101017C +:1090E0000101010101010100000000000000000079 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000202020202020202028D +:1091D0000202020202020000000000000000000083 +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000001300000000000000007B +:1092E000000000000000000000000000000101007C +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000029B +:1093D000010000000000000000000000000000008C +:1093E000000000000000000000000000000101007B +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000029A +:1094D000010000000000000000000000000000008B +:1094E000000000000000000000000000000101007A +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C0000000000000000000000000000000000299 +:1095D0000101010000000000000000000000000088 +:1095E0000000000000000000000000010101010077 +:1095F000000000000000000000000000000000006B +:10960000000000000000000000000000000000005A +:10961000000000000000000000000000000000004A +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C0000000000000000000000000000000000298 +:1096D0000201010101000000000000000000000084 +:1096E0000000000000000000000001010101010075 +:1096F000000000000000000000000000000000006A +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000049 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000297 +:1097D0000202010101000000000000000000000082 +:1097E0000000000000000001010101010101010071 +:1097F0000000000000000000000000000000000069 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000000000000000000000A8 +:1098C0000000000000000000000000000000000296 +:1098D000020202010100000100000000000000007F +:1098E000000000000000010101010101010101006F +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000000000057 +:109910000000000000000000000000000000000047 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000000B7 +:1099B00000000000000000000000000000000000A7 +:1099C0000000000000000000000000000000000295 +:1099D000020202020100010100000000000100007B +:1099E000000000000101010101010101010101006C +:1099F0000000000000000000000000000000000067 +:109A00000000000000000000000000000000000056 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000000000000000000000000000000000F6 +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000000000000000000B6 +:109AB00000000000000000000000000000000000A6 +:109AC0000000000000000000000000000000000294 +:109AD0000202020202010101000000000001000078 +:109AE000000000000101010101010101010101006B +:109AF0000000000000000000000000000000000066 +:109B00000000000000000000000000000000000055 +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000293 +:109BD0000202020202010101000000000001000077 +:109BE0000000000101010101010101010101010069 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000292 +:109CD0000202020202020202010000000001000072 +:109CE0000000010101010101010101010101010067 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000291 +:109DD0000202020202020202010001000001000070 +:109DE0000000010101010101010101010101010066 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000290 +:109ED000020202020202020202010101000100006C +:109EE0000101010101010101010101010101010063 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC000000000000000000000000000000000028F +:109FD0000202020202020202020202010002000068 +:109FE0000101010101010101010101010101010062 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C000000000000000000000000000000000028E +:10A0D0000202020202020202020202020102000065 +:10A0E0000101010101010101010101010101010061 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000028D +:10A1D0000202020202020202020202020202000063 +:10A1E0000101010101010101010101010101010060 +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000028C +:10A2D0000202020202020202020202020202000062 +:10A2E000010101010101010101010101010101005F +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000028B +:10A3D0000202020202020202020202020202000061 +:10A3E000010101010101010101010101010101005E +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000028A +:10A4D0000202020202020202020202020202000060 +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000116A +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D0000000000000000000010100000000000078 +:10A6E000000000000000000000000000000000006A +:10A6F0000000000000010100000000000000000058 +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000002010101000000000074 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000010100000000000000000057 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000002010101000000000073 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000101010100000000000000000054 +:10A900000000000000000000000000000000000047 +:10A910000000000000000000000000000000000037 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000002020101010000000070 +:10A9E0000000000000000000000000000000000067 +:10A9F0000001010101010100000000000000000051 +:10AA00000000000000000000000000000000000046 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD000000000000000000202020101000000006E +:10AAE0000000000000010000000000000000000164 +:10AAF000010101010101010000000000000000004F +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD000000000000000000202020201000000006C +:10ABE0000000000000010000000000000000010162 +:10ABF000010101010101010000000000000000004E +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000002020202020000000169 +:10ACE0000000000000010000000000000001010160 +:10ACF000010101010101010000000000000000004D +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000002020202020100010166 +:10ADE000000100000001000000000101010101015B +:10ADF000010101010101010000000000000000004C +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000002020202020201010163 +:10AEE0000101000100010000000101010101010157 +:10AEF000010101010101010000000000000000004B +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD000000000000000000202020202020202025F +:10AFE0000101010100010000000101010101010155 +:10AFF000010101010101010000000000000000004A +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D000000000000000000202020202020202025E +:10B0E0000202010100020000010101010101010150 +:10B0F0000101010101010100000000000000000049 +:10B10000000000000000000000000000000000003F +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000202020202020202025D +:10B1E000020202020002000001010101010101014D +:10B1F0000101010101010100000000000000000048 +:10B20000000000000000000000000000000000003E +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000202020202020202025C +:10B2E000020202020102000001010101010101014B +:10B2F0000101010101010100000000000000000047 +:10B30000000000000000000000000000000000003D +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000202020202020202025B +:10B3E0000202020202020000010101010101010149 +:10B3F0000101010101010100000000000000000046 +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000202020202020202025A +:10B4E0000202020202020000010101010101010148 +:10B4F0000101010101010100000000000000000045 +:10B50000000000000000000000000000000000003B +:10B51000000000000000000000000000000000002B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D0000000000000000002020202020202020259 +:10B5E000020202020202000000000000000000004F +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000001000000000000000004A +:10B6F0000000000000000000000000000000010049 +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000267 +:10B7E0000101010000000000000000000000000056 +:10B7F0000000000000000000000000000101010046 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000266 +:10B8E0000101010100000000000000000000000054 +:10B8F0000000000000000000000000010101010044 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000265 +:10B9E0000201010100000000000000000000000052 +:10B9F0000000000000000000000101010101010041 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000264 +:10BAE0000202010100000000000000000000000050 +:10BAF000000000000000000101010101010101003E +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000263 +:10BBE000020202010000000000000000010000004D +:10BBF000000000000001010101010101010101003B +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000262 +:10BCE000020202020100000000000000010000004A +:10BCF0000000000101010101010101010101010038 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000261 +:10BDE0000202020201010000000000000101000047 +:10BDF0000000010101010101010101010101010036 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000260 +:10BEE0000202020202010001000000000101000044 +:10BEF0000000010101010101010101010101010035 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD000000000000000000000000000000000025F +:10BFE0000202020202020101000100000101000040 +:10BFF0000001010101010101010101010101010033 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D000000000000000000000000000000000025E +:10C0E000020202020202020201010001020100003A +:10C0F0000001010101010101010101010101010032 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000025D +:10C1E0000202020202020202020201010202000035 +:10C1F0000101010101010101010101010101010030 +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D000000000000000000000000000000000025C +:10C2E0000202020202020202020202020202000032 +:10C2F000010101010101010101010101010101002F +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000000001D +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000025B +:10C3E0000202020202020202020202020202000031 +:10C3F000010101010101010101010101010101002E +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000025A +:10C4E0000202020202020202020202020202000030 +:10C4F000010101010101010101010101010101002D +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D0000000000000000000000000000000000259 +:10C5E000020202020202020202020202020200002F +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000103A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000100000000000000000028 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000002000001000100000045 +:10C7F0000000000000000000000000000000000039 +:10C800000000010101010100000000000000000023 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000002010101010100010040 +:10C8F0000000000000000000000000000000000038 +:10C900000000010101010100000000000000000022 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E000000000000000000201010101010001003F +:10C9F0000000010101010000000000000000000033 +:10CA0000010101010101010000000000000000001F +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE000000000000000000202010101010001003D +:10CAF0000000010101010000000000000000010130 +:10CB0000010101010101010000000000000000001E +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000002020202010101010039 +:10CBF000010001010101000000000000010101012C +:10CC0000010101010101010000000000000000001D +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000054 +:10CCE0000000000000000002020202020201010135 +:10CCF000010001010101000000000001010101012A +:10CD0000010101010101010000000000000000001C +:10CD10000000000000000000000000000000000013 +:10CD20000000000000000000000000000000000003 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000002020202020201020133 +:10CDF0000101010101010000000001010101010127 +:10CE0000010101010101010000000000000000001B +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000002020202020202020131 +:10CEF0000101010101010000000101010101010125 +:10CF0000010101010101010000000000000000001A +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE000000000000000000202020202020202022F +:10CFF000020102020202000000010101010101011F +:10D000000101010101010100000000000000000019 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E000000000000000000202020202020202022E +:10D0F000020202020202000001010101010101011C +:10D100000101010101010100000000000000000018 +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000202020202020202022D +:10D1F000020202020202000001010101010101011B +:10D200000101010101010100000000000000000017 +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000202020202020202022C +:10D2F000020202020202000001010101010101011A +:10D300000101010101010100000000000000000016 +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000202020202020202022B +:10D3F0000202020202020000010101010101010119 +:10D400000101010101010100000000000000000015 +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000202020202020202022A +:10D4F0000202020202020000010101010101010118 +:10D500000101010101010100000000000000000014 +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E0000000000000000002020202020202020229 +:10D5F000020202020202000000000000000000001F +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000F00000000000000001B +:10D700000000000000000000000000000001010017 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000237 +:10D7F0000100000000000100000001000001000025 +:10D800000000000000000000000000000001010016 +:10D810000000000000000000000000000000000008 +:10D8200000000000000000000000000000000000F8 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000236 +:10D8F0000101010000000100010001000001000021 +:10D900000000000000000000000001010101010012 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000000000000000000F7 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000235 +:10D9F000020101000000010001000101000100001E +:10DA0000000000000000000001010101010101000F +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000234 +:10DAF000020101000101010001010101000100001A +:10DB0000000000000000010101010101010101000C +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000233 +:10DBF0000202020001010101010101010101000015 +:10DC00000000000001010101010101010101010009 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000232 +:10DCF0000202020101010201010101010101000012 +:10DD00000000000001010101010101010101010008 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000231 +:10DDF000020202020202020102010201010100000C +:10DE00000001010101010101010101010101010004 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000230 +:10DEF0000202020202020202020202020102000007 +:10DF00000001010101010101010101010101010003 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000000000000000000000000051 +:10DFD0000000000000000000000000000000000041 +:10DFE000000000000000000000000000000000022F +:10DFF0000202020202020202020202020202000005 +:10E000000001010101010101010101010101010002 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D0000000000000000000000000000000000040 +:10E0E000000000000000000000000000000000022E +:10E0F0000202020202020202020202020202000004 +:10E100000101010101010101010101010101010000 +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000022D +:10E1F0000202020202020202020202020202000003 +:10E2000001010101010101010101010101010100FF +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000022C +:10E2F0000202020202020202020202020202000002 +:10E3000001010101010101010101010101010100FE +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000022B +:10E3F0000202020202020202020202020202000001 +:10E4000001010101010101010101010101010100FD +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000022A +:10E4F0000202020202020202020202020202000000 +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F0000000000000000000000000000000000B10 +:10E60000000000000000000000000000000000000A +:10E6100000000000000001000000000000000000F9 +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F0000000000000000002000001000000000017 +:10E700000000000000000000000000000000000009 +:10E7100000000000000101000000000000000000F7 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000002020101000000000013 +:10E800000000000000010000000000000000000007 +:10E8100000000101010101000000000000000000F3 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000002020202000000000010 +:10E900000000000000010000000000000000000105 +:10E9100001010101010101000000000000000000F0 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000000000000000000000037 +:10E9E0000000000000000000000000000000000027 +:10E9F000000000000000000202020200000000000F +:10EA00000000000000010000000000000001010102 +:10EA100001010101010101000000000000000000EF +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000000000000000000000036 +:10EAE0000000000000000000000000000000000026 +:10EAF000000000000000000202020202000101000A +:10EB000000000100000100000000000001010101FF +:10EB100001010101010101000000000000000000EE +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000000000000000000000035 +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000002020202020202020104 +:10EC000001000100000200000000010101010101FA +:10EC100001010101010101000000000000000000ED +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000000000000000000000034 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000002020202020202020202 +:10ED000002000201000200000001010101010101F5 +:10ED100001010101010101000000000000000000EC +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000002020202020202020201 +:10EE000002020202000200000001010101010101F1 +:10EE100001010101010101000000000000000000EB +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000002020202020202020200 +:10EF000002020202020200000101010101010101ED +:10EF100001010101010101000000000000000000EA +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF00000000000000000020202020202020202FF +:10F0000002020202020200000000000000000000F4 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F10000000000000000000F0000000000000000F0 +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000010001000000000000000001000000FB +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000010001000000000001000001000000F9 +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000010001000000000001000001000000F8 +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000010001000000000001000001000000F7 +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000001010001000000000001000001000000F5 +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000001020002000000000001000001000000F2 +:10F7100000000000000000000000000001000100E7 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000207 +:10F8000002020102000000000001010001000000EE +:10F8100000000000000000000001000101010100E3 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000206 +:10F9000002020202010202010102010102000000E2 +:10F9100000000000000000000001010101010100E1 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000000000000000000000000000037 +:10F9D0000000000000000000000000000000000027 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000205 +:10FA000002020202020202020102010102000000DF +:10FA100000000000000000000101010101010100DF +:10FA200000000000000000000000000000000000D6 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC0000000000000000000000000000000000036 +:10FAD0000000000000000000000000000000000026 +:10FAE0000000000000000000000000000000000016 +:10FAF0000000000000000000000000000000000204 +:10FB000002020202020202020202020102010000DB +:10FB100000010001000000000101010101010100DC +:10FB200000000000000000000000000000000000D5 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000055 +:10FBB0000000000000000000000000000000000045 +:10FBC0000000000000000000000000000000000035 +:10FBD0000000000000000000000000000000000025 +:10FBE0000000000000000000000000000000000015 +:10FBF0000000000000000000000000000000000203 +:10FC000002020202020202020202020202010000D9 +:10FC100000010001010000010101010101010100D9 +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000000000000000000000000000000000034 +:10FCD0000000000000000000000000000000000024 +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000202 +:10FD000002020202020202020202020202020000D7 +:10FD100001010101010000010101010101010100D6 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000201 +:10FE000002020202020202020202020202020000D6 +:10FE100001010101010101010101010101010100D3 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000200 +:10FF000002020202020202020202020202020000D5 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:0200000260009C +:1000000000000000000000000000000000000009E7 +:1000100000000000000000000000000000000000E0 +:1000200000000000000101000000000000000000CE +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000020100010000000000EB +:1001100000000101000100000000000000000000DC +:1001200000000000010101000000000000000000CC +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000000000000000000020202020101010201E0 +:1002100001010101010100000000000000000000D8 +:1002200000000001010101000000000000000000CA +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000000000000000000020202020202020202DB +:1003100002010201010100000000000000000000D5 +:1003200000010001010101000000000000000000C8 +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000000000000000000020202020202020202DA +:1004100002020202010100000000000000000000D2 +:1004200000010101010101000000000000000000C6 +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000020202020202020202D9 +:1005100002020202020200000000000101010001CB +:1005200001010101010101000000000000000000C4 +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000020202020202020202D8 +:1006100002020202020200000100010101010001C8 +:1006200001010101010101000000000000000000C3 +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000020202020202020202D7 +:1007100002020202020200000101010101010101C5 +:1007200001010101010101000000000000000000C2 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000020202020202020202D6 +:1008100002020202020200000000000000000000CC +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000090000000000000000CE +:1009200000000000000000000000000000000100C6 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000002E4 +:100A100000000100000101000000010000000000D2 +:100A200000000000000000000100000000000100C4 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000002E3 +:100B100002010201000101000101010000000000CA +:100B200000000000000001000100000000010100C1 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000000000000000000002E2 +:100C100002020202020201000101020000010000C2 +:100C200000000000000001010101000001010100BD +:100C300000000000000000000000000000000000B4 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000002E1 +:100D100002020202020202010102020001010000BD +:100D200000000000000101010101010101010100B9 +:100D300000000000000000000000000000000000B3 +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000000000000000000000073 +:100D80000000000000000000000000000000000063 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000000000000000000023 +:100DD0000000000000000000000000000000000013 +:100DE0000000000000000000000000000000000003 +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000002E0 +:100E100002020202020202020202020202020000B6 +:100E200000010001000101010101010101010100B6 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000002DF +:100F100002020202020202020202020202020000B5 +:100F200000010101010101010101010101010100B3 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000002DE +:1010100002020202020202020202020202020000B4 +:1010200001010101010101010101010101010100B1 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000002DD +:1011100002020202020202020202020202020000B3 +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:10121000000000000000000000000000000000507E +:101220001206000000000058620600000000006086 +:10123000AC06000000000068EE0600000000007030 +:1012400031070000000000787107000000000080F6 +:10125000AC07000000000088DF07000000000090DD +:10126000100800000000009841080000000000A0E5 +:1012700072080000000000A8A3080000000000B0F1 +:10128000D4080000000000B805090000000000506C +:10129000000000000000000000000001000000004D +:1012A000000000010100000000000000000000003C +:1012B000000000000000010000000000000000002D +:1012C000000000000000000000000000000000011D +:1012D000000000000000000000000000000000010D +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000010000ED +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000010000000000000000007C +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000010001000000004B +:1013A000000000010100000000000000000000003B +:1013B000000100000000010000000000000000002B +:1013C000000000000000000000000000000000011C +:1013D000000000000000010000000000000000010B +:1013E00001000000000000000000000000000000FC +:1013F00000000000000100000000000000010000EB +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000010000000000000000007B +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:101490000000000000000000000101010000010048 +:1014A000000000010100000000000000000000003A +:1014B000000100000000010000000000000000002A +:1014C000000000000000010000000000000000011A +:1014D000000000000000010000000000000000010A +:1014E00001000000000000000000000001010000F9 +:1014F00000000000000100000000000000010000EA +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000100000000000000000000BA +:1015300000000000000000000000000000000000AB +:101540000000000000000000010100000000000099 +:10155000000000000000000000000000000000008B +:10156000000000000000010000000000000000007A +:10157000000000000000010000000000000000006A +:10158000000000000000000000000000000000005B +:101590000000000000000000000101010100010046 +:1015A0000000000101000000000000000000000039 +:1015B0000001000000000100000000000001000028 +:1015C0000000000000000100000000000000000119 +:1015D0000100010000000100000000000000000107 +:1015E00001000000000000000000000101010000F7 +:1015F00000000000000100000000000000010100E8 +:1016000000000000000100000000000000000000D9 +:1016100000000000000000000000000000000000CA +:1016200000000000000100000000000000000000B9 +:1016300000000000000000000000000000000000AA +:101640000000000000000000010101000000000097 +:101650000000000001000000000000000000000089 +:101660000000000000000100000000000000000079 +:101670000000000000000100000000000000000069 +:10168000000000000000000000000000000000005A +:101690000001000000000000000101010100010044 +:1016A0000000010101000000000000010000000036 +:1016B0000001000000000100000001000001000026 +:1016C0000000000000000100000000000000000118 +:1016D0000100010000000100000000000000000106 +:1016E00001000000000000000000000101010000F6 +:1016F00000010000000100000000000000010101E5 +:1017000000000000000100000000000000000000D8 +:1017100000000000000000000000000000000000C9 +:1017200000000000000100000000000000000000B8 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000010101000000000096 +:101750000000000001000000000000000000000088 +:101760000000000000000100000000000000000078 +:101770000000000000000100000000000000000068 +:101780000000000000000000000000000000000059 +:101790000001010000000001010101010100010040 +:1017A0000000010101000001010100010000000032 +:1017B0000001000000000100000001000101000024 +:1017C0000000000000000100000000000000010116 +:1017D0000100010000000100000000000000000105 +:1017E00001000000000000000000000101010100F4 +:1017F00001010101000100000000000000010101E1 +:1018000000000000000100000000000000000000D7 +:1018100000000000000000000000000000000000C8 +:1018200000000000000100000000000000000000B7 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000010101010000000094 +:101850000000000001000100000000000000000185 +:101860000000000000000100000000000000000077 +:101870000000000000000100000000000000000067 +:101880000000000000000000000000000000000058 +:10189000000101000000000101010101010001003F +:1018A0000000010101000001010100010000000031 +:1018B0000001000100000100000001000101010021 +:1018C0000100000000000100000000000000010114 +:1018D0000100010000000100000000000100000103 +:1018E00001000000000000000000000101010101F2 +:1018F00001010101000100000000000000010101E0 +:1019000000000000000100000000000000000000D6 +:1019100000000000000000000000000000000000C7 +:1019200000000000000100000000000000000000B6 +:1019300000000000000000000000000000000000A7 +:101940000000000000010001010101010000000091 +:101950000000000001000100000000000000000184 +:101960000000000000000100000000000000000076 +:101970000000000000010100000000000000000065 +:101980000000000000000000000000000000000057 +:10199000010101010100000101010101010001003B +:1019A0000000010101000001010100010000000030 +:1019B000000100010000010100000100010101001F +:1019C0000100000000000100000000000000010113 +:1019D0000100010000000100000000000100000102 +:1019E00001000000000000000000000101010101F1 +:1019F00001010101000100000000000000010101DF +:101A000000000001000100000000000000000000D4 +:101A100000000000000100000000000000000000C5 +:101A200000000000000100000000000000000000B5 +:101A300000000000000000000000000000000000A6 +:101A4000000100000001000101010101000000008F +:101A50000000000001000100000000000000000183 +:101A60000000000000000100000000000000000075 +:101A70000001000000010100000000000000000063 +:101A80000000000000000000000000000101000153 +:101A9000010101010100000101010101010001003A +:101AA000000001010100000101010001000000002F +:101AB000000100010100010100000100010101001D +:101AC0000100000000000100000100000000010111 +:101AD0000100010000000101000000000100000100 +:101AE00001000000000000000000000101010101F0 +:101AF00001010101000100000000000001010101DD +:101B000000000001000100000000000000000000D3 +:101B100000000000000100000000000000000000C4 +:101B200000000000010100000000000000000000B3 +:101B300000000000000100000000000000000000A4 +:101B4000010101000001000101010101010100008A +:101B50000000000001000100000000000000000182 +:101B60000100000000000100000000000000000073 +:101B7000010101000101010000000000000000005F +:101B8000000000000000000000000101010101014F +:101B90000101010101000001010101010100010138 +:101BA000000001010100000101010001000000002E +:101BB000000100010100010101010100010101001A +:101BC0000100000000000100000100000000010110 +:101BD00001000100000101010000000001000001FE +:101BE00001000000000000000000000101010101EF +:101BF00001010101000100000000000001010101DC +:101C000000000101010100000000000000000000D0 +:101C100001000000000100000100000000000001C0 +:101C200000000000010100000000000000000000B2 +:101C300000000000000100000101000001000000A0 +:101C40000101010000010001010101010101010088 +:101C50000000000001010100000000000000000180 +:101C60000100000000000100000000000000000072 +:101C7000010101000101010000000000000000005E +:101C8000000000000000000000000101010101014E +:101C90000101010101000001010101010100010137 +:101CA000010001010100000101010001000000002C +:101CB0000101010101000101010101000101010017 +:101CC000010000000000010001010000000001010E +:101CD00001010100000101010000000001000001FC +:101CE00001000000000000000000000101010101EE +:101CF00001010101000100000000000001010101DB +:101D000000000101010100000000000000000000CF +:101D100001010000000100000100000000000001BE +:101D200000000000010101000000000000000000B0 +:101D3000000000000001000001010100010000009E +:101D40000101010000010001010101010101010186 +:101D5000000100000101010000000000000000017E +:101D60000100000001000100000000000000000070 +:101D7000010101000101010000000000000000005D +:101D8000000000000000000000000101010101014D +:101D90000101010101000001010101010101010135 +:101DA0000101010101000001010100010100000029 +:101DB0000101010101000101010101000101010016 +:101DC000010000000000010001010000000001010D +:101DD00001010101000101010000000001000001FA +:101DE00001000100010000000000000101010101EB +:101DF00001010101010100000000010001010101D8 +:101E000000000101010100000000000000000000CE +:101E100001010000000101000101000000000001BB +:101E200000000000010101000000000000000000AF +:101E3000000000000001000001010100010100009C +:101E40000101010000010001010101010101010185 +:101E5000010101010101010000000000000000017A +:101E6000010000000100010000000000000000006F +:101E7000010101000101010000000000000000005C +:101E8000000000000000000000000101010101014C +:101E90000101010101000001010201020101010132 +:101EA0000101010101000002020100020100000025 +:101EB0000101010101000101010101010101010014 +:101EC000010000000000010101010000000101010A +:101ED00001010101000101010000000001010001F8 +:101EE00001000100010000000000000101010101EA +:101EF00001010101010100000000010001010101D7 +:101F000000000101010100000000000000010000CC +:101F100001010000000101000101000000000001BA +:101F200001000001010101000000010100000000AA +:101F3000000000000001000001010100010100009B +:101F40000101010001010101010101010101010182 +:101F50000101010101010100000000000000000179 +:101F6000010000000100010000000000000000006E +:101F7000010101000101010000000000000000005B +:101F8000000100000000000000000101010101014A +:101F90000101010101000001010202020101010130 +:101FA0000101010101000002020200020100000023 +:101FB0000101010101000101010102010101010111 +:101FC0000101000000000101010101000001010107 +:101FD00001010101000101010000000101010001F6 +:101FE00001000100010000000000000101010101E9 +:101FF00001010101010100000000010001010101D6 +:1020000000000101010100000000000000010000CB +:1020100001010000010101000101000000000001B8 +:1020200001010001010101000000010100000000A8 +:102030000000000000010000010101000101000199 +:102040000101010001010101010101010101010181 +:102050000101010101010101000000000001000176 +:10206000010000000100010000000000000100006C +:10207000010101000101010000000000000000005A +:102080000001010101000000000001010101010146 +:10209000010101010100000202020202010101012D +:1020A0000101010101000002020201020100000021 +:1020B000010201010101010201010201010201010C +:1020C0000101000100000101010101000001010105 +:1020D00001010101000101010000000101010001F5 +:1020E00001000100010000000001000101010101E7 +:1020F00001010101010100000000010001010101D5 +:1021000000000101010100000000000000010000CA +:1021100001010000010101000101000100000001B6 +:1021200001010101010101000000010100000000A6 +:102130000000000000010000010101000101010197 +:102140000101010001010101010101010101010180 +:102150000101010101010101000000000001010174 +:10216000010000000100010000000000000100006B +:102170000101010001010100000000000000000059 +:102180000001010101000000000001010101010145 +:10219000010101010100000202020202020102012A +:1021A000010101010100000202020102010100011E +:1021B0000102010101010102020102010202010109 +:1021C0000101000100000101010101000001010203 +:1021D00001010101000101010000000101010101F3 +:1021E00001000100010001000001010101010101E4 +:1021F00001010101010101000000010001010101D3 +:1022000000000101010100000000000000010100C8 +:1022100001010100010101000101000101000001B3 +:1022200001010101010101000101010101000000A2 +:102230000000000000010000010101000101010196 +:10224000010101000101010101010101010101017F +:102250000101010101010101010100000001010171 +:10226000010000000100010000000000000100006A +:102270000101010001010100000000000000000058 +:102280000001010101000000000001010101010144 +:102290000101010101000002020202020201020129 +:1022A000010101010100000202020102010100011D +:1022B0000102010101010102020202010202020106 +:1022C0000101010100000101010101000101010200 +:1022D00001010101000101010000000101010101F2 +:1022E00001010100010001000001010101010101E2 +:1022F00001010101010101010100010001010101D0 +:1023000000000101010100000000000001010101C5 +:1023100001010100010101000101010101000001B1 +:1023200001010101010101000101010101000000A1 +:102330000000000000010000010101010101010194 +:10234000010101010101010101010101010101017D +:10235000010101010101010101010100000101016F +:102360000100000001000100000000000001010068 +:102370000101010101010100000100000000000055 +:102380000001010101000000000001010101010143 +:102390000101010101000002020202020201020128 +:1023A000010101010100000202020102020100011B +:1023B0000102010201010102020202010202020104 +:1023C00002010101000001010202010001010202FB +:1023D00002010101010101020000000101010102ED +:1023E00001010101010001000001010201010101DF +:1023F00001010101010101010100010001010101CF +:1024000000000101010101000000000001010101C3 +:1024100001010101010101000101010101010001AE +:10242000010101010101010001010101010100019E +:102430000000000000010000010101010101010193 +:10244000010101010101010101010101010101017C +:10245000010101010101010101010100000101016E +:102460000100000001000101010100000001010064 +:102470000101010101010100000101000000000053 +:102480000001010101000000000001010101010142 +:102490000101010101000002020202020201020127 +:1024A0000101010201000002020202020201010117 +:1024B0000202010201010102020202020202020101 +:1024C00002010101000001010202010001010202FA +:1024D00002010201010101020100000102010102E9 +:1024E00002010101010001000001010202010101DC +:1024F00001010101010101010101010001020101CC +:1025000000010101010101000001000001010101C0 +:1025100001010101010101000101010101010101AC +:10252000010101010101010001010101010100019D +:102530000000000000010000010101010101010192 +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101000101016C +:102560000100010101000101010101000001010060 +:102570000101010101010100010101000000000051 +:102580000001010101000000000001010101010141 +:102590000101010101000002020202020201020126 +:1025A0000101020202000002020202020201010114 +:1025B00002020202020102020202020202020201FD +:1025C00002010101000001020202010101010202F7 +:1025D00002010201010101020100010102010102E7 +:1025E00002010101010001000001010202020101DA +:1025F00001010101010101010101010001020101CB +:1026000001010101010101000001010001010101BD +:1026100001010101010101000101010101010101AB +:10262000010101010101010101010101010100019B +:102630000001000000010000010101010101010190 +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010001010100010101010100000101005F +:10267000010101010101010001010101000000004F +:102680000001010101000000000001010101010140 +:102690000101010101000002020202020202020223 +:1026A0000101020202010002020202020202010111 +:1026B00002020202020102020202020202020201FC +:1026C00002010101010001020202020101010202F4 +:1026D00002010201010101020101010102010102E5 +:1026E00002010101010001010101010202020101D7 +:1026F00001010101010101010101010001020201C9 +:1027000001010101010101000001010001010101BC +:1027100001010101010101000101010101010101AA +:10272000010101010101010101010101010100019A +:10273000010100000001010001010101010101018D +:102740000101010101010101020101010101010178 +:102750000101010101010101010101010101010169 +:10276000010001010100010101010101000101005D +:10277000010101010101010001010101010100004C +:10278000000101010100000000000101010101013F +:102790000101010101000002020202020202020222 +:1027A000020102020201000202020202020201020E +:1027B00002020202020102020202020202020202FA +:1027C00002010101010001020202020101020202F2 +:1027D00002010201010101020101010202010102E3 +:1027E00002010101010001010101010202020201D5 +:1027F00001010101010101010101010101020201C7 +:1028000001010101010101000001010101010101BA +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101000199 +:10283000010100000001010101010101010101018B +:102840000101010101010101020201010101010176 +:102850000101010101010101010101010101010168 +:10286000010001010100010101010101010101005B +:10287000010101010101010001010101010100004B +:10288000000101010101010000000101010101013C +:102890000101010101000002020202020202020221 +:1028A000020102020201000202020202020202020C +:1028B00002020202020102020202020202020202F9 +:1028C00002020101010002020202020101020202EF +:1028D00002020201010101020101010202020102E0 +:1028E00002010101010001010101010202020201D4 +:1028F00002010101010101010101020102020202C2 +:1029000001010101010101000001010101010101B9 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101000198 +:102930000101010101010101010101010101010187 +:102940000101010101010102020202010101010173 +:102950000101010101010101010101010101010167 +:10296000010001010100010101010101010101005A +:102970000101010101010100010101010101000149 +:10298000000101010101010000000101010101013B +:10299000010101010101010202020202020202021E +:1029A000020202020201000202020202020202020A +:1029B00002020202020102020202020202020202F8 +:1029C00002020102010002020202020102020202EC +:1029D00002020202010102020201010202020102DC +:1029E00002010101010001010102010202020202D1 +:1029F00002020101010101010101020102020202C0 +:102A000001010101010101000001010101010101B8 +:102A100001010101010101010201010101010101A5 +:102A20000101010101010101010101010101000197 +:102A30000101010101010101010101010101010186 +:102A40000101010101010102020202010101010172 +:102A50000101010101010101010101010101010166 +:102A60000101010101000101010101010101010157 +:102A70000101010101010100010101010101010147 +:102A80000101010101010100010101010101010137 +:102A9000010101010101010202020202020202021D +:102AA0000202020202010002020202020202020209 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202010102020202020202020202E8 +:102AD00002020202010102020201020202020202D9 +:102AE00002010201010001010102020202020202CE +:102AF00002020201010101020201020102020202BC +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010201010101010101A4 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101020101010101010184 +:102B40000101010101010102020202020101010170 +:102B50000101010101010101010101010101010165 +:102B60000101010101010101010101010101010155 +:102B70000101010101010101010101010101010145 +:102B80000101010101010100010101010101010136 +:102B9000010101010101010202020202020202021C +:102BA0000202020202010002020202020202020208 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202010102020202020202020202E7 +:102BD00002020202010102020202020202020202D7 +:102BE00002010201010101010102020202020202CC +:102BF00002020202010101020201020102020202BA +:102C000001010101010101010101010101020101B3 +:102C100002010101010101010202010101010101A1 +:102C20000101010101010101010102010101010193 +:102C30000101010101010101020201010101010182 +:102C4000010101010101010202020202010101016F +:102C50000101010101010101010101010101010164 +:102C60000101010101010101010101010101010154 +:102C70000101010101010101010101010101010144 +:102C80000101010101010100010102010101010134 +:102C9000010101010101010202020202020202021B +:102CA0000202020202010002020202020202020207 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202010102020202020202020202E6 +:102CD00002020202010202020202020202020202D5 +:102CE00002010201020101020202020202020202C8 +:102CF00002020202010101020202020102020202B8 +:102D000001010101010101010102010101020101B1 +:102D100002010101010101010202010101010101A0 +:102D20000101010101010101020102020101010190 +:102D30000101010101010101020202010101010180 +:102D4000010101010101010202020202010101016E +:102D50000101010101010102010101010101010162 +:102D60000101010101010101010101010101010153 +:102D70000101010101010101010101010101010143 +:102D80000101010101010100010102020101010132 +:102D9000010101010101010202020202020202021A +:102DA0000202020202010002020202020202020206 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020102020202020202020202E4 +:102DD00002020202020202020202020202020202D3 +:102DE00002020201020101020202020202020202C6 +:102DF00002020202010201020202020102020202B6 +:102E000001010202010101010102020102020201AB +:102E1000020201010101010102020102010101019D +:102E2000010101010101010102020202010101018E +:102E3000010101010101010102020201020101017E +:102E4000010101010101010202020202020101016C +:102E5000010101010101010202010101010101025F +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010100010102020201010130 +:102E90000101010101010102020202020202020219 +:102EA0000202020202010002020202020202020205 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020102020202020202020202E3 +:102ED00002020202020202020202020202020202D2 +:102EE00002020202020101020202020202020202C4 +:102EF00002020202010201020202020102020202B5 +:102F000001010202010101010102020102020201AA +:102F1000020201010101010102020202010101029A +:102F2000010101010101010202020202010101018C +:102F3000010101010101010102020201020101017D +:102F4000010101010101010202020202020201016A +:102F5000010101010101010202020101010101025D +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F8000010101010101010001010202020201012E +:102F90000101010101010102020202020202020218 +:102FA0000202020202010002020202020202020204 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020102020202020202020202E2 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020101020202020202020202C3 +:102FF00002020202020201020202020202020202B2 +:1030000001010202020201020202020202020202A3 +:103010000202010101010101020202020201010298 +:10302000010101010101010202020202020101018A +:10303000010101010101010102020201020201017B +:103040000201010101010102020202020202020167 +:10305000010101010101010202020201010101025B +:10306000020101010101010202010101010101014D +:10307000010101010101010102020101010101013E +:10308000010101010101010001010202020202012C +:103090000101010101010102020202020202020217 +:1030A0000202020202010002020202020202020203 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020102020202020202020202E1 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020101020202020202020202C2 +:1030F00002020202020201020202020202020202B1 +:1031000001010202020201020202020202020202A2 +:103110000202020101010102020202020201010295 +:103120000201010101010102020202020201010188 +:103130000101010101010101020202020202010179 +:103140000202010101010102020202020202020165 +:103150000101010101010102020202010102010259 +:10316000020101010101010202020101010101014B +:10317000020101010101010102020201010101013B +:10318000010101010101010001010202020202022A +:103190000202010101010102020202020202020214 +:1031A0000202020202020002020202020202020201 +:1031B00002020202020202020202020202020202EF +:1031C00002020202020102020202020202020202E0 +:1031D00002020202020202020202020202020202CF +:1031E00002020202020102020202020202020202C0 +:1031F00002020202020201020202020202020202B0 +:1032000002010202020201020202020202020202A0 +:103210000202020102020102020202020202010291 +:103220000201010101020102020202020202010185 +:103230000101010101010102020202020202020176 +:103240000202020101010102020202020202020262 +:103250000101010101010102020202020102020256 +:103260000201010101010102020202010102010148 +:103270000202010101010101020202010101010139 +:103280000101010101010100010102020202020229 +:103290000202020101010102020202020202020212 +:1032A0000202020202020002020202020202020200 +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020102020202020202020202BF +:1032F00002020202020201020202020202020202AF +:10330000020202020202010202020202020202029E +:10331000020202020202010202020202020202028E +:103320000202010102020102020202020202010281 +:103330000101010101010102020202020202020274 +:103340000202020101010102020202020202020261 +:103350000201010102010102020202020102020253 +:103360000201010101010202020202010102010146 +:103370000202020101010101020202020101010136 +:103380000101010101010100020102020202020227 +:103390000202020101010102020202020202020211 +:1033A00002020202020200020202020202020202FF +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020102020202020202020202BE +:1033F00002020202020201020202020202020202AE +:10340000020202020202010202020202020202029D +:10341000020202020202010202020202020202028D +:10342000020202020202010202020202020201027E +:103430000101010101010102020202020202020273 +:103440000202020101010102020202020202020260 +:103450000202010102010102020202020202020250 +:103460000201010101010202020202020102020143 +:103470000202020101010102020202020101010134 +:103480000101010101010100020202020202020225 +:10349000020202020101010202020202020202020F +:1034A00002020202020200020202020202020202FE +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020102020202020202020202BD +:1034F00002020202020201020202020202020202AD +:10350000020202020202010202020202020202029C +:10351000020202020202020202020202020202028B +:10352000020202020202010202020202020201027D +:103530000201010101020102020202020202020270 +:10354000020202010101010202020202020202025F +:10355000020202010201010202020202020202024E +:103560000201010101010202020202020102020142 +:103570000202020101010202020202020201010131 +:103580000102010101010100020202020202020223 +:10359000020202020201010202020202020202020D +:1035A00002020202020200020202020202020202FD +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020102020202020202020202BC +:1035F00002020202020202020202020202020202AB +:10360000020202020202010202020202020202029B +:10361000020202020202020202020202020202028A +:10362000020202020202010202020202020202027B +:10363000020201010102010202020202020202026E +:10364000020202010102010202020202020202025D +:10365000020202020201010202020202020202024C +:10366000020101010201020202020202020202013F +:10367000020202010201020202020202020201012E +:103680000102020101010100020202020202020221 +:10369000020202020201010202020202020202020C +:1036A00002020202020200020202020202020202FC +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:10370000020202020202010202020202020202029A +:103710000202020202020202020202020202020289 +:10372000020202020202010202020202020202027A +:10373000020201010102010202020202020202026D +:10374000020202010202010202020202020202025B +:10375000020202020201020202020202020202024A +:10376000020101010201020202020202020202013E +:10377000020202010202020202020202020201012C +:10378000010202020101010002020202020202021F +:10379000020202020201010202020202020202020B +:1037A00002020202020200020202020202020202FB +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:10383000020202010102010202020202020202026B +:103840000202020202020102020202020202020259 +:103850000202020202010202020202020202020249 +:10386000020102010201020202020202020202013C +:10387000020202010202020202020202020202012A +:10388000010202020201010002020202020202021D +:10389000020202020201010202020202020202020A +:1038A00002020202020200020202020202020202FA +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020201020102020202020202020269 +:103940000202020202020102020202020202020258 +:103950000202020202020202020202020202020247 +:10396000020102020201020202020202020202013A +:103970000202020202020202020202020202020227 +:10398000010202020201010002020202020202021C +:103990000202020202010102020202020202020209 +:1039A00002020202020200020202020202020202F9 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020102020202020202020267 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000201020202010202020202020202020238 +:103A70000202020202020202020202020202020226 +:103A8000020202020201010002020202020202021A +:103A90000202020202010102020202020202020208 +:103AA00002020202020200020202020202020202F8 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020102020202020202020266 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202010202020202020202020236 +:103B70000202020202020202020202020202020225 +:103B80000202020202010100020202020202020219 +:103B90000202020202010102020202020202020207 +:103BA00002020202020200020202020202020202F7 +:103BB00002020201010102020202020202020202E8 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020102020202020202020265 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202010202020202020202020235 +:103C70000202020202020202020202020202020224 +:103C80000202020202010100020202020202020218 +:103C90000202020202010102020202020202020206 +:103CA00002020202020200020202020202020202F6 +:103CB00002010101010101020202020202020202EA +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202010202020202020202020234 +:103D70000202020202020202020202020202020223 +:103D80000202020202010102020202020202020215 +:103D90000202020202010102020202020202020205 +:103DA00002020202020200020202020202020202F5 +:103DB00001010101010101020202020202020202EA +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202010202020202020202020233 +:103E70000202020202020202020202020202020222 +:103E80000202020202010102020202020202020214 +:103E90000202020202010102020202020202020204 +:103EA00002020202020200020202020202020201F5 +:103EB00001010101010101020202020202020202E9 +:103EC00002020201010202020202020202020202D4 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202010202020202020202020232 +:103F70000202020202020202020202020202020221 +:103F80000202020202020102020202020202020212 +:103F90000202020202010102020202020202020203 +:103FA00002020202020200020202020101010101F8 +:103FB00001010101010101020202020202020202E8 +:103FC00001010101010101020202020202020202D8 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202010202020202020202020231 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020102020202020202020201 +:1040A00002020101010100020202020101010101FB +:1040B00001010101010101020202020202010101EA +:1040C00001010101010101020202020202020202D7 +:1040D00002020101010202020202020202020202C3 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:104190000202020202020202020202020202010101 +:1041A0000101010101010001010101010101010100 +:1041B00001010101010101020202020201010101EA +:1041C00001010101010101020202020202020201D7 +:1041D00001010101010101020202020202020202C6 +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:104290000202020202020202020202010101010103 +:1042A00001010101010101010101010101010101FE +:1042B00001010101010101020202010101010101EB +:1042C00001010101010101020202020202020101D7 +:1042D00001010101010101020202020202020202C5 +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202029E +:10430000020202020202020202020202020202028D +:10431000020202020202020202020202020202027D +:10432000020202020202020202020202020202026D +:10433000020202020202020202020202020202025D +:10434000020202020202020202020202020202024D +:10435000020202020202020202020202020202023D +:10436000020202020202020202020202020202022D +:10437000020202020202020202020202020202021D +:10438000020202020202020202020202020202020D +:104390000202020202020202020101010101010104 +:1043A00001010101010101010101010101010101FD +:1043B00001010101010101010101010101010101ED +:1043C00001010101010101020202020202010101D7 +:1043D00001010101010101020202020202020202C4 +:1043E00002020101010201020202020202020202B1 +:1043F000020202020202020202020202020202029D +:10440000020202020202020202020202020202028C +:10441000020202020202020202020202020202027C +:10442000020202020202020202020202020202026C +:10443000020202020202020202020202020202025C +:10444000020202020202020202020202020202024C +:10445000020202020202020202020202020202023C +:10446000020202020202020202020202020202022C +:10447000020202020202020202020202020202021C +:10448000020202020202020202020202020202020C +:104490000202020202020201010101010101010105 +:1044A00001010101010101010101010101010101FC +:1044B00001010101010101010101010101010101EC +:1044C00001010101010101020202020201010101D7 +:1044D00001010101010101020202020202020201C4 +:1044E00001010101010101020202020202020202B3 +:1044F000020202020202020202020202020202029C +:10450000020202020202020202020202020202028B +:10451000020202020202020202020202020202027B +:10452000020202020202020202020202020202026B +:10453000020202020202020202020202020202025B +:10454000020202020202020202020202020202024B +:10455000020202020202020202020202020202023B +:10456000020202020202020202020202020202022B +:10457000020202020202020202020202020202021B +:10458000020202020202020202020202020202020B +:104590000202020202020201010101010101010104 +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101010101010101010101EB +:1045C00001010101010101020101010101010101DA +:1045D00001010101010101020202020201010101C6 +:1045E00001010101010101020202020202020202B2 +:1045F000020202020202020202020202020202029B +:10460000020202020202020202020202020202028A +:10461000020202020202020202020202020202027A +:10462000020202020202020202020202020202026A +:10463000020202020202020202020202020202025A +:10464000020202020202020202020202020202024A +:10465000020202020202020202020202020202023A +:10466000020202020202020202020202020202022A +:10467000020202020202020202020202020202021A +:10468000020202020202020202020202020202020A +:104690000202020202020201010101010101010103 +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010101EA +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101020202020101010101C6 +:1046E00001010101010101020202020202020202B1 +:1046F000020202020202020202020202020202029A +:104700000202020202020202020202020202020289 +:104710000202020202020202020202020202020279 +:104720000202020202020202020202020202020269 +:104730000202020202020202020202020202020259 +:104740000202020202020202020202020202020249 +:104750000202020202020202020202020202020239 +:104760000202020202020202020202020202020229 +:104770000202020202020202020202020202020219 +:104780000202020202020202020202020202020209 +:104790000202020202020201010101010101010102 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010202010101010101C7 +:1047E00001010101010101020202020202020202B0 +:1047F0000202020202020202020202020202020299 +:104800000202020202020202020202020202020288 +:104810000202020202020202020202020202020278 +:104820000202020202020202020202020202020268 +:104830000202020202020202020202020202020258 +:104840000202020202020202020202020202020248 +:104850000202020202020202020202020202020238 +:104860000202020202020202020202020202020228 +:104870000202020202020202020202020202020218 +:104880000202020202020202020202020202020208 +:104890000202020202020201010101010101010101 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101020202020202020202AF +:1048F000010101010102020202020202020202029D +:104900000202020202020202020202020202020287 +:104910000202020202020202020202020202020277 +:104920000202020202020202020202020202020267 +:104930000202020202020202020202020202020257 +:104940000202020202020202020202020202020247 +:104950000202020202020202020202020202020237 +:104960000202020202020202020202020202020227 +:104970000202020202020202020202020202020217 +:104980000202020202020202020202020202020207 +:104990000202020202020201010101010101010100 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101020202020101010101B3 +:1049F000010101010101010202020202020202029E +:104A00000202020202020202020202020202020286 +:104A10000202020202020202020202020202020276 +:104A20000202020202020202020202020202020266 +:104A30000202020202020202020202020202020256 +:104A40000202020202020202020202020202020246 +:104A50000202020202020202020202020202020236 +:104A60000202020202020202020202020202020226 +:104A70000202020202020202020202020202020216 +:104A80000202020202020202020202020202020206 +:104A900002020202020202010101010101010101FF +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101020202020101010101B2 +:104AF00001010101010101020202020202010101A0 +:104B00000202010101020202020202020202020288 +:104B1000010101010102020202020202020202027A +:104B20000202020202020202020202020202020265 +:104B30000202020202020202020202020202020255 +:104B40000202020202020202020202020202020245 +:104B50000202020202020202020202020202020235 +:104B60000202020202020202020202020202020225 +:104B70000202020202020202020202020202020215 +:104B80000202020202020202020202020202020205 +:104B900002020202020202010101010101010101FE +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101020201010101010101B3 +:104BF00001010101010101020202020201010101A0 +:104C0000010101010101010202020202020101018E +:104C1000010101010101010202020202020202027B +:104C20000202020202020202020202020202020264 +:104C30000202020202020202020202020202020254 +:104C40000202020202020202020202020202020244 +:104C50000202020202020202020202020202020234 +:104C60000202020202020202020202020202020224 +:104C70000202020202020202020202020202020214 +:104C80000202020202020202020202020202020204 +:104C900002020202020202010101010101010101FD +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101020202010201010101A0 +:104D0000010101010101010202020202010101018E +:104D1000010101010101010202020202020202027A +:104D20000202020202020202020202020202020263 +:104D30000202020202020202020202020202020253 +:104D40000202020202020202020202020202020243 +:104D50000202020202020202020202020202020233 +:104D60000202020202020202020202020202020223 +:104D70000202020202020202020202020202020213 +:104D80000202020202020202020202020202020203 +:104D900002020202020202010101010101010101FC +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010102020101010101010190 +:104E10000101010101010102020202020202020279 +:104E20000202020202020202020202020202020262 +:104E30000202020202020202020202020202020252 +:104E40000202020202020202020202020202020242 +:104E50000202020202020202020202020202020232 +:104E60000202020202020202020202020202020222 +:104E70000202020202020202020202020202020212 +:104E80000202020202020202020202020202020202 +:104E900002020202020202010101010101010101FB +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010102020202020202020278 +:104F20000202020202020202020202020202020261 +:104F30000202020202020202020202020202020251 +:104F40000202020202020202020202020202020241 +:104F50000202020202020202020202020202020231 +:104F60000202020202020202020202020202020221 +:104F70000202020202020202020202020202020211 +:104F80000202020202020202020202020202020201 +:104F900002020202020202010101010101010101FA +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010102020202020202020277 +:105020000202020202020202020202020202020260 +:105030000202020202020202020202020202020250 +:105040000202020202020202020202020202020240 +:105050000202020202020202020202020202020230 +:105060000202020202020202020202020202020220 +:105070000202020202020202020202020202020210 +:105080000202020202020202020202020202020200 +:1050900002020202020202010101010101010101F9 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:105110000101010101010102020202020202020177 +:105120000101010101010202020202020202020166 +:105130000101010101010202020202020202020255 +:10514000020202020202020202020202020202023F +:10515000020202020202020202020202020202022F +:10516000020202020202020202020202020202021F +:10517000020202020202020202020202020202020F +:1051800002020202020202020202020202020202FF +:1051900002020202020202010101010101010101F8 +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010202020201010101017A +:10522000010101010101010202020101010101016B +:105230000101010101010102020202020202020255 +:10524000020202020202020202020202020202023E +:10525000020202020202020202020202020202022E +:10526000020202020202020202020202020202021E +:10527000020202020202020202020202020202020E +:1052800002020202020202020202020202020202FE +:1052900002020202020202010101010101010101F7 +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010201010101010101017C +:10532000010101010101010101010101010101016D +:105330000101010101010102020202020202020254 +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202020202010101010101010101F6 +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010101010101BD +:1053E00001010101010101010101010101010101AD +:1053F000010101010101010101010101010101019D +:10540000010101010101010101010101010101018C +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101016C +:105430000101010101010102020202020202020253 +:10544000010101020202020202020202020202023F +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202010101010101010101F5 +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101010101010101010101BC +:1054E00001010101010101010101010101010101AC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:105530000101010101010102020202020101010156 +:105540000101010101010102020202020202020242 +:10555000020202020202020202020202020202012C +:10556000010202020202010202020202020202021D +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202010101010101010101F4 +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:105630000101010101010102010101010101010159 +:10564000010101010101010101010101010101014A +:105650000101010101020102020202020201010133 +:10566000010201010102010202020202020202021F +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202010101010101010101F3 +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000101010101010101010101010101010169 +:105730000101010101010101010101010101010159 +:105740000101010101010101010101010101010149 +:105750000101010101010101010101010101010139 +:10576000010101010102010202020202020202021F +:10577000010101020202010202020202020202020D +:1057800002020202020202020202020202020202F9 +:1057900002020202020202010101010101010101F2 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101010101010101010101B9 +:1057E00001010101010101010101010101010101A9 +:1057F0000101010101010101010101010101010199 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010102020202020201010221 +:10587000010101010101010202020202020202020F +:1058800002020202020202020202020202020202F8 +:1058900002020202020202010101010101010101F1 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010187 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:10597000010101010101010202020202020202020E +:105980000201010101020202020201010101010101 +:1059900001010101010202010101010101010101F5 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000101010101010101010101010101010186 +:105A10000101010101010101010101010101010176 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010102010101010101010115 +:105A80000101010101010100010101010101010107 +:105A900001010101010101010101010101010101F6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00001010101010101010101010101010101C6 +:105AD00001010101010101010101010101010101B6 +:105AE00001010101010101010101010101010101A6 +:105AF0000101010101010101010101010101010196 +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010175 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101010101010101010145 +:105B50000101010101010101010101010101010135 +:105B60000101010101010101010101010101010125 +:105B70000101010101010101010101010101010115 +:105B8000010101010101010000000000000000000E +:105B900000000000000000010101010101010101FC +:105BA00001010101010101010101010101010101E5 +:105BB00001010101010101010101010101010101D5 +:105BC00001010101010101010101010101010101C5 +:105BD00001010101010101010101010101010101B5 +:105BE00001010101010101010101010101010101A5 +:105BF0000101010101010101010101010101010195 +:105C00000101010101010101010101010101010184 +:105C10000101010101010101010101010101010174 +:105C20000101010101010101010101010101010164 +:105C30000101010101010101010101010101010154 +:105C40000101010101010101010101010101010144 +:105C50000101010101010101010101010101010134 +:105C60000101010101010101010101010101010124 +:105C70000101010101010101010101010101010114 +:105C8000010101010101010000000000000000000D +:105C900000000000000000010101010101010101FB +:105CA00001010101010101010101010101010101E4 +:105CB00001010101010101010101010101010101D4 +:105CC00001010101010101010101010101010101C4 +:105CD00001010101010101010101010101010101B4 +:105CE00001010101010101010101010101010101A4 +:105CF0000101010101010101010101010101010194 +:105D00000101010101010101010101010101010183 +:105D10000101010101010101010101010101010173 +:105D20000101010101010101010101010101010163 +:105D30000101010101010101010101010101010153 +:105D40000101010101010101010101010101010143 +:105D50000101010101010101010101010101010133 +:105D60000101010101010101010101010101010123 +:105D70000101010101010101010101010101010113 +:105D8000010101010101010000000000000000000C +:105D900000000000000000010101010101010101FA +:105DA00001010101010101010101010101010101E3 +:105DB00001010101010101010101010101010101D3 +:105DC00001010101010101010101010101010101C3 +:105DD00001010101010101010101010101010101B3 +:105DE00001010101010101010101010101010101A3 +:105DF0000101010101010101010101010101010193 +:105E00000101010101010101010101010101010182 +:105E10000101010101010101010101010101010172 +:105E20000101010101010101010101010101010162 +:105E30000101010101010101010101010101010152 +:105E40000101010101010101010101010101010142 +:105E50000101010101010101010101010101010132 +:105E60000101010101010101010101010101010122 +:105E70000101010101010101010101010101010112 +:105E8000010101010101010000000000000000000B +:105E900000000000000000010101010101010101F9 +:105EA00001010101010101010101010101010101E2 +:105EB00001010101010101010101010101010101D2 +:105EC00001010101010101010101010101010101C2 +:105ED00001010101010101010101010101010101B2 +:105EE00001010101010101010101010101010101A2 +:105EF0000101010101010101010101010101010192 +:105F00000101010101010101010101010101010181 +:105F10000101010101010101010101010101010171 +:105F20000101010101010101010101010101010161 +:105F30000101010101010101010101010101010151 +:105F40000101010101010101010101010101010141 +:105F50000101010101010101010101010101010131 +:105F60000101010101010101010101010101010121 +:105F70000101010101010101010101010101010111 +:105F8000010101010101010000000000000000000A +:105F90000000000000000000000000000000000001 +:105FA00000000000000000020202020202020202DF +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020200000000000000000072 +:10602000000000000000000202020202020202025E +:106030000202020202020200000000000000000052 +:106040000000000000000000000000000000000050 +:10605000000000000000000202020202020202022E +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:106080000202020202020200000000000000000002 +:106090000000000000000000000000000000000000 +:1060A00000000000000000020202020202020202DE +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E00002020202020202000000000000000000A2 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000202020202020202027D +:106110000202020202020200000000000000000071 +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000202020202020202020D +:106180000202020202020200000000000000000001 +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:10629000000000000000004A0000000000000000B4 +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:10631000000000000000000000000100000000007C +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000100000000007B +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:106510000000000000000000000101010101000076 +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000000000000000000000000000000000003B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00000000000000001000000000000000000EA +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:10660000000000000000000000000000000000008A +:106610000000000000000001010101010101000172 +:106620000100000000000000000000000001000068 +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000010001010100000000000000E6 +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000000000000000000AA +:1066F0000000000000010000000000000000000099 +:106700000000000000000000000000000000000089 +:106710000000000000000101010101010101000170 +:106720000100000000000000000000000001000067 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000001F8 +:1067A00001010101010101010101010001010000DC +:1067B00000000000000000000000000000000001D8 +:1067C00001000000000101000001010000000000C4 +:1067D00000000000000000000000000000000000B9 +:1067E00000010000000000000000000000000000A8 +:1067F0000000000000010000000000000000000098 +:106800000000000000000000000000000000000088 +:10681000000000000000010101010101010100016F +:106820000100000000000000000000000001000066 +:106830000000000000010000000000000000000057 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000038 +:106860000000000000000000000000000000010027 +:106870000000000000000000000001000100000016 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000001F7 +:1068A00001010101010101010101010001010000DB +:1068B00000000000000000000000000000000001D7 +:1068C00001000000010101000101010000000000C1 +:1068D00000000000000000000000000000000000B8 +:1068E00000010000000000000000000000000000A7 +:1068F0000000000000010100000000000101000094 +:106900000000000000000000000000000000000087 +:10691000000000000000010101010101010100016E +:106920000100000000000000000000000001000065 +:106930000000000000010000000000000000000056 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000010026 +:106970000000000000000000010001000100000014 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000001F6 +:1069A00001010101010101010101010001010001D9 +:1069B00000010100000000000000000000000001D4 +:1069C00001010101010101000101010000000000BD +:1069D00001010101000000000000000000000000B3 +:1069E00000010100000000000000000000000000A5 +:1069F0000000000000010100000000000101010092 +:106A00000000000000000000000000000000000086 +:106A1000000000000000010101010101010100016D +:106A20000101010000000000000000000001000062 +:106A30000000000000010000000000000000000055 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000100000035 +:106A60000000000000000000000000000000010025 +:106A70000000000000000000010101000100000012 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000001F5 +:106AA00001010101010101010101010001010001D8 +:106AB00000010100000000000000000000000001D3 +:106AC00001010101010101010101010000000000BB +:106AD00001010101010000000000000000000000B1 +:106AE00000010100000000000000000000000001A3 +:106AF000010100000001010000010100010101008D +:106B00000000000000000000000000000000000184 +:106B1000010100000000010101010101010100016A +:106B20000101010001000000000000000001000060 +:106B30000000000000010000000000000000000054 +:106B40000000000000000000000000000000000045 +:106B50000000000000000001010000000100000032 +:106B60000000000000000000000000000000010024 +:106B70000000000000000001010101000100000010 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000001F4 +:106BA00001010101010101010101010101010001D6 +:106BB00001010101000000000000010000000001CF +:106BC00001010101010101010101010000010000B9 +:106BD00001010101010100000000000000000000AF +:106BE00000010100000100000000000000000001A1 +:106BF000010100000001010101010100010101008A +:106C00000000000000000000000000000000000183 +:106C10000101000000000101010101010101000169 +:106C2000010101000101010000000000000100005D +:106C30000000000000010100000000000000000052 +:106C40000000000000000000000000000000000044 +:106C5000000000000000000101010100010000002F +:106C60000000000000000000000000000000010023 +:106C7000000000000000000101010100010000000F +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000001F3 +:106CA00001010101010101010101010101010001D5 +:106CB00001010101010000000000010000000101CC +:106CC00001010101010101010101010000010000B8 +:106CD00001010101010100000000000000000000AE +:106CE000000101000101000000000000000000019F +:106CF0000101000000010101010101000101010089 +:106D00000000000000000000000000000000000182 +:106D10000101010000000101010101010101000167 +:106D2000010101000101010000000000000100005C +:106D30000000000000010100000000000000000051 +:106D40000000000000000000000000000000000043 +:106D5000000000000000000101010100010000002E +:106D60000000000000000000000000000000010022 +:106D7000000000000000000101010100010001000D +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000001F2 +:106DA00001010101010101010101010101010001D4 +:106DB00001010101010101000000010000000101C9 +:106DC00001010101010101010101010100010000B6 +:106DD00001010101010101000000000001000000AB +:106DE000000101010101000000000000000000019D +:106DF0000101000000010101010101000101010088 +:106E00000000000000000000000000000000000181 +:106E10000101010000000101010101010101000166 +:106E2000010101010101010000000000000100005A +:106E3000000000000001010000000000010100004E +:106E40000000000000000000000000000000000042 +:106E5000000000000000000101010100010100002C +:106E60000000000000000000000000000000010021 +:106E7000000000000000000101010100010001000C +:106E80000000000000010000000000000000000001 +:106E900000000000000000000000000000000001F1 +:106EA00001010101010101010101010101010001D3 +:106EB00001010101010101000000010000000101C8 +:106EC00001010101010101010101010100010100B4 +:106ED00001010101010101000000000001000000AA +:106EE000000101010101000000000000000000019C +:106EF0000101010000010101010101000101010086 +:106F00000000000000000000000000000000000180 +:106F10000101010000000101010101010101000165 +:106F20000101010101010100000000000001000059 +:106F3000000000000001010101000000010100004B +:106F40000000000000000000000000000000000041 +:106F5000000000000000000101010100010100002B +:106F60000000000000000000000000000000010020 +:106F7000000000000000000101010100010001000B +:106F80000000000000010000000000000000000000 +:106F900000000000000000000000000000000001F0 +:106FA00001010101010101010101010101010001D2 +:106FB00001010101010101000000010000000101C7 +:106FC00001010101010101010101010101010101B1 +:106FD00001010101010101000000000001000001A8 +:106FE000010101010101000000000000000000019A +:106FF0000101010000010101010101000101010184 +:10700000000000000000000000000000000100017E +:107010000101010001000101010101010101000163 +:107020000101010101010100000000000001000058 +:10703000000000000001010101000000010100004A +:107040000000000000000000000000000000000040 +:107050000000000000000001010101010101000029 +:10706000000000000000000000000000000001001F +:10707000000000000000000101010100010001000A +:1070800000000000000101000000000000000000FE +:1070900000000000000000000000000000000001EF +:1070A00001010101010101010101010101010001D1 +:1070B00001010101010101010000010000000101C5 +:1070C00001010101010101010101010101010101B0 +:1070D00001010101010101010100000001000001A5 +:1070E0000101010101010000000000000000000199 +:1070F0000101010000010101010101010101010182 +:10710000000000000000000000000000000100017D +:107110000101010101010101010101010101000160 +:107120000101010101010100000000000001000057 +:107130000000000000010101010000000101000049 +:10714000000000000000000000000000000000003F +:107150000000000000000001010101010101010126 +:10716000010100000000000000000000000001001C +:107170000000000000000001010101000100010009 +:1071800000000000000101010100000000000000FB +:1071900000000000000000000000000000000002ED +:1071A00002010101010101010101010101010001CF +:1071B00001010101010101010000010000000102C3 +:1071C00002010101010101010101010101010101AE +:1071D00001010101010101010101010001010001A1 +:1071E0000101010101010000000000000000000198 +:1071F0000101010000010101010101010101010181 +:10720000000000000000000000000001000100017B +:10721000010101010101010101010101010100015F +:107220000101010101010100000000000101000055 +:107230000000000000010101010000000101000048 +:10724000000000000000000000000000000000013D +:107250000101000000000001010101010101010123 +:10726000010100000000000000000000000001001B +:107270000000000000000001010101000100010008 +:1072800000000000000101010100000000000000FA +:1072900000000000000000000000000000000002EC +:1072A00002020101010101010101010101010001CD +:1072B00001010101010101010100010000000102C1 +:1072C00002010101010101010101010101010101AD +:1072D00001010101010101010101010001010001A0 +:1072E0000101010101010000000000000000000197 +:1072F000010101010001010101010101010101017F +:107300000000000000000000000000010001010179 +:10731000010101010101010101010101010100015E +:107320000101010101010100000000000101000054 +:107330000000000000010101010000000101010046 +:10734000000000000000000000000000000000013C +:107350000101000000000001010101010101010122 +:107360000101010000000000000000000100010018 +:107370000000000000000001010101000100010007 +:1073800000000000000101010100000000000000F9 +:1073900000000000000000000000000000000002EB +:1073A00002020202010101010101010101010002C9 +:1073B00001020201010101010100010000000102BE +:1073C00002020101010101010101010101010101AB +:1073D000020101010101010101010101010100019D +:1073E0000102010101010100000000000000000194 +:1073F000010101010101010101010101010101017D +:107400000000010000000000000000010001010177 +:10741000010101010101010101010101010100015D +:107420000101010101010100000000000101000152 +:107430000100000000010101010000000101010044 +:10744000000000000000000000000000000000013B +:107450000101000000000001010101010101010121 +:107460000101010001000000000000000100010016 +:107470000000000000000001010101000100010006 +:1074800000000000000101010101010000000000F6 +:1074900000000000000000000000000000000002EA +:1074A00002020202010102010101010101010002C7 +:1074B00002020202010101010100010000000102BB +:1074C00002020202010102010101010101010101A7 +:1074D000020202010101010101010101010100019A +:1074E0000102010101010100000000000000000193 +:1074F000010101010101010101010101010101017C +:107500000000010000000000000000010001010176 +:10751000010101010101010101010101010100015C +:10752000010101010101010101000000010101014E +:107530000100000000010101010000000101010043 +:10754000000000000000000000000000000000013A +:107550000101000000000001010101010101010120 +:107560000101010001010000000001000100010013 +:107570000000000000000001010101000100010005 +:1075800000000000000101010101010000000000F5 +:1075900000000000000000000000000000000002E9 +:1075A00002020202020102020101010101010002C4 +:1075B00002020202010101010101010000000102B9 +:1075C00002020202010202010101010101010101A5 +:1075D0000202020201010101010101010101000198 +:1075E0000102020101010100000000000100000190 +:1075F000010101010101010101010101010101017B +:107600000000010000000000000001010101010173 +:10761000010101010101010101010101010100025A +:10762000020101010101010101000000010101014C +:107630000101000000010101010000000101010041 +:107640000000000000010000000000000100000137 +:10765000010101000000000101010101010101011E +:107660000101010001010000010001000100010011 +:107670000000000000000001010101000100010103 +:1076800001010000000101010101010000000000F2 +:1076900000000000000000000000000000000002E8 +:1076A00002020202020202020201010101010002C1 +:1076B00002020202010101010101010000000102B8 +:1076C00002020202020202020202010101010101A0 +:1076D0000202020201010101010101010101000197 +:1076E000010202010101010001000000010000028D +:1076F0000201010101010101010101010101010179 +:107700000000010000000000000001010101010172 +:107710000101010101010101010101010101000259 +:10772000020101010101010101000000010101014B +:10773000010100000101010101000000010101003F +:107740000000000000010000000000000100000136 +:10775000010101000100000101010101010101011C +:10776000010101010101010001010100010101000C +:107770000000000000000001010101000100010102 +:1077800001010000010101010101010000000000F0 +:1077900000000000000000000000000000000002E7 +:1077A00002020202020202020202010101010002BF +:1077B00002020202020202010101010100000102B3 +:1077C000020202020202020202020201010101029D +:1077D0000202020202010101010101010101000294 +:1077E0000202020101010100010101000100000289 +:1077F0000202010101010101010101010101010177 +:10780000000001010000000000000101010101026F +:107810000201010101010101010101010101010256 +:107820000201010101010101010001010101010148 +:10783000010101000101010101010100010101013A +:107840000000000000010100000000000100000134 +:107850000101010101010001010101010101010119 +:107860000101010101010101010101000101010109 +:107870000000000000000001010101000100010101 +:1078800001010000010101010101010000000000EF +:1078900000000000000000000000000000000002E6 +:1078A00002020202020202020202020101010002BD +:1078B00002020202020202010101020100000102B1 +:1078C000020202020202020202020201010101029C +:1078D0000202020202020101010101010101010291 +:1078E0000202020201010100010101000100000287 +:1078F0000202010101010101010101010101010176 +:10790000000001010000000000000101010101026E +:107910000202010101010101010101010101010254 +:107920000202010101010101010001010101010146 +:107930000101010001010101010101000101010139 +:107940000000000000010101010000000100000131 +:107950000101010101010001010101010101010118 +:107960000101010101010101010101010101010107 +:1079700000000000010000010101010001000101FF +:1079800001010000010101010101010000000000EE +:1079900000000000000000000000000000000002E5 +:1079A00002020202020202020202020101010002BC +:1079B00002020202020202020101020101000102AE +:1079C000020202020202020202020201010101029B +:1079D000020202020202020101010101010101028F +:1079E0000202020201020100010101000100000285 +:1079F0000202010101020101010101010101010174 +:107A0000000001010001000000000101010101026C +:107A10000202010101010101010101010101010253 +:107A20000202020101010101010101010101010143 +:107A30000101010101010101010101010101010136 +:107A4000010100000001010101000000010100012D +:107A50000101010101010001010101010101010117 +:107A60000101010101010101010101010101010106 +:107A700001010100010100010101010001010101F9 +:107A800001010100010101010101010000000000EC +:107A900000000000010000000000000000000102E2 +:107AA00002020202020202020202020202020002B8 +:107AB00002020202020202020201020101000102AC +:107AC0000202020202020202020202020101010299 +:107AD000020202020202020201010101010101028D +:107AE0000202020202020100010101000100000283 +:107AF0000202020101020201010101010101010270 +:107B0000000001010101000000000101010101026A +:107B1000020202010101020201010101010101024F +:107B20000202020101010101010101010101010142 +:107B30000101010101010101010101010101010135 +:107B4000010100000001010101000000010101012B +:107B50000101010101010001010101010101010116 +:107B60000101010101010101010101010101010105 +:107B700001010100010100010101010001010101F8 +:107B800001010100010101010101010000000000EB +:107B900000000000010100000000000001010102DE +:107BA00002020202020202020202020202020002B7 +:107BB00002020202020202020201020101010202A9 +:107BC0000202020202020202020202020102010297 +:107BD000020202020202020202010101010101028B +:107BE0000202020202020100010101000100000282 +:107BF000020202010102020101010101010101026F +:107C00000101010101010000000001010101010267 +:107C1000020202010101020202020201010101024B +:107C20000202020101010101010101010101010141 +:107C30000101010101010101010101010101010134 +:107C40000101010000010101010101010101010126 +:107C50000101010101010001010101010101010115 +:107C60000101010101010101010101010101010104 +:107C700001010100010101010101010101010101F5 +:107C800001010101010101010101010001000000E8 +:107C900000000000010100000000000001010102DD +:107CA00002020202020202020202020202020002B6 +:107CB00002020202020202020202020101010202A7 +:107CC0000202020202020202020202020102010296 +:107CD0000202020202020202020201010101010289 +:107CE0000202020202020101010101000100000280 +:107CF000020202010102020201010101010101026D +:107D00000101010101010000000001010101010266 +:107D10000202020101010202020202020101010249 +:107D2000020202020101010101010101010101013F +:107D30000101010101020101010101010101010132 +:107D40000101010001010101010101010101010223 +:107D50000201010101010001010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010100010101010101010101010101F4 +:107D800001010101010101010101010001000100E6 +:107D900001010101010101000000010101010102D5 +:107DA00002020202020202020202020202020002B5 +:107DB00002020202020202020202020101010202A6 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020202010201010286 +:107DE000020202020202020101010101010000027D +:107DF0000202020201020202020201010101010269 +:107E00000101010101010000000001010101010265 +:107E10000202020201010202020202020101010247 +:107E2000020202020201010101010101010101023C +:107E30000201010101020101010101010101010130 +:107E40000101010001010101010101010101010222 +:107E5000020201010101010101010101010101020F +:107E60000201010101010101010101010101010101 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010100E3 +:107E900001010101010101010100010101010102D2 +:107EA00002020202020202020202020202020002B4 +:107EB00002020202020202020202020201010202A4 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020202020202020201010284 +:107EE000020202020202020101010101010000027C +:107EF0000202020201020202020202010101010267 +:107F00000101020101010000000001010101010263 +:107F10000202020201010202020202020202010244 +:107F20000202020202020201010101010101010239 +:107F3000020101010102020101010101010101012E +:107F40000101010001010101010101010101010221 +:107F5000020201010101010201010101010101020D +:107F600002020101010101010101010101010101FF +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010100E2 +:107F900001010101010101010101010101010102D0 +:107FA00002020202020202020202020202020002B3 +:107FB00002020202020202020202020201010202A3 +:107FC0000202020202020202020202020202020291 +:107FD0000202020202020202020202020202010282 +:107FE0000202020202020201020101010101000279 +:107FF0000202020201020202020202010202010264 +:108000000101020101010100000101010101010260 +:108010000202020202010202020202020202010242 +:108020000202020202020201010101010102010237 +:10803000020201010102020101010101010101022B +:10804000010101010101010101010101010101021F +:10805000020201010101010202010101010101020B +:1080600002020101010101010101010101010101FE +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010100E1 +:1080900001010101010101010101010101010102CF +:1080A00002020202020202020202020202020002B2 +:1080B00002020202020202020202020201010202A2 +:1080C0000202020202020202020202020202020290 +:1080D0000202020202020202020202020202010281 +:1080E0000202020202020201020201010101010276 +:1080F0000202020202020202020202010202010262 +:10810000010102010101010101010101010101025D +:108110000202020202020202020202020202010240 +:108120000202020202020201010101010102010236 +:108130000202010101020202010101010101010229 +:10814000020101010101010101010101010101021D +:108150000202020101010102020201010101010208 +:1081600002020201010101010101010101010101FC +:1081700001010101010101020201010101010102EC +:1081800002010101010101010101010101010100DF +:1081900001010101010101010101010101010102CE +:1081A00002020202020202020202020202020002B1 +:1081B00002020202020202020202020202010202A0 +:1081C000020202020202020202020202020202028F +:1081D0000202020202020202020202020202010280 +:1081E0000202020202020201020202010101010274 +:1081F000020202020202020202020202020202025F +:10820000020102020101010101010101010101025A +:10821000020202020202020202020202020201023F +:108220000202020202020201010101010102010235 +:108230000202020101020202020101010101010226 +:10824000020201010101010101010101010101021B +:108250000202020101010102020202010101010206 +:1082600002020201010101010101010101010102FA +:1082700001010101010101020202020101010102E9 +:1082800002020101010201010101010101010100DC +:1082900001010101010101010101010101010102CD +:1082A00002020202020202020202020202020002B0 +:1082B000020202020202020202020202020202029E +:1082C000020202020202020202020202020202028E +:1082D000020202020202020202020202020201027F +:1082E0000202020202020202020202010201010271 +:1082F000020202020202020202020202020202025E +:108300000202020201010101010101020101010257 +:10831000020202020202020202020202020201023E +:108320000202020202020201010101010102010234 +:108330000202020101020202020101010101010225 +:10834000020201010101010101010101010101021A +:108350000202020201010102020202010201010203 +:1083600002020201010101010101010101010102F9 +:1083700002010101010101020202020101010102E7 +:1083800002020101010202010101010101010100DA +:1083900001010101010101010101010101010102CC +:1083A00002020202020202020202020202020002AF +:1083B000020202020202020202020202020202029D +:1083C000020202020202020202020202020202028D +:1083D000020202020202020202020202020202027D +:1083E000020202020202020202020202020101026F +:1083F000020202020202020202020202020202025D +:108400000202020201010101010101020101010256 +:10841000020202020202020202020202020201023D +:108420000202020202020202010101010102010232 +:108430000202020201020202020101010101010223 +:108440000202020101020101010101010101010217 +:108450000202020201010102020202020201010201 +:1084600002020202010101010101010101010102F7 +:1084700002020101010101020202020102010102E4 +:1084800002020101010202020101010101010100D8 +:1084900002010101010101010101010101010102CA +:1084A00002020202020202020202020202020002AE +:1084B000020202020202020202020202020202029C +:1084C000020202020202020202020202020202028C +:1084D000020202020202020202020202020202027C +:1084E000020202020202020202020202020101026E +:1084F000020202020202020202020202020202025C +:108500000202020201020101010102020102010252 +:10851000020202020202020202020202020201023C +:108520000202020202020202020101010102010230 +:10853000020202020202020202010101020201021F +:108540000202020101020201010101010101010215 +:1085500002020202020101020202020202020102FE +:1085600002020202020101010101010101010202F4 +:1085700002020201010101020202020102010102E2 +:1085800002020201010202020201010101010100D5 +:1085900002020101010101010101010101010102C8 +:1085A00002020202020202020202020202020002AD +:1085B000020202020202020202020202020202029B +:1085C000020202020202020202020202020202028B +:1085D000020202020202020202020202020202027B +:1085E000020202020202020202020202020101026D +:1085F000020202020202020202020202020202025B +:108600000202020202020101010102020102010250 +:10861000020202020202020202020202020201023B +:10862000020202020202020202010101010201022F +:10863000020202020202020202010101020201021E +:108640000202020101020202010101010101010213 +:1086500002020202020201020202020202020102FC +:1086600002020202020201010101010101010202F2 +:1086700002020201010101020202020102010102E1 +:1086800002020201010202020201010101010100D4 +:1086900002020201010101010101010101010102C6 +:1086A00002020202020202020202020202020002AC +:1086B000020202020202020202020202020202029A +:1086C000020202020202020202020202020202028A +:1086D000020202020202020202020202020202027A +:1086E000020202020202020202020202020201026B +:1086F000020202020202020202020202020202025A +:10870000020202020202010101010202010201024F +:10871000020202020202020202020202020201023A +:10872000020202020202020202010101020201022D +:10873000020202020202020202020101020201021C +:108740000202020201020202020101010101010210 +:1087500002020202020201020202020202020102FB +:1087600002020202020202010101010101010202F0 +:1087700002020201010101020202020102010102E0 +:1087800002020202020202020202010101010100D0 +:1087900002020202010101010101010101010102C4 +:1087A00002020202020202020202020202020002AB +:1087B0000202020202020202020202020202020299 +:1087C0000202020202020202020202020202020289 +:1087D0000202020202020202020202020202020279 +:1087E000020202020202020202020202020201026A +:1087F0000202020202020202020202020202020259 +:10880000020202020202020101010202020202024B +:108810000202020202020202020202020202010239 +:108820000202020202020202020202020202010229 +:10883000020202020202020202020201020201021A +:10884000020202020202020202010101010101020E +:1088500002020202020201020202020202020202F9 +:1088600002020202020202020201010101010202ED +:1088700002020202020101020202020102010202DC +:1088800002020202020202020202020101010100CE +:1088900002020202020101010101010101010102C2 +:1088A00002020202020202020202020202020002AA +:1088B0000202020202020202020202020202020298 +:1088C0000202020202020202020202020202020288 +:1088D0000202020202020202020202020202020278 +:1088E0000202020202020202020202020202010269 +:1088F0000202020202020202020202020202020258 +:108900000202020202020202010102020202020249 +:108910000202020202020202020202020202010238 +:108920000202020202020202020202020202010228 +:108930000202020202020202020202020202020217 +:10894000020202020202020202020101020101020B +:1089500002020202020202020202020202020202F7 +:1089600002020202020202020202020101010202EA +:1089700002020202020201020202020102010202DA +:1089800002020202020202020202020101010100CD +:1089900002020202020201010101010101010102C0 +:1089A00002020202020202020202020202020002A9 +:1089B0000202020202020202020202020202020297 +:1089C0000202020202020202020202020202020287 +:1089D0000202020202020202020202020202020277 +:1089E0000202020202020202020202020202020267 +:1089F0000202020202020202020202020202020257 +:108A00000202020202020202020202020202020246 +:108A10000202020202020202020202020202010237 +:108A20000202020202020202020202020202020226 +:108A30000202020202020202020202020202020216 +:108A40000202020202020202020202020201010208 +:108A500002020202020202020202020202020202F6 +:108A600002020202020202020202020102010202E8 +:108A700002020202020202020202020102010202D8 +:108A800002020202020202020202020101010100CC +:108A900002020202020202010101010101010102BE +:108AA00002020202020202020202020202020002A8 +:108AB0000202020202020202020202020202020296 +:108AC0000202020202020202020202020202020286 +:108AD0000202020202020202020202020202020276 +:108AE0000202020202020202020202020202020266 +:108AF0000202020202020202020202020202020256 +:108B00000202020202020202020202020202020245 +:108B10000202020202020202020202020202020235 +:108B20000202020202020202020202020202020225 +:108B30000202020202020202020202020202020215 +:108B40000202020202020202020202020202010206 +:108B500002020202020202020202020202020202F5 +:108B600002020202020202020202020202010202E6 +:108B700002020202020202020202020102010202D7 +:108B800002020202020202020202020101010100CB +:108B900002020202020202020101010101010102BC +:108BA00002020202020202020202020202020002A7 +:108BB0000202020202020202020202020202020295 +:108BC0000202020202020202020202020202020285 +:108BD0000202020202020202020202020202020275 +:108BE0000202020202020202020202020202020265 +:108BF0000202020202020202020202020202020255 +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202010205 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020102010202D6 +:108C800002020202020202020202020101010100CA +:108C900002020202020202020201010101010102BA +:108CA00002020202020202020202020202020002A6 +:108CB0000202020202020202020202020202010295 +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020202020202020202020274 +:108CE0000202020202020202020202020202020264 +:108CF0000202020202020202020202020202020254 +:108D00000202020202020202020202020202020243 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202010202D4 +:108D800002020202020202020202020101010102C7 +:108D900002020202020202020202020201010102B6 +:108DA00002020202020202020202020202020002A5 +:108DB000020202020202020201010101010101029A +:108DC0000202020202020202020202020202020283 +:108DD0000202020202020202020202020202020273 +:108DE0000202020202020202020202020202020263 +:108DF0000202020202020202020202020202020253 +:108E00000202020202020202020202020202020242 +:108E10000202020202020202020202020202020232 +:108E20000202020202020202020202020202020222 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202020202020201010102C5 +:108E900002020202020202020202020202020102B3 +:108EA00002020202020202020202020202020002A4 +:108EB000020202020201010101010101010101029C +:108EC0000202020202020202020202020202010283 +:108ED0000202020202020202020202020202020272 +:108EE0000202020202020202020202020202020262 +:108EF0000202020202020202020202020202020252 +:108F00000202020202020202020202020202020241 +:108F10000202020202020202020202020202020231 +:108F20000202020202020202020202020202020221 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202020202020202020202D1 +:108F800002020202020202020202020202010102C3 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020202020202020002A3 +:108FB000020202010101010101010101010101029D +:108FC000020202020202010101010101010101028A +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202020202020261 +:108FF0000202020202020202020202020202020251 +:109000000202020202020202020202020202020240 +:109010000202020202020202020202020202020230 +:109020000202020202020202020202020202020220 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020102C1 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020201010101010101010102A9 +:1090B000020201010101010101010101010101029D +:1090C000020202020201010101010101010101028A +:1090D0000202020202020202020202020202010271 +:1090E0000202020202020202020202020202020260 +:1090F0000202020202020202020202020202020250 +:10910000020202020202020202020202020202023F +:10911000020202020202020202020202020202022F +:10912000020202020202020202020202020202021F +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A00002020201010101010101010101010102AB +:1091B000020101010101010101010101010101029D +:1091C000020202010101010101010101010101028B +:1091D0000202020202020201010101010101010277 +:1091E000020202020202020202020202020202025F +:1091F000020202020202020202020202020202024F +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020201AF +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101028D +:1092D0000202020201010101010101010101010279 +:1092E0000202020202020202020202010201020260 +:1092F000020202020202020202020202020202024E +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020201AE +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101028C +:1093D000020201010101010101010101010101027A +:1093E0000202020202020202010101010101010264 +:1093F000020202020202020202020202020202024D +:10940000020202020202020202020202020202023C +:10941000020202020202020202020202020202022C +:10942000020202020202020202020202020202021C +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020201AD +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101028B +:1094D000010101010101010101010101010101027B +:1094E0000202020202010101010101010101010266 +:1094F000020202020202020202020202020202024C +:10950000020202020202020202020202020202023B +:10951000020202020202020202020202020202022B +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020201AC +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101027A +:1095E0000201010101010101010101010101010269 +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020202020202020202022A +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020201AB +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E0000101010101010101010101010101010269 +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020201AA +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010268 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:109810000202020202020202020202020202020228 +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020201A9 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010267 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020201A8 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010266 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020202020226 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020201A7 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010265 +:109AF0000202020202010101010101010101010250 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020201A6 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010254 +:109C00000202020202020202020201010202020236 +:109C1000020202020202010101010101010102022C +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020201A5 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010253 +:109D0000020202020201010101010101010101013E +:109D10000101010101010101010101010101010232 +:109D20000202020202020202020202020201020214 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020202020202020202020202020202E3 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020201A4 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000202010101010101010101010101010140 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010221 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202020202020202E2 +:109E600002020202020202020202020202020202D2 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020201A3 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010220 +:109F3000020202020201010101010101010101020B +:109F400002020202020101010101010101010102FB +:109F500002020202020202020202020202020202E1 +:109F600002020202020202020202020202020202D1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020201A2 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A0400001010101010101010101010101010102FF +:10A0500002020202020202010101010101010102E8 +:10A0600002020202020202020202020202020202D0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020201A1 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010102EE +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A1900002020202020202020202020202020201A0 +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010102ED +:10A2600002020202020202020202020202020102CF +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202019F +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010102DC +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202019E +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010102DB +:10A4700002020202020202020202020202020202BC +:10A4800002020202020101010101010202020202B2 +:10A49000020202020202020202020202020202019D +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010102DA +:10A5700002020202020202010101010201020101C2 +:10A5800001010101010101010101010101010102BA +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010101010101010101010101010100BB +:10A6900000000000000000000000000000000001B9 +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010100BA +:10A7900000000000000000000000000000000001B8 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010100B9 +:10A8900000000000000000000000000000000001B7 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010100B8 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000002A5 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020049 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000244 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020200C8 +:10AA700000000000000000000000000000000002D4 +:10AA800002020202020202020202020202020200A8 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000002A4 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020048 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000213 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020200D7 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000002D3 +:10AB800002020202020202020202020202020200A7 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC90000000000000000000000000000000004272 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000001000000010000000000000000000021 +:10AD30000000000000000000010000000000000012 +:10AD40000000000000000000000100000000000002 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000010000000041 +:10AE10000000000000000000000000000000010130 +:10AE2000000100000101000000000000000000001F +:10AE3000000000000000000001010100000000000F +:10AE40000000000000000000010100000000000000 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000001A1 +:10AEB0000000000000000000000000000100000091 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000010000000040 +:10AF1000000000000000000000000000000001012F +:10AF2000000100000101010000000000000000001D +:10AF3000000000000000000001010100000000000E +:10AF400000000000000000000101010000000000FE +:10AF500000000000010000000100000000000000EF +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000001A0 +:10AFB0000000000000000000000000000100000090 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B00000000000000000000000000001000000003F +:10B01000000000000000000000000000000001012E +:10B02000010100000101010000000000000000001B +:10B03000000000000000000001010100000000000D +:10B0400000000000000000000101010000000000FD +:10B0500000000000010000000101000000000000ED +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A000000000000000000000000000000000019F +:10B0B000000000000000000000000000010000008F +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E000000000000000000001000000000000005F +:10B0F000000000010000000000000000000000004F +:10B10000000000000000000000000001000000003E +:10B11000000000000000000000000000000001012D +:10B120000101000101010100000000000000000019 +:10B13000000000000000000101010100000000000B +:10B1400000000000000000000101010001000000FB +:10B1500000000000010000000101000000000000EC +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000019E +:10B1B000000000000000000000000000010000008E +:10B1C000000000000000000100000000000000007E +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000001000001010000015B +:10B1F000000001010000000000000000000000004D +:10B20000000000000000000000000001000000003D +:10B21000000000000000000000000000000001012C +:10B220000101010101010100000000000000000017 +:10B230000000000000000001010101010101000007 +:10B2400000000000000000010101010001000000F9 +:10B2500000000000010000000101010000000000EA +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000001000000019C +:10B2B000000000000000000000000100010000008C +:10B2C000000000000000000100000000000000007D +:10B2D000000000000000000000000000000000006E +:10B2E0000000000000000001010000010100000159 +:10B2F000000101010000000000000000000000004B +:10B30000000000000000000100000001000000003B +:10B31000000000000000000001000000000001012A +:10B320000101010101010101000000000000000015 +:10B330000000000000000001010101010101000006 +:10B3400000000000000000010101010101010000F6 +:10B3500000000000010000000101010000000000E9 +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000001000000019B +:10B3B000000000000000000000000100010000008B +:10B3C000000000000000000100000001000000007B +:10B3D000000000000000000000000000000001016B +:10B3E0000000000000000001010000010101000157 +:10B3F0000101010100000000000000000000000049 +:10B40000000000000000000100000001000000003A +:10B410000000000000000000010100000000010128 +:10B420000101010101010101000000010000000013 +:10B430000000000000000001010101010101000005 +:10B4400000000000010000010101010101010000F4 +:10B4500000000000010000000101010101010000E5 +:10B4600000000000000000000100000000000000DB +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000001000000019A +:10B4B0000100000000000000000001000101000187 +:10B4C0000100000000000001000000010000000178 +:10B4D0000000000000000001000000000000010169 +:10B4E0000001000000000101010000010101000154 +:10B4F0000101010100000000000000000000000048 +:10B500000000000000000001000000010000000039 +:10B510000000000000000001010100000000010126 +:10B520000101010101010101000000010000000012 +:10B530000000000000000001010101010101000004 +:10B5400000000000010100010101010101010100F1 +:10B5500000000000010000010101010101010000E3 +:10B5600000000000000000000101010000000000D8 +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A0000000000000000000000000010000000199 +:10B5B0000101000000000000000001000101000185 +:10B5C0000101000000000001000000010000000176 +:10B5D0000000000000000001000000000000010168 +:10B5E0000101000000000101010100010101000151 +:10B5F0000101010100000000000000000000000047 +:10B600000000000000000001000000010000000038 +:10B610000000000000000001010100000000010125 +:10B62000010101010101010100000001010000010F +:10B630000000000000000001010101010101010101 +:10B6400001000000010100010101010101010100EF +:10B6500000000000010100010101010101010101DF +:10B6600000000000010000010101010000000000D5 +:10B6700000000000000000000001010000000000C8 +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A0000000000000000000000001010100000196 +:10B6B0000101000000000000000001000101010183 +:10B6C0000101010000000001010000010000000173 +:10B6D0000000000000000001010000000000010166 +:10B6E000010100000001010101010001010100014F +:10B6F0000101010100000000000000000000000046 +:10B700000000000000000001000000010000000037 +:10B710000000000000000001010100000000010124 +:10B72000010101010101010100000001010000010E +:10B730000000000000000001010101010101010100 +:10B7400001000001010101010101010101010101EB +:10B7500001000000010100010101010101010101DD +:10B7600000000000010100010101010000000000D3 +:10B7700000000000000000000001010000000000C7 +:10B7800000000000000000000000000000010101B6 +:10B7900000000000010000000000000000000000A8 +:10B7A0000000000000000000000001010100000195 +:10B7B0000101000000010001000001000101010180 +:10B7C0000101010000000001010100010000000171 +:10B7D0000000000000000001010000010000010164 +:10B7E000010100000001010101010001010101014D +:10B7F0000101010100000000000000000000000045 +:10B800000000000000000001000000010000000036 +:10B810000000000000000001010101000000010122 +:10B82000010101010101010100000001010101010B +:10B8300000000100010000010101010101010101FD +:10B8400001000001010101010101010101010101EA +:10B8500001000001010101010101010101010101DA +:10B8600001000000010100010101010000000000D1 +:10B8700000000000000000000001010001000000C5 +:10B8800000000000000000000000000000010101B5 +:10B8900000000000010100000000000000000000A6 +:10B8A0000000000000000000000001010101000193 +:10B8B000010100000001000100000100010101017F +:10B8C000010101010000000101010001000000016F +:10B8D0000000000000000001010000010000010163 +:10B8E000010100000001010101010001010101014C +:10B8F0000101010100000000000000000000000044 +:10B900000000000000000101000000010000000034 +:10B910000000000000000001010101000000010121 +:10B92000010101010101010100000001010101010A +:10B9300000000100010000010101010101010101FC +:10B9400001010001010101010101010101010101E8 +:10B9500001000101010101010101010101010101D8 +:10B9600001010001010101010101010101000000CB +:10B9700000000000000000000001010001000000C4 +:10B9800000000000000000000000000000010101B4 +:10B9900001000100010100000000000000000000A3 +:10B9A0000000000000000001000001010101000191 +:10B9B000010100000001000101000100010101017D +:10B9C000010101010000010101010001000001016C +:10B9D0000000000000000001010100010000010161 +:10B9E0000101010000010101010101010101010149 +:10B9F0000101010100000000000000000000000043 +:10BA00000000000000000101000100010001000031 +:10BA10000000000000000001010101000000010120 +:10BA20000101010101010101000000010101010109 +:10BA300000000100010000010101010101010101FB +:10BA400001010101010101010101010101010101E6 +:10BA500001010101010101010101010101010101D6 +:10BA600001010101010101010101010101000000C9 +:10BA700000000000000000000001010101000000C2 +:10BA800000000000000000000000000000010101B3 +:10BA9000010101010101010000000000000000009F +:10BAA000000000000000000100010101010101018E +:10BAB000010100000001000101010101010101017A +:10BAC000010101010100010101010001000001016A +:10BAD0000000000000000001010100010000010160 +:10BAE0000101010000010101010101010101010148 +:10BAF0000101010100000001010000000000000040 +:10BB00000000000000000101000100010001000030 +:10BB1000000000000100000101010100000001011E +:10BB20000101010101010101000000010101010108 +:10BB300000000101010001010101010101010101F8 +:10BB400001010101010101010101010101010101E5 +:10BB500001010101010101010101010101010101D5 +:10BB600001010101010101010101010101010101C5 +:10BB700000000000010000000001010101000000C0 +:10BB800000000000000000000000000000010101B2 +:10BB9000010101010101010000000000000000009E +:10BBA000000000000000000101010101010101018C +:10BBB0000101000000010001010101010101010179 +:10BBC0000101010101000102010101010100010166 +:10BBD000000000000100000101010101010001015C +:10BBE0000101010001010101010101010101010146 +:10BBF000010101010000000101010001000000003D +:10BC0000000000000100010200010101000101002B +:10BC1000000100000100000101010100000001011C +:10BC20000101010101010101000100010101010106 +:10BC300001000101010001010101010101010101F6 +:10BC400001010101010101010101010101010101E4 +:10BC500001010101010101010101010101010101D4 +:10BC600001010101010101010101010101010101C4 +:10BC700000000000010100000001010101010101BB +:10BC800000000000000000000000000000010101B1 +:10BC9000010101010101010000000000000000009D +:10BCA000000000000000000101010101010101018B +:10BCB0000101010000010001010101010201010176 +:10BCC0000101010101000102010101010100010165 +:10BCD0000000000101000002010101010100010159 +:10BCE0000101010001010102020101010101010143 +:10BCF000010101010000000101010001000000003C +:10BD00000000000001010102000101010001010029 +:10BD1000000100000100000101010100000001011B +:10BD20000101010101010101010100010101010104 +:10BD300001010101010001010101010101010101F4 +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001000000010100000001010101010101B9 +:10BD800000000000000000000000000000010101B0 +:10BD9000010101010101010000010000000000009B +:10BDA000000000000000000101010101010101018A +:10BDB0000101010000010001010102010201010174 +:10BDC0000101010101010102010101010100010163 +:10BDD0000000000101000002010101010100010158 +:10BDE0000101010001010102020101010101010142 +:10BDF0000101010100000001010101010100010137 +:10BE00000000000001010102000101020001010027 +:10BE10000001000001000001010101010000010119 +:10BE20000101010101010101010100010101010103 +:10BE300001010101010001010101010101010101F3 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010001010101000001010101010101B5 +:10BE800001000000000000000000000000010101AE +:10BE90000101010101010100010100000000000099 +:10BEA0000000000000000001010101020101010287 +:10BEB0000101010000010002010102010201010172 +:10BEC0000101010101010102010101010100010162 +:10BED0000000000101000102020101010100010155 +:10BEE0000101010001010102020101020101010140 +:10BEF0000101010101000001010101010100010135 +:10BF00000000000001010102010101020001010025 +:10BF10000101010001000001010101010000010116 +:10BF20000101010101010101010100010101010102 +:10BF300001010101010001010101010101010101F2 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101000001010101010101B3 +:10BF800001010000000100000000000000010101AB +:10BF90000101010101010100010101000000000097 +:10BFA0000000000000000001010101020101010286 +:10BFB0000101010100010002010102010201010170 +:10BFC000010101010101010202010102010101015E +:10BFD0000000000101000102020101010101020152 +:10BFE000010101000101010202010102020101013E +:10BFF0000101010101000001010101010101010133 +:10C000000100010001010102010101020001010022 +:10C010000101010101000001010101010101010112 +:10C020000101010101010101010101010101010100 +:10C0300001010101010001010201010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101000001010101010101B2 +:10C0800001010100010100000000000000010101A8 +:10C090000101010101010100010101000000000096 +:10C0A0000000000000000002010102020101010283 +:10C0B000010101010001000202010201020201016D +:10C0C000020101010101010202010102010101015C +:10C0D000000000010100010202010102010102024F +:10C0E000010101000101010202020102020101023B +:10C0F0000101010101000001010101010101010132 +:10C10000010101010101010201010102000101001F +:10C11000010101010100000202010101010101010F +:10C1200001010101010101020101010101010101FE +:10C1300001010101010001020201010101010101EE +:10C1400001010101010101010201010101010101DE +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101000001010101010101B1 +:10C1800001010100010101000000000000010101A6 +:10C190000101010101010100010101010101010190 +:10C1A0000000000001000002010102020201010280 +:10C1B0000202010100010002020102010202020268 +:10C1C0000202020101010102020201020101010257 +:10C1D000000000010100010202020102010102024D +:10C1E0000202010001010102020201020202010237 +:10C1F000020202020100000201010101010101012C +:10C20000010101010101010201010102000101001E +:10C21000010101010100000202010101010102010D +:10C2200001010101010101020101010101010101FD +:10C2300001010101010001020202020101010101EB +:10C2400001010101010101020202010101010101DB +:10C2500001010101010101010201010101010101CD +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101000001010101010101B0 +:10C2800001010100010101000100000000010101A4 +:10C29000010101010101010001010101010101018F +:10C2A000000000000101000202010202020101027D +:10C2B0000202010100010002020202020202020265 +:10C2C0000202020201010102020201020101010255 +:10C2D000000001010100010202020202010102024A +:10C2E0000202010001010102020202020202010235 +:10C2F000020202020100000202010101010101012A +:10C30000010101010101010201010102000101001D +:10C310000101010101000102020201010101020209 +:10C3200001020101010101020101010101010101FB +:10C3300001010101010001020202020101010101EA +:10C3400001010101010101020202020101010101D9 +:10C3500001010101010101010201010101010101CC +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101000101010101010101AE +:10C3800001010101010101000101000000010101A1 +:10C39000010101010101010001010101010101018E +:10C3A0000100000001010002020202020202010279 +:10C3B0000202010100010002020202020202020264 +:10C3C0000202020201010102020202020101010253 +:10C3D0000100010101000102020202020201020247 +:10C3E0000202020001010102020202020202020232 +:10C3F0000202020201000002020101010101010129 +:10C400000101010101010102020201020101010118 +:10C410000101010101000102020201010101020208 +:10C4200002020101010101020101010101010101F9 +:10C4300001010101010001020202020101010101E9 +:10C4400001010101010101020202020101010101D8 +:10C4500001010101010101020202010101010101C9 +:10C4600001010101010101020201010101010101BA +:10C4700001010101010101000101010101010101AD +:10C4800001010101010101000101000000010101A0 +:10C49000010101010101010001010101010101018D +:10C4A0000101000101010102020202020202020274 +:10C4B0000202010101010002020202020202020262 +:10C4C0000202020201010102020202020201020250 +:10C4D0000100010201010102020202020201020244 +:10C4E0000202020101010102020202020202020230 +:10C4F0000202020201000002020201020101010126 +:10C500000101010101010102020202020101010116 +:10C510000101010101000102020202010101020206 +:10C5200002020101010101020101010201010101F7 +:10C5300001010101010001020202020201010101E7 +:10C5400001010101010101020202020101010101D7 +:10C5500001010101010101020202020101010101C7 +:10C5600001010101010101020201010101010101B9 +:10C5700001010101010101000102020101010101AA +:10C58000010101010101010001010100000101019E +:10C59000010101010101010001010101010101018C +:10C5A0000101010101010102020202020202020272 +:10C5B0000202020101010002020202020202020260 +:10C5C000020202020201010202020202020102024E +:10C5D0000100010202010102020202020201020242 +:10C5E000020202010102020202020202020202022D +:10C5F0000202020201000002020202020101010124 +:10C600000101010101010102020202020102010114 +:10C610000101010101000102020202010101020205 +:10C6200002020202020201020101010201010101F2 +:10C6300001010101010001020202020202010101E5 +:10C6400001010101010101020202020202010101D4 +:10C6500001010101010101020202020101010101C6 +:10C6600001010101010101020202020101010101B6 +:10C6700001010101010101000102020101010101A9 +:10C68000010101010101010101010100000101019C +:10C69000010101010101010001010101010101018B +:10C6A0000101010101010102020202020202020271 +:10C6B000020202010102000202020202020202025E +:10C6C000020202020201020202020202020102024C +:10C6D000010101020201010202020202020202023F +:10C6E000020202010102020202020202020202022C +:10C6F0000202020201000102020202020201020120 +:10C700000101010101010102020202020102020112 +:10C710000102010101010102020202010101020202 +:10C7200002020202020201020101010202010101F0 +:10C7300001010101010001020202020202020101E3 +:10C7400001010101010101020202020202010101D3 +:10C7500001010101010101020202020201010101C4 +:10C7600001010101010101020202020101010101B5 +:10C7700001010101010101010102020101010101A7 +:10C78000010101010101010101010100000101019B +:10C79000010101010101010001010101010101018A +:10C7A0000101010101010102020202020202020270 +:10C7B000020202020102000202020202020202025C +:10C7C0000202020202020202020202020202020249 +:10C7D000010102020201010202020202020202023D +:10C7E000020202010202020202020202020202022A +:10C7F000020202020100010202020202020102021E +:10C800000101010101010102020202020102020111 +:10C8100002020201010101020202020101010202FF +:10C8200002020202020202020202010202010101EC +:10C8300001010101010001020202020202020101E2 +:10C8400001010101010101020202020202020101D1 +:10C8500001010101010101020202020202010101C2 +:10C8600001010101010101020202020101010101B4 +:10C8700001010101010101010102020202010101A4 +:10C88000010101010101010101010100000101019A +:10C890000101010101010100010101010101010189 +:10C8A000010101010101010202020202020202026F +:10C8B000020202020102000202020202020202025B +:10C8C0000202020202020202020202020202020248 +:10C8D000020102020201010202020202020202023B +:10C8E0000202020102020202020202020202020229 +:10C8F000020202020100010202020202020202021C +:10C90000020102010201010202020202010202010D +:10C9100002020202010101020202020201010202FC +:10C9200002020202020202020202010202020202E8 +:10C9300001010101010001020202020202020201E0 +:10C9400001010101010101020202020202020201CF +:10C9500001010101010101020202020202020101C0 +:10C9600001010101010101020202020201010101B2 +:10C9700001010101010101010102020202010101A3 +:10C980000101010101010101010101010102020195 +:10C990000101010101010100020101010101010187 +:10C9A000010101010101010202020202020202026E +:10C9B000020202020102000202020202020202025A +:10C9C0000202020202020202020202020202020247 +:10C9D000020102020201010202020202020202023A +:10C9E0000202020202020202020202020202020227 +:10C9F000020202020200010202020202020202021A +:10CA00000202020202020202020202020102020108 +:10CA100002020202020101020202020201010202FA +:10CA200002020202020202020202020202020202E6 +:10CA300001010101010101020202020202020202DD +:10CA400002010101010101020202020202020201CD +:10CA500001010101020101020202020202020201BD +:10CA600001010101010101020202020202010101B0 +:10CA700001010101010101010102020202010101A2 +:10CA80000101010101010101010101010102020293 +:10CA90000101010101010100020201010101010185 +:10CAA000010101010101010202020202020202026D +:10CAB0000202020201020002020202020202020259 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202000102020202020202020219 +:10CB00000202020202020202020202020202020106 +:10CB100002020202020101020202020202010202F8 +:10CB200002020202020202020202020202020202E5 +:10CB300001010201010101020202020202020202DB +:10CB400002010101010101020202020202020202CB +:10CB500002010101020101020202020202020202BA +:10CB600001010101010101020202020202010101AF +:10CB7000010101010101010102020202020202019E +:10CB80000101010101010101020101010102020291 +:10CB90000201010101010100020202010101010182 +:10CBA000010101010101010202020202020202026C +:10CBB0000202020202020002020202020202020257 +:10CBC0000202020202020200020202020202020247 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202000102020202020202020218 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020101020202020202020202F6 +:10CC200002020202020202020202020202020202E4 +:10CC300002010201010101020202020202020202D9 +:10CC400002020102020101020202020202020202C7 +:10CC500002010101020101020202020202020202B9 +:10CC600002010101010101020202020202020201AB +:10CC7000010101010101010202020202020202029B +:10CC8000010101010101010202010101010202028F +:10CC9000020202010101010002020201010101017F +:10CCA000010101010101010202020202020202026B +:10CCB0000202020202020002020202020202020256 +:10CCC0000202020202020202020202020202020046 +:10CCD0000202020000020202020202020202020238 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202000102020202020202020217 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020101020202020202020202F5 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020101020202020202020202D5 +:10CD400002020202020201020202020202020202C4 +:10CD500002020202020101020202020202020202B5 +:10CD600002020101010101020202020202020202A8 +:10CD7000010101010101010202020202020202029A +:10CD8000020101010101010202020101010202028C +:10CD9000020202020201010002020202010101017B +:10CDA000010101010101010202020202020202026A +:10CDB0000202020202020002020202020202020255 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020000020202020202020202020237 +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202000102020202020202020216 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020101020202020202020202F4 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020101020202020202020202D4 +:10CE400002020202020201020202020202020202C3 +:10CE500002020202020201020202020202020202B3 +:10CE600002020202020101020202020202020202A4 +:10CE70000201010101010102020202020202020298 +:10CE80000202010101010102020202010102020289 +:10CE90000202020202020100020202020201010178 +:10CEA0000101010101010102020202020202020269 +:10CEB0000202020202020002020202020202020254 +:10CEC0000202020202020202020202020202020242 +:10CED0000202000200020202020202020202020236 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202000202020202020202020214 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020102020202020202020202F2 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020101020202020202020202D3 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020201020202020202020202B2 +:10CF600002020202020201020202020202020202A2 +:10CF70000202010101010102020202020202020296 +:10CF80000202020101010102020202010102020287 +:10CF90000202020202020100020202020202020175 +:10CFA0000101010101010102020202020202020268 +:10CFB0000202020202020002020202020202020253 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202000202000202020202020202020235 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202000202020202020202020213 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020102020202020202020202D1 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020201020202020202020202A1 +:10D070000202020202010102020202020202020292 +:10D080000202020101010102020202010102020286 +:10D090000202020202020200020202020202020272 +:10D0A0000101010101010102020202020202020267 +:10D0B0000202020202020002020202020202020252 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202000202000202020202020202020234 +:10D0E0000202020202020202020202020202020220 +:10D0F0000202020202000202020202020202020212 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020102020202020202020202D0 +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D170000202020202020102020202020202020290 +:10D180000202020202020102020202020102020281 +:10D190000202020202020200020202020202020271 +:10D1A0000201010101010102020202020202020265 +:10D1B0000202020202020002020202020202020251 +:10D1C000020202020202020202020202020202023F +:10D1D0000202020202000202020202020202020231 +:10D1E000020202020202020202020202020202021F +:10D1F0000202020202000202020202020202020211 +:10D2000002020202020202020202020202020202FE +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020102020202020202020202CF +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202010202020202020202028F +:10D28000020202020202010202020202020202027F +:10D290000202020202020200020202020202020270 +:10D2A0000202010101010102020202020202020263 +:10D2B0000202020202020002020202020202020250 +:10D2C000020202020202020202020202020202023E +:10D2D0000202020202000202020202020202020230 +:10D2E000020202020202020202020202020202021E +:10D2F0000202020202000202020202020202020210 +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020102020202020202020202CE +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020201010202020202020202025F +:10D3B000020202020202000202020202020202024F +:10D3C000020202000202020202020202020202023F +:10D3D000020202020202020202020202020202022D +:10D3E000020202020202020202020202020202021D +:10D3F000020202020200020202020202020202020F +:10D4000002020202020202020202020202020202FC +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020202DC +:10D4300002020202020102020202020202020202CD +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202010202020202020202025D +:10D4B000020202020202000202020202020202024E +:10D4C0000202000002020202020202020202020240 +:10D4D000020202020202020202020202020202022C +:10D4E000020202020202020202020202020202021C +:10D4F000020202020201020202020202020202020D +:10D5000002020202020202020202020202020202FB +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020102020202020202020202CC +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A000020202020202010202020202020202025C +:10D5B000020202020202000202020202020202024D +:10D5C0000202000001010102020202020202020242 +:10D5D000020202000002020202020202020202022F +:10D5E000020202020202020202020202020202021B +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B0000201010101020002020202020202020250 +:10D6C0000101010101010102020202020202020241 +:10D6D000020202000002020202020202020202022E +:10D6E000020201010202020202020202020202021C +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A000020202020202020202020202020202015A +:10D7B0000101010101010102020202020101010154 +:10D7C0000101010101010102020202020202020240 +:10D7D000020202000002020202020202020201012F +:10D7E0000101010101010102020202020202020220 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A000020202020202020202020201010101015D +:10D8B0000101010101010102020201010101010155 +:10D8C0000101010101010102020202020202020041 +:10D8D0000101010000010102020202010101010136 +:10D8E000010101010101010202020202020202021F +:10D8F000020202020002010202020202020202020B +:10D9000002020202000002020202020202020202FB +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A000020202020202020202020101010101015D +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010102020202020202020040 +:10D9D0000101010100010101010101010101010138 +:10D9E000010101010101010202020202020202011F +:10D9F000010101010101010202020202020202020E +:10DA000002020202000002020202020202020202FA +:10DA100002020000020202020202020202020202EA +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA000020202020202020101010101010101015F +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010102020202010101010142 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010102020202010101010122 +:10DAF000010101010101010202020202020202020D +:10DB000002020101000002020202020202020202FB +:10DB100000000000020202020202020202020202ED +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA000020202020202020101010101010101015E +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF000010101010101010202020202020201010E +:10DC000001010101000001010202020202020202FE +:10DC100000000000020202020202020202020202EC +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA000020202020202020101010101010101015D +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010102020202010101010110 +:10DD000001010101010101010102020202020202FC +:10DD100000000101000101020202020202020202ED +:10DD200002020202020202020202020202020202D3 +:10DD300002020202020202020202020202020202C3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA000020202020202020101010101010101015C +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE000001010101010101010102020102010101FF +:10DE100001010101010101020202020202020202E9 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA000020202020202020101010101010101015B +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101020202020202020202E8 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA000020202020202020101010101010101015A +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101020202020202020202E7 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020201010101010101010159 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101020202020202020101E8 +:10E1200001010101010101020202020202020202D6 +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A0000202020202020201010101010101010158 +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101020202020202020202D5 +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E28000020202020202020202020202020202026E +:10E29000020202020202020202020202020202025E +:10E2A0000202020202020201010101010101010157 +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101020202020202020202D4 +:10E3300002020202020002020202020202020202BF +:10E3400002020202020202020202020202020202AD +:10E35000020202020202020202020202020202029D +:10E36000020202020202020202020202020202028D +:10E37000020202020202020202020202020202027D +:10E38000020202020202020202020202020202026D +:10E39000020202020202020202020202020202025D +:10E3A0000202020202020201010101010101010156 +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101020200000202020202D7 +:10E4300002020202020002020202020202020202BE +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A0000202020202020201010101010101010155 +:10E4B000010101010101010101010101010101014C +:10E4C000010101010101010101010101010101013C +:10E4D000010101010101010101010101010101012C +:10E4E000010101010101010101010101010101011C +:10E4F000010101010101010101010101010101010C +:10E5000001010101010101010101010101010101FB +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010200000101010101DC +:10E5300001010101010001020202020202020202C3 +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A0000202020202020201010101010101010154 +:10E5B000010101010101010101010101010101014B +:10E5C000010101010101010101010101010101013B +:10E5D000010101010101010101010101010101012B +:10E5E000010101010101010101010101010101011B +:10E5F000010101010101010101010101010101010B +:10E6000001010101010101010101010101010101FA +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101020202020202020202B1 +:10E65000020202020202020202020202020202029A +:10E66000020202020202020202020202020202028A +:10E670000202020202020202020101010101010181 +:10E680000101010101010102020202020202020271 +:10E69000020202020202020202020202020202025A +:10E6A0000202020202020201010101010101010153 +:10E6B000010101010101010101010101010101014A +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E000010101010101010101010101010101011A +:10E6F000010101010101010101010101010101010A +:10E7000001010101010101010101010101010101F9 +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010101010101010101D9 +:10E7300001010101010101010101010101010101C9 +:10E7400001010101010101010101010101010101B9 +:10E7500001010101010101020202020202020202A0 +:10E760000202020202020201010101010101010192 +:10E770000101010101010101010101010101010189 +:10E780000101010101010102020202020201010173 +:10E790000101010101010102020202020202020260 +:10E7A0000202020202020201010101010101010152 +:10E7B0000101010101010101010101010101010149 +:10E7C0000101010101010101010101010101010139 +:10E7D0000101010101010101010101010101010129 +:10E7E0000101010101010101010101010101010119 +:10E7F0000101010101010101010101010101010109 +:10E8000001010101010101010101010101010101F8 +:10E8100001010101010101010101010101010101E8 +:10E8200001010101010101010101010101010101D8 +:10E8300001010101010101010101010101010101C8 +:10E8400001010101010101010101010101010101B8 +:10E8500001010101010101010101010101010101A8 +:10E860000101010101010101010101010101010198 +:10E870000101010101010101010101010101010188 +:10E880000101010101010101010101010101010178 +:10E89000010101010101010202020202020202025F +:10E8A0000202020202020201010101010101010151 +:10E8B0000101010101010101010101010101010148 +:10E8C0000101010101010101010101010101010138 +:10E8D0000101010101010101010101010101010128 +:10E8E0000101010101010101010101010101010118 +:10E8F0000101010101010101010101010101010108 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010101010101010101D7 +:10E9300001010101010101010101010101010101C7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010101010101010101010177 +:10E990000101010101010100010101010101010168 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010101010101010101D6 +:10EA300001010101010101010101010101010101C6 +:10EA400001010101010101010101010101010101B6 +:10EA500001010101010101010101010101010101A6 +:10EA60000101010101010101010101010101010196 +:10EA70000101010101010101010101010101010186 +:10EA80000101010101010101010101010101010176 +:10EA9000010101010101010000000000000000006F +:10EAA000000000000000000101010101010101015D +:10EAB0000101010101010101010101010101010146 +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101020201010101010101F3 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101010101010101010101D5 +:10EB300001010101010101010101010101010101C5 +:10EB400001010101010101010101010101010101B5 +:10EB500001010101010101010101010101010101A5 +:10EB60000101010101010101010101010101010195 +:10EB70000101010101010101010101010101010185 +:10EB80000101010101010101010101010101010175 +:10EB9000010101010101010000000000000000006E +:10EBA000000000000000000101010101010101015C +:10EBB0000101010101010101010101010101010145 +:10EBC0000101010101010101010101010101010135 +:10EBD000010101010101010202020202020202021C +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202010101010101010101DD +:10EC200001010101010101010101010101010101D4 +:10EC300001010101010101010101010101010101C4 +:10EC400001010101010101010101010101010101B4 +:10EC500001010101010101010101010101010101A4 +:10EC60000101010101010101010101010101010194 +:10EC7000010101010101010202020202020202027B +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020200000000000000000066 +:10ECA000000000000000000101010101010101015B +:10ECB000010101010101010202020202020202023B +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202010101010101010101CC +:10ED300001010101010101010101010101010101C3 +:10ED400001010101010101010101010101010101B3 +:10ED500001010101010101010101010101010101A3 +:10ED6000010101010101010202020202020202028A +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020200000000000000000065 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA000000000000000004300000000000000001F +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000010000000000000000000000C0 +:10EF500000000000010000000000000000000000B0 +:10EF6000010100010100000000000000000000009D +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB000010101010101000000000000000000004B +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000100CF +:10F0400000000000010000000000000000000000BF +:10F0500000000000010000000000000000000000AF +:10F06000010100010100000000000000000001009B +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A000000000000000000000000000000000015F +:10F0B0000101010101010100000000000000000049 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000001010100000000000000000100CB +:10F1400000000000010000000000000000000000BE +:10F1500000010001010100000000000000000000AB +:10F160000101010101010000000000000000010098 +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000015E +:10F1B0000101010101010101010000010000000045 +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000010000000000000000000E +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000001010101000000000000000100C9 +:10F2400000000000010000000000000000000001BC +:10F2500000010001010100000000000000000101A8 +:10F260000101010101010000000000000000010097 +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000015D +:10F2B0000101010101010101010001010001000042 +:10F2C000000000000100000000000000000000003D +:10F2D000000000000000000000000000000000002E +:10F2E000000000010000000000000000000000001D +:10F2F000000000000000010000000000000000000D +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000001010101000000000000000100C8 +:10F3400000000001010100000000000000000001B9 +:10F3500000010101010100000000000000000101A6 +:10F360000101010101010000010000000000010095 +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000015C +:10F3B0000101010101010101010101010001000040 +:10F3C000000000000100000000000000000000003C +:10F3D000000000000000000000000000000000002D +:10F3E000000000010000000000000000000000001C +:10F3F000000000000000010000000100000000000B +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000001010101000000000000000100C7 +:10F4400000000001010100000000000000000101B7 +:10F4500000010101010100000000000000000101A5 +:10F460000101010101010100010000000001010092 +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000015B +:10F4B000010101010101010101010101010100003E +:10F4C000000000000100000000000000000000003B +:10F4D000000000000000000000000000000000002C +:10F4E000000000010000000000000000000000001B +:10F4F0000000010000000101010001010000000006 +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000001010101010100000000000100C4 +:10F5400000000001010100000000000000000101B6 +:10F5500000010101010100000100000000000101A3 +:10F560000101010101010101010000000001010090 +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000015A +:10F5B000010101010101010101010101010100003D +:10F5C000000000000100000000000000000000003A +:10F5D000000000000000000000000000010000002A +:10F5E000000000010000000000000000000000001A +:10F5F0000000010000000101010001010000000005 +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000001010000000000000000000000D8 +:10F6300000000001010101010100000000000100C3 +:10F6400000000001010101000000000000000101B4 +:10F6500000010101010101000100000000000101A1 +:10F66000010101010101010101000000000101008F +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A0000000000000000000000000000000000159 +:10F6B000010101010101010101010101010100003C +:10F6C0000000000001010000000000000000000038 +:10F6D0000000000000000000000000000100000029 +:10F6E0000000000100000000000000000000000019 +:10F6F0000100010000000101010001010000000003 +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000001010000000000000000000000D7 +:10F7300000000001010101010101000000000100C1 +:10F7400000000001010101010100000000000101B1 +:10F75000000101010101010101000000000001019F +:10F76000010101010101010101010001000101008C +:10F770000000000001000000000000000000000088 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000158 +:10F7B000010101010101010101010101010100003B +:10F7C0000000000001010000000000000000000037 +:10F7D0000000000000000000000000000100000028 +:10F7E0000000000100000000000000000000000018 +:10F7F0000100010000000101010001010100000001 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000001010100000000000000000000D5 +:10F8300000000001010101010101000000000100C0 +:10F8400000000001010101010100000000000101B0 +:10F85000000101010101010101000000000101019D +:10F86000010101010101010101010101000101008A +:10F870000000000001000000000000000000000087 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000157 +:10F8B000010101010101010101010101010100003A +:10F8C0000100000001010000000000000000000035 +:10F8D0000000000000010000000000000100000026 +:10F8E0000000000100000000000000000000000017 +:10F8F00001010100000001010100010101000000FF +:10F9000000000000000100000000000000000000F6 +:10F9100000000000000000000000000000000000E7 +:10F9200000000001010100000000000000000100D3 +:10F9300000000001010101010101000000000100BF +:10F9400000000001010101010100000000000101AF +:10F95000000101010101010101010000000101019B +:10F960000101010101010101010101010001010089 +:10F970000100000001010000000000000000000084 +:10F980000000000001000000000000000000000076 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000156 +:10F9B0000101010101010101010101010101000039 +:10F9C0000100000001010000000000000000000034 +:10F9D0000000000000010000000000000100000025 +:10F9E0000000000100000000000000000000000016 +:10F9F00001010100000001010100010101000000FE +:10FA000000000000000101000000000000000000F4 +:10FA100000000000000000000000000000000000E6 +:10FA200000000001010100000000000000000100D2 +:10FA300000000001010101010101000000010100BD +:10FA400000000001010101010100000000000101AE +:10FA5000000101010101010101010000000101019A +:10FA60000101010101010101010101010101010087 +:10FA70000100000001010000000000000000000083 +:10FA80000000000001000000000000000000000075 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000155 +:10FAB0000101010101010101010101010101000038 +:10FAC0000100000001010000000000000000000033 +:10FAD0000001000001010000000000000100000022 +:10FAE0000100000100000000000000000000000014 +:10FAF00001010101000001010101010101000000FB +:10FB000000000000000101000000000000000000F3 +:10FB100000000000000000000000000000000000E5 +:10FB200000000001010100000000000000000100D1 +:10FB300000000001010101010101000100010100BB +:10FB400000000001010101010101000000000101AC +:10FB50000001010101010101010100010001010198 +:10FB60000101010101010101010101010101010086 +:10FB70000101000101010000000000000000000080 +:10FB80000100000001010000000000000000000072 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000253 +:10FBB0000101010101010101010101010101000037 +:10FBC0000100000001010100000000000000010030 +:10FBD0000001000001010100000000000100000020 +:10FBE0000100000100000000000000000000000013 +:10FBF00001010101000001010101010101000000FA +:10FC000000000000000101000000000000000000F2 +:10FC100000000000000000000000000000000000E4 +:10FC200000000001010100000000000000000100D0 +:10FC300000000001010101010101010100010100B9 +:10FC400000000001010101010101000000000101AB +:10FC50000001010101010101010101010001010196 +:10FC60000101010101010101010101010101010184 +:10FC7000010100010101010000000000000001007D +:10FC80000100000001010000000000000000010070 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000252 +:10FCB0000101010101010101010101010101000036 +:10FCC000010101000101010000010000000001002C +:10FCD000000101010101010000000000010000001D +:10FCE0000100000101000000000000000000000011 +:10FCF00001010101000001010101010101000000F9 +:10FD000001000100000101010000000000000000EE +:10FD100000000000000000000000000000000000E3 +:10FD200000000001010100000000000000000100CF +:10FD300000000001010101010101010100010100B8 +:10FD400000000001010101010101000000000101AA +:10FD50000001010101010101010101010001010195 +:10FD60000101010101010101010101010101010183 +:10FD7000010101010101010001000000000001007A +:10FD8000010100010101000000000000000001006D +:10FD90000100000000000000000000000000000062 +:10FDA0000000000000000000000000000000000251 +:10FDB0000202020101010101010101010101000032 +:10FDC000010101000101010000010100000001002A +:10FDD000000101010101010000000000010000001C +:10FDE0000100000101000000000000000000000010 +:10FDF00001010101000001010101010101010101F5 +:10FE000001000100000101010000000000000000ED +:10FE100000000000000000000000000000000000E2 +:10FE200000000001010100000000000000000100CE +:10FE300000000001010101010101010100010100B7 +:10FE400000000001010101010101000000010101A8 +:10FE50000001010101010101010101010101010193 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010100010000000000010178 +:10FE8000010100010101010000000000000001006B +:10FE90000100000000000000000000000000000061 +:10FEA0000000000000000000000000000000000250 +:10FEB0000202020201010101010101010101000030 +:10FEC0000101010001010100000101000000010029 +:10FED000000101010101010000000000010000001B +:10FEE000010101010100000000000000000000000D +:10FEF00001010101000001010101010101010101F4 +:10FF000001010100000101010100000000000000EA +:10FF100000000000000000000000000000000000E1 +:10FF200000000001010101000000000000000100CC +:10FF300001000001010101010101010100010100B5 +:10FF400000000001010101010101000100010101A6 +:10FF50000001010101010101010101010101010192 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010100010000000000010177 +:10FF80000101010101010100010000000000010068 +:10FF90000100000000000000000000000000000060 +:10FFA000000000000000000000000000000000024F +:10FFB000020202020202010101010101010100002D +:10FFC0000101010001010100000101000101010125 +:10FFD000000101010101010000000000010000001A +:10FFE000010101010100000000000000000000000C +:10FFF00001010101000001010101010101010101F3 +:0200000270008C +:1000000001010100000101010100000000000000E9 +:1000100000000000000000000000000000000000E0 +:1000200000000001010101010100000000000101C8 +:1000300001000001010101010101010101010100B3 +:1000400000000001010101010101010100010101A4 +:100050000001010101010101010101010101010191 +:100060000101010101010101010101010101010180 +:100070000101010101010100010000000001010175 +:100080000101010101010100010000000001010165 +:10009000010000000000000000000000000000005F +:1000A000000000000000000000000000000000024E +:1000B000020202020202020101010101010100002B +:1000C0000101010101010100000101000101010123 +:1000D0000001010101010100000000000100000019 +:1000E000010101020100000000000000000000000A +:1000F00001010101000001010101010101010101F2 +:1001000001010100000101010100000000000000E8 +:1001100000000000000000000000000000000000DF +:1001200000000001010101010100000000000101C7 +:1001300001000001010101010101010101010100B2 +:1001400000000001010101010101010100010101A3 +:100150000001010101010101010101010101010190 +:10016000010101010101010101010101010101017F +:100170000101010101010101010100010001010171 +:100180000101010101010101010100010001010161 +:10019000010100000100000000000000000000005C +:1001A000000000000000000000000000000000024D +:1001B0000202020202020202010101010101000128 +:1001C0000101010101010100000101000101010122 +:1001D0000001010101010100000000000100000117 +:1001E0000101010201000000000000000000000108 +:1001F00001010101000001010101010101010101F1 +:1002000001010100000101010100000000000000E7 +:1002100000000000000000000000000000000000DE +:1002200000000001010101010100000000000101C6 +:1002300001000001010101010101010101010100B1 +:1002400000000001010101010101010101010101A1 +:10025000000101010101010101010101010101018F +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101000101016F +:10028000010101010101010101010101000101015F +:10029000010100000100000000000000000000005B +:1002A000000000000000000000000000000000024C +:1002B0000202020202020202020102020101000124 +:1002C000010101010101010101010100010101011F +:1002D0000101010101010100000000000100000115 +:1002E0000101010201000000000000000000000107 +:1002F00001010201000001010101010101010101EF +:1003000001010101000101010100000000000000E5 +:1003100001000000000100000000000000000001DA +:1003200000000001010101010100000000000101C5 +:1003300001010001010101010101010101010100AF +:10034000000000010101010101010101010101029F +:10035000000101010101010101010101010101018E +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101000101016E +:10038000010101010101010101010101000101015E +:100390000101010101010000000000000000000057 +:1003A000000000000000000000000000000000024B +:1003B0000202020202020202020202020101000122 +:1003C000010101010201010101010100010101011D +:1003D0000101010101010100000000000100000114 +:1003E0000101010201000000000000000000000106 +:1003F00002010201000002010101010101010101EC +:1004000001010101000101010100000000000101E2 +:1004100001000000000100000000000000000001D9 +:1004200001000001010101010100000000000101C3 +:1004300001010002010101010101010101010100AD +:10044000000000010101010101010101010101029E +:10045000000101010101010101010101010101028C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:100490000101010101010000000000000000000056 +:1004A000000000000000000000000000000000024A +:1004B000020202020202020202020202020200011F +:1004C000020101010201010101010100010101011B +:1004D0000101010101010100000000000100000113 +:1004E0000201010201010000000200000000000101 +:1004F00002020201010002010101010101010102E8 +:1005000001010101000101010101000000000101E0 +:1005100001000000000100000000000000000001D8 +:1005200001000001010101010100000000000101C2 +:1005300001010102010101010101010101010100AB +:100540000101000202010101010101010101010299 +:100550000102010101010101010101010101010289 +:100560000202010101010101010101010101010179 +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:100590000101010101010000000000000000000055 +:1005A0000000000000000000000000000000000249 +:1005B000020202020202020202020202020200011E +:1005C0000201010102020101010101000101010119 +:1005D0000102010101010100000000000100000111 +:1005E00002010102010100000002000002000101FD +:1005F00002020201010002020101020101010102E5 +:1006000001010101000101010101000000010101DE +:1006100001000000000100000000000000000001D7 +:1006200001010102010101010101000000000101BD +:1006300001010102020201010101010101010101A7 +:100640000101000202010101010101010101010298 +:100650000102020201010101010101010101010286 +:100660000202020201010101010101010101010176 +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:100690000101010101010100000000000000010052 +:1006A0000000000000000000000000000000000248 +:1006B000020202020202020202020202020200011D +:1006C0000202020102020101010101010101010214 +:1006D000010202010102010000000000010000020D +:1006E00002020202010100000201000002000101F9 +:1006F00002020202010002020201020201010102E1 +:1007000002010201010201010101000000010101D9 +:1007100001010100000100010000000000000001D3 +:1007200001010102010101010101000000010101BB +:1007300001010102020202010101010101010101A5 +:100740000101010202020101010101010101010295 +:100750000102020202010101010101010101010284 +:100760000202020201010101010101010101010175 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:10079000010101010101010101000000000001004F +:1007A0000000000000000000000000000000000247 +:1007B000020202020202020202020202020200021B +:1007C0000202020102020101010101010101010213 +:1007D000010202020102010000000000020000020A +:1007E00002020202020100000101000001000102F8 +:1007F00002020202010002020201020201010102E0 +:1008000002020201010202010101010001010101D4 +:1008100001010100000100010000000000010001D1 +:1008200001010102020101010101000000010101B9 +:1008300001010102020202010101010101010101A4 +:100840000101010202020101010101010101010294 +:100850000102020202020101010101010101010282 +:100860000202020202010101010101010101010173 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:10089000010101010101010101000000000101004D +:1008A0000000000000000000000000020000000244 +:1008B000020202020202020202020202020200021A +:1008C0000202020102020201010101010101010211 +:1008D0000102020202020200000000000200000207 +:1008E00002020202020100020101000001000102F5 +:1008F00002020202010002020201020202010102DE +:1009000002020201010202010101010101010101D2 +:1009100001010100000100010000000000010001D0 +:1009200001010102020201010101010000010102B5 +:1009300001010102020202020101010101010101A2 +:100940000101010202020201010101010101010292 +:100950000102020202020101010101010101010281 +:100960000202020202020101010101010101010171 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:10099000010101010101010101010001000101004A +:1009A0000000000000000000000000020000000243 +:1009B0000202020202020202020202020202000219 +:1009C000020202020202020101020101010101020E +:1009D0000102020202020200000002000201010202 +:1009E00002020202020100010101020001000102F3 +:1009F00002020202010002020202020202010102DC +:100A000002020201010202020101010101010102CF +:100A100001010100000101010000000000010102CC +:100A200001010102020201010101010000010102B4 +:100A300001010102020202020201010101010101A0 +:100A40000101010202020202010101010101010290 +:100A50000102020202020101010101010101010280 +:100A6000020202020202010101010101010101026F +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010255 +:100A90000101010101010101010101010001010048 +:100AA0000000000201000000000000010000000240 +:100AB0000202020202020202020202020202000218 +:100AC000020202020202020101020201010101020C +:100AD00002020202020202000202010202010102FB +:100AE00002020202020100010101020001000102F2 +:100AF00002020202010002020202020202010102DB +:100B000002020202010202020101010101010102CD +:100B100001010100000101010000000000010102CB +:100B200001010102020201010101010000010102B3 +:100B3000020101020202020202020101010102019C +:100B4000010101020202020202010101010101028E +:100B5000010202020202020101010101010101027E +:100B6000020202020202020101010101010101026D +:100B70000201010101010101010101010101010263 +:100B80000101010101010101010101010101010254 +:100B90000201010101010101010101010001010046 +:100BA000000000020100000000000001000000023F +:100BB0000202020202020202020202020202000217 +:100BC000020202020202020101020201010101020B +:100BD00002020202020202000101010102010102FD +:100BE00002020202020201010101010001000102F0 +:100BF00002020202010002020202020202010102DA +:100C000002020202010202020201010101010102CB +:100C100002010100000101010000000001010102C8 +:100C200001010102020201010101010000010102B2 +:100C3000020101020202020202020101010102029A +:100C4000010101020202020202010101010101028D +:100C5000010202020202020202010101010101027B +:100C6000020202020202020202010101010101026A +:100C70000202010101010101010101010101010261 +:100C80000201010101010101010101010101010252 +:100C90000201010101010101010101010101010044 +:100CA000000000010100000000000001000000023F +:100CB0000202020202020202020202020202000216 +:100CC0000202020202020202010202010201010208 +:100CD00002020202020202010101010102010102FB +:100CE00002020202020201010101010001000102EF +:100CF00002020202010102020202020202010102D8 +:100D000002020202010202020201010101010102CA +:100D100002010101000101010100000001010102C5 +:100D200002010102020202010101010000010102AF +:100D30000202010202020202020201010101020298 +:100D4000010101020202020202020101010102028A +:100D5000010202020202020202010101010101027A +:100D60000202020202020202020101010101010269 +:100D7000020202020201010101010101010101025D +:100D80000202010101010101010101010101010250 +:100D90000202010101010101010101010101010042 +:100DA000010001010100000000000001000000023C +:100DB0000202020202020202020202020202000215 +:100DC0000202020202020202020202010202020204 +:100DD00002020202020202010101010102010102FA +:100DE00002020202020201010101010001000102EE +:100DF00002020202020102020202020202020102D5 +:100E000002020202010202020201010101010102C9 +:100E100002020201000201010100010001010102C0 +:100E200002020202020202020101010200010102A9 +:100E30000202020202020202020202020101020294 +:100E40000202010202020202020201010101020287 +:100E50000102020202020202020201010101020277 +:100E60000202020202020202020201010101020266 +:100E7000020202020202010101010101010101025B +:100E8000020202020201010101010101010101024C +:100E90000202020101010101010101010101010040 +:100EA0000100000101000000020200010000010237 +:100EB0000202020202020202020202020202000214 +:100EC0000202020202020202020202010202020203 +:100ED00002020202020202010101010102010102F9 +:100EE00002020202020202020202010001000102E9 +:100EF00002020202020102020202020202020202D3 +:100F000002020202020202020202010101010102C6 +:100F100002020201000201010100010101010102BE +:100F200002020202020202020201010200010202A6 +:100F30000202020202020202020202020102020292 +:100F40000202020202020202020201010101020285 +:100F50000102020202020202020201010101020276 +:100F60000202020202020202020202020102020262 +:100F7000020202020202010101010101010101025A +:100F8000020202020202010101010101010101024A +:100F9000020202020101010101010101010101003E +:100FA0000100000000000200010202010000010235 +:100FB0000202020202020202020202020202000213 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202010101010102010102F8 +:100FE00002020202020202020202010002010202E5 +:100FF00002020202020102020202020202020202D2 +:1010000002020202020202020202020101010102C4 +:1010100002020201000201020100010101010102BC +:1010200002020202020202020201010100010202A6 +:101030000202020202020202020202020102020291 +:101040000202020202020202020202020101020282 +:101050000202020202020202020202020102020271 +:101060000202020202020202020202020102020261 +:101070000202020202020201010101010101010258 +:101080000202020202020101010101010101010249 +:10109000020202020201010101010101010101003C +:1010A0000001000000000100010102010200010234 +:1010B0000202020202020202020202020202000212 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202010101010102010102F7 +:1010E00002020202020202020202020002010202E3 +:1010F00002020202020102020202020202020202D1 +:1011000002020202020202020202020202020102C0 +:1011100002020201010201020100010101010102BA +:1011200002020202020202020201010102010202A3 +:10113000020202020202020202020202020202028F +:101140000202020202020202020202020102020280 +:101150000202020202020202020202020102020270 +:10116000020202020202020202020202020202025F +:101170000202020202020201010101010101010257 +:101180000202020202020201010101010101010247 +:10119000020202020202010101010101010101003A +:1011A0000000000000010100010101010100010235 +:1011B0000202020202020202020202020202000211 +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020102020102010102F3 +:1011E00002020202020202020202020002010202E2 +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202010202020100010101010102B7 +:1012200002020202020202020202010102010202A1 +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:101270000202020202020201020101010101010255 +:101280000202020202020201010101010101010246 +:101290000202020202020101010101010101010039 +:1012A0000000000000010102010101000100010233 +:1012B0000202020202020202020202020202000210 +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020102EF +:1012E00002020202020202020202020102020202DF +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202010202020101010101010102B5 +:1013200002020202020202020202010102010202A0 +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:101370000202020202020202020101010101010253 +:101380000202020202020202020101010101010243 +:101390000202020202020201010101010101010037 +:1013A0000000000000010101010101000102010231 +:1013B000020202020202020202020202020200020F +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020102EE +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202010202020201020102020102B0 +:10142000020202020202020202020201010102029F +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:101470000202020202020202020201010101010251 +:101480000202020202020202020201010101010241 +:101490000202020202020202010101010101010035 +:1014A0000000000000000001010101000101010233 +:1014B000020202020202020202020202020200020E +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202010202020201020202020102AE +:10152000020202020202020202020201010202029D +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202010102024D +:10158000020202020202020202020202010102023D +:101590000202020202020202020101010101010033 +:1015A0000000000000000001000101000101010233 +:1015B000020202020202020202020202020200020D +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020201020202020102AC +:10162000020202020202020202020201010202029C +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202010202024B +:10168000020202020202020202020202010202023B +:101690000202020202020202020201010101010031 +:1016A0000000000000000000000001000101010234 +:1016B000020202020202020202020202020200020C +:1016C00002020202020202020202020202020202FA +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202020202020202020202DA +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:10172000020202020202020202020201010202029B +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:10179000020202020202020202020202010101022C +:1017A0000000000000000000000000000001010235 +:1017B000020202020202020202020202020200020B +:1017C00002020202020202020202020202020202F9 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202020202020202020202D9 +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:10182000020202020202020202020201010202029A +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020102020229 +:1018A0000000000000000000000000000001010234 +:1018B000020202020202020202020202020200020A +:1018C00002020202020202020202020202020202F8 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202020202020202020202D8 +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020202A7 +:101920000202020202020202020202020102020298 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000200000000000000000000000001010231 +:1019B000020202020202020202020101010100020D +:1019C00002020202020202020202020202020202F7 +:1019D00002020202020202020202020202020202E7 +:1019E00002020202020202020202020202010202D8 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020102020297 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000200000000000000000000000001000231 +:101AB0000202020201010101010101010101010211 +:101AC00002020202020202020202020202020202F6 +:101AD00002020202020202020202020202020202E6 +:101AE00002020202020202020202010101010102DB +:101AF00002020202020202020202020202020202C6 +:101B000002020202020202020202020202020202B5 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020102020296 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA000020202000000000000000000000100012D +:101BB0000101010101010101010101010101010214 +:101BC00002020202020202020202020202020202F5 +:101BD00002020202020202020202020202020202E5 +:101BE00002020202020201010101010101010102DE +:101BF00002020202020202020202020202020202C5 +:101C000002020202020202020202020202020202B4 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA000020202000000000000000000000000012D +:101CB0000101010101010101010101010101010213 +:101CC00002020202020202020202020202020202F4 +:101CD00002020202020202020202020202020202E4 +:101CE00002020201010101010101010101010102E0 +:101CF00002020202020202020202020202020202C4 +:101D000002020202020202020202020202020202B3 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202000000000000000000000128 +:101DB0000101010101010101010101010101010212 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020201010101010202E8 +:101DE00001010101010101010101010101010102E2 +:101DF00002020202020202020202010101020202C6 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202000000000000000000000127 +:101EB0000101010101010101010101010101010211 +:101EC00002020202020202020201010101010202F7 +:101ED00002020202020101010101010101010101ED +:101EE00001010101010101010101010101010102E1 +:101EF00002020202020201010101010101010102CB +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020000000000000000000124 +:101FB0000101010101010101010101010101010210 +:101FC00002020202010101010101010101010102FC +:101FD00002010101010101010101010101010101F0 +:101FE00001010101010101010101010101010102E0 +:101FF00001010101010101010101010101010102D0 +:1020000002020202020202020202010101010202B4 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020200000000000000000121 +:1020B000010101010101010101010101010101020F +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010102CF +:1021000002020202020101010101010101010102B9 +:1021100002020202020202020202010101020202A2 +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020002000000000002011C +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010102BD +:1022100002020202020202010101010101010202A5 +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A0000202020202020202020200020000020115 +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010102BC +:1023100002020202020101010101010101010102A7 +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A0000202020202020202020202020000020112 +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010102AB +:102420000202020101010101010101010101010298 +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202010D +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101029A +:102530000202020101010101010101010101010287 +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202010C +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:102630000101010101010101010101010101010289 +:102640000202020101010101010101010101010276 +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202010B +:1026B000010101010101010101010101010101010A +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010278 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A000020202020202020202020202020202010A +:1027B0000101010101010101010101010101010109 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010277 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020109 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000201010101010101010101010101010265 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020108 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010265 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020028 +:102A90000000000000000000000000000000000234 +:102AA0000202020202020202020202020202020107 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010066 +:102B60000000000000000000000000000000000263 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020027 +:102B90000000000000000000000000000000000233 +:102BA0000202020202020202020202020202020106 +:102BB0000101010101010101010101010101010105 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101010101010101010101E5 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000101010101010101010101010101010164 +:102C60000101010101010101010101010101010253 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020026 +:102C90000000000000000000000000000000000232 +:102CA0000202020202020202020202020202020105 +:102CB0000101010101010101010101010101010104 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010173 +:102D50000101010101010101010101010101010163 +:102D60000101010101010101010101010101010153 +:102D70000101010101010101010101010101010044 +:102D80000000000000000000000000000000000142 +:102D90000101010101010101010101010101010024 +:102DA0000000000000000000000000000000000122 +:102DB0000101010101010101010101010101010103 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010132 +:102E90000101010101010101010101010101010023 +:102EA0000000000000000000000000000000000121 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010102E1 +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020162 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010022 +:102FA0000000000000000000000000000000000120 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010102F0 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020151 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:10308000010101010101010101010101010101022F +:103090000202020202020202020202020202020012 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A00000000000000000000000000000000040DF +:1031B000000000000000000000000000000000000F +:1031C00000000000010100000000000000000000FD +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B0000000000000000001000000010101010009 +:1032C00000000000010100000000000000000000FC +:1032D00000000000000000000000000000000000EE +:1032E00000000000000000000000000000000000DE +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000101000000004B +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B0000000000000000001010000010101010007 +:1033C00000000000010100000000000000000000FB +:1033D00000000000000000000000000000000000ED +:1033E00000000000000000010000000000000000DC +:1033F00000000000000000000000000000000000CD +:1034000000000000000000010000000100000000BA +:1034100000000000000001000000000000000000AB +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000101000000004A +:103480000100000001010000000000000000000039 +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B0000000000000000001010000010101010006 +:1034C00000000000010100000001000000000000F9 +:1034D00000000000000000000000000001000000EB +:1034E00000000000000000010100000000000000DA +:1034F00000000000000000000100000000000000CB +:1035000000000000000000010101000100000000B7 +:1035100000000000000001000000000100000000A9 +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:10354000000000000000000001000000000000007A +:103550000000000000000000000000010100000069 +:10356000000000000000000000000000000000005B +:103570000000000000000000000001010101000047 +:103580000100000001010100000000000000000037 +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B0000000000000000001010100010101010004 +:1035C00001000000010100000001010000000000F6 +:1035D00000000000000000000000000001000000EA +:1035E00000000000000000010100000000000000D9 +:1035F00000000000000000010100000000000000C9 +:1036000000000000000000010101010101000000B4 +:1036100000000000000001000101000100000000A6 +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:103640000000000000000001010000000000000078 +:103650000000000000000000010100010100000066 +:103660000000000000000000010000000000000059 +:103670000000000000000000010101010101010043 +:103680000100000001010100000000000000000036 +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B0000000000000000001010101010101010002 +:1036C00001000000010100000001010000000000F5 +:1036D00000000000000000010000000101000000E7 +:1036E00000000000000000010100000000000000D8 +:1036F00000000000000000010101000000000000C7 +:1037000000000000000000010101010101000000B3 +:1037100000000000000101010101010100000000A2 +:103720000000000000000000000000000000000099 +:103730000000000000000000010000000000000088 +:103740000000000000000001010100000000000076 +:103750000000000000000001010101010100000063 +:103760000000000000000101010001010100000053 +:103770000000000000000000010101010101010141 +:103780000100010101010100000000000000000033 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000001010101010101010001 +:1037C00001010000010100000001010000000000F3 +:1037D00000000000000001010000000101000000E5 +:1037E00000000000000000010100000000000000D7 +:1037F00000000000000001010101010000000000C4 +:1038000000000000000000010101010101010000B1 +:1038100000000000000101010101010100000000A1 +:103820000000000000000000010000000000000097 +:103830000000000000000000010001010100000084 +:103840000000000000000001010100010100000073 +:103850000000000000000001010101010100000062 +:103860000000000000010101010101010100000050 +:103870000000000000000000010101010101010140 +:103880000101010101010100000000000000000031 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B00000000000000000010101010101010101FF +:1038C00001010100010100000001010000000000F1 +:1038D00000000000000001010000000101000000E4 +:1038E00000000000000001010101000000000000D4 +:1038F00000000000000001010101010000000000C3 +:1039000000000000000000010101010101010100AF +:10391000010000000101010101010101000000009E +:103920000000000000000100010000000000000095 +:103930000000000000000000010101010100000082 +:103940000000000000000001010100010100000072 +:103950000000000000000001010101010100000061 +:10396000000000000001010101010101010000004F +:10397000000000000000000101010101010101013E +:103980000101010101010100000000000000000030 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B00000000000000000010101010101010101FE +:1039C00001010100010100010001010101000000ED +:1039D00000000000000001010000000101000000E3 +:1039E00000000000000001010101010000010000D1 +:1039F00000000000000001010101010101000000C0 +:103A000000000000000000010101010101010100AE +:103A1000010000000101010101010101000000009D +:103A20000000000000000100010100000000000093 +:103A30000000000000000001010101010100000080 +:103A4000000000000000010101010101010000006F +:103A5000000000000000000101010101010001005F +:103A6000010000000101010101010101010000004C +:103A7000000000000000000101010101010101013D +:103A8000010101010101010001000000000000002E +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB00000000000000000010101010101010101FD +:103AC00001010101010100010001010101000000EB +:103AD00000000000010101010000000101010000DF +:103AE00000000000000001010101010000010100CF +:103AF00001000000000001010101010101000000BE +:103B000000000000000000010101010101010100AD +:103B1000010000000101010101010101010000009B +:103B2000000000000000010101010101010100008D +:103B3000000000000000000101010101010000007F +:103B4000000000000001010101010101010000006D +:103B5000000000000000000101010101010101015C +:103B60000100010101010101010101010100000049 +:103B7000000000000000010101010101010101013B +:103B8000010101010101010101000000000000002C +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB00000000000000000010101010101010101FC +:103BC00001010101010100010001010101000000EA +:103BD00000000000010101010100000101010000DD +:103BE00000000000000101010101010101010100CB +:103BF00001000000000001010101010101000000BD +:103C000000000000000001010101010101010101AA +:103C10000100000001010101010101010100010099 +:103C2000000000000001010101010101010100008B +:103C3000000000000000000101010101010100007D +:103C4000000000000001010101010101010000006C +:103C5000000000000000000101010101010101015B +:103C60000100010101010101010101010100000048 +:103C70000100000001010101010101010101010137 +:103C8000010101010101010101000000000000002B +:103C90000000000000000001000000000000000023 +:103CA0000000000000000000000000000000000014 +:103CB00000000000000000010101010101010101FB +:103CC00001010101010100010001010101000000E9 +:103CD00000000000010101010100010101010000DB +:103CE00000000000000101010101010101010100CA +:103CF00001000000010101010101010101000000BA +:103D000000000000000001010101010101010101A9 +:103D10000100000001010101010101010101010196 +:103D2000000000000001010101010101010100008A +:103D3000000000000000010101010101010101007A +:103D40000100000001010101010101010100000069 +:103D50000100000000000001010101010101010159 +:103D60000100010101010101010101010101000145 +:103D70000100010001010101010101010101010135 +:103D80000101010101010101010001010100000027 +:103D90000000000000000001010000000000000021 +:103DA0000000000000000000000000000000000013 +:103DB00000000000000000010101010101010101FA +:103DC00001010101010100010001010101000000E8 +:103DD00000000000010101010101010101010000D9 +:103DE00001000000010101010101010101010101C6 +:103DF00001000100010101010101010101010000B7 +:103E000000000000000001010101010101010101A8 +:103E10000100010101010101010101010101010193 +:103E20000100000001010101010101010101010086 +:103E30000000000000000101010101010101010079 +:103E40000100000001010101010101010100000068 +:103E50000100000000000101010101010101010157 +:103E60000101010101010101010101010101010142 +:103E70000100010001010101010101010101010134 +:103E80000101010101010101010101010100000025 +:103E90000000000000000001010000000000000020 +:103EA0000000000000000000000000000000000012 +:103EB00000000000000000020101010101010101F8 +:103EC00001010101010100010101010101000000E6 +:103ED00001000000010101010101010101010000D7 +:103EE00001000000010101010101010101010101C5 +:103EF00001000100010101010101010101010100B5 +:103F000001000000000001010101010101010101A6 +:103F10000100010101010101010101010101010192 +:103F20000100010001010101010101010101010084 +:103F30000000000000000101010101010101010078 +:103F40000100000001010101010101010100000067 +:103F50000100000000000101010101010101010156 +:103F60000101010101010101010101010101010141 +:103F70000100010101010101010101010101010132 +:103F80000101010101010101010101010100000024 +:103F9000000000000000000101000000000000001F +:103FA0000000000000000000000000000000000011 +:103FB00000000000000000020101010101010101F7 +:103FC00001010101010100010101010101010000E4 +:103FD00001000000010101010101010101010100D5 +:103FE00001000000010101010101010101010101C4 +:103FF00001000100010101010101010101010100B4 +:1040000001000000000001010101010101010101A5 +:104010000100010101010101010101010101010191 +:104020000100010001010101010101010101010083 +:104030000000000001010101010101010101010174 +:104040000100010101010101010101010101000063 +:104050000100000000000101010101010101010155 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:104080000101010101010101010101010100000023 +:10409000000000000000000101000100000000001D +:1040A0000000000000000000000000000000000010 +:1040B00000000000000000020101010101010201F5 +:1040C00001010101010100010101010101010100E2 +:1040D00001000000010101010101010101010101D3 +:1040E00001000000010101020101010101010101C2 +:1040F00001000100010101010101010101010100B3 +:1041000001000000010101010101010101010101A2 +:104110000100010101010101010101010101010190 +:104120000100010101010101010101010101010081 +:104130000000000001010101010101010101010173 +:104140000100010101010101010101010101010061 +:104150000100000001010101010101010101010152 +:10416000010101010101010101010101010101013F +:10417000010101010101010101010101010101012F +:104180000101010101010101010101010101000021 +:10419000000000000000000101010100000000001B +:1041A000000000000000000000000000000000000F +:1041B00000000000000000020201010101010201F3 +:1041C00001010101010100010101010101010101E0 +:1041D00001000100010101020101010101010101D0 +:1041E00001000000010101020101010101010101C1 +:1041F00001000101010101010101010101010101B0 +:1042000001000000010101020101010101010101A0 +:10421000010001010101010101010101010101018F +:104220000100010101010101010101010101010080 +:104230000100000001010101010101010101010171 +:10424000010001010101010101010101010101015F +:10425000010001010101010101010101010101014F +:10426000010101010101010101010101010101013E +:10427000010101010101010101010101010101012E +:10428000010101010101010101010101010101001F +:104290000100000000000001010101010100000017 +:1042A000000000000000000000000000000000000E +:1042B00000000000000000020202010201010201F0 +:1042C00001010101010100010102010101010101DE +:1042D00001000100010101020101010101010101CF +:1042E00001000100010101020101010101010101BF +:1042F00001010101010101020101010101010101AD +:10430000010000000101010201010101010101019F +:10431000010001010101010101010101010101018E +:10432000010001010101010101010101010101017E +:10433000010001010101010101010101010101016E +:10434000010101010101010101010101010101015D +:10435000010001010101010101010101010101014E +:10436000010101010101010101010101010101013D +:10437000010101010101010101010101010101012D +:10438000010101010101010101010101010101011D +:104390000100000100000001010101010100000015 +:1043A000000000000000000000000000000000000D +:1043B00000000000000000020202010202020201ED +:1043C00001010101010100020102010101010101DC +:1043D00001000101010101020101010101010101CD +:1043E00001000100010101020201010101010101BD +:1043F00001010101010101020101010101010101AC +:10440000010000000101010201010101010101019E +:10441000010001010101010201010101010101018C +:10442000010101010101010101010101010101017C +:10443000010001010101010101010101010101016D +:10444000010101010101010201010101010101015B +:10445000010001010101010101010101010101014D +:10446000010101010101010101010101010101013C +:10447000010101010101010101010101010101012C +:10448000010101010101010101010101010101011C +:104490000100000101010001010101010101000011 +:1044A000000000000000000000000000000000000C +:1044B00000000000000000020202020202020201EB +:1044C00001020101010100020102020101010101D9 +:1044D00001000101010101020101010101010101CC +:1044E00001000100010101020201010101010101BC +:1044F00001010101010101020201010101010101AA +:10450000010000000101010202020101010101019B +:10451000010001010101010201010101010101018B +:10452000010101010101010101010101010101017B +:10453000010001010101010101010101010101016C +:10454000010101010101010201010101010101015A +:10455000010101010101010201010101010101014A +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101011B +:10459000010001010101000101010101010101000E +:1045A0000000000000000000000200000000000009 +:1045B00000000000000000020202020202020201EA +:1045C00002020101010100020102020101010101D7 +:1045D00001000101010101020101010202010101C9 +:1045E00001000100010101020202010101010101BA +:1045F00001010101010101020202010101010101A8 +:10460000010000000101010202020101010101019A +:104610000100010101010102020201010101010188 +:104620000101010101010102010101010101010179 +:10463000010101010101010101010101010101016A +:104640000101010101010102020101010101010158 +:104650000101010101010102010101010101010149 +:104660000101010101010102010101010101010139 +:10467000010101010101010101010101010101012A +:104680000101010101010102010101010101010119 +:10469000010101010101000101010101010101010B +:1046A0000000000000000000000200000000000008 +:1046B00000000000000000020202020202020202E8 +:1046C00002020101020200020102020101010101D4 +:1046D00001000101010101020201010202010101C7 +:1046E00001000100010101020202010101010101B9 +:1046F00001010101010101020202010101010101A7 +:104700000100000001010102020202020101010197 +:104710000100010101010102020201010101010187 +:104720000101010101010102020101010101010177 +:104730000101010101010102010101010101010168 +:104740000101010101010102020201010101010156 +:104750000101010101010102020201010101010146 +:104760000101010101010102010101010101010138 +:104770000101010101010102010101010101010128 +:104780000101010101010102010101010101010118 +:104790000101010101010102010101010101010108 +:1047A0000100000001000000000200000000000005 +:1047B00000000000000000020202020202020202E7 +:1047C00002020201020200020102020201010101D1 +:1047D00001000101010101020202010202010101C5 +:1047E00001000100010101020202020101010101B7 +:1047F00001010101010101020202020101010101A5 +:104800000100000001010102020202020101010196 +:104810000100010101010102020202020101010184 +:104820000101010101010102020201010101010175 +:104830000101010101010102020101010101010166 +:104840000101010101010102020201010101010155 +:104850000101010101010102020201010101010145 +:104860000101010101010102020101010101010136 +:104870000101010101010102020202010101010124 +:104880000101010101010102020101010101010116 +:104890000101010101010102010101010101010107 +:1048A0000100010101000000000200000000000002 +:1048B00000000000000000020202020202020202E6 +:1048C00002020201020200020202020202010101CE +:1048D00001010101010101020202020202020101C1 +:1048E00001000100010101020202020101020101B5 +:1048F00001010101010101020202020101010101A4 +:104900000100000001010102020202020201010194 +:104910000101010101010102020202020101010182 +:104920000101010101010102020201010101010174 +:104930000101010101010102020201010101010164 +:104940000101010101010102020201010101010154 +:104950000101010101010102020202020101010142 +:104960000101010101010102020201010101010134 +:104970000101010101010102020202020101010122 +:104980000101010101010102020101010101010115 +:104990000101010101010102010101010101010106 +:1049A0000101010101010000000100000000000000 +:1049B00000000000010000020202020202020202E4 +:1049C00002020202020200020202020202010101CC +:1049D00001010101010101020202020202020101C0 +:1049E00001000100010101020202020201020201B2 +:1049F00001010101010101020202020201010101A2 +:104A00000100000101010102020202020202010191 +:104A10000101010101010102020202020101010181 +:104A20000101010101010102020202010101010172 +:104A30000101010101010102020202010101010162 +:104A40000101010101010102020202020101010151 +:104A50000101010101010102020202020201010140 +:104A60000101010101010102020202010101010132 +:104A70000101010101010102020202020101010121 +:104A80000101010101010102020201010101010113 +:104A90000101010101010102020101010101010104 +:104AA00001010101010101000001010000000000FD +:104AB00000000000010000020202020202020202E3 +:104AC00002020202020200020202020202010101CB +:104AD00001010101010101020202020202020101BF +:104AE00001000101010101020202020202020201AF +:104AF000020101010101010202020202020101019F +:104B0000010000010101010202020202020202018F +:104B10000101010101010102020202020101010180 +:104B20000101010101010102020202020101010170 +:104B30000101010101010102020202020101010160 +:104B4000010101010101010202020202020101014F +:104B5000010101010101010202020202020101013F +:104B60000101010101010102020202020101010130 +:104B7000010101010101010202020202020201011E +:104B80000101010101010102020202010101010111 +:104B90000101010101010102020101010101010103 +:104BA00001010101010101000001010000000000FC +:104BB00000000000010000020202020202020202E2 +:104BC00002020202020200020202020202020101C9 +:104BD00001010101010102020202020202020201BC +:104BE00002010101010102020202020202020202AA +:104BF000020101010101020202020202020101019D +:104C0000010000010101010202020202020202018E +:104C1000020101010101020202020202020101017C +:104C2000010101010101010202020202020201016D +:104C3000010101010101010202020202020101015E +:104C4000010101010101010202020202020101014E +:104C5000010101010101010202020202020101013E +:104C6000010101010101010202020202020101012E +:104C7000010101010101010202020202020202011C +:104C8000020101010101010202020202010101010E +:104C90000101010101010102020201010101010101 +:104CA00001010101010101000001010000000000FB +:104CB00000000000010000020202020202020202E1 +:104CC00002020202020200020202020202020201C7 +:104CD00002010101020202020202020202020202B7 +:104CE00002010101010202020202020202020202A8 +:104CF000020102010101020202020202020201019A +:104D0000010000010101010202020202020202028C +:104D10000201010101020202020202020202020178 +:104D2000010101010101010202020202020201016C +:104D3000010101010101010202020202020101015D +:104D4000010101010101010202020202020101014D +:104D5000010101010101010202020202020202013B +:104D6000010101010101010202020202020101012D +:104D7000010101010101010202020202020202021A +:104D8000020101010101010202020202020101010C +:104D900001010101010101020202020101010101FF +:104DA00001010101010101000101010000000000F9 +:104DB00000000000010100020202020202020202DF +:104DC00002020202020200020202020202020202C5 +:104DD00002010101020202020202020202020202B6 +:104DE00002010101020202020202020202020202A6 +:104DF0000201020102020202020202020202020196 +:104E0000010001010101010202020202020202028A +:104E10000201010102020202020202020202020275 +:104E2000010101010101010202020202020202016A +:104E3000010101010101010202020202020201015B +:104E4000010101010101010202020202020101014C +:104E50000101010101010102020202020202020239 +:104E6000020101010101010202020202020101012B +:104E70000101010101010102020202020202020219 +:104E80000202020102020102020202020201010107 +:104E900001010101010101020202020101010101FE +:104EA00001010101010101000101000101000001F6 +:104EB00000000000010101020202020202020202DD +:104EC00002020202020200020202020202020202C4 +:104ED00002010201020202020202020202020202B4 +:104EE00002010201020202020202020202020202A4 +:104EF0000202020102020202020202020202020194 +:104F00000202010101010102020202020202020286 +:104F10000201020102020202020202020202020273 +:104F20000201010101010202020202020202020167 +:104F30000101010101010102020202020202020159 +:104F4000010101010101010202020202020201014A +:104F50000201010101010102020202020202020237 +:104F60000201020101020202020202020202010126 +:104F70000101010101010102020202020202020218 +:104F80000202020202020202020202020202010103 +:104F900001010101010101020202020201010101FC +:104FA00001010101010101000100000101000001F6 +:104FB00000000000010101020202020202020202DC +:104FC00002020202020200020202020202020202C3 +:104FD00002010201020202020202020202020202B3 +:104FE00002010201020202020202020202020202A3 +:104FF0000202020202020202020202020202020291 +:105000000201010101010202020202020202020285 +:105010000201020202020202020202020202020271 +:105020000201020101020202020202020202020164 +:105030000101010101010102020202020202020158 +:105040000201010101010102020202020202020147 +:105050000201010101010102020202020202020236 +:105060000202020202020202020202020202020220 +:105070000201010101010102020202020202020216 +:105080000202020202020202020202020202020101 +:1050900001010101010101020202020202010101FA +:1050A00001010101010101000000000101000001F6 +:1050B00000000001010101020202020202020202DA +:1050C00002020202020200020202020202020202C2 +:1050D00002010202020202020202020202020202B1 +:1050E00002010201020202020202020202020202A2 +:1050F0000202020202020202020202020202020290 +:105100000201010101010202020202020202020284 +:105110000201020202020202020202020202020270 +:105120000201020102020202020202020202020261 +:105130000201010101010202020202020202020254 +:105140000201010101020202020202020202020243 +:105150000201010101010102020202020202020235 +:10516000020202020202020202020202020202021F +:105170000201020101010102020202020202020214 +:1051800002020202020202020202020202020202FF +:1051900002010101010101020202020202020101F7 +:1051A00001010101010101000000000101000001F5 +:1051B00001000101010101020202020202020202D7 +:1051C00002020202020200020202020202020202C1 +:1051D00002020202020202020202020202020202AF +:1051E00002010201020202020202020202020202A1 +:1051F000020202020202020202020202020202028F +:105200000201010102020202020202020202020281 +:10521000020102020202020202020202020202026F +:10522000020202020202020202020202020202025E +:105230000201020102020202020202020202020250 +:105240000201020102020202020202020202020240 +:105250000201020101010202020202020202020232 +:10526000020202020202020202020202020202021E +:10527000020202010202020202020202020202020F +:1052800002020202020202020202020202020202FE +:1052900002010101010101020202020202020201F5 +:1052A00001010101010101000000000101000001F4 +:1052B00001000101010101020202020202020202D6 +:1052C00002020202020200020202020202020202C0 +:1052D00002020202020202020202020202020202AE +:1052E000020202010202020202020202020202029F +:1052F000020202020202020202020202020202028E +:105300000201010102020202020202020202020280 +:10531000020102020202020202020202020202026E +:10532000020202020202020202020202020202025D +:10533000020202020202020202020202020202024D +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202010101020202020202020202F0 +:1053A00001010101010101000000000001000101F3 +:1053B00001000101010101020202020202020202D5 +:1053C00002020202020200020202020202020202BF +:1053D00002020202020202020202020202020202AD +:1053E000020202020202020202020202020202029D +:1053F000020202020202020202020202020202028D +:10540000020101010202020202020202020202027F +:10541000020202020202020202020202020202026C +:10542000020202020202020202020202020202025C +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020201020202020202020202ED +:1054A00002010101010101000000000000000100F3 +:1054B00001010101000101020202020202020202D4 +:1054C00002020202020200020202020202020202BE +:1054D00002020202020202020202020202020202AC +:1054E000020202020202020202020202020202029C +:1054F000020202020202020202020202020202028C +:10550000020101010202020202020202020202027E +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020201020202020202020202EC +:1055A00002020201010101000000000000000100F0 +:1055B00001010101000101020202020202020102D4 +:1055C00002020202020200020202020202020202BD +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020101020202020202020202020202027C +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020202020101000000000000010100EC +:1056B00001010101000101020202020202020102D3 +:1056C00002010202020200020202020202020202BD +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:10570000020102020202020202020202020202027A +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020201000000000000010100EA +:1057B00000010101000001020202020202020102D4 +:1057C00002010202020200020202020202020202BC +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020000000000010000E7 +:1058B00000010001000001020202020202020102D4 +:1058C00002010202020200020202020202020202BB +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020000000000010000E6 +:1059B00000000000000000020202020202020102D6 +:1059C00002010202020200020202020202020202BA +:1059D00002020202020202020202020202020202A7 +:1059E0000202020202020202020202020202020297 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A40000202020202020202020202020202020236 +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002020202020202020202020202020202E6 +:105AA00002020202020202020200000000000000E4 +:105AB00000000000000000020202020202020101D6 +:105AC00001010101020201020202020202020202BB +:105AD00002020202020202020202020202020202A6 +:105AE0000202020202020202020202020202020296 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020202020202020202020202020202E5 +:105BA00002020202020202020202000000000000E1 +:105BB00000000000000000020202020101010101D8 +:105BC00001010101010101020202020202020202BC +:105BD00002020202020202020202020202020202A5 +:105BE0000202020202020202020202020202020295 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020202020202020202020202020202E4 +:105CA00002020202020202020202020000000000DE +:105CB00000000000000000010101010101010101DB +:105CC00001010101010101020202020202020202BB +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202020202020202020294 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020202020202020202020202E3 +:105DA00002020202020202020202020200000000DB +:105DB00000000000000000010101010101010101DA +:105DC00001010101010101020202020202020202BA +:105DD00002020202020202020202020000000000AD +:105DE00000000000000000020202020202020202A1 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202000000D8 +:105EB00000000000000000010101010101010101D9 +:105EC00001010101010101020202020202020202B9 +:105ED00002020202020202000000000000000000B4 +:105EE00000000000000000020202020202010101A3 +:105EF0000101010101010102020202020202020289 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202000000D7 +:105FB00000000000000000010101010101010001D9 +:105FC00001010101010101020201010101010101BF +:105FD00001010101010101000000000101010101B5 +:105FE0000101010101010102020202020202020298 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00000000000020000010101010101010001D6 +:1060C00001000101010101010101010101010101C1 +:1060D00001010101010101010101010101010101B0 +:1060E00001010101010101010101010101000000A3 +:1060F000000000000000000202020202020202028E +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002000202020202010101010101010001CB +:1061C00001000101010101010101010101010101C0 +:1061D00001010101010101010101010101010101AF +:1061E000010101010101010202020202020000009C +:1061F000000000000000000202020202020202028D +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202010101010101010001C8 +:1062C00001000101010101010101010101010101BF +:1062D00001010101010101010101010101010101AE +:1062E000010101010101010101010101010101019E +:1062F0000101010101010102020202020202020285 +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202010101010101010001C7 +:1063C00001000101010101010101010101010101BE +:1063D00001010101010101010101010101010101AD +:1063E000010101010101010101010101010101019D +:1063F000010101010101010101010101010101018D +:106400000101010101010102020202020202020273 +:106410000202020202020201010101010101010165 +:10642000010101010101010101010101010101015C +:106430000101010101010102020202020202020243 +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202010101010101010101C5 +:1064C00001010101010101010101010101010101BC +:1064D00001010101010101010101010101010101AC +:1064E000010101010101010101010101010101019C +:1064F000010101010101010101010101010101018C +:10650000010101010101010101010101010101017B +:106510000101010101010102020202020202020262 +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202010101010101010101C4 +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101018B +:10660000010101010101010101010101010101017A +:106610000101010101010100000000000000000073 +:10662000000000000000000000000000000000006A +:106630000000000000000002020202020202020248 +:106640000202020202020201010101010101010133 +:10665000010101010101010101010101010101012A +:106660000101010101010102020202020202020211 +:1066700002020202020202020202020202020202FA +:1066800002020202020202010101010101010101F3 +:1066900001010101010101010101010101010101EA +:1066A00001010101010101020202020202020202D1 +:1066B00002020202020202010101010101010101C3 +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101010101010101010101AA +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101018A +:106700000101010101010101010101010101010179 +:106710000101010101010101010101010101010169 +:106720000101010101010100000000000000000062 +:106730000000000000000002020202020202020247 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202010101010101010101C2 +:1067C00001010101010101010101010101010101B9 +:1067D00001010101010101010101010101010101A9 +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010178 +:106810000101010101010101010101010101010168 +:106820000101010101010101010101010101010158 +:106830000101010101010101010101010101010148 +:106840000101010101010101010101010101010138 +:106850000101010101010100000000000000000031 +:106860000000000000000002020202020202020216 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202000000000000000000FA +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000020202020202020202D6 +:1068B00002020202020202010101010101010101C1 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010147 +:106940000101010101010101010101010101010137 +:106950000101010101010100000000000000000030 +:10696000000000000000000101010101010101011E +:1069700001010101010101020202020202020202FE +:1069800002020202020202000000000000000000F9 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000020202020202020202D5 +:1069B00002020202020202010101010101010101C0 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101010101010101010101A7 +:1069E0000101010101010101010101010101010197 +:1069F0000101010101010101010101010101010187 +:106A00000101010101010101010101010101010176 +:106A10000101010101010101010101010101010166 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000101010101010101010101010101010136 +:106A50000101010101010101010101010101010126 +:106A60000101010101010101010101010101010116 +:106A70000101010101010101010101010101010106 +:106A800001010101010101000000000000000000FF +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000020202020202020202D4 +:106AB00002020202020202010101010101010101BF +:106AC00001010101010101010101010101010101B6 +:106AD00001010101010101010101010101010101A6 +:106AE0000101010101010101010101010101010196 +:106AF0000101010101010101010101010101010186 +:106B00000101010101010101010101010101010175 +:106B10000101010101010101010101010101010165 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B700001010101010101020202020202020202FC +:106B800002020202020202000000000000000000F7 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000020202020202020202D3 +:106BB00002020202020202010101010101010101BE +:106BC00001010101010101010101010101010101B5 +:106BD00001010101010101010101010101010101A5 +:106BE0000101010101010101010101010101010195 +:106BF0000101010101010101010101010101010185 +:106C00000101010101010101010101010101010174 +:106C10000101010101010101010101010101010164 +:106C20000101010101010101010101010101010154 +:106C30000101010101010101010101010101010144 +:106C40000101010101010101010101010101010134 +:106C50000101010101010101010101010101010124 +:106C60000101010101010101010101010101010114 +:106C70000101010101010101010101010101010104 +:106C800001010101010101010101010101010101F4 +:106C900001010101010101010101010101010101E4 +:106CA00001010101010101000000000000000000DD +:106CB00000000000000000010101010101010101CB +:106CC00001010101010101010101010101010101B4 +:106CD00001010101010101010101010101010101A4 +:106CE0000101010101010101010101010101010194 +:106CF0000101010101010101010101010101010184 +:106D00000101010101010101010101010101010173 +:106D10000101010101010101010101010101010163 +:106D20000101010101010101010101010101010153 +:106D30000101010101010101010101010101010143 +:106D40000101010101010101010101010101010133 +:106D50000101010101010101010101010101010123 +:106D60000101010101010101010101010101010113 +:106D70000101010101010101010101010101010103 +:106D800001010101010101010101010101010101F3 +:106D900001010101010101010101010101010101E3 +:106DA00001010101010101000000000000000000DC +:106DB00000000000000000010101010101010101CA +:106DC00001010101010101010101010101010101B3 +:106DD00001010101010101010101010101010101A3 +:106DE0000101010101010101010101010101010193 +:106DF0000101010101010101010101010101010183 +:106E00000101010101010101010101010101010172 +:106E10000101010101010101010101010101010162 +:106E20000101010101010101010101010101010152 +:106E30000101010101010101010101010101010142 +:106E40000101010101010101010101010101010132 +:106E50000101010101010101010101010101010122 +:106E60000101010101010101010101010101010112 +:106E70000101010101010101010101010101010102 +:106E800001010101010101010101010101010101F2 +:106E900001010101010101010101010101010101E2 +:106EA00001010101010101000000000000000000DB +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000020202020202020202A0 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F70000202020202020200000000000000000003 +:106F800000000000000000020202020202020202EF +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202000000000000000000D3 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:10704000000000000000000202020202020202022E +:107050000202020202020200000000000000000022 +:10706000000000000000000202020202020202020E +:107070000202020202020200000000000000000002 +:107080000000000000000000000000000000000000 +:1070900000000000000000020202020202020202DE +:1070A00002020202020202000000000000000000D2 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B000000000000000003B000000000000000094 +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000001007D +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000001010000010000000101000000B9 +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000001007C +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000001010000010000010101010000B6 +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000101007A +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000001010000010100010101010000B4 +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:107500000000000101000000000000000001010077 +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00001010001010000010100010101010000B1 +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:107600000000000101000000000000000001010076 +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:107640000000000000000000000000000000010039 +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00001010001010000010101010101010000AF +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000101010000000000000001010074 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000010038 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00001010101010000010101010101010000AD +:1077D00001000000000000000000000000000000A8 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000101010100000000000001010072 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000101010000000000000000000001010033 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00001010101010100010101010101010000AB +:1078D00001000000000000000000000000000000A7 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000101010101000000000001010070 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000010046 +:10794000010101010100000001000000000101002F +:107950000000000000000000000000000000000027 +:107960000101010000000000000000000000010013 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000001C6 +:1079C00001010101010101010101010101010001A8 +:1079D00001010000000000000000000000000000A5 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A0000000000010101010100000000000101006F +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000010055 +:107A30000000000000000000000000000000010144 +:107A4000010101010100000001000000000101012D +:107A50000101010000000000000000000000000023 +:107A60000101010101000000000000000000010010 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000010000000000000000000000E5 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000001C5 +:107AC00001010101010101010101010101010001A7 +:107AD00001010000000000000000000000000000A4 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000010085 +:107B0000000000010101010101020000000101006B +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000010054 +:107B30000100000000000000000000000001010141 +:107B4000010101010101000001000000000101012B +:107B5000010101010100000000000000000000011F +:107B6000010101010100000000000000000001000F +:107B70000000000000000000000000000000000005 +:107B800001000000000000000000000000000000F4 +:107B900000000000010000000000000000010100E2 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000001C4 +:107BC00001010101010101010101010101010001A6 +:107BD00001010100000000000000000000010100A0 +:107BE0000000000100000000000000000000000094 +:107BF0000000000101000000000000000000010082 +:107C0000010000010101010101010000000101006A +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000010053 +:107C3000010000000000000001000000000101013F +:107C40000101010101010100010001000001010128 +:107C5000010101010100000000000000000000011E +:107C6000010101010101000101000000000001000B +:107C70000000000000000000000000000000000004 +:107C800001000000000000000000000000000000F3 +:107C900000000000010000010100000000010100DF +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000001C3 +:107CC00001010101010101010101010101010001A5 +:107CD000010101000000000000000000000101009F +:107CE0000000000100000000000000000000000093 +:107CF0000000000101000000000000000000010081 +:107D00000100000101010101010100020001010067 +:107D10000000000000000000000000000000000063 +:107D20000000000001000000000000000000010150 +:107D3000010101000000000001000000000101013C +:107D40000101010101010101010101010001010124 +:107D5000010101010100000000000000000000011D +:107D60000101010101010101010000000001010008 +:107D70000000000000000000000000000000000003 +:107D800001010100000000000000000000000000F0 +:107D900001000100010001010100010000010100DA +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000001C2 +:107DC00001010101010101010101010101010001A4 +:107DD000010101000000000000000000000101009E +:107DE0000000000101000000000000000000000091 +:107DF000000000010101000000000000000001017E +:107E00000101000101010101010102010001010064 +:107E10000000000000000000000000000000000062 +:107E2000010101000100000000000000000101014B +:107E30000101010101000000010000000001010139 +:107E40000101010101010101010101010001010123 +:107E5000010101010100000000000000000001011B +:107E60000101010101010101010100010001010005 +:107E70000000000001000000000000000000000001 +:107E800001010101010000000000000000000000ED +:107E900001000101010101010101010100010100D5 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000001C1 +:107EC00001010101010101010101010101010001A3 +:107ED000010101000100000000000000010101019A +:107EE000010000010100000000000000000000008F +:107EF000000000010101000000000000000001017D +:107F00000101000101010101010101010001010064 +:107F10000000000000000000000000000000000061 +:107F2000010101000100000000000000000101014A +:107F30000101010101000100010000000001010137 +:107F40000101010101010101010101010001010122 +:107F50000101010101010001000000000000010118 +:107F60000101010101010101010101010001010003 +:107F700001010100010000000000000000000001FC +:107F800001010101010000000000000000010100EA +:107F900001010101010101010101010100010100D3 +:107FA00001000000000000000000000000000000D0 +:107FB00000000000000000000000000000000001C0 +:107FC00001010101010101010101010101010001A2 +:107FD0000101010001000000000001000101010198 +:107FE000010000010100000000000000000000008E +:107FF000000000010101000000000000000001017C +:108000000101010101010101010101010001010062 +:10801000000000000000000000000000000000015F +:108020000101010001000100000000000001010148 +:108030000101010101010101010100000001010133 +:108040000101010101010101010101010001010121 +:108050000101010101010101000000000000010116 +:108060000101010101010101010101010001010002 +:1080700001010101010000000000000000000001FA +:1080800001010101010100010100000000010100E6 +:1080900001010101010101010101010100010100D2 +:1080A00001000000010000000000000000000000CE +:1080B00000000000000000000000000000000001BF +:1080C00001010101010101010101010101010001A1 +:1080D0000101010101000000000101010101010194 +:1080E000010000010100000000000000000000008D +:1080F000000000010101000000000000000001017B +:108100000101010101010101010101010001010061 +:10811000000000000000000000000000000000015E +:108120000101010101010101010000000001010143 +:108130000101010101010101010101000001010131 +:10814000010101010101010101010101010101011F +:108150000101010101010101010000000000010114 +:108160000101010101010101010101010001010001 +:1081700001010101010000000000000000010101F7 +:1081800001010101010101010100000000010100E4 +:1081900001010101010101010101010100010100D1 +:1081A00001010000010000000000000000000000CC +:1081B00000000000000000000000000000000002BD +:1081C000010101020101010101010101020100029D +:1081D0000101010101000000000101010101010193 +:1081E000010000010100000000000000000000008C +:1081F000000000010101000000000000000001017A +:108200000101010101010101010101010001010060 +:10821000000000000000000000000000000000015D +:108220000101010101010101010000000001010142 +:10823000010101010101010101010101000101012F +:10824000010101010101010101010101010101011E +:108250000101010101010101010000000001010112 +:108260000101010101010101010101010001010000 +:1082700001010101010100010100000100010101F2 +:1082800001010101010101010101000100010100E1 +:1082900001010101010101010101010100010100D0 +:1082A00001010001010000000000000000000000CA +:1082B00001000000000000000000000000000002BB +:1082C0000202010202010102010102020201000296 +:1082D0000101010101000000000101010101010192 +:1082E0000101000101000000000000000000010089 +:1082F0000000000101010100000000000000010178 +:10830000010101010101010101010101020101005D +:10831000000000000000000000000000000000015C +:108320000101010101010101010000010001010140 +:10833000010101010101010101010101000101012E +:10834000010101010101010101010101010101011D +:10835000010101010101010101010001000101010F +:1083600001010101010101010101010100010101FE +:1083700001010101010101010100000100010101F0 +:1083800001010101010101010101010100010101DE +:1083900001010101010101010101010100010101CE +:1083A00001010101010000000000000000000000C8 +:1083B00001000000000000000000000000000002BA +:1083C0000202010202010102020102020201000294 +:1083D0000201010101000000000101010101010190 +:1083E0000101000101010000000000000000010087 +:1083F0000000000101010101000000000000010176 +:10840000010101010101010101010101020101005C +:108410000101010000000000000000000000010157 +:10842000010101010101010101000101000101013E +:10843000010101010101010101010101000101012D +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101000101010D +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101000100010101EE +:1084800001010101010101010101010100010101DD +:1084900001010101010101010101010101010101CC +:1084A00001010101010100010000000000000000C5 +:1084B00001000000000000000000000000000002B9 +:1084C0000202020202010102020202020202000290 +:1084D000020201010100000001010101010101018D +:1084E0000101010101010000000000000000010184 +:1084F0000100000101010101000000000000010174 +:10850000010101010101010101010101010101005C +:108510000101010000000000000000000000010156 +:10852000010101010101010101010101000101013C +:10853000010101010101010101010101000101012C +:10854000010101010101010101010101010101021A +:10855000010101010101010101010101000101010C +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010100010101EC +:1085800001010101010101010101010100010101DC +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010000000000010000C2 +:1085B00001010000000000000000000000000002B7 +:1085C000020202020202010202020202020200028E +:1085D000020201010100010001010101010101028A +:1085E0000101010101010000000000000000010183 +:1085F000010000010101010100020002020001016D +:10860000010101020101010101010101010101005A +:108610000101010000000000000000000001010154 +:10862000010101010101010101010101000101013B +:10863000010101010101010101010101000101022A +:108640000101010101010101010101010101010219 +:10865000010101010101010101010101000101010B +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010100010101EB +:1086800001010101010101010101010100010101DB +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010100000000010000C0 +:1086B00001010000000100000000000000010002B4 +:1086C000020202020202020202020202020200028C +:1086D0000202020101010101010101010101010286 +:1086E0000101010101010000000000000002010180 +:1086F0000100000101010101000202020201010268 +:108700000101010202010101010101010101010058 +:108710000101010000000000000000000001010153 +:108720000101010101010101010101010001010239 +:108730000101010101010101010101010001010229 +:108740000101010101010101010101010101010218 +:108750000101010101010101010101010001010209 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010100010101EA +:1087800001010101010101010101010100010101DA +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010100010000010100BD +:1087B00001010001010100000000000000010002B1 +:1087C000020202020202020202020202020200028B +:1087D0000202020101010101010101010101010285 +:1087E0000101010201010000000200020201010179 +:1087F0000100000101010101010102010201010268 +:108800000101010202020101010101010101010056 +:108810000101010000000000000000000001010152 +:108820000101010101010101010101010001010238 +:108830000101010101010101010101010101010227 +:108840000202010101010101010101010101010215 +:108850000202010101010101010101010001010206 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010100010101E9 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010000010100BB +:1088B00000010101010100000000000000010002B0 +:1088C000020202020202020202020202020200028A +:1088D0000202020101010101010101010101010284 +:1088E0000201010201010100000202020201010174 +:1088F0000101000201010101010101010101010267 +:108900000201010202020201010101010101020052 +:10891000010101010100000000000000000101024E +:108920000101010101010101010101010101010236 +:108930000201010101010101010101010101010225 +:108940000202020101010101010101010101010213 +:108950000202020101010101010101010101010203 +:1089600002020101010101010101010101010101F5 +:1089700001010101010101010101010100010102E7 +:1089800001010101010101010101010101010101D7 +:1089900001010101010101010101010101010101C7 +:1089A00001010101010101010101010000010100BA +:1089B00000010101010100010000000001010002AD +:1089C0000202020202020202020202020202000289 +:1089D0000202020202010101010101010101010281 +:1089E0000201010202010101020102010201010270 +:1089F0000101000202010101010101010101010265 +:108A0000020201020202020201010101010202004E +:108A1000010101010100000000000000000101024D +:108A20000101010101010101010101010101010235 +:108A30000202010101010101010101010101010223 +:108A40000202020201010101010101010101010211 +:108A50000202020201010101010101010101010201 +:108A600002020201010101010101010101010101F3 +:108A700001010101010101010101010101010102E5 +:108A800002010101010101010101010101010101D5 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010100010100B8 +:108AB00000000101010101010000000001010002AC +:108AC0000202020202020202020202020202000288 +:108AD000020202020201010101020201020101027D +:108AE0000202010202010101010101010201010270 +:108AF0000101010202020101010101010101010262 +:108B0000020201020202020202010101010202004C +:108B1000010101010100000000000000000101024C +:108B20000202010101010101010101010101010232 +:108B30000202020101010101010101010101010221 +:108B4000020202020201010101010101010101020F +:108B500002020202020101010101010101010102FF +:108B600002020202010101010101010101010101F1 +:108B700001010101010101010101010101010102E4 +:108B800002020101010101010101010101010101D3 +:108B900001010101010101010101010101010102C4 +:108BA00001010101010101010101010100010100B7 +:108BB00000000101010101010100000101010002A9 +:108BC0000202020202020202020202020202000287 +:108BD0000202020202010101010202020202020279 +:108BE0000202010202010101010101010101010270 +:108BF0000101010202020101010101010101010261 +:108C00000202020202020202020201010102020148 +:108C1000010101010100000000000000000101024B +:108C20000202020101010101010101010101010230 +:108C3000020202020101010101010101010101021F +:108C4000020202020202010102010101010101020C +:108C500002020202020101010101010101010102FE +:108C600002020202020101010101010101010102EE +:108C700001010101010101010101010101010102E3 +:108C800002020201010101010101010101010101D1 +:108C900001010101010101010101010101010102C3 +:108CA00002010101010101010101010100010100B5 +:108CB00000000101010001010100010101010002A8 +:108CC0000202020202020202020202020202000286 +:108CD0000202020202010101010202020202020278 +:108CE000020202020202010101010101010101026D +:108CF000020101020202010101010101010102025E +:108D00000202020202020202020201010102020147 +:108D10000202010101010000000000000001010247 +:108D2000020202010201010101010101010101022E +:108D3000020202020201010102010101010101021C +:108D40000202020202020201020101010101020209 +:108D500002020202020201010101010101010102FC +:108D600002020202020201010101010101010102EC +:108D700002020101010101010101010101010102E0 +:108D800002020202010101010101010101010102CE +:108D900002010101010101010101010101010102C1 +:108DA00002020101010101010101010100010100B3 +:108DB00000000000010001010101010101010002A8 +:108DC0000202020202020202020202020202000285 +:108DD0000202020202020201020202020202020274 +:108DE000020202020202010101010101010101026C +:108DF000020101020202020101010101010102025C +:108E00000202020202020202020202020102020144 +:108E10000202020101010100000000000001010244 +:108E2000020202020201010101010101010101022C +:108E30000202020202020201020101010101020218 +:108E40000202020202020202020202010102020204 +:108E500002020202020202020101010101010102F9 +:108E600002020202020202020201010101010102E8 +:108E700002020201010101010101010101010102DE +:108E800002020202020101010101010101010102CC +:108E900002020201020101010101010101010102BD +:108EA00002020101010101010101010100010100B2 +:108EB00000000000000001010101010101010002A8 +:108EC0000202020202020202020202020202000284 +:108ED0000202020202020202020202020202020272 +:108EE000020202020202010101010101010101026B +:108EF0000202010202020202010101010101020259 +:108F00000202020202020202020202020102020242 +:108F10000202020101010101000000000001010242 +:108F20000202020202020201010101010101020228 +:108F30000202020202020202020201010102020214 +:108F40000202020202020202020202020102020202 +:108F500002020202020202020201010101010102F7 +:108F600002020202020202020202010101010202E5 +:108F700002020202020101010101010101010102DB +:108F800002020202020201010101010101010102CA +:108F900002020202020101010101010101010102BB +:108FA00002020202020101010101010100010100AE +:108FB00000000000000001010101010101010002A7 +:108FC0000202020202020202020202020202000283 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020201010101010101020268 +:108FF0000202010202020202010101010101020258 +:109000000202020202020202020202020102020241 +:109010000202020101010101000000000001010241 +:109020000202020202020202020101010101020225 +:109030000202020202020202020202010102020212 +:109040000202020202020202020202020102020201 +:1090500002020202020202020202010101010202F4 +:1090600002020202020202020202020201010202E2 +:1090700002020202020101010101010101010102DA +:1090800002020202020202020201010101010102C6 +:1090900002020202020202020201010101010102B6 +:1090A00002020202020101010101010101010100AC +:1090B00000000000000000000101010100010002A9 +:1090C0000202020202020202020202020202000282 +:1090D0000202020202020202020202020202020270 +:1090E0000202020202020202010101010101020266 +:1090F0000202020202020202020101010101020255 +:109100000202020202020202020202020102020240 +:10911000020202020101010101000000000101023E +:109120000202020202020202020101010102020223 +:109130000202020202020202020202020102020210 +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020201010202F1 +:1091600002020202020202020202020201020202E0 +:1091700002020202020201010101010101010102D8 +:1091800002020202020202020202010101010102C4 +:1091900002020202020202020202020101010102B3 +:1091A00002020202020201010101010101010100AA +:1091B00000000000000000000001010100000002AA +:1091C0000202020202020202020202020202000281 +:1091D000020202020202020202020202020202026F +:1091E0000202020202020202020201010101020263 +:1091F0000202020202020202020201010101020253 +:10920000020202020202020202020202020202023E +:10921000020202020201010101000000000101023C +:10922000020202020202020202020202010202021F +:10923000020202020202020202020202010202020F +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020201020202EF +:1092600002020202020202020202020201020202DF +:1092700002020202020202020201010101010102D4 +:1092800002020202020202020202020201020202BF +:1092900002020202020202020202020201020202AF +:1092A00002020202020202020101010101010100A7 +:1092B00000000000000000000000000000000002AC +:1092C0000202020202020202020202020202000280 +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202010202025F +:1092F000020202020202020202020202010202024F +:10930000020202020202020202020202020202023D +:109310000202020202010101010000020201020236 +:10932000020202020202020202020202010202021E +:10933000020202020202020202020202010202020E +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020201020202EE +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202010201010102D1 +:1093800002020202020202020202020201020202BE +:1093900002020202020202020202020201020202AE +:1093A00002020202020202020201010101010100A5 +:1093B00000000000000000000000000000000002AB +:1093C000020202020202020202020202020200027F +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202010202025E +:1093F000020202020202020202020202020202024D +:10940000020202020202020202020202020202023C +:109410000202020202020101010002010202020232 +:10942000020202020202020202020202010202021D +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020201020202CD +:1094800002020202020202020202020201020202BD +:1094900002020202020202020202020201020202AD +:1094A00002020202020202020202020101010100A2 +:1094B00000000000000000000000000000000002AA +:1094C000020202020202020202020202020200027E +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202020202020202020202024C +:10950000020202020202020202020202020202023B +:109510000202020202020201010201010102020230 +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020201020202CC +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020202AB +:1095A000020202020202020202020201010201029E +:1095B00002000000000000000000000000000102A6 +:1095C000020202020202020202020202010200027E +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020201010101010202022F +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020201020202CB +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202010202029B +:1096B00002020000000000000000000000000102A3 +:1096C0000202020202020202020201010101000280 +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:10971000020202020202020202010101010202022D +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A000020202020202020202020202010202029A +:1097B00002020000000000000000000000000102A2 +:1097C0000202020202020201010101010101010281 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:10981000020202020202020202010101010202022C +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020102020299 +:1098B000020202020000000000000000000001029D +:1098C0000202020101010101010101010101010284 +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:10991000020202020202020202010101010202022B +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B000020202020200000000000000000001019B +:1099C0000101010101010101010101010101010286 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020102020227 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020202A6 +:109AA0000202020202020202020202020202020296 +:109AB0000202020202020000000000000000010198 +:109AC0000101010101010101010101010101010285 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020202A5 +:109BA0000202020202020202020202020202020295 +:109BB0000202020202020202000000000000010193 +:109BC0000101010101010101010101010101010284 +:109BD0000202020202020202020101010102020269 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020202A4 +:109CA0000202020202020202020202020202020294 +:109CB000020202020202020202000000000201018E +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010273 +:109CE0000202020101010101010101010101010260 +:109CF0000202020202020202020202020202020244 +:109D00000202020202020202020202020202020233 +:109D10000202020202020202020202020202020223 +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020202020202020202020202020202E3 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020202A3 +:109DA0000202020202020202020202020202020293 +:109DB0000202020202020202020202020202010185 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010262 +:109DF0000202020202020202020202020202020243 +:109E00000202020202020202020202020202020232 +:109E10000202020202020202020202020202020222 +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202020202020202E2 +:109E600002020202020202020202020202020202D2 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020202A2 +:109EA0000202020202020202020202020202020292 +:109EB0000202020202020202020202020202020183 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010261 +:109EF000020202010101010101010101010101024E +:109F0000020202010101010101010101010101023D +:109F10000202020202020202020202020202020221 +:109F20000202020202020202020202020202020211 +:109F30000202020202020202020202020202020201 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202020202020202E1 +:109F600002020202020202020202020202020202D1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020202A1 +:109FA0000202020202020202020202020202020291 +:109FB0000202020202020202020202020202020182 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010250 +:10A000000202020202020202020202020202020230 +:10A010000202020202020202020202020202020220 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020202020202020202020202020202D0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020202A0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020181 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101023E +:10A11000010101010101010101010101010101022E +:10A12000020202020202020202020202020202020F +:10A1300002020202020202020202020202020202FF +:10A1400002020202020202020202020202020201F0 +:10A1500001010101010101010101010101010102EE +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A19000020202020202020202020202020202029F +:10A1A000020202020202020202020202020202028F +:10A1B0000202020202020202020202020202020180 +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101023D +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202010F +:10A23000010101010101010101010101010101020D +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202017F +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101021C +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020200EF +:10A3500000000000000000000000000000000002FB +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202017E +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010102DB +:10A4700002020202020202020202020202020201BD +:10A4800001010101010101010101010101010102BB +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202017D +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010102DA +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202017C +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010100CB +:10A6800000000000000000000000000000000002C8 +:10A69000020202020202020202020202020202009C +:10A6A00000000000000000000000000000000002A8 +:10A6B000020202020202020202020202020202017B +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010102B8 +:10A79000020202020202020202020202020202009B +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000198 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010099 +:10A8B0000000000000000000000000000000000197 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010098 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000000000275 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020200A8 +:10AA900000000000000000000000000000000002B4 +:10AAA0000202020202020202020202020202020088 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000203 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020200C7 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000003361 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000100000000000000000042 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000100000000000000000041 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF0000000000000001010000000000000000003F +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000100000000000000000050 +:10B00000000000000001010000000000000000003E +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D000000000000001000000000000000000006F +:10B0E0000000000000000000000000000000000060 +:10B0F000000000000000010001000000000000004E +:10B10000000000000001010000000000000000003D +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000010000000000000000000E +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000001007E +:10B1D000000101000001000001000000000000006B +:10B1E000000000000000000000000000000000005F +:10B1F000000000000001010001000100000000004B +:10B20000000000000001010000000000000000003C +:10B21000000000000000010000000000000000002D +:10B22000000000000000000000000000000000001E +:10B23000000000000000010000000000000000000D +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000101017B +:10B2D0000101010101010000010000000000000067 +:10B2E000000000000000000000000000000000005E +:10B2F0000000000000010100010101000000000049 +:10B30000000000000001010000000000000000003B +:10B31000000000000000010000000000000000002C +:10B32000000000000000000001010000000000001B +:10B33000000000000001010000000100000000000A +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000001010001000000009A +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000101017A +:10B3D0000101010101010000010100000000000065 +:10B3E000000000000000010001010000000000005A +:10B3F0000000000000010101010101010000000046 +:10B40000000000000001010000000000000000003A +:10B41000000000000001010000000000000000002A +:10B420000000000000000000010101000000000019 +:10B430000000000000010100010101000000000007 +:10B4400000000000000101000000000000000000FA +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000101000000000000000000CA +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A0000000000000000001010101010000000097 +:10B4B000000000000000000000000000000000008C +:10B4C0000000000000000000000000000001010179 +:10B4D0000101010101010001010101000000000062 +:10B4E0000000000000000101010101010000000056 +:10B4F0000000000000010101010101010000000045 +:10B500000000000001010100000000000000000038 +:10B510000000000000010100000000000000000029 +:10B520000000000000000000010101000000000018 +:10B530000000000000010101010101010000000004 +:10B5400000000000000101000000000000000000F9 +:10B5500000000000000101000000000000000000E9 +:10B5600000000000000101000000000000000000D9 +:10B5700000000000000101000000000000000000C9 +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A0000000000000000001010101010100000095 +:10B5B000000000000000000000000000000000008B +:10B5C0000000000000000000000001010001010176 +:10B5D0000101010101010001010101000000000061 +:10B5E0000000000000000101010101010000000055 +:10B5F0000000000000010101010101010000000044 +:10B600000000000001010100000000000000000037 +:10B610000000000000010100010100000000000026 +:10B620000000000000010101010101010000010012 +:10B630000000000000010101010101010000000003 +:10B6400000000000000101000000000000000000F8 +:10B6500000000000000101000000010000000000E7 +:10B6600000000000000101000101000000000000D6 +:10B6700000000000000101000000000000000000C8 +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A0000000000000000001010101010101000093 +:10B6B000000000000000000000000000000000008A +:10B6C0000000000000000000000001010001010175 +:10B6D000010101010101000101010101000000005F +:10B6E0000000000000000101010101010000000054 +:10B6F0000000000000010101010101010000000142 +:10B700000000000101010100000000000000000035 +:10B710000000000000010100010101000000000024 +:10B720000000000000010101010101010000010110 +:10B730000100000100010101010101010000000000 +:10B7400000000000000101000000000000000000F7 +:10B7500000000000000101000101010000000000E4 +:10B7600000000000000101000101010000000000D4 +:10B7700000000000000101000000000000000000C7 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000100000000000000000000A8 +:10B7A0000000000000000001010101010101010091 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000001010101010173 +:10B7D000010101010101000101010101000000005E +:10B7E0000000000001000101010101010000000052 +:10B7F000000000000001010101010101010001013F +:10B800000001000101010100000000000000000033 +:10B810000000000000010100010101000000000023 +:10B82000000000000001010101010101010001010E +:10B8300001000101000101010101010100000000FE +:10B8400000000000000101000000010000000000F5 +:10B8500000000000000101000101010100000000E2 +:10B8600000000000000101000101010000000001D2 +:10B8700000000001000101000000000000000000C5 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000100000000000000000000A7 +:10B8A000000000000000000101010101010101018F +:10B8B0000100000000000000000000000000000087 +:10B8C0000000000000000000010101010101010170 +:10B8D000010101010101000101010101000000005D +:10B8E0000000000001000101010101010000000051 +:10B8F000000000000001010101010101010101013D +:10B900000001000101010100000000000100000031 +:10B910000000000000010101010101000000000021 +:10B92000000000000001010101010101010101010C +:10B9300001000101010101010101010101000100FA +:10B9400000000000000101000101010000000000F2 +:10B9500000000000000101000101010100000000E1 +:10B9600000000000000101010101010100000101CE +:10B9700000010101000101000000000000000000C2 +:10B9800000000000000000000101000000000000B5 +:10B9900000000000000101000101000000000000A3 +:10B9A000000000000000000101010101010101018E +:10B9B0000100000000000000000000000000000086 +:10B9C000000000000000000101010101010101016E +:10B9D000010101010101000101010101000000005C +:10B9E000010000000101010101010101000000004E +:10B9F000000000000001010101010101010101013C +:10BA00000001000101010100000000000100000030 +:10BA10000000000000010101010101000000000020 +:10BA2000000000000001010101010101010101010B +:10BA300001010101010101010101010101010101F6 +:10BA400000000000000101010101010100000000EF +:10BA500000000000000101010101010101000000DE +:10BA600000000000000101010101010100010101CC +:10BA700001010101010101000100000000000000BE +:10BA800000000000000100000101010000000000B2 +:10BA9000000101000001010001010100000000009F +:10BAA000000000000000000101010101010101018D +:10BAB0000100000000000100000000000000000084 +:10BAC000000000000000000101010101010101016D +:10BAD000010101010101000201010101000000005A +:10BAE000010101000101010101010101000000004B +:10BAF000000000000001010101010101010101013B +:10BB0000000100010101010000000000010000002F +:10BB1000000000000001010101010101000000001E +:10BB2000000000000001010101010101010101010A +:10BB300001010101010101010101010101010101F5 +:10BB400000010000000101010101010100000001EC +:10BB500000000001010101010101010101010001D9 +:10BB600000000001010101010101010101010101C8 +:10BB700001010101010101000100010000000000BC +:10BB800000000000000100000101010000000001B0 +:10BB9000010101010001010001010100000000009C +:10BBA000000000000001000101010101010101018B +:10BBB0000101010000000100000000000000000081 +:10BBC000000000000000000101010101010101016C +:10BBD0000101010101010002020101010000000157 +:10BBE0000101010101010102010101010000000048 +:10BBF0000000000000010102010101010101010139 +:10BC0000000101010101010000000000010100002C +:10BC1000000000000001010101010101000000001D +:10BC20000000000000010101010101010101010109 +:10BC300001010101010101020101010101010101F3 +:10BC400001010001010101010101010101000101E6 +:10BC500000010101010101010101010101010101D5 +:10BC600000010101010101010101010101010101C5 +:10BC700001010101010101000101010000000000BA +:10BC800000000000000101000101010100000101AC +:10BC90000101010100010101010101010000000099 +:10BCA000000000000001000101010101010101018A +:10BCB000010101010001010000000000000000007E +:10BCC000000000000000000101010101010101016B +:10BCD0000101010101010002020101010000000156 +:10BCE0000101010101010102010101010000010046 +:10BCF0000000000000010102020101010101010137 +:10BD0000010101010101010000000000010100002A +:10BD1000000000000001010101010101000000001C +:10BD20000000000000010102010101010101010107 +:10BD300001010101010101020101010101010101F2 +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101010101010100000000B7 +:10BD800000010000000101000101010100010101A9 +:10BD90000101010101010101010101010000000097 +:10BDA0000000000000010002010101010101010188 +:10BDB000010101010001010000000000000000007D +:10BDC0000000000000000001010101010102020168 +:10BDD0000101010101010002020201010000000154 +:10BDE0000101010101010102020101010000010143 +:10BDF0000000000000010102020101010101010136 +:10BE00000101010101010100000000000101000029 +:10BE1000000000000001010101010101000000001B +:10BE20000000000100010102020101010101010104 +:10BE300001010101010101020201010101010101F0 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101010101010100000001B5 +:10BE800001010000000101010101010101010101A5 +:10BE90000101010101010101010101010000000096 +:10BEA0000000000000010002010101010101010187 +:10BEB0000101010101010100000100000001000079 +:10BEC0000000000000000002010101010102020265 +:10BED000020202010101000202020201000000014F +:10BEE0000101010101010102020201010100010140 +:10BEF0000000000000010102020202010101010133 +:10BF00000101010101010100000000000101010027 +:10BF10000000000000010101010101010100000019 +:10BF20000000000100010102020201010101010102 +:10BF300001010101010101020202020101010101ED +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101010101010101000101B2 +:10BF800001010100000101010101010101010101A3 +:10BF90000101010101010101010101010001000193 +:10BFA0000000000000010102020101010101010184 +:10BFB0000101010101010100010101010001000174 +:10BFC0000000000100000002010102020102020261 +:10BFD000020202020202000202020202000000014A +:10BFE000010101010101010202020202010101013C +:10BFF0000000000000010102020202020101010131 +:10C000000101010101010201000000000101010024 +:10C010000000000202010102010101010101000111 +:10C020000000000100010102020202010101010100 +:10C0300001010101010101020202020201010101EB +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101010101010101010101B0 +:10C0800001010101010101010101010101010101A0 +:10C090000101010101010101010101010101010190 +:10C0A000000101000001010202020102010101017F +:10C0B0000101010101010100010101010001010172 +:10C0C000000100010100000202010202020202025C +:10C0D0000202020202020002020202020000010148 +:10C0E000010101010101010202020202010101013B +:10C0F000000000000001020202020202010101012F +:10C100000101010101020201010000000101010021 +:10C11000000200010101010202010101010101010E +:10C1200000010101000101020202020201010101FC +:10C1300001010101010101020202020201010101EA +:10C1400001010101010101020101010101010101DE +:10C1500001010101010101020101010101010101CE +:10C1600001010101010101020101010101010101BE +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A000010101010001010202020202020101017A +:10C1B0000101010101010100010101010101010170 +:10C1C0000101000101000002020202020202020259 +:10C1D0000202020202020002020202020001010146 +:10C1E0000201010102010202020202020101010137 +:10C1F000000000000002020202020202020101012C +:10C20000010101010102020201000000020101011D +:10C21000020100010101020202020101010101010A +:10C2200000010101000101020202020202010201F9 +:10C2300001010101010102020202020202010101E7 +:10C2400001010101010101020101010101010101DD +:10C2500001010101010101020201010101010101CC +:10C2600001010101010101020201010101010101BC +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010201010101010101018D +:10C2A0000101010100010102020202020202010178 +:10C2B0000101010101010100010001010100010171 +:10C2C0000101010101000002020202020202020257 +:10C2D0000202020202020002020202020101010243 +:10C2E0000202020102010202020202020101010134 +:10C2F0000000000000020202020202020202020228 +:10C30000010101010202020201010000020101011A +:10C310000101020101020202020202010101010106 +:10C3200000010101000101020202020202020202F6 +:10C3300002010101010202020202020202020201E2 +:10C3400001010101010202020201010101010101D9 +:10C3500001010101010101020202020101010101C9 +:10C3600001010101010101020202010101010101BA +:10C3700001010101010101020101010101010101AC +:10C38000010101010101010101010101010101019D +:10C39000010101010101010202010101010101018B +:10C3A0000101010101010102020202020202020175 +:10C3B0000101010101010100000000000100010173 +:10C3C0000101010101000002020202020202020256 +:10C3D0000202020202020002020202020101010242 +:10C3E0000202020202010202020202020101010132 +:10C3F0000100000101020202020202020202020224 +:10C400000102010202020202010101000202010115 +:10C410000101010101020202020202010101010106 +:10C4200001010101010101020202020202020202F3 +:10C4300002010202010202020202020202020202DE +:10C4400001010101010202020202020101010101D6 +:10C4500001010101010101020202020201010101C7 +:10C4600001010101010101020202020101010101B8 +:10C4700001010101010101020201010101010101AA +:10C48000010101010101010202010101010101019A +:10C490000101010101010102020201010101010189 +:10C4A0000101010101010102020202020202020273 +:10C4B0000201010101010100000000000000010172 +:10C4C0000101010101000002020202020202020255 +:10C4D0000202020202020002020202020101010241 +:10C4E000020202020202020202020202020102012E +:10C4F0000101010101020202020202020202020221 +:10C500000102010202020202020101000202010113 +:10C510000101010101020202020202020101010104 +:10C5200001010101010101020202020202020202F2 +:10C5300002020202020202020202020202020202DB +:10C5400002020101010202020202020201010101D2 +:10C5500001010101010101020202020202010101C5 +:10C5600001010101010101020202020201010101B6 +:10C5700001010101010101020201010101010101A9 +:10C580000101010101010102020201010101010198 +:10C590000101010101010102020202010101010187 +:10C5A0000101010101010102020202020202020272 +:10C5B0000201010101010100000000000000000073 +:10C5C0000101010101000002020202020202020254 +:10C5D000020202020202000202020202020202023D +:10C5E000020202020202020202020202020202022B +:10C5F0000101010101020202020202020202020220 +:10C60000020202020202020202010101020202010E +:10C610000101010101020202020202020101010103 +:10C6200001010101010202020202020202020202EF +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202010101CD +:10C6500001010101010202020202020202020101C1 +:10C6600001010101010202020202020202020202AF +:10C6700001010101010202020202020101010101A4 +:10C680000101010101010102020202010101010196 +:10C690000101010101010102020202020101010185 +:10C6A0000101010101010102020202020202020271 +:10C6B0000202020101010100000000000000000070 +:10C6C0000000010001000002020202020202020256 +:10C6D000020202020202000202020202020202023C +:10C6E000020202020202020202020202020202022A +:10C6F000010101010102020202020202020202021F +:10C70000020202020202020202020101020202010C +:10C710000101010101020202020202020201010101 +:10C7200001010101010202020202020202020202EE +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500001010101010202020202020202020202BE +:10C7600001010101010202020202020202020202AE +:10C77000020202020102020202020202010101019E +:10C780000101010101010102020202020101010194 +:10C790000101010101010102020202020101010184 +:10C7A0000101010101010102020202020202020270 +:10C7B000020202020101020000000000000000006D +:10C7C0000000000000010002020202020202020256 +:10C7D000020202020202000202020202020202023B +:10C7E0000202020202020202020202020202020229 +:10C7F000010101010102020202020202020202021E +:10C800000202020202020202020202010202020209 +:10C8100001010101010202020202020202020101FF +:10C8200001010101010202020202020202020202ED +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C87000020202020202020202020202020101019B +:10C88000010101010101010202020202020202028F +:10C89000020202010102010202020202020201017D +:10C8A000010101010101010202020202020202026F +:10C8B000020202020202020000000000000000006A +:10C8C0000000000000010002020202020202020255 +:10C8D000020202020202000202020202020202023A +:10C8E0000202020202020202020202020202020228 +:10C8F000020101010102020202020202020202021C +:10C900000202020202020202020202020202020207 +:10C9100002020102020202020202020202020202F8 +:10C9200001010102010202020202020202020202EB +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C98000020201010102010202020202020202028B +:10C990000202020201020202020202020202020278 +:10C9A000010101010102010202020202020202026D +:10C9B0000202020202020200000000000000000069 +:10C9C0000000000000010002020202020202020254 +:10C9D0000202020202020002020202020202020239 +:10C9E0000202020202020202020202020202020227 +:10C9F0000202020202020202020202020202020217 +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200001020202010202020202020202020202E8 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020101020202020202020202020288 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020101020102020202020202020269 +:10CAB0000202020202020202000000000000000066 +:10CAC0000000000000010002020202020202020253 +:10CAD0000202020202020002020202020202020238 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202010202020202020202020202E6 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020201020202020202020202020266 +:10CBB0000202020202020202020000000000000063 +:10CBC0000000000000010102020202020202020251 +:10CBD0000202020202020002020202020202020237 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020000000000000062 +:10CCC0000000000000010102020202020202020250 +:10CCD0000202020202020102020202020202020235 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB000020202020202020202020000000000005F +:10CDC0000000000000010102020202020201010152 +:10CDD000010101010101010202020202020202023A +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202020202020202020202020213 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB000020202020202020202020202000000005A +:10CEC0000000000000000102020201010101010155 +:10CED0000101010101010102020202020202020239 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202020202020202020202020212 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000000000000000101010101010101010157 +:10CFD0000101010101010102020202020202020139 +:10CFE0000101010101020202020202020202020226 +:10CFF0000202020202020202020202020202020211 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C000020200020200010101010101010101014E +:10D0D0000101010101010101010101010101010140 +:10D0E0000101010101010102020202020202020227 +:10D0F0000202020202020202020202020202020210 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202010101010101010101D8 +:10D1400001010101010101020202020202020202C6 +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D17000020202020202020202020202020202028F +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020200010101010101010101014B +:10D1D000010101010101010101010101010101013F +:10D1E0000101010101010102020202020202020226 +:10D1F000020202020202020202020202020202020F +:10D200000202020202020201010101010101010107 +:10D2100001010101010101020202020202020202F5 +:10D2200002020202020202000000000000000000F0 +:10D2300000000000000000020202020202020202DC +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C0000202020202020201010101010101010147 +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D300000101010101010102020202020202020204 +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202000000000000000000EF +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000020202020202020202CB +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020202020202020202020202025D +:10D3B000020202020202020202020202020202024D +:10D3C0000202020202020201010101010101010146 +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F0000101010101010102020202020202020214 +:10D40000020202020202020000000000010101010A +:10D4100001010101010101020202020202020202F3 +:10D4200002020202020202000000000000000000EE +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000020202020202020202CA +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202020202020202025C +:10D4B000020202020202020202020202020202024C +:10D4C0000202020202020201010101010101010145 +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101000000000000000000F4 +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000020202020202020202C9 +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A0000202020202020202020202000000000065 +:10D5B0000000000000000002020202020202020259 +:10D5C0000202020202020201010101010101010144 +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101000000000000000000E3 +:10D6400000000000000000020202020202020202C8 +:10D6500002020202020202010101010101010101B3 +:10D6600001010101010101020202020202020202A1 +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D690000202020202020201010101010101010173 +:10D6A0000101010101010100000000000000000073 +:10D6B0000000000000000002020202020202020258 +:10D6C0000202020202020201010101010101010143 +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101020202020202020202B0 +:10D760000202020202020202020202020202020299 +:10D770000202020202020201010101010101010192 +:10D780000101010101010102020202020202020280 +:10D790000202020202020202020202020202020269 +:10D7A000020202020202020000000000000000006B +:10D7B0000000000000000002020202020202020257 +:10D7C0000202020202020201010101010101010142 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D87000010101010101010202020202020202028F +:10D880000202020202020202020202020202020278 +:10D89000020202020202020000000000000000007A +:10D8A000000000000000000101010101010101016F +:10D8B000010101010101010202020202020202024F +:10D8C0000202020202020201010101010101010141 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010100000000000000000080 +:10D9A000000000000000000101010101010101016E +:10D9B0000101010101010100000000000000000060 +:10D9C000000000000000000101010101010101014E +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB000010101010101010000000000000000005F +:10DAC000000000000000000101010101010101014D +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB000010101010101010000000000000000005E +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000002020202020202020202 +:10DC100002020202020202020202020202020202E4 +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB0000202020202020200000000000000000056 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000002020202020202020261 +:10DDB0000202020202020200000000000000000055 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000002020202020202020260 +:10DEB0000202020202020200000000000000000054 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000000031000000000000000020 +:10DFD0000000000100000000000000000000000040 +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E09000000000010100000000000000000001007D +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D000000000010001000000000000010100003C +:10E0E000000000000000000000000000010000002F +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000001000E +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E190000000010101010000000000000101010078 +:10E1A000000000000000000000000000000000006F +:10E1B000000101000000000000000000000000005D +:10E1C000000000000000000000000000000000004F +:10E1D000000000010101000000000000010100003A +:10E1E000000000000000000000000000010000002E +:10E1F000000000000000000000000000000001001E +:10E20000000000000000000000000000000001000D +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E290000000010101010001000000010101010075 +:10E2A000000000000000000000000000000000006E +:10E2B000010101010000000000000000000000005A +:10E2C000000000000000000000000000000000004E +:10E2D0000000000101010100000000000101000038 +:10E2E000000000000000000000000000010100002C +:10E2F000000000000000000000000000000001001D +:10E30000000000010000000000000000000001000B +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000001010000EB +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000001000000000000000100000100BA +:10E3600000000000000000000000000000010000AC +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E390000000010101010101000100010101010072 +:10E3A000000000000000000000000000000000006D +:10E3B0000101010100000000000000000000000059 +:10E3C000000000000000000000000000000000004D +:10E3D0000000000101010101000000010101000035 +:10E3E000000000000000000000000000010101002A +:10E3F000000000010000000000000000000001001B +:10E400000000000100010000000000000001010008 +:10E4100000000000000000000000000000000000FC +:10E4200000000001000000000000000001010100E8 +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000001000000000000000101010100B7 +:10E4600000000000000000000000000100010100A9 +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E490000000010101010101010100010101010070 +:10E4A000000000000000000000000000000000006C +:10E4B0000101010101000000000000000000000057 +:10E4C000000000000000000000000000000000004C +:10E4D000010101010101010100010101010100002F +:10E4E0000000000000000000000000000101010029 +:10E4F0000000000100010000000000000101010017 +:10E500000000000100010000000000010001010006 +:10E5100000000001000000000000000000000000FA +:10E5200000000001000000000000000001010100E7 +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000100CA +:10E5500000000001000000000000000101010100B6 +:10E5600000000000000000000000000100010100A8 +:10E57000000000000000000000000000000100009A +:10E58000000000000000000000000000000001008A +:10E59000000101010101010101010101010101006D +:10E5A000000000000000000000000000000000006B +:10E5B0000101010101000000000000000000000056 +:10E5C000000000000000000000000000000000004B +:10E5D000010101010101010101010101010100002D +:10E5E0000000000100000000000000000101010027 +:10E5F0000000000100010000000000010101010015 +:10E600000000000100010000000000010101010004 +:10E6100000000001000000000000000000000000F9 +:10E6200000000001000000000000000001010100E6 +:10E6300000000001000000000000000000000000D9 +:10E6400000000000000000000000000001010100C7 +:10E6500000010101000100000001000101010100B1 +:10E6600000000001000000000000000100010100A6 +:10E670000000000100000000000000000001010097 +:10E680000000000000000000000000000101010087 +:10E69000000101010101010101010101010101006C +:10E6A000000000000000000000000000000000006A +:10E6B0000101010101000000000000000000000055 +:10E6C0000000000000000000000000000000000149 +:10E6D000010101010101010101010101010100002C +:10E6E0000000000100000000000000000101010125 +:10E6F0000000000100010000000000010101010014 +:10E700000000000101010001000000010101010001 +:10E7100000000001000000000000000000000000F8 +:10E7200000000001000100000000000001010100E4 +:10E7300000000001000000000000000000000000D8 +:10E7400000000001000000000000000001010100C5 +:10E7500000010101010100000001000101010100AF +:10E7600000000001000100000001000101010100A2 +:10E770000000000100000000000000000101010095 +:10E780000000000100000000000000010101010084 +:10E79000010101010101010101010101010101006A +:10E7A0000000000000000000000000000000000069 +:10E7B0000101010101010100000000000000000052 +:10E7C0000000000000000000000000000000000148 +:10E7D000010101010101010101010101010100002B +:10E7E0000000000100000000000000000101010124 +:10E7F0000000000100010001000000010101010012 +:10E8000000000101010101010001000101010100FD +:10E8100000000001000000000000000001010000F5 +:10E8200000000001010100000000000001010100E2 +:10E8300000000001000000000000000000000000D7 +:10E8400000000001000100000001000001010100C2 +:10E8500001010101010101000001000101010100AC +:10E86000000000010101000100010001010101009F +:10E870000000000101000000000000010101010092 +:10E880000000000100010000000100010101010081 +:10E890000101010101010101010101010101010069 +:10E8A0000000000000000000000000000000000167 +:10E8B0000101010101010100000000000000010050 +:10E8C0000000000000000000000000000000000147 +:10E8D000010101010101010101010101010100002A +:10E8E0000100000100010000000000000101010121 +:10E8F0000000010100010001000000010101010010 +:10E9000000000101010101010101000101010100FB +:10E9100000000001000000000000000001010101F2 +:10E9200001000101010100000000000001010100DF +:10E9300000000101000000000000000000010000D4 +:10E9400000000001010100000001000101010100BF +:10E9500001010101010101010101000101010100A9 +:10E96000000101010101010100010001010101009B +:10E97000010101010101000000000001010101008D +:10E98000000000010101000101010001010101017C +:10E990000101010101010101010101010101010068 +:10E9A0000000000000000000000000000000000166 +:10E9B000010101010101010000000000000001004F +:10E9C0000000000000000000000000000000000146 +:10E9D0000101010101010101010101010101000029 +:10E9E0000100000100010000000000000101010120 +:10E9F000000001010101000100000001010101000E +:10EA000000000101010101010101010101010101F8 +:10EA100000000101000000000000000001010101F0 +:10EA200001000101010100010000000101010100DC +:10EA300000000101010000000000000000010100D1 +:10EA400000000001010101000001000101010101BC +:10EA500001010101010101010101000101010100A8 +:10EA60000001010101010101010100010101010099 +:10EA7000010101010101000000000001010101008C +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010101010101010101010067 +:10EAA0000000000000000000000000000000000165 +:10EAB000010101010101010100000001000001004C +:10EAC0000000000000000000000000000000000145 +:10EAD0000101010101010101010101010101000127 +:10EAE000010101010001000000010000010101011C +:10EAF0000101010101010101000100010101010009 +:10EB000000000101010101010101010101010101F7 +:10EB100000000101000000000000000001010101EF +:10EB200001010101010101010001000101010101D7 +:10EB300001000101010100000000000001010100CD +:10EB400000000001010101010101000101010101B9 +:10EB500001010101010101010101000101010100A7 +:10EB60000101010101010101010100010101010196 +:10EB70000101010101010100000100010101010089 +:10EB80000101010101010101010101010101010175 +:10EB90000101010101010101010101010101010066 +:10EBA0000000000000000000000000000000000164 +:10EBB0000101010101010101000000010101010049 +:10EBC0000000000000000000000000000000000144 +:10EBD0000101010101010101010101010101000126 +:10EBE0000101010101010001000100010101010118 +:10EBF0000101010101010101010100010101010106 +:10EC000001010101010101010101010101010101F4 +:10EC100001000101000100000000000001010101EC +:10EC200001010101010101010001000101010101D6 +:10EC300001000101010100000000000001010100CC +:10EC400000000101010101010101010101010101B6 +:10EC500001010101010101010101010101010100A5 +:10EC60000101010101010101010100010101010195 +:10EC70000101010101010101010100010101010086 +:10EC80000101010101010101010101010101010174 +:10EC90000101010101010101010101010101010065 +:10ECA0000000000000000000000000000000000163 +:10ECB0000101010101010101010000010101010047 +:10ECC0000000000000000000000000000000000242 +:10ECD0000101010101010101010101010101000125 +:10ECE0000101010101010001000100010101010117 +:10ECF0000101010101010101010101010101010104 +:10ED000001010101010101010101010101010101F3 +:10ED100001000101010100000000000001010101EA +:10ED200001010101010101010001000101010101D5 +:10ED300001010101010100000000000001010100CA +:10ED400000000101010101010101010101010101B5 +:10ED500001010101010101010101010101010101A3 +:10ED60000101010101010101010101010101010193 +:10ED70000101010101010101010101010101010084 +:10ED80000101010101010101010101010101010173 +:10ED90000101010101010101010101010101010064 +:10EDA0000000000000000000000000000000000162 +:10EDB0000101010101010101010101010101010044 +:10EDC0000000000000000000000000000000000241 +:10EDD0000201010201010101010101010101000122 +:10EDE0000101010101010001000100010101010116 +:10EDF0000101010101010101010101010101010103 +:10EE000001010101010101010101010101010101F2 +:10EE100001010101010100000000000001010101E8 +:10EE200001010101010101010101000101010101D3 +:10EE300001010101010100000000000001010100C9 +:10EE400001000101010101010101010101010101B3 +:10EE500001010101010101010101010101010101A2 +:10EE60000101010101010101010101010101010192 +:10EE70000101010101010101010101010101010182 +:10EE80000101010101010101010101010101010172 +:10EE90000101010101010101010101010101010063 +:10EEA0000000000000000000000000000000000161 +:10EEB0000101010101010101010101010101010043 +:10EEC000000000010000000000000000000000023F +:10EED000020201020202010101010101010100021D +:10EEE0000101010101010001000100010101010214 +:10EEF0000101010101010101010101010101010102 +:10EF000001010101010101010101010101010101F1 +:10EF100001010101010100000000000001010101E7 +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101000000000001010100C7 +:10EF400001000101010101010101010101010101B2 +:10EF500001010101010101010101010101010101A1 +:10EF60000101010101010101010101010101010191 +:10EF70000101010101010101010101010101010181 +:10EF80000101010101010101010101010101010171 +:10EF90000101010101010101010101010101010062 +:10EFA000000001000000000000000000000000015F +:10EFB0000202010101010101010101010101010040 +:10EFC000000001010000000000000000000000023D +:10EFD000020202020202020101010101010100021A +:10EFE0000201010101010001000100010101010212 +:10EFF0000101010101010101010101010101010101 +:10F0000001010101010101010101010101010102EF +:10F0100001010101010100000000000001010102E5 +:10F0200001010101010101010101010101010102CF +:10F0300001010101010101000000000101010101C4 +:10F0400001010101010101010101010101010101B0 +:10F0500001010101010101010101010101010101A0 +:10F060000101010101010101010101010101010190 +:10F070000101010101010101010101010101010180 +:10F080000101010101010101010101010101010170 +:10F090000101010101010101010101010101010061 +:10F0A000000001010000000000000000000000025C +:10F0B000020202010101010101010101010101003E +:10F0C000000001010000000000000000000000023C +:10F0D0000202020202020202010101010202000216 +:10F0E000020101020101010100010101020101020D +:10F0F00001010101010101010101010101010102FF +:10F1000001010102010101010101010101010102ED +:10F1100001010101010100000000000001010102E4 +:10F1200001010101010101010101010101010102CE +:10F1300001010101010101000001000101010101C2 +:10F1400001010101010101010101010101010102AE +:10F15000010101010101010101010101010101019F +:10F16000010101010101010101010101010101028E +:10F17000010101010101010101010101010101017F +:10F18000010101010101010101010101010101016F +:10F190000101010101010101010101010101010060 +:10F1A0000101010100000000000000000000000259 +:10F1B000020202020101010101010101010101003C +:10F1C000000101010000000000000000000000023A +:10F1D0000202020202020202020202020202000211 +:10F1E0000202010201010101010101010202010209 +:10F1F00001010102010101010101010101010102FD +:10F2000001010102010201010101010101010102EB +:10F2100001010102010100000000000001010102E2 +:10F2200002010102010101010101010101010102CB +:10F2300002010102010101010001000101010101BE +:10F2400001010101010101010101010101010102AD +:10F25000020201020101010101010101010101019B +:10F26000010101010101010101010101010101028D +:10F27000020101010101010101010101010101017D +:10F28000010101010101010101010101010101026D +:10F29000010102020201010101010101010101005C +:10F2A0000101010100000000000000000000000258 +:10F2B000020202020201010101010101010101003A +:10F2C0000001010100000000000000000000000239 +:10F2D0000202020202020202020202020202000210 +:10F2E0000202020201020101010101010202020205 +:10F2F00002010102010201010101010101010102FA +:10F3000002010202020201010101010101010202E6 +:10F3100002010102010100000000000001010102E0 +:10F3200002010102010101010101010101010102CA +:10F3300002010202010101010001000101010101BC +:10F3400001010101010101010101010101010102AC +:10F350000202020201010101010101010101010199 +:10F36000010101010101010101010101010101028C +:10F37000020201020101010101010101010101017A +:10F38000010101010101010101010101010101026C +:10F390000202020202020101010101010101010157 +:10F3A0000101010100000000000000000000000257 +:10F3B0000202020202010101010101010101010039 +:10F3C0000001010100000000000000000000000238 +:10F3D000020202020202020202020202020200020F +:10F3E0000202020202020101010101010202020203 +:10F3F00002020202010201010101010101010202F6 +:10F4000002020202020202020101010201020202E0 +:10F4100002010202010100000002020001010102DA +:10F4200002020202020201010101010102020102C3 +:10F4300002020202020101010001000101010101B9 +:10F4400001010101010101010101010101010102AB +:10F450000202020202020101010101020101010294 +:10F46000010101010101010101010101010101028B +:10F470000202020202010101010101010101010276 +:10F48000020101010101010101010101010101026A +:10F490000202020202020202010101010101010154 +:10F4A0000101010101000000000000000000000255 +:10F4B0000202020202020201010101010101010036 +:10F4C0000001010001000000000000000000000237 +:10F4D000020202020202020202020202020200020E +:10F4E0000202020202020102010201010202020200 +:10F4F00002020202020201020101010202020202F0 +:10F5000002020202020202020202010202020202DC +:10F5100002020202010100020201010201010102D4 +:10F5200002020202020201010101010102020202C1 +:10F5300002020202020201010001020101010102B4 +:10F5400001010102010101010101010101010102A9 +:10F55000020202020202020101020102020202028E +:10F560000202010201010101010101010101010287 +:10F570000202020202020101010101010102010273 +:10F580000202010201010101010101010101010267 +:10F59000020202020202020202020102020202014D +:10F5A0000101010101010000000000000101000251 +:10F5B0000202020202020201010101010101010035 +:10F5C0000101000001010100000000000000000234 +:10F5D000020202020202020202020202020200020D +:10F5E00002020202020201020102010202020202FE +:10F5F00002020202020202020101010202020202EE +:10F6000002020202020202020202020202020202DA +:10F6100002020202020201010101010102020102D1 +:10F6200002020202020202020101010102020202BE +:10F6300002020202020201010101010101020102B2 +:10F6400002010102020201010101010101010102A5 +:10F65000020202020202020202020102020202028B +:10F660000202020202020101010101020102010281 +:10F67000020202020202020101010102020202026E +:10F680000202020202020101010101010101010263 +:10F69000020202020202020202020202020202024A +:10F6A000010101010101000000000001010101024E +:10F6B0000202020202020202010101010101010033 +:10F6C0000100000001010101010000000000000232 +:10F6D000020202020202020202020202020200020C +:10F6E00002020202020202020102010202020202FC +:10F6F00002020202020202020202010202020202EB +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020201010101010102020202CF +:10F7200002020202020202020102010202020202BB +:10F7300002020202020202010101010102020202AE +:10F74000020102020202020101020101020202029E +:10F75000020202020202020202020102020202028A +:10F76000020202020202020201020102010202027C +:10F77000020202020202020202020102020202026A +:10F78000020202020202020202020102020202025A +:10F790000202020202020202020202020202020249 +:10F7A000020101010101010000000001010101024B +:10F7B000020202020202020202010102010102002F +:10F7C000010000000101010101000000010101022E +:10F7D000020202020202020202020202020200020B +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020201010101010102020202CE +:10F8200002020202020202020202010202020202B9 +:10F8300002020202020202010101010102020202AD +:10F840000202020202020202020201020202020299 +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020201020202020279 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F890000202020202020202020202020202020248 +:10F8A0000202020101010101000000010101010247 +:10F8B000020202020202020202020202020202002A +:10F8C000000000000101010101000000010101022E +:10F8D000020202020202020202020202020200020A +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020201010101010102020202CD +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202020102010202020202A9 +:10F940000202020202020202020202020202020297 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020201020202020278 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020201010101000100010101010244 +:10F9B0000202020202020202020202020202020029 +:10F9C000000000000001010101010000010101022D +:10F9D0000202020202020202020202020202000209 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020201010101010102020202CC +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020102010202020202A8 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020201010101010100010101010242 +:10FAB0000202020202020202020202020202020028 +:10FAC000000000000000000101010001010101022D +:10FAD0000202020202020202020202020202000208 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202010101010102020202CA +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202010202020202A6 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA000020202020201010101010101010101023F +:10FBB0000202020202020202020202020202020027 +:10FBC000000000000000000000010001010101022E +:10FBD0000202020202020202020202020202000207 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020102020202C5 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA000020202020202010101010101010101023D +:10FCB0000202020202020202020202020202020224 +:10FCC000000000000000000000010001010101022D +:10FCD0000202020202020202020202020202000206 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020202020202020202020243 +:10FDA000020202020202020101010101010101023B +:10FDB0000202020202020202020202020202020223 +:10FDC0000202000000000000000001010101010228 +:10FDD0000202020202020202020202020202010204 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202020202020242 +:10FEA0000202020202020202010101020202010236 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020000000000000001010101010225 +:10FED0000202020202020202020202020202010203 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202020202020241 +:10FFA0000202020202020202020201020202020232 +:10FFB0000202020202020202020202020202020221 +:10FFC0000202020200000000000001010000010125 +:10FFD0000101010101010101010101010101010210 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:0200000280007C +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C0000202020202000000000001000000000124 +:1000D0000101010101010101010101010101010011 +:1000E000000000000000000000000000000000020E +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C0000202020202020200000000000000000120 +:1001D0000101010101010101010101010101010010 +:1001E000000000000000000000000000000000020D +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000020202020202020202020202020202023E +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C0000202020202020202020000000202020115 +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010102FD +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020201AE +:1003300001010101010101010101010101010102AC +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C0000202020202020202020000020202020112 +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010102FC +:1003F00002020202020202020202020202020201DE +:1004000001010101010101010101010101010102DB +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020202020202020202023C +:1004A000020202020202020202020202020202022C +:1004B000020202020202020202020202020202021C +:1004C000020202020202020202020202020202010D +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010102EB +:1005000002020202020202020202020202020200CD +:1005100000000000000000000000000000000001DA +:1005200001010101010101010101010101010100BC +:1005300000000000000000000000000000000002B9 +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202016C +:10057000010101010101010101010101010101026A +:10058000020202020202020202020202020202024B +:10059000020202020202020202020202020202023B +:1005A000020202020202020202020202020202022B +:1005B000020202020202020202020202020202021B +:1005C000020202020202020202020202020202010C +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010100EC +:1006000000000000000000000000000000000001E9 +:1006100001010101010101010101010101010102C9 +:1006200002020202020202020202020202020200AC +:1006300000000000000000000000000000000002B8 +:10064000020202020202020202020202020202018B +:100650000101010101010101010101010101010289 +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202024A +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B0000200000000000000000000000000000236 +:1006C000020202020202020202020202020202010B +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010100BA +:1007300000000000000000000000000000000002B7 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:10076000020202020202020202020202020202006B +:100770000000000000000000000000000000000277 +:100780000202020202020202020202020202020249 +:100790000202020202020202020202020202020239 +:1007A000020202020202020202020202020202002B +:1007B0000000000000000000000000000000000237 +:1007C000020202020202020202020202020202010A +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010099 +:100850000000000000000000000000000000000296 +:10086000020202020202020202020202020202006A +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000266 +:10089000020202020202020202020202020202003A +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000236 +:1008C0000202020202020202020202020202020109 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010078 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000265 +:100990000202020202020202020202020202020039 +:1009A0000000000000000000000000000000000146 +:1009B0000101010101010101010101010101010226 +:1009C0000202020202020202020202020202020108 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010047 +:100AA0000000000000000000000000000000000145 +:100AB0000101010101010101010101010101010225 +:100AC0000202020202020202020202020202020107 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010026 +:100BC0000000000000000000000000000000000124 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010025 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000002E1 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020015 +:100DC0000000000000000000000000000000000023 +:100DD0000000000000000000000000000000000013 +:100DE0000000000000000000000000000000000003 +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000240 +:100EB0000202020202020202020202020202020014 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA000000000000000000000000000000000023F +:100FB0000202020202020202020202020202020013 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C00000000000000000000000000000000031EF +:1010D000000000000000000000000000000000010F +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000001000001000000000000000000000000DD +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000100010100010B +:1011E00001000101010100000000000000000000FA +:1011F00000000000000000000000000000000000EF +:1012000001000001000001000000000000000000DB +:1012100000000000000001000000000000000000CD +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D0000000000000000000010101010101010106 +:1012E00001000101010100010000000000000000F8 +:1012F00000000101000100010000000000000000EA +:1013000001000101010101000000000000000000D7 +:1013100001000101010101000000000000000000C7 +:1013200000000000000001000000000000000000BC +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000010000000000000000007C +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D0000000000000000000010101010101010105 +:1013E00001010101010100010000000000000000F6 +:1013F00000000101000101010000000000000100E7 +:1014000001000101010101000000000000000000D6 +:1014100001000101010101000000000000000000C6 +:1014200001000101010101000000000000000000B6 +:1014300000000101000100000000000000000000A9 +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:101460000100010101010100000000000000000076 +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000000000000000000001C +:1014D0000001000000000000010101010101010103 +:1014E00001010101010100010000000000000000F5 +:1014F00001000101010101010000000000000100E4 +:1015000001010101010101000000000000000000D4 +:1015100001010101010101000000000000000000C4 +:1015200001000101010101000000000000000000B5 +:1015300000000101000101000000000000000000A7 +:10154000000000000000000000000000000000009B +:10155000000000000000000000000001000000008A +:101560000100010101010100000000000000000075 +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:101590000000000100010000000000000000000049 +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C0000000000000000000000100000001000019 +:1015D0000101000000000001010101010101010100 +:1015E00001010101010100010000000000000000F4 +:1015F00001000101010101010000000100000100E2 +:1016000001010101010101000000000000000100D2 +:1016100001010101010101000000000000000000C3 +:1016200001000101010101000000000000000000B4 +:1016300001000101010101000000000000000000A4 +:10164000000000000000000000000000000000009A +:101650000000000000000000000000010000000089 +:101660000101010101010100000000000000000073 +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:101690000000000100010100000000000000000047 +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C0000000000000000000000100000001000018 +:1016D00001010000010000010101010101010101FE +:1016E00001010101010100010000000001000000F2 +:1016F00001000101010101010000000101000100E0 +:1017000001010101010101000000000001010100CF +:1017100001010101010101000101000100000100BE +:1017200001000101010101000000000000000000B3 +:1017300001000101010101000000000000000000A3 +:101740000000010100010000000000000000000096 +:101750000000000000000000010100010000010085 +:101760000101010101010100000000000000000072 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000100010101010100000000000000000043 +:1017A0000000000000000000000000000000000039 +:1017B0000000000100010001000000000000000026 +:1017C0000000000000000000000100000001000017 +:1017D00001010000010000010101010101010101FD +:1017E00001010101010100010000000101000100EF +:1017F00001000101010101010000000101000101DE +:1018000001010101010101000000000101010101CC +:1018100001010101010101010101010101000100BA +:1018200001010101010101000000000000000000B1 +:1018300001000101010101000000000000000000A2 +:101840000000010100010100000000000000000094 +:101850000000000100000000010101010101010080 +:101860000101010101010100000000000000000071 +:101870000000000000000000000000000000000068 +:101880000000000100010000000000000000010055 +:101890000100010101010100000000000000000042 +:1018A0000000000000000000000000000000000038 +:1018B0000000000100010101000000000000000024 +:1018C0000000000000000000000100000001000016 +:1018D00001010000010000010101010101010101FC +:1018E00001010101010100010000000101000100EE +:1018F00001010101010101010000000101010101DB +:1019000001010101010101000000000101010101CB +:1019100001010101010101010101010101000100B9 +:1019200001010101010101000000000100000100AE +:1019300001000101010101000000000000000000A1 +:101940000100010101010100000000000000000091 +:10195000000000010000000001010101010101017E +:101960000101010101010100000000000000000070 +:101970000000000000000000000000000000000067 +:101980000000000100010100000000000000010053 +:101990000101010101010100000000000000000040 +:1019A0000000000000000000000000000000000037 +:1019B0000100010101010101000000000000000020 +:1019C0000000000000000000000100000001010014 +:1019D00001010100010000010101010101010101FA +:1019E00001010101010100010100000101000100EC +:1019F00001010101010101010001000101010101D9 +:101A000001010101010101000001000101010101C9 +:101A100001010101010101010101010101010100B7 +:101A200001010101010101000000000101000100AC +:101A3000010101010101010000000000000000009F +:101A40000100010101010100000000000000000090 +:101A5000000001010001000001010101010101017B +:101A6000010101010101010000000000000000006F +:101A70000000000000000000000000000000000066 +:101A8000000001010101010001010001000001004D +:101A9000010101010101010000000000000000003F +:101AA0000000000000000000000000000000010035 +:101AB000010001010101010101000000000000001E +:101AC0000000000000000000000100000101010111 +:101AD00001010100010000020101010101010101F8 +:101AE00001010101010100020100000101010100E9 +:101AF00001010101010101010001010101010101D7 +:101B000001010101010101000001010101010101C7 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101000101000101000100A9 +:101B3000010101010101010000000000000000009E +:101B4000010001010101010000000001000000008E +:101B50000000010100010100010101010101010179 +:101B6000010101010101010000000000000000006E +:101B70000000000000000000000000000000000065 +:101B80000000010101010100010101010101010049 +:101B9000010101010101010000000000000000003E +:101BA0000000000000000000000000000100010033 +:101BB000010001010101010101000000000000001D +:101BC0000000000000000000000100000101010110 +:101BD00001010100010100020101010101010101F6 +:101BE00001010101010100020101000101010100E7 +:101BF00001010101010101020101010101010101D4 +:101C000001010101010101000101010101010101C5 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010100A5 +:101C30000101010101010100010100010000010099 +:101C4000010001010101010000000001010000008C +:101C50000000010101010101010101010101010176 +:101C6000010101010101010000000000000000006D +:101C70000000000000000000000000000100000063 +:101C80000100010101010100010101010101010146 +:101C9000010101010101010000000000000000003D +:101CA0000000000000000000000100010100010030 +:101CB000010001010101010101010001000000001A +:101CC000000000000000010000010001010101010D +:101CD00001010100010100020201010101010101F4 +:101CE00001010101010100020101010101010100E5 +:101CF00001010101010101020101010101010101D3 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010100010101010100010096 +:101D40000101010101010100000100010100000089 +:101D50000000010101010101010101010101010175 +:101D6000010101010101010000000000000000006C +:101D7000000000000000000001010001010001005E +:101D80000100010101010100010101010101010145 +:101D9000010101010101010000000000000000003C +:101DA000000000000000000000010101010101002D +:101DB0000101010101010101010101010100000016 +:101DC0000000000100010100010100010101010109 +:101DD00001010100010100020202020101010102F0 +:101DE00001010101010100020101010101010101E3 +:101DF00001010101010101020101010101010101D2 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010100010101010100010194 +:101E40000101010101010100000101010100000087 +:101E50000100010101010101010101010101010173 +:101E6000010101010101010000000000000000006B +:101E7000000000000000000001010101010101005B +:101E80000101010101010100010101010101010143 +:101E9000010101010101010000000000000000003B +:101EA0000000000100000000010101010101010129 +:101EB0000101010101010101010101010100010014 +:101EC0000000000100010100010101010101010107 +:101ED00001010100010100020202020202020102EC +:101EE00001010101010100020101010101010101E2 +:101EF00001010101010101020101010101010101D1 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101020101010101010101B0 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010100010101010100010084 +:101F50000100010101010101010101010101010172 +:101F6000010101010101010000000000000000006A +:101F70000000000000000000010101010101010159 +:101F80000101010101010101010101010101010141 +:101F90000101010101010100010100010000000037 +:101FA0000000000100000001010101010101010127 +:101FB0000101010101010101010101010101010012 +:101FC0000100010100010100010101010101010104 +:101FD00001010101010100020202020202020202E9 +:101FE00002020101020200020101010101010101DD +:101FF00001010101010101020101010101010101D0 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101020101010101010101AF +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010100010082 +:102050000101010101010101010101010101010170 +:102060000101010101010100000000000000000069 +:102070000000010100010001010101010101010154 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010000000034 +:1020A0000000010100010001010101010101010124 +:1020B0000101010101010102010101010101010010 +:1020C0000100010100010100010101010101010103 +:1020D00001010101010100020202020202020202E8 +:1020E00002020202020200020101010101010101DA +:1020F00001010101010101020101010101010101CF +:1021000001010101010101010101010101010101BF +:1021100001010101010101020201010101010101AD +:10212000010101010101010201010101010101019E +:10213000010101010101010101010101010101018F +:102140000101010101010101010101010100010081 +:10215000010101010101010101010101010101016F +:102160000101010101010100000000000000000068 +:102170000000010100010101010101010101010152 +:10218000010101010101010101010101010101013F +:102190000101010101010101010101010000000033 +:1021A0000000010100010101010101010101010122 +:1021B000010101010101010201010101010101000F +:1021C0000101010101010100010001010101010101 +:1021D00001010101010100020202020202020202E7 +:1021E00002020202020200020201010101010101D8 +:1021F00001010101010101020101010101010101CE +:1022000002010101010101010101010101010101BD +:1022100001010101010101020202010101010101AB +:10222000010101010101010201010101010101019D +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101007F +:10225000010101010101010202010101010101016C +:102260000101010101010100000000000000000067 +:102270000000010101010101010101010101010150 +:10228000010101010101010101010101010101013E +:102290000101010101010101010101010100000031 +:1022A0000000010101010101010101010101010120 +:1022B000010101010101010201010101010101010D +:1022C0000101010101010100010001010101010100 +:1022D00001010101010101020202020202020202E5 +:1022E00002020202020200020201010202010101D5 +:1022F00002010202010201020101010201010201C7 +:1023000002010102010101020101010101010101BA +:1023100001010101010101020202020201010101A8 +:10232000020101010101010202010101010101019A +:10233000010101010101010201010101010101018C +:10234000010101010101010101010101010101017D +:102350000101010101010102020201020101010169 +:102360000101010101010100010100000000000064 +:10237000000001010101010101010101010101014F +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010001002F +:1023A000000001010101010101010101010101011F +:1023B000010101010101010201010101010101010C +:1023C0000101010101010100010001010100010100 +:1023D00001010101010101020202020202020202E4 +:1023E00002020202020200020202010202010201D2 +:1023F00002010202020202020202010202010201C1 +:1024000002020202020202020101010101010101B4 +:1024100002010101010101020202020202010201A4 +:102420000201020202020202020201020101010192 +:102430000201020201020102020101010101010186 +:10244000010101010101010201010101010101017B +:102450000101010101010102020202020101010167 +:10246000020101010101010101010100010000005F +:10247000010001010101010101010101010101014D +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010001002E +:1024A000010001010101010101010101010101011D +:1024B000010101010101010202010101010101010A +:1024C00001010101010101000100010101000101FF +:1024D00000000101010101020202020202020202E5 +:1024E00002020202020200020202020202020201CF +:1024F00002020202020202020202020202020202BC +:1025000002020202020202020202010202020201AD +:10251000020202020202020202020202020202019C +:10252000020202020202020202020202020102018D +:102530000201020202020202020201010101010182 +:10254000010101010101010201010101010101017A +:102550000101010101010102020202020202020163 +:102560000202020202020201010101010100010056 +:10257000010001010101010201010101010101014B +:102580000101010101010102020101010101010139 +:10259000010101010101010201010101010001012B +:1025A000010001010101010201010101010101011B +:1025B0000101010101010102020101010101010109 +:1025C00001010101010101000000010101000101FF +:1025D00000000101010101020202020202020202E4 +:1025E00002020202020200020202020202020201CE +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202018B +:10263000020202020202020202020202010101017E +:102640000201020201020102020201020101010172 +:102650000101010101010102020202020202020261 +:102660000202020202020202010101010100010054 +:102670000100010101010102020101010101010149 +:102680000101010101010102020201010101010137 +:102690000101010101010102010101010101010129 +:1026A000010001010101010201010101010101011A +:1026B0000101010101010102020201010101010107 +:1026C00001010101010101000000010101000101FE +:1026D00000000101010101020202020202020202E3 +:1026E00002020202020200020202020202020202CC +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:10273000020202020202020202020202020102017B +:10274000020102020202020202020202020101016D +:10275000010101020101010202020202020202025F +:102760000202020202020202010101010100010053 +:102770000100010101010102020201010101010147 +:102780000101010101010102020202020101020133 +:102790000201010201020102020101010101010124 +:1027A0000100010101010102020201010101010117 +:1027B0000101010101010102020202020101010104 +:1027C0000101010101010100000001010000000000 +:1027D00000000101000101020202020202020202E3 +:1027E00002020202020200020202020202020202CB +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:10284000020202020202020202020202020101016B +:10285000010102020102010202020202020202025C +:102860000202020202020202020101010101010050 +:102870000101010101010102020202020201010142 +:10288000010101020102010202020202020202012E +:10289000020202020202020202020101010101011E +:1028A0000101010101010102020202020201020111 +:1028B00002010102010201020202020202010101FF +:1028C0000101010101010100000001000000000000 +:1028D00000000101000101020202020202020202E2 +:1028E00002020202020200020202020202020202CA +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020201020169 +:102950000201020202020202020202020202020258 +:10296000020202020202020202020101010101014D +:10297000010101010101010202020202020202013F +:102980000201020202020202020202020202020228 +:10299000020202020202020202020202010101011B +:1029A000010101010101010202020202020202010F +:1029B00002010202020202020202020202020201F9 +:1029C0000101010101010100000000000000000000 +:1029D00000000101000101020202020202020202E1 +:1029E00002020202020200020202020202020202C9 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020167 +:102A50000202020202020202020202020202020256 +:102A6000020202020202020202020201010101014B +:102A7000010101010101010202020202020202023D +:102A80000202020202020202020202020202020226 +:102A9000020202020202020202020202010101011A +:102AA000010101010101010202020202020202020D +:102AB00002020202020202020202020202020201F7 +:102AC00002010102010202000002000000000000F9 +:102AD00000000001000101020202020202020202E1 +:102AE00002020202020200020202020202020202C8 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020201010148 +:102B70000101020201020102020202020202020239 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020201010118 +:102BA000010101020101010202020202020202020B +:102BB00002020202020202020202020202020202F5 +:102BC00002020202010202000002000000020000F4 +:102BD00000020001000001020202020202020202DF +:102BE00002020202020200020202020202020202C7 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020201020146 +:102C70000201020202020202020202020202020235 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020201020116 +:102CA0000101020201020102020202020202020208 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202000202020202020200E8 +:102CD00002020201020001020202020202020202D8 +:102CE00002020202020200020202020202020202C6 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020144 +:102D70000201020202020202020202020202020234 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000201020202020202020202020202020204 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202000202020202020202E5 +:102DD00002020200020201020202020202020202D6 +:102DE00002020202020200020202020202020202C5 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000201020202020202020202020202020203 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202000202020202020202E4 +:102ED00002020200020201010202020202020201D7 +:102EE00002010202010101020202020202020202C6 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020200010101010101010101DC +:102FE00001010101010101020202020202020202C8 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020200010101010101010101DB +:1030E00001010101010101020202020202020202C7 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202010101010101010101D8 +:1031E00001010101010101010202020202020202C7 +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202010101010101010101D7 +:1032E00001010101010101020101010101010101CD +:1032F00001010101010101020202020202020202B5 +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202010101010101010101D6 +:1033E00001010101010101010202020202020202C5 +:1033F00002020202020202010202020202020202AE +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202010101010101010101D5 +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101020101010101010101BB +:1035000001010101010101020202020202020202A2 +:103510000202020202020201010101010101010194 +:103520000101010101010100000000000000000094 +:10353000000000000000000000000000000000008B +:103540000000000000000002020202020202020269 +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202010101010101010101D4 +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010202020202020202B3 +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020000000000000000008C +:10363000000000000000000000000000000000008A +:103640000000000000000001010101010101010171 +:103650000101010101010100000000000000000063 +:103660000000000000000001010101010101010151 +:103670000101010101010102020202020202020231 +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202010101010101010101D3 +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101000000000000000000B2 +:1037100000000000000000010101010101010101A0 +:103720000101010101010100000000000000000092 +:103730000000000000000000000000000000000089 +:103740000000000000000002020202020202020267 +:10375000020202020202020000000000000000005B +:103760000000000000000002020202020202020247 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202010101010101010101D2 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010100000000000000000081 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000002020202020202020226 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202000000000000000000FA +:1038C00000000000000000020202020202020202E6 +:1038D00002020202020202010101010101010101D1 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010100000000000000000070 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000002020202020202020225 +:103990000202020202020201010101010101010110 +:1039A00001010101010101020202020202020202FE +:1039B00002020202020202000000000000000000F9 +:1039C00000000000000000020202020202020202E5 +:1039D00002020202020202010101010101010101D0 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000101010101010101010101010101010176 +:103A40000101010101010101010101010101010166 +:103A50000101010101010101010101010101010156 +:103A6000010101010101010000000000000000004F +:103A70000000000000000000000000000000000046 +:103A80000000000000000002020202020202020224 +:103A90000202020202020202020202020202020206 +:103AA0000202020202020200000000000000000008 +:103AB00000000000000000010101010101010101FD +:103AC00001010101010101020202020202020202DD +:103AD00002020202020202010101010101010101CF +:103AE00001010101010101010101010101010101C6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000101010101010101010101010101010135 +:103B80000101010101010101010101010101010125 +:103B9000010101010101010000000000000000001E +:103BA0000000000000000000000000000000000015 +:103BB00000000000000000010101010101010101FC +:103BC00001010101010101020202020202020202DC +:103BD00002020202020202010101010101010101CE +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C60000101010101010101010101010101010144 +:103C70000101010101010101010101010101010134 +:103C80000101010101010101010101010101010124 +:103C90000101010101010101010101010101010114 +:103CA0000101010101010101010101010101010104 +:103CB00001010101010101010101010101010101F4 +:103CC00001010101010101020202020202020202DB +:103CD00002020202020202010101010101010101CD +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010101B4 +:103D000001010101010101010101010101010101A3 +:103D10000101010101010101010101010101010193 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000101010101010101010101010101010103 +:103DB00001010101010101010101010101010101F3 +:103DC00001010101010101020202020202020202DA +:103DD00002020202020202000000000000000000D5 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E10000000000000000002020202020202020290 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202000000000000000000E4 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB00000000000000000020202020202020202EF +:103FC00002020202020202000000000000000000E3 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B00000000000000000020202020202020202EE +:1040C00002020202020202000000000000000000E2 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000310000000000000000AE +:1041E00000000000000000000100000000000000CE +:1041F00000000000000000000000000000010000BE +:1042000000000000000000000000000000010000AD +:10421000000000000000000000000100000001009C +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000100007D +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000100004D +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000100002D +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000100000D +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000010100000000000000CC +:1042F00000000000000000000000000000010000BD +:1043000000000000000000000000010000010100AA +:10431000000000000000000000000100000001009B +:10432000000000000000000000000000000100008C +:10433000000000000000000000000000000100007C +:10434000000000000000000000000000000100006C +:10435000000000000000000000000000000100005C +:10436000000000000000000000000000000100004C +:10437000000000000000000000000000000100003C +:10438000000000000000000000000000000100002C +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000100000C +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000010101000000000000CA +:1043F00000000000000000000000000000010000BC +:1044000000000000000000000000010000010100A9 +:104410000000000000000000000001010100010098 +:104420000000000000000000000001000001010089 +:10443000000000000000000000000000000100007B +:10444000000000000000000000000000000100006B +:10445000000000000000000000000000000100005B +:10446000000000000000000000000000000100004B +:10447000000000000000000000000000000100003B +:104480000000000000000000000001000001010029 +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000100000B +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000010101010100000000C7 +:1044F00000000000000000000000000000010000BB +:1045000000000000000000000000010101010100A6 +:104510000000000001010000010001010100010094 +:104520000000000000000000000001000001010088 +:104530000000000000000000000001000001010078 +:10454000000000000000000000000000000100006A +:104550000000000000000000000001000001010058 +:10456000000000000000000000000000000100004A +:104570000000000000000000000000000001010039 +:104580000000000000000000000001000001010028 +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000100000A +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000010100010101010100000000C4 +:1045F00000000000000000000000010000010100B8 +:1046000000000000000000000100010101010100A4 +:104610000000000001010100010001010100010092 +:104620000000000000000000000001010101010085 +:104630000000000000000000000001000001010077 +:104640000000000000000000000000000001000069 +:104650000000000000000000000001000001010057 +:104660000000000000000000000001000001010047 +:104670000000000000000000000000000001010038 +:104680000000000000000000000001010101010025 +:10469000000000000000000000000000000000001A +:1046A0000000000000000000000000000001000009 +:1046B00000000000000000000000000000010000F9 +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000010101010101010100000000C2 +:1046F00000000000000000000000010000010100B7 +:1047000000000000000000000100010101010100A3 +:10471000000000010101010001010101010001008F +:104720000000000001000000000001010101010083 +:104730000000000000000000000001010101010074 +:104740000000000000000000000000000001000068 +:104750000000000000000000000001010101010054 +:104760000000000000000000000001000001010046 +:104770000000000000000000000001010101010034 +:104780000000000000000000010101010101010022 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000001000008 +:1047B00000000000000000000000000000010000F8 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000010101010101010100000000C1 +:1047F00000000000000000000000010100010100B5 +:10480000000100000100000001010101010101009F +:10481000000000010101010101010101010001008D +:104820000000000001000000000001010101010082 +:104830000000000001000000000001010101010072 +:104840000000000000000000000000000001000067 +:104850000000000001010000000001010101010051 +:104860000000000000000000000001010101010043 +:104870000000000000000000010001010101010032 +:10488000000000000000010101010101010101001F +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000001000001010005 +:1048B00000000000000000000000000000010000F7 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000010101010101010100000000C0 +:1048F00000000000000000000000010100010100B4 +:10490000000100000100010001010101010101009D +:10491000000101010101010101010101010001008A +:10492000000100010101000001010101010101007C +:104930000000000001000000000001010101010071 +:104940000000000000000000000001000001010064 +:104950000000000001010000000001010101010050 +:104960000000000001000000010001010101010040 +:10497000000000000000010101000101010101002F +:10498000000000000101010101010101010101001C +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000001000001010004 +:1049B00000000000000000000000000000010000F6 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000010101010101010101010100000000BC +:1049F00000000000000000000000010101010100B2 +:104A0000000101000101010001010101010101009A +:104A10000001010101010101010101010101010088 +:104A20000001000101010101010101010101010079 +:104A3000000100000101000001010101010101006C +:104A40000000000000000000000001000001010063 +:104A5000000100010101000001010101010101004B +:104A6000000000000100010001000101010101003E +:104A7000000000000101010101010101010101002B +:104A8000000000000101010101010101010101001B +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000001010101010001 +:104AB00000000000000000000000000000010100F4 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000010000D5 +:104AE00000010101010101010101010101000000BA +:104AF00000000000000000000000010101010100B1 +:104B00000001010001010101010101010101010098 +:104B10000001010101010101010101010101010087 +:104B20000001010101010101010101010101010077 +:104B3000000100000101010001010101010101006A +:104B40000000000000000000000001010101010060 +:104B50000001000101010101010101010101010048 +:104B6000000000000101010001010101010101003B +:104B7000000000000101010101010101010101002A +:104B80000001010101010101010101010101010017 +:104B90000000000000000000000000000001000014 +:104BA00000000000000000000100010101010100FF +:104BB00000000000000000000000000000010100F3 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000010000D4 +:104BE00000010101010101010101010101000000B9 +:104BF00000000000000000000000010101010100B0 +:104C00000001010101010101010101010101010096 +:104C10000101010101010101010101010101010085 +:104C20000101010101010101010101010101010075 +:104C30000001010101010100010101010101010067 +:104C4000000000000000000000000101010101005F +:104C50000001010101010101010101010101010046 +:104C60000000000001010101010101010101010039 +:104C70000001000101010101010101010101010027 +:104C80000001010101010101010101010101010016 +:104C90000000000000000000000000000001000013 +:104CA00000000000000001000100010101010100FD +:104CB00000000000000001000000010101010101ED +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000010101010000D0 +:104CE00001010101010101010101010101010000B6 +:104CF00000010000010000000101010101010100AB +:104D00000001010101010101010101010101010095 +:104D10000101010101010101010101010101010084 +:104D20000101010101010101010101010101010074 +:104D30000101010101010101010101010101010064 +:104D4000000000000000000000000101010101005E +:104D50000001010101010101010101010101010045 +:104D60000001010101010101010101010101010035 +:104D70000001000101010101010101010101010026 +:104D80000001010101010101010101010101010015 +:104D90000000000000000000000000000001000012 +:104DA00000010000010101000101010101010100F8 +:104DB00000000000000001000100010101010101EB +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000101010101010000CD +:104DE00001010101010101010101010101010001B4 +:104DF00000010000010000000101010101010100AA +:104E00000001010101010101010101010101010094 +:104E10000101010101010101010101010101010083 +:104E20000101010101010101010101010101010073 +:104E30000101010101010101010101010101010063 +:104E4000000000000100000001010101010101005A +:104E50000001010101010101010101010101010044 +:104E60000001010101010101010101010101010034 +:104E70000001010101010101010101010101010024 +:104E80000101010101010101010101010101010013 +:104E90000000000000000000000000000001000011 +:104EA00000010000010101010101010101010100F6 +:104EB00000000000000001000100010101010101EA +:104EC00000000000000000010000000000000000E1 +:104ED00000000000000001000101010101010000CB +:104EE00001010101010101010101010101010001B3 +:104EF00000010100010000000101010101010100A8 +:104F00000101010101010101010101010101010092 +:104F10000101010101010101010101010101010082 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010062 +:104F40000000000001000101010101010101010057 +:104F50000101010101010101010101010101010042 +:104F60000001010101010101010101010101010033 +:104F70000101010101010101010101010101010022 +:104F80000101010101010101010101010101010012 +:104F90000000000000000000000000000001000010 +:104FA00000010101010101010101010101010100F3 +:104FB00000010100010101000101010101010101E4 +:104FC00000000000000000010000000000000000E0 +:104FD00000000000010101000101010101010000C8 +:104FE00001010101010101020201010101010001B0 +:104FF00000010100010001000101010101010100A6 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010061 +:105040000001010001010101010101010101010053 +:105050000101010101010101010101010101010041 +:105060000101010101010101010101010101010031 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010011 +:10509000000000000000000000000000000100000F +:1050A00001010101010101010101010101010100F1 +:1050B00000010100010101010101010101010101E2 +:1050C00001000000000000010000000000010000DD +:1050D00000000000010101000101010101010101C5 +:1050E00001010101020201020202010101010001AC +:1050F00000010100010101000101010101010101A3 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:105130000101010101010101010101010101010060 +:105140000001010001010101010101010101010151 +:105150000101010101010101010101010101010040 +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:105180000101010101010101010101010101010010 +:10519000000000000000000000000000000100000E +:1051A00001010101010101010101010101010100F0 +:1051B00000010101010101010101010101010101E0 +:1051C00001000000000000010000000000010000DC +:1051D00001010101010101000101010101010102BF +:1051E00002020202020202020202010101010002A5 +:1051F00000010100010101010101010101010101A1 +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101005F +:10524000000101010101010101010101010101014F +:10525000010101010101010101010101010101003F +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101000F +:10529000000000000000000000000000000100000D +:1052A00001010101010101010101010101010100EF +:1052B00000010101010101010101010101010102DE +:1052C00001000000000000010000000000010000DB +:1052D00001010101010101000101010101010102BE +:1052E00002020202020202020202020201010002A2 +:1052F000000101010101010101010101010101019F +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101026C +:10533000010101010101010101010101010101005E +:10534000010101010101010101010101010101014D +:10535000010101010101010101010101010101003E +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101000E +:10539000000000000000000000000000000101000B +:1053A00001010101010101010101010101010100EE +:1053B00000010101010101010101010101010102DD +:1053C00001010101000000010000000000010000D7 +:1053D00001010101010101000101010101010102BD +:1053E00002020202020202020202020201010002A1 +:1053F000010101010101010101010101010201019C +:10540000010201010101010101010201010101018A +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101026B +:105430000202010102010101010102010101010059 +:10544000010101010101010101010101010101014C +:10545000010101010101010101010101010101013C +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101000D +:105490000001000000000000000000000001010108 +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010102DB +:1054C00001010101000000010000000000010100D5 +:1054D00001010101010101000101010101010102BC +:1054E00002020202020202020202020201010002A0 +:1054F0000101010101010101010102010102010299 +:105500000102020102010101020102020202020182 +:105510000101010202020101010102010101010276 +:105520000202010202010101010102010101010265 +:105530000202020202020101010102020202020051 +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101000C +:105590000101000000000000000000000001010106 +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010102DA +:1055C00001010101010100010000000000010100D2 +:1055D00001010101010101000101010101010102BB +:1055E000020202020202020202020202020100029E +:1055F0000102010101010101010102020102020295 +:10560000020202020202020102020202020202027B +:10561000020202020202020102010202020102026D +:10562000020202020202010101010202020202025E +:10563000020202020202020102020202020202004D +:105640000101010101010101010101010101010249 +:105650000102010202020101010102010102010134 +:105660000101010101010101010101010101010229 +:105670000101010101010101010101010102010119 +:10568000010101010101010101010101010101000B +:105690000101010001000000010000000001010102 +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010102D9 +:1056C00002010101010101010000010100010100CD +:1056D00001010101010101000101010101010102BA +:1056E000020202020202020202020202020100029D +:1056F0000102020102010101010102020202020291 +:105700000202020202020202020202020202020279 +:10571000020202020202020202020202020102026A +:105720000202020202020202020202020202020259 +:10573000020202020202020202020202020202014A +:105740000101010101010101010101010102010247 +:10575000020202020202010101010202020202012E +:105760000101010101010101010101010102010227 +:10577000020201020202020202010202020202020B +:105780000101010101010101010102010102010107 +:1057900001010100010001010100010100010101FD +:1057A00001010101010101010101010101020101E8 +:1057B00001010101010101010101010101010102D8 +:1057C00002010101010101010000010100010100CC +:1057D00001010101010101000101010101010102B9 +:1057E000020202020202020202020202020100029C +:1057F000020202010201010102020202020202028D +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020201020269 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020149 +:105840000101010101010101010101010102010246 +:105850000202020202020202020202020202020129 +:105860000101010102010101010102010102010224 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020201F9 +:1058900001010101010101010101010100010101F9 +:1058A00001010101010101010101010101020101E7 +:1058B00001010101010101010101010101010102D7 +:1058C00002010101010101020000010101010100C9 +:1058D00000010101010101000101010101010102B9 +:1058E000020202020202020202020202020200029A +:1058F0000202020202020201020202020202020289 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020201020268 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020148 +:105940000101010101010101010102010102010244 +:105950000202020202020202020202020202020227 +:105960000202020202020201020102020202020219 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900001010101010101010101010101010102F6 +:1059A00002020101010101010101020101020101E3 +:1059B00001010101010101010101010101010102D6 +:1059C00002020202010101020101010101010100C3 +:1059D00000010101010101000101010101010102B8 +:1059E0000202020202020202020202020202000299 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020201020267 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A4000020202010201010101010202020202023C +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002010101010101010101010101020102F3 +:105AA00002020202020202010201020202020202D8 +:105AB00001010101010101010101010101020102D4 +:105AC00002020202010101020101010101010100C2 +:105AD00000010101010101010101010101010102B6 +:105AE0000202020202020202020202020202000298 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020101010101010101010101020102F1 +:105BA00002020202020202020202020202020202D5 +:105BB00001020201010102010101010101020102D0 +:105BC00002020202020201020101010101020100BE +:105BD00000000000000000010000000000000102C1 +:105BE0000202020202020202020202020202000297 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020201010101010101010101020102EF +:105CA00002020202020202020202020202020202D4 +:105CB00002020202020202010201020202020202C6 +:105CC00002020202020202020101010101020100BC +:105CD00002020202020202010202020202020102A6 +:105CE0000202020202020202020202020202000296 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020101010101010101020102EC +:105DA00002020202020202020202020202020202D3 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020101020201020200B8 +:105DD00002020202020202010202020202020102A5 +:105DE0000202020202020202020202020202000295 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020201010101020202E6 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020200B4 +:105ED00002020202020202010202020202020002A5 +:105EE0000202020202020202020202020202000294 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020201020202E2 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202010202020202020202A2 +:105FE0000202020202020202020202020202000293 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202010202020202020201A2 +:1060E000010101010101010101010202020201029B +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D00002020202020202000202020202020201A2 +:1061E000010101010101010101010101010201029D +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202019F +:1062E000010101010101010101010101010101029D +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202019E +:1063E000010101010101010101010101010101009E +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202019D +:1064E000010101010101010101010101010101019C +:1064F000000000000000000000000000000000029A +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202004D +:106530000000000000000000000000000002000257 +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202019C +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101028A +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202004C +:106630000000000000000000000000000002000256 +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202019B +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101008B +:106700000000000000000000000000000002000285 +:10671000020202020202020202020202020202005B +:106720000000000000000000000000000002000067 +:106730000000000000000000000000000002000255 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020201BA +:1067C00001010101010101010101010101010102B8 +:1067D000020202020202020202020202020202019A +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010277 +:106810000202020202020202020202020202020159 +:106820000101010101010101010101010101010059 +:106830000000000000000000000000000000000256 +:106840000202020202020202020202020202020129 +:106850000101010101010101010101010101010227 +:106860000202020202020202020202020202020109 +:106870000101010101010101010101010101010207 +:1068800002020202020202020202020202020201E9 +:1068900001010101010101010101010101010102E7 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020199 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010102010166 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010246 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020200B9 +:1069C00000000000000000000000000000000002C5 +:1069D0000202020202020202020202020202020198 +:1069E0000101010101010101010101010101010197 +:1069F0000101010101010101010101010101010187 +:106A00000101010101010101010101010101010176 +:106A10000101010101010101010101010101010166 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000101010101010101010101010101010037 +:106A50000000000000000000000000000000000234 +:106A60000202020202020202020202020202020008 +:106A70000000000000000000000000000000000214 +:106A800002020202020202020202020202020200E8 +:106A900000000000000000000000000000000002F4 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020200B8 +:106AC00000000000000000000000000000000002C4 +:106AD0000202020202020202020202020202020197 +:106AE0000101010101010101010101010101010196 +:106AF0000101010101010101010101010101010186 +:106B00000101010101010101010101010101010175 +:106B10000101010101010101010101010101010165 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010016 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000001F4 +:106BA00001010101010101010101010101010102D4 +:106BB00002020202020202020202020202020201B6 +:106BC00001010101010101010101010101010102B4 +:106BD0000202020202020202020202020202020196 +:106BE0000101010101010101010101010101010195 +:106BF0000101010101010101010101010101010185 +:106C00000101010101010101010101010101010174 +:106C10000101010101010101010101010101010164 +:106C20000101010101010101010101010101010154 +:106C30000101010101010101010101010101010144 +:106C40000101010101010101010101010101010134 +:106C50000101010101010101010101010101010124 +:106C60000101010101010101010101010101010114 +:106C70000101010101010101010101010101010104 +:106C800001010101010101010101010101010100F5 +:106C900000000000000000000000000000000002F2 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020201B5 +:106CC00001010101010101010101010101010102B3 +:106CD0000202020202020202020202020202020195 +:106CE0000101010101010101010101010101010194 +:106CF0000101010101010101010101010101010184 +:106D00000101010101010101010101010101010173 +:106D10000101010101010101010101010101010163 +:106D20000101010101010101010101010101010153 +:106D30000101010101010101010101010101010143 +:106D40000101010101010101010101010101010133 +:106D50000101010101010101010101010101010123 +:106D60000101010101010101010101010101010113 +:106D70000101010101010101010101010101010103 +:106D800001010101010101010101010101010101F3 +:106D900001010101010101010101010101010101E3 +:106DA00001010101010101010101010101010101D3 +:106DB00001010101010101010101010101010101C3 +:106DC00001010101010101010101010101010100B4 +:106DD00000000000000000000000000000000001B2 +:106DE0000101010101010101010101010101010193 +:106DF0000101010101010101010101010101010183 +:106E00000101010101010101010101010101010172 +:106E10000101010101010101010101010101010162 +:106E20000101010101010101010101010101010152 +:106E30000101010101010101010101010101010142 +:106E40000101010101010101010101010101010132 +:106E50000101010101010101010101010101010122 +:106E60000101010101010101010101010101010112 +:106E70000101010101010101010101010101010102 +:106E800001010101010101010101010101010101F2 +:106E900001010101010101010101010101010101E2 +:106EA00001010101010101010101010101010101D2 +:106EB00001010101010101010101010101010101C2 +:106EC00001010101010101010101010101010100B3 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F1000000000000000000000000000000000026F +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020200A3 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000002CE +:1070C00002020202020202020202020202020200A2 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000002CD +:1071C00002020202020202020202020202020200A1 +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D000000000000000000000000000000000317D +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000001000000000000000000EC +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000001000000000000000000007B +:10741000000000000001000000000000000000006B +:10742000000000000000010000000000000000005B +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000001FB +:1074900000000000000101000000000000000000EA +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000100000000000000000000BB +:1074D00000000000000001000000000000000000AB +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:107500000000000000010100000000000000000079 +:107510000000010000010100000000000000000068 +:107520000000000000010100000000000000000059 +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000001FA +:1075900000000101010101000000000000000000E6 +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000101000000000000000000B9 +:1075D00000000000000001000000000000000000AA +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:107600000000000000010100000000000000000078 +:107610000000010000010100000000000000000067 +:107620000000010100010100000000000000000056 +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000001F9 +:1076900001000101010101000000000000000000E4 +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000101000000000000000000B8 +:1076D00000000000000001000000000000000000A9 +:1076E0000000000000000000000000000000000199 +:1076F0000100000000000000000000000000000089 +:107700000000010100010100000000000000000075 +:107710000000010101010100000000000000000163 +:107720000100010100010100000000000000000054 +:107730000000000000000000000000000000000049 +:107740000000000000010000000000000000000038 +:107750000000000000000100000000000000000028 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000010001F7 +:1077900001000101010101000000000000000000E3 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000101000101000000000000000000B5 +:1077D00000000000000101000000000000000000A7 +:1077E0000000000000000000000000000001000197 +:1077F0000100000000000000000000000000000187 +:107800000100010100010100000000000000000172 +:107810000100010101010100000000000000010160 +:107820000100010101010100000000000000000052 +:107830000000000000010000000000000000000047 +:107840000000000000010100000000000000000036 +:107850000000000000010100000000000000000026 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000001010001F5 +:1078900001010101010101000000000000000000E1 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000001C7 +:1078C00001000101000101000000000000000000B3 +:1078D00000000101000101000000000000000000A4 +:1078E0000000000000000000000000000001000196 +:1078F0000100000000000000000000010000000185 +:107900000100010101010100000000000000000170 +:10791000010001010101010000000000010001015E +:107920000101010101010100000000000000000050 +:107930000000000000010100000000000000000045 +:107940000000000000010100000000000000000035 +:107950000000010101010100000000000000000022 +:107960000000000000010000000000000000000016 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000101010101F2 +:1079900001010101010101000000000000000000E0 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000101C5 +:1079C00001000101010101000000000000000000B1 +:1079D00000000101000101000000000000000000A3 +:1079E0000000000000000000000000000001010194 +:1079F0000100000001000000000000010000000183 +:107A0000010101010101010000000000010000016D +:107A1000010101010101010000000001010101015A +:107A2000010101010101010000000000000000004F +:107A30000000000000010100000000000000000044 +:107A40000000010000010100000000000000000132 +:107A50000100010101010100000000000000000020 +:107A60000000000000010100000000000000000014 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000101010101F1 +:107A900001010101010101000000000000000000DF +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000001000101C3 +:107AC00001010101010101000000000100000000AE +:107AD00000000101010101000000000000000000A1 +:107AE0000000000000000000000000000101010192 +:107AF0000100000001000000000000010001010180 +:107B00000101010101010100000000010101010169 +:107B10000101010101010100000000010101010159 +:107B2000010101010101010000000000000000004E +:107B30000000000000010100000000000000000043 +:107B40000000010000010100000000000000000131 +:107B5000010001010101010000000000000000001F +:107B60000000000000010100000000000000000013 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000010101010101EF +:107B900001010101010101000000000000000000DE +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000101010101C0 +:107BC00001010101010101000000000101000001AB +:107BD000010001010101010000000000000000009F +:107BE000000000000000000000000101010101018F +:107BF000010000000100000000000001010101017E +:107C00000101010101010100000000010101010168 +:107C10000101010101010101000000010101010157 +:107C2000010101010101010000000000000000004D +:107C30000000000000010100000000000000000042 +:107C4000000001010001010000000000010000012E +:107C5000010101010101010000000000000000001D +:107C60000000010100010100000000000000000010 +:107C70000000000000000000000000000000000004 +:107C800000000000000100000001010101010101EC +:107C900001010101010101000000000000000000DD +:107CA00000000000000100000000000000000000D3 +:107CB00000000000000000000000000101010101BF +:107CC00001010101010101010000000101010101A7 +:107CD000010001010101010000000000000000009E +:107CE000000000000000000000010101010101018D +:107CF000010100000100000000000001010101017C +:107D00000101010101010101000000010101010166 +:107D10000101010101010101000100010101010155 +:107D2000010101010101010000000000000000004C +:107D30000000000000010100000000000000000041 +:107D4000000001010001010000000001010101012A +:107D5000010101010101010000000000000000011B +:107D6000000001010001010000000000000000000F +:107D70000000000000000000000000000000000003 +:107D800000000000000101010001010101010101E9 +:107D900001010101010101000000000000000000DC +:107DA00000000000000101000000000000000000D1 +:107DB00000000000000100000000010101010101BC +:107DC00001010101010101010101000101010101A4 +:107DD000010101010101010000000000000000009C +:107DE000000000000000000000010101010101018C +:107DF000010100010100000000000001010101017A +:107E00000101010101010101000000010101010165 +:107E10000101010101010101000101010101010153 +:107E2000010101010101010000000000000000004B +:107E3000000000000001010000000000000100003F +:107E40000000010101010100000000010101010128 +:107E5000010101010101010000000000000000011A +:107E6000000001010101010000000000000000000D +:107E70000000000000000000000000000000000002 +:107E800000000000000101010101010101010101E7 +:107E900001010101010101000000000000000000DB +:107EA00000000000000101000000000000000000D0 +:107EB00000000000000101000001010101010101B9 +:107EC00001010101010101010101010101010101A2 +:107ED000010101010101010000000000000000009B +:107EE000000000000000000100010101010101018A +:107EF0000101000101010000000001010101010177 +:107F00000101010101010101000001010101010163 +:107F10000101010101010101000101010101010152 +:107F2000010101010101010000000000000000004A +:107F3000000000000001010000000000000100013D +:107F40000100010101010100000000010101010126 +:107F50000101010101010100000000000100000118 +:107F6000010001010101010000000000000000000B +:107F70000000000000000000000000000000000001 +:107F800000000100000101010101010101010101E5 +:107F900001010101010101000000000000000000DA +:107FA00000000100000101000000000000000000CE +:107FB00000000000000101010001010101010101B7 +:107FC00001010101010101010101010101010101A1 +:107FD000010101010101010000000000000000009A +:107FE0000000000000000001000101010101010189 +:107FF0000101000101010000000001010101010176 +:108000000101010101010101000101010101010161 +:108010000101010101010101000101010101010151 +:108020000101010101010100000000000000000148 +:10803000010000000001010100000000000100013A +:108040000100010101010100000100010101010124 +:108050000101010101010100000000010101010114 +:10806000010001010101010000000000000000000A +:108070000000000000000000000000000000000000 +:1080800000000100000101010101010101010101E4 +:1080900001010101010101000000000000000000D9 +:1080A00000000100000101000000000000000000CD +:1080B00000000100000101010101010101010101B4 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010100000000000000000099 +:1080E0000000000000000001000101010101010188 +:1080F0000101000101010001000001010101010174 +:108100000101010101010101000101010101010160 +:10811000010101010101010101010101010101014F +:108120000101010101010100000000000000010146 +:108130000100010001010101000000000101000136 +:108140000100010101010100000101010101010122 +:108150000101010101010100000000010101010113 +:108160000101010101010100000000000000000008 +:1081700000000000000100000000000000000000FE +:1081800000000101010101010101010101010101E1 +:1081900001010101010101000000000000000000D8 +:1081A00000000101000101000000000000000000CB +:1081B00000000100000101010101010101010101B3 +:1081C000010101010101010101010101010101019F +:1081D0000101010101010100000000000000000098 +:1081E0000000000000000001000202010102010283 +:1081F0000201000101010001000101010101010171 +:10820000010101010101010100010101010101015F +:10821000010101010101010101010101010101014E +:108220000101010101010100000000000000010145 +:108230000101010001010101000000010101010132 +:108240000100010101010100000101010101010121 +:108250000101010101010101000001010101010110 +:108260000101010101010100000000000000000007 +:1082700000000000000101000000000000000001FB +:1082800001000101010101010101010101010101DF +:1082900001010101010101000000000000000001D6 +:1082A00000000101000101000000000000000000CA +:1082B00000000101010101010101010101010101B0 +:1082C000010101010101010101010101010101019E +:1082D0000101010101010100000000000000000097 +:1082E000000000000000000201020202020202027D +:1082F0000201000101010001000101010101010170 +:10830000010101010101010100010101010101015E +:10831000010101010101010101010101010101014D +:108320000101010101010101000000000001010142 +:10833000010101010101010101010001010101012E +:10834000010101010101010100010101010101011E +:10835000010101010101010100010101010101010E +:108360000101010101010100000000000000000006 +:1083700000000000000101000000000000010001F9 +:1083800001000101010101010101010101010101DE +:1083900001010101010101000000000100010001D3 +:1083A00000000101010101000000000000000001C7 +:1083B00000000101010101010101010101010101AF +:1083C000010101010101010101010101010101019D +:1083D0000101010101010100020000000000000094 +:1083E000000000000000000201020202020202027C +:1083F000020100010201000100010101010101016E +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101000000010101013F +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010100010101010101010D +:108460000101010101010100000000000000000005 +:1084700000000100000101000001000001010001F5 +:1084800001010101010101010101010101010101DC +:1084900001010101010101000000000101010001D1 +:1084A00000010101010101000000000000010001C4 +:1084B00000000101010101010101010101010101AE +:1084C000010101010101010101010101010101019C +:1084D0000101010101010100020000000000000093 +:1084E0000000010100000002020202020202020278 +:1084F000020200010201000100010102010101016B +:10850000010101010102010101010101010101015A +:10851000010101010101010101010101010101014B +:10852000010101010101010101000000010101013E +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:108560000101010101010100000000000000000004 +:1085700000000100000101000001000101010101F2 +:1085800001010101010101010101010101010101DB +:1085900001010101010101010000010101010101CD +:1085A00000010101010101000000000001010001C2 +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010201010101010101019A +:1085D0000101010101010100020000000000000191 +:1085E0000101010100000002020202020202020275 +:1085F0000202000102010001010101020101010268 +:108600000201020201020202010101010101010154 +:108610000101020101020102010101010101010147 +:10862000010101010101010101000000010101013D +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:108660000101010101010100000000000000000003 +:1086700000000101010101000101000101010101EE +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010000010101010101BC +:1086B00001010101010101010101010101010101AA +:1086C0000101010101010102020101020101010197 +:1086D000010101010101020001000000000101018E +:1086E0000101010101000002020202020202020273 +:1086F0000202010102010002010101020202020262 +:10870000020202020202020201010102020101024E +:10871000020102020202020201010102020102023E +:108720000201020201020201010001010101010135 +:108730000101010101020102010101010101010127 +:108740000101010101020101010101010101010118 +:108750000101010101010101010101010101010109 +:108760000101010101010100000000000000000101 +:1087700000000101010101010101010101010101EB +:1087800001010101010101010101010101010102D8 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010102020201020201010194 +:1087D0000101020201020200010000000101010189 +:1087E0000101010101000002020202020202020272 +:1087F000020201020201000201010202020202025F +:10880000020202020202020201010102020202024B +:10881000020202020202020201020102020202023A +:108820000202020202020202010101010101010130 +:108830000101010101020202010101010101010125 +:108840000101020101020201010101010101010115 +:108850000101010101010101010101010101010108 +:1088600001010101010101010000000000010001FE +:1088700000000101010101010101010101010101EA +:1088800001010101010101020101010202020102D3 +:1088900002010202020202010101010101010101C2 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C000010101010101010202020202020202028F +:1088D0000201020202020200010001010101010184 +:1088E0000101010101000002020202020202020271 +:1088F000020201020201000201020202020202025D +:108900000202020202020202010202020202020248 +:108910000202020202020202020202020202020237 +:10892000020202020202020202010101010101012E +:108930000101010101020202020101010102010122 +:108940000101020201020201010101020201010210 +:108950000201020202020202010101010101010100 +:1089600001010101010201010000000001010001FB +:1089700001010101010101010101010101010101E7 +:1089800001010101010101020202020202020202CE +:1089900002020202020202010101010101010101C0 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C000010101010102010202020202020202028D +:1089D0000202020202020200010001010101010182 +:1089E0000101010101000002020202020202020270 +:1089F000020201020202000202020202020202025A +:108A00000202020202020202020202020202020246 +:108A10000202020202020202020202020202020236 +:108A2000020202020202020202010101010102022B +:108A3000020101010102020202020102020201021C +:108A40000201020202020202010201020202020209 +:108A500002020202020202020101010202010102FB +:108A600001010202010202010000010101010101F4 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101020202020202020202CD +:108A900002020202020202010101010101010101BF +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101020101010202010202A1 +:108AC0000201020201020202020202020202020288 +:108AD0000202020202020200000101010101010181 +:108AE000010101010100000202020202020202026F +:108AF0000202010202020002020202020202020259 +:108B00000202020202020202020202020202020245 +:108B10000202020202020202020202020202020235 +:108B20000202020202020202020101010202020228 +:108B30000202020102020202020202020202020216 +:108B40000201020202020202020202020202020206 +:108B500002020202020202020202020202020202F5 +:108B600002010202020202010001010101010101F0 +:108B700001010101010101010101010101010101E5 +:108B800001010101010201020202020202020202CB +:108B900002020202020202020101010101010101BD +:108BA00001010101010201010101010101010101B4 +:108BB000010101010101010202020202020202029C +:108BC0000202020202020202020202020202020285 +:108BD0000202020202020200000101010100000083 +:108BE0000000000001010002020202020202020271 +:108BF0000202010202020002020202020202020258 +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020001010101010101ED +:108C700001010101010101020202010101010101E1 +:108C800001010201010202020202020202020202C8 +:108C900002020202020202020201010201010101BA +:108CA00001010201010202020101010101010101B0 +:108CB000010101010102010202020202020202029A +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020200000100000000000085 +:108CE000000000000101010202020202020202026F +:108CF0000202020202020002020202020202020256 +:108D00000202020202020202020202020202020243 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020101010101010101EB +:108D700001010101010201020202010202020102DB +:108D800002010202020202020202020202020202C4 +:108D900002020202020202020202020202020102B4 +:108DA00001010202010202020201010101010101AD +:108DB0000101020101020202020202020202020297 +:108DC0000202020202020202020202020202020283 +:108DD0000202020202020200000000000000000085 +:108DE0000000000000010102020101020202020271 +:108DF0000202020202020002020202020202020255 +:108E00000202020202020202020202020202020242 +:108E10000202020202020202020202020202020232 +:108E20000202020202020202020202020202020222 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020101010101010101EA +:108E700001010201010202020202020202020202D6 +:108E800002020202020202020202020202020202C2 +:108E900002020202020202020202020202020202B2 +:108EA00001020202020202020202020202020102A4 +:108EB0000101020202020202020202020202020294 +:108EC0000202020202020202020202020202020282 +:108ED0000202020202020200000000000000000084 +:108EE0000000000000010102020101020202020270 +:108EF0000202020202020002020202020202020254 +:108F00000202020202020202020202020202020241 +:108F10000202020202020202020202020202020231 +:108F20000202020202020202020202020202020221 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020102E2 +:108F700001010202020202020202020202020202D3 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020202020202020202A1 +:108FB0000202020202020202020202020202020291 +:108FC0000202020202020202020202020202020281 +:108FD0000202020202020200000000000000000083 +:108FE0000000000000010102010101010101010175 +:108FF0000101020201020002020202020202020256 +:109000000202020202020202020202020202020240 +:109010000202020202020202020202020202020230 +:109020000202020202020202020202020202020220 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020202020202020202020202A0 +:1090B0000202020202020202020202020202020290 +:1090C0000202020202020202020202020202020280 +:1090D0000202020202020200000000000000000082 +:1090E0000000000000010101010101010101010175 +:1090F0000101020201020002020202020202020255 +:10910000020202020202020202020202020202023F +:10911000020202020202020202020202020202022F +:10912000020202020202020202020202020202021F +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D0000202020202020200000000000000000081 +:1091E0000000000000010101010101010101010174 +:1091F0000101020201020002020202020202020254 +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D0000202020202020200000000000000000080 +:1092E0000000000000010101010000010101010175 +:1092F0000101020201020002020202020202020253 +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202029D +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020000000000000000007F +:1093E0000000000000000101010000010101010175 +:1093F0000101020101020002020202020202020253 +:10940000020202020202020202020202020202023C +:10941000020202020202020202020202020202022C +:10942000020202020202020202020202020202021C +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020202AC +:1094A000020202020202020202020202020202029C +:1094B000020202020202020202020202020202028C +:1094C000020202020202020202020202020202027C +:1094D0000202020202020202020202020200000072 +:1094E000000000000000000100000000000000007B +:1094F0000000010100020002020202020202020256 +:10950000020202020202020202020202020202023B +:10951000020202020202020202020202020202022B +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020202AB +:1095A000020202020202020202020202020202029B +:1095B000020202020202020202020202020202028B +:1095C000020202020202020202020202020202027B +:1095D000020202020202020202020202020202026B +:1095E000020202020202000000000000000000006F +:1095F0000000010100010100000000000000000067 +:109600000000000000000002020202020202020248 +:10961000020202020202020202020202020202022A +:109620000202020202020201010101010101010123 +:109630000101010101010102020202020202020211 +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202020202029A +:1096B000020202020202020202020202020202028A +:1096C000020202020202020202020202020202027A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020000000000000000006C +:1096F0000000010100010100000000000000000066 +:109700000000000000000002020202020202020247 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020201010101010101010112 +:109740000101010101010102020202020202020200 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A0000202020202020202020202020202020299 +:1097B0000202020202020202020202020202020289 +:1097C0000202020202020202020202020202020279 +:1097D0000202020202020202020202020202020269 +:1097E000020202020202020000000000000000006B +:1097F000000001010001010101010101010101015C +:109800000101010101010100000000000000000051 +:109810000000000000000002020202020202020236 +:10982000020202020202020000000000000000002A +:109830000000000000000002020202020202020216 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020202020298 +:1098B0000202020202020202020202020202020288 +:1098C0000202020202020202020202020202020278 +:1098D0000202020202020202020202020202020268 +:1098E000020202020202020000000000000000006A +:1098F000000001000001010101010101010101015C +:109900000101010101010100000000000000000050 +:109910000000000000000000000000000000000047 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000002020202020202020205 +:1099500002020202020202000000000000000000F9 +:1099600000000000000000010101010101010101EE +:1099700001010101010101020202020202020202CE +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B0000202020202020202020202020202020287 +:1099C0000202020202020201010101010101010180 +:1099D000010101010101010202020202020202026E +:1099E0000202020202020200000000000000000069 +:1099F000000000000001010101010101010101015C +:109A00000101010101010101010101010101010146 +:109A1000010101010101010000000000000000003F +:109A2000000000000000000101010101010101012D +:109A3000010101010101010000000000000000001F +:109A40000000000000000002020202020202020204 +:109A500002020202020202000000000000000000F8 +:109A600000000000000000020202020202020202E4 +:109A700002020202020202000000000000000000D8 +:109A800000000000000000020202020202020202C4 +:109A900002020202020202010101010101010101AF +:109AA000010101010101010202020202020202029D +:109AB0000202020202020202020202020202020286 +:109AC0000202020202020202020202020202020276 +:109AD0000202020202020202020202020202020266 +:109AE000020202020202020101010101010101015F +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101000000000000000000FE +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000020202020202020202C3 +:109B900002020202020202020202020202020202A5 +:109BA00002020202020202000000000000000000A7 +:109BB0000000000000000002020202020202020293 +:109BC000020202020202020101010101010101017E +:109BD000010101010101010202020202020202026C +:109BE000020202020202020101010101010101015E +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101000000000000000000ED +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB0000000000000000002020202020202020292 +:109CC000020202020202020101010101010101017D +:109CD000010101010101010202020202020202026B +:109CE000020202020202020101010101010101015D +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101000000000000000000BC +:109DA00000000000000000000000000000000000B3 +:109DB0000000000000000002020202020202020291 +:109DC000020202020202020101010101010101017C +:109DD000010101010101010202020202020202026A +:109DE000020202020202020101010101010101015C +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED000010101010101010000000000000000007B +:109EE0000000000000000001010101010101010169 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD000010101010101010000000000000000007A +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A02000000000000000000202020202020202021E +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020202020202020202020202020202D0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020202A0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020280 +:10A0C0000202020202020202020202020202020270 +:10A0D0000202020202020200000000000000000072 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000202020202020202027D +:10A1D0000202020202020200000000000000000071 +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000202020202020202027C +:10A2D0000202020202020200000000000000000070 +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000003100000000000000003C +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000001000000000000FB +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000001010000000000F9 +:10A5600000000000000000000000010000000000EA +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A610000000000000000000000000000100000039 +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000001010000010000F7 +:10A6600000000000000000000001010000000000E8 +:10A6700000000000000000000001000000000000D9 +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000100000038 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000001010000010000F6 +:10A7600000000000000000000001010001000000E6 +:10A7700000000000000000000001010000000000D7 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000100000047 +:10A810000000000000000000000001000100010035 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000001010000010000F5 +:10A8600000000000000000000001010001010000E4 +:10A8700000000000000000000001010000000000D6 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000001000100A6 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000000000000000100010076 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000058 +:10A900000000000000000000000000000100000046 +:10A910000000000000000000000101010101010031 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000100000016 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000001010001010000F3 +:10A9600000000000000000000001010001010000E3 +:10A9700000000000000000000001010001000000D4 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000001000000B6 +:10A9A00000000000000000000001000001000100A4 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000100010075 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000100000045 +:10AA10000000000000000000000101010101010030 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000100000015 +:10AA40000000000000000000000100000000000005 +:10AA500000000000000000000001010001010000F2 +:10AA600000000000000000000001010001010000E2 +:10AA700000000000000000000001010101000000D2 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000001000001000000B4 +:10AAA00000000000000000000001010001000100A2 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000100010074 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000100000044 +:10AB1000000000000000000001010101010101002E +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000100000014 +:10AB40000000000000000000000100000100000003 +:10AB500000010001000000000001010001010000EF +:10AB600000000000000000000001010001010000E1 +:10AB700000000000000000000001010101000000D1 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000001000001000100B2 +:10ABA000000000000000000000010101010101009F +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000100000000010101010070 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000001000100010041 +:10AC1000000000010000000001010101010101002C +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000010100000012 +:10AC40000000000000000000000100000100000002 +:10AC500000010001000000000001010001010000EE +:10AC600000000000000000000001010001010000E0 +:10AC700000000000000000000001010101000000D0 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000101000101010100AE +:10ACA000000100010000000000010101010101009C +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD000000000010000010000000101010101006D +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000100000053 +:10AD0000000000000000000000010101010101003D +:10AD1000000000010000000101010101010101002A +:10AD20000000000000000000000000000000000023 +:10AD3000000000000000000000000101010001000F +:10AD40000000000000000000000100000100010000 +:10AD500000010001000000000001010001010100EC +:10AD600000010000000000000001010001010000DE +:10AD700000000000000000000001010101000000CF +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000101010101010100AC +:10ADA000000100010100000000010101010101009A +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD000000000010000010100010101010101006A +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000100000052 +:10AE0000000000000000000000010101010101003C +:10AE10000001010100000001010101010101010027 +:10AE20000000000000000000000000000000000022 +:10AE3000000000000000000200010101010101000A +:10AE400000000000000000000001000101010100FD +:10AE500000010001000000000101010001010100EA +:10AE600000010000000102000201010001010000D8 +:10AE700000000000000000000001010101000000CE +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000101010101010100AB +:10AEA0000101010101000000000101010101010097 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000181 +:10AED0000000010100000101000101010101010068 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000010100000050 +:10AF0000000000000000000001010101010101003A +:10AF10000001010101000001010101010101010025 +:10AF20000000000000000000000000000100000020 +:10AF3000000000000000000100010101010101000A +:10AF400000010001000000000001010101010100F9 +:10AF500000010001000000000101010001010100E9 +:10AF600000010000000102000101010001010000D8 +:10AF700000010000000000000001010101000000CC +:10AF800000000000000000000000000000000000C1 +:10AF900000010001000000000101010101010100A8 +:10AFA0000101010101000000000101010101010096 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000180 +:10AFD0000000010101010101010101010101010064 +:10AFE0000000000000000000000000000000000061 +:10AFF000000000000000000000000001010000004F +:10B000000000000100000000010101010101010038 +:10B010000001010101000001010101010101010024 +:10B02000000000000000000000000000010000001F +:10B030000000000000000001000101010101010009 +:10B0400000010001000000000001010101010100F8 +:10B0500000010001010000000101010101010100E6 +:10B0600000010000000102000101010101010000D6 +:10B0700000010000000000000101010101000000CA +:10B0800000000000000000000000000000000000C0 +:10B0900000010001000000010101010101010101A5 +:10B0A0000101010101000000000101010101010095 +:10B0B0000000000000000000000000000000000090 +:10B0C000000000000000000000000000000000017F +:10B0D0000101010101010101010101010101010061 +:10B0E0000000000000000000000000000000000060 +:10B0F000000000000000000000000001010000004E +:10B100000000000100000000010101010101010037 +:10B110000001010101000001010101010101010023 +:10B12000000000000000000000000000010000001E +:10B130000000000100000001000101010101010007 +:10B1400000010101000000000001010101010100F6 +:10B1500001010101010000000101010101010100E3 +:10B1600000010000000102000101010101010000D5 +:10B1700000010001000000000101010101000000C8 +:10B1800000000000000000000000000000000000BF +:10B1900001010101000000010101010101010101A2 +:10B1A0000101010101010001000101010101010092 +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000017E +:10B1D0000101010101010101010101010101010060 +:10B1E000000000000000020000000000000000005D +:10B1F000000000000000000000000001010000004D +:10B200000001010100000000010101010101010133 +:10B210000101010101000001010101010101010021 +:10B22000000000000000000000000000010000001D +:10B230000000000101000001000101010101010005 +:10B2400000010101010000000001010101010100F4 +:10B2500001010101010001020101010101010100DF +:10B2600000010000010101020101010101010000D2 +:10B2700000010001010000000101010101000000C6 +:10B2800000000000000000000000000001000000BD +:10B29000010101010101010101010101010101019E +:10B2A0000101010101010001000101010101010091 +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000017D +:10B2D000010101010101010101010101010101005F +:10B2E000000000000000020000000000000000005C +:10B2F000000000000000000000000001010000004C +:10B300000001010100000000010101010101010132 +:10B310000101010101000001010101010101010020 +:10B32000000000000000000000000000010000001C +:10B330000001000101000001000101010101010003 +:10B3400001010101010000000001010101010100F2 +:10B3500001010101010001020101010101010100DE +:10B3600000010001010101010101010101010000D1 +:10B3700000010101010000000101010101000000C4 +:10B3800000000000000000000000000001000001BB +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010100010101010101008F +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000017C +:10B3D000010101010101010101010101010101005E +:10B3E0000000000000020200000000000100000058 +:10B3F000000000000000000000000001010000004B +:10B400000001010100000000010101010101010131 +:10B41000010101010100000101010101010101001F +:10B420000000000000020200000000000100000017 +:10B430000001000101020001000101010101010000 +:10B4400001010101010000000001010101010100F1 +:10B4500001010101010101010101010101010100DD +:10B4600000010001010101010101010101010000D0 +:10B4700000010101010202000101010101000000BF +:10B4800000000000000000000000000001000101B9 +:10B49000010101010101010101010101010101019C +:10B4A000010101010101010100010101010101008E +:10B4B000000000000000000000000000010000008B +:10B4C000000000000000000000000000000000017B +:10B4D000010101010101010101010101010101005D +:10B4E0000000000000020200000100000100000056 +:10B4F000000000000000000000000001010000004A +:10B500000001010100000000010101010101010130 +:10B51000010101010100000101010101010101001E +:10B520000000000000020200000000000100010114 +:10B530000001000101010001000101010101010000 +:10B5400001010101010000000001010101010100F0 +:10B5500001010101010101010102020101010100DA +:10B5600000010001010101010101010101010000CF +:10B5700000010101010202000101010101000000BE +:10B5800000000000000000000001000101010101B5 +:10B59000010101010101010101010101010101019B +:10B5A000010101010101010100010101010101008D +:10B5B000000000000000000000000000010000008A +:10B5C000000000000000000000000000000000017A +:10B5D000010101010101010101010101010101005C +:10B5E000000102000002020200010100010000014E +:10B5F0000000000000000000000000010100000148 +:10B60000010101010000000001010101010101012E +:10B61000010101010100000101010101010101001D +:10B62000000000000002020202000000010001010F +:10B6300000010001010102010101010101010100FC +:10B6400001010101010000000001010101010100EF +:10B6500001010101010102010102020101020100D7 +:10B6600000010001010101010101020101010000CD +:10B6700000010101010101010101010101000000BE +:10B6800000010000000000000001010101010101B2 +:10B69000010101010101010101010101010101019A +:10B6A000010101010101010100010101010101008C +:10B6B0000000000000000000000000000100010088 +:10B6C0000001000100000000000000000100010175 +:10B6D000010101010101010101010101010101005B +:10B6E000000102000002010200010101010100014C +:10B6F0000000000000000000000000010100000147 +:10B70000010101010000000001010101010101012D +:10B71000010101010100000101010201020101001A +:10B72000000000000002020202000000010001010E +:10B7300001010101010101010101010101010101F9 +:10B7400001010101010000000001010101010100EE +:10B7500001020102010102010102020101020100D4 +:10B7600001010001010201010102020101010100C8 +:10B7700001010101010101010102020101000100B9 +:10B7800000010000000000000001010101010101B1 +:10B790000101010101010101010101010101010199 +:10B7A000010101010101010100010101010101008B +:10B7B0000000000000000000000100010101010084 +:10B7C0000001000100000000000000000100010174 +:10B7D000010101010101010101010101010101005A +:10B7E000000101000001010100010101010100024D +:10B7F0000000000000000000000000010100000146 +:10B80000010101010000000001010101020101012B +:10B810000101020201000002020202020202020011 +:10B82000000000000201010201000001010001010D +:10B8300001010101010101010101010102010101F7 +:10B8400001010101010000000101010101010100EC +:10B8500001020102010202010102020102020100D1 +:10B8600001010001010201010102020102020100C5 +:10B8700001010101010101010102020101000100B8 +:10B8800000010001000000000001010101010101AF +:10B890000101010101010101010101010101010198 +:10B8A000010101010101010100010101010101008A +:10B8B000000100010000000000010101010101017F +:10B8C0000101010100000000000000000100010171 +:10B8D0000101010101010201010101010101010058 +:10B8E000000101010001010101010101010100024A +:10B8F0000000000000000000000000020100000144 +:10B900000101010100000000010102010201010228 +:10B91000010202020200000202020202020202000E +:10B92000000100000201010201000001010001010B +:10B9300001010101010101020101020202010101F3 +:10B9400001010101010000000101010101010100EB +:10B9500002020202020202010202020102020100CC +:10B9600001020001010201010102020102020100C3 +:10B9700001010101010101010102020202000100B5 +:10B9800000010001000000000001010101010101AE +:10B990000101010101010101010101010101010296 +:10B9A0000202020202010101000202010201020080 +:10B9B000000100010000000000010101010101017E +:10B9C000010101010001010000000000010001026D +:10B9D0000101010101010201010101010101010057 +:10B9E0000101010100010101010101010101000248 +:10B9F000000101000000000000010002020000013F +:10BA00000101020200000000020202020202020220 +:10BA1000020202020200000202020202020202000C +:10BA2000000100000101010101000001010101020A +:10BA300001010102020201020102020202020201EC +:10BA400001010101010000000102010101010100E9 +:10BA500002020202020202010202020102020200CA +:10BA600001020001010202020102020102020100C0 +:10BA700001020101010101010102020202000100B3 +:10BA800001010101000000000001010101010101AB +:10BA90000101010101010101010101010101010295 +:10BAA000020202020202010100020202020202007C +:10BAB000010100010000000000010101010101017C +:10BAC000010101010001010000000100010001026B +:10BAD0000101020201020202010101010201020050 +:10BAE0000100000100010101010101010101000249 +:10BAF000010101000000000101010002020000023A +:10BB0000010202020000010002020202020202021D +:10BB1000020202020200000202020202020202010A +:10BB20000101000001010101010001010101010207 +:10BB300001020102020202020102020202020201E9 +:10BB400001020202010000000102010102010100E4 +:10BB500002020202020202010202020202020200C8 +:10BB600001020001020202020202020102020100BD +:10BB700001020202020101010202020202000100AE +:10BB800001010101000000000101010101010101A9 +:10BB90000101010101010101020201010201010291 +:10BBA0000202020202020202000202020202020079 +:10BBB000010100010000000000010101010101017B +:10BBC0000101010101010101000101010101010265 +:10BBD000020102020202020201010202020202004A +:10BBE000010000000100000001010101010100024B +:10BBF0000101020000000001010101020200000237 +:10BC0000020202020000010002020202020202021B +:10BC10000202020202000002020202020202020109 +:10BC20000101000001010101010101010201010204 +:10BC300002020202020202020102020202020201E6 +:10BC400002020202020000000102020202020200DD +:10BC500002020202020202020202020202020200C6 +:10BC600001020002020202020202020202020100BA +:10BC700001020202020202020202020202010101A8 +:10BC800001010101000000000101010101010102A7 +:10BC90000202020201020202020202020202020285 +:10BCA0000202020202020202000202020202020177 +:10BCB0000101000100000000000101010101010279 +:10BCC0000101010101010101000101010101010264 +:10BCD0000202020202020202020202020202020046 +:10BCE000000000000000000000000001000101024F +:10BCF0000101020101000202020101020200000230 +:10BD00000202020201000100020202020202020219 +:10BD10000202020202000002020202020202020108 +:10BD200001010101010202010101010102010102FF +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020000000102020202020200DC +:10BD500002020202020202020202020202020201C4 +:10BD600002020002020202020202020202020101B7 +:10BD700002020202020202020202020202010101A6 +:10BD800001010101010000000101010101010102A5 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202000202020202020176 +:10BDB0000101000100000000000101010101010278 +:10BDC000020202020102020101010101010101025C +:10BDD0000202020202020202020202020202020045 +:10BDE0000000000000000000000000000000010250 +:10BDF000020102010200020202010102020100022C +:10BE00000202020201000200020202020202020217 +:10BE10000202020202000002020202020202020206 +:10BE200001010101010202010101010102010102FE +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020000000102020202020200DB +:10BE500002020202020202020202020202020201C3 +:10BE600002020002020202020202020202020101B6 +:10BE700002020202020202020202020202010101A5 +:10BE800001010101010000000101010101010102A4 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202000202020202020175 +:10BEB0000101010100000000000101010101010276 +:10BEC000020202020102020101010101010101025B +:10BED0000202020202020202020202020202020044 +:10BEE000000000000000000000000000000001024F +:10BEF000020202010200020202010102020100022A +:10BF00000202020201000201020202020202020215 +:10BF10000202020202010102020202020202020203 +:10BF200002020201020202010101010102010202F8 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020000000102020202020202D8 +:10BF500002020202020202020202020202020202C1 +:10BF600002020102020202020202020202020102B3 +:10BF700002020202020202020202020202010101A4 +:10BF8000010201010102020101010101020101029C +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202000202020202020174 +:10BFB0000101010100000000010101010101010274 +:10BFC0000202020202020202010101010201020256 +:10BFD0000202020202020202020202020202020043 +:10BFE000000000000000000000000000000001024E +:10BFF0000202020202020202020101020201000226 +:10C000000202020202000201020202020202020213 +:10C010000202020202020202020202020202020200 +:10C0200002020201020202010201010202010202F5 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020100010202020202020202D4 +:10C0500002020202020202020202020202020202C0 +:10C0600002020102020202020202020202020202B1 +:10C0700002020202020202020202020202010202A1 +:10C080000202020201010101010202020202020295 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202000202020202020272 +:10C0B000020201020000000001010101020101026F +:10C0C0000202020202020202010102010201020254 +:10C0D0000202020202020202020202020202020042 +:10C0E000000000000000000000000000000001024D +:10C0F0000202020202020202020202020201000223 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020201020202020202F0 +:10C1300002020202020202020202020202020202DF +:10C1400002020202020100010202020202020202D3 +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C1700002020202020202020202020202010202A0 +:10C180000202020201010101010202020202020294 +:10C19000020202020202020202020202020202027F +:10C1A0000202020202020202010202020202020270 +:10C1B0000202010201000000010202020202020268 +:10C1C000020202020202020202020202020202024F +:10C1D0000202020202020202020202020202020041 +:10C1E000000000000000000000000000000001014D +:10C1F0000202020202020202010202020201000223 +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020201010202020202020202D0 +:10C2500002020202020201020202020202020202BF +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C280000202020202010101020202020202020291 +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020201020202020202026F +:10C2B0000202020201000000010202020202020266 +:10C2C000020202020202020202020202020202024E +:10C2D0000202020202020202020202020202020040 +:10C2E000000000000000000000000000000001014C +:10C2F0000202020202020202010202020202000221 +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020201020202020202020202BE +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020201020202020202026E +:10C3B0000202020201010101010202020202020262 +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202003F +:10C3E000000000000000000000000000000001014B +:10C3F0000202010201020101010202010202000225 +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020101020202020202020202BE +:10C4600002020202020201010202020202020202AE +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020102020202020202025D +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202003E +:10C4E000000000000000000000000000000000014B +:10C4F0000202010201020101010202010202000224 +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020101020202020202020202ED +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020102020202020202020202BC +:10C5600002020202020201010202020202020202AD +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202003D +:10C5E000000000000000000000000000000000004B +:10C5F0000202010201020101000202010202000224 +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020101020202020202020202EC +:10C6300002020202020101020202020202020202DC +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020101010202020202020202AD +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202003C +:10C6E0000202000000000000000202000200000040 +:10C6F0000102010101010101000202010102000227 +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020102010101020202020202020202ED +:10C7300002020202020101020202020202020202DB +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020102020202020202020202AA +:10C77000020202020201010102020202020202029C +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020202020202020202020202020249 +:10C7D0000202020202020202020202020202020239 +:10C7E0000202000000000000000202020202020039 +:10C7F000010100010001000000020100010200022D +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020102010202020202020202020201EB +:10C8300001010101010202010101010101010102E5 +:10C8400002020202020202020202020202020201C9 +:10C8500001010101010101010101010101010101C8 +:10C8600001010101010202020101010101010102B4 +:10C87000020202020201010102020202020202029B +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020202020202020202020202020248 +:10C8D0000202020202020202020202020202020238 +:10C8E000020202020002020202020202020202002C +:10C8F0000101000100010000000101000101000030 +:10C900000000000000000000000000000000000126 +:10C910000101010101010101010101010101010107 +:10C9200001010201020202010101010101010102F2 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020201C8 +:10C9500001010101010101010101010101010102C6 +:10C9600002020202020202020202020202020201A8 +:10C9700001010101010202020101010101010102A3 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020158 +:10C9C0000101010101010101010101010101010256 +:10C9D0000202020202020202020202020202020237 +:10C9E0000202020202020202020202020202020029 +:10C9F000010100010001000000010100010101002E +:10CA00000000000000000000000000000000000224 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020200E8 +:10CA300000000000000000000000000000000001F5 +:10CA400001010101010101010101010101010101D6 +:10CA500001010101010101010101010101010101C6 +:10CA600001010101010101010101010101010102B5 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020028 +:10CAF0000001000000000000000101000001010130 +:10CB00000101010101010101010101010101010016 +:10CB10000000000000000000000000000000000114 +:10CB200001010101010101010101010101010100F6 +:10CB300000000000000000000000000000000002F3 +:10CB400002020202020202020202020202020201C6 +:10CB500001010101010101010101010101010101C5 +:10CB600001010101010101010101010101010101B5 +:10CB700001010101010101010101010101010100A6 +:10CB800000000000000000000000000000000002A3 +:10CB90000202020202020202020202020202020176 +:10CBA0000101010101010101010101010101010274 +:10CBB0000202020202020202020202020202020057 +:10CBC0000000000000000000000000000000000263 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020027 +:10CBF0000000000000000000000100000001010131 +:10CC00000101010101010101010101010101010015 +:10CC10000000000000000000000000000000000113 +:10CC200001010101010101010101010101010101F4 +:10CC300001010101010101010101010101010100E5 +:10CC400000000000000000000000000000000001E3 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010100A5 +:10CC800000000000000000000000000000000002A2 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020066 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000252 +:10CCE0000202020202020202020202020202020026 +:10CCF0000000000000000000000000000000010132 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010100A4 +:10CD800000000000000000000000000000000002A1 +:10CD90000202020202020202020202020202020174 +:10CDA0000101010101010101010101010101010074 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000251 +:10CDE0000202020202020202020202020202020124 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010100A3 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000191 +:10CEA0000101010101010101010101010101010073 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000250 +:10CEE0000202020202020202020202020202020123 +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400001010101010101010101010101010101D1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700001010101010101010101010101010101A1 +:10CF80000101010101010101010101010101010191 +:10CF90000101010101010101010101010101010181 +:10CFA0000101010101010101010101010101010072 +:10CFB0000000000000000000000000000000000170 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010042 +:10CFE0000000000000000000000000000000000140 +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010101010101010101010110 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010101010101010101010101010101C0 +:10D0600001010101010101010101010101010101B0 +:10D0700001010101010101010101010101010101A0 +:10D080000101010101010101010101010101010190 +:10D090000101010101010101010101010101010180 +:10D0A0000101010101010101010101010101010170 +:10D0B0000101010101010101010101010101010160 +:10D0C0000101010101010101010101010101010150 +:10D0D0000101010101010101010101010101010041 +:10D0E000000000000000000000000000000000013F +:10D0F0000101010101010101010101010101010120 +:10D10000010101010101010101010101010101010F +:10D1100001010101010101010101010101010101FF +:10D1200001010101010101010101010101010101EF +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D0000101010101010101010101010101010040 +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000020C +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D0000202020202020202020202020202020030 +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000002DB +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202008F +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000028B +:10D3A000020202020202020202020202020202005F +:10D3B000000000000000000000000000000000026B +:10D3C000020202020202020202020202020202023D +:10D3D000020202020202020202020202020202002F +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000310B +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000100010101E7 +:10D5400001000000000000000000000000000000DA +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000010101010101E4 +:10D6400001010000000000010000000000000000D7 +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000010000000000000000000008 +:10D7200000000000010000000000000000000000F8 +:10D7300000000000000000000000010101010101E3 +:10D7400001010100000000010000000000000000D5 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D810000000000001010000000000000000000006 +:10D8200000000001010101000000000000000000F4 +:10D8300000000000010000000000010101010101E1 +:10D8400001010100000000010000000000000000D4 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000001000000000000000000000027 +:10D900000000000000000000000000000000000017 +:10D910000000000101010100000000000000000003 +:10D9200000000001010101000000000000000000F3 +:10D9300000000001010101000001010101010101DC +:10D9400001010100000000010000000000000000D3 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000010000000000000000A6 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000101000000000000000000000025 +:10DA00000000000000000000000000000000000016 +:10DA10000000000101010100000000000000000002 +:10DA200000000101010101000000000000000000F1 +:10DA300000000001010101010101010101010101D9 +:10DA400001010100000000010000000000000000D2 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000010000000000000000000000B5 +:10DA700000000000000000010000000000000000A5 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000101000000000000000000000024 +:10DB00000000000000000000000000000000000015 +:10DB100000000101010101000000000000000001FF +:10DB200000010101010101000000000000000000EF +:10DB300000000101010101010101010101010101D7 +:10DB400001010100000000010000000000000000D1 +:10DB500000000000000000000000000000000000C5 +:10DB600000000001010101000000000000000000B1 +:10DB700000000000000000010000000000000000A4 +:10DB80000000000000010000000000000000000094 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000010000000000000000000064 +:10DBC0000000000000010100000000000000000053 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000101000000000000000000000023 +:10DC00000000000000000000000000000000000014 +:10DC100000010101010101000000000000000001FD +:10DC200000010101010101000000000000000001ED +:10DC300000010101010101010101010101010101D5 +:10DC400001010100000000010000000000000000D0 +:10DC500000000000000000000000000000000000C4 +:10DC600000000001010101000000000000000000B0 +:10DC700000000000000000010000000000000000A3 +:10DC80000000000000010000000000000000000093 +:10DC90000000000000010000000000000000000083 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000001010000000000000000000062 +:10DCC0000000000001010100000000000000000051 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000101000000000000000000000022 +:10DD00000000000000000000000000000000000013 +:10DD100000010101010101000000000101010001F9 +:10DD200001010101010101000000000000000001EB +:10DD300000010101010101010101010101010101D4 +:10DD400001010100000000010000000000000000CF +:10DD500000000000000000000000000000000000C3 +:10DD600000000001010101000000000000000000AF +:10DD700000020000000000010000000000000000A0 +:10DD80000000000000010000000000000000000092 +:10DD90000000000001010000000000000000000081 +:10DDA0000000000000000000000000000000000073 +:10DDB000000000010101010000000000000000005F +:10DDC000000000010101010000000000000000004F +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000101000000000000000000000021 +:10DE0000000000000000000000000001010000010F +:10DE100001010101010101010000000101010001F6 +:10DE200001010101010101000000000101010001E7 +:10DE300001010101010101010101010101010101D2 +:10DE400001010100000000010000000000000000CE +:10DE500000000000000100000000000100000000C0 +:10DE600000010001010101000000000000000000AD +:10DE7000000200000000000100000000000000009F +:10DE80000000000001010000000000000000000090 +:10DE9000000000010101000000000000000000007F +:10DEA0000000000000000000000000000000000072 +:10DEB000000000010101010000000001000000005D +:10DEC000000000010101010000000000000000004E +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000101000000000000000000000020 +:10DF0000000000000000000000000001010000010E +:10DF100001010101010101010000000101010101F4 +:10DF200001010101010101000000000101010001E6 +:10DF300001010101010101010101010101010101D1 +:10DF400001010100000100010000000000000000CC +:10DF500000000000010100000000000100000000BE +:10DF600000010101010101000000000000000000AB +:10DF7000020200000000000100000000000000009C +:10DF8000000000000101000000000000000000008F +:10DF9000000000010101000000000000000000007E +:10DFA000000000000001010000000000000000006F +:10DFB000000000010101010000000001000000005C +:10DFC000000000010101010000000000000000004D +:10DFD000000000000001010000000000000000003F +:10DFE0000000000000000100000000000000000030 +:10DFF000000000010100000000000000000000001F +:10E00000000000000000000000000001010100010C +:10E0100001010101010101010100010101010101F1 +:10E0200001010101010101000000000101010101E4 +:10E0300001010101010101010101010101010101D0 +:10E0400001010100010100010000000000000000CA +:10E0500000000001010101000000000101000001B9 +:10E0600000010101010101000000000000000000AA +:10E07000020100000000000100000000000000009C +:10E08000000000000101000000000000000000008E +:10E09000000000010101010000000000000000007C +:10E0A000000000000101010000000000000000006D +:10E0B000000000010101010000000001000000005B +:10E0C000000100010101010000000000000000004B +:10E0D000000000000101010000000000000000003D +:10E0E000000000000000010000000000000000002F +:10E0F000000000010100000000000000000000001E +:10E10000000000000000000001000001010100010A +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101000100010101010101E1 +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010000000000000000C7 +:10E1500000000001010101000100000101000001B7 +:10E1600000010101010101000000000002020000A5 +:10E17000020100000000000100000000000000009B +:10E180000000000001010000000000000002000289 +:10E190000200000101010100000000000000000079 +:10E1A000000000010101010000000000000000006B +:10E1B000000000010101010000000001000000005A +:10E1C0000001010101010100000000000000000049 +:10E1D000000000010101010000000000000000003B +:10E1E000000000000001010000000000000000002D +:10E1F000000000010100000000000000000000001D +:10E200000000000000000000010000010101000109 +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101000101010101010101DF +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010000000000000000C6 +:10E2500000000001010101000100000101010001B5 +:10E2600001010101010101000000000002020000A3 +:10E27000010100000001000100000000000000009A +:10E280000000000001010000000000000002000288 +:10E290000200000101010100000000010000000077 +:10E2A0000001000101010100000000000000000069 +:10E2B0000000000101010100000000010101000156 +:10E2C0000101010101010100000000000000000047 +:10E2D000000000010101010000000000000000003A +:10E2E000000000000101010000000000000000002B +:10E2F000000000010100000000000000000000001C +:10E300000000000000000001010001010101000106 +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010201CC +:10E3400001010101010101010000000100000000C4 +:10E3500000000001010101000100010101010001B3 +:10E36000010101010101010000020002010102029C +:10E370000101000000010001000000000000000099 +:10E380000000000101010100000000000001000187 +:10E390000101000101010100000000010000000076 +:10E3A0000001010101010100000000000000000067 +:10E3B0000000000101010100010001010101000153 +:10E3C0000101010101010100000000000000000046 +:10E3D0000000000101010100000000000000000039 +:10E3E0000000000101010100000000000000000029 +:10E3F000000000010100000000000000000000001B +:10E400000000000000000001010001010101000105 +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101010101010101DC +:10E4300001010101010101010101020201020202C7 +:10E4400002010101010101020000000100000000C1 +:10E4500000000001010101000101010101010001B1 +:10E460000101010101010101000102020101020299 +:10E470000101020000010002000000000002000291 +:10E480000200000101010100000000000001000184 +:10E490000101000101010100000000010100000173 +:10E4A0000101010101010100000000000000000065 +:10E4B000000100010101010001010101010101014F +:10E4C0000101010101010100000000010100000043 +:10E4D0000000000101010100000000010100000036 +:10E4E0000000000101010100000000000000000028 +:10E4F000000000010100000000000000000000001A +:10E500000000000000000001010001010101000104 +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010101DB +:10E5300001010101010101020102020202020202C3 +:10E5400002010101010101020000000100000000C0 +:10E5500000000001010101010101010101010001AF +:10E56000010101010101010100010101010102029A +:10E570000101010001010002000000000002000290 +:10E580000200010101010100000000000101000181 +:10E590000101000101010100010000010100000171 +:10E5A0000101010101010100010000000000000063 +:10E5B000000100010101010101010101010101014D +:10E5C0000101010101010100000000010100000042 +:10E5D0000000010101010100000000010100000034 +:10E5E0000000000101010100010000000000000026 +:10E5F000000000000001000000000000000000001A +:10E600000000000000010001010001010101000102 +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101020202020202020202C1 +:10E6400002020201010101020100000100000000BC +:10E6500000000101010101010101010101010101AC +:10E66000010101010101010100010101010101019B +:10E670000101010001010002000000000001000191 +:10E680000101010101010100000000000101000180 +:10E69000010100010101010001000001010100016F +:10E6A0000101010101010100010000000000000062 +:10E6B000000100010101010101010101010101014C +:10E6C0000101010101010100000000010101000040 +:10E6D0000001010101010100000000010101010030 +:10E6E0000001000101010100010000000000000024 +:10E6F0000000000000010000000000000000000019 +:10E700000000000100010001010001010101000100 +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010101010101010101D9 +:10E7300001010101010101020202020202020202C0 +:10E7400002020201010101020100000100000000BB +:10E7500000000101010101010101010101010101AB +:10E76000010101010101010100010101010101019A +:10E77000010101000101000200000000000102018E +:10E78000010101010101010000000000010100017F +:10E79000010100010101010101000101010100016C +:10E7A0000101010101010100010001000000000060 +:10E7B000000101010101010101010101010101014A +:10E7C000010101010101010001000001010100003E +:10E7D000000101010101010001000001010101002E +:10E7E0000001010101010100010000010000000021 +:10E7F0000000000000010000000000000000000018 +:10E8000000000001000100010100010101010101FE +:10E8100001010202020201010101010101010101E4 +:10E8200001010101010101010101010101010101D8 +:10E8300001010101010101020202020202020202BF +:10E8400002020201010101020100000100000000BA +:10E8500000000101010101010101010101010101AA +:10E860000101010101010101000101010101010199 +:10E870000101010101010102000100010101020188 +:10E88000010101010101010000000000010100017E +:10E890000101000101010101010101010101010169 +:10E8A000010101010101010001000100000100005E +:10E8B0000001010101010101010101010101010149 +:10E8C000010101010101010001010001010100013B +:10E8D000000101010101010001010001010101012B +:10E8E000010101010101010001000101000000001E +:10E8F0000000000000010000000000000000000017 +:10E9000000000001000100010100010202010102FA +:10E9100002020202020202020101010101010102DE +:10E9200001010202020101010101010101010101D4 +:10E9300001010101010101020202020202020202BE +:10E9400002020201010101020100000101000000B8 +:10E9500000000101010101010101010101010101A9 +:10E960000101010101010101000101010101010198 +:10E970000101010101010102000101010101010187 +:10E98000010101010101010000000000010100017D +:10E990000101000101010101010101010101010168 +:10E9A000010101010101010101000100000100005C +:10E9B0000001010101010101010101010101010148 +:10E9C0000101010101010101010101010101000138 +:10E9D0000001010101010101010101010101010128 +:10E9E0000101010101010100000101010001020119 +:10E9F0000000000000010000000200000001000013 +:10EA000000010001000100020200010202020102F5 +:10EA100002020202020202020101010202020202D9 +:10EA200002020202020202010101010101010102CE +:10EA300001010202020101020202020202020202BA +:10EA400002020201010101020100000101000000B7 +:10EA500000000101010101010101010101010101A8 +:10EA60000101010101010102000201010101010195 +:10EA70000101010101010102000101010101010186 +:10EA80000101010101020100010000000101010179 +:10EA90000101020202020101010101010101010162 +:10EAA0000101010101010101010101010101000058 +:10EAB0000001010101010101010101010101010147 +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010100000101010001010119 +:10EAF0000000010000010000000200000001000011 +:10EB000000010101000100020200020202020102F2 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202010101010202020202C9 +:10EB300002020202020202020202020202020202B5 +:10EB400002020201010101020100000101010000B5 +:10EB500000000101010101010101010201010101A6 +:10EB6000010101020201010200020201020201018F +:10EB70000201010101010102010101010101010183 +:10EB80000101010102020100010000000101010177 +:10EB90000101010202020101010101010101010162 +:10EBA0000101010101010101010101010101000057 +:10EBB0000001010202020101010101020101010142 +:10EBC0000101010101010101010101010101010135 +:10EBD0000101010101010101010101010101010125 +:10EBE0000101010101010100000101010101010117 +:10EBF000000101000001010000020000000202000B +:10EC000000010101010100020200020202020102F0 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020201020100000101010000B1 +:10EC500000000101010101010201010202010102A2 +:10EC60000102020202020202000202020202010189 +:10EC70000201020101010102010201010101010180 +:10EC80000101020102020100010000000202010272 +:10EC9000020201020202020101010101010101015E +:10ECA0000101010101010101010101010101000056 +:10ECB0000001010202020201010101020101010140 +:10ECC0000101010202020201010101010101010130 +:10ECD0000101010101010101010101010101010124 +:10ECE0000101010101010100000101010101010116 +:10ECF0000001010000010100000202000002020008 +:10ED000000010102010100020200020202020202ED +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020100000201010000AE +:10ED5000000001020202010202020202020201029A +:10ED60000202020202020202000202020202020285 +:10ED70000202020101010102010202020202010279 +:10ED8000020202020202010001000001020202026C +:10ED9000020201020202020101010101010101015D +:10EDA0000101010101010101020101010101000054 +:10EDB0000001010202020202020202020202020237 +:10EDC000020202020202020101010101010101012C +:10EDD0000101010101010101010101010101010123 +:10EDE0000101010101010100000000000101010118 +:10EDF0000101010000010100000202000202020202 +:10EE000002020202010100020200020202020202E8 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020200000201010000AC +:10EE50000000010202020202020202020202020297 +:10EE60000202020202020202000202020202020284 +:10EE70000202020101020102010202020202020276 +:10EE80000202020202020200020001010202020268 +:10EE9000020201020202020101010101010101015C +:10EEA0000101010101010102020102010101000051 +:10EEB0000002010202020202020202020202020235 +:10EEC0000202020202020201010101020201010129 +:10EED000010101020202020101010102020102011B +:10EEE0000101010101010200000000000100000019 +:10EEF00001010100000101020202020102020202FC +:10EF000002020202010100020200020202020202E7 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020202020200000201010000AB +:10EF50000000020202020202020202020202020295 +:10EF60000202020202020202000202020202020283 +:10EF70000202020102020102020202020202020273 +:10EF80000202020202020200020001010202020267 +:10EF9000020201020202020101010102010101015A +:10EFA000010101010101010202020201010200004E +:10EFB0000002020202020202020202020202020233 +:10EFC0000202020202020202020201020202010124 +:10EFD0000101020202020202020201020202020115 +:10EFE0000101010202020200000000000000000016 +:10EFF00001010000000101020202020102020202FC +:10F0000002020202010200020200020202020202E5 +:10F0100002020202020202020202020202020202D0 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020202020202020202020202B0 +:10F0400002020202020202020200010202010000A8 +:10F050000000020202020202020202020202020294 +:10F060000202020202020202010202020202020281 +:10F070000202020202020102020202020202020271 +:10F080000202020202020202020002020202020262 +:10F090000202020202020202020101020201010254 +:10F0A0000202020202020202020202020202000143 +:10F0B0000102020202020202020202020202020231 +:10F0C0000202020202020202020202020202020220 +:10F0D0000102020202020202020202020202020211 +:10F0E0000202020202020200000000000000000012 +:10F0F00000000000000101020201020202020202FD +:10F1000002020202010200020200020202020202E4 +:10F1100002020202020202020202020202020202CF +:10F1200002020202020202020202020202020202BF +:10F1300002020202020202020202020202020202AF +:10F1400002020202020202020201010202020001A4 +:10F150000000020202020202020202020202020293 +:10F160000202020202020202010202020202020280 +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A0000202020202020202020202020202000142 +:10F1B0000102020202020202020202020202020230 +:10F1C000020202020202020202020202020202021F +:10F1D000020202020202020202020202020202020F +:10F1E0000202020202020200000000000000000011 +:10F1F00000000000000101020201020202020202FC +:10F2000002020202010200020202020202020202E1 +:10F2100002020202020202020202020202020202CE +:10F2200002020202020202020202020202020202BE +:10F2300002020202020202020202020202020202AE +:10F2400002020202020202020201010202020001A3 +:10F250000000020202020202020202020202020292 +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A0000202020202020202020202020202000141 +:10F2B000010202020202020202020202020202022F +:10F2C000020202020202020202020202020202021E +:10F2D000020202020202020202020202020202020E +:10F2E0000202020202020200000000000000000010 +:10F2F0000000000000010102020101020101010100 +:10F3000001020202020200020202020202020202E0 +:10F3100002020202020202020202020202020202CD +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020202020202AD +:10F3400002020202020202020202020202020001A0 +:10F350000001020202020202020202020202020290 +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020200023F +:10F3B000020202020202020202020202020202022D +:10F3C000020202020202020202020202020202021D +:10F3D000020202020202020202020202020202020D +:10F3E000020202020202020000000000000000000F +:10F3F00000000002020201020201010201010101FA +:10F4000001020202020200020202020202020202DF +:10F4100002020202020202020202020202020202CC +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020200029E +:10F45000000102020202020202020202020202028F +:10F46000020202020202020202020202020202027C +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C000020202020202020202020202020202021C +:10F4D000020202020202020202020202020202020C +:10F4E000020202020202020000000000000000000E +:10F4F00000000002020201020100010201010101FB +:10F5000001010101020200020202020202020202E1 +:10F5100002020202020202020202020202020202CB +:10F5200002020202020202020202020202020202BB +:10F5300002020202020202020202020202020202AB +:10F54000020202020202020202020202020202029B +:10F55000010102020202020202020202020202028D +:10F560000202020202020202020101010101020181 +:10F57000010201020202020202020202020202026D +:10F58000020202020202020202020202020202025B +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B000020202020202020202020202020202022B +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020202020202020202020B +:10F5E000020202020202020000000000000000000D +:10F5F00000000002020201020100010201010101FA +:10F6000001010101020200020202020202020202E0 +:10F6100002020202020202020202020202020202CA +:10F6200002020202020202020202020202020202BA +:10F6300002020202020202020202020202020202AA +:10F64000020202020202020202020202020202029A +:10F65000020202020202020202020202020202028A +:10F660000202020202020202020101010101020180 +:10F67000010201020202020202020202020202026C +:10F68000020202020202020202020202020202025A +:10F69000020202020202020202020202020202024A +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020202020202020202020A +:10F6E0000202020202020200000202020000000006 +:10F6F00000000002020202010100000200000000FE +:10F7000000010101020200020202020202020202E0 +:10F7100002020202020202020202020202020202C9 +:10F7200002020202020202020202020202020202B9 +:10F7300002020202020202020202020202020202A9 +:10F740000202020202020202020202020202020299 +:10F750000202020202020202020202020202020289 +:10F76000020202020202020202010101010102017F +:10F77000010201020202020202020202020202026B +:10F780000202020202020202020202020202020259 +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020202000202020200020202FD +:10F7F00000000002020202010100000100000000FE +:10F8000000010101020200020202020202020202DF +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020202020202020202020202B8 +:10F8300002020202020202020202020202020202A8 +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F86000020202020202020102020202020201027A +:10F87000020202020202020202010101010102016E +:10F88000010101020202020000000000000000006D +:10F890000000000000000002020202020202020256 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202000202020202020202FA +:10F8F00000000202020202010000000100000000FC +:10F9000000000000020200020202020202020202E1 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202010101010102010101AF +:10F94000010202010101010202020202020202029C +:10F950000202020202020202020202020202020287 +:10F960000202020202020202010202020202020278 +:10F97000020102010101010002020202020202026E +:10F980000202020202020200000000000000000069 +:10F990000000000000000002020202020202020255 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202010000000100000000F7 +:10FA000000000000020100010101010101010101EA +:10FA100001010101010101020202020202020202CD +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020201020202A7 +:10FA40000201010202020201020202020202020299 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020201020202020202010278 +:10FA70000202020202020201000000000000010076 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000002020202020202020254 +:10FAA000020202020202020101010101010101013F +:10FAB000010101010101010202020202020202022D +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202000000000100000000F7 +:10FB000000000000010101020202020202020202E0 +:10FB100002020202020202000000000000000000D7 +:10FB200000000000000000020202020202020202C3 +:10FB300002020202020202000000000002000000B5 +:10FB400000020200000000020101010101010101A7 +:10FB5000010101010101010202020202020202028C +:10FB6000020202020202020101010101010101017E +:10FB70000101010101010101010101010101010175 +:10FB8000010101010101010000000000000001006D +:10FB90000000000000000002020202020202020253 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202000000000000000000F7 +:10FC000000000000010101010101010101010101E8 +:10FC100001010101010101000000000000000000DD +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000010101010101010101BB +:10FC400001010100000000000202020202020202A1 +:10FC50000202020202020200000000000000000096 +:10FC6000000000000000000101010101010101018B +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC9000010101010101010202020202020202024B +:10FCA0000202020202020200000000000000000046 +:10FCB0000000000000000002020202020202020232 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202000000000000000000F6 +:10FD000000000000010101010101010101010101E7 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101000000000000000000CC +:10FD300000000000000000010101010101010101BA +:10FD400001010101010101010000000000000000AB +:10FD500000000000000000000000000000000000A3 +:10FD6000000000000000000101010101010101018A +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD9000010101010101010202020202020202024A +:10FDA0000202020202020200000000000000000045 +:10FDB0000000000000000002020202020202020231 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202000000000000000000F5 +:10FE000000000000010001010101010101010101E7 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010102020202020202020249 +:10FEA000020202020202020101010101010101013B +:10FEB0000101010101010101010101010101010132 +:10FEC000010101010101010000000000000000002B +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000002020202020202020200 +:10FEF00002020202020202010101010101010101EB +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010102020202020202020248 +:10FFA000020202020202020101010101010101013A +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD000010101010101010000000000000000001A +:10FFE00000000000000000020202020202020202FF +:10FFF00002020202020202010101010101010101EA +:0200000290006C +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E00001010101010101020202020202020202F7 +:1000F00002020202020202010101010101010101E9 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E0000101010101010100000000000000000008 +:1001F00000000000000000010101010101010101F6 +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E0000101010101010100000000000000000007 +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000020202020202020202AB +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202020202020202020D +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202000000000000000000FF +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000202020202020202027A +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020000000000000000004E +:1004A000000000000000000202020202020202023A +:1004B000020202020202020202020202020202021C +:1004C000020202020202020202020202020202020C +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202000000000000000000FE +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000300000000000000000CB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:100650000000000000000000000001000001010097 +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:100680000000000000000000000000000001010068 +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C0000000000000000000000000000000010029 +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000010001000101010094 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000001010000000001010065 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000010028 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000010008 +:1007F00000000000000001000000000000000000F8 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000001000000000000000000A7 +:100850000000000000010100010001010101010090 +:100860000000000000000000000001000001010085 +:100870000000000000000000000000000000000078 +:100880000000000000010101010000000001010062 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000010047 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000100000000000001010025 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000010007 +:1008F00000000000000001010000000000000000F6 +:1009000001000000000000000001000000000000E5 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000001000000000000000000A6 +:10095000000100000001010101010101010101008C +:100960000000000000000001010001000101010081 +:100970000000000000000000000000000000000077 +:10098000000000010001010101010000010101005E +:100990000000000000000000000000000000000057 +:1009A0000000000000000000010100000000010044 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000100010100000101010021 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000100000000000001010004 +:1009F00000000000000001010000000000010001F3 +:100A000001000000010000000001010100000000E1 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000001000000000000010100A3 +:100A5000000100000101010101010101010101008A +:100A6000000000000001010101000100010101007E +:100A70000000000000000000000000000000000076 +:100A8000000001010001010101010101010101005A +:100A90000000000000000000000000000000000056 +:100AA0000000000000000100010100000001010041 +:100AB0000000000000000000000000000000000036 +:100AC000000000000000010001010101010101001E +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000100010000000001010002 +:100AF00000000000000001010100000000010001F1 +:100B000001000000010000000001010100000000E0 +:100B100000000000000000000000000000010100D3 +:100B200000000000000000000000000000010100C3 +:100B300000000000000000000000000000000000B5 +:100B400000000000000001010100000000010100A0 +:100B50000101000101010101010101010101010087 +:100B6000000100000001010101010100010101007B +:100B70000000000000000000000000000000000075 +:100B80000001010100010101010101010101010058 +:100B90000000000000000000000000000000000055 +:100BA000000000000000010101010000010101003E +:100BB0000000000000000000000000000000000035 +:100BC000000000000000010101010101010101001C +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000100010000000001010001 +:100BF00000000000000001010100000000010001F0 +:100C000001000000010100000001010100000000DE +:100C100000000000000000000100000001010100D0 +:100C200000000000000000000100000001010100C0 +:100C300000000000000000000000000000000000B4 +:100C4000000000000000010101000000000101009F +:100C50000101010101010101010101010101010085 +:100C60000001010000010101010101010101010078 +:100C70000000000000000000000000000000000074 +:100C80000001010101010101010101010101010056 +:100C90000000000000000000000000000000000054 +:100CA000000000000001010101010101010101003A +:100CB0000000000000000000000000000001010032 +:100CC000000000000001010101010101010101001A +:100CD0000000000000000000000000000000000014 +:100CE00000000000000001000101000001010100FE +:100CF00000000000000001010101000001010001ED +:100D000001010001010100000001010101000000DA +:100D100000000000000001000100010001010100CD +:100D200000000000000001000100010101010100BC +:100D300000000000000000000000000000000000B3 +:100D4000000000010000010101000000010101009C +:100D50000101010101010101010101010101010084 +:100D60000001010100010101010101010101010076 +:100D70000000000000000000000000000000000073 +:100D80000101010101010101010101010101010054 +:100D90000000000000000000000000000000000053 +:100DA0000001000100010101010101010101010037 +:100DB0000000000000000000010000000001010030 +:100DC0000001000100010101010101010101010017 +:100DD0000000000000000000000000000000000013 +:100DE00000000000000001000101010101010100FB +:100DF00000000000000001010101010101010002E9 +:100E000002010101010100000001010101000000D7 +:100E100000000000000001010101010001010100CA +:100E200000000000000001010101010101010100B9 +:100E300000000000000000000000000000010100B0 +:100E40000000010100010101010000010101010197 +:100E50000101010101010101010101010101010083 +:100E60000001010101010101010101010101010074 +:100E70000000000000000000000000000000000171 +:100E80000101010101010101010101010101010053 +:100E90000000000000000100000000000000010050 +:100EA0000001010101010101010101010101010034 +:100EB000000000000000010001000000000101002E +:100EC0000001010101010101010101010101010014 +:100ED0000000000000000000000000000000000012 +:100EE00000000000000001010101010101010100F9 +:100EF00000000000000001010101010101010002E8 +:100F000002010101020100000001010101000000D5 +:100F100000000000000101010101010101010101C6 +:100F200000000000000101010101010101010100B7 +:100F300000000000000000000100000000010100AE +:100F40000001010100010101010100010101010194 +:100F50000101010101010101010101010101010082 +:100F60000101010101010101010101010101010072 +:100F7000000000000000000000000000000101016E +:100F80000101010101010101010101010101010052 +:100F9000000000000000010001000000000001004E +:100FA0000101010101010101010101010101010032 +:100FB000000000000000010101010000010101002A +:100FC0000101010101010101010101010101010012 +:100FD0000000000000000000000000000000010010 +:100FE00000000100000101010101010101010100F6 +:100FF00000000000000101010101010101010002E6 +:1010000002010101020100000001010101000000D4 +:1010100000010001000101010101010101010101C3 +:1010200000000001000101010101010101010100B5 +:1010300000000000000001000100000100010100AB +:101040000001010100010101010101010101010192 +:101050000101010101010101010101010101010081 +:101060000101010101010101010101010101010071 +:10107000000000000000000001000000000101016C +:101080000101010101010101010101010101010051 +:10109000000000000001010001000000000101014A +:1010A0000101010101010101010101010101010031 +:1010B0000000000000000101010101010101010126 +:1010C0000101010101010101010101010101010011 +:1010D000000000000000000000000000000001000F +:1010E00000000101000101010101010101010100F4 +:1010F00000010001000101010101010101010002E3 +:1011000002010101020100010001010101000000D2 +:1011100000010101000101010101010101010101C1 +:1011200000000101000101010101010101010100B3 +:1011300001000001000001000100000101010100A7 +:101140000101010100010101010101010101010190 +:101150000101010101010101010101010101010080 +:101160000101010101010101010101010101010070 +:10117000000000000000010001000000000101016A +:101180000101010101010101010101010101010050 +:101190000000000000010100010000000101010148 +:1011A0000101010101010101010101010101010030 +:1011B0000000000000000101010101010101010125 +:1011C0000101010101010101010101010101010010 +:1011D000000000000000000000000000000101000D +:1011E00000000101000101010101010101010100F3 +:1011F00000010101010101010101010101010002E0 +:1012000002020202020200010002020201000000CA +:1012100000010101000101010101010101010101C0 +:1012200000010101000101010101010101010101B0 +:1012300001000101000101000100010101010100A3 +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101006F +:101270000000000000000101010000000101010167 +:10128000010101010101010101010101010101004F +:101290000000000000010100010001010101010145 +:1012A000010101010101010101010101010101002F +:1012B0000000000001010101010101010101010122 +:1012C000010101010101010101010101010101000F +:1012D000000000000000000001000000000101000B +:1012E00000010101000101010101010101010100F1 +:1012F00001010101010101010101010101010002DE +:1013000002020202020200010002020201000000C9 +:1013100000010101010101010101010101010101BE +:1013200000010101010101010101010101010101AE +:10133000010101010001010101010101010101009F +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101006E +:101370000000000000000101010001010101010164 +:10138000010101010101010101010101010101004E +:101390000001000000010101010101010101010141 +:1013A000010101010101010101010101010101002E +:1013B0000000000101010101010101010101010120 +:1013C000010101010101010101010101010101000E +:1013D0000000000000000100010000000001010009 +:1013E00000010101010101010101010101010100EF +:1013F00001010101010100000101010101010002DF +:1014000002020202020200010102020201000000C7 +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101006D +:101470000000000000000101010101010101010162 +:10148000010101010101010101010101010101004D +:101490000001000000010101010101010101010140 +:1014A000010101010101010101010101010101002D +:1014B000000000010101010101010101010101011F +:1014C000010101010101010101010101010101000D +:1014D0000000000000000101010100000101010005 +:1014E00001010101010101010101010101010100ED +:1014F00001010101010100000101010101000002DF +:1015000002020202020200010102020202000001C4 +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101018B +:10155000010101010101010101010101010101017B +:10156000010101010101010101010101010101006C +:101570000000000000010101010101010101010160 +:10158000010101010101010101010101010101004C +:10159000000100010001010101010101010101013E +:1015A000010101010101010101010101010101002C +:1015B000000100010101010101010101010101011D +:1015C000010101010101010101010101010101000C +:1015D0000000000000000101010101010101010101 +:1015E00001010101010101010101010101010100EC +:1015F00001010101010100000000000000000002E3 +:1016000002020202020200010102020202000001C3 +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010101010101010101019A +:10164000010101010101010101010101010101018A +:10165000010101010101010101010101010101017A +:10166000010101010101010101010101010101006B +:10167000000100010001010101010101010101015D +:10168000010101010101010101010101010101004B +:10169000000101010001010101010101010101013C +:1016A000010101010101010101010101010101002B +:1016B000000100010101010101010101010101011C +:1016C000010101010101010101010101010101000B +:1016D0000000000000000101010101010101010100 +:1016E00001010101010101010101010101010100EB +:1016F00000000000000000000000000000000002E8 +:1017000002020202020201020102020202000001C0 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010102010101010178 +:101760000101010101010101010102010101010069 +:10177000000101010001010101010101010101015B +:10178000010101010101010101010101010101004A +:10179000010101010001010101010101010101013A +:1017A000010101010101010101010101010101002A +:1017B000000100010101010101010101010101011B +:1017C000010101010101010101010101010101000A +:1017D00000000100000101010101010101010101FD +:1017E00001010101010101010101010101010100EA +:1017F00000000000000000000000000000000102E6 +:1018000002020202020201020102020202000001BF +:1018100001010101010101010101010101010102B7 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010201010101010101010187 +:101850000202010102020101010102020202010170 +:101860000102020101020102010102010202010062 +:101870000101010100010101010101010101010159 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000001010101010101010101010101010119 +:1018C0000101010101010101010101010101010009 +:1018D00000010101000101010101010101010101FA +:1018E00001010101010101010101010101010100E9 +:1018F00000000000000000000000000000000102E5 +:1019000002020202020201020102020202010001BD +:1019100001010101010101010101020102020102B3 +:1019200001010101010101010101020202020102A2 +:101930000201010101010101010101010101010196 +:101940000101020201010202010101010102010281 +:101950000202020202020202020202020202020168 +:101960000202020202020202020202020202020158 +:101970000101010101010101010101010101010157 +:101980000101020201020102010101010102010142 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010008 +:1019D00000010101000101010101010101010101F9 +:1019E00001010101010102010101010101020200E5 +:1019F00000000000000000000000000000000102E4 +:101A000002020202020201020102020202010001BC +:101A100001020202010202020202020202020202A8 +:101A20000101020201020202020202020202020299 +:101A30000201020201010101010101020102010191 +:101A40000202020201020202020101020202020279 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020157 +:101A70000101010101010101010101010101010255 +:101A80000202020202020202020202020202020137 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010201010202020202020000 +:101AD00001010101000101010101010101010101F7 +:101AE00001010201010102010202020202020200DE +:101AF00000000000000000000000000000000102E3 +:101B000002020202020201020102020202010002BA +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020201020102020202020287 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020156 +:101B70000101010101010101010101010101010254 +:101B80000202020202020202020202020202020136 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010201010101010124 +:101BB0000101010101010101010101010102010213 +:101BC00002020202020202020202020202020201F6 +:101BD00001010101000101010101010101010101F6 +:101BE00001010202010202020202020202020200DA +:101BF00000000000000000000000000000000102E2 +:101C000002020202020201020202020202010002B8 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020155 +:101C70000101010101010101010101010102010252 +:101C80000202020202020202020202020202020135 +:101C90000101010101020201010101010101010231 +:101CA0000202020202020202020202020202020115 +:101CB0000101010102010202020202020202020209 +:101CC00002020202020202020202020202020201F5 +:101CD00001010101000101010101010101010102F4 +:101CE00002020202020202020202020202020200D6 +:101CF00000000000000000000000000000000102E1 +:101D000002020202020202020202020202020002B5 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020154 +:101D7000010101010101020202010202020202024A +:101D80000202020202020202020202020202020134 +:101D90000102010101020201020102020202020229 +:101DA0000202020202020202020202020202020114 +:101DB0000101010202020202020202020202020206 +:101DC00002020202020202020202020202020201F4 +:101DD00001010101010101010101010101010102F2 +:101DE00002020202020202020202020202020200D5 +:101DF00000000000000000000000000000000101E1 +:101E000001020202010202020202020202020002B6 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020201020202020202020202020243 +:101E80000202020202020202020202020202020232 +:101E90000202020201020202020202020202020223 +:101EA0000202020202020202020202020202020212 +:101EB0000102010202020202020202020202020204 +:101EC00002020202020202020202020202020201F3 +:101ED00001010101010101010101010101010102F1 +:101EE00002020202020202020202020202020200D4 +:101EF00000000000000000000000000000000101E0 +:101F000001010101010102020202020202020002B9 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020201F2 +:101FD00001010101010101010101010101020202EE +:101FE00002020202020202020202020202020200D3 +:101FF00000000000000000000000000000000101DF +:1020000001010101010102020201010102020002BB +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020201F1 +:1020D00001010201010102020202020202020202E5 +:1020E00002020202020202020202020202020200D2 +:1020F00000000000000000000000000000000101DE +:1021000001010101010102010201010101020002BC +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020202020202020202020F +:1021B00002020202020202020202020202020202FF +:1021C00002020202020202020202020202020202EF +:1021D00002020202010202020202020202020202E0 +:1021E00002020202020202020202020202020200D1 +:1021F00000000000000002020000000000000101D9 +:1022000001010101010102010201010101020002BB +:10221000020202020202020202020202020202029E +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A000020202020202020202020202020202020E +:1022B00002020202020202020202020202020202FE +:1022C00002020202020202020202020202020202EE +:1022D00002020202010202020202020202020202DF +:1022E00002020202020202020202020202020200D0 +:1022F00000000000000002020000000000020201D5 +:1023000001010101010102010201010101010002BB +:10231000020202020202020202020202020202029D +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A000020202020202020202020202020202020D +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020202020202ED +:1023D00002020202020202020202020202020202DD +:1023E00002020202020202020202020202020200CF +:1023F00000000000000002020202020202020200CB +:1024000000010101010102010201010101010002BB +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202020202020202020202DC +:1024E00002020202020202020202020202020200CE +:1024F00002020202020202020202020202020200BE +:1025000000010101010101010101010101010002BC +:10251000020202020202020202020202020202029B +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C00002020202020202020202020202020202EB +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020200CD +:1025F00002020202020202020202020202020200BD +:1026000000000000000001000100000000010002C5 +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202020202020202020202DA +:1026E00002020202020202020202020202020200CC +:1026F00002020202020202020202020202020200BC +:1027000000000000000001000100000000000002C5 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020200BB +:1028000000000000000001000100000000000002C4 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020000BC +:1029000000000000000000000000000000000001C6 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010098 +:102930000000000000000000000000000000000295 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020000BB +:102A000000000000000000000000000000000102C3 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020187 +:102A30000101010101010101010101010101010285 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020058 +:102A60000000000000000000000000000000000264 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020200B8 +:102B000000000000000000000000000000000101C3 +:102B100001010101010101010101010101010100A6 +:102B200000000000000000000000000000000001A4 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010076 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000263 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020106 +:102BB0000101010101010101010101010101010204 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020201B6 +:102C000001000000000000000000000000000101C1 +:102C100001010101010101010101010101010100A5 +:102C200000000000000000000000000000000001A3 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000101010101010101010101010101010065 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000252 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020201D5 +:102CE00001010101010101010101010101010102D3 +:102CF00002020202020202020202020202020201B5 +:102D000001000000000000000000000000000101C0 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010173 +:102D50000101010101010101010101010101010163 +:102D60000101010101010101010101010101010054 +:102D70000000000000000000000000000000000251 +:102D80000202020202020202020202020202020025 +:102D90000000000000000000000000000000000231 +:102DA0000202020202020202020202020202020104 +:102DB0000101010101010101010101010101010103 +:102DC00001010101010101010101010101010102F2 +:102DD00002020202020202020202020202020201D4 +:102DE00001010101010101010101010101010102D2 +:102DF00002020202020202020202020202020201B4 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010033 +:102E90000000000000000000000000000000000230 +:102EA0000202020202020202020202020202020103 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010102D1 +:102EF00002020202020202020202020202020201B3 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010100D2 +:102FF00000000000000000000000000000000001D0 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010100D1 +:1030F00000000000000000000000000000000001CF +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:10317000010101010101010101010101010101013F +:10318000010101010101010101010101010101012F +:10319000010101010101010101010101010101011F +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010100D0 +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000029C +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020200C0 +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000021B +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020200BF +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000002EA +:1034E00002020202020202020202020202020200BE +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000000000000000000000EB +:1035E00000000000000000000000000000000000DB +:1035F000000000000000000000000000000000309B +:1036000036090000000000386B090000000000408F +:103610009A09000000000048C8090000000000509E +:10362000F409000000000058200A000000000060BB +:10363000440A000000000068620A000000000070F8 +:10364000800A0000000000789E0A00000000008050 +:10365000BC0A000000000088DA0A000000000090A8 +:10366000F80A000000000098160B0000000000356A +:103670000000000000000000000000000001000148 +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000101000000000000F8 +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000010100000000000001010144 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000101010000000000F6 +:1037D00000000000000001000000000000000000E8 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000100000000000000000000000000000097 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000001000057 +:10387000000000000001010200010000010101013F +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000101010000000000F5 +:1038D00000000000000001000000000000000000E7 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000010000000000010000A5 +:103920000100000000000000000000000000000096 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000010001000055 +:103970000000000000010102000201010202010139 +:103980000100000000000000000000000000000036 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000201010100000000F2 +:1039D00000000000000001000000000000000000E6 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000010000000000010000A4 +:103A20000100000000000000000000000000000095 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000010101000152 +:103A70000000000000010102020202020202020232 +:103A80000100000000000000000000000000000035 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000202010100000000F0 +:103AD00000000000000001000000000000000000E5 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000010101000001010000A0 +:103B20000100000000000000000000000000000094 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B6000000000000000000000000101010101014F +:103B7000010001010101010202020202020202022D +:103B80000100010101000000000000000000000031 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000202020100000000EE +:103BD00000000000000001000000000000000000E4 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C1000000000000000000101010101010101009C +:103C20000100010000000000000000000000000092 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C6000000000000000000000010101010101014D +:103C7000010001010101010202020202020202022C +:103C8000020001010100000000000000000000002F +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000020202020101010000E9 +:103CD00000000000000001000000000000000000E3 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D1000000000000000000101010101010101019A +:103D20000100010000000000000000000000000091 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D6000000000000000000000010101010101014C +:103D7000010001010101010202020202020202022B +:103D8000020001010100000000000000000000002E +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000020202020201010000E7 +:103DD00000000000000001000000000000000000E2 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E10000000000000000002010101010101010198 +:103E2000010001000000010000000000000000008F +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E6000000000000000000001010101010101014A +:103E70000101010101010102020202020202020229 +:103E8000020202010100000000000000000000002A +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000020202020202010000E5 +:103ED00000000000000001000000000000000000E1 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F10000000000000000002020101010101010196 +:103F2000010001000000010000000000000000008E +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000010101010101010149 +:103F70000101010101010102020202020202020228 +:103F80000202020201000000000000000000000028 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000020202020202010100E3 +:103FD00000000000000001000000000000000000E0 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:104010000000000000000002020201010101010194 +:10402000010001000000010000000000000000008D +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000010101010101010148 +:104070000101010101010102020202020202020227 +:104080000202020202000000000000000000000026 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000020202020202020101E0 +:1040D00000000000000001000000000000000000DF +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:104110000000000000000002020202010101010192 +:10412000010001000000010000000000000000008C +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:104160000000000000000000010101010101010147 +:104170000101010101010102020202020202020226 +:104180000202020202010000000000000000000024 +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000020202020202020101DF +:1041D00000000100000001000000000000000000DD +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000202020202020201018E +:10422000010001010000010000000000000000008A +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:104260000000000000000000010101010101010146 +:104270000101010101010102020202020202020225 +:104280000202020202010000000000000000000023 +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000020202020202020201DD +:1042D00000000100000002000000000000000000DB +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000202020202020201018D +:104320000200010100000100000000000000000088 +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:104360000000000000000000010101010101010145 +:104370000101010101010102020202020202020224 +:104380000202020202010000000000000000000022 +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000020202020202020201DC +:1043D00001000100010002000000000000000000D8 +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000202020202020202018B +:104420000200010100010100000000000000000086 +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:104460000000000000000000020202020101010140 +:104470000101010101010102020202020202020223 +:104480000202020202010000000000000000000021 +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000020202020202020202DA +:1044D00001000100010002000000000000000000D7 +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000202020202020202018A +:104520000200010100010100000000000000000085 +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000002020202010101013F +:104570000101010101010102020202020202020222 +:104580000202020202010000000000000000000020 +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000020202020202020202D9 +:1045D00002000201010002000000000000000000D3 +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:104610000000000000000002020202020202020288 +:104620000200010100010100000000000000000084 +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000002020202020201013C +:104670000101010101010102020202020202020221 +:10468000020202020201000000000000000000001F +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000020202020202020202D8 +:1046D00002020201010002000000000000000000D0 +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000002020202020202020287 +:104720000200020100010100000000000000000082 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:10476000000000000000000002020202020201013B +:104770000101010101010102020202020202020220 +:10478000020202020201000000000000000000001E +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000020202020202020202D7 +:1047D00002020201020002000000000000000000CE +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000002020202020202020286 +:104820000200020101010100000000000000000080 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000020202020202020139 +:10487000010101010101010202020202020202021F +:10488000020202020202000000000000000000001C +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000020202020202020202D6 +:1048D00002020202020002000000000000000000CC +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000002020202020202020285 +:10492000020002010101010000000000000000007F +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000020202020202020237 +:10497000010101010101010202020202020202021E +:10498000020202020202000000000000000000001B +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000020202020202020202D5 +:1049D00002020202020002000000000000000000CB +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000002020202020202020284 +:104A2000020002010101010000000000000000007E +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000020202020202020236 +:104A7000020101010101010202020202020202021C +:104A8000020102020202000000000000000000001B +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000020202020202020202D4 +:104AD00002020202020002000000000000000000CA +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000002020202020202020283 +:104B2000020102020101020000000000000000007A +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000002020202020202020233 +:104B7000020101010101010202020202020202021B +:104B8000020101010102010000000000000000001C +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000020202020202020202D3 +:104BD00002020202020102000000000000000000C8 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000002020202020202020282 +:104C20000201020201010200000000000000000079 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000002020202020202020232 +:104C7000020102010101010202020202020202011A +:104C8000010101010102010000000000000000001C +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000020202020202020202D2 +:104CD00002020202020102000000000000000000C7 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000002020202020202020281 +:104D20000201020201010200000000000000000078 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000002020202020202020231 +:104D7000020202020101010202020202010101011A +:104D8000010101010102010000000000000000001B +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000020202020202020202D1 +:104DD00002020202020102000000000000000000C6 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000002020202020202020280 +:104E20000202020201010200000000000000000076 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000002020202020202020230 +:104E70000202020202020102020202020101010117 +:104E8000010101010101010000000000000000001B +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000020202020202020202D0 +:104ED00002020202020102000000000000000000C5 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F1000000000000000000202020202020202027F +:104F20000202020202010200000000000000000074 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F6000000000000000000202020202020202022F +:104F70000202020202020202020202010101010116 +:104F8000010101010101010000000000000000001A +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000020202020202020202CF +:104FD00002020202020101000000000000000000C5 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:10501000000000000000000202020202020202027E +:105020000202020202020200000000000000000072 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:10506000000000000000000202020202020202022E +:105070000202020202020201020101010101010118 +:105080000101010101010100000000000000000019 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000020202020202020202CE +:1050D00002020202020201000000000000000000C3 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000202020202020202027D +:105120000202020202020200000000000000000071 +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000202020202020202022D +:105170000202020202020201010101010101010118 +:105180000101010101010100000000000000000018 +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000020202020202020202CD +:1051D00002010202010201000000000000000000C4 +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000202020202020202027C +:105220000202020202020200000000000000000070 +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000202020202020202022C +:105270000202020202020201010101010101010117 +:105280000101010101010100000000000000000017 +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000020202020202020202CC +:1052D00002010101010201000000000000000000C5 +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000202020202020202027B +:10532000020202020202020000000000000000006F +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000202020202020202022B +:105370000202020202020201010101010101010116 +:105380000101010101010100000000000000000016 +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000020202020201020202CC +:1053D00001010101010201000000000000000000C5 +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000202020202020202027A +:10542000020202020202020000000000000000006E +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000202020202020202022A +:105470000202020202020201010101010101010115 +:105480000101010101010100000000000000000015 +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000020202020201010101CE +:1054D00001010101010101000000000000000000C5 +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:105510000000000000000002020202020202020279 +:10552000020202020202020000000000000000006D +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:105560000000000000000002020202020202020229 +:105570000202020202020201010101010101010114 +:105580000101010101010100000000000000000014 +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000010101010101010101D2 +:1055D00001010101010101000000000000000000C4 +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:105610000000000000000002020202020202020278 +:10562000020202020202020000000000000000006C +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:105660000000000000000002020202020202020228 +:105670000202020202020201010101010101010113 +:105680000101010101010100000000000000000013 +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000010101010101010101D1 +:1056D00001010101010101000000000000000000C3 +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000000000000000000000000000000000099 +:105710000000000000000002020202020202020277 +:10572000020202020202020000000000000000006B +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000002020202020202020227 +:105770000202020202020201010101010101010112 +:105780000101010101010100000000000000000012 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000010101010101010101D0 +:1057D00001010101010101000000000000000000C2 +:1057E00000000000000000000000000000000000B9 +:1057F00000000000000000000000000000000000A9 +:105800000000000000000000000000000000000098 +:105810000000000000000002020202020202020276 +:10582000020202020202020000000000000000006A +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000002020202020202020226 +:105870000202020202020201010101010101010111 +:105880000101010101010100000000000000000011 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000010101010101010101CF +:1058D00001010101010101000000000000000000C1 +:1058E00000000000000000000000000000000000B8 +:1058F00000000000000000000000000000000000A8 +:105900000000000000000000000000000000000097 +:105910000000000000000002020202020202020275 +:105920000202020202020200000000000000000069 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000002020202020202020225 +:105970000202020202020201010101010101010110 +:105980000101010101010100000000000000000010 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000010101010101010101CE +:1059D00001010101010101000000000000000000C0 +:1059E00000000000000000000000000000000000B7 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000002020202020202020274 +:105A20000202020202020100000000000000000069 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000002020202020202020224 +:105A7000020202020202020101010101010101010F +:105A8000010101010101010000000000000000000F +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000010101010101010101CD +:105AD00001010101010101000000000000000000BF +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000002020202020202020273 +:105B20000202020202020100000000000000000068 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000002020202020202020223 +:105B7000020202020202020101010101010101010E +:105B8000010101010101010000000000000000000E +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000010101010101010101CC +:105BD00001010101010101000000000000000000BE +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000002020202020202020272 +:105C2000010101010102010000000000000000006C +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000002020202020202020222 +:105C7000020202020202020101010101010101010D +:105C8000010101010101010000000000000000000D +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000010101010101010101CB +:105CD00001010101010101000000000000000000BD +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000002020202020101010175 +:105D2000010101010101010000000000000000006C +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000002020202020202020221 +:105D7000020202020202020101010101010101010C +:105D8000010101010101010000000000000000000C +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000010101010101010101CA +:105DD00001010101010101000000000000000000BC +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000001010101010101010179 +:105E2000010101010101010000000000000000006B +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000002020202020202020220 +:105E7000020202020202020101010101010101010B +:105E8000010101010101010000000000000000000B +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000010101010101010101C9 +:105ED00001010101010101000000000000000000BB +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000001010101010101010178 +:105F2000010101010101010000000000000000006A +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F6000000000000000000202020202020202021F +:105F7000020202020202020101010101010101010A +:105F8000010101010101010000000000000000000A +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000010101010101010101C8 +:105FD00001010101010101000000000000000000BA +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000001010101010101010177 +:106020000101010101010100000000000000000069 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:10606000000000000000000202020202020202021E +:106070000202020202020201010101010101010109 +:106080000101010101010100000000000000000009 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000010101010101010101C7 +:1060D00001010101010101000000000000000000B9 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000000000000000000008F +:106110000000000000000001010101010101010176 +:106120000101010101010100000000000000000068 +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000202020202020202021D +:106170000202020202020201010101010101010108 +:106180000101010101010100000000000000000008 +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000010101010101010101C6 +:1061D00001010101010101000000000000000000B8 +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:106210000000000000000001010101010101010175 +:106220000101010101010100000000000000000067 +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000202020202020202021C +:106270000202020202020201010101010101010107 +:106280000101010101010100000000000000000007 +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000010101010101010101C5 +:1062D00001010101010101000000000000000000B7 +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:106310000000000000000001010101010101010174 +:106320000101010101010100000000000000000066 +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000202020202020202021B +:106370000202020202020201010101010101010106 +:106380000101010101010100000000000000000006 +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000010101010101010101C4 +:1063D00001010101010101000000000000000000B6 +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:106410000000000000000001010101010101010173 +:106420000101010101010100000000000000000065 +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000202020202020202021A +:106470000202020202020201010101010101010105 +:106480000101010101010100000000000000000005 +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000010101010101010101C3 +:1064D00001010101010101000000000000000000B5 +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:106510000000000000000001010101010101010172 +:106520000101010101010100000000000000000064 +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000000000000000000000000000000000003B +:106560000000000000000002020202020202020219 +:106570000202020202020201010101010101010104 +:106580000101010101010100000000000000000004 +:1065900000000000000000000000000000000000FB +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000010101010101010101C2 +:1065D00001010101010101000000000000000000B4 +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:10660000000000000000000000000000000000008A +:106610000000000000000001010101010101010171 +:106620000101010101010100000000000000000063 +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:106660000000000000000002020202020202020218 +:106670000202020202020201010101010101010103 +:106680000101010101010100000000000000000003 +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000010101010101010101C1 +:1066D00001010101010101000000000000000000B3 +:1066E00000000000000000000000000000000000AA +:1066F000000000000000000000000000000000009A +:106700000000000000000000000000000000000089 +:106710000000000000000001010101010101010170 +:106720000101010101010100000000000000000062 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000002020202020202020217 +:106770000202020202020201010101010101010102 +:106780000101010101010100000000000000000002 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000010101010101010101C0 +:1067D00001010101010101000000000000000000B2 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000099 +:106800000000000000000000000000000000000088 +:10681000000000000000000101010101010101016F +:106820000101010101010100000000000000000061 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000038 +:106860000000000000000000010101010101010120 +:106870000101010101010100000000000000000011 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000020202020202020202B6 +:1068D00002020202020202000000000000000000AA +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000098 +:106900000000000000000000000000000000000087 +:106910000000000000000002020202020202020265 +:106920000202020202020200000000000000000059 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000020202020202020202B5 +:1069D00002020202020202000000000000000000A9 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000097 +:106A00000000000000000000000000000000000086 +:106A10000000000000000002020202020202020264 +:106A20000202020202020200000000000000000058 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000000B6 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000096 +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000035 +:106B60000000000000000000000000000000000025 +:106B7000000000000000002F0000000000000000E6 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000010000010000000000000100B2 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000001C3 +:106CD00001010000010101010000010001000100AB +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000001000000000000000000000062 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000112 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000001C2 +:106DD00002010000010101010000010001000100A9 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000001000000000000000000000061 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E7000000000000100000000000000000001010F +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000002C0 +:106ED00002020000010101010000010001000100A7 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000001000000000000000000000060 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F7000000000000101000000000000010101020A +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000002BF +:106FD00002020000010101010100010001000100A5 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:10702000010000000100000000000001000000005D +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000001010000000000000101010209 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000002BE +:1070D00002020100010101010101010101000100A1 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000010000000100000000000001000000005C +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:107170000001010101010100000001000101010203 +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000002BD +:1071D000020202000101020201010101010001009D +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000016D +:107220000101000001000100000001010000000058 +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:107270000001010101010101010001000101010200 +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000002BC +:1072D0000202020102020202010101010100010099 +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000016C +:107320000201000001000100000001010000010055 +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:1073700001010101010101010101010101010102FC +:1073800002000000000000000000000000000000FB +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000002BB +:1073D0000202020202020202010102010100010096 +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000016B +:107420000201010001010100000101010100010050 +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:1074700001010101010101010101010101010102FB +:1074800002000000010000000000000000000000F9 +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000002BA +:1074D0000202020202020202020102010100010094 +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:107510000000000000000000000000000000000269 +:10752000020201000101010100010101010001004D +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:1075700001010101010101010101010101010102FA +:1075800002020200010000000000000001000000F3 +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000002B9 +:1075D0000202020202020202020202020200010090 +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:107610000000000000000000000000000000000268 +:10762000020201010101010100010101010001004B +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:1076700001010101010101010101010101010102F9 +:1076800002020200010000000000000001000000F2 +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000002B8 +:1076D000020202020202020202020202020002008E +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000267 +:107720000202020102010101010101010100010047 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:1077700001010101010101010101010101010102F8 +:1077800002020202020000000000000001010000ED +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000002B7 +:1077D000020202020202020202020202020002008D +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000266 +:107820000202020102010101010101010101010045 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:1078700001010101010101010101010101010102F7 +:1078800002020202020000020000000001010000EA +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000002B6 +:1078D000020202020202020202020202020102008B +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000265 +:107920000202020202010201010101020101010041 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:1079700002020101010101010101010101010102F4 +:1079800002020202020002020002000202010000E2 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000002B5 +:1079D000020202020202020202020202020102008A +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000264 +:107A20000202020202010201010101020101010040 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A700002020201010101010101010101010102F2 +:107A800002020202020002020202000202020000DE +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000002B4 +:107AD0000202020202020202020202020201020089 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000263 +:107B2000020202020202020201010202010101003C +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B700002020202010101010101010101010102F0 +:107B800002020202020202020202020202020000D9 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000002B3 +:107BD0000202020202020202020202020202020087 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000262 +:107C2000020202020202020201020202010101003A +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C700002020202020101010101010101010102EE +:107C800002020202020202020202020202020000D8 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000002B2 +:107CD0000202020202020202020202020202020086 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000261 +:107D20000202020202020202020202020101010038 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D700002020202020201010101010101010102EC +:107D800002020202020202020202020202020000D7 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000002B1 +:107DD0000202020202020202020202020202020085 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000260 +:107E20000202020202020202020202020101010037 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E700002020202020202010101010101010102EA +:107E800002020202020202020202020202020000D6 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000002B0 +:107ED0000202020202020202020202020202020084 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F1000000000000000000000000000000000025F +:107F20000202020202020202020202020201010035 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F6000000000000000000000000000000000020F +:107F700002020202020202020101010101010102E8 +:107F800002020202020202020202020202020000D5 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000002AF +:107FD0000202020202020202020202020202020083 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:10801000000000000000000000000000000000025E +:108020000202020202020202020202020201020033 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:10806000000000000000000000000000000000020E +:1080700002020202020202020201010101010102E6 +:1080800002020202020202020202020101010100D6 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000002AE +:1080D0000202020202020202020202020202020082 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000025D +:108120000202020202020202020202020202020031 +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000020D +:1081700002020202020202020202020101010102E3 +:1081800002020202020202020201010101010100D7 +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000002AD +:1081D0000202020202020202020202020202020081 +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000025C +:108220000202020202020202020202020202020030 +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000020C +:1082700002020202020202020202020202020102DF +:1082800002020202020202010101010101010100D8 +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000002AC +:1082D0000202020202020202020202020202020080 +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000025B +:10832000020202020202020202020202020202002F +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000020B +:1083700002020202020202020202020202020202DD +:1083800002020202020201010101010101010100D8 +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000002AB +:1083D000020202020202020202020202020202007F +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000025A +:10842000020202020202020202020202020202002E +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000020A +:1084700002020202020202020202020202020202DC +:1084800002020202010101010101010101010100D9 +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000002AA +:1084D000020202020202020202020202020202007E +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:108510000000000000000000000000000000000259 +:10852000020202020202020202020202020202002D +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:108560000000000000000000000000000000000209 +:1085700002020202020202020202020202020201DC +:1085800002020101010101010101010101010100DA +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000002A9 +:1085D0000202020202020202020201010101010082 +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:108610000000000000000000000000000000000258 +:10862000020202020202020202020202020202002C +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:108660000000000000000000000000000000000208 +:1086700002020202020202020202020202020201DB +:1086800001010101010101010101010101010100DB +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000002A8 +:1086D0000202020202020101010101010101010085 +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000257 +:10872000020202020202020202020202020202002B +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000207 +:1087700002020202020202020202020202020201DA +:1087800001010101010101010101010101010100DA +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000002A7 +:1087D0000202020202010101010101010101010085 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000256 +:10882000020202020202020202020202020202002A +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000206 +:1088700002020202020202020202020202020201D9 +:1088800001010101010101010101010101010100D9 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000002A6 +:1088D0000101010101010101010101010101010089 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000255 +:108920000202020202020202020202020202020029 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000205 +:1089700002020202020202020202020202020201D8 +:1089800001010101010101010101010101010100D8 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000001A6 +:1089D0000101010101010101010101010101010088 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000254 +:108A20000202020202020202020202020202020028 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000204 +:108A700002020202020202020202020202020201D7 +:108A800001010101010101010101010101010100D7 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000001A5 +:108AD0000101010101010101010101010101010087 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000253 +:108B20000202020202020202020202010202020028 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000203 +:108B700002020202020202020202020202020201D6 +:108B800001010101010101010101010101010100D6 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000001A4 +:108BD0000101010101010101010101010101010086 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000252 +:108C20000202020202020202020201010202020028 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000202 +:108C700002020202020202020202020202020201D5 +:108C800001010101010101010101010101010100D5 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000001A3 +:108CD0000101010101010101010101010101010085 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000251 +:108D2000020202020202010101010101010101002E +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000201 +:108D700002020202020202020202020202020201D4 +:108D800001010101010101010101010101010100D4 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000001A2 +:108DD0000101010101010101010101010101010084 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000250 +:108E20000101010101010101010101010101010033 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000200 +:108E700002020202020202020202020202020201D3 +:108E800001010101010101010101010101010100D3 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000001A1 +:108ED0000101010101010101010101010101010083 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000150 +:108F20000101010101010101010101010101010032 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F600000000000000000000000000000000002FF +:108F700002020202020202020202020202020201D2 +:108F800001010101010101010101010101010100D2 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000001A0 +:108FD0000101010101010101010101010101010082 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:10901000000000000000000000000000000000014F +:109020000101010101010101010101010101010031 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:1090600000000000000000000000000000000002FE +:1090700002020202020202020202020202020201D1 +:1090800001010101010101010101010101010100D1 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C000000000000000000000000000000000019F +:1090D0000101010101010101010101010101010081 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000014E +:109120000101010101010101010101010101010030 +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000002FD +:1091700002020202020202020202020202020201D0 +:1091800001010101010101010101010101010100D0 +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000019E +:1091D0000101010101010101010101010101010080 +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000014D +:10922000010101010101010101010101010101002F +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000002FC +:1092700002020202020202020202020202020201CF +:1092800001010101010101010101010101010100CF +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000019D +:1092D000010101010101010101010101010101007F +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000014C +:10932000010101010101010101010101010101002E +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000002FB +:1093700002020202020202020202020202020201CE +:1093800001010101010101010101010101010100CE +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000019C +:1093D000010101010101010101010101010101007E +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000014B +:10942000010101010101010101010101010101002D +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000002FA +:1094700002020202020202020202020202020201CD +:1094800001010101010101010101010101010100CD +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000019B +:1094D000010101010101010101010101010101007D +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000014A +:10952000010101010101010101010101010101002C +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000002F9 +:1095700002020202020202020202020202020201CC +:1095800001010101010101010101010101010100CC +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000019A +:1095D000010101010101010101010101010101007C +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:10960000000000000000000000000000000000005A +:109610000000000000000000000000000000000149 +:10962000010101010101010101010101010101002B +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000002F8 +:1096700002020202020202020202020202020201CB +:1096800001010101010101010101010101010100CB +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C0000000000000000000000000000000000199 +:1096D000010101010101010101010101010101007B +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000148 +:10972000010101010101010101010101010101002A +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000002F7 +:1097700002020202020202020202020202020201CA +:1097800001010101010101010101010101010100CA +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000198 +:1097D000010101010101010101010101010101007A +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000246 +:10982000020202020202020202020202020202001A +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700002020202020202020202020202020201C9 +:1098800001010101010101010101010101010100C9 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000000000000000000000A8 +:1098C0000000000000000000000000000000000296 +:1098D000020202020202020202020202020202006A +:1098E0000000000000000000000000000000000078 +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000000000057 +:109910000000000000000000000000000000000245 +:109920000202020202020202020202020202020019 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700001010101010101010101010101010100D8 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000000B7 +:1099B00000000000000000000000000000000000A7 +:1099C0000000000000000000000000000000000097 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0000000000000000000000000000000000067 +:109A00000000000000000000000000000000000056 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000000000000000000000000000000000F6 +:109A70000000000000000000000000000000002EB8 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000000000000000000B6 +:109AB00000000000000000000000000000000000A6 +:109AC0000000000000000000000000000000000096 +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000076 +:109AF0000000000000000000000000000000000066 +:109B00000000000000000000000000000000000055 +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000010000000034 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000010000000000000000D4 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE0000100000000000000000000000000000074 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000010000000033 +:109C30000000000000010000000000000000000023 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000010000000000000000D3 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000101000000000000000000000000000072 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D2000000000000000000000000001010100012F +:109D30000000000001010000000000000000000021 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000010100000000000000D1 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000001000000000000000082 +:109DE0000101000000000000000000000000000071 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E2000000000000000000000000001010100012E +:109E3000000000000101010000000000000000001F +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000010100010001DE +:109E800000000000010000010100000000000000CF +:109E900001000000000000000000000000000000C1 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000001000000000000000081 +:109EE0000101000000000000000000000000000070 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F2000000000000000000000000001010101012C +:109F3000000000000101010000000000000000001E +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000010100010001DD +:109F800000000000010100020100000000000000CC +:109F900001000000000000000000000000000000C0 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD000000000000000000100000001000000007F +:109FE000010100000000000000000000000000006F +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A02000000000000000000000000001010101012B +:10A03000000000000101010000000000000000001D +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000010101010101DA +:10A0800001000000010100020100000000000000CA +:10A0900001000000000000000000000000000000BF +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D000000000000000000201010101000000007A +:10A0E000010100000000010000000000000000006D +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000001010101012A +:10A13000010001000101010000000000000000001A +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000010101010101D9 +:10A1800001010001010101020100000000000000C6 +:10A1900001000000000000000000000000000000BE +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D0000000000000000002010101010100000078 +:10A1E000010100000000010000000000000000006C +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A21000000000000000000000000000000000003E +:10A220000000000000000001010000010101010127 +:10A230000100010001010100000000000000000019 +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000010101010101D8 +:10A2800001010101010101020200010000000001C1 +:10A2900001000000000000000000000000000000BD +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D0000000000000000002010101010100000077 +:10A2E000010100000000010000000000000000006B +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A320000000000000000001010100010101010125 +:10A330000100010001010100000000000000000018 +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000010101010101D7 +:10A3800001010101010101020200010000000001C0 +:10A3900001000000000000000000000000000000BC +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D0000000000000000002020102010101000073 +:10A3E0000202000000000100000000000000000068 +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A420000000000000000001010100010101010124 +:10A430000100010001010100000000000000000017 +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000010101010101D6 +:10A4800001010101010101020200010100000101BD +:10A4900002000000000000000000000000000000BA +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D0000000000000000002020202020101000070 +:10A4E0000202000000000100000000000000000067 +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A520000000000000000001010101020101010121 +:10A530000100010001010100000000000000000016 +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000010101010101D5 +:10A5800001010101010101020200010100000101BC +:10A5900002000000000000000000000000000000B9 +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000202020202020101006D +:10A5E0000202000000000100000000000000000066 +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000201010102010101011F +:10A630000100010001010100000000000000000015 +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000010101010101D4 +:10A6800001010101010101020200020100010101B9 +:10A6900002000000000000000000000000000000B8 +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000202020202020101016B +:10A6E0000202000000000100000000000000000065 +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A72000000000000000000202010102020101011C +:10A730000100010001010100000000000000000014 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000010101010101D3 +:10A7800001010101010101020200020100010102B7 +:10A7900002010001000000000000000000000000B5 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000002020202020202010169 +:10A7E0000202010000000100000000000000000063 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A82000000000000000000202010102020201011A +:10A830000101010101010100000000000000000011 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000010101010101D2 +:10A8800001010101010101020201020201010202B2 +:10A8900002010001000000000000000000000000B4 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000002020202020202020167 +:10A8E0000202010000000100000000000000000062 +:10A8F0000000000000000000000000000000000058 +:10A900000000000000000000000000000000000047 +:10A910000000000000000000000000000000000037 +:10A920000000000000000002020201020202020216 +:10A930000101010101010100000000000000000010 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000101010101D2 +:10A9800001010101010101020201020201010202B1 +:10A9900002020001000000000000000000000000B2 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000002020202020202020265 +:10A9E000020202000100020000000000000000005E +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000046 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000002020202020202020214 +:10AA3000010101010101010000000000000000000F +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000020001010101D0 +:10AA800001010101010101020201020202020202AE +:10AA900002020102000000000000000000000000AF +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000002020202020202020264 +:10AAE000020202000100020000000000000000005D +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000002020202020202020213 +:10AB3000020101010101010000000000000000000D +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000020201010101CD +:10AB800001010101010101020202020202020202AC +:10AB900002020102000000000000000000000000AE +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000002020202020202020263 +:10ABE000020202000100020000000000000000005C +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000002020202020202020212 +:10AC30000201020102020100000000000000000009 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000020200000101CE +:10AC800001010101010101020202020202020202AB +:10AC900002020202000000000000000000000000AC +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000002020202020202020262 +:10ACE000020202010100020000000000000000005A +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000002020202020202020211 +:10AD30000201020102020100000000000000000008 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000020202020000CB +:10AD800001010101010101020202020202020202AA +:10AD900002020202000100000000000000000000AA +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000002020202020202020261 +:10ADE0000202020202000200000000000000000057 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000002020202020202020210 +:10AE30000201020102020200000000000000000006 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000020202020202C6 +:10AE800000010101010101020202020202020202AA +:10AE900002020202000100000000000000000000A9 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000002020202020202020260 +:10AEE0000202020202000200000000000000000056 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF2000000000000000000202020202020202020F +:10AF30000202020102020200000000000000000004 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000001020202020202C4 +:10AF800002000101010101020202020202020202A8 +:10AF900002020202000100000000000000000000A8 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD000000000000000000202020202020202025F +:10AFE0000202020202000200000000000000000055 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B02000000000000000000202020202020202020E +:10B030000202020202020200000000000000000002 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000101020202020202C2 +:10B0800002020000000101020202020202020202A8 +:10B0900002020202010100000000000000000000A6 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D000000000000000000202020202020202025E +:10B0E0000202020202010200000000000000000053 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000000000000000000000000000000000002F +:10B12000000000000000000202020202020202020D +:10B130000202020202020200000000000000000001 +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000020001020202020202C0 +:10B1800002020202020001020202020202020202A2 +:10B1900002020202010201000000000000000000A3 +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000202020202020202025D +:10B1E0000202020202020200000000000000000051 +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B21000000000000000000000000000000000002E +:10B22000000000000000000202020202020202020C +:10B230000202020202020200000000000000000000 +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000020200020202020202BE +:10B28000020202020202010202020202020202029F +:10B2900001010201010201000000000000000000A5 +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000202020202020202025C +:10B2E0000202020202020200000000000000000050 +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B31000000000000000000000000000000000002D +:10B32000000000000000000202020202020202020B +:10B3300002020202020202000000000000000000FF +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000020202020202020202BB +:10B3800002020202020200020202020202020201A0 +:10B3900001010101010201000000000000000000A5 +:10B3A000000000000000000000000000000000009D +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000202020202020202025B +:10B3E0000200000202020200000000000000000053 +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000000002C +:10B42000000000000000000202020202020202020A +:10B4300002020202020202000000000000000000FE +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000020202020202020202BA +:10B48000020202020202020202020202020201019E +:10B4900001010101020101000000000000000000A4 +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000202020202020202005C +:10B4E0000200000202020100000000000000000053 +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000000000000000000000000000000000002B +:10B520000000000000000002020202020202020209 +:10B5300002020202020202000000000000000000FD +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000020202020202020202B9 +:10B5800002020202020202010202020201010101A0 +:10B5900001010101020101000000000000000000A3 +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D0000000000000000002020200020000000063 +:10B5E0000101010101010100000000000000000054 +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B620000000000000000002020202020202020208 +:10B6300002020202020202000000000000000000FC +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000020202020202020202B8 +:10B6800002020202020202010102010101010101A2 +:10B6900001010101010101000000000000000000A3 +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D0000000000000000002020200020000000062 +:10B6E0000101010101010100000000000000000053 +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000002020202020202020207 +:10B7300002020202020202000000000000000000FB +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000020202020202020202B7 +:10B7800002020202020202010102010101010101A1 +:10B7900001010101010101000000000000000000A2 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000020000010101010162 +:10B7E0000101010101010100000000000000000052 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000002020202020202020206 +:10B8300002020202020202000000000000000000FA +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000020202020202020202B6 +:10B8800002020202020202010101010101010101A1 +:10B8900001010101010101000000000000000000A1 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D000000000000000000101010101010101015F +:10B8E0000101010101010100000000000000000051 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000002020202020202020205 +:10B9300002020202020202000000000000000000F9 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000020202020202020202B5 +:10B9800002020202020202010101010101010101A0 +:10B9900001010101010101000000000000000000A0 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D000000000000000000101010101010101015E +:10B9E0000101010101010100000000000000000050 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000002020202020202020204 +:10BA300002020202020202000000000000000000F8 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000020202020202020202B4 +:10BA8000020202020202020101010101010101019F +:10BA9000010101010101010000000000000000009F +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD000000000000000000101010101010101015D +:10BAE000010101010101010000000000000000004F +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000002020202020202020203 +:10BB300002020202020202000000000000000000F7 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000020202020202020202B3 +:10BB8000020202020202020101010101010101019E +:10BB9000010101010101010000000000000000009E +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD000000000000000000101010101010101015C +:10BBE000010101010101010000000000000000004E +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000002020202020202020202 +:10BC300002020202020202000000000000000000F6 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000020202020202020202B2 +:10BC8000020202020202020101010101010101019D +:10BC9000010101010101010000000000000000009D +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD000000000000000000101010101010101015B +:10BCE000010101010101010000000000000000004D +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000002020202010101010106 +:10BD300001010101010101000000000000000000FC +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000020202020202020202B1 +:10BD8000020202020202020101010101010101019C +:10BD9000010101010101010000000000000000009C +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD000000000000000000101010101010101015A +:10BDE000010101010101010000000000000000004C +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000001010101010101010109 +:10BE300001010101010101000000000000000000FB +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000020202020202020202B0 +:10BE8000020202020202020101010101010101019B +:10BE9000010101010101010000000000000000009B +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000001010101010101010159 +:10BEE000010101010101010000000000000000004B +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000001010101010101010108 +:10BF300001010101010101000000000000000000FA +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000020202020202020202AF +:10BF8000020202020202020101010101010101019A +:10BF9000010101010101010000000000000000009A +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000001010101010101010158 +:10BFE000010101010101010000000000000000004A +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000001010101010101010107 +:10C0300001010101010101000000000000000000F9 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000020202020202020202AE +:10C080000202020202020201010101010101010199 +:10C090000101010101010100000000000000000099 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000001010101010101010157 +:10C0E0000101010101010100000000000000000049 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C120000000000000000001010101010101010106 +:10C1300001010101010101000000000000000000F8 +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000020202020202020202AD +:10C180000202020202020201010101010101010198 +:10C190000101010101010100000000000000000098 +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D0000000000000000001010101010101010156 +:10C1E0000101010101010100000000000000000048 +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C220000000000000000001010101010101010105 +:10C2300001010101010101000000000000000000F7 +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000020202020202020202AC +:10C280000202020202020201010101010101010197 +:10C290000101010101010100000000000000000097 +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D0000000000000000001010101010101010155 +:10C2E0000101010101010100000000000000000047 +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000000001D +:10C320000000000000000001010101010101010104 +:10C3300001010101010101000000000000000000F6 +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000020202020202020202AB +:10C380000202020202020201010101010101010196 +:10C390000101010101010100000000000000000096 +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D0000000000000000001010101010101010154 +:10C3E0000101010101010100000000000000000046 +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C420000000000000000001010101010101010103 +:10C4300001010101010101000000000000000000F5 +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000020202020202020202AA +:10C480000202020202020201010101010101010195 +:10C490000101010101010100000000000000000095 +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D0000000000000000001010101010101010153 +:10C4E0000101010101010100000000000000000045 +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C520000000000000000001010101010101010102 +:10C5300001010101010101000000000000000000F4 +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000020202020202020202A9 +:10C580000202020202020201010101010101010194 +:10C590000101010101010100000000000000000094 +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D0000000000000000002020202020202020249 +:10C5E000020202020202020000000000000000003D +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C6200000000000000000020202020202020202F8 +:10C6300002020202020202000000000000000000EC +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000020202020202020202A8 +:10C680000202020202020201010101010101010193 +:10C690000101010101010100000000000000000093 +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D0000000000000000002020202020202020248 +:10C6E000020202020202020000000000000000003C +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C7200000000000000000020202020202020202F7 +:10C7300002020202020202000000000000000000EB +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000010101010101B3 +:10C7800001010101010101000000000000000000A2 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C88000000000000000002C00000000000000007C +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000100F6 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000010000000046 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000010100000000000000000100F3 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000010000000045 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000010101000000000000000100F1 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000100000001000000000000010000000042 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000010101000000000000000100F0 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000001010000010000000000000000000091 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000153 +:10CCE0000100000001000000000000010000000041 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD10000000000000000000000000000000000013 +:10CD20000000000000000000000000000000000003 +:10CD300000000000010101000000000000000100EF +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000001A2 +:10CD90000001010000010000000000000000000090 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000152 +:10CDE000010000000101000000000001000000003F +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000010101000000000000000100EE +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000001A1 +:10CE9000000101000101000000000000000000008E +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000151 +:10CEE000010000000101000000000001010001003C +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000100 +:10CF300000000000010101000000000000010100EC +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000001A0 +:10CF9000000101000101000000000000010000008C +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000150 +:10CFE000010100000101000000000001010001003A +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D0200000000000000000000000000000000001FF +:10D0300001000000010101010101000000010100E7 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D08000000000000000000000000000000000029E +:10D090000001010101010000010100000100000088 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D000000000000000000000000000000000024E +:10D0E0000101000001010000000001010101010037 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000001FE +:10D1300001000000010101010101000000010100E6 +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000029D +:10D190000002020101010000010100000100000085 +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000024D +:10D1E0000101010001010000000001010101010035 +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000001FD +:10D2300001000000010101010101000000010100E5 +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000100000000000000000000029B +:10D290000102020101020000010100010100000081 +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000024C +:10D2E0000201010001010100000001010101010032 +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000002FB +:10D3300001000000010101010101000001010100E3 +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000100000000000000000000029A +:10D39000010202010202000001010001010000007F +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000024B +:10D3E000020101010101010000010101010101002F +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000002FA +:10D4300001010000010101010101000001010100E1 +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D480000000000001000000000000010000000298 +:10D49000010202020202000101020001020000007A +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000024A +:10D4E000020201010201010000010101010101002C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000002F9 +:10D5300001010000020201010101010001010100DD +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D580000100010001000000000000010000010294 +:10D590000102020202020101020200020201000075 +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D0000000000000000000000000000000000249 +:10D5E0000202020102020100000101020101010028 +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000002F8 +:10D6300002010100020202010101010101010100D8 +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D680000100000101000000000000010000010293 +:10D690000202020202020101020200020201000073 +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D0000000000000000000000000000000000248 +:10D6E0000202020102020100000101020101010027 +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000002F7 +:10D7300002010100020202010101010101010100D7 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000100000000000000000000010000010294 +:10D790000202020202020102020201020201000070 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000247 +:10D7E0000202020202020101000101020101010024 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D810000000000000000000000000000000000008 +:10D8200000000000000000000000000000000002F6 +:10D8300002020101020202010101010101010100D4 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000001000000000000010000010000010292 +:10D89000020202020202020202020202020200006C +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000246 +:10D8E0000202020202020201000102020201010020 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000000000000000002F5 +:10D9300002020201020202020101010101010100D1 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000010100010000010000010290 +:10D99000020202020202020202020202020200006B +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000245 +:10D9E000020202020202020101020202020101001D +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000002F4 +:10DA300002020201020202020202010101010200CD +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA8000000000000001010001000000010001028F +:10DA9000020202020202020202020202020200006A +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000244 +:10DAE000020202020202020101020202020201001B +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000002F3 +:10DB300002020202020202020202010101010200CB +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB8000000000000001010001000000010001028E +:10DB90000202020202020202020202020202000069 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000243 +:10DBE0000202020202020202010202020202020018 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000002F2 +:10DC300002020202020202020202010101020200C9 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC8000000000000000000001000000010001028F +:10DC90000202020202020202020202020202000068 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000242 +:10DCE0000202020202020202010202020202020017 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000002F1 +:10DD300002020202020202020202020102020200C6 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD8000000000000000000000000000010101028E +:10DD90000202020202020202020202010101010069 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000241 +:10DDE0000202020202020202020202020202020015 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000002F0 +:10DE300002020202020202020202020202020200C4 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000002A0 +:10DE8000000000000000000000010000010101028C +:10DE9000020202020202020202010101010101006A +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000240 +:10DEE0000202020202020202020202020202020014 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000002EF +:10DF300002020202020202020202020202020200C3 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF7000000000000000000000000000000000029F +:10DF8000000000000000000000010100000101028B +:10DF9000020202020202020201010101010101006A +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000000000000000000000000051 +:10DFD000000000000000000000000000000000023F +:10DFE0000202020202020202020202020202020013 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000002EE +:10E0300002020202020202020202020202020200C2 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E07000000000000000000000000000000000029E +:10E080000200000000000001000101000001010287 +:10E09000020202020101020101010101010101006C +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D000000000000000000000000000000000023E +:10E0E0000202020202020202020202020202020012 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000002ED +:10E1300002020202020202020202020202020200C1 +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000029D +:10E180000200000000000001000101000001000287 +:10E19000020202020101010101010101010101006C +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000023D +:10E1E0000202020202020202020202020202020011 +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000002EC +:10E2300002020202020202020202020202020200C0 +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000029C +:10E280000202020000000000000001000001000284 +:10E29000020101010101010101010101010101006E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000023C +:10E2E0000202020202020202020202020202020010 +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000002EB +:10E3300002020202020202020202020202020200BF +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000029B +:10E380000202020000000000000000000001000185 +:10E39000020101010101010101010101010101006D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000023B +:10E3E000020202020202020202020202020202000F +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000002EA +:10E4300002020202020202020202020202020200BE +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000029A +:10E480000202020202000000000000000000000181 +:10E49000010101010101010101010101010101006D +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000023A +:10E4E000020202020202020202020202020202000E +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000002E9 +:10E5300002020202020202020202020202020200BD +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E570000000000000000000000000000000000299 +:10E580000202020202000000000000000000000180 +:10E59000010101010101010101010101010101006C +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D0000000000000000000000000000000000239 +:10E5E000020202020202020202020202020202000D +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000002E8 +:10E6300002020202020202020202020202020200BC +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E670000000000000000000000000000000000298 +:10E68000020202020202000000000000000000017D +:10E69000010101010101010101010101010101006B +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D0000000000000000000000000000000000238 +:10E6E0000202020202020202020101010101020011 +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000002E7 +:10E7300002020202020202020202020202020200BB +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000297 +:10E78000020202020202020000000000000000017A +:10E79000010101010101010101010101010101006A +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000237 +:10E7E0000202020201010101010101010101010016 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000002E6 +:10E8300002020202020202020202020202020200BA +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000296 +:10E880000202020202020200020000000000020175 +:10E890000101010101010101010101010101010069 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000137 +:10E8E0000101010101010101010101010101010019 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000002E5 +:10E9300002020202020202020202020202020200B9 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000295 +:10E98000020202020202020202020002000002016E +:10E990000101010101010101010101010101010068 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000000000000000000000136 +:10E9E0000101010101010101010101010101010018 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000002E4 +:10EA300002020202010101010101010101010100C3 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000294 +:10EA8000020202020202020202020202000002016B +:10EA90000101010101010101010101010101010067 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000000000000000000000135 +:10EAE0000101010101010101010101010101010017 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000001E4 +:10EB300001010101010101010101010101010100C6 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000293 +:10EB80000202020202020202020202020202020166 +:10EB90000101010101010101010101010101010066 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000000000000000000000134 +:10EBE0000101010101010101010101010101010016 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000001E3 +:10EC300001010101010101010101010101010100C5 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000292 +:10EC80000202020202020202020202020202020165 +:10EC90000101010101010101010101010101010065 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000000000000000000000133 +:10ECE0000101010101010101010101010101010015 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000001E2 +:10ED300001010101010101010101010101010100C4 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000291 +:10ED80000202020202020202020202020202020164 +:10ED90000101010101010101010101010101010064 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000132 +:10EDE0000101010101010101010101010101010014 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000001E1 +:10EE300001010101010101010101010101010100C3 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000290 +:10EE80000202020202020202020202020202020163 +:10EE90000101010101010101010101010101010063 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000131 +:10EEE0000101010101010101010101010101010013 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000001E0 +:10EF300001010101010101010101010101010100C2 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF7000000000000000000000000000000000028F +:10EF80000202020202020202020202020202020162 +:10EF90000101010101010101010101010101010062 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000130 +:10EFE0000101010101010101010101010101010012 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000001DF +:10F0300001010101010101010101010101010100C1 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F07000000000000000000000000000000000028E +:10F080000202020202020202020202020202020161 +:10F090000101010101010101010101010101010061 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D000000000000000000000000000000000012F +:10F0E0000101010101010101010101010101010011 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000001DE +:10F1300001010101010101010101010101010100C0 +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000028D +:10F180000202020202020202020202020202020160 +:10F190000101010101010101010101010101010060 +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000012E +:10F1E0000101010101010101010101010101010010 +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000002DC +:10F2300002020202020202020202020202020200B0 +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000028C +:10F28000020202020202020202020202020202015F +:10F29000010101010101010101010101010101005F +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000022C +:10F2E0000202020202020202020202020202020000 +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000002DB +:10F3300002020202020202020202020202020200AF +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000028B +:10F38000020202020202020202020202020202005F +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F480000000000000000000000000000000002C50 +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000100000000000000001B +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000100000000000000001A +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E0000000000000000001000000000000000019 +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000002000000000000000017 +:10F7F0000001000000000000000000000000000008 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000100000000000067 +:10F8A0000000000000010000000000000000000057 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000002000000000001000015 +:10F8F0000001010100000100000000000000000004 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000200000000000075 +:10F990000000000000000000000100000100000065 +:10F9A0000000000000010000000000000000000056 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000000000000000000000000000037 +:10F9D0000000000000000000000000000000000027 +:10F9E0000000000000000002000100000001010012 +:10F9F0000001010101010100000000000000000001 +:10FA000000000000000000000000000000000000F6 +:10FA100000000000000000000000000000000000E6 +:10FA200000000000000000000000000000000000D6 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000200000000000074 +:10FA90000000000000000000010100000100000063 +:10FAA0000000000000010000000000000000000055 +:10FAB0000000000000000000000000000000000046 +:10FAC0000000000000000000000000000000000036 +:10FAD0000000000000000000000000000000000026 +:10FAE000000000000000000200010001010101010E +:10FAF0000001010101010100000000000000000000 +:10FB000000000000000000000000000000000000F5 +:10FB100000000000000000000000000000000000E5 +:10FB200000000000000000000000000000000000D5 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000200000000000073 +:10FB90000000000000000001010100000100000061 +:10FBA0000000000000010000000000000000000054 +:10FBB0000000000000000000000000000000000045 +:10FBC0000000000000000000000000000000000035 +:10FBD0000000000000000000000000000000000025 +:10FBE000000000000000000201010001010101010C +:10FBF00000010101010101000000000000000000FF +:10FC000000000000000000000000000000000000F4 +:10FC100000000000000000000000000000000000E4 +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000200000000000072 +:10FC90000000000000000001010100000100000060 +:10FCA0000001000001010000000000000000000051 +:10FCB0000000000000000000000000000000000044 +:10FCC0000000000000000000000000000000000034 +:10FCD0000000000000000000000000000000000024 +:10FCE000000000000000000201010101010101010A +:10FCF00000010101010101000000000000000000FE +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000100000000000072 +:10FD9000000000000100000101010000010100005D +:10FDA000000101000101000000000000000000004F +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000002010201010101010108 +:10FDF00001010101010101000000000000000000FC +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000010000000000000000C1 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000101000000000070 +:10FE9000000000000100000101010000010101005B +:10FEA000000101000101000000000000000000004E +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000002010201010101010107 +:10FEF00001010101010101000000000000000000FB +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000010000000000000000C0 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF8000000000000000000000010100000000006F +:10FF90000000000001000002010200010101010057 +:10FFA000000101000101000000000000000000004D +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000002020201010102010104 +:10FFF00001020101010101000000000000000000F9 +:02000002A0005C +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000010000000000000000BF +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:10008000000000000000000000010100010000016C +:100090000000000001000002010200010101010056 +:1000A000000101000101000000000000000000004C +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000002020202020102020100 +:1000F00001020201010101000000000000000000F7 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000000000000000000000CF +:1001300000000000000000010000000000000000BE +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000001010100010000016A +:100190000000000001010002020201010101010151 +:1001A000000101010101000000000000000000004A +:1001B000000000000000000000000000000000003F +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E00000000000000000020202020202020202FD +:1001F00001020202010101000000000000000000F5 +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000020000000001000000BB +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:100280000000000000000000010100010100000169 +:10029000000000000101010202020101010101014F +:1002A0000102010101010000000000000000000047 +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E00000000000000000020202020202020202FC +:1002F00001020202020202000000000000000000F1 +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000020001000001000000B9 +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:100380000000000000000000010100010100000168 +:10039000010000000101010202020101020201014B +:1003A0000102020101020000000000000000000044 +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E00000000000000000020202020202020202FB +:1003F00002020202020202000000000000000000EF +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000020101010101000000B5 +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:100480000000000000000000000000010100000169 +:100490000100000101010102020201010202020148 +:1004A0000102020101020000000000000000000043 +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E00000000000000000020202020202020202FA +:1004F00002020202020202000000000000000000EE +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000020101010101000000B4 +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:100580000000000000000000000000010100000168 +:100590000100010101010102020201020202020145 +:1005A0000102020101020000000000000000000042 +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E00000000000000000020202020202020202F9 +:1005F00002020202020202000000000000000000ED +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000020101010101010000B2 +:1006400000000000000001000000000000000000A9 +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:100680000000000000000000000000010100000167 +:100690000100010101010102020202020202020242 +:1006A0000102020101020000000000000000000041 +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E00000000000000000020202020202020202F8 +:1006F00002020202020202000000000000000000EC +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000020102010101010100AF +:1007400001000000010101000000000000000000A5 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000010068 +:100790000100010101010102020202020202020241 +:1007A000010202010202000000000000000000003F +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E00000000000000000020202020202020202F7 +:1007F00002020202020202000000000000000000EB +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000020202010101010101AC +:1008400001000101010101000000000000000000A2 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000010067 +:100890000101010100010102020202020202020240 +:1008A000010202020202000000000000000000003D +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E00000000000000000020202020202020202F6 +:1008F00002020202020202000000000000000000EA +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000020202020101010101AA +:1009400001000101010101000000000000000000A1 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000010066 +:10099000010101010001010202020202020202023F +:1009A000020202020202000000000000000000003B +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E00000000000000000020202020202020202F5 +:1009F00002020202020202000000000000000000E9 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000020202020202010101A7 +:100A400001000101010101000000000000000000A0 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000001010064 +:100A9000000101010001010202020202020202023F +:100AA000020202020202000000000000000000003A +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE00000000000000000020202020202020202F4 +:100AF00002020202020202000000000000000000E8 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000020202020202010101A6 +:100B4000010001010101010000000000000000009F +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000001010063 +:100B9000000101010000010202020202020202023F +:100BA0000202020202020100000000000000000038 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE00000000000000000020202020202020202F3 +:100BF00002020202020202000000000000000000E7 +:100C000000000000000000000000000000000000E4 +:100C100000000000000000000000000000000000D4 +:100C200000000000000000000000000000000000C4 +:100C300000000000000000020202020202020101A4 +:100C4000010001010101010000000000000000009E +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000002000000000001000061 +:100C9000000100010000010202020202020202023F +:100CA0000201010202020100000000000000000039 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE00000000000000000020202020202020202F2 +:100CF00002020202020202000000000000000000E6 +:100D000000000000000000000000000000000000E3 +:100D100000000000000000000000000000000000D3 +:100D200000000000000000000000000000000000C3 +:100D300000000000000000020202020202020201A2 +:100D4000010101010101010000000000000000009C +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000000000000000000000073 +:100D80000000000000000002000000000001000060 +:100D90000000000000000002020202020202020241 +:100DA0000201010202010100000000000000000039 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000000000000000000023 +:100DD0000000000000000000000000000000000013 +:100DE00000000000000000020202020202020202F1 +:100DF00002020202020202000000000000000000E5 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000020202020202020202A0 +:100E4000020101010101010000000000000000009A +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E8000000000000000000202020000000000005C +:100E90000000000000000002020202020201010143 +:100EA0000201010102010100000000000000000039 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE00000000000000000010202020202020202F1 +:100EF00002010101010101000000000000000000EA +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F3000000000000000000202020202020202029F +:100F40000201020101010100000000000000000098 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F8000000000000000000202020000000000005B +:100F90000000000000000002020202020201010142 +:100FA0000201010101010100000000000000000039 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE00000000000000000020202020202010202F0 +:100FF00002020202020202000000000000000000E3 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:10103000000000000000000202020202020202029E +:101040000201020202020200000000000000000093 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000002020202000000000058 +:101090000000000000000002020102010101010144 +:1010A0000101010101010100000000000000000039 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E00000000000000000000201010202020000F6 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:10113000000000000000000202020202020202029D +:101140000202020202020200000000000000000091 +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:101180000000000000000002020202020200000053 +:101190000000000000000001010101010101010146 +:1011A0000101010101010100000000000000000038 +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000202020000000101F7 +:1011F00001010101010101000000000000000000E8 +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:10123000000000000000000202020202020202029C +:101240000202020202020200000000000000000090 +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:101280000000000000000002020202020200000052 +:101290000000000000000001010101010101010145 +:1012A0000101010101010100000000000000000037 +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000101010101F9 +:1012F00001010101010101000000000000000000E7 +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:10133000000000000000000202020202020202029B +:10134000020202020202020000000000000000008F +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000202020202020000024F +:101390000000000000000001010101010101010144 +:1013A0000101010101010100000000000000000036 +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000010101010101010101F4 +:1013F00001010101010101000000000000000000E6 +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:10143000000000000000000202020202020202029A +:10144000020202020202020000000000000000008E +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000202020202020202024A +:10149000020000000200000101010101010101013F +:1014A0000101010101010100000000000000000035 +:1014B000000000000000000000000000000000002C +:1014C000000000000000000000000000000000001C +:1014D000000000000000000000000000000000000C +:1014E00000000000000000010101010101010101F3 +:1014F00001010101010101000000000000000000E5 +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:101530000000000000000002020202020202020299 +:10154000020202020202020000000000000000008D +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:101580000000000000000002020202020202020249 +:101590000200020202020201010101010101010136 +:1015A0000101010101010100000000000000000034 +:1015B000000000000000000000000000000000002B +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000010101010101010101F2 +:1015F00001010101010101000000000000000000E4 +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:101630000000000000000002020202020202020298 +:10164000020202020202020000000000000000008C +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:101680000000000000000002020202020202020248 +:101690000202020202020201010101010101010133 +:1016A0000101010101010100000000000000000033 +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000010101010101010101F1 +:1016F00001010101010101000000000000000000E3 +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:101730000000000000000002020202020202020297 +:10174000020202020202020000000000000000008B +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000002020202020202020247 +:101790000202020202020201010101010101010132 +:1017A0000101010101010100000000000000000032 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000000000000000000019 +:1017D0000000000000000000000000000000000009 +:1017E00000000000000000010101010101010101F0 +:1017F00001010101010101000000000000000000E2 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:101830000000000000000002020202020202020296 +:10184000020202020202020000000000000000008A +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000002020202020202020246 +:101890000202020202020201010101010101010131 +:1018A0000101010101010100000000000000000031 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000010101010101010101EF +:1018F00001010101010101000000000000000000E1 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000200000000000000A5 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000002020202020202020245 +:101990000202020202020201010101010101010130 +:1019A0000101010101010100000000000000000030 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000010101010101010101EE +:1019F00001010101010101000000000000000000E0 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A3000000000000000000101010101010101019D +:101A4000010101010101010000000000000000008F +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000002020202020202020244 +:101A9000020202020202020101010101010101012F +:101AA000010101010101010000000000000000002F +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000010101010101010101ED +:101AF00001010101010101000000000000000000DF +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B3000000000000000000101010101010101019C +:101B4000010101010101010000000000000000008E +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000002020202020202020243 +:101B9000020202020202020101010101010101012E +:101BA000010101010101010000000000000000002E +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000010101010101010101EC +:101BF00001010101010101000000000000000000DE +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000000000000000B4 +:101C3000000000000000000101010101010101019B +:101C4000010101010101010000000000000000008D +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000000000002020202020202020242 +:101C9000020202020202020101010101010101012D +:101CA000010101010101010000000000000000002D +:101CB0000000000000000000000000000000000024 +:101CC0000000000000000000000000000000000014 +:101CD0000000000000000000000000000000000004 +:101CE00000000000000000010101010101010101EB +:101CF00001010101010101000000000000000000DD +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000000C3 +:101D200000000000000000000000000000000000B3 +:101D3000000000000000000101010101010101019A +:101D4000010101010101010000000000000000008C +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000073 +:101D70000000000000000000000000000000000063 +:101D80000000000000000002020202020202020241 +:101D9000020202020202020101010101010101012C +:101DA000010101010101010000000000000000002C +:101DB0000000000000000000000000000000000023 +:101DC0000000000000000000000000000000000013 +:101DD0000000000000000000000000000000000003 +:101DE00000000000000000020202020202020202E1 +:101DF00002020202020202000000000000000000D5 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E30000000000000000001010101010101010199 +:101E4000010101010101010000000000000000008B +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000002020202020202020240 +:101E9000020202020202020101010101010101012B +:101EA000010101010101010000000000000000002B +:101EB0000000000000000000000000000000000022 +:101EC0000000000000000000000000000000000012 +:101ED0000000000000000000000000000000000002 +:101EE00000000000000000020202020202020202E0 +:101EF00002020202020202000000000000000000D4 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000000000000000000B1 +:101F3000000000000000000202020202020202028F +:101F40000202020202020200000000000000000083 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F8000000000000000000202020202020202023F +:101F90000202020202020200000000000000000033 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000000000000000000021 +:101FC0000000000000000000000000000000000011 +:101FD0000000000000000000000000000000000001 +:101FE00000000000000000000000000000000000F1 +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000000000000000000B0 +:1020300000000000000000000000000000000000A0 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:10209000000000000000002400000000000000011B +:1020A0000101010101010101010101010101010021 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000000000000000010 +:1020D0000000000000000000000000000000000000 +:1020E00000000000000000000000000000000000F0 +:1020F00000000000000000000000000000000100DF +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000010000000000000101008C +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000024D +:10219000010101010101010101010101010101012F +:1021A0000101010101010101010101010101010020 +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000100DE +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:102240000000000001010101010100000001010086 +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000024C +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101001F +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000100DD +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:102340000000000001010101010100000001010085 +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000024B +:10239000010101010101010101010101010101022C +:1023A000010101010101010101010101010101001E +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00000000000000000000000000000000000FD +:1023E00000000000000000000000000000000000ED +:1023F00000000000000100000000000000000100DB +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:102440000000000001010101010100000001010084 +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000024A +:10249000010101010101010101010101010101022B +:1024A000010101010101010101010101010101001D +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000100000000000000000100DA +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:102540000000000001010101010100000001010083 +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:102580000000000000000000000000000000000249 +:10259000010101010101010101010101010101022A +:1025A0000102010201010101010101010201010019 +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000100000000000000000100D9 +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:102640000000000001010101010100010001010081 +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:102680000000000000000000000000000000000248 +:10269000010001010101010101010101010101022A +:1026A0000202020201020201010102010201010013 +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000001E9 +:1026F00001000000000101000000000000010100D5 +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:10274000000100000101010101010101000101007E +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000247 +:10279000000000000101010101000001000101022F +:1027A000020202020102020202020202020101000E +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000001E8 +:1027F00001000001010101010000000000010100D1 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:10284000000100000101010101010101000101007D +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000246 +:102890000000000001000001000000000001010232 +:1028A000020202020202020202020202020101000C +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000002E6 +:1028F00001000001010101010000000000010100D0 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:10294000000101000101010101010101000101007B +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000245 +:102990000000000000000000000000000001010233 +:1029A000020202020202020202020202010101000C +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000002E5 +:1029F00001000001010101010000000202010100CB +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000001010101010101010101010001010079 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000244 +:102A90000000000000000000000000000001020231 +:102AA000020202020202020202020202010101000B +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000002E4 +:102AF00001010101010101010000010102010100C8 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000101010101010101010101010001010077 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000243 +:102B90000000000000000000000000000001020230 +:102BA000020202020202020202020102010101000B +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000002E3 +:102BF00002010101010201010100010101010100C5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000102010102020201010101010101010071 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000242 +:102C9000000000000000000000000000000102022F +:102CA000020202010202010202020102010101000C +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000004 +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000002E2 +:102CF00002010102010201010100010101010100C3 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000291 +:102D4000010201010202020202020101010101006D +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000241 +:102D9000000000000000000000000000000002022F +:102DA000020202010201010101020101010101000F +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000002E1 +:102DF00002020102020202010102010101010200BC +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000290 +:102E4000010202010202020202020101010101006B +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000240 +:102E9000000000000000000000000000000002022E +:102EA000020102010201010101010101010201000F +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000002E0 +:102EF00002020202020202020101010101010200BA +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F3000000000000000000000000000000000028F +:102F40000202020202020202020201010102020066 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F8000000000000000000000000000000000023F +:102F9000000200000000000000000000000002022B +:102FA000020101010201010101010101010201000F +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000002DF +:102FF00002020202020202020101020101010200B8 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:10303000000000000000000000000000000000028E +:103040000202020202020202020202020102020063 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:10308000000000000000000000000000000000023E +:10309000020202020000000000020200020002021E +:1030A0000101010101010101010101010102010010 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000002DE +:1030F00002020202020202020201020201020200B4 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000028D +:103140000202020202020202020202020102020062 +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000023D +:103190000202020200020200020202020200020116 +:1031A000010101010101010101010101010201000F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000000FF +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000002DD +:1031F00002020202020202020201020202020200B2 +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000028C +:103240000202020202020202020202020102020061 +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000023C +:10329000020202020202020202020202020202010F +:1032A000010101010101010101010101010200000F +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000000FE +:1032D00000000000000000000000000000000000EE +:1032E00000000000000000000000000000000002DC +:1032F00002020202020202020202020202020200B0 +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000028B +:10334000020202020202020202020202020202005F +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:103390000202020202020202020202020202000110 +:1033A000010101010101010101010101010200000E +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000000FD +:1033D00000000000000000000000000000000000ED +:1033E00000000000000000000000000000000002DB +:1033F00002020202020202020202020202020200AF +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000028A +:10344000020202020202020202020202020202005E +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000020202020202020202020202020200010F +:1034A000010101010101010101010101010200000D +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000000EC +:1034E00000000000000000000000000000000002DA +:1034F00002020202020202020202020202020200AE +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:103530000000000000000000000000000000000289 +:10354000020202020202020202020202020202005D +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000020202020202020202020202020200010E +:1035A000010101010101010101010101010200000C +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000000000000000000000EB +:1035E00000000000000000000000000000000002D9 +:1035F00002020202020202020202020202020200AD +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:103630000000000000000000000000000000000288 +:10364000020202020202020202020202020202005C +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000020202020202020202020202020200010D +:1036A000010101010101010101010101010100000C +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000002D8 +:1036F00002020202020202020202020202020200AC +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000287 +:10374000020202020202020202020202020202005B +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:10379000020202020202020202020202020200010C +:1037A000010101000101010101010101000100000D +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000002D7 +:1037F00002020202020202020202020202020200AB +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000286 +:10384000020202020202020202020202020202005A +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:10389000020202020202020202020202020200010B +:1038A000010001000101000101010001000100000F +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000002D6 +:1038F00002020202020202020202010101020200AD +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000285 +:103940000202020202020202020202020202020059 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:10399000020202020202020202020202000200010C +:1039A0000100010001000000000100010001000011 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000002D5 +:1039F00002020201010202020202020202020200AB +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000284 +:103A40000202020202020202020202020202020058 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A9000020202020202020202020002000200010D +:103AA0000000000001000000000100010001000012 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000002D4 +:103AF00002020202020101010101010101010100B2 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000283 +:103B4000020101010202020202020202020202005A +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000202020202020202020000000002000110 +:103BA0000000000000000000000000000001000014 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000001D4 +:103BF00001010101010101010101010101010100B6 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000282 +:103C40000202020201010101010101010101010061 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000202020202020202020000000002000010 +:103CA0000000000000000000000000000001000013 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000001D3 +:103CF00001010101010101010101010101010100B5 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000182 +:103D40000101010101010101010101010101010064 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000202020202020202000000000002000011 +:103DA0000000000000000000000000000001000012 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000001D2 +:103DF00001010101010101010101010101010100B4 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000181 +:103E40000101010101010101010101010101010063 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000202020202020002000000000000000014 +:103EA0000000000000000000000000000001000011 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000001D1 +:103EF00001010101010101010101010101010100B3 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000180 +:103F40000101010101010101010101010101010062 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000202020002000000000000000000000019 +:103FA0000000000000000000000000000001000010 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000001D0 +:103FF00001010101010101010101010101010100B2 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:10403000000000000000000000000000000000017F +:104040000101010101010101010101010101010061 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:10409000020000000200000000000000000000001C +:1040A000000000000000000000000000000100000F +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000001CF +:1040F00001010101010101010101010101010100B1 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000017E +:104140000101010101010101010101010101010060 +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000020000000000000000000000000000001D +:1041A000000000000000000000000000000100000E +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000001CE +:1041F00001010101010101010101010101010100B0 +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000027C +:104240000202020202020202020202020202020050 +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000002CC +:1042F00002020202020202020202020202020200A0 +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000027B +:10434000020202020202020202020202020202004F +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:104490000000000000000000000000000000001EFE +:1044A0000000000000000001010101010101010103 +:1044B00001010101010101000000000000000000F5 +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000010001BA +:1045000000000000000101000000000000000000A9 +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000001006A +:10455000000100000000000000000000000000005A +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:104590000000000000000002010101010101010111 +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101000000000000000000F4 +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000001010101B7 +:1046000000000000000101000000000000000000A8 +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:104640000000000000000000010000000001010166 +:104650000101000100010100000000000000000055 +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:104690000000000000000002010101010101010110 +:1046A00001010101010101020101010101010101F9 +:1046B00001010101010101000000000000000000F3 +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000001010101B6 +:1047000002000000000101000000000000000000A5 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000010000000001010165 +:104750000101010100010100000000000000000053 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:10479000000000000000000201010101010101010F +:1047A00001010101010101020101010101010101F8 +:1047B00001010101010101000000000000000000F2 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000001010101B5 +:1048000001010200000101000000000000000000A2 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000010100000001010163 +:104850000101010100010100000000000000000052 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:10489000000000000000000201010101010101010E +:1048A00001010101010101020101010101010101F7 +:1048B00001010101010101000000000000000000F1 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000100000001010101B3 +:10490000010101020201010000000000000000009E +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000010101000001010161 +:104950000101010100010100000000000000000051 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000002000101010000000111 +:1049A00001010101010101020101010101020101F5 +:1049B00001010101010101000000000000000000F0 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000100000001010101B2 +:104A0000010101010101010000000000000000009F +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A4000000000000000000201010100000101015E +:104A5000010101010101010000000000000000004F +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000002000001000000000112 +:104AA00000000001010101020202010102020101F4 +:104AB00001010101010101000000000000000000EF +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000101000001010101B0 +:104B0000010101010101010000000000000000009E +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B4000000000000000000202010101000101015B +:104B5000010101010101010000000000000000004E +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000002000000000000000013 +:104BA00000000000000101020202010102020201F4 +:104BB00001010101010101000000000000000000EE +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000101000001010101AF +:104C0000010101010101010000000000000000009D +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C4000000000000000000202010101000101015A +:104C5000010101010101010000000000000000004D +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000002000000000000000012 +:104CA00000000000000102020202020202020201F0 +:104CB00001010201010101000000000000000000EC +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000101000002020101AC +:104D0000010101010101010000000000000000009C +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000002020201010002020156 +:104D5000010101010101010000000000000000004C +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000002000000000000000011 +:104DA00000000000000002020202020202020202EF +:104DB00002020201010101000000000000000000E9 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000020201010002020202A5 +:104E0000010101010101010000000000000000009B +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000002020202010002020253 +:104E50000202010101010100000000000000000049 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000002000000000000000010 +:104EA00000020000000002020202020202020202EC +:104EB00002020202020101000000000000000000E6 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000020201010002020202A4 +:104F0000010101010101010000000000000000009A +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000002020202020002020251 +:104F50000202020201010100000000000000000046 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F9000000000000000000202000000000000000D +:104FA00000020000000002020202020202020202EB +:104FB00002020202020101000000000000000000E5 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000020202010102020202A1 +:105000000202010101020200000000000000000095 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000002020202020002020250 +:105050000202020201020200000000000000000043 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:10509000000000000000000202020000000000000A +:1050A00000020000000202020202020202010202E9 +:1050B00002020202020101000000000000000000E4 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000020202010102020202A0 +:105100000202020101020200000000000000000093 +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000202020202010202024E +:105150000202020202020200000000000000000041 +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:105190000000000000000002020200000202020003 +:1051A00000020000000202010202020202010202E9 +:1051B00002020202020201000000000000000000E2 +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F000000000000000000202020201020202029E +:105200000202020202020200000000000000000090 +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000202020202020202024C +:105250000202020202020200000000000000000040 +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:105290000000000000000002020200020202020000 +:1052A00002020200000202010201020201010202E6 +:1052B00002020202020201000000000000000000E1 +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F000000000000000000202020202020202029C +:10530000020202020202020000000000000000008F +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000202020202020202024B +:10535000020202020202020000000000000000003F +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:1053900000000000000000020202020202020202FB +:1053A00002020202020200010201020201010102E4 +:1053B00002020102020200000000000000000000E2 +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F000000000000000000202020202020202029B +:10540000020202020202020000000000000000008E +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000202020202020202024A +:10545000020202020202020000000000000000003E +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:1054900000000000000000000202020202020202FC +:1054A00002020202020200010101020201010102E4 +:1054B00002010102020200000000000000000000E2 +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F000000000000000000202020202020202029A +:10550000020202020202020000000000000000008D +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:105540000000000000000002020202020202020249 +:10555000020202020202020000000000000000003D +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:1055900000000000000000000202020202020202FB +:1055A00002020202020200010101020201010102E3 +:1055B00002010102010200000000000000000000E2 +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F0000000000000000002020202020202020299 +:10560000020202020202020000000000000000008C +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:105640000000000000000002020202020202020248 +:10565000020202020202020000000000000000003C +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:1056900000000000000000000202020202020202FA +:1056A00002000202020200010101010101010101E7 +:1056B00001010101010200000000000000000000E3 +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000000CA +:1056E00000000000000000000000000000000000BA +:1056F0000000000000000002020202020202020298 +:10570000020202020202020000000000000000008B +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000002020202020202020247 +:10575000020202020202020000000000000000003B +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:1057900000000000000000000202020202020202F9 +:1057A00002000202020200010101010101010101E6 +:1057B00001010101010200000000000000000000E2 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000000000000000000000C9 +:1057E00000000000000000000000000000000000B9 +:1057F0000000000000000002020202020202020297 +:10580000020202020202020000000000000000008A +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000001020202020202020247 +:10585000020202020202020000000000000000003A +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:1058900000000000000000000202020202020202F8 +:1058A00002000202020000010101010101010101E7 +:1058B00001010101010100000000000000000000E2 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000000000000000000000C8 +:1058E00000000000000000000000000000000000B8 +:1058F0000000000000000002020202020202020296 +:105900000202020202020200000000000000000089 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:10594000000000000000000101010101010202024B +:105950000202020202020200000000000000000039 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:1059900000000000000000000202020202020202F7 +:1059A00002000202020000010101010101010101E6 +:1059B00001010101010100000000000000000000E1 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000000000000000000000C7 +:1059E00000000000000000000000000000000000B7 +:1059F0000000000000000002020202020101010199 +:105A0000010101010101010000000000000000008F +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A4000000000000000000202020202020000004A +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A900000000000000000000202020202020002F8 +:105AA00002000002020000000101010101010101E8 +:105AB00001010101010100000000000000000000E0 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF000000000000000000101010101010101019D +:105B0000010101010101010000000000000000008E +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000002000000000001010150 +:105B5000010101010101010000000000000000003E +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B900000000000000000000202020202000002F9 +:105BA00000000000000000000100010101000101EF +:105BB00001010101010100000000000000000000DF +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF000000000000000000101010101010101019C +:105C0000010101010101010000000000000000008D +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C4000000000000000000101010101010101014B +:105C5000010101010101010000000000000000003D +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C900000000000000000000202020200000002FA +:105CA00000000000000000000100010100000101EF +:105CB00001010101010100000000000000000000DE +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF000000000000000000101010101010101019B +:105D0000010101010101010000000000000000008C +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D4000000000000000000101010101010101014A +:105D5000010101010101010000000000000000003C +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D900000000000000000000000020200000000FF +:105DA00000000000000000000000010100000101EF +:105DB00001010101010100000000000000000000DD +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF000000000000000000101010101010101019A +:105E0000010101010101010000000000000000008B +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000001010101010101010149 +:105E5000010101010101010000000000000000003B +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000002000000000000 +:105EA00000000000000000000000010100000001EF +:105EB00001000001010100000000000000000000DE +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF0000000000000000001010101010101010199 +:105F0000010101010101010000000000000000008A +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000001010101010101010148 +:105F5000010101010101010000000000000000003A +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F900000000000000000000000020000000000FF +:105FA00000000000000000000000010100000001EE +:105FB00001000001000100000000000000000000DE +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF0000000000000000001010101010101010198 +:106000000101010101010100000000000000000089 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:10604000000000000000000202020202020202023E +:106050000202020202020200000000000000000032 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000001EF +:1060B00001000001000100000000000000000000DD +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000000000000000000B0 +:1060F000000000000000000202020202020202028E +:106100000202020202020200000000000000000081 +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000202020202020202023D +:106150000202020202020200000000000000000031 +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A000000000000000001E0000000000000001CF +:1062B00001010101010101010101010101010100CF +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:106300000001010001000000000000000000010089 +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000002FB +:1063A00001010101010101010101010101010101DD +:1063B00001010101010101010101010101010100CE +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:106400000001010101010000000002000101010082 +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000002FA +:1064A00001010101010101010101010101010102DB +:1064B00001010101010101010101010101010100CD +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:106500000001010101010000000002000101010081 +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:106550000101000100000000000000000000000038 +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000002F9 +:1065A00001010101010101010101010101010102DA +:1065B00001010101010101010101010101010100CC +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:106600000001010101010000000001000101010081 +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:106650000101000100000000000000000000000037 +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000002F8 +:1066A00000010101010101010101010101010102DA +:1066B00002020101010101010101010101010100C9 +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000000000000000000AA +:1066F0000000000000000000000000000000000199 +:106700000001010101010000000001000101010080 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000101010101000000000000000000010033 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000002F7 +:1067A00000010101010101010101010101010102D9 +:1067B00002020201010101010101010101010100C7 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000198 +:10680000000101010101000000000100010101007F +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:10685000010101010101000000000000010101002F +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000002F6 +:1068A00000000001000000010000000001010102E1 +:1068B00002020201010102010101010101010100C5 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000000B8 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000296 +:10690000000101010101000000000100010101007E +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:10695000010101010101000000000000010101002E +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000002F5 +:1069A00000000000000000000000000001010102E2 +:1069B00002020202020102020201010101010100C0 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000000000000000000B7 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000295 +:106A0000010201010101000000000100010101007B +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A5000010101010101000000010000010101002C +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000002F4 +:106AA00000000000000000000000000001000102E2 +:106AB00002020202020202020201020101010100BD +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000000B6 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000294 +:106B00000102020102010000000001000101010078 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000144 +:106B50000201010101010000000100010101010029 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000002F3 +:106BA00000000000000000000000000000000102E2 +:106BB00002020202020202020202020201010100BA +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000293 +:106C00000202020202020000000001000101010074 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000242 +:106C50000202010101010100000100010101010026 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000002F2 +:106CA00002000200020202000202020000000002D2 +:106CB00002010102020202020202020201010100BB +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000292 +:106D0000020202020202000002000102010101006F +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000241 +:106D50000202010201010101010100010101010022 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000002F1 +:106DA00002000202020202020202020000000002CD +:106DB00002010102020202020202020201010100BA +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000291 +:106E0000020202020202000101020101020202006A +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000240 +:106E5000020202020201010101010101010101001E +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000002F0 +:106EA00002020202020202020202020200000202C6 +:106EB00001010102020201020202020202020100B9 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000290 +:106F00000202020202020001010102010202020069 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F4000000000000000000000000000000000023F +:106F5000020202020202010101010101010101001C +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000002EF +:106FA00002020202020202020202020200000201C6 +:106FB00001010101020201010202020202020100BA +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF000000000000000000000000000000000028F +:107000000202020202020101010102010202020067 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:10704000000000000000000000000000000000023E +:10705000020202020202010101010101010101001B +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000002EE +:1070A00002020202020202020202020200020201C3 +:1070B00001010101010201010102010202020100BC +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F000000000000000000000000000000000028E +:107100000202020202020102010102010202020065 +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000023D +:107150000202020202020201010201010202020015 +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000002ED +:1071A00002020202020202020202020202020201C0 +:1071B00001010101010201010102010102020000BD +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000028D +:107200000202020202020202020102010202020062 +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000023C +:107250000202020202020202020201020202020011 +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00002020202020202020202020202020201BF +:1072B00001010101010101010101010102020000BE +:1072C00000000000000000000000000000000000BE +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000028C +:10730000020202020202020202020202020202005F +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000023B +:10735000020202020202020202020202020202000F +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00002020202020202020202020202020201BE +:1073B00001010101010101010101010102020000BD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000028B +:10740000020202020202020202020202020202005E +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000023A +:10745000020202020202020202020202020202000E +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00002020202020202020200000202020201C1 +:1074B00001000001010101010101010101010000C0 +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000028A +:10750000020202020202020202020202020202005D +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:107540000000000000000000000000000000000239 +:10755000020202020202020202020202020202000D +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00002020202020202020000000002020201C4 +:1075B00001000001010101010101010101010000BF +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F0000000000000000000000000000000000289 +:10760000020202020202020202020202020202005C +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:107640000000000000000000000000000000000238 +:10765000020202020202020202020202020202000C +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00002020202020000020000000002020201C7 +:1076B00000000001010101010101010101010000BF +:1076C00000000000000000000000000000000000BA +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F0000000000000000000000000000000000288 +:10770000020202020202020002020202020202005D +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000237 +:10775000020202020202020202020202020202000B +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00002020202000000000000000002020001CC +:1077B00000000000010101010101010101010000BF +:1077C00000000000000000000000000000000000B9 +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000287 +:107800000002020200000000000000000000000072 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000236 +:10785000020202020202020202020202020202000A +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00002020002000000000000000002000000D0 +:1078B00000000000010100010101010101010000BF +:1078C00000000000000000000000000000000000B8 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000187 +:107900000101010101010101010101010101010068 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000235 +:107950000202020202020202020202020202020009 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00002020000000000000000000002000000D1 +:1079B00000000000000100000101010101010000C0 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000186 +:107A00000101010101010101010101010101010067 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000234 +:107A50000202020000000000000000000000000020 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000020000000000000000000000000000D4 +:107AB00000000000000100000101000101010000C0 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000185 +:107B00000101010101010101010101010101010066 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000020000000000000000000000000000D3 +:107BB00000000000000100000001000001010000C1 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000184 +:107C00000101010101010101010101010101010065 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000133 +:107C50000101010101010101010101010101010015 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000183 +:107D00000101010101010101010101010101010064 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000132 +:107D50000101010101010101010101010101010014 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000182 +:107E00000101010101010101010101010101010063 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000131 +:107E50000101010101010101010101010101010013 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000280 +:107F00000202020202020202020202020202020053 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F4000000000000000000000000000000000022F +:107F50000202020202020202020202020202020003 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A0000000000000000000000000000000001EB2 +:1080B00000000000000000010101010101010101B7 +:1080C00001010101010101000000000000000000A9 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000001010000000000006D +:10811000000000000000010000000000000000005E +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000101010101010101C7 +:1081B00001010101010101010101010101010101AF +:1081C00001010101010101000000000000000000A8 +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000001010000000000006C +:10821000000000000000010000000000000000005D +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000101010101010101C6 +:1082B00001010101010101020101010101010101AD +:1082C00001010101010101000000000000000000A7 +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000001010001000000006A +:10831000000000000000010000000000000000005C +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000101010101010101C5 +:1083B00001010101010101020101010101010101AC +:1083C00001010101010101000000000000000000A6 +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:108400000000000000000000010101010100000067 +:10841000000000000000010000000000000000005B +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:108460000000010100010000000000000000000009 +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000020101010101010101C2 +:1084B00001010101010101020101010101010101AB +:1084C00001010101010101000000000000000000A5 +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:108500000000000000000000010101010100000066 +:10851000000000000000010000000000000000005A +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:108550000000000000000000010100000000000019 +:108560000000010100010100000000000000000007 +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000020101010101010101C1 +:1085B00001010101010101020101010101010101AA +:1085C00001010101010101000000000000000000A4 +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:108600000000000000000000010101010100000065 +:108610000000000000000100000000000000000059 +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:108650000000000000000000010100000100000017 +:108660000100010101010100000000000000000004 +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000020101010101010101C0 +:1086B00001010101010101020201010101010101A8 +:1086C00001010101010101000000000000000000A3 +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000002020101010100010060 +:108710000000000000000100000000000000000058 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000010100010100010014 +:108760000100010101010100000000000000000003 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000020001010101010101C0 +:1087B00001010101010101020201010101010101A7 +:1087C00001010101010101000000000000000000A2 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:10880000000000000000000202020101010001005E +:108810000100000001000100000000000000000055 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000010101010100010012 +:108860000100010101010100000000000000000002 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000020000010101010101C0 +:1088B00001000101010101020202020101020102A3 +:1088C00002010101010101000000000000000000A0 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:10890000000000000000000202020101010001005D +:108910000100000001000100000000000000000054 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000010101010100010011 +:108960000100010101010100000000000000000001 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000020000010001010101C0 +:1089B00001000101010101020202020201020102A1 +:1089C000020101010101010000000000000000009F +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A0000000000000000000202020202010001005A +:108A10000100000001010100000000000000000052 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A5000000000000000000101010101010101000E +:108A600001010101010101000000000000000000FF +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000020000000000000000C4 +:108AB000000001010101010202020202020202029F +:108AC000020101010101010000000000000000009E +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000002020202020200010058 +:108B10000100000001010100000000000000000051 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B5000000000000000000202010101010101010A +:108B600001010101010101000000000000000000FE +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000020002000000000000C1 +:108BB000000201010101010202020202020202029C +:108BC000020201010101010000000000000000009C +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000002020202020201010155 +:108C1000010000000101020000000000000000004F +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000002020201010101010108 +:108C600001010101010101000000000000000000FD +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000020202000200000000BC +:108CB000000201010001010202020202020202029C +:108CC000020202010101010000000000000000009A +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000002020202020201020153 +:108D1000010100000101020000000000000000004D +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000002020201010101010107 +:108D600001010101010101000000000000000000FC +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000020202020202000200B5 +:108DB000020200000000000202020202020202029D +:108DC0000202020202010100000000000000000097 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000002020202020201020251 +:108E1000020100010101020000000000000000004A +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000002020202020201010103 +:108E600001010101010101000000000000000000FB +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000020202020202020202B0 +:108EB000020200000000000102020202020202029D +:108EC0000102020202020100000000000000000096 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F0000000000000000000202020202020202024F +:108F10000202000102010200000000000000000047 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000002020202020201020101 +:108F600002010202010201000000000000000000F6 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000020202020202020202AF +:108FB000020200000200000102020202020202029A +:108FC0000102020202020000000000000000000096 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:10900000000000000000000202020202020202024E +:109010000202010102020200000000000000000044 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:1090500000000000000000020202020202020201FF +:1090600002010202020202000000000000000000F3 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000020202020202020202AE +:1090B0000202020202020201020202020202020291 +:1090C0000102020202020000000000000000000095 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000202020202020202024D +:109110000202010102020200000000000000000043 +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:1091500000000000000000020202020202020202FD +:1091600002020202020202000000000000000000F1 +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000020202020202020202AD +:1091B0000202020202020201010202020201020193 +:1091C0000102020202020000000000000000000094 +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000202020202020202024C +:109210000202010202020200000000000000000041 +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:1092500000000000000000020202020202020202FC +:1092600002020202020202000000000000000000F0 +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000020202020202020202AC +:1092B0000202020202020201010201020201020193 +:1092C0000102020202020000000000000000000093 +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000202020202020202024B +:10931000020202020202020000000000000000003F +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:1093500000000000000000020202020202020202FB +:1093600002020202020202000000000000000000EF +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000202020202020202AD +:1093B0000202020202020201010101010101010196 +:1093C0000101010202020000000000000000000094 +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000202020202020202004C +:109410000200020202020200000000000000000040 +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:1094500000000000000000020202020202020202FA +:1094600002020202020202000000000000000000EE +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000202020202020202AC +:1094B0000202020202020201010101010101010195 +:1094C0000101010101020000000000000000000095 +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000102020202020202004C +:10951000020002020202020000000000000000003F +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:1095500000000000000000020202020202020202F9 +:1095600002020202020202000000000000000000ED +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000202020202020202AB +:1095B0000200020202020201010101010101010196 +:1095C0000101010101010000000000000000000095 +:1095D000000000000000000000000000000000008B +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:10960000000000000000000202020202020202004A +:10961000020002020202020000000000000000003E +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:1096500000000000000000020202020202020202F8 +:1096600002020202020202000000000000000000EC +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000202020202020202AA +:1096B0000200020202020201010101010101010195 +:1096C0000101010101010000000000000000000094 +:1096D000000000000000000000000000000000008A +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:109700000000000000000000010101010101010151 +:109710000101010101010100000000000000000042 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:1097500000000000000000020202020202020202F7 +:1097600002020202020202000000000000000000EB +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000202020202020202A9 +:1097B0000200020202020201010101010101010194 +:1097C0000101010101010000000000000000000093 +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:10980000000000000000000101010101010101014F +:109810000101010101010100000000000000000041 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:1098500000000000000000020202020202020202F6 +:1098600002020202020202000000000000000000EA +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000202020202020202A8 +:1098B0000200020202020200010101010101010194 +:1098C0000001010101010000000000000000000093 +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000000000000000078 +:1098F0000000000000000000000000000000000068 +:10990000000000000000000101010101010101014E +:109910000101010101010100000000000000000040 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:1099500000000000000000020202020202020202F5 +:1099600002020202020202000000000000000000E9 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000202020202020202A7 +:1099B0000000020202020200010101010101010195 +:1099C0000001010101010000000000000000000092 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0000000000000000000000000000000000067 +:109A0000000000000000000101010101010101014D +:109A1000010101010101010000000000000000003F +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A500000000000000000010101010101010101FD +:109A600001010101010101000000000000000000EF +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000200020002020002AC +:109AB0000000020202020200010101010101010194 +:109AC0000001010101010000000000000000000091 +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000076 +:109AF0000000000000000000000000000000000066 +:109B0000000000000000000101010101010101014C +:109B1000010101010101010000000000000000003E +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B500000000000000000010101010101010101FC +:109B600001010101010101000000000000000000EE +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000200020000020000AF +:109BB0000000020200020200000101010101010196 +:109BC0000001010101010000000000000000000090 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C0000000000000000000101010101010101014B +:109C1000010101010101010000000000000000003D +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C500000000000000000010101010101010101FB +:109C600001010101010101000000000000000000ED +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000020000000000B2 +:109CB000000002020002000000010001000001019A +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000002020202020202020241 +:109D10000202020202020200000000000000000035 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D500000000000000000020202020202020202F1 +:109D600002020202020202000000000000000000E5 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB000000000000000001E000000000000000282 +:109EC0000101010101010101010101010101010083 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F1000010000000000000000000000000100003F +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB0000101010101010101010101010101010290 +:109FC0000101010101010101010101010101010082 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A01000010000000100000000000000000100003D +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B000010101010101010101010101010101028F +:10A0C0000101010101010101010101010101010081 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000010000000100000000000000000101003B +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000002AD +:10A1B000010101010101010101010101010101028E +:10A1C0000101010101010101010101010101010080 +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A210000101000001000000000000000001010039 +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000002AC +:10A2B000010101010101010101010101010101028D +:10A2C000020101010101010101010101010101007E +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A310000101000001000000000001000001010037 +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000002AB +:10A3B000010101010101010101010101010101028C +:10A3C000020101010101010101010101010101007D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A410000201010001000000000001000001010034 +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000002AA +:10A4B000010101010101010101010101010101028B +:10A4C000020101010101010101010101020101007B +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A500000000000000000000000000000000000249 +:10A510000201010001000000000001010101010031 +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600001000000000000000000000000000000EA +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000002A9 +:10A5B000010101010101010101010101010101028A +:10A5C0000201010201010101010101020201010078 +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A600000000000000000000000000000000000248 +:10A61000020101000101000000000101010101002F +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600001010100010000000000000000000000E6 +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000002A8 +:10A6B000000101010101010101010101010101028A +:10A6C0000202020201020102010101020201010073 +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000247 +:10A71000020201000201000000000101010101002C +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000002F7 +:10A7600001010100010000000000000000010000E4 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000002A7 +:10A7B0000001010101010101010101010101010289 +:10A7C0000202020202020202010101020201010070 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000246 +:10A810000202020102010000000001010101010029 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000002F6 +:10A8600002010101010100000000000000010000E0 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000002A6 +:10A8B0000201010101010101010101010101010286 +:10A8C000020202020202020202010102020101006E +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000058 +:10A900000000000000000000000000000000000245 +:10A910000202020102010000000001010101010028 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000002F5 +:10A9600002010101010101000000000000010100DD +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000002A5 +:10A9B0000200000001010101010101010101010189 +:10A9C000020202020202020202020102010101006D +:10A9D0000000000000000000000000000000000077 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000244 +:10AA10000202020202020000000102010202020020 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000002F4 +:10AA600002020201010101000000000000010100DA +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000002A4 +:10AAB0000202020200000000010101010101010186 +:10AAC000020202020202020202020201010101006C +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000243 +:10AB1000020202020202000000010202020202001E +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000002F3 +:10AB600002020202020101010000010000010100D5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000002A3 +:10ABB0000202020202020202000000000001000183 +:10ABC000020202020202020202020201010201006A +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000242 +:10AC1000020202020202000001020202020202001B +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000002F2 +:10AC600002020202020201010101010000010100D1 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000002A2 +:10ACB0000202020202020202020202020200020177 +:10ACC000020202020202020202020201010200006A +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000241 +:10AD10000202020202020100020202020202020018 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000002F1 +:10AD600002020202020202010101010100010100CE +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000002A1 +:10ADB0000202020202020202020202020202020174 +:10ADC000010202020202020202020201010200006A +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000240 +:10AE10000202020202020200020202020202020016 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000002F0 +:10AE600002020202020202020101010100020100CB +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000002A0 +:10AEB0000202020202020202020202020202020173 +:10AEC0000102020202020202020202010102000069 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF0000000000000000000000000000000000023F +:10AF10000202020202020202020202020202020013 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000002EF +:10AF600002020202020202020202020100020200C6 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000202020202020202020202020202020172 +:10AFC0000102020202020201020202010102000069 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B00000000000000000000000000000000000023E +:10B010000202020202020202010102020102020015 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000002EE +:10B0600002020202020202020202020200020200C4 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000202020202020202020202020202020171 +:10B0C000010202010201010102020201010100006C +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000023D +:10B110000202020202020202010102020102020014 +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000002ED +:10B1600002020202020202020202020200020200C3 +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B0000202020202020202020202020202020170 +:10B1C000010101010101010101020201010100006F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000013D +:10B21000010101010101010102020101020201001B +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000002EC +:10B2600002020202020202020202020200020200C2 +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000020202020202020202020202020202016F +:10B2C0000101010101010101010101010101000070 +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000023B +:10B31000020202020202020202020202020202000F +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000002EB +:10B3600002020202020202020202020202020200BF +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000020202020202020202020202020202016E +:10B3C000010101010101010101010101010100006F +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000100002B +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000002EA +:10B4600002020202020202020202020202020200BE +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000020202020202020202020202020202006E +:10B4C0000101010101010101010101000001000070 +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B510000000000000000000000000000002000029 +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000001EA +:10B5600001010101010101010101010101010100CC +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000020202020202020202020202020202006D +:10B5C000010101010101010101010100000100006F +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B600000000000000000000000000000000000139 +:10B61000010101010101010101010101010101001B +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000001E9 +:10B6600001010101010101010101010101010100CB +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000020202020202020202020202020202006C +:10B6C000010101010101010101010100000000006F +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000138 +:10B71000010101010101010101010101010101001A +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000001E8 +:10B7600001010101010101010101010101010100CA +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B000020202020202020202020202020202006B +:10B7C000010101010101010101010100000000006E +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000137 +:10B810000101010101010101010101010101010019 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000001E7 +:10B8600001010101010101010101010101010100C9 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B000020202020202020202020202020200006C +:10B8C000000101010101010101010100000000006E +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000136 +:10B910000101010101010101010101010101010018 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000001E6 +:10B9600001010101010101010101010101010100C8 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B000000202020202020202020202020200006D +:10B9C000000101010101010101010100000000006D +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000135 +:10BA10000101010101010101010101010101010017 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000002E4 +:10BA600002020202020202020202020202020200B8 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000002020202020000020200000000000078 +:10BAC000000101010101000001010000000000006F +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000233 +:10BB10000202020202020202020202020202020007 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000002E3 +:10BB600002020202020202020202020202020200B7 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000001E66 +:10BCC000000000000000000101010101010101016B +:10BCD000010101010201010000000000000000005C +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000010000000000000000D2 +:10BD700000000000000001000000000000000000C2 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB000000000000000000001010101010101017B +:10BDC0000101010101010102010101010101010162 +:10BDD0000201010202020100000000000000000058 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000010000000000000000D1 +:10BE700000000000000001000000000000000000C1 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB000000000000000000000010101000101017C +:10BEC0000101010101010102020101010101010160 +:10BED0000202010201020100000000000000000057 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000010000000000000000D0 +:10BF700000000000010001000000000000000000BF +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB000000000000000000000010101000101017B +:10BFC000010101010101010202020101010101015E +:10BFD0000202020201010100000000000000000056 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000010100000000000000CE +:10C0700000000000010101000000000000000000BD +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000002000101010201010176 +:10C0C0000101010101010102020202020101020259 +:10C0D0000202020101010100000000000000000056 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000010100010100000000CB +:10C1700000000000010101000000000000000000BC +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B0000000000000000002000001000201010177 +:10C1C0000101010101010102020202020202020256 +:10C1D0000102020101010100000000000000000056 +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000020101010101000000C7 +:10C2700000000000010101000000000000000000BB +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B0000000000000000002000001000200010177 +:10C2C0000001010101010102020202020202020256 +:10C2D0000102020101010100000000000000000055 +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000000001D +:10C32000000000000000010000000000000000000C +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000020101010101010000C5 +:10C3700000000000010101000000000000000000BA +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B0000000000000000002000000000202010175 +:10C3C0000001000100010102020202020202020257 +:10C3D0000101020101010100000000000000000055 +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000001010000000000000000000A +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000020201010101010000C3 +:10C4700000000000010101000000000000000000B9 +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B0000000000000000002000000000202000076 +:10C4C0000001000100010102020202020202020256 +:10C4D0000101010101010100000000000000000055 +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000100000000000000001A +:10C520000000000001010100000000000000000008 +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000020201010101010000C2 +:10C5700000000000010101000000000000000000B8 +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B0000000000000000002000000000202000075 +:10C5C0000200020000010002020202020202020254 +:10C5D0000101010101010100000000000000000054 +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C610000000000000000001010100000000000017 +:10C620000000000001010100000000000000000007 +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000020202020201010000BE +:10C6700000000000010101000000000000000000B7 +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B0000000000000000002020200000002000072 +:10C6C0000200020002010001020202020202020153 +:10C6D0000101010101010000000000000000000054 +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000002010101000000000014 +:10C720000001000001010100000000000000000005 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000020202020202010000BC +:10C7700000000000020102000000000000000000B4 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B000000000000000000202020200000200006F +:10C7C0000200020002010201020202020202010151 +:10C7D0000101010101010000000000000000000053 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000002020101000000000012 +:10C820000001000001010100000000000000000004 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000020202020202020000BA +:10C8700000000000020202000000000000000000B2 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B000000000000000000202020200000200006E +:10C8C0000202020002000201010102020202010151 +:10C8D0000101010100010000000000000000000053 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000002020201000000000010 +:10C920000001000101010100000000000000000002 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000020202020202020000B9 +:10C9700000000000020202000000000000000000B1 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B000000000000000000202020200000202006B +:10C9C000020202020202020101010101020101014F +:10C9D0000101010100000000000000000000000053 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA1000000000000000000202020200010000000D +:10CA20000001000102010100000000000000000000 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000020202020202020001B7 +:10CA700000010000020202000000000000000000AF +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB000000000000000000002020200000202026A +:10CAC0000202020202020200010101010101010150 +:10CAD0000101010000000000000000000000000053 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB1000000000000000000202020201010000000B +:10CB200000020001020202000000000000000000FC +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000020202020202020101B5 +:10CB700000010000020202000000000000000000AE +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000020202020002020267 +:10CBC000020202020202020001010101010101014F +:10CBD0000001010000000000000000000000000053 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000002020202020200000107 +:10CC200000020002020202000000000000000000FA +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000020202020202020202B2 +:10CC700001020000020202000000000000000000AB +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000020202020000020268 +:10CCC000020202020202020001010101010101014E +:10CCD0000001010000000000000000000000000052 +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD10000000000000000002020202020201000105 +:10CD200000020002020202000000000000000000F9 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000020202020202020202B1 +:10CD700002020000020202000000000000000000A9 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000020202020000020267 +:10CDC0000002000202020200010101010101010151 +:10CDD0000000010000000000000000000000000052 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000002020202020202000202 +:10CE200000020002020202000000000000000000F8 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000020202020202020202B0 +:10CE700002020000020202000000000000000000A8 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000020202020000020266 +:10CEC0000002000200020200010101010101010152 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF100000000000000000020202020202020202FF +:10CF200000020202020202000000000000000000F5 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000020202020202020202AF +:10CF700002020202020202000000000000000000A3 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000020202020000020265 +:10CFC0000002000200020001010101010101010053 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D0100000000000000000020202020202020202FE +:10D0200002020101010202000000000000000000F5 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000020202020202020202AE +:10D0700002020202020202000000000000000000A2 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000202020000020266 +:10D0C0000002000200020001010101010101000053 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D1100000000000000000020202020202020202FD +:10D1200002010202020202000000000000000000F2 +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000010101010101010101B6 +:10D1700001010101010101000000000000000000A8 +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B0000000000000000000000002020000020267 +:10D1C0000002000200020001000001010101000054 +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000020000000000000000000000000000FC +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000020202020202020202AC +:10D2700002020202020202000000000000000000A0 +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B0000000000000000000000002020000020266 +:10D2C0000002000200020001000000000100000056 +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000010101010101010101B4 +:10D3700001010101010101000000000000000000A6 +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B0000000000000000000000000020000020267 +:10D3C000000000000002000000000000000000005B +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D410000000000000000001010101010101010103 +:10D4200001010101010101000000000000000000F5 +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000010101010101010101B3 +:10D4700001010101010101000000000000000000A5 +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000002000000006A +:10D4C000000000000002000000000000000000005A +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D510000000000000000001010101010101010102 +:10D5200001010101010101000000000000000000F4 +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000010101010101010101B2 +:10D5700001010101010101000000000000000000A4 +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D610000000000000000001010101010101010101 +:10D6200001010101010101000000000000000000F3 +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000010101010101010101B1 +:10D6700001010101010101000000000000000000A3 +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000001010101010101010100 +:10D7200001010101010101000000000000000000F2 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000010101010101010101B0 +:10D7700001010101010101000000000000000000A2 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D8100000000000000000010101010101010101FF +:10D8200001010101010101000000000000000000F1 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000020202020202020202A6 +:10D87000020202020202020000000000000000009A +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D9100000000000000000020202020202020202F5 +:10D9200002020202020202000000000000000000E9 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000020202020202020202A5 +:10D970000202020202020200000000000000000099 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC000000000000000001E000000000000000038 +:10DAD0000000000001000001010000010001000041 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000020200000000000000000150 +:10DBD000010101010100000101000101010100003A +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC7000000000000002020000010000000000009F +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC000000000000002020000000000000000014F +:10DCD0000101010101010101010001010101000037 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD7000000100000002020000010000010001009B +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC000000000000002020000000000000000014E +:10DDD0000101010101010101010001010101000036 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE7000000100000002020000010000010001009A +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC000000000000002020000000000000000014D +:10DED0000101010101020201010101010101000032 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF70000001000000020200000100000100010099 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000020202020000000000000247 +:10DFD0000101010101020201010101010101000031 +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E070000001000000020200000100010101010096 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000010102020000000000000248 +:10E0D000020101010102020201010101010100002E +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000001000000EE +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E170000101000100010100000101010101010094 +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C0000000000000010101010000000000000249 +:10E1D000020102010202020201010101010100002B +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000001000000ED +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E270000101000100010100000101010101010093 +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C0000000000000010101010000000000000248 +:10E2D0000202020202020202020101010101000027 +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000010000000000000000000001000000EB +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E370000101010100010100000101010101010091 +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C0000000000001010101010000000100000245 +:10E3D0000202020202020202020101010101000026 +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000010000010000000001000001000000E8 +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E470000101010100010100000101010101010090 +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C0000000000001010101010000000100000244 +:10E4D0000202020202020202020102020102000022 +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000010000010000000001000001000100E6 +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000010101010001010000010101010101008F +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C0000000000001010101010000000100010242 +:10E5D0000202020202020202020102020102000021 +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000010000010000000001000001000100E5 +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000010201010101010101010101010101008A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C0000000010000000000010100010101010241 +:10E6D000020202020202020202010202020200001F +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200001010000010000000001000001000100E3 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000001A8 +:10E770000202010101010101010201010101010087 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000010101010101010240 +:10E7D000020202020202020202020202020200001D +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200001010000010000000001000101010100E0 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000001A7 +:10E870000202020201010101010201010201020082 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000101010101010240 +:10E8D000020202020202020202020202020200001C +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200001010001020000000001000101010100DD +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000002A5 +:10E97000020202020102020101020202020202007C +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C000000100010000000000010101010101023D +:10E9D000020202020202020202020202020200001B +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200001020001020101000001000101010100D9 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000002A4 +:10EA70000202020202020202010202020202020079 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC000000100010000000000010101010101023C +:10EAD000020202020202020202020202020200001A +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200002020101020202000001010102010100D2 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000002A3 +:10EB70000202020202020202020202020202020077 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC000010100010000000000010101010101023A +:10EBD000020202020201010202020202020200001B +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200002020101020202000002010102010100D0 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000002A2 +:10EC70000202020202020202020202020202020076 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC000010100010000000000010101000101023A +:10ECD000020202020201010202020202020200001A +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000002F1 +:10ED200002020202020202000002010102010200CC +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000002A1 +:10ED70000202020202020202020202020202020075 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000142 +:10EDD000010202020201010102020202020200001B +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000002F0 +:10EE200002020202020202010002010202020200C8 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000002A0 +:10EE70000202020202020202020202020202020074 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000141 +:10EED000010101010101010101020202020200001F +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000002EF +:10EF200002020202020202020002020202020200C5 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF6000000000000000000000000000000000029F +:10EF70000202020202020202020202020202020073 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC000000000000000000000000000020000013E +:10EFD0000101010101010101010201010201010020 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000002EE +:10F0200002020202020202020102020202020200C3 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F06000000000000000000000000000000000029E +:10F070000202020202020202020202020202020072 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B000000000000000000000000000000000024E +:10F0C0000202000202020202020202020202020123 +:10F0D0000101010101010101010101010101010021 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000002ED +:10F1200002020202010101020202020202020200C4 +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000029D +:10F170000202020202020202020202020202020071 +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000024D +:10F1C0000202020202020202020202020202020120 +:10F1D0000101010101010101010101010101010020 +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000002EC +:10F2200002020202020202020202020202020200C0 +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000029C +:10F270000202020202020202020202020202020070 +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000024C +:10F2C000020202020202020202020202020202011F +:10F2D000010101010101010101010101010101001F +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000001EC +:10F3200001010101010101010101010101010100CE +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000029B +:10F37000020202020202020202020202020202006F +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000024B +:10F3C000020202020202020202020202020202011E +:10F3D000010101010101010101010101010101001E +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000001EB +:10F4200001010101010101010101010101010100CD +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000019B +:10F47000010101010101010101010101010101007D +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000024A +:10F4C000020202020202020202020202020202011D +:10F4D000010101010101010101010101010101001D +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000001EA +:10F5200001010101010101010101010101010100CC +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000019A +:10F57000010101010101010101010101010101007C +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B0000000000000000000000000000000000249 +:10F5C000020202020202020202020202020202011C +:10F5D000010101010101010101010101010101001C +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000001E9 +:10F6200001010101010101010101010101010100CB +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F660000000000000000000000000000000000199 +:10F67000010101010101010101010101010101007B +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B0000000000000000000000000000000000248 +:10F6C000020202020202020202020202020202011B +:10F6D000010101010101010101010101010101001B +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000002E7 +:10F7200002020202020202020202020202020200BB +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000297 +:10F77000020202020202020202020202020202006B +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000247 +:10F7C000020202020202020202020202020202001B +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000001E1A +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000200D5 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000000000000000000010000000036 +:10F9D0000000000000000000000001000001000025 +:10F9E0000100010000010000000000000000000014 +:10F9F0000000000000000000000000000000000007 +:10FA000000000000000000000000000000000000F6 +:10FA100000000000000000000000000000000000E6 +:10FA200000000000000000000000000000000200D4 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC0000000000000000000000000010000000035 +:10FAD000000000000001000000010101010100011F +:10FAE0000101010000010000000000000000000012 +:10FAF0000000000000000000000000000000000006 +:10FB000000000000000000000000000000000000F5 +:10FB100000000000000000000000000000000000E5 +:10FB200000000000000000000000000000000200D3 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000055 +:10FBB0000000000000000000000000000000000045 +:10FBC0000000000000000000000000010000020032 +:10FBD0000000000001010002010201010101010118 +:10FBE0000101010100010000000000000000000010 +:10FBF0000000000000000000000000000000000005 +:10FC000000000000000000000000000000000000F4 +:10FC100000000000000000000000000000000000E4 +:10FC200000000000000000000000000000000200D2 +:10FC300000000000000100000000000000000000C3 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000000000000000000000000010000020031 +:10FCD0000000000101010002010202010102020113 +:10FCE000020101010101000000000000000000000D +:10FCF0000000000000000000000000000000000004 +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200000000000000000000000000000000200D1 +:10FD300000000000000100000000000000000000C2 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000010000010031 +:10FDD000000000010101000202020202010202020F +:10FDE000020102010101000000000000000000000B +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200000000000000000000000000000000200D0 +:10FE300000000000000101000000000000000000C0 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000010000000000000000000071 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000010000010030 +:10FED000000000010101000202020202020202020D +:10FEE000020102010101000000000000000000000A +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000100D0 +:10FF300000000000010101000000000000000000BE +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000010000000000000000000070 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC000000000000000000000000001000001002F +:10FFD000000000010101000202020202020202020C +:10FFE0000201020101010000000000000000000009 +:10FFF0000000000000000000000000000000000001 +:02000002B0004C +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000010000000000000100CE +:1000300000000000010101000000000000000000BD +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:10008000000000000001010000000000000000006E +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C000000000000000000001000001000001002D +:1000D000000000010101010202020202020202020A +:1000E0000201020101010000000000000000000008 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000010000000100000100CC +:1001300000000000010101000000000000000000BC +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000002007D +:10018000000000000101010000000000000000006C +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000001000000000001002D +:1001D0000101000101010102020202020202020207 +:1001E0000202020201010000000000000000000005 +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000020000010100000100C9 +:1002300000000000010101000000000000000000BB +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000002007C +:100280000000020001010100000000000000000069 +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000001000000000000012C +:1002D0000101000101010102020202020202020206 +:1002E0000202020201010000000000000000000004 +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000020001010101020100C4 +:1003300002000000010101000000000000000000B8 +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000002007B +:100380000000020001010100000000000000000068 +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000001000000000000002C +:1003D0000101000101010102020202020202020205 +:1003E0000202020201020000000000000000000002 +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000020102020201020100BF +:1004300002000000010101000000000000000000B7 +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000002007A +:100480000000010101010100000000000000000067 +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000001000000000000002B +:1004D0000001010101010102020202020202020204 +:1004E0000202020202020000000000000000000000 +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000020102020202010100BE +:1005300002000000010201000000000000000000B5 +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:100570000000000000000000000000000002020077 +:100580000200010101010100000000000000000064 +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C0000000000000000000010000000001000029 +:1005D0000001010101010102020202020202020203 +:1005E00002020202020200000000000000000000FF +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000020202020202010200BB +:1006300001000201020202000000000000000000B0 +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:100670000000000000000000010000000002010076 +:100680000200010101010100000000000000000063 +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C0000000000000000000010000000001000028 +:1006D0000001010101010102020202020202020202 +:1006E00002020202020200000000000000000000FE +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000020202020202020200B9 +:1007300001000201020202000000000000000000AF +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000010000010201010073 +:100780000101010101010100000000000000000062 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000010000000001000027 +:1007D0000001010101010102020102020202020202 +:1007E00002020202020200000000000000000000FD +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000020202020202020200B8 +:1008300001000101020202000000000000000000AF +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000001010200010101010070 +:100880000101010101020100000000000000000060 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000020000000001000025 +:1008D0000000010202020101020102020201010202 +:1008E00001020202020200000000000000000000FD +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000020202020202020202B5 +:1009300002000102020202000000000000000000AC +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:10097000000000000000000202010001010101006E +:10098000010101010202020000000000000000005D +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000020000020000000023 +:1009D0000000000202020101010101010201010106 +:1009E00001020102020200000000000000000000FD +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000020202020202020202B4 +:100A300002000202020202000000000000000000AA +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A7000000000000000000202020102010101006A +:100A8000010102020202020000000000000000005A +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000020001020000000021 +:100AD0000000000202020101010101010101010106 +:100AE00001020102020200000000000000000000FC +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000010201010101010202B9 +:100B300002020202020202000000000000000000A7 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000002020202020202020164 +:100B80000202020202020200000000000000000057 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000020001020000000020 +:100BD0000000000202020201010101010101010104 +:100BE00001020101020200000000000000000000FC +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000000000000000000000E4 +:100C100000000000000000000000000000000000D4 +:100C200000000000000000020202020202020202B2 +:100C300002020202020202000000000000000000A6 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000002020202020202020262 +:100C80000202020202020200000000000000000056 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC000000000000000000002000102010002001C +:100CD0000002000202020201010101010101010101 +:100CE00001010101020200000000000000000000FC +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000000E3 +:100D100000000000000000000000000000000000D3 +:100D200000000000000000000000000000000000C3 +:100D300000000000000000000000000000000000B3 +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000002020202020202020261 +:100D80000202020202020200000000000000000055 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000020102020102020017 +:100DD00000020202020202010100010101010101FF +:100DE00001010101010101000000000000000000FC +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000002020202020202020260 +:100E80000202020202020200000000000000000054 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000002020202020002020014 +:100ED00002020202020202010100010101000001FE +:100EE00000010101010101000000000000000000FC +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000002020102020202020260 +:100F80000202020202020200000000000000000053 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000002020202020202020011 +:100FD00002020202020202010101010101010101FA +:100FE00001010101010101000000000000000000FA +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000010101010101010101B7 +:1010300001010101010101000000000000000000A9 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000001010101010101010167 +:101080000101010101010100000000000000000059 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C000000000000000000202020202020202020E +:1010D00002020202020202010101010101010101F9 +:1010E00001010101010101000000000000000000F9 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000010101010101010101B6 +:1011300001010101010101000000000000000000A8 +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000202020202020202025D +:101180000202020202020200000000000000000051 +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000202020202020202020D +:1011D00002020202020202010101010101010101F8 +:1011E00001010101010101000000000000000000F8 +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000010101010101010101B5 +:1012300001010101010101000000000000000000A7 +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000020000000000006C +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000202020202020202020C +:1012D00002020202020202010101010101010101F7 +:1012E00001010101010101000000000000000000F7 +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000010101010101010101B4 +:1013300001010101010101000000000000000000A6 +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:101370000000000000000001010101010101010164 +:101380000101010101010100000000000000000056 +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000202020202020202020B +:1013D00002020202020202010101010101010101F6 +:1013E00001010101010101000000000000000000F6 +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000010101010101010101B3 +:1014300001010101010101000000000000000000A5 +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:101470000000000000000001010101010101010163 +:101480000101010101010100000000000000000055 +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000202020202020202020A +:1014D00002020202020202010101010101010101F5 +:1014E00001010101010101000000000000000000F5 +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000020202020202020202A9 +:10153000020202020202020000000000000000009D +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:101570000000000000000002020202020202020259 +:10158000020202020202020000000000000000004D +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C0000000000000000002020202020202020209 +:1015D00002020202020202000000000000000000FD +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000001E0000000000000002EA +:1016E00000000000000000010001000001000000F7 +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000000000000000000019 +:1017D0000101000100000000000000000000000204 +:1017E00000000000010101010001010101010000F0 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D0000101010101000000000000000000000201 +:1018E00000010001010101010101010101010000EC +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D00001010101010000000000010000000002FF +:1019E00001010101020101010101010101010000E8 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000002000000000000000000010053 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD00001010101010000010001010000000002FC +:101AE00002010101020101010101020201010000E4 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000002000000010000000000010051 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD00000010101010100010001010000000002FB +:101BE00002020202020201020102020202010000DC +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000000000000000B4 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000002000000010000000000010050 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000000000000000000000034 +:101CB0000000000000000000000000000000000024 +:101CC0000000000000000000000000000000000014 +:101CD00000000000000100010001010000000102FD +:101CE00002020202020201020102020202010000DB +:101CF00000000000000000000000000000000000E4 +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000000C3 +:101D200000000000000000000000000000000000B3 +:101D300000000000000000000000000000000000A3 +:101D40000000000000000000000000000000000093 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000073 +:101D70000000000000000000000000000000000063 +:101D8000000000000200000001000000000001004F +:101D90000000000000000000000000000000000043 +:101DA0000000000000000000000000000000000033 +:101DB0000000000000000000000000000000000023 +:101DC0000000000000000000000000000000000013 +:101DD00000000000000100010001010001000102FB +:101DE00002020202020202020102020202020000D8 +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E300000000000000000000000000000000100A1 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E8000000000000100010001000000000101004D +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000000000000000000022 +:101EC0000000000000000000000000000000000012 +:101ED00000000000000100010101010101000102F8 +:101EE00002020202020202020102020202020000D7 +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000000000000000000B1 +:101F3000000000000000000001000000000001009F +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F8000000000000100010001000000000101004C +:101F90000000000000000000000000000000000041 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000000000000000000021 +:101FC0000000000000000000000000000000000011 +:101FD00000000000000101010101010101010102F5 +:101FE00002020202020202020202020202020000D5 +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000000000000000000B0 +:10203000000000000000010001000000000101009C +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:10208000000000000100010001000000000101004B +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000000000000000010 +:1020D00000000000000101010101000101010102F5 +:1020E00002020202020202020202020202020000D4 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000010001000000000101009B +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:102180000001000001000101010000000001010048 +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000101010101000101010102F4 +:1021E00002020202020202020202020202020000D3 +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000010001000000000101009A +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000015D +:102280000001000001000101010000000101010046 +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00000000000000001000100000101010102F6 +:1022E00002020202020202020202020202020000D2 +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:102330000000000000000100010100000101010097 +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000015C +:102380000101000101000101010100000101010042 +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00000000000000001000100000001010101F7 +:1023E00002020202020202020202020202020000D1 +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000001AB +:102430000000000000000100010100000101010096 +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000025A +:10248000010101010101010102010000010102003D +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000001000100000001010101F6 +:1024E00002020202020202020202020202020000D0 +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000002A9 +:102530000001000001000101010100000101010092 +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:102570000000000000000000000000000000000259 +:102580000202010102010201020101000102020036 +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000001000100000000010101F6 +:1025E00002020202010202020202010102020000D2 +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000002A8 +:102630000001000001010101010100000101010090 +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:102670000000000000000000000000000000000258 +:102680000202020202010202020101000102020032 +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000001000100000000010101F5 +:1026E00001020202010202020202010102020000D2 +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000002A7 +:10273000000100010201010101010000010101008D +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000257 +:10278000020202020202020202020101020202002D +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000001000100000000010201F3 +:1027E00001010101010102010201010101020000D8 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000002A6 +:102830000001000102010201020101000102020087 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000256 +:10288000020202020202020202020201020202002B +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000202020202020002020201E5 +:1028E00001010101010101010201010101010000D9 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000002A5 +:102930000102000102010201020201000202020082 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000255 +:102980000202020202020202020202020202020029 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00002000000000202020202020002020201E2 +:1029E00001010101010101010101010101010000D9 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000002A4 +:102A3000020201020202020202020100020202007C +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000254 +:102A80000202020202020202020202020202020028 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00002020202020202020202020002020201D9 +:102AE00001010101010101010101010101010000D8 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000001A4 +:102B30000202020202020202020202000202020079 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000253 +:102B80000202020202020202020202020202020027 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00002020202020202020202020202020201D6 +:102BE00001010101010101010101010101010100D6 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000002A2 +:102C30000202020201020202020202000202020079 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000153 +:102C80000101010101010101010102020201010032 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000202 +:102CD00002020202020202020202020202020200D6 +:102CE00001010101010101010101010101010100D5 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000202020202020202020202000202020077 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000152 +:102D80000202020201020202020201010102020029 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000201 +:102DD00002020202020202020202020202020000D7 +:102DE00001010101000101010101000001010100D7 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000202020200020202020202020202020076 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000250 +:102E8000000000000200000000000202020000003A +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000200 +:102ED00002020202020000000000000200000000E6 +:102EE00000010101000101010101000001010100D7 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000001A0 +:102F30000101010101010101010101010101010082 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F7000000000000000000000000000000000024F +:102F8000000000000200000000000000000000003F +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC00000000000000000000000000000000002FF +:102FD00002020202020202020202020202020201D2 +:102FE00001010101010101010101010101010100D2 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:10302000000000000000000000000000000000019F +:103030000101010101010101010101010101010081 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C00000000000000000000000000000000002FE +:1030D00002020202020202020202020202020201D1 +:1030E00001010101010101010101010101010100D1 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000019E +:103130000101010101010101010101010101010080 +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000014E +:103180000101010101010101010101010101010030 +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000002FD +:1031D00002020202020202020202020202020201D0 +:1031E00001010101010101010101010101010100D0 +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000019D +:10323000010101010101010101010101010101007F +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000014D +:10328000010101010101010101010101010101002F +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000002FC +:1032D00002020202020202020202020202020201CF +:1032E00001010101010101010101010101010100CF +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000029B +:10333000020202020202020202020202020202006F +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000024B +:10338000020202020202020202020202020202001F +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000002FB +:1033D00002020202020202020202020202020200CF +:1033E00000000000000000000000000000000000DD +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:0F34D000000000000000000000000000000000ED +:00000001FF diff --git a/firmware/imx/epdc_E60_V220.fw.ihex b/firmware/imx/epdc_E60_V220.fw.ihex new file mode 100644 index 000000000000..812cbfbc270d --- /dev/null +++ b/firmware/imx/epdc_E60_V220.fw.ihex @@ -0,0 +1,77569 @@ +:10000000BD611693236A0100BC04000007060500C9 +:100010000304021D3C180085000000004000001190 +:100020004700000100040D00FFFC00000000005428 +:10003000000306090C0F1215181B1E21262B302851 +:1000400000000000000000086B070000000000E84E +:1000500015090000000000C8A20D0000000000A863 +:100060002F1200000000009800000000000000A017 +:10007000F3000000000000A8CA010000000000B06A +:1000800081020000000000B838030000000000C03A +:10009000CF030000000000C844040000000000D0AE +:1000A000B1040000000000D816050000000000E0C8 +:1000B00073050000000000E8D0050000000000F01B +:1000C0002D060000000000F88E0600000000000071 +:1000D000F8060000000000F300000000000000012E +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010198 +:100850000101010101010101010101010101010188 +:100860000101010101010101010101010101010178 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010118 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000001010101010101010101010101010101D2 +:100E100001010101010101010101010101010101C2 +:100E200001010101010101010101010101010101B2 +:100E300001010101010101010101010101010101A2 +:100E40000101010101010101010101010101010192 +:100E50000101010101010101010101010101010182 +:100E60000101010101010101010101010101010172 +:100E70000101010101010101010101010101010162 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101010101010101010101E2 +:100F000001010101010101010101010101010101D1 +:100F100001010101010101010101010101010101C1 +:100F200001010101010101010101010101010101B1 +:100F300001010101010101010101010101010101A1 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000101010101010101010101010101010171 +:100F70000101010101010101010101010101010161 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101010101010101010101E1 +:1010000001010101010101010101010101010101D0 +:1010100001010101010101010101010101010101C0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000101010101010101010101010101010170 +:101070000101010101010101010101010101010160 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010101010101BF +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:10116000010101010101010101010101010101016F +:10117000010101010101010101010101010101015F +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010101010101BE +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101016E +:10127000010101010101010101010101010101015E +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101010101010101010101BD +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101016D +:10137000010101010101010101010101010101015D +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101016C +:10147000010101010101010101010101010101015C +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101018B +:10155000010101010101010101010101010101017B +:10156000010101010101010101010101010101016B +:10157000010101010101010101010101010101015B +:10158000010101010101010101010101010101014B +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010101010101010101019A +:10164000010101010101010101010101010101018A +:10165000010101010101010101010101010101017A +:10166000010101010101010101010101010101016A +:10167000010101010101010101010101010101015A +:10168000010101010101010101010101010101014A +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010101010101010101010157 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101014B +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:10267000010101010101010101010101010101014A +:10268000010101010101010101010101010101013A +:10269000010101010101010101010101010101012A +:1026A000010101010101010101010101010101011A +:1026B000010101010101010101010101010101010A +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101010101010101010159 +:102770000101010101010101010101010101010149 +:102780000101010101010101010101010101010139 +:102790000101010101010101010101010101010129 +:1027A0000101010101010101010101010101010119 +:1027B0000101010101010101010101010101010109 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010147 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010101010127 +:1029A0000101010101010101010101010101010117 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010146 +:102A80000101010101010101010101010101010136 +:102A90000101010101010101010101010101010126 +:102AA0000101010101010101010101010101010116 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010165 +:102B60000101010101010101010101010101010155 +:102B70000101010101010101010101010101010145 +:102B80000101010101010101010101010101010135 +:102B90000101010101010101010101010101010125 +:102BA0000101010101010101010101010101010115 +:102BB0000101010101010101010101010101010105 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101010101010101010101E5 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000101010101010101010101010101010164 +:102C60000101010101010101010101010101010154 +:102C70000101010101010101010101010101010144 +:102C80000101010101010101010101010101010134 +:102C90000101010101010101010101010101010124 +:102CA0000101010101010101010101010101010114 +:102CB0000101010101010101010101010101010104 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010173 +:102D50000101010101010101010101010101010163 +:102D60000101010101010101010101010101010153 +:102D70000101010101010101010101010101010143 +:102D80000101010101010101010101010101010133 +:102D90000101010101010101010101010101010123 +:102DA0000101010101010101010101010101010113 +:102DB0000101010101010101010101010101010103 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010132 +:102E90000101010101010101010101010101010122 +:102EA0000101010101010101010101010101010112 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010101D2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:10317000010101010101010101010101010101013F +:10318000010101010101010101010101010101012F +:10319000010101010101010101010101010101011F +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000010101010101010101010101010101014E +:10327000010101010101010101010101010101013E +:10328000010101010101010101010101010101012E +:10329000010101010101010101010101010101011E +:1032A000010101010101010101010101010101010E +:1032B00001010101010101010101010101010101FE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000010101010101010101010101010101011D +:1033A000010101010101010101010101010101010D +:1033B00001010101010101010101010101010101FD +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000010101010101010101010101010101017C +:10344000010101010101010101010101010101016C +:10345000010101010101010101010101010101015C +:10346000010101010101010101010101010101014C +:10347000010101010101010101010101010101013C +:10348000010101010101010101010101010101012C +:10349000010101010101010101010101010101011C +:1034A000010101010101010101010101010101010C +:1034B00001010101010101010101010101010101FC +:1034C00001010101010101010101010101010101EC +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101014A +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A000010101010101010101010101010101010A +:1036B00001010101010101010101010101010101FA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010101F8 +:1038C00001010101010101010101010101010101E8 +:1038D00001010101010101010101010101010100D9 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000002E2 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202029E +:10430000020202020202020202020202020202028D +:10431000020202020202020202020202020202027D +:10432000020202020202020202020202020202026D +:10433000020202020202020202020202020202025D +:10434000020202020202020202020202020202024D +:10435000020202020202020202020202020202023D +:10436000020202020202020202020202020202022D +:10437000020202020202020202020202020202021D +:10438000020202020202020202020202020202020D +:1043900002020202020202020202020202020202FD +:1043A00002020202020202020202020202020202ED +:1043B00002020202020202020202020202020202DD +:1043C00002020202020202020202020202020202CD +:1043D00002020202020202020202020202020202BD +:1043E00002020202020202020202020202020202AD +:1043F000020202020202020202020202020202029D +:10440000020202020202020202020202020202028C +:10441000020202020202020202020202020202027C +:10442000020202020202020202020202020202026C +:10443000020202020202020202020202020202025C +:10444000020202020202020202020202020202024C +:10445000020202020202020202020202020202023C +:10446000020202020202020202020202020202022C +:10447000020202020202020202020202020202021C +:10448000020202020202020202020202020202020C +:1044900002020202020202020202020202020202FC +:1044A00002020202020202020202020202020202EC +:1044B00002020202020202020202020202020202DC +:1044C00002020202020202020202020202020202CC +:1044D00002020202020202020202020202020202BC +:1044E00002020202020202020202020202020202AC +:1044F000020202020202020202020202020202029C +:10450000020202020202020202020202020202028B +:10451000020202020202020202020202020202027B +:10452000020202020202020202020202020202026B +:10453000020202020202020202020202020202025B +:10454000020202020202020202020202020202024B +:10455000020202020202020202020202020202023B +:10456000020202020202020202020202020202022B +:10457000020202020202020202020202020202021B +:10458000020202020202020202020202020202020B +:1045900002020202020202020202020202020202FB +:1045A00002020202020202020202020202020202EB +:1045B00002020202020202020202020202020202DB +:1045C00002020202020202020202020202020202CB +:1045D00002020202020202020202020202020202BB +:1045E00002020202020202020202020202020202AB +:1045F000020202020202020202020202020202029B +:10460000020202020202020202020202020202028A +:10461000020202020202020202020202020202027A +:10462000020202020202020202020202020202026A +:10463000020202020202020202020202020202025A +:10464000020202020202020202020202020202024A +:10465000020202020202020202020202020202023A +:10466000020202020202020202020202020202022A +:10467000020202020202020202020202020202021A +:10468000020202020202020202020202020202020A +:1046900002020202020202020202020202020202FA +:1046A00002020202020202020202020202020202EA +:1046B00002020202020202020202020202020202DA +:1046C00002020202020202020202020202020202CA +:1046D00002020202020202020202020202020202BA +:1046E00002020202020202020202020202020202AA +:1046F000020202020202020202020202020202029A +:104700000202020202020202020202020202020289 +:104710000202020202020202020202020202020279 +:104720000202020202020202020202020202020269 +:104730000202020202020202020202020202020259 +:104740000202020202020202020202020202020249 +:104750000202020202020202020202020202020239 +:104760000202020202020202020202020202020229 +:104770000202020202020202020202020202020219 +:104780000202020202020202020202020202020209 +:1047900002020202020202020202020202020202F9 +:1047A00002020202020202020202020202020202E9 +:1047B00002020202020202020202020202020202D9 +:1047C00002020202020202020202020202020202C9 +:1047D00002020202020202020202020202020202B9 +:1047E00002020202020202020202020202020202A9 +:1047F0000202020202020202020202020202020299 +:104800000202020202020202020202020202020288 +:104810000202020202020202020202020202020278 +:104820000202020202020202020202020202020268 +:104830000202020202020202020202020202020258 +:104840000202020202020202020202020202020248 +:104850000202020202020202020202020202020238 +:104860000202020202020202020202020202020228 +:104870000202020202020202020202020202020218 +:104880000202020202020202020202020202020208 +:1048900002020202020202020202020202020202F8 +:1048A00002020202020202020202020202020202E8 +:1048B00002020202020202020202020202020202D8 +:1048C00002020202020202020202020202020202C8 +:1048D00002020202020202020202020202020202B8 +:1048E00002020202020202020202020202020202A8 +:1048F0000202020202020202020202020202020298 +:104900000202020202020202020202020202020287 +:104910000202020202020202020202020202020277 +:104920000202020202020202020202020202020267 +:104930000202020202020202020202020202020257 +:104940000202020202020202020202020202020247 +:104950000202020202020202020202020202020237 +:104960000202020202020202020202020202020227 +:104970000202020202020202020202020202020217 +:104980000202020202020202020202020202020207 +:1049900002020202020202020202020202020202F7 +:1049A00002020202020202020202020202020202E7 +:1049B00002020202020202020202020202020202D7 +:1049C00002020202020202020202020202020202C7 +:1049D00002020202020202020202020202020202B7 +:1049E00002020202020202020202020202020202A7 +:1049F0000202020202020202020202020202020297 +:104A00000202020202020202020202020202020286 +:104A10000202020202020202020202020202020276 +:104A20000202020202020202020202020202020266 +:104A30000202020202020202020202020202020256 +:104A40000202020202020202020202020202020246 +:104A50000202020202020202020202020202020236 +:104A60000202020202020202020202020202020226 +:104A70000202020202020202020202020202020216 +:104A80000202020202020202020202020202020206 +:104A900002020202020202020202020202020202F6 +:104AA00002020202020202020202020202020202E6 +:104AB00002020202020202020202020202020202D6 +:104AC00002020202020202020202020202020202C6 +:104AD00002020202020202020202020202020202B6 +:104AE00002020202020202020202020202020202A6 +:104AF0000202020202020202020202020202020296 +:104B00000202020202020202020202020202020285 +:104B10000202020202020202020202020202020275 +:104B20000202020202020202020202020202020265 +:104B30000202020202020202020202020202020255 +:104B40000202020202020202020202020202020245 +:104B50000202020202020202020202020202020235 +:104B60000202020202020202020202020202020225 +:104B70000202020202020202020202020202020215 +:104B80000202020202020202020202020202020205 +:104B900002020202020202020202020202020202F5 +:104BA00002020202020202020202020202020202E5 +:104BB00002020202020202020202020202020202D5 +:104BC00002020202020202020202020202020202C5 +:104BD00002020202020202020202020202020202B5 +:104BE00002020202020202020202020202020202A5 +:104BF0000202020202020202020202020202020295 +:104C00000202020202020202020202020202020284 +:104C10000202020202020202020202020202020274 +:104C20000202020202020202020202020202020264 +:104C30000202020202020202020202020202020254 +:104C40000202020202020202020202020202020244 +:104C50000202020202020202020202020202020234 +:104C60000202020202020202020202020202020224 +:104C70000202020202020202020202020202020214 +:104C80000202020202020202020202020202020204 +:104C900002020202020202020202020202020202F4 +:104CA00002020202020202020202020202020202E4 +:104CB00002020202020202020202020202020202D4 +:104CC00002020202020202020202020202020202C4 +:104CD00002020202020202020202020202020202B4 +:104CE00002020202020202020202020202020202A4 +:104CF0000202020202020202020202020202020294 +:104D00000202020202020202020202020202020283 +:104D10000202020202020202020202020202020273 +:104D20000202020202020202020202020202020263 +:104D30000202020202020202020202020202020253 +:104D40000202020202020202020202020202020243 +:104D50000202020202020202020202020202020233 +:104D60000202020202020202020202020202020223 +:104D70000202020202020202020202020202020213 +:104D80000202020202020202020202020202020203 +:104D900002020202020202020202020202020202F3 +:104DA00002020202020202020202020202020202E3 +:104DB00002020202020202020202020202020202D3 +:104DC00002020202020202020202020202020202C3 +:104DD00002020202020202020202020202020202B3 +:104DE00002020202020202020202020202020202A3 +:104DF0000202020202020202020202020202020293 +:104E00000202020202020202020202020202020282 +:104E10000202020202020202020202020202020272 +:104E20000202020202020202020202020202020262 +:104E30000202020202020202020202020202020252 +:104E40000202020202020202020202020202020242 +:104E50000202020202020202020202020202020232 +:104E60000202020202020202020202020202020222 +:104E70000202020202020202020202020202020212 +:104E80000202020202020202020202020202020202 +:104E900002020202020202020202020202020202F2 +:104EA00002020202020202020202020202020202E2 +:104EB00002020202020202020202020202020202D2 +:104EC00002020202020202020202020202020202C2 +:104ED00002020202020202020202020202020202B2 +:104EE00002020202020202020202020202020202A2 +:104EF0000202020202020202020202020202020292 +:104F00000202020202020202020202020202020281 +:104F10000202020202020202020202020202020271 +:104F20000202020202020202020202020202020261 +:104F30000202020202020202020202020202020251 +:104F40000202020202020202020202020202020241 +:104F50000202020202020202020202020202020231 +:104F60000202020202020202020202020202020221 +:104F70000202020202020202020202020202020211 +:104F80000202020202020202020202020202020201 +:104F900002020202020202020202020202020202F1 +:104FA00002020202020202020202020202020202E1 +:104FB00002020202020202020202020202020202D1 +:104FC00002020202020202020202020202020202C1 +:104FD00002020202020202020202020202020202B1 +:104FE00002020202020202020202020202020202A1 +:104FF0000202020202020202020202020202020291 +:105000000202020202020202020202020202020280 +:105010000202020202020202020202020202020270 +:105020000202020202020202020202020202020260 +:105030000202020202020202020202020202020250 +:105040000202020202020202020202020202020240 +:105050000202020202020202020202020202020230 +:105060000202020202020202020202020202020220 +:105070000202020202020202020202020202020210 +:105080000202020202020202020202020202020200 +:1050900002020202020202020202020202020202F0 +:1050A00002020202020202020202020202020202E0 +:1050B00002020202020202020202020202020202D0 +:1050C00002020202020202020202020202020202C0 +:1050D00002020202020202020202020202020202B0 +:1050E00002020202020202020202020202020202A0 +:1050F0000202020202020202020202020202020290 +:10510000020202020202020202020202020202027F +:10511000020202020202020202020202020202026F +:10512000020202020202020202020202020202025F +:10513000020202020202020202020202020202024F +:10514000020202020202020202020202020202023F +:10515000020202020202020202020202020202022F +:10516000020202020202020202020202020202021F +:10517000020202020202020202020202020202020F +:1051800002020202020202020202020202020202FF +:1051900002020202020202020202020202020202EF +:1051A00002020202020202020202020202020202DF +:1051B00002020202020202020202020202020202CF +:1051C00002020202020202020202020202020202BF +:1051D00002020202020202020202020202020202AF +:1051E000020202020202020202020202020202029F +:1051F000020202020202020202020202020202028F +:10520000020202020202020202020202020202027E +:10521000020202020202020202020202020202026E +:10522000020202020202020202020202020202025E +:10523000020202020202020202020202020202024E +:10524000020202020202020202020202020202023E +:10525000020202020202020202020202020202022E +:10526000020202020202020202020202020202021E +:10527000020202020202020202020202020202020E +:1052800002020202020202020202020202020202FE +:1052900002020202020202020202020202020202EE +:1052A00002020202020202020202020202020202DE +:1052B00002020202020202020202020202020202CE +:1052C00002020202020202020202020202020202BE +:1052D00002020202020202020202020202020202AE +:1052E000020202020202020202020202020202029E +:1052F000020202020202020202020202020202028E +:10530000020202020202020202020202020202027D +:10531000020202020202020202020202020202026D +:10532000020202020202020202020202020202025D +:10533000020202020202020202020202020202024D +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202020202020202020202020202ED +:1053A00002020202020202020202020202020202DD +:1053B00002020202020202020202020202020202CD +:1053C00002020202020202020202020202020202BD +:1053D00002020202020202020202020202020202AD +:1053E000020202020202020202020202020202029D +:1053F000020202020202020202020202020202028D +:10540000020202020202020202020202020202027C +:10541000020202020202020202020202020202026C +:10542000020202020202020202020202020202025C +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202020202020202020202EC +:1054A00002020202020202020202020202020202DC +:1054B00002020202020202020202020202020202CC +:1054C00002020202020202020202020202020202BC +:1054D00002020202020202020202020202020202AC +:1054E000020202020202020202020202020202029C +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020202020202020202020202020202DB +:1055B00002020202020202020202020202020202CB +:1055C00002020202020202020202020202020202BB +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020202020202020202020202020202027A +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020202020202020202020202020202DA +:1056B00002020202020202020202020202020202CA +:1056C00002020202020202020202020202020202BA +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020202020202020202D8 +:1058B00002020202020202020202020202020202C8 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020202020202020202D7 +:1059B00002020202020202020202020202020202C7 +:1059C00002020202020202020202020202020202B7 +:1059D00002020202020202020202020202020202A7 +:1059E0000202020202020202020202020202020297 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A40000202020202020202020202020202020236 +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002020202020202020202020202020202E6 +:105AA00002020202020202020202020202020202D6 +:105AB00002020202020202020202020202020202C6 +:105AC00002020202020202020202020202020202B6 +:105AD00002020202020202020202020202020202A6 +:105AE0000202020202020202020202020202020296 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020202020202020202020202020202E5 +:105BA00002020202020202020202020202020202D5 +:105BB00002020202020202020202020202020202C5 +:105BC00002020202020202020202020202020202B5 +:105BD00002020202020202020202020202020202A5 +:105BE0000202020202020202020202020202020295 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020202020202020202020202020202E4 +:105CA00002020202020202020202020202020202D4 +:105CB00002020202020202020202020202020202C4 +:105CC00002020202020202020202020202020202B4 +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202020202020202020294 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020202020202020202020202E3 +:105DA00002020202020202020202020202020202D3 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020202020202020202B3 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202020202020202020293 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020202B2 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202020202020202020292 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202008E +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000000BA +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000000B9 +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000000B8 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000001A4 +:107BE0000101010101010101010101010101010185 +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101010101010101010134 +:107C40000101010101010101010101010101010124 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010101010101010101E4 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD0000101010101010101010101010101010194 +:107CE0000101010101010101010101010101010184 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010101010101010101010123 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010101010101010101E3 +:107D900001010101010101010101010101010101D3 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010101010101010101010107 +:1089600001010101010101010101010101010101F7 +:1089700001010101010101010101010101010101E7 +:1089800001010101010101010101010101010101D7 +:1089900001010101010101010101010101010101C7 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010114 +:108C50000101010101010101010101010101010104 +:108C600001010101010101010101010101010101F4 +:108C700001010101010101010101010101010101E4 +:108C800001010101010101010101010101010101D4 +:108C900001010101010101010101010101010101C4 +:108CA00001010101010101010101010101010101B4 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010101DD +:10A3700001010101010101010101010101010101CD +:10A3800001010101010101010101010101010101BD +:10A3900001010101010101010101010101010101AD +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010101DC +:10A4700001010101010101010101010101010101CC +:10A4800001010101010101010101010101010101BC +:10A4900001010101010101010101010101010101AC +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800001010101010101010101010101010101BB +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010101010101010101010101010101BA +:10A6900001010101010101010101010101010101AA +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010101B9 +:10A7900001010101010101010101010101010101A9 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB10000101010101010101010101010101010125 +:10AB20000101010101010101010101010101010115 +:10AB30000101010101010101010101010101010105 +:10AB400001010101010101010101010101010101F5 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010101C5 +:10AB800001010101010101010101010101010101B5 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010185 +:10ABC0000101010101010101010101010101010175 +:10ABD0000101010101010101010101010101010165 +:10ABE0000101010101010101010101010101010155 +:10ABF0000101010101010101010101010101010145 +:10AC00000101010101010101010101010101010134 +:10AC10000101010101010101010101010101010124 +:10AC20000101010101010101010101010101010114 +:10AC30000101010101010101010101010101010104 +:10AC400001010101010101010101010101010101F4 +:10AC500001010101010101010101010101010101E4 +:10AC600001010101010101010101010101010101D4 +:10AC700001010101010101010101010101010101C4 +:10AC800001010101010101010101010101010101B4 +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010184 +:10ACC0000101010101010101010101010101010174 +:10ACD0000101010101010101010101010101010164 +:10ACE0000101010101010101010101010101010154 +:10ACF0000101010101010101010101010101010144 +:10AD00000101010101010101010101010101010133 +:10AD10000101010101010101010101010101010123 +:10AD20000101010101010101010101010101010113 +:10AD30000101010101010101010101010101010103 +:10AD400001010101010101010101010101010101F3 +:10AD500001010101010101010101010101010101E3 +:10AD600001010101010101010101010101010101D3 +:10AD700001010101010101010101010101010101C3 +:10AD800001010101010101010101010101010101B3 +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010183 +:10ADC0000101010101010101010101010101010173 +:10ADD0000101010101010101010101010101010163 +:10ADE0000101010101010101010101010101010153 +:10ADF0000101010101010101010101010101010143 +:10AE00000101010101010101010101010101010132 +:10AE10000101010101010101010101010101010122 +:10AE20000101010101010101010101010101010112 +:10AE30000101010101010101010101010101010102 +:10AE400001010101010101010101010101010101F2 +:10AE500001010101010101010101010101010101E2 +:10AE600001010101010101010101010101010101D2 +:10AE700001010101010101010101010101010101C2 +:10AE800001010101010101010101010101010101B2 +:10AE900001010101010101010101010101010101A2 +:10AEA0000101010101010101010101010101010192 +:10AEB0000101010101010101010101010101010182 +:10AEC0000101010101010101010101010101010172 +:10AED0000101010101010101010101010101010162 +:10AEE0000101010101010101010101010101010152 +:10AEF0000101010101010101010101010101010142 +:10AF00000101010101010101010101010101010131 +:10AF10000101010101010101010101010101010121 +:10AF20000101010101010101010101010101010111 +:10AF30000101010101010101010101010101010101 +:10AF400001010101010101010101010101010101F1 +:10AF500001010101010101010101010101010101E1 +:10AF600001010101010101010101010101010101D1 +:10AF700001010101010101010101010101010101C1 +:10AF800001010101010101010101010101010101B1 +:10AF900001010101010101010101010101010101A1 +:10AFA0000101010101010101010101010101010191 +:10AFB0000101010101010101010101010101010181 +:10AFC0000101010101010101010101010101010171 +:10AFD0000101010101010101010101010101010161 +:10AFE0000101010101010101010101010101010151 +:10AFF0000101010101010101010101010101010141 +:10B000000101010101010101010101010101010130 +:10B010000101010101010101010101010101010120 +:10B020000101010101010101010101010101010110 +:10B030000101010101010101010101010101010100 +:10B0400001010101010101010101010101010101F0 +:10B0500001010101010101010101010101010101E0 +:10B0600001010101010101010101010101010101D0 +:10B0700001010101010101010101010101010101C0 +:10B0800001010101010101010101010101010101B0 +:10B0900001010101010101010101010101010101A0 +:10B0A0000101010101010101010101010101010190 +:10B0B0000101010101010101010101010101010180 +:10B0C0000101010101010101010101010101010170 +:10B0D0000101010101010101010101010101010160 +:10B0E0000101010101010101010101010101010150 +:10B0F0000101010101010101010101010101010140 +:10B10000010101010101010101010101010101012F +:10B11000010101010101010101010101010101011F +:10B12000010101010101010101010101010101010F +:10B1300001010101010101010101010101010101FF +:10B1400001010101010101010101010101010101EF +:10B1500001010101010101010101010101010101DF +:10B1600001010101010101010101010101010101CF +:10B1700001010101010101010101010101010101BF +:10B1800001010101010101010101010101010101AF +:10B19000010101010101010101010101010101019F +:10B1A000010101010101010101010101010101018F +:10B1B000010101010101010101010101010101017F +:10B1C000010101010101010101010101010101016F +:10B1D000010101010101010101010101010101015F +:10B1E000010101010101010101010101010101014F +:10B1F000010101010101010101010101010101013F +:10B20000010101010101010101010101010101012E +:10B21000010101010101010101010101010101011E +:10B22000010101010101010101010101010101010E +:10B2300001010101010101010101010101010101FE +:10B2400001010101010101010101010101010101EE +:10B2500001010101010101010101010101010101DE +:10B2600001010101010101010101010101010101CE +:10B2700001010101010101010101010101010101BE +:10B2800001010101010101010101010101010101AE +:10B29000010101010101010101010101010101019E +:10B2A000010101010101010101010101010101018E +:10B2B000010101010101010101010101010101017E +:10B2C000010101010101010101010101010101016E +:10B2D000010101010101010101010101010101015E +:10B2E000010101010101010101010101010101014E +:10B2F000010101010101010101010101010101013E +:10B30000010101010101010101010101010101012D +:10B31000010101010101010101010101010101011D +:10B32000010101010101010101010101010101010D +:10B3300001010101010101010101010101010101FD +:10B3400001010101010101010101010101010101ED +:10B3500001010101010101010101010101010101DD +:10B3600001010101010101010101010101010101CD +:10B3700001010101010101010101010101010101BD +:10B3800001010101010101010101010101010101AD +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010101010101010101018D +:10B3B000010101010101010101010101010101017D +:10B3C000010101010101010101010101010101016D +:10B3D000010101010101010101010101010101005E +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000000000000000000000000000000000002B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000267 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020202020202020202020202C5 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020255 +:10BBD0000202020202020202020202020202020245 +:10BBE0000202020202020202020202020202020235 +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020251 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202023D +:10C3E000020202020202020202020202020202022D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202023C +:10C4E000020202020202020202020202020202022C +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000020202020202020202020202020202022B +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202023A +:10C6E000020202020202020202020202020202022A +:10C6F000020202020202020202020202020202021A +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020202020202020202020202020249 +:10C7D0000202020202020202020202020202020239 +:10C7E0000202020202020202020202020202020229 +:10C7F0000202020202020202020202020202020219 +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020202020202020202020202020248 +:10C8D0000202020202020202020202020202020238 +:10C8E0000202020202020202020202020202020228 +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020257 +:10C9C0000202020202020202020202020202020247 +:10C9D0000202020202020202020202020202020237 +:10C9E0000202020202020202020202020202020227 +:10C9F0000202020202020202020202020202020217 +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020233 +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202020202020202020202020213 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020202020252 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020232 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202020202020202020202020212 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020231 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202020202020202020202020211 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202020202020202020202020202020230 +:10D0E0000202020202020202020202020202020220 +:10D0F0000202020202020202020202020202020210 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D17000020202020202020202020202020202028F +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020202020202020202020202023F +:10D1D000020202020202020202020202020202022F +:10D1E000020202020202020202020202020202021F +:10D1F000020202020202020202020202020202020F +:10D2000002020202020202020202020202020202FE +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D000020202020202020202020202020202022E +:10D2E000020202020202020202020202020202021E +:10D2F000020202020202020202020202020202020E +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020202020202020202020202CD +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020202020202020202020202025D +:10D3B000020202020202020202020202020202024D +:10D3C000020202020202020202020202020202023D +:10D3D000020202020202020202020202020202022D +:10D3E000020202020202020202020202020202021D +:10D3F000020202020202020202020202020202020D +:10D4000002020202020202020202020202020202FC +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020202DC +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202020202020202025C +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020202020202020202023C +:10D4D000020202020202020202020202020202022C +:10D4E000020202020202020202020202020202021C +:10D4F000020202020202020202020202020202020C +:10D5000002020202020202020202020202020202FB +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020202020202020202020202CB +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A000020202020202020202020202020202025B +:10D5B000020202020202020202020202020202024B +:10D5C000020202020202020202020202020202023B +:10D5D000020202020202020202020202020202022B +:10D5E000020202020202020202020202020202021B +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B000020202020202020202020202020202024A +:10D6C000020202020202020202020202020202023A +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020202020202020202020239 +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C0000202020202020202020202020202020238 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202020202020237 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202020202020236 +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020202020202020202020216 +:10DAF0000202020202020202020202020202020206 +:10DB000002020202020202020202020202020202F5 +:10DB100002020202020202020202020202020202E5 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB0000202020202020202020202020202020245 +:10DBC0000202020202020202020202020202020235 +:10DBD0000202020202020202020202020202020225 +:10DBE0000202020202020202020202020202020215 +:10DBF0000202020202020202020202020202020205 +:10DC000002020202020202020202020202020202F4 +:10DC100002020202020202020202020202020202E4 +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB0000202020202020202020202020202020244 +:10DCC0000202020202020202020202020202020234 +:10DCD0000202020202020202020202020202020224 +:10DCE0000202020202020202020202020202020214 +:10DCF0000202020202020202020202020202020204 +:10DD000002020202020202020202020202020202F3 +:10DD100002020202020202020202020202020202E3 +:10DD200002020202020202020202020202020202D3 +:10DD300002020202020202020202020202020202C3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB0000202020202020202020202020202020243 +:10DDC0000202020202020202020202020202020233 +:10DDD0000202020202020202020202020202020223 +:10DDE0000202020202020202020202020202020213 +:10DDF0000202020202020202020202020202020203 +:10DE000002020202020202020202020202020202F2 +:10DE100002020202020202020202020202020202E2 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA0000202020202020202020202020202020252 +:10DEB0000202020202020202020202020202020242 +:10DEC0000202020202020202020202020202020232 +:10DED0000202020202020202020202020202020222 +:10DEE0000202020202020202020202020202020212 +:10DEF0000202020202020202020202020202020202 +:10DF000002020202020202020202020202020202F1 +:10DF100002020202020202020202020202020202E1 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202020202020231 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020202020202020202020211 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020202020202020202020250 +:10E0B0000202020202020202020202020202020240 +:10E0C0000202020202020202020202020202020230 +:10E0D0000202020202020202020202020202020220 +:10E0E0000202020202020202020202020202020210 +:10E0F0000202020202020202020202020202020200 +:10E1000002020202020202020202020202020202EF +:10E1100002020202020202020202020202020202DF +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A000020202020202020202020202020202024F +:10E1B000020202020202020202020202020202023F +:10E1C000020202020202020202020202020202022F +:10E1D000020202020202020202020202020202021F +:10E1E000020202020202020202020202020202020F +:10E1F00002020202020202020202020202020202FF +:10E2000002020202020202020202020202020202EE +:10E2100002020202020202020202020202020202DE +:10E2200002020202020202020202020202020202CE +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E28000020202020202020202020202020202026E +:10E29000020202020202020202020202020202025E +:10E2A000020202020202020202020202020202024E +:10E2B000020202020202020202020202020202023E +:10E2C000020202020202020202020202020202022E +:10E2D000020202020202020202020202020202021E +:10E2E000020202020202020202020202020202020E +:10E2F00002020202020202020202020202020202FE +:10E3000002020202020202020202020202020202ED +:10E3100002020202020202020202020202020202DD +:10E3200002020202020202020202020202020202CD +:10E3300002020202020202020202020202020202BD +:10E3400002020202020202020202020202020202AD +:10E35000020202020202020202020202020202029D +:10E36000020202020202020202020202020202028D +:10E37000020202020202020202020202020202027D +:10E38000020202020202020202020202020202026D +:10E39000020202020202020202020202020202025D +:10E3A000020202020202020202020202020202024D +:10E3B000020202020202020202020202020202023D +:10E3C000020202020202020202020202020202022D +:10E3D000020202020202020202020202020202021D +:10E3E000020202020202020202020202020202020D +:10E3F00002020202020202020202020202020202FD +:10E4000002020202020202020202020202020202EC +:10E4100002020202020202020202020202020202DC +:10E4200002020202020202020202020202020202CC +:10E4300002020202020202020202020202020202BC +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A000020202020202020202020202020202024C +:10E4B000020202020202020202020202020202023C +:10E4C000020202020202020202020202020202022C +:10E4D000020202020202020202020202020202021C +:10E4E000020202020202020202020202020202020C +:10E4F00002020202020202020202020202020202FC +:10E5000002020202020202020202020202020202EB +:10E5100002020202020202020202020202020202DB +:10E5200002020202020202020202020202020202CB +:10E5300002020202020202020202020202020202BB +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A000020202020202020202020202020202024B +:10E5B000020202020202020202020202020202023B +:10E5C000020202020202020202020202020202022B +:10E5D000020202020202020202020202020202021B +:10E5E000020202020202020202020202020202020B +:10E5F00002020202020202020202020202020202FB +:10E6000002020202020202020202020202020202EA +:10E6100002020202020202020202020202020202DA +:10E6200002020202020202020202020202020202CA +:10E6300002020202020202020202020202020202BA +:10E6400002020202020202020202020202020202AA +:10E65000020202020202020202020202020202029A +:10E66000020202020202020202020202020202028A +:10E67000020202020202020202020202020202027A +:10E68000020202020202020202020202020202026A +:10E69000020202020202020202020202020202025A +:10E6A000020202020202020202020202020202024A +:10E6B000020202020202020202020202020202023A +:10E6C000020202020202020202020202020202022A +:10E6D000020202020202020202020202020202021A +:10E6E000020202020202020202020202020202020A +:10E6F00002020202020202020202020202020202FA +:10E7000002020202020202020202020202020202E9 +:10E7100002020202020202020202020202020202D9 +:10E7200002020202020202020202020202020202C9 +:10E7300002020202020202020202020202020202B9 +:10E7400002020202020202020202020202020202A9 +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000202020202020202020202020202020229 +:10E7D0000202020202020202020202020202020219 +:10E7E0000202020202020202020202020202020209 +:10E7F00002020202020202020202020202020202F9 +:10E8000002020202020202020202020202020202E8 +:10E8100002020202020202020202020202020202D8 +:10E8200002020202020202020202020202020202C8 +:10E8300002020202020202020202020202020202B8 +:10E8400002020202020202020202020202020202A8 +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C0000202020202020202020202020202020228 +:10E8D0000202020202020202020202020202020218 +:10E8E0000202020202020202020202020202020208 +:10E8F00002020202020202020202020202020202F8 +:10E9000002020202020202020202020202020202E7 +:10E9100002020202020202020202020202020202D7 +:10E9200002020202020202020202020202020202C7 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202020202020202020202020202F7 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020202020202020202020202020202C6 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020203 +:10EDF00002020202020202020202020202020202F3 +:10EE000002020202020202020202020202020202E2 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202020202020202020202F2 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020202020202020202020202A1 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020202020202020221 +:10EFD0000202020202020202020202020202020013 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000D756 +:10F3E0000000000000000001010101010101010114 +:10F3F00001010101010101010101010101010101FD +:10F4000001010101010101010101010101010101EC +:10F4100001010101010101010101010101010101DC +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F46000010101010101010101010101010101018C +:10F47000010101010101010101010101010101017C +:10F48000010101010101010101010101010101016C +:10F49000010101010101010101010101010101015C +:10F4A000010101010101010101010101010101014C +:10F4B000010101010101010101010101010101013C +:10F4C000010101010101010101010101010101012C +:10F4D000010101010101010101010101010101011C +:10F4E000010101010101010101010101010101010C +:10F4F00001010101010101010101010101010101FC +:10F5000001010101010101010101010101010101EB +:10F5100001010101010101010101010101010101DB +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101010101010101010101AB +:10F55000010101010101010101010101010101019B +:10F56000010101010101010101010101010101018B +:10F57000010101010101010101010101010101017B +:10F58000010101010101010101010101010101016B +:10F59000010101010101010101010101010101015B +:10F5A000010101010101010101010101010101014B +:10F5B000010101010101010101010101010101013B +:10F5C000010101010101010101010101010101012B +:10F5D000010101010101010101010101010101011B +:10F5E000010101010101010101010101010101010B +:10F5F00001010101010101010101010101010101FB +:10F6000001010101010101010101010101010101EA +:10F6100001010101010101010101010101010101DA +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010101010101010101017A +:10F68000010101010101010101010101010101016A +:10F69000010101010101010101010101010101015A +:10F6A000010101010101010101010101010101014A +:10F6B000010101010101010101010101010101013A +:10F6C000010101010101010101010101010101012A +:10F6D000010101010101010101010101010101011A +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010101010101010101010139 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101010101010101010141 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD0000101010101010101010101010101010111 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:020000021000EC +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010198 +:100850000101010101010101010101010101010188 +:100860000101010101010101010101010101010178 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010118 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000001010101010101010101010101010101D2 +:100E100001010101010101010101010101010101C2 +:100E200001010101010101010101010101010101B2 +:100E300001010101010101010101010101010101A2 +:100E40000101010101010101010101010101010192 +:100E50000101010101010101010101010101010182 +:100E60000101010101010101010101010101010172 +:100E70000101010101010101010101010101010162 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101010101010101010101E2 +:100F000001010101010101010101010101010101D1 +:100F100001010101010101010101010101010101C1 +:100F200001010101010101010101010101010101B1 +:100F300001010101010101010101010101010101A1 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000101010101010101010101010101010171 +:100F70000101010101010101010101010101010161 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101010101010101010101E1 +:1010000001010101010101010101010101010101D0 +:1010100001010101010101010101010101010101C0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000101010101010101010101010101010170 +:101070000101010101010101010101010101010160 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010101010101BF +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:10116000010101010101010101010101010101016F +:10117000010101010101010101010101010101015F +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010101010101BE +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101016E +:10127000010101010101010101010101010101015E +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101010101010101010101BD +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101016D +:10137000010101010101010101010101010101015D +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101016C +:10147000010101010101010101010101010101015C +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101018B +:10155000010101010101010101010101010101017B +:10156000010101010101010101010101010101016B +:10157000010101010101010101010101010101015B +:10158000010101010101010101010101010101014B +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010101010101010101019A +:10164000010101010101010101010101010101018A +:10165000010101010101010101010101010101017A +:10166000010101010101010101010101010101016A +:10167000010101010101010101010101010101015A +:10168000010101010101010101010101010101014A +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010101010101010101010157 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101000000000000000000E5 +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000020202020202020202D6 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020202D3 +:102DE00002020202020202020202020202020202C3 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020202D2 +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202029E +:10430000020202020202020202020202020202028D +:10431000020202020202020202020202020202027D +:10432000020202020202020202020202020202026D +:10433000020202020202020202020202020202025D +:10434000020202020202020202020202020202024D +:10435000020202020202020202020202020202023D +:10436000020202020202020202020202020202022D +:10437000020202020202020202020202020202021D +:10438000020202020202020202020202020202020D +:1043900002020202020202020202020202020202FD +:1043A00002020202020202020202020202020202ED +:1043B00002020202020202020202020202020202DD +:1043C00002020202020202020202020202020202CD +:1043D00002020202020202020202020202020202BD +:1043E00002020202020202020202020202020202AD +:1043F000020202020202020202020202020202029D +:10440000020202020202020202020202020202028C +:10441000020202020202020202020202020202027C +:10442000020202020202020202020202020202026C +:10443000020202020202020202020202020202025C +:10444000020202020202020202020202020202024C +:10445000020202020202020202020202020202023C +:10446000020202020202020202020202020202022C +:10447000020202020202020202020202020202021C +:10448000020202020202020202020202020202020C +:1044900002020202020202020202020202020202FC +:1044A00002020202020202020202020202020202EC +:1044B00002020202020202020202020202020202DC +:1044C00002020202020202020202020202020202CC +:1044D00002020202020202020202020202020202BC +:1044E00002020202020202020202020202020202AC +:1044F000020202020202020202020202020202029C +:10450000020202020202020202020202020202028B +:10451000020202020202020202020202020202027B +:10452000020202020202020202020202020202026B +:10453000020202020202020202020202020202025B +:10454000020202020202020202020202020202024B +:10455000020202020202020202020202020202023B +:10456000020202020202020202020202020202022B +:10457000020202020202020202020202020202021B +:10458000020202020202020202020202020202020B +:1045900002020202020202020202020202020202FB +:1045A00002020202020202020202020202020202EB +:1045B00002020202020202020202020202020202DB +:1045C00002020202020202020202020202020202CB +:1045D00002020202020202020202020202020202BB +:1045E00002020202020202020202020202020202AB +:1045F000020202020202020202020202020202029B +:10460000020202020202020202020202020202028A +:10461000020202020202020202020202020202027A +:10462000020202020202020202020202020202026A +:10463000020202020202020202020202020202025A +:10464000020202020202020202020202020202024A +:10465000020202020202020202020202020202023A +:10466000020202020202020202020202020202022A +:10467000020202020202020202020202020202021A +:10468000020202020202020202020202020202020A +:1046900002020202020202020202020202020202FA +:1046A00002020202020202020202020202020202EA +:1046B00002020202020202020202020202020202DA +:1046C00002020202020202020202020202020202CA +:1046D00002020202020202020202020202020202BA +:1046E00002020202020202020202020202020202AA +:1046F000020202020202020202020202020202029A +:104700000202020202020202020202020202020289 +:104710000202020202020202020202020202020279 +:104720000202020202020202020202020202020269 +:104730000202020202020202020202020202020259 +:104740000202020202020202020202020202020249 +:104750000202020202020202020202020202020239 +:104760000202020202020202020202020202020229 +:104770000202020202020202020202020202020219 +:104780000202020202020202020202020202020209 +:1047900002020202020202020202020202020202F9 +:1047A00002020202020202020202020202020202E9 +:1047B00002020202020202020202020202020202D9 +:1047C00002020202020202020202020202020202C9 +:1047D00002020202020202020202020202020202B9 +:1047E00002020202020202020202020202020202A9 +:1047F0000202020202020202020202020202020299 +:104800000202020202020202020202020202020288 +:104810000202020202020202020202020202020278 +:104820000202020202020202020202020202020268 +:104830000202020202020202020202020202020258 +:104840000202020202020202020202020202020248 +:104850000202020202020202020202020202020238 +:104860000202020202020202020202020202020228 +:104870000202020202020202020202020202020218 +:104880000202020202020202020202020202020208 +:1048900002020202020202020202020202020202F8 +:1048A00002020202020202020202020202020202E8 +:1048B00002020202020202020202020202020202D8 +:1048C00002020202020202020202020202020202C8 +:1048D00002020202020202020202020202020202B8 +:1048E00002020202020202020202020202020202A8 +:1048F0000202020202020202020202020202020298 +:104900000202020202020202020202020202020287 +:104910000202020202020202020202020202020277 +:104920000202020202020202020202020202020267 +:104930000202020202020202020202020202020257 +:104940000202020202020202020202020202020247 +:104950000202020202020202020202020202020237 +:104960000202020202020202020202020202020227 +:104970000202020202020202020202020202020217 +:104980000202020202020202020202020202020207 +:1049900002020202020202020202020202020202F7 +:1049A00002020202020202020202020202020202E7 +:1049B00002020202020202020202020202020202D7 +:1049C00002020202020202020202020202020202C7 +:1049D00002020202020202020202020202020202B7 +:1049E00002020202020202020202020202020202A7 +:1049F0000202020202020202020202020202020297 +:104A00000202020202020202020202020202020286 +:104A10000202020202020202020202020202020276 +:104A20000202020202020202020202020202020266 +:104A30000202020202020202020202020202020256 +:104A40000202020202020202020202020202020246 +:104A50000202020202020202020202020202020236 +:104A60000202020202020202020202020202020226 +:104A70000202020202020202020202020202020216 +:104A80000202020202020202020202020202020206 +:104A900002020202020202020202020202020202F6 +:104AA00002020202020202020202020202020202E6 +:104AB00002020202020202020202020202020202D6 +:104AC00002020202020202020202020202020202C6 +:104AD00002020202020202020202020202020202B6 +:104AE00002020202020202020202020202020202A6 +:104AF0000202020202020202020202020202020296 +:104B00000202020202020202020202020202020285 +:104B10000202020202020202020202020202020275 +:104B20000202020202020202020202020202020265 +:104B30000202020202020202020202020202020255 +:104B40000202020202020202020202020202020245 +:104B50000202020202020202020202020202020235 +:104B60000202020202020202020202020202020225 +:104B70000202020202020202020202020202020215 +:104B80000202020202020202020202020202020205 +:104B900002020202020202020202020202020202F5 +:104BA00002020202020202020202020202020202E5 +:104BB00002020202020202020202020202020202D5 +:104BC00002020202020202020202020202020202C5 +:104BD00002020202020202020202020202020202B5 +:104BE00002020202020202020202020202020202A5 +:104BF0000202020202020202020202020202020295 +:104C00000202020202020202020202020202020284 +:104C10000202020202020202020202020202020274 +:104C20000202020202020202020202020202020264 +:104C30000202020202020202020202020202020254 +:104C40000202020202020202020202020202020244 +:104C50000202020202020202020202020202020234 +:104C60000202020202020202020202020202020224 +:104C70000202020202020202020202020202020214 +:104C80000202020202020202020202020202020204 +:104C900002020202020202020202020202020202F4 +:104CA00002020202020202020202020202020202E4 +:104CB00002020202020202020202020202020202D4 +:104CC00002020202020202020202020202020202C4 +:104CD00002020202020202020202020202020202B4 +:104CE00002020202020202020202020202020202A4 +:104CF0000202020202020202020202020202020294 +:104D00000202020202020202020202020202020283 +:104D10000202020202020202020202020202020273 +:104D20000202020202020202020202020202020263 +:104D30000202020202020202020202020202020253 +:104D40000202020202020202020202020202020243 +:104D50000202020202020202020202020202020233 +:104D60000202020202020202020202020202020223 +:104D70000202020202020202020202020202020213 +:104D80000202020202020202020202020202020203 +:104D900002020202020202020202020202020202F3 +:104DA00002020202020202020202020202020202E3 +:104DB00002020202020202020202020202020202D3 +:104DC00002020202020202020202020202020202C3 +:104DD00002020202020202020202020202020202B3 +:104DE00002020202020202020202020202020202A3 +:104DF0000202020202020202020202020202020293 +:104E00000202020202020202020202020202020282 +:104E10000202020202020202020202020202020272 +:104E20000202020202020202020202020202020262 +:104E30000202020202020202020202020202020252 +:104E40000202020202020202020202020202020242 +:104E50000202020202020202020202020202020232 +:104E60000202020202020202020202020202020222 +:104E70000202020202020202020202020202020212 +:104E80000202020202020202020202020202020202 +:104E900002020202020202020202020202020202F2 +:104EA00002020202020202020202020202020202E2 +:104EB00002020202020202020202020202020202D2 +:104EC00002020202020202020202020202020202C2 +:104ED00002020202020202020202020202020202B2 +:104EE00002020202020202020202020202020202A2 +:104EF0000202020202020202020202020202020292 +:104F00000202020202020202020202020202020281 +:104F10000202020202020202020202020202020271 +:104F20000202020202020202020202020202020261 +:104F30000202020202020202020202020202020251 +:104F40000202020202020202020202020202020241 +:104F50000202020202020202020202020202020231 +:104F60000202020202020202020202020202020221 +:104F70000202020202020202020202020202020211 +:104F80000202020202020202020202020202020201 +:104F900002020202020202020202020202020202F1 +:104FA00002020202020202020202020202020202E1 +:104FB00002020202020202020202020202020202D1 +:104FC00002020202020202020202020202020202C1 +:104FD00002020202020202020202020202020202B1 +:104FE00002020202020202020202020202020202A1 +:104FF0000202020202020202020202020202020291 +:105000000202020202020202020202020202020280 +:105010000202020202020202020202020202020270 +:105020000202020202020202020202020202020260 +:105030000202020202020202020202020202020250 +:105040000202020202020202020202020202020240 +:105050000202020202020202020202020202020230 +:105060000202020202020202020202020202020220 +:105070000202020202020202020202020202020210 +:105080000202020202020202020202020202020200 +:1050900002020202020202020202020202020202F0 +:1050A00002020202020202020202020202020202E0 +:1050B00002020202020202020202020202020202D0 +:1050C00002020202020202020202020202020202C0 +:1050D00002020202020202020202020202020202B0 +:1050E00002020202020202020202020202020202A0 +:1050F0000202020202020202020202020202020290 +:10510000020202020202020202020202020202027F +:10511000020202020202020202020202020202026F +:10512000020202020202020202020202020202025F +:10513000020202020202020202020202020202024F +:10514000020202020202020202020202020202023F +:10515000020202020202020202020202020202022F +:10516000020202020202020202020202020202021F +:10517000020202020202020202020202020202020F +:1051800002020202020202020202020202020202FF +:1051900002020202020202020202020202020202EF +:1051A00002020202020202020202020202020202DF +:1051B00002020202020202020202020202020202CF +:1051C00002020202020202020202020202020202BF +:1051D00002020202020202020202020202020202AF +:1051E000020202020202020202020202020202029F +:1051F000020202020202020202020202020202028F +:10520000020202020202020202020202020202027E +:10521000020202020202020202020202020202026E +:10522000020202020202020202020202020202025E +:10523000020202020202020202020202020202024E +:10524000020202020202020202020202020202023E +:10525000020202020202020202020202020202022E +:10526000020202020202020202020202020202021E +:10527000020202020202020202020202020202020E +:1052800002020202020202020202020202020202FE +:1052900002020202020202020202020202020202EE +:1052A00002020202020202020202020202020202DE +:1052B00002020202020202020202020202020202CE +:1052C00002020202020202020202020202020202BE +:1052D00002020202020202020202020202020202AE +:1052E000020202020202020202020202020202029E +:1052F000020202020202020202020202020202028E +:10530000020202020202020202020202020202027D +:10531000020202020202020202020202020202026D +:10532000020202020202020202020202020202025D +:10533000020202020202020202020202020202024D +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202020202020202020202020202ED +:1053A00002020202020202020202020202020202DD +:1053B00002020202020202020202020202020202CD +:1053C00002020202020202020202020202020202BD +:1053D00002020202020202020202020202020202AD +:1053E000020202020202020202020202020202029D +:1053F000020202020202020202020202020202028D +:10540000020202020202020202020202020202027C +:10541000020202020202020202020202020202026C +:10542000020202020202020202020202020202025C +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202020202020202020202EC +:1054A00002020202020202020202020202020202DC +:1054B00002020202020202020202020202020202CC +:1054C00002020202020202020202020202020202BC +:1054D00002020202020202020202020202020202AC +:1054E000020202020202020202020202020202029C +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020202020202020202020202020202DB +:1055B00002020202020202020202020202020202CB +:1055C00002020202020202020202020202020202BB +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020202020202020202020202020202027A +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020202020202020202020202020202DA +:1056B00002020202020202020202020202020202CA +:1056C00002020202020202020202020202020202BA +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020202020202020202D8 +:1058B00002020202020202020202020202020202C8 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020202020202020202D7 +:1059B00002020202020202020202020202020202C7 +:1059C00002020202020202020202020202020202B7 +:1059D00002020202020202020202020202020202A7 +:1059E00002020202020202000000000000000000A9 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000010101010101010101A7 +:1060F0000101010101010101010101010101010190 +:10610000010101010101010101010101010101017F +:10611000010101010101010101010101010101016F +:10612000010101010101010101010101010101015F +:10613000010101010101010101010101010101014F +:10614000010101010101010101010101010101013F +:10615000010101010101010101010101010101012F +:10616000010101010101010101010101010101011F +:10617000010101010101010101010101010101010F +:1061800001010101010101010101010101010101FF +:1061900001010101010101010101010101010101EF +:1061A00001010101010101010101010101010101DF +:1061B00001010101010101010101010101010101CF +:1061C00001010101010101010101010101010101BF +:1061D00001010101010101010101010101010101AF +:1061E000010101010101010101010101010101019F +:1061F000010101010101010101010101010101018F +:10620000010101010101010101010101010101017E +:10621000010101010101010101010101010101016E +:10622000010101010101010101010101010101015E +:10623000010101010101010101010101010101014E +:10624000010101010101010101010101010101013E +:10625000010101010101010101010101010101012E +:10626000010101010101010101010101010101011E +:10627000010101010101010101010101010101010E +:1062800001010101010101010101010101010101FE +:1062900001010101010101010101010101010101EE +:1062A00001010101010101010101010101010101DE +:1062B00001010101010101010101010101010101CE +:1062C00001010101010101010101010101010101BE +:1062D00001010101010101010101010101010101AE +:1062E000010101010101010101010101010101019E +:1062F000010101010101010101010101010101018E +:10630000010101010101010101010101010101017D +:10631000010101010101010101010101010101016D +:10632000010101010101010101010101010101015D +:10633000010101010101010101010101010101014D +:10634000010101010101010101010101010101013D +:10635000010101010101010101010101010101012D +:10636000010101010101010101010101010101011D +:10637000010101010101010101010101010101010D +:1063800001010101010101010101010101010101FD +:1063900001010101010101010101010101010101ED +:1063A00001010101010101010101010101010101DD +:1063B00001010101010101010101010101010101CD +:1063C00001010101010101010101010101010101BD +:1063D00001010101010101010101010101010101AD +:1063E000010101010101010101010101010101019D +:1063F000010101010101010101010101010101018D +:10640000010101010101010101010101010101017C +:10641000010101010101010101010101010101016C +:10642000010101010101010101010101010101015C +:10643000010101010101010101010101010101014C +:10644000010101010101010101010101010101013C +:10645000010101010101010101010101010101012C +:10646000010101010101010101010101010101011C +:10647000010101010101010101010101010101010C +:1064800001010101010101010101010101010101FC +:1064900001010101010101010101010101010101EC +:1064A00001010101010101010101010101010101DC +:1064B00001010101010101010101010101010101CC +:1064C00001010101010101010101010101010101BC +:1064D00001010101010101010101010101010101AC +:1064E000010101010101010101010101010101019C +:1064F000010101010101010101010101010101018C +:10650000010101010101010101010101010101017B +:10651000010101010101010101010101010101016B +:10652000010101010101010101010101010101015B +:10653000010101010101010101010101010101014B +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010101010101010101FB +:1065900001010101010101010101010101010101EB +:1065A00001010101010101010101010101010101DB +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101018B +:10660000010101010101010101010101010101017A +:10661000010101010101010101010101010101016A +:10662000010101010101010101010101010101015A +:10663000010101010101010101010101010101014A +:10664000010101010101010101010101010101013A +:10665000010101010101010101010101010101012A +:10666000010101010101010101010101010101011A +:10667000010101010101010101010101010101010A +:1066800001010101010101010101010101010101FA +:1066900001010101010101010101010101010101EA +:1066A00001010101010101010101010101010101DA +:1066B00001010101010101010101010101010101CA +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101010101010101010101AA +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101018A +:106700000101010101010101010101010101010179 +:106710000101010101010101010101010101010169 +:106720000101010101010101010101010101010159 +:106730000101010101010101010101010101010149 +:106740000101010101010101010101010101010139 +:106750000101010101010101010101010101010129 +:106760000101010101010101010101010101010119 +:106770000101010101010101010101010101010109 +:1067800001010101010101010101010101010101F9 +:1067900001010101010101010101010101010101E9 +:1067A00001010101010101010101010101010101D9 +:1067B00001010101010101010101010101010101C9 +:1067C00001010101010101010101010101010101B9 +:1067D00001010101010101010101010101010101A9 +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010178 +:106810000101010101010101010101010101010168 +:106820000101010101010101010101010101010158 +:106830000101010101010101010101010101010148 +:106840000101010101010101010101010101010138 +:106850000101010101010101010101010101010128 +:106860000101010101010101010101010101010118 +:106870000101010101010101010101010101010108 +:1068800001010101010101010101010101010101F8 +:1068900001010101010101010101010101010101E8 +:1068A00001010101010101010101010101010101D8 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010147 +:106940000101010101010101010101010101010137 +:106950000101010101010101010101010101010127 +:106960000101010101010101010101010101010117 +:106970000101010101010101010101010101010107 +:1069800001010101010101010101010101010101F7 +:1069900001010101010101010101010101010101E7 +:1069A00001010101010101010101010101010101D7 +:1069B00001010101010101010101010101010101C7 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101010101010101010101A7 +:1069E0000101010101010101010101010101010197 +:1069F0000101010101010101010101010101010187 +:106A00000101010101010101010101010101010176 +:106A10000101010101010101010101010101010166 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000101010101010101010101010101010136 +:106A50000101010101010101010101010101010126 +:106A60000101010101010101010101010101010116 +:106A70000101010101010101010101010101010106 +:106A800001010101010101010101010101010101F6 +:106A900001010101010101010101010101010101E6 +:106AA00001010101010101010101010101010101D6 +:106AB00001010101010101010101010101010101C6 +:106AC00001010101010101010101010101010101B6 +:106AD00001010101010101010101010101010101A6 +:106AE0000101010101010101010101010101010196 +:106AF0000101010101010101010101010101010186 +:106B00000101010101010101010101010101010175 +:106B10000101010101010101010101010101010165 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B70000101010101010101010101010101010105 +:106B800001010101010101010101010101010101F5 +:106B900001010101010101010101010101010101E5 +:106BA00001010101010101010101010101010101D5 +:106BB00001010101010101010101010101010101C5 +:106BC00001010101010101010101010101010101B5 +:106BD00001010101010101010101010101010101A5 +:106BE0000101010101010101010101010101010195 +:106BF0000101010101010101010101010101010185 +:106C00000101010101010101010101010101010174 +:106C10000101010101010101010101010101010164 +:106C20000101010101010101010101010101010154 +:106C30000101010101010101010101010101010144 +:106C40000101010101010101010101010101010134 +:106C50000101010101010101010101010101010124 +:106C60000101010101010101010101010101010114 +:106C70000101010101010101010101010101010104 +:106C800001010101010101010101010101010101F4 +:106C900001010101010101010101010101010101E4 +:106CA00001010101010101010101010101010101D4 +:106CB00001010101010101010101010101010101C4 +:106CC00001010101010101010101010101010101B4 +:106CD00001010101010101010101010101010101A4 +:106CE0000101010101010101010101010101010194 +:106CF0000101010101010101010101010101010184 +:106D00000101010101010101010101010101010173 +:106D10000101010101010101010101010101010163 +:106D20000101010101010101010101010101010153 +:106D30000101010101010101010101010101010143 +:106D40000101010101010101010101010101010133 +:106D50000101010101010101010101010101010123 +:106D60000101010101010101010101010101010113 +:106D70000101010101010101010101010101010103 +:106D800001010101010101010101010101010101F3 +:106D900001010101010101010101010101010101E3 +:106DA00001010101010101010101010101010101D3 +:106DB00001010101010101010101010101010101C3 +:106DC00001010101010101010101010101010101B3 +:106DD00001010101010101010101010101010101A3 +:106DE0000101010101010101010101010101010193 +:106DF0000101010101010101010101010101010183 +:106E00000101010101010101010101010101010172 +:106E10000101010101010101010101010101010162 +:106E20000101010101010101010101010101010152 +:106E30000101010101010101010101010101010142 +:106E40000101010101010101010101010101010132 +:106E50000101010101010101010101010101010122 +:106E60000101010101010101010101010101010112 +:106E70000101010101010101010101010101010102 +:106E800001010101010101010101010101010101F2 +:106E900001010101010101010101010101010101E2 +:106EA00001010101010101010101010101010101D2 +:106EB00001010101010101010101010101010101C2 +:106EC00001010101010101010101010101010101B2 +:106ED00001010101010101010101010101010101A2 +:106EE0000101010101010101010101010101010192 +:106EF0000101010101010101010101010101010182 +:106F00000101010101010101010101010101010171 +:106F10000101010101010101010101010101010161 +:106F20000101010101010101010101010101010151 +:106F30000101010101010101010101010101010141 +:106F40000101010101010101010101010101010131 +:106F50000101010101010101010101010101010121 +:106F60000101010101010101010101010101010111 +:106F70000101010101010101010101010101010101 +:106F800001010101010101010101010101010101F1 +:106F900001010101010101010101010101010101E1 +:106FA00001010101010101010101010101010101D1 +:106FB00001010101010101010101010101010101C1 +:106FC00001010101010101010101010101010101B1 +:106FD00001010101010101010101010101010101A1 +:106FE0000101010101010101010101010101010191 +:106FF0000101010101010101010101010101010181 +:107000000101010101010101010101010101010170 +:107010000101010101010101010101010101010160 +:107020000101010101010101010101010101010150 +:107030000101010101010101010101010101010140 +:107040000101010101010101010101010101010130 +:107050000101010101010101010101010101010120 +:107060000101010101010101010101010101010110 +:107070000101010101010101010101010101010100 +:1070800001010101010101010101010101010101F0 +:1070900001010101010101010101010101010101E0 +:1070A00001010101010101010101010101010101D0 +:1070B00001010101010101010101010101010101C0 +:1070C00001010101010101010101010101010101B0 +:1070D00001010101010101010101010101010101A0 +:1070E0000101010101010101010101010101010190 +:1070F0000101010101010101010101010101010180 +:10710000010101010101010101010101010101016F +:10711000010101010101010101010101010101015F +:10712000010101010101010101010101010101014F +:10713000010101010101010101010101010101013F +:10714000010101010101010101010101010101012F +:10715000010101010101010101010101010101011F +:10716000010101010101010101010101010101010F +:1071700001010101010101010101010101010101FF +:1071800001010101010101010101010101010101EF +:1071900001010101010101010101010101010101DF +:1071A00001010101010101010101010101010101CF +:1071B00001010101010101010101010101010101BF +:1071C00001010101010101010101010101010101AF +:1071D000010101010101010101010101010101019F +:1071E000010101010101010101010101010101018F +:1071F000010101010101010101010101010101017F +:10720000010101010101010101010101010101016E +:10721000010101010101010101010101010101015E +:10722000010101010101010101010101010101014E +:10723000010101010101010101010101010101013E +:10724000010101010101010101010101010101012E +:10725000010101010101010101010101010101011E +:10726000010101010101010101010101010101010E +:1072700001010101010101010101010101010101FE +:1072800001010101010101010101010101010101EE +:1072900001010101010101010101010101010101DE +:1072A00001010101010101010101010101010101CE +:1072B00001010101010101010101010101010101BE +:1072C00001010101010101010101010101010101AE +:1072D000010101010101010101010101010101019E +:1072E000010101010101010101010101010101018E +:1072F000010101010101010101010101010101017E +:10730000010101010101010101010101010101016D +:10731000010101010101010101010101010101015D +:10732000010101010101010101010101010101014D +:10733000010101010101010101010101010101013D +:10734000010101010101010101010101010101012D +:10735000010101010101010101010101010101011D +:10736000010101010101010101010101010101010D +:1073700001010101010101010101010101010101FD +:1073800001010101010101010101010101010101ED +:1073900001010101010101010101010101010101DD +:1073A00001010101010101010101010101010101CD +:1073B00001010101010101010101010101010101BD +:1073C00001010101010101010101010101010101AD +:1073D000010101010101010101010101010101019D +:1073E000010101010101010101010101010101018D +:1073F000010101010101010101010101010101017D +:10740000010101010101010101010101010101016C +:10741000010101010101010101010101010101015C +:10742000010101010101010101010101010101014C +:10743000010101010101010101010101010101013C +:10744000010101010101010101010101010101012C +:10745000010101010101010101010101010101011C +:10746000010101010101010101010101010101010C +:1074700001010101010101010101010101010101FC +:1074800001010101010101010101010101010101EC +:1074900001010101010101010101010101010101DC +:1074A00001010101010101010101010101010101CC +:1074B00001010101010101010101010101010101BC +:1074C00001010101010101010101010101010101AC +:1074D000010101010101010101010101010101019C +:1074E000010101010101010101010101010101018C +:1074F000010101010101010101010101010101017C +:10750000010101010101010101010101010101016B +:10751000010101010101010101010101010101015B +:10752000010101010101010101010101010101014B +:10753000010101010101010101010101010101013B +:10754000010101010101010101010101010101012B +:10755000010101010101010101010101010101011B +:10756000010101010101010101010101010101010B +:1075700001010101010101010101010101010101FB +:1075800001010101010101010101010101010101EB +:1075900001010101010101010101010101010101DB +:1075A00001010101010101010101010101010101CB +:1075B00001010101010101010101010101010101BB +:1075C00001010101010101010101010101010101AB +:1075D000010101010101010101010101010101019B +:1075E000010101010101010101010101010101018B +:1075F000010101010101010101010101010101017B +:10760000010101010101010101010101010101016A +:10761000010101010101010101010101010101015A +:10762000010101010101010101010101010101014A +:10763000010101010101010101010101010101013A +:10764000010101010101010101010101010101012A +:10765000010101010101010101010101010101011A +:10766000010101010101010101010101010101010A +:1076700001010101010101010101010101010101FA +:1076800001010101010101010101010101010101EA +:1076900001010101010101010101010101010101DA +:1076A00001010101010101010101010101010101CA +:1076B00001010101010101010101010101010101BA +:1076C00001010101010101010101010101010101AA +:1076D000010101010101010101010101010101019A +:1076E000010101010101010101010101010101018A +:1076F000010101010101010101010101010101017A +:107700000101010101010101010101010101010169 +:107710000101010101010101010101010101010159 +:107720000101010101010101010101010101010149 +:107730000101010101010101010101010101010139 +:107740000101010101010101010101010101010129 +:107750000101010101010101010101010101010119 +:107760000101010101010101010101010101010109 +:1077700001010101010101010101010101010101F9 +:1077800001010101010101010101010101010101E9 +:1077900001010101010101010101010101010101D9 +:1077A00001010101010101010101010101010101C9 +:1077B00001010101010101010101010101010101B9 +:1077C00001010101010101010101010101010101A9 +:1077D0000101010101010101010101010101010199 +:1077E0000101010101010101010101010101010189 +:1077F0000101010101010101010101010101010179 +:107800000101010101010101010101010101010168 +:107810000101010101010101010101010101010158 +:107820000101010101010101010101010101010148 +:107830000101010101010101010101010101010138 +:107840000101010101010101010101010101010128 +:107850000101010101010101010101010101010118 +:107860000101010101010101010101010101010108 +:1078700001010101010101010101010101010101F8 +:1078800001010101010101010101010101010101E8 +:1078900001010101010101010101010101010101D8 +:1078A00001010101010101010101010101010101C8 +:1078B00001010101010101010101010101010101B8 +:1078C00001010101010101010101010101010101A8 +:1078D0000101010101010101010101010101010198 +:1078E0000101010101010101010101010101010188 +:1078F0000101010101010101010101010101010178 +:107900000101010101010101010101010101010167 +:107910000101010101010101010101010101010157 +:107920000101010101010101010101010101010147 +:107930000101010101010101010101010101010137 +:107940000101010101010101010101010101010127 +:107950000101010101010101010101010101010117 +:107960000101010101010101010101010101010107 +:1079700001010101010101010101010101010101F7 +:1079800001010101010101010101010101010101E7 +:1079900001010101010101010101010101010101D7 +:1079A00001010101010101010101010101010101C7 +:1079B00001010101010101010101010101010101B7 +:1079C00001010101010101010101010101010101A7 +:1079D0000101010101010101010101010101010197 +:1079E0000101010101010101010101010101010187 +:1079F0000101010101010101010101010101010177 +:107A00000101010101010101010101010101010166 +:107A10000101010101010101010101010101010156 +:107A20000101010101010101010101010101010146 +:107A30000101010101010101010101010101010136 +:107A40000101010101010101010101010101010126 +:107A50000101010101010101010101010101010116 +:107A60000101010101010101010101010101010106 +:107A700001010101010101010101010101010101F6 +:107A800001010101010101010101010101010101E6 +:107A900001010101010101010101010101010101D6 +:107AA00001010101010101010101010101010101C6 +:107AB00001010101010101010101010101010101B6 +:107AC00001010101010101010101010101010101A6 +:107AD0000101010101010101010101010101010196 +:107AE0000101010101010101010101010101010186 +:107AF0000101010101010101010101010101010176 +:107B00000101010101010101010101010101010165 +:107B10000101010101010101010101010101010155 +:107B20000101010101010101010101010101010145 +:107B30000101010101010101010101010101010135 +:107B40000101010101010101010101010101010125 +:107B50000101010101010101010101010101010115 +:107B60000101010101010101010101010101010105 +:107B700001010101010101010101010101010101F5 +:107B800001010101010101010101010101010101E5 +:107B900001010101010101010101010101010101D5 +:107BA00001010101010101010101010101010101C5 +:107BB00001010101010101010101010101010101B5 +:107BC00001010101010101010101010101010101A5 +:107BD0000101010101010101010101010101010195 +:107BE0000101010101010101010101010101010185 +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101010101010101010134 +:107C40000101010101010101010101010101010124 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010101010101010101E4 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD0000101010101010101010101010101010194 +:107CE0000101010101010101010101010101010184 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010101010101010101010123 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010101010101010101E3 +:107D900001010101010101010101010101010101D3 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010101010101010101010107 +:1089600001010101010101010101010101010101F7 +:1089700001010101010101010101010101010101E7 +:1089800001010101010101010101010101010101D7 +:1089900001010101010101010101010101010101C7 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010114 +:108C50000101010101010101010101010101010104 +:108C600001010101010101010101010101010101F4 +:108C700001010101010101010101010101010101E4 +:108C800001010101010101010101010101010101D4 +:108C900001010101010101010101010101010101C4 +:108CA00001010101010101010101010101010101B4 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E0000101010101010100000000000000000078 +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D000000000000000000000000000000000008B +:1095E0000000000000000002020202020202020269 +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020202020202020202022A +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202020202029A +:1096B000020202020202020202020202020202028A +:1096C000020202020202020202020202020202027A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A0000202020202020202020202020202020299 +:1097B0000202020202020202020202020202020289 +:1097C0000202020202020202020202020202020279 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:109810000202020202020202020202020202020228 +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020202020298 +:1098B0000202020202020202020202020202020288 +:1098C0000202020202020202020202020202020278 +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B0000202020202020202020202020202020287 +:1099C0000202020202020202020202020202020277 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020202020226 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020202A6 +:109AA0000202020202020202020202020202020296 +:109AB0000202020202020202020202020202020286 +:109AC0000202020202020202020202020202020276 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020202A5 +:109BA0000202020202020202020202020202020295 +:109BB0000202020202020202020202020202020285 +:109BC0000202020202020202020202020202020275 +:109BD0000202020202020202020202020202020265 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020202A4 +:109CA0000202020202020202020202020202020294 +:109CB0000202020202020202020202020202020284 +:109CC0000202020202020202020202020202020274 +:109CD0000202020202020202020202020202020264 +:109CE0000202020202020202020202020202020254 +:109CF0000202020202020202020202020202020244 +:109D00000202020202020202020202020202020233 +:109D10000202020202020202020202020202020223 +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020202020202020202020202020202E3 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020202A3 +:109DA0000202020202020202020202020202020293 +:109DB0000202020202020202020202020202020283 +:109DC0000202020202020202020202020202020273 +:109DD0000202020202020202020202020202020263 +:109DE0000202020202020202020202020202020253 +:109DF0000202020202020202020202020202020243 +:109E00000202020202020202020202020202020232 +:109E10000202020202020202020202020202020222 +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202020202020202E2 +:109E600002020202020202020202020202020202D2 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020202A2 +:109EA0000202020202020202020202020202020292 +:109EB0000202020202020202020202020202020282 +:109EC0000202020202020202020202020202020272 +:109ED0000202020202020202020202020202020262 +:109EE0000202020202020202020202020202020252 +:109EF0000202020202020202020202020202020242 +:109F00000202020202020202020202020202020231 +:109F10000202020202020202020202020202020221 +:109F20000202020202020202020202020202020211 +:109F30000202020202020202020202020202020201 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202020202020202E1 +:109F600002020202020202020202020202020202D1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020202A1 +:109FA0000202020202020202020202020202020291 +:109FB0000202020202020202020202020202020281 +:109FC0000202020202020202020202020202020271 +:109FD0000202020202020202020202020202020261 +:109FE0000202020202020202020202020202020251 +:109FF0000202020202020202020202020202020241 +:10A000000202020202020202020202020202020230 +:10A010000202020202020202020202020202020220 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020202020202020202020202020202D0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020202A0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020280 +:10A0C0000202020202020202020202020202020270 +:10A0D0000202020202020202020202020202020260 +:10A0E0000202020202020202020202020202020250 +:10A0F0000202020202020202020202020202020240 +:10A10000020202020202020202020202020202022F +:10A11000020202020202020202020202020202021F +:10A12000020202020202020202020202020202020F +:10A1300002020202020202020202020202020202FF +:10A1400002020202020202020202020202020202EF +:10A1500002020202020202020202020202020202DF +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A19000020202020202020202020202020202029F +:10A1A000020202020202020202020202020202028F +:10A1B000020202020202020202020202020202027F +:10A1C000020202020202020202020202020202026F +:10A1D000020202020202020202020202020202025F +:10A1E000020202020202020202020202020202024F +:10A1F000020202020202020202020202020202023F +:10A20000020202020202020202020202020202022E +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202020E +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202027E +:10A2C000020202020202020202020202020202026E +:10A2D000020202020202020202020202020202025E +:10A2E000020202020202020202020202020202024E +:10A2F000020202020202020202020202020202023E +:10A30000020202020202020202020202020202022D +:10A31000020202020202020202020202020202021D +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202024D +:10A3F000020202020202020202020202020202023D +:10A40000020202020202020202020202020202022C +:10A41000020202020202020202020202020202021C +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202027C +:10A4C000020202020202020202020202020202026C +:10A4D000020202020202020202020202020202025C +:10A4E000020202020202020202020202020202024C +:10A4F000020202020202020202020202020202023C +:10A50000020202020202020202020202020202022B +:10A51000020202020202020202020202020202021B +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E000020202020202020202020202020202024B +:10A5F000020202020202020202020202020202023B +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E000020202020202020202020202020202024A +:10A6F000020202020202020202020202020202023A +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000202020202020202020202020202020239 +:10A800000202020202020202020202020202020228 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020202A8 +:10A890000202020202020202020202020202020298 +:10A8A0000202020202020202020202020202020288 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202020202020202020202020202EA +:10B6400002020202020202020202020202020202DA +:10B6500002020202020202020202020202020202CA +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020202020202020202020202028A +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C000020202020202020202020202020202025A +:10B6D000020202020202020202020202020202024A +:10B6E000020202020202020202020202020202023A +:10B6F000020202020202020202020202020202022A +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020202020202020202020202C5 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020255 +:10BBD0000202020202020202020202020202020245 +:10BBE0000202020202020202020202020202020235 +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020251 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202023D +:10C3E000020202020202020202020202020202022D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202023C +:10C4E000020202020202020202020202020202022C +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000020202020202020202020202020202022B +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202023A +:10C6E000020202020202020000000000000000003C +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE00000000000000000B700000000000000018E +:10CAF0000101010101010101010101010101010126 +:10CB00000101010101010101010101010101010115 +:10CB10000101010101010101010101010101010105 +:10CB200001010101010101010101010101010101F5 +:10CB300001010101010101010101010101010101E5 +:10CB400001010101010101010101010101010101D5 +:10CB500001010101010101010101010101010101C5 +:10CB600001010101010101010101010101010101B5 +:10CB700001010101010101010101010101010101A5 +:10CB80000101010101010101010101010101010195 +:10CB90000101010101010101010101010101010185 +:10CBA0000101010101010101010101010101010175 +:10CBB0000101010101010101010101010101010165 +:10CBC0000101010101010101010101010101010155 +:10CBD0000101010101010101010101010101010145 +:10CBE0000101010101010101010101010101010135 +:10CBF0000101010101010101010101010101010125 +:10CC00000101010101010101010101010101010114 +:10CC10000101010101010101010101010101010104 +:10CC200001010101010101010101010101010101F4 +:10CC300001010101010101010101010101010101E4 +:10CC400001010101010101010101010101010101D4 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010101A4 +:10CC80000101010101010101010101010101010194 +:10CC90000101010101010101010101010101010184 +:10CCA0000101010101010101010101010101010174 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010101A3 +:10CD80000101010101010101010101010101010193 +:10CD90000101010101010101010101010101010183 +:10CDA0000101010101010101010101010101010173 +:10CDB0000101010101010101010101010101010163 +:10CDC0000101010101010101010101010101010153 +:10CDD0000101010101010101010101010101010143 +:10CDE0000101010101010101010101010101010133 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010101A2 +:10CE80000101010101010101010101010101010192 +:10CE90000101010101010101010101010101010182 +:10CEA0000101010101010101010101010101010172 +:10CEB0000101010101010101010101010101010162 +:10CEC0000101010101010101010101010101010152 +:10CED0000101010101010101010101010101010142 +:10CEE0000101010101010101010101010101010132 +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400001010101010101010101010101010101D1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700001010101010101010101010101010101A1 +:10CF80000101010101010101010101010101010191 +:10CF90000101010101010101010101010101010181 +:10CFA0000101010101010101010101010101010171 +:10CFB0000101010101010101010101010101010161 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010141 +:10CFE0000101010101010101010101010101010131 +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010101010101010101010110 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010101010101010101010101010101C0 +:10D0600001010101010101010101010101010101B0 +:10D0700001010101010101010101010101010101A0 +:10D080000101010101010101010101010101010190 +:10D090000101010101010101010101010101010180 +:10D0A0000101010101010101010101010101010170 +:10D0B0000101010101010101010101010101010160 +:10D0C0000101010101010101010101010101010150 +:10D0D0000101010101010101010101010101010140 +:10D0E0000101010101010101010101010101010130 +:10D0F0000101010101010101010101010101010120 +:10D10000010101010101010101010101010101010F +:10D1100001010101010101010101010101010101FF +:10D1200001010101010101010101010101010101EF +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010101010101AE +:10D27000010101010101010101010101010101019E +:10D28000010101010101010101010101010101018E +:10D29000010101010101010101010101010101017E +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010101FC +:10D4200001010101010101010101010101010101EC +:10D4300001010101010101010101010101010101DC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101017C +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010101CA +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010101AA +:10D67000010101010101010101010101010101019A +:10D68000010101010101010101010101010101018A +:10D69000010101010101010101010101010101017A +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000010101010101010101010101010101014A +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010101A9 +:10D770000101010101010101010101010101010199 +:10D780000101010101010101010101010101010189 +:10D790000101010101010101010101010101010179 +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000101010101010101010101010101010149 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010101010101010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010147 +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010101010101010101010146 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF0000101010101010101010101010101010115 +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010184 +:10DC90000101010101010101010101010101010174 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010101010101010101010114 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010101010101010101010173 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE90000101010101010101010101010101010172 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101010101010101010101DF +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101010101010101010101AF +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101010101010101DC +:10E4300001010101010101010101010101010101CC +:10E4400001010101010101010101010101010101BC +:10E4500001010101010101010101010101010101AC +:10E46000010101010101010101010101010101019C +:10E47000010101010101010101010101010101018C +:10E48000010101010101010101010101010101017C +:10E49000010101010101010101010101010101016C +:10E4A000010101010101010101010101010101015C +:10E4B000010101010101010101010101010101014C +:10E4C000010101010101010101010101010101013C +:10E4D000010101010101010101010101010101012C +:10E4E000010101010101010101010101010101011C +:10E4F000010101010101010101010101010101010C +:10E5000001010101010101010101010101010101FB +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010101DB +:10E5300001010101010101010101010101010101CB +:10E5400001010101010101010101010101010101BB +:10E5500001010101010101010101010101010101AB +:10E56000010101010101010101010101010101019B +:10E57000010101010101010101010101010101018B +:10E58000010101010101010101010101010101017B +:10E59000010101010101010101010101010101016B +:10E5A000010101010101010101010101010101015B +:10E5B000010101010101010101010101010101014B +:10E5C000010101010101010101010101010101013B +:10E5D000010101010101010101010101010101012B +:10E5E000010101010101010101010101010101011B +:10E5F000010101010101010101010101010101010B +:10E6000001010101010101010101010101010101FA +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101010101010101010101BA +:10E6500001010101010101010101010101010101AA +:10E66000010101010101010101010101010101019A +:10E67000010101010101010101010101010101018A +:10E68000010101010101010101010101010101017A +:10E69000010101010101010101010101010101016A +:10E6A000010101010101010101010101010101015A +:10E6B000010101010101010101010101010101014A +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E000010101010101010101010101010101011A +:10E6F000010101010101010101010101010101010A +:10E7000001010101010101010101010101010101F9 +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010101010101010101D9 +:10E7300001010101010101010101010101010101C9 +:10E7400001010101010101010101010101010101B9 +:10E7500001010101010101010101010101010101A9 +:10E760000101010101010101010101010101010199 +:10E770000101010101010101010101010101010189 +:10E780000101010101010101010101010101010179 +:10E790000101010101010101010101010101010169 +:10E7A0000101010101010101010101010101010159 +:10E7B0000101010101010101010101010101010149 +:10E7C0000101010101010101010101010101010139 +:10E7D0000101010101010101010101010101010129 +:10E7E0000101010101010101010101010101010119 +:10E7F0000101010101010101010101010101010109 +:10E8000001010101010101010101010101010101F8 +:10E8100001010101010101010101010101010101E8 +:10E8200001010101010101010101010101010101D8 +:10E8300001010101010101010101010101010101C8 +:10E8400001010101010101010101010101010101B8 +:10E8500001010101010101010101010101010101A8 +:10E860000101010101010101010101010101010198 +:10E870000101010101010101010101010101010188 +:10E880000101010101010101010101010101010178 +:10E890000101010101010101010101010101010168 +:10E8A0000101010101010101010101010101010158 +:10E8B0000101010101010101010101010101010148 +:10E8C0000101010101010101010101010101010138 +:10E8D0000101010101010101010101010101010128 +:10E8E0000101010101010101010101010101010118 +:10E8F0000101010101010101010101010101010108 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010101010101010101D7 +:10E9300001010101010101010101010101010101C7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010101010101010101010177 +:10E990000101010101010101010101010101010167 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010101010101010101D6 +:10EA300001010101010101010101010101010101C6 +:10EA400001010101010101010101010101010101B6 +:10EA500001010101010101010101010101010101A6 +:10EA60000101010101010101010101010101010196 +:10EA70000101010101010101010101010101010186 +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010101010101010101010166 +:10EAA0000101010101010101010101010101010156 +:10EAB0000101010101010101010101010101010146 +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101010101010101010101F5 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101010101010101010101D5 +:10EB300001010101010101010101010101010101C5 +:10EB400001010101010101010101010101010101B5 +:10EB500001010101010101010101010101010101A5 +:10EB60000101010101010101010101010101010195 +:10EB70000101010101010101010101010101010185 +:10EB80000101010101010101010101010101010175 +:10EB90000101010101010101010101010101010165 +:10EBA0000101010101010101010101010101010155 +:10EBB0000101010101010101010101010101010145 +:10EBC0000101010101010101010101010101010135 +:10EBD0000101010101010101010101010101010125 +:10EBE0000101010101010101010101010101010115 +:10EBF0000101010101010101010101010101010105 +:10EC000001010101010101010101010101010101F4 +:10EC100001010101010101010101010101010101E4 +:10EC200001010101010101010101010101010101D4 +:10EC300001010101010101010101010101010101C4 +:10EC400001010101010101010101010101010101B4 +:10EC500001010101010101010101010101010101A4 +:10EC60000101010101010101010101010101010194 +:10EC70000101010101010101010101010101010184 +:10EC80000101010101010101010101010101010174 +:10EC90000101010101010101010101010101010164 +:10ECA0000101010101010101010101010101010154 +:10ECB0000101010101010101010101010101010144 +:10ECC0000101010101010101010101010101010134 +:10ECD0000101010101010101010101010101010124 +:10ECE0000101010101010101010101010101010114 +:10ECF0000101010101010101010101010101010104 +:10ED000001010101010101010101010101010101F3 +:10ED100001010101010101010101010101010101E3 +:10ED200001010101010101010101010101010101D3 +:10ED300001010101010101010101010101010101C3 +:10ED400001010101010101010101010101010101B3 +:10ED500001010101010101010101010101010101A3 +:10ED60000101010101010101010101010101010193 +:10ED70000101010101010101010101010101010183 +:10ED80000101010101010101010101010101010173 +:10ED90000101010101010101010101010101010163 +:10EDA0000101010101010101010101010101010153 +:10EDB0000101010101010101010101010101010143 +:10EDC0000101010101010101010101010101010133 +:10EDD0000101010101010101010101010101010123 +:10EDE0000101010101010101010101010101010113 +:10EDF0000101010101010101010101010101010103 +:10EE000001010101010101010101010101010101F2 +:10EE100001010101010101010101010101010101E2 +:10EE200001010101010101010101010101010101D2 +:10EE300001010101010101010101010101010101C2 +:10EE400001010101010101010101010101010101B2 +:10EE500001010101010101010101010101010101A2 +:10EE60000101010101010101010101010101010192 +:10EE70000101010101010101010101010101010182 +:10EE80000101010101010101010101010101010172 +:10EE90000101010101010101010101010101010162 +:10EEA0000101010101010101010101010101010152 +:10EEB0000101010101010101010101010101010142 +:10EEC0000101010101010101010101010101010132 +:10EED0000101010101010101010101010101010122 +:10EEE0000101010101010101010101010101010112 +:10EEF0000101010101010101010101010101010102 +:10EF000001010101010101010101010101010101F1 +:10EF100001010101010101010101010101010101E1 +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101010101010101010101C1 +:10EF400001010101010101010101010101010101B1 +:10EF500001010101010101010101010101010101A1 +:10EF60000101010101010101010101010101010191 +:10EF70000101010101010101010101010101010181 +:10EF80000101010101010101010101010101010171 +:10EF90000101010101010101010101010101010161 +:10EFA0000101010101010101010101010101010151 +:10EFB0000101010101010101010101010101010141 +:10EFC0000101010101010101010101010101010131 +:10EFD0000101010101010101010101010101010121 +:10EFE0000101010101010101010101010101010111 +:10EFF0000101010101010101010101010101010101 +:10F0000001010101010101010101010101010101F0 +:10F0100001010101010101010101010101010101E0 +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101010101010101010101C0 +:10F0400001010101010101010101010101010101B0 +:10F0500001010101010101010101010101010101A0 +:10F060000101010101010101010101010101010190 +:10F070000101010101010101010101010101010180 +:10F080000101010101010101010101010101010170 +:10F090000101010101010101010101010101010160 +:10F0A0000101010101010101010101010101010150 +:10F0B0000101010101010101010101010101010140 +:10F0C0000101010101010101010101010101010130 +:10F0D0000101010101010101010101010101010120 +:10F0E0000101010101010101010101010101010110 +:10F0F0000101010101010101010101010101010100 +:10F1000001010101010101010101010101010101EF +:10F1100001010101010101010101010101010101DF +:10F1200001010101010101010101010101010101CF +:10F1300001010101010101010101010101010101BF +:10F1400001010101010101010101010101010101AF +:10F15000010101010101010101010101010101019F +:10F16000010101010101010101010101010101018F +:10F17000010101010101010101010101010101017F +:10F18000010101010101010101010101010101016F +:10F19000010101010101010101010101010101015F +:10F1A000010101010101010101010101010101014F +:10F1B000010101010101010101010101010101013F +:10F1C000010101010101010101010101010101012F +:10F1D000010101010101010101010101010101011F +:10F1E000010101010101010101010101010101010F +:10F1F00001010101010101010101010101010101FF +:10F2000001010101010101010101010101010101EE +:10F2100001010101010101010101010101010101DE +:10F2200001010101010101010101010101010101CE +:10F2300001010101010101010101010101010101BE +:10F2400001010101010101010101010101010101AE +:10F25000010101010101010101010101010101019E +:10F26000010101010101010101010101010101018E +:10F27000010101010101010101010101010101017E +:10F28000010101010101010101010101010101016E +:10F29000010101010101010101010101010101015E +:10F2A000010101010101010101010101010101014E +:10F2B000010101010101010101010101010101013E +:10F2C000010101010101010101010101010101012E +:10F2D000010101010101010101010101010101011E +:10F2E000010101010101010101010101010101010E +:10F2F00001010101010101010101010101010101FE +:10F3000001010101010101010101010101010101ED +:10F3100001010101010101010101010101010101DD +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010101010101010101019D +:10F36000010101010101010101010101010101018D +:10F37000010101010101010101010101010101017D +:10F38000010101010101010101010101010101016D +:10F39000010101010101010101010101010101015D +:10F3A000010101010101010101010101010101014D +:10F3B000010101010101010101010101010101013D +:10F3C000010101010101010101010101010101012D +:10F3D000010101010101010101010101010101011D +:10F3E000010101010101010101010101010101000E +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000217 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020202020202020202020202B8 +:10F8300002020202020202020202020202020202A8 +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202020202020202020202A7 +:10F940000202020202020202020202020202020297 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020277 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020202020202020202020243 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202020202020202020223 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202020202020242 +:10FEA0000202020202020202020202020202020232 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202020202020241 +:10FFA0000202020202020202020202020202020231 +:10FFB0000202020202020202020202020202020221 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:020000022000DC +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C000020202020202020202020202020202020F +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000020202020202020202020202020202023E +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C000020202020202020202020202020202020E +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202020202020202020D +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020202020202020202023C +:1004A000020202020202020202020202020202022C +:1004B000020202020202020202020202020202021C +:1004C000020202020202020202020202020202020C +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202024B +:10059000020202020202020202020202020202023B +:1005A000020202020202020202020202020202022B +:1005B000020202020202020202020202020202021B +:1005C000020202020202020202020202020202020B +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202024A +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020202020202020202021A +:1006C000020202020202020202020202020202020A +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:100770000202020202020202020202020202020259 +:100780000202020202020202020202020202020249 +:100790000202020202020202020202020202020239 +:1007A0000202020202020202020202020202020229 +:1007B0000202020202020202020202020202020219 +:1007C0000202020202020202020202020202020209 +:1007D00002020202020202020202020202020202F9 +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020248 +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B0000202020202020202020202020202020218 +:1008C0000202020202020202020202020202020208 +:1008D00002020202020202020202020202020202F8 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020247 +:100990000202020202020202020202020202020237 +:1009A0000202020202020202020202020202020227 +:1009B0000202020202020202020202020202020217 +:1009C0000202020202020202020202020202020207 +:1009D00002020202020202020202020202020202F7 +:1009E00002020202020202020202020202020202E7 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020202020202020202020226 +:100AB0000202020202020202020202020202020216 +:100AC0000202020202020202020202020202020206 +:100AD00002020202020202020202020202020202F6 +:100AE00002020202020202020202020202020202E6 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202020202020202020205 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A000020202020202020202020202020202021A +:1016B000020202020202020202020202020202020A +:1016C00002020202020202020202020202020202FA +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202020202020202020202DA +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A0000202020202020202020202020202020219 +:1017B0000202020202020202020202020202020209 +:1017C00002020202020202020202020202020202F9 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202020202020202020202D9 +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A0000202020202020202020202020202020218 +:1018B0000202020202020202020202020202020208 +:1018C00002020202020202020202020202020202F8 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202020202020202020202D8 +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020202A7 +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020202020202020202020217 +:1019B0000202020202020202020202020202020207 +:1019C00002020202020202020202020202020202F7 +:1019D00002020202020202020202020202020202E7 +:1019E00002020202020202020202020202020202D7 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000202020202020202020202020202020216 +:101AB0000202020202020202020202020202020206 +:101AC00002020202020202020202020202020202F6 +:101AD00002020202020202020202020202020202E6 +:101AE00002020202020202020202020202020202D6 +:101AF00002020202020202020202020202020202C6 +:101B000002020202020202020202020202020202B5 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA0000202020202020202020202020202020215 +:101BB0000202020202020202020202020202020205 +:101BC00002020202020202020202020202020202F5 +:101BD00002020202020202020202020202020202E5 +:101BE00002020202020202020202020202020202D5 +:101BF00002020202020202020202020202020202C5 +:101C000002020202020202020202020202020202B4 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA0000202020202020202020202020202020214 +:101CB0000202020202020202020202020202020204 +:101CC00002020202020202020202020202020202F4 +:101CD00002020202020202020202020202020202E4 +:101CE00002020202020202020202020202020202D4 +:101CF00002020202020202020202020202020202C4 +:101D000002020202020202020202020202020202B3 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020202020203 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020202D3 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202020202 +:101EC00002020202020202020202020202020202F2 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020202D2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020200D2 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00000000000000000000000000000000000FD +:1023E00000000000000000000000000000000000ED +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000001E8 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010147 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010101010127 +:1029A0000101010101010101010101010101010117 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010146 +:102A80000101010101010101010101010101010136 +:102A90000101010101010101010101010101010126 +:102AA0000101010101010101010101010101010116 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010165 +:102B60000101010101010101010101010101010155 +:102B70000101010101010101010101010101010145 +:102B80000101010101010101010101010101010135 +:102B90000101010101010101010101010101010125 +:102BA0000101010101010101010101010101010115 +:102BB0000101010101010101010101010101010105 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101010101010101010101E5 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000101010101010101010101010101010164 +:102C60000101010101010101010101010101010154 +:102C70000101010101010101010101010101010144 +:102C80000101010101010101010101010101010134 +:102C90000101010101010101010101010101010124 +:102CA0000101010101010101010101010101010114 +:102CB0000101010101010101010101010101010104 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010173 +:102D50000101010101010101010101010101010163 +:102D60000101010101010101010101010101010153 +:102D70000101010101010101010101010101010143 +:102D80000101010101010101010101010101010133 +:102D90000101010101010101010101010101010123 +:102DA0000101010101010101010101010101010113 +:102DB0000101010101010101010101010101010103 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010132 +:102E90000101010101010101010101010101010122 +:102EA0000101010101010101010101010101010112 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010101D2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:10317000010101010101010101010101010101013F +:10318000010101010101010101010101010101012F +:10319000010101010101010101010101010101011F +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000010101010101010101010101010101014E +:10327000010101010101010101010101010101013E +:10328000010101010101010101010101010101012E +:10329000010101010101010101010101010101011E +:1032A000010101010101010101010101010101010E +:1032B00001010101010101010101010101010101FE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000010101010101010101010101010101011D +:1033A000010101010101010101010101010101010D +:1033B00001010101010101010101010101010101FD +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000010101010101010101010101010101017C +:10344000010101010101010101010101010101016C +:10345000010101010101010101010101010101015C +:10346000010101010101010101010101010101014C +:10347000010101010101010101010101010101013C +:10348000010101010101010101010101010101012C +:10349000010101010101010101010101010101011C +:1034A000010101010101010101010101010101010C +:1034B00001010101010101010101010101010101FC +:1034C00001010101010101010101010101010101EC +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101014A +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A000010101010101010101010101010101010A +:1036B00001010101010101010101010101010101FA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010101F8 +:1038C00001010101010101010101010101010101E8 +:1038D00001010101010101010101010101010101D8 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010101010101010101010167 +:103950000101010101010101010101010101010157 +:103960000101010101010101010101010101010147 +:103970000101010101010101010101010101010137 +:103980000101010101010101010101010101010127 +:103990000101010101010101010101010101010117 +:1039A0000101010101010101010101010101010107 +:1039B00001010101010101010101010101010101F7 +:1039C00001010101010101010101010101010101E7 +:1039D00001010101010101010101010101010101D7 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000101010101010101010101010101010176 +:103A40000101010101010101010101010101010166 +:103A50000101010101010101010101010101010156 +:103A60000101010101010101010101010101010146 +:103A70000101010101010101010101010101010136 +:103A80000101010101010101010101010101010126 +:103A90000101010101010101010101010101010116 +:103AA0000101010101010101010101010101010106 +:103AB00001010101010101010101010101010101F6 +:103AC00001010101010101010101010101010101E6 +:103AD00001010101010101010101010101010101D6 +:103AE00001010101010101010101010101010101C6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000101010101010101010101010101010135 +:103B80000101010101010101010101010101010125 +:103B90000101010101010101010101010101010115 +:103BA0000101010101010101010101010101010105 +:103BB00001010101010101010101010101010101F5 +:103BC00001010101010101010101010101010101E5 +:103BD00001010101010101010101010101010101D5 +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C60000101010101010101010101010101010144 +:103C70000101010101010101010101010101010134 +:103C80000101010101010101010101010101010124 +:103C90000101010101010101010101010101010114 +:103CA0000101010101010101010101010101010104 +:103CB00001010101010101010101010101010101F4 +:103CC00001010101010101010101010101010101E4 +:103CD00001010101010101010101010101010101D4 +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010101B4 +:103D000001010101010101010101010101010101A3 +:103D10000101010101010101010101010101010193 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000101010101010101010101010101010103 +:103DB00001010101010101010101010101010101F3 +:103DC00001010101010101010101010101010101E3 +:103DD00001010101010101010101010101010101D3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101010101010101010101B3 +:103E000001010101010101010101010101010101A2 +:103E10000101010101010101010101010101010192 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010172 +:103E40000101010101010101010101010101010162 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000101010101010101010101010101010112 +:103EA0000101010101010101010101010101010102 +:103EB00001010101010101010101010101010101F2 +:103EC00001010101010101010101010101010101E2 +:103ED00001010101010101010101010101010101D2 +:103EE00001010101010101010101010101010101C2 +:103EF00001010101010101010101010101010101B2 +:103F000001010101010101010101010101010101A1 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010171 +:103F40000101010101010101010101010101010161 +:103F50000101010101010101010101010101010151 +:103F60000101010101010101010101010101010141 +:103F70000101010101010101010101010101010131 +:103F80000101010101010101010101010101010121 +:103F90000101010101010101010101010101010111 +:103FA0000101010101010101010101010101010101 +:103FB00001010101010101010101010101010101F1 +:103FC00001010101010101010101010101010101E1 +:103FD00001010101010101010101010101010101D1 +:103FE00001010101010101010101010101010101C1 +:103FF00001010101010101010101010101010101B1 +:1040000001010101010101010101010101010101A0 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:104030000101010101010101010101010101010170 +:104040000101010101010101010101010101010160 +:104050000101010101010101010101010101010150 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:104080000101010101010101010101010101010120 +:104090000101010101010101010101010101010110 +:1040A0000101010101010101010101010101010100 +:1040B00001010101010101010101010101010101F0 +:1040C00001010101010101010101010101010101E0 +:1040D00001010101010101010101010101010101D0 +:1040E00001010101010101010101010101010101C0 +:1040F00001010101010101010101010101010101B0 +:10410000010101010101010101010101010101019F +:10411000010101010101010101010101010101018F +:10412000010101010101010101010101010101017F +:10413000010101010101010101010101010101016F +:10414000010101010101010101010101010101015F +:10415000010101010101010101010101010101014F +:10416000010101010101010101010101010101013F +:10417000010101010101010101010101010101012F +:10418000010101010101010101010101010101011F +:10419000010101010101010101010101010101010F +:1041A00001010101010101010101010101010101FF +:1041B00001010101010101010101010101010101EF +:1041C00001010101010101010101010101010101DF +:1041D00001010101010101010101010101010101CF +:1041E00001010101010101010101010101010101BF +:1041F00001010101010101010101010101010101AF +:10420000010101010101010101010101010101019E +:10421000010101010101010101010101010101018E +:10422000010101010101010101010101010101017E +:10423000010101010101010101010101010101016E +:10424000010101010101010101010101010101015E +:10425000010101010101010101010101010101014E +:10426000010101010101010101010101010101013E +:10427000010101010101010101010101010101012E +:10428000010101010101010101010101010101011E +:10429000010101010101010101010101010101010E +:1042A00001010101010101010101010101010101FE +:1042B00001010101010101010101010101010101EE +:1042C00001010101010101010101010101010101DE +:1042D00001010101010101010101010101010101CE +:1042E00001010101010101010101010101010101BE +:1042F00001010101010101010101010101010101AE +:10430000010101010101010101010101010101019D +:10431000010101010101010101010101010101018D +:10432000010101010101010101010101010101017D +:10433000010101010101010101010101010101016D +:10434000010101010101010101010101010101015D +:10435000010101010101010101010101010101014D +:10436000010101010101010101010101010101013D +:10437000010101010101010101010101010101012D +:10438000010101010101010101010101010101011D +:10439000010101010101010101010101010101010D +:1043A00001010101010101010101010101010101FD +:1043B00001010101010101010101010101010101ED +:1043C00001010101010101010101010101010101DD +:1043D00001010101010101010101010101010101CD +:1043E00001010101010101010101010101010101BD +:1043F00001010101010101010101010101010101AD +:10440000010101010101010101010101010101019C +:10441000010101010101010101010101010101018C +:10442000010101010101010101010101010101017C +:10443000010101010101010101010101010101016C +:10444000010101010101010101010101010101015C +:10445000010101010101010101010101010101014C +:10446000010101010101010101010101010101013C +:10447000010101010101010101010101010101012C +:10448000010101010101010101010101010101011C +:10449000010101010101010101010101010101010C +:1044A00001010101010101010101010101010101FC +:1044B00001010101010101010101010101010101EC +:1044C00001010101010101010101010101010101DC +:1044D00001010101010101010101010101010101CC +:1044E00001010101010101010101010101010101BC +:1044F00001010101010101010101010101010101AC +:10450000010101010101010101010101010101019B +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101011B +:10459000010101010101010101010101010101010B +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101010101010101010101EB +:1045C00001010101010101010101010101010101DB +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:10468000010101010101010101010101010101011A +:10469000010101010101010101010101010101010A +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010101EA +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010100B1 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000002BA +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020202020202020202020202020202DB +:1055B00002020202020202020202020202020202CB +:1055C00002020202020202020202020202020202BB +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020202020202020202020202020202027A +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020202020202020202020202020202DA +:1056B00002020202020202020202020202020202CA +:1056C00002020202020202020202020202020202BA +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020202020202020202D8 +:1058B00002020202020202020202020202020202C8 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020202020202020202D7 +:1059B00002020202020202020202020202020202C7 +:1059C00002020202020202020202020202020202B7 +:1059D00002020202020202020202020202020202A7 +:1059E0000202020202020202020202020202020297 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A40000202020202020202020202020202020236 +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002020202020202020202020202020202E6 +:105AA00002020202020202020202020202020202D6 +:105AB00002020202020202020202020202020202C6 +:105AC00002020202020202020202020202020202B6 +:105AD00002020202020202020202020202020202A6 +:105AE0000202020202020202020202020202020296 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020202020202020202020202020202E5 +:105BA00002020202020202020202020202020202D5 +:105BB00002020202020202020202020202020202C5 +:105BC00002020202020202020202020202020202B5 +:105BD00002020202020202020202020202020202A5 +:105BE0000202020202020202020202020202020295 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020202020202020202020202020202E4 +:105CA00002020202020202020202020202020202D4 +:105CB00002020202020202020202020202020202C4 +:105CC00002020202020202020202020202020202B4 +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202020202020202020294 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020202020202020202020202E3 +:105DA00002020202020202020202020202020202D3 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020202020202020202B3 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202020202020202020293 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020202B2 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202020202020202020292 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202020286 +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020202020285 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020202B4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202020202020202020284 +:107CE0000202020202020202020202020202020274 +:107CF0000202020202020202020202020202020264 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020202020202020283 +:107DE0000202020202020202020202020202020075 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000B7D8 +:1081F0000000000000000001010101010101010176 +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010101010101010101010107 +:1089600001010101010101010101010101010101F7 +:1089700001010101010101010101010101010101E7 +:1089800001010101010101010101010101010101D7 +:1089900001010101010101010101010101010101C7 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010114 +:108C50000101010101010101010101010101010104 +:108C600001010101010101010101010101010101F4 +:108C700001010101010101010101010101010101E4 +:108C800001010101010101010101010101010101D4 +:108C900001010101010101010101010101010101C4 +:108CA00001010101010101010101010101010101B4 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010101DD +:10A3700001010101010101010101010101010101CD +:10A3800001010101010101010101010101010101BD +:10A3900001010101010101010101010101010101AD +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010101DC +:10A4700001010101010101010101010101010101CC +:10A4800001010101010101010101010101010101BC +:10A4900001010101010101010101010101010101AC +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800001010101010101010101010101010101BB +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010101010101010101010101010101BA +:10A6900001010101010101010101010101010101AA +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010101B9 +:10A7900001010101010101010101010101010101A9 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF000010101010101010000000000000000004F +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000002020202020202020240 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202020202020202020202020202EA +:10B6400002020202020202020202020202020202DA +:10B6500002020202020202020202020202020202CA +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020202020202020202020202028A +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C000020202020202020202020202020202025A +:10B6D000020202020202020202020202020202024A +:10B6E000020202020202020202020202020202023A +:10B6F000020202020202020202020202020202022A +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020202020202020202020202C5 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020255 +:10BBD0000202020202020202020202020202020245 +:10BBE0000202020202020202020202020202020235 +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020251 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202023D +:10C3E000020202020202020202020202020202022D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202023C +:10C4E000020202020202020202020202020202022C +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000020202020202020202020202020202022B +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202023A +:10C6E000020202020202020202020202020202022A +:10C6F000020202020202020202020202020202021A +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020202020202020202020202020249 +:10C7D0000202020202020202020202020202020239 +:10C7E0000202020202020202020202020202020229 +:10C7F0000202020202020202020202020202020219 +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020202020202020202020202020248 +:10C8D0000202020202020202020202020202020238 +:10C8E0000202020202020202020202020202020228 +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020257 +:10C9C0000202020202020202020202020202020247 +:10C9D0000202020202020202020202020202020237 +:10C9E0000202020202020202020202020202020227 +:10C9F0000202020202020202020202020202020217 +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020233 +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202020202020202020202020213 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020202020252 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020232 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202020202020202020202020212 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020231 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202020202020202020202020211 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202020202020202020202020202020230 +:10D0E0000202020202020202020202020202020220 +:10D0F0000202020202020202020202020202020210 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D17000020202020202020202020202020202028F +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020202020202020202020202023F +:10D1D000020202020202020202020202020202022F +:10D1E000020202020202020202020202020202021F +:10D1F000020202020202020202020202020202020F +:10D2000002020202020202020202020202020202FE +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D000020202020202020202020202020202022E +:10D2E000020202020202020202020202020202021E +:10D2F000020202020202020202020202020202020E +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020202020202020202020202CD +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020202020202020202020202025D +:10D3B000020202020202020202020202020202024D +:10D3C000020202020202020202020202020202023D +:10D3D000020202020202020202020202020202022D +:10D3E000020202020202020202020202020202021D +:10D3F000020202020202020202020202020202020D +:10D4000002020202020202020202020202020202FC +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020202DC +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202020202020202025C +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020202020202020202023C +:10D4D000020202020202020202020202020202022C +:10D4E000020202020202020202020202020202021C +:10D4F000020202020202020202020202020202020C +:10D5000002020202020202020202020202020202FB +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020202020202020202020202CB +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A000020202020202020202020202020202025B +:10D5B000020202020202020202020202020202024B +:10D5C000020202020202020202020202020202023B +:10D5D000020202020202020202020202020202022B +:10D5E000020202020202020202020202020202021B +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B000020202020202020202020202020202024A +:10D6C000020202020202020202020202020202023A +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020202020202020202020239 +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F000020202020202020000000000000000001B +:10D800000000000000000000000000000000000018 +:10D810000000000000000000000000000000000008 +:10D8200000000000000000000000000000000000F8 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000000000000000000F7 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000001010101010101010119 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101010101010101010101DF +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101010101010101010101AF +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101010101010101DC +:10E4300001010101010101010101010101010101CC +:10E4400001010101010101010101010101010101BC +:10E4500001010101010101010101010101010101AC +:10E46000010101010101010101010101010101019C +:10E47000010101010101010101010101010101018C +:10E48000010101010101010101010101010101017C +:10E49000010101010101010101010101010101016C +:10E4A000010101010101010101010101010101015C +:10E4B000010101010101010101010101010101014C +:10E4C000010101010101010101010101010101013C +:10E4D000010101010101010101010101010101012C +:10E4E000010101010101010101010101010101011C +:10E4F000010101010101010101010101010101010C +:10E5000001010101010101010101010101010101FB +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010101DB +:10E5300001010101010101010101010101010101CB +:10E5400001010101010101010101010101010101BB +:10E5500001010101010101010101010101010101AB +:10E56000010101010101010101010101010101019B +:10E57000010101010101010101010101010101018B +:10E58000010101010101010101010101010101017B +:10E59000010101010101010101010101010101016B +:10E5A000010101010101010101010101010101015B +:10E5B000010101010101010101010101010101014B +:10E5C000010101010101010101010101010101013B +:10E5D000010101010101010101010101010101012B +:10E5E000010101010101010101010101010101011B +:10E5F000010101010101010101010101010101010B +:10E6000001010101010101010101010101010101FA +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101010101010101010101BA +:10E6500001010101010101010101010101010101AA +:10E66000010101010101010101010101010101019A +:10E67000010101010101010101010101010101018A +:10E68000010101010101010101010101010101017A +:10E69000010101010101010101010101010101016A +:10E6A000010101010101010101010101010101015A +:10E6B000010101010101010101010101010101014A +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E000010101010101010101010101010101011A +:10E6F000010101010101010101010101010101010A +:10E7000001010101010101010101010101010101F9 +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010101010101010101D9 +:10E7300001010101010101010101010101010101C9 +:10E7400001010101010101010101010101010101B9 +:10E7500001010101010101010101010101010101A9 +:10E760000101010101010101010101010101010199 +:10E770000101010101010101010101010101010189 +:10E780000101010101010101010101010101010179 +:10E790000101010101010101010101010101010169 +:10E7A0000101010101010101010101010101010159 +:10E7B0000101010101010101010101010101010149 +:10E7C0000101010101010101010101010101010139 +:10E7D0000101010101010101010101010101010129 +:10E7E0000101010101010101010101010101010119 +:10E7F0000101010101010101010101010101010109 +:10E8000001010101010101010101010101010101F8 +:10E8100001010101010101010101010101010101E8 +:10E8200001010101010101010101010101010101D8 +:10E8300001010101010101010101010101010101C8 +:10E8400001010101010101010101010101010101B8 +:10E8500001010101010101010101010101010101A8 +:10E860000101010101010101010101010101010198 +:10E870000101010101010101010101010101010188 +:10E880000101010101010101010101010101010178 +:10E890000101010101010101010101010101010168 +:10E8A0000101010101010101010101010101010158 +:10E8B0000101010101010101010101010101010148 +:10E8C0000101010101010101010101010101010138 +:10E8D0000101010101010101010101010101010128 +:10E8E0000101010101010101010101010101010118 +:10E8F0000101010101010101010101010101010108 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010101010101010101D7 +:10E9300001010101010101010101010101010101C7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010101010101010101010177 +:10E990000101010101010101010101010101010167 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010101010101010101D6 +:10EA300001010101010101010101010101010101C6 +:10EA400001010101010101010101010101010101B6 +:10EA500001010101010101010101010101010101A6 +:10EA60000101010101010101010101010101010196 +:10EA70000101010101010101010101010101010186 +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010101010101010101010166 +:10EAA0000101010101010101010101010101010156 +:10EAB0000101010101010101010101010101010146 +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101010101010101010101F5 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101010101010101010101D5 +:10EB300001010101010101010101010101010101C5 +:10EB400001010101010101010101010101010101B5 +:10EB500001010101010101010101010101010101A5 +:10EB60000101010101010101010101010101010195 +:10EB70000101010101010101010101010101010185 +:10EB80000101010101010101010101010101010175 +:10EB90000101010101010101010101010101010165 +:10EBA0000101010101010101010101010101010155 +:10EBB0000101010101010101010101010101010145 +:10EBC0000101010101010101010101010101010135 +:10EBD0000101010101010101010101010101010125 +:10EBE0000101010101010101010101010101010115 +:10EBF0000101010101010101010101010101010105 +:10EC000001010101010101010101010101010101F4 +:10EC100001010101010101010101010101010101E4 +:10EC200001010101010101010101010101010101D4 +:10EC300001010101010101010101010101010101C4 +:10EC400001010101010101010101010101010101B4 +:10EC500001010101010101010101010101010101A4 +:10EC60000101010101010101010101010101010194 +:10EC70000101010101010101010101010101010184 +:10EC80000101010101010101010101010101010174 +:10EC90000101010101010101010101010101010164 +:10ECA0000101010101010101010101010101010154 +:10ECB0000101010101010101010101010101010144 +:10ECC0000101010101010101010101010101010134 +:10ECD0000101010101010101010101010101010124 +:10ECE0000101010101010101010101010101010114 +:10ECF0000101010101010101010101010101010104 +:10ED000001010101010101010101010101010101F3 +:10ED100001010101010101010101010101010101E3 +:10ED200001010101010101010101010101010101D3 +:10ED300001010101010101010101010101010101C3 +:10ED400001010101010101010101010101010101B3 +:10ED500001010101010101010101010101010101A3 +:10ED60000101010101010101010101010101010193 +:10ED70000101010101010101010101010101010183 +:10ED80000101010101010101010101010101010173 +:10ED90000101010101010101010101010101010163 +:10EDA0000101010101010101010101010101010153 +:10EDB0000101010101010101010101010101010143 +:10EDC0000101010101010101010101010101010133 +:10EDD0000101010101010101010101010101010123 +:10EDE0000101010101010101010101010101010113 +:10EDF0000101010101010101010101010101010103 +:10EE000001010101010101010101010101010101F2 +:10EE100001010101010101010101010101010101E2 +:10EE200001010101010101010101010101010101D2 +:10EE300001010101010101010101010101010101C2 +:10EE400001010101010101010101010101010101B2 +:10EE500001010101010101010101010101010101A2 +:10EE60000101010101010101010101010101010192 +:10EE70000101010101010101010101010101010182 +:10EE80000101010101010101010101010101010172 +:10EE90000101010101010101010101010101010162 +:10EEA0000101010101010101010101010101010152 +:10EEB0000101010101010101010101010101010142 +:10EEC0000101010101010101010101010101010132 +:10EED0000101010101010101010101010101010122 +:10EEE0000101010101010101010101010101010112 +:10EEF0000101010101010101010101010101010102 +:10EF000001010101010101010101010101010101F1 +:10EF100001010101010101010101010101010101E1 +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101010101010101010101C1 +:10EF400001010101010101010101010101010101B1 +:10EF500001010101010101010101010101010101A1 +:10EF60000101010101010101010101010101010191 +:10EF70000101010101010101010101010101010181 +:10EF80000101010101010101010101010101010171 +:10EF90000101010101010101010101010101010161 +:10EFA0000101010101010101010101010101010151 +:10EFB0000101010101010101010101010101010141 +:10EFC0000101010101010101010101010101010131 +:10EFD0000101010101010101010101010101010121 +:10EFE0000101010101010101010101010101010111 +:10EFF0000101010101010101010101010101010101 +:10F0000001010101010101010101010101010101F0 +:10F0100001010101010101010101010101010101E0 +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101010101010101010101C0 +:10F0400001010101010101010101010101010101B0 +:10F0500001010101010101010101010101010101A0 +:10F060000101010101010101010101010101010190 +:10F070000101010101010101010101010101010180 +:10F080000101010101010101010101010101010170 +:10F090000101010101010101010101010101010160 +:10F0A0000101010101010101010101010101010150 +:10F0B0000101010101010101010101010101010140 +:10F0C0000101010101010101010101010101010130 +:10F0D0000101010101010101010101010101010120 +:10F0E0000101010101010101010101010101010110 +:10F0F0000101010101010101010101010101010100 +:10F1000001010101010101010101010101010101EF +:10F1100001010101010101010101010101010101DF +:10F1200001010101010101010101010101010101CF +:10F1300001010101010101010101010101010101BF +:10F1400001010101010101010101010101010101AF +:10F15000010101010101010101010101010101019F +:10F16000010101010101010101010101010101018F +:10F17000010101010101010101010101010101017F +:10F18000010101010101010101010101010101016F +:10F19000010101010101010101010101010101015F +:10F1A000010101010101010101010101010101014F +:10F1B000010101010101010101010101010101013F +:10F1C000010101010101010101010101010101012F +:10F1D000010101010101010101010101010101011F +:10F1E000010101010101010101010101010101010F +:10F1F00001010101010101010101010101010101FF +:10F2000001010101010101010101010101010101EE +:10F2100001010101010101010101010101010101DE +:10F2200001010101010101010101010101010101CE +:10F2300001010101010101010101010101010101BE +:10F2400001010101010101010101010101010101AE +:10F25000010101010101010101010101010101019E +:10F26000010101010101010101010101010101018E +:10F27000010101010101010101010101010101017E +:10F28000010101010101010101010101010101016E +:10F29000010101010101010101010101010101015E +:10F2A000010101010101010101010101010101014E +:10F2B000010101010101010101010101010101013E +:10F2C000010101010101010101010101010101012E +:10F2D000010101010101010101010101010101011E +:10F2E000010101010101010101010101010101010E +:10F2F00001010101010101010101010101010101FE +:10F3000001010101010101010101010101010101ED +:10F3100001010101010101010101010101010101DD +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010101010101010101019D +:10F36000010101010101010101010101010101018D +:10F37000010101010101010101010101010101017D +:10F38000010101010101010101010101010101016D +:10F39000010101010101010101010101010101015D +:10F3A000010101010101010101010101010101014D +:10F3B000010101010101010101010101010101013D +:10F3C000010101010101010101010101010101012D +:10F3D000010101010101010101010101010101011D +:10F3E000010101010101010101010101010101010D +:10F3F00001010101010101010101010101010101FD +:10F4000001010101010101010101010101010101EC +:10F4100001010101010101010101010101010101DC +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F46000010101010101010101010101010101018C +:10F47000010101010101010101010101010101017C +:10F48000010101010101010101010101010101016C +:10F49000010101010101010101010101010101015C +:10F4A000010101010101010101010101010101014C +:10F4B000010101010101010101010101010101013C +:10F4C000010101010101010101010101010101012C +:10F4D000010101010101010101010101010101011C +:10F4E000010101010101010101010101010101010C +:10F4F00001010101010101010101010101010101FC +:10F5000001010101010101010101010101010101EB +:10F5100001010101010101010101010101010101DB +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101010101010101010101AB +:10F55000010101010101010101010101010101019B +:10F56000010101010101010101010101010101018B +:10F57000010101010101010101010101010101017B +:10F58000010101010101010101010101010101016B +:10F59000010101010101010101010101010101015B +:10F5A000010101010101010101010101010101014B +:10F5B000010101010101010101010101010101013B +:10F5C000010101010101010101010101010101012B +:10F5D000010101010101010101010101010101011B +:10F5E000010101010101010101010101010101010B +:10F5F00001010101010101010101010101010101FB +:10F6000001010101010101010101010101010101EA +:10F6100001010101010101010101010101010101DA +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010101010101010101017A +:10F68000010101010101010101010101010101016A +:10F69000010101010101010101010101010101015A +:10F6A000010101010101010101010101010101014A +:10F6B000010101010101010101010101010101013A +:10F6C000010101010101010101010101010101012A +:10F6D000010101010101010101010101010101011A +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010101010101010101010139 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101010101010101010141 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD0000101010101010101010101010101010111 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:020000023000CC +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101000000000000000000F2 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000020202020202020202E3 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A000020202020202020202020202020202021A +:1016B000020202020202020202020202020202020A +:1016C00002020202020202020202020202020202FA +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202020202020202020202DA +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A0000202020202020202020202020202020219 +:1017B0000202020202020202020202020202020209 +:1017C00002020202020202020202020202020202F9 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202020202020202020202D9 +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A0000202020202020202020202020202020218 +:1018B0000202020202020202020202020202020208 +:1018C00002020202020202020202020202020202F8 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202020202020202020202D8 +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020202A7 +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020202020202020202020217 +:1019B0000202020202020202020202020202020207 +:1019C00002020202020202020202020202020202F7 +:1019D00002020202020202020202020202020202E7 +:1019E00002020202020202020202020202020202D7 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000202020202020202020202020202020216 +:101AB0000202020202020202020202020202020206 +:101AC00002020202020202020202020202020202F6 +:101AD00002020202020202020202020202020202E6 +:101AE00002020202020202020202020202020202D6 +:101AF00002020202020202020202020202020202C6 +:101B000002020202020202020202020202020202B5 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA0000202020202020202020202020202020215 +:101BB0000202020202020202020202020202020205 +:101BC00002020202020202020202020202020202F5 +:101BD00002020202020202020202020202020202E5 +:101BE00002020202020202020202020202020202D5 +:101BF00002020202020202020202020202020202C5 +:101C000002020202020202020202020202020202B4 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA0000202020202020202020202020202020214 +:101CB0000202020202020202020202020202020204 +:101CC00002020202020202020202020202020202F4 +:101CD00002020202020202020202020202020202E4 +:101CE00002020202020202020202020202020202D4 +:101CF00002020202020202020202020202020202C4 +:101D000002020202020202020202020202020202B3 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020202020203 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020202D3 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202020202 +:101EC00002020202020202020202020202020202F2 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020202D2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020202D0 +:1020F00002020202020202020202020202020202C0 +:1021000002020202020202020202020202020202AF +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020202020202020202020F +:1021B00002020202020202020202020202020202FF +:1021C00002020202020202020202020202020202EF +:1021D00002020202020202020202020202020202DF +:1021E00002020202020202020202020202020202CF +:1021F00002020202020202020202020202020202BF +:1022000002020202020202020202020202020202AE +:10221000020202020202020202020202020202029E +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A000020202020202020202020202020202020E +:1022B00002020202020202020202020202020202FE +:1022C00002020202020202020202020202020202EE +:1022D00002020202020202020202020202020202DE +:1022E00002020202020202020202020202020202CE +:1022F00002020202020202020202020202020202BE +:1023000002020202020202020202020202020202AD +:10231000020202020202020202020202020202029D +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A000020202020202020202020202020202020D +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020202020202ED +:1023D00002020202020202020202020202020202DD +:1023E00002020202020202020202020202020202CD +:1023F00002020202020202020202020202020202BD +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202020202020202020202DC +:1024E00002020202020202020202020202020202CC +:1024F00002020202020202020202020202020202BC +:1025000002020202020202020202020202020202AB +:10251000020202020202020202020202020202029B +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C00002020202020202020202020202020202EB +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020202CB +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202020202020202020202DA +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020202D3 +:102DE00002020202020202020202020202020202C3 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020202D2 +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202000000000000000000BE +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000000000000000000000EB +:1035E00000000000000000000000000000000000DB +:1035F00000000000000000000000000000000000CB +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F0000000000000000097000000000000000130 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010101010101010101010167 +:103950000101010101010101010101010101010157 +:103960000101010101010101010101010101010147 +:103970000101010101010101010101010101010137 +:103980000101010101010101010101010101010127 +:103990000101010101010101010101010101010117 +:1039A0000101010101010101010101010101010107 +:1039B00001010101010101010101010101010101F7 +:1039C00001010101010101010101010101010101E7 +:1039D00001010101010101010101010101010101D7 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000101010101010101010101010101010176 +:103A40000101010101010101010101010101010166 +:103A50000101010101010101010101010101010156 +:103A60000101010101010101010101010101010146 +:103A70000101010101010101010101010101010136 +:103A80000101010101010101010101010101010126 +:103A90000101010101010101010101010101010116 +:103AA0000101010101010101010101010101010106 +:103AB00001010101010101010101010101010101F6 +:103AC00001010101010101010101010101010101E6 +:103AD00001010101010101010101010101010101D6 +:103AE00001010101010101010101010101010101C6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000101010101010101010101010101010135 +:103B80000101010101010101010101010101010125 +:103B90000101010101010101010101010101010115 +:103BA0000101010101010101010101010101010105 +:103BB00001010101010101010101010101010101F5 +:103BC00001010101010101010101010101010101E5 +:103BD00001010101010101010101010101010101D5 +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C60000101010101010101010101010101010144 +:103C70000101010101010101010101010101010134 +:103C80000101010101010101010101010101010124 +:103C90000101010101010101010101010101010114 +:103CA0000101010101010101010101010101010104 +:103CB00001010101010101010101010101010101F4 +:103CC00001010101010101010101010101010101E4 +:103CD00001010101010101010101010101010101D4 +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010101B4 +:103D000001010101010101010101010101010101A3 +:103D10000101010101010101010101010101010193 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000101010101010101010101010101010103 +:103DB00001010101010101010101010101010101F3 +:103DC00001010101010101010101010101010101E3 +:103DD00001010101010101010101010101010101D3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101010101010101010101B3 +:103E000001010101010101010101010101010101A2 +:103E10000101010101010101010101010101010192 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010172 +:103E40000101010101010101010101010101010162 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000101010101010101010101010101010112 +:103EA0000101010101010101010101010101010102 +:103EB00001010101010101010101010101010101F2 +:103EC00001010101010101010101010101010101E2 +:103ED00001010101010101010101010101010101D2 +:103EE00001010101010101010101010101010101C2 +:103EF00001010101010101010101010101010101B2 +:103F000001010101010101010101010101010101A1 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010171 +:103F40000101010101010101010101010101010161 +:103F50000101010101010101010101010101010151 +:103F60000101010101010101010101010101010141 +:103F70000101010101010101010101010101010131 +:103F80000101010101010101010101010101010121 +:103F90000101010101010101010101010101010111 +:103FA0000101010101010101010101010101010101 +:103FB00001010101010101010101010101010101F1 +:103FC00001010101010101010101010101010101E1 +:103FD00001010101010101010101010101010101D1 +:103FE00001010101010101010101010101010101C1 +:103FF00001010101010101010101010101010101B1 +:1040000001010101010101010101010101010101A0 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:104030000101010101010101010101010101010170 +:104040000101010101010101010101010101010160 +:104050000101010101010101010101010101010150 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:104080000101010101010101010101010101010120 +:104090000101010101010101010101010101010110 +:1040A0000101010101010101010101010101010100 +:1040B00001010101010101010101010101010101F0 +:1040C00001010101010101010101010101010101E0 +:1040D00001010101010101010101010101010101D0 +:1040E00001010101010101010101010101010101C0 +:1040F00001010101010101010101010101010101B0 +:10410000010101010101010101010101010101019F +:10411000010101010101010101010101010101018F +:10412000010101010101010101010101010101017F +:10413000010101010101010101010101010101016F +:10414000010101010101010101010101010101015F +:10415000010101010101010101010101010101014F +:10416000010101010101010101010101010101013F +:10417000010101010101010101010101010101012F +:10418000010101010101010101010101010101011F +:10419000010101010101010101010101010101010F +:1041A00001010101010101010101010101010101FF +:1041B00001010101010101010101010101010101EF +:1041C00001010101010101010101010101010101DF +:1041D00001010101010101010101010101010101CF +:1041E00001010101010101010101010101010101BF +:1041F00001010101010101010101010101010101AF +:10420000010101010101010101010101010101019E +:10421000010101010101010101010101010101018E +:10422000010101010101010101010101010101017E +:10423000010101010101010101010101010101016E +:10424000010101010101010101010101010101015E +:10425000010101010101010101010101010101014E +:10426000010101010101010101010101010101013E +:10427000010101010101010101010101010101012E +:10428000010101010101010101010101010101011E +:10429000010101010101010101010101010101010E +:1042A00001010101010101010101010101010101FE +:1042B00001010101010101010101010101010101EE +:1042C00001010101010101010101010101010101DE +:1042D00001010101010101010101010101010101CE +:1042E00001010101010101010101010101010101BE +:1042F00001010101010101010101010101010101AE +:10430000010101010101010101010101010101019D +:10431000010101010101010101010101010101018D +:10432000010101010101010101010101010101017D +:10433000010101010101010101010101010101016D +:10434000010101010101010101010101010101015D +:10435000010101010101010101010101010101014D +:10436000010101010101010101010101010101013D +:10437000010101010101010101010101010101012D +:10438000010101010101010101010101010101011D +:10439000010101010101010101010101010101010D +:1043A00001010101010101010101010101010101FD +:1043B00001010101010101010101010101010101ED +:1043C00001010101010101010101010101010101DD +:1043D00001010101010101010101010101010101CD +:1043E00001010101010101010101010101010101BD +:1043F00001010101010101010101010101010101AD +:10440000010101010101010101010101010101019C +:10441000010101010101010101010101010101018C +:10442000010101010101010101010101010101017C +:10443000010101010101010101010101010101016C +:10444000010101010101010101010101010101015C +:10445000010101010101010101010101010101014C +:10446000010101010101010101010101010101013C +:10447000010101010101010101010101010101012C +:10448000010101010101010101010101010101011C +:10449000010101010101010101010101010101010C +:1044A00001010101010101010101010101010101FC +:1044B00001010101010101010101010101010101EC +:1044C00001010101010101010101010101010101DC +:1044D00001010101010101010101010101010101CC +:1044E00001010101010101010101010101010101BC +:1044F00001010101010101010101010101010101AC +:10450000010101010101010101010101010101019B +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101011B +:10459000010101010101010101010101010101010B +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101010101010101010101EB +:1045C00001010101010101010101010101010101DB +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:10468000010101010101010101010101010101011A +:10469000010101010101010101010101010101010A +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010101EA +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101016D +:10533000010101010101010101010101010101015D +:10534000010101010101010101010101010101014D +:10535000010101010101010101010101010101013D +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101010D +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010101010101BD +:1053E00001010101010101010101010101010101AD +:1053F000010101010101010101010101010101019D +:10540000010101010101010101010101010101018C +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101016C +:10543000010101010101010101010101010101015C +:10544000010101010101010101010101010101014C +:10545000010101010101010101010101010101013C +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101010101010101010101BC +:1054E00001010101010101010101010101010101AC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:10553000010101010101010101010101010101015B +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000101010101010101010101010101010169 +:105730000101010101010101010101010101010159 +:105740000101010101010101010101010101010149 +:105750000101010101010101010101010101010139 +:105760000101010101010101010101010101010129 +:105770000101010101010101010101010101010119 +:105780000101010101010101010101010101010109 +:1057900001010101010101010101010101010101F9 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101010101010101010101B9 +:1057E00001010101010101010101010101010101A9 +:1057F0000101010101010101010101010101010199 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010187 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010098 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000002A1 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020202B2 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202020202020202020292 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202020286 +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020202020285 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020202B4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202020202020202020284 +:107CE0000202020202020202020202020202020274 +:107CF0000202020202020202020202020202020264 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020202020202020283 +:107DE0000202020202020202020202020202020273 +:107DF0000202020202020202020202020202020263 +:107E00000202020202020202020202020202020252 +:107E10000202020202020202020202020202020242 +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020202C2 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020202020202020202020282 +:107EE0000202020202020202020202020202020272 +:107EF0000202020202020202020202020202020064 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000017A +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010101010101010101010107 +:1089600001010101010101010101010101010101F7 +:1089700001010101010101010101010101010101E7 +:1089800001010101010101010101010101010101D7 +:1089900001010101010101010101010101010101C7 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010114 +:108C50000101010101010101010101010101010104 +:108C600001010101010101010101010101010101F4 +:108C700001010101010101010101010101010101E4 +:108C800001010101010101010101010101010101D4 +:108C900001010101010101010101010101010101C4 +:108CA00001010101010101010101010101010101B4 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010101DD +:10A3700001010101010101010101010101010101CD +:10A3800001010101010101010101010101010101BD +:10A3900001010101010101010101010101010101AD +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010101DC +:10A4700001010101010101010101010101010101CC +:10A4800001010101010101010101010101010101BC +:10A4900001010101010101010101010101010101AC +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800001010101010101010101010101010101BB +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010101010101010101010101010101BA +:10A6900001010101010101010101010101010101AA +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101004B +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000058 +:10A900000000000000000000000000000000000047 +:10A910000000000000000000000000000000000037 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000000000077 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000046 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000254 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202020202020202020202020202EA +:10B6400002020202020202020202020202020202DA +:10B6500002020202020202020202020202020202CA +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020202020202020202020202028A +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C000020202020202020202020202020202025A +:10B6D000020202020202020202020202020202024A +:10B6E000020202020202020202020202020202023A +:10B6F000020202020202020202020202020202022A +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020202020202020202020202C5 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020255 +:10BBD0000202020202020202020202020202020245 +:10BBE0000202020202020202020202020202020235 +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020251 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202023D +:10C3E000020202020202020202020202020202022D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202023C +:10C4E000020202020202020202020202020202022C +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000020202020202020202020202020202022B +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202023A +:10C6E000020202020202020202020202020202022A +:10C6F000020202020202020202020202020202021A +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020202020202020202020202020249 +:10C7D0000202020202020202020202020202020239 +:10C7E0000202020202020202020202020202020229 +:10C7F0000202020202020202020202020202020219 +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020202020202020202020202020248 +:10C8D0000202020202020202020202020202020238 +:10C8E0000202020202020202020202020202020228 +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020257 +:10C9C0000202020202020202020202020202020247 +:10C9D0000202020202020202020202020202020237 +:10C9E0000202020202020202020202020202020227 +:10C9F0000202020202020202020202020202020217 +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020017 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000054 +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD10000000000000000000000000000000000013 +:10CD20000000000000000000000000000000000003 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF00000000000000000000000000000000075BC +:10D000000000000000000001010101010101010117 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010101010101010101010101010101C0 +:10D0600001010101010101010101010101010101B0 +:10D0700001010101010101010101010101010101A0 +:10D080000101010101010101010101010101010190 +:10D090000101010101010101010101010101010180 +:10D0A0000101010101010101010101010101010170 +:10D0B0000101010101010101010101010101010160 +:10D0C0000101010101010101010101010101010150 +:10D0D0000101010101010101010101010101010140 +:10D0E0000101010101010101010101010101010130 +:10D0F0000101010101010101010101010101010120 +:10D10000010101010101010101010101010101010F +:10D1100001010101010101010101010101010101FF +:10D1200001010101010101010101010101010101EF +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010101010101AE +:10D27000010101010101010101010101010101019E +:10D28000010101010101010101010101010101018E +:10D29000010101010101010101010101010101017E +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010101FC +:10D4200001010101010101010101010101010101EC +:10D4300001010101010101010101010101010101DC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101017C +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010101CA +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010101AA +:10D67000010101010101010101010101010101019A +:10D68000010101010101010101010101010101018A +:10D69000010101010101010101010101010101017A +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000010101010101010101010101010101014A +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010101A9 +:10D770000101010101010101010101010101010199 +:10D780000101010101010101010101010101010189 +:10D790000101010101010101010101010101010179 +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000101010101010101010101010101010149 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010101010101010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010147 +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010101010101010101010146 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF0000101010101010101010101010101010115 +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010184 +:10DC90000101010101010101010101010101010174 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010101010101010101010114 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010101010101010101010173 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE90000101010101010101010101010101010172 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101010101010101010101DF +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101010101010101010101AF +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101010101010101DC +:10E4300001010101010101010101010101010101CC +:10E4400001010101010101010101010101010101BC +:10E4500001010101010101010101010101010101AC +:10E46000010101010101010101010101010101019C +:10E47000010101010101010101010101010101018C +:10E48000010101010101010101010101010101017C +:10E49000010101010101010101010101010101016C +:10E4A000010101010101010101010101010101015C +:10E4B000010101010101010101010101010101014C +:10E4C000010101010101010101010101010101013C +:10E4D000010101010101010101010101010101012C +:10E4E000010101010101010101010101010101011C +:10E4F000010101010101010101010101010101010C +:10E5000001010101010101010101010101010101FB +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010101DB +:10E5300001010101010101010101010101010101CB +:10E5400001010101010101010101010101010101BB +:10E5500001010101010101010101010101010101AB +:10E56000010101010101010101010101010101019B +:10E57000010101010101010101010101010101018B +:10E58000010101010101010101010101010101017B +:10E59000010101010101010101010101010101016B +:10E5A000010101010101010101010101010101015B +:10E5B000010101010101010101010101010101014B +:10E5C000010101010101010101010101010101013B +:10E5D000010101010101010101010101010101012B +:10E5E000010101010101010101010101010101011B +:10E5F000010101010101010101010101010101010B +:10E6000001010101010101010101010101010101FA +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101010101010101010101BA +:10E6500001010101010101010101010101010101AA +:10E66000010101010101010101010101010101019A +:10E67000010101010101010101010101010101018A +:10E68000010101010101010101010101010101017A +:10E69000010101010101010101010101010101016A +:10E6A000010101010101010101010101010101015A +:10E6B000010101010101010101010101010101014A +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E000010101010101010101010101010101011A +:10E6F000010101010101010101010101010101010A +:10E7000001010101010101010101010101010101F9 +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010101010101010101D9 +:10E7300001010101010101010101010101010101C9 +:10E7400001010101010101010101010101010101B9 +:10E7500001010101010101010101010101010101A9 +:10E760000101010101010101010101010101010199 +:10E770000101010101010101010101010101010189 +:10E780000101010101010101010101010101010179 +:10E790000101010101010101010101010101010169 +:10E7A0000101010101010101010101010101010159 +:10E7B0000101010101010101010101010101010149 +:10E7C0000101010101010101010101010101010139 +:10E7D0000101010101010101010101010101010129 +:10E7E0000101010101010101010101010101010119 +:10E7F0000101010101010101010101010101010109 +:10E8000001010101010101010101010101010101F8 +:10E8100001010101010101010101010101010101E8 +:10E8200001010101010101010101010101010101D8 +:10E8300001010101010101010101010101010101C8 +:10E8400001010101010101010101010101010101B8 +:10E8500001010101010101010101010101010101A8 +:10E860000101010101010101010101010101010198 +:10E870000101010101010101010101010101010188 +:10E880000101010101010101010101010101010178 +:10E890000101010101010101010101010101010168 +:10E8A0000101010101010101010101010101010158 +:10E8B0000101010101010101010101010101010148 +:10E8C0000101010101010101010101010101010138 +:10E8D0000101010101010101010101010101010128 +:10E8E0000101010101010101010101010101010118 +:10E8F0000101010101010101010101010101010108 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010101010101010101D7 +:10E9300001010101010101010101010101010101C7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010101010101010101010177 +:10E990000101010101010101010101010101010167 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101000000000000000000FF +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000000000000000000000036 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000000000000000000000035 +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000000000000000000000034 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE000000000000000000020202020202020202F0 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202020202020202020202F2 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020202020202020202020202A1 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020202020202020221 +:10EFD0000202020202020202020202020202020211 +:10EFE0000202020202020202020202020202020201 +:10EFF00002020202020202020202020202020202F1 +:10F0000002020202020202020202020202020202E0 +:10F0100002020202020202020202020202020202D0 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020202020202020202020202B0 +:10F0400002020202020202020202020202020202A0 +:10F050000202020202020202020202020202020290 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020202020202020202020230 +:10F0C0000202020202020202020202020202020220 +:10F0D0000202020202020202020202020202020210 +:10F0E0000202020202020202020202020202020200 +:10F0F00002020202020202020202020202020202F0 +:10F1000002020202020202020202020202020202DF +:10F1100002020202020202020202020202020202CF +:10F1200002020202020202020202020202020202BF +:10F1300002020202020202020202020202020202AF +:10F14000020202020202020202020202020202029F +:10F15000020202020202020202020202020202028F +:10F16000020202020202020202020202020202027F +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A000020202020202020202020202020202023F +:10F1B000020202020202020202020202020202022F +:10F1C000020202020202020202020202020202021F +:10F1D000020202020202020202020202020202020F +:10F1E00002020202020202020202020202020202FF +:10F1F00002020202020202020202020202020202EF +:10F2000002020202020202020202020202020202DE +:10F2100002020202020202020202020202020202CE +:10F2200002020202020202020202020202020202BE +:10F2300002020202020202020202020202020202AE +:10F24000020202020202020202020202020202029E +:10F25000020202020202020202020202020202028E +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202020202020202023E +:10F2B000020202020202020202020202020202022E +:10F2C000020202020202020202020202020202021E +:10F2D000020202020202020202020202020202020E +:10F2E00002020202020202020202020202020202FE +:10F2F00002020202020202020202020202020202EE +:10F3000002020202020202020202020202020202DD +:10F3100002020202020202020202020202020202CD +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020202020202AD +:10F34000020202020202020202020202020202029D +:10F35000020202020202020202020202020202028D +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B000020202020202020202020202020202022D +:10F3C000020202020202020202020202020202021D +:10F3D000020202020202020202020202020202020D +:10F3E00002020202020202020202020202020202FD +:10F3F00002020202020202020202020202020202ED +:10F4000002020202020202020202020202020202DC +:10F4100002020202020202020202020202020202CC +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020202029C +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202020202027C +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C000020202020202020202020202020202021C +:10F4D000020202020202020202020202020202020C +:10F4E00002020202020202020202020202020202FC +:10F4F00002020202020202020202020202020202EC +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020202020202020202CB +:10F5200002020202020202020202020202020202BB +:10F5300002020202020202020202020202020202AB +:10F54000020202020202020202020202020202029B +:10F55000020202020202020202020202020202028B +:10F56000020202020202020202020202020202027B +:10F57000020202020202020202020202020202026B +:10F58000020202020202020202020202020202025B +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B000020202020202020202020202020202022B +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020202020202020202020B +:10F5E00002020202020202020202020202020202FB +:10F5F00002020202020202020202020202020202EB +:10F6000002020202020202020202020202020202DA +:10F6100002020202020202020202020202020202CA +:10F6200002020202020202020202020202020202BA +:10F6300002020202020202020202020202020202AA +:10F64000020202020202020202020202020202029A +:10F65000020202020202020202020202020202028A +:10F66000020202020202020202020202020202027A +:10F67000020202020202020202020202020202026A +:10F68000020202020202020202020202020202025A +:10F69000020202020202020202020202020202024A +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020202020202020202020A +:10F6E00002020202020202020202020202020202FA +:10F6F00002020202020202020202020202020202EA +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020202020202020202020202C9 +:10F7200002020202020202020202020202020202B9 +:10F7300002020202020202020202020202020202A9 +:10F740000202020202020202020202020202020299 +:10F750000202020202020202020202020202020289 +:10F760000202020202020202020202020202020279 +:10F770000202020202020202020202020202020269 +:10F780000202020202020202020202020202020259 +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020202020202020202020202B8 +:10F8300002020202020202020202020202020202A8 +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202020202020202020202A7 +:10F940000202020202020202020202020202020297 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020277 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020202020202020202020243 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202020202020202020223 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202020202020242 +:10FEA0000202020202020202020202020202020232 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202020202020241 +:10FFA0000202020202020202020202020202020231 +:10FFB0000202020202020202020202020202020221 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:020000024000BC +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C000020202020202020202020202020202020F +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000020202020202020202020202020202023E +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C000020202020202020202020202020202020E +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202020202020202020D +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020202020202020202023C +:1004A000020202020202020202020202020202022C +:1004B000020202020202020202020202020202021C +:1004C000020202020202020202020202020202020C +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202024B +:10059000020202020202020202020202020202023B +:1005A000020202020202020202020202020202022B +:1005B000020202020202020202020202020202021B +:1005C000020202020202020202020202020202020B +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202024A +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020202020202020202021A +:1006C000020202020202020202020202020202020A +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:100770000202020202020202020202020202020259 +:100780000202020202020202020202020202020249 +:100790000202020202020202020202020202020239 +:1007A0000202020202020202020202020202020229 +:1007B0000202020202020202020202020202020219 +:1007C0000202020202020202020202020202020209 +:1007D00002020202020202020202020202020202F9 +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202000000000000000000DA +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000010101010101010101DB +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000001010101010101010101010101010101D2 +:100E100001010101010101010101010101010101C2 +:100E200001010101010101010101010101010101B2 +:100E300001010101010101010101010101010101A2 +:100E40000101010101010101010101010101010192 +:100E50000101010101010101010101010101010182 +:100E60000101010101010101010101010101010172 +:100E70000101010101010101010101010101010162 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101010101010101010101E2 +:100F000001010101010101010101010101010101D1 +:100F100001010101010101010101010101010101C1 +:100F200001010101010101010101010101010101B1 +:100F300001010101010101010101010101010101A1 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000101010101010101010101010101010171 +:100F70000101010101010101010101010101010161 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101010101010101010101E1 +:1010000001010101010101010101010101010101D0 +:1010100001010101010101010101010101010101C0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000101010101010101010101010101010170 +:101070000101010101010101010101010101010160 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010101010101BF +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:10116000010101010101010101010101010101016F +:10117000010101010101010101010101010101015F +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010101010101BE +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101016E +:10127000010101010101010101010101010101015E +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101010101010101010101BD +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101016D +:10137000010101010101010101010101010101015D +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101016C +:10147000010101010101010101010101010101015C +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101018B +:10155000010101010101010101010101010101017B +:10156000010101010101010101010101010101016B +:10157000010101010101010101010101010101015B +:10158000010101010101010101010101010101014B +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010101010101010101019A +:10164000010101010101010101010101010101018A +:10165000010101010101010101010101010101017A +:10166000010101010101010101010101010101016A +:10167000010101010101010101010101010101015A +:10168000010101010101010101010101010101014A +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010101010101010101010157 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101014B +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101000000000000000000C3 +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000000E8 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000020202020202020202B4 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020202D3 +:102DE00002020202020202020202020202020202C3 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020202D2 +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202029E +:10430000020202020202020202020202020202028D +:10431000020202020202020202020202020202027D +:10432000020202020202020202020202020202026D +:10433000020202020202020202020202020202025D +:10434000020202020202020202020202020202024D +:10435000020202020202020202020202020202023D +:10436000020202020202020202020202020202022D +:10437000020202020202020202020202020202021D +:10438000020202020202020202020202020202020D +:1043900002020202020202020202020202020202FD +:1043A00002020202020202020202020202020202ED +:1043B00002020202020202020202020202020202DD +:1043C00002020202020202020202020202020202CD +:1043D00002020202020202020202020202020202BD +:1043E00002020202020202020202020202020202AD +:1043F000020202020202020202020202020202029D +:10440000020202020202020000000000000000009E +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:10450000000000000000006D00000000000000013D +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101011B +:10459000010101010101010101010101010101010B +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101010101010101010101EB +:1045C00001010101010101010101010101010101DB +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:10468000010101010101010101010101010101011A +:10469000010101010101010101010101010101010A +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010101EA +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101016D +:10533000010101010101010101010101010101015D +:10534000010101010101010101010101010101014D +:10535000010101010101010101010101010101013D +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101010D +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010101010101BD +:1053E00001010101010101010101010101010101AD +:1053F000010101010101010101010101010101019D +:10540000010101010101010101010101010101018C +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101016C +:10543000010101010101010101010101010101015C +:10544000010101010101010101010101010101014C +:10545000010101010101010101010101010101013C +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101010101010101010101BC +:1054E00001010101010101010101010101010101AC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:10553000010101010101010101010101010101015B +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000101010101010101010101010101010169 +:105730000101010101010101010101010101010159 +:105740000101010101010101010101010101010149 +:105750000101010101010101010101010101010139 +:105760000101010101010101010101010101010129 +:105770000101010101010101010101010101010119 +:105780000101010101010101010101010101010109 +:1057900001010101010101010101010101010101F9 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101010101010101010101B9 +:1057E00001010101010101010101010101010101A9 +:1057F0000101010101010101010101010101010199 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010187 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000101010101010101010101010101010186 +:105A10000101010101010101010101010101010176 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010101010101010101010116 +:105A80000101010101010101010101010101010106 +:105A900001010101010101010101010101010101F6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00001010101010101010101010101010101C6 +:105AD00001010101010101010101010101010101B6 +:105AE00001010101010101010101010101010101A6 +:105AF0000101010101010101010101010101010196 +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010175 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101010101010101010145 +:105B50000101010101010101010101010101010135 +:105B60000101010101010101010101010101010125 +:105B70000101010101010101010101010101010115 +:105B80000101010101010101010101010101010105 +:105B900001010101010101010101010101010101F5 +:105BA00001010101010101010101010101010101E5 +:105BB00001010101010101010101010101010101D5 +:105BC00001010101010101010101010101010101C5 +:105BD00001010101010101010101010101010101B5 +:105BE00001010101010101010101010101010101A5 +:105BF0000101010101010101010101010101010195 +:105C00000101010101010101010101010101010184 +:105C10000101010101010101010101010101010174 +:105C20000101010101010101010101010101010164 +:105C30000101010101010101010101010101010154 +:105C40000101010101010101010101010101010144 +:105C50000101010101010101010101010101010134 +:105C60000101010101010101010101010101010124 +:105C70000101010101010101010101010101010114 +:105C80000101010101010101010101010101010104 +:105C900001010101010101010101010101010101F4 +:105CA00001010101010101010101010101010101E4 +:105CB00001010101010101010101010101010101D4 +:105CC00001010101010101010101010101010101C4 +:105CD00001010101010101010101010101010101B4 +:105CE00001010101010101010101010101010101A4 +:105CF0000101010101010101010101010101010194 +:105D00000101010101010101010101010101010084 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000000000000000000028D +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020059 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000172 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010101010101010101010123 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010101010101010101E3 +:107D900001010101010101010101010101010101D3 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010101010101010101010107 +:1089600001010101010101010101010101010101F7 +:1089700001010101010101010101010101010101E7 +:1089800001010101010101010101010101010101D7 +:1089900001010101010101010101010101010101C7 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010114 +:108C50000101010101010101010101010101010104 +:108C600001010101010101010101010101010101F4 +:108C700001010101010101010101010101010101E4 +:108C800001010101010101010101010101010101D4 +:108C900001010101010101010101010101010101C4 +:108CA00001010101010101010101010101010101B4 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101004C +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D000000000000000000000000000000000008B +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:10960000000000000000000000000000000000005A +:10961000000000000000000000000000000000004A +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C000000000000000000000000000000000009A +:1096D000000000000000000000000000000000008A +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000049 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000099 +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000000000000000000000A8 +:1098C0000000000000000000000000000000000098 +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000000000000000078 +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000000000255 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B0000202020202020202020202020202020287 +:1099C0000202020202020202020202020202020277 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020202020226 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020202A6 +:109AA0000202020202020202020202020202020296 +:109AB0000202020202020202020202020202020286 +:109AC0000202020202020202020202020202020276 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020202A5 +:109BA0000202020202020202020202020202020295 +:109BB0000202020202020202020202020202020285 +:109BC0000202020202020202020202020202020275 +:109BD0000202020202020202020202020202020265 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020202A4 +:109CA0000202020202020202020202020202020294 +:109CB0000202020202020202020202020202020284 +:109CC0000202020202020202020202020202020274 +:109CD0000202020202020202020202020202020264 +:109CE0000202020202020202020202020202020254 +:109CF0000202020202020202020202020202020244 +:109D00000202020202020202020202020202020233 +:109D10000202020202020202020202020202020223 +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020202020202020202020202020202E3 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020202A3 +:109DA0000202020202020202020202020202020293 +:109DB0000202020202020202020202020202020283 +:109DC0000202020202020202020202020202020273 +:109DD0000202020202020202020202020202020263 +:109DE0000202020202020202020202020202020253 +:109DF0000202020202020202020202020202020243 +:109E00000202020202020202020202020202020232 +:109E10000202020202020202020202020202020222 +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202020202020202E2 +:109E600002020202020202020202020202020202D2 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020202A2 +:109EA0000202020202020202020202020202020292 +:109EB0000202020202020202020202020202020282 +:109EC0000202020202020202020202020202020272 +:109ED0000202020202020202020202020202020262 +:109EE0000202020202020202020202020202020252 +:109EF0000202020202020202020202020202020242 +:109F00000202020202020202020202020202020231 +:109F10000202020202020202020202020202020221 +:109F20000202020202020202020202020202020211 +:109F30000202020202020202020202020202020201 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202020202020202E1 +:109F600002020202020202020202020202020202D1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020202A1 +:109FA0000202020202020202020202020202020291 +:109FB0000202020202020202020202020202020281 +:109FC0000202020202020202020202020202020271 +:109FD0000202020202020202020202020202020261 +:109FE0000202020202020202020202020202020251 +:109FF0000202020202020202020202020202020241 +:10A000000202020202020202020202020202020230 +:10A010000202020202020202020202020202020220 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020202020202020202020202020202D0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020202A0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020280 +:10A0C0000202020202020202020202020202020270 +:10A0D0000202020202020202020202020202020260 +:10A0E0000202020202020202020202020202020250 +:10A0F0000202020202020202020202020202020240 +:10A10000020202020202020202020202020202022F +:10A11000020202020202020202020202020202021F +:10A12000020202020202020202020202020202020F +:10A1300002020202020202020202020202020202FF +:10A1400002020202020202020202020202020202EF +:10A1500002020202020202020202020202020202DF +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A19000020202020202020202020202020202029F +:10A1A000020202020202020202020202020202028F +:10A1B000020202020202020202020202020202027F +:10A1C000020202020202020202020202020202026F +:10A1D000020202020202020202020202020202025F +:10A1E000020202020202020202020202020202024F +:10A1F000020202020202020202020202020202023F +:10A20000020202020202020202020202020202022E +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202020E +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202027E +:10A2C000020202020202020202020202020202026E +:10A2D000020202020202020202020202020202025E +:10A2E000020202020202020202020202020202024E +:10A2F000020202020202020202020202020202023E +:10A30000020202020202020202020202020202022D +:10A31000020202020202020202020202020202021D +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202024D +:10A3F000020202020202020202020202020202023D +:10A40000020202020202020202020202020202022C +:10A41000020202020202020202020202020202021C +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202027C +:10A4C000020202020202020202020202020202026C +:10A4D000020202020202020202020202020202025C +:10A4E000020202020202020202020202020202024C +:10A4F000020202020202020202020202020202023C +:10A50000020202020202020202020202020202022B +:10A51000020202020202020202020202020202021B +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E000020202020202020202020202020202024B +:10A5F000020202020202020202020202020202023B +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E000020202020202020202020202020202024A +:10A6F000020202020202020202020202020202023A +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000202020202020202020202020202020239 +:10A800000202020202020202020202020202020228 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020202A8 +:10A890000202020202020202020202020202020298 +:10A8A0000202020202020202020202020202020288 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B100000202020202020202020202020202020021 +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B2000000000000000000000000000000000065D9 +:10B210000000000000000001010101010101010125 +:10B22000010101010101010101010101010101010E +:10B2300001010101010101010101010101010101FE +:10B2400001010101010101010101010101010101EE +:10B2500001010101010101010101010101010101DE +:10B2600001010101010101010101010101010101CE +:10B2700001010101010101010101010101010101BE +:10B2800001010101010101010101010101010101AE +:10B29000010101010101010101010101010101019E +:10B2A000010101010101010101010101010101018E +:10B2B000010101010101010101010101010101017E +:10B2C000010101010101010101010101010101016E +:10B2D000010101010101010101010101010101015E +:10B2E000010101010101010101010101010101014E +:10B2F000010101010101010101010101010101013E +:10B30000010101010101010101010101010101012D +:10B31000010101010101010101010101010101011D +:10B32000010101010101010101010101010101010D +:10B3300001010101010101010101010101010101FD +:10B3400001010101010101010101010101010101ED +:10B3500001010101010101010101010101010101DD +:10B3600001010101010101010101010101010101CD +:10B3700001010101010101010101010101010101BD +:10B3800001010101010101010101010101010101AD +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010101010101010101018D +:10B3B000010101010101010101010101010101017D +:10B3C000010101010101010101010101010101016D +:10B3D000010101010101010101010101010101015D +:10B3E000010101010101010101010101010101014D +:10B3F000010101010101010101010101010101013D +:10B40000010101010101010101010101010101012C +:10B41000010101010101010101010101010101011C +:10B42000010101010101010101010101010101010C +:10B4300001010101010101010101010101010101FC +:10B4400001010101010101010101010101010101EC +:10B4500001010101010101010101010101010101DC +:10B4600001010101010101010101010101010101CC +:10B4700001010101010101010101010101010101BC +:10B4800001010101010101010101010101010101AC +:10B49000010101010101010101010101010101019C +:10B4A000010101010101010101010101010101018C +:10B4B000010101010101010101010101010101017C +:10B4C000010101010101010101010101010101016C +:10B4D000010101010101010101010101010101015C +:10B4E000010101010101010101010101010101014C +:10B4F000010101010101010101010101010101013C +:10B50000010101010101010101010101010101012B +:10B51000010101010101010101010101010101011B +:10B52000010101010101010101010101010101010B +:10B5300001010101010101010101010101010101FB +:10B5400001010101010101010101010101010101EB +:10B5500001010101010101010101010101010101DB +:10B5600001010101010101010101010101010101CB +:10B5700001010101010101010101010101010101BB +:10B5800001010101010101010101010101010101AB +:10B59000010101010101010101010101010101019B +:10B5A000010101010101010101010101010101018B +:10B5B000010101010101010101010101010101017B +:10B5C000010101010101010101010101010101016B +:10B5D000010101010101010101010101010101015B +:10B5E000010101010101010101010101010101014B +:10B5F000010101010101010101010101010101013B +:10B60000010101010101010101010101010101012A +:10B61000010101010101010101010101010101011A +:10B62000010101010101010101010101010101010A +:10B6300001010101010101010101010101010101FA +:10B6400001010101010101010101010101010101EA +:10B6500001010101010101010101010101010101DA +:10B6600001010101010101010101010101010101CA +:10B6700001010101010101010101010101010101BA +:10B6800001010101010101010101010101010101AA +:10B69000010101010101010101010101010101019A +:10B6A000010101010101010101010101010101018A +:10B6B000010101010101010101010101010101017A +:10B6C000010101010101010101010101010101016A +:10B6D000010101010101010101010101010101015A +:10B6E000010101010101010101010101010101014A +:10B6F000010101010101010101010101010101013A +:10B700000101010101010101010101010101010129 +:10B710000101010101010101010101010101010119 +:10B720000101010101010101010101010101010109 +:10B7300001010101010101010101010101010101F9 +:10B7400001010101010101010101010101010101E9 +:10B7500001010101010101010101010101010101D9 +:10B7600001010101010101010101010101010101C9 +:10B7700001010101010101010101010101010101B9 +:10B7800001010101010101010101010101010101A9 +:10B790000101010101010101010101010101010199 +:10B7A0000101010101010101010101010101010189 +:10B7B0000101010101010101010101010101010179 +:10B7C0000101010101010101010101010101010169 +:10B7D0000101010101010101010101010101010159 +:10B7E0000101010101010101010101010101010149 +:10B7F0000101010101010101010101010101010139 +:10B800000101010101010101010101010101010128 +:10B810000101010101010101010101010101010118 +:10B820000101010101010101010101010101010108 +:10B8300001010101010101010101010101010101F8 +:10B8400001010101010101010101010101010101E8 +:10B8500001010101010101010101010101010101D8 +:10B8600001010101010101010101010101010101C8 +:10B8700001010101010101010101010101010101B8 +:10B8800001010101010101010101010101010101A8 +:10B890000101010101010101010101010101010198 +:10B8A0000101010101010101010101010101010188 +:10B8B0000101010101010101010101010101010178 +:10B8C0000101010101010101010101010101010168 +:10B8D0000101010101010101010101010101010158 +:10B8E0000101010101010101010101010101010148 +:10B8F0000101010101010101010101010101010138 +:10B900000101010101010101010101010101010127 +:10B910000101010101010101010101010101010117 +:10B920000101010101010101010101010101010107 +:10B9300001010101010101010101010101010101F7 +:10B9400001010101010101010101010101010101E7 +:10B9500001010101010101010101010101010101D7 +:10B9600001010101010101010101010101010101C7 +:10B9700001010101010101010101010101010101B7 +:10B9800001010101010101010101010101010101A7 +:10B990000101010101010101010101010101010197 +:10B9A0000101010101010101010101010101010187 +:10B9B0000101010101010101010101010101010177 +:10B9C0000101010101010101010101010101010167 +:10B9D0000101010101010101010101010101010157 +:10B9E0000101010101010101010101010101010147 +:10B9F0000101010101010101010101010101010137 +:10BA00000101010101010101010101010101010126 +:10BA10000101010101010101010101010101010116 +:10BA20000101010101010101010101010101010106 +:10BA300001010101010101010101010101010101F6 +:10BA400001010101010101010101010101010101E6 +:10BA500001010101010101010101010101010101D6 +:10BA600001010101010101010101010101010101C6 +:10BA700001010101010101010101010101010101B6 +:10BA800001010101010101010101010101010101A6 +:10BA90000101010101010101010101010101010196 +:10BAA0000101010101010101010101010101010186 +:10BAB0000101010101010101010101010101010176 +:10BAC0000101010101010101010101010101010166 +:10BAD0000101010101010101010101010101010156 +:10BAE0000101010101010101010101010101010146 +:10BAF0000101010101010101010101010101010136 +:10BB00000101010101010101010101010101010125 +:10BB10000101010101010101010101010101010115 +:10BB20000101010101010101010101010101010105 +:10BB300001010101010101010101010101010101F5 +:10BB400001010101010101010101010101010101E5 +:10BB500001010101010101010101010101010101D5 +:10BB600001010101010101010101010101010101C5 +:10BB700001010101010101010101010101010101B5 +:10BB800001010101010101010101010101010101A5 +:10BB90000101010101010101010101010101010195 +:10BBA0000101010101010101010101010101010185 +:10BBB0000101010101010101010101010101010175 +:10BBC0000101010101010101010101010101010165 +:10BBD0000101010101010101010101010101010155 +:10BBE0000101010101010101010101010101010145 +:10BBF0000101010101010101010101010101010135 +:10BC00000101010101010101010101010101010124 +:10BC10000101010101010101010101010101010114 +:10BC20000101010101010101010101010101010104 +:10BC300001010101010101010101010101010101F4 +:10BC400001010101010101010101010101010101E4 +:10BC500001010101010101010101010101010101D4 +:10BC600001010101010101010101010101010101C4 +:10BC700001010101010101010101010101010101B4 +:10BC800001010101010101010101010101010101A4 +:10BC90000101010101010101010101010101010194 +:10BCA0000101010101010101010101010101010184 +:10BCB0000101010101010101010101010101010174 +:10BCC0000101010101010101010101010101010164 +:10BCD0000101010101010101010101010101010154 +:10BCE0000101010101010101010101010101010144 +:10BCF0000101010101010101010101010101010134 +:10BD00000101010101010101010101010101010123 +:10BD10000101010101010101010101010101010113 +:10BD20000101010101010101010101010101010103 +:10BD300001010101010101010101010101010101F3 +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101010101010101010101B3 +:10BD800001010101010101010101010101010101A3 +:10BD90000101010101010101010101010101010193 +:10BDA0000101010101010101010101010101010183 +:10BDB0000101010101010101010101010101010173 +:10BDC0000101010101010101010101010101010163 +:10BDD0000101010101010101010101010101010153 +:10BDE0000101010101010101010101010101010143 +:10BDF0000101010101010101010101010101010133 +:10BE00000101010101010101010101010101010122 +:10BE10000101010101010101010101010101010112 +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101010101010101010101B2 +:10BE800001010101010101010101010101010101A2 +:10BE90000101010101010101010101010101010192 +:10BEA0000101010101010101010101010101010182 +:10BEB0000101010101010101010101010101010172 +:10BEC0000101010101010101010101010101010162 +:10BED0000101010101010101010101010101010152 +:10BEE0000101010101010101010101010101010142 +:10BEF0000101010101010101010101010101010132 +:10BF00000101010101010101010101010101010121 +:10BF10000101010101010101010101010101010111 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101010101010101010101B1 +:10BF800001010101010101010101010101010101A1 +:10BF90000101010101010101010101010101010191 +:10BFA0000101010101010101010101010101010181 +:10BFB0000101010101010101010101010101010171 +:10BFC0000101010101010101010101010101010161 +:10BFD0000101010101010101010101010101010151 +:10BFE0000101010101010101010101010101010141 +:10BFF0000101010101010101010101010101010131 +:10C000000101010101010101010101010101010120 +:10C010000101010101010101010101010101010110 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101010101010101010101B0 +:10C0800001010101010101010101010101010101A0 +:10C090000101010101010101010101010101010190 +:10C0A0000101010101010101010101010101010180 +:10C0B0000101010101010101010101010101010170 +:10C0C0000101010101010101010101010101010160 +:10C0D0000101010101010101010101010101010150 +:10C0E0000101010101010101010101010101010140 +:10C0F0000101010101010101010101010101010130 +:10C10000010101010101010101010101010101011F +:10C11000010101010101010101010101010101010F +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010101010101DF +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A000010101010101010101010101010101017F +:10C1B000010101010101010101010101010101016F +:10C1C000010101010101010101010101010101015F +:10C1D000010101010101010101010101010101014F +:10C1E000010101010101010101010101010101013F +:10C1F000010101010101010101010101010101012F +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101010101010101010101CE +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A000010101010101010101010101010101017E +:10C2B000010101010101010101010101010101016E +:10C2C000010101010101010101010101010101015E +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010101010101ED +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101010101010101010101CD +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010101010101010101017D +:10C3B000010101010101010101010101010101016D +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101010C +:10C4200001010101010101010101010101010101FC +:10C4300001010101010101010101010101010101EC +:10C4400001010101010101010101010101010101DC +:10C4500001010101010101010101010101010101CC +:10C4600001010101010101010101010101010101BC +:10C4700001010101010101010101010101010101AC +:10C48000010101010101010101010101010101019C +:10C49000010101010101010101010101010101018C +:10C4A000010101010101010101010101010101017C +:10C4B000010101010101010101010101010101016C +:10C4C000010101010101010101010101010101015C +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010101010101010101013C +:10C4F000010101010101010101010101010101012C +:10C50000010101010101010101010101010101011B +:10C51000010101010101010101010101010101010B +:10C5200001010101010101010101010101010101FB +:10C5300001010101010101010101010101010101EB +:10C5400001010101010101010101010101010101DB +:10C5500001010101010101010101010101010101CB +:10C5600001010101010101010101010101010101BB +:10C5700001010101010101010101010101010101AB +:10C58000010101010101010101010101010101019B +:10C59000010101010101010101010101010101018B +:10C5A000010101010101010101010101010101017B +:10C5B000010101010101010101010101010101016B +:10C5C000010101010101010101010101010101015B +:10C5D000010101010101010101010101010101014B +:10C5E000010101010101010101010101010101013B +:10C5F000010101010101010101010101010101012B +:10C60000010101010101010101010101010101011A +:10C61000010101010101010101010101010101010A +:10C6200001010101010101010101010101010101FA +:10C6300001010101010101010101010101010101EA +:10C6400001010101010101010101010101010101DA +:10C6500001010101010101010101010101010101CA +:10C6600001010101010101010101010101010101BA +:10C6700001010101010101010101010101010101AA +:10C68000010101010101010101010101010101019A +:10C69000010101010101010101010101010101018A +:10C6A000010101010101010101010101010101017A +:10C6B000010101010101010101010101010101016A +:10C6C000010101010101010101010101010101015A +:10C6D000010101010101010101010101010101014A +:10C6E000010101010101010101010101010101013A +:10C6F000010101010101010101010101010101012A +:10C700000101010101010101010101010101010119 +:10C710000101010101010101010101010101010109 +:10C7200001010101010101010101010101010101F9 +:10C7300001010101010101010101010101010101E9 +:10C7400001010101010101010101010101010101D9 +:10C7500001010101010101010101010101010101C9 +:10C7600001010101010101010101010101010101B9 +:10C7700001010101010101010101010101010101A9 +:10C780000101010101010101010101010101010199 +:10C790000101010101010101010101010101010189 +:10C7A0000101010101010101010101010101010179 +:10C7B0000101010101010101010101010101010169 +:10C7C0000101010101010101010101010101010159 +:10C7D0000101010101010101010101010101010149 +:10C7E0000101010101010101010101010101010139 +:10C7F0000101010101010101010101010101010129 +:10C800000101010101010101010101010101010118 +:10C810000101010101010100000000000000000011 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000002020202020202020202 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020233 +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202020202020202020202020213 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020202020252 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020232 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202020202020202020202020212 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020231 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202020202020202020202020211 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202020202020202020202020202020230 +:10D0E0000202020202020202020202020202020220 +:10D0F0000202020202020202020202020202020210 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D17000020202020202020202020202020202028F +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020202020202020202020202023F +:10D1D000020202020202020202020202020202022F +:10D1E000020202020202020202020202020202021F +:10D1F000020202020202020202020202020202020F +:10D2000002020202020202020202020202020202FE +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D000020202020202020202020202020202022E +:10D2E000020202020202020202020202020202021E +:10D2F000020202020202020202020202020202020E +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020202020202020202020202CD +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020202020202020202020202025D +:10D3B000020202020202020202020202020202024D +:10D3C000020202020202020202020202020202023D +:10D3D000020202020202020202020202020202022D +:10D3E000020202020202020202020202020202021D +:10D3F000020202020202020202020202020202020D +:10D4000002020202020202020202020202020202FC +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020202DC +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202020202020202025C +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020202020202020202023C +:10D4D000020202020202020202020202020202022C +:10D4E000020202020202020202020202020202021C +:10D4F000020202020202020202020202020202020C +:10D5000002020202020202020202020202020202FB +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020202020202020202020202CB +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A000020202020202020202020202020202025B +:10D5B000020202020202020202020202020202024B +:10D5C000020202020202020202020202020202023B +:10D5D000020202020202020202020202020202022B +:10D5E000020202020202020202020202020202021B +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B000020202020202020202020202020202024A +:10D6C000020202020202020202020202020202023A +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020202020202020202020239 +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C0000202020202020202020202020202020238 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202020202020237 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202020202020236 +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020202020202020202020216 +:10DAF0000202020202020202020202020202020206 +:10DB000002020202020202020202020202020202F5 +:10DB100002020202020202020202020202020202E5 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB0000202020202020202020202020202020245 +:10DBC0000202020202020202020202020202020235 +:10DBD0000202020202020202020202020202020225 +:10DBE0000202020202020202020202020202020215 +:10DBF0000202020202020202020202020202020205 +:10DC000002020202020202020202020202020202F4 +:10DC100002020202020202020202020202020202E4 +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB0000202020202020202020202020202020244 +:10DCC0000202020202020202020202020202020234 +:10DCD0000202020202020202020202020202020224 +:10DCE0000202020202020202020202020202020214 +:10DCF0000202020202020202020202020202020204 +:10DD000002020202020202020202020202020202F3 +:10DD100002020202020202020202020202020202E3 +:10DD200002020202020202020202020202020202D3 +:10DD300002020202020202020202020202020202C3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB0000202020202020202020202020202020243 +:10DDC0000202020202020202020202020202020233 +:10DDD0000202020202020202020202020202020223 +:10DDE0000202020202020202020202020202020213 +:10DDF0000202020202020202020202020202020203 +:10DE000002020202020202020202020202020202F2 +:10DE100002020202020202020202020202020202E2 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA0000202020202020202020202020202020252 +:10DEB0000202020202020202020202020202020242 +:10DEC0000202020202020202020202020202020232 +:10DED0000202020202020202020202020202020222 +:10DEE0000202020202020202020202020202020212 +:10DEF0000202020202020202020202020202020202 +:10DF000002020202020202020202020202020202F1 +:10DF100002020202020202020202020202020202E1 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202020202020231 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020202020202020202020211 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020202020202020202020250 +:10E0B0000202020202020202020202020202020240 +:10E0C0000202020202020202020202020202020230 +:10E0D0000202020202020202020202020202020220 +:10E0E0000202020202020202020202020202020210 +:10E0F0000202020202020202020202020202020200 +:10E1000002020202020202020202020202020202EF +:10E1100002020202020202020202020202020202DF +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A000020202020202020202020202020202024F +:10E1B000020202020202020202020202020202023F +:10E1C000020202020202020202020202020202022F +:10E1D000020202020202020202020202020202021F +:10E1E000020202020202020202020202020202020F +:10E1F00002020202020202020202020202020202FF +:10E2000002020202020202020202020202020202EE +:10E2100002020202020202000000000000000000F0 +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000010101010101010101F1 +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101010101010101010101BA +:10E6500001010101010101010101010101010101AA +:10E66000010101010101010101010101010101019A +:10E67000010101010101010101010101010101018A +:10E68000010101010101010101010101010101017A +:10E69000010101010101010101010101010101016A +:10E6A000010101010101010101010101010101015A +:10E6B000010101010101010101010101010101014A +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E000010101010101010101010101010101011A +:10E6F000010101010101010101010101010101010A +:10E7000001010101010101010101010101010101F9 +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010101010101010101D9 +:10E7300001010101010101010101010101010101C9 +:10E7400001010101010101010101010101010101B9 +:10E7500001010101010101010101010101010101A9 +:10E760000101010101010101010101010101010199 +:10E770000101010101010101010101010101010189 +:10E780000101010101010101010101010101010179 +:10E790000101010101010101010101010101010169 +:10E7A0000101010101010101010101010101010159 +:10E7B0000101010101010101010101010101010149 +:10E7C0000101010101010101010101010101010139 +:10E7D0000101010101010101010101010101010129 +:10E7E0000101010101010101010101010101010119 +:10E7F0000101010101010101010101010101010109 +:10E8000001010101010101010101010101010101F8 +:10E8100001010101010101010101010101010101E8 +:10E8200001010101010101010101010101010101D8 +:10E8300001010101010101010101010101010101C8 +:10E8400001010101010101010101010101010101B8 +:10E8500001010101010101010101010101010101A8 +:10E860000101010101010101010101010101010198 +:10E870000101010101010101010101010101010188 +:10E880000101010101010101010101010101010178 +:10E890000101010101010101010101010101010168 +:10E8A0000101010101010101010101010101010158 +:10E8B0000101010101010101010101010101010148 +:10E8C0000101010101010101010101010101010138 +:10E8D0000101010101010101010101010101010128 +:10E8E0000101010101010101010101010101010118 +:10E8F0000101010101010101010101010101010108 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010101010101010101D7 +:10E9300001010101010101010101010101010101C7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010101010101010101010177 +:10E990000101010101010101010101010101010167 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010101010101010101D6 +:10EA300001010101010101010101010101010101C6 +:10EA400001010101010101010101010101010101B6 +:10EA500001010101010101010101010101010101A6 +:10EA60000101010101010101010101010101010196 +:10EA70000101010101010101010101010101010186 +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010101010101010101010166 +:10EAA0000101010101010101010101010101010156 +:10EAB0000101010101010101010101010101010146 +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101010101010101010101F5 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101010101010101010101D5 +:10EB300001010101010101010101010101010101C5 +:10EB400001010101010101010101010101010101B5 +:10EB500001010101010101010101010101010101A5 +:10EB60000101010101010101010101010101010195 +:10EB70000101010101010101010101010101010185 +:10EB80000101010101010101010101010101010175 +:10EB90000101010101010101010101010101010165 +:10EBA0000101010101010101010101010101010155 +:10EBB0000101010101010101010101010101010145 +:10EBC0000101010101010101010101010101010135 +:10EBD0000101010101010101010101010101010125 +:10EBE0000101010101010101010101010101010115 +:10EBF0000101010101010101010101010101010105 +:10EC000001010101010101010101010101010101F4 +:10EC100001010101010101010101010101010101E4 +:10EC200001010101010101010101010101010101D4 +:10EC300001010101010101010101010101010101C4 +:10EC400001010101010101010101010101010101B4 +:10EC500001010101010101010101010101010101A4 +:10EC60000101010101010101010101010101010194 +:10EC70000101010101010101010101010101010184 +:10EC80000101010101010101010101010101010174 +:10EC90000101010101010101010101010101010164 +:10ECA0000101010101010101010101010101010154 +:10ECB0000101010101010101010101010101010144 +:10ECC0000101010101010101010101010101010134 +:10ECD0000101010101010101010101010101010124 +:10ECE0000101010101010101010101010101010114 +:10ECF0000101010101010101010101010101010104 +:10ED000001010101010101010101010101010101F3 +:10ED100001010101010101010101010101010101E3 +:10ED200001010101010101010101010101010101D3 +:10ED300001010101010101010101010101010101C3 +:10ED400001010101010101010101010101010101B3 +:10ED500001010101010101010101010101010101A3 +:10ED60000101010101010101010101010101010193 +:10ED70000101010101010101010101010101010183 +:10ED80000101010101010101010101010101010173 +:10ED90000101010101010101010101010101010163 +:10EDA0000101010101010101010101010101010153 +:10EDB0000101010101010101010101010101010143 +:10EDC0000101010101010101010101010101010133 +:10EDD0000101010101010101010101010101010123 +:10EDE0000101010101010101010101010101010113 +:10EDF0000101010101010101010101010101010103 +:10EE000001010101010101010101010101010101F2 +:10EE100001010101010101010101010101010101E2 +:10EE200001010101010101010101010101010101D2 +:10EE300001010101010101010101010101010101C2 +:10EE400001010101010101010101010101010101B2 +:10EE500001010101010101010101010101010101A2 +:10EE60000101010101010101010101010101010192 +:10EE70000101010101010101010101010101010182 +:10EE80000101010101010101010101010101010172 +:10EE90000101010101010101010101010101010162 +:10EEA0000101010101010101010101010101010152 +:10EEB0000101010101010101010101010101010142 +:10EEC0000101010101010101010101010101010132 +:10EED0000101010101010101010101010101010122 +:10EEE0000101010101010101010101010101010112 +:10EEF0000101010101010101010101010101010102 +:10EF000001010101010101010101010101010101F1 +:10EF100001010101010101010101010101010101E1 +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101010101010101010101C1 +:10EF400001010101010101010101010101010101B1 +:10EF500001010101010101010101010101010101A1 +:10EF60000101010101010101010101010101010191 +:10EF70000101010101010101010101010101010181 +:10EF80000101010101010101010101010101010171 +:10EF90000101010101010101010101010101010161 +:10EFA0000101010101010101010101010101010151 +:10EFB0000101010101010101010101010101010141 +:10EFC0000101010101010101010101010101010131 +:10EFD0000101010101010101010101010101010121 +:10EFE0000101010101010101010101010101010111 +:10EFF0000101010101010101010101010101010101 +:10F0000001010101010101010101010101010101F0 +:10F0100001010101010101010101010101010101E0 +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101010101010101010101C0 +:10F0400001010101010101010101010101010101B0 +:10F0500001010101010101010101010101010101A0 +:10F060000101010101010101010101010101010190 +:10F070000101010101010101010101010101010180 +:10F080000101010101010101010101010101010170 +:10F090000101010101010101010101010101010160 +:10F0A0000101010101010101010101010101010150 +:10F0B0000101010101010101010101010101010140 +:10F0C0000101010101010101010101010101010130 +:10F0D0000101010101010101010101010101010120 +:10F0E0000101010101010101010101010101010110 +:10F0F0000101010101010101010101010101010100 +:10F1000001010101010101010101010101010101EF +:10F1100001010101010101010101010101010101DF +:10F1200001010101010101010101010101010101CF +:10F1300001010101010101010101010101010101BF +:10F1400001010101010101010101010101010101AF +:10F15000010101010101010101010101010101019F +:10F16000010101010101010101010101010101018F +:10F17000010101010101010101010101010101017F +:10F18000010101010101010101010101010101016F +:10F19000010101010101010101010101010101015F +:10F1A000010101010101010101010101010101014F +:10F1B000010101010101010101010101010101013F +:10F1C000010101010101010101010101010101012F +:10F1D000010101010101010101010101010101011F +:10F1E000010101010101010101010101010101010F +:10F1F00001010101010101010101010101010101FF +:10F2000001010101010101010101010101010101EE +:10F2100001010101010101010101010101010101DE +:10F2200001010101010101010101010101010101CE +:10F2300001010101010101010101010101010101BE +:10F2400001010101010101010101010101010101AE +:10F25000010101010101010101010101010101019E +:10F26000010101010101010101010101010101018E +:10F27000010101010101010101010101010101017E +:10F28000010101010101010101010101010101016E +:10F29000010101010101010101010101010101015E +:10F2A000010101010101010101010101010101014E +:10F2B000010101010101010101010101010101013E +:10F2C000010101010101010101010101010101012E +:10F2D000010101010101010101010101010101011E +:10F2E000010101010101010101010101010101010E +:10F2F00001010101010101010101010101010101FE +:10F3000001010101010101010101010101010101ED +:10F3100001010101010101010101010101010101DD +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010101010101010101019D +:10F36000010101010101010101010101010101018D +:10F37000010101010101010101010101010101017D +:10F38000010101010101010101010101010101016D +:10F39000010101010101010101010101010101015D +:10F3A000010101010101010101010101010101014D +:10F3B000010101010101010101010101010101013D +:10F3C000010101010101010101010101010101012D +:10F3D000010101010101010101010101010101011D +:10F3E000010101010101010101010101010101010D +:10F3F00001010101010101010101010101010101FD +:10F4000001010101010101010101010101010101EC +:10F4100001010101010101010101010101010101DC +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F46000010101010101010101010101010101018C +:10F47000010101010101010101010101010101017C +:10F48000010101010101010101010101010101016C +:10F49000010101010101010101010101010101015C +:10F4A000010101010101010101010101010101014C +:10F4B000010101010101010101010101010101013C +:10F4C000010101010101010101010101010101012C +:10F4D000010101010101010101010101010101011C +:10F4E000010101010101010101010101010101010C +:10F4F00001010101010101010101010101010101FC +:10F5000001010101010101010101010101010101EB +:10F5100001010101010101010101010101010101DB +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101010101010101010101AB +:10F55000010101010101010101010101010101019B +:10F56000010101010101010101010101010101018B +:10F57000010101010101010101010101010101017B +:10F58000010101010101010101010101010101016B +:10F59000010101010101010101010101010101015B +:10F5A000010101010101010101010101010101014B +:10F5B000010101010101010101010101010101013B +:10F5C000010101010101010101010101010101012B +:10F5D000010101010101010101010101010101011B +:10F5E000010101010101010101010101010101010B +:10F5F00001010101010101010101010101010101FB +:10F6000001010101010101010101010101010101EA +:10F6100001010101010101010101010101010101DA +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010101010101010101017A +:10F68000010101010101010101010101010101016A +:10F69000010101010101010101010101010101015A +:10F6A000010101010101010101010101010101014A +:10F6B000010101010101010101010101010101013A +:10F6C000010101010101010101010101010101012A +:10F6D000010101010101010101010101010101011A +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010101010101010101010139 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101000000000000000000DD +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000000000000000000000000000000000034 +:10FCD0000000000000000000000000000000000024 +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000004 +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:020000025000AC +:1000000000000000000000000000000000000000F0 +:1000100000000000000000020202020202020202CE +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C000020202020202020202020202020202020F +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000020202020202020202020202020202023E +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C000020202020202020202020202020202020E +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202020202020202020D +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020202020202020202023C +:1004A000020202020202020202020202020202022C +:1004B000020202020202020202020202020202021C +:1004C000020202020202020202020202020202020C +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202024B +:10059000020202020202020202020202020202023B +:1005A000020202020202020202020202020202022B +:1005B000020202020202020202020202020202021B +:1005C000020202020202020202020202020202020B +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202024A +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020202020202020202021A +:1006C000020202020202020202020202020202020A +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:100770000202020202020202020202020202020259 +:100780000202020202020202020202020202020249 +:100790000202020202020202020202020202020239 +:1007A0000202020202020202020202020202020229 +:1007B0000202020202020202020202020202020219 +:1007C0000202020202020202020202020202020209 +:1007D00002020202020202020202020202020202F9 +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020248 +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B0000202020202020202020202020202020218 +:1008C0000202020202020202020202020202020208 +:1008D00002020202020202020202020202020202F8 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020247 +:100990000202020202020202020202020202020237 +:1009A0000202020202020202020202020202020227 +:1009B0000202020202020202020202020202020217 +:1009C0000202020202020202020202020202020207 +:1009D00002020202020202020202020202020202F7 +:1009E00002020202020202020202020202020202E7 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020202020202020202020226 +:100AB0000202020202020202020202020202020216 +:100AC0000202020202020202020202020202020206 +:100AD00002020202020202020202020202020202F6 +:100AE00002020202020202020202020202020202E6 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202020202020202020205 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202000000000000000000BC +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:10171000000000000000005D00000000000000016B +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010101010101010101010157 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101014B +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:10267000010101010101010101010101010101014A +:10268000010101010101010101010101010101013A +:10269000010101010101010101010101010101012A +:1026A000010101010101010101010101010101011A +:1026B000010101010101010101010101010101010A +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101010101010101010159 +:102770000101010101010101010101010101010149 +:102780000101010101010101010101010101010139 +:102790000101010101010101010101010101010129 +:1027A0000101010101010101010101010101010119 +:1027B0000101010101010101010101010101010109 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010147 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010101010127 +:1029A0000101010101010101010101010101010117 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010146 +:102A80000101010101010101010101010101010136 +:102A90000101010101010101010101010101010126 +:102AA0000101010101010101010101010101010116 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010100A6 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000004 +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000002AF +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202029E +:10430000020202020202020202020202020202028D +:10431000020202020202020202020202020202007F +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000198 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101016D +:10533000010101010101010101010101010101015D +:10534000010101010101010101010101010101014D +:10535000010101010101010101010101010101013D +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101010D +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010101010101BD +:1053E00001010101010101010101010101010101AD +:1053F000010101010101010101010101010101019D +:10540000010101010101010101010101010101018C +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101016C +:10543000010101010101010101010101010101015C +:10544000010101010101010101010101010101014C +:10545000010101010101010101010101010101013C +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101010101010101010101BC +:1054E00001010101010101010101010101010101AC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:10553000010101010101010101010101010101015B +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000101010101010101010101010101010169 +:105730000101010101010101010101010101010159 +:105740000101010101010101010101010101010149 +:105750000101010101010101010101010101010139 +:105760000101010101010101010101010101010129 +:105770000101010101010101010101010101010119 +:105780000101010101010101010101010101010109 +:1057900001010101010101010101010101010101F9 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101010101010101010101B9 +:1057E00001010101010101010101010101010101A9 +:1057F0000101010101010101010101010101010199 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010187 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000101010101010101010101010101010186 +:105A10000101010101010101010101010101010176 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010101010101010101010116 +:105A80000101010101010101010101010101010106 +:105A900001010101010101010101010101010101F6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00001010101010101010101010101010101C6 +:105AD00001010101010101010101010101010101B6 +:105AE00001010101010101010101010101010101A6 +:105AF0000101010101010101010101010101010196 +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010076 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F1000000000000000000000000000000000027F +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202004F +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:107410000000000000000000000000000000005D0F +:107420000000000000000001010101010101010153 +:10743000010101010101010101010101010101013C +:10744000010101010101010101010101010101012C +:10745000010101010101010101010101010101011C +:10746000010101010101010101010101010101010C +:1074700001010101010101010101010101010101FC +:1074800001010101010101010101010101010101EC +:1074900001010101010101010101010101010101DC +:1074A00001010101010101010101010101010101CC +:1074B00001010101010101010101010101010101BC +:1074C00001010101010101010101010101010101AC +:1074D000010101010101010101010101010101019C +:1074E000010101010101010101010101010101018C +:1074F000010101010101010101010101010101017C +:10750000010101010101010101010101010101016B +:10751000010101010101010101010101010101015B +:10752000010101010101010101010101010101014B +:10753000010101010101010101010101010101013B +:10754000010101010101010101010101010101012B +:10755000010101010101010101010101010101011B +:10756000010101010101010101010101010101010B +:1075700001010101010101010101010101010101FB +:1075800001010101010101010101010101010101EB +:1075900001010101010101010101010101010101DB +:1075A00001010101010101010101010101010101CB +:1075B00001010101010101010101010101010101BB +:1075C00001010101010101010101010101010101AB +:1075D000010101010101010101010101010101019B +:1075E000010101010101010101010101010101018B +:1075F000010101010101010101010101010101017B +:10760000010101010101010101010101010101016A +:10761000010101010101010101010101010101015A +:10762000010101010101010101010101010101014A +:10763000010101010101010101010101010101013A +:10764000010101010101010101010101010101012A +:10765000010101010101010101010101010101011A +:10766000010101010101010101010101010101010A +:1076700001010101010101010101010101010101FA +:1076800001010101010101010101010101010101EA +:1076900001010101010101010101010101010101DA +:1076A00001010101010101010101010101010101CA +:1076B00001010101010101010101010101010101BA +:1076C00001010101010101010101010101010101AA +:1076D000010101010101010101010101010101019A +:1076E000010101010101010101010101010101018A +:1076F000010101010101010101010101010101017A +:107700000101010101010101010101010101010169 +:107710000101010101010101010101010101010159 +:107720000101010101010101010101010101010149 +:107730000101010101010101010101010101010139 +:107740000101010101010101010101010101010129 +:107750000101010101010101010101010101010119 +:107760000101010101010101010101010101010109 +:1077700001010101010101010101010101010101F9 +:1077800001010101010101010101010101010101E9 +:1077900001010101010101010101010101010101D9 +:1077A00001010101010101010101010101010101C9 +:1077B00001010101010101010101010101010101B9 +:1077C00001010101010101010101010101010101A9 +:1077D0000101010101010101010101010101010199 +:1077E0000101010101010101010101010101010189 +:1077F0000101010101010101010101010101010179 +:107800000101010101010101010101010101010168 +:107810000101010101010101010101010101010158 +:107820000101010101010101010101010101010148 +:107830000101010101010101010101010101010138 +:107840000101010101010101010101010101010128 +:107850000101010101010101010101010101010118 +:107860000101010101010101010101010101010108 +:1078700001010101010101010101010101010101F8 +:1078800001010101010101010101010101010101E8 +:1078900001010101010101010101010101010101D8 +:1078A00001010101010101010101010101010101C8 +:1078B00001010101010101010101010101010101B8 +:1078C00001010101010101010101010101010101A8 +:1078D0000101010101010101010101010101010198 +:1078E0000101010101010101010101010101010188 +:1078F0000101010101010101010101010101010178 +:107900000101010101010101010101010101010167 +:107910000101010101010101010101010101010157 +:107920000101010101010101010101010101010147 +:107930000101010101010101010101010101010137 +:107940000101010101010101010101010101010127 +:107950000101010101010101010101010101010117 +:107960000101010101010101010101010101010107 +:1079700001010101010101010101010101010101F7 +:1079800001010101010101010101010101010101E7 +:1079900001010101010101010101010101010101D7 +:1079A00001010101010101010101010101010101C7 +:1079B00001010101010101010101010101010101B7 +:1079C00001010101010101010101010101010101A7 +:1079D0000101010101010101010101010101010197 +:1079E0000101010101010101010101010101010187 +:1079F0000101010101010101010101010101010177 +:107A00000101010101010101010101010101010166 +:107A10000101010101010101010101010101010156 +:107A20000101010101010101010101010101010146 +:107A30000101010101010101010101010101010136 +:107A40000101010101010101010101010101010126 +:107A50000101010101010101010101010101010116 +:107A60000101010101010101010101010101010106 +:107A700001010101010101010101010101010101F6 +:107A800001010101010101010101010101010101E6 +:107A900001010101010101010101010101010101D6 +:107AA00001010101010101010101010101010101C6 +:107AB00001010101010101010101010101010101B6 +:107AC00001010101010101010101010101010101A6 +:107AD0000101010101010101010101010101010196 +:107AE0000101010101010101010101010101010186 +:107AF0000101010101010101010101010101010176 +:107B00000101010101010101010101010101010165 +:107B10000101010101010101010101010101010155 +:107B20000101010101010101010101010101010145 +:107B30000101010101010101010101010101010135 +:107B40000101010101010101010101010101010125 +:107B50000101010101010101010101010101010115 +:107B60000101010101010101010101010101010105 +:107B700001010101010101010101010101010101F5 +:107B800001010101010101010101010101010101E5 +:107B900001010101010101010101010101010101D5 +:107BA00001010101010101010101010101010101C5 +:107BB00001010101010101010101010101010101B5 +:107BC00001010101010101010101010101010101A5 +:107BD0000101010101010101010101010101010195 +:107BE0000101010101010101010101010101010185 +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101010101010101010134 +:107C40000101010101010101010101010101010124 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010101010101010101E4 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD0000101010101010101010101010101010194 +:107CE0000101010101010101010101010101010184 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010101010101010101010123 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010101010101010101E3 +:107D900001010101010101010101010101010101D3 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010100000000000000000041 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000002020202020202020232 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202020202020202020202C4 +:108C900002020202020202020202020202020202B4 +:108CA00002020202020202020202020202020202A4 +:108CB0000202020202020202020202020202020294 +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020202020202020202020274 +:108CE0000202020202020202020202020202020264 +:108CF0000202020202020202020202020202020254 +:108D00000202020202020202020202020202020243 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202020202D3 +:108D800002020202020202020202020202020202C3 +:108D900002020202020202020202020202020202B3 +:108DA00002020202020202020202020202020202A3 +:108DB0000202020202020202020202020202020293 +:108DC0000202020202020202020202020202020283 +:108DD0000202020202020202020202020202020273 +:108DE0000202020202020202020202020202020263 +:108DF0000202020202020202020202020202020253 +:108E00000202020202020202020202020202020242 +:108E10000202020202020202020202020202020232 +:108E20000202020202020202020202020202020222 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202020202020202020202C2 +:108E900002020202020202020202020202020202B2 +:108EA00002020202020202020202020202020202A2 +:108EB0000202020202020202020202020202020292 +:108EC0000202020202020202020202020202020282 +:108ED0000202020202020202020202020202020272 +:108EE0000202020202020202020202020202020262 +:108EF0000202020202020202020202020202020252 +:108F00000202020202020202020202020202020241 +:108F10000202020202020202020202020202020231 +:108F20000202020202020202020202020202020221 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202020202020202020202D1 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020202020202020202A1 +:108FB0000202020202020202020202020202020291 +:108FC0000202020202020202020202020202020281 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202020202020261 +:108FF0000202020202020202020202020202020251 +:109000000202020202020202020202020202020240 +:109010000202020202020202020202020202020230 +:109020000202020202020202020202020202020220 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020202020202020202020202A0 +:1090B0000202020202020202020202020202020290 +:1090C0000202020202020202020202020202020280 +:1090D0000202020202020202020202020202020270 +:1090E0000202020202020202020202020202020260 +:1090F0000202020202020202020202020202020250 +:10910000020202020202020202020202020202023F +:10911000020202020202020202020202020202022F +:10912000020202020202020202020202020202021F +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D000020202020202020202020202020202026F +:1091E000020202020202020202020202020202025F +:1091F000020202020202020202020202020202024F +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202020202025E +:1092F000020202020202020202020202020202024E +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202029D +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202020202025D +:1093F000020202020202020202020202020202024D +:10940000020202020202020202020202020202023C +:10941000020202020202020202020202020202022C +:10942000020202020202020202020202020202021C +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020202AC +:1094A000020202020202020202020202020202029C +:1094B000020202020202020202020202020202028C +:1094C000020202020202020202020202020202027C +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202020202020202020202024C +:10950000020202020202020202020202020202023B +:10951000020202020202020202020202020202022B +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020202AB +:1095A000020202020202020202020202020202029B +:1095B000020202020202020202020202020202028B +:1095C000020202020202020202020202020202027B +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020202020202020202022A +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202020202029A +:1096B000020202020202020202020202020202028A +:1096C000020202020202020202020202020202027A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A0000202020202020202020202020202020299 +:1097B0000202020202020202020202020202020289 +:1097C0000202020202020202020202020202020279 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:109810000202020202020202020202020202020228 +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020202020298 +:1098B0000202020202020202020202020202020288 +:1098C0000202020202020202020202020202020278 +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B0000202020202020202020202020202020287 +:1099C0000202020202020202020202020202020277 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020202020226 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020202A6 +:109AA0000202020202020202020202020202020296 +:109AB0000202020202020202020202020202020286 +:109AC0000202020202020202020202020202020276 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020202A5 +:109BA0000202020202020202020202020202020295 +:109BB0000202020202020202020202020202020285 +:109BC0000202020202020202020202020202020275 +:109BD0000202020202020202020202020202020265 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020202A4 +:109CA0000202020202020202020202020202020294 +:109CB0000202020202020202020202020202020284 +:109CC0000202020202020202020202020202020274 +:109CD0000202020202020202020202020202020264 +:109CE0000202020202020202020202020202020254 +:109CF0000202020202020202020202020202020244 +:109D00000202020202020202020202020202020233 +:109D10000202020202020202020202020202020223 +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020202020202020202020202020202E3 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020202A3 +:109DA0000202020202020202020202020202020293 +:109DB0000202020202020202020202020202020283 +:109DC0000202020202020202020202020202020273 +:109DD0000202020202020202020202020202020263 +:109DE0000202020202020202020202020202020253 +:109DF0000202020202020202020202020202020243 +:109E00000202020202020202020202020202020232 +:109E10000202020202020202020202020202020222 +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202020202020202E2 +:109E600002020202020202020202020202020202D2 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020202A2 +:109EA0000202020202020202020202020202020292 +:109EB0000202020202020202020202020202020282 +:109EC0000202020202020202020202020202020272 +:109ED0000202020202020202020202020202020262 +:109EE0000202020202020202020202020202020252 +:109EF0000202020202020202020202020202020242 +:109F00000202020202020202020202020202020231 +:109F10000202020202020202020202020202020221 +:109F20000202020202020202020202020202020211 +:109F30000202020202020202020202020202020201 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202020202020202E1 +:109F600002020202020202020202020202020202D1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020202A1 +:109FA0000202020202020202020202020202020291 +:109FB0000202020202020202020202020202020281 +:109FC0000202020202020202020202020202020271 +:109FD0000202020202020202020202020202020261 +:109FE0000202020202020202020202020202020251 +:109FF0000202020202020202020202020202020241 +:10A000000202020202020202020202020202020230 +:10A010000202020202020202020202020202020220 +:10A020000202020202020200000000000000000022 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A420000000000000000001010101010101010123 +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010101DC +:10A4700001010101010101010101010101010101CC +:10A4800001010101010101010101010101010101BC +:10A4900001010101010101010101010101010101AC +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800001010101010101010101010101010101BB +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010101010101010101010101010101BA +:10A6900001010101010101010101010101010101AA +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010101B9 +:10A7900001010101010101010101010101010101A9 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB10000101010101010101010101010101010125 +:10AB20000101010101010101010101010101010115 +:10AB30000101010101010101010101010101010105 +:10AB400001010101010101010101010101010101F5 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010101C5 +:10AB800001010101010101010101010101010101B5 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010185 +:10ABC0000101010101010101010101010101010175 +:10ABD0000101010101010101010101010101010165 +:10ABE0000101010101010101010101010101010155 +:10ABF0000101010101010101010101010101010145 +:10AC00000101010101010101010101010101010134 +:10AC10000101010101010101010101010101010124 +:10AC20000101010101010101010101010101010114 +:10AC30000101010101010101010101010101010104 +:10AC400001010101010101010101010101010101F4 +:10AC500001010101010101010101010101010101E4 +:10AC600001010101010101010101010101010101D4 +:10AC700001010101010101010101010101010101C4 +:10AC800001010101010101010101010101010101B4 +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010184 +:10ACC0000101010101010101010101010101010174 +:10ACD0000101010101010101010101010101010164 +:10ACE0000101010101010101010101010101010154 +:10ACF0000101010101010101010101010101010144 +:10AD00000101010101010101010101010101010133 +:10AD10000101010101010101010101010101010123 +:10AD20000101010101010101010101010101010113 +:10AD30000101010101010101010101010101010103 +:10AD400001010101010101010101010101010101F3 +:10AD500001010101010101010101010101010101E3 +:10AD600001010101010101010101010101010101D3 +:10AD700001010101010101010101010101010101C3 +:10AD800001010101010101010101010101010101B3 +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010183 +:10ADC0000101010101010101010101010101010173 +:10ADD0000101010101010101010101010101010163 +:10ADE0000101010101010101010101010101010153 +:10ADF0000101010101010101010101010101010143 +:10AE00000101010101010101010101010101010132 +:10AE10000101010101010101010101010101010122 +:10AE20000101010101010101010101010101010112 +:10AE30000101010101010101010101010101010102 +:10AE400001010101010101010101010101010101F2 +:10AE500001010101010101010101010101010101E2 +:10AE600001010101010101010101010101010101D2 +:10AE700001010101010101010101010101010101C2 +:10AE800001010101010101010101010101010101B2 +:10AE900001010101010101010101010101010101A2 +:10AEA0000101010101010101010101010101010192 +:10AEB0000101010101010101010101010101010182 +:10AEC0000101010101010101010101010101010172 +:10AED0000101010101010101010101010101010162 +:10AEE0000101010101010101010101010101010152 +:10AEF0000101010101010101010101010101010142 +:10AF00000101010101010101010101010101010131 +:10AF10000101010101010101010101010101010121 +:10AF20000101010101010101010101010101010111 +:10AF30000101010101010101010101010101010101 +:10AF400001010101010101010101010101010101F1 +:10AF500001010101010101010101010101010101E1 +:10AF600001010101010101010101010101010101D1 +:10AF700001010101010101010101010101010101C1 +:10AF800001010101010101010101010101010101B1 +:10AF900001010101010101010101010101010101A1 +:10AFA0000101010101010101010101010101010191 +:10AFB0000101010101010101010101010101010181 +:10AFC0000101010101010101010101010101010171 +:10AFD0000101010101010101010101010101010161 +:10AFE0000101010101010101010101010101010151 +:10AFF0000101010101010101010101010101010141 +:10B000000101010101010101010101010101010130 +:10B010000101010101010101010101010101010120 +:10B020000101010101010101010101010101010110 +:10B030000101010101010101010101010101010100 +:10B0400001010101010101010101010101010101F0 +:10B0500001010101010101010101010101010101E0 +:10B0600001010101010101010101010101010101D0 +:10B0700001010101010101010101010101010101C0 +:10B0800001010101010101010101010101010101B0 +:10B0900001010101010101010101010101010101A0 +:10B0A0000101010101010101010101010101010190 +:10B0B0000101010101010101010101010101010180 +:10B0C0000101010101010101010101010101010170 +:10B0D0000101010101010101010101010101010160 +:10B0E0000101010101010101010101010101010150 +:10B0F0000101010101010101010101010101010140 +:10B10000010101010101010101010101010101012F +:10B11000010101010101010101010101010101011F +:10B12000010101010101010101010101010101010F +:10B1300001010101010101010101010101010101FF +:10B1400001010101010101010101010101010101EF +:10B1500001010101010101010101010101010101DF +:10B1600001010101010101010101010101010101CF +:10B1700001010101010101010101010101010101BF +:10B1800001010101010101010101010101010101AF +:10B19000010101010101010101010101010101019F +:10B1A000010101010101010101010101010101018F +:10B1B000010101010101010101010101010101017F +:10B1C000010101010101010101010101010101016F +:10B1D000010101010101010101010101010101015F +:10B1E000010101010101010101010101010101014F +:10B1F000010101010101010101010101010101013F +:10B20000010101010101010101010101010101012E +:10B21000010101010101010101010101010101011E +:10B22000010101010101010101010101010101010E +:10B2300001010101010101010101010101010101FE +:10B2400001010101010101010101010101010101EE +:10B2500001010101010101010101010101010101DE +:10B2600001010101010101010101010101010101CE +:10B2700001010101010101010101010101010101BE +:10B2800001010101010101010101010101010101AE +:10B29000010101010101010101010101010101019E +:10B2A000010101010101010101010101010101018E +:10B2B000010101010101010101010101010101017E +:10B2C000010101010101010101010101010101016E +:10B2D000010101010101010101010101010101015E +:10B2E000010101010101010101010101010101014E +:10B2F000010101010101010101010101010101013E +:10B30000010101010101010101010101010101012D +:10B31000010101010101010101010101010101011D +:10B32000010101010101010101010101010101010D +:10B3300001010101010101010101010101010101FD +:10B3400001010101010101010101010101010101ED +:10B3500001010101010101010101010101010101DD +:10B3600001010101010101010101010101010101CD +:10B3700001010101010101010101010101010101BD +:10B3800001010101010101010101010101010101AD +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010101010101010101018D +:10B3B000010101010101010101010101010101017D +:10B3C000010101010101010101010101010101016D +:10B3D000010101010101010101010101010101015D +:10B3E000010101010101010101010101010101014D +:10B3F000010101010101010101010101010101013D +:10B40000010101010101010101010101010101012C +:10B41000010101010101010101010101010101011C +:10B42000010101010101010101010101010101010C +:10B4300001010101010101010101010101010101FC +:10B4400001010101010101010101010101010101EC +:10B4500001010101010101010101010101010101DC +:10B4600001010101010101010101010101010101CC +:10B4700001010101010101010101010101010101BC +:10B4800001010101010101010101010101010101AC +:10B49000010101010101010101010101010101019C +:10B4A000010101010101010101010101010101018C +:10B4B000010101010101010101010101010101017C +:10B4C000010101010101010101010101010101016C +:10B4D000010101010101010101010101010101015C +:10B4E000010101010101010101010101010101014C +:10B4F000010101010101010101010101010101013C +:10B50000010101010101010101010101010101012B +:10B51000010101010101010101010101010101011B +:10B52000010101010101010101010101010101010B +:10B5300001010101010101010101010101010101FB +:10B5400001010101010101010101010101010101EB +:10B5500001010101010101010101010101010101DB +:10B5600001010101010101010101010101010101CB +:10B5700001010101010101010101010101010101BB +:10B5800001010101010101010101010101010101AB +:10B59000010101010101010101010101010101019B +:10B5A000010101010101010101010101010101018B +:10B5B000010101010101010101010101010101017B +:10B5C000010101010101010101010101010101016B +:10B5D000010101010101010101010101010101015B +:10B5E000010101010101010101010101010101014B +:10B5F000010101010101010101010101010101013B +:10B60000010101010101010101010101010101012A +:10B61000010101010101010101010101010101011A +:10B62000010101010101010101010101010101010A +:10B6300001010101010101010101010101010101FA +:10B6400001010101010101010101010101010101EA +:10B6500001010101010101010101010101010101DA +:10B6600001010101010101010101010101010101CA +:10B6700001010101010101010101010101010101BA +:10B6800001010101010101010101010101010101AA +:10B69000010101010101010101010101010101019A +:10B6A000010101010101010101010101010101018A +:10B6B000010101010101010101010101010101017A +:10B6C000010101010101010101010101010101016A +:10B6D000010101010101010101010101010101015A +:10B6E000010101010101010101010101010101014A +:10B6F000010101010101010101010101010101013A +:10B700000101010101010101010101010101010129 +:10B710000101010101010101010101010101010119 +:10B720000101010101010101010101010101010109 +:10B7300001010101010101010101010101010101F9 +:10B7400001010101010101010101010101010101E9 +:10B7500001010101010101010101010101010101D9 +:10B7600001010101010101010101010101010101C9 +:10B7700001010101010101010101010101010101B9 +:10B7800001010101010101010101010101010101A9 +:10B790000101010101010101010101010101010199 +:10B7A0000101010101010101010101010101010189 +:10B7B0000101010101010101010101010101010179 +:10B7C0000101010101010101010101010101010169 +:10B7D0000101010101010101010101010101010159 +:10B7E0000101010101010101010101010101010149 +:10B7F0000101010101010101010101010101010139 +:10B800000101010101010101010101010101010128 +:10B810000101010101010101010101010101010118 +:10B820000101010101010100000000000000000011 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000002020202020202020202 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020251 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202023D +:10C3E000020202020202020202020202020202022D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202023C +:10C4E000020202020202020202020202020202022C +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000020202020202020202020202020202022B +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202023A +:10C6E000020202020202020202020202020202022A +:10C6F000020202020202020202020202020202021A +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020202020202020202020202020249 +:10C7D0000202020202020202020202020202020239 +:10C7E0000202020202020202020202020202020229 +:10C7F0000202020202020202020202020202020219 +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020202020202020202020202020248 +:10C8D0000202020202020202020202020202020238 +:10C8E0000202020202020202020202020202020228 +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020257 +:10C9C0000202020202020202020202020202020247 +:10C9D0000202020202020202020202020202020237 +:10C9E0000202020202020202020202020202020227 +:10C9F0000202020202020202020202020202020217 +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020233 +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202020202020202020202020213 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020202020252 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020232 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202020202020202020202020212 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020231 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202020202020202020202020211 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202000000000000000000F2 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D12000000000000000005D0000000000000001A1 +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010101010101AE +:10D27000010101010101010101010101010101019E +:10D28000010101010101010101010101010101018E +:10D29000010101010101010101010101010101017E +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010101FC +:10D4200001010101010101010101010101010101EC +:10D4300001010101010101010101010101010101DC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101017C +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010101CA +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010101AA +:10D67000010101010101010101010101010101019A +:10D68000010101010101010101010101010101018A +:10D69000010101010101010101010101010101017A +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000010101010101010101010101010101014A +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010101A9 +:10D770000101010101010101010101010101010199 +:10D780000101010101010101010101010101010189 +:10D790000101010101010101010101010101010179 +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000101010101010101010101010101010149 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010101010101010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010147 +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010101010101010101010146 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF0000101010101010101010101010101010115 +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010184 +:10DC90000101010101010101010101010101010174 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010101010101010101010114 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010101010101010101010173 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE90000101010101010101010101010101010172 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101010101010101010101DF +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101010101010101010101AF +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101010101010101DC +:10E4300001010101010101010101010101010101CC +:10E4400001010101010101010101010101010101BC +:10E4500001010101010101010101010101010101AC +:10E46000010101010101010101010101010101019C +:10E47000010101010101010101010101010101018C +:10E48000010101010101010101010101010101017C +:10E49000010101010101010101010101010101016C +:10E4A000010101010101010101010101010101015C +:10E4B000010101010101010101010101010101014C +:10E4C000010101010101010101010101010101013C +:10E4D000010101010101010101010101010101012C +:10E4E000010101010101010101010101010101011C +:10E4F000010101010101010101010101010101010C +:10E5000001010101010101010101010101010101FB +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010100DC +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000002E5 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202020202020202020202020202F7 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020202020202020202020202020202C6 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020203 +:10EDF00002020202020202020202020202020202F3 +:10EE000002020202020202020202020202020202E2 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202020202020202020202F2 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020202020202020202020202A1 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020202020202020221 +:10EFD0000202020202020202020202020202020211 +:10EFE0000202020202020202020202020202020201 +:10EFF00002020202020202020202020202020202F1 +:10F0000002020202020202020202020202020202E0 +:10F0100002020202020202020202020202020202D0 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020202020202020202020202B0 +:10F0400002020202020202020202020202020202A0 +:10F050000202020202020202020202020202020290 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020202020202020202020230 +:10F0C0000202020202020202020202020202020220 +:10F0D0000202020202020202020202020202020210 +:10F0E0000202020202020202020202020202020200 +:10F0F00002020202020202020202020202020202F0 +:10F1000002020202020202020202020202020202DF +:10F1100002020202020202020202020202020202CF +:10F1200002020202020202020202020202020202BF +:10F1300002020202020202020202020202020202AF +:10F14000020202020202020202020202020202029F +:10F15000020202020202020202020202020202028F +:10F16000020202020202020202020202020202027F +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A000020202020202020202020202020202023F +:10F1B000020202020202020202020202020202022F +:10F1C000020202020202020202020202020202021F +:10F1D000020202020202020202020202020202020F +:10F1E00002020202020202020202020202020202FF +:10F1F00002020202020202020202020202020202EF +:10F2000002020202020202020202020202020202DE +:10F2100002020202020202020202020202020202CE +:10F2200002020202020202020202020202020202BE +:10F2300002020202020202020202020202020202AE +:10F24000020202020202020202020202020202029E +:10F25000020202020202020202020202020202028E +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202020202020202023E +:10F2B000020202020202020202020202020202022E +:10F2C000020202020202020202020202020202021E +:10F2D000020202020202020202020202020202020E +:10F2E00002020202020202020202020202020202FE +:10F2F00002020202020202020202020202020202EE +:10F3000002020202020202020202020202020202DD +:10F3100002020202020202020202020202020202CD +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020202020202AD +:10F34000020202020202020202020202020202029D +:10F35000020202020202020202020202020202028D +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B000020202020202020202020202020202022D +:10F3C000020202020202020202020202020202021D +:10F3D000020202020202020202020202020202020D +:10F3E00002020202020202020202020202020202FD +:10F3F00002020202020202020202020202020202ED +:10F4000002020202020202020202020202020202DC +:10F4100002020202020202020202020202020202CC +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020202029C +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202020202027C +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C000020202020202020202020202020202021C +:10F4D000020202020202020202020202020202020C +:10F4E00002020202020202020202020202020202FC +:10F4F00002020202020202020202020202020202EC +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020202020202020202CB +:10F5200002020202020202020202020202020202BB +:10F5300002020202020202020202020202020202AB +:10F54000020202020202020202020202020202029B +:10F55000020202020202020202020202020202028B +:10F56000020202020202020202020202020202027B +:10F57000020202020202020202020202020202026B +:10F58000020202020202020202020202020202025B +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B000020202020202020202020202020202022B +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020202020202020202020B +:10F5E00002020202020202020202020202020202FB +:10F5F00002020202020202020202020202020202EB +:10F6000002020202020202020202020202020202DA +:10F6100002020202020202020202020202020202CA +:10F6200002020202020202020202020202020202BA +:10F6300002020202020202020202020202020202AA +:10F64000020202020202020202020202020202029A +:10F65000020202020202020202020202020202028A +:10F66000020202020202020202020202020202027A +:10F67000020202020202020202020202020202026A +:10F68000020202020202020202020202020202025A +:10F69000020202020202020202020202020202024A +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020202020202020202020A +:10F6E00002020202020202020202020202020202FA +:10F6F00002020202020202020202020202020202EA +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020202020202020202020202C9 +:10F7200002020202020202020202020202020202B9 +:10F7300002020202020202020202020202020202A9 +:10F740000202020202020202020202020202020299 +:10F750000202020202020202020202020202020289 +:10F760000202020202020202020202020202020279 +:10F770000202020202020202020202020202020269 +:10F780000202020202020202020202020202020259 +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020202020202020202020202B8 +:10F8300002020202020202020202020202020202A8 +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202020202020202020202A7 +:10F940000202020202020202020202020202020297 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020277 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020200B5 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:0200000260009C +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000000000000000000001CE +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010198 +:100850000101010101010101010101010101010188 +:100860000101010101010101010101010101010178 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010118 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000001010101010101010101010101010101D2 +:100E100001010101010101010101010101010101C2 +:100E200001010101010101010101010101010101B2 +:100E300001010101010101010101010101010101A2 +:100E40000101010101010101010101010101010192 +:100E50000101010101010101010101010101010182 +:100E60000101010101010101010101010101010172 +:100E70000101010101010101010101010101010162 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101010101010101010101E2 +:100F000001010101010101010101010101010101D1 +:100F100001010101010101010101010101010101C1 +:100F200001010101010101010101010101010101B1 +:100F300001010101010101010101010101010101A1 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000101010101010101010101010101010171 +:100F70000101010101010101010101010101010161 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101010101010101010101E1 +:1010000001010101010101010101010101010101D0 +:1010100001010101010101010101010101010101C0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000101010101010101010101010101010170 +:101070000101010101010101010101010101010160 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010101010101BF +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:10116000010101010101010101010101010101016F +:10117000010101010101010101010101010101015F +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010101010101BE +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101016E +:10127000010101010101010101010101010101015E +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101010101010101010101BD +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101016D +:10137000010101010101010101010101010101015D +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101016C +:10147000010101010101010101010101010101015C +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010100AC +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000000000000000000019 +:1017D0000000000000000000000000000000000009 +:1017E00000000000000000000000000000000000F9 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000000000000000000000F8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000002B5 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020202020202020202020217 +:1019B0000202020202020202020202020202020207 +:1019C00002020202020202020202020202020202F7 +:1019D00002020202020202020202020202020202E7 +:1019E00002020202020202020202020202020202D7 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000202020202020202020202020202020216 +:101AB0000202020202020202020202020202020206 +:101AC00002020202020202020202020202020202F6 +:101AD00002020202020202020202020202020202E6 +:101AE00002020202020202020202020202020202D6 +:101AF00002020202020202020202020202020202C6 +:101B000002020202020202020202020202020202B5 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA0000202020202020202020202020202020215 +:101BB0000202020202020202020202020202020205 +:101BC00002020202020202020202020202020202F5 +:101BD00002020202020202020202020202020202E5 +:101BE00002020202020202020202020202020202D5 +:101BF00002020202020202020202020202020202C5 +:101C000002020202020202020202020202020202B4 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA0000202020202020202020202020202020214 +:101CB0000202020202020202020202020202020204 +:101CC00002020202020202020202020202020202F4 +:101CD00002020202020202020202020202020202E4 +:101CE00002020202020202020202020202020202D4 +:101CF00002020202020202020202020202020202C4 +:101D000002020202020202020202020202020202B3 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020202020203 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020202D3 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202020202 +:101EC00002020202020202020202020202020202F2 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020202D2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020202D0 +:1020F00002020202020202020202020202020202C0 +:1021000002020202020202020202020202020202AF +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020202020202020202020F +:1021B00002020202020202020202020202020202FF +:1021C00002020202020202020202020202020202EF +:1021D00002020202020202020202020202020202DF +:1021E00002020202020202020202020202020202CF +:1021F00002020202020202020202020202020202BF +:1022000002020202020202020202020202020202AE +:10221000020202020202020202020202020202029E +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A000020202020202020202020202020202020E +:1022B00002020202020202020202020202020202FE +:1022C00002020202020202020202020202020202EE +:1022D00002020202020202020202020202020202DE +:1022E00002020202020202020202020202020202CE +:1022F00002020202020202020202020202020202BE +:1023000002020202020202020202020202020202AD +:10231000020202020202020202020202020202029D +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A000020202020202020202020202020202020D +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020202020202ED +:1023D00002020202020202020202020202020202DD +:1023E00002020202020202020202020202020202CD +:1023F00002020202020202020202020202020202BD +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202020202020202020202DC +:1024E00002020202020202020202020202020202CC +:1024F00002020202020202020202020202020202BC +:1025000002020202020202020202020202020202AB +:10251000020202020202020202020202020202029B +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C00002020202020202020202020202020202EB +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020202CB +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202020202020202020202DA +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020085 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E20000000000000000000000000000000006141 +:102E30000000000000000001010101010101010189 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010132 +:102E90000101010101010101010101010101010122 +:102EA0000101010101010101010101010101010112 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010101D2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:10317000010101010101010101010101010101013F +:10318000010101010101010101010101010101012F +:10319000010101010101010101010101010101011F +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000010101010101010101010101010101014E +:10327000010101010101010101010101010101013E +:10328000010101010101010101010101010101012E +:10329000010101010101010101010101010101011E +:1032A000010101010101010101010101010101010E +:1032B00001010101010101010101010101010101FE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000010101010101010101010101010101011D +:1033A000010101010101010101010101010101010D +:1033B00001010101010101010101010101010101FD +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000010101010101010101010101010101017C +:10344000010101010101010101010101010101016C +:10345000010101010101010101010101010101015C +:10346000010101010101010101010101010101014C +:10347000010101010101010101010101010101013C +:10348000010101010101010101010101010101012C +:10349000010101010101010101010101010101011C +:1034A000010101010101010101010101010101010C +:1034B00001010101010101010101010101010101FC +:1034C00001010101010101010101010101010101EC +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101014A +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A000010101010101010101010101010101010A +:1036B00001010101010101010101010101010101FA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010101F8 +:1038C00001010101010101010101010101010101E8 +:1038D00001010101010101010101010101010101D8 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010101010101010101010167 +:103950000101010101010101010101010101010157 +:103960000101010101010101010101010101010147 +:103970000101010101010101010101010101010137 +:103980000101010101010101010101010101010127 +:103990000101010101010101010101010101010117 +:1039A0000101010101010101010101010101010107 +:1039B00001010101010101010101010101010101F7 +:1039C00001010101010101010101010101010101E7 +:1039D00001010101010101010101010101010101D7 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000101010101010101010101010101010176 +:103A40000101010101010101010101010101010166 +:103A50000101010101010101010101010101010156 +:103A60000101010101010101010101010101010146 +:103A70000101010101010101010101010101010136 +:103A80000101010101010101010101010101010126 +:103A90000101010101010101010101010101010116 +:103AA0000101010101010101010101010101010106 +:103AB00001010101010101010101010101010101F6 +:103AC00001010101010101010101010101010101E6 +:103AD00001010101010101010101010101010101D6 +:103AE00001010101010101010101010101010101C6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000101010101010101010101010101010135 +:103B80000101010101010101010101010101010125 +:103B90000101010101010101010101010101010115 +:103BA0000101010101010101010101010101010105 +:103BB00001010101010101010101010101010101F5 +:103BC00001010101010101010101010101010101E5 +:103BD00001010101010101010101010101010101D5 +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C60000101010101010101010101010101010144 +:103C70000101010101010101010101010101010134 +:103C80000101010101010101010101010101010124 +:103C90000101010101010101010101010101010114 +:103CA0000101010101010101010101010101010104 +:103CB00001010101010101010101010101010101F4 +:103CC00001010101010101010101010101010101E4 +:103CD00001010101010101010101010101010101D4 +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010101B4 +:103D000001010101010101010101010101010101A3 +:103D10000101010101010101010101010101010193 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000101010101010101010101010101010103 +:103DB00001010101010101010101010101010101F3 +:103DC00001010101010101010101010101010101E3 +:103DD00001010101010101010101010101010101D3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101010101010101010101B3 +:103E000001010101010101010101010101010101A2 +:103E10000101010101010101010101010101010192 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010172 +:103E40000101010101010101010101010101010162 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000101010101010101010101010101010112 +:103EA0000101010101010101010101010101010102 +:103EB00001010101010101010101010101010101F2 +:103EC00001010101010101010101010101010101E2 +:103ED00001010101010101010101010101010101D2 +:103EE00001010101010101010101010101010101C2 +:103EF00001010101010101010101010101010101B2 +:103F000001010101010101010101010101010101A1 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010171 +:103F40000101010101010101010101010101010161 +:103F50000101010101010101010101010101010151 +:103F60000101010101010101010101010101010141 +:103F70000101010101010101010101010101010131 +:103F80000101010101010101010101010101010121 +:103F90000101010101010101010101010101010111 +:103FA0000101010101010101010101010101010101 +:103FB00001010101010101010101010101010101F1 +:103FC00001010101010101010101010101010101E1 +:103FD00001010101010101010101010101010101D1 +:103FE00001010101010101010101010101010101C1 +:103FF00001010101010101010101010101010101B1 +:1040000001010101010101010101010101010101A0 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:104030000101010101010101010101010101010170 +:104040000101010101010101010101010101010160 +:104050000101010101010101010101010101010150 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:104080000101010101010101010101010101010120 +:104090000101010101010101010101010101010110 +:1040A0000101010101010101010101010101010100 +:1040B00001010101010101010101010101010101F0 +:1040C00001010101010101010101010101010101E0 +:1040D00001010101010101010101010101010101D0 +:1040E00001010101010101010101010101010101C0 +:1040F00001010101010101010101010101010101B0 +:10410000010101010101010101010101010101019F +:10411000010101010101010101010101010101018F +:10412000010101010101010101010101010101017F +:10413000010101010101010101010101010101016F +:10414000010101010101010101010101010101015F +:10415000010101010101010101010101010101014F +:10416000010101010101010101010101010101013F +:10417000010101010101010101010101010101012F +:10418000010101010101010101010101010101011F +:10419000010101010101010101010101010101010F +:1041A00001010101010101010101010101010101FF +:1041B00001010101010101010101010101010101EF +:1041C00001010101010101010101010101010101DF +:1041D00001010101010101010101010101010101CF +:1041E00001010101010101010101010101010101BF +:1041F00001010101010101010101010101010101AF +:10420000010101010101010101010101010101019E +:10421000010101010101010101010101010101018E +:10422000010101010101010101010101010101017E +:104230000101010101010100000000000000000077 +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:104630000000000000000002020202020202020268 +:10464000020202020202020202020202020202024A +:10465000020202020202020202020202020202023A +:10466000020202020202020202020202020202022A +:10467000020202020202020202020202020202021A +:10468000020202020202020202020202020202020A +:1046900002020202020202020202020202020202FA +:1046A00002020202020202020202020202020202EA +:1046B00002020202020202020202020202020202DA +:1046C00002020202020202020202020202020202CA +:1046D00002020202020202020202020202020202BA +:1046E00002020202020202020202020202020202AA +:1046F000020202020202020202020202020202029A +:104700000202020202020202020202020202020289 +:104710000202020202020202020202020202020279 +:104720000202020202020202020202020202020269 +:104730000202020202020202020202020202020259 +:104740000202020202020202020202020202020249 +:104750000202020202020202020202020202020239 +:104760000202020202020202020202020202020229 +:104770000202020202020202020202020202020219 +:104780000202020202020202020202020202020209 +:1047900002020202020202020202020202020202F9 +:1047A00002020202020202020202020202020202E9 +:1047B00002020202020202020202020202020202D9 +:1047C00002020202020202020202020202020202C9 +:1047D00002020202020202020202020202020202B9 +:1047E00002020202020202020202020202020202A9 +:1047F0000202020202020202020202020202020299 +:104800000202020202020202020202020202020288 +:104810000202020202020202020202020202020278 +:104820000202020202020202020202020202020268 +:104830000202020202020202020202020202020258 +:104840000202020202020202020202020202020248 +:104850000202020202020202020202020202020238 +:104860000202020202020202020202020202020228 +:104870000202020202020202020202020202020218 +:104880000202020202020202020202020202020208 +:1048900002020202020202020202020202020202F8 +:1048A00002020202020202020202020202020202E8 +:1048B00002020202020202020202020202020202D8 +:1048C00002020202020202020202020202020202C8 +:1048D00002020202020202020202020202020202B8 +:1048E00002020202020202020202020202020202A8 +:1048F0000202020202020202020202020202020298 +:104900000202020202020202020202020202020287 +:104910000202020202020202020202020202020277 +:104920000202020202020202020202020202020267 +:104930000202020202020202020202020202020257 +:104940000202020202020202020202020202020247 +:104950000202020202020202020202020202020237 +:104960000202020202020202020202020202020227 +:104970000202020202020202020202020202020217 +:104980000202020202020202020202020202020207 +:1049900002020202020202020202020202020202F7 +:1049A00002020202020202020202020202020202E7 +:1049B00002020202020202020202020202020202D7 +:1049C00002020202020202020202020202020202C7 +:1049D00002020202020202020202020202020202B7 +:1049E00002020202020202020202020202020202A7 +:1049F0000202020202020202020202020202020297 +:104A00000202020202020202020202020202020286 +:104A10000202020202020202020202020202020276 +:104A20000202020202020202020202020202020266 +:104A30000202020202020202020202020202020256 +:104A40000202020202020202020202020202020246 +:104A50000202020202020202020202020202020236 +:104A60000202020202020202020202020202020226 +:104A70000202020202020202020202020202020216 +:104A80000202020202020202020202020202020206 +:104A900002020202020202020202020202020202F6 +:104AA00002020202020202020202020202020202E6 +:104AB00002020202020202020202020202020202D6 +:104AC00002020202020202020202020202020202C6 +:104AD00002020202020202020202020202020202B6 +:104AE00002020202020202020202020202020202A6 +:104AF0000202020202020202020202020202020296 +:104B00000202020202020202020202020202020285 +:104B10000202020202020202020202020202020275 +:104B20000202020202020202020202020202020265 +:104B30000202020202020202020202020202020255 +:104B40000202020202020202020202020202020245 +:104B50000202020202020202020202020202020235 +:104B60000202020202020202020202020202020225 +:104B70000202020202020202020202020202020215 +:104B80000202020202020202020202020202020205 +:104B900002020202020202020202020202020202F5 +:104BA00002020202020202020202020202020202E5 +:104BB00002020202020202020202020202020202D5 +:104BC00002020202020202020202020202020202C5 +:104BD00002020202020202020202020202020202B5 +:104BE00002020202020202020202020202020202A5 +:104BF0000202020202020202020202020202020295 +:104C00000202020202020202020202020202020284 +:104C10000202020202020202020202020202020274 +:104C20000202020202020202020202020202020264 +:104C30000202020202020202020202020202020254 +:104C40000202020202020202020202020202020244 +:104C50000202020202020202020202020202020234 +:104C60000202020202020202020202020202020224 +:104C70000202020202020202020202020202020214 +:104C80000202020202020202020202020202020204 +:104C900002020202020202020202020202020202F4 +:104CA00002020202020202020202020202020202E4 +:104CB00002020202020202020202020202020202D4 +:104CC00002020202020202020202020202020202C4 +:104CD00002020202020202020202020202020202B4 +:104CE00002020202020202020202020202020202A4 +:104CF0000202020202020202020202020202020294 +:104D00000202020202020202020202020202020283 +:104D10000202020202020202020202020202020273 +:104D20000202020202020202020202020202020263 +:104D30000202020202020202020202020202020253 +:104D40000202020202020202020202020202020243 +:104D50000202020202020202020202020202020233 +:104D60000202020202020202020202020202020223 +:104D70000202020202020202020202020202020213 +:104D80000202020202020202020202020202020203 +:104D900002020202020202020202020202020202F3 +:104DA00002020202020202020202020202020202E3 +:104DB00002020202020202020202020202020202D3 +:104DC00002020202020202020202020202020202C3 +:104DD00002020202020202020202020202020202B3 +:104DE00002020202020202020202020202020202A3 +:104DF0000202020202020202020202020202020293 +:104E00000202020202020202020202020202020282 +:104E10000202020202020202020202020202020272 +:104E20000202020202020202020202020202020262 +:104E30000202020202020202020202020202020252 +:104E40000202020202020202020202020202020242 +:104E50000202020202020202020202020202020232 +:104E60000202020202020202020202020202020222 +:104E70000202020202020202020202020202020212 +:104E80000202020202020202020202020202020202 +:104E900002020202020202020202020202020202F2 +:104EA00002020202020202020202020202020202E2 +:104EB00002020202020202020202020202020202D2 +:104EC00002020202020202020202020202020202C2 +:104ED00002020202020202020202020202020202B2 +:104EE00002020202020202020202020202020202A2 +:104EF0000202020202020202020202020202020292 +:104F00000202020202020202020202020202020281 +:104F10000202020202020202020202020202020271 +:104F20000202020202020202020202020202020261 +:104F30000202020202020202020202020202020251 +:104F40000202020202020202020202020202020241 +:104F50000202020202020202020202020202020231 +:104F60000202020202020202020202020202020221 +:104F70000202020202020202020202020202020211 +:104F80000202020202020202020202020202020201 +:104F900002020202020202020202020202020202F1 +:104FA00002020202020202020202020202020202E1 +:104FB00002020202020202020202020202020202D1 +:104FC00002020202020202020202020202020202C1 +:104FD00002020202020202020202020202020202B1 +:104FE00002020202020202020202020202020202A1 +:104FF0000202020202020202020202020202020291 +:105000000202020202020202020202020202020280 +:105010000202020202020202020202020202020270 +:105020000202020202020202020202020202020260 +:105030000202020202020202020202020202020250 +:105040000202020202020202020202020202020240 +:105050000202020202020202020202020202020230 +:105060000202020202020202020202020202020220 +:105070000202020202020202020202020202020210 +:105080000202020202020202020202020202020200 +:1050900002020202020202020202020202020202F0 +:1050A00002020202020202020202020202020202E0 +:1050B00002020202020202020202020202020202D0 +:1050C00002020202020202020202020202020202C0 +:1050D00002020202020202020202020202020202B0 +:1050E00002020202020202020202020202020202A0 +:1050F0000202020202020202020202020202020290 +:10510000020202020202020202020202020202027F +:10511000020202020202020202020202020202026F +:10512000020202020202020202020202020202025F +:10513000020202020202020202020202020202024F +:10514000020202020202020202020202020202023F +:10515000020202020202020202020202020202022F +:10516000020202020202020202020202020202021F +:10517000020202020202020202020202020202020F +:1051800002020202020202020202020202020202FF +:1051900002020202020202020202020202020202EF +:1051A00002020202020202020202020202020202DF +:1051B00002020202020202020202020202020202CF +:1051C00002020202020202020202020202020202BF +:1051D00002020202020202020202020202020202AF +:1051E000020202020202020202020202020202029F +:1051F000020202020202020202020202020202028F +:10520000020202020202020202020202020202027E +:10521000020202020202020202020202020202026E +:10522000020202020202020202020202020202025E +:10523000020202020202020202020202020202024E +:10524000020202020202020202020202020202023E +:10525000020202020202020202020202020202022E +:10526000020202020202020202020202020202021E +:10527000020202020202020202020202020202020E +:1052800002020202020202020202020202020202FE +:1052900002020202020202020202020202020202EE +:1052A00002020202020202020202020202020202DE +:1052B00002020202020202020202020202020202CE +:1052C00002020202020202020202020202020202BE +:1052D00002020202020202020202020202020202AE +:1052E000020202020202020202020202020202029E +:1052F000020202020202020202020202020202028E +:10530000020202020202020202020202020202027D +:10531000020202020202020202020202020202026D +:10532000020202020202020202020202020202025D +:10533000020202020202020202020202020202024D +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202020202020202020202020202ED +:1053A00002020202020202020202020202020202DD +:1053B00002020202020202020202020202020202CD +:1053C00002020202020202020202020202020202BD +:1053D00002020202020202020202020202020202AD +:1053E000020202020202020202020202020202029D +:1053F000020202020202020202020202020202028D +:10540000020202020202020202020202020202027C +:10541000020202020202020202020202020202026C +:10542000020202020202020202020202020202025C +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202020202020202020202EC +:1054A00002020202020202020202020202020202DC +:1054B00002020202020202020202020202020202CC +:1054C00002020202020202020202020202020202BC +:1054D00002020202020202020202020202020202AC +:1054E000020202020202020202020202020202029C +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020202020202020202020202020202DB +:1055B00002020202020202020202020202020202CB +:1055C00002020202020202020202020202020202BB +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020202020202020202020202020202027A +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020202020202020202020202020202DA +:1056B00002020202020202020202020202020202CA +:1056C00002020202020202020202020202020202BA +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020202020202020202D8 +:1058B00002020202020202020202020202020202C8 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020202020202020202D7 +:1059B00002020202020202020202020202020202C7 +:1059C00002020202020202020202020202020202B7 +:1059D00002020202020202020202020202020202A7 +:1059E0000202020202020202020202020202020297 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020200000000000000000058 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000001010101010101010157 +:106040000101010101010101010101010101010140 +:106050000101010101010101010101010101010130 +:106060000101010101010101010101010101010120 +:106070000101010101010101010101010101010110 +:106080000101010101010101010101010101010100 +:1060900001010101010101010101010101010101F0 +:1060A00001010101010101010101010101010101E0 +:1060B00001010101010101010101010101010101D0 +:1060C00001010101010101010101010101010101C0 +:1060D00001010101010101010101010101010101B0 +:1060E00001010101010101010101010101010101A0 +:1060F0000101010101010101010101010101010190 +:10610000010101010101010101010101010101017F +:10611000010101010101010101010101010101016F +:10612000010101010101010101010101010101015F +:10613000010101010101010101010101010101014F +:10614000010101010101010101010101010101013F +:10615000010101010101010101010101010101012F +:10616000010101010101010101010101010101011F +:10617000010101010101010101010101010101010F +:1061800001010101010101010101010101010101FF +:1061900001010101010101010101010101010101EF +:1061A00001010101010101010101010101010101DF +:1061B00001010101010101010101010101010101CF +:1061C00001010101010101010101010101010101BF +:1061D00001010101010101010101010101010101AF +:1061E000010101010101010101010101010101019F +:1061F000010101010101010101010101010101018F +:10620000010101010101010101010101010101017E +:10621000010101010101010101010101010101016E +:10622000010101010101010101010101010101015E +:10623000010101010101010101010101010101014E +:10624000010101010101010101010101010101013E +:10625000010101010101010101010101010101012E +:10626000010101010101010101010101010101011E +:10627000010101010101010101010101010101010E +:1062800001010101010101010101010101010101FE +:1062900001010101010101010101010101010101EE +:1062A00001010101010101010101010101010101DE +:1062B00001010101010101010101010101010101CE +:1062C00001010101010101010101010101010101BE +:1062D00001010101010101010101010101010101AE +:1062E000010101010101010101010101010101019E +:1062F000010101010101010101010101010101018E +:10630000010101010101010101010101010101017D +:10631000010101010101010101010101010101016D +:10632000010101010101010101010101010101015D +:10633000010101010101010101010101010101014D +:10634000010101010101010101010101010101013D +:10635000010101010101010101010101010101012D +:10636000010101010101010101010101010101011D +:10637000010101010101010101010101010101010D +:1063800001010101010101010101010101010101FD +:1063900001010101010101010101010101010101ED +:1063A00001010101010101010101010101010101DD +:1063B00001010101010101010101010101010101CD +:1063C00001010101010101010101010101010101BD +:1063D00001010101010101010101010101010101AD +:1063E000010101010101010101010101010101019D +:1063F000010101010101010101010101010101018D +:10640000010101010101010101010101010101017C +:10641000010101010101010101010101010101016C +:10642000010101010101010101010101010101015C +:10643000010101010101010101010101010101014C +:10644000010101010101010101010101010101013C +:10645000010101010101010101010101010101012C +:10646000010101010101010101010101010101011C +:10647000010101010101010101010101010101010C +:1064800001010101010101010101010101010101FC +:1064900001010101010101010101010101010101EC +:1064A00001010101010101010101010101010101DC +:1064B00001010101010101010101010101010101CC +:1064C00001010101010101010101010101010101BC +:1064D00001010101010101010101010101010101AC +:1064E000010101010101010101010101010101019C +:1064F000010101010101010101010101010101018C +:10650000010101010101010101010101010101017B +:10651000010101010101010101010101010101016B +:10652000010101010101010101010101010101015B +:10653000010101010101010101010101010101014B +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010101010101010101FB +:1065900001010101010101010101010101010101EB +:1065A00001010101010101010101010101010101DB +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101018B +:10660000010101010101010101010101010101017A +:10661000010101010101010101010101010101016A +:10662000010101010101010101010101010101015A +:10663000010101010101010101010101010101014A +:10664000010101010101010101010101010101013A +:10665000010101010101010101010101010101012A +:10666000010101010101010101010101010101011A +:10667000010101010101010101010101010101010A +:1066800001010101010101010101010101010101FA +:1066900001010101010101010101010101010101EA +:1066A00001010101010101010101010101010101DA +:1066B00001010101010101010101010101010101CA +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101010101010101010101AA +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101018A +:106700000101010101010101010101010101010179 +:106710000101010101010101010101010101010169 +:106720000101010101010101010101010101010159 +:106730000101010101010101010101010101010149 +:106740000101010101010101010101010101010139 +:106750000101010101010101010101010101010129 +:106760000101010101010101010101010101010119 +:106770000101010101010101010101010101010109 +:1067800001010101010101010101010101010101F9 +:1067900001010101010101010101010101010101E9 +:1067A00001010101010101010101010101010101D9 +:1067B00001010101010101010101010101010101C9 +:1067C00001010101010101010101010101010101B9 +:1067D00001010101010101010101010101010101A9 +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010178 +:106810000101010101010101010101010101010168 +:106820000101010101010101010101010101010158 +:106830000101010101010101010101010101010148 +:106840000101010101010101010101010101010138 +:106850000101010101010101010101010101010128 +:106860000101010101010101010101010101010118 +:106870000101010101010101010101010101010108 +:1068800001010101010101010101010101010101F8 +:1068900001010101010101010101010101010101E8 +:1068A00001010101010101010101010101010101D8 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010147 +:106940000101010101010101010101010101010137 +:106950000101010101010101010101010101010127 +:106960000101010101010101010101010101010117 +:106970000101010101010101010101010101010107 +:1069800001010101010101010101010101010101F7 +:1069900001010101010101010101010101010101E7 +:1069A00001010101010101010101010101010101D7 +:1069B00001010101010101010101010101010101C7 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101010101010101010101A7 +:1069E0000101010101010101010101010101010197 +:1069F0000101010101010101010101010101010187 +:106A00000101010101010101010101010101010176 +:106A10000101010101010101010101010101010166 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000101010101010101010101010101010136 +:106A50000101010101010101010101010101010126 +:106A60000101010101010101010101010101010116 +:106A70000101010101010101010101010101010106 +:106A800001010101010101010101010101010101F6 +:106A900001010101010101010101010101010101E6 +:106AA00001010101010101010101010101010101D6 +:106AB00001010101010101010101010101010101C6 +:106AC00001010101010101010101010101010101B6 +:106AD00001010101010101010101010101010101A6 +:106AE0000101010101010101010101010101010196 +:106AF0000101010101010101010101010101010186 +:106B00000101010101010101010101010101010175 +:106B10000101010101010101010101010101010165 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B70000101010101010101010101010101010105 +:106B800001010101010101010101010101010101F5 +:106B900001010101010101010101010101010101E5 +:106BA00001010101010101010101010101010101D5 +:106BB00001010101010101010101010101010101C5 +:106BC00001010101010101010101010101010101B5 +:106BD00001010101010101010101010101010101A5 +:106BE0000101010101010101010101010101010195 +:106BF0000101010101010101010101010101010185 +:106C00000101010101010101010101010101010174 +:106C10000101010101010101010101010101010164 +:106C20000101010101010101010101010101010154 +:106C30000101010101010101010101010101010144 +:106C40000101010101010101010101010101010134 +:106C50000101010101010101010101010101010124 +:106C60000101010101010101010101010101010114 +:106C70000101010101010101010101010101010104 +:106C800001010101010101010101010101010101F4 +:106C900001010101010101010101010101010101E4 +:106CA00001010101010101010101010101010101D4 +:106CB00001010101010101010101010101010101C4 +:106CC00001010101010101010101010101010101B4 +:106CD00001010101010101010101010101010101A4 +:106CE0000101010101010101010101010101010194 +:106CF0000101010101010101010101010101010184 +:106D00000101010101010101010101010101010173 +:106D10000101010101010101010101010101010163 +:106D20000101010101010101010101010101010153 +:106D30000101010101010101010101010101010143 +:106D40000101010101010101010101010101010133 +:106D50000101010101010101010101010101010123 +:106D60000101010101010101010101010101010113 +:106D70000101010101010101010101010101010103 +:106D800001010101010101010101010101010101F3 +:106D900001010101010101010101010101010101E3 +:106DA00001010101010101010101010101010101D3 +:106DB00001010101010101010101010101010101C3 +:106DC00001010101010101010101010101010101B3 +:106DD00001010101010101010101010101010101A3 +:106DE0000101010101010101010101010101010193 +:106DF0000101010101010101010101010101010183 +:106E00000101010101010101010101010101010172 +:106E10000101010101010101010101010101010162 +:106E20000101010101010101010101010101010152 +:106E30000101010101010101010101010101010142 +:106E40000101010101010101010101010101010132 +:106E50000101010101010101010101010101010122 +:106E60000101010101010101010101010101010112 +:106E70000101010101010101010101010101010102 +:106E800001010101010101010101010101010101F2 +:106E900001010101010101010101010101010101E2 +:106EA00001010101010101010101010101010101D2 +:106EB00001010101010101010101010101010101C2 +:106EC00001010101010101010101010101010101B2 +:106ED00001010101010101010101010101010101A2 +:106EE0000101010101010101010101010101010192 +:106EF0000101010101010101010101010101010182 +:106F00000101010101010101010101010101010171 +:106F10000101010101010101010101010101010161 +:106F20000101010101010101010101010101010151 +:106F30000101010101010101010101010101010141 +:106F40000101010101010101010101010101010131 +:106F50000101010101010101010101010101010121 +:106F60000101010101010101010101010101010111 +:106F70000101010101010101010101010101010101 +:106F800001010101010101010101010101010101F1 +:106F900001010101010101010101010101010101E1 +:106FA00001010101010101010101010101010101D1 +:106FB00001010101010101010101010101010101C1 +:106FC00001010101010101010101010101010101B1 +:106FD00001010101010101010101010101010101A1 +:106FE0000101010101010101010101010101010191 +:106FF0000101010101010101010101010101010181 +:107000000101010101010101010101010101010170 +:107010000101010101010101010101010101010160 +:107020000101010101010101010101010101010150 +:107030000101010101010101010101010101010140 +:107040000101010101010101010101010101010130 +:107050000101010101010101010101010101010120 +:107060000101010101010101010101010101010110 +:107070000101010101010101010101010101010100 +:1070800001010101010101010101010101010101F0 +:1070900001010101010101010101010101010101E0 +:1070A00001010101010101010101010101010101D0 +:1070B00001010101010101010101010101010101C0 +:1070C00001010101010101010101010101010101B0 +:1070D00001010101010101010101010101010101A0 +:1070E0000101010101010101010101010101010190 +:1070F0000101010101010101010101010101010180 +:10710000010101010101010101010101010101016F +:10711000010101010101010101010101010101015F +:10712000010101010101010101010101010101014F +:10713000010101010101010101010101010101013F +:10714000010101010101010101010101010101012F +:10715000010101010101010101010101010101011F +:10716000010101010101010101010101010101010F +:1071700001010101010101010101010101010101FF +:1071800001010101010101010101010101010101EF +:1071900001010101010101010101010101010101DF +:1071A00001010101010101010101010101010101CF +:1071B00001010101010101010101010101010101BF +:1071C00001010101010101010101010101010101AF +:1071D000010101010101010101010101010101019F +:1071E000010101010101010101010101010101018F +:1071F000010101010101010101010101010101017F +:10720000010101010101010101010101010101016E +:10721000010101010101010101010101010101015E +:10722000010101010101010101010101010101014E +:10723000010101010101010101010101010101013E +:10724000010101010101010101010101010101012E +:10725000010101010101010101010101010101011E +:10726000010101010101010101010101010101010E +:1072700001010101010101010101010101010101FE +:1072800001010101010101010101010101010101EE +:1072900001010101010101010101010101010101DE +:1072A00001010101010101010101010101010101CE +:1072B00001010101010101010101010101010101BE +:1072C00001010101010101010101010101010101AE +:1072D000010101010101010101010101010101019E +:1072E000010101010101010101010101010101018E +:1072F000010101010101010101010101010101017E +:10730000010101010101010101010101010101016D +:10731000010101010101010101010101010101015D +:10732000010101010101010101010101010101014D +:10733000010101010101010101010101010101013D +:10734000010101010101010101010101010101012D +:10735000010101010101010101010101010101011D +:10736000010101010101010101010101010101010D +:1073700001010101010101010101010101010101FD +:1073800001010101010101010101010101010101ED +:1073900001010101010101010101010101010101DD +:1073A00001010101010101010101010101010101CD +:1073B00001010101010101010101010101010101BD +:1073C00001010101010101010101010101010101AD +:1073D000010101010101010101010101010101019D +:1073E000010101010101010101010101010101018D +:1073F000010101010101010101010101010101017D +:10740000010101010101010101010101010101016C +:10741000010101010101010101010101010101015C +:10742000010101010101010101010101010101014C +:107430000101010101010100000000000000000045 +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000000BA +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000000B9 +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000002020202020202020236 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202020286 +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020202020285 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020202B4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202020202020202020284 +:107CE0000202020202020202020202020202020274 +:107CF0000202020202020202020202020202020264 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020202020202020283 +:107DE0000202020202020202020202020202020273 +:107DF0000202020202020202020202020202020263 +:107E00000202020202020202020202020202020252 +:107E10000202020202020202020202020202020242 +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020202C2 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020202020202020202020282 +:107EE0000202020202020202020202020202020272 +:107EF0000202020202020202020202020202020262 +:107F00000202020202020202020202020202020251 +:107F10000202020202020202020202020202020241 +:107F20000202020202020202020202020202020231 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020202C1 +:107FA00002020202020202020202020202020202B1 +:107FB00002020202020202020202020202020202A1 +:107FC0000202020202020202020202020202020291 +:107FD0000202020202020202020202020202020281 +:107FE0000202020202020202020202020202020271 +:107FF0000202020202020202020202020202020261 +:108000000202020202020202020202020202020250 +:108010000202020202020202020202020202020240 +:108020000202020202020202020202020202020230 +:108030000202020202020202020202020202020220 +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202020202020202020202C0 +:1080A00002020202020202020202020202020202B0 +:1080B00002020202020202020202020202020202A0 +:1080C0000202020202020202020202020202020290 +:1080D0000202020202020202020202020202020280 +:1080E0000202020202020202020202020202020270 +:1080F0000202020202020202020202020202020260 +:10810000020202020202020202020202020202024F +:10811000020202020202020202020202020202023F +:10812000020202020202020202020202020202022F +:10813000020202020202020202020202020202021F +:10814000020202020202020202020202020202020F +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202020202020202020202BF +:1081A00002020202020202020202020202020202AF +:1081B000020202020202020202020202020202029F +:1081C000020202020202020202020202020202028F +:1081D000020202020202020202020202020202027F +:1081E000020202020202020202020202020202026F +:1081F000020202020202020202020202020202025F +:10820000020202020202020202020202020202024E +:10821000020202020202020202020202020202023E +:10822000020202020202020202020202020202022E +:10823000020202020202020202020202020202021E +:10824000020202020202020202020202020202020E +:1082500002020202020202020202020202020202FE +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202020202020202020202BE +:1082A00002020202020202020202020202020202AE +:1082B000020202020202020202020202020202029E +:1082C000020202020202020202020202020202028E +:1082D000020202020202020202020202020202027E +:1082E000020202020202020202020202020202026E +:1082F000020202020202020202020202020202025E +:10830000020202020202020202020202020202024D +:10831000020202020202020202020202020202023D +:10832000020202020202020202020202020202022D +:10833000020202020202020202020202020202021D +:10834000020202020202020202020202020202020D +:1083500002020202020202020202020202020202FD +:1083600002020202020202020202020202020202ED +:1083700002020202020202020202020202020202DD +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020202BD +:1083A00002020202020202020202020202020202AD +:1083B000020202020202020202020202020202029D +:1083C000020202020202020202020202020202028D +:1083D000020202020202020202020202020202027D +:1083E000020202020202020202020202020202026D +:1083F000020202020202020202020202020202025D +:10840000020202020202020202020202020202024C +:10841000020202020202020202020202020202023C +:10842000020202020202020202020202020202022C +:10843000020202020202020202020202020202021C +:10844000020202020202020202020202020202020C +:1084500002020202020202020202020202020202FC +:1084600002020202020202020202020202020202EC +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020202BC +:1084A00002020202020202020202020202020202AC +:1084B000020202020202020202020202020202029C +:1084C000020202020202020202020202020202028C +:1084D000020202020202020202020202020202027C +:1084E000020202020202020202020202020202026C +:1084F000020202020202020202020202020202025C +:10850000020202020202020202020202020202024B +:10851000020202020202020202020202020202023B +:10852000020202020202020202020202020202022B +:10853000020202020202020202020202020202021B +:10854000020202020202020202020202020202020B +:1085500002020202020202020202020202020202FB +:1085600002020202020202020202020202020202EB +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020202AB +:1085B000020202020202020202020202020202029B +:1085C000020202020202020202020202020202028B +:1085D000020202020202020202020202020202027B +:1085E000020202020202020202020202020202026B +:1085F000020202020202020202020202020202025B +:10860000020202020202020202020202020202024A +:10861000020202020202020202020202020202023A +:10862000020202020202020202020202020202022A +:10863000020202020202020202020202020202021A +:10864000020202020202020202020202020202020A +:1086500002020202020202020202020202020202FA +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202020202DA +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020202AA +:1086B000020202020202020202020202020202029A +:1086C000020202020202020202020202020202028A +:1086D000020202020202020202020202020202027A +:1086E000020202020202020202020202020202026A +:1086F000020202020202020202020202020202025A +:108700000202020202020202020202020202020249 +:108710000202020202020202020202020202020239 +:108720000202020202020202020202020202020229 +:108730000202020202020202020202020202020219 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020202A9 +:1087B0000202020202020202020202020202020299 +:1087C0000202020202020202020202020202020289 +:1087D0000202020202020202020202020202020279 +:1087E0000202020202020202020202020202020269 +:1087F0000202020202020202020202020202020259 +:108800000202020202020202020202020202020248 +:108810000202020202020202020202020202020238 +:108820000202020202020202020202020202020228 +:108830000202020202020202020202020202020218 +:108840000202020202020202020202020202020208 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202020202020202020202D8 +:1088800002020202020202020202020202020202C8 +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202020202A8 +:1088B0000202020202020202020202020202020298 +:1088C0000202020202020202020202020202020288 +:1088D0000202020202020202020202020202020278 +:1088E0000202020202020202020202020202020268 +:1088F0000202020202020202020202020202020258 +:108900000202020202020202020202020202020247 +:108910000202020202020202020202020202020237 +:108920000202020202020202020202020202020227 +:108930000202020202020202020202020202020217 +:108940000202020202020202020202020202020207 +:1089500002020202020202020202020202020202F7 +:1089600002020202020202020202020202020202E7 +:1089700002020202020202020202020202020202D7 +:1089800002020202020202020202020202020202C7 +:1089900002020202020202020202020202020202B7 +:1089A00002020202020202020202020202020202A7 +:1089B0000202020202020202020202020202020297 +:1089C0000202020202020202020202020202020287 +:1089D0000202020202020202020202020202020277 +:1089E0000202020202020202020202020202020267 +:1089F0000202020202020202020202020202020257 +:108A00000202020202020202020202020202020246 +:108A10000202020202020202020202020202020236 +:108A20000202020202020202020202020202020226 +:108A30000202020202020202020202020202020216 +:108A40000202020202020202020202020202020206 +:108A500002020202020202020202020202020202F6 +:108A600002020202020202020202020202020202E6 +:108A700002020202020202020202020202020202D6 +:108A800002020202020202020202020202020202C6 +:108A900002020202020202020202020202020202B6 +:108AA00002020202020202020202020202020202A6 +:108AB0000202020202020202020202020202020296 +:108AC0000202020202020202020202020202020286 +:108AD0000202020202020202020202020202020276 +:108AE0000202020202020202020202020202020266 +:108AF0000202020202020202020202020202020256 +:108B00000202020202020202020202020202020245 +:108B10000202020202020202020202020202020235 +:108B20000202020202020202020202020202020225 +:108B30000202020202020202020202020202020215 +:108B40000202020202020202020202020202020205 +:108B500002020202020202020202020202020202F5 +:108B600002020202020202020202020202020202E5 +:108B700002020202020202020202020202020202D5 +:108B800002020202020202020202020202020202C5 +:108B900002020202020202020202020202020202B5 +:108BA00002020202020202020202020202020202A5 +:108BB0000202020202020202020202020202020295 +:108BC0000202020202020202020202020202020285 +:108BD0000202020202020202020202020202020275 +:108BE0000202020202020202020202020202020265 +:108BF0000202020202020202020202020202020255 +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020200000000000000000026 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F300000000000000000690000000000000001C7 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101000E +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000217 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000202020202020202020202020202020239 +:10A800000202020202020202020202020202020228 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020202A8 +:10A890000202020202020202020202020202020298 +:10A8A0000202020202020202020202020202020288 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202020202020202020202020202EA +:10B6400002020202020202020202020202020202DA +:10B6500002020202020202020202020202020202CA +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020202020202020202020202028A +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C000020202020202020202020202020202025A +:10B6D000020202020202020202020202020202024A +:10B6E000020202020202020202020202020202023A +:10B6F000020202020202020202020202020202022A +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020200E7 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D000000000000000000000000000000000005E +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000000001D +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000001FA +:10C5400001010101010101010101010101010101DB +:10C5500001010101010101010101010101010101CB +:10C5600001010101010101010101010101010101BB +:10C5700001010101010101010101010101010101AB +:10C58000010101010101010101010101010101019B +:10C59000010101010101010101010101010101018B +:10C5A000010101010101010101010101010101017B +:10C5B000010101010101010101010101010101016B +:10C5C000010101010101010101010101010101015B +:10C5D000010101010101010101010101010101014B +:10C5E000010101010101010101010101010101013B +:10C5F000010101010101010101010101010101012B +:10C60000010101010101010101010101010101011A +:10C61000010101010101010101010101010101010A +:10C6200001010101010101010101010101010101FA +:10C6300001010101010101010101010101010101EA +:10C6400001010101010101010101010101010101DA +:10C6500001010101010101010101010101010101CA +:10C6600001010101010101010101010101010101BA +:10C6700001010101010101010101010101010101AA +:10C68000010101010101010101010101010101019A +:10C69000010101010101010101010101010101018A +:10C6A000010101010101010101010101010101017A +:10C6B000010101010101010101010101010101016A +:10C6C000010101010101010101010101010101015A +:10C6D000010101010101010101010101010101014A +:10C6E000010101010101010101010101010101013A +:10C6F000010101010101010101010101010101012A +:10C700000101010101010101010101010101010119 +:10C710000101010101010101010101010101010109 +:10C7200001010101010101010101010101010101F9 +:10C7300001010101010101010101010101010101E9 +:10C7400001010101010101010101010101010101D9 +:10C7500001010101010101010101010101010101C9 +:10C7600001010101010101010101010101010101B9 +:10C7700001010101010101010101010101010101A9 +:10C780000101010101010101010101010101010199 +:10C790000101010101010101010101010101010189 +:10C7A0000101010101010101010101010101010179 +:10C7B0000101010101010101010101010101010169 +:10C7C0000101010101010101010101010101010159 +:10C7D0000101010101010101010101010101010149 +:10C7E0000101010101010101010101010101010139 +:10C7F0000101010101010101010101010101010129 +:10C800000101010101010101010101010101010118 +:10C810000101010101010101010101010101010108 +:10C8200001010101010101010101010101010101F8 +:10C8300001010101010101010101010101010101E8 +:10C8400001010101010101010101010101010101D8 +:10C8500001010101010101010101010101010101C8 +:10C8600001010101010101010101010101010101B8 +:10C8700001010101010101010101010101010101A8 +:10C880000101010101010101010101010101010198 +:10C890000101010101010101010101010101010188 +:10C8A0000101010101010101010101010101010178 +:10C8B0000101010101010101010101010101010168 +:10C8C0000101010101010101010101010101010158 +:10C8D0000101010101010101010101010101010148 +:10C8E0000101010101010101010101010101010138 +:10C8F0000101010101010101010101010101010128 +:10C900000101010101010101010101010101010117 +:10C910000101010101010101010101010101010107 +:10C9200001010101010101010101010101010101F7 +:10C9300001010101010101010101010101010101E7 +:10C9400001010101010101010101010101010101D7 +:10C9500001010101010101010101010101010101C7 +:10C9600001010101010101010101010101010101B7 +:10C9700001010101010101010101010101010101A7 +:10C980000101010101010101010101010101010197 +:10C990000101010101010101010101010101010187 +:10C9A0000101010101010101010101010101010177 +:10C9B0000101010101010101010101010101010167 +:10C9C0000101010101010101010101010101010157 +:10C9D0000101010101010101010101010101010147 +:10C9E0000101010101010101010101010101010137 +:10C9F0000101010101010101010101010101010127 +:10CA00000101010101010101010101010101010116 +:10CA10000101010101010101010101010101010106 +:10CA200001010101010101010101010101010101F6 +:10CA300001010101010101010101010101010101E6 +:10CA400001010101010101010101010101010101D6 +:10CA500001010101010101010101010101010101C6 +:10CA600001010101010101010101010101010101B6 +:10CA700001010101010101010101010101010101A6 +:10CA80000101010101010101010101010101010196 +:10CA90000101010101010101010101010101010186 +:10CAA0000101010101010101010101010101010176 +:10CAB0000101010101010101010101010101010166 +:10CAC0000101010101010101010101010101010156 +:10CAD0000101010101010101010101010101010146 +:10CAE0000101010101010101010101010101010136 +:10CAF0000101010101010101010101010101010126 +:10CB00000101010101010101010101010101010115 +:10CB10000101010101010101010101010101010105 +:10CB200001010101010101010101010101010101F5 +:10CB300001010101010101010101010101010101E5 +:10CB400001010101010101010101010101010101D5 +:10CB500001010101010101010101010101010101C5 +:10CB600001010101010101010101010101010101B5 +:10CB700001010101010101010101010101010101A5 +:10CB80000101010101010101010101010101010195 +:10CB90000101010101010101010101010101010185 +:10CBA0000101010101010101010101010101010175 +:10CBB0000101010101010101010101010101010165 +:10CBC0000101010101010101010101010101010155 +:10CBD0000101010101010101010101010101010145 +:10CBE0000101010101010101010101010101010135 +:10CBF0000101010101010101010101010101010125 +:10CC00000101010101010101010101010101010114 +:10CC10000101010101010101010101010101010104 +:10CC200001010101010101010101010101010101F4 +:10CC300001010101010101010101010101010101E4 +:10CC400001010101010101010101010101010101D4 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010101A4 +:10CC80000101010101010101010101010101010194 +:10CC90000101010101010101010101010101010184 +:10CCA0000101010101010101010101010101010174 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010101A3 +:10CD80000101010101010101010101010101010193 +:10CD90000101010101010101010101010101010183 +:10CDA0000101010101010101010101010101010173 +:10CDB0000101010101010101010101010101010163 +:10CDC0000101010101010101010101010101010153 +:10CDD0000101010101010101010101010101010143 +:10CDE0000101010101010101010101010101010133 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010101A2 +:10CE80000101010101010101010101010101010192 +:10CE90000101010101010101010101010101010182 +:10CEA0000101010101010101010101010101010172 +:10CEB0000101010101010101010101010101010162 +:10CEC0000101010101010101010101010101010152 +:10CED0000101010101010101010101010101010142 +:10CEE0000101010101010101010101010101010132 +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400001010101010101010101010101010101D1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700001010101010101010101010101010101A1 +:10CF80000101010101010101010101010101010191 +:10CF90000101010101010101010101010101010181 +:10CFA0000101010101010101010101010101010171 +:10CFB0000101010101010101010101010101010161 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010141 +:10CFE0000101010101010101010101010101010131 +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010101010101010101010110 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010101010101010101010101010101C0 +:10D0600001010101010101010101010101010101B0 +:10D0700001010101010101010101010101010101A0 +:10D080000101010101010101010101010101010190 +:10D090000101010101010101010101010101010180 +:10D0A0000101010101010101010101010101010170 +:10D0B0000101010101010101010101010101010160 +:10D0C0000101010101010101010101010101010150 +:10D0D0000101010101010101010101010101010140 +:10D0E0000101010101010101010101010101010130 +:10D0F0000101010101010101010101010101010120 +:10D10000010101010101010101010101010101010F +:10D1100001010101010101010101010101010101FF +:10D1200001010101010101010101010101010101EF +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010101010101AE +:10D27000010101010101010101010101010101019E +:10D28000010101010101010101010101010101018E +:10D29000010101010101010101010101010101017E +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010101FC +:10D4200001010101010101010101010101010101EC +:10D4300001010101010101010101010101010101DC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101017C +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010101CA +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010101AA +:10D67000010101010101010101010101010101019A +:10D68000010101010101010101010101010101018A +:10D69000010101010101010101010101010101017A +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000010101010101010101010101010101014A +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010101A9 +:10D770000101010101010101010101010101010199 +:10D780000101010101010101010101010101010189 +:10D790000101010101010101010101010101010179 +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000101010101010101010101010101010149 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010100D8 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000002E1 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB0000202020202020202020202020202020243 +:10DDC0000202020202020202020202020202020233 +:10DDD0000202020202020202020202020202020223 +:10DDE0000202020202020202020202020202020213 +:10DDF0000202020202020202020202020202020203 +:10DE000002020202020202020202020202020202F2 +:10DE100002020202020202020202020202020202E2 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA0000202020202020202020202020202020252 +:10DEB0000202020202020202020202020202020242 +:10DEC0000202020202020202020202020202020232 +:10DED0000202020202020202020202020202020222 +:10DEE0000202020202020202020202020202020212 +:10DEF0000202020202020202020202020202020202 +:10DF000002020202020202020202020202020202F1 +:10DF100002020202020202020202020202020202E1 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202020202020231 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020202020202020202020211 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020202020202020202020250 +:10E0B0000202020202020202020202020202020240 +:10E0C0000202020202020202020202020202020230 +:10E0D0000202020202020202020202020202020220 +:10E0E0000202020202020202020202020202020210 +:10E0F0000202020202020202020202020202020200 +:10E1000002020202020202020202020202020202EF +:10E1100002020202020202020202020202020202DF +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A000020202020202020202020202020202024F +:10E1B000020202020202020202020202020202023F +:10E1C000020202020202020202020202020202022F +:10E1D000020202020202020202020202020202021F +:10E1E000020202020202020202020202020202020F +:10E1F00002020202020202020202020202020202FF +:10E2000002020202020202020202020202020202EE +:10E2100002020202020202020202020202020202DE +:10E2200002020202020202020202020202020202CE +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E28000020202020202020202020202020202026E +:10E29000020202020202020202020202020202025E +:10E2A000020202020202020202020202020202024E +:10E2B000020202020202020202020202020202023E +:10E2C000020202020202020202020202020202022E +:10E2D000020202020202020202020202020202021E +:10E2E000020202020202020202020202020202020E +:10E2F00002020202020202020202020202020202FE +:10E3000002020202020202020202020202020202ED +:10E3100002020202020202020202020202020202DD +:10E3200002020202020202020202020202020202CD +:10E3300002020202020202020202020202020202BD +:10E3400002020202020202020202020202020202AD +:10E35000020202020202020202020202020202029D +:10E36000020202020202020202020202020202028D +:10E37000020202020202020202020202020202027D +:10E38000020202020202020202020202020202026D +:10E39000020202020202020202020202020202025D +:10E3A000020202020202020202020202020202024D +:10E3B000020202020202020202020202020202023D +:10E3C000020202020202020202020202020202022D +:10E3D000020202020202020202020202020202021D +:10E3E000020202020202020202020202020202020D +:10E3F00002020202020202020202020202020202FD +:10E4000002020202020202020202020202020202EC +:10E4100002020202020202020202020202020202DC +:10E4200002020202020202020202020202020202CC +:10E4300002020202020202020202020202020202BC +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A000020202020202020202020202020202024C +:10E4B000020202020202020202020202020202023C +:10E4C000020202020202020202020202020202022C +:10E4D000020202020202020202020202020202021C +:10E4E000020202020202020202020202020202020C +:10E4F00002020202020202020202020202020202FC +:10E5000002020202020202020202020202020202EB +:10E5100002020202020202020202020202020202DB +:10E5200002020202020202020202020202020202CB +:10E5300002020202020202020202020202020202BB +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A000020202020202020202020202020202024B +:10E5B000020202020202020202020202020202023B +:10E5C000020202020202020202020202020202022B +:10E5D000020202020202020202020202020202021B +:10E5E000020202020202020202020202020202020B +:10E5F00002020202020202020202020202020202FB +:10E6000002020202020202020202020202020202EA +:10E6100002020202020202020202020202020202DA +:10E6200002020202020202020202020202020202CA +:10E6300002020202020202020202020202020202BA +:10E6400002020202020202020202020202020202AA +:10E65000020202020202020202020202020202029A +:10E66000020202020202020202020202020202028A +:10E67000020202020202020202020202020202027A +:10E68000020202020202020202020202020202026A +:10E69000020202020202020202020202020202025A +:10E6A000020202020202020202020202020202024A +:10E6B000020202020202020202020202020202023A +:10E6C000020202020202020202020202020202022A +:10E6D000020202020202020202020202020202021A +:10E6E000020202020202020202020202020202020A +:10E6F00002020202020202020202020202020202FA +:10E7000002020202020202020202020202020202E9 +:10E7100002020202020202020202020202020202D9 +:10E7200002020202020202020202020202020202C9 +:10E7300002020202020202020202020202020202B9 +:10E7400002020202020202020202020202020202A9 +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000202020202020202020202020202020229 +:10E7D0000202020202020202020202020202020219 +:10E7E0000202020202020202020202020202020209 +:10E7F00002020202020202020202020202020202F9 +:10E8000002020202020202020202020202020202E8 +:10E8100002020202020202020202020202020202D8 +:10E8200002020202020202020202020202020202C8 +:10E8300002020202020202020202020202020202B8 +:10E8400002020202020202020202020202020202A8 +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C0000202020202020202020202020202020228 +:10E8D0000202020202020202020202020202020218 +:10E8E0000202020202020202020202020202020208 +:10E8F00002020202020202020202020202020202F8 +:10E9000002020202020202020202020202020202E7 +:10E9100002020202020202020202020202020202D7 +:10E9200002020202020202020202020202020202C7 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202020202020202020202020202F7 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020202020202020202020202020202C6 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020203 +:10EDF00002020202020202020202020202020202F3 +:10EE000002020202020202020202020202020202E2 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202020202020202020202F2 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020202020202020202020202A1 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020202020202020221 +:10EFD0000202020202020202020202020202020211 +:10EFE0000202020202020202020202020202020201 +:10EFF00002020202020202020202020202020202F1 +:10F0000002020202020202020202020202020202E0 +:10F0100002020202020202020202020202020202D0 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020202020202020202020202B0 +:10F0400002020202020202020202020202020202A0 +:10F050000202020202020202020202020202020290 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020202020202020202020230 +:10F0C0000202020202020202020202020202020220 +:10F0D0000202020202020202020202020202020210 +:10F0E0000202020202020202020202020202020200 +:10F0F00002020202020202020202020202020202F0 +:10F1000002020202020202020202020202020202DF +:10F1100002020202020202020202020202020202CF +:10F1200002020202020202020202020202020202BF +:10F1300002020202020202020202020202020200B1 +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F830000000000000000000000000000000007355 +:10F8400000000000000000010101010101010101AF +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101010101010101010141 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD0000101010101010101010101010101010111 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:0200000270008C +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010198 +:100850000101010101010101010101010101010188 +:100860000101010101010101010101010101010178 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010118 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C4000010101010101010000000000000000009D +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000000E3 +:100D100000000000000000000000000000000000D3 +:100D200000000000000000000000000000000000C3 +:100D300000000000000000000000000000000000B3 +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000000000000000000000073 +:100D80000000000000000000000000000000000063 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000000000000000000023 +:100DD0000000000000000000000000000000000013 +:100DE0000000000000000000000000000000000003 +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:10104000000000000000000202020202020202028E +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A000020202020202020202020202020202021A +:1016B000020202020202020202020202020202020A +:1016C00002020202020202020202020202020202FA +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202020202020202020202DA +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A0000202020202020202020202020202020219 +:1017B0000202020202020202020202020202020209 +:1017C00002020202020202020202020202020202F9 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202020202020202020202D9 +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A0000202020202020202020202020202020218 +:1018B0000202020202020202020202020202020208 +:1018C00002020202020202020202020202020202F8 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202020202020202020202D8 +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020202A7 +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020202020202020202020217 +:1019B0000202020202020202020202020202020207 +:1019C00002020202020202020202020202020202F7 +:1019D00002020202020202020202020202020202E7 +:1019E00002020202020202020202020202020202D7 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000202020202020202020202020202020216 +:101AB0000202020202020202020202020202020206 +:101AC00002020202020202020202020202020202F6 +:101AD00002020202020202020202020202020202E6 +:101AE00002020202020202020202020202020202D6 +:101AF00002020202020202020202020202020202C6 +:101B000002020202020202020202020202020202B5 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA0000202020202020202020202020202020215 +:101BB0000202020202020202020202020202020205 +:101BC00002020202020202020202020202020202F5 +:101BD00002020202020202020202020202020202E5 +:101BE00002020202020202020202020202020202D5 +:101BF00002020202020202020202020202020202C5 +:101C000002020202020202020202020202020202B4 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA0000202020202020202020202020202020214 +:101CB0000202020202020202020202020202020204 +:101CC00002020202020202020202020202020202F4 +:101CD00002020202020202020202020202020202E4 +:101CE00002020202020202020202020202020202D4 +:101CF00002020202020202020202020202020202C4 +:101D000002020202020202020202020202020202B3 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020202020203 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020202D3 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202020202 +:101EC00002020202020202020202020202020202F2 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020202D2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020202D0 +:1020F00002020202020202020202020202020202C0 +:1021000002020202020202020202020202020202AF +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020202020202020202020F +:1021B00002020202020202020202020202020202FF +:1021C00002020202020202020202020202020202EF +:1021D00002020202020202020202020202020202DF +:1021E00002020202020202020202020202020202CF +:1021F00002020202020202020202020202020202BF +:1022000002020202020202020202020202020202AE +:10221000020202020202020202020202020202029E +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A000020202020202020202020202020202020E +:1022B00002020202020202020202020202020202FE +:1022C00002020202020202020202020202020202EE +:1022D00002020202020202020202020202020202DE +:1022E00002020202020202020202020202020202CE +:1022F00002020202020202020202020202020202BE +:1023000002020202020202020202020202020202AD +:10231000020202020202020202020202020202029D +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A000020202020202020202020202020202020D +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020202020202ED +:1023D00002020202020202020202020202020202DD +:1023E00002020202020202020202020202020202CD +:1023F00002020202020202020202020202020202BD +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020000000000000000007E +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000000E8 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000000E6 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000004 +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000000E1 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000000FF +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000000FE +:1032D00000000000000000000000000000000000EE +:1032E00000000000000000000000000000000000DE +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:103340000000000000000001010101010101010174 +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000010101010101010101010101010101011D +:1033A000010101010101010101010101010101010D +:1033B00001010101010101010101010101010101FD +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000010101010101010101010101010101017C +:10344000010101010101010101010101010101016C +:10345000010101010101010101010101010101015C +:10346000010101010101010101010101010101014C +:10347000010101010101010101010101010101013C +:10348000010101010101010101010101010101012C +:10349000010101010101010101010101010101011C +:1034A000010101010101010101010101010101010C +:1034B00001010101010101010101010101010101FC +:1034C00001010101010101010101010101010101EC +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101014A +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A000010101010101010101010101010101010A +:1036B00001010101010101010101010101010101FA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010101F8 +:1038C00001010101010101010101010101010101E8 +:1038D00001010101010101010101010101010101D8 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010101010101010101010167 +:103950000101010101010101010101010101010157 +:103960000101010101010101010101010101010147 +:103970000101010101010101010101010101010137 +:103980000101010101010101010101010101010127 +:103990000101010101010101010101010101010117 +:1039A0000101010101010101010101010101010107 +:1039B00001010101010101010101010101010101F7 +:1039C00001010101010101010101010101010101E7 +:1039D00001010101010101010101010101010101D7 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000101010101010101010101010101010176 +:103A40000101010101010101010101010101010166 +:103A50000101010101010101010101010101010156 +:103A60000101010101010101010101010101010146 +:103A70000101010101010101010101010101010136 +:103A80000101010101010101010101010101010126 +:103A90000101010101010101010101010101010116 +:103AA0000101010101010101010101010101010106 +:103AB00001010101010101010101010101010101F6 +:103AC00001010101010101010101010101010101E6 +:103AD00001010101010101010101010101010101D6 +:103AE00001010101010101010101010101010101C6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000101010101010101010101010101010135 +:103B80000101010101010101010101010101010125 +:103B90000101010101010101010101010101010115 +:103BA0000101010101010101010101010101010105 +:103BB00001010101010101010101010101010101F5 +:103BC00001010101010101010101010101010101E5 +:103BD00001010101010101010101010101010101D5 +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C60000101010101010101010101010101010144 +:103C70000101010101010101010101010101010134 +:103C80000101010101010101010101010101010124 +:103C90000101010101010101010101010101010114 +:103CA0000101010101010101010101010101010104 +:103CB00001010101010101010101010101010101F4 +:103CC00001010101010101010101010101010101E4 +:103CD00001010101010101010101010101010101D4 +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010101B4 +:103D000001010101010101010101010101010101A3 +:103D10000101010101010101010101010101010193 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000101010101010101010101010101010103 +:103DB00001010101010101010101010101010101F3 +:103DC00001010101010101010101010101010101E3 +:103DD00001010101010101010101010101010101D3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101010101010101010101B3 +:103E000001010101010101010101010101010101A2 +:103E10000101010101010101010101010101010192 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010172 +:103E40000101010101010101010101010101010162 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000101010101010101010101010101010112 +:103EA0000101010101010101010101010101010102 +:103EB00001010101010101010101010101010101F2 +:103EC00001010101010101010101010101010101E2 +:103ED00001010101010101010101010101010101D2 +:103EE00001010101010101010101010101010101C2 +:103EF00001010101010101010101010101010101B2 +:103F000001010101010101010101010101010101A1 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010171 +:103F40000101010101010101010101010101010161 +:103F50000101010101010101010101010101010151 +:103F60000101010101010101010101010101010141 +:103F70000101010101010101010101010101010131 +:103F80000101010101010101010101010101010121 +:103F90000101010101010101010101010101010111 +:103FA0000101010101010101010101010101010101 +:103FB00001010101010101010101010101010101F1 +:103FC00001010101010101010101010101010101E1 +:103FD00001010101010101010101010101010101D1 +:103FE00001010101010101010101010101010101C1 +:103FF00001010101010101010101010101010101B1 +:1040000001010101010101010101010101010101A0 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:104030000101010101010101010101010101010170 +:104040000101010101010101010101010101010160 +:104050000101010101010101010101010101010150 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:104080000101010101010101010101010101010120 +:104090000101010101010101010101010101010110 +:1040A0000101010101010101010101010101010100 +:1040B00001010101010101010101010101010101F0 +:1040C00001010101010101010101010101010101E0 +:1040D00001010101010101010101010101010101D0 +:1040E00001010101010101010101010101010101C0 +:1040F00001010101010101010101010101010101B0 +:10410000010101010101010101010101010101019F +:10411000010101010101010101010101010101018F +:10412000010101010101010101010101010101017F +:10413000010101010101010101010101010101016F +:10414000010101010101010101010101010101015F +:10415000010101010101010101010101010101014F +:10416000010101010101010101010101010101013F +:10417000010101010101010101010101010101012F +:10418000010101010101010101010101010101011F +:10419000010101010101010101010101010101010F +:1041A00001010101010101010101010101010101FF +:1041B00001010101010101010101010101010101EF +:1041C00001010101010101010101010101010101DF +:1041D00001010101010101010101010101010101CF +:1041E00001010101010101010101010101010101BF +:1041F00001010101010101010101010101010101AF +:10420000010101010101010101010101010101019E +:10421000010101010101010101010101010101018E +:10422000010101010101010101010101010101017E +:10423000010101010101010101010101010101016E +:10424000010101010101010101010101010101015E +:10425000010101010101010101010101010101014E +:10426000010101010101010101010101010101013E +:10427000010101010101010101010101010101012E +:10428000010101010101010101010101010101011E +:10429000010101010101010101010101010101010E +:1042A00001010101010101010101010101010101FE +:1042B00001010101010101010101010101010101EE +:1042C00001010101010101010101010101010101DE +:1042D00001010101010101010101010101010101CE +:1042E00001010101010101010101010101010101BE +:1042F00001010101010101010101010101010101AE +:10430000010101010101010101010101010101019D +:10431000010101010101010101010101010101018D +:10432000010101010101010101010101010101017D +:10433000010101010101010101010101010101016D +:10434000010101010101010101010101010101015D +:10435000010101010101010101010101010101014D +:10436000010101010101010101010101010101013D +:10437000010101010101010101010101010101012D +:10438000010101010101010101010101010101011D +:10439000010101010101010101010101010101010D +:1043A00001010101010101010101010101010101FD +:1043B00001010101010101010101010101010101ED +:1043C00001010101010101010101010101010101DD +:1043D00001010101010101010101010101010101CD +:1043E00001010101010101010101010101010101BD +:1043F00001010101010101010101010101010101AD +:10440000010101010101010101010101010101019C +:10441000010101010101010101010101010101018C +:10442000010101010101010101010101010101017C +:10443000010101010101010101010101010101016C +:10444000010101010101010101010101010101015C +:10445000010101010101010101010101010101014C +:10446000010101010101010101010101010101013C +:10447000010101010101010101010101010101012C +:10448000010101010101010101010101010101011C +:10449000010101010101010101010101010101010C +:1044A00001010101010101010101010101010101FC +:1044B00001010101010101010101010101010101EC +:1044C00001010101010101010101010101010101DC +:1044D00001010101010101010101010101010101CC +:1044E00001010101010101010101010101010101BC +:1044F00001010101010101010101010101010101AC +:10450000010101010101010101010101010101019B +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101011B +:10459000010101010101010101010101010101010B +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101010101010101010101EB +:1045C00001010101010101010101010101010101DB +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:10468000010101010101010101010101010101011A +:10469000010101010101010101010101010101010A +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010101EA +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010100000000000000000062 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000002020202020202020253 +:104B50000202020202020202020202020202020235 +:104B60000202020202020202020202020202020225 +:104B70000202020202020202020202020202020215 +:104B80000202020202020202020202020202020205 +:104B900002020202020202020202020202020202F5 +:104BA00002020202020202020202020202020202E5 +:104BB00002020202020202020202020202020202D5 +:104BC00002020202020202020202020202020202C5 +:104BD00002020202020202020202020202020202B5 +:104BE00002020202020202020202020202020202A5 +:104BF0000202020202020202020202020202020295 +:104C00000202020202020202020202020202020284 +:104C10000202020202020202020202020202020274 +:104C20000202020202020202020202020202020264 +:104C30000202020202020202020202020202020254 +:104C40000202020202020202020202020202020244 +:104C50000202020202020202020202020202020234 +:104C60000202020202020202020202020202020224 +:104C70000202020202020202020202020202020214 +:104C80000202020202020202020202020202020204 +:104C900002020202020202020202020202020202F4 +:104CA00002020202020202020202020202020202E4 +:104CB00002020202020202020202020202020202D4 +:104CC00002020202020202020202020202020202C4 +:104CD00002020202020202020202020202020202B4 +:104CE00002020202020202020202020202020202A4 +:104CF0000202020202020202020202020202020294 +:104D00000202020202020202020202020202020283 +:104D10000202020202020202020202020202020273 +:104D20000202020202020202020202020202020263 +:104D30000202020202020202020202020202020253 +:104D40000202020202020202020202020202020243 +:104D50000202020202020202020202020202020233 +:104D60000202020202020202020202020202020223 +:104D70000202020202020202020202020202020213 +:104D80000202020202020202020202020202020203 +:104D900002020202020202020202020202020202F3 +:104DA00002020202020202020202020202020202E3 +:104DB00002020202020202020202020202020202D3 +:104DC00002020202020202020202020202020202C3 +:104DD00002020202020202020202020202020202B3 +:104DE00002020202020202020202020202020202A3 +:104DF0000202020202020202020202020202020293 +:104E00000202020202020202020202020202020282 +:104E10000202020202020202020202020202020272 +:104E20000202020202020202020202020202020262 +:104E30000202020202020202020202020202020252 +:104E40000202020202020202020202020202020242 +:104E50000202020202020202020202020202020232 +:104E60000202020202020202020202020202020222 +:104E70000202020202020202020202020202020212 +:104E80000202020202020202020202020202020202 +:104E900002020202020202020202020202020202F2 +:104EA00002020202020202020202020202020202E2 +:104EB00002020202020202020202020202020202D2 +:104EC00002020202020202020202020202020202C2 +:104ED00002020202020202020202020202020202B2 +:104EE00002020202020202020202020202020202A2 +:104EF0000202020202020202020202020202020292 +:104F00000202020202020202020202020202020281 +:104F10000202020202020202020202020202020271 +:104F20000202020202020202020202020202020261 +:104F30000202020202020202020202020202020251 +:104F40000202020202020202020202020202020241 +:104F50000202020202020202020202020202020231 +:104F60000202020202020202020202020202020221 +:104F70000202020202020202020202020202020211 +:104F80000202020202020202020202020202020201 +:104F900002020202020202020202020202020202F1 +:104FA00002020202020202020202020202020202E1 +:104FB00002020202020202020202020202020202D1 +:104FC00002020202020202020202020202020202C1 +:104FD00002020202020202020202020202020202B1 +:104FE00002020202020202020202020202020202A1 +:104FF0000202020202020202020202020202020291 +:105000000202020202020202020202020202020280 +:105010000202020202020202020202020202020270 +:105020000202020202020202020202020202020260 +:105030000202020202020202020202020202020250 +:105040000202020202020202020202020202020240 +:105050000202020202020202020202020202020230 +:105060000202020202020202020202020202020220 +:105070000202020202020202020202020202020210 +:105080000202020202020202020202020202020200 +:1050900002020202020202020202020202020202F0 +:1050A00002020202020202020202020202020202E0 +:1050B00002020202020202020202020202020202D0 +:1050C00002020202020202020202020202020202C0 +:1050D00002020202020202020202020202020202B0 +:1050E00002020202020202020202020202020202A0 +:1050F0000202020202020202020202020202020290 +:10510000020202020202020202020202020202027F +:10511000020202020202020202020202020202026F +:10512000020202020202020202020202020202025F +:10513000020202020202020202020202020202024F +:10514000020202020202020202020202020202023F +:10515000020202020202020202020202020202022F +:10516000020202020202020202020202020202021F +:10517000020202020202020202020202020202020F +:1051800002020202020202020202020202020202FF +:1051900002020202020202020202020202020202EF +:1051A00002020202020202020202020202020202DF +:1051B00002020202020202020202020202020202CF +:1051C00002020202020202020202020202020202BF +:1051D00002020202020202020202020202020202AF +:1051E000020202020202020202020202020202029F +:1051F000020202020202020202020202020202028F +:10520000020202020202020202020202020202027E +:10521000020202020202020202020202020202026E +:10522000020202020202020202020202020202025E +:10523000020202020202020202020202020202024E +:10524000020202020202020202020202020202023E +:10525000020202020202020202020202020202022E +:10526000020202020202020202020202020202021E +:10527000020202020202020202020202020202020E +:1052800002020202020202020202020202020202FE +:1052900002020202020202020202020202020202EE +:1052A00002020202020202020202020202020202DE +:1052B00002020202020202020202020202020202CE +:1052C00002020202020202020202020202020202BE +:1052D00002020202020202020202020202020202AE +:1052E000020202020202020202020202020202029E +:1052F000020202020202020202020202020202028E +:10530000020202020202020202020202020202027D +:10531000020202020202020202020202020202026D +:10532000020202020202020202020202020202025D +:10533000020202020202020202020202020202024D +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202020202020202020202020202ED +:1053A00002020202020202020202020202020202DD +:1053B00002020202020202020202020202020202CD +:1053C00002020202020202020202020202020202BD +:1053D00002020202020202020202020202020202AD +:1053E000020202020202020202020202020202029D +:1053F000020202020202020202020202020202028D +:10540000020202020202020202020202020202027C +:10541000020202020202020202020202020202026C +:10542000020202020202020202020202020202025C +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202020202020202020202EC +:1054A00002020202020202020202020202020202DC +:1054B00002020202020202020202020202020202CC +:1054C00002020202020202020202020202020202BC +:1054D00002020202020202020202020202020202AC +:1054E000020202020202020202020202020202029C +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020202020202020202020202020202DB +:1055B00002020202020202020202020202020202CB +:1055C00002020202020202020202020202020202BB +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020202020202020202020202020202027A +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020202020202020202020202020202DA +:1056B00002020202020202020202020202020202CA +:1056C00002020202020202020202020202020202BA +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020202020202020202D8 +:1058B00002020202020202020202020202020202C8 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020202020202020202D7 +:1059B00002020202020202020202020202020202C7 +:1059C00002020202020202020202020202020202B7 +:1059D00002020202020202020202020202020202A7 +:1059E0000202020202020202020202020202020297 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A40000202020202020202020202020202020236 +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002020202020202020202020202020202E6 +:105AA00002020202020202020202020202020202D6 +:105AB00002020202020202020202020202020202C6 +:105AC00002020202020202020202020202020202B6 +:105AD00002020202020202020202020202020202A6 +:105AE0000202020202020202020202020202020296 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020202020202020202020202020202E5 +:105BA00002020202020202020202020202020202D5 +:105BB00002020202020202020202020202020202C5 +:105BC00002020202020202020202020202020202B5 +:105BD00002020202020202020202020202020202A5 +:105BE0000202020202020202020202020202020295 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020202020202020202020202020202E4 +:105CA00002020202020202020202020202020202D4 +:105CB00002020202020202020202020202020202C4 +:105CC00002020202020202020202020202020202B4 +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202020202020202020294 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020202020202020202020202E3 +:105DA00002020202020202020202020202020202D3 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020202020202020202B3 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202020202020202020293 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020202B2 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202020202020202020292 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020200000000000000000043 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000000000000000000008F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000000000000000000000000000000000003B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:10660000000000000000000000000000000000008A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000000000000000000AA +:1066F000000000000000000000000000000000009A +:106700000000000000000000000000000000000089 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000099 +:106800000000000000000000000000000000000088 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000038 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000000B8 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000098 +:106900000000000000000000000000000000000087 +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000000000000000000B7 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000097 +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000000B6 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000096 +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B400000000000000000786B07000000000080DB +:106B5000A407000000000088D60700000000009095 +:106B600000080000000000982A080000000000A0B3 +:106B70004C080000000000A867080000000000B0FA +:106B800080080000000000B897080000000000C066 +:106B9000AC080000000000C8C1080000000000D0E0 +:106BA000D6080000000000D8EB080000000000E05C +:106BB0000009000000000039000000000000000093 +:106BC00000000000000000000000000000000100C4 +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000002E2 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000100C3 +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000002E1 +:106DB00000010101010101010001000100000000CA +:106DC00000000000000000000000000000000100C2 +:106DD00000000000000000000000000000000000B3 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000002E0 +:106EB00001010101010101010101010101010000C4 +:106EC00000000000000000000000000000000100C1 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000002DF +:106FB00002010101010101010101010101010000C2 +:106FC00000000000000000000000000000000100C0 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000002DE +:1070B00002010101010101010101010101010000C1 +:1070C00000000000000000000000000000000100BF +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000002DD +:1071B00002010101010101010101010101010000C0 +:1071C00000000000000000000000000000010100BD +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000002DC +:1072B00002020101010101010101010101010000BE +:1072C00000000000000000000000000000010100BC +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000002DB +:1073B00002020101010101010101010101010000BD +:1073C00000000000000000000000000000010100BB +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000002DA +:1074B00002020201010101010101010101010000BB +:1074C00000000000000000000000000000010100BA +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000002D9 +:1075B00002020202010101010101010101010000B9 +:1075C00000000000000000000000000000010100B9 +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000002D8 +:1076B00002020202010101010101010101010000B8 +:1076C00000000000000000000000000000010100B8 +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000002D7 +:1077B00002020202010101010101010101010000B7 +:1077C00000000000000000000000000001010100B6 +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000002D6 +:1078B00002020202020101010101010101010000B5 +:1078C00000000000000000000000000101010100B4 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000002D5 +:1079B00002020202020101010101010101010000B4 +:1079C00000000000000000000000000101010100B3 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000002D4 +:107AB00002020202020101010101010101010000B3 +:107AC00000000000000000000000000101010100B2 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000002D3 +:107BB00002020202020202010101010101010000B0 +:107BC00000000000000000000000010101010100B0 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000002D2 +:107CB00002020202020202020101010101010000AE +:107CC00000000000000000000000010101010100AF +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000002D1 +:107DB00002020202020202020101010101010000AD +:107DC00000000000000000000000010101010100AE +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000002D0 +:107EB00002020202020202020201010101010000AB +:107EC00000000000000000000001010101010100AC +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000002CF +:107FB00002020202020202020202010101010000A9 +:107FC00000000000000000000001010101010100AB +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000002CE +:1080B00002020202020202020202010101010000A8 +:1080C00000000000000000000001010101010100AA +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000002CD +:1081B00002020202020202020202020101010000A6 +:1081C00000000000000000000101010101010100A8 +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000002CC +:1082B00002020202020202020202020201010000A4 +:1082C00000000000000000000101010101010100A7 +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000002CB +:1083B00002020202020202020202020202010000A2 +:1083C00000000000000000000101010101010100A6 +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000002CA +:1084B00002020202020202020202020202010000A1 +:1084C00000000000000000010101010101010100A4 +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000002C9 +:1085B00002020202020202020202020202010000A0 +:1085C00000000000000000010101010101010100A3 +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000002C8 +:1086B000020202020202020202020202020200009E +:1086C00000000000000101010101010101010100A0 +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000002C7 +:1087B000020202020202020202020202020200009D +:1087C000000000000001010101010101010101009F +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000002C6 +:1088B000020202020202020202020202020200009C +:1088C000000000000001010101010101010101009E +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000002C5 +:1089B000020202020202020202020202020200009B +:1089C000000000000001010101010101010101009D +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000002C4 +:108AB000020202020202020202020202020200009A +:108AC000000000000001010101010101010101009C +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000002C3 +:108BB0000202020202020202020202020202000099 +:108BC000000000000001010101010101010101009B +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000002C2 +:108CB0000202020202020202020202020202000098 +:108CC0000000000001010101010101010101010099 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000002C1 +:108DB0000202020202020202020202020202000097 +:108DC0000000000001010101010101010101010098 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000002C0 +:108EB0000202020202020202020202020202000096 +:108EC0000000000001010101010101010101010097 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000002BF +:108FB0000202020202020202020202020202000095 +:108FC0000000000001010101010101010101010096 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000002BE +:1090B0000202020202020202020202020202000094 +:1090C0000000000001010101010101010101010095 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000002BD +:1091B0000202020202020202020202020202000093 +:1091C0000000000001010101010101010101010094 +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000002BC +:1092B0000202020202020202020202020202000092 +:1092C0000000000101010101010101010101010092 +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000002BB +:1093B0000202020202020202020202020202000091 +:1093C0000000000101010101010101010101010091 +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000002BA +:1094B0000202020202020202020202020202000090 +:1094C000000001010101010101010101010101008F +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000002B9 +:1095B000020202020202020202020202020200008F +:1095C000000001010101010101010101010101008E +:1095D000000000000000000000000000000000008B +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:10960000000000000000000000000000000000005A +:10961000000000000000000000000000000000004A +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000002B8 +:1096B000020202020202020202020202020200008E +:1096C000000001010101010101010101010101008D +:1096D000000000000000000000000000000000008A +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000049 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000002B7 +:1097B000020202020202020202020202020200008D +:1097C000000001010101010101010101010101008C +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000000000000000002B6 +:1098B000020202020202020202020202020200008C +:1098C000000101010101010101010101010101008A +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000000000000000078 +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000000000057 +:109910000000000000000000000000000000000047 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000002B5 +:1099B000020202020202020202020202020200008B +:1099C0000001010101010101010101010101010089 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0000000000000000000000000000000000067 +:109A00000000000000000000000000000000000056 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000000000000000000000000000000000F6 +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000000000000000002B4 +:109AB000020202020202020202020202020200008A +:109AC0000001010101010101010101010101010088 +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000076 +:109AF0000000000000000000000000000000000066 +:109B00000000000000000000000000000000000055 +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000002B3 +:109BB0000202020202020202020202020202000089 +:109BC0000001010101010101010101010101010087 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000002B2 +:109CB0000202020202020202020202020202000088 +:109CC0000001010101010101010101010101010086 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000002B1 +:109DB0000202020202020202020202020202000087 +:109DC0000001010101010101010101010101010085 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000002B0 +:109EB0000202020202020202020202020202000086 +:109EC0000001010101010101010101010101010084 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000002AF +:109FB0000202020202020202020202020202000085 +:109FC0000101010101010101010101010101010082 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000002AE +:10A0B0000202020202020202020202020202000084 +:10A0C0000101010101010101010101010101010081 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000002AD +:10A1B0000202020202020202020202020202000083 +:10A1C0000101010101010101010101010101010080 +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000002AC +:10A2B0000202020202020202020202020202000082 +:10A2C000010101010101010101010101010101007F +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000002AB +:10A3B0000202020202020202020202020202000081 +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000326A +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000010000000000000000007B +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B0000000000000000002000000000000000099 +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000010000000000000000007A +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B0000000000000000002000000010000000097 +:10A6C0000100010001000000000000000000000087 +:10A6D0000000000000000100000000000000000079 +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B000000000000000000201010101010101018F +:10A7C0000101010101010000000000000000000083 +:10A7D0000000000000000100000000000000000078 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B000000000000000000202010101010101018D +:10A8C0000101010101010000000000000000000082 +:10A8D0000000000000000100000000000000000077 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000058 +:10A900000000000000000000000000000000000047 +:10A910000000000000000000000000000000000037 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B000000000000000000202010101010101018C +:10A9C0000101010101010000000000000000000081 +:10A9D0000000000000010100000000000000000075 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000046 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB000000000000000000202010101010101018B +:10AAC0000101010101010000000000000000000080 +:10AAD0000000000000010100000000000000000074 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000002020201010101010189 +:10ABC000010101010101000000000000000000007F +:10ABD0000000000000010100000000000000000073 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000002020201010101010188 +:10ACC000010101010101000000000000000000007E +:10ACD0000000000001010100000000000000000071 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000002020202010101010186 +:10ADC000010101010101000000000000000000007D +:10ADD0000000000001010100000000000000000070 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000002020202020101010184 +:10AEC000010101010101000000000000000000007C +:10AED000000000000101010000000000000000006F +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000002020202020101010183 +:10AFC000010101010101000000000000000000007B +:10AFD000000000010101010000000000000000006D +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000002020202020101010182 +:10B0C000010101010101000000000000000000007A +:10B0D000000001010101010000000000000000006B +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B0000000000000000002020202020201010180 +:10B1C0000101010101010000000000000000000079 +:10B1D0000001010101010100000000000000000069 +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000202020202020201017E +:10B2C0000101010101010000000000000000000078 +:10B2D0000001010101010100000000000000000068 +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000000000000000000202020202020201017D +:10B3C0000101010101010000000000000000000077 +:10B3D0000001010101010100000000000000000067 +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000202020202020202017B +:10B4C0000101010101010000000000000000000076 +:10B4D0000101010101010100000000000000000065 +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000000000000000000000000000000000002B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B0000000000000000002020202020202020279 +:10B5C0000101010101010000000000000000000075 +:10B5D0000101010101010100000000000000000064 +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B0000000000000000002020202020202020278 +:10B6C0000201010101010000000000000000000073 +:10B6D0000101010101010100000000000000000063 +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000002020202020202020277 +:10B7C0000201010101010000000000000000000171 +:10B7D0000101010101010100000000000000000062 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000002020202020202020276 +:10B8C000020202010101000000000000000000016E +:10B8D0000101010101010100000000000000000061 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000002020202020202020275 +:10B9C000020202020101000000000000000001016B +:10B9D0000101010101010100000000000000000060 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000002020202020202020274 +:10BAC0000202020202010000000000000000010169 +:10BAD000010101010101010000000000000000005F +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000002020202020202020273 +:10BBC0000202020202010000000000000000010168 +:10BBD000010101010101010000000000000000005E +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000002020202020202020272 +:10BCC0000202020202020000000000000000010166 +:10BCD000010101010101010000000000000000005D +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000002020202020202020271 +:10BDC0000202020202020000000000000001010164 +:10BDD000010101010101010000000000000000005C +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000002020202020202020270 +:10BEC0000202020202020000000000000001010163 +:10BED000010101010101010000000000000000005B +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB000000000000000000202020202020202026F +:10BFC0000202020202020000000000000101010161 +:10BFD000010101010101010000000000000000005A +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B000000000000000000202020202020202026E +:10C0C0000202020202020000000000000101010160 +:10C0D0000101010101010100000000000000000059 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000202020202020202026D +:10C1C000020202020202000000000000010101015F +:10C1D0000101010101010100000000000000000058 +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000202020202020202026C +:10C2C000020202020202000000000000010101015E +:10C2D0000101010101010100000000000000000057 +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000000001D +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000202020202020202026B +:10C3C000020202020202000000000000010101015D +:10C3D0000101010101010100000000000000000056 +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000202020202020202026A +:10C4C000020202020202000000000001010101015B +:10C4D0000101010101010100000000000000000055 +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B0000000000000000002020202020202020269 +:10C5C000020202020202000000000001010101015A +:10C5D0000101010101010100000000000000000054 +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B0000000000000000002020202020202020268 +:10C6C0000202020202020000000000010101010159 +:10C6D0000101010101010100000000000000000053 +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000002020202020202020267 +:10C7C0000202020202020000000001010101010157 +:10C7D0000101010101010100000000000000000052 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000002020202020202020266 +:10C8C0000202020202020000000001010101010156 +:10C8D0000101010101010100000000000000000051 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000002020202020202020265 +:10C9C0000202020202020000000001010101010155 +:10C9D0000101010101010100000000000000000050 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000002020202020202020264 +:10CAC0000202020202020000000001010101010154 +:10CAD000010101010101010000000000000000004F +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000002020202020202020263 +:10CBC0000202020202020000000101010101010152 +:10CBD000010101010101010000000000000000004E +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000002020202020202020262 +:10CCC0000202020202020000000101010101010151 +:10CCD000010101010101010000000000000000004D +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD10000000000000000000000000000000000013 +:10CD20000000000000000000000000000000000003 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000002020202020202020261 +:10CDC0000202020202020000000101010101010150 +:10CDD000010101010101010000000000000000004C +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000002020202020202020260 +:10CEC000020202020202000000010101010101014F +:10CED000010101010101010000000000000000004B +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB000000000000000000202020202020202025F +:10CFC000020202020202000000010101010101014E +:10CFD000010101010101010000000000000000004A +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B000000000000000000202020202020202025E +:10D0C000020202020202000000010101010101014D +:10D0D0000101010101010100000000000000000049 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000202020202020202025D +:10D1C000020202020202000001010101010101014B +:10D1D0000101010101010100000000000000000048 +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000202020202020202025C +:10D2C000020202020202000001010101010101014A +:10D2D0000101010101010100000000000000000047 +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000202020202020202025B +:10D3C0000202020202020000010101010101010149 +:10D3D0000101010101010100000000000000000046 +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000202020202020202025A +:10D4C0000202020202020000010101010101010148 +:10D4D0000101010101010100000000000000000045 +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B0000000000000000002020202020202020259 +:10D5C000020202020202000000000000000000004F +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000002A000000000000000030 +:10D6D0000000000000000000000000000000010049 +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000267 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000010048 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D810000000000000000000000000000000000008 +:10D8200000000000000000000000000000000000F8 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000266 +:10D8C0000000000000000001000001000101000054 +:10D8D0000000000000000000000000000000010047 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000000000000000000F7 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000265 +:10D9C000020000010101000101010101010100004B +:10D9D0000000000000000000000000000000010046 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000264 +:10DAC0000200000101010101010101010101000049 +:10DAD0000000000000000000000000000001010044 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000263 +:10DBC0000200000101010101010101010101000048 +:10DBD0000000000000000000000000000001010043 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000262 +:10DCC0000200010101010101010101010101000046 +:10DCD0000000000000000000000000000101010041 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000261 +:10DDC0000201010101010101010101010101000044 +:10DDD0000000000000000000000000000101010040 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000260 +:10DEC0000202010101010101010101010101000042 +:10DED000000000000000000000000000010101003F +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB000000000000000000000000000000000025F +:10DFC0000202020101010101010101010101000040 +:10DFD000000000000000000000000001010101003D +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B000000000000000000000000000000000025E +:10E0C000020202020101010101010101010100003E +:10E0D000000000000000000000000101010101003B +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000025D +:10E1C000020202020101010101010101010100003D +:10E1D0000000000000000000000101010101010039 +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000025C +:10E2C000020202020201010101010101010100003B +:10E2D0000000000000000000000101010101010038 +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000025B +:10E3C0000202020202020101010101010101000039 +:10E3D0000000000000000000010101010101010036 +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000025A +:10E4C0000202020202020201010101010101000037 +:10E4D0000000000000000001010101010101010034 +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B0000000000000000000000000000000000259 +:10E5C0000202020202020202010101010101000035 +:10E5D0000000000000000001010101010101010033 +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B0000000000000000000000000000000000258 +:10E6C0000202020202020202020101010101000033 +:10E6D0000000000000000001010101010101010032 +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000257 +:10E7C0000202020202020202020202010101000030 +:10E7D0000000000000000001010101010101010031 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000256 +:10E8C000020202020202020202020202010100002E +:10E8D000000000000000010101010101010101002F +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000255 +:10E9C000020202020202020202020202020100002C +:10E9D000000000000001010101010101010101002D +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000254 +:10EAC000020202020202020202020202020200002A +:10EAD000000000000001010101010101010101002C +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000253 +:10EBC0000202020202020202020202020202000029 +:10EBD000000000000101010101010101010101002A +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000252 +:10ECC0000202020202020202020202020202000028 +:10ECD0000000000001010101010101010101010029 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000251 +:10EDC0000202020202020202020202020202000027 +:10EDD0000000000001010101010101010101010028 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000250 +:10EEC0000202020202020202020202020202000026 +:10EED0000000000001010101010101010101010027 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB000000000000000000000000000000000024F +:10EFC0000202020202020202020202020202000025 +:10EFD0000000000101010101010101010101010025 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B000000000000000000000000000000000024E +:10F0C0000202020202020202020202020202000024 +:10F0D0000000000101010101010101010101010024 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000024D +:10F1C0000202020202020202020202020202000023 +:10F1D0000000000101010101010101010101010023 +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000024C +:10F2C0000202020202020202020202020202000022 +:10F2D0000000000101010101010101010101010022 +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000024B +:10F3C0000202020202020202020202020202000021 +:10F3D0000000000101010101010101010101010021 +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000024A +:10F4C0000202020202020202020202020202000020 +:10F4D000000001010101010101010101010101001F +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B0000000000000000000000000000000000249 +:10F5C000020202020202020202020202020200001F +:10F5D000000001010101010101010101010101001E +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B0000000000000000000000000000000000248 +:10F6C000020202020202020202020202020200001E +:10F6D000000001010101010101010101010101001D +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000247 +:10F7C000020202020202020202020202020200001D +:10F7D000000101010101010101010101010101001B +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000246 +:10F8C000020202020202020202020202020200001C +:10F8D000000101010101010101010101010101001A +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000245 +:10F9C000020202020202020202020202020200001B +:10F9D0000001010101010101010101010101010019 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000000000000000000000000000000000000F6 +:10FA100000000000000000000000000000000000E6 +:10FA200000000000000000000000000000000000D6 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000244 +:10FAC000020202020202020202020202020200001A +:10FAD0000001010101010101010101010101010018 +:10FAE0000000000000000000000000000000000016 +:10FAF0000000000000000000000000000000000006 +:10FB000000000000000000000000000000000000F5 +:10FB100000000000000000000000000000000000E5 +:10FB200000000000000000000000000000000000D5 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000055 +:10FBB0000000000000000000000000000000000243 +:10FBC0000202020202020202020202020202000019 +:10FBD0000001010101010101010101010101010017 +:10FBE0000000000000000000000000000000000015 +:10FBF0000000000000000000000000000000000005 +:10FC000000000000000000000000000000000000F4 +:10FC100000000000000000000000000000000000E4 +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000242 +:10FCC0000202020202020202020202020202000018 +:10FCD0000001010101010101010101010101010016 +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000004 +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000241 +:10FDC0000202020202020202020202020202000017 +:10FDD0000101010101010101010101010101010014 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000240 +:10FEC0000202020202020202020202020202000016 +:10FED0000101010101010101010101010101010013 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB000000000000000000000000000000000023F +:10FFC0000202020202020202020202020202000015 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:0200000280007C +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000002A06 +:1000D0000000000000000000000000000000000020 +:1000E000000000000000010000000000000000000F +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000000000000000000000CF +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000200000000000000002D +:1001D000000000000000000000000000000000001F +:1001E000000000000000010000000000000000000E +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000200000000000000002C +:1002D000000000010000000000000000000000001D +:1002E000000000000000010000000000000000000D +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000200000000000000002B +:1003D000000001010000000000000000000000001B +:1003E000000000000000010000000000000000000C +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000200000000000000002A +:1004D000000001010000000000000000000000001A +:1004E000000000000001010000000000000000000A +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C0000000000000000002010000000000000028 +:1005D0000100010101000000000000000000000017 +:1005E0000000000001010100000000000000000008 +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C0000000000000000002020000000000000026 +:1006D0000101010101000000000000000000000015 +:1006E0000000000101010100000000000000000006 +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000002020000010100000122 +:1007D0000101010101000000000000000000000014 +:1007E0000000010101010100000000000000000004 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C000000000000000000202020001010000011F +:1008D0000101010101010000000000000000000012 +:1008E0000000010101010100000000000000000003 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C000000000000000000202020001010000011E +:1009D0000101010101010000000000000000000011 +:1009E0000000010101010100000000000000000002 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC000000000000000000202020001010101011B +:100AD0000101010101010000000000000000000010 +:100AE0000001010101010100000000000000000000 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC000000000000000000202020001010101011A +:100BD000010101010101000000000000000000000F +:100BE00001010101010101000000000000000000FE +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000000000000000000000E4 +:100C100000000000000000000000000000000000D4 +:100C200000000000000000000000000000000000C4 +:100C300000000000000000000000000000000000B4 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000002020202010101010117 +:100CD000010101010101000000000000000000000E +:100CE00001010101010101000000000000000000FD +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000000E3 +:100D100000000000000000000000000000000000D3 +:100D200000000000000000000000000000000000C3 +:100D300000000000000000000000000000000000B3 +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000000000000000000000073 +:100D80000000000000000000000000000000000063 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000002020202020101010115 +:100DD000010101010101000000000000000000010C +:100DE00001010101010101000000000000000000FC +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000002020202020101010114 +:100ED000010101010101000000000000000000010B +:100EE00001010101010101000000000000000000FB +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000002020202020201010112 +:100FD000010101010101000000000000000000010A +:100FE00001010101010101000000000000000000FA +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000002020202020201010111 +:1010D0000101010101010000000000000000010108 +:1010E00001010101010101000000000000000000F9 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000202020202020201010F +:1011D0000101010101010000000000000000010107 +:1011E00001010101010101000000000000000000F8 +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000202020202020202020C +:1012D0000201010101010000000000000001010104 +:1012E00001010101010101000000000000000000F7 +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000202020202020202020B +:1013D00002020202010100000000000001010101FF +:1013E00001010101010101000000000000000000F6 +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000202020202020202020A +:1014D00002020202010100000000000001010101FE +:1014E00001010101010101000000000000000000F5 +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C0000000000000000002020202020202020209 +:1015D00002020202020100000000000001010101FC +:1015E00001010101010101000000000000000000F4 +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C0000000000000000002020202020202020208 +:1016D00002020202020100000000000001010101FB +:1016E00001010101010101000000000000000000F3 +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000002020202020202020207 +:1017D00002020202020200000000000101010101F8 +:1017E00001010101010101000000000000000000F2 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000002020202020202020206 +:1018D00002020202020200000000000101010101F7 +:1018E00001010101010101000000000000000000F1 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000002020202020202020205 +:1019D00002020202020200000000000101010101F6 +:1019E00001010101010101000000000000000000F0 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000002020202020202020204 +:101AD00002020202020200000000000101010101F5 +:101AE00001010101010101000000000000000000EF +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000002020202020202020203 +:101BD00002020202020200000000000101010101F4 +:101BE00001010101010101000000000000000000EE +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000000000000000B4 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000000000000000000000000000054 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000000000000000000000034 +:101CB0000000000000000000000000000000000024 +:101CC0000000000000000002020202020202020202 +:101CD00002020202020200000000000101010101F3 +:101CE00001010101010101000000000000000000ED +:101CF00000000000000000000000000000000000E4 +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000000C3 +:101D200000000000000000000000000000000000B3 +:101D300000000000000000000000000000000000A3 +:101D40000000000000000000000000000000000093 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000073 +:101D70000000000000000000000000000000000063 +:101D80000000000000000000000000000000000053 +:101D90000000000000000000000000000000000043 +:101DA0000000000000000000000000000000000033 +:101DB0000000000000000000000000000000000023 +:101DC0000000000000000002020202020202020201 +:101DD00002020202020200000000000101010101F2 +:101DE00001010101010101000000000000000000EC +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E300000000000000000000000000000000000A2 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000000000000000000022 +:101EC0000000000000000002020202020202020200 +:101ED00002020202020200000000010101010101F0 +:101EE00001010101010101000000000000000000EB +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000000000000000000B1 +:101F300000000000000000000000000000000000A1 +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F80000000000000000000000000000000000051 +:101F90000000000000000000000000000000000041 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000000000000000000021 +:101FC00000000000000000020202020202020202FF +:101FD00002020202020200000000010101010101EF +:101FE00001010101010101000000000000000000EA +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000000000000000000B0 +:1020300000000000000000000000000000000000A0 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C00000000000000000020202020202020202FE +:1020D00002020202020200000000010101010101EE +:1020E00001010101010101000000000000000000E9 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C00000000000000000020202020202020202FD +:1021D00002020202020200000000010101010101ED +:1021E00001010101010101000000000000000000E8 +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C00000000000000000020202020202020202FC +:1022D00002020202020200000001010101010101EB +:1022E00001010101010101000000000000000000E7 +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C00000000000000000020202020202020202FB +:1023D00002020202020200000101010101010101E9 +:1023E00001010101010101000000000000000000E6 +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C00000000000000000020202020202020202FA +:1024D00002020202020200000101010101010101E8 +:1024E00001010101010101000000000000000000E5 +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C00000000000000000020202020202020202F9 +:1025D00002020202020200000101010101010101E7 +:1025E00001010101010101000000000000000000E4 +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C00000000000000000020202020202020202F8 +:1026D00002020202020200000101010101010101E6 +:1026E00001010101010101000000000000000000E3 +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C00000000000000000020202020202020202F7 +:1027D00002020202020200000101010101010101E5 +:1027E00001010101010101000000000000000000E2 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C00000000000000000020202020202020202F6 +:1028D00002020202020200000101010101010101E4 +:1028E00001010101010101000000000000000000E1 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C00000000000000000020202020202020202F5 +:1029D00002020202020200000000000000000000EB +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000220000000000000000D4 +:102AE00000000000000000000000000000000100E5 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000203 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000010100E3 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000202 +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000010100E2 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000201 +:102DD00002000000000000000000000000000000F1 +:102DE00000000000000000000000000001010100E0 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000200 +:102ED00002000000000000000000000000000000F0 +:102EE00000000000000000000000000101010100DE +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC00000000000000000000000000000000002FF +:102FD00002000000000000000000000000010000EE +:102FE00000000000000000000000010101010100DC +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C00000000000000000000000000000000002FE +:1030D00002000000000000000000000000010000ED +:1030E00000000000000000000000010101010100DB +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000002FD +:1031D00002000000000000000000000000010000EC +:1031E00000000000000000000101010101010100D8 +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000002FC +:1032D00002000000000000000000000000010000EB +:1032E00000000000000000000101010101010100D7 +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000002FB +:1033D00002000000000000000100010000010000E8 +:1033E00000000000000000010101010101010100D5 +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000002FA +:1034D00002000000000000000100010000010000E7 +:1034E00000000000000000010101010101010100D4 +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000000000000000002F9 +:1035D00002020000000000010101010000010000E2 +:1035E00000000000000001010101010101010100D2 +:1035F00000000000000000000000000000000000CB +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000002F8 +:1036D00002020200000000010101010100010000DE +:1036E00000000000000001010101010101010100D1 +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000002F7 +:1037D00002020200000101010101010101010000DA +:1037E00000000000000101010101010101010100CF +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000002F6 +:1038D00002020201000101010101010101010000D8 +:1038E00000000000000101010101010101010100CE +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000002F5 +:1039D00002020202010101010101010101010000D5 +:1039E00000000000010101010101010101010100CC +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000002F4 +:103AD00002020202010101010101010101010000D4 +:103AE00000000000010101010101010101010100CB +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000002F3 +:103BD00002020202020201010101010101010000D1 +:103BE00000000000010101010101010101010100CA +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000002F2 +:103CD00002020202020202020201010101010000CD +:103CE00000000001010101010101010101010100C8 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000002F1 +:103DD00002020202020202020202020101020000C9 +:103DE00000000001010101010101010101010100C7 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000002F0 +:103ED00002020202020202020202020101020000C8 +:103EE00000000001010101010101010101010100C6 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000002EF +:103FD00002020202020202020202020201020000C6 +:103FE00000000001010101010101010101010100C5 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000002EE +:1040D00002020202020202020202020202020000C4 +:1040E00000000101010101010101010101010100C3 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000002ED +:1041D00002020202020202020202020202020000C3 +:1041E00000010101010101010101010101010100C1 +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000002EC +:1042D00002020202020202020202020202020000C2 +:1042E00000010101010101010101010101010100C0 +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000002EB +:1043D00002020202020202020202020202020000C1 +:1043E00000010101010101010101010101010100BF +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000002EA +:1044D00002020202020202020202020202020000C0 +:1044E00000010101010101010101010101010100BE +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000002E9 +:1045D00002020202020202020202020202020000BF +:1045E00000010101010101010101010101010100BD +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000002E8 +:1046D00002020202020202020202020202020000BE +:1046E00000010101010101010101010101010100BC +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000002E7 +:1047D00002020202020202020202020202020000BD +:1047E00000010101010101010101010101010100BB +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000002E6 +:1048D00002020202020202020202020202020000BC +:1048E00000010101010101010101010101010100BA +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000002E5 +:1049D00002020202020202020202020202020000BB +:1049E00001010101010101010101010101010100B8 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000002E4 +:104AD00002020202020202020202020202020000BA +:104AE00001010101010101010101010101010100B7 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000002E3 +:104BD00002020202020202020202020202020000B9 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD0000000000000000000000000000000001BB9 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000001000000000000000000B3 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000020000000000000000D1 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000001000000000000000000B2 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000020000000000000000D0 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000010101000000000000000000AF +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000020200000000000000CD +:104FE00000000000000000000000000000000000C1 +:104FF00000000001010101000000000000000000AD +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000020200000000000000CC +:1050E00000000000000000000000000000000000C0 +:1050F00000000101010101000000000000000000AB +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000020200000000000000CB +:1051E00000000000000000000000000000000000BF +:1051F00000010101010101000000000000000000A9 +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000020200000000000000CA +:1052E00000000000000000000000000000000000BE +:1052F00001010101010101000000000000000000A7 +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000020202000000000000C7 +:1053E00000000000000000000000000000000001BC +:1053F00001010101010101000000000000000000A6 +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000020202020000000000C4 +:1054E00000000000000000000000000000000001BB +:1054F00001010101010101000000000000000000A5 +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000020202020000000000C3 +:1055E00000000000000000000000000000000101B9 +:1055F00001010101010101000000000000000000A4 +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000020202020000000001C1 +:1056E00000010001000000000000000000000101B6 +:1056F00001010101010101000000000000000000A3 +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000020202020000000001C0 +:1057E00001010101010000000000000000010101B1 +:1057F00001010101010101000000000000000000A2 +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000020202020200000101BC +:1058E00001010101010000000000000001010101AF +:1058F00001010101010101000000000000000000A1 +:105900000000000000000000000000000000000097 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000020202020201000101BA +:1059E00001010101010000000000000001010101AE +:1059F00001010101010101000000000000000000A0 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000020202020202010101B7 +:105AE00001010101010000000000000001010101AD +:105AF000010101010101010000000000000000009F +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000020202020202020202B3 +:105BE00001010101010000000000000101010101AB +:105BF000010101010101010000000000000000009E +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000020202020202020202B2 +:105CE00002020101010000000000000101010101A8 +:105CF000010101010101010000000000000000009D +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000020202020202020202B1 +:105DE00002020202010000000000000101010101A5 +:105DF000010101010101010000000000000000009C +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000020202020202020202B0 +:105EE00002020202020000000000000101010101A3 +:105EF000010101010101010000000000000000009B +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000020202020202020202AF +:105FE00002020202020100000000010101010101A0 +:105FF000010101010101010000000000000000009A +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000020202020202020202AE +:1060E000020202020201000000010101010101019E +:1060F0000101010101010100000000000000000099 +:10610000000000000000000000000000000000008F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000020202020202020202AD +:1061E000020202020201000000010101010101019D +:1061F0000101010101010100000000000000000098 +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000020202020202020202AC +:1062E000020202020202000000010101010101019B +:1062F0000101010101010100000000000000000097 +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000020202020202020202AB +:1063E000020202020202000000010101010101019A +:1063F0000101010101010100000000000000000096 +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000020202020202020202AA +:1064E0000202020202020000010101010101010198 +:1064F0000101010101010100000000000000000095 +:10650000000000000000000000000000000000008B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000000000000000000000000000000000003B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000020202020202020202A9 +:1065E0000202020202020000010101010101010197 +:1065F0000101010101010100000000000000000094 +:10660000000000000000000000000000000000008A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000020202020202020202A8 +:1066E000020202020202000000000000000000009E +:1066F000000000000000000000000000000000009A +:106700000000000000000000000000000000000089 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E0000000000000000019000000000000000090 +:1067F0000000000000000000000000000000010098 +:106800000000000000000000000000000000000088 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000038 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000002B6 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000001010096 +:106900000000000000000000000000000000000087 +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000000000000000002B5 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000101010094 +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000002B4 +:106AE00001000000000000000000000000000000A5 +:106AF0000000000000000000000000000101010093 +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000035 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000000000000000002B3 +:106BE00001000000000000000000000000000000A4 +:106BF0000000000000000000000000000101010092 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000002B2 +:106CE00002000000000000000000000000000000A2 +:106CF0000000000000000000000000010101010090 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000002B1 +:106DE00002000000000000000000000000000000A1 +:106DF000000000000000000000000101010101008E +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000000000000000002B0 +:106EE000020100000000000000000000000000009F +:106EF000000000000000000000000101010101008D +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000002AF +:106FE000020201000000000000000000000000009C +:106FF000000000000000000000010101010101008B +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000002AE +:1070E0000202020000000000000000000100000099 +:1070F0000000000000000000010101010101010089 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000002AD +:1071E0000202020200000000000000000101000095 +:1071F0000000000000000001010101010101010087 +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D00000000000000000000000000000000002AC +:1072E0000202020200000000000000000101000094 +:1072F0000000000000000101010101010101010085 +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000002AB +:1073E0000202020202000000000000000101000091 +:1073F0000000000000010101010101010101010083 +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000002AA +:1074E000020202020202000000000100010100008D +:1074F0000000000001010101010101010101010081 +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000002A9 +:1075E0000202020202020200010001010101000088 +:1075F0000000000001010101010101010101010080 +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000000BA +:1076D00000000000000000000000000000000002A8 +:1076E0000202020202020202020101010101000083 +:1076F000000001010101010101010101010101007D +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000000B9 +:1077D00000000000000000000000000000000002A7 +:1077E000020202020202020202020201020100007F +:1077F000000101010101010101010101010101007B +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000000B8 +:1078D00000000000000000000000000000000002A6 +:1078E000020202020202020202020202020200007C +:1078F000000101010101010101010101010101007A +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000002A5 +:1079E000020202020202020202020202020200007B +:1079F0000101010101010101010101010101010078 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000002A4 +:107AE000020202020202020202020202020200007A +:107AF0000101010101010101010101010101010077 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000002A3 +:107BE0000202020202020202020202020202000079 +:107BF0000101010101010101010101010101010076 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000002A2 +:107CE0000202020202020202020202020202000078 +:107CF0000101010101010101010101010101010075 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000002A1 +:107DE0000202020202020202020202020202000077 +:107DF0000101010101010101010101010101010074 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000002A0 +:107EE0000202020202020202020202020202000076 +:107EF0000101010101010101010101010101010073 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD000000000000000000000000000000000029F +:107FE0000202020202020202020202020202000075 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000001779 +:1080F0000000000000000000000000000000000080 +:10810000000000000000010000000000000000006E +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000200000000000000008D +:1081F000000000000000000000000000000000007F +:10820000000000000000010000000000000000006D +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E000000000000000000200000000000000008C +:1082F000000000000000000000000000000000007E +:10830000000000000101010000000000000000006A +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E000000000000000000201000000000000008A +:1083F000000000000000000000000000000000007D +:108400000000000001010100000000000000000069 +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E0000000000000000002010000000000000089 +:1084F000000000000000000000000000000000007C +:108500000000000101010100000000000000000067 +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E0000000000000000002020000000000000087 +:1085F000000000000000000000000000000000007B +:108600000000010101010100000000000000000065 +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E0000000000000000002020000000000000086 +:1086F000000000000000000000000000000000007A +:108700000000010101010100000000000000000064 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000002020000000000000085 +:1087F0000000000000000000000000000000000079 +:108800000001010101010100000000000000000062 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000002020202000000000080 +:1088F0000000000000000000000000000000000078 +:108900000101010101010100000000000000000060 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E000000000000000000202020200000000007F +:1089F0000000000000000000000000000000000176 +:108A0000010101010101010000000000000000005F +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE000000000000000000202020202000000007C +:108AF0000000000000000000000000000000010174 +:108B0000010101010101010000000000000000005E +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000002020202020200000079 +:108BF0000000000000000000000000000001010172 +:108C0000010101010101010000000000000000005D +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000002020202020202000076 +:108CF000000001000000000000000000010101016F +:108D0000010101010101010000000000000000005C +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000002020202020202020073 +:108DF000000001000100000000000001010101016C +:108E0000010101010101010000000000000000005B +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000002020202020202020270 +:108EF000000101000100000000000001010101016A +:108F0000010101010101010000000000000000005A +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE000000000000000000202020202020202026F +:108FF0000202020101000000000101010101010162 +:109000000101010101010100000000000000000059 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E000000000000000000202020202020202026E +:1090F0000202020101000000010101010101010160 +:109100000101010101010100000000000000000058 +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000000000000000000202020202020202026D +:1091F000020202020200000001010101010101015D +:109200000101010101010100000000000000000057 +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000202020202020202026C +:1092F000020202020200000001010101010101015C +:109300000101010101010100000000000000000056 +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000202020202020202026B +:1093F000020202020201000001010101010101015A +:109400000101010101010100000000000000000055 +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000000000000000000202020202020202026A +:1094F0000202020202020000010101010101010158 +:109500000101010101010100000000000000000054 +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D000000000000000000000000000000000008B +:1095E0000000000000000002020202020202020269 +:1095F0000202020202020000010101010101010157 +:109600000101010101010100000000000000000053 +:10961000000000000000000000000000000000004A +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C000000000000000000000000000000000009A +:1096D000000000000000000000000000000000008A +:1096E0000000000000000002020202020202020268 +:1096F000020202020202000000000000000000005E +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000049 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000099 +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000015000000000000000054 +:109800000000000000000000000000000000010057 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000000000000000000000A8 +:1098C0000000000000000000000000000000000098 +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000000000000000276 +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000101010054 +:109910000000000000000000000000000000000047 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000000B7 +:1099B00000000000000000000000000000000000A7 +:1099C0000000000000000000000000000000000097 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000275 +:1099F0000000000000000000000000000000000067 +:109A00000000000000000000000000010101010052 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000000000000000000000000000000000F6 +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000000000000000000B6 +:109AB00000000000000000000000000000000000A6 +:109AC0000000000000000000000000000000000096 +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000274 +:109AF0000000000000000000000000000000000066 +:109B00000000000000000000000000010101010051 +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000273 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000010101010050 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000272 +:109CF0000200000000000000000000000000000062 +:109D0000000000000000000000000101010101004E +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000271 +:109DF0000200000000000000000000000100000060 +:109E0000000000000000000000010101010101004C +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000270 +:109EF000020000000000000000000001010000005E +:109F00000000000000000001010101010101010049 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE000000000000000000000000000000000026F +:109FF000020200000000000000000001010000005B +:10A000000000000000000001010101010101010048 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E000000000000000000000000000000000026E +:10A0F0000202020000000000000000010100000058 +:10A100000000000000010101010101010101010045 +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000026D +:10A1F0000202020200000000000000010101000054 +:10A200000000000001010101010101010101010043 +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000026C +:10A2F0000202020202000000000000010101000051 +:10A300000000000101010101010101010101010041 +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000026B +:10A3F000020202020202020100000001010100004B +:10A40000000001010101010101010101010101003F +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000026A +:10A4F0000202020202020202000100020201000046 +:10A50000000101010101010101010101010101003D +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E0000000000000000000000000000000000269 +:10A5F0000202020202020202020201020201000041 +:10A60000000101010101010101010101010101003C +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E0000000000000000000000000000000000268 +:10A6F000020202020202020202020202020200003E +:10A70000000101010101010101010101010101003B +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000267 +:10A7F000020202020202020202020202020200003D +:10A800000101010101010101010101010101010039 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000000000000000000266 +:10A8F000020202020202020202020202020200003C +:10A900000101010101010101010101010101010038 +:10A910000000000000000000000000000000000037 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000000000077 +:10A9E0000000000000000000000000000000000265 +:10A9F000020202020202020202020202020200003B +:10AA00000101010101010101010101010101010037 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000264 +:10AAF000020202020202020202020202020200003A +:10AB00000101010101010101010101010101010036 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000263 +:10ABF0000202020202020202020202020202000039 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF000000000000000000000000000000000153F +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000100000000000000000032 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000002000000000000000051 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000010100000000000000000030 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000002000000000000000050 +:10AF00000000000000000000000000000000000041 +:10AF1000000000000001010000000000000000002F +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF000000000000000000200000000000000004F +:10B000000000000000000000000000000000000040 +:10B01000000000000101010000000000000000002D +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F000000000000000000202000000000000004C +:10B10000000000000000000000000000000000003F +:10B11000000000000101010000000000000000002C +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000202000000000000004B +:10B20000000000000000000000000000000000003E +:10B210000000010101010100000000000000000029 +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000202000000000000004A +:10B30000000000000000000000000000000000003D +:10B310000001010101010100000000000000000027 +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000000000000000005D +:10B3F0000000000000000002020000000000000049 +:10B40000000000000000000000000000000000003C +:10B410000101010101010100000000000000000025 +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F0000000000000000002020202000000000044 +:10B50000000000000000000000000000000000013A +:10B510000101010101010100000000000000000024 +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F0000000000000000002020202000000000043 +:10B600000000000000000000000000000000010138 +:10B610000101010101010100000000000000000023 +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F0000000000000000002020202020000000040 +:10B700000000000000000000000000000101010135 +:10B710000101010101010100000000000000000022 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F000000000000000000202020202020200003B +:10B800000000000000000000000000010101010133 +:10B810000101010101010100000000000000000021 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000002020202020202020038 +:10B900000000000000010000000000010101010131 +:10B910000101010101010100000000000000000020 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000002020202020202020235 +:10BA0000000000000001000000010101010101012E +:10BA1000010101010101010000000000000000001F +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000002020202020202020234 +:10BB0000020000000001000000010101010101012B +:10BB1000010101010101010000000000000000001E +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000002020202020202020233 +:10BC00000202000000010000000101010101010128 +:10BC1000010101010101010000000000000000001D +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000002020202020202020232 +:10BD00000202020201020000000101010101010121 +:10BD1000010101010101010000000000000000001C +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000002020202020202020231 +:10BE0000020202020202000001010101010101011E +:10BE1000010101010101010000000000000000001B +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000002020202020202020230 +:10BF0000020202020202000001010101010101011D +:10BF1000010101010101010000000000000000001A +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF000000000000000000202020202020202022F +:10C00000020202020202000001010101010101011C +:10C010000101010101010100000000000000000019 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F000000000000000000202020202020202022E +:10C100000202020202020000000000000000000023 +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C200000000000000000015000000000000000019 +:10C21000000000000000000000000000000001001D +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D000000000000000000000000000000000005E +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000023C +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000101001B +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000023B +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000101001A +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000023A +:10C50000000000000000000000000000000000002B +:10C510000000000000000000000000000101010018 +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F0000000000000000000000000000000000239 +:10C60000000000000000000000000000000000002A +:10C610000000000000000000000000000101010017 +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F0000000000000000000000000000000000238 +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000010101010015 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000237 +:10C800000200000000000000000000000000000026 +:10C810000000000000000000000000010101010014 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000236 +:10C900000200000000000000000000000000000025 +:10C91000000000000000000101010101010101000F +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000235 +:10CA00000202000000000000000000000001000021 +:10CA1000000000000000000101010101010101000E +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000234 +:10CB0000020202020000000000000000000100001C +:10CB1000000000000001010101010101010101000B +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000233 +:10CC0000020202020000000000000000000100001B +:10CC10000000000001010101010101010101010009 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000054 +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000232 +:10CD00000202020202000000000000000001000018 +:10CD10000000000001010101010101010101010008 +:10CD20000000000000000000000000000000000003 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000231 +:10CE00000202020202020200000000000001000013 +:10CE10000000010101010101010101010101010005 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000230 +:10CF00000202020202020200000000000001000012 +:10CF10000001010101010101010101010101010003 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF000000000000000000000000000000000022F +:10D000000202020202020202020202000002000008 +:10D010000001010101010101010101010101010002 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F000000000000000000000000000000000022E +:10D100000202020202020202020202000002000007 +:10D110000101010101010101010101010101010000 +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000022D +:10D200000202020202020202020202020102000003 +:10D2100001010101010101010101010101010100FF +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000022C +:10D300000202020202020202020202020202000001 +:10D3100001010101010101010101010101010100FE +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000022B +:10D400000202020202020202020202020202000000 +:10D4100001010101010101010101010101010100FD +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000022A +:10D5000002020202020202020202020202020000FF +:10D5100001010101010101010101010101010100FC +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F0000000000000000000000000000000000229 +:10D6000002020202020202020202020202020000FE +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000001504 +:10D710000000000000000000000000000000000009 +:10D7200000000000000101000000000000000000F7 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000002000000000000000016 +:10D810000000000000000000000000000000000008 +:10D8200000000001010101000000000000000000F4 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000002000000000000000015 +:10D910000000000100000000000000000000000006 +:10D9200000000001010101000000000000000000F3 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000002000000000000000014 +:10DA10000000000100010000000000000000000004 +:10DA200000000101010101000000000000000000F1 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000002000000000000000013 +:10DB10000000000101010000000000000000000002 +:10DB200000010101010101000000000000000000EF +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000002000000000000000012 +:10DC10000000000101010000000000000000000001 +:10DC200001010101010101000000000000000000ED +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD0000000000000000000202000000000000000F +:10DD10000000000101010000000000000000000000 +:10DD200001010101010101000000000000000000EC +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE0000000000000000000202000000000000000E +:10DE100000000001010100000000000000010101FC +:10DE200001010101010101000000000000000000EB +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000002020202020000000007 +:10DF100000000001010100000000000000010101FB +:10DF200001010101010101000000000000000000EA +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000000000000000000000000051 +:10DFD0000000000000000000000000000000000041 +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000002020202020200000004 +:10E0100000000001010100000000000000010101FA +:10E0200001010101010101000000000000000000E9 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D0000000000000000000000000000000000040 +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E100000000000000000002020202020200000003 +:10E1100000000001010100000000000000010101F9 +:10E1200001010101010101000000000000000000E8 +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E200000000000000000002020202020200000002 +:10E2100000000002010100000000000000010101F7 +:10E2200001010101010101000000000000000000E7 +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E300000000000000000002020202020201000000 +:10E3100000000102020200000000000001010101F2 +:10E3200001010101010101000000000000000000E6 +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E4000000000000000000020202020202020000FE +:10E4100000000102020200000001010101010101EE +:10E4200001010101010101000000000000000000E5 +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E5000000000000000000020202020202020202F9 +:10E5100001000102020200000001010101010101EC +:10E5200001010101010101000000000000000000E4 +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E6000000000000000000020202020202020202F8 +:10E6100002010202020200000101010101010101E7 +:10E6200001010101010101000000000000000000E3 +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E7000000000000000000020202020202020202F7 +:10E7100002020202020200000101010101010101E5 +:10E7200001010101010101000000000000000000E2 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E8000000000000000000020202020202020202F6 +:10E8100002020202020200000101010101010101E4 +:10E8200001010101010101000000000000000000E1 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E9000000000000000000020202020202020202F5 +:10E9100002020202020200000101010101010101E3 +:10E9200001010101010101000000000000000000E0 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000000000000000000000037 +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA000000000000000000020202020202020202F4 +:10EA100002020202020200000101010101010101E2 +:10EA200001010101010101000000000000000000DF +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000000000000000000000036 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB000000000000000000020202020202020202F3 +:10EB100002020202020200000000000000000000E9 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000000000000000000000035 +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000150000000000000000DF +:10EC200000000000000000000000000000010100E2 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000000000000000000000034 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000201 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000101010100DF +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000200 +:10EE100000000000000000000000000101000000F0 +:10EE200000000000000000000000000101010100DE +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF000000000000000000000000000000000002FF +:10EF100000000000000000000000000101010000EE +:10EF200000000000000000000000010101010100DC +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F0000000000000000000000000000000000002FE +:10F0100000000000000000000000000101010000ED +:10F0200000000000000000000101010101010100D9 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000002FD +:10F1100000000000000000000000000101010000EC +:10F1200000000000000000010101010101010100D7 +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000002FC +:10F2100002000000000000000000010101010000E8 +:10F2200000000000000001010101010101010100D5 +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000002FB +:10F3100002000000000000000000010101010000E7 +:10F3200000000000000001010101010101010100D4 +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000002FA +:10F4100002020200000000000000010101010000E2 +:10F4200000000000000101010101010101010100D2 +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000002F9 +:10F5100002020202020000000000010101010000DD +:10F5200000000000000101010101010101010100D1 +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000002F8 +:10F6100002020202020000000000010101010000DC +:10F6200000000000000101010101010101010100D0 +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000002F7 +:10F7100002020202020000000100010202010000D8 +:10F7200000000000000101010101010101010100CF +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000002F6 +:10F8100002020202020000010100020202020000D4 +:10F8200000000001010101010101010101010100CC +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000002F5 +:10F9100002020202020201010101020202020000CF +:10F9200000010101010101010101010101010100C9 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000000000000000000000000000037 +:10F9D0000000000000000000000000000000000027 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000000000000000000000000000000000002F4 +:10FA100002020202020202020201020202020000CB +:10FA200000010101010101010101010101010100C8 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC0000000000000000000000000000000000036 +:10FAD0000000000000000000000000000000000026 +:10FAE0000000000000000000000000000000000016 +:10FAF0000000000000000000000000000000000006 +:10FB000000000000000000000000000000000002F3 +:10FB100002020202020202020202020202020000C9 +:10FB200001010101010101010101010101010100C6 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000055 +:10FBB0000000000000000000000000000000000045 +:10FBC0000000000000000000000000000000000035 +:10FBD0000000000000000000000000000000000025 +:10FBE0000000000000000000000000000000000015 +:10FBF0000000000000000000000000000000000005 +:10FC000000000000000000000000000000000002F2 +:10FC100002020202020202020202020202020000C8 +:10FC200001010101010101010101010101010100C5 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000000000000000000000000000000000034 +:10FCD0000000000000000000000000000000000024 +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000004 +:10FD000000000000000000000000000000000002F1 +:10FD100002020202020202020202020202020000C7 +:10FD200001010101010101010101010101010100C4 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000002F0 +:10FE100002020202020202020202020202020000C6 +:10FE200001010101010101010101010101010100C3 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000002EF +:10FF100002020202020202020202020202020000C5 +:10FF200001010101010101010101010101010100C2 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:0200000290006C +:1000000000000000000000000000000000000002EE +:1000100002020202020202020202020202020000C4 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000015CA +:1001200000000000000000000000000000000000CF +:1001300000000000000101000000000000000000BD +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000020000000000000000DC +:1002200000000000000000000000000000000000CE +:1002300000000000010101000000000000000000BB +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000020000000001000000DA +:1003200000000100010000000000000000000000CB +:1003300000000001010101000000000000000000B9 +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000020000000001000000D9 +:1004200000000101010100000000000000000000C8 +:1004300000000101010101000000000000000000B7 +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000020000000001000000D8 +:1005200000000101010100000000000000000000C7 +:1005300001010101010101000000000000000000B4 +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000020000000001000000D7 +:1006200000000101010100000000000000000001C5 +:1006300001010101010101000000000000000000B3 +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000020200000001000000D4 +:1007200000000101010100000000000000000001C4 +:1007300001010101010101000000000000000000B2 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000020200000001000000D3 +:1008200001000101010100000000000001000101C0 +:1008300001010101010101000000000000000000B1 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000020202020002000000CD +:1009200001000101010100000000000001000101BF +:1009300001010101010101000000000000000000B0 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000020202020202000000CA +:100A200001000101010100000000000001010101BD +:100A300001010101010101000000000000000000AF +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000020202020202000000C9 +:100B200001000201010100000000000001010101BB +:100B300001010101010101000000000000000000AE +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000000000000000000000E4 +:100C100000000000000000020202020202000000C8 +:100C200001000202020100000000000001010101B8 +:100C300001010101010101000000000000000000AD +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000000E3 +:100D100000000000000000020202020202020001C4 +:100D200002000202020200000000000101010101B4 +:100D300001010101010101000000000000000000AC +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000000000000000000000073 +:100D80000000000000000000000000000000000063 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000000000000000000023 +:100DD0000000000000000000000000000000000013 +:100DE0000000000000000000000000000000000003 +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000020202020202020001C3 +:100E200002010202020200000001010101010101B0 +:100E300001010101010101000000000000000000AB +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000020202020202020202BF +:100F200002010202020200000001010101010101AF +:100F300001010101010101000000000000000000AA +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000020202020202020202BE +:1010200002020202020200000101010101010101AC +:1010300001010101010101000000000000000000A9 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000020202020202020202BD +:1011200002020202020200000101010101010101AB +:1011300001010101010101000000000000000000A8 +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000020202020202020202BC +:1012200002020202020200000101010101010101AA +:1012300001010101010101000000000000000000A7 +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000020202020202020202BB +:1013200002020202020200000101010101010101A9 +:1013300001010101010101000000000000000000A6 +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000020202020202020202BA +:1014200002020202020200000101010101010101A8 +:1014300001010101010101000000000000000000A5 +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000000000000000000001C +:1014D000000000000000000000000000000000000C +:1014E00000000000000000000000000000000000FC +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000020202020202020202B9 +:1015200002020202020200000000000000000000AF +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000581609000000000060E3 +:10163000AF09000000000068370A000000000070D9 +:101640009D0A000000000078020B000000000080EE +:10165000560B000000000088940B00000000009072 +:10166000CF0B000000000098060C0000000000A056 +:10167000390C0000000000A86C0C0000000000B055 +:10168000AA0C0000000000B8FD0C0000000000C023 +:10169000500D000000000099000000000000000054 +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C0000000000000000000000001000101010016 +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000178 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000100010001000100000000000045 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000000001000101010015 +:1017D0000000000000000000000000000000000009 +:1017E00000000000000000000000000000000100F8 +:1017F00000000000000000000000000001000000E8 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000177 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000100010001010100000001000042 +:1018A0000000000000000000000000000001000037 +:1018B0000100000000000000010000000001010024 +:1018C0000000000000000000000001000101010014 +:1018D0000000000000000000000000010000000007 +:1018E00000000000000000000000000100000100F6 +:1018F00000000000000000000000000001000000E7 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000176 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000100010001010100010001000040 +:1019A0000000000000000000000000000001000036 +:1019B0000100000000000000010000000001010023 +:1019C0000000000000000100000001000101010012 +:1019D0000000000000000000000000010100010004 +:1019E00000000000000000000000000101000100F4 +:1019F00000000000000000000000000001000100E5 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000010095 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000175 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A9000010000010001000101010001000100003E +:101AA0000100000000000000000000000001000133 +:101AB0000100000000000000010000000001010022 +:101AC0000000000000000100000001000101010011 +:101AD0000000000000000000000000010100010003 +:101AE00000000000000000000000000101000100F3 +:101AF00000000000000000000000000001000100E4 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000010094 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000174 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B9000010100010001010101010001000100003B +:101BA0000100000000010000000000000001000131 +:101BB0000100000000000000010000000001010021 +:101BC000000000000000010000000101010101010E +:101BD0000100000000000000000000010101010000 +:101BE00000000000000000000000000101000100F2 +:101BF00000000000000000000000000001000100E3 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000100C3 +:101C200000000000000000000100000000000100B2 +:101C300000000000000000000000000000000100A3 +:101C40000000000000000000000000000000010093 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000173 +:101C70000000000000000000000000000000000064 +:101C80000000000000000000000000000000000054 +:101C90000101000100010101010101010001000039 +:101CA0000100000000010000000000000001000130 +:101CB0000100000000000000010000000001010020 +:101CC000000000000000010000000101010101010D +:101CD00001000000000000000000000101010100FF +:101CE00000000000000000000000000101000100F1 +:101CF00000000000000000000000000001000100E2 +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000100C2 +:101D200000000000000000000100000000000100B1 +:101D300000000000000000000000000000000100A2 +:101D40000000000000000000000000000000010092 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000172 +:101D70000000000000000000000000000000000063 +:101D80000000000000000000000000000000000053 +:101D90000101000100010101010101010001000038 +:101DA000010000000001000000000000000100012F +:101DB000010000000000000001000000000101001F +:101DC000000000000000010000000101010101010C +:101DD00001000000000000000000000101010100FE +:101DE00000000000000000000000010101010100EE +:101DF00000000000000000000000000001000100E1 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000100C1 +:101E200000000000000000000100000000000100B0 +:101E300000000000000000000000000000000100A1 +:101E40000000000000000000000000000000010091 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000171 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000101000100010101010101010101000036 +:101EA000010000000001000000000000000100012E +:101EB000010000000000000001000000010101001D +:101EC000010000000000010000000101010101010A +:101ED00001000000000101000000000101010100FB +:101EE00000000100000000000000010101010100EC +:101EF00000000000010000000000000001000100DF +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000100C0 +:101F200000000000000000000100000000000100AF +:101F300000000000000000000000000000000100A0 +:101F40000000000000000000000000000000010090 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000170 +:101F70000000000000000000000000000000010060 +:101F80000000000000000000000000000000000051 +:101F90000101010101010101010101010101000033 +:101FA000010000000001000000000000000100012D +:101FB000010000000000000001000000010101001C +:101FC0000100000000000100000001010101010109 +:101FD00001000000000101000000000101010100FA +:101FE00000000100000000000000010101010101EA +:101FF00000000000010000000000010001000100DD +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000100BF +:1020200000000000000000000100000000000100AE +:10203000000000000000000000000000000001009F +:10204000000000000000000000000000000001008F +:102050000000000000000000000000000000000080 +:10206000000000000000000000000000000001016E +:10207000000000000000000000000000000001005F +:102080000000000000000000000000000000000050 +:102090000101010101010101010101010101010031 +:1020A000010000000001000000000000000100012C +:1020B000010000000000000001000000010101001B +:1020C0000100000000000100000001010101010108 +:1020D00001000000000101000000000101010100F9 +:1020E00000000100000000000000010101010101E9 +:1020F00000000000010000000000010101000100DB +:1021000000000000000000000000000000000100CE +:1021100000000000000000000000000000000100BE +:1021200000000000000000000100000000000100AD +:10213000000000000000000000000000000001009E +:10214000000000000000000000000000000001008E +:10215000000000000000000000000000000001007E +:10216000000000000000000000000000000001016D +:10217000000000000000000000000000000001005E +:10218000000000000000000000000000000000004F +:102190000101010101010101010101010101010030 +:1021A000010000000001000000000000000100012B +:1021B000010000000000000001000000010101001A +:1021C0000100000000000100000001010101010107 +:1021D00001000000000101000000010101010101F6 +:1021E00000000100000000000000010101010101E8 +:1021F00000000000010000000000010101000100DA +:1022000000000000000000000000000000000100CD +:1022100000000000000000000000000000000100BD +:1022200000000000000000000100000000000100AC +:10223000000000000000000000000000000001009D +:10224000000000000000000000000000000001008D +:10225000000000000000000000000000000001007D +:10226000000000000000000000000000000001016C +:10227000000000000000000000000000000001005D +:10228000000000000000000000000000000000004E +:10229000010101010101010101010101010101012E +:1022A000010000000001000000000000000100012A +:1022B0000100000000000000010000000101010019 +:1022C0000100000000000100010001010101010105 +:1022D00001000000000101000000010101010101F5 +:1022E00000000100000000000000010101010101E7 +:1022F00000000000010000000000010101000101D8 +:1023000000000000000000000000000000000100CC +:1023100000000000000000000000000000000100BC +:1023200000000000000000000100000000000100AB +:10233000000000000000000000000000000001009C +:10234000000000000000000000000000000001008C +:10235000000000000000000000000000000001007C +:10236000000000000000000000000000000001016B +:10237000000000000000000000000000000001005C +:10238000000000000000000000000000000000004D +:10239000010101010101010101010101010101012D +:1023A0000100000000010000000000000001000129 +:1023B0000100010100000000010000000101010016 +:1023C0000100000000000100010001010101010104 +:1023D00001000000000101000000010101010101F4 +:1023E00000000100000000000000010101010101E6 +:1023F00000000000010000000000010101000101D7 +:1024000000000000000000000000000000000100CB +:1024100000000000000000000000000000000100BB +:1024200000000000000000000100000000000100AA +:10243000000000000000000000000000000001009B +:10244000000000000000000000000000000101008A +:10245000000000000000000000000000000001007B +:10246000000000000000000000000000000001016A +:10247000000000000000000000000000000001005B +:10248000000000000000000000000000000001004B +:10249000010101010101010101010101010101012C +:1024A0000100000000010000000000000001000128 +:1024B0000100010100000000010000000101010114 +:1024C0000100000000000100010001010101010103 +:1024D00001000000000101010000010101010101F2 +:1024E00000000100000100000000010101010101E4 +:1024F00000000000010000000000010101000101D6 +:1025000000000000000000000000000000010100C9 +:1025100000000000000000000000000000000100BA +:1025200000000000000000000100000000000100A9 +:10253000000000000000000000000000000001009A +:102540000000000000000000000000000001010089 +:10255000000000000000000000000000000001007A +:102560000000000000000000000000000000010169 +:10257000000000000000000000000000000001005A +:10258000000000000000000000000000000001004A +:10259000010101010101010101010101010101012B +:1025A0000101000000010000000000000001000126 +:1025B0000100010100000000010000000101010113 +:1025C0000100000000000100010001010101010102 +:1025D00001000000000101010000010101010101F1 +:1025E00000000100000100000000010101010101E3 +:1025F00000000000010000000000010101000101D5 +:1026000000000000000000000000000000010101C7 +:1026100000000000000000000000000000000100B9 +:1026200000000000000000000100000000000100A8 +:102630000000000000000000000000000000010099 +:102640000000000000000000000000000001010088 +:102650000000000000000000000000000000010079 +:102660000000000000000000000000000000010168 +:102670000000000000000000000000000000010059 +:102680000000000000000000000000000000010049 +:10269000010101010101010101010101010101012A +:1026A0000101000000010000000000000001000125 +:1026B0000100010100000000010000000101010112 +:1026C0000100000000000100010001010101010101 +:1026D00001000000000101010000010101010101F0 +:1026E00000000100000100000000010101010101E2 +:1026F00000000000010000000000010101000101D4 +:1027000001000000000000000000000000010101C5 +:1027100000000000000000000000000000000100B8 +:1027200000000000000000000100000000000100A7 +:102730000000000000000000000000000000010098 +:102740000000000000000000000000000001010087 +:102750000000000000000000000000000000010078 +:102760000000000000000000000000000000010167 +:102770000000000000000000000000000001010057 +:102780000000000000000000000000000000010048 +:102790000101010101010101010101010101010129 +:1027A0000101000000010000000000000001000124 +:1027B0000100010100000000010000000101010111 +:1027C0000100000000000100010001010101010100 +:1027D00001000000000101010000010101010101EF +:1027E00000000100000100000000010101010101E1 +:1027F00000000000010000000000010101000101D3 +:1028000001000000000000000000000100010101C3 +:1028100000000000000000000000000000000100B7 +:1028200000000000000000000100000000000100A6 +:102830000000000000000000000000000000010196 +:102840000000000000000000000000000001010086 +:102850000000000000000000000000000000010077 +:102860000000000000000000000000000000010166 +:102870000000000000000000000000000001010056 +:102880000000000000000000000000000000010047 +:102890000101010101010101010101010101010128 +:1028A0000101000000010000000000000001000123 +:1028B0000100010100000000010000000101010110 +:1028C00001000000000001000100010101010101FF +:1028D00001000000000101010000010101010101EE +:1028E00000000100000101000000010101010101DF +:1028F00000000000010000000000010101000101D2 +:1029000001000000000000000000000101010101C1 +:1029100000000000000000000000000000000100B6 +:1029200000000000000000000100000000000100A5 +:102930000000000000000000000000000000010195 +:102940000000000000000000000000000001010085 +:102950000000000000000000000000000001010075 +:102960000000000000000000000000000000010165 +:102970000000000000000000000000000001010055 +:102980000000000000000000000000000000010046 +:102990000101010101010101010101010101010127 +:1029A0000101000000010000000000000001000122 +:1029B000020001010000000001000000010101010E +:1029C00001000000000001000100010101010101FE +:1029D00001000000000101010000010101010101ED +:1029E00001000100000101000000010101010101DD +:1029F00000000000010000000000010101000101D1 +:102A000001000000000000000000000101010101C0 +:102A100000000000000000000000000000000100B5 +:102A200000000000000000000100000000010100A3 +:102A30000000000000000000000000000001010193 +:102A40000000000000000000000000000001010084 +:102A50000000000000000000000000000001010074 +:102A60000000000000000000000000000001010163 +:102A70000000000000000000000000000001010054 +:102A80000000000000000000000000000000010045 +:102A90000101010101010101010101010101010126 +:102AA0000101000000010000000000000001000220 +:102AB000020001010000000001000000010101010D +:102AC00001000000000001000100010101010101FD +:102AD00001000000000101010000010101010101EC +:102AE00001000100000101000000010101010101DC +:102AF00000000100010000000001010101000101CE +:102B000001000000000000000000000101010101BF +:102B100000000000000000000000000000000100B4 +:102B200000000000000000000100000000010100A2 +:102B30000000000000000000000000000001010192 +:102B40000000000000000000000000000001010083 +:102B50000000000000000000000000000001010073 +:102B60000000000000000000000000000001010162 +:102B70000000000000000000000000000001010053 +:102B80000000000000000000000000000000010044 +:102B90000101010101010101010101010101010125 +:102BA000010100000001000000000000000100021F +:102BB000020001010000000001000000010101010C +:102BC00001000000000001000100010101010101FC +:102BD00001000000000101010000010101010101EB +:102BE00001000100000101000000010101010101DB +:102BF00000000100010000000001010101000101CD +:102C000001000000000100000000000101010101BD +:102C100000000000000000000000000001000100B2 +:102C200000000000000000000100000000010100A1 +:102C30000000000000000000000000000001010191 +:102C40000000000000000000000000000001010082 +:102C50000000000000000000000000000001010072 +:102C60000000000000000000000000000001010161 +:102C70000000000000000000000000010001010051 +:102C80000000000000000000000000000000010043 +:102C90000101010101010101010101010101010124 +:102CA000010100000001000000000000000100021E +:102CB000020001010000000001000000010101010B +:102CC00001000000000001000100010101010101FB +:102CD00001010000000101010000010101010101E9 +:102CE00001000100000101000000010101010101DA +:102CF00000000100010000000001010101000101CC +:102D000001000000000100000000000101010101BC +:102D100000000000000000000000000001000100B1 +:102D200000000000000000000100000000010100A0 +:102D30000000000000000000000000000001010190 +:102D40000000000000000000000000010001010080 +:102D50000000000000000000000000000001010071 +:102D60000000000000000000000000000001010160 +:102D7000000000000000000000000101000101004F +:102D80000000000000000000000000000000010042 +:102D90000101010101010101010101010101010123 +:102DA000010100000001000000010000000100021C +:102DB000020001010000000001000000010101010A +:102DC00001000000000001000100010101010101FA +:102DD00001010000000101010000010101010101E8 +:102DE00001000100000101000000010101010101D9 +:102DF00000000100010000000001010101010101CA +:102E000001000000000100000000000101010101BB +:102E100000000000000000000000000001010100AF +:102E2000000000000000000001000000010101009E +:102E3000000000000000000000000000000101018F +:102E4000000000000000000000000001000101007F +:102E50000000000000000000000000000001010070 +:102E6000000000000000000000000000000101015F +:102E7000000000000000000000000101000101004E +:102E80000000000000000000000000000001010040 +:102E90000101010101010101010101010101010122 +:102EA000020100000001000000010000000100021A +:102EB0000200010100000000010000000101010109 +:102EC00001000000000001000100010101010102F8 +:102ED00001010000000101010000010101010101E7 +:102EE00001000100000101000000010101010101D8 +:102EF00000000100010000000001010101010101C9 +:102F000001000000000100000000000101010101BA +:102F100000000000000000000000000101010100AD +:102F2000000000000000000001000000010101009D +:102F3000000000000000000000000001000101018D +:102F4000000000000000000000000001000101007E +:102F5000000000000000000000000000000101006F +:102F6000000000000000000000000001000101015D +:102F7000000000000000000000000101010101004C +:102F8000000000000000000000000001000101003E +:102F90000101010101010101010101010101010121 +:102FA0000201000000010000000100000001000219 +:102FB0000201010100000000010000000101010107 +:102FC00001000000000001000100010101010102F7 +:102FD00001010000000101010000010101010101E6 +:102FE00001000100000101000000010101010101D7 +:102FF00000000100010000000001010101010101C8 +:1030000001000000000100000000000101010101B9 +:1030100000000000000000000000000101010100AC +:10302000000000000000000001000000010101009C +:10303000000000000000000000000001000101018C +:10304000000000000000000000000101000101007C +:10305000000000000000000000000001000101006D +:10306000000000000000000000000001000101015C +:10307000000000000000000000000101010101004B +:10308000000000000000000000000001010101003C +:10309000010101010101010101010101010101021F +:1030A0000201000000010000000100000001000218 +:1030B0000201010100000000010000000101010106 +:1030C00001000000000001000100010101010102F6 +:1030D00001010000000101010000010101010101E5 +:1030E00001000100000101000000010101010101D6 +:1030F00000000100010000000001010101010101C7 +:1031000001000000000100000000000101010101B8 +:1031100000000000000000000000000101010100AB +:103120000000000100000000010000010101010099 +:10313000000000000000000000000001000101018B +:10314000000000000000000000000101000101007B +:10315000000000000000000000000001000101006C +:10316000000000000000000000000001000101015B +:10317000000000000000000000000101010101004A +:10318000000000000000000000000001010101003B +:10319000010101010101010101010101010101021E +:1031A0000201000000010000000100000001000217 +:1031B0000201010100000000010000000101010105 +:1031C00001000000000001000100010101010102F5 +:1031D00002010000000101010000010101010101E3 +:1031E00001000100000101000000010101010101D5 +:1031F00000000100010000000001010101010101C6 +:1032000001000000000100000000000101010101B7 +:1032100000000000000000000000000101010100AA +:103220000000000100000000010000010101010098 +:10323000000000000000000000000001000101018A +:10324000000000000000000000000101000101007A +:10325000000000000000000000000001000101006B +:103260000000000000000000000001010001010159 +:103270000000000000000000000001010101010049 +:10328000000000000000000000000001010101003A +:10329000010101010101010101010101010101021D +:1032A0000201000000010000000100000001000216 +:1032B0000201010100000000010000000101010104 +:1032C00001000000000001000100010101010102F4 +:1032D00002010000000101010000010101010101E2 +:1032E00001000100000101000000010101010101D4 +:1032F00000000100010000000001010101010101C5 +:1033000001000000000100000000000101010101B6 +:1033100000000000000000000000000101010100A9 +:103320000000000100000000010000010101010097 +:103330000000000000000000000000010001010189 +:103340000000000000000000000101010001010078 +:103350000000000000000000000001010001010069 +:103360000000000000000000000001010001010158 +:103370000000000000000000000001010101010048 +:103380000000000000000000000000010101010039 +:10339000010101010101010101010101010101021C +:1033A0000201000000010000000100000001000215 +:1033B0000201010100010000010000000101010102 +:1033C00001000000000001000100010101010102F3 +:1033D00002010000000101010000010101010101E1 +:1033E00001000100000101000000010101010101D3 +:1033F00001000100010000000001010101010101C3 +:1034000001000000000100000000000101010101B5 +:1034100000000000000000000000000101010101A7 +:103420000000000100000000010000010101010096 +:103430000000000000000000000001010001010187 +:103440000000000000000000000101010001010077 +:103450000000000000000000000001010001010068 +:103460000000000000000000000001010001010157 +:103470000000000000000000000101010101010046 +:103480000000000000000000000001010101010037 +:10349000010101010101010101010101010101021B +:1034A0000201000000010000000100000001000214 +:1034B00002010201000100000200000001010101FF +:1034C00002000000000001000100010101010102F1 +:1034D00002010000000101010000010101010101E0 +:1034E00001000100000101000000010101010101D2 +:1034F00001000100010000000001010101010101C2 +:1035000001000000000100000000000101010101B4 +:1035100000000000000000000000000101010101A6 +:103520000001000100000000010000010101010094 +:103530000000000000000000000001010001010186 +:103540000000000000000000000101010001010076 +:103550000000000000000000000001010001010067 +:103560000000000000000000000101010001010155 +:103570000000000000000000000101010101010045 +:103580000000000000000000000101010101010035 +:10359000010101010101010101010101010101021A +:1035A0000201000000010000000100000001000213 +:1035B00002010202000100000200000001010102FC +:1035C00002000100000001000100010101010102EF +:1035D00002010000000101010000010101010102DE +:1035E00001000100000101000000010101010102D0 +:1035F00001000100010000000001010101010101C1 +:1036000001000000000100000000000101010101B3 +:1036100000000000000000000000000101010101A5 +:103620000001000100000000010001010101010092 +:103630000000000000000000000001010001010185 +:103640000000000000000000000101010101010074 +:103650000000000000000000000001010001010066 +:103660000000000000000000000101010101010153 +:103670000000000000000000000101010101010044 +:103680000000000000000000000101010101010034 +:103690000101010101010101010101010101010219 +:1036A0000201000000010000000100000001000212 +:1036B00002010202000100000200000001010102FB +:1036C00002000100000001000100010101010102EE +:1036D00002010000000101010000010101010102DD +:1036E00001000101010101000000010101010102CD +:1036F00001000100010000010001010101010101BF +:1037000001000000000100000000000101010101B2 +:1037100000000000000000000000000101010101A4 +:103720000001000100000000010001010101010091 +:103730000000000000000000000001010001010184 +:103740000000000000000000000101010101010172 +:103750000000000000000000000001010001010065 +:103760000000000000000000000101010101010152 +:103770000000000000000000000101010101010043 +:103780000000000000000000000101010101010033 +:103790000101010101010101010101010101010218 +:1037A000020200000002000000010000000100020F +:1037B00002010202000100000200000001010102FA +:1037C00002000100000001000100010101010102ED +:1037D00002010000000101010000010101010102DC +:1037E00001000101010101000000010101010102CC +:1037F00001000100010000010001010101010102BD +:1038000001000000000100000001000101010101B0 +:1038100001000000000000000000000101010101A2 +:10382000000100010000000001000101010101018F +:103830000000000000000000000001010001010183 +:103840000000000000000000000101010101010171 +:103850000000000000000000000101010001010162 +:103860000000000000000000000101010101010151 +:103870000000000000010000000101010101010041 +:103880000000000000000000010101010101010031 +:103890000101010101010101010101010101010217 +:1038A000020200000002000000010000000100020E +:1038B00002020202000100000200000001010102F8 +:1038C00002000100000001000100010101010102EC +:1038D00002010100000101010000010101010102DA +:1038E00001000101010101000000010101010102CB +:1038F00001000100010000010001010101010102BC +:1039000001000000000100000101000101010101AE +:1039100001000000000000000000000101010101A1 +:10392000000100010000000001000101010101018E +:103930000000000000000000000001010001010182 +:103940000000000000000000000101010101010170 +:103950000000000000000000000101010001010161 +:103960000000000000000000000101010101010150 +:10397000000000000001000001010101010101003F +:10398000000000000001000001010101010101002F +:103990000101010101010101010101010101010216 +:1039A000020200000002000000010000000100020D +:1039B00002020202000100000200000001010102F7 +:1039C00002010100000002000100010101010102E9 +:1039D00002010100000101010000010101010102D9 +:1039E00001000201010101000000010101010102C9 +:1039F00001000100010000010001010101010102BB +:103A000001000000000100000101000101010101AD +:103A100001000000000000000000000101010101A0 +:103A2000010100010000000001000101010101018C +:103A30000000000000000000000001010001010181 +:103A4000000000000000000000010101010101016F +:103A50000000000000000000000101010001010160 +:103A6000000000000000000000010101010101014F +:103A7000000000000001000001010101010101003E +:103A8000000000000001000001010101010101002E +:103A90000101010101010101010101010101010215 +:103AA000020200000002000000010000000100020C +:103AB00002020202000100000200000001010102F6 +:103AC00002010100000002000100010101010102E8 +:103AD00002010101000101010000010101010102D7 +:103AE00001000201010101000000010101010102C8 +:103AF00001010100010000010001010101010102B9 +:103B000001000000000100000101000101010101AC +:103B1000010000000000000000000001010101019F +:103B2000010100010000000001010101010101018A +:103B30000000000000000000000001010001010180 +:103B4000000000000000000100010101010101016D +:103B5000000000000000000000010101010101015E +:103B6000000000000001000000010101010101014D +:103B7000000000000001000001010101010101003D +:103B8000000000000001010101010101010101002B +:103B90000101010101010101010101010101010214 +:103BA000020200000002000000010000000100020B +:103BB00002020202000100000200000001010102F5 +:103BC00002010100000002000100010101010102E7 +:103BD00002010101000102010000010101010102D5 +:103BE00001000201010101000000010101010102C7 +:103BF00001010100010000010001010101010102B8 +:103C000002000000000100000101000101010101AA +:103C1000010000000000000000000101010101019D +:103C20000101000100000000010101010101010189 +:103C3000000000000000000000000101000101017F +:103C4000000000000000000101010101010101016B +:103C5000000000000000000000010101010101015D +:103C6000000000000001000001010101010101014B +:103C7000000000000001010101010101010101003A +:103C8000000000000001010101010101010101002A +:103C90000101010101010101010101010101010213 +:103CA000020200000002000000010000000100020A +:103CB00002020202000100000200000001010102F4 +:103CC00002010100000002000100010101010102E6 +:103CD00002010101000202010000010101010102D3 +:103CE00002010201010101000000010101010102C4 +:103CF00001010100010000010001010101010102B7 +:103D000002000000000100000101010101010102A7 +:103D1000010000000000000000000101010101019C +:103D20000101000100000000010101010101010188 +:103D3000000000000000000000010101000101017D +:103D40000000000000010001010101010101010169 +:103D5000000000000000000001010101010101015B +:103D60000000000000010000010101010101010249 +:103D70000000000000010101010101010101010039 +:103D80000000000000010101010101010101010029 +:103D90000101010101010101010101010101010212 +:103DA0000202000000020000000100000001000209 +:103DB00002020202000100000200000001010102F3 +:103DC00002010100000002000100010101010102E5 +:103DD00002020101000202020000010101010102D0 +:103DE00002010201010101000000010101010102C3 +:103DF00001010100020000010001010101010102B5 +:103E000002000000000100000101010101010102A6 +:103E1000010000000000000000000101010101019B +:103E20000101000100000000010101010101010187 +:103E3000000000000000000000010101000101017C +:103E40000100000000010001010101010101010167 +:103E5000000000000000000001010101010101015A +:103E60000000000000010000010101010101010248 +:103E70000000000000010101010101010101010038 +:103E80000000000000010101010101010101010028 +:103E90000101010101010101010101010101010211 +:103EA0000202000000020000000100000001000208 +:103EB00002020202000100000200000001010102F2 +:103EC00002010100000002000100010101010102E4 +:103ED00002020101000202020000010101010102CF +:103EE00002010201010101000000010101010102C2 +:103EF00001010100020000010001010101010102B4 +:103F000002000000000100000101010101010102A5 +:103F10000100000000000000000101010101010199 +:103F20000101000100000000010101010101010186 +:103F3000000000000000000000010101000101017B +:103F40000100000000010001010101010101010166 +:103F50000000000000000000010101010101010159 +:103F60000000000000010101010101010101010245 +:103F70000000000000010101010101010101010037 +:103F80000000000001010101010101010101010026 +:103F90000101010101010101010101010101010210 +:103FA0000202000000020000000100000001000207 +:103FB00002020202000100000200000002020102EF +:103FC00002010100000002000100020101010102E2 +:103FD00002020101000202020000010102010102CD +:103FE00002010201010101000000010101010102C1 +:103FF00001010100020000010001010101010102B3 +:1040000002000000000101000101010101010102A3 +:104010000100000000000000000101010101010198 +:104020000101000100000000010101010101010185 +:104030000000000000000000000101010101010179 +:104040000100000000010001010101010101010165 +:104050000000000000010000010101010101010157 +:104060000000000000010101010101010101010244 +:104070000000000000010101010101010101010135 +:104080000000000001010101010101010101010025 +:10409000010101010101010101010101010101020F +:1040A0000202000000020000000100000001000206 +:1040B00002020202000100000200000002020102EE +:1040C00002010100000002000100020102010102E0 +:1040D00002020101000202020000010202010102CB +:1040E00002010201010101000000010101010102C0 +:1040F00001010101020000010001010101010102B1 +:1041000002000000000101000101010101010102A2 +:104110000100010000000000000101010101010196 +:104120000101010100010000010101010101010182 +:104130000000000000000000000101010101010178 +:104140000101000000010101010101010101010162 +:104150000000000000010000010101010101010156 +:104160000000000000010101010101010101010243 +:104170000000000000010101010101010101010134 +:104180000000010001010101010101010101010023 +:10419000010101010101010101010101010101020E +:1041A0000202010000020000000100000001000204 +:1041B00002020202000100000200000002020102ED +:1041C00002010100000002000200020102010102DE +:1041D00002020101000202020000010202010102CA +:1041E00002010201010101000000010101010102BF +:1041F00001010101020000010001010101010102B0 +:1042000002000000000101000101010101010102A1 +:104210000100010000000000000101010101010195 +:104220000101010100010000010101010101010181 +:104230000100000000000000000101010101010275 +:104240000101000000010101010101010101010161 +:104250000000000000010001010101010101010154 +:104260000000000000010101010101010101010242 +:104270000000010001010101010101010101010131 +:104280000000010001010101010101010101010022 +:10429000020101010101010101010101010101020C +:1042A0000202010000020000000100000002000202 +:1042B00002020202000100000200000002020102EC +:1042C00002010100000002000200020102010102DD +:1042D00002020101000202020000010202010102C9 +:1042E00002010201010201000000010101010102BD +:1042F00001010201020000010001010101010102AE +:1043000002000000000101000101010101010102A0 +:104310000101010000010000000101010101010192 +:104320000101010100010000010101010101010180 +:104330000100000000010000000101010101010273 +:10434000010101010101010101010101010101015D +:104350000000000000010001010101010101010153 +:104360000000010000010101010101010101010240 +:104370000000010001010101010101010101010130 +:10438000000101010101010101010101010101001F +:10439000020101010101010101010101010101020B +:1043A0000202010000020000000100000002000201 +:1043B00002020202000200000200000002020202E9 +:1043C00002010100000002000200020202020102DA +:1043D00002020101000202020000020202010102C7 +:1043E00002010201010202000000010101010102BB +:1043F00002010201020000010001010101010102AC +:10440000020100000001010001010101010101029E +:104410000101010000010000000101010101010191 +:10442000010101010001000001010101010101017F +:104430000100000000010000000101010101010272 +:10444000010101010101010101010101010101015C +:104450000000010000010001010101010101010151 +:10446000010001000001010101010101010101023E +:10447000000001010101010101010101010101012E +:10448000000101010101010101010101010101001E +:10449000020101010101010101010101010101020A +:1044A0000202010000020000000100000002000200 +:1044B00002020202000200000200000002020202E8 +:1044C00002010100000002000200020202020102D9 +:1044D00002020101000202020000020202010102C6 +:1044E00002010201010202000000020202010102B7 +:1044F00002010201020000010001010102010102AA +:10450000020100000001010001010101010101029D +:104510000101010000010000000101010101010190 +:10452000010101010101000001010101010101017D +:10453000010101000001000000010101010101026F +:10454000010101010101010101010101010101015B +:10455000010001000001000101010101010101014F +:10456000010001000101010101010101010101023C +:10457000000001010101010101010101010101012D +:10458000000101010101010101010101010101001D +:104590000201010101010101010101010101010209 +:1045A00002020100000200000001000000020002FF +:1045B00002020202000200000200000002020202E7 +:1045C00002020200000002000200020202020102D6 +:1045D00002020201000202020000020202020102C3 +:1045E00002010201010202000000020202010102B6 +:1045F00002010201020000010001010102010102A9 +:10460000020100000001010001010101010101029C +:10461000010101000001000000010101010101018F +:10462000010101010101000001010101010101017C +:10463000010101000001000000010101010101026E +:10464000010101010101010101010101010101015A +:10465000010101000001010101010101010101014C +:10466000010001000101010101010101010101023B +:10467000000101010101010101010101010101012B +:10468000010101010101010101010101010101001B +:104690000202010101010101010101010101010207 +:1046A00002020100000200000001000000020002FE +:1046B00002020202000200000200000002020202E6 +:1046C00002020200000002000200020202020102D5 +:1046D00002020201000202020000020202020102C2 +:1046E00002010201010202000000020202010102B5 +:1046F00002010201020000010001010102010102A8 +:10470000020100000001010001010101010101029B +:10471000010101010001000000010101010101028C +:10472000010101010101000001010101010101017B +:10473000010101010101000100010101010101026A +:104740000101010101010101010101010101010159 +:10475000010101000001010101010101010101014B +:104760000101010101010101010101010101010238 +:104770000101010101010101010101010101010129 +:10478000010101010101010101010101010101001A +:104790000202010201010101010101010101010205 +:1047A00002020200000200000001000000020002FC +:1047B00002020202000200000200000002020202E5 +:1047C00002020200000002000200020202020102D4 +:1047D00002020202000202020000020202020102C0 +:1047E00002010202010202000000020202010102B3 +:1047F00002010201020000010001010102010102A7 +:104800000201010000010101010101010101010298 +:10481000010101010001000000010101010101028B +:10482000010101010101000001010101010101017A +:104830000101010101010001010101010101010268 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010237 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010019 +:104890000202010201010101010101010101010204 +:1048A00002020200000200000002000000020002FA +:1048B00002020202000200000200000002020202E4 +:1048C00002020200000002000200020202020102D3 +:1048D00002020202000202020000020202020102BF +:1048E00002010202010202000000020202010102B2 +:1048F00002010201020000010001020102010102A5 +:104900000201010000010101010101010101010297 +:10491000010101010001000000010101010101028A +:104920000101010101010000020101010101010178 +:104930000101010101010101010101010101010266 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010236 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010018 +:104990000202010201010101010101010101010203 +:1049A00002020200000200000002000000020002F9 +:1049B00002020202000200000200000002020202E3 +:1049C00002020201000002000200020202020102D1 +:1049D00002020202000202020000020202020102BE +:1049E00002020202010202000000020202010102B0 +:1049F00002010201020000010001020102010102A4 +:104A00000201010101020101010101010101010293 +:104A10000101010100010000000101010101010289 +:104A20000101010101010000020101010101010177 +:104A30000101010101010101010101010101010265 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010235 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010017 +:104A90000202010201010101010101010101010202 +:104AA00002020200000200000002000000020002F8 +:104AB00002020202000200000200000002020202E2 +:104AC00002020201000002000200020202020202CF +:104AD00002020202000202020000020202020202BC +:104AE00002020202020202000000020202010102AE +:104AF00002020201020000010001020102010102A2 +:104B00000201010101020101010101010101010292 +:104B10000201010100010000000101010101010287 +:104B20000101010101010000020101010101010176 +:104B30000101010101010101010101010101010264 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010234 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010016 +:104B90000202020201010101010101010101010200 +:104BA00002020200000200000002000000020002F7 +:104BB00002020202010200000200000002020202E0 +:104BC00002020201000002000200020202020202CE +:104BD00002020202000202020000020202020202BB +:104BE00002020202020202000000020202020102AC +:104BF00002020201020000010001020202010102A0 +:104C00000201010101020101010101010101010291 +:104C10000201010100010000000101010101010286 +:104C20000102010201010000020101010101010272 +:104C30000101010101010101010101010101010263 +:104C40000101010101010101010101010101010253 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010233 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010015 +:104C900002020202010101010101010101010102FF +:104CA00002020200000200000002000000020002F6 +:104CB00002020202020200000200000002020202DE +:104CC00002020201000002000200020202020202CD +:104CD00002020202000202020000020202020202BA +:104CE00002020202020202000000020202020102AB +:104CF000020202010200000100020202020101029E +:104D00000201010101020101010101010101010290 +:104D10000201010100010100000101010101010284 +:104D20000202010201010000020101010101010270 +:104D30000101010101010101010101010101010262 +:104D40000101010101010101010101010101010252 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010232 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010014 +:104D900002020202010101010101010101010102FE +:104DA00002020201000200000002000000020002F4 +:104DB00002020202020200000200000002020202DD +:104DC00002020201000002000200020202020202CC +:104DD00002020202000202020000020202020202B9 +:104DE00002020202020202000000020202020202A9 +:104DF000020202010200000100020202020101029D +:104E0000020101010102010101010101010101028F +:104E10000201010100010100000101010101010283 +:104E2000020201020101000002010101010101026F +:104E30000101010101010101010101010101010261 +:104E40000101010101010101010101010101010251 +:104E50000101010101010101010101010101010241 +:104E60000101010101010101010101010101010231 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010013 +:104E900002020202010201020101010101010102FB +:104EA00002020202000200000002000000020002F2 +:104EB00002020202020200000200000002020202DC +:104EC00002020201000002000200020202020202CB +:104ED00002020202000202020000020202020202B8 +:104EE00002020202020202000000020202020202A8 +:104EF000020202010200000100020202020101029C +:104F0000020101010102010101010101010101028E +:104F10000201010101010100000101010101010281 +:104F2000020201020101010102010101010101026C +:104F30000101010101010101010101010101010260 +:104F40000101010101010101010101010101010250 +:104F50000101010101010101010101010101010240 +:104F60000101010101010101010101010101010230 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010012 +:104F900002020202020201020101010101010102F9 +:104FA00002020202000200000002000000020002F1 +:104FB00002020202020200000200000002020202DB +:104FC00002020201000002000200020202020202CA +:104FD00002020202000202020000020202020202B7 +:104FE00002020202020202000000020202020202A7 +:104FF000020202010200000200020202020101029A +:10500000020101010102010101010101010101028D +:10501000020101010101010001010101010101027F +:10502000020201020101010102010101010101026B +:10503000010101010101010101010101010101025F +:10504000010101010101010101010101010101024F +:10505000010101010101010101010101010101023F +:10506000010101010101010101010101010101022F +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010011 +:1050900002020202020202020201010101010102F6 +:1050A00002020202000200000002000000020002F0 +:1050B00002020202020200000200000002020202DA +:1050C00002020202000002000200020202020202C8 +:1050D00002020202000202020000020202020202B6 +:1050E00002020202020202000000020202020202A6 +:1050F0000202020202000002000202020201020297 +:105100000202010101020101010101020201010289 +:10511000020101010101010001010101010101027E +:10512000020201020101010102010101010101026A +:10513000010101010101010101010101010101025E +:10514000010101010101010101010101010101024E +:10515000010101010101010101010101010101023E +:10516000010101010101010101010101010101022E +:10517000010101010101010101010101010101011F +:105180000101010101010101010101010101010010 +:1051900002020202020202020201010101010102F5 +:1051A00002020202010200000002000000020002EE +:1051B00002020202020200000200000002020202D9 +:1051C00002020202000002000200020202020202C7 +:1051D00002020202000202020000020202020202B5 +:1051E00002020202020202000000020202020202A5 +:1051F0000202020202000002000202020201020296 +:105200000202010101020101010101020201010288 +:10521000020101010101010001010101010101027D +:105220000202010201010101020101010101010269 +:10523000010101010101010101010101010101025D +:10524000010101010101010101010101010101024D +:10525000010101010101010101010101010101023D +:10526000010101010101010101010101010101022D +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101000F +:1052900002020202020202020202010101010102F3 +:1052A00002020202010200000002000000020002ED +:1052B00002020202020200000200000002020202D8 +:1052C00002020202000002000200020202020202C6 +:1052D00002020202000202020000020202020202B4 +:1052E00002020202020202000000020202020202A4 +:1052F0000202020202000002000202020201020295 +:105300000202010101020101010101020202010286 +:10531000020101010101010001010101010101027C +:105320000202010201010101020101010101010268 +:10533000010101010101010101010101010101025C +:10534000020101010101010101010101010101024B +:10535000010101010101010101010101010101023C +:10536000010101010101010101010101010101022C +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101000E +:1053900002020202020202020202010101010102F2 +:1053A00002020202020200000002000000020002EB +:1053B00002020202020202000200000002020202D5 +:1053C00002020202000002000200020202020202C5 +:1053D00002020202000202020000020202020202B3 +:1053E00002020202020202000000020202020202A3 +:1053F0000202020202000002000202020201020294 +:105400000202010101020101020101020202010284 +:10541000020201010101010001010101010101027A +:105420000202010201010101020101010101010267 +:10543000010101010101010101010101010101025B +:10544000020101010101010101010101010101024A +:10545000010101010101010101010101010101023B +:10546000010101010101010101010101010101022B +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101000D +:1054900002020202020202020202010101010102F1 +:1054A00002020202020200000002000000020002EA +:1054B00002020202020202000200000002020202D4 +:1054C00002020202000002000200020202020202C4 +:1054D00002020202000202020000020202020202B2 +:1054E00002020202020202000000020202020202A2 +:1054F0000202020202000002000202020201020293 +:105500000202020101020201020101020202010281 +:105510000202020101010101010101010101010277 +:105520000202010201010101020101010101010266 +:105530000201010101010101010101010101010259 +:105540000201010101010101010101010101010249 +:10555000010101010101010101010101010101023A +:10556000010101010101010101010101010101022A +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101000C +:1055900002020202020202020202010101010102F0 +:1055A00002020202020201000002000000020002E8 +:1055B00002020202020202020200000002020202D1 +:1055C00002020202000002000200020202020202C3 +:1055D00002020202000202020000020202020202B1 +:1055E00002020202020202000000020202020202A1 +:1055F0000202020202000002000202020201020292 +:10560000020202010102020102020102020202027E +:105610000202020101010101010101010201010275 +:105620000202020201010101020101010101010264 +:105630000201010101010101010101010101010258 +:105640000201010101010101010101010101010248 +:105650000101010101010101010101010101010239 +:105660000101010101010101010101010101010229 +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101000B +:1056900002020202020202020202010201010102EE +:1056A00002020202020201000002000000020002E7 +:1056B00002020202020202020200010002020202CF +:1056C00002020202000002000200020202020202C2 +:1056D00002020202000202020000020202020202B0 +:1056E00002020202020202000000020202020202A0 +:1056F0000202020202000002000202020202020290 +:10570000020202020102020102020102020202027C +:105710000202020101010101010101010201020273 +:105720000202020201010101020101010101010263 +:105730000201010101010101010101010101010257 +:105740000202010101010101010101010101010246 +:105750000101010101010101010101010101010238 +:105760000101010101010101010101010101010228 +:105770000101010101010101010101010101010218 +:10578000010101010101010101010101010101000A +:1057900002020202020202020202020201010102EC +:1057A00002020202020201000002000000020002E6 +:1057B00002020202020202020200010002020202CE +:1057C00002020202000002000200020202020202C1 +:1057D00002020202000202020000020202020202AF +:1057E000020202020202020000000202020202029F +:1057F000020202020200000200020202020202028F +:10580000020202020102020102020102020202027B +:105810000202020101010101010101010201020272 +:105820000202020201010101020101010101020261 +:105830000201010101010101010101010101010256 +:105840000202010101010101010101010101010245 +:105850000201010101010101010101010101010236 +:105860000101010101010101010101010101010227 +:105870000101010101010101010101010101010217 +:105880000101010101010101010101010101010009 +:1058900002020202020202020202020201010102EB +:1058A00002020202020202000002000000020002E4 +:1058B00002020202020202020200010002020202CD +:1058C00002020202000002000200020202020202C0 +:1058D00002020202010202020000020202020202AD +:1058E000020202020202020000000202020202029E +:1058F000020202020200000200020202020202028E +:105900000202020202020201020201020202020279 +:10591000020202020101010101010102020102026F +:10592000020202020101010102010101020102025F +:105930000201010101010101010101010101010255 +:105940000202010101010101010101010101010244 +:105950000201010101010101010101010101010235 +:105960000201010101010101010101010101010225 +:105970000101010101010101010101010101010216 +:105980000101010101010101010101010101010008 +:1059900002020202020202020202020201020102E9 +:1059A00002020202020202010002000000020002E2 +:1059B00002020202020202020201010002020202CB +:1059C00002020202010102000200020202020202BD +:1059D00002020202020202020000020202020202AB +:1059E000020202020202020000000202020202029D +:1059F000020202020200000200020202020202028D +:105A00000202020202020201020202020202020277 +:105A1000020202020101010101010102020102026E +:105A2000020202020101010102010101020102025E +:105A30000202010101010101010101010101010253 +:105A40000202010101010101010101010101010243 +:105A50000201010101010101010101010101010234 +:105A60000201010101010101010101010101010224 +:105A70000101010101010101010101010101010215 +:105A80000101010101010101010101010101010007 +:105A900002020202020202020202020202020102E7 +:105AA00002020202020202010002000000020002E1 +:105AB00002020202020202020202020002020202C8 +:105AC00002020202010102000200020202020202BC +:105AD00002020202020202020000020202020202AA +:105AE000020202020202020000000202020202029C +:105AF000020202020201000200020202020202028B +:105B00000202020202020202020202020202020275 +:105B1000020202020101010101010102020102026D +:105B2000020202020101010102010201020102025C +:105B30000202010101010101010101010101010252 +:105B40000202020101010101010101010101020240 +:105B50000201010101010101010101010101010233 +:105B60000201010101010101010101010101010223 +:105B70000101010101010101010101010101010214 +:105B80000101010101010101010101010101010006 +:105B900002020202020202020202020202020102E6 +:105BA00002020202020202020002000000020002DF +:105BB00002020202020202020202020002020202C7 +:105BC00002020202020102000200020202020202BA +:105BD00002020202020202020000020202020202A9 +:105BE000020202020202020000000202020202029B +:105BF000020202020201000200020202020202028A +:105C00000202020202020202020202020202020274 +:105C1000020202020101010101010102020102026C +:105C20000202020202010101020102020202020258 +:105C3000020202010101010101010101010102024F +:105C4000020202020101010101010101010102023E +:105C50000202010101010101010101010101010231 +:105C60000201010101010101010101010101010222 +:105C70000101010101010101010101010101010213 +:105C80000101010101010101010101010101010005 +:105C900002020202020202020202020202020102E5 +:105CA00002020202020202020002000000020002DE +:105CB00002020202020202020202020002020202C6 +:105CC00002020202020102000200020202020202B9 +:105CD00002020202020202020000020202020202A8 +:105CE000020202020202020000000202020202029A +:105CF0000202020202010002000202020202020289 +:105D00000202020202020202020202020202020273 +:105D10000202020201020101010101020202020269 +:105D20000202020202020101020202020202020255 +:105D3000020202010101010101010101010102024E +:105D4000020202020101010101010101010202023C +:105D5000020202010101010101010101010101022F +:105D60000201010101010101010101010101010221 +:105D70000101010101010101010101010101010212 +:105D80000201010101010101010101010101010003 +:105D900002020202020202020202020202020102E4 +:105DA00002020202020202020002000000020002DD +:105DB00002020202020202020202020102020202C4 +:105DC00002020202020102000200020202020202B8 +:105DD00002020202020202020000020202020202A7 +:105DE0000202020202020200000002020202020299 +:105DF0000202020202010002000202020202020288 +:105E00000202020202020202020202020202020272 +:105E10000202020201020101010202020202020266 +:105E20000202020202020101020202020202020254 +:105E3000020202020101010101010101010102024C +:105E40000202020201010101010202020102020238 +:105E5000020202010101010101010101010101022E +:105E6000020202010101010101010101010101021E +:105E70000201010101010101010101010101010210 +:105E80000201010101010101010101010101010002 +:105E900002020202020202020202020202020102E3 +:105EA00002020202020202020002000000020002DC +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202000200020202020202B6 +:105ED00002020202020202020000020202020202A6 +:105EE0000202020202020200000002020202020298 +:105EF0000202020202010002000202020202020287 +:105F00000202020202020202020202020202020271 +:105F10000202020201020101010202020202020265 +:105F20000202020202020101020202020202020253 +:105F3000020202020101010101010102010102024A +:105F40000202020202020102010202020102020234 +:105F5000020202010101010101010101010101022D +:105F6000020202010101010101010101010101021D +:105F7000020101010101010101010101010101020F +:105F80000202010101010101010101010101010000 +:105F900002020202020202020202020202020102E2 +:105FA00002020202020202020002000000020002DB +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202010200020202020202B4 +:105FD00002020202020202020000020202020202A5 +:105FE0000202020202020200000002020202020297 +:105FF0000202020202010002000202020202020286 +:106000000202020202020202020202020202020270 +:106010000202020202020101010202020202020263 +:106020000202020202020101020202020202020252 +:106030000202020201010101010102020102020247 +:106040000202020202020102010202020102020233 +:10605000020202020101010101010101010102022A +:10606000020202010101010101010101010101021C +:10607000020101010101010101010101010101020E +:1060800002020201010101010101010101010100FE +:1060900002020202020202020202020202020102E1 +:1060A00002020202020202020202010002020002D5 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202010200020202020202B3 +:1060D00002020202020202020000020202020202A4 +:1060E0000202020202020200000002020202020296 +:1060F0000202020202010002000202020202020285 +:10610000020202020202020202020202020202026F +:106110000202020202020101010202020202020262 +:106120000202020202020101020202020202020251 +:106130000202020202010101010102020102020245 +:106140000202020202020202020202020102020230 +:106150000202020201010101010102020102020226 +:106160000202020201020101010101010101020218 +:10617000020202010101010101010101010101020B +:1061800002020201010101010101010101010100FD +:1061900002020202020202020202020202020102E0 +:1061A00002020202020202020202020002020002D3 +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020200020202020202B1 +:1061D00002020202020202020000020202020202A3 +:1061E0000202020202020200000002020202020295 +:1061F0000202020202010002000202020202020284 +:10620000020202020202020202020202020202026E +:106210000202020202020201010202020202020260 +:106220000202020202020101020202020202020250 +:106230000202020202020101010102020102020243 +:10624000020202020202020202020202010202022F +:106250000202020201020101010202020102020223 +:106260000202020201020101010202020101020214 +:10627000020202010101010101010101010101020A +:1062800002020202010101010101010101010100FB +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020002020002D2 +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020200020202020202B0 +:1062D00002020202020202020000020202020202A2 +:1062E0000202020202020200000002020202020294 +:1062F0000202020202010002000202020202020283 +:10630000020202020202020202020202020202026D +:10631000020202020202020101020202020202025F +:10632000020202020202010102020202020202024F +:106330000202020202020101010202020102020241 +:10634000020202020202020202020202020202022D +:106350000202020202020101020202020102020220 +:106360000202020202020201010202020102020210 +:106370000202020201020101010102010101010206 +:1063800002020202020201010101010101010100F8 +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020002020002D1 +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020200020202020202AF +:1063D00002020202020202020100020202020202A0 +:1063E0000202020202020200000002020202020293 +:1063F0000202020202020002010202020202020280 +:10640000020202020202020202020202020202026C +:10641000020202020202020101020202020202025E +:10642000020202020202020102020202020202024D +:106430000202020202020101010202020102020240 +:10644000020202020202020202020202020202022C +:10645000020202020202010202020202010202021E +:10646000020202020202020202020202010202020D +:106470000202020201020101010102020101020203 +:1064800002020202020202010101010101010100F6 +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020002020002D0 +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020200020202020202AE +:1064D000020202020202020202000202020202029E +:1064E0000202020202020200000002020202020292 +:1064F000020202020202000201020202020202027F +:10650000020202020202020202020202020202026B +:10651000020202020202020102020202020202025C +:10652000020202020202020202020202020202024B +:10653000020202020202020201020202010202023D +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202010202021C +:10656000020202020202020202020202010202020C +:1065700002020202020202010102020201020202FE +:1065800002020202020202020202010201010100F1 +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020102020002CE +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020201020202020202AC +:1065D000020202020202020202000202020202029D +:1065E0000202020202020200010002020202020290 +:1065F000020202020202000201020202020202027E +:10660000020202020202020202020202020202026A +:10661000020202020202020102020202020202025B +:10662000020202020202020202020202020202024A +:10663000020202020202020201020202010202023C +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202010202021B +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202010200ED +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020002CC +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020001010202020202028E +:1066F000020202020202010201020202020202027C +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:10673000020202020202020202020202010202023A +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202010200EC +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020002CB +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E000020202020202020002010202020202028C +:1067F000020202020202010201020202020202027B +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020200EA +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020002CA +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E000020202020202020002010202020202028B +:1068F0000202020202020102020202020202020279 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020200E9 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020002C9 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020200020202020202020289 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020200E8 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020002C8 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020200E7 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020002C7 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020200E6 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020002C6 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020200E5 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020002C5 +:106DB00002020202020202020102020202020202B4 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020200E4 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020002C4 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020200E3 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020002C3 +:106FB00002020202020202020102020202020202B2 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020200E2 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020002C2 +:1070B00002020202020202020102020101010202B4 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020200E1 +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020201020002C2 +:1071B00001010101010101010101010202020102BB +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020200E0 +:1072900002020202020202020202020202020202CE +:1072A00002020202020102020202020201020002C2 +:1072B00002020202020202020102020101010202B2 +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020200DF +:1073900002020202020202020202020202020202CD +:1073A00002020202020102020202020201020001C2 +:1073B00001010101010101010101010101010102BC +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020102020202010201010002C2 +:1074B00001010101010101010101010101010102BB +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020102020202010101010001C3 +:1075B00001010101010101010101010101010102BA +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020201CB +:1076A00001010101010101010101010101010101CA +:1076B00001010101010101010101010101010102B9 +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020201CA +:1077A00001010101010101010101010101010101C9 +:1077B00001010101010101010101010101010102B8 +:1077C0000202020202020202020202020202020299 +:1077D000020202020202020102020202020202028A +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020201C9 +:1078A00001010101010101010101010101010101C8 +:1078B00001010101010101010101010101010102B7 +:1078C0000202020202020102020202020202020299 +:1078D0000202020202020202020202020102020289 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020201C8 +:1079A00001010101010101010101010101010101C7 +:1079B00001010101010101010101010101010102B6 +:1079C000020202020202020201020202010102029A +:1079D0000202020202020101020202020202020289 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020201C7 +:107AA00001010101010101010101010101010101C6 +:107AB00001010101010101010101010101010102B5 +:107AC0000202020202020102020201010202020299 +:107AD000020202020201020102020101010102028C +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020201C6 +:107BA00001010101010101010101010101010101C5 +:107BB00001010101010101010101010101010102B4 +:107BC000020202020202010201010202010102029A +:107BD0000202020202020101020202020102020288 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020201C5 +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010102B3 +:107CC000020202020202010101020101010102019C +:107CD000020202020201010102010101010102028C +:107CE0000202020202020202020202020202020274 +:107CF0000202020202020202020202020202020264 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020201C4 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101020101010101010102A1 +:107DD0000101010101010101010201010101010291 +:107DE0000202020202020202020202020202020273 +:107DF0000202020202020202020202020202020263 +:107E00000202020202020202020202020202020252 +:107E10000202020202020202020202020202020242 +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020201C3 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010102B1 +:107EC000020202020202010101010101010102019B +:107ED000020202020201010102010101010102028A +:107EE0000202020202020102020202020202020273 +:107EF0000202020202020202020202020202020262 +:107F00000202020202020202020202020202020251 +:107F10000202020202020202020202020202020241 +:107F20000202020202020202020202020202020231 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020201C2 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010290 +:107FE0000202020202010102020201020102020275 +:107FF0000202020202020202020202020202020261 +:108000000202020202020202020202020202020250 +:108010000202020202020202020202020202020240 +:108020000202020202020202020202020202020230 +:108030000202020202020202020202020202020220 +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202020202020202020201C1 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D000010101010101010101010101010101028F +:1080E0000202010202010102020201010102020276 +:1080F0000202020202020202020202020202020260 +:10810000020202020202020202020202020202024F +:10811000020202020202020202020202020202023F +:10812000020202020202020202020202020202022F +:10813000020202020202020202020202020202021F +:10814000020202020202020202020202020202020F +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202020202020202020201C0 +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101028E +:1081E000020201010101010201010101010102027A +:1081F000020202020202020202020202020202025F +:10820000020202020202020202020202020202024E +:10821000020202020202020202020202020202023E +:10822000020202020202020202020202020202022E +:10823000020202020202020202020202020202021E +:10824000020202020202020202020202020202020E +:1082500002020202020202020202020202020202FE +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202020202020202020201BF +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E0000202010101010102010101010101020279 +:1082F0000202020201020202020202020102020260 +:10830000020202020202020202020202020202024D +:10831000020202020202020202020202020202023D +:10832000020202020202020202020202020202022D +:10833000020202020202020202020202020202021D +:10834000020202020202020202020202020202020D +:1083500002020202020202020202020202020202FD +:1083600002020202020202020202020202020202ED +:1083700002020202020202020202020202020202DD +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020201BE +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101027C +:1083F000020202020202020202020202020202025D +:10840000020202020202020202020202020202024C +:10841000020202020202020202020202020202023C +:10842000020202020202020202020202020202022C +:10843000020202020202020202020202020202021C +:10844000020202020202020202020202020202020C +:1084500002020202020202020202020202020202FC +:1084600002020202020202020202020202020202EC +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020201BD +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101027B +:1084F0000202020201020201020101020102020261 +:10850000020202020202020202020202020202024B +:10851000020202020202020202020202020202023B +:10852000020202020202020202020202020202022B +:10853000020202020202020202020202020202021B +:10854000020202020202020202020202020202020B +:1085500002020202020202020202020202020202FB +:1085600002020202020202020202020202020202EB +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020201BC +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F0000202010201020202010202010102020260 +:10860000020202020202020202020202020202024A +:10861000020202020202020202020202020202023A +:10862000020202020202020202020202020202022A +:10863000020202020202020202020202020202021A +:10864000020202020202020202020202020202020A +:1086500002020202020202020202020202020202FA +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202020202DA +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020201BB +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E0000101010101010101010101010101010279 +:1086F0000202020201020201020101020101020260 +:108700000202020202020202020202020202020249 +:108710000202020202020202020202020202020239 +:108720000202020202020202020202020202020229 +:108730000202020202020202020202020202020219 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020201BA +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010102010267 +:108800000202020202020202020202020202020248 +:108810000202020202020202020202020202020238 +:108820000202020202020202020202020202020228 +:108830000202020202020202020202020202020218 +:108840000202020202020202020202020202020208 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202020202020202020202D8 +:1088800002020202020202020202020202020202C8 +:1088900002020202020202020202020202020201B9 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000202010201020201010101010101020261 +:108900000202020202010202020202020202020248 +:108910000202020202020202020202020202020237 +:108920000202020202020202020202020202020227 +:108930000202020202020202020202020202020217 +:108940000202020202020202020202020202020207 +:1089500002020202020202020202020202020202F7 +:1089600002020202020202020202020202020202E7 +:1089700002020202020202020202020202020202D7 +:1089800002020202020202020202020202020202C7 +:1089900002020202020202020202020202020201B8 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A0000010202020202010201020202010202024A +:108A10000202020202020202020202020202020236 +:108A20000202020202020202020202020202020226 +:108A30000202020202020202020202020202020216 +:108A40000202020202020202020202020202020206 +:108A500002020202020202020202020202020202F6 +:108A600002020202020202020202020202020202E6 +:108A700002020202020202020202020202020202D6 +:108A800002020202020202020202020202020202C6 +:108A900002020202020202020202020202020201B7 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010265 +:108B0000020202020201020102010101020102024B +:108B10000202020202020202020202020202020235 +:108B20000202020202020202020202020202020225 +:108B30000202020202020202020202020202020215 +:108B40000202020202020202020202020202020205 +:108B500002020202020202020202020202020202F5 +:108B600002020202020202020202020202020202E5 +:108B700002020202020202020202020202020202D5 +:108B800002020202020202020202020202020202C5 +:108B900002020202020202020202020202020201B6 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C0000010202020101010201020202010202024A +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202020202020202020202C4 +:108C900002020202020202020202020202020201B5 +:108CA00001010101010101010101010101010101B4 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010102010101010101010101010251 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202020202D3 +:108D800002020202020202020202020202020202C3 +:108D900002020202020202020202020202020201B4 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E0000010202020101010101010101010102014E +:108E10000202020202020202020202020102020233 +:108E20000202020202020202010202020202020223 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202020202020202020202C2 +:108E900002020202020202020202020202020201B3 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000202020202020202020202020102020232 +:108F20000202020102020202010202020202020223 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202020202020202020202D1 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020201B2 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000202020202020202010101010102020235 +:109020000201020102020202010201020102020225 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020201B1 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:109120000201020102020202010101020102020225 +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020201B0 +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101022D +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020201AF +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101022C +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020201AE +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101022B +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020201AD +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101022A +:10953000020202020202020202020202020202010C +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020201AC +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000020202020202020202020202020202010B +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020201AB +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010228 +:10973000020202020202020202020202020202010A +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020201AA +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:1098400002010202020202020202020202020202F9 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020201A9 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000202020202020202020202020202020108 +:109940000101010101010101010101010101010107 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020201A8 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020201A7 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020201A6 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020201A5 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600002020202020202020202020202020201D4 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020201A4 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600002020202020202020202020202020201D3 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020201A3 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020201A2 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020201A1 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A1900002020202020202020202020202020201A0 +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202019F +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010101DD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202019E +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101011C +:10A43000010101010101010101010101010101010C +:10A4400001010101010101010101010101010101FC +:10A4500001010101010101010101010101010101EC +:10A4600001010101010101010101010101010101DC +:10A4700001010101010101010101010101010102CB +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202019D +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E000010101010101010101010101010101015C +:10A4F000010101010101010101010101010101014C +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A53000010101010101010101010101010101010B +:10A5400001010101010101010101010101010101FB +:10A5500001010101010101010101010101010101EB +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800002020202020202020202020202020202AB +:10A5900001010201020202010102020202020201A1 +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010101010101015B +:10A5F000010101010101010101010101010101014B +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000010101010101010101010101010101011A +:10A63000010101010101010101010101010101010A +:10A6400001010101010101010101010101010101FA +:10A6500001010101010101010101010101010101EA +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010102C9 +:10A6800001010101010101010101010101010102B9 +:10A6900001010101010101010101020102010201A7 +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E000010101010101010101010101010101015A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800002020202020202020202020202020202A9 +:10A7900001010101010101010101010101010201A8 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010102B7 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010102B6 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010102B5 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB10000101010101010101010101010101010125 +:10AB20000101010101010101010101010101010115 +:10AB30000101010101010101010101010101010105 +:10AB400001010101010101010101010101010101F5 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010101C5 +:10AB800001010101010101010101010101010102B4 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010294 +:10ABB0000202020202020202020202020202020077 +:10ABC0000000000000000000000000000000000283 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020037 +:10AC00000000000000000000000000000000000242 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020006 +:10AC30000000000000000000000000000000000212 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020200B6 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000001B3 +:10ACA0000101010101010101010101010101010095 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000231 +:10AD20000202020202020202020202020202020005 +:10AD30000000000000000000000000000000000211 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020200C5 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000001B2 +:10ADA0000101010101010101010101010101010094 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000230 +:10AE20000202020202020202020202020202020004 +:10AE30000000000000000000000000000000000210 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020200C4 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF90000000000000000000000000000000008829 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B00000000000000000010000000000000000003F +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000100000000AF +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C000000000000000000000000000000001007F +:10B0D000000000000000000100000000000000006F +:10B0E0000000000000000000000000000000000060 +:10B0F000000000000000000000000100000000004F +:10B10000000000000000010100000000000000003D +:10B11000000000000000000100000000000000002E +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000100010101010100A9 +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000010000000000010000000000000001007C +:10B1D000000000000000010100000000000000006D +:10B1E000000000000000000100000100000000005D +:10B1F000000000010000000000000100000000004D +:10B20000000000000000010100000000000000003C +:10B21000000000000000000100000000000000002D +:10B22000000000000000010000000000000000001D +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000100010101010100A8 +:10B2A000000000000000000000000000000000009E +:10B2B000000100000001000000000000000000008C +:10B2C000010000000000010000000000000001007B +:10B2D000000000000000010100000000000100006B +:10B2E000000000000000000100000100000000005C +:10B2F000000000010000010100000100000000004A +:10B30000000000000000010100000000000000003B +:10B31000000000000000000100000000000000002C +:10B32000000000000000010000000000000000001C +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000001000000000000000000CC +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000101010101010100A6 +:10B3A000000000000000000000000000000000009D +:10B3B000000100000001000000000000000000008B +:10B3C000010000000000010000000000000001007A +:10B3D000000000000000010100000000000100006A +:10B3E000000000000000010100000100000000005A +:10B3F0000000000100000101000001000000000049 +:10B40000000000000000010100000000000000003A +:10B41000000000000000000100000000000000002B +:10B42000000000000000010000000000000000001B +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000001000000000000000000EB +:10B4600000000000000000000000000000000000DC +:10B4700000000000000001000000000000000000CB +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000101010101010100A5 +:10B4A000000000000000000101000000000000009A +:10B4B0000001000000010001000000000000000089 +:10B4C0000100000000000100000000000000010079 +:10B4D0000000000000000101000000000001000069 +:10B4E0000000000000000101000001000000000059 +:10B4F0000000000100000101000001000000000048 +:10B500000000000100000101000000000000000038 +:10B51000000000000000000100000000000000002A +:10B52000000000000000010000000000000000001A +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000001000000000000000000EA +:10B5600000000000000000000000000000000000DB +:10B5700000000000000001000000000000000000CA +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000101010101010100A4 +:10B5A0000000000000000001010000000000000099 +:10B5B0000001000000010001000000000000000088 +:10B5C0000100000000000100000000000000010078 +:10B5D0000000000000000101000000000001000068 +:10B5E0000000000000000101000001000000000058 +:10B5F0000000000100000101000001000000000047 +:10B600000000000100000101000000000000000037 +:10B610000000000000000001000000000000000029 +:10B620000000000000000100000000000000000019 +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000001000000000000000000E9 +:10B6600000000000000000000000000000000000DA +:10B6700000000000000001000000000000000000C9 +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000101010101010100A3 +:10B6A0000000000000000101010000000000000097 +:10B6B0000001000000010001000000000000000087 +:10B6C0000100000100010100000000000000010075 +:10B6D0000000000000000101000000000001000067 +:10B6E0000000000000000101000001000000000057 +:10B6F0000000000100000101000001000000000046 +:10B700000000000100000101000000000000000036 +:10B710000000000000000001000000000000000028 +:10B720000000000000000100000000000000000018 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000001000000000000000000E8 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000001000000000000000000C8 +:10B7800000000000000001000000000000000000B8 +:10B7900000000000000000000101010101010100A2 +:10B7A0000000000000000101010000000000000096 +:10B7B0000001000000010001000000000000000086 +:10B7C0000100000100010100000000000000010074 +:10B7D0000100010000000101000000000001000064 +:10B7E0000000000001000101000001000001000054 +:10B7F0000000000100000101000001000000000045 +:10B800000000000100000101000000000000000035 +:10B810000000000000000001000000000000000027 +:10B820000000000000000100000000000000000017 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000001000000000000000000E7 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000001000000000000000000C7 +:10B8800000000000000001000000000000000000B7 +:10B8900000000000000000000101010101010100A1 +:10B8A0000000000000000101010100000000000094 +:10B8B0000001000000010001000000000000000085 +:10B8C0000100000100010100000000000000010073 +:10B8D0000100010000000101000000000001000063 +:10B8E0000000000001000101000001000001000053 +:10B8F0000000000100000101000001000000000044 +:10B900000000000100000101000000000000000034 +:10B910000000000000000001000000000000000026 +:10B920000000000000000100000000000000000016 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000001000000000000000000E6 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000001000000000000000000C6 +:10B9800000000000000001000000000000000000B6 +:10B9900000000000000000000101010101010100A0 +:10B9A0000000000000010101010100000000000092 +:10B9B0000001000000010001000000000000000084 +:10B9C0000100000100010100000000000000010072 +:10B9D0000100010000000101000000000001000062 +:10B9E0000000000001000101000001000001000052 +:10B9F0000000000100000101000001000000000043 +:10BA00000000000100000101000000000000000033 +:10BA10000000000000000101000000000000000024 +:10BA20000000000000000100000000000000000015 +:10BA30000100000000000000000000000000000005 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000001000000000000000000E5 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000001000000000000000000C5 +:10BA800000000000000001000000000000000000B5 +:10BA9000000000000000000001010101010101009F +:10BAA0000000000000010101010100000000000091 +:10BAB0000001000000010001000000000100000082 +:10BAC0000100000100010100000000000000010071 +:10BAD0000100010000000101000000000001010060 +:10BAE0000000000001000101000001000001000051 +:10BAF0000000000100000101000001000100000041 +:10BB00000000000100000101010000000000000031 +:10BB10000000000000000101000000000000000023 +:10BB20000000000000010100000000000000000013 +:10BB30000100000000000000000000000000000004 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000101000000000000000000E3 +:10BB600000000000000001000000000000000000D4 +:10BB700000000000000001000000000000000000C4 +:10BB800000000000000001000000000000000000B4 +:10BB9000000000000000000001010101010101009E +:10BBA0000000000000010101010100000000000090 +:10BBB0000001000001010001000000000100000080 +:10BBC000010001010001010000000000000001006F +:10BBD000010001000100010100000000000101005E +:10BBE0000000000001000101000001000001000050 +:10BBF0000000000100000101000001000100000040 +:10BC00000000000100000101010000000000000030 +:10BC10000000000000000101000000000000000022 +:10BC20000000000000010100000000000000000012 +:10BC30000100000000000100000000000000000002 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000101000000000000000000E2 +:10BC600000000000000001000000000000000000D3 +:10BC700000000000000101000000000000000000C2 +:10BC800000000000000001000000000000000000B3 +:10BC9000000000000000000001010101010101009D +:10BCA000000001000101010101010000000000008D +:10BCB000000100000101000100000000010000007F +:10BCC000010001010001010000000000000001006E +:10BCD000010001000101010100000000000101005C +:10BCE000000000000100010100000101000100004E +:10BCF000000000010000010100000100010000003F +:10BD0000000000010001010101000000000000002E +:10BD10000000000000000101000000000000000021 +:10BD20000000000000010100000000000000000011 +:10BD30000100000000000100000000000000000001 +:10BD400000000000000001000000000000000000F2 +:10BD500000000000000101000000000000000000E1 +:10BD600000000000000001000000000000000000D2 +:10BD700000000000000101000000000000000000C1 +:10BD800000000000000001000000000000000000B2 +:10BD9000000000000000000001010101010101009C +:10BDA000000101000101010101010000000000008B +:10BDB000000100000101000100000000010000007E +:10BDC000010001010001010000000000000001006D +:10BDD000010001000101010100000000000101005B +:10BDE000000000000100010100000101000100004D +:10BDF000000000010000010100000100010000003E +:10BE0000000000010001010101000000000000002D +:10BE10000000000000000101000000000000000020 +:10BE20000000000000010100000000000000000010 +:10BE30000100000000000100000000000000000000 +:10BE400000000000000001000000000000000000F1 +:10BE500000000000000101000000000000000000E0 +:10BE600000000000000001000000000000000000D1 +:10BE700000000000000101000000000000000000C0 +:10BE800000000000000101000000000000000000B0 +:10BE9000000000000000000001010101010101009B +:10BEA000000101000101010101010000000000008A +:10BEB000000100000101000100000100010000007C +:10BEC0000100010100010101000100000001010069 +:10BED0000100010001010101010000000001010158 +:10BEE000000100000100010100000101000100004B +:10BEF000000000010100010100000100010000003C +:10BF0000000000010001010101000000000000002C +:10BF1000000000000000010100000000000000001F +:10BF2000000000000001010000010000000000000E +:10BF300001000000000001000000000000000000FF +:10BF400000000000000001000000000000000000F0 +:10BF500000000000000101000000000000000000DF +:10BF600000000000000001000000000000000000D0 +:10BF700000000000000101000000000000000000BF +:10BF800000000000000101000000000000000000AF +:10BF9000000000000000000001010101010101009A +:10BFA0000001010001010101010100000000000089 +:10BFB000000100000101000100000100010000007B +:10BFC0000100010100010101000100000001010068 +:10BFD0000100010001010101010000000001010157 +:10BFE000000100000100010100000101000100004A +:10BFF000000000010100010100000100010000003B +:10C00000000000010001010101000000000000002B +:10C01000000000000000010100000000000000001E +:10C02000000000000001010000010000000000000D +:10C0300001000000000001000000000000000000FE +:10C0400000000000000001000000000000000000EF +:10C0500000000000000101000000000000000000DE +:10C0600000000000000001000000000000000000CF +:10C0700000000000000101000000000000000000BE +:10C0800000000000000101000000000000000000AE +:10C090000000000000000100010101010101010098 +:10C0A0000101010001010101010100000000000087 +:10C0B000000100000101000100000100010000007A +:10C0C0000100010100010101000100000001010067 +:10C0D0000100010001010101010000000001010156 +:10C0E0000001000001000101000001010001000049 +:10C0F000000000010100010100000100010000003A +:10C10000000000010001010101000000000000002A +:10C11000000000000000010100000000000000001D +:10C12000000000000001010000010000000000000C +:10C1300001000000000001000000000000000000FD +:10C1400000000000000001000000000000000000EE +:10C1500000000000000101000000000000000000DD +:10C1600000000000000001000000000000000000CE +:10C1700000000000010101000000000000000000BC +:10C1800000000000010101000000000000000000AC +:10C190000000000000000100010101010101010097 +:10C1A0000101010101010101010100000000000085 +:10C1B0000001000001010001000001000100000079 +:10C1C0000100010100010101000100000001010066 +:10C1D0000100010001010101010000000001010155 +:10C1E0000001000001000101000001010001000048 +:10C1F0000000000101000101000001010100000038 +:10C200000000000100010101010000000000000029 +:10C21000000000000000010100000000000000001C +:10C22000000000000001010000010001000000000A +:10C2300001000000000001000000000000000000FC +:10C2400000000000000001000000000000000000ED +:10C2500000000000000101000000000000000000DC +:10C2600000000000000101000000000000000000CC +:10C2700000000000010101000000000000000000BB +:10C2800000000000010101000000000000000000AB +:10C290000000000000000100010101010101010096 +:10C2A0000101010101010101010100000000000084 +:10C2B0000001000001010001000001000100000078 +:10C2C0000100010100010101010100000001010064 +:10C2D0000100010001010101010000000101010153 +:10C2E0000001000001000101000001010001000047 +:10C2F0000000000101000101000001010100000037 +:10C300000000000100010101010000000001000027 +:10C31000000000000000010100000000000000001B +:10C320000000000000010100000100010000000009 +:10C3300001000000000001000000000000000000FB +:10C3400000000000000001000000000000000000EC +:10C3500000000000000101000000000000000000DB +:10C3600000000000000101000000000000000000CB +:10C3700000000000010101000000000000000000BA +:10C3800000000000010101000000000000000000AA +:10C390000000000000000100010101010101010194 +:10C3A0000101010101010101010100000000000083 +:10C3B0000001000001010001000001000100000077 +:10C3C0000100010101010101010100010001010061 +:10C3D0000100010001010101010000000101010152 +:10C3E0000001000001000101010001010101010043 +:10C3F0000000000101000101000001010100000036 +:10C400000000000100010101010000000001000026 +:10C41000000000000000010100000000000000001A +:10C420000000000000010100000100010000000008 +:10C4300001000000000001000000000000010000F9 +:10C4400000000000000001000000000000000000EB +:10C4500000000000010101000000000000000000D9 +:10C4600000000000000101000000000000000000CA +:10C4700000010000010101000000000000000000B8 +:10C4800000010000010101000000000000000000A8 +:10C490000000000000000100010101010101010193 +:10C4A0000101010101010102010100000000000081 +:10C4B0000001000001010001010001000100000075 +:10C4C0000100010101010101010100010001010060 +:10C4D0000100010101010101010000000101010150 +:10C4E0000001000101010101010001010101010040 +:10C4F0000000000101000101000001010100000035 +:10C500000000000100010101010000000001000025 +:10C510000000000100000101000000000000000018 +:10C520000000000000010100000100010000000007 +:10C5300001000000000001000000000000010000F8 +:10C5400000000000000001000000000000000000EA +:10C5500000000000010101000000000000000000D8 +:10C5600000000000000101000000000000000000C9 +:10C5700000010100010101000000000000000000B6 +:10C5800000010100010101000000000000000000A6 +:10C590000000000000010100010101010101010191 +:10C5A0000101010101010102010100000000000080 +:10C5B0000001000001010001010001000100000074 +:10C5C000010001010101010101010001000101005F +:10C5D000010001010101010201000000010101014E +:10C5E000000100010101010101000101010101013E +:10C5F0000000000101000101000001010100000034 +:10C600000000000100010101010000000001000024 +:10C610000000000100000101000000000000000017 +:10C620000000000000010100000100010000000006 +:10C6300001000000000001000000000000010000F7 +:10C6400000000000000001000000000000000000E9 +:10C6500000000000010101000000000000000000D7 +:10C6600000000000000101000000000000000000C8 +:10C6700000010100010101000000000000000000B5 +:10C6800000010100010101000000000000000000A5 +:10C690000000000000010100010101010101010190 +:10C6A000010101010101010202010100000000007D +:10C6B0000001000001010001010001000100000073 +:10C6C000010001010101010101010001000101005E +:10C6D000010101010101010201000000010101014C +:10C6E000000100010101010101000101010101013D +:10C6F0000000000101000101000001010100000033 +:10C700000000000100010101010000000001010022 +:10C710000000000100000101000000000000000016 +:10C720000000000000010100000100010000000005 +:10C7300001000000000101000000000000010000F5 +:10C7400000000000000001000000000000000000E8 +:10C7500000000000010101000000000000000000D6 +:10C7600000000000000101000000000000000000C7 +:10C7700000010100010101000000000000000000B4 +:10C7800000010100010101000000000000000000A4 +:10C79000000000000001010001010101010101018F +:10C7A000010101010101010202010100000000007C +:10C7B0000001000001010002010001000100000071 +:10C7C000010001010101010101010001000101005D +:10C7D000010101010101010201000000010101014B +:10C7E000000101010101010101000101010101013B +:10C7F0000000000101000101000001010100000032 +:10C800000000000100010101010000000001010021 +:10C810000000000100000101000000000000000015 +:10C820000000000000010100000100010000000004 +:10C8300001000000000101000000000000010000F4 +:10C8400000000000000001000000000000000000E7 +:10C8500000000000010101000000000000000000D5 +:10C8600000000000000101000000000000000000C6 +:10C8700000010101010101000000000000000000B2 +:10C8800000010101010101000000000000000000A2 +:10C89000000000000101010001010101010101018D +:10C8A000010101010101010202010100000000007B +:10C8B0000001000001010002010001000100000070 +:10C8C000010001010101010101010001000101005C +:10C8D000010101010101010201000000010101014A +:10C8E0000001010101010102010001010101010139 +:10C8F000000000010100010101000101010000012F +:10C90000000000010001010101000000010101001F +:10C910000000000100000101000000000000000014 +:10C920000000000000010100000100010000000003 +:10C9300001000000000101000000000000010000F3 +:10C9400000000000000001010000000000000000E5 +:10C9500000010000010101000000000000000000D3 +:10C9600000000000010101000000000000000000C4 +:10C9700000010101010101000000000000000000B1 +:10C9800001010101010101000000000000000000A0 +:10C99000000000000101010001010101010101018C +:10C9A000010101010101010202010100000000007A +:10C9B000000100000101000201000100010000006F +:10C9C000010001010101010101010001000101005B +:10C9D0000101010101010102010000000101010149 +:10C9E0000001010101010102010001010101010138 +:10C9F000000000010100010101000101010000012E +:10CA0000000000010101010101000000010101001D +:10CA10000100000100000101000000010000000011 +:10CA20000000000000010100000100010000000002 +:10CA300001000000000101000000000000010000F2 +:10CA400000000000000101010000000000000000E3 +:10CA500000010000010101000000000000000000D2 +:10CA600000000000010101000000000000000000C3 +:10CA700000010101010101000000000000000000B0 +:10CA8000010101010101010000000000000000009F +:10CA9000000000000101010001010101010101018B +:10CAA0000101010101010102020101000000000079 +:10CAB000000100000101000201000100010000006E +:10CAC0000101010101010101010100010001010059 +:10CAD0000101010101010102010100000101010147 +:10CAE0000001010101010102010001010101010137 +:10CAF000000001010100010201000101010000012B +:10CB0000000100010101010201000000010101001A +:10CB1000010000010000010100000001000100000F +:10CB20000000000100010100000100010000000000 +:10CB300001000001000101000000000000010000F0 +:10CB400000000000000101010001000000000000E1 +:10CB500000010000010101000000000000000000D1 +:10CB600000000000010101000000000000000000C2 +:10CB700000010101010101000000000000000000AF +:10CB8000010101010101010000000000000000009E +:10CB90000001000001010100010101010101010189 +:10CBA0000101010101010102020201000000000077 +:10CBB000000100000101000201000100010000006D +:10CBC0000101010101010101010100010001010058 +:10CBD0000101010101010102010100000101010146 +:10CBE0000001010101010102010101010101010135 +:10CBF0000000010101010102010001010100000129 +:10CC00000001010101010102010000000101010018 +:10CC1000010000010000010200000001000100000D +:10CC200000000001000101000001000100000000FF +:10CC300001000001000101000000000000010000EF +:10CC400000000000000101010001000000000000E0 +:10CC500000010100010101000000000000000000CF +:10CC600000000000010101000000000000000000C1 +:10CC700000010101010101010000000000000000AD +:10CC8000010101010101010000000000000000009D +:10CC90000001000001010100010101010101010188 +:10CCA0000101010101010102020201000000000076 +:10CCB000000100000101000201000100010000006C +:10CCC0000101010101010101010100010001010057 +:10CCD0000101010101010102010100000101010145 +:10CCE0000001010101010102010101010101010134 +:10CCF0000000010101010102010001010100000128 +:10CD00000001010101010102010000000101010017 +:10CD1000010100010000010201000001000100000A +:10CD200000000001000101000001000100000000FE +:10CD300001000001000101000000000000010000EE +:10CD400000000000000101010001000000000000DF +:10CD500000010100010101000000000000000000CE +:10CD600000000000010101000000000000000000C0 +:10CD700001010101010101010000000000000000AB +:10CD8000010101010101010000000000000000009C +:10CD90000001000001010100010101010101010187 +:10CDA0000101010101010102020201000000000075 +:10CDB000000100000101000201000100010000006B +:10CDC0000101010101010101010100010001010056 +:10CDD0000101010101010102010100000101010144 +:10CDE0000001010101010102010102010101010132 +:10CDF0000000010101010102010001010100000127 +:10CE00000001010101010102010000000101010016 +:10CE10000101000100000102010000010001000009 +:10CE200000000001000101000001000100000000FD +:10CE300001000001000101000000000000010000ED +:10CE400000000000000101010001000000000000DE +:10CE500000010100010101000000000000000000CD +:10CE600000010001010101000000000000000000BD +:10CE700001010101010101010000000000000000AA +:10CE8000010101010101010000000000000000009B +:10CE90000001010001010100010101010101010185 +:10CEA0000101010101010102020201000000010073 +:10CEB0000001000001010002010101000100000069 +:10CEC0000101010101010101010100010001010055 +:10CED0000101010101010102010100000101010143 +:10CEE0000001010101010102010102010101010131 +:10CEF0000000010101010102010102010100000124 +:10CF00000001010101010102010000000101010015 +:10CF10000101000100000102010101010001000006 +:10CF200000000001000101000001000100000000FC +:10CF300001000001000101000000000000010000EC +:10CF400000000000000101010101000000000000DC +:10CF500000010101010101000000000000000000CB +:10CF600000010101010101000000000000000000BB +:10CF700001010101010101010000000000000000A9 +:10CF8000010101010101010000000000000000009A +:10CF90000001010101010100010101010101010183 +:10CFA0000101010101010102020201010000010071 +:10CFB0000101000001010002010101000100000067 +:10CFC0000101010101010102010100010001010053 +:10CFD0000101010101010102020100000102010140 +:10CFE0000001010101010102010102010101010130 +:10CFF0000000010101010102010102010100000123 +:10D000000001010101010102010000000101010014 +:10D010000101000100000102010101010001000005 +:10D0200000000001000101000001000100000000FB +:10D0300001000001010101000000000000010000EA +:10D0400000000000000101010101000000000000DB +:10D0500000010101010101000000000000000000CA +:10D0600000010101010101000100000000000001B8 +:10D0700001010101010101010000000000000001A7 +:10D080000101010101010100000000000000000099 +:10D090000101010101010100010101010101010181 +:10D0A000010101010101010202020101010001006F +:10D0B0000101000001010002010102000200000064 +:10D0C0000101010101010102010100010101010051 +:10D0D000010101010101010202010000010201013F +:10D0E000000101010101010201010201010101012F +:10D0F0000000010101010102010102010100000122 +:10D100000001010101010102010001000101010012 +:10D110000101000100000102010101010001000004 +:10D1200000000001000101000001000100000100F9 +:10D1300001000001010101000000000000010000E9 +:10D1400000000000000101010101000000000000DA +:10D1500000010101010101000000000000000000C9 +:10D1600000010101010101000100000000000001B7 +:10D1700001010101010101010000000000000001A6 +:10D180000101010101010100000000000000000098 +:10D190000101010101010100010101010101010180 +:10D1A000010101010101010202020101010001006E +:10D1B0000101000001010002020102000200000062 +:10D1C000020101010101010201020001010102004D +:10D1D000010101010101010202010000010201013E +:10D1E000000101010101010201010201010101012E +:10D1F0000001010101010102010102010100000120 +:10D200000001010101010102020001000101010010 +:10D210000101000100000102010101010001000003 +:10D2200000000001000101000001000100000100F8 +:10D2300001000001010101000000000000010000E8 +:10D2400000000000000101010101000000000000D9 +:10D2500001010101010101000000000000000000C7 +:10D2600000010101010101000100000000000101B5 +:10D2700001010101010101010000000000000001A5 +:10D280000101010101010100000000000000000097 +:10D29000010101010101010001010101010101017F +:10D2A000010101010101010202020101010001006D +:10D2B0000101000001010002020102000200000061 +:10D2C000020101010101010201020101010102004B +:10D2D000010101010101010202010100010201013C +:10D2E000000101010101010201010201010101012D +:10D2F000000101010101010201010201010000011F +:10D30000000101010101010202000100010101000F +:10D310000101000100010102010101010001000001 +:10D3200000010001000101010001000100000100F5 +:10D3300001000001010101000000000000010000E7 +:10D3400000000000000101010101000000000000D8 +:10D3500001010101010101000000000000000000C6 +:10D3600001010101010101000100000000000101B3 +:10D3700001010101010101010000000000000001A4 +:10D380000101010101010100000000000000000096 +:10D39000010101010101010001010101010101017E +:10D3A000010101010101010202020101010001006C +:10D3B0000101000001010002020102000200000060 +:10D3C0000201010101010102020201010101020049 +:10D3D000010101010101010202010100010201013B +:10D3E000000101010101010201010201010101012C +:10D3F000000101010101010201010201010000011E +:10D40000000101010101010202000100010101000E +:10D410000101000100010102010101010001000000 +:10D4200000010001010101010001000100000100F3 +:10D4300001000001010101000000000000010000E6 +:10D4400000000000000101010101000000000000D7 +:10D4500001010101010101000000000000000000C5 +:10D4600001010101010101000100000000000101B2 +:10D4700001010101010101010000000000000101A2 +:10D480000101010101010100000000000000000095 +:10D49000010101010101010001010101010101017D +:10D4A000010101010101010202020201010001006A +:10D4B000010100000101000202010200020000005F +:10D4C0000201010101010102020201010101020048 +:10D4D000010101010101010202010100010201013A +:10D4E0000001010101010102020102020102010128 +:10D4F000000101010101010201010201010000011D +:10D50000000101010101010202000100010101000D +:10D5100001010001000101020101010100010000FF +:10D5200000010001010101010001000100010100F1 +:10D5300001000001010101000000000000010000E5 +:10D5400000000000010101010101000000000000D5 +:10D5500001010101010101000000000000000000C4 +:10D5600001010101010101000100000000000101B1 +:10D5700001010101010101010000000000000101A1 +:10D580000101010101010100000000000000010192 +:10D59000010101010101010001010101010101017C +:10D5A0000101010101010102020202010100010069 +:10D5B000010200000101000202010201020000005C +:10D5C0000201010101010102020201010101020047 +:10D5D0000101010101010102020101000102010139 +:10D5E0000001010101010102020102020102010127 +:10D5F000000101010101010201010201010000011C +:10D60000000101010101010202000100010101000C +:10D6100001010001010101020101010100010000FD +:10D6200000010001010101010001000100010100F0 +:10D6300001000001010101000000000000010000E4 +:10D6400000000000010101010101000000000000D4 +:10D6500001010101010101010000000000000000C2 +:10D6600001010101010101000100000000000101B0 +:10D6700001010101010101010000000000000101A0 +:10D680000101010101010100000000000000010191 +:10D69000010101010101010001010101010101017B +:10D6A0000101010101010102020202010100010167 +:10D6B000010200000101000202010201020000005B +:10D6C0000201010101010102020201010101020046 +:10D6D0000101010101010102020101000102020137 +:10D6E0000001010101010102020102020102010126 +:10D6F000000101010101010201010201010000011B +:10D70000000101010101010202000100010101010A +:10D7100001010001010101020101010100010000FC +:10D7200000010001010101010001000100010100EF +:10D7300001000001010101000000000000010000E3 +:10D7400000000100010101010101010000000001D0 +:10D7500001010101010101010000000000000000C1 +:10D7600001010101010101000100000000000101AF +:10D77000010101010101010100000000000001019F +:10D780000101010101010100000000000000010190 +:10D790000101010101010100020101010101010179 +:10D7A0000101010101010102020202010100010166 +:10D7B000010200000101000202010201020000005A +:10D7C0000201010201010102020201020102020042 +:10D7D0000101010101010102020101010202020233 +:10D7E0000001010101010102020102020102010125 +:10D7F0000001010101010102010102010200000119 +:10D800000001010101010102020001000101010109 +:10D8100001010001010101020101010100010000FB +:10D8200000010001010101010001000100010100EE +:10D8300001000001010101000000000000010000E2 +:10D8400000010100010101010101010000000001CE +:10D8500001010101010101010000010000000000BF +:10D8600001010101010101000100000001000101AD +:10D87000010101010101010100000000010001019D +:10D88000010101010101010000000000000001018F +:10D890000101010101010100020101010101010178 +:10D8A0000101010101010102020202010101010164 +:10D8B0000102000001010002020202010200000058 +:10D8C0000201010201010102020201020102020041 +:10D8D0000101010101010102020201010202020231 +:10D8E0000001010101010102020102020102010124 +:10D8F0000001010101010102020102010200000117 +:10D900000001010101010102020001000101010108 +:10D9100001010001010101020101010100010000FA +:10D9200000010001010101010002000100010100EC +:10D9300001000001010101000000000000010000E1 +:10D9400000010100010101010101010000000001CD +:10D9500001010101010101010000010000000000BE +:10D9600001010101010101000100000001000101AC +:10D97000010101010101010100000000010001019C +:10D98000010101010101010000000000010101018C +:10D990000101010101010100020101010101010177 +:10D9A0000101010101010102020202010101010163 +:10D9B0000102000001020002020202010200000056 +:10D9C0000201010201010102020201020102020040 +:10D9D000020101010101010202020101020202022F +:10D9E0000001010101010102020102020102010123 +:10D9F0000001010201010102020102020200000114 +:10DA00000001010101010102020001010101010106 +:10DA100001010101010101020101010100010000F8 +:10DA200000010001010101010002000100010100EB +:10DA300001000001010101010001000000010001DD +:10DA400000010100010101010101010000000001CC +:10DA500001010101010101010000010000000000BD +:10DA600001010101010101010100000001010101A9 +:10DA70000101010101010101000001000101010199 +:10DA8000010101010101010000000000010101018B +:10DA90000101010101010100020101010101010176 +:10DAA0000101010101010102020202020101010161 +:10DAB0000102000001020002020202010200000055 +:10DAC000020101020101010202020102010202003F +:10DAD000020101010101010202020101020202022E +:10DAE0000001010101010102020202020102010121 +:10DAF0000001010201010102020102020200000113 +:10DB00000001010101010102020001010101010105 +:10DB100001010101010101020101010100010000F7 +:10DB200000010001010101010102000100010100E9 +:10DB300001010001010101010001000000010001DB +:10DB400000010100010101010101010000000101CA +:10DB500001010101010101010000010000000000BC +:10DB600001010101010101010100000001010101A8 +:10DB70000101010101010101000001000101010198 +:10DB80000101010101010101000001000101010188 +:10DB90000101010101010100020201010101010174 +:10DBA0000101010101010102020202020101010160 +:10DBB0000102000002020002020202010200000053 +:10DBC000020102020101010202020102010202003D +:10DBD000020101010101010202020101020202022D +:10DBE000000101010101010202020202020201011F +:10DBF0000001010201010102020102020200000112 +:10DC00000001010101010102020001010101010104 +:10DC100001010101010101020101010100010000F6 +:10DC200000010001010101010102000100010100E8 +:10DC300001010101010101010001000000010001D9 +:10DC400000010100010101020101010000000101C8 +:10DC500001010101010101010000010000000001BA +:10DC600001010101010101010100010001010101A6 +:10DC70000101010101010101010001000101010196 +:10DC80000101010101010101000001010101010186 +:10DC90000101010101010100020202010101010172 +:10DCA000010101010101010202020202010101015F +:10DCB0000102000002020002020202010200000052 +:10DCC000020102020101010202020102010202003C +:10DCD000020102010101010202020101020202022B +:10DCE000000101010201010202020202020201011D +:10DCF0000001010201010102020102020200000111 +:10DD00000001010101010102020101010101010102 +:10DD100001010101010101020101010100010000F5 +:10DD200000010001010101010102000100010100E7 +:10DD300001010101010101010001000000010001D8 +:10DD400000010100010101020101010000000101C7 +:10DD500001010101010101010000010000000001B9 +:10DD600001010101010101010100010101010101A4 +:10DD70000101010101010101010001010101010194 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010100020202020101010170 +:10DDA000010101010101010202020202020101015D +:10DDB0000102000002020002020202010200000051 +:10DDC000020102020101010202020102010202003B +:10DDD000020102010101010202020101020202022A +:10DDE000000201010201010202020202020202011A +:10DDF0000001010201010102020102020200000110 +:10DE00000001010201010102020101010101010100 +:10DE100001010101010101020201010100010000F3 +:10DE200000010101010101010102000200010100E4 +:10DE300001010101010101010101000000010001D6 +:10DE400000010100010101020101010000000101C6 +:10DE500001010101010101010000010000000001B8 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE9000010101010101010002020202010101016F +:10DEA000010101010101010202020202020101015C +:10DEB0000102000002020002020202010200000050 +:10DEC0000201020201020202020201020102020038 +:10DED0000201020101010102020202010202020228 +:10DEE0000002010102010102020202020202020119 +:10DEF000000101020101010202020202020000010E +:10DF000000010102010101020201010101020101FE +:10DF100001010101010101020201010100010100F1 +:10DF200000010101010101010102000200010100E3 +:10DF300001010101010101010101000000010001D5 +:10DF400000010100010101020101010001000101C4 +:10DF500001010101010101010000010000000001B7 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF9000010101010101010002020202010101016E +:10DFA000010101010101010202020202020102015A +:10DFB000010200000202000202020201020000004F +:10DFC0000201020201020202020201020102020037 +:10DFD0000201020101010102020202010202020227 +:10DFE0000002010102010102020202020202020217 +:10DFF000000101020101010202020202020000010D +:10E0000001010102010101020201010101020101FC +:10E0100001010101010101020201010100010100F0 +:10E0200000010101010101010102000200010100E2 +:10E0300001010101010101010101000000010001D4 +:10E0400000010101010101020101010001000101C2 +:10E0500001010101010101010000010000000101B5 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E09000010101010101010002020202020101016C +:10E0A0000101010101010102020202020201020159 +:10E0B000010200000202000202020202020000004D +:10E0C0000201020201020202020202020102020035 +:10E0D0000201020101010102020202010202020226 +:10E0E0000002010202010202020202020202020214 +:10E0F000000101020101010202020202020000010C +:10E1000001010102010101020201010101020101FB +:10E1100001010101010101020202010200010100ED +:10E1200000010101010101020102010200010100DF +:10E1300001010101010101010101000000010001D3 +:10E1400000010101010101020202010001000101BF +:10E1500001010101010101010000010000000101B4 +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010002020202020201016A +:10E1A0000101010101010102020202020201020158 +:10E1B000010200000202000202020202020000004C +:10E1C0000201020201020202020202020202020033 +:10E1D0000201020102010202020202010202020223 +:10E1E0000002010202010202020202020202020213 +:10E1F000000101020101010202020202020000010B +:10E2000001010102010101020201010102020101F9 +:10E2100001010101010101020202010200010100EC +:10E2200000010101010101020102010200010100DE +:10E2300001010101010101010101000000010001D2 +:10E2400000010101010101020202010101000101BD +:10E2500001010101010101010100010000000101B2 +:10E26000010101010101010101010101010101019E +:10E27000010101010101010201010101010101018D +:10E28000010101010101010101010101010101017E +:10E290000101010101010100020202020202010169 +:10E2A0000101010101010102020202020202020156 +:10E2B000020200000202000202020202020000004A +:10E2C0000202020201020202020202020202020031 +:10E2D0000201020202010202020202020202020220 +:10E2E0000002020202010202020202020202020211 +:10E2F0000001010201010202020202020200000109 +:10E3000001010102010102020201020102020101F6 +:10E3100001010101010101020202020201010100E9 +:10E3200000010101010101020102010201010100DC +:10E3300002010101010101010101000000010001D0 +:10E3400000010101010101020202010101010101BB +:10E3500001010101010101010100010000000101B1 +:10E36000010101010101010101010101010101019D +:10E37000010101010101010201010101010101018C +:10E38000010101010101010101010101010101017D +:10E390000101010101010100020202020202020167 +:10E3A0000101010101010102020202020202020155 +:10E3B0000202000002020002020202020200000049 +:10E3C000020202020202020202020202020202002F +:10E3D000020202020202020202020202020202021D +:10E3E0000002020202010202020202020202020210 +:10E3F0000001010202010202020202020200000206 +:10E4000001010102010102020201020102020201F4 +:10E4100001010101010101020202020201010100E8 +:10E4200000010101010101020102010201010100DB +:10E4300002010101010101010101010001020001CC +:10E4400000010101010101020202010101010101BA +:10E4500001010101010101010101010001010101AD +:10E46000010101010101010101010101010101019C +:10E47000010101010101010201010101010101018B +:10E48000010101010101010101010101010101017C +:10E490000101010101010100020202020202020166 +:10E4A0000101010101010102020202020202020253 +:10E4B0000202000002020002020202020201000047 +:10E4C000020202020202020202020202020202002E +:10E4D000020202020202020202020202020202021C +:10E4E000000202020201020202020202020202020F +:10E4F0000001010202010202020202020200000205 +:10E5000001010102010102020201020102020201F3 +:10E5100001010101010101020202020201020100E6 +:10E5200000010101010101020102010201010100DA +:10E5300002010101010101010101010101020001CA +:10E5400001010101010101020202010101010101B8 +:10E5500001010101010101020101010101010101AA +:10E56000010101010101010102010101010101019A +:10E57000010101010101010201010101010101018A +:10E58000010101010101010101010101010101017B +:10E590000101010101010100020202020202020165 +:10E5A0000101010101010102020202020202020252 +:10E5B0000202000002020002020202020201000046 +:10E5C000020202020202020202020202020202002D +:10E5D000020202020202020202020202020202021B +:10E5E000000202020202020202020202020202020D +:10E5F0000001010202010202020202020200000204 +:10E6000001010102010102020201020102020201F2 +:10E6100001010101010101020202020201020100E5 +:10E6200001010101010101020102010201010100D8 +:10E6300002010101010101020101010101020001C8 +:10E6400001010101010101020202010101010101B7 +:10E6500001010101010101020101010101010101A9 +:10E660000101010101010101020101010101010199 +:10E670000101010101010102010101010101010189 +:10E68000010101010101010101010101010101017A +:10E690000101010101010100020202020202020164 +:10E6A0000101010101010102020202020202020251 +:10E6B0000202000002020002020202020201000045 +:10E6C000020202020202020202020202020202002C +:10E6D000020202020202020202020202020202021A +:10E6E000000202020202020202020202020202020C +:10E6F0000001020202010202020202020200000202 +:10E7000001010102010202020201020102020201F0 +:10E7100001010101010101020202020201020100E4 +:10E7200001010101010102020202010201010100D5 +:10E7300002010101010101020101010101020001C7 +:10E7400001010101010101020202010101010101B6 +:10E7500001010101010101020101010101010101A8 +:10E760000101010101010101020101010101010198 +:10E770000101010101010102010101010101010188 +:10E780000101010101010101010101010101010179 +:10E790000101010101010100020202020202020163 +:10E7A0000101010101010102020202020202020250 +:10E7B0000202000002020002020202020201000044 +:10E7C000020202020202020202020202020202002B +:10E7D0000202020202020202020202020202020219 +:10E7E000000202020202020202020202020202020B +:10E7F0000001020202010202020202020200000201 +:10E8000001010102010202020201020102020201EF +:10E8100001010101010101020202020201020100E3 +:10E8200001010101010102020202010201010100D4 +:10E8300002010101010101020101010101020101C5 +:10E8400001010101010101020202010101010101B5 +:10E8500001010101010101020101010101010101A7 +:10E860000101010101010101020101010101010197 +:10E870000101010101010102010101010101010187 +:10E880000101010101010101010101010101010178 +:10E890000101010101010100020202020202020162 +:10E8A000010101010101010202020202020202024F +:10E8B0000202000002020002020202020201000043 +:10E8C000020202020202020202020202020202002A +:10E8D0000202020202020202020202020202020218 +:10E8E000000202020202020202020202020202020A +:10E8F0000001020202010202020202020200000200 +:10E9000001020102010202020202020102020201EC +:10E9100002010102010101020202020201020101DF +:10E9200001010101010202020202010201010100D2 +:10E9300002010101010101020101010101020101C4 +:10E9400001010101010101020202010101010101B4 +:10E9500001010101010101020101010101010101A6 +:10E960000101010101010102020101010101010195 +:10E970000101010101010102010101010101010186 +:10E980000101010101010101010101010101010177 +:10E990000101010101010100020202020202020161 +:10E9A000010101010101010202020202020202024E +:10E9B0000202000002020002020202020201000042 +:10E9C0000202020202020202020202020202020029 +:10E9D0000202020202020202020202020202020217 +:10E9E0000002020202020202020202020202020209 +:10E9F00000010202020102020202020202000002FF +:10EA000001020202010202020202020202020201E9 +:10EA100002010102010101020202020201020101DE +:10EA200001010101010202020202010201010100D1 +:10EA300002010101010101020202010101020101C1 +:10EA400001010101010101020202020101010101B2 +:10EA500001010101010101020101010101010101A5 +:10EA60000101010101010102020101010101010194 +:10EA70000101010101010102010101010101010185 +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010100020202020202020160 +:10EAA000010101010101010202020202020202024D +:10EAB0000202000002020002020202020201000041 +:10EAC0000202020202020202020202020202020127 +:10EAD0000202020202020202020202020202020216 +:10EAE0000002020202020202020202020202020208 +:10EAF00000020202020102020202020202000002FD +:10EB000001020202020202020202020202020201E7 +:10EB100002010102010102020202020201020101DC +:10EB200001010101010202020202010201010100D0 +:10EB300002010101010101020202010101020101C0 +:10EB400001010101010101020202020101010101B1 +:10EB500001010101010102020101010101010101A3 +:10EB60000101010101010102020101010101010193 +:10EB70000101010101010102010101010101010184 +:10EB80000101010101010102010101010101010174 +:10EB9000010101010101010002020202020202015F +:10EBA000010101010101010202020202020202024C +:10EBB000020200000202000202020202020200003F +:10EBC0000202020202020202020202020202020126 +:10EBD0000202020202020202020202020202020215 +:10EBE0000002020202020202020202020202020207 +:10EBF00000020202020102020202020202000002FC +:10EC000001020202020202020202020202020201E6 +:10EC100002010102010102020202020201020101DB +:10EC200001010101010202020202010201020200CD +:10EC300002010101010101020202010101020101BF +:10EC400001010101010101020202020101010101B0 +:10EC500001010101010202020101010101010101A1 +:10EC60000101010101010102020101010101010192 +:10EC70000101010101010102010101010101010183 +:10EC80000101010101010102010101010101010173 +:10EC9000010101010101010002020202020202015E +:10ECA000010101010101010202020202020202024B +:10ECB000020200000202000202020202020200003E +:10ECC0000202020202020202020202020202020125 +:10ECD0000202020202020202020202020202020214 +:10ECE0000002020202020202020202020202020206 +:10ECF00000020202020202020202020202000002FA +:10ED000001020202020202020202020202020201E5 +:10ED100002020102010102020202020201020101D9 +:10ED200001010102010202020202010201020200CB +:10ED300002010101010101020202010101020101BE +:10ED400001010101010101020202020101010101AF +:10ED5000010101010102020201010201010101019F +:10ED60000101010101010102020101010101010191 +:10ED70000101010101010102020101010101010181 +:10ED80000101010101010102010101010101010172 +:10ED9000010101010101010002020202020202015D +:10EDA000010101010101010202020202020202024A +:10EDB000020200000202000202020202020200003D +:10EDC0000202020202020202020202020202020124 +:10EDD0000202020202020202020202020202020213 +:10EDE0000002020202020202020202020202020205 +:10EDF00000020202020202020202020202000002F9 +:10EE000001020202020202020202020202020202E3 +:10EE100002020102010102020202020201020101D8 +:10EE200001010102010202020202010201020200CA +:10EE300002010101010102020202010101020101BC +:10EE400001010101010101020202020101010101AE +:10EE5000010101010102020202010201010101019D +:10EE60000101010101010102020101010101010190 +:10EE7000010101010101020202010101010101017F +:10EE80000101010101010102020101010101010170 +:10EE9000010101010101010002020202020202025B +:10EEA0000202020101010102020202020202020246 +:10EEB000020200000202000202020202020201003B +:10EEC0000202020202020202020202020202020123 +:10EED0000202020202020202020202020202020212 +:10EEE0000002020202020202020202020202020204 +:10EEF00000020202020202020202020202000102F7 +:10EF000001020202020202020202020202020202E2 +:10EF100002020102010102020202020201020101D7 +:10EF200001010102010202020202020201020201C7 +:10EF300002010102010102020202010101020101BA +:10EF400001010101010101020202020101010101AD +:10EF5000010201010202020202010201010101019A +:10EF6000010101010101010202010101010101018F +:10EF7000010101010101020202010101010101017E +:10EF8000010101010101010202010101010101016F +:10EF9000010101010101010002020202020202025A +:10EFA0000202020101010102020202020202020245 +:10EFB000020200000202000202020202020201003A +:10EFC0000202020202020202020202020202020122 +:10EFD0000202020202020202020202020202020211 +:10EFE0000002020202020202020202020202020203 +:10EFF00000020202020202020202020202000102F6 +:10F0000001020202020202020202020202020202E1 +:10F0100002020102010102020202020201020101D6 +:10F0200001010102010202020202020201020201C6 +:10F0300002010102010102020202010101020101B9 +:10F0400001010101010102020202020101010101AB +:10F050000102010102020202020102010101010199 +:10F06000010101010101010202020101010101018D +:10F07000010201010102020202010101010101017B +:10F08000010101010101010202010101010101016E +:10F090000101010101010100020202020202020259 +:10F0A0000202020102020102020202020202020242 +:10F0B0000202000002020002020202020202010039 +:10F0C0000202020202020202020202020202020121 +:10F0D0000202020202020202020202020202020210 +:10F0E0000002020202020202020202020202020202 +:10F0F00000020202020202020202020202000102F5 +:10F1000001020202020202020202020202020202E0 +:10F1100002020102010102020202020201020101D5 +:10F1200001020102010202020202020201020201C4 +:10F1300002010102010202020202010101020101B7 +:10F1400001010101010102020202020101010101AA +:10F150000102020102020202020102010101010197 +:10F16000010101010101020202020201010101018A +:10F170000102020102020202020202010101010176 +:10F18000010201010101020202020101010101016A +:10F190000101010101010100020202020202020258 +:10F1A000020202020202020202020202020202023F +:10F1B0000202000002020002020202020202010038 +:10F1C0000202020202020202020202020202020120 +:10F1D000020202020202020202020202020202020F +:10F1E0000102020202020202020202020202020200 +:10F1F00000020202020202020202020202000102F4 +:10F2000002020202020202020202020202020202DE +:10F2100002020102010102020202020202020101D3 +:10F2200001020102010202020202020201020201C3 +:10F2300002010102010202020202020101020101B5 +:10F2400001010101010102020202020201010101A8 +:10F250000202020102020202020202010101010194 +:10F260000101010101020202020202010101010188 +:10F270000102020102020202020202010101010175 +:10F280000202020102020202020202010101010164 +:10F290000101010101010100020202020202020257 +:10F2A000020202020202020202020202020202023E +:10F2B0000202000002020002020202020202020135 +:10F2C000020202020202020202020202020202011F +:10F2D000020202020202020202020202020202020E +:10F2E00001020202020202020202020202020202FF +:10F2F00001020202020202020202020202010102F1 +:10F3000002020202020202020202020202020202DD +:10F3100002020102010102020202020202020201D1 +:10F3200001020102010202020202020201020201C2 +:10F3300002010102010202020202020101020101B4 +:10F3400001010101010102020202020202010102A5 +:10F350000202020202020202020202010101010192 +:10F360000101010101020202020202020201020283 +:10F370000202020202020202020202010101010172 +:10F380000202020102020202020202010101010163 +:10F390000101010101010100020202020202020256 +:10F3A000020202020202020202020202020202023D +:10F3B0000202000002020002020202020202020134 +:10F3C000020202020202020202020202020202021D +:10F3D000020202020202020202020202020202020D +:10F3E00001020202020202020202020202020202FE +:10F3F00001020202020202020202020202010102F0 +:10F4000002020202020202020202020202020202DC +:10F4100002020202010102020202020202020201CF +:10F4200001020102020202020202020202020201BF +:10F4300002010102020202020202020201020102B0 +:10F4400001010101010202020202020202010202A2 +:10F450000202020202020202020202010101010191 +:10F460000102010102020202020202020201020280 +:10F47000020202020202020202020202020101026E +:10F480000202020202020202020202020101010160 +:10F490000101010101010100020202020202020255 +:10F4A000020202020202020202020202020202023C +:10F4B0000202000002020002020202020202020232 +:10F4C000020202020202020202020202020202021C +:10F4D000020202020202020202020202020202020C +:10F4E00001020202020202020202020202020202FD +:10F4F00001020202020202020202020202010102EF +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020202020202020201CC +:10F5200001020102020202020202020202020201BE +:10F5300002010102020202020202020201020102AF +:10F5400001010101010202020202020202010202A1 +:10F550000202020202020202020202010101010190 +:10F56000020202020202020202020202020202027B +:10F57000020202020202020202020202020102026C +:10F58000020202020202020202020202020101015E +:10F590000102010101010100020202020202020253 +:10F5A000020202020202020202020202020202023B +:10F5B0000202010002020002020202020202020230 +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020202020202020202020B +:10F5E00001020202020202020202020202020202FC +:10F5F00001020202020202020202020202010102EE +:10F6000002020202020202020202020202020202DA +:10F6100002020202020202020202020202020201CB +:10F6200001020102020202020202020202020201BD +:10F6300002010102020202020202020202020102AD +:10F64000010101010102020202020202020202029F +:10F65000020202020202020202020202010101018E +:10F66000020202020202020202020202020202027A +:10F67000020202020202020202020202020202026A +:10F68000020202020202020202020202020202015B +:10F69000020201010202020002020202020202024E +:10F6A000020202020202020202020202020202023A +:10F6B000020201010202000202020202020202022E +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020202020202020202020A +:10F6E00001020202020202020202020202020202FB +:10F6F00001020202020202020202020202010102ED +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020202020202020202020201CA +:10F7200001020202020202020202020202020201BB +:10F7300002020202020202020202020202020102AA +:10F74000010202010102020202020202020202029C +:10F75000020202020202020202020202010101018D +:10F760000202020202020202020202020202020279 +:10F770000202020202020202020202020202020269 +:10F780000202020202020202020202020202020259 +:10F79000020202010202020002020202020202024C +:10F7A0000202020202020202020202020202020239 +:10F7B000020202020202000202020202020202022B +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020202020202020202020202F9 +:10F7F00001020202020202020202020202020202EA +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020201C9 +:10F8200001020202020202020202020202020201BA +:10F8300002020202020202020202020202020102A9 +:10F84000010202010202020202020202020202029A +:10F85000020202020202020202020202020101028A +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F89000020202020202020002020202020202024A +:10F8A0000202020202020202020202020202020238 +:10F8B000020202020202000202020202020202022A +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00001020202020202020202020202020202E9 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020201B8 +:10F9300002020202020202020202020202020102A8 +:10F940000102020102020202020202020202020299 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020277 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020200020202020202020249 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020002020202020202020229 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020202020202020201B7 +:10FA300002020202020202020202020202020102A7 +:10FA40000102020102020202020202020202020298 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020200020202020202020248 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020002020202020202020228 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020202020202020201B6 +:10FB300002020202020202020202020202020202A5 +:10FB40000102020102020202020202020202020297 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020200020202020202020247 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020002020202020202020227 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020201B5 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020200020202020202020246 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020002020202020202020226 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020201B4 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020200020202020202020245 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020002020202020202020225 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020200020202020202020244 +:10FEA0000202020202020202020202020202020232 +:10FEB0000202020202020002020202020202020224 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020200020202020202020243 +:10FFA0000202020202020202020202020202020231 +:10FFB0000202020202020002020202020202020223 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:02000002A0005C +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020200020202020202020242 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020002020202020202020222 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:100190000202020202020200020202020202020241 +:1001A000020202020202020202020202020202022F +:1001B0000202020202020002020202020202020221 +:1001C000020202020202020202020202020202020F +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:100290000202020202020200020202020202020240 +:1002A000020202020202020202020202020202022E +:1002B0000202020202020002020202020202020220 +:1002C000020202020202020202020202020202020E +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B0000202020202020002020202020102020220 +:1003C000010202020202020202020202020202020E +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020202020202020202023C +:1004A000020202020202020202020202020202022C +:1004B0000202020101020002020202020102020221 +:1004C000010202010202020202020202020202020E +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202024B +:10059000020202020202020202020202020202023B +:1005A0000202020202020201010101010101010134 +:1005B0000101010101010102020201020102020224 +:1005C000010202010202020202020202020202020D +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202024A +:10069000020202020202020202020202020202023A +:1006A0000202020202020201010101010101010133 +:1006B0000101010101010102020201020102020223 +:1006C000010101010202020202020202020202020E +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:100770000202020202020202020202020202020259 +:100780000202020202020202020202020202020249 +:100790000202020202020202020202020202020239 +:1007A0000202020202020201010101010101010132 +:1007B0000101010101010102020101020102020124 +:1007C000010101010202020202020202020202020D +:1007D00002020202020202020202020202020201FA +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020248 +:100890000202020202020202020202020202020238 +:1008A0000202020202020201010101010101010131 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010102020202020202010210 +:1008D00002020202020202020202020202010202F9 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020247 +:100990000202020202020202020202020202020237 +:1009A0000202020202020201010101010101010130 +:1009B0000101010101010101010101010101010127 +:1009C000010101010101010202020202020102020F +:1009D00002020202020202020202020201020101FA +:1009E00002020201020202020202020202020202E8 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA000020202020202020101010101010101012F +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010102020102010202010210 +:100AD00001020201020202020202020202010201FA +:100AE00002010102010202020202020202020202E9 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA000020202020202020101010101010101012E +:100BB0000101010101010101010101010101010125 +:100BC000010101010101010202020202010101020F +:100BD00002010102020202010202020201010101FC +:100BE00002020201020102020202020202020202E7 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA000020202020202020101010101010101012D +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010102020102010201010110 +:100CD0000102020101010202010101010101010100 +:100CE00001010101010201020202020202010202EB +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA000020202020202020101010101010101012C +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010212 +:100DD00001010101020201010202020201010101FD +:100DE00002010101010102020202010102020101EC +:100DF00002020201020202020202020202020202D4 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA000020202020202020101010101010101012B +:100EB0000101010101010101010101010101010122 +:100EC000010101010101010202010201010101010F +:100ED0000101010101010201010101010101010101 +:100EE00001010101010101020202020201010202EB +:100EF00002020102020202020202020202020202D3 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA000020202020202020101010101010101012A +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010201010102010101EF +:100FF00001010201010202020202020202020202D5 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020201010101010101010129 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101020102010101010101EE +:1010F00002020101020101020202020202020202D4 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A0000202020202020201010101010101010128 +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010201010101010101EE +:1011F00001010101010202020202020202020202D4 +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A0000202020202020201010101010101010127 +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101020202010201020202D7 +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A0000202020202020201010101010101010126 +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101020202010101020201D8 +:1014000002020201020202020202020202020202BD +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A0000202020202020201010101010101010125 +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010202010101020201D8 +:1015000001010101010202020202020202010202C1 +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A0000202020202020201010101010101010124 +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010102020201020102C5 +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A0000202020202020201010101010101010123 +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101020202010202010201C3 +:1017100001020201020202020202020202020202AB +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A0000202020202020201010101010101010122 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010102020101010102C5 +:1018100002010102020202020202020202020202AA +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A0000202020202020201010101010101010121 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010201010101C6 +:1019100001020201010101020202020202020202AC +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020201010101010101010120 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010102010101010101C5 +:101A100001010101020202010202020102010202AD +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA000020202020202020101010101010101011F +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010201010102010202B1 +:101B20000202020102020202020102010202020298 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA000020202020202020101010101010101011E +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C2000010101010101010202020202020101029D +:101C30000102020202020202020202020202020285 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA000020202020202020101010101010101011D +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D2000010101010101010202010201020202029C +:101D30000202010102020202020202020202020285 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA000020202020202020101010101010101011C +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101020201010102020202020202020287 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA000020202020202020101010101010101011B +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F2000010101010101010202010201020101029C +:101F30000102010102020202020202020201020285 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA000020202020202020101010101010101011A +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010102020202020201020288 +:102040000202020202020202020102020202020271 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020201010101010101010119 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:102130000101010101010102020102020201020189 +:102140000202020202020201010201020202020272 +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A0000202020202020201010101010101010118 +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010202010201010101017B +:102250000101010101010102020202020202020265 +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A0000202020202020201010101010101010117 +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:102340000101010101010101010101020202020278 +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A0000202020202020201010101010101010116 +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:102450000101010101010102020202020202020263 +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A0000202020202020201010101010101010115 +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:102550000101010101010101020201020202020264 +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A0000202020202020201010101010101010114 +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:102660000101010101010102010202020202020252 +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A0000202020202020201010101010101010113 +:1026B000010101010101010101010101010101010A +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101020101010101010158 +:102770000101010101010102020202020202020240 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020201010101010101010112 +:1027B0000101010101010101010101010101010109 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010102010202020202020250 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020201010101010101010111 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:10297000010101010101010102020202020202023F +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020201010101010101010110 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010146 +:102A8000010101010101010202020202020202022D +:102A90000202020202020202020202020202020216 +:102AA000020202020202020101010101010101010F +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010165 +:102B60000101010101010101010101010101010155 +:102B70000101010101010101010101010101010145 +:102B80000101010101010101010101010101010135 +:102B9000010101010101010202020202020202021C +:102BA000020202020202020101010101010101010E +:102BB0000101010101010101010101010101010105 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101010101010101010101E5 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000101010101010101010101010101010164 +:102C60000101010101010101010101010101010154 +:102C70000101010101010101010101010101010144 +:102C8000010101010101010202020202020202022B +:102C90000202020202020202020202020202020214 +:102CA000020202020202020101010101010101010D +:102CB0000101010101010101010101010101010104 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010173 +:102D50000101010101010101010101010101010163 +:102D60000101010101010101010101010101010153 +:102D70000101010101010101010101010101010143 +:102D80000101010101010101010101010101010133 +:102D9000010101010101010202020202020202021A +:102DA000020202020202020101010101010101010C +:102DB0000101010101010101010101010101010103 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010132 +:102E90000101010101010102020202020202020219 +:102EA000020202020202020101010101010101010B +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010101D2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F9000010101010101010201010101010101021F +:102FA000020202020202020101010101010101010A +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:10309000010101010101010201010101010101011F +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:10317000010101010101010101010101010101013F +:10318000010101010101010101010101010101012F +:10319000010101010101010201010101010101011E +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000010101010101010101010101010101014E +:10327000010101010101010101010101010101013E +:10328000010101010101010101010101010101012E +:10329000010101010101010201010101010101011D +:1032A000010101010101010101010101010101010E +:1032B00001010101010101010101010101010101FE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000010101010101010201010101010101011C +:1033A000010101010101010101010101010101010D +:1033B00001010101010101020202020202020202F4 +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020000000000000000001E +:1034A0000000000000000001010101010101010113 +:1034B0000101010101010100000000000000000005 +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000020202020202020202DA +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020000000000000000001D +:1035A0000000000000000001010101010101010112 +:1035B0000101010101010100000000000000000004 +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000020202020202020202D9 +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020000000000000000004C +:103670000000000000000002020202020202020238 +:10368000020202020202020202020202020202021A +:10369000020202020202020000000000000000001C +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A00000000000000000660000000000000000B3 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000001000000000000000000E8 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000001000000000000000000E7 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000010000000000000100000000B5 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000010096 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000100000000000000F6 +:1039D00000000000000001000000000000000100E5 +:1039E00001000000000000000000000100000000D5 +:1039F00000000000000001000000000000000100C5 +:103A000000000000010000000000000100000000B4 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000010000010094 +:103A30000001000000000000000000000000000085 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000010065 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000010015 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000100000000000100F4 +:103AD00001000000000101000000000000000100E2 +:103AE00001000000000000010000010100000100D1 +:103AF00000000000000001000000000100000100C3 +:103B000000000000010000000000000100000000B3 +:103B100000000000000100000100000000000000A3 +:103B20000000000000000000000000010000010093 +:103B30000001000000000000000000000000010083 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000010064 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000100000100000000000000000000010012 +:103BB0000000000000000000000000000001000004 +:103BC00000000000000000000100000000000100F3 +:103BD00001000000000101000000000000000100E1 +:103BE00001000000000000010000010100000100D0 +:103BF00000000100000001000000000100000100C1 +:103C000000000100010000000000000101000100AF +:103C100000000000000100000100000000000000A2 +:103C20000000000000000000000000010000010092 +:103C30000001000100000000000000000000010081 +:103C40000000000000000000000000000000010073 +:103C50000000000000000000000000000000010063 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000100000100000000000000000000010011 +:103CB0000001000000000000000000000001000002 +:103CC00000000000000000000100000000000100F2 +:103CD00001000000000101000100000000000100DF +:103CE00001000000000000010000010100000100CF +:103CF00001000100000001000000000100000100BF +:103D000000000100010000000000000101000100AE +:103D100000000000000100000100000000000000A1 +:103D20000000000000000000000000010000010091 +:103D30000001000100000000000000000000010080 +:103D40000000000000000000000000000000010072 +:103D50000000000000000000000000000000010062 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000010042 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000100000100000000000000000000010010 +:103DB0000001000000000000000000000001000001 +:103DC00000000000000000000100000000000100F1 +:103DD00001000000000101000100000000000100DE +:103DE00001000000000000010000010100000100CE +:103DF00001000100000001010000000100000100BD +:103E000000000100010000000000000101000100AD +:103E100000000000000100000100000000000000A0 +:103E20000000000000000000000000010000010090 +:103E3000000100010000000000000000000001007F +:103E40000000000000000000000000000000010071 +:103E50000000000000000000000000000000010061 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000010041 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA000010001010000000000000000000001000E +:103EB00001010000000000000000000000010000FF +:103EC00000000000000000000100000001010101ED +:103ED00001000000000101000100000000000100DD +:103EE00001000000000000010000010100000100CD +:103EF00001000101000101010000000100000100BA +:103F000000000100010000000000000101000100AC +:103F1000000000000001000001000000000000009F +:103F2000000000000000000000000001000001008F +:103F3000000100010000000000000000000001007E +:103F40000000000000000000000000000000010070 +:103F50000000000000000000000000000000010060 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000010040 +:103F80000000000000000000000000000000010030 +:103F90000000000000000000000000000000000021 +:103FA000010001010000000000000000000001000D +:103FB00001010000000000000000000000010001FD +:103FC00000000000010000000100000001010101EB +:103FD00001000000000101000100000000000101DB +:103FE00001000000000100010000010100000100CB +:103FF00001000101000101010000000100000100B9 +:1040000000000100010000000000000101010100AA +:10401000000000000001000001000000000001009D +:10402000000000000000000000000001000001018D +:10403000000100010000000000000000000001007D +:10404000000000000000000000000000000001006F +:10405000000000000000000000000000000001005F +:104060000000000000000000000000000000000050 +:10407000010000000000000000000000000001003E +:10408000000000000000000000000000000001002F +:104090000000000000000000000000000000000020 +:1040A000010001010000000000000000000001010B +:1040B00001010000000000000000000000010001FC +:1040C00000000000010000000100000001010101EA +:1040D00001000000000101000100000000000101DA +:1040E00001000000000100010000010100000100CA +:1040F00001000101010101010000000100000100B7 +:1041000000000100010000000000000101010100A9 +:10411000000000000001000001000000000001009C +:10412000000000000000000000000001010001018B +:10413000000100010000000000000000000001007C +:10414000000000000000000000000000000001006E +:10415000000000000000000000000000000001005E +:10416000000000000000000000000000000000004F +:10417000010000000000000000000000000001003D +:10418000000000000000000000000000000001002E +:10419000000000000000000000000000000000001F +:1041A000010001010000000000000000000001010A +:1041B00001010000000000000000000000010001FB +:1041C00001000000010000000100000001010101E8 +:1041D00001000000000101000100000001000101D8 +:1041E00001000000000100010000010100000100C9 +:1041F00001000101010101010000000100000100B6 +:1042000000000100010000000000000101010100A8 +:10421000000000000001000001000000000001009B +:10422000000000000000000000000001010001018A +:10423000000100010001000000000000000001007A +:10424000000000000000000000000000000001006D +:10425000000000000000000000000000000101005C +:10426000000000000000000000000000000000004E +:10427000010000000000000000000000000001003C +:10428000000000000000000000000000000001002D +:10429000000000000000000000000000000000001E +:1042A0000100010100000000000000000000010109 +:1042B00001010000000000000000000000010001FA +:1042C00001000100010000000100000001010101E6 +:1042D00001010000000101000100000001000101D6 +:1042E00001000000000100010000010101000100C7 +:1042F00001000101010101010000000100000100B5 +:1043000000000100010000000000000101010100A7 +:10431000000000000001000001000000000001009A +:104320000000000000000000000000010100010189 +:104330000001000100010000000000000100010078 +:10434000000000000000000000000000000001006C +:10435000000000000000000000000000000101005B +:10436000000000000000000000000000000001004C +:10437000010000000000000000000000000001003B +:10438000000000000000000000000000000001002C +:10439000000000000000000000000000000000001D +:1043A0000100010100000000000000000000010108 +:1043B00001010000000000000000000000010001F9 +:1043C00001000100010000000100000001010101E5 +:1043D00001010000000101000100000001000101D5 +:1043E00001000000010100010000010101000100C5 +:1043F00001000101010101010000000100010100B3 +:1044000000000100010000000000000101010100A6 +:104410000000000000010000010000000000010198 +:104420000100000000000000000000010100010187 +:104430000001000100010000010000000100010076 +:10444000000000000000000000000000000001006B +:10445000000000000000000000000000000101005A +:10446000000000000000000000000000000001004B +:10447000010000000000000000000000000001003A +:10448000000000000000000000000000000001002B +:10449000000000000000000000000000000000001C +:1044A0000100010100000000000000000000010107 +:1044B00001010000000000000000000000010001F8 +:1044C00001000100010000000100000001010101E4 +:1044D00001010001000101000100000001000101D3 +:1044E00001000000010100010000010101000100C4 +:1044F00001000101010101010000000100010100B2 +:1045000000000100010100000000000101010100A4 +:104510000000000000010000010000000000010197 +:104520000100000000000000000000010100010186 +:104530000001000100010000010000000100010075 +:104540000000000000010000000000000000010069 +:104550000000000000000000000000000001010059 +:10456000000000000000000000000000000001004A +:104570000100000000000000000000000001010038 +:104580000000000000000000000000000001010029 +:10459000000000000000000000000000000001001A +:1045A0000100010100000000000000000000010106 +:1045B00001010000000000000000000000010001F7 +:1045C00001000100010000000100000001010101E3 +:1045D00001010001000101000100000001010101D1 +:1045E00001000000010100010000010101000100C3 +:1045F00001000101010101010000000100010100B1 +:1046000000000100010100010000000101010100A2 +:104610000000000000010000010000000000010196 +:104620000100000000010000000000010100010184 +:104630000001000100010000010000000100010074 +:104640000000000000010000000000000000010068 +:104650000000000000000000000000000001010058 +:104660000000000000000000000000000000010049 +:104670000100000000000000000000000001010037 +:104680000000000000000000000000000001010028 +:104690000000000000000000000000000000010019 +:1046A0000100010100000000000000000000010105 +:1046B00001010000000000000000000000010001F6 +:1046C00001000100010000000100000001010101E2 +:1046D00002010001000101000100000001010101CF +:1046E00001000000010100010000010101010100C1 +:1046F00001000101010101010000000100010100B0 +:1047000000000100010100010000000101010100A1 +:104710000000000000010000010000000000010195 +:104720000100000000010000000000010101010182 +:104730000001000100010100010000000100010072 +:104740000000000000010000000000000000010067 +:104750000000000000000000000000000001010057 +:104760000000000000000000000000000000010048 +:104770000100000000000000000000000001010036 +:104780000000000000000000000000000101010026 +:104790000000000000000000000000000000010018 +:1047A0000100010100000000000000000000010104 +:1047B00002020000000000000000000000010001F3 +:1047C00001000100010000000100000001010101E1 +:1047D00002010101000101000100000001010101CD +:1047E00002010000010100010000010101010100BE +:1047F00001000101010101010000000100010100AF +:1048000000000100010100010000000101010100A0 +:104810000000000000010100010000000000010193 +:104820000100000000010000000000010101010181 +:104830000001000100010100010000000100010071 +:104840000000000000010000000000000001010065 +:104850000000000000000000000000000001010056 +:104860000000000000000000000000000000010047 +:104870000100000000000000000000000001010035 +:104880000000000000000000000000000101010025 +:104890000000000000000000000000000000010017 +:1048A0000100010100000000000000000000010103 +:1048B00002020000000000000000000000010001F2 +:1048C00001000100010000000100000001010101E0 +:1048D00002010101000101000100000001010101CC +:1048E00002010100010100010000010101010100BC +:1048F00001000101010101010000000100010101AD +:10490000010001010101000100010001010101009C +:104910000100000000010100010100000000010190 +:104920000100000000010000000000010101010180 +:104930000001000100010100010000000100010070 +:104940000000000000010000000000000001010064 +:104950000000000000000000000000000001010055 +:104960000000000000000000000000000000010046 +:104970000100000000000000000000000101010033 +:104980000000000000000000000000000101010024 +:104990000000000000000000000000000000010016 +:1049A0000100010100000000000000000000010201 +:1049B00002020100000000000000000000010001F0 +:1049C00002000100010000000100000001010102DD +:1049D00002010101000102000100000001010101CA +:1049E00002010100010100010000010101010100BB +:1049F00002000101010101010000000101010101AA +:104A0000010001010101000100010001010101009B +:104A1000010000000001010001010000000001018F +:104A2000010000000001000000000001010101017F +:104A3000000100010001010001000000010001006F +:104A40000000000000010000000000000001010063 +:104A50000000000000000000000000000001010054 +:104A60000000000000000000000000000000010045 +:104A70000100000000000000000000000101010032 +:104A80000000000000000000000000000101010023 +:104A90000000000000000000000000000000010015 +:104AA0000100010100000000000000000000010200 +:104AB00002020100000000000001000000010002ED +:104AC00002000100010000000100000001010102DC +:104AD00002010101000102000100000001010101C9 +:104AE00002010100010101010000010101010101B8 +:104AF00002010101010101010000000101010101A8 +:104B0000010001010101000100010001010101009A +:104B1000010000000001010001010000000001018E +:104B2000010000000001000000000001010101017E +:104B3000000100010001010001000000010101016C +:104B40000000000000010000000000000001010161 +:104B50000100000000000000000000000001010052 +:104B60000000000000000000000000000001010043 +:104B70000100000000000000000000000101010031 +:104B80000000000000000000000000000101010022 +:104B90000000000000000000000000000001010013 +:104BA00001000101000000000000000000000102FF +:104BB00002020100000000000001000000010002EC +:104BC00002000100010000000100000001010102DB +:104BD00002010101000202000100000001010102C6 +:104BE00002010100010101010000010101010101B7 +:104BF00002010201010101010000000101010101A6 +:104C00000100010101010001000100010101010099 +:104C1000010001000001010101010000010001018A +:104C2000010100000001000000000001010101017C +:104C3000000100010001010001000001010101016A +:104C4000000000000001000100000000000101015F +:104C50000100000000000000000000000101010050 +:104C60000000000000000000000000000001010042 +:104C7000010000000000000000010000010101002F +:104C80000000000000000000000100000101010020 +:104C90000000000000000000000000000001010012 +:104CA00001000101000000000000000000000102FE +:104CB00002020101000000000001000000010002EA +:104CC00002000200010000000100000001010102D9 +:104CD00002020101000202000100000001010102C4 +:104CE00002010100010101010000010101010101B6 +:104CF00002010201010101010000000101010101A5 +:104D00000101010101010001000100010101010196 +:104D10000100010001010101010100000100010188 +:104D2000010101000001000000000001010101017A +:104D30000001000100010100010000010101010169 +:104D4000000000000001000100000000000101015E +:104D5000010000000100000000010000010101004D +:104D60000000000000000000000000000001010041 +:104D7000010000000000000000010000010101002E +:104D8000000000000000000000010100010101001E +:104D90000000000000000000000000000101010010 +:104DA00001000101000000000000000000000102FD +:104DB00002020101000000000001000000010002E9 +:104DC00002010200020000000200000001010102D5 +:104DD00002020101000202000100000001010102C3 +:104DE00002010100010101010000010101010101B5 +:104DF00002010201010101010000000101010101A4 +:104E00000101020101010001000100010101010194 +:104E10000100010001010101010100000101010186 +:104E20000101010100010000000000010101010178 +:104E30000002000100010100010000010101010167 +:104E4000000000000001000100000000000101015D +:104E5000010000000100000000010000010101014B +:104E60000000000000000000000000000001010040 +:104E7000010000000000000000010001010101002C +:104E8000000000000000000001010101010101011A +:104E9000000000000000000000000000010101000F +:104EA00001000101000000000000000000000102FC +:104EB00002020101000000000001000000010002E8 +:104EC00002010200020000000200000001010102D4 +:104ED00002020101000202000100000001010102C2 +:104EE00002010100010101010000010101010101B4 +:104EF00002010201010102010000000101010101A2 +:104F00000101020101010001000100010101010193 +:104F10000100010001010101010100010101010184 +:104F20000101010100010000000001010101010275 +:104F30000002000100010100010000010101010166 +:104F4000000100000001000100000000000101015B +:104F50000101000001000000000100000101010149 +:104F6000000000000000000000000000000101003F +:104F7000010000000000000000010101010101002A +:104F80000000000000000000010101010101010119 +:104F9000000000000000000000000000010101000E +:104FA00001000101000000000000000000000102FB +:104FB00002020201000000000001000000010002E6 +:104FC00002010201020000000200000001010102D2 +:104FD00002020101000202000100000001010102C1 +:104FE00002010101010101020000010101010101B1 +:104FF00002010202010102010000000101010101A0 +:105000000101020102010001000100010101010191 +:105010000100010001010101010101010101010182 +:105020000101010100010000000101010101010273 +:105030000102000100010100010000010101010164 +:10504000000100000001000100000000000101015A +:105050000101000001000000000100000101010148 +:10506000000000000000000000000000000101003E +:105070000100000000000000000101010101010029 +:105080000000000000000000010101010101010118 +:10509000000000000000000000010000010101000C +:1050A00001000101000000000000000001010102F8 +:1050B00002020201000000000001000000010002E5 +:1050C00002010201020000000200000001010102D1 +:1050D00002020202000202000200000001010102BD +:1050E00002010101010101020000010101010101B0 +:1050F000020102020101020100000001010101019F +:10510000010102010201000101010001010101018F +:105110000100010101010101010101010101010180 +:105120000101010100010001000101010101010271 +:105130000102000100010101010000010101010162 +:105140000001000000010001000000000001010159 +:105150000101000001000000000100000101010147 +:10516000000000000000000000000000000101003D +:105170000100000000000001000101010101010027 +:105180000000000000000001010101010101010116 +:10519000000000000000000000010100010101000A +:1051A00001000101000000000001000001010102F6 +:1051B00002020201000000000001000000010002E4 +:1051C00002010201020000000200000001010102D0 +:1051D00002020202000202000200000001010102BC +:1051E00002020101010201020000010101010101AD +:1051F000020102020102020100000001010101019D +:10520000020102010201000101010101010101018C +:10521000010001010101010101010101010101027E +:10522000020101010101000100010101010101026E +:105230000102000100010101010000010101010161 +:105240000001010000010001000000000101010156 +:105250000101010001000001000100000101010144 +:10526000000000000000000000000000000101003C +:105270000100000000000001010101010101010124 +:105280000000000000000001010101010101010115 +:105290000000000000000000010101010101010007 +:1052A00001000101000000000001010001010102F4 +:1052B00002020201010000000001000000010002E2 +:1052C00002020201020000000200000001010102CE +:1052D00002020202010202000200000001010102BA +:1052E00002020201020201020000010201010102A8 +:1052F0000201020202020201010000010101010299 +:10530000020102010201000101010101010101018B +:10531000020001010102010101010101010101027B +:10532000020101010101000100010101010101026D +:10533000010200020001010101000101010101015E +:105340000001010000010001000000010101010154 +:105350000101010001000001010100000101010142 +:10536000000000000000000000000000010101003A +:105370000100000000000001010101010101010123 +:105380000000000000000001010101010101010114 +:105390000000000000000001010101010101010005 +:1053A00001000101000000000101010001010102F2 +:1053B00002020202010000000001000000010002E0 +:1053C00002020201020000000200000001010102CD +:1053D00002020202010202000200000001010102B9 +:1053E00002020201020201020000020201010102A6 +:1053F0000202020202020202010000010101010296 +:10540000020102010201000101010101010101018A +:10541000020001010102010101010101010101027A +:10542000020101010101000100010101010101026C +:10543000010200020001010101000101010101015D +:105440000001010000010001000000010101010153 +:105450000101010001000001010101000101010140 +:105460000100000000000000000000000101010038 +:105470000200000000000001010101010101010121 +:105480000000000000000001010101010101010113 +:105490000000000000000001010101010101010004 +:1054A00002000101000000000101010001010102F0 +:1054B00002020202010100000001000000010002DE +:1054C00002020201020000000200000001010102CC +:1054D00002020202010202000200000001010102B8 +:1054E00002020201020201020000020201010102A5 +:1054F0000202020202020202010000020101010294 +:105500000201020102010001010101010101010189 +:105510000200010101020101010101010101010279 +:10552000020101010101000100010101010101026B +:10553000010200020001010101000101010101015C +:105540000101010000010001000000010101010151 +:10555000010101000100000101010100010101013F +:105560000100000000000000000001000101010036 +:105570000200000000000001010101010101010120 +:105580000000000000000001010101010101010112 +:105590000000000000000001010101010101010003 +:1055A00002010101000000000101010101010102ED +:1055B00002020202010101000001000000020002DB +:1055C00002020201020000000200000001010102CB +:1055D00002020202010202000200000001010102B7 +:1055E00002020201020201020000020201010102A4 +:1055F0000202020202020202010000020101010293 +:105600000201020102010001010101020101010286 +:105610000200010101020101010101010101010278 +:105620000201010101010001010101010101010269 +:10563000010200020001010101010101010101015A +:105640000101010000010001000000010101010150 +:10565000010101000100000101010100010101013E +:105660000100000000000000010101010101010032 +:10567000020000000000000101010101010101011F +:105680000000000001000001010101010101010110 +:105690000000000000010001010101010101010001 +:1056A00002010101000000010101010101010102EB +:1056B00002020202010101000001000000020002DA +:1056C00002020201020000000200000001010102CA +:1056D00002020202010202000200000001010102B6 +:1056E00002020201020201020000020201010102A3 +:1056F0000202020202020202010000020101010292 +:105700000202020102020001010101020101010283 +:105710000201010101020101020101010101010275 +:105720000201010101010101010101010101010267 +:105730000102010200010101010101010101010257 +:10574000010101000001000100000001010101024E +:10575000020101000100000101010101010101013B +:105760000100010000000000010101010101010030 +:10577000020000000000000101010101010101011E +:10578000000000000100010101010101010101010E +:105790000000000000010001010101010101010000 +:1057A00002010101010100010101010101010102E8 +:1057B00002020202010101000001000000020002D9 +:1057C00002020202020000000200000002010102C7 +:1057D00002020202010202000200000002010102B4 +:1057E00002020201020201020000020201010102A2 +:1057F0000202020202020202010000020101010291 +:105800000202020202020001010101020101010281 +:105810000201020101020101020101010101010273 +:105820000201010101010101010101010101010266 +:105830000202010201010101010101010101010254 +:10584000010101000001000100000001010101024D +:10585000020101000100000101010101010101013A +:10586000010001000000000001010101010101002F +:10587000020000000101000101010101010101011B +:10588000000000000101010101010101010101010C +:1058900000000001010100010101010101010100FD +:1058A00002010101010101010101010101010102E6 +:1058B00002020202020101000001000000020002D7 +:1058C00002020202020000000200000002020102C5 +:1058D00002020202010202000200000002010202B2 +:1058E00002020201020202020000020201010102A0 +:1058F0000202020202020202010000020101010290 +:105900000202020202020001010101020101010280 +:105910000201020101020101020101010101010272 +:105920000202010101010101010101010101010264 +:105930000202010201020101010101010101010252 +:105940000101010101010001000100010101010249 +:105950000201010101000001010101010101010138 +:10596000010001000000000101010101010101002D +:105970000200000001010101010101010101010119 +:10598000000000000101010101010101010101010B +:1059900000000001010101010101010101010100FB +:1059A00002010101010101010101010101010102E5 +:1059B00002020202020101010002000000020002D4 +:1059C00002020202020000000200000002020202C3 +:1059D00002020202010202000200000002010202B1 +:1059E000020202020202020200000202010101029E +:1059F000020202020202020201000102010101028E +:105A0000020202020202000101010102020101027E +:105A10000201020101020101020101010101010271 +:105A20000202010101010101010101010101010263 +:105A30000202010201020101010101010101010251 +:105A40000101010101010001000101010101010247 +:105A50000201010101000001010101010101010236 +:105A6000010001000000000101010101010101002C +:105A70000200000101010101010101010101010117 +:105A80000000000101010101010101010101010109 +:105A900001010001010101010101010101010100F8 +:105AA00002010201010101010101010101010102E3 +:105AB00002020202020201010002000000020002D2 +:105AC00002020202020000000200000002020202C2 +:105AD00002020202020202000200000002020202AE +:105AE000020202020202020200000202020101029C +:105AF000020202020202020201000102010101028D +:105B0000020202020202000201010102020101027C +:105B1000020102010102020102010101010101026F +:105B20000202020101010101010101020101010260 +:105B30000202010201020101010101010101010250 +:105B40000101010101010001000101010101010246 +:105B50000201010101010001010101010101010234 +:105B6000010001000000000101010101010101002B +:105B70000200000101010101010101010101010116 +:105B80000000010101010101010101010101010107 +:105B900001010101010101010101010101010100F6 +:105BA00002010202010101010101010101010102E1 +:105BB00002020202020202010002000000020002D0 +:105BC00002020202020100000200000002020202C0 +:105BD00002020202020202000200000002020202AD +:105BE000020202020202020200000202020102029A +:105BF000020202020202020201000102010102028B +:105C0000020202020202000201010102020101027B +:105C1000020102010102020102010101010101026E +:105C2000020202010102010101010102010101025E +:105C3000020201020102020101010101010101024E +:105C40000102010101010001000101010101010244 +:105C50000202010101010001010101010101010232 +:105C6000010001000000000101010101010101002A +:105C70000200000101010101010101010101010115 +:105C80000101010101010101010101010101010104 +:105C900001010101010101010101010101010100F5 +:105CA00002010202010101010101010101010102E0 +:105CB00002020202020202010102000000020002CE +:105CC00002020202020100000200000002020202BF +:105CD00002020202020202000200000002020202AC +:105CE0000202020202020202000002020201020299 +:105CF0000202020202020202010101020101020289 +:105D0000020202020202000201010102020101027A +:105D1000020102010202020102010101010101026C +:105D2000020202010102010101010102010101025D +:105D3000020201020102020101010101010101024D +:105D40000202010101020001000101010101010241 +:105D50000202010101010001010101010101010231 +:105D60000100010000000001010101010101010029 +:105D70000200010101010101010101010101010113 +:105D80000101010101010101010101010101010202 +:105D900001010101010101010101010101010100F4 +:105DA00002010202010101010101010101010102DF +:105DB00002020202020202010102000000020002CD +:105DC00002020202020100000200000002020202BE +:105DD00002020202020202000200000002020202AB +:105DE0000202020202020202000002020202020297 +:105DF0000202020202020202010101020102020287 +:105E00000202020202020002010201020202010277 +:105E10000202020202020201020101010101010269 +:105E2000020202020102010101010102010101025B +:105E3000020201020102020102010101010101024B +:105E40000202010101020001000101010101010240 +:105E5000020201010101010101010101010101022F +:105E60000200010000010001010101010101010125 +:105E70000201010101010101010101010101010210 +:105E80000101010101010101010101010101010201 +:105E900001010101010101010101010101010100F3 +:105EA00002010202010101010101010101010102DE +:105EB00002020202020202010102000000020002CC +:105EC00002020202020100000200000002020202BD +:105ED00002020202020202000200000002020202AA +:105EE0000202020202020202000002020202020296 +:105EF0000202020202020202010101020202020285 +:105F00000202020202020002010201020202020275 +:105F10000202020202020201020101010101010268 +:105F2000020202020102010101010102010101025A +:105F3000020201020102020102010101010101024A +:105F4000020202010102000101010101010101023D +:105F5000020202010101010101010101010101022D +:105F60000200010000010001010101010101010124 +:105F7000020101010101010101010101010101020F +:105F80000101010101010101010101010101010200 +:105F900001010101010101010101010101010100F2 +:105FA00002010202010101010101010101010102DD +:105FB00002020202020202020102000001020002C9 +:105FC00002020202020100000200000002020202BC +:105FD00002020202020202000200000002020202A9 +:105FE0000202020202020202010002020202020294 +:105FF0000202020202020202020101020202020283 +:106000000202020202020002010201020202020274 +:106010000202020202020202020201010101010265 +:106020000202020201020101010101020101010259 +:106030000202020201020201020101010101010248 +:10604000020202010102010101010101010101023B +:10605000020202010101010101010101010101022C +:106060000200010101010001010101010101010121 +:10607000020101010101010101010101010101020E +:1060800001010101010101010101010101010102FF +:1060900001010101010101010101010101010100F1 +:1060A00002010202010101010101010101010102DC +:1060B00002020202020202020102000001020002C8 +:1060C00002020202020200000200000002020202BA +:1060D00002020202020202000200000002020202A8 +:1060E0000202020202020202010002020202020293 +:1060F0000202020202020202020101020202020282 +:106100000202020202020002020201020202020272 +:106110000202020202020202020201010101010264 +:106120000202020201020101010101020201020256 +:106130000202020201020201020101010201020245 +:10614000020202010102010101010101010101023A +:10615000020202010201010101010101010101022A +:10616000020001010101010101010101010101011F +:10617000020101010101010101010101010101020D +:1061800001010101010101010101010101010102FE +:1061900001010101010101010101010101010100F0 +:1061A00002010202010101010101010101010102DB +:1061B00002020202020202020202000001020002C6 +:1061C00002020202020200000200000002020202B9 +:1061D00002020202020202000200000002020202A7 +:1061E0000202020202020202010102020202020291 +:1061F0000202020202020202020101020202020281 +:106200000202020202020002020201020202020271 +:106210000202020202020202020201010101010263 +:106220000202020202020101010101020201020254 +:106230000202020201020201020101010201020244 +:106240000202020101020101010101010101010239 +:106250000202020102010101010101010101010229 +:10626000020101010101010101010101010101011D +:10627000020101010101010101010101010101020C +:1062800001010101010101010101010101010102FD +:1062900001010101010101010101010101010100EF +:1062A00002010202010101010101010101010102DA +:1062B00002020202020202020202000101020002C4 +:1062C00002020202020200010200000002020202B7 +:1062D00002020202020202000200000002020202A6 +:1062E0000202020202020202010102020202020290 +:1062F0000202020202020202020101020202020280 +:10630000020202020202000202020202020202026F +:10631000020202020202020202020202010102025F +:106320000202020202020101010101020201020253 +:106330000202020201020201020101010201020243 +:106340000202020101020101010101010101010238 +:106350000202020102010101010101010101020227 +:10636000020101010101010101010101010101011C +:10637000020101010101010101010101010101020B +:1063800001010101010101010101010101010102FC +:1063900001010101010101010101010101010100EE +:1063A00002010202010101010101010101010102D9 +:1063B00002020202020202020202000101020002C3 +:1063C00002020202020200010200000002020202B6 +:1063D00002020202020202000200000002020202A5 +:1063E000020202020202020201010202020202028F +:1063F000020202020202020202010202020202027E +:10640000020202020202000202020202020202026E +:10641000020202020202020202020202020102025D +:106420000202020202020101010101020201020252 +:106430000202020201020202020101020201020240 +:106440000202020101020102010101010101020235 +:106450000202020102010101010101010101020226 +:10646000020102010101010101010101010101011A +:10647000020101010101010101010101010101020A +:1064800002010101010101010101010101010102FA +:1064900002010101010101010101010101010100EC +:1064A00002010202010101010101010101010102D8 +:1064B00002020202020202020202000202020002C0 +:1064C00002020202020200020200000002020202B4 +:1064D00002020202020202000200000102020202A3 +:1064E000020202020202020201010202020202028E +:1064F000020202020202020202010202020202027D +:10650000020202020202000202020202020202026D +:10651000020202020202020202020202020102025C +:106520000202020202020102010101020201020250 +:10653000020202020202020202010102020102023E +:106540000202020101020102010101010101020234 +:106550000202020102010101010101010102020224 +:106560000201020101010101010101010101010218 +:106570000201010101010101010101010101010209 +:1065800002010101010101010101010101010102F9 +:1065900002010101010101010101010101010100EB +:1065A00002020202010101010101010101010102D6 +:1065B00002020202020202020202000202020002BF +:1065C00002020202020200020200000002020202B3 +:1065D00002020202020202010200000102020202A1 +:1065E000020202020202020201010202020202028D +:1065F000020202020202020202020202020202027B +:10660000020202020202000202020202020202026C +:10661000020202020202020202020202020202025A +:10662000020202020202020201020202020202024B +:10663000020202020202020202010202020102023C +:106640000202020201020102010101010101020232 +:106650000202020202010101010101010102020222 +:106660000201020101010101010101010101010217 +:106670000201010101010101010101010101010208 +:1066800002010101010101010101010101010102F8 +:1066900002010101010101010101010101010100EA +:1066A00002020202010101010101010101010102D5 +:1066B00002020202020202020202000202020002BE +:1066C00002020202020202020200000002020202B0 +:1066D000020202020202020102010002020202029E +:1066E000020202020202020202010202020202028B +:1066F000020202020202020202020202020202027A +:10670000020202020202000202020202020202026B +:106710000202020202020202020202020202020259 +:10672000020202020202020201020202020202024A +:10673000020202020202020202010202020202023A +:106740000202020201020102010101010101020231 +:106750000202020202010101010201010102020220 +:106760000201020101010101010101010101010216 +:106770000201010101010101010101010101010207 +:1067800002020101010101010101010101010102F6 +:1067900002020101010101010101010101010100E8 +:1067A00002020202010101010101010101010202D3 +:1067B00002020202020202020202000202020002BD +:1067C00002020202020202020200000002020202AF +:1067D000020202020202020202020002020202029B +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:10680000020202020202000202020202020202026A +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:10684000020202020202010201010101010202022E +:10685000020202020201010201020101010202021E +:106860000201020101010101010101010101010215 +:106870000202010101010101010101010101020204 +:1068800002020201010101010101010101010102F4 +:1068900002020101010101010101010101010100E7 +:1068A00002020202010101010101010101010202D2 +:1068B00002020202020202020202000202020002BC +:1068C00002020202020202020200000002020202AE +:1068D000020202020202020202020002020202029A +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020002020202020202020269 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:10694000020202020202010201010101010202022D +:10695000020202020201010202020101020202021B +:106960000202020101010101010101010101010213 +:106970000202020101010101010101010101020202 +:1069800002020201010101010101010101010202F2 +:1069900002020201010101010101010101010100E5 +:1069A00002020202010101010101010101010202D1 +:1069B00002020202020202020202020202020002B9 +:1069C00002020202020202020200000202020202AB +:1069D0000202020202020202020201020202020298 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020002020202020202020268 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A4000020202020202010201010102010202022B +:106A50000202020202020102020201010202020219 +:106A60000202020101010101010101010101020211 +:106A700002020202010101010102010101020202FE +:106A800002020202020101010202010102020202EB +:106A900002020202010101010101010101010100E3 +:106AA00002020202010101010101010101010202D0 +:106AB00002020202020202020202020202020002B8 +:106AC00002020202020202020200000202020202AA +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020002020202020202020267 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B4000020202020202010201010102010202022A +:106B50000202020202020102020202010202020217 +:106B60000202020101010101010101010101020210 +:106B700002020202020101020102010102020202FA +:106B800002020202020101020202020102020202E8 +:106B900002020202010101010101010101010100E2 +:106BA00002020202010101010101010101010202CF +:106BB00002020202020202020202020202020002B7 +:106BC00002020202020202020202000202020202A7 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020002020202020202020266 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020102010101020202020228 +:106C50000202020202020202020202010202020215 +:106C6000020202020101010101010101010202020D +:106C700002020202020201020202020202020202F5 +:106C800002020202020202020202020202020202E4 +:106C900002020202020201010101010101010100DF +:106CA00002020202020101010101010101010202CD +:106CB00002020202020202020202020202020002B6 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020002020202020202020265 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202010201020202020225 +:106D50000202020202020202020202020202020213 +:106D6000020202020101010102010101010202020B +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020201020202010101010200DA +:106DA00002020202020201010101010101010202CB +:106DB00002020202020202020202020202020002B5 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020102020202020202020263 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202010202020202020223 +:106E50000202020202020202020202020202020212 +:106E60000202020202020102020202010102020205 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020102020200D5 +:106EA00002020202020202010202010101010202C7 +:106EB00002020202020202020202020202020002B4 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020102020202020202020202 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020200D3 +:106FA00002020202020202020202020101010202C4 +:106FB00002020202020202020202020202020002B3 +:106FC00002020202020202020102020202020202A2 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020200D2 +:1070A00002020202020202020202020102010202C2 +:1070B00002020202020202020202020202020002B2 +:1070C00002020202010202020102020202020202A2 +:1070D0000202020202020102020202020202020291 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020101020002B3 +:1071C00002020202010202020102020102020202A2 +:1071D0000202020202010202020202020202020290 +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020101020002B2 +:1072C00002020102010202010102020102020202A3 +:1072D0000202020202020102010202010202020291 +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002010101010101010101010101010102BB +:1073C00002020102010202010101010101010202A6 +:1073D0000202020202010102020102020101020292 +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002010101010101010101010101010102BA +:1074C00001010101010101010101010101010102AB +:1074D0000202020102010102010201010202020292 +:1074E000020202020202020102020202020202027D +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00001010101010101010101010101010102BA +:1075C00001010101010101010101010101010102AA +:1075D0000201010201010101010102010101010297 +:1075E000020202020202020202020201020202027C +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00001010101010101010101010101010102B9 +:1076C00001010101010101010101010101010102A9 +:1076D0000102020102010102010101010101020294 +:1076E000020202020101020102020102020202027E +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020201BA +:1077B00001010101010101010101010101010101B9 +:1077C00001010101010101010101010101010102A8 +:1077D0000201010101010101010101010101010297 +:1077E000020202020202010102010201010102027F +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020201B9 +:1078B00001010101010101010101010101010101B8 +:1078C00001010101010101010101010101010101A8 +:1078D0000101010101010101010101010101010297 +:1078E000020201020101020101020101020202027F +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020201B8 +:1079B00001010101010101010101010101010101B7 +:1079C00001010101010101010101010101010102A6 +:1079D0000101010101010101010101010101010296 +:1079E0000101020101010101020101010101010284 +:1079F0000202020202020102020202020202020268 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020201B7 +:107AB00001010101010101010101010101010101B6 +:107AC00001010101010101010101010101010101A6 +:107AD0000101010101010101010101010101010295 +:107AE0000202010201010101010101010101020281 +:107AF000020202020201010102020101020202026B +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020201B6 +:107BB00001010101010101010101010101010101B5 +:107BC00001010101010101010101010101010101A5 +:107BD0000101010101010101010101010101010195 +:107BE0000101010101010101010101010101010284 +:107BF0000202010101010101010101010102020270 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020201B5 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD0000101010101010101010101010101010293 +:107CE0000101010101010101010101010101010283 +:107CF0000202010101010101010101010101020270 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020201B4 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010282 +:107DF0000101010101010101010101010101010272 +:107E00000202020202020202020202020202020252 +:107E10000202020202020202020202020202020242 +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020202C2 +:107EA00002020202020202020202020202020201B3 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010281 +:107EF0000101010101010101010101010101010271 +:107F00000202020201010202020202010202020254 +:107F10000202020202020202020202020202020241 +:107F20000202020202020202020202020202020231 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020202C1 +:107FA00002020202020202020202020202020201B2 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010280 +:107FF0000101010101010101010101010101010270 +:108000000202010201010201010101010102020259 +:108010000202020202020202020202020202020240 +:108020000202020202020202020202020202020230 +:108030000202020202020202020202020202020220 +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202020202020202020202C0 +:1080A00002020202020202020202020202020201B1 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F000010101010101010101010101010101026F +:10810000020201010101020101010101010102025A +:108110000202020202010202020202020202020240 +:10812000020202020202020202020202020202022F +:10813000020202020202020202020202020202021F +:10814000020202020202020202020202020202020F +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202020202020202020202BF +:1081A00002020202020202020202020202020201B0 +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101026E +:10820000010101010101010101010101010101025D +:108210000202020202010102010201010202020243 +:10822000020202020202020202020202020202022E +:10823000020202020202020202020202020202021E +:10824000020202020202020202020202020202020E +:1082500002020202020202020202020202020202FE +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202020202020202020202BE +:1082A00002020202020202020202020202020201AF +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101026D +:10830000010101010101010101010101010101025C +:108310000202010201010101010101010101020248 +:10832000020202020202020202020202020202022D +:10833000020202020202020202020202020202021D +:10834000020202020202020202020202020202020D +:1083500002020202020202020202020202020202FD +:1083600002020202020202020202020202020202ED +:1083700002020202020202020202020202020202DD +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020202BD +:1083A00002020202020202020202020202020201AE +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101025B +:108410000102010101010101010101010101020249 +:10842000020202020202020202020202020202022C +:10843000020202020202020202020202020202021C +:10844000020202020202020202020202020202020C +:1084500002020202020202020202020202020202FC +:1084600002020202020202020202020202020202EC +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020202BC +:1084A00002020202020202020202020202020201AD +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101025A +:10851000010101010101010101010101010101024A +:10852000020202020201020202020201020202022D +:108530000201020102010102020201020202020220 +:10854000020202020202020202020202020202020B +:1085500002020202020202020202020202020202FB +:1085600002020202020202020202020202020202EB +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020201AC +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:108610000101010101010101010101010101010249 +:108620000101010101010101010101010102020237 +:10863000020202020202020101010201010202021F +:10864000020202020202020202020202020202020A +:1086500002020202020202020202020202020202FA +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202020202DA +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020201AB +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010102020201020201010223 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020201AA +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010237 +:108830000201020102010101010101010102020222 +:108840000202020202020202020202020202020208 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202020202020202020202D8 +:1088800002020202020202020202020202020202C8 +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202020201A9 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010226 +:108940000202020202010202020202020202020208 +:1089500002020202020202020202020202020202F7 +:1089600002020202020202020202020202020202E7 +:1089700002020202020202020202020202020202D7 +:1089800002020202020202020202020202020202C7 +:1089900002020202020202020202020202020202B7 +:1089A00002020202020202020202020202020201A8 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010225 +:108A4000020101020201020102020201020202020B +:108A500001010102010202020202020202020202FA +:108A600002020202020202020202020202020202E6 +:108A700002020202020202020202020202020202D6 +:108A800002020202020202020202020202020202C6 +:108A900002020202020202020202020202020202B6 +:108AA00002020202020202020202020202020201A7 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000202020102010101010101010101010200 +:108B600002020202020202020202020202020202E5 +:108B700002020202020202020202020202020202D5 +:108B800002020202020202020202020202020202C5 +:108B900002020202020202020202020202020202B5 +:108BA00002020202020202020202020202020201A6 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010213 +:108C500001010102010202020202020202020202F8 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202020202020202020202C4 +:108C900002020202020202020202020202020202B4 +:108CA00002020202020202020202020202020201A5 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010202 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202020202D3 +:108D800002020202020202020202020202020202C3 +:108D900002020202020202020202020202020202B3 +:108DA00002020202020202020202020202020201A4 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001020102020202020202020202020202E4 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202020202020202020202C2 +:108E900002020202020202020202020202020202B2 +:108EA00002020202020202020202020202020201A3 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010102F0 +:108F700001020202020202020202020202020202D2 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020202020202020201A2 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010102EF +:1090700001020202020202020202020202020202D1 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020202020202020202020201A1 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010102EE +:1091700001010101010101010101010101010102DE +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A00002020202020202020202020202020201A0 +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010102CD +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202019F +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010102CC +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202019E +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010102BB +:1094A000020202020202020202020202020202019D +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010102BA +:1095A000020202020202020202020202020202019C +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010102B9 +:1096A000020202020202020202020202020202019B +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010102B8 +:1097A000010201010202020202020202020201019E +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010102B7 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010102B6 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010296 +:1099C0000202020202020202020202020202020277 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020202020226 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020200A8 +:109AA00000000000000000000000000000000001B5 +:109AB0000101010101010101010101010101010295 +:109AC0000202020202020202020202020202020276 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020200A7 +:109BA00000000000000000000000000000000001B4 +:109BB0000101010101010101010101010101010096 +:109BC0000000000000000000000000000000000293 +:109BD0000202020202020202020202020202020265 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020200D6 +:109C700000000000000000000000000000000002E2 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020200A6 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA000000000000000000000000000000000654E +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000100000051 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000100000100000000000080 +:109EE0000000000000000100000000000000000071 +:109EF0000000000000000000000001000000000061 +:109F00000000000000000000000000000100000050 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD000000000000000010000010000000000007F +:109FE0000000000000000100000000000000000070 +:109FF000000000000000010000000100010000005E +:10A00000000000000000000000000000010000004F +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D000000000000000010000010000000101007C +:10A0E000000000000000010000000000000000016E +:10A0F000000000000000010000000100010000005D +:10A10000000000000000000000000000010000004E +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000010000000000000000000E +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000100000000000000009E +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000010000010000000101007B +:10A1E000000000000000010000000000000100016C +:10A1F000000000000000010000000101010000005B +:10A20000000000000000000000000000010000004D +:10A21000000000000000000000000000000101003C +:10A22000000000000000010000000000000000002D +:10A23000000000000000010000000000000000001D +:10A24000000000000000010000000000000000000D +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000100000000000000009D +:10A2C000000000000000000000000100000000008D +:10A2D000000000000000010000010000000101007A +:10A2E000000000000000010100000000000100016A +:10A2F000000000000000010000000101010000005A +:10A30000000000000000010000000000010000004B +:10A31000000000000000010000000000000101003A +:10A32000000000000000010000000000000000002C +:10A33000000000000000010000000000000100001B +:10A34000000000000000010000000000000000000C +:10A3500000000000000001000000000000000000FC +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000100000000000000009C +:10A3C000000000000000000000000100000000008C +:10A3D0000000000000000100000100000001010079 +:10A3E0000000000000000101000101000001000167 +:10A3F0000000000000000100000001010100000059 +:10A40000000000000000010000000000010000004A +:10A410000000000000000100000000000001010039 +:10A42000000000000000010000000000000000002B +:10A43000000000000000010000000000000100001A +:10A44000010000000000010000000000000000000A +:10A4500000000000000001000000000000000000FB +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000100000000000000009B +:10A4C000000000000000000000000100000000008B +:10A4D0000000000000000100000100000001010078 +:10A4E0000000000000000101000101000101000165 +:10A4F0000000000000000100000101010101000056 +:10A500000000000000000100000000000100000049 +:10A510000000000000000100000000000001010038 +:10A520000100000000000100000000010000000028 +:10A530000000000000000100000000000001000019 +:10A540000100000000000100000000000000000009 +:10A5500000000000000001000000000000000000FA +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B0000000000000000001010000000000000099 +:10A5C000000000000000000000000100000000008A +:10A5D0000000000000000101000100000001010076 +:10A5E0000000000000000101000101000101000164 +:10A5F0000000000000000100000101010101000055 +:10A600000000000000000100000000010100000047 +:10A610000000000000000100000000000001010037 +:10A620000100000000000100000000010000000027 +:10A630000000000000000100000000000001000018 +:10A640000100000000000100000000000000000008 +:10A6500000000000000001000000000000000000F9 +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B0000000000000000001010000000000000098 +:10A6C0000000000000000000000001000000000089 +:10A6D0000000000000000101000101000001010074 +:10A6E0000000000000000101000101000101000163 +:10A6F0000000000000000100000101010101010053 +:10A700000000000000000100000000010100000046 +:10A710000000000000000100000000000001010036 +:10A720000100000000000100000000010000000026 +:10A730000000000000000100000000000001000017 +:10A740000100000000000100000000000000000007 +:10A7500000000000000001000000000000000000F8 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000001000000000000000000B8 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000001010000000000000097 +:10A7C0000000000000000001000001000000000087 +:10A7D0000000000000000101000101010001010072 +:10A7E0000100000000000101000101000101010160 +:10A7F0000000000000000100000101010101010052 +:10A800000000000000000101000000010100000044 +:10A810000000000000000100000000000001010035 +:10A820000100000000000100000000010001000024 +:10A830000000000000000100000000000001000016 +:10A840000100000000000100000000000000000006 +:10A8500000000000000001000000000000010000F6 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000001000000000000000000C7 +:10A8900000000000000001000000000000000000B7 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000001010000000000000096 +:10A8C0000000000000000001000101000000000085 +:10A8D0000000000000000101000101010001010071 +:10A8E000010000000000010100010101010101015E +:10A8F0000000000000000100000101010101010051 +:10A900000000000000000101000001010100000042 +:10A910000000000000000100010000010001010032 +:10A920000100000000000101000000010001000022 +:10A930000000000000000100000000000001010014 +:10A940000100000000000100000000000000000005 +:10A9500000000000000001000000000000010000F5 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000001000000000000000000C6 +:10A9900000000000000001000000000000000000B6 +:10A9A00000000000000000000100000000000000A6 +:10A9B0000000000000000001010000000000000095 +:10A9C0000000000000000001000101000000000084 +:10A9D0000000000000000101000101010001010070 +:10A9E000010000000000010100010101010101015D +:10A9F0000000000000000100000101010101010050 +:10AA00000000000000000101000001010100000041 +:10AA10000000000001000100010000010001010030 +:10AA20000100000000000101000001010001000020 +:10AA30000000000000000100000000000001010013 +:10AA40000100000000000100000000000000000004 +:10AA500000000000000001000000000000010000F4 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000001000000000000000000C5 +:10AA900000000000000001000000000000000000B5 +:10AAA00000000000000000000100000000000000A5 +:10AAB0000000000000000001010000000000000094 +:10AAC0000000000000000001000101000000000083 +:10AAD000000000000001010100010101000101006E +:10AAE000010000000000010101010101010101015B +:10AAF000000000000000010000010101010101004F +:10AB00000000000000000101000001010100000040 +:10AB1000000000000100010001000001010101012D +:10AB2000010000000000010100000101000100001F +:10AB30000000000000000100000000000001010012 +:10AB40000100000000000100000000000000000003 +:10AB500000000000000001000000000000010000F3 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000001000000000000000000C4 +:10AB900000000000000001000000000000000000B4 +:10ABA00000000000000000000100000000000000A4 +:10ABB000010001010000000201000000000000008F +:10ABC0000000000000000001000101000000000082 +:10ABD000000000000001010100010101000101006D +:10ABE0000100000001000101010101010101010159 +:10ABF000000000000000010000010101010101014D +:10AC0000000000000000010100000101010000003F +:10AC1000000000000100010001000001010101012C +:10AC2000010000000000010100000101000100001E +:10AC30000000000000000100000000000001010011 +:10AC40000100000000000100000000000000000002 +:10AC500000000000000001000001000000010000F1 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000001000000000000000000C3 +:10AC900000000000000001000000000000000000B3 +:10ACA00000000000000000000100000100000000A2 +:10ACB000010001010000000201000000000000008E +:10ACC0000000000000000001000101000000000081 +:10ACD000000000000001010100010101000101006C +:10ACE0000100000001010101010101010101010157 +:10ACF000000000000000010000010101010101014C +:10AD0000000000000000010100000101010100003D +:10AD1000000000000100010101000001010101012A +:10AD2000010000000000010100000101000100001D +:10AD30000000000000000100000000000001010010 +:10AD40000100000000000100000000000000000001 +:10AD500000000000000001000001000000010000F0 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000001000000000000000000C2 +:10AD900000000000000001000000000000000000B2 +:10ADA00000000000000000000100000100000000A1 +:10ADB000010001010000000201000000000000008D +:10ADC000000000000000000101010200000000007E +:10ADD0000000000001010101010101010001010069 +:10ADE0000100000001010101010101010101010156 +:10ADF000000000000000010100010101010101014A +:10AE0000000000000000010100000101010100003C +:10AE10000000000001000101010001010101010128 +:10AE2000010000000000010100000101000100001C +:10AE3000000000000001010000000000000101000E +:10AE400001000000010001000000000000000001FE +:10AE500000000000000001000001000000010000EF +:10AE600000000000000001000000000000000000E1 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000001000000000000000000C1 +:10AE900000000000010001000000000000000000B0 +:10AEA00000000000000000000100000100000000A0 +:10AEB0000101010101000002020001000000000088 +:10AEC000000000000000000101010200000000007D +:10AED0000000000001010101010101010001010068 +:10AEE0000100000001010101010101010101010155 +:10AEF0000000000000000101000101010101010149 +:10AF0000000000000000010100000101010100003B +:10AF10000000000001000101010001010101010127 +:10AF2000010000000000010100000101000100001B +:10AF3000000000000001010000000000000101000D +:10AF400001000001010101000000000000000001FB +:10AF500000000000000001000101000000010000ED +:10AF600000000000000001000000000000000000E0 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000001000000000000000000C0 +:10AF900000000001010101000000000000000000AD +:10AFA000000000000000000001000001000000019E +:10AFB0000101010101010002020002000000000085 +:10AFC000000000000000000101020200000000007B +:10AFD0000000000001010101010201010001010066 +:10AFE0000100000001010101010101010101010154 +:10AFF0000000000000000101010101010101010147 +:10B000000000000000000101010001010101000039 +:10B010000000000001000101010001010101010126 +:10B02000010000000000010100000101000100001A +:10B03000000000000001010000000000000101000C +:10B0400001000001010101000000000000000001FA +:10B0500000000000000001000101000000010000EC +:10B0600000000000000001000100000000000000DE +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000001000000000000000000BF +:10B0900000000101010101000000000000000000AB +:10B0A000000000000000000001000001010000019C +:10B0B0000101010101010002020102000000000083 +:10B0C000000000000000000101020200000000007A +:10B0D0000000000001010101010201010001010065 +:10B0E0000100000001010101010101010101010153 +:10B0F0000000010000000101010102010101010144 +:10B100000000000100000101010001010101000037 +:10B110000000000001010101010001010101010124 +:10B120000100000001000101000001010001000018 +:10B13000000000000001010000000000000101000B +:10B1400001000001010101000000000000000001F9 +:10B1500000000001000001000101000000010001E9 +:10B1600000000000000001000100000000000000DD +:10B1700000000000000000000000000000000000CF +:10B1800000000000000001000000000000000000BE +:10B1900000000101010101000000000000000000AA +:10B1A0000000000000000000010001010101010198 +:10B1B0000101010101010002020202000000000081 +:10B1C0000000000000000001010202000000000079 +:10B1D0000000000001010101010201010101010063 +:10B1E0000100010001010102010101010101010150 +:10B1F0000000010000000101010102010101010143 +:10B200000000000100000101010001010101000036 +:10B210000000000001010101010001010101010123 +:10B220000101000001000101000001010001000016 +:10B23000000000000001010000000000000101000A +:10B2400001000001010101000100000000000001F7 +:10B2500000000001000001000101000000010001E8 +:10B2600000000000000001000100000000000000DC +:10B2700000000000000000000000000000000000CE +:10B2800000000000000001000000000000000000BD +:10B2900001000101010101000000000000000000A8 +:10B2A0000000000000000100010001010101010196 +:10B2B0000101010101010002020202000000000080 +:10B2C0000000000000000002010202000000000077 +:10B2D0000000000001010101010201010101010062 +:10B2E000010001010101010201020101010101014D +:10B2F0000000010000000101010202010101010141 +:10B300000000000100000101010001010101000035 +:10B310000000000001010101010001010101010122 +:10B320000101000001000101010001010001000014 +:10B330000000000001010100000000000001010008 +:10B3400001000001010101000100010000000001F5 +:10B3500000000001000101000101000000010001E6 +:10B3600000000000000001000100000000000000DB +:10B3700000000000000001000000000000000000CC +:10B3800000000000000001000000000000000000BC +:10B3900001000101010101000000000000000000A7 +:10B3A0000000000000000100010001010101010195 +:10B3B000010101010101000202020200000000007F +:10B3C0000000000000000002010202000000000076 +:10B3D0000000000001010101010201010101010061 +:10B3E000010001010101010201020201010101014B +:10B3F000000001000001010101020201010101013F +:10B400000000000100000101010001010101000034 +:10B410000000000001010101010101010101010120 +:10B420000101000101010101010001010001000011 +:10B430000000000101010100010000010101010003 +:10B4400001000001010101000100010000000001F4 +:10B4500000000101010101000101000000010001E3 +:10B4600000000000000001000100000000000000DA +:10B4700000000000000001000000000000000000CB +:10B4800000000001000101000000000000000000B9 +:10B4900001000101010101000000000000000000A6 +:10B4A0000000000000000100010001010101010194 +:10B4B000010101010101000202020200000000007E +:10B4C0000000000000000002010202000000000075 +:10B4D000000000000101010201020101010101005F +:10B4E000010001010101010201020201010101014A +:10B4F000010001000001010101020201010101013D +:10B500000000000100000101010001010101010032 +:10B51000000000000101010101010101010101011F +:10B520000101000101010101010001010001000010 +:10B530000000000101010100010100010101010001 +:10B5400001000001010101000101010000000001F2 +:10B5500000000101010101000101000000010001E2 +:10B5600000000000000001000100000000000000D9 +:10B5700000000000000001000000000000000000CA +:10B5800000000001010101000000000000000000B7 +:10B5900001010101010101010000000000000000A3 +:10B5A0000000000000000100010001010101010193 +:10B5B000010101010101010202020200000000007C +:10B5C0000000000000000002010202000000000074 +:10B5D000000000000101010201020101010101005E +:10B5E0000100010101010102010202010101010149 +:10B5F000010001000001010101020202010101013B +:10B60000000000010100010201000101010101002F +:10B61000000000000101010101010101010101011E +:10B62000010100010101010101000101000100000F +:10B6300000000001010101010101000101010100FF +:10B6400001000001010101010101010000000001F0 +:10B6500000000101010101000101000000010001E1 +:10B6600000000000000001000100000000000000D8 +:10B6700000000000000001000000000000000000C9 +:10B6800000000001010101000100000000000000B5 +:10B6900001010101010101010000000000000000A2 +:10B6A0000000000000000100010001010101010192 +:10B6B000010101010101010202020200000000007B +:10B6C0000000000000000002020202000000000072 +:10B6D000000000000101010201020201010101005C +:10B6E0000100010101010102010202010101010148 +:10B6F0000100010000010101010202020201010139 +:10B70000000000010100010201000101010101002E +:10B71000000000010101010101010101010101011C +:10B72000010100010101010101000101000100000E +:10B7300000000101010101010101010101010100FC +:10B7400001000001010101010101010000000001EF +:10B7500000000101010101000101000000010001E0 +:10B7600000000000000001000100000000000000D7 +:10B7700000000000000001000000000000000000C8 +:10B7800000000101010101000100000000000000B3 +:10B7900001010101010101010000000000000000A1 +:10B7A000000001000000010001010101010101018F +:10B7B000010101010101010202020200000000007A +:10B7C0000000000000000002020202000000000071 +:10B7D000000000000101010201020201010201005A +:10B7E0000100010101010102010202010102010146 +:10B7F0000100010000010102010202020201010137 +:10B80000000000010100010201000101020101002C +:10B81000000000010101010101010101010101011B +:10B82000010100010101010101010101000100000C +:10B8300000000101010101010101010101010100FB +:10B8400001000001010101010101010000000001EE +:10B8500000000101010101000101000000010001DF +:10B8600000000000000001000100000000000000D6 +:10B8700000000000000001000000000000000000C7 +:10B8800000000101010101000100000000000000B2 +:10B8900001010101010101010000000000000000A0 +:10B8A000000001010000010001010101010101018D +:10B8B0000101010101010102020202000000000079 +:10B8C000000000000001000202020200000000006F +:10B8D0000000000001010102010202010102020058 +:10B8E0000100010101010102020202010102010144 +:10B8F0000100010000010102010202020202010135 +:10B90000000000010100010201000201020101002A +:10B910000001000101010101020101010101010118 +:10B92000010100010101010201010101000100000A +:10B9300000000101010101010101010101010100FA +:10B9400001000001010101010101010000000001ED +:10B9500000000101010101010101000000010001DD +:10B9600000000000000001000100000000000000D5 +:10B9700000000000000001000000000000000000C6 +:10B9800000000101010101000100000000000000B1 +:10B99000010101010101010100000000000000009F +:10B9A000000001010100010001010101010101018B +:10B9B0000101010101010102020202000000000078 +:10B9C000000000000001000202020200000000006E +:10B9D0000000000001010102010202010102020057 +:10B9E0000100010101010102020202010202010241 +:10B9F0000100010100010102010202020202010133 +:10BA00000000000101000102010002010201010128 +:10BA10000001000101010102020101010101010116 +:10BA20000101000101010102010101010001000009 +:10BA300000000101010101010101010101010100F9 +:10BA400001000001010101010101010000000001EC +:10BA500000000101010101010101000000010001DC +:10BA600000000000000101000100000000000000D3 +:10BA700000000000000001000000000000000000C5 +:10BA800000000101010101000100000000000001AF +:10BA9000010101010101010100000000000000009E +:10BAA0000000010101010100010101010101010189 +:10BAB0000101010101010102020202000000000077 +:10BAC000000000000001000202020200000000006D +:10BAD0000000000001010102010202020102020055 +:10BAE000010001010101010202020202020201023F +:10BAF0000100010100010102020202020202020130 +:10BB00000000000101000102010002020201010126 +:10BB10000001000101010102020101010101010115 +:10BB20000101010101010102010101010001000007 +:10BB300000000101010101010101010101010100F8 +:10BB400001000001010101010101010000000001EB +:10BB500000000101010101010101000000010001DB +:10BB600000000000010101000100000000000000D1 +:10BB700000000000000001000100000000000000C3 +:10BB800000000101010101000100000000000001AE +:10BB9000010101010101010100000000000000009D +:10BBA0000000010101010100010101010101010188 +:10BBB0000101010101010102020202000000000076 +:10BBC000000000000001000202020200000000006C +:10BBD0000000000001010102020202020102020053 +:10BBE000010001010101010202020202020201023E +:10BBF000010001010001010202020202020202012F +:10BC00000000010101000102020002020201010123 +:10BC10000001000101010102020101010102010113 +:10BC20000101010101010102010101010001000006 +:10BC300000000101010101010101010101010100F7 +:10BC400001000101010101010101010000000001E9 +:10BC500000000101010101010101000000010001DA +:10BC600000000001010101010100000000000000CE +:10BC700000000000000001000100000000000000C2 +:10BC800000010101010101000100000000000001AC +:10BC9000010101010101010100000000000000009C +:10BCA0000000010101010100010101010101010187 +:10BCB0000101010101010102020202000000000075 +:10BCC000000000000001000202020200000000006B +:10BCD0000000000001010102020202020102020052 +:10BCE000010001010101010202020202020202023C +:10BCF000010001010101010202020202020202012D +:10BD00000000010101010102020102020201010120 +:10BD10000001000101010102020102010102020110 +:10BD20000101010101010102010102010101000003 +:10BD300000000101010101010101010101010100F6 +:10BD400001000101010101010101010000000001E8 +:10BD500000000101010101010101000000010001D9 +:10BD600000000101010101010100000000000000CC +:10BD700000000001000001000100000000000000C0 +:10BD800000010101010101000100000000000001AB +:10BD9000010101010101010101000000000000009A +:10BDA0000100010101010100010101010101010185 +:10BDB0000101010101010102020202000000000074 +:10BDC000000000000001000202020200000000006A +:10BDD0000000010001010102020202020102020050 +:10BDE000010001010101010202020202020202023B +:10BDF000010001010101010202020202020202012C +:10BE0000000001010101010202010202020101011F +:10BE1000000101010101010202010202010202010D +:10BE20000101010101010102010102020101000001 +:10BE300000010101010101010101010101010100F4 +:10BE400001000101010101010101010000000001E7 +:10BE500000000101010101010102000000010101D6 +:10BE600000000101010101010100000000000000CB +:10BE700000000001000001000100000000000000BF +:10BE800000010101010101000100000000000001AA +:10BE90000101010101010101010000000000000099 +:10BEA0000101010101010100000101010101010184 +:10BEB0000101010101010102020202000000000073 +:10BEC0000000000000010002020202000000000069 +:10BED000000001000101010202020202010202004F +:10BEE000010001010101010202020202020202023A +:10BEF000010001010101010202020202020202012B +:10BF0000000001010101010202010202020101011E +:10BF1000000101010101010202020202010202010B +:10BF20000101010101010102010102020101000000 +:10BF300000010101010101010101010101020100F2 +:10BF400001010101010101010101010000000001E5 +:10BF500000010101010101010102000101010101D2 +:10BF600000000101010101010101000000000000C9 +:10BF700000000001000101000100000000000000BD +:10BF800001010101010101000100000000000001A8 +:10BF90000101010101010101010000000000000098 +:10BFA0000101010101010100000101010101010183 +:10BFB0000101010101010102020202010000000071 +:10BFC0000000000000010002020202000000000068 +:10BFD000000001000101020202020202010202004D +:10BFE0000100010101010102020202020202020239 +:10BFF0000101010101010102020202020202020228 +:10C00000010001010101010202010202020201011B +:10C010000101010101010102020202020102020109 +:10C0200001010101010101020101020201010000FF +:10C0300000010101010101020101010101020100F0 +:10C0400001010101010101020201010101000001E0 +:10C0500000010101010101010202000101010101D0 +:10C0600000000101010101010201000000000000C7 +:10C0700000000101010101000100000000000000BA +:10C0800001010101010101000100000001000001A6 +:10C090000101010101010101010000000000000097 +:10C0A0000101010101010100000101010101010182 +:10C0B000010101010101010202020202000000006F +:10C0C0000000000000010002020202000000000067 +:10C0D000000001000101020202020202010202004C +:10C0E0000100010101010102020202020202020238 +:10C0F0000101010101010102020202020202020227 +:10C10000010001010101010202010202020201011A +:10C110000101010101010102020202020202020107 +:10C1200001010101010101020201020201010000FD +:10C1300001010101010101020202010101020100EC +:10C1400001010101010101020202010101000001DE +:10C1500000010101010101010202000101010101CF +:10C1600000000101010101010201010000000000C5 +:10C1700000000101010101000100000100000001B7 +:10C1800001010101010101000100000001000101A4 +:10C190000101010101010101010000010000000194 +:10C1A0000101010101010100000101010101010181 +:10C1B000010101010101010202020202000000006E +:10C1C0000000000000010002020202000000000066 +:10C1D000000001000101020202020202010202004B +:10C1E0000200010101010102020202020202020236 +:10C1F0000101010101010102020202020202020226 +:10C200000100010101010102020102020202010119 +:10C210000101010101010102020202020202020106 +:10C2200002010101010101020201020201020000FA +:10C2300001010101010101020202010101020101EA +:10C2400001010101010101020202020101000001DC +:10C2500001010101010101010202000101010101CD +:10C2600000000101010101010201010000000000C4 +:10C2700000000101010101000100000100000001B6 +:10C2800001010101010101010100000101000101A1 +:10C290000101010101010101010000010000000193 +:10C2A0000101010101010100000100010101010181 +:10C2B000010101010101010202020202000100006C +:10C2C0000000000000010002020202000000000065 +:10C2D0000000010001010202020202020202020049 +:10C2E0000200010101010102020202020202020235 +:10C2F0000101010101010102020202020202020225 +:10C300000100010101010102020202020202010117 +:10C310000101010101010102020202020202020105 +:10C3200002010101010101020202020201020000F8 +:10C3300001010101010101020202010101020201E8 +:10C3400001010101010101020202020101000001DB +:10C3500001010101010101020202000101010101CB +:10C3600001000101010101010201010000000000C2 +:10C3700000000101010101010100000100000001B4 +:10C38000010101010101010101010001010101019E +:10C390000101010101010102010000010100000190 +:10C3A000010101010101010002010000010101017F +:10C3B0000101010101010102020202020102000069 +:10C3C0000000000000010002020202000000000064 +:10C3D0000000010001020202020202020202020047 +:10C3E0000200010101010102020202020202020234 +:10C3F0000101010101010102020202020202020224 +:10C400000100010101010102020202020202010116 +:10C410000101010101010102020202020202020203 +:10C4200002010101010101020202020201020000F7 +:10C4300001010101010101020202020101020201E6 +:10C4400002010101010101020202020101000001D9 +:10C4500001010101010101020202010101020101C8 +:10C4600001010101010101020201010000000000BF +:10C4700000000101010101010100000100000001B3 +:10C48000010101010101010101010001010101019D +:10C49000010101010101010201000001010101018D +:10C4A000010101010101010002010000010101017E +:10C4B0000101010101010102020202020202010066 +:10C4C0000001000000010002020202000001000061 +:10C4D0000000010002020202020202020202020045 +:10C4E0000200010101010102020202020202020233 +:10C4F0000101010101010202020202020202020222 +:10C500000101010101010202020202020202010113 +:10C510000101010101010102020202020202020202 +:10C5200002010101010101020202020201020001F5 +:10C5300001010101010101020202020101020201E5 +:10C5400002010101010101020202020101000001D8 +:10C5500001010101010101020202010101020101C7 +:10C5600001010101010101020201010000000000BE +:10C5700000000101010101010100000101000001B1 +:10C58000010101010101010102010101010101019A +:10C59000010101010101010201000001010101018C +:10C5A000010101010101010002010000010101017D +:10C5B0000101010101010102020202020202020064 +:10C5C000000100000001000202020201000100005F +:10C5D0000000010002020202020202020202020044 +:10C5E0000200010101010202020202020202020231 +:10C5F0000101010101010202020202020202020221 +:10C600000101010101010202020202020202020111 +:10C610000101010101010102020202020202020201 +:10C6200002010101010101020202020201020001F4 +:10C6300001010101010101020202020201020201E3 +:10C6400002010101010101020202020101000001D7 +:10C6500001010101010101020202010101020101C6 +:10C6600001010101010101020201010000000000BD +:10C6700001000101010101010101000101000101AD +:10C680000101010101010101020101010101010199 +:10C69000010101010101010201000001010101018B +:10C6A000010101010101010002010000010101017C +:10C6B0000101010101010102020202020202020063 +:10C6C000000100000002000202020201000100005D +:10C6D0000000010002020202020202020202020043 +:10C6E0000200010101010202020202020202020230 +:10C6F0000101010101010202020202020202020220 +:10C700000101010101010202020202020202020110 +:10C7100001010101020102020202020202020202FE +:10C7200002010101010101020202020201020001F3 +:10C7300001010101010101020202020201020201E2 +:10C7400002010101010101020202020101010001D5 +:10C7500001010101010101020202010101020101C5 +:10C7600001010101010101020201010000000000BC +:10C7700001000101010101010201000101000101AB +:10C780000101010101010101020101010101010198 +:10C79000010101010101010201000001010101018A +:10C7A000010101010101010002010000000101017C +:10C7B0000101010101010102020202020202020062 +:10C7C000000100000002000202020201000100005C +:10C7D0000000010002020202020202020202020042 +:10C7E000020001010101020202020202020202022F +:10C7F000010101010101020202020202020202021F +:10C80000010101020101020202020202020202010E +:10C8100001010101020102020202020202020202FD +:10C8200002010101010102020202020201020101F0 +:10C8300001010101010101020202020202020201E0 +:10C8400002010101010101020202020101010002D3 +:10C8500001010101010101020202010101020101C4 +:10C8600001010101010101020202010000000000BA +:10C8700001000101010101010201000101010101A9 +:10C880000101010101010101020101010101010197 +:10C890000101010101010102010101010101010187 +:10C8A000010101010101010002020000000001017B +:10C8B0000101010101010102020202020202020061 +:10C8C000000100000002000202020201000100005B +:10C8D0000000010002020202020202020202020041 +:10C8E000020001010101020202020202020202022E +:10C8F000020102010101020202020202020202021C +:10C90000010101020101020202020202020202010D +:10C9100001010101020102020202020202020202FC +:10C9200002010101010102020202020201020101EF +:10C9300001010101010101020202020202020201DF +:10C9400002010101010102020202020101010102D0 +:10C9500001010101010101020202010101020101C3 +:10C9600001010101010101020202010000000000B9 +:10C9700001010101010101020201000101010101A6 +:10C980000101010101010102020101010101010195 +:10C990000101010101010102010101010101010186 +:10C9A000010101010101010002020000000000017B +:10C9B000010101010101010202020202020202015F +:10C9C0000102000000020002020202020002000056 +:10C9D000000001000202020202020202020202013F +:10C9E000020001010201020202020202020202022C +:10C9F000020102010101020202020202020202021B +:10CA0000010101020101020202020202020202010C +:10CA100001010101020102020202020202020202FB +:10CA200002020101010102020202020201020101ED +:10CA300001010101010102020202020202020201DD +:10CA400002010101010102020202020101010102CF +:10CA500001010101010102020202010101020101C1 +:10CA600001010101010101020202010100000000B7 +:10CA700001010101010101020201010101010101A4 +:10CA80000101010101010102020101010101010194 +:10CA90000101010101010102020101010101010184 +:10CAA000010101010101010002020000000000017A +:10CAB000000101010101010202020202020202025E +:10CAC0000102000000020002020202020002000055 +:10CAD000000001000202020202020202020202013E +:10CAE0000201010102020202020202020202020229 +:10CAF000020102010101020202020202020202021A +:10CB0000010101020101020202020202020202020A +:10CB100001010101020102020202020202020202FA +:10CB200002020101010102020202020201020101EC +:10CB300001010101010102020202020202020201DC +:10CB400002010101010102020202020101010102CE +:10CB500001010101010102020202010101020101C0 +:10CB600001010101010101020202020100000000B5 +:10CB700001010101010101020201010101010101A3 +:10CB80000101010101010102020101010101010193 +:10CB90000101010101010102020101010101010183 +:10CBA000010101010101010002020000000000007A +:10CBB000000101010101010202020202020202025D +:10CBC0000202000000020002020202020002000053 +:10CBD000000002000202020202020202020202013C +:10CBE0000201020102020202020202020202020227 +:10CBF0000201020101010202020202020202020219 +:10CC00000101010202010202020202020202020208 +:10CC100001020101020202020202020202020202F7 +:10CC200002020101010102020202020201020101EB +:10CC300001010101010102020202020202020201DB +:10CC400002010101010102020202020101010102CD +:10CC500001010101010102020202010101020102BE +:10CC600001010101010101020202020100000001B3 +:10CC700001010101010101020201010101010101A2 +:10CC80000101010101010102020201010101010191 +:10CC90000101010101010102020101010101010182 +:10CCA0000101010101010100020202000000000077 +:10CCB000000101010101010202020202020202025C +:10CCC0000202000000020002020202020002010051 +:10CCD000000002000202020202020202020202013B +:10CCE0000201020202020202020202020202020225 +:10CCF0000201020101020202020202020202020217 +:10CD00000201020202010202020202020202020205 +:10CD100001020101020202020202020202020202F6 +:10CD200002020101020102020202020202020101E8 +:10CD300001010101010102020202020202020201DA +:10CD400002010102020102020202020201010102C9 +:10CD500001010101010102020202020101020102BC +:10CD600001010101010101020202020100000001B2 +:10CD700001010101010101020202010101010101A0 +:10CD80000101010101010102020201010101010190 +:10CD90000101010101010102020101010101010181 +:10CDA0000101010101010100020202020000000074 +:10CDB000000001010101010202020202020202025C +:10CDC0000202000000020002020202020002010050 +:10CDD0000100020002020202020202020202020139 +:10CDE0000201020202020202020202020202020224 +:10CDF0000201020101020202020202020202020216 +:10CE00000201020202010202020202020202020204 +:10CE100001020102020202020202020202020202F4 +:10CE200002020102020102020202020202020101E6 +:10CE300001010101010202020202020202020201D8 +:10CE400002010102020202020202020201010102C7 +:10CE500001010102010102020202020201020102B9 +:10CE600001010101010101020202020101000001B0 +:10CE7000010101010101010202020101010101019F +:10CE8000010101010101010202020101010101018F +:10CE90000101010101010102020101010101010180 +:10CEA0000101010101010100020202020000000073 +:10CEB000000000000101010202020202020202025D +:10CEC000020200000002000202020202000201004F +:10CED0000101020002020202020202020202020137 +:10CEE0000201020202020202020202020202020223 +:10CEF0000202020201020202020202020202020213 +:10CF00000201020202010202020202020202020203 +:10CF100002020102020202020202020202020202F2 +:10CF200002020102020202020202020202020101E4 +:10CF300001010101010202020202020202020201D7 +:10CF400002010102020202020202020202010102C5 +:10CF500001010202010102020202020201020102B7 +:10CF600001010101010101020202020101010101AD +:10CF7000010101010101010202020101010101019E +:10CF8000010101010101020202020201010101018C +:10CF9000020101010101020202010101010101017D +:10CFA0000101010101010100020202020000000072 +:10CFB000000000000001010202020202020202025D +:10CFC000020201000002000202020202000202014B +:10CFD0000101020002020202020202020202020136 +:10CFE0000201020202020202020202020202020222 +:10CFF0000202020201020202020202020202020212 +:10D000000202020202020202020202020202020200 +:10D0100002020102020202020202020202020202F1 +:10D0200002020102020202020202020202020101E3 +:10D0300001010102020202020202020202020201D4 +:10D0400002010102020202020202020202010102C4 +:10D0500001010202020202020202020202020102B3 +:10D0600001010101010101020202020101010101AC +:10D07000010101010101010202020102010101019C +:10D08000010101010101020202020201010101018B +:10D090000201020202010202020201010101010178 +:10D0A0000101010101010100020202020000000071 +:10D0B000000000000000010202020202020202025D +:10D0C0000202020100020002020202020002020148 +:10D0D0000101020002020202020202020202020135 +:10D0E0000201020202020202020202020202020221 +:10D0F0000202020202020202020202020202020210 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020101E1 +:10D1300001010202020202020202020202020201D2 +:10D1400002010102020202020202020202010102C3 +:10D1500001010202020202020202020202020202B1 +:10D1600001010101010101020202020101010101AB +:10D17000010101010101010202020202010101019A +:10D180000101010101010202020202020101010189 +:10D190000202020202020202020201010101010175 +:10D1A000010101010101010002020202020000006E +:10D1B0000200020000000102020202020202020258 +:10D1C0000202020201020002020202020002020244 +:10D1D0000201020002020202020202020202020133 +:10D1E0000201020202020202020202020202020220 +:10D1F000020202020202020202020202020202020F +:10D2000002020202020202020202020202020202FE +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020101E0 +:10D2300001010202020202020202020202020201D1 +:10D2400002010102020202020202020202010102C2 +:10D2500001010202020202020202020202020202B0 +:10D2600001010101010102020202020101010101A9 +:10D270000101010101010102020202020101010199 +:10D280000101010201010202020202020201010285 +:10D290000202020202020202020202020101010172 +:10D2A0000101010101010100020202020202000269 +:10D2B0000202020200000102020202020202020253 +:10D2C0000202020202020002020202020002020242 +:10D2D0000202020102020202020202020202020130 +:10D2E000020102020202020202020202020202021F +:10D2F000020202020202020202020202020202020E +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020101DF +:10D3300001020202020202020202020202020202CE +:10D3400002020202020202020202020202020102BE +:10D3500001020202020202020202020202020202AE +:10D3600001010101010102020202020101010101A8 +:10D370000101010101010102020202020101010198 +:10D380000101020202020202020202020201010281 +:10D390000202020202020202020202020101010171 +:10D3A0000101010101010100020202020202020266 +:10D3B0000202020200000102020201020202020253 +:10D3C000020202020202000202020202020202023F +:10D3D000020202010202020202020202020202012F +:10D3E000020102020202020202020202020202021E +:10D3F000020202020202020202020202020202020D +:10D4000002020202020202020202020202020202FC +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020101DE +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020102BD +:10D4500002020202020202020202020202020202AC +:10D4600001010101010102020202020201010101A6 +:10D470000101010101010202020202020201010195 +:10D48000010202020202020202020202020202027D +:10D490000202020202020202020202020101010170 +:10D4A0000101010101010100020202020202020265 +:10D4B0000202020200000102020201020202020252 +:10D4C000020202020202000202020202020202023E +:10D4D000020202010202020202020202020202022D +:10D4E000020102020202020202020202020202021D +:10D4F000020202020202020202020202020202020C +:10D5000002020202020202020202020202020202FB +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020202020202020202020202CB +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D5600001010101010102020202020201010101A5 +:10D570000101010101010202020202020201010293 +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020101016E +:10D5A0000101020101010100020202020202020263 +:10D5B000020202020200010202020102020202024F +:10D5C000020202020202000202020202020202023D +:10D5D000020202010202020202020202020202022C +:10D5E000020102020202020202020202020202021C +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D6600001010202020202020202020201010101A0 +:10D67000010101020101020202020202020202028F +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020201016C +:10D6A000020102020101020202020202020202025D +:10D6B000020202020202010202010102020202024D +:10D6C000020202020202000202020202020202023C +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D76000020102020202020202020202010101019E +:10D77000010102020101020202020202020202028D +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A000020202020201020202020202020202025A +:10D7B000020202020202010202010102020101024E +:10D7C000020202020202000202020202020202023B +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D86000020202020202020202020202020101019B +:10D870000201020202020202020202020202020289 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B000020202020202020202010101010101014F +:10D8C0000101010101010102020201020202020240 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202010199 +:10D970000201020202020202020202020202020288 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B000020202020202020201010101010101014F +:10D9C0000101010101010102020101020202020240 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB000020202020202020201010101010101014E +:10DAC000010101010101010202010102020202023F +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020202020202020202020216 +:10DAF0000202020202020202020202020202020206 +:10DB000002020202020202020202020202020202F5 +:10DB100002020202020202020202020202020202E5 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB000020202020202020101010101010101014E +:10DBC000010101010101010202010102020202023E +:10DBD0000202020202020202020202020202020225 +:10DBE0000202020202020202020202020202020215 +:10DBF0000202020202020202020202020202020205 +:10DC000002020202020202020202020202020202F4 +:10DC100002020202020202020202020202020202E4 +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB000020202020202020101010101010101014D +:10DCC000010101010101010202010102020202023D +:10DCD0000202020202020202020202020201010226 +:10DCE0000202020202020202020202020202020214 +:10DCF0000202020202020202020202020202020204 +:10DD000002020202020202020202020202020202F3 +:10DD100002020202020202020202020202020202E3 +:10DD200002020202020202020202020202020202D3 +:10DD300002020202020202020202020202020202C3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB000020202020202020101010101010101014C +:10DDC000010101010101010202010102020102013E +:10DDD000010101010101010202010202020202022B +:10DDE0000202020202020202020202020201020115 +:10DDF0000202020202020202020202020202020203 +:10DE000002020202020202020202020202020202F2 +:10DE100002020202020202020202020202020202E2 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA0000202020202020202020202020202020252 +:10DEB000020202020202020101010101010101014B +:10DEC000010101010101010201010102020101013F +:10DED000010101010101010202020101020101022D +:10DEE0000202020202020202020201020102010215 +:10DEF0000202020202020202020202020202020202 +:10DF000002020202020202020202020202020202F1 +:10DF100002020202020202020202020202020202E1 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB000020202020202020101010101010101014A +:10DFC000010101010101010201010101020101013F +:10DFD000010101010101010202010202010101022C +:10DFE0000102020202020202020102010201020116 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020202020202020202020250 +:10E0B0000202020202020201010101010101010149 +:10E0C0000101010101010101010101010101010140 +:10E0D000010101010101010202010101020101022C +:10E0E0000202020202020202020201020101010115 +:10E0F0000202020202020202020202020201010202 +:10E1000002020202020202020202020202020202EF +:10E1100002020202020202020202020202020202DF +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A000020202020202020202020202020202024F +:10E1B0000202020202020201010101010101010148 +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010202010101010101022C +:10E1E0000102020202020202020101010101010117 +:10E1F0000101010202020202020201010102020106 +:10E2000002020202020202020202020202020202EE +:10E2100002020202020202020202020202020202DE +:10E2200002020202020202020202020202020202CE +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E28000020202020202020202020202020202026E +:10E29000020202020202020202020202020202025E +:10E2A000020202020202020202020202020202024E +:10E2B0000202020202020201010101010101010147 +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F0000202020101010102020102020201010205 +:10E3000002020202020202020202020202020202ED +:10E3100002020202020202020202020202020202DD +:10E3200002020202020202020202020202020202CD +:10E3300002020202020202020202020202020202BD +:10E3400002020202020202020202020202020202AD +:10E35000020202020202020202020202020202029D +:10E36000020202020202020202020202020202028D +:10E37000020202020202020202020202020202027D +:10E38000020202020202020202020202020202026D +:10E39000020202020202020202020202020202025D +:10E3A000020202020202020202020202020202024D +:10E3B0000202020202020201010101010101010146 +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010202010101010101022A +:10E3E0000102020202020202020101010101010115 +:10E3F0000101010202020202020201010101010106 +:10E4000001010101020202020202020202020202F0 +:10E4100002020202020202020202020202020202DC +:10E4200002020202020202020202020202020202CC +:10E4300002020202020202020202020202020202BC +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A000020202020202020202020202020202024C +:10E4B0000202020202020201010101010101010145 +:10E4C000010101010101010101010101010101013C +:10E4D000010101010101010101010101010101012C +:10E4E000010101010101010101010101010101011C +:10E4F000010101010101010202010101010101010A +:10E5000002020202010101020202020202020202EE +:10E5100002020202020202020202020202020202DB +:10E5200002020202020202020202020202020202CB +:10E5300002020202020202020202020202020202BB +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A000020202020202020202020202020202024B +:10E5B0000202020202020201010101010101010144 +:10E5C000010101010101010101010101010101013B +:10E5D000010101010101010101010101010101012B +:10E5E000010101010101010101010101010101011B +:10E5F000010101010101010201010101010101010A +:10E6000001010101020202020202020201010202F0 +:10E6100002020202020202020202020202020202DA +:10E6200002020202020202020202020202020202CA +:10E6300002020202020202020202020202020202BA +:10E6400002020202020202020202020202020202AA +:10E65000020202020202020202020202020202029A +:10E66000020202020202020202020202020202028A +:10E67000020202020202020202020202020202027A +:10E68000020202020202020202020202020202026A +:10E69000020202020202020202020202020202025A +:10E6A000020202020202020202020202020202024A +:10E6B0000202020202020201010101010101010143 +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E000010101010101010101010101010101011A +:10E6F0000101010101010101020101010101010109 +:10E7000001010101010101020202010102020102F3 +:10E7100002020202020202020202020202020202D9 +:10E7200002020202020202020202020202020202C9 +:10E7300002020202020202020202020202020202B9 +:10E7400002020202020202020202020202020202A9 +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020201010101010101010142 +:10E7C0000101010101010101010101010101010139 +:10E7D0000101010101010101010101010101010129 +:10E7E0000101010101010101010101010101010119 +:10E7F0000101010101010102010101010101010108 +:10E8000001010101010101020202020201010201F2 +:10E8100001010202010202020202020202010102DD +:10E8200002020202020202020202020202020202C8 +:10E8300002020202020202020202020202020202B8 +:10E8400002020202020202020202020202020202A8 +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020201010101010101010141 +:10E8C0000101010101010101010101010101010138 +:10E8D0000101010101010101010101010101010128 +:10E8E0000101010101010101010101010101010118 +:10E8F0000101010101010101010101010101010108 +:10E9000001010101010101020101010101010102F5 +:10E9100002020101020101020202010101020201DF +:10E9200001020202020202020202020202020202C8 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020201010101010101010140 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010202010101010101F4 +:10EA100001010202010202020101020202010102DD +:10EA200002010202020202020202020202020202C7 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB000020202020202020101010101010101013F +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101020101010101010101F4 +:10EB100001010101010101020202010101010101E2 +:10EB200001020101010101020202020202020202CB +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB000020202020202020101010101010101013E +:10EBC0000101010101010101010101010101010135 +:10EBD0000101010101010101010101010101010125 +:10EBE0000101010101010101010101010101010115 +:10EBF0000101010101010101010101010101010105 +:10EC000001010101010101010101010101010101F4 +:10EC100001010101010101010101010101010101E4 +:10EC200001010202020202020202020202020202C6 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB000020202020202020101010101010101013D +:10ECC0000101010101010101010101010101010134 +:10ECD0000101010101010101010101010101010124 +:10ECE0000101010101010101010101010101010114 +:10ECF0000101010101010101010101010101010104 +:10ED000001010101010101010101010101010101F3 +:10ED100001010101010101020101010101010101E2 +:10ED200001010101010101020202010102010202CD +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB000020202020202020101010101010101013C +:10EDC0000101010101010101010101010101010133 +:10EDD0000101010101010101010101010101010123 +:10EDE0000101010101010101010101010101010113 +:10EDF0000101010101010101010101010101010103 +:10EE000001010101010101010101010101010101F2 +:10EE100001010101010101010101010101010101E2 +:10EE200001010101010101020201010101010202CE +:10EE300002020202020202020202020202010102B4 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB000020202020202020101010101010101013B +:10EEC0000101010101010101010101010101010132 +:10EED0000101010101010101010101010101010122 +:10EEE0000101010101010101010101010101010112 +:10EEF0000101010101010101010101010101010102 +:10EF000001010101010101010101010101010101F1 +:10EF100001010101010101010101010101010101E1 +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101020201010101010102BE +:10EF400001020202020202020201010202020201A5 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB000020202020202020101010101010101013A +:10EFC0000101010101010101010101010101010131 +:10EFD0000101010101010101010101010101010121 +:10EFE0000101010101010101010101010101010111 +:10EFF0000101010101010101010101010101010101 +:10F0000001010101010101010101010101010101F0 +:10F0100001010101010101010101010101010101E0 +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101020101010101010101BF +:10F0400001010101010101020102020101010102AC +:10F050000101010101010102020202020202020297 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020201010101010101010139 +:10F0C0000101010101010101010101010101010130 +:10F0D0000101010101010101010101010101010120 +:10F0E0000101010101010101010101010101010110 +:10F0F0000101010101010101010101010101010100 +:10F1000001010101010101010101010101010101EF +:10F1100001010101010101010101010101010101DF +:10F1200001010101010101010101010101010101CF +:10F1300001010101010101010101010101010101BF +:10F1400001010101010101010201010202020201AA +:10F15000020202020202020202020202020202028F +:10F16000020202020202020202020202020202027F +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A000020202020202020202020202020202023F +:10F1B0000202020202020201010101010101010138 +:10F1C000010101010101010101010101010101012F +:10F1D000010101010101010101010101010101011F +:10F1E000010101010101010101010101010101010F +:10F1F00001010101010101010101010101010101FF +:10F2000001010101010101010101010101010101EE +:10F2100001010101010101010101010101010101DE +:10F2200001010101010101010101010101010101CE +:10F2300001010101010101010101010101010101BE +:10F2400001010101010101020101010101010101AD +:10F250000101010101010102020102020201020297 +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202020202020202023E +:10F2B0000202020202020201010101010101010137 +:10F2C000010101010101010101010101010101012E +:10F2D000010101010101010101010101010101011E +:10F2E000010101010101010101010101010101010E +:10F2F00001010101010101010101010101010101FE +:10F3000001010101010101010101010101010101ED +:10F3100001010101010101010101010101010101DD +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010201010101010101019C +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B0000202020202020201010101010101010136 +:10F3C000010101010101010101010101010101012D +:10F3D000010101010101010101010101010101011D +:10F3E000010101010101010101010101010101010D +:10F3F00001010101010101010101010101010101FD +:10F4000001010101010101010101010101010101EC +:10F4100001010101010101010101010101010101DC +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F460000101010101010102010101020202020286 +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B0000202020202020201010101010101010135 +:10F4C000010101010101010101010101010101012C +:10F4D000010101010101010101010101010101011C +:10F4E000010101010101010101010101010101010C +:10F4F00001010101010101010101010101010101FC +:10F5000001010101010101010101010101010101EB +:10F5100001010101010101010101010101010101DB +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101010101010101010101AB +:10F55000010101010101010101010101010101019B +:10F56000010101010101010101010101010101018B +:10F570000101010101010102020202020202020272 +:10F58000020202020202020202020202020202025B +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B0000202020202020201010101010101010134 +:10F5C000010101010101010101010101010101012B +:10F5D000010101010101010101010101010101011B +:10F5E000010101010101010101010101010101010B +:10F5F00001010101010101010101010101010101FB +:10F6000001010101010101010101010101010101EA +:10F6100001010101010101010101010101010101DA +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F670000101010101010102010101010101010179 +:10F680000101010101010102010101010101010169 +:10F690000101010101010102020202020202020251 +:10F6A000020202020202020202020202020202023A +:10F6B0000202020202020201010101010101010133 +:10F6C000010101010101010101010101010101012A +:10F6D000010101010101010101010101010101011A +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101020202020202020261 +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020201010101010101010132 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010102010101010101010167 +:10F890000101010101010101010101010101010158 +:10F8A000010101010101010202020202020202023F +:10F8B0000202020202020201010101010101010131 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F99000010101010101010202020202020202024E +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020201010101010101010130 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA000010101010101010202020202020202023D +:10FAB000020202020202020101010101010101012F +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA000010101010101010202020202020202023C +:10FBB000020202020202020101010101010101012E +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA000010101010101010202020202020202023B +:10FCB000020202020202020101010101010101012D +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010102010101010101010142 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010102010101010101010141 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010102020202020202020219 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202020202020241 +:10FFA0000202020202020200000000000000000043 +:10FFB0000000000000000001010101010101010138 +:10FFC000010101010101010000000000000000002A +:10FFD000000000000000000202020202020202020F +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:02000002B0004C +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020200000000000000000042 +:1000B0000000000000000001010101010101010137 +:1000C0000101010101010100000000000000000029 +:1000D0000000000000000000000000000000000020 +:1000E00000000000000000020202020202020202FE +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A0000202020202020200000000000000000041 +:1001B000000000000000000000000000000000003F +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B00000000000000000540000000000000000EA +:1002C000000000000000000000000000000000002E +:1002D000000100000000000000000000000000001D +:1002E000000000000001010001000000000000000B +:1002F00000010000000000000000000000000000FD +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000100010000000000000000000000001B +:1003E0000000010000010100010000000000000009 +:1003F00000010100000000000000000000000000FB +:1004000000000100000000000000000000000000EB +:1004100000000100000000000000000000000000DB +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000010000000200000000000000000000A9 +:100450000000000000010000000100000000000199 +:100460000100000000000100000000000000000189 +:10047000000000000000000000000000000000017B +:10048000000000000000000000000000000000016B +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000001013A +:1004C0000000020202000000000002010101000120 +:1004D0000001000101010101010101000101000011 +:1004E0000000010000010100010101000101000103 +:1004F00000010100010000010101010001010000F3 +:1005000000000100000000000000000000020000E8 +:1005100000000100000000000101000000020000D6 +:1005200000000000000000000000000100000100C9 +:1005300000010000000002000200010001000000B4 +:1005400000010000000200000200000200000000A4 +:100550000000000000010000000100020000000196 +:100560000100000000000100000000000000010187 +:100570000000000000000000000000020000000178 +:100580000000000000000000000000020000010167 +:100590000000000000000000000000020000000059 +:1005A000000000000000000000000000000001004A +:1005B0000000000000000000000000000000010139 +:1005C000000002020200000000000202010100011E +:1005D000000101010101010101010101010101000D +:1005E0000000010000010100010101010101010100 +:1005F00000010100010000010101010101010100F0 +:1006000000000100000000000000000000010100E7 +:1006100000000101000000000101000200010000D3 +:1006200000000000010001000002010102020100BF +:1006300000010000000002000100010101000100B2 +:10064000000100000002000002010202020200009C +:10065000000000000001020101010002020200018D +:100660000101000001000100000000000201010181 +:100670000000000001000000000000020202000172 +:100680000000000000000000000000020202010162 +:100690000000000000000000020002020202000050 +:1006A000000000000000000002020200020201003F +:1006B0000000000000000000000000000000010138 +:1006C0000101020202000000020202020201000116 +:1006D000010101010101010101010101010101010A +:1006E00000000100010101020101010101010101FC +:1006F00000010100010101010101010101010101EC +:1007000000000100000101010002010001010100DF +:1007100000000101010001000101000100010000D1 +:1007200000000000010001000001010102010100C0 +:1007300000010000000001020101010101010100AE +:10074000000100000001000002010102020101009D +:10075000000001000001020101010002020201018A +:10076000010100000100010000000002020101017E +:100770000000000001000000000000020201010171 +:100780000000000000000000000000020201010162 +:10079000000000000000000002000202020200004F +:1007A000000000000000000001020202020101003E +:1007B0000000000000000000000000000000010137 +:1007C0000102020202000000020202020201000114 +:1007D0000101010101010101010101010101010109 +:1007E00000000100010101020101010101010101FB +:1007F00001010101010101010101010101010101E9 +:1008000000000101000101010002010201010100DB +:1008100000000101010001000101000100010100CF +:1008200000010000010101000001010101010100BE +:1008300000010100000001020101010101010100AC +:10084000000100000001020001010101020101009C +:10085000000001000001010101010201020101018A +:10086000010100000100010000000202020101017B +:10087000000000000100000000000201020101016F +:100880000000000000000000000002010201010160 +:100890000000000000000000020002010201000050 +:1008A000000000000000000201020102020101003C +:1008B0000000000000000000000000000000010136 +:1008C0000202020202000000020202020201000112 +:1008D0000101010101010101010101010101010108 +:1008E00001010100010101020101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000000010101010101010002010201010100D8 +:1009100000000101010001020101000100010100CC +:1009200000010000010101000001010101010100BD +:1009300001010100000001010101010101010100AB +:10094000000100000001020001010101010101009C +:10095000000001000001010101010201010101018A +:10096000010100010100010000000202010101017A +:10097000000000000100000000000201010101016F +:100980000000000000000000000002010101010160 +:100990000000000000000000010001010101010051 +:1009A000000000000000000201010101010101003E +:1009B0000000000000000000000000000000010135 +:1009C0000202020202000000020202020201000111 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000000010101010101010001010201010100D8 +:100A100000000101010001020101000100010100CB +:100A200000010000010101020101010101010100B9 +:100A300001010101000001010101010101010100A9 +:100A4000000100000001020001010101010101009B +:100A50000000010000010101010102010101010189 +:100A60000101000101010100000002010101010179 +:100A7000000000000100000000000201010101016E +:100A8000000000000000000000000201010101015F +:100A9000000000000000000001020101010101004E +:100AA000000000000000000201010101010101003D +:100AB0000000000000000000000000000000010134 +:100AC0000202020202000000020202020201000110 +:100AD0000101010101020101010101010101010105 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000000010101010101010101010101010101D6 +:100B100000010101010001010101020100010100C8 +:100B200000010001010101010101010101010101B7 +:100B300001010101000101010101010101010100A7 +:100B4000000101000001010001010101010101009A +:100B50000000010000010101010101010101010189 +:100B60000101000101010100000001010101010179 +:100B7000000000000100000000000101010101016E +:100B8000000000000000000000000101010101015F +:100B9000000000000000000001020101010101004D +:100BA000000000000000000101010101010101003D +:100BB0000000000000000000000000000000010232 +:100BC000020202020200000002020202020100010F +:100BD0000101010101020202010101010101010102 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000000010101010101010101010101010101D5 +:100C100000010101010001010101020100010100C7 +:100C200000010001010101010101010101010101B6 +:100C300001010101000101010101010101010100A6 +:100C40000101010001010101010101010101010096 +:100C50000000010000010101010101010101010188 +:100C60000101000101010100020001010101010176 +:100C7000000000000100000002000101010101016B +:100C8000000000000000000002020101010101015A +:100C9000000000000000000001020101010101004C +:100CA0000100000000020001010101010101010039 +:100CB0000000000000000000000000000000010231 +:100CC000020202020200000002020202020100010E +:100CD00001020101020202020101010101010101FF +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000000010101010101010101010101010101D4 +:100D100000010101010101010101020100010100C5 +:100D200000010001010101010101010101010101B5 +:100D300001010101000101010101010101010100A5 +:100D40000101010001010101010101010101010095 +:100D50000000010000010101010101010101010187 +:100D60000101000101010100020001010101010175 +:100D7000000000000100000002000101010101016A +:100D80000000000000000000020201010101010159 +:100D9000000000000000000001010101010101004C +:100DA0000100000000020001010101010101010038 +:100DB0000000000000000000000000000000010230 +:100DC000020202020200000002020202020100010D +:100DD00001020202020202020101010101010101FC +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000000010101010101010101010101010101D3 +:100E100001010101010101010101010100010101C3 +:100E200001010001010101010101010101010101B3 +:100E300001010101000101010101010101010100A4 +:100E40000101010001010101010101010101010094 +:100E50000000010000010101010101010101010186 +:100E60000101000101010100020201010101010172 +:100E70000000000001000000020001010101010169 +:100E80000000000000000000020201010101010158 +:100E9000000000000000000001010101010101004B +:100EA0000101000000020201010101010101010034 +:100EB000000000000000000000000000000001022F +:100EC0000202020202020000020202020202000109 +:100ED00002020202020202020201010101010101F9 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101010101010101010101E2 +:100F000000010101010101010101010101010101D2 +:100F100001010101010101010101010100010101C2 +:100F200001010001010101010101010101010101B2 +:100F300001010101010101010101010101010100A2 +:100F40000101010101010101010101010101010092 +:100F50000000010000010101010101010101010185 +:100F60000101010101010100010201010101010171 +:100F70000000000001000000010001010101010169 +:100F80000000000000000000010101010101010159 +:100F9000000000000000000001010101010101004A +:100FA0000101000000010201010101010101010034 +:100FB000000000000000000000000000000001022E +:100FC0000202020202020000020202020202000207 +:100FD00002020202020202020202010101010101F7 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101010101010101010101E1 +:1010000000010101010101010101010101010101D1 +:1010100001010101010101010101010100010101C1 +:1010200001010001010101010101010101010101B1 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010091 +:101050000100010000010101010101010101010183 +:10106000010101010101010201020101010101016E +:101070000000000001000000010201010101010166 +:101080000000000000000002010101010101010156 +:101090000000000000000002010101010101010047 +:1010A0000101000000010201010101010101010033 +:1010B000000000000000000000000000000001022D +:1010C0000202020202020002020202020202000204 +:1010D00002020202020202020202010101010102F5 +:1010E00001010201010101010101010101010102EE +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010100010101C0 +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:101140000101010101010101010101010101010090 +:101150000100010000010101010101010101010182 +:10116000010101010101010201010101010101016E +:101170000000000001000000010201010101010165 +:101180000000000000000002010101010101010155 +:101190000000000000000002010101010101010046 +:1011A0000101000000010101010101010101010033 +:1011B000000000000000000000000000000001022C +:1011C0000202020202020002020202020202000203 +:1011D00002020202020202020202010101010102F4 +:1011E00002010201010201010101010101010102EB +:1011F00002020201010101010101010101010102DB +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010100010101BF +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:101250000100010000010101010101010101010181 +:10126000010101010101010201010101010101016D +:101270000000000001000000010201010101010164 +:101280000100000000000002010101010101010153 +:101290000000000000000002010101010101010045 +:1012A0000101000000010101010101010101010032 +:1012B000000000000000000000000000000001022B +:1012C0000202020202020202020202020202000200 +:1012D00002020202020202020202010101010102F3 +:1012E00002010201010202010101010101010102E9 +:1012F00002020201010101010101010101010102DA +:1013000001010201010101010101010101010101CC +:1013100001010101010101010101010100010101BE +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:101350000100010000010101010101010101010180 +:10136000010101010101010101010101010101016D +:101370000000000001000000010101010101010164 +:101380000100000000000001010101010101010153 +:101390000000000000000001010101010101010045 +:1013A0000101000100010101010101010101010030 +:1013B000000000000000000000000000000001022A +:1013C00002020202020202020202020202020002FF +:1013D00002020202020202020202020101010102F1 +:1013E00002020201020202010101010101010102E6 +:1013F00002020201010101010101010101010102D9 +:1014000001010201010101010101010101010101CB +:1014100001010101010101010101010100010101BD +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010001000001010101010101010101017F +:10146000010101010101010101010101010101016C +:101470000000000001000000010101010101010163 +:101480000100000000000201010101010101010150 +:101490000000000000000201010101010101010042 +:1014A000010100010001010101010101010101002F +:1014B0000000000000000000000000000000010229 +:1014C00002020202020202020202020202020002FE +:1014D00002020202020202020202020101010102F0 +:1014E00002020201020202010101010101010102E5 +:1014F00002020201020101010101010101010102D7 +:1015000001010201010101010101010101010101CA +:1015100001010201010101010101010100010101BB +:1015200001010101010101010101010101010101AB +:10153000020101010101010101010101010101019A +:10154000010101010101010101010101010101018B +:10155000010001000001010101010101010101017E +:10156000010101010101010101010101010101016B +:101570000000000001000000010101010101010162 +:10158000010000000000020101010101010101014F +:101590000000000000000201010101010101010041 +:1015A000010101010001010101010101010101002D +:1015B0000000000000000000000000000000010228 +:1015C00002020202020202020202020202020002FD +:1015D00002020202020202020202020201010102EE +:1015E00002020202020202010202010101010102E1 +:1015F00002020202020201010101010101010102D4 +:1016000001020201010101010101010101010102C7 +:1016100001010201010101010101010100010101BA +:1016200001010101010101010101010101010102A9 +:101630000202010101010101010101010101010198 +:10164000010101010101010101010101010101018A +:10165000010101000001010101010101010101027B +:101660000201010101010101010101010101010268 +:10167000000000000100000201010101010101025E +:10168000010000000002020101010101010101014C +:10169000010000000000020101010101010101003F +:1016A000010101010001010101010101010101002C +:1016B0000000000000000000000000000000000228 +:1016C00002020202020202020202020202020002FC +:1016D00002020202020202020202020201010102ED +:1016E00002020202020202010202010101010102E0 +:1016F00002020202020201020101010101010102D2 +:1017000001020202010101010101010101010102C5 +:1017100002010201010101010101010102010101B6 +:1017200001010101010101010101010101010102A8 +:101730000202010101010101010101010101010197 +:101740000102010101010101010101010101010188 +:10175000010101000001010101010101010101027A +:101760000201010101010101010101010101010267 +:10177000000000000100000201010101010101025D +:10178000010000000002010101010101010101024B +:10179000010000000000010101010101010101003F +:1017A000010101010001010101010101010101002B +:1017B0000000000000000000000000000000000227 +:1017C00002020202020202020202020202020002FB +:1017D00002020202020202020202020202010102EB +:1017E00002020202020202010202010101010102DF +:1017F00002020202020202020101010101010102D0 +:1018000002020202010201010101010101010102C2 +:1018100002010202010101010101010101010102B4 +:1018200002020101010101010101010101010102A5 +:101830000202020101010101010101010101010195 +:101840000202010101010101010101010101010186 +:101850000101010000010101010101010101010279 +:101860000201010101010101010101010101010266 +:10187000000000000100000201010101010101025C +:10188000010000000002010101010101010101024A +:10189000010000000002010101010101010101013B +:1018A000010101010001010101010101010101002A +:1018B0000000000000000000000000000000000226 +:1018C00002020202020202020202020202020002FA +:1018D00002020202020202020202020202010102EA +:1018E00002020202020202010202010101010102DE +:1018F00002020202020202020102010101010102CE +:1019000002020202020202010101010101010102BF +:1019100002020202010101010101010101010102B2 +:1019200002020101010101010101010101010102A4 +:101930000202020101010101010101010101010194 +:101940000202010101010101010101010101010185 +:101950000101010000010101010101010101010278 +:101960000201010101010101010101010101010265 +:10197000000000000100000101010101010101025C +:10198000010000000001010101010101010101024A +:10199000010000000002010101010101010101013A +:1019A0000101010100010101010101010101010029 +:1019B0000000000000000000000000000000000225 +:1019C00002020202020202020202020202020002F9 +:1019D00002020202020202020202020202010102E9 +:1019E00002020202020202010202020101010102DC +:1019F00002020202020202020202010101010102CC +:101A000002020202020202020101010101010102BD +:101A100002020202020101010101010101010102B0 +:101A200002020101020101010101010101010102A2 +:101A30000202020101010101010101010101010292 +:101A40000202010101010101010101010101010184 +:101A50000101020000010101010101010101010276 +:101A60000201010101010101010101010101010264 +:101A7000000000000100000101010101010101025B +:101A80000101000000010101010101010101010248 +:101A90000101000000020101010101010101010138 +:101AA0000101010101010101010101010101010027 +:101AB0000000000000000000000000000000000224 +:101AC00002020202020202020202020202020002F8 +:101AD00002020202020202020202020202010102E8 +:101AE00002020202020202010202020201010102DA +:101AF00002020202020202020202020101010102CA +:101B000002020202020202020101010101010102BC +:101B100002020202020101010101010101010102AF +:101B200002020101020101010101010101010102A1 +:101B30000202020201010101010101010101010290 +:101B40000202020101010101010101010101010182 +:101B50000201020000010101010101010101010274 +:101B60000202010101010101010101010101010262 +:101B7000000000000100000101010101010101025A +:101B80000101000000010101010101010101010247 +:101B90000101000000010101010101010101010138 +:101BA0000101010101010101010101010101010026 +:101BB0000000000000000000000000000000000223 +:101BC00002020202020202020202010202020002F8 +:101BD00002020202020202020202020202010102E7 +:101BE00002020202020202020202020202010102D7 +:101BF00002020202020202020202020101010102C9 +:101C000002020202020202020101010101010102BB +:101C100002020202020102010101010101010102AD +:101C2000020201020202020101010101010101029D +:101C3000020202020101010101010101010101028F +:101C40000202020101010101010101010101010280 +:101C50000201020000010101010101010101010273 +:101C60000202010101010101010101010101010261 +:101C70000001000001000001010101010101010258 +:101C80000101000000010101010101010101010246 +:101C90000101000000010101010101010101010137 +:101CA0000201010101010101010101010101010024 +:101CB0000000000000000000000000000000000222 +:101CC00002020202010202020202010202020002F8 +:101CD00002020202020202020202020202020102E5 +:101CE00002020202020202020202020202010102D6 +:101CF00002020202020202020202020202010102C6 +:101D000002020202020202020101020101010102B9 +:101D100002020202020102010202010101010102AA +:101D2000020202020202020101010101010101029B +:101D3000020202020101010101010101010101028E +:101D4000020202010101010101010101010101027F +:101D50000201020100020101010101010101010270 +:101D60000202010101010101010101010101010260 +:101D70000001010001000001010101010101010256 +:101D80000101000100010101010101010101010244 +:101D90000101000000010101010101010101010136 +:101DA0000201010101010101010101010101010023 +:101DB0000000000000000000000000000000000221 +:101DC00002020201010202020101010202020002FA +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020102D4 +:101DF00002020202020202020202020202010102C5 +:101E000002020202020202020201020101010102B7 +:101E100002020202020202010202010101010102A8 +:101E2000020202020202020101010101010101029A +:101E3000020202020102020101010101010101028B +:101E4000020202010101010101010101010101027E +:101E5000020102010102010101010101010101026E +:101E6000020201010101010101010101010101025F +:101E70000101010001000001010101010101010254 +:101E80000201000101010101010101010101010241 +:101E90000101000000010101010101010101010135 +:101EA0000201010101010101010101010101010022 +:101EB0000000000000000000000000000000000220 +:101EC00002020201010202020101010202020002F9 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020102D3 +:101EF00002020202020202020202020202020102C3 +:101F000002020202020202020201020102010102B5 +:101F100002020202020202010202010101010102A7 +:101F20000202020202020201010101010101010299 +:101F30000202020202020201020202010101010286 +:101F4000020202020202010101010101010101027A +:101F5000020102010102010101010101010101026D +:101F6000020201020201010101010101010101025C +:101F70000101010002000001010101010101010252 +:101F8000020101010101010101010101010101023F +:101F90000101010000010101010101010101010133 +:101FA0000201010101010101010101010101010021 +:101FB000000000000000000000000000000100021E +:101FC00002020201010202010101010101020002FB +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020102C2 +:1020000002020202020202020202020102010102B3 +:1020100002020202020202010202010101010102A6 +:102020000202020202020201010202020101010295 +:102030000202020202020202020202020201010282 +:102040000202020202020101010201010101010278 +:10205000020102010102010201020101010101026A +:102060000202020202010201010101010101010259 +:102070000101010002010001010101010101010250 +:10208000020101010101010101010101010101023E +:102090000101010001010101010101010101010131 +:1020A0000201010101010101010101010101010020 +:1020B000000002000000000000000000000100021B +:1020C00002020201020102010101010101020002FA +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020202D0 +:1020F00002020202020202020202020202020202C0 +:1021000002020202020202020202020102020202B0 +:1021100002020202020202020202010201010102A3 +:102120000202020202020202020202020101010292 +:102130000202020202020202020202020201010281 +:102140000202020202020101010201010101010277 +:102150000201020101020202020201010101010267 +:102160000202020202010201010101010101010258 +:10217000010101010201000101010101010101024E +:10218000020101010101010101010101010101023D +:10219000020101010101010101010101010101012E +:1021A000020201010101010101010101010101001E +:1021B0000002020000000000010001000001000216 +:1021C00002020202020101010101010101020002F9 +:1021D00002020202020202020202020202020202DF +:1021E00002020202020202020202020202020202CF +:1021F00002020202020202020202020202020202BF +:1022000002020202020202020202020102020202AF +:1022100002020202020202020202010201010102A2 +:102220000202020202020202020202020101010291 +:102230000202020202020202020202020201010280 +:102240000202020202020202010202010101010273 +:102250000202020101020202020201010101010265 +:102260000202020202020201010101010101010256 +:10227000010101010201010101010101010101024C +:10228000020101010101010101010101010101023C +:10229000020101010101010101010101010101022C +:1022A000020201010101010101010101010101001D +:1022B0000002020000000001010101010101000211 +:1022C00002020202020101010101010101020002F8 +:1022D00002020202020202020202020202020202DE +:1022E00002020202020202020202020202020202CE +:1022F00002020202020202020202020202020202BE +:1023000002020202020202020202020202020202AD +:1023100002020202020202020202010201020102A0 +:10232000020202020202020202020202010102028F +:10233000020202020202020202020202020202027D +:102340000202020202020202020202010101010271 +:102350000202020101020202020201010101010264 +:102360000202020202020201010101010101010255 +:10237000010101010201010101010101010101024B +:10238000020101010101010101010101010101023B +:10239000020101010101010101010101010101022B +:1023A000020201010101010101010101010101001C +:1023B000000102000101000101010101010100020F +:1023C00002020102020101020101010101020002F7 +:1023D00002020202020202020202020202020202DD +:1023E00002020202020202020202020202020202CD +:1023F00002020202020202020202020202020202BD +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020102010202029E +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:102440000202020202020202020202010101010270 +:102450000202020101020202020201010101010263 +:102460000202020202020201010101010101010254 +:102470000201010102010101010101010101010249 +:10248000020101010101010101010101010101023A +:10249000020101010101010101010101010101022A +:1024A000020201010101010101010101010101001B +:1024B000000102020101010101010101010100020B +:1024C00002020102010201020101010101020002F6 +:1024D00002020202020202020202020202020202DC +:1024E00002020202020202020202020202020202CC +:1024F00002020202020202020202020202020202BC +:1025000002020202020202020202020202020202AB +:10251000020202020202020202020102010202029D +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202010202026C +:102550000202020101020202020201010101010262 +:102560000202020202020201010101010101010253 +:102570000201010102010101010101010101010248 +:102580000201010101010101010101010101010239 +:102590000201010101010101010101010101010229 +:1025A0000202020101010101010101010101010019 +:1025B000000102010101010101010101010100020B +:1025C00002020101010202020101010101020002F5 +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020202CB +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020202010202029B +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202010102020202020102010102025F +:102660000202020202020201010101010101010252 +:102670000201010102010101010101010101010247 +:102680000202010101010101010101010101010237 +:102690000201010101010101010101010101010228 +:1026A0000202020201010101020101010101010016 +:1026B000000002010001010101010101010100020C +:1026C00002020101010202020101010101010002F5 +:1026D00002020202020202010202020202020202DB +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:10271000020202020202020202020202010202029A +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:10275000020202010102020202020202020202025B +:10276000020202020202020101010101010202024F +:102770000202010102010101010101010101010245 +:102780000202010101010101010101010101020235 +:102790000202010101010101010101010101010226 +:1027A0000202020201010101020101010101010015 +:1027B000000001010000010101010101010100020D +:1027C00002020201010202010101010101010002F4 +:1027D00002020202020101010202020202020202DC +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020102020299 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020201020202020202020202020259 +:10286000020202020202020101010101010202024E +:102870000202020102010101010101020102020240 +:102880000202010101010101010101020102020232 +:102890000202010101010101020101010101010224 +:1028A000020202020102010202020201010102000F +:1028B000000001000000010101010101010100020D +:1028C00002020201010102010101010101010002F4 +:1028D00002020202020101010102020202020202DC +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020102020298 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020201020202020202020202020258 +:10296000020202020202020101010202020202024A +:10297000020202010201010101010202020202023D +:10298000020202010101010101010202020202022E +:102990000202010101010101020102020101010221 +:1029A000020202020102010202020202010202000C +:1029B000000001000000000001010101010100020E +:1029C00002010201010101010101010101010002F5 +:1029D00002020202020101010101020202020202DC +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020102020297 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020201020102020202020248 +:102A7000020202010201010102010202020202023B +:102A8000020202020101010102020202020202022A +:102A9000020202010101010102020202020202021B +:102AA0000202020201020202020202020202020009 +:102AB000000001000000000000000101010100020F +:102AC00002010201010101010101010101010002F4 +:102AD00002020202010101010101020202020202DC +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B7000020202010201010102010202020202023A +:102B80000202020201010102020202020202020228 +:102B9000020202010101010102020202020202021A +:102BA0000202020202020202020202020202020007 +:102BB000000001000000000000000001010100020F +:102BC00002010101010101010101010101010002F4 +:102BD00002020202010101010101020202020202DB +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202010101020202020202020237 +:102C80000202020202020202020202020202020224 +:102C90000202020101010102020202020202020218 +:102CA0000202020202020202020202020202020006 +:102CB0000000010000000000000000000001000210 +:102CC00002010101010101010101010101010002F3 +:102CD00002020202010101010101010202020202DB +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202010101020202020202020236 +:102D80000202020202020202020202020202020223 +:102D90000202020201010202020202020202020215 +:102DA0000202020202020202020202020202020005 +:102DB0000000010000000000000000000000000210 +:102DC00002010101010101010101010101010002F2 +:102DD00002020201010101010101010102020202DC +:102DE00002020202020202020202020202020202C3 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020102020202020202020233 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020004 +:102EB0000000000000000000000000000000000210 +:102EC00001010101010101010101010101010002F2 +:102ED00002020101010101010101010102020202DC +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020102020202020202020232 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020003 +:102FB000000000000000000000000000000000020F +:102FC00001010101010101010101010101010002F1 +:102FD00002010101010101010101010101020202DD +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020002 +:1030B000000000000000000000000000000000020E +:1030C00001010101010101010101010101010002F0 +:1030D00002010101010101010101010101020202DC +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A0000202020202020202020202020202020001 +:1031B000000000000000000000000000000000020D +:1031C00001010101010101010101010101010002EF +:1031D00002010101010101010101010101020202DB +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B000000000000000000000000000000000020C +:1032C00001010101010101010101010101010002EE +:1032D00002010101010101010101010101020202DA +:1032E00002020202020101020201020202020202C1 +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B000000000000000000000000000000000010C +:1033C00001010101010101010101010101010002ED +:1033D00001010101010101010101010101010102DC +:1033E00002020202010202020102020202020202BF +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B0000200000000000000000000000000000109 +:1034C00001010101010101010101000101010102EC +:1034D00001010101010101010101010101010102DB +:1034E00002020202020101020201020202020202BF +:1034F00002020202020102010202020202020202AE +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B0000200000000000000000000000000000108 +:1035C00001010101010101010000000101010102ED +:1035D00001010101010101010101010101010102DA +:1035E00002020101010101010101010102020202C5 +:1035F00002020202010201020201020202020202AE +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B0000200000000000000000000000000000107 +:1036C00001010101010101010000000101010101ED +:1036D00001010101010101010101010101010102D9 +:1036E00002010202010101020101020201020202C1 +:1036F00002020101020102010102010202020202B0 +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B0000200000000000000000000000000000106 +:1037C00001010101010101010000000101010101EC +:1037D00001010101010101010101010101010102D8 +:1037E00002020101010101010101010102010202C4 +:1037F00002010202010101010201020101020202B1 +:10380000020202020201010102020202020202029B +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B0000200000000000000000000000000000105 +:1038C00001010101010101010000000101010101EB +:1038D00001010101010101010101010101010102D7 +:1038E00001010101010101010101010101020102C6 +:1038F00001020101010101010101010202010202B3 +:10390000020201010102020201020102020202029C +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B0000200000000000000000000000000000104 +:1039C00001010100000101010000000100010101ED +:1039D00001010101010101010101010101010101D7 +:1039E00002010101010101010101010101010202C4 +:1039F00002010101010101010101010101020102B4 +:103A0000020102020200000002010202010202029F +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB0000200000000000000000000000000000103 +:103AC00001010100000101000000000101010101EC +:103AD00001010101010101010101010101010102D5 +:103AE00001010101010101010101010101010101C6 +:103AF00000010101010101010101010101010202B5 +:103B000002020000000000000002000102010102A8 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB0000202000000000000000000000000000100 +:103BC00001010100000000000000010101010101EC +:103BD00001010101010101010101010101010101D5 +:103BE00001010101010101010101010101010102C4 +:103BF00001010101010101010101010101010101B5 +:103C000001000000000101010000000200020202A8 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020000000000000000000000000001FF +:103CC00001010100000000000101010101010101E9 +:103CD00001010101010101010101010101010101D4 +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010102B3 +:103D000002000101010101010100010000000002A7 +:103D1000020201010101010201010202020202028A +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020200000000000000000000000001FC +:103DC00001010100000000000101010101000101E9 +:103DD00001010101010101010101010101010101D3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101010101010101010100B4 +:103E000000010101010101010101010001000002A5 +:103E10000101020202020201020202010202020286 +:103E20000202020201010102020202020202020275 +:103E3000020101010101010101010101010202026E +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020200000000000000000000000001FB +:103EC00001000100000000000101010101010101E8 +:103ED00001010101010101010101010101010101D2 +:103EE00001010101010101010101010101010101C2 +:103EF00001010101010101010101010101010100B3 +:103F000000010101010101010101010101010102A1 +:103F10000202000000000002000001020101010293 +:103F20000201010102020201010101010202020279 +:103F30000101010101010101010101010101010270 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202000000000000000000000001F8 +:103FC00001010100000000000101010101010101E6 +:103FD00001010101010101010101010101010101D1 +:103FE00001010101010101010101010101010101C1 +:103FF00001010101010101010101010101010101B1 +:1040000001010101010101010101010101010101A0 +:10401000000001010101010001010200020202028F +:10402000010202020000000202020202010101017B +:104030000102020202020202020202020201010263 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202000000000000000000000001F7 +:1040C00001010100010000000101010101010101E4 +:1040D00001010101010101010101010101010101D0 +:1040E00001010101010101010101010101010101C0 +:1040F00001010101010101010101010101010101B0 +:10410000010101010101010101010101010101029E +:104110000001010101010101010100010000000194 +:104120000200000000000000000000000202020186 +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020000000000000000000201F2 +:1041C00000010101010000010101010101010101E2 +:1041D00001010101010101010101010101010101CF +:1041E00001010101010101010101010101010101BF +:1041F00001010101010101010101010101010101AF +:10420000010101010101010101010101010101009F +:10421000010101010101010101010101010101028D +:104220000000000001010100000000000000000289 +:104230000200000000000000000000000002020276 +:104240000201010101010101010101020202020258 +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020200000000000000000201EF +:1042C00001010101010101010101010101010101DE +:1042D00001010101010101010101010101010101CE +:1042E00001010101010101010101010101010101BE +:1042F00001010101010101010101010101010101AE +:10430000010101010101010101010101010101019D +:10431000010101010101010101010101010101008E +:104320000001010101010101010101010000000280 +:10433000000000000000000000000000000000027B +:10434000010101010101010101010101010101025C +:10435000020202020202020202020202020202023D +:10436000020202020202020202020202020202022D +:10437000020202020202020202020202020202021D +:10438000020202020202020202020202020202020D +:1043900002020202020202020202020202020202FD +:1043A00002020202020202020202020202020202ED +:1043B00002020202020202020200000000000200E9 +:1043C00001010101010101010101010101010101DD +:1043D00001010101010101010101010101010101CD +:1043E00001010101010101010101010101010101BD +:1043F00001010101010101010101010101010101AD +:10440000010101010101010101010101010101019C +:10441000010101010101010101010101010101008D +:10442000010101010101010101010101010101007D +:10443000000000000000000000000000000000017B +:104440000102020202020202020202010101010251 +:10445000020202020202020202020202020202023C +:10446000020202020202020202020202020202022C +:10447000020202020202020202020202020202021C +:10448000020202020202020202020202020202020C +:1044900002020202020202020202020202020202FC +:1044A00002020202020202020202020202020202EC +:1044B00002020202020202020202020000020201E1 +:1044C00001010101010101010101010101010101DC +:1044D00001010101010101010101010101010101CC +:1044E00001010101010101010101010101010101BC +:1044F00001010101010101010101010101010101AC +:10450000010101010101010101010101010101019B +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101007C +:10453000000101010101010101010101010000016E +:10454000020202020202020202020202020202024B +:104550000202010202010101010102020202020241 +:10456000020202020202020202020202020202022B +:10457000020202020202020202020202020202021B +:10458000020202020202020202020202020202020B +:1045900002020202020202020202020202020202FB +:1045A00002020202020202020202020202020202EB +:1045B00002020202020202020202020200020201DE +:1045C00001010101010101010101010101010101DB +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101007B +:104630000101010101010101010101010101010269 +:104640000201010101010101000101020202020255 +:104650000101020101020202020201010101010243 +:10466000020202020202020202020202020202022A +:10467000020202020202020202020202020202021A +:10468000020202020202020202020202020202020A +:1046900002020202020202020202020202020202FA +:1046A00002020202020202020202020202020202EA +:1046B00002020202020202020202020202020201DB +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010268 +:104740000101010101010101010101010101010159 +:10475000020201020201010101010202020202023F +:10476000000202020202020202020202020202022B +:104770000202020202020202020202020202020219 +:104780000202020202020202020202020202020209 +:1047900002020202020202020202020202020202F9 +:1047A00002020202020202020202020202020202E9 +:1047B00002020202020202020202020202020201DA +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010257 +:104850000101010101010101010101010101010247 +:104860000001010101010102020202020202020230 +:104870000202020202020202020202020202020218 +:104880000202020202020202020202020202020208 +:1048900002020202020202020202020202020202F8 +:1048A00002020202020202020202020202020202E8 +:1048B00002020202020202020202020202020201D9 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010236 +:10497000010202020102020202020202020202011A +:104980000101010101010101010101010101010216 +:1049900002020202020202020202020202020202F7 +:1049A00002020202020202020202020202020202E7 +:1049B00002020202020202020202020202020201D8 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000201010101010101010101010101010224 +:104A80000202020202020202020202020202020206 +:104A900002020202020202020202020202020202F6 +:104AA00002020202020202020202020202020202E6 +:104AB00002020202020202020202020202020201D7 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010026 +:104B80000000000000000000000000000000000124 +:104B90000101010101010101010101010101010204 +:104BA00002020202020202020202020202020202E5 +:104BB00002020202020202020202020202020201D6 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010213 +:104C900002020202020202020202020202020202F4 +:104CA00001010101010101010101010101010102F3 +:104CB00002020202020202020202020202020201D5 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00002020202020202020202020202020202E3 +:104DB00002020202020202020202020202020201D4 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010201 +:104EA00001010101010101010101010101010102F1 +:104EB00002020202020202020202020202020201D3 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010102F0 +:104FB00002020202020202020202020202020201D2 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010102EF +:1050B00002020202020202020202020202020201D1 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010102EE +:1051B00002020202020202020202020202020201D0 +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010102ED +:1052B00002020202020202020202020202020201CF +:1052C00001010101010101010101010101010102CD +:1052D00002020202020202020202020202020202AE +:1052E000020202020202020202020202020202029E +:1052F000020202020202020202020202020202028E +:10530000020202020202020202020202020202027D +:10531000020202020202020202020202020202026D +:10532000020202020202020202020202020202025D +:10533000020202020202020202020202020202024D +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202020202020202020202020202ED +:1053A00002020202020202020202020202020200DF +:1053B00000000000000000000000000000000001EC +:1053C00001010101010101010101010101010102CC +:1053D00002020202020202020202020202020202AD +:1053E000020202020202020202020202020202029D +:1053F000020202020202020202020202020202028D +:10540000020202020202020202020202020202027C +:10541000020202020202020202020202020202026C +:10542000020202020202020202020202020202025C +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202020202020202020202EC +:1054A00002020202020202020202020202020200DE +:1054B00000000000000000000000000000000001EB +:1054C00001010101010101010101010101010100CD +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000002BA +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020202020202020202020202020200DD +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B0000000000000000000000000000000003EAC +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000001C9 +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000000000001000000000000000000000098 +:105710000000000000000000000000000000000089 +:105720000000000000000100000000000000000078 +:105730000000000000000000000000000000000069 +:105740000000000000000100000000000000000058 +:105750000000000200000000000000000000000047 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000002000000000000000000000000000007 +:1057A00000000000000000000000000000000000F9 +:1057B00002000000000000000000000000000000E7 +:1057C00000000000000000010202020000000000D2 +:1057D00000000000000200000000000000000001C6 +:1057E00001000100010101000000000000000001B3 +:1057F00000000001000000000000000000000000A8 +:105800000000000001000000000000000000000097 +:105810000000000000000000000000000000000088 +:105820000000000200000100000000000000000075 +:105830000000000000000000000000000000000068 +:105840000000000000000100000000000000000057 +:105850000000000200020100000000000000000043 +:105860000000000000000000000000000000000038 +:105870000000000002020100000000000000000023 +:105880000000000200000000000000000000000016 +:105890000002000000020000000000000000000004 +:1058A00000000000000000000000000000000002F6 +:1058B00002020000000000000000000000000000E4 +:1058C00000000000000000020202020000000000D0 +:1058D00000000000000200000000000000000001C5 +:1058E00001010101010101010100000001000001AD +:1058F00000000101000101000000000000000000A4 +:105900000000010001010100000000000000000093 +:105910000000000001020100000000000000000083 +:10592000000002020201010000000000000000006F +:105930000000020001010100000000000000000062 +:105940000000000000000100000000000000000056 +:105950000000000100020100000000000000000043 +:105960000000000002020100000000000000000032 +:105970000000000002020100000000000000000022 +:105980000000000202020100000000000000000010 +:105990000002000000020000000000000000000003 +:1059A00000000000020001000000000000000002F2 +:1059B00002020200020201000000000000000000DC +:1059C00000000000000000020202020200000000CD +:1059D00000000200020200000000000001000001BF +:1059E00001010101010101010100000001000001AC +:1059F00000010101000101000000000000000000A2 +:105A00000000010001010100000000000001010090 +:105A10000000000001020100000000000000000082 +:105A2000000002020201010000000000000000006E +:105A30000000020001010100000000000001000060 +:105A40000000000000000100000000000000000055 +:105A50000000000100010100000000000000000043 +:105A60000000000002020100000000000000000031 +:105A70000000000001010100000000000000000221 +:105A80000000000102020100000000000000000010 +:105A90000001000000020100000000000000000200 +:105AA00000000000020001000000000000000002F1 +:105AB00001020200020201000000000000000000DC +:105AC00000000000000000020202020200000000CC +:105AD00000000200020200000000000001000101BD +:105AE00001010101010101010101000001000001AA +:105AF000000101010101010000010000000000009F +:105B0000000001000101010000000000000101008F +:105B10000000000001010100000000000000000082 +:105B2000000002010201010000000000000000006E +:105B3000000002000101010000000000000100005F +:105B40000000000000000100000000000000000054 +:105B50000000000100010100000000000000000042 +:105B60000000000001010100000000000000000032 +:105B70000000000001010100000000000000000220 +:105B80000000000101010100000000000000000011 +:105B90000001000000010100000000000000000200 +:105BA00000000000010001000000000000000001F2 +:105BB00001010100010201000000000000000000DE +:105BC00000000000000000020202020200000000CB +:105BD00002000202020200000101000001000101B6 +:105BE00001010101010101010101000001000001A9 +:105BF000000101010101010000010100000000019C +:105C0000000001000101010000000001000101008D +:105C10000001000001010100000000000000000080 +:105C2000000001010101010000000000000000006F +:105C3000000001000101010000000000000100005F +:105C40000000000000000100000000000000000053 +:105C50000000000100010100000000000000000041 +:105C60000000000001010100000000000000000031 +:105C7000000000000101010000000000000000021F +:105C80000000000101010100000000000000000010 +:105C900000010000000101000000000000000002FF +:105CA00000000000010001000000000000000201EF +:105CB00001010100010101000202020200000000D6 +:105CC00000000000000000020202020200000000CA +:105CD00002000202020200000101010101010102B1 +:105CE00001010101010101010101000001000001A8 +:105CF000000101010101010000010100000000019B +:105D0000000001000101010000000001010101008B +:105D1000010100000101010000000000000000007E +:105D2000000001010101010000000000000000006E +:105D3000000001000101010100000000000100005D +:105D40000000000000000100000000000000000052 +:105D50000000000100010100000000000000000040 +:105D60000000000001010100000000000000000030 +:105D7000000000000101010000000000000000011F +:105D8000000000010101010000000000000000000F +:105D900000010000000101000000000000000001FF +:105DA00000000000010001000100000000000201ED +:105DB00001010100010101000202020202020000D1 +:105DC00000000000000000020202020200020002C5 +:105DD00002000202020200000101010101010102B0 +:105DE00001010101010101010101000001000001A7 +:105DF000000101010101010000010100000000019A +:105E00000000010101010100000000010101010287 +:105E1000010100000101010000000000000100007C +:105E2000000001010101010000000000000000006D +:105E3000000001000101010100000000000100025A +:105E40000000000100000100000000000000000050 +:105E5000000000010001010000000000000000003F +:105E6000000000000101010000000000000000002F +:105E7000000000000101010000000000000000011E +:105E8000000000010101010000000000000000000E +:105E900000010000000101000000000000000001FE +:105EA00000000000010001000100000000020201EA +:105EB00001010100010101000101010101010101D4 +:105EC00001010101010101020202020200020002BD +:105ED00002000202020200000101010101010102AF +:105EE00002010101010101010201000001000001A4 +:105EF0000101010101010100010101000100000196 +:105F00000100010101010101000000010101010185 +:105F1000010100000101010000000000000100007B +:105F2000000001010101010000000000000000006C +:105F3000000001000101010100000000000100015A +:105F4000000000010000010000000000000000024D +:105F5000000000010001010000000000000000003E +:105F6000000000000101010000000000000000002E +:105F7000000000000101010000000000000000011D +:105F8000000000010101010000000000000000000D +:105F900000010000000101000000000000000001FD +:105FA00000000000010001000100000000020101EA +:105FB00001010100010101000101010101010101D3 +:105FC00001010101010101020202020202020002BA +:105FD00002000202020200010101010102010102AC +:105FE00002010101010101020201000001000001A2 +:105FF0000101010101010100010101000100010194 +:106000000101010101010101000000010101010183 +:10601000010100000101010000000000000100007A +:10602000000001010101010000000000000000006B +:106030000000010001010101000000000001000159 +:10604000000100010000010100000000000000014B +:10605000020000010001010000000000000000003B +:10606000000000000101010000000000000000002D +:10607000000000000101010000000000000000011C +:10608000000000010101010000000000000000000C +:1060900000010000000101000000000000020001FA +:1060A00000000000010001000100000000020101E9 +:1060B00001010100010101000000000101010101D5 +:1060C00001010101010101020202020202020002B9 +:1060D00002000202020200010202020102020102A7 +:1060E000020201010101010202020000010000019F +:1060F0000101010101010100010101000100010193 +:106100000101010101010101010000010101010181 +:106110000101000001010100000000010101000077 +:10612000000001010101010000000000000000006A +:106130000000010001010101000100000001000157 +:106140000201010100000101000001000002000144 +:106150000200000100010100000000000002000038 +:10616000000000000101010000000000000000002C +:10617000000000000101010000000000000000011B +:10618000000000010101010000000000000000000B +:1061900000010000000101000000000000020001F9 +:1061A00000000000010001000100000000010101E9 +:1061B00001010100010101000000000101010101D4 +:1061C00001010101010101020202020202020002B8 +:1061D00002020202020200010202020102020202A3 +:1061E0000202020101010102020200000201010299 +:1061F0000101010101010100010202000100010190 +:106200000101010101010101010000010101010180 +:106210000101000001010100010000010101020172 +:106220000000010101010100000000000000000069 +:106230000000010001010101000101010001020152 +:106240000201010100000101000101010101000141 +:106250000200000100010100000000010002000036 +:106260000000000201010100000000000000000029 +:10627000000000000101010000000000000000011A +:10628000000000010101010000000000000000000A +:1062900000010000000101000000000000020001F8 +:1062A00000000000010001000100000100010101E7 +:1062B00001010100010101000000000101010101D3 +:1062C00001010101010101020202020202020002B7 +:1062D00002020202020200010202020202020202A1 +:1062E0000202020201010102020200000201010297 +:1062F000010101010101010001020200010001018F +:10630000010101010101010101000001010201017E +:106310000101000001010100010100010101020170 +:106320000100010101010100000000000000000067 +:106330000000010001010101000101010001020151 +:10634000020101010202010100010101010100013C +:106350000102000100010100000000010002000034 +:106360000000020201010100000000000000000026 +:106370000000000001010100000000000000000119 +:106380000000000101010100000000000000000009 +:1063900000010000000101000000000000010001F8 +:1063A00000000000010001000101000100010101E5 +:1063B00001010100010101000000000000000000D7 +:1063C00000000000000101020202020202020202B9 +:1063D00002020102020200010202020202020202A1 +:1063E0000202020201010102020201010201010294 +:1063F000010101010101010002020201010101018B +:106400000101010101010102020001020102020178 +:10641000010100000101010001010001010102016F +:106420000101010101010100000000000002000063 +:10643000000001000101010200010101000102014F +:10644000010101010202010101010101010100013B +:10645000010201010201010000010101000102012C +:106460000002020201010100000000000000000023 +:106470000000000001010100000000000000000118 +:106480000000000101010100000000000000000008 +:1064900000010000000101000000000000010001F7 +:1064A00000000000010001000101000100010101E4 +:1064B00001010100010101000000000000000000D6 +:1064C00000000000000101020202020202020202B8 +:1064D00002020102020200010202020202020202A0 +:1064E0000202020201010102020201010201010293 +:1064F0000102010201010100020202010101010188 +:106500000101010101010102020101020102020176 +:10651000010100000101010001010001010101016F +:106520000101010101010100000101000002000060 +:10653000000001000101010201010101010101014D +:10654000010101010101010101010101010101013B +:10655000010201010201010000010101000101012C +:106560000102020101010100000000000000000022 +:106570000002000001010100000000000000000115 +:106580000000000101010100000000000000000007 +:1065900000010000000101000000000000010001F6 +:1065A00000000000010001000101000101010101E2 +:1065B00001010100010101000000000000000000D5 +:1065C00000010101010001020202020202020202B4 +:1065D00001020101020200020202020202020202A0 +:1065E0000202020202010102020201010201010291 +:1065F0000102020201010100020202010101010285 +:106600000101020102010102020101020202020172 +:10661000010100000101010102010001010101016C +:10662000010101010101010000010101000100015E +:10663000000001000101010201010101010101014C +:106640000101010101010102010101010101010139 +:10665000010101010101010000010101000101012D +:106660000102010101010100000000000000000022 +:106670000202020001010100000000000000000110 +:106680000000000101010100000000000000000006 +:1066900000010000020101000000000000010001F3 +:1066A00000000000010001000101010101010101E0 +:1066B00001010100010101000000000000000001D3 +:1066C00001010101010001020202020202020202B2 +:1066D00001020101010100020202020202020202A1 +:1066E000020202020202010202020101020101028F +:1066F0000102020201010101020202010201010282 +:106700000101020102010102020101020202020171 +:106710000101020001010101020100010101010169 +:10672000010101010101010000010101010100015C +:106730000200010001010102010101010101010149 +:106740000101010101010102010101010101010138 +:10675000010101010101010000010101000101012C +:10676000010101010101010100010000000100021D +:10677000020202000101010000000000000000010F +:106780000200020101010100000000000000000001 +:1067900000010002020101000000000000010001F0 +:1067A00000000000010001000101010101010101DF +:1067B00001010100010101000000000000000001D2 +:1067C00001010101010001020202020202020201B2 +:1067D000010202010101000202020202020202029F +:1067E000020202020202010202020201020201028C +:1067F000010202020102010102020201020102027F +:10680000010102010202010202020202020202016D +:106810000202020002010101020200010102010163 +:10682000010101010101010000010101010100015B +:106830000200010001010102010201010102010146 +:106840000101010101010102020102010101010135 +:10685000010101010101010000010101000101012B +:10686000010101010101010100010000010100021B +:10687000020102000101010000000000000000010F +:1068800002020201010101000000000000000000FE +:1068900000010202020101000000000000010001ED +:1068A00000020002010001000101010101010101DA +:1068B00001010102010101000000000000000000D0 +:1068C00000000001000001020202020202020201B5 +:1068D000010102020101000202020202020202029E +:1068E000020202020202010202020201020202028A +:1068F000020202020102010102020201020102027D +:10690000010102010202010202020202020202016C +:106910000202010002010102020201020102010160 +:106920000101010101010101010101010101000158 +:106930000100010001010102020202010102010144 +:106940000101010101010102020202010101010133 +:106950000101010101010100010101010001010129 +:106960000101010101010101000100000101020218 +:10697000010101020101010000000001000000010D +:1069800002020201010101000000000000000000FD +:1069900000010202010101000000000000010001ED +:1069A00002020202010201010201010101010101D1 +:1069B00001010102010101000000000000000000CF +:1069C00000000000000001020202020102010201B7 +:1069D000020102020101000202020202020202029C +:1069E0000202020202020102020202020202020288 +:1069F0000202020202020102020202020202020278 +:106A00000202020202020102020202020202020267 +:106A1000020201000201020202020102020201015D +:106A20000101010101020101010101010101010155 +:106A30000100010001010102020202010102010143 +:106A40000101010101010102020202010101010132 +:106A50000101010101010100010101010001010128 +:106A60000101010101010101000101000101020117 +:106A7000010101020101010100000001000000010B +:106A800001020101010101000000000000000000FE +:106A900002010201010101000000000000010001EB +:106AA00002020202010201010201010101010101D0 +:106AB00001010102010101000000000000000000CE +:106AC00000000000000001020202020101010201B7 +:106AD000020102020101000202020202020202029B +:106AE0000202020202020102020202020202020287 +:106AF0000202020202020102020202020202020277 +:106B00000202020202020202020202020202020265 +:106B1000020201000202020202020102020201015B +:106B20000101010101020201010202010101010151 +:106B30000100010001010102020202020102010141 +:106B40000101010101010102020202020101010130 +:106B50000101010101010100010202010001010125 +:106B60000101010101010102000101000101020115 +:106B7000010101010101010100000001000000010B +:106B800001010101010101000000000000000002FC +:106B900002010101010101010000000000010001EA +:106BA00002010201010201010201010101010101D1 +:106BB00001010101010101000000000000000000CE +:106BC00000000000000000020202010101010102B8 +:106BD000020101010101000202020202020202029C +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202010102020202020202020202010158 +:106C2000010101010102020202020201010101014E +:106C3000010201020101010202020202010201013C +:106C4000010101010101010202020202020101012E +:106C50000101010101010100020202020001010122 +:106C60000101010101010102010101000101010114 +:106C70000101010101010101000001010002020105 +:106C800001010101010101010000000000000002FA +:106C900002010101010101010000000000010001E9 +:106CA00001010101010101010201010101010101D3 +:106CB00001010101010101000000000000000000CD +:106CC00000000000000000020202010101010102B7 +:106CD000020201010101000202020202020202029A +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202010102020202020202020202010256 +:106D2000010102020102020202020201010101014B +:106D3000010101020202010202020202010201013A +:106D4000010101010101020202020202020201012B +:106D5000010101020101020002020202000101011F +:106D60000101010101010102010201000101010112 +:106D70000101010101010102010001010002020102 +:106D800001010101010101010100000000000202F6 +:106D900001010101010101010000000000010001E9 +:106DA00001010101010101010201010101010101D2 +:106DB00001010101010101000000000000000000CC +:106DC00000000000000000020202010201020102B4 +:106DD000010201010101000202020202020202029A +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202010102020202020202020202010255 +:106E20000201020202020202020202020101010147 +:106E30000101010202020102020202020202010237 +:106E40000101010101010202020202020202010229 +:106E5000010101020102020002020202000101011D +:106E60000101010101010102020201000101010110 +:106E70000101010101010102010001010002020101 +:106E800001010101010101010100000000000201F6 +:106E900001010101010101010000010000010201E5 +:106EA00001010101010101010202010101010101D0 +:106EB00001010101010101000000000000000000CB +:106EC00000000000000000020201010202020102B3 +:106ED0000102010101010002020202020202020299 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202010102020202020202020202010254 +:106F20000202020202020202020202020101010145 +:106F30000101010102020202020202020202010236 +:106F40000102010201010202020202020202020225 +:106F50000101010201020202020202020101010119 +:106F6000010101010101020202020200010101010D +:106F70000101010101010202020001010001010100 +:106F800001010101010101020100000000020201F2 +:106F900001010101010101020000010000010201E3 +:106FA00001010101010101020202010101010101CE +:106FB00001010101010101000000000000000000CA +:106FC00000000000000000020201020202020201B1 +:106FD0000102010101010002020202020202020199 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202010102020202020202020202020252 +:107020000202020202020202020202020201010143 +:107030000101020102020202020202020202010234 +:107040000102020201010202020202020202020223 +:107050000101010201020202020202020101010118 +:107060000101010102020202020202000201010109 +:1070700001010101020202020200010100010102FC +:1070800001010102010102020200000000020101EF +:1070900001010101010101020000010000010201E2 +:1070A00001010101010101020202020201010101CB +:1070B00001010101010101000000000000000000C9 +:1070C00000000000000000020101020202020201B1 +:1070D0000101010101010002020202020202020298 +:1070E0000102020202020202020202020202020281 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:107110000202010102020202020202020202020251 +:107120000202020202020202020202020202010141 +:107130000101020102020202020202020202010233 +:107140000102020201010202020202020202020222 +:107150000101020201020202020202020102020213 +:107160000101010102020202020202010202010106 +:1071700001010101020202020201020200010102F8 +:1071800001010102020202020200000000020101EC +:1071900001020101010101020000010000010101E1 +:1071A00001010101010101020202020201010101CA +:1071B00001010101010101000000000000000000C8 +:1071C00000000000000000020101020102010201B2 +:1071D0000101010101010002020202020202020198 +:1071E0000201020202020202020202020202020280 +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020201023F +:107230000101020102020202020202020202020231 +:107240000102020201010202020202020202020221 +:107250000201020201020202020202020102020211 +:107260000201010102020202020202010202010104 +:1072700001010101020202020201020200010102F7 +:1072800001010102020202020200000000010101EC +:1072900001020101010102020000010000010102DE +:1072A00001010101010102020202020201010102C7 +:1072B00002010101010101000000000000000000C6 +:1072C00000000000000000020102020101010201B1 +:1072D0000101010101010002020202020201020198 +:1072E0000102010102020202020202020202020281 +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:107330000101020102020202020202020202020230 +:10734000020202020101020202020202020202021F +:107350000201020201020202020202020102020210 +:107360000201010102020202020202010202010103 +:1073700001010101020202020202020200010102F5 +:1073800001010102020202020200000000010101EB +:1073900001020101010202020000020000020102DA +:1073A00001010101020102020202020202020202C2 +:1073B00002020201010102000000000000000000C2 +:1073C00000000000000000020102010101010101B2 +:1073D0000101010101010002020202020102010198 +:1073E000010102020202020202020202020202027F +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000010102010202020202020202020202022F +:10744000020202020101020202020202020202021E +:10745000020202020102020202020202010202020E +:107460000201010102020202020202010202010102 +:1074700001010101020202020202020200010102F4 +:1074800001010102020202020200000000010101EA +:1074900001020101010202020000020000020102D9 +:1074A00001010101020102020202020202020202C1 +:1074B00002020201020102000000000000000000C0 +:1074C00000000000000000020202010101010101B0 +:1074D0000101010101010002020202020201020196 +:1074E0000101010102020202020202020202020280 +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000010102010202020202020202020202022E +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:107560000201010102020202020202020202010100 +:1075700001010101020202020202020201010102F2 +:1075800001010102020202020200000000010101E9 +:1075900001020101010202020200020000020102D6 +:1075A00001010101020102020202020202020202C0 +:1075B00002020201020202000000000000000000BE +:1075C00000000000000000020202010101010101AF +:1075D0000101010101010002020202020101010197 +:1075E0000101010101020202020202020202020181 +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020102010202020202020202020202022C +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020101FC +:1076700001010101020202020202020201010102F1 +:1076800001010102020202020201000001010101E6 +:1076900001020101010202020200020100020102D4 +:1076A00001010101020102020202020202020202BF +:1076B00002020201020202000000000000000000BD +:1076C00000000000000000010201010101010101B0 +:1076D0000101010101010002020201010101010198 +:1076E000010101010201020202020202020202027F +:1076F000020102010202020202020202020202026C +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:10773000020102010202020202020202020202022B +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020101020202020202020201010102EE +:1077800001010102020202020202000101010101E3 +:1077900001020101010202020201020101020102D1 +:1077A00001010101020102020202020202020202BE +:1077B00002020201020202000000000000000000BC +:1077C00000000000000000010201010101010101AF +:1077D0000101010101010002020102020101010196 +:1077E0000101010101020202020202020102020180 +:1077F000020201020202020202020202020202016B +:10780000020201020102020202020202020101025C +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020102020202020202020202020229 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020201020202020202020201020102EB +:1078800002010102020202020202000101010101E1 +:1078900001020101010202020202020101020102CF +:1078A00001010101020102020202020202020202BD +:1078B00002020201020202000000000000000000BB +:1078C00000000000000000010101010101010101AF +:1078D0000101010100010002020201010101010197 +:1078E0000101010101010202020202020201010181 +:1078F000010102010201020202020202020201026D +:10790000020102010201020202020202020101025C +:10791000010102020102020202020202020202024A +:107920000202020202020202020202020202020237 +:107930000202020102020202020202020202020228 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020101010101DC +:1079900001020101010202020202020101020102CE +:1079A00001010101020102020202020202020202BC +:1079B00002020201020202000000000000000000BA +:1079C00000000000000000010101010101010101AE +:1079D0000101010100000102010101010101010198 +:1079E0000101010101010202020102020102020180 +:1079F000020101010102020202020102010102016F +:107A0000010201020102020202020201010202015C +:107A1000010102010101010202020202020202024C +:107A20000202020202020202020202020202020236 +:107A30000202020102020202020202020202020227 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020201010101DA +:107A900001020101010202020202020201020102CC +:107AA00001010101020102020202020202020202BB +:107AB00002020201020202020202020202020202A7 +:107AC000020202020202020101010101010101019F +:107AD0000101010100000102020101010101010196 +:107AE0000101010101010102010202020101010182 +:107AF000010101010201020202020202020201016D +:107B0000020101010101010202020201010202015E +:107B10000202010102010102020202020202020249 +:107B20000202020202020202020202020202020235 +:107B30000202020102020202020202020202020226 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020201020102C7 +:107BA00002020101020102020202020202020202B8 +:107BB00002020201020202020202020202020202A6 +:107BC000020202020202020101010101010101019E +:107BD0000101000000000102010101010101010198 +:107BE0000101010101010202020101010101010182 +:107BF0000101010101010102020101010101010173 +:107C00000101010101010202010102020100000261 +:107C10000202010202020202020202020202020245 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020102020202020202020202B5 +:107CB00002020201020202020202020202020202A5 +:107CC000020202020202020101010101010101019D +:107CD0000001000000000102010101010101010198 +:107CE0000101010101010101010102020101010182 +:107CF0000101010101010202010101020101010171 +:107D00000101010101010102010101020200000261 +:107D1000000002020002020202020202020102024A +:107D20000202020202010202020202020202020234 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC000020202020202020101010101010101009D +:107DD0000001000000000102010101010101010197 +:107DE0000101010101010102010101010101010182 +:107DF0000101010101010102020101010101010171 +:107E00000101010101010102020201000201010060 +:107E10000000020000000002020202020101020151 +:107E20000101010101010102020202020202020239 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020202C2 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC000020202020202020101010100000001009F +:107ED0000000000000000101010101010101010198 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010102010101010101010171 +:107F0000010101010101010202020200020101005E +:107F10000101000001000002020102010102010151 +:107F20000101010101020102020202020202020237 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020202C1 +:107FA00002020202020202020202020202020202B1 +:107FB00002020202020202020202020202020202A1 +:107FC000020202020202020101010100000000009F +:107FD0000000000000010101010101010101010196 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010100000002010101010162 +:10801000010100010101010201010101020201024D +:108020000202020202020202020202020202020230 +:108030000202020202020202020202020202020220 +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202020202020202020202C0 +:1080A00002020202020202020202020202020202B0 +:1080B00002020202020202020202020202020202A0 +:1080C000020202020202020101010000000000009F +:1080D0000000000001010101010101010101010194 +:1080E0000101010101010101010101010101010180 +:1080F000010101010101010201010101010101016F +:108100000101010101010100000001010101010162 +:10811000010101010101010201020102020002024A +:108120000202020202000202020202020202020231 +:108130000202020202020202020202020201020220 +:10814000020202020202020202020202020202020F +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202020202020202020202BF +:1081A00002020202020202020202020202020202AF +:1081B000020202020202020202020202020202029F +:1081C000020202020202020101010000000000009E +:1081D0000000000001010101010101010101010193 +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010202020202000102004A +:10822000000000000001000202020202020202023B +:108230000202020202020202020101010101020124 +:108240000201010102020102020201020101010117 +:108250000202010102010102020202020202020202 +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202020202020202020202BE +:1082A00002020202020202020202020202020202AE +:1082B000020202020202020202020202020202029E +:1082C000020202020202020101010000000000009D +:1082D0000000000101010101010101010101010191 +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010002000201010100014E +:108320000101010101010102020200020202020236 +:108330000202020201010201010101010102010127 +:108340000101010101010102010202010202020216 +:108350000101020201020202020202020202020200 +:1083600002020202020202020202020201020202EE +:1083700002020202020202020202020202020202DD +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020202BD +:1083A00002020202020202020202020202020202AD +:1083B000020202020202020202020202020202029D +:1083C000020202020200020101010000000000009E +:1083D000000001010101010101010101010101018F +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010001010101010101014D +:10842000010101010101010202010101010101013A +:108430000202010201010101010202020202010223 +:10844000010202020101020202010002000000001A +:108450000202000002000002020202020202020204 +:1084600002020202020202020202020201020202ED +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020202BC +:1084A00002020202020202020202020202020202AC +:1084B000020202020202020202020202020202029C +:1084C000020202020000020101010000000000019E +:1084D000010001010101010101010101010101018D +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010201010101010101013A +:108530000101010201010102020202020201020222 +:10854000020202020202020000020000000000001B +:10855000000000000000000202020101020201010D +:1085600001020202010101020202020201020202F0 +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020202AB +:1085B000020202020202020202020202020202029B +:1085C000020202020000020101010101000100019A +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:108630000101010101010102020101010101020127 +:108640000201010102020100000000000000000020 +:10865000000000000000000201010202010102020C +:1086600002010101020202020202020202010202EE +:1086700002020202010101020202020202020202DD +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020202AA +:1086B000020202020202020202020202020202029A +:1086C000020200000000020101010101010101019B +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:10874000010101010101010000010101010101011B +:10875000000001010001010102020000020200000C +:1087600000020202000000020101010102020101F7 +:1087700001010101020202020202020202020201DE +:1087800002020201010101020202020202020202CD +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020202A9 +:1087B0000202020202020202020202020202020299 +:1087C00000000000000000010101010101010101A0 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010102000101010001010109 +:1088600001000000010101010202020202000202F5 +:1088700002020202000000020101020101010102E4 +:1088800001010102020202020202020202020202CB +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202020202A8 +:1088B000020202020202020202020202020200009C +:1088C000000000000000000101010101010101019F +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010100010101010101010108 +:1089600001010101010101020001010000010000FB +:1089700000000000010101010202000202020200E7 +:1089800002020200000000020202020202020202CF +:1089900002020202020202020202020202020202B7 +:1089A00002020202020202020202020202020202A7 +:1089B000020202020202020202020202020000009D +:1089C000000000000000000101010101010101019E +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101020000010100000001EA +:108A800000000001010101020202020202020202D0 +:108A900002020202020202020202020202020202B6 +:108AA00002020202020202020202020202020202A6 +:108AB000020202020202020202020202000000009E +:108AC000000000000000000101010101010101019D +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101020002020202020202CE +:108B900002010202020101020202000202020202BA +:108BA00002020202020202020202020202020202A5 +:108BB000020202020202020202020202000000009D +:108BC000000000000000000101010101010101019C +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010114 +:108C50000101010101010101010101010101010104 +:108C600001010101010101010101010101010101F4 +:108C700001010101010101010101010101010101E4 +:108C800001010101010101010101010101010101D4 +:108C900001010101010101020202000202010201BF +:108CA00002020202010201020202020202020202A6 +:108CB000020202020202020202020200000000009E +:108CC000000000000000000101010101010101019B +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101020101010101010101B2 +:108DB00001010102010101020202000000000000A5 +:108DC000000000000000000101010101010101019A +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101020200000000000000A7 +:108EC0000000000000000001010101010101010199 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101020200000000000000A6 +:108FC0000000000000000001010101010101010198 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101020200000000000000A5 +:1090C0000000000000000001010101010101010197 +:1090D0000101010101010102020202020202020277 +:1090E0000202020202020202020202020202020260 +:1090F0000202020202020202020202020202020250 +:10910000020202020202020202020202020202023F +:10911000020202020202020202020202020202022F +:10912000020202020202020202020202020202021F +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202000000000000009D +:1091C0000000000000000001010101010101010196 +:1091D0000101010101010100000000000000000088 +:1091E000000000000000000202020202020202026D +:1091F000020202020202020202020202020202024F +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020200000000000000009E +:1092C0000000000000000001010101010101010195 +:1092D0000101010101010100000000000000000087 +:1092E000000000000000000000000000000000007E +:1092F000000000000000000202020202020202025C +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202000000000000000000CF +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000020000000000000000AB +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000003B000000000000000061 +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:109540000102000000000000000000000000000018 +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700001000000000000000000000000000000EA +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000020200020202020202020202020200027F +:1095D0000002020000000000000000000002000085 +:1095E0000000000200000000000000000002000077 +:1095F0000000000000000000000000000002000069 +:109600000002000000000000000000000000020056 +:109610000002000000000000000000000000020046 +:109620000000010200000000000000020002000033 +:10963000020200020100020000000000000002001F +:109640000202000000020000000000020000000012 +:109650000200010000000000000000000000020005 +:1096600000000000000000000000000000000000FA +:1096700002000202000002000000000002000200DE +:1096800002010200000000000000000000000000D5 +:1096900002000000000000000000000000000200C6 +:1096A00000000200000000000000000200020000B4 +:1096B000000200000002000200020200020002009C +:1096C0000101010101010101010101010101010289 +:1096D0000102020000000000000000000002000083 +:1096E000000000020000000000020202000202006E +:1096F0000102000000000000000000000002020063 +:109700000002000000000000000000000002020053 +:109710000002000000000000020000000002020041 +:10972000000102020000000000000002000202002E +:109730000202020202000200020000000002020017 +:109740000202000200020202000000020200020007 +:109750000200020000000000000000000002020001 +:1097600000000000000000000000000000000001F8 +:1097700002000202010202000000020002020200D6 +:1097800002020200000100000000000002000000D0 +:1097900002020000020002000200000000000200BD +:1097A00000010200000000020000000202020200AC +:1097B000000202020202020202020202020202008D +:1097C0000101010101010101010101010101010288 +:1097D0000102020000000000000000000002000082 +:1097E000000000020000000000020202000202006D +:1097F0000102000000000000000000000002020062 +:109800000102000000000000000000000002020150 +:10981000000200000000000002000000000202023E +:109820000002020202010002000000020002020027 +:109830000202020202000200020000000002020016 +:109840000202010200020202000000020202020003 +:109850000200020000000000000000000002020000 +:1098600000000000000000000000000000000002F6 +:1098700002010202020202020002020002020201CE +:1098800002020200010200000000000002000000CD +:1098900002020000020202020202020000000200B4 +:1098A00000020202020002020000000202020202A2 +:1098B000000202020202020202020202020202008C +:1098C0000101010001010101010101010101010288 +:1098D0000102020000000000000000000002000081 +:1098E000000000020000000000020202000202006C +:1098F0000102000000000000000000000002020061 +:10990000010200000000000000000000000202014F +:10991000000201000000000002000000000202023C +:109920000202020202020202000000020002020021 +:109930000202020202000200020000000202020013 +:1099400002020102010202020200000202020202FD +:1099500002010202010200000200000002020200F5 +:1099600000000000000000000000000000000002F5 +:1099700002020202020202020202020002020202C9 +:1099800002020200020200000000000002000200C9 +:1099900002020201020202020202020200000200AE +:1099A0000202020202020202000202020202020299 +:1099B000000202020202020202020202020202008B +:1099C000010100000000010101010101010101028A +:1099D000010202000000000000020000000200007E +:1099E000000000020000000000020202000202006B +:1099F000020200000000000000000000000202015E +:109A0000020200000000000000000000020202014B +:109A10000102020000010000020000000002020238 +:109A2000020202020202020200000002020202021C +:109A30000202020202000200020000000202020210 +:109A400002020202020202020200000202020202FA +:109A500002010202020200020200000002020200F1 +:109A600000000000000000000000000000000002F4 +:109A700002020202020202020202020002020202C8 +:109A800002020202020202000200000002020202BE +:109A900002020201020202020202020200000200AD +:109AA0000202020202020202020202020202020296 +:109AB000000202020202020202020202020202008A +:109AC000010000000000010101010101010101028A +:109AD000020202000000000000020000000200007C +:109AE000000000020000000000020202000202006A +:109AF000020200000000000000000000020202015B +:109B00000202000000000000000000000202020249 +:109B10000202020001010000020000000002020235 +:109B2000020202020202020200000002020202021B +:109B3000020202020200020202000000020202020D +:109B400002020202020202020200000202020202F9 +:109B500002020202020202020200000002020200ED +:109B600000000000000000000000000000000002F3 +:109B700002020202020202020202020002020202C7 +:109B800002020202020202020202000002020202B9 +:109B900002020202020202020202020200000202A9 +:109BA0000202020202020202020202020202020295 +:109BB000000202020202020202020202020201008A +:109BC0000000000000000000000000000000010292 +:109BD0000202020200000000020200000202000075 +:109BE0000000000200000000000202020002020069 +:109BF0000202000100000000000000000202020258 +:109C00000202000000000000000000000202020248 +:109C10000202020001010000020000000202020232 +:109C2000020202020202020200000002020202021A +:109C3000020202020201020202000000020202020B +:109C400002020202020202020200000202020202F8 +:109C500002020202020202020200020002020200EA +:109C600000000000000000000000000000000002F2 +:109C700002020202020202020202020002020202C6 +:109C800002020202020202020202000202020202B6 +:109C900002020202020202020202020202000202A6 +:109CA0000202020202020202020202020202020294 +:109CB0000202020202020202020202020101010089 +:109CC0000000000000000000000000000000010291 +:109CD0000202020200000000020200000202000074 +:109CE0000000000200010000000202020002020067 +:109CF0000202000100000000000000000202020257 +:109D00000202010001000000000000000202020245 +:109D1000020202010102000002000000020202022F +:109D20000202020202020202000000020202020219 +:109D30000202020202020202020000000202020209 +:109D400002020202020202020202000202020202F5 +:109D500002020202020202020202020202020200E5 +:109D600000000000000000000000000000000002F1 +:109D700002020202020202020202020002020202C5 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020202A3 +:109DA0000202020202020202020202020202020293 +:109DB0000202020202020202020201020101010089 +:109DC0000000000000000000000000000000010290 +:109DD0000202020200000002020200000202000071 +:109DE0000000000201010000000202020002020065 +:109DF0000202000101000000000000000202020255 +:109E00000202010001010000000000000202020243 +:109E1000020202010202000002000000020202022D +:109E20000202020202020202000000020202020218 +:109E30000202020202020202020200020202020204 +:109E400002020202020202020202000202020202F4 +:109E500002020202020202020202020202020202E2 +:109E600002020100000000000000000000000002EB +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020202A2 +:109EA0000202020202020202020202020202020292 +:109EB000020202020202020202010101010101008A +:109EC000000000000000000000000000000001028F +:109ED0000202020200000002020200000202000070 +:109EE0000000000201010000000202020002020064 +:109EF0000202000201000000000000000202020253 +:109F00000202010101010000000000000202020241 +:109F1000020202020202000002000000020202022B +:109F20000202020202020202000000020202020217 +:109F30000202020202020202020200020202020203 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202020202020202E1 +:109F600002020200020000000000000000000202E5 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020202A1 +:109FA0000202020202020202020202020202020291 +:109FB000020101020202020101010101010101008D +:109FC000000000000000000000000000000001028E +:109FD000020202020002020202020000020200006B +:109FE0000000000201020000000202020002020062 +:109FF0000202010201000000000000000202020251 +:10A00000020202010202000000000000020202023D +:10A01000020202020202000002000000020202022A +:10A020000202020202020202020000020202020214 +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020200020002000200000000020202DE +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020102A1 +:10A0A0000202020202020202020202020201010292 +:10A0B000020101020101020101010101010101008E +:10A0C000000000000000000000000000000001028D +:10A0D000020202020002020202020000020200006A +:10A0E000000000020202000000020202020202025C +:10A0F000020201020200000000000000020202024F +:10A10000020202020202000000000000020202023B +:10A110000202020202020000020000000202020229 +:10A120000202020202020202020200020202020211 +:10A1300002020202020202020202020202020202FF +:10A1400002020202020202020202020202020202EF +:10A1500002020202020202020202020202020202DF +:10A1600002020201020202020202000000020202D6 +:10A1700002020202020202020202020202020102C0 +:10A1800002020202020202020202020202020202AF +:10A1900002020202020202020202020202020102A0 +:10A1A0000202020202020202020202020101010292 +:10A1B0000101010101010101010101010101010090 +:10A1C000000000000000000000000000000001028C +:10A1D0000202020202020202020102020201000065 +:10A1E000000000020202000000020202020202025B +:10A1F000020201020200000000000000020202024E +:10A20000020202020202000000000000020202023A +:10A210000202020202020000020000000202020228 +:10A220000202020202020202020200020202020210 +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020102DF +:10A2600002020202020202020202000002020202D2 +:10A2700002020202020202020202020201010102C1 +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020201029F +:10A2A0000202020202020202020202010101010292 +:10A2B000010101010101010101010101010101008F +:10A2C000000000000000000000000000000001028B +:10A2D0000202020202020202020102020201000064 +:10A2E0000001000202020000000202020202020259 +:10A2F000020202020200000000000000020202024C +:10A300000202020202020000000000000202020239 +:10A310000202020202020000020000000202020227 +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020102FE +:10A3400002020202020202020202020202020102EE +:10A3500002020202020202020202020202010102DF +:10A3600002020202020202020202020002020202CF +:10A3700002020202020202020202020201010102C0 +:10A3800002020202020202020202020201020102AF +:10A39000020202020202020202020202020201029E +:10A3A0000202020202020202020202010101010291 +:10A3B000010101010101010101010101010101008E +:10A3C000000000000000000000000000000000028B +:10A3D0000202020202020202020102020201000063 +:10A3E0000002000202020200000202020202020255 +:10A3F000020202020200000000000000020202024B +:10A400000202020202020000000200000202020236 +:10A410000202020202020002020200000202010223 +:10A42000020202020202020202020202020101020E +:10A4300002020202020202020202020202010102FE +:10A4400002020202020202020202020201010102EF +:10A4500002020202020202020202020202010102DE +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020201010102BF +:10A4800002020202020202020202020201010102AF +:10A49000020202020202020202020202020201029D +:10A4A0000202020202020202020202010101010290 +:10A4B000010101010101010101010101010101008D +:10A4C000000000000000000000000000000000028A +:10A4D0000202020202020202010102020201000063 +:10A4E0000002000202020200000202020202020254 +:10A4F0000202020202000000000200000202020248 +:10A500000202020202020200020200000202010232 +:10A51000020202020202020202020002020101021F +:10A52000020202020202020202020202020101020D +:10A5300002020202020202020202020202010102FD +:10A5400002020202020202020202020101010102EF +:10A5500002020202020202020202020201010102DE +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202010201010102BF +:10A5800002020202020202020202020201010102AE +:10A5900002020202020202020202010101010102A0 +:10A5A0000202020202020202020201010101010191 +:10A5B000010101010101010101010101010101008C +:10A5C0000000000000000000000000000000000289 +:10A5D0000202020202020202010102020101000261 +:10A5E0000002000202020200000202020202020253 +:10A5F0000202020202000000020200000201010247 +:10A600000202020202020202020200000201010230 +:10A61000020202020202020202020202020101021C +:10A62000020202020202020202020201020101020D +:10A6300002020202020202020202020201010102FD +:10A6400002020202020202020202020101010102EE +:10A6500002020202020202020202020201010102DD +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202010201010102BE +:10A6800002020202020202020202020201010102AD +:10A6900002020202020202020101010101010102A1 +:10A6A0000202020202020201020101010101010192 +:10A6B000010101010101010101010101010101008B +:10A6C0000000000000000000000000000000000288 +:10A6D0000202020202020201010102020101000261 +:10A6E0000102000202020200000202020201010253 +:10A6F0000202020202000002020200000201010244 +:10A70000020202020202020202020000020101022F +:10A71000020202020202020202020202020101021B +:10A72000020202020202020202020201010101020D +:10A7300002020202020202020202020201010102FC +:10A7400002020202020202020202020101010102ED +:10A7500002020202020202020202020201010102DC +:10A7600002020202020202020202020202020102CA +:10A7700002020202020201020201010201010102BF +:10A7800002020202020202020202020201010102AC +:10A7900002020202020201010101010101010102A2 +:10A7A0000202010202020101010101010101010194 +:10A7B000010101010101010101010101010101008A +:10A7C0000000000000000000000000000000000287 +:10A7D0000202020202020201010201010101000261 +:10A7E0000102020202020200000202020201010250 +:10A7F0000202020202000202020200000201010241 +:10A80000020202020202020202020200010101022D +:10A81000020202020202020202020202010101021B +:10A82000020202020202020202020201010101020C +:10A8300002020202020202020102020201010102FC +:10A8400002020202020202010202020101010102ED +:10A8500002020202020202020202020201010102DB +:10A8600002020202020202020202020202010102CA +:10A8700002020202020101010101010201010102C1 +:10A8800002020202020202020202020101010102AC +:10A8900002020202010101010101010101010102A3 +:10A8A0000202010201010101010101010101010195 +:10A8B0000101010101010101010101010101010089 +:10A8C0000000000000000000000000000000000286 +:10A8D0000202020102020101020201010101000261 +:10A8E000020202020202020000020202020101024E +:10A8F000020202020202020202020000010101023F +:10A90000020202020202020202020202010101022A +:10A91000020202020202020201020202010101021B +:10A92000020202020202020202020201010101020B +:10A9300002020202020201020102020201010102FC +:10A9400002020202020101010102020101010102EF +:10A9500002020202020202020102010101010102DD +:10A9600002020202020202020202020202010102C9 +:10A9700002020101020101010101010101010102C3 +:10A9800002020102020202020101010101010102AF +:10A9900001010202010101010101010101010102A4 +:10A9A0000202010101010101010101010101010195 +:10A9B0000101010101010101010101010101010088 +:10A9C0000000000000000000000000000000000285 +:10A9D0000202010102010101020201020101000261 +:10A9E000020202020202020000020101020101024F +:10A9F000020202020202020202020000010101023E +:10AA00000202020202020202020202020101010229 +:10AA1000020202020202020201020202010101021A +:10AA2000020202020202020102020201010101020B +:10AA300002020202020201020102020101010102FC +:10AA400002010202020101010102020101010102EF +:10AA500002020202020102010102010101010102DE +:10AA600002020202020202020202020201010102C9 +:10AA700002020101010101010101010101010102C3 +:10AA800001020102020101010101010101010102B2 +:10AA900001010102010101010101010101010102A4 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010087 +:10AAC0000000000000000000000000000000000284 +:10AAD000020201010201010202020202010100025E +:10AAE000020202020202020000020101020101024E +:10AAF000020202020202020202020200010101023B +:10AB00000202020202020202020202020101010228 +:10AB10000202020202020202010202020101010219 +:10AB2000020202010102010102020201010101020D +:10AB30000201010101020101010202010101010200 +:10AB400002010201020101010101010101010102F1 +:10AB500001020102020101010101010101010102E1 +:10AB600002020202020202020202020201010102C8 +:10AB700001020101010101010101010101010102C3 +:10AB800001010102010101010101010101010102B3 +:10AB900001010102010101010101010101010102A3 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010086 +:10ABC0000000000000000000000000000000000283 +:10ABD000020101020101020202020201010100025E +:10ABE000020202020202020000010101020101024E +:10ABF0000202020202020202020202020101010238 +:10AC00000202020202020202020202020101010227 +:10AC10000201020202020202010202020101010219 +:10AC2000020201010101010102020201010101020E +:10AC30000101010101020101010101010101010202 +:10AC400001010201010101010101010101010102F2 +:10AC500001020101010101010101010101010102E2 +:10AC600002020202020202020202020201010102C7 +:10AC700001010101010101010101010101010102C3 +:10AC800001010101010101010101010101010102B3 +:10AC900001010102010101010101010101010102A2 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010085 +:10ACC0000000000000000000000000000000000282 +:10ACD000020101020102020201020201010100025D +:10ACE000020202020202020000010101010101024E +:10ACF0000202020202020202020202020101010237 +:10AD00000201020202020202020202020101010227 +:10AD10000201020202020202010202020101010218 +:10AD2000020101010101010102020201010101020E +:10AD30000101010101020101010101010101010201 +:10AD400001010201010101010101010101010102F1 +:10AD500001020101010101010101010101010102E1 +:10AD600002020202020202020101010101010102CA +:10AD700001010101010101010101010101010102C2 +:10AD800001010101010101010101010101010102B2 +:10AD900001010101010101010101010101010102A2 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010084 +:10ADC0000000000000000000000000000000000281 +:10ADD000020101020202020201010101010100025D +:10ADE000020202010202020000010101010101024E +:10ADF0000201020202020202020202020101010237 +:10AE00000201020202020202020202020101010226 +:10AE10000201010202020202010202020101010218 +:10AE20000101010101010101010101010101010211 +:10AE30000101010101010101010101010101010201 +:10AE400001010101010101010101010101010102F1 +:10AE500001020101010101010101010101010102E0 +:10AE600002020202010201010101010101010102CC +:10AE700001010101010101010101010101010102C1 +:10AE800001010101010101010101010101010102B1 +:10AE900001010101010101010101010101010102A1 +:10AEA0000101010101010101010101010101010192 +:10AEB0000101010101010101010101010101010083 +:10AEC0000000000000000000000000000000000181 +:10AED000020101010202010101010101010100025F +:10AEE000020202010202020200010101010101024B +:10AEF0000201020202020202020202020101010236 +:10AF00000201020202020202020202020101010225 +:10AF10000201010202020202010202010101010218 +:10AF20000101010101010101010101010101010210 +:10AF30000101010101010101010101010101010200 +:10AF400001010101010101010101010101010102F0 +:10AF500001010101010101010101010101010102E0 +:10AF600002010202010101010101010101010102CD +:10AF700001010101010101010101010101010102C0 +:10AF800001010101010101010101010101010102B0 +:10AF900001010101010101010101010101010102A0 +:10AFA0000101010101010101010101010101010191 +:10AFB0000101010101010101010101010101010082 +:10AFC0000000000000000000000000000000000180 +:10AFD0000201010101010101010101010101000260 +:10AFE0000202020102020202020101010101010248 +:10AFF0000201020202020202020202020101010235 +:10B000000201020202020202020202020101010224 +:10B01000010101020201020201010101010101021B +:10B02000010101010101010101010101010101020F +:10B0300001010101010101010101010101010102FF +:10B0400001010101010101010101010101010102EF +:10B0500001010101010101010101010101010102DF +:10B0600001010102010101010101010101010101CF +:10B0700001010101010101010101010101010102BF +:10B0800001010101010101010101010101010101B0 +:10B0900001010101010101010101010101010101A0 +:10B0A0000101010101010101010101010101010190 +:10B0B0000201010101010101010101010101010080 +:10B0C000000000000000000000000000000000027E +:10B0D000020101010101010101010101010100025F +:10B0E0000202020102020202020101010101010247 +:10B0F0000201020202020202020202020101010234 +:10B100000101020202020202020102020101010225 +:10B11000010101020101020101010101010101011D +:10B12000010101010101010101010101010101020E +:10B1300001010101010101010101010101010102FE +:10B1400001010101010101010101010101010101EF +:10B1500001010101010101010101010101010102DE +:10B1600001010102010101010101010101010101CE +:10B1700001010101010101010101010101010101BF +:10B1800001010101010101010101010101010101AF +:10B19000010101010101010101010101010101019F +:10B1A000010101010101010101010101010101018F +:10B1B000020101010101010101010101010101007F +:10B1C000000000000000000000000000010100027B +:10B1D000020101010101010101010101010100025E +:10B1E0000202020102020202020101010101010246 +:10B1F0000101020202020202020102020101010235 +:10B200000101020202010202010101010101010228 +:10B21000010101010101010101010101010101011E +:10B22000010101010101010101010101010101010E +:10B2300001010101010101010101010101010101FE +:10B2400001010101010101010101010101010101EE +:10B2500001010101010101010101010101010102DD +:10B2600001010101010101010101010101010101CE +:10B2700001010101010101010101010101010101BE +:10B2800001010101010101010101010101010101AE +:10B29000010101010101010101010101010101019E +:10B2A000010101010101010101010101010101018E +:10B2B000020202010101010101010101010101007C +:10B2C000000000000000000000000000010100017B +:10B2D000020101010101010101010101010000025E +:10B2E0000202020102020102020101010101010246 +:10B2F0000101020202020202010102020101010235 +:10B30000010102020101010101010101010101022A +:10B31000010101010101010101010101010101011D +:10B32000010101010101010101010101010101010D +:10B3300001010101010101010101010101010101FD +:10B3400001010101010101010101010101010101ED +:10B3500001010101010101010101010101010102DC +:10B3600001010101010101010101010101010101CD +:10B3700001010101010101010101010101010101BD +:10B3800001010101010101010101010101010101AD +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010101010101010101028C +:10B3B000020202010101010101010101010101007B +:10B3C000000000000000000000000000010100017A +:10B3D000010101010101010101010101010000025E +:10B3E0000202020102010102020101010101010246 +:10B3F0000101020101020201010101010101010239 +:10B40000010101010101010101010101010101022B +:10B41000010101010101010101010101010101011C +:10B42000010101010101010101010101010101010C +:10B4300001010101010101010101010101010101FC +:10B4400001010101010101010101010101010101EC +:10B4500001010101010101010101010101010101DC +:10B4600001010101010101010101010101010101CC +:10B4700001010101010101010101010101010101BC +:10B4800001010101010101010101010101010101AC +:10B49000010101010101010101010101010101019C +:10B4A000010101010101010101010101010101028B +:10B4B0000202020202010101010101010101010078 +:10B4C0000000000000000000000001010101000177 +:10B4D000010101010101010101010101010000025D +:10B4E0000202020101010102020101010101010246 +:10B4F0000101020101020101010101010101010239 +:10B50000010101010101010101010101010101012B +:10B51000010101010101010101010101010101011B +:10B52000010101010101010101010101010101010B +:10B5300001010101010101010101010101010101FB +:10B5400001010101010101010101010101010101EB +:10B5500001010101010101010101010101010101DB +:10B5600001010101010101010101010101010101CB +:10B5700001010101010101010101010101010101BB +:10B5800001010101010101010101010101010101AB +:10B59000010101010101010101010101010101019B +:10B5A000010101010101010101010101010101028A +:10B5B0000202020202020102020202010101010072 +:10B5C0000000000000000000010101010101000174 +:10B5D000010101010101010101010101000000025D +:10B5E0000201020101010102020101010101010246 +:10B5F000010101010101010101010101010101013B +:10B60000010101010101010101010101010101012A +:10B61000010101010101010101010101010101011A +:10B62000010101010101010101010101010101010A +:10B6300001010101010101010101010101010101FA +:10B6400001010101010101010101010101010101EA +:10B6500001010101010101010101010101010101DA +:10B6600001010101010101010101010101010101CA +:10B6700001010101010101010101010101010101BA +:10B6800001010101010101010101010101010101AA +:10B69000010101010101010101010101010101019A +:10B6A0000101010101010101010101010101010289 +:10B6B000020202020202020202020202020202006C +:10B6C0000100000000000001010101010101000171 +:10B6D000010101010101010101010101000001025B +:10B6E0000201010101010102020101010101010246 +:10B6F000010101010101010101010101010101013A +:10B700000101010101010101010101010101010129 +:10B710000101010101010101010101010101010119 +:10B720000101010101010101010101010101010109 +:10B7300001010101010101010101010101010101F9 +:10B7400001010101010101010101010101010101E9 +:10B7500001010101010101010101010101010101D9 +:10B7600001010101010101010101010101010101C9 +:10B7700001010101010101010101010101010101B9 +:10B7800001010101010101010101010101010101A9 +:10B790000101010101010101010101010101010199 +:10B7A0000101010101010101010101010101010288 +:10B7B0000202020202020202020202020202020269 +:10B7C000020202020202020202020202020202015A +:10B7D000010100010101010101010100000001025C +:10B7E0000201010101010102020101010101010146 +:10B7F0000101010101010101010101010101010139 +:10B800000101010101010101010101010101010128 +:10B810000101010101010101010101010101010118 +:10B820000101010101010101010101010101010108 +:10B8300001010101010101010101010101010101F8 +:10B8400001010101010101010101010101010101E8 +:10B8500001010101010101010101010101010101D8 +:10B8600001010101010101010101010101010101C8 +:10B8700001010101010101010101010101010101B8 +:10B8800001010101010101010101010101010101A8 +:10B890000101010101010101010101010101010198 +:10B8A0000101010101010101010101010101010287 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020159 +:10B8D000010100010101010100010100000001025C +:10B8E0000201010101010101010101010101010147 +:10B8F0000101010101010101010101010101010138 +:10B900000101010101010101010101010101010127 +:10B910000101010101010101010101010101010117 +:10B920000101010101010101010101010101010107 +:10B9300001010101010101010101010101010101F7 +:10B9400001010101010101010101010101010101E7 +:10B9500001010101010101010101010101010101D7 +:10B9600001010101010101010101010101010101C7 +:10B9700001010101010101010101010101010101B7 +:10B9800001010101010101010101010101010101A7 +:10B990000101010101010101010101010101010197 +:10B9A0000101010101010101010101010101010286 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020158 +:10B9D0000101000000010000000000000000010261 +:10B9E0000101010101010101010101010101010147 +:10B9F0000101010101010101010101010101010137 +:10BA00000101010101010101010101010101010126 +:10BA10000101010101010101010101010101010116 +:10BA20000101010101010101010101010101010106 +:10BA300001010101010101010101010101010101F6 +:10BA400001010101010101010101010101010101E6 +:10BA500001010101010101010101010101010101D6 +:10BA600001010101010101010101010101010101C6 +:10BA700001010101010101010101010101010101B6 +:10BA800001010101010101010101010101010101A6 +:10BA90000101010101010101010101010101010196 +:10BAA0000101010101010101010101010101010285 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020157 +:10BAD0000100000000000000000000000000010262 +:10BAE0000101010101010101010101010101010146 +:10BAF0000101010101010101010101010101010136 +:10BB00000101010101010101010101010101010125 +:10BB10000101010101010101010101010101010115 +:10BB20000101010101010101010101010101010105 +:10BB300001010101010101010101010101010101F5 +:10BB400001010101010101010101010101010101E5 +:10BB500001010101010101010101010101010101D5 +:10BB600001010101010101010101010101010101C5 +:10BB700001010101010101010101010101010101B5 +:10BB800001010101010101010101010101010101A5 +:10BB90000101010101010101010101010101010195 +:10BBA000020102010101010101010102020202027E +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020156 +:10BBD0000100000000000000000000000000010162 +:10BBE0000101010101010101010101010101010145 +:10BBF0000101010101010101010101010101010135 +:10BC00000101010101010101010101010101010124 +:10BC10000101010101010101010101010101010114 +:10BC20000101010101010101010101010101010104 +:10BC300001010101010101010101010101010101F4 +:10BC400001010101010101010101010101010101E4 +:10BC500001010101010101010101010101010101D4 +:10BC600001010101010101010101010101010101C4 +:10BC700001010101010101010101010101010101B4 +:10BC800001010101010101010101010101010101A4 +:10BC90000101010101010101010101010101010194 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020155 +:10BCD0000100000000000000000000000001010160 +:10BCE0000101010101010101010101010101010144 +:10BCF0000101010101010101010101010101010134 +:10BD00000101010101010101010101010101010123 +:10BD10000101010101010101010101010101010113 +:10BD20000101010101010101010101010101010103 +:10BD300001010101010101010101010101010101F3 +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101010101010101010101B3 +:10BD800002010101010101010101010101010101A2 +:10BD90000200010101010101010101010101020291 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020154 +:10BDD000010000000000000000000000000101015F +:10BDE0000101010101010101010101010101010143 +:10BDF0000101010101010101010101010101010133 +:10BE00000101010101010101010101010101010122 +:10BE10000101010101010101010101010101010112 +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101010101010101010101B2 +:10BE800001010001010101010101010101010101A3 +:10BE90000202020102020202020202020202020283 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020054 +:10BED000010000000000000000000000010101015D +:10BEE0000101010101010101010101010101010142 +:10BEF0000101010101010101010101010101010132 +:10BF00000101010101010101010101010101010121 +:10BF10000101010101010101010101010101010111 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700002010000010000010101000100000001B8 +:10BF800000000001010101010101010102020202A0 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020053 +:10BFD000010101000000000000000000010101015A +:10BFE0000101010101010101010101010101010141 +:10BFF0000101010101010101010101010101010131 +:10C000000101010101010101010101010101010120 +:10C010000101010101010101010101010101010110 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500002010101010101010101010101010101CF +:10C0600001010101010101010101010101010100C1 +:10C0700001000000000000000000000102020200B8 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020052 +:10C0D0000101010000000000000000000101010159 +:10C0E0000101010101010101010101010101010140 +:10C0F0000101010101010101010101010101010130 +:10C10000010101010101010101010101010101011F +:10C11000010101010101010101010101010101010F +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400002020101010101000101010201010101DD +:10C1500001010001010001010101010101000001D3 +:10C1600001020101000101010101010101000000C2 +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C0000202020202020202020202020202020150 +:10C1D0000101010000000000000000010101010157 +:10C1E000010101010101010101010101010101013F +:10C1F000010101010101010101010101010101012F +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001020201010101010001010101010101ED +:10C2400001010102000202000001010100000001E1 +:10C2500000010000000000000001000002020201D5 +:10C2600002010001000000000000000002020202C2 +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C0000202020202020202020202020200020151 +:10C2D0000101010000000001010101010101010152 +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001020202020101010101010201010101F8 +:10C3300000010102020102000001010001000001F0 +:10C3400000000001000101000000000002020202E2 +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C0000202020202020202020202000000020154 +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101020B +:10C4200000010101010202020101010101000000FD +:10C4300002000001010001000000000002020202EF +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C0000202020202020202020200000000000157 +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010101010101010101013C +:10C4F000010101010101010101010101010101012C +:10C50000010101010101010101010101010101011B +:10C51000010102010101010100010101020101010A +:10C5200002000000000101010000000002020202FE +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020200020202000000000000015A +:10C5D000010101010101010101010101010101014B +:10C5E000010101010101010101010101010101013B +:10C5F000010101010101010101010101010101012B +:10C600000101010101010101010101010201010119 +:10C610000202010101010101000101010102020206 +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C0000202020200000000000000000000000161 +:10C6D000010101010101010101010101010101014A +:10C6E000010101010101010101010101010101013A +:10C6F0000101010101010101010101010201010129 +:10C700000202010101010101010101010102020214 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020000000000000000000000000162 +:10C7D0000101010101010101010101010101010149 +:10C7E0000101010101010101010101010101010139 +:10C7F0000202010101010101010101010102020224 +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020000000000000000000000000161 +:10C8D0000101010101010101010101010101010148 +:10C8E0000101010101010201010102010101010235 +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020257 +:10C9C0000202000000000000000000000000000162 +:10C9D0000101010101010101010101010101010147 +:10C9E000000000000101010101010100000000023E +:10C9F0000202020202020202020202020202020217 +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000200000000000000000000000000000163 +:10CAD0000101010101010101010101010101010146 +:10CAE0000202020200000000000000000202020236 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000200000000000000000000000000000162 +:10CBD0000101010101010101010101010101010244 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000200000000000000000000000000000161 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010101A3 +:10CD80000101010101010101010101010101010193 +:10CD90000101010101010101010101010101010183 +:10CDA0000101010101010101010101010101010173 +:10CDB0000101010101010101010101010101010262 +:10CDC0000200000000000000000000000000000160 +:10CDD0000101010101010101010101010101010044 +:10CDE0000000000000000000000000000000000142 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010101A2 +:10CE80000101010101010101010101010101010192 +:10CE90000101010101010101010101010101010182 +:10CEA0000101010101010101010101010101010172 +:10CEB0000101010101010101010101010101010261 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC000000000000000000000000000000000372A +:10CFD0000000000000000000000000000000000051 +:10CFE000000000000000000000000200000000003F +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D0200000000000000000000000020000000000FE +:10D0300000000002000000000000000000000000EE +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000200000000AE +:10D08000000000000000000002000000000000009E +:10D09000000000000000020000000000000000008E +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000020002020002020254 +:10D0D0000202020200000002020000000000000044 +:10D0E000000000000000000200000200000000003C +:10D0F000000000000000020000000000000000002E +:10D10000000000000002020000000000000000001B +:10D11000000000000000000000000000000000000F +:10D1200000000000000000010202020201000000F5 +:10D1300000000002020200000000000000000000E9 +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000020200000200000000A9 +:10D18000000000020202000002010202000200028E +:10D19000000000000002020000000000000000008B +:10D1A000000000000000020002000000000000007B +:10D1B000020000020202020202000000020002005D +:10D1C0000000000202020200020002020202020249 +:10D1D0000202020200000002020000000000000043 +:10D1E000000000000000000200000200000000003B +:10D1F000000002000000020000000000000000002B +:10D20000000000000002020000000000000000001A +:10D21000000000000000000000000000000000000E +:10D2200000000000000002020202020201020000EF +:10D2300000000002020200000000000000000000E8 +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000020202020200000000A4 +:10D28000000000020202000002020202000202028A +:10D290000200000000020200000001020002000281 +:10D2A0000000000000000200020202000002000272 +:10D2B0000200020202020202020202020202020250 +:10D2C0000000000202020200020202020202020246 +:10D2D000020202020202000202000000000000003E +:10D2E000000000000000000200000200000000003A +:10D2F000000002000000020000000000000000002A +:10D300000200000000020200000000000000000017 +:10D31000000000000000000002000000000000000B +:10D3200000000000020002020202020202020000EB +:10D3300000000002020200000000000000000000E7 +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000020000000000000000BB +:10D3700000000000000000020202020200000000A3 +:10D380000000000202020200020202020002020287 +:10D390000202000000020200020001020202020278 +:10D3A000020000000000020002020200020202026B +:10D3B000020002020202020202020202020202024F +:10D3C0000200000202020200020202020202020243 +:10D3D000020202020202000202000000000000003D +:10D3E0000000000000000002000002000000000039 +:10D3F0000000020000000200000000000000000029 +:10D400000200000000020200000000000000000016 +:10D410000000000000000000020000000000000208 +:10D4200000000000020002020202020202020002E8 +:10D4300000000002020200000000000000000000E6 +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000020000000100000000B9 +:10D4700000000000000000020202020200020000A0 +:10D480000000020202020202020202020002020282 +:10D490000202000000020200020202020202020274 +:10D4A0000202000000000200020202020202020266 +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020002020202020202023E +:10D4D0000202020202020002020002000000000238 +:10D4E0000000000000000002000002000000000038 +:10D4F0000000020000020200000000000000000026 +:10D500000200000000020200000000000000000015 +:10D510000000000000000001020000000000000206 +:10D5200000000000020002020202020202020202E5 +:10D5300002000002020202000000000000000000E1 +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000020200000200000000B5 +:10D57000000000000000000202020202020202009B +:10D580000000020202020202020202020002020281 +:10D59000020202000002020202020202020202026F +:10D5A0000202000200000200020202020202020263 +:10D5B000020202020202020202020202020202024B +:10D5C0000202020202020200010101010101010145 +:10D5D000010101010101010202000200000000023C +:10D5E0000000000000000002000002010000000036 +:10D5F0000000020000020200000000000000000025 +:10D600000200000000020200000000000000000014 +:10D610000000000000000001020001000000000204 +:10D6200000000000020002020202020202020202E4 +:10D6300002000002020202000000000000000000E0 +:10D6400000000000000000000000020000000000D8 +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000020201020200000000B1 +:10D670000000000000000002020202020202020298 +:10D68000000202020202020202020202010202027D +:10D69000020202020002020202020202020202026C +:10D6A0000202020200000200020202020202020260 +:10D6B000020202020202020202020202020202024A +:10D6C0000202020202020200010101010101010144 +:10D6D0000101010101010102020202000000000239 +:10D6E0000002000000020002000002020000000030 +:10D6F0000000020000020200010000000000000023 +:10D700000200000000020200000000000000000013 +:10D710000000000000000001020001000000000203 +:10D7200000000000020202020202020202020202E1 +:10D7300002000002020202000000000000000000DF +:10D7400000000000000000020100020000000000D4 +:10D7500000000000000000000002020000000000C5 +:10D7600000000000000000020202020200010000AE +:10D770000000000000000202020202020202020295 +:10D780000202020202020202020202020202020279 +:10D79000020202020002020202020202020202026B +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020200010100010101010144 +:10D7D0000101010101010102020202000000000238 +:10D7E000000200000002000200000202000000002F +:10D7F0000000020000020201010000000000000021 +:10D800000200000000020200000200000000000010 +:10D810000000000000000002020001000000000201 +:10D8200000000000020202020202020202020202E0 +:10D8300002000002020202000200020000000000DA +:10D8400000000000000000020100020000000000D3 +:10D8500000000000000000020002020000000000C2 +:10D8600000000000000000020202020200010002AB +:10D870000000000000020202020202020202020292 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020102020202020202020249 +:10D8C0000202020202020200010100010101010143 +:10D8D0000101010101010102020202000202000233 +:10D8E000000200000002000200000202000000002E +:10D8F000000002020002020102000000000000001D +:10D90000020000000002020000020000000000000F +:10D9100000000000000000020200020001000002FE +:10D9200000000000020202020202020202020202DF +:10D9300002000002020202000202020000000000D7 +:10D9400000000000000000020102020001020200CB +:10D9500000000000000002020002020000000000BF +:10D9600000000000000000020202020202020202A5 +:10D97000020000000002020202020202020202028F +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B000020202020101010202020202020202024A +:10D9C0000202020202020200010000010001010144 +:10D9D0000101010101010102020202000202000232 +:10D9E000000200000002000200000202000000002D +:10D9F000000002020002020202000000000000001B +:10DA0000020000000002020000020000000000000E +:10DA100000000000000000020200020101000002FC +:10DA200000000000020202020202020202020202DE +:10DA300002000002020202000202020000000000D6 +:10DA400000000000000000020202020102020200C7 +:10DA500000000000000002020202020201010200B6 +:10DA600000000000000200020202020202020202A2 +:10DA7000020200000002020202020202020202028C +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020102020202020202020257 +:10DAB000020202010101010202020202020202024A +:10DAC0000202020202020100000000000000000049 +:10DAD0000000000000000102020202000202000237 +:10DAE000000200000002000200000202000000002C +:10DAF000000002020002020202000000000000001A +:10DB0000020000000002020100020000000000000C +:10DB100000000000000000020200020101000002FB +:10DB200000000000020202020202020202020202DD +:10DB300002000002020202000202020002000200D1 +:10DB400000000000000000020202020202020200C5 +:10DB500000000200000002020202020202020200B1 +:10DB6000000000020002000202020202020202029F +:10DB7000020200000002020202020202020202028B +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020102020202020202020266 +:10DBA0000202020202020102020202020202020256 +:10DBB000020201010101010202020202020202024A +:10DBC000020202020101010000000000000000004A +:10DBD0000000000000000102020202000202000137 +:10DBE000000100000002000200000202000000002C +:10DBF0000002020200020202020100000000000016 +:10DC0000020000000002020100020000000000000B +:10DC100000000000000000020200020102000002F9 +:10DC200000000000020202020202020202020202DC +:10DC300002000002020202000202020202020202CA +:10DC400000020002000002020202020202020202BC +:10DC500002000202000002020202020202020202AA +:10DC6000000000020002020202020202020202029C +:10DC70000202020000020202020202020202020288 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020102020202020202020265 +:10DCA0000202020202020102020202020202020255 +:10DCB000010201010101010202020202020202024A +:10DCC000020202010101010000000000000000004A +:10DCD0000000000000000102020202000202000136 +:10DCE0000001000002020002000002020200000027 +:10DCF0000002020202020202020100000100000012 +:10DD00000200000000020202020200000000000007 +:10DD100000000000000000020200020202000002F7 +:10DD200000000000020202020202020202020202DB +:10DD300002000002020202000202020202020202C9 +:10DD400002020202000202020202020202020202B5 +:10DD500002000202020002020202020202020202A7 +:10DD60000200000200020202020202020202020299 +:10DD70000202020200020202020202020202020285 +:10DD80000202020201010102020202020202020276 +:10DD90000202020202010102020202020202020265 +:10DDA0000202020202020102020202020202020254 +:10DDB0000102010101010102020202020202020249 +:10DDC0000202020101010100000000000000000049 +:10DDD0000000000000000102020202000202000135 +:10DDE0000001000002020002000002020202000024 +:10DDF0000002020202020202020101000100000010 +:10DE00000200000000020202020200000000000006 +:10DE100000000000000000020200020202000002F6 +:10DE200000000000020202020202020202020202DA +:10DE300002020002010102000202020202020202C8 +:10DE400002020202000202020202020202020202B4 +:10DE500002020202020002020202020202020202A4 +:10DE60000200000202020202020202020202020296 +:10DE70000202020200020202020202020202020284 +:10DE80000202020101010102020202020202020276 +:10DE90000202020202010102020202020202020264 +:10DEA0000202020202020102020202020202020154 +:10DEB0000101010101010102020202020202020249 +:10DEC0000202020101010100000000000000000048 +:10DED000000001000000010202020202020202012F +:10DEE000020102000202000200000202020202001D +:10DEF000000202020202020202020200020000000C +:10DF00000200000000020102020200000000000006 +:10DF100000000000000000020200020202000002F5 +:10DF200000000000020201020202020202020202DA +:10DF300002020001010101000202020202020202C9 +:10DF400002020202000202020202020202020202B3 +:10DF500002020202020202020202020202020202A1 +:10DF60000202000202020202020202020202020293 +:10DF70000202020202020202020202020202020281 +:10DF80000202020101010102020202020202020275 +:10DF90000202020202010102020202020202020263 +:10DFA0000202020101010102010202020201010159 +:10DFB0000101010101010102020202020202020248 +:10DFC0000202010101010100000000000000000048 +:10DFD000000001010101010202020102020102012D +:10DFE000020102000201000200020202020202001B +:10DFF000000202020202010202020201020000000B +:10E000000200000000010102020200000000000006 +:10E0100000000000000000020200020202000002F4 +:10E0200000000000020201020202020202020202D9 +:10E0300002020001010101020202020202020202C6 +:10E0400002020202000202020202020202020202B2 +:10E0500002020202020202020202020202020202A0 +:10E060000202000202020202020202020202020292 +:10E070000202020202020102020202020202020281 +:10E080000202010101010102020202020202020275 +:10E090000202020202010102020202020202020163 +:10E0A000010101010101010201010202010101015D +:10E0B0000101010101010102020202020202010149 +:10E0C0000101010101010100000000000000000049 +:10E0D000000001010101010202020102010102012D +:10E0E000020102000201000200020202020202001A +:10E0F000000202020202010202020201020000000A +:10E100000200000000010102020200000000000005 +:10E1100000000000000000020200020202000002F3 +:10E1200000000000010201020202020202020202D9 +:10E1300002020001010101020202020202020202C5 +:10E1400002020202000202020202020202020202B1 +:10E1500002020202020201020202020202020202A0 +:10E16000020202020202020202020202020202028F +:10E170000202020202020102020202020202020280 +:10E180000202010101010102020202020202020175 +:10E190000101010101010102020202020201010169 +:10E1A000010101010101010201010101010101015E +:10E1B000010101010101010202020202010101014A +:10E1C0000101010101010100000000000000000048 +:10E1D000000001010101000202020102010102022C +:10E1E0000202020002010002000202020202020018 +:10E1F0000002020202020102020202020200000008 +:10E200000200000000010102020200000000000004 +:10E2100000000000000000020201020202000002F1 +:10E2200000000000010201020202020202010202D9 +:10E2300002020201010101020202020202020202C2 +:10E2400002020202000202020202020202020202B0 +:10E25000020202020202010202020202020202029F +:10E26000020202020202020202020202020202028E +:10E270000202020202010102020202010202020281 +:10E280000202010101010102020202020201010176 +:10E29000010101010101010202020201010101016A +:10E2A000010101010101010201010101010101015D +:10E2B000010101010101010201020201010101014B +:10E2C0000101010101010100000000000000000047 +:10E2D000000001010101000202020102010102022B +:10E2E0000202010201010002000202020202020017 +:10E2F0000202020202010102020202020200000006 +:10E300000200000002010102020200000000000001 +:10E3100000000000000200020202020202000002ED +:10E3200000000000010101020202010202010202DA +:10E3300002020201010101020202020202020202C1 +:10E3400002020202000201020202020202020202B0 +:10E35000020202020202010202020202020202029E +:10E36000020202020201010202020202020202028F +:10E370000202020202010102020202010202020280 +:10E380000201010101010102010202010201010178 +:10E39000010101010101010201020201010101016A +:10E3A000010101010101010201010101010101015C +:10E3B000010101010101010201010101010101014C +:10E3C0000101010101010100000000000000000046 +:10E3D000000001010101000202020102010102022A +:10E3E0000102010201010002000202020202020017 +:10E3F0000202010202010102020202020201000005 +:10E400000100000002010102020200000000000001 +:10E4100000000000000200020202020202020002EA +:10E4200000000002010101020102010102010201DA +:10E4300001020201010101020202020202020202C1 +:10E4400002020202000201020202020202020202AF +:10E45000020202020202010202020202020202029D +:10E46000020202020201010202020202020202028E +:10E470000202020202010102010102010201010184 +:10E480000101010101010102010201010201010179 +:10E49000010101010101010201010201010101016A +:10E4A000010101010101010201010101010101015B +:10E4B000010101010101010201010101010101014B +:10E4C0000101010101010100000000000000000045 +:10E4D0000000010101010001020202020102010229 +:10E4E0000102020201010002000202020202020015 +:10E4F0000202010202010102020202020202000003 +:10E500000100000002010102020200000000000000 +:10E5100002000000000202020202020202020201E4 +:10E5200002000202010101020101010102010101D7 +:10E5300001020201010101020202020202020202C0 +:10E5400002020201000101020202020202020202B0 +:10E55000020202020101010202020202020202029E +:10E56000020202010101010202020202020202028F +:10E570000202020202010102010101010101010185 +:10E580000101010101010102010101010201010179 +:10E590000101010101010102010102010101010169 +:10E5A000010101010101010201010101010101015A +:10E5B000010101010101010201010101010101014A +:10E5C0000101010101010100000000000000000044 +:10E5D0000000010101010001020102020202010228 +:10E5E0000102020201010002000202020202020014 +:10E5F0000202010202010102020202020202000200 +:10E6000001000000020101020202000000000000FF +:10E6100002020000000202020202020202020201E1 +:10E6200002020202010101020101010101010101D5 +:10E6300001020201010101020202020202020202BF +:10E6400002020101020101020202020202020202AE +:10E65000020201010101010202020202020202029F +:10E660000202020101010102020202010202020190 +:10E670000101010101010102010101010101010189 +:10E680000101010101010102010101010201010178 +:10E690000101010101010102010101010101010169 +:10E6A0000101010101010102010101010101010159 +:10E6B0000101010101010102010101010101010149 +:10E6C0000101010101010100000000000000000043 +:10E6D0000000010101010001010102020202010228 +:10E6E0000202010101010002020202020202020012 +:10E6F0000202010101010102020202020202000201 +:10E7000001000000020101020201000000000000FF +:10E7100002020000000202020102020202020201E1 +:10E7200002020202010101020101010101010101D4 +:10E7300001020201010101020202020202020202BE +:10E7400002020101020101020202020202020102AE +:10E7500002020101010101020201020202020102A0 +:10E760000202020101010102010202010202010191 +:10E770000101010101010102010101010101010188 +:10E780000101010101010102010101010101010178 +:10E790000101010101010102010101010101010168 +:10E7A0000101010101010102010101010101010158 +:10E7B0000101010101010101010101010101010149 +:10E7C0000101010101010100000000000000000042 +:10E7D000000000010100000101010201020202012A +:10E7E0000201010101010002020201020202020211 +:10E7F0000202010101010102020202020202000200 +:10E8000001020000020101020101010000000000FC +:10E8100002020200000202020102020202020201DE +:10E8200002020202010101020101010101010101D3 +:10E8300001010201010101020202020202020202BE +:10E8400002010101020101020202010202010101B1 +:10E8500001010101010101020201010202020101A3 +:10E860000102020101010102010201010102010193 +:10E870000101010101010101010101010101010188 +:10E880000101010101010102010101010101010177 +:10E890000101010101010102010101010101010167 +:10E8A0000101010101010101010101010101010158 +:10E8B0000101010101010101010101010101010148 +:10E8C0000101010101010100000000000000000041 +:10E8D000000000000000000101010202020202012A +:10E8E0000201010101010002020201020202020210 +:10E8F00002020101010101020202020202020202FD +:10E9000001020000020101020101010000000000FB +:10E9100002020200000101020102020202020201DF +:10E9200002020202010101020101010101010101D2 +:10E9300001010101010101020101020202020101C2 +:10E9400001010101020101020202010201010101B2 +:10E9500001010101010101020201010101010101A5 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010102010101010101010176 +:10E990000101010101010101010101010101010167 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010100000000000000000040 +:10E9D000000100000000000101010101020102012B +:10E9E0000101010101010002020201020202020210 +:10E9F00002020101010101020202020202020202FC +:10EA000001020000010101020101010000000000FB +:10EA100002020200000101020102020202020201DE +:10EA200002020202010101010101010101010101D2 +:10EA300001010101010101020101010201010101C4 +:10EA400001010101010101020201010101010101B4 +:10EA500001010101010101020101010101010101A5 +:10EA60000101010101010101010101010101010196 +:10EA70000101010101010101010101010101010186 +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010101010101010101010166 +:10EAA0000101010101010101010101010101010156 +:10EAB0000101010101010101010101010101010146 +:10EAC000010101010101010000000000000000003F +:10EAD000010100000000000201010101010101012A +:10EAE0000101010101010001020201010202020211 +:10EAF00002010101010101020202020202020202FC +:10EB000001020000010101020101020000000000F9 +:10EB100002020202000101020102020202020201DB +:10EB200002020201010101010101010101010101D2 +:10EB300001010101010101020101010101010101C4 +:10EB400001010101010101020201010101010101B3 +:10EB500001010101010101020101010101010101A4 +:10EB60000101010101010101010101010101010195 +:10EB70000101010101010101010101010101010185 +:10EB80000101010101010101010101010101010175 +:10EB90000101010101010101010101010101010165 +:10EBA0000101010101010101010101010101010155 +:10EBB0000101010101010101010101010101010145 +:10EBC000010101010101010000000000000000013D +:10EBD0000101000000000002010101010101010129 +:10EBE0000101010101010001020201010202020210 +:10EBF00002010101010101020102020202020202FC +:10EC000001020200010101020101020000000000F6 +:10EC100002020202000101020102020202020201DA +:10EC200002020101010101010101010101010101D2 +:10EC300001010101010101020101010101010101C3 +:10EC400001010101010101010101010101010101B4 +:10EC500001010101010101020101010101010101A3 +:10EC60000101010101010101010101010101010194 +:10EC70000101010101010101010101010101010184 +:10EC80000101010101010101010101010101010174 +:10EC90000101010101010101010101010101010164 +:10ECA0000101010101010101010101010101010154 +:10ECB0000101010101010101010101010101010144 +:10ECC000010101010101010001000000000000013B +:10ECD0000101000000000002010101010101010128 +:10ECE0000101010101010001020201010202010210 +:10ECF00002010101010101020102020202020202FB +:10ED000001020202010101020101020001000000F2 +:10ED100001010101010101020102010201020201DE +:10ED200002020101010101010101010101010101D1 +:10ED300001010101010101020101010101010101C2 +:10ED400001010101010101010101010101010101B3 +:10ED500001010101010101010101010101010101A3 +:10ED60000101010101010101010101010101010193 +:10ED70000101010101010101010101010101010183 +:10ED80000101010101010101010101010101010173 +:10ED90000101010101010101010101010101010163 +:10EDA0000101010101010101010101010101010153 +:10EDB0000101010101010101010101010101010143 +:10EDC0000101010101010100010000000000010139 +:10EDD0000101000000000002010101010101010127 +:10EDE0000101010101000001020201010101010212 +:10EDF00001010101010101020102020201020202FC +:10EE000001020202010101020101020101000000F0 +:10EE100001010101010101020102010101020201DE +:10EE200001010101010101010101010101010101D2 +:10EE300001010101010101020101010101010101C1 +:10EE400001010101010101010101010101010101B2 +:10EE500001010101010001010101010101010101A3 +:10EE60000101010101010101010101010101010192 +:10EE70000101010101010101010101010101010182 +:10EE80000101010101010101010101010101010172 +:10EE90000101010101010101010101010101010162 +:10EEA0000101010101010101010101010101010152 +:10EEB0000101010101010101010101010101010142 +:10EEC0000101010101010100010000010001010136 +:10EED0000101000000000002010101010101010126 +:10EEE0000101010101000001020101010101010212 +:10EEF00001010101010101020102010201020201FD +:10EF000001010202010101020101020101000000F0 +:10EF100001010101010101020102010101010101DF +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101020101010101010101C0 +:10EF400001010101010101010101010101010101B1 +:10EF500001010101010001010101010101010101A2 +:10EF60000101010101010101010101000101010192 +:10EF70000101010101010101010101010101010181 +:10EF80000101010101010101010101010101010171 +:10EF90000101010101010101010101010101010161 +:10EFA0000101010101010101000101010101010152 +:10EFB0000101010101010101010101010101010141 +:10EFC0000101010101010100010000010001010135 +:10EFD0000101000000000002010101010101010125 +:10EFE0000101010100000101020101010101010211 +:10EFF00001010101010101020101010101010201FF +:10F0000001010101010101020101020102000000F0 +:10F0100001010101010101010102010101010101DF +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101020101010101010101BF +:10F0400001010101010101010101010101010101B0 +:10F0500001010101010101010101010101010101A0 +:10F060000101010101010100010101000101010192 +:10F070000101010101010101010101010101010180 +:10F080000101010101010101010101010101010170 +:10F090000101010101010101010101010101010160 +:10F0A0000101010101010101000001010101010152 +:10F0B0000001000000000001010101010101010146 +:10F0C0000101010101010102020202020202020227 +:10F0D000020202020202020101000101010101011A +:10F0E0000101000100000101020101010101010211 +:10F0F0000101010101010101010101010101010100 +:10F1000001010101010101010101020202000000EF +:10F1100001010101010101010101010101010101DF +:10F1200001010101010101010101010101010101CF +:10F1300001010101010101020101010101010101BE +:10F1400001010101010101010101000101010101B0 +:10F15000010101010101010101010101010101019F +:10F160000101010101010100010101010101010190 +:10F17000010101010101010101010101010101017F +:10F18000010101010101010101010101010101016F +:10F19000010101010101010101010101010101015F +:10F1A0000101010101010101000000000000000057 +:10F1B0000000000000000001010101010101010146 +:10F1C0000101010101010102020202020202020226 +:10F1D000020202020202020101000101010101001A +:10F1E0000100000000000101020101010101010113 +:10F1F00001010101010101010101010101010101FF +:10F2000001010101010101010101020202000000EE +:10F2100001010101010101010101010101010101DE +:10F2200001010101010101010101010101010101CE +:10F2300001010101010101010101010101010101BE +:10F2400001010101010101010101010101010101AE +:10F25000010101010101010101010101010101019E +:10F26000010101010101010101010101010101018E +:10F27000010101010101010101010101010101017E +:10F28000010101010101010101010101010101016E +:10F29000010101010101010101010101010101015E +:10F2A0000101010101010100020000000000000055 +:10F2B0000000000000000001010101010101010145 +:10F2C0000101010101010102020202020202020225 +:10F2D000020202020202020101000000010001001C +:10F2E0000000000000000101010101010101010114 +:10F2F00001010101010101010101010101010101FE +:10F3000001010101010101010201020202000200EA +:10F3100001010101010101010101010101010101DD +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010101010101010101019D +:10F36000010101010101010101010101010101018D +:10F37000010101010101010101010101010101017D +:10F38000010101010101010101010101010101016D +:10F39000010101010101010101010101010101015D +:10F3A0000101010101010100020200000000000052 +:10F3B0000200020202020201010101010101010138 +:10F3C0000101010101010102020202020202020224 +:10F3D000020202020202020101000000000000001D +:10F3E0000000000000000101010101010101010113 +:10F3F00001010101010101010101010101010101FD +:10F4000001010101010101010201020202000200E9 +:10F4100001010101010101010101010101010101DC +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F46000010101010101010101010101010101018C +:10F47000010101010101010101010101010101017C +:10F48000010101010101010101010101010101016C +:10F49000010101010101010100010101010101015D +:10F4A0000101010101010000020202020202020246 +:10F4B0000202020202020201020101010101010134 +:10F4C000010101020202020202020202020202021F +:10F4D000020202020202020100000000000000001D +:10F4E0000000000000000101010101010101010112 +:10F4F00001010101010101010101010101010101FC +:10F5000001010101010101010201020202000200E8 +:10F5100001010101010101010101010101010101DB +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101010101010101010101AB +:10F55000010101010101010101010101010101019B +:10F56000010101010101010101010101010101018B +:10F57000010101010101010101010101010101017B +:10F58000010101010101010102010101010101016A +:10F590000101010101010101020001000000000060 +:10F5A0000000000000000202020202020202020247 +:10F5B000020202020202020102020202020202022C +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020100000000000000001C +:10F5E0000000000000000101010101010101010111 +:10F5F00001010101010101010101010101010101FB +:10F6000001010101010101010201020202000202E5 +:10F6100001010101010101010101010101010101DA +:10F6200001010101010101010101020101020101C8 +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010101010101010101017A +:10F680000101010101010101010102010101010169 +:10F690000101010101010000020200020202020256 +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020100000000000000001B +:10F6E000000000000001010101010101010101010F +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010202020202000102E4 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010201020101020101C6 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F75000010101010101010101000101010101019A +:10F760000101010101010101010101010101010189 +:10F77000010101010101010101000100010101017B +:10F78000010100020101010100000100010000006F +:10F790000000000000020202020202020202020253 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020201010000000000000019 +:10F7E000000000000001010101010101010101010E +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010202010202020101E3 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010201020101020101C5 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010001010101010199 +:10F860000101010101010101020101010101010187 +:10F870000101010101010101020001000101010179 +:10F880000101000102020200020200020002020263 +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020201010000000000000018 +:10F8E000000000000101010101010101010101010C +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010202010201020101E3 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101020202010102010101010101B3 +:10F9400001010202010101010101010101010101A5 +:10F95000010101010101000102000001000100019B +:10F960000101010102010102010101010101010185 +:10F97000010101010101000202020202020202026F +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020201010000000000000017 +:10F9E000000000000101010101010101010101010B +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010102010101020101E4 +:10FA100001010102020101010101010101010101D4 +:10FA200001010101010101010102010201010101C4 +:10FA300001020202020202010001010101010101B1 +:10FA400001010101010100000001010000010200AB +:10FA5000010001010100000101000002020000009C +:10FA60000001010101000001000000000001000090 +:10FA70000000000000020202020202020202020270 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020200010100000000000016 +:10FAE0000000010101010101010101010101010108 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010102010101010101E4 +:10FB100001010102020101010101010101010101D3 +:10FB200001010101010101020002010202010202C0 +:10FB300002020202010101010000010101010101B3 +:10FB400001010000000000000001020000010100AE +:10FB5000020001010000000000000001020000009E +:10FB6000000000020002020002020202020202027F +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020201010100000000000113 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101020101010101010101E3 +:10FC100001010102020101010001010101010101D3 +:10FC200001010101010101010001000101000101C7 +:10FC300001010101010101000000010101010101B7 +:10FC400001010000000000000002010000020000AD +:10FC50000100020202000202020202020202020289 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020200020002020218 +:10FCD0000202020202000001010101010101010111 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000002010101010101020101010101010101E1 +:10FD100002020202020101010001010101010102CE +:10FD200001010101010100000001000100000000CB +:10FD300000010101000000000200020202020202B2 +:10FD40000202000000020202020202020202020299 +:10FD50000202020202020202020202020002020285 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020202020202020202020243 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202020202020202020223 +:10FDC000020202020202020202020002000000021B +:10FDD0000202020000000001010101010101010114 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010001010101010101F4 +:10FE000001010101010000020101010101010101E3 +:10FE100002020201010202010201010101010101CC +:10FE200001010000020202020202000202000202BC +:10FE300002000002020202000202020202020202A8 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020002020284 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202020202020242 +:10FEA0000202020202020202020202020202020232 +:10FEB0000202020202020202020202020202020222 +:10FEC000020202020202020202020002000000001C +:10FED0000000000000000001010101010101010119 +:10FEE00001010101010101020202010101010101FF +:10FEF00001010101020202010000000000000000F7 +:10FF000000000000010000010101010101010101E7 +:10FF100001010101010101020202020202020202C8 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202020202020241 +:10FFA0000202020202020202020202020202020231 +:10FFB0000202020202020202020202020202020221 +:10FFC000020202020202020202020000000000001D +:10FFD0000000000000000001010101010101010118 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101000200000000000000F8 +:02000002C0003C +:1000000000000000020202010101010101010100E2 +:1000100001010101010202020202020202020202C5 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C000020202020202020202000000000000001E +:1000D0000000000000000001010101010101010117 +:1000E0000101010101010100000000000101000106 +:1000F00000010000000000020202020202020202ED +:1001000002020202020202010202010101010200D6 +:1001100002020201010202020202020202020202C1 +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C000020202020202020202000000000000001D +:1001D0000000000000000001010101010101010116 +:1001E0000101010101010100000000000101000105 +:1001F00000010000000000020202020202020202EC +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000020202020202020202020202020202023E +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C000020202020202020202000000000000001C +:1002D0000000000000000001010101010101010115 +:1002E00001010101010101020202020202020202F5 +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202000000000000001B +:1003D0000000000000000001010101010101010114 +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C0000101010101010102000000000000000023 +:1004D0000000000000000001010101010101010113 +:1004E0000101010101010100000000000000000005 +:1004F00000000000000000010101010101010101F3 +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B0000101010101010100000000000000000034 +:1005C0000000000000000002000000000000000029 +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D00000000000000000330000000000000000E7 +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000002000000000000000000000202000093 +:100760000000000000000000000000020000000087 +:100770000000000000000000000000000000000079 +:100780000200020000000000000000000202000061 +:100790000000010000000000000000020000020054 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000002000000000000000000000202000092 +:100860000000020000000000000000020200000082 +:100870000000000000000000000000000000000078 +:10088000020002000000000200000000020202005C +:10089000000102000000020000000002000002004F +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000216 +:1008E0000000000000000000000000000000000008 +:1008F00000000000010000000002000000000200F3 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000200D5 +:1009200000020000000000000002000000020200BF +:1009300000000100000000000000000200000200B2 +:1009400000000200000000000000000000020000A3 +:10095000000200000000000000000000020200028F +:10096000020002000002000000000002020000007D +:100970000000000000000000000000000000000077 +:100980000201020100000002000000000202020059 +:100990000202020002000200000000020000020049 +:1009A0000001000000000000000000000202000240 +:1009B0000200020002000000000200020000020229 +:1009C000020002000000000000000002000002001F +:1009D0000002020000000000000000000000000211 +:1009E0000000000000000000000000000000000007 +:1009F00000000002010102020202000000020200E7 +:100A000000000000000000000000000000000200E4 +:100A100000000000000000000000000000000200D4 +:100A200000020000000000000002000002020200BC +:100A300000010100000000000000000200000202AE +:100A4000000202000000000000000000000200029E +:100A50000202000001000000000000000202020289 +:100A60000200020001020200000000020202000077 +:100A70000000000000000000000000000000000274 +:100A80000202020200000002000000000202020056 +:100A90000202020202020200020000020000020042 +:100AA0000202010001000000000000020202020236 +:100AB0000202020202020202020202020202020216 +:100AC0000202020200000200000000020202020014 +:100AD0000202020202000002000200000000000206 +:100AE0000000000000000000000000000000000006 +:100AF00000000002010102020202000000020200E6 +:100B000000000000000000000000000000000200E3 +:100B100000000000000000000000000000000200D3 +:100B200000020000010000000002000002020200BA +:100B300000010100010000000002000200000202AA +:100B40000002020002000200000000000002000299 +:100B50000202000101010000020000000202020284 +:100B60000200020001020200000200020202020072 +:100B70000000000000000000000000000000000273 +:100B8000020202020002020202000000020202024D +:100B9000020202020202020002020002000002003F +:100BA000020202020200020002000002020202022D +:100BB0000202020202020202020202020202020215 +:100BC000020202020200020000020002020202000F +:100BD0000202020202020202000200000000000201 +:100BE0000000000000000000000000000000000005 +:100BF00000010002020102020202000000020200E3 +:100C000001000000000000000000000000000200E1 +:100C100000000000000000000000000000000200D2 +:100C200000020002010000020002000002020200B5 +:100C300000010200010000000002020200000202A6 +:100C40000002020202000200000000020202020290 +:100C5000020200010201000002020002020202027E +:100C6000020202020102020000020002020202006D +:100C70000000000000000000000000000000000272 +:100C80000202020202020202020200000202020248 +:100C90000202020202020202020202020000020238 +:100CA000020202020200020002020002020202022A +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020006 +:100CD00002020202020202020202000000000002FE +:100CE0000000000000000000000000000000000004 +:100CF00000020002020202020202000000020200E0 +:100D000001000000000000000000000000000200E0 +:100D100000000000000000000000000000000200D1 +:100D200000020002010000020002000002020202B2 +:100D300001020200010000000002020200000202A3 +:100D4000010202020201020000000002020202028D +:100D50000202000202020002020202020202020277 +:100D60000202020202020200020200020202020267 +:100D7000020000000000000000000000000000026F +:100D80000202020202020202020202000202020245 +:100D90000202020202020202020202020000020237 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020005 +:100DD00002020202020202020202020000000002FB +:100DE0000000000000000000000000000000000003 +:100DF00000020002020202020202000000020200DF +:100E000001000000000000000000000000000200DF +:100E100000000000000000000000000000000200D0 +:100E200001020002020100020002000002020202AE +:100E300002020200020000000002020200000202A0 +:100E40000202020202010200020200020202020287 +:100E50000202010202020002020202020202020275 +:100E60000202020202020200020200020202020266 +:100E7000020100000000000000000000000000026D +:100E80000202020202020202020202000202020244 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020004 +:100ED00002020202020202020202020200000002F8 +:100EE00002000000000000000000000000020000FE +:100EF00000020002020202020202000000020200DE +:100F000002000000000000000000000000000200DD +:100F100001000100000000000000000000000202CB +:100F200001020002020100020002000002020202AD +:100F3000020202000200000000020202000002029F +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020200020200020202020265 +:100F70000202000000000000000000000000020269 +:100F80000202020202020202020202000202020243 +:100F90000202020202020202020202020202010232 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202010202010213 +:100FC0000202020202020202020202020202020003 +:100FD00002020202020202020202020202020002F3 +:100FE00002000000000000000000000000020000FD +:100FF00000020002020202020202000000020200DD +:1010000002000000000000000000000000000200DC +:1010100001010100000000000000000000000202C9 +:1010200002020002020200020002000002020202AA +:10103000020202010201000000020202000002029C +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020000000200000000000000020264 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202010202010232 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202010101010214 +:1010C0000202020202020202020202020202020002 +:1010D0000101010101010101010101010101000200 +:1010E00002000000000000000200000002020000F8 +:1010F00000020002020202020202000000020200DC +:1011000002000001000000000000000000000202D8 +:1011100002010100000000000000000000000202C7 +:1011200002020002020200020002000002020202A9 +:101130000202020202020000000202020000020299 +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:101170000202020202020202000000020000020259 +:101180000202020202020202020202020101010242 +:101190000202020202020202020202010202010231 +:1011A000020202020202020202020202020202021F +:1011B0000202020202020202020202010101010213 +:1011C0000202020202020202020202020202010002 +:1011D00001010101010101010101010101010002FF +:1011E00002000000000000000200000002020000F7 +:1011F00000020002020202020202000002020202D7 +:1012000002000001000000000000000000000202D7 +:1012100002010200000000000000000000000202C5 +:1012200002020002020200020002000002020202A8 +:101230000202020202020200000202020000020296 +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:101270000202020202020202000000020000020258 +:101280000202020202020202020202020101010241 +:101290000202020202020202020202010202010230 +:1012A0000202020202020202020202020101010221 +:1012B0000202020202020202020101010101010214 +:1012C0000202020202020202020202010101010004 +:1012D00001010101010101010101010101010002FE +:1012E00002020000000000000200020002020001F1 +:1012F00000020102020202020202000002020202D5 +:1013000002000001000000000000000000000202D6 +:1013100002020200000000000000000200000202C1 +:1013200002020002020200020002000002020202A7 +:101330000202020202020200000202020000020295 +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202010102026F +:10136000020202020202020202020202020202025D +:101370000202020202020202020200020000020253 +:101380000202020202020202020202020101010240 +:10139000020202020202020202020201020201022F +:1013A0000202020202020202020202010101010221 +:1013B0000202020202020201010101010101010215 +:1013C0000202020202020202020202010101010003 +:1013D00001010101010101010101010101010002FD +:1013E00002020000000000000200020002020002EF +:1013F00000020202020202020202000002020202D3 +:1014000002000002000000000000000000000202D4 +:1014100002020201000000000000000200000202BF +:1014200002020002020200020002000002020202A6 +:101430000202020202020202020202020000020290 +:10144000020202020202020202020202020102027D +:10145000020202020202020202020202010101026F +:10146000020202020202020202020201010202025E +:101470000202020202020202020202020000020250 +:10148000020202020202020202020202010101023F +:101490000202020202020202020202010101010230 +:1014A0000202020202020202020202010101010220 +:1014B0000202020201010201010101010101010216 +:1014C0000202020202020202020202010101010002 +:1014D00001010101010101010101010101010102FB +:1014E00002020200000002000202020202020002E6 +:1014F00000020202020202020202000202020102D1 +:1015000002000002000000000000000000000202D3 +:1015100002020201000000000000000200000202BE +:1015200002020002020200020002000201020102A5 +:101530000202020202020202020202020000010290 +:10154000020202020202020202020202020101027D +:10155000020202020202020202020202010101026E +:10156000020202020202020202020201010101025F +:10157000020202020202020202020202000002024F +:10158000020202020202020202020202010101023E +:101590000202020202020102010101010101010233 +:1015A000020202020202020202020201010101021F +:1015B0000202010101010101010101010101010218 +:1015C0000202020202020202020202010101010001 +:1015D0000000000000000000000000000001010207 +:1015E00002020200000002000102020202010002E7 +:1015F00000020202020202020202000202010102D1 +:1016000002000002000000000000000000000202D2 +:1016100002020202000000000000000200000102BD +:1016200002020002020200020002000201010102A5 +:101630000202020202020202020202010000010290 +:10164000020202020202020202020202010101027D +:10165000020202020202020202020201010101026E +:10166000020202020202020202020201010101025E +:10167000020202020202020202020202000201024D +:10168000020202020202020102020202010101023E +:101690000202020201010101010101010101010235 +:1016A000020202020202020202020201010101021E +:1016B0000201010101010101010101010101010218 +:1016C0000202020202020202020101010101010002 +:1016D0000000000000000000000100000001010106 +:1016E00002020200000002000102010201010002E8 +:1016F00001020202020202020202000202010102CF +:1017000002000002000100000000000000000102D1 +:1017100002020202000000000000000200000102BC +:1017200002020202020200020002000201010102A2 +:10173000020202020202020202020201000001028F +:10174000020202020202020202020201010101027D +:10175000020202020202020202020201010101026D +:10176000020202020202020202020201010101025D +:10177000020202020202020202020202000201024C +:101780000202020202020201010101010101010241 +:101790000202010101010101010101010101010236 +:1017A0000202020202020202010101010101010220 +:1017B0000101010101010101010101010101010218 +:1017C0000202010202020101010101010101010005 +:1017D0000000000000000001000101010101010101 +:1017E00002020200000002000102010201010002E7 +:1017F00001020202020202020202000202010102CE +:1018000002000102010100000000000000000102CE +:1018100002020202000002000000000202020102B5 +:10182000020202020202000200020202010101029F +:10183000020202020202020202020201000001028E +:10184000020202020202020202020201010101027C +:10185000020202020202020201010201010101026E +:10186000020202020202020202010201010101025D +:101870000202020202020202020202020202010249 +:101880000202010202010101010101010101010243 +:101890000201010101010101010101010101010236 +:1018A0000202020202020101010101010101010221 +:1018B0000101010101010101010101010101010217 +:1018C0000202010101010101010101010101010007 +:1018D0000000000000000001000101010101010100 +:1018E00002020202000202020101010201010002E1 +:1018F00002020202020202020202000202010102CC +:1019000002000102010200000000000000000102CC +:1019100002020202000002000000000202020102B4 +:10192000020202020202000202010202010101029D +:10193000020202020202020202010101020001028D +:10194000020202020202020202020201010101027B +:10195000020102020202020201010101010101026F +:10196000020202020201010202010201010101025E +:101970000202020202020202020202010202010249 +:101980000202010101010101010101010101010244 +:101990000101010101010101010101010101010236 +:1019A0000202020101010101010101010101010223 +:1019B0000101010101010101010101010101010216 +:1019C0000201010101010101010101010101010007 +:1019D00000000000000000010101010101010101FE +:1019E00002020202000201020201020101010002E0 +:1019F00002020202020202020201000201010102CD +:101A000002000202020200000000000200000102C7 +:101A100002020202000002000000000202020102B3 +:101A2000020202020202000102010202010101029D +:101A3000020202020202020202010101020001028C +:101A4000020202020102020202020201010101027B +:101A5000020102020202020101010101010101026F +:101A6000020201020201010201010201010101025F +:101A70000202020202020202020202010202010248 +:101A80000101010101010101010101010101010245 +:101A90000101010101010101010101010101010235 +:101AA0000201010101010101010101010101010125 +:101AB0000101010101010101010101010101010215 +:101AC0000101010101010101010101010101010007 +:101AD00000000000000001010101010101010101FC +:101AE00001020202020201020201020101010002DE +:101AF00002020202020202010101000201010102CE +:101B000002000202020200000000000200000102C6 +:101B100002020202000002000002000202020102B0 +:101B2000020102020202000102010202010101029D +:101B3000020202020202020202010101020001028B +:101B40000202010101020102010101010101010280 +:101B5000020102020202020101010101010101026E +:101B60000202010102010102010101010101010260 +:101B70000202020202020202020202010201010248 +:101B80000101010101010101010101010101010244 +:101B90000101010101010101010101010101010234 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010214 +:101BC0000101010101010101010101010101010006 +:101BD00000000000010101010101010101010101F9 +:101BE00001020202020201020202020101010002DC +:101BF00002020201020201010101000101010102D0 +:101C000002000202020200000000000200000102C5 +:101C100002020202000202000202020102020102AA +:101C2000020102010202000102010201010101029E +:101C30000202020202020202020101010202010288 +:101C40000201010101020101010101010101010281 +:101C50000101020201010101010101010101010271 +:101C60000101010102010101010101010101010262 +:101C7000020202020201010102010101010101024D +:101C80000101010101010101010101010101010243 +:101C90000101010101010101010101010101010233 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010213 +:101CC0000101010101010101010101010101010005 +:101CD00000000101010101010101010101000102F6 +:101CE00001020202020202020202010101010002DB +:101CF00002020201020201010101000101010102CF +:101D000002000202020202000000000200000102C2 +:101D100002020202020202000202020102020102A7 +:101D2000020102010202000102010201010101029D +:101D30000202020202020202020101010202010287 +:101D40000201010101010101010101010101010281 +:101D50000101020101010101010101010101010271 +:101D60000101010102010101010101010101010261 +:101D7000020202020101010101010101010101014F +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010232 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010004 +:101DD00001010101010100010101000101000102F5 +:101DE00002010202020102010102010101010002DD +:101DF00002020201020201010101000101010102CE +:101E000002000202020202000000000200000102C1 +:101E100002020202020202020202020101010102A6 +:101E2000020102010202020102010201010101029A +:101E30000202020202020202020101010102010287 +:101E40000201010101010101010101010101010280 +:101E50000101010101010101010101010101010271 +:101E60000101010101010101010101010101010261 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010231 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010003 +:101ED00000010101010100010101000101000102F5 +:101EE00002010102020202010101010101010002DD +:101EF00002010201010101010101000101010102D0 +:101F000002020202020202000000000202020102BA +:101F100002020202020202020202020101010102A5 +:101F2000020102010101020102010201010101029B +:101F3000020201020101010101010101010201018D +:101F40000201010101010101010101010101010180 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010260 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010002 +:101FD00000010101010100010001000100000102F6 +:101FE00002010101020101010101010101010002DF +:101FF00002010201010101010101000101010102CF +:1020000002020202020202000002000102020102B8 +:1020100002020202020202020202020101010102A4 +:10202000020102010101020102010101010101029B +:10203000020101010101010101010101010101018F +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:10206000010101010101010101010101010101025F +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010001 +:1020D00000010101000000010001000100000002F8 +:1020E00001010101010101010101010101010002E0 +:1020F00002010201010101010101000101010102CE +:1021000002020202020202000202000102020102B5 +:1021100002020202020202020202020101010102A3 +:10212000020102010101020102010101010101029A +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C0000101010101010101010101010101010000 +:1021D00000010100000000000000000000000002FB +:1021E00001010101010101010101010101010002DF +:1021F00002010101010101010101000101010102CE +:1022000002020202020202000202000101010102B6 +:1022100002020202020202020202020101010102A2 +:10222000020102010101020101010101010101019B +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010100FF +:1022D00000000000000000000000000000000001FD +:1022E00001010101010101010101010100000002E0 +:1022F00002010101010101010101000101010102CD +:1023000002020202020202020202020101010102B1 +:1023100002020102020201020201010101010101A6 +:10232000010101010101020101010101010101019C +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010100FE +:1023D00000000000000000000000000000000001FC +:1023E00001010101010101010101010100000002DF +:1023F00002010101010101010101000101010102CC +:1024000001020201020202020202020101010102B2 +:1024100001010101020201020101010101010101A9 +:10242000010101010101020101010101010101019B +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010100010101010D +:1024C00001010101010101010101010101010100FD +:1024D00000000000000000000000000000000001FB +:1024E00001010101010101010101010000000102DE +:1024F00002010101010101010101000101010102CB +:1025000001020201020102020202020101010101B3 +:1025100001010101020101010101010101010101AA +:10252000010101010101020101010101010101019A +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101014B +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B0000000000000000100000000020000000117 +:1025C00001010101010101010101010101010102FA +:1025D00002020202020202020202020202020201DC +:1025E00001010101010101010101000000000102DE +:1025F00002010101010101010101020101010101C9 +:1026000001020201010101020201020101010101B5 +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:10267000010101010101010101010101010101014A +:10268000010101010101010101010101010101013A +:10269000010101010101010101010100010100012C +:1026A000010101010101010101010101010101001B +:1026B00002020202020200020202020202020201FD +:1026C00001010101010101010101010101010102F9 +:1026D00002020202020202020202020202020201DB +:1026E00001000101010101000001000000000101E1 +:1026F00002010101010101010101010101010101C9 +:1027000001020101010101020101010101010101B7 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101010101010101010159 +:102770000101010101010101010101010101010149 +:102780000101010101010101010101010101010139 +:102790000000000000000000000000000000000138 +:1027A0000101010101010101010101010101010218 +:1027B00002020202020202020202020202020201FA +:1027C00001010101010101010101010101010102F8 +:1027D00002020202020202020202020202020201DA +:1027E00001000000010000000000000000000101E5 +:1027F00001010101010101010101010101010101C9 +:1028000001020101010101010101010101010101B7 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010039 +:102890000000000000000000000000000000000137 +:1028A000010101010101010101010100000000021B +:1028B00002020202020202020202020202020201F9 +:1028C00001010201010101010101010202020202F2 +:1028D00002020202020202020202020202020201D9 +:1028E00000000000000000000000000000000101E6 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010048 +:10298000010101010101010101010101000000003B +:102990000000000000000000000000000000000136 +:1029A000000000000000000000000002020202021D +:1029B00002020202020202020202020202020201F8 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020200D9 +:1029E00000000000000000000000000000000101E5 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010047 +:102A80000100010000000001000000000000000043 +:102A90000000000000000000000000000000000036 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020200D8 +:102AE00000000000000000000000000000000101E4 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010165 +:102B60000101010101010101010101010101010155 +:102B70000101010101000101010101010101000048 +:102B80000200010000000001000000000000000041 +:102B9000000000000000000000000002000002022F +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020200D7 +:102BE00000000000000000000000000001010101E1 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010201010193 +:102C30000101010101010101010101010101010283 +:102C40000101010202010101010101010100000174 +:102C5000020201010101010102020102010101015F +:102C60000000010001010001010001010101010159 +:102C7000000001010000000101000001000000004F +:102C80000100020000000002000000000202020039 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020200D6 +:102CE00000000000000000000000000101010101DF +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000102010101010101010101010201010191 +:102D30000101010101010101010101010101010282 +:102D40000101010101000101010101010000000177 +:102D5000010201010101010101010102020202015E +:102D6000000002000102000100000100000000015B +:102D7000000002020000000200000000000000004D +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020200D5 +:102DE00000000000000000000000000101010101DE +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E2000010201020101010201010102020101018D +:102E30000101010101010101010101010101010281 +:102E40000001010000000101020101000000000278 +:102E50000001020202020201000001010101010061 +:102E60000000010001010000000000020202020057 +:102E70000000010100000001000000020000020249 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020200D4 +:102EE00000000000000000000000010101010101DC +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F2000010201020101010201010102010102018C +:102F30000101010101010101010000020101010182 +:102F4000000000000000010101010100000000017B +:102F5000000101010101010200000201020202025E +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020200D3 +:102FE00000010100000000010101010101010101D6 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:10301000010101010101010101010101010101029F +:10302000010102010202010101010201010201018B +:103030000101010101010101010000010001020182 +:10304000000202000000020200020202020202026A +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020200D2 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010202020201BC +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010102020201019C +:10312000020101010101010102000101010100028E +:103130000202020202020202020202020202020170 +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020200020202020202000001D6 +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010202020201BB +:1032000001010101010101010101010202020101AB +:10321000010101010101010101010101010102009E +:103220000101000000000000010200000002020293 +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020200020202000200000001D9 +:1032E00001010101010101010101010101010101CE +:1032F00001020202010101010101000101010101BC +:1033000001010101010101010101010101010202AB +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202000000020002000200000001DE +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101000101010102BD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020200000000020002000000000001E1 +:1034E00001010101010101010101010101010102CB +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00000000000000000000000000000000001EA +:1035E00001010101010101010101010101010102CA +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00000000000000000000000000000000001E9 +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010102E8 +:1037D00000000000000000000000000000000001E8 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010100F9 +:1038C00000000000000000000000000000000002F6 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000033B4 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000020000000000000084 +:103A40000000000200000000000000000000000074 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000020001000000000033 +:103A90000000000000020000000000000000000024 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000020000000000000083 +:103B4000000000020002020000000000000000006F +:103B50000000000000000000020000000000000063 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B8000000000000000000002000200000200002F +:103B90000000000000020200000000000000000021 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000002000000000000E3 +:103BE00000000000000000020000000000000000D3 +:103BF00000000000000000000000000100000200C2 +:103C000002000202000000000000000000000000AE +:103C100000000000020000000000000000000000A2 +:103C20000000000002000000000000000000000092 +:103C30000000000000000000020000000000000082 +:103C4000020000020002020000000000000000006C +:103C50000000000000000000020000000000000062 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C8000000000000000000202000200000202002A +:103C9000000000000002020000000000000002001E +:103CA000000000000002000200000200000200000C +:103CB0000000000000000200000000000000000002 +:103CC00000000000000000020000000000020000F0 +:103CD00000020000000002000002000200000000DC +:103CE00000000000000000020000000000000000D2 +:103CF00000000000000000000000000102020202BB +:103D000002020202000000000000000000000000AB +:103D1000000000000200020000000000000000009F +:103D2000000000000200020000000000000000008F +:103D3000000000000000020202000000000000007D +:103D40000202000200020200000000000000000069 +:103D50000000000000000000020000000000000061 +:103D60000000000000000001000000000000000052 +:103D70000000000000000000000000000000000043 +:103D80000000000000000002020002000002020227 +:103D90000000000002020200000000000002020217 +:103DA0000000000000020202000202020002020003 +:103DB00000000000000202000102020200000200F6 +:103DC00000000000000200020202020200020200E3 +:103DD00000020000020202000002020200000000D5 +:103DE00000000000000000020000000000000000D1 +:103DF00000000000000000000000000102020202BA +:103E000002020202000000000000000000000000AA +:103E1000000000000200020000000000000000009E +:103E2000000000000200020000000000000000008E +:103E3000000000000000020202010000000000007B +:103E40000202000200020200000000000000000068 +:103E50000000000000000000020000000000000060 +:103E60000000000000000002000000000000000050 +:103E70000000000000000000000000000002000040 +:103E80000000000000000002020202020002020222 +:103E9000020002000202020001000200000202020F +:103EA00000000000000202020002020202020202FE +:103EB00000000000000202020202020202020202EC +:103EC00000000000000202020202020202020202DC +:103ED00000020000020202000002020202020000D0 +:103EE00000020000000000020000000000000000CE +:103EF00000000000000000000000000202020202B8 +:103F000002020202000000000000000000000000A9 +:103F1000000000000200020100000000000000009C +:103F2000000000000200020200000000000000008B +:103F30000000000000000202020101000102000076 +:103F40000202000200020200000000000000000067 +:103F5000000000000000000002000000000000005F +:103F6000000000000000000200000000000000004F +:103F7000000000000000000000000001000200003E +:103F8000000000000000000202020202020202021F +:103F90000202020002020202020002000202020207 +:103FA00000020000000202020202020202020202F9 +:103FB00002000200000202020202020202020202E7 +:103FC00002000000000202020202020202020202D9 +:103FD00002020202020202000002020202020202C5 +:103FE00000020002000000020200000000000000C9 +:103FF00000000000000000000000000202020202B7 +:1040000002020202000000000000000000000000A8 +:10401000000000000200020200000000000000009A +:104020000000000002000202010001000000000088 +:104030000000000000000202020201000102000074 +:104040000202000200020200000000000000000066 +:10405000000000000000000002000000000000005E +:10406000000000000000000200000000000000004E +:104070000000000000000000010200020002000237 +:10408000000000000002020202020202020202021A +:104090000202020202020202020202020202020200 +:1040A00002020202000202020202020202020202F2 +:1040B00002020200000202020202020202020202E4 +:1040C00002020000000202020202020202020202D6 +:1040D00002020202020202000002020202020202C4 +:1040E00002020002000000020200000000000000C6 +:1040F00000000000000000000000000202020202B6 +:1041000002020202000002020000000000000000A3 +:104110000000000002000202000000000000000099 +:104120000000000002000202010001000100000086 +:104130000000000000000202020202000202000071 +:104140000202000200020200000000000000000065 +:10415000000000000000000002000000000000005D +:10416000000000000000000200000000000000004D +:104170000000000000000000020200020002020233 +:104180000000000000020202020202020202020219 +:1041900002020202020202020202020202020202FF +:1041A00002020202000202020202020202020202F1 +:1041B00002020202000202020202020202020202E1 +:1041C00002020202000202020202020202020202D1 +:1041D00002020202020202000002020202020202C3 +:1041E00002020202000000020200000000000000C3 +:1041F00000000000000200000001010202020202B1 +:1042000002020202000002020001000100000000A0 +:104210000000000002000202000000000000000098 +:104220000000000002000202010102000100000083 +:10423000000000000000020202020201020202006D +:104240000202000200020200000000000000000064 +:104250000000000000000002020000000001000059 +:104260000000000000000002020000000001000049 +:10427000000000000000000202020002020202022E +:104280000002000000020202020202020202020216 +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202000202020202020202020202E0 +:1042C00002020202000202020202020202020202D0 +:1042D00002020202020202000002020202020202C2 +:1042E00002020202020000020200000000000000C0 +:1042F00000000000000200000001010202020202B0 +:10430000020202020000020200010001000000009F +:104310000000000002000202000000000000000097 +:104320000000000002000202020102000200000080 +:104330000000000000000202020202020202020269 +:104340000202000200020200000000000000000063 +:104350000000000000000002020000000002000057 +:104360000000000000000002020000000001000048 +:10437000000000000000000202020202020202022B +:104380000202020000020202020202020202020211 +:1043900002020202020202020202020202020202FD +:1043A00002020202020202020202020202020202ED +:1043B00002020202020202020202020202020202DD +:1043C00002020202020202020202020202020202CD +:1043D00002020202020202000002020202020202C1 +:1043E00002020202020200020200000000000000BD +:1043F00000000000000200000101010202020202AE +:10440000020202020000020200010001000000009E +:104410000000000002000202000000000000000096 +:10442000000000000200020202020200020000007E +:104430000000000002000202020202020202020266 +:104440000202000200020200000000000000000062 +:104450000000000000000002020202000002000052 +:104460000000000000000002020000000001000047 +:10447000000000000000000202020202020202022A +:104480000202020000020202020202020202020210 +:1044900002020202020101020202020202020202FE +:1044A00002020202020202020202020202020202EC +:1044B00002020202020202020202020202020202DC +:1044C00002020202020202020202020202020202CC +:1044D00002020202020201000001010101010101C8 +:1044E00001010101010100020200000000000000C2 +:1044F00000000000000200010102020202020202AA +:10450000020202020000020200020002000000009B +:104510000000000002000202000000000000000095 +:10452000000000000200020202020200020000007D +:104530000000000002000202020202020202020265 +:104540000202000200020200000000000000000061 +:104550000000000000000002020202000002000051 +:10456000000000000002000202020000000202003F +:104570000000000000000002020202020202020229 +:10458000020202020002020202020202020202020D +:1045900002020202020101020202020202020202FD +:1045A00002020202020101020202020202020202ED +:1045B00002020202020201020202020202020202DC +:1045C00002020202020202020202020202020202CB +:1045D00002020202020101000001010101010101C8 +:1045E00001010101010100020200020000000000BF +:1045F00000000000000200020202020202020202A7 +:104600000202020200020202020200020000000096 +:104610000000000002000202020000000000000092 +:104620000000000002000202020202010200020079 +:104630000000000002000202020202020202020264 +:10464000020200020002020200000000000000005E +:10465000000000000000000202020202000200004E +:104660000000000002020202020202010002020037 +:104670000000000000000002020202020202020228 +:10468000020202020002020202020202020202020C +:1046900002020202020101020202020202020202FC +:1046A00002020202020101020202020202020202EC +:1046B00002020202020201020202020202020202DB +:1046C00002020202020202020202020202020202CA +:1046D00002020202010101000001010101010101C8 +:1046E00001010101010101020200020000000000BD +:1046F00000000000000200020202020202020202A6 +:104700000202020200020202020200020000000095 +:104710000000000002000202020000000000000091 +:104720000000000002000202020202020200020275 +:104730000000000002000202020202020202020263 +:10474000020200020002010202010000000000005B +:104750000000020200000002020202020002000049 +:104760000000000002020202020202020002020233 +:104770000000000200000202020202020202020223 +:104780000202020202020202020202020202020209 +:1047900002020202020101020202020202020202FB +:1047A00002020202020101020202020202020202EB +:1047B00002020202020101020202020202020202DB +:1047C00002020202020101020202020202020202CB +:1047D00002010202010101000001010101010101C8 +:1047E00001010101010101020200020000000000BC +:1047F00000000200020200020202020202020202A1 +:104800000202020200020202020200020000000094 +:10481000000000000200020202010100000000008E +:104820000000000002000202020202020200020274 +:104830000000000002020202020202020202020260 +:104840000202020200010102020200000000000058 +:104850000000020200000002020202020202020242 +:10486000000002020202020202020202000202022E +:104870000000000200000202020202020202020222 +:104880000202020202020102020202020202020209 +:1048900002020202010101020202020202020202FB +:1048A00002020202020101020202020202020202EA +:1048B00002020202020101020202020202020202DA +:1048C00002020202020101020202020202020202CA +:1048D00002010202010101000001010101010101C7 +:1048E00001010101010101020200020000000000BB +:1048F00000000200020100020202020202020202A1 +:104900000202020200020202020200020100000092 +:10491000000000000200020202010200000000008C +:104920000000000002000102020202020200020274 +:104930000000000002020102020202020202020260 +:104940000202020100010102020200000000000058 +:104950000000020200000002020202020202020241 +:104960000200020202020202020202020202020229 +:10497000000200020002020202020202020202021D +:104980000202020202010102020202020202020209 +:1049900002020102010101020202020202020202FB +:1049A00002020202020101020202020202020202E9 +:1049B00002020202020101020202020202020202D9 +:1049C00002020202020101020202020202020202C9 +:1049D00002010101010101000000000000000000CF +:1049E00000010001000001010200020000000000BF +:1049F00000000200020100020202020202020202A0 +:104A00000202020200020202020200020100000091 +:104A1000000000000200010202020200000000008B +:104A20000000000001000102020202020200020274 +:104A3000020000000202010202020202020202025D +:104A40000202020100010102020200000100000056 +:104A50000000020200000002020202020202020240 +:104A60000202020202020202020202020202020226 +:104A7000020200020002020202020202020202021A +:104A8000020202020201010202020202020101010B +:104A900001010101010101020202020202020101FF +:104AA00002010101010101020202020202020202EC +:104AB00002020102020101020202020202020202D9 +:104AC00002020202020101020202020202010101CB +:104AD00001010101010101000000000000000000CF +:104AE00000010101000101010100020000000000BD +:104AF00000000100020100020202020202020202A0 +:104B00000202020100020102020200020200000091 +:104B10000000000001000102020202000002000089 +:104B20000000000001000102020202020200020273 +:104B3000020200000202010202020202020202025A +:104B40000202020100010102020200010100000054 +:104B5000000002020000000202020202020202023F +:104B60000202020202010102020202020202020227 +:104B70000202020200020202020202020202020217 +:104B8000020202020201010202020202020101010A +:104B900001010101010101020202020202010101FF +:104BA00001010101010101020202020202010101EF +:104BB00001010101010101020202020202020202DC +:104BC00002020202020101020202020101010101CC +:104BD00001010101010101000000000000000000CE +:104BE00000010101010101010102020200020002B3 +:104BF000020001000201000202020202020202029D +:104C00000202010100020102020200020200000091 +:104C10000000000001000102020202000002000088 +:104C20000000000001000102020202020200020272 +:104C30000202020202020102020202020202020255 +:104C40000101020102010102020200010200000052 +:104C5000000002020000000202020202020202023E +:104C60000202020202010102020202020202020226 +:104C70000202020200020102020202020202020217 +:104C8000020202020201010202020101010101010C +:104C900001010101010101020202020201010101FF +:104CA00001010101010101020202020101010101F0 +:104CB00001010101010101020202020202020101DD +:104CC00001010101010101020201010101010101D2 +:104CD00001010101010101000000000000000100CC +:104CE00001010101010101010102010200020002B2 +:104CF000020001000101000202020202020202029D +:104D00000101010100020102020200020202000090 +:104D10000000000001000102020202000102000086 +:104D20000000000001000102020202020201020270 +:104D30000202020202020102020202020202020254 +:104D4000010102010201010202020202020002004C +:104D5000000002020000000202020202020202023D +:104D60000202020202010102020202020202020225 +:104D70000202020200020102020202020201020118 +:104D8000020101020201010201010101010101010F +:104D90000101010101010102020201010101010100 +:104DA00001010101010101020201010101010101F1 +:104DB00001010101010101020202020101010101DF +:104DC00001010101010101020201010101010101D1 +:104DD00001010101010101000000000100000101C9 +:104DE00001010101010101010102010202020202AD +:104DF0000202020201010002020202020202010199 +:104E0000010101010201010202020202020200008C +:104E10000000000001000102020202010202020081 +:104E2000000000000102010202020202020202026C +:104E30000202020201020102020202020202020254 +:104E40000101020102010102020202020202020247 +:104E5000000002020000020201020202020202023B +:104E60000202020201010102020202020202020225 +:104E70000202020202010102020202020201010117 +:104E80000101010101010102010101010101010111 +:104E90000101010101010102020101010101010100 +:104EA00001010101010101020201010101010101F0 +:104EB00001010101010101020201010101010101E0 +:104EC00001010101010101020201010101010101D0 +:104ED00001010101010101000001010101010101C4 +:104EE00001010101010101010102010202020201AD +:104EF000010202020101000202020202010101019B +:104F0000010101010201010202020202020200008B +:104F1000000000000100010202020202020202027D +:104F2000000000000102010202020202020202026B +:104F30000202020201010102010202020201020256 +:104F40000101020102010102020202020202020246 +:104F50000000020202000202010202020202020238 +:104F60000202020201010102020202020202020224 +:104F70000202020202010102020202010101010118 +:104F80000101010101010102010101010101010110 +:104F900001010101010101020201010101010101FF +:104FA00001010101010101020201010101010101EF +:104FB00001010101010101020201010101010101DF +:104FC00001010101010101020101010101010101D0 +:104FD00001010101010101000001000101010101C4 +:104FE00001010101010101020202010202010201AB +:104FF000010102020101000202020202010101019B +:10500000010101010201010202020202020200008A +:10501000000000000100010202020202020202027C +:10502000000000000102010202020202020202026A +:105030000202020201010102010202020201010157 +:105040000101020102010102020202020202020245 +:105050000002010102000202010202020201020238 +:105060000202020201010102020202020202010224 +:105070000202020102010102020102010101010119 +:10508000010101010101010201010101010101010F +:1050900001010101010101020201010101010101FE +:1050A00001010101010101020201010101010101EE +:1050B00001010101010101020201010101010101DE +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101000001000101010101C3 +:1050E00001010101010101020202020202010101AA +:1050F000020101010101000202020202010101019B +:105100000101010102010102020202020202000287 +:10511000000000000100010202020202020202027B +:105120000000000001020102020202020202020269 +:105130000202020201010102010202020101010157 +:105140000101010102010102020202020202020245 +:105150000002010102000102010202020201020139 +:105160000101010101010102020202020202010128 +:10517000020102010201010202010101010101011A +:10518000010101010101010101010101010101010F +:1051900001010101010101020101010101010101FE +:1051A00001010101010101020201010101010101ED +:1051B00001010101010101020201010101010101DD +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101000001000101010001C3 +:1051E00001010101010101020202020202010102A8 +:1051F000020201010101000202020201010101019A +:105200000101010102010102020202020202020284 +:10521000000000000100010202020202020202027A +:105220000000020001010102020202020202020267 +:105230000202020201010102010102010101010158 +:105240000101010101010102020202020202020245 +:10525000000201010200010201010201010102013B +:105260000101010101010102010202020202010128 +:10527000010101010101010202010101010101011C +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101020101010101010101DD +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101000001000101000001C3 +:1052E00000010001000001020202020102020202AA +:1052F000010201010101000202020201010101019A +:105300000101010101010102020202020202020284 +:105310000000000001000102020202020202020279 +:105320000002020001010102020202020102010167 +:105330000202020201010101010101010101010159 +:105340000101010101010102020202020202020244 +:10535000020201010100010201010101010101013B +:10536000010101010101010101010101010201012C +:10537000010101010101010201010101010101011C +:10538000010101010101010101010101010101010D +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101000000000000000000C6 +:1053E00000010000000000020201020101020202AD +:1053F000010101010101000202020201010101019A +:105400000101010101010102020202020202020283 +:105410000000000001000102020202020202020278 +:105420000202020201010102020201020102010163 +:10543000010101010101010101010101010101015C +:105440000101010101010102020202020202020243 +:10545000020201010100010101010101010101013B +:10546000010101010101010101010101010101012C +:10547000010101010101010201010101010101011B +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101000200000000000000C3 +:1054E00000000000000000020101010101020101B1 +:1054F0000101010101010002020202010101010199 +:105500000101010101010102020202020202020282 +:105510000002000001000102020202020202020275 +:105520000202020201010101020101010102010165 +:10553000010101010101010101010101010101015B +:105540000101010101010102010102020202020244 +:10555000020201010100010101010101010101013A +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101000200000000000000C2 +:1055E00000000000000000010101010101010101B2 +:1055F000010101010100000202010101010101019B +:105600000101010101010102020202010202020282 +:105610000202000001020101020202020201020272 +:105620000202020201010101020101010102010164 +:10563000010101010101010101010101010101015A +:105640000101010101010101010102020202010146 +:10565000020101010100010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101000200000000000000C1 +:1056E00000000000000000010101010101010101B1 +:1056F000010101010100000202010101010101019A +:105700000101010101010101020102010202020283 +:105710000202000001010101010201020201010176 +:105720000202010201010101020101010102010164 +:105730000101010101010101010101010101010159 +:105740000101010101010101010102020101010147 +:105750000201010101010101010101010101010138 +:105760000101010101010101010101010101010129 +:105770000101010101010101010101010101010119 +:105780000101010101010101010101010101010109 +:1057900001010101010101010101010101010101F9 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101000200000000000000C0 +:1057E00000000000000000010101010101010101B0 +:1057F000010101010000010201010101010101019A +:105800000101010101010101010102010101020285 +:105810000202020201010101010101020101010173 +:105820000201010101010101010101010102010166 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101020202020202020202AF +:1058E00002020202020202010101010101010101A1 +:1058F000010101010000010101010101010101019A +:105900000101010101010101010102010101020185 +:105910000202020201010101010101010101010173 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101020202020202020202AE +:1059E00002020202020202010101010101010101A0 +:1059F000010100000000010101010101010101019B +:105A00000101010101010101010101010101010186 +:105A10000201020201010101010101010101010173 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010101010101010101010116 +:105A80000101010101010101010101010101010106 +:105A900001010101010101010101010101010101F6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00001010101010101010101010101010101C6 +:105AD00001010101010101020202020202020202AD +:105AE00002020202020202010100010001010101A1 +:105AF000000100000000010101010101010101019B +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010175 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101010101010101010145 +:105B50000101010101010101010101010101010135 +:105B60000101010101010101010101010101010125 +:105B70000101010101010101010101010101010115 +:105B80000101010101010101010101010101010105 +:105B900001010101010101010101010101010101F5 +:105BA00001010101010101010101010101010101E5 +:105BB00001010101010101010101010101010101D5 +:105BC00001010101010101010101010101010101C5 +:105BD00001020101020202020202020202020202A8 +:105BE00002020202020202010000000000010000A5 +:105BF000000000000000010101010101010101019B +:105C00000101010101010101010101010101010184 +:105C10000101010101010101010101010101010174 +:105C20000101010101010101010101010101010164 +:105C30000101010101010101010101010101010154 +:105C40000101010101010101010101010101010144 +:105C50000101010101010101010101010101010134 +:105C60000101010101010101010101010101010124 +:105C70000101010101010101010101010101010114 +:105C80000101010101010101020102010101010102 +:105C900001010101010000010101010101010101F6 +:105CA00001010101010101010101010101010101E4 +:105CB00001010101010100010101010101010101D5 +:105CC00001010101010101010102020202020202BD +:105CD00002020202020202020202020202020202A4 +:105CE00002020202020202000000000000000000A6 +:105CF000000000000000010101010101010101019A +:105D00000101010101010101010101010101010183 +:105D10000101010101010101010101010101010173 +:105D20000101010101010101010101010101010163 +:105D30000101010101010101010101010101010153 +:105D40000101010101010101010101010101010143 +:105D50000101010101010101020101010101010132 +:105D60000101010101010101020101010101010122 +:105D70000101010101010101010101010101010113 +:105D80000101010101010101010001000000000009 +:105D900000000000010000010101010101010101F9 +:105DA00001010101010202010100010000000000E7 +:105DB00000000000000100010101010101010101D9 +:105DC00001010101010101020202020202020202BA +:105DD00002020202020202020202020202020202A3 +:105DE00002020202020202000000000000000000A5 +:105DF0000000000000000101010101010101010199 +:105E00000101010101010101010101010101010182 +:105E10000101010101010101010101010101010172 +:105E20000101010101010101010101010101010162 +:105E30000101010101010101010101010101010152 +:105E40000101010101010102020101010101010140 +:105E50000101010101010102010101010101010131 +:105E60000101010101000001010101010101010124 +:105E70000101010101010101010102010101010111 +:105E8000010101010101000100000000000000000B +:105E900000000000010000010102020202020202F1 +:105EA00002020202020202010100000000000000E2 +:105EB00000000000000000010101010101010101D9 +:105EC00001010101010202020202020202020202B7 +:105ED00002020202020202020002020202020202A4 +:105EE00002020202020202000000000000000000A4 +:105EF0000000000000010101010101010101010197 +:105F00000101010101010101010101010101010181 +:105F10000101010101010101010101010101010171 +:105F20000101010101010101010101010101010161 +:105F30000101010101010101010101010101010151 +:105F4000010101010101010202010101010101013F +:105F50000101010101010101000101010000010035 +:105F60000000010101000001000101010101000127 +:105F70000101010101010001000101000000000018 +:105F80000000000000000001000000000000000010 +:105F900000000000020202020202020202020202E9 +:105FA00002020202020202010100000000000000E1 +:105FB00000000000000000010102020202020202D1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020002020202020202A3 +:105FE00002020202020202000000000000000000A3 +:105FF0000000000000010101010101010101010196 +:106000000101010101010101010101010101010180 +:106010000101010101010101010101010101010170 +:106020000101010101010101010101010101010160 +:10603000010101010101010102010101010101014F +:10604000010101020101010202010101010101013D +:106050000101010101010100000201020000010033 +:10606000000001010100000000010000000100002B +:10607000000001010000000000020000000000001C +:106080000000000000000002000200020202020202 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202010100000000000000E0 +:1060B00000000000000202020202020202020202CA +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020002020202020202A2 +:1060E00002020202020202000000000000000000A2 +:1060F0000000000001010101010101010101010194 +:10610000010101010101010101010101010101017F +:10611000010101010101010101010101010101016F +:10612000010101010101010101010101010101015F +:10613000010101010101010101010101010101014F +:10614000010101020101020202020101010101013A +:106150000101010102010100000101010000010033 +:10616000000001010000000000020000000100002A +:10617000000000010000000000010000000000001D +:1061800000000000000202020202020202020202F9 +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D00002020202020202020002020202020202A1 +:1061E00002020202020202000000000000000000A1 +:1061F0000000000001010101010101010101010193 +:10620000010101010101010101010101010101017E +:10621000010101010101010101010101010101016E +:10622000010101010101010101010101010101015E +:106230000101010102010102000201020202020247 +:10624000010102010202010101020101010101013A +:106250000101020202010200000001000000020030 +:10626000000001010000000000010000000100002A +:10627000000000020002020000020002020202020C +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E00002020202020202000000000000000000A0 +:1062F0000000010101010101010101010101010190 +:10630000010101010101010101010101010101017D +:10631000010101010101010101010101010101016D +:10632000010101010101010101010101010101015D +:10633000010101010200020100010201010101014C +:10634000000001010101000101010202020201013C +:106350000201010101020100000002000000010031 +:106360000000020202020202000202020202020213 +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020000010001010000019B +:1063F000010101010101010101010101010101018D +:10640000010101010101010101010101010101017C +:10641000010101010101010101010101010101016C +:106420000101010102020102010202020201020253 +:106430000202020201000100000001000000000051 +:106440000202000000020201010101010101020239 +:106450000102020201010200020202020202020221 +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020002020202029E +:1064E0000202020202020201010101010101010195 +:1064F000010101010101010101010101010101018C +:10650000010101010101010101010101010101017B +:106510000101010102020101010101010101010169 +:10652000010101010101020101010101010101015A +:106530000101010101020202020202020202020240 +:10654000020202020202020101020202020202022D +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020002020002029F +:1065E000020202020000000101010101010101019A +:1065F000010101010101010101010101010101018B +:10660000010101000101010101010101010101017B +:106610000101010101010202020202020202020260 +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D00002020202020202020200000000000000A8 +:1066E000000202020000000101010101010101019B +:1066F000010101010101010101010101010101018A +:10670000010101000202020202020202020202026E +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D00002020202020202020200000000000000A7 +:1067E000000200000000000101010101010101019E +:1067F0000101010101010102020202020202020280 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D00002020202020202020200000000000000A6 +:1068E000000000000000000101010101010101019F +:1068F000010101010101010202020202020202027F +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D00002020202020202020000000000000000A7 +:1069E000000000000000000101010101010101019E +:1069F0000101010101010101010101010101010187 +:106A00000101010101010101010101010101010176 +:106A10000101010101010101010101010101010166 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000101010101010101010101010101010136 +:106A50000101010101010101010101010101010126 +:106A60000101010101010101010101010101010116 +:106A70000101010101010101010101010101010106 +:106A800001010101010101010101010101010101F6 +:106A900001010101010101010101010101010101E6 +:106AA00001010101010101010101010101010101D6 +:106AB00001010101010101010101010101010101C6 +:106AC00001010101010101010101010101010101B6 +:106AD00001010101010101020000000000000000AD +:106AE000000000000000000101010101010101019D +:106AF0000101010101010101010101010101010186 +:106B00000101010101010101010101010101010175 +:106B10000101010101010101010101010101010165 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B70000101010101010101010101010101010105 +:106B800001010101010101010101010101010101F5 +:106B900001010101010101010101010101010101E5 +:106BA00001010101010101000000000000000000DE +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000020000000000000000B3 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE000000000000000003E000000000000000066 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE000020202020202020200000202020000028B +:106DF000000000000000000000000000020200008F +:106E0000000000000002000000000002020200007A +:106E1000000000000000000000000000000202006E +:106E2000000000000000000000000000000202005E +:106E30000002000000000000000000000000000050 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000010000000000000000000000020000CF +:106EC00000000000000000000000000000000200C0 +:106ED00000000202020000000000000000000200AA +:106EE0000202020202020202020202020202000284 +:106EF000000000000000000000000000020200028C +:106F00000000000000020000000000020202020077 +:106F1000000000000000000000000002000202006B +:106F20000000000000000000000000020202020059 +:106F3000000200000001000000000000000200004C +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000001E0 +:106FB00000010101010000000000000002020200C7 +:106FC00002010000000100000000000000020200B9 +:106FD0000202020202020202020202020202020093 +:106FE0000202020202020202020202020202000283 +:106FF000000000000000000000000000020200028B +:107000000000000000020002000000020202020074 +:10701000000000000000000000000002000202006A +:107020000000000000000000000000020202020058 +:10703000000200010001000000000000000200004A +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000001DF +:1070B00001020102010100000000000002020201C1 +:1070C00002020202010100000000000000020202B0 +:1070D0000202020202020202020202020202020092 +:1070E0000202020202020202020202020202000282 +:1070F000000000000000000000000000020200028A +:107100000000000000020002000000020202020073 +:107110000000000000000000000000020202020067 +:107120000000000000000000000000020202020057 +:107130000002000100010000000000000002000049 +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000001DE +:1071B00002020202020100000000000002020202BC +:1071C00002020202020202000000000000020202AB +:1071D0000202020202020202020202020202020091 +:1071E0000202020202020202020202020202000281 +:1071F0000000000000000000000000000202000289 +:107200000000000000020002000000020202020072 +:107210000000000000000000000000020202020066 +:107220000000000000000000000000020202020056 +:107230000002000100020000000000000002000047 +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800001000000010100000000000000000000FB +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000002DC +:1072B00002020202020200000000000002020202BA +:1072C00002020202020202000000000000020202AA +:1072D0000202020202020202020202020202020090 +:1072E0000202020202020202020202020202000280 +:1072F0000000000000000000000000000202000288 +:107300000000000000020002000000020202020071 +:107310000000000000000000000000020202020065 +:107320000000000000000000000000020202020055 +:107330000002000200020000000000000202000043 +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000021B +:10737000000000000000000000000000000000000D +:1073800001000000010100000000000000000000FA +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000002DB +:1073B00002020202020200000000000002020202B9 +:1073C00002020202020202020002020000020202A3 +:1073D000020202020202020202020202020202008F +:1073E000020202020202020202020202020200027F +:1073F0000000000000000000000000000202000287 +:107400000000000000020002000000020202020070 +:107410000000000000000000000000020202020064 +:107420000000000000000000000000020202020153 +:107430000002000200020000000000000202000042 +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000021A +:10747000000000000000000000000000000000020A +:1074800001000001020100000000000000020200F3 +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000002DA +:1074B00002020202020202000000000002020202B6 +:1074C00002020202020202020002020000020202A2 +:1074D000020202020202020202020202020202008E +:1074E000020202020202020202020202020200027E +:1074F0000000000000000000000000000202000286 +:10750000000000000002000200000002020202016E +:107510000000000000000000000000020202020063 +:107520000000000000000000000000020202020251 +:107530000002000200020000000000000202000041 +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:107560000000000000000000000000000000000219 +:107570000000000100000000000000000000000208 +:1075800002000002020200000000000000020200EF +:1075900000000000000000000000000000000000EB +:1075A00001000000000000000000000000000002D8 +:1075B00002020202020202000000000002020202B5 +:1075C000020202020202020202020202000202029D +:1075D000020202020202020202020202020202008D +:1075E000020202020202020202020202020200027D +:1075F0000000000000000000000000000202000285 +:10760000000000000002000200000002020202026C +:107610000000000000000000000000020202020062 +:107620000000000000000000000000020202020250 +:107630000002000200020000000000000202000040 +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:107660000000000000000000000000000000000218 +:107670000101000100010000000002000002000200 +:1076800002000102020200000000000000020200ED +:1076900000000000000000000000000000000000EA +:1076A00001000100000000000000000000000002D6 +:1076B00002020202020202000202020002020202AE +:1076C000020202020202020202020202000202029C +:1076D000020202020202020202020202020202008C +:1076E000020202020202020202020202020200027C +:1076F0000000000000000000000000000202000284 +:10770000000000000002000200000002020202026B +:107710000000000000000000000000020202020061 +:10772000000000000000000000000002020202024F +:10773000000200020002000000000000020200003F +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000217 +:1077700001020102000100000000020000020002FC +:1077800002000202020202000000000000020200E9 +:1077900000000000000000000000000000000000E9 +:1077A00001010100000100000000000000000002D3 +:1077B00002020202020202000202020002020202AD +:1077C000020202020202020202020202000202029B +:1077D000020202020202020202020202020202008B +:1077E0000101010101010101010101010101000289 +:1077F0000000000000000000000000020202000281 +:10780000000000000002000200000002020202026A +:107810000000000000000000000000020202020060 +:10782000000000000000000000000002020202024E +:10783000000200020002000000000000020202003C +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000010000000000000000000000000215 +:1078700002020102000200000200020000020002F7 +:1078800002000202020202000000000000020200E8 +:1078900000000000000000000000000000000002E6 +:1078A00002010101000100000000000000000002D0 +:1078B00002020202020202020202020202020202A8 +:1078C000020202020202020202020202000202029A +:1078D000020202020202020202020202020202008A +:1078E0000101010101010101010101010101000288 +:1078F0000000000000000000000000020102000281 +:107900000000000200020002000000020202020267 +:10791000000000000000000000000002020202005F +:10792000000000000000000000000002020202024D +:107930000102000200020002000000000202020038 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000010100000000000000000000000213 +:1079700002020202010200000200020000020202F2 +:1079800002000202020202000202020000020200E1 +:1079900001000000000000000000000000000002E4 +:1079A00002010201000100000000000000000002CE +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020089 +:1079E0000101010101010101010101010101000287 +:1079F000000000000000000200000002010200027E +:107A00000000000200020002000000020202020266 +:107A1000000000000000000000000002020202025C +:107A2000000000000000000000000002020202024C +:107A30000102010200020002000000000202020036 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000010100000000000000000000000212 +:107A700002020202020202000200020000020202EE +:107A800002010202020202000202020000020201DE +:107A900001000000000000000000000000000002E3 +:107AA00002020202010200000000000000000002C9 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202010089 +:107AE0000101010101010101010101010101000286 +:107AF000000000000000000200000002010100027E +:107B00000000000200020002000000020202020265 +:107B1000010000000000000000000002020202025A +:107B2000000000000000000000000002020202024B +:107B30000102010200020002000000000202020035 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000223 +:107B60000000020100000000000000000000000210 +:107B700002020202020202000200020000020202ED +:107B800002020202020202020202020000020202D9 +:107B900001010000000000000000000000000002E1 +:107BA00002020202010200000000000000000002C8 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020201010089 +:107BE0000101010101010101010101010101000285 +:107BF0000202000002020002020200020101000271 +:107C00000000000200020002000000020202020264 +:107C10000100000000000000000000020202020259 +:107C2000000000000000000000000002020202024A +:107C30000202010201020002000000000202020032 +:107C40000000000000000000000000000000000034 +:107C50000000000000000200000000000000000220 +:107C60000000020200010000000000020200000209 +:107C700002020202020202000202020200020202E8 +:107C800002020202020202020202020000020202D8 +:107C900002010001010000000000000000000002DD +:107CA00002020202020200000000000000000202C4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202020202020101010089 +:107CE0000000000000000000000000000001000192 +:107CF0000202000002020002020200020101000270 +:107D00000000000200020002000000020202020263 +:107D10000100000000000000000000020202020258 +:107D20000000000000000000000000020202020249 +:107D30000202020201020002000000000202020030 +:107D40000000000000000000000000000000000033 +:107D5000000000000000020000000200000000021D +:107D60000000020200010000000000020200000208 +:107D700002020202020202000202020200020202E7 +:107D800002020202020202020202020200020202D5 +:107D900002010001010000000000000000000002DC +:107DA00002020202020200000000000000020202C1 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202010294 +:107DD0000202020202020202020202010101010089 +:107DE0000000000000000000000000000001000191 +:107DF000020202000202000202020002010100026D +:107E00000101000200020002000000020202020260 +:107E10000200000100000000000000020202020255 +:107E20000000000000000000000000020202020248 +:107E3000020202020202000200000000020202012D +:107E40000000000000000000000000000000000032 +:107E5000000000000000020000020200000000021A +:107E60000002020200010000000000020200000205 +:107E700002020202020202000202020200020202E6 +:107E800002020202020202020202020200020202D4 +:107E900002020101020000000000000000000002D8 +:107EA00002020202020200000000000000020202C0 +:107EB00002020202020202020202020202010102A4 +:107EC0000202020202020202020202020201010294 +:107ED000020202020202020101010101010101008C +:107EE0000000000000000000000000000001000190 +:107EF000020202000202000202020001010100026D +:107F0000020101020102000200000002020202025C +:107F10000200000200000000000000020202020253 +:107F20000000000000000000000000020202020247 +:107F3000020202020202000200000000020202022B +:107F40000000000000000000000000000000000031 +:107F50000000000100000200000202000000000218 +:107F60000002020202020000000000020200000201 +:107F700002020202020202000202020200020202E5 +:107F800002020202020202020202020200020202D3 +:107F900002020102020100000000000000000002D5 +:107FA00002020202020202000000020000020202BB +:107FB00002020202020202020202020202010102A3 +:107FC0000202020202020202020202020201010293 +:107FD000020202020101010101010101010101008E +:107FE000000000000000000000000000000100018F +:107FF0000202020002020202020202010101000268 +:108000000202010202020202000000020202020257 +:108010000200000200000000000000020202020252 +:108020000000000000000000000000020202010247 +:10803000020202020202000200000000020202022A +:108040000000000000000000000000000000000030 +:108050000000000200000200000202000000000216 +:1080600000020202020200000000000202020002FE +:1080700002020202020202020202020200020202E2 +:1080800002020202020202020202020200020202D2 +:1080900002020102020100000000000000000002D4 +:1080A00002020202020202000000020000020202BA +:1080B00002020202020202020202020201010102A3 +:1080C0000202020202020202020202020201010292 +:1080D000020201010101010101010101010101008F +:1080E000000000000000000000000000000101018D +:1080F0000202020002020201020202010101000268 +:108100000202020202020202000000020201020256 +:108110000200000200000000000000020202010252 +:108120000000000000010200000000020201010244 +:10813000020202020202000200000000020102022A +:10814000000000000000000000000000000000012E +:108150000000000200000200000202000000000215 +:1081600000020202020200000000000202020002FD +:1081700002020202020202020202020200020202E1 +:1081800002020202020202020202020202020102D0 +:1081900002020202020102020000000000000002CE +:1081A00002020202020202000202020002020202B3 +:1081B00002020202020202020202020201010102A2 +:1081C0000202020202020202020202020201010291 +:1081D000020101010101010101010101010101008F +:1081E0000000000000000000000000010101010289 +:1081F0000202020202020201010102010101000267 +:108200000202020202020202000200020201010254 +:108210000200000200000000000000020201010252 +:10822000000001020102020000000002020101023E +:108230000202020202020002000000000201020229 +:10824000000000000000000000000000000000022C +:108250000000000200000200000202000000000214 +:1082600001020202020200020000000202020002F9 +:1082700002020202020202020202020200020202E0 +:1082800002020202020202020202020202010102D0 +:1082900002020202020202020000000000000002CC +:1082A00002020202020202000202020002020202B2 +:1082B00002020202020202020202020201010102A1 +:1082C0000202020202020202020202020201010290 +:1082D000020101010101010101010101010101008E +:1082E0000000000000000000000000010101010288 +:1082F0000102020202010201010101010101000269 +:108300000202020202020202000200020101010254 +:108310000200000200000000000000020201010251 +:108320000000020202020200000202010101010239 +:108330000202020202020202000000000201020226 +:10834000000000000000000000000000000000022B +:108350000000000200000200000202000000020211 +:1083600001020202020200020000000202020202F6 +:1083700002020202020202020202020200020202DF +:1083800002020202020202020202020202010102CF +:1083900002020202020202020002000200020002C5 +:1083A00002020202020202020202020202020202AD +:1083B00002020202020202020202020201010102A0 +:1083C000020202020202020202020202020101028F +:1083D000010101010101010101010101010101008E +:1083E0000000000000000000000000010101010287 +:1083F0000102020201010201010102010101000268 +:108400000202020202020202000200010101010254 +:108410000200000201000000000000010101010251 +:108420000002020202020200000202010101010236 +:108430000202020202020202000000000101020226 +:10844000000000000000000000000000000000022A +:108450000000000200000200000202000000020210 +:1084600001020202020202020002020202020202EF +:1084700002020202020202020202020202010202DD +:1084800002020202020202020202020202010102CE +:1084900002020202020202020002000200020202C2 +:1084A00002020202020202020202020202020202AC +:1084B000020202020202020202020202010101029F +:1084C0000202020202020101020101010201010293 +:1084D000010101010101010101010101010101008D +:1084E0000000000000000000000000010101010286 +:1084F000010102020101010101010101010100026A +:108500000202020202020202000200010101010253 +:10851000020000020201020000000201010101024A +:108520000202020202020200020202010101010231 +:108530000201020202020202000000000101010227 +:108540000000000000000000000000000000000229 +:10855000000001020000020000020200000002020E +:1085600002020202020202020002020202020202ED +:1085700002020202020202020202020202010102DD +:1085800002020202020202020202020202010102CD +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020202AB +:1085B000020202020202020202020202010101029E +:1085C0000202010101010101010101010101010298 +:1085D000010101010101010101010101010101008C +:1085E0000000000000000000000000010101010285 +:1085F000020101010101010101010101010100026A +:10860000020202020202020202020201010101024E +:108610000200000202020200000002010101010248 +:10862000020202020202020202020201010101022E +:108630000201020202020202000000020101010224 +:108640000000000000000000000000000200000226 +:108650000101010200000200000202000002020209 +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202010102DC +:1086800002020202020202020202020202010102CC +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020102AB +:1086B00002020201010101020101010101010102A5 +:1086C0000101010101010101010101010101010299 +:1086D000010101010101010101010101010101008B +:1086E0000000000000000001000000010101010184 +:1086F000020101010101010101010101000100026A +:10870000020202020201020102020201010101024F +:108710000200000202020200000002010101010247 +:10872000020202020202020202020201010101022D +:10873000020102020202020202020202010101021D +:108740000100000000000000000000000200020222 +:108750000101010201000200000202000002020207 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202010202010102DC +:1087800002020202020202020202020202010102CB +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202010102AB +:1087B00002010101010101010101010101010102A7 +:1087C0000101010101010101010101010101010199 +:1087D000010101010101010101010101010101008A +:1087E0000000000000000001010101010101010180 +:1087F0000201010201010101010101010001000268 +:10880000020202020201020102020201010101024E +:108810000200010202020202000002010101010243 +:10882000020202020202020202020201010101022C +:10883000020102020202020202020202010101021C +:108840000101000000000000000000000200020220 +:108850000201020201010200000202000002020203 +:1088600002020202020202020202020201020202E9 +:1088700002020202020202020102010202010102DC +:1088800002020202010201020101010202010102CF +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202010102AA +:1088B00001010101010101010101010101010102A7 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010089 +:1088E000000000000000000101010101010101017F +:1088F0000101010201010101010101010001000268 +:10890000020202020201020102020201010101024D +:10891000020002020202020202020201010101023D +:10892000020202020202020202020201010101022B +:10893000020102020201020102020202010101021D +:10894000020100000000000000000000020202021C +:108950000202020201010200000202000002020201 +:1089600002020202020202020202020101010202EA +:1089700002020202020202020102010102010102DC +:1089800002020201010101010101010102010102D2 +:1089900002020202020202020202020202020202B7 +:1089A00002020202020202020202020202010102A9 +:1089B00001010101010101010101010101010102A6 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010088 +:1089E000000000000001010101010101010101017C +:1089F0000101010101010101010101000001000269 +:108A0000020202020201020102020201010101024C +:108A1000020002020202020202020201010101023C +:108A2000020202020202020202020201010101022A +:108A3000020102020201020102020202010101021C +:108A40000201010100000000000000000202020219 +:108A500002020202020102000002020000020202FF +:108A600002020202020202020202020101010102EA +:108A700002020202020202020102010102010102DB +:108A800002020101010101010101010101010102D3 +:108A900002020202020202020202020202020202B6 +:108AA00002020202020202020202020201010102A9 +:108AB00001010101010101010101010101010102A5 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010087 +:108AE000000000000101010101010101010101017A +:108AF000010101010101010000000100000000026C +:108B0000020202020201020102020201010101024B +:108B1000020002020202020202020201010101023B +:108B20000202020202020202020202010101010229 +:108B3000020102010201020102020202010101021C +:108B40000202010100000000000000000202020217 +:108B500002020202020202000002010000020102FF +:108B600002020202020202020202020101010102E9 +:108B700002010202020101020101010102010102DE +:108B800002020101010101010101010101010102D2 +:108B900002020202020202020202020202010102B7 +:108BA00002020202020202020202020201010102A8 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010086 +:108BE0000000000001010101010101010101010179 +:108BF000010101010100010000000100000000026C +:108C0000020202020201020102020201010101024A +:108C1000020002020202020202020201010101023A +:108C20000202020202020202020202010101010228 +:108C3000020102010201020102020202010101021B +:108C40000202010101000000000000000202020215 +:108C50000202020202020100000101000002010200 +:108C600002020202020202020202020101010102E8 +:108C700002010201010101020101010102010101E0 +:108C800001020101010101010101010101010102D2 +:108C900002020202020202020202020202010102B6 +:108CA00002020202020102020202010201010102A9 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010085 +:108CE0000000000101010101010101010101010177 +:108CF0000100010100000000000000000000000170 +:108D00000202020202010201020202010101010249 +:108D10000202020202020202020202010101010237 +:108D20000202020202020202020202010101010227 +:108D3000020102010201020102020202010101021A +:108D40000202020201010000000000000202010212 +:108D50000202020202020100000101000001010200 +:108D600002020202010202010202020101010101EA +:108D700002010101010101010101010101010101E2 +:108D800001010101010101010101010101010102D2 +:108D900002020202020202010202020101010102B8 +:108DA00002020101010101020101010101010101B0 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010084 +:108DE0000000010101010101010101010101010076 +:108DF0000100000100000000000000000000000170 +:108E00000202020102010201020202010101010249 +:108E10000202020202020202020202010101010236 +:108E20000202020202020202020202010101010226 +:108E30000201020102010201020202020101010219 +:108E40000202020201010000000000000102010212 +:108E500002020202020201000001010000010102FF +:108E600002010102010202010202020101010101EB +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010102D1 +:108E900002020202020201010201020101010102B9 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010083 +:108EE0000000010101010101010101010101010075 +:108EF0000000000100000000000000000000000170 +:108F00000202020102010201020202010101010248 +:108F10000202020202020202020202010101010235 +:108F20000202020202020102020101010101010129 +:108F3000020102010101020102020201010101021A +:108F40000202020202010000000000000101010211 +:108F500002020202020201000001010000010102FE +:108F600002010101010102010201010101010101EE +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010102D0 +:108F900002020202010201010101020101010101BB +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010082 +:108FE0000001010101010101010101010101010073 +:108FF0000000000000000000000000000000000170 +:109000000202020102010101020102010101010249 +:109010000202020202020202020202010101010234 +:10902000020202020201010101010101010101012B +:10903000020101010101010102020201010101021B +:10904000020202020202000000000000010101020F +:1090500002020202020201000001010000010102FD +:1090600002010101010101010101010101010101EF +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010102CF +:1090900002020202010201010101010101010101BB +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010081 +:1090E0000001010101010101010101010101010072 +:1090F000000000000000000000000000000000016F +:10910000020202010101010102010201010101014A +:109110000202020102020202020201010101010235 +:10912000020202010101010101010101010101012C +:10913000010101010101010101010101010101021E +:10914000020202020202000000000000010101020E +:1091500002020201020201000001010000010101FE +:1091600002010101010101010101010101010101EE +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010102CE +:1091900001010201010101010101010101010101BE +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D0000101010101010101010101010101010080 +:1091E0000101010101010101010101010100000072 +:1091F000000000000000000000000000000000016E +:10920000020202010101010101010101010101014B +:109210000202020102020101020201010101010137 +:10922000020101010101010101010101010101012D +:10923000010101010101010101010101010101021D +:10924000020202020202000000000000010101020D +:1092500002020201020201000201010000010101FB +:1092600002010101010101010101010101010101ED +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101007F +:1092E0000101010101010101010101010100000071 +:1092F000000000000000000000000000000000016D +:10930000010101010101010101010101010101014D +:10931000010202010101010101010101010101013B +:10932000020101010101010101010101010101012C +:10933000010101010101010101010101010101021C +:10934000020202020202000000000000010101020C +:1093500002020201020201000201010000010101FA +:1093600002010101010101010101010101010101EC +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101007E +:1093E0000101010101010101010101000100000071 +:1093F000000000000000000000000000000000016C +:10940000010101010101010101010101010101014C +:10941000010202010101010101010101010101013A +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101021B +:109440000202020202020000000002000101010209 +:1094500002020201020201020201010200010101F5 +:1094600002010101010101010101010101010101EB +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101007D +:1094E0000101010101010101010101000100000070 +:1094F000000000000000000000000000000000016B +:10950000010101010101010101010101010101014B +:109510000102020101010101010101010101010139 +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:109540000202020202020200020002000101010204 +:1095500002020201020201020201010200010101F4 +:1095600002010101010101010101010101010101EA +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010202020202020202020202020202006E +:1095E0000101010101010101010101000000000070 +:1095F0000000000000000000000000000000010169 +:10960000010101010101010101010101010101014A +:109610000102010101010101010101010101010139 +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:109640000202020202020200020202000101010201 +:1096500002020201020201020201010202010101F1 +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202005C +:1096F0000000000000000000000000000000010168 +:109700000101010101010101010101010101010149 +:109710000102010101010101010101010101010138 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000202020202020200020202000101010101 +:1097500002020101010101020201010202010101F3 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010288 +:1097D0000201010101010101010101010101010277 +:1097E000020202020202020202020202020202005B +:1097F0000000000000000000000000000000010167 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:1098400001020202020202020202020001010101FF +:1098500001010101010101020101010101010101F7 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010287 +:1098D0000101010101010101010101010101010277 +:1098E000020202020202020202020202020202005A +:1098F0000000000000000000000000000000010166 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:1099400001010202020202020102010201010101FF +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000102020202020202020202020202020268 +:1099E0000202020202020202020202020202020059 +:1099F0000000000000000000000000000001010164 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010202010101020101010103 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020058 +:109AF0000000000000000000000000000001010163 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010102020282 +:109BD0000202020202020202020202020202020265 +:109BE0000202020202020202020202020202020057 +:109BF0000000000000000000000000000101010161 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010100000196 +:109CC0000202020202020202020202020202020274 +:109CD0000202020202020202020202020202020264 +:109CE0000202020202020202020202020202020056 +:109CF0000000000000000000000000000101010160 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010102D2 +:109D800001010101010101010101010101010001C4 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB000000000000000000000000000020202029B +:109DC0000202020202020202020202020202020273 +:109DD0000202020202020202020202020202020263 +:109DE0000202020202020202020202020202020055 +:109DF000000000000000000000000000010101015F +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000100010101010101010101010101010113 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001000101010101010001000001010101D6 +:109E800001010000000100000000000000020201CA +:109E900001010101010102020202010102010101AD +:109EA00001010101010101010101010100020100A3 +:109EB0000202020202020202020202020202020282 +:109EC0000202020202020202020202020202020272 +:109ED0000202020202020202020202020202020262 +:109EE0000202020202020202020202020202020054 +:109EF000000000000000000000000001010101015D +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000100010101010101010101010101010112 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101000101010101F2 +:109F600001000101000101000101010201010101E3 +:109F700001000101010101010001000001020200D4 +:109F800002020202020202020202020202020201B2 +:109F900001010101010101020101010002020201AE +:109FA00001010101010101010101010100010202A0 +:109FB0000202020202020202020202020202020281 +:109FC0000202020202020202020202020202020271 +:109FD0000202020202020202020202020202020261 +:109FE0000202020202020202020202020202020053 +:109FF0000000000000000001010100010101010159 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A02000010101010101010101010102010101011F +:10A030000100010101010101010101010101010111 +:10A0400001010101010101010101010102010101FF +:10A0500001010101010100010100000101020101F2 +:10A0600001000001000101000101010102020202E0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900001010202010200010000010001010102B0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020280 +:10A0C0000202020202020202020202020202020270 +:10A0D0000202020202020202020202020202020260 +:10A0E0000202020202020202020202020202020052 +:10A0F0000000000001010001010100010101010156 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A120000100010101010100010101010101000122 +:10A130000100010101010100010101010201010110 +:10A140000101010101010101010101010101000100 +:10A1500001010101010100010100000101010202F0 +:10A1600001020202020202020202020202020202D0 +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020201B0 +:10A1900002020101020100010000020201020202AA +:10A1A000020202020202020202020202020202028F +:10A1B000020202020202020202020202020202027F +:10A1C000020202020202020202020202020202026F +:10A1D000020202020202020202020202020202025F +:10A1E0000202020202020202020202020202020150 +:10A1F0000001010001010101010101010101010151 +:10A20000010101010101010101010101010201013D +:10A21000010101010101010101010102020101012C +:10A22000000000000000000000000000010000012C +:10A23000010001010101010001010100010202010F +:10A2400000010101010101010001010100020201FF +:10A2500001010102010102010102020101020202E7 +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202027E +:10A2C000020202020202020202020202020202026E +:10A2D000020202020202020202020202020202025E +:10A2E000020202020202020202020202020202014F +:10A2F0000001010001010101010101010101010150 +:10A30000010101010101010101010101010201013C +:10A31000010101010101010001010101010100012F +:10A320000000000000000000000000000202020225 +:10A3300002020202020202020202020202020202FD +:10A3400000000101010101000000000102020202FF +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202014E +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010102020101013A +:10A410000000000000000000000000000002020236 +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202027C +:10A4C000020202020202020202020202020202026C +:10A4D000020202020202020202020202020202025C +:10A4E000020202020202020202020202020202014D +:10A4F000010101010101010101010101010101014C +:10A500000101010101010101010101010101020239 +:10A51000020202020202020202020202020202021B +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E0000000020202020202020202020202020150 +:10A5F000010101010101010101010101010101024A +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E0000000000202020202020202020202020151 +:10A6F0000101010101010101010101010101010249 +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E000000000000000000202020002020200015C +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010267 +:10A8E0000000000000000000000000000000000167 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010100B8 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000000000275 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000046 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000005313 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000010000000004 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000010000000000000000E4 +:10AB700000000000000000000000010000000000D4 +:10AB800000000000000101000000000000000000C3 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000002000000000000000053 +:10AC0000000000000002000001010101000101013B +:10AC1000010001010100000100000000010000002E +:10AC20000001000000010000000000000000000022 +:10AC30000001000000010000000000000000000012 +:10AC400000000101010000000000000101000000FF +:10AC500000010000000200000000000000000200EF +:10AC600001000101010000010000000000000000DF +:10AC700001000101010000000000010001000202CA +:10AC800001000100010101000000000000000000BF +:10AC900000010000000101000000000000000000B1 +:10ACA000000100020001010000000000010000009E +:10ACB000000000000002000000000000000100028F +:10ACC0000100010101000000000000000000000080 +:10ACD000000100000001000000000000000102006F +:10ACE0000100010101000000000000000000000060 +:10ACF0000000000000000002000000000000000052 +:10AD00000000000000020000010101010101010139 +:10AD10000101010101000001010000000101010128 +:10AD2000010101010101000000000000000002001B +:10AD3000010102020101000000000000010000000A +:10AD400000010101010200000000000101000202F7 +:10AD500001010102020200010000000000000200E7 +:10AD600001010101010101010000000000000000DB +:10AD700001010101010001000000010001000101C9 +:10AD800001020101010101000000000000010000BA +:10AD900001010101010101000000000001010202A6 +:10ADA000010101010101010000000000010000009B +:10ADB0000200020202010000000000000001000287 +:10ADC0000101010101010100000000000002020276 +:10ADD000010101010101000000000000000102006A +:10ADE000010101010101010000000000000000005C +:10ADF0000000000000000002000000000000000051 +:10AE00000000000000020000010101010101010138 +:10AE10000101010101000001010000000101010127 +:10AE2000010101010101000000000000000002001A +:10AE30000101020201010000000000000100000108 +:10AE400002010101010100000000000101000101F7 +:10AE500001010102020200010000000000020100E5 +:10AE600001010101010101010000000000000200D8 +:10AE700001010101010001000000010001010101C7 +:10AE800001010101010101000000000000010000BA +:10AE900001010101010101000000000001010101A7 +:10AEA000010101010101010000000000010000009A +:10AEB0000202020202010000000000000101010282 +:10AEC0000101010101010100000000000002020275 +:10AED0000101010101010000000000000001010169 +:10AEE000010101010101010000000000000000005B +:10AEF0000000000000000002000000000000000050 +:10AF00000000000000020000010101010201010136 +:10AF10000101010101020001010000000101010124 +:10AF2000010101010101000000000000000001001A +:10AF30000101020101010000000000000100000108 +:10AF400002010101010100000000000101000101F6 +:10AF500001010102020100010000000000010100E6 +:10AF600001010101010101010000000001000100D7 +:10AF700001010101010001000000010001010101C6 +:10AF800001010101010101000000000000010000B9 +:10AF900001010101010101000000000001010101A6 +:10AFA0000101010101010100000000000100000099 +:10AFB0000202010101010000000000000101010185 +:10AFC0000101010101010100000000000002020274 +:10AFD0000101010101010001000000000001010167 +:10AFE000010101010101010000000000000000005A +:10AFF000000000000000000200000000000000004F +:10B000000000000000020000010101020201010134 +:10B010000101010101010001010000000101010124 +:10B020000101010101010100000000000000010018 +:10B030000101010101010000000000000100000108 +:10B0400001010101010100000000000101000101F6 +:10B0500001010101010100010000010000010100E6 +:10B0600001010101010101010000000001000102D4 +:10B0700001010101010001000000010001010101C5 +:10B0800001010101010101000000000000010000B8 +:10B0900001010101010101000000000001010101A5 +:10B0A0000101010101010100000000000100000098 +:10B0B0000102010101010000000000000101010185 +:10B0C0000101010101010100000000000001010176 +:10B0D0000101010101010101000000000001010165 +:10B0E0000101010101010100000000000000000059 +:10B0F000000000000000000200000000000000004E +:10B100000000000000020001010101020201010132 +:10B110000101010101010001010100010101010121 +:10B120000101010101010100000001000002010014 +:10B130000101010101010000000000000100000107 +:10B1400001010101010101000000000101010101F3 +:10B1500001010101010100010000010000010100E5 +:10B1600001010101010101010000000001000101D4 +:10B1700001010101010001000000010001010101C4 +:10B1800001010101010101000000000000010202B3 +:10B1900001010101010101000000000001010101A4 +:10B1A0000101010101010100000000000100000097 +:10B1B0000101010101010000000000000101010185 +:10B1C0000101010101010100000000000001010175 +:10B1D0000101010101010101000000000001010164 +:10B1E0000101010101010100000000000000000058 +:10B1F000000000000000000200000000000000004D +:10B20000000000000002000101010202020101022F +:10B210000101010101010001010100010101010120 +:10B220000101010101010100000001000002010013 +:10B230000101010101010100010101000100020100 +:10B2400001010101010101000000000101010101F2 +:10B2500001010101010100010000010000010101E3 +:10B2600001010101010101010000000001010101D2 +:10B2700001010101010001000000010001010101C3 +:10B2800001010101010101000000000000010101B4 +:10B2900001010101010101000000000001010101A3 +:10B2A0000101010101010100000000000100000096 +:10B2B0000101010101010000000000000101010184 +:10B2C0000101010101010100000000000001010174 +:10B2D0000101010101010101000000000001010163 +:10B2E0000101010101010100000000000000000057 +:10B2F000000000000000000200000000000000004C +:10B30000000000000002000101010202020101022E +:10B31000010101010101000101010001010101011F +:10B320000101010101010100000001000002010012 +:10B3300001010101010101000101010001000201FF +:10B3400001010101010101000100000101010101F0 +:10B3500001010101010100010000010000010101E2 +:10B3600001010101010101010000000001010101D1 +:10B3700001010101010001000000010001010101C2 +:10B3800001010101010101000000000000010101B3 +:10B3900001010101010101000000000001010101A2 +:10B3A0000101010101010100000000000100000095 +:10B3B0000101010101010000000000000101010183 +:10B3C0000101010101010100000000000001010173 +:10B3D0000101010101010101000000000001010162 +:10B3E0000101010101010100000000000000000056 +:10B3F000000000000000000200000000000000004B +:10B40000000000000002000101010202020101022D +:10B41000010101010101000101010001010101011E +:10B420000101010101010101000001000001010011 +:10B4300001010101010101000101010001000201FE +:10B4400001010101010101000100000101010101EF +:10B4500001010101010100010000010000010101E1 +:10B4600001010101010101010000000001010101D0 +:10B4700001010101010001000000010001010101C1 +:10B4800001010101010101000000000000010101B2 +:10B4900001010101010101000000000001010101A1 +:10B4A0000101010101010100000000000100000094 +:10B4B0000101010101010000000000000101010182 +:10B4C0000101010101010100000000000001010172 +:10B4D0000101010101010101000000000001010161 +:10B4E0000101010101010100000000000000000055 +:10B4F000000000000000000200000000000000004A +:10B500000000000000020002010202020201020229 +:10B51000010101010101000101010001010101011D +:10B52000010101010101010101010100000101020C +:10B5300001010101010101000101010001000101FE +:10B5400001010101010101000101000101010101ED +:10B5500001010101010100010000010000010101E0 +:10B5600001010101010101010000000001010101CF +:10B5700001010101010001000000010001010101C0 +:10B5800001010101010101000100000000010101B0 +:10B5900001010101010101000000000001010101A0 +:10B5A0000101010101010100000000000100000093 +:10B5B0000101010101010000000000000101010181 +:10B5C0000101010101010100000000000001010171 +:10B5D0000101010101010101000000000001010160 +:10B5E0000101010101010100000000000000000054 +:10B5F0000000000000000002000000000000000049 +:10B600000000000000020002020202020202020226 +:10B61000010101010101000101010001010101011C +:10B62000010101010101010101010100010101020A +:10B6300001010101010101000101010101020101FA +:10B6400001010101010101000101000101010101EC +:10B6500001010101010101010000010001010101DD +:10B6600001010101010101010000000001010101CE +:10B6700001010101010001000100010001010101BE +:10B6800001010101010101000100000000010101AF +:10B69000010101010101010000000000010101019F +:10B6A0000101010101010100000000000100000092 +:10B6B0000101010101010000000000000101010180 +:10B6C0000101010101010100000000000001010170 +:10B6D000010101010101010100000100000101015E +:10B6E0000101010101010100000000000000000053 +:10B6F0000000000000000002000000000000000048 +:10B700000000000000020002020202020202020225 +:10B71000010101010101000101010001010101011B +:10B72000010101010101010101010100010101010A +:10B7300001010101010101010101010101020101F8 +:10B7400001010101010101000101010101010101EA +:10B7500001010101010101010000010001010101DC +:10B7600001010101010101010000000001010101CD +:10B7700001010101010001000100010001010101BD +:10B7800001010101010101000101000100010101AC +:10B79000010101010101010001000000010101019D +:10B7A000010101010101010000000000010200008F +:10B7B000010101010101000000000000010101017F +:10B7C000010101010101010000000000000101016F +:10B7D000010101010101010100000100010101015C +:10B7E0000101010101010100000000000000000052 +:10B7F0000000000000000002000000000000000047 +:10B800000000000000020002020202020202020224 +:10B810000201010101010001010100010101010119 +:10B820000101010101010101010101000101010109 +:10B8300001010101010101010101010101010101F8 +:10B8400001010101010101000101010101010101E9 +:10B8500001010101010101010000010001010101DB +:10B8600001010101010101010100000001010101CB +:10B8700001010101010001000100010001010101BC +:10B8800001010101010101000101000100010101AB +:10B89000010101010101010001000000010101019C +:10B8A000010101010101010000000000010200008E +:10B8B000010101010101010000000000010101017D +:10B8C000010101010101010000000000000101016E +:10B8D000010101010101010100000100010101015B +:10B8E0000101010101010100000000000000000051 +:10B8F0000000000000000002000000000000000046 +:10B900000000000000020002020202020202020223 +:10B910000202010101010001010101010101010116 +:10B920000101010101010101010101010101010107 +:10B9300001010101010101010101010101010101F7 +:10B9400001010101010101000101010101010101E8 +:10B9500001010101010101010000010001010101DA +:10B9600001010101010101010100000001010101CA +:10B9700001010101010201000100010001010101B9 +:10B9800001010101010101000101000100010101AA +:10B99000010101010101010001000000010101019B +:10B9A000010101010101010000000000010100028C +:10B9B000010101010101010000000000010101017C +:10B9C000010101010101010000000000000101016D +:10B9D000010101010101010100000100010101015A +:10B9E0000101010101010100000000000000000050 +:10B9F0000000000000000002000000000000000045 +:10BA00000000000000020002020202020202020222 +:10BA10000202010101010001010101010101010115 +:10BA20000101010101010101010101010101010106 +:10BA300001010101010101010101010101010101F6 +:10BA400001010101010101000101010101010101E7 +:10BA500001010101010101010101010001010101D7 +:10BA600001010101010101010100000001010101C9 +:10BA700001010101010201000101010001010101B7 +:10BA800001010101010101010101000101010101A7 +:10BA9000010101010101010001000000010101019A +:10BAA000010101010101010000000000010100028B +:10BAB000010101010101010000000000010101017B +:10BAC000010101010101010000000000000101016C +:10BAD0000101010101010101000001000101010159 +:10BAE000010101010101010000000000000000004F +:10BAF0000000000000000002000000000000000044 +:10BB00000000000000020002020202020202020221 +:10BB10000202010101010001010101010101010114 +:10BB20000101010101010101010101010101010105 +:10BB300001010101010101010101010101010101F5 +:10BB400001010101010101000101010101010101E6 +:10BB500001010101010101010101010001010101D6 +:10BB600001010101010101010100000001010101C8 +:10BB700001010101010201000101010001010101B6 +:10BB800001010101010101010101010101010101A5 +:10BB90000101010101010100010100000101010198 +:10BBA0000101010101010100000000000101020189 +:10BBB000010101010101010000000000010101017A +:10BBC000010101010101010000000000000101016B +:10BBD0000101010101010101000001000101010158 +:10BBE000010101010101010000000002020000004A +:10BBF0000000000000000002000000000000000043 +:10BC00000000000000020002020202020202020220 +:10BC10000202010101010002010101010101010112 +:10BC20000101010101010101010101010101010104 +:10BC300001010101010101010101010101010101F4 +:10BC400001010101010101000101010101010101E5 +:10BC500001010101010101010101010101010101D4 +:10BC600001010101010101010101010101010101C4 +:10BC700001010101010101000101010001010101B6 +:10BC800001010101010101010101010101010101A4 +:10BC90000101010101010101010100000101010196 +:10BCA0000101010101010100000000000101020188 +:10BCB0000101010101010100010101000101010176 +:10BCC000010101010101010000000000000101016A +:10BCD0000101010101010101000001000101010157 +:10BCE0000101010101010100020000020200000047 +:10BCF0000000000000000002000000000000000042 +:10BD0000000000000002000202020202020202021F +:10BD1000020202020201000201010101010101010E +:10BD20000101010101010101010101010101010103 +:10BD300001010101010101010101010101010101F3 +:10BD400001010101010101000101010101010101E4 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101000101010001010101B5 +:10BD800001010101010101010101010101010101A3 +:10BD90000101010101010101010100010101010194 +:10BDA0000101010101010100000000000101010188 +:10BDB0000101010101010101010101000101010174 +:10BDC0000101010101010100000000000001010169 +:10BDD0000101010101010101000001000101010156 +:10BDE0000101010101010100020000020200000046 +:10BDF0000000000000000002000000000000000041 +:10BE0000000000000002000202020202020202021E +:10BE1000020202020201000201010101010101010D +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101000101010101010101B3 +:10BE800001010101010101010101010101010101A2 +:10BE90000101010101010101010100010101010193 +:10BEA0000101010101010100000000000101010187 +:10BEB0000101010101010101010101000101010173 +:10BEC0000101010101010101000000000001010167 +:10BED0000101010101010101000001000101010155 +:10BEE0000101010101010100020002020200000043 +:10BEF0000000000000000002000000000000000040 +:10BF0000000000000002000202020202020202021D +:10BF1000020202020201010201010101020101010A +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101000101010101010101B2 +:10BF800001010101010101010101010101010101A1 +:10BF90000101010101010101010100010101010192 +:10BFA0000101010101010100000001020101010183 +:10BFB0000101010101010101010101000101010172 +:10BFC0000101010101010101000100000001010165 +:10BFD0000101010101010101000001000101010154 +:10BFE0000101010101010100020002020200000042 +:10BFF000000000000000000200000000000000003F +:10C00000000000000002000202020202020202021C +:10C010000202020202010102020101010201010108 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101000101010101010101B1 +:10C0800001010101010101010101010101010101A0 +:10C090000101010101010101010100010101010191 +:10C0A0000101010101010100000001010101010183 +:10C0B0000101010101010101010101000101010171 +:10C0C0000101010101010101000100000001010164 +:10C0D0000101010101010101000101000101010152 +:10C0E0000101010101010100020002020200000041 +:10C0F000000000000000000200000000000000003E +:10C10000000000000002000202020202020202021B +:10C110000202020202010102020101010201010107 +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010101010101DF +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A0000101010101010100010001010101010181 +:10C1B0000101010101010101010101000101010170 +:10C1C0000101010101010101010101000001010161 +:10C1D0000101010101010101000101000101010151 +:10C1E0000101010101010100020002020200000040 +:10C1F000000000000000000200000000000000003D +:10C20000000000000002000202020202020202021A +:10C210000202020202020102020101010201010105 +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010102010101ED +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101020101010101010101CD +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A0000101010101010100010001010101010180 +:10C2B000010101010101010101010100010101016F +:10C2C0000101010101010101010101000001010160 +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010001010101010101013F +:10C2F0000101010101010002000000000000000036 +:10C300000000000000020002020202020202020219 +:10C310000202020202020102020201020201010102 +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010102010101EC +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101020101010101010101CC +:10C3600001010101010101020101010101010101BC +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010001000101010101017F +:10C3B000010101010101010101010100010101016E +:10C3C000010101010101010101010100000101015F +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010001010101010101013E +:10C3F0000101010101010002000000000000000035 +:10C400000000000000020002020202020202020218 +:10C4100002020202020201020202010202020202FE +:10C4200001010101010101020101010101010101FB +:10C4300001010101010101020201010102010101E9 +:10C4400001010101010101010101010101010101DC +:10C4500001010101010101020101010101010101CB +:10C4600001010101010101020101010101010101BB +:10C4700001010101010101010101010101010101AC +:10C48000010101010101010101010101010101019C +:10C49000010101010101010101010101010101018C +:10C4A000010101010101010001000101010101017E +:10C4B000010101010101010101010101010101016C +:10C4C000010101010101010101010100000101015E +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010001010101010101013D +:10C4F0000101010101010002000000000000000034 +:10C500000000000000020002020202020202020217 +:10C5100002020202020201020202010202020202FD +:10C5200001020101010101020101010101010101F9 +:10C5300001010101010101020202020102010101E6 +:10C5400001010101010101010101010201010101DA +:10C5500001010101010101020101010101010101CA +:10C5600001010101010101020101010101010101BA +:10C5700001010101010101010101020101010101AA +:10C58000010101010101010101010101010101019B +:10C59000010101010101010101010101010101018B +:10C5A000010101010101010001000101010101017D +:10C5B000010101010101010101010101010101016B +:10C5C000010101010101010101010100000101015D +:10C5D000010101010101010101010101010101014B +:10C5E000010101010101010001010101010101013C +:10C5F0000101010101010002000000000000000033 +:10C600000000000000020002020202020202020216 +:10C6100002020202020201020202010202020202FC +:10C6200002020101010101020101010101010101F7 +:10C6300001010101010101020202020102010102E4 +:10C6400001010101010101010101010202010101D8 +:10C6500001010101010101020101010101010101C9 +:10C6600001010101010101020101010101010101B9 +:10C6700001010101010101010101020102010101A8 +:10C68000010101010101010101010101010101019A +:10C69000010101010101010101010101010101018A +:10C6A000010101010101010101000101010101017B +:10C6B000010101010101010101010101010101016A +:10C6C000010101010101010101010100000101015C +:10C6D000010101010101010101010101010101014A +:10C6E000010101010101010001010101010101013B +:10C6F0000101010101010002000000000000000032 +:10C700000000000000010002020202020202020216 +:10C7100002020202020202020202010202020202FA +:10C7200002020201010101020101020101010101F4 +:10C7300001010101010101020202020202010102E2 +:10C7400001020201010101010101010202010101D5 +:10C7500001010101010101020101020101010101C7 +:10C7600001010101010101020101010101010101B8 +:10C7700001010101010101010101020102010101A7 +:10C780000101010101010101010101010101010199 +:10C790000101010101010101010101010101010189 +:10C7A0000101010101010101010101010101010179 +:10C7B0000101010101010101010101010101010169 +:10C7C000010101010101010101010100000101015B +:10C7D0000101010101010101010101010101010149 +:10C7E0000101010101010100000000000000000042 +:10C7F0000000000101010002000000000000000034 +:10C800000000000000010002020202020202020215 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020201020201020101010101EF +:10C8300001010101010101020202020202010102E1 +:10C8400001020202020101010101010202010101D2 +:10C8500001010101010101020101020101010101C6 +:10C8600001010101010101020101010101010101B7 +:10C8700001010101010101010101020102010101A6 +:10C880000101010101010101010101010101010198 +:10C890000101010101010101010101010201010187 +:10C8A0000101010101010101010101010201010177 +:10C8B0000101010101010101010101010101010168 +:10C8C0000101010101010101010101000101010159 +:10C8D0000101010101010102010101010101010147 +:10C8E0000101010101010100000000000000000041 +:10C8F0000000010101010002000000000000000032 +:10C900000000000000010002020202020202020214 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020201020202020101010101ED +:10C9300002020101010101020202020202010102DE +:10C9400001020202020101010201010202010101D0 +:10C9500001010101010101020101020101010101C5 +:10C9600001010101010101020101010102010101B5 +:10C9700001010101010101010101020102010101A5 +:10C980000101010101010102020101010102010194 +:10C990000101010101010101010101010201010186 +:10C9A0000101010101010101010101010201010176 +:10C9B0000101010101010101010101010201010166 +:10C9C0000101010101010101010101000101010158 +:10C9D0000101010101010102010101010101010146 +:10C9E0000101010101010100000000000000000040 +:10C9F000010101010101000200000000000000002F +:10CA00000000000000010002020202020202020213 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020201020202020102010201EA +:10CA300002020101010101020202020202010102DD +:10CA400002020202020101010201010202010101CE +:10CA500001010101010101020101020101010101C4 +:10CA600002010101010101020101010102010101B3 +:10CA700001010101010101010201020102020202A0 +:10CA80000201010101010102020101010102010192 +:10CA90000202010101010101010101010202010182 +:10CAA0000101010101010101010101010201010175 +:10CAB0000101010101010101010101010201010165 +:10CAC0000101010101010101010101000101010157 +:10CAD0000101010101010102010101010101010145 +:10CAE000010101010101010000000000000101013C +:10CAF000010101010101000200000000000000002E +:10CB00000000000000010002020202020202020212 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202010201E7 +:10CB300002020101020201020202020202010102DA +:10CB400002020202020201010202010202010202C9 +:10CB500002020101010101020101020102020201BE +:10CB600002020201010101020101010102010101B0 +:10CB7000010101010101010102010201020202029F +:10CB8000020102010101010202020102010201018E +:10CB9000020202010101010202010101020202027C +:10CBA0000202010101010101010101010201010172 +:10CBB0000101010101010101010101010202010163 +:10CBC0000101010101010101010101000101010156 +:10CBD0000101010101010102010101010101010144 +:10CBE000010101010101010000000000000101013B +:10CBF000010101010101000200000000000000002D +:10CC00000000000000010002020202020202020211 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202010201E6 +:10CC300002020101020201020202020202010202D8 +:10CC400002020202020202020202020202020202C4 +:10CC500002020201010101020201020102020202BA +:10CC600002020202020101020101010102010101AD +:10CC7000020101010101010102010201020202029D +:10CC80000202020102020202020201020102020287 +:10CC90000202020202020202020101010202020277 +:10CCA0000202020101010101010101010201010170 +:10CCB0000101010101010101010101010202020161 +:10CCC0000201010101010101010101000101010154 +:10CCD0000101010101010102010101010101010143 +:10CCE000010101010101010000000000000101013A +:10CCF000010101010101000100000000000000002D +:10CD00000000000000010002020202020202020210 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202010201E5 +:10CD300002020101020201020202020202020202D6 +:10CD400002020202020202020202020202020202C3 +:10CD500002020201010101020202020102020202B8 +:10CD600002020202020202020201010102010201A8 +:10CD70000202020101010102020202010202020298 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020101010202020276 +:10CDA000020202010202020101010101020101016C +:10CDB000010101010101010201010101020202015F +:10CDC0000202020101010101010101000101010151 +:10CDD0000101010101010102010101010102010141 +:10CDE0000101010101010100000000000001010139 +:10CDF000010101010101010100000000000000002B +:10CE0000000000000001000202020202020202020F +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020201E3 +:10CE300002020202020201020202020202020202D3 +:10CE400002020202020202020202020202020202C2 +:10CE500002020201010101020202020202020202B6 +:10CE600002020202020202020201010102020202A5 +:10CE70000202020202010102020202010202020295 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020201010202020274 +:10CEA000020202020202020101010101020101016A +:10CEB000010101010101010201010101020202025D +:10CEC000020202020201010101010100010101014E +:10CED000020201010101010201010101010201023D +:10CEE0000201010101010100000000000001010137 +:10CEF000010101010101010100000000000000002A +:10CF0000000000000001000202020202020202020E +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020201010101020202020202020202B5 +:10CF600002020202020202020201010102020202A4 +:10CF70000202020202010202020202020202020292 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020201020202020272 +:10CFA0000202020202020201010101010201010169 +:10CFB000010101010101010202010101020202025B +:10CFC000020202020202020201010100010101014A +:10CFD0000202020101010102010102010102020239 +:10CFE0000202020101010100000000000000000037 +:10CFF0000101010101010101000000000000000029 +:10D00000000000000001000202020202020202020D +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020201010101020202020202020202B4 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202010202020202020202020291 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020201020202020271 +:10D0A0000202020202020201010101010201010168 +:10D0B0000201020101020102020202010202020255 +:10D0C0000202020202020202010101000102020246 +:10D0D0000202020202020102010102010202020234 +:10D0E0000202020202010100000000000000000034 +:10D0F0000101010101010102000000000000000027 +:10D10000000000000001000202020202020202020C +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020201020202020202020202B0 +:10D16000020202020202020202020202020202029F +:10D170000202020202010202020202020202020290 +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A0000202020202020201010101010201010167 +:10D1B0000202020202020102020202010202020251 +:10D1C0000202020202020202010101000102020245 +:10D1D0000202020202020102010102010202020233 +:10D1E0000202020202020200000001000000000030 +:10D1F0000101010101010102000000000000000026 +:10D20000000000000001000202020202020202020B +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020201020202020202020202AF +:10D26000020202020202020202020202020202029E +:10D27000020202020201020202020202020202028F +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A0000202020202020202020102010201010163 +:10D2B0000202020202020102020202010202020250 +:10D2C0000202020202020202010101000102020244 +:10D2D0000202020202020202010102010202020231 +:10D2E000020202020202020000000100000000002F +:10D2F0000001010101010102000000000000000026 +:10D30000000000000001000202020202010202020B +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020202020202020202020202CD +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020201020202020202020202028E +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A0000202020202020202020102020202010160 +:10D3B000020202020202010202020201020202024F +:10D3C0000202020202020202020201000102020241 +:10D3D0000202020202020202010102010202020230 +:10D3E000020202020202020000000100000000002E +:10D3F0000000010101010102000000000000000026 +:10D40000000000000001000202020202020202010A +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020202DC +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020201020202020202020202028D +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202010202020201025E +:10D4B000020202020202010202020202020202024D +:10D4C000020202020202020202020200010202023F +:10D4D000020202020202020202020201020202022D +:10D4E000020202020202020001000001010000002B +:10D4F0000000000101010101000000000000000027 +:10D50000000000000001000202020201010202020A +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020202020202020202020202CB +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020201020202020202020202028C +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A000020202020202020202010202020202025C +:10D5B000020202020202020202020202020202024B +:10D5C000020202020202020202020200010202023E +:10D5D000020202020202020202020202020202022B +:10D5E000020202020202020001000001010000002A +:10D5F0000000000101010101000000000000000026 +:10D600000000000000010002020202020102020109 +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020201020202020202020202028B +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B000020202020202020202020202020202024A +:10D6C000020202020202020202020200010202023D +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020000000000010000002B +:10D6F0000000000000010101000000000000000027 +:10D70000000000000001000202020101010201010B +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D77000020202020201020202020202020202028A +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C000020202020202020202020200010202023C +:10D7D0000202020202020202020202020202020229 +:10D7E000020202020202020000000000000000002B +:10D7F0000000000000010101000000000000000026 +:10D800000000000000010002020202010101020109 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202010202020202020202020289 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C000020202020202020202020200020202023A +:10D8D0000202020202020202020202020202020228 +:10D8E000020202020202020000000000000000002A +:10D8F0000000000000000101000000000000000026 +:10D900000000000000010002020201010102010109 +:10D9100001010202020202020202020202020202E9 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202000202020239 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020200000000000000000029 +:10D9F0000000000000000101000200000000000023 +:10DA00000200000000010002020101010101010108 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202000202020238 +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020200000000000000000028 +:10DAF0000000000000000101000200000000000022 +:10DB00000200000000010001020201010101010107 +:10DB100001010202020202020202020202020202E7 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB0000202020202020202020202020202020245 +:10DBC0000202020202020202020202010202020236 +:10DBD0000202020202020202020202020202020225 +:10DBE0000202020202020200000000000000000027 +:10DBF000000000000000010102020000000200001D +:10DC00000200000202010002010101010101010103 +:10DC100001010201010201020202020202020202E9 +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB0000202020202020202020202020202020244 +:10DCC0000202020202020202020202010202020235 +:10DCD0000202020202020202020202020202020224 +:10DCE0000202020202020200000000000000000026 +:10DCF000000000000000010102020000000200001C +:10DD00000100000202010001020101010101010103 +:10DD100001010102020202020202020202020202E6 +:10DD200002020202020202020202020202020202D3 +:10DD300002020202020202020202020202020202C3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB0000202020202020202020202020202020243 +:10DDC0000202020202020202020202010202020234 +:10DDD0000202020202020202020202020202020223 +:10DDE0000202020202020200000000000000000025 +:10DDF0000000000000000101020202000002020017 +:10DE00000100000202000001010101010101010104 +:10DE100001010201010101020202020202020202E8 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA0000202020202020202020202020202020252 +:10DEB0000202020202020202020202020202020242 +:10DEC0000202020202020202020202010202020233 +:10DED0000202020202020202020202020202020222 +:10DEE0000202020202020200000000000000000024 +:10DEF0000000000000000101020202000001020017 +:10DF00000100000101000001010101010101010105 +:10DF100001010101010201020202020202020202E7 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202010202020232 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020200000000000000000023 +:10DFF0000000000000000101020102020201020211 +:10E000000200020101000001010101010101010101 +:10E0100001010101010101020202020202020202E7 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020270 +:10E090000202020202020202020202020202020260 +:10E0A0000202020202020202020202020202020250 +:10E0B0000202020202020202020202020202020240 +:10E0C0000202020202020202020202010202020231 +:10E0D0000202020202020202020202020202020220 +:10E0E0000202020202020200000000000000000022 +:10E0F0000000000000000101020102020201010211 +:10E100000200010101000001010101010101010101 +:10E1100001010101010101020202020202020202E6 +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E18000020202020202020202020202020202026F +:10E19000020202020202020202020202020202025F +:10E1A000020202020202020202020202020202024F +:10E1B000020202020202020202020202020202023F +:10E1C000020202020202020202020202020202022F +:10E1D000020202020202020202020202020202021F +:10E1E0000202020202020200000000000000000021 +:10E1F0000000000000000101020102020202010110 +:10E2000002000201010000010101010101010101FF +:10E2100001010101010101020202020202020202E5 +:10E2200002020202020202020202020202020202CE +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E28000020202020202020202020202020202026E +:10E29000020202020202020202020202020202025E +:10E2A000020202020202020202020202020202024E +:10E2B000020202020202020202020202020202023E +:10E2C000020202020202020202020202020202022E +:10E2D000020202020202020202020202020202021E +:10E2E0000202020202020200000000000000000020 +:10E2F0000000000000000001010101020202020111 +:10E300000100010101000001010101010101010100 +:10E3100001010101010101020202020202020202E4 +:10E3200002020202020202020202020202020202CD +:10E3300002020202020202020202020202020202BD +:10E3400002020202020202020202020202020202AD +:10E35000020202020202020202020202020202029D +:10E36000020202020202020202020202020202028D +:10E37000020202020202020202020202020202027D +:10E38000020202020202020202020202020202026D +:10E39000020202020202020202020202020202025D +:10E3A000020202020202020202020202020202024D +:10E3B000020202020202020202020202020202023D +:10E3C000020202020202020202020202020202022D +:10E3D000020202020202020202020202020202021D +:10E3E000020202020202020000000000000000001F +:10E3F0000000000000000001010201010102020210 +:10E4000001020101010000010101010101010101FD +:10E4100001010101010101020202020200020202E5 +:10E4200002020202020202020202020202020202CC +:10E4300002020202020202020202020201020202BD +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A000020202020202020202020202020202024C +:10E4B000020202020202020202020202020202023C +:10E4C000020202020202020202020202020202022C +:10E4D000020202020202020202020202020202021C +:10E4E000020202020202020000000000000000001E +:10E4F0000000000000000000010201010101010212 +:10E5000001010101010100010101010101010101FC +:10E5100001010101010101000202020200020202E6 +:10E5200002020202020202020202020202020202CB +:10E5300002020202020202020202020201020202BC +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A000020202020202020202020202020202024B +:10E5B000020202020202020202020202020202023B +:10E5C000020202020202020202020202020202022B +:10E5D000020202020202020202020202020202021B +:10E5E000020202020202020000010000000000001C +:10E5F0000000000000000000020202010101010110 +:10E6000001010101010100010101010101010101FB +:10E6100001010101010101000000020000000000F1 +:10E6200002000202020202020202020202020202CC +:10E6300002020202020202010201010101020202BF +:10E6400002020202020202020202020202020202AA +:10E65000020202020202020202020202020202029A +:10E66000020202020202020202020202020202028A +:10E67000020202020202020202020202020202027A +:10E68000020202020202020202020202020202026A +:10E69000020202020202020202020202020202025A +:10E6A000020202020202020202020202020202024A +:10E6B000020202020202020202020202020202023A +:10E6C000020202020202020202020202020202022A +:10E6D000020202020202020202020202020202021A +:10E6E000020202020202020000010000000000001B +:10E6F000000000000000000002020202020101010D +:10E7000001010101010100010101010101010101FA +:10E7100001010101010101000000000001000000F1 +:10E7200000000000000002020202020202020202D5 +:10E7300002020202020202010101010102020201BF +:10E7400002010101010202020202020202020202AD +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000202020202020202020202020202020229 +:10E7D0000202020202020202020202020202020219 +:10E7E0000202020202020202020202020202020209 +:10E7F00002020202020202000201020202010101FF +:10E8000001010101010100010101010101010101F9 +:10E8100001010101010101010000000001000000EF +:10E8200000000000000000020202020202020202D6 +:10E8300002020202020202020202020202010102BA +:10E8400001020202020101020202020202020202AB +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C0000202020202020202020202020202020228 +:10E8D0000202020202020202020202020202020218 +:10E8E0000202020202020202020202020202020208 +:10E8F0000202020202020200010101020201010100 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101000101010101E8 +:10E9200000010000000000010202010201020202D7 +:10E9300002020202020202020102020202020201B9 +:10E9400002010101010202020202020202020202AB +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F0000202020202020200010101010101010101 +:10EA000001010100000101010101010101010101F8 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010100020101010101020102D4 +:10EA300001010202010102010101010101010101C3 +:10EA400001010101010101020202020202020202AD +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF0000202020202020200010101010101010100 +:10EB000001010100000101010101010101010101F7 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101010202020202010201CF +:10EB300002020101020201010101010101010101C1 +:10EB400001010101010101020202020202020202AC +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202010101010101010101FE +:10EC000000010000000101010101010101010101F8 +:10EC100001010101010101010101010101010101E4 +:10EC200001010101010101010101020102020102D0 +:10EC300001010202010102010101010101010101C1 +:10EC400001010101010101020202020101020202AD +:10EC50000202020202020202020201020202020295 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020201020102020276 +:10EC8000020202020202020101010101010101016D +:10EC9000010101010101010202020202020202025B +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF0000202020202020201010101010100000000 +:10ED000000000000000101010101010101010101F8 +:10ED100001010101010101010101010101010101E3 +:10ED200001010101010101010101010101010101D3 +:10ED300001010101010101010101010101010101C3 +:10ED400001010101010101010101010101010101B3 +:10ED50000101010202020202020202020102020297 +:10ED60000202020202020202020202020202020283 +:10ED7000020202020202020101010101010101017C +:10ED80000101010201010101010101010101010172 +:10ED9000010101010101010202020202020202025A +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020203 +:10EDF0000202020202020201010001010100000000 +:10EE000000000000000101010101010101010101F7 +:10EE100001010101010101010101010101010101E2 +:10EE200001010101010101010101010101010101D2 +:10EE300001010101010101010101010101010101C2 +:10EE400001010101010101010101010101010101B2 +:10EE500001010101010101010101000102010101A2 +:10EE60000101010101010102020202020202020289 +:10EE70000202020202020202020202020202020272 +:10EE8000020202010202020101010101010101016C +:10EE90000101010101010101010101010201010161 +:10EEA0000101010201010102020202020202020248 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF0000202020202020201000000000100000002 +:10EF000000000000000101010101010101010101F6 +:10EF100001010101010101010101010101010101E1 +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101010101010101010101C1 +:10EF400001010101010101010101010101010101B1 +:10EF5000010101010101010102020002000202029D +:10EF60000202020202020202020202020002020283 +:10EF7000020202020202020000000200020000007F +:10EF8000000000020000000202020202020202026D +:10EF90000202020202020202020202020202020251 +:10EFA0000202020102020202020202020202020242 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020202020202020221 +:10EFD0000202020202020202020202020202020211 +:10EFE0000202020202020202020202020202020201 +:10EFF0000202020202020201000000000000000002 +:10F0000000000000000101010101010101010101F5 +:10F0100001010101010101010101010101010101E0 +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101010101010101010101C0 +:10F0400001010101010101010101010101010101B0 +:10F0500001010101010101010101010101010101A0 +:10F06000010101010101010102020202000202028A +:10F070000202020202020201010101010101010179 +:10F080000101010101010102020202020202020267 +:10F090000202020202020200000000000000000062 +:10F0A000000000020000000202020202010202024D +:10F0B0000202020202020202020202020202020230 +:10F0C0000202020202020202020202020202020220 +:10F0D0000202020202020202020202020202020210 +:10F0E0000202020202020202020202020202020200 +:10F0F0000202020202020201000000000000000001 +:10F1000000000000000101010101010101010101F4 +:10F1100001010101010101010101010101010101DF +:10F1200001010101010101010101010101010101CF +:10F1300001010101010101010101010101010101BF +:10F1400001010101010101010101010101010101AF +:10F15000010101010101010101010101010101019F +:10F16000010101010101010101010101010101018F +:10F17000010101010102010101010101010101017E +:10F180000101010101010102020202020202020266 +:10F190000202020202020200000000000000000061 +:10F1A000000000000000000202020202010202024E +:10F1B0000202020202020202020202020002020231 +:10F1C000020202020202020202020202020202021F +:10F1D000020202020202020202020202020202020F +:10F1E00002020202020202020202020202020202FF +:10F1F0000202020202020201000000000000000000 +:10F2000000000001010101010101010101010101F1 +:10F2100001010101010101010101010101010101DE +:10F2200001010101010101010101010101010101CE +:10F2300001010101010101010101010101010101BE +:10F2400001010101010101010101010101010101AE +:10F25000010101010101010101010101010101019E +:10F26000010101010101010101010101010101018E +:10F27000010101010101010101010101010101017E +:10F28000010101010101010101010101010101016E +:10F290000101010101010100000000000100000066 +:10F2A0000000000000000001010101010201010154 +:10F2B0000101010101010100000000000000000047 +:10F2C000000000000000000202020202020202022C +:10F2D000020202020202020202020202020202020E +:10F2E00002020202020202020202020202020202FE +:10F2F00002020202020202010000000000000000FF +:10F3000000000001010101010101010101010101F0 +:10F3100001010101010101010101010101010101DD +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010101010101010101019D +:10F36000010101010101010101010101010101018D +:10F37000010101010101010101010101010101017D +:10F38000010101010101010101010101010101016D +:10F39000010101010101010101010101010101015D +:10F3A0000101010101010102020202020202020244 +:10F3B000020202020202020000000000000000003F +:10F3C000000000000000000202020202020202022B +:10F3D000020202020202020202020202020202020D +:10F3E00002020202020202020202020202020202FD +:10F3F00002020202020202010000000000000000FE +:10F4000001010101010101010101010101010101EC +:10F4100001010101010101010101010101010101DC +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F46000010101010101010101010101010101018C +:10F47000010101010101010101010101010101017C +:10F48000010101010101010101010101010101016C +:10F49000010101010101010101010101010101015C +:10F4A000010101010101010101010101010101014C +:10F4B0000101010101010100000000000000000045 +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000202020202020202021A +:10F4E0000202020202020202020202000002020200 +:10F4F00002020202020202010000000000010101FA +:10F5000001010101010101010101010101010101EB +:10F5100001010101010101010101010101010101DB +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101010101010101010101AB +:10F55000010101010101010101010101010101019B +:10F56000010101010101010101010101010101018B +:10F57000010101010101010101010101010101017B +:10F58000010101010101010101010101010101016B +:10F59000010101010101010101010101010101015B +:10F5A000010101010101010101010101010101014B +:10F5B000010101010101010101010101010101013B +:10F5C0000101010101010100000000000000000034 +:10F5D0000000000000000001010101010101010122 +:10F5E0000101010101010102020202000002020206 +:10F5F00002020202020202010001000000010101F8 +:10F6000001010101010101010101010101010101EA +:10F6100001010101010101010101010101010101DA +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101010101010101010101AA +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010101010101010101017A +:10F68000010101010101010101010101010101016A +:10F69000010101010101010101010101010101015A +:10F6A000010101010101010101010101010101014A +:10F6B000010101010101010101010101010101013A +:10F6C000010101010101010101010101010101012A +:10F6D0000101010101010102020202020202020211 +:10F6E00002020202020202020202020000020202FE +:10F6F00002020202020202010101010101010101F3 +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010101010101010101010139 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010102000202000002020206 +:10F7F00002020202020202010101010101010101F2 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E000010101010101010200020000000000000D +:10F8F00002020202020202010101010101010101F1 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E000010101010101010200020000000000000C +:10F9F00002020202020202010101010101010101F0 +:10FA000001010101010101000000000000000000EF +:10FA100000000000000000000000000000000000E6 +:10FA200000000000000000020202020202020202C4 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE0000202020202020202000200000000000004 +:10FAF00000000202020202010101010101010101F3 +:10FB000001010101010101000000000000000000EE +:10FB100000000000000000000000000000000000E5 +:10FB200000000000000000000000000000000000D5 +:10FB300000000000000000020202020202020202B3 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE0000202020202020200000000000000000007 +:10FBF00000000002020202010101010101010101F4 +:10FC000001010101010101000000000000000000ED +:10FC100000000000000000000000000000000000E4 +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000002020202020202020272 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE0000202020202020200000000000000000006 +:10FCF0000000000000020000000000000000000002 +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF00000000000000000530000000000000000B0 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000002000000000000000000E0 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000010000000000000071 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000200 +:10FF000000000000000000000000000202010000EC +:10FF100001010000000002000000010101000000DA +:10FF200000000000000000000000000101000000CF +:10FF300000000000000200000101000000010000BC +:10FF400000000000000000020000020000000000AD +:10FF5000000000000000000000000101010000019D +:10FF6000000000000000000000000000000200008F +:10FF70000000000000000000000000000000000081 +:10FF8000000000000000000101000100000000006E +:10FF9000000000000000000100000100010000005E +:10FFA000000000000000000100000101010000004D +:10FFB000000000000000020002000000000100003C +:10FFC000000000000000000100000101010000002D +:10FFD000000000000000000100000101010000001D +:10FFE000000000000100000000000102000000000D +:10FFF00000000000000000000000000000000002FF +:02000002D0002C +:1000000000000000000000000000000202020001E9 +:1000100001010001010002000201010101010000D3 +:1000200000000000000202000102000101020000C5 +:1000300000000000000200020101010101010000B6 +:1000400000000000000102020202010000010001A4 +:100050000000000101020100010101010101000194 +:100060000000000000000000000002020202000088 +:100070000000000000000000000000000000000080 +:100080000000000000020101010101000000010068 +:100090000000000000020101010101020100010055 +:1000A0000000000100010101010101010101010045 +:1000B0000000000000000201020001010101000037 +:1000C0000000000000010101010101010101010026 +:1000D0000000000000010101010101010101010016 +:1000E0000000000001000000020201020001000007 +:1000F00000000000000000000000000000000002FE +:1001000000000000000000000000000202020001E8 +:1001100001010001010001000201010101010000D3 +:1001200000000000000202020102010101010000C2 +:1001300000000000000101010101010101010100B5 +:1001400000000000000102020201010101010001A2 +:100150000001000101020101010101010101000191 +:100160000000000000000200020202020202000081 +:10017000000000000000000000000000000000007F +:100180000000000000010101010101000000010068 +:100190000000000000010101010101010102010054 +:1001A0000000000100010101010101010101010044 +:1001B0000000000000020201020101010101000033 +:1001C0000000000000010101010101010101010025 +:1001D0000000000000010101010101010101010015 +:1001E0000000000001000000020201020001000006 +:1001F00000000000000000000000000000000002FD +:1002000000000000000000000000000202020001E7 +:1002100001010001010001000201010101010000D2 +:1002200000000000000102020102010101010000C2 +:1002300000000000000101010101010101010100B4 +:1002400000000000000102010101010101010001A3 +:100250000001000101010101010101010101010190 +:100260000000000000000202020202010201000080 +:10027000000000000000000000000000000000007E +:100280000000000000010101010101000000010067 +:100290000000000000010101010101010101010054 +:1002A0000000000100010101010101010101010043 +:1002B0000000000000020101010101010101000034 +:1002C0000000000000010101010101010101010024 +:1002D0000000000000010101010101010101010014 +:1002E0000000000001000000020201010001000006 +:1002F00000000000000000000000000000000002FC +:1003000000000000000000000000000202020001E6 +:1003100001010001010001020101010101010000D0 +:1003200000000000000101020101010101010000C3 +:1003300000000001000101010101010101010100B2 +:1003400000000100000101010101010101010001A2 +:10035000010101010101010101010101010101018D +:100360000000000100000202020201010101000080 +:100370000000000000000000000200000002000079 +:100380000000000000010101010101000000010066 +:100390000000000000010101010101010101010053 +:1003A0000000000100010101010101010101010042 +:1003B0000000000000020101010101010101000033 +:1003C0000000000000010101010101010101010023 +:1003D0000000000000010101010101010101010013 +:1003E0000000000001000002010101010201000003 +:1003F00000000000000000000000000000000002FB +:1004000000000000000000000000000202020001E5 +:1004100001010001010201020101010101010100CC +:1004200000000000000101010101010101010000C3 +:1004300000000001000101010101010101010100B1 +:10044000000001000101010101010101010101019F +:10045000010101010101010101010101010101018C +:100460000000000100000102010101010101000082 +:100470000000000000000000000202020202000072 +:100480000000000000010101010101000000010065 +:100490000000000000010101010101010101010052 +:1004A0000000000100010101010101010101010041 +:1004B0000000000000010101010101010101000033 +:1004C0000000000000010101010101010101010022 +:1004D0000000000000010101010101010101010012 +:1004E0000000000001020002010101010101000001 +:1004F00000000000000000000000000000000002FA +:1005000000000000000000000000000202020001E4 +:1005100001010101010201020101010101010100CA +:1005200000000100000101010101010101010000C1 +:1005300000000001000101010101010101010100B0 +:10054000000001000101010101010101010101019E +:10055000010101010101010101010101010101018B +:100560000000000100020101010101010101000080 +:10057000000000000000000002020202020200006F +:100580000000000000010101010101000000010064 +:100590000000000000010101010101010101010051 +:1005A0000000000100010101010101010101010040 +:1005B0000000000000010101010101010101010031 +:1005C0000000000000010101010101010101010021 +:1005D0000000000000010101010101010101010011 +:1005E0000000000001020001010101010101000001 +:1005F00000000000000000000000000000000002F9 +:1006000000000000000000000000000202020001E3 +:1006100001010101010201010101010101010100CA +:1006200000000100000101010101010101010100BF +:1006300000000001000101010101010101010100AF +:10064000000001000101010101010101010101019D +:10065000010101010101010101010101010101018A +:10066000000000010002010101010101010100007F +:100670000000000000000000020102020201000070 +:100680000001000000010101010101000000010062 +:10069000000000010101010101010101010101004E +:1006A000000000010001010101010101010101003F +:1006B0000000000000010101010101010101010030 +:1006C000000000010001010101010101010101001F +:1006D0000000000000010101010101010101010010 +:1006E0000000000001010001010101010101000001 +:1006F00000000000000000000000000000000002F8 +:1007000000000000000000000000000202020001E2 +:1007100001010101010101010101010101010100CA +:1007200000010100000101010101010101010101BC +:1007300000000001000101010101010101010100AE +:10074000000001000101010101010101010101019C +:100750000101010101010101010101010101010189 +:10076000000000010002010101010101010100007E +:100770000000000000000200020101010101000070 +:100780000001000000010101010101000000010061 +:10079000000000010101010101010101010101004D +:1007A000000100010001010101010101010101003D +:1007B000000000000001010101010101010101002F +:1007C000000000010001010101010101010101001E +:1007D000000000000001010101010101010101000F +:1007E0000000000001010001010101010101000000 +:1007F00000000000000000000000000000000002F7 +:1008000000000000000000000000000202020001E1 +:1008100001010101010101010101010101010100C9 +:1008200000010100000101010101010101010101BB +:1008300000000001000101010101010101010100AD +:10084000000001000101010101010101010101019B +:100850000101010101010101010101010101010188 +:10086000000000010001010101010101010100007E +:10087000000000000000020201010101010100006E +:100880000001000000010101010101000000010060 +:10089000000000010101010101010101010101004C +:1008A000000100010001010101010101010101003C +:1008B000000000000001010101010101010101002E +:1008C000000000010001010101010101010101001D +:1008D000000000000001010101010101010101000E +:1008E00000000000010100010101010101010000FF +:1008F00000000000000000000000000000000002F6 +:1009000000000000000000000000000202020001E0 +:1009100001010101010101010101010101010100C8 +:1009200000010100000101010101010101010101BA +:1009300000000001000101010101010101010100AC +:10094000000001000101010101010101010101019A +:100950000101010101010101010101010101010187 +:10096000000000010001010101010101010100007D +:10097000000000000000020201010101010100006D +:10098000000100000001010101010100000001005F +:10099000000000010101010101010101010101004B +:1009A000000100010001010101010101010101003B +:1009B000000000000001010101010101010101002D +:1009C000000000010001010101010101010101001C +:1009D000000000000001010101010101010101000D +:1009E00000000000010100010101010101010000FE +:1009F00000000000000000000000000000000002F5 +:100A000000000000000000000000000202020002DE +:100A100001010101010101010101010101010100C7 +:100A200000010101000101010101010101010101B8 +:100A300000010001000101010101010101010100AA +:100A40000000010101010101010101010101010198 +:100A50000101010101010101010101010101010186 +:100A6000000000010001010101010101010100007C +:100A7000000000000000010201010101010100006D +:100A8000000100010001010101010100000001005D +:100A9000000000010101010101010101010101004A +:100AA000000100010001010101010101010101003A +:100AB000000000000001010101010101010101002C +:100AC000000000010001010101010101010101001B +:100AD000000000000101010101010101010101000B +:100AE00000000000010102010101010101010000FB +:100AF00000000000000000000000000000000002F4 +:100B000000000000000000000000000202020002DD +:100B100001010101010101010101010101010100C6 +:100B200000010101000101010101010101010101B7 +:100B300000010001010101010101010101010100A8 +:100B40000000010101010101010101010101010197 +:100B50000101010101010101010101010101010185 +:100B6000000000010001010101010101010101007A +:100B7000000000000000010101010101010100006D +:100B8000000100010001010101010100000001005C +:100B90000000000101010101010101010101010049 +:100BA0000101010100010101010101010101010037 +:100BB000000000000001010101010101010101002B +:100BC0000000010100010101010101010101010019 +:100BD000000000000101010101010101010101000A +:100BE00000000000010102010101010101010000FA +:100BF00000000000000000000000000000000002F3 +:100C000000000000000000000000000202020002DC +:100C100002010101010101010101010101010101C3 +:100C200000010101000101010101010101010101B6 +:100C300001010001010101010101010101010100A6 +:100C40000000010101010101010101010101010196 +:100C50000101010101010101010101010101010184 +:100C60000000010100010101010101010101010078 +:100C7000000000000000010101010101010100006C +:100C8000000100010101010101010100000001005A +:100C90000000000101010101010101010101010048 +:100CA0000101010101010101010101010101010035 +:100CB000000000000001010101010101010101002A +:100CC0000000010101010101010101010101010017 +:100CD0000000000001010101010101010101010009 +:100CE00000000000010101010101010101010000FA +:100CF00000000000000000000000000000000002F2 +:100D000000000000000000000000000202020002DB +:100D100002020101010101010101010101010101C1 +:100D200000010101000101010101010101010101B5 +:100D300001010001010101010101010101010100A5 +:100D40000000010101010101010101010101010195 +:100D50000101010101010101010101010101010183 +:100D60000000010100010101010101010101010077 +:100D70000000000000020101010101010101000069 +:100D80000001010101010101010101020000010056 +:100D90000000010101010101010101010101010046 +:100DA0000101010101010101010101010101010034 +:100DB0000000000000010101010101010101010029 +:100DC0000000010101010101010101010101010016 +:100DD0000000000001010101010101010101010008 +:100DE00000000000010101010101010101010000F9 +:100DF00000000000020000000000000000000002EF +:100E000000000000000000000000000202020002DA +:100E100002020102020101010101010101010101BE +:100E200000010101010101010101010101010101B3 +:100E300001010001010101010101010101010100A4 +:100E40000000010101010101010101010101010194 +:100E50000101010101010101010101010101010182 +:100E60000001010100010101010101010101010075 +:100E70000000000000020101010101010101000068 +:100E80000001010101010101010101020000010055 +:100E90000000010101010101010101010101010045 +:100EA0000101010101010101010101010101010033 +:100EB0000000000000010101010101010101010028 +:100EC0000000010101010101010101010101010015 +:100ED0000000000101010101010101010101010006 +:100EE00000000000010101010101010101010000F8 +:100EF00000020202020000000000000000000002E8 +:100F000000000000000000000000000202020002D9 +:100F100002020102020101010101010101010101BD +:100F200001010101010101010101010101010101B1 +:100F300001010001010101010101010101010100A3 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000001010100010101010101010101010074 +:100F70000000000000020101010101010101000067 +:100F80000001010101010101010101020200010052 +:100F90000000010101010101010101010101010044 +:100FA0000101010101010101010101010101010032 +:100FB0000000000000010101010101010101010027 +:100FC0000100010101010101010101010101010013 +:100FD0000000010101010101010101010101010004 +:100FE00000000000010101010101010101010000F7 +:100FF00000020202020000000000000000000002E7 +:1010000000000000000000000000000202020002D8 +:1010100002020102020101010101010101010101BC +:1010200001010101010101010101010101010101B0 +:1010300001010001010101010101010101010101A1 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000001010100010101010101010101010073 +:101070000000000000010101010101010101000067 +:101080000001010101010101010101010200010052 +:101090000000010101010101010101010101010142 +:1010A0000101010101010101010101010101010031 +:1010B0000000000000010101010101010101010125 +:1010C0000100010101010101010101010101010012 +:1010D0000000010101010101010101010101010003 +:1010E00000000000010101010101010101010100F5 +:1010F00000020202020000000000000000000002E6 +:1011000000000000000000000000000202020002D7 +:1011100002020202020101010101010101010101BA +:1011200001010101010101010101010101010101AF +:1011300001010001010101010101010101010101A0 +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:101160000001010101010101010101010101010071 +:101170000000000001010101010101010101010064 +:101180000101010101010101010101010200010050 +:101190000100010101010101010101010101010140 +:1011A0000101010101010101010101010101010030 +:1011B0000000000100010101010101010101010123 +:1011C0000101010101010101010101010101010010 +:1011D0000000010101010101010101010101010002 +:1011E00000000000010101010101010101010100F4 +:1011F00000020202020000000000000000000002E5 +:1012000000000000000000000000000202020002D6 +:1012100002020202020101010101010101010101B9 +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:101260000001010101010101010101010101010070 +:101270000000010001010101010101010101010062 +:101280000101010101010101010101010100010050 +:10129000010001010101010101010101010101013F +:1012A000010101010101010101010101010101002F +:1012B0000001000100010101010101010101010121 +:1012C000010101010101010101010101010101000F +:1012D0000000010101010101010101010101010001 +:1012E00000000000010101010101010101010100F3 +:1012F00001010101010101010101010101010002DE +:1013000000000000000000000000000202020002D5 +:1013100002020202020101010102020101010101B6 +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101028C +:10135000010101010101010101010101010101017D +:10136000000101010101010101010101010101016E +:101370000000010001010101010101010101010061 +:10138000010101010101010101010101010001004F +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101002E +:1013B0000001000100010101010101010101010120 +:1013C000010101010101010101010101010101000E +:1013D00000010101010101010101010101010100FF +:1013E00000000000010101010101010101010100F2 +:1013F00001010101010101010101010101010002DD +:1014000000000000000000000000000202020002D4 +:1014100002020202020101010102020202010101B3 +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101028B +:10145000010101010101010101010101010101027B +:10146000000101010101010101010101010101016D +:101470000000010001010101010101010101010060 +:10148000010101010101010101010101010201004C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101002D +:1014B000000100010001010101010101010101011F +:1014C000010101010101010101010101010101000D +:1014D00000010101010101010101010101010100FE +:1014E00000000000010101010101010101010100F1 +:1014F00001010101010101010101010101010002DC +:1015000000000000000000000000000202020002D3 +:1015100002020202020102010102020202010101B1 +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101028A +:10155000010101010101010101010101010101027A +:10156000000101010101010101010101010101016C +:10157000000001010101010101010101010101005E +:10158000010101010101010101010101010101004C +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101002C +:1015B000000100010001010101010101010101011E +:1015C000010101010101010101010101010101000C +:1015D00001010101010101010101010101010100FC +:1015E00000000000010101010101010101010100F0 +:1015F00001010101010101010101010101010002DB +:1016000000000000000000000000000202020002D2 +:1016100002020202020102010102020202020101AF +:1016200001010101010101010101010101010102A9 +:10163000010101010101010101010101010101019A +:101640000101010101010101010101010101010289 +:101650000101010101010101010101010101010279 +:10166000000101010101010101010101010101016B +:10167000000001010101010101010101010101005D +:10168000010101010101010101010101010101004B +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101002B +:1016B000010101010001010101010101010101011B +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010100FB +:1016E00000000000010101010101010101010100EF +:1016F00001010101010101010101010101010002DA +:1017000000000000000000000000000202020002D1 +:1017100002020202020202010202020202020101AC +:1017200001010101010101010101010101010102A8 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010288 +:101750000101010101010101010101010101010278 +:10176000000101010101010101010101010101016A +:10177000000001010101010101010101010101005C +:10178000010101010101010101010101010101004A +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B000010101010001010101010101010101011A +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010100FA +:1017E00000000000010101010101010101010100EE +:1017F00000000000000000000000010101010102E2 +:1018000000000000000000000000000202020002D0 +:1018100002020202020202020202020202020202A8 +:1018200001010101010101010101010101010102A7 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010287 +:101850000202010202010101010101010101010273 +:101860000101010101010101010101010101010168 +:10187000000001010101010101010101010101005B +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010100010101010101010101010119 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00000000000010101010101010101010100ED +:1018F00000000000000000010001010101010102DF +:1019000000000000000000000000000202020002CF +:1019100002020202020202020202020202020202A7 +:1019200001010201010101010101010101010102A5 +:101930000101010201010101010101010101010196 +:101940000101010101010101010101010101010286 +:101950000202020202010101010101010101010271 +:101960000101010101010101010101010101010167 +:10197000000001010101010101010101010101005A +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010201010101010101010101010126 +:1019B0000101010100010101010101010101010118 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00000000000010101010101010101010100EC +:1019F00000000000000000010001010101010102DE +:101A000000000000000000000000000202020002CE +:101A100002020202020202020202020202020202A6 +:101A200001020201010101010101010101010102A3 +:101A30000101010201010101010101010101010195 +:101A40000101010101010101010101010101010285 +:101A50000202020202010101010101010101010270 +:101A60000101010101010101010101010101010166 +:101A70000000010101010101010101010101010158 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010201010101010101010101010125 +:101AB0000101010100010101010101010101010117 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00000000000010101010101010101010100EB +:101AF00000000000000100010001010101010102DC +:101B000000000000000000000000000102020002CE +:101B100002020202020202020202020202020202A5 +:101B200001020201010201010201010101010102A0 +:101B30000101010201010101010101010101010194 +:101B40000101020101010101010101010101010283 +:101B5000020202020201010101010101010101026F +:101B60000101010201010101010101010101010164 +:101B70000000010101010101010101010101010157 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010201020101010101010101010123 +:101BB0000101010100010101010101010101010116 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00000000000010101010101010101010100EA +:101BF00000000000000100010001010101010102DB +:101C000000000000000000000000000101020002CE +:101C100002020202020202020202020202020202A4 +:101C2000010202020102010102010202020101029B +:101C3000010101020102020102020101010101018F +:101C40000101020102020101010101010101010280 +:101C5000020202020201020101010101010101026D +:101C60000101010201010101010101010101010163 +:101C70000100010101010101010101010101010155 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA000010201020102020201010101010101011F +:101CB0000101010100010101010101010101010115 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00000000000010101010101010101010100E9 +:101CF00000010000000100010001010101010102D9 +:101D000000000000000000000000000101020002CD +:101D100002020202020202020202020202020202A3 +:101D2000010202020102010102010202020101029A +:101D3000020201020102020202020201010101018A +:101D4000010102010202010101010101010101027F +:101D50000202020202020202020202010101010267 +:101D60000101010201010101010101010101010162 +:101D70000100010101010101010101010101010154 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010232 +:101DA000020201020102020202020201010101011A +:101DB0000101010100010101010101010101010114 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00000000100010101010101010101010100E7 +:101DF00000010000000100010001010101010102D8 +:101E000000000000000000000000000101010002CD +:101E100002020202020202020202020202020202A2 +:101E20000202020202020201020102020201010296 +:101E30000202010202020202020202020202010284 +:101E4000010102010202010101010101010101027E +:101E50000202020202020202020202020201010264 +:101E60000101010201010101010101010101010161 +:101E70000101010101010101010101010101010152 +:101E80000102010101010101010101010101010141 +:101E90000101010101010101010101010101010231 +:101EA0000202020201020202020202020201010116 +:101EB0000101010100010101010101010101010113 +:101EC0000101010101020101010101010101010101 +:101ED00001010101010101010101010101010101F2 +:101EE00000000100020101010101010101010100E5 +:101EF00000010000000100010001010101010102D7 +:101F000000000000000000000000000101010002CC +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202010292 +:101F30000202010202020202020202020202020282 +:101F4000010102020202010101010101010101027C +:101F50000202020202020202020202020202010262 +:101F6000010102020101010101010101010101015F +:101F70000101010101010101010101010101010151 +:101F8000010201010102020202010101010101013C +:101F9000010101020202020201010101010101022B +:101FA0000202020202020202020202020202020112 +:101FB0000101010100010101010101010101010112 +:101FC00001010102010202020101010101010101FD +:101FD00001010101010101010101010101010101F1 +:101FE00000000100020101010101010101010100E4 +:101FF00000010000000100010001010101010101D7 +:1020000000000000000000000000000101010002CB +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202010291 +:102030000202010202020202020202020202020281 +:102040000101020202020101010202010101010279 +:102050000202020202020202020202020202020260 +:10206000010202020101010101010101010101025C +:102070000101010101010101010101010101010150 +:102080000102010101020202020202010101010139 +:102090000101010202020202020202010101010227 +:1020A0000202020202020202020202020202020111 +:1020B000010101010001010201010101010101020F +:1020C00001010102010202020202020101010101F9 +:1020D00001010101010201010101010101010101EF +:1020E00000000100020101010101010101010100E3 +:1020F00000010101000100010001010101010101D4 +:1021000000000000000000000000000101010002CA +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:102140000201020202020202020202020202010271 +:10215000020202020202020202020202020202025F +:10216000010202020101020101010101010101025A +:10217000010101010101010101010101010101014F +:102180000102010201020202020202010101010137 +:102190000101010202020202020202010201010225 +:1021A0000202020202020202020202020202020110 +:1021B000010101010101010201020201010101020B +:1021C00001010202010202020202020202010101F5 +:1021D00001010101010202020101010101010101EC +:1021E00000000100020101010101010101010100E2 +:1021F00000010101010000010001010101010101D3 +:1022000000000000000000000000000101010002C9 +:10221000020202020202020202020202020202029E +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020201026F +:10225000020202020202020202020202020202025E +:102260000102020202020202020202020101010252 +:10227000010101010101010101010101010101014E +:102280000102020202020202020202010101020133 +:102290000101020202020202020202010201020222 +:1022A000020202020202020202020202020202010F +:1022B0000101010101020202010202020202010205 +:1022C00002010202020202020202020202020201F0 +:1022D00001010101010202020202020101010101E8 +:1022E00000000100020101010101010101010100E1 +:1022F00000010101010000010001010101010101D2 +:1023000000000000000000000000000101010002C8 +:10231000020202020202020202020202020202029D +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000010202020202020202020202020201024F +:10237000010102010201010101010101010101014B +:102380000202020202020202020202010101020131 +:10239000020102020202020202020202020102021F +:1023A000020202020202020202020202020202010E +:1023B0000101010101020202020202020202010203 +:1023C00002010202020202020202020202020201EF +:1023D00001010101020202020202020202010101E4 +:1023E00001010100020101010101020101010100DD +:1023F00000000101010000000001010101010102D2 +:1024000000000000000000000000000101010002C7 +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000010202020202020202020202020201024E +:102470000101020102010101010201010101010149 +:10248000020202020202020202020201010102022F +:10249000020102020202020202020202020202021D +:1024A000020202020202020202020202020202020C +:1024B0000101010101020202020202020202010202 +:1024C00002020202020202020202020202020201ED +:1024D00001010101020202020202020202020201E1 +:1024E00001010100020101010101020101010100DC +:1024F00000000000010000000001010101010102D3 +:1025000000000000000000000000000101010002C6 +:10251000020202020202020202020202020202029B +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020201024C +:102570000101020202010201020202010101010243 +:10258000020202020202020202020201010102022E +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00001020102010202020202020202020202FE +:1025C00002020202020202020202020202020202EB +:1025D00001010202020202020202020202020201DE +:1025E00001010100020201010101020101020100D9 +:1025F00000000000010000000001010101010102D2 +:1026000000000000000000000000000101010002C5 +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000010102020201020202020202020201023E +:10268000020202020202020202020201010102022D +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020102010202020202020202020202FC +:1026C00002020202020202020202020202020202EA +:1026D00001010202020202020202020202020201DD +:1026E00001010101020201020202020101020100D4 +:1026F00000000000000000000001010101010102D2 +:1027000000000000000000000000000101010002C4 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:10277000010102020202020202020202020201023C +:10278000020202020202020202020201010102022C +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202010202020202020202020202FA +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00001010101020201020202020202020100D1 +:1027F00000000000000000000000000100010101D5 +:1028000000000000000000000000000101010002C3 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:10287000020102020202020202020202020201023A +:10288000020202020202020202020201010102022B +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202010202020202020202020202F9 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00001010101020201020202020202020100D0 +:1028F00000000000000000000000000000010101D5 +:1029000000000000000000000000020101010002C0 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000201020202020202020202020202010239 +:10298000020202020202020202020201010102022A +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202010202020202020202020202F8 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00001010101020202020202020202020100CE +:1029F00000000000000000000000000000010101D4 +:102A000000000000000000000000020101010002BF +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202010101020229 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202010202020202020202020202F7 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00001010101020202020202020202020100CD +:102AF00000000000000000000000000000010101D3 +:102B000000000000000000000002020101010002BC +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202010101020228 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202010202020202020202020202F6 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00001010101020202020202020202020100CC +:102BF00000000000000000000100000000010101D1 +:102C000000000000000000000002010101010002BC +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020101020226 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202010202020202020202020202F5 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00001010101020202020202020202020100CB +:102CF00000000000000000000100000000000101D1 +:102D000000000000000000000202010101010002B9 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020201020224 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020202D3 +:102DE00001010201020202020202020202020200C8 +:102DF00000000000000001000100000000000101CF +:102E000000000000000000000201010101010002B9 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020202D2 +:102EE00001010201020202020202020202020200C7 +:102EF00000000000000001000100000000000101CE +:102F000000000000000000000101010101010002B9 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002010201020202020202020202020200C5 +:102FF00000000000000001000100000000000101CD +:1030000000000000000000000101020101010001B8 +:103010000101020101020202020202020202020294 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020201020202020202020202020200C3 +:1030F00000000000000001000100000000000101CC +:1031000000000000000000020101020101010001B5 +:103110000101020101020202020202020202020293 +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020201020202020202020202020200C2 +:1031F00000000000000001000100000000000001CC +:1032000000000000000000020102020001010001B4 +:103210000101010101020202020202020202020293 +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020200C0 +:1032F00000000000000001000100000000000001CB +:1033000000020002000200010202020001010002AC +:103310000202010202020202020101010102020292 +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020200BF +:1033F00000000000000001000100000000000001CA +:1034000000020002000200010202010000010002AD +:103410000202020202010101010202020201010292 +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020200BE +:1034F00000000000000001000100000000000001C9 +:1035000002020202000102020202010000010002A6 +:10351000020202020202020202010101010202028F +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020200BD +:1035F00000000000000001000100000000000001C8 +:1036000002020202000102020201010000000001A8 +:103610000101010101010101010101010101010299 +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020201AB +:1037000002020201000102010101010000010001A9 +:103710000101010101010101010101010101010298 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020200AB +:1038000002010201000201010101010101010001A7 +:103810000101010101010101010101010101010297 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020200AA +:1039000002010101020201010101010101010001A5 +:103910000101010101010101010101010101010296 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020200A9 +:103A000001020102020201010101010101010001A3 +:103A10000101010101010101010101010101010295 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020200A8 +:103B000001020202010101010101010101010001A3 +:103B10000101010101010101010101010101010195 +:103B20000201010102020202020202020202020179 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020057 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020200A7 +:103C000002010202010101010101010101010101A1 +:103C10000101010101010101010101010101010293 +:103C2000020101020101020201020101010202027C +:103C30000202020102020202020202020202020265 +:103C40000202020202020202020202020202020056 +:103C5000000000000002020202020202020202024E +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020200A6 +:103D000002010101020101010101010101010101A1 +:103D10000101010101010101010101010101010193 +:103D2000010202000202010102010202020101017C +:103D30000101010201010101010101010101010271 +:103D40000202020202020202020202020202020055 +:103D50000000000000000000000000000000000261 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020200A5 +:103E000001010101020101010101000101010101A2 +:103E10000101010101010101010101010101010192 +:103E2000020202000101020201020101010202017B +:103E30000202020102020202020202020202020263 +:103E40000202020202020202020202020202020153 +:103E50000000000000000000000000000000000260 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020103 +:103EA0000101010101010101010101010101010201 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020201A3 +:103F000001010101010101000100000101010101A4 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010270 +:103F40000202020002020202020202020202020154 +:103F5000010101010100000000000000000000015B +:103F60000201010201020202020202020202020234 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020102 +:103FA0000101010101010101010101010101010200 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020201A2 +:1040000001010101010100000000000101010101A5 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:104030000101010101010101010101010101010170 +:104040000202010001010202020202020202020156 +:10405000010101010101010101010101010101024F +:104060000202020102020202020202020202020231 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020201A1 +:1041000001010101010100000000000101010101A4 +:10411000010101010101010101010101010101018F +:10412000010101010101010101010101010101017F +:10413000010101010101010101010101010101016F +:10414000010101010101010101010101010101015F +:10415000010101010101010101010101010101014F +:104160000100000200010101010101010101010240 +:104170000202010101020202020202020202020222 +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F00002020202020202020202020202020201A0 +:1042000001000001010000000000000101010101A6 +:10421000010101010101010101010101010101018E +:10422000010101010101010101010101010101017E +:10423000010101010101010101010101010101016E +:10424000010101010101010101010101010101015E +:10425000010101010101010101010101010101014E +:104260000200000100020202020202020202020235 +:10427000020202020102020202020202020202021F +:10428000020202020202020202020202020202020E +:104290000202020202020202020202020202020000 +:1042A000000000000000000000000000000000020C +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202019F +:1043000000000000010000000000000101010101A7 +:10431000010101010101010101010101010101018D +:10432000010101010101010101010101010101017D +:10433000010101010101010101010101010101016D +:10434000010101010101010101010101010101015D +:10435000010101010101010101010101010101014D +:10436000010101010101010101010101010101013D +:10437000010100000201010101010101010101022D +:10438000020202020202020202020202020202020D +:1043900002020202020202020202020202020200FF +:1043A000000000000000000000000000000000020B +:1043B00002020202020202020202020202020202DD +:1043C00002020202020202020202020202020202CD +:1043D00002020202020202020202020202020202BD +:1043E00002020202020202020202020202020202AD +:1043F000020202020202020202020202020202019E +:1044000000000000000000000000000101010101A7 +:10441000010101010101010101010101010101018C +:10442000010101010101010101010101010101017C +:10443000010101010101010101010101010101016C +:10444000010101010101010101010101010101015C +:10445000010101010101010101010101010101014C +:10446000010101010101010101010101010101013C +:104470000202000002020202020202020202020220 +:10448000020002020202020202020202020202010F +:10449000010101010101010101010102010201000B +:1044A000000000000000000000000000000000020A +:1044B00002020202020202020202020202020202DC +:1044C00002020202020202020202020202020202CC +:1044D00002020202020202020202020202020202BC +:1044E00002020202020202020202020202020202AC +:1044F000020202020202020202020202020202019D +:1045000000000000000000000000000101010101A6 +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:104580000101010101010101010101020202010217 +:1045900002020202020202020202020102010200FF +:1045A0000000000000000000000000000000000209 +:1045B00002020202020202020202020202020200DD +:1045C00000000000000000000000000000000002E9 +:1045D00002020202020202020202020202020202BB +:1045E00002020202020202020202020202020202AB +:1045F000020202020202020202020202020202019C +:1046000000000000000000000001010101010101A3 +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:10468000010101010101010101010101010101001B +:104690000000000000000000000000020002000115 +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010100EB +:1046C00000000000000000000000000000000002E8 +:1046D00002020202020202020202020202020202BA +:1046E00002020202020202020202020202020202AA +:1046F000020202020202020202020202020202019B +:10470000000000000000010101010101010101019F +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010100EA +:1047C00000000000000000000000000000000002E7 +:1047D00002020202020202020202020202020202B9 +:1047E00002020202020202020202020202020202A9 +:1047F000020202000002020202020202020202019E +:10480000000000000000010101010101010101019E +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010100D9 +:1048D00000000000000000000000000000000002D6 +:1048E00002020202020202020202020202020202A8 +:1048F000020200000002020202020202020202019F +:10490000000000000001010101010101010101019C +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010102C6 +:1049E00002020202000202020202020202020202A9 +:1049F000020200000002020202020202020202019E +:104A00000001010100010101010101010101010198 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010100B7 +:104AF00000020000000000020002020202020201A5 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010100B6 +:104BF00000000000000000000002020202020201A8 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010100B5 +:104CF00000000000000000000002020200020201A9 +:104D00000101010101010101010101010101010094 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000281 +:104D30000202020202020202020202020202020253 +:104D40000202020202020202020202020202020243 +:104D50000202020202020202020202020202020233 +:104D60000202020202020202020202020202020223 +:104D70000202020202020202020202020202020213 +:104D80000202020202020202020202020202020203 +:104D900002020202020202020202020202020202F3 +:104DA00002020202020202020202020202020202E3 +:104DB00002020202020202020202020202020202D3 +:104DC00002020202020202020202020202020202C3 +:104DD00002020202020202020202020202020202B3 +:104DE00002020202020202020202020202020200A5 +:104DF00000000000000000000002020000020201AA +:104E00000101010101010101010101010101010093 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000260 +:104E50000202020202020202020202020202020232 +:104E60000202020202020202020202020202020222 +:104E70000202020202020202020202020202020212 +:104E80000202020202020202020202020202020202 +:104E900002020202020202020202020202020202F2 +:104EA00002020202020202020202020202020202E2 +:104EB00002020202020202020202020202020202D2 +:104EC00002020202020202020202020202020202C2 +:104ED00002020202020202020202020202020202B2 +:104EE00002020202020202020202020202020200A4 +:104EF00000000000000000000000000000020201AD +:104F00000101010101010101010101010101010092 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F9000000000000000000000000000000000020F +:104FA00002020202020202020202020202020202E1 +:104FB00002020202020202020202020202020202D1 +:104FC00002020202020202020202020202020202C1 +:104FD00002020202020202020202020202020202B1 +:104FE00002020202020202020202020202020200A3 +:104FF00000000000000000000000000000020200AD +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F000000000000000000000000000000000525E +:105100000000000000000002000002020000020295 +:105110000200000201010001000000010000000087 +:105120000101000100010000000000000100010079 +:10513000000000000100000000010000010001006B +:10514000000002000000000000000100000100015A +:105150000000010002000000000100000002000148 +:105160000000010001000000000000000001010239 +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00001010000000201000000000001020101E5 +:1051C00000000100010000000000000001010101D9 +:1051D00000000100010000000000000000000000CD +:1051E00001010001000100000000000000000000BB +:1051F00000000000000000000000000000000000AF +:105200000000000000000002000002020000020294 +:105210000200000201010001010001010101010180 +:105220000101010101010001000000000100010075 +:105230000101000101010001000100010100010064 +:105240000101010200010000000001000001000155 +:105250000101010202020000000100000002000141 +:105260000101010001000000000000000001010236 +:10527000020200020002000001010000000202021E +:10528000000001000100000000000000000000001C +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000001020101F9 +:1052B00001010200020201000000000001020101E0 +:1052C00001010101010101000000000101010101D2 +:1052D00001010101010101000000000001000002C4 +:1052E00001010101010100000000000000000000B8 +:1052F00000000000000000000002020200000000A8 +:105300000000000000000002000002020000020293 +:10531000020000020202000101000101010101017D +:105320000101010101010001000000000101010172 +:10533000010101010101000100010101010201025D +:105340000101010101010000000001000101000153 +:10535000010101020202000001010000000202013D +:105360000101010001000000000000000001010136 +:10537000020202020201000001010000000202011B +:105380000101010101010000000000000000000017 +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000001020101F8 +:1053B00001010200020101000000000001020101E0 +:1053C00001010101010101000000000101010101D1 +:1053D00001010101010101000000000001000002C3 +:1053E00001010101010100000000000001010001B4 +:1053F00000000100010000000002020200000000A5 +:105400000000000000000002000002020000020292 +:10541000020000020202000101010101010101017B +:105420000101010101010001000000000101010171 +:10543000010101010101000100010101010201015D +:105440000101010101010000000001000101000152 +:105450000101010201010000010100000001010140 +:105460000101010001000100000000010001010133 +:10547000010201010101000001010000000202011E +:105480000101010101010000000000000000000016 +:10549000000000000000000000000000000000000C +:1054A00000000000020000000000000001020101F5 +:1054B00001010200010101000000000001010101E1 +:1054C00001010101010101000000000101010101D0 +:1054D00001010101010101000000000001020202BE +:1054E00001010101010100000000000001010001B3 +:1054F000010101010101010000020202000000009F +:105500000000000000000002000002020000020291 +:10551000020000020202000101010101010101017A +:10552000010101010101010100000000010101016F +:10553000010101010101000100010101010201015C +:10554000010101010101000000000100010102014F +:10555000010101010101000001010000010101013F +:105560000101010001000100000000010001010132 +:105570000101010101010000010100000001010120 +:105580000101010101010000000000000000000015 +:105590000000000002000000000000000000000009 +:1055A00000000002020200000000000001010101F1 +:1055B00001010100010101000000000001010101E1 +:1055C00001010101010101000000000101010101CF +:1055D00001010101010101000000000001020201BE +:1055E00001010101010100000000000001010201B0 +:1055F000010101010101010000020202000000009E +:105600000000000000000002000002020000020290 +:105610000200000202020001010101010101010179 +:10562000010101010101010100000001010101016D +:10563000010101010101000100010101010101015C +:10564000010101010101010100000100010102014C +:10565000010101010101000001010000010101013E +:10566000010101000102010100000001000101012E +:10567000010101010101000001010000000101011F +:105680000101010101010000000000000000000014 +:105690000000000202020000000000000000000004 +:1056A00000000202020200000000000001010101EE +:1056B00001010100010101000000000001010101E0 +:1056C00001010101010101000000000101010101CE +:1056D00001010101010101000000000001010101BF +:1056E00001010101010100000000000001010101B0 +:1056F000010101010101010001010101010101019B +:105700000101010101010102000002020000020288 +:105710000200000202020001010101010101010178 +:10572000010101010101010100000101010101016B +:10573000010101010101000101010101010101015A +:10574000010101010101010100000100010102014B +:10575000010101010101000001010000010101013D +:10576000010101000102010100000001000101012D +:10577000010101010101000001010000000101011E +:105780000101010101010100000000000000000012 +:105790000000000202020000000000000000000003 +:1057A00002000202010200000000000001010101EC +:1057B00001010100010101000000000001010101DF +:1057C00001010101010101000000010101010101CC +:1057D00001010101010101000000000001010101BE +:1057E00001010101010100000000000001010101AF +:1057F000010101010101010001010101010101019A +:105800000101010101010102000002020000020287 +:105810000200000202020001010101010101010177 +:10582000010101010101010100000101010101016A +:105830000101010101010001010101010101010159 +:10584000010101010101010100000100010101014B +:10585000010101010101000001010000010101013C +:10586000010101020102010100000001000101012A +:10587000010101010101000001010000010101011C +:105880000101010101010100000000000000000011 +:105890000200000201020000000000000000000001 +:1058A00002000201010100000000000001010101ED +:1058B00001010100010101000000000101010101DD +:1058C00001010101010101010000010101010101CA +:1058D00001010101010101000000000001010101BD +:1058E00001010101010100000000000001010101AE +:1058F0000101010101010100010101010101010199 +:105900000101010101010102000002020000020286 +:105910000200000202020001010101010101010176 +:105920000101010101010101010001010101010168 +:105930000101010101010001010101010101010158 +:10594000010101010101010100000100010101014A +:10595000010101010101000001010000010101013B +:105960000101010201010101000001010101010128 +:10597000010101010101000001010000010101011B +:10598000010101010101010000000000000000020E +:105990000200020101010000000000000000000000 +:1059A00002020101010100000000000001010101EB +:1059B00001010100010101000000000101010101DC +:1059C00001010101010101010000010101010101C9 +:1059D00001010101010101000000000001010101BC +:1059E00001010101010101000000010001010101AB +:1059F0000101010101010100010101010101010198 +:105A00000101010101010102000002020000020285 +:105A10000200000202020001010101010101010175 +:105A20000101010101010101010001010101010167 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101000001000101010149 +:105A50000101010101010100010100000101010139 +:105A60000101010201010101000001010101010127 +:105A70000101010101010100010100000101010119 +:105A8000010101010101010000000000000000020D +:105A900002020201010100000000000000000002FB +:105AA00001020101010100000000000001010101EB +:105AB00001010102010101000000000101010101D9 +:105AC00001010101010101010000010101010101C8 +:105AD00001010101010101000000000001010101BB +:105AE00001010101010101000000010001010101AA +:105AF0000101010101010100010101010101010197 +:105B00000101010101010102000002020000020284 +:105B10000200000202020002010101010101010173 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101000101000101010147 +:105B50000101010101010100010100000101010138 +:105B60000101010101010101010001010101010126 +:105B70000101010101010101010100000101010117 +:105B8000010101010101010000000000000000020C +:105B900001020201010100000000000000000002FB +:105BA00001020101010100000000000101010101E9 +:105BB00001010101010101000000000101010101D9 +:105BC00001010101010101010001010101010101C6 +:105BD00001010101010101000000000001010101BA +:105BE00001010101010101000000010001010101A9 +:105BF000010101010101010000000000000000009E +:105C00000000000000000102000002020000020289 +:105C10000200000202020002010101010101010172 +:105C20000101010101010101010101010101010164 +:105C30000101010101010101010101010101010154 +:105C40000101010101010101000101010101010145 +:105C50000101010101010101010100000101010136 +:105C60000101010101010101010001010101010125 +:105C70000101010101010101010100000101010116 +:105C8000010101010101010000000000000000010C +:105C900001020101010100000000000000000202F9 +:105CA00001010101010100000000000101010101E9 +:105CB00001010101010101000000000101010101D8 +:105CC00001010101010101010001010101010101C5 +:105CD00001010101010101000000000001010101B9 +:105CE00001010101010101000000010001010101A8 +:105CF000010101010101010000000000000000009D +:105D00000000000000000102000002020000020288 +:105D10000200000202020002010101010101010171 +:105D20000101010101010101010101010101010163 +:105D30000101010101010101010101010101010153 +:105D40000101010101010101000101010101010144 +:105D50000101010101010101010101000101010134 +:105D60000101010101010101010001010101010124 +:105D70000101010101010101010100000101010115 +:105D80000101010101010100000000000000020109 +:105D900001010101010100000000000000000201FA +:105DA00001010101010100000000000101010101E8 +:105DB00001010101010101000001000101010101D6 +:105DC00001010101010101010101010101010101C3 +:105DD00001010101010101000000000001010101B8 +:105DE00001010101010101000000010001010101A7 +:105DF000010101010101010000000000000000009C +:105E00000000000000000102000002020000020287 +:105E10000200000202020002010101010101010170 +:105E20000101010101010101010101010101010162 +:105E30000101010101010101010101010101010152 +:105E40000101010101010101000101010101010143 +:105E50000101010101010101010101010101010132 +:105E60000101010101010101010001010101010123 +:105E70000101010101010101010100000101010114 +:105E80000101010101010100000000000000020108 +:105E900001010101010100000000000000020201F7 +:105EA00001010101010100000000000101010101E7 +:105EB00001010101010101000001000101010101D5 +:105EC00001010101010101010101010101010101C2 +:105ED00001010101010101000000000001010101B7 +:105EE00001010101010101000000010001010101A6 +:105EF000010101010101010000000000000000009B +:105F00000000000000000102000002020000020286 +:105F1000020000020202000202010101010101016E +:105F20000101010101010101010101010101010161 +:105F30000101010101010101010101010101010151 +:105F40000101010101010101010101010101010141 +:105F50000101010101010101010101010101010131 +:105F60000101010101010101010001010101010122 +:105F70000101010101010101010100010101010112 +:105F80000101010101010100000000000000020107 +:105F900001010101010100000000000000020101F7 +:105FA00001010101010100000000000101010101E6 +:105FB00001010101010101000001010101010101D3 +:105FC00001010101010101010101010101010101C1 +:105FD00001010101010101000000000001010101B6 +:105FE00001010101010101000000010001010101A5 +:105FF000010101010101010000000000000000009A +:106000000000000000000102000002020000020285 +:10601000020000020202000202010202010101016B +:106020000101010101010101010101010101010160 +:106030000101010101010101010101010101010150 +:106040000101010101010101010101010101010140 +:106050000101010101010101010101010101010130 +:106060000101010101010101010001010101010121 +:106070000101010101010101010100010101010111 +:106080000101010101010101000000000000010106 +:1060900001010101010100000000000001020101F5 +:1060A00001010101010100000000010101010101E4 +:1060B00001010101010101010001010101010101D1 +:1060C00001010101010101010101010101010101C0 +:1060D00001010101010101000000000001010101B5 +:1060E00001010101010101000000010001010101A4 +:1060F0000101010101010100000000000000000099 +:106100000000000000000102000002020000020284 +:106110000200000202020002020202020101010169 +:10612000010101010101010201010101010101015E +:10613000010101010101010101010101010101014F +:10614000010101010101010101010101010101013F +:10615000010101010101010101010101010101012F +:106160000101010101010101010001010101010120 +:106170000101010101010101010100010101010110 +:106180000101010101010101000000000002010103 +:1061900001010101010100000000000001010101F5 +:1061A00001010101010100000000010101010101E3 +:1061B00001010101010101010001010101010101D0 +:1061C00001010101010101010101010101010101BF +:1061D00001010101010101000000000001010101B4 +:1061E00001010101010101000000010001010101A3 +:1061F0000101010101010100000000000000000098 +:106200000000000000000102000002020000020283 +:106210000200000202020002020202020101010168 +:10622000010101010101010201010101010101015D +:10623000010101010101010201010101010101014D +:10624000010101010101010101010101010101013E +:10625000010101010101010101010101010101012E +:10626000010101010101010101000101010101011F +:10627000010101010101010101010101010101010E +:106280000101010101010101000000000002010102 +:1062900001010101010100000000000001010101F4 +:1062A00001010101010100000001010101010101E1 +:1062B00001010101010101010001010101010101CF +:1062C00001010101010101010101010101010101BE +:1062D00001010101010101000000000001010101B3 +:1062E00001010101010101000000010101010101A1 +:1062F0000101010101010100000000000000000097 +:106300000000000000000102000002020000020282 +:106310000200000202020002020202020102010166 +:10632000010101010101010201010101010101015C +:10633000010101010101010201010101010101014C +:10634000010101010101010101010101010101013D +:10635000010101010101010101010101010101012D +:10636000010101010101010101000101010101011E +:10637000010101010101010101010101010101010D +:106380000101010101010101000001000002010100 +:1063900001010101010100000000000001010101F3 +:1063A00001010101010101000001010101010101DF +:1063B00001010101010101010101010101010101CD +:1063C00001010101010101010101010101010101BD +:1063D00001010101010101000000000001010101B2 +:1063E00001010101010101000000010101010101A0 +:1063F0000101010101010100000000000000000096 +:106400000000000000000102000002020000020281 +:106410000200000202020002020202020202010164 +:10642000010101010101010201010101010101015B +:10643000010101010101010201010101010101014B +:10644000010101010101010101010101010101013C +:10645000010101010101010101010101010101012C +:10646000010101010101010101000101010101011D +:10647000010101010101010101010101010101010C +:1064800001010101010101010000010100010101FF +:1064900001010101010101000000000001010101F1 +:1064A00001010101010101000001010101010101DE +:1064B00001010101010101010101010101010101CC +:1064C00001010101010101010101010101010101BC +:1064D00001010101010101000000000001010101B1 +:1064E000010101010101010000000101010101019F +:1064F0000101010101010100000000000000000095 +:10650000000000000101010200000202000002027E +:106510000200000202020002020202020202020162 +:106520000102010101010102010101010101010159 +:10653000010101010101010201010101010101014A +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010000010101010101FD +:1065900001010101010101000000000001010101F0 +:1065A00001010101010101000001010101010101DD +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101000000000001010101B0 +:1065E000010101010101010000000101010101019E +:1065F0000101010101010100000000000000000193 +:10660000000101010101010200000202000002027A +:106610000200000202020002020202020202020260 +:106620000102010101010102010101010101010158 +:106630000101010101010102010101010101010149 +:10664000010101010101010101010101010101013A +:10665000010101010101010101010101010101012A +:10666000010101010101010101010101010101011A +:10667000010101010101010101010101010101010A +:1066800001010101010101010000010101010101FC +:1066900001010101010101000000010001010101EE +:1066A00001010101010101000101010101010101DB +:1066B00001010101010101010101010101010101CA +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101000000000001010101AF +:1066E000010101010101010100000101010101019C +:1066F0000101010101010100000000000000000192 +:106700000101010101010102000002020000020278 +:10671000020000020202000202020202020202025F +:106720000202010201010102010101010101010155 +:106730000101010101010102010201010101010147 +:106740000101010101010101010101010101010139 +:106750000101010101010101010101010101010129 +:106760000101010101010101010101010101010119 +:106770000101010101010101010101010101010109 +:1067800001010101010101010001010101010101FA +:1067900001010101010101000000010001010101ED +:1067A00001010101010101000101010101010101DA +:1067B00001010101010101010101010101010101C9 +:1067C00001010101010101010101010101010101B9 +:1067D00001010101010101000000000101010101AD +:1067E000010101010101010100000101010101019B +:1067F0000101010101010100000000000000000191 +:106800000101010101010102000002020000020277 +:10681000020000020202000202020202020202025E +:106820000202020201010102010101010101010153 +:106830000101010101010102010202020101010144 +:106840000101010101010102010101010101010137 +:106850000101010101010101010101010101010128 +:106860000101010101010102010101010101010117 +:106870000101010101010101010101010101010108 +:1068800001010101010101010001010101010101F9 +:1068900001010101010101000001010001010101EB +:1068A00001010101010101000101010101010101D9 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101000000010101010101AB +:1068E000010101010101010100000101010101019A +:1068F0000101010101010100000000000000000190 +:106900000101010101010102000002020000020276 +:10691000020000020202000202020202020202025D +:106920000202020202020102010101010101010150 +:106930000101010101010102020202020101010142 +:106940000101010101010102010101010101010136 +:106950000101010101010101010101010101010127 +:106960000101010101010102010101010101010116 +:106970000101010101010101010101010101010107 +:1069800001010101010101010101010101010101F7 +:1069900001010101010101000001010001010101EA +:1069A00001010101010101000101010101010101D8 +:1069B00001010101010101010101010101010101C7 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101000000010101010101AA +:1069E0000101010101010101000001010101010199 +:1069F000010101010101010000010001000000018D +:106A00000101010101010102000002020000020275 +:106A1000020000020202000202020202020202025C +:106A20000202020202020102020102020202020149 +:106A30000101010101010102020202020101010141 +:106A40000101010101010102010102010101010134 +:106A50000101010101010101020201010101010124 +:106A60000101010101010102010101010101010115 +:106A70000101010101010101020101010101010105 +:106A800001010101010101010101010101010101F6 +:106A900001010101010101000001010001010101E9 +:106AA00001010101010101000101010101010101D7 +:106AB00001010101010101010101010101010101C6 +:106AC00001010101010101010101010101010101B6 +:106AD00001010101010101000000010101010101A9 +:106AE0000101010101010101000001010101010198 +:106AF000010101010101010000010001000000018C +:106B00000101010101010102000002020000020274 +:106B1000020000020202000202020202020202025B +:106B20000202020202020202020102020202020147 +:106B3000010101010101010202020202020102013E +:106B40000101010101010102010102010101010133 +:106B50000101010101010101020201010101010123 +:106B60000101010101010102010101010101010114 +:106B70000101010101010101020201010101010103 +:106B800001010101010101010101010101010101F5 +:106B900001010101010101000001010001010101E8 +:106BA00001010101010101000101010101010101D6 +:106BB00001010101010101010101010101010101C5 +:106BC00001010101010101010101010101010101B5 +:106BD00001010101010101000000010101010101A8 +:106BE0000101010101010101000001010101010197 +:106BF000010101010101010000010001000000018B +:106C00000101010101010102000002020000020273 +:106C1000020000020202000202020202020202025A +:106C20000202020202020202020202020202020145 +:106C3000010201010101010202020202020102013C +:106C40000101010101010102010102010102010131 +:106C50000101010101010102020201010101010121 +:106C60000101010101010102010101020102010111 +:106C70000101010101010102020201010101010101 +:106C800001010101010101010101010101010101F4 +:106C900001010101010101000101010001010101E6 +:106CA00001010101010101000101010101010101D5 +:106CB00001010101010101010101010101010101C4 +:106CC00001010101010101010101010101010101B4 +:106CD00001010101010101000000010101010101A7 +:106CE0000101010101010101000001010101010196 +:106CF000010101010101010000010001000000018A +:106D00000101010101010102000002020000020272 +:106D10000200000202020002020202020202020259 +:106D20000202020202020202020202020202020243 +:106D3000020201010101010202020202020102013A +:106D4000010201010101010201010201010201012F +:106D50000101010101010102020201010101010120 +:106D6000010101010101010201010102010202010F +:106D70000101010101010102020201010101010100 +:106D800001010101010101010101010101010101F3 +:106D900001010101010101000101010101010101E4 +:106DA00001010101010101010101010101010101D3 +:106DB00001010101010101010101010101010101C3 +:106DC00001010101010101010101010101010101B3 +:106DD00001010101010101000000010101010101A6 +:106DE0000101010101010101000001010101010195 +:106DF0000101010101010100000101010000000188 +:106E00000101010101010102000001010000020273 +:106E10000200000202020002020202020202020258 +:106E20000202020202020202020202020202020242 +:106E30000202020202010102020202020201020136 +:106E4000020201010101010201010201010201012D +:106E5000010101010101010202020101010101011F +:106E6000010101010101010202010202010202010C +:106E700001010101010101020202010101010101FF +:106E800001010101010101010101010101010101F2 +:106E900001010101010101000101010101010101E3 +:106EA00001010101010101010101010101010101D2 +:106EB00001010101010101010101010101010101C2 +:106EC00001010101010101020101010101010101B1 +:106ED00001010101010101000101010101010101A3 +:106EE0000101010101010101000001010101010194 +:106EF0000101010101010100000101010000000187 +:106F00000101010101010102000001010000010174 +:106F10000200000102020002020202020202020258 +:106F20000202020202020202020202020202020241 +:106F30000202020202020102020202020202020232 +:106F40000202020101010102010102010202010229 +:106F5000010101010101010202020101010101021D +:106F6000010101010101010202010202010202010B +:106F700001010101010101020202010101010101FE +:106F800001010101010101010101010101010101F1 +:106F900001010101010101000101010101010101E2 +:106FA00001010101010101010101010101010101D1 +:106FB00001010101010101010101010102010201BF +:106FC00001010101010101020101010201010101AF +:106FD00001010101010101010101010101010101A1 +:106FE0000101010101010101000001010101010193 +:106FF0000101010101010100000101010000000186 +:107000000101010101010102000001010000020172 +:107010000100000102020002020202020202020258 +:107020000202020202020202020202020202020240 +:107030000202020202020102020202020202020231 +:107040000202020202020102010202010202010224 +:107050000202020101010102020201010202020216 +:107060000202020101010102020102020102020107 +:1070700001010101010101020202010101010101FD +:1070800001010101010101020101010101010101EF +:1070900001010101010101000101010101010101E1 +:1070A00001010101010101010101010101010101D0 +:1070B00001010101010101020101010202010202BB +:1070C00001010101010101020101010201020101AD +:1070D00001010101010101010101010101010101A0 +:1070E0000101010101010101000001010101010192 +:1070F0000101010101010100000101010000000185 +:107100000101010101010102000001010000010172 +:107110000100000102010002020202020202020258 +:10712000020202020202020202020202020202023F +:107130000202020202020102020202020202020230 +:107140000202020202020102020202020202010221 +:107150000202020101010102020202010202020214 +:107160000202020102010102020102020102020204 +:1071700001010101010101020202010101020102FA +:1071800002020201010101020101010101010101EB +:1071900001010101010101000101010101010101E0 +:1071A00001010101010101010101010101010101CF +:1071B00001010101010101020101010202020202B9 +:1071C00002020201010101020101020202020201A6 +:1071D000010101010101010101010101010101019F +:1071E0000101010101010101000101010101010190 +:1071F0000101010101010100000001010000000185 +:107200000101010101010101000002020000010170 +:107210000100000101010002020202020202020258 +:10722000020202020202020202020202020202023E +:10723000020202020202010202020202020202022F +:10724000020202020202020202020202020201021F +:107250000202020101010102020202020202020212 +:107260000202020102010102020102020202020202 +:1072700002010201010101020202010102020202F5 +:1072800002020202020101020101010101010101E8 +:1072900001010101010101000101010101010101DF +:1072A00001010101010101010101010102010201CC +:1072B00001010101010101020102010202020202B7 +:1072C00002020202020101020101020202020202A2 +:1072D000010101010101010101010101010101019E +:1072E000010101010101010100010101010101018F +:1072F0000101010101010100000001000000000185 +:10730000010101010101010100000202000001016F +:107310000100000101010002020202020202020257 +:10732000020202020202020202020202020202023D +:10733000020202020202010202020202020202022E +:10734000020202020202020202020202020201021E +:107350000202020101010102020202020202020211 +:107360000202020102010202020102020202020200 +:1073700002020202020201020202010202020202EF +:1073800002020202020201020101010101010101E6 +:1073900001010101010101000101010101010101DE +:1073A00001010101010101010101010102010202CA +:1073B00002020101010101020102020202020202B3 +:1073C000020202020202020202020202020202029D +:1073D0000202020101010101010101010201010199 +:1073E000010101010101010101010101010201018C +:1073F0000101010101010100000000000000000185 +:10740000010101010101010100000202000001016E +:107410000100000101010002020202020202020256 +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:107450000202020101010102020202020202020210 +:1074600002020201020102020201020202020202FF +:1074700002020202020201020202020202020202ED +:1074800002020202020201020101010101010101E5 +:1074900001010101010101000101010101010101DD +:1074A00001010101010101010101010202020202C7 +:1074B00002020101010101020202020202020202B1 +:1074C000020202020202020202020202020202029C +:1074D0000202020202010101010101010201010196 +:1074E0000202010101010101010102010202010187 +:1074F0000101010101010100000000000000000085 +:10750000010001010101010100000202000001016E +:107510000100000101010002020202020202020255 +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202010202020202020202020C +:1075600002020201020102020202020202020202FD +:1075700002020202020201020202020202020202EC +:1075800002020202020202020101020101010101E2 +:1075900001010101010101000101010101010101DC +:1075A00001010101010101010101010202020202C6 +:1075B00002020101010102020202020202020202AF +:1075C000020202020202020202020202020202029B +:1075D0000202020202020201010101010202010192 +:1075E0000202020201010101010102010202010283 +:1075F0000101010101010100000000000000000084 +:107600000000010101010002000001010000010170 +:107610000100000101010002020202020202020254 +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202010202020202020202020B +:1076600002020201020102020202020202020202FC +:1076700002020202020202020202020202020202EA +:1076800002020202020202020101020201010101E0 +:1076900001010101010101000101010101010101DB +:1076A00001010101010101010101020202020202C4 +:1076B00002020101010102020202020202020202AE +:1076C000020202020202020202020202020202029A +:1076D0000202020202020201010101010202020190 +:1076E000020202020202010101010201020202027F +:1076F0000202020101010100000000000000000080 +:107700000000000101010002000001010000010170 +:107710000100000101010002020202020202020253 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020201020102020202020202020202FB +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020201010101DD +:1077900001010101010101000101020101010101D9 +:1077A00001010101010101010102020202020202C2 +:1077B00002020201020202020202020202020202AA +:1077C0000202020202020202020202020202020299 +:1077D000020202020202020101010101020202028E +:1077E000020202020202010201010201020202027D +:1077F000020202020201010000000000000000007D +:10780000000000010101000200000101000001016F +:107810000100000101010002020202020202020252 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020201010102DB +:1078900002010102020101000102020102010101D3 +:1078A00002010202020101010202020202020202BC +:1078B00002020201020202020202020202020202A9 +:1078C0000202020202020202020202020202020298 +:1078D000020202020202020101010101020202028D +:1078E000020202020202010201010201020202027C +:1078F000020202020202020000000000000000007A +:10790000000000010101000200000101000001016E +:10791000010002010101000202020202020202024F +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020201010202D9 +:1079900002020202020201000202020102020202CB +:1079A00002020202020201020202020202020202B8 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D000020202020202020101010101020202028C +:1079E000020202020202010201010202020202027A +:1079F0000202020202020200000000000000000079 +:107A00000000000000010001000001010000010170 +:107A1000010002010101000202020202020202024E +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020201000202020102020202CA +:107AA00002020202020201020202020202020202B7 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD000020202020202020101010101020202028B +:107AE0000202020202020202010102020202020278 +:107AF0000202020202020200000000000000000078 +:107B0000000000000001000100000101000001016F +:107B1000010002010101000202020202020202024D +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020201010202020102020202C8 +:107BA00002020202020201020202020202020202B6 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202010102020202020287 +:107BE0000202020202020202010102020202020277 +:107BF0000202020202020200000000000100010075 +:107C0000000000000001000100000101000001016E +:107C1000010002010101000202020202020202024C +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020201010202020202020202C6 +:107CA00002020202020201020202020202020202B5 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202010102020202020286 +:107CE0000202020202020202010102020202020276 +:107CF0000202020202020200000000000100010074 +:107D0000000000000001000100000101020001016B +:107D1000010001010101000202020202020202024C +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202010202020202020202C4 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020102020202020284 +:107DE0000202020202020202010102020202020275 +:107DF0000202020202020200000000000101010072 +:107E0000000000000000000100000101020001016B +:107E1000010001010101000202020202020202024B +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202010202020202020202C3 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020202020202020202020282 +:107EE0000202020202020202010102020202020274 +:107EF0000202020202020200000000000101010071 +:107F0000000000000000000100000101020001016A +:107F10000102010101010002020202020202020248 +:107F20000202020202020202020202020202020231 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020202C1 +:107FA00002020202020202020202020202020202B1 +:107FB00002020202020202020202020202020202A1 +:107FC0000202020202020202020202020202020291 +:107FD0000202020202020202020202020202020281 +:107FE0000202020202020202010102020202020273 +:107FF0000202020202020200000000000101010070 +:108000000000000000000001000001010200010169 +:108010000102010101010002020202020202020247 +:108020000202020202020202020202020202020230 +:108030000202020202020202020202020202020220 +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202020202020202020202C0 +:1080A00002020202020202020202020202020202B0 +:1080B00002020202020202020202020202020202A0 +:1080C0000202020202020202020202020202020290 +:1080D0000202020202020202020202020202020280 +:1080E0000202020202020202020202020202020270 +:1080F000020202020202020000000000010101006F +:108100000000000000000001000001010100010169 +:108110000101020101010002020202020202020246 +:10812000020202020202020202020202020202022F +:10813000020202020202020202020202020202021F +:10814000020202020202020202020202020202020F +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202020202020202020202BF +:1081A00002020202020202020202020202020202AF +:1081B000020202020202020202020202020202029F +:1081C000020202020202020202020202020202028F +:1081D000020202020202020202020202020202027F +:1081E000020202020202020202020202020202026F +:1081F000020202020202020000000000010101006E +:108200000000000000000001000001010100010168 +:108210000101020101010002020202020202020245 +:10822000020202020202020202020202020202022E +:10823000020202020202020202020202020202021E +:10824000020202020202020202020202020202020E +:1082500002020202020202020202020202020202FE +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202020202020202020202BE +:1082A00002020202020202020202020202020202AE +:1082B000020202020202020202020202020202029E +:1082C000020202020202020202020202020202028E +:1082D000020202020202020202020202020202027E +:1082E000020202020202020202020202020202026E +:1082F000020202020202020000000000010101006D +:108300000000000000000001000201010100010165 +:108310000101020101010000020202020202020246 +:10832000020202020202020202020202020202022D +:10833000020202020202020202020202020202021D +:10834000020202020202020202020202020202020D +:1083500002020202020202020202020202020202FD +:1083600002020202020202020202020202020202ED +:1083700002020202020202020202020202020202DD +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020202BD +:1083A00002020202020202020202020202020202AD +:1083B000020202020202020202020202020202029D +:1083C000020202020202020202020202020202028D +:1083D000020202020202020202020202020202027D +:1083E000020202020202020202020202020202026D +:1083F000020202020202020202020202020202025D +:108400000202020202020201000201010100010156 +:10841000010102010101000000000000020202024D +:10842000020202020202020202020202020202022C +:10843000020202020202020202020202020202021C +:10844000020202020202020202020202020202020C +:1084500002020202020202020202020202020202FC +:1084600002020202020202020202020202020202EC +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020202BC +:1084A00002020202020202020202020202020202AC +:1084B000020202020202020202020202020202029C +:1084C000020202020202020202020202020202028C +:1084D000020202020202020202020202020202027C +:1084E000020202020202020202020202020202026C +:1084F000020202020202020202020202020202025C +:108500000202020202020201000201010202010053 +:108510000102010101010000000000000000020250 +:10852000020002020202020202020202020202022D +:10853000020202020202020202020202020202021B +:10854000020202020202020202020202020202020B +:1085500002020202020202020202020202020202FB +:1085600002020202020202020202020202020202EB +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020202AB +:1085B000020202020202020202020202020202029B +:1085C000020202020202020202020202020202028B +:1085D000020202020202020202020202020202027B +:1085E000020202020202020202020202020202026B +:1085F000020202020202020202020202020202025B +:108600000202020202020201000201010202000053 +:108610000102010101010001000000000000000052 +:10862000020002000202020202020202020202022E +:10863000020202020202020202020202020202021A +:10864000020202020202020202020202020202020A +:1086500002020202020202020202020202020202FA +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202020202DA +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020202AA +:1086B000020202020202020202020202020202029A +:1086C000020202020202020202020202020202028A +:1086D000020202020202020202020202020202027A +:1086E000020202020202020202020202020202026A +:1086F000020202020202020202020202020202025A +:108700000202020202020201000201010201000053 +:10871000000201000101000101010101000000004F +:108720000000000000000002020202020202020237 +:108730000202020202020202020202020202020219 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020202A9 +:1087B0000202020202020202020202020202020299 +:1087C0000202020202020202020202020202020289 +:1087D0000202020202020202020202020202020279 +:1087E0000202020202020202020202020202020269 +:1087F0000202020202020202020202020202020259 +:108800000202020202020201000100000201000055 +:10881000000201000101000101010101010100004C +:108820000001000000000002020202020202020235 +:108830000202020202020202020202020202020218 +:108840000202020202020202020202020202020208 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202020202020202020202D8 +:1088800002020202020202020202020202020202C8 +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202020202A8 +:1088B0000202020202020202020202020202020298 +:1088C0000202020202020202020202020202020288 +:1088D0000202020202020202020202020202020278 +:1088E0000202020202020202020202020202020268 +:1088F0000202020202020202020202020202020258 +:108900000202020202020201000100000101000055 +:10891000000101000100000101010101010101014B +:108920000001000100000002020202020202020233 +:108930000202020202020202020202020202020217 +:108940000202020202020202020202020202020207 +:1089500002020202020202020202020202020202F7 +:1089600002020202020202020202020202020202E7 +:1089700002020202020202020202020202020202D7 +:1089800002020202020202020202020202020202C7 +:1089900002020202020202020202020202020202B7 +:1089A00002020202020202020202020202020202A7 +:1089B0000202020202020202020202020202020297 +:1089C0000202020202020202020202020202020287 +:1089D0000202020202020202020202020202020277 +:1089E0000202020202020202020202020202020267 +:1089F0000202020202020202020202020202020257 +:108A00000202020202020200000100000102000054 +:108A10000101010101010001010101010101010147 +:108A2000010101010101010002020202020202022F +:108A30000202020202020200020202020202020218 +:108A40000202020202020202020202020202020206 +:108A500002020202020202020202020202020202F6 +:108A600002020202020202020202020202020202E6 +:108A700002020202020202020202020202020202D6 +:108A800002020202020202020202020202020202C6 +:108A900002020202020202020202020202020202B6 +:108AA00002020202020202020202020202020202A6 +:108AB0000202020202020202020202020202020296 +:108AC0000202020202020202020202020202020286 +:108AD0000202020202020202020202020202020276 +:108AE0000202020202020202020202020202020266 +:108AF0000202020202020202020202020202020256 +:108B0000020202020202020002020000010200014F +:108B10000101010101010001010101010101010146 +:108B2000010101010101010002020202020202022E +:108B30000202020202020200020202020202020217 +:108B40000202020202020202020202020202020205 +:108B500002020202020202020202020202020202F5 +:108B600002020202020202020202020202020202E5 +:108B700002020202020202020202020202020202D5 +:108B800002020202020202020202020202020202C5 +:108B900002020202020202020202020202020202B5 +:108BA00002020202020202020202020202020202A5 +:108BB0000202020202020202020202020202020295 +:108BC0000202020202020202020202020202020285 +:108BD0000202020202020202020202020202020275 +:108BE0000202020202020202020202020202020265 +:108BF0000202020202020202020202020202020255 +:108C0000020202020202020002020000010201014D +:108C10000101010101010001010101010101010145 +:108C2000010101010101010102020202020202022C +:108C3000020202020202020000000000020202021E +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202020202020202020202C4 +:108C900002020202020202020202020202020202B4 +:108CA00002020202020202020202020202020202A4 +:108CB0000202020202020202020202020202020294 +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020202020202020202020274 +:108CE0000202020202020202020202020202020264 +:108CF0000202020202020202020202020202020254 +:108D0000020202020202020002020000010101014D +:108D10000101010101010001010101010101010144 +:108D20000101010101010101000000000000000239 +:108D30000200020202020201000000000002000222 +:108D40000200020202020202020202020202020205 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202020202D3 +:108D800002020202020202020202020202020202C3 +:108D900002020202020202020202020202020202B3 +:108DA00002020202020202020202020202020202A3 +:108DB0000202020202020202020202020202020293 +:108DC0000202020202020202020202020202020283 +:108DD0000202020202020202020202020202020273 +:108DE0000202020202020202020202020202020263 +:108DF0000202020202020202020202020202020253 +:108E0000020202020202020001010000010101014E +:108E10000101010101010101010101010101010142 +:108E2000010101010101010100000000000000003A +:108E3000000000000000020100000000000000002F +:108E40000000000000000002020202020202020210 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202020202020202020202C2 +:108E900002020202020202020202020202020202B2 +:108EA00002020202020202020202020202020202A2 +:108EB0000202020202020202020202020202020292 +:108EC0000202020202020202020202020202020282 +:108ED0000202020202020202020202020202020272 +:108EE0000202020202020202020202020202020262 +:108EF0000202020202020202020202020202020252 +:108F0000020202020202020001010001010101014C +:108F10000101000101010101010101010101010142 +:108F20000101010101010101010101010101010032 +:108F3000000100000000000101010101000000002B +:108F4000000000000000000202020202020202020F +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202020202020202020202D1 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020202020202020202A1 +:108FB0000202020202020202020202020202020291 +:108FC0000202020202020202020202020202020281 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202020202020261 +:108FF0000202020202020202020202020202020251 +:109000000202020202020200020101010101010149 +:109010000101000101010101010101010101010141 +:109020000101010101010101010101010101010130 +:109030000101010101010001010101010100010023 +:10904000000100000000000102020202020202020E +:1090500002020202020202020202020202020202F0 +:1090600002020202020202010202020202020202E1 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020202020202020202020202A0 +:1090B0000202020202020202020202020202020290 +:1090C0000202020202020202020202020202020280 +:1090D0000202020202020202020202020202020270 +:1090E0000202020202020202020202020202020260 +:1090F0000202020202020202020202020202020250 +:109100000202020202020201020101010001010148 +:109110000101000101010101010101010101010140 +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010100020102020102020B +:1091500002020202020202020202020202020202EF +:1091600002020202020202020102010102010102E4 +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D000020202020202020202020202020202026F +:1091E000020202020202020202020202020202025F +:1091F000020202020202020202020202020202024F +:109200000202020202020201010101010001010148 +:109210000100000101010101010101010101010140 +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010100010101010102010E +:1092500001010102020202000000020202020202F7 +:1092600002020202020202010201020201020201E2 +:1092700001010101010101000000020202020202DB +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202020202025E +:1092F000020202020202020202020202020202024E +:109300000202020202020201010101010000010148 +:10931000010000010101010101010101010101013F +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:109350000101010101010100000000000000000006 +:1093600000000002000200010102010102010102ED +:1093700002020202020202000000000000000000DF +:1093800000000000000000020202020202020202CB +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202029D +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202020202025D +:1093F000020202020202020202020202020202024D +:109400000202020202020201010001010000010148 +:10941000010000010101010101010101010101013E +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:109450000101010101010100000000000000000005 +:1094600000000000000000010101010101010101F3 +:1094700001010101010101000000000000000000E5 +:1094800000000000000000020101010102020202CE +:1094900002020202020202020202020202020202AC +:1094A000020202020202020202020202020202029C +:1094B000020202020202020202020202020202028C +:1094C000020202020202020202020202020202027C +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202020202020202020202024C +:109500000202020202020201010001010000010147 +:10951000010000010101010101010101010101013D +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:109550000101010101010101010100000000000001 +:1095600000000000000000010101010101010101F2 +:1095700001010101010101010101000000000000E1 +:1095800000000000000000020202020202020202C9 +:1095900002020202020202020101010202020202AE +:1095A000020202020202020202020202020202029B +:1095B000020202020202020000000000000000009D +:1095C0000000000000000002020202020202020289 +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202020202020202020202024B +:109600000202020202020201000001010000010147 +:10961000010000010101010101010101010101013C +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010100010001010101010101010101EC +:1096700001010101010101010101010101010101DA +:1096800001010101010101010000000001010101CE +:1096900001010101010101020202020202020202B1 +:1096A000020202020202020202020202020202029A +:1096B000020202020202020000000000000000009C +:1096C0000000000000000002020202020202020288 +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020201000001010000010146 +:10971000010001010101010101010101010101013A +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010000000002020202C9 +:1097900002020202020202010000000101010101B5 +:1097A00001010101010101020202020202020202A0 +:1097B000020202000202020000000000000000009D +:1097C0000000000000000002020202020202020287 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020200000200020000000255 +:109800000202020202020201000001010000010145 +:109810000100010101010101010101010101010139 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101020000000202020202B5 +:1098A0000202020202020202020202020202020298 +:1098B0000202010001010201010101010101010196 +:1098C0000101010101010101010101010101010188 +:1098D000010101010101010202020202020202026F +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020200000200020000000254 +:109900000202020202020201000001010100010143 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101020002020101010101010101010195 +:1099C000010101010101010202020202020202027E +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020200000000000000000257 +:109A00000202020202020201000001010100010142 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD000010101010101010202020202020202026D +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020200000000000000000256 +:109B00000202020202020201000001010101010140 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE000010101010101010202020202020202025C +:109BF0000202020202020200000000000000000255 +:109C00000000020202020201000101010101010142 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF000010101010101010000000000000000005D +:109D00000000000202020201000101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF000010101010101010000000000000000005C +:109E00000000000202020201010101010101010141 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF000010101010101010000000000000000005B +:109F00000000000000020201010101010101010144 +:109F1000010101010101010000000000000000003A +:109F20000000000000000000000000000000000031 +:109F3000000000000000000202020202020202020F +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202020202020202E1 +:109F600002020202020202020202020202020202D1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020202A1 +:109FA0000202020202020202020202020202020291 +:109FB0000202020202020202020202020202020281 +:109FC0000202020202020202020202020202020271 +:109FD0000202020202020202020202020202020261 +:109FE0000202020202020202020202020202020251 +:109FF0000202020202020200000000000000000053 +:10A000000000000000020201010101010101010143 +:10A010000101010101010100000000000000000039 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000020202020202020202DE +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020202A0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020280 +:10A0C0000202020202020202020202020202020270 +:10A0D0000202020202020202020202020202020260 +:10A0E0000202020202020202020202020202020250 +:10A0F0000202020202020200000000000000000052 +:10A100000000000000020201010101010101010142 +:10A110000101010101010100000000000000000038 +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000202020202020202028D +:10A1C000020202020202020202020202020202026F +:10A1D000020202020202020202020202020202025F +:10A1E000020202020202020202020202020202024F +:10A1F0000202020202020200000000000000000051 +:10A20000000000000000020000000000000000004C +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A300000000000000000038A30D00000000004025 +:10A310003C0E000000000048C40E00000000005089 +:10A320002A0F0000000000588F0F0000000000609E +:10A33000E30F000000000068211000000000007022 +:10A340005C10000000000078931000000000008006 +:10A35000C610000000000088F91000000000009006 +:10A3600037110000000000988A110000000000A0D2 +:10A37000DD11000000000099000000000000000056 +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000010001010100A9 +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000010B +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000001000100010001000000000000D8 +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000010001010100A8 +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000001008B +:10A4D000000000000000000000000000010000007B +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000010A +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000001000100010101000000010000D5 +:10A5800000000000000000000000000000010000CA +:10A5900001000000000000000100000000010100B7 +:10A5A00000000000000000000000010001010100A7 +:10A5B000000000000000000000000001000000009A +:10A5C0000000000000000000000000010000010089 +:10A5D000000000000000000000000000010000007A +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A640000000000000000000000000000000000109 +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000001000100010101000100010000D3 +:10A6800000000000000000000000000000010000C9 +:10A6900001000000000000000100000000010100B6 +:10A6A00000000000000001000000010001010100A5 +:10A6B0000000000000000000000000010100010097 +:10A6C0000000000000000000000000010100010087 +:10A6D0000000000000000000000000000100010078 +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000010028 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000108 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700001000001000100010101000100010000D1 +:10A7800001000000000000000000000000010001C6 +:10A7900001000000000000000100000000010100B5 +:10A7A00000000000000001000000010001010100A4 +:10A7B0000000000000000000000000010100010096 +:10A7C0000000000000000000000000010100010086 +:10A7D0000000000000000000000000000100010077 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000010027 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000107 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700001010001000101010101000100010000CE +:10A8800001000000000100000000000000010001C4 +:10A8900001000000000000000100000000010100B4 +:10A8A00000000000000001000000010101010101A1 +:10A8B0000100000000000000000000010101010093 +:10A8C0000000000000000000000000010100010085 +:10A8D0000000000000000000000000000100010076 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000010057 +:10A900000000000000000000010000000000010045 +:10A910000000000000000000000000000000010036 +:10A920000000000000000000000000000000010026 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000106 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700001010001000101010101010100010000CC +:10A9800001000000000100000000000000010001C3 +:10A9900001000000000000000100000000010100B3 +:10A9A00000000000000001000000010101010101A0 +:10A9B0000100000000000000000000010101010092 +:10A9C0000000000000000000000000010100010084 +:10A9D0000000000000000000000000000100010075 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000010056 +:10AA00000000000000000000010000000000010044 +:10AA10000000000000000000000000000000010035 +:10AA20000000000000000000000000000000010025 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000105 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700001010001000101010101010100010000CB +:10AA800001000000000100000000000000010001C2 +:10AA900001000000000000000100000000010100B2 +:10AAA000000000000000010000000101010101019F +:10AAB0000100000000000000000000010101010091 +:10AAC0000000000000000000000001010101010081 +:10AAD0000000000000000000000000000100010074 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000010055 +:10AB00000000000000000000010000000000010043 +:10AB10000000000000000000000000000000010034 +:10AB20000000000000000000000000000000010024 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000104 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700001010001000101010101010101010000C9 +:10AB800001000000000100000000000000010001C1 +:10AB900001000000000000000100000001010100B0 +:10ABA000010000000000010000000101010101019D +:10ABB000010000000001010000000001010101008E +:10ABC000000001000000000000000101010101007F +:10ABD0000000000001000000000000000100010072 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000010054 +:10AC00000000000000000000010000000000010042 +:10AC10000000000000000000000000000000010033 +:10AC20000000000000000000000000000000010023 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000103 +:10AC500000000000000000000000000000000100F3 +:10AC600000000000000000000000000000000000E4 +:10AC700001010101010101010101010101010000C6 +:10AC800001000000000100000000000000010001C0 +:10AC900001000000000000000100000001010100AF +:10ACA000010000000000010000000101010101019C +:10ACB000010000000001010000000001010101008D +:10ACC000000001000000000000000101010101017D +:10ACD0000000000001000000000001000100010070 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000010053 +:10AD00000000000000000000010000000000010041 +:10AD10000000000000000000000000000000010032 +:10AD20000000000000000000000000000000010022 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000010101 +:10AD500000000000000000000000000000000100F2 +:10AD600000000000000000000000000000000000E3 +:10AD700001010101010101010101010101010100C4 +:10AD800001000000000100000000000000010001BF +:10AD900001000000000000000100000001010100AE +:10ADA000010000000000010000000101010101019B +:10ADB000010000000001010000000001010101008C +:10ADC000000001000000000000000101010101017C +:10ADD000000000000100000000000101010001006E +:10ADE0000000000000000000000000000000010062 +:10ADF0000000000000000000000000000000010052 +:10AE00000000000000000000010000000000010040 +:10AE10000000000000000000000000000000010031 +:10AE20000000000000000000000000000000010021 +:10AE30000000000000000000000000000000010011 +:10AE40000000000000000000000000000000010100 +:10AE500000000000000000000000000000000100F1 +:10AE600000000000000000000000000000000000E2 +:10AE700001010101010101010101010101010100C3 +:10AE800001000000000100000000000000010001BE +:10AE900001000000000000000100000001010100AD +:10AEA000010000000000010000000101010101019A +:10AEB0000100000000010100000001010101010189 +:10AEC000000001000000000000000101010101017B +:10AED000000000000100000000000101010001006D +:10AEE0000000000000000000000000000000010061 +:10AEF0000000000000000000000000000000010051 +:10AF0000000000000000000001000000000001003F +:10AF10000000000000000000000000000000010030 +:10AF20000000000000000000000000000000010020 +:10AF30000000000000000000000000000000010010 +:10AF400000000000000000000000000000000101FF +:10AF500000000000000000000000000000000100F0 +:10AF600000000000000000000000000000000000E1 +:10AF700001010101010101010101010101010101C1 +:10AF800001000000000100000000000000010001BD +:10AF900001000000000000000100000001010100AC +:10AFA0000100000000000100010001010101010198 +:10AFB0000100000000010100000001010101010188 +:10AFC000000001000000000000000101010101017A +:10AFD000000000000100000000000101010001016B +:10AFE0000000000000000000000000000000010060 +:10AFF0000000000000000000000000000000010050 +:10B00000000000000000000001000000000001003E +:10B01000000000000000000000000000000001002F +:10B02000000000000000000000000000000001001F +:10B03000000000000000000000000000000001000F +:10B0400000000000000000000000000000000101FE +:10B0500000000000000000000000000000000100EF +:10B0600000000000000000000000000000000000E0 +:10B0700001010101010101010101010101010101C0 +:10B0800001000000000100000000000000010001BC +:10B0900001000101000000000100000001010100A9 +:10B0A0000100000000000100010001010101010197 +:10B0B0000100000000010100000001010101010187 +:10B0C0000000010000000000000001010101010179 +:10B0D000000000000100000000000101010001016A +:10B0E000000000000000000000000000000001005F +:10B0F000000000000000000000000000000001004F +:10B10000000000000000000001000000000001003D +:10B11000000000000000000000000000000001002E +:10B12000000000000000000000000000000101001D +:10B13000000000000000000000000000000001000E +:10B1400000000000000000000000000000000101FD +:10B1500000000000000000000000000000000100EE +:10B1600000000000000000000000000000000100DE +:10B1700001010101010101010101010101010101BF +:10B1800001000000000100000000000000010001BB +:10B1900001000101000000000100000001010101A7 +:10B1A0000100000000000100010001010101010196 +:10B1B0000100000000010101000001010101010185 +:10B1C0000000010000010000000001010101010177 +:10B1D0000000000001000000000001010100010169 +:10B1E000000000000000000000000000000101005D +:10B1F000000000000000000000000000000001004E +:10B20000000000000000000001000000000001003C +:10B21000000000000000000000000000000001002D +:10B22000000000000000000000000000000101001C +:10B23000000000000000000000000000000001000D +:10B2400000000000000000000000000000000101FC +:10B2500000000000000000000000000000000100ED +:10B2600000000000000000000000000000000100DD +:10B2700001010101010101010101010101010101BE +:10B2800001010000000100000000000000010001B9 +:10B2900001000101000000000100000001010101A6 +:10B2A0000100000000000100010001010101010195 +:10B2B0000100000000010101000001010101010184 +:10B2C0000000010000010000000001010101010176 +:10B2D0000000000001000000000001010100010168 +:10B2E000000000000000000000000000000101015B +:10B2F000000000000000000000000000000001004D +:10B30000000000000000000001000000000001003B +:10B31000000000000000000000000000000001002C +:10B32000000000000000000000000000000101001B +:10B33000000000000000000000000000000001000C +:10B3400000000000000000000000000000000101FB +:10B3500000000000000000000000000000000100EC +:10B3600000000000000000000000000000000100DC +:10B3700001010101010101010101010101010101BD +:10B3800001010000000100000000000000010001B8 +:10B3900001000101000000000100000001010101A5 +:10B3A0000100000000000100010001010101010194 +:10B3B0000100000000010101000001010101010183 +:10B3C0000000010000010000000001010101010175 +:10B3D0000000000001000000000001010100010167 +:10B3E0000100000000000000000000000001010159 +:10B3F000000000000000000000000000000001004C +:10B40000000000000000000001000000000001003A +:10B41000000000000000000000000000000001002B +:10B42000000000000000000000000000000101001A +:10B43000000000000000000000000000000001000B +:10B4400000000000000000000000000000000101FA +:10B4500000000000000000000000000000010100EA +:10B4600000000000000000000000000000000100DB +:10B4700001010101010101010101010101010101BC +:10B4800001010000000100000000000000010001B7 +:10B4900001000101000000000100000001010101A4 +:10B4A0000100000000000100010001010101010193 +:10B4B0000100000000010101000001010101010182 +:10B4C0000000010000010000000001010101010174 +:10B4D0000000000001000000000001010100010166 +:10B4E0000100000000000000000000010001010157 +:10B4F000000000000000000000000000000001004B +:10B500000000000000000000010000000000010039 +:10B510000000000000000000000000000000010129 +:10B520000000000000000000000000000001010019 +:10B53000000000000000000000000000000001000A +:10B5400000000000000000000000000000000101F9 +:10B5500000000000000000000000000000010100E9 +:10B5600000000000000000000000000000000100DA +:10B5700001010101010101010101010101010101BB +:10B5800001010000000100000000000000010001B6 +:10B5900001000101000000000100000001010101A3 +:10B5A0000100000000000100010001010101010192 +:10B5B0000100000000010101000001010101010181 +:10B5C0000000010000010100000001010101010172 +:10B5D0000000000001000000000001010100010165 +:10B5E0000100000000000000000000010101010155 +:10B5F000000000000000000000000000000001004A +:10B600000000000000000000010000000000010038 +:10B610000000000000000000000000000000010128 +:10B620000000000000000000000000000001010018 +:10B630000000000000000000000000000001010008 +:10B6400000000000000000000000000000000101F8 +:10B6500000000000000000000000000000010100E8 +:10B6600000000000000000000000000000000100D9 +:10B6700001010101010101010101010101010101BA +:10B6800001010000000100000000000000010001B5 +:10B6900002000101000000000100000001010101A1 +:10B6A0000100000000000100010001010101010191 +:10B6B0000100000000010101000001010101010180 +:10B6C0000100010000010100000001010101010170 +:10B6D0000000000001000000000001010100010164 +:10B6E0000100000000000000000000010101010154 +:10B6F0000000000000000000000000000000010049 +:10B700000000000000000000010000000001010036 +:10B710000000000000000000000000000001010126 +:10B720000000000000000000000000000001010017 +:10B730000000000000000000000000000001010007 +:10B7400000000000000000000000000000010101F6 +:10B7500000000000000000000000000000010100E7 +:10B7600000000000000000000000000000000100D8 +:10B7700001010101010101010101010101010101B9 +:10B7800001010000000100000000000000010002B3 +:10B7900002000101000000000100000001010101A0 +:10B7A0000100000000000100010001010101010190 +:10B7B000010000000001010100000101010101017F +:10B7C000010001000001010000000101010101016F +:10B7D0000000010001000000000101010100010161 +:10B7E0000100000000000000000000010101010153 +:10B7F0000000000000000000000000000000010048 +:10B800000000000000000000010000000001010035 +:10B810000000000000000000000000000001010125 +:10B820000000000000000000000000000001010016 +:10B830000000000000000000000000000001010006 +:10B8400000000000000000000000000000010101F5 +:10B8500000000000000000000000000000010100E6 +:10B8600000000000000000000000000000000100D7 +:10B8700001010101010101010101010101010101B8 +:10B8800001010000000100000000000000010002B2 +:10B89000020001010000000001000000010101019F +:10B8A000010000000000010001000101010101018F +:10B8B000010000000001010100000101010101017E +:10B8C000010001000001010000000101010101016E +:10B8D0000000010001000000000101010100010160 +:10B8E0000100000000010000000000010101010151 +:10B8F0000000000000000000000000000100010046 +:10B900000000000000000000010000000001010034 +:10B910000000000000000000000000000001010124 +:10B920000000000000000000000000000001010015 +:10B930000000000000000000000000000001010005 +:10B9400000000000000000000000000000010101F4 +:10B9500000000000000000000000000100010100E4 +:10B9600000000000000000000000000000000100D6 +:10B9700001010101010101010101010101010101B7 +:10B9800001010000000100000000000000010002B1 +:10B99000020001010000000001000000010101019E +:10B9A000010000000000010001000101010101018E +:10B9B000010100000001010100000101010101017C +:10B9C000010001000001010000000101010101016D +:10B9D000000001000100000000010101010001015F +:10B9E0000100000000010000000000010101010150 +:10B9F0000000000000000000000000000100010045 +:10BA00000000000000000000010000000001010033 +:10BA10000000000000000000000000000001010123 +:10BA20000000000000000000000000010001010013 +:10BA30000000000000000000000000000001010004 +:10BA400000000000000000000000000000010101F3 +:10BA500000000000000000000000010100010100E2 +:10BA600000000000000000000000000000000100D5 +:10BA700001010101010101010101010101010101B6 +:10BA800001010000000100000001000000010002AF +:10BA9000020001010000000001000000010101019D +:10BAA000010000000000010001000101010101018D +:10BAB000010100000001010100000101010101017B +:10BAC000010001000001010000000101010101016C +:10BAD000000001000100000000010101010101015D +:10BAE000010000000001000000000001010101014F +:10BAF0000000000000000000000000000101010043 +:10BB00000000000000000000010000000101010031 +:10BB10000000000000000000000000000001010122 +:10BB20000000000000000000000000010001010012 +:10BB30000000000000000000000000000001010003 +:10BB400000000000000000000000000000010101F2 +:10BB500000000000000000000000010100010100E1 +:10BB600000000000000000000000000000010100D3 +:10BB700001010101010101010101010101010101B5 +:10BB800002010000000100000001000000010002AD +:10BB9000020001010000000001000000010101019C +:10BBA000010000000000010001000101010101028B +:10BBB000010100000001010100000101010101017A +:10BBC000010001000001010000000101010101016B +:10BBD000000001000100000000010101010101015C +:10BBE000010000000001000000000001010101014E +:10BBF0000000000000000000000000010101010041 +:10BC00000000000000000000010000000101010030 +:10BC10000000000000000000000000010001010120 +:10BC20000000000000000000000000010001010011 +:10BC30000000000000000000000000000001010002 +:10BC400000000000000000000000000100010101F0 +:10BC500000000000000000000000010101010100DF +:10BC600000000000000000000000000100010100D1 +:10BC700001010101010101010101010101010101B4 +:10BC800002010000000100000001000000010002AC +:10BC9000020101010000000001000000010101019A +:10BCA000010000000000010001000101010101028A +:10BCB0000101000000010101000001010101010179 +:10BCC000010001000001010000000101010101016A +:10BCD000000001000100000000010101010101015B +:10BCE000010000000001000000000001010101014D +:10BCF0000000000000000000000000010101010040 +:10BD0000000000000000000001000000010101002F +:10BD1000000000000000000000000001000101011F +:10BD2000000000000000000000000101000101000F +:10BD30000000000000000000000000010001010000 +:10BD400000000000000000000000000100010101EF +:10BD500000000000000000000000010101010100DE +:10BD600000000000000000000000000101010100CF +:10BD700001010101010101010101010101010102B2 +:10BD800002010000000100000001000000010002AB +:10BD90000201010100000000010000000101010199 +:10BDA0000100000000000100010001010101010289 +:10BDB0000101000000010101000001010101010178 +:10BDC0000100010000010100000001010101010169 +:10BDD000000001000100000000010101010101015A +:10BDE000010000000001000000000001010101014C +:10BDF000000000000000000000000001010101003F +:10BE0000000000010000000001000001010101002C +:10BE1000000000000000000000000001000101011E +:10BE2000000000000000000000000101000101000E +:10BE300000000000000000000000000100010100FF +:10BE400000000000000000000000000100010101EE +:10BE500000000000000000000000010101010100DD +:10BE600000000000000000000000000101010100CE +:10BE700001010101010101010101010101010102B1 +:10BE800002010000000100000001000000010002AA +:10BE90000201010100000000010000000101010198 +:10BEA0000100000000000100010001010101010288 +:10BEB0000201000000010101000001010101010176 +:10BEC0000100010000010100000001010101010168 +:10BED0000000010001000000000101010101010159 +:10BEE000010000000001000000000001010101014B +:10BEF000000000000000000000000001010101003E +:10BF0000000000010000000001000001010101002B +:10BF1000000000000000000000000001000101011D +:10BF2000000000000000000000000101000101000D +:10BF300000000000000000000000000100010100FE +:10BF400000000000000000000000010100010101EC +:10BF500000000000000000000000010101010100DC +:10BF600000000000000000000000000101010100CD +:10BF700001010101010101010101010101010102B0 +:10BF800002010000000100000001000000010002A9 +:10BF90000201010100000000010000000101010197 +:10BFA0000100000000000100010001010101010287 +:10BFB0000201000000010101000001010101010175 +:10BFC0000100010000010100000001010101010167 +:10BFD0000000010001000000000101010101010158 +:10BFE000010000000001000000000001010101014A +:10BFF000000000000000000000000001010101003D +:10C00000000000010000000001000001010101002A +:10C01000000000000000000000000001000101011C +:10C02000000000000000000000010101000101000B +:10C0300000000000000000000000010100010100FC +:10C0400000000000000000000000010100010101EB +:10C0500000000000000000000000010101010100DB +:10C0600000000000000000000000000101010100CC +:10C0700001010101010101010101010101010102AF +:10C0800002010000000100000001000000010002A8 +:10C090000201010100010000010000000101010195 +:10C0A0000100000000000100010001010101010286 +:10C0B0000201000000010101000001010101010174 +:10C0C0000100010000010100000001010101010166 +:10C0D0000100010001000000000101010101010156 +:10C0E0000100000000010000000000010101010149 +:10C0F000000000000000000000000001010101013B +:10C100000000000100000000010000010101010029 +:10C11000000000000000000000000101000101011A +:10C12000000000000000000000010101000101000A +:10C1300000000000000000000000010100010100FB +:10C1400000000000000000000000010100010101EA +:10C1500000000000000000000001010101010100D9 +:10C1600000000000000000000000010101010100CA +:10C1700001010101010101010101010101010102AE +:10C1800002010000000100000001000000010002A7 +:10C190000201020100010000020000000101010192 +:10C1A0000200000000000100010001010101010284 +:10C1B0000201000000010101000001010101010173 +:10C1C0000100010000010100000001010101010165 +:10C1D0000100010001000000000101010101010155 +:10C1E0000100000000010000000000010101010148 +:10C1F000000000000000000000000001010101013A +:10C200000001000100000000010000010101010027 +:10C210000000000000000000000001010001010119 +:10C220000000000000000000000101010001010009 +:10C2300000000000000000000000010100010100FA +:10C2400000000000000000000001010100010101E8 +:10C2500000000000000000000001010101010100D8 +:10C2600000000000000000000001010101010100C8 +:10C2700001010101010101010101010101010102AD +:10C2800002010000000100000001000000010002A6 +:10C29000020102020001000002000000010101028F +:10C2A0000200010000000100010001010101010282 +:10C2B0000201000000010101000001010101010271 +:10C2C0000100010000010100000001010101010263 +:10C2D0000100010001000000000101010101010154 +:10C2E0000100000000010000000000010101010147 +:10C2F0000000000000000000000000010101010139 +:10C300000001000100000000010001010101010025 +:10C310000000000000000000000001010001010118 +:10C320000000000000000000000101010101010007 +:10C3300000000000000000000000010100010100F9 +:10C3400000000000000000000001010101010101E6 +:10C3500000000000000000000001010101010100D7 +:10C3600000000000000000000001010101010100C7 +:10C3700001010101010101010101010101010102AC +:10C3800002010000000100000001000000010002A5 +:10C39000020102020001000002000000010101028E +:10C3A0000200010000000100010001010101010281 +:10C3B0000201000000010101000001010101010270 +:10C3C0000100010101010100000001010101010260 +:10C3D0000100010001000001000101010101010152 +:10C3E0000100000000010000000000010101010146 +:10C3F0000000000000000000000000010101010138 +:10C400000001000100000000010001010101010024 +:10C410000000000000000000000001010001010117 +:10C420000000000000000000000101010101010105 +:10C4300000000000000000000000010100010100F8 +:10C4400000000000000000000001010101010101E5 +:10C4500000000000000000000001010101010100D6 +:10C4600000000000000000000001010101010100C6 +:10C4700001010101010101010101010101010102AB +:10C4800002020000000200000001000000010002A2 +:10C49000020102020001000002000000010101028D +:10C4A0000200010000000100010001010101010280 +:10C4B000020100000001010100000101010101026F +:10C4C000010001010101010000000101010101025F +:10C4D0000100010001000001000101010101010250 +:10C4E0000100000000010000000100010101010144 +:10C4F0000100000000000000000000010101010136 +:10C500000001000100000000010001010101010122 +:10C510000000000000000000000001010001010116 +:10C520000000000000000000000101010101010104 +:10C5300000000000000000000001010100010101F5 +:10C5400000000000000000000001010101010101E4 +:10C5500000000000000100000001010101010100D4 +:10C5600000000000000000000101010101010100C4 +:10C5700001010101010101010101010101010102AA +:10C5800002020000000200000001000000010002A1 +:10C59000020202020001000002000000010101028B +:10C5A000020001000000010001000101010101027F +:10C5B000020101000001010100000101010101026D +:10C5C000010001010101010000000101010101025E +:10C5D000010001000100000100010101010101024F +:10C5E0000100000000010000010100010101010142 +:10C5F0000100000000000000000000010101010135 +:10C600000001000100000000010001010101010121 +:10C610000000000000000000000001010001010115 +:10C620000000000000000000000101010101010103 +:10C6300000000000000000000001010100010101F4 +:10C6400000000000000000000001010101010101E3 +:10C6500000000000000100000101010101010100D2 +:10C6600000000000000100000101010101010100C2 +:10C6700001010101010101010101010101010102A9 +:10C6800002020000000200000001000000010002A0 +:10C69000020202020001000002000000010101028A +:10C6A000020101000000020001000101010101027C +:10C6B000020101000001010100000101010101026C +:10C6C000010002010101010000000101010101025C +:10C6D000010001000100000100010101010101024E +:10C6E0000100000000010000010100010101010141 +:10C6F0000100000000000000000000010101010134 +:10C70000010100010000000001000101010101011F +:10C710000000000000000000000001010001010114 +:10C720000000000000000000000101010101010102 +:10C7300000000000000000000001010100010101F3 +:10C7400000000000000000000001010101010101E2 +:10C7500000000000000100000101010101010100D1 +:10C7600000000000000100000101010101010100C1 +:10C7700001010101010101010101010101010102A8 +:10C78000020200000002000000010000000100029F +:10C790000202020200010000020000000101010289 +:10C7A000020101000000020001000101010101027B +:10C7B000020101010001010100000101010101026A +:10C7C000010002010101010000000101010101025B +:10C7D000010101000100000100010101010101024C +:10C7E0000100000000010000010100010101010140 +:10C7F0000100000000000000000000010101010133 +:10C80000010100010000000001010101010101011D +:10C810000000000000000000000001010001010113 +:10C820000000000000000001000101010101010100 +:10C8300000000000000000000001010101010101F1 +:10C8400000000000000100000001010101010101E0 +:10C8500000000000000100000101010101010100D0 +:10C8600000000000000101010101010101010100BE +:10C8700001010101010101010101010101010102A7 +:10C88000020200000002000000010000000100029E +:10C890000202020200010000020000000101010288 +:10C8A000020101000000020001000101010101027A +:10C8B0000201010100010201000001010101010268 +:10C8C000010002010101010000000101010101025A +:10C8D000010101000100000100010101010101024B +:10C8E000020000000001000001010001010101013E +:10C8F0000100000000000000000001010101010131 +:10C90000010100010000000001010101010101011C +:10C910000000000000000000000001010001010112 +:10C9200000000000000000010101010101010101FE +:10C9300000000000000000000001010101010101F0 +:10C9400000000000000100000101010101010101DE +:10C9500000000000000101010101010101010100CD +:10C9600000000000000101010101010101010100BD +:10C9700001010101010101010101010101010102A6 +:10C98000020200000002000000010000000100029D +:10C990000202020200010000020000000101010287 +:10C9A0000201010000000200010001010101010279 +:10C9B0000201010100020201000001010101010266 +:10C9C0000201020101010100000001010101010257 +:10C9D000010101000100000100010101010101024A +:10C9E000020000000001000001010101010101023B +:10C9F0000100000000000000000001010101010130 +:10CA0000010100010000000001010101010101011B +:10CA10000000000000000000000101010001010110 +:10CA200000000000000100010101010101010101FC +:10CA300000000000000000000101010101010101EE +:10CA400000000000000100000101010101010102DC +:10CA500000000000000101010101010101010100CC +:10CA600000000000000101010101010101010100BC +:10CA700001010101010101010101010101010102A5 +:10CA8000020200000002000000010000000100029C +:10CA90000202020200010000020000000101010286 +:10CAA0000201010000000200010001010101010278 +:10CAB0000202010100020202000001010101010263 +:10CAC0000201020101010100000001010101010256 +:10CAD0000101010002000001000101010101010248 +:10CAE000020000000001000001010101010101023A +:10CAF000010000000000000000000101010101012F +:10CB0000010100010000000001010101010101011A +:10CB1000000000000000000000010101000101010F +:10CB200001000000000100010101010101010101FA +:10CB300000000000000000000101010101010101ED +:10CB400000000000000100000101010101010102DB +:10CB500000000000000101010101010101010100CB +:10CB600000000000000101010101010101010100BB +:10CB700001010101010101010101010101010102A4 +:10CB8000020200000002000000010000000100029B +:10CB90000202020200010000020000000101010285 +:10CBA0000201010000000200010001010101010277 +:10CBB0000202010100020202000001010101010262 +:10CBC0000201020101010100000001010101010255 +:10CBD0000101010002000001000101010101010247 +:10CBE0000200000000010000010101010101010239 +:10CBF000010000000000000000010101010101012D +:10CC00000101000100000000010101010101010119 +:10CC1000000000000000000000010101000101010E +:10CC200001000000000100010101010101010101F9 +:10CC300000000000000000000101010101010101EC +:10CC400000000000000101010101010101010102D8 +:10CC500000000000000101010101010101010100CA +:10CC600000000000010101010101010101010100B9 +:10CC700001010101010101010101010101010102A3 +:10CC8000020200000002000000010000000100029A +:10CC90000202020200010000020000000202010282 +:10CCA0000201010000000200010002010101010275 +:10CCB0000202010100020202000001010201010260 +:10CCC0000201020101010100000001010101010254 +:10CCD0000101010002000001000101010101010246 +:10CCE0000200000000010100010101010101010237 +:10CCF000010000000000000000010101010101012C +:10CD00000101000100000000010101010101010118 +:10CD1000000000000000000000010101010101010C +:10CD200001000000000100010101010101010101F8 +:10CD300000000000000100000101010101010101EA +:10CD400000000000000101010101010101010102D7 +:10CD500000000000000101010101010101010101C8 +:10CD600000000000010101010101010101010100B8 +:10CD700001010101010101010101010101010102A2 +:10CD80000202000000020000000100000001000299 +:10CD90000202020200010000020000000202010281 +:10CDA0000201010000000200010002010201010273 +:10CDB000020201010002020200000102020101025E +:10CDC0000201020101010100000001010101010253 +:10CDD0000101010102000001000101010101010244 +:10CDE0000200000000010100010101010101010236 +:10CDF000010001000000000000010101010101012A +:10CE00000101010100010000010101010101010115 +:10CE1000000000000000000000010101010101010B +:10CE200001010000000101010101010101010101F5 +:10CE300000000000000100000101010101010101E9 +:10CE400000000000000101010101010101010102D6 +:10CE500000000000000101010101010101010101C7 +:10CE600000000100010101010101010101010100B6 +:10CE700001010101010101010101010101010102A1 +:10CE80000202010000020000000100000001000297 +:10CE90000202020200010000020000000202010280 +:10CEA0000201010000000200020002010201010271 +:10CEB000020201010002020200000102020101025D +:10CEC0000201020101010100000001010101010252 +:10CED0000101010102000001000101010101010243 +:10CEE0000200000000010100010101010101010235 +:10CEF0000100010000000000000101010101010129 +:10CF00000101010100010000010101010101010114 +:10CF10000100000000000000000101010101010208 +:10CF200001010000000101010101010101010101F4 +:10CF300000000000000100010101010101010101E7 +:10CF400000000000000101010101010101010102D5 +:10CF500000000100010101010101010101010101C4 +:10CF600000000100010101010101010101010100B5 +:10CF7000020101010101010101010101010101029F +:10CF80000202010000020000000100000002000295 +:10CF9000020202020001000002000000020201027F +:10CFA0000201010000000200020002010201010270 +:10CFB000020201010002020200000102020101025C +:10CFC0000201020101020100000001010101010250 +:10CFD0000101020102000001000101010101010241 +:10CFE0000200000000010100010101010101010234 +:10CFF0000101010000010000000101010101010126 +:10D000000101010100010000010101010101010113 +:10D010000100000000010000000101010101010206 +:10D0200001010101010101010101010101010101F0 +:10D0300000000000000100010101010101010101E6 +:10D0400000000100000101010101010101010102D3 +:10D0500000000100010101010101010101010101C3 +:10D0600000010101010101010101010101010100B2 +:10D07000020101010101010101010101010101029E +:10D080000202010000020000000100000002000294 +:10D09000020202020002000002000000020202027C +:10D0A000020101000000020002000202020201026D +:10D0B000020201010002020200000202020101025A +:10D0C000020102010102020000000101010101024E +:10D0D000020102010200000100010101010101023F +:10D0E0000201000000010100010101010101010232 +:10D0F0000101010000010000000101010101010125 +:10D100000101010100010000010101010101010112 +:10D110000100000000010000000101010101010205 +:10D1200001010101010101010101010101010101EF +:10D1300000000100000100010101010101010101E4 +:10D1400001000100000101010101010101010102D1 +:10D1500000000101010101010101010101010101C1 +:10D1600000010101010101010101010101010100B1 +:10D17000020101010101010101010101010101029D +:10D180000202010000020000000100000002000293 +:10D19000020202020002000002000000020202027B +:10D1A000020101000000020002000202020201026C +:10D1B0000202010100020202000002020201010259 +:10D1C000020102010102020000000202020101024A +:10D1D000020102010200000100010101020101023D +:10D1E0000201000000010100010101010101010231 +:10D1F0000101010000010000000101010101010124 +:10D200000101010101010000010101010101010110 +:10D210000101010000010000000101010101010202 +:10D2200001010101010101010101010101010101EE +:10D2300001000100000100010101010101010101E2 +:10D2400001000100010101010101010101010102CF +:10D2500000000101010101010101010101010101C0 +:10D2600000010101010101010101010101010100B0 +:10D27000020101010101010101010101010101029C +:10D280000202010000020000000100000002000292 +:10D29000020202020002000002000000020202027A +:10D2A0000202020000000200020002020202010269 +:10D2B0000202020100020202000002020202010256 +:10D2C0000201020101020200000002020201010249 +:10D2D000020102010200000100010101020101023C +:10D2E0000201000000010100010101010101010230 +:10D2F0000101010000010000000101010101010123 +:10D30000010101010101000001010101010101010F +:10D310000101010000010000000101010101010201 +:10D3200001010101010101010101010101010101ED +:10D3300001010100000101010101010101010101DF +:10D3400001000100010101010101010101010102CE +:10D3500000010101010101010101010101010101BE +:10D3600001010101010101010101010101010100AE +:10D37000020201010101010101010101010101029A +:10D380000202010000020000000100000002000291 +:10D390000202020200020000020000000202020279 +:10D3A0000202020000000200020002020202010268 +:10D3B0000202020100020202000002020202010255 +:10D3C0000201020101020200000002020201010248 +:10D3D000020102010200000100010101020101023B +:10D3E000020100000001010001010101010101022F +:10D3F0000101010100010000000101010101010220 +:10D40000010101010101000001010101010101010E +:10D4100001010101010100010001010101010102FD +:10D4200001010101010101010101010101010101EC +:10D4300001010100000101010101010101010101DE +:10D4400001010101010101010101010101010102CB +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010100AD +:10D470000202010201010101010101010101010298 +:10D48000020202000002000000010000000200028F +:10D490000202020200020000020000000202020278 +:10D4A0000202020000000200020002020202010267 +:10D4B0000202020200020202000002020202010253 +:10D4C0000201020201020200000002020201010246 +:10D4D000020102010200000100010101020101023A +:10D4E000020101000001010101010101010101022C +:10D4F000010101010001000000010101010101021F +:10D50000010101010101000001010101010101010D +:10D5100001010101010100010101010101010102FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010102CA +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010100AC +:10D570000202010201010101010101010101010297 +:10D58000020202000002000000020000000200028D +:10D590000202020200020000020000000202020277 +:10D5A0000202020000000200020002020202010266 +:10D5B0000202020200020202000002020202010252 +:10D5C0000201020201020200000002020201010245 +:10D5D0000201020102000001000102010201010238 +:10D5E000020101000001010101010101010101022B +:10D5F000010101010001000000010101010101021E +:10D60000010101010101000002010101010101010B +:10D6100001010101010101010101010101010102F9 +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010102C9 +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010100AB +:10D670000202010201010101010101010101010296 +:10D68000020202000002000000020000000200028C +:10D690000202020200020000020000000202020276 +:10D6A0000202020100000200020002020202010264 +:10D6B0000202020200020202000002020202010251 +:10D6C0000202020201020200000002020201010243 +:10D6D0000201020102000001000102010201010237 +:10D6E0000201010101020101010101010101010227 +:10D6F000010101010001000000010101010101021D +:10D70000010101010101000002010101010101010A +:10D7100001010101010101010101010101010102F8 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010102C8 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010100AA +:10D770000202010201010101010101010101010295 +:10D78000020202000002000000020000000200028B +:10D790000202020200020000020000000202020275 +:10D7A0000202020100000200020002020202020262 +:10D7B000020202020002020200000202020202024F +:10D7C0000202020202020200000002020201010241 +:10D7D0000202020102000001000102010201010235 +:10D7E0000201010101020101010101010101010226 +:10D7F000020101010001000000010101010101021B +:10D800000101010101010000020101010101010109 +:10D8100001010101010101010101010101010102F7 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010102C7 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010100A9 +:10D870000202020201010101010101010101010293 +:10D88000020202000002000000020000000200028A +:10D890000202020201020000020000000202020273 +:10D8A0000202020100000200020002020202020261 +:10D8B000020202020002020200000202020202024E +:10D8C000020202020202020000000202020201023F +:10D8D0000202020102000001000102020201010233 +:10D8E0000201010101020101010101010101010225 +:10D8F000020101010001000000010101010101021A +:10D900000102010201010000020101010101010205 +:10D9100001010101010101010101010101010102F6 +:10D9200001010101010101010101010101010102E6 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010102C6 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010100A8 +:10D970000202020201010101010101010101010292 +:10D980000202020000020000000200000002000289 +:10D990000202020202020000020000000202020271 +:10D9A0000202020100000200020002020202020260 +:10D9B000020202020002020200000202020202024D +:10D9C000020202020202020000000202020201023E +:10D9D0000202020102000001000202020201010231 +:10D9E0000201010101020101010101010101010224 +:10D9F0000201010100010100000101010101010218 +:10DA00000202010201010000020101010101010203 +:10DA100001010101010101010101010101010102F5 +:10DA200001010101010101010101010101010102E5 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010102C5 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010100A7 +:10DA70000202020201010101010101010101010291 +:10DA80000202020100020000000200000002000287 +:10DA90000202020202020000020000000202020270 +:10DAA000020202010000020002000202020202025F +:10DAB000020202020002020200000202020202024C +:10DAC000020202020202020000000202020202023C +:10DAD0000202020102000001000202020201010230 +:10DAE0000201010101020101010101010101010223 +:10DAF0000201010100010100000101010101010217 +:10DB00000202010201010000020101010101010202 +:10DB100001010101010101010101010101010102F4 +:10DB200001010101010101010101010101010102E4 +:10DB300001010101010101010101010101010102D4 +:10DB400001010101010101010101010101010102C4 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010100A6 +:10DB7000020202020102010201010101010101028E +:10DB80000202020200020000000200000002000285 +:10DB9000020202020202000002000000020202026F +:10DBA000020202010000020002000202020202025E +:10DBB000020202020002020200000202020202024B +:10DBC000020202020202020000000202020202023B +:10DBD000020202010200000100020202020101022F +:10DBE0000201010101020101010101010101010222 +:10DBF0000201010101010100000101010101010215 +:10DC000002020102010101010201010101010102FF +:10DC100001010101010101010101010101010102F3 +:10DC200001010101010101010101010101010102E3 +:10DC300001010101010101010101010101010102D3 +:10DC400001010101010101010101010101010102C3 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010100A5 +:10DC7000020202020202010201010101010101028C +:10DC80000202020200020000000200000002000284 +:10DC9000020202020202000002000000020202026E +:10DCA000020202010000020002000202020202025D +:10DCB000020202020002020200000202020202024A +:10DCC000020202020202020000000202020202023A +:10DCD000020202010200000200020202020101022D +:10DCE0000201010101020101010101010101010221 +:10DCF0000201010101010100010101010101010213 +:10DD000002020102010101010201010101010102FE +:10DD100001010101010101010101010101010102F2 +:10DD200001010101010101010101010101010102E2 +:10DD300001010101010101010101010101010102D2 +:10DD400001010101010101010101010101010102C2 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010100A4 +:10DD70000202020202020202020101010101010289 +:10DD80000202020200020000000200000002000283 +:10DD9000020202020202000002000000020202026D +:10DDA000020202020000020002000202020202025B +:10DDB0000202020200020202000002020202020249 +:10DDC0000202020202020200000002020202020239 +:10DDD000020202020200000200020202020102022A +:10DDE000020201010102010101010102020101021D +:10DDF0000201010101010100010101010101010212 +:10DE000002020102010101010201010101010102FD +:10DE100001010101010101010101010101010102F1 +:10DE200001010101010101010101010101010102E1 +:10DE300001010101010101010101010101010102D1 +:10DE400001010101010101010101010101010102C1 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010100A3 +:10DE70000202020202020202020101010101010288 +:10DE80000202020201020000000200000002000281 +:10DE9000020202020202000002000000020202026C +:10DEA000020202020000020002000202020202025A +:10DEB0000202020200020202000002020202020248 +:10DEC0000202020202020200000002020202020238 +:10DED0000202020202000002000202020201020229 +:10DEE000020201010102010101010102020101021C +:10DEF0000201010101010100010101010101010211 +:10DF000002020102010101010201010101010102FC +:10DF100001010101010101010101010101010102F0 +:10DF200001010101010101010101010101010102E0 +:10DF300001010101010101010101010101010102D0 +:10DF400001010101010101010101010101010102C0 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010100A2 +:10DF70000202020202020202020201010101010286 +:10DF80000202020201020000000200000002000280 +:10DF9000020202020202000002000000020202026B +:10DFA0000202020200000200020002020202020259 +:10DFB0000202020200020202000002020202020247 +:10DFC0000202020202020200000002020202020237 +:10DFD0000202020202000002000202020201020228 +:10DFE000020201010102010101010102020201021A +:10DFF0000201010101010100010101010101010210 +:10E0000002020102010101010201010101010102FB +:10E0100001010101010101010101010101010102EF +:10E0200002010101010101010101010101010102DE +:10E0300001010101010101010101010101010102CF +:10E0400001010101010101010101010101010102BF +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010100A1 +:10E070000202020202020202020201010101010285 +:10E08000020202020202000000020000000200027E +:10E090000202020202020200020000000202020268 +:10E0A0000202020200000200020002020202020258 +:10E0B0000202020200020202000002020202020246 +:10E0C0000202020202020200000002020202020236 +:10E0D0000202020202000002000202020201020227 +:10E0E0000202010101020101020101020202010218 +:10E0F000020201010101010001010101010101020E +:10E1000002020102010101010201010101010102FA +:10E1100001010101010101010101010101010102EE +:10E1200002010101010101010101010101010102DD +:10E1300001010101010101010101010101010102CE +:10E1400001010101010101010101010101010102BE +:10E1500001010101010101010101010101010101AF +:10E1600001010101010101010101010101010100A0 +:10E170000202020202020202020201010101010284 +:10E18000020202020202000000020000000200027D +:10E190000202020202020200020000000202020267 +:10E1A0000202020200000200020002020202020257 +:10E1B0000202020200020202000002020202020245 +:10E1C0000202020202020200000002020202020235 +:10E1D0000202020202000002000202020201020226 +:10E1E0000202020101020201020101020202010215 +:10E1F000020202010101010101010101010101020B +:10E2000002020102010101010201010101010102F9 +:10E2100002010101010101010101010101010102EC +:10E2200002010101010101010101010101010102DC +:10E2300001010101010101010101010101010102CD +:10E2400001010101010101010101010101010102BD +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101009F +:10E270000202020202020202020201010101010283 +:10E28000020202020202010000020000000200027B +:10E290000202020202020202020000000202020264 +:10E2A0000202020200000200020002020202020256 +:10E2B0000202020200020202000002020202020244 +:10E2C0000202020202020200000002020202020234 +:10E2D0000202020202000002000202020201020225 +:10E2E0000202020101020201020201020202020212 +:10E2F0000202020101010101010101010201010209 +:10E3000002020202010101010201010101010102F7 +:10E3100002010101010101010101010101010102EB +:10E3200002010101010101010101010101010102DB +:10E3300001010101010101010101010101010102CC +:10E3400001010101010101010101010101010102BC +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101009E +:10E370000202020202020202020201020101010281 +:10E38000020202020202010000020000000200027A +:10E390000202020202020202020001000202020262 +:10E3A0000202020200000200020002020202020255 +:10E3B0000202020200020202000002020202020243 +:10E3C0000202020202020200000002020202020233 +:10E3D0000202020202000002000202020202020223 +:10E3E0000202020201020201020201020202020210 +:10E3F0000202020101010101010101010201020207 +:10E4000002020202010101010201010101010102F6 +:10E4100002010101010101010101010101010102EA +:10E4200002020101010101010101010101010102D9 +:10E4300001010101010101010101010101010102CB +:10E4400001010101010101010101010101010102BB +:10E4500001010101010101010101010101010102AB +:10E46000010101010101010101010101010101009D +:10E47000020202020202020202020202010101027F +:10E480000202020202020100000200000002000279 +:10E490000202020202020202020001000202020261 +:10E4A0000202020200000200020002020202020254 +:10E4B0000202020200020202000002020202020242 +:10E4C0000202020202020200000002020202020232 +:10E4D0000202020202000002000202020202020222 +:10E4E000020202020102020102020102020202020F +:10E4F0000202020101010101010101010201020206 +:10E5000002020202010101010201010101010202F4 +:10E5100002010101010101010101010101010102E9 +:10E5200002020101010101010101010101010102D8 +:10E5300002010101010101010101010101010102C9 +:10E5400001010101010101010101010101010102BA +:10E5500001010101010101010101010101010102AA +:10E56000010101010101010101010101010101009C +:10E57000020202020202020202020202010101027E +:10E580000202020202020200000200000002000277 +:10E590000202020202020202020001000202020260 +:10E5A0000202020200000200020002020202020253 +:10E5B0000202020201020202000002020202020240 +:10E5C0000202020202020200000002020202020231 +:10E5D0000202020202000002000202020202020221 +:10E5E000020202020202020102020102020202020D +:10E5F0000202020201010101010101020201020203 +:10E6000002020202010101010201010102010202F2 +:10E6100002010101010101010101010101010102E8 +:10E6200002020101010101010101010101010102D7 +:10E6300002010101010101010101010101010102C8 +:10E6400002010101010101010101010101010102B8 +:10E6500001010101010101010101010101010102A9 +:10E66000010101010101010101010101010101009B +:10E67000020202020202020202020202010201027C +:10E680000202020202020201000200000002000275 +:10E69000020202020202020202010100020202025E +:10E6A0000202020201010200020002020202020250 +:10E6B000020202020202020200000202020202023E +:10E6C0000202020202020200000002020202020230 +:10E6D0000202020202000002000202020202020220 +:10E6E000020202020202020102020202020202020B +:10E6F0000202020201010101010101020201020202 +:10E7000002020202010101010201010102010202F1 +:10E7100002020101010101010101010101010102E6 +:10E7200002020101010101010101010101010102D6 +:10E7300002010101010101010101010101010102C7 +:10E7400002010101010101010101010101010102B7 +:10E7500001010101010101010101010101010102A8 +:10E76000010101010101010101010101010101009A +:10E77000020202020202020202020202020201027A +:10E780000202020202020201000200000002000274 +:10E79000020202020202020202020200020202025B +:10E7A000020202020101020002000202020202024F +:10E7B000020202020202020200000202020202023D +:10E7C000020202020202020000000202020202022F +:10E7D000020202020201000200020202020202021E +:10E7E0000202020202020202020202020202020209 +:10E7F0000202020201010101010101020201020201 +:10E8000002020202010101010201020102010202EF +:10E8100002020101010101010101010101010102E5 +:10E8200002020201010101010101010101010202D3 +:10E8300002010101010101010101010101010102C6 +:10E8400002010101010101010101010101010102B6 +:10E8500001010101010101010101010101010102A7 +:10E860000101010101010101010101010101010099 +:10E870000202020202020202020202020202010279 +:10E880000202020202020202000200000002000272 +:10E89000020202020202020202020200020202025A +:10E8A000020202020201020002000202020202024D +:10E8B000020202020202020200000202020202023C +:10E8C000020202020202020000000202020202022E +:10E8D000020202020201000200020202020202021D +:10E8E0000202020202020202020202020202020208 +:10E8F0000202020201010101010101020201020200 +:10E9000002020202020101010201020202020202EB +:10E9100002020201010101010101010101010202E2 +:10E9200002020202010101010101010101010202D1 +:10E9300002020101010101010101010101010102C4 +:10E9400002010101010101010101010101010102B5 +:10E9500001010101010101010101010101010102A6 +:10E960000101010101010101010101010101010098 +:10E970000202020202020202020202020202010278 +:10E980000202020202020202000200000002000271 +:10E990000202020202020202020202000202020259 +:10E9A000020202020201020002000202020202024C +:10E9B000020202020202020200000202020202023B +:10E9C000020202020202020000000202020202022D +:10E9D000020202020201000200020202020202021C +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202010201010101010202020202FD +:10EA000002020202020201010202020202020202E8 +:10EA100002020201010101010101010101010202E1 +:10EA200002020202010101010101010101020202CF +:10EA300002020201010101010101010101010102C2 +:10EA400002010101010101010101010101010102B4 +:10EA500001010101010101010101010101010102A5 +:10EA60000201010101010101010101010101010096 +:10EA70000202020202020202020202020202010277 +:10EA80000202020202020202000200000002000270 +:10EA90000202020202020202020202010202020257 +:10EAA000020202020201020002000202020202024B +:10EAB000020202020202020200000202020202023A +:10EAC000020202020202020000000202020202022C +:10EAD000020202020201000200020202020202021B +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202010201010102020202020202FA +:10EB000002020202020201010202020202020202E7 +:10EB100002020202010101010101010101010202DF +:10EB200002020202010101010102020201020202CB +:10EB300002020201010101010101010101010102C1 +:10EB400002020201010101010101010101010102B1 +:10EB500002010101010101010101010101010102A3 +:10EB60000201010101010101010101010101010095 +:10EB70000202020202020202020202020202010276 +:10EB8000020202020202020200020000000200026F +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020200020002020202020249 +:10EBB0000202020202020202000002020202020239 +:10EBC000020202020202020000000202020202022B +:10EBD000020202020201000200020202020202021A +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202010201010102020202020202F9 +:10EC000002020202020201010202020202020202E6 +:10EC100002020202010101010101010201010202DD +:10EC200002020202020201020102020201020202C7 +:10EC300002020201010101010101010101010102C0 +:10EC400002020201010101010101010101010102B0 +:10EC500002010101010101010101010101010102A2 +:10EC60000202010101010101010101010101010093 +:10EC70000202020202020202020202020202010275 +:10EC8000020202020202020200020000000200026E +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020201020002020202020247 +:10ECB0000202020202020202000002020202020238 +:10ECC000020202020202020000000202020202022A +:10ECD0000202020202010002000202020202020219 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020201010102020202020202F7 +:10ED000002020202020201010202020202020202E5 +:10ED100002020202010101010101020201020202DA +:10ED200002020202020201020102020201020202C6 +:10ED300002020202010101010101010101010202BD +:10ED400002020201010101010101010101010102AF +:10ED500002010101010101010101010101010102A1 +:10ED60000202020101010101010101010101010091 +:10ED70000202020202020202020202020202010274 +:10ED80000202020202020202020201000202000268 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020201020002020202020246 +:10EDB0000202020202020202000002020202020237 +:10EDC0000202020202020200000002020202020229 +:10EDD0000202020202010002000202020202020218 +:10EDE0000202020202020202020202020202020203 +:10EDF00002020202020201010102020202020202F6 +:10EE000002020202020201010202020202020202E4 +:10EE100002020202020101010101020201020202D8 +:10EE200002020202020202020202020201020202C3 +:10EE300002020202010101010101020201020202B9 +:10EE400002020202010201010101010101010202AB +:10EE5000020202010101010101010101010101029E +:10EE60000202020101010101010101010101010090 +:10EE70000202020202020202020202020202010273 +:10EE80000202020202020202020202000202000266 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020002020202020244 +:10EEB0000202020202020202000002020202020236 +:10EEC0000202020202020200000002020202020228 +:10EED0000202020202010002000202020202020217 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202010102020202020202F4 +:10EF000002020202020201010202020202020202E3 +:10EF100002020202020201010101020201020202D6 +:10EF200002020202020202020202020201020202C2 +:10EF300002020202010201010102020201020202B6 +:10EF400002020202010201010102020201010202A7 +:10EF5000020202010101010101010101010101029D +:10EF6000020202020101010101010101010101008E +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202000202000265 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020002020202020243 +:10EFB0000202020202020202000002020202020235 +:10EFC0000202020202020200000002020202020227 +:10EFD0000202020202010002000202020202020216 +:10EFE0000202020202020202020202020202020201 +:10EFF00002020202020202010102020202020202F3 +:10F0000002020202020201010202020202020202E2 +:10F0100002020202020201010102020201020202D4 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020201010202020201020202B3 +:10F0400002020202020202010102020201020202A3 +:10F050000202020201020101010102010101010299 +:10F06000020202020202010101010101010101008B +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202000202000264 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020002020202020242 +:10F0B0000202020202020202010002020202020233 +:10F0C0000202020202020200000002020202020226 +:10F0D0000202020202020002010202020202020213 +:10F0E0000202020202020202020202020202020200 +:10F0F00002020202020202010102020202020202F2 +:10F1000002020202020202010202020202020202E0 +:10F1100002020202020201010102020201020202D3 +:10F1200002020202020202020202020202020202BF +:10F1300002020202020201020202020201020202B1 +:10F1400002020202020202020202020201020202A0 +:10F150000202020201020101010102020101020296 +:10F160000202020202020201010101010101010089 +:10F17000020202020202020202020202020202026F +:10F180000202020202020202020202000202000263 +:10F19000020202020202020202020202020202024F +:10F1A0000202020202020202020002020202020241 +:10F1B0000202020202020202020002020202020231 +:10F1C0000202020202020200000002020202020225 +:10F1D0000202020202020002010202020202020212 +:10F1E00002020202020202020202020202020202FF +:10F1F00002020202020202010202020202020202F0 +:10F2000002020202020202020202020202020202DE +:10F2100002020202020202020102020201020202D0 +:10F2200002020202020202020202020202020202BE +:10F2300002020202020202020202020201020202AF +:10F24000020202020202020202020202010202029F +:10F250000202020202020201010202020102020291 +:10F260000202020202020202020201020101010084 +:10F27000020202020202020202020202020202026E +:10F280000202020202020202020202010202000261 +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202010202020202023F +:10F2B0000202020202020202020002020202020230 +:10F2C0000202020202020200010002020202020223 +:10F2D0000202020202020002010202020202020211 +:10F2E00002020202020202020202020202020202FE +:10F2F00002020202020202010202020202020202EF +:10F3000002020202020202020202020202020202DD +:10F3100002020202020202020102020201020202CF +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020201020202AE +:10F34000020202020202020202020202020202029D +:10F35000020202020202020202020202020202028D +:10F360000202020202020202020202020201020080 +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020200025F +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B000020202020202020202020202020202022D +:10F3C0000202020202020200010102020202020221 +:10F3D000020202020202010201020202020202020F +:10F3E00002020202020202020202020202020202FD +:10F3F00002020202020202020202020202020202ED +:10F4000002020202020202020202020202020202DC +:10F4100002020202020202020202020201020202CD +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020202029C +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202020102007F +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020200025E +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C000020202020202020002010202020202021F +:10F4D000020202020202010201020202020202020E +:10F4E00002020202020202020202020202020202FC +:10F4F00002020202020202020202020202020202EC +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020202020202020202CB +:10F5200002020202020202020202020202020202BB +:10F5300002020202020202020202020202020202AB +:10F54000020202020202020202020202020202029B +:10F55000020202020202020202020202020202028B +:10F56000020202020202020202020202020202007D +:10F57000020202020202020202020202020202026B +:10F58000020202020202020202020202020200025D +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B000020202020202020202020202020202022B +:10F5C000020202020202020002010202020202021E +:10F5D000020202020202010202020202020202020C +:10F5E00002020202020202020202020202020202FB +:10F5F00002020202020202020202020202020202EB +:10F6000002020202020202020202020202020202DA +:10F6100002020202020202020202020202020202CA +:10F6200002020202020202020202020202020202BA +:10F6300002020202020202020202020202020202AA +:10F64000020202020202020202020202020202029A +:10F65000020202020202020202020202020202028A +:10F66000020202020202020202020202020202007C +:10F67000020202020202020202020202020202026A +:10F68000020202020202020202020202020200025C +:10F69000020202020202020202020202020202024A +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020002020202020202021C +:10F6D000020202020202020202020202020202020A +:10F6E00002020202020202020202020202020202FA +:10F6F00002020202020202020202020202020202EA +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020202020202020202020202C9 +:10F7200002020202020202020202020202020202B9 +:10F7300002020202020202020202020202020202A9 +:10F740000202020202020202020202020202020299 +:10F750000202020202020202020202020202020289 +:10F76000020202020202020202020202020202007B +:10F770000202020202020202020202020202020269 +:10F78000020202020202020202020202020200025B +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020202020202020202020202B8 +:10F8300002020202020202020202020202020202A8 +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F86000020202020202020202020202020202007A +:10F870000202020202020202020202020202020268 +:10F88000020202020202020202020202020200025A +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202020202020202020202A7 +:10F940000202020202020202020202020202020297 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020079 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202000259 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020078 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202000258 +:10FA90000202020202020202010202020202020247 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020077 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202000257 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020076 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202000256 +:10FC90000202020202020202010202020202020245 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020075 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202000255 +:10FD90000202020202020202010202010101020247 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202020202020202020223 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020074 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020102000255 +:10FE9000010101010101010101010102020201024E +:10FEA0000202020202020202020202020202020232 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020073 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202010202020202020102000255 +:10FF90000202020202020202010202010101020245 +:10FFA0000202020202020202020202020202020231 +:10FFB0000202020202020202020202020202020221 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:02000002E0001C +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020072 +:100070000202020202020202020202020202020260 +:100080000202020202010202020202020102000155 +:10009000010101010101010101010101010101024F +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:100180000202020202010202020201020101000255 +:10019000010101010101010101010101010101024E +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C000020202020202020202020202020202020F +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:100280000202020202010202020201010101000156 +:10029000010101010101010101010101010101024D +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C000020202020202020202020202020202020E +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202015E +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101024C +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202020202020202020D +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202015D +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101024B +:1004A000020202020202020202020202020202022C +:1004B000020202020202020102020202020202021D +:1004C000020202020202020202020202020202020C +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202015C +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101024A +:1005A000020202020202010202020202020202022C +:1005B000020202020202020202020202010202021C +:1005C000020202020202020202020202020202020B +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202015B +:10068000010101010101010101010101010101015A +:100690000101010101010101010101010101010249 +:1006A000020202020202020201020202010102022D +:1006B000020202020202010102020202020202021C +:1006C000020202020202020202020202020202020A +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:10077000020202020202020202020202020202015A +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010248 +:1007A000020202020202010202020101020202022C +:1007B000020202020201020102020101010102021F +:1007C0000202020202020202020202020202020209 +:1007D00002020202020202020202020202020202F9 +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020159 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010247 +:1008A000020202020202010201010202010102022D +:1008B000020202020202010102020202010202021B +:1008C0000202020202020202020202020202020208 +:1008D00002020202020202020202020202020202F8 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020158 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010246 +:1009A000020202020202010101020101010102012F +:1009B000020202020201010102010101010102021F +:1009C0000202020202020202020202020202020207 +:1009D00002020202020202020202020202020202F7 +:1009E00002020202020202020202020202020202E7 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020157 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010102010101010101010234 +:100AB0000101010101010101010201010101010224 +:100AC0000202020202020202020202020202020206 +:100AD00002020202020202020202020202020202F6 +:100AE00002020202020202020202020202020202E6 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020156 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010244 +:100BA000020202020202010101010101010102012E +:100BB000020202020201010102010101010102021D +:100BC0000202020202020102020202020202020206 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020155 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010223 +:100CC0000202020202010102020201020102020208 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020154 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010222 +:100DC0000202010202010102020201010102020209 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020153 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010221 +:100EC000020201010101010201010101010102020D +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020152 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC000020201010101010201010101010102020C +:100FD00002020202010202020202020201020202F3 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020151 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C000010101010101010101010101010101020F +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:101170000202020202020202020202020202020150 +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101020E +:1011D00002020202010202010201010201020202F4 +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202014F +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00002020102010202020102020101020202F3 +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202014E +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101020C +:1013D00002020202010202010201010201010202F3 +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202014D +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101020102FA +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202014C +:10158000010101010101010101010101010101014B +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00002020102010202010101010101010202F4 +:1015E00002020202020102020202020202020202DC +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202014B +:10168000010101010101010101010101010101014A +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001020202020201020102020201020202DE +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:10177000020202020202020202020202020202014A +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010102F8 +:1017E00002020202020102010201010102010202DF +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020149 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001020202010101020102020201020202DE +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020202A7 +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020148 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101020101010101010101010102E5 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020147 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001020202010101010101010101010201E2 +:101AF00002020202020202020202020201020202C7 +:101B000002020202020202020102020202020202B6 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020146 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00002020202020202020202020201020202C6 +:101C000002020201020202020102020202020202B6 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020145 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00002020202020202020101010101020202C9 +:101D000002010201020202020102010201020202B8 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020144 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000002010201020202020101010201020202B8 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020143 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010102C0 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020142 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010102BF +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020141 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010102BE +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:102170000202020202020202020202020202020140 +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010102BD +:10221000020202020202020202020202020202019F +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202013F +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:10231000020202020202020202020202020202019E +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202013E +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010102BB +:10241000020202020202020202020202020202019D +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202013D +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000020102020202020202020202020202028C +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202013C +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:10261000020202020202020202020202020202019B +:10262000010101010101010101010101010101019A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202013B +:10268000010101010101010101010101010101013A +:10269000010101010101010101010101010101012A +:1026A000010101010101010101010101010101011A +:1026B000010101010101010101010101010101010A +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:10277000020202020202020202020202020202013A +:102780000101010101010101010101010101010139 +:102790000101010101010101010101010101010129 +:1027A0000101010101010101010101010101010119 +:1027B0000101010101010101010101010101010109 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020139 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020138 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010101010127 +:1029A0000101010101010101010101010101010117 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000202020202020202020202020202020167 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020137 +:102A80000101010101010101010101010101010136 +:102A90000101010101010101010101010101010126 +:102AA0000101010101010101010101010101010116 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000202020202020202020202020202020166 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020136 +:102B80000101010101010101010101010101010135 +:102B90000101010101010101010101010101010125 +:102BA0000101010101010101010101010101010115 +:102BB0000101010101010101010101010101010105 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101010101010101010101E5 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020135 +:102C80000101010101010101010101010101010134 +:102C90000101010101010101010101010101010124 +:102CA0000101010101010101010101010101010114 +:102CB0000101010101010101010101010101010104 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010173 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020134 +:102D80000101010101010101010101010101010133 +:102D90000101010101010101010101010101010123 +:102DA0000101010101010101010101010101010113 +:102DB0000101010101010101010101010101010103 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020133 +:102E80000101010101010101010101010101010132 +:102E90000101010101010101010101010101010122 +:102EA0000101010101010101010101010101010112 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010101D2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020132 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020131 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101025E +:10316000020202020202020202020202020202023F +:103170000202020202020202020202020202020130 +:10318000010101010101010101010101010101012F +:10319000010101010101010101010101010101011F +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000020202020202020202020202020202023E +:103270000101020102020201010202020202020134 +:10328000010101010101010101010101010101012E +:10329000010101010101010101010101010101011E +:1032A000010101010101010101010101010101010E +:1032B00001010101010101010101010101010101FE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101025C +:10336000010101010101010101010101010101024C +:10337000010101010101010101010201020102013A +:10338000010101010101010101010101010101012D +:10339000010101010101010101010101010101011D +:1033A000010101010101010101010101010101010D +:1033B00001010101010101010101010101010101FD +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000010101010101010101010101010101017C +:10344000010101010101010101010101010101016C +:10345000010101010101010101010101010101015C +:10346000020202020202020202020202020202023C +:10347000010101010101010101010101010102013B +:10348000010101010101010101010101010101012C +:10349000010101010101010101010101010101011C +:1034A000010101010101010101010101010101010C +:1034B00001010101010101010101010101010101FC +:1034C00001010101010101010101010101010101EC +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101024A +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:103660000101010101010101010101010101010249 +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A000010101010101010101010101010101010A +:1036B00001010101010101010101010101010101FA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010248 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010247 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010227 +:10389000020202020202020202020202020202000A +:1038A0000000000000000000000000000000000216 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020200CA +:1038E00000000000000000000000000000000002D6 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020099 +:1039100000000000000000000000000000000002A5 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020049 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000146 +:103980000101010101010101010101010101010028 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000002C5 +:103A00000202020202020202020202020202020098 +:103A100000000000000000000000000000000002A4 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020058 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000145 +:103A80000101010101010101010101010101010027 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000002C4 +:103B00000202020202020202020202020202020097 +:103B100000000000000000000000000000000002A3 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020057 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C700000000000000000000000000000000088BC +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000001000000000000000000D3 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000010000000042 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000010012 +:103DB0000000000000000001000000000000000002 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000010000000000E2 +:103DE00000000000000001010000000000000000D1 +:103DF00000000000000000010000000000000000C2 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E7000000000000000000001000101010101003C +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA000010000000000010000000000000001000F +:103EB0000000000000000101000000000000000000 +:103EC00000000000000000010000010000000000F0 +:103ED00000000001000000000000010000000000E0 +:103EE00000000000000001010000000000000000D0 +:103EF00000000000000000010000000000000000C1 +:103F000000000000000001000000000000000000B0 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F7000000000000000000001000101010101003B +:103F80000000000000000000000000000000000031 +:103F9000000100000001000000000000000000001F +:103FA000010000000000010000000000000001000E +:103FB00000000000000001010000000000010000FE +:103FC00000000000000000010000010000000000EF +:103FD00000000001000001010000010000000000DD +:103FE00000000000000001010000000000000000CF +:103FF00000000000000000010000000000000000C0 +:1040000000000000000001000000000000000000AF +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:10405000000000000000010000000000000000005F +:104060000000000000000000000000000000000050 +:104070000000000000000000010101010101010039 +:104080000000000000000000000000000000000030 +:10409000000100000001000000000000000000001E +:1040A000010000000000010000000000000001000D +:1040B00000000000000001010000000000010000FD +:1040C00000000000000001010000010000000000ED +:1040D00000000001000001010000010000000000DC +:1040E00000000000000001010000000000000000CE +:1040F00000000000000000010000000000000000BF +:1041000000000000000001000000000000000000AE +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000010000000000000000007E +:10414000000000000000000000000000000000006F +:10415000000000000000010000000000000000005E +:10416000000000000000000000000000000000004F +:104170000000000000000000010101010101010038 +:10418000000000000000000101000000000000002D +:10419000000100000001000100000000000000001C +:1041A000010000000000010000000000000001000C +:1041B00000000000000001010000000000010000FC +:1041C00000000000000001010000010000000000EC +:1041D00000000001000001010000010000000000DB +:1041E00000000001000001010000000000000000CC +:1041F00000000000000000010000000000000000BE +:1042000000000000000001000000000000000000AD +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000010000000000000000007D +:10424000000000000000000000000000000000006E +:10425000000000000000010000000000000000005D +:10426000000000000000000000000000000000004E +:104270000000000000000000010101010101010037 +:10428000000000000000000101000000000000002C +:10429000000100000001000100000000000000001B +:1042A000010000000000010000000000000001000B +:1042B00000000000000001010000000000010000FB +:1042C00000000000000001010000010000000000EB +:1042D00000000001000001010000010000000000DA +:1042E00000000001000001010000000000000000CB +:1042F00000000000000000010000000000000000BD +:1043000000000000000001000000000000000000AC +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000010000000000000000007C +:10434000000000000000000000000000000000006D +:10435000000000000000010000000000000000005C +:10436000000000000000000000000000000000004D +:104370000000000000000000010101010101010036 +:10438000000000000000010101000000000000002A +:10439000000100000001000100000000000000001A +:1043A0000100000100010100000000000000010008 +:1043B00000000000000001010000000000010000FA +:1043C00000000000000001010000010000000000EA +:1043D00000000001000001010000010000000000D9 +:1043E00000000001000001010000000000000000CA +:1043F00000000000000000010000000000000000BC +:1044000000000000000001000000000000000000AB +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000010000000000000000007B +:10444000000000000000000000000000000000006C +:10445000000000000000010000000000000000005B +:10446000000000000000010000000000000000004B +:104470000000000000000000010101010101010035 +:104480000000000000000101010000000000000029 +:104490000001000000010001000000000000000019 +:1044A0000100000100010100000000000000010007 +:1044B00001000100000001010000000000010000F7 +:1044C00000000000010001010000010000010000E7 +:1044D00000000001000001010000010000000000D8 +:1044E00000000001000001010000000000000000C9 +:1044F00000000000000000010000000000000000BB +:1045000000000000000001000000000000000000AA +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000010000000000000000007A +:10454000000000000000000000000000000000006B +:10455000000000000000010000000000000000005A +:10456000000000000000010000000000000000004A +:104570000000000000000000010101010101010034 +:104580000000000000000101010100000000000027 +:104590000001000000010001000000000000000018 +:1045A0000100000100010100000000000000010006 +:1045B00001000100000001010000000000010000F6 +:1045C00000000000010001010000010000010000E6 +:1045D00000000001000001010000010000000000D7 +:1045E00000000001000001010000000000000000C8 +:1045F00000000000000000010000000000000000BA +:1046000000000000000001000000000000000000A9 +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:104630000000000000000100000000000000000079 +:10464000000000000000000000000000000000006A +:104650000000000000000100000000000000000059 +:104660000000000000000100000000000000000049 +:104670000000000000000000010101010101010033 +:104680000000000000010101010100000000000025 +:104690000001000000010001000000000000000017 +:1046A0000100000100010100000000000000010005 +:1046B00001000100000001010000000000010000F5 +:1046C00000000000010001010000010000010000E5 +:1046D00000000001000001010000010000000000D6 +:1046E00000000001000001010000000000000000C7 +:1046F00000000000000001010000000000000000B8 +:1047000000000000000001000000000000000000A8 +:104710000100000000000000000000000000000098 +:104720000000000000000000000000000000000089 +:104730000000000000000100000000000000000078 +:104740000000000000000000000000000000000069 +:104750000000000000000100000000000000000058 +:104760000000000000000100000000000000000048 +:104770000000000000000000010101010101010032 +:104780000000000000010101010100000000000024 +:104790000001000000010001000000000100000015 +:1047A0000100000100010100000000000000010004 +:1047B00001000100000001010000000000010100F3 +:1047C00000000000010001010000010000010000E4 +:1047D00000000001000001010000010001000000D4 +:1047E00000000001000001010100000000000000C5 +:1047F00000000000000001010000000000000000B7 +:1048000000000000000101000000000000000000A6 +:104810000100000000000000000000000000000097 +:104820000000000000000000000000000000000088 +:104830000000000000010100000000000000000076 +:104840000000000000000100000000000000000067 +:104850000000000000000100000000000000000057 +:104860000000000000000100000000000000000047 +:104870000000000000000000010101010101010031 +:104880000000000000010101010100000000000023 +:104890000001000001010001000000000100000013 +:1048A0000100010100010100000000000000010002 +:1048B00001000100010001010000000000010100F1 +:1048C00000000000010001010000010000010000E3 +:1048D00000000001000001010000010001000000D3 +:1048E00000000001000001010100000000000000C4 +:1048F00000000000000001010000000000000000B6 +:1049000000000000000101000000000000000000A5 +:104910000100000000000100000000000000000095 +:104920000000000000000000000000000000000087 +:104930000000000000010100000000000000000075 +:104940000000000000000100000000000000000066 +:104950000000000000010100000000000000000055 +:104960000000000000000100000000000000000046 +:104970000000000000000000010101010101010030 +:104980000000010001010101010100000000000020 +:104990000001000001010001000000000100000012 +:1049A0000100010100010100000000000000010001 +:1049B00001000100010101010000000000010100EF +:1049C00000000000010001010000010100010000E1 +:1049D00000000001000001010000010001000000D2 +:1049E00000000001000101010100000000000000C2 +:1049F00000000000000001010000000000000000B5 +:104A000000000000000101000000000000000000A4 +:104A10000100000000000100000000000000000094 +:104A20000000000000000100000000000000000085 +:104A30000000000000010100000000000000000074 +:104A40000000000000000100000000000000000065 +:104A50000000000000010100000000000000000054 +:104A60000000000000000100000000000000000045 +:104A7000000000000000000001010101010101002F +:104A8000000101000101010101010000000000001E +:104A90000001000001010001000000000100000011 +:104AA0000100010100010100000000000000010000 +:104AB00001000100010101010000000000010100EE +:104AC00000000000010001010000010100010000E0 +:104AD00000000001000001010000010001000000D1 +:104AE00000000001000101010100000000000000C1 +:104AF00000000000000001010000000000000000B4 +:104B000000000000000101000000000000000000A3 +:104B10000100000000000100000000000000000093 +:104B20000000000000000100000000000000000084 +:104B30000000000000010100000000000000000073 +:104B40000000000000000100000000000000000064 +:104B50000000000000010100000000000000000053 +:104B60000000000000010100000000000000000043 +:104B7000000000000000000001010101010101002E +:104B8000000101000101010101010000000000001D +:104B9000000100000101000100000100010000000F +:104BA00001000101000101010001000000010100FC +:104BB00001000100010101010100000000010101EB +:104BC00000010000010001010000010100010000DE +:104BD00000000001010001010000010001000000CF +:104BE00000000001000101010100000000000000C0 +:104BF00000000000000001010000000000000000B3 +:104C000000000000000101000001000000000000A1 +:104C10000100000000000100000000000000000092 +:104C20000000000000000100000000000000000083 +:104C30000000000000010100000000000000000072 +:104C40000000000000000100000000000000000063 +:104C50000000000000010100000000000000000052 +:104C60000000000000010100000000000000000042 +:104C7000000000000000000001010101010101002D +:104C8000000101000101010101010000000000001C +:104C9000000100000101000100000100010000000E +:104CA00001000101000101010001000000010100FB +:104CB00001000100010101010100000000010101EA +:104CC00000010000010001010000010100010000DD +:104CD00000000001010001010000010001000000CE +:104CE00000000001000101010100000000000000BF +:104CF00000000000000001010000000000000000B2 +:104D000000000000000101000001000000000000A0 +:104D10000100000000000100000000000000000091 +:104D20000000000000000100000000000000000082 +:104D30000000000000010100000000000000000071 +:104D40000000000000000100000000000000000062 +:104D50000000000000010100000000000000000051 +:104D60000000000000010100000000000000000041 +:104D7000000000000000010001010101010101002B +:104D8000010101000101010101010000000000001A +:104D9000000100000101000100000100010000000D +:104DA00001000101000101010001000000010100FA +:104DB00001000100010101010100000000010101E9 +:104DC00000010000010001010000010100010000DC +:104DD00000000001010001010000010001000000CD +:104DE00000000001000101010100000000000000BE +:104DF00000000000000001010000000000000000B1 +:104E0000000000000001010000010000000000009F +:104E10000100000000000100000000000000000090 +:104E20000000000000000100000000000000000081 +:104E30000000000000010100000000000000000070 +:104E40000000000000000100000000000000000061 +:104E5000000000000101010000000000000000004F +:104E6000000000000101010000000000000000003F +:104E7000000000000000010001010101010101002A +:104E80000101010101010101010100000000000018 +:104E9000000100000101000100000100010000000C +:104EA00001000101000101010001000000010100F9 +:104EB00001000100010101010100000000010101E8 +:104EC00000010000010001010000010100010000DB +:104ED00000000001010001010000010101000000CB +:104EE00000000001000101010100000000000000BD +:104EF00000000000000001010000000000000000B0 +:104F0000000000000001010000010001000000009D +:104F1000010000000000010000000000000000008F +:104F20000000000000000100000000000000000080 +:104F3000000000000001010000000000000000006F +:104F4000000000000001010000000000000000005F +:104F5000000000000101010000000000000000004E +:104F6000000000000101010000000000000000003E +:104F70000000000000000100010101010101010029 +:104F80000101010101010101010100000000000017 +:104F9000000100000101000100000100010000000B +:104FA00001000101000101010101000000010100F7 +:104FB00001000100010101010100000001010101E6 +:104FC00000010000010001010000010100010000DA +:104FD00000000001010001010000010101000000CA +:104FE00000000001000101010100000000010000BB +:104FF00000000000000001010000000000000000AF +:10500000000000000001010000010001000000009C +:10501000010000000000010000000000000000008E +:10502000000000000000010000000000000000007F +:10503000000000000001010000000000000000006E +:10504000000000000001010000000000000000005E +:10505000000000000101010000000000000000004D +:10506000000000000101010000000000000000003D +:105070000000000000000100010101010101010127 +:105080000101010101010101010100000000000016 +:10509000000100000101000100000100010000000A +:1050A00001000101010101010101000100010100F4 +:1050B00001000100010101010100000001010101E5 +:1050C00000010000010001010100010101010100D6 +:1050D00000000001010001010000010101000000C9 +:1050E00000000001000101010100000000010000BA +:1050F00000000000000001010000000000000000AE +:10510000000000000001010000010001000000009B +:10511000010000000000010000000000000100008C +:10512000000000000000010000000000000000007E +:10513000000000000101010000000000000000006C +:10514000000000000001010000000000000000005D +:10515000000100000101010000000000000000004B +:10516000000100000101010000000000000000003B +:105170000000000000000100010101010101010126 +:105180000101010101010102010100000000000014 +:105190000001000001010001010001000100000008 +:1051A00001000101010101010101000100010100F3 +:1051B00001000101010101010100000001010101E3 +:1051C00000010001010101010100010101010100D3 +:1051D00000000001010001010000010101000000C8 +:1051E00000000001000101010100000000010000B9 +:1051F00000000001000001010000000000000000AC +:10520000000000000001010000010001000000009A +:10521000010000000000010000000000000100008B +:10522000000000000000010000000000000000007D +:10523000000000000101010000000000000000006B +:10524000000000000001010000000000000000005C +:105250000001010001010100000000000000000049 +:105260000001010001010100000000000000000039 +:105270000000000000010100010101010101010124 +:105280000101010101010102010100000000000013 +:105290000001000001010001010001000100000007 +:1052A00001000101010101010101000100010100F2 +:1052B00001000101010101020100000001010101E1 +:1052C00000010001010101010100010101010101D1 +:1052D00000000001010001010000010101000000C7 +:1052E00000000001000101010100000000010000B8 +:1052F00000000001000001010000000000000000AB +:105300000000000000010100000100010000000099 +:10531000010000000000010000000000000100008A +:10532000000000000000010000000000000000007C +:10533000000000000101010000000000000000006A +:10534000000000000001010000000000000000005B +:105350000001010001010100000000000000000048 +:105360000001010001010100000000000000000038 +:105370000000000000010100010101010101010123 +:105380000101010101010102020101000000000010 +:105390000001000001010001010001000100000006 +:1053A00001000101010101010101000100010100F1 +:1053B00001010101010101020100000001010101DF +:1053C00000010001010101010100010101010101D0 +:1053D00000000001010001010000010101000000C6 +:1053E00000000001000101010100000000010100B6 +:1053F00000000001000001010000000000000000AA +:105400000000000000010100000100010000000098 +:105410000100000000010100000000000001000088 +:10542000000000000000010000000000000000007B +:105430000000000001010100000000000000000069 +:10544000000000000001010000000000000000005A +:105450000001010001010100000000000000000047 +:105460000001010001010100000000000000000037 +:105470000000000000010100010101010101010122 +:10548000010101010101010202010100000000000F +:105490000001000001010002010001000100000004 +:1054A00001000101010101010101000100010100F0 +:1054B00001010101010101020100000001010101DE +:1054C00000010101010101010100010101010101CE +:1054D00000000001010001010000010101000000C5 +:1054E00000000001000101010100000000010100B5 +:1054F00000000001000001010000000000000000A9 +:105500000000000000010100000100010000000097 +:105510000100000000010100000000000001000087 +:10552000000000000000010000000000000000007A +:105530000000000001010100000000000000000068 +:105540000000000000010100000000000000000059 +:105550000001010101010100000000000000000045 +:105560000001010101010100000000000000000035 +:105570000000000001010100010101010101010120 +:10558000010101010101010202010100000000000E +:105590000001000001010002010001000100000003 +:1055A00001000101010101010101000100010100EF +:1055B00001010101010101020100000001010101DD +:1055C00000010101010101020100010101010101CC +:1055D00000000001010001010100010101000001C2 +:1055E00000000001000101010100000001010100B3 +:1055F00000000001000001010000000000000000A8 +:105600000000000000010100000100010000000096 +:105610000100000000010100000000000001000086 +:105620000000000000000101000000000000000078 +:105630000001000001010100000000000000000066 +:105640000000000001010100000000000000000057 +:105650000001010101010100000000000000000044 +:105660000101010101010100000000000000000033 +:10567000000000000101010001010101010101011F +:10568000010101010101010202010100000000000D +:105690000001000001010002010001000100000002 +:1056A00001000101010101010101000100010100EE +:1056B00001010101010101020100000001010101DC +:1056C00000010101010101020100010101010101CB +:1056D00000000001010001010100010101000001C1 +:1056E00000000001010101010100000001010100B1 +:1056F00001000001000001010000000100000000A5 +:105700000000000000010100000100010000000095 +:105710000100000000010100000000000001000085 +:105720000000000000010101000000000000000076 +:105730000001000001010100000000000000000065 +:105740000000000001010100000000000000000056 +:105750000001010101010100000000000000000043 +:105760000101010101010100000000000000000032 +:10577000000000000101010001010101010101011E +:10578000010101010101010202010100000000000C +:105790000001000001010002010001000100000001 +:1057A00001010101010101010101000100010100EC +:1057B00001010101010101020101000001010101DA +:1057C00000010101010101020100010101010101CA +:1057D00000000101010001020100010101000001BE +:1057E00000010001010101020100000001010100AE +:1057F00001000001000001010000000100010000A3 +:105800000000000100010100000100010000000093 +:105810000100000100010100000000000001000083 +:105820000000000000010101000100000000000074 +:105830000001000001010100000000000000000064 +:105840000000000001010100000000000000000055 +:105850000001010101010100000000000000000042 +:105860000101010101010100000000000000000031 +:10587000000100000101010001010101010101011C +:10588000010101010101010202020100000000000A +:105890000001000001010002010001000100000000 +:1058A00001010101010101010101000100010100EB +:1058B00001010101010101020101000001010101D9 +:1058C00000010101010101020101010101010101C8 +:1058D00000000101010101020100010101000001BC +:1058E00000010101010101020100000001010100AC +:1058F00001000001000001020000000100010000A1 +:105900000000000100010100000100010000000092 +:105910000100000100010100000000000001000082 +:105920000000000000010101000100000000000073 +:105930000001010001010100000000000000000062 +:105940000000000001010100000000000000000054 +:105950000001010101010101000000000000000040 +:105960000101010101010100000000000000000030 +:10597000000100000101010001010101010101011B +:105980000101010101010102020201000000000009 +:1059900000010000010100020100010001000000FF +:1059A00001010101010101010101000100010100EA +:1059B00001010101010101020101000001010101D8 +:1059C00000010101010101020101010101010101C7 +:1059D00000000101010101020100010101000001BB +:1059E00000010101010101020100000001010100AB +:1059F000010100010000010201000001000100009E +:105A00000000000100010100000100010000000091 +:105A10000100000100010100000000000001000081 +:105A20000000000000010101000100000000000072 +:105A30000001010001010100000000000000000061 +:105A40000000000001010100000000000000000053 +:105A5000010101010101010100000000000000003E +:105A6000010101010101010000000000000000002F +:105A7000000100000101010001010101010101011A +:105A80000101010101010102020201000000000008 +:105A900000010000010100020100010001000000FE +:105AA00001010101010101010101000100010100E9 +:105AB00001010101010101020101000001010101D7 +:105AC00000010101010101020101020101010101C5 +:105AD00000000101010101020100010101000001BA +:105AE00000010101010101020100000001010100AA +:105AF000010100010000010201000001000100009D +:105B00000000000100010100000100010000000090 +:105B10000100000100010100000000000001000080 +:105B20000000000000010101000100000000000071 +:105B30000001010001010100000000000000000060 +:105B40000001000101010100000000000000000050 +:105B5000010101010101010100000000000000003D +:105B6000010101010101010000000000000000002E +:105B70000001010001010100010101010101010118 +:105B80000101010101010102020201000000010006 +:105B900000010000010100020101010001000000FC +:105BA00001010101010101010101000100010100E8 +:105BB00001010101010101020101000001010101D6 +:105BC00000010101010101020101020101010101C4 +:105BD00000000101010101020101020101000001B7 +:105BE00000010101010101020100000001010100A9 +:105BF000010100010000010201010101000100009A +:105C0000000000010001010000010001000000008F +:105C1000010000010001010000000000000100007F +:105C2000000000000001010101010000000000006F +:105C3000000101010101010000000000000000005E +:105C4000000101010101010000000000000000004E +:105C5000010101010101010100000000000000003C +:105C6000010101010101010000000000000000002D +:105C70000001010101010100010101010101010116 +:105C80000101010101010102020201010000010004 +:105C900001010000010100020101010001000000FA +:105CA00001010101010101020101000100010100E6 +:105CB00001010101010101020201000001020101D3 +:105CC00000010101010101020101020101010101C3 +:105CD00000000101010101020101020101000001B6 +:105CE00000010101010101020100000001010100A8 +:105CF0000101000100000102010101010001000099 +:105D0000000000010001010000010001000000008E +:105D1000010000010101010000000000000100007D +:105D2000000000000001010101010000000000006E +:105D3000000101010101010000000000000000005D +:105D4000000101010101010001000000000000014B +:105D5000010101010101010100000000000000013A +:105D6000010101010101010000000000000000002C +:105D70000101010101010100010101010101010114 +:105D80000101010101010102020201010100010002 +:105D900001010000010100020101020002000000F7 +:105DA00001010101010101020101000101010100E4 +:105DB00001010101010101020201000001020101D2 +:105DC00000010101010101020101020101010101C2 +:105DD00000000101010101020101020101000001B5 +:105DE00000010101010101020100010001010100A6 +:105DF0000101000100000102010101010001000098 +:105E0000000000010001010000010001000001008C +:105E1000010000010101010000000000000100007C +:105E2000000000000001010101010000000000006D +:105E3000000101010101010000000000000000005C +:105E4000000101010101010001000000000000014A +:105E50000101010101010101000000000000000139 +:105E6000010101010101010000000000000000002B +:105E70000101010101010100010101010101010113 +:105E80000101010101010102020201010100010001 +:105E900001010000010100020201020002000000F5 +:105EA00002010101010101020102000101010200E0 +:105EB00001010101010101020201000001020101D1 +:105EC00000010101010101020101020101010101C1 +:105ED00000010101010101020101020101000001B3 +:105EE00000010101010101020200010001010100A4 +:105EF0000101000100000102010101010001000097 +:105F0000000000010001010000010001000001008B +:105F1000010000010101010000000000000100007B +:105F2000000000000001010101010000000000006C +:105F3000010101010101010000000000000000005A +:105F40000001010101010100010000000000010148 +:105F50000101010101010101000000000000000138 +:105F6000010101010101010000000000000000002A +:105F70000101010101010100010101010101010112 +:105F80000101010101010102020201010100010000 +:105F900001010000010100020201020002000000F4 +:105FA00002010101010101020102010101010200DE +:105FB00001010101010101020201010001020101CF +:105FC00000010101010101020101020101010101C0 +:105FD00000010101010101020101020101000001B2 +:105FE00000010101010101020200010001010100A3 +:105FF0000101000100010102010101010001000095 +:106000000001000100010101000100010000010088 +:10601000010000010101010000000000000100007A +:10602000000000000001010101010000000000006B +:106030000101010101010100000000000000000059 +:106040000101010101010100010000000000010146 +:106050000101010101010101000000000000000137 +:106060000101010101010100000000000000000029 +:106070000101010101010100010101010101010111 +:1060800001010101010101020202010101000100FF +:1060900001010000010100020201020002000000F3 +:1060A00002010101010101020202010101010200DC +:1060B00001010101010101020201010001020101CE +:1060C00000010101010101020101020101010101BF +:1060D00000010101010101020101020101000001B1 +:1060E00000010101010101020200010001010100A2 +:1060F0000101000100010102010101010001000094 +:106100000001000101010101000100010000010086 +:106110000100000101010100000000000001000079 +:10612000000000000001010101010000000000006A +:106130000101010101010100000000000000000058 +:106140000101010101010100010000000000010145 +:106150000101010101010101000000000000010135 +:106160000101010101010100000000000000000028 +:106170000101010101010100010101010101010110 +:1061800001010101010101020202020101000100FD +:1061900001010000010100020201020002000000F2 +:1061A00002010101010101020202010101010200DB +:1061B00001010101010101020201010001020101CD +:1061C00000010101010101020201020201020101BB +:1061D00000010101010101020101020101000001B0 +:1061E00000010101010101020200010001010100A1 +:1061F0000101000100010102010101010001000093 +:106200000001000101010101000100010001010084 +:106210000100000101010100000000000001000078 +:106220000000000001010101010100000000000068 +:106230000101010101010100000000000000000057 +:106240000101010101010100010000000000010144 +:106250000101010101010101000000000000010134 +:106260000101010101010100000000000000010125 +:10627000010101010101010001010101010101010F +:1062800001010101010101020202020101000100FC +:1062900001020000010100020201020102000000EF +:1062A00002010101010101020202010101010200DA +:1062B00001010101010101020201010001020101CC +:1062C00000010101010101020201020201020101BA +:1062D00000010101010101020101020101000001AF +:1062E00000010101010101020200010001010100A0 +:1062F0000101000101010102010101010001000091 +:106300000001000101010101000100010001010083 +:106310000100000101010100000000000001000077 +:106320000000000001010101010100000000000067 +:106330000101010101010101000000000000000055 +:106340000101010101010100010000000000010143 +:106350000101010101010101000000000000010133 +:106360000101010101010100000000000000010124 +:10637000010101010101010001010101010101010E +:1063800001010101010101020202020101000101FA +:1063900001020000010100020201020102000000EE +:1063A00002010101010101020202010101010200D9 +:1063B00001010101010101020201010001020201CA +:1063C00000010101010101020201020201020101B9 +:1063D00000010101010101020101020101000001AE +:1063E000000101010101010202000100010101019E +:1063F0000101000101010102010101010001000090 +:106400000001000101010101000100010001010082 +:106410000100000101010100000000000001000076 +:106420000000010001010101010101000000000163 +:106430000101010101010101000000000000000054 +:106440000101010101010100010000000000010142 +:106450000101010101010101000000000000010132 +:106460000101010101010100000000000000010123 +:10647000010101010101010002010101010101010C +:1064800001010101010101020202020101000101F9 +:1064900001020000010100020201020102000000ED +:1064A00002010102010101020202010201020200D5 +:1064B00001010101010101020201010102020202C6 +:1064C00000010101010101020201020201020101B8 +:1064D00000010101010101020101020102000001AC +:1064E000000101010101010202000100010101019D +:1064F000010100010101010201010101000100008F +:106500000001000101010101000100010001010081 +:106510000100000101010100000000000001000075 +:106520000001010001010101010101000000000161 +:106530000101010101010101000001000000000052 +:106540000101010101010100010000000100010140 +:106550000101010101010101000000000100010130 +:106560000101010101010100000000000000010122 +:10657000010101010101010002010101010101010B +:1065800001010101010101020202020101010101F7 +:1065900001020000010100020202020102000000EB +:1065A00002010102010101020202010201020200D4 +:1065B00001010101010101020202010102020202C4 +:1065C00000010101010101020201020201020101B7 +:1065D00000010101010101020201020102000001AA +:1065E000000101010101010202000100010101019C +:1065F000010100010101010201010101000100008E +:10660000000100010101010100020001000101007F +:106610000100000101010100000000000001000074 +:106620000001010001010101010101000000000160 +:106630000101010101010101000001000000000051 +:10664000010101010101010001000000010001013F +:10665000010101010101010100000000010001012F +:10666000010101010101010000000000010101011F +:10667000010101010101010002010101010101010A +:1066800001010101010101020202020101010101F6 +:1066900001020000010200020202020102000000E9 +:1066A00002010102010101020202010201020200D3 +:1066B00002010101010101020202010102020202C2 +:1066C00000010101010101020201020201020101B6 +:1066D00000010102010101020201020202000001A7 +:1066E000000101010101010202000101010101019A +:1066F000010101010101010201010101000100008C +:10670000000100010101010100020001000101007E +:106710000100000101010101000100000001000170 +:10672000000101000101010101010100000000015F +:106730000101010101010101000001000000000050 +:10674000010101010101010101000000010101013C +:10675000010101010101010100000100010101012C +:10676000010101010101010000000000010101011E +:106770000101010101010100020101010101010109 +:1067800001010101010101020202020201010101F4 +:1067900001020000010200020202020102000000E8 +:1067A00002010102010101020202010201020200D2 +:1067B00002010101010101020202010102020202C1 +:1067C00000010101010101020202020201020101B4 +:1067D00000010102010101020201020202000001A6 +:1067E0000001010101010102020001010101010199 +:1067F000010101010101010201010101000100008B +:10680000000100010101010101020001000101007C +:10681000010100010101010100010000000100016E +:10682000000101000101010101010100000001015D +:10683000010101010101010100000100000000004F +:10684000010101010101010101000000010101013B +:10685000010101010101010100000100010101012B +:10686000010101010101010100000100010101011B +:106870000101010101010100020201010101010107 +:1068800001010101010101020202020201010101F3 +:1068900001020000020200020202020102000000E6 +:1068A00002010202010101020202010201020200D0 +:1068B00002010101010101020202010102020202C0 +:1068C00000010101010101020202020202020101B2 +:1068D00000010102010101020201020202000001A5 +:1068E0000001010101010102020001010101010198 +:1068F000010101010101010201010101000100008A +:10690000000100010101010101020001000101007B +:10691000010101010101010100010000000100016C +:10692000000101000101010201010100000001015B +:10693000010101010101010100000100000000014D +:106940000101010101010101010001000101010139 +:106950000101010101010101010001000101010129 +:106960000101010101010101000001010101010119 +:106970000101010101010100020202010101010105 +:1069800001010101010101020202020201010101F2 +:1069900001020000020200020202020102000000E5 +:1069A00002010202010101020202010201020200CF +:1069B00002010201010101020202010102020202BE +:1069C00000010101020101020202020202020101B0 +:1069D00000010102010101020201020202000001A4 +:1069E0000001010101010102020101010101010196 +:1069F0000101010101010102010101010001000089 +:106A0000000100010101010101020001000101007A +:106A1000010101010101010100010000000100016B +:106A2000000101000101010201010100000001015A +:106A3000010101010101010100000100000000014C +:106A40000101010101010101010001010101010137 +:106A50000101010101010101010001010101010127 +:106A60000101010101010101010101010101010116 +:106A70000101010101010100020202020101010103 +:106A800001010101010101020202020202010101F0 +:106A900001020000020200020202020102000000E4 +:106AA00002010202010101020202010201020200CE +:106AB00002010201010101020202010102020202BD +:106AC00000020101020101020202020202020201AD +:106AD00000010102010101020201020202000001A3 +:106AE0000001010201010102020101010101010194 +:106AF0000101010101010102020101010001000087 +:106B00000001010101010101010200020001010077 +:106B10000101010101010101010100000001000169 +:106B20000001010001010102010101000000010159 +:106B3000010101010101010100000100000000014B +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B70000101010101010100020202020101010102 +:106B800001010101010101020202020202010101EF +:106B900001020000020200020202020102000000E3 +:106BA00002010202010202020202010201020200CB +:106BB00002010201010101020202020102020202BB +:106BC00000020101020101020202020202020201AC +:106BD00000010102010101020202020202000001A1 +:106BE0000001010201010102020101010102010192 +:106BF0000101010101010102020101010001010085 +:106C00000001010101010101010200020001010076 +:106C10000101010101010101010100000001000168 +:106C20000001010001010102010101000100010157 +:106C3000010101010101010100000100000000014A +:106C40000101010101010101010101010101010134 +:106C50000101010101010101010101010101010124 +:106C60000101010101010101010101010101010114 +:106C70000101010101010100020202020101010101 +:106C800001010101010101020202020202010201ED +:106C900001020000020200020202020102000000E2 +:106CA00002010202010202020202010201020200CA +:106CB00002010201010101020202020102020202BA +:106CC00000020101020101020202020202020202AA +:106CD00000010102010101020202020202000001A0 +:106CE0000101010201010102020101010102010190 +:106CF0000101010101010102020101010001010084 +:106D00000001010101010101010200020001010075 +:106D10000101010101010101010100000001000167 +:106D20000001010101010102010101000100010155 +:106D30000101010101010101000001000000010148 +:106D40000101010101010101010101010101010133 +:106D50000101010101010101010101010101010123 +:106D60000101010101010101010101010101010113 +:106D700001010101010101000202020202010101FF +:106D800001010101010101020202020202010201EC +:106D900001020000020200020202020202000000E0 +:106DA00002010202010202020202020201020200C8 +:106DB00002010201010101020202020102020202B9 +:106DC00000020102020102020202020202020202A7 +:106DD000000101020101010202020202020000019F +:106DE000010101020101010202010101010201018F +:106DF0000101010101010102020201020001010081 +:106E00000001010101010102010201020001010072 +:106E10000101010101010101010100000001000166 +:106E20000001010101010102020201000100010152 +:106E30000101010101010101000001000000010147 +:106E40000101010101010101010101010101010132 +:106E50000101010101010101010101010101010122 +:106E60000101010101010101010101010101010112 +:106E700001010101010101000202020202020101FD +:106E800001010101010101020202020202010201EB +:106E900001020000020200020202020202000000DF +:106EA00002010202010202020202020202020200C6 +:106EB00002010201020102020202020102020202B6 +:106EC00000020102020102020202020202020202A6 +:106ED000000101020101010202020202020000019E +:106EE000010101020101010202010101020201018D +:106EF0000101010101010102020201020001010080 +:106F00000001010101010102010201020001010071 +:106F10000101010101010101010100000001000165 +:106F20000001010101010102020201010100010150 +:106F30000101010101010101010001000000010145 +:106F40000101010101010101010101010101010131 +:106F50000101010101010102010101010101010120 +:106F60000101010101010101010101010101010111 +:106F700001010101010101000202020202020101FC +:106F800001010101010101020202020202020201E9 +:106F900002020000020200020202020202000000DD +:106FA00002020202010202020202020202020200C4 +:106FB00002010202020102020202020202020202B3 +:106FC00000020202020102020202020202020202A4 +:106FD000000101020101020202020202020000019C +:106FE000010101020101020202010201020201018A +:106FF000010101010101010202020202010101007D +:10700000000101010101010201020102010101006F +:107010000201010101010101010100000001000163 +:10702000000101010101010202020101010101014E +:107030000101010101010101010001000000010144 +:107040000101010101010101010101010101010130 +:10705000010101010101010201010101010101011F +:107060000101010101010101010101010101010110 +:1070700001010101010101000202020202020201FA +:1070800001010101010101020202020202020201E8 +:1070900002020000020200020202020202000000DC +:1070A00002020202020202020202020202020200C2 +:1070B00002020202020202020202020202020202B0 +:1070C00000020202020102020202020202020202A3 +:1070D0000001010202010202020202020200000299 +:1070E0000101010201010202020102010202020188 +:1070F000010101010101010202020202010101007C +:10710000000101010101010201020102010101006E +:10711000020101010101010101010100010200015F +:10712000000101010101010202020101010101014D +:107130000101010101010101010101000101010140 +:10714000010101010101010101010101010101012F +:10715000010101010101010201010101010101011E +:10716000010101010101010101010101010101010F +:1071700001010101010101000202020202020201F9 +:1071800001010101010101020202020202020202E6 +:1071900002020000020200020202020202010000DA +:1071A00002020202020202020202020202020200C1 +:1071B00002020202020202020202020202020202AF +:1071C00000020202020102020202020202020202A2 +:1071D0000001010202010202020202020200000298 +:1071E0000101010201010202020102010202020187 +:1071F000010101010101010202020202010201007A +:10720000000101010101010201020102010101006D +:10721000020101010101010101010101010200015D +:10722000010101010101010202020101010101014B +:10723000010101010101010201010101010101013D +:10724000010101010101010102010101010101012D +:10725000010101010101010201010101010101011D +:10726000010101010101010101010101010101010E +:1072700001010101010101000202020202020201F8 +:1072800001010101010101020202020202020202E5 +:1072900002020000020200020202020202010000D9 +:1072A00002020202020202020202020202020200C0 +:1072B00002020202020202020202020202020202AE +:1072C00000020202020202020202020202020202A0 +:1072D0000001010202010202020202020200000297 +:1072E0000101010201010202020102010202020186 +:1072F0000101010101010102020202020102010079 +:10730000010101010101010201020102010101006B +:10731000020101010101010201010101010200015B +:10732000010101010101010202020101010101014A +:10733000010101010101010201010101010101013C +:10734000010101010101010102010101010101012C +:10735000010101010101010201010101010101011C +:10736000010101010101010101010101010101010D +:1073700001010101010101000202020202020201F7 +:1073800001010101010101020202020202020202E4 +:1073900002020000020200020202020202010000D8 +:1073A00002020202020202020202020202020200BF +:1073B00002020202020202020202020202020202AD +:1073C000000202020202020202020202020202029F +:1073D0000001020202010202020202020200000295 +:1073E0000101010201020202020102010202020184 +:1073F0000101010101010102020202020102010078 +:107400000101010101010202020201020101010068 +:10741000020101010101010201010101010200015A +:107420000101010101010102020201010101010149 +:10743000010101010101010201010101010101013B +:10744000010101010101010102010101010101012B +:10745000010101010101010201010101010101011B +:10746000010101010101010101010101010101010C +:1074700001010101010101000202020202020201F6 +:1074800001010101010101020202020202020202E3 +:1074900002020000020200020202020202010000D7 +:1074A00002020202020202020202020202020200BE +:1074B00002020202020202020202020202020202AC +:1074C000000202020202020202020202020202029E +:1074D0000001020202010202020202020200000294 +:1074E0000101010201020202020102010202020183 +:1074F0000101010101010102020202020102010077 +:107500000101010101010202020201020101010067 +:107510000201010101010102010101010102010158 +:107520000101010101010102020201010101010148 +:10753000010101010101010201010101010101013A +:10754000010101010101010102010101010101012A +:10755000010101010101010201010101010101011A +:10756000010101010101010101010101010101010B +:1075700001010101010101000202020202020201F5 +:1075800001010101010101020202020202020202E2 +:1075900002020000020200020202020202010000D6 +:1075A00002020202020202020202020202020200BD +:1075B00002020202020202020202020202020202AB +:1075C000000202020202020202020202020202029D +:1075D0000001020202010202020202020200000293 +:1075E0000102010201020202020202010202020180 +:1075F0000201010201010102020202020102010173 +:107600000101010101020202020201020101010065 +:107610000201010101010102010101010102010157 +:107620000101010101010102020201010101010147 +:107630000101010101010102010101010101010139 +:107640000101010101010102020101010101010128 +:107650000101010101010102010101010101010119 +:10766000010101010101010101010101010101010A +:1076700001010101010101000202020202020201F4 +:1076800001010101010101020202020202020202E1 +:1076900002020000020200020202020202010000D5 +:1076A00002020202020202020202020202020200BC +:1076B00002020202020202020202020202020202AA +:1076C000000202020202020202020202020202029C +:1076D0000001020202010202020202020200000292 +:1076E000010202020102020202020202020202017D +:1076F0000201010201010102020202020102010172 +:107700000101010101020202020201020101010064 +:107710000201010101010102020201010102010154 +:107720000101010101010102020202010101010145 +:107730000101010101010102010101010101010138 +:107740000101010101010102020101010101010127 +:107750000101010101010102010101010101010118 +:107760000101010101010101010101010101010109 +:1077700001010101010101000202020202020201F3 +:1077800001010101010101020202020202020202E0 +:1077900002020000020200020202020202010000D4 +:1077A00002020202020202020202020202020201BA +:1077B00002020202020202020202020202020202A9 +:1077C000000202020202020202020202020202029B +:1077D0000002020202010202020202020200000290 +:1077E000010202020202020202020202020202017B +:1077F0000201010201010202020202020102010170 +:107800000101010101020202020201020101010063 +:107810000201010101010102020201010102010153 +:107820000101010101010102020202010101010144 +:107830000101010101010202010101010101010136 +:107840000101010101010102020101010101010126 +:107850000101010101010102010101010101010117 +:107860000101010101010102010101010101010107 +:1078700001010101010101000202020202020201F2 +:1078800001010101010101020202020202020202DF +:1078900002020000020200020202020202020000D2 +:1078A00002020202020202020202020202020201B9 +:1078B00002020202020202020202020202020202A8 +:1078C000000202020202020202020202020202029A +:1078D000000202020201020202020202020000028F +:1078E000010202020202020202020202020202017A +:1078F000020101020101020202020202010201016F +:107900000101010101020202020201020102020060 +:107910000201010101010102020201010102010152 +:107920000101010101010102020202010101010143 +:107930000101010101020202010101010101010134 +:107940000101010101010102020101010101010125 +:107950000101010101010102010101010101010116 +:107960000101010101010102010101010101010106 +:1079700001010101010101000202020202020201F1 +:1079800001010101010101020202020202020202DE +:1079900002020000020200020202020202020000D1 +:1079A00002020202020202020202020202020201B8 +:1079B00002020202020202020202020202020202A7 +:1079C0000002020202020202020202020202020299 +:1079D000000202020202020202020202020000028D +:1079E0000102020202020202020202020202020179 +:1079F000020201020101020202020202010201016D +:107A0000010101020102020202020102010202005E +:107A10000201010101010102020201010102010151 +:107A20000101010101010102020202010101010142 +:107A30000101010101020202010102010101010132 +:107A40000101010101010102020101010101010124 +:107A50000101010101010102020101010101010114 +:107A60000101010101010102010101010101010105 +:107A700001010101010101000202020202020201F0 +:107A800001010101010101020202020202020202DD +:107A900002020000020200020202020202020000D0 +:107AA00002020202020202020202020202020201B7 +:107AB00002020202020202020202020202020202A6 +:107AC0000002020202020202020202020202020298 +:107AD000000202020202020202020202020000028C +:107AE0000102020202020202020202020202020277 +:107AF000020201020101020202020202010201016C +:107B0000010101020102020202020102010202005D +:107B1000020101010101020202020101010201014F +:107B20000101010101010102020202010101010141 +:107B30000101010101020202020102010101010130 +:107B40000101010101010102020101010101010123 +:107B50000101010101010202020101010101010112 +:107B60000101010101010102020101010101010103 +:107B700001010101010101000202020202020202EE +:107B800002020201010101020202020202020202D9 +:107B900002020000020200020202020202020100CE +:107BA00002020202020202020202020202020201B6 +:107BB00002020202020202020202020202020202A5 +:107BC0000002020202020202020202020202020297 +:107BD000000202020202020202020202020001028A +:107BE0000102020202020202020202020202020276 +:107BF000020201020101020202020202010201016B +:107C0000010101020102020202020202010202015A +:107C1000020101020101020202020101010201014D +:107C20000101010101010102020202010101010140 +:107C3000010201010202020202010201010101012D +:107C40000101010101010102020101010101010122 +:107C50000101010101010202020101010101010111 +:107C60000101010101010102020101010101010102 +:107C700001010101010101000202020202020202ED +:107C800002020201010101020202020202020202D8 +:107C900002020000020200020202020202020100CD +:107CA00002020202020202020202020202020201B5 +:107CB00002020202020202020202020202020202A4 +:107CC0000002020202020202020202020202020296 +:107CD0000002020202020202020202020200010289 +:107CE0000102020202020202020202020202020275 +:107CF000020201020101020202020202010201016A +:107D00000101010201020202020202020102020159 +:107D1000020101020101020202020101010201014C +:107D2000010101010101020202020201010101013E +:107D3000010201010202020202010201010101012C +:107D40000101010101010102020201010101010120 +:107D5000010201010102020202010101010101010E +:107D60000101010101010102020101010101010101 +:107D700001010101010101000202020202020202EC +:107D800002020201020201020202020202020202D5 +:107D900002020000020200020202020202020100CC +:107DA00002020202020202020202020202020201B4 +:107DB00002020202020202020202020202020202A3 +:107DC0000002020202020202020202020202020295 +:107DD0000002020202020202020202020200010288 +:107DE0000102020202020202020202020202020274 +:107DF0000202010201010202020202020102010169 +:107E00000102010201020202020202020102020157 +:107E1000020101020102020202020101010201014A +:107E2000010101010101020202020201010101013D +:107E3000010202010202020202010201010101012A +:107E4000010101010101020202020201010101011D +:107E50000102020102020202020202010101010109 +:107E600001020101010102020202010101010101FD +:107E700001010101010101000202020202020202EB +:107E800002020202020202020202020202020202D2 +:107E900002020000020200020202020202020100CB +:107EA00002020202020202020202020202020201B3 +:107EB00002020202020202020202020202020202A2 +:107EC0000102020202020202020202020202020293 +:107ED0000002020202020202020202020200010287 +:107EE0000202020202020202020202020202020272 +:107EF0000202010201010202020202020202010167 +:107F00000102010201020202020202020102020156 +:107F10000201010201020202020202010102010148 +:107F2000010101010101020202020202010101013B +:107F30000202020102020202020202010101010127 +:107F4000010101010102020202020201010101011B +:107F50000102020102020202020202010101010108 +:107F600002020201020202020202020101010101F7 +:107F700001010101010101000202020202020202EA +:107F800002020202020202020202020202020202D1 +:107F900002020000020200020202020202020201C8 +:107FA00002020202020202020202020202020201B2 +:107FB00002020202020202020202020202020202A1 +:107FC0000102020202020202020202020202020292 +:107FD0000102020202020202020202020201010284 +:107FE0000202020202020202020202020202020271 +:107FF0000202010201010202020202020202020165 +:108000000102010201020202020202020102020155 +:108010000201010201020202020202010102010147 +:108020000101010101010202020202020201010238 +:108030000202020202020202020202010101010125 +:108040000101010101020202020202020201020216 +:108050000202020202020202020202010101010105 +:1080600002020201020202020202020101010101F6 +:1080700001010101010101000202020202020202E9 +:1080800002020202020202020202020202020202D0 +:1080900002020000020200020202020202020201C7 +:1080A00002020202020202020202020202020202B0 +:1080B00002020202020202020202020202020202A0 +:1080C0000102020202020202020202020202020291 +:1080D0000102020202020202020202020201010283 +:1080E0000202020202020202020202020202020270 +:1080F0000202020201010202020202020202020163 +:108100000102010202020202020202020202020152 +:108110000201010202020202020202020102010243 +:108120000101010101020202020202020201020235 +:108130000202020202020202020202010101010124 +:108140000102010102020202020202020201020213 +:108150000202020202020202020202020201010201 +:1081600002020202020202020202020201010101F3 +:1081700001010101010101000202020202020202E8 +:1081800002020202020202020202020202020202CF +:1081900002020000020200020202020202020202C5 +:1081A00002020202020202020202020202020202AF +:1081B000020202020202020202020202020202029F +:1081C0000102020202020202020202020202020290 +:1081D0000102020202020202020202020201010282 +:1081E000020202020202020202020202020202026F +:1081F0000202020202020202020202020202020160 +:108200000102010202020202020202020202020151 +:108210000201010202020202020202020102010242 +:108220000101010101020202020202020201020234 +:108230000202020202020202020202010101010123 +:10824000020202020202020202020202020202020E +:1082500002020202020202020202020202010202FF +:1082600002020202020202020202020202010101F1 +:1082700001020101010101000202020202020202E6 +:1082800002020202020202020202020202020202CE +:1082900002020100020200020202020202020202C3 +:1082A00002020202020202020202020202020202AE +:1082B000020202020202020202020202020202029E +:1082C000010202020202020202020202020202028F +:1082D0000102020202020202020202020201010281 +:1082E000020202020202020202020202020202026E +:1082F000020202020202020202020202020202015F +:108300000102010202020202020202020202020150 +:108310000201010202020202020202020202010240 +:108320000101010101020202020202020202020232 +:108330000202020202020202020202020101010121 +:10834000020202020202020202020202020202020D +:1083500002020202020202020202020202020202FD +:1083600002020202020202020202020202020201EE +:1083700002020101020202000202020202020202E1 +:1083800002020202020202020202020202020202CD +:1083900002020101020200020202020202020202C1 +:1083A00002020202020202020202020202020202AD +:1083B000020202020202020202020202020202029D +:1083C000010202020202020202020202020202028E +:1083D0000102020202020202020202020201010280 +:1083E000020202020202020202020202020202026D +:1083F000020202020202020202020202020202015E +:10840000010202020202020202020202020202014E +:10841000020202020202020202020202020201023D +:10842000010202010102020202020202020202022F +:108430000202020202020202020202020101010120 +:10844000020202020202020202020202020202020C +:1084500002020202020202020202020202020202FC +:1084600002020202020202020202020202020202EC +:1084700002020201020202000202020202020202DF +:1084800002020202020202020202020202020202CC +:1084900002020202020200020202020202020202BE +:1084A00002020202020202020202020202020202AC +:1084B000020202020202020202020202020202029C +:1084C000020202020202020202020202020202028C +:1084D000010202020202020202020202020202027D +:1084E000020202020202020202020202020202026C +:1084F000020202020202020202020202020202015D +:10850000010202020202020202020202020202014D +:10851000020202020202020202020202020201023C +:10852000010202010202020202020202020202022D +:10853000020202020202020202020202020101021D +:10854000020202020202020202020202020202020B +:1085500002020202020202020202020202020202FB +:1085600002020202020202020202020202020202EB +:1085700002020202020202000202020202020202DD +:1085800002020202020202020202020202020202CB +:1085900002020202020200020202020202020202BD +:1085A00002020202020202020202020202020202AB +:1085B000020202020202020202020202020202029B +:1085C000020202020202020202020202020202028B +:1085D000010202020202020202020202020202027C +:1085E000020202020202020202020202020202026B +:1085F000020202020202020202020202020202025B +:10860000020202020202020202020202020202014B +:10861000020202020202020202020202020201023B +:10862000010202010202020202020202020202022C +:10863000020202020202020202020202020202021A +:10864000020202020202020202020202020202020A +:1086500002020202020202020202020202020202FA +:1086600002020202020202020202020202020202EA +:1086700002020202020202000202020202020202DC +:1086800002020202020202020202020202020202CA +:1086900002020202020200020202020202020202BC +:1086A00002020202020202020202020202020202AA +:1086B000020202020202020202020202020202029A +:1086C000020202020202020202020202020202028A +:1086D000020202020202020202020202020202027A +:1086E000020202020202020202020202020202026A +:1086F000020202020202020202020202020202025A +:10870000020202020202020202020202020202014A +:10871000020202020202020202020202020201023A +:10872000010202010202020202020202020202022B +:108730000202020202020202020202020202020219 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202000202020202020202DB +:1087800002020202020202020202020202020202C9 +:1087900002020202020200020202020202020202BB +:1087A00002020202020202020202020202020202A9 +:1087B0000202020202020202020202020202020299 +:1087C0000202020202020202020202020202020289 +:1087D0000202020202020202020202020202020279 +:1087E0000202020202020202020202020202020269 +:1087F0000202020202020202020202020202020259 +:108800000202020202020202020202020202020149 +:108810000202020202020202020202020202020238 +:10882000010202010202020202020202020202022A +:108830000202020202020202020202020202020218 +:108840000202020202020202020202020202020208 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202000202020202020202DA +:1088800002020202020202020202020202020202C8 +:1088900002020202020200020202020202020202BA +:1088A00002020202020202020202020202020202A8 +:1088B0000202020202020202020202020202020298 +:1088C0000202020202020202020202020202020288 +:1088D0000202020202020202020202020202020278 +:1088E0000202020202020202020202020202020268 +:1088F0000202020202020202020202020202020258 +:108900000202020202020202020202020202020148 +:108910000202020202020202020202020202020237 +:108920000202020202020202020202020202020227 +:108930000202020202020202020202020202020217 +:108940000202020202020202020202020202020207 +:1089500002020202020202020202020202020202F7 +:1089600002020202020202020202020202020202E7 +:1089700002020202020202000202020202020202D9 +:1089800002020202020202020202020202020202C7 +:1089900002020202020200020202020202020202B9 +:1089A00002020202020202020202020202020202A7 +:1089B0000202020202020202020202020202020297 +:1089C0000202020202020202020202020202020287 +:1089D0000202020202020202020202020202020277 +:1089E0000202020202020202020202020202020267 +:1089F0000202020202020202020202020202020257 +:108A00000202020202020202020202020202020147 +:108A10000202020202020202020202020202020236 +:108A20000202020202020202020202020202020226 +:108A30000202020202020202020202020202020216 +:108A40000202020202020202020202020202020206 +:108A500002020202020202020202020202020202F6 +:108A600002020202020202020202020202020202E6 +:108A700002020202020202000202020202020202D8 +:108A800002020202020202020202020202020202C6 +:108A900002020202020200020202020202020202B8 +:108AA00002020202020202020202020202020202A6 +:108AB0000202020202020202020202020202020296 +:108AC0000202020202020202020202020202020286 +:108AD0000202020202020202020202020202020276 +:108AE0000202020202020202020202020202020266 +:108AF0000202020202020202020202020202020256 +:108B00000202020202020202020202020202020245 +:108B10000202020202020202020202020202020235 +:108B20000202020202020202020202020202020225 +:108B30000202020202020202020202020202020215 +:108B40000202020202020202020202020202020205 +:108B500002020202020202020202020202020202F5 +:108B600002020202020202020202020202020202E5 +:108B700002020202020202000202020202020202D7 +:108B800002020202020202020202020202020202C5 +:108B900002020202020200020202020202020202B7 +:108BA00002020202020202020202020202020202A5 +:108BB0000202020202020202020202020202020295 +:108BC0000202020202020202020202020202020285 +:108BD0000202020202020202020202020202020275 +:108BE0000202020202020202020202020202020265 +:108BF0000202020202020202020202020202020255 +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202000202020202020202D6 +:108C800002020202020202020202020202020202C4 +:108C900002020202020200020202020202020202B6 +:108CA00002020202020202020202020202020202A4 +:108CB0000202020202020202020202020202020294 +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020202020202020202020274 +:108CE0000202020202020202020202020202020264 +:108CF0000202020202020202020202020202020254 +:108D00000202020202020202020202020202020243 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202000202020202020202D5 +:108D800002020202020202020202020202020202C3 +:108D900002020202020200020202020202020202B5 +:108DA00002020202020202020202020202020202A3 +:108DB0000202020202020202020202020202020293 +:108DC0000202020202020202020202020202020283 +:108DD0000202020202020202020202020202020273 +:108DE0000202020202020202020202020202020263 +:108DF0000202020202020202020202020202020253 +:108E00000202020202020202020202020202020242 +:108E10000202020202020202020202020202020232 +:108E20000202020202020202020202020202020222 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202000202020202020202D4 +:108E800002020202020202020202020202020202C2 +:108E900002020202020200020202020202020202B4 +:108EA00002020202020202020202020202020202A2 +:108EB0000202020202020202020202020202020292 +:108EC0000202020202020202020202020202020282 +:108ED0000202020202020202020202020202020272 +:108EE0000202020202020202020202020202020262 +:108EF0000202020202020202020202020202020252 +:108F00000202020202020202020202020202020241 +:108F10000202020202020202020202020202020231 +:108F20000202020202020202020202020202020221 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202000202020202020202D3 +:108F800002020202020202020202020202020202C1 +:108F900002020202020200020202020202020202B3 +:108FA00002020202020202020202020202020202A1 +:108FB0000202020202020202020202020202020291 +:108FC0000202020202020202020202020202020281 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202020202020261 +:108FF0000202020202020202020202020202020251 +:109000000202020202020202020202020202020240 +:109010000202020202020202020202020202020230 +:109020000202020202020202020202020202020220 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020200020202020201020202B3 +:1090A00001020202020202020202020202020202A1 +:1090B0000202020202020202020202020202020290 +:1090C0000202020202020202020202020202020280 +:1090D0000202020202020202020202020202020270 +:1090E0000202020202020202020202020202020260 +:1090F0000202020202020202020202020202020250 +:10910000020202020202020202020202020202023F +:10911000020202020202020202020202020202022F +:10912000020202020202020202020202020202021F +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020201010200020202020201020202B4 +:1091A00001020201020202020202020202020202A1 +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D000020202020202020202020202020202026F +:1091E000020202020202020202020202020202025F +:1091F000020202020202020202020202020202024F +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202010101010101010101C7 +:1092900001010101010101020202010201020202B7 +:1092A00001020201020202020202020202020202A0 +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202020202025E +:1092F000020202020202020202020202020202024E +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202010101010101010101C6 +:1093900001010101010101020202010201020202B6 +:1093A00001010101020202020202020202020202A1 +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202020202025D +:1093F000020202020202020202020202020202024D +:10940000020202020202020202020202020202023C +:10941000020202020202020202020202020202022C +:10942000020202020202020202020202020202021C +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202010101010101010101C5 +:1094900001010101010101020201010201020201B7 +:1094A00001010101020202020202020202020202A0 +:1094B000020202020202020202020202020202018D +:1094C000020202020202020202020202020202027C +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202020202020202020202024C +:10950000020202020202020202020202020202023B +:10951000020202020202020202020202020202022B +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202010101010101010101C4 +:1095900001010101010101010101010101010101BB +:1095A00001010101010101020202020202020102A3 +:1095B000020202020202020202020202020102028C +:1095C000020202020202020202020202020202027B +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020202020202020202022A +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202010101010101010101C3 +:1096900001010101010101010101010101010101BA +:1096A00001010101010101020202020202010202A2 +:1096B000020202020202020202020202010201018D +:1096C000020202010202020202020202020202027B +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202010101010101010101C2 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101020201020102020102A3 +:1097B000010202010202020202020202020102018D +:1097C000020101020102020202020202020202027C +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:109810000202020202020202020202020202020228 +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202010101010101010101C1 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101020202020201010102A2 +:1098B000020101020202020102020202010101018F +:1098C000020202010201020202020202020202027A +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202010101010101010101C0 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101020201020102010101A3 +:1099B0000102020101010202010101010101010193 +:1099C000010101010102010202020202020102027E +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020202020226 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202010101010101010101BF +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010102A5 +:109AB0000101010102020101020202020101010190 +:109AC000020101010101020202020101020201017F +:109AD0000202020102020202020202020202020267 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202010101010101010101BE +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101020201020101010101A2 +:109BB0000101010101010201010101010101010194 +:109BC000010101010101010202020202010102027E +:109BD0000202010202020202020202020202020266 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202010101010101010101BD +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101020101010201010182 +:109CD0000101020101020202020202020202020268 +:109CE0000202020202020202020202020202020254 +:109CF0000202020202020202020202020202020244 +:109D00000202020202020202020202020202020233 +:109D10000202020202020202020202020202020223 +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020202020202020202020202020202E3 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202010101010101010101BC +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010102010201010101010181 +:109DD0000202010102010102020202020202020267 +:109DE0000202020202020202020202020202020253 +:109DF0000202020202020202020202020202020243 +:109E00000202020202020202020202020202020232 +:109E10000202020202020202020202020202020222 +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202020202020202E2 +:109E600002020202020202020202020202020202D2 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202010101010101010101BB +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101020101010101010181 +:109ED0000101010101020202020202020202020267 +:109EE0000202020202020202020202020202020252 +:109EF0000202020202020202020202020202020242 +:109F00000202020202020202020202020202020231 +:109F10000202020202020202020202020202020221 +:109F20000202020202020202020202020202020211 +:109F30000202020202020202020202020202020201 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202020202020202E1 +:109F600002020202020202020202020202020202D1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202010101010101010101BA +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD000010101010101010202020102010202026A +:109FE0000202020202020202020202020202020251 +:109FF0000202020202020202020202020202020241 +:10A000000202020202020202020202020202020230 +:10A010000202020202020202020202020202020220 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020202020202020202020202020202D0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202010101010101010101B9 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D000010101010101010202020101010202016B +:10A0E0000202020102020202020202020202020251 +:10A0F0000202020202020202020202020202020240 +:10A10000020202020202020202020202020202022F +:10A11000020202020202020202020202020202021F +:10A12000020202020202020202020202020202020F +:10A1300002020202020202020202020202020202FF +:10A1400002020202020202020202020202020202EF +:10A1500002020202020202020202020202020202DF +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202010101010101010101B8 +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010102020101010202016B +:10A1E0000101010101020202020202020201020255 +:10A1F000020202020202020202020202020202023F +:10A20000020202020202020202020202020202022E +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202020E +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202010101010101010101B7 +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E0000101010101010101010202020102010259 +:10A2F000020202020202020202020202020202023E +:10A30000020202020202020202020202020202022D +:10A31000020202020202020202020202020202021D +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202010101010101010101B6 +:10A3900001010101010101010101010101010101AD +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E0000101010101010102020201020201020157 +:10A3F000010202010202020202020202020202023F +:10A40000020202020202020202020202020202022C +:10A41000020202020202020202020202020202021C +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202010101010101010101B5 +:10A4900001010101010101010101010101010101AC +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101018C +:10A4C000010101010101010101010101010101017C +:10A4D000010101010101010101010101010101016C +:10A4E0000101010101010101010202010101010259 +:10A4F000020101020202020202020202020202023E +:10A50000020202020202020202020202020202022B +:10A51000020202020202020202020202020202021B +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202010101010101010101B4 +:10A5900001010101010101010101010101010101AB +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C000010101010101010101010101010101017B +:10A5D000010101010101010101010101010101016B +:10A5E000010101010101010101010102010101015A +:10A5F0000102020101010102020202020202020240 +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202010101010101010101B3 +:10A6900001010101010101010101010101010101AA +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000010101010101010101010101010101017A +:10A6D000010101010101010101010101010101016A +:10A6E0000101010101010101010201010101010159 +:10A6F0000101010102020201020202010201020241 +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202010101010101010101B2 +:10A7900001010101010101010101010101010101A9 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101020101010201020245 +:10A80000020202010202020202010201020202022B +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202010101010101010101B1 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010102020202020201010230 +:10A910000102020202020202020202020202020218 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202010101010101010101B0 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA0000010101010101010202010201020202022F +:10AA10000202010102020202020202020202020218 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202010101010101010101AF +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB1000010102020101010202020202020202021A +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202010101010101010101AE +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010185 +:10ABC0000101010101010101010101010101010175 +:10ABD0000101010101010101010101010101010165 +:10ABE0000101010101010101010101010101010155 +:10ABF0000101010101010101010101010101010145 +:10AC0000010101010101010202010201020101022F +:10AC10000102010102020202020202020201020218 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202010101010101010101AD +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010184 +:10ACC0000101010101010101010101010101010174 +:10ACD0000101010101010101010101010101010164 +:10ACE0000101010101010101010101010101010154 +:10ACF0000101010101010101010101010101010144 +:10AD00000101010101010101010101010101010133 +:10AD1000010101010101010202020202020102021B +:10AD20000202020202020202020102020202020204 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202010101010101010101AC +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010183 +:10ADC0000101010101010101010101010101010173 +:10ADD0000101010101010101010101010101010163 +:10ADE0000101010101010101010101010101010153 +:10ADF0000101010101010101010101010101010143 +:10AE00000101010101010101010101010101010132 +:10AE1000010101010101010202010202020102011C +:10AE20000202020202020201010201020202020205 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202010101010101010101AB +:10AE900001010101010101010101010101010101A2 +:10AEA0000101010101010101010101010101010192 +:10AEB0000101010101010101010101010101010182 +:10AEC0000101010101010101010101010101010172 +:10AED0000101010101010101010101010101010162 +:10AEE0000101010101010101010101010101010152 +:10AEF0000101010101010101010101010101010142 +:10AF00000101010101010101010101010101010131 +:10AF10000101010101010101010101010101010121 +:10AF2000010101010101010202010201010101010E +:10AF300001010101010101020202020202020202F8 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202010101010101010101AA +:10AF900001010101010101010101010101010101A1 +:10AFA0000101010101010101010101010101010191 +:10AFB0000101010101010101010101010101010181 +:10AFC0000101010101010101010101010101010171 +:10AFD0000101010101010101010101010101010161 +:10AFE0000101010101010101010101010101010151 +:10AFF0000101010101010101010101010101010141 +:10B000000101010101010101010101010101010130 +:10B010000101010101010101010101010101010120 +:10B02000010101010101010101010102020202020B +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202010101010101010101A9 +:10B0900001010101010101010101010101010101A0 +:10B0A0000101010101010101010101010101010190 +:10B0B0000101010101010101010101010101010180 +:10B0C0000101010101010101010101010101010170 +:10B0D0000101010101010101010101010101010160 +:10B0E0000101010101010101010101010101010150 +:10B0F0000101010101010101010101010101010140 +:10B10000010101010101010101010101010101012F +:10B11000010101010101010101010101010101011F +:10B12000010101010101010101010101010101010F +:10B1300001010101010101020202020202020202F6 +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B1800002020202020202010101010101010101A8 +:10B19000010101010101010101010101010101019F +:10B1A000010101010101010101010101010101018F +:10B1B000010101010101010101010101010101017F +:10B1C000010101010101010101010101010101016F +:10B1D000010101010101010101010101010101015F +:10B1E000010101010101010101010101010101014F +:10B1F000010101010101010101010101010101013F +:10B20000010101010101010101010101010101012E +:10B21000010101010101010101010101010101011E +:10B22000010101010101010101010101010101010E +:10B2300001010101010101010202010202020202F7 +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B2800002020202020202010101010101010101A7 +:10B29000010101010101010101010101010101019E +:10B2A000010101010101010101010101010101018E +:10B2B000010101010101010101010101010101017E +:10B2C000010101010101010101010101010101016E +:10B2D000010101010101010101010101010101015E +:10B2E000010101010101010101010101010101014E +:10B2F000010101010101010101010101010101013E +:10B30000010101010101010101010101010101012D +:10B31000010101010101010101010101010101011D +:10B32000010101010101010101010101010101010D +:10B3300001010101010101010101010101010101FD +:10B3400001010101010101020102020202020202E5 +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B3800002020202020202010101010101010101A6 +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010101010101010101018D +:10B3B000010101010101010101010101010101017D +:10B3C000010101010101010101010101010101016D +:10B3D000010101010101010101010101010101015D +:10B3E000010101010101010101010101010101014D +:10B3F000010101010101010101010101010101013D +:10B40000010101010101010101010101010101012C +:10B41000010101010101010101010101010101011C +:10B42000010101010101010101010101010101010C +:10B4300001010101010101010101010101010101FC +:10B4400001010101010101010201010101010101EB +:10B4500001010101010101020202020202020202D3 +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B4800002020202020202010101010101010101A5 +:10B49000010101010101010101010101010101019C +:10B4A000010101010101010101010101010101018C +:10B4B000010101010101010101010101010101017C +:10B4C000010101010101010101010101010101016C +:10B4D000010101010101010101010101010101015C +:10B4E000010101010101010101010101010101014C +:10B4F000010101010101010101010101010101013C +:10B50000010101010101010101010101010101012B +:10B51000010101010101010101010101010101011B +:10B52000010101010101010101010101010101010B +:10B5300001010101010101010101010101010101FB +:10B5400001010101010101020102020202020202E3 +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B5800002020202020202010101010101010101A4 +:10B59000010101010101010101010101010101019B +:10B5A000010101010101010101010101010101018B +:10B5B000010101010101010101010101010101017B +:10B5C000010101010101010101010101010101016B +:10B5D000010101010101010101010101010101015B +:10B5E000010101010101010101010101010101014B +:10B5F000010101010101010101010101010101013B +:10B60000010101010101010101010101010101012A +:10B61000010101010101010101010101010101011A +:10B62000010101010101010101010101010101010A +:10B6300001010101010101010101010101010101FA +:10B6400001010101010101010101010101010101EA +:10B6500001010101010101010202020202020202D2 +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B6800002020202020202010101010101010101A3 +:10B69000010101010101010101010101010101019A +:10B6A000010101010101010101010101010101018A +:10B6B000010101010101010101010101010101017A +:10B6C000010101010101010101010101010101016A +:10B6D000010101010101010101010101010101015A +:10B6E000010101010101010101010101010101014A +:10B6F000010101010101010101010101010101013A +:10B700000101010101010101010101010101010129 +:10B710000101010101010101010101010101010119 +:10B720000101010101010101010101010101010109 +:10B7300001010101010101010101010101010101F9 +:10B7400001010101010101010101010101010101E9 +:10B7500001010101010101010101010101010101D9 +:10B7600001010101010101020202020202020202C0 +:10B7700002020202020202020202020202020202A9 +:10B7800002020202020202010101010101010101A2 +:10B790000101010101010101010101010101010199 +:10B7A0000101010101010101010101010101010189 +:10B7B0000101010101010101010101010101010179 +:10B7C0000101010101010101010101010101010169 +:10B7D0000101010101010101010101010101010159 +:10B7E0000101010101010101010101010101010149 +:10B7F0000101010101010101010101010101010139 +:10B800000101010101010101010101010101010128 +:10B810000101010101010101010101010101010118 +:10B820000101010101010101010101010101010108 +:10B8300001010101010101010101010101010101F8 +:10B8400001010101010101010101010101010101E8 +:10B8500001010101010101010101010101010101D8 +:10B8600001010101010101010101010101010101C8 +:10B8700001010101010101020202020202020202AF +:10B8800002020202020202010101010101010101A1 +:10B890000101010101010101010101010101010198 +:10B8A0000101010101010101010101010101010188 +:10B8B0000101010101010101010101010101010178 +:10B8C0000101010101010101010101010101010168 +:10B8D0000101010101010101010101010101010158 +:10B8E0000101010101010101010101010101010148 +:10B8F0000101010101010101010101010101010138 +:10B900000101010101010101010101010101010127 +:10B910000101010101010101010101010101010117 +:10B920000101010101010101010101010101010107 +:10B9300001010101010101010101010101010101F7 +:10B9400001010101010101010101010101010101E7 +:10B9500001010101010101010101010101010101D7 +:10B9600001010101010101020202020202020202BE +:10B9700002020202020202020202020202020202A7 +:10B9800002020202020202010101010101010101A0 +:10B990000101010101010101010101010101010197 +:10B9A0000101010101010101010101010101010187 +:10B9B0000101010101010101010101010101010177 +:10B9C0000101010101010101010101010101010167 +:10B9D0000101010101010101010101010101010157 +:10B9E0000101010101010101010101010101010147 +:10B9F0000101010101010101010101010101010137 +:10BA00000101010101010101010101010101010126 +:10BA10000101010101010101010101010101010116 +:10BA20000101010101010101010101010101010106 +:10BA300001010101010101010101010101010101F6 +:10BA400001010101010101010101010101010101E6 +:10BA500001010101010101010101010101010101D6 +:10BA600001010101010101010101010101010101C6 +:10BA700001010101010101020202020202020202AD +:10BA8000020202020202020101010101010101019F +:10BA90000101010101010101010101010101010196 +:10BAA0000101010101010101010101010101010186 +:10BAB0000101010101010101010101010101010176 +:10BAC0000101010101010101010101010101010166 +:10BAD0000101010101010101010101010101010156 +:10BAE0000101010101010101010101010101010146 +:10BAF0000101010101010101010101010101010136 +:10BB00000101010101010101010101010101010125 +:10BB10000101010101010101010101010101010115 +:10BB20000101010101010101010101010101010105 +:10BB300001010101010101010101010101010101F5 +:10BB400001010101010101010101010101010101E5 +:10BB500001010101010101010101010101010101D5 +:10BB600001010101010101010101010101010101C5 +:10BB700001010101010101020202020202020202AC +:10BB8000020202020202020101010101010101019E +:10BB90000101010101010101010101010101010195 +:10BBA0000101010101010101010101010101010185 +:10BBB0000101010101010101010101010101010175 +:10BBC0000101010101010101010101010101010165 +:10BBD0000101010101010101010101010101010155 +:10BBE0000101010101010101010101010101010145 +:10BBF0000101010101010101010101010101010135 +:10BC00000101010101010101010101010101010124 +:10BC10000101010101010101010101010101010114 +:10BC20000101010101010101010101010101010104 +:10BC300001010101010101010101010101010101F4 +:10BC400001010101010101010101010101010101E4 +:10BC500001010101010101010101010101010101D4 +:10BC600001010101010101010101010101010101C4 +:10BC700001010101010101020101010101010102B2 +:10BC8000020202020202020101010101010101019D +:10BC90000101010101010101010101010101010194 +:10BCA0000101010101010101010101010101010184 +:10BCB0000101010101010101010101010101010174 +:10BCC0000101010101010101010101010101010164 +:10BCD0000101010101010101010101010101010154 +:10BCE0000101010101010101010101010101010144 +:10BCF0000101010101010101010101010101010134 +:10BD00000101010101010101010101010101010123 +:10BD10000101010101010101010101010101010113 +:10BD20000101010101010101010101010101010103 +:10BD300001010101010101010101010101010101F3 +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101020101010101010101B2 +:10BD800001010101010101010101010101010101A3 +:10BD90000101010101010101010101010101010193 +:10BDA0000101010101010101010101010101010183 +:10BDB0000101010101010101010101010101010173 +:10BDC0000101010101010101010101010101010163 +:10BDD0000101010101010101010101010101010153 +:10BDE0000101010101010101010101010101010143 +:10BDF0000101010101010101010101010101010133 +:10BE00000101010101010101010101010101010122 +:10BE10000101010101010101010101010101010112 +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101020101010101010101B1 +:10BE800001010101010101010101010101010101A2 +:10BE90000101010101010101010101010101010192 +:10BEA0000101010101010101010101010101010182 +:10BEB0000101010101010101010101010101010172 +:10BEC0000101010101010101010101010101010162 +:10BED0000101010101010101010101010101010152 +:10BEE0000101010101010101010101010101010142 +:10BEF0000101010101010101010101010101010132 +:10BF00000101010101010101010101010101010121 +:10BF10000101010101010101010101010101010111 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101020101010101010101B0 +:10BF800001010101010101010101010101010101A1 +:10BF90000101010101010101010101010101010191 +:10BFA0000101010101010101010101010101010181 +:10BFB0000101010101010101010101010101010171 +:10BFC0000101010101010101010101010101010161 +:10BFD0000101010101010101010101010101010151 +:10BFE0000101010101010101010101010101010141 +:10BFF0000101010101010101010101010101010131 +:10C000000101010101010101010101010101010120 +:10C010000101010101010101010101010101010110 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101020101010101010101AF +:10C0800001010101010101010101010101010101A0 +:10C090000101010101010102020202020202020287 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C1700002020202020202000000000000000000B1 +:10C1800000000000000000010101010101010101A6 +:10C190000101010101010100000000000000000098 +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000202020202020202026D +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C2700002020202020202000000000000000000B0 +:10C2800000000000000000010101010101010101A5 +:10C290000101010101010100000000000000000097 +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000202020202020202026C +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202000000000000000000DF +:10C3500000000000000000020202020202020202CB +:10C3600002020202020202020202020202020202AD +:10C3700002020202020202000000000000000000AF +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C480000000000000000066000000000000000046 +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000010000000000000000007B +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000010000000000000000007A +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E0000000000001000000000000010000000049 +:10C5F000000000000000000000000000000000003B +:10C600000000000000000000000000000000010029 +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A0000000000000000000010000000000000089 +:10C6B0000000000000000100000000000000010078 +:10C6C0000100000000000000000000010000000068 +:10C6D0000000000000000100000000000000010058 +:10C6E0000000000001000000000000010000000048 +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000010000010027 +:10C710000001000000000000000000000000000018 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000100F8 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000100A8 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000010000000000010087 +:10C7B0000100000000010100000000000000010075 +:10C7C0000100000000000001000001010000010064 +:10C7D0000000000000000100000000010000010056 +:10C7E0000000000001000000000000010000000047 +:10C7F0000000000000010000010000000000000037 +:10C800000000000000000000000000010000010026 +:10C810000001000000000000000000000000010016 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000100F7 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800001000001000000000000000000000100A5 +:10C890000000000000000000000000000001000097 +:10C8A0000000000000000000010000000000010086 +:10C8B0000100000000010100000000000000010074 +:10C8C0000100000000000001000001010000010063 +:10C8D0000000010000000100000000010000010054 +:10C8E0000000010001000000000000010100010043 +:10C8F0000000000000010000010000000000000036 +:10C900000000000000000000000000010000010025 +:10C910000001000100000000000000000000010014 +:10C920000000000000000000000000000000010006 +:10C9300000000000000000000000000000000100F6 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800001000001000000000000000000000100A4 +:10C990000001000000000000000000000001000095 +:10C9A0000000000000000000010000000000010085 +:10C9B0000100000000010100010000000000010072 +:10C9C0000100000000000001000001010000010062 +:10C9D0000100010000000100000000010000010052 +:10C9E0000000010001000000000000010100010042 +:10C9F0000000000000010000010000000000000035 +:10CA00000000000000000000000000010000010024 +:10CA10000001000100000000000000000000010013 +:10CA20000000000000000000000000000000010005 +:10CA300000000000000000000000000000000100F5 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000100D5 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800001000001000000000000000000000100A3 +:10CA90000001000000000000000000000001000094 +:10CAA0000000000000000000010000000000010084 +:10CAB0000100000000010100010000000000010071 +:10CAC0000100000000000001000001010000010061 +:10CAD0000100010000000101000000010000010050 +:10CAE0000000010001000000000000010100010041 +:10CAF0000000000000010000010000000000000034 +:10CB00000000000000000000000000010000010023 +:10CB10000001000100000000000000000000010012 +:10CB20000000000000000000000000000000010004 +:10CB300000000000000000000000000000000100F4 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000100D4 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800001000101000000000000000000000100A1 +:10CB90000101000000000000000000000001000092 +:10CBA0000000000000000000010000000101010180 +:10CBB0000100000000010100010000000000010070 +:10CBC0000100000000000001000001010000010060 +:10CBD000010001010001010100000001000001004D +:10CBE0000000010001000000000000010100010040 +:10CBF0000000000000010000010000000000000033 +:10CC00000000000000000000000000010000010022 +:10CC10000001000100000000000000000000010011 +:10CC20000000000000000000000000000000010003 +:10CC300000000000000000000000000000000100F3 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000100D3 +:10CC600000000000000000000000000000000100C3 +:10CC700000000000000000000000000000000000B4 +:10CC800001000101000000000000000000000100A0 +:10CC90000101000000000000000000000001000190 +:10CCA000000000000100000001000000010101017E +:10CCB000010000000001010001000000000001016E +:10CCC000010000000001000100000101000001005E +:10CCD000010001010001010100000001000001004C +:10CCE000000001000100000000000001010101003E +:10CCF0000000000000010000010000000000010031 +:10CD00000000000000000000000000010000010120 +:10CD10000001000100000000000000000000010010 +:10CD20000000000000000000000000000000010002 +:10CD300000000000000000000000000000000100F2 +:10CD400000000000000000000000000000000000E3 +:10CD500001000000000000000000000000000100D1 +:10CD600000000000000000000000000000000100C2 +:10CD700000000000000000000000000000000000B3 +:10CD8000010001010000000000000000000001019E +:10CD9000010100000000000000000000000100018F +:10CDA000000000000100000001000000010101017D +:10CDB000010000000001010001000000000001016D +:10CDC000010000000001000100000101000001005D +:10CDD000010001010101010100000001000001004A +:10CDE000000001000100000000000001010101003D +:10CDF0000000000000010000010000000000010030 +:10CE0000000000000000000000000001010001011E +:10CE1000000100010000000000000000000001000F +:10CE20000000000000000000000000000000010001 +:10CE300000000000000000000000000000000100F1 +:10CE400000000000000000000000000000000000E2 +:10CE500001000000000000000000000000000100D0 +:10CE600000000000000000000000000000000100C1 +:10CE700000000000000000000000000000000000B2 +:10CE8000010001010000000000000000000001019D +:10CE9000010100000000000000000000000100018E +:10CEA000010000000100000001000000010101017B +:10CEB000010000000001010001000000010001016B +:10CEC000010000000001000100000101000001005C +:10CED0000100010101010101000000010000010049 +:10CEE000000001000100000000000001010101003C +:10CEF000000000000001000001000000000001002F +:10CF0000000000000000000000000001010001011D +:10CF1000000100010001000000000000000001000D +:10CF20000000000000000000000000000000010000 +:10CF300000000000000000000000000000010100EF +:10CF400000000000000000000000000000000000E1 +:10CF500001000000000000000000000000000100CF +:10CF600000000000000000000000000000000100C0 +:10CF700000000000000000000000000000000000B1 +:10CF8000010001010000000000000000000001019C +:10CF9000010100000000000000000000000100018D +:10CFA0000100010001000000010000000101010179 +:10CFB0000101000000010100010000000100010169 +:10CFC000010000000001000100000101010001005A +:10CFD0000100010101010101000000010000010048 +:10CFE000000001000100000000000001010101003B +:10CFF000000000000001000001000000000001002E +:10D00000000000000000000000000001010001011C +:10D01000000100010001000000000000010001000B +:10D0200000000000000000000000000000000100FF +:10D0300000000000000000000000000000010100EE +:10D0400000000000000000000000000000000100DF +:10D0500001000000000000000000000000000100CE +:10D0600000000000000000000000000000000100BF +:10D0700000000000000000000000000000000000B0 +:10D08000010001010000000000000000000001019B +:10D09000010100000000000000000000000100018C +:10D0A0000100010001000000010000000101010178 +:10D0B0000101000000010100010000000100010168 +:10D0C0000100000001010001000001010100010058 +:10D0D0000100010101010101000000010001010046 +:10D0E000000001000100000000000001010101003A +:10D0F000000000000001000001000000000001012C +:10D10000010000000000000000000001010001011A +:10D110000001000100010000010000000100010009 +:10D1200000000000000000000000000000000100FE +:10D1300000000000000000000000000000010100ED +:10D1400000000000000000000000000000000100DE +:10D1500001000000000000000000000000000100CD +:10D1600000000000000000000000000000000100BE +:10D1700000000000000000000000000000000000AF +:10D18000010001010000000000000000000001019A +:10D19000010100000000000000000000000100018B +:10D1A0000100010001000000010000000101010177 +:10D1B0000101000100010100010000000100010166 +:10D1C0000100000001010001000001010100010057 +:10D1D0000100010101010101000000010001010045 +:10D1E0000000010001010000000000010101010038 +:10D1F000000000000001000001000000000001012B +:10D200000100000000000000000000010100010119 +:10D210000001000100010000010000000100010008 +:10D2200000000000000100000000000000000100FC +:10D2300000000000000000000000000000010100EC +:10D2400000000000000000000000000000000100DD +:10D2500001000000000000000000000000010100CB +:10D2600000000000000000000000000000010100BC +:10D2700000000000000000000000000000000100AD +:10D280000100010100000000000000000000010199 +:10D29000010100000000000000000000000100018A +:10D2A0000100010001000000010000000101010176 +:10D2B0000101000100010100010000000101010164 +:10D2C0000100000001010001000001010100010056 +:10D2D0000100010101010101000000010001010044 +:10D2E0000000010001010001000000010101010036 +:10D2F000000000000001000001000000000001012A +:10D300000100000000010000000000010100010117 +:10D310000001000100010000010000000100010007 +:10D3200000000000000100000000000000000100FB +:10D3300000000000000000000000000000010100EB +:10D3400000000000000000000000000000000100DC +:10D3500001000000000000000000000000010100CA +:10D3600000000000000000000000000000010100BB +:10D3700000000000000000000000000000000100AC +:10D380000100010100000000000000000000010198 +:10D390000101000000000000000000000001000189 +:10D3A0000100010001000000010000000101010175 +:10D3B0000201000100010100010000000101010162 +:10D3C0000100000001010001000001010101010054 +:10D3D0000100010101010101000000010001010043 +:10D3E0000000010001010001000000010101010035 +:10D3F0000000000000010000010000000000010129 +:10D400000100000000010000000000010101010115 +:10D410000001000100010100010000000100010005 +:10D4200000000000000100000000000000000100FA +:10D4300000000000000000000000000000010100EA +:10D4400000000000000000000000000000000100DB +:10D4500001000000000000000000000000010100C9 +:10D4600000000000000000000000000001010100B9 +:10D4700000000000000000000000000000000100AB +:10D480000100010100000000000000000000010197 +:10D490000202000000000000000000000001000186 +:10D4A0000100010001000000010000000101010174 +:10D4B0000201010100010100010000000101010160 +:10D4C0000201000001010001000001010101010051 +:10D4D0000100010101010101000000010001010042 +:10D4E0000000010001010001000000010101010034 +:10D4F0000000000000010100010000000000010127 +:10D500000100000000010000000000010101010114 +:10D510000001000100010100010000000100010004 +:10D5200000000000000100000000000000010100F8 +:10D5300000000000000000000000000000010100E9 +:10D5400000000000000000000000000000000100DA +:10D5500001000000000000000000000000010100C8 +:10D5600000000000000000000000000001010100B8 +:10D5700000000000000000000000000000000100AA +:10D580000100010100000000000000000000010196 +:10D590000202000000000000000000000001000185 +:10D5A0000100010001000000010000000101010173 +:10D5B000020101010001010001000000010101015F +:10D5C000020101000101000100000101010101004F +:10D5D0000100010101010101000000010001010140 +:10D5E0000100010101010001000100010101010030 +:10D5F0000100000000010100010100000000010124 +:10D600000100000000010000000000010101010113 +:10D610000001000100010100010000000100010003 +:10D6200000000000000100000000000000010100F7 +:10D6300000000000000000000000000000010100E8 +:10D6400000000000000000000000000000000100D9 +:10D6500001000000000000000000000001010100C6 +:10D6600000000000000000000000000001010100B7 +:10D6700000000000000000000000000000000100A9 +:10D680000100010100000000000000000000010294 +:10D690000202010000000000000000000001000183 +:10D6A0000200010001000000010000000101010270 +:10D6B000020101010001020001000000010101015D +:10D6C000020101000101000100000101010101004E +:10D6D000020001010101010100000001010101013D +:10D6E000010001010101000100010001010101002F +:10D6F0000100000000010100010100000000010123 +:10D700000100000000010000000000010101010112 +:10D710000001000100010100010000000100010002 +:10D7200000000000000100000000000000010100F6 +:10D7300000000000000000000000000000010100E7 +:10D7400000000000000000000000000000000100D8 +:10D7500001000000000000000000000001010100C5 +:10D7600000000000000000000000000001010100B6 +:10D7700000000000000000000000000000000100A8 +:10D780000100010100000000000000000000010293 +:10D790000202010000000000000100000001000280 +:10D7A000020001000100000001000000010101026F +:10D7B000020101010001020001000000010101015C +:10D7C000020101000101010100000101010101014B +:10D7D000020101010101010100000001010101013B +:10D7E000010001010101000100010001010101002E +:10D7F0000100000000010100010100000000010122 +:10D800000100000000010000000000010101010111 +:10D8100000010001000101000100000001010101FF +:10D8200000000000000100000000000000010101F4 +:10D8300001000000000000000000000000010100E5 +:10D8400000000000000000000000000000010100D6 +:10D8500001000000000000000000000001010100C4 +:10D8600000000000000000000000000001010100B5 +:10D8700000000000000000000000000000010100A6 +:10D880000100010100000000000000000000010292 +:10D89000020201000000000000010000000100027F +:10D8A000020001000100000001000000010101026E +:10D8B0000201010100020200010000000101010259 +:10D8C000020101000101010100000101010101014A +:10D8D0000201020101010101000000010101010139 +:10D8E000010001010101000100010001010101002D +:10D8F000010001000001010101010000010001011E +:10D90000010100000001000000000001010101010F +:10D9100000010001000101000100000101010101FD +:10D9200000000000000100010000000000010101F2 +:10D9300001000000000000000000000001010100E3 +:10D9400000000000000000000000000000010100D5 +:10D9500001000000000000000001000001010100C2 +:10D9600000000000000000000001000001010100B3 +:10D9700000000000000000000000000000010100A5 +:10D980000100010100000000000000000000010291 +:10D99000020201010000000000010000000100027D +:10D9A000020002000100000001000000010101026C +:10D9B0000202010100020200010000000101010257 +:10D9C0000201010001010101000001010101010149 +:10D9D0000201020101010101000000010101010138 +:10D9E000010101010101000100010001010101012A +:10D9F000010001000101010101010000010001011C +:10DA0000010101000001000000000001010101010D +:10DA100000010001000101000100000101010101FC +:10DA200000000000000100010000000000010101F1 +:10DA300001000000010000000001000001010100E0 +:10DA400000000000000000000000000000010100D4 +:10DA500001000000000000000001000001010100C1 +:10DA600000000000000000000001010001010100B1 +:10DA700000000000000000000000000001010100A3 +:10DA80000100010100000000000000000000010290 +:10DA9000020201010000000000010000000100027C +:10DAA0000201020002000000020000000101010268 +:10DAB0000202010100020200010000000101010256 +:10DAC0000201010001010101000001010101010148 +:10DAD0000201020101010101000000010101010137 +:10DAE0000101020101010001000100010101010128 +:10DAF000010001000101010101010000010101011A +:10DB0000010101010001000000000001010101010B +:10DB100000020001000101000100000101010101FA +:10DB200000000000000100010000000000010101F0 +:10DB300001000000010000000001000001010101DE +:10DB400000000000000000000000000000010100D3 +:10DB500001000000000000000001000101010100BF +:10DB600000000000000000000101010101010101AD +:10DB700000000000000000000000000001010100A2 +:10DB8000010001010000000000000000000001028F +:10DB9000020201010000000000010000000100027B +:10DBA0000201020002000000020000000101010267 +:10DBB0000202010100020200010000000101010255 +:10DBC0000201010001010101000001010101010147 +:10DBD0000201020101010201000000010101010135 +:10DBE0000101020101010001000100010101010127 +:10DBF0000100010001010101010100010101010118 +:10DC00000101010100010000000001010101010208 +:10DC100000020001000101000100000101010101F9 +:10DC200000010000000100010000000000010101EE +:10DC300001010000010000000001000001010101DC +:10DC400000000000000000000000000000010100D2 +:10DC500001000000000000000001010101010100BD +:10DC600000000000000000000101010101010101AC +:10DC700000000000000000000000000001010100A1 +:10DC8000010001010000000000000000000001028E +:10DC90000202020100000000000100000001000279 +:10DCA0000201020102000000020000000101010265 +:10DCB0000202010100020200010000000101010254 +:10DCC0000201010101010102000001010101010144 +:10DCD0000201020201010201000000010101010133 +:10DCE0000101020102010001000100010101010125 +:10DCF0000100010001010101010101010101010116 +:10DD00000101010100010000000101010101010206 +:10DD100001020001000101000100000101010101F7 +:10DD200000010000000100010000000000010101ED +:10DD300001010000010000000001000001010101DB +:10DD400000000000000000000000000000010100D1 +:10DD500001000000000000000001010101010100BC +:10DD600000000000000000000101010101010101AB +:10DD7000000000000000000000010000010101009F +:10DD8000010001010000000000000000010101028B +:10DD90000202020100000000000100000001000278 +:10DDA0000201020102000000020000000101010264 +:10DDB0000202020200020200020000000101010250 +:10DDC0000201010101010102000001010101010143 +:10DDD0000201020201010201000000010101010132 +:10DDE0000101020102010001010100010101010123 +:10DDF0000100010101010101010101010101010114 +:10DE00000101010100010001000101010101010204 +:10DE100001020001000101010100000101010101F5 +:10DE200000010000000100010000000000010101EC +:10DE300001010000010000000001000001010101DA +:10DE400000000000000000000000000000010100D0 +:10DE500001000000000000010001010101010100BA +:10DE600000000000000000010101010101010101A9 +:10DE7000000000000000000000010100010101009D +:10DE80000100010100000000000100000101010289 +:10DE90000202020100000000000100000001000277 +:10DEA0000201020102000000020000000101010263 +:10DEB000020202020002020002000000010101024F +:10DEC0000202010101020102000001010101010140 +:10DED0000201020201020201000000010101010130 +:10DEE0000201020102010001010101010101010120 +:10DEF0000100010101010101010101010101010212 +:10DF00000201010101010001000101010101010201 +:10DF100001020001000101010100000101010101F4 +:10DF200000010100000100010000000001010101E9 +:10DF300001010100010000010001000001010101D7 +:10DF400000000000000000000000000000010100CF +:10DF500001000000000000010101010101010101B7 +:10DF600000000000000000010101010101010101A8 +:10DF7000000000000000000001010101010101009A +:10DF80000100010100000000000101000101010287 +:10DF90000202020101000000000100000001000275 +:10DFA0000202020102000000020000000101010261 +:10DFB000020202020102020002000000010101024D +:10DFC000020202010202010200000102010101023B +:10DFD000020102020202020101000001010101022C +:10DFE000020102010201000101010101010101011F +:10DFF000020001010102010101010101010101020F +:10E000000201010101010001000101010101010200 +:10E0100001020002000101010100010101010101F1 +:10E0200000010100000100010000000101010101E7 +:10E0300001010100010000010101000001010101D5 +:10E0400000000000000000000000000001010100CD +:10E0500001000000000000010101010101010101B6 +:10E0600000000000000000010101010101010101A7 +:10E070000000000000000001010101010101010098 +:10E080000100010100000000010101000101010285 +:10E090000202020201000000000100000001000273 +:10E0A0000202020102000000020000000101010260 +:10E0B000020202020102020002000000010101024C +:10E0C0000202020102020102000002020101010239 +:10E0D0000202020202020202010000010101010229 +:10E0E000020102010201000101010101010101011E +:10E0F000020001010102010101010101010101020E +:10E1000002010101010100010001010101010102FF +:10E1100001020002000101010100010101010101F0 +:10E1200000010100000100010000000101010101E6 +:10E1300001010100010000010101010001010101D3 +:10E1400001000000000000000000000001010100CB +:10E1500002000000000000010101010101010101B4 +:10E1600000000000000000010101010101010101A6 +:10E170000000000000000001010101010101010097 +:10E180000200010100000000010101000101010283 +:10E190000202020201010000000100000001000271 +:10E1A000020202010200000002000000010101025F +:10E1B000020202020102020002000000010101024B +:10E1C0000202020102020102000002020101010238 +:10E1D0000202020202020202010000020101010227 +:10E1E000020102010201000101010101010101011D +:10E1F000020001010102010101010101010101020D +:10E2000002010101010100010001010101010102FE +:10E2100001020002000101010100010101010101EF +:10E2200001010100000100010000000101010101E4 +:10E2300001010100010000010101010001010101D2 +:10E2400001000000000000000000010001010100C9 +:10E2500002000000000000010101010101010101B3 +:10E2600000000000000000010101010101010101A5 +:10E270000000000000000001010101010101010096 +:10E280000201010100000000010101010101010280 +:10E29000020202020101010000010000000200026E +:10E2A000020202010200000002000000010101025E +:10E2B000020202020102020002000000010101024A +:10E2C0000202020102020102000002020101010237 +:10E2D0000202020202020202010000020101010226 +:10E2E000020102010201000101010102010101021A +:10E2F000020001010102010101010101010101020C +:10E3000002010101010100010101010101010102FC +:10E3100001020002000101010101010101010101ED +:10E3200001010100000100010000000101010101E3 +:10E3300001010100010000010101010001010101D1 +:10E3400001000000000000000101010101010100C5 +:10E3500002000000000000010101010101010101B2 +:10E3600000000000010000010101010101010101A3 +:10E370000000000000010001010101010101010094 +:10E38000020101010000000101010101010101027E +:10E39000020202020101010000010000000200026D +:10E3A000020202010200000002000000010101025D +:10E3B0000202020201020200020000000101010249 +:10E3C0000202020102020102000002020101010236 +:10E3D0000202020202020202010000020101010225 +:10E3E0000202020102020001010101020101010217 +:10E3F0000201010101020101020101010101010209 +:10E4000002010101010101010101010101010102FA +:10E4100001020102000101010101010101010102EA +:10E4200001010100000100010000000101010102E1 +:10E4300002010100010000010101010101010101CE +:10E4400001000100000000000101010101010100C3 +:10E4500002000000000000010101010101010101B1 +:10E4600000000000010001010101010101010101A1 +:10E470000000000000010001010101010101010093 +:10E48000020101010101000101010101010101027B +:10E49000020202020101010000010000000200026C +:10E4A000020202020200000002000000020101025A +:10E4B0000202020201020200020000000201010247 +:10E4C0000202020102020102000002020101010235 +:10E4D0000202020202020202010000020101010224 +:10E4E0000202020202020001010101020101010215 +:10E4F0000201020101020101020101010101010207 +:10E5000002010101010101010101010101010102F9 +:10E5100002020102010101010101010101010102E7 +:10E5200001010100000100010000000101010102E0 +:10E5300002010100010000010101010101010101CD +:10E5400001000100000000000101010101010100C2 +:10E5500002000000010100010101010101010101AE +:10E56000000000000101010101010101010101019F +:10E570000000000101010001010101010101010090 +:10E580000201010101010101010101010101010279 +:10E59000020202020201010000010000000200026A +:10E5A0000202020202000000020000000202010258 +:10E5B0000202020201020200020000000201020245 +:10E5C0000202020102020202000002020101010233 +:10E5D0000202020202020202010000020101010223 +:10E5E0000202020202020001010101020101010214 +:10E5F0000201020101020101020101010101010206 +:10E6000002020101010101010101010101010102F7 +:10E6100002020102010201010101010101010102E5 +:10E6200001010101010100010001000101010102DC +:10E6300002010101010000010101010101010101CB +:10E6400001000100000000010101010101010100C0 +:10E6500002000000010101010101010101010101AC +:10E66000000000000101010101010101010101019E +:10E67000000000010101010101010101010101008E +:10E680000201010101010101010101010101010278 +:10E690000202020202010101000200000002000267 +:10E6A0000202020202000000020000000202020256 +:10E6B0000202020201020200020000000201020244 +:10E6C0000202020202020202000002020101010231 +:10E6D0000202020202020202010001020101010221 +:10E6E0000202020202020001010101020201010212 +:10E6F0000201020101020101020101010101010205 +:10E7000002020101010101010101010101010102F6 +:10E7100002020102010201010101010101010102E4 +:10E7200001010101010100010001010101010102DA +:10E7300002010101010000010101010101010102C9 +:10E7400001000100000000010101010101010100BF +:10E7500002000001010101010101010101010101AA +:10E76000000000010101010101010101010101019C +:10E77000010100010101010101010101010101008B +:10E780000201020101010101010101010101010276 +:10E790000202020202020101000200000002000265 +:10E7A0000202020202000000020000000202020255 +:10E7B0000202020202020200020000000202020241 +:10E7C000020202020202020200000202020101022F +:10E7D0000202020202020202010001020101010220 +:10E7E0000202020202020002010101020201010210 +:10E7F0000201020101020201020101010101010203 +:10E8000002020201010101010101010201010102F3 +:10E8100002020102010201010101010101010102E3 +:10E8200001010101010100010001010101010102D9 +:10E8300002010101010100010101010101010102C7 +:10E8400001000100000000010101010101010100BE +:10E8500002000001010101010101010101010101A9 +:10E86000000001010101010101010101010101019A +:10E870000101010101010101010101010101010089 +:10E880000201020201010101010101010101010274 +:10E890000202020202020201000200000002000263 +:10E8A0000202020202010000020000000202020253 +:10E8B0000202020202020200020000000202020240 +:10E8C000020202020202020200000202020102022D +:10E8D000020202020202020201000102010102021E +:10E8E000020202020202000201010102020101020F +:10E8F0000201020101020201020101010101010202 +:10E9000002020201010201010101010201010102F1 +:10E9100002020102010202010101010101010102E1 +:10E9200001020101010100010001010101010102D7 +:10E9300002020101010100010101010101010102C5 +:10E9400001000100000000010101010101010100BD +:10E9500002000001010101010101010101010101A8 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010088 +:10E980000201020201010101010101010101010273 +:10E990000202020202020201010200000002000261 +:10E9A0000202020202010000020000000202020252 +:10E9B000020202020202020002000000020202023F +:10E9C000020202020202020200000202020102022C +:10E9D000020202020202020201010102010102021C +:10E9E000020202020202000201010102020101020E +:10E9F0000201020102020201020101010101010200 +:10EA000002020201010201010101010201010102F0 +:10EA100002020102010202010101010101010102E0 +:10EA200002020101010200010001010101010102D4 +:10EA300002020101010100010101010101010102C4 +:10EA400001000100000000010101010101010100BC +:10EA500002000101010101010101010101010101A6 +:10EA60000101010101010101010101010101010295 +:10EA70000101010101010101010101010101010087 +:10EA80000201020201010101010101010101010272 +:10EA90000202020202020201010200000002000260 +:10EAA0000202020202010000020000000202020251 +:10EAB000020202020202020002000000020202023E +:10EAC000020202020202020200000202020202022A +:10EAD000020202020202020201010102010202021A +:10EAE000020202020202000201020102020201020B +:10EAF00002020202020202010201010101010102FD +:10EB000002020202010201010101010201010102EE +:10EB100002020102010202010201010101010102DE +:10EB200002020101010200010001010101010102D3 +:10EB300002020101010101010101010101010102C2 +:10EB400002000100000100010101010101010101B8 +:10EB500002010101010101010101010101010102A3 +:10EB60000101010101010101010101010101010294 +:10EB70000101010101010101010101010101010086 +:10EB80000201020201010101010101010101010271 +:10EB9000020202020202020101020000000200025F +:10EBA0000202020202010000020000000202020250 +:10EBB000020202020202020002000000020202023D +:10EBC0000202020202020202000002020202020229 +:10EBD0000202020202020202010101020202020218 +:10EBE0000202020202020002010201020202020209 +:10EBF00002020202020202010201010101010102FC +:10EC000002020202010201010101010201010102ED +:10EC100002020102010202010201010101010102DD +:10EC200002020201010200010101010101010102D0 +:10EC300002020201010101010101010101010102C0 +:10EC400002000100000100010101010101010101B7 +:10EC500002010101010101010101010101010102A2 +:10EC60000101010101010101010101010101010293 +:10EC70000101010101010101010101010101010085 +:10EC80000201020201010101010101010101010270 +:10EC9000020202020202020201020000010200025C +:10ECA000020202020201000002000000020202024F +:10ECB000020202020202020002000000020202023C +:10ECC0000202020202020202010002020202020227 +:10ECD0000202020202020202020101020202020216 +:10ECE0000202020202020002010201020202020208 +:10ECF00002020202020202020202010101010102F9 +:10ED000002020202010201010101010201010102EC +:10ED100002020202010202010201010101010102DB +:10ED200002020201010201010101010101010102CE +:10ED300002020201010101010101010101010102BF +:10ED400002000101010100010101010101010101B4 +:10ED500002010101010101010101010101010102A1 +:10ED60000101010101010101010101010101010292 +:10ED70000101010101010101010101010101010084 +:10ED8000020102020101010101010101010101026F +:10ED9000020202020202020201020000010200025B +:10EDA000020202020202000002000000020202024D +:10EDB000020202020202020002000000020202023B +:10EDC0000202020202020202010002020202020226 +:10EDD0000202020202020202020101020202020215 +:10EDE0000202020202020002020201020202020206 +:10EDF00002020202020202020202010101010102F8 +:10EE000002020202010201010101010202010202E9 +:10EE100002020202010202010201010102010202D8 +:10EE200002020201010201010101010101010102CD +:10EE300002020201020101010101010101010102BD +:10EE400002000101010101010101010101010101B2 +:10EE500002010101010101010101010101010102A0 +:10EE60000101010101010101010101010101010291 +:10EE70000101010101010101010101010101010083 +:10EE8000020102020101010101010101010101026E +:10EE90000202020202020202020200000102000259 +:10EEA000020202020202000002000000020202024C +:10EEB000020202020202020002000000020202023A +:10EEC0000202020202020202010102020202020224 +:10EED0000202020202020202020101020202020214 +:10EEE0000202020202020002020201020202020205 +:10EEF00002020202020202020202010101010102F7 +:10EF000002020202020201010101010202010202E7 +:10EF100002020202010202010201010102010202D7 +:10EF200002020201010201010101010101010102CC +:10EF300002020201020101010101010101010102BC +:10EF400002010101010101010101010101010101B0 +:10EF5000020101010101010101010101010101029F +:10EF60000101010101010101010101010101010290 +:10EF70000101010101010101010101010101010082 +:10EF8000020102020101010101010101010101026D +:10EF90000202020202020202020200010102000257 +:10EFA000020202020202000102000000020202024A +:10EFB0000202020202020200020000000202020239 +:10EFC0000202020202020202010102020202020223 +:10EFD0000202020202020202020101020202020213 +:10EFE0000202020202020002020202020202020203 +:10EFF00002020202020202020202020201010202F3 +:10F0000002020202020201010101010202010202E6 +:10F0100002020202010202010201010102010202D6 +:10F0200002020201010201010101010101010102CB +:10F0300002020201020101010101010101010202BA +:10F0400002010101010101010101010101010101AF +:10F05000020101010101010101010101010101029E +:10F06000010101010101010101010101010101028F +:10F070000101010101010101010101010101010081 +:10F08000020102020101010101010101010101026C +:10F090000202020202020202020200010102000256 +:10F0A0000202020202020001020000000202020249 +:10F0B0000202020202020200020000000202020238 +:10F0C0000202020202020202010102020202020222 +:10F0D0000202020202020202020102020202020211 +:10F0E0000202020202020002020202020202020202 +:10F0F00002020202020202020202020202010202F1 +:10F1000002020202020201010101010202010202E5 +:10F1100002020202010202020201010202010202D3 +:10F1200002020201010201020101010101010202C8 +:10F1300002020201020101010101010101010202B9 +:10F1400002010201010101010101010101010101AD +:10F15000020101010101010101010101010101029D +:10F16000020101010101010101010101010101028D +:10F17000020101010101010101010101010101007F +:10F18000020102020101010101010101010101026B +:10F190000202020202020202020200020202000253 +:10F1A0000202020202020002020000000202020247 +:10F1B0000202020202020200020000010202020236 +:10F1C0000202020202020202010102020202020221 +:10F1D0000202020202020202020102020202020210 +:10F1E0000202020202020002020202020202020201 +:10F1F00002020202020202020202020202010202F0 +:10F2000002020202020201020101010202010202E3 +:10F2100002020202020202020201010202010202D1 +:10F2200002020201010201020101010101010202C7 +:10F2300002020201020101010101010101020202B7 +:10F2400002010201010101010101010101010102AB +:10F25000020101010101010101010101010101029C +:10F26000020101010101010101010101010101028C +:10F27000020101010101010101010101010101007E +:10F280000202020201010101010101010101010269 +:10F290000202020202020202020200020202000252 +:10F2A0000202020202020002020000000202020246 +:10F2B0000202020202020201020000010202020234 +:10F2C0000202020202020202010102020202020220 +:10F2D000020202020202020202020202020202020E +:10F2E0000202020202020002020202020202020200 +:10F2F00002020202020202020202020202020202EE +:10F3000002020202020202020102020202020202DE +:10F3100002020202020202020201020202010202CF +:10F3200002020202010201020101010101010202C5 +:10F3300002020202020101010101010101020202B5 +:10F3400002010201010101010101010101010102AA +:10F35000020101010101010101010101010101029B +:10F36000020101010101010101010101010101028B +:10F37000020101010101010101010101010101007D +:10F380000202020201010101010101010101010268 +:10F390000202020202020202020200020202000251 +:10F3A0000202020202020202020000000202020243 +:10F3B0000202020202020201020100020202020231 +:10F3C000020202020202020202010202020202021E +:10F3D000020202020202020202020202020202020D +:10F3E00002020202020200020202020202020202FF +:10F3F00002020202020202020202020202020202ED +:10F4000002020202020202020102020202020202DD +:10F4100002020202020202020201020202020202CD +:10F4200002020202010201020101010101010202C4 +:10F4300002020202020101010102010101020202B3 +:10F4400002010201010101010101010101010102A9 +:10F45000020101010101010101010101010101029A +:10F460000202010101010101010101010101010289 +:10F47000020201010101010101010101010101007B +:10F480000202020201010101010101010101020266 +:10F490000202020202020202020200020202000250 +:10F4A0000202020202020202020000000202020242 +:10F4B000020202020202020202020002020202022E +:10F4C000020202020202020202020202020202021C +:10F4D000020202020202020202020202020202020C +:10F4E00002020202020200020202020202020202FE +:10F4F00002020202020202020202020202020202EC +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020202020202020202CB +:10F5200002020202020201020101010101020202C1 +:10F5300002020202020101020102010101020202B1 +:10F5400002010201010101010101010101010102A8 +:10F550000202010101010101010101010101020297 +:10F560000202020101010101010101010101010287 +:10F57000020201010101010101010101010101007A +:10F580000202020201010101010101010101020265 +:10F59000020202020202020202020002020200024F +:10F5A0000202020202020202020000000202020241 +:10F5B000020202020202020202020002020202022D +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020202020202020202020B +:10F5E00002020202020200020202020202020202FD +:10F5F00002020202020202020202020202020202EB +:10F6000002020202020202020202020202020202DA +:10F6100002020202020202020202020202020202CA +:10F6200002020202020201020101010101020202C0 +:10F6300002020202020101020202010102020202AE +:10F6400002020201010101010101010101010102A6 +:10F650000202020101010101010101010101020295 +:10F660000202020101010101010101010101020285 +:10F670000202020101010101010101010101010078 +:10F680000202020201010101010101010101020264 +:10F69000020202020202020202020202020200024C +:10F6A000020202020202020202000002020202023E +:10F6B000020202020202020202020102020202022B +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020202020202020202020A +:10F6E00002020202020200020202020202020202FC +:10F6F00002020202020202020202020202020202EA +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020202020202020202020202C9 +:10F7200002020202020201020101010201020202BE +:10F7300002020202020201020202010102020202AC +:10F7400002020201010101010101010101010202A4 +:10F750000202020201010101010201010102020291 +:10F76000020202020201010102020101020202027E +:10F770000202020201010101010101010101010076 +:10F780000202020201010101010101010101020263 +:10F79000020202020202020202020202020200024B +:10F7A000020202020202020202000002020202023D +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020200020202020202020202FB +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020201020101010201020202BD +:10F8300002020202020201020202020102020202AA +:10F8400002020201010101010101010101010202A3 +:10F85000020202020201010201020101020202028D +:10F86000020202020201010202020201020202027B +:10F870000202020201010101010101010101010075 +:10F880000202020201010101010101010101020262 +:10F89000020202020202020202020202020200024A +:10F8A000020202020202020202020002020202023A +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020200020202020202020202FA +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020201020101010202020202BB +:10F9300002020202020202020202020102020202A8 +:10F9400002020202010101010101010101020202A0 +:10F950000202020202020102020202020202020288 +:10F960000202020202020202020202020202020277 +:10F970000202020202020101010101010101010072 +:10F980000202020202010101010101010101020260 +:10F990000202020202020202020202020202000249 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020200020202020202020202F9 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020102010202020202B8 +:10FA300002020202020202020202020202020202A6 +:10FA4000020202020101010102010101010202029E +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA7000020202020202010202020101010102006D +:10FA8000020202020202010101010101010102025E +:10FA90000202020202020202020202020202000248 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020201020202020202020202F7 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020102020202020202B6 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020102020202010102020298 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202010202020068 +:10FB8000020202020202020102020101010102025A +:10FB90000202020202020202020202020202000247 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020102020202020202020295 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020066 +:10FC80000202020202020202020202010101020257 +:10FC90000202020202020202020202020202000246 +:10FCA0000202020202020202010202020202020235 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020065 +:10FD80000202020202020202020202010201020255 +:10FD90000202020202020202020202020202000245 +:10FDA0000202020201020202010202020202020235 +:10FDB0000202020202020102020202020202020224 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202010102000246 +:10FEA0000202020201020202010202010202020235 +:10FEB0000202020202010202020202020202020223 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202010102000245 +:10FFA0000202010201020201010202010202020236 +:10FFB0000202020202020102010202010202020224 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:02000002F0000C +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:10009000020101010101010101010101010101024E +:1000A0000202010201020201010101010101020239 +:1000B0000202020202010102020102020101020225 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020101010101010101010101010101024D +:1001A000010101010101010101010101010101023E +:1001B0000202020102010102010201010202020225 +:1001C0000202020202020201020202020202020210 +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000010101010101010101010101010101024D +:1002A000010101010101010101010101010101023D +:1002B000020101020101010101010201010101022A +:1002C000020202020202020202020201020202020F +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000010101010101010101010101010101024C +:1003A000010101010101010101010101010101023C +:1003B0000102020102010102010101010101020227 +:1003C0000202020201010201020201020202020211 +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202014D +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101023B +:1004B000020101010101010101010101010101022A +:1004C0000202020202020101020102010101020212 +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202014C +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101022A +:1005C0000202010201010201010201010202020212 +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202014B +:10069000010101010101010101010101010101014A +:1006A0000101010101010101010101010101010239 +:1006B0000101010101010101010101010101010229 +:1006C0000101020101010101020101010101010217 +:1006D00002020202020201020202020202020202FB +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:100770000202020202020202020202020202020259 +:10078000020202020202020202020202020202014A +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010228 +:1007C0000202010201010101010101010101020214 +:1007D00002020202020101010202010102020202FE +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020149 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010217 +:1008D0000202010101010101010101010102020203 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020148 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010226 +:1009C0000101010101010101010101010101010216 +:1009D0000202010101010101010101010101020203 +:1009E00002020202020202020202020202020202E7 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020147 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010215 +:100AD0000101010101010101010101010101010205 +:100AE00002020202020202020202020202020202E6 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020146 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010214 +:100BD0000101010101010101010101010101010204 +:100BE00002020202010102020202020102020202E8 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020145 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010213 +:100CD0000101010101010101010101010101010203 +:100CE00002020102010102010101010101020202ED +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020144 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010202 +:100DE00002020101010102010101010101010202EE +:100DF00002020202020102020202020202020202D4 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020143 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010201 +:100EE00001010101010101010101010101010102F1 +:100EF00002020202020101020102010102020202D7 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020142 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010200 +:100FE00001010101010101010101010101010102F0 +:100FF00002020102010101010101010101010202DC +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020141 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010102EF +:1010F00001020101010101010101010101010202DD +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:101180000202020202020202020202020202020140 +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010102EE +:1011F00001010101010101010101010101010102DE +:1012000002020202020102020202020102020202C0 +:1012100002010201020101020202010202020202B3 +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202013F +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010102DD +:1013000001010101010101010101010101020202CA +:1013100002020202020202010101020101020202B2 +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202013E +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101020202010202010102B6 +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202013D +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010102CA +:1015100002010201020101010101010101020202B5 +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202013C +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010102B9 +:10162000020202020201020202020202020202029B +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202013B +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010102B8 +:10172000020101020201020102020201020202029E +:10173000010101020102020202020202020202028D +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:10178000020202020202020202020202020202013A +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000202020102010101010101010101010293 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020139 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010102A6 +:10193000010101020102020202020202020202028B +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020138 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010295 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020137 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000102010202020202020202020202020277 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020136 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010283 +:101C50000102020202020202020202020202020265 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020135 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010282 +:101D50000102020202020202020202020202020264 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020134 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010281 +:101E50000101010101010101010101010101010271 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020133 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010260 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020132 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:10206000010101010101010101010101010101025F +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020131 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101024E +:102180000202020202020202020202020202020130 +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101024D +:10228000020202020202020202020202020202012F +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101024C +:10238000020202020202020202020202020202012E +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101024B +:102480000102010102020202020202020202010131 +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101011C +:1024B000010101010101010101010101010101010C +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101024A +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101011B +:1025B000010101010101010101010101010101010B +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:102670000101010101010101010101010101010249 +:10268000010101010101010101010101010101013A +:102690000101010101010101010101010101010229 +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202020202020202020202DA +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:10277000020202020202020202020202020202003B +:102780000000000000000000000000000000000148 +:102790000101010101010101010101010101010228 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:10287000020202020202020202020202020202003A +:102880000000000000000000000000000000000147 +:102890000101010101010101010101010101010029 +:1028A0000000000000000000000000000000000226 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020069 +:102950000000000000000000000000000000000275 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020039 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A800000000000000000000000000000000065E1 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000001000000E5 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000100000100000000000013 +:102BC0000000000000000100000000000000000004 +:102BD00000000000000000000000010000000000F4 +:102BE00000000000000000000000000001000000E4 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000100000100000000000012 +:102CC0000000000000000100000000000000000003 +:102CD00000000000000001000000010001000000F1 +:102CE00000000000000000000000000001000000E3 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB000000000000000010000010000000101000F +:102DC0000000000000000100000000000000000101 +:102DD00000000000000001000000010001000000F0 +:102DE00000000000000000000000000001000000E2 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000001000000000000000000A1 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000001000000000000000031 +:102EA0000000000000000000000000000000000022 +:102EB000000000000000010000010000000101000E +:102EC00000000000000001000000000000010001FF +:102ED00000000000000001000000010101000000EE +:102EE00000000000000000000000000001000000E1 +:102EF00000000000000000000000000000010100D0 +:102F000000000000000001000000000000000000C0 +:102F100000000000000001000000000000000000B0 +:102F200000000000000001000000000000000000A0 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000001000000000000000030 +:102FA0000000000000000000000001000000000020 +:102FB000000000000000010000010000000101000D +:102FC00000000000000001010000000000010001FD +:102FD00000000000000001000000010101000000ED +:102FE00000000000000001000000000001000000DF +:102FF00000000000000001000000000000010100CE +:1030000000000000000001000000000000000000BF +:1030100000000000000001000000000000010000AE +:10302000000000000000010000000000000000009F +:10303000000000000000010000000000000000008F +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:10309000000000000000000100000000000000002F +:1030A000000000000000000000000100000000001F +:1030B000000000000000010000010000000101000C +:1030C00000000000000001010001010000010001FA +:1030D00000000000000001000000010101000000EC +:1030E00000000000000001000000000001000000DE +:1030F00000000000000001000000000000010100CD +:1031000000000000000001000000000000000000BE +:1031100000000000000001000000000000010000AD +:10312000010000000000010000000000000000009D +:10313000000000000000010000000000000000008E +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000100000000000000002E +:1031A000000000000000000000000100000000001E +:1031B000000000000000010000010000000101000B +:1031C00000000000000001010001010001010001F8 +:1031D00000000000000001000001010101010000E9 +:1031E00000000000000001000000000001000000DD +:1031F00000000000000001000000000000010100CC +:1032000001000000000001000000000100000000BB +:1032100000000000000001000000000000010000AC +:10322000010000000000010000000000000000009C +:10323000000000000000010000000000000000008D +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000101000000000000002C +:1032A000000000000000000000000100000000001D +:1032B0000000000000000101000100000001010009 +:1032C00000000000000001010001010001010001F7 +:1032D00000000000000001000001010101010000E8 +:1032E00000000000000001000000000101000000DB +:1032F00000000000000001000000000000010100CB +:1033000001000000000001000000000100000000BA +:1033100000000000000001000000000000010000AB +:10332000010000000000010000000000000000009B +:10333000000000000000010000000000000000008C +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000101000000000000002B +:1033A000000000000000000000000100000000001C +:1033B0000000000000000101000101000001010007 +:1033C00000000000000001010001010001010001F6 +:1033D00000000000000001000001010101010100E6 +:1033E00000000000000001000000000101000000DA +:1033F00000000000000001000000000000010100CA +:1034000001000000000001000000000100000000B9 +:1034100000000000000001000000000000010000AA +:10342000010000000000010000000000000000009A +:10343000000000000000010000000000000000008B +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000010000000000000000004B +:10348000000000000000000000000000000000003C +:10349000000000000000000101000000000000002A +:1034A000000000000000000100000100000000001A +:1034B0000000000000000101000101010001010005 +:1034C00001000000000001010001010001010101F3 +:1034D00000000000000001000001010101010100E5 +:1034E00000000000000001010000000101000000D8 +:1034F00000000000000001000000000000010100C9 +:1035000001000000000001000000000100010000B7 +:1035100000000000000001000000000000010000A9 +:103520000100000000000100000000000000000099 +:103530000000000000000100000000000001000089 +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000010000000000000000005A +:10357000000000000000010000000000000000004A +:10358000000000000000000000000000000000003B +:103590000000000000000001010000000000000029 +:1035A0000000000000000001000101000000000018 +:1035B0000000000000000101000101010001010004 +:1035C00001000000000001010001010101010101F1 +:1035D00000000000000001000001010101010100E4 +:1035E00000000000000001010000010101000000D6 +:1035F00000000000000001000100000100010100C6 +:1036000001000000000001010000000100010000B5 +:1036100000000000000001000000000000010100A7 +:103620000100000000000100000000000000000098 +:103630000000000000000100000000000001000088 +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:103660000000000000000100000000000000000059 +:103670000000000000000100000000000000000049 +:103680000000000000000000010000000000000039 +:103690000000000000000001010000000000000028 +:1036A0000000000000000001000101000000000017 +:1036B0000000000000000101000101010001010003 +:1036C00001000000000001010001010101010101F0 +:1036D00000000000000001000001010101010100E3 +:1036E00000000000000001010000010101000000D5 +:1036F00000000000010001000100000100010100C4 +:1037000001000000000001010000010100010000B3 +:1037100000000000000001000000000000010100A6 +:103720000100000000000100000000000000000097 +:103730000000000000000100000000000001000087 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000100000000000000000058 +:103770000000000000000100000000000000000048 +:103780000000000000000000010000000000000038 +:103790000000000000000001010000000000000027 +:1037A0000000000000000001000101000000000016 +:1037B0000000000000010101000101010001010001 +:1037C00001000000000001010101010101010101EE +:1037D00000000000000001000001010101010100E2 +:1037E00000000000000001010000010101000000D4 +:1037F00000000000010001000100000101010101C1 +:1038000001000000000001010000010100010000B2 +:1038100000000000000001000000000000010100A5 +:103820000100000000000100000000000000000096 +:103830000000000000000100000000000001000086 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000100000000000000000057 +:103870000000000000000100000000000000000047 +:103880000000000000000000010000000000000037 +:103890000100010100000002010000000000000022 +:1038A0000000000000000001000101000000000015 +:1038B0000000000000010101000101010001010000 +:1038C00001000000010001010101010101010101EC +:1038D00000000000000001000001010101010101E0 +:1038E00000000000000001010000010101000000D3 +:1038F00000000000010001000100000101010101C0 +:1039000001000000000001010000010100010000B1 +:1039100000000000000001000000000000010100A4 +:103920000100000000000100000000000000000095 +:103930000000000000000100000100000001000084 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000100000000000000000056 +:103970000000000000000100000000000000000046 +:103980000000000000000000010000010000000035 +:103990000100010100000002010000000000000021 +:1039A0000000000000000001000101000000000014 +:1039B00000000000000101010001010100010100FF +:1039C00001000000010101010101010101010101EA +:1039D00000000000000001000001010101010101DF +:1039E00000000000000001010000010101010000D1 +:1039F00000000000010001010100000101010101BE +:103A000001000000000001010000010100010000B0 +:103A100000000000000001000000000000010100A3 +:103A20000100000000000100000000000000000094 +:103A30000000000000000100000100000001000083 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000100000000000000000055 +:103A70000000000000000100000000000000000045 +:103A80000000000000000000010000010000000034 +:103A90000100010100000002010000000000000020 +:103AA0000000000000000001010102000000000011 +:103AB00000000000010101010101010100010100FC +:103AC00001000000010101010101010101010101E9 +:103AD00000000000000001010001010101010101DD +:103AE00000000000000001010000010101010000D0 +:103AF00000000000010001010100010101010101BC +:103B000001000000000001010000010100010000AF +:103B100000000000000101000000000000010100A1 +:103B20000100000001000100000000000000000191 +:103B30000000000000000100000100000001000082 +:103B40000000000000000100000000000000000074 +:103B50000000000000000000000000000000000065 +:103B60000000000000000100000000000000000054 +:103B70000000000001000100000000000000000043 +:103B80000000000000000000010000010000000033 +:103B9000010101010100000202000100000000001B +:103BA0000000000000000001010102000000000010 +:103BB00000000000010101010101010100010100FB +:103BC00001000000010101010101010101010101E8 +:103BD00000000000000001010001010101010101DC +:103BE00000000000000001010000010101010000CF +:103BF00000000000010001010100010101010101BB +:103C000001000000000001010000010100010000AE +:103C100000000000000101000000000000010100A0 +:103C2000010000010101010000000000000000018E +:103C30000000000000000100010100000001000080 +:103C40000000000000000100000000000000000073 +:103C50000000000000000000000000000000000064 +:103C60000000000000000100000000000000000053 +:103C70000000000101010100000000000000000040 +:103C80000000000000000000010000010000000131 +:103C90000101010101010002020002000000000018 +:103CA000000000000000000101020200000000000E +:103CB00000000000010101010102010100010100F9 +:103CC00001000000010101010101010101010101E7 +:103CD00000000000000001010101010101010101DA +:103CE00000000000000001010100010101010000CD +:103CF00000000000010001010100010101010101BA +:103D000001000000000001010000010100010000AD +:103D1000000000000001010000000000000101009F +:103D2000010000010101010000000000000000018D +:103D3000000000000000010001010000000100007F +:103D40000000000000000100010000000000000071 +:103D50000000000000000000000000000000000063 +:103D60000000000000000100000000000000000052 +:103D7000000001010101010000000000000000003E +:103D8000000000000000000001000001010000012F +:103D90000101010101010002020102000000000016 +:103DA000000000000000000101020200000000000D +:103DB00000000000010101010102010100010100F8 +:103DC00001000000010101010101010101010101E6 +:103DD00000000100000001010101020101010101D7 +:103DE00000000001000001010100010101010000CB +:103DF00000000000010101010100010101010101B8 +:103E000001000000010001010000010100010000AB +:103E1000000000000001010000000000000101009E +:103E2000010000010101010000000000000000018C +:103E3000000000010000010001010000000100017C +:103E40000000000000000100010000000000000070 +:103E50000000000000000000000000000000000062 +:103E60000000000000000100000000000000000051 +:103E7000000001010101010000000000000000003D +:103E8000000000000000000001000101010101012B +:103E90000101010101010002020202000000000014 +:103EA000000000000000000101020200000000000C +:103EB00000000000010101010102010101010100F6 +:103EC00001000100010101020101010101010101E3 +:103ED00000000100000001010101020101010101D6 +:103EE00000000001000001010100010101010000CA +:103EF00000000000010101010100010101010101B7 +:103F000001010000010001010000010100010000A9 +:103F1000000000000001010000000000000101009D +:103F2000010000010101010001000000000000018A +:103F3000000000010000010001010000000100017B +:103F4000000000000000010001000000000000006F +:103F50000000000000000000000000000000000061 +:103F60000000000000000100000000000000000050 +:103F7000010001010101010000000000000000003B +:103F80000000000000000100010001010101010129 +:103F90000101010101010002020202000000000013 +:103FA000000000000000000201020200000000000A +:103FB00000000000010101010102010101010100F5 +:103FC00001000101010101020102010101010101E0 +:103FD00000000100000001010102020101010101D4 +:103FE00000000001000001010100010101010000C9 +:103FF00000000000010101010100010101010101B6 +:1040000001010000010001010100010100010000A7 +:10401000000000000101010000000000000101009B +:104020000100000101010100010001000000000188 +:104030000000000100010100010100000001000179 +:10404000000000000000010001000000000000006E +:10405000000000000000010000000000000000005F +:10406000000000000000010000000000000000004F +:10407000010001010101010000000000000000003A +:104080000000000000000100010001010101010128 +:104090000101010101010002020202000000000012 +:1040A0000000000000000002010202000000000009 +:1040B00000000000010101010102010101010100F4 +:1040C00001000101010101020102020101010101DE +:1040D00000000100000101010102020101010101D2 +:1040E00000000001000001010100010101010000C8 +:1040F00000000000010101010101010101010101B4 +:1041000001010001010101010100010100010000A4 +:104110000000000101010100010000010101010096 +:104120000100000101010100010001000000000187 +:104130000000010101010100010100000001000176 +:10414000000000000000010001000000000000006D +:10415000000000000000010000000000000000005E +:10416000000000010001010000000000000000004C +:104170000100010101010100000000000000000039 +:104180000000000000000100010001010101010127 +:104190000101010101010002020202000000000011 +:1041A0000000000000000002010202000000000008 +:1041B00000000000010101020102010101010100F2 +:1041C00001000101010101020102020101010101DD +:1041D00001000100000101010102020101010101D0 +:1041E00000000001000001010100010101010100C6 +:1041F00000000000010101010101010101010101B3 +:1042000001010001010101010100010100010000A3 +:104210000000000101010100010100010101010094 +:104220000100000101010100010101000000000185 +:104230000000010101010100010100000001000175 +:10424000000000000000010001000000000000006C +:10425000000000000000010000000000000000005D +:10426000000000010101010000000000000000004A +:104270000101010101010101000000000000000036 +:104280000000000000000100010001010101010126 +:10429000010101010101010202020200000000000F +:1042A0000000000000000002010202000000000007 +:1042B00000000000010101020102010101010100F1 +:1042C00001000101010101020102020101010101DC +:1042D00001000100000101010102020201010101CE +:1042E00000000001010001020100010101010100C3 +:1042F00000000000010101010101010101010101B2 +:1043000001010001010101010100010100010000A2 +:104310000000000101010101010100010101010092 +:104320000100000101010101010101000000000183 +:104330000000010101010100010100000001000174 +:10434000000000000000010001000000000000006B +:10435000000000000000010000000000000000005C +:104360000000000101010100010000000000000048 +:104370000101010101010101000000000000000035 +:104380000000000000000100010001010101010125 +:10439000010101010101010202020200000000000E +:1043A0000000000000000002020202000000000005 +:1043B00000000000010101020102020101010100EF +:1043C00001000101010101020102020101010101DB +:1043D00001000100000101010102020202010101CC +:1043E00000000001010001020100010101010100C2 +:1043F00000000001010101010101010101010101B0 +:1044000001010001010101010100010100010000A1 +:10441000000001010101010101010101010101008F +:104420000100000101010101010101000000000182 +:104430000000010101010100010100000001000173 +:10444000000000000000010001000000000000006A +:10445000000000000000010000000000000000005B +:104460000000010101010100010000000000000046 +:104470000101010101010101000000000000000034 +:104480000000010000000100010101010101010122 +:10449000010101010101010202020200000000000D +:1044A0000000000000000002020202000000000004 +:1044B00000000000010101020102020101020100ED +:1044C00001000101010101020102020101020101D9 +:1044D00001000100000101020102020202010101CA +:1044E00000000001010001020100010102010100C0 +:1044F00000000001010101010101010101010101AF +:10450000010100010101010101010101000100009F +:10451000000001010101010101010101010101008E +:104520000100000101010101010101000000000181 +:104530000000010101010100010100000001000172 +:104540000000000000000100010000000000000069 +:10455000000000000000010000000000000000005A +:104560000000010101010100010000000000000045 +:104570000101010101010101000000000000000033 +:104580000000010100000100010101010101010120 +:10459000010101010101010202020200000000000C +:1045A0000000000000010002020202000000000002 +:1045B00000000000010101020102020101020200EB +:1045C00001000101010101020202020101020101D7 +:1045D00001000100000101020102020202020101C8 +:1045E00000000001010001020100020102010100BE +:1045F00000010001010101010201010101010101AC +:10460000010100010101010201010101000100009D +:10461000000001010101010101010101010101008D +:104620000100000101010101010101000000000180 +:104630000000010101010101010100000001000170 +:104640000000000000000100010000000000000068 +:104650000000000000000100000000000000000059 +:104660000000010101010100010000000000000044 +:104670000101010101010101000000000000000032 +:10468000000001010100010001010101010101011E +:10469000010101010101010202020200000000000B +:1046A0000000000000010002020202000000000001 +:1046B00000000000010101020102020101020200EA +:1046C00001000101010101020202020102020102D4 +:1046D00001000101000101020102020202020101C6 +:1046E00000000001010001020100020102010101BC +:1046F00000010001010101020201010101010101AA +:10470000010100010101010201010101000100009C +:10471000000001010101010101010101010101008C +:10472000010000010101010101010100000000017F +:10473000000001010101010101010000000100016F +:104740000000000000010100010000000000000066 +:104750000000000000000100000000000000000058 +:104760000000010101010100010000000000000142 +:104770000101010101010101000000000000000031 +:10478000000001010101010001010101010101011C +:10479000010101010101010202020200000000000A +:1047A0000000000000010002020202000000000000 +:1047B00000000000010101020102020201020200E8 +:1047C00001000101010101020202020202020102D2 +:1047D00001000101000101020202020202020201C3 +:1047E00000000001010001020100020202010101BA +:1047F00000010001010101020201010101010101A9 +:10480000010101010101010201010101000100009A +:10481000000001010101010101010101010101008B +:10482000010000010101010101010100000000017E +:10483000000001010101010101010000000100016E +:104840000000000001010100010000000000000064 +:104850000000000000000100010000000000000056 +:104860000000010101010100010000000000000141 +:104870000101010101010101000000000000000030 +:10488000000001010101010001010101010101011B +:104890000101010101010102020202000000000009 +:1048A00000000000000100020202020000000000FF +:1048B00000000000010101020202020201020200E6 +:1048C00001000101010101020202020202020102D1 +:1048D00001000101000101020202020202020201C2 +:1048E00000000101010001020200020202010101B7 +:1048F00000010001010101020201010101020101A7 +:104900000101010101010102010101010001000099 +:10491000000001010101010101010101010101008A +:10492000010001010101010101010100000000017C +:10493000000001010101010101010000000100016D +:104940000000000101010101010000000000000061 +:104950000000000000000100010000000000000055 +:10496000000101010101010001000000000000013F +:10497000010101010101010100000000000000002F +:10498000000001010101010001010101010101011A +:104990000101010101010102020202000000000008 +:1049A00000000000000100020202020000000000FE +:1049B00000000000010101020202020201020200E5 +:1049C00001000101010101020202020202020202CF +:1049D00001000101010101020202020202020201C0 +:1049E00000000101010101020201020202010101B4 +:1049F00000010001010101020201020101020201A4 +:104A00000101010101010102010102010101000096 +:104A10000000010101010101010101010101010089 +:104A2000010001010101010101010100000000017B +:104A3000000001010101010101010000000100016C +:104A4000000001010101010101000000000000005F +:104A50000000000100000100010000000000000053 +:104A6000000101010101010001000000000000013E +:104A7000010101010101010101000000000000002D +:104A80000100010101010100010101010101010118 +:104A90000101010101010102020202000000000007 +:104AA00000000000000100020202020000000000FD +:104AB00000000100010101020202020201020200E3 +:104AC00001000101010101020202020202020202CE +:104AD00001000101010101020202020202020201BF +:104AE00000000101010101020201020202010101B3 +:104AF00000010101010101020201020201020201A1 +:104B00000101010101010102010102020101000094 +:104B10000001010101010101010101010101010087 +:104B2000010001010101010101010100000000017A +:104B30000000010101010101010200000001010169 +:104B4000000001010101010101000000000000005E +:104B50000000000100000100010000000000000052 +:104B6000000101010101010001000000000000013D +:104B7000010101010101010101000000000000002C +:104B80000101010101010100000101010101010117 +:104B90000101010101010102020202000000000006 +:104BA00000000000000100020202020000000000FC +:104BB00000000100010101020202020201020200E2 +:104BC00001000101010101020202020202020202CD +:104BD00001000101010101020202020202020201BE +:104BE00000000101010101020201020202010101B2 +:104BF000000101010101010202020202010202019F +:104C00000101010101010102010102020101000093 +:104C10000001010101010101010101010102010085 +:104C20000101010101010101010101000000000178 +:104C30000001010101010101010200010101010165 +:104C4000000001010101010101010000000000005C +:104C50000000000100010100010000000000000050 +:104C6000010101010101010001000000000000013B +:104C7000010101010101010101000000000000002B +:104C80000101010101010100000101010101010116 +:104C90000101010101010102020202010000000004 +:104CA00000000000000100020202020000000000FB +:104CB00000000100010102020202020201020200E0 +:104CC00001000101010101020202020202020202CC +:104CD00001010101010101020202020202020202BB +:104CE00001000101010101020201020202020101AF +:104CF000010101010101010202020202010202019D +:104D00000101010101010102010102020101000092 +:104D10000001010101010102010101010102010083 +:104D20000101010101010102020101010100000173 +:104D30000001010101010101020200010101010163 +:104D4000000001010101010102010000000000005A +:104D5000000001010101010001000000000000004D +:104D60000101010101010100010000000100000139 +:104D7000010101010101010101000000000000002A +:104D80000101010101010100000101010101010115 +:104D90000101010101010102020202020000000002 +:104DA00000000000000100020202020000000000FA +:104DB00000000100010102020202020201020200DF +:104DC00001000101010101020202020202020202CB +:104DD00001010101010101020202020202020202BA +:104DE00001000101010101020201020202020101AE +:104DF000010101010101010202020202020202019B +:104E00000101010101010102020102020101000090 +:104E1000010101010101010202020101010201007F +:104E20000101010101010102020201010100000171 +:104E30000001010101010101020200010101010162 +:104E40000000010101010101020101000000000058 +:104E5000000001010101010001000001000000014A +:104E60000101010101010100010000000100010137 +:104E70000101010101010101010000010000000127 +:104E80000101010101010100000101010101010114 +:104E90000101010101010102020202020000000001 +:104EA00000000000000100020202020000000000F9 +:104EB00000000100010102020202020201020200DE +:104EC00002000101010101020202020202020202C9 +:104ED00001010101010101020202020202020202B9 +:104EE00001000101010101020201020202020101AD +:104EF000010101010101010202020202020202019A +:104F0000020101010101010202010202010200008D +:104F1000010101010101010202020101010201017D +:104F2000010101010101010202020201010000016F +:104F30000101010101010101020200010101010160 +:104F40000000010101010101020101000000000057 +:104F50000000010101010100010000010000000149 +:104F60000101010101010101010000010100010134 +:104F70000101010101010101010000010000000126 +:104F80000101010101010100000100010101010114 +:104F900001010101010101020202020200010000FF +:104FA00000000000000100020202020000000000F8 +:104FB00000000100010102020202020202020200DC +:104FC00002000101010101020202020202020202C8 +:104FD00001010101010101020202020202020202B8 +:104FE00001000101010101020202020202020101AB +:104FF0000101010101010102020202020202020199 +:10500000020101010101010202020202010200008B +:10501000010101010101010202020101010202017B +:10502000010101010101010202020201010000016E +:10503000010101010101010202020001010101015E +:105040000100010101010101020101000000000055 +:105050000000010101010101010000010000000147 +:105060000101010101010101010100010101010131 +:105070000101010101010102010000010100000123 +:105080000101010101010100020100000101010112 +:1050900001010101010101020202020201020000FC +:1050A00000000000000100020202020000000000F7 +:1050B00000000100010202020202020202020200DA +:1050C00002000101010101020202020202020202C7 +:1050D00001010101010101020202020202020202B7 +:1050E00001000101010101020202020202020101AA +:1050F0000101010101010102020202020202020297 +:10510000020101010101010202020202010200008A +:105110000101010101010102020202010102020179 +:10512000020101010101010202020201010000016C +:10513000010101010101010202020101010201015B +:105140000101010101010102020101000000000052 +:105150000000010101010101010000010000000146 +:105160000101010101010101010100010101010130 +:105170000101010101010102010000010101010120 +:105180000101010101010100020100000101010111 +:1051900001010101010101020202020202020100F9 +:1051A00000010000000100020202020000010000F4 +:1051B00000000100020202020202020202020200D8 +:1051C00002000101010101020202020202020202C6 +:1051D00001010101010102020202020202020202B5 +:1051E00001010101010102020202020202020101A7 +:1051F0000101010101010102020202020202020296 +:105200000201010101010102020202020102000188 +:105210000101010101010102020202010102020178 +:10522000020101010101010202020201010000016B +:10523000010101010101010202020101010201015A +:105240000101010101010102020101000000000051 +:105250000000010101010101010000010100000144 +:10526000010101010101010102010101010101012D +:10527000010101010101010201000001010101011F +:105280000101010101010100020100000101010110 +:1052900001010101010101020202020202020200F7 +:1052A00000010000000100020202020100010000F2 +:1052B00000000100020202020202020202020200D7 +:1052C00002000101010102020202020202020202C4 +:1052D00001010101010102020202020202020202B4 +:1052E00001010101010102020202020202020201A5 +:1052F0000101010101010102020202020202020295 +:105300000201010101010102020202020102000187 +:105310000101010101010102020202020102020176 +:10532000020101010101010202020201010000016A +:105330000101010101010102020201010102010159 +:105340000101010101010102020101000000000050 +:105350000100010101010101010100010100010140 +:10536000010101010101010102010101010101012C +:10537000010101010101010201000001010101011E +:10538000010101010101010002010000010101010F +:1053900001010101010101020202020202020200F6 +:1053A00000010000000200020202020100010000F0 +:1053B00000000100020202020202020202020200D6 +:1053C00002000101010102020202020202020202C3 +:1053D00001010101010102020202020202020202B3 +:1053E00001010101010102020202020202020201A4 +:1053F0000101010102010202020202020202020292 +:105400000201010101010102020202020102000186 +:105410000101010101010102020202020102020175 +:105420000201010101010102020202010101000168 +:105430000101010101010102020201010102010158 +:10544000010101010101010202010100000000004F +:10545000010001010101010102010001010001013E +:10546000010101010101010102010101010101012B +:10547000010101010101010201000001010101011D +:10548000010101010101010002010000000101010F +:1054900001010101010101020202020202020200F5 +:1054A00000010000000200020202020100010000EF +:1054B00000000100020202020202020202020200D5 +:1054C00002000101010102020202020202020202C2 +:1054D00001010101010102020202020202020202B2 +:1054E00001010102010102020202020202020201A2 +:1054F0000101010102010202020202020202020291 +:105500000201010101010202020202020102010183 +:105510000101010101010102020202020202020173 +:105520000201010101010102020202010101000266 +:105530000101010101010102020201010102010157 +:10554000010101010101010202020100000000004D +:10555000010001010101010102010001010101013C +:10556000010101010101010102010101010101012A +:10557000010101010101010201010101010101011A +:10558000010101010101010002020000000001010E +:1055900001010101010101020202020202020200F4 +:1055A00000010000000200020202020100010000EE +:1055B00000000100020202020202020202020200D4 +:1055C00002000101010102020202020202020202C1 +:1055D00002010201010102020202020202020202AF +:1055E00001010102010102020202020202020201A1 +:1055F0000101010102010202020202020202020290 +:105600000201010101010202020202020102010182 +:105610000101010101010102020202020202020172 +:105620000201010101010202020202010101010263 +:105630000101010101010102020201010102010156 +:10564000010101010101010202020100000000004C +:105650000101010101010102020100010101010139 +:105660000101010101010102020101010101010128 +:105670000101010101010102010101010101010119 +:10568000010101010101010002020000000000010E +:1056900001010101010101020202020202020201F2 +:1056A00001020000000200020202020200020000E9 +:1056B00000000100020202020202020202020201D2 +:1056C00002000101020102020202020202020202BF +:1056D00002010201010102020202020202020202AE +:1056E00001010102010102020202020202020201A0 +:1056F000010101010201020202020202020202028F +:105700000202010101010202020202020102010180 +:105710000101010101010202020202020202020170 +:105720000201010101010202020202010101010262 +:105730000101010101010202020201010102010154 +:10574000010101010101010202020101000000004A +:105750000101010101010102020101010101010137 +:105760000101010101010102020101010101010127 +:105770000101010101010102020101010101010117 +:10578000010101010101010002020000000000010D +:1057900000010101010101020202020202020202F1 +:1057A00001020000000200020202020200020000E8 +:1057B00000000100020202020202020202020201D1 +:1057C00002010101020202020202020202020202BC +:1057D00002010201010102020202020202020202AD +:1057E000010101020101020202020202020202029E +:1057F000010101010201020202020202020202028E +:10580000020201010101020202020202010201017F +:10581000010101010101020202020202020202016F +:105820000201010101010202020202010101010261 +:105830000101010101010202020201010102010153 +:105840000101010101010102020202010000000048 +:105850000101010101010102020101010101010136 +:105860000101010101010102020101010101010126 +:105870000101010101010102020101010101010116 +:10588000010101010101010002020000000000000D +:1058900000010101010101020202020202020202F0 +:1058A00002020000000200020202020200020000E6 +:1058B00000000200020202020202020202020201CF +:1058C00002010201020202020202020202020202BA +:1058D00002010201010102020202020202020202AC +:1058E000010101020201020202020202020202029C +:1058F000010201010202020202020202020202028B +:10590000020201010101020202020202010201017E +:10591000010101010101020202020202020202016E +:105920000201010101010202020202010101010260 +:105930000101010101010202020201010102010251 +:105940000101010101010102020202010000000146 +:105950000101010101010102020101010101010135 +:105960000101010101010102020201010101010124 +:105970000101010101010102020101010101010115 +:10598000010101010101010002020200000000000A +:1059900000010101010101020202020202020202EF +:1059A00002020000000200020202020200020100E4 +:1059B00000000200020202020202020202020201CE +:1059C00002010202020202020202020202020202B8 +:1059D00002010201010202020202020202020202AA +:1059E0000201020202010202020202020202020299 +:1059F000010201010202020202020202020202028A +:105A0000020201010201020202020202020201017B +:105A1000010101010101020202020202020202016D +:105A2000020101020201020202020202010101025C +:105A3000010101010101020202020201010201024F +:105A40000101010101010102020202010000000145 +:105A50000101010101010102020201010101010133 +:105A60000101010101010102020201010101010123 +:105A70000101010101010102020101010101010114 +:105A80000101010101010100020202020000000007 +:105A900000000101010101020202020202020202EF +:105AA00002020000000200020202020200020100E3 +:105AB00001000200020202020202020202020201CC +:105AC00002010202020202020202020202020202B7 +:105AD00002010201010202020202020202020202A9 +:105AE0000201020202010202020202020202020298 +:105AF0000102010202020202020202020202020288 +:105B00000202010202010202020202020202010179 +:105B1000010101010102020202020202020202016B +:105B2000020101020202020202020202010101025A +:105B3000010101020101020202020202010201024C +:105B40000101010101010102020202010100000143 +:105B50000101010101010102020201010101010132 +:105B60000101010101010102020201010101010122 +:105B70000101010101010102020101010101010113 +:105B80000101010101010100020202020000000006 +:105B900000000000010101020202020202020202F0 +:105BA00002020000000200020202020200020100E2 +:105BB00001010200020202020202020202020201CA +:105BC00002010202020202020202020202020202B6 +:105BD00002020202010202020202020202020202A6 +:105BE0000201020202010202020202020202020297 +:105BF0000202010202020202020202020202020286 +:105C00000202010202020202020202020202010177 +:105C1000010101010102020202020202020202016A +:105C20000201010202020202020202020201010258 +:105C3000010102020101020202020202010201024A +:105C40000101010101010102020202010101010140 +:105C50000101010101010102020201010101010131 +:105C6000010101010101020202020201010101011F +:105C70000201010101010202020101010101010110 +:105C80000101010101010100020202020000000005 +:105C900000000000000101020202020202020202F0 +:105CA00002020100000200020202020200020201DE +:105CB00001010200020202020202020202020201C9 +:105CC00002010202020202020202020202020202B5 +:105CD00002020202010202020202020202020202A5 +:105CE0000202020202020202020202020202020294 +:105CF0000202010202020202020202020202020285 +:105D00000202010202020202020202020202010176 +:105D10000101010202020202020202020202020167 +:105D20000201010202020202020202020201010257 +:105D30000101020202020202020202020202010246 +:105D4000010101010101010202020201010101013F +:105D5000010101010101010202020102010101012F +:105D6000010101010101020202020201010101011E +:105D7000020102020201020202020101010101010B +:105D80000101010101010100020202020000000004 +:105D900000000000000001020202020202020202F0 +:105DA00002020201000200020202020200020201DB +:105DB00001010200020202020202020202020201C8 +:105DC00002010202020202020202020202020202B4 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202020202020202020293 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202010174 +:105E10000101020202020202020202020202020165 +:105E20000201010202020202020202020201010256 +:105E30000101020202020202020202020202020244 +:105E4000010101010101010202020201010101013E +:105E5000010101010101010202020202010101012D +:105E6000010101010101020202020202010101011C +:105E70000202020202020202020201010101010108 +:105E80000101010101010100020202020200000001 +:105E900002000200000001020202020202020202EB +:105EA00002020202010200020202020200020202D7 +:105EB00002010200020202020202020202020201C6 +:105EC00002010202020202020202020202020202B3 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202020202020202020292 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202010173 +:105F10000101020202020202020202020202020164 +:105F20000201010202020202020202020201010255 +:105F30000101020202020202020202020202020243 +:105F4000010101010101020202020201010101013C +:105F5000010101010101010202020202010101012C +:105F60000101010201010202020202020201010218 +:105F70000202020202020202020202020101010105 +:105F800001010101010101000202020202020002FC +:105F900002020202000001020202020202020202E6 +:105FA00002020202020200020202020200020202D5 +:105FB00002020201020202020202020202020201C3 +:105FC00002010202020202020202020202020202B2 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202010172 +:106010000102020202020202020202020202020261 +:106020000202020202020202020202020202010251 +:106030000102020202020202020202020202020241 +:10604000010101010101020202020201010101013B +:10605000010101010101010202020202010101012B +:106060000101020202020202020202020201010214 +:106070000202020202020202020202020101010104 +:1060800001010101010101000202020202020202F9 +:1060900002020202000001020202010202020202E6 +:1060A00002020202020200020202020202020202D2 +:1060B00002020201020202020202020202020201C2 +:1060C00002010202020202020202020202020202B1 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:106100000202020202020202020202020202010171 +:10611000020202020202020202020202020202025F +:106120000202020202020202020202020202010250 +:10613000020202020202020202020202020202023F +:106140000101010101010202020202020101010139 +:106150000101010101010202020202020201010128 +:106160000102020202020202020202020202020210 +:106170000202020202020202020202020101010103 +:1061800001010101010101000202020202020202F8 +:1061900002020202000001020202010202020202E5 +:1061A00002020202020200020202020202020202D1 +:1061B00002020201020202020202020202020202C0 +:1061C00002010202020202020202020202020202B0 +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:106240000101010101010202020202020101010138 +:106250000101010101010202020202020201010226 +:10626000020202020202020202020202020202020E +:106270000202020202020202020202020201010101 +:1062800001010201010101000202020202020202F6 +:1062900002020202020001020202010202020202E2 +:1062A00002020202020200020202020202020202D0 +:1062B00002020201020202020202020202020202BF +:1062C00002010202020202020202020202020202AF +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:106340000101020202020202020202020101010133 +:106350000101010201010202020202020202020222 +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020101FF +:1063800002010202010102020202020202020202F0 +:1063900002020202020201020201010202020202E0 +:1063A00002020202020200020202020202020202CF +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:106440000201020202020202020202020101010131 +:106450000101020201010202020202020202020220 +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020102020202020202020202ED +:1064900002020202020201020201010202010102E1 +:1064A00002020202020200020202020202020202CE +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020101012E +:10655000020102020202020202020202020202021C +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020201010101010101E2 +:1065A00001010101010101020202010202020202D3 +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020201012C +:10665000020102020202020202020202020202021B +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020101010101010101E2 +:1066A00001010101010101020201010202020202D3 +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020101010101010101E1 +:1067A00001010101010101020201010202020202D2 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202010101010101010101E1 +:1068A00001010101010101020201010202020202D1 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202010101010101010101E0 +:1069A00001010101010101020201010202020202D0 +:1069B00002020202020202020202020202010102B9 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202010101010101010101DF +:106AA00001010101010101020201010202010201D1 +:106AB00001010101010101020201020202020202BE +:106AC00002020202020202020202020202010201A8 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202010101010101010101DE +:106BA00001010101010101020101010202010101D2 +:106BB00001010101010101020202010102010102C0 +:106BC00002020202020202020202010201020102A8 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202010101010101010101DD +:106CA00001010101010101020101010102010101D2 +:106CB00001010101010101020201020201010102BF +:106CC00001020202020202020201020102010201A9 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202010101010101010101DC +:106DA00001010101010101010101010101010101D3 +:106DB00001010101010101020201010102010102BF +:106DC00002020202020202020202010201010101A8 +:106DD0000202020202020202020202020201010295 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202010101010101010101DB +:106EA00001010101010101010101010101010101D2 +:106EB00001010101010101020201010101010102BF +:106EC00001020202020202020201010101010101AA +:106ED0000101010202020202020201010102020199 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202010101010101010101DA +:106FA00001010101010101010101010101010101D1 +:106FB00001010101010101010101010101010101C1 +:106FC00001010101010101010101010101010101B1 +:106FD0000202020101010102020102020201010298 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202010101010101010101D9 +:1070A00001010101010101010101010101010101D0 +:1070B00001010101010101020201010101010102BD +:1070C00001020202020202020201010101010101A8 +:1070D0000101010202020202020201010101010199 +:1070E0000101010102020202020202020202020284 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202010101010101010101D8 +:1071A00001010101010101010101010101010101CF +:1071B00001010101010101010101010101010101BF +:1071C00001010101010101010101010101010101AF +:1071D000010101010101010202010101010101019D +:1071E0000202020201010102020202020202020282 +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202010101010101010101D7 +:1072A00001010101010101010101010101010101CE +:1072B00001010101010101010101010101010101BE +:1072C00001010101010101010101010101010101AE +:1072D000010101010101010201010101010101019D +:1072E0000101010102020202020202020101020284 +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202010101010101010101D6 +:1073A00001010101010101010101010101010101CD +:1073B00001010101010101010101010101010101BD +:1073C00001010101010101010101010101010101AD +:1073D000010101010101010102010101010101019C +:1073E0000101010101010102020201010202010287 +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202010101010101010101D5 +:1074A00001010101010101010101010101010101CC +:1074B00001010101010101010101010101010101BC +:1074C00001010101010101010101010101010101AC +:1074D000010101010101010201010101010101019B +:1074E0000101010101010102020202020101020186 +:1074F0000101020201020202020202020201010271 +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202010101010101010101D4 +:1075A00001010101010101010101010101010101CB +:1075B00001010101010101010101010101010101BB +:1075C00001010101010101010101010101010101AB +:1075D000010101010101010101010101010101019B +:1075E0000101010101010102010101010101010289 +:1075F0000202010102010102020201010102020173 +:10760000010202020202020202020202020202025B +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202010101010101010101D3 +:1076A00001010101010101010101010101010101CA +:1076B00001010101010101010101010101010101BA +:1076C00001010101010101010101010101010101AA +:1076D000010101010101010101010101010101019A +:1076E0000101010101010101020201010101010188 +:1076F0000101020201020202010102020201010271 +:10770000020102020202020202020202020202025A +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202010101010101010101D2 +:1077A00001010101010101010101010101010101C9 +:1077B00001010101010101010101010101010101B9 +:1077C00001010101010101010101010101010101A9 +:1077D0000101010101010101010101010101010199 +:1077E0000101010101010102010101010101010188 +:1077F0000101010101010102020201010101010176 +:10780000010201010101010202020202020202025E +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202010101010101010101D1 +:1078A00001010101010101010101010101010101C8 +:1078B00001010101010101010101010101010101B8 +:1078C00001010101010101010101010101010101A8 +:1078D0000101010101010101010101010101010198 +:1078E0000101010101010101010101010101010188 +:1078F0000101010101010101010101010101010178 +:107900000101020202020202020202020202020259 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202010101010101010101D0 +:1079A00001010101010101010101010101010101C7 +:1079B00001010101010101010101010101010101B7 +:1079C00001010101010101010101010101010101A7 +:1079D0000101010101010101010101010101010197 +:1079E0000101010101010101010101010101010187 +:1079F0000101010101010102010101010101010176 +:107A00000101010101010102020201010201020260 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202010101010101010101CF +:107AA00001010101010101010101010101010101C6 +:107AB00001010101010101010101010101010101B6 +:107AC00001010101010101010101010101010101A6 +:107AD0000101010101010101010101010101010196 +:107AE0000101010101010101010101010101010186 +:107AF0000101010101010101010101010101010176 +:107B00000101010101010102020101010101020261 +:107B10000202020202020202020202020201010247 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202010101010101010101CE +:107BA00001010101010101010101010101010101C5 +:107BB00001010101010101010101010101010101B5 +:107BC00001010101010101010101010101010101A5 +:107BD0000101010101010101010101010101010195 +:107BE0000101010101010101010101010101010185 +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010102020101010101010251 +:107C20000102020202020202020101020202020138 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202010101010101010101CD +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD0000101010101010101010101010101010194 +:107CE0000101010101010101010101010101010184 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010102010101010101010152 +:107D2000010101010101010201020201010101023F +:107D3000010101010101010202020202020202022A +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202010101010101010101CC +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E2000010101010101010102010102020202013D +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202010101010101010101CB +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010102010101010101010140 +:107F3000010101010101010202010202020102022A +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202010101010101010101CA +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:10803000010101010101010201010101010101012F +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202010101010101010101C9 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:108140000101010101010102010101020202020219 +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202010101010101010101C8 +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:108250000101010101010102020202020202020205 +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202010101010101010101C7 +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010201010101010101010C +:1083600001010101010101020101010101010101FC +:1083700001010101010101020202020202020202E4 +:1083800002020202020202020202020202020202CD +:1083900002020202020202010101010101010101C6 +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010202020202020202F4 +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202010101010101010101C5 +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101020101010101010101FA +:1085700001010101010101010101010101010101EB +:1085800001010101010101020202020202020202D2 +:1085900002020202020202010101010101010101C4 +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101020202020202020202E1 +:1086800002020202020202020202020202020202CA +:1086900002020202020202010101010101010101C3 +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101020202020202020202D0 +:1087900002020202020202010101010101010101C2 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101020202020202020202CF +:1088900002020202020202010101010101010101C1 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:108920000101010101010101010101010101010137 +:108930000101010101010101010101010101010127 +:108940000101010101010101010101010101010117 +:108950000101010101010101010101010101010107 +:1089600001010101010101010101010101010101F7 +:1089700001010101010101010101010101010101E7 +:1089800001010101010101020202020202020202CE +:1089900002020202020202010101010101010101C0 +:1089A00001010101010101010101010101010101B7 +:1089B00001010101010101010101010101010101A7 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000101010101010101010101010101010177 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101020101010101010101D5 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101020101010101010101D4 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101020202020202020202AC +:108BB0000202020202020202020202020202020295 +:108BC0000202020202020202020202020202020285 +:108BD0000202020202020202020202020202020275 +:108BE0000202020202020202020202020202020265 +:108BF0000202020202020202020202020202020255 +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202000000000000000000D6 +:108C900000000000000000010101010101010101CB +:108CA00001010101010101000000000000000000BD +:108CB00000000000000000020202020202020202A2 +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020202020202020202020274 +:108CE0000202020202020202020202020202020264 +:108CF0000202020202020202020202020202020254 +:108D00000202020202020202020202020202020243 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202020202D3 +:108D800002020202020202000000000000000000D5 +:108D900000000000000000010101010101010101CA +:108DA00001010101010101000000000000000000BC +:108DB00000000000000000000000000000000000B3 +:108DC0000000000000000002020202020202020291 +:108DD0000202020202020202020202020202020273 +:108DE0000202020202020202020202020202020263 +:108DF0000202020202020202020202020202020253 +:108E00000202020202020202020202020202020242 +:108E10000202020202020202020202020202020232 +:108E20000202020202020202020202020202020222 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202000000000000000000D4 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F9000000000000000005400000000000000007D +:108FA00000000000000000000000000000000000C1 +:108FB00000010000000000000000000000000000B0 +:108FC000000000000001010001000000000000009E +:108FD0000001000000000000000000000000000090 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000010001000000000000000000000000AE +:1090C000000001000001010001000000000000009C +:1090D000000101000000000000000000000000008E +:1090E000000001000000000000000000000000007F +:1090F000000001000000000000000000000000006F +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000100000002000000000000000000003C +:10913000000000000001000000010000000000012C +:10914000010000000000010000000000000000011C +:10915000000000000000000000000000000000010E +:1091600000000000000000000000000000000001FE +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000101CD +:1091A00000000202020000000000020101010001B3 +:1091B00000010001010101010101010001010000A4 +:1091C0000000010000010100010101000101000196 +:1091D0000001010001000001010101000101000086 +:1091E000000001000000000000000000000200007C +:1091F000000001000000000001010000000200006A +:10920000000000000000000000000001000001005C +:109210000001000000000200020001000100000047 +:109220000001000000020000020000020000000037 +:109230000000000000010000000100020000000129 +:10924000010000000000010000000000000001011A +:10925000000000000000000000000002000000010B +:1092600000000000000000000000000200000101FA +:1092700000000000000000000000000200000000EC +:1092800000000000000000000000000000000100DD +:1092900000000000000000000000000000000101CC +:1092A00000000202020000000000020201010001B1 +:1092B00000010101010101010101010101010100A0 +:1092C0000000010000010100010101010101010193 +:1092D0000001010001000001010101010101010083 +:1092E000000001000000000000000000000101007B +:1092F0000000010100000000010100020001000067 +:109300000000000001000100000201010202010052 +:109310000001000000000200010001010100010045 +:10932000000100000002000002010202020200002F +:109330000000000000010201010100020202000120 +:109340000101000001000100000000000201010114 +:109350000000000001000000000000020202000105 +:1093600000000000000000000000000202020101F5 +:1093700000000000000000000200020202020000E3 +:1093800000000000000000000202020002020100D2 +:1093900000000000000000000000000000000101CB +:1093A00001010202020000000202020202010001A9 +:1093B000010101010101010101010101010101019D +:1093C000000001000101010201010101010101018F +:1093D000000101000101010101010101010101017F +:1093E0000000010000010101000201000101010073 +:1093F0000000010101000100010100010001000065 +:109400000000000001000100000101010201010053 +:109410000001000000000102010101010101010041 +:109420000001000000010000020101020201010030 +:10943000000001000001020101010002020201011D +:109440000101000001000100000000020201010111 +:109450000000000001000000000000020201010104 +:1094600000000000000000000000000202010101F5 +:1094700000000000000000000200020202020000E2 +:1094800000000000000000000102020202010100D1 +:1094900000000000000000000000000000000101CA +:1094A00001020202020000000202020202010001A7 +:1094B000010101010101010101010101010101019C +:1094C000000001000101010201010101010101018E +:1094D000010101010101010101010101010101017C +:1094E000000001010001010100020102010101006F +:1094F0000000010101000100010100010001010063 +:109500000001000001010100000101010101010051 +:10951000000101000000010201010101010101003F +:10952000000100000001020001010101020101002F +:10953000000001000001010101010201020101011D +:10954000010100000100010000000202020101010E +:109550000000000001000000000002010201010102 +:1095600000000000000000000000020102010101F3 +:1095700000000000000000000200020102010000E3 +:1095800000000000000000020102010202010100CF +:1095900000000000000000000000000000000101C9 +:1095A00002020202020000000202020202010001A5 +:1095B000010101010101010101010101010101019B +:1095C000010101000101010201010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000000101010101010100020102010101006C +:1095F0000000010101000102010100010001010060 +:109600000001000001010100000101010101010050 +:10961000010101000000010101010101010101003E +:10962000000100000001020001010101010101002F +:10963000000001000001010101010201010101011D +:10964000010100010100010000000202010101010D +:109650000000000001000000000002010101010102 +:1096600000000000000000000000020101010101F3 +:1096700000000000000000000100010101010100E4 +:1096800000000000000000020101010101010100D1 +:1096900000000000000000000000000000000101C8 +:1096A00002020202020000000202020202010001A4 +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000000101010101010100010102010101006C +:1096F000000001010100010201010001000101005F +:10970000000100000101010201010101010101004C +:10971000010101010000010101010101010101003C +:10972000000100000001020001010101010101002E +:10973000000001000001010101010201010101011C +:10974000010100010101010000000201010101010C +:109750000000000001000000000002010101010101 +:1097600000000000000000000000020101010101F2 +:1097700000000000000000000102010101010100E1 +:1097800000000000000000020101010101010100D0 +:1097900000000000000000000000000000000101C7 +:1097A00002020202020000000202020202010001A3 +:1097B0000101010101020101010101010101010198 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E000000101010101010101010101010101016A +:1097F000000101010100010101010201000101005C +:10980000000100010101010101010101010101014A +:10981000010101010001010101010101010101003A +:10982000000101000001010001010101010101002D +:10983000000001000001010101010101010101011C +:10984000010100010101010000000101010101010C +:109850000000000001000000000001010101010101 +:1098600000000000000000000000010101010101F2 +:1098700000000000000000000102010101010100E0 +:1098800000000000000000010101010101010100D0 +:1098900000000000000000000000000000000102C5 +:1098A00002020202020000000202020202010001A2 +:1098B0000101010101020202010101010101010195 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000001010101010101010101010101010169 +:1098F000000101010100010101010201000101005B +:109900000001000101010101010101010101010149 +:109910000101010100010101010101010101010039 +:109920000101010001010101010101010101010029 +:10993000000001000001010101010101010101011B +:109940000101000101010100020001010101010109 +:1099500000000000010000000200010101010101FE +:1099600000000000000000000202010101010101ED +:1099700000000000000000000102010101010100DF +:1099800001000000000200010101010101010100CC +:1099900000000000000000000000000000000102C4 +:1099A00002020202020000000202020202010001A1 +:1099B0000102010102020202010101010101010192 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000001010101010101010101010101010168 +:1099F0000001010101010101010102010001010059 +:109A00000001000101010101010101010101010148 +:109A10000101010100010101010101010101010038 +:109A20000101010001010101010101010101010028 +:109A3000000001000001010101010101010101011A +:109A40000101000101010100020001010101010108 +:109A500000000000010000000200010101010101FD +:109A600000000000000000000202010101010101EC +:109A700000000000000000000101010101010100DF +:109A800001000000000200010101010101010100CB +:109A900000000000000000000000000000000102C3 +:109AA00002020202020000000202020202010001A0 +:109AB000010202020202020201010101010101018F +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000001010101010101010101010101010167 +:109AF0000101010101010101010101010001010157 +:109B00000101000101010101010101010101010146 +:109B10000101010100010101010101010101010037 +:109B20000101010001010101010101010101010027 +:109B30000000010000010101010101010101010119 +:109B40000101000101010100020201010101010105 +:109B500000000000010000000200010101010101FC +:109B600000000000000000000202010101010101EB +:109B700000000000000000000101010101010100DE +:109B800001010000000202010101010101010100C7 +:109B900000000000000000000000000000000102C2 +:109BA000020202020202000002020202020200019C +:109BB000020202020202020202010101010101018C +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000001010101010101010101010101010166 +:109BF0000101010101010101010101010001010156 +:109C00000101000101010101010101010101010145 +:109C10000101010101010101010101010101010035 +:109C20000101010101010101010101010101010025 +:109C30000000010000010101010101010101010118 +:109C40000101010101010100010201010101010104 +:109C500000000000010000000100010101010101FC +:109C600000000000000000000101010101010101EC +:109C700000000000000000000101010101010100DD +:109C800001010000000102010101010101010100C7 +:109C900000000000000000000000000000000102C1 +:109CA000020202020202000002020202020200029A +:109CB000020202020202020202020101010101018A +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000001010101010101010101010101010165 +:109CF0000101010101010101010101010001010155 +:109D00000101000101010101010101010101010144 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010024 +:109D30000100010000010101010101010101010116 +:109D40000101010101010102010201010101010101 +:109D500000000000010000000102010101010101F9 +:109D600000000000000000020101010101010101E9 +:109D700000000000000000020101010101010100DA +:109D800001010000000102010101010101010100C6 +:109D900000000000000000000000000000000102C0 +:109DA0000202020202020002020202020202000297 +:109DB0000202020202020202020201010101010288 +:109DC0000101020101010101010101010101010281 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010001010154 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010023 +:109E30000100010000010101010101010101010115 +:109E40000101010101010102010101010101010101 +:109E500000000000010000000102010101010101F8 +:109E600000000000000000020101010101010101E8 +:109E700000000000000000020101010101010100D9 +:109E800001010000000101010101010101010100C6 +:109E900000000000000000000000000000000102BF +:109EA0000202020202020002020202020202000296 +:109EB0000202020202020202020201010101010287 +:109EC000020102010102010101010101010101027E +:109ED000020202010101010101010101010101026E +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010001010153 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000100010000010101010101010101010114 +:109F40000101010101010102010101010101010100 +:109F500000000000010000000102010101010101F7 +:109F600001000000000000020101010101010101E6 +:109F700000000000000000020101010101010100D8 +:109F800001010000000101010101010101010100C5 +:109F900000000000000000000000000000000102BE +:109FA0000202020202020202020202020202000293 +:109FB0000202020202020202020201010101010286 +:109FC000020102010102020101010101010101027C +:109FD000020202010101010101010101010101026D +:109FE0000101020101010101010101010101010160 +:109FF0000101010101010101010101010001010152 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000100010000010101010101010101010113 +:10A040000101010101010101010101010101010100 +:10A0500000000000010000000101010101010101F7 +:10A0600001000000000000010101010101010101E6 +:10A0700000000000000000010101010101010100D8 +:10A0800001010001000101010101010101010100C3 +:10A0900000000000000000000000000000000102BD +:10A0A0000202020202020202020202020202000292 +:10A0B0000202020202020202020202010101010284 +:10A0C0000202020102020201010101010101010279 +:10A0D000020202010101010101010101010101026C +:10A0E000010102010101010101010101010101015F +:10A0F0000101010101010101010101010001010151 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A130000100010000010101010101010101010112 +:10A1400001010101010101010101010101010101FF +:10A1500000000000010000000101010101010101F6 +:10A1600001000000000002010101010101010101E3 +:10A1700000000000000002010101010101010100D5 +:10A1800001010001000101010101010101010100C2 +:10A1900000000000000000000000000000000102BC +:10A1A0000202020202020202020202020202000291 +:10A1B0000202020202020202020202010101010283 +:10A1C0000202020102020201010101010101010278 +:10A1D000020202010201010101010101010101026A +:10A1E000010102010101010101010101010101015E +:10A1F000010102010101010101010101000101014F +:10A20000010101010101010101010101010101013E +:10A21000020101010101010101010101010101012D +:10A22000010101010101010101010101010101011E +:10A230000100010000010101010101010101010111 +:10A2400001010101010101010101010101010101FE +:10A2500000000000010000000101010101010101F5 +:10A2600001000000000002010101010101010101E2 +:10A2700000000000000002010101010101010100D4 +:10A2800001010101000101010101010101010100C0 +:10A2900000000000000000000000000000000102BB +:10A2A0000202020202020202020202020202000290 +:10A2B0000202020202020202020202020101010281 +:10A2C0000202020202020201020201010101010274 +:10A2D0000202020202020101010101010101010267 +:10A2E000010202010101010101010101010101025B +:10A2F000010102010101010101010101000101014E +:10A30000010101010101010101010101010101023C +:10A31000020201010101010101010101010101012B +:10A32000010101010101010101010101010101011D +:10A33000010101000001010101010101010101020E +:10A3400002010101010101010101010101010102FB +:10A3500000000000010000020101010101010102F1 +:10A3600001000000000202010101010101010101DF +:10A3700001000000000002010101010101010100D2 +:10A3800001010101000101010101010101010100BF +:10A3900000000000000000000000000000000002BB +:10A3A000020202020202020202020202020200028F +:10A3B0000202020202020202020202020101010280 +:10A3C0000202020202020201020201010101010273 +:10A3D0000202020202020102010101010101010265 +:10A3E0000102020201010101010101010101010259 +:10A3F000020102010101010101010101020101014A +:10A40000010101010101010101010101010101023B +:10A41000020201010101010101010101010101012A +:10A42000010201010101010101010101010101011B +:10A43000010101000001010101010101010101020D +:10A4400002010101010101010101010101010102FA +:10A4500000000000010000020101010101010102F0 +:10A4600001000000000201010101010101010102DE +:10A4700001000000000001010101010101010100D2 +:10A4800001010101000101010101010101010100BE +:10A4900000000000000000000000000000000002BA +:10A4A000020202020202020202020202020200028E +:10A4B000020202020202020202020202020101027E +:10A4C0000202020202020201020201010101010272 +:10A4D0000202020202020202010101010101010263 +:10A4E0000202020201020101010101010101010256 +:10A4F0000201020201010101010101010101010248 +:10A500000202010101010101010101010101010238 +:10A510000202020101010101010101010101010128 +:10A520000202010101010101010101010101010119 +:10A53000010101000001010101010101010101020C +:10A5400002010101010101010101010101010102F9 +:10A5500000000000010000020101010101010102EF +:10A5600001000000000201010101010101010102DD +:10A5700001000000000201010101010101010101CE +:10A5800001010101000101010101010101010100BD +:10A5900000000000000000000000000000000002B9 +:10A5A000020202020202020202020202020200028D +:10A5B000020202020202020202020202020101027D +:10A5C0000202020202020201020201010101010271 +:10A5D0000202020202020202010201010101010261 +:10A5E0000202020202020201010101010101010253 +:10A5F0000202020201010101010101010101010246 +:10A600000202010101010101010101010101010237 +:10A610000202020101010101010101010101010127 +:10A620000202010101010101010101010101010118 +:10A63000010101000001010101010101010101020B +:10A6400002010101010101010101010101010102F8 +:10A6500000000000010000010101010101010102EF +:10A6600001000000000101010101010101010102DD +:10A6700001000000000201010101010101010101CD +:10A6800001010101000101010101010101010100BC +:10A6900000000000000000000000000000000002B8 +:10A6A000020202020202020202020202020200028C +:10A6B000020202020202020202020202020101027C +:10A6C000020202020202020102020201010101026F +:10A6D000020202020202020202020101010101025F +:10A6E0000202020202020202010101010101010251 +:10A6F0000202020202010101010101010101010244 +:10A700000202010102010101010101010101010235 +:10A710000202020101010101010101010101010225 +:10A720000202010101010101010101010101010117 +:10A730000101020000010101010101010101010209 +:10A7400002010101010101010101010101010102F7 +:10A7500000000000010000010101010101010102EE +:10A7600001010000000101010101010101010102DB +:10A7700001010000000201010101010101010101CB +:10A7800001010101010101010101010101010100BA +:10A7900000000000000000000000000000000002B7 +:10A7A000020202020202020202020202020200028B +:10A7B000020202020202020202020202020101027B +:10A7C000020202020202020102020202010101026D +:10A7D000020202020202020202020201010101025D +:10A7E0000202020202020202010101010101010250 +:10A7F0000202020202010101010101010101010243 +:10A800000202010102010101010101010101010234 +:10A810000202020201010101010101010101010223 +:10A820000202020101010101010101010101010115 +:10A830000201020000010101010101010101010207 +:10A8400002020101010101010101010101010102F5 +:10A8500000000000010000010101010101010102ED +:10A8600001010000000101010101010101010102DA +:10A8700001010000000101010101010101010101CB +:10A8800001010101010101010101010101010100B9 +:10A8900000000000000000000000000000000002B6 +:10A8A000020202020202020202020102020200028B +:10A8B000020202020202020202020202020101027A +:10A8C000020202020202020202020202020101026A +:10A8D000020202020202020202020201010101025C +:10A8E000020202020202020201010101010101024F +:10A8F0000202020202010201010101010101010241 +:10A900000202010202020201010101010101010230 +:10A910000202020201010101010101010101010222 +:10A920000202020101010101010101010101010213 +:10A930000201020000010101010101010101010206 +:10A9400002020101010101010101010101010102F4 +:10A9500000010000010000010101010101010102EB +:10A9600001010000000101010101010101010102D9 +:10A9700001010000000101010101010101010101CA +:10A9800002010101010101010101010101010100B7 +:10A9900000000000000000000000000000000002B5 +:10A9A000020202020102020202020102020200028B +:10A9B0000202020202020202020202020202010278 +:10A9C0000202020202020202020202020201010269 +:10A9D0000202020202020202020202020201010259 +:10A9E000020202020202020201010201010101024D +:10A9F000020202020201020102020101010101023E +:10AA0000020202020202020101010101010101022E +:10AA10000202020201010101010101010101010221 +:10AA20000202020101010101010101010101010212 +:10AA30000201020100020101010101010101010203 +:10AA400002020101010101010101010101010102F3 +:10AA500000010100010000010101010101010102E9 +:10AA600001010001000101010101010101010102D7 +:10AA700001010000000101010101010101010101C9 +:10AA800002010101010101010101010101010100B6 +:10AA900000000000000000000000000000000002B4 +:10AAA000020202010102020201010102020200028D +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202010267 +:10AAD0000202020202020202020202020201010258 +:10AAE000020202020202020202010201010101024B +:10AAF000020202020202020102020101010101023C +:10AB0000020202020202020101010101010101022D +:10AB1000020202020102020101010101010101021E +:10AB20000202020101010101010101010101010211 +:10AB30000201020101020101010101010101010201 +:10AB400002020101010101010101010101010102F2 +:10AB500001010100010000010101010101010102E7 +:10AB600002010001010101010101010101010102D4 +:10AB700001010000000101010101010101010101C8 +:10AB800002010101010101010101010101010100B5 +:10AB900000000000000000000000000000000002B3 +:10ABA000020202010102020201010102020200028C +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202010266 +:10ABD0000202020202020202020202020202010256 +:10ABE0000202020202020202020102010201010249 +:10ABF000020202020202020102020101010101023B +:10AC0000020202020202020101010101010101022C +:10AC10000202020202020201020202010101010219 +:10AC2000020202020202010101010101010101020D +:10AC30000201020101020101010101010101010200 +:10AC400002020102020101010101010101010102EF +:10AC500001010100020000010101010101010102E5 +:10AC600002010101010101010101010101010102D2 +:10AC700001010100000101010101010101010101C6 +:10AC800002010101010101010101010101010100B4 +:10AC900000000000000000000000000000010002B1 +:10ACA000020202010102020101010101010200028E +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202010255 +:10ACE0000202020202020202020202010201010247 +:10ACF000020202020202020102020101010101023A +:10AD00000202020202020201010202020101010228 +:10AD10000202020202020202020202020201010215 +:10AD2000020202020202010101020101010101020B +:10AD300002010201010201020102010101010102FD +:10AD400002020202020102010101010101010102EC +:10AD500001010100020100010101010101010102E3 +:10AD600002010101010101010101010101010102D1 +:10AD700001010100010101010101010101010101C4 +:10AD800002010101010101010101010101010100B3 +:10AD900000000200000000000000000000010002AE +:10ADA000020202010201020101010101010200028D +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202010202020244 +:10ADF0000202020202020202020201020101010237 +:10AE00000202020202020202020202020101010225 +:10AE10000202020202020202020202020201010214 +:10AE2000020202020202010101020101010101020A +:10AE300002010201010202020202010101010102FA +:10AE400002020202020102010101010101010102EB +:10AE500001010101020100010101010101010102E1 +:10AE600002010101010101010101010101010102D0 +:10AE700002010101010101010101010101010101C1 +:10AE800002020101010101010101010101010100B1 +:10AE900000020200000000000100010000010002A9 +:10AEA000020202020201010101010101010200028C +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202010202020243 +:10AEF0000202020202020202020201020101010236 +:10AF00000202020202020202020202020101010224 +:10AF10000202020202020202020202020201010213 +:10AF20000202020202020202010202010101010206 +:10AF300002020201010202020202010101010102F8 +:10AF400002020202020202010101010101010102E9 +:10AF500001010101020101010101010101010102DF +:10AF600002010101010101010101010101010102CF +:10AF700002010101010101010101010101010102BF +:10AF800002020101010101010101010101010100B0 +:10AF900000020200000000010101010101010002A4 +:10AFA000020202020201010101010101010200028B +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020201020102010234 +:10B000000202020202020202020202020101020222 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202010101010204 +:10B0300002020201010202020202010101010102F7 +:10B0400002020202020202010101010101010102E8 +:10B0500001010101020101010101010101010102DE +:10B0600002010101010101010101010101010102CE +:10B0700002010101010101010101010101010102BE +:10B0800002020101010101010101010101010100AF +:10B0900000010200010100010101010101010002A2 +:10B0A000020201020201010201010101010200028A +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020201020102020232 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B120000202020202020202020202010101010203 +:10B1300002020201010202020202010101010102F6 +:10B1400002020202020202010101010101010102E7 +:10B1500002010101020101010101010101010102DC +:10B1600002010101010101010101010101010102CD +:10B1700002010101010101010101010101010102BD +:10B1800002020101010101010101010101010100AE +:10B19000000102020101010101010101010100029E +:10B1A0000202010201020102010101010102000289 +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F0000202020202020202020201020102020231 +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020201020202FF +:10B2300002020201010202020202010101010102F5 +:10B2400002020202020202010101010101010102E6 +:10B2500002010101020101010101010101010102DB +:10B2600002010101010101010101010101010102CC +:10B2700002010101010101010101010101010102BC +:10B2800002020201010101010101010101010100AC +:10B29000000102010101010101010101010100029E +:10B2A0000202010101020202010101010102000288 +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202010202022F +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020201010202020202010201010202F2 +:10B3400002020202020202010101010101010102E5 +:10B3500002010101020101010101010101010102DA +:10B3600002020101010101010101010101010102CA +:10B3700002010101010101010101010101010102BB +:10B3800002020202010101010201010101010100A9 +:10B39000000002010001010101010101010100029F +:10B3A0000202010101020202010101010101000288 +:10B3B000020202020202020102020202020202026E +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202010202022E +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020201010202020202020202020202EE +:10B4400002020202020202010101010101020202E2 +:10B4500002020101020101010101010101010102D8 +:10B4600002020101010101010101010101010202C8 +:10B4700002020101010101010101010101010102B9 +:10B4800002020202010101010201010101010100A8 +:10B4900000000101000001010101010101010002A0 +:10B4A0000202020101020201010101010101000287 +:10B4B000020202020201010102020202020202026F +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202010202022D +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202010202020202020202020202EC +:10B5400002020202020202010101010101020202E1 +:10B5500002020201020101010101010201020202D3 +:10B5600002020101010101010101010201020202C5 +:10B5700002020101010101010201010101010102B7 +:10B5800002020202010201020202020101010200A2 +:10B5900000000100000001010101010101010002A0 +:10B5A0000202020101010201010101010101000287 +:10B5B000020202020201010101020202020202026F +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202010202022C +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202010202020202020202020202EB +:10B6400002020202020202010101020202020202DD +:10B6500002020201020101010101020202020202D0 +:10B6600002020201010101010101020202020202C1 +:10B6700002020101010101010201020201010102B4 +:10B68000020202020102010202020202010202009F +:10B6900000000100000000000101010101010002A1 +:10B6A0000201020101010101010101010101000288 +:10B6B000020202020201010101010202020202026F +:10B6C000020202020202020202020202020202025A +:10B6D000020202020202020202020202020202024A +:10B6E000020202020202020202020202020202023A +:10B6F000020202020202020202020202010202022B +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202010201020202020202DB +:10B7500002020201020101010201020202020202CE +:10B7600002020202010101010202020202020202BD +:10B7700002020201010101010202020202020202AE +:10B78000020202020102020202020202020202009C +:10B7900000000100000000000000010101010002A2 +:10B7A0000201020101010101010101010101000287 +:10B7B000020202020101010101010202020202026F +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020201020101010201020202020202CD +:10B8600002020202010101020202020202020202BB +:10B8700002020201010101010202020202020202AD +:10B88000020202020202020202020202020202009A +:10B8900000000100000000000000000101010002A2 +:10B8A0000201010101010101010101010101000287 +:10B8B000020202020101010101010202020202026E +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020101010202020202020202CA +:10B9600002020202020202020202020202020202B7 +:10B9700002020201010101020202020202020202AB +:10B980000202020202020202020202020202020099 +:10B9900000000100000000000000000000010002A3 +:10B9A0000201010101010101010101010101000286 +:10B9B000020202020101010101010102020202026E +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020101010202020202020202C9 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202010102020202020202020202A8 +:10BA80000202020202020202020202020202020098 +:10BA900000000100000000000000000000000002A3 +:10BAA0000201010101010101010101010101000285 +:10BAB000020202010101010101010101020202026F +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020201020202020202020202C6 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020097 +:10BB900000000000000000000000000000000002A3 +:10BBA0000101010101010101010101010101000285 +:10BBB000020201010101010101010101020202026F +:10BBC0000202020202020202020202020202020255 +:10BBD0000202020202020202020202020202020245 +:10BBE0000202020202020202020202020202020235 +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020201020202020202020202C5 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020096 +:10BC900000000000000000000000000000000002A2 +:10BCA0000101010101010101010101010101000284 +:10BCB0000201010101010101010101010102020270 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020095 +:10BD900000000000000000000000000000000002A1 +:10BDA0000101010101010101010101010101000283 +:10BDB000020101010101010101010101010202026F +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020094 +:10BE900000000000000000000000000000000002A0 +:10BEA0000101010101010101010101010101000282 +:10BEB000020101010101010101010101010202026E +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF9000000000000000000000000000000000029F +:10BFA0000101010101010101010101010101000281 +:10BFB000020101010101010101010101010202026D +:10BFC0000202020202010102020102020202020254 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C09000000000000000000000000000000000019F +:10C0A0000101010101010101010101010101000280 +:10C0B000010101010101010101010101010101026F +:10C0C0000202020201020202010202020202020252 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020000000000000000000000000000019C +:10C1A000010101010101010101010001010101027F +:10C1B000010101010101010101010101010101026E +:10C1C0000202020202010102020102020202020252 +:10C1D0000202020202010201020202020202020241 +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020000000000000000000000000000019B +:10C2A0000101010101010101000000010101010280 +:10C2B000010101010101010101010101010101026D +:10C2C0000202010101010101010101010202020258 +:10C2D0000202020201020102020102020202020241 +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020000000000000000000000000000019A +:10C3A0000101010101010101000000010101010180 +:10C3B000010101010101010101010101010101026C +:10C3C0000201020201010102010102020102020254 +:10C3D0000202010102010201010201020202020243 +:10C3E000020202020202020202020202020202022D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C490000200000000000000000000000000000199 +:10C4A000010101010101010100000001010101017F +:10C4B000010101010101010101010101010101026B +:10C4C0000202010101010101010101010201020257 +:10C4D0000201020201010101020102010102020244 +:10C4E000020202020201010102020202020202022F +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C590000200000000000000000000000000000198 +:10C5A000010101010101010100000001010101017E +:10C5B000010101010101010101010101010101026A +:10C5C0000101010101010101010101010102010259 +:10C5D0000102010101010101010101020201020246 +:10C5E0000202010101020202010201020202020230 +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C690000200000000000000000000000000000197 +:10C6A0000101010000010101000000010001010180 +:10C6B000010101010101010101010101010101016A +:10C6C0000201010101010101010101010101020257 +:10C6D0000201010101010101010101010102010247 +:10C6E0000201020202000000020102020102020233 +:10C6F000020202020202020202020202020202021A +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000200000000000000000000000000000196 +:10C7A000010101000001010000000001010101017F +:10C7B0000101010101010101010101010101010268 +:10C7C0000101010101010101010101010101010159 +:10C7D0000001010101010101010101010101020248 +:10C7E000020200000000000000020001020101023C +:10C7F0000202020202020202020202020202020219 +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202000000000000000000000000000193 +:10C8A000010101000000000000000101010101017F +:10C8B0000101010101010101010101010101010168 +:10C8C0000101010101010101010101010101010257 +:10C8D0000101010101010101010101010101010148 +:10C8E000010000000001010100000002000202023C +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202000000000000000000000000000192 +:10C9A000010101000000000001010101010101017C +:10C9B0000101010101010101010101010101010167 +:10C9C0000101010101010101010101010101010157 +:10C9D0000101010101010101010101010101010246 +:10C9E000020001010101010101000100000000023B +:10C9F000020201010101010201010202020202021E +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA9000020202000000000000000000000000018F +:10CAA000010101000000000001010101010001017C +:10CAB0000101010101010101010101010101010166 +:10CAC0000101010101010101010101010101010156 +:10CAD0000101010101010101010101010101010047 +:10CAE0000001010101010101010101000100000239 +:10CAF000010102020202020102020201020202021A +:10CB00000202020201010102020202020202020208 +:10CB10000201010101010101010101010102020201 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB9000020202000000000000000000000000018E +:10CBA000010001000000000001010101010101017B +:10CBB0000101010101010101010101010101010165 +:10CBC0000101010101010101010101010101010155 +:10CBD0000101010101010101010101010101010046 +:10CBE0000001010101010101010101010101010235 +:10CBF0000202000000000002000001020101010227 +:10CC0000020101010202020101010101020202020C +:10CC10000101010101010101010101010101010203 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC9000020202020000000000000000000000018B +:10CCA0000101010000000000010101010101010179 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000000010101010100010102000202020223 +:10CD0000010202020000000202020202010101010E +:10CD100001020202020202020202020202010102F6 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD9000020202020000000000000000000000018A +:10CDA0000101010001000000010101010101010177 +:10CDB0000101010101010101010101010101010163 +:10CDC0000101010101010101010101010101010153 +:10CDD0000101010101010101010101010101010143 +:10CDE0000101010101010101010101010101010232 +:10CDF0000001010101010101010100010000000128 +:10CE00000200000000000000000000000202020119 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202000000000000000000020185 +:10CEA0000001010101000001010101010101010175 +:10CEB0000101010101010101010101010101010162 +:10CEC0000101010101010101010101010101010152 +:10CED0000101010101010101010101010101010142 +:10CEE0000101010101010101010101010101010033 +:10CEF0000101010101010101010101010101010221 +:10CF0000000000000101010000000000000000021C +:10CF10000200000000000000000000000002020209 +:10CF200002010101010101010101010202020202EB +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020000000000000000020182 +:10CFA0000101010101010101010101010101010171 +:10CFB0000101010101010101010101010101010161 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010141 +:10CFE0000101010101010101010101010101010131 +:10CFF0000101010101010101010101010101010022 +:10D000000001010101010101010101010000000213 +:10D01000000000000000000000000000000000020E +:10D0200001010101010101010101010101010102EF +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D09000020202020202020202000000000002007C +:10D0A0000101010101010101010101010101010170 +:10D0B0000101010101010101010101010101010160 +:10D0C0000101010101010101010101010101010150 +:10D0D0000101010101010101010101010101010140 +:10D0E0000101010101010101010101010101010130 +:10D0F0000101010101010101010101010101010021 +:10D100000101010101010101010101010101010010 +:10D11000000000000000000000000000000000010E +:10D1200001020202020202020202020101010102E4 +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D17000020202020202020202020202020202028F +:10D18000020202020202020202020202020202027F +:10D190000202020202020202020202000002020174 +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101000F +:10D210000001010101010101010101010100000101 +:10D2200002020202020202020202020202020202DE +:10D2300002020102020101010101020202020202D4 +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D290000202020202020202020202020002020171 +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101000E +:10D3100001010101010101010101010101010102FC +:10D3200002010101010101010001010202020202E8 +:10D3300001010201010202020202010101010102D6 +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202016E +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010102FB +:10D4200001010101010101010101010101010101EC +:10D4300002020102020101010101020202020202D2 +:10D4400000020202020202020202020202020202BE +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202016D +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010102EA +:10D5300001010101010101010101010101010102DA +:10D5400000010101010101020202020202020202C3 +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202016C +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010102C9 +:10D6500001020202010202020202020202020201AD +:10D6600001010101010101010101010101010102A9 +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202016B +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000010101010101010101010101010101014A +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500002010101010101010101010101010102B7 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D79000020202020202020202020202020202016A +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000101010101010101010101010101010149 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010100B9 +:10D8600000000000000000000000000000000001B7 +:10D870000101010101010101010101010101010297 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020169 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010102A6 +:10D970000202020202020202020202020202020287 +:10D980000101010101010101010101010101010286 +:10D990000202020202020202020202020202020168 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010147 +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020167 +:10DAA0000101010101010101010101010101010166 +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010101010101010101010146 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010294 +:10DB80000101010101010101010101010101010284 +:10DB90000202020202020202020202020202020166 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF0000101010101010101010101010101010115 +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010283 +:10DC90000202020202020202020202020202020165 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010101010101010101010114 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010282 +:10DD90000202020202020202020202020202020164 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010281 +:10DE90000202020202020202020202020202020163 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010280 +:10DF90000202020202020202020202020202020162 +:10DFA0000101010101010101010101010101010260 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202020202020231 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020202020202020202020211 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400002020202020202020202020202020202B0 +:10E0500002020202020202020202020202020202A0 +:10E060000202020202020202020202020202020290 +:10E070000202020202020202020202020202020280 +:10E080000202020202020202020202020202020072 +:10E09000000000000000000000000000000000017F +:10E0A000010101010101010101010101010101025F +:10E0B0000202020202020202020202020202020240 +:10E0C0000202020202020202020202020202020230 +:10E0D0000202020202020202020202020202020220 +:10E0E0000202020202020202020202020202020210 +:10E0F0000202020202020202020202020202020200 +:10E1000002020202020202020202020202020202EF +:10E1100002020202020202020202020202020202DF +:10E1200002020202020202020202020202020202CF +:10E1300002020202020202020202020202020202BF +:10E1400002020202020202020202020202020202AF +:10E15000020202020202020202020202020202029F +:10E16000020202020202020202020202020202028F +:10E17000020202020202020202020202020202027F +:10E180000202020202020202020202020202020071 +:10E19000000000000000000000000000000000017E +:10E1A0000101010101010101010101010101010060 +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000024D +:10E1D000020202020202020202020202020202021F +:10E1E000020202020202020202020202020202020F +:10E1F00002020202020202020202020202020202FF +:10E2000002020202020202020202020202020202EE +:10E2100002020202020202020202020202020202DE +:10E2200002020202020202020202020202020202CE +:10E2300002020202020202020202020202020202BE +:10E2400002020202020202020202020202020202AE +:10E25000020202020202020202020202020202029E +:10E26000020202020202020202020202020202028E +:10E27000020202020202020202020202020202027E +:10E280000202020202020202020202020202020070 +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E390000000000000000000000000000000003E3F +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000015C +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000100000000000000000000002C +:10E3F000000000000000000000000000000000001D +:10E40000000000000000010000000000000000000B +:10E4100000000000000000000000000000000000FC +:10E4200000000000000001000000000000000000EB +:10E4300000000002000000000000000000000000DA +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000200000000000000000000000000009A +:10E48000000000000000000000000000000000008C +:10E49000020000000000000000000000000000007A +:10E4A0000000000000000001020202000000000065 +:10E4B0000000000000020000000000000000000159 +:10E4C0000100010001010100000000000000000146 +:10E4D000000000010000000000000000000000003B +:10E4E000000000000100000000000000000000002B +:10E4F000000000000000000000000000000000001C +:10E500000000000200000100000000000000000008 +:10E5100000000000000000000000000000000000FB +:10E5200000000000000001000000000000000000EA +:10E5300000000002000201000000000000000000D6 +:10E5400000000000000000000000000000000000CB +:10E5500000000000020201000000000000000000B6 +:10E5600000000002000000000000000000000000A9 +:10E570000002000000020000000000000000000097 +:10E580000000000000000000000000000000000289 +:10E590000202000000000000000000000000000077 +:10E5A0000000000000000002020202000000000063 +:10E5B0000000000000020000000000000000000158 +:10E5C0000101010101010101010000000100000140 +:10E5D0000000010100010100000000000000000037 +:10E5E0000000010001010100000000000000000027 +:10E5F0000000000001020100000000000000000017 +:10E600000000020202010100000000000000000002 +:10E6100000000200010101000000000000000000F5 +:10E6200000000000000001000000000000000000E9 +:10E6300000000001000201000000000000000000D6 +:10E6400000000000020201000000000000000000C5 +:10E6500000000000020201000000000000000000B5 +:10E6600000000002020201000000000000000000A3 +:10E670000002000000020000000000000000000096 +:10E680000000000002000100000000000000000285 +:10E69000020202000202010000000000000000006F +:10E6A0000000000000000002020202020000000060 +:10E6B0000000020002020000000000000100000152 +:10E6C000010101010101010101000000010000013F +:10E6D0000001010100010100000000000000000035 +:10E6E0000000010001010100000000000001010024 +:10E6F0000000000001020100000000000000000016 +:10E700000000020202010100000000000000000001 +:10E7100000000200010101000000000000010000F3 +:10E7200000000000000001000000000000000000E8 +:10E7300000000001000101000000000000000000D6 +:10E7400000000000020201000000000000000000C4 +:10E7500000000000010101000000000000000002B4 +:10E7600000000001020201000000000000000000A3 +:10E770000001000000020100000000000000000293 +:10E780000000000002000100000000000000000284 +:10E79000010202000202010000000000000000006F +:10E7A000000000000000000202020202000000005F +:10E7B0000000020002020000000000000100010150 +:10E7C000010101010101010101010000010000013D +:10E7D0000001010101010100000100000000000032 +:10E7E0000000010001010100000000000001010023 +:10E7F0000000000001010100000000000000000016 +:10E800000000020102010100000000000000000001 +:10E8100000000200010101000000000000010000F2 +:10E8200000000000000001000000000000000000E7 +:10E8300000000001000101000000000000000000D5 +:10E8400000000000010101000000000000000000C5 +:10E8500000000000010101000000000000000002B3 +:10E8600000000001010101000000000000000000A4 +:10E870000001000000010100000000000000000293 +:10E880000000000001000100000000000000000185 +:10E890000101010001020100000000000000000071 +:10E8A000000000000000000202020202000000005E +:10E8B0000200020202020000010100000100010149 +:10E8C000010101010101010101010000010000013C +:10E8D000000101010101010000010100000000012F +:10E8E0000000010001010100000000010001010021 +:10E8F0000001000001010100000000000000000014 +:10E900000000010101010100000000000000000002 +:10E9100000000100010101000000000000010000F2 +:10E9200000000000000001000000000000000000E6 +:10E9300000000001000101000000000000000000D4 +:10E9400000000000010101000000000000000000C4 +:10E9500000000000010101000000000000000002B2 +:10E9600000000001010101000000000000000000A3 +:10E970000001000000010100000000000000000292 +:10E980000000000001000100000000000000020182 +:10E990000101010001010100020202020000000069 +:10E9A000000000000000000202020202000000005D +:10E9B0000200020202020000010101010101010244 +:10E9C000010101010101010101010000010000013B +:10E9D000000101010101010000010100000000012E +:10E9E000000001000101010000000001010101001F +:10E9F0000101000001010100000000000000000012 +:10EA00000000010101010100000000000000000001 +:10EA100000000100010101010000000000010000F0 +:10EA200000000000000001000000000000000000E5 +:10EA300000000001000101000000000000000000D3 +:10EA400000000000010101000000000000000000C3 +:10EA500000000000010101000000000000000001B2 +:10EA600000000001010101000000000000000000A2 +:10EA70000001000000010100000000000000000192 +:10EA80000000000001000100010000000000020180 +:10EA90000101010001010100020202020202000064 +:10EAA0000000000000000002020202020002000258 +:10EAB0000200020202020000010101010101010243 +:10EAC000010101010101010101010000010000013A +:10EAD000000101010101010000010100000000012D +:10EAE000000001010101010000000001010101021B +:10EAF0000101000001010100000000000001000010 +:10EB00000000010101010100000000000000000000 +:10EB100000000100010101010000000000010002ED +:10EB200000000001000001000000000000000000E3 +:10EB300000000001000101000000000000000000D2 +:10EB400000000000010101000000000000000000C2 +:10EB500000000000010101000000000000000001B1 +:10EB600000000001010101000000000000000000A1 +:10EB70000001000000010100000000000000000191 +:10EB8000000000000100010001000000000202017D +:10EB90000101010001010100010101010101010167 +:10EBA0000101010101010102020202020002000250 +:10EBB0000200020202020000010101010101010242 +:10EBC0000201010101010101020100000100000137 +:10EBD0000101010101010100010101000100000129 +:10EBE0000100010101010101000000010101010119 +:10EBF000010100000101010000000000000100000F +:10EC000000000101010101000000000000000000FF +:10EC100000000100010101010000000000010001ED +:10EC200000000001000001000000000000000002E0 +:10EC300000000001000101000000000000000000D1 +:10EC400000000000010101000000000000000000C1 +:10EC500000000000010101000000000000000001B0 +:10EC600000000001010101000000000000000000A0 +:10EC70000001000000010100000000000000000190 +:10EC8000000000000100010001000000000201017D +:10EC90000101010001010100010101010101010166 +:10ECA000010101010101010202020202020200024D +:10ECB000020002020202000101010101020101023F +:10ECC0000201010101010102020100000100000135 +:10ECD0000101010101010100010101000100010127 +:10ECE0000101010101010101000000010101010117 +:10ECF000010100000101010000000000000100000E +:10ED000000000101010101000000000000000000FE +:10ED100000000100010101010000000000010001EC +:10ED200000010001000001010000000000000001DE +:10ED300002000001000101000000000000000000CE +:10ED400000000000010101000000000000000000C0 +:10ED500000000000010101000000000000000001AF +:10ED6000000000010101010000000000000000009F +:10ED7000000100000001010000000000000200018D +:10ED8000000000000100010001000000000201017C +:10ED90000101010001010100000000010101010168 +:10EDA000010101010101010202020202020200024C +:10EDB000020002020202000102020201020201023A +:10EDC0000202010101010102020200000100000132 +:10EDD0000101010101010100010101000100010126 +:10EDE0000101010101010101010000010101010115 +:10EDF000010100000101010000000001010100000B +:10EE000000000101010101000000000000000000FD +:10EE100000000100010101010001000000010001EA +:10EE200002010101000001010000010000020001D7 +:10EE300002000001000101000000000000020000CB +:10EE400000000000010101000000000000000000BF +:10EE500000000000010101000000000000000001AE +:10EE6000000000010101010000000000000000009E +:10EE7000000100000001010000000000000200018C +:10EE8000000000000100010001000000000101017C +:10EE90000101010001010100000000010101010167 +:10EEA000010101010101010202020202020200024B +:10EEB0000202020202020001020202010202020236 +:10EEC000020202010101010202020000020101022C +:10EED0000101010101010100010202000100010123 +:10EEE0000101010101010101010000010101010114 +:10EEF0000101000001010100010000010101020106 +:10EF000000000101010101000000000000000000FC +:10EF100000000100010101010001010100010201E5 +:10EF200002010101000001010001010101010001D4 +:10EF300002000001000101000000000100020000C9 +:10EF400000000002010101000000000000000000BC +:10EF500000000000010101000000000000000001AD +:10EF6000000000010101010000000000000000009D +:10EF7000000100000001010000000000000200018B +:10EF8000000000000100010001000001000101017A +:10EF90000101010001010100000000010101010166 +:10EFA000010101010101010202020202020200024A +:10EFB0000202020202020001020202020202020234 +:10EFC000020202020101010202020000020101022A +:10EFD0000101010101010100010202000100010122 +:10EFE0000101010101010101010000010102010112 +:10EFF0000101000001010100010100010101020104 +:10F0000001000101010101000000000000000000FA +:10F0100000000100010101010001010100010201E4 +:10F0200002010101020201010001010101010001CF +:10F0300001020001000101000000000100020000C7 +:10F0400000000202010101000000000000000000B9 +:10F0500000000000010101000000000000000001AC +:10F06000000000010101010000000000000000009C +:10F07000000100000001010000000000000100018B +:10F080000000000001000100010100010001010178 +:10F09000010101000101010000000000000000006A +:10F0A000000000000001010202020202020202024C +:10F0B0000202010202020001020202020202020234 +:10F0C0000202020201010102020201010201010227 +:10F0D000010101010101010002020201010101011E +:10F0E000010101010101010202000102010202010C +:10F0F0000101000001010100010100010101020103 +:10F1000001010101010101000000000000020000F6 +:10F1100000000100010101020001010100010201E2 +:10F1200001010101020201010101010101010001CE +:10F1300001020101020101000001010100010201BF +:10F1400000020202010101000000000000000000B6 +:10F1500000000000010101000000000000000001AB +:10F16000000000010101010000000000000000009B +:10F17000000100000001010000000000000100018A +:10F180000000000001000100010100010001010177 +:10F190000101010001010100000000000000000069 +:10F1A000000000000001010202020202020202024B +:10F1B0000202010202020001020202020202020233 +:10F1C0000202020201010102020201010201010226 +:10F1D000010201020101010002020201010101011B +:10F1E000010101010101010202010102010202010A +:10F1F0000101000001010100010100010101010103 +:10F2000001010101010101000001010000020000F3 +:10F2100000000100010101020101010101010101E0 +:10F2200001010101010101010101010101010101CE +:10F2300001020101020101000001010100010101BF +:10F2400001020201010101000000000000000000B5 +:10F2500000020000010101000000000000000001A8 +:10F26000000000010101010000000000000000009A +:10F270000001000000010100000000000001000189 +:10F280000000000001000100010100010101010175 +:10F290000101010001010100000000000000000068 +:10F2A0000001010101000102020202020202020247 +:10F2B0000102010102020002020202020202020233 +:10F2C0000202020202010102020201010201010224 +:10F2D0000102020201010100020202010101010218 +:10F2E0000101020102010102020101020202020106 +:10F2F0000101000001010101020100010101010100 +:10F3000001010101010101000001010100010001F1 +:10F3100000000100010101020101010101010101DF +:10F3200001010101010101020101010101010101CC +:10F3300001010101010101000001010100010101C0 +:10F3400001020101010101000000000000000000B5 +:10F3500002020200010101000000000000000001A3 +:10F360000000000101010100000000000000000099 +:10F370000001000002010100000000000001000186 +:10F380000000000001000100010101010101010173 +:10F390000101010001010100000000000000000166 +:10F3A0000101010101000102020202020202020245 +:10F3B0000102010101010002020202020202020234 +:10F3C0000202020202020102020201010201010222 +:10F3D0000102020201010101020202010201010215 +:10F3E0000101020102010102020101020202020105 +:10F3F00001010200010101010201000101010101FD +:10F4000001010101010101000001010101010001EF +:10F4100002000100010101020101010101010101DC +:10F4200001010101010101020101010101010101CB +:10F4300001010101010101000001010100010101BF +:10F4400001010101010101010001000000010002B0 +:10F4500002020200010101000000000000000001A2 +:10F460000200020101010100000000000000000094 +:10F470000001000202010100000000000001000183 +:10F480000000000001000100010101010101010172 +:10F490000101010001010100000000000000000165 +:10F4A0000101010101000102020202020202020145 +:10F4B0000102020101010002020202020202020232 +:10F4C000020202020202010202020201020201021F +:10F4D0000102020201020101020202010201020212 +:10F4E0000101020102020102020202020202020101 +:10F4F00002020200020101010202000101020101F7 +:10F5000001010101010101000001010101010001EE +:10F5100002000100010101020102010101020101D9 +:10F5200001010101010101020201020101010101C8 +:10F5300001010101010101000001010100010101BE +:10F5400001010101010101010001000001010002AE +:10F5500002010200010101000000000000000001A2 +:10F560000202020101010100000000000000000091 +:10F570000001020202010100000000000001000180 +:10F58000000200020100010001010101010101016D +:10F590000101010201010100000000000000000063 +:10F5A0000000000100000102020202020202020148 +:10F5B0000101020201010002020202020202020231 +:10F5C000020202020202010202020201020202021D +:10F5D0000202020201020101020202010201020210 +:10F5E0000101020102020102020202020202020100 +:10F5F00002020100020101020202010201020101F4 +:10F6000001010101010101010101010101010001EB +:10F6100001000100010101020202020101020101D7 +:10F6200001010101010101020202020101010101C6 +:10F6300001010101010101000101010100010101BC +:10F6400001010101010101010001000001010202AB +:10F6500001010102010101000000000100000001A0 +:10F660000202020101010100000000000000000090 +:10F670000001020201010100000000000001000180 +:10F680000202020201020101020101010101010164 +:10F690000101010201010100000000000000000062 +:10F6A000000000000000010202020201020102014A +:10F6B000020102020101000202020202020202022F +:10F6C000020202020202010202020202020202021B +:10F6D000020202020202010202020202020202020B +:10F6E00002020202020201020202020202020202FB +:10F6F00002020100020102020202010202020101F1 +:10F7000001010101010201010101010101010101E8 +:10F7100001000100010101020202020101020101D6 +:10F7200001010101010101020202020101010101C5 +:10F7300001010101010101000101010100010101BB +:10F7400001010101010101010001010001010201AA +:10F75000010101020101010100000001000000019E +:10F760000102010101010100000000000000000091 +:10F77000020102010101010000000000000100017E +:10F780000202020201020101020101010101010163 +:10F790000101010201010100000000000000000061 +:10F7A000000000000000010202020201010102014A +:10F7B000020102020101000202020202020202022E +:10F7C000020202020202010202020202020202021A +:10F7D000020202020202010202020202020202020A +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020100020202020202010202020101EF +:10F8000001010101010202010102020101010101E4 +:10F8100001000100010101020202020201020101D4 +:10F8200001010101010101020202020201010101C3 +:10F8300001010101010101000102020100010101B8 +:10F8400001010101010101020001010001010201A8 +:10F85000010101010101010100000001000000019E +:10F86000010101010101010000000000000000028F +:10F87000020101010101010100000000000100017D +:10F880000201020101020101020101010101010164 +:10F890000101010101010100000000000000000061 +:10F8A000000000000000000202020101010101024B +:10F8B000020101010101000202020202020202022F +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020101020202020202020202020101EC +:10F9000001010101010202020202020101010101E1 +:10F9100001020102010101020202020201020101CF +:10F9200001010101010101020202020202010101C1 +:10F9300001010101010101000202020200010101B5 +:10F9400001010101010101020101010001010101A7 +:10F950000101010101010101000001010002020198 +:10F96000010101010101010100000000000000028D +:10F97000020101010101010100000000000100017C +:10F980000101010101010101020101010101010166 +:10F990000101010101010100000000000000000060 +:10F9A000000000000000000202020101010101024A +:10F9B000020201010101000202020202020202022D +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020101020202020202020202020102EA +:10FA000001010202010202020202020101010101DE +:10FA100001010102020201020202020201020101CD +:10FA200001010101010102020202020202020101BE +:10FA300001010102010102000202020200010101B2 +:10FA400001010101010101020102010001010101A5 +:10FA50000101010101010102010001010002020195 +:10FA60000101010101010101010000000000020289 +:10FA7000010101010101010100000000000100017C +:10FA80000101010101010101020101010101010165 +:10FA9000010101010101010000000000000000005F +:10FAA0000000000000000002020201020102010247 +:10FAB000010201010101000202020202020202022D +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020101020202020202020202020102E9 +:10FB000002010202020202020202020201010101DA +:10FB100001010102020201020202020202020102CA +:10FB200001010101010102020202020202020102BC +:10FB300001010102010202000202020200010101B0 +:10FB400001010101010101020202010001010101A3 +:10FB50000101010101010102010001010002020194 +:10FB60000101010101010101010000000000020189 +:10FB70000101010101010101000001000001020178 +:10FB80000101010101010101020201010101010163 +:10FB9000010101010101010000000000000000005E +:10FBA0000000000000000002020101020202010246 +:10FBB000010201010101000202020202020202022C +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020101020202020202020202020102E8 +:10FC000002020202020202020202020201010101D8 +:10FC100001010101020202020202020202020102C9 +:10FC200001020102010102020202020202020202B8 +:10FC300001010102010202020202020201010101AC +:10FC400001010101010102020202020001010101A0 +:10FC50000101010101010202020001010001010193 +:10FC60000101010101010102010000000002020185 +:10FC70000101010101010102000001000001020176 +:10FC80000101010101010102020201010101010161 +:10FC9000010101010101010000000000000000005D +:10FCA0000000000000000002020102020202020144 +:10FCB000010201010101000202020202020202012C +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020101020202020202020202020202E6 +:10FD000002020202020202020202020202010101D6 +:10FD100001010201020202020202020202020102C7 +:10FD200001020202010102020202020202020202B6 +:10FD300001010102010202020202020201010101AB +:10FD4000010101010202020202020200020101019C +:10FD5000010101010202020202000101000101028F +:10FD60000101010201010202020000000002010182 +:10FD70000101010101010102000001000001020175 +:10FD8000010101010101010202020202010101015E +:10FD9000010101010101010000000000000000005C +:10FDA0000000000000000002010102020202020144 +:10FDB000010101010101000202020202020202022B +:10FDC0000102020202020202020202020202020214 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020101020202020202020202020202E5 +:10FE000002020202020202020202020202020101D4 +:10FE100001010201020202020202020202020102C6 +:10FE200001020202010102020202020202020202B5 +:10FE300001010202010202020202020201020202A6 +:10FE40000101010102020202020202010202010199 +:10FE5000010101010202020202010202000101028B +:10FE6000010101020202020202000000000201017F +:10FE70000102010101010102000001000001010174 +:10FE8000010101010101010202020202010101015D +:10FE9000010101010101010000000000000000005B +:10FEA0000000000000000002010102010201020145 +:10FEB000010101010101000202020202020202012B +:10FEC0000201020202020202020202020202020213 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020102D2 +:10FF100001010201020202020202020202020202C4 +:10FF200001020202010102020202020202020202B4 +:10FF300002010202010202020202020201020202A4 +:10FF40000201010102020202020202010202010197 +:10FF5000010101010202020202010202000101028A +:10FF6000010101020202020202000000000101017F +:10FF70000102010101010202000001000001010271 +:10FF8000010101010101020202020202010101025A +:10FF90000201010101010100000000000000000059 +:10FFA0000000000000000002010202010101020144 +:10FFB000010101010101000202020202020102012B +:10FFC0000102010102020202020202020202020214 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:020000020000FC +:020000040010EA +:1000000002020202020202020202020202020202D0 +:1000100001010201020202020202020202020202C3 +:1000200002020202010102020202020202020202B2 +:1000300002010202010202020202020201020202A3 +:100040000201010102020202020202010202010196 +:100050000101010102020202020202020001010288 +:10006000010101020202020202000000000101017E +:10007000010201010102020200000200000201026D +:100080000101010102010202020202020202020255 +:100090000202020101010200000000000000000055 +:1000A0000000000000000002010201010101010145 +:1000B000010101010101000202020202010201012B +:1000C0000101020202020202020202020202020212 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100001010201020202020202020202020202C2 +:1001200002020202010102020202020202020202B1 +:1001300002020202010202020202020201020202A1 +:100140000201010102020202020202010202010195 +:100150000101010102020202020202020001010287 +:10016000010101020202020202000000000101017D +:10017000010201010102020200000200000201026C +:100180000101010102010202020202020202020254 +:100190000202020102010200000000000000000053 +:1001A0000000000000000002020201010101010143 +:1001B0000101010101010002020202020201020129 +:1001C0000101010102020202020202020202020213 +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020202DF +:1002000002020202020202020202020202020202CE +:1002100001010201020202020202020202020202C1 +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:100240000201010102020202020202020202010193 +:100250000101010102020202020202020101010285 +:10026000010101020202020202000000000101017C +:100270000102010101020202020002000002010269 +:100280000101010102010202020202020202020253 +:100290000202020102020200000000000000000051 +:1002A0000000000000000002020201010101010142 +:1002B000010101010101000202020202010101012A +:1002C0000101010101020202020202020202020114 +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002010201020202020202020202020202BF +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020201018F +:100350000101010102020202020202020101010284 +:100360000101010202020202020100000101010179 +:100370000102010101020202020002010002010267 +:100380000101010102010202020202020202020252 +:100390000202020102020200000000000000000050 +:1003A0000000000000000001020101010101010143 +:1003B000010101010101000202020101010101012B +:1003C0000101010102010202020202020202020212 +:1003D00002010201020202020202020202020202FF +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002010201020202020202020202020202BE +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:100450000202010102020202020202020101010281 +:100460000101010202020202020200010101010176 +:100470000102010101020202020102010102010264 +:100480000101010102010202020202020202020251 +:10049000020202010202020000000000000000004F +:1004A0000000000000000001020101010101010142 +:1004B0000101010101010002020102020101010129 +:1004C0000101010101020202020202020102020113 +:1004D00002020102020202020202020202020201FE +:1004E00002020102010202020202020202010102F0 +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020201020202020202020202020202BC +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202010202020202020202010201027E +:100560000201010202020202020200010101010174 +:100570000102010101020202020202010102010262 +:100580000101010102010202020202020202020250 +:10059000020202010202020000000000000000004E +:1005A0000000000000000001010101010101010142 +:1005B000010101010001000202020101010101012A +:1005C0000101010101010202020202020201010114 +:1005D0000101020102010202020202020202010200 +:1005E00002010201020102020202020202010102F0 +:1005F00001010202010202020202020202020202DE +:1006000002020202020202020202020202020202CA +:1006100002020201020202020202020202020202BB +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020201010101016F +:100670000102010101020202020202010102010261 +:10068000010101010201020202020202020202024F +:10069000020202010202020000000000000000004D +:1006A0000000000000000001010101010101010141 +:1006B000010101010000010201010101010101012B +:1006C0000101010101010202020102020102020113 +:1006D0000201010101020202020201020101020102 +:1006E00001020102010202020202020101020201F0 +:1006F00001010201010101020202020202020202E0 +:1007000002020202020202020202020202020202C9 +:1007100002020201020202020202020202020202BA +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:10076000020202020202020202020202010101016D +:10077000010201010102020202020202010201025F +:10078000010101010201020202020202020202024E +:10079000020202010202020202020202020202023A +:1007A0000202020202020201010101010101010132 +:1007B0000101010100000102020101010101010129 +:1007C0000101010101010102010202020101010115 +:1007D0000101010102010202020202020202010100 +:1007E00002010101010101020202020101020201F2 +:1007F00002020101020101020202020202020202DD +:1008000002020202020202020202020202020202C8 +:1008100002020201020202020202020202020202B9 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:10087000020202020202020202020202010201025A +:10088000020201010201020202020202020202024B +:100890000202020102020202020202020202020239 +:1008A0000202020202020201010101010101010131 +:1008B000010100000000010201010101010101012B +:1008C0000101010101010202020101010101010115 +:1008D0000101010101010102020101010101010106 +:1008E00001010101010102020101020201000002F5 +:1008F00002020102020202020202020202020202D9 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202010202020202020202020248 +:100990000202020102020202020202020202020238 +:1009A0000202020202020201010101010101010130 +:1009B000000100000000010201010101010101012B +:1009C0000101010101010101010102020101010115 +:1009D0000101010101010202010101020101010104 +:1009E00001010101010101020101010202000002F5 +:1009F00000000202000202020202020202010202DE +:100A000002020202020102020202020202020202C7 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020201010101010101010030 +:100AB000000100000000010201010101010101012A +:100AC0000101010101010102010101010101010115 +:100AD0000101010101010102020101010101010104 +:100AE00001010101010101020202010002010100F4 +:100AF00000000200000000020202020201010201E5 +:100B000001010101010101020202020202020202CC +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020201010101000000010032 +:100BB000000000000000010101010101010101012B +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010102010101010101010104 +:100BE00001010101010101020202020002010100F2 +:100BF00001010000010000020201020101020101E5 +:100C000001010101010201020202020202020202CA +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020201010101000000000032 +:100CB0000000000000010101010101010101010129 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101000000020101010101F6 +:100CF00001010001010101020101010102020102E1 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020201010100000000000032 +:100DB0000000000001010101010101010101010127 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010102010101010101010102 +:100DE00001010101010101000000010101010101F6 +:100DF00001010101010101020102010202000202DE +:100E000002020202020002020202020202020202C4 +:100E100002020202020202020202020202010202B3 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020201010100000000000031 +:100EB0000000000001010101010101010101010126 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101020202020200010200DE +:100F000000000000000100020202020202020202CE +:100F100002020202020202020201010101010201B7 +:100F200002010101020201020202010201010101AA +:100F30000202010102010102020202020202020295 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020201010100000000000030 +:100FB0000000000101010101010101010101010124 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101000200020101010001E2 +:1010000001010101010101020202000202020202C9 +:1010100002020202010102010101010101020101BA +:1010200001010101010101020102020102020202A9 +:101030000101020201020202020202020202020293 +:101040000202020202020202020202020102020281 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202000201010100000000000031 +:1010B0000000010101010101010101010101010122 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101000101010101010101E1 +:1011000001010101010101020201010101010101CD +:1011100002020102010101010102020202020102B6 +:1011200001020202010102020201000200000000AD +:101130000202000002000002020202020202020297 +:101140000202020202020202020202020102020280 +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A0000202020200000201010100000000000131 +:1011B0000100010101010101010101010101010120 +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101020101010101010101CD +:1012100001010102010101020202020202010202B5 +:1012200002020202020202000002000000000000AE +:1012300000000000000000020202010102020101A0 +:101240000102020201010102020202020102020283 +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020000020101010101000100012D +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101020201010101010201BA +:1013200002010101020201000000000000000000B3 +:10133000000000000000000201010202010102029F +:101340000201010102020202020202020201020281 +:101350000202020201010102020202020202020270 +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020200000000020101010101010101012E +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101000001010101010101AE +:10143000000001010001010102020000020200009F +:10144000000202020000000201010101020201018A +:101450000101010102020202020202020202020171 +:101460000202020101010102020202020202020260 +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A0000000000000000001010101010101010133 +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010200010101000101019C +:101540000100000001010101020202020200020288 +:101550000202020200000002010102010101010277 +:10156000010101020202020202020202020202025E +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020200002F +:1015A0000000000000000001010101010101010132 +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010001010101010101019B +:10164000010101010101010200010100000100008E +:10165000000000000101010102020002020202007A +:101660000202020000000002020202020202020262 +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:101690000202020202020202020202020200000030 +:1016A0000000000000000001010101010101010131 +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:10175000010101010101010200000101000000017D +:101760000000000101010102020202020202020263 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020000000031 +:1017A0000000000000000001010101010101010130 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010102000202020202020261 +:10187000020102020201010202020002020202024D +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020000000030 +:1018A000000000000000000101010101010101012F +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010102020200020201020152 +:101980000202020201020102020202020202020239 +:101990000202020202020202020202000000000031 +:1019A000000000000000000101010101010101012E +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010102010101010101010145 +:101A90000101010201010102020200000000000038 +:101AA000000000000000000101010101010101012D +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B9000010101010101010202000000000000003A +:101BA000000000000000000101010101010101012C +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010102020000000000000039 +:101CA000000000000000000101010101010101012B +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010102020000000000000038 +:101DA000000000000000000101010101010101012A +:101DB000010101010101010202020202020202020A +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020202D3 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020000000000000030 +:101EA0000000000000000001010101010101010129 +:101EB000010101010101010000000000000000001B +:101EC0000000000000000002020202020202020200 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020202D2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202000000000000000031 +:101FA0000000000000000001010101010101010128 +:101FB000010101010101010000000000000000001A +:101FC0000000000000000000000000000000000011 +:101FD00000000000000000020202020202020202EF +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020200000000000000000062 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:10209000000000000000000200000000000000003E +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000000000000000010 +:1020D0000000000000000000000000000000000000 +:1020E00000000000000000000000000000000000F0 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000003B0000000000000000F4 +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200001020000000000000000000000000000AB +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000010000000000000000000000000000007D +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A0000202000202020202020202020202000212 +:1022B0000002020000000000000000000002000018 +:1022C000000000020000000000000000000200000A +:1022D00000000000000000000000000000020000FC +:1022E00000020000000000000000000000000200EA +:1022F00000020000000000000000000000000200DA +:1023000000000102000000000000000200020000C6 +:1023100002020002010002000000000000000200B2 +:1023200002020000000200000000000200000000A5 +:102330000200010000000000000000000000020098 +:10234000000000000000000000000000000000008D +:102350000200020200000200000000000200020071 +:102360000201020000000000000000000000000068 +:102370000200000000000000000000000000020059 +:102380000000020000000000000000020002000047 +:10239000000200000002000200020200020002002F +:1023A000010101010101010101010101010101021C +:1023B0000102020000000000000000000002000016 +:1023C0000000000200000000000202020002020001 +:1023D00001020000000000000000000000020200F6 +:1023E00000020000000000000000000000020200E7 +:1023F00000020000000000000200000000020200D5 +:1024000000010202000000000000000200020200C1 +:1024100002020202020002000200000000020200AA +:10242000020200020002020200000002020002009A +:102430000200020000000000000000000002020094 +:10244000000000000000000000000000000000018B +:102450000200020201020200000002000202020069 +:102460000202020000010000000000000200000063 +:102470000202000002000200020000000000020050 +:10248000000102000000000200000002020202003F +:102490000002020202020202020202020202020020 +:1024A000010101010101010101010101010101021B +:1024B0000102020000000000000000000002000015 +:1024C0000000000200000000000202020002020000 +:1024D00001020000000000000000000000020200F5 +:1024E00001020000000000000000000000020201E4 +:1024F00000020000000000000200000000020202D2 +:1025000000020202020100020000000200020200BA +:1025100002020202020002000200000000020200A9 +:102520000202010200020202000000020202020096 +:102530000200020000000000000000000002020093 +:102540000000000000000000000000000000000289 +:102550000201020202020202000202000202020161 +:102560000202020001020000000000000200000060 +:102570000202000002020202020202000000020047 +:102580000002020202000202000000020202020235 +:10259000000202020202020202020202020202001F +:1025A000010101000101010101010101010101021B +:1025B0000102020000000000000000000002000014 +:1025C00000000002000000000002020200020200FF +:1025D00001020000000000000000000000020200F4 +:1025E00001020000000000000000000000020201E3 +:1025F00000020100000000000200000000020202D0 +:1026000002020202020202020000000200020200B4 +:1026100002020202020002000200000002020200A6 +:102620000202010201020202020000020202020290 +:102630000201020201020000020000000202020088 +:102640000000000000000000000000000000000288 +:10265000020202020202020202020200020202025C +:10266000020202000202000000000000020002005C +:102670000202020102020202020202020000020041 +:10268000020202020202020200020202020202022C +:10269000000202020202020202020202020202001E +:1026A000010100000000010101010101010101021D +:1026B0000102020000000000000200000002000011 +:1026C00000000002000000000002020200020200FE +:1026D00002020000000000000000000000020201F1 +:1026E00002020000000000000000000002020201DF +:1026F00001020200000100000200000000020202CC +:1027000002020202020202020000000202020202AF +:1027100002020202020002000200000002020202A3 +:10272000020202020202020202000002020202028D +:102730000201020202020002020000000202020084 +:102740000000000000000000000000000000000287 +:10275000020202020202020202020200020202025B +:102760000202020202020200020000000202020251 +:102770000202020102020202020202020000020040 +:102780000202020202020202020202020202020229 +:10279000000202020202020202020202020202001D +:1027A000010000000000010101010101010101021D +:1027B000020202000000000000020000000200000F +:1027C00000000002000000000002020200020200FD +:1027D00002020000000000000000000002020201EE +:1027E00002020000000000000000000002020202DD +:1027F00002020200010100000200000000020202C9 +:1028000002020202020202020000000202020202AE +:1028100002020202020002020200000002020202A0 +:10282000020202020202020202000002020202028C +:102830000202020202020202020000000202020080 +:102840000000000000000000000000000000000286 +:10285000020202020202020202020200020202025A +:10286000020202020202020202020000020202024C +:10287000020202020202020202020202000002023C +:102880000202020202020202020202020202020228 +:10289000000202020202020202020202020201001D +:1028A0000000000000000000000000000000010225 +:1028B0000202020200000000020200000202000008 +:1028C00000000002000000000002020200020200FC +:1028D00002020001000000000000000002020202EB +:1028E00002020000000000000000000002020202DC +:1028F00002020200010100000200000002020202C6 +:1029000002020202020202020000000202020202AD +:10291000020202020201020202000000020202029E +:10292000020202020202020202000002020202028B +:10293000020202020202020202000200020202007D +:102940000000000000000000000000000000000285 +:102950000202020202020202020202000202020259 +:102960000202020202020202020200020202020249 +:102970000202020202020202020202020200020239 +:102980000202020202020202020202020202020227 +:10299000020202020202020202020202010101001C +:1029A0000000000000000000000000000000010224 +:1029B0000202020200000000020200000202000007 +:1029C00000000002000100000002020200020200FA +:1029D00002020001000000000000000002020202EA +:1029E00002020100010000000000000002020202D9 +:1029F00002020201010200000200000002020202C3 +:102A000002020202020202020000000202020202AC +:102A1000020202020202020202000000020202029C +:102A20000202020202020202020200020202020288 +:102A30000202020202020202020202020202020078 +:102A40000000000000000000000000000000000284 +:102A50000202020202020202020202000202020258 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A9000020202020202020202020102010101001C +:102AA0000000000000000000000000000000010223 +:102AB0000202020200000002020200000202000004 +:102AC00000000002010100000002020200020200F8 +:102AD00002020001010000000000000002020202E8 +:102AE00002020100010100000000000002020202D7 +:102AF00002020201020200000200000002020202C1 +:102B000002020202020202020000000202020202AB +:102B10000202020202020202020200020202020297 +:102B20000202020202020202020200020202020287 +:102B30000202020202020202020202020202020275 +:102B4000020201000000000000000000000000027E +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B9000020202020202020202010101010101001D +:102BA0000000000000000000000000000000010222 +:102BB0000202020200000002020200000202000003 +:102BC00000000002010100000002020200020200F7 +:102BD00002020002010000000000000002020202E6 +:102BE00002020101010100000000000002020202D5 +:102BF00002020202020200000200000002020202BF +:102C000002020202020202020000000202020202AA +:102C10000202020202020202020200020202020296 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020002000000000000000000020278 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000201010202020201010101010101010020 +:102CA0000000000000000000000000000000010221 +:102CB00002020202000202020202000002020000FE +:102CC00000000002010200000002020200020200F5 +:102CD00002020102010000000000000002020202E4 +:102CE00002020201020200000000000002020202D1 +:102CF00002020202020200000200000002020202BE +:102D000002020202020202020200000202020202A7 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020002000200020000000002020271 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202010234 +:102D80000202020202020202020202020201010225 +:102D90000201010201010201010101010101010021 +:102DA0000000000000000000000000000000010220 +:102DB00002020202000202020202000002020000FD +:102DC00000000002020200000002020202020202EF +:102DD00002020102020000000000000002020202E2 +:102DE00002020202020200000000000002020202CF +:102DF00002020202020200000200000002020202BD +:102E000002020202020202020202000202020202A4 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020102020202020200000002020269 +:102E50000202020202020202020202020202010253 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202010233 +:102E80000202020202020202020202020101010225 +:102E90000101010101010101010101010101010023 +:102EA000000000000000000000000000000001021F +:102EB00002020202020202020201020202010000F8 +:102EC00000000002020200000002020202020202EE +:102ED00002020102020000000000000002020202E1 +:102EE00002020202020200000000000002020202CE +:102EF00002020202020200000200000002020202BC +:102F000002020202020202020202000202020202A3 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202010272 +:102F40000202020202020202020200000202020265 +:102F50000202020202020202020202020101010254 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202010232 +:102F80000202020202020202020202010101010225 +:102F90000101010101010101010101010101010022 +:102FA000000000000000000000000000000001021E +:102FB00002020202020202020201020202010000F7 +:102FC00000010002020200000002020202020202EC +:102FD00002020202020000000000000002020202DF +:102FE00002020202020200000000000002020202CD +:102FF00002020202020200000200000002020202BB +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202010291 +:103020000202020202020202020202020202010281 +:103030000202020202020202020202020201010272 +:103040000202020202020202020202000202020262 +:103050000202020202020202020202020101010253 +:103060000202020202020202020202020102010242 +:103070000202020202020202020202020202010231 +:103080000202020202020202020202010101010224 +:103090000101010101010101010101010101010021 +:1030A000000000000000000000000000000000021E +:1030B00002020202020202020201020202010000F6 +:1030C00000020002020202000002020202020202E8 +:1030D00002020202020000000000000002020202DE +:1030E00002020202020200000002000002020202CA +:1030F00002020202020200020202000002020102B7 +:1031000002020202020202020202020202010102A1 +:103110000202020202020202020202020201010291 +:103120000202020202020202020202020101010282 +:103130000202020202020202020202020201010271 +:10314000020202020202020202020202020202025F +:103150000202020202020202020202020101010252 +:103160000202020202020202020202020101010242 +:103170000202020202020202020202020202010230 +:103180000202020202020202020202010101010223 +:103190000101010101010101010101010101010020 +:1031A000000000000000000000000000000000021D +:1031B00002020202020202020101020202010000F6 +:1031C00000020002020202000002020202020202E7 +:1031D00002020202020000000002000002020202DB +:1031E00002020202020202000202000002020102C6 +:1031F00002020202020202020202000202010102B3 +:1032000002020202020202020202020202010102A0 +:103210000202020202020202020202020201010290 +:103220000202020202020202020202010101010282 +:103230000202020202020202020202020101010271 +:10324000020202020202020202020202020202025E +:103250000202020202020202020201020101010252 +:103260000202020202020202020202020101010241 +:103270000202020202020202020201010101010233 +:103280000202020202020202020201010101010124 +:10329000010101010101010101010101010101001F +:1032A000000000000000000000000000000000021C +:1032B00002020202020202020101020201010002F4 +:1032C00000020002020202000002020202020202E6 +:1032D00002020202020000000202000002010102DA +:1032E00002020202020202020202000002010102C4 +:1032F00002020202020202020202020202010102B0 +:1033000002020202020202020202020102010102A0 +:103310000202020202020202020202020101010290 +:103320000202020202020202020202010101010281 +:103330000202020202020202020202020101010270 +:10334000020202020202020202020202020202025D +:103350000202020202020202020201020101010251 +:103360000202020202020202020202020101010240 +:103370000202020202020202010101010101010234 +:103380000202020202020201020101010101010125 +:10339000010101010101010101010101010101001E +:1033A000000000000000000000000000000000021B +:1033B00002020202020202010101020201010002F4 +:1033C00001020002020202000002020202010102E6 +:1033D00002020202020000020202000002010102D7 +:1033E00002020202020202020202000002010102C3 +:1033F00002020202020202020202020202010102AF +:1034000002020202020202020202020101010102A0 +:10341000020202020202020202020202010101028F +:103420000202020202020202020202010101010280 +:10343000020202020202020202020202010101026F +:10344000020202020202020202020202020201025D +:103450000202020202020102020101020101010252 +:10346000020202020202020202020202010101023F +:103470000202020202020101010101010101010235 +:103480000202010202020101010101010101010127 +:10349000010101010101010101010101010101001D +:1034A000000000000000000000000000000000021A +:1034B00002020202020202010102010101010002F4 +:1034C00001020202020202000002020202010102E3 +:1034D00002020202020002020202000002010102D4 +:1034E00002020202020202020202020001010102C1 +:1034F00002020202020202020202020201010102AF +:10350000020202020202020202020201010101029F +:10351000020202020202020201020202010101028F +:103520000202020202020201020202010101010280 +:10353000020202020202020202020202010101026E +:10354000020202020202020202020202020101025D +:103550000202020202010101010101020101010254 +:10356000020202020202020202020201010101023F +:103570000202020201010101010101010101010236 +:103580000202010201010101010101010101010128 +:10359000010101010101010101010101010101001C +:1035A0000000000000000000000000000000000219 +:1035B00002020201020201010202010101010002F4 +:1035C00002020202020202000002020202010102E1 +:1035D00002020202020202020202000001010102D2 +:1035E00002020202020202020202020201010102BE +:1035F00002020202020202020102020201010102AF +:10360000020202020202020202020201010101029E +:10361000020202020202010201020202010101028F +:103620000202020202010101010202010101010282 +:103630000202020202020202010201010101010270 +:10364000020202020202020202020202020101025C +:103650000202010102010101010101010101010256 +:103660000202010202020202010101010101010242 +:103670000101020201010101010101010101010237 +:103680000202010101010101010101010101010128 +:10369000010101010101010101010101010101001B +:1036A0000000000000000000000000000000000218 +:1036B00002020101020101010202010201010002F4 +:1036C00002020202020202000002010102010102E2 +:1036D00002020202020202020202000001010102D1 +:1036E00002020202020202020202020201010102BD +:1036F00002020202020202020102020201010102AE +:10370000020202020202020102020201010101029E +:10371000020202020202010201020201010101028F +:103720000201020202010101010202010101010282 +:103730000202020202010201010201010101010271 +:10374000020202020202020202020202010101025C +:103750000202010101010101010101010101010256 +:103760000102010202010101010101010101010245 +:103770000101010201010101010101010101010237 +:103780000101010101010101010101010101010129 +:10379000010101010101010101010101010101001A +:1037A0000000000000000000000000000000000217 +:1037B00002020101020101020202020201010002F1 +:1037C00002020202020202000002010102010102E1 +:1037D00002020202020202020202020001010102CE +:1037E00002020202020202020202020201010102BC +:1037F00002020202020202020102020201010102AD +:1038000002020201010201010202020101010102A0 +:103810000201010101020101010202010101010293 +:103820000201020102010101010101010101010284 +:103830000102010202010101010101010101010274 +:10384000020202020202020202020202010101025B +:103850000102010101010101010101010101010256 +:103860000101010201010101010101010101010246 +:103870000101010201010101010101010101010236 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010019 +:1038A0000000000000000000000000000000000216 +:1038B00002010102010102020202020101010002F1 +:1038C00002020202020202000001010102010102E1 +:1038D00002020202020202020202020201010102CB +:1038E00002020202020202020202020201010102BB +:1038F00002010202020202020102020201010102AD +:1039000002020101010101010202020101010102A1 +:103910000101010101020101010101010101010295 +:103920000101020101010101010101010101010285 +:103930000102010101010101010101010101010275 +:10394000020202020202020202020202010101025A +:103950000101010101010101010101010101010256 +:103960000101010101010101010101010101010246 +:103970000101010201010101010101010101010235 +:103980000101010101010101010101010101010127 +:103990000101010101010101010101010101010018 +:1039A0000000000000000000000000000000000215 +:1039B00002010102010202020102020101010002F0 +:1039C00002020202020202000001010101010102E1 +:1039D00002020202020202020202020201010102CA +:1039E00002010202020202020202020201010102BB +:1039F00002010202020202020102020201010102AC +:103A000002010101010101010202020101010102A1 +:103A10000101010101020101010101010101010294 +:103A20000101020101010101010101010101010284 +:103A30000102010101010101010101010101010274 +:103A4000020202020202020201010101010101025D +:103A50000101010101010101010101010101010255 +:103A60000101010101010101010101010101010245 +:103A70000101010101010101010101010101010235 +:103A80000101010101010101010101010101010126 +:103A90000101010101010101010101010101010017 +:103AA0000000000000000000000000000000000214 +:103AB00002010102020202020101010101010002F0 +:103AC00002020201020202000001010101010102E1 +:103AD00002010202020202020202020201010102CA +:103AE00002010202020202020202020201010102BA +:103AF00002010102020202020102020201010102AC +:103B000001010101010101010101010101010102A4 +:103B10000101010101010101010101010101010294 +:103B20000101010101010101010101010101010284 +:103B30000102010101010101010101010101010273 +:103B4000020202020102010101010101010101025F +:103B50000101010101010101010101010101010254 +:103B60000101010101010101010101010101010244 +:103B70000101010101010101010101010101010234 +:103B80000101010101010101010101010101010125 +:103B90000101010101010101010101010101010016 +:103BA0000000000000000000000000000000000114 +:103BB00002010101020201010101010101010002F2 +:103BC00002020201020202020001010101010102DE +:103BD00002010202020202020202020201010102C9 +:103BE00002010202020202020202020201010102B9 +:103BF00002010102020202020102020101010102AC +:103C000001010101010101010101010101010102A3 +:103C10000101010101010101010101010101010293 +:103C20000101010101010101010101010101010283 +:103C30000101010101010101010101010101010273 +:103C40000201020201010101010101010101010260 +:103C50000101010101010101010101010101010253 +:103C60000101010101010101010101010101010243 +:103C70000101010101010101010101010101010233 +:103C80000101010101010101010101010101010124 +:103C90000101010101010101010101010101010015 +:103CA0000000000000000000000000000000000113 +:103CB00002010101010101010101010101010002F3 +:103CC00002020201020202020201010101010102DB +:103CD00002010202020202020202020201010102C8 +:103CE00002010202020202020202020201010102B8 +:103CF00001010102020102020101010101010102AF +:103D000001010101010101010101010101010102A2 +:103D10000101010101010101010101010101010292 +:103D20000101010101010101010101010101010282 +:103D30000101010101010101010101010101010272 +:103D40000101010201010101010101010101010162 +:103D50000101010101010101010101010101010252 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000201010101010101010101010101010013 +:103DA0000000000000000000000000000000000211 +:103DB00002010101010101010101010101010002F2 +:103DC00002020201020202020201010101010102DA +:103DD00002010202020202020202020201010102C7 +:103DE00001010202020202020201020201010102B9 +:103DF00001010102010102010101010101010101B1 +:103E000001010101010101010101010101010102A1 +:103E10000101010101010101010101010101010291 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010271 +:103E40000101010201010101010101010101010161 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000201010101010101010101010101010012 +:103EA000000000000000000000000000010100020E +:103EB00002010101010101010101010101010002F1 +:103EC00002020201020202020201010101010102D9 +:103ED00001010202020202020201020201010102C8 +:103EE00001010202020102020101010101010102BC +:103EF00001010101010101010101010101010101B2 +:103F000001010101010101010101010101010101A1 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010270 +:103F40000101010101010101010101010101010161 +:103F50000101010101010101010101010101010151 +:103F60000101010101010101010101010101010141 +:103F70000101010101010101010101010101010131 +:103F80000101010101010101010101010101010121 +:103F9000020202010101010101010101010101000F +:103FA000000000000000000000000000010100010E +:103FB00002010101010101010101010101000002F1 +:103FC00002020201020201020201010101010102D9 +:103FD00001010202020202020101020201010102C8 +:103FE00001010202010101010101010101010102BE +:103FF00001010101010101010101010101010101B1 +:1040000001010101010101010101010101010101A0 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:10403000010101010101010101010101010101026F +:104040000101010101010101010101010101010160 +:104050000101010101010101010101010101010150 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:10408000010101010101010101010101010101021F +:10409000020202010101010101010101010101000E +:1040A000000000000000000000000000010100010D +:1040B00001010101010101010101010101000002F1 +:1040C00002020201020101020201010101010102D9 +:1040D00001010201010202010101010101010102CC +:1040E00001010101010101010101010101010102BF +:1040F00001010101010101010101010101010101B0 +:10410000010101010101010101010101010101019F +:10411000010101010101010101010101010101018F +:10412000010101010101010101010101010101017F +:10413000010101010101010101010101010101016F +:10414000010101010101010101010101010101015F +:10415000010101010101010101010101010101014F +:10416000010101010101010101010101010101013F +:10417000010101010101010101010101010101012F +:10418000010101010101010101010101010101021E +:10419000020202020201010101010101010101000B +:1041A000000000000000000000000101010100010A +:1041B00001010101010101010101010101000002F0 +:1041C00002020201010101020201010101010102D9 +:1041D00001010201010201010101010101010102CC +:1041E00001010101010101010101010101010101BF +:1041F00001010101010101010101010101010101AF +:10420000010101010101010101010101010101019E +:10421000010101010101010101010101010101018E +:10422000010101010101010101010101010101017E +:10423000010101010101010101010101010101016E +:10424000010101010101010101010101010101015E +:10425000010101010101010101010101010101014E +:10426000010101010101010101010101010101013E +:10427000010101010101010101010101010101012E +:10428000010101010101010101010101010101021D +:104290000202020202020102020202010101010005 +:1042A0000000000000000000010101010101000107 +:1042B00001010101010101010101010100000002F0 +:1042C00002010201010101020201010101010102D9 +:1042D00001010101010101010101010101010101CE +:1042E00001010101010101010101010101010101BE +:1042F00001010101010101010101010101010101AE +:10430000010101010101010101010101010101019D +:10431000010101010101010101010101010101018D +:10432000010101010101010101010101010101017D +:10433000010101010101010101010101010101016D +:10434000010101010101010101010101010101015D +:10435000010101010101010101010101010101014D +:10436000010101010101010101010101010101013D +:10437000010101010101010101010101010101012D +:10438000010101010101010101010101010101021C +:1043900002020202020202020202020202020200FF +:1043A0000100000000000001010101010101000104 +:1043B00001010101010101010101010100000102EE +:1043C00002010101010101020201010101010102D9 +:1043D00001010101010101010101010101010101CD +:1043E00001010101010101010101010101010101BD +:1043F00001010101010101010101010101010101AD +:10440000010101010101010101010101010101019C +:10441000010101010101010101010101010101018C +:10442000010101010101010101010101010101017C +:10443000010101010101010101010101010101016C +:10444000010101010101010101010101010101015C +:10445000010101010101010101010101010101014C +:10446000010101010101010101010101010101013C +:10447000010101010101010101010101010101012C +:10448000010101010101010101010101010101021B +:1044900002020202020202020202020202020202FC +:1044A00002020202020202020202020202020201ED +:1044B00001010001010101010101010000000102EF +:1044C00002010101010101020201010101010101D9 +:1044D00001010101010101010101010101010101CC +:1044E00001010101010101010101010101010101BC +:1044F00001010101010101010101010101010101AC +:10450000010101010101010101010101010101019B +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101021A +:1045900002020202020202020202020202020202FB +:1045A00002020202020202020202020202020201EC +:1045B00001010001010101010001010000000102EF +:1045C00002010101010101010101010101010101DA +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:104680000101010101010101010101010101010219 +:1046900002020202020202020202020202020202FA +:1046A00002020202020202020202020202020201EB +:1046B00001010000000100000000000000000102F4 +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010218 +:1047900002020202020202020202020202020202F9 +:1047A00002020202020202020202020202020201EA +:1047B00001000000000000000000000000000102F5 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000201020101010101010101020202020211 +:1048900002020202020202020202020202020202F8 +:1048A00002020202020202020202020202020201E9 +:1048B00001000000000000000000000000000101F5 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000202020202020202020202020202020207 +:1049900002020202020202020202020202020202F7 +:1049A00002020202020202020202020202020201E8 +:1049B00001000000000000000000000000010101F3 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000201010101010101010101010101010135 +:104A70000200010101010101010101010101020224 +:104A80000202020202020202020202020202020206 +:104A900002020202020202020202020202020202F6 +:104AA00002020202020202020202020202020201E7 +:104AB00001000000000000000000000000010101F2 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101000101010101010101010101010136 +:104B70000202020102020202020202020202020216 +:104B80000202020202020202020202020202020205 +:104B900002020202020202020202020202020202F5 +:104BA00002020202020202020202020202020200E7 +:104BB00001000000000000000000000001010101F0 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C5000020100000100000101010001000000014B +:104C60000000000101010101010101010202020233 +:104C70000202020202020202020202020202020214 +:104C80000202020202020202020202020202020204 +:104C900002020202020202020202020202020202F4 +:104CA00002020202020202020202020202020200E6 +:104CB00001010100000000000000000001010101ED +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000201010101010101010101010101010162 +:104D40000101010101010101010101010101010054 +:104D5000010000000000000000000001020202004B +:104D60000202020202020202020202020202020223 +:104D70000202020202020202020202020202020213 +:104D80000202020202020202020202020202020203 +:104D900002020202020202020202020202020202F3 +:104DA00002020202020202020202020202020200E5 +:104DB00001010100000000000000000001010101EC +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000202010101010100010101020101010170 +:104E30000101000101000101010101010100000166 +:104E40000102010100010101010101010100000055 +:104E50000202020202020202020202020202020232 +:104E60000202020202020202020202020202020222 +:104E70000202020202020202020202020202020212 +:104E80000202020202020202020202020202020202 +:104E900002020202020202020202020202020202F2 +:104EA00002020202020202020202020202020201E3 +:104EB00001010100000000000000000101010101EA +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000102020101010101000101010101010180 +:104F20000101010200020200000101010000000174 +:104F30000001000000000000000100000202020168 +:104F40000201000100000000000000000202020255 +:104F50000202020202020202020202020202020231 +:104F60000202020202020202020202020202020221 +:104F70000202020202020202020202020202020211 +:104F80000202020202020202020202020202020201 +:104F900002020202020202020202020202020202F1 +:104FA00002020202020202020202020202000201E4 +:104FB00001010100000000010101010101010101E5 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:10500000010202020201010101010102010101018B +:105010000001010202010200000101000100000183 +:105020000000000100010100000000000202020275 +:105030000202020202020202020202020202020250 +:105040000202020202020202020202020202020240 +:105050000202020202020202020202020202020230 +:105060000202020202020202020202020202020220 +:105070000202020202020202020202020202020210 +:105080000202020202020202020202020202020200 +:1050900002020202020202020202020202020202F0 +:1050A00002020202020202020202020000000201E7 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F000010101010101010101010101010101029F +:105100000001010101020202010101010100000090 +:105110000200000101000100000000000202020282 +:10512000020202020202020202020202020202025F +:10513000020202020202020202020202020202024F +:10514000020202020202020202020202020202023F +:10515000020202020202020202020202020202022F +:10516000020202020202020202020202020202021F +:10517000020202020202020202020202020202020F +:1051800002020202020202020202020202020202FF +:1051900002020202020202020202020202020202EF +:1051A00002020202020202020202000000000001EA +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010102010101010100010101020101019E +:105200000200000000010101000000000202020291 +:10521000020202020202020202020202020202026E +:10522000020202020202020202020202020202025E +:10523000020202020202020202020202020202024E +:10524000020202020202020202020202020202023E +:10525000020202020202020202020202020202022E +:10526000020202020202020202020202020202021E +:10527000020202020202020202020202020202020E +:1052800002020202020202020202020202020202FE +:1052900002020202020202020202020202020202EE +:1052A00002020202020002020200000000000001ED +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010102010101AD +:1052F000020201010101010100010101010202029A +:10530000020202020202020202020202020202027D +:10531000020202020202020202020202020202026D +:10532000020202020202020202020202020202025D +:10533000020202020202020202020202020202024D +:10534000020202020202020202020202020202023D +:10535000020202020202020202020202020202022D +:10536000020202020202020202020202020202021D +:10537000020202020202020202020202020202020D +:1053800002020202020202020202020202020202FD +:1053900002020202020202020202020202020202ED +:1053A00002020202000000000000000000000001F4 +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010102010101BC +:1053E00002020101010101010101010101020202A8 +:1053F000020202020202020202020202020202028D +:10540000020202020202020202020202020202027C +:10541000020202020202020202020202020202026C +:10542000020202020202020202020202020202025C +:10543000020202020202020202020202020202024C +:10544000020202020202020202020202020202023C +:10545000020202020202020202020202020202022C +:10546000020202020202020202020202020202021C +:10547000020202020202020202020202020202020C +:1054800002020202020202020202020202020202FC +:1054900002020202020202020202020202020202EC +:1054A00002020200000000000000000000000001F5 +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00002020101010101010101010101020202B7 +:1054E000020202020202020202020202020202029C +:1054F000020202020202020202020202020202028C +:10550000020202020202020202020202020202027B +:10551000020202020202020202020202020202026B +:10552000020202020202020202020202020202025B +:10553000020202020202020202020202020202024B +:10554000020202020202020202020202020202023B +:10555000020202020202020202020202020202022B +:10556000020202020202020202020202020202021B +:10557000020202020202020202020202020202020B +:1055800002020202020202020202020202020202FB +:1055900002020202020202020202020202020202EB +:1055A00002020200000000000000000000000001F4 +:1055B00001010101010101010101010101010101DB +:1055C00001010101010102010101020101010102C8 +:1055D00002020202020202020202020202020202AB +:1055E000020202020202020202020202020202029B +:1055F000020202020202020202020202020202028B +:10560000020202020202020202020202020202027A +:10561000020202020202020202020202020202026A +:10562000020202020202020202020202020202025A +:10563000020202020202020202020202020202024A +:10564000020202020202020202020202020202023A +:10565000020202020202020202020202020202022A +:10566000020202020202020202020202020202021A +:10567000020202020202020202020202020202020A +:1056800002020202020202020202020202020202FA +:1056900002020202020202020202020202020202EA +:1056A00002020000000000000000000000000001F5 +:1056B00001010101010101010101010101010101DA +:1056C00000000000010101010101010000000002D1 +:1056D00002020202020202020202020202020202AA +:1056E000020202020202020202020202020202029A +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002000000000000000000000000000001F6 +:1057B00001010101010101010101010101010101D9 +:1057C00002020202000000000000000002020202C9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002000000000000000000000000000001F5 +:1058B00001010101010101010101010101010102D7 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002000000000000000000000000000001F4 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000101010101010101010101010101010186 +:105A10000101010101010101010101010101010176 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010101010101010101010116 +:105A80000101010101010101010101010101010106 +:105A900001010101010101010101010101010102F5 +:105AA00002000000000000000000000000000001F3 +:105AB00001010101010101010101010101010100D7 +:105AC00000000000000000000000000000000001D5 +:105AD00001010101010101010101010101010101B6 +:105AE00001010101010101010101010101010101A6 +:105AF0000101010101010101010101010101010196 +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010175 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101010101010101010145 +:105B50000101010101010101010101010101010135 +:105B60000101010101010101010101010101010125 +:105B70000101010101010101010101010101010115 +:105B80000101010101010101010101010101010105 +:105B900001010101010101010101010101010102F4 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000037BD +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000020000000000D2 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000002000000000091 +:105D10000000000200000000000000000000000081 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000020000000041 +:105D60000000000000000000020000000000000031 +:105D70000000000000000200000000000000000021 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000200020200020202E7 +:105DB00002020202000000020200000000000000D7 +:105DC00000000000000000020000020000000000CF +:105DD00000000000000002000000000000000000C1 +:105DE00000000000000202000000000000000000AF +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000001020202020100000088 +:105E1000000000020202000000000000000000007C +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E5000000000000000000202000002000000003C +:105E60000000000202020000020102020002000221 +:105E7000000000000002020000000000000000001E +:105E8000000000000000020002000000000000000E +:105E900002000002020202020200000002000200F0 +:105EA00000000002020202000200020202020202DC +:105EB00002020202000000020200000000000000D6 +:105EC00000000000000000020000020000000000CE +:105ED00000000200000002000000000000000000BE +:105EE00000000000000202000000000000000000AE +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000202020202020102000082 +:105F1000000000020202000000000000000000007B +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000002020202020000000037 +:105F6000000000020202000002020202000202021D +:105F70000200000000020200000001020002000214 +:105F80000000000000000200020202000002000205 +:105F900002000202020202020202020202020202E3 +:105FA00000000002020202000202020202020202D9 +:105FB00002020202020200020200000000000000D1 +:105FC00000000000000000020000020000000000CD +:105FD00000000200000002000000000000000000BD +:105FE00002000000000202000000000000000000AB +:105FF000000000000000000002000000000000009F +:10600000000000000200020202020202020200007E +:10601000000000020202000000000000000000007A +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:10604000000000000000000200000000000000004E +:106050000000000000000002020202020000000036 +:10606000000000020202020002020202000202021A +:10607000020200000002020002000102020202020B +:1060800002000000000002000202020002020202FE +:1060900002000202020202020202020202020202E2 +:1060A00002000002020202000202020202020202D6 +:1060B00002020202020200020200000000000000D0 +:1060C00000000000000000020000020000000000CC +:1060D00000000200000002000000000000000000BC +:1060E00002000000000202000000000000000000AA +:1060F000000000000000000002000000000000029C +:10610000000000000200020202020202020200027B +:106110000000000202020000000000000000000079 +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000200000001000000004C +:106150000000000000000002020202020002000033 +:106160000000020202020202020202020002020215 +:106170000202000000020200020202020202020207 +:1061800002020000000002000202020202020202F9 +:1061900002020202020202020202020202020202DF +:1061A00002020202020202000202020202020202D1 +:1061B00002020202020200020200020000000002CB +:1061C00000000000000000020000020000000000CB +:1061D00000000200000202000000000000000000B9 +:1061E00002000000000202000000000000000000A9 +:1061F000000000000000000102000000000000029A +:106200000000000002000202020202020202020278 +:106210000200000202020200000000000000000074 +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:106240000000000000000002020000020000000048 +:10625000000000000000000202020202020202002E +:106260000000020202020202020202020002020214 +:106270000202020000020202020202020202020202 +:1062800002020002000002000202020202020202F6 +:1062900002020202020202020202020202020202DE +:1062A00002020202020202000101010101010101D8 +:1062B00001010101010101020200020000000002CF +:1062C00000000000000000020000020100000000C9 +:1062D00000000200000202000000000000000000B8 +:1062E00002000000000202000000000000000000A8 +:1062F0000000000000000001020001000000000298 +:106300000000000002000202020202020202020277 +:106310000200000202020200000000000000000073 +:10632000000000000000000000000200000000006B +:10633000000000000000000000000000000000005D +:106340000000000000000002020102020000000044 +:10635000000000000000000202020202020202022B +:106360000002020202020202020202020102020210 +:1063700002020202000202020202020202020202FF +:1063800002020202000002000202020202020202F3 +:1063900002020202020202020202020202020202DD +:1063A00002020202020202000101010101010101D7 +:1063B00001010101010101020202020000000002CC +:1063C00000020000000200020000020200000000C3 +:1063D00000000200000202000100000000000000B6 +:1063E00002000000000202000000000000000000A7 +:1063F0000000000000000001020001000000000297 +:106400000000000002020202020202020202020274 +:106410000200000202020200000000000000000072 +:106420000000000000000002010002000000000067 +:106430000000000000000000000202000000000058 +:106440000000000000000002020202020001000041 +:106450000000000000000202020202020202020228 +:10646000020202020202020202020202020202020C +:1064700002020202000202020202020202020202FE +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202000101000101010101D7 +:1064B00001010101010101020202020000000002CB +:1064C00000020000000200020000020200000000C2 +:1064D00000000200000202010100000000000000B4 +:1064E00002000000000202000002000000000000A4 +:1064F0000000000000000002020001000000000295 +:106500000000000002020202020202020202020273 +:10651000020000020202020002000200000000006D +:106520000000000000000002010002000000000066 +:106530000000000000000002000202000000000055 +:10654000000000000000000202020202000100023E +:106550000000000000020202020202020202020225 +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020201020202020202020202DC +:1065A00002020202020202000101000101010101D6 +:1065B00001010101010101020202020002020002C6 +:1065C00000020000000200020000020200000000C1 +:1065D00000000202000202010200000000000000B0 +:1065E00002000000000202000002000000000000A3 +:1065F0000000000000000002020002000100000292 +:106600000000000002020202020202020202020272 +:10661000020000020202020002020200000000006A +:10662000000000000000000201020200010202005E +:106630000000000000000202000202000000000052 +:106640000000000000000002020202020202020238 +:106650000200000000020202020202020202020222 +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202010101020202020202020202DD +:1066A00002020202020202000100000100010101D7 +:1066B00001010101010101020202020002020002C5 +:1066C00000020000000200020000020200000000C0 +:1066D00000000202000202020200000000000000AE +:1066E00002000000000202000002000000000000A2 +:1066F0000000000000000002020002010100000290 +:106700000000000002020202020202020202020271 +:106710000200000202020200020202000000000069 +:10672000000000000000000202020201020202005A +:106730000000000000000202020202020101020049 +:106740000000000000020002020202020202020235 +:10675000020200000002020202020202020202021F +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020201020202020202020202EA +:1067900002020201010101020202020202020202DD +:1067A00002020202020201000000000000000000DC +:1067B00000000000000001020202020002020002CA +:1067C00000020000000200020000020200000000BF +:1067D00000000202000202020200000000000000AD +:1067E00002000000000202010002000000000000A0 +:1067F000000000000000000202000201010000028F +:106800000000000002020202020202020202020270 +:106810000200000202020200020202000200020064 +:106820000000000000000002020202020202020058 +:106830000000020000000202020202020202020044 +:106840000000000200020002020202020202020232 +:10685000020200000002020202020202020202021E +:106860000202020202020202020202020202020208 +:1068700002020202020201020202020202020202F9 +:1068800002020202020201020202020202020202E9 +:1068900002020101010101020202020202020202DD +:1068A00002020202010101000000000000000000DD +:1068B00000000000000001020202020002020001CA +:1068C00000010000000200020000020200000000BF +:1068D00000020202000202020201000000000000A9 +:1068E000020000000002020100020000000000009F +:1068F000000000000000000202000201020000028D +:10690000000000000202020202020202020202026F +:10691000020000020202020002020202020202025D +:10692000000200020000020202020202020202024F +:10693000020002020000020202020202020202023D +:10694000000000020002020202020202020202022F +:10695000020202000002020202020202020202021B +:106960000202020202020202020202020202020207 +:1069700002020202020201020202020202020202F8 +:1069800002020202020201020202020202020202E8 +:1069900001020101010101020202020202020202DD +:1069A00002020201010101000000000000000000DD +:1069B00000000000000001020202020002020001C9 +:1069C00000010000020200020000020202000000BA +:1069D00000020202020202020201000001000000A5 +:1069E000020000000002020202020000000000009B +:1069F000000000000000000202000202020000028B +:106A0000000000000202020202020202020202026E +:106A1000020000020202020002020202020202025C +:106A20000202020200020202020202020202020248 +:106A3000020002020200020202020202020202023A +:106A4000020000020002020202020202020202022C +:106A50000202020200020202020202020202020218 +:106A60000202020201010102020202020202020209 +:106A700002020202020101020202020202020202F8 +:106A800002020202020201020202020202020202E7 +:106A900001020101010101020202020202020202DC +:106AA00002020201010101000000000000000000DC +:106AB00000000000000001020202020002020001C8 +:106AC00000010000020200020000020202020000B7 +:106AD00000020202020202020201010001000000A3 +:106AE000020000000002020202020000000000009A +:106AF000000000000000000202000202020000028A +:106B0000000000000202020202020202020202026D +:106B1000020200020101020002020202020202025B +:106B20000202020200020202020202020202020247 +:106B30000202020202000202020202020202020237 +:106B40000200000202020202020202020202020229 +:106B50000202020200020202020202020202020217 +:106B60000202020101010102020202020202020209 +:106B700002020202020101020202020202020202F7 +:106B800002020202020201020202020202020201E7 +:106B900001010101010101020202020202020202DC +:106BA00002020201010101000000000000000000DB +:106BB00000000100000001020202020202020201C2 +:106BC00002010200020200020000020202020200B0 +:106BD000000202020202020202020200020000009F +:106BE000020000000002010202020000000000009A +:106BF0000000000000000002020002020200000289 +:106C0000000000000202010202020202020202026D +:106C1000020200010101010002020202020202025C +:106C20000202020200020202020202020202020246 +:106C30000202020202020202020202020202020234 +:106C40000202000202020202020202020202020226 +:106C50000202020202020202020202020202020214 +:106C60000202020101010102020202020202020208 +:106C700002020202020101020202020202020202F6 +:106C800002020201010101020102020202010101EC +:106C900001010101010101020202020202020202DB +:106CA00002020101010101000000000000000000DB +:106CB00000000101010101020202010202010201C0 +:106CC00002010200020100020002020202020200AE +:106CD000000202020202010202020201020000009E +:106CE000020000000001010202020000000000009A +:106CF0000000000000000002020002020200000288 +:106D0000000000000202010202020202020202026C +:106D10000202000101010102020202020202020259 +:106D20000202020200020202020202020202020245 +:106D30000202020202020202020202020202020233 +:106D40000202000202020202020202020202020225 +:106D50000202020202020102020202020202020214 +:106D60000202010101010102020202020202020208 +:106D700002020202020101020202020202020201F6 +:106D800001010101010101020101020201010101F0 +:106D900001010101010101020202020202020101DC +:106DA00001010101010101000000000000000000DC +:106DB00000000101010101020202010201010201C0 +:106DC00002010200020100020002020202020200AD +:106DD000000202020202010202020201020000009D +:106DE0000200000000010102020200000000000099 +:106DF0000000000000000002020002020200000287 +:106E0000000000000102010202020202020202026C +:106E10000202000101010102020202020202020258 +:106E20000202020200020202020202020202020244 +:106E30000202020202020102020202020202020233 +:106E40000202020202020202020202020202020222 +:106E50000202020202020102020202020202020213 +:106E60000202010101010102020202020202020108 +:106E700001010101010101020202020202010101FC +:106E800001010101010101020101010101010101F1 +:106E900001010101010101020202020201010101DD +:106EA00001010101010101000000000000000000DB +:106EB00000000101010100020202010201010202BF +:106EC00002020200020100020002020202020200AB +:106ED000000202020202010202020202020000009B +:106EE0000200000000010102020200000000000098 +:106EF0000000000000000002020102020200000285 +:106F0000000000000102010202020202020102026C +:106F10000202020101010102020202020202020255 +:106F20000202020200020202020202020202020243 +:106F30000202020202020102020202020202020232 +:106F40000202020202020202020202020202020221 +:106F50000202020202010102020202010202020214 +:106F60000202010101010102020202020201010109 +:106F700001010101010101020202020101010101FD +:106F800001010101010101020101010101010101F0 +:106F900001010101010101020102020101010101DE +:106FA00001010101010101000000000000000000DA +:106FB00000000101010100020202010201010202BE +:106FC00002020102010100020002020202020200AA +:106FD0000202020202010102020202020200000099 +:106FE0000200000002010102020200000000000095 +:106FF0000000000000020002020202020200000281 +:10700000000000000101010202020102020102026D +:107010000202020101010102020202020202020254 +:107020000202020200020102020202020202020243 +:107030000202020202020102020202020202020231 +:107040000202020202010102020202020202020222 +:107050000202020202010102020202010202020213 +:10706000020101010101010201020201020101010B +:1070700001010101010101020102020101010101FD +:1070800001010101010101020101010101010101EF +:1070900001010101010101020101010101010101DF +:1070A00001010101010101000000000000000000D9 +:1070B00000000101010100020202010201010202BD +:1070C00001020102010100020002020202020200AA +:1070D0000202010202010102020202020201000098 +:1070E0000100000002010102020200000000000095 +:1070F000000000000002000202020202020200027E +:10710000000000020101010201020101020102016D +:107110000102020101010102020202020202020254 +:107120000202020200020102020202020202020242 +:107130000202020202020102020202020202020230 +:107140000202020202010102020202020202020221 +:107150000202020202010102010102010201010117 +:10716000010101010101010201020101020101010C +:1071700001010101010101020101020101010101FD +:1071800001010101010101020101010101010101EE +:1071900001010101010101020101010101010101DE +:1071A00001010101010101000000000000000000D8 +:1071B00000000101010100010202020201020102BC +:1071C00001020202010100020002020202020200A8 +:1071D0000202010202010102020202020202000096 +:1071E0000100000002010102020200000000000094 +:1071F0000200000000020202020202020202020178 +:10720000020002020101010201010101020101016A +:107210000102020101010102020202020202020253 +:107220000202020100010102020202020202020243 +:107230000202020201010102020202020202020231 +:107240000202020101010102020202020202020222 +:107250000202020202010102010101010101010118 +:10726000010101010101010201010101020101010C +:1072700001010101010101020101020101010101FC +:1072800001010101010101020101010101010101ED +:1072900001010101010101020101010101010101DD +:1072A00001010101010101000000000000000000D7 +:1072B00000000101010100010201020202020102BB +:1072C00001020202010100020002020202020200A7 +:1072D0000202010202010102020202020202000293 +:1072E0000100000002010102020200000000000093 +:1072F0000202000000020202020202020202020175 +:107300000202020201010102010101010101010168 +:107310000102020101010102020202020202020252 +:107320000202010102010102020202020202020241 +:107330000202010101010102020202020202020232 +:107340000202020101010102020202010202020123 +:10735000010101010101010201010101010101011C +:10736000010101010101010201010101020101010B +:1073700001010101010101020101010101010101FC +:1073800001010101010101020101010101010101EC +:1073900001010101010101020101010101010101DC +:1073A00001010101010101000000000000000000D6 +:1073B00000000101010100010101020202020102BB +:1073C00002020101010100020202020202020200A5 +:1073D0000202010101010102020202020202000294 +:1073E0000100000002010102020100000000000093 +:1073F0000202000000020202010202020202020175 +:107400000202020201010102010101010101010167 +:107410000102020101010102020202020202020251 +:107420000202010102010102020202020202010241 +:107430000202010101010102020102020202010233 +:107440000202020101010102010202010202010124 +:10745000010101010101010201010101010101011B +:10746000010101010101010201010101010101010B +:1074700001010101010101020101010101010101FB +:1074800001010101010101020101010101010101EB +:1074900001010101010101010101010101010101DC +:1074A00001010101010101000000000000000000D5 +:1074B00000000001010000010101020102020201BD +:1074C00002010101010100020202010202020202A4 +:1074D0000202010101010102020202020202000293 +:1074E0000102000002010102010101000000000090 +:1074F0000202020000020202010202020202020172 +:107500000202020201010102010101010101010166 +:107510000101020101010102020202020202020251 +:107520000201010102010102020201020201010144 +:107530000101010101010102020101020202010136 +:107540000102020101010102010201010102010126 +:10755000010101010101010101010101010101011B +:10756000010101010101010201010101010101010A +:1075700001010101010101020101010101010101FA +:1075800001010101010101010101010101010101EB +:1075900001010101010101010101010101010101DB +:1075A00001010101010101000000000000000000D4 +:1075B00000000000000000010101020202020201BD +:1075C00002010101010100020202010202020202A3 +:1075D0000202010101010102020202020202020290 +:1075E000010200000201010201010100000000008F +:1075F0000202020000010102010202020202020173 +:107600000202020201010102010101010101010165 +:107610000101010101010102010102020202010155 +:107620000101010102010102020201020101010145 +:107630000101010101010102020101010101010138 +:10764000010101010101010101010101010101012A +:10765000010101010101010101010101010101011A +:107660000101010101010102010101010101010109 +:1076700001010101010101010101010101010101FA +:1076800001010101010101010101010101010101EA +:1076900001010101010101010101010101010101DA +:1076A00001010101010101000000000000000000D3 +:1076B00000010000000000010101010102010201BE +:1076C00001010101010100020202010202020202A3 +:1076D000020201010101010202020202020202028F +:1076E000010200000101010201010100000000008F +:1076F0000202020000010102010202020202020172 +:107700000202020201010101010101010101010165 +:107710000101010101010102010101020101010157 +:107720000101010101010102020101010101010147 +:107730000101010101010102010101010101010138 +:107740000101010101010101010101010101010129 +:107750000101010101010101010101010101010119 +:107760000101010101010101010101010101010109 +:1077700001010101010101010101010101010101F9 +:1077800001010101010101010101010101010101E9 +:1077900001010101010101010101010101010101D9 +:1077A00001010101010101000000000000000000D2 +:1077B00001010000000000020101010101010101BD +:1077C00001010101010100010202010102020202A4 +:1077D000020101010101010202020202020202028F +:1077E000010200000101010201010200000000008D +:1077F000020202020001010201020202020202016F +:107800000202020101010101010101010101010165 +:107810000101010101010102010101010101010157 +:107820000101010101010102020101010101010146 +:107830000101010101010102010101010101010137 +:107840000101010101010101010101010101010128 +:107850000101010101010101010101010101010118 +:107860000101010101010101010101010101010108 +:1078700001010101010101010101010101010101F8 +:1078800001010101010101010101010101010101E8 +:1078900001010101010101010101010101010101D8 +:1078A00001010101010101000000000000000001D0 +:1078B00001010000000000020101010101010101BC +:1078C00001010101010100010202010102020202A3 +:1078D000020101010101010201020202020202028F +:1078E000010202000101010201010200000000008A +:1078F000020202020001010201020202020202016E +:107900000202010101010101010101010101010165 +:107910000101010101010102010101010101010156 +:107920000101010101010101010101010101010147 +:107930000101010101010102010101010101010136 +:107940000101010101010101010101010101010127 +:107950000101010101010101010101010101010117 +:107960000101010101010101010101010101010107 +:1079700001010101010101010101010101010101F7 +:1079800001010101010101010101010101010101E7 +:1079900001010101010101010101010101010101D7 +:1079A00001010101010101000100000000000001CE +:1079B00001010000000000020101010101010101BB +:1079C00001010101010100010202010102020102A3 +:1079D000020101010101010201020202020202028E +:1079E0000102020201010102010102000100000086 +:1079F0000101010101010102010201020102020172 +:107A00000202010101010101010101010101010164 +:107A10000101010101010102010101010101010155 +:107A20000101010101010101010101010101010146 +:107A30000101010101010101010101010101010136 +:107A40000101010101010101010101010101010126 +:107A50000101010101010101010101010101010116 +:107A60000101010101010101010101010101010106 +:107A700001010101010101010101010101010101F6 +:107A800001010101010101010101010101010101E6 +:107A900001010101010101010101010101010101D6 +:107AA00001010101010101000100000000000101CC +:107AB00001010000000000020101010101010101BA +:107AC00001010101010000010202010101010102A5 +:107AD000010101010101010201020202010202028F +:107AE0000102020201010102010102010100000084 +:107AF0000101010101010102010201010102020172 +:107B00000101010101010101010101010101010165 +:107B10000101010101010102010101010101010154 +:107B20000101010101010101010101010101010145 +:107B30000101010101000101010101010101010136 +:107B40000101010101010101010101010101010125 +:107B50000101010101010101010101010101010115 +:107B60000101010101010101010101010101010105 +:107B700001010101010101010101010101010101F5 +:107B800001010101010101010101010101010101E5 +:107B900001010101010101010101010101010101D5 +:107BA00001010101010101000100000100010101C9 +:107BB00001010000000000020101010101010101B9 +:107BC00001010101010000010201010101010102A5 +:107BD0000101010101010102010201020102020190 +:107BE0000101020201010102010102010100000084 +:107BF0000101010101010102010201010101010173 +:107C00000101010101010101010101010101010164 +:107C10000101010101010102010101010101010153 +:107C20000101010101010101010101010101010144 +:107C30000101010101000101010101010101010135 +:107C40000101010101010101010101000101010125 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010001010101010101E5 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101000100000100010101C8 +:107CB00001010000000000020101010101010101B8 +:107CC00001010101000001010201010101010102A4 +:107CD0000101010101010102010101010101020192 +:107CE0000101010101010102010102010200000084 +:107CF0000101010101010101010201010101010173 +:107D00000101010101010101010101010101010163 +:107D10000101010101010102010101010101010152 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010100010101000101010125 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010000010101010101E5 +:107D900000010000000000010101010101010101D9 +:107DA00001010101010101020202020202020202BA +:107DB00002020202020202010100010101010101AD +:107DC00001010001000001010201010101010102A4 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010102020200000083 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010102010101010101010151 +:107E20000101010101010101010100010101010143 +:107E30000101010101010101010101010101010132 +:107E40000101010101010100010101010101010123 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010000000000000000EA +:107E900000000000000000010101010101010101D9 +:107EA00001010101010101020202020202020202B9 +:107EB00002020202020202010100010101010100AD +:107EC00001000000000001010201010101010101A6 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010102020200000082 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101000200000000000000E8 +:107F900000000000000000010101010101010101D8 +:107FA00001010101010101020202020202020202B8 +:107FB00002020202020202010100000001000100AF +:107FC00000000000000001010101010101010101A7 +:107FD0000101010101010101010101010101010191 +:107FE000010101010101010102010202020002007E +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101000202000000000000E5 +:1080900002000202020202010101010101010101CB +:1080A00001010101010101020202020202020202B7 +:1080B00002020202020202010100000000000000B0 +:1080C00000000000000001010101010101010101A6 +:1080D0000101010101010101010101010101010190 +:1080E000010101010101010102010202020002007D +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010001010101010101F0 +:1081800001010101010100000202020202020202D9 +:1081900002020202020202010201010101010101C7 +:1081A00001010102020202020202020202020202B2 +:1081B00002020202020202010000000000000000B0 +:1081C00000000000000001010101010101010101A5 +:1081D000010101010101010101010101010101018F +:1081E000010101010101010102010202020002007C +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010201010101010101FD +:1082700001010101010101010200010000000000F3 +:1082800000000000000002020202020202020202DA +:1082900002020202020202010202020202020202BF +:1082A00002020202020202020202020202020202AE +:1082B00002020202020202010000000000000000AF +:1082C00000000000000001010101010101010101A4 +:1082D000010101010101010101010101010101018E +:1082E0000101010101010101020102020200020279 +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010201010201015B +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101020101010101FC +:1083700001010101010100000202000202020202E9 +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020202BD +:1083A00002020202020202020202020202020202AD +:1083B00002020202020202010000000000000000AE +:1083C00000000000000101010101010101010101A2 +:1083D000010101010101010101010101010101018D +:1083E0000101010101010101020202020200010278 +:1083F000010101010101010101010101010101016D +:108400000101010101010101020102010102010159 +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101000101010101012D +:10844000010101010101010101010101010101011C +:10845000010101010101010101000100010101010E +:108460000101000201010101000001000100000002 +:1084700000000000000202020202020202020202E6 +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020202BC +:1084A00002020202020202020202020202020202AC +:1084B00002020202020202010100000000000000AC +:1084C00000000000000101010101010101010101A1 +:1084D000010101010101010101010101010101018C +:1084E0000101010101010101020201020202010177 +:1084F000010101010101010101010101010101016C +:108500000101010101010101020102010102010158 +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101000101010101012C +:10854000010101010101010102010101010101011A +:10855000010101010101010102000100010101010C +:1085600001010001020202000202000200020202F6 +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020202AB +:1085B00002020202020202010100000000000000AB +:1085C000000000000101010101010101010101019F +:1085D000010101010101010101010101010101018B +:1085E0000101010101010101020201020102010177 +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:108610000101010102020201010201010101010146 +:108620000101020201010101010101010101010138 +:10863000010101010101000102000001000100012E +:108640000101010102010102010101010101010118 +:108650000101010101010002020202020202020202 +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202020202DA +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020202AA +:1086B00002020202020202010100000000000000AA +:1086C000000000000101010101010101010101019E +:1086D000010101010101010101010101010101018A +:1086E0000101010101010101010201010102010178 +:1086F0000101010202010101010101010101010168 +:108700000101010101010101010201020101010157 +:108710000102020202020201000101010101010144 +:10872000010101010101000000010100000102003E +:10873000010001010100000101000002020000002F +:108740000001010101000001000000000001000023 +:108750000000000000020202020202020202020203 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020202A9 +:1087B00002020202020202000101000000000000A9 +:1087C000000001010101010101010101010101019B +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010201010101010178 +:1087F0000101010202010101010101010101010167 +:108800000101010101010102000201020201020253 +:108810000202020201010101000001010101010146 +:108820000101000000000000000102000001010041 +:108830000200010100000000000000010200000031 +:108840000000000200020200020202020202020212 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202020202020202020202D8 +:1088800002020202020202020202020202020202C8 +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202020202A8 +:1088B00002020202020202010101000000000001A6 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010102010101010101010177 +:1088F0000101010202010101000101010101010167 +:10890000010101010101010100010001010001015A +:10891000010101010101010000000101010101014A +:108920000101000000000000000201000002000040 +:10893000010002020200020202020202020202021C +:108940000202020202020202020202020202020207 +:1089500002020202020202020202020202020202F7 +:1089600002020202020202020202020202020202E7 +:1089700002020202020202020202020202020202D7 +:1089800002020202020202020202020202020202C7 +:1089900002020202020202020202020202020202B7 +:1089A00002020202020202020202000200020202AB +:1089B00002020202020000010101010101010101A4 +:1089C0000101010101010101010101010101010197 +:1089D0000101010101010101010101010101010187 +:1089E0000201010101010102010101010101010175 +:1089F0000202020202010101000101010101010262 +:108A0000010101010101000000010001000000005E +:108A10000001010100000000020002020202020245 +:108A2000020200000002020202020202020202022C +:108A30000202020202020202020202020002020218 +:108A40000202020202020202020202020202020206 +:108A500002020202020202020202020202020202F6 +:108A600002020202020202020202020202020202E6 +:108A700002020202020202020202020202020202D6 +:108A800002020202020202020202020202020202C6 +:108A900002020202020202020202020202020202B6 +:108AA00002020202020202020202000200000002AE +:108AB00002020200000000010101010101010101A7 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101000101010101010187 +:108AE0000101010101000002010101010101010177 +:108AF0000202020101020201020101010101010160 +:108B0000010100000202020202020002020002024F +:108B1000020000020202020002020202020202023B +:108B20000202020202020202020202020202020225 +:108B30000202020202020202020202020002020217 +:108B40000202020202020202020202020202020205 +:108B500002020202020202020202020202020202F5 +:108B600002020202020202020202020202020202E5 +:108B700002020202020202020202020202020202D5 +:108B800002020202020202020202020202020202C5 +:108B900002020202020202020202020202020202B5 +:108BA00002020202020202020202000200000000AF +:108BB00000000000000000010101010101010101AC +:108BC0000101010101010102020201010101010192 +:108BD000010101010202020100000000000000008A +:108BE000000000000100000101010101010101017B +:108BF000010101010101010202020202020202025C +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202020202020202020202C4 +:108C900002020202020202020202020202020202B4 +:108CA00002020202020202020202000000000000B0 +:108CB00000000000000000010101010101010101AB +:108CC0000101010101010101010101010101010194 +:108CD000010101010101010002000000000000008B +:108CE0000000000002020201010101010101010076 +:108CF0000101010101020202020202020202020259 +:108D00000202020202020202020202020202020243 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202020202D3 +:108D800002020202020202020202020202020202C3 +:108D900002020202020202020202020202020202B3 +:108DA00002020202020202020200000000000000B1 +:108DB00000000000000000010101010101010101AA +:108DC0000101010101010100000000000101000199 +:108DD0000001000000000002020202020202020280 +:108DE000020202020202020102020101010102006A +:108DF0000202020101020202020202020202020255 +:108E00000202020202020202020202020202020242 +:108E10000202020202020202020202020202020232 +:108E20000202020202020202020202020202020222 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202020202020202020202C2 +:108E900002020202020202020202020202020202B2 +:108EA00002020202020202020200000000000000B0 +:108EB00000000000000000010101010101010101A9 +:108EC0000101010101010100000000000101000198 +:108ED000000100000000000202020202020202027F +:108EE0000202020202020202020202020202020262 +:108EF0000202020202020202020202020202020252 +:108F00000202020202020202020202020202020241 +:108F10000202020202020202020202020202020231 +:108F20000202020202020202020202020202020221 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202020202020202020202D1 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020200000000000000AF +:108FB00000000000000000010101010101010101A8 +:108FC0000101010101010102020202020202020288 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202020202020261 +:108FF0000202020202020202020202020202020251 +:109000000202020202020202020202020202020240 +:109010000202020202020202020202020202020230 +:109020000202020202020202020202020202020220 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020202020200000000000000AE +:1090B00000000000000000010101010101010101A7 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101020000000000000000B6 +:1091B00000000000000000010101010101010101A6 +:1091C0000101010101010100000000000000000098 +:1091D0000000000000000001010101010101010186 +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101000000000000000000C7 +:1092A00000000000000000020000000000000000BC +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B000000000000000003300000000000000007A +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:109430000002000000000000000000000202000026 +:10944000000000000000000000000002000000001A +:10945000000000000000000000000000000000000C +:1094600002000200000000000000000002020000F4 +:1094700000000100000000000000000200000200E7 +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:109530000002000000000000000000000202000025 +:109540000000020000000000000000020200000015 +:10955000000000000000000000000000000000000B +:1095600002000200000000020000000002020200EF +:1095700000010200000002000000000200000200E2 +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000002A9 +:1095C000000000000000000000000000000000009B +:1095D0000000000001000000000200000000020086 +:1095E000000000000000000000000000000000007B +:1095F0000000000000000000000000000000020069 +:109600000002000000000000000200000002020052 +:109610000000010000000000000000020000020045 +:109620000000020000000000000000000002000036 +:109630000002000000000000000000000202000222 +:109640000200020000020000000000020200000010 +:10965000000000000000000000000000000000000A +:1096600002010201000000020000000002020200EC +:1096700002020200020002000000000200000200DC +:1096800000010000000000000000000002020002D3 +:1096900002000200020000000002000200000202BC +:1096A00002000200000000000000000200000200B2 +:1096B00000020200000000000000000000000002A4 +:1096C000000000000000000000000000000000009A +:1096D000000000020101020202020000000202007A +:1096E0000000000000000000000000000000020078 +:1096F0000000000000000000000000000000020068 +:10970000000200000000000000020000020202004F +:109710000001010000000000000000020000020241 +:109720000002020000000000000000000002000231 +:10973000020200000100000000000000020202021C +:10974000020002000102020000000002020200000A +:109750000000000000000000000000000000000207 +:1097600002020202000000020000000002020200E9 +:1097700002020202020202000200000200000200D5 +:1097800002020100010000000000000202020202C9 +:1097900002020202020202020202020202020202A9 +:1097A00002020202000002000000000202020200A7 +:1097B0000202020202000002000200000000000299 +:1097C0000000000000000000000000000000000099 +:1097D0000000000201010202020200000002020079 +:1097E0000000000000000000000000000000020077 +:1097F0000000000000000000000000000000020067 +:10980000000200000100000000020000020202004D +:10981000000101000100000000020002000002023D +:10982000000202000200020000000000000200022C +:109830000202000101010000020000000202020217 +:109840000200020001020200000200020202020005 +:109850000000000000000000000000000000000206 +:1098600002020202000202020200000002020202E0 +:1098700002020202020202000202000200000200D2 +:1098800002020202020002000200000202020202C0 +:1098900002020202020202020202020202020202A8 +:1098A00002020202020002000002000202020200A2 +:1098B0000202020202020202000200000000000294 +:1098C0000000000000000000000000000000000098 +:1098D0000001000202010202020200000002020076 +:1098E0000100000000000000000000000000020075 +:1098F0000000000000000000000000000000020066 +:109900000002000201000002000200000202020048 +:109910000001020001000000000202020000020239 +:109920000002020202000200000000020202020223 +:109930000202000102010000020200020202020211 +:109940000202020201020200000200020202020000 +:109950000000000000000000000000000000000205 +:1099600002020202020202020202000002020202DB +:1099700002020202020202020202020200000202CB +:1099800002020202020002000202000202020202BD +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020099 +:1099B0000202020202020202020200000000000291 +:1099C0000000000000000000000000000000000097 +:1099D0000002000202020202020200000002020073 +:1099E0000100000000000000000000000000020074 +:1099F0000000000000000000000000000000020065 +:109A00000002000201000002000200000202020245 +:109A10000102020001000000000202020000020236 +:109A20000102020202010200000000020202020220 +:109A3000020200020202000202020202020202020A +:109A400002020202020202000202000202020202FA +:109A50000200000000000000000000000000000202 +:109A600002020202020202020202020002020202D8 +:109A700002020202020202020202020200000202CA +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020202A6 +:109AA0000202020202020202020202020202020098 +:109AB000020202020202020202020200000000028E +:109AC0000000000000000000000000000000000096 +:109AD0000002000202020202020200000002020072 +:109AE0000100000000000000000000000000020073 +:109AF0000000000000000000000000000000020064 +:109B00000102000202010002000200000202020241 +:109B10000202020002000000000202020000020233 +:109B2000020202020201020002020002020202021A +:109B30000202010202020002020202020202020208 +:109B400002020202020202000202000202020202F9 +:109B50000201000000000000000000000000000200 +:109B600002020202020202020202020002020202D7 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020202A5 +:109BA0000202020202020202020202020202020097 +:109BB000020202020202020202020202000000028B +:109BC0000200000000000000000000000002000091 +:109BD0000002000202020202020200000002020071 +:109BE0000200000000000000000000000000020071 +:109BF000010001000000000000000000000002025F +:109C00000102000202010002000200000202020240 +:109C10000202020002000000000202020000020232 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202000202000202020202F8 +:109C500002020000000000000000000000000202FC +:109C600002020202020202020202020002020202D6 +:109C700002020202020202020202020202020102C5 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020102020102A6 +:109CA0000202020202020202020202020202020096 +:109CB0000202020202020202020202020202000286 +:109CC0000200000000000000000000000002000090 +:109CD0000002000202020202020200000002020070 +:109CE0000200000000000000000000000000020070 +:109CF000010101000000000000000000000002025D +:109D0000020200020202000200020000020202023D +:109D1000020202010201000000020202000002022F +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020200000002000000000000000202F7 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020102020102C5 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020101010102A7 +:109DA0000202020202020202020202020202020095 +:109DB0000101010101010101010101010101000293 +:109DC000020000000000000002000000020200008B +:109DD000000200020202020202020000000202006F +:109DE000020000010000000000000000000002026C +:109DF000020101000000000000000000000002025B +:109E0000020200020202000200020000020202023C +:109E1000020202020202000000020202000002022C +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020000000200000202EC +:109E600002020202020202020202020201010102D5 +:109E700002020202020202020202020102020102C4 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020101010102A6 +:109EA0000202020202020202020202020202010095 +:109EB0000101010101010101010101010101000292 +:109EC000020000000000000002000000020200008A +:109ED000000200020202020202020000020202026A +:109EE000020000010000000000000000000002026B +:109EF0000201020000000000000000000000020259 +:109F0000020200020202000200020000020202023B +:109F10000202020202020200000202020000020229 +:109F20000202020202020202020202020202020211 +:109F30000202020202020202020202020202020201 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020000000200000202EB +:109F600002020202020202020202020201010102D4 +:109F700002020202020202020202020102020102C3 +:109F800002020202020202020202020201010102B4 +:109F900002020202020202020201010101010102A7 +:109FA0000202020202020202020202010101010097 +:109FB0000101010101010101010101010101000291 +:109FC0000202000000000000020002000202000184 +:109FD0000002010202020202020200000202020268 +:109FE000020000010000000000000000000002026A +:109FF0000202020000000000000000020000020255 +:10A00000020200020202000200020000020202023A +:10A010000202020202020200000202020000020228 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020101020202 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202000200000202E6 +:10A0600002020202020202020202020201010102D3 +:10A0700002020202020202020202020102020102C2 +:10A0800002020202020202020202020101010102B4 +:10A0900002020202020202010101010101010102A8 +:10A0A0000202020202020202020202010101010096 +:10A0B0000101010101010101010101010101000290 +:10A0C0000202000000000000020002000202000282 +:10A0D0000002020202020202020200000202020266 +:10A0E0000200000200000000000000000000020268 +:10A0F0000202020100000000000000020000020253 +:10A100000202000202020002000200000202020239 +:10A110000202020202020202020202020000020223 +:10A120000202020202020202020202020201020210 +:10A130000202020202020202020202020101010202 +:10A1400002020202020202020202020101020202F1 +:10A1500002020202020202020202020200000202E3 +:10A1600002020202020202020202020201010102D2 +:10A1700002020202020202020202020101010102C3 +:10A1800002020202020202020202020101010102B3 +:10A1900002020202010102010101010101010102A9 +:10A1A0000202020202020202020202010101010095 +:10A1B000010101010101010101010101010101028E +:10A1C0000202020000000200020202020202000279 +:10A1D0000002020202020202020200020202010264 +:10A1E0000200000200000000000000000000020267 +:10A1F0000202020100000000000000020000020252 +:10A200000202000202020002000200020102010238 +:10A210000202020202020202020202020000010223 +:10A220000202020202020202020202020201010210 +:10A230000202020202020202020202020101010201 +:10A2400002020202020202020202020101010102F2 +:10A2500002020202020202020202020200000202E2 +:10A2600002020202020202020202020201010102D1 +:10A2700002020202020201020101010101010102C6 +:10A2800002020202020202020202020101010102B2 +:10A2900002020101010101010101010101010102AB +:10A2A0000202020202020202020202010101010094 +:10A2B000000000000000000000000000000101029A +:10A2C000020202000000020001020202020100027A +:10A2D0000002020202020202020200020201010264 +:10A2E0000200000200000000000000000000020266 +:10A2F0000202020200000000000000020000010251 +:10A300000202000202020002000200020101010238 +:10A310000202020202020202020202010000010223 +:10A320000202020202020202020202020101010210 +:10A330000202020202020202020202010101010201 +:10A3400002020202020202020202020101010102F1 +:10A3500002020202020202020202020200020102E0 +:10A3600002020202020202010202020201010102D1 +:10A3700002020202010101010101010101010102C8 +:10A3800002020202020202020202020101010102B1 +:10A3900002010101010101010101010101010102AB +:10A3A0000202020202020202020101010101010095 +:10A3B0000000000000000000000100000001010199 +:10A3C000020202000000020001020102010100027B +:10A3D0000102020202020202020200020201010262 +:10A3E0000200000200010000000000000000010265 +:10A3F0000202020200000000000000020000010250 +:10A400000202020202020002000200020101010235 +:10A410000202020202020202020202010000010222 +:10A420000202020202020202020202010101010210 +:10A430000202020202020202020202010101010200 +:10A4400002020202020202020202020101010102F0 +:10A4500002020202020202020202020200020102DF +:10A4600002020202020202010101010101010102D4 +:10A4700002020101010101010101010101010102C9 +:10A4800002020202020202020101010101010102B3 +:10A4900001010101010101010101010101010102AB +:10A4A0000202010202020101010101010101010098 +:10A4B0000000000000000001000101010101010194 +:10A4C000020202000000020001020102010100027A +:10A4D0000102020202020202020200020201010261 +:10A4E0000200010201010000000000000000010262 +:10A4F0000202020200000200000000020202010249 +:10A500000202020202020002000202020101010232 +:10A510000202020202020202020202010000010221 +:10A52000020202020202020202020201010101020F +:10A530000202020202020202010102010101010201 +:10A5400002020202020202020201020101010102F0 +:10A5500002020202020202020202020202020102DC +:10A5600002020102020101010101010101010102D6 +:10A5700002010101010101010101010101010102C9 +:10A5800002020202020201010101010101010102B4 +:10A5900001010101010101010101010101010102AA +:10A5A000020201010101010101010101010101009A +:10A5B0000000000000000001000101010101010193 +:10A5C0000202020200020202010101020101000274 +:10A5D000020202020202020202020002020101025F +:10A5E0000200010201020000000000000000010260 +:10A5F0000202020200000200000000020202010248 +:10A600000202020202020002020102020101010230 +:10A610000202020202020202020101010200010220 +:10A62000020202020202020202020201010101020E +:10A630000201020202020202010101010101010202 +:10A6400002020202020101020201020101010102F1 +:10A6500002020202020202020202020102020102DC +:10A6600002020101010101010101010101010102D7 +:10A6700001010101010101010101010101010102C9 +:10A6800002020201010101010101010101010102B6 +:10A6900001010101010101010101010101010102A9 +:10A6A000020101010101010101010101010101009A +:10A6B0000000000000000001010101010101010191 +:10A6C0000202020200020102020102010101000273 +:10A6D0000202020202020202020100020101010260 +:10A6E000020002020202000000000002000001025B +:10A6F0000202020200000200000000020202010247 +:10A700000202020202020001020102020101010230 +:10A71000020202020202020202010101020001021F +:10A72000020202020102020202020201010101020E +:10A730000201020202020201010101010101010202 +:10A7400002020102020101020101020101010102F2 +:10A7500002020202020202020202020102020102DB +:10A7600001010101010101010101010101010102D8 +:10A7700001010101010101010101010101010102C8 +:10A7800002010101010101010101010101010101B8 +:10A7900001010101010101010101010101010102A8 +:10A7A000010101010101010101010101010101009A +:10A7B000000000000000010101010101010101018F +:10A7C0000102020202020102020102010101000271 +:10A7D0000202020202020201010100020101010261 +:10A7E000020002020202000000000002000001025A +:10A7F0000202020200000200000200020202010244 +:10A800000201020202020001020102020101010230 +:10A81000020202020202020202010101020001021E +:10A820000202010101020102010101010101010213 +:10A830000201020202020201010101010101010201 +:10A8400002020101020101020101010101010102F3 +:10A8500002020202020202020202020102010102DB +:10A8600001010101010101010101010101010102D7 +:10A8700001010101010101010101010101010102C7 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010102A7 +:10A8A0000101010101010101010101010101010099 +:10A8B000000000000101010101010101010101018C +:10A8C000010202020202010202020201010100026F +:10A8D0000202020102020101010100010101010263 +:10A8E0000200020202020000000000020000010259 +:10A8F000020202020002020002020201020201023E +:10A900000201020102020001020102010101010231 +:10A91000020202020202020202010101020201021B +:10A920000201010101020101010101010101010214 +:10A930000101020201010101010101010101010204 +:10A9400001010101020101010101010101010102F5 +:10A9500002020202020101010201010101010102E0 +:10A9600001010101010101010101010101010102D6 +:10A9700001010101010101010101010101010102C6 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010102A6 +:10A9A0000101010101010101010101010101010098 +:10A9B0000000010101010101010101010100010289 +:10A9C000010202020202020202020101010100026E +:10A9D0000202020102020101010100010101010262 +:10A9E0000200020202020200000000020000010256 +:10A9F000020202020202020002020201020201023B +:10AA00000201020102020001020102010101010230 +:10AA1000020202020202020202010101020201021A +:10AA20000201010101010101010101010101010214 +:10AA30000101020101010101010101010101010204 +:10AA400001010101020101010101010101010102F4 +:10AA500002020202010101010101010101010101E2 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010102C5 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010097 +:10AAB0000101010101010001010100010100010288 +:10AAC0000201020202010201010201010101000270 +:10AAD0000202020102020101010100010101010261 +:10AAE0000200020202020200000000020000010255 +:10AAF000020202020202020202020201010101023A +:10AB0000020102010202020102010201010101022D +:10AB1000020202020202020202010101010201021A +:10AB20000201010101010101010101010101010213 +:10AB30000101010101010101010101010101010204 +:10AB400001010101010101010101010101010102F4 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010102C4 +:10AB800001010101010101010101010101010101B5 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010096 +:10ABB0000001010101010001010100010100010288 +:10ABC0000201010202020201010101010101000270 +:10ABD0000201020101010101010100010101010263 +:10ABE000020202020202020000000002020201024E +:10ABF0000202020202020202020202010101010239 +:10AC0000020102010101020102010201010101022E +:10AC10000202010201010101010101010102010120 +:10AC20000201010101010101010101010101010113 +:10AC30000101010101010101010101010101010104 +:10AC400001010101010101010101010101010102F3 +:10AC500001010101010101010101010101010101E4 +:10AC600001010101010101010101010101010101D4 +:10AC700001010101010101010101010101010101C4 +:10AC800001010101010101010101010101010101B4 +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010095 +:10ACB0000001010101010001000100010000010289 +:10ACC0000201010102010101010101010101000272 +:10ACD0000201020101010101010100010101010262 +:10ACE000020202020202020000020001020201024C +:10ACF0000202020202020202020202010101010238 +:10AD0000020102010101020102010101010101022E +:10AD10000201010101010101010101010101010122 +:10AD20000101010101010101010101010101010113 +:10AD30000101010101010101010101010101010103 +:10AD400001010101010101010101010101010102F2 +:10AD500001010101010101010101010101010101E3 +:10AD600001010101010101010101010101010101D3 +:10AD700001010101010101010101010101010101C3 +:10AD800001010101010101010101010101010101B3 +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010094 +:10ADB000000101010000000100010001000000028B +:10ADC0000101010101010101010101010101000273 +:10ADD0000201020101010101010100010101010261 +:10ADE0000202020202020200020200010202010249 +:10ADF0000202020202020202020202010101010237 +:10AE0000020102010101020102010101010101022D +:10AE10000101010101010101010101010101010122 +:10AE20000101010101010101010101010101010112 +:10AE30000101010101010101010101010101010102 +:10AE400001010101010101010101010101010101F2 +:10AE500001010101010101010101010101010101E2 +:10AE600001010101010101010101010101010101D2 +:10AE700001010101010101010101010101010101C2 +:10AE800001010101010101010101010101010101B2 +:10AE900001010101010101010101010101010101A2 +:10AEA0000101010101010101010101010101010093 +:10AEB000000101000000000000000000000000028E +:10AEC0000101010101010101010101010101000272 +:10AED0000201010101010101010100010101010261 +:10AEE000020202020202020002020001010101024A +:10AEF0000202020202020202020202010101010236 +:10AF0000020102010101020101010101010101012E +:10AF10000101010101010101010101010101010121 +:10AF20000101010101010101010101010101010111 +:10AF30000101010101010101010101010101010101 +:10AF400001010101010101010101010101010101F1 +:10AF500001010101010101010101010101010101E1 +:10AF600001010101010101010101010101010101D1 +:10AF700001010101010101010101010101010101C1 +:10AF800001010101010101010101010101010101B1 +:10AF900001010101010101010101010101010101A1 +:10AFA0000101010101010101010101010101010092 +:10AFB0000000000000000000000000000000000190 +:10AFC0000101010101010101010101010000000273 +:10AFD0000201010101010101010100010101010260 +:10AFE0000202020202020202020202010101010245 +:10AFF000020201020202010202010101010101013A +:10B00000010101010101020101010101010101012F +:10B010000101010101010101010101010101010120 +:10B020000101010101010101010101010101010110 +:10B030000101010101010101010101010101010100 +:10B0400001010101010101010101010101010101F0 +:10B0500001010101010101010101010101010101E0 +:10B0600001010101010101010101010101010101D0 +:10B0700001010101010101010101010101010101C0 +:10B0800001010101010101010101010101010101B0 +:10B0900001010101010101010101010101010101A0 +:10B0A0000101010101010101010101010101010091 +:10B0B000000000000000000000000000000000018F +:10B0C0000101010101010101010101010000000272 +:10B0D000020101010101010101010001010101025F +:10B0E0000102020102020202020202010101010246 +:10B0F000010101010202010201010101010101013D +:10B10000010101010101020101010101010101012E +:10B11000010101010101010101010101010101011F +:10B12000010101010101010101010101010101010F +:10B1300001010101010101010101010101010101FF +:10B1400001010101010101010101010101010101EF +:10B1500001010101010101010101010101010101DF +:10B1600001010101010101010101010101010101CF +:10B1700001010101010101010101010101010101BF +:10B1800001010101010101010101010101010101AF +:10B1900001010101010101010101010001010101A0 +:10B1A0000101010101010101010101010101010090 +:10B1B000000000000000000000000000000000018E +:10B1C0000101010101010101010101000000010271 +:10B1D000020101010101010101010001010101025E +:10B1E0000102020102010202020202010101010147 +:10B1F000010101010201010101010101010101013E +:10B20000010101010101020101010101010101012D +:10B21000010101010101010101010101010101011E +:10B22000010101010101010101010101010101010E +:10B2300001010101010101010101010101010101FE +:10B2400001010101010101010101010101010101EE +:10B2500001010101010101010101010101010101DE +:10B2600001010101010101010101010101010101CE +:10B2700001010101010101010101010101010101BE +:10B2800001010101010101010101010101010101AE +:10B2900000000000000001000000000200000001AA +:10B2A000010101010101010101010101010101028D +:10B2B000020202020202020202020202020202016F +:10B2C0000101010101010101010100000000010271 +:10B2D000020101010101010101010201010101015C +:10B2E0000102020101010102020102010101010149 +:10B2F000010101010101010101010101010101013E +:10B30000010101010101010101010101010101012D +:10B31000010101010101010101010101010101011D +:10B32000010101010101010101010101010101010D +:10B3300001010101010101010101010101010101FD +:10B3400001010101010101010101010101010101ED +:10B3500001010101010101010101010101010101DD +:10B3600001010101010101010101010101010101CD +:10B3700001010101010101010101010001010001BF +:10B3800001010101010101010101010101010100AE +:10B390000202020202020002020202020202020190 +:10B3A000010101010101010101010101010101028C +:10B3B000020202020202020202020202020202016E +:10B3C0000100010101010100000100000000010174 +:10B3D000020101010101010101010101010101015C +:10B3E000010201010101010201010101010101014B +:10B3F000010101010101010101010101010101013D +:10B40000010101010101010101010101010101012C +:10B41000010101010101010101010101010101011C +:10B42000010101010101010101010101010101010C +:10B4300001010101010101010101010101010101FC +:10B4400001010101010101010101010101010101EC +:10B4500001010101010101010101010101010101DC +:10B4600001010101010101010101010101010101CC +:10B4700000000000000000000000000000000001CB +:10B4800001010101010101010101010101010102AB +:10B49000020202020202020202020202020202018D +:10B4A000010101010101010101010101010101028B +:10B4B000020202020202020202020202020202016D +:10B4C0000100000001000000000000000000010178 +:10B4D000010101010101010101010101010101015C +:10B4E000010201010101010101010101010101014B +:10B4F000010101010101010101010101010101013C +:10B50000010101010101010101010101010101012B +:10B51000010101010101010101010101010101011B +:10B52000010101010101010101010101010101010B +:10B5300001010101010101010101010101010101FB +:10B5400001010101010101010101010101010101EB +:10B5500001010101010101010101010101010101DB +:10B5600001010101010101010101010101010100CC +:10B5700000000000000000000000000000000001CA +:10B5800001010101010101010101010000000002AE +:10B59000020202020202020202020202020202018C +:10B5A0000101020101010101010101020202020285 +:10B5B000020202020202020202020202020202016C +:10B5C0000000000000000000000000000000010179 +:10B5D000010101010101010101010101010101015B +:10B5E000010101010101010101010101010101014B +:10B5F000010101010101010101010101010101013B +:10B60000010101010101010101010101010101012A +:10B61000010101010101010101010101010101011A +:10B62000010101010101010101010101010101010A +:10B6300001010101010101010101010101010101FA +:10B6400001010101010101010101010101010101EA +:10B6500001010101010101010101010101010100DB +:10B6600001010101010101010101010100000000CE +:10B6700000000000000000000000000000000001C9 +:10B6800000000000000000000000000202020202B0 +:10B69000020202020202020202020202020202018B +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202006C +:10B6C0000000000000000000000000000000010178 +:10B6D000010101010101010101010101010101015A +:10B6E000010101010101010101010101010101014A +:10B6F000010101010101010101010101010101013A +:10B700000101010101010101010101010101010129 +:10B710000101010101010101010101010101010119 +:10B720000101010101010101010101010101010109 +:10B7300001010101010101010101010101010101F9 +:10B7400001010101010101010101010101010101E9 +:10B7500001010101010101010101010101010100DA +:10B7600001000100000000010000000000000000D6 +:10B7700000000000000000000000000000000000C9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B000020202020202020202020202020202006B +:10B7C0000000000000000000000000000000010177 +:10B7D0000101010101010101010101010101010159 +:10B7E0000101010101010101010101010101010149 +:10B7F0000101010101010101010101010101010139 +:10B800000101010101010101010101010101010128 +:10B810000101010101010101010101010101010118 +:10B820000101010101010101010101010101010108 +:10B8300001010101010101010101010101010101F8 +:10B8400001010101010101010101010101010101E8 +:10B8500001010101010001010101010101010000DB +:10B8600002000100000000010000000000000000D4 +:10B8700000000000000000000000000200000202C2 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B000020202020202020202020202020202006A +:10B8C0000000000000000000000000000101010174 +:10B8D0000101010101010101010101010101010158 +:10B8E0000101010101010101010101010101010148 +:10B8F0000101010101010101010101010101010138 +:10B900000101010101010101010101010201010126 +:10B910000101010101010101010101010101010216 +:10B920000101010202010101010101010100000107 +:10B9300002020101010101010202010201010101F2 +:10B9400000000100010100010100010101010101EC +:10B9500000000101000000010100000100000000E2 +:10B9600001000200000000020000000002020200CC +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020069 +:10B9C0000000000000000000000000010101010172 +:10B9D0000101010101010101010101010101010157 +:10B9E0000101010101010101010101010101010147 +:10B9F0000101010101010101010101010101010137 +:10BA00000102010101010101010101010201010124 +:10BA10000101010101010101010101010101010215 +:10BA2000010101010100010101010101000000010A +:10BA300001020101010101010101010202020201F1 +:10BA400000000200010200010000010000000001EE +:10BA500000000202000000020000000000000000E0 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020068 +:10BAC0000000000000000000000000010101010171 +:10BAD0000101010101010101010101010101010156 +:10BAE0000101010101010101010101010101010146 +:10BAF0000101010101010101010101010101010136 +:10BB00000102010201010102010101020201010120 +:10BB10000101010101010101010101010101010214 +:10BB2000000101000000010102010100000000020B +:10BB300000010202020202010000010101010100F4 +:10BB400000000100010100000000000202020200EA +:10BB500000000101000000010000000200000202DC +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020067 +:10BBC000000000000000000000000101010101016F +:10BBD0000101010101010101010101010101010155 +:10BBE0000101010101010101010101010101010145 +:10BBF0000101010101010101010101010101010135 +:10BC0000010201020101010201010102010102011F +:10BC10000101010101010101010000020101010115 +:10BC2000000000000000010101010100000000010E +:10BC300000010101010101020000020102020202F1 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020066 +:10BCC0000001010000000001010101010101010169 +:10BCD0000101010101010101010101010101010154 +:10BCE0000101010101010101010101010101010144 +:10BCF0000101010101010101010101010101010233 +:10BD0000010102010202010101010201010201011E +:10BD10000101010101010101010000010001020115 +:10BD200000020200000002020002020202020202FD +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020065 +:10BDC0000101010101010101010101010101010163 +:10BDD000010101010101010101010102020202014F +:10BDE0000101010101010101010101010101010143 +:10BDF0000101010101010101010101020202010130 +:10BE00000201010101010101020001010101000221 +:10BE10000202020202020202020202020202020103 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020002020202020200000169 +:10BEC0000101010101010101010101010101010162 +:10BED000010101010101010101010102020202014E +:10BEE000010101010101010101010102020201013F +:10BEF0000101010101010101010101010101020032 +:10BF00000101000000000000010200000002020226 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB000020202020202000202020002000000016C +:10BFC0000101010101010101010101010101010161 +:10BFD000010202020101010101010001010101014F +:10BFE000010101010101010101010101010102023F +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020200000002000200020000000171 +:10C0C0000101010101010101010101010101010160 +:10C0D0000101010101010101010100010101010250 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B0000202020000000002000200000000000174 +:10C1C000010101010101010101010101010101025E +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000000000000000000000000000000000017D +:10C2C000010101010101010101010101010101025D +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000000000000000000000000000000000017C +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101010C +:10C4200001010101010101010101010101010101FC +:10C4300001010101010101010101010101010101EC +:10C4400001010101010101010101010101010101DC +:10C4500001010101010101010101010101010101CC +:10C4600001010101010101010101010101010101BC +:10C4700001010101010101010101010101010101AC +:10C48000010101010101010101010101010101019C +:10C49000010101010101010101010101010101018C +:10C4A000010101010101010101010101010101027B +:10C4B000000000000000000000000000000000017B +:10C4C000010101010101010101010101010101015C +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010101010101010101013C +:10C4F000010101010101010101010101010101012C +:10C50000010101010101010101010101010101011B +:10C51000010101010101010101010101010101010B +:10C5200001010101010101010101010101010101FB +:10C5300001010101010101010101010101010101EB +:10C5400001010101010101010101010101010101DB +:10C5500001010101010101010101010101010101CB +:10C5600001010101010101010101010101010101BB +:10C5700001010101010101010101010101010101AB +:10C58000010101010101010101010101010101019B +:10C59000010101010101010101010101010101008C +:10C5A0000000000000000000000000000000000289 +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B0000000000000000000000000000000003347 +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000020000000000000017 +:10C720000000000200000000000000000000000007 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000200010000000000C6 +:10C7700000000000000200000000000000000000B7 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000020000000000000016 +:10C820000000000200020200000000000000000002 +:10C8300000000000000000000200000000000000F6 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000200020000020000C2 +:10C8700000000000000202000000000000000000B4 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000200000000000076 +:10C8C0000000000000000002000000000000000066 +:10C8D0000000000000000000000000010000020055 +:10C8E0000200020200000000000000000000000042 +:10C8F0000000000002000000000000000000000036 +:10C900000000000002000000000000000000000025 +:10C910000000000000000000020000000000000015 +:10C9200002000002000202000000000000000000FF +:10C9300000000000000000000200000000000000F5 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000020200020000020200BD +:10C9700000000000000202000000000000000200B1 +:10C98000000000000002000200000200000200009F +:10C990000000000000000200000000000000000095 +:10C9A0000000000000000002000000000002000083 +:10C9B000000200000000020000020002000000006F +:10C9C0000000000000000002000000000000000065 +:10C9D000000000000000000000000001020202024E +:10C9E000020202020000000000000000000000003F +:10C9F0000000000002000200000000000000000033 +:10CA00000000000002000200000000000000000022 +:10CA10000000000000000202020000000000000010 +:10CA200002020002000202000000000000000000FC +:10CA300000000000000000000200000000000000F4 +:10CA400000000000000000010000000000000000E5 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000020200020000020202BA +:10CA700000000000020202000000000000020202AA +:10CA80000000000000020202000202020002020096 +:10CA90000000000000020200010202020000020089 +:10CAA0000000000000020002020202020002020076 +:10CAB0000002000002020200000202020000000068 +:10CAC0000000000000000002000000000000000064 +:10CAD000000000000000000000000001020202024D +:10CAE000020202020000000000000000000000003E +:10CAF0000000000002000200000000000000000032 +:10CB00000000000002000200000000000000000021 +:10CB1000000000000000020202010000000000000E +:10CB200002020002000202000000000000000000FB +:10CB300000000000000000000200000000000000F3 +:10CB400000000000000000020000000000000000E3 +:10CB500000000000000000000000000000020000D3 +:10CB600000000000000000020202020200020202B5 +:10CB700002000200020202000100020000020202A2 +:10CB80000000000000020202000202020202020291 +:10CB9000000000000002020202020202020202027F +:10CBA000000000000002020202020202020202026F +:10CBB0000002000002020200000202020202000063 +:10CBC0000002000000000002000000000000000061 +:10CBD000000000000000000000000002020202024B +:10CBE000020202020000000000000000000000003D +:10CBF0000000000002000201000000000000000030 +:10CC0000000000000200020200000000000000001E +:10CC10000000000000000202020101000102000009 +:10CC200002020002000202000000000000000000FA +:10CC300000000000000000000200000000000000F2 +:10CC400000000000000000020000000000000000E2 +:10CC500000000000000000000000000100020000D1 +:10CC600000000000000000020202020202020202B2 +:10CC7000020202000202020202000200020202029A +:10CC8000000200000002020202020202020202028C +:10CC9000020002000002020202020202020202027A +:10CCA000020000000002020202020202020202026C +:10CCB0000202020202020200000202020202020258 +:10CCC000000200020000000202000000000000005C +:10CCD000000000000000000000000002020202024A +:10CCE000020202020000000000000000000000003C +:10CCF000000000000200020200000000000000002E +:10CD0000000000000200020201000100000000001B +:10CD10000000000000000202020201000102000007 +:10CD200002020002000202000000000000000000F9 +:10CD300000000000000000000200000000000000F1 +:10CD400000000000000000020000000000000000E1 +:10CD500000000000000000000102000200020002CA +:10CD600000000000000202020202020202020202AD +:10CD70000202020202020202020202020202020293 +:10CD80000202020200020202020202020202020285 +:10CD90000202020000020202020202020202020277 +:10CDA0000202000000020202020202020202020269 +:10CDB0000202020202020200000202020202020257 +:10CDC0000202000200000002020000000000000059 +:10CDD0000000000000000000000000020202020249 +:10CDE0000202020200000202000000000000000037 +:10CDF000000000000200020200000000000000002D +:10CE00000000000002000202010001000100000019 +:10CE10000000000000000202020202000202000004 +:10CE200002020002000202000000000000000000F8 +:10CE300000000000000000000200000000000000F0 +:10CE400000000000000000020000000000000000E0 +:10CE500000000000000000000202000200020202C6 +:10CE600000000000000202020202020202020202AC +:10CE70000202020202020202020202020202020292 +:10CE80000202020200020202020202020202020284 +:10CE90000202020200020202020202020202020274 +:10CEA0000202020200020202020202020202020264 +:10CEB0000202020202020200000202020202020256 +:10CEC0000202020200000002020000000000000056 +:10CED0000000000000020000000101020202020244 +:10CEE0000202020200000202000100010000000034 +:10CEF000000000000200020200000000000000002C +:10CF00000000000002000202010102000100000016 +:10CF10000000000000000202020202010202020000 +:10CF200002020002000202000000000000000000F7 +:10CF300000000000000000020200000000010000EC +:10CF400000000000000000020200000000010000DC +:10CF500000000000000000020202000202020202C1 +:10CF600000020000000202020202020202020202A9 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020200020202020202020202020273 +:10CFA0000202020200020202020202020202020263 +:10CFB0000202020202020200000202020202020255 +:10CFC0000202020202000002020000000000000053 +:10CFD0000000000000020000000101020202020243 +:10CFE0000202020200000202000100010000000033 +:10CFF000000000000200020200000000000000002B +:10D000000000000002000202020102000200000013 +:10D0100000000000000002020202020202020202FC +:10D0200002020002000202000000000000000000F6 +:10D0300000000000000000020200000000020000EA +:10D0400000000000000000020200000000010000DB +:10D0500000000000000000020202020202020202BE +:10D0600002020200000202020202020202020202A4 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020200000202020202020254 +:10D0C0000202020202020002020000000000000050 +:10D0D0000000000000020000010101020202020241 +:10D0E0000202020200000202000100010000000032 +:10D0F000000000000200020200000000000000002A +:10D100000000000002000202020202000200000011 +:10D1100000000000020002020202020202020202F9 +:10D1200002020002000202000000000000000000F5 +:10D1300000000000000000020202020000020000E5 +:10D1400000000000000000020200000000010000DA +:10D1500000000000000000020202020202020202BD +:10D1600002020200000202020202020202020202A3 +:10D170000202020202010102020202020202020291 +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202010000010101010101015B +:10D1C0000101010101010002020000000000000055 +:10D1D000000000000002000101020202020202023D +:10D1E000020202020000020200020002000000002F +:10D1F0000000000002000202000000000000000029 +:10D200000000000002000202020202000200000010 +:10D2100000000000020002020202020202020202F8 +:10D2200002020002000202000000000000000000F4 +:10D2300000000000000000020202020000020000E4 +:10D2400000000000000200020202000000020200D2 +:10D2500000000000000000020202020202020202BC +:10D2600002020202000202020202020202020202A0 +:10D270000202020202010102020202020202020290 +:10D280000202020202010102020202020202020280 +:10D29000020202020202010202020202020202026F +:10D2A000020202020202020202020202020202025E +:10D2B000020202020201010000010101010101015B +:10D2C0000101010101010002020002000000000052 +:10D2D000000000000002000202020202020202023A +:10D2E000020202020002020202020002000000002A +:10D2F0000000000002000202020000000000000026 +:10D30000000000000200020202020201020002000C +:10D3100000000000020002020202020202020202F7 +:10D3200002020002000202020000000000000000F1 +:10D3300000000000000000020202020200020000E1 +:10D3400000000000020202020202020100020200CA +:10D3500000000000000000020202020202020202BB +:10D36000020202020002020202020202020202029F +:10D37000020202020201010202020202020202028F +:10D38000020202020201010202020202020202027F +:10D39000020202020202010202020202020202026E +:10D3A000020202020202020202020202020202025D +:10D3B000020202020101010000010101010101015B +:10D3C0000101010101010102020002000000000050 +:10D3D0000000000000020002020202020202020239 +:10D3E0000202020200020202020200020000000029 +:10D3F0000000000002000202020000000000000025 +:10D400000000000002000202020202020200020208 +:10D4100000000000020002020202020202020202F6 +:10D4200002020002000201020201000000000000EE +:10D4300000000202000000020202020200020000DC +:10D4400000000000020202020202020200020202C6 +:10D4500000000002000002020202020202020202B6 +:10D46000020202020202020202020202020202029C +:10D47000020202020201010202020202020202028E +:10D48000020202020201010202020202020202027E +:10D49000020202020201010202020202020202026E +:10D4A000020202020201010202020202020202025E +:10D4B000020102020101010000010101010101015B +:10D4C000010101010101010202000200000000004F +:10D4D0000000020002020002020202020202020234 +:10D4E0000202020200020202020200020000000028 +:10D4F0000000000002000202020101000000000022 +:10D500000000000002000202020202020200020207 +:10D5100000000000020202020202020202020202F3 +:10D5200002020202000101020202000000000000EB +:10D5300000000202000000020202020202020202D5 +:10D5400000000202020202020202020200020202C1 +:10D5500000000002000002020202020202020202B5 +:10D56000020202020202010202020202020202029C +:10D57000020202020101010202020202020202028E +:10D58000020202020201010202020202020202027D +:10D59000020202020201010202020202020202026D +:10D5A000020202020201010202020202020202025D +:10D5B000020102020101010000010101010101015A +:10D5C000010101010101010202000200000000004E +:10D5D0000000020002010002020202020202020234 +:10D5E0000202020200020202020200020100000026 +:10D5F0000000000002000202020102000000000020 +:10D600000000000002000102020202020200020207 +:10D6100000000000020201020202020202020202F3 +:10D6200002020201000101020202000000000000EB +:10D6300000000202000000020202020202020202D4 +:10D6400002000202020202020202020202020202BC +:10D6500000020002000202020202020202020202B0 +:10D66000020202020201010202020202020202029C +:10D67000020201020101010202020202020202028E +:10D68000020202020201010202020202020202027C +:10D69000020202020201010202020202020202026C +:10D6A000020202020201010202020202020202025C +:10D6B0000201010101010100000000000000000062 +:10D6C0000001000100000101020002000000000052 +:10D6D0000000020002010002020202020202020233 +:10D6E0000202020200020202020200020100000025 +:10D6F000000000000200010202020200000000001F +:10D700000000000001000102020202020200020207 +:10D7100002000000020201020202020202020202F0 +:10D7200002020201000101020202000001000000E9 +:10D7300000000202000000020202020202020202D3 +:10D7400002020202020202020202020202020202B9 +:10D7500002020002000202020202020202020202AD +:10D76000020202020201010202020202020101019E +:10D770000101010101010102020202020202010192 +:10D78000020101010101010202020202020202027F +:10D79000020201020201010202020202020202026C +:10D7A000020202020201010202020202020101015E +:10D7B0000101010101010100000000000000000062 +:10D7C0000001010100010101010002000000000050 +:10D7D0000000010002010002020202020202020233 +:10D7E0000202020100020102020200020200000025 +:10D7F000000000000100010202020200000200001D +:10D800000000000001000102020202020200020206 +:10D8100002020000020201020202020202020202ED +:10D8200002020201000101020202000101000000E7 +:10D8300000000202000000020202020202020202D2 +:10D8400002020202020101020202020202020202BA +:10D8500002020202000202020202020202020202AA +:10D86000020202020201010202020202020101019D +:10D870000101010101010102020202020201010192 +:10D880000101010101010102020202020201010182 +:10D89000010101010101010202020202020202026F +:10D8A000020202020201010202020201010101015F +:10D8B0000101010101010100000000000000000061 +:10D8C0000001010101010101010202020002000246 +:10D8D0000200010002010002020202020202020230 +:10D8E0000202010100020102020200020200000025 +:10D8F000000000000100010202020200000200001C +:10D900000000000001000102020202020200020205 +:10D9100002020202020201020202020202020202E8 +:10D9200001010201020101020202000102000000E5 +:10D9300000000202000000020202020202020202D1 +:10D9400002020202020101020202020202020202B9 +:10D9500002020202000201020202020202020202AA +:10D96000020202020201010202020101010101019F +:10D970000101010101010102020202020101010192 +:10D980000101010101010102020202010101010183 +:10D990000101010101010102020202020202010170 +:10D9A0000101010101010102020101010101010165 +:10D9B000010101010101010000000000000001005F +:10D9C0000101010101010101010201020002000245 +:10D9D0000200010001010002020202020202020230 +:10D9E0000101010100020102020200020202000024 +:10D9F000000000000100010202020200010200001A +:10DA00000000000001000102020202020201020203 +:10DA100002020202020201020202020202020202E7 +:10DA200001010201020101020202020202000200DF +:10DA300000000202000000020202020202020202D0 +:10DA400002020202020101020202020202020202B8 +:10DA500002020202000201020202020202010201AB +:10DA600002010102020101020101010101010101A2 +:10DA70000101010101010102020201010101010193 +:10DA80000101010101010102020101010101010184 +:10DA90000101010101010102020202010101010172 +:10DAA0000101010101010102020101010101010164 +:10DAB000010101010101010000000001000001015C +:10DAC0000101010101010101010201020202020240 +:10DAD000020202020101000202020202020201012C +:10DAE0000101010102010102020202020202000020 +:10DAF0000000000001000102020202010202020015 +:10DB000000000000010201020202020202020202FF +:10DB100002020202010201020202020202020202E7 +:10DB200001010201020101020202020202020202DA +:10DB300000000202000002020102020202020202CE +:10DB400002020202010101020202020202020202B8 +:10DB500002020202020101020202020202010101AA +:10DB600001010101010101020101010101010101A4 +:10DB70000101010101010102020101010101010193 +:10DB80000101010101010102020101010101010183 +:10DB90000101010101010102020101010101010173 +:10DBA0000101010101010102020101010101010163 +:10DBB0000101010101010100000101010101010157 +:10DBC0000101010101010101010201020202020140 +:10DBD000010202020101000202020202010101012E +:10DBE000010101010201010202020202020200001F +:10DBF0000000000001000102020202020202020211 +:10DC000000000000010201020202020202020202FE +:10DC100002020202010101020102020202010202E9 +:10DC200001010201020101020202020202020202D9 +:10DC300000000202020002020102020202020202CB +:10DC400002020202010101020202020202020202B7 +:10DC500002020202020101020202020101010101AB +:10DC600001010101010101020101010101010101A3 +:10DC70000101010101010102020101010101010192 +:10DC80000101010101010102020101010101010182 +:10DC90000101010101010102020101010101010172 +:10DCA0000101010101010102010101010101010163 +:10DCB0000101010101010100000100010101010157 +:10DCC000010101010101010202020102020102013E +:10DCD000010102020101000202020202010101012E +:10DCE000010101010201010202020202020200001E +:10DCF0000000000001000102020202020202020210 +:10DD000000000000010201020202020202020202FD +:10DD100002020202010101020102020202010101EA +:10DD200001010201020101020202020202020202D8 +:10DD300000020101020002020102020202010202CB +:10DD400002020202010101020202020202020102B7 +:10DD500002020201020101020201020101010101AC +:10DD600001010101010101020101010101010101A2 +:10DD70000101010101010102020101010101010191 +:10DD80000101010101010102020101010101010181 +:10DD90000101010101010102020101010101010171 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010100000100010101010156 +:10DDC000010101010101010202020202020101013D +:10DDD000020101010101000202020202010101012E +:10DDE000010101010201010202020202020200021B +:10DDF000000000000100010202020202020202020F +:10DE000000000000010201020202020202020202FC +:10DE100002020202010101020102020201010101EA +:10DE200001010101020101020202020202020202D8 +:10DE300000020101020001020102020202010201CC +:10DE400001010101010101020202020202020101BB +:10DE500002010201020101020201010101010101AD +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010102010101010101010191 +:10DE80000101010101010102020101010101010180 +:10DE90000101010101010102020101010101010170 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010100000100010101000156 +:10DEC000010101010101010202020202020101023B +:10DED000020201010101000202020201010101012D +:10DEE0000101010102010102020202020202020218 +:10DEF000000000000100010202020202020202020E +:10DF000000000200010101020202020202020202FA +:10DF100002020202010101020101020101010101EB +:10DF200001010101010101020202020202020202D8 +:10DF300000020101020001020101020101010201CE +:10DF400001010101010101020102020202020101BB +:10DF500001010101010101020201010101010101AF +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010102010101010101010170 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010100000100010100000156 +:10DFC000000100010000010202020201020202023D +:10DFD000010201010101000202020201010101012D +:10DFE0000101010101010102020202020202020218 +:10DFF000000000000100010202020202020202020D +:10E0000000020200010101020202020201020101FA +:10E0100002020202010101010101010101010101EC +:10E0200001010101010101020202020202020202D7 +:10E0300002020101010001020101010101010101CE +:10E0400001010101010101010101010101020101BF +:10E0500001010101010101020101010101010101AF +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010100000000000000000059 +:10E0C0000001000000000002020102010102020240 +:10E0D000010101010101000202020201010101012D +:10E0E0000101010101010102020202020202020217 +:10E0F000000000000100010202020202020202020C +:10E1000002020202010101020202010201020101F6 +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101020202020202020202D6 +:10E1300002020101010001010101010101010101CE +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101020101010101010101AE +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B0000101010101010100020000000000000056 +:10E1C0000000000000000002010101010102010144 +:10E1D000010101010101000202020201010101012C +:10E1E0000101010101010102020202020202020216 +:10E1F0000002000001000102020202020202020209 +:10E2000002020202010101010201010101020101F8 +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101020101020202020202D7 +:10E2300002020101010001010101010101010101CD +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B0000101010101010100020000000000000055 +:10E2C0000000000000000001010101010101010145 +:10E2D000010101010100000202010101010101012E +:10E2E0000101010101010102020202010202020216 +:10E2F0000202000001020101020202020201020206 +:10E3000002020202010101010201010101020101F7 +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101020202020101D9 +:10E3300002010101010001010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B0000101010101010100020000000000000054 +:10E3C0000000000000000001010101010101010144 +:10E3D000010101010100000202010101010101012D +:10E3E0000101010101010101020102010202020217 +:10E3F000020200000101010101020102020101010A +:10E4000002020102010101010201010101020101F7 +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101020201010101DA +:10E4300002010101010101010101010101010101CB +:10E4400001010101010101010101010101010101BC +:10E4500001010101010101010101010101010101AC +:10E46000010101010101010101010101010101019C +:10E47000010101010101010101010101010101018C +:10E48000010101010101010101010101010101017C +:10E49000010101010101010101010101010101016C +:10E4A000010101010101010101010101010101015C +:10E4B0000101010101010100020000000000000053 +:10E4C0000000000000000001010101010101010143 +:10E4D000010101010000010201010101010101012D +:10E4E0000101010101010101010102010101020219 +:10E4F0000202020201010101010101020101010107 +:10E5000002010101010101010101010101020101F9 +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010101DB +:10E5300001010101010101010101010101010101CB +:10E5400001010101010101010101010101010101BB +:10E5500001010101010101010101010101010101AB +:10E56000010101010101010101010101010101019B +:10E57000010101010101010101010101010101018B +:10E58000010101010101010101010101010101017B +:10E59000010101010101010101010101010101016B +:10E5A000010101010101010101010101010101015B +:10E5B0000101010101010102020202020202020242 +:10E5C0000202020202020201010101010101010134 +:10E5D000010101010000010101010101010101012D +:10E5E0000101010101010101010102010101020119 +:10E5F0000202020201010101010101010101010107 +:10E6000001010101010101010101010101010101FA +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101010101010101010101BA +:10E6500001010101010101010101010101010101AA +:10E66000010101010101010101010101010101019A +:10E67000010101010101010101010101010101018A +:10E68000010101010101010101010101010101017A +:10E69000010101010101010101010101010101016A +:10E6A000010101010101010101010101010101015A +:10E6B0000101010101010102020202020202020241 +:10E6C0000202020202020201010101010101010133 +:10E6D000010100000000010101010101010101012E +:10E6E000010101010101010101010101010101011A +:10E6F0000201020201010101010101010101010107 +:10E7000001010101010101010101010101010101F9 +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010101010101010101D9 +:10E7300001010101010101010101010101010101C9 +:10E7400001010101010101010101010101010101B9 +:10E7500001010101010101010101010101010101A9 +:10E760000101010101010101010101010101010199 +:10E770000101010101010101010101010101010189 +:10E780000101010101010101010101010101010179 +:10E790000101010101010101010101010101010169 +:10E7A0000101010101010101010101010101010159 +:10E7B0000101010101010102020202020202020240 +:10E7C0000202020202020201010001000101010134 +:10E7D000000100000000010101010101010101012E +:10E7E0000101010101010101010101010101010119 +:10E7F0000101010101010101010101010101010109 +:10E8000001010101010101010101010101010101F8 +:10E8100001010101010101010101010101010101E8 +:10E8200001010101010101010101010101010101D8 +:10E8300001010101010101010101010101010101C8 +:10E8400001010101010101010101010101010101B8 +:10E8500001010101010101010101010101010101A8 +:10E860000101010101010101010101010101010198 +:10E870000101010101010101010101010101010188 +:10E880000101010101010101010101010101010178 +:10E890000101010101010101010101010101010168 +:10E8A0000101010101010101010101010101010158 +:10E8B000010201010202020202020202020202023B +:10E8C0000202020202020201000000000001000038 +:10E8D000000000000000010101010101010101012E +:10E8E0000101010101010101010101010101010118 +:10E8F0000101010101010101010101010101010108 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010101010101010101D7 +:10E9300001010101010101010101010101010101C7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101020102010101010195 +:10E970000101010101000001010101010101010189 +:10E980000101010101010101010101010101010177 +:10E990000101010101010001010101010101010168 +:10E9A0000101010101010101010202020202020250 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020200000000000000000039 +:10E9D000000000000000010101010101010101012D +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010101010101010101D6 +:10EA300001010101010101010201010101010101C5 +:10EA400001010101010101010201010101010101B5 +:10EA500001010101010101010101010101010101A6 +:10EA6000010101010101010101000100000000009C +:10EA7000000000000100000101010101010101018C +:10EA8000010101010102020101000100000000007A +:10EA9000000000000001000101010101010101016C +:10EAA000010101010101010202020202020202024D +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020200000000000000000038 +:10EAD000000000000000010101010101010101012C +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101010101010101010101F5 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101020201010101010101D3 +:10EB300001010101010101020101010101010101C4 +:10EB400001010101010000010101010101010101B7 +:10EB500001010101010101010101020101010101A4 +:10EB6000010101010101000100000000000000009E +:10EB70000000000001000001010202020202020284 +:10EB80000202020202020201010000000000000075 +:10EB9000000000000000000101010101010101016C +:10EBA000010101010102020202020202020202024A +:10EBB0000202020202020202000202020202020237 +:10EBC0000202020202020200000000000000000037 +:10EBD000000000000001010101010101010101012A +:10EBE0000101010101010101010101010101010115 +:10EBF0000101010101010101010101010101010105 +:10EC000001010101010101010101010101010101F4 +:10EC100001010101010101010101010101010101E4 +:10EC200001010101010101020201010101010101D2 +:10EC300001010101010101010001010100000100C8 +:10EC400000000101010000010001010101010001BA +:10EC500001010101010100010001010000000000AB +:10EC600000000000000000010000000000000000A3 +:10EC7000000000000202020202020202020202027C +:10EC80000202020202020201010000000000000074 +:10EC90000000000000000001010202020202020264 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202000202020202020236 +:10ECC0000202020202020200000000000000000036 +:10ECD0000000000000010101010101010101010129 +:10ECE0000101010101010101010101010101010114 +:10ECF0000101010101010101010101010101010104 +:10ED000001010101010101010101010101010101F3 +:10ED100001010101010101010201010101010101E2 +:10ED200001010102010101020201010101010101D0 +:10ED300001010101010101000002010200000100C6 +:10ED400000000101010000000001000000010000BE +:10ED500000000101000000000002000000000000AF +:10ED60000000000000000002000200020202020295 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020201010000000000000073 +:10ED9000000000000002020202020202020202025D +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202000202020202020235 +:10EDC0000202020202020200000000000000000035 +:10EDD0000000000001010101010101010101010127 +:10EDE0000101010101010101010101010101010113 +:10EDF0000101010101010101010101010101010103 +:10EE000001010101010101010101010101010101F2 +:10EE100001010101010101010101010101010101E2 +:10EE200001010102010102020202010101010101CD +:10EE300001010101020101000001010100000100C6 +:10EE400000000101000000000002000000010000BD +:10EE500000000001000000000001000000000000B0 +:10EE6000000000000002020202020202020202028C +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202000202020202020234 +:10EEC0000202020202020200000000000000000034 +:10EED0000000000001010101010101010101010126 +:10EEE0000101010101010101010101010101010112 +:10EEF0000101010101010101010101010101010102 +:10EF000001010101010101010101010101010101F1 +:10EF100001010101020101020002010202020202DA +:10EF200001010201020201010102010101010101CD +:10EF300001010202020102000000010000000200C3 +:10EF400000000101000000000001000000010000BD +:10EF5000000000020002020000020002020202029F +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020200000000000000000033 +:10EFD0000000010101010101010101010101010123 +:10EFE0000101010101010101010101010101010111 +:10EFF0000101010101010101010101010101010101 +:10F0000001010101010101010101010101010101F0 +:10F0100001010101020002010001020101010101DF +:10F0200000000101010100010101020202020101CF +:10F0300002010101010201000000020000000100C4 +:10F0400000000202020202020002020202020202A6 +:10F050000202020202020202020202020202020290 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020202020202020202020230 +:10F0C000020202020202020000010001010000012E +:10F0D0000101010101010101010101010101010120 +:10F0E0000101010101010101010101010101010110 +:10F0F0000101010101010101010101010101010100 +:10F1000001010101020201020102020202010202E6 +:10F1100002020202010001000000010000000000E4 +:10F1200002020000000202010101010101010202CC +:10F1300001020202010102000202020202020202B4 +:10F14000020202020202020202020202020202029F +:10F15000020202020202020202020202020202028F +:10F16000020202020202020202020202020202027F +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A000020202020202020202020202020202023F +:10F1B0000202020202020202020200020202020231 +:10F1C0000202020202020201010101010101010128 +:10F1D000010101010101010101010101010101011F +:10F1E000010101010101010101010101010101010F +:10F1F00001010101020201010101010101010101FD +:10F2000001010101010102010101010101010101ED +:10F2100001010101010202020202020202020202D3 +:10F2200002020202020202010102020202020202C0 +:10F2300002020202020202020202020202020202AE +:10F24000020202020202020202020202020202029E +:10F25000020202020202020202020202020202028E +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202020202020202023E +:10F2B0000202020202020202020200020200020232 +:10F2C000020202020000000101010101010101012D +:10F2D000010101010101010101010101010101011E +:10F2E000010101000101010101010101010101010F +:10F2F00001010101010102020202020202020202F4 +:10F3000002020202020202020202020202020202DD +:10F3100002020202020202020202020202020202CD +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020202020202AD +:10F34000020202020202020202020202020202029D +:10F35000020202020202020202020202020202028D +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B000020202020202020202000000000000003B +:10F3C000000202020000000101010101010101012E +:10F3D000010101010101010101010101010101011D +:10F3E0000101010002020202020202020202020202 +:10F3F00002020202020202020202020202020202ED +:10F4000002020202020202020202020202020202DC +:10F4100002020202020202020202020202020202CC +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020202029C +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202020202027C +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202000000000000003A +:10F4C0000002000000000001010101010101010131 +:10F4D0000101010101010102020202020202020213 +:10F4E00002020202020202020202020202020202FC +:10F4F00002020202020202020202020202020202EC +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020202020202020202CB +:10F5200002020202020202020202020202020202BB +:10F5300002020202020202020202020202020202AB +:10F54000020202020202020202020202020202029B +:10F55000020202020202020202020202020202028B +:10F56000020202020202020202020202020202027B +:10F57000020202020202020202020202020202026B +:10F58000020202020202020202020202020202025B +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B0000202020202020202020000000000000039 +:10F5C0000000000000000001010101010101010132 +:10F5D0000101010101010102020202020202020212 +:10F5E00002020202020202020202020202020202FB +:10F5F00002020202020202020202020202020202EB +:10F6000002020202020202020202020202020202DA +:10F6100002020202020202020202020202020202CA +:10F6200002020202020202020202020202020202BA +:10F6300002020202020202020202020202020202AA +:10F64000020202020202020202020202020202029A +:10F65000020202020202020202020202020202028A +:10F66000020202020202020202020202020202027A +:10F67000020202020202020202020202020202026A +:10F68000020202020202020202020202020202025A +:10F69000020202020202020202020202020202024A +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020200000000000000003A +:10F6C0000000000000000001010101010101010131 +:10F6D000010101010101010101010101010101011A +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010101010101010101D9 +:10F7200001010101010101010101010101010101C9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010102000000000000000040 +:10F7C0000000000000000001010101010101010130 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010100000000000000000071 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000002000000000000000046 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C000000000000000003E0000000000000000F9 +:10F9D0000000000000000000000000000000000027 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000000000000000000000000000000000000F6 +:10FA100000000000000000000000000000000000E6 +:10FA200000000000000000000000000000000000D6 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC000020202020202020200000202020000021E +:10FAD0000000000000000000000000000202000022 +:10FAE000000000000002000000000002020200000E +:10FAF0000000000000000000000000000002020002 +:10FB000000000000000000000000000000020200F1 +:10FB100000020000000000000000000000000000E3 +:10FB200000000000000000000000000000000000D5 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000000000000000075 +:10FB90000001000000000000000000000002000062 +:10FBA0000000000000000000000000000000020053 +:10FBB000000002020200000000000000000002003D +:10FBC0000202020202020202020202020202000217 +:10FBD000000000000000000000000000020200021F +:10FBE000000000000002000000000002020202000B +:10FBF00000000000000000000000000200020200FF +:10FC000000000000000000000000000202020200EC +:10FC100000020000000100000000000000020000DF +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000173 +:10FC9000000101010100000000000000020202005A +:10FCA000020100000001000000000000000202004C +:10FCB0000202020202020202020202020202020026 +:10FCC0000202020202020202020202020202000216 +:10FCD000000000000000000000000000020200021E +:10FCE0000000000000020002000000020202020008 +:10FCF00000000000000000000000000200020200FE +:10FD000000000000000000000000000202020200EB +:10FD100000020001000100000000000000020000DD +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000172 +:10FD90000102010201010000000000000202020154 +:10FDA0000202020201010000000000000002020243 +:10FDB0000202020202020202020202020202020025 +:10FDC0000202020202020202020202020202000215 +:10FDD000000000000000000000000000020200021D +:10FDE0000000000000020002000000020202020007 +:10FDF00000000000000000000000000202020200FB +:10FE000000000000000000000000000202020200EA +:10FE100000020001000100000000000000020000DC +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000171 +:10FE9000020202020201000000000000020202024F +:10FEA000020202020202020000000000000202023E +:10FEB0000202020202020202020202020202020024 +:10FEC0000202020202020202020202020202000214 +:10FED000000000000000000000000000020200021C +:10FEE0000000000000020002000000020202020006 +:10FEF00000000000000000000000000202020200FA +:10FF000000000000000000000000000202020200E9 +:10FF100000020001000200000000000000020000DA +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF6000010000000101000000000000000000008E +:10FF70000000000000000000000000000000000081 +:10FF8000000000000000000000000000000000026F +:10FF9000020202020202000000000000020202024D +:10FFA000020202020202020000000000000202023D +:10FFB0000202020202020202020202020202020023 +:10FFC0000202020202020202020202020202000213 +:10FFD000000000000000000000000000020200021B +:10FFE0000000000000020002000000020202020005 +:10FFF00000000000000000000000000202020200F9 +:020000040011E9 +:1000000000000000000000000000000202020200E8 +:1000100000020002000200000000000002020000D6 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000002AE +:1000500000000000000000000000000000000000A0 +:10006000010000000101000000000000000000008D +:100070000000000000000000000000000000000080 +:10008000000000000000000000000000000000026E +:10009000020202020202000000000000020202024C +:1000A0000202020202020202000202000002020236 +:1000B0000202020202020202020202020202020022 +:1000C0000202020202020202020202020202000212 +:1000D000000000000000000000000000020200021A +:1000E0000000000000020002000000020202020004 +:1000F00000000000000000000000000202020200F8 +:1001000000000000000000000000000202020201E6 +:1001100000020002000200000000000002020000D5 +:1001200000000000000000000000000000000000CF +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000002AD +:10015000000000000000000000000000000000029D +:100160000100000102010000000000000002020086 +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000026D +:100190000202020202020200000000000202020249 +:1001A0000202020202020202000202000002020235 +:1001B0000202020202020202020202020202020021 +:1001C0000202020202020202020202020202000211 +:1001D0000000000000000000000000000202000219 +:1001E0000000000000020002000000020202020102 +:1001F00000000000000000000000000202020200F7 +:1002000000000000000000000000000202020202E4 +:1002100000020002000200000000000002020000D4 +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000002AC +:10025000000000010000000000000000000000029B +:100260000200000202020000000000000002020082 +:10027000000000000000000000000000000000007E +:10028000010000000000000000000000000000026B +:100290000202020202020200000000000202020248 +:1002A0000202020202020202020202020002020230 +:1002B0000202020202020202020202020202020020 +:1002C0000202020202020202020202020202000210 +:1002D0000000000000000000000000000202000218 +:1002E0000000000000020002000000020202020200 +:1002F00000000000000000000000000202020200F6 +:1003000000000000000000000000000202020202E3 +:1003100000020002000200000000000002020000D3 +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000002AB +:100350000101000100010000000002000002000293 +:100360000200010202020000000000000002020080 +:10037000000000000000000000000000000000007D +:100380000100010000000000000000000000000269 +:100390000202020202020200020202000202020241 +:1003A000020202020202020202020202000202022F +:1003B000020202020202020202020202020202001F +:1003C000020202020202020202020202020200020F +:1003D0000000000000000000000000000202000217 +:1003E00000000000000200020000000202020202FF +:1003F00000000000000000000000000202020200F5 +:1004000000000000000000000000000202020202E2 +:1004100000020002000200000000000002020000D2 +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000002AA +:10045000010201020001000000000200000200028F +:10046000020002020202020000000000000202007C +:10047000000000000000000000000000000000007C +:100480000101010000010000000000000000000266 +:100490000202020202020200020202000202020240 +:1004A000020202020202020202020202000202022E +:1004B000020202020202020202020202020202001E +:1004C000010101010101010101010101010100021C +:1004D0000000000000000000000000020202000214 +:1004E00000000000000200020000000202020202FE +:1004F00000000000000000000000000202020200F4 +:1005000000000000000000000000000202020202E1 +:1005100000020002000200000000000002020200CF +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000100000000000000000000000002A8 +:10055000020201020002000002000200000200028A +:10056000020002020202020000000000000202007B +:100570000000000000000000000000000000000279 +:100580000201010100010000000000000000000263 +:10059000020202020202020202020202020202023B +:1005A000020202020202020202020202000202022D +:1005B000020202020202020202020202020202001D +:1005C000010101010101010101010101010100021B +:1005D0000000000000000000000000020102000214 +:1005E00000000002000200020000000202020202FB +:1005F00000000000000000000000000202020200F3 +:1006000000000000000000000000000202020202E0 +:1006100001020002000200020000000002020200CB +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000101000000000000000000000002A6 +:100650000202020201020000020002000002020285 +:100660000200020202020200020202000002020074 +:100670000100000000000000000000000000000277 +:100680000201020100010000000000000000000261 +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020202020202020202001C +:1006C000010101010101010101010101010100021A +:1006D0000000000000000002000000020102000211 +:1006E00000000002000200020000000202020202FA +:1006F00000000000000000000000000202020202F0 +:1007000000000000000000000000000202020202DF +:1007100001020102000200020000000002020200C9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000101000000000000000000000002A5 +:100750000202020202020200020002000002020281 +:100760000201020202020200020202000002020171 +:100770000100000000000000000000000000000276 +:10078000020202020102000000000000000000025C +:100790000202020202020202020202020202020239 +:1007A0000202020202020202020202020202020229 +:1007B000020202020202020202020202020201001C +:1007C0000101010101010101010101010101000219 +:1007D0000000000000000002000000020101000211 +:1007E00000000002000200020000000202020202F9 +:1007F00001000000000000000000000202020202EE +:1008000000000000000000000000000202020202DE +:1008100001020102000200020000000002020200C8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000002B6 +:1008400000000201000000000000000000000002A3 +:100850000202020202020200020002000002020280 +:10086000020202020202020202020200000202026C +:100870000101000000000000000000000000000274 +:10088000020202020102000000000000000000025B +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B000020202020202020202020202020101001C +:1008C0000101010101010101010101010101000218 +:1008D0000202000002020002020200020101000204 +:1008E00000000002000200020000000202020202F8 +:1008F00001000000000000000000000202020202ED +:1009000000000000000000000000000202020202DD +:1009100002020102010200020000000002020200C5 +:1009200000000000000000000000000000000000C7 +:1009300000000000000002000000000000000002B3 +:10094000000002020001000000000002020000029C +:10095000020202020202020002020202000202027B +:10096000020202020202020202020200000202026B +:100970000201000101000000000000000000000270 +:100980000202020202020000000000000000020257 +:100990000202020202020202020202020202020237 +:1009A0000202020202020202020202020202020227 +:1009B000020202020202020202020202010101001C +:1009C0000000000000000000000000000001000125 +:1009D0000202000002020002020200020101000203 +:1009E00000000002000200020000000202020202F7 +:1009F00001000000000000000000000202020202EC +:100A000000000000000000000000000202020202DC +:100A100002020202010200020000000002020200C3 +:100A200000000000000000000000000000000000C6 +:100A300000000000000002000000020000000002B0 +:100A4000000002020001000000000002020000029B +:100A5000020202020202020002020202000202027A +:100A60000202020202020202020202020002020268 +:100A7000020100010100000000000000000000026F +:100A80000202020202020000000000000002020254 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020202020202020202010227 +:100AB000020202020202020202020201010101001C +:100AC0000000000000000000000000000001000124 +:100AD0000202020002020002020200020101000200 +:100AE00001010002000200020000000202020202F4 +:100AF00002000001000000000000000202020202E9 +:100B000000000000000000000000000202020202DB +:100B100002020202020200020000000002020201C0 +:100B200000000000000000000000000000000000C5 +:100B300000000000000002000002020000000002AD +:100B40000002020200010000000000020200000298 +:100B50000202020202020200020202020002020279 +:100B60000202020202020202020202020002020267 +:100B7000020201010200000000000000000000026B +:100B80000202020202020000000000000002020253 +:100B90000202020202020202020202020201010237 +:100BA0000202020202020202020202020201010227 +:100BB000020202020202020101010101010101001F +:100BC0000000000000000000000000000001000123 +:100BD0000202020002020002020200010101000200 +:100BE00002010102010200020000000202020202F0 +:100BF00002000002000000000000000202020202E7 +:100C000000000000000000000000000202020202DA +:100C100002020202020200020000000002020202BE +:100C200000000000000000000000000000000000C4 +:100C300000000001000002000002020000000002AB +:100C40000002020202020000000000020200000294 +:100C50000202020202020200020202020002020278 +:100C60000202020202020202020202020002020266 +:100C70000202010202010000000000000000000268 +:100C8000020202020202020000000200000202024E +:100C90000202020202020202020202020201010236 +:100CA0000202020202020202020202020201010226 +:100CB0000202020201010101010101010101010021 +:100CC0000000000000000000000000000001000122 +:100CD00002020200020202020202020101010002FB +:100CE00002020102020202020000000202020202EB +:100CF00002000002000000000000000202020202E6 +:100D000000000000000000000000000202020102DA +:100D100002020202020200020000000002020202BD +:100D200000000000000000000000000000000000C3 +:100D300000000002000002000002020000000002A9 +:100D40000002020202020000000000020202000291 +:100D50000202020202020202020202020002020275 +:100D60000202020202020202020202020002020265 +:100D70000202010202010000000000000000000267 +:100D8000020202020202020000000200000202024D +:100D90000202020202020202020202020101010236 +:100DA0000202020202020202020202020201010225 +:100DB0000202010101010101010101010101010022 +:100DC0000000000000000000000000000001010120 +:100DD00002020200020202010202020101010002FB +:100DE00002020202020202020000000202010202EA +:100DF00002000002000000000000000202020102E6 +:100E000000000000000102000000000202010102D7 +:100E100002020202020200020000000002010202BD +:100E200000000000000000000000000000000001C1 +:100E300000000002000002000002020000000002A8 +:100E40000002020202020000000000020202000290 +:100E50000202020202020202020202020002020274 +:100E60000202020202020202020202020202010263 +:100E70000202020202010202000000000000000261 +:100E80000202020202020200020202000202020246 +:100E90000202020202020202020202020101010235 +:100EA0000202020202020202020202020201010224 +:100EB0000201010101010101010101010101010022 +:100EC000000000000000000000000001010101021C +:100ED00002020202020202010101020101010002FA +:100EE00002020202020202020002000202010102E8 +:100EF00002000002000000000000000202010102E6 +:100F000000000102010202000000000202010102D1 +:100F100002020202020200020000000002010202BC +:100F200000000000000000000000000000000002BF +:100F300000000002000002000002020000000002A7 +:100F4000010202020202000200000002020200028C +:100F50000202020202020202020202020002020273 +:100F60000202020202020202020202020201010263 +:100F7000020202020202020200000000000000025F +:100F80000202020202020200020202000202020245 +:100F90000202020202020202020202020101010234 +:100FA0000202020202020202020202020201010223 +:100FB0000201010101010101010101010101010021 +:100FC000000000000000000000000001010101021B +:100FD00001020202020102010101010101010002FC +:100FE00002020202020202020002000201010102E8 +:100FF00002000002000000000000000202010102E5 +:1010000000000202020202000002020101010102CC +:1010100002020202020202020000000002010202B9 +:1010200000000000000000000000000000000002BE +:1010300000000002000002000002020000000202A4 +:101040000102020202020002000000020202020289 +:101050000202020202020202020202020002020272 +:101060000202020202020202020202020201010262 +:101070000202020202020202000200020002000258 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020101010233 +:1010A0000202020202020202020202020201010222 +:1010B0000101010101010101010101010101010021 +:1010C000000000000000000000000001010101021A +:1010D00001020202010102010101020101010002FB +:1010E00002020202020202020002000101010102E8 +:1010F00002000002010000000000000101010102E5 +:1011000000020202020202000002020101010102C9 +:1011100002020202020202020000000001010202B9 +:1011200000000000000000000000000000000002BD +:1011300000000002000002000002020000000202A3 +:101140000102020202020202000202020202020282 +:101150000202020202020202020202020201020270 +:101160000202020202020202020202020201010261 +:101170000202020202020202000200020002020255 +:10118000020202020202020202020202020202023F +:101190000202020202020202020202020101010232 +:1011A0000202020202020101020101010201010226 +:1011B0000101010101010101010101010101010020 +:1011C0000000000000000000000000010101010219 +:1011D00001010202010101010101010101010002FD +:1011E00002020202020202020002000101010102E7 +:1011F00002000002020102000000020101010102DE +:1012000002020202020202000202020101010102C4 +:1012100002010202020202020000000001010102BA +:1012200000000000000000000000000000000002BC +:1012300000000102000002000002020000000202A1 +:101240000202020202020202000202020202020280 +:101250000202020202020202020202020201010270 +:101260000202020202020202020202020201010260 +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:101290000202020202020202020202020101010231 +:1012A000020201010101010101010101010101022B +:1012B000010101010101010101010101010101001F +:1012C0000000000000000000000000010101010218 +:1012D00002010101010101010101010101010002FD +:1012E00002020202020202020202020101010102E2 +:1012F00002000002020202000000020101010102DC +:1013000002020202020202020202020101010102C1 +:1013100002010202020202020000000201010102B7 +:1013200000000000000000000000000002000002B9 +:10133000010101020000020000020200000202029C +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020101026F +:10136000020202020202020202020202020101025F +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020201023E +:101390000202020101010102010101010101010238 +:1013A000010101010101010101010101010101022C +:1013B000010101010101010101010101010101001E +:1013C0000000000000000001000000010101010117 +:1013D00002010101010101010101010100010002FD +:1013E00002020202020102010202020101010102E3 +:1013F00002000002020202000000020101010102DB +:1014000002020202020202020202020101010102C0 +:1014100002010202020202020202020201010102B0 +:1014200001000000000000000000000002000202B5 +:10143000010101020100020000020200000202029A +:10144000020202020202020202020202020202027C +:10145000020202020202020202020102020101026F +:10146000020202020202020202020202020101025E +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020101023E +:10149000020101010101010101010101010101023A +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101001D +:1014C0000000000000000001010101010101010113 +:1014D00002010102010101010101010100010002FB +:1014E00002020202020102010202020101010102E2 +:1014F00002000102020202020000020101010102D7 +:1015000002020202020202020202020101010102BF +:1015100002010202020202020202020201010102AF +:1015200001010000000000000000000002000202B3 +:101530000201020201010200000202000002020296 +:10154000020202020202020202020202010202027C +:10155000020202020202020201020102020101026F +:101560000202020201020102010101020201010262 +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020101023D +:10159000010101010101010101010101010101023A +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101001C +:1015C0000000000000000001010101010101010112 +:1015D00001010102010101010101010100010002FB +:1015E00002020202020102010202020101010102E1 +:1015F00002000202020202020202020101010102D1 +:1016000002020202020202020202020101010102BE +:1016100002010202020102010202020201010102B0 +:1016200002010000000000000000000002020202AF +:101630000202020201010200000202000002020294 +:10164000020202020202020202020201010102027D +:10165000020202020202020201020101020101026F +:101660000202020101010101010101010201010265 +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020101023C +:101690000101010101010101010101010101010239 +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101001B +:1016C000000000000001010101010101010101010F +:1016D00001010101010101010101010000010002FC +:1016E00002020202020102010202020101010102E0 +:1016F00002000202020202020202020101010102D0 +:1017000002020202020202020202020101010102BD +:1017100002010202020102010202020201010102AF +:1017200002010101000000000000000002020202AC +:101730000202020202010200000202000002020292 +:10174000020202020202020202020201010101027D +:10175000020202020202020201020101020101026E +:101760000202010101010101010101010101010266 +:101770000202020202020202020202020202020249 +:10178000020202020202020202020202010101023C +:101790000101010101010101010101010101010238 +:1017A0000101010101010101010101010101010129 +:1017B000010101010101010101010101010101001A +:1017C000000000000101010101010101010101010D +:1017D00001010101010101000000010000000002FF +:1017E00002020202020102010202020101010102DF +:1017F00002000202020202020202020101010102CF +:1018000002020202020202020202020101010102BC +:1018100002010201020102010202020201010102AF +:1018200002020101000000000000000002020202AA +:101830000202020202020200000201000002010292 +:10184000020202020202020202020201010101027C +:101850000201020202010102010101010201010271 +:101860000202010101010101010101010101010265 +:10187000020202020202020202020202020101024A +:10188000020202020202020202020202010101023B +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010019 +:1018C000000000000101010101010101010101010C +:1018D00001010101010001000000010000000002FF +:1018E00002020202020102010202020101010102DE +:1018F00002000202020202020202020101010102CE +:1019000002020202020202020202020101010102BB +:1019100002010201020102010202020201010102AE +:1019200002020101010000000000000002020202A8 +:101930000202020202020100000101000002010293 +:10194000020202020202020202020201010101027B +:101950000201020101010102010101010201010173 +:101960000102010101010101010101010101010265 +:101970000202020202020202020202020201010249 +:10198000020202020201020202020102010101023C +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010018 +:1019C000000000010101010101010101010101010A +:1019D0000100010100000000000000000000000103 +:1019E00002020202020102010202020101010102DD +:1019F00002020202020202020202020101010102CB +:101A000002020202020202020202020101010102BA +:101A100002010201020102010202020201010102AD +:101A200002020202010100000000000002020102A5 +:101A30000202020202020100000101000001010293 +:101A4000020202020102020102020201010101017D +:101A50000201010101010101010101010101010175 +:101A60000101010101010101010101010101010265 +:101A7000020202020202020102020201010101024B +:101A80000202010101010102010101010101010143 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010017 +:101AC0000000010101010101010101010101010009 +:101AD0000100000100000000000000000000000103 +:101AE00002020201020102010202020101010102DD +:101AF00002020202020202020202020101010102CA +:101B000002020202020202020202020101010102B9 +:101B100002010201020102010202020201010102AC +:101B200002020202010100000000000001020102A5 +:101B30000202020202020100000101000001010292 +:101B4000020101020102020102020201010101017E +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010264 +:101B7000020202020202010102010201010101024C +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010016 +:101BC0000000010101010101010101010101010008 +:101BD0000000000100000000000000000000000103 +:101BE00002020201020102010202020101010102DC +:101BF00002020202020202020202020101010102C9 +:101C000002020202020201020201010101010101BC +:101C100002010201010102010202020101010102AD +:101C200002020202020100000000000001010102A4 +:101C30000202020202020100000101000001010291 +:101C40000201010101010201020101010101010181 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010263 +:101C7000020202020102010101010201010101014E +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010015 +:101CC0000001010101010101010101010101010006 +:101CD0000000000000000000000000000000000103 +:101CE00002020201020101010201020101010102DD +:101CF00002020202020202020202020101010102C8 +:101D000002020202020101010101010101010101BE +:101D100002010101010101010202020101010102AE +:101D200002020202020200000000000001010102A2 +:101D30000202020202020100000101000001010290 +:101D40000201010101010101010101010101010182 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010262 +:101D7000020202020102010101010101010101014E +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010014 +:101DC0000001010101010101010101010101010005 +:101DD0000000000000000000000000000000000102 +:101DE00002020201010101010201020101010101DE +:101DF00002020201020202020202010101010102C9 +:101E000002020201010101010101010101010101BF +:101E100001010101010101010101010101010102B1 +:101E200002020202020200000000000001010102A1 +:101E30000202020102020100000101000001010191 +:101E40000201010101010101010101010101010181 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010261 +:101E70000101020101010101010101010101010151 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010013 +:101EC0000101010101010101010101010100000005 +:101ED0000000000000000000000000000000000101 +:101EE00002020201010101010101010101010101DF +:101EF00002020201020201010202010101010101CB +:101F000002010101010101010101010101010101C0 +:101F100001010101010101010101010101010102B0 +:101F200002020202020200000000000001010102A0 +:101F3000020202010202010002010100000101018E +:101F40000201010101010101010101010101010180 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010012 +:101FC0000101010101010101010101010100000004 +:101FD0000000000000000000000000000000000100 +:101FE00001010101010101010101010101010101E1 +:101FF00001020201010101010101010101010101CF +:1020000002010101010101010101010101010101BF +:1020100001010101010101010101010101010102AF +:10202000020202020202000000000000010101029F +:10203000020202010202010002010100000101018D +:10204000020101010101010101010101010101017F +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010011 +:1020C0000101010101010101010101000100000004 +:1020D00000000000000000000000000000000001FF +:1020E00001010101010101010101010101010101E0 +:1020F00001020201010101010101010101010101CE +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010102AE +:10212000020202020202000000000200010101029C +:102130000202020102020102020101020001010188 +:10214000020101010101010101010101010101017E +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B0000101010101010101010101010101010010 +:1021C0000101010101010101010101000100000003 +:1021D00000000000000000000000000000000001FE +:1021E00001010101010101010101010101010101DF +:1021F00001020201010101010101010101010101CD +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:102220000202020202020200020002000101010297 +:102230000202020102020102020101020001010187 +:10224000020101010101010101010101010101017D +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B0000102020202020202020202020202020001 +:1022C0000101010101010101010101000000000003 +:1022D00000000000000000000000000000000101FC +:1022E00001010101010101010101010101010101DE +:1022F00001020101010101010101010101010101CD +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:102320000202020202020200020202000101010294 +:102330000202020102020102020101020201010184 +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020202020200EF +:1023D00000000000000000000000000000000101FB +:1023E00001010101010101010101010101010101DD +:1023F00001020101010101010101010101010101CC +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:102420000202020202020200020202000101010194 +:102430000202010101010102020101020201010186 +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010101010101010101015C +:10247000010101010101010101010101010101014C +:10248000010101010101010101010101010101013C +:10249000010101010101010101010101010101012C +:1024A000010101010101010101010101010101021B +:1024B000020101010101010101010101010101020A +:1024C00002020202020202020202020202020200EE +:1024D00000000000000000000000000000000101FA +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:102520000102020202020202020202000101010192 +:10253000010101010101010201010101010101018A +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:10257000010101010101010101010101010101014B +:10258000010101010101010101010101010101013B +:10259000010101010101010101010101010101012B +:1025A000010101010101010101010101010101021A +:1025B000010101010101010101010101010101020A +:1025C00002020202020202020202020202020200ED +:1025D00000000000000000000000000000000101F9 +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:102620000101020202020202010201020101010192 +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:10267000010101010101010101010101010101014A +:10268000010101010101010101010101010101013A +:10269000010101010101010101010101010101012A +:1026A000010101010101010101010101010101011A +:1026B00001020202020202020202020202020202FB +:1026C00002020202020202020202020202020200EC +:1026D00000000000000000000000000000010101F7 +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010202010101020101010196 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101010101010101010159 +:102770000101010101010101010101010101010149 +:102780000101010101010101010101010101010139 +:102790000101010101010101010101010101010129 +:1027A0000101010101010101010101010101010119 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020200EB +:1027D00000000000000000000000000000010101F6 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010102020215 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020200EA +:1028D00000000000000000000000000001010101F4 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010147 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010100000129 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020200E9 +:1029D00000000000000000000000000001010101F3 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010265 +:102A60000101010101010101010101010101000157 +:102A70000101010101010101010101010101010146 +:102A80000101010101010101010101010101010136 +:102A9000000000000000000000000000020202022E +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020200E8 +:102AD00000000000000000000000000001010101F2 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001000101010101010101010101010101A6 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000100010101010101000100000101010169 +:102B6000010100000001000000000000000202015D +:102B70000101010101010202020201010201010140 +:102B80000101010101010101010101010002010036 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020200E7 +:102BD00000000000000000000000000101010101F0 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001000101010101010101010101010101A5 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010100010101010185 +:102C40000100010100010100010101020101010176 +:102C50000100010101010101000100000102020067 +:102C60000202020202020202020202020202020145 +:102C70000101010101010102010101000202020141 +:102C80000101010101010101010101010001020233 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020200E6 +:102CD00000000000000000010101000101010101EC +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010201010101B2 +:102D100001000101010101010101010101010101A4 +:102D20000101010101010101010101010201010192 +:102D30000101010101010001010000010102010185 +:102D40000100000100010100010101010202020273 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000101020201020001000001000101010243 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020200E5 +:102DD00000000000010100010101000101010101E9 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001000101010101000101010101010001B5 +:102E100001000101010101000101010102010101A3 +:102E20000101010101010101010101010101000193 +:102E30000101010101010001010000010101020283 +:102E40000102020202020202020202020202020263 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020143 +:102E7000020201010201000100000202010202023D +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020201E3 +:102ED00000010100010101010101010101010101E4 +:102EE00001010101010101010101010101020101D1 +:102EF00001010101010101010101010202010101C0 +:102F000000000000000000000000000001000001BF +:102F100001000101010101000101010001020201A2 +:102F20000001010101010101000101010002020192 +:102F3000010101020101020101020201010202027A +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020201E2 +:102FD00000010100010101010101010101010101E3 +:102FE00001010101010101010101010101020101D0 +:102FF00001010101010101000101010101010001C3 +:1030000000000000000000000000000002020202B8 +:103010000202020202020202020202020202020290 +:103020000000010101010100000000010202020292 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020201E1 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010202010101CE +:1030F00000000000000000000000000000020202CA +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020201E0 +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010202CD +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00000000202020202020202020202020201E3 +:1032D00001010101010101010101010101010102DD +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00000000002020202020202020202020201E4 +:1033D00001010101010101010101010101010102DC +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00000000000000000020202000202020001EF +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010102FA +:1035C00000000000000000000000000000000001FA +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101004B +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B0000000000000000000000000000000000208 +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000053A6 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000010000000097 +:103830000000000000000000000000000000000088 +:103840000000000000000001000000000000000077 +:103850000000000000000000000001000000000067 +:103860000000000000010100000000000000000056 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000020000000000000000E6 +:1038E00000000000000200000101010100010101CF +:1038F00001000101010000010000000001000000C2 +:1039000000010000000100000000000000000000B5 +:1039100000010000000100000000000000000000A5 +:103920000000010101000000000000010100000092 +:103930000001000000020000000000000000020082 +:103940000100010101000001000000000000000072 +:10395000010001010100000000000100010002025D +:103960000100010001010100000000000000000052 +:103970000001000000010100000000000000000044 +:103980000001000200010100000000000100000031 +:103990000000000000020000000000000001000222 +:1039A0000100010101000000000000000000000013 +:1039B0000001000000010000000000000001020002 +:1039C00001000101010000000000000000000000F3 +:1039D00000000000000000020000000000000000E5 +:1039E00000000000000200000101010101010101CD +:1039F00001010101010000010100000001010101BC +:103A000001010101010100000000000000000200AE +:103A1000010102020101000000000000010000009D +:103A2000000101010102000000000001010002028A +:103A3000010101020202000100000000000002007A +:103A4000010101010101010100000000000000006E +:103A5000010101010100010000000100010001015C +:103A6000010201010101010000000000000100004D +:103A70000101010101010100000000000101020239 +:103A8000010101010101010000000000010000002E +:103A9000020002020201000000000000000100021A +:103AA0000101010101010100000000000002020209 +:103AB00001010101010100000000000000010200FD +:103AC00001010101010101000000000000000000EF +:103AD00000000000000000020000000000000000E4 +:103AE00000000000000200000101010101010101CC +:103AF00001010101010000010100000001010101BB +:103B000001010101010100000000000000000200AD +:103B1000010102020101000000000000010000019B +:103B2000020101010101000000000001010001018A +:103B30000101010202020001000000000002010078 +:103B4000010101010101010100000000000002006B +:103B5000010101010100010000000100010101015A +:103B6000010101010101010000000000000100004D +:103B7000010101010101010000000000010101013A +:103B8000010101010101010000000000010000002D +:103B90000202020202010000000000000101010215 +:103BA0000101010101010100000000000002020208 +:103BB00001010101010100000000000000010101FC +:103BC00001010101010101000000000000000000EE +:103BD00000000000000000020000000000000000E3 +:103BE00000000000000200000101010102010101CA +:103BF00001010101010200010100000001010101B8 +:103C000001010101010100000000000000000100AD +:103C1000010102010101000000000000010000019B +:103C20000201010101010000000000010100010189 +:103C30000101010202010001000000000001010079 +:103C4000010101010101010100000000010001006A +:103C50000101010101000100000001000101010159 +:103C6000010101010101010000000000000100004C +:103C70000101010101010100000000000101010139 +:103C8000010101010101010000000000010000002C +:103C90000202010101010000000000000101010118 +:103CA0000101010101010100000000000002020207 +:103CB00001010101010100010000000000010101FA +:103CC00001010101010101000000000000000000ED +:103CD00000000000000000020000000000000000E2 +:103CE00000000000000200000101010202010101C8 +:103CF00001010101010100010100000001010101B8 +:103D000001010101010101000000000000000100AB +:103D1000010101010101000000000000010000019B +:103D20000101010101010000000000010100010189 +:103D30000101010101010001000001000001010079 +:103D40000101010101010101000000000100010267 +:103D50000101010101000100000001000101010158 +:103D6000010101010101010000000000000100004B +:103D70000101010101010100000000000101010138 +:103D8000010101010101010000000000010000002B +:103D90000102010101010000000000000101010118 +:103DA0000101010101010100000000000001010109 +:103DB00001010101010101010000000000010101F8 +:103DC00001010101010101000000000000000000EC +:103DD00000000000000000020000000000000000E1 +:103DE00000000000000200010101010202010101C6 +:103DF00001010101010100010101000101010101B5 +:103E000001010101010101000000010000020100A7 +:103E1000010101010101000000000000010000019A +:103E20000101010101010100000000010101010186 +:103E30000101010101010001000001000001010078 +:103E40000101010101010101000000000100010167 +:103E50000101010101000100000001000101010157 +:103E60000101010101010100000000000001020246 +:103E70000101010101010100000000000101010137 +:103E8000010101010101010000000000010000002A +:103E90000101010101010000000000000101010118 +:103EA0000101010101010100000000000001010108 +:103EB00001010101010101010000000000010101F7 +:103EC00001010101010101000000000000000000EB +:103ED00000000000000000020000000000000000E0 +:103EE00000000000000200010101020202010102C3 +:103EF00001010101010100010101000101010101B4 +:103F000001010101010101000000010000020100A6 +:103F10000101010101010100010101000100020193 +:103F20000101010101010100000000010101010185 +:103F30000101010101010001000001000001010176 +:103F40000101010101010101000000000101010165 +:103F50000101010101000100000001000101010156 +:103F60000101010101010100000000000001010147 +:103F70000101010101010100000000000101010136 +:103F80000101010101010100000000000100000029 +:103F90000101010101010000000000000101010117 +:103FA0000101010101010100000000000001010107 +:103FB00001010101010101010000000000010101F6 +:103FC00001010101010101000000000000000000EA +:103FD00000000000000000020000000000000000DF +:103FE00000000000000200010101020202010102C2 +:103FF00001010101010100010101000101010101B3 +:1040000001010101010101000000010000020100A5 +:104010000101010101010100010101000100020192 +:104020000101010101010100010000010101010183 +:104030000101010101010001000001000001010175 +:104040000101010101010101000000000101010164 +:104050000101010101000100000001000101010155 +:104060000101010101010100000000000001010146 +:104070000101010101010100000000000101010135 +:104080000101010101010100000000000100000028 +:104090000101010101010000000000000101010116 +:1040A0000101010101010100000000000001010106 +:1040B00001010101010101010000000000010101F5 +:1040C00001010101010101000000000000000000E9 +:1040D00000000000000000020000000000000000DE +:1040E00000000000000200010101020202010102C1 +:1040F00001010101010100010101000101010101B2 +:1041000001010101010101010000010000010100A4 +:104110000101010101010100010101000100020191 +:104120000101010101010100010000010101010182 +:104130000101010101010001000001000001010174 +:104140000101010101010101000000000101010163 +:104150000101010101000100000001000101010154 +:104160000101010101010100000000000001010145 +:104170000101010101010100000000000101010134 +:104180000101010101010100000000000100000027 +:104190000101010101010000000000000101010115 +:1041A0000101010101010100000000000001010105 +:1041B00001010101010101010000000000010101F4 +:1041C00001010101010101000000000000000000E8 +:1041D00000000000000000020000000000000000DD +:1041E00000000000000200020102020202010202BD +:1041F00001010101010100010101000101010101B1 +:10420000010101010101010101010100000101029F +:104210000101010101010100010101000100010191 +:104220000101010101010100010100010101010180 +:104230000101010101010001000001000001010173 +:104240000101010101010101000000000101010162 +:104250000101010101000100000001000101010153 +:104260000101010101010100010000000001010143 +:104270000101010101010100000000000101010133 +:104280000101010101010100000000000100000026 +:104290000101010101010000000000000101010114 +:1042A0000101010101010100000000000001010104 +:1042B00001010101010101010000000000010101F3 +:1042C00001010101010101000000000000000000E7 +:1042D00000000000000000020000000000000000DC +:1042E00000000000000200020202020202020202BA +:1042F00001010101010100010101000101010101B0 +:10430000010101010101010101010100010101029D +:10431000010101010101010001010101010201018D +:10432000010101010101010001010001010101017F +:104330000101010101010101000001000101010170 +:104340000101010101010101000000000101010161 +:104350000101010101000100010001000101010151 +:104360000101010101010100010000000001010142 +:104370000101010101010100000000000101010132 +:104380000101010101010100000000000100000025 +:104390000101010101010000000000000101010113 +:1043A0000101010101010100000000000001010103 +:1043B00001010101010101010000010000010101F1 +:1043C00001010101010101000000000000000000E6 +:1043D00000000000000000020000000000000000DB +:1043E00000000000000200020202020202020202B9 +:1043F00001010101010100010101000101010101AF +:10440000010101010101010101010100010101019D +:10441000010101010101010101010101010201018B +:10442000010101010101010001010101010101017D +:10443000010101010101010100000100010101016F +:104440000101010101010101000000000101010160 +:104450000101010101000100010001000101010150 +:10446000010101010101010001010001000101013F +:104470000101010101010100010000000101010130 +:104480000101010101010100000000000102000022 +:104490000101010101010000000000000101010112 +:1044A0000101010101010100000000000001010102 +:1044B00001010101010101010000010001010101EF +:1044C00001010101010101000000000000000000E5 +:1044D00000000000000000020000000000000000DA +:1044E00000000000000200020202020202020202B8 +:1044F00002010101010100010101000101010101AD +:10450000010101010101010101010100010101019C +:10451000010101010101010101010101010101018B +:10452000010101010101010001010101010101017C +:10453000010101010101010100000100010101016E +:10454000010101010101010101000000010101015E +:10455000010101010100010001000100010101014F +:10456000010101010101010001010001000101013E +:10457000010101010101010001000000010101012F +:104580000101010101010100000000000102000021 +:104590000101010101010100000000000101010110 +:1045A0000101010101010100000000000001010101 +:1045B00001010101010101010000010001010101EE +:1045C00001010101010101000000000000000000E4 +:1045D00000000000000000020000000000000000D9 +:1045E00000000000000200020202020202020202B7 +:1045F00002020101010100010101010101010101AA +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010001010101010101017B +:10463000010101010101010100000100010101016D +:10464000010101010101010101000000010101015D +:10465000010101010102010001000100010101014C +:10466000010101010101010001010001000101013D +:10467000010101010101010001000000010101012E +:10468000010101010101010000000000010100021F +:10469000010101010101010000000000010101010F +:1046A0000101010101010100000000000001010100 +:1046B00001010101010101010000010001010101ED +:1046C00001010101010101000000000000000000E3 +:1046D00000000000000000020000000000000000D8 +:1046E00000000000000200020202020202020202B6 +:1046F00002020101010100010101010101010101A9 +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:10472000010101010101010001010101010101017A +:10473000010101010101010101010100010101016A +:10474000010101010101010101000000010101015C +:10475000010101010102010001010100010101014A +:10476000010101010101010101010001010101013A +:10477000010101010101010001000000010101012D +:10478000010101010101010000000000010100021E +:10479000010101010101010000000000010101010E +:1047A00001010101010101000000000000010101FF +:1047B00001010101010101010000010001010101EC +:1047C00001010101010101000000000000000000E2 +:1047D00000000000000000020000000000000000D7 +:1047E00000000000000200020202020202020202B5 +:1047F00002020101010100010101010101010101A8 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010100010101010101010179 +:104830000101010101010101010101000101010169 +:10484000010101010101010101000000010101015B +:104850000101010101020100010101000101010149 +:104860000101010101010101010101010101010138 +:10487000010101010101010001010000010101012B +:10488000010101010101010000000000010102011C +:10489000010101010101010000000000010101010D +:1048A00001010101010101000000000000010101FE +:1048B00001010101010101010000010001010101EB +:1048C00001010101010101000000000202000000DD +:1048D00000000000000000020000000000000000D6 +:1048E00000000000000200020202020202020202B4 +:1048F00002020101010100020101010101010101A6 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010100010101010101010178 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010100010101000101010149 +:104960000101010101010101010101010101010137 +:104970000101010101010101010100000101010129 +:10498000010101010101010000000000010102011B +:104990000101010101010100010101000101010109 +:1049A00001010101010101000000000000010101FD +:1049B00001010101010101010000010001010101EA +:1049C00001010101010101000200000202000000DA +:1049D00000000000000000020000000000000000D5 +:1049E00000000000000200020202020202020202B3 +:1049F00002020202020100020101010101010101A2 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010100010101010101010177 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010100010101000101010148 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010100010101010127 +:104A8000010101010101010000000000010101011B +:104A90000101010101010101010101000101010107 +:104AA00001010101010101000000000000010101FC +:104AB00001010101010101010000010001010101E9 +:104AC00001010101010101000200000202000000D9 +:104AD00000000000000000020000000000000000D4 +:104AE00000000000000200020202020202020202B2 +:104AF00002020202020100020101010101010101A1 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010100010101010101010146 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010100010101010126 +:104B8000010101010101010000000000010101011A +:104B90000101010101010101010101000101010106 +:104BA00001010101010101010000000000010101FA +:104BB00001010101010101010000010001010101E8 +:104BC00001010101010101000200020202000000D6 +:104BD00000000000000000020000000000000000D3 +:104BE00000000000000200020202020202020202B1 +:104BF000020202020201010201010101020101019E +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010100010101010101010145 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010100010101010125 +:104C80000101010101010100000001020101010116 +:104C90000101010101010101010101000101010105 +:104CA00001010101010101010001000000010101F8 +:104CB00001010101010101010000010001010101E7 +:104CC00001010101010101000200020202000000D5 +:104CD00000000000000000020000000000000000D2 +:104CE00000000000000200020202020202020202B0 +:104CF000020202020201010202010101020101019C +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010100010101010101010144 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010100010101010124 +:104D80000101010101010100000001010101010116 +:104D90000101010101010101010101000101010104 +:104DA00001010101010101010001000000010101F7 +:104DB00001010101010101010001010001010101E5 +:104DC00001010101010101000200020202000000D4 +:104DD00000000000000000020000000000000000D1 +:104DE00000000000000200020202020202020202AF +:104DF000020202020201010202010101020101019B +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010100010001010101010114 +:104E90000101010101010101010101000101010103 +:104EA00001010101010101010101010000010101F4 +:104EB00001010101010101010001010001010101E4 +:104EC00001010101010101000200020202000000D3 +:104ED00000000000000000020000000000000000D0 +:104EE00000000000000200020202020202020202AE +:104EF0000202020202020102020101010201010199 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010201010180 +:104F20000101010101010101010101010101010171 +:104F30000101010101010102010101010101010160 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010100010001010101010113 +:104F90000101010101010101010101000101010102 +:104FA00001010101010101010101010000010101F3 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101000101010101010101D2 +:104FD00001010101010100020000000000000000C9 +:104FE00000000000000200020202020202020202AD +:104FF0000202020202020102020201020201010196 +:105000000101010101010101010101010101010190 +:10501000010101010101010101010101020101017F +:105020000101010101010101010101010101010170 +:10503000010101010101010201010101010101015F +:10504000010101010101010201010101010101014F +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010100010001010101010112 +:105090000101010101010101010101000101010101 +:1050A00001010101010101010101010000010101F2 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101000101010101010101D1 +:1050D00001010101010100020000000000000000C8 +:1050E00000000000000200020202020202020202AC +:1050F0000202020202020102020201020202020292 +:10510000010101010101010201010101010101018E +:10511000010101010101010202010101020101017C +:10512000010101010101010101010101010101016F +:10513000010101010101010201010101010101015E +:10514000010101010101010201010101010101014E +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:105180000101010101010100010001010101010111 +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010000010101F1 +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101000101010101010101D0 +:1051D00001010101010100020000000000000000C7 +:1051E00000000000000200020202020202020202AB +:1051F0000202020202020102020201020202020291 +:10520000010201010101010201010101010101018C +:105210000101010101010102020202010201010179 +:10522000010101010101010101010102010101016D +:10523000010101010101010201010101010101015D +:10524000010101010101010201010101010101014D +:10525000010101010101010101010201010101013D +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:105280000101010101010100010001010101010110 +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010000010101F0 +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101000101010101010101CF +:1052D00001010101010100020000000000000000C6 +:1052E00000000000000200020202020202020202AA +:1052F0000202020202020102020201020202020290 +:10530000020201010101010201010101010101018A +:105310000101010101010102020202010201010277 +:10532000010101010101010101010102020101016B +:10533000010101010101010201010101010101015C +:10534000010101010101010201010101010101014C +:10535000010101010101010101010201020101013B +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101000101010101010E +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010000010101EF +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101000101010101010101CE +:1053D00001010101010100020000000000000000C5 +:1053E00000000000000100020202020202020202AA +:1053F000020202020202020202020102020202028E +:105400000202020101010102010102010101010187 +:105410000101010101010102020202020201010275 +:105420000102020101010101010101020201010168 +:10543000010101010101010201010201010101015A +:10544000010101010101010201010101010101014B +:10545000010101010101010101010201020101013A +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010000010101EE +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101000000000000000000D5 +:1054D00000000001010100020000000000000000C7 +:1054E00000000000000100020202020202020202A9 +:1054F000020202020202020202020202020202028C +:105500000202020202020102020102010101010182 +:105510000101010101010102020202020201010274 +:105520000102020202010101010101020201010165 +:105530000101010101010102010102010101010159 +:10554000010101010101010201010101010101014A +:105550000101010101010101010102010201010139 +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101020101011A +:10558000010101010101010101010101020101010A +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010001010101EC +:1055B00001010101010101020101010101010101DA +:1055C00001010101010101000000000000000000D4 +:1055D00000000101010100020000000000000000C5 +:1055E00000000000000100020202020202020202A8 +:1055F000020202020202020202020202020202028B +:105600000202020202020102020202010101010180 +:105610000202010101010102020202020201010271 +:105620000102020202010101020101020201010163 +:105630000101010101010102010102010101010158 +:105640000101010101010102010101010201010148 +:105650000101010101010101010102010201010138 +:105660000101010101010102020101010102010127 +:105670000101010101010101010101010201010119 +:105680000101010101010101010101010201010109 +:1056900001010101010101010101010102010101F9 +:1056A00001010101010101010101010001010101EB +:1056B00001010101010101020101010101010101D9 +:1056C00001010101010101000000000000000000D3 +:1056D00001010101010100020000000000000000C2 +:1056E00000000000000100020202020202020202A7 +:1056F000020202020202020202020202020202028A +:10570000020202020202010202020201020102017D +:105710000202010101010102020202020201010270 +:105720000202020202010101020101020201010161 +:105730000101010101010102010102010101010157 +:105740000201010101010102010101010201010146 +:105750000101010101010101020102010202020233 +:105760000201010101010102020101010102010125 +:105770000202010101010101010101010202010115 +:105780000101010101010101010101010201010108 +:1057900001010101010101010101010102010101F8 +:1057A00001010101010101010101010001010101EA +:1057B00001010101010101020101010101010101D8 +:1057C00001010101010101000000000000010101CF +:1057D00001010101010100020000000000000000C1 +:1057E00000000000000100020202020202020202A6 +:1057F0000202020202020202020202020202020289 +:10580000020202020202020202020202020102017A +:10581000020201010202010202020202020101026D +:10582000020202020202010102020102020102025C +:105830000202010101010102010102010202020151 +:105840000202020101010102010101010201010143 +:105850000101010101010101020102010202020232 +:105860000201020101010102020201020102010121 +:10587000020202010101010202010101020202020F +:105880000202010101010101010101010201010105 +:1058900001010101010101010101010102020101F6 +:1058A00001010101010101010101010001010101E9 +:1058B00001010101010101020101010101010101D7 +:1058C00001010101010101000000000000010101CE +:1058D00001010101010100020000000000000000C0 +:1058E00000000000000100020202020202020202A5 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020201020179 +:10591000020201010202010202020202020102026B +:105920000202020202020202020202020202020257 +:10593000020202010101010202010201020202024D +:105940000202020202010102010101010201010140 +:105950000201010101010101020102010202020230 +:10596000020202010202020202020102010202021A +:10597000020202020202020202010101020202020A +:105980000202020101010101010101010201010103 +:1059900001010101010101010101010102020201F4 +:1059A00002010101010101010101010001010101E7 +:1059B00001010101010101020101010101010101D6 +:1059C00001010101010101000000000000010101CD +:1059D00001010101010100010000000000000000C0 +:1059E00000000000000100020202020202020202A4 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020201020178 +:105A10000202010102020102020202020202020269 +:105A20000202020202020202020202020202020256 +:105A3000020202010101010202020201020202024B +:105A4000020202020202020202010101020102013B +:105A5000020202010101010202020201020202022B +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020101010202020209 +:105A800002020201020202010101010102010101FF +:105A900001010101010101020101010102020201F2 +:105AA00002020201010101010101010001010101E4 +:105AB00001010101010101020101010101020101D4 +:105AC00001010101010101000000000000010101CC +:105AD00001010101010101010000000000000000BE +:105AE00000000000000100020202020202020202A3 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020176 +:105B10000202020202020102020202020202020266 +:105B20000202020202020202020202020202020255 +:105B30000202020101010102020202020202020249 +:105B40000202020202020202020101010202020238 +:105B50000202020202010102020202010202020228 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020201010202020207 +:105B800002020202020202010101010102010101FD +:105B900001010101010101020101010102020202F0 +:105BA00002020202020101010101010001010101E1 +:105BB00002020101010101020101010101020102D0 +:105BC00002010101010101000000000000010101CA +:105BD00001010101010101010000000000000000BD +:105BE00000000000000100020202020202020202A2 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020101010102020202020202020248 +:105C40000202020202020202020101010202020237 +:105C50000202020202010202020202020202020225 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020201020202020205 +:105C800002020202020202010101010102010101FC +:105C900001010101010101020201010102020202EE +:105CA00002020202020202020101010001010101DD +:105CB00002020201010101020101020101020202CC +:105CC00002020201010101000000000000000000CA +:105CD00001010101010101010000000000000000BC +:105CE00000000000000100020202020202020202A1 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020101010102020202020202020247 +:105D40000202020202020202020202020202020233 +:105D50000202020202010202020202020202020224 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020201020202020204 +:105D800002020202020202010101010102010101FB +:105D900002010201010201020202020102020202E8 +:105DA00002020202020202020101010001020202D9 +:105DB00002020202020201020101020102020202C7 +:105DC00002020202020101000000000000000000C7 +:105DD00001010101010101020000000000000000BA +:105DE00000000000000100020202020202020202A0 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020102020202020202020243 +:105E40000202020202020202020202020202020232 +:105E50000202020202010202020202020202020223 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202010101010102010101FA +:105E900002020202020201020202020102020202E4 +:105EA00002020202020202020101010001020202D8 +:105EB00002020202020201020101020102020202C6 +:105EC00002020202020202000000010000000000C3 +:105ED00001010101010101020000000000000000B9 +:105EE000000000000001000202020202020202029F +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020102020202020202020242 +:105F40000202020202020202020202020202020231 +:105F50000202020202010202020202020202020222 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020201020102010101F6 +:105F900002020202020201020202020102020202E3 +:105FA00002020202020202020101010001020202D7 +:105FB00002020202020202020101020102020202C4 +:105FC00002020202020202000000010000000000C2 +:105FD00000010101010101020000000000000000B9 +:105FE000000000000001000202020202010202029F +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202010202020202020202020221 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020201020202020101F3 +:1060900002020202020201020202020102020202E2 +:1060A00002020202020202020202010001020202D4 +:1060B00002020202020202020101020102020202C3 +:1060C00002020202020202000000010000000000C1 +:1060D00000000101010101020000000000000000B9 +:1060E000000000000001000202020202020202019E +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:106150000202020202010202020202020202020220 +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020201020202020102F1 +:1061900002020202020201020202020202020202E0 +:1061A00002020202020202020202020001020202D2 +:1061B00002020202020202020202020102020202C0 +:1061C00002020202020202000100000101000000BE +:1061D00000000001010101010000000000000000BA +:1061E000000000000001000202020201010202029E +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020201020202020202020202021F +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020201020202020202EF +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020001020202D1 +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202000100000101000000BD +:1062D00000000001010101010000000000000000B9 +:1062E000000000000001000202020202010202019D +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020201020202020202020202021E +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020001020202D0 +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202000000000001000000BE +:1063D00000000000000101010000000000000000BA +:1063E000000000000001000202020101010201019F +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020201020202020202020202021D +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020001020202CF +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202000000000000000000BE +:1064D00000000000000101010000000000000000B9 +:1064E000000000000001000202020201010102019D +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020201020202020202020202021C +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020002020202CD +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202000000000000000000BD +:1065D00000000000000001010000000000000000B9 +:1065E000000000000001000202020101010201019D +:1065F000010102020202020202020202020202027D +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020002020202CC +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202000000000000000000BC +:1066D00000000000000001010002000000000000B6 +:1066E000020000000001000202010101010101019C +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020002020202CB +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202000000000000000000BB +:1067D00000000000000001010002000000000000B5 +:1067E000020000000001000102020101010101019B +:1067F000010102020202020202020202020202027B +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020102020202C9 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202000000000000000000BA +:1068D00000000000000001010202000000020000B0 +:1068E0000200000202010002010101010101010197 +:1068F000010102010102010202020202020202027D +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020102020202C8 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202000000000000000000B9 +:1069D00000000000000001010202000000020000AF +:1069E0000100000202010001020101010101010197 +:1069F000010101020202020202020202020202027A +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020102020202C7 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202000000000000000000B8 +:106AD00000000000000001010202020000020200AA +:106AE0000100000202000001010101010101010198 +:106AF000010102010101010202020202020202027C +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020102020202C6 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202000000000000000000B7 +:106BD00000000000000001010202020000010200AA +:106BE0000100000101000001010101010101010199 +:106BF000010101010102010202020202020202027B +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020102020202C5 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202000000000000000000B6 +:106CD00000000000000001010201020202010202A4 +:106CE0000200020101000001010101010101010195 +:106CF000010101010101010202020202020202027B +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020102020202C4 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202000000000000000000B5 +:106DD00000000000000001010201020202010102A4 +:106DE0000200010101000001010101010101010195 +:106DF000010101010101010202020202020202027A +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202000000000000000000B4 +:106ED00000000000000001010201020202020101A3 +:106EE0000200020101000001010101010101010193 +:106EF0000101010101010102020202020202020279 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202000000000000000000B3 +:106FD00000000000000000010101010202020201A4 +:106FE0000100010101000001010101010101010194 +:106FF0000101010101010102020202020202020278 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202000000000000000000B2 +:1070D00000000000000000010102010101020202A3 +:1070E0000102010101000001010101010101010191 +:1070F0000101010101010102020202020002020279 +:10710000020202020202020202020202020202025F +:107110000202020202020202020202020102020250 +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C00002020202020202000000000000000000B1 +:1071D00000000000000000000102010101010102A5 +:1071E0000101010101010001010101010101010190 +:1071F000010101010101010002020202000202027A +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202010202024F +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C00002020202020202000001000000000000AF +:1072D00000000000000000000202020101010101A3 +:1072E000010101010101000101010101010101018F +:1072F0000101010101010100000002000000000085 +:10730000020002020202020202020202020202025F +:107310000202020202020201020101010102020252 +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C00002020202020202000001000000000000AE +:1073D00000000000000000000202020202010101A0 +:1073E000010101010101000101010101010101018E +:1073F0000101010101010100000000000100000085 +:107400000000000000000202020202020202020268 +:107410000202020202020201010101010202020152 +:107420000201010101020202020202020202020240 +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D0000202020202020200020102020201010192 +:1074E000010101010101000101010101010101018D +:1074F0000101010101010101000000000100000083 +:107500000000000000000002020202020202020269 +:10751000020202020202020202020202020101024D +:10752000010202020201010202020202020202023E +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D0000202020202020200010101020201010193 +:1075E000010101010101010101010101010101018B +:1075F000010101010101010101010001010101017C +:10760000000100000000000102020102010202026A +:10761000020202020202020201020202020202014C +:10762000020101010102020202020202020202023E +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D0000202020202020200010101010101010194 +:1076E000010101000001010101010101010101018C +:1076F000010101010101010101010101010101017A +:107700000101010101010002010101010102010267 +:107710000101020201010201010101010101010156 +:107720000101010101010102020202020202020240 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020200010101010101010193 +:1077E000010101000001010101010101010101018B +:1077F0000101010101010101010101010101010179 +:107800000101010101010101020202020201020162 +:107810000202010102020101010101010101010154 +:10782000010101010101010202020202020202023F +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020201010101010101010191 +:1078E000000100000001010101010101010101018C +:1078F0000101010101010101010101010101010178 +:107900000101010101010101010102010202010263 +:107910000101020201010201010101010101010154 +:107920000101010101010102020202010102020240 +:107930000202020202020202020201020202020228 +:107940000202020202020202020202020202020217 +:107950000202020202020202020201020102020209 +:107960000202020202020201010101010101010100 +:1079700001010101010101020202020202020202EE +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020201010101010100000093 +:1079E000000000000001010101010101010101018C +:1079F0000101010101010101010101010101010177 +:107A00000101010101010101010101010101010166 +:107A10000101010101010101010101010101010156 +:107A20000101010101010101010101010101010146 +:107A3000010101020202020202020202010202022A +:107A40000202020202020202020202020202020216 +:107A5000020202020202020101010101010101010F +:107A60000101010201010101010101010101010105 +:107A700001010101010101020202020202020202ED +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020201010001010100000093 +:107AE000000000000001010101010101010101018B +:107AF0000101010101010101010101010101010176 +:107B00000101010101010101010101010101010165 +:107B10000101010101010101010101010101010155 +:107B20000101010101010101010101010101010145 +:107B30000101010101010101010100010201010135 +:107B4000010101010101010202020202020202021C +:107B50000202020202020202020202020202020205 +:107B600002020201020202010101010101010101FF +:107B700001010101010101010101010102010101F4 +:107B800001010102010101020202020202020202DB +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020201000000000100000095 +:107BE000000000000001010101010101010101018A +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101020200020002020230 +:107C40000202020202020202020202020002020216 +:107C50000202020202020200000002000200000012 +:107C60000000000200000002020202020202020200 +:107C700002020202020202020202020202020202E4 +:107C800002020201020202020202020202020202D5 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020202B4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020201000000000000000095 +:107CE0000000000000010101010101010101010189 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D4000010101010101010102020202000202021D +:107D5000020202020202020101010101010101010C +:107D600001010101010101020202020202020202FA +:107D700002020202020202000000000000000000F5 +:107D800000000002000000020202020201020202E0 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020201000000000000000094 +:107DE0000000000000010101010101010101010188 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101020101010101010101010111 +:107E600001010101010101020202020202020202F9 +:107E700002020202020202000000000000000000F4 +:107E800000000000000000020202020201020202E1 +:107E900002020202020202020202020200020202C4 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020201000000000000000093 +:107EE0000000000101010101010101010101010185 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101000000000001000000F9 +:107F800000000000000000010101010102010101E7 +:107F900001010101010101000000000000000000DA +:107FA00000000000000000020202020202020202BF +:107FB00002020202020202020202020202020202A1 +:107FC0000202020202020202020202020202020291 +:107FD0000202020202020201000000000000000092 +:107FE0000000000101010101010101010101010184 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101020202020202020202D7 +:1080900002020202020202000000000000000000D2 +:1080A00000000000000000020202020202020202BE +:1080B00002020202020202020202020202020202A0 +:1080C0000202020202020202020202020202020290 +:1080D0000202020202020201000000000000000091 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101000000000000000000D8 +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000020202020202020202AD +:1081C0000202020202020202020202000002020293 +:1081D000020202020202020100000000000101018D +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101000000000000000000C7 +:1082B00000000000000000010101010101010101B5 +:1082C0000101010101010102020202000002020299 +:1082D000020202020202020100010000000101018B +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101020202020202020202A4 +:1083C0000202020202020202020202000002020291 +:1083D0000202020202020201010101010101010186 +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C0000101010101010102000202000002020299 +:1084D0000202020202020201010101010101010185 +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C00001010101010101020002000000000000A0 +:1085D0000202020202020201010101010101010184 +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010200020000000000009F +:1086D0000202020202020201010101010101010183 +:1086E0000101010101010100000000000000000083 +:1086F000000000000000000000000000000000007A +:108700000000000000000002020202020202020257 +:108710000202020202020202020202020202020239 +:108720000202020202020202020202020202020229 +:108730000202020202020202020202020202020219 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020202A9 +:1087B0000202020202020202020202020202020299 +:1087C0000202020202020202000200000000000097 +:1087D0000000020202020201010101010101010186 +:1087E0000101010101010100000000000000000082 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000002020202020202020246 +:108820000202020202020202020202020202020228 +:108830000202020202020202020202020202020218 +:108840000202020202020202020202020202020208 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202020202020202020202D8 +:1088800002020202020202020202020202020202C8 +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202020202A8 +:1088B0000202020202020202020202020202020298 +:1088C000020202020202020000000000000000009A +:1088D0000000000202020201010101010101010187 +:1088E0000101010101010100000000000000000081 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000002020202020202020205 +:1089600002020202020202020202020202020202E7 +:1089700002020202020202020202020202020202D7 +:1089800002020202020202020202020202020202C7 +:1089900002020202020202020202020202020202B7 +:1089A00002020202020202020202020202020202A7 +:1089B0000202020202020202020202020202020297 +:1089C0000202020202020200000000000000000099 +:1089D0000000000000020000000000000000000095 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000053000000000000000043 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000200000000000000000074 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000010000000000000004 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000293 +:108BE0000000000000000000000000020201000080 +:108BF000010100000000020000000101010000006E +:108C00000000000000000000000000010100000062 +:108C1000000000000002000001010000000100004F +:108C20000000000000000002000002000000000040 +:108C30000000000000000000000001010100000130 +:108C40000000000000000000000000000002000022 +:108C50000000000000000000000000000000000014 +:108C60000000000000000001010001000000000001 +:108C700000000000000000010000010001000000F1 +:108C800000000000000000010000010101000000E0 +:108C900000000000000002000200000000010000CF +:108CA00000000000000000010000010101000000C0 +:108CB00000000000000000010000010101000000B0 +:108CC00000000000010000000000010200000000A0 +:108CD0000000000000000000000000000000000292 +:108CE000000000000000000000000002020200017D +:108CF0000101000101000200020101010101000067 +:108D00000000000000020200010200010102000058 +:108D10000000000000020002010101010101000049 +:108D20000000000000010202020201000001000137 +:108D30000000000101020100010101010101000127 +:108D4000000000000000000000000202020200001B +:108D50000000000000000000000000000000000013 +:108D600000000000000201010101010000000100FB +:108D700000000000000201010101010201000100E8 +:108D800000000001000101010101010101010100D8 +:108D900000000000000002010200010101010000CA +:108DA00000000000000101010101010101010100B9 +:108DB00000000000000101010101010101010100A9 +:108DC000000000000100000002020102000100009A +:108DD0000000000000000000000000000000000291 +:108DE000000000000000000000000002020200017C +:108DF0000101000101000100020101010101000067 +:108E00000000000000020202010201010101000055 +:108E10000000000000010101010101010101010048 +:108E20000000000000010202020101010101000135 +:108E30000001000101020101010101010101000124 +:108E40000000000000000200020202020202000014 +:108E50000000000000000000000000000000000012 +:108E600000000000000101010101010000000100FB +:108E700000000000000101010101010101020100E7 +:108E800000000001000101010101010101010100D7 +:108E900000000000000202010201010101010000C6 +:108EA00000000000000101010101010101010100B8 +:108EB00000000000000101010101010101010100A8 +:108EC0000000000001000000020201020001000099 +:108ED0000000000000000000000000000000000290 +:108EE000000000000000000000000002020200017B +:108EF0000101000101000100020101010101000066 +:108F00000000000000010202010201010101000055 +:108F10000000000000010101010101010101010047 +:108F20000000000000010201010101010101000136 +:108F30000001000101010101010101010101010123 +:108F40000000000000000202020202010201000013 +:108F50000000000000000000000000000000000011 +:108F600000000000000101010101010000000100FA +:108F700000000000000101010101010101010100E7 +:108F800000000001000101010101010101010100D6 +:108F900000000000000201010101010101010000C7 +:108FA00000000000000101010101010101010100B7 +:108FB00000000000000101010101010101010100A7 +:108FC0000000000001000000020201010001000099 +:108FD000000000000000000000000000000000028F +:108FE000000000000000000000000002020200017A +:108FF0000101000101000102010101010101000064 +:109000000000000000010102010101010101000056 +:109010000000000100010101010101010101010045 +:109020000000010000010101010101010101000135 +:109030000101010101010101010101010101010120 +:109040000000000100000202020201010101000013 +:10905000000000000000000000020000000200000C +:1090600000000000000101010101010000000100F9 +:1090700000000000000101010101010101010100E6 +:1090800000000001000101010101010101010100D5 +:1090900000000000000201010101010101010000C6 +:1090A00000000000000101010101010101010100B6 +:1090B00000000000000101010101010101010100A6 +:1090C0000000000001000002010101010201000096 +:1090D000000000000000000000000000000000028E +:1090E0000000000000000000000000020202000179 +:1090F0000101000101020102010101010101010060 +:109100000000000000010101010101010101000056 +:109110000000000100010101010101010101010044 +:109120000000010001010101010101010101010132 +:10913000010101010101010101010101010101011F +:109140000000000100000102010101010101000015 +:109150000000000000000000000202020202000005 +:1091600000000000000101010101010000000100F8 +:1091700000000000000101010101010101010100E5 +:1091800000000001000101010101010101010100D4 +:1091900000000000000101010101010101010000C6 +:1091A00000000000000101010101010101010100B5 +:1091B00000000000000101010101010101010100A5 +:1091C0000000000001020002010101010101000094 +:1091D000000000000000000000000000000000028D +:1091E0000000000000000000000000020202000178 +:1091F000010101010102010201010101010101005E +:109200000000010000010101010101010101000054 +:109210000000000100010101010101010101010043 +:109220000000010001010101010101010101010131 +:10923000010101010101010101010101010101011E +:109240000000000100020101010101010101000013 +:109250000000000000000000020202020202000002 +:1092600000000000000101010101010000000100F7 +:1092700000000000000101010101010101010100E4 +:1092800000000001000101010101010101010100D3 +:1092900000000000000101010101010101010100C4 +:1092A00000000000000101010101010101010100B4 +:1092B00000000000000101010101010101010100A4 +:1092C0000000000001020001010101010101000094 +:1092D000000000000000000000000000000000028C +:1092E0000000000000000000000000020202000177 +:1092F000010101010102010101010101010101005E +:109300000000010000010101010101010101010052 +:109310000000000100010101010101010101010042 +:109320000000010001010101010101010101010130 +:10933000010101010101010101010101010101011D +:109340000000000100020101010101010101000012 +:109350000000000000000000020102020201000003 +:1093600000010000000101010101010000000100F5 +:1093700000000001010101010101010101010100E1 +:1093800000000001000101010101010101010100D2 +:1093900000000000000101010101010101010100C3 +:1093A00000000001000101010101010101010100B2 +:1093B00000000000000101010101010101010100A3 +:1093C0000000000001010001010101010101000094 +:1093D000000000000000000000000000000000028B +:1093E0000000000000000000000000020202000176 +:1093F000010101010101010101010101010101005E +:10940000000101000001010101010101010101014F +:109410000000000100010101010101010101010041 +:10942000000001000101010101010101010101012F +:10943000010101010101010101010101010101011C +:109440000000000100020101010101010101000011 +:109450000000000000000200020101010101000003 +:1094600000010000000101010101010000000100F4 +:1094700000000001010101010101010101010100E0 +:1094800000010001000101010101010101010100D0 +:1094900000000000000101010101010101010100C2 +:1094A00000000001000101010101010101010100B1 +:1094B00000000000000101010101010101010100A2 +:1094C0000000000001010001010101010101000093 +:1094D000000000000000000000000000000000028A +:1094E0000000000000000000000000020202000175 +:1094F000010101010101010101010101010101005D +:10950000000101000001010101010101010101014E +:109510000000000100010101010101010101010040 +:10952000000001000101010101010101010101012E +:10953000010101010101010101010101010101011B +:109540000000000100010101010101010101000011 +:109550000000000000000202010101010101000001 +:1095600000010000000101010101010000000100F3 +:1095700000000001010101010101010101010100DF +:1095800000010001000101010101010101010100CF +:1095900000000000000101010101010101010100C1 +:1095A00000000001000101010101010101010100B0 +:1095B00000000000000101010101010101010100A1 +:1095C0000000000001010001010101010101000092 +:1095D0000000000000000000000000000000000289 +:1095E0000000000000000000000000020202000174 +:1095F000010101010101010101010101010101005C +:10960000000101000001010101010101010101014D +:10961000000000010001010101010101010101003F +:10962000000001000101010101010101010101012D +:10963000010101010101010101010101010101011A +:109640000000000100010101010101010101000010 +:109650000000000000000202010101010101000000 +:1096600000010000000101010101010000000100F2 +:1096700000000001010101010101010101010100DE +:1096800000010001000101010101010101010100CE +:1096900000000000000101010101010101010100C0 +:1096A00000000001000101010101010101010100AF +:1096B00000000000000101010101010101010100A0 +:1096C0000000000001010001010101010101000091 +:1096D0000000000000000000000000000000000288 +:1096E0000000000000000000000000020202000272 +:1096F000010101010101010101010101010101005B +:10970000000101010001010101010101010101014B +:10971000000100010001010101010101010101003D +:10972000000001010101010101010101010101012B +:109730000101010101010101010101010101010119 +:10974000000000010001010101010101010100000F +:109750000000000000000102010101010101000000 +:1097600000010001000101010101010000000100F0 +:1097700000000001010101010101010101010100DD +:1097800000010001000101010101010101010100CD +:1097900000000000000101010101010101010100BF +:1097A00000000001000101010101010101010100AE +:1097B000000000000101010101010101010101009E +:1097C000000000000101020101010101010100008E +:1097D0000000000000000000000000000000000287 +:1097E0000000000000000000000000020202000271 +:1097F000010101010101010101010101010101005A +:10980000000101010001010101010101010101014A +:10981000000100010101010101010101010101003B +:10982000000001010101010101010101010101012A +:109830000101010101010101010101010101010118 +:10984000000000010001010101010101010101000D +:109850000000000000000101010101010101000000 +:1098600000010001000101010101010000000100EF +:1098700000000001010101010101010101010100DC +:1098800001010101000101010101010101010100CA +:1098900000000000000101010101010101010100BE +:1098A00000000101000101010101010101010100AC +:1098B000000000000101010101010101010101009D +:1098C000000000000101020101010101010100008D +:1098D0000000000000000000000000000000000286 +:1098E0000000000000000000000000020202000270 +:1098F0000201010101010101010101010101010157 +:109900000001010100010101010101010101010149 +:109910000101000101010101010101010101010039 +:109920000000010101010101010101010101010129 +:109930000101010101010101010101010101010117 +:10994000000001010001010101010101010101000B +:1099500000000000000001010101010101010000FF +:1099600000010001010101010101010000000100ED +:1099700000000001010101010101010101010100DB +:1099800001010101010101010101010101010100C8 +:1099900000000000000101010101010101010100BD +:1099A00000000101010101010101010101010100AA +:1099B000000000000101010101010101010101009C +:1099C000000000000101010101010101010100008D +:1099D0000000000000000000000000000000000285 +:1099E000000000000000000000000002020200026F +:1099F0000202010101010101010101010101010155 +:109A00000001010100010101010101010101010148 +:109A10000101000101010101010101010101010038 +:109A20000000010101010101010101010101010128 +:109A30000101010101010101010101010101010116 +:109A4000000001010001010101010101010101000A +:109A500000000000000201010101010101010000FC +:109A600000010101010101010101010200000100E9 +:109A700000000101010101010101010101010100D9 +:109A800001010101010101010101010101010100C7 +:109A900000000000000101010101010101010100BC +:109AA00000000101010101010101010101010100A9 +:109AB000000000000101010101010101010101009B +:109AC000000000000101010101010101010100008C +:109AD0000000000002000000000000000000000282 +:109AE000000000000000000000000002020200026E +:109AF0000202010202010101010101010101010152 +:109B00000001010101010101010101010101010146 +:109B10000101000101010101010101010101010037 +:109B20000000010101010101010101010101010127 +:109B30000101010101010101010101010101010115 +:109B40000001010100010101010101010101010008 +:109B500000000000000201010101010101010000FB +:109B600000010101010101010101010200000100E8 +:109B700000000101010101010101010101010100D8 +:109B800001010101010101010101010101010100C6 +:109B900000000000000101010101010101010100BB +:109BA00000000101010101010101010101010100A8 +:109BB0000000000101010101010101010101010099 +:109BC000000000000101010101010101010100008B +:109BD000000202020200000000000000000000027B +:109BE000000000000000000000000002020200026D +:109BF0000202010202010101010101010101010151 +:109C00000101010101010101010101010101010144 +:109C10000101000101010101010101010101010036 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000001010100010101010101010101010007 +:109C500000000000000201010101010101010000FA +:109C600000010101010101010101010202000100E5 +:109C700000000101010101010101010101010100D7 +:109C800001010101010101010101010101010100C5 +:109C900000000000000101010101010101010100BA +:109CA00001000101010101010101010101010100A6 +:109CB0000000010101010101010101010101010097 +:109CC000000000000101010101010101010100008A +:109CD000000202020200000000000000000000027A +:109CE000000000000000000000000002020200026C +:109CF0000202010202010101010101010101010150 +:109D00000101010101010101010101010101010143 +:109D10000101000101010101010101010101010134 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000001010100010101010101010101010006 +:109D500000000000000101010101010101010000FA +:109D600000010101010101010101010102000100E5 +:109D700000000101010101010101010101010101D5 +:109D800001010101010101010101010101010100C4 +:109D900000000000000101010101010101010101B8 +:109DA00001000101010101010101010101010100A5 +:109DB0000000010101010101010101010101010096 +:109DC0000000000001010101010101010101010088 +:109DD0000002020202000000000000000000000279 +:109DE000000000000000000000000002020200026B +:109DF000020202020201010101010101010101014E +:109E00000101010101010101010101010101010142 +:109E10000101000101010101010101010101010133 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000001010101010101010101010101010004 +:109E500000000000010101010101010101010100F7 +:109E600001010101010101010101010102000100E3 +:109E700001000101010101010101010101010101D3 +:109E800001010101010101010101010101010100C3 +:109E900000000001000101010101010101010101B6 +:109EA00001010101010101010101010101010100A3 +:109EB0000000010101010101010101010101010095 +:109EC0000000000001010101010101010101010087 +:109ED0000002020202000000000000000000000278 +:109EE000000000000000000000000002020200026A +:109EF000020202020201010101010101010101014D +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000001010101010101010101010101010003 +:109F500000000100010101010101010101010100F5 +:109F600001010101010101010101010101000100E3 +:109F700001000101010101010101010101010101D2 +:109F800001010101010101010101010101010100C2 +:109F900000010001000101010101010101010101B4 +:109FA00001010101010101010101010101010100A2 +:109FB0000000010101010101010101010101010094 +:109FC0000000000001010101010101010101010086 +:109FD0000101010101010101010101010101000271 +:109FE0000000000000000000000000020202000269 +:109FF000020202020201010101020201010101014A +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A02000010101010101010101010101010101021F +:10A030000101010101010101010101010101010110 +:10A040000001010101010101010101010101010101 +:10A0500000000100010101010101010101010100F4 +:10A0600001010101010101010101010101000100E2 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010100C1 +:10A0900000010001000101010101010101010101B3 +:10A0A00001010101010101010101010101010100A1 +:10A0B0000001010101010101010101010101010092 +:10A0C0000000000001010101010101010101010085 +:10A0D0000101010101010101010101010101000270 +:10A0E0000000000000000000000000020202000268 +:10A0F0000202020202010101010202020201010147 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101021E +:10A13000010101010101010101010101010101020E +:10A140000001010101010101010101010101010100 +:10A1500000000100010101010101010101010100F3 +:10A1600001010101010101010101010101020100DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010100C0 +:10A1900000010001000101010101010101010101B2 +:10A1A00001010101010101010101010101010100A0 +:10A1B0000001010101010101010101010101010091 +:10A1C0000000000001010101010101010101010084 +:10A1D000010101010101010101010101010100026F +:10A1E0000000000000000000000000020202000267 +:10A1F0000202020202010201010202020201010145 +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101021D +:10A23000010101010101010101010101010101020D +:10A2400000010101010101010101010101010101FF +:10A2500000000101010101010101010101010100F1 +:10A2600001010101010101010101010101010100DF +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010100BF +:10A2900000010001000101010101010101010101B1 +:10A2A000010101010101010101010101010101009F +:10A2B000010101010101010101010101010101008F +:10A2C0000000000001010101010101010101010083 +:10A2D000010101010101010101010101010100026E +:10A2E0000000000000000000000000020202000266 +:10A2F0000202020202010201010202020202010143 +:10A30000010101010101010101010101010101023C +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101021C +:10A33000010101010101010101010101010101020C +:10A3400000010101010101010101010101010101FE +:10A3500000000101010101010101010101010100F0 +:10A3600001010101010101010101010101010100DE +:10A3700001010101010101010101010101010101CD +:10A3800001010101010101010101010101010100BE +:10A3900001010101000101010101010101010101AE +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101008E +:10A3C0000000000001010101010101010101010082 +:10A3D000010101010101010101010101010100026D +:10A3E0000000000000000000000000020202000265 +:10A3F0000202020202020201020202020202010140 +:10A40000010101010101010101010101010101023B +:10A41000010101010101010101010101010101012C +:10A42000010101010101010101010101010101021B +:10A43000010101010101010101010101010101020B +:10A4400000010101010101010101010101010101FD +:10A4500000000101010101010101010101010100EF +:10A4600001010101010101010101010101010100DD +:10A4700001010101010101010101010101010101CC +:10A4800001010101010101010101010101010101BC +:10A4900001010101000101010101010101010101AD +:10A4A000010101010101010101010101010101019C +:10A4B000010101010101010101010101010101008D +:10A4C0000000000001010101010101010101010081 +:10A4D0000000000000000000000001010101010275 +:10A4E0000000000000000000000000020202000264 +:10A4F000020202020202020202020202020202023C +:10A50000010101010101010101010101010101023A +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101021A +:10A530000202010202010101010101010101010206 +:10A5400001010101010101010101010101010101FB +:10A5500000000101010101010101010101010100EE +:10A5600001010101010101010101010101010101DB +:10A5700001010101010101010101010101010101CB +:10A5800001010101010101010101010101010101BB +:10A5900001010101000101010101010101010101AC +:10A5A000010101010101010101010101010101019B +:10A5B000010101010101010101010101010101018B +:10A5C0000000000001010101010101010101010080 +:10A5D0000000000000000001000101010101010272 +:10A5E0000000000000000000000000020202000263 +:10A5F000020202020202020202020202020202023B +:10A600000101020101010101010101010101010238 +:10A610000101010201010101010101010101010129 +:10A620000101010101010101010101010101010219 +:10A630000202020202010101010101010101010204 +:10A6400001010101010101010101010101010101FA +:10A6500000000101010101010101010101010100ED +:10A6600001010101010101010101010101010101DA +:10A6700001010101010101010101010101010101CA +:10A6800001010102010101010101010101010101B9 +:10A6900001010101000101010101010101010101AB +:10A6A000010101010101010101010101010101019A +:10A6B000010101010101010101010101010101018A +:10A6C000000000000101010101010101010101007F +:10A6D0000000000000000001000101010101010271 +:10A6E0000000000000000000000000020202000262 +:10A6F000020202020202020202020202020202023A +:10A700000102020101010101010101010101010236 +:10A710000101010201010101010101010101010128 +:10A720000101010101010101010101010101010218 +:10A730000202020202010101010101010101010203 +:10A7400001010101010101010101010101010101F9 +:10A7500000000101010101010101010101010101EB +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010102010101010101010101010101B8 +:10A7900001010101000101010101010101010101AA +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C000000000000101010101010101010101007E +:10A7D000000000000001000100010101010101026F +:10A7E0000000000000000000000000010202000262 +:10A7F0000202020202020202020202020202020239 +:10A800000102020101020101020101010101010233 +:10A810000101010201010101010101010101010127 +:10A820000101020101010101010101010101010216 +:10A830000202020202010101010101010101010202 +:10A8400001010102010101010101010101010101F7 +:10A8500000000101010101010101010101010101EA +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010102010201010101010101010101B6 +:10A8900001010101000101010101010101010101A9 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C000000000000101010101010101010101007D +:10A8D000000000000001000100010101010101026E +:10A8E0000000000000000000000000010102000262 +:10A8F0000202020202020202020202020202020238 +:10A90000010202020102010102010202020101022E +:10A910000101010201020201020201010101010122 +:10A920000101020102020101010101010101010213 +:10A930000202020202010201010101010101010200 +:10A9400001010102010101010101010101010101F6 +:10A9500001000101010101010101010101010101E8 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001020102010202020101010101010101B2 +:10A9900001010101000101010101010101010101A8 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C000000000000101010101010101010101007C +:10A9D000000100000001000100010101010101026C +:10A9E0000000000000000000000000010102000261 +:10A9F0000202020202020202020202020202020237 +:10AA0000010202020102010102010202020101022D +:10AA1000020201020102020202020201010101011D +:10AA20000101020102020101010101010101010212 +:10AA300002020202020202020202020101010102FA +:10AA400001010102010101010101010101010101F5 +:10AA500001000101010101010101010101010101E7 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010102C5 +:10AA800002020102010202020202020101010101AD +:10AA900001010101000101010101010101010101A7 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC000000001000101010101010101010101007A +:10AAD000000100000001000100010101010101026B +:10AAE0000000000000000000000000010101000261 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020201020102020201010229 +:10AB10000202010202020202020202020202010217 +:10AB20000101020102020101010101010101010211 +:10AB300002020202020202020202020202010102F7 +:10AB400001010102010101010101010101010101F4 +:10AB500001010101010101010101010101010101E5 +:10AB600001020101010101010101010101010101D4 +:10AB700001010101010101010101010101010102C4 +:10AB800002020202010202020202020202010101A9 +:10AB900001010101000101010101010101010101A6 +:10ABA0000101010101020101010101010101010194 +:10ABB0000101010101010101010101010101010185 +:10ABC0000000010002010101010101010101010078 +:10ABD000000100000001000100010101010101026A +:10ABE0000000000000000000000000010101000260 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202010225 +:10AC10000202010202020202020202020202020215 +:10AC2000010102020202010101010101010101020F +:10AC300002020202020202020202020202020102F5 +:10AC400001010202010101010101010101010101F2 +:10AC500001010101010101010101010101010101E4 +:10AC600001020101010202020201010101010101CF +:10AC700001010102020202020101010101010102BE +:10AC800002020202020202020202020202020201A5 +:10AC900001010101000101010101010101010101A5 +:10ACA0000101010201020202010101010101010190 +:10ACB0000101010101010101010101010101010184 +:10ACC0000000010002010101010101010101010077 +:10ACD000000100000001000100010101010101016A +:10ACE000000000000000000000000001010100025F +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202010224 +:10AD10000202010202020202020202020202020214 +:10AD2000010102020202010101020201010101020C +:10AD300002020202020202020202020202020202F3 +:10AD400001020202010101010101010101010102EF +:10AD500001010101010101010101010101010101E3 +:10AD600001020101010202020202020101010101CC +:10AD700001010102020202020202020101010102BA +:10AD800002020202020202020202020202020201A4 +:10AD900001010101000101020101010101010102A2 +:10ADA000010101020102020202020201010101018C +:10ADB0000101010101020101010101010101010182 +:10ADC0000000010002010101010101010101010076 +:10ADD0000001010100010001000101010101010167 +:10ADE000000000000000000000000001010100025E +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000201020202020202020202020202010204 +:10AE300002020202020202020202020202020202F2 +:10AE400001020202010102010101010101010102ED +:10AE500001010101010101010101010101010101E2 +:10AE600001020102010202020202020101010101CA +:10AE700001010102020202020202020102010102B8 +:10AE800002020202020202020202020202020201A3 +:10AE9000010101010101010201020201010101029E +:10AEA0000101020201020202020202020201010188 +:10AEB000010101010102020201010101010101017F +:10AEC0000000010002010101010101010101010075 +:10AED0000001010101000001000101010101010166 +:10AEE000000000000000000000000001010100025D +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202010202 +:10AF300002020202020202020202020202020202F1 +:10AF400001020202020202020202020201010102E5 +:10AF500001010101010101010101010101010101E1 +:10AF600001020202020202020202020101010201C6 +:10AF700001010202020202020202020102010202B5 +:10AF800002020202020202020202020202020201A2 +:10AF90000101010101020202010202020202010298 +:10AFA0000201020202020202020202020202020183 +:10AFB000010101010102020202020201010101017B +:10AFC0000000010002010101010101010101010074 +:10AFD0000001010101000001000101010101010165 +:10AFE000000000000000000000000001010100025C +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400001020202020202020202020202020102E2 +:10B0500001010201020101010101010101010101DE +:10B0600002020202020202020202020101010201C4 +:10B0700002010202020202020202020202010202B2 +:10B0800002020202020202020202020202020201A1 +:10B090000101010101020202020202020202010296 +:10B0A0000201020202020202020202020202020182 +:10B0B0000101010102020202020202020201010177 +:10B0C0000101010002010101010102010101010070 +:10B0D0000000010101000000000101010101010265 +:10B0E000000000000000000000000001010100025B +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400001020202020202020202020202020102E1 +:10B1500001010201020101010102010101010101DC +:10B1600002020202020202020202020101010202C2 +:10B1700002010202020202020202020202020202B0 +:10B18000020202020202020202020202020202029F +:10B190000101010101020202020202020202010295 +:10B1A0000202020202020202020202020202020180 +:10B1B0000101010102020202020202020202020174 +:10B1C000010101000201010101010201010101006F +:10B1D0000000000001000000000101010101010266 +:10B1E000000000000000000000000001010100025A +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020102DF +:10B2500001010202020102010202020101010102D6 +:10B2600002020202020202020202020101010202C1 +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B290000102010201020202020202020202020291 +:10B2A000020202020202020202020202020202027E +:10B2B0000101020202020202020202020202020171 +:10B2C000010101000202010101010201010201006C +:10B2D0000000000001000000000101010101010265 +:10B2E0000000000000000000000000010101000259 +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500001010202020102020202020202020102D1 +:10B3600002020202020202020202020101010202C0 +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020201020102020202020202020202028F +:10B3A000020202020202020202020202020202027D +:10B3B0000101020202020202020202020202020170 +:10B3C0000101010102020102020202010102010067 +:10B3D0000000000000000000000101010101010265 +:10B3E0000000000000000000000000010101000258 +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500001010202020202020202020202020102CF +:10B4600002020202020202020202020101010202BF +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020102020202020202020202028D +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C0000101010102020102020202020202010064 +:10B4D0000000000000000000000000010001010168 +:10B4E0000000000000000000000000010101000257 +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002010202020202020202020202020102CD +:10B5600002020202020202020202020101010202BE +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020102020202020202020202028C +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C0000101010102020102020202020202010063 +:10B5D0000000000000000000000000000001010168 +:10B5E0000000000000000000000002010101000254 +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202020202020202020202020202EA +:10B6400002020202020202020202020202020202DA +:10B6500002010202020202020202020202020102CC +:10B6600002020202020202020202020101010202BD +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020102020202020202020202028B +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C0000101010102020202020202020202010061 +:10B6D0000000000000000000000000000001010167 +:10B6E0000000000000000000000002010101000253 +:10B6F000020202020202020202020202020202022A +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020101010202BC +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B79000020202020102020202020202020202028A +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000101010102020202020202020202010060 +:10B7D0000000000000000000000000000001010166 +:10B7E0000000000000000000000202010101000250 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020101010202BB +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020201020202020202020202020289 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C000010101010202020202020202020201005F +:10B8D0000000000000000000010000000001010164 +:10B8E0000000000000000000000201010101000250 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020201010202B9 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020201020202020202020202020288 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C000010101010202020202020202020201005E +:10B9D0000000000000000000010000000000010164 +:10B9E000000000000000000002020101010100024D +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202010202B7 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC000010102010202020202020202020202005B +:10BAD0000000000000000100010000000000010162 +:10BAE000000000000000000002010101010100024D +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020202020202020202020202C5 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC000010102010202020202020202020202005A +:10BBD0000000000000000100010000000000010161 +:10BBE000000000000000000001010101010100024D +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000201020102020202020202020202020058 +:10BCD0000000000000000100010000000000010160 +:10BCE000000000000000000001010201010100014C +:10BCF0000101020101020202020202020202020228 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020102020202020202020202020056 +:10BDD000000000000000010001000000000001015F +:10BDE0000000000000000002010102010101000149 +:10BDF0000101020101020202020202020202020227 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020102020202020202020202020055 +:10BED000000000000000010001000000000000015F +:10BEE0000000000000000002010202000101000148 +:10BEF0000101010101020202020202020202020227 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020053 +:10BFD000000000000000010001000000000000015E +:10BFE0000002000200020001020202000101000240 +:10BFF0000202010202020202020101010102020226 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020052 +:10C0D000000000000000010001000000000000015D +:10C0E0000002000200020001020201000001000241 +:10C0F0000202020202010101010202020201010226 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C0000202020202020202020202020202020051 +:10C1D000000000000000010001000000000000015C +:10C1E000020202020001020202020100000100023A +:10C1F0000202020202020202020101010102020223 +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C0000202020202020202020202020202020050 +:10C2D000000000000000010001000000000000015B +:10C2E000020202020001020202010100000000013C +:10C2F000010101010101010101010101010101022D +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202013E +:10C3E000020202010001020101010100000100013D +:10C3F000010101010101010101010101010101022C +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202003E +:10C4E000020102010002010101010101010100013B +:10C4F000010101010101010101010101010101022B +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202003D +:10C5E0000201010102020101010101010101000139 +:10C5F000010101010101010101010101010101022A +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202003C +:10C6E0000102010202020101010101010101000137 +:10C6F0000101010101010101010101010101010229 +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020202020202020202020202020249 +:10C7D000020202020202020202020202020202003B +:10C7E0000102020201010101010101010101000137 +:10C7F0000101010101010101010101010101010129 +:10C80000020101010202020202020202020202010C +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020200EA +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020202020202020202020202020248 +:10C8D000020202020202020202020202020202003A +:10C8E0000201020201010101010101010101010135 +:10C8F0000101010101010101010101010101010227 +:10C90000020101020101020201020101010202020F +:10C9100002020201020202020202020202020202F8 +:10C9200002020202020202020202020202020200E9 +:10C9300000000000000202020202020202020202E1 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020257 +:10C9C0000202020202020202020202020202020247 +:10C9D0000202020202020202020202020202020039 +:10C9E0000201010102010101010101010101010135 +:10C9F0000101010101010101010101010101010127 +:10CA0000010202000202010102010202020101010F +:10CA10000101010201010101010101010101010204 +:10CA200002020202020202020202020202020200E8 +:10CA300000000000000000000000000000000002F4 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020038 +:10CAE0000101010102010101010100010101010136 +:10CAF0000101010101010101010101010101010126 +:10CB0000020202000101020201020101010202010E +:10CB100002020201020202020202020202020202F6 +:10CB200002020202020202020202020202020201E6 +:10CB300000000000000000000000000000000002F3 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020196 +:10CB80000101010101010101010101010101010294 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020136 +:10CBE0000101010101010100010000010101010138 +:10CBF0000101010101010101010101010101010125 +:10CC00000101010101010101010101010101010114 +:10CC10000101010101010101010101010101010203 +:10CC200002020200020202020202020202020201E7 +:10CC300001010101010000000000000000000001EE +:10CC400002010102010202020202020202020202C7 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020195 +:10CC80000101010101010101010101010101010293 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020135 +:10CCE0000101010101010000000000010101010139 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200002020100010102020202020202020201E9 +:10CD300001010101010101010101010101010102E2 +:10CD400002020201020202020202020202020202C4 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020134 +:10CDE0000101010101010000000000010101010138 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001000002000101010101010101010102D3 +:10CE500002020101010202020202020202020202B5 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020202020252 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020133 +:10CEE000010000010100000000000001010101013A +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400002000001000202020202020202020202C8 +:10CF500002020202010202020202020202020202B2 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020093 +:10CF8000000000000000000000000000000000029F +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020132 +:10CFE000000000000100000000000001010101013B +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010101010101010101010110 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010000020101010101010101010102C0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020092 +:10D08000000000000000000000000000000000029E +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202020202020202020202020202020131 +:10D0E000000000000000000000000001010101013B +:10D0F0000101010101010101010101010101010120 +:10D10000010101010101010101010101010101010F +:10D1100001010101010101010101010101010101FF +:10D1200001010101010101010101010101010101EF +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500002020000020202020202020202020202B3 +:10D1600002000202020202020202020202020201A2 +:10D17000010101010101010101010102010201009E +:10D18000000000000000000000000000000000029D +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020202020202020202020202023F +:10D1D0000202020202020202020202020202020130 +:10D1E000000000000000000000000001010101013A +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010202020102AA +:10D270000202020202020202020202010201020092 +:10D28000000000000000000000000000000000029C +:10D290000202020202020202020202020202020070 +:10D2A000000000000000000000000000000000027C +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D000020202020202020202020202020202012F +:10D2E0000000000000000000000101010101010137 +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010100AE +:10D3700000000000000000000000000200020001A8 +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101007E +:10D3A000000000000000000000000000000000027B +:10D3B000020202020202020202020202020202024D +:10D3C000020202020202020202020202020202023D +:10D3D000020202020202020202020202020202012E +:10D3E0000000000000000101010101010101010133 +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010101FC +:10D4200001010101010101010101010101010101EC +:10D4300001010101010101010101010101010101DC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101007D +:10D4A000000000000000000000000000000000027A +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020202020202020202023C +:10D4D0000202020000020202020202020202020131 +:10D4E0000000000000000101010101010101010132 +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101006C +:10D5B0000000000000000000000000000000000269 +:10D5C000020202020202020202020202020202023B +:10D5D0000202000000020202020202020202020132 +:10D5E0000000000000010101010101010101010130 +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010101CA +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010101AA +:10D67000010101010101010101010101010101019A +:10D68000010101010101010101010101010101018A +:10D69000010101010101010101010101010101017A +:10D6A000010101010101010101010101010101016A +:10D6B0000101010101010101010101010101010259 +:10D6C000020202020002020202020202020202023C +:10D6D0000202000000020202020202020202020131 +:10D6E000000101010001010101010101010101012C +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010101A9 +:10D770000101010101010101010101010101010199 +:10D780000101010101010101010101010101010189 +:10D790000101010101010101010101010101010179 +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C000010101010101010101010101010101004A +:10D7D0000002000000000002000202020202020138 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010049 +:10D8D000000000000000000000020202020202013B +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010101010101010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010048 +:10D9D000000000000000000000020202000202013C +:10D9E0000101010101010101010101010101010028 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000214 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202020202020038 +:10DAD000000000000000000000020200000202013D +:10DAE0000101010101010101010101010101010027 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000002F3 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB0000202020202020202020202020202020245 +:10DBC0000202020202020202020202020202020037 +:10DBD0000000000000000000000000000002020140 +:10DBE0000101010101010101010101010101010026 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000002A2 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB0000202020202020202020202020202020244 +:10DCC0000202020202020202020202020202020036 +:10DCD0000000000000000000000000000002020040 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD00000000000000000000000000000000052F1 +:10DDE0000000000000000002000002020000020229 +:10DDF000020000020101000100000001000000001B +:10DE0000010100010001000000000000010001000C +:10DE100000000000010000000001000001000100FE +:10DE200000000200000000000000010000010001ED +:10DE300000000100020000000001000000020001DB +:10DE400000000100010000000000000000010102CC +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000101000000020100000000000102010178 +:10DEA000000001000100000000000000010101016C +:10DEB0000000010001000000000000000000000060 +:10DEC000010100010001000000000000000000004E +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000002000002020000020228 +:10DEF0000200000201010001010001010101010114 +:10DF00000101010101010001000000000100010008 +:10DF100001010001010100010001000101000100F7 +:10DF200001010102000100000000010000010001E8 +:10DF300001010102020200000001000000020001D4 +:10DF400001010100010000000000000000010102C9 +:10DF500002020002000200000101000000020202B1 +:10DF600000000100010000000000000000000000AF +:10DF700000000000000000000000000000000000A1 +:10DF8000000000000000000000000000010201018C +:10DF90000101020002020100000000000102010173 +:10DFA0000101010101010100000000010101010165 +:10DFB0000101010101010100000000000100000257 +:10DFC000010101010101000000000000000000004B +:10DFD000000000000000000000020202000000003B +:10DFE0000000000000000002000002020000020227 +:10DFF0000200000202020001010001010101010111 +:10E000000101010101010001000000000101010105 +:10E0100001010101010100010001010101020102F0 +:10E0200001010101010100000000010001010001E6 +:10E0300001010102020200000101000000020201D0 +:10E0400001010100010000000000000000010101C9 +:10E0500002020202020100000101000000020201AE +:10E0600001010101010100000000000000000000AA +:10E0700000000000000000000000000000000000A0 +:10E08000000000000000000000000000010201018B +:10E090000101020002010100000000000102010173 +:10E0A0000101010101010100000000010101010164 +:10E0B0000101010101010100000000000100000256 +:10E0C0000101010101010000000000000101000147 +:10E0D0000000010001000000000202020000000038 +:10E0E0000000000000000002000002020000020226 +:10E0F000020000020202000101010101010101010F +:10E100000101010101010001000000000101010104 +:10E1100001010101010100010001010101020101F0 +:10E1200001010101010100000000010001010001E5 +:10E1300001010102010100000101000000010101D3 +:10E1400001010100010001000000000100010101C6 +:10E1500001020101010100000101000000020201B1 +:10E1600001010101010100000000000000000000A9 +:10E17000000000000000000000000000000000009F +:10E180000000000002000000000000000102010188 +:10E190000101020001010100000000000101010174 +:10E1A0000101010101010100000000010101010163 +:10E1B0000101010101010100000000000102020251 +:10E1C0000101010101010000000000000101000146 +:10E1D0000101010101010100000202020000000032 +:10E1E0000000000000000002000002020000020225 +:10E1F000020000020202000101010101010101010E +:10E200000101010101010101000000000101010102 +:10E2100001010101010100010001010101020101EF +:10E2200001010101010100000000010001010201E2 +:10E2300001010101010100000101000001010101D2 +:10E2400001010100010001000000000100010101C5 +:10E2500001010101010100000101000000010101B3 +:10E2600001010101010100000000000000000000A8 +:10E27000000000000200000000000000000000009C +:10E280000000000202020000000000000101010184 +:10E290000101010001010100000000000101010174 +:10E2A0000101010101010100000000010101010162 +:10E2B0000101010101010100000000000102020151 +:10E2C0000101010101010000000000000101020143 +:10E2D0000101010101010100000202020000000031 +:10E2E0000000000000000002000002020000020224 +:10E2F000020000020202000101010101010101010D +:10E300000101010101010101000000010101010100 +:10E3100001010101010100010001010101010101EF +:10E3200001010101010101010000010001010201DF +:10E3300001010101010100000101000001010101D1 +:10E3400001010100010201010000000100010101C1 +:10E3500001010101010100000101000000010101B2 +:10E3600001010101010100000000000000000000A7 +:10E370000000000202020000000000000000000097 +:10E380000000020202020000000000000101010181 +:10E390000101010001010100000000000101010173 +:10E3A0000101010101010100000000010101010161 +:10E3B0000101010101010100000000000101010152 +:10E3C0000101010101010000000000000101010143 +:10E3D000010101010101010001010101010101012E +:10E3E000010101010101010200000202000002021C +:10E3F000020000020202000101010101010101010C +:10E4000001010101010101010000010101010101FE +:10E4100001010101010100010101010101010101ED +:10E4200001010101010101010000010001010201DE +:10E4300001010101010100000101000001010101D0 +:10E4400001010100010201010000000100010101C0 +:10E4500001010101010100000101000000010101B1 +:10E4600001010101010101000000000000000000A5 +:10E470000000000202020000000000000000000096 +:10E48000020002020102000000000000010101017F +:10E490000101010001010100000000000101010172 +:10E4A000010101010101010000000101010101015F +:10E4B0000101010101010100000000000101010151 +:10E4C0000101010101010000000000000101010142 +:10E4D000010101010101010001010101010101012D +:10E4E000010101010101010200000202000002021B +:10E4F000020000020202000101010101010101010B +:10E5000001010101010101010000010101010101FD +:10E5100001010101010100010101010101010101EC +:10E5200001010101010101010000010001010101DE +:10E5300001010101010100000101000001010101CF +:10E5400001010102010201010000000100010101BD +:10E5500001010101010100000101000001010101AF +:10E5600001010101010101000000000000000000A4 +:10E570000200000201020000000000000000000094 +:10E580000200020101010000000000000101010180 +:10E590000101010001010100000000010101010170 +:10E5A000010101010101010100000101010101015D +:10E5B0000101010101010100000000000101010150 +:10E5C0000101010101010000000000000101010141 +:10E5D000010101010101010001010101010101012C +:10E5E000010101010101010200000202000002021A +:10E5F000020000020202000101010101010101010A +:10E6000001010101010101010100010101010101FB +:10E6100001010101010100010101010101010101EB +:10E6200001010101010101010000010001010101DD +:10E6300001010101010100000101000001010101CE +:10E6400001010102010101010000010101010101BB +:10E6500001010101010100000101000001010101AE +:10E6600001010101010101000000000000000002A1 +:10E670000200020101010000000000000000000093 +:10E68000020201010101000000000000010101017E +:10E69000010101000101010000000001010101016F +:10E6A000010101010101010100000101010101015C +:10E6B000010101010101010000000000010101014F +:10E6C000010101010101010000000100010101013E +:10E6D000010101010101010001010101010101012B +:10E6E0000101010101010102000002020000020219 +:10E6F0000200000202020001010101010101010109 +:10E7000001010101010101010100010101010101FA +:10E7100001010101010101010101010101010101E9 +:10E7200001010101010101010000010001010101DC +:10E7300001010101010101000101000001010101CC +:10E7400001010102010101010000010101010101BA +:10E7500001010101010101000101000001010101AC +:10E7600001010101010101000000000000000002A0 +:10E77000020202010101000000000000000000028E +:10E78000010201010101000000000000010101017E +:10E79000010101020101010000000001010101016C +:10E7A000010101010101010100000101010101015B +:10E7B000010101010101010000000000010101014E +:10E7C000010101010101010000000100010101013D +:10E7D000010101010101010001010101010101012A +:10E7E0000101010101010102000002020000020218 +:10E7F0000200000202020002010101010101010107 +:10E8000001010101010101010101010101010101F8 +:10E8100001010101010101010101010101010101E8 +:10E8200001010101010101010001010001010101DA +:10E8300001010101010101000101000001010101CB +:10E8400001010101010101010100010101010101B9 +:10E8500001010101010101010101000001010101AA +:10E86000010101010101010000000000000000029F +:10E87000010202010101000000000000000000028E +:10E88000010201010101000000000001010101017C +:10E89000010101010101010000000001010101016C +:10E8A0000101010101010101000101010101010159 +:10E8B000010101010101010000000000010101014D +:10E8C000010101010101010000000100010101013C +:10E8D0000101010101010100000000000000000031 +:10E8E000000000000000010200000202000002021D +:10E8F0000200000202020002010101010101010106 +:10E9000001010101010101010101010101010101F7 +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010001010101010101D8 +:10E9300001010101010101010101000001010101C9 +:10E9400001010101010101010100010101010101B8 +:10E9500001010101010101010101000001010101A9 +:10E96000010101010101010000000000000000019F +:10E97000010201010101000000000000000002028C +:10E98000010101010101000000000001010101017C +:10E99000010101010101010000000001010101016B +:10E9A0000101010101010101000101010101010158 +:10E9B000010101010101010000000000010101014C +:10E9C000010101010101010000000100010101013B +:10E9D0000101010101010100000000000000000030 +:10E9E000000000000000010200000202000002021C +:10E9F0000200000202020002010101010101010105 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010001010101010101D7 +:10EA300001010101010101010101010001010101C7 +:10EA400001010101010101010100010101010101B7 +:10EA500001010101010101010101000001010101A8 +:10EA6000010101010101010000000000000002019C +:10EA7000010101010101000000000000000002018D +:10EA8000010101010101000000000001010101017B +:10EA90000101010101010100000100010101010169 +:10EAA0000101010101010101010101010101010156 +:10EAB000010101010101010000000000010101014B +:10EAC000010101010101010000000100010101013A +:10EAD000010101010101010000000000000000002F +:10EAE000000000000000010200000202000002021B +:10EAF0000200000202020002010101010101010104 +:10EB000001010101010101010101010101010101F5 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101010001010101010101D6 +:10EB300001010101010101010101010101010101C5 +:10EB400001010101010101010100010101010101B6 +:10EB500001010101010101010101000001010101A7 +:10EB6000010101010101010000000000000002019B +:10EB7000010101010101000000000000000202018A +:10EB8000010101010101000000000001010101017A +:10EB90000101010101010100000100010101010168 +:10EBA0000101010101010101010101010101010155 +:10EBB000010101010101010000000000010101014A +:10EBC0000101010101010100000001000101010139 +:10EBD000010101010101010000000000000000002E +:10EBE000000000000000010200000202000002021A +:10EBF0000200000202020002020101010101010102 +:10EC000001010101010101010101010101010101F4 +:10EC100001010101010101010101010101010101E4 +:10EC200001010101010101010101010101010101D4 +:10EC300001010101010101010101010101010101C4 +:10EC400001010101010101010100010101010101B5 +:10EC500001010101010101010101000101010101A5 +:10EC6000010101010101010000000000000002019A +:10EC7000010101010101000000000000000201018A +:10EC80000101010101010000000000010101010179 +:10EC90000101010101010100000101010101010166 +:10ECA0000101010101010101010101010101010154 +:10ECB0000101010101010100000000000101010149 +:10ECC0000101010101010100000001000101010138 +:10ECD000010101010101010000000000000000002D +:10ECE0000000000000000102000002020000020219 +:10ECF00002000002020200020201020201010101FF +:10ED000001010101010101010101010101010101F3 +:10ED100001010101010101010101010101010101E3 +:10ED200001010101010101010101010101010101D3 +:10ED300001010101010101010101010101010101C3 +:10ED400001010101010101010100010101010101B4 +:10ED500001010101010101010101000101010101A4 +:10ED60000101010101010101000000000000010199 +:10ED70000101010101010000000000000102010188 +:10ED80000101010101010000000001010101010177 +:10ED90000101010101010101000101010101010164 +:10EDA0000101010101010101010101010101010153 +:10EDB0000101010101010100000000000101010148 +:10EDC0000101010101010100000001000101010137 +:10EDD000010101010101010000000000000000002C +:10EDE0000000000000000102000002020000020218 +:10EDF00002000002020200020202020201010101FD +:10EE000001010101010101020101010101010101F1 +:10EE100001010101010101010101010101010101E2 +:10EE200001010101010101010101010101010101D2 +:10EE300001010101010101010101010101010101C2 +:10EE400001010101010101010100010101010101B3 +:10EE500001010101010101010101000101010101A3 +:10EE60000101010101010101000000000002010196 +:10EE70000101010101010000000000000101010188 +:10EE80000101010101010000000001010101010176 +:10EE90000101010101010101000101010101010163 +:10EEA0000101010101010101010101010101010152 +:10EEB0000101010101010100000000000101010147 +:10EEC0000101010101010100000001000101010136 +:10EED000010101010101010000000000000000002B +:10EEE0000000000000000102000002020000020217 +:10EEF00002000002020200020202020201010101FC +:10EF000001010101010101020101010101010101F0 +:10EF100001010101010101020101010101010101E0 +:10EF200001010101010101010101010101010101D1 +:10EF300001010101010101010101010101010101C1 +:10EF400001010101010101010100010101010101B2 +:10EF500001010101010101010101010101010101A1 +:10EF60000101010101010101000000000002010195 +:10EF70000101010101010000000000000101010187 +:10EF80000101010101010000000101010101010174 +:10EF90000101010101010101000101010101010162 +:10EFA0000101010101010101010101010101010151 +:10EFB0000101010101010100000000000101010146 +:10EFC0000101010101010100000001010101010134 +:10EFD000010101010101010000000000000000002A +:10EFE0000000000000000102000002020000020216 +:10EFF00002000002020200020202020201020101FA +:10F0000001010101010101020101010101010101EF +:10F0100001010101010101020101010101010101DF +:10F0200001010101010101010101010101010101D0 +:10F0300001010101010101010101010101010101C0 +:10F0400001010101010101010100010101010101B1 +:10F0500001010101010101010101010101010101A0 +:10F060000101010101010101000001000002010193 +:10F070000101010101010000000000000101010186 +:10F080000101010101010100000101010101010172 +:10F090000101010101010101010101010101010160 +:10F0A0000101010101010101010101010101010150 +:10F0B0000101010101010100000000000101010145 +:10F0C0000101010101010100000001010101010133 +:10F0D0000101010101010100000000000000000029 +:10F0E0000000000000000102000002020000020215 +:10F0F00002000002020200020202020202020101F8 +:10F1000001010101010101020101010101010101EE +:10F1100001010101010101020101010101010101DE +:10F1200001010101010101010101010101010101CF +:10F1300001010101010101010101010101010101BF +:10F1400001010101010101010100010101010101B0 +:10F15000010101010101010101010101010101019F +:10F160000101010101010101000001010001010192 +:10F170000101010101010100000000000101010184 +:10F180000101010101010100000101010101010171 +:10F19000010101010101010101010101010101015F +:10F1A000010101010101010101010101010101014F +:10F1B0000101010101010100000000000101010144 +:10F1C0000101010101010100000001010101010132 +:10F1D0000101010101010100000000000000000028 +:10F1E0000000000001010102000002020000020212 +:10F1F00002000002020200020202020202020201F6 +:10F2000001020101010101020101010101010101EC +:10F2100001010101010101020101010101010101DD +:10F2200001010101010101010101010101010101CE +:10F2300001010101010101010101010101010101BE +:10F2400001010101010101010101010101010101AE +:10F25000010101010101010101010101010101019E +:10F260000101010101010101000001010101010190 +:10F270000101010101010100000000000101010183 +:10F280000101010101010100000101010101010170 +:10F29000010101010101010101010101010101015E +:10F2A000010101010101010101010101010101014E +:10F2B0000101010101010100000000000101010143 +:10F2C0000101010101010100000001010101010131 +:10F2D0000101010101010100000000000000000126 +:10F2E000000101010101010200000202000002020E +:10F2F00002000002020200020202020202020202F4 +:10F3000001020101010101020101010101010101EB +:10F3100001010101010101020101010101010101DC +:10F3200001010101010101010101010101010101CD +:10F3300001010101010101010101010101010101BD +:10F3400001010101010101010101010101010101AD +:10F35000010101010101010101010101010101019D +:10F36000010101010101010100000101010101018F +:10F370000101010101010100000001000101010181 +:10F38000010101010101010001010101010101016E +:10F39000010101010101010101010101010101015D +:10F3A000010101010101010101010101010101014D +:10F3B0000101010101010100000000000101010142 +:10F3C000010101010101010100000101010101012F +:10F3D0000101010101010100000000000000000125 +:10F3E000010101010101010200000202000002020C +:10F3F00002000002020200020202020202020202F3 +:10F4000002020102010101020101010101010101E8 +:10F4100001010101010101020102010101010101DA +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010101010101010101010101010101AC +:10F45000010101010101010101010101010101019C +:10F46000010101010101010100010101010101018D +:10F470000101010101010100000001000101010180 +:10F48000010101010101010001010101010101016D +:10F49000010101010101010101010101010101015C +:10F4A000010101010101010101010101010101014C +:10F4B0000101010101010100000000010101010140 +:10F4C000010101010101010100000101010101012E +:10F4D0000101010101010100000000000000000124 +:10F4E000010101010101010200000202000002020B +:10F4F00002000002020200020202020202020202F2 +:10F5000002020202010101020101010101010101E6 +:10F5100001010101010101020102020201010101D7 +:10F5200001010101010101020101010101010101CA +:10F5300001010101010101010101010101010101BB +:10F5400001010101010101020101010101010101AA +:10F55000010101010101010101010101010101019B +:10F56000010101010101010100010101010101018C +:10F57000010101010101010000010100010101017E +:10F58000010101010101010001010101010101016C +:10F59000010101010101010101010101010101015B +:10F5A000010101010101010101010101010101014B +:10F5B000010101010101010000000101010101013E +:10F5C000010101010101010100000101010101012D +:10F5D0000101010101010100000000000000000123 +:10F5E000010101010101010200000202000002020A +:10F5F00002000002020200020202020202020202F1 +:10F6000002020202020201020101010101010101E3 +:10F6100001010101010101020202020201010101D5 +:10F6200001010101010101020101010101010101C9 +:10F6300001010101010101010101010101010101BA +:10F6400001010101010101020101010101010101A9 +:10F65000010101010101010101010101010101019A +:10F66000010101010101010101010101010101018A +:10F67000010101010101010000010100010101017D +:10F68000010101010101010001010101010101016B +:10F69000010101010101010101010101010101015A +:10F6A000010101010101010101010101010101014A +:10F6B000010101010101010000000101010101013D +:10F6C000010101010101010100000101010101012C +:10F6D0000101010101010100000100010000000120 +:10F6E0000101010101010102000002020000020209 +:10F6F00002000002020200020202020202020202F0 +:10F7000002020202020201020201020202020201DC +:10F7100001010101010101020202020201010101D4 +:10F7200001010101010101020101020101010101C7 +:10F7300001010101010101010202010101010101B7 +:10F7400001010101010101020101010101010101A8 +:10F750000101010101010101020101010101010198 +:10F760000101010101010101010101010101010189 +:10F77000010101010101010000010100010101017C +:10F78000010101010101010001010101010101016A +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B000010101010101010000000101010101013C +:10F7C000010101010101010100000101010101012B +:10F7D000010101010101010000010001000000011F +:10F7E0000101010101010102000002020000020208 +:10F7F00002000002020200020202020202020202EF +:10F8000002020202020202020201020202020201DA +:10F8100001010101010101020202020202010201D1 +:10F8200001010101010101020101020101010101C6 +:10F8300001010101010101010202010101010101B6 +:10F8400001010101010101020101010101010101A7 +:10F850000101010101010101020201010101010196 +:10F860000101010101010101010101010101010188 +:10F87000010101010101010000010100010101017B +:10F880000101010101010100010101010101010169 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B000010101010101010000000101010101013B +:10F8C000010101010101010100000101010101012A +:10F8D000010101010101010000010001000000011E +:10F8E0000101010101010102000002020000020207 +:10F8F00002000002020200020202020202020202EE +:10F9000002020202020202020202020202020201D8 +:10F9100001020101010101020202020202010201CF +:10F9200001010101010101020101020101020101C4 +:10F9300001010101010101020202010101010101B4 +:10F9400001010101010101020101010201020101A4 +:10F950000101010101010102020201010101010194 +:10F960000101010101010101010101010101010187 +:10F970000101010101010100010101000101010179 +:10F980000101010101010100010101010101010168 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B000010101010101010000000101010101013A +:10F9C0000101010101010101000001010101010129 +:10F9D000010101010101010000010001000000011D +:10F9E0000101010101010102000002020000020206 +:10F9F00002000002020200020202020202020202ED +:10FA000002020202020202020202020202020202D6 +:10FA100002020101010101020202020202010201CD +:10FA200001020101010101020101020101020101C2 +:10FA300001010101010101020202010101010101B3 +:10FA400001010101010101020101010201020201A2 +:10FA50000101010101010102020201010101010193 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010100010101010101010177 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010100000001010101010139 +:10FAC0000101010101010101000001010101010128 +:10FAD000010101010101010000010101000000011B +:10FAE0000101010101010102000001010000020207 +:10FAF00002000002020200020202020202020202EC +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020101020202020202010201C9 +:10FB200002020101010101020101020101020101C0 +:10FB300001010101010101020202010101010101B2 +:10FB4000010101010101010202010202010202019F +:10FB50000101010101010102020201010101010192 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010100010101010101010176 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010102010101010101010144 +:10FBB0000101010101010100010101010101010136 +:10FBC0000101010101010101000001010101010127 +:10FBD000010101010101010000010101000000011A +:10FBE0000101010101010102000001010000010108 +:10FBF00002000001020200020202020202020202EC +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020201020202020202020202C5 +:10FC200002020201010101020101020102020102BC +:10FC300001010101010101020202010101010102B0 +:10FC4000010101010101010202010202010202019E +:10FC50000101010101010102020201010101010191 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010100010101010101010175 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010201020152 +:10FCA0000101010101010102010101020101010142 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101000001010101010126 +:10FCD0000101010101010100000101010000000119 +:10FCE0000101010101010102000001010000020106 +:10FCF00001000001020200020202020202020202EC +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020201020202020202020202C4 +:10FD200002020202020201020102020102020102B7 +:10FD300002020201010101020202010102020202A9 +:10FD4000020202010101010202010202010202019A +:10FD50000101010101010102020201010101010190 +:10FD60000101010101010102010101010101010182 +:10FD70000101010101010100010101010101010174 +:10FD80000101010101010101010101010101010163 +:10FD9000010101010101010201010102020102024E +:10FDA0000101010101010102010101020102010140 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101000001010101010125 +:10FDD0000101010101010100000101010000000118 +:10FDE0000101010101010102000001010000010106 +:10FDF00001000001020100020202020202020202EC +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020201020202020202020202C3 +:10FE200002020202020201020202020202020102B4 +:10FE300002020201010101020202020102020202A7 +:10FE40000202020102010102020102020102020297 +:10FE5000010101010101010202020101010201028D +:10FE6000020202010101010201010101010101017E +:10FE70000101010101010100010101010101010173 +:10FE80000101010101010101010101010101010162 +:10FE9000010101010101010201010102020202024C +:10FEA0000202020101010102010102020202020139 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101000101010101010123 +:10FED0000101010101010100000001010000000118 +:10FEE0000101010101010101000002020000010104 +:10FEF00001000001010100020202020202020202EC +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020201020202020202020202C2 +:10FF200002020202020202020202020202020102B2 +:10FF300002020201010101020202020202020202A5 +:10FF40000202020102010102020102020202020295 +:10FF50000201020101010102020201010202020288 +:10FF6000020202020201010201010101010101017B +:10FF70000101010101010100010101010101010172 +:10FF8000010101010101010101010101020102015F +:10FF9000010101010101010201020102020202024A +:10FFA0000202020202010102010102020202020235 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101000101010101010122 +:10FFD0000101010101010100000001000000000118 +:10FFE0000101010101010101000002020000010103 +:10FFF00001000001010100020202020202020202EB +:020000040012E8 +:1000000002020202020202020202020202020202D0 +:1000100002020202020201020202020202020202C1 +:1000200002020202020202020202020202020102B1 +:1000300002020201010101020202020202020202A4 +:100040000202020102010202020102020202020293 +:100050000202020202020102020201020202020282 +:100060000202020202020102010101010101010179 +:100070000101010101010100010101010101010171 +:10008000010101010101010101010101020102025D +:100090000202010101010102010202020202020246 +:1000A0000202020202020202020202020202020230 +:1000B000020202010101010101010101020101012C +:1000C000010101010101010101010101010201011F +:1000D0000101010101010100000000000000000118 +:1000E0000101010101010101000002020000010102 +:1000F00001000001010100020202020202020202EA +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:1001300002020201010101020202020202020202A3 +:100140000202020102010202020102020202020292 +:100150000202020202020102020202020202020280 +:100160000202020202020102010101010101010178 +:100170000101010101010100010101010101010170 +:10018000010101010101010101010102020202025A +:100190000202010101010102020202020202020244 +:1001A000020202020202020202020202020202022F +:1001B0000202020202010101010101010201010129 +:1001C000020201010101010101010201020201011A +:1001D0000101010101010100000000000000000018 +:1001E0000100010101010101000002020000010102 +:1001F00001000001010100020202020202020202E9 +:1002000002020202020202020202020202020202CE +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202010202020202020202029F +:100240000202020102010202020202020202020290 +:10025000020202020202010202020202020202027F +:100260000202020202020202010102010101010175 +:10027000010101010101010001010101010101016F +:100280000101010101010101010101020202020259 +:100290000202010101010202020202020202020242 +:1002A000020202020202020202020202020202022E +:1002B0000202020202020201010101010202010125 +:1002C0000202020201010101010102010202010216 +:1002D0000101010101010100000000000000000017 +:1002E0000000010101010002000001010000010104 +:1002F00001000001010100020202020202020202E8 +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202010202020202020202029E +:10034000020202010201020202020202020202028F +:10035000020202020202020202020202020202027D +:100360000202020202020202010102020101010173 +:10037000010101010101010001010101010101016E +:100380000101010101010101010102020202020257 +:100390000202010101010202020202020202020241 +:1003A000020202020202020202020202020202022D +:1003B0000202020202020201010101010202020123 +:1003C0000202020202020101010102010202020212 +:1003D0000202020101010100000000000000000013 +:1003E0000000000101010002000001010000010104 +:1003F00001000001010100020202020202020202E7 +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202010201020202020202020202028E +:10045000020202020202020202020202020202027C +:100460000202020202020202020202020101010170 +:10047000010101010101010001010201010101016C +:100480000101010101010101010202020202020255 +:10049000020202010202020202020202020202023D +:1004A000020202020202020202020202020202022C +:1004B0000202020202020201010101010202020221 +:1004C0000202020202020102010102010202020210 +:1004D0000202020202010100000000000000000010 +:1004E0000000000101010002000001010000010103 +:1004F00001000001010100020202020202020202E6 +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202010101026E +:100570000201010202010100010202010201010166 +:10058000020102020201010102020202020202024F +:10059000020202010202020202020202020202023C +:1005A000020202020202020202020202020202022B +:1005B0000202020202020201010101010202020220 +:1005C000020202020202010201010201020202020F +:1005D000020202020202020000000000000000000D +:1005E0000000000101010002000001010000010102 +:1005F00001000201010100020202020202020202E3 +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202010102026C +:10067000020202020202010002020201020202025E +:10068000020202020202010202020202020202024B +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020101010101020202021F +:1006C000020202020202010201010202020202020D +:1006D000020202020202020000000000000000000C +:1006E0000000000000010001000001010000010104 +:1006F00001000201010100020202020202020202E2 +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:10077000020202020202010002020201020202025D +:10078000020202020202010202020202020202024A +:100790000202020202020202020202020202020239 +:1007A0000202020202020202020202020202020229 +:1007B000020202020202020101010101020202021E +:1007C000020202020202020201010202020202020B +:1007D000020202020202020000000000000000000B +:1007E0000000000000010001000001010000010103 +:1007F00001000201010100020202020202020202E1 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:10087000020202020202010102020201020202025B +:100880000202020202020102020202020202020249 +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B000020202020202020201010202020202021A +:1008C000020202020202020201010202020202020A +:1008D0000202020202020200000000000100010008 +:1008E0000000000000010001000001010000010102 +:1008F00001000201010100020202020202020202E0 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020101020202020202020259 +:100980000202020202020102020202020202020248 +:100990000202020202020202020202020202020237 +:1009A0000202020202020202020202020202020227 +:1009B0000202020202020202010102020202020219 +:1009C0000202020202020202010102020202020209 +:1009D0000202020202020200000000000100010007 +:1009E00000000000000100010000010102000101FF +:1009F00001000101010100020202020202020202E0 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020201020202020202020257 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020202020202020202020226 +:100AB0000202020202020202020102020202020217 +:100AC0000202020202020202010102020202020208 +:100AD0000202020202020200000000000101010005 +:100AE00000000000000000010000010102000101FF +:100AF00001000101010100020202020202020202DF +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020201020202020202020256 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202010102020202020207 +:100BD0000202020202020200000000000101010004 +:100BE00000000000000000010000010102000101FE +:100BF00001020101010100020202020202020202DC +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202010102020202020206 +:100CD0000202020202020200000000000101010003 +:100CE00000000000000000010000010102000101FD +:100CF00001020101010100020202020202020202DB +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD0000202020202020200000000000101010002 +:100DE00000000000000000010000010101000101FD +:100DF00001010201010100020202020202020202DA +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED0000202020202020200000000000101010001 +:100EE00000000000000000010000010101000101FC +:100EF00001010201010100020202020202020202D9 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD0000202020202020200000000000101010000 +:100FE00000000000000000010002010101000101F9 +:100FF00001010201010100000202020202020202DA +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202010002010101000101EA +:1010F00001010201010100000000000002020202E1 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202010002010102020100E7 +:1011F00001020101010100000000000000000202E4 +:1012000002000202020202020202020202020202C0 +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202010002010102020000E7 +:1012F00001020101010100010000000000000000E6 +:1013000002000200020202020202020202020202C1 +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202010002010102010000E7 +:1013F00000020100010100010101010100000000E3 +:1014000000000000000000020202020202020202CA +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202010001000002010000E9 +:1014F00000020100010100010101010101010000E0 +:1015000000010000000000020202020202020202C8 +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202010001000001010000E9 +:1015F00000010100010000010101010101010101DF +:1016000000010001000000020202020202020202C6 +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A000020202020202020202020202020202021A +:1016B000020202020202020202020202020202020A +:1016C00002020202020202020202020202020202FA +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202000001000001020000E8 +:1016F00001010101010100010101010101010101DB +:1017000001010101010101000202020202020202C2 +:1017100002020202020202000202020202020202AB +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A0000202020202020202020202020202020219 +:1017B0000202020202020202020202020202020209 +:1017C00002020202020202020202020202020202F9 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202000202000001020001E3 +:1017F00001010101010100010101010101010101DA +:1018000001010101010101000202020202020202C1 +:1018100002020202020202000202020202020202AA +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A0000202020202020202020202020202020218 +:1018B0000202020202020202020202020202020208 +:1018C00002020202020202020202020202020202F8 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202000202000001020101E1 +:1018F00001010101010100010101010101010101D9 +:1019000001010101010101010202020202020202BF +:1019100002020202020202000000000002020202B1 +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020202020202020202020217 +:1019B0000202020202020202020202020202020207 +:1019C00002020202020202020202020202020202F7 +:1019D00002020202020202020202020202020202E7 +:1019E00002020202020202000202000001010101E1 +:1019F00001010101010100010101010101010101D8 +:101A000001010101010101010000000000000002CC +:101A100002000202020202010000000000020002B5 +:101A20000200020202020202020202020202020298 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000202020202020202020202020202020216 +:101AB0000202020202020202020202020202020206 +:101AC00002020202020202020202020202020202F6 +:101AD00002020202020202020202020202020202E6 +:101AE00002020202020202000101000001010101E2 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010000000000000000CD +:101B100000000000000002010000000000000000C2 +:101B200000000000000000020202020202020202A3 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA0000202020202020202020202020202020215 +:101BB0000202020202020202020202020202020205 +:101BC00002020202020202020202020202020202F5 +:101BD00002020202020202020202020202020202E5 +:101BE00002020202020202000101000101010101E0 +:101BF00001010001010101010101010101010101D6 +:101C000001010101010101010101010101010100C5 +:101C100000010000000000010101010100000000BE +:101C200000000000000000020202020202020202A2 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA0000202020202020202020202020202020214 +:101CB0000202020202020202020202020202020204 +:101CC00002020202020202020202020202020202F4 +:101CD00002020202020202020202020202020202E4 +:101CE00002020202020202000201010101010101DD +:101CF00001010001010101010101010101010101D5 +:101D000001010101010101010101010101010101C3 +:101D100001010101010100010101010101000100B6 +:101D200000010000000000010202020202020202A1 +:101D30000202020202020202020202020202020283 +:101D40000202020202020201020202020202020274 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020202020203 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202010201010100010101DC +:101DF00001010001010101010101010101010101D4 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E2000010101010101010100020102020102029E +:101E30000202020202020202020202020202020282 +:101E40000202020202020202010201010201010277 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202020202 +:101EC00002020202020202020202020202020202F2 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202010101010100010101DC +:101EF00001000001010101010101010101010101D4 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010001010101010201A1 +:101F3000010101020202020000000202020202028A +:101F40000202020202020201020102020102020175 +:101F5000010101010101010000000202020202026E +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202010101010100000101DC +:101FF00001000001010101010101010101010101D3 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010100000000000000000099 +:102040000000000200020001010201010201010280 +:102050000202020202020200000000000000000072 +:10206000000000000000000202020202020202025E +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202010100010100000101DC +:1020F00001000001010101010101010101010101D2 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:102130000101010101010100000000000000000098 +:102140000000000000000001010101010101010186 +:102150000101010101010100000000000000000078 +:102160000000000000000002010101010202020261 +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020202020202020202020F +:1021B00002020202020202020202020202020202FF +:1021C00002020202020202020202020202020202EF +:1021D00002020202020202020202020202020202DF +:1021E00002020202020202010100010100000101DB +:1021F00001000001010101010101010101010101D1 +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:102230000101010101010101010100000000000094 +:102240000000000000000001010101010101010185 +:102250000101010101010101010100000000000074 +:10226000000000000000000202020202020202025C +:102270000202020202020202010101020202020241 +:10228000020202020202020202020202020202022E +:102290000202020202020200000000000000000030 +:1022A000000000000000000202020202020202021C +:1022B00002020202020202020202020202020202FE +:1022C00002020202020202020202020202020202EE +:1022D00002020202020202020202020202020202DE +:1022E00002020202020202010000010100000101DB +:1022F00001000001010101010101010101010101D0 +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101000100010101010101010101017F +:10235000010101010101010101010101010101016D +:102360000101010101010101000000000101010161 +:102370000101010101010102020202020202020244 +:10238000020202020202020202020202020202022D +:10239000020202020202020000000000000000002F +:1023A000000000000000000202020202020202021B +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020202020202ED +:1023D00002020202020202020202020202020202DD +:1023E00002020202020202010000010100000101DA +:1023F00001000101010101010101010101010101CE +:1024000001010101010101010101010101010101BC +:1024100001010101010101010101010101010101AC +:10242000010101010101010101010101010101019C +:10243000010101010101010101010101010101018C +:10244000010101010101010101010101010101017C +:10245000010101010101010101010101010101016C +:10246000010101010101010100000000020202025C +:102470000202020202020201000000010101010148 +:102480000101010101010102020202020202020233 +:102490000202020002020200000000000000000030 +:1024A000000000000000000202020202020202021A +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202000002000200000002E8 +:1024E00002020202020202010000010100000101D9 +:1024F00001000101010101010101010101010101CD +:1025000001010101010101010101010101010101BB +:1025100001010101010101010101010101010101AB +:10252000010101010101010101010101010101019B +:10253000010101010101010101010101010101018B +:10254000010101010101010101010101010101017B +:10255000010101010101010101010101010101016B +:10256000010101010101010101010101010101015B +:102570000101010101010102000000020202020248 +:10258000020202020202020202020202020202022B +:102590000202010001010201010101010101010129 +:1025A000010101010101010101010101010101011B +:1025B0000101010101010102020202020202020202 +:1025C00002020202020202020202020202020202EB +:1025D00002020202020202000002000200000002E7 +:1025E00002020202020202010000010101000101D7 +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101010101BA +:1026100001010101010101010101010101010101AA +:10262000010101010101010101010101010101019A +:10263000010101010101010101010101010101018A +:10264000010101010101010101010101010101017A +:10265000010101010101010101010101010101016A +:10266000010101010101010101010101010101015A +:10267000010101010101010101010101010101014A +:10268000010101010101010101010101010101013A +:102690000101020002020101010101010101010128 +:1026A0000101010101010102020202020202020211 +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202000000000000000002EA +:1026E00002020202020202010000010101000101D6 +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010101A9 +:102720000101010101010101010101010101010199 +:102730000101010101010101010101010101010189 +:102740000101010101010101010101010101010179 +:102750000101010101010101010101010101010169 +:102760000101010101010101010101010101010159 +:102770000101010101010101010101010101010149 +:102780000101010101010101010101010101010139 +:102790000101010101010101010101010101010129 +:1027A0000101010101010101010101010101010119 +:1027B0000101010101010102020202020202020200 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202000000000000000002E9 +:1027E00002020202020202010000010101010101D4 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101020202020202020202EF +:1028D00002020202020202000000000000000002E8 +:1028E00000000202020202010001010101010101D6 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010147 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010101010127 +:1029A0000101010101010101010101010101010117 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101000000000000000000F0 +:1029E00000000002020202010001010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010196 +:102A30000101010101010101010101010101010186 +:102A40000101010101010101010101010101010176 +:102A50000101010101010101010101010101010166 +:102A60000101010101010101010101010101010156 +:102A70000101010101010101010101010101010146 +:102A80000101010101010101010101010101010136 +:102A90000101010101010101010101010101010126 +:102AA0000101010101010101010101010101010116 +:102AB0000101010101010101010101010101010106 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101000000000000000000EF +:102AE00000000002020202010101010101010101D5 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000101010101010101010101010101010185 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010165 +:102B60000101010101010101010101010101010155 +:102B70000101010101010101010101010101010145 +:102B80000101010101010101010101010101010135 +:102B90000101010101010101010101010101010125 +:102BA0000101010101010101010101010101010115 +:102BB0000101010101010101010101010101010105 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101000000000000000000EE +:102BE00000000000000202010101010101010101D8 +:102BF00001010101010101000000000000000000CE +:102C000000000000000000000000000000000000C4 +:102C100000000000000000020202020202020202A2 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202000000000000000000E6 +:102CE00000000000000202010101010101010101D7 +:102CF00001010101010101000000000000000000CD +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000002020202020202020271 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202000000000000000000E5 +:102DE00000000000000202010101010101010101D6 +:102DF00001010101010101000000000000000000CC +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000002020202020202020220 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202000000000000000000E4 +:102EE00000000000000002000000000000000000E0 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE0000000000000000018301200000000002067 +:102FF00047120000000000285B12000000000030B3 +:103000006D120000000000387F1200000000004038 +:103010008F120000000000489E12000000000050C7 +:10302000A812000000000058B2120000000000606A +:10303000BC12000000000068C61200000000007012 +:10304000D012000000000078DA12000000000080BA +:10305000E412000000000017000000000000000063 +:10306000000000000000000000000000000001005F +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000027D +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000001005E +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000000FF +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000027C +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000001005D +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000000FE +:1032D00000000000000000000000000000000000EE +:1032E00000000000000000000000000000000000DE +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000027B +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000001005C +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000000FD +:1033D00000000000000000000000000000000000ED +:1033E00000000000000000000000000000000000DD +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000027A +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000001005B +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000000EC +:1034E00000000000000000000000000000000000DC +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:103540000000000000000000000000000000000279 +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000001005A +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000000000000000000000EB +:1035E00000000000000000000000000000000000DB +:1035F00000000000000000000000000000000000CB +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:103640000000000000000000000000000000000278 +:10365000000000000000000000000000000000006A +:103660000000000000000000000000000000010059 +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000277 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000010058 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000276 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000010057 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000275 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000010056 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000274 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000010055 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000273 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000010054 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000272 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000010053 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000271 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000010052 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000270 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000010051 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F4000000000000000000000000000000000026F +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000010050 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:10404000000000000000000000000000000000026E +:104050000000000000000000000000000000000060 +:10406000000000000000000000000000000001004F +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000026D +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000001004E +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000026C +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000001004D +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000026B +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000001004C +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000026A +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000001004B +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:104540000000000000000000000000000000000269 +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000001004A +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:104640000000000000000000000000000000000268 +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000001445 +:104760000000000000000000000000000000000049 +:104770000000000000000100000000000000000038 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000002000000000000000056 +:104860000000000000000000000000000000000048 +:104870000000000000000100000000000000000037 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000002000000000000000055 +:104960000000000000000000000000000000000047 +:104970000000000000000100000000000000000036 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000002000000000000000054 +:104A60000000000000000000000000000000000046 +:104A70000000000000000100000000000000000035 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000002000000000000000053 +:104B60000000000000000000000000000000000045 +:104B70000000000000000100000000000000000034 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000002000000000000000052 +:104C60000000000000000000000000000000000044 +:104C70000000000000000100000000000000000033 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000002000000000000000051 +:104D60000000000000000000000000000000000043 +:104D70000000000000000100000000000000000032 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000002000000000000000050 +:104E60000000000000000000000000000000000042 +:104E70000000000000000100000000000000000031 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F5000000000000000000200000000000000004F +:104F60000000000000000000000000000000000041 +:104F70000000000000000100000000000000000030 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:10505000000000000000000200000000000000004E +:105060000000000000000000000000000000000040 +:10507000000000000000010000000000000000002F +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000200000000000000004D +:10516000000000000000000000000000000000003F +:10517000000000000000010000000000000000002E +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000200000000000000004C +:10526000000000000000000000000000000000003E +:10527000000000000000010000000000000000002D +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000200000000000000004B +:10536000000000000000000000000000000000003D +:10537000000000000000010000000000000000002C +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000200000000000000004A +:10546000000000000000000000000000000000003C +:10547000000000000000010000000000000000002B +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:105550000000000000000002000000000000000049 +:10556000000000000000000000000000000000003B +:10557000000000000000010000000000000000002A +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:105650000000000000000002000000000000000048 +:10566000000000000000000000000000000000003A +:105670000000000000000100000000000000000029 +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000000CA +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000002000000000000000047 +:105760000000000000000000000000000000000039 +:105770000000000000000100000000000000000028 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000000000000000000000C9 +:1057E00000000000000000000000000000000000B9 +:1057F00000000000000000000000000000000000A9 +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000002000000000000000046 +:105860000000000000000000000000000000000038 +:105870000000000000000100000000000000000027 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000000000000000000000C8 +:1058E00000000000000000000000000000000000B8 +:1058F00000000000000000000000000000000000A8 +:105900000000000000000000000000000000000097 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000002000000000000000045 +:105960000000000000000000000000000000000037 +:105970000000000000000100000000000000000026 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000000000000000000000C7 +:1059E00000000000000000000000000000000000B7 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000002000000000000000044 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000012000000000000000023 +:105B70000000000000000000000000000000010024 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000242 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000010023 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000241 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000010022 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000240 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000010021 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F5000000000000000000000000000000000023F +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000010020 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:10605000000000000000000000000000000000023E +:106060000000000000000000000000000000000030 +:10607000000000000000000000000000000001001F +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000000000000000000008F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000023D +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000001001E +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000023C +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000001001D +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000023B +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000001001C +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000023A +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000001001B +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:106550000000000000000000000000000000000239 +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000001001A +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:10660000000000000000000000000000000000008A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:106650000000000000000000000000000000000238 +:10666000000000000000000000000000000000002A +:106670000000000000000000000000000000010019 +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000000000000000000AA +:1066F000000000000000000000000000000000009A +:106700000000000000000000000000000000000089 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000237 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000010018 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000099 +:106800000000000000000000000000000000000088 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000236 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000010017 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000000B8 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000098 +:106900000000000000000000000000000000000087 +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000235 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000010016 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000000000000000000B7 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000097 +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000234 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000010015 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000000B6 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000096 +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000233 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000010014 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000232 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000001211 +:106D70000000000000000000000000000000000013 +:106D80000000000000000100000000000000000002 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000002000000000000000020 +:106E70000000000000000000000000000000000012 +:106E80000000000000000100000000000000000001 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F6000000000000000000200000000000000001F +:106F70000000000000000000000000000000000011 +:106F80000000000000000100000000000000000000 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:10706000000000000000000200000000000000001E +:107070000000000000000000000000000000000010 +:1070800000000000000001000000000000000000FF +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000200000000000000001D +:10717000000000000000000000000000000000000F +:1071800000000000000001000000000000000000FE +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000200000000000000001C +:10727000000000000000000000000000000000000E +:1072800000000000000001000000000000000000FD +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000200000000000000001B +:10737000000000000000000000000000000000000D +:1073800000000000000001000000000000000000FC +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000200000000000000001A +:10747000000000000000000000000000000000000C +:1074800000000000000001000000000000000000FB +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:107560000000000000000002000000000000000019 +:10757000000000000000000000000000000000000B +:1075800000000000000001000000000000000000FA +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:107660000000000000000002000000000000000018 +:10767000000000000000000000000000000000000A +:1076800000000000000001000000000000000000F9 +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000000BA +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000002000000000000000017 +:107770000000000000000000000000000000000009 +:1077800000000000000001000000000000000000F8 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000000B9 +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000002000000000000000016 +:107870000000000000000000000000000000000008 +:1078800000000000000001000000000000000000F7 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000000B8 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000002000000000000000015 +:107970000000000000000000000000000000000007 +:1079800000000000000001000000000000000000F6 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000002000000000000000014 +:107A70000000000000000000000000000000000006 +:107A800000000000000001000000000000000000F5 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000002000000000000000013 +:107B70000000000000000000000000000000000005 +:107B800000000000000001000000000000000000F4 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000002000000000000000012 +:107C70000000000000000000000000000000000004 +:107C800000000000000001000000000000000000F3 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000002000000000000000011 +:107D70000000000000000000000000000000000003 +:107D800000000000000001000000000000000000F2 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000002000000000000000010 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F700000000000000000100000000000000000F1 +:107F800000000000000000000000000000000100F0 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:10806000000000000000000000000000000000020E +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000100EF +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000020D +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000100EE +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000020C +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000100ED +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000020B +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000100EC +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000020A +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000100EB +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:108560000000000000000000000000000000000209 +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000100EA +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:108660000000000000000000000000000000000208 +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000100E9 +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000207 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000100E8 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000206 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000100E7 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000205 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000100E6 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000204 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000100E5 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000203 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000100E4 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000202 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000100E3 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000201 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000100E2 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000200 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F70000000000000000000000000000000000FE2 +:108F800000000000000000000000000000000000E1 +:108F900000000000000001000000000000000000D0 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000020000000000000000EE +:1090800000000000000000000000000000000000E0 +:1090900000000000000001000000000000000000CF +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000020000000000000000ED +:1091800000000000000000000000000000000000DF +:1091900000000000000001000000000000000000CE +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000020000000000000000EC +:1092800000000000000000000000000000000000DE +:1092900000000000000001000000000000000000CD +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000020000000000000000EB +:1093800000000000000000000000000000000000DD +:1093900000000000000001000000000000000000CC +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000020000000000000000EA +:1094800000000000000000000000000000000000DC +:1094900000000000000001000000000000000000CB +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000020000000000000000E9 +:1095800000000000000000000000000000000000DB +:1095900000000000000001000000000000000000CA +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D000000000000000000000000000000000008B +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:10960000000000000000000000000000000000005A +:10961000000000000000000000000000000000004A +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000020000000000000000E8 +:1096800000000000000000000000000000000000DA +:1096900000000000000001000000000000000000C9 +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C000000000000000000000000000000000009A +:1096D000000000000000000000000000000000008A +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000049 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000020000000000000000E7 +:1097800000000000000000000000000000000000D9 +:1097900000000000000001000000000000000000C8 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000099 +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000020000000000000000E6 +:1098800000000000000000000000000000000000D8 +:1098900000000000000001000000000000000000C7 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000000000000000000000A8 +:1098C0000000000000000000000000000000000098 +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000000000000000078 +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000000000057 +:109910000000000000000000000000000000000047 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700000000000000000020000000000000000E5 +:1099800000000000000000000000000000000000D7 +:1099900000000000000001000000000000000000C6 +:1099A00000000000000000000000000000000000B7 +:1099B00000000000000000000000000000000000A7 +:1099C0000000000000000000000000000000000097 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0000000000000000000000000000000000067 +:109A00000000000000000000000000000000000056 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000000000000000000000000000000000F6 +:109A700000000000000000020000000000000000E4 +:109A800000000000000000000000000000000000D6 +:109A900000000000000001000000000000000000C5 +:109AA00000000000000000000000000000000000B6 +:109AB00000000000000000000000000000000000A6 +:109AC0000000000000000000000000000000000096 +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000076 +:109AF0000000000000000000000000000000000066 +:109B00000000000000000000000000000000000055 +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000020000000000000000E3 +:109B800000000000000000000000000000000000D5 +:109B900000000000000001000000000000000000C4 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000020000000000000000E2 +:109C800000000000000000000000000000000000D4 +:109C900000000000000001000000000000000000C3 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000020000000000000000E1 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E8000000000000000000A0000000000000000C8 +:109E900000000000000000000000000000000100C1 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000002DF +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000100C0 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000002DE +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000100BF +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000002DD +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000100BE +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000002DC +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000100BD +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000002DB +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000100BC +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000002DA +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000100BB +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000002D9 +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000100BA +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000002D8 +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000100B9 +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000002D7 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A880000000000000000000000000000000000ABE +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000001000000000000000000A7 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000058 +:10A900000000000000000000000000000000000047 +:10A910000000000000000000000000000000000037 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000020000000000000000C5 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000001000000000000000000A6 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000000000077 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000046 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000020000000000000000C4 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000001000000000000000000A5 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000020000000000000000C3 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000001000000000000000000A4 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000020000000000000000C2 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000001000000000000000000A3 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000020000000000000000C1 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000001000000000000000000A2 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000020000000000000000C0 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000001000000000000000000A1 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000020000000000000000BF +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000001000000000000000000A0 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000020000000000000000BE +:10B0900000000000000000000000000000000000B0 +:10B0A000000000000000010000000000000000009F +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000020000000000000000BD +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B29000000000000000000A0000000000000000A4 +:10B2A000000000000000000000000000000001009D +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000002BB +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000001009C +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000002BA +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000001009B +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000000000000000000000000000000000002B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000002B9 +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000001009A +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000002B8 +:10B6900000000000000000000000000000000000AA +:10B6A0000000000000000000000000000000010099 +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000002B7 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000010098 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000002B6 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000010097 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000002B5 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000010096 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000002B4 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000010095 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000002B3 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC90000000000000000000000000000000000A9A +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000100000000000000000083 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000020000000000000000A1 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000100000000000000000082 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000020000000000000000A0 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000100000000000000000081 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF9000000000000000000200000000000000009F +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000100000000000000000080 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C09000000000000000000200000000000000009E +:10C0A0000000000000000000000000000000000090 +:10C0B000000000000000010000000000000000007F +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000200000000000000009D +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000010000000000000000007E +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000200000000000000009C +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000010000000000000000007D +:10C2C000000000000000000000000000000000006E +:10C2D000000000000000000000000000000000005E +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000000001D +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000200000000000000009B +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000010000000000000000007C +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000200000000000000009A +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000010000000000000000007B +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C590000000000000000002000000000000000099 +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000A000000000000000080 +:10C6B0000000000000000000000000000000010079 +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000297 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000010078 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000296 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000010077 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000295 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000010076 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000294 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000010075 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000293 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000010074 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000292 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000010073 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000054 +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD10000000000000000000000000000000000013 +:10CD20000000000000000000000000000000000003 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000291 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000010072 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000290 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000010071 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF9000000000000000000000000000000000028F +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000A76 +:10D0B0000000000000000000000000000000000070 +:10D0C000000000000000010000000000000000005F +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000200000000000000007D +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000010000000000000000005E +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000200000000000000007C +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000010000000000000000005D +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000200000000000000007B +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000010000000000000000005C +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000200000000000000007A +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000010000000000000000005B +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A0000000000000000002000000000000000079 +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000010000000000000000005A +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A0000000000000000002000000000000000078 +:10D6B000000000000000000000000000000000006A +:10D6C0000000000000000100000000000000000059 +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000002000000000000000077 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000100000000000000000058 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D810000000000000000000000000000000000008 +:10D8200000000000000000000000000000000000F8 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000002000000000000000076 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000100000000000000000057 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000000000000000000F7 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000002000000000000000075 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB000000000000000000A00000000000000005C +:10DAC0000000000000000000000000000000010055 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000273 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000010054 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000272 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000010053 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000271 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000010052 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000270 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000010051 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA000000000000000000000000000000000026F +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000000000000000000000010050 +:10DFD0000000000000000000000000000000000041 +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A000000000000000000000000000000000026E +:10E0B0000000000000000000000000000000000060 +:10E0C000000000000000000000000000000001004F +:10E0D0000000000000000000000000000000000040 +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000026D +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000001004E +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000026C +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000001004D +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000026B +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B0000000000000000000000000000000000A52 +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000010000000000000000003B +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B0000000000000000002000000000000000059 +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000010000000000000000003A +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B0000000000000000002000000000000000058 +:10E6C000000000000000000000000000000000004A +:10E6D0000000000000000100000000000000000039 +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000002000000000000000057 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000100000000000000000038 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000002000000000000000056 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000100000000000000000037 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000002000000000000000055 +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000100000000000000000036 +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000002000000000000000054 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000100000000000000000035 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000002000000000000000053 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000100000000000000000034 +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000002000000000000000052 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000100000000000000000033 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000002000000000000000051 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:07EEC000000000000000004B +:00000001FF diff --git a/firmware/imx/epdc_E97_V110.fw.ihex b/firmware/imx/epdc_E97_V110.fw.ihex new file mode 100644 index 000000000000..3078acdcbaaf --- /dev/null +++ b/firmware/imx/epdc_E97_V110.fw.ihex @@ -0,0 +1,54512 @@ +:1000000095533B1702B60000B701000004042C0012 +:100010000131020E6101010000000000410000D228 +:100020004800000100030E00FFFC00000000005526 +:10003000000306090C0F1215181B1E21262B303247 +:10004000200000000000000010DE0600000000009C +:1000500000E9070000000000F0330B000000000082 +:100060009800000000000000A089000000000000CF +:10007000A802010000000000B06F010000000000B5 +:10008000B8DC010000000000C077020000000000A2 +:10009000C806030000000000D07D0300000000003F +:1000A000D8FA030000000000E06B0400000000002C +:1000B000E8DE040000000000F04B05000000000036 +:1000C000F8B2050000000000001C0600000000005F +:1000D000087F06000000000089000000000000000A +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010198 +:100850000101010101010101010101010101010188 +:100860000101010101010101010101010101010178 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010118 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000001010101010101010101010101010101D2 +:100E100001010101010101010101010101010101C2 +:100E200001010101010101010101010101010101B2 +:100E300001010101010101010101010101010101A2 +:100E40000101010101010101010101010101010192 +:100E50000101010101010101010101010101010182 +:100E60000101010101010101010101010101010172 +:100E70000101010101010101010101010101010162 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101010101010101010101E2 +:100F000001010101010101010101010101010101D1 +:100F100001010101010101010101010101010101C1 +:100F200001010101010101010101010101010101B1 +:100F300001010101010101010101010101010101A1 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000101010101010101010101010101010171 +:100F70000101010101010101010101010101010161 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101010101010101010101E1 +:1010000001010101010101010101010101010101D0 +:1010100001010101010101010101010101010101C0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000101010101010101010101010101010170 +:101070000101010101010101010101010101010160 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010101010101BF +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:10116000010101010101010101010101010101016F +:10117000010101010101010101010101010101015F +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010101010101BE +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101016E +:10127000010101010101010101010101010101015E +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101010101010101010101BD +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101016D +:10137000010101010101010101010101010101015D +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101016C +:10147000010101010101010101010101010101015C +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101018B +:10155000010101010101010101010101010101017B +:10156000010101010101010101010101010101016B +:10157000010101010101010101010101010101015B +:10158000010101010101010101010101010101014B +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010101010101010101019A +:10164000010101010101010101010101010101018A +:10165000010101010101010101010101010101017A +:10166000010101010101010101010101010101016A +:10167000010101010101010101010101010101015A +:10168000010101010101010101010101010101014A +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010101010101010101010157 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00000000000000000000000000000000000F3 +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E300000000000000000000000000000000000A2 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000000000000000000022 +:101EC0000000000000000000000000000000000012 +:101ED0000000000000000000000000000000000002 +:101EE00000000000000000000000000000000000F2 +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000000000000000000B1 +:101F300000000000000000000000000000000000A1 +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F80000000000000000000000000000000000051 +:101F90000000000000000000000000000000000041 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000000000000000000021 +:101FC0000000000000000000000000000000000011 +:101FD0000000000000000000000000000000000001 +:101FE00000000000000000000000000000000000F1 +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000000000000000000B0 +:1020300000000000000000000000000000000000A0 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000000000000000010 +:1020D0000000000000000000000000000000000000 +:1020E00000000000000000000000000000000000F0 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00002020202020202020202020202020202CD +:1023F00002020202020202020202020202020202BD +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202020202020202020202DC +:1024E00002020202020202020202020202020202CC +:1024F00002020202020202020202020202020202BC +:1025000002020202020202020202020202020202AB +:10251000020202020202020202020202020202029B +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C00002020202020202020202020202020202EB +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020202CB +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202020202020202020202DA +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020202D3 +:102DE00002020202020202020202020202020202C3 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020202D2 +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101016D +:10533000010101010101010101010101010101015D +:10534000010101010101010101010101010101014D +:10535000010101010101010101010101010101013D +:10536000010101010101010101010101010101012D +:10537000010101010101010101010101010101011D +:10538000010101010101010101010101010101010D +:1053900001010101010101010101010101010101FD +:1053A00001010101010101010101010101010101ED +:1053B00001010101010101010101010101010101DD +:1053C00001010101010101010101010101010101CD +:1053D00001010101010101010101010101010101BD +:1053E00001010101010101010101010101010101AD +:1053F000010101010101010101010101010101019D +:10540000010101010101010101010101010101018C +:10541000010101010101010101010101010101017C +:10542000010101010101010101010101010101016C +:10543000010101010101010101010101010101015C +:10544000010101010101010101010101010101014C +:10545000010101010101010101010101010101013C +:10546000010101010101010101010101010101012C +:10547000010101010101010101010101010101011C +:10548000010101010101010101010101010101010C +:1054900001010101010101010101010101010101FC +:1054A00001010101010101010101010101010101EC +:1054B00001010101010101010101010101010101DC +:1054C00001010101010101010101010101010101CC +:1054D00001010101010101010101010101010101BC +:1054E00001010101010101010101010101010101AC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:10553000010101010101010101010101010101015B +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000101010101010101010101010101010169 +:105730000101010101010101010101010101010159 +:105740000101010101010101010101010101010149 +:105750000101010101010101010101010101010139 +:105760000101010101010101010101010101010129 +:105770000101010101010101010101010101010119 +:105780000101010101010101010101010101010109 +:1057900001010101010101010101010101010101F9 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101010101010101010101C9 +:1057D00001010101010101010101010101010101B9 +:1057E00001010101010101010101010101010101A9 +:1057F0000101010101010101010101010101010199 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010187 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000101010101010101010101010101010186 +:105A10000101010101010101010101010101010176 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010101010101010101010116 +:105A80000101010101010101010101010101010106 +:105A900001010101010101010101010101010101F6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00001010101010101010101010101010101C6 +:105AD00001010101010101010101010101010101B6 +:105AE00001010101010101010101010101010101A6 +:105AF0000101010101010101010101010101010196 +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010175 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101010101010101010145 +:105B50000101010101010101010101010101010135 +:105B60000101010101010101010101010101010125 +:105B70000101010101010101010101010101010115 +:105B80000101010101010101010101010101010105 +:105B900001010101010101010101010101010101F5 +:105BA00001010101010101010101010101010101E5 +:105BB00001010101010101010101010101010101D5 +:105BC00001010101010101010101010101010101C5 +:105BD00001010101010101010101010101010101B5 +:105BE00001010101010101010101010101010101A5 +:105BF0000101010101010101010101010101010195 +:105C00000101010101010101010101010101010184 +:105C10000101010101010101010101010101010174 +:105C20000101010101010101010101010101010164 +:105C30000101010101010101010101010101010154 +:105C40000101010101010101010101010101010144 +:105C50000101010101010101010101010101010134 +:105C60000101010101010101010101010101010124 +:105C70000101010101010101010101010101010114 +:105C80000101010101010101010101010101010104 +:105C900001010101010101010101010101010101F4 +:105CA00001010101010101010101010101010101E4 +:105CB00001010101010101010101010101010101D4 +:105CC00001010101010101010101010101010101C4 +:105CD00001010101010101010101010101010101B4 +:105CE00001010101010101010101010101010101A4 +:105CF0000101010101010101010101010101010194 +:105D00000101010101010101010101010101010183 +:105D10000101010101010101010101010101010173 +:105D20000101010101010101010101010101010163 +:105D30000101010101010101010101010101010153 +:105D40000101010101010101010101010101010143 +:105D50000101010101010101010101010101010133 +:105D60000101010101010101010101010101010123 +:105D70000101010101010101010101010101010113 +:105D80000101010101010101010101010101010103 +:105D900001010101010101010101010101010101F3 +:105DA00001010101010101010101010101010101E3 +:105DB00001010101010101010101010101010101D3 +:105DC00001010101010101010101010101010101C3 +:105DD00001010101010101010101010101010101B3 +:105DE00001010101010101010101010101010101A3 +:105DF0000101010101010101010101010101010193 +:105E00000101010101010101010101010101010182 +:105E10000101010101010101010101010101010172 +:105E20000101010101010101010101010101010162 +:105E30000101010101010101010101010101010152 +:105E40000101010101010101010101010101010142 +:105E50000101010101010101010101010101010132 +:105E60000101010101010101010101010101010122 +:105E70000101010101010101010101010101010112 +:105E80000101010101010101010101010101010102 +:105E900001010101010101010101010101010101F2 +:105EA00001010101010101010101010101010101E2 +:105EB00001010101010101010101010101010101D2 +:105EC00001010101010101010101010101010101C2 +:105ED00001010101010101010101010101010101B2 +:105EE00001010101010101010101010101010101A2 +:105EF0000101010101010101010101010101010192 +:105F00000101010101010101010101010101010181 +:105F10000101010101010101010101010101010171 +:105F20000101010101010101010101010101010161 +:105F30000101010101010101010101010101010151 +:105F40000101010101010101010101010101010141 +:105F50000101010101010101010101010101010131 +:105F60000101010101010101010101010101010121 +:105F70000101010101010101010101010101010111 +:105F80000101010101010101010101010101010101 +:105F900001010101010101010101010101010101F1 +:105FA00001010101010101010101010101010101E1 +:105FB00001010101010101010101010101010101D1 +:105FC00001010101010101010101010101010101C1 +:105FD00001010101010101010101010101010101B1 +:105FE00001010101010101010101010101010101A1 +:105FF0000101010101010101010101010101010191 +:106000000101010101010101010101010101010180 +:106010000101010101010101010101010101010170 +:106020000101010101010101010101010101010160 +:106030000101010101010101010101010101010150 +:106040000101010101010101010101010101010140 +:106050000101010101010101010101010101010130 +:106060000101010101010101010101010101010120 +:106070000101010101010101010101010101010110 +:106080000101010101010101010101010101010100 +:1060900001010101010101010101010101010101F0 +:1060A00001010101010101010101010101010101E0 +:1060B00001010101010101010101010101010101D0 +:1060C00001010101010101010101010101010101C0 +:1060D00001010101010101010101010101010101B0 +:1060E00001010101010101010101010101010101A0 +:1060F0000101010101010101010101010101010190 +:10610000010101010101010101010101010101017F +:10611000010101010101010101010101010101016F +:10612000010101010101010101010101010101015F +:10613000010101010101010101010101010101014F +:10614000010101010101010101010101010101013F +:10615000010101010101010101010101010101012F +:10616000010101010101010101010101010101011F +:10617000010101010101010101010101010101010F +:1061800001010101010101010101010101010101FF +:1061900001010101010101010101010101010101EF +:1061A00001010101010101010101010101010101DF +:1061B00001010101010101010101010101010101CF +:1061C00001010101010101010101010101010101BF +:1061D00001010101010101010101010101010101AF +:1061E000010101010101010101010101010101019F +:1061F000010101010101010101010101010101018F +:10620000010101010101010101010101010101017E +:10621000010101010101010101010101010101016E +:10622000010101010101010101010101010101015E +:10623000010101010101010101010101010101014E +:10624000010101010101010101010101010101013E +:10625000010101010101010101010101010101012E +:10626000010101010101010101010101010101011E +:10627000010101010101010101010101010101010E +:1062800001010101010101010101010101010101FE +:1062900001010101010101010101010101010101EE +:1062A00001010101010101010101010101010101DE +:1062B00001010101010101010101010101010101CE +:1062C00001010101010101010101010101010101BE +:1062D00001010101010101010101010101010101AE +:1062E000010101010101010101010101010101019E +:1062F000010101010101010101010101010101018E +:10630000010101010101010101010101010101017D +:10631000010101010101010101010101010101016D +:10632000010101010101010101010101010101015D +:10633000010101010101010101010101010101014D +:10634000010101010101010101010101010101013D +:10635000010101010101010101010101010101012D +:10636000010101010101010101010101010101011D +:10637000010101010101010101010101010101010D +:1063800001010101010101010101010101010101FD +:1063900001010101010101010101010101010101ED +:1063A00001010101010101010101010101010101DD +:1063B00001010101010101010101010101010101CD +:1063C00001010101010101010101010101010101BD +:1063D00001010101010101010101010101010101AD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000000000000000000000000000000000003B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:10660000000000000000000000000000000000008A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000000000000000000AA +:1066F000000000000000000000000000000000009A +:106700000000000000000000000000000000000089 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010178 +:106810000101010101010101010101010101010168 +:106820000101010101010101010101010101010158 +:106830000101010101010101010101010101010148 +:106840000101010101010101010101010101010138 +:106850000101010101010101010101010101010128 +:106860000101010101010101010101010101010118 +:106870000101010101010101010101010101010108 +:1068800001010101010101010101010101010101F8 +:1068900001010101010101010101010101010101E8 +:1068A00001010101010101010101010101010101D8 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010147 +:106940000101010101010101010101010101010137 +:106950000101010101010101010101010101010127 +:106960000101010101010101010101010101010117 +:106970000101010101010101010101010101010107 +:1069800001010101010101010101010101010101F7 +:1069900001010101010101010101010101010101E7 +:1069A00001010101010101010101010101010101D7 +:1069B00001010101010101010101010101010101C7 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101010101010101010101A7 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202020286 +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020202020285 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202020202020202020214 +:107C50000202020202020202020202020202020204 +:107C600002020202020202020202020202020202F4 +:107C700002020202020202020202020202020202E4 +:107C800002020202020202020202020202020202D4 +:107C900002020202020202020202020202020202C4 +:107CA00002020202020202020202020202020202B4 +:107CB00002020202020202020202020202020202A4 +:107CC0000202020202020202020202020202020294 +:107CD0000202020202020202020202020202020284 +:107CE0000202020202020202020202020202020274 +:107CF0000202020202020202020202020202020264 +:107D00000202020202020202020202020202020253 +:107D10000202020202020202020202020202020243 +:107D20000202020202020202020202020202020233 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202020202020202020283 +:107DE0000202020202020202020202020202020273 +:107DF0000202020202020202020202020202020263 +:107E00000202020202020202020202020202020252 +:107E10000202020202020202020202020202020242 +:107E20000202020202020202020202020202020232 +:107E30000202020202020202020202020202020222 +:107E40000202020202020202020202020202020212 +:107E50000202020202020202020202020202020202 +:107E600002020202020202020202020202020202F2 +:107E700002020202020202020202020202020202E2 +:107E800002020202020202020202020202020202D2 +:107E900002020202020202020202020202020202C2 +:107EA00002020202020202020202020202020202B2 +:107EB00002020202020202020202020202020202A2 +:107EC0000202020202020202020202020202020292 +:107ED0000202020202020202020202020202020282 +:107EE0000202020202020202020202020202020272 +:107EF0000202020202020202020202020202020262 +:107F00000202020202020202020202020202020251 +:107F10000202020202020202020202020202020241 +:107F20000202020202020202020202020202020231 +:107F30000202020202020202020202020202020221 +:107F40000202020202020202020202020202020211 +:107F50000202020202020202020202020202020201 +:107F600002020202020202020202020202020202F1 +:107F700002020202020202020202020202020202E1 +:107F800002020202020202020202020202020202D1 +:107F900002020202020202020202020202020202C1 +:107FA00002020202020202020202020202020202B1 +:107FB00002020202020202020202020202020202A1 +:107FC0000202020202020202020202020202020291 +:107FD0000202020202020202020202020202020281 +:107FE0000202020202020202020202020202020271 +:107FF0000202020202020202020202020202020261 +:108000000202020202020202020202020202020250 +:108010000202020202020202020202020202020240 +:108020000202020202020202020202020202020230 +:108030000202020202020202020202020202020220 +:108040000202020202020202020202020202020210 +:108050000202020202020202020202020202020200 +:1080600002020202020202020202020202020202F0 +:1080700002020202020202020202020202020202E0 +:1080800002020202020202020202020202020202D0 +:1080900002020202020202020202020202020202C0 +:1080A00002020202020202020202020202020202B0 +:1080B00002020202020202020202020202020202A0 +:1080C0000202020202020202020202020202020290 +:1080D0000202020202020202020202020202020280 +:1080E0000202020202020202020202020202020270 +:1080F0000202020202020202020202020202020260 +:10810000020202020202020202020202020202024F +:10811000020202020202020202020202020202023F +:10812000020202020202020202020202020202022F +:10813000020202020202020202020202020202021F +:10814000020202020202020202020202020202020F +:1081500002020202020202020202020202020202FF +:1081600002020202020202020202020202020202EF +:1081700002020202020202020202020202020202DF +:1081800002020202020202020202020202020202CF +:1081900002020202020202020202020202020202BF +:1081A00002020202020202020202020202020202AF +:1081B000020202020202020202020202020202029F +:1081C000020202020202020202020202020202028F +:1081D000020202020202020202020202020202027F +:1081E000020202020202020202020202020202026F +:1081F000020202020202020202020202020202025F +:10820000020202020202020202020202020202024E +:10821000020202020202020202020202020202023E +:10822000020202020202020202020202020202022E +:10823000020202020202020202020202020202021E +:10824000020202020202020202020202020202020E +:1082500002020202020202020202020202020202FE +:1082600002020202020202020202020202020202EE +:1082700002020202020202020202020202020202DE +:1082800002020202020202020202020202020202CE +:1082900002020202020202020202020202020202BE +:1082A00002020202020202020202020202020202AE +:1082B000020202020202020202020202020202029E +:1082C000020202020202020202020202020202028E +:1082D000020202020202020202020202020202027E +:1082E000020202020202020202020202020202026E +:1082F000020202020202020202020202020202025E +:10830000020202020202020202020202020202024D +:10831000020202020202020202020202020202023D +:10832000020202020202020202020202020202022D +:10833000020202020202020202020202020202021D +:10834000020202020202020202020202020202020D +:1083500002020202020202020202020202020202FD +:1083600002020202020202020202020202020202ED +:1083700002020202020202020202020202020202DD +:1083800002020202020202020202020202020202CD +:1083900002020202020202020202020202020202BD +:1083A00002020202020202020202020202020202AD +:1083B000020202020202020202020202020202029D +:1083C000020202020202020202020202020202028D +:1083D000020202020202020202020202020202027D +:1083E000020202020202020202020202020202026D +:1083F000020202020202020202020202020202025D +:10840000020202020202020202020202020202024C +:10841000020202020202020202020202020202023C +:10842000020202020202020202020202020202022C +:10843000020202020202020202020202020202021C +:10844000020202020202020202020202020202020C +:1084500002020202020202020202020202020202FC +:1084600002020202020202020202020202020202EC +:1084700002020202020202020202020202020202DC +:1084800002020202020202020202020202020202CC +:1084900002020202020202020202020202020202BC +:1084A00002020202020202020202020202020202AC +:1084B000020202020202020202020202020202029C +:1084C000020202020202020202020202020202028C +:1084D000020202020202020202020202020202027C +:1084E000020202020202020202020202020202026C +:1084F000020202020202020202020202020202025C +:10850000020202020202020202020202020202024B +:10851000020202020202020202020202020202023B +:10852000020202020202020202020202020202022B +:10853000020202020202020202020202020202021B +:10854000020202020202020202020202020202020B +:1085500002020202020202020202020202020202FB +:1085600002020202020202020202020202020202EB +:1085700002020202020202020202020202020202DB +:1085800002020202020202020202020202020202CB +:1085900002020202020202020202020202020202BB +:1085A00002020202020202020202020202020202AB +:1085B000020202020202020202020202020202029B +:1085C000020202020202020202020202020202028B +:1085D000020202020202020202020202020202027B +:1085E000020202020202020202020202020202026B +:1085F000020202020202020202020202020202025B +:10860000020202020202020202020202020202024A +:10861000020202020202020202020202020202023A +:10862000020202020202020202020202020202022A +:10863000020202020202020202020202020202021A +:10864000020202020202020202020202020202020A +:1086500002020202020202020202020202020202FA +:1086600002020202020202020202020202020202EA +:1086700002020202020202020202020202020202DA +:1086800002020202020202020202020202020202CA +:1086900002020202020202020202020202020202BA +:1086A00002020202020202020202020202020202AA +:1086B000020202020202020202020202020202029A +:1086C000020202020202020202020202020202028A +:1086D000020202020202020202020202020202027A +:1086E000020202020202020202020202020202026A +:1086F000020202020202020202020202020202025A +:108700000202020202020202020202020202020249 +:108710000202020202020202020202020202020239 +:108720000202020202020202020202020202020229 +:108730000202020202020202020202020202020219 +:108740000202020202020202020202020202020209 +:1087500002020202020202020202020202020202F9 +:1087600002020202020202020202020202020202E9 +:1087700002020202020202020202020202020202D9 +:1087800002020202020202020202020202020202C9 +:1087900002020202020202020202020202020202B9 +:1087A00002020202020202020202020202020202A9 +:1087B0000202020202020202020202020202020299 +:1087C0000202020202020202020202020202020289 +:1087D0000202020202020202020202020202020279 +:1087E0000202020202020202020202020202020269 +:1087F0000202020202020202020202020202020259 +:108800000202020202020202020202020202020248 +:108810000202020202020202020202020202020238 +:108820000202020202020202020202020202020228 +:108830000202020202020202020202020202020218 +:108840000202020202020202020202020202020208 +:1088500002020202020202020202020202020202F8 +:1088600002020202020202020202020202020202E8 +:1088700002020202020202020202020202020202D8 +:1088800002020202020202020202020202020202C8 +:1088900002020202020202020202020202020202B8 +:1088A00002020202020202020202020202020202A8 +:1088B0000202020202020202020202020202020298 +:1088C0000202020202020202020202020202020288 +:1088D0000202020202020202020202020202020278 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0007900000000000000010101010101010106 +:1089F0000101010101010101010101010101010167 +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF0000101010101010101010101010101010165 +:108C00000101010101010101010101010101010154 +:108C10000101010101010101010101010101010144 +:108C20000101010101010101010101010101010134 +:108C30000101010101010101010101010101010124 +:108C40000101010101010101010101010101010114 +:108C50000101010101010101010101010101010104 +:108C600001010101010101010101010101010101F4 +:108C700001010101010101010101010101010101E4 +:108C800001010101010101010101010101010101D4 +:108C900001010101010101010101010101010101C4 +:108CA00001010101010101010101010101010101B4 +:108CB00001010101010101010101010101010101A4 +:108CC0000101010101010101010101010101010194 +:108CD0000101010101010101010101010101010184 +:108CE0000101010101010101010101010101010174 +:108CF0000101010101010101010101010101010164 +:108D00000101010101010101010101010101010153 +:108D10000101010101010101010101010101010143 +:108D20000101010101010101010101010101010133 +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101010101010101010131 +:108F30000101010101010101010101010101010121 +:108F40000101010101010101010101010101010111 +:108F50000101010101010101010101010101010101 +:108F600001010101010101010101010101010101F1 +:108F700001010101010101010101010101010101E1 +:108F800001010101010101010101010101010101D1 +:108F900001010101010101010101010101010101C1 +:108FA00001010101010101010101010101010101B1 +:108FB00001010101010101010101010101010101A1 +:108FC0000101010101010101010101010101010191 +:108FD0000101010101010101010101010101010181 +:108FE0000101010101010101010101010101010171 +:108FF0000101010101010101010101010101010161 +:109000000101010101010101010101010101010150 +:109010000101010101010101010101010101010140 +:109020000101010101010101010101010101010130 +:109030000101010101010101010101010101010120 +:109040000101010101010101010101010101010110 +:109050000101010101010101010101010101010100 +:1090600001010101010101010101010101010101F0 +:1090700001010101010101010101010101010101E0 +:1090800001010101010101010101010101010101D0 +:1090900001010101010101010101010101010101C0 +:1090A00001010101010101010101010101010101B0 +:1090B00001010101010101010101010101010101A0 +:1090C0000101010101010101010101010101010190 +:1090D0000101010101010101010101010101010180 +:1090E0000101010101010101010101010101010170 +:1090F0000101010101010101010101010101010160 +:10910000010101010101010101010101010101014F +:10911000010101010101010101010101010101013F +:10912000010101010101010101010101010101012F +:10913000010101010101010101010101010101011F +:10914000010101010101010101010101010101010F +:1091500001010101010101010101010101010101FF +:1091600001010101010101010101010101010101EF +:1091700001010101010101010101010101010101DF +:1091800001010101010101010101010101010101CF +:1091900001010101010101010101010101010101BF +:1091A00001010101010101010101010101010101AF +:1091B000010101010101010101010101010101019F +:1091C000010101010101010101010101010101018F +:1091D000010101010101010101010101010101017F +:1091E000010101010101010101010101010101016F +:1091F000010101010101010101010101010101015F +:10920000010101010101010101010101010101014E +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010101010101010101E2 +:109E700001010101010101010101010101010101D2 +:109E800001010101010101010101010101010101C2 +:109E900001010101010101010101010101010101B2 +:109EA00001010101010101010101010101010101A2 +:109EB0000101010101010101010101010101010192 +:109EC0000101010101010101010101010101010182 +:109ED0000101010101010101010101010101010172 +:109EE0000101010101010101010101010101010162 +:109EF0000101010101010101010101010101010152 +:109F00000101010101010101010101010101010141 +:109F10000101010101010101010101010101010131 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010101010101010101F1 +:109F600001010101010101010101010101010101E1 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010101010101010101C1 +:109F900001010101010101010101010101010101B1 +:109FA00001010101010101010101010101010101A1 +:109FB0000101010101010101010101010101010191 +:109FC0000101010101010101010101010101010181 +:109FD0000101010101010101010101010101010171 +:109FE0000101010101010101010101010101010161 +:109FF0000101010101010101010101010101010151 +:10A000000101010101010101010101010101010140 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A20000010101010101010101010101010101013E +:10A21000010101010101010101010101010101012E +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E0000101010101010101000000000000000066 +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E0000000000000000000010101010101010162 +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010101B9 +:10A7900001010101010101010101010101010101A9 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101020202020202020250 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020202020202020202021A +:10B61000020202020202020202020202020202020A +:10B6200002020202020202020202020202020202FA +:10B6300002020202020202020202020202020202EA +:10B6400002020202020202020202020202020202DA +:10B6500002020202020202020202020202020202CA +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020202020202020202020202028A +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C000020202020202020202020202020202025A +:10B6D000020202020202020202020202020202024A +:10B6E000020202020202020202020202020202023A +:10B6F000020202020202020202020202020202022A +:10B700000202020202020202020202020202020219 +:10B710000202020202020202020202020202020209 +:10B7200002020202020202020202020202020202F9 +:10B7300002020202020202020202020202020202E9 +:10B7400002020202020202020202020202020202D9 +:10B7500002020202020202020202020202020202C9 +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000202020202020202020202020202020249 +:10B7E0000202020202020202020202020202020239 +:10B7F0000202020202020202020202020202020229 +:10B800000202020202020202020202020202020218 +:10B810000202020202020202020202020202020208 +:10B8200002020202020202020202020202020202F8 +:10B8300002020202020202020202020202020202E8 +:10B8400002020202020202020202020202020202D8 +:10B8500002020202020202020202020202020202C8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000202020202020202020202020202020248 +:10B8E0000202020202020202020202020202020238 +:10B8F0000202020202020202020202020202020228 +:10B900000202020202020202020202020202020217 +:10B910000202020202020202020202020202020207 +:10B9200002020202020202020202020202020202F7 +:10B9300002020202020202020202020202020202E7 +:10B9400002020202020202020202020202020202D7 +:10B9500002020202020202020202020202020202C7 +:10B9600002020202020202020202020202020202B7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000202020202020202020202020202020247 +:10B9E0000202020202020202020202020202020237 +:10B9F0000202020202020202020202020202020227 +:10BA00000202020202020202020202020202020216 +:10BA10000202020202020202020202020202020206 +:10BA200002020202020202020202020202020202F6 +:10BA300002020202020202020202020202020202E6 +:10BA400002020202020202020202020202020202D6 +:10BA500002020202020202020202020202020202C6 +:10BA600002020202020202020202020202020202B6 +:10BA700002020202020202020202020202020202A6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000202020202020202020202020202020246 +:10BAE0000202020202020202020202020202020236 +:10BAF0000202020202020202020202020202020226 +:10BB00000202020202020202020202020202020215 +:10BB10000202020202020202020202020202020205 +:10BB200002020202020202020202020202020202F5 +:10BB300002020202020202020202020202020202E5 +:10BB400002020202020202020202020202020202D5 +:10BB500002020202020202020202020202020202C5 +:10BB600002020202020202020202020202020202B5 +:10BB700002020202020202020202020202020202A5 +:10BB80000202020202020202020202020202020295 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020255 +:10BBD0000202020202020202020202020202020245 +:10BBE0000202020202020202020202020202020235 +:10BBF0000202020202020202020202020202020225 +:10BC00000202020202020202020202020202020214 +:10BC10000202020202020202020202020202020204 +:10BC200002020202020202020202020202020202F4 +:10BC300002020202020202020202020202020202E4 +:10BC400002020202020202020202020202020202D4 +:10BC500002020202020202020202020202020202C4 +:10BC600002020202020202020202020202020202B4 +:10BC700002020202020202020202020202020202A4 +:10BC80000202020202020202020202020202020294 +:10BC90000202020202020202020202020202020284 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000202020202020202020202020202020244 +:10BCE0000202020202020202020202020202020234 +:10BCF0000202020202020202020202020202020224 +:10BD00000202020202020202020202020202020213 +:10BD10000202020202020202020202020202020203 +:10BD200002020202020202020202020202020202F3 +:10BD300002020202020202020202020202020202E3 +:10BD400002020202020202020202020202020202D3 +:10BD500002020202020202020202020202020202C3 +:10BD600002020202020202020202020202020202B3 +:10BD700002020202020202020202020202020202A3 +:10BD80000202020202020202020202020202020293 +:10BD90000202020202020202020202020202020283 +:10BDA0000202020202020202020202020202020273 +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000202020202020202020202020202020243 +:10BDE0000202020202020202020202020202020233 +:10BDF0000202020202020202020202020202020223 +:10BE00000202020202020202020202020202020212 +:10BE10000202020202020202020202020202020202 +:10BE200002020202020202020202020202020202F2 +:10BE300002020202020202020202020202020202E2 +:10BE400002020202020202020202020202020202D2 +:10BE500002020202020202020202020202020202C2 +:10BE600002020202020202020202020202020202B2 +:10BE700002020202020202020202020202020202A2 +:10BE80000202020202020202020202020202020292 +:10BE90000202020202020202020202020202020282 +:10BEA0000202020202020202020202020202020272 +:10BEB0000202020202020202020202020202020262 +:10BEC0000202020202020202020202020202020252 +:10BED0000202020202020202020202020202020242 +:10BEE0000202020202020202020202020202020232 +:10BEF0000202020202020202020202020202020222 +:10BF00000202020202020202020202020202020211 +:10BF10000202020202020202020202020202020201 +:10BF200002020202020202020202020202020202F1 +:10BF300002020202020202020202020202020202E1 +:10BF400002020202020202020202020202020202D1 +:10BF500002020202020202020202020202020202C1 +:10BF600002020202020202020202020202020202B1 +:10BF700002020202020202020202020202020202A1 +:10BF80000202020202020202020202020202020291 +:10BF90000202020202020202020202020202020281 +:10BFA0000202020202020202020202020202020271 +:10BFB0000202020202020202020202020202020261 +:10BFC0000202020202020202020202020202020251 +:10BFD0000202020202020202020202020202020241 +:10BFE0000202020202020202020202020202020231 +:10BFF0000202020202020202020202020202020221 +:10C000000202020202020202020202020202020210 +:10C010000202020202020202020202020202020200 +:10C0200002020202020202020202020202020202F0 +:10C0300002020202020202020202020202020202E0 +:10C0400002020202020202020202020202020202D0 +:10C0500002020202020202020202020202020202C0 +:10C0600002020202020202020202020202020202B0 +:10C0700002020202020202020202020202020202A0 +:10C080000202020202020202020202020202020290 +:10C090000202020202020202020202020202020280 +:10C0A0000202020202020202020202020202020270 +:10C0B0000202020202020202020202020202020260 +:10C0C0000202020202020202020202020202020250 +:10C0D0000202020202020202020202020202020240 +:10C0E0000202020202020202020202020202020230 +:10C0F0000202020202020202020202020202020220 +:10C10000020202020202020202020202020202020F +:10C1100002020202020202020202020202020202FF +:10C1200002020202020202020202020202020202EF +:10C1300002020202020202020202020202020202DF +:10C1400002020202020202020202020202020202CF +:10C1500002020202020202020202020202020202BF +:10C1600002020202020202020202020202020202AF +:10C17000020202020202020202020202020202029F +:10C18000020202020202020202020202020202028F +:10C19000020202020202020202020202020202027F +:10C1A000020202020202020202020202020202026F +:10C1B000020202020202020202020202020202025F +:10C1C000020202020202020202020202020202024F +:10C1D000020202020202020202020202020202023F +:10C1E000020202020202020202020202020202022F +:10C1F000020202020202020202020202020202021F +:10C20000020202020202020202020202020202020E +:10C2100002020202020202020202020202020202FE +:10C2200002020202020202020202020202020202EE +:10C2300002020202020202020202020202020202DE +:10C2400002020202020202020202020202020202CE +:10C2500002020202020202020202020202020202BE +:10C2600002020202020202020202020202020202AE +:10C27000020202020202020202020202020202029E +:10C28000020202020202020202020202020202028E +:10C29000020202020202020202020202020202027E +:10C2A000020202020202020202020202020202026E +:10C2B000020202020202020202020202020202025E +:10C2C000020202020202020202020202020202024E +:10C2D000020202020202020202020202020202023E +:10C2E000020202020202020202020202020202022E +:10C2F000020202020202020202020202020202021E +:10C30000020202020202020202020202020202020D +:10C3100002020202020202020202020202020202FD +:10C3200002020202020202020202020202020202ED +:10C3300002020202020202020202020202020202DD +:10C3400002020202020202020202020202020202CD +:10C3500002020202020202020202020202020202BD +:10C3600002020202020202020202020202020202AD +:10C37000020202020202020202020202020202029D +:10C38000020202020202020202020202020202028D +:10C39000020202020202020202020202020202027D +:10C3A000020202020202020202020202020202026D +:10C3B000020202020202020202020202020202025D +:10C3C000020202020202020202020202020202024D +:10C3D000020202020202020202020202020202023D +:10C3E000020202020202020200000000000000003D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000010101010101010141 +:10C7F0000101010101010101010101010101010129 +:10C800000101010101010101010101010101010118 +:10C810000101010101010101010101010101010108 +:10C8200001010101010101010101010101010101F8 +:10C8300001010101010101010101010101010101E8 +:10C8400001010101010101010101010101010101D8 +:10C8500001010101010101010101010101010101C8 +:10C8600001010101010101010101010101010101B8 +:10C8700001010101010101010101010101010101A8 +:10C880000101010101010101010101010101010198 +:10C890000101010101010101010101010101010188 +:10C8A0000101010101010101010101010101010178 +:10C8B0000101010101010101010101010101010168 +:10C8C0000101010101010101010101010101010158 +:10C8D0000101010101010101010101010101010148 +:10C8E0000101010101010101010101010101010138 +:10C8F0000101010101010101010101010101010128 +:10C900000101010101010101010101010101010117 +:10C910000101010101010101010101010101010107 +:10C9200001010101010101010101010101010101F7 +:10C9300001010101010101010101010101010101E7 +:10C9400001010101010101010101010101010101D7 +:10C9500001010101010101010101010101010101C7 +:10C9600001010101010101010101010101010101B7 +:10C9700001010101010101010101010101010101A7 +:10C980000101010101010101010101010101010197 +:10C990000101010101010101010101010101010187 +:10C9A0000101010101010101010101010101010177 +:10C9B0000101010101010101010101010101010167 +:10C9C0000101010101010101010101010101010157 +:10C9D0000101010101010101010101010101010147 +:10C9E0000101010101010101010101010101010137 +:10C9F0000101010101010101010101010101010127 +:10CA00000101010101010101010101010101010116 +:10CA10000101010101010101010101010101010106 +:10CA200001010101010101010101010101010101F6 +:10CA300001010101010101010101010101010101E6 +:10CA400001010101010101010101010101010101D6 +:10CA500001010101010101010101010101010101C6 +:10CA600001010101010101010101010101010101B6 +:10CA700001010101010101010101010101010101A6 +:10CA80000101010101010101010101010101010196 +:10CA90000101010101010101010101010101010186 +:10CAA0000101010101010101010101010101010176 +:10CAB0000101010101010101010101010101010166 +:10CAC0000101010101010101010101010101010156 +:10CAD0000101010101010101010101010101010146 +:10CAE0000101010101010101010101010101010136 +:10CAF0000101010101010101010101010101010126 +:10CB00000101010101010101010101010101010115 +:10CB10000101010101010101010101010101010105 +:10CB200001010101010101010101010101010101F5 +:10CB300001010101010101010101010101010101E5 +:10CB400001010101010101010101010101010101D5 +:10CB500001010101010101010101010101010101C5 +:10CB600001010101010101010101010101010101B5 +:10CB700001010101010101010101010101010101A5 +:10CB80000101010101010101010101010101010195 +:10CB90000101010101010101010101010101010185 +:10CBA0000101010101010101010101010101010175 +:10CBB0000101010101010101010101010101010165 +:10CBC0000101010101010101010101010101010155 +:10CBD0000101010101010101010101010101010145 +:10CBE0000101010101010101010101010101010135 +:10CBF0000101010101010101010101010101010125 +:10CC00000101010101010101010101010101010114 +:10CC10000101010101010101010101010101010104 +:10CC200001010101010101010101010101010101F4 +:10CC300001010101010101010101010101010101E4 +:10CC400001010101010101010101010101010101D4 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010101A4 +:10CC80000101010101010101010101010101010194 +:10CC90000101010101010101010101010101010184 +:10CCA0000101010101010101010101010101010174 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010101A3 +:10CD80000101010101010101010101010101010193 +:10CD90000101010101010101010101010101010183 +:10CDA0000101010101010101010101010101010173 +:10CDB0000101010101010101010101010101010163 +:10CDC0000101010101010101010101010101010153 +:10CDD0000101010101010101010101010101010143 +:10CDE0000101010101010101010101010101010133 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010101A2 +:10CE80000101010101010101010101010101010192 +:10CE90000101010101010101010101010101010182 +:10CEA0000101010101010101010101010101010172 +:10CEB0000101010101010101010101010101010162 +:10CEC0000101010101010101010101010101010152 +:10CED0000101010101010101010101010101010142 +:10CEE0000101010101010101010101010101010132 +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400001010101010101010101010101010101D1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700001010101010101010101010101010101A1 +:10CF80000101010101010101010101010101010191 +:10CF90000101010101010101010101010101010181 +:10CFA0000101010101010101010101010101010171 +:10CFB0000101010101010101010101010101010161 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010141 +:10CFE0000101010101010101010101010101010131 +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010101010101010101010110 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010101010101010101010101010101C0 +:10D0600001010101010101010101010101010101B0 +:10D0700001010101010101010101010101010101A0 +:10D080000101010101010101010101010101010190 +:10D090000101010101010101010101010101010180 +:10D0A0000101010101010101010101010101010170 +:10D0B0000101010101010101010101010101010160 +:10D0C0000101010101010101010101010101010150 +:10D0D0000101010101010101010101010101010140 +:10D0E0000101010101010101010101010101010130 +:10D0F0000101010101010101010101010101010120 +:10D10000010101010101010101010101010101010F +:10D1100001010101010101010101010101010101FF +:10D1200001010101010101010101010101010101EF +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010101010101AE +:10D27000010101010101010101010101010101019E +:10D28000010101010101010101010101010101018E +:10D29000010101010101010101010101010101017E +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000010101010101010101010101010101012E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010101FC +:10D4200001010101010101010101010101010101EC +:10D4300001010101010101010101010101010101DC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101017C +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010101CA +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010101AA +:10D67000010101010101010101010101010101019A +:10D68000010101010101010101010101010101018A +:10D69000010101010101010101010101010101017A +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000010101010101010101010101010101014A +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010101A9 +:10D770000101010101010101010101010101010199 +:10D780000101010101010101010101010101010189 +:10D790000101010101010101010101010101010179 +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000101010101010101010101010101010149 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010101010101010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010147 +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010101010101010101010146 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF0000101010101010101010101010101010115 +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010184 +:10DC90000101010101010101010101010101010174 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010101010101010101010114 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010101010101010101010173 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE90000101010101010101010101010101010172 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101000000000000000028 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E0000000000000000000010101010101010124 +:10E4F000010101010101010101010101010101010C +:10E5000001010101010101010101010101010101FB +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010101DB +:10E5300001010101010101010101010101010101CB +:10E5400001010101010101010101010101010101BB +:10E5500001010101010101010101010101010101AB +:10E56000010101010101010101010101010101019B +:10E57000010101010101010101010101010101018B +:10E58000010101010101010101010101010101017B +:10E59000010101010101010101010101010101016B +:10E5A000010101010101010101010101010101015B +:10E5B000010101010101010101010101010101014B +:10E5C000010101010101010101010101010101013B +:10E5D000010101010101010101010101010101012B +:10E5E000010101010101010101010101010101011B +:10E5F000010101010101010101010101010101010B +:10E6000001010101010101010101010101010101FA +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101010101010101010101BA +:10E6500001010101010101010101010101010101AA +:10E66000010101010101010101010101010101019A +:10E67000010101010101010101010101010101018A +:10E68000010101010101010101010101010101017A +:10E69000010101010101010101010101010101016A +:10E6A000010101010101010101010101010101015A +:10E6B000010101010101010101010101010101014A +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E0000101010101010101020202020202020212 +:10E6F00002020202020202020202020202020202FA +:10E7000002020202020202020202020202020202E9 +:10E7100002020202020202020202020202020202D9 +:10E7200002020202020202020202020202020202C9 +:10E7300002020202020202020202020202020202B9 +:10E7400002020202020202020202020202020202A9 +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000202020202020202020202020202020229 +:10E7D0000202020202020202020202020202020219 +:10E7E0000202020202020202020202020202020209 +:10E7F00002020202020202020202020202020202F9 +:10E8000002020202020202020202020202020202E8 +:10E8100002020202020202020202020202020202D8 +:10E8200002020202020202020202020202020202C8 +:10E8300002020202020202020202020202020202B8 +:10E8400002020202020202020202020202020202A8 +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C0000202020202020202020202020202020228 +:10E8D0000202020202020202020202020202020218 +:10E8E0000202020202020202020202020202020208 +:10E8F00002020202020202020202020202020202F8 +:10E9000002020202020202020202020202020202E7 +:10E9100002020202020202020202020202020202D7 +:10E9200002020202020202020202020202020202C7 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202020202020202020202020202F7 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020202020202020202020202020202C6 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020203 +:10EDF00002020202020202020202020202020202F3 +:10EE000002020202020202020202020202020202E2 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202020202020202020202F2 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020202020202020202020202A1 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020202020202020221 +:10EFD0000202020202020202020202020202020211 +:10EFE0000202020202020202020202020202020201 +:10EFF00002020202020202020202020202020202F1 +:10F0000002020202020202020202020202020202E0 +:10F0100002020202020202020202020202020202D0 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020202020202020202020202B0 +:10F0400002020202020202020202020202020202A0 +:10F050000202020202020202020202020202020290 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020202020202020202020230 +:10F0C0000202020202020202020202020202020220 +:10F0D0000202020202020202020202020202020210 +:10F0E0000202020202020202020202020202020200 +:10F0F00002020202020202020202020202020202F0 +:10F1000002020202020202020202020202020202DF +:10F1100002020202020202020202020202020202CF +:10F1200002020202020202020202020202020202BF +:10F1300002020202020202020202020202020202AF +:10F14000020202020202020202020202020202029F +:10F15000020202020202020202020202020202028F +:10F16000020202020202020202020202020202027F +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A000020202020202020202020202020202023F +:10F1B000020202020202020202020202020202022F +:10F1C000020202020202020202020202020202021F +:10F1D000020202020202020202020202020202020F +:10F1E00002020202020202020202020202020202FF +:10F1F00002020202020202020202020202020202EF +:10F2000002020202020202020202020202020202DE +:10F2100002020202020202020202020202020202CE +:10F2200002020202020202020202020202020202BE +:10F2300002020202020202020202020202020202AE +:10F24000020202020202020202020202020202029E +:10F25000020202020202020202020202020202028E +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202020202020202023E +:10F2B000020202020202020202020202020202022E +:10F2C000020202020202020202020202020202021E +:10F2D000020202020202020202020202020202020E +:10F2E00002020202020202020202020202020202FE +:10F2F00002020202020202020202020202020202EE +:10F3000002020202020202020202020202020202DD +:10F3100002020202020202020202020202020202CD +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020202020202AD +:10F34000020202020202020202020202020202029D +:10F35000020202020202020202020202020202028D +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B000020202020202020202020202020202022D +:10F3C000020202020202020202020202020202021D +:10F3D000020202020202020202020202020202020D +:10F3E00002020202020202020202020202020202FD +:10F3F00002020202020202020202020202020202ED +:10F4000002020202020202020202020202020202DC +:10F4100002020202020202020202020202020202CC +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020202029C +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202020202027C +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C000020202020202020202020202020202021C +:10F4D000020202020202020202020202020202020C +:10F4E00002020202020202020202020202020202FC +:10F4F00002020202020202020202020202020202EC +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020202020202020202CB +:10F5200002020202020202020202020202020202BB +:10F5300002020202020202020202020202020202AB +:10F54000020202020202020202020202020202029B +:10F55000020202020202020202020202020202028B +:10F56000020202020202020202020202020202027B +:10F57000020202020202020202020202020202026B +:10F58000020202020202020202020202020202025B +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B000020202020202020202020202020202022B +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020202020202020202020B +:10F5E00002020202020202020202020202020202FB +:10F5F00002020202020202020202020202020202EB +:10F6000002020202020202020202020202020202DA +:10F6100002020202020202020202020202020202CA +:10F6200002020202020202020202020202020202BA +:10F6300002020202020202020202020202020202AA +:10F64000020202020202020202020202020202029A +:10F65000020202020202020202020202020202028A +:10F66000020202020202020202020202020202027A +:10F67000020202020202020202020202020202026A +:10F68000020202020202020202020202020202025A +:10F69000020202020202020202020202020202024A +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020202020202020202020A +:10F6E00002020202020202020202020202020202FA +:10F6F00002020202020202020202020202020202EA +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020202020202020202020202C9 +:10F7200002020202020202020202020202020202B9 +:10F7300002020202020202020202020202020202A9 +:10F740000202020202020202020202020202020299 +:10F750000202020202020202020202020202020289 +:10F760000202020202020202020202020202020279 +:10F770000202020202020202020202020202020269 +:10F780000202020202020202020202020202020259 +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020202020202020202020202B8 +:10F8300002020202020202020202020202020202A8 +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202020202020202020202A7 +:10F940000202020202020202020202020202020297 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020277 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020202020202020202020243 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202020202020202020223 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202020202020242 +:10FEA0000202020202020202020202020202020232 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020202020202020202D1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202020202020241 +:10FFA0000202020202020202020202020202020231 +:10FFB0000202020202020202020202020202020221 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202020202F1 +:10FFF00002020202020202020202020202020202E1 +:020000021000EC +:1000000002020202020202020202020202020202D0 +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020202E0 +:1001000002020202020202020202020202020202CF +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C000020202020202020202020202020202020F +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020000000000000000FF +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E00000000000000000006D00000000000000A1 +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:10064000010101010101010101010101010101019A +:10065000010101010101010101010101010101018A +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:10068000010101010101010101010101010101015A +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010101010101013A +:1006B000010101010101010101010101010101012A +:1006C000010101010101010101010101010101011A +:1006D000010101010101010101010101010101010A +:1006E00001010101010101010101010101010101FA +:1006F00001010101010101010101010101010101EA +:1007000001010101010101010101010101010101D9 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010198 +:100850000101010101010101010101010101010188 +:100860000101010101010101010101010101010178 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010118 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000001010101010101010101010101010101D2 +:100E100001010101010101010101010101010101C2 +:100E200001010101010101010101010101010101B2 +:100E300001010101010101010101010101010101A2 +:100E40000101010101010101010101010101010192 +:100E50000101010101010101010101010101010182 +:100E60000101010101010101010101010101010172 +:100E70000101010101010101010101010101010162 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00001010101010101010101010101010101E2 +:100F000001010101010101010101010101010101D1 +:100F100001010101010101010101010101010101C1 +:100F200001010101010101010101010101010101B1 +:100F300001010101010101010101010101010101A1 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000101010101010101010101010101010171 +:100F70000101010101010101010101010101010161 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000101010101010101010101010101010111 +:100FD0000101010101010101010101010101010101 +:100FE00001010101010101010101010101010101F1 +:100FF00001010101010101010101010101010101E1 +:1010000001010101010101010101010101010101D0 +:1010100001010101010101010101010101010101C0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000101010101010101010101010101010170 +:101070000101010101010101010101010101010160 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010101010101BF +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:10116000010101010101010101010101010101016F +:10117000010101010101010101010101010101015F +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010101010101BE +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101016E +:10127000010101010101010101010101010101015E +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101010101010101010101BD +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101016D +:10137000010101010101010101010101010101015D +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101016C +:10147000010101010101010101010101010101015C +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101018B +:10155000010101010101010101010101010101017B +:10156000010101010101010101010101010101016B +:10157000010101010101010101010101010101015B +:10158000010101010101010101010101010101014B +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010101010101010101019A +:10164000010101010101010101010101010101018A +:10165000010101010101010101010101010101017A +:10166000010101010101010101010101010101016A +:10167000010101010101010101010101010101015A +:10168000010101010101010101010101010101014A +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000000000000000000000F5 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000000000000000B4 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000000000000000000000000000054 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000000000000000000000034 +:101CB0000000000000000000000000000000000024 +:101CC0000000000000000000000000000000000014 +:101CD0000000000000000000000000000000000004 +:101CE00000000000000000000000000000000000F4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020202D0 +:1020F00002020202020202020202020202020202C0 +:1021000002020202020202020202020202020202AF +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020202020202020202020F +:1021B00002020202020202020202020202020202FF +:1021C00002020202020202020202020202020202EF +:1021D00002020202020202020202020202020202DF +:1021E00002020202020202020202020202020202CF +:1021F00002020202020202020202020202020202BF +:1022000002020202020202020202020202020202AE +:10221000020202020202020202020202020202029E +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A000020202020202020202020202020202020E +:1022B00002020202020202020202020202020202FE +:1022C00002020202020202020202020202020202EE +:1022D00002020202020202020202020202020202DE +:1022E00002020202020202020202020202020202CE +:1022F00002020202020202020202020202020202BE +:1023000002020202020202020202020202020202AD +:10231000020202020202020202020202020202029D +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A000020202020202020202020202020202020D +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020202020202ED +:1023D00002020202020202020202020202020202DD +:1023E00002020202020202020202020202020202CD +:1023F00002020202020202020202020202020202BD +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202020202020202020202DC +:1024E00002020202020202020202020202020202CC +:1024F00002020202020202020202020202020202BC +:1025000002020202020202020202020202020202AB +:10251000020202020202020202020202020202029B +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C00002020202020202020202020202020202EB +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020202CB +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202020202020202020202DA +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020202D3 +:102DE00002020202020202020202020202020202C3 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020202D2 +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000101010101010101010101010101010135 +:103B80000101010101010101010101010101010125 +:103B90000101010101010101010101010101010115 +:103BA0000101010101010101010101010101010105 +:103BB00001010101010101010101010101010101F5 +:103BC00001010101010101010101010101010101E5 +:103BD00001010101010101010101010101010101D5 +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C60000101010101010101010101010101010144 +:103C70000101010101010101010101010101010134 +:103C80000101010101010101010101010101010124 +:103C90000101010101010101010101010101010114 +:103CA0000101010101010101010101010101010104 +:103CB00001010101010101010101010101010101F4 +:103CC00001010101010101010101010101010101E4 +:103CD00001010101010101010101010101010101D4 +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010101B4 +:103D000001010101010101010101010101010101A3 +:103D10000101010101010101010101010101010193 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000101010101010101010101010101010103 +:103DB00001010101010101010101010101010101F3 +:103DC00001010101010101010101010101010101E3 +:103DD00001010101010101010101010101010101D3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101010101010101010101B3 +:103E000001010101010101010101010101010101A2 +:103E10000101010101010101010101010101010192 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010172 +:103E40000101010101010101010101010101010162 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000101010101010101010101010101010112 +:103EA0000101010101010101010101010101010102 +:103EB00001010101010101010101010101010101F2 +:103EC00001010101010101010101010101010101E2 +:103ED00001010101010101010101010101010101D2 +:103EE00001010101010101010101010101010101C2 +:103EF00001010101010101010101010101010101B2 +:103F000001010101010101010101010101010101A1 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010171 +:103F40000101010101010101010101010101010161 +:103F50000101010101010101010101010101010151 +:103F60000101010101010101010101010101010141 +:103F70000101010101010101010101010101010131 +:103F80000101010101010101010101010101010121 +:103F90000101010101010101010101010101010111 +:103FA0000101010101010101010101010101010101 +:103FB00001010101010101010101010101010101F1 +:103FC00001010101010101010101010101010101E1 +:103FD00001010101010101010101010101010101D1 +:103FE00001010101010101010101010101010101C1 +:103FF00001010101010101010101010101010101B1 +:1040000001010101010101010101010101010101A0 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:104030000101010101010101010101010101010170 +:104040000101010101010101010101010101010160 +:104050000101010101010101010101010101010150 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:104080000101010101010101010101010101010120 +:104090000101010101010101010101010101010110 +:1040A0000101010101010101010101010101010100 +:1040B00001010101010101010101010101010101F0 +:1040C00001010101010101010101010101010101E0 +:1040D00001010101010101010101010101010101D0 +:1040E00001010101010101010101010101010101C0 +:1040F00001010101010101010101010101010101B0 +:10410000010101010101010101010101010101019F +:10411000010101010101010101010101010101018F +:10412000010101010101010101010101010101017F +:10413000010101010101010101010101010101016F +:10414000010101010101010101010101010101015F +:10415000010101010101010101010101010101014F +:10416000010101010101010101010101010101013F +:10417000010101010101010101010101010101012F +:10418000010101010101010101010101010101011F +:10419000010101010101010101010101010101010F +:1041A00001010101010101010101010101010101FF +:1041B00001010101010101010101010101010101EF +:1041C00001010101010101010101010101010101DF +:1041D00001010101010101010101010101010101CF +:1041E00001010101010101010101010101010101BF +:1041F00001010101010101010101010101010101AF +:10420000010101010101010101010101010101019E +:10421000010101010101010101010101010101018E +:10422000010101010101010101010101010101017E +:10423000010101010101010101010101010101016E +:10424000010101010101010101010101010101015E +:10425000010101010101010101010101010101014E +:10426000010101010101010101010101010101013E +:10427000010101010101010101010101010101012E +:10428000010101010101010101010101010101011E +:10429000010101010101010101010101010101010E +:1042A00001010101010101010101010101010101FE +:1042B00001010101010101010101010101010101EE +:1042C00001010101010101010101010101010101DE +:1042D00001010101010101010101010101010101CE +:1042E00001010101010101010101010101010101BE +:1042F00001010101010101010101010101010101AE +:10430000010101010101010101010101010101019D +:10431000010101010101010101010101010101018D +:10432000010101010101010101010101010101017D +:10433000010101010101010101010101010101016D +:10434000010101010101010101010101010101015D +:10435000010101010101010101010101010101014D +:10436000010101010101010101010101010101013D +:10437000010101010101010101010101010101012D +:10438000010101010101010101010101010101011D +:10439000010101010101010101010101010101010D +:1043A00001010101010101010101010101010101FD +:1043B00001010101010101010101010101010101ED +:1043C00001010101010101010101010101010101DD +:1043D00001010101010101010101010101010101CD +:1043E00001010101010101010101010101010101BD +:1043F00001010101010101010101010101010101AD +:10440000010101010101010101010101010101019C +:10441000010101010101010101010101010101018C +:10442000010101010101010101010101010101017C +:10443000010101010101010101010101010101016C +:10444000010101010101010101010101010101015C +:10445000010101010101010101010101010101014C +:10446000010101010101010101010101010101013C +:10447000010101010101010101010101010101012C +:10448000010101010101010101010101010101011C +:10449000010101010101010101010101010101010C +:1044A00001010101010101010101010101010101FC +:1044B00001010101010101010101010101010101EC +:1044C00001010101010101010101010101010101DC +:1044D00001010101010101010101010101010101CC +:1044E00001010101010101010101010101010101BC +:1044F00001010101010101010101010101010101AC +:10450000010101010101010101010101010101019B +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101011B +:10459000010101010101010101010101010101010B +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101010101010101010101EB +:1045C00001010101010101010101010101010101DB +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:10468000010101010101010101010101010101011A +:10469000010101010101010101010101010101010A +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010101EA +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F000010101010101010101010101010101019C +:10550000010101010101010101010101010101018B +:10551000010101010101010101010101010101017B +:10552000010101010101010101010101010101016B +:10553000010101010101010101010101010101015B +:10554000010101010101010101010101010101014B +:10555000010101010101010101010101010101013B +:10556000010101010101010101010101010101012B +:10557000010101010101010101010101010101011B +:10558000010101010101010101010101010101010B +:1055900001010101010101010101010101010101FB +:1055A00001010101010101010101010101010101EB +:1055B00001010101010101010101010101010101DB +:1055C00001010101010101010101010101010101CB +:1055D00001010101010101010101010101010101BB +:1055E00001010101010101010101010101010101AB +:1055F000010101010101010101010101010101019B +:10560000010101010101010101010101010101018A +:10561000010101010101010101010101010101017A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000020202020202020202020202020202028A +:105700000202020202020202020202020202020279 +:105710000202020202020202020202020202020269 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020202020202020202D8 +:1058B00002020202020202020202020202020202C8 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020202020202020202D7 +:1059B00002020202020202020202020202020202C7 +:1059C00002020202020202020202020202020202B7 +:1059D00002020202020202020202020202020202A7 +:1059E0000202020202020202020202020202020297 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A40000202020202020202020202020202020236 +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002020202020202020202020202020202E6 +:105AA00002020202020202020202020202020202D6 +:105AB00002020202020202020202020202020202C6 +:105AC00002020202020202020202020202020202B6 +:105AD00002020202020202020202020202020202A6 +:105AE0000202020202020202020202020202020296 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020202020202020202020202020202E5 +:105BA00002020202020202020202020202020202D5 +:105BB00002020202020202020202020202020202C5 +:105BC00002020202020202020202020202020202B5 +:105BD00002020202020202020202020202020202A5 +:105BE0000202020202020202020202020202020295 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020202020202020202020202020202E4 +:105CA00002020202020202020202020202020202D4 +:105CB00002020202020202020202020202020202C4 +:105CC00002020202020202020202020202020202B4 +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202020202020202020294 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020202020202020202020202E3 +:105DA00002020202020202020202020202020202D3 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020202020202020202B3 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202020202020202020293 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020202B2 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202020202020202020292 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0006D0000000000000001010101010101011C +:107000000101010101010101010101010101010170 +:107010000101010101010101010101010101010160 +:107020000101010101010101010101010101010150 +:107030000101010101010101010101010101010140 +:107040000101010101010101010101010101010130 +:107050000101010101010101010101010101010120 +:107060000101010101010101010101010101010110 +:107070000101010101010101010101010101010100 +:1070800001010101010101010101010101010101F0 +:1070900001010101010101010101010101010101E0 +:1070A00001010101010101010101010101010101D0 +:1070B00001010101010101010101010101010101C0 +:1070C00001010101010101010101010101010101B0 +:1070D00001010101010101010101010101010101A0 +:1070E0000101010101010101010101010101010190 +:1070F0000101010101010101010101010101010180 +:10710000010101010101010101010101010101016F +:10711000010101010101010101010101010101015F +:10712000010101010101010101010101010101014F +:10713000010101010101010101010101010101013F +:10714000010101010101010101010101010101012F +:10715000010101010101010101010101010101011F +:10716000010101010101010101010101010101010F +:1071700001010101010101010101010101010101FF +:1071800001010101010101010101010101010101EF +:1071900001010101010101010101010101010101DF +:1071A00001010101010101010101010101010101CF +:1071B00001010101010101010101010101010101BF +:1071C00001010101010101010101010101010101AF +:1071D000010101010101010101010101010101019F +:1071E000010101010101010101010101010101018F +:1071F000010101010101010101010101010101017F +:10720000010101010101010101010101010101016E +:10721000010101010101010101010101010101015E +:10722000010101010101010101010101010101014E +:10723000010101010101010101010101010101013E +:10724000010101010101010101010101010101012E +:10725000010101010101010101010101010101011E +:10726000010101010101010101010101010101010E +:1072700001010101010101010101010101010101FE +:1072800001010101010101010101010101010101EE +:1072900001010101010101010101010101010101DE +:1072A00001010101010101010101010101010101CE +:1072B00001010101010101010101010101010101BE +:1072C00001010101010101010101010101010101AE +:1072D000010101010101010101010101010101019E +:1072E000010101010101010101010101010101018E +:1072F000010101010101010101010101010101017E +:10730000010101010101010101010101010101016D +:10731000010101010101010101010101010101015D +:10732000010101010101010101010101010101014D +:10733000010101010101010101010101010101013D +:10734000010101010101010101010101010101012D +:10735000010101010101010101010101010101011D +:10736000010101010101010101010101010101010D +:1073700001010101010101010101010101010101FD +:1073800001010101010101010101010101010101ED +:1073900001010101010101010101010101010101DD +:1073A00001010101010101010101010101010101CD +:1073B00001010101010101010101010101010101BD +:1073C00001010101010101010101010101010101AD +:1073D000010101010101010101010101010101019D +:1073E000010101010101010101010101010101018D +:1073F000010101010101010101010101010101017D +:10740000010101010101010101010101010101016C +:10741000010101010101010101010101010101015C +:10742000010101010101010101010101010101014C +:10743000010101010101010101010101010101013C +:10744000010101010101010101010101010101012C +:10745000010101010101010101010101010101011C +:10746000010101010101010101010101010101010C +:1074700001010101010101010101010101010101FC +:1074800001010101010101010101010101010101EC +:1074900001010101010101010101010101010101DC +:1074A00001010101010101010101010101010101CC +:1074B00001010101010101010101010101010101BC +:1074C00001010101010101010101010101010101AC +:1074D000010101010101010101010101010101019C +:1074E000010101010101010101010101010101018C +:1074F000010101010101010101010101010101017C +:10750000010101010101010101010101010101016B +:10751000010101010101010101010101010101015B +:10752000010101010101010101010101010101014B +:10753000010101010101010101010101010101013B +:10754000010101010101010101010101010101012B +:10755000010101010101010101010101010101011B +:10756000010101010101010101010101010101010B +:1075700001010101010101010101010101010101FB +:1075800001010101010101010101010101010101EB +:1075900001010101010101010101010101010101DB +:1075A00001010101010101010101010101010101CB +:1075B00001010101010101010101010101010101BB +:1075C00001010101010101010101010101010101AB +:1075D000010101010101010101010101010101019B +:1075E000010101010101010101010101010101018B +:1075F000010101010101010101010101010101017B +:10760000010101010101010101010101010101016A +:10761000010101010101010101010101010101015A +:10762000010101010101010101010101010101014A +:10763000010101010101010101010101010101013A +:10764000010101010101010101010101010101012A +:10765000010101010101010101010101010101011A +:10766000010101010101010101010101010101010A +:1076700001010101010101010101010101010101FA +:1076800001010101010101010101010101010101EA +:1076900001010101010101010101010101010101DA +:1076A00001010101010101010101010101010101CA +:1076B00001010101010101010101010101010101BA +:1076C00001010101010101010101010101010101AA +:1076D000010101010101010101010101010101019A +:1076E000010101010101010101010101010101018A +:1076F000010101010101010101010101010101017A +:107700000101010101010101010101010101010169 +:107710000101010101010101010101010101010159 +:107720000101010101010101010101010101010149 +:107730000101010101010101010101010101010139 +:107740000101010101010101010101010101010129 +:107750000101010101010101010101010101010119 +:107760000101010101010101010101010101010109 +:1077700001010101010101010101010101010101F9 +:1077800001010101010101010101010101010101E9 +:1077900001010101010101010101010101010101D9 +:1077A00001010101010101010101010101010101C9 +:1077B00001010101010101010101010101010101B9 +:1077C00001010101010101010101010101010101A9 +:1077D0000101010101010101010101010101010199 +:1077E0000101010101010101010101010101010189 +:1077F0000101010101010101010101010101010179 +:107800000101010101010101010101010101010168 +:107810000101010101010101010101010101010158 +:107820000101010101010101010101010101010148 +:107830000101010101010101010101010101010138 +:107840000101010101010101010101010101010128 +:107850000101010101010101010101010101010118 +:107860000101010101010101010101010101010108 +:1078700001010101010101010101010101010101F8 +:1078800001010101010101010101010101010101E8 +:1078900001010101010101010101010101010101D8 +:1078A00001010101010101010101010101010101C8 +:1078B00001010101010101010101010101010101B8 +:1078C00001010101010101010101010101010101A8 +:1078D0000101010101010101010101010101010198 +:1078E0000101010101010101010101010101010188 +:1078F0000101010101010101010101010101010178 +:107900000101010101010101010101010101010167 +:107910000101010101010101010101010101010157 +:107920000101010101010101010101010101010147 +:107930000101010101010101010101010101010137 +:107940000101010101010101010101010101010127 +:107950000101010101010101010101010101010117 +:107960000101010101010101010101010101010107 +:1079700001010101010101010101010101010101F7 +:1079800001010101010101010101010101010101E7 +:1079900001010101010101010101010101010101D7 +:1079A00001010101010101010101010101010101C7 +:1079B00001010101010101010101010101010101B7 +:1079C00001010101010101010101010101010101A7 +:1079D0000101010101010101010101010101010197 +:1079E0000101010101010101010101010101010187 +:1079F0000101010101010101010101010101010177 +:107A00000101010101010101010101010101010166 +:107A10000101010101010101010101010101010156 +:107A20000101010101010101010101010101010146 +:107A30000101010101010101010101010101010136 +:107A40000101010101010101010101010101010126 +:107A50000101010101010101010101010101010116 +:107A60000101010101010101010101010101010106 +:107A700001010101010101010101010101010101F6 +:107A800001010101010101010101010101010101E6 +:107A900001010101010101010101010101010101D6 +:107AA00001010101010101010101010101010101C6 +:107AB00001010101010101010101010101010101B6 +:107AC00001010101010101010101010101010101A6 +:107AD0000101010101010101010101010101010196 +:107AE0000101010101010101010101010101010186 +:107AF0000101010101010101010101010101010176 +:107B00000101010101010101010101010101010165 +:107B10000101010101010101010101010101010155 +:107B20000101010101010101010101010101010145 +:107B30000101010101010101010101010101010135 +:107B40000101010101010101010101010101010125 +:107B50000101010101010101010101010101010115 +:107B60000101010101010101010101010101010105 +:107B700001010101010101010101010101010101F5 +:107B800001010101010101010101010101010101E5 +:107B900001010101010101010101010101010101D5 +:107BA00001010101010101010101010101010101C5 +:107BB00001010101010101010101010101010101B5 +:107BC00001010101010101010101010101010101A5 +:107BD0000101010101010101010101010101010195 +:107BE0000101010101010101010101010101010185 +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101010101010101010134 +:107C40000101010101010101010101010101010124 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010101010101010101E4 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD0000101010101010101010101010101010194 +:107CE0000101010101010101010101010101010184 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010101010101010101010123 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010101010101010101E3 +:107D900001010101010101010101010101010101D3 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F0000101010101010101000000000000000073 +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F000000000000000000001010101010101016F +:108A00000101010101010101010101010101010156 +:108A10000101010101010101010101010101010146 +:108A20000101010101010101010101010101010136 +:108A30000101010101010101010101010101010126 +:108A40000101010101010101010101010101010116 +:108A50000101010101010101010101010101010106 +:108A600001010101010101010101010101010101F6 +:108A700001010101010101010101010101010101E6 +:108A800001010101010101010101010101010101D6 +:108A900001010101010101010101010101010101C6 +:108AA00001010101010101010101010101010101B6 +:108AB00001010101010101010101010101010101A6 +:108AC0000101010101010101010101010101010196 +:108AD0000101010101010101010101010101010186 +:108AE0000101010101010101010101010101010176 +:108AF0000101010101010101010101010101010166 +:108B00000101010101010101010101010101010155 +:108B10000101010101010101010101010101010145 +:108B20000101010101010101010101010101010135 +:108B30000101010101010101010101010101010125 +:108B40000101010101010101010101010101010115 +:108B50000101010101010101010101010101010105 +:108B600001010101010101010101010101010101F5 +:108B700001010101010101010101010101010101E5 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010101010101B5 +:108BB00001010101010101010101010101010101A5 +:108BC0000101010101010101010101010101010195 +:108BD0000101010101010101010101010101010185 +:108BE0000101010101010101010101010101010175 +:108BF000010101010101010102020202020202025D +:108C00000202020202020202020202020202020244 +:108C10000202020202020202020202020202020234 +:108C20000202020202020202020202020202020224 +:108C30000202020202020202020202020202020214 +:108C40000202020202020202020202020202020204 +:108C500002020202020202020202020202020202F4 +:108C600002020202020202020202020202020202E4 +:108C700002020202020202020202020202020202D4 +:108C800002020202020202020202020202020202C4 +:108C900002020202020202020202020202020202B4 +:108CA00002020202020202020202020202020202A4 +:108CB0000202020202020202020202020202020294 +:108CC0000202020202020202020202020202020284 +:108CD0000202020202020202020202020202020274 +:108CE0000202020202020202020202020202020264 +:108CF0000202020202020202020202020202020254 +:108D00000202020202020202020202020202020243 +:108D10000202020202020202020202020202020233 +:108D20000202020202020202020202020202020223 +:108D30000202020202020202020202020202020213 +:108D40000202020202020202020202020202020203 +:108D500002020202020202020202020202020202F3 +:108D600002020202020202020202020202020202E3 +:108D700002020202020202020202020202020202D3 +:108D800002020202020202020202020202020202C3 +:108D900002020202020202020202020202020202B3 +:108DA00002020202020202020202020202020202A3 +:108DB0000202020202020202020202020202020293 +:108DC0000202020202020202020202020202020283 +:108DD0000202020202020202020202020202020273 +:108DE0000202020202020202020202020202020263 +:108DF0000202020202020202020202020202020253 +:108E00000202020202020202020202020202020242 +:108E10000202020202020202020202020202020232 +:108E20000202020202020202020202020202020222 +:108E30000202020202020202020202020202020212 +:108E40000202020202020202020202020202020202 +:108E500002020202020202020202020202020202F2 +:108E600002020202020202020202020202020202E2 +:108E700002020202020202020202020202020202D2 +:108E800002020202020202020202020202020202C2 +:108E900002020202020202020202020202020202B2 +:108EA00002020202020202020202020202020202A2 +:108EB0000202020202020202020202020202020292 +:108EC0000202020202020202020202020202020282 +:108ED0000202020202020202020202020202020272 +:108EE0000202020202020202020202020202020262 +:108EF0000202020202020202020202020202020252 +:108F00000202020202020202020202020202020241 +:108F10000202020202020202020202020202020231 +:108F20000202020202020202020202020202020221 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202020202020202020202D1 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020202020202020202A1 +:108FB0000202020202020202020202020202020291 +:108FC0000202020202020202020202020202020281 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202020202020261 +:108FF0000202020202020202020202020202020251 +:109000000202020202020202020202020202020240 +:109010000202020202020202020202020202020230 +:109020000202020202020202020202020202020220 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020202020202020202020202A0 +:1090B0000202020202020202020202020202020290 +:1090C0000202020202020202020202020202020280 +:1090D0000202020202020202020202020202020270 +:1090E0000202020202020202020202020202020260 +:1090F0000202020202020202020202020202020250 +:10910000020202020202020202020202020202023F +:10911000020202020202020202020202020202022F +:10912000020202020202020202020202020202021F +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D000020202020202020202020202020202026F +:1091E000020202020202020202020202020202025F +:1091F000020202020202020202020202020202024F +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202020202025E +:1092F000020202020202020202020202020202024E +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202029D +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202020202025D +:1093F000020202020202020202020202020202024D +:10940000020202020202020202020202020202023C +:10941000020202020202020202020202020202022C +:10942000020202020202020202020202020202021C +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020202AC +:1094A000020202020202020202020202020202029C +:1094B000020202020202020202020202020202028C +:1094C000020202020202020202020202020202027C +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202020202020202020202024C +:10950000020202020202020202020202020202023B +:10951000020202020202020202020202020202022B +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020202AB +:1095A000020202020202020202020202020202029B +:1095B000020202020202020202020202020202028B +:1095C000020202020202020202020202020202027B +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020202020202020202022A +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202020202029A +:1096B000020202020202020202020202020202028A +:1096C000020202020202020202020202020202027A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A0000202020202020202020202020202020299 +:1097B0000202020202020202020202020202020289 +:1097C0000202020202020202020202020202020279 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:109810000202020202020202020202020202020228 +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020202020298 +:1098B0000202020202020202020202020202020288 +:1098C0000202020202020202020202020202020278 +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B0000202020202020202020202020202020287 +:1099C0000202020202020202020202020202020277 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020202020226 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020202A6 +:109AA0000202020202020202020202020202020296 +:109AB0000202020202020202020202020202020286 +:109AC0000202020202020202020202020202020276 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020202A5 +:109BA0000202020202020202020202020202020295 +:109BB0000202020202020202020202020202020285 +:109BC0000202020202020202020202020202020275 +:109BD0000202020202020202020202020202020265 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020202A4 +:109CA0000202020202020202020202020202020294 +:109CB0000202020202020202020202020202020284 +:109CC0000202020202020202020202020202020274 +:109CD0000202020202020202020202020202020264 +:109CE0000202020202020202020202020202020254 +:109CF0000202020202020202020202020202020244 +:109D00000202020202020202020202020202020233 +:109D10000202020202020202020202020202020223 +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020202020202020202020202020202E3 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020202A3 +:109DA0000202020202020202020202020202020293 +:109DB0000202020202020202020202020202020283 +:109DC0000202020202020202020202020202020273 +:109DD0000202020202020202020202020202020263 +:109DE0000202020202020202020202020202020253 +:109DF0000202020202020202020202020202020243 +:109E00000202020202020202020202020202020232 +:109E10000202020202020202020202020202020222 +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202020202020202E2 +:109E600002020202020202020202020202020202D2 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020202A2 +:109EA0000202020202020202020202020202020292 +:109EB0000202020202020202020202020202020282 +:109EC0000202020202020202020202020202020272 +:109ED0000202020202020202020202020202020262 +:109EE0000202020202020202020202020202020252 +:109EF0000202020202020202020202020202020242 +:109F00000202020202020202020202020202020231 +:109F10000202020202020202020202020202020221 +:109F20000202020202020202020202020202020211 +:109F30000202020202020202020202020202020201 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202020202020202E1 +:109F600002020202020202020202020202020202D1 +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020202A1 +:109FA0000202020202020202020202020202020291 +:109FB0000202020202020202020202020202020281 +:109FC0000202020202020202020202020202020271 +:109FD0000202020202020202020202020202020261 +:109FE0000202020202020202020202020202020251 +:109FF0000202020202020202020202020202020241 +:10A000000202020202020202020202020202020230 +:10A010000202020202020202020202020202020220 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020202020202020202020202020202D0 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020202A0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020280 +:10A0C0000202020202020202020202020202020270 +:10A0D0000202020202020202020202020202020260 +:10A0E0000202020202020202020202020202020250 +:10A0F0000202020202020202020202020202020240 +:10A10000020202020202020202020202020202022F +:10A11000020202020202020202020202020202021F +:10A12000020202020202020202020202020202020F +:10A1300002020202020202020202020202020202FF +:10A1400002020202020202020202020202020202EF +:10A1500002020202020202020202020202020202DF +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A19000020202020202020202020202020202029F +:10A1A000020202020202020202020202020202028F +:10A1B000020202020202020202020202020202027F +:10A1C000020202020202020202020202020202026F +:10A1D000020202020202020202020202020202025F +:10A1E000020202020202020202020202020202024F +:10A1F000020202020202020202020202020202023F +:10A20000020202020202020202020202020202022E +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202020E +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202027E +:10A2C000020202020202020202020202020202026E +:10A2D000020202020202020202020202020202025E +:10A2E000020202020202020202020202020202024E +:10A2F000020202020202020202020202020202023E +:10A30000020202020202020202020202020202022D +:10A31000020202020202020202020202020202021D +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202024D +:10A3F000020202020202020200000000000000004D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000010101010101010151 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB10000101010101010101010101010101010125 +:10AB20000101010101010101010101010101010115 +:10AB30000101010101010101010101010101010105 +:10AB400001010101010101010101010101010101F5 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010101C5 +:10AB800001010101010101010101010101010101B5 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010185 +:10ABC0000101010101010101010101010101010175 +:10ABD0000101010101010101010101010101010165 +:10ABE0000101010101010101010101010101010155 +:10ABF0000101010101010101010101010101010145 +:10AC00000101010101010101010101010101010134 +:10AC10000101010101010101010101010101010124 +:10AC20000101010101010101010101010101010114 +:10AC30000101010101010101010101010101010104 +:10AC400001010101010101010101010101010101F4 +:10AC500001010101010101010101010101010101E4 +:10AC600001010101010101010101010101010101D4 +:10AC700001010101010101010101010101010101C4 +:10AC800001010101010101010101010101010101B4 +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010184 +:10ACC0000101010101010101010101010101010174 +:10ACD0000101010101010101010101010101010164 +:10ACE0000101010101010101010101010101010154 +:10ACF0000101010101010101010101010101010144 +:10AD00000101010101010101010101010101010133 +:10AD10000101010101010101010101010101010123 +:10AD20000101010101010101010101010101010113 +:10AD30000101010101010101010101010101010103 +:10AD400001010101010101010101010101010101F3 +:10AD500001010101010101010101010101010101E3 +:10AD600001010101010101010101010101010101D3 +:10AD700001010101010101010101010101010101C3 +:10AD800001010101010101010101010101010101B3 +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010183 +:10ADC0000101010101010101010101010101010173 +:10ADD0000101010101010101010101010101010163 +:10ADE0000101010101010101010101010101010153 +:10ADF0000101010101010101010101010101010143 +:10AE00000101010101010101010101010101010132 +:10AE10000101010101010101010101010101010122 +:10AE20000101010101010101010101010101010112 +:10AE30000101010101010101010101010101010102 +:10AE400001010101010101010101010101010101F2 +:10AE500001010101010101010101010101010101E2 +:10AE600001010101010101010101010101010101D2 +:10AE700001010101010101010101010101010101C2 +:10AE800001010101010101010101010101010101B2 +:10AE900001010101010101010101010101010101A2 +:10AEA0000101010101010101010101010101010192 +:10AEB0000101010101010101010101010101010182 +:10AEC0000101010101010101010101010101010172 +:10AED0000101010101010101010101010101010162 +:10AEE0000101010101010101010101010101010152 +:10AEF0000101010101010101010101010101010142 +:10AF00000101010101010101010101010101010131 +:10AF10000101010101010101010101010101010121 +:10AF20000101010101010101010101010101010111 +:10AF30000101010101010101010101010101010101 +:10AF400001010101010101010101010101010101F1 +:10AF500001010101010101010101010101010101E1 +:10AF600001010101010101010101010101010101D1 +:10AF700001010101010101010101010101010101C1 +:10AF800001010101010101010101010101010101B1 +:10AF900001010101010101010101010101010101A1 +:10AFA0000101010101010101010101010101010191 +:10AFB0000101010101010101010101010101010181 +:10AFC0000101010101010101010101010101010171 +:10AFD0000101010101010101010101010101010161 +:10AFE0000101010101010101010101010101010151 +:10AFF0000101010101010101010101010101010141 +:10B000000101010101010101010101010101010130 +:10B010000101010101010101010101010101010120 +:10B020000101010101010101010101010101010110 +:10B030000101010101010101010101010101010100 +:10B0400001010101010101010101010101010101F0 +:10B0500001010101010101010101010101010101E0 +:10B0600001010101010101010101010101010101D0 +:10B0700001010101010101010101010101010101C0 +:10B0800001010101010101010101010101010101B0 +:10B0900001010101010101010101010101010101A0 +:10B0A0000101010101010101010101010101010190 +:10B0B0000101010101010101010101010101010180 +:10B0C0000101010101010101010101010101010170 +:10B0D0000101010101010101010101010101010160 +:10B0E0000101010101010101010101010101010150 +:10B0F0000101010101010101010101010101010140 +:10B10000010101010101010101010101010101012F +:10B11000010101010101010101010101010101011F +:10B12000010101010101010101010101010101010F +:10B1300001010101010101010101010101010101FF +:10B1400001010101010101010101010101010101EF +:10B1500001010101010101010101010101010101DF +:10B1600001010101010101010101010101010101CF +:10B1700001010101010101010101010101010101BF +:10B1800001010101010101010101010101010101AF +:10B19000010101010101010101010101010101019F +:10B1A000010101010101010101010101010101018F +:10B1B000010101010101010101010101010101017F +:10B1C000010101010101010101010101010101016F +:10B1D000010101010101010101010101010101015F +:10B1E000010101010101010101010101010101014F +:10B1F000010101010101010101010101010101013F +:10B20000010101010101010101010101010101012E +:10B21000010101010101010101010101010101011E +:10B22000010101010101010101010101010101010E +:10B2300001010101010101010101010101010101FE +:10B2400001010101010101010101010101010101EE +:10B2500001010101010101010101010101010101DE +:10B2600001010101010101010101010101010101CE +:10B2700001010101010101010101010101010101BE +:10B2800001010101010101010101010101010101AE +:10B29000010101010101010101010101010101019E +:10B2A000010101010101010101010101010101018E +:10B2B000010101010101010101010101010101017E +:10B2C000010101010101010101010101010101016E +:10B2D000010101010101010101010101010101015E +:10B2E000010101010101010101010101010101014E +:10B2F000010101010101010101010101010101013E +:10B30000010101010101010101010101010101012D +:10B31000010101010101010101010101010101011D +:10B32000010101010101010101010101010101010D +:10B3300001010101010101010101010101010101FD +:10B3400001010101010101010101010101010101ED +:10B3500001010101010101010101010101010101DD +:10B3600001010101010101010101010101010101CD +:10B3700001010101010101010101010101010101BD +:10B3800001010101010101010101010101010101AD +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010101010101010101018D +:10B3B000010101010101010101010101010101017D +:10B3C000010101010101010101010101010101016D +:10B3D000010101010101010101010101010101015D +:10B3E000010101010101010101010101010101014D +:10B3F000010101010101010101010101010101013D +:10B40000010101010101010101010101010101012C +:10B41000010101010101010101010101010101011C +:10B42000010101010101010101010101010101010C +:10B4300001010101010101010101010101010101FC +:10B4400001010101010101010101010101010101EC +:10B4500001010101010101010101010101010101DC +:10B4600001010101010101010101010101010101CC +:10B4700001010101010101010101010101010101BC +:10B4800001010101010101010101010101010101AC +:10B49000010101010101010101010101010101019C +:10B4A000010101010101010101010101010101018C +:10B4B000010101010101010101010101010101017C +:10B4C000010101010101010101010101010101016C +:10B4D000010101010101010101010101010101015C +:10B4E000010101010101010101010101010101014C +:10B4F000010101010101010101010101010101013C +:10B50000010101010101010101010101010101012B +:10B51000010101010101010101010101010101011B +:10B52000010101010101010101010101010101010B +:10B5300001010101010101010101010101010101FB +:10B5400001010101010101010101010101010101EB +:10B5500001010101010101010101010101010101DB +:10B5600001010101010101010101010101010101CB +:10B5700001010101010101010101010101010101BB +:10B5800001010101010101010101010101010101AB +:10B59000010101010101010101010101010101019B +:10B5A000010101010101010101010101010101018B +:10B5B000010101010101010101010101010101017B +:10B5C000010101010101010101010101010101016B +:10B5D000010101010101010101010101010101015B +:10B5E000010101010101010101010101010101014B +:10B5F000010101010101010101010101010101013B +:10B60000010101010101010101010101010101012A +:10B61000010101010101010101010101010101011A +:10B62000010101010101010101010101010101010A +:10B6300001010101010101010101010101010101FA +:10B6400001010101010101010101010101010101EA +:10B6500001010101010101010101010101010101DA +:10B6600001010101010101010101010101010101CA +:10B6700001010101010101010101010101010101BA +:10B6800001010101010101010101010101010101AA +:10B69000010101010101010101010101010101019A +:10B6A000010101010101010101010101010101018A +:10B6B000010101010101010101010101010101017A +:10B6C000010101010101010101010101010101016A +:10B6D000010101010101010101010101010101015A +:10B6E000010101010101010101010101010101014A +:10B6F000010101010101010101010101010101013A +:10B700000101010101010101010101010101010129 +:10B710000101010101010101010101010101010119 +:10B720000101010101010101010101010101010109 +:10B7300001010101010101010101010101010101F9 +:10B7400001010101010101010101010101010101E9 +:10B7500001010101010101010101010101010101D9 +:10B7600001010101010101010101010101010101C9 +:10B7700001010101010101010101010101010101B9 +:10B7800001010101010101010101010101010101A9 +:10B790000101010101010101010101010101010199 +:10B7A0000101010101010101010101010101010189 +:10B7B0000101010101010101010101010101010179 +:10B7C0000101010101010101010101010101010169 +:10B7D0000101010101010101010101010101010159 +:10B7E0000101010101010101010101010101010149 +:10B7F0000101010101010101010101010101010139 +:10B800000101010101010101010101010101010128 +:10B810000101010101010101010101010101010118 +:10B820000101010101010101010101010101010108 +:10B8300001010101010101010101010101010101F8 +:10B8400001010101010101010101010101010101E8 +:10B8500001010101010101010101010101010101D8 +:10B8600001010101010101010101010101010101C8 +:10B8700001010101010101010101010101010101B8 +:10B8800001010101010101010101010101010101A8 +:10B890000101010101010101010101010101010198 +:10B8A0000101010101010101010101010101010188 +:10B8B0000101010101010101010101010101010178 +:10B8C0000101010101010101010101010101010168 +:10B8D0000101010101010101010101010101010158 +:10B8E0000101010101010101010101010101010148 +:10B8F0000101010101010101010101010101010138 +:10B900000101010101010101010101010101010127 +:10B910000101010101010101010101010101010117 +:10B920000101010101010101010101010101010107 +:10B9300001010101010101010101010101010101F7 +:10B9400001010101010101010101010101010101E7 +:10B9500001010101010101010101010101010101D7 +:10B9600001010101010101010101010101010101C7 +:10B9700001010101010101010101010101010101B7 +:10B9800001010101010101010101010101010101A7 +:10B990000101010101010101010101010101010197 +:10B9A0000101010101010101010101010101010187 +:10B9B0000101010101010101010101010101010177 +:10B9C0000101010101010101010101010101010167 +:10B9D0000101010101010101010101010101010157 +:10B9E0000101010101010101010101010101010147 +:10B9F0000101010101010101010101010101010137 +:10BA00000101010101010101010101010101010126 +:10BA10000101010101010101010101010101010116 +:10BA20000101010101010101010101010101010106 +:10BA300001010101010101010101010101010101F6 +:10BA400001010101010101010101010101010101E6 +:10BA500001010101010101010101010101010101D6 +:10BA600001010101010101010101010101010101C6 +:10BA700001010101010101010101010101010101B6 +:10BA800001010101010101010101010101010101A6 +:10BA90000101010101010101010101010101010196 +:10BAA0000101010101010101010101010101010186 +:10BAB0000101010101010101010101010101010176 +:10BAC0000101010101010101010101010101010166 +:10BAD0000101010101010101010101010101010156 +:10BAE0000101010101010101010101010101010146 +:10BAF0000101010101010101010101010101010136 +:10BB00000101010101010101010101010101010125 +:10BB10000101010101010101010101010101010115 +:10BB20000101010101010101010101010101010105 +:10BB300001010101010101010101010101010101F5 +:10BB400001010101010101010101010101010101E5 +:10BB500001010101010101010101010101010101D5 +:10BB600001010101010101010101010101010101C5 +:10BB700001010101010101010101010101010101B5 +:10BB800001010101010101010101010101010101A5 +:10BB90000101010101010101010101010101010195 +:10BBA0000101010101010101010101010101010185 +:10BBB0000101010101010101010101010101010175 +:10BBC0000101010101010101010101010101010165 +:10BBD0000101010101010101010101010101010155 +:10BBE0000101010101010101010101010101010145 +:10BBF0000101010101010101010101010101010135 +:10BC00000101010101010101010101010101010124 +:10BC10000101010101010101010101010101010114 +:10BC20000101010101010101010101010101010104 +:10BC300001010101010101010101010101010101F4 +:10BC400001010101010101010101010101010101E4 +:10BC500001010101010101010101010101010101D4 +:10BC600001010101010101010101010101010101C4 +:10BC700001010101010101010101010101010101B4 +:10BC800001010101010101010101010101010101A4 +:10BC90000101010101010101010101010101010194 +:10BCA0000101010101010101010101010101010184 +:10BCB0000101010101010101010101010101010174 +:10BCC0000101010101010101010101010101010164 +:10BCD0000101010101010101010101010101010154 +:10BCE0000101010101010101010101010101010144 +:10BCF0000101010101010101010101010101010134 +:10BD00000101010101010101010101010101010123 +:10BD10000101010101010101010101010101010113 +:10BD20000101010101010101010101010101010103 +:10BD300001010101010101010101010101010101F3 +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101010101010101010101B3 +:10BD800001010101010101010101010101010101A3 +:10BD90000101010101010101010101010101010193 +:10BDA0000101010101010101010101010101010183 +:10BDB0000101010101010101010101010101010173 +:10BDC0000101010101010101010101010101010163 +:10BDD0000101010101010101010101010101010153 +:10BDE0000101010101010101010101010101010143 +:10BDF000010101010101010100000000000000003B +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F0000000000000000000010101010101010137 +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101010101010101010101CE +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A000010101010101010101010101010101017E +:10C2B000010101010101010101010101010101016E +:10C2C000010101010101010101010101010101015E +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010101010101ED +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101010101010101010101CD +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010101010101010101017D +:10C3B000010101010101010101010101010101016D +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F0000101010101010101020202020202020225 +:10C40000020202020202020202020202020202020C +:10C4100002020202020202020202020202020202FC +:10C4200002020202020202020202020202020202EC +:10C4300002020202020202020202020202020202DC +:10C4400002020202020202020202020202020202CC +:10C4500002020202020202020202020202020202BC +:10C4600002020202020202020202020202020202AC +:10C47000020202020202020202020202020202029C +:10C48000020202020202020202020202020202028C +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B000020202020202020202020202020202025C +:10C4C000020202020202020202020202020202024C +:10C4D000020202020202020202020202020202023C +:10C4E000020202020202020202020202020202022C +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C5100002020202020202020202020202020202FB +:10C5200002020202020202020202020202020202EB +:10C5300002020202020202020202020202020202DB +:10C5400002020202020202020202020202020202CB +:10C5500002020202020202020202020202020202BB +:10C5600002020202020202020202020202020202AB +:10C57000020202020202020202020202020202029B +:10C58000020202020202020202020202020202028B +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020202025B +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000020202020202020202020202020202022B +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C6100002020202020202020202020202020202FA +:10C6200002020202020202020202020202020202EA +:10C6300002020202020202020202020202020202DA +:10C6400002020202020202020202020202020202CA +:10C6500002020202020202020202020202020202BA +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020202020202020202028A +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020202025A +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202023A +:10C6E000020202020202020202020202020202022A +:10C6F000020202020202020202020202020202021A +:10C700000202020202020202020202020202020209 +:10C7100002020202020202020202020202020202F9 +:10C7200002020202020202020202020202020202E9 +:10C7300002020202020202020202020202020202D9 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202020202020202020202020202B9 +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B0000202020202020202020202020202020259 +:10C7C0000202020202020202020202020202020249 +:10C7D0000202020202020202020202020202020239 +:10C7E0000202020202020202020202020202020229 +:10C7F0000202020202020202020202020202020219 +:10C800000202020202020202020202020202020208 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020202020202C8 +:10C8500002020202020202020202020202020202B8 +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B0000202020202020202020202020202020258 +:10C8C0000202020202020202020202020202020248 +:10C8D0000202020202020202020202020202020238 +:10C8E0000202020202020202020202020202020228 +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020202020202C7 +:10C9500002020202020202020202020202020202B7 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020202020257 +:10C9C0000202020202020202020202020202020247 +:10C9D0000202020202020202020202020202020237 +:10C9E0000202020202020202020202020202020227 +:10C9F0000202020202020202020202020202020217 +:10CA00000202020202020202020202020202020206 +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020233 +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202020202020202020202020213 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020202020252 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020232 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202020202020202020202020212 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020231 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202020202020202020202020211 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202020202020202020202020202020230 +:10D0E0000202020202020202020202020202020220 +:10D0F0000202020202020202020202020202020210 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D17000020202020202020202020202020202028F +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020202020202020202020202023F +:10D1D000020202020202020202020202020202022F +:10D1E000020202020202020202020202020202021F +:10D1F000020202020202020202020202020202020F +:10D2000002020202020202020202020202020202FE +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D000020202020202020202020202020202022E +:10D2E000020202020202020202020202020202021E +:10D2F000020202020202020202020202020202020E +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020202020202020202020202CD +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020202020202020202020202025D +:10D3B000020202020202020202020202020202024D +:10D3C000020202020202020202020202020202023D +:10D3D000020202020202020202020202020202022D +:10D3E000020202020202020202020202020202021D +:10D3F000020202020202020202020202020202020D +:10D4000002020202020202020202020202020202FC +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020202DC +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202020202020202025C +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020202020202020202023C +:10D4D000020202020202020202020202020202022C +:10D4E000020202020202020202020202020202021C +:10D4F000020202020202020202020202020202020C +:10D5000002020202020202020202020202020202FB +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020202020202020202020202CB +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A000020202020202020202020202020202025B +:10D5B000020202020202020202020202020202024B +:10D5C000020202020202020202020202020202023B +:10D5D000020202020202020202020202020202022B +:10D5E000020202020202020202020202020202021B +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B000020202020202020202020202020202024A +:10D6C000020202020202020202020202020202023A +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020202020202020202020239 +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C0000202020202020202020202020202020238 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202020202020237 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202020202020236 +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020202020202020202020216 +:10DAF0000202020202020202020202020202020206 +:10DB000002020202020202020202020202020202F5 +:10DB100002020202020202020202020202020202E5 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB0000202020202020202020202020202020245 +:10DBC0000202020202020202020202020202020235 +:10DBD0000202020202020202020202020202020225 +:10DBE0000202020202020202020202020202020215 +:10DBF0000202020202020202000000000000000015 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF00000000000000000009B0000000000000089 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010101010101010101010173 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE90000101010101010101010101010101010172 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101010101010101010101DF +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101010101010101010101AF +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101010101010101DC +:10E4300001010101010101010101010101010101CC +:10E4400001010101010101010101010101010101BC +:10E4500001010101010101010101010101010101AC +:10E46000010101010101010101010101010101019C +:10E47000010101010101010101010101010101018C +:10E48000010101010101010101010101010101017C +:10E49000010101010101010101010101010101016C +:10E4A000010101010101010101010101010101015C +:10E4B000010101010101010101010101010101014C +:10E4C000010101010101010101010101010101013C +:10E4D000010101010101010101010101010101012C +:10E4E000010101010101010101010101010101011C +:10E4F000010101010101010101010101010101010C +:10E5000001010101010101010101010101010101FB +:10E5100001010101010101010101010101010101EB +:10E5200001010101010101010101010101010101DB +:10E5300001010101010101010101010101010101CB +:10E5400001010101010101010101010101010101BB +:10E5500001010101010101010101010101010101AB +:10E56000010101010101010101010101010101019B +:10E57000010101010101010101010101010101018B +:10E58000010101010101010101010101010101017B +:10E59000010101010101010101010101010101016B +:10E5A000010101010101010101010101010101015B +:10E5B000010101010101010101010101010101014B +:10E5C000010101010101010101010101010101013B +:10E5D000010101010101010101010101010101012B +:10E5E000010101010101010101010101010101011B +:10E5F000010101010101010101010101010101010B +:10E6000001010101010101010101010101010101FA +:10E6100001010101010101010101010101010101EA +:10E6200001010101010101010101010101010101DA +:10E6300001010101010101010101010101010101CA +:10E6400001010101010101010101010101010101BA +:10E6500001010101010101010101010101010101AA +:10E66000010101010101010101010101010101019A +:10E67000010101010101010101010101010101018A +:10E68000010101010101010101010101010101017A +:10E69000010101010101010101010101010101016A +:10E6A000010101010101010101010101010101015A +:10E6B000010101010101010101010101010101014A +:10E6C000010101010101010101010101010101013A +:10E6D000010101010101010101010101010101012A +:10E6E000010101010101010101010101010101011A +:10E6F000010101010101010101010101010101010A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000000000000000000000037 +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000000000000000000000036 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000000000000000000000035 +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000000000000000000000034 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000000000000000000000000000037 +:10F9D0000000000000000000000000000000000027 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101010101010101010141 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD0000101010101010101010101010101010111 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:020000022000DC +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202020202020202020205 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020202025A +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A000020202020202020202020202020202021A +:1016B000020202020202020202020202020202020A +:1016C00002020202020202020202020202020202FA +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202020202020202020202DA +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:101720000202020202020202020202020202020299 +:101730000202020202020202020202020202020289 +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:101760000202020202020202020202020202020259 +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A0000202020202020202020202020202020219 +:1017B0000202020202020202020202020202020209 +:1017C00002020202020202020202020202020202F9 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202020202020202020202D9 +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020288 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A0000202020202020202020202020202020218 +:1018B0000202020202020202020202020202020208 +:1018C00002020202020202020202020202020202F8 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202020202020202020202D8 +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020202A7 +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020202020202020202020217 +:1019B0000202020202020202020202020202020207 +:1019C00002020202020202020202020202020202F7 +:1019D00002020202020202020202020202020202E7 +:1019E00002020202020202020202020202020202D7 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000202020202020202020202020202020216 +:101AB0000202020202020202020202020202020206 +:101AC00002020202020202020202020202020202F6 +:101AD00002020202020202020202020202020202E6 +:101AE00002020202020202020202020202020202D6 +:101AF00002020202020202020202020202020202C6 +:101B000002020202020202020202020202020202B5 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA0000202020202020202020202020202020215 +:101BB0000202020202020202020202020202020205 +:101BC00002020202020202020202020202020202F5 +:101BD00002020202020202020202020202020202E5 +:101BE00002020202020202020202020202020202D5 +:101BF00002020202020202020202020202020202C5 +:101C000002020202020202020202020202020202B4 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA0000202020202020202020202020202020214 +:101CB0000202020202020202020202020202020204 +:101CC00002020202020202020202020202020202F4 +:101CD00002020202020202020202020202020202E4 +:101CE00002020202020202020202020202020202D4 +:101CF00002020202020202020202020202020202C4 +:101D000002020202020202020202020202020202B3 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020202020203 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020202D3 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202020202 +:101EC00002020202020202020202020202020202F2 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020202D2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020202D0 +:1020F00002020202020202020202020202020202C0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00000000000000000000000000000000000FD +:1023E00000000000000000000000000000000000ED +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000000E8 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000000E6 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010184 +:102C40000101010101010101010101010101010174 +:102C50000101010101010101010101010101010164 +:102C60000101010101010101010101010101010154 +:102C70000101010101010101010101010101010144 +:102C80000101010101010101010101010101010134 +:102C90000101010101010101010101010101010124 +:102CA0000101010101010101010101010101010114 +:102CB0000101010101010101010101010101010104 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010173 +:102D50000101010101010101010101010101010163 +:102D60000101010101010101010101010101010153 +:102D70000101010101010101010101010101010143 +:102D80000101010101010101010101010101010133 +:102D90000101010101010101010101010101010123 +:102DA0000101010101010101010101010101010113 +:102DB0000101010101010101010101010101010103 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010132 +:102E90000101010101010101010101010101010122 +:102EA0000101010101010101010101010101010112 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010101D2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:10317000010101010101010101010101010101013F +:10318000010101010101010101010101010101012F +:10319000010101010101010101010101010101011F +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000010101010101010101010101010101014E +:10327000010101010101010101010101010101013E +:10328000010101010101010101010101010101012E +:10329000010101010101010101010101010101011E +:1032A000010101010101010101010101010101010E +:1032B00001010101010101010101010101010101FE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000010101010101010101010101010101011D +:1033A000010101010101010101010101010101010D +:1033B00001010101010101010101010101010101FD +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000010101010101010101010101010101017C +:10344000010101010101010101010101010101016C +:10345000010101010101010101010101010101015C +:10346000010101010101010101010101010101014C +:10347000010101010101010101010101010101013C +:10348000010101010101010101010101010101012C +:10349000010101010101010101010101010101011C +:1034A000010101010101010101010101010101010C +:1034B00001010101010101010101010101010101FC +:1034C00001010101010101010101010101010101EC +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000000CA +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000000000000000000000C9 +:1057E00000000000000000000000000000000000B9 +:1057F00000000000000000000000000000000000A9 +:105800000101010101010101010101010101010188 +:105810000101010101010101010101010101010178 +:105820000101010101010101010101010101010168 +:105830000101010101010101010101010101010158 +:105840000101010101010101010101010101010148 +:105850000101010101010101010101010101010138 +:105860000101010101010101010101010101010128 +:105870000101010101010101010101010101010118 +:105880000101010101010101010101010101010108 +:1058900001010101010101010101010101010101F8 +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101010101010101010101010101C8 +:1058D00001010101010101010101010101010101B8 +:1058E00001010101010101010101010101010101A8 +:1058F0000101010101010101010101010101010198 +:105900000101010101010101010101010101010187 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A40000202020202020202020202020202020236 +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002020202020202020202020202020202E6 +:105AA00002020202020202020202020202020202D6 +:105AB00002020202020202020202020202020202C6 +:105AC00002020202020202020202020202020202B6 +:105AD00002020202020202020202020202020202A6 +:105AE0000202020202020202020202020202020296 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020202020202020202020202020202E5 +:105BA00002020202020202020202020202020202D5 +:105BB00002020202020202020202020202020202C5 +:105BC00002020202020202020202020202020202B5 +:105BD00002020202020202020202020202020202A5 +:105BE0000202020202020202020202020202020295 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020202020202020202020202020202E4 +:105CA00002020202020202020202020202020202D4 +:105CB00002020202020202020202020202020202C4 +:105CC00002020202020202020202020202020202B4 +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202020202020202020294 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020202020202020202020202E3 +:105DA00002020202020202020202020202020202D3 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020202020202020202B3 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202020202020202020293 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020202B2 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202020202020202020292 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000000BA +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000000B9 +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800008F000000000000000101010101010101E1 +:107810000101010101010101010101010101010158 +:107820000101010101010101010101010101010148 +:107830000101010101010101010101010101010138 +:107840000101010101010101010101010101010128 +:107850000101010101010101010101010101010118 +:107860000101010101010101010101010101010108 +:1078700001010101010101010101010101010101F8 +:1078800001010101010101010101010101010101E8 +:1078900001010101010101010101010101010101D8 +:1078A00001010101010101010101010101010101C8 +:1078B00001010101010101010101010101010101B8 +:1078C00001010101010101010101010101010101A8 +:1078D0000101010101010101010101010101010198 +:1078E0000101010101010101010101010101010188 +:1078F0000101010101010101010101010101010178 +:107900000101010101010101010101010101010167 +:107910000101010101010101010101010101010157 +:107920000101010101010101010101010101010147 +:107930000101010101010101010101010101010137 +:107940000101010101010101010101010101010127 +:107950000101010101010101010101010101010117 +:107960000101010101010101010101010101010107 +:1079700001010101010101010101010101010101F7 +:1079800001010101010101010101010101010101E7 +:1079900001010101010101010101010101010101D7 +:1079A00001010101010101010101010101010101C7 +:1079B00001010101010101010101010101010101B7 +:1079C00001010101010101010101010101010101A7 +:1079D0000101010101010101010101010101010197 +:1079E0000101010101010101010101010101010187 +:1079F0000101010101010101010101010101010177 +:107A00000101010101010101010101010101010166 +:107A10000101010101010101010101010101010156 +:107A20000101010101010101010101010101010146 +:107A30000101010101010101010101010101010136 +:107A40000101010101010101010101010101010126 +:107A50000101010101010101010101010101010116 +:107A60000101010101010101010101010101010106 +:107A700001010101010101010101010101010101F6 +:107A800001010101010101010101010101010101E6 +:107A900001010101010101010101010101010101D6 +:107AA00001010101010101010101010101010101C6 +:107AB00001010101010101010101010101010101B6 +:107AC00001010101010101010101010101010101A6 +:107AD0000101010101010101010101010101010196 +:107AE0000101010101010101010101010101010186 +:107AF0000101010101010101010101010101010176 +:107B00000101010101010101010101010101010165 +:107B10000101010101010101010101010101010155 +:107B20000101010101010101010101010101010145 +:107B30000101010101010101010101010101010135 +:107B40000101010101010101010101010101010125 +:107B50000101010101010101010101010101010115 +:107B60000101010101010101010101010101010105 +:107B700001010101010101010101010101010101F5 +:107B800001010101010101010101010101010101E5 +:107B900001010101010101010101010101010101D5 +:107BA00001010101010101010101010101010101C5 +:107BB00001010101010101010101010101010101B5 +:107BC00001010101010101010101010101010101A5 +:107BD0000101010101010101010101010101010195 +:107BE0000101010101010101010101010101010185 +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101010101010101010134 +:107C40000101010101010101010101010101010124 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010101010101010101E4 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD0000101010101010101010101010101010194 +:107CE0000101010101010101010101010101010184 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010101010101010101010123 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010101010101010101E3 +:107D900001010101010101010101010101010101D3 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010101010101010101B3 +:107DC00001010101010101010101010101010101A3 +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:108100000101010101010101000000000000000067 +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:109200000000000000000000010101010101010156 +:10921000010101010101010101010101010101013E +:10922000010101010101010101010101010101012E +:10923000010101010101010101010101010101011E +:10924000010101010101010101010101010101010E +:1092500001010101010101010101010101010101FE +:1092600001010101010101010101010101010101EE +:1092700001010101010101010101010101010101DE +:1092800001010101010101010101010101010101CE +:1092900001010101010101010101010101010101BE +:1092A00001010101010101010101010101010101AE +:1092B000010101010101010101010101010101019E +:1092C000010101010101010101010101010101018E +:1092D000010101010101010101010101010101017E +:1092E000010101010101010101010101010101016E +:1092F000010101010101010101010101010101015E +:10930000010101010101010101010101010101014D +:10931000010101010101010101010101010101013D +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B0000010101010101010100000000000000004D +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000010101010101010148 +:10A010000101010101010101010101010101010130 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A200000101010101010101020202020202020236 +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202020E +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202027E +:10A2C000020202020202020202020202020202026E +:10A2D000020202020202020202020202020202025E +:10A2E000020202020202020202020202020202024E +:10A2F000020202020202020202020202020202023E +:10A30000020202020202020202020202020202022D +:10A31000020202020202020202020202020202021D +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202024D +:10A3F000020202020202020202020202020202023D +:10A40000020202020202020202020202020202022C +:10A41000020202020202020202020202020202021C +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202027C +:10A4C000020202020202020202020202020202026C +:10A4D000020202020202020202020202020202025C +:10A4E000020202020202020202020202020202024C +:10A4F000020202020202020202020202020202023C +:10A50000020202020202020202020202020202022B +:10A51000020202020202020202020202020202021B +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E000020202020202020202020202020202024B +:10A5F000020202020202020202020202020202023B +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E000020202020202020202020202020202024A +:10A6F000020202020202020202020202020202023A +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000202020202020202020202020202020239 +:10A800000202020202020202020202020202020228 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020202A8 +:10A890000202020202020202020202020202020298 +:10A8A0000202020202020202020202020202020288 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020202020202020202020B +:10B5200002020202020202020202020202020202FB +:10B5300002020202020202020202020202020202EB +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000020202020202020202020202020202024B +:10B5E000020202020202020202020202020202023B +:10B5F000020202020202020202020202020202022B +:10B60000020202020202020200000000000000002A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C100000000000000000000010101010101010127 +:10C11000010101010101010101010101010101010F +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010101010101DF +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A000010101010101010101010101010101017F +:10C1B000010101010101010101010101010101016F +:10C1C000010101010101010101010101010101015F +:10C1D000010101010101010101010101010101014F +:10C1E000010101010101010101010101010101013F +:10C1F000010101010101010101010101010101012F +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101010101010101010101CE +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A000010101010101010101010101010101017E +:10C2B000010101010101010101010101010101016E +:10C2C000010101010101010101010101010101015E +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010101010101ED +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101010101010101010101CD +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010101010101010101017D +:10C3B000010101010101010101010101010101016D +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101010C +:10C4200001010101010101010101010101010101FC +:10C4300001010101010101010101010101010101EC +:10C4400001010101010101010101010101010101DC +:10C4500001010101010101010101010101010101CC +:10C4600001010101010101010101010101010101BC +:10C4700001010101010101010101010101010101AC +:10C48000010101010101010101010101010101019C +:10C49000010101010101010101010101010101018C +:10C4A000010101010101010101010101010101017C +:10C4B000010101010101010101010101010101016C +:10C4C000010101010101010101010101010101015C +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010101010101010101013C +:10C4F000010101010101010101010101010101012C +:10C50000010101010101010101010101010101011B +:10C51000010101010101010101010101010101010B +:10C5200001010101010101010101010101010101FB +:10C5300001010101010101010101010101010101EB +:10C5400001010101010101010101010101010101DB +:10C5500001010101010101010101010101010101CB +:10C5600001010101010101010101010101010101BB +:10C5700001010101010101010101010101010101AB +:10C58000010101010101010101010101010101019B +:10C59000010101010101010101010101010101018B +:10C5A000010101010101010101010101010101017B +:10C5B000010101010101010101010101010101016B +:10C5C000010101010101010101010101010101015B +:10C5D000010101010101010101010101010101014B +:10C5E000010101010101010101010101010101013B +:10C5F000010101010101010101010101010101012B +:10C60000010101010101010101010101010101011A +:10C61000010101010101010101010101010101010A +:10C6200001010101010101010101010101010101FA +:10C6300001010101010101010101010101010101EA +:10C6400001010101010101010101010101010101DA +:10C6500001010101010101010101010101010101CA +:10C6600001010101010101010101010101010101BA +:10C6700001010101010101010101010101010101AA +:10C68000010101010101010101010101010101019A +:10C69000010101010101010101010101010101018A +:10C6A000010101010101010101010101010101017A +:10C6B000010101010101010101010101010101016A +:10C6C000010101010101010101010101010101015A +:10C6D000010101010101010101010101010101014A +:10C6E000010101010101010101010101010101013A +:10C6F000010101010101010101010101010101012A +:10C700000101010101010101010101010101010119 +:10C710000101010101010101010101010101010109 +:10C7200001010101010101010101010101010101F9 +:10C7300001010101010101010101010101010101E9 +:10C7400001010101010101010101010101010101D9 +:10C7500001010101010101010101010101010101C9 +:10C7600001010101010101010101010101010101B9 +:10C7700001010101010101010101010101010101A9 +:10C780000101010101010101010101010101010199 +:10C790000101010101010101010101010101010189 +:10C7A0000101010101010101010101010101010179 +:10C7B0000101010101010101010101010101010169 +:10C7C0000101010101010101010101010101010159 +:10C7D0000101010101010101010101010101010149 +:10C7E0000101010101010101010101010101010139 +:10C7F0000101010101010101010101010101010129 +:10C800000101010101010101010101010101010118 +:10C810000101010101010101010101010101010108 +:10C8200001010101010101010101010101010101F8 +:10C8300001010101010101010101010101010101E8 +:10C8400001010101010101010101010101010101D8 +:10C8500001010101010101010101010101010101C8 +:10C8600001010101010101010101010101010101B8 +:10C8700001010101010101010101010101010101A8 +:10C880000101010101010101010101010101010198 +:10C890000101010101010101010101010101010188 +:10C8A0000101010101010101010101010101010178 +:10C8B0000101010101010101010101010101010168 +:10C8C0000101010101010101010101010101010158 +:10C8D0000101010101010101010101010101010148 +:10C8E0000101010101010101010101010101010138 +:10C8F0000101010101010101010101010101010128 +:10C900000101010101010101010101010101010117 +:10C910000101010101010101010101010101010107 +:10C9200001010101010101010101010101010101F7 +:10C9300001010101010101010101010101010101E7 +:10C9400001010101010101010101010101010101D7 +:10C9500001010101010101010101010101010101C7 +:10C9600001010101010101010101010101010101B7 +:10C9700001010101010101010101010101010101A7 +:10C980000101010101010101010101010101010197 +:10C990000101010101010101010101010101010187 +:10C9A0000101010101010101010101010101010177 +:10C9B0000101010101010101010101010101010167 +:10C9C0000101010101010101010101010101010157 +:10C9D0000101010101010101010101010101010147 +:10C9E0000101010101010101010101010101010137 +:10C9F0000101010101010101010101010101010127 +:10CA0000010101010101010100000000000000001E +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000054 +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD10000000000000000000000000000000000013 +:10CD20000000000000000000000000000000000003 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D810000000000000000000000000000000000008 +:10D8200000000000000000000000000000000000F8 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000000000000000000F7 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB0000000000000000000001010101010101010D +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE0000101010101010101010101010101010125 +:10DBF0000101010101010101010101010101010115 +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010184 +:10DC90000101010101010101010101010101010174 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE0000101010101010101010101010101010124 +:10DCF0000101010101010101010101010101010114 +:10DD00000101010101010101010101010101010103 +:10DD100001010101010101010101010101010101F3 +:10DD200001010101010101010101010101010101E3 +:10DD300001010101010101010101010101010101D3 +:10DD400001010101010101010101010101010101C3 +:10DD500001010101010101010101010101010101B3 +:10DD600001010101010101010101010101010101A3 +:10DD70000101010101010101010101010101010193 +:10DD80000101010101010101010101010101010183 +:10DD90000101010101010101010101010101010173 +:10DDA0000101010101010101010101010101010163 +:10DDB0000101010101010101010101010101010153 +:10DDC0000101010101010101010101010101010143 +:10DDD0000101010101010101010101010101010133 +:10DDE0000101010101010101010101010101010123 +:10DDF0000101010101010101010101010101010113 +:10DE00000101010101010101010101010101010102 +:10DE100001010101010101010101010101010101F2 +:10DE200001010101010101010101010101010101E2 +:10DE300001010101010101010101010101010101D2 +:10DE400001010101010101010101010101010101C2 +:10DE500001010101010101010101010101010101B2 +:10DE600001010101010101010101010101010101A2 +:10DE70000101010101010101010101010101010192 +:10DE80000101010101010101010101010101010182 +:10DE90000101010101010101010101010101010172 +:10DEA0000101010101010101010101010101010162 +:10DEB0000101010101010101010101010101010152 +:10DEC0000101010101010101010101010101010142 +:10DED0000101010101010101010101010101010132 +:10DEE0000101010101010101010101010101010122 +:10DEF0000101010101010101010101010101010112 +:10DF00000101010101010101010101010101010101 +:10DF100001010101010101010101010101010101F1 +:10DF200001010101010101010101010101010101E1 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101010101010101010101DF +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101010101010101010101AF +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E400000101010101010101000000000000000004 +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E9000000000000000000000101010101010101FF +:10E9100001010101010101010101010101010101E7 +:10E9200001010101010101010101010101010101D7 +:10E9300001010101010101010101010101010101C7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010101010101010101010177 +:10E990000101010101010101010101010101010167 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010101010101010101D6 +:10EA300001010101010101010101010101010101C6 +:10EA400001010101010101010101010101010101B6 +:10EA500001010101010101010101010101010101A6 +:10EA60000101010101010101010101010101010196 +:10EA70000101010101010101010101010101010186 +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010101010101010101010166 +:10EAA0000101010101010101010101010101010156 +:10EAB0000101010101010101010101010101010146 +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101010202020202020202ED +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020203 +:10EDF00002020202020202020202020202020202F3 +:10EE000002020202020202020202020202020202E2 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202020202020202020202F2 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020202020202020202020202A1 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020202020202020221 +:10EFD0000202020202020202020202020202020211 +:10EFE0000202020202020202020202020202020201 +:10EFF00002020202020202020202020202020202F1 +:10F0000002020202020202020202020202020202E0 +:10F0100002020202020202020202020202020202D0 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020202020202020202020202B0 +:10F0400002020202020202020202020202020202A0 +:10F050000202020202020202020202020202020290 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020202020202020202020230 +:10F0C0000202020202020202020202020202020220 +:10F0D0000202020202020202020202020202020210 +:10F0E0000202020202020202020202020202020200 +:10F0F00002020202020202020202020202020202F0 +:10F1000002020202020202020202020202020202DF +:10F1100002020202020202020202020202020202CF +:10F1200002020202020202020202020202020202BF +:10F1300002020202020202020202020202020202AF +:10F14000020202020202020202020202020202029F +:10F15000020202020202020202020202020202028F +:10F16000020202020202020202020202020202027F +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A000020202020202020202020202020202023F +:10F1B000020202020202020202020202020202022F +:10F1C000020202020202020202020202020202021F +:10F1D000020202020202020202020202020202020F +:10F1E00002020202020202020202020202020202FF +:10F1F00002020202020202020202020202020202EF +:10F2000002020202020202020202020202020202DE +:10F2100002020202020202020202020202020202CE +:10F2200002020202020202020202020202020202BE +:10F2300002020202020202020202020202020202AE +:10F24000020202020202020202020202020202029E +:10F25000020202020202020202020202020202028E +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202020202020202023E +:10F2B000020202020202020202020202020202022E +:10F2C000020202020202020202020202020202021E +:10F2D000020202020202020202020202020202020E +:10F2E00002020202020202020202020202020202FE +:10F2F00002020202020202020202020202020202EE +:10F3000002020202020202020202020202020202DD +:10F3100002020202020202020202020202020202CD +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020202020202AD +:10F34000020202020202020202020202020202029D +:10F35000020202020202020202020202020202028D +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B000020202020202020202020202020202022D +:10F3C000020202020202020202020202020202021D +:10F3D000020202020202020202020202020202020D +:10F3E00002020202020202020202020202020202FD +:10F3F00002020202020202020202020202020202ED +:10F4000002020202020202020202020202020202DC +:10F4100002020202020202020202020202020202CC +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020202029C +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202020202027C +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C000020202020202020202020202020202021C +:10F4D000020202020202020202020202020202020C +:10F4E00002020202020202020202020202020202FC +:10F4F00002020202020202020202020202020202EC +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020202020202020202CB +:10F5200002020202020202020202020202020202BB +:10F5300002020202020202020202020202020202AB +:10F54000020202020202020202020202020202029B +:10F55000020202020202020202020202020202028B +:10F56000020202020202020202020202020202027B +:10F57000020202020202020202020202020202026B +:10F58000020202020202020202020202020202025B +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B000020202020202020202020202020202022B +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020202020202020202020B +:10F5E00002020202020202020202020202020202FB +:10F5F00002020202020202020202020202020202EB +:10F6000002020202020202020202020202020202DA +:10F6100002020202020202020202020202020202CA +:10F6200002020202020202020202020202020202BA +:10F6300002020202020202020202020202020202AA +:10F64000020202020202020202020202020202029A +:10F65000020202020202020202020202020202028A +:10F66000020202020202020202020202020202027A +:10F67000020202020202020202020202020202026A +:10F68000020202020202020202020202020202025A +:10F69000020202020202020202020202020202024A +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020202020202020202020A +:10F6E00002020202020202020202020202020202FA +:10F6F00002020202020202020202020202020202EA +:10F7000002020202020202020202020202020202D9 +:10F7100002020202020202020202020202020202C9 +:10F7200002020202020202020202020202020202B9 +:10F7300002020202020202020202020202020202A9 +:10F740000202020202020202020202020202020299 +:10F750000202020202020202020202020202020289 +:10F760000202020202020202020202020202020279 +:10F770000202020202020202020202020202020269 +:10F780000202020202020202020202020202020259 +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D0000202020202020202020202020202020209 +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020202020202020202020202020202D8 +:10F8100002020202020202020202020202020202C8 +:10F8200002020202020202020202020202020202B8 +:10F8300002020202020202020202020202020202A8 +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000202020202020202020202020202020208 +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020202020202020202020202020202D7 +:10F9100002020202020202020202020202020202C7 +:10F9200002020202020202020202020202020202B7 +:10F9300002020202020202020202020202020202A7 +:10F940000202020202020202020202020202020297 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020277 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000202020202020202020202020202020207 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020202020202020202020202020202D6 +:10FA100002020202020202020202020202020202C6 +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202020202020202020296 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020202020202020202C5 +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB60000202020202020202020202020202020275 +:10FB70000202020202020202020202020202020265 +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020202020202020202E5 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020202020202C4 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020202020202020202020274 +:10FC70000202020202020202020202020202020264 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020202020202020202E4 +:10FD000002020202020202020202020202020202D3 +:10FD100002020202020202020202020202020202C3 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020202020202020273 +:10FD70000202020202020202020202020202020263 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020202020202020202020243 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202020202020202020223 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020202020202020202020202F3 +:10FDF00002020202020202020202020202020202E3 +:10FE000002020202020202020202020202020202D2 +:10FE100002020202020202020202020202020202C2 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020202020202020272 +:10FE70000202020202020202020202020202020262 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202020202020242 +:10FEA0000202020202020202020202020202020232 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202020202020202F2 +:10FEF00002020202020202020202020202020202E2 +:10FF000002020202020202020000000000000000E1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:020000023000CC +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000000000000000000000CF +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:100700000000000000000000770000000000000072 +:1007100001010101010101010101010101010101C9 +:1007200001010101010101010101010101010101B9 +:1007300001010101010101010101010101010101A9 +:100740000101010101010101010101010101010199 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000101010101010101010101010101010169 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000101010101010101010101010101010139 +:1007B0000101010101010101010101010101010129 +:1007C0000101010101010101010101010101010119 +:1007D0000101010101010101010101010101010109 +:1007E00001010101010101010101010101010101F9 +:1007F00001010101010101010101010101010101E9 +:1008000001010101010101010101010101010101D8 +:1008100001010101010101010101010101010101C8 +:1008200001010101010101010101010101010101B8 +:1008300001010101010101010101010101010101A8 +:100840000101010101010101010101010101010198 +:100850000101010101010101010101010101010188 +:100860000101010101010101010101010101010178 +:100870000101010101010101010101010101010168 +:100880000101010101010101010101010101010158 +:100890000101010101010101010101010101010148 +:1008A0000101010101010101010101010101010138 +:1008B0000101010101010101010101010101010128 +:1008C0000101010101010101010101010101010118 +:1008D0000101010101010101010101010101010108 +:1008E00001010101010101010101010101010101F8 +:1008F00001010101010101010101010101010101E8 +:1009000001010101010101010101010101010101D7 +:1009100001010101010101010101010101010101C7 +:1009200001010101010101010101010101010101B7 +:1009300001010101010101010101010101010101A7 +:100940000101010101010101010101010101010197 +:100950000101010101010101010101010101010187 +:100960000101010101010101010101010101010177 +:100970000101010101010101010101010101010167 +:100980000101010101010101010101010101010157 +:100990000101010101010101010101010101010147 +:1009A0000101010101010101010101010101010137 +:1009B0000101010101010101010101010101010127 +:1009C0000101010101010101010101010101010117 +:1009D0000101010101010101010101010101010107 +:1009E00001010101010101010101010101010101F7 +:1009F00001010101010101010101010101010101E7 +:100A000001010101010101010101010101010101D6 +:100A100001010101010101010101010101010101C6 +:100A200001010101010101010101010101010101B6 +:100A300001010101010101010101010101010101A6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000101010101010101010101010101010154 +:100C90000101010101010101010101010101010144 +:100CA0000101010101010101010101010101010134 +:100CB0000101010101010101010101010101010124 +:100CC0000101010101010101010101010101010114 +:100CD0000101010101010101010101010101010104 +:100CE00001010101010101010101010101010101F4 +:100CF00001010101010101010101010101010101E4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00001010101010101010101010101010101E3 +:100E000001010101010101010101010101010101D2 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000000000000000000001C +:1014D000000000000000000000000000000000000C +:1014E00000000000000000000000000000000000FC +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000000000000000000019 +:1017D0000000000000000000000000000000000009 +:1017E00000000000000000000000000000000000F9 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000000000000000000000F8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000000000000000000000F5 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101010101010101010180 +:102050000101010101010101010101010101010170 +:102060000101010101010101010101010101010160 +:102070000101010101010101010101010101010150 +:102080000101010101010101010101010101010140 +:102090000101010101010101010101010101010130 +:1020A0000101010101010101010101010101010120 +:1020B0000101010101010101010101010101010110 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010101010101010101010101010101E0 +:1020F00001010101010101010101010101010101D0 +:1021000001010101010101010101010101010101BF +:1021100001010101010101010101010101010101AF +:10212000010101010101010101010101010101019F +:10213000010101010101010101010101010101018F +:10214000010101010101010101010101010101017F +:10215000010101010101010101010101010101016F +:10216000010101010101010101010101010101015F +:10217000010101010101010101010101010101014F +:10218000010101010101010101010101010101013F +:10219000010101010101010101010101010101012F +:1021A000010101010101010101010101010101011F +:1021B000010101010101010101010101010101010F +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00001010101010101010101010101010101CF +:1022000001010101010101010101010101010101BE +:1022100001010101010101010101010101010101AE +:10222000010101010101010101010101010101019E +:10223000010101010101010101010101010101018E +:10224000010101010101010101010101010101017E +:10225000010101010101010101010101010101016E +:10226000010101010101010101010101010101015E +:10227000010101010101010101010101010101014E +:10228000010101010101010101010101010101013E +:10229000010101010101010101010101010101012E +:1022A000010101010101010101010101010101011E +:1022B000010101010101010101010101010101010E +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00001010101010101010101010101010101CE +:1023000001010101010101010101010101010101BD +:1023100001010101010101010101010101010101AD +:10232000010101010101010101010101010101019D +:10233000010101010101010101010101010101018D +:10234000010101010101010101010101010101017D +:10235000010101010101010101010101010101016D +:10236000010101010101010101010101010101015D +:10237000010101010101010101010101010101014D +:10238000010101010101010101010101010101013D +:10239000010101010101010101010101010101012D +:1023A000010101010101010101010101010101011D +:1023B000010101010101010101010101010101010D +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00001010101010101010101010101010101CD +:1024000001010101010101010101010101010101BC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100001010101010101010101010101010101A8 +:102820000101010101010101010101010101010198 +:102830000101010101010101010101010101010188 +:102840000101010101010101010101010101010178 +:102850000101010101010101010101010101010168 +:102860000101010101010101010101010101010158 +:102870000101010101010101010101010101010148 +:102880000101010101010101010101010101010138 +:102890000101010101010101010101010101010128 +:1028A0000101010101010101010101010101010118 +:1028B0000101010101010101010101010101010108 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000101010101010101010101010101010197 +:102930000101010101010101010101010101010187 +:102940000101010101010101010101010101010177 +:102950000101010101010101010101010101010167 +:102960000101010101010101010101010101010157 +:102970000101010101010101010101010101010147 +:102980000101010101010101010101010101010137 +:102990000101010101010101010101010101010127 +:1029A0000101010101010101010101010101010117 +:1029B0000101010101010101010101010101010107 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020202020202020283 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020202020202020263 +:102D50000202020202020202020202020202020253 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00002020202020202020202020202020202E3 +:102DD00002020202020202020202020202020202D3 +:102DE00002020202020202020202020202020202C3 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020202020202020282 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020202020202020262 +:102E50000202020202020202020202020202020252 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020202020202020202E2 +:102ED00002020202020202020202020202020202D2 +:102EE00002020202020202020202020202020202C2 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020202020202E1 +:102FD00002020202020202020202020202020202D1 +:102FE00002020202020202020202020202020202C1 +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202020202020202020202D0 +:1030E00002020202020202020202020202020202C0 +:1030F00002020202020202020202020202020202B0 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00002020202020202020202020202020202BE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00002020202020202020202020202020202BD +:1033F00002020202020202020202020202020202AD +:10340000020202020202020202020202020202029C +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00002020202020202020202020202020202BC +:1034F00002020202020202020202020202020202AC +:10350000020202020202020202020202020202029B +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020202020202020202020202020202AB +:10360000020202020202020202020202020202029A +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020202020202020202020202020202AA +:103700000202020202020202020202020202020299 +:103710000202020202020202020202020202020289 +:103720000202020202020202020202020202020279 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020202020202020202020202020202A9 +:103800000202020202020202020202020202020298 +:103810000202020202020202020202020202020288 +:103820000202020202020202020202020202020278 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:103870000202020202020202020202020202020228 +:103880000202020202020202020202020202020218 +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:103900000202020202020202020202020202020297 +:103910000202020202020202020202020202020287 +:103920000202020202020202020202020202020277 +:103930000202020202020202020202020202020267 +:103940000202020202020202020202020202020257 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A00000202020202020202020202020202020296 +:103A10000202020202020202020202020202020286 +:103A20000202020202020202020202020202020276 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000010101010101010101010101010101018C +:10442000010101010101010101010101010101017C +:10443000010101010101010101010101010101016C +:10444000010101010101010101010101010101015C +:10445000010101010101010101010101010101014C +:10446000010101010101010101010101010101013C +:10447000010101010101010101010101010101012C +:10448000010101010101010101010101010101011C +:10449000010101010101010101010101010101010C +:1044A00001010101010101010101010101010101FC +:1044B00001010101010101010101010101010101EC +:1044C00001010101010101010101010101010101DC +:1044D00001010101010101010101010101010101CC +:1044E00001010101010101010101010101010101BC +:1044F00001010101010101010101010101010101AC +:10450000010101010101010101010101010101019B +:10451000010101010101010101010101010101018B +:10452000010101010101010101010101010101017B +:10453000010101010101010101010101010101016B +:10454000010101010101010101010101010101015B +:10455000010101010101010101010101010101014B +:10456000010101010101010101010101010101013B +:10457000010101010101010101010101010101012B +:10458000010101010101010101010101010101011B +:10459000010101010101010101010101010101010B +:1045A00001010101010101010101010101010101FB +:1045B00001010101010101010101010101010101EB +:1045C00001010101010101010101010101010101DB +:1045D00001010101010101010101010101010101CB +:1045E00001010101010101010101010101010101BB +:1045F00001010101010101010101010101010101AB +:10460000010101010101010101010101010101019A +:10461000010101010101010101010101010101018A +:10462000010101010101010101010101010101017A +:10463000010101010101010101010101010101016A +:10464000010101010101010101010101010101015A +:10465000010101010101010101010101010101014A +:10466000010101010101010101010101010101013A +:10467000010101010101010101010101010101012A +:10468000010101010101010101010101010101011A +:10469000010101010101010101010101010101010A +:1046A00001010101010101010101010101010101FA +:1046B00001010101010101010101010101010101EA +:1046C00001010101010101010101010101010101DA +:1046D00001010101010101010101010101010101CA +:1046E00001010101010101010101010101010101BA +:1046F00001010101010101010101010101010101AA +:104700000101010101010101010101010101010199 +:104710000101010101010101010101010101010189 +:104720000101010101010101010101010101010179 +:104730000101010101010101010101010101010169 +:104740000101010101010101010101010101010159 +:104750000101010101010101010101010101010149 +:104760000101010101010101010101010101010139 +:104770000101010101010101010101010101010129 +:104780000101010101010101010101010101010119 +:104790000101010101010101010101010101010109 +:1047A00001010101010101010101010101010101F9 +:1047B00001010101010101010101010101010101E9 +:1047C00001010101010101010101010101010101D9 +:1047D00001010101010101010101010101010101C9 +:1047E00001010101010101010101010101010101B9 +:1047F00001010101010101010101010101010101A9 +:104800000101010101010101010101010101010198 +:104810000101010101010101010101010101010188 +:104820000101010101010101010101010101010178 +:104830000101010101010101010101010101010168 +:104840000101010101010101010101010101010158 +:104850000101010101010101010101010101010148 +:104860000101010101010101010101010101010138 +:104870000101010101010101010101010101010128 +:104880000101010101010101010101010101010118 +:104890000101010101010101010101010101010108 +:1048A00001010101010101010101010101010101F8 +:1048B00001010101010101010101010101010101E8 +:1048C00001010101010101010101010101010101D8 +:1048D00001010101010101010101010101010101C8 +:1048E00001010101010101010101010101010101B8 +:1048F00001010101010101010101010101010101A8 +:104900000101010101010101010101010101010197 +:104910000101010101010101010101010101010187 +:104920000101010101010101010101010101010177 +:104930000101010101010101010101010101010167 +:104940000101010101010101010101010101010157 +:104950000101010101010101010101010101010147 +:104960000101010101010101010101010101010137 +:104970000101010101010101010101010101010127 +:104980000101010101010101010101010101010117 +:104990000101010101010101010101010101010107 +:1049A00001010101010101010101010101010101F7 +:1049B00001010101010101010101010101010101E7 +:1049C00001010101010101010101010101010101D7 +:1049D00001010101010101010101010101010101C7 +:1049E00001010101010101010101010101010101B7 +:1049F00001010101010101010101010101010101A7 +:104A00000101010101010101010101010101010196 +:104A10000101010101010101010101010101010186 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000000CA +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000000000000000000000C9 +:1057E00000000000000000000000000000000000B9 +:1057F00000000000000000000000000000000000A9 +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000000000000000000000C8 +:1058E00000000000000000000000000000000000B8 +:1058F00000000000000000000000000000000000A8 +:105900000000000000000000000000000000000097 +:105910000101010101010101010101010101010177 +:105920000101010101010101010101010101010167 +:105930000101010101010101010101010101010157 +:105940000101010101010101010101010101010147 +:105950000101010101010101010101010101010137 +:105960000101010101010101010101010101010127 +:105970000101010101010101010101010101010117 +:105980000101010101010101010101010101010107 +:1059900001010101010101010101010101010101F7 +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00001010101010101010101010101010101C7 +:1059D00001010101010101010101010101010101B7 +:1059E00001010101010101010101010101010101A7 +:1059F0000101010101010101010101010101010197 +:105A00000101010101010101010101010101010186 +:105A10000101010101010101010101010101010176 +:105A20000101010101010101010101010101010166 +:105A30000101010101010101010101010101010156 +:105A40000101010101010101010101010101010146 +:105A50000101010101010101010101010101010136 +:105A60000101010101010101010101010101010126 +:105A70000101010101010101010101010101010116 +:105A80000101010101010101010101010101010106 +:105A900001010101010101010101010101010101F6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00001010101010101010101010101010101C6 +:105AD00001010101010101010101010101010101B6 +:105AE00001010101010101010101010101010101A6 +:105AF0000101010101010101010101010101010196 +:105B00000101010101010101010101010101010185 +:105B10000101010101010101010101010101010175 +:105B20000101010101010101010101010101010165 +:105B30000101010101010101010101010101010155 +:105B40000101010101010101010101010101010145 +:105B50000101010101010101010101010101010135 +:105B60000101010101010101010101010101010125 +:105B70000101010101010101010101010101010115 +:105B80000101010101010101010101010101010105 +:105B900001010101010101010101010101010101F5 +:105BA00001010101010101010101010101010101E5 +:105BB00001010101010101010101010101010101D5 +:105BC00001010101010101010101010101010101C5 +:105BD00001010101010101010101010101010101B5 +:105BE00001010101010101010101010101010101A5 +:105BF0000101010101010101010101010101010195 +:105C00000101010101010101010101010101010184 +:105C10000101010101010101010101010101010174 +:105C20000101010101010101010101010101010164 +:105C30000101010101010101010101010101010154 +:105C40000101010101010101010101010101010144 +:105C50000101010101010101010101010101010134 +:105C60000101010101010101010101010101010124 +:105C70000101010101010101010101010101010114 +:105C80000101010101010101010101010101010104 +:105C900001010101010101010101010101010101F4 +:105CA00001010101010101010101010101010101E4 +:105CB00001010101010101010101010101010101D4 +:105CC00001010101010101010101010101010101C4 +:105CD00001010101010101010101010101010101B4 +:105CE00001010101010101010101010101010101A4 +:105CF0000101010101010101010101010101010194 +:105D00000101010101010101010101010101010183 +:105D10000101010101010101010101010101010173 +:105D20000101010101010101010101010101010163 +:105D30000101010101010101010101010101010153 +:105D40000101010101010101010101010101010143 +:105D50000101010101010101010101010101010133 +:105D60000101010101010101010101010101010123 +:105D70000101010101010101010101010101010113 +:105D80000101010101010101010101010101010103 +:105D900001010101010101010101010101010101F3 +:105DA00001010101010101010101010101010101E3 +:105DB00001010101010101010101010101010101D3 +:105DC00001010101010101010101010101010101C3 +:105DD00001010101010101010101010101010101B3 +:105DE00001010101010101010101010101010101A3 +:105DF0000101010101010101010101010101010193 +:105E00000101010101010101010101010101010182 +:105E10000101010101010101010101010101010172 +:105E20000101010101010101010101010101010162 +:105E30000101010101010101010101010101010152 +:105E40000101010101010101010101010101010142 +:105E50000101010101010101010101010101010132 +:105E60000101010101010101010101010101010122 +:105E70000101010101010101010101010101010112 +:105E80000101010101010101010101010101010102 +:105E900001010101010101010101010101010101F2 +:105EA00001010101010101010101010101010101E2 +:105EB00001010101010101010101010101010101D2 +:105EC00001010101010101010101010101010101C2 +:105ED00001010101010101010101010101010101B2 +:105EE00001010101010101010101010101010101A2 +:105EF0000101010101010101010101010101010192 +:105F00000101010101010101010101010101010181 +:105F10000101010101010101010101010101010171 +:105F20000101010101010101010101010101010161 +:105F30000101010101010101010101010101010151 +:105F40000101010101010101010101010101010141 +:105F50000101010101010101010101010101010131 +:105F60000101010101010101010101010101010121 +:105F70000101010101010101010101010101010111 +:105F80000101010101010101010101010101010101 +:105F900001010101010101010101010101010101F1 +:105FA00001010101010101010101010101010101E1 +:105FB00001010101010101010101010101010101D1 +:105FC00001010101010101010101010101010101C1 +:105FD00001010101010101010101010101010101B1 +:105FE00001010101010101010101010101010101A1 +:105FF0000101010101010101010101010101010191 +:106000000101010101010101010101010101010180 +:106010000101010101010101010101010101010170 +:106020000101010101010101010101010101010160 +:106030000101010101010101010101010101010150 +:106040000101010101010101010101010101010140 +:106050000101010101010101010101010101010130 +:106060000101010101010101010101010101010120 +:106070000101010101010101010101010101010110 +:106080000101010101010101010101010101010100 +:1060900001010101010101010101010101010101F0 +:1060A00001010101010101010101010101010101E0 +:1060B00001010101010101010101010101010101D0 +:1060C00001010101010101010101010101010101C0 +:1060D00001010101010101010101010101010101B0 +:1060E00001010101010101010101010101010101A0 +:1060F0000101010101010101010101010101010190 +:10610000010101010101010101010101010101017F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:10651000010101010101010101010101010101016B +:10652000010101010101010101010101010101015B +:10653000010101010101010101010101010101014B +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010101010101010101FB +:1065900001010101010101010101010101010101EB +:1065A00001010101010101010101010101010101DB +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101018B +:10660000010101010101010101010101010101017A +:10661000010101010101010101010101010101016A +:10662000010101010101010101010101010101015A +:10663000010101010101010101010101010101014A +:10664000010101010101010101010101010101013A +:10665000010101010101010101010101010101012A +:10666000010101010101010101010101010101011A +:10667000010101010101010101010101010101010A +:1066800001010101010101010101010101010101FA +:1066900001010101010101010101010101010101EA +:1066A00001010101010101010101010101010101DA +:1066B00001010101010101010101010101010101CA +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101010101010101010101AA +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101018A +:106700000101010101010101010101010101010179 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020202020202020202020202A8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000202020202020202020202020202020278 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000202020202020202020202020202020277 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000202020202020202020202020202020276 +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202020295 +:106BE0000202020202020202020202020202020285 +:106BF0000202020202020202020202020202020275 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000202020202020202020202020202020284 +:106CF0000202020202020202020202020202020274 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020202020202020202020202020283 +:106DF0000202020202020202020202020202020273 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020202020202020202020202020282 +:106EF0000202020202020202020202020202020272 +:106F00000202020202020202020202020202020261 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020202020202020202020202020281 +:106FF0000202020202020202020202020202020271 +:107000000202020202020202020202020202020260 +:107010000202020202020202020202020202020250 +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000000B8 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10007D000000000000000101010101010101DD +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010101010101010101B2 +:107EC00001010101010101010101010101010101A2 +:107ED0000101010101010101010101010101010192 +:107EE0000101010101010101010101010101010182 +:107EF0000101010101010101010101010101010172 +:107F00000101010101010101010101010101010161 +:107F10000101010101010101010101010101010151 +:107F20000101010101010101010101010101010141 +:107F30000101010101010101010101010101010131 +:107F40000101010101010101010101010101010121 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:108510000101010101010101000000000000000053 +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:109310000000000000000000010101010101010145 +:10932000010101010101010101010101010101012D +:10933000010101010101010101010101010101011D +:10934000010101010101010101010101010101010D +:1093500001010101010101010101010101010101FD +:1093600001010101010101010101010101010101ED +:1093700001010101010101010101010101010101DD +:1093800001010101010101010101010101010101CD +:1093900001010101010101010101010101010101BD +:1093A00001010101010101010101010101010101AD +:1093B000010101010101010101010101010101019D +:1093C000010101010101010101010101010101018D +:1093D000010101010101010101010101010101017D +:1093E000010101010101010101010101010101016D +:1093F000010101010101010101010101010101015D +:10940000010101010101010101010101010101014C +:10941000010101010101010101010101010101013C +:10942000010101010101010101010101010101012C +:10943000010101010101010101010101010101011C +:10944000010101010101010101010101010101010C +:1094500001010101010101010101010101010101FC +:1094600001010101010101010101010101010101EC +:1094700001010101010101010101010101010101DC +:1094800001010101010101010101010101010101CC +:1094900001010101010101010101010101010101BC +:1094A00001010101010101010101010101010101AC +:1094B000010101010101010101010101010101019C +:1094C000010101010101010101010101010101018C +:1094D000010101010101010101010101010101017C +:1094E000010101010101010101010101010101016C +:1094F000010101010101010101010101010101015C +:10950000010101010101010101010101010101014B +:10951000010101010101010101010101010101013B +:10952000010101010101010101010101010101012B +:10953000010101010101010101010101010101011B +:10954000010101010101010101010101010101010B +:1095500001010101010101010101010101010101FB +:1095600001010101010101010101010101010101EB +:1095700001010101010101010101010101010101DB +:1095800001010101010101010101010101010101CB +:1095900001010101010101010101010101010101BB +:1095A00001010101010101010101010101010101AB +:1095B000010101010101010101010101010101019B +:1095C000010101010101010101010101010101018B +:1095D000010101010101010101010101010101017B +:1095E000010101010101010101010101010101016B +:1095F000010101010101010101010101010101015B +:10960000010101010101010101010101010101014A +:10961000010101010101010101010101010101013A +:10962000010101010101010101010101010101012A +:10963000010101010101010101010101010101011A +:10964000010101010101010101010101010101010A +:1096500001010101010101010101010101010101FA +:1096600001010101010101010101010101010101EA +:1096700001010101010101010101010101010101DA +:1096800001010101010101010101010101010101CA +:1096900001010101010101010101010101010101BA +:1096A00001010101010101010101010101010101AA +:1096B000010101010101010101010101010101019A +:1096C000010101010101010101010101010101018A +:1096D000010101010101010101010101010101017A +:1096E000010101010101010101010101010101016A +:1096F000010101010101010101010101010101015A +:109700000101010101010101010101010101010149 +:109710000101010101010101010101010101010139 +:109720000101010101010101010101010101010129 +:109730000101010101010101010101010101010119 +:109740000101010101010101010101010101010109 +:1097500001010101010101010101010101010101F9 +:1097600001010101010101010101010101010101E9 +:1097700001010101010101010101010101010101D9 +:1097800001010101010101010101010101010101C9 +:1097900001010101010101010101010101010101B9 +:1097A00001010101010101010101010101010101A9 +:1097B0000101010101010101010101010101010199 +:1097C0000101010101010101010101010101010189 +:1097D0000101010101010101010101010101010179 +:1097E0000101010101010101010101010101010169 +:1097F0000101010101010101010101010101010159 +:109800000101010101010101010101010101010148 +:109810000101010101010101010101010101010138 +:109820000101010101010101010101010101010128 +:109830000101010101010101010101010101010118 +:109840000101010101010101010101010101010108 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B1000010101010101010100000000000000003D +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A210000000000000000000010101010101010136 +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A30000010101010101010101010101010101013D +:10A31000010101010101010101010101010101012D +:10A32000010101010101010101010101010101011D +:10A33000010101010101010101010101010101010D +:10A3400001010101010101010101010101010101FD +:10A3500001010101010101010101010101010101ED +:10A3600001010101010101010101010101010101DD +:10A3700001010101010101010101010101010101CD +:10A3800001010101010101010101010101010101BD +:10A3900001010101010101010101010101010101AD +:10A3A000010101010101010101010101010101019D +:10A3B000010101010101010101010101010101018D +:10A3C000010101010101010101010101010101017D +:10A3D000010101010101010101010101010101016D +:10A3E000010101010101010101010101010101015D +:10A3F000010101010101010101010101010101014D +:10A40000010101010101010101010101010101013C +:10A410000101010101010101020202020202020224 +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202027C +:10A4C000020202020202020202020202020202026C +:10A4D000020202020202020202020202020202025C +:10A4E000020202020202020202020202020202024C +:10A4F000020202020202020202020202020202023C +:10A50000020202020202020202020202020202022B +:10A51000020202020202020202020202020202021B +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E000020202020202020202020202020202024B +:10A5F000020202020202020202020202020202023B +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E000020202020202020202020202020202024A +:10A6F000020202020202020202020202020202023A +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000202020202020202020202020202020239 +:10A800000202020202020202020202020202020228 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020202A8 +:10A890000202020202020202020202020202020298 +:10A8A0000202020202020202020202020202020288 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020202A3 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020202020202020202020283 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020202020263 +:10ADD0000202020202020202020202020202020253 +:10ADE0000202020202020202020202020202020243 +:10ADF0000202020202020202020202020202020233 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000202020202020202020202020202020242 +:10AEF0000202020202020202020202020202020232 +:10AF00000202020202020202020202020202020221 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020202020202020202020281 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020202020261 +:10AFD0000202020202020202020202020202020251 +:10AFE0000202020202020202020202020202020241 +:10AFF0000202020202020202020202020202020231 +:10B000000202020202020202020202020202020220 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000202020202020202020202020202020250 +:10B0E0000202020202020202020202020202020240 +:10B0F0000202020202020202020202020202020230 +:10B10000020202020202020202020202020202021F +:10B11000020202020202020202020202020202020F +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000020202020202020202020202020202024F +:10B1E000020202020202020202020202020202023F +:10B1F000020202020202020202020202020202022F +:10B20000020202020202020202020202020202021E +:10B21000020202020202020202020202020202020E +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000020202020202020202020202020202024E +:10B2E000020202020202020202020202020202023E +:10B2F000020202020202020202020202020202022E +:10B30000020202020202020202020202020202021D +:10B31000020202020202020202020202020202020D +:10B3200002020202020202020202020202020202FD +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000020202020202020202020202020202024D +:10B3E000020202020202020202020202020202023D +:10B3F000020202020202020202020202020202022D +:10B40000020202020202020202020202020202021C +:10B41000020202020202020202020202020202020C +:10B4200002020202020202020202020202020202FC +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000020202020202020202020202020202024C +:10B4E000020202020202020202020202020202023C +:10B4F000020202020202020202020202020202022C +:10B50000020202020202020202020202020202021B +:10B51000020202020202020200000000000000001B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE1000000000000000000001010101010101011A +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101010101010101010101B2 +:10BE800001010101010101010101010101010101A2 +:10BE90000101010101010101010101010101010192 +:10BEA0000101010101010101010101010101010182 +:10BEB0000101010101010101010101010101010172 +:10BEC0000101010101010101010101010101010162 +:10BED0000101010101010101010101010101010152 +:10BEE0000101010101010101010101010101010142 +:10BEF0000101010101010101010101010101010132 +:10BF00000101010101010101010101010101010121 +:10BF10000101010101010101010101010101010111 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101010101010101010101B1 +:10BF800001010101010101010101010101010101A1 +:10BF90000101010101010101010101010101010191 +:10BFA0000101010101010101010101010101010181 +:10BFB0000101010101010101010101010101010171 +:10BFC0000101010101010101010101010101010161 +:10BFD0000101010101010101010101010101010151 +:10BFE0000101010101010101010101010101010141 +:10BFF0000101010101010101010101010101010131 +:10C000000101010101010101010101010101010120 +:10C010000101010101010101010101010101010110 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101010101010101010101B0 +:10C0800001010101010101010101010101010101A0 +:10C090000101010101010101010101010101010190 +:10C0A0000101010101010101010101010101010180 +:10C0B0000101010101010101010101010101010170 +:10C0C0000101010101010101010101010101010160 +:10C0D0000101010101010101010101010101010150 +:10C0E0000101010101010101010101010101010140 +:10C0F0000101010101010101010101010101010130 +:10C10000010101010101010101010101010101011F +:10C11000010101010101010101010101010101010F +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010101010101DF +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A000010101010101010101010101010101017F +:10C1B000010101010101010101010101010101016F +:10C1C000010101010101010101010101010101015F +:10C1D000010101010101010101010101010101014F +:10C1E000010101010101010101010101010101013F +:10C1F000010101010101010101010101010101012F +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101010101010101010101CE +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A000010101010101010101010101010101017E +:10C2B000010101010101010101010101010101016E +:10C2C000010101010101010101010101010101015E +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010101010101ED +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101010101010101010101CD +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010101010101010101017D +:10C3B000010101010101010101010101010101016D +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101010C +:10C4200001010101010101010101010101010101FC +:10C4300001010101010101010101010101010101EC +:10C4400001010101010101010101010101010101DC +:10C4500001010101010101010101010101010101CC +:10C4600001010101010101010101010101010101BC +:10C4700001010101010101010101010101010101AC +:10C48000010101010101010101010101010101019C +:10C49000010101010101010101010101010101018C +:10C4A000010101010101010101010101010101017C +:10C4B000010101010101010101010101010101016C +:10C4C000010101010101010101010101010101015C +:10C4D000010101010101010101010101010101014C +:10C4E000010101010101010101010101010101013C +:10C4F000010101010101010101010101010101012C +:10C50000010101010101010101010101010101011B +:10C510000101010101010101000000000000000013 +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000054 +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD10000000000000000000000000000000000013 +:10CD20000000000000000000000000000000000003 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D310000000000000000000010101010101010105 +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D4100001010101010101010101010101010101FC +:10D4200001010101010101010101010101010101EC +:10D4300001010101010101010101010101010101DC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101017C +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400001010101010101010101010101010101CA +:10D6500001010101010101010101010101010101BA +:10D6600001010101010101010101010101010101AA +:10D67000010101010101010101010101010101019A +:10D68000010101010101010101010101010101018A +:10D69000010101010101010101010101010101017A +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000010101010101010101010101010101014A +:10D6D000010101010101010101010101010101013A +:10D6E000010101010101010101010101010101012A +:10D6F000010101010101010101010101010101011A +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010101010101010101B9 +:10D7600001010101010101010101010101010101A9 +:10D770000101010101010101010101010101010199 +:10D780000101010101010101010101010101010189 +:10D790000101010101010101010101010101010179 +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000101010101010101010101010101010149 +:10D7D0000101010101010101010101010101010139 +:10D7E0000101010101010101010101010101010129 +:10D7F0000101010101010101010101010101010119 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010101010101010101A8 +:10D870000101010101010101010101010101010198 +:10D880000101010101010101010101010101010188 +:10D890000101010101010101010101010101010178 +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000101010101010101010101010101010148 +:10D8D0000101010101010101010101010101010138 +:10D8E0000101010101010101010101010101010128 +:10D8F0000101010101010101010101010101010118 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D990000101010101010101010101010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000101010101010101010101010101010147 +:10D9D0000101010101010101010101010101010137 +:10D9E0000101010101010101010101010101010127 +:10D9F0000101010101010101010101010101010117 +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB0000101010101010101010101010101010156 +:10DAC0000101010101010101010101010101010146 +:10DAD0000101010101010101010101010101010136 +:10DAE0000101010101010101010101010101010126 +:10DAF0000101010101010101010101010101010116 +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010000000000000000FD +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000000000000000000000000051 +:10DFD0000000000000000000000000000000000041 +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D0000000000000000000000000000000000040 +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000101010101010101F6 +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010202020202020202E4 +:10E4200002020202020202020202020202020202CC +:10E4300002020202020202020202020202020202BC +:10E4400002020202020202020202020202020202AC +:10E45000020202020202020202020202020202029C +:10E46000020202020202020202020202020202028C +:10E47000020202020202020202020202020202027C +:10E48000020202020202020202020202020202026C +:10E49000020202020202020202020202020202025C +:10E4A000020202020202020202020202020202024C +:10E4B000020202020202020202020202020202023C +:10E4C000020202020202020202020202020202022C +:10E4D000020202020202020202020202020202021C +:10E4E000020202020202020202020202020202020C +:10E4F00002020202020202020202020202020202FC +:10E5000002020202020202020202020202020202EB +:10E5100002020202020202020202020202020202DB +:10E5200002020202020202020202020202020202CB +:10E5300002020202020202020202020202020202BB +:10E5400002020202020202020202020202020202AB +:10E55000020202020202020202020202020202029B +:10E56000020202020202020202020202020202028B +:10E57000020202020202020202020202020202027B +:10E58000020202020202020202020202020202026B +:10E59000020202020202020202020202020202025B +:10E5A000020202020202020202020202020202024B +:10E5B000020202020202020202020202020202023B +:10E5C000020202020202020202020202020202022B +:10E5D000020202020202020202020202020202021B +:10E5E000020202020202020202020202020202020B +:10E5F00002020202020202020202020202020202FB +:10E6000002020202020202020202020202020202EA +:10E6100002020202020202020202020202020202DA +:10E6200002020202020202020202020202020202CA +:10E6300002020202020202020202020202020202BA +:10E6400002020202020202020202020202020202AA +:10E65000020202020202020202020202020202029A +:10E66000020202020202020202020202020202028A +:10E67000020202020202020202020202020202027A +:10E68000020202020202020202020202020202026A +:10E69000020202020202020202020202020202025A +:10E6A000020202020202020202020202020202024A +:10E6B000020202020202020202020202020202023A +:10E6C000020202020202020202020202020202022A +:10E6D000020202020202020202020202020202021A +:10E6E000020202020202020202020202020202020A +:10E6F00002020202020202020202020202020202FA +:10E7000002020202020202020202020202020202E9 +:10E7100002020202020202020202020202020202D9 +:10E7200002020202020202020202020202020202C9 +:10E7300002020202020202020202020202020202B9 +:10E7400002020202020202020202020202020202A9 +:10E750000202020202020202020202020202020299 +:10E760000202020202020202020202020202020289 +:10E770000202020202020202020202020202020279 +:10E780000202020202020202020202020202020269 +:10E790000202020202020202020202020202020259 +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000202020202020202020202020202020229 +:10E7D0000202020202020202020202020202020219 +:10E7E0000202020202020202020202020202020209 +:10E7F00002020202020202020202020202020202F9 +:10E8000002020202020202020202020202020202E8 +:10E8100002020202020202020202020202020202D8 +:10E8200002020202020202020202020202020202C8 +:10E8300002020202020202020202020202020202B8 +:10E8400002020202020202020202020202020202A8 +:10E850000202020202020202020202020202020298 +:10E860000202020202020202020202020202020288 +:10E870000202020202020202020202020202020278 +:10E880000202020202020202020202020202020268 +:10E890000202020202020202020202020202020258 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C0000202020202020202020202020202020228 +:10E8D0000202020202020202020202020202020218 +:10E8E0000202020202020202020202020202020208 +:10E8F00002020202020202020202020202020202F8 +:10E9000002020202020202020202020202020202E7 +:10E9100002020202020202020202020202020202D7 +:10E9200002020202020202020202020202020202C7 +:10E9300002020202020202020202020202020202B7 +:10E9400002020202020202020202020202020202A7 +:10E950000202020202020202020202020202020297 +:10E960000202020202020202020202020202020287 +:10E970000202020202020202020202020202020277 +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C0000202020202020202020202020202020227 +:10E9D0000202020202020202020202020202020217 +:10E9E0000202020202020202020202020202020207 +:10E9F00002020202020202020202020202020202F7 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020202020202020202020202020202C6 +:10EA300002020202020202020202020202020202B6 +:10EA400002020202020202020202020202020202A6 +:10EA50000202020202020202020202020202020296 +:10EA60000202020202020202020202020202020286 +:10EA70000202020202020202020202020202020276 +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202020202020202020202020202020226 +:10EAD0000202020202020202020202020202020216 +:10EAE0000202020202020202020202020202020206 +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202020202020202020202020202C5 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020202020202020202020202A5 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000202020202020202020202020202020275 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020202020202020202020202020225 +:10EBD0000202020202020202020202020202020215 +:10EBE0000202020202020202020202020202020205 +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202020202020202020202020202C4 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020202020202020202020202A4 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020202020202020202020224 +:10ECD0000202020202020202020202020202020214 +:10ECE0000202020202020202020202020202020204 +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202020202020202020202020202C3 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020202020202020202020202A3 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020202020202020223 +:10EDD0000202020202020202020202020202020213 +:10EDE0000202020202020202020202020202020203 +:10EDF00002020202020202020202020202020202F3 +:10EE000002020202020202020202020202020202E2 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020202020202020202020202A2 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020202020202020222 +:10EED0000202020202020202020202020202020212 +:10EEE0000202020202020202020202020202020202 +:10EEF00002020202020202020202020202020202F2 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020202020202020202020202A1 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020202020202020221 +:10EFD0000202020202020202020202020202020211 +:10EFE0000202020202020202020202020202020201 +:10EFF00002020202020202020202020202020202F1 +:10F0000002020202020202020202020202020202E0 +:10F0100002020202020202020202020202020202D0 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020202020202020202020202B0 +:10F0400002020202020202020202020202020202A0 +:10F050000202020202020202020202020202020290 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020202020202020202020230 +:10F0C0000202020202020202020202020202020220 +:10F0D0000202020202020202020202020202020210 +:10F0E0000202020202020202020202020202020200 +:10F0F00002020202020202020202020202020202F0 +:10F1000002020202020202020202020202020202DF +:10F1100002020202020202020202020202020202CF +:10F1200002020202020202020202020202020202BF +:10F1300002020202020202020202020202020202AF +:10F14000020202020202020202020202020202029F +:10F15000020202020202020202020202020202028F +:10F16000020202020202020202020202020202027F +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A000020202020202020202020202020202023F +:10F1B000020202020202020202020202020202022F +:10F1C000020202020202020202020202020202021F +:10F1D000020202020202020202020202020202020F +:10F1E00002020202020202020202020202020202FF +:10F1F00002020202020202020202020202020202EF +:10F2000002020202020202020202020202020202DE +:10F2100002020202020202020202020202020202CE +:10F2200002020202020202020202020202020202BE +:10F2300002020202020202020202020202020202AE +:10F24000020202020202020202020202020202029E +:10F25000020202020202020202020202020202028E +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202020202020202023E +:10F2B000020202020202020202020202020202022E +:10F2C000020202020202020202020202020202021E +:10F2D000020202020202020202020202020202020E +:10F2E00002020202020202020202020202020202FE +:10F2F00002020202020202020202020202020202EE +:10F3000002020202020202020202020202020202DD +:10F3100002020202020202020202020202020202CD +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020202020202AD +:10F34000020202020202020202020202020202029D +:10F35000020202020202020202020202020202028D +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B000020202020202020202020202020202022D +:10F3C000020202020202020202020202020202021D +:10F3D000020202020202020202020202020202020D +:10F3E00002020202020202020202020202020202FD +:10F3F00002020202020202020202020202020202ED +:10F4000002020202020202020202020202020202DC +:10F4100002020202020202020202020202020202CC +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020202029C +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202020202027C +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C000020202020202020202020202020202021C +:10F4D000020202020202020202020202020202020C +:10F4E00002020202020202020202020202020202FC +:10F4F00002020202020202020202020202020202EC +:10F5000002020202020202020202020202020202DB +:10F5100002020202020202020000000000000000DB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000000000000000000000000000037 +:10F9D0000000000000000000000000000000000027 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000000000000000000000000000000000000F6 +:10FA100000000000000000000000000000000000E6 +:10FA200000000000000000000000000000000000D6 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC0000000000000000000000000000000000036 +:10FAD0000000000000000000000000000000000026 +:10FAE0000000000000000000000000000000000016 +:10FAF0000000000000000000000000000000000006 +:10FB000000000000000000000000000000000000F5 +:10FB10000000000000000000710000000000000074 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC50000101010101010101010101010101010194 +:10FC60000101010101010101010101010101010184 +:10FC70000101010101010101010101010101010174 +:10FC80000101010101010101010101010101010164 +:10FC90000101010101010101010101010101010154 +:10FCA0000101010101010101010101010101010144 +:10FCB0000101010101010101010101010101010134 +:10FCC0000101010101010101010101010101010124 +:10FCD0000101010101010101010101010101010114 +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD70000101010101010101010101010101010173 +:10FD80000101010101010101010101010101010163 +:10FD90000101010101010101010101010101010153 +:10FDA0000101010101010101010101010101010143 +:10FDB0000101010101010101010101010101010133 +:10FDC0000101010101010101010101010101010123 +:10FDD0000101010101010101010101010101010113 +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE80000101010101010101010101010101010162 +:10FE90000101010101010101010101010101010152 +:10FEA0000101010101010101010101010101010142 +:10FEB0000101010101010101010101010101010132 +:10FEC0000101010101010101010101010101010122 +:10FED0000101010101010101010101010101010112 +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101010101010101010141 +:10FFB0000101010101010101010101010101010131 +:10FFC0000101010101010101010101010101010121 +:10FFD0000101010101010101010101010101010111 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:020000024000BC +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000000000000000000000E4 +:100C100000000000000000000000000000000000D4 +:100C200000000000000000000000000000000000C4 +:100C300000000000000000000000000000000000B4 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000000E3 +:100D100000000000000000000000000000000000D3 +:100D200000000000000000000000000000000000C3 +:100D300000000000000000000000000000000000B3 +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000000000000000000000073 +:100D80000000000000000000000000000000000063 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000000000000000000023 +:100DD0000000000000000000000000000000000013 +:100DE0000000000000000000000000000000000003 +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000101010101010101010101010101010190 +:101050000101010101010101010101010101010180 +:101060000101010101010101010101010101010170 +:101070000101010101010101010101010101010160 +:101080000101010101010101010101010101010150 +:101090000101010101010101010101010101010140 +:1010A0000101010101010101010101010101010130 +:1010B0000101010101010101010101010101010120 +:1010C0000101010101010101010101010101010110 +:1010D0000101010101010101010101010101010100 +:1010E00001010101010101010101010101010101F0 +:1010F00001010101010101010101010101010101E0 +:1011000001010101010101010101010101010101CF +:1011100001010101010101010101010101010101BF +:1011200001010101010101010101010101010101AF +:10113000010101010101010101010101010101019F +:10114000010101010101010101010101010101018F +:10115000010101010101010101010101010101017F +:10116000010101010101010101010101010101016F +:10117000010101010101010101010101010101015F +:10118000010101010101010101010101010101014F +:10119000010101010101010101010101010101013F +:1011A000010101010101010101010101010101012F +:1011B000010101010101010101010101010101011F +:1011C000010101010101010101010101010101010F +:1011D00001010101010101010101010101010101FF +:1011E00001010101010101010101010101010101EF +:1011F00001010101010101010101010101010101DF +:1012000001010101010101010101010101010101CE +:1012100001010101010101010101010101010101BE +:1012200001010101010101010101010101010101AE +:10123000010101010101010101010101010101019E +:10124000010101010101010101010101010101018E +:10125000010101010101010101010101010101017E +:10126000010101010101010101010101010101016E +:10127000010101010101010101010101010101015E +:10128000010101010101010101010101010101014E +:10129000010101010101010101010101010101013E +:1012A000010101010101010101010101010101012E +:1012B000010101010101010101010101010101011E +:1012C000010101010101010101010101010101010E +:1012D00001010101010101010101010101010101FE +:1012E00001010101010101010101010101010101EE +:1012F00001010101010101010101010101010101DE +:1013000001010101010101010101010101010101CD +:1013100001010101010101010101010101010101BD +:1013200001010101010101010101010101010101AD +:10133000010101010101010101010101010101019D +:10134000010101010101010101010101010101018D +:10135000010101010101010101010101010101017D +:10136000010101010101010101010101010101016D +:10137000010101010101010101010101010101015D +:10138000010101010101010101010101010101014D +:10139000010101010101010101010101010101013D +:1013A000010101010101010101010101010101012D +:1013B000010101010101010101010101010101011D +:1013C000010101010101010101010101010101010D +:1013D00001010101010101010101010101010101FD +:1013E00001010101010101010101010101010101ED +:1013F00001010101010101010101010101010101DD +:1014000001010101010101010101010101010101CC +:1014100001010101010101010101010101010101BC +:1014200001010101010101010101010101010101AC +:10143000010101010101010101010101010101019C +:10144000010101010101010101010101010101018C +:10145000010101010101010101010101010101017C +:10146000010101010101010101010101010101016C +:10147000010101010101010101010101010101015C +:10148000010101010101010101010101010101014C +:10149000010101010101010101010101010101013C +:1014A000010101010101010101010101010101012C +:1014B000010101010101010101010101010101011C +:1014C000010101010101010101010101010101010C +:1014D00001010101010101010101010101010101FC +:1014E00001010101010101010101010101010101EC +:1014F00001010101010101010101010101010101DC +:1015000001010101010101010101010101010101CB +:1015100001010101010101010101010101010101BB +:1015200001010101010101010101010101010101AB +:10153000010101010101010101010101010101019B +:10154000010101010101010101010101010101018B +:10155000010101010101010101010101010101017B +:10156000010101010101010101010101010101016B +:10157000010101010101010101010101010101015B +:10158000010101010101010101010101010101014B +:10159000010101010101010101010101010101013B +:1015A000010101010101010101010101010101012B +:1015B000010101010101010101010101010101011B +:1015C000010101010101010101010101010101010B +:1015D00001010101010101010101010101010101FB +:1015E00001010101010101010101010101010101EB +:1015F00001010101010101010101010101010101DB +:1016000001010101010101010101010101010101CA +:1016100001010101010101010101010101010101BA +:1016200001010101010101010101010101010101AA +:10163000010101010101010101010101010101019A +:10164000010101010101010101010101010101018A +:10165000010101010101010101010101010101017A +:10166000010101010101010101010101010101016A +:10167000010101010101010101010101010101015A +:10168000010101010101010101010101010101014A +:10169000010101010101010101010101010101013A +:1016A000010101010101010101010101010101012A +:1016B000010101010101010101010101010101011A +:1016C000010101010101010101010101010101010A +:1016D00001010101010101010101010101010101FA +:1016E00001010101010101010101010101010101EA +:1016F00001010101010101010101010101010101DA +:1017000001010101010101010101010101010101C9 +:1017100001010101010101010101010101010101B9 +:1017200001010101010101010101010101010101A9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000000000000000000000F8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000000000000000000000F5 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200001010101010101010101010101010101A4 +:101C30000101010101010101010101010101010194 +:101C40000101010101010101010101010101010184 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020202020203 +:101DC00002020202020202020202020202020202F3 +:101DD00002020202020202020202020202020202E3 +:101DE00002020202020202020202020202020202D3 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202020202 +:101EC00002020202020202020202020202020202F2 +:101ED00002020202020202020202020202020202E2 +:101EE00002020202020202020202020202020202D2 +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC00002020202020202020202020202020202F1 +:101FD00002020202020202020202020202020202E1 +:101FE00002020202020202020202020202020202D1 +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C00002020202020202020202020202020202F0 +:1020D00002020202020202020202020202020202E0 +:1020E00002020202020202020202020202020202D0 +:1020F00002020202020202020202020202020202C0 +:1021000002020202020202020202020202020202AF +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020202020202020202020F +:1021B00002020202020202020202020202020202FF +:1021C00002020202020202020202020202020202EF +:1021D00002020202020202020202020202020202DF +:1021E00002020202020202020202020202020202CF +:1021F00002020202020202020202020202020202BF +:1022000002020202020202020202020202020202AE +:10221000020202020202020202020202020202029E +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A000020202020202020202020202020202020E +:1022B00002020202020202020202020202020202FE +:1022C00002020202020202020202020202020202EE +:1022D00002020202020202020202020202020202DE +:1022E00002020202020202020202020202020202CE +:1022F00002020202020202020202020202020202BE +:1023000002020202020202020202020202020202AD +:10231000020202020202020202020202020202029D +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A000020202020202020202020202020202020D +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020202020202ED +:1023D00002020202020202020202020202020202DD +:1023E00002020202020202020202020202020202CD +:1023F00002020202020202020202020202020202BD +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202020202020202020202DC +:1024E00002020202020202020202020202020202CC +:1024F00002020202020202020202020202020202BC +:1025000002020202020202020202020202020202AB +:10251000020202020202020202020202020202029B +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C00002020202020202020202020202020202EB +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020202CB +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020202020202029A +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00002020202020202020202020202020202EA +:1026D00002020202020202020202020202020202DA +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:102710000202020202020202020202020202020299 +:102720000202020202020202020202020202020289 +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00002020202020202020202020202020202E9 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000202020202020202020202020202020288 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C00002020202020202020202020202020202E8 +:1028D00002020202020202020202020202020202D8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:102920000202020202020202020202020202020287 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00002020202020202020202020202020202E7 +:1029D00002020202020202020202020202020202D7 +:1029E00002020202020202020202020202020202C7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020202020202020296 +:102A20000202020202020202020202020202020286 +:102A30000202020202020202020202020202020276 +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00002020202020202020202020202020202E6 +:102AD00002020202020202020202020202020202D6 +:102AE00002020202020202020202020202020202C6 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020202020285 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00002020202020202020202020202020202E5 +:102BD00002020202020202020202020202020202D5 +:102BE00002020202020202020202020202020202C5 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020202020202020284 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020202020202020264 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00002020202020202020202020202020202E4 +:102CD00002020202020202020202020202020202D4 +:102CE00002020202020202020202020202020202C4 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000000E1 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000000FF +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000000FE +:1032D00000000000000000000000000000000000EE +:1032E00000000000000000000000000000000000DE +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000000FD +:1033D00000000000000000000000000000000000ED +:1033E00000000000000000000000000000000000DD +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000000EC +:1034E00000000000000000000000000000000000DC +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101014A +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A000010101010101010101010101010101010A +:1036B00001010101010101010101010101010101FA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010101F8 +:1038C00001010101010101010101010101010101E8 +:1038D00001010101010101010101010101010101D8 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010101010101010101010167 +:103950000101010101010101010101010101010157 +:103960000101010101010101010101010101010147 +:103970000101010101010101010101010101010137 +:103980000101010101010101010101010101010127 +:103990000101010101010101010101010101010117 +:1039A0000101010101010101010101010101010107 +:1039B00001010101010101010101010101010101F7 +:1039C00001010101010101010101010101010101E7 +:1039D00001010101010101010101010101010101D7 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000101010101010101010101010101010176 +:103A40000101010101010101010101010101010166 +:103A50000101010101010101010101010101010156 +:103A60000101010101010101010101010101010146 +:103A70000101010101010101010101010101010136 +:103A80000101010101010101010101010101010126 +:103A90000101010101010101010101010101010116 +:103AA0000101010101010101010101010101010106 +:103AB00001010101010101010101010101010101F6 +:103AC00001010101010101010101010101010101E6 +:103AD00001010101010101010101010101010101D6 +:103AE00001010101010101010101010101010101C6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000101010101010101010101010101010135 +:103B80000101010101010101010101010101010125 +:103B90000101010101010101010101010101010115 +:103BA0000101010101010101010101010101010105 +:103BB00001010101010101010101010101010101F5 +:103BC00001010101010101010101010101010101E5 +:103BD00001010101010101010101010101010101D5 +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000101010101010101010101010101010176 +:104A30000101010101010101010101010101010166 +:104A40000101010101010101010101010101010156 +:104A50000101010101010101010101010101010146 +:104A60000101010101010101010101010101010136 +:104A70000101010101010101010101010101010126 +:104A80000101010101010101010101010101010116 +:104A90000101010101010101010101010101010106 +:104AA00001010101010101010101010101010101F6 +:104AB00001010101010101010101010101010101E6 +:104AC00001010101010101010101010101010101D6 +:104AD00001010101010101010101010101010101C6 +:104AE00001010101010101010101010101010101B6 +:104AF00001010101010101010101010101010101A6 +:104B00000101010101010101010101010101010195 +:104B10000101010101010101010101010101010185 +:104B20000101010101010101010101010101010175 +:104B30000101010101010101010101010101010165 +:104B40000101010101010101010101010101010155 +:104B50000101010101010101010101010101010145 +:104B60000101010101010101010101010101010135 +:104B70000101010101010101010101010101010125 +:104B80000101010101010101010101010101010115 +:104B90000101010101010101010101010101010105 +:104BA00001010101010101010101010101010101F5 +:104BB00001010101010101010101010101010101E5 +:104BC00001010101010101010101010101010101D5 +:104BD00001010101010101010101010101010101C5 +:104BE00001010101010101010101010101010101B5 +:104BF00001010101010101010101010101010101A5 +:104C00000101010101010101010101010101010194 +:104C10000101010101010101010101010101010184 +:104C20000101010101010101010101010101010174 +:104C30000101010101010101010101010101010164 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000010101010101010101010101010101016A +:10563000010101010101010101010101010101015A +:10564000010101010101010101010101010101014A +:10565000010101010101010101010101010101013A +:10566000010101010101010101010101010101012A +:10567000010101010101010101010101010101011A +:10568000010101010101010101010101010101010A +:1056900001010101010101010101010101010101FA +:1056A00001010101010101010101010101010101EA +:1056B00001010101010101010101010101010101DA +:1056C00001010101010101010101010101010101CA +:1056D00001010101010101010101010101010101BA +:1056E00001010101010101010101010101010101AA +:1056F000010101010101010101010101010101019A +:105700000101010101010101010101010101010189 +:105710000101010101010101010101010101010179 +:105720000202020202020202020202020202020259 +:105730000202020202020202020202020202020249 +:105740000202020202020202020202020202020239 +:105750000202020202020202020202020202020229 +:105760000202020202020202020202020202020219 +:105770000202020202020202020202020202020209 +:1057800002020202020202020202020202020202F9 +:1057900002020202020202020202020202020202E9 +:1057A00002020202020202020202020202020202D9 +:1057B00002020202020202020202020202020202C9 +:1057C00002020202020202020202020202020202B9 +:1057D00002020202020202020202020202020202A9 +:1057E0000202020202020202020202020202020299 +:1057F0000202020202020202020202020202020289 +:105800000202020202020202020202020202020278 +:105810000202020202020202020202020202020268 +:105820000202020202020202020202020202020258 +:105830000202020202020202020202020202020248 +:105840000202020202020202020202020202020238 +:105850000202020202020202020202020202020228 +:105860000202020202020202020202020202020218 +:105870000202020202020202020202020202020208 +:1058800002020202020202020202020202020202F8 +:1058900002020202020202020202020202020202E8 +:1058A00002020202020202020202020202020202D8 +:1058B00002020202020202020202020202020202C8 +:1058C00002020202020202020202020202020202B8 +:1058D00002020202020202020202020202020202A8 +:1058E0000202020202020202020202020202020298 +:1058F0000202020202020202020202020202020288 +:105900000202020202020202020202020202020277 +:105910000202020202020202020202020202020267 +:105920000202020202020202020202020202020257 +:105930000202020202020202020202020202020247 +:105940000202020202020202020202020202020237 +:105950000202020202020202020202020202020227 +:105960000202020202020202020202020202020217 +:105970000202020202020202020202020202020207 +:1059800002020202020202020202020202020202F7 +:1059900002020202020202020202020202020202E7 +:1059A00002020202020202020202020202020202D7 +:1059B00002020202020202020202020202020202C7 +:1059C00002020202020202020202020202020202B7 +:1059D00002020202020202020202020202020202A7 +:1059E0000202020202020202020202020202020297 +:1059F0000202020202020202020202020202020287 +:105A00000202020202020202020202020202020276 +:105A10000202020202020202020202020202020266 +:105A20000202020202020202020202020202020256 +:105A30000202020202020202020202020202020246 +:105A40000202020202020202020202020202020236 +:105A50000202020202020202020202020202020226 +:105A60000202020202020202020202020202020216 +:105A70000202020202020202020202020202020206 +:105A800002020202020202020202020202020202F6 +:105A900002020202020202020202020202020202E6 +:105AA00002020202020202020202020202020202D6 +:105AB00002020202020202020202020202020202C6 +:105AC00002020202020202020202020202020202B6 +:105AD00002020202020202020202020202020202A6 +:105AE0000202020202020202020202020202020296 +:105AF0000202020202020202020202020202020286 +:105B00000202020202020202020202020202020275 +:105B10000202020202020202020202020202020265 +:105B20000202020202020202020202020202020255 +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B50000202020202020202020202020202020225 +:105B60000202020202020202020202020202020215 +:105B70000202020202020202020202020202020205 +:105B800002020202020202020202020202020202F5 +:105B900002020202020202020202020202020202E5 +:105BA00002020202020202020202020202020202D5 +:105BB00002020202020202020202020202020202C5 +:105BC00002020202020202020202020202020202B5 +:105BD00002020202020202020202020202020202A5 +:105BE0000202020202020202020202020202020295 +:105BF0000202020202020202020202020202020285 +:105C00000202020202020202020202020202020274 +:105C10000202020202020202020202020202020264 +:105C20000202020202020202020202020202020254 +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C50000202020202020202020202020202020224 +:105C60000202020202020202020202020202020214 +:105C70000202020202020202020202020202020204 +:105C800002020202020202020202020202020202F4 +:105C900002020202020202020202020202020202E4 +:105CA00002020202020202020202020202020202D4 +:105CB00002020202020202020202020202020202C4 +:105CC00002020202020202020202020202020202B4 +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202020202020202020294 +:105CF0000202020202020202020202020202020284 +:105D00000202020202020202020202020202020273 +:105D10000202020202020202020202020202020263 +:105D20000202020202020202020202020202020253 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202020202020202020202020223 +:105D60000202020202020202020202020202020213 +:105D70000202020202020202020202020202020203 +:105D800002020202020202020202020202020202F3 +:105D900002020202020202020202020202020202E3 +:105DA00002020202020202020202020202020202D3 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020202020202020202B3 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202020202020202020293 +:105DF0000202020202020202020202020202020283 +:105E00000202020202020202020202020202020272 +:105E10000202020202020202020202020202020262 +:105E20000202020202020202020202020202020252 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020202020202020222 +:105E60000202020202020202020202020202020212 +:105E70000202020202020202020202020202020202 +:105E800002020202020202020202020202020202F2 +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020202B2 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202020202020202020292 +:105EF0000202020202020202020202020202020282 +:105F00000202020202020202020202020202020271 +:105F10000202020202020202020202020202020261 +:105F20000202020202020202020202020202020251 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202020202020202020202020202020201 +:105F800002020202020202020202020202020202F1 +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202020202020202020291 +:105FF0000202020202020202020202020202020281 +:106000000202020202020202020202020202020270 +:106010000202020202020202020202020202020260 +:106020000202020202020202020202020202020250 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020202020202020200 +:1060800002020202020202020202020202020202F0 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202020202020202020290 +:1060F0000202020202020202020202020202020280 +:10610000020202020202020202020202020202026F +:10611000020202020202020202020202020202025F +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020202020202020202EF +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202020202020202020202020202025E +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020202020202020202EE +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020202020202020202ED +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000099 +:106800000000000000000000000000000000000088 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000038 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000000B8 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000098 +:106900000000000000000000000000000000000087 +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000000000000000000B7 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000097 +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000000B6 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000096 +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000035 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C200073000000000000000101010101010101E9 +:106C30000101010101010101010101010101010144 +:106C40000101010101010101010101010101010134 +:106C50000101010101010101010101010101010124 +:106C60000101010101010101010101010101010114 +:106C70000101010101010101010101010101010104 +:106C800001010101010101010101010101010101F4 +:106C900001010101010101010101010101010101E4 +:106CA00001010101010101010101010101010101D4 +:106CB00001010101010101010101010101010101C4 +:106CC00001010101010101010101010101010101B4 +:106CD00001010101010101010101010101010101A4 +:106CE0000101010101010101010101010101010194 +:106CF0000101010101010101010101010101010184 +:106D00000101010101010101010101010101010173 +:106D10000101010101010101010101010101010163 +:106D20000101010101010101010101010101010153 +:106D30000101010101010101010101010101010143 +:106D40000101010101010101010101010101010133 +:106D50000101010101010101010101010101010123 +:106D60000101010101010101010101010101010113 +:106D70000101010101010101010101010101010103 +:106D800001010101010101010101010101010101F3 +:106D900001010101010101010101010101010101E3 +:106DA00001010101010101010101010101010101D3 +:106DB00001010101010101010101010101010101C3 +:106DC00001010101010101010101010101010101B3 +:106DD00001010101010101010101010101010101A3 +:106DE0000101010101010101010101010101010193 +:106DF0000101010101010101010101010101010183 +:106E00000101010101010101010101010101010172 +:106E10000101010101010101010101010101010162 +:106E20000101010101010101010101010101010152 +:106E30000101010101010101010101010101010142 +:106E40000101010101010101010101010101010132 +:106E50000101010101010101010101010101010122 +:106E60000101010101010101010101010101010112 +:106E70000101010101010101010101010101010102 +:106E800001010101010101010101010101010101F2 +:106E900001010101010101010101010101010101E2 +:106EA00001010101010101010101010101010101D2 +:106EB00001010101010101010101010101010101C2 +:106EC00001010101010101010101010101010101B2 +:106ED00001010101010101010101010101010101A2 +:106EE0000101010101010101010101010101010192 +:106EF0000101010101010101010101010101010182 +:106F00000101010101010101010101010101010171 +:106F10000101010101010101010101010101010161 +:106F20000101010101010101010101010101010151 +:106F30000101010101010101010101010101010141 +:106F40000101010101010101010101010101010131 +:106F50000101010101010101010101010101010121 +:106F60000101010101010101010101010101010111 +:106F70000101010101010101010101010101010101 +:106F800001010101010101010101010101010101F1 +:106F900001010101010101010101010101010101E1 +:106FA00001010101010101010101010101010101D1 +:106FB00001010101010101010101010101010101C1 +:106FC00001010101010101010101010101010101B1 +:106FD00001010101010101010101010101010101A1 +:106FE0000101010101010101010101010101010191 +:106FF0000101010101010101010101010101010181 +:107000000101010101010101010101010101010170 +:107010000101010101010101010101010101010160 +:107020000101010101010101010101010101010150 +:107030000101010101010101010101010101010140 +:107040000101010101010101010101010101010130 +:107050000101010101010101010101010101010120 +:107060000101010101010101010101010101010110 +:107070000101010101010101010101010101010100 +:1070800001010101010101010101010101010101F0 +:1070900001010101010101010101010101010101E0 +:1070A00001010101010101010101010101010101D0 +:1070B00001010101010101010101010101010101C0 +:1070C00001010101010101010101010101010101B0 +:1070D00001010101010101010101010101010101A0 +:1070E0000101010101010101010101010101010190 +:1070F0000101010101010101010101010101010180 +:10710000010101010101010101010101010101016F +:10711000010101010101010101010101010101015F +:10712000010101010101010101010101010101014F +:10713000010101010101010101010101010101013F +:10714000010101010101010101010101010101012F +:10715000010101010101010101010101010101011F +:10716000010101010101010101010101010101010F +:1071700001010101010101010101010101010101FF +:1071800001010101010101010101010101010101EF +:1071900001010101010101010101010101010101DF +:1071A00001010101010101010101010101010101CF +:1071B00001010101010101010101010101010101BF +:1071C00001010101010101010101010101010101AF +:1071D000010101010101010101010101010101019F +:1071E000010101010101010101010101010101018F +:1071F000010101010101010101010101010101017F +:10720000010101010101010101010101010101016E +:10721000010101010101010101010101010101015E +:10722000010101010101010101010101010101014E +:10723000010101010101010101010101010101013E +:10724000010101010101010101010101010101012E +:10725000010101010101010101010101010101011E +:10726000010101010101010101010101010101010E +:1072700001010101010101010101010101010101FE +:1072800001010101010101010101010101010101EE +:1072900001010101010101010101010101010101DE +:1072A00001010101010101010101010101010101CE +:1072B00001010101010101010101010101010101BE +:1072C00001010101010101010101010101010101AE +:1072D000010101010101010101010101010101019E +:1072E000010101010101010101010101010101018E +:1072F000010101010101010101010101010101017E +:10730000010101010101010101010101010101016D +:10731000010101010101010101010101010101015D +:107320000101010101010101000000000000000055 +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000000BA +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000000B9 +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000000B8 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:108220000000000000000000010101010101010146 +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:10853000010101010101010101010101010101012B +:10854000010101010101010101010101010101011B +:10855000010101010101010101010101010101010B +:1085600001010101010101010101010101010101FB +:1085700001010101010101010101010101010101EB +:1085800001010101010101010101010101010101DB +:1085900001010101010101010101010101010101CB +:1085A00001010101010101010101010101010101BB +:1085B00001010101010101010101010101010101AB +:1085C000010101010101010101010101010101019B +:1085D000010101010101010101010101010101018B +:1085E000010101010101010101010101010101017B +:1085F000010101010101010101010101010101016B +:10860000010101010101010101010101010101015A +:10861000010101010101010101010101010101014A +:10862000010101010101010101010101010101013A +:10863000010101010101010101010101010101012A +:10864000010101010101010101010101010101011A +:10865000010101010101010101010101010101010A +:1086600001010101010101010101010101010101FA +:1086700001010101010101010101010101010101EA +:1086800001010101010101010101010101010101DA +:1086900001010101010101010101010101010101CA +:1086A00001010101010101010101010101010101BA +:1086B00001010101010101010101010101010101AA +:1086C000010101010101010101010101010101019A +:1086D000010101010101010101010101010101018A +:1086E000010101010101010101010101010101017A +:1086F000010101010101010101010101010101016A +:108700000101010101010101010101010101010159 +:108710000101010101010101010101010101010149 +:108720000101010101010101010101010101010139 +:108730000101010101010101010101010101010129 +:108740000101010101010101010101010101010119 +:108750000101010101010101010101010101010109 +:1087600001010101010101010101010101010101F9 +:1087700001010101010101010101010101010101E9 +:1087800001010101010101010101010101010101D9 +:1087900001010101010101010101010101010101C9 +:1087A00001010101010101010101010101010101B9 +:1087B00001010101010101010101010101010101A9 +:1087C0000101010101010101010101010101010199 +:1087D0000101010101010101010101010101010189 +:1087E0000101010101010101010101010101010179 +:1087F0000101010101010101010101010101010169 +:108800000101010101010101010101010101010158 +:108810000101010101010101010101010101010148 +:108820000101010101010101010101010101010138 +:108830000101010101010101010101010101010128 +:108840000101010101010101010101010101010118 +:108850000101010101010101010101010101010108 +:1088600001010101010101010101010101010101F8 +:1088700001010101010101010101010101010101E8 +:1088800001010101010101010101010101010101D8 +:1088900001010101010101010101010101010101C8 +:1088A00001010101010101010101010101010101B8 +:1088B00001010101010101010101010101010101A8 +:1088C0000101010101010101010101010101010198 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101010178 +:1088F0000101010101010101010101010101010168 +:108900000101010101010101010101010101010157 +:108910000101010101010101010101010101010147 +:10892000010101010101010100000000000000003F +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D2000000000000000000001010101010101013B +:108D30000101010101010101010101010101010123 +:108D40000101010101010101010101010101010113 +:108D50000101010101010101010101010101010103 +:108D600001010101010101010101010101010101F3 +:108D700001010101010101010101010101010101E3 +:108D800001010101010101010101010101010101D3 +:108D900001010101010101010101010101010101C3 +:108DA00001010101010101010101010101010101B3 +:108DB00001010101010101010101010101010101A3 +:108DC0000101010101010101010101010101010193 +:108DD0000101010101010101010101010101010183 +:108DE0000101010101010101010101010101010173 +:108DF0000101010101010101010101010101010163 +:108E00000101010101010101010101010101010152 +:108E10000101010101010101010101010101010142 +:108E20000101010101010101010101010101010132 +:108E30000101010101010101010101010101010122 +:108E40000101010101010101010101010101010112 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010101010101010101010101010101D2 +:108E900001010101010101010101010101010101C2 +:108EA00001010101010101010101010101010101B2 +:108EB00001010101010101010101010101010101A2 +:108EC0000101010101010101010101010101010192 +:108ED0000101010101010101010101010101010182 +:108EE0000101010101010101010101010101010172 +:108EF0000101010101010101010101010101010162 +:108F00000101010101010101010101010101010151 +:108F10000101010101010101010101010101010141 +:108F20000101010101010101020202020202020229 +:108F30000202020202020202020202020202020211 +:108F40000202020202020202020202020202020201 +:108F500002020202020202020202020202020202F1 +:108F600002020202020202020202020202020202E1 +:108F700002020202020202020202020202020202D1 +:108F800002020202020202020202020202020202C1 +:108F900002020202020202020202020202020202B1 +:108FA00002020202020202020202020202020202A1 +:108FB0000202020202020202020202020202020291 +:108FC0000202020202020202020202020202020281 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202020202020261 +:108FF0000202020202020202020202020202020251 +:109000000202020202020202020202020202020240 +:109010000202020202020202020202020202020230 +:109020000202020202020202020202020202020220 +:109030000202020202020202020202020202020210 +:109040000202020202020202020202020202020200 +:1090500002020202020202020202020202020202F0 +:1090600002020202020202020202020202020202E0 +:1090700002020202020202020202020202020202D0 +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020202020202020202B0 +:1090A00002020202020202020202020202020202A0 +:1090B0000202020202020202020202020202020290 +:1090C0000202020202020202020202020202020280 +:1090D0000202020202020202020202020202020270 +:1090E0000202020202020202020202020202020260 +:1090F0000202020202020202020202020202020250 +:10910000020202020202020202020202020202023F +:10911000020202020202020202020202020202022F +:10912000020202020202020202020202020202021F +:10913000020202020202020202020202020202020F +:1091400002020202020202020202020202020202FF +:1091500002020202020202020202020202020202EF +:1091600002020202020202020202020202020202DF +:1091700002020202020202020202020202020202CF +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D000020202020202020202020202020202026F +:1091E000020202020202020202020202020202025F +:1091F000020202020202020202020202020202024F +:10920000020202020202020202020202020202023E +:10921000020202020202020202020202020202022E +:10922000020202020202020202020202020202021E +:10923000020202020202020202020202020202020E +:1092400002020202020202020202020202020202FE +:1092500002020202020202020202020202020202EE +:1092600002020202020202020202020202020202DE +:1092700002020202020202020202020202020202CE +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202020202025E +:1092F000020202020202020202020202020202024E +:10930000020202020202020202020202020202023D +:10931000020202020202020202020202020202022D +:10932000020202020202020202020202020202021D +:10933000020202020202020202020202020202020D +:1093400002020202020202020202020202020202FD +:1093500002020202020202020202020202020202ED +:1093600002020202020202020202020202020202DD +:1093700002020202020202020202020202020202CD +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202029D +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202020202025D +:1093F000020202020202020202020202020202024D +:10940000020202020202020202020202020202023C +:10941000020202020202020202020202020202022C +:10942000020202020202020202020202020202021C +:10943000020202020202020202020202020202020C +:1094400002020202020202020202020202020202FC +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202020202020202DC +:1094700002020202020202020202020202020202CC +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020202AC +:1094A000020202020202020202020202020202029C +:1094B000020202020202020202020202020202028C +:1094C000020202020202020202020202020202027C +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202020202020202020202024C +:10950000020202020202020202020202020202023B +:10951000020202020202020202020202020202022B +:10952000020202020202020202020202020202021B +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202020202DB +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020202AB +:1095A000020202020202020202020202020202029B +:1095B000020202020202020202020202020202028B +:1095C000020202020202020202020202020202027B +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202020202020202020202024B +:10960000020202020202020202020202020202023A +:10961000020202020202020202020202020202022A +:10962000020202020202020202020202020202021A +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202020202029A +:1096B000020202020202020202020202020202028A +:1096C000020202020202020202020202020202027A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202020202020202020202024A +:109700000202020202020202020202020202020239 +:109710000202020202020202020202020202020229 +:109720000202020202020202020202020202020219 +:109730000202020202020202020202020202020209 +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A0000202020202020202020202020202020299 +:1097B0000202020202020202020202020202020289 +:1097C0000202020202020202020202020202020279 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202020202020202020238 +:109810000202020202020202020202020202020228 +:109820000202020202020202020202020202020218 +:109830000202020202020202020202020202020208 +:1098400002020202020202020202020202020202F8 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020202020298 +:1098B0000202020202020202020202020202020288 +:1098C0000202020202020202020202020202020278 +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202020202020202020237 +:109910000202020202020202020202020202020227 +:109920000202020202020202020202020202020217 +:109930000202020202020202020202020202020207 +:1099400002020202020202020202020202020202F7 +:1099500002020202020202020202020202020202E7 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B0000202020202020202020202020202020287 +:1099C0000202020202020202020202020202020277 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202020202020202020226 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020202020202020206 +:109A400002020202020202020202020202020202F6 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020202020202020202B6 +:109A900002020202020202020202020202020202A6 +:109AA0000202020202020202020202020202020296 +:109AB0000202020202020202020202020202020286 +:109AC0000202020202020202020202020202020276 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202020202020202020225 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202020202020202020202020202E5 +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020202A5 +:109BA0000202020202020202020202020202020295 +:109BB0000202020202020202020202020202020285 +:109BC0000202020202020202020202020202020275 +:109BD0000202020202020202020202020202020265 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020202020202020202020202020202E4 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020202020202020202B4 +:109C900002020202020202020202020202020202A4 +:109CA0000202020202020202020202020202020294 +:109CB0000202020202020202020202020202020284 +:109CC0000202020202020202020202020202020274 +:109CD0000202020202020202020202020202020264 +:109CE0000202020202020202020202020202020254 +:109CF0000202020202020202020202020202020244 +:109D00000202020202020202020202020202020233 +:109D10000202020202020202020202020202020223 +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020202020202020202020202020202E3 +:109D600002020202020202020202020202020202D3 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020202020202020202B3 +:109D900002020202020202020202020202020202A3 +:109DA0000202020202020202020202020202020293 +:109DB0000202020202020202020202020202020283 +:109DC0000202020202020202020202020202020273 +:109DD0000202020202020202020202020202020263 +:109DE0000202020202020202020202020202020253 +:109DF0000202020202020202020202020202020243 +:109E00000202020202020202020202020202020232 +:109E10000202020202020202020202020202020222 +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202020202020202E2 +:109E600002020202020202020202020202020202D2 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020202020202020202B2 +:109E900002020202020202020202020202020202A2 +:109EA0000202020202020202020202020202020292 +:109EB0000202020202020202020202020202020282 +:109EC0000202020202020202020202020202020272 +:109ED0000202020202020202020202020202020262 +:109EE0000202020202020202020202020202020252 +:109EF0000202020202020202020202020202020242 +:109F00000202020202020202020202020202020231 +:109F10000202020202020202020202020202020221 +:109F20000202020202020202000000000000000021 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000000000000000000039 +:10A720000000000000000000010101010101010121 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500001010101010101010101010101010101E9 +:10A7600001010101010101010101010101010101D9 +:10A7700001010101010101010101010101010101C9 +:10A7800001010101010101010101010101010101B9 +:10A7900001010101010101010101010101010101A9 +:10A7A0000101010101010101010101010101010199 +:10A7B0000101010101010101010101010101010189 +:10A7C0000101010101010101010101010101010179 +:10A7D0000101010101010101010101010101010169 +:10A7E0000101010101010101010101010101010159 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600001010101010101010101010101010101D8 +:10A8700001010101010101010101010101010101C8 +:10A8800001010101010101010101010101010101B8 +:10A8900001010101010101010101010101010101A8 +:10A8A0000101010101010101010101010101010198 +:10A8B0000101010101010101010101010101010188 +:10A8C0000101010101010101010101010101010178 +:10A8D0000101010101010101010101010101010168 +:10A8E0000101010101010101010101010101010158 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800001010101010101010101010101010101B7 +:10A9900001010101010101010101010101010101A7 +:10A9A0000101010101010101010101010101010197 +:10A9B0000101010101010101010101010101010187 +:10A9C0000101010101010101010101010101010177 +:10A9D0000101010101010101010101010101010167 +:10A9E0000101010101010101010101010101010157 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA0000101010101010101010101010101010196 +:10AAB0000101010101010101010101010101010186 +:10AAC0000101010101010101010101010101010176 +:10AAD0000101010101010101010101010101010166 +:10AAE0000101010101010101010101010101010156 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB10000101010101010101010101010101010125 +:10AB20000101010101010101010101010101010115 +:10AB30000101010101010101010101010101010105 +:10AB400001010101010101010101010101010101F5 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010101C5 +:10AB800001010101010101010101010101010101B5 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010185 +:10ABC0000101010101010101010101010101010175 +:10ABD0000101010101010101010101010101010165 +:10ABE0000101010101010101010101010101010155 +:10ABF0000101010101010101010101010101010145 +:10AC00000101010101010101010101010101010134 +:10AC10000101010101010101010101010101010124 +:10AC20000101010101010101010101010101010114 +:10AC30000101010101010101010101010101010104 +:10AC400001010101010101010101010101010101F4 +:10AC500001010101010101010101010101010101E4 +:10AC600001010101010101010101010101010101D4 +:10AC700001010101010101010101010101010101C4 +:10AC800001010101010101010101010101010101B4 +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010184 +:10ACC0000101010101010101010101010101010174 +:10ACD0000101010101010101010101010101010164 +:10ACE0000101010101010101010101010101010154 +:10ACF0000101010101010101010101010101010144 +:10AD00000101010101010101010101010101010133 +:10AD10000101010101010101010101010101010123 +:10AD20000101010101010101010101010101010113 +:10AD30000101010101010101010101010101010103 +:10AD400001010101010101010101010101010101F3 +:10AD500001010101010101010101010101010101E3 +:10AD600001010101010101010101010101010101D3 +:10AD700001010101010101010101010101010101C3 +:10AD800001010101010101010101010101010101B3 +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010183 +:10ADC0000101010101010101010101010101010173 +:10ADD0000101010101010101010101010101010163 +:10ADE0000101010101010101010101010101010153 +:10ADF0000101010101010101010101010101010143 +:10AE00000101010101010101010101010101010132 +:10AE10000101010101010101010101010101010122 +:10AE2000010101010101010100000000000000001A +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000000000000000000000000000000000002B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD2000000000000000000001010101010101010B +:10BD300001010101010101010101010101010101F3 +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101010101010101010101B3 +:10BD800001010101010101010101010101010101A3 +:10BD90000101010101010101010101010101010193 +:10BDA0000101010101010101010101010101010183 +:10BDB0000101010101010101010101010101010173 +:10BDC0000101010101010101010101010101010163 +:10BDD0000101010101010101010101010101010153 +:10BDE0000101010101010101010101010101010143 +:10BDF0000101010101010101010101010101010133 +:10BE00000101010101010101010101010101010122 +:10BE10000101010101010101010101010101010112 +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101010101010101010101B2 +:10BE800001010101010101010101010101010101A2 +:10BE90000101010101010101010101010101010192 +:10BEA0000101010101010101010101010101010182 +:10BEB0000101010101010101010101010101010172 +:10BEC0000101010101010101010101010101010162 +:10BED0000101010101010101010101010101010152 +:10BEE0000101010101010101010101010101010142 +:10BEF0000101010101010101010101010101010132 +:10BF00000101010101010101010101010101010121 +:10BF10000101010101010101010101010101010111 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101010101010101010101B1 +:10BF800001010101010101010101010101010101A1 +:10BF90000101010101010101010101010101010191 +:10BFA0000101010101010101010101010101010181 +:10BFB0000101010101010101010101010101010171 +:10BFC0000101010101010101010101010101010161 +:10BFD0000101010101010101010101010101010151 +:10BFE0000101010101010101010101010101010141 +:10BFF0000101010101010101010101010101010131 +:10C000000101010101010101010101010101010120 +:10C010000101010101010101010101010101010110 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010101010101E0 +:10C0500001010101010101010101010101010101D0 +:10C0600001010101010101010101010101010101C0 +:10C0700001010101010101010101010101010101B0 +:10C0800001010101010101010101010101010101A0 +:10C090000101010101010101010101010101010190 +:10C0A0000101010101010101010101010101010180 +:10C0B0000101010101010101010101010101010170 +:10C0C0000101010101010101010101010101010160 +:10C0D0000101010101010101010101010101010150 +:10C0E0000101010101010101010101010101010140 +:10C0F0000101010101010101010101010101010130 +:10C10000010101010101010101010101010101011F +:10C11000010101010101010101010101010101010F +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010101010101DF +:10C1500001010101010101010101010101010101CF +:10C1600001010101010101010101010101010101BF +:10C1700001010101010101010101010101010101AF +:10C18000010101010101010101010101010101019F +:10C19000010101010101010101010101010101018F +:10C1A000010101010101010101010101010101017F +:10C1B000010101010101010101010101010101016F +:10C1C000010101010101010101010101010101015F +:10C1D000010101010101010101010101010101014F +:10C1E000010101010101010101010101010101013F +:10C1F000010101010101010101010101010101012F +:10C20000010101010101010101010101010101011E +:10C21000010101010101010101010101010101010E +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010101010101010101DE +:10C2500001010101010101010101010101010101CE +:10C2600001010101010101010101010101010101BE +:10C2700001010101010101010101010101010101AE +:10C28000010101010101010101010101010101019E +:10C29000010101010101010101010101010101018E +:10C2A000010101010101010101010101010101017E +:10C2B000010101010101010101010101010101016E +:10C2C000010101010101010101010101010101015E +:10C2D000010101010101010101010101010101014E +:10C2E000010101010101010101010101010101013E +:10C2F000010101010101010101010101010101012E +:10C30000010101010101010101010101010101011D +:10C31000010101010101010101010101010101010D +:10C3200001010101010101010101010101010101FD +:10C3300001010101010101010101010101010101ED +:10C3400001010101010101010101010101010101DD +:10C3500001010101010101010101010101010101CD +:10C3600001010101010101010101010101010101BD +:10C3700001010101010101010101010101010101AD +:10C38000010101010101010101010101010101019D +:10C39000010101010101010101010101010101018D +:10C3A000010101010101010101010101010101017D +:10C3B000010101010101010101010101010101016D +:10C3C000010101010101010101010101010101015D +:10C3D000010101010101010101010101010101014D +:10C3E000010101010101010101010101010101013D +:10C3F000010101010101010101010101010101012D +:10C40000010101010101010101010101010101011C +:10C41000010101010101010101010101010101010C +:10C420000101010101010101000000000000000004 +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000010101010101010100 +:10C8300001010101010101010101010101010101E8 +:10C8400001010101010101010101010101010101D8 +:10C8500001010101010101010101010101010101C8 +:10C8600001010101010101010101010101010101B8 +:10C8700001010101010101010101010101010101A8 +:10C880000101010101010101010101010101010198 +:10C890000101010101010101010101010101010188 +:10C8A0000101010101010101010101010101010178 +:10C8B0000101010101010101010101010101010168 +:10C8C0000101010101010101010101010101010158 +:10C8D0000101010101010101010101010101010148 +:10C8E0000101010101010101010101010101010138 +:10C8F0000101010101010101010101010101010128 +:10C900000101010101010101010101010101010117 +:10C910000101010101010101010101010101010107 +:10C9200001010101010101010101010101010101F7 +:10C9300001010101010101010101010101010101E7 +:10C9400001010101010101010101010101010101D7 +:10C9500001010101010101010101010101010101C7 +:10C9600001010101010101010101010101010101B7 +:10C9700001010101010101010101010101010101A7 +:10C980000101010101010101010101010101010197 +:10C990000101010101010101010101010101010187 +:10C9A0000101010101010101010101010101010177 +:10C9B0000101010101010101010101010101010167 +:10C9C0000101010101010101010101010101010157 +:10C9D0000101010101010101010101010101010147 +:10C9E0000101010101010101010101010101010137 +:10C9F0000101010101010101010101010101010127 +:10CA00000101010101010101010101010101010116 +:10CA10000101010101010101010101010101010106 +:10CA200001010101010101010202020202020202EE +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202020202B6 +:10CA600002020202020202020202020202020202A6 +:10CA70000202020202020202020202020202020296 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202020256 +:10CAC0000202020202020202020202020202020246 +:10CAD0000202020202020202020202020202020236 +:10CAE0000202020202020202020202020202020226 +:10CAF0000202020202020202020202020202020216 +:10CB00000202020202020202020202020202020205 +:10CB100002020202020202020202020202020202F5 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020202B5 +:10CB600002020202020202020202020202020202A5 +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000202020202020202020202020202020245 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF0000202020202020202020202020202020215 +:10CC00000202020202020202020202020202020204 +:10CC100002020202020202020202020202020202F4 +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202020202A4 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020202020202020202020224 +:10CCF0000202020202020202020202020202020214 +:10CD00000202020202020202020202020202020203 +:10CD100002020202020202020202020202020202F3 +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020202A3 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020202020202020202020202020243 +:10CDD0000202020202020202020202020202020233 +:10CDE0000202020202020202020202020202020223 +:10CDF0000202020202020202020202020202020213 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020202020252 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020232 +:10CEE0000202020202020202020202020202020222 +:10CEF0000202020202020202020202020202020212 +:10CF00000202020202020202020202020202020201 +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020202020251 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020231 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202020202020202020202020211 +:10D000000202020202020202020202020202020200 +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202020202020202020202020202020230 +:10D0E0000202020202020202020202020202020220 +:10D0F0000202020202020202020202020202020210 +:10D1000002020202020202020202020202020202FF +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D16000020202020202020202020202020202029F +:10D17000020202020202020202020202020202028F +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020202020202020202020202023F +:10D1D000020202020202020202020202020202022F +:10D1E000020202020202020202020202020202021F +:10D1F000020202020202020202020202020202020F +:10D2000002020202020202020202020202020202FE +:10D2100002020202020202020202020202020202EE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D000020202020202020202020202020202022E +:10D2E000020202020202020202020202020202021E +:10D2F000020202020202020202020202020202020E +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020202020202020202020202CD +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020202020202020202020202025D +:10D3B000020202020202020202020202020202024D +:10D3C000020202020202020202020202020202023D +:10D3D000020202020202020202020202020202022D +:10D3E000020202020202020202020202020202021D +:10D3F000020202020202020202020202020202020D +:10D4000002020202020202020202020202020202FC +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020202DC +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202020202020202025C +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020202020202020202023C +:10D4D000020202020202020202020202020202022C +:10D4E000020202020202020202020202020202021C +:10D4F000020202020202020202020202020202020C +:10D5000002020202020202020202020202020202FB +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020202020202020202020202CB +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A000020202020202020202020202020202025B +:10D5B000020202020202020202020202020202024B +:10D5C000020202020202020202020202020202023B +:10D5D000020202020202020202020202020202022B +:10D5E000020202020202020202020202020202021B +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B000020202020202020202020202020202024A +:10D6C000020202020202020202020202020202023A +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020202020202020202020239 +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C0000202020202020202020202020202020238 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202020202020237 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020000000000000000E6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000006D0000000000000084 +:10DF300001010101010101010101010101010101D1 +:10DF400001010101010101010101010101010101C1 +:10DF500001010101010101010101010101010101B1 +:10DF600001010101010101010101010101010101A1 +:10DF70000101010101010101010101010101010191 +:10DF80000101010101010101010101010101010181 +:10DF90000101010101010101010101010101010171 +:10DFA0000101010101010101010101010101010161 +:10DFB0000101010101010101010101010101010151 +:10DFC0000101010101010101010101010101010141 +:10DFD0000101010101010101010101010101010131 +:10DFE0000101010101010101010101010101010121 +:10DFF0000101010101010101010101010101010111 +:10E000000101010101010101010101010101010100 +:10E0100001010101010101010101010101010101F0 +:10E0200001010101010101010101010101010101E0 +:10E0300001010101010101010101010101010101D0 +:10E0400001010101010101010101010101010101C0 +:10E0500001010101010101010101010101010101B0 +:10E0600001010101010101010101010101010101A0 +:10E070000101010101010101010101010101010190 +:10E080000101010101010101010101010101010180 +:10E090000101010101010101010101010101010170 +:10E0A0000101010101010101010101010101010160 +:10E0B0000101010101010101010101010101010150 +:10E0C0000101010101010101010101010101010140 +:10E0D0000101010101010101010101010101010130 +:10E0E0000101010101010101010101010101010120 +:10E0F0000101010101010101010101010101010110 +:10E1000001010101010101010101010101010101FF +:10E1100001010101010101010101010101010101EF +:10E1200001010101010101010101010101010101DF +:10E1300001010101010101010101010101010101CF +:10E1400001010101010101010101010101010101BF +:10E1500001010101010101010101010101010101AF +:10E16000010101010101010101010101010101019F +:10E17000010101010101010101010101010101018F +:10E18000010101010101010101010101010101017F +:10E19000010101010101010101010101010101016F +:10E1A000010101010101010101010101010101015F +:10E1B000010101010101010101010101010101014F +:10E1C000010101010101010101010101010101013F +:10E1D000010101010101010101010101010101012F +:10E1E000010101010101010101010101010101011F +:10E1F000010101010101010101010101010101010F +:10E2000001010101010101010101010101010101FE +:10E2100001010101010101010101010101010101EE +:10E2200001010101010101010101010101010101DE +:10E2300001010101010101010101010101010101CE +:10E2400001010101010101010101010101010101BE +:10E2500001010101010101010101010101010101AE +:10E26000010101010101010101010101010101019E +:10E27000010101010101010101010101010101018E +:10E28000010101010101010101010101010101017E +:10E29000010101010101010101010101010101016E +:10E2A000010101010101010101010101010101015E +:10E2B000010101010101010101010101010101014E +:10E2C000010101010101010101010101010101013E +:10E2D000010101010101010101010101010101012E +:10E2E000010101010101010101010101010101011E +:10E2F000010101010101010101010101010101010E +:10E3000001010101010101010101010101010101FD +:10E3100001010101010101010101010101010101ED +:10E3200001010101010101010101010101010101DD +:10E3300001010101010101010101010101010101CD +:10E3400001010101010101010101010101010101BD +:10E3500001010101010101010101010101010101AD +:10E36000010101010101010101010101010101019D +:10E37000010101010101010101010101010101018D +:10E38000010101010101010101010101010101017D +:10E39000010101010101010101010101010101016D +:10E3A000010101010101010101010101010101015D +:10E3B000010101010101010101010101010101014D +:10E3C000010101010101010101010101010101013D +:10E3D000010101010101010101010101010101012D +:10E3E000010101010101010101010101010101011D +:10E3F000010101010101010101010101010101010D +:10E4000001010101010101010101010101010101FC +:10E4100001010101010101010101010101010101EC +:10E4200001010101010101010101010101010101DC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000000000000000000000037 +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000000000000000000000036 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000000000000000000000035 +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000000000000000000000034 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300001010101010101010101010101010101B9 +:10F7400001010101010101010101010101010101A9 +:10F750000101010101010101010101010101010199 +:10F760000101010101010101010101010101010189 +:10F770000101010101010101010101010101010179 +:10F780000101010101010101010101010101010169 +:10F790000101010101010101010101010101010159 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010101010101010101010101010139 +:10F7C0000101010101010101010101010101010129 +:10F7D0000101010101010101010101010101010119 +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101010101010101010101010101C8 +:10F8300001010101010101010101010101010101B8 +:10F8400001010101010101010101010101010101A8 +:10F850000101010101010101010101010101010198 +:10F860000101010101010101010101010101010188 +:10F870000101010101010101010101010101010178 +:10F880000101010101010101010101010101010168 +:10F890000101010101010101010101010101010158 +:10F8A0000101010101010101010101010101010148 +:10F8B0000101010101010101010101010101010138 +:10F8C0000101010101010101010101010101010128 +:10F8D0000101010101010101010101010101010118 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010101010101010101010101B7 +:10F9400001010101010101010101010101010101A7 +:10F950000101010101010101010101010101010197 +:10F960000101010101010101010101010101010187 +:10F970000101010101010101010101010101010177 +:10F980000101010101010101010101010101010167 +:10F990000101010101010101010101010101010157 +:10F9A0000101010101010101010101010101010147 +:10F9B0000101010101010101010101010101010137 +:10F9C0000101010101010101010101010101010127 +:10F9D0000101010101010101010101010101010117 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA400001010101010101010101010101010101A6 +:10FA50000101010101010101010101010101010196 +:10FA60000101010101010101010101010101010186 +:10FA70000101010101010101010101010101010176 +:10FA80000101010101010101010101010101010166 +:10FA90000101010101010101010101010101010156 +:10FAA0000101010101010101010101010101010146 +:10FAB0000101010101010101010101010101010136 +:10FAC0000101010101010101010101010101010126 +:10FAD0000101010101010101010101010101010116 +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010101010101010101010101A5 +:10FB50000101010101010101010101010101010195 +:10FB60000101010101010101010101010101010185 +:10FB70000101010101010101010101010101010175 +:10FB80000101010101010101010101010101010165 +:10FB90000101010101010101010101010101010155 +:10FBA0000101010101010101010101010101010145 +:10FBB0000101010101010101010101010101010135 +:10FBC0000101010101010101010101010101010125 +:10FBD0000101010101010101010101010101010115 +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000000000000000000000000000000000034 +:10FCD0000000000000000000000000000000000024 +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000004 +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:020000025000AC +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101010101010101010130 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101010101010101010110 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C000010101010101010101010101010101011F +:1001D000010101010101010101010101010101010F +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000020202020202020202020202020202023E +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C000020202020202020202020202020202020E +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000002020202020202020202020202020202CD +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202020202020202020D +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000002020202020202020202020202020202CC +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020202020202020202023C +:1004A000020202020202020202020202020202022C +:1004B000020202020202020202020202020202021C +:1004C000020202020202020202020202020202020C +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000002020202020202020202020202020202CB +:1005100002020202020202020202020202020202BB +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202020202020202028B +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202024B +:10059000020202020202020202020202020202023B +:1005A000020202020202020202020202020202022B +:1005B000020202020202020202020202020202021B +:1005C000020202020202020202020202020202020B +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020202020202020202027A +:10066000020202020202020202020202020202026A +:10067000020202020202020202020202020202025A +:10068000020202020202020202020202020202024A +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020202020202020202021A +:1006C000020202020202020202020202020202020A +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020202020202020202B9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:100740000202020202020202020202020202020289 +:100750000202020202020202020202020202020279 +:100760000202020202020202020202020202020269 +:100770000202020202020202020202020202020259 +:100780000202020202020202020202020202020249 +:100790000202020202020202020202020202020239 +:1007A0000202020202020202020202020202020229 +:1007B0000202020202020202020202020202020219 +:1007C0000202020202020202020202020202020209 +:1007D00002020202020202020202020202020202F9 +:1007E00002020202020202020202020202020202E9 +:1007F00002020202020202020202020202020202D9 +:1008000002020202020202020202020202020202C8 +:1008100002020202020202020202020202020202B8 +:1008200002020202020202020202020202020202A8 +:100830000202020202020202020202020202020298 +:100840000202020202020202020202020202020288 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020248 +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B0000202020202020202020202020202020218 +:1008C0000202020202020202020202020202020208 +:1008D00002020202020202020202020202020202F8 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000002020202020202020202020202020202C7 +:1009100002020202020202020202020202020202B7 +:1009200002020202020202020202020202020202A7 +:100930000202020202020202020202020202020297 +:100940000202020202020202020202020202020287 +:100950000202020202020202020202020202020277 +:100960000202020202020202020202020202020267 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020247 +:100990000202020202020202020202020202020237 +:1009A0000202020202020202020202020202020227 +:1009B0000202020202020202020202020202020217 +:1009C0000202020202020202020202020202020207 +:1009D00002020202020202020202020202020202F7 +:1009E00002020202020202020202020202020202E7 +:1009F00002020202020202020202020202020202D7 +:100A000002020202020202020202020202020202C6 +:100A100002020202020202020202020202020202B6 +:100A200002020202020202020202020202020202A6 +:100A30000202020202020202020202020202020296 +:100A40000202020202020202020202020202020286 +:100A50000202020202020202020202020202020276 +:100A60000202020202020202020202020202020266 +:100A70000202020202020202020202020202020256 +:100A80000202020202020202020202020202020246 +:100A90000202020202020202020202020202020236 +:100AA0000202020202020202020202020202020226 +:100AB0000202020202020202020202020202020216 +:100AC0000202020202020202020202020202020206 +:100AD00002020202020202020202020202020202F6 +:100AE00002020202020202020202020202020202E6 +:100AF00002020202020202020202020202020202D6 +:100B000002020202020202020202020202020202C5 +:100B100002020202020202020202020202020202B5 +:100B200002020202020202020202020202020202A5 +:100B30000202020202020202020202020202020295 +:100B40000202020202020202020202020202020285 +:100B50000202020202020202020202020202020275 +:100B60000202020202020202020202020202020265 +:100B70000202020202020202020202020202020255 +:100B80000202020202020202020202020202020245 +:100B90000202020202020202020202020202020235 +:100BA0000202020202020202020202020202020225 +:100BB0000202020202020202020202020202020215 +:100BC0000202020202020202020202020202020205 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202020202D5 +:100C000002020202020202020202020202020202C4 +:100C100002020202020202020202020202020202B4 +:100C200002020202020202020202020202020202A4 +:100C30000202020202020202020202020202020294 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000000000000000000001C +:1014D000000000000000000000000000000000000C +:1014E00000000000000000000000000000000000FC +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:101730000101010101010101010101010101010199 +:101740000101010101010101010101010101010189 +:101750000101010101010101010101010101010179 +:101760000101010101010101010101010101010169 +:101770000101010101010101010101010101010159 +:101780000101010101010101010101010101010149 +:101790000101010101010101010101010101010139 +:1017A0000101010101010101010101010101010129 +:1017B0000101010101010101010101010101010119 +:1017C0000101010101010101010101010101010109 +:1017D00001010101010101010101010101010101F9 +:1017E00001010101010101010101010101010101E9 +:1017F00001010101010101010101010101010101D9 +:1018000001010101010101010101010101010101C8 +:1018100001010101010101010101010101010101B8 +:1018200001010101010101010101010101010101A8 +:101830000101010101010101010101010101010198 +:101840000101010101010101010101010101010188 +:101850000101010101010101010101010101010178 +:101860000101010101010101010101010101010168 +:101870000101010101010101010101010101010158 +:101880000101010101010101010101010101010148 +:101890000101010101010101010101010101010138 +:1018A0000101010101010101010101010101010128 +:1018B0000101010101010101010101010101010118 +:1018C0000101010101010101010101010101010108 +:1018D00001010101010101010101010101010101F8 +:1018E00001010101010101010101010101010101E8 +:1018F00001010101010101010101010101010101D8 +:1019000001010101010101010101010101010101C7 +:1019100001010101010101010101010101010101B7 +:1019200001010101010101010101010101010101A7 +:101930000101010101010101010101010101010197 +:101940000101010101010101010101010101010187 +:101950000101010101010101010101010101010177 +:101960000101010101010101010101010101010167 +:101970000101010101010101010101010101010157 +:101980000101010101010101010101010101010147 +:101990000101010101010101010101010101010137 +:1019A0000101010101010101010101010101010127 +:1019B0000101010101010101010101010101010117 +:1019C0000101010101010101010101010101010107 +:1019D00001010101010101010101010101010101F7 +:1019E00001010101010101010101010101010101E7 +:1019F00001010101010101010101010101010101D7 +:101A000001010101010101010101010101010101C6 +:101A100001010101010101010101010101010101B6 +:101A200001010101010101010101010101010101A6 +:101A30000101010101010101010101010101010196 +:101A40000101010101010101010101010101010186 +:101A50000101010101010101010101010101010176 +:101A60000101010101010101010101010101010166 +:101A70000101010101010101010101010101010156 +:101A80000101010101010101010101010101010146 +:101A90000101010101010101010101010101010136 +:101AA0000101010101010101010101010101010126 +:101AB0000101010101010101010101010101010116 +:101AC0000101010101010101010101010101010106 +:101AD00001010101010101010101010101010101F6 +:101AE00001010101010101010101010101010101E6 +:101AF00001010101010101010101010101010101D6 +:101B000001010101010101010101010101010101C5 +:101B100001010101010101010101010101010101B5 +:101B200001010101010101010101010101010101A5 +:101B30000101010101010101010101010101010195 +:101B40000101010101010101010101010101010185 +:101B50000101010101010101010101010101010175 +:101B60000101010101010101010101010101010165 +:101B70000101010101010101010101010101010155 +:101B80000101010101010101010101010101010145 +:101B90000101010101010101010101010101010135 +:101BA0000101010101010101010101010101010125 +:101BB0000101010101010101010101010101010115 +:101BC0000101010101010101010101010101010105 +:101BD00001010101010101010101010101010101F5 +:101BE00001010101010101010101010101010101E5 +:101BF00001010101010101010101010101010101D5 +:101C000001010101010101010101010101010101C4 +:101C100001010101010101010101010101010101B4 +:101C200001010101010101010101010101010101A4 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000000000000000000000000000054 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000000000000000000000034 +:101CB0000000000000000000000000000000000024 +:101CC0000000000000000000000000000000000014 +:101CD0000000000000000000000000000000000004 +:101CE00000000000000000000000000000000000F4 +:101CF00000000000000000000000000000000000E4 +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000000C3 +:101D200000000000000000000000000000000000B3 +:101D300000000000000000000000000000000000A3 +:101D40000000000000000000000000000000000093 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000073 +:101D70000000000000000000000000000000000063 +:101D80000000000000000000000000000000000053 +:101D90000000000000000000000000000000000043 +:101DA0000000000000000000000000000000000033 +:101DB0000000000000000000000000000000000023 +:101DC0000000000000000000000000000000000013 +:101DD0000000000000000000000000000000000003 +:101DE00000000000000000000000000000000000F3 +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E300000000000000000000000000000000000A2 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000000000000000000022 +:101EC0000000000000000000000000000000000012 +:101ED0000000000000000000000000000000000002 +:101EE00000000000000000000000000000000000F2 +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000000000000000000B1 +:101F300000000000000000000000000000000000A1 +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F80000000000000000000000000000000000051 +:101F90000000000000000000000000000000000041 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000000000000000000021 +:101FC0000000000000000000000000000000000011 +:101FD0000000000000000000000000000000000001 +:101FE00000000000000000000000000000000000F1 +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000000000000000000B0 +:1020300000000000000000000000000000000000A0 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000000000000000010 +:1020D0000000000000000000000000000000000000 +:1020E00000000000000000000000000000000000F0 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00000000000000000000000000000000000FD +:1023E00000000000000000000000000000000000ED +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000000E8 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000000E6 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000004 +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:10317000010101010101010101010101010101013F +:10318000010101010101010101010101010101012F +:10319000010101010101010101010101010101011F +:1031A000010101010101010101010101010101010F +:1031B00001010101010101010101010101010101FF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000010101010101010101010101010101014E +:10327000010101010101010101010101010101013E +:10328000010101010101010101010101010101012E +:10329000010101010101010101010101010101011E +:1032A000010101010101010101010101010101010E +:1032B00001010101010101010101010101010101FE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000010101010101010101010101010101011D +:1033A000010101010101010101010101010101010D +:1033B00001010101010101010101010101010101FD +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000000EC +:1034E00000000000000000000000000000000000DC +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000000000000000000000EB +:1035E00000000000000000000000000000000000DB +:1035F00000000000000000000000000000000000CB +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010101F8 +:1038C00001010101010101010101010101010101E8 +:1038D00001010101010101010101010101010101D8 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010101010101010101010167 +:103950000101010101010101010101010101010157 +:103960000101010101010101010101010101010147 +:103970000101010101010101010101010101010137 +:103980000101010101010101010101010101010127 +:103990000101010101010101010101010101010117 +:1039A0000101010101010101010101010101010107 +:1039B00001010101010101010101010101010101F7 +:1039C00001010101010101010101010101010101E7 +:1039D00001010101010101010101010101010101D7 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000202020202020202020202020202020266 +:103A40000202020202020202020202020202020256 +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020202020236 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202020202020202020216 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B00000202020202020202020202020202020295 +:103B10000202020202020202020202020202020285 +:103B20000202020202020202020202020202020275 +:103B30000202020202020202020202020202020265 +:103B40000202020202020202020202020202020255 +:103B50000202020202020202020202020202020245 +:103B60000202020202020202020202020202020235 +:103B70000202020202020202020202020202020225 +:103B80000202020202020202020202020202020215 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00002020202020202020202020202020202B5 +:103BF00002020202020202020202020202020202A5 +:103C00000202020202020202020202020202020294 +:103C10000202020202020202020202020202020284 +:103C20000202020202020202020202020202020274 +:103C30000202020202020202020202020202020264 +:103C40000202020202020202020202020202020254 +:103C50000202020202020202020202020202020244 +:103C60000202020202020202020202020202020234 +:103C70000202020202020202020202020202020224 +:103C80000202020202020202020202020202020214 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00002020202020202020202020202020202D4 +:103CD00002020202020202020202020202020202C4 +:103CE00002020202020202020202020202020202B4 +:103CF00002020202020202020202020202020202A4 +:103D00000202020202020202020202020202020293 +:103D10000202020202020202020202020202020283 +:103D20000202020202020202020202020202020273 +:103D30000202020202020202020202020202020263 +:103D40000202020202020202020202020202020253 +:103D50000202020202020202020202020202020243 +:103D60000202020202020202020202020202020233 +:103D70000202020202020202020202020202020223 +:103D80000202020202020202020202020202020213 +:103D90000202020202020202020202020202020203 +:103DA00002020202020202020202020202020202F3 +:103DB00002020202020202020202020202020202E3 +:103DC00002020202020202020202020202020202D3 +:103DD00002020202020202020202020202020202C3 +:103DE00002020202020202020202020202020202B3 +:103DF00002020202020202020202020202020202A3 +:103E00000202020202020202020202020202020292 +:103E10000202020202020202020202020202020282 +:103E20000202020202020202020202020202020272 +:103E30000202020202020202020202020202020262 +:103E40000202020202020202020202020202020252 +:103E50000202020202020202020202020202020242 +:103E60000202020202020202020202020202020232 +:103E70000202020202020202020202020202020222 +:103E80000202020202020202020202020202020212 +:103E90000202020202020202020202020202020202 +:103EA00002020202020202020202020202020202F2 +:103EB00002020202020202020202020202020202E2 +:103EC00002020202020202020202020202020202D2 +:103ED00002020202020202020202020202020202C2 +:103EE00002020202020202020202020202020202B2 +:103EF00002020202020202020202020202020202A2 +:103F00000202020202020202020202020202020291 +:103F10000202020202020202020202020202020281 +:103F20000202020202020202020202020202020271 +:103F30000202020202020202020202020202020261 +:103F40000202020202020202020202020202020251 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202029E +:10430000020202020202020202020202020202028D +:10431000020202020202020202020202020202027D +:10432000020202020202020202020202020202026D +:10433000020202020202020202020202020202025D +:10434000020202020202020202020202020202024D +:10435000020202020202020202020202020202023D +:10436000020202020202020202020202020202022D +:10437000020202020202020202020202020202021D +:10438000020202020202020202020202020202020D +:1043900002020202020202020202020202020202FD +:1043A00002020202020202020202020202020202ED +:1043B00002020202020202020202020202020202DD +:1043C00002020202020202020202020202020202CD +:1043D00002020202020202020202020202020202BD +:1043E00002020202020202020202020202020202AD +:1043F000020202020202020202020202020202029D +:10440000020202020202020202020202020202028C +:10441000020202020202020202020202020202027C +:10442000020202020202020202020202020202026C +:10443000020202020202020202020202020202025C +:10444000020202020202020202020202020202024C +:10445000020202020202020202020202020202023C +:10446000020202020202020202020202020202022C +:10447000020202020202020202020202020202021C +:10448000020202020202020202020202020202020C +:1044900002020202020202020202020202020202FC +:1044A00002020202020202020202020202020202EC +:1044B00002020202020202020202020202020202DC +:1044C00002020202020202020202020202020202CC +:1044D00002020202020202020202020202020202BC +:1044E00002020202020202020202020202020202AC +:1044F000020202020202020202020202020202029C +:10450000020202020202020202020202020202028B +:10451000020202020202020202020202020202027B +:10452000020202020202020202020202020202026B +:10453000020202020202020202020202020202025B +:10454000020202020202020202020202020202024B +:10455000020202020202020202020202020202023B +:10456000020202020202020202020202020202022B +:10457000020202020202020202020202020202021B +:10458000020202020202020202020202020202020B +:1045900002020202020202020202020202020202FB +:1045A00002020202020202020202020202020202EB +:1045B00002020202020202020202020202020202DB +:1045C00002020202020202020202020202020202CB +:1045D00002020202020202020202020202020202BB +:1045E00002020202020202020202020202020202AB +:1045F000020202020202020202020202020202029B +:10460000020202020202020202020202020202028A +:10461000020202020202020202020202020202027A +:10462000020202020202020202020202020202026A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30006700000000000000010101010101010105 +:104C40000101010101010101010101010101010154 +:104C50000101010101010101010101010101010144 +:104C60000101010101010101010101010101010134 +:104C70000101010101010101010101010101010124 +:104C80000101010101010101010101010101010114 +:104C90000101010101010101010101010101010104 +:104CA00001010101010101010101010101010101F4 +:104CB00001010101010101010101010101010101E4 +:104CC00001010101010101010101010101010101D4 +:104CD00001010101010101010101010101010101C4 +:104CE00001010101010101010101010101010101B4 +:104CF00001010101010101010101010101010101A4 +:104D00000101010101010101010101010101010193 +:104D10000101010101010101010101010101010183 +:104D20000101010101010101010101010101010173 +:104D30000101010101010101010101010101010163 +:104D40000101010101010101010101010101010153 +:104D50000101010101010101010101010101010143 +:104D60000101010101010101010101010101010133 +:104D70000101010101010101010101010101010123 +:104D80000101010101010101010101010101010113 +:104D90000101010101010101010101010101010103 +:104DA00001010101010101010101010101010101F3 +:104DB00001010101010101010101010101010101E3 +:104DC00001010101010101010101010101010101D3 +:104DD00001010101010101010101010101010101C3 +:104DE00001010101010101010101010101010101B3 +:104DF00001010101010101010101010101010101A3 +:104E00000101010101010101010101010101010192 +:104E10000101010101010101010101010101010182 +:104E20000101010101010101010101010101010172 +:104E30000101010101010101010101010101010162 +:104E40000101010101010101010101010101010152 +:104E50000101010101010101010101010101010142 +:104E60000101010101010101010101010101010132 +:104E70000101010101010101010101010101010122 +:104E80000101010101010101010101010101010112 +:104E90000101010101010101010101010101010102 +:104EA00001010101010101010101010101010101F2 +:104EB00001010101010101010101010101010101E2 +:104EC00001010101010101010101010101010101D2 +:104ED00001010101010101010101010101010101C2 +:104EE00001010101010101010101010101010101B2 +:104EF00001010101010101010101010101010101A2 +:104F00000101010101010101010101010101010191 +:104F10000101010101010101010101010101010181 +:104F20000101010101010101010101010101010171 +:104F30000101010101010101010101010101010161 +:104F40000101010101010101010101010101010151 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101000000000000000068 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000000CA +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000000000000000000000C9 +:1057E00000000000000000000000000000000000B9 +:1057F00000000000000000000000000000000000A9 +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000000000000000000000C8 +:1058E00000000000000000000000000000000000B8 +:1058F00000000000000000000000000000000000A8 +:105900000000000000000000000000000000000097 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000000000000000000000C7 +:1059E00000000000000000000000000000000000B7 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000000000000000000008F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:106530000000000000000000010101010101010153 +:10654000010101010101010101010101010101013B +:10655000010101010101010101010101010101012B +:10656000010101010101010101010101010101011B +:10657000010101010101010101010101010101010B +:1065800001010101010101010101010101010101FB +:1065900001010101010101010101010101010101EB +:1065A00001010101010101010101010101010101DB +:1065B00001010101010101010101010101010101CB +:1065C00001010101010101010101010101010101BB +:1065D00001010101010101010101010101010101AB +:1065E000010101010101010101010101010101019B +:1065F000010101010101010101010101010101018B +:10660000010101010101010101010101010101017A +:10661000010101010101010101010101010101016A +:10662000010101010101010101010101010101015A +:10663000010101010101010101010101010101014A +:10664000010101010101010101010101010101013A +:10665000010101010101010101010101010101012A +:10666000010101010101010101010101010101011A +:10667000010101010101010101010101010101010A +:1066800001010101010101010101010101010101FA +:1066900001010101010101010101010101010101EA +:1066A00001010101010101010101010101010101DA +:1066B00001010101010101010101010101010101CA +:1066C00001010101010101010101010101010101BA +:1066D00001010101010101010101010101010101AA +:1066E000010101010101010101010101010101019A +:1066F000010101010101010101010101010101018A +:106700000101010101010101010101010101010179 +:106710000101010101010101010101010101010169 +:106720000101010101010101010101010101010159 +:106730000101010101010101010101010101010149 +:106740000101010101010101010101010101010139 +:106750000101010101010101010101010101010129 +:106760000101010101010101010101010101010119 +:106770000101010101010101010101010101010109 +:1067800001010101010101010101010101010101F9 +:1067900001010101010101010101010101010101E9 +:1067A00001010101010101010101010101010101D9 +:1067B00001010101010101010101010101010101C9 +:1067C00001010101010101010101010101010101B9 +:1067D00001010101010101010101010101010101A9 +:1067E0000101010101010101010101010101010199 +:1067F0000101010101010101010101010101010189 +:106800000101010101010101010101010101010178 +:106810000101010101010101010101010101010168 +:106820000101010101010101010101010101010158 +:106830000101010101010101010101010101010148 +:106840000101010101010101010101010101010138 +:106850000101010101010101010101010101010128 +:106860000101010101010101010101010101010118 +:106870000101010101010101010101010101010108 +:1068800001010101010101010101010101010101F8 +:1068900001010101010101010101010101010101E8 +:1068A00001010101010101010101010101010101D8 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:10693000010101010101010100000000000000004F +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000000000000000000B7 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000097 +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000000B6 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000096 +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000035 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000020202020202020240 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000020202020202020202020202020202025F +:10711000020202020202020202020202020202024F +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000020202020202020202020202020202025E +:10721000020202020202020202020202020202024E +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202000000000000000038 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000000B8 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:108130000000000000000000010101010101010137 +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000010101010101010101010101010101010D +:1083600001010101010101010101010101010101FD +:1083700001010101010101010101010101010101ED +:1083800001010101010101010101010101010101DD +:1083900001010101010101010101010101010101CD +:1083A00001010101010101010101010101010101BD +:1083B00001010101010101010101010101010101AD +:1083C000010101010101010101010101010101019D +:1083D000010101010101010101010101010101018D +:1083E000010101010101010101010101010101017D +:1083F000010101010101010101010101010101016D +:10840000010101010101010101010101010101015C +:10841000010101010101010101010101010101014C +:10842000010101010101010101010101010101013C +:10843000010101010101010101010101010101012C +:10844000010101010101010101010101010101011C +:10845000010101010101010101010101010101010C +:1084600001010101010101010101010101010101FC +:1084700001010101010101010101010101010101EC +:1084800001010101010101010101010101010101DC +:1084900001010101010101010101010101010101CC +:1084A00001010101010101010101010101010101BC +:1084B00001010101010101010101010101010101AC +:1084C000010101010101010101010101010101019C +:1084D000010101010101010101010101010101018C +:1084E000010101010101010101010101010101017C +:1084F000010101010101010101010101010101016C +:10850000010101010101010101010101010101015B +:10851000010101010101010101010101010101014B +:10852000010101010101010101010101010101013B +:108530000101010101010101000000000000000033 +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D000000000000000000000000000000000008B +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:10960000000000000000000000000000000000005A +:10961000000000000000000000000000000000004A +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C000000000000000000000000000000000009A +:1096D000000000000000000000000000000000008A +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000049 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000099 +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000000000000000000000A8 +:1098C0000000000000000000000000000000000098 +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000000000000000078 +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000000000057 +:109910000000000000000000000000000000000047 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000000B7 +:1099B00000000000000000000000000000000000A7 +:1099C0000000000000000000000000000000000097 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0000000000000000000000000000000000067 +:109A00000000000000000000000000000000000056 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A3000000000000000000001010101010101011E +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C500001010101010101010101010101010101F4 +:109C600001010101010101010101010101010101E4 +:109C700001010101010101010101010101010101D4 +:109C800001010101010101010101010101010101C4 +:109C900001010101010101010101010101010101B4 +:109CA00001010101010101010101010101010101A4 +:109CB0000101010101010101010101010101010194 +:109CC0000101010101010101010101010101010184 +:109CD0000101010101010101010101010101010174 +:109CE0000101010101010101010101010101010164 +:109CF0000101010101010101010101010101010154 +:109D00000101010101010101010101010101010143 +:109D10000101010101010101010101010101010133 +:109D20000101010101010101010101010101010123 +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010101010101010101F3 +:109D600001010101010101010101010101010101E3 +:109D700001010101010101010101010101010101D3 +:109D800001010101010101010101010101010101C3 +:109D900001010101010101010101010101010101B3 +:109DA00001010101010101010101010101010101A3 +:109DB0000101010101010101010101010101010193 +:109DC0000101010101010101010101010101010183 +:109DD0000101010101010101010101010101010173 +:109DE0000101010101010101010101010101010163 +:109DF0000101010101010101010101010101010153 +:109E00000101010101010101010101010101010142 +:109E10000101010101010101010101010101010132 +:109E20000101010101010101010101010101010122 +:109E3000010101010101010100000000000000001A +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000002020202020202020B +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E000020202020202020202020202020202024B +:10A5F000020202020202020202020202020202023B +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E000020202020202020202020202020202024A +:10A6F000020202020202020202020202020202023A +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000202020202020202020202020202020239 +:10A800000202020202020202020202020202020228 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020202A8 +:10A890000202020202020202020202020202020298 +:10A8A0000202020202020202020202020202020288 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020202A6 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020202020202020202020202020286 +:10AAB0000202020202020202020202020202020276 +:10AAC0000202020202020202020202020202020266 +:10AAD0000202020202020202020202020202020256 +:10AAE0000202020202020202020202020202020246 +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202020202F5 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020202A5 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020202020202020202020285 +:10ABB0000202020202020202020202020202020275 +:10ABC0000202020202020202020202020202020265 +:10ABD0000202020202020202020202020202020255 +:10ABE0000202020202020202020202020202020245 +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020202A4 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020202020202020202020284 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020202020264 +:10ACD0000202020202020202020202020202020254 +:10ACE0000202020202020202020202020202020244 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD30000202020202020202000000000000000003 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000001D +:10B3300000000000000000006900000000000000A4 +:10B3400001010101010101010101010101010101ED +:10B3500001010101010101010101010101010101DD +:10B3600001010101010101010101010101010101CD +:10B3700001010101010101010101010101010101BD +:10B3800001010101010101010101010101010101AD +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010101010101010101018D +:10B3B000010101010101010101010101010101017D +:10B3C000010101010101010101010101010101016D +:10B3D000010101010101010101010101010101015D +:10B3E000010101010101010101010101010101014D +:10B3F000010101010101010101010101010101013D +:10B40000010101010101010101010101010101012C +:10B41000010101010101010101010101010101011C +:10B42000010101010101010101010101010101010C +:10B4300001010101010101010101010101010101FC +:10B4400001010101010101010101010101010101EC +:10B4500001010101010101010101010101010101DC +:10B4600001010101010101010101010101010101CC +:10B4700001010101010101010101010101010101BC +:10B4800001010101010101010101010101010101AC +:10B49000010101010101010101010101010101019C +:10B4A000010101010101010101010101010101018C +:10B4B000010101010101010101010101010101017C +:10B4C000010101010101010101010101010101016C +:10B4D000010101010101010101010101010101015C +:10B4E000010101010101010101010101010101014C +:10B4F000010101010101010101010101010101013C +:10B50000010101010101010101010101010101012B +:10B51000010101010101010101010101010101011B +:10B52000010101010101010101010101010101010B +:10B5300001010101010101010101010101010101FB +:10B5400001010101010101010101010101010101EB +:10B5500001010101010101010101010101010101DB +:10B5600001010101010101010101010101010101CB +:10B5700001010101010101010101010101010101BB +:10B5800001010101010101010101010101010101AB +:10B59000010101010101010101010101010101019B +:10B5A000010101010101010101010101010101018B +:10B5B000010101010101010101010101010101017B +:10B5C000010101010101010101010101010101016B +:10B5D000010101010101010101010101010101015B +:10B5E000010101010101010101010101010101014B +:10B5F000010101010101010101010101010101013B +:10B60000010101010101010101010101010101012A +:10B61000010101010101010101010101010101011A +:10B62000010101010101010101010101010101010A +:10B6300001010101010101010101010101010101FA +:10B6400001010101010101010101010101010101EA +:10B6500001010101010101010101010101010101DA +:10B6600001010101010101010101010101010101CA +:10B6700001010101010101010101010101010101BA +:10B6800001010101010101010101010101010101AA +:10B69000010101010101010101010101010101019A +:10B6A000010101010101010101010101010101018A +:10B6B000010101010101010101010101010101017A +:10B6C000010101010101010101010101010101016A +:10B6D000010101010101010101010101010101015A +:10B6E000010101010101010101010101010101014A +:10B6F000010101010101010101010101010101013A +:10B700000101010101010101010101010101010129 +:10B710000101010101010101010101010101010119 +:10B720000101010101010101010101010101010109 +:10B7300001010101010101010101010101010101F9 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D000000000000000000000000000000000005E +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000000001D +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400001010101010101010101010101010101D4 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010101A4 +:10CC80000101010101010101010101010101010194 +:10CC90000101010101010101010101010101010184 +:10CCA0000101010101010101010101010101010174 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500001010101010101010101010101010101C3 +:10CD600001010101010101010101010101010101B3 +:10CD700001010101010101010101010101010101A3 +:10CD80000101010101010101010101010101010193 +:10CD90000101010101010101010101010101010183 +:10CDA0000101010101010101010101010101010173 +:10CDB0000101010101010101010101010101010163 +:10CDC0000101010101010101010101010101010153 +:10CDD0000101010101010101010101010101010143 +:10CDE0000101010101010101010101010101010133 +:10CDF0000101010101010101010101010101010123 +:10CE00000101010101010101010101010101010112 +:10CE10000101010101010101010101010101010102 +:10CE200001010101010101010101010101010101F2 +:10CE300001010101010101010101010101010101E2 +:10CE400001010101010101010101010101010101D2 +:10CE500001010101010101010101010101010101C2 +:10CE600001010101010101010101010101010101B2 +:10CE700001010101010101010101010101010101A2 +:10CE80000101010101010101010101010101010192 +:10CE90000101010101010101010101010101010182 +:10CEA0000101010101010101010101010101010172 +:10CEB0000101010101010101010101010101010162 +:10CEC0000101010101010101010101010101010152 +:10CED0000101010101010101010101010101010142 +:10CEE0000101010101010101010101010101010132 +:10CEF0000101010101010101010101010101010122 +:10CF00000101010101010101010101010101010111 +:10CF10000101010101010101010101010101010101 +:10CF200001010101010101010101010101010101F1 +:10CF300001010101010101010101010101010101E1 +:10CF400001010101010101010101010101010101D1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700001010101010101010101010101010101A1 +:10CF80000101010101010101010101010101010191 +:10CF90000101010101010101010101010101010181 +:10CFA0000101010101010101010101010101010171 +:10CFB0000101010101010101010101010101010161 +:10CFC0000101010101010101010101010101010151 +:10CFD0000101010101010101010101010101010141 +:10CFE0000101010101010101010101010101010131 +:10CFF0000101010101010101010101010101010121 +:10D000000101010101010101010101010101010110 +:10D010000101010101010101010101010101010100 +:10D0200001010101010101010101010101010101F0 +:10D0300001010101010101010101010101010101E0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400001010101010101010101010101010101CC +:10D4500001010101010101010101010101010101BC +:10D4600001010101010101010101010101010101AC +:10D47000010101010101010101010101010101019C +:10D48000010101010101010101010101010101018C +:10D49000010101010101010101010101010101017C +:10D4A000010101010101010101010101010101016C +:10D4B000010101010101010101010101010101015C +:10D4C000010101010101010101010101010101014C +:10D4D000010101010101010101010101010101013C +:10D4E000010101010101010101010101010101012C +:10D4F000010101010101010101010101010101011C +:10D50000010101010101010101010101010101010B +:10D5100001010101010101010101010101010101FB +:10D5200001010101010101010101010101010101EB +:10D5300001010101010101010101010101010101DB +:10D5400001010101010101010101010101010101CB +:10D5500001010101010101010101010101010101BB +:10D5600001010101010101010101010101010101AB +:10D57000010101010101010101010101010101019B +:10D58000010101010101010101010101010101018B +:10D59000010101010101010101010101010101017B +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000010101010101010101010101010101014B +:10D5D000010101010101010101010101010101013B +:10D5E000010101010101010101010101010101012B +:10D5F000010101010101010101010101010101011B +:10D60000010101010101010101010101010101010A +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010101010101010101EA +:10D6300001010101010101010101010101010101DA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B000020202020202020202020202020202024A +:10D6C000020202020202020202020202020202023A +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020202020202020202020239 +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C0000202020202020202020202020202020238 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202020202020237 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202020202020236 +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020202020202020202020216 +:10DAF0000202020202020202020202020202020206 +:10DB000002020202020202020202020202020202F5 +:10DB100002020202020202020202020202020202E5 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500002020202020202020202020202020202A5 +:10DB60000202020202020202020202020202020295 +:10DB70000202020202020202020202020202020285 +:10DB80000202020202020202020202020202020275 +:10DB90000202020202020202020202020202020265 +:10DBA0000202020202020202020202020202020255 +:10DBB0000202020202020202020202020202020245 +:10DBC0000202020202020202020202020202020235 +:10DBD0000202020202020202020202020202020225 +:10DBE0000202020202020202020202020202020215 +:10DBF0000202020202020202020202020202020205 +:10DC000002020202020202020202020202020202F4 +:10DC100002020202020202020202020202020202E4 +:10DC200002020202020202020202020202020202D4 +:10DC300002020202020202020202020202020202C4 +:10DC400002020202020202020202020202020202B4 +:10DC500002020202020202020202020202020202A4 +:10DC60000202020202020202020202020202020294 +:10DC70000202020202020202020202020202020284 +:10DC80000202020202020202020202020202020274 +:10DC90000202020202020202020202020202020264 +:10DCA0000202020202020202020202020202020254 +:10DCB0000202020202020202020202020202020244 +:10DCC0000202020202020202020202020202020234 +:10DCD0000202020202020202020202020202020224 +:10DCE0000202020202020202020202020202020214 +:10DCF0000202020202020202020202020202020204 +:10DD000002020202020202020202020202020202F3 +:10DD100002020202020202020202020202020202E3 +:10DD200002020202020202020202020202020202D3 +:10DD300002020202020202020202020202020202C3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB0000202020202020202020202020202020243 +:10DDC0000202020202020202020202020202020233 +:10DDD0000202020202020202020202020202020223 +:10DDE0000202020202020202020202020202020213 +:10DDF0000202020202020202020202020202020203 +:10DE000002020202020202020202020202020202F2 +:10DE100002020202020202020202020202020202E2 +:10DE200002020202020202020202020202020202D2 +:10DE300002020202020202020202020202020202C2 +:10DE400002020202020202020202020202020202B2 +:10DE500002020202020202020202020202020202A2 +:10DE60000202020202020202020202020202020292 +:10DE70000202020202020202020202020202020282 +:10DE80000202020202020202020202020202020272 +:10DE90000202020202020202020202020202020262 +:10DEA0000202020202020202020202020202020252 +:10DEB0000202020202020202020202020202020242 +:10DEC0000202020202020202020202020202020232 +:10DED0000202020202020202020202020202020222 +:10DEE0000202020202020202020202020202020212 +:10DEF0000202020202020202020202020202020202 +:10DF000002020202020202020202020202020202F1 +:10DF100002020202020202020202020202020202E1 +:10DF200002020202020202020202020202020202D1 +:10DF300002020202020202020202020202020202C1 +:10DF400002020202020202020202020202020202B1 +:10DF500002020202020202020202020202020202A1 +:10DF60000202020202020202020202020202020291 +:10DF70000202020202020202020202020202020281 +:10DF80000202020202020202020202020202020271 +:10DF90000202020202020202020202020202020261 +:10DFA0000202020202020202020202020202020251 +:10DFB0000202020202020202020202020202020241 +:10DFC0000202020202020202020202020202020231 +:10DFD0000202020202020202020202020202020221 +:10DFE0000202020202020202020202020202020211 +:10DFF0000202020202020202020202020202020201 +:10E0000002020202020202020202020202020202F0 +:10E0100002020202020202020202020202020202E0 +:10E0200002020202020202020202020202020202D0 +:10E0300002020202020202020202020202020202C0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D0000000000000000000000000000000000040 +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400001010101010101010101010101010101B7 +:10E9500001010101010101010101010101010101A7 +:10E960000101010101010101010101010101010197 +:10E970000101010101010101010101010101010187 +:10E980000101010101010101010101010101010177 +:10E990000101010101010101010101010101010167 +:10E9A0000101010101010101010101010101010157 +:10E9B0000101010101010101010101010101010147 +:10E9C0000101010101010101010101010101010137 +:10E9D0000101010101010101010101010101010127 +:10E9E0000101010101010101010101010101010117 +:10E9F0000101010101010101010101010101010107 +:10EA000001010101010101010101010101010101F6 +:10EA100001010101010101010101010101010101E6 +:10EA200001010101010101010101010101010101D6 +:10EA300001010101010101010101010101010101C6 +:10EA400001010101010101010101010101010101B6 +:10EA500001010101010101010101010101010101A6 +:10EA60000101010101010101010101010101010196 +:10EA70000101010101010101010101010101010186 +:10EA80000101010101010101010101010101010176 +:10EA90000101010101010101010101010101010166 +:10EAA0000101010101010101010101010101010156 +:10EAB0000101010101010101010101010101010146 +:10EAC0000101010101010101010101010101010136 +:10EAD0000101010101010101010101010101010126 +:10EAE0000101010101010101010101010101010116 +:10EAF0000101010101010101010101010101010106 +:10EB000001010101010101010101010101010101F5 +:10EB100001010101010101010101010101010101E5 +:10EB200001010101010101010101010101010101D5 +:10EB300001010101010101010101010101010101C5 +:10EB400001010101010101010101010101010101B5 +:10EB500001010101010101010101010101010101A5 +:10EB60000101010101010101010101010101010195 +:10EB70000101010101010101010101010101010185 +:10EB80000101010101010101010101010101010175 +:10EB90000101010101010101010101010101010165 +:10EBA0000101010101010101010101010101010155 +:10EBB0000101010101010101010101010101010145 +:10EBC0000101010101010101010101010101010135 +:10EBD0000101010101010101010101010101010125 +:10EBE0000101010101010101010101010101010115 +:10EBF0000101010101010101010101010101010105 +:10EC000001010101010101010101010101010101F4 +:10EC100001010101010101010101010101010101E4 +:10EC200001010101010101010101010101010101D4 +:10EC300001010101010101010101010101010101C4 +:10EC400001010101010101010101010101010101B4 +:10EC500001010101010101010101010101010101A4 +:10EC60000101010101010101010101010101010194 +:10EC70000101010101010101010101010101010184 +:10EC80000101010101010101010101010101010174 +:10EC90000101010101010101010101010101010164 +:10ECA0000101010101010101010101010101010154 +:10ECB0000101010101010101010101010101010144 +:10ECC0000101010101010101010101010101010134 +:10ECD0000101010101010101010101010101010124 +:10ECE0000101010101010101010101010101010114 +:10ECF0000101010101010101010101010101010104 +:10ED000001010101010101010101010101010101F3 +:10ED100001010101010101010101010101010101E3 +:10ED200001010101010101010101010101010101D3 +:10ED300001010101010101010101010101010101C3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000000000000000000000000000037 +:10F9D0000000000000000000000000000000000027 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000000000000000000000000000000000000F6 +:10FA100000000000000000000000000000000000E6 +:10FA200000000000000000000000000000000000D6 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC0000000000000000000000000000000000036 +:10FAD0000000000000000000000000000000000026 +:10FAE0000000000000000000000000000000000016 +:10FAF0000000000000000000000000000000000006 +:10FB000000000000000000000000000000000000F5 +:10FB100000000000000000000000000000000000E5 +:10FB200000000000000000000000000000000000D5 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000055 +:10FBB0000000000000000000000000000000000045 +:10FBC0000000000000000000000000000000000035 +:10FBD0000000000000000000000000000000000025 +:10FBE0000000000000000000000000000000000015 +:10FBF0000000000000000000000000000000000005 +:10FC000000000000000000000000000000000000F4 +:10FC100000000000000000000000000000000000E4 +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000000000000000000000000000000000034 +:10FCD0000000000000000000000000000000000024 +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000004 +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:0200000260009C +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000000000000000000000CF +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D000010101010101010101010101010101010E +:1002E00001010101010101010101010101010101FE +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010101010101010101DD +:1003100001010101010101010101010101010101CD +:1003200001010101010101010101010101010101BD +:1003300001010101010101010101010101010101AD +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010101010101010101CC +:1004200001010101010101010101010101010101BC +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010101010101010101CB +:1005200001010101010101010101010101010101BB +:1005300001010101010101010101010101010101AB +:10054000010101010101010101010101010101019B +:10055000010101010101010101010101010101018B +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010101010101010101010101010101015B +:10059000010101010101010101010101010101014B +:1005A000010101010101010101010101010101013B +:1005B000010101010101010101010101010101012B +:1005C000010101010101010101010101010101011B +:1005D000010101010101010101010101010101010B +:1005E00001010101010101010101010101010101FB +:1005F00001010101010101010101010101010101EB +:1006000001010101010101010101010101010101DA +:1006100001010101010101010101010101010101CA +:1006200001010101010101010101010101010101BA +:1006300001010101010101010101010101010101AA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A40000101010101010101010101010101010196 +:100A50000101010101010101010101010101010186 +:100A60000101010101010101010101010101010176 +:100A70000101010101010101010101010101010166 +:100A80000101010101010101010101010101010156 +:100A90000101010101010101010101010101010146 +:100AA0000101010101010101010101010101010136 +:100AB0000101010101010101010101010101010126 +:100AC0000101010101010101010101010101010116 +:100AD0000101010101010101010101010101010106 +:100AE00001010101010101010101010101010101F6 +:100AF00001010101010101010101010101010101E6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300001010101010101010101010101010101A5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000101010101010101010101010101010175 +:100B70000101010101010101010101010101010165 +:100B80000101010101010101010101010101010155 +:100B90000101010101010101010101010101010145 +:100BA0000101010101010101010101010101010135 +:100BB0000101010101010101010101010101010125 +:100BC0000101010101010101010101010101010115 +:100BD0000101010101010101010101010101010105 +:100BE00001010101010101010101010101010101F5 +:100BF00001010101010101010101010101010101E5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000202020202020202020202020202020284 +:100C50000202020202020202020202020202020274 +:100C60000202020202020202020202020202020264 +:100C70000202020202020202020202020202020254 +:100C80000202020202020202020202020202020244 +:100C90000202020202020202020202020202020234 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000202020202020202020202020202020204 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020202D4 +:100D000002020202020202020202020202020202C3 +:100D100002020202020202020202020202020202B3 +:100D200002020202020202020202020202020202A3 +:100D30000202020202020202020202020202020293 +:100D40000202020202020202020202020202020283 +:100D50000202020202020202020202020202020273 +:100D60000202020202020202020202020202020263 +:100D70000202020202020202020202020202020253 +:100D80000202020202020202020202020202020243 +:100D90000202020202020202020202020202020233 +:100DA0000202020202020202020202020202020223 +:100DB0000202020202020202020202020202020213 +:100DC0000202020202020202020202020202020203 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020202D3 +:100E000002020202020202020202020202020202C2 +:100E100002020202020202020202020202020202B2 +:100E200002020202020202020202020202020202A2 +:100E30000202020202020202020202020202020292 +:100E40000202020202020202020202020202020282 +:100E50000202020202020202020202020202020272 +:100E60000202020202020202020202020202020262 +:100E70000202020202020202020202020202020252 +:100E80000202020202020202020202020202020242 +:100E90000202020202020202020202020202020232 +:100EA0000202020202020202020202020202020222 +:100EB0000202020202020202020202020202020212 +:100EC0000202020202020202020202020202020202 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020202D2 +:100F000002020202020202020202020202020202C1 +:100F100002020202020202020202020202020202B1 +:100F200002020202020202020202020202020202A1 +:100F30000202020202020202020202020202020291 +:100F40000202020202020202020202020202020281 +:100F50000202020202020202020202020202020271 +:100F60000202020202020202020202020202020261 +:100F70000202020202020202020202020202020251 +:100F80000202020202020202020202020202020241 +:100F90000202020202020202020202020202020231 +:100FA0000202020202020202020202020202020221 +:100FB0000202020202020202020202020202020211 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020202D1 +:1010000002020202020202020202020202020202C0 +:1010100002020202020202020202020202020202B0 +:1010200002020202020202020202020202020202A0 +:101030000202020202020202020202020202020290 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000202020202020202020202020202020200 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020202D0 +:1011000002020202020202020202020202020202BF +:1011100002020202020202020202020202020202AF +:10112000020202020202020202020202020202029F +:10113000020202020202020202020202020202028F +:10114000020202020202020202020202020202027F +:10115000020202020202020202020202020202026F +:10116000020202020202020202020202020202025F +:10117000020202020202020202020202020202024F +:10118000020202020202020202020202020202023F +:10119000020202020202020202020202020202022F +:1011A000020202020202020202020202020202021F +:1011B000020202020202020202020202020202020F +:1011C00002020202020202020202020202020202FF +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202020202BE +:1012100002020202020202020202020202020202AE +:10122000020202020202020202020202020202029E +:10123000020202020202020202020202020202028E +:10124000020202020202020202020202020202027E +:10125000020202020202020202020202020202026E +:10126000020202020202020202020202020202025E +:10127000020202020202020202020202020202024E +:10128000020202020202020202020202020202023E +:10129000020202020202020202020202020202022E +:1012A000020202020202020202020202020202021E +:1012B000020202020202020202020202020202020E +:1012C00002020202020202020202020202020202FE +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202020202BD +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202029D +:10133000020202020202020202020202020202028D +:10134000020202020202020202020202020202027D +:10135000020202020202020202020202020202026D +:10136000020202020202020202020202020202025D +:10137000020202020202020202020202020202024D +:10138000020202020202020202020202020202023D +:10139000020202020202020202020202020202022D +:1013A000020202020202020202020202020202021D +:1013B000020202020202020202020202020202020D +:1013C00002020202020202020202020202020202FD +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202020202BC +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202029C +:10143000020202020202020202020202020202028C +:10144000020202020202020202020202020202027C +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020202025C +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A000020202020202020202020202020202021C +:1014B000020202020202020202020202020202020C +:1014C00002020202020202020202020202020202FC +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202020202BB +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202029B +:10153000020202020202020202020202020202028B +:10154000020202020202020202020202020202027B +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020202025B +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A000020202020202020202020202020202021B +:1015B000020202020202020202020202020202020B +:1015C00002020202020202020202020202020202FB +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202029A +:10163000020202020202020202020202020202028A +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000000000000000000019 +:1017D0000000000000000000000000000000000009 +:1017E00000000000000000000000000000000000F9 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000000000000000000000F8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000000000000000000000F5 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000000000000000B4 +:101C300000000000000000000000000000000000A4 +:101C40006300000000000000010101010101010129 +:101C50000101010101010101010101010101010174 +:101C60000101010101010101010101010101010164 +:101C70000101010101010101010101010101010154 +:101C80000101010101010101010101010101010144 +:101C90000101010101010101010101010101010134 +:101CA0000101010101010101010101010101010124 +:101CB0000101010101010101010101010101010114 +:101CC0000101010101010101010101010101010104 +:101CD00001010101010101010101010101010101F4 +:101CE00001010101010101010101010101010101E4 +:101CF00001010101010101010101010101010101D4 +:101D000001010101010101010101010101010101C3 +:101D100001010101010101010101010101010101B3 +:101D200001010101010101010101010101010101A3 +:101D30000101010101010101010101010101010193 +:101D40000101010101010101010101010101010183 +:101D50000101010101010101010101010101010173 +:101D60000101010101010101010101010101010163 +:101D70000101010101010101010101010101010153 +:101D80000101010101010101010101010101010143 +:101D90000101010101010101010101010101010133 +:101DA0000101010101010101010101010101010123 +:101DB0000101010101010101010101010101010113 +:101DC0000101010101010101010101010101010103 +:101DD00001010101010101010101010101010101F3 +:101DE00001010101010101010101010101010101E3 +:101DF00001010101010101010101010101010101D3 +:101E000001010101010101010101010101010101C2 +:101E100001010101010101010101010101010101B2 +:101E200001010101010101010101010101010101A2 +:101E30000101010101010101010101010101010192 +:101E40000101010101010101010101010101010182 +:101E50000101010101010101010101010101010172 +:101E60000101010101010101010101010101010162 +:101E70000101010101010101010101010101010152 +:101E80000101010101010101010101010101010142 +:101E90000101010101010101010101010101010132 +:101EA0000101010101010101010101010101010122 +:101EB0000101010101010101010101010101010112 +:101EC0000101010101010101010101010101010102 +:101ED00001010101010101010101010101010101F2 +:101EE00001010101010101010101010101010101E2 +:101EF00001010101010101010101010101010101D2 +:101F000001010101010101010101010101010101C1 +:101F100001010101010101010101010101010101B1 +:101F200001010101010101010101010101010101A1 +:101F30000101010101010101010101010101010191 +:101F40000101010101010101010101010101010181 +:101F50000101010101010101010101010101010171 +:101F60000101010101010101010101010101010161 +:101F70000101010101010101010101010101010151 +:101F80000101010101010101010101010101010141 +:101F90000101010101010101010101010101010131 +:101FA0000101010101010101010101010101010121 +:101FB0000101010101010101010101010101010111 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00001010101010101010101010101010101E1 +:101FF00001010101010101010101010101010101D1 +:1020000001010101010101010101010101010101C0 +:1020100001010101010101010101010101010101B0 +:1020200001010101010101010101010101010101A0 +:102030000101010101010101010101010101010190 +:102040000101010101010101000000000000000088 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000000000000000010 +:1020D0000000000000000000000000000000000000 +:1020E00000000000000000000000000000000000F0 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00000000000000000000000000000000000FD +:1023E00000000000000000000000000000000000ED +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000000E8 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000000E6 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000004 +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000000E1 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000000FF +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000000FE +:1032D00000000000000000000000000000000000EE +:1032E00000000000000000000000000000000000DE +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000000FD +:1033D00000000000000000000000000000000000ED +:1033E00000000000000000000000000000000000DD +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000000EC +:1034E00000000000000000000000000000000000DC +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:103540000000000000000000010101010101010173 +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A000010101010101010101010101010101010B +:1035B00001010101010101010101010101010101FB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101014A +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A000010101010101010101010101010101010A +:1036B00001010101010101010101010101010101FA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00001010101010101010101010101010101F9 +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00001010101010101010101010101010101F8 +:1038C00001010101010101010101010101010101E8 +:1038D00001010101010101010101010101010101D8 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:10394000010101010101010100000000000000006F +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D4000000000000000000001010101010101016B +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000101010101010101010101010101010103 +:103DB00001010101010101010101010101010101F3 +:103DC00001010101010101010101010101010101E3 +:103DD00001010101010101010101010101010101D3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101010101010101010101B3 +:103E000001010101010101010101010101010101A2 +:103E10000101010101010101010101010101010192 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010172 +:103E40000101010101010101010101010101010162 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000101010101010101010101010101010112 +:103EA0000101010101010101010101010101010102 +:103EB00001010101010101010101010101010101F2 +:103EC00001010101010101010101010101010101E2 +:103ED00001010101010101010101010101010101D2 +:103EE00001010101010101010101010101010101C2 +:103EF00001010101010101010101010101010101B2 +:103F000001010101010101010101010101010101A1 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010171 +:103F40000101010101010101020202020202020259 +:103F50000202020202020202020202020202020241 +:103F60000202020202020202020202020202020231 +:103F70000202020202020202020202020202020221 +:103F80000202020202020202020202020202020211 +:103F90000202020202020202020202020202020201 +:103FA00002020202020202020202020202020202F1 +:103FB00002020202020202020202020202020202E1 +:103FC00002020202020202020202020202020202D1 +:103FD00002020202020202020202020202020202C1 +:103FE00002020202020202020202020202020202B1 +:103FF00002020202020202020202020202020202A1 +:104000000202020202020202020202020202020290 +:104010000202020202020202020202020202020280 +:104020000202020202020202020202020202020270 +:104030000202020202020202020202020202020260 +:104040000202020202020202020202020202020250 +:104050000202020202020202020202020202020240 +:104060000202020202020202020202020202020230 +:104070000202020202020202020202020202020220 +:104080000202020202020202020202020202020210 +:104090000202020202020202020202020202020200 +:1040A00002020202020202020202020202020202F0 +:1040B00002020202020202020202020202020202E0 +:1040C00002020202020202020202020202020202D0 +:1040D00002020202020202020202020202020202C0 +:1040E00002020202020202020202020202020202B0 +:1040F00002020202020202020202020202020202A0 +:10410000020202020202020202020202020202028F +:10411000020202020202020202020202020202027F +:10412000020202020202020202020202020202026F +:10413000020202020202020202020202020202025F +:10414000020202020202020202020202020202024F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F000020202020202020202020202020202029F +:10420000020202020202020202020202020202028E +:10421000020202020202020202020202020202027E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00002020202020202020202020202020202BE +:1042E00002020202020202020202020202020202AE +:1042F000020202020202020202020202020202029E +:10430000020202020202020202020202020202028D +:10431000020202020202020202020202020202027D +:10432000020202020202020202020202020202026D +:10433000020202020202020202020202020202025D +:10434000020202020202020202020202020202024D +:10435000020202020202020202020202020202023D +:10436000020202020202020202020202020202022D +:10437000020202020202020202020202020202021D +:10438000020202020202020202020202020202020D +:1043900002020202020202020202020202020202FD +:1043A00002020202020202020202020202020202ED +:1043B00002020202020202020202020202020202DD +:1043C00002020202020202020202020202020202CD +:1043D00002020202020202020202020202020202BD +:1043E00002020202020202020202020202020202AD +:1043F000020202020202020202020202020202029D +:10440000020202020202020202020202020202028C +:10441000020202020202020202020202020202027C +:10442000020202020202020202020202020202026C +:10443000020202020202020202020202020202025C +:10444000020202020202020202020202020202024C +:10445000020202020202020202020202020202023C +:10446000020202020202020202020202020202022C +:10447000020202020202020202020202020202021C +:10448000020202020202020202020202020202020C +:1044900002020202020202020202020202020202FC +:1044A00002020202020202020202020202020202EC +:1044B00002020202020202020202020202020202DC +:1044C00002020202020202020202020202020202CC +:1044D00002020202020202020202020202020202BC +:1044E00002020202020202020202020202020202AC +:1044F000020202020202020202020202020202029C +:10450000020202020202020202020202020202028B +:10451000020202020202020202020202020202027B +:10452000020202020202020202020202020202026B +:10453000020202020202020202020202020202025B +:10454000020202020202020202020202020202024B +:10455000020202020202020202020202020202023B +:10456000020202020202020202020202020202022B +:10457000020202020202020202020202020202021B +:10458000020202020202020202020202020202020B +:1045900002020202020202020202020202020202FB +:1045A00002020202020202020202020202020202EB +:1045B00002020202020202020202020202020202DB +:1045C00002020202020202020202020202020202CB +:1045D00002020202020202020202020202020202BB +:1045E00002020202020202020202020202020202AB +:1045F000020202020202020202020202020202029B +:10460000020202020202020202020202020202028A +:10461000020202020202020202020202020202027A +:10462000020202020202020202020202020202026A +:10463000020202020202020202020202020202025A +:10464000020202020202020202020202020202024A +:10465000020202020202020202020202020202023A +:10466000020202020202020202020202020202022A +:10467000020202020202020202020202020202021A +:10468000020202020202020202020202020202020A +:1046900002020202020202020202020202020202FA +:1046A00002020202020202020202020202020202EA +:1046B00002020202020202020202020202020202DA +:1046C00002020202020202020202020202020202CA +:1046D00002020202020202020202020202020202BA +:1046E00002020202020202020202020202020202AA +:1046F000020202020202020202020202020202029A +:104700000202020202020202020202020202020289 +:104710000202020202020202020202020202020279 +:104720000202020202020202020202020202020269 +:104730000202020202020202020202020202020259 +:104740000202020202020202020202020202020249 +:104750000202020202020202020202020202020239 +:104760000202020202020202020202020202020229 +:104770000202020202020202020202020202020219 +:104780000202020202020202020202020202020209 +:1047900002020202020202020202020202020202F9 +:1047A00002020202020202020202020202020202E9 +:1047B00002020202020202020202020202020202D9 +:1047C00002020202020202020202020202020202C9 +:1047D00002020202020202020202020202020202B9 +:1047E00002020202020202020202020202020202A9 +:1047F0000202020202020202020202020202020299 +:104800000202020202020202020202020202020288 +:104810000202020202020202020202020202020278 +:104820000202020202020202020202020202020268 +:104830000202020202020202020202020202020258 +:104840000202020202020202020202020202020248 +:104850000202020202020202020202020202020238 +:104860000202020202020202020202020202020228 +:104870000202020202020202020202020202020218 +:104880000202020202020202020202020202020208 +:1048900002020202020202020202020202020202F8 +:1048A00002020202020202020202020202020202E8 +:1048B00002020202020202020202020202020202D8 +:1048C00002020202020202020202020202020202C8 +:1048D00002020202020202020202020202020202B8 +:1048E00002020202020202020202020202020202A8 +:1048F0000202020202020202020202020202020298 +:104900000202020202020202020202020202020287 +:104910000202020202020202020202020202020277 +:104920000202020202020202020202020202020267 +:104930000202020202020202020202020202020257 +:104940000202020202020202000000000000000057 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000010101010101010159 +:104F50000101010101010101010101010101010141 +:104F60000101010101010101010101010101010131 +:104F70000101010101010101010101010101010121 +:104F80000101010101010101010101010101010111 +:104F90000101010101010101010101010101010101 +:104FA00001010101010101010101010101010101F1 +:104FB00001010101010101010101010101010101E1 +:104FC00001010101010101010101010101010101D1 +:104FD00001010101010101010101010101010101C1 +:104FE00001010101010101010101010101010101B1 +:104FF00001010101010101010101010101010101A1 +:105000000101010101010101010101010101010190 +:105010000101010101010101010101010101010180 +:105020000101010101010101010101010101010170 +:105030000101010101010101010101010101010160 +:105040000101010101010101010101010101010150 +:105050000101010101010101010101010101010140 +:105060000101010101010101010101010101010130 +:105070000101010101010101010101010101010120 +:105080000101010101010101010101010101010110 +:105090000101010101010101010101010101010100 +:1050A00001010101010101010101010101010101F0 +:1050B00001010101010101010101010101010101E0 +:1050C00001010101010101010101010101010101D0 +:1050D00001010101010101010101010101010101C0 +:1050E00001010101010101010101010101010101B0 +:1050F00001010101010101010101010101010101A0 +:10510000010101010101010101010101010101018F +:10511000010101010101010101010101010101017F +:10512000010101010101010101010101010101016F +:10513000010101010101010101010101010101015F +:10514000010101010101010101010101010101014F +:10515000010101010101010101010101010101013F +:10516000010101010101010101010101010101012F +:10517000010101010101010101010101010101011F +:10518000010101010101010101010101010101010F +:1051900001010101010101010101010101010101FF +:1051A00001010101010101010101010101010101EF +:1051B00001010101010101010101010101010101DF +:1051C00001010101010101010101010101010101CF +:1051D00001010101010101010101010101010101BF +:1051E00001010101010101010101010101010101AF +:1051F000010101010101010101010101010101019F +:10520000010101010101010101010101010101018E +:10521000010101010101010101010101010101017E +:10522000010101010101010101010101010101016E +:10523000010101010101010101010101010101015E +:10524000010101010101010101010101010101014E +:10525000010101010101010101010101010101013E +:10526000010101010101010101010101010101012E +:10527000010101010101010101010101010101011E +:10528000010101010101010101010101010101010E +:1052900001010101010101010101010101010101FE +:1052A00001010101010101010101010101010101EE +:1052B00001010101010101010101010101010101DE +:1052C00001010101010101010101010101010101CE +:1052D00001010101010101010101010101010101BE +:1052E00001010101010101010101010101010101AE +:1052F000010101010101010101010101010101019E +:10530000010101010101010101010101010101018D +:10531000010101010101010101010101010101017D +:10532000010101010101010101010101010101016D +:10533000010101010101010101010101010101015D +:105340000101010101010101000000000000000055 +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000000CA +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000000000000000000000C9 +:1057E00000000000000000000000000000000000B9 +:1057F00000000000000000000000000000000000A9 +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000000000000000000000C8 +:1058E00000000000000000000000000000000000B8 +:1058F00000000000000000000000000000000000A8 +:105900000000000000000000000000000000000097 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000000000000000000000C7 +:1059E00000000000000000000000000000000000B7 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000000000000000000000000000000000008F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000000000000000000000000000000000008B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000000000000000000000000000000000003B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:10660000000000000000000000000000000000008A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000000000000000000AA +:1066F000000000000000000000000000000000009A +:106700000000000000000000000000000000000089 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000099 +:106800000000000000000000000000000000000088 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000010101010101010140 +:106850000101010101010101010101010101010128 +:106860000101010101010101010101010101010118 +:106870000101010101010101010101010101010108 +:1068800001010101010101010101010101010101F8 +:1068900001010101010101010101010101010101E8 +:1068A00001010101010101010101010101010101D8 +:1068B00001010101010101010101010101010101C8 +:1068C00001010101010101010101010101010101B8 +:1068D00001010101010101010101010101010101A8 +:1068E0000101010101010101010101010101010198 +:1068F0000101010101010101010101010101010188 +:106900000101010101010101010101010101010177 +:106910000101010101010101010101010101010167 +:106920000101010101010101010101010101010157 +:106930000101010101010101010101010101010147 +:106940000101010101010101010101010101010137 +:106950000101010101010101010101010101010127 +:106960000101010101010101010101010101010117 +:106970000101010101010101010101010101010107 +:1069800001010101010101010101010101010101F7 +:1069900001010101010101010101010101010101E7 +:1069A00001010101010101010101010101010101D7 +:1069B00001010101010101010101010101010101C7 +:1069C00001010101010101010101010101010101B7 +:1069D00001010101010101010101010101010101A7 +:1069E0000101010101010101010101010101010197 +:1069F0000101010101010101010101010101010187 +:106A00000101010101010101010101010101010176 +:106A10000101010101010101010101010101010166 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000101010101010101010101010101010136 +:106A50000101010101010101010101010101010126 +:106A60000101010101010101010101010101010116 +:106A70000101010101010101010101010101010106 +:106A800001010101010101010101010101010101F6 +:106A900001010101010101010101010101010101E6 +:106AA00001010101010101010101010101010101D6 +:106AB00001010101010101010101010101010101C6 +:106AC00001010101010101010101010101010101B6 +:106AD00001010101010101010101010101010101A6 +:106AE0000101010101010101010101010101010196 +:106AF0000101010101010101010101010101010186 +:106B00000101010101010101010101010101010175 +:106B10000101010101010101010101010101010165 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000101010101010101010101010101010135 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B70000101010101010101010101010101010105 +:106B800001010101010101010101010101010101F5 +:106B900001010101010101010101010101010101E5 +:106BA00001010101010101010101010101010101D5 +:106BB00001010101010101010101010101010101C5 +:106BC00001010101010101010101010101010101B5 +:106BD00001010101010101010101010101010101A5 +:106BE0000101010101010101010101010101010195 +:106BF0000101010101010101010101010101010185 +:106C00000101010101010101010101010101010174 +:106C10000101010101010101010101010101010164 +:106C20000101010101010101010101010101010154 +:106C30000101010101010101010101010101010144 +:106C4000010101010101010100000000000000003C +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000010101010101010138 +:107050000101010101010101010101010101010120 +:107060000101010101010101010101010101010110 +:107070000101010101010101010101010101010100 +:1070800001010101010101010101010101010101F0 +:1070900001010101010101010101010101010101E0 +:1070A00001010101010101010101010101010101D0 +:1070B00001010101010101010101010101010101C0 +:1070C00001010101010101010101010101010101B0 +:1070D00001010101010101010101010101010101A0 +:1070E0000101010101010101010101010101010190 +:1070F0000101010101010101010101010101010180 +:10710000010101010101010101010101010101016F +:10711000010101010101010101010101010101015F +:10712000010101010101010101010101010101014F +:10713000010101010101010101010101010101013F +:10714000010101010101010101010101010101012F +:10715000010101010101010101010101010101011F +:10716000010101010101010101010101010101010F +:1071700001010101010101010101010101010101FF +:1071800001010101010101010101010101010101EF +:1071900001010101010101010101010101010101DF +:1071A00001010101010101010101010101010101CF +:1071B00001010101010101010101010101010101BF +:1071C00001010101010101010101010101010101AF +:1071D000010101010101010101010101010101019F +:1071E000010101010101010101010101010101018F +:1071F000010101010101010101010101010101017F +:10720000010101010101010101010101010101016E +:10721000010101010101010101010101010101015E +:10722000010101010101010101010101010101014E +:10723000010101010101010101010101010101013E +:107240000101010101010101020202020202020226 +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E000020202020202020202020202020202027E +:1072F000020202020202020202020202020202026E +:10730000020202020202020202020202020202025D +:10731000020202020202020202020202020202024D +:10732000020202020202020202020202020202023D +:10733000020202020202020202020202020202022D +:10734000020202020202020202020202020202021D +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E000020202020202020202020202020202027D +:1073F000020202020202020202020202020202026D +:10740000020202020202020202020202020202025C +:10741000020202020202020202020202020202024C +:10742000020202020202020202020202020202023C +:10743000020202020202020202020202020202022C +:10744000020202020202020202020202020202021C +:10745000020202020202020202020202020202020C +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E000020202020202020202020202020202027C +:1074F000020202020202020202020202020202026C +:10750000020202020202020202020202020202025B +:10751000020202020202020202020202020202024B +:10752000020202020202020202020202020202023B +:10753000020202020202020202020202020202022B +:10754000020202020202020202020202020202021B +:10755000020202020202020202020202020202020B +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E000020202020202020202020202020202027B +:1075F000020202020202020202020202020202026B +:10760000020202020202020202020202020202025A +:10761000020202020202020202020202020202024A +:10762000020202020202020202020202020202023A +:10763000020202020202020202020202020202022A +:10764000020202020202020202020202020202021A +:10765000020202020202020202020202020202020A +:1076600002020202020202020202020202020202FA +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E000020202020202020202020202020202027A +:1076F000020202020202020202020202020202026A +:107700000202020202020202020202020202020259 +:107710000202020202020202020202020202020249 +:107720000202020202020202020202020202020239 +:107730000202020202020202020202020202020229 +:107740000202020202020202020202020202020219 +:107750000202020202020202020202020202020209 +:1077600002020202020202020202020202020202F9 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202020202020202020289 +:1077E0000202020202020202020202020202020279 +:1077F0000202020202020202020202020202020269 +:107800000202020202020202020202020202020258 +:107810000202020202020202020202020202020248 +:107820000202020202020202020202020202020238 +:107830000202020202020202020202020202020228 +:107840000202020202020202020202020202020218 +:107850000202020202020202020202020202020208 +:1078600002020202020202020202020202020202F8 +:1078700002020202020202020202020202020202E8 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C0000202020202020202020202020202020298 +:1078D0000202020202020202020202020202020288 +:1078E0000202020202020202020202020202020278 +:1078F0000202020202020202020202020202020268 +:107900000202020202020202020202020202020257 +:107910000202020202020202020202020202020247 +:107920000202020202020202020202020202020237 +:107930000202020202020202020202020202020227 +:107940000202020202020202020202020202020217 +:107950000202020202020202020202020202020207 +:1079600002020202020202020202020202020202F7 +:1079700002020202020202020202020202020202E7 +:1079800002020202020202020202020202020202D7 +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C0000202020202020202020202020202020297 +:1079D0000202020202020202020202020202020287 +:1079E0000202020202020202020202020202020277 +:1079F0000202020202020202020202020202020267 +:107A00000202020202020202020202020202020256 +:107A10000202020202020202020202020202020246 +:107A20000202020202020202020202020202020236 +:107A30000202020202020202020202020202020226 +:107A40000202020202020202020202020202020216 +:107A50000202020202020202020202020202020206 +:107A600002020202020202020202020202020202F6 +:107A700002020202020202020202020202020202E6 +:107A800002020202020202020202020202020202D6 +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC0000202020202020202020202020202020296 +:107AD0000202020202020202020202020202020286 +:107AE0000202020202020202020202020202020276 +:107AF0000202020202020202020202020202020266 +:107B00000202020202020202020202020202020255 +:107B10000202020202020202020202020202020245 +:107B20000202020202020202020202020202020235 +:107B30000202020202020202020202020202020225 +:107B40000202020202020202020202020202020215 +:107B50000202020202020202020202020202020205 +:107B600002020202020202020202020202020202F5 +:107B700002020202020202020202020202020202E5 +:107B800002020202020202020202020202020202D5 +:107B900002020202020202020202020202020202C5 +:107BA00002020202020202020202020202020202B5 +:107BB00002020202020202020202020202020202A5 +:107BC0000202020202020202020202020202020295 +:107BD0000202020202020202020202020202020285 +:107BE0000202020202020202020202020202020275 +:107BF0000202020202020202020202020202020265 +:107C00000202020202020202020202020202020254 +:107C10000202020202020202020202020202020244 +:107C20000202020202020202020202020202020234 +:107C30000202020202020202020202020202020224 +:107C40000202020202020202000000000000000024 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F400000000000000000005F00000000000000D2 +:107F50000101010101010101010101010101010111 +:107F60000101010101010101010101010101010101 +:107F700001010101010101010101010101010101F1 +:107F800001010101010101010101010101010101E1 +:107F900001010101010101010101010101010101D1 +:107FA00001010101010101010101010101010101C1 +:107FB00001010101010101010101010101010101B1 +:107FC00001010101010101010101010101010101A1 +:107FD0000101010101010101010101010101010191 +:107FE0000101010101010101010101010101010181 +:107FF0000101010101010101010101010101010171 +:108000000101010101010101010101010101010160 +:108010000101010101010101010101010101010150 +:108020000101010101010101010101010101010140 +:108030000101010101010101010101010101010130 +:108040000101010101010101010101010101010120 +:108050000101010101010101010101010101010110 +:108060000101010101010101010101010101010100 +:1080700001010101010101010101010101010101F0 +:1080800001010101010101010101010101010101E0 +:1080900001010101010101010101010101010101D0 +:1080A00001010101010101010101010101010101C0 +:1080B00001010101010101010101010101010101B0 +:1080C00001010101010101010101010101010101A0 +:1080D0000101010101010101010101010101010190 +:1080E0000101010101010101010101010101010180 +:1080F0000101010101010101010101010101010170 +:10810000010101010101010101010101010101015F +:10811000010101010101010101010101010101014F +:10812000010101010101010101010101010101013F +:10813000010101010101010101010101010101012F +:10814000010101010101010101010101010101011F +:10815000010101010101010101010101010101010F +:1081600001010101010101010101010101010101FF +:1081700001010101010101010101010101010101EF +:1081800001010101010101010101010101010101DF +:1081900001010101010101010101010101010101CF +:1081A00001010101010101010101010101010101BF +:1081B00001010101010101010101010101010101AF +:1081C000010101010101010101010101010101019F +:1081D000010101010101010101010101010101018F +:1081E000010101010101010101010101010101017F +:1081F000010101010101010101010101010101016F +:10820000010101010101010101010101010101015E +:10821000010101010101010101010101010101014E +:10822000010101010101010101010101010101013E +:10823000010101010101010101010101010101012E +:10824000010101010101010101010101010101011E +:10825000010101010101010101010101010101010E +:1082600001010101010101010101010101010101FE +:1082700001010101010101010101010101010101EE +:1082800001010101010101010101010101010101DE +:1082900001010101010101010101010101010101CE +:1082A00001010101010101010101010101010101BE +:1082B00001010101010101010101010101010101AE +:1082C000010101010101010101010101010101019E +:1082D000010101010101010101010101010101018E +:1082E000010101010101010101010101010101017E +:1082F000010101010101010101010101010101016E +:10830000010101010101010101010101010101015D +:10831000010101010101010101010101010101014D +:10832000010101010101010101010101010101013D +:10833000010101010101010101010101010101012D +:10834000010101010101010101010101010101011D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D000000000000000000000000000000000008B +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:10960000000000000000000000000000000000005A +:10961000000000000000000000000000000000004A +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C000000000000000000000000000000000009A +:1096D000000000000000000000000000000000008A +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000049 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000099 +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:1098500001010101010101010101010101010101F8 +:1098600001010101010101010101010101010101E8 +:1098700001010101010101010101010101010101D8 +:1098800001010101010101010101010101010101C8 +:1098900001010101010101010101010101010101B8 +:1098A00001010101010101010101010101010101A8 +:1098B0000101010101010101010101010101010198 +:1098C0000101010101010101010101010101010188 +:1098D0000101010101010101010101010101010178 +:1098E0000101010101010101010101010101010168 +:1098F0000101010101010101010101010101010158 +:109900000101010101010101010101010101010147 +:109910000101010101010101010101010101010137 +:109920000101010101010101010101010101010127 +:109930000101010101010101010101010101010117 +:109940000101010101010101010101010101010107 +:1099500001010101010101010101010101010101F7 +:1099600001010101010101010101010101010101E7 +:1099700001010101010101010101010101010101D7 +:1099800001010101010101010101010101010101C7 +:1099900001010101010101010101010101010101B7 +:1099A00001010101010101010101010101010101A7 +:1099B0000101010101010101010101010101010197 +:1099C0000101010101010101010101010101010187 +:1099D0000101010101010101010101010101010177 +:1099E0000101010101010101010101010101010167 +:1099F0000101010101010101010101010101010157 +:109A00000101010101010101010101010101010146 +:109A10000101010101010101010101010101010136 +:109A20000101010101010101010101010101010126 +:109A30000101010101010101010101010101010116 +:109A40000101010101010101010101010101010106 +:109A500001010101010101010101010101010101F6 +:109A600001010101010101010101010101010101E6 +:109A700001010101010101010101010101010101D6 +:109A800001010101010101010101010101010101C6 +:109A900001010101010101010101010101010101B6 +:109AA00001010101010101010101010101010101A6 +:109AB0000101010101010101010101010101010196 +:109AC0000101010101010101010101010101010186 +:109AD0000101010101010101010101010101010176 +:109AE0000101010101010101010101010101010166 +:109AF0000101010101010101010101010101010156 +:109B00000101010101010101010101010101010145 +:109B10000101010101010101010101010101010135 +:109B20000101010101010101010101010101010125 +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010101010101010105 +:109B500001010101010101010101010101010101F5 +:109B600001010101010101010101010101010101E5 +:109B700001010101010101010101010101010101D5 +:109B800001010101010101010101010101010101C5 +:109B900001010101010101010101010101010101B5 +:109BA00001010101010101010101010101010101A5 +:109BB0000101010101010101010101010101010195 +:109BC0000101010101010101010101010101010185 +:109BD0000101010101010101010101010101010175 +:109BE0000101010101010101010101010101010165 +:109BF0000101010101010101010101010101010155 +:109C00000101010101010101010101010101010144 +:109C10000101010101010101010101010101010134 +:109C20000101010101010101010101010101010124 +:109C30000101010101010101010101010101010114 +:109C40000101010101010101010101010101010104 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010101010101010101B0 +:10A0A00001010101010101010101010101010101A0 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101010101010101010170 +:10A0E0000101010101010101010101010101010160 +:10A0F0000101010101010101010101010101010150 +:10A10000010101010101010101010101010101013F +:10A11000010101010101010101010101010101012F +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500002020202020202020202020202020202DF +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A19000020202020202020202020202020202029F +:10A1A000020202020202020202020202020202028F +:10A1B000020202020202020202020202020202027F +:10A1C000020202020202020202020202020202026F +:10A1D000020202020202020202020202020202025F +:10A1E000020202020202020202020202020202024F +:10A1F000020202020202020202020202020202023F +:10A20000020202020202020202020202020202022E +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202020E +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202027E +:10A2C000020202020202020202020202020202026E +:10A2D000020202020202020202020202020202025E +:10A2E000020202020202020202020202020202024E +:10A2F000020202020202020202020202020202023E +:10A30000020202020202020202020202020202022D +:10A31000020202020202020202020202020202021D +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202024D +:10A3F000020202020202020202020202020202023D +:10A40000020202020202020202020202020202022C +:10A41000020202020202020202020202020202021C +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202027C +:10A4C000020202020202020202020202020202026C +:10A4D000020202020202020202020202020202025C +:10A4E000020202020202020202020202020202024C +:10A4F000020202020202020202020202020202023C +:10A50000020202020202020202020202020202022B +:10A51000020202020202020202020202020202021B +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E000020202020202020202020202020202024B +:10A5F000020202020202020202020202020202023B +:10A60000020202020202020202020202020202022A +:10A61000020202020202020202020202020202021A +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020202020202FA +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020202020202020202DA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E000020202020202020202020202020202024A +:10A6F000020202020202020202020202020202023A +:10A700000202020202020202020202020202020229 +:10A710000202020202020202020202020202020219 +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202020202F9 +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000202020202020202020202020202020269 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000202020202020202020202020202020239 +:10A800000202020202020202020202020202020228 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202020202F8 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020202A8 +:10A890000202020202020202020202020202020298 +:10A8A0000202020202020202020202020202020288 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202020227 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202020202F7 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000202020202020202020202020202020267 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202020202F6 +:10AA400002020202020202020202020202020202E6 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500001010101010101010101010101010101E0 +:10B0600001010101010101010101010101010101D0 +:10B0700001010101010101010101010101010101C0 +:10B0800001010101010101010101010101010101B0 +:10B0900001010101010101010101010101010101A0 +:10B0A0000101010101010101010101010101010190 +:10B0B0000101010101010101010101010101010180 +:10B0C0000101010101010101010101010101010170 +:10B0D0000101010101010101010101010101010160 +:10B0E0000101010101010101010101010101010150 +:10B0F0000101010101010101010101010101010140 +:10B10000010101010101010101010101010101012F +:10B11000010101010101010101010101010101011F +:10B12000010101010101010101010101010101010F +:10B1300001010101010101010101010101010101FF +:10B1400001010101010101010101010101010101EF +:10B1500001010101010101010101010101010101DF +:10B1600001010101010101010101010101010101CF +:10B1700001010101010101010101010101010101BF +:10B1800001010101010101010101010101010101AF +:10B19000010101010101010101010101010101019F +:10B1A000010101010101010101010101010101018F +:10B1B000010101010101010101010101010101017F +:10B1C000010101010101010101010101010101016F +:10B1D000010101010101010101010101010101015F +:10B1E000010101010101010101010101010101014F +:10B1F000010101010101010101010101010101013F +:10B20000010101010101010101010101010101012E +:10B21000010101010101010101010101010101011E +:10B22000010101010101010101010101010101010E +:10B2300001010101010101010101010101010101FE +:10B2400001010101010101010101010101010101EE +:10B2500001010101010101010101010101010101DE +:10B2600001010101010101010101010101010101CE +:10B2700001010101010101010101010101010101BE +:10B2800001010101010101010101010101010101AE +:10B29000010101010101010101010101010101019E +:10B2A000010101010101010101010101010101018E +:10B2B000010101010101010101010101010101017E +:10B2C000010101010101010101010101010101016E +:10B2D000010101010101010101010101010101015E +:10B2E000010101010101010101010101010101014E +:10B2F000010101010101010101010101010101013E +:10B30000010101010101010101010101010101012D +:10B31000010101010101010101010101010101011D +:10B32000010101010101010101010101010101010D +:10B3300001010101010101010101010101010101FD +:10B3400001010101010101010101010101010101ED +:10B3500001010101010101010101010101010101DD +:10B3600001010101010101010101010101010101CD +:10B3700001010101010101010101010101010101BD +:10B3800001010101010101010101010101010101AD +:10B39000010101010101010101010101010101019D +:10B3A000010101010101010101010101010101018D +:10B3B000010101010101010101010101010101017D +:10B3C000010101010101010101010101010101016D +:10B3D000010101010101010101010101010101015D +:10B3E000010101010101010101010101010101014D +:10B3F000010101010101010101010101010101013D +:10B40000010101010101010101010101010101012C +:10B41000010101010101010101010101010101011C +:10B42000010101010101010101010101010101010C +:10B4300001010101010101010101010101010101FC +:10B4400001010101010101010101010101010101EC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000000000000000000000000000000000002B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D000000000000000000000000000000000005E +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000000000000000000000000000000000001D +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500001010101010101010101010101010101C7 +:10C9600001010101010101010101010101010101B7 +:10C9700001010101010101010101010101010101A7 +:10C980000101010101010101010101010101010197 +:10C990000101010101010101010101010101010187 +:10C9A0000101010101010101010101010101010177 +:10C9B0000101010101010101010101010101010167 +:10C9C0000101010101010101010101010101010157 +:10C9D0000101010101010101010101010101010147 +:10C9E0000101010101010101010101010101010137 +:10C9F0000101010101010101010101010101010127 +:10CA00000101010101010101010101010101010116 +:10CA10000101010101010101010101010101010106 +:10CA200001010101010101010101010101010101F6 +:10CA300001010101010101010101010101010101E6 +:10CA400001010101010101010101010101010101D6 +:10CA500001010101010101010101010101010101C6 +:10CA600001010101010101010101010101010101B6 +:10CA700001010101010101010101010101010101A6 +:10CA80000101010101010101010101010101010196 +:10CA90000101010101010101010101010101010186 +:10CAA0000101010101010101010101010101010176 +:10CAB0000101010101010101010101010101010166 +:10CAC0000101010101010101010101010101010156 +:10CAD0000101010101010101010101010101010146 +:10CAE0000101010101010101010101010101010136 +:10CAF0000101010101010101010101010101010126 +:10CB00000101010101010101010101010101010115 +:10CB10000101010101010101010101010101010105 +:10CB200001010101010101010101010101010101F5 +:10CB300001010101010101010101010101010101E5 +:10CB400001010101010101010101010101010101D5 +:10CB500001010101010101010101010101010101C5 +:10CB600001010101010101010101010101010101B5 +:10CB700001010101010101010101010101010101A5 +:10CB80000101010101010101010101010101010195 +:10CB90000101010101010101010101010101010185 +:10CBA0000101010101010101010101010101010175 +:10CBB0000101010101010101010101010101010165 +:10CBC0000101010101010101010101010101010155 +:10CBD0000101010101010101010101010101010145 +:10CBE0000101010101010101010101010101010135 +:10CBF0000101010101010101010101010101010125 +:10CC00000101010101010101010101010101010114 +:10CC10000101010101010101010101010101010104 +:10CC200001010101010101010101010101010101F4 +:10CC300001010101010101010101010101010101E4 +:10CC400001010101010101010101010101010101D4 +:10CC500001010101010101010101010101010101C4 +:10CC600001010101010101010101010101010101B4 +:10CC700001010101010101010101010101010101A4 +:10CC80000101010101010101010101010101010194 +:10CC90000101010101010101010101010101010184 +:10CCA0000101010101010101010101010101010174 +:10CCB0000101010101010101010101010101010164 +:10CCC0000101010101010101010101010101010154 +:10CCD0000101010101010101010101010101010144 +:10CCE0000101010101010101010101010101010134 +:10CCF0000101010101010101010101010101010124 +:10CD00000101010101010101010101010101010113 +:10CD10000101010101010101010101010101010103 +:10CD200001010101010101010101010101010101F3 +:10CD300001010101010101010101010101010101E3 +:10CD400001010101010101010101010101010101D3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000010101010101010101010101010101014F +:10D1D000010101010101010101010101010101013F +:10D1E000010101010101010101010101010101012F +:10D1F000010101010101010101010101010101011F +:10D20000010101010101010101010101010101010E +:10D2100001010101010101010101010101010101FE +:10D2200001010101010101010101010101010101EE +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500002020202020202020202020202020202AE +:10D26000020202020202020202020202020202029E +:10D27000020202020202020202020202020202028E +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B000020202020202020202020202020202024E +:10D2C000020202020202020202020202020202023E +:10D2D000020202020202020202020202020202022E +:10D2E000020202020202020202020202020202021E +:10D2F000020202020202020202020202020202020E +:10D3000002020202020202020202020202020202FD +:10D3100002020202020202020202020202020202ED +:10D3200002020202020202020202020202020202DD +:10D3300002020202020202020202020202020202CD +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D36000020202020202020202020202020202029D +:10D37000020202020202020202020202020202028D +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020202020202020202020202025D +:10D3B000020202020202020202020202020202024D +:10D3C000020202020202020202020202020202023D +:10D3D000020202020202020202020202020202022D +:10D3E000020202020202020202020202020202021D +:10D3F000020202020202020202020202020202020D +:10D4000002020202020202020202020202020202FC +:10D4100002020202020202020202020202020202EC +:10D4200002020202020202020202020202020202DC +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202020202020202025C +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020202020202020202023C +:10D4D000020202020202020202020202020202022C +:10D4E000020202020202020202020202020202021C +:10D4F000020202020202020202020202020202020C +:10D5000002020202020202020202020202020202FB +:10D5100002020202020202020202020202020202EB +:10D5200002020202020202020202020202020202DB +:10D5300002020202020202020202020202020202CB +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020202020202AB +:10D56000020202020202020202020202020202029B +:10D57000020202020202020202020202020202028B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020202020202026B +:10D5A000020202020202020202020202020202025B +:10D5B000020202020202020202020202020202024B +:10D5C000020202020202020202020202020202023B +:10D5D000020202020202020202020202020202022B +:10D5E000020202020202020202020202020202021B +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D6100002020202020202020202020202020202EA +:10D6200002020202020202020202020202020202DA +:10D6300002020202020202020202020202020202CA +:10D6400002020202020202020202020202020202BA +:10D6500002020202020202020202020202020202AA +:10D66000020202020202020202020202020202029A +:10D67000020202020202020202020202020202028A +:10D68000020202020202020202020202020202027A +:10D69000020202020202020202020202020202026A +:10D6A000020202020202020202020202020202025A +:10D6B000020202020202020202020202020202024A +:10D6C000020202020202020202020202020202023A +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F000020202020202020202020202020202020A +:10D7000002020202020202020202020202020202F9 +:10D7100002020202020202020202020202020202E9 +:10D7200002020202020202020202020202020202D9 +:10D7300002020202020202020202020202020202C9 +:10D7400002020202020202020202020202020202B9 +:10D7500002020202020202020202020202020202A9 +:10D760000202020202020202020202020202020299 +:10D770000202020202020202020202020202020289 +:10D780000202020202020202020202020202020279 +:10D790000202020202020202020202020202020269 +:10D7A0000202020202020202020202020202020259 +:10D7B0000202020202020202020202020202020249 +:10D7C0000202020202020202020202020202020239 +:10D7D0000202020202020202020202020202020229 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202020202020202020209 +:10D8000002020202020202020202020202020202F8 +:10D8100002020202020202020202020202020202E8 +:10D8200002020202020202020202020202020202D8 +:10D8300002020202020202020202020202020202C8 +:10D8400002020202020202020202020202020202B8 +:10D8500002020202020202020202020202020202A8 +:10D860000202020202020202020202020202020298 +:10D870000202020202020202020202020202020288 +:10D880000202020202020202020202020202020278 +:10D890000202020202020202020202020202020268 +:10D8A0000202020202020202020202020202020258 +:10D8B0000202020202020202020202020202020248 +:10D8C0000202020202020202020202020202020238 +:10D8D0000202020202020202020202020202020228 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202020202020202020208 +:10D9000002020202020202020202020202020202F7 +:10D9100002020202020202020202020202020202E7 +:10D9200002020202020202020202020202020202D7 +:10D9300002020202020202020202020202020202C7 +:10D9400002020202020202020202020202020202B7 +:10D9500002020202020202020202020202020202A7 +:10D960000202020202020202020202020202020297 +:10D970000202020202020202020202020202020287 +:10D980000202020202020202020202020202020277 +:10D990000202020202020202020202020202020267 +:10D9A0000202020202020202020202020202020257 +:10D9B0000202020202020202020202020202020247 +:10D9C0000202020202020202020202020202020237 +:10D9D0000202020202020202020202020202020227 +:10D9E0000202020202020202020202020202020217 +:10D9F0000202020202020202020202020202020207 +:10DA000002020202020202020202020202020202F6 +:10DA100002020202020202020202020202020202E6 +:10DA200002020202020202020202020202020202D6 +:10DA300002020202020202020202020202020202C6 +:10DA400002020202020202020202020202020202B6 +:10DA500002020202020202020202020202020202A6 +:10DA60000202020202020202020202020202020296 +:10DA70000202020202020202020202020202020286 +:10DA80000202020202020202020202020202020276 +:10DA90000202020202020202020202020202020266 +:10DAA0000202020202020202020202020202020256 +:10DAB0000202020202020202020202020202020246 +:10DAC0000202020202020202020202020202020236 +:10DAD0000202020202020202020202020202020226 +:10DAE0000202020202020202020202020202020216 +:10DAF0000202020202020202020202020202020206 +:10DB000002020202020202020202020202020202F5 +:10DB100002020202020202020202020202020202E5 +:10DB200002020202020202020202020202020202D5 +:10DB300002020202020202020202020202020202C5 +:10DB400002020202020202020202020202020202B5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500088DE06000000000090FE060000000000C2 +:10DE60009818070000000000A02F07000000000025 +:10DE7000A848070000000000B05D07000000000097 +:10DE8000B870070000000000C0800700000000001C +:10DE9000C890070000000000D0A0070000000000AC +:10DEA000D8AF070000000000E0BA07000000000043 +:10DEB000E8C3070000000000F0D0070000000000E9 +:10DEC000F8DD070000000000200000000000000056 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000100000000000000000000000000000050 +:10DFD0000000000000000000000000000000000041 +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C000020000000000000000000000000000004E +:10E0D000000000000000000000000000000000013F +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000020000000000000000000000000000004D +:10E1D000000000000000000000000000000000013E +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000020000000000000000000000000000004C +:10E2D000000000000000000000000000000000013D +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C0000202010000000000000000000000000048 +:10E3D000000000000000000000000000000000013C +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C0000202020000000000000000000000000046 +:10E4D000000000000000000000000000000001013A +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C0000202020000000000000000000000000045 +:10E5D0000000000000000000000000000001010138 +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C0000202020100000000000000000000000043 +:10E6D0000000000000000000000000000001010137 +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000202020201000000000000000000000040 +:10E7D0000000000000000000000000000101010135 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C000020202020201000000000000000000003D +:10E8D0000000000000000000000000010101010133 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E9600000000000000000000000000000000000A7 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C000020202020201000000000000000000003C +:10E9D0000000000000000000000000010101010132 +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000202020202020101000000000000000038 +:10EAD0000000000000000000000001010101010130 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000202020202020101000000000000000037 +:10EBD000000000000000000000010101010101012E +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000202020202020201000000000000000035 +:10ECD000000000000000000000010101010101012D +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000202020202020202000000000000000033 +:10EDD000000000000000000000010101010101012C +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000202020202020202000000000000000032 +:10EED0000000000000000001010101010101010129 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000000000000000000F1 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF600000000000000000000000000000000000A1 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000202020202020202000100000000000030 +:10EFD0000000000000000001010101010101010128 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C000020202020202020202010100000000002C +:10F0D0000000000000000101010101010101010126 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000020202020202020202020100000000002A +:10F1D0000000000000000101010101010101010125 +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C0000202020202020202020202010000000027 +:10F2D0000000000000010101010101010101010123 +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C0000202020202020202020202010000000026 +:10F3D0000000000000010101010101010101010122 +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C0000202020202020202020202020000000024 +:10F4D0000000000000010101010101010101010121 +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C0000202020202020202020202020101000021 +:10F5D000000000000101010101010101010101011F +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000020202020202020202020202020100001F +:10F6D000000000010101010101010101010101011D +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C000020202020202020202020202020200001D +:10F7D000000000010101010101010101010101011C +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C000020202020202020202020202020201001B +:10F8D000000000010101010101010101010101011B +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000202020202020202020202020202020019 +:10F9D0000000010101010101010101010101010119 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000000000000000000000000000000000000F6 +:10FA100000000000000000000000000000000000E6 +:10FA200000000000000000000000000000000000D6 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC0000202020202020202020202020202020018 +:10FAD0000000010101010101010101010101010118 +:10FAE0000000000000000000000000000000000016 +:10FAF0000000000000000000000000000000000006 +:10FB000000000000000000000000000000000000F5 +:10FB100000000000000000000000000000000000E5 +:10FB200000000000000000000000000000000000D5 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000055 +:10FBB0000000000000000000000000000000000045 +:10FBC0000202020202020202020202020202020017 +:10FBD0000001010101010101010101010101010116 +:10FBE0000000000000000000000000000000000015 +:10FBF0000000000000000000000000000000000005 +:10FC000000000000000000000000000000000000F4 +:10FC100000000000000000000000000000000000E4 +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000202020202020202020202020202020016 +:10FCD0000001010101010101010101010101010115 +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000004 +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC0000202020202020202020202020202020015 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0001A00000000000000000000000000000008 +:10FEE0000000000000000001000000000000000011 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC000000000000000000002000000000000002F +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000001000000000000000010 +:10FFF0000000000000000000000000000000000001 +:0200000270008C +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C000000000000000000002000000000000002E +:1000D0000000000000000000000000000000000020 +:1000E000000000000000010100000000000000000E +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000000000000000000000CF +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000000000000000000002020000000000002B +:1001D000000000000000000000000000000000001F +:1001E000000000000000010100000000000000000D +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C0000000000000000000020201010000000028 +:1002D000000000000000000000000000000000001E +:1002E000000000000001010100000000000000000B +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C0000000000000000000020202010000000026 +:1003D000000000000000000000000000000000001D +:1003E000000000000001010100000000000000000A +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C0000000000000000000020202020000000024 +:1004D000000000000000000000000000000000001C +:1004E0000000000101010101000000000000000007 +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C0000000000000000000020202020100000022 +:1005D000000000000000000000000000000000001B +:1005E0000000000101010101000000000000000006 +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C0000000000000000000020202020200000020 +:1006D000000000000000000000000000000000001A +:1006E0000000000101010101000000000000000005 +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C000000000000000000002020202020100001E +:1007D0000000000000000000000000000000000019 +:1007E0000000010101010101000000000000000003 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C000000000000000000002020202020200001C +:1008D0000000000000000000000000000000000018 +:1008E0000001010101010101000000000000000001 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000020202020202010119 +:1009D0000000000000000000000000000000000116 +:1009E00001010101010101010000000000000000FF +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000020202020202020117 +:100AD0000000000000000000000000000000000115 +:100AE00001010101010101010000000000000000FE +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000020202020202020215 +:100BD0000000000000000000000000000000010113 +:100BE00001010101010101010000000000000000FD +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000000000000000000000E4 +:100C100000000000000000000000000000000000D4 +:100C200000000000000000000000000000000000C4 +:100C300000000000000000000000000000000000B4 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000020202020202020214 +:100CD0000000000000000000000000000000010112 +:100CE00001010101010101010000000000000000FC +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000000E3 +:100D100000000000000000000000000000000000D3 +:100D200000000000000000000000000000000000C3 +:100D300000000000000000000000000000000000B3 +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000000000000000000000073 +:100D80000000000000000000000000000000000063 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000020202020202020213 +:100DD000020000000000000000000000000101010E +:100DE00001010101010101010000000000000000FB +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000000000000000000000D2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000020202020202020212 +:100ED000020200010000000000000000000101010A +:100EE00001010101010101010000000000000000FA +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000020202020202020211 +:100FD0000202020100000000000000000101010106 +:100FE00001010101010101010000000000000000F9 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000020202020202020210 +:1010D0000202020200010100000000010101010101 +:1010E00001010101010101010000000000000000F8 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000002020202020202020F +:1011D0000202020200010100000000010101010100 +:1011E00001010101010101010000000000000000F7 +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000002020202020202020E +:1012D00002020202020201000000010101010101FB +:1012E00001010101010101010000000000000000F6 +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C000000000000000000002020202020202020D +:1013D00002020202020202000000010101010101F9 +:1013E00001010101010101010000000000000000F5 +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C000000000000000000002020202020202020C +:1014D00002020202020202000000010101010101F8 +:1014E00001010101010101010000000000000000F4 +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C000000000000000000002020202020202020B +:1015D00002020202020202000001010101010101F6 +:1015E00001010101010101010000000000000000F3 +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000002020202020202020A +:1016D00002020202020202000001010101010101F5 +:1016E00001010101010101010000000000000000F2 +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000020202020202020209 +:1017D00002020202020202000000000000000000FB +:1017E00000000000000000000000000000000000F9 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D00000000000000000001700000000000000F1 +:1018E00000000000000000000000000000000001F7 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D0000201010000000000000000000000000003 +:1019E00000000000000000000000000000000001F6 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD00002020101010000000000000000000000FF +:101AE00000000000000000000000000000000101F4 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000000000000000B5 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD00002020201010000000000000000000000FD +:101BE00000000000000000000000000000000101F3 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000000000000000B4 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000000000000000000000000000054 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000000000000000000000034 +:101CB0000000000000000000000000000000000024 +:101CC0000000000000000000000000000000000014 +:101CD00002020201010000000000000000000000FC +:101CE00000000000000000000000000000010101F1 +:101CF00000000000000000000000000000000000E4 +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000000C3 +:101D200000000000000000000000000000000000B3 +:101D300000000000000000000000000000000000A3 +:101D40000000000000000000000000000000000093 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000073 +:101D70000000000000000000000000000000000063 +:101D80000000000000000000000000000000000053 +:101D90000000000000000000000000000000000043 +:101DA0000000000000000000000000000000000033 +:101DB0000000000000000000000000000000000023 +:101DC0000000000000000000000000000000000013 +:101DD00002020202010000000000000000000000FA +:101DE00000000000000000000000000101010101EE +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000000000000000000B2 +:101E300000000000000000000000000000000000A2 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000000000000000000022 +:101EC0000000000000000000000000000000000012 +:101ED00002020202020000000000000000000000F8 +:101EE00000000000000000000000000101010101ED +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000000000000000000B1 +:101F300000000000000000000000000000000000A1 +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F80000000000000000000000000000000000051 +:101F90000000000000000000000000000000000041 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000000000000000000021 +:101FC0000000000000000000000000000000000011 +:101FD00002020202020000000000000000000000F7 +:101FE00000000000000000000000010101010101EB +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000000000000000000B0 +:1020300000000000000000000000000000000000A0 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000000000000000010 +:1020D00002020202020100000000000000000000F5 +:1020E00000000000000000000000010101010101EA +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000000000000000000AF +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000000000000005F +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C000000000000000000000000000000000000F +:1021D00002020202020201000000000000000000F2 +:1021E00000000000000000000001010101010101E8 +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000000000000000000AE +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000000000000000005E +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C000000000000000000000000000000000000E +:1022D00002020202020202000000000000000000F0 +:1022E00000000000000000000101010101010101E6 +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000000000000000000AD +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000000000000000005D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C000000000000000000000000000000000000D +:1023D00002020202020202000000000000000000EF +:1023E00000000000000000010101010101010101E4 +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000000000000000000AC +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000000000000000005C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C000000000000000000000000000000000000C +:1024D00002020202020202020000000100000000EB +:1024E00000000000000001010101010101010101E2 +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:10257000000000000000000000000000000000005B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C000000000000000000000000000000000000B +:1025D00002020202020202020200000100000000E8 +:1025E00000000000010101010101010101010101DF +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:10267000000000000000000000000000000000005A +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C000000000000000000000000000000000000A +:1026D00002020202020202020202010100000000E4 +:1026E00000000000010101010101010101010101DE +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000000000000000000059 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000000000000000000009 +:1027D00002020202020202020202020200000000E1 +:1027E00000000001010101010101010101010101DC +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:1028200000000000000000000000000000000000A8 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000000000000000000008 +:1028D00002020202020202020202020201000000DF +:1028E00000000001010101010101010101010101DB +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:1029200000000000000000000000000000000000A7 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00002020202020202020202020202010100DB +:1029E00000000001010101010101010101010101DA +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A200000000000000000000000000000000000A6 +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A70000000000000000000000000000000000056 +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00002020202020202020202020202020100D9 +:102AE00000000101010101010101010101010101D8 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B200000000000000000000000000000000000A5 +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B70000000000000000000000000000000000055 +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00002020202020202020202020202020200D7 +:102BE00000000101010101010101010101010101D7 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C200000000000000000000000000000000000A4 +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000000000000000000054 +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC0000000000000000000000000000000000004 +:102CD00002020202020202020202020202020200D6 +:102CE00000010101010101010101010101010101D5 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D200000000000000000000000000000000000A3 +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000000000000000000053 +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC0000000000000000000000000000000000003 +:102DD00002020202020202020202020202020200D5 +:102DE00000010101010101010101010101010101D4 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000000000000000000052 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC0000000000000000000000000000000000002 +:102ED00002020202020202020202020202020200D4 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00019000000000000000000000000000000C8 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000000000000A0 +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000100000000000000EF +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000000000000000000009F +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000000FF +:1031D00000000000000000000200000000000000ED +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000010000000000000000CE +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000000000000000000009E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000000FE +:1032D00000000000000000000200000000000000EC +:1032E00000000000000000000000000000000000DE +:1032F00000000000000001010000000000000000CC +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000000FD +:1033D00000000000000000000200000000000000EB +:1033E00000000000000000000000000000000000DD +:1033F00000000000000101010000000000000000CA +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000201000100000000E8 +:1034E00000000000000000000000000000000000DC +:1034F00000000000010101010000000000000000C8 +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000000202000100000000E6 +:1035E00000000000000000000000000000000000DB +:1035F00000000000010101010000000000000000C7 +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000202000100000000E5 +:1036E00000000000000000000000000000000000DA +:1036F00000000001010101010000000000000000C5 +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000202000100000000E4 +:1037E00000000000000000000000000000000000D9 +:1037F00000000101010101010000000000000000C3 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000202020201000000DF +:1038E00000000000000000000000000000000000D8 +:1038F00000010101010101010000000000000000C1 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000202020201000000DE +:1039E00000000000000000000000000000000001D6 +:1039F00001010101010101010000000000000000BF +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000202020202010000DB +:103AE00000000000000000000000000000000001D5 +:103AF00001010101010101010000000000000000BE +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000202020202010000DA +:103BE00000000000000000000000000000010101D2 +:103BF00001010101010101010000000000000000BD +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000202020202020001D7 +:103CE00000000000000000000000000000010101D1 +:103CF00001010101010101010000000000000000BC +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000202020202020001D6 +:103DE00000000000000000000000000101010101CE +:103DF00001010101010101010000000000000000BB +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000202020202020202D2 +:103EE00000000000000000000000000101010101CD +:103EF00001010101010101010000000000000000BA +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000202020202020202D1 +:103FE00000000000000000000000000101010101CC +:103FF00001010101010101010000000000000000B9 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000202020202020202D0 +:1040E00002000000000000000000000101010101C9 +:1040F00001010101010101010000000000000000B8 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000202020202020202CF +:1041E00002020000010001000000010101010101C3 +:1041F00001010101010101010000000000000000B7 +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000202020202020202CE +:1042E00002020200010101000000010101010101BF +:1042F00001010101010101010000000000000000B6 +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000202020202020202CD +:1043E00002020202020101000001010101010101BA +:1043F00001010101010101010000000000000000B5 +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000202020202020202CC +:1044E00002020202020202000001010101010101B7 +:1044F00001010101010101010000000000000000B4 +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000202020202020202CB +:1045E00002020202020202000001010101010101B6 +:1045F00001010101010101010000000000000000B3 +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000202020202020202CA +:1046E00002020202020202000001010101010101B5 +:1046F00001010101010101010000000000000000B2 +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000202020202020202C9 +:1047E00002020202020202000000000000000000BB +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000001500000000000000B3 +:1048F00000000000000000000000000000000101B6 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00002000000000000000000000000000000C5 +:1049F00000000000000000000000000000000101B5 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00002000000000000000000000000000000C4 +:104AF00000000000000000000000000000010101B3 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00002000000000000000000000000000000C3 +:104BF00000000000000000000000000000010101B2 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00002020000000000000000000000000000C0 +:104CF00000000000000000000000000101010101AF +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00002020000000000000000000000000000BF +:104DF00000000000000000000000010101010101AD +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00002020000000000000000000000000000BE +:104EF00000000000000000000001010101010101AB +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00002020200000000000000000000000100BA +:104FF00000000000000000000101010101010101A9 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00002020200000000000000000000000100B9 +:1050F00000000000000000010101010101010101A7 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00002020202000000000000000000000100B6 +:1051F00000000000000001010101010101010101A5 +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00002020202020000000000000000000100B3 +:1052F00000000000000101010101010101010101A3 +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00002020202020200000000000000000100B0 +:1053F00000000000010101010101010101010101A1 +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00002020202020202000000000000000100AD +:1054F000000000010101010101010101010101019F +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00002020202020202020000000000000100AA +:1055F000000000010101010101010101010101019E +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000000CA +:1056E00002020202020202020200000000000200A6 +:1056F000000001010101010101010101010101019C +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000000000000000000000C9 +:1057E00002020202020202020202000100010200A1 +:1057F000000001010101010101010101010101019B +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000000000000000000000C8 +:1058E000020202020202020202020202000102009D +:1058F000000001010101010101010101010101019A +:105900000000000000000000000000000000000097 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000000000000000000000C7 +:1059E0000202020202020202020202020202020099 +:1059F0000001010101010101010101010101010198 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE0000202020202020202020202020202020098 +:105AF0000001010101010101010101010101010197 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE0000202020202020202020202020202020097 +:105BF0000001010101010101010101010101010196 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE0000202020202020202020202020202020096 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF0001300000000000000000000000000000090 +:105E00000000000000000101000000000000000090 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000200010000000000AF +:105EF00000000000000000000000000000000000A2 +:105F0000000000000001010100000000000000008E +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000201010000000000AD +:105FF00000000000000000000000000000000000A1 +:10600000000000000001010100000000000000008D +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000202010100000000AA +:1060F00000000000000000000000000000000000A0 +:10610000000000000101010100000000000000008B +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000202010100000000A9 +:1061F000000000000000000000000000000000009F +:106200000000010101010101000000000000000088 +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000202020101000000A6 +:1062F000000000000000000000000000000000009E +:106300000001010101010101000000000000000086 +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000202020201000000A4 +:1063F000000000000000000000000000000000019C +:106400000101010101010101000000000000000084 +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000202020201000000A3 +:1064F0000000000000000100000000000000010199 +:106500000101010101010101000000000000000083 +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000000000000000000000000000000000003B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000202020202000000A1 +:1065F0000000000000000100000000000101010196 +:106600000101010101010101000000000000000082 +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000202020202000000A0 +:1066F0000000000000000100000000000101010195 +:106700000101010101010101000000000000000081 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E000000000000000000002020202020000009F +:1067F0000000000000010100000001010101010191 +:106800000101010101010101000000000000000080 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000000000000000000000000000000000038 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000000B8 +:1068E000000000000000000002020202020200019B +:1068F0000000000000010100000001010101010190 +:10690000010101010101010100000000000000007F +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000000000000000000B7 +:1069E0000000000000000000020202020202020297 +:1069F000000100000001010000000101010101018E +:106A0000010101010101010100000000000000007E +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000000000000000000B6 +:106AE0000000000000000000020202020202020296 +:106AF0000202010000010200000001010101010188 +:106B0000010101010101010100000000000000007D +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000035 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000000000000000000B5 +:106BE0000000000000000000020202020202020295 +:106BF0000202020000020200000001010101010185 +:106C0000010101010101010100000000000000007C +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE0000000000000000000020202020202020294 +:106CF0000202020200020200000101010101010181 +:106D0000010101010101010100000000000000007B +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE0000000000000000000020202020202020293 +:106DF000020202020202020000010101010101017E +:106E0000010101010101010100000000000000007A +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000000000000000000B2 +:106EE0000000000000000000020202020202020292 +:106EF000020202020202020000010101010101017D +:106F00000101010101010101000000000000000079 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000000000000000000B1 +:106FE0000000000000000000020202020202020291 +:106FF0000202020202020200000000000000000083 +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000100000000000000080 +:10710000000000000000000000000000000000017E +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000020100000000000000000000000000008C +:10720000000000000000000000000000000001017C +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F0000201010100000000000000000000000089 +:10730000000000000000000000000000000101017A +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F0000202010100000000000000000000000087 +:107400000000000000000000000000010101010177 +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F0000202020100000000000000000000000085 +:107500000000000000000000000101010101010174 +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F0000202020200000100000000000000000082 +:107600000000000000000101010101010101010170 +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000000BA +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F0000202020201000100000000000000000080 +:10770000000000000000010101010101010101016F +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000000B9 +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F000020202020201010000000000000001007C +:10780000000000000001010101010101010101016D +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000000B8 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000202020202020200000100000000010078 +:10790000000000010101010101010101010101016A +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000202020202020201010100010000010074 +:107A00000000000101010101010101010101010169 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF000020202020202020202020101000001006F +:107B00000000010101010101010101010101010167 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF000020202020202020202020202010002006A +:107C00000001010101010101010101010101010165 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000202020202020202020202020201020067 +:107D00000001010101010101010101010101010164 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000202020202020202020202020202020065 +:107E00000001010101010101010101010101010163 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000202020202020202020202020202020064 +:107F00000001010101010101010101010101010162 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000202020202020202020202020202020063 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000100000000000000000000000000000005F +:10811000000000000000000100000000000000005E +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000002000101000000007B +:10820000000000000000000000000000000000006E +:108210000001010101010101000000000000000057 +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F0000000000000000000020101010000000178 +:10830000000000000000000000000000000000016C +:108310000101010101010101000000000000000055 +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F0000000000000000000020101010000000177 +:108400000001010000000000000000000000000169 +:108410000101010101010101000000000000000054 +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F0000000000000000000020201010000000175 +:108500000101010000000000000000000000010166 +:108510000101010101010101000000000000000053 +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F0000000000000000000020202020000000172 +:108600000101010100000000000000000001010163 +:108610000101010101010101000000000000000052 +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F0000000000000000000020202020000000171 +:108700000101010100000000000000000001010162 +:108710000101010101010101000000000000000051 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000020202020000000170 +:10880000010101010000000000000101010101015E +:108810000101010101010101000000000000000050 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F000000000000000000002020202000001026D +:10890000010101010000000000000101010101015D +:10891000010101010101010100000000000000004F +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000020202020201010269 +:108A00000202020101010000000001010101010157 +:108A1000010101010101010100000000000000004E +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000020202020202020266 +:108B00000202020201010000000101010101010154 +:108B1000010101010101010100000000000000004D +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000020202020202020265 +:108C00000202020201010000000101010101010153 +:108C1000010101010101010100000000000000004C +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000020202020202020264 +:108D00000202020202020000000101010101010150 +:108D1000010101010101010100000000000000004B +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000020202020202020263 +:108E0000020202020202010000010101010101014E +:108E1000010101010101010100000000000000004A +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000020202020202020262 +:108F0000020202020202020000010101010101014C +:108F10000101010101010101000000000000000049 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000020202020202020261 +:109000000202020202020200000000000000000052 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:10910000000000000000000010000000000000004F +:10911000000000000000000000000000010101014B +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:10920000020000010000000000000000000000005B +:109210000000000000000000000000010101010149 +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:10930000020000010000000000000000000000005A +:109310000000000000000000000001010101010147 +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:109400000201010100000000000000000000000057 +:109410000000000000010101010101010101010141 +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:109500000201010100000000000000000101000054 +:10951000000000000101010101010101010101013F +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D000000000000000000000000000000000008B +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:109600000202010100010000000000000101000051 +:10961000000000010101010101010101010101013D +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C000000000000000000000000000000000009A +:1096D000000000000000000000000000000000008A +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:10970000020202020101000000000000010101004C +:10971000000000010101010101010101010101013C +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000099 +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:10980000020202020101000000000000010101004B +:10981000000001010101010101010101010101013A +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000000000000000000000A8 +:1098C0000000000000000000000000000000000098 +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000000000000000078 +:1098F0000000000000000000000000000000000068 +:10990000020202020101000000000000010101004A +:109910000000010101010101010101010101010139 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000000B7 +:1099B00000000000000000000000000000000000A7 +:1099C0000000000000000000000000000000000097 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0000000000000000000000000000000000067 +:109A00000202020202020100000000010101010045 +:109A10000001010101010101010101010101010137 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000000000000000000000000000000000F6 +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000000000000000000B6 +:109AB00000000000000000000000000000000000A6 +:109AC0000000000000000000000000000000000096 +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000076 +:109AF0000000000000000000000000000000000066 +:109B00000202020202020100000000010202010042 +:109B10000001010101010101010101010101010136 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C0000020202020202020100000001020202003E +:109C10000001010101010101010101010101010135 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D0000020202020202020200000102020202003A +:109D10000001010101010101010101010101010134 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000202020202020202020202020202020034 +:109E10000001010101010101010101010101010133 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000202020202020202020202020202020033 +:109F10000001010101010101010101010101010132 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000202020202020202020202020202020032 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A110000F00000000000000000000000000000030 +:10A12000000000000101010100000000000000002B +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000002000001000000004B +:10A21000000000000000000000000000000000003E +:10A220000000000101010101000000000000000029 +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A300000000000000000000020101010000000048 +:10A31000000000000000000000000000000000003D +:10A320000000010101010101000000000000000027 +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A400000000000000000000020101010000000047 +:10A410000000000001010100000000000000010137 +:10A420000101010101010101000000000000000024 +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A500000000000000000000020201010000000045 +:10A510000000000001010100000000000001010135 +:10A520000101010101010101000000000000000023 +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A600000000000000000000020202020000000042 +:10A610000000000001010100000000000001010134 +:10A620000101010101010101000000000000000022 +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000020202020000000041 +:10A710000000000101010100000000010101010130 +:10A720000101010101010101000000000000000021 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A80000000000000000000002020202000100003F +:10A81000000000010101010000000101010101012E +:10A820000101010101010101000000000000000020 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000058 +:10A90000000000000000000002020202000101013C +:10A91000000000010101010000000101010101012D +:10A92000010101010101010100000000000000001F +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000000000077 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000020202020202010138 +:10AA10000000010102020200000101010101010127 +:10AA2000010101010101010100000000000000001E +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000020202020202020235 +:10AB10000101010202020200000101010101010123 +:10AB2000010101010101010100000000000000001D +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000020202020202020234 +:10AC1000020202020202020000010101010101011F +:10AC2000010101010101010100000000000000001C +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000020202020202020233 +:10AD1000020202020202020000010101010101011E +:10AD2000010101010101010100000000000000001B +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000020202020202020232 +:10AE1000020202020202020000010101010101011D +:10AE2000010101010101010100000000000000001A +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000020202020202020231 +:10AF10000202020202020200000000000000000023 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B0100000000000000000000B0000000000000025 +:10B02000000000000000000000000000000101011D +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000020001000000000000000000000101002A +:10B12000000000000000000000000001010101011A +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B210000201010100000000000000000001010027 +:10B220000000000000000000000001010101010118 +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B310000202020100000000000000000001010024 +:10B320000000000000000101010101010101010113 +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B410000202020200000000000000010101010020 +:10B420000000000000010101010101010101010111 +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000020202020001000000000101010101001D +:10B52000000000010101010101010101010101010E +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B610000202020202020100000001010102020016 +:10B62000000001010101010101010101010101010C +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B710000202020202020200000002020202020011 +:10B72000000101010101010101010101010101010A +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B81000020202020202020202020202020202000A +:10B820000001010101010101010101010101010109 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000202020202020202020202020202020009 +:10B920000001010101010101010101010101010108 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000202020202020202020202020202020008 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000000000000000000000000000000000025 +:10BB2000090000000000000000000000000000000C +:10BB30000000000001010001000000000000000002 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC1000000000000000000002010101010000001E +:10BC20000000000001010000000000000000000012 +:10BC300001000000010101010000000000000000FF +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD1000000000000000000002020201010000001B +:10BD2000010000000101000000000000010000000F +:10BD300001000101010101010000000000000000FC +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000000000000000000020202020100000019 +:10BE2000010000000101000000000000010001010C +:10BE300001010101010101010000000000000000FA +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000000000000000000020202020200010115 +:10BF20000100000001010000000000010101010109 +:10BF300001010101010101010000000000000000F9 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000020202020202020210 +:10C020000200010002020000000000010101010104 +:10C0300001010101010101010000000000000000F8 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000002020202020202020F +:10C1200002020200020201000001010101010101FD +:10C1300001010101010101010000000000000000F7 +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000002020202020202020E +:10C2200002020202020202000001010101010101F9 +:10C2300001010101010101010000000000000000F6 +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D000000000000000000000000000000000005E +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000000000000000000002020202020202020D +:10C3200002020202020202000000000000000000FF +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C4200000000000000000000D00000000000000FF +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000010000000000000000000000000000000A +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C61000000000000000000000000000000000001A +:10C620000100000000000000000000000000000009 +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000000000019 +:10C720000200000000010000000000000000000006 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000000000000000018 +:10C820000201010000010000000000000000000003 +:10C8300000000000000000000000000000000101F6 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000000000000000017 +:10C9200002010101000101000000010000000100FE +:10C9300000000000000000000000000000000101F5 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000000000000000000016 +:10CA200002020101000101000001010000000100FB +:10CA300000000000000101010000010001010101EE +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000000000000000000015 +:10CB200002020202010201010001010001010100F3 +:10CB300000000100000101010101010101010101E9 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC10000000000000000000000000000000000014 +:10CC200002020202020202010102020001010100ED +:10CC300000000101010101010101010101010101E6 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000054 +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD10000000000000000000000000000000000013 +:10CD200002020202020202020202020002020200E7 +:10CD300000010101010101010101010101010101E4 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE10000000000000000000000000000000000012 +:10CE200002020202020202020202020202020200E4 +:10CE300000010101010101010101010101010101E3 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000000000000000000011 +:10CF200002020202020202020202020202020200E3 +:10CF300000010101010101010101010101010101E2 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000000000000000000010 +:10D0200002020202020202020202020202020200E2 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D130000D000000000000000000000000000000E2 +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000100000000000000FD +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000100000000000000FC +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000200000000000000FA +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000200000000000000F9 +:10D5300000000000000000000000000000000000EB +:10D5400000000001000000010000000000000000D9 +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D61000000000000000000000000000000000000A +:10D6200000000000000000000200010100000100F5 +:10D6300000000101000000000000000000000000E8 +:10D6400000000001000101010000000000000000D6 +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000201010101010101F0 +:10D7300000010101000100000000000000000100E4 +:10D7400000000101010101010000000000000000D3 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D810000000000000000000000000000000000008 +:10D8200000000000000000000202020201010101EC +:10D8300000010101000100000000000001010101E0 +:10D8400001010101010101010000000000000000D0 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000202020202020202E7 +:10D9300000020201000101000000010101010101DA +:10D9400001010101010101010000000000000000CF +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000202020202020202E6 +:10DA300000020202000201000001010101010101D6 +:10DA400001010101010101010000000000000000CE +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000202020202020202E5 +:10DB300002020202000202000001010101010101D2 +:10DB400001010101010101010000000000000000CD +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000202020202020202E4 +:10DC300002020202020202000001010101010101CF +:10DC400001010101010101010000000000000000CC +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000202020202020202E3 +:10DD300002020202020202000000000000000000D5 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000B00000000000000D7 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300001000000000000000000000000000000E0 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000000000000000000000000051 +:10DFD0000000000000000000000000000000000041 +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300002000000000000000000000000000000DE +:10E0400000000000000000000000000100000001CE +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D0000000000000000000000000000000000040 +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300002000101000001000000010100000000D8 +:10E1400000000000000000000000000100010101CB +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300002010101010101010001010100010000D1 +:10E2400000000000000001000000010101010101C7 +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300002020202010101010001010100010000CD +:10E3400000000000010101010101010101010101C1 +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300002020202020202020002020100010100C5 +:10E4400000000101010101010101010101010101BE +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000000000005C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300002020202020202020002020200020100C2 +:10E5400000010101010101010101010101010101BC +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000000000000000000005B +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300002020202020202020202020200020200BE +:10E6400000010101010101010101010101010101BB +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000000000000000000005A +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300002020202020202020202020202020200BB +:10E7400000010101010101010101010101010101BA +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000000000000000000059 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000000000000F8 +:10E8200000000000000000000000000000000000E8 +:10E8300002020202020202020202020202020200BA +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000000000000000000058 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000000000000F7 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400078E907000000000080390800000000009E +:10E95000887F08000000000090C008000000000050 +:10E960009803090000000000A04309000000000017 +:10E97000A87E090000000000B0AF09000000000000 +:10E98000B8E0090000000000C0110A00000000000B +:10E99000C8430A0000000000D0730A000000000015 +:10E9A000D8A60A0000000000E0D70A00000000001E +:10E9B000E8070B000000000050000000000000000D +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000000010000000000000036 +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000001000000000085 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000101000000000000000100000000000043 +:10EAD0000100000000000000010000000000000034 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000001000101000082 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000154 +:10EBC0000101000000000000000100000000000042 +:10EBD0000100000100000000010000000000000032 +:10EBE0000000000100000000000000000000000024 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000001000101000081 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000153 +:10ECC0000101000000000000000100000000000041 +:10ECD0000100000100000000010000000000000031 +:10ECE0000000000100000000000000000000000023 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000000000000000000F3 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000001000101000080 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000152 +:10EDC0000101000000000000000100000000000040 +:10EDD000010000010000000001000100000000002F +:10EDE0000000000100000000000000000000010021 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000010000000001 +:10EE100000000000000000000000000000000000F2 +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000100000000B1 +:10EE600000000000000000000000000000000000A2 +:10EE70000000000000000000000000000000000092 +:10EE8000000000000000000000000100010101007E +:10EE9000000000000001010100000000000000006F +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000151 +:10EEC000010100000000000000010000000000003F +:10EED000010001010000000001000100000100002C +:10EEE0000000000100000000000000000000010020 +:10EEF0000000000000000000000000000000000012 +:10EF000001010000000000000000000100000000FE +:10EF100000000000000000010000000000000000F0 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000100000000B0 +:10EF600000000000000000000000000000000001A0 +:10EF70000000000000000000000000000000000091 +:10EF8000000100000000000000000100010101007C +:10EF9000000000000101010100000000000000006D +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000150 +:10EFC000010100000001000001010000000000003C +:10EFD000010001010000000001000100000100012A +:10EFE000000000010000000000000000000001001F +:10EFF0000000000000000000000000000000000011 +:10F0000001010000000101010000000100000000FA +:10F0100000010000000000010001000000000000ED +:10F0200000000000000000000001000000000000DF +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000001000000000100010100000000AC +:10F06000000000000000000000000000000000019F +:10F070000000000000000000000000000000000090 +:10F08000000100010000000000000100010101007A +:10F09000000000000101010100000000000000016B +:10F0A0000000000000000000000000000000000060 +:10F0B000000000000000000000000000000000014F +:10F0C000010100000101000001010000000000003A +:10F0D0000100010100000000010001000001000129 +:10F0E000000000010100000000000000000001001D +:10F0F0000000000000000000000000000000000010 +:10F1000001010000000101010001000100000000F8 +:10F1100000010000000000010001010000000000EB +:10F1200000000000000000010001000000000000DD +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000001000000000100010100000000AB +:10F16000000000000000000000000000000000019E +:10F17000000000000000000100000000000000018D +:10F180000001000100000000000001000101010079 +:10F190000000000001010101000100000000000169 +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000014E +:10F1C0000202000001010000010100000000000037 +:10F1D0000100010100000000010001000001000128 +:10F1E000000000010100000000000000000001001C +:10F1F000000000000000000000000000000000000F +:10F2000001010000000101010101010100000000F5 +:10F2100000010000000000010001010000000000EA +:10F2200000000000000000010001000000000000DC +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000001000000000100010100000000AA +:10F26000000000000000000000000000000000019D +:10F27000000000000000000100010000000000018B +:10F280000001000100010100000001000101010076 +:10F290000000000001010101010101010000000165 +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000014D +:10F2C0000202000001010000010100000000000036 +:10F2D0000100010100000000010001000101000126 +:10F2E0000100000101000000000000000001010019 +:10F2F000000000000000000000000000000000000E +:10F3000001010000000101010101010100000000F4 +:10F3100000010001000000010101010000000000E7 +:10F3200000000000000000010001000000000000DB +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000001000000000100010100000000A9 +:10F36000000000000000000000000000000000019C +:10F370000000000000000001010100000000000189 +:10F380000001010101010100000001000101010073 +:10F390000000000001010101010101010101000162 +:10F3A000000000000000000001000001000000015A +:10F3B000000000000000000000000000000000014C +:10F3C0000202000001010100010200000000000033 +:10F3D0000100010100000000010001000101000125 +:10F3E0000100000101000000010000000001010116 +:10F3F000000000000000000000000000000000000D +:10F4000001010000000101010101010100000000F3 +:10F4100001010101000000010101010000010000E3 +:10F4200000000000000000010001000000000000DA +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000010000BB +:10F4500000000001000101010100010100000000A5 +:10F46000000000000000000000000000000000019B +:10F470000000000000000001010100000000000188 +:10F480000001010101010101000001000101010170 +:10F490000000000001010101010101010101000161 +:10F4A0000000000000000000010000010000000159 +:10F4B000000000000000000000000000000000014B +:10F4C0000202010001010100010200000000000031 +:10F4D0000100010100000000010001000101000124 +:10F4E0000100000101000000010000000001010115 +:10F4F000000000000000000000000000000000000C +:10F5000001010100000101010101010100000000F1 +:10F5100001010101000000010101010000010100E1 +:10F5200000000000000000010001000000000000D9 +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000010100B9 +:10F5500000010001010101010100010100000000A2 +:10F56000000000000000000000000000000000019A +:10F570000000000000000001010101010000000185 +:10F58000010101010101010100010100010101016D +:10F590000000000001010101010101010101000160 +:10F5A0000000000000000000010000010000000158 +:10F5B000000000000000000000000000000000014A +:10F5C000020201000202010002020000000000002D +:10F5D0000200010100000000010001010101000121 +:10F5E0000100000101010000010000000001010113 +:10F5F000000000000000000000000000000000000B +:10F6000001010100000101010101010100000001EF +:10F6100001010101000000010101010000010100E0 +:10F6200000000000000000010001000000000000D8 +:10F6300000000000000000000000000000000000CA +:10F6400001010000000000000000000000010100B6 +:10F6500000010001010101010100010100000000A1 +:10F660000000000000000000000000000100000198 +:10F670000000000000000001010101010100000183 +:10F68000010101010101010101010100010101016B +:10F69000000000000101010101010101010101015E +:10F6A0000000000000000000010000010001000156 +:10F6B0000000000000000000000000000000000149 +:10F6C000020201000202010002020000010000002B +:10F6D000020001010000000001010101010100011F +:10F6E0000101000101010000010100000001010110 +:10F6F000000000000000000000000000000000000A +:10F7000001010100000101010101010100000001EE +:10F7100001010101000000010101010000010100DF +:10F7200000000000000000010101000000000000D6 +:10F7300000000000000000000000000000000000C9 +:10F7400001010000000000000000000000010100B5 +:10F75000010100010101010101000101000000009F +:10F760000000000000000000000000000100000197 +:10F770000000000000000001010101010100000182 +:10F78000010101010101010101010100010101016A +:10F79000000000000101010101010101010101015D +:10F7A0000000000000000000010000010001000155 +:10F7B0000000000000000000000000000000000148 +:10F7C0000202020002020101020200010100000027 +:10F7D000020001020000000001010101010100011D +:10F7E000010100010101010001010000000101010E +:10F7F0000000000001000000000000000000000008 +:10F8000001010100000101010101010100000001ED +:10F8100001010101000000010101010000010100DE +:10F8200000000000000000010101000000000000D5 +:10F8300000000000000000000000000000000000C8 +:10F8400001010000000000000000000001010100B3 +:10F85000010100010101010101000101000000019D +:10F860000001000000000000000000000100000195 +:10F870000000000000000001010101010101000180 +:10F880000101010101010101010101010101010168 +:10F89000000000000101010101010101010101015C +:10F8A0000000000000000000010000010101000153 +:10F8B0000000000000000000000000000000000147 +:10F8C0000202020002020201020200010100000025 +:10F8D000020002020000000002010101010100011A +:10F8E000010100010101010001010000010101010C +:10F8F0000000000001010100000000000000000005 +:10F9000001010100000101010101010100000001EC +:10F9100001010101000100010101010000010101DB +:10F9200000000000000000010101000000000000D4 +:10F9300000000000000000000000000000000000C7 +:10F9400001010000000000000000000101010100B1 +:10F950000101010101010101010101010001000199 +:10F960000001000000000000000000000100010193 +:10F97000000000000000000101010101010100017F +:10F980000101010101010101010101010101010167 +:10F99000000000000101010101010101010101015B +:10F9A0000000000000000000010000010101010151 +:10F9B0000000000000000000000000000000000146 +:10F9C0000202020002020201020200010100000024 +:10F9D0000200020200000101020101010101000117 +:10F9E000010100020101010001010000010101010A +:10F9F0000000000001010100000000000000000004 +:10FA000001010101000101010101010100000001EA +:10FA100001010101010100010101010001010101D8 +:10FA200000000000000000010101000000000000D3 +:10FA300000000000000000000000000000000000C6 +:10FA400001010000000000000001000101010100AF +:10FA50000101010101010101010101010001000198 +:10FA60000001000000000000000000000100010192 +:10FA7000000000000000000101010101010100017E +:10FA80000101010101010101010101010101010166 +:10FA9000000000000101010101010101010101015A +:10FAA0000000000000000000010000010101010150 +:10FAB0000000000000000000000000000000000145 +:10FAC0000202020002020201020200010100000023 +:10FAD0000200020200000101020101010101000116 +:10FAE0000101000201010100010100000101010109 +:10FAF0000000000101010101000000000000000001 +:10FB000001010101000101010101010100000001E9 +:10FB100001010101010101010101010001010101D6 +:10FB200000000000000100010101000000000000D1 +:10FB300000000000000000000000000000000000C5 +:10FB400001010000000000000101010101010101AB +:10FB50000101010101010101010101010101000196 +:10FB60000001000000000000000000000100010191 +:10FB7000000000010000000101010101010101017B +:10FB80000101010101010101010101010101010165 +:10FB90000000000001010101010101010101010159 +:10FBA000000000000000000001000001010101014F +:10FBB0000000000000000000000000000000000144 +:10FBC0000202020002020202020200010100000021 +:10FBD0000200020200000101020101010101010114 +:10FBE0000201000201010100010100000101010107 +:10FBF00000010001010101010000000000000000FF +:10FC000002010101000101010101010100000101E6 +:10FC100001010101010101010101010001010101D5 +:10FC200000000000010100010101000000000000CF +:10FC300000000000000000000000000001010000C2 +:10FC400001010000000000000101010101010101AA +:10FC50000101010101010101010101010101010194 +:10FC6000010100000000000000010000010001018E +:10FC70000101000100000001010101010101010178 +:10FC80000101010101010101010101010101010164 +:10FC90000000000001010101010101010101010158 +:10FCA000000000000000000001000001010101014E +:10FCB0000000000000000000000000000000000143 +:10FCC000020202000202020202020002020000001E +:10FCD0000200020201000101020102010101010111 +:10FCE0000201000202010100010100000101010105 +:10FCF00000010001010101010000000100000001FC +:10FD000002020101000101010101010100000101E4 +:10FD100001020101010101010101010101010101D2 +:10FD200000000000010101010101000100000000CC +:10FD300000000000000000000000000101010000C0 +:10FD400001010000000000000101010101010101A9 +:10FD50000101010101010101010101010101010193 +:10FD6000010100010000000000010101010001018A +:10FD70000101000100000001010101010101010177 +:10FD80000101010101010101010101010101010163 +:10FD90000000000001010101010101010101010157 +:10FDA000000000000000000001000001010101014D +:10FDB0000000000000000000000000000000000142 +:10FDC000020202010202020202020002020000001C +:10FDD0000200020201000101020102010101010110 +:10FDE0000201000202010100010100000101010104 +:10FDF00000010101010101010000000101010001F8 +:10FE000002020101000101010101010100000101E3 +:10FE100001020101010101010101010101010101D1 +:10FE200000010100010101010101000100000000C9 +:10FE300000010000000000000001000101010000BD +:10FE400001010100000000000101010101010101A7 +:10FE50000101010101010101010101010101010192 +:10FE60000101010100000000000101010100010188 +:10FE70000101010101000001010101010101010174 +:10FE80000101010101010101010101010101010162 +:10FE90000000000001010101010101010101010156 +:10FEA000000000000000000001000001010101014C +:10FEB0000000000000000000000000000000000141 +:10FEC000020202020202020202020002020000001A +:10FED000020102020100010102010201010101010E +:10FEE0000202000202010100010100000101010102 +:10FEF00000010101010101010100000101010001F6 +:10FF000002020101010101010101010100000101E1 +:10FF100002020101010101010101010101010101CF +:10FF200000010100010101010101010100000000C7 +:10FF300000010000000000000101010101010100B9 +:10FF400001010101000000000101010101010101A5 +:10FF50000101010101010101010101010101010191 +:10FF60000101010100000000010101010100010186 +:10FF70000101010101010001010101010101010172 +:10FF80000101010101010101010101010101010161 +:10FF90000000000001010101010101010101010155 +:10FFA000000000000000000001000001010101014B +:10FFB0000000000000000000000000000000000140 +:10FFC0000202020202020202020200020200000019 +:10FFD000020102020101010102010201010101010C +:10FFE00002020002020101010101000101010101FF +:10FFF00001010101010101010100000101010001F4 +:0200000280007C +:1000000002020101010101010101010100000101E0 +:1000100002020201010101010101010101010101CD +:1000200001010100010101010101010100000000C5 +:1000300001010000000000000101010101010100B7 +:1000400001010101000000000101010101010101A4 +:100050000101010101010101010101010101010190 +:100060000101010101000000010101010100010184 +:100070000101010101010001010101010101010171 +:100080000101010101010101010101010101010160 +:100090000000000101010101010101010101010153 +:1000A000000000000000000001000001010101014A +:1000B000000000000000000000000000000000013F +:1000C0000202020202020202020200020201000017 +:1000D000020102020101010102010201010101010B +:1000E00002020102020101010201000101010101FC +:1000F00001010101020101010100010101010101F0 +:1001000002020201010201010101010100000101DD +:1001100002020202010101010101010101010101CB +:1001200001010101010101010101010100000101C1 +:1001300001010001000000000101010101010100B5 +:1001400001010101000000000101010101010101A3 +:10015000010101010101010101010101010101018F +:100160000101010101010000010101010100010182 +:100170000101010101010001010101010101010170 +:10018000010101010101010101010101010101015F +:100190000001010101010101010101010101010150 +:1001A0000000000000000000010000010101010149 +:1001B000000000010000000000000000000000013D +:1001C0000202020202020202020200020201010015 +:1001D0000201020202010201020202010102010106 +:1001E00002020102020201010201010101010101F9 +:1001F00001010101020101010101010101010101EE +:1002000002020201010202010101010100000101DB +:1002100002020202010101020101010101010101C9 +:1002200001010101010101010101010100010101BF +:1002300001010001000000000101010101010100B4 +:1002400001010101000000000101010101010101A2 +:10025000010101010101010101010101010101018E +:100260000101010101010000010101010100010181 +:10027000010101010101000101010101010101016F +:10028000010101010101010101010101010101015E +:10029000000101010101010101010101010101014F +:1002A0000000000000000000010000010101010148 +:1002B000000001010000000000000000000000013B +:1002C0000202020202020202020200020201010014 +:1002D0000202020202010202020202020202010101 +:1002E00002020102020201010201010101010101F8 +:1002F00001020102020201010101010101010101EA +:1003000002020201010202020101010101000101D8 +:1003100002020202010101020101010101010101C8 +:1003200001010101010101010101010100010101BE +:1003300001010001000000000101010101010101B2 +:1003400001010101000000000101010101010101A1 +:10035000010101020101010101010101010101018C +:10036000010101010101010001010101010001017F +:10037000010101010101000101010101010101016E +:10038000010101010101010101010101010101015D +:10039000000101010101010101010101010101014E +:1003A0000000000100000000010000010101010146 +:1003B0000000010100010100000000000000000138 +:1003C0000202020202020202020200020201010013 +:1003D0000202020202010202020202020202010100 +:1003E00002020102020202010202010101010201F4 +:1003F00001020202020202010101010101010101E7 +:1004000002020201010202020201010101000101D6 +:1004100002020202010101020202010101010101C5 +:1004200001010101010101020101010101010101BB +:1004300001010101000000000101010101010101B0 +:10044000020101010100000001010101010101019E +:100450000202010201010101010101010101010189 +:10046000010101010101010001010101010101017D +:10047000010101010101000101010101010101016D +:10048000010201010101010101010101010101015B +:10049000000101010101010101010101010101014D +:1004A0000101000100000000010000010101010143 +:1004B0000001010101010100000000000000000135 +:1004C0000202020202020202020200020202010011 +:1004D00002020202020202020202020202020101FE +:1004E00002020102020202010202010101010201F3 +:1004F00002020202020202010101010101010101E5 +:1005000002020202010202020202010201000101D2 +:1005100002020202020101020202020101010101C2 +:1005200001010101010101020102010101010101B9 +:1005300001010101000000000101010101010101AF +:10054000020201010101000001010101010101019B +:100550000202010201010101010101010101010188 +:10056000010101010101010101010101010101017B +:10057000010101010101010101010101010101016B +:10058000010201010101010101010101010101015A +:10059000010101010101010101010101010101014B +:1005A000010100010001010101000001010101013F +:1005B0000001010101010101000000000000000133 +:1005C000020202020202020202020202020202000D +:1005D00002020202020202020202020202020101FD +:1005E00002020202020202010202010101020201F0 +:1005F00002020202020202020101010101010101E3 +:1006000002020202010202020202020201000101D0 +:1006100002020202020201020202020101010101C0 +:1006200001010101010101020102010101010101B8 +:1006300001010101000000000101010101010101AE +:10064000020201010101000001010101010101019A +:100650000202010202010101020101010101010185 +:10066000010101010101010101010101010101017A +:10067000010101010101010101010101010101016A +:100680000202010101010101010101010101010158 +:10069000010101010101010101010101010101014A +:1006A000010101010101010101010001010101013B +:1006B0000001010101010101000000000000000132 +:1006C000020202020202020202020202020202000C +:1006D00002020202020202020202020202020102FB +:1006E00002020202020202010202010101020201EF +:1006F00002020202020202020101010101010101E2 +:1007000002020202010202020202020201010101CE +:1007100002020202020201020202020101010101BF +:1007200002020201020101020202010101010101B2 +:1007300001010101000000000101010101010101AD +:100740000202010101010100010101010101010198 +:100750000202020202020101020101010101010182 +:100760000102010101010101010101010101010178 +:100770000101010101010101010101010101010169 +:100780000202020201010101010101010101010155 +:100790000101010102010101010101010101010148 +:1007A000010101010101010101010001010101013A +:1007B0000001010101010101010000000000000130 +:1007C000020202020202020202020202020202000B +:1007D00002020202020202020202020202020102FA +:1007E00002020202020202010202010102020201ED +:1007F00002020202020202020201010101010101E0 +:1008000002020202020202020202020201010101CC +:1008100002020202020202020202020101010101BD +:1008200002020201020201020202010101010101B0 +:1008300002020101010000000101010101010101A9 +:100840000202010101010100010101010101010197 +:10085000020202020202020102010202010101017E +:100860000202010101010101010101010101010176 +:100870000101010101010101010101010101010168 +:100880000202020201010101010101010101010154 +:100890000101010102020101010101010101010146 +:1008A0000101010101010101010100010101010139 +:1008B000000101010101010101010000000000012E +:1008C000020202020202020202020202020202000A +:1008D00002020202020202020202020202020102F9 +:1008E00002020202020202020202010102020201EB +:1008F00002020202020202020201010101010101DF +:1009000002020202020202020202020201010101CB +:1009100002020202020202020202020101010101BC +:1009200002020201020201020202010101010101AF +:1009300002020101010101010101010101010101A5 +:100940000202010101010101010101010101010195 +:10095000020202020202020202010202010101017C +:100960000202010101010101010101010101010175 +:100970000201010101010101010101010101010166 +:100980000202020202010101010102010101010151 +:100990000101010102020201010101010101010144 +:1009A0000101010101010101010100010101010138 +:1009B000000101010101010101010101000000012B +:1009C0000202020202020202020202020202020009 +:1009D00002020202020202020202020202020202F7 +:1009E00002020202020202020202010102020201EA +:1009F00002020202020202020201010101010101DE +:100A000002020202020202020202020201010101CA +:100A100002020202020202020202020101020101BA +:100A200002020202020202020202010101010101AC +:100A300002020101010101010101010101010101A4 +:100A40000202020101010101010101010101010193 +:100A5000020202020202020202010202010101017B +:100A60000202010101010101010101010101010174 +:100A70000202010101010102010101010101010163 +:100A8000020202020202010101010201010101014F +:100A90000101010102020202010101010101010142 +:100AA0000101010101010101010100010101010137 +:100AB0000001010101010101010101010101000128 +:100AC0000202020202020202020202020202020008 +:100AD00002020202020202020202020202020202F6 +:100AE00002020202020202020202020102020201E8 +:100AF00002020202020202020202020201010101DA +:100B000002020202020202020202020201010101C9 +:100B100002020202020202020202020101020201B8 +:100B200002020202020202020202010101010101AB +:100B300002020102010101010101010101010101A2 +:100B40000202020101010101010101010101010192 +:100B5000020202020202020202010202010101017A +:100B60000202020101010101010101010101010172 +:100B70000202010101010102020101010101010161 +:100B8000020202020202020101010201020101014C +:100B90000101010102020202010101010101010141 +:100BA0000101010101010101010101010101010135 +:100BB0000001010101010101010101010101010126 +:100BC0000202020202020202020202020202020007 +:100BD00002020202020202020202020202020202F5 +:100BE00002020202020202020202020202020202E5 +:100BF00002020202020202020202020202010101D8 +:100C000002020202020202020202020201010101C8 +:100C100002020202020202020202020102020201B6 +:100C200002020202020202020202010101010101AA +:100C300002020202010101010101010101010101A0 +:100C40000202020201010101010101010101010190 +:100C50000202020202020202020102020101010179 +:100C60000202020201010101010101010101010170 +:100C7000020202020101010202020101010101015D +:100C8000020202020202020101010201020201014A +:100C9000010101010202020202010101010101013F +:100CA0000101010101010101010101010101010134 +:100CB0000001010101010101010101010101010125 +:100CC0000202020202020202020202020202020006 +:100CD00002020202020202020202020202020202F4 +:100CE00002020202020202020202020202020202E4 +:100CF00002020202020202020202020202020101D6 +:100D000002020202020202020202020201010101C7 +:100D100002020202020202020202020202020201B4 +:100D200002020202020202020202010101010101A9 +:100D3000020202020101010102010101010101019E +:100D4000020202020101010102010101010101018E +:100D50000202020202020202020202020101010177 +:100D6000020202020101010101010101010101016F +:100D7000020202020101010202020101010101015C +:100D80000202020202020202010102010202010148 +:100D9000010101010202020202020101010101013D +:100DA0000101010101010101010101010101010133 +:100DB0000001010101010101010101010101010124 +:100DC0000202020202020202020202020202020005 +:100DD00002020202020202020202020202020202F3 +:100DE00002020202020202020202020202020202E3 +:100DF00002020202020202020202020202020101D5 +:100E000002020202020202020202020201010101C6 +:100E100002020202020202020202020202020201B3 +:100E200002020202020202020202020201010101A6 +:100E3000020202020101010102020101010101019C +:100E4000020202020101010102020101010201018B +:100E50000202020202020202020202020101010176 +:100E6000020202020201010101010101010101016D +:100E70000202020202010102020202010101010159 +:100E80000202020202020202020102010202020145 +:100E9000010201010202020202020201010101013A +:100EA0000101010101010101020101010101010131 +:100EB0000001010101010101010101010101010123 +:100EC0000202020202020202020202020202020004 +:100ED00002020202020202020202020202020202F2 +:100EE00002020202020202020202020202020202E2 +:100EF00002020202020202020202020202020101D4 +:100F000002020202020202020202020201010101C5 +:100F100002020202020202020202020202020201B2 +:100F200002020202020202020202020201010101A5 +:100F30000202020202010101020202020201010197 +:100F40000202020202010101020202020202020185 +:100F50000202020202020202020202020101010175 +:100F6000020202020201010101010101020101026A +:100F70000202020202010102020202020101010157 +:100F80000202020202020202020202010202020143 +:100F90000202020102020202020202020101010136 +:100FA0000101010101010101020101010101010130 +:100FB0000001010101010101010101010101010122 +:100FC0000202020202020202020202020202020003 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00002020202020202020202020202020201D2 +:1010000002020202020202020202020201010202C2 +:1010100002020202020202020202020202020201B1 +:1010200002020202020202020202020201010101A4 +:101030000202020202010101020202020202010195 +:101040000202020202010101020202020202020184 +:101050000202020202020202020202020202010172 +:101060000202020202020101020201010201010266 +:101070000202020202020102020202020201010154 +:101080000202020202020202020202010202020142 +:101090000202020202020202020202020201010133 +:1010A000020101010101010102010101010101012E +:1010B000000202010101010101010101010101021E +:1010C0000202020202020202020202020202020002 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00002020202020202020202020202020201D1 +:1011000002020202020202020202020201010202C1 +:1011100002020202020202020202020202020202AF +:1011200002020202020202020202020201010101A3 +:101130000202020202020101020202020202010193 +:101140000202020202020101020202020202020182 +:101150000202020202020202020202020202010171 +:101160000202020202020101020202010201010264 +:101170000202020202020102020202020201010252 +:101180000202020202020202020202010202020141 +:101190000202020202020202020202020202010131 +:1011A000020201010101010102010102010101012B +:1011B000000202020101010101010101010101021C +:1011C0000202020202020202020102020202020002 +:1011D00002020202020202020202020202020202EF +:1011E00002020202020202020202020202020202DF +:1011F00002020202020202020202020202020202CF +:1012000002020202020202020202020202010202BF +:1012100002020202020202020202020202020202AE +:1012200002020202020202020202020201010101A2 +:101230000202020202020201020202020202010191 +:101240000202020202020101020202020202020181 +:10125000020202020202020202020202020202016F +:101260000202020202020201020202020201020260 +:101270000202020202020102020202020202010250 +:10128000020202020202020202020202020202013F +:10129000020202020202020202020202020201022F +:1012A000020201010101010102010102010101012A +:1012B000000202020101010101010101010101021B +:1012C0000202020202020202010102010102020004 +:1012D00002020202020202020202020202020202EE +:1012E00002020202020202020202020202020202DE +:1012F00002020202020202020202020202020202CE +:1013000002020202020202020202020202010202BE +:1013100002020202020202020202020202020202AD +:10132000020202020202020202020202020202019E +:10133000020202020202020202020202020202018E +:10134000020202020202020102020202020202017F +:10135000020202020202020202020202020202026D +:10136000020202020202020102020202020102025F +:10137000020202020202010202020202020201024F +:10138000020202020202020202020202020202013E +:10139000020202020202020202020202020202022D +:1013A0000202020201010101020101020101010127 +:1013B0000002020202010101010101010101010219 +:1013C0000202020202020202010102010102020003 +:1013D00002020202020202020202020202020202ED +:1013E00002020202020202020202020202020202DD +:1013F00002020202020202020202020202020202CD +:1014000002020202020202020202020202010202BD +:1014100002020202020202020202020202020202AC +:10142000020202020202020202020202020202019D +:10143000020202020202020202020202020202018D +:10144000020202020202020102020202020202017E +:10145000020202020202020202020202020202026C +:10146000020202020202020202020202020102025D +:10147000020202020202020202020202020202024C +:10148000020202020202020202020202020202023C +:10149000020202020202020202020202020202022C +:1014A0000202020201010101020101020202010124 +:1014B0000002020202020101010101010101010217 +:1014C0000202020202010101010102010101010007 +:1014D00002020202020202020202020202020202EC +:1014E00002020202020202020202020202020202DC +:1014F00002020202020202020202020202020202CC +:1015000002020202020202020202020202010202BC +:1015100002020202020202020202020202020202AB +:10152000020202020202020202020202020202019C +:10153000020202020202020202020202020202018C +:10154000020202020202020202020202020202017C +:10155000020202020202020202020202020202026B +:10156000020202020202020202020202020102025C +:10157000020202020202020202020202020202024B +:10158000020202020202020202020202020202023B +:10159000020202020202020202020202020202022B +:1015A0000202020202010101020101020202010221 +:1015B0000002020202020201010101010101010215 +:1015C0000202020201010101010101010101010008 +:1015D00002020202020202020202020202020202EB +:1015E00002020202020202020202020202020202DB +:1015F00002020202020202020202020202020202CB +:1016000002020202020202020202020202020202BA +:1016100002020202020202020202020202020202AA +:10162000020202020202020202020202020202019B +:10163000020202020202020202020202020202018B +:10164000020202020202020202020202020202027A +:10165000020202020202020202020202020202026A +:10166000020202020202020202020202020102025B +:10167000020202020202020202020202020202024A +:10168000020202020202020202020202020202023A +:10169000020202020202020202020202020202022A +:1016A000020202020202010102010102020202021E +:1016B0000002020202020201010101010101010214 +:1016C0000202020201010101010101010101010007 +:1016D00002020202020202020202020202020202EA +:1016E00002020202020202020202020202020202DA +:1016F00002020202020202020202020202020202CA +:1017000002020202020202020202020202020202B9 +:1017100002020202020202020202020202020202A9 +:101720000202020202020202020202020202020299 +:10173000020202020202020202020202020202018A +:101740000202020202020202020202020202020279 +:101750000202020202020202020202020202020269 +:10176000020202020202020202020202020102025A +:101770000202020202020202020202020202020249 +:101780000202020202020202020202020202020239 +:101790000202020202020202020202020202020229 +:1017A000020202020202020102010102020202021C +:1017B0000002020202020202010101010101010212 +:1017C0000201010201010101010101010101010008 +:1017D00002020202020202020202020202020202E9 +:1017E00002020202020202020202020202020202D9 +:1017F00002020202020202020202020202020202C9 +:1018000002020202020202020202020202020202B8 +:1018100002020202020202020202020202020202A8 +:101820000202020202020202020202020202020298 +:101830000202020202020202020202020202020189 +:101840000202020202020202020202020202020278 +:101850000202020202020202020202020202020268 +:101860000202020202020202020202020202020258 +:101870000202020202020202020202020202020248 +:101880000202020202020202020202020202020238 +:101890000202020202020202020202020202020228 +:1018A000020202020202020202010102020202021A +:1018B000010202020202020202010101010101020F +:1018C0000101010101010101010101010101010009 +:1018D00002020202020202020202020202020202E8 +:1018E00002020202020202020202020202020202D8 +:1018F00002020202020202020202020202020202C8 +:1019000002020202020202020202020202020202B7 +:1019100002020202020202020202020202020202A7 +:101920000202020202020202020202020202020297 +:101930000202020202020202020202020202020287 +:101940000202020202020202020202020202020277 +:101950000202020202020202020202020202020267 +:101960000202020202020202020202020202020257 +:101970000202020202020202020202020202020247 +:101980000202020202020202020202020202020237 +:101990000202020202020202020202020202020227 +:1019A0000202020202020202020101020202020219 +:1019B000010202020202020202010101010101020E +:1019C0000101010101010101010101010101010008 +:1019D00002020202020202020102010202020202E9 +:1019E00002020202020202020202020202020202D7 +:1019F00002020202020202020202020202020202C7 +:101A000002020202020202020202020202020202B6 +:101A100002020202020202020202020202020202A6 +:101A20000202020202020202020202020202020296 +:101A30000202020202020202020202020202020286 +:101A40000202020202020202020202020202020276 +:101A50000202020202020202020202020202020266 +:101A60000202020202020202020202020202020256 +:101A70000202020202020202020202020202020246 +:101A80000202020202020202020202020202020236 +:101A90000202020202020202020202020202020226 +:101AA0000202020202020202020201020202020217 +:101AB000020202020202020202020101010101020B +:101AC0000101010101010101010101010101010007 +:101AD00002020202020202020101010102020202EA +:101AE00002020202020202020202020202020202D6 +:101AF00002020202020202020202020202020202C6 +:101B000002020202020202020202020202020202B5 +:101B100002020202020202020202020202020202A5 +:101B20000202020202020202020202020202020295 +:101B30000202020202020202020202020202020285 +:101B40000202020202020202020202020202020275 +:101B50000202020202020202020202020202020265 +:101B60000202020202020202020202020202020255 +:101B70000202020202020202020202020202020245 +:101B80000202020202020202020202020202020235 +:101B90000202020202020202020202020202020225 +:101BA0000202020202020202020201020202020216 +:101BB0000202020202020202020202010101010209 +:101BC0000101010101010101010101010101010105 +:101BD00002020201020201010101010101010202EE +:101BE00002020202020202020202020202020202D5 +:101BF00002020202020202020202020202020202C5 +:101C000002020202020202020202020202020202B4 +:101C100002020202020202020202020202020202A4 +:101C20000202020202020202020202020202020294 +:101C30000202020202020202020202020202020284 +:101C40000202020202020202020202020202020274 +:101C50000202020202020202020202020202020264 +:101C60000202020202020202020202020202020254 +:101C70000202020202020202020202020202020244 +:101C80000202020202020202020202020202020234 +:101C90000202020202020202020202020202020224 +:101CA0000202020202020202020201020202020215 +:101CB0000202020202020202020202020101010207 +:101CC0000101010101010101010101010101010104 +:101CD00002020101010101010101010101010102F1 +:101CE00002020202020202020202020202020202D4 +:101CF00002020202020202020202020202020202C4 +:101D000002020202020202020202020202020202B3 +:101D100002020202020202020202020202020202A3 +:101D20000202020202020202020202020202020293 +:101D30000202020202020202020202020202020283 +:101D40000202020202020202020202020202020273 +:101D50000202020202020202020202020202020263 +:101D60000202020202020202020202020202020253 +:101D70000202020202020202020202020202020243 +:101D80000202020202020202020202020202020233 +:101D90000202020202020202020202020202020223 +:101DA0000202020202020202020202020202020213 +:101DB0000202020202020202020202020201010205 +:101DC0000101010101010101010101010101010103 +:101DD00001020101010101010101010101010101F2 +:101DE00002020202020202020101020202020202D5 +:101DF00002020202020202020202020202020202C3 +:101E000002020202020202020202020202020202B2 +:101E100002020202020202020202020202020202A2 +:101E20000202020202020202020202020202020292 +:101E30000202020202020202020202020202020282 +:101E40000202020202020202020202020202020272 +:101E50000202020202020202020202020202020262 +:101E60000202020202020202020202020202020252 +:101E70000202020202020202020202020202020242 +:101E80000202020202020202020202020202020232 +:101E90000202020202020202020202020202020222 +:101EA0000202020202020202020202020202020212 +:101EB0000202020202020202020202020202010203 +:101EC0000101010101010101010101010101010102 +:101ED00001020101010101010101010101010101F1 +:101EE00002020201010202020101010201010102DA +:101EF00002020202020202020202020202020202C2 +:101F000002020202020202020202020202020202B1 +:101F100002020202020202020202020202020202A1 +:101F20000202020202020202020202020202020291 +:101F30000202020202020202020202020202020281 +:101F40000202020202020202020202020202020271 +:101F50000202020202020202020202020202020261 +:101F60000202020202020202020202020202020251 +:101F70000202020202020202020202020202020241 +:101F80000202020202020202020202020202020231 +:101F90000202020202020202020202020202020221 +:101FA0000202020202020202020202020202020211 +:101FB0000202020202020202020202020202020201 +:101FC0000101010101010101010101010101010101 +:101FD00001010101010101010101010101010101F1 +:101FE00002020201010101010101010101010102DD +:101FF00002020202020202020202020202020202C1 +:1020000002020202020202020202020202020202B0 +:1020100002020202020202020202020202020202A0 +:102020000202020202020202020202020202020290 +:102030000202020202020202020202020202020280 +:102040000202020202020202020202020202020270 +:102050000202020202020202020202020202020260 +:102060000202020202020202020202020202020250 +:102070000202020202020202020202020202020240 +:102080000202020202020202020202020202020230 +:102090000202020202020202020202020202020220 +:1020A0000202020202020202020202020202020210 +:1020B0000202020202020202020202020202020200 +:1020C0000101010101010101010101010101010100 +:1020D00001010101010101010101010101010101F0 +:1020E00001010201010101010101010101010102DE +:1020F00002020202010101010101010202020202C7 +:1021000002020202020202020202020202020202AF +:10211000020202020202020202020202020202029F +:10212000020202020202020202020202020202028F +:10213000020202020202020202020202020202027F +:10214000020202020202020202020202020202026F +:10215000020202020202020202020202020202025F +:10216000020202020202020202020202020202024F +:10217000020202020202020202020202020202023F +:10218000020202020202020202020202020202022F +:10219000020202020202020202020202020202021F +:1021A000020202020202020202020202020202020F +:1021B00002020202020202020202020202020202FF +:1021C00001010101010101010101010101010101FF +:1021D00001010101010101010101010101010101EF +:1021E00001010101010101010101010101010101DF +:1021F00002020201010101010101010101010202CA +:1022000002020202020202020202020202020202AE +:10221000020202020202020202020202020202029E +:10222000020202020202020202020202020202028E +:10223000020202020202020202020202020202027E +:10224000020202020202020202020202020202026E +:10225000020202020202020202020202020202025E +:10226000020202020202020202020202020202024E +:10227000020202020202020202020202020202023E +:10228000020202020202020202020202020202022E +:10229000020202020202020202020202020202021E +:1022A000020202020202020202020202020202020E +:1022B00002020202020202020202020202020202FE +:1022C00001010101010101010101010101010101FE +:1022D00001010101010101010101010101010101EE +:1022E00001010101010101010101010101010101DE +:1022F00002020101010101010101010101010102CB +:1023000002020202020202020202020202020202AD +:10231000020202020202020202020202020202029D +:10232000020202020202020202020202020202028D +:10233000020202020202020202020202020202027D +:10234000020202020202020202020202020202026D +:10235000020202020202020202020202020202025D +:10236000020202020202020202020202020202024D +:10237000020202020202020202020202020202023D +:10238000020202020202020202020202020202022D +:10239000020202020202020202020202020202021D +:1023A000020202020202020202020202020202020D +:1023B00002020202020202020202020202020202FD +:1023C00001010101010101010101010101010101FD +:1023D00001010101010101010101010101010101ED +:1023E00001010101010101010101010101010101DD +:1023F00002010101010101010101010101010102CB +:1024000002020202020101010101010102020202B3 +:10241000020202020202020202020202020202029C +:10242000020202020202020202020202020202028C +:10243000020202020202020202020202020202027C +:10244000020202020202020202020202020202026C +:10245000020202020202020202020202020202025C +:10246000020202020202020202020202020202024C +:10247000020202020202020202020202020202023C +:10248000020202020202020202020202020202022C +:10249000020202020202020202020202020202021C +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00001010101010101010101010101010101FC +:1024D00001010101010101010101010101010101EC +:1024E00001010101010101010101010101010101DC +:1024F00001010101010101010101010101010101CC +:1025000001010101010101010101010102020202B7 +:10251000020202020202020101010102020202029F +:10252000020202020202020202020202020202028B +:10253000020202020202020202020202020202027B +:10254000020202020202020202020202020202026B +:10255000020202020202020202020202020202025B +:10256000020202020202020202020202020202024B +:10257000020202020202020202020202020202023B +:10258000020202020202020202020202020202022B +:10259000020202020202020202020202020202021B +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C00001010101010101010101010101010101FB +:1025D00001010101010101010101010101010101EB +:1025E00001010101010101010101010101010101DB +:1025F00001010101010101010101010101010101CB +:1026000001010101010101010101010101020102B8 +:1026100002010101010101010101010101010102A8 +:10262000020202020202020202020202020202028A +:10263000020202020202020202020202020202027A +:10264000020202020202020202020202020202026A +:10265000020202020202020202020202020202025A +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202020202020202020202020202022A +:10269000020202020202020202020202020202021A +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C00001010101010101010101010101010101FA +:1026D00001010101010101010101010101010101EA +:1026E00001010101010101010101010101010101DA +:1026F00001010101010101010101010101010101CA +:1027000001010101010101010101010101010101B9 +:1027100001010101010101010101010101010102A8 +:10272000020202020202020101010202020202028C +:102730000202020202020202020202020202020279 +:102740000202020202020202020202020202020269 +:102750000202020202020202020202020202020259 +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:102780000202020202020202020202020202020229 +:102790000202020202020202020202020202020219 +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C00001010101010101010101010101010101F9 +:1027D00001010101010101010101010101010101E9 +:1027E00001010101010101010101010101010101D9 +:1027F00001010101010101010101010101010101C9 +:1028000001010101010101010101010101010101B8 +:1028100001010101010101010101010101010101A8 +:102820000202020201010101010101010202020290 +:102830000202020202020202020202020202020278 +:102840000202020202020202020202020202020268 +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C00001010101010101010101010101010101F8 +:1028D00001010101010101010101010101010101E8 +:1028E00001010101010101010101010101010101D8 +:1028F00001010101010101010101010101010101C8 +:1029000001010101010101010101010101010101B7 +:1029100001010101010101010101010101010101A7 +:102920000202010101010101010101010101010294 +:102930000202020202020202020202020202020277 +:102940000202020202020202020202020202020267 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C00001010101010101010101010101010101F7 +:1029D00001010101010101010101010101010101E7 +:1029E00001010101010101010101010101010101D7 +:1029F00001010101010101010101010101010101C7 +:102A000001010101010101010101010101010101B6 +:102A100001010101010101010101010101010101A6 +:102A20000101010101010101010101010101010295 +:102A3000020202020202020201010101010102027C +:102A40000202020202020202020202020202020266 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020202020202020226 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020202020202020202020202F6 +:102AC00001010101010101010101010101010101F6 +:102AD00001010101010101010101010101010101E6 +:102AE00001010101010101010101010101010101D6 +:102AF00001010101010101010101010101010101C6 +:102B000001010101010101010101010101010101B5 +:102B100001010101010101010101010101010101A5 +:102B20000101010101010101010101010101010195 +:102B30000202020101010101010101010101010281 +:102B40000202020202020202020202020202020265 +:102B50000202020202020202020202020202020255 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020202020202020225 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020202020202020202F5 +:102BC00001010101010101010101010101010101F5 +:102BD00001010101010101010101010101010101E5 +:102BE00001010101010101010101010101010101D5 +:102BF00001010101010101010101010101010101C5 +:102C000001010101010101010101010101010101B4 +:102C100001010101010101010101010101010101A4 +:102C20000101010101010101010101010101010194 +:102C30000101010101010101010101010101010283 +:102C4000020202020202020201010101010101026B +:102C50000202020202020202010201010202020257 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020202020202020202F4 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00001010101010101010101010101010101D4 +:102CF00001010101010101010101010101010101C4 +:102D000001010101010101010101010101010101B3 +:102D100001010101010101010101010101010101A3 +:102D20000101010101010101010101010101010193 +:102D30000101010101010101010101010101010183 +:102D40000101010101010101010101010101010272 +:102D5000020202010101010101010101010101025F +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020202020202F3 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00001010101010101010101010101010101D3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100001010101010101010101010101010101A2 +:102E20000101010101010101010101010101010192 +:102E30000101010101010101010101010101010182 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00001010101010101010101010101010101D2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100001010101010101010101010101010101A1 +:102F20000101010101010101010101010101010191 +:102F30000101010101010101010101010101010181 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000202020202020202010101010102010148 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000101010101010101010101010101010190 +:103030000101010101010101010101010101010180 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000010101010101010101010101010101018F +:10313000010101010101010101010101010101017F +:10314000010101010101010101010101010101016F +:10315000010101010101010101010101010101015F +:10316000010101010101010101010101010101014F +:103170000202020202020201010101010101010138 +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00001010101010101010101010101010101EF +:1031D00001010101010101010101010101010101DF +:1031E00001010101010101010101010101010101CF +:1031F00001010101010101010101010101010101BF +:1032000001010101010101010101010101010101AE +:10321000010101010101010101010101010101019E +:10322000010101010101010101010101010101018E +:10323000010101010101010101010101010101017E +:10324000010101010101010101010101010101016E +:10325000010101010101010101010101010101015E +:10326000010101010101010101010101010101014E +:10327000010101010101010101010101010101013E +:103280000202020202020202020201020101010222 +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00001010101010101010101010101010101EE +:1032D00001010101010101010101010101010101DE +:1032E00001010101010101010101010101010101CE +:1032F00001010101010101010101010101010101BE +:1033000001010101010101010101010101010101AD +:10331000010101010101010101010101010101019D +:10332000010101010101010101010101010101018D +:10333000010101010101010101010101010101017D +:10334000010101010101010101010101010101016D +:10335000010101010101010101010101010101015D +:10336000010101010101010101010101010101014D +:10337000010101010101010101010101010101013D +:10338000010101010101010101010101010101012D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00001010101010101010101010101010101ED +:1033D00001010101010101010101010101010101DD +:1033E00001010101010101010101010101010101CD +:1033F00001010101010101010101010101010101BD +:1034000001010101010101010101010101010101AC +:10341000010101010101010101010101010101019C +:10342000010101010101010101010101010101018C +:10343000010101010101010101010101010101017C +:10344000010101010101010101010101010101016C +:10345000010101010101010101010101010101015C +:10346000010101010101010101010101010101014C +:10347000010101010101010101010101010101013C +:10348000010101010101010101010101010101012C +:103490000202020201010101010101010101010118 +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00001010101010101010101010101010101EC +:1034D00001010101010101010101010101010101DC +:1034E00001010101010101010101010101010101CC +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000010101010101010101010101010101019B +:10352000010101010101010101010101010101018B +:10353000010101010101010101010101010101017B +:10354000010101010101010101010101010101016B +:10355000010101010101010101010101010101015B +:10356000010101010101010101010101010101014B +:10357000010101010101010101010101010101013B +:10358000010101010101010101010101010101012B +:10359000010101010101010101010101010101011B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00001010101010101010101010101010101EB +:1035D00001010101010101010101010101010101DB +:1035E00001010101010101010101010101010101CB +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000010101010101010101010101010101019A +:10362000010101010101010101010101010101018A +:10363000010101010101010101010101010101017A +:10364000010101010101010101010101010101016A +:10365000010101010101010101010101010101015A +:10366000010101010101010101010101010101014A +:10367000010101010101010101010101010101013A +:10368000010101010101010101010101010101012A +:10369000010101010101010101010101010101011A +:1036A0000202020202020202010202010101010100 +:1036B00002020202020202020202020202020202EA +:1036C00001010101010101010101010101010101EA +:1036D00001010101010101010101010101010101DA +:1036E00001010101010101010101010101010101CA +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010101010101010199 +:103720000101010101010101010101010101010189 +:103730000101010101010101010101010101010179 +:103740000101010101010101010101010101010169 +:103750000101010101010101010101010101010159 +:103760000101010101010101010101010101010149 +:103770000101010101010101010101010101010139 +:103780000101010101010101010101010101010129 +:103790000101010101010101010101010101010119 +:1037A0000101010101010101010101010101010109 +:1037B00002020202020202020202020202020201EA +:1037C00001010101010101010101010101010101E9 +:1037D00001010101010101010101010101010101D9 +:1037E00001010101010101010101010101010101C9 +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010101010101010178 +:103840000101010101010101010101010101010168 +:103850000101010101010101010101010101010158 +:103860000101010101010101010101010101010148 +:103870000101010101010101010101010101010138 +:103880000101010101010101010101010101010128 +:103890000101010101010101010101010101010118 +:1038A0000101010101010101010101010101010108 +:1038B00002010101010101010101010101010101F7 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00046000000000000000000000000000000B1 +:1039D00000010000000000000000000000000000E6 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000000000000F6 +:103AD00001010000000000000000000000000000E4 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000010000000024 +:103BA0000000000000000000000000010000000014 +:103BB0000000000000000000000000000000000005 +:103BC00000000000010100000000000000000000F3 +:103BD00001010000000000000000000000000000E3 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000100010000000022 +:103CA0000000000000000000000100010000000012 +:103CB0000000000000000000000000000000000004 +:103CC00000000000010100000000000001000000F1 +:103CD00001010000000000000000000000000000E2 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000100000000000000000052 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000101010000000020 +:103DA0000000000000000000000101010000000010 +:103DB0000000000000000000000000000000000003 +:103DC00000000000010100000000000001000000F0 +:103DD00001010000000000000000000000000000E1 +:103DE00000000000000000000000000000000100D2 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000001000000000000000091 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000100000000000000000051 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E9000000000000000000001010101010001001C +:103EA000000000000000000000010101010000000E +:103EB0000000000000000000000000000000000002 +:103EC00000000000010100000000000001000001EE +:103ED00001010000000000000000000000000000E0 +:103EE00000000000000000000000000000000100D1 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000001000000000000000090 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000100000000000000000050 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F9000000000000000000001010101010001001B +:103FA000000000000000000000010101010000000D +:103FB0000000000000000000000000000000000001 +:103FC00000000000010100000000000001000001ED +:103FD00001010001000000000000000000000000DE +:103FE00000000000000000000000000000010100CF +:103FF00000000000000000000001000000000101BE +:1040000000000100000000000000000000000000AF +:1040100000000000000000000000000000000000A0 +:10402000000000000000000100000000000000008F +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:10406000000000000000010000000000000000004F +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000010101010101010019 +:1040A000000000000000000000010101010100010A +:1040B0000000000000000000000000000000000000 +:1040C00000000000010100000000000001000001EC +:1040D00002020001000000000100000000000000DA +:1040E00000000000000000000000000000010100CE +:1040F00000000000000000000001000000000101BD +:1041000000000100000000000000000000000000AE +:10411000010000000000000000000000000000009E +:10412000000000000000000100000000000000008E +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000010000000000000000004E +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:104190000000000000000000010101010101010018 +:1041A0000000000000000000000101010101000109 +:1041B00000000000000000000000000000000000FF +:1041C00000000000010100000000000001000001EB +:1041D00002020001000001000100010000000000D7 +:1041E00000000000000000000000000000010100CD +:1041F00000000000000000000001000000010101BB +:1042000001000100000000000000000000000000AC +:10421000010000000000000100000000000000009C +:10422000000000000000000100000000000000008D +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000101015B +:10426000000000000000010000000000000000004D +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:104290000000000000000000010101010101010017 +:1042A0000000000000000000000101010101000108 +:1042B00000000000000000000000000000000000FE +:1042C00000000000010100000000000002000001E9 +:1042D00002020001000001000100010000000001D5 +:1042E00000000000000000000000000000010100CC +:1042F00000000000000000000001010100010101B8 +:1043000001000100000000000000000000000000AB +:104310000100000000000001000000000001010099 +:10432000000000000000000100000000000000008C +:10433000000000000000000001000000000000007C +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000101015A +:10436000000000000000010000000000000000004C +:10437000000000000000000000000000000000003D +:10438000000000000000000000000101000000002B +:104390000000000000000000010101010101010016 +:1043A0000000000000000101000101010101000105 +:1043B00000000001000000000000000000000000FC +:1043C00000000000010100000000000002000001E8 +:1043D00002020001000001000100010000000001D4 +:1043E00000000000000000010000000000010100CA +:1043F00000000000000000000001010100010101B7 +:1044000001000100000000000000000100000000A9 +:104410000101000000000001000000000001010097 +:10442000000000000000000100000000000000008B +:10443000000000000000000001000000000000007B +:10444000000000000000000000000000000000006C +:104450000000000100000000000000000001010158 +:10446000000000000000010000000100000000004A +:10447000000000000000000000000000000000003C +:104480000000000000000000000101010000000029 +:104490000000000000000000010101010101010015 +:1044A0000000000000000101000101010101010103 +:1044B00001000001000000000000000000000000FA +:1044C00000000000010100000100000002000002E5 +:1044D00002020001000001000100010000010001D2 +:1044E00000000000000000010000000000010100C9 +:1044F00000000000000000000001010100010101B6 +:1045000001000100000000000000000100000000A8 +:104510000101000000000001000100000001010095 +:10452000000000000000000100000000000000008A +:104530000000000000000000010100000000010078 +:10454000000000000000000000000000000000006B +:104550000000000100000000000000000001010157 +:104560000000000000000100010101000000000047 +:10457000000000000000000000000000000000003B +:104580000000000000000000000101010000000028 +:104590000000000000000000010101010101010014 +:1045A0000001000000010101000101010101010100 +:1045B00001000001000000000000000000000000F9 +:1045C00000000000010100000100000002000002E4 +:1045D00002020001000001000100010000010001D1 +:1045E00000000000010000010000000000010100C7 +:1045F00000000000000000000001010100010101B5 +:1046000001000100000000000000000100000000A7 +:104610000101000000000101000100000001010093 +:104620000000000101000001000000000000000087 +:104630000000000000000000010101000000010076 +:104640000000000000000001000000000000000069 +:104650000000000100000000000000000001010156 +:104660000000000000000100010101010000000045 +:104670000000000000000001000000000000000039 +:104680000000000000000000000101010100000026 +:104690000000000000000000010101010101010013 +:1046A00001010000000101010001010101010101FE +:1046B00001000001000000000000000000000000F8 +:1046C00000000000010100000101000002000002E2 +:1046D00002020002000001000100010000010101CE +:1046E00000000000010000010000000000010100C6 +:1046F00000000000000000000001010100010101B4 +:1047000001000100010000000100000100000000A4 +:104710000101000000000101000100000001010191 +:104720000000000101000001000000000000000086 +:104730000000000000000000010101000001010173 +:104740000000000000000001000000000000000068 +:104750000000000100000000000000000001010155 +:104760000000000000010100010101010000000043 +:104770000000000000000001000000000000000038 +:104780000000000000000100000101010100000024 +:104790000000000000000000010101010101010012 +:1047A00001010000010101010001010101010101FC +:1047B00001010001000001010000000000000000F4 +:1047C00000000000010100000101010002000002E0 +:1047D00002020002000001000100010000010101CD +:1047E00000000000010000010000000000010100C5 +:1047F00000000000000000000001010100010101B3 +:1048000001000100010000000100000100000000A3 +:10481000010100000100010100010100000101018E +:104820000000000101000001000000000000000085 +:104830000001000000000001010101000001010170 +:104840000000000000000001000000010000000066 +:104850000000000100000000010000000001010153 +:104860000000000000010100010101010000000042 +:104870000000000000000101000000000100000035 +:104880000000000000000100000101010101010120 +:104890000000000000000000010101010101010011 +:1048A00001010100010101010001010101010101FA +:1048B00001010001000001010000000000000000F3 +:1048C00000000000010100000201010002010002DD +:1048D00002020002000001000101010000010101CB +:1048E00000000000010000010000000000010100C4 +:1048F00000000000000000000001010100010101B2 +:1049000001000100010000000100000100000000A2 +:10491000010100000100010100010100000101018D +:104920000100010101000001000000000000000082 +:10493000000100000000000101010100000101016F +:104940000000000000000001000000010000000065 +:104950000000000100000000010000000001010152 +:104960000000000000010101010101010000000040 +:104970000000000000000101000000000100000034 +:10498000000000000000010000010101010101011F +:10499000000000010000000101010101010101000E +:1049A00001010100010101010001010101010101F9 +:1049B00001010001010101010000000000000000F0 +:1049C00000000000010100000202010102010002DA +:1049D00002020002000001000201010000010101C9 +:1049E00000000000010000010000000000010100C3 +:1049F00000000000000000000001010100010101B1 +:104A000001000100010000000100000100000000A1 +:104A1000010100000100010100010100000101018C +:104A20000100010101000001000000000000000081 +:104A3000000100010000000101010100000101016D +:104A40000000000100000001000000010000000063 +:104A5000000000010100010001010000000101014E +:104A6000010000000001010101010101000000003E +:104A70000000000000000101000000000101010130 +:104A8000000000000000010000010101010101011E +:104A9000000000010000000101010101010101000D +:104AA00001010100010101010001010101010101F8 +:104AB00001010101010101010000000000000000EE +:104AC00000000000010100000202020102020102D6 +:104AD00002020002000002000201010000010101C7 +:104AE00000000000010000010000000000010100C2 +:104AF00000000000000000000002010100010101AF +:104B0000010001010100000001000001000000009F +:104B1000010100000100010101010100000101018A +:104B2000010001010100000101000000000000007F +:104B3000000101010000000101010100000101016B +:104B40000000000100000001010000010000000061 +:104B5000000000010100010001010100000101014C +:104B60000101000101010101010101010100010038 +:104B7000000000000000010100000000010101012F +:104B8000000000000000010000010101010101011D +:104B9000000000010000010101010101010101000B +:104BA00001010100010101010001010101010101F7 +:104BB00001010101010101010000000000000000ED +:104BC00000000000010100000202020202020102D4 +:104BD00002020002000002000201020000010101C5 +:104BE00000000000010000010000000000020200BF +:104BF00000000000000000000002010101010101AD +:104C0000010001010100000001000001000000009E +:104C10000101000001000101010101000001010189 +:104C2000010101010100010101000000000000007C +:104C30000001010100010001010101000001010169 +:104C40000000000100000001010000010000000060 +:104C5000000100010100010001010100000101014A +:104C60000101000101010101010101010100010037 +:104C7000000000000000010100000000010101012E +:104C8000000000000000010001010101010101011B +:104C90000100000100000101010101010101010009 +:104CA00001010100010101010001010101010101F6 +:104CB00001010101010101010000000000000000EC +:104CC00000000000010100000202020202020202D2 +:104CD00002020002000002000201020001010101C3 +:104CE00000000000010000010000000100020200BD +:104CF00000000000000000000002010101010101AC +:104D0000010001010100010101000001000000009B +:104D10000101000001000101010101000001010188 +:104D2000010101010100010101000000000000007B +:104D30000001010100010001010101000001010168 +:104D4000010000010000000101010001010000005C +:104D50000001000101000100010101010001010148 +:104D60000101000101010101010101010101010134 +:104D7000000000000000010100000000010101012D +:104D80000000000100010100010101010101010118 +:104D90000101000100010101010101010101010006 +:104DA00001010100010101010001010101010101F5 +:104DB00001010101010101010000010100000000E9 +:104DC00000000000010100000202020202020202D1 +:104DD00002020002000102000201020001020101C0 +:104DE00000000000010000010100000100020201BA +:104DF00000000000000000000002020101010101AA +:104E00000100010101000101010001010000000099 +:104E10000101000001000101010101000001010187 +:104E2000010101010100010101000000000000007A +:104E30000001010100010001010101000001010167 +:104E40000100000101000101010100010100000059 +:104E50000001000101000100010101010001010147 +:104E60000101010101010101010101010101010132 +:104E7000000000000000010100000000010101012C +:104E80000100000100010100010101010101010116 +:104E90000101000100010101010101010101010005 +:104EA00001010100010101010001010101010101F4 +:104EB00001010101010101010001010100000000E7 +:104EC00000000000010100000202020202020202D0 +:104ED00002020202000102000202020001020102BB +:104EE00000000000010000010100000100020201B9 +:104EF00000000001010001010002020201020201A2 +:104F00000100010101000101010001010000000098 +:104F10000101000001000101010101000001010186 +:104F20000101010101000101010000000100000078 +:104F30000001010100010001020101000001010165 +:104F40000100000101000101010100010101000057 +:104F50000001010101000100010101010001010145 +:104F60000101010101010101010101010101010131 +:104F7000000000000000010100000000010101012B +:104F80000100000100010100010101010101010115 +:104F90000101000101010101010101010101010003 +:104FA00001010100010101010001010101010101F3 +:104FB00001010101010101010001010100000000E6 +:104FC00000000000010100000202020202020202CF +:104FD00002020202000102000202020001020202B9 +:104FE00000000001010000010100000100020201B7 +:104FF000010000010100010100020202010202029F +:105000000100020101000101020001010000000095 +:105010000101000001010101010201010001010182 +:105020000101010101000101010000000100000077 +:105030000001010101010001020101010001010162 +:105040000100000101000101010101010101000055 +:105050000001010101010100010101010001010143 +:105060000101010101010101010101010101010130 +:105070000000000000010101000000000101010129 +:105080000100000100010100010101010101010114 +:1050900001010101010101010202010101010100FF +:1050A00001010100010101010002010101010101F1 +:1050B00001010101010101010001010101000000E4 +:1050C00000000000010100000202020202020202CE +:1050D00002020202000102000202020001020202B8 +:1050E00000000001020000010100000100020201B5 +:1050F000010000010100010100020202010202029E +:105100000200020101000101020001020000000092 +:105110000101000001010101010201010001010181 +:105120000101010101000101010100000101000074 +:105130000001010101010001020201010001010160 +:105140000100000101000101010101010101010152 +:105150000001010101010100010101010001010142 +:10516000010101010101010101010101010101012F +:105170000000000000010101000000000101010128 +:105180000101000100010100010101010101010112 +:1051900001010101010101010202010101010100FE +:1051A00001010100010101010002010101010101F0 +:1051B00001010101010101010001010101000000E3 +:1051C00000000000010100000202020202020202CD +:1051D00002020202000202000202020002020202B5 +:1051E00000000001020001010200000101020201B1 +:1051F000010000010100010100020202010202029D +:105200000200020101000101020001020000000091 +:10521000020100000101010101020101000201017E +:105220000101010101000101010100000101000073 +:10523000000101010101000102020101000101015F +:105240000101000101000101010101010101010150 +:10525000000101010101010101010101010101013F +:10526000010101010101010101010101010101012E +:105270000000000100010101000000000101010126 +:105280000101000100010100010101010101010111 +:1052900001010101010101010202020201010100FB +:1052A00001010100010101010002020201010101ED +:1052B00001010101010101010001010101010101DF +:1052C00000000000010100000202020202020202CC +:1052D00002020202000202000202020002020202B4 +:1052E00000000001020001010200000201020201AF +:1052F000010100010100010100020202010202029B +:105300000200020101000101020001020000000090 +:10531000020100000101010102020201000202017A +:105320000101010101000101020100000101010070 +:10533000000101010101000102020201000101015D +:10534000010100010100010101010101010101014F +:10535000000101010101010101010101010101013E +:10536000010101010101010102010101010101012C +:105370000100000100010101000001000101010123 +:10538000010100010101010101010101010101010E +:1053900001010101010101010202020201010100FA +:1053A00001010100010101010002020201010101EC +:1053B00001010101010101010001010101010101DE +:1053C00000000000010100000202020202020202CB +:1053D00002020202000202000202020002020202B3 +:1053E00000010001020001010200000201020201AD +:1053F0000101000101000101010202020202020298 +:10540000020002010100010102000102000000008F +:105410000202000001010101020202010002020178 +:10542000010101010100010102010100010101006E +:10543000000101010101010102020201000101015B +:10544000010100010100010101010101010101014E +:10545000000101010101010102010101010101013C +:10546000010101010101010102020101010101012A +:105470000100000100010101010101000101010120 +:10548000010101010101010101010101010101010C +:1054900001010101010101010202020202010100F8 +:1054A00001010100010101010002020202010101EA +:1054B00001010101010101010001010101010101DD +:1054C00000000000010100000202020202020202CA +:1054D00002020202000202000202020002020202B2 +:1054E00001010101020001010200000201020202A9 +:1054F0000101000101000101010202020202020297 +:105500000201020101000101020101020001010189 +:105510000202010001010101020202010102020175 +:10552000010101010100010102010100010101006D +:105530000001010101010101020202010102020157 +:10554000010100010100010102010101010101014C +:10555000000101010101010102010101010201013A +:105560000101010101010101020202010101010128 +:10557000010000010001010101010100010101011F +:10558000010101010101010101020101010101010A +:1055900001010101010101010202020202010100F7 +:1055A00001010101010101010002020202010101E8 +:1055B00001010101010101010001010101010101DC +:1055C00000000000010100000202020202020202C9 +:1055D00002020202010202000202020002020202B0 +:1055E00001010101020001010200000202020202A7 +:1055F0000201010101000101010202020202020294 +:105600000201020102000101020102020001010186 +:105610000202010001010101020202010102020273 +:10562000010101010100010102010100010101006C +:105630000001010101010101020202010102020156 +:10564000010100010100010102010102010101014A +:105650000001010101010101020201010102020137 +:105660000101010101010101020202010101010127 +:10567000010000010101010101010100010101011D +:105680000101010101010101010202010101010108 +:1056900001010101010101010202020202020201F3 +:1056A00001010101010101010002020202020101E6 +:1056B00001010101010101010001010101010101DB +:1056C00000000000010100000202020202020202C8 +:1056D00002020202020202000202020002020202AE +:1056E00001020101020001020200010202020202A3 +:1056F0000201010101000101020202020202020292 +:105700000201020102010101020102020001010184 +:105710000202010001010101020202010102020272 +:105720000201010101000101020201000101010168 +:105730000002010101010101020202010102020253 +:105740000101000101000101020201020101010148 +:105750000101010101010101020201010102020234 +:105760000101010101010101020202020101010125 +:10577000010000010101010101010101010101011B +:105780000101010101010101010202020101010106 +:1057900001010101010101010202020202020201F2 +:1057A00001010101010101010002020202020101E5 +:1057B00001010101010101010001010101010101DA +:1057C00000000001010100010202020202020202C5 +:1057D00002020202020202000202020102020202AC +:1057E000020202020200010202000102020202029F +:1057F000020201020200010102020202020202028E +:105800000201020102010101020102020001010183 +:10581000020201000201010102020202010202026F +:105820000201020202010102020201010201010160 +:105830000002010101010101020202010102020252 +:105840000101000101000101020201020101010147 +:105850000101010101010101020202010102020232 +:105860000101010101010101020202020101010124 +:105870000101000101010101010101010201010118 +:105880000101010101010101020202020101010104 +:1058900001010101010101010202020202020201F1 +:1058A00001010101010101010002020202020102E3 +:1058B00001010101010101010001010101010101D9 +:1058C00001000001020100010202020202020202C2 +:1058D00002020202020202000202020202020202AA +:1058E000020202020200010202000202020202029D +:1058F000020201020200010102020202020202028D +:105900000201020202010101020202020001010180 +:10591000020201000201010102020202010202026E +:10592000020202020201010202020101020101015E +:10593000010202010101010102020202010202024E +:105940000101010101000101020201020201010144 +:105950000101010201010101020202010102020230 +:105960000101010101010201020202020101010122 +:105970000101010101010101010101010201010116 +:105980000101010101010101020202020201010102 +:1059900001010101010101010202020202020201F0 +:1059A00001010101010101010002020202020202E1 +:1059B00001010101010101010001010101010101D8 +:1059C00001010001020201010202020202020202BE +:1059D00002020202020202000202020202020202A9 +:1059E000020202020200010202020202020202029A +:1059F000020202020200010102020202020202028B +:105A0000020102020201010102020202000101017F +:105A1000020201010201010202020202010202026B +:105A2000020202020201010202020201020201015B +:105A3000010202020101010102020202010202024C +:105A40000201010101010101020202020201010140 +:105A5000010101020101010102020202010202022E +:105A60000101010101010201020202020201010120 +:105A70000101010101010101010101010202010114 +:105A80000101010101010101020202020201010101 +:105A900001010101010101010202020202020201EF +:105AA00001010101010101010002020202020202E0 +:105AB00002010101010101010002010101010101D5 +:105AC00001010101020201010202020202020202BC +:105AD00002020202020202000202020202020202A8 +:105AE0000202020202000102020202020202020299 +:105AF0000202020202010101020202020202020289 +:105B0000020202020201010102020202010201017B +:105B10000202010102010202020202020202020268 +:105B2000020202020201010202020201020201015A +:105B3000010202020101010102020202010202024B +:105B4000020101020101010102020202020201013D +:105B5000010201020101010102020202010202022C +:105B6000020101010101020102020202020101011E +:105B70000101010101010101020101010202020111 +:105B800001010101010101010202020202020101FF +:105B900001010101010101010202020202020201EE +:105BA00002020101010101010002020202020202DD +:105BB00002010101010101010002020101010101D3 +:105BC00001010101020201010202020202020202BB +:105BD00001010202020202000202020202020202A9 +:105BE0000202020202010102020202020202020297 +:105BF0000202020202010101020202020202020288 +:105C00000202020202010101020202020102020179 +:105C10000202010102010202020202020202020267 +:105C20000202020202010102020202010202020158 +:105C30000102020201010101020202020202020249 +:105C4000020101020101010102020202020201013C +:105C5000010201020201010102020202010202022A +:105C6000020201010101020102020202020202011A +:105C7000010101010101010102020101020202020E +:105C800001010101010101010202020202020201FD +:105C900001010101010101010202020202020201ED +:105CA00002020101010101010102020202020202DB +:105CB00002020102010101010002020201010101CF +:105CC00001010101020201010202020202020202BA +:105CD00001010201020202000202020202020202A9 +:105CE0000202020202010102020202020202020296 +:105CF0000202020202010201020202020202020286 +:105D00000202020202010101020202020102020277 +:105D10000202020102010202020202020202020265 +:105D20000202020202010102020202020202020156 +:105D30000102020202020101020202020202020246 +:105D40000202010202010102020202020202020137 +:105D50000102020202010101020202020202020227 +:105D60000202010101020201020202020202020118 +:105D7000010101010101010102020201020202020C +:105D800001010101010101010202020202020202FB +:105D900001010101010101010202020202020201EC +:105DA00002020201010101010102020202020202D9 +:105DB00002020102010101010002020201010101CE +:105DC00001010101020201010202020202020201BA +:105DD00001010201020201000202020202020202A9 +:105DE0000202020202010102020202020202020295 +:105DF0000202020202010201020202020202020285 +:105E00000202020202010201020202020202020274 +:105E10000202020102010202020202020202020264 +:105E20000202020202010102020202020202020155 +:105E30000102020202020102020202020202020244 +:105E40000202010202010102020202020202020235 +:105E50000102020202010101020202020202020226 +:105E60000202020202020201020202020202020213 +:105E7000010101010101010102020201020202020B +:105E800002010101010101010202020202020202F9 +:105E900001010101010101010202020202020201EB +:105EA00002020201020202010102020202020202D5 +:105EB00002020202010101010002020202010101CB +:105EC00001010101020201010202020202020201B9 +:105ED00001010101020201000202020202020202A9 +:105EE0000202020202010202020202020202020293 +:105EF0000202020202010202020202020202020283 +:105F00000202020202010201020202020202020273 +:105F10000202020102020202020202020202020262 +:105F20000202020202010202020202020202020252 +:105F30000102020202020102020202020202020243 +:105F40000202010202010102020202020202020234 +:105F50000102020202010201020202020202020224 +:105F60000202020202020201020202020202020212 +:105F7000010101010101010102020201020202020A +:105F800002010101010102010202020202020202F7 +:105F900002010101010101010202020202020201E9 +:105FA00002020201020202020102020202020202D3 +:105FB00002020202020101010002020202010101C9 +:105FC00001010101020201010202020201020201B9 +:105FD00001010101020101000202020202020202A9 +:105FE0000202020202010202020202020202020292 +:105FF0000202020202010202020202020202020282 +:106000000202020202010202020202020202020271 +:106010000202020102020202020202020202020261 +:106020000202020202010202020202020202020251 +:106030000202020202020102020202020202020241 +:106040000202010202010202020202020202020232 +:106050000102020202010201020202020202020223 +:106060000202020202020201020202020202020211 +:106070000101010101010202020202020202020206 +:1060800002020102010102010202020202020202F4 +:1060900002020102010101010202020202020201E6 +:1060A00002020201020202020202020202020202D1 +:1060B00002020202020202010002020202020101C5 +:1060C00001010101020201010202020201010101BA +:1060D00001010101020101000202020202020202A8 +:1060E0000202020202010202020202020202020291 +:1060F0000202020202010202020202020202020281 +:106100000202020202010202020202020202020270 +:106110000202020102020202020202020202020260 +:106120000202020202010202020202020202020250 +:106130000202020202020102020202020202020240 +:106140000202020202010202020202020202020230 +:106150000202020202020201020202020202020220 +:10616000020202020202020202020202020202020F +:106170000201010101010202020202020202020204 +:1061800002020102010202010202020202020202F2 +:1061900002020102010101010202020202020201E5 +:1061A00002020201020202020202020202020202D0 +:1061B00002020202020202020002020202020201C2 +:1061C00001010101020201010202020201010101B9 +:1061D00001010101010101000202020202020202A8 +:1061E000020202020202020202020202020202028F +:1061F000020202020202020202020202020202027F +:10620000020202020202020202020202020202026E +:10621000020202010202020202020202020202025F +:10622000020202020201020202020202020202024F +:10623000020202020202010202020202020202023F +:10624000020202020201020202020202020202022F +:10625000020202020202020102020202020202021F +:10626000020202020202020202020202020202020E +:106270000201010101010202020202020202020203 +:1062800002020202010202010202020202020202F0 +:1062900002020202010101010202020202020201E3 +:1062A00002020201020202020202020202020202CF +:1062B00002020202020202020102020202020202BF +:1062C00001010101020201010202020101010101B9 +:1062D00001010101010101000202020202020202A7 +:1062E000020202020202020202020202020202028E +:1062F000020202020202020202020202020202027E +:10630000020202020202020202020202020202026D +:10631000020202020202020202020202020202025D +:10632000020202020201020202020202020202024E +:10633000020202020202010202020202020202023E +:10634000020202020201020202020202020202022E +:10635000020202020202020102020202020202021E +:10636000020202020202020202020202020202020D +:106370000201010201020202020202020202020200 +:1063800002020202020202010202020202020202EE +:1063900002020202020202020202020202020201DE +:1063A00002020201020202020202020202020202CE +:1063B00002020202020202020102020202020202BE +:1063C00001010101020201010202010101010101B9 +:1063D00001010101010101000202020202020202A6 +:1063E000020202020202020202020202020202028D +:1063F000020202020202020202020202020202027D +:10640000020202020202020202020202020202026C +:10641000020202020202020202020202020202025C +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020201020202020202020202022D +:10645000020202020202020102020202020202021D +:10646000020202020202020202020202020202020C +:1064700002020102010202020202020202020202FE +:1064800002020202020202010202020202020202ED +:1064900002020202020202020202020202020202DC +:1064A00002020201020202020202020202020202CD +:1064B00002020202020202020202020202020202BC +:1064C00001010101020201010201010101010101B9 +:1064D00001010101010101000202020202020202A5 +:1064E000020202020102020202020202020202028D +:1064F000020202020202020202020202020202027C +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020102020202020202021C +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202010202020202020202EC +:1065900002020202020202020202020202020202DB +:1065A00002020201020202020202020202020202CC +:1065B00002020202020202020202020202020202BB +:1065C00002010101020201010101010101010101B8 +:1065D00001010101010101010202020202020202A3 +:1065E000020101020102020202020202020202028E +:1065F000020202020202020202020202020202027B +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020202020202020202020202020202024A +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202010202020202020202EB +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020101020201010101010101010101B6 +:1066D00001010101010101010202020202010101A5 +:1066E000010101010102020202020202020202028F +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:106720000202020202020202020202020202020249 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800002020202020202020202020202020202E9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020201010101010101010101B3 +:1067D00001010101010101010202020201010101A5 +:1067E000010101010102020202020202020202028E +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00002020202020201010101010101010101B2 +:1068D00001010101010101010202010201010101A5 +:1068E0000101010101020201020202020201010191 +:1068F000010101010102020202020202020202027D +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:106930000202020202020202020202020202020237 +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:1069800002020202020202020202020202020202E7 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020201010101010101010101B1 +:1069D00001010101010101010101010101010101A7 +:1069E0000101010101010201020202020201010191 +:1069F000010101010102020202020202020202027C +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A30000202020202020202020202020202020236 +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002020202020202020202020202020202F6 +:106A800002020202020202020202020202020202E6 +:106A900002020202020202020202020202020202D6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020101010101010101AE +:106AD00001010101010101010101010101010101A6 +:106AE0000101010101010101020202010101010193 +:106AF000010101010102020202020202020202027B +:106B00000202010202020202020202020202020266 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020202020202020202020202020235 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002020202020202020202020202020202F5 +:106B800002020202020202020202020202020202E5 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020101010101010101AD +:106BD00001010101010101010101010101010101A5 +:106BE0000101010101010101020202010101010192 +:106BF000010101010101010202020202020101017F +:106C00000101010201020202020202020202020268 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020202020202020202020202020234 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002020202020202020202020202020202F4 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020101010101010101AC +:106CD00001010101010101010101010101010101A4 +:106CE0000101010101010101010201010101010193 +:106CF0000101010101010101020101010101010183 +:106D00000101010101020202020202020202020268 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020202020202020202020202020233 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002020202020202020202020202020202F3 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020101010101010101AB +:106DD00001010101010101010101010101010101A3 +:106DE0000101010101010101010101010101010193 +:106DF0000101010101010101020101010101010182 +:106E00000101010101020202020202020202020267 +:106E10000101010201020202020202020202020256 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002020202020202020202020202020202F2 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020101010101010101AA +:106ED00001010101010101010101010101010101A2 +:106EE0000101010101010101010101010101010192 +:106EF0000101010101010101020101010101010181 +:106F0000010101010101010202020201020101016C +:106F10000101010201020202020202020202020255 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020101010101010101A9 +:106FD00001010101010101010101010101010101A1 +:106FE0000101010101010101010101010101010191 +:106FF0000101010101010101010101010101010181 +:10700000010101010101010101020101010101016F +:10701000010101010101010102020202020101015B +:107020000101010101020202020202020202020245 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020101010101010101A8 +:1070D00001010101010101010101010101010101A0 +:1070E0000101010101010101010101010101010190 +:1070F0000101010101010101010101010101010180 +:10710000010101010101010101010101010101016F +:10711000010101010101010102010101010101015E +:107120000101010101020201020202020202020245 +:107130000201010101020202020202020202020233 +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C00002020202020202020101010101010101A7 +:1071D000010101010101010101010101010101019F +:1071E000010101010101010101010101010101018F +:1071F000010101010101010101010101010101017F +:10720000010101010101010101010101010101016E +:10721000010101010101010101010101010101015E +:10722000010101010101010102020202010101014A +:107230000101010101010202020202020202020234 +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C00002020202020202020101010101010101A6 +:1072D000010101010101010101010101010101019E +:1072E000010101010101010101010101010101018E +:1072F000010101010101010101010101010101017E +:10730000010101010101010101010101010101016D +:10731000010101010101010101010101010101015D +:10732000010101010101010101010101010101014D +:107330000101010101010201020202020201010137 +:107340000101010101020202020202020202020222 +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C00002020202020202020101010101010101A5 +:1073D000010101010101010101010101010101019D +:1073E000010101010101010101010101010101018D +:1073F000010101010101010101010101010101017D +:10740000010101010101010101010101010101016C +:10741000010101010101010101010101010101015C +:10742000010101010101010101010101010101014C +:10743000010101010101010101010101010101013C +:107440000101010101010101020202020202020224 +:107450000201010101020202020202020202020210 +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C00002020202020202020101010101010101A4 +:1074D000010101010101010101010101010101019C +:1074E000010101010101010101010101010101018C +:1074F000010101010101010101010101010101017C +:10750000010101010101010101010101010101016B +:10751000010101010101010101010101010101015B +:10752000010101010101010101010101010101014B +:10753000010101010101010101010101010101013B +:107540000101010101010101020202010101010128 +:107550000101010101010102020202020202020212 +:1075600002020202020202020202020202020202FB +:1075700002020202020202020202020202020202EB +:1075800002020202020202020202020202020202DB +:1075900002020202020202020202020202020202CB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C00002020202020202020101010101010101A3 +:1075D000010101010101010101010101010101019B +:1075E000010101010101010101010101010101018B +:1075F000010101010101010101010101010101017B +:10760000010101010101010101010101010101016A +:10761000010101010101010101010101010101015A +:10762000010101010101010101010101010101014A +:10763000010101010101010101010101010101013A +:10764000010101010101010101010101010101012A +:107650000101010101010102020202020201010114 +:107660000101010101010102020202020202020201 +:1076700002020202020202020202020202020202EA +:1076800002020202020202020202020202020202DA +:1076900002020202020202020202020202020202CA +:1076A00002020202020202020202020202020202BA +:1076B00002020202020202020202020202020202AA +:1076C00002020202020202020101010101010101A2 +:1076D000010101010101010101010101010101019A +:1076E000010101010101010101010101010101018A +:1076F000010101010101010101010101010101017A +:107700000101010101010101010101010101010169 +:107710000101010101010101010101010101010159 +:107720000101010101010101010101010101010149 +:107730000101010101010101010101010101010139 +:107740000101010101010101010101010101010129 +:107750000101010101010101010101010101010119 +:107760000101010101010101020202020202020201 +:1077700002020202020202020202020202020202E9 +:1077800002020202020202020202020202020202D9 +:1077900002020202020202020202020202020202C9 +:1077A00002020202020202020202020202020202B9 +:1077B00002020202020202020202020202020202A9 +:1077C00002020202020202020101010101010101A1 +:1077D0000101010101010101010101010101010199 +:1077E0000101010101010101010101010101010189 +:1077F0000101010101010101010101010101010179 +:107800000101010101010101010101010101010168 +:107810000101010101010101010101010101010158 +:107820000101010101010101010101010101010148 +:107830000101010101010101010101010101010138 +:107840000101010101010101010101010101010128 +:107850000101010101010101010101010101010118 +:107860000101010101010101010101010101010108 +:1078700001010101010101010202020202020202F0 +:1078800002020202020202020202020202020202D8 +:1078900002020202020202020202020202020202C8 +:1078A00002020202020202020202020202020202B8 +:1078B00002020202020202020202020202020202A8 +:1078C00002020202020202020101010101010101A0 +:1078D0000101010101010101010101010101010198 +:1078E0000101010101010101010101010101010188 +:1078F0000101010101010101010101010101010178 +:107900000101010101010101010101010101010167 +:107910000101010101010101010101010101010157 +:107920000101010101010101010101010101010147 +:107930000101010101010101010101010101010137 +:107940000101010101010101010101010101010127 +:107950000101010101010101010101010101010117 +:107960000101010101010101010101010101010107 +:1079700001010101010101010202020201010101F3 +:1079800001010101010101020202020202020202DE +:1079900002020202020202020202020202020202C7 +:1079A00002020202020202020202020202020202B7 +:1079B00002020202020202020202020202020202A7 +:1079C000020202020202020201010101010101019F +:1079D0000101010101010101010101010101010197 +:1079E0000101010101010101010101010101010187 +:1079F0000101010101010101010101010101010177 +:107A00000101010101010101010101010101010166 +:107A10000101010101010101010101010101010156 +:107A20000101010101010101010101010101010146 +:107A30000101010101010101010101010101010136 +:107A40000101010101010101010101010101010126 +:107A50000101010101010101010101010101010116 +:107A60000101010101010101010101010101010106 +:107A700001010101010101010101010101010101F6 +:107A800001010101010101010202020202020202DE +:107A900002020202020202020202020202020202C6 +:107AA00002020202020202020202020202020202B6 +:107AB00002020202020202020202020202020202A6 +:107AC000020202020202020201010101010101019E +:107AD0000101010101010101010101010101010196 +:107AE0000101010101010101010101010101010186 +:107AF0000101010101010101010101010101010176 +:107B00000101010101010101010101010101010165 +:107B10000101010101010101010101010101010155 +:107B20000101010101010101010101010101010145 +:107B30000101010101010101010101010101010135 +:107B40000101010101010101010101010101010125 +:107B50000101010101010101010101010101010115 +:107B60000101010101010101010101010101010105 +:107B700001010101010101010101010101010101F5 +:107B800001010101010101010101010101010101E5 +:107B900001010101010101010101010101010102D4 +:107BA00001010102010101010202020202020202BC +:107BB00002020202020202020202020202020202A5 +:107BC000020202020202020201010101010101019D +:107BD0000101010101010101010101010101010195 +:107BE0000101010101010101010101010101010185 +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101010101010101010134 +:107C40000101010101010101010101010101010124 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010101010101010101E4 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101010201010101010101C3 +:107CB00001010101010101010202020202020202AC +:107CC000020202020202020201010101010101019C +:107CD0000101010101010101010101010101010194 +:107CE0000101010101010101010101010101010184 +:107CF0000101010101010101010101010101010174 +:107D00000101010101010101010101010101010163 +:107D10000101010101010101010101010101010153 +:107D20000101010101010101010101010101010143 +:107D30000101010101010101010101010101010133 +:107D40000101010101010101010101010101010123 +:107D50000101010101010101010101010101010113 +:107D60000101010101010101010101010101010103 +:107D700001010101010101010101010101010101F3 +:107D800001010101010101010101010101010101E3 +:107D900001010101010101010101010101010101D3 +:107DA00001010101010101010101010101010101C3 +:107DB00001010101010101010202020202020202AB +:107DC000020202020101020201010101010101019D +:107DD0000101010101010101010101010101010193 +:107DE0000101010101010101010101010101010183 +:107DF0000101010101010101010101010101010173 +:107E00000101010101010101010101010101010162 +:107E10000101010101010101010101010101010152 +:107E20000101010101010101010101010101010142 +:107E30000101010101010101010101010101010132 +:107E40000101010101010101010101010101010122 +:107E50000101010101010101010101010101010112 +:107E60000101010101010101010101010101010102 +:107E700001010101010101010101010101010101F2 +:107E800001010101010101010101010101010101E2 +:107E900001010101010101010101010101010101D2 +:107EA00001010101010101010101010101010101C2 +:107EB00001010101010101010201010101010101B1 +:107EC00001010101010101010000000000000000AA +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC0000000000000000000410000000000000070 +:107FD00000000000000000000000000000000000A1 +:107FE000000001000000000001000000000100008E +:107FF0000000000000000000000000000000000081 +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:10804000000000000001000000000000000000002F +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000001010000000000000000000000DE +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E000000001000000000001000000000100008D +:1080F0000000000000000000000000000000000080 +:10810000000000000000000000000000000000006F +:10811000000000000000010000000000000000005E +:10812000000000000000000001000000000000004E +:10813000000000000000000000000000000000003F +:10814000000000000001010000000000000000002D +:10815000000000000000000000000000010000001E +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900001010101010000000000000000000000DA +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000001000000000001000000000100008C +:1081F000000000000000000000000000000000007F +:10820000000000000000000000000000000000006E +:10821000000000010000010000000000000000005C +:10822000000000000000000001000000000000004D +:10823000000001000000000000000000000000003D +:10824000000000000001010100000001000000002A +:10825000000000000000000000000000010000001D +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900001010101010000000000000000000000D9 +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000100000000000000000000009D +:1082E000000001000000000001000000010100008A +:1082F000000000000000000000000000000000007E +:10830000000000000000000000000000000000006D +:10831000000000010000010000000000000000005B +:10832000000000000000000001000000000000004C +:10833000000001000000000000000000000000003C +:108340000000000000010101000000010000000128 +:10835000000000000000000000010000010000001B +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900001010101010000000000000000000001D7 +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000100000000000000000000009C +:1083E0000000010000000000010000000101010088 +:1083F000000000000000000000000000000000007D +:10840000000000000000000000000000000000006C +:108410000000000101000100000000000000000059 +:10842000000000010000000001000000000000004A +:10843000000001000000000000000000000000003B +:108440000000000000010101000001010000000126 +:108450000100000000000000000100000100000019 +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000010000000000000000000000EB +:1084900001010101010100000000000000000001D5 +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000010100000000000000000000009A +:1084E0000000010000000001010000000101010086 +:1084F000000000000000000000000000000000007C +:10850000000000000000000000000000000000006B +:108510000000000101000100000000000000000058 +:108520000000010100000000010000000000010047 +:10853000000001000000000000000000000000003A +:108540000100000000010101010001010000000123 +:108550000100000000000000000101000100000017 +:108560000100000000000000000000000000000109 +:1085700000000000000000000000000000000000FB +:1085800000000000010000000000000000000000EA +:1085900001010101010101000000000000000001D3 +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D0000100000101000000000000000000000098 +:1085E0000000010000000001010000000101010085 +:1085F0000000000000000100000000000000000179 +:108600000000000000000000000000000100000069 +:108610000000000101000100000000000000000057 +:108620000000010100000000010000000000010046 +:108630000100010000000000000000000000000038 +:108640000100000000010101010001010100000121 +:108650000100000000000000000101000100000115 +:108660000100000000000000000000000000000108 +:1086700000000000000000000000000000000000FA +:1086800000000001010000000000000000000000E8 +:1086900001010101010101000000000000000001D2 +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D0000100000101000000000000000000000097 +:1086E0000000010000000001010100000101010083 +:1086F0000000000000000100000000010000000177 +:108700000000000000000000000000000100000068 +:108710000000000101000100000000000000010055 +:108720000000010100000000010000000000010045 +:108730000100010000010000000000000000000036 +:108740000100000000010101010001010100000120 +:108750000100000000000000000101000100000114 +:108760000100000000000000000000000000000107 +:1087700000000000000000000000000000000000F9 +:1087800001010101010000000000000000000000E4 +:1087900001010101010101000000000000000001D1 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000100000000000000000000B8 +:1087C00000000000000000000000000000000000A9 +:1087D0000100000101000000000000000000000096 +:1087E0000000010000000001010100000101010181 +:1087F0000000000000000100000000010000000176 +:108800000000000000000000000100000100000066 +:108810000000000101010101000000000000010052 +:108820000000010101000000010100000000010042 +:108830000100010000010000000000000000000134 +:10884000010000000001010101010101010000011E +:108850000100000000000000000101000100000113 +:108860000100000100000000000000000000000105 +:1088700000000000000000000000000000000000F8 +:1088800001010101010000000000000000000000E3 +:1088900001010101010101010000000100000001CE +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000100000000000000000000B7 +:1088C00000000000000000000000000000000000A8 +:1088D0000100000101000000000000000000000095 +:1088E000000001010100000101010000010101017E +:1088F0000000000000000101000001010000000173 +:108900000000010000000000000100000100000064 +:10891000000100010101010101000000000101004E +:108920000000010101000000010100000000010140 +:108930000100010000010000000000000000000133 +:10894000010100000001010101010101010000011C +:108950000100000000000000000101000100000112 +:108960000101010100000000000000000000000102 +:1089700001000000000000000000000000000000F6 +:1089800001010101010000000000000000000000E2 +:1089900001010101010101010000000100000001CD +:1089A00000000000000100000000000000000000C6 +:1089B00000000000000100000000000000000000B6 +:1089C00000000000000000000000000000000000A7 +:1089D0000100000201000100000000000000000092 +:1089E000000001010100000101010000010101017D +:1089F0000000000000000101010001010000000171 +:108A00000000010101000000000100000100000061 +:108A1000000100010101010101000000000101004D +:108A2000000001010100000001010000000001013F +:108A30000100010000010100000000000000000131 +:108A4000010100010001010101010101010000011A +:108A50000101000000000000000101000100000110 +:108A60000101010101000000000000000000000100 +:108A700001000000000000000000000000000000F5 +:108A800001010101010000000000000000000000E1 +:108A900001010101010101010000010100000001CB +:108AA00000000000000101000000000000000001C3 +:108AB00000000000000101000000000000000000B4 +:108AC00000000000000000000000000000000000A6 +:108AD0000100000202000100000000000000000090 +:108AE000000001010100000101010100010101017B +:108AF0000000000000000101010001010000000170 +:108B0000010001010100000000010000010000005F +:108B1000000100010101010101000000000101004C +:108B2000000001010100000001010000000101013D +:108B3000010001000001010000000101000000012E +:108B40000101000100010101010101010100010118 +:108B5000010100000100000000010100010000010E +:108B600001010101010000000000000000000001FF +:108B700001010000000000000000000000000001F2 +:108B800001010101010000000000000000000001DF +:108B900001010101010101010100010100000101C8 +:108BA00000000000000101000000000000000001C2 +:108BB00000000000000101000000000000000000B3 +:108BC00000000000000000000000000000000000A5 +:108BD000020100020200020001000000000000008B +:108BE000000001010100000101010100010101017A +:108BF000010000000000010101000101000000016E +:108C0000010001010100000100010000010000005D +:108C1000000100010101010101000000000101004B +:108C2000000001010101000001010000000101013B +:108C3000010001000001010000000101000000012D +:108C40000101000101010101010101010100010116 +:108C5000010101000100000000010100010001010B +:108C600001010101010000000000000000000001FE +:108C700001010001010000000000000000000001EF +:108C800001010101010100000000000000000001DD +:108C900001010101010101010101010100000101C6 +:108CA00000000000000101000000000000000001C1 +:108CB00000000000000101000000000000000001B1 +:108CC00000000000000000000000000000000000A4 +:108CD0000201000202000201020100000100000086 +:108CE0000000020101010001010101000101010177 +:108CF000010000000001010101010101000000016B +:108D0000010001010100000100010000010000005C +:108D10000101010101010101010000000001010048 +:108D2000000001010101000001010000000101013A +:108D3000010001000001010000000101000000012C +:108D40000101010101010101010101010100010114 +:108D5000010101000100000000010100010001010A +:108D600001010101010000000000000000000101FC +:108D700001010101010000000000000000000001ED +:108D800001010101010100000000000000000001DC +:108D900001010101010101010101010100000101C5 +:108DA00000000000000101000000000000000001C0 +:108DB00000000000000101010000000100000001AE +:108DC00000000000000000000000000000000000A3 +:108DD0000201000202000202020200000100000083 +:108DE0000100020101010001010101000101010175 +:108DF000010000000001010101010101000000016A +:108E0000010001010100000100010000010000005B +:108E10000101010101010101010101000001010045 +:108E20000000010101010000010100010101010137 +:108E3000010101000001010000000101000000012A +:108E40000101010101010101010101010100010113 +:108E50000101010001000000000101000100010109 +:108E600001010101010000000000000000000101FB +:108E700001010101010000000000000000000001EC +:108E800001010101010100000000000000000001DB +:108E900001010101010101010101010101000101C3 +:108EA00000000000000101000000000000000001BF +:108EB00000000000000101010000000100000001AD +:108EC00000000000000000000000000000000000A2 +:108ED0000202000202000202020200000200000080 +:108EE0000100020101010001020101000101010173 +:108EF0000100000101010101010101010000000167 +:108F00000101010101000001010100000100000058 +:108F10000101010101010101010101000001010044 +:108F20000000010101010100010100010101010135 +:108F30000101010000010101000001010000000128 +:108F40000101010101010101010101010100010112 +:108F50000101010101000000000101000100010107 +:108F600001010101010000000000000000000101FA +:108F700001010101010000000000000000000001EB +:108F800001010101010100000000000000000001DA +:108F900001010101010101010101010101010101C1 +:108FA00000000000000101000000010100000001BC +:108FB00000000000000101010000010100000001AB +:108FC000000000010100000000000000000000009F +:108FD000020200020200020202020000020000007F +:108FE0000100020101010001020101000101010172 +:108FF0000100010101010101010101010001000164 +:109000000101010101000001010100000100000057 +:109010000101010101010101010101000101010042 +:109020000000010101010100010101010101010133 +:109030000101010000010101000001010000010126 +:109040000101010101010101010101010100010111 +:109050000101010101000000000101000100010106 +:1090600001010101010100000000000000000101F8 +:1090700001010101010000000000000000000001EA +:1090800001010101010100000000000000000001D9 +:1090900001010101010101010101010101010101C0 +:1090A00000000000000101000100010100000101B9 +:1090B00000000000000101010100010100000001A9 +:1090C000000000010100000000000000000000009E +:1090D000020200020200020202020000020000007E +:1090E0000100020101010001020101010101010170 +:1090F0000100010101010101010101010001000163 +:109100000101010101000001010100000100000056 +:109110000101010101010101010101000101010041 +:109120000001010101010100010101010101010131 +:109130000101010001010101000101010000010123 +:109140000101010101010101010101010100010110 +:109150000101010101000000000101000100010105 +:1091600001010101010100000000000000000101F7 +:1091700001010101010000000000000000000001E9 +:1091800001010101010100000000000000000001D8 +:1091900001010101010101010101010101010101BF +:1091A00000000000000101000101010101000101B6 +:1091B00000000000000101010101010101000001A6 +:1091C000000000010100000000000000000000009D +:1091D000020201020200020202020000020000007C +:1091E000010002010101000202010101010101016E +:1091F0000100010101010101010101010001000162 +:109200000101010101000001010100000100000055 +:10921000010101020101020101010100010101003E +:109220000001010101010100010101010101010130 +:109230000101010001010101010101010000010121 +:10924000010101010101010101010101010001010F +:109250000101010101000000000101000100010104 +:1092600001010101010100000000000000000101F6 +:1092700001010101010000000000000000000001E8 +:1092800001010101010100000000000000000001D7 +:1092900001010101010101010101010101010101BE +:1092A00000000000000101000101010101000101B5 +:1092B00000000000000101010101010101000101A4 +:1092C000000000010100000000000000000000009C +:1092D0000202020202020202020202000200000076 +:1092E000010002010101000202010101010201016C +:1092F0000100010101010101010101010001000161 +:109300000101010101000001010100000100000054 +:10931000010101020101020101010100010101003D +:10932000000101010101010001010101010101012F +:10933000010102010101010101010101000001011E +:10934000010101010101010101010101010101010D +:109350000101010101000000000101010100010102 +:1093600001010101010101000000000000010101F3 +:1093700001010101010000000000000000000001E7 +:1093800001010101010101000000000000000001D5 +:1093900001010101010101010101010101010101BD +:1093A00000000000000101000101010101000101B4 +:1093B00000000000000101010101010101000101A3 +:1093C000000000010100000000000000000000009B +:1093D0000202020202020202020202000201000074 +:1093E0000101020201010102020201010202010166 +:1093F000010101010101020101010101000100015E +:109400000201020101000001010100000100000051 +:10941000010201020201020101010100010101003A +:10942000000102010101010101010101010101012C +:10943000020102010101010101010101000001011C +:10944000020101010101010101010101010101010B +:109450000201010101000000000101010100010100 +:1094600001010101010101000000010101010101EF +:1094700001010101010000000000000100000001E5 +:1094800001010101010101010000000000000001D3 +:1094900002010101010101010101010101010101BB +:1094A00000000000000101000101010101010101B2 +:1094B00000000000000101010101010101000101A2 +:1094C0000001010101000000000000000000000098 +:1094D0000202020202020202020202000202000072 +:1094E0000101020202010102020201010202010164 +:1094F000020101010101020101010101010100015B +:109500000201020101000001010100000100000050 +:109510000102010202010201010101000101010039 +:109520000101020201010101020101010101010128 +:10953000020102010101010101010101000001011B +:109540000201010101020101010101010101010109 +:1095500002010101010100000001010101000101FE +:1095600002010101010101000000010101010101ED +:1095700001010101010000000000000100000101E3 +:1095800001010101010101010000000000000001D2 +:1095900002020101010101010101010101010101B9 +:1095A00000000000000101000101010101010101B1 +:1095B00000000000000101010101010101000101A1 +:1095C0000001010101010000000000000000000096 +:1095D0000202020202020202020202000202000071 +:1095E0000201020202010102020201010202010162 +:1095F0000201010101010202010101010101000159 +:10960000020102020100000101020001010000004C +:109610000202010202020202010101010101010034 +:109620000101020201010101020101010101010127 +:10963000020102010101010101010101000001011A +:109640000201010101020201010101010101010107 +:1096500002010101010100000001010101010101FC +:1096600002010101010101010000010101010101EB +:1096700001010101010100000000000100000101E1 +:1096800002010101010101010000000000000001D0 +:1096900002020201010101010101010101010101B7 +:1096A00000000000000101000101010101010101B0 +:1096B000000000000001010101010101010101019F +:1096C0000001010101010000000000000000000095 +:1096D0000202020202020202020202000202000070 +:1096E000020102020202010202020201020202015E +:1096F0000201010101010202020101010101000157 +:109700000202020202000001010200010101000147 +:109710000202020202020202020101010101010031 +:109720000101020201010101020101010101010126 +:109730000201020101010101010101010000010119 +:109740000202010101020202010101010101010104 +:1097500002010101010100000001010101010101FB +:1097600002010101010101010000010101010101EA +:1097700002010101010101000000000100000101DE +:1097800002020101010101010100000000000001CD +:1097900002020202010101010101010101010101B5 +:1097A00000000000000101000101010101010101AF +:1097B000000000000001010101010101010101019E +:1097C0000001010101010000000000000000000094 +:1097D000020202020202020202020200020200006F +:1097E000020102020202010202020201020202015D +:1097F0000201020101020202020101010101000154 +:109800000202020202010002010200010201000143 +:109810000202020202020202020101010101010030 +:109820000101020202010101020101010101010124 +:109830000201020101020101010101010000010117 +:109840000202010101020202010101010101010103 +:1098500002020101010101000001010101010101F8 +:1098600002020101010101010001010101010101E7 +:1098700002010101010101000000000100000101DD +:1098800002020201010101010101010101000001C7 +:1098900002020202020101010101010101010101B3 +:1098A00000000000000101000101010101010101AE +:1098B000000000000001010101010101010101019D +:1098C0000001010101010100000000000000000092 +:1098D000020202020202020202020202020200006C +:1098E000020202020202010202020201020202015B +:1098F000020102020102020202020202010100014F +:109900000202020202010002010200010201000142 +:10991000020202020202020202010101010101012E +:109920000101020202010101020201010101010122 +:109930000202020101020101010101010000010115 +:109940000202010101020202020101010101010101 +:1099500002020101010101000002010101010101F6 +:1099600002020201010101010101010101010101E4 +:1099700002020101010101000000000100010101DA +:1099800002020202020101010101010101010001C3 +:1099900002020202020101010101010101010101B2 +:1099A00000000000000101000101010101010101AD +:1099B000000000000001010101010101010101019C +:1099C0000001010101010100000000000000000091 +:1099D000020202020202020202020202020200006B +:1099E0000202020202020202020202010202020159 +:1099F000020202020202020202020202010100014C +:109A0000020202020201000202020101020100013F +:109A1000020202020202020202020101010201012B +:109A2000010202020202010102020101010101011F +:109A30000202020101020201010101010000010113 +:109A400002020202010202020201020201010101FC +:109A500002020201010101000002010102010101F3 +:109A600002020202010101010101010101010101E2 +:109A700002020101010101000000010101010101D7 +:109A800002020202020101010101010101010001C2 +:109A900002020202020201010101010101010101B0 +:109AA00000000000000101000101010101010101AC +:109AB000000000000001010101010101010101019B +:109AC0000001010101010100000000000000000090 +:109AD000020202020202020202020202020200006A +:109AE0000202020202020202020202010202020158 +:109AF000020202020202020202020202010100014B +:109B0000020202020201010202020101020100013D +:109B10000202020202020202020202010102020128 +:109B2000010202020202010102020101010101011E +:109B30000202020101020201010101010100010111 +:109B400002020202010202020202020201010101FA +:109B500002020201010101000002020102010101F1 +:109B600002020202010101010101010101010101E1 +:109B700002020201010101000000010101010101D5 +:109B800002020202020101010101010101010001C1 +:109B900002020202020202010101010101010101AE +:109BA00000000000000101000101010101010101AB +:109BB000000000000001010101010101010101019A +:109BC000000101010101010000000000000000008F +:109BD0000202020202020202020202020202000069 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020101010248 +:109C0000020202020201010202020101020100013C +:109C10000202020202020202020202010102020127 +:109C2000020202020202020102020101010102011A +:109C30000202020101020201010101010100010110 +:109C400002020202020202020202020202010101F7 +:109C500002020201020101000002020102010101EF +:109C600002020202020101010101010101010101DF +:109C700002020202010101010000010101010101D2 +:109C800002020202020101010101010101010001C0 +:109C900002020202020202010101010101010101AD +:109CA00000000000000101000101010101010101AA +:109CB0000000000000020101010101010101010198 +:109CC000000101010101010000000000000000018D +:109CD0000202020202020202020202020202000068 +:109CE0000202020202020202020202020202020254 +:109CF0000202020202020202020202020101010247 +:109D0000020202020201010202020101020100013B +:109D10000202020202020202020202010202020125 +:109D20000202020202020201020201010101020119 +:109D3000020202010102020201010201010001010D +:109D400002020202020202020202020202010101F6 +:109D500002020202020101010002020102010101EC +:109D600002020202020101010101010101010101DE +:109D700002020202020101010100010101010101CF +:109D800002020202020201010101010101010001BE +:109D900002020202020202020101010101010101AB +:109DA00000000000000201000101010101010101A8 +:109DB0000000000000020101010101010101010197 +:109DC000000101010101010100000000000000018B +:109DD0000202020202020202020202020202000067 +:109DE0000202020202020202020202020202020253 +:109DF0000202020202020202020202020102010245 +:109E00000202020202020102020201010201000139 +:109E10000202020202020202020202010202020124 +:109E20000202020202020201020201010102020117 +:109E30000202020202020202010102020100010109 +:109E400002020202020202020202020202010102F4 +:109E500002020202020101010102020102010101EA +:109E600002020202020101010101010101010101DD +:109E700002020202020101010101010101010101CD +:109E800002020202020201010101010101010001BD +:109E900002020202020202020101010101010101AA +:109EA00000000000000202000101010101010101A6 +:109EB0000000000000020201010101010101010195 +:109EC0000001010101010101010000000000000189 +:109ED0000202020202020202020202020202000066 +:109EE0000202020202020202020202020202020252 +:109EF0000202020202020202020202020102010244 +:109F00000202020202020102020201010201010137 +:109F10000202020202020202020202010202020123 +:109F20000202020202020202020202020202020112 +:109F30000202020202020202020202020100010106 +:109F400002020202020202020202020202010102F3 +:109F500002020202020101010102020102010101E9 +:109F600002020202020201010101010101010101DB +:109F700002020202020101010101010101010101CC +:109F800002020202020201010101010101010001BC +:109F900002020202020202020201010101010101A8 +:109FA00000000000000202000101010101010101A5 +:109FB0000000000000020201010101010101010194 +:109FC0000002010201010101010001010000000184 +:109FD0000202020202020202020202020102000066 +:109FE0000202020202020202020202020202020251 +:109FF0000202020202020202020202020202010242 +:10A000000202020202020202020201010201010135 +:10A010000202020202020202020202010202020122 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020100010204 +:10A0400002020202020202020202020202010102F2 +:10A0500002020202020101010102020102010102E7 +:10A0600002020202020201010101010101010102D9 +:10A0700002020202020101010101010101010101CB +:10A0800002020202020201010101010101010001BB +:10A0900002020202020202020202020201010102A3 +:10A0A00000000000000202000101010101010101A4 +:10A0B0000000000000020202010101010101010192 +:10A0C0000002020202010101010001010000000181 +:10A0D0000202020202020202010102020102000067 +:10A0E0000202020202020202020202020202020250 +:10A0F0000202020202020202020202020202010241 +:10A100000202020202020202020202020201010132 +:10A110000202020202020202020202020202020120 +:10A12000020202020202020202020202020202020F +:10A130000202020202020202020202020100010203 +:10A1400002020202020202020202020202010202F0 +:10A1500002020202020201010102020102010102E5 +:10A1600002020202020202010101010101010102D7 +:10A1700002020202020101010101010101010101CA +:10A1800002020202020202010101010101010001B9 +:10A1900002020202020202020202020201010102A2 +:10A1A00000000000000202000101010101010101A3 +:10A1B0000000000000020202010101010101010191 +:10A1C000000202020201010101010101000000017F +:10A1D0000202020202020101010101020101020068 +:10A1E000020202020202020202020202020202024F +:10A1F0000202020202020202020202020202010240 +:10A200000202020202020202020202020202010130 +:10A21000020202020202020202020202020202011F +:10A22000020202020202020202020202020202020E +:10A230000202020202020202020202020101010201 +:10A2400002020202020202020202020202010202EF +:10A2500002020202020201010102020102010202E3 +:10A2600002020202020202010101010101010102D6 +:10A2700002020202020201010101010101010101C8 +:10A2800002020202020202020101010101010001B7 +:10A2900002020202020202020202020201010102A1 +:10A2A00000000000000202000201010101010101A1 +:10A2B000010000000002020202010101010101018E +:10A2C000000202020201010101010101000001017D +:10A2D0000202020202020101010101020101020067 +:10A2E000020202020202020202020202020202024E +:10A2F000020202020202020202020202020201023F +:10A30000020202020202020202020202020201012F +:10A31000020202020202020202020202020202011E +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020201010202FF +:10A3400002020202020202020202020202010202EE +:10A3500002020202020202010102020102010202E1 +:10A3600002020202020202020101010101010202D3 +:10A3700002020202020202010101010101010102C5 +:10A3800002020202020202020101010101010102B4 +:10A39000020202020202020202020202020102029E +:10A3A000000000010102020002020201010101019C +:10A3B000010000000002020202020202010101018A +:10A3C000000202020202010101010101010001017A +:10A3D0000202020102020101010101010101020068 +:10A3E000020202020202020202020202020202024D +:10A3F000020202020202020202020202020201023E +:10A40000020202020202020202020202020201012E +:10A41000020202020202020202020202020202011D +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020201010202FE +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202010102020202010202DF +:10A4600002020202020202020101020101010202D1 +:10A4700002020202020202010101010101010102C4 +:10A4800002020202020202020201010101010102B2 +:10A49000020202020202020202020202020202029C +:10A4A0000101010101020200020202020101010296 +:10A4B0000101010000020202020202020101010187 +:10A4C0000002020202020101010101010100010179 +:10A4D0000202020101010101010101010101020069 +:10A4E000020202020202020202020202020202024C +:10A4F000020202020202020202020202020201023D +:10A50000020202020202020202020202020201012D +:10A51000020202020202020202020202020202011C +:10A52000020202020202020202020202020202020B +:10A5300002020202020202020202020201010202FD +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202010102020202010202DE +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202010101010201010102C2 +:10A5800002020202020202020202010101010102B0 +:10A59000020202020202020202020202020202029B +:10A5A0000101010101020200020202020201010294 +:10A5B0000101010101020202020202020201010282 +:10A5C0000002020202020201010101010100010177 +:10A5D0000202020101010101010101010101020068 +:10A5E000020202020202020202020202020202024B +:10A5F000020202020202020202020202020201023C +:10A60000020202020202020202020202020201012C +:10A61000020202020202020202020202020202011B +:10A62000020202020202020202020202020202020A +:10A6300002020202020202020202020201010202FC +:10A6400002020202020202020202020202020202EA +:10A6500002020202020202020102020202020202DB +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020101010201010102C0 +:10A6800002020202020202020202020101010102AE +:10A69000020202020202020202020202020202029A +:10A6A0000101010101020200020202020201020292 +:10A6B0000201010101020202020202020201010280 +:10A6C0000102020202020201010101010101010174 +:10A6D0000202020101010101010101010101010068 +:10A6E000020202020202020202020202020202024A +:10A6F000020202020202020202020202020201023B +:10A70000020202020202020202020202020201022A +:10A71000020202020202020202020202020202011A +:10A720000202020202020202020202020202020209 +:10A7300002020202020202020202020202010202FA +:10A7400002020202020202020202020202020202E9 +:10A7500002020202020202020202020202020202D9 +:10A7600002020202020202020202020202020202C9 +:10A7700002020202020202020201020201010202BC +:10A7800002020202020202020202020202010102AB +:10A790000202020202020202020202020202020299 +:10A7A000020101010102020002020202020202028F +:10A7B000020101010102020202020202020102027E +:10A7C0000102020202020201010101010101010173 +:10A7D0000201010101010101010101010101010069 +:10A7E0000202020202020202020202020202020249 +:10A7F000020202020202020202020202020201023A +:10A800000202020202020202020202020202010229 +:10A810000202020202020202020202020202020218 +:10A820000202020202020202020202020202020208 +:10A8300002020202020202020202020202010202F9 +:10A8400002020202020202020202020202020202E8 +:10A8500002020202020202020202020202020202D8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800002020202020202020202020202020102A9 +:10A890000202020202020202020202020202020298 +:10A8A000020201010102020002020202020202028D +:10A8B000020201010102020202020202020202027B +:10A8C0000202020202020202010101010101010170 +:10A8D0000101010101010101010101010101010069 +:10A8E0000202020202020202020202020202020248 +:10A8F0000202020202020202020202020202020238 +:10A900000202020202020202020202020202010228 +:10A910000202020202020202020202020202020217 +:10A920000202020202020202020202020202020207 +:10A9300002020202020202020202020202010202F8 +:10A9400002020202020202020202020202020202E7 +:10A9500002020202020202020202020202020202D7 +:10A9600002020202020202020202020202020202C7 +:10A9700002020202020202020202020202020202B7 +:10A9800002020202020202020202020202020102A8 +:10A990000202020202020202020202020202020297 +:10A9A000020202010102020002020202020202028B +:10A9B0000202020101020202020202020202020279 +:10A9C000020202020202020202010101010101016E +:10A9D0000101010101010101010101010101010167 +:10A9E0000202020202020202010202020202020248 +:10A9F0000202020202020202020202020202020237 +:10AA00000202020202020202020202020202020226 +:10AA10000202020202020202020202020202020216 +:10AA20000202020202020202020202020202020206 +:10AA300002020202020202020202020202010202F7 +:10AA400002020202020202020202020202020202E6 +:10AA500002020202020202020202020202020202D6 +:10AA600002020202020202020202020202020202C6 +:10AA700002020202020202020202020202020202B6 +:10AA800002020202020202020202020202020102A7 +:10AA90000202020202020202020202020202020296 +:10AAA0000202020201020200020202020202020289 +:10AAB0000202020101020202020202020202020278 +:10AAC000020202020202020202010101010101016D +:10AAD0000101010101010101010101010101010166 +:10AAE000020202020202020101010102010102024C +:10AAF0000202020202020202020202020202020236 +:10AB00000202020202020202020202020202020225 +:10AB10000202020202020202020202020202020215 +:10AB20000202020202020202020202020202020205 +:10AB300002020202020202020202020202010202F6 +:10AB400002020202020202020202020202020202E5 +:10AB500002020202020202020202020202020202D5 +:10AB600002020202020202020202020202020202C5 +:10AB700002020202020202020202020202020202B5 +:10AB800002020202020202020202020202020102A6 +:10AB90000202020202020202020202020202020295 +:10ABA0000202020202020201020202020202020286 +:10ABB0000202020201020202020202020202020276 +:10ABC000020202020202020202020201010101016A +:10ABD0000101010101010101010101010101010165 +:10ABE000020201020202010101010101010101024F +:10ABF0000202020202020202020202020202020235 +:10AC00000202020202020202020202020202020224 +:10AC10000202020202020202020202020202020214 +:10AC20000202020202020202020202020202020204 +:10AC300002020202020202020202020202020202F4 +:10AC400002020202020202020202020202020202E4 +:10AC500002020202020202020202020202020202D4 +:10AC600002020202020202020202020202020202C4 +:10AC700002020202020202020202020202020202B4 +:10AC800002020202020202020202020202020102A5 +:10AC90000202020202020202020202020202020294 +:10ACA0000202020202020201020202020202020285 +:10ACB0000202020202020202020202020202020274 +:10ACC0000202020202020202020202020101010168 +:10ACD0000101010101010101010101010101010164 +:10ACE0000202010101010101010101010101010251 +:10ACF0000202020202020202020202020202020234 +:10AD00000202020202020202020202020202020223 +:10AD10000202020202020202020202020202020213 +:10AD20000202020202020202020202020202020203 +:10AD300002020202020202020202020202020202F3 +:10AD400002020202020202020202020202020202E3 +:10AD500002020202020202020202020202020202D3 +:10AD600002020202020202020202020202020202C3 +:10AD700002020202020202020202020202020202B3 +:10AD800002020202020202020202020202020102A4 +:10AD90000202020202020202020202020202020293 +:10ADA0000202020202020201020202020202020284 +:10ADB0000202020202020202020202020202020273 +:10ADC0000202020202020202020202020101010266 +:10ADD0000101010101010101010101010101010163 +:10ADE0000202010101010101010101010101010151 +:10ADF0000202020202020101010102020202020237 +:10AE00000202020202020202020202020202020222 +:10AE10000202020202020202020202020202020212 +:10AE20000202020202020202020202020202020202 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020102A3 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020201020202020202020283 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020201010264 +:10AED0000101010101010101010101010101010162 +:10AEE0000201010101010101010101010101010151 +:10AEF000020202020201010101010101010102023B +:10AF00000202020202020202020102020202020222 +:10AF10000202020202020202020202020202020211 +:10AF20000202020202020202020202020202020201 +:10AF300002020202020202020202020202020202F1 +:10AF400002020202020202020202020202020202E1 +:10AF500002020202020202020202020202020202D1 +:10AF600002020202020202020202020202020202C1 +:10AF700002020202020202020202020202020202B1 +:10AF800002020202020202020202020202020202A1 +:10AF90000202020202020202020202020202020291 +:10AFA0000202020202020201020202020202020282 +:10AFB0000202020202020202020202020202020271 +:10AFC0000202020202020202020202020201020262 +:10AFD0000101010101010101010101010101010161 +:10AFE0000101010101010101010101010101010151 +:10AFF000020201010101010101010101010102013E +:10B000000202020202020201010101020102020225 +:10B010000202020202020202020202020202020210 +:10B020000202020202020202020202020202020200 +:10B0300002020202020202020202020202020202F0 +:10B0400002020202020202020202020202020202E0 +:10B0500002020202020202020202020202020202D0 +:10B0600002020202020202020202020202020202C0 +:10B0700002020202020202020202020202020202B0 +:10B0800002020202020202020202020202020202A0 +:10B090000202020202020202020202020202020290 +:10B0A0000202020202020202020202020202020280 +:10B0B0000202020202020202020202020202020270 +:10B0C0000202020202020202020202020202020260 +:10B0D0000101010101010101010101010101010160 +:10B0E0000101010101010101010101010101010150 +:10B0F000010101010101010101010101010102013F +:10B10000020201010101010101010101010102022B +:10B110000202020202020101010101020101020216 +:10B1200002020202020202020202020202020202FF +:10B1300002020202020202020202020202020202EF +:10B1400002020202020202020202020202020202DF +:10B1500002020202020202020202020202020202CF +:10B1600002020202020202020202020202020202BF +:10B1700002020202020202020202020202020202AF +:10B18000020202020202020202020202020202029F +:10B19000020202020202020202020202020202028F +:10B1A000020202020202020202020202020202027F +:10B1B000020202020202020202020202020202026F +:10B1C000020202020202020202020202020202025F +:10B1D000010101010101010101010101010101015F +:10B1E000010101010101010101010101010101014F +:10B1F000010101010101010101010101010102013E +:10B20000010101010101010101010101010102022C +:10B21000020202010101010101010101010101021A +:10B2200002020202020202020202020202020202FE +:10B2300002020202020202020202020202020202EE +:10B2400002020202020202020202020202020202DE +:10B2500002020202020202020202020202020202CE +:10B2600002020202020202020202020202020202BE +:10B2700002020202020202020202020202020202AE +:10B28000020202020202020202020202020202029E +:10B29000020202020202020202020202020202028E +:10B2A000020202020202020202020202020202027E +:10B2B000020202020202020202020202020202026E +:10B2C000020202020202020202020202020202025E +:10B2D000010101010101010101010101010101015E +:10B2E000010101010101010101010101010101014E +:10B2F000010101010101010101010101010101013E +:10B30000010101010101010101010101010102022B +:10B31000020101010101010101010101010101021B +:10B3200002020202020202020101020202020202FF +:10B3300002020202020202020202020202020202ED +:10B3400002020202020202020202020202020202DD +:10B3500002020202020202020202020202020202CD +:10B3600002020202020202020202020202020202BD +:10B3700002020202020202020202020202020202AD +:10B38000020202020202020202020202020202029D +:10B39000020202020202020202020202020202028D +:10B3A000020202020202020202020202020202027D +:10B3B000020202020202020202020202020202026D +:10B3C000020202020202020202020202020202025D +:10B3D000010101010101010101010101010101015D +:10B3E000010101010101010101010101010101014D +:10B3F000010101010101010101010101010101013D +:10B40000010101010101010101010101010101012C +:10B41000010101010101010101010101010101021B +:10B420000202010101010101010101010101010209 +:10B4300002020202020202020202020202020202EC +:10B4400002020202020202020202020202020202DC +:10B4500002020202020202020202020202020202CC +:10B4600002020202020202020202020202020202BC +:10B4700002020202020202020202020202020202AC +:10B48000020202020202020202020202020202029C +:10B49000020202020202020202020202020202028C +:10B4A000020202020202020202020202020202027C +:10B4B000020202020202020202020202020202026C +:10B4C000020202020202020202020202020202025C +:10B4D000010101010101010101010101010101015C +:10B4E000010101010101010101010101010101014C +:10B4F000010101010101010101010101010101013C +:10B50000010101010101010101010101010101012B +:10B51000010101010101010101010101010101011B +:10B52000020101010101010101010101010101010A +:10B5300002020102020101010101010102020202F3 +:10B5400002020202020202020202020202020202DB +:10B5500002020202020202020202020202020202CB +:10B5600002020202020202020202020202020202BB +:10B5700002020202020202020202020202020202AB +:10B58000020202020202020202020202020202029B +:10B59000020202020202020202020202020202028B +:10B5A000020202020202020202020202020202027B +:10B5B000020202020202020202020202020202026B +:10B5C000020202020202020202020202020202025B +:10B5D000010101010101010101010101010101015B +:10B5E000010101010101010101010101010101014B +:10B5F000010101010101010101010101010101013B +:10B60000010101010101010101010101010101012A +:10B61000010101010101010101010101010101011A +:10B62000010101010101010101010101010101010A +:10B6300001010101010101010101010101020101F9 +:10B6400002020202020101010101010101020202E2 +:10B6500002020202020202020202020202020202CA +:10B6600002020202020202020202020202020202BA +:10B6700002020202020202020202020202020202AA +:10B68000020202020202020202020202020202029A +:10B69000020202020202020202020202020202028A +:10B6A000020202020202020202020202020202027A +:10B6B000020202020202020202020202020202026A +:10B6C000020202020202020202020202020202025A +:10B6D000010101010101010101010101010101015A +:10B6E000010101010101010101010101010101014A +:10B6F000010101010101010101010101010101013A +:10B700000101010101010101010101010101010129 +:10B710000101010101010101010101010101010119 +:10B720000101010101010101010101010101010109 +:10B7300001010101010101010101010101010101F9 +:10B7400001010101010101010101010101010101E9 +:10B7500002020202020202020201010201020202CC +:10B7600002020202020202020202020202020202B9 +:10B7700002020202020202020202020202020202A9 +:10B780000202020202020202020202020202020299 +:10B790000202020202020202020202020202020289 +:10B7A0000202020202020202020202020202020279 +:10B7B0000202020202020202020202020202020269 +:10B7C0000202020202020202020202020202020259 +:10B7D0000101010101010101010101010101010159 +:10B7E0000101010101010101010101010101010149 +:10B7F0000101010101010101010101010101010139 +:10B800000101010101010101010101010101010128 +:10B810000101010101010101010101010101010118 +:10B820000101010101010101010101010101010108 +:10B8300001010101010101010101010101010101F8 +:10B8400001010101010101010101010101010101E8 +:10B8500001010101010101010101010101010101D8 +:10B8600002020202020202020202020202020202B8 +:10B8700002020202020202020202020202020202A8 +:10B880000202020202020202020202020202020298 +:10B890000202020202020202020202020202020288 +:10B8A0000202020202020202020202020202020278 +:10B8B0000202020202020202020202020202020268 +:10B8C0000202020202020202020202020202020258 +:10B8D0000101010101010101010101010101010158 +:10B8E0000101010101010101010101010101010148 +:10B8F0000101010101010101010101010101010138 +:10B900000101010101010101010101010101010127 +:10B910000101010101010101010101010101010117 +:10B920000101010101010101010101010101010107 +:10B9300001010101010101010101010101010101F7 +:10B9400001010101010101010101010101010101E7 +:10B9500001010101010101010101010101010101D7 +:10B9600001010101010101010101010101010101C7 +:10B9700002020202020202020202020202020202A7 +:10B980000202020202020202020202020202020297 +:10B990000202020202020202020202020202020287 +:10B9A0000202020202020202020202020202020277 +:10B9B0000202020202020202020202020202020267 +:10B9C0000202020202020202020202020202020257 +:10B9D0000101010101010101010101010101010157 +:10B9E0000101010101010101010101010101010147 +:10B9F0000101010101010101010101010101010137 +:10BA00000101010101010101010101010101010126 +:10BA10000101010101010101010101010101010116 +:10BA20000101010101010101010101010101010106 +:10BA300001010101010101010101010101010101F6 +:10BA400001010101010101010101010101010101E6 +:10BA500001010101010101010101010101010101D6 +:10BA600001010101010101010101010101010101C6 +:10BA700001010101010101010101010101010101B6 +:10BA80000202020202020202020202020202020296 +:10BA90000202020202020202020202020202020286 +:10BAA0000202020202020202020202020202020276 +:10BAB0000202020202020202020202020202020266 +:10BAC0000202020202020202020202020202020256 +:10BAD0000101010101010101010101010101010156 +:10BAE0000101010101010101010101010101010146 +:10BAF0000101010101010101010101010101010136 +:10BB00000101010101010101010101010101010125 +:10BB10000101010101010101010101010101010115 +:10BB20000101010101010101010101010101010105 +:10BB300001010101010101010101010101010101F5 +:10BB400001010101010101010101010101010101E5 +:10BB500001010101010101010101010101010101D5 +:10BB600001010101010101010101010101010101C5 +:10BB700001010101010101010101010101010101B5 +:10BB800001010101010101010101010101010201A4 +:10BB90000202020202020202020202020202020285 +:10BBA0000202020202020202020202020202020275 +:10BBB0000202020202020202020202020202020265 +:10BBC0000202020202020202020202020202020255 +:10BBD0000101010101010101010101010101010155 +:10BBE0000101010101010101010101010101010145 +:10BBF0000101010101010101010101010101010135 +:10BC00000101010101010101010101010101010124 +:10BC10000101010101010101010101010101010114 +:10BC20000101010101010101010101010101010104 +:10BC300001010101010101010101010101010101F4 +:10BC400001010101010101010101010101010101E4 +:10BC500001010101010101010101010101010101D4 +:10BC600001010101010101010101010101010101C4 +:10BC700001010101010101010101010101010101B4 +:10BC800001010101010101010101010101010101A4 +:10BC90000101010101010101010101010101010194 +:10BCA0000202020202020202020202020202020274 +:10BCB0000202020202020202020202020202020264 +:10BCC0000202020202020202020202020202020254 +:10BCD0000101010101010101010101010101010154 +:10BCE0000101010101010101010101010101010144 +:10BCF0000101010101010101010101010101010134 +:10BD00000101010101010101010101010101010123 +:10BD10000101010101010101010101010101010113 +:10BD20000101010101010101010101010101010103 +:10BD300001010101010101010101010101010101F3 +:10BD400001010101010101010101010101010101E3 +:10BD500001010101010101010101010101010101D3 +:10BD600001010101010101010101010101010101C3 +:10BD700001010101010101010101010101010101B3 +:10BD800001010101010101010101010101010101A3 +:10BD90000101010101010101010101010101010193 +:10BDA000020202020201010201010101010101017D +:10BDB0000202020202020202020202020202020263 +:10BDC0000202020202020202020202020202020253 +:10BDD0000101010101010101010101010101010153 +:10BDE0000101010101010101010101010101010143 +:10BDF0000101010101010101010101010101010133 +:10BE00000101010101010101010101010101010122 +:10BE10000101010101010101010101010101010112 +:10BE20000101010101010101010101010101010102 +:10BE300001010101010101010101010101010101F2 +:10BE400001010101010101010101010101010101E2 +:10BE500001010101010101010101010101010101D2 +:10BE600001010101010101010101010101010101C2 +:10BE700001010101010101010101010101010101B2 +:10BE800001010101010101010101010101010101A2 +:10BE90000101010101010101010101010101010192 +:10BEA0000101010101010101010101010101010182 +:10BEB000020202020201010101010101010101016D +:10BEC0000202020202020202020202020202020252 +:10BED0000101010101010101010101010101010152 +:10BEE0000101010101010101010101010101010142 +:10BEF0000101010101010101010101010101010132 +:10BF00000101010101010101010101010101010121 +:10BF10000101010101010101010101010101010111 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010101010101F1 +:10BF400001010101010101010101010101010101E1 +:10BF500001010101010101010101010101010101D1 +:10BF600001010101010101010101010101010101C1 +:10BF700001010101010101010101010101010101B1 +:10BF800001010101010101010101010101010101A1 +:10BF90000101010101010101010101010101010191 +:10BFA0000101010101010101010101010101010181 +:10BFB0000101010101010101010101010101010171 +:10BFC0000201010101010101010101010101010160 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D000430000000000000000000000000000001D +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000100000E +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000100010100010000000000000000004B +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000100000D +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D0000000000000000000010101010101010156 +:10C2E0000101010101010100000000000000000047 +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000100000000000000002C +:10C31000000000000000000000000000000000001D +:10C32000000000000000000000000000010100000B +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D0000000000000000000010101010101010155 +:10C3E0000101010101010100000000000000000046 +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000100000000000000002B +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000010100000A +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000001000000008B +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D0000000000000000000010101010101010154 +:10C4E0000101010101010100000000000000000045 +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000100000000000000002A +:10C51000000000000000000000000000000000001B +:10C520000000000000000000000000000101000009 +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C590000000000000000000000101010101010194 +:10C5A0000000000000000001000000010000000089 +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D0000000000000000000010101010101010153 +:10C5E0000101010101010100000000000000000044 +:10C5F000000000000000000000000000000000003B +:10C600000000000000000001000000000000000029 +:10C61000000000000000000000000000000000001A +:10C620000000000000000000000000000101000008 +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C690000000000000000000000101010101010193 +:10C6A0000000000000000001000000010101000086 +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D0000000000000000000010101010101010152 +:10C6E0000101010101010100000000000000000043 +:10C6F000000000000000000000000000000000003A +:10C700000000000000000001000000000000000028 +:10C710000000000000000000000001010001000016 +:10C720000000000000000000000000000101010105 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000001000000000000E8 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000010000000000000000C8 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000101010101010192 +:10C7A0000000000000000001000000010101000085 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000010101010101010151 +:10C7E0000101010101010100000000000000000042 +:10C7F0000000000101000000000000000000000037 +:10C800000000000001000001000000000000000026 +:10C810000000000000000000000001010001000015 +:10C820000000000000000000000000000101010104 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000001000000000000E7 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000010000000000000000C7 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000101010101010191 +:10C8A0000000000000000001000101010101000082 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000010101010101010150 +:10C8E0000101010101010100000000000000000041 +:10C8F0000000010101000001000100000000000132 +:10C900000000010001000001000000000000000024 +:10C910000000000000000000000001010101000013 +:10C920000000000000000001000000000101010102 +:10C9300000000000000000000000000100000000F6 +:10C9400000000000000000000101000100000000E4 +:10C9500000000000000100000000000000000000D6 +:10C9600000000000000000010000000000000000C6 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C99000000000000000000001010101010101018F +:10C9A0000000000000000001000101010101000081 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D000000000000000000001010101010101014F +:10C9E0000101010101010100000000000000000040 +:10C9F0000001010101000001000100000000000130 +:10CA00000001010101000001000000000000000021 +:10CA10000000000000000000000001010101000012 +:10CA20000000000000000001000000000101010101 +:10CA300000000000000000000000000100000000F5 +:10CA400000000000000000000101000100000000E3 +:10CA500000000000000100000000000000000000D5 +:10CA600000000000000000010000000000000000C5 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000010000000000000000A5 +:10CA9000000000000000000001010101010101018E +:10CAA000000000000000000100010101010101017E +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD000000000000000000001010101010101014E +:10CAE0000101010101010100010101010101000039 +:10CAF000010101010100000101010000000001012C +:10CB0000010101010100000100000000000001001E +:10CB1000000000000000000000000101010101010F +:10CB20000000000000000001000000000101010100 +:10CB300000000000000000000101000100000000F2 +:10CB400000000000000000000101010100000000E1 +:10CB500000000000000100000000000100000000D3 +:10CB600000000000000000010000000000000000C4 +:10CB700000000000000000010000000000000000B4 +:10CB800000000000000000010000000000000000A4 +:10CB9000000000000000000001010101010101018D +:10CBA000000000000000000100010101010101017D +:10CBB0000000000000000000000000010000000074 +:10CBC0000000000000000000000000000000000065 +:10CBD000000000000000000001010101010101014D +:10CBE0000101010101010100010101010101000038 +:10CBF000010101010100000101010000000001012B +:10CC0000010101010100000100000000000001001D +:10CC1000000000000000000000000101010101010E +:10CC200000000000000000010000000001010101FF +:10CC300000000000000000000101000100000000F1 +:10CC400000000000000000000101010100000000E0 +:10CC500000000000000100000000000100000000D2 +:10CC600000000000000000010000000000000000C3 +:10CC700000000000000000010000000100000000B2 +:10CC800000000000000000010001000100000000A1 +:10CC9000000000000000000101010101010101018B +:10CCA0000001000001000101010101010101010178 +:10CCB0000000000000000001000000010000000072 +:10CCC0000000000000000000000000000000000064 +:10CCD000000000000000000001010101010101014C +:10CCE0000101010101010100010101010101010135 +:10CCF000010101010100000101010000000001012A +:10CD0000010101010100000100000000000001011B +:10CD1000000000000000000000000101010101010D +:10CD200000000000000000010100000001010101FD +:10CD300000000000000000000101010100010000EE +:10CD400000000000000000000101010100000000DF +:10CD500000000000000100000101000100000000CF +:10CD600000000000000000010000000000000000C2 +:10CD700000000000000000010000000100000000B1 +:10CD800000000000000000010001000100000000A0 +:10CD9000000000000000000101010101010101018A +:10CDA0000001000001010101010101010101010176 +:10CDB0000000000000000001000000010000000071 +:10CDC0000000000000000000000000000000000063 +:10CDD000000000000000000001010101010101014B +:10CDE0000101010101010100010101010101010134 +:10CDF0000101010101000001010100000000010129 +:10CE0000010101010100000100000000000001011A +:10CE1000000000010000010000000101010101010A +:10CE200000010000000000010100000001010101FB +:10CE300000000000000000000101010100010000ED +:10CE400000000000000000000101010100000000DE +:10CE500000000000000100000101000100000000CE +:10CE600000000000000001010000000000000000C0 +:10CE700000000000000000010001000100000000AF +:10CE8000000000000000000100010001000000009F +:10CE90000000000000000001010101010101010189 +:10CEA0000001000001010101010101010101010175 +:10CEB0000000000000000001000000010000000070 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000020101010101010149 +:10CEE0000101010101010100010101010101010133 +:10CEF0000101010101000001010100010000010127 +:10CF00000101010101010001000100000000010117 +:10CF10000000010100000100000001010101010108 +:10CF200000010100000000010101000001010101F8 +:10CF300000000000000000000101010101010000EB +:10CF400000000000000000000101010100000000DD +:10CF500000000000000100000101000100000000CD +:10CF600000000000000001010101000100000000BC +:10CF700000000000000000010001000100000000AE +:10CF8000000000000000010100010001000000009D +:10CF90000000000000000001010101010101010188 +:10CFA0000101010001010101010101010101010172 +:10CFB000000000000000000100000001000100006E +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000020101010101010148 +:10CFE0000101010101010100010101010101010132 +:10CFF0000101010101000001010100010000010126 +:10D000000101010101010001000100000000010116 +:10D010000001010100000100000001010101010106 +:10D0200000010100000000010101000001010101F7 +:10D0300000000000000000000101010101010000EA +:10D0400000000000000000000101010100000000DC +:10D0500000000000000100000101000100000000CC +:10D0600000000000000001010101000100000000BB +:10D0700000000000000001010101010100000000AA +:10D080000000000000000101010101010001000099 +:10D090000000000000000001010101010101010187 +:10D0A0000101010101010101010101010101010170 +:10D0B000000000000000000100000001000100006D +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000020202010101010145 +:10D0E0000101010101010100010101010101010131 +:10D0F0000101010101000001010101010001010123 +:10D100000101010101010001000101010000010113 +:10D110000001010100000100010001010101010104 +:10D1200000010100000000010101000101010101F5 +:10D1300000000100000000000101010101010000E8 +:10D1400000000000000000000101010101010000D9 +:10D1500000000000000100000101010100000000CA +:10D1600000000000000101010101000100000000B9 +:10D1700000000000000001010101010100000000A9 +:10D180000000000000000101010101010001000098 +:10D190000000000000000101010101010101010185 +:10D1A000010101010101010101010101010101016F +:10D1B0000001000001000101000101010101000066 +:10D1C000000000000000000000000000000000005F +:10D1D0000000000000000000020202010101010144 +:10D1E000010202020202010001010101010101012B +:10D1F0000101010101000001010101010001010122 +:10D200000101010101010001000101010000010112 +:10D210000001010101000100010001010101010102 +:10D2200000010100000000010101000101010101F4 +:10D2300000010100000000000101010101010000E6 +:10D2400000000000000000000101010101010000D8 +:10D2500000000000000100000101010100000000C9 +:10D2600000000000010101010101000100000000B7 +:10D2700000000000000001010101010100010000A7 +:10D280000000000000010101010101010101000095 +:10D290000000000000010101010101010101010183 +:10D2A000010101010101010101010101010101016E +:10D2B0000001000001010101000101010101000064 +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000002020202020202013F +:10D2E0000202020202020100010101010101010129 +:10D2F0000101010101000001010101010001010121 +:10D300000101010101010001000101010000010111 +:10D3100001010101010001010100010101010101FF +:10D3200000010100000000010101010101010101F2 +:10D3300001010100000100000101010101010000E3 +:10D3400000000000000000000101010101010000D7 +:10D3500000000000000100000101010100000000C8 +:10D3600000000000010101010101010100000000B5 +:10D3700000000000000101010101010100010000A5 +:10D380000000000001010101010101010101000093 +:10D390000000000001010101010101010101010181 +:10D3A000010101010101010101010101010101016D +:10D3B0000001000001010101000101010101010161 +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000002020202020202023D +:10D3E0000202020202020100020101010101010127 +:10D3F0000101010101000001010101010001010120 +:10D400000101010101010001000101010000010110 +:10D4100001010101010001010100010101010101FE +:10D4200000010100000000010101010101010101F1 +:10D4300001010101000100000101010101010000E1 +:10D4400000000000000000000101010101010000D6 +:10D4500000000000000100000101010100000000C7 +:10D4600000000000010101010101010100000000B4 +:10D4700000000000010101010101010101010000A2 +:10D480000000000001010101010101010101000191 +:10D490000000000001010101010101010101010180 +:10D4A000010101010101010101010101010101016C +:10D4B000010101000101010100010101010101015E +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000002020202020202023C +:10D4E0000202020202020100020101010101010126 +:10D4F000010101010101000102010101010101011C +:10D50000010101010101000101010101000001010E +:10D5100001010101010101010101010101010101FB +:10D5200001010100000000010101010101010101EF +:10D5300001010101000100000101010101010101DE +:10D5400000000000000000000101010101010001D4 +:10D5500000000000000100000101010101010000C4 +:10D5600000000000010101010101010101010000B1 +:10D5700000000000010101010101010101010000A1 +:10D580000000000001010101010101010101000190 +:10D59000000000000101010101010101010101017F +:10D5A000010101010101010101010101010101016B +:10D5B000010101010101010101010101010101015B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000002020202020202023B +:10D5E0000202020202020200020201010101010123 +:10D5F000010101010101000102020101010101011A +:10D60000010101010101000101010101000001010D +:10D6100001010101010101010101010101010101FA +:10D6200001010100000000010101010101010101EE +:10D6300001010101010100000101010101010101DC +:10D6400000000000010000000101010101010001D2 +:10D6500000000001010100000101010101010000C1 +:10D6600000000000010101010101010101010000B0 +:10D67000000000000101010101010101010100019F +:10D68000000000000101010101010101010101018E +:10D69000000000000101010101010101010101017E +:10D6A000010101010101010101010101010101016A +:10D6B000010101010101010101010101010101015A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000002020202020202023A +:10D6E0000202020202020200020202010101010121 +:10D6F0000101010101010001020201010101010119 +:10D70000010101010101000101010101010101010A +:10D7100001010101010101010101020101010101F8 +:10D7200001010100000000010101010102020101EB +:10D7300001010101010100010101010101010101DA +:10D7400000000100010000000201010101010101CE +:10D7500000000001010100010101010101010000BF +:10D7600000000000010101010101010101010000AF +:10D77000000000000101010101010101010100019E +:10D78000000000000101010101010101010101018D +:10D79000000000000101010101010101010101017D +:10D7A0000101010101010101010101010101010169 +:10D7B0000101010101010101010101010101010159 +:10D7C0000000000000000001000000000000000058 +:10D7D0000000000000000000020202020202020239 +:10D7E000020202020202020002020201020101011F +:10D7F0000202020201010001020201010101010114 +:10D800000101010101010001010101010101010109 +:10D8100001010101010101010101020101010101F7 +:10D8200001010100000000010201010102020101E9 +:10D8300001010101010100010201010101010101D8 +:10D8400000010100010000000202010101010101CB +:10D8500000000001010100010101010101010000BE +:10D8600000000000010101010101010101010000AE +:10D87000000000000101010101010101010100019D +:10D88000000000000101010101010101010101018C +:10D89000000000000101010102020101010101017A +:10D8A0000101010101010101010101010101010168 +:10D8B0000101010101010101010101010101010158 +:10D8C0000000000000000001000000000000000057 +:10D8D0000000000000000000020202020202020238 +:10D8E000020202020202020002020202020202011B +:10D8F0000202020202010001020201010101010112 +:10D900000101010101010001010201010101010107 +:10D9100001010101010101010101020201010101F5 +:10D9200001010100000000010201010102020101E8 +:10D9300001010101010100010201010101010101D7 +:10D9400000010100010000000202010101010101CA +:10D9500000000001010100010201010101010000BC +:10D9600000000000010101010101010101010000AD +:10D97000000000000101010101010101010100019C +:10D980000001000101010101010101010101010189 +:10D990000000000101010101020202010101010177 +:10D9A0000101010101010101010101010101010167 +:10D9B0000101010101010101010101010101010157 +:10D9C0000000000000000001000000000000000056 +:10D9D0000000000000000000020202020202020237 +:10D9E0000202020202020200020202020202020219 +:10D9F000020202020201000102020101010102020F +:10DA00000101010101010101010201010101020104 +:10DA100001010101010101010201020202020101F1 +:10DA200001010100000000010201010102020201E6 +:10DA300001010101010100010202010101010101D5 +:10DA400000010101010000000202010101010101C8 +:10DA500000010001010101010201010101010000B9 +:10DA600000000000010101010101010101010000AC +:10DA7000000000000101010101010101010101019A +:10DA80000001010101010101010101010101010187 +:10DA90000000000101010101020202010101010176 +:10DAA0000101010101010101020201010101010164 +:10DAB0000101010101010101010101010101010156 +:10DAC0000001000001000001000000000000000053 +:10DAD0000000000000000000020202020202020236 +:10DAE0000202020202020200020202020202020218 +:10DAF000020202020201000102020201010102020D +:10DB000002020201010101010202020101010201FE +:10DB100001010101010101010201020202020101F0 +:10DB200001010100000000010202010102020202E3 +:10DB300001010101010100010202010101010101D4 +:10DB400000010101010000000202020101010101C6 +:10DB500000010101010101010202010101010001B5 +:10DB600000000100010101010201010101010001A8 +:10DB70000000000001010101020101010101010198 +:10DB80000001010101010101020201010101010184 +:10DB90000001000101010101020202020201010172 +:10DBA0000101010101010101020202020101010161 +:10DBB0000101010101010101010101010101010155 +:10DBC0000001000001010001000000000000000051 +:10DBD0000000000000000000020202020202020235 +:10DBE0000202020202020200020202020202020217 +:10DBF000020202020201000102020202010102020B +:10DC000002020202020101020202020101010202F9 +:10DC100001010101010101010201020202020201EE +:10DC200001010100000001010202010102020202E1 +:10DC300001010101010101010202020201010101D0 +:10DC400000010101010000000202020201010101C4 +:10DC500000010101010101010202010101010001B4 +:10DC600000000101010101010201010101010001A6 +:10DC70000000000001010101020201010101010196 +:10DC80000001010101010101020201010101010183 +:10DC9000010101010101010102020202020202016D +:10DCA000010101010101010102020202020101015F +:10DCB0000101010101010101010101010101010154 +:10DCC000000100000101010100000000000000004F +:10DCD0000000000000000000020202020202020234 +:10DCE0000202020202020200020202020202020216 +:10DCF000020202020201000102020202010102020A +:10DD000002020202020101020202020201010202F7 +:10DD100001010101010101010201020202020202EC +:10DD200001010100000001010202010102020202E0 +:10DD300001010101010101010202020201010101CF +:10DD400001010101010000010202020201010101C1 +:10DD500001010101010101010202010201010101B0 +:10DD600000000101010101010202010101010001A4 +:10DD70000000000001010101020201010101010195 +:10DD80000001010101010101020201010101010182 +:10DD9000010101010101010102020202020202026B +:10DDA000010101010101010102020202020201015D +:10DDB0000101010101010101010101010101010153 +:10DDC000010101000101010100000000000000004C +:10DDD0000000000000000000020202020202020233 +:10DDE0000202020202020200020202020202020215 +:10DDF0000202020202010102020202020102020206 +:10DE000002020202020101020202020201010202F6 +:10DE100001020202010101010202020202020202E7 +:10DE200001010100000001010202020102020202DE +:10DE300001010101010101010202020201010101CE +:10DE400001010101010000010202020201010101C0 +:10DE500001010101010101010202020201010101AE +:10DE600000010101010101010202010101010001A2 +:10DE70000000000101010101020202020101010191 +:10DE8000010101010101010102020202010101017E +:10DE9000010101010101010102020202020202026A +:10DEA000010101010101010102020202020201015C +:10DEB0000101010101010101010101010101010152 +:10DEC000010101010101010100000000000000004A +:10DED0000000000000000000020202020202020232 +:10DEE0000202020202020200020202020202020214 +:10DEF0000202020202010102020202020202020204 +:10DF000002020202020101020202020201010202F5 +:10DF100002020202010101010202020202020202E5 +:10DF200001020100000001010202020202020202DB +:10DF300001010101010101010202020202020101CB +:10DF400001010101010000010202020201010101BF +:10DF500001010101010101010202020201010101AD +:10DF6000010101010101010102020101010101019F +:10DF7000000001010101010102020202010101018F +:10DF8000010101010101010102020202010101017D +:10DF90000101010101010101020202020202020269 +:10DFA000010101010101010102020202020202015A +:10DFB000010101010101010102020102010101014E +:10DFC0000101010101010101000000000000000049 +:10DFD0000000000000000000020202020202020231 +:10DFE0000202020202020200020202020202020213 +:10DFF0000202020202010102020202020202020203 +:10E0000002020202020101020202020202010202F3 +:10E0100002020202010101010202020202020202E4 +:10E0200001020200000001010202020202020202D9 +:10E0300001010101010101010202020202020101CA +:10E0400001010101010000010202020202010101BD +:10E0500001010101010101010202020201010101AC +:10E06000010101010101010102020202010101019C +:10E07000000101010101010102020202010101018D +:10E08000010101010101010102020202010101017C +:10E090000101010101010101020202020202020268 +:10E0A0000101010101010101020202020202020258 +:10E0B000010101010101010102020202010101014C +:10E0C0000101010101010101000000000000000048 +:10E0D0000000000000000000020202020202020230 +:10E0E0000202020202020200020202020202020212 +:10E0F0000202020202010102020202020202020202 +:10E1000002020202020201020202020202020202F0 +:10E1100002020202010102010202020202020202E2 +:10E1200001020200000101020202020202020202D6 +:10E1300002020201010101010202020202020101C6 +:10E1400001010101010000010202020202020101BB +:10E1500001010101010201010202020201010101AA +:10E16000010101010101010202020202010101019A +:10E17000000101010101010102020202010101018C +:10E180000101010101010101020202020202010179 +:10E190000101010101010101020202020202020267 +:10E1A0000102010101010102020202020202020255 +:10E1B000010101010101010102020202010101014B +:10E1C0000101010101010101000000020000000045 +:10E1D000000000000000000102020202020202022E +:10E1E0000202020202020200020202020202020211 +:10E1F0000202020202020102020202020202020200 +:10E2000002020202020201020202020202020202EF +:10E2100002020202020102010202020202020202E0 +:10E2200002020201000101020202020202020202D3 +:10E2300002020201010101010202020202020101C5 +:10E2400001010101010001010202020202020101B9 +:10E2500001010101010201010202020202010101A8 +:10E260000101010101010102020202020101010199 +:10E270000001010101010101020202020202010189 +:10E280000101010101010101020202020202010178 +:10E290000101010101010101020202020202020266 +:10E2A0000202010101010102020202020202020253 +:10E2B0000101010101010101020202020202010148 +:10E2C0000101010101010101000000020000000044 +:10E2D000000000000000000102020202020202022D +:10E2E0000202020202020200020202020202020210 +:10E2F00002020202020201020202020202020202FF +:10E3000002020202020201020202020202020202EE +:10E3100002020202020102010202020202020202DF +:10E3200002020201000101020202020202020202D2 +:10E3300002020202010101010202020202020201C2 +:10E3400001010101010001010202020202020101B8 +:10E3500001010101010201010202020202020101A6 +:10E360000101010101010102020202020201010197 +:10E370000101010101010101020202020202010187 +:10E380000101010101010102020202020202010176 +:10E390000101010101010101020202020202020265 +:10E3A0000202020102010102020202020202020250 +:10E3B0000101010101010101020202020202010147 +:10E3C0000101010101010101000000020000000043 +:10E3D000000000000000000102020202020202022C +:10E3E000020202020202020002020202020202020F +:10E3F00002020202020201020202020202020202FE +:10E4000002020202020201020202020202020202ED +:10E4100002020202020202010202020202020202DD +:10E4200002020201010101020202020202020202D0 +:10E4300002020202010101010202020202020202C0 +:10E4400001010101010001010202020202020202B5 +:10E4500001010101010201010202020202020101A5 +:10E460000101010101010202020202020202010194 +:10E470000101010101010102020202020202010185 +:10E480000101010101010102020202020202020273 +:10E490000101010101010102020202020202020263 +:10E4A000020202020202020202020202020202024C +:10E4B0000102010101010101020202020202020144 +:10E4C0000101010101010101000000020000000042 +:10E4D000000000000000000102020202020202022B +:10E4E000020202020202020002020202020202020E +:10E4F00002020202020201020202020202020202FD +:10E5000002020202020201020202020202020202EC +:10E5100002020202020202020202020202020202DB +:10E5200002020201010101020202020202020202CF +:10E5300002020202010201010202020202020202BE +:10E5400001010101010101010202020202020202B3 +:10E5500001010101010201010202020202020101A4 +:10E560000101010102020202020202020202010191 +:10E570000101010101010102020202020202010283 +:10E580000101010101010202020202020202020271 +:10E590000101010101010102020202020202020262 +:10E5A000020202020202020202020202020202024B +:10E5B0000202010101010102020202020202020240 +:10E5C0000101010101010101000000010000000042 +:10E5D000000000000000000102020202020202022A +:10E5E000020202020202020002020202020202020D +:10E5F00002020202020201020202020202020202FC +:10E6000002020202020201020202020202020202EB +:10E6100002020202020202020202020202020202DA +:10E6200002020201010101020202020202020202CE +:10E6300002020202020201010202020202020202BC +:10E6400001020201010101010202020202020202B0 +:10E6500001010102010201010202020202020101A2 +:10E660000101010102020202020202020202010190 +:10E670000101010101010202020202020202020280 +:10E68000010101010202020202020202020202026E +:10E69000010101010202020202020202020202025E +:10E6A000020202020202020202020202020202024A +:10E6B000020202010201010202020202020202023D +:10E6C0000101010101010101000000010000000041 +:10E6D0000000000000000001020202020202020229 +:10E6E000020202020202020002020202020202020C +:10E6F00002020202020201020202020202020202FB +:10E7000002020202020201020202020202020202EA +:10E7100002020202020202020202020202020202D9 +:10E7200002020201010101020202020202020202CD +:10E7300002020202020201010202020202020202BB +:10E7400001020201020101010202020202020202AE +:10E75000010201020202010102020202020202029D +:10E76000010101010202020202020202020201018F +:10E77000010101010202020202020202020202027D +:10E78000010201010202020202020202020202026C +:10E79000010101010202020202020202020202025D +:10E7A0000202020202020202020202020202020249 +:10E7B0000202020202020202020202020202020239 +:10E7C0000101010101010101000000010000000040 +:10E7D0000000000000000001020202020202020228 +:10E7E000020202020201020002020202020202020C +:10E7F00002020202020201020202020202020202FA +:10E8000002020202020201020202020202020202E9 +:10E8100002020202020202020202020202020202D8 +:10E8200002020201010101020202020202020202CC +:10E8300002020202020201010202020202020202BA +:10E8400002020202020101010202020202020202AB +:10E85000020202020202010102020202020202029A +:10E86000010102010202020202020202020201028C +:10E87000010101010202020202020202020202027C +:10E880000102020202020202020202020202020269 +:10E890000202010202020202020202020202020259 +:10E8A0000202020202020202020202020202020248 +:10E8B0000202020202020202020202020202020238 +:10E8C000010101010101010100000001000000003F +:10E8D0000000000002000001020202020202020225 +:10E8E000020202020101020002020202020202020C +:10E8F00002020202020201020202020202020202F9 +:10E9000002020202020202020202020202020202E7 +:10E9100002020202020202020202020202020202D7 +:10E9200002020201010101020202020202020202CB +:10E9300002020202020201020202020202020202B8 +:10E9400002020202020101010202020202020202AA +:10E950000202020202020101020202020202020299 +:10E960000202020202020202020202020202020287 +:10E97000010101010202020202020202020202027B +:10E980000202020202020202020202020202020267 +:10E990000202020202020202020202020202020257 +:10E9A0000202020202020202020202020202020247 +:10E9B0000202020202020202020202020202020237 +:10E9C000010201010101010101020001000000003A +:10E9D0000000000002000001020202020202020224 +:10E9E000020201010101020002020202020202020D +:10E9F00002020202020201020202020202020202F8 +:10EA000002020202020202020202020202020202E6 +:10EA100002020202020202020202020202020202D6 +:10EA200002020201010101020202020202020202CA +:10EA300002020202020201020202020202020202B7 +:10EA400002020202020101010202020202020202A9 +:10EA50000202020202020102020202020202020297 +:10EA60000202020202020202020202020202020286 +:10EA7000010101010202020202020202020202027A +:10EA80000202020202020202020202020202020266 +:10EA90000202020202020202020202020202020256 +:10EAA0000202020202020202020202020202020246 +:10EAB0000202020202020202020202020202020236 +:10EAC0000202010101010101010200010000000038 +:10EAD0000000000002000001020202020202020223 +:10EAE000020101010101020002020202020202020D +:10EAF00002020202020202020202020202020202F6 +:10EB000002020202020202020202020202020202E5 +:10EB100002020202020202020202020202020202D5 +:10EB200002020202010102020202020202020202C7 +:10EB300002020202020202020202020202020202B5 +:10EB400002020202020101010202020202020202A8 +:10EB50000202020202020202020202020202020295 +:10EB60000202020202020202020202020202020285 +:10EB70000102020202020202020202020202020276 +:10EB80000202020202020202020202020202020265 +:10EB90000202020202020202020202020202020255 +:10EBA0000202020202020202020202020202020245 +:10EBB0000202020202020202020202020202020235 +:10EBC0000202020102010102020202010202020229 +:10EBD0000000000002020001020202020202020220 +:10EBE000010101010101010002020202020202020E +:10EBF00002020202020202020202020202020202F5 +:10EC000002020202020202020202020202020202E4 +:10EC100002020202020202020202020202020202D4 +:10EC200002020202010102020202020202020202C6 +:10EC300002020202020202020202020202020202B4 +:10EC400002020202020101010202020202020202A7 +:10EC50000202020202020202020202020202020294 +:10EC60000202020202020202020202020202020284 +:10EC70000202020202020202020202020202020274 +:10EC80000202020202020202020202020202020264 +:10EC90000202020202020202020202020202020254 +:10ECA0000202020202020202020202020202020244 +:10ECB0000202020202020202020202020202020234 +:10ECC0000202020202020102020102010202020227 +:10ECD0000000000201020000020202020201010122 +:10ECE000010101010101010102020202020202020C +:10ECF00002020202020202020202020202020202F4 +:10ED000002020202020202020202020202020202E3 +:10ED100002020202020202020202020202020202D3 +:10ED200002020202010202020202020202020202C4 +:10ED300002020202020202020202020202020202B3 +:10ED400002020202020101010202020202020202A6 +:10ED50000202020202020202020202020202020293 +:10ED60000202020202020202020202020202020283 +:10ED70000202020202020202020202020202020273 +:10ED80000202020202020202020202020202020263 +:10ED90000202020202020202020202020202020253 +:10EDA0000202020202020202020202020202020243 +:10EDB0000202020202020202020202020202020233 +:10EDC0000202020202020202020102010202020225 +:10EDD0000200020201020000020201010101010120 +:10EDE000010101010101010102020202020202020B +:10EDF00002020202020202020202020202020202F3 +:10EE000002020202020202020202020202020202E2 +:10EE100002020202020202020202020202020202D2 +:10EE200002020202020202020202020202020202C2 +:10EE300002020202020202020202020202020202B2 +:10EE400002020202020101020202020202020202A4 +:10EE50000202020202020202020202020202020292 +:10EE60000202020202020202020202020202020282 +:10EE70000202020202020202020202020202020272 +:10EE80000202020202020202020202020202020262 +:10EE90000202020202020202020202020202020252 +:10EEA0000202020202020202020202020202020242 +:10EEB0000202020202020202020202020202020232 +:10EEC0000202020202020202020101010201020226 +:10EED000020202020101020001010101010101011E +:10EEE000010101010101010102020202020202020A +:10EEF00001010101010202020202020202020202F7 +:10EF000002020202020202020202020202020202E1 +:10EF100002020202020202020202020202020202D1 +:10EF200002020202020202020202020202020202C1 +:10EF300002020202020202020202020202020202B1 +:10EF400002020202020101020202020202020202A3 +:10EF50000202020202020202020202020202020291 +:10EF60000202020202020202020202020202020281 +:10EF70000202020202020202020202020202020271 +:10EF80000202020202020202020202020202020261 +:10EF90000202020202020202020202020202020251 +:10EFA0000202020202020202020202020202020241 +:10EFB0000202020202020202020202020202020231 +:10EFC0000202020202020202020101010101020127 +:10EFD000020202020101020001010101010101011D +:10EFE000010101010101010102020202020201010B +:10EFF00001010101010202020202020202020202F6 +:10F0000002020202020202020202020202020202E0 +:10F0100002020202020202020202020202020202D0 +:10F0200002020202020202020202020202020202C0 +:10F0300002020202020202020202020202020202B0 +:10F0400002020202020102020202020202020202A1 +:10F050000202020202020202020202020202020290 +:10F060000202020202020202020202020202020280 +:10F070000202020202020202020202020202020270 +:10F080000202020202020202020202020202020260 +:10F090000202020202020202020202020202020250 +:10F0A0000202020202020202020202020202020240 +:10F0B0000202020202020202020202020202020230 +:10F0C0000202020202020202020201020101010125 +:10F0D000020202020101010001010101010101011D +:10F0E000010101010101010102020202010101010C +:10F0F00001010101010102020202020202020202F6 +:10F1000002020202020202020202020202020202DF +:10F1100002020202020202020202020202020202CF +:10F1200002020202020202020202020202020202BF +:10F1300002020202020202020202020202020202AF +:10F14000020202020202020202020202020202029F +:10F15000020202020202020202020202020202028F +:10F16000020202020202020202020202020202027F +:10F17000020202020202020202020202020202026F +:10F18000020202020202020202020202020202025F +:10F19000020202020202020202020202020202024F +:10F1A000020202020202020202020202020202023F +:10F1B000020202020202020202020202020202022F +:10F1C0000202020202020202020201020101010124 +:10F1D000020202010101010001010101010101011D +:10F1E000010101010101010101010101010101010F +:10F1F00001010101010102010202020202020202F6 +:10F2000002020202020202020202020202020202DE +:10F2100002020202020202020202020202020202CE +:10F2200002020202020202020202020202020202BE +:10F2300002020202020202020202020202020202AE +:10F24000020202020202020202020202020202029E +:10F25000020202020202020202020202020202028E +:10F26000020202020202020202020202020202027E +:10F27000020202020202020202020202020202026E +:10F28000020202020202020202020202020202025E +:10F29000020202020202020202020202020202024E +:10F2A000020202020202020202020202020202023E +:10F2B000020202020202020202020202020202022E +:10F2C0000202020202020202020202020101010122 +:10F2D000020201010101010001010101010101011D +:10F2E000010101010101010101010101010101010E +:10F2F00001010101010102010202020202020101F7 +:10F3000001010101010202020202020202020202E2 +:10F3100002020202020202020202020202020202CD +:10F3200002020202020202020202020202020202BD +:10F3300002020202020202020202020202020202AD +:10F34000020202020202020202020202020202029D +:10F35000020202020202020202020202020202028D +:10F36000020202020202020202020202020202027D +:10F37000020202020202020202020202020202026D +:10F38000020202020202020202020202020202025D +:10F39000020202020202020202020202020202024D +:10F3A000020202020202020202020202020202023D +:10F3B000020202020202020202020202020202022D +:10F3C0000202020202020202020202020101010121 +:10F3D000010101010101010001010101010101011E +:10F3E000010101010101010101010101010101010D +:10F3F00001010101010102010101010101010101FC +:10F4000001010101010102010202020202020202E3 +:10F4100002020202020202020202020202020202CC +:10F4200002020202020202020202020202020202BC +:10F4300002020202020202020202020202020202AC +:10F44000020202020202020202020202020202029C +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202020202027C +:10F47000020202020202020202020202020202026C +:10F48000020202020202020202020202020202025C +:10F49000020202020202020202020202020202024C +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C0000202020202020202020202020101010120 +:10F4D000010101010101010001010101010101011D +:10F4E000010101010101010101010101010101010C +:10F4F00001010101010101010101010101010101FC +:10F5000001010101010102010202020202020101E4 +:10F5100001010101020202020202020202020202CF +:10F5200002020202020202020202020202020202BB +:10F5300002020202020202020202020202020202AB +:10F54000020202020202020202020202020202029B +:10F55000020202020202020202020202020202028B +:10F56000020202020202020202020202020202027B +:10F57000020202020202020202020202020202026B +:10F58000020202020202020202020202020202025B +:10F59000020202020202020202020202020202024B +:10F5A000020202020202020202020202020202023B +:10F5B000020202020202020202020202020202022B +:10F5C000020202020202020202020202020201011D +:10F5D000010101010101010001010101010101011C +:10F5E000010101010101010101010101010101010B +:10F5F00001010101010101010101010101010101FB +:10F6000001010101010101010201010101010101E9 +:10F6100001010101010101020202020202020202D1 +:10F6200002020202020202020202020202020202BA +:10F6300002020202020202020202020202020202AA +:10F64000020202020202020202020202020202029A +:10F65000020202020202020202020202020202028A +:10F66000020202020202020202020202020202027A +:10F67000020202020202020202020202020202026A +:10F68000020202020202020202020202020202025A +:10F69000020202020202020202020202020202024A +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020202020202020201011C +:10F6D000010101010101010001010101010101011B +:10F6E000010101010101010101010101010101010A +:10F6F00001010101010101010101010101010101FA +:10F7000001010101010101010101010101010101E9 +:10F7100001010101010101010202010101010101D7 +:10F7200001010102020202020202020202020202BC +:10F7300002020202020202020202020202020202A9 +:10F740000202020202020202020202020202020299 +:10F750000202020202020202020202020202020289 +:10F760000202020202020202020202020202020279 +:10F770000202020202020202020202020202020269 +:10F780000202020202020202020202020202020259 +:10F790000202020202020202020202020202020249 +:10F7A0000202020202020202020202020202020239 +:10F7B0000202020202020202020202020202020229 +:10F7C0000202020202020202020202020202020219 +:10F7D000010101010101010001010101010101011A +:10F7E0000101010101010101010101010101010109 +:10F7F00001010101010101010101010101010101F9 +:10F8000001010101010101010101010101010101E8 +:10F8100001010101010101010101010101010101D8 +:10F8200001010101020202010202020201010101C1 +:10F8300001010101020202020202020202020202AC +:10F840000202020202020202020202020202020298 +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202020268 +:10F880000202020202020202020202020202020258 +:10F890000202020202020202020202020202020248 +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202020202020202020218 +:10F8D0000101010102010102010101010101010116 +:10F8E0000101010101010101010101010101010108 +:10F8F00001010101010101010101010101010101F8 +:10F9000001010101010101010101010101010101E7 +:10F9100001010101010101010101010101010101D7 +:10F9200001010101010101010101010101010101C7 +:10F9300001010101010102020202020202020202AD +:10F940000202020202020202020202020202020297 +:10F950000202020202020202000000000000000097 +:10F960000000000000000000020202020202020287 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020202020202020247 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202020202020202020227 +:10F9C0000202020202020202020202020202020217 +:10F9D0000101010102020102010101010101010114 +:10F9E0000101010101010101010101010101010107 +:10F9F00001010101010101010101010101010101F7 +:10FA000001010101010101010101010101010101E6 +:10FA100001010101010101010101010101010101D6 +:10FA200001010101010101010101010101010101C6 +:10FA300001010101010101010101010101010101B6 +:10FA4000010101010102020202020202020202029B +:10FA50000202020202020202000000000000000096 +:10FA60000000000000000000020202020202020286 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202020202020202020226 +:10FAC0000202020202020202020202020202020216 +:10FAD000020202020202020201010101010101010E +:10FAE0000101010101010101010101010101010106 +:10FAF00001010101010101010101010101010101F6 +:10FB000001010101010101010101010101010101E5 +:10FB100001010101010101010101010101010101D5 +:10FB200001010101010101010101010101010101C5 +:10FB300001010101010101010101010101010101B5 +:10FB400001010101010202020101010101010101A2 +:10FB5000010101010101020200000000000000009B +:10FB60000000000000000000020202020202020285 +:10FB70000202020202020202000000000000000075 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000020202020202020255 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202020202020202020215 +:10FBD000020202020202020201010101010101010D +:10FBE0000101010101010101010101010101010105 +:10FBF00001010101010101010101010101010101F5 +:10FC000001010101010101010101010101010101E4 +:10FC100001010101010101010101010101010101D4 +:10FC200001010101010101010101010101010101C4 +:10FC300001010101010101010101010101010101B4 +:10FC400001010101010101010101010101010101A4 +:10FC5000010101010101010100000000000000009C +:10FC60000000000000000000000000000000000094 +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000020202020202020254 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202020202020202020214 +:10FCD000020202020202020201010101010101010C +:10FCE0000101010101010101010101010101010104 +:10FCF00001010101010101010101010101010101F4 +:10FD000001010101010101010101010101010101E3 +:10FD100001010101010101010101010101010101D3 +:10FD200001010101010101010101010101010101C3 +:10FD300001010101010101010101010101010101B3 +:10FD400001010101010101010101010101010101A3 +:10FD50000101010101010101010101010101010193 +:10FD60000101010101010101010101010101010183 +:10FD7000010101010101010100000000000000007B +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000020202020202020253 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202020202020202020223 +:10FDC0000202020202020202020202020202020213 +:10FDD000020202020202020201010101010101010B +:10FDE0000101010101010101010101010101010103 +:10FDF00001010101010101010101010101010101F3 +:10FE000001010101010101010101010101010101E2 +:10FE100001010101010101010101010101010101D2 +:10FE200001010101010101010101010101010101C2 +:10FE300001010101010101010101010101010101B2 +:10FE400001010101010101010101010101010101A2 +:10FE50000101010101010101010101010101010192 +:10FE60000101010101010101010101010101010182 +:10FE70000101010101010101010101010101010172 +:10FE8000010101010101010100000000000000006A +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000020202020202020242 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020202020202020202020202020212 +:10FED000020202020202020201010101010101010A +:10FEE0000101010101010101010101010101010102 +:10FEF00001010101010101010101010101010101F2 +:10FF000001010101010101010101010101010101E1 +:10FF100001010101010101010101010101010101D1 +:10FF200001010101010101010101010101010101C1 +:10FF300001010101010101010101010101010101B1 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101010101010101010191 +:10FF60000101010101010101010101010101010181 +:10FF70000101010101010101010101010101010171 +:10FF80000101010101010101010101010101010161 +:10FF90000101010101010101010101010101010151 +:10FFA0000101010101010101000000000000000049 +:10FFB0000000000000000000020202020202020231 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202010101010101010109 +:10FFE0000101010101010101010101010101010101 +:10FFF00001010101010101010101010101010101F1 +:0200000290006C +:1000000001010101010101010101010101010101E0 +:1000100001010101010101010101010101010101D0 +:1000200001010101010101010101010101010101C0 +:1000300001010101010101010101010101010101B0 +:1000400001010101010101010101010101010101A0 +:100050000101010101010101010101010101010190 +:100060000101010101010101010101010101010180 +:100070000101010101010101010101010101010170 +:100080000101010101010101010101010101010160 +:100090000101010101010101010101010101010150 +:1000A0000101010101010101010101010101010140 +:1000B0000101010101010101000000000000000038 +:1000C0000000000000000000020202020202020220 +:1000D0000202020202020202010101010101010108 +:1000E0000101010101010101010101010101010100 +:1000F00001010101010101010101010101010101F0 +:1001000001010101010101010101010101010101DF +:1001100001010101010101010101010101010101CF +:1001200001010101010101010101010101010101BF +:1001300001010101010101010101010101010101AF +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:10019000010101010101010101010101010101014F +:1001A000010101010101010101010101010101013F +:1001B000010101010101010101010101010101012F +:1001C0000101010101010101020202020202020217 +:1001D0000202020202020202010101010101010107 +:1001E00001010101010101010101010101010101FF +:1001F00001010101010101010101010101010101EF +:1002000001010101010101010101010101010101DE +:1002100001010101010101010101010101010101CE +:1002200001010101010101010101010101010101BE +:1002300001010101010101010101010101010101AE +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:10029000010101010101010101010101010101014E +:1002A000010101010101010101010101010101013E +:1002B000010101010101010101010101010101012E +:1002C0000101010101010101020202020202020216 +:1002D000020202020202020200000000000000000E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D00000000000000000004000000000000000DD +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000001000000000000000000000000000000EB +:1004100000000000000000000000000000000000DC +:1004200000000000000000000000000000000000CC +:1004300000010000000000000000000000000000BB +:1004400000000000000000000000000000000000AC +:100450000001000001000100010000000000000098 +:10046000000000000000000000000000000000008C +:10047000000000000000000001000000000000007B +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000001000000000000000000000000000000EA +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300001010100000000000000000000000000B8 +:1005400000000000000000000000000000000000AB +:100550000101010101010101010000000000000092 +:10056000000000000000000000000000000000008B +:100570000000000000000001010000000000000079 +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000001000000000000000000000000000101E7 +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300001010100010000000000000000000000B6 +:1006400000000000000000000000000000000000AA +:100650000101010101010101010000000000000091 +:100660000000000000000000000000000000010188 +:100670000000000001000101010000000000000076 +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000101F8 +:1007000001000000000000000000000000000101E6 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300001010101010100010000000000000000B2 +:1007400000010000000000000000000000000000A8 +:100750000101010101010101010000000000000090 +:100760000000000000000000000000000000010187 +:100770000000000101010101010000000000000073 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000101F7 +:1008000001000000000000000000000000000101E5 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300001010101010101010000000000000000B0 +:1008400001010100000000000000000000000000A5 +:10085000010101010101010101000000000000008F +:100860000000000000000000000000000000010186 +:100870000000000101010101010000000000000072 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000010000000000000000000000000007 +:1008F00000000000000000000000000000000101F6 +:1009000001000000000000000000000000000101E4 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300001010101010101010000000000000000AF +:1009400001010100000000000000000000000000A4 +:10095000010101010101010101000000000000008E +:100960000000000000000000000000000000010185 +:10097000000000010101010101000000000001016F +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000010000000000000000000000000006 +:1009F00000000000000000000000000000000101F5 +:100A000001000000000000000000000000000101E3 +:100A100001000000000000000000000000000000D5 +:100A200000000000000000000000000000000000C6 +:100A300001010101010101010100000000000000AD +:100A400001010101000000000000000000000000A2 +:100A5000010101010101010101000000000000008D +:100A60000000000000000000000000000000010184 +:100A7000000000010101010101000000000001016E +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000010144 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000010100000000000000000000000004 +:100AF00000000000000000000000000000000101F4 +:100B000001000000000000000000000000000101E2 +:100B100001010000000000000000000000000000D3 +:100B200000000000000000000000000000000000C5 +:100B300001010101010101010100000000000101AA +:100B400001010101010000000000000000000000A0 +:100B5000010101010101010101000000000000008C +:100B60000000000000000000000000000000010183 +:100B7000000000010101010101000000000001016D +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000010153 +:100BA0000000000000000000000000000000010143 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000010100000000000000000000000003 +:100BF00000000000000000000000000000000101F3 +:100C000001000001000000000000000000000101E0 +:100C100001010000000000000000000000000101D0 +:100C200001000000000000000000000000000000C3 +:100C300001010101010101010100000000000101A9 +:100C4000010101010101000000000000000000009E +:100C5000010101010101010101000000000000008B +:100C60000000000000000000000000000000010182 +:100C7000000000010101010101000000000001016C +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000010152 +:100CA0000000010000000000000000000000010141 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE0000000010100000000000000000000000002 +:100CF00001000000000000000000000000000101F1 +:100D000001000001010000000000000000000101DE +:100D100001010000000000000000000000000101CF +:100D200001010000000000000000000000000000C1 +:100D300001010101010101010100000000000101A8 +:100D4000010101010101010000000000000000009C +:100D5000010101010101010101000000000000008A +:100D60000000000000000000000000000000010181 +:100D7000000000010101010101000000000001016B +:100D80000000000100000000000000000000000062 +:100D90000000000000000000000000000000010151 +:100DA000000101000000000000000000000001013F +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000000000000000000023 +:100DD0000000000000000000000000000000000013 +:100DE0000000020100000000000000000000000000 +:100DF00001000000000000000000000000000101F0 +:100E000001000001010000000000000000010101DC +:100E100001010000000000000000000000000101CE +:100E200001010000000000000000000000000000C0 +:100E300001010101010101010100000000000101A7 +:100E4000010101010101010100000000000000009A +:100E50000101010101010101010000000000000089 +:100E6000000000000000000000000000000101017F +:100E7000000000010101010101000000000001016A +:100E80000000000100000000000000000000000061 +:100E90000000000000000000000000000000010150 +:100EA000000101010000000000000000000101013C +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE00000000202000100000000000000000000FD +:100EF00001000000000000000000000000000101EF +:100F000001000001010000000000000000010101DB +:100F100001010000000000000000000000000101CD +:100F200001010000000000000000000000000000BF +:100F300001010101010101010100000000000101A6 +:100F40000101010101010101010000000000000098 +:100F50000101010101010101010000000000000088 +:100F6000000000000000000000000000000101017E +:100F70000000000101010101010000000000010169 +:100F80000000000100000000000000000000000060 +:100F9000000000000000000000000000000001014F +:100FA000000101010000000000000000000101013B +:100FB0000000000000000000000000000000000031 +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE00000000202000100000000000000000000FC +:100FF00001010000010000000000000000000101EC +:1010000001000001010100000000000000010101D9 +:1010100001010101000000000000000000000101CA +:1010200001010100000000000000000000000101BB +:1010300001010101010101010100000000000101A5 +:101040000101010101010101010000000000000097 +:101050000101010101010101010000000000000087 +:10106000000001000000000000000000000101017C +:101070000000000101010101010000000000010168 +:10108000000000010100000000000000000000005E +:10109000000000000000000000000000000001014E +:1010A0000101010100000000000000000001010139 +:1010B0000000000000000000000000000000000030 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E00000000202000200000000000000000000FA +:1010F00001010000010000000000000000000101EB +:1011000001000001010101000000000000010101D7 +:1011100001010101010000000000000000000101C8 +:1011200001010100000000000000000000000101BA +:1011300001010101010101010100000000000101A4 +:101140000101010101010101010000000000000096 +:101150000101010101010101010000000000000086 +:10116000000101000000000000000000000101017A +:101170000000000101010101010000000001010166 +:10118000000000010100000000000000000001015B +:10119000000000000000000000000000000101014C +:1011A0000101010101000000000000000001010137 +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000202000200000000000000000000F9 +:1011F00001010000010000000000000000000101EA +:1012000002000001010101010000000000010101D4 +:1012100001010101010100000000000000000101C6 +:1012200001010100000000000000000000000101B9 +:1012300001010101010101010100000000000101A3 +:101240000101010101010101010000000000010193 +:101250000101010101010101010000000000000085 +:101260000101010000000000000000000001010178 +:101270000001000101010101010000000001010164 +:101280000000000101000100000000000000010159 +:10129000000100000000000000000000000101014A +:1012A0000101010101000000000000010001010135 +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00001000202000200000000000000000000F7 +:1012F00001010000010000000000000000010101E8 +:1013000002010001010101010000000000010101D2 +:1013100001010101010101000000000000000101C4 +:1013200001010100000000000000000000000101B8 +:1013300001010101010101010100000000010101A1 +:101340000101010101010101010000000000010192 +:101350000101010101010101010000000000010182 +:101360000101010000000000000000000001010177 +:101370000101000101010101010000000001010162 +:101380000000000101010101000100000000010155 +:101390000101010000000000000000000001010147 +:1013A0000101010101000000000001010001010133 +:1013B000000000000000000000000000000000002D +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00001010202000202000200000000000000F1 +:1013F00001010000010000000000000000010101E7 +:1014000002010001010101010000000000010101D1 +:1014100001010101010101010000000000010101C1 +:1014200001010101000000000000000000000101B6 +:1014300001010101010101010100000000010101A0 +:101440000101010101010101010000000000010191 +:101450000101010101010101010000000000010181 +:101460000101010000000000000000010001010175 +:101470000101000101010101010000000001010161 +:101480000000000101010101010100000000010153 +:101490000101010000000000000000000001010146 +:1014A0000101010101000000000001010101010131 +:1014B000000000000000000000000000000000002C +:1014C000000000000000000000000000000000001C +:1014D000000000000000000000000000000000010B +:1014E00001010202000202020200000000000000EE +:1014F00001010100010000000000000000010101E5 +:1015000002010001010101010100000000010101CF +:1015100001010101010101010100000000010101BF +:1015200001010101010000000000000000000101B4 +:10153000020101010101010101000000000101019E +:101540000101010101010101010000000000010190 +:101550000101010101010101010000000000010180 +:101560000101010000000000000000010001010174 +:10157000010101010101010101000000000101015F +:101580000000000101010101010100000000010152 +:101590000101010000000000000000010001010144 +:1015A000010101010100010000000101010101012F +:1015B000000000000000000000000000000000002B +:1015C0000100010000000000000000000000000019 +:1015D000000000000000000000000000000000010A +:1015E00002010202000202020200000000000000EC +:1015F00002010100010000000000000000010101E3 +:1016000002010101010101010100000000010101CD +:1016100001010101010101010100000000010101BE +:1016200001010101010000000000000000000101B3 +:10163000020201010101010101000000000101019C +:10164000010101010101010101000000000001018F +:10165000020101010101010101000000000001017E +:101660000101010000000000000000010101010172 +:10167000010101010101010101000000000101015E +:101680000001000101010101010100000000010150 +:101690000101010000000000000000010001010143 +:1016A000010101010101010100010101010101012B +:1016B0000001000000000000000000000000000029 +:1016C0000101010000000000000000000000000017 +:1016D0000000000000000000000000000000000109 +:1016E00002020202000202020202000000000000E8 +:1016F00002010100010100000000000000010101E1 +:1017000002010101010101010100000000010101CC +:1017100002010101010101010100000000010101BC +:1017200001010101010000000000000000000101B2 +:10173000020201010101010101000000000101019B +:10174000020101010101010101000000000001018D +:10175000020201010101010101000000000001017C +:101760000101010000000000000001010101010170 +:10177000010101010101010101000001000101015C +:10178000010101010101010101010000000101014C +:101790000101010100000000000000010001010141 +:1017A0000101010101010101010101010101010129 +:1017B0000101010000000000000000000000010025 +:1017C0000101010000000000000000000000000016 +:1017D0000000000000000000000000000200000106 +:1017E00002020202020202020202000000000000E5 +:1017F00002010100010100000000000000010101E0 +:1018000002010101010101010100000100010101CA +:1018100002010101010101010100000000010101BB +:1018200002010101010100000000000000010101AE +:101830000202020101010101010000000001010199 +:10184000020201010101010101000000000001018B +:10185000020201010101010101000000000001017B +:10186000010101010000000000010101010101016D +:10187000010101010101010101000101000101015A +:10188000010101010101010101010000000101014B +:10189000010101010000000000000101000101013F +:1018A0000101010101010101010101010101010128 +:1018B0000101010000000000000000000000010024 +:1018C0000101010000000000000000000000000015 +:1018D0000000000000000000000000000200000105 +:1018E00002020202020202020202000100000000E3 +:1018F00002020100010100000000000000010101DE +:1019000002010101010101010100000100010101C9 +:1019100002020101010101010100000000010101B9 +:1019200002010101010101000000000000010101AC +:101930000202020101010101010000000001010198 +:10194000020201010101010101000000000001018A +:101950000202020101010101010000000000010179 +:10196000010101010100000001010101010101016A +:101970000101010101010101010001010101010158 +:10198000010101010101010101010000000101014A +:10199000010101010000000000000101010101013D +:1019A0000101010101010101010101010101010127 +:1019B0000101010100000000000000000000010121 +:1019C0000101010000000000000000000000000014 +:1019D0000000000000000000000000000200000104 +:1019E00002020202020202020202000200000000E1 +:1019F00002020100010102000000000000010101DB +:101A000002010102010101010100000101010101C6 +:101A100002020101010101010100000000010101B8 +:101A200002020101010101010000000000010101A9 +:101A30000202020202010101010000000001010195 +:101A40000202020101010101010000000001010187 +:101A50000202020202010101010000000000010176 +:101A60000101010101010001010101010101010167 +:101A70000101010202010101010001010101010155 +:101A80000101010101010101010100000001010149 +:101A9000010101010100000000000101010101013B +:101AA0000101010101010101010101010101010126 +:101AB0000101010100000000000000000000010120 +:101AC0000101010000000000000000000000000013 +:101AD0000000000000000000000002000100000102 +:101AE00002020202020202020202000200000101DE +:101AF00002020101020101020002000000010101D5 +:101B000002010102020101010100010101010101C3 +:101B100002020101010101010100000000010101B7 +:101B200002020101010101010100000000010101A7 +:101B30000202020202020101010000010001010192 +:101B40000202020101010101010000000001010186 +:101B50000202020202020201010000000001010172 +:101B60000101010101010101010101010101010165 +:101B7000010101020202020202010101010101014F +:101B80000101010101010101010100000001010148 +:101B90000101010101000000000101010101010139 +:101BA0000101010101010101010101010101010125 +:101BB000010101010000000000000000000001011F +:101BC0000101010100000000000000000000000011 +:101BD00000000002000000000002020001000001FD +:101BE00002020202020202020202020200000101DB +:101BF00002020101020101010201000000010101D4 +:101C000002020102020101010100010101010101C1 +:101C100002020101010101010100000100010101B5 +:101C200002020101010101010100000000010101A6 +:101C3000020202020202020201000001000101018F +:101C40000202020201010101010000000001010184 +:101C5000020202020202020202000000000101016F +:101C60000101010101010101010101010101010164 +:101C7000010101020202020202010101010101014E +:101C80000101010101010101010100000001010147 +:101C90000101010101000000010101010101010137 +:101CA0000101010101010101010101010101010124 +:101CB000010101010100000000000000000001011D +:101CC0000101010100000000000000000000000010 +:101CD00000010001000000000202010001000001FB +:101CE00002020202020202020202020200010101D9 +:101CF00002020201020101010101000000010202D1 +:101D000002020102020201010100010101010101BF +:101D100002020201010101010100000100010101B3 +:101D200002020201010101010100000000010101A4 +:101D3000020202020202020201000001010101018D +:101D40000202020202010101010000000001010182 +:101D5000020202020202020202000000000101016E +:101D60000201010101010101010101010101010162 +:101D7000020101020202020202010101010101014C +:101D80000101010201010101010100000001010145 +:101D90000101010101010001010101010101010134 +:101DA0000202010101010101010101010101010121 +:101DB000010101010100000000000000000101011B +:101DC000010101010000000000000000000000000F +:101DD00000010101000000000201010001000101F9 +:101DE00002020202020202020202020200010101D8 +:101DF00002020201020101010101000000010202D0 +:101E000002020102020202010100010101010202BB +:101E100002020202010101010100000101010101B0 +:101E200002020201010101010100000000010101A3 +:101E3000020202020202020202000101010101018A +:101E40000202020202020101010000000001010180 +:101E5000020202020202020202000000000101016D +:101E60000202010101010101010101010101010160 +:101E7000020201020202020202010101010101014A +:101E80000101010201010101010100000001010144 +:101E90000201010101010101010101010101010131 +:101EA000020202010101010101010101010101011F +:101EB000010101010100000000000000000101011A +:101EC000020101010100000000000000000000000C +:101ED00000010101000002000101010001000101F7 +:101EE00002020202020202020202020202020101D4 +:101EF00002020201020201010101000000010202CE +:101F000002020202020202020100010101010202B8 +:101F100002020202020101010100010101010101AD +:101F200002020201010101010100000000010101A2 +:101F30000202020202020202020001010101010189 +:101F4000020202020202020101000000000101017E +:101F5000020202020202020202000000000101016C +:101F6000020202010101010101010101010101015E +:101F70000202010202020202020101010101010149 +:101F80000201010202010101010100010001010140 +:101F9000020201010101010101010101010101012F +:101FA000020202010101010101010101010101011E +:101FB0000101010101000000000000010001010118 +:101FC000020101010100000000000000000001000A +:101FD00000000101000002000101010001000101F7 +:101FE00002020202020202020202020202020101D3 +:101FF00002020201020201010101020000010202CB +:1020000002020202020202020101010101010202B6 +:1020100002020202020201010100010101010101AB +:1020200002020202010101010100000000010101A0 +:102030000202020202020202020001010101010188 +:10204000020202020202020201000000000101017C +:10205000020202020202020202000000000101016B +:10206000020202010101010101010101010101015D +:102070000202010202020202020101010101010148 +:10208000020201020201010101010001000101013E +:10209000020201010101010101010101010101012E +:1020A000020202020101010101010101010101011C +:1020B0000201010101000100000001010001010114 +:1020C0000202010101000000000000000000010008 +:1020D00000000101020001000101010001000101F5 +:1020E00002020202020202020102020202020101D3 +:1020F00002020202020201010101010101010202C8 +:1021000002020202020202020201010101020202B3 +:1021100002020202020202010100010101010101A9 +:10212000020202020201010101000000000101019E +:102130000202020202020202020101010101010186 +:10214000020202020202020202000000000101017A +:102150000202020202020202020000010001010169 +:10216000020202010101010101010101010102025A +:102170000202020202020202020101010101010146 +:10218000020201020202020101010001010101013A +:10219000020202010101010101010101010101012C +:1021A000020202020101010101010101010101011B +:1021B0000202010101000101000001010001010111 +:1021C0000202020101000000000000000000010105 +:1021D00000000001010201020101010001010100F2 +:1021E00002020202020202020101020202020101D3 +:1021F00002020202020202010101010101020202C5 +:1022000002020202020202020201010101020202B2 +:1022100002020202020202020101010101010101A6 +:10222000020202020201010101000001000101019C +:102230000202020202020202020101010101010185 +:102240000202020202020202020000010001010178 +:102250000202020202020202020000010001010168 +:102260000202020101010101010101010101020259 +:102270000202020202020202020101010101020243 +:102280000202020202020202010101010101010136 +:10229000020202010101010101010101010101012B +:1022A0000202020202010101010101010101010119 +:1022B000020201010100010101000101000101010F +:1022C0000202020101000100000000000000010103 +:1022D00000000000010201020101010001010100F2 +:1022E00002020202020101010101020202020201D4 +:1022F00002020202020202020101010101020202C3 +:1023000002020202020202020201010101020202B1 +:1023100002020202020202020201010101010202A2 +:10232000020202020202010101000001000101019A +:102330000202020202020202020101010101020282 +:102340000202020202020202020000010001010177 +:102350000202020202020202020000010101010166 +:102360000202020101010101010101010101020258 +:102370000202020202020202020101010101020242 +:102380000202020202020202020201010101010133 +:10239000020202010101010101010101010101012A +:1023A0000202020202010101010101010101010118 +:1023B000020202010101010101010101010101010A +:1023C00002020201010101010000000100010101FE +:1023D00000000000010101010101010001010100F3 +:1023E00002020201020101010101010102020201D6 +:1023F00002020202020202020202010101020202C0 +:1024000002020202020202020201010101020202B0 +:1024100002020202020202020201010101010202A1 +:102420000202020202020201010000010101010197 +:102430000202020202020202020101010101020281 +:102440000202020202020202020000010001010176 +:102450000202020202020202020001010101010164 +:102460000202020201010101010101010102020255 +:102470000202020202020202020101010101020241 +:102480000202020202020202020201010101010132 +:102490000202020201010101010101010101020226 +:1024A0000202020202010101010101010101020215 +:1024B0000202020101010101010101010101010109 +:1024C00002020201010101010100000100010101FC +:1024D00001000000010101010101010001010100F1 +:1024E00002020101020101010101010102020200D7 +:1024F00002020202020202020202010101020202BF +:1025000002020202020202020201010201020202AE +:1025100002020202020202020201010101010202A0 +:102520000202020202020202010000010101020293 +:102530000202020202020202020101010101020280 +:102540000202020202020202020001010001010174 +:102550000202020202020202020001010101010163 +:102560000202020202010101010101010102020253 +:10257000020202020202020202010101010202023F +:102580000202020202020202020201010101010131 +:102590000202020201010101010101010101020225 +:1025A0000202020202020201010101010102020211 +:1025B0000202020201010101010101010101010107 +:1025C00002020202010101010100000100010101FA +:1025D00001000000000101010101010101010100F0 +:1025E00002020101010101010101010101010200D9 +:1025F00002020202020202020202010101020202BE +:1026000002020202020202020201020202020202AB +:10261000020202020202020202010101010202029E +:102620000202020202020202020000010101020291 +:10263000020202020202020202010101010202027E +:102640000202020202020202020001010101010172 +:102650000202020202020202020001010101010162 +:102660000202020202020101010101020102020250 +:10267000020202020202020202010101010202023E +:10268000020202020202020202020101010102022E +:102690000202020202010101010101010102020222 +:1026A000020202020202020201010202010202020D +:1026B0000202020201010101010101010101010106 +:1026C00002020202010101010100010100010101F8 +:1026D00002000000000100010000000100010100F3 +:1026E00002020101010101010101010101010200D8 +:1026F00002020202020202020202010101020202BD +:1027000002020202020202020201020202020202AA +:10271000020202020202020202010101010202029D +:10272000020202020202020202000101010102028F +:10273000020202020202020202010101010202027D +:10274000020202020202020202000101010102026F +:102750000202020202020202020101010101010160 +:102760000202020202020202020202020202020249 +:10277000020202020202020202010202010202023B +:10278000020202020202020202020101010102022D +:102790000202020202010101010101020102020220 +:1027A0000202020202020202020202020202020209 +:1027B0000202020202010101010101010101010104 +:1027C00002020202020101010100010100010101F6 +:1027D00002000000000000010000000100010100F3 +:1027E00002020101010101010101010101010200D7 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:10281000020202020202020202010101010202029C +:10282000020202020202020202000101010202028D +:10283000020202020202020202010101010202027C +:10284000020202020202020202010101010102026D +:10285000020202020202020202010101010102025D +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:10288000020202020202020202020101010202022B +:10289000020202020202010101010202010202021D +:1028A0000202020202020202020202020202020208 +:1028B0000202020202010101010101010101010103 +:1028C00002020202020101010100010100010101F5 +:1028D00002020000000000000000000100010000F2 +:1028E00002020101010101010101010101010200D6 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:10291000020202020202020202010102010202029A +:10292000020202020202020202000101010202028C +:10293000020202020202020202010102010202027A +:10294000020202020202020202010101010102026C +:10295000020202020202020202010101010102025C +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:10298000020202020202020202020101010202022A +:102990000202020202020202020202020202020217 +:1029A0000202020202020202020202020202020207 +:1029B0000202020202010101010101010101010102 +:1029C00002020202020101010101010101010101F2 +:1029D00002020000000000000000000100000000F2 +:1029E00002010101010101010101010101010100D7 +:1029F00002020202020202020202020202020202B7 +:102A000002020202020202020202020202020202A6 +:102A10000202020202020202020102020202020297 +:102A2000020202020202020202010101010202028A +:102A30000202020202020202020102020202020277 +:102A4000020202020202020202010101010202026A +:102A5000020202020202020202010101010102025B +:102A60000202020202020202020202020202020246 +:102A70000202020202020202020202020202020236 +:102A80000202020202020202020201010102020229 +:102A90000202020202020202020202020202020216 +:102AA0000202020202020202020202020202020206 +:102AB00002020202020102010101010101010201FF +:102AC00002020202020202010101010101010101EF +:102AD00002020200000000000000000000000000F0 +:102AE00001010101010101010101010101010100D7 +:102AF00002020202020202020202020202020202B6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020101010102020289 +:102B30000202020202020202020202020202020275 +:102B40000202020202020202020101010102020269 +:102B50000202020202020202020101010102020259 +:102B60000202020202020202020202020202020245 +:102B70000202020202020202020202020202020235 +:102B80000202020202020202020201020102020227 +:102B90000202020202020202020202020202020215 +:102BA0000202020202020202020202020202020205 +:102BB00002020202020202020101010101010202FB +:102BC00002020202020202020101010101010101ED +:102BD00002020202000000000000000000000000ED +:102BE00001010101010101010101010101010100D6 +:102BF00002020202020202020202020202020202B5 +:102C000002020202020202020202020202020202A4 +:102C10000202020202020202020202020202020294 +:102C20000202020202020202020101020102020287 +:102C30000202020202020202020202020202020274 +:102C40000202020202020202020101010102020268 +:102C50000202020202020202020101010102020258 +:102C60000202020202020202020202020202020244 +:102C70000202020202020202020202020202020234 +:102C80000202020202020202020202020202020224 +:102C90000202020202020202020202020202020214 +:102CA0000202020202020202020202020202020204 +:102CB00002020202020202020201020201020202F6 +:102CC00002020202020202020201010101010101EB +:102CD00002020202000000000000000000000000EC +:102CE00001010101010101010101010101010100D5 +:102CF00002020202020202020202020202020202B4 +:102D000002020202020202020202020202020202A3 +:102D10000202020202020202020202020202020293 +:102D20000202020202020202020101020202020285 +:102D30000202020202020202020202020202020273 +:102D40000202020202020202020101020102020266 +:102D50000202020202020202020101020102020256 +:102D60000202020202020202020202020202020243 +:102D70000202020202020202020202020202020233 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020202020202020213 +:102DA0000202020202020202020202020202020203 +:102DB00002020202020202020202020201020202F4 +:102DC00002020202020202020201010201010201E8 +:102DD00002020202000000000000000000000000EB +:102DE00001010101010101010000010101010100D6 +:102DF00002020202020202020202020202020202B3 +:102E000002020202020202020202020202020202A2 +:102E10000202020202020202020202020202020292 +:102E20000202020202020202020102020202020283 +:102E30000202020202020202020202020202020272 +:102E40000202020202020202020102020102020264 +:102E50000202020202020202020102020202020253 +:102E60000202020202020202020202020202020242 +:102E70000202020202020202020202020202020232 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202020202020212 +:102EA0000202020202020202020202020202020202 +:102EB00002020202020202020202020202020202F2 +:102EC00002020202020202020201020201020202E4 +:102ED00002020202020000000000000000000000E8 +:102EE00001010101010101010000000101010100D6 +:102EF00002020202020202020202020202020202B2 +:102F000002020202020202020202020202020202A1 +:102F10000202020202020202020202020202020291 +:102F20000202020202020202020202020202020281 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202020202020261 +:102F50000202020202020202020202020202020251 +:102F60000202020202020202020202020202020241 +:102F70000202020202020202020202020202020231 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020202020202020201 +:102FB00002020202020202020202020202020202F1 +:102FC00002020202020202020202020201020202E2 +:102FD00002020202020002000202020002000002DB +:102FE00001010100010000000000000001010100DA +:102FF00002020202020202020202020202020202B1 +:1030000002020202020202020202020202020202A0 +:103010000202020202020202020202020202020290 +:103020000202020202020202020202020202020280 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020202020260 +:103050000202020202020202020202020202020250 +:103060000202020202020202020202020202020240 +:103070000202020202020202020202020202020230 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020202020202020200 +:1030B00002020202020202020202020202020202F0 +:1030C00002020202020202020202020202020202E0 +:1030D00002020202020202000202020002000002D8 +:1030E00001010000000000000000000000000100DD +:1030F00002020202010101010101020202020202B6 +:10310000020202020202020202020202020202029F +:10311000020202020202020202020202020202028F +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:10315000020202020202020202020202020202024F +:10316000020202020202020202020202020202023F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A00002020202020202020202020202020202FF +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020002000202D3 +:1031E00001010000000000000000000000000100DC +:1031F00001010101010101010101010101010101BF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A00002020202020202020202020202020202FE +:1032B00002020202020202020202020202020202EE +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020002020202D0 +:1032E00001000000000000000000000000000000DD +:1032F00001010101010101010101010101010101BE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020202020202FD +:1033B00002020202020202020202020202020202ED +:1033C00002020202020202020202020202020202DD +:1033D00002020202020202020202020202020202CD +:1033E00000000000000000000000000000000000DD +:1033F00001010101010101010101010101010101BD +:1034000001020201010101010102020202020202A3 +:10341000020202020202020202020202020202028C +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002020202020202020202020202020202EC +:1034C00002020202020202020202020202020202DC +:1034D00002020202020202020202020202020202CC +:1034E00000000001000101010101000100000000D5 +:1034F00001010101010101010101010101010101BC +:1035000001010101010101010101010101010101AB +:10351000020202020202020202020202020202028B +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002020202020202020202020202020202EB +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00000000101010101010101010101010000CF +:1035F00001010101010101010101010101010101BB +:1036000001010101010101010101010101010101AA +:10361000020202020202020202020202020202028A +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00000000101010101010101010101010000CE +:1036F00001010101010101010101010101010101BA +:1037000001010101010101010101010101010101A9 +:103710000101010101010101010202020202020292 +:103720000101010101010101010202020202020282 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020202020202E9 +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00000010101010101010101010101010101CA +:1037F00001010101010101010101010101010101B9 +:1038000001010101010101010101010101010101A8 +:103810000101010101010101010101010101010198 +:103820000101010101010101010101010101010188 +:103830000101010101010101010202020202020271 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020202020238 +:10387000020202010101010101020202020202022E +:10388000020202010101010101010202020202021F +:103890000202020202020202020202020202020208 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020202020202020202E8 +:1038C00002020202020202020202020202020202D8 +:1038D00002020202020202020202020202020202C8 +:1038E00001010101010101010101010101010101C8 +:1038F00001010101010101010101010101010101B8 +:1039000001010101010101010101010101010101A7 +:103910000101010101010101010101010101010197 +:103920000101010101010101010101010101010187 +:103930000101010101010101010101010101010177 +:103940000101010101010101010202020202020260 +:103950000202020202020202020202020202020247 +:103960000202020202020202020202020202020237 +:103970000202020202020202020202020202020227 +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020202020202E7 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00001010101010101010101010101010101C7 +:1039F00001010101010101010101010101010101B7 +:103A000001010101010101010101010101010101A6 +:103A10000101010101010101010101010101010196 +:103A20000101010101010101010101010101010186 +:103A30000101010101010101010101010101010176 +:103A40000101010101010101010101010101010166 +:103A5000010101010101010101020202020202024F +:103A60000202020202020202020202020202020236 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000202020202020202020202020202020206 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020202020202020202E6 +:103AC00002020202020202020202020202020202D6 +:103AD00002020202020202020202020202020202C6 +:103AE00001010101010101010101010101010101C6 +:103AF00001010101010101010101010101010101B6 +:103B000001010101010101010101010101010101A5 +:103B10000101010101010101010101010101010195 +:103B20000101010101010101010101010101010185 +:103B30000101010101010101010101010101010175 +:103B40000101010101010101010101010101010165 +:103B50000101010101010101010101010101010155 +:103B60000101010101010101010101010101010145 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000202020202020202020202020202020205 +:103BA00002020202020202020202020202020202F5 +:103BB00002020202020202020202020202020202E5 +:103BC00002020202020202020202020202020202D5 +:103BD00002020202020202020202020202020202C5 +:103BE00001010101010101010101010101010101C5 +:103BF00001010101010101010101010101010101B5 +:103C000001010101010101010101010101010101A4 +:103C10000101010101010101010101010101010194 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C60000101010101010101010101010101010144 +:103C70000101010101010101010101010101010134 +:103C80000000000000000000000000000000000034 +:103C90000202020202020202020202020202020204 +:103CA00002020202020202020202020202020202F4 +:103CB00002020202020202020202020202020202E4 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00001010101010101010101010101010101C4 +:103CF00001010101010101010101010101010101B4 +:103D000001010101010101010101010101010101A3 +:103D10000101010101010101010101010101010193 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D80000101010101010101010101010101010123 +:103D90000101010101010101010101010101010113 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00001010101010101010101010101010101C3 +:103DF00001010101010101010101010101010101B3 +:103E000001010101010101010101010101010101A2 +:103E10000101010101010101010101010101010192 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010172 +:103E40000101010101010101010101010101010162 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000101010101010101010101010101010112 +:103EA0000101010101010101010101010101010102 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00001010101010101010101010101010101C2 +:103EF00001010101010101010101010101010101B2 +:103F000001010101010101010101010101010101A1 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010171 +:103F40000101010101010101010101010101010161 +:103F50000101010101010101010101010101010151 +:103F60000101010101010101010101010101010141 +:103F70000101010101010101010101010101010131 +:103F80000101010101010101010101010101010121 +:103F90000101010101010101010101010101010111 +:103FA0000101010101010101010101010101010101 +:103FB00001010101010101010101010101010101F1 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00001010101010101010101010101010101C1 +:103FF00001010101010101010101010101010101B1 +:1040000001010101010101010101010101010101A0 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:104030000101010101010101010101010101010170 +:104040000101010101010101010101010101010160 +:104050000101010101010101010101010101010150 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:104080000101010101010101010101010101010120 +:104090000101010101010101010101010101010110 +:1040A0000101010101010101010101010101010100 +:1040B00001010101010101010101010101010101F0 +:1040C00001010101010101010101010101010101E0 +:1040D00000000000000000000000000000000000E0 +:1040E00001010101010101010101010101010101C0 +:1040F00001010101010101010101010101010101B0 +:10410000010101010101010101010101010101019F +:10411000010101010101010101010101010101018F +:10412000010101010101010101010101010101017F +:10413000010101010101010101010101010101016F +:10414000010101010101010101010101010101015F +:10415000010101010101010101010101010101014F +:10416000010101010101010101010101010101013F +:10417000010101010101010101010101010101012F +:10418000010101010101010101010101010101011F +:10419000010101010101010101010101010101010F +:1041A00001010101010101010101010101010101FF +:1041B00001010101010101010101010101010101EF +:1041C00001010101010101010101010101010101DF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000020202020202020202020202020202026E +:10423000020202020202020202020202020202025E +:10424000020202020202020202020202020202024E +:10425000020202020202020202020202020202023E +:10426000020202020202020202020202020202022E +:10427000020202020202020202020202020202021E +:10428000020202020202020202020202020202020E +:1042900002020202020202020202020202020202FE +:1042A00002020202020202020202020202020202EE +:1042B00002020202020202020202020202020202DE +:1042C00002020202020202020202020202020202CE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E0003B00000000000000000000000000000092 +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000001010000008A +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:104490000000000000000000000000010101000019 +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:104520000000000000000000000000010100000089 +:10453000000000000000000000010000000000007A +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:104590000000000000000000000000010101000018 +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000001010000000000000000A8 +:104610000000000000000100000000000000000099 +:104620000000000000000000000000010101000186 +:104630000100000000000000010100000000000077 +:10464000000000000000000000000000000000006A +:104650000000000000000000000000000100000059 +:10466000000000000000000000000000000000004A +:104670000000000000000000000000000100000039 +:10468000000000000000000000000000000000002A +:104690000000000000000000000000010101000116 +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000001010000000000000000A7 +:104710000000000000000100000000000000000098 +:104720000000000000000000000000010101010184 +:104730000101000000000000010100000000000075 +:104740000000000000000000000001000100000067 +:104750000000000000000000000000000100000058 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000100000038 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000010101010114 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000010000C8 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000001010000000000000000A6 +:104810000000000000000101000001000000000095 +:104820000000000000000000000000010101010183 +:104830000101000000000000010101000000000073 +:104840000000000000000000000001000100000066 +:104850000000000000000000000000000100000057 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000010100000036 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000010101010113 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000010000C7 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000101010000000000000000A4 +:104910000000000000000101000001000000000094 +:104920000000000000000000000000010101010182 +:104930000101000000000000010101000000000072 +:104940000000000000000000000001010101000063 +:104950000000000000000000000000000100000056 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000010100000035 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000010101010112 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000010000000000E6 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000001010000C5 +:1049F00000000000000000000100010000000000B5 +:104A000000000000000101010000000000000000A3 +:104A10000000000000000101000001000100000092 +:104A20000000000000000000000000010101010181 +:104A30000101000000000000010101000000000071 +:104A40000000000000000000000001010101010061 +:104A50000000000000000000000000010100000153 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000010100000133 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000010101010111 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000010000000000E5 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000001010000C4 +:104AF00000000000000000000100010000000000B4 +:104B000000000000000101010000000000000100A1 +:104B1000000100000000010100010100010000008F +:104B20000000000000000000000000010101010180 +:104B30000101000000000000010101000000000070 +:104B4000000000000000000000000101010101015F +:104B50000000000000000101000000010100000150 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000010100010131 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000010101010110 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000010001000000E3 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000010001010000C2 +:104BF00000000000000000000100010001000000B2 +:104C0000000000000001010100000000000101019E +:104C1000010101010000010101010100010000008A +:104C2000000000000000000000000001010101017F +:104C3000010100000000010101010100000000006D +:104C4000000000000000010100000101010101015C +:104C5000000000000000010100000001010100014E +:104C60000000000000000000000000000000000044 +:104C7000000000000000000000000001010101012F +:104C80000000000000000100000000000000000023 +:104C9000000000000000000000000001010101010F +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000010001000000E2 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000010001020000C0 +:104CF00000000000000000000100010001000000B1 +:104D0000000000000001010100000000000101019D +:104D10000101010101010101010101000100000087 +:104D2000000000000000000000000001010101017E +:104D3000010100000000010101010100000000006C +:104D4000000000000000010100000101010101015B +:104D5000010000000000010100000001010101014B +:104D60000000000000000000000000000000000043 +:104D7000000000000000000000000001010101012E +:104D80000000000000000100000000000000000022 +:104D9000000000000000000000000001010101010E +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000010101000000E0 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000010101020000BE +:104DF00000000000000001000100010001000000AF +:104E0000000000000001010100000100000101019B +:104E10000101010101010101010101010100000184 +:104E2000000000000000010100000001010101017B +:104E30000101000000000101010101010100000069 +:104E4000000000000000010100000101010101015A +:104E50000100000000010101000000010101010149 +:104E60000000000000000101000000000000000040 +:104E7000000000000000000000000001010101012D +:104E8000010000000000010100000000000000001F +:104E9000000000000000000000000001010101010D +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000010101000000DF +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000010101020000BD +:104EF00000000000000001000101010001000000AD +:104F0000000000000001010100000100000101019A +:104F10000101010101010101010101010100010182 +:104F2000000000000000010100000001010101017A +:104F30000101000000000101010101010100000068 +:104F40000000000000010101000001010101010158 +:104F50000100000000010101000000010101010148 +:104F6000000000000000010100000000000000003F +:104F7000000000000000000000000001010101012C +:104F8000010000000001010100000000000000001D +:104F9000000000000000000000000001010101010C +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000010101000000DE +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000010102020000BB +:104FF00000000000000001000101010001000000AC +:105000000000000000010101010001000001010198 +:105010000101010101010101010101010101010180 +:105020000000000000000101000000010101010179 +:105030000101000000000101010101010101000066 +:105040000000000000010101000001010101010157 +:105050000100000000010101000000010101010147 +:10506000010000000000010100000000000000003D +:10507000000000000000000000000001010101012B +:10508000010000000001010100000000000000001C +:10509000000000000000000000000001010101010B +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000001010101000000DC +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000010202020100B8 +:1050F00000000000000001000101010001000000AB +:105100000000000000010101010001000001010197 +:10511000010101010101010101010101010101017F +:105120000000000000000101000000010101010178 +:105130000101000000010101010101010101010063 +:105140000000000000010101000001010101010156 +:105150000100000000010101000000010101010146 +:10516000010000000001010100000000000000003B +:10517000000000000000000000000001010101012A +:10518000010000000001010100000000000000001B +:10519000000000000000000000000001010101010A +:1051A00000000000000000000000000000000000FF +:1051B00000000000000001010000010000000000EC +:1051C00000000000000000000101010101010000D9 +:1051D00000000000000000000000000000000000CF +:1051E00000020000000000000100010202020200B3 +:1051F00000000000000001000101010101000000A9 +:105200000000000000010101010001000001010196 +:10521000010101010101010101010101010101017E +:105220000000000000000101000001010101010176 +:105230000101000000010101010101010101010161 +:105240000000000000010101000001010101010155 +:105250000100000000010101000000010101010145 +:10526000010000000001010100000000000000003A +:105270000000000000000000000000010101010129 +:10528000010000000001010100000000000000001A +:105290000000000000000000000000010101010109 +:1052A00000000000000000000000000000000000FE +:1052B00000000000000101010000010000000000EA +:1052C00000000000000000000101010101010000D8 +:1052D00000000000000000000000000000000000CE +:1052E00000020000000000010101020202020200AF +:1052F00000000000000001000201010101000000A7 +:105300000000000000010101010101000001010194 +:10531000010101010101010101010101010101017D +:105320000000000000010101000001010101010174 +:105330000101000000010101010101010101010160 +:105340000000000000010101000001010101010154 +:105350000100000000010101000000010101010144 +:105360000100000000010101000000000000000039 +:105370000000000000000000000000010101010128 +:105380000100000000010101000000000000000019 +:105390000000000000000000000000010101010108 +:1053A00000000000000000000000010000000000FC +:1053B00000000000000101010000010000000000E9 +:1053C00000000000000001000101010101010000D6 +:1053D00000000000000001000000000000000000CC +:1053E00000020000000000010101020202020200AE +:1053F00000000100000001000201010101000000A5 +:105400000000000000010101010101010101010191 +:10541000010101010101010101010101010101017C +:105420000100000000010101010001010101010171 +:10543000010100000001010102010101010101015E +:105440000100000000010101000001010101010152 +:105450000100000000010101000001010101010142 +:105460000100000000010101000000000000000038 +:105470000000000000000000000001010101010126 +:105480000100000000010101000000000000000018 +:105490000000000000000101000001010101010104 +:1054A00000000000000001010000010000000000F9 +:1054B00000000000000101010000010000000000E8 +:1054C00000000000000101000101010101010000D4 +:1054D00000000000000101000000010002000000C7 +:1054E00000010000000000010201020202020200AD +:1054F00000000200000001000201010101000000A3 +:10550000000000000101010101010101010101018F +:10551000010101010101010101010101010101017B +:10552000010000000001010101010101010101016F +:10553000010100000001010102020101010101015C +:105540000100000000010101010001010101010150 +:105550000100000000010101000001010101010141 +:105560000100000000010101000000000000000037 +:105570000000000000000000000001010101010125 +:105580000100000000010101000000000000000017 +:105590000000000000000101000001010101010103 +:1055A00000000000000001010100010000000000F7 +:1055B00000000000000101010000010001000000E6 +:1055C00000000000000101010101010101010000D2 +:1055D00000000000000101000000010001000000C7 +:1055E00000010000000000010202020202020202A9 +:1055F000020002020000010002010101010000009E +:10560000000000000101010101010101010101018E +:10561000010101010101010101010101010101017A +:10562000010000000001010101010102010101016D +:10563000010100000001010102020101010101015B +:10564000010000000001010101010101010101014E +:10565000010000000001010101000101010101013F +:105660000100000000010101000001000000000035 +:105670000000000000000000010001010101010123 +:105680000100000000010101000001000000000015 +:105690000000000000000101000001010101010102 +:1056A00000000000000001010101010000000000F5 +:1056B00000000000000101010000010001000000E5 +:1056C00000000000000101010101010101010100D0 +:1056D00000000000000101000000010001000000C6 +:1056E00000010200000000010202020202020202A6 +:1056F000020202020000010002010101010000009B +:10570000000000000101010102010101010101018C +:105710000101010101010101020101010101010178 +:10572000010000000001010101010102020101016B +:10573000010100000001010102020101010101015A +:10574000010000000001010101010101010101014D +:10575000010000000001010101010101010101013D +:105760000100000000010101000101000000000033 +:105770000000000000000000010101010101010121 +:105780000100000000010101000001000000000014 +:105790000000000000010101000001010101010100 +:1057A00000000000000101010101010101000000F1 +:1057B00000000000000101010100010101000000E2 +:1057C00000000000000101010101010101010101CE +:1057D00000000000000101010000010001000000C4 +:1057E00000010200000000010202020202020202A5 +:1057F0000202020200000100020202010100000098 +:10580000000000000101010102010101010101018B +:105810000101010101010101020201010101010176 +:105820000100000000010101010101020202010169 +:105830000101000000010101020201010101010159 +:10584000010000000001010101010101010101014C +:10585000010000000001010101010101010101013C +:105860000100000000010101000101000000000032 +:105870000000000000000000010101010101010120 +:105880000100000000010101010001000000000012 +:1058900000000000000101010100010101010101FE +:1058A00000000000000101010101010101000000F0 +:1058B00000000000000101010101010101000000E0 +:1058C00000000000000101010101010101010101CD +:1058D00000000000000101010000010101000000C2 +:1058E00000010100000001010202020202020202A4 +:1058F0000202020201000200020202010100000095 +:105900000000000001010101020101010102020188 +:105910000101010101010101020202010101010174 +:105920000100000000010101010101020202020266 +:105930000201000000010101020202010101010156 +:10594000010000000001010101010201010101014A +:10595000010001000001010101010101010101013A +:105960000100000000010101000101000000000031 +:10597000000000000000000001010101010101011F +:10598000010000000101010101010100000000000F +:1059900000000000000101010101010201010101FB +:1059A00000000000000101010101010101000000EF +:1059B00000000000000101010101010101000000DF +:1059C00000000000000101010101010101010101CC +:1059D00000000000000101010001010101000000C0 +:1059E00000010100000001010202020202020202A3 +:1059F0000202020202000201020202010200000091 +:105A00000200000001010101020202010102020282 +:105A10000202010101010101020202010101010171 +:105A20000100000000010101010101020202020265 +:105A30000202000000010101020202010101010154 +:105A40000100000000010101010102020201010147 +:105A50000100010001010101010101010201010137 +:105A60000100000000010101000101000000000030 +:105A7000000000000000010101010102020101011A +:105A8000010001000101010101010100000000000D +:105A900000000000000101010101010202020101F8 +:105AA00000000000000101010101010101000000EE +:105AB00000000000000101010101010101000000DE +:105AC00000000000000101010101010101010101CB +:105AD00000010000000101010001010101020002BA +:105AE00000010100000001010202020202020202A2 +:105AF0000202020202000201020202010200000090 +:105B0000020200000101020202020201010202027D +:105B1000020202020101020102020201020101016C +:105B20000100000001010101020101020202020262 +:105B30000202000000010101020202010101010153 +:105B40000100000001010101010102020202010144 +:105B50000100010001010101010101020201010135 +:105B6000010000000101010100010100000000002E +:105B70000000000000000101010101020201010119 +:105B8000010101000101010101010100000000000B +:105B900000000000000101010101010202020101F7 +:105BA00000000000000101010101010101000000ED +:105BB00000000100000101010101010101010000DB +:105BC00000000100000101010201020101010101C7 +:105BD00001010100000101010001010101010002B8 +:105BE00000010100000101010202020202020202A0 +:105BF000020202020200020102020202020100008D +:105C0000010101000102020202020201010202027C +:105C10000202020202010202020202020201010168 +:105C20000100010001010101020101020202020260 +:105C30000202000000010101020202020101010151 +:105C40000100010001010101010102020202020141 +:105C50000101010001010101010101020201010133 +:105C60000100010001010101000101010100000129 +:105C70000000000000000101010101020201010118 +:105C80000101010101010101010101000000000009 +:105C900000000000000101010101010202020202F4 +:105CA00000000000000101010101010101000000EC +:105CB00000010100010101010101010101010000D8 +:105CC00000010100010101010202020101010101C3 +:105CD00001010100000101010000000101010001BA +:105CE000000101000001010102020202020202029F +:105CF000020202020201020102020202020101008A +:105D0000010101000102020202020202010202027A +:105D10000202020202010202020202020201010167 +:105D2000010001000101010102020102020202025E +:105D3000020200000001010102020202020101014F +:105D4000010001000101010102010202020202023E +:105D5000010101010101010101010102020201022F +:105D60000100010001010101000101010100010127 +:105D70000000000000010101010101020202020213 +:105D80000101010101010101010101000000000008 +:105D900000000000000101010101010202020202F3 +:105DA00000000000000101010201010101010000E9 +:105DB00000010100010101010101010101010001D6 +:105DC00001010101010101010202020202010101BE +:105DD00001010100000101010000000101010201B7 +:105DE000000101000001010102020202020202029E +:105DF0000202020202010201020202020201010188 +:105E00000101010101020202020202020202020277 +:105E10000202020202020202020202020202020262 +:105E2000010001010101010102020202020202025B +:105E3000020200000001010102020202020201014D +:105E4000010001010101010102010202020202023C +:105E5000020101010101010102010102020202022B +:105E60000100010001010101000101010101010125 +:105E70000100000000010101020101020202020210 +:105E80000101010101010101020101010100000004 +:105E900000000000000101010101010202020202F2 +:105EA00000000000000101010201010101010100E7 +:105EB00000010100010101010101010101010101D4 +:105EC00001010101010101010202020202010101BD +:105ED00001010100010101010000000000010101B8 +:105EE000020101000001010002020202020202029C +:105EF0000202020202020201020202020201010186 +:105F00000101010101020202020202020202020276 +:105F10000202020202020202020202020202020261 +:105F20000101010101010101020202020202020259 +:105F3000020200000001010102020202020202014B +:105F40000101010101010101020202020202020239 +:105F5000020101010101010102010102020202022A +:105F60000101010001010101000101010101010123 +:105F7000010000000001010102010102020202020F +:105F80000201010101010101020101010100000002 +:105F900000000000000101010101010202020202F1 +:105FA00000000000000101010202010101010101E4 +:105FB00000010101010101010201010101010101D1 +:105FC00001010101010101010202020202010101BC +:105FD00001010101010101010000000000010101B6 +:105FE000010101000201010002020202020101029C +:105FF0000202010102020201020202020201010187 +:106000000101010101020202020202020202020275 +:106010000202020202020202020202020202020260 +:106020000101010101010101020202020202020258 +:106030000202000000010202020202020202020247 +:106040000101010101010101020202020202020238 +:106050000201010101010101020201020202020228 +:10606000020101010101010101020101010101011E +:10607000010000000001010102020102020202020D +:106080000201010101010101020201010100000000 +:1060900000000000000101010201010202020202EF +:1060A00002000100000101010202020101010101DF +:1060B00000010101010101010201020101010101CF +:1060C00001010101010101010202020202020101BA +:1060D00001010101010101010000000000010101B5 +:1060E000010001000101010002020202020101019E +:1060F0000101010102020201020202020201010188 +:106100000101010102020202020202020202020273 +:10611000020202020202020202020202020202025F +:106120000201010101010101020202020202020256 +:106130000202000000010202020202020202020246 +:106140000201010101010202020202020202020234 +:106150000201010101010202020202020202020224 +:10616000020101010101010101020101010101011D +:10617000010000000001010102020202020202020B +:1061800002010101010101010202020101000000FE +:1061900000000000000101010201010202020202EE +:1061A00001010100010101010202020101010101DD +:1061B00000010101010101010202020101010101CD +:1061C00001010101010101010202020202020101B9 +:1061D00001010101010101010100000000000101B4 +:1061E000010001000101010002020201010101019F +:1061F0000101010101020201020202020202010187 +:106200000101010102020202020202020202020272 +:10621000020202020202020202020202020202025E +:106220000201010101010202020202020202020253 +:106230000202000000020202020202020202020244 +:106240000201010101020202020202020202020232 +:106250000201010101020202020202020202020222 +:10626000020101010101010101020201010101011B +:10627000010000000001010102020202020202020A +:1062800002010101010102010202020101010000FB +:1062900002000000000101010202020202020202E9 +:1062A00001010101010101010202020201010101DA +:1062B00000010101010101010202020101010101CC +:1062C00001010101010101010202020202020101B8 +:1062D00001010101010101010100000000000101B3 +:1062E000010000020101010002020201010101019D +:1062F0000101010101020200020202020202020186 +:106300000101010102020202020202020202020271 +:10631000020202020202020202020202020202025D +:106320000201010101010202020202020202020252 +:106330000202000000020202020202020202020243 +:106340000201010101020202020202020202020231 +:106350000201010101020202020202020202020221 +:106360000201010101010202010202010101010118 +:106370000100000000010101020202020202020209 +:1063800002010101010202020202020101010000F8 +:1063900001000000000101010202020202020202E9 +:1063A00001010101010101010202020202010101D8 +:1063B00001010101010101010202020202010101C8 +:1063C00001010101010101010202020202020201B6 +:1063D00001010101010101010200000000000000B3 +:1063E000010000010101000002020201010101019E +:1063F0000101010101010200020202020202020285 +:10640000020202010202020202020202020202026D +:10641000020202020202020202020202020202025C +:106420000201010101020202020202020202020250 +:106430000202000000020202020202020202020242 +:106440000201010101020202020202020202020230 +:106450000201010101020202020202020202020220 +:106460000201010101020202020202010101010115 +:106470000100000000010101020202020202020208 +:1064800002010101010202020202020101010001F6 +:1064900001000100000101010202020202020202E7 +:1064A00001010101010101010202020202010101D7 +:1064B00001010101010202020202020202010101C4 +:1064C00001010101010101010202020202020202B4 +:1064D00001010101010101010200000000000000B2 +:1064E00000000001010000000202010101010101A0 +:1064F0000101010101010100020202020202020285 +:10650000020202020202020202020202020202026B +:10651000020202020202020202020202020202025B +:10652000020101010102020202020202020202024F +:106530000202000001020202020202020202020240 +:10654000020101010102020202020202020202022F +:10655000020101010102020202020202020202021F +:106560000201010101020202020202020101010113 +:106570000100000001010101020202020202020206 +:1065800002010101010202020202020201010101F3 +:1065900001010100010102020202020202020202E2 +:1065A00001010101010101010202020202010101D6 +:1065B00001010101010202020202020202010101C3 +:1065C00001010101010101010202020202020202B3 +:1065D00001010101010202010202020000000000AB +:1065E000000000010100000002020101010101019F +:1065F0000101010101010100020202020202020284 +:10660000020202020202020202020202020202026A +:10661000020202020202020202020202020202025A +:10662000020101010102020202020202020202024E +:10663000020201000102020202020202020202023E +:10664000020101010102020202020202020202022E +:10665000020102010102020202020202020202021D +:106660000201010101020202020202020201010111 +:106670000100010001010101020202020202020204 +:1066800002010101010202020202020202010101F1 +:1066900001010101010202020202020202020202DF +:1066A00001010101010101010202020202020101D4 +:1066B00001010101010202020202020202020101C1 +:1066C00001010101010202010202020202020202B0 +:1066D00002020101010202010202020000000000A8 +:1066E00000000001000000000201010101010101A0 +:1066F0000101010101010100020202020202020283 +:106700000202020202020202020202020202020269 +:106710000202020202020202020202020202020259 +:10672000020102010202020202020202020202024B +:10673000020201000102020202020202020202023D +:10674000020102010202020202020202020202022B +:10675000020202010202020202020202020202021A +:10676000020101010102020202020202020202020D +:106770000100010001010101020202020202020203 +:1067800002020201020202020202020202010101ED +:1067900001010101010202020202020202020202DE +:1067A00001010101010102020202020202020201D0 +:1067B00001020201010202020202020202020101BE +:1067C00001010101010202020202020202020202AE +:1067D00002020201010202020202020202000000A1 +:1067E00000000000000000000101010101010101A1 +:1067F0000101010101010100020202020202020282 +:106800000202020202020202020202020202020268 +:106810000202020202020202020202020202020258 +:106820000202020202020202020202020202020248 +:10683000020201000102020202020202020202023C +:106840000202020202020202020202020202020228 +:106850000202020202020202020202020202020218 +:10686000020102010202020202020202020202020A +:106870000200010101010101020202020202020200 +:1068800002020202020202020202020202020101EA +:1068900001010101010202020202020202020202DD +:1068A00001010101010202020202020202020202CD +:1068B00001020201020202020202020202020202BA +:1068C00002020201010202020202020202020202AA +:1068D00002020201010202020202020202000000A0 +:1068E00000000000000000000101010101010101A0 +:1068F0000101010101010100020202020202020281 +:106900000202020202020202020202020202020267 +:106910000202020202020202020202020202020257 +:106920000202020202020202020202020202020247 +:10693000020201000102020202020202020202023B +:106940000202020202020202020202020202020227 +:106950000202020202020202020202020202020217 +:106960000202020102020202020202020202020208 +:1069700002010101010101010202020202020202FE +:1069800002020202020202020202020202020101E9 +:1069900001010101010202020202020202020202DC +:1069A00001010101010202020202020202020202CC +:1069B00001020202020202020202020202020202B8 +:1069C00002020202020202020202020202020202A7 +:1069D000020202020202020202020202020000009D +:1069E000000200000000000001010101010101019D +:1069F0000101010101010100020202020202020280 +:106A00000202020202020202020202020202020266 +:106A10000202020202020202020202020202020256 +:106A20000202020202020202020202020202020246 +:106A3000020201000102020202020202020202023A +:106A40000202020202020202020202020202020226 +:106A50000202020202020202020202020202020216 +:106A60000202020202020202020202020202020206 +:106A700002010101010102020202020202020202FB +:106A800002020202020202020202020202020202E6 +:106A900002010101010202020202020202020202DA +:106AA00001010101010202020202020202020202CB +:106AB00002020202020202020202020202020202B6 +:106AC00002020202020202020202020202020202A6 +:106AD000020202020202020202020202020200009A +:106AE000000200000000000001010101010101019C +:106AF000010101010101010002020202020202027F +:106B00000202020202020202020202020202020265 +:106B10000202020202020202020202020202020255 +:106B20000202020202020202020202020202020245 +:106B30000202020002020202020202020202020237 +:106B40000202020202020202020202020202020225 +:106B50000202020202020202020202020202020215 +:106B60000202020202020202020202020202020205 +:106B700002010101010202020202020202020202F9 +:106B800002020202020202020202020202020202E5 +:106B900002020201010202020202020202020202D7 +:106BA00002020201010202020202020202020202C7 +:106BB00002020202020202020202020202020202B5 +:106BC00002020202020202020202020202020202A5 +:106BD0000202020202020202020202020202000099 +:106BE000000202000000000201010101010000009A +:106BF0000000000001010100020202020202020282 +:106C00000202020202020202020202020202020264 +:106C10000202020202020202020202020202020254 +:106C20000202020202020202020202020202020244 +:106C30000202020102020202020202020202020235 +:106C40000202020202020202020202020202020224 +:106C50000202020202020202020202020202020214 +:106C60000202020202020202020202020202020204 +:106C700002010101010202020202020202020202F8 +:106C800002020202020202020202020202020202E4 +:106C900002020202020202020202020202020202D4 +:106CA00002020202020202020202020202020202C4 +:106CB00002020202020202020202020202020202B4 +:106CC00002020202020202020202020202020202A4 +:106CD0000202020202020202020202020202020294 +:106CE0000002020000000202010101000000000099 +:106CF0000000000000010100020202020202020282 +:106D00000202020202020202020202020202020263 +:106D10000202020202020202020202020202020253 +:106D20000202020202020202020202020202020243 +:106D30000202020102020202020202020202020234 +:106D40000202020202020202020202020202020223 +:106D50000202020202020202020202020202020213 +:106D60000202020202020202020202020202020203 +:106D700002010101010202020202020202020202F7 +:106D800002020202020202020202020202020202E3 +:106D900002020202020202020202020202020202D3 +:106DA00002020202020202020202020202020202C3 +:106DB00002020202020202020202020202020202B3 +:106DC00002020202020202020202020202020202A3 +:106DD0000202020202020202020202020202020293 +:106DE0000202020000020202010100000000000095 +:106DF0000000000000000000010202020202020284 +:106E00000202020202020202020202020202020262 +:106E10000202020202020202020202020202020252 +:106E20000202020202020202020202020202020242 +:106E30000202020202020202020202020202020232 +:106E40000202020202020202020202020202020222 +:106E50000202020202020202020202020202020212 +:106E60000202020202020202020202020202020202 +:106E700002010201020202020202020202020202F4 +:106E800002020202020202020202020202020202E2 +:106E900002020202020202020202020202020202D2 +:106EA00002020202020202020202020202020202C2 +:106EB00002020202020202020202020202020202B2 +:106EC00002020202020202020202020202020202A2 +:106ED0000202020202020202020202020202020292 +:106EE0000202020000020202010000000000000095 +:106EF000000000000000000001010101010101018A +:106F00000101010101010101020202020202020269 +:106F10000202020202020202020202020202020251 +:106F20000202020202020202020202020202020241 +:106F30000202020202020202020202020202020231 +:106F40000202020202020202020202020202020221 +:106F50000202020202020202020202020202020211 +:106F60000202020202020202020202020202020201 +:106F700002020202020202020202020202020202F1 +:106F800002020202020202020202020202020202E1 +:106F900002020202020202020202020202020202D1 +:106FA00002020202020202020202020202020202C1 +:106FB00002020202020202020202020202020202B1 +:106FC00002020202020202020202020202020202A1 +:106FD0000202020202020202020202020202020291 +:106FE0000202020002020202000000000000000093 +:106FF0000000000000000000010101010101010189 +:10700000010101010101010102020202020000006E +:10701000000000000002020202020202020202025A +:107020000202020202020202020202020202020240 +:107030000202020202020202020202020202020230 +:107040000202020202020202020202020202020220 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E000020202020202020200000000000101018D +:1070F0000101010100000000010101010101010184 +:107100000101010101010101000000000001010174 +:10711000010101010100000002020202020202025A +:10712000020202020202020202020202020202023F +:10713000020202020202020202020202020202022F +:10714000020202020202020202020202020202021F +:10715000020202020202020202020202020202020F +:1071600002020202020202020202020202020202FF +:1071700002020202020202020202020202020202EF +:1071800002020202020202020202020202020202DF +:1071900002020202020202020202020202020202CF +:1071A00002020202020202020202020202020202BF +:1071B00002020202020202020202020202020202AF +:1071C000020202020202020202020202020202029F +:1071D000020202020202020202020202020202028F +:1071E000020202020202020200000001010101018A +:1071F0000101010101000000010101010101010182 +:10720000010101010101010101010101010101016E +:107210000101010101010101020202020202020256 +:10722000020202020202020202020202020202023E +:10723000020202020202020202020202020202022E +:10724000020202020202020202020202020202021E +:10725000020202020202020202020202020202020E +:1072600002020202020202020202020202020202FE +:1072700002020202020202020202020202020202EE +:1072800002020202020202020202020202020202DE +:1072900002020202020202020202020202020202CE +:1072A00002020202020202020202020202020202BE +:1072B00002020202020202020202020202020202AE +:1072C000020202020202020202020202020202029E +:1072D000020202020202020202020202020202028E +:1072E0000202020202020202000001010101010188 +:1072F000010101010101010001010101010101017F +:10730000010101010101010101010101010101016D +:107310000101010101010101000000000000000065 +:107320000002020202020202020202010101010144 +:107330000101020202020202020201010101010135 +:10734000010202020202020202020202020202021E +:10735000020202020202020202020202020202020D +:1073600002020202020202020202020202020202FD +:1073700002020202020202020202020202020202ED +:1073800002020202020202020202020202020202DD +:1073900002020202020202020202020202020202CD +:1073A00002020202020202020202020202020202BD +:1073B00002020202020202020202020202020202AD +:1073C000020202020202020202020202020202029D +:1073D000020202020202020202020202020202028D +:1073E0000202020202020202000101010101010186 +:1073F000010101010101010101010101010101017D +:10740000010101010101010101010101010101016C +:10741000010101010101010101010101010101015C +:107420000100000000000000010101010101010153 +:107430000101010101010101010102020202020236 +:107440000202020202020202020201010101010122 +:10745000010202020202020202020202020202020D +:1074600002020202020202020202020202020202FC +:1074700002020202020202020202020202020202EC +:1074800002020202020202020202020202020202DC +:1074900002020202020202020202020202020202CC +:1074A00002020202020202020202020202020202BC +:1074B00002020202020202020202020202020202AC +:1074C000020202020202020202020202020202029C +:1074D000020202020202020202020202020202028C +:1074E0000202020202020202010101010101010184 +:1074F000010101010101010101010101010101017C +:10750000010101010101010101010101010101016B +:10751000010101010101010101010101010101015B +:10752000010101010101010101010101010101014B +:10753000010101010101010101010101010101013B +:107540000101010101010101020202020202020223 +:107550000202020202020202020202010101010110 +:1075600001020202020202020202020202020202FC +:1075700002020202020202020202020101010101F0 +:1075800001020202020202020000000000000000EC +:1075900000000000000000000202020202020202DB +:1075A00002020202020202020202020202020202BB +:1075B00002020202020202020202020202020202AB +:1075C000020202020202020202020202020202029B +:1075D000020202020202020202020202020202028B +:1075E0000202020202020202010101010101010183 +:1075F000010101010101010101010101010101017B +:10760000010101010101010101010101010101016A +:10761000010101010101010101010101010101015A +:10762000010101010101010101010101010101014A +:10763000010101010101010101010101010101013A +:10764000010101010101010101010101010101012A +:107650000101010101010101020202020202020212 +:107660000202020202020202020101010101010101 +:1076700001020202020202020202020202020202EB +:1076800002020202020202020000000000000000EA +:1076900000000000000000000202020202020202DA +:1076A00002020202020202020000000000000000CA +:1076B00000000000000000000202020202020202BA +:1076C000020202020202020202020202020202029A +:1076D000020202020202020202020202020202028A +:1076E0000202020202020202010101010101010182 +:1076F000010101010101010101010101010101017A +:107700000101010101010101010101010101010169 +:107710000101010101010101010101010101010159 +:107720000101010101010101010101010101010149 +:107730000101010101010101010101010101010139 +:107740000101010101010101010101010101010129 +:107750000101010101010101010101010101010119 +:107760000101010101010101020202020202020201 +:1077700002020202020202020000000000000000F9 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000202020101010101DE +:1077A00002020202020202020000000000000000C9 +:1077B00000000000000000000202020202020202B9 +:1077C0000202020202020202020202020202020299 +:1077D0000202020202020202000000000000000099 +:1077E0000000000000000000010101010101010191 +:1077F0000101010101010101010101010101010179 +:107800000101010101010101010101010101010168 +:107810000101010101010101010101010101010158 +:107820000101010101010101010101010101010148 +:107830000101010101010101010101010101010138 +:107840000101010101010101010101010101010128 +:107850000101010101010101010101010101010118 +:107860000101010101010101010101010101010108 +:1078700001010101010101010101010101010101F8 +:1078800001010101010101010000000000000000F0 +:1078900000000000000000000202020202020202D8 +:1078A00002020202020202020000000000000000C8 +:1078B00000000000000000000202020202020202B8 +:1078C00002020202020202020000000000000000A8 +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000010101010101010190 +:1078F0000101010101010101010101010101010178 +:107900000101010101010101010101010101010167 +:107910000101010101010101010101010101010157 +:107920000101010101010101010101010101010147 +:107930000101010101010101010101010101010137 +:107940000101010101010101010101010101010127 +:107950000101010101010101010101010101010117 +:107960000101010101010101010101010101010107 +:1079700001010101010101010101010101010101F7 +:1079800001010101010101010101010101010101E7 +:1079900001010101010101010101010101010101D7 +:1079A00001010101010101010000000000000000CF +:1079B00000000000000000000202020202020202B7 +:1079C00002020202020202020000000000000000A7 +:1079D00000000000000000000000000000000000A7 +:1079E000000000000000000001010101010101018F +:1079F0000101010101010101010101010101010177 +:107A00000101010101010101010101010101010166 +:107A10000101010101010101010101010101010156 +:107A20000101010101010101010101010101010146 +:107A30000101010101010101010101010101010136 +:107A40000101010101010101010101010101010126 +:107A50000101010101010101010101010101010116 +:107A60000101010101010101010101010101010106 +:107A700001010101010101010101010101010101F6 +:107A800001010101010101010101010101010101E6 +:107A900001010101010101010101010101010101D6 +:107AA00001010101010101010101010101010101C6 +:107AB00001010101010101010101010101010101B6 +:107AC00001010101010101010000000000000000AE +:107AD00000000000000000000000000000000000A6 +:107AE000000000000000000001010101010101018E +:107AF0000101010101010101010101010101010176 +:107B00000101010101010101010101010101010165 +:107B10000101010101010101010101010101010155 +:107B20000101010101010101010101010101010145 +:107B30000101010101010101010101010101010135 +:107B40000101010101010101010101010101010125 +:107B50000101010101010101010101010101010115 +:107B60000101010101010101010101010101010105 +:107B700001010101010101010101010101010101F5 +:107B800001010101010101010101010101010101E5 +:107B900001010101010101010101010101010101D5 +:107BA00001010101010101010101010101010101C5 +:107BB00001010101010101010101010101010101B5 +:107BC00001010101010101010101010101010101A5 +:107BD000010101010101010100000000000000009D +:107BE000000000000000000001010101010101018D +:107BF0000101010101010101010101010101010175 +:107C00000101010101010101010101010101010164 +:107C10000101010101010101010101010101010154 +:107C20000101010101010101010101010101010144 +:107C30000101010101010101010101010101010134 +:107C40000101010101010101010101010101010124 +:107C50000101010101010101010101010101010114 +:107C60000101010101010101010101010101010104 +:107C700001010101010101010101010101010101F4 +:107C800001010101010101010101010101010101E4 +:107C900001010101010101010101010101010101D4 +:107CA00001010101010101010101010101010101C4 +:107CB00001010101010101010101010101010101B4 +:107CC00001010101010101010101010101010101A4 +:107CD000010101010101010100000000000000009C +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000020202020202020243 +:107D30000202020202020202020202020202020223 +:107D40000202020202020202020202020202020213 +:107D50000202020202020202020202020202020203 +:107D600002020202020202020202020202020202F3 +:107D700002020202020202020202020202020202E3 +:107D800002020202020202020202020202020202D3 +:107D900002020202020202020202020202020202C3 +:107DA00002020202020202020202020202020202B3 +:107DB00002020202020202020202020202020202A3 +:107DC0000202020202020202020202020202020293 +:107DD0000202020202020202000000000000000093 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000310000000000000061 +:107EF000000001010100000000000000000000007F +:107F00000000000000000000000000000000000071 +:107F10000100000000000000000000000000000060 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000140 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF000000001010101010100000000000000007B +:10800000010000000000000000000000000000006F +:10801000010000000000000000000000000000005F +:10802000000000000000000000000000000000014F +:10803000000000000000000000000000000000013F +:108040000000000000000000000000000000000030 +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:1080700000000000000000000000000000000001FF +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F000000001010101010100000000000000007A +:10810000010000000000000000000000000000006E +:10811000010000000000000000000000000000005E +:10812000000000000000000000000000000000014E +:10813000000000000000000000000000000000013E +:10814000000000000000000000000000000000002F +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000001FE +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F0000101010101010101000000000000000077 +:10820000010000000000000000000000000000006D +:10821000010000000000000000000000000000015C +:10822000000000000000000000000000000000014D +:10823000000000000000000000000000000000013D +:10824000000000000000000000000000000000012D +:10825000000000000000010000000000000000011C +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000001FD +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F0000101010101010101000000000000000076 +:10830000010000000000000000000000000000016B +:10831000010000000000000000000000000000015B +:10832000000000000000000000000000000001014B +:10833000000000000000000000000000000000013C +:10834000000000000000000000000000000000012C +:10835000000000000000010000000000000000011B +:10836000000000000000010000000000000000000C +:1083700000000000000000000000000000000101FB +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F0000101010101010101000000000000000075 +:10840000010000000000000000000000000000016A +:10841000010000000000000000000000000000015A +:10842000000000000000000000000000000001014A +:10843000000000000000000000000000000001013A +:10844000000000000000000000000000000000012B +:108450000000000000000100000100010000000118 +:108460000000000100000100000000000000000109 +:1084700000000000000000000000000000000101FA +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F0000101020201010101000000000000000072 +:108500000100000000000000000000000000000169 +:108510000100000000000000000000000000010158 +:108520000000000000000000000000000000010149 +:108530000000000000000000000000000000010139 +:108540000000000000000000000000000000010129 +:108550000000000000000100000100010000000117 +:108560000000000100000101000000000000000107 +:1085700000000000000001000000000000000101F8 +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E0000000000000000000000002000000000089 +:1085F000020102020202010100000000000000006E +:108600000100000000000000000000000000000168 +:108610000100000000000000000000000000010157 +:108620000000000000000000000000000001010147 +:108630000000000000000000000000000000010138 +:108640000000000000000000000000000000010128 +:108650000000000000000100000100010000000116 +:108660000000000100000101000000000000000106 +:1086700000000000000001000000000000010101F6 +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E0000000000000000200000002020000000084 +:1086F000020102020202010100000000000000006D +:108700000100000000000000000000000000000167 +:108710000100000000000000000000000000010156 +:108720000000000000000000000000000001010146 +:108730000000000000000000000000000001010136 +:108740000000000000000000000000000000010127 +:108750000000000000000100000100010000010114 +:108760000000010100000101000000000000010103 +:1087700000010000000001000000000000010101F4 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000001D8 +:1087A00000000000000000000000000000000001C8 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000200000002020000000083 +:1087F0000202020202020201010000010000000068 +:108800000201000000000000000000000000000164 +:108810000100000000000000000000000001010154 +:108820000000000000000000000000000001010145 +:108830000101000000000100000000000001010132 +:108840000000000000000000000000000001010125 +:108850000000000000000101010100010000010111 +:108860000000010100000101000000000000010102 +:1088700000010000000001000000000000010101F3 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000001D7 +:1088A00000010000000000000000000000000001C6 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000100000002020200000081 +:1088F0000202020202020202020001010000000064 +:108900000201000000000000000000000000000163 +:108910000101000000000000000000000001010152 +:108920000101000000000100000000000001010141 +:108930000101000000000100000000000001010131 +:108940000100000000000000000000000001010123 +:10895000010100000100010101010001000001010D +:108960000000010100010101000000000000010100 +:1089700001010000000001010000000100010101EF +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000001D6 +:1089A00000010000000000000000000000000001C5 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000100000201010200000080 +:1089F0000202020202020202020002020100000060 +:108A00000201000000010000000000000000010160 +:108A10000201000000000000000000000001010150 +:108A20000101000000000100000000000001010140 +:108A30000101000000000100000000000001010130 +:108A40000100000000000000000000000001010122 +:108A5000010100000101010101010001000001010B +:108A600000000101010101010100000100000101FC +:108A700001010101000001010001000100010101EB +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000101D4 +:108AA00000010000000000000000000000000101C3 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE000000000000000010000020101020000007F +:108AF000020202020202020202000202020000005E +:108B0000020100000101000000000000000001015E +:108B1000020100000000010000000000000101014E +:108B2000010100000000010000000001000101013E +:108B3000010101010000010000000000000101012D +:108B4000010100000000010000000000000101011F +:108B50000101010101010101010100010000010108 +:108B600001010101010101010101000100000101F8 +:108B700001010101000001010001000101010101E9 +:108B800000000000000000000000000000000001E4 +:108B900000000000000000000000000000000101D3 +:108BA00000010001000000000000000000000101C1 +:108BB00000000000000000000000000000000000B5 +:108BC00000010000000000000000000000000000A4 +:108BD0000000000000000000000000000000000095 +:108BE000000000000200010000010101010000017D +:108BF000020202020202020202000202020000005D +:108C0000020100000101010001000000000001015B +:108C1000020101000000010000000000000101014C +:108C2000010101010000010000000001000101013B +:108C3000010101010000010100000001000101012A +:108C4000010100000000010000000000000101011E +:108C50000101010101010101010100010001010106 +:108C600001010101010101010101000100010101F6 +:108C700001010101010001010001000101010101E7 +:108C800000000000000000000000000000000001E3 +:108C900000010000000000000000000000000101D1 +:108CA00001010001000001000000000000000101BE +:108CB00000000000000000000000000000000001B3 +:108CC00000010001000000000000000000000000A2 +:108CD0000000000000000000000000000000000094 +:108CE000000000000200010000010101010000017C +:108CF000020202020202020202020202020000005A +:108D00000201010001010100010100000000010158 +:108D1000020101000000010000000001000101014A +:108D20000101010100000101000000010101010138 +:108D30000101010101000101000100010001010127 +:108D4000010100000000010100000001000101011B +:108D50000101010101010101010101010001010104 +:108D600001010101010101010101010100010101F4 +:108D700001010101010101010101000101010101E4 +:108D800000000000000000000000000000000001E2 +:108D900000010100000000000000000000010101CE +:108DA00001010101000001000000000000010101BB +:108DB00000010000000000000000000000000001B1 +:108DC00001010001000000000000000000000000A0 +:108DD0000000000000000000000000000000000093 +:108DE000000000010100010000010101010000017B +:108DF0000202020202020202020202020200000059 +:108E00000201010001010101010100000000010156 +:108E10000201010100000100000100010001010147 +:108E20000101010100000101000100010101010136 +:108E30000101010101000101000100010101010125 +:108E40000101010100000101000000010001010118 +:108E50000101010101010101010101010101010102 +:108E600001010101010101010101010101010101F2 +:108E700001010101010101010101010101010101E2 +:108E800001010000000000000000000000000101DE +:108E900001010100000001000000000000010101CB +:108EA00001010101000001000000000000010101BA +:108EB00000010000000000000000000000000001B0 +:108EC000010101010000000000000000000000009E +:108ED0000000000100000000000000000000000091 +:108EE0000001000101000102000101010100000177 +:108EF0000202020202020202020202020200000058 +:108F00000202010101010101010101000000010152 +:108F10000201010100000101000100010101010144 +:108F20000101010100010101000100010101010134 +:108F30000101010101000101000100010101010124 +:108F40000101010100000101000000010101010116 +:108F50000101010101010101010101010101010101 +:108F600001010102010101010101010101010101F0 +:108F700001010101010101010101010101010101E1 +:108F800001010000000000000000000000000101DD +:108F900001010101000001000000000000010101C9 +:108FA00001010101000001000000000000010101B9 +:108FB00000010000000001000000000000000101AD +:108FC000010101010000000000000000000000009D +:108FD000000100010000000000000000000000008F +:108FE0000001010101000101000101010100000176 +:108FF0000202020202020202020202020200000057 +:10900000020201010202010101010101000001014E +:109010000201010100000101000100010101010143 +:109020000201010101010101000101010101010130 +:109030000201010101010101010100010101010120 +:109040000101010100000101000101010101010113 +:1090500002010101010102010102010101010101FD +:1090600001010202010102010101010101010101ED +:1090700001010101010101010101010101010101E0 +:1090800001010000000000000000000000000101DC +:1090900001010101000001010000000101010101C5 +:1090A00001010101000001010000000100010101B6 +:1090B00000010101000001000000000000010101A9 +:1090C000010101010000000000000000000000019B +:1090D000000101010000000000000000000000008D +:1090E0000001010101020101020101010100000171 +:1090F0000202020202020202020202020200000056 +:10910000020201010202010101010101000001014D +:109110000201010100010101000100010101010141 +:10912000020101010101010101010101010101012E +:10913000020101010101010101010001010101011F +:10914000020101010001010101010101010101010F +:1091500002010101010102010102010101010101FC +:1091600001010202010102020101010101010101EB +:1091700001010101010101010101010101010101DF +:1091800001010000000000000000000000010101DA +:1091900001010101000001010001000101010101C3 +:1091A00001010101010001010001000100010101B3 +:1091B00001010101000001000000000000010101A7 +:1091C0000101010100000100000000000000010198 +:1091D000010101010000000000000000000000008B +:1091E000000101010101010102010101010200016F +:1091F0000202020202020202020202020200000154 +:109200000202020102020101020101010100010248 +:10921000020201010101010100010001010101013E +:10922000020201010101010101010101010101012C +:10923000020201010101010101010001010101011D +:10924000020101010001010101010101010101010E +:1092500002020101020102010102010201010101F8 +:1092600002010202020202020101010101010101E7 +:1092700002010101010101010101010101010101DD +:1092800001010000000000000000000000010101D9 +:1092900001010101000101010001000101010101C1 +:1092A00001010101010101010001000100010101B1 +:1092B00001010101000001000001000000010101A5 +:1092C0000101010100000100000000000000010197 +:1092D000010101010000000000000000000000008A +:1092E0000000010101010101010101010101000171 +:1092F0000202020202020202020202020200000153 +:109300000202020102020101020201010101010245 +:10931000020201010101010100010001010101013D +:10932000020201010101010101010101010101022A +:10933000020201010101010101010101010101021A +:10934000020101010001010101010101010101010D +:1093500002020201020202020202010201010101F3 +:1093600002010202020202020101010101010101E6 +:1093700002020101010101010101010101010101DB +:1093800001010100000000000000000000010101D7 +:1093900001010101010101010001010101010101BE +:1093A00002020101010101010001000100010101AE +:1093B00001010101000001010001000100010101A2 +:1093C0000201010100000101000000000000010194 +:1093D0000101010100000100000000000000000088 +:1093E0000000000001010001010101010101000173 +:1093F0000202020202020202020202020200000152 +:109400000202020202020201020202010101010241 +:109410000202020101010101000101010101010239 +:109420000202020101010101010101010101020227 +:109430000202020101010101010101010101010218 +:10944000020201010101010101010101010101010A +:1094500002020202020202020202010201010102F0 +:1094600002020202020202020201010101010101E3 +:1094700002020101010101010101010101010101DA +:1094800002010100000000000000000000010101D5 +:1094900001010101010101010101010101010101BC +:1094A00002020101010101010101000101010101AB +:1094B00001010101010001010001000100010101A0 +:1094C0000202010101000101000100000000010190 +:1094D0000101010100000100000000000000000186 +:1094E0000000000000010001010101010101010172 +:1094F0000202020202020202010201010100000155 +:10950000020202020202020202020202010102023D +:109510000202020101010101000101010101020237 +:109520000202020201010201010101010102020223 +:109530000202020201010201010101010101020214 +:109540000202010101010101010101010101010208 +:1095500002020202020202020202010201010102EF +:1095600002020202020202020201010101010101E2 +:1095700002020201010102010101010101010102D6 +:1095800002010101000000000000000000010101D3 +:1095900002010101010101010101010101010101BA +:1095A00002020101010101010101010101010101A9 +:1095B000010101010101010101010001010101019C +:1095C000020201010101010100010000000001018E +:1095D0000101010100000101000000000000010183 +:1095E0000000000000010001010000000101010075 +:1095F0000202020202020202010101010100000155 +:10960000020202020202020202020202020102023B +:109610000202020201010201000101010102020233 +:109620000202020201010201010101010102020222 +:109630000202020202010201010101010102020211 +:109640000202020101010101010101010101020205 +:1096500002020202020202020202020201010202EC +:1096600002020202020202020202010201010102DE +:1096700002020202010102010101010101010202D3 +:1096800002020101000001010000000102010101CC +:1096900002020101010101010101010101010101B8 +:1096A00002020202010101010101010101010101A6 +:1096B000010101010101010101010101010101019A +:1096C000020202020101010100010000000101018A +:1096D0000101010101000101000100000000010180 +:1096E0000000000000000000010000000001010077 +:1096F0000202020102010202010101010102000154 +:10970000020202020202020202020202020102023A +:109710000202020201010201010101010102020231 +:10972000020202020202020201010102010202021D +:10973000020202020201020201010101010202020F +:109740000202020201010201010101010102020201 +:1097500002020202020202020202020202010202EA +:1097600002020202020202020202020201010202DB +:1097700002020202020102020101010101020202CF +:1097800002020101000001010001020101010101C9 +:1097900002020201010101010101010101010101B6 +:1097A00002020202010101010101010101010101A5 +:1097B0000202010101010101010101010101010197 +:1097C0000202020201010101000100010001010188 +:1097D000020101010101010100010000000001017D +:1097E0000100000000000000010000000001010075 +:1097F0000202010101010102010101010102000156 +:109800000202020202020202020202020201020239 +:10981000020202020202020201020102010202022B +:10982000020202020202020201020102020202021A +:10983000020202020202020201020102010202020B +:1098400002020202010102020101010101020202FF +:1098500002020202020202020200020202020202EA +:1098600002020200020202020202020202010202DB +:1098700002020202020202020102010201020202CB +:1098800002020101000101010001010101010101C8 +:1098900002020201010101010101010101010101B5 +:1098A00002020202010102010101010101010102A2 +:1098B0000202010101010101010101010101010196 +:1098C0000202020201010101000100010001010187 +:1098D000020201010101010100010000000101017A +:1098E0000100000000000000000000000001010075 +:1098F0000202010101010101010101010102000057 +:109900000202020202020202020202020202020237 +:109910000202020202020202010201020202020229 +:109920000202020202020202020202020202020217 +:109930000202020202020202020201020202020208 +:1099400002020202010202020101010201020202FC +:1099500002020202020202020200020202020202E9 +:1099600002020000020200000202020202020202DF +:1099700002020202020202020202010202020202C8 +:1099800002020201010101010001010101010101C5 +:1099900002020202010101010101010101010102B2 +:1099A000020202020201020101010101010102029F +:1099B0000202020101010101010101010101010194 +:1099C0000202020201010101010100010101010184 +:1099D0000202020201010101010100010101010174 +:1099E0000200000000000000000000000000010074 +:1099F0000101010101010101010101010101020057 +:109A00000202020202020202020202020202020236 +:109A10000202020202020202010201020202020228 +:109A20000202020202020202020202020202020216 +:109A30000202020202020202020201020202020207 +:109A400002020202020202020202020202020202F6 +:109A500002020202020200020200020202020202EA +:109A600002020000000000000202020202020202E2 +:109A700002020202020202020202020202020202C6 +:109A800002020201010101010101010101010102C2 +:109A900002020202010102010101010101010202AF +:109AA000020202020202020201010101010202029B +:109AB0000202020201010101010101010101010192 +:109AC0000202020202010201010101010101010180 +:109AD0000202020201010101010101010101010172 +:109AE0000200000000000000000000000000000074 +:109AF0000101010101010101010101010101010057 +:109B00000202020202020202020202020202020235 +:109B10000202020202020202010202020202020226 +:109B20000202020202020202020202020202020215 +:109B30000202020202020202020202020202020205 +:109B400002020202020202020202020202020202F5 +:109B500002020202000000000000020002020202F3 +:109B600002020000000000000002020202020202E3 +:109B700002020202020202020202020202020202C5 +:109B800002020202010101010101010101010202BF +:109B900002020202020202020101010101020202AA +:109BA0000202020202020202010201020102020298 +:109BB0000202020201010201010101010101010190 +:109BC000020202020202020201010101010101017D +:109BD0000202020201010101010101010101010171 +:109BE0000202000000000000000000000000000071 +:109BF0000101010101010101010101010101010056 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202020202020202020224 +:109C20000202020202020202020202020202020214 +:109C30000202020202020202020202020202020204 +:109C400002020202020202020202020202020202F4 +:109C500002020002000000000000020002020202F4 +:109C600002020000000000000002020202020202E2 +:109C700002020202020202020202020202020202C4 +:109C800002020202010101010101010101020202BD +:109C900002020202020202020102010202020202A6 +:109CA0000202020202020202020201020102020296 +:109CB000020202020201020101010101010101028D +:109CC0000202020202020202010201010101020279 +:109CD0000202020201010101010101010101010170 +:109CE000020202020000020000000000000000006A +:109CF0000101010101010101010101010101010055 +:109D0000020202020101020201010101010202023A +:109D10000202020202020202020202020202020223 +:109D20000202020202020202020202020202020213 +:109D30000202020202020202020202020202020203 +:109D400002020202020202020202020202020202F3 +:109D500002020200000002000000000000020202F5 +:109D600002020000000000000000020002020202E5 +:109D700002020202020202020202020202020202C3 +:109D800002020202020202020101010101020202B8 +:109D900002020202020202020202020202020202A3 +:109DA0000202020202020202020202020202020293 +:109DB0000202020202020202010201010102020287 +:109DC0000202020202020202010201010101020278 +:109DD000020202020201020101010101010101016D +:109DE0000202020202000200000000000000000067 +:109DF0000101010101010101010101010101010054 +:109E00000202020202020202020202020202020232 +:109E10000202020202020202020202020202020222 +:109E20000202020202020202020202020202020212 +:109E30000202020202020202020202020202020202 +:109E400002020202020202020202020202020202F2 +:109E500002020202020202020202000200020202E6 +:109E600002020202000000000000000000020202E4 +:109E700002020202020202020202020202020202C2 +:109E800002020202020202020102010201020202B5 +:109E900002020202020202020202020202020202A2 +:109EA0000202020202020202020202020202020292 +:109EB0000202020202020202020201020102020284 +:109EC0000202020202020202020201020102020274 +:109ED000020202020202020201010101010101016A +:109EE0000202020202000200000202020000000060 +:109EF0000101010101010101000100000001010057 +:109F0000020202020000020200000000000202023F +:109F10000202020202020202020202020202020221 +:109F20000202020202020202020202020202020211 +:109F30000202020202020202020202020202020201 +:109F400002020202020202020202020202020202F1 +:109F500002020202020202020202000200020202E5 +:109F600002020202000002020000000000020202DF +:109F700002020202020202020202020202020202C1 +:109F800002020202020202020202020202020202B1 +:109F900002020202020202020202020202020202A1 +:109FA0000202020202020202020202020202020291 +:109FB0000202020202020202020202020202020281 +:109FC0000202020202020202020202020202020271 +:109FD0000202020202020202010201010101010168 +:109FE0000202020202020202000202020200000059 +:109FF0000101010001000101000000000001010059 +:10A00000010202020000020200000000000202023F +:10A010000202020202020202020202020202020220 +:10A020000202020202020202020202020202020210 +:10A030000202020202020202020202020202020200 +:10A0400002020202020202020202020202020202F0 +:10A0500002020202020202020202020202020202E0 +:10A0600002020202020202020202000200020202D4 +:10A0700002020202020202020202020202020202C0 +:10A0800002020202020202020202020202020202B0 +:10A0900002020202020202020202020202020202A0 +:10A0A0000202020202020202020202020202020290 +:10A0B0000202020202020202020202020202020280 +:10A0C0000202020202020202020202020202020270 +:10A0D0000202020202020202020201010101020264 +:10A0E0000202020202020202000202020200000256 +:10A0F000010100000000000000000000000101005C +:10A100000201010100000101000000000001010145 +:10A11000020202020202020202020202020202021F +:10A12000020202020202020202020202020202020F +:10A1300002020202020202020202020202020202FF +:10A1400002020202020202020202020202020202EF +:10A1500002020202020202020202020202020202DF +:10A1600002020202020202020202020202020202CF +:10A1700002020202020202020202020202020202BF +:10A1800002020202020202020202020202020202AF +:10A19000020202020202020202020202020202029F +:10A1A000020202020202020202020202020202028F +:10A1B000020202020202020202020202020202027F +:10A1C000020202020202020202020202020202026F +:10A1D000020202020202020202020202020202025F +:10A1E0000202020202020202020202020200000253 +:10A1F000000000000000000000000000000000005F +:10A20000010202020000020200000000000202023D +:10A21000020202020202020202020202020202021E +:10A22000020202020202020202020202020202020E +:10A2300002020202020202020202020202020202FE +:10A2400002020202020202020202020202020202EE +:10A2500002020202020202020202020202020202DE +:10A2600002020202020202020202020202020202CE +:10A2700002020202020202020202020202020202BE +:10A2800002020202020202020202020202020202AE +:10A29000020202020202020202020202020202029E +:10A2A000020202020202020202020202020202028E +:10A2B000020202020202020202020202020202027E +:10A2C000020202020202020202020202020202026E +:10A2D000020202020202020202020202020202025E +:10A2E0000202020202020202020202020202000250 +:10A2F000000000000000000000000000000000005E +:10A30000010101010101010101010101010101013D +:10A31000020202020202020202020202020202021D +:10A32000020202020202020202020202020202020D +:10A3300002020202020202020202020202020202FD +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020202020202020202DD +:10A3600002020202020202020202020202020202CD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A39000020202020202020202020202020202029D +:10A3A000020202020202020202020202020202028D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202024D +:10A3F0000000000000000000010001010100000059 +:10A40000010101010101010101010101010101013C +:10A41000010202020202020202020202020202021D +:10A42000020202020202020202020202020202020C +:10A4300002020202020202020202020202020202FC +:10A4400002020202020202020202020202020202EC +:10A4500002020202020202020202020202020202DC +:10A4600002020202020202020202020202020202CC +:10A4700002020202020202020202020202020202BC +:10A4800002020202020202020202020202020202AC +:10A49000020202020202020202020202020202029C +:10A4A000020202020202020202020202020202028C +:10A4B000020202020202020202020202020202027C +:10A4C000020202020202020202020202020202026C +:10A4D000020202020202020202020202020202025C +:10A4E000020202020202020202020202020202024C +:10A4F0000000000100010000010101010100000055 +:10A50000010101010101010101010101010101013B +:10A51000010101010101010101010101010101012B +:10A52000010101010101010101010101010101011B +:10A5300002020202020202020202020202020202FB +:10A5400002020202020202020202020202020202EB +:10A5500002020202020202020202020202020202DB +:10A5600002020202020202020202020202020202CB +:10A5700002020202020202020202020202020202BB +:10A5800002020202020202020202020202020202AB +:10A59000020202020202020202020202020202029B +:10A5A000020202020202020202020202020202028B +:10A5B000020202020202020202020202020202027B +:10A5C000020202020202020202020202020202026B +:10A5D000020202020202020202020202020202025B +:10A5E000020202020202020202020202020202024B +:10A5F0000000010101010101010101010100000050 +:10A60000010101010101010101010101010101013A +:10A61000010101010101010101010101010101012A +:10A62000020202020202020202020202020202020A +:10A63000010101010101010101010101010101010A +:10A6400002020202020202020202020202020202EA +:10A6500001010101010101010101010101010101EA +:10A6600002020202020202020202020202020202CA +:10A6700002020202020202020202020202020202BA +:10A6800002020202020202020202020202020202AA +:10A69000020202020202020202020202020202029A +:10A6A000020202020202020202020202020202028A +:10A6B000020202020202020202020202020202027A +:10A6C000020202020202020202020202020202026A +:10A6D000020202020202020202020202020202025A +:10A6E000020202020202020202020202020202024A +:10A6F000010101010101010101010101010101014A +:10A700000101010101010101010101010101010139 +:10A710000101010101010101010101010101010129 +:10A720000101010101010101010101010101010119 +:10A730000101010101010101010101010101010109 +:10A7400001010101010101010101010101010101F9 +:10A7500002020202020202020202020202020202D9 +:10A7600001010101010101010101010101010101D9 +:10A7700002020202020202020202020202020202B9 +:10A7800002020202020202020202020202020202A9 +:10A790000202020202020202020202020202020299 +:10A7A0000202020202020202020202020202020289 +:10A7B0000202020202020202020202020202020279 +:10A7C0000101010101010101010101010101010179 +:10A7D0000202020202020202020202020202020259 +:10A7E0000202020202020202020202020202020249 +:10A7F0000101010101010101010101010101010149 +:10A800000101010101010101010101010101010138 +:10A810000101010101010101010101010101010128 +:10A820000101010101010101010101010101010118 +:10A830000101010101010101010101010101010108 +:10A8400001010101010101010101010101010101F8 +:10A8500001010101010101010101010101010101E8 +:10A8600002020202020202020202020202020202C8 +:10A8700002020202020202020202020202020202B8 +:10A8800001010101010101010101010101010101B8 +:10A890000202020202020202020202020202020298 +:10A8A0000101010101010101010101010101010198 +:10A8B0000202020202020202020202020202020278 +:10A8C0000202020202020202020202020202020268 +:10A8D0000202020202020202020202020202020258 +:10A8E0000202020202020202020202020202020248 +:10A8F0000101010101010101010101010101010148 +:10A900000101010101010101010101010101010137 +:10A910000101010101010101010101010101010127 +:10A920000101010101010101010101010101010117 +:10A930000101010101010101010101010101010107 +:10A9400001010101010101010101010101010101F7 +:10A9500001010101010101010101010101010101E7 +:10A9600001010101010101010101010101010101D7 +:10A9700001010101010101010101010101010101C7 +:10A9800002020202020202020202020202020202A7 +:10A990000202020202020202020202020202020297 +:10A9A0000202020202020202020202020202020287 +:10A9B0000202020202020202020202020202020277 +:10A9C0000000000000000000000000000000000087 +:10A9D0000202020202020202020202020202020257 +:10A9E0000202020202020202020202020202020247 +:10A9F0000101010101010101010101010101010147 +:10AA00000101010101010101010101010101010136 +:10AA10000101010101010101010101010101010126 +:10AA20000101010101010101010101010101010116 +:10AA30000101010101010101010101010101010106 +:10AA400001010101010101010101010101010101F6 +:10AA500001010101010101010101010101010101E6 +:10AA600001010101010101010101010101010101D6 +:10AA700001010101010101010101010101010101C6 +:10AA800001010101010101010101010101010101B6 +:10AA900001010101010101010101010101010101A6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000202020202020202020202020202020276 +:10AAC0000000000000000000000000000000000086 +:10AAD0000202020202020202020202020202020256 +:10AAE0000000000000000000000000000000000066 +:10AAF0000101010101010101010101010101010146 +:10AB00000101010101010101010101010101010135 +:10AB10000101010101010101010101010101010125 +:10AB20000101010101010101010101010101010115 +:10AB30000101010101010101010101010101010105 +:10AB400001010101010101010101010101010101F5 +:10AB500001010101010101010101010101010101E5 +:10AB600001010101010101010101010101010101D5 +:10AB700001010101010101010101010101010101C5 +:10AB800001010101010101010101010101010101B5 +:10AB900001010101010101010101010101010101A5 +:10ABA0000101010101010101010101010101010195 +:10ABB0000101010101010101010101010101010185 +:10ABC0000000000000000000000000000000000085 +:10ABD0000202020202020202020202020202020255 +:10ABE0000000000000000000000000000000000065 +:10ABF0000101010101010101010101010101010145 +:10AC00000101010101010101010101010101010134 +:10AC10000101010101010101010101010101010124 +:10AC20000101010101010101010101010101010114 +:10AC30000101010101010101010101010101010104 +:10AC400001010101010101010101010101010101F4 +:10AC500001010101010101010101010101010101E4 +:10AC600001010101010101010101010101010101D4 +:10AC700001010101010101010101010101010101C4 +:10AC800001010101010101010101010101010101B4 +:10AC900001010101010101010101010101010101A4 +:10ACA0000101010101010101010101010101010194 +:10ACB0000101010101010101010101010101010184 +:10ACC0000101010101010101010101010101010174 +:10ACD0000101010101010101010101010101010164 +:10ACE0000000000000000000000000000000000064 +:10ACF0000101010101010101010101010101010144 +:10AD00000101010101010101010101010101010133 +:10AD10000101010101010101010101010101010123 +:10AD20000101010101010101010101010101010113 +:10AD30000101010101010101010101010101010103 +:10AD400001010101010101010101010101010101F3 +:10AD500001010101010101010101010101010101E3 +:10AD600001010101010101010101010101010101D3 +:10AD700001010101010101010101010101010101C3 +:10AD800001010101010101010101010101010101B3 +:10AD900001010101010101010101010101010101A3 +:10ADA0000101010101010101010101010101010193 +:10ADB0000101010101010101010101010101010183 +:10ADC0000101010101010101010101010101010173 +:10ADD0000101010101010101010101010101010163 +:10ADE0000000000000000000000000000000000063 +:10ADF0000101010101010101010101010101010143 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE300002020202020202020202020202020202F2 +:10AE400002020202020202020202020202020202E2 +:10AE500002020202020202020202020202020202D2 +:10AE600002020202020202020202020202020202C2 +:10AE700002020202020202020202020202020202B2 +:10AE800002020202020202020202020202020202A2 +:10AE90000202020202020202020202020202020292 +:10AEA0000202020202020202020202020202020282 +:10AEB0000202020202020202020202020202020272 +:10AEC0000202020202020202020202020202020262 +:10AED0000202020202020202020202020202020252 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF000310000000000000000000000000100001F +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B0400000010100000000000000000000000000FE +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A000000000000000000000000000000000019F +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E000000000000000000000000000000001015E +:10B0F000000000000000000000010000000101014C +:10B10000010000000000000000000000000000003E +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000101000100010000000000000000010A +:10B1400000010100000000010000000000000000FC +:10B1500000010100010000000000000000000000EC +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000019E +:10B1B000000101010000000000000000000000008C +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000020001015B +:10B1F0000001010102000200010101010101010140 +:10B20000010101000000010000000000000000003A +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000011D +:10B230000001010001000101000000000000000108 +:10B2400000010101010101010000000000000001F6 +:10B2500000010100010000010000000000000000EA +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000100BD +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000019D +:10B2B0000101010100000000000001000000000089 +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000010001015B +:10B2F000010101010100020001010101010101013F +:10B300000101010000000100000000000000000039 +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000011C +:10B330000001010101010101000000000000000105 +:10B3400001010101010101010000000000000001F4 +:10B3500000010101010101010000000000000000E6 +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000010100BB +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000100000000019B +:10B3B0000101010101000100000101000000000085 +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000000000000000000006D +:10B3E0000000000000000000000001010101010157 +:10B3F000010101010100010002010101010101013E +:10B400000101010000000100000000000000000038 +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000011B +:10B430000101010101010101000000000000000103 +:10B4400001010101010101010000000000000001F3 +:10B4500001010101010101010000000000000000E4 +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000010100BA +:10B4900000000000000000000000000000000000AC +:10B4A0000001010000000000000001000000000198 +:10B4B0000101010101000100000101000000000084 +:10B4C000000000000000000000000000000000007C +:10B4D0000001010000000000000001000000000069 +:10B4E0000000000000000000000001010101010156 +:10B4F000010101010100010002010101010101013D +:10B500000101010000000100000000000000000037 +:10B510000001000000010000000000000000000029 +:10B52000000000000000000000000000000000011A +:10B530000101010101010101000000000000000102 +:10B5400001010101010101010000000000000001F2 +:10B5500001010101010101010000000000000000E3 +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000100010100B8 +:10B5900000000000000000000000000000000001AA +:10B5A0000101010000000000000001000000000196 +:10B5B0000101010101010100000101000000000082 +:10B5C000000000000000000000000000000000017A +:10B5D0000001010000000000000101000000000067 +:10B5E0000000000000000000000001010101010155 +:10B5F000010101010102010002010101010101013A +:10B600000101010000000100000100000000000134 +:10B610000001000000010000000000000000000028 +:10B620000000000000000000000000000000000119 +:10B630000101010101010101000000000000000101 +:10B6400001010101010101010000000000000001F1 +:10B6500001010101010101010000000000000000E2 +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000100010100B7 +:10B6900000000000000000000000000000000001A9 +:10B6A0000101010101000100000001000000000192 +:10B6B000010101010101010101010101000000007E +:10B6C0000000000000000000000000000000000179 +:10B6D0000001010001000000000101000000000065 +:10B6E0000000000000000000000001010101010154 +:10B6F000010101010101010002010101010101013A +:10B700000101010000000100000101000000000132 +:10B710000001010000010000000000000000000026 +:10B720000000000000000000000001000000000117 +:10B7300001010101010101010000000000000101FF +:10B7400001010101010101010000000000000001F0 +:10B7500001010101010101010000000000000000E1 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000100010100B6 +:10B7900000000000000000000000000000000001A8 +:10B7A0000101010101000100000001000000000191 +:10B7B000010101010101010101010101000000007D +:10B7C0000000000000000000000000000000000178 +:10B7D0000101010001000000000101000000010161 +:10B7E0000000000000000000000001010101010153 +:10B7F0000101010101010100020201010201010137 +:10B800000101010000000100000101000000000131 +:10B810000101010000010000000000000000000024 +:10B820000000000000000000000001000000010115 +:10B8300001010101010101010000010000000101FD +:10B8400001010101010101010000000000000001EF +:10B8500001010101010101010000000000000000E0 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000100010100B5 +:10B8900000000000000000000000010000000001A6 +:10B8A000010101010101010000010100000001018D +:10B8B000010101010101010101010101000000007C +:10B8C0000000000000000000000000000000000177 +:10B8D000010101010100010001010100000001015D +:10B8E0000001000000000000000001010101010151 +:10B8F0000101010101010100020201010201020135 +:10B90000010101000000010001010100000000012F +:10B910000101010101010000000000000000000120 +:10B920000000000000000000000001000001010113 +:10B9300001010101010101010001010000000101FB +:10B9400001010101010101010000010000000001ED +:10B9500001010101010101010000000000000000DF +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000100010100B4 +:10B9900000000000000000000000010000000001A5 +:10B9A000010101010101010100010100000001018B +:10B9B000010101010101010101010101000000007B +:10B9C0000000000000000000000000000000010175 +:10B9D000010101010100010001010100000001015C +:10B9E0000001000000000000000001010101010150 +:10B9F0000101010101010100020201020202020132 +:10BA0000010101010000020001010100000000012C +:10BA1000010101010101000000000000000000011F +:10BA20000001000000000000000101000001010110 +:10BA300001010101010101010001010000010101F9 +:10BA400001010101010101010001010000000101EA +:10BA500001010101010101010000000000000000DE +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000100010100B3 +:10BA900000010100000000000000010000010001A1 +:10BAA000010101010101010100010100000001018A +:10BAB000010101010101010101010101000000007A +:10BAC0000000000000000000000001000000010173 +:10BAD0000101010101010100010101010000010159 +:10BAE000000100000101000000010101010101014C +:10BAF000010101010101010102020202020202012F +:10BB0000010101010000020001010100000000012B +:10BB1000010101010101010000010000000000011C +:10BB2000000100000000000000010100000101010F +:10BB300001010101010101010001010000010101F8 +:10BB400001010101010101010001010000010101E8 +:10BB500001010101010101010000000000000000DD +:10BB600000010100000000000000000000000000D3 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000100010101B1 +:10BB9000000101000000000000010100000101019E +:10BBA0000101010101010101000101010001010187 +:10BBB0000101010101010101010101010100000078 +:10BBC0000000000000000000000001000000010172 +:10BBD0000101010101010100010101010000010158 +:10BBE000010100000101000000010101010101014A +:10BBF000010101010101010102020202020202022D +:10BC0000010101010000020001010100000000012A +:10BC1000010101010101010100010000000000011A +:10BC2000000101010100000000010100000101010B +:10BC300001010101010101010001010100010101F6 +:10BC400001010101010101010001010000010101E7 +:10BC500001010101010101010000000000000001DB +:10BC600000010100000000010001000000000000D0 +:10BC700000000000000000000000000000000000C4 +:10BC800000010100000000000000000100010101AE +:10BC9000000101000000000000010100000101019D +:10BCA0000101010101010101000101010001010186 +:10BCB0000101010101010101010101010100000077 +:10BCC000000000000000000000000101000101016F +:10BCD0000101010101010100010101010001010156 +:10BCE0000101000001010000000101010101010149 +:10BCF000010101010101010102020202020202022C +:10BD00000201020100000200020101000000000126 +:10BD10000101010101010101000100000000000119 +:10BD20000101010101000001000101010001010107 +:10BD300001010101010101010001010100010101F5 +:10BD400001010101010101010101010000010101E5 +:10BD500001010101010101010000000000000001DA +:10BD600000010101010000010001010000000000CC +:10BD700000010100000000000000010000000001BF +:10BD800000010100000000010000000101010101AB +:10BD90000101010000000001000101010001010199 +:10BDA0000101010101010101010101010001010184 +:10BDB0000101010101010101010101010100000076 +:10BDC000000000000000000000010101000101016D +:10BDD0000101010101010101010101010001010154 +:10BDE0000101000001010000000101010101010148 +:10BDF000010101010101010102020202020202022B +:10BE00000202020101000200020101000000000123 +:10BE10000101010101010101010100000000000117 +:10BE20000101010101010101000101010001010104 +:10BE300001010101010101010101010100010101F3 +:10BE400001010101010101010101010000010101E4 +:10BE500001010101010101010000000000000001D9 +:10BE600001010101010000010001010000000001C9 +:10BE700000010100000000010000010000000001BD +:10BE800000010100000000010000010101010101A9 +:10BE90000101010100000001010101010001010196 +:10BEA0000101010101010101010101010101010182 +:10BEB0000101010101010101020101010100000074 +:10BEC000000000000000000000010101000101016C +:10BED0000101010101010101010101010001010153 +:10BEE0000101010101010000000101010101010145 +:10BEF000010101010101010102020202020202022A +:10BF00000202020101000200020201000000000121 +:10BF10000101010101010101010100000000000116 +:10BF20000101010101010101010101010101010101 +:10BF300001010101010101010101010100010101F2 +:10BF400001010101010101010101010100010101E2 +:10BF500001010101010101010000000000000001D8 +:10BF600001010101010101010101010100000001C4 +:10BF700000010101000000010001010000000001BA +:10BF800001010100000000010001010101010101A6 +:10BF90000101010100000001010101010001010195 +:10BFA0000101010101010101010101010101010181 +:10BFB0000101010101010101020201010100000072 +:10BFC000000000000000000000010101000101016B +:10BFD0000101010101010101010101010001010152 +:10BFE0000101010101010000000100000001000148 +:10BFF0000101010101010101020202020202020229 +:10C00000020202010100020102020100000000011F +:10C010000101010101010101010101000000010113 +:10C020000101010101010101010101010101010100 +:10C0300001010101010101010101010101010101F0 +:10C0400001010101010101010101010100010101E1 +:10C0500001010101010101010001000000000001D6 +:10C0600001010101010101010101010100000001C3 +:10C0700001010101000000010001010100000001B7 +:10C0800001010101010001010101010101010101A1 +:10C090000101010100000001010101010001010194 +:10C0A0000101010101010101010101010101010180 +:10C0B000010101010101010102020201010100006F +:10C0C0000000000000000000010101010001010169 +:10C0D0000101010101010101010101010101010150 +:10C0E0000101010101010000000100000000000049 +:10C0F0000101010101010101020202020202020228 +:10C10000020202020100020102020200000000011C +:10C110000101010101010101020101000000010111 +:10C1200001010101010101010101010101010101FF +:10C1300001010101010101010101010101010101EF +:10C1400001010101010101010101010100010101E0 +:10C1500001010101010101010101010000000001D3 +:10C1600001010101010101010201010100010101BF +:10C1700001010101010000010001010100000001B5 +:10C1800001010101010001010101010101010101A0 +:10C190000101010100000001010101010001010193 +:10C1A000010101010101010101010101010101017F +:10C1B000010101010101010102020201020100006D +:10C1C0000000000000010100010101010001010166 +:10C1D000010101010101010102010101010101014E +:10C1E0000101010101010001000000000000000048 +:10C1F000000000000101010102020202020202022B +:10C200000202020202000201020202000000010119 +:10C21000010101010101010102020100000001010F +:10C2200001010101010101010101010101010101FE +:10C2300001010101010101010101010101010101EE +:10C2400001010101010101010201010100010101DE +:10C2500001010101010101010101010100000001D1 +:10C2600001010101010101010202010101010101BC +:10C2700001010101010000010101010100000101B2 +:10C28000010101010101010101010102010202019B +:10C290000101010101000001020101010001010190 +:10C2A000010101010101010101010201010101017D +:10C2B000010101010101010102020202020100016A +:10C2C0000000000000010100010101010101010164 +:10C2D000010101010101010102020101010101014C +:10C2E0000101010101010101000000000000000046 +:10C2F000000000000001010102020202020202022B +:10C300000202020202000201020202000000010217 +:10C31000010201010102010102020101000101010A +:10C3200001010101010101010202020101010102F9 +:10C3300001020201020102010202010101010102E6 +:10C3400001020201010101010202010100010102D9 +:10C3500001020201020101010101010100000001CD +:10C3600001010101010101010202010201010101BA +:10C3700001010101010000010101010100010101B0 +:10C38000010101010101010101010102010202019A +:10C39000010101010100000102020201000101018D +:10C3A0000101010101010101020202010101010279 +:10C3B0000101010101010101020202020201000169 +:10C3C0000001000000010100010101010101010162 +:10C3D000010101010101010102020201010101014A +:10C3E0000101010101010101000000000000000045 +:10C3F000000000000001000102020202020202022B +:10C400000202020202000201020202000000010216 +:10C410000202020101020101020201010001010107 +:10C4200001010101010101010202020101010102F8 +:10C4300002020202020202020202020101010102E0 +:10C4400002020202020202020202020100010102D1 +:10C4500002020202020202020201010100000001C6 +:10C4600001010101010101010202020202010101B7 +:10C4700001010101010000010101010101010101AE +:10C480000101010101010101020101020102020198 +:10C490000101010101010101020202010101010288 +:10C4A0000202020101010101020202010101010275 +:10C4B0000202020201010101020202020201000164 +:10C4C0000001000000010100020101010101010160 +:10C4D0000101010101010101020202010101010149 +:10C4E0000101010101010101000000000000000044 +:10C4F000000000000000000102020202020202022B +:10C500000202020202000201020202010001010213 +:10C510000202020202020101020201010001010203 +:10C5200001010101010101010202020101020202F5 +:10C5300002020202020202020202020101010202DE +:10C5400002020202020202020202020101010102CF +:10C5500002020202020202020201010100010001C4 +:10C5600001010101010101010202020202020101B5 +:10C5700001010101010100010201010101010101AB +:10C580000101010101010101020101020102020197 +:10C590000101010101010101020202020102010285 +:10C5A0000202020202010201020202010101010271 +:10C5B0000202020202010201020202020201000161 +:10C5C000000101000001010002020201010101025B +:10C5D0000102020101010101020202010101010146 +:10C5E0000101010101010101000000000000000043 +:10C5F000000000000000000102020202020202022A +:10C600000202020202010101020202010001010212 +:10C6100002020202020202010202020200010202FE +:10C6200001020101010101010202020201020202F2 +:10C6300002020202020202020202020201020202DB +:10C6400002020202020202020202020101020202CC +:10C6500002020202020202020202010101010101C0 +:10C6600001010101010101010202020202020201B3 +:10C6700001010101010101010202020101010101A7 +:10C680000101010101010101020201020202020194 +:10C690000101010101010101020202020102020283 +:10C6A000020202020202020102020202010102026D +:10C6B000020202020202020102020202020100015F +:10C6C0000101010000010100020202020101020257 +:10C6D0000202020102010101020202020101020141 +:10C6E0000101010101010101000000000000000042 +:10C6F000000000000000000001020202010201022D +:10C700000202020202010100020202010001010212 +:10C7100002020202020202020202020201020202FA +:10C7200002020202020101010202020202020202EC +:10C7300002020202020202020202020201020202DA +:10C7400002020202020202020202020201020202CA +:10C7500002020202020202020202010101010101BF +:10C7600001010101010101010202020202020202B1 +:10C7700001020201010101010202020201010101A3 +:10C780000101010101010101020202020202020192 +:10C790000101010101010101020202020102020282 +:10C7A0000202020202020202020202020202020269 +:10C7B000020202020202020202020202020100015D +:10C7C0000101010100010100020202020102020254 +:10C7D000020202020201020102020202010102023D +:10C7E0000101010101010101000000000000000041 +:10C7F000000000000000000001020202010201022C +:10C800000202020201010100020202020001020210 +:10C8100002020202020202020202020202020202F8 +:10C8200002020202020202020202020202020202E8 +:10C8300002020202020202020202020202020202D8 +:10C8400002020202020202020202020201020202C9 +:10C8500002020202020202020202020201010102BB +:10C8600001020201010101010202020202020202AE +:10C87000020202020201010202020202010101019E +:10C880000101010101010101020202020202020290 +:10C89000010202010101010102020202020202027E +:10C8A0000202020202020202020202020202020268 +:10C8B000020202020202020202020202020200015B +:10C8C0000101010100010101020202020102020252 +:10C8D000020202020202020102020202010202023A +:10C8E0000102010101010101010002020200020036 +:10C8F000000000000000000001010201010101012F +:10C90000020201010101010002020202010202020F +:10C9100002020202020202020202020202020202F7 +:10C9200002020202020202020202020202020202E7 +:10C9300002020202020202020202020202020202D7 +:10C9400002020202020202020202020201020202C8 +:10C9500002020202020202020202020201010102BA +:10C9600002020202020101020202020000020202AD +:10C97000020202020201010202020202020101029B +:10C98000010202010101010102020202020202028D +:10C99000020202010101010102020202020202027C +:10C9A0000202020202020202020202020202020267 +:10C9B000020202020202020202020202020200015A +:10C9C000010101010102020102020202020202024D +:10C9D0000202020202020201020202020202020238 +:10C9E000020201010202010101000202020202022E +:10C9F000000000000000000001010101010101012F +:10CA0000010101010102010002020202020202020E +:10CA100002020202020202020202020202020202F6 +:10CA200002020202020202020202020202020202E6 +:10CA300002020202020202020202020202020202D6 +:10CA400002020202020202020202020202020202C6 +:10CA500002020202020202020202020202010102B8 +:10CA600002020202020202020202020000000202AC +:10CA70000202020202020102020202020202020297 +:10CA8000020202010101010202020202020202028A +:10CA90000202020201010102020202020202020279 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020202010257 +:10CAC000010101010102020102020202020202024C +:10CAD0000202020202020202020202020202020236 +:10CAE000020201010202010102020202020202022A +:10CAF0000202020200000000010101010101010126 +:10CB0000010101010102010002020202020202020D +:10CB100002020202020202020202020002020002F9 +:10CB200002020202020202020202020202020202E5 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500002020202020202020202020202020102B6 +:10CB600002020202020202020202020000000002AD +:10CB70000202020202020202020202020202020295 +:10CB80000202020202010202020202020202020286 +:10CB90000202020201010102020202020202020278 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202010256 +:10CBC000010201010102020102020202020202024A +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020101020202020202020227 +:10CBF0000202020202000000010101010101010123 +:10CC0000010101010101010002020202020202020D +:10CC100002020202020202020202020000000002FC +:10CC200002020202020202020202020202020202E4 +:10CC300002020202020202020202020202020202D4 +:10CC400002020202020202020202020202020202C4 +:10CC500002020202020202020202020202020202B4 +:10CC600002020202020202020202020202000002A8 +:10CC70000202020202020202020202020202020294 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202010102020202020202020276 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202010255 +:10CCC0000202020101020201020202020202020247 +:10CCD0000202020202020202020202020202020234 +:10CCE0000202020202020101020202020202020226 +:10CCF0000202020202000200010101010101010120 +:10CD0000010101010101010002020202020202020C +:10CD100002020202020202020202020000000002FB +:10CD200002020202020202020202020202020202E3 +:10CD300002020202020202020202020202020202D3 +:10CD400002020202020202020202020202020202C3 +:10CD500002020202020202020202020202020202B3 +:10CD600002020202020202020202020202020002A5 +:10CD70000202020202020202020202020202020293 +:10CD80000202020202020202020202020202020283 +:10CD90000202020202020202020202020202020273 +:10CDA0000202020202020202020202020202020263 +:10CDB0000202020202020202020202020202020253 +:10CDC0000202020201020201020202020202020245 +:10CDD0000202020202020202020202020202020233 +:10CDE0000202020202020202020202020202020223 +:10CDF000020202020202020001010101010101011D +:10CE0000010101010101010002020202020202020B +:10CE100002020202020202020202020200000202F6 +:10CE200002020202020202020202020202020202E2 +:10CE300002020202020202020202020202020202D2 +:10CE400002020202020202020202020202020202C2 +:10CE500002020202020202020202020202020202B2 +:10CE600002020202020202020202020202020202A2 +:10CE70000202020202020202020202020202020292 +:10CE80000202020202020202020202020202020282 +:10CE90000202020202020202020202020202020272 +:10CEA0000202020202020202020202020202020262 +:10CEB0000202020202020202020202020102020253 +:10CEC0000202020202020202020202020202020242 +:10CED0000202020202020202020202020202020232 +:10CEE0000202020202020202020202020202020222 +:10CEF000020202020202020000010101000100011F +:10CF0000010101010101000002020202020202020B +:10CF100002020202020202020202020202020202F1 +:10CF200002020202020202020202020202020202E1 +:10CF300002020202020202020202020202020202D1 +:10CF400002020202020202020202020202020202C1 +:10CF500002020202020202020202020202020202B1 +:10CF600002020202020202020202020202020202A1 +:10CF70000202020202020202020202020202020291 +:10CF80000202020202020202020202020202020281 +:10CF90000202020202020202020202020202020271 +:10CFA0000202020202020202020202020202020261 +:10CFB0000202020202020202020202020102020252 +:10CFC0000202020202020202020202020202020241 +:10CFD0000202020202020202020202020202020231 +:10CFE0000202020202020202020202020202020221 +:10CFF0000202020202020202000001000000000020 +:10D00000010100000001000002020202020202020D +:10D0100002020202020202020202020202020202F0 +:10D0200002020202020202020202020202020202E0 +:10D0300002020202020202020202020202020202D0 +:10D0400002020202020202020202020202020202C0 +:10D0500002020202020202020202020202020202B0 +:10D0600002020202020202020202020202020202A0 +:10D070000202020202020202020202020202020290 +:10D080000202020202020202020202020202020280 +:10D090000202020202020202020202020202020270 +:10D0A0000202020202020202020202020202020260 +:10D0B0000202020202020202020202020202020250 +:10D0C0000202020202020202020202020202020240 +:10D0D0000202020202020202020202020202020230 +:10D0E0000202020202020202020202020202020220 +:10D0F0000202020202020202000000000000000020 +:10D100000000000000010000000202020202020210 +:10D1100002020202020202020202020202020202EF +:10D1200002020202020202020202020202020202DF +:10D1300002020202020202020202020202020202CF +:10D1400002020202020202020202020202020202BF +:10D1500002020202020202020202020202020202AF +:10D1600002020202020202020202020201020202A0 +:10D170000202020201010202020202020202020291 +:10D18000020202020202020202020202020202027F +:10D19000020202020202020202020202020202026F +:10D1A000020202020202020202020202020202025F +:10D1B000020202020202020202020202020202024F +:10D1C000020202020202020202020202020202023F +:10D1D000020202020202020202020202020202022F +:10D1E000020202020202020202020202020202021F +:10D1F000020202020202020200000000000000001F +:10D20000000000000000000001000000000000001D +:10D2100000000000000000000202020202020202FE +:10D2200002020202020202020202020202020202DE +:10D2300002020202020202020202020202020202CE +:10D2400002020202020202020202020202020202BE +:10D2500002020202020202020202020202020202AE +:10D2600002020202020202020202020102010202A0 +:10D27000020202020202010202020202020202028F +:10D28000020202020202020202020202020202027E +:10D29000020202020202020202020202020202026E +:10D2A000020202020202020202020202020202025E +:10D2B0000202020202020202020202020002020250 +:10D2C0000202020202010102020202020202020240 +:10D2D000020202020202020202020202020202022E +:10D2E000020202020202020202020202020202021E +:10D2F000020202020202020200000000000000001E +:10D300000000000000000000010101010101010115 +:10D3100001010101010101010101010101010101FD +:10D3200001010101010101010202020202020202E5 +:10D3300002020202020202020202020202020202CD +:10D3400002020202020202020202020202020202BD +:10D3500002020202020202020202020202020202AD +:10D3600002020202020202020101010200020101A4 +:10D370000101010100000201020202020202020296 +:10D38000020202020202020202020202020202027D +:10D39000020202020202020202020202020202026D +:10D3A000020202020202020202020202020202025D +:10D3B000020202020202020202020202000202024F +:10D3C000020202020201010202020202020202023F +:10D3D000020202020202020202020202020202022D +:10D3E000020202020202020202020202020202021D +:10D3F000020202020202020201000000010001001A +:10D400000000000000000100010101010101010113 +:10D4100001010101010101010202020202020202F4 +:10D4200002020202020202020202020202020202DC +:10D4300002020202020202020202020202020202CC +:10D4400002020202020202020202020202020202BC +:10D4500002020202020202020202020202020202AC +:10D4600002020202020202020202020000000202A2 +:10D470000202020200000002020202020202020292 +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202010202026D +:10D4A000020202020202020202020202020202025C +:10D4B0000202020202020202020202020002010150 +:10D4C0000101010101020201020202020202020242 +:10D4D000020202020202020202020202020202022C +:10D4E000020202020202020202020202020202021C +:10D4F0000202020202020202010100010101010115 +:10D50000000001010100010101010101010101010E +:10D510000101010101010101000000000000000003 +:10D5200000000000000000000101010101010101F3 +:10D5300001010101010101010202020202020202D3 +:10D5400002020202020202020202020202020202BB +:10D5500002020202020202020202020101020202AD +:10D5600002020202020202020000000000000000AB +:10D57000000000000000000002020202020202029B +:10D58000020202020202020202020202020202027B +:10D59000020202020202020202020201020202026C +:10D5A000020202020202020202020202020202025B +:10D5B0000202020202020202010101010001020252 +:10D5C000020202020202020202020202020202023B +:10D5D000020202020202020202020202020202022B +:10D5E000020202020202020202020202020202021B +:10D5F0000202020202020202010101010101010113 +:10D60000010101010100010101010101010101010B +:10D6100001010101010101010101010101010101FA +:10D6200001010101010101010202020202020202E2 +:10D6300002020202020202020101010101010101D2 +:10D6400001010101010101010000000000000000D2 +:10D6500000000000000000000101010202010101C0 +:10D6600001010101010101010000000000000000B2 +:10D67000000000000000000002020200000202029E +:10D68000020202020202020202020202020202027A +:10D690000202020202020202010101020001010172 +:10D6A0000101010101010101020202020202020262 +:10D6B0000202020202020202010101010001000055 +:10D6C000000000000000000002020202020202024A +:10D6D000020202020202020202020202020202022A +:10D6E000020202020202020202020202020202021A +:10D6F0000202020202020202010101010101010112 +:10D700000101010101010101010101010101010109 +:10D7100001010101010101010101010101010101F9 +:10D7200001010101010101010101010101010101E9 +:10D7300001010101010101010101010101010101D9 +:10D7400001010101010101010101010101010101C9 +:10D7500001010101010101010202020000020202B5 +:10D7600002020202020202020000000000000000A9 +:10D7700000000000000000000202000000000002A3 +:10D780000202020202020202020202020202020279 +:10D79000020202020202020202020200000202026D +:10D7A0000202020202020202020202020202020259 +:10D7B000020202020202020202020202000200004F +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000020202020202020239 +:10D7E0000202020202020202020202020202020219 +:10D7F0000202020202020202010101010101010111 +:10D800000101010101010101010101010101010108 +:10D8100001010101010101010101010101010101F8 +:10D8200001010101010101010101010101010101E8 +:10D8300001010101010101010101010101010101D8 +:10D8400001010101010101010101010101010101C8 +:10D8500001010101010101010101010101010101B8 +:10D8600001010101010101010000000000000000B0 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000020202000000000290 +:10D890000202020202020202000000000000000078 +:10D8A000000000000000000002020202000202026A +:10D8B000020202020202020202020202000200004E +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000020202020202020238 +:10D8E0000202020202020202020202020202020218 +:10D8F0000202020202020202010101010101010110 +:10D900000101010101010101010101010101010107 +:10D9100001010101010101010101010101010101F7 +:10D9200001010101010101010101010101010101E7 +:10D9300001010101010101010101010101010101D7 +:10D9400001010101010101010101010101010101C7 +:10D9500001010101010101010101010101010101B7 +:10D9600001010101010101010101010101010101A7 +:10D970000101010101010101010101010101010197 +:10D980000101010101010101010101010101010187 +:10D99000010101010101010100000000000000007F +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D000000000000000000001010101010101013F +:10D9E000010101010101010102020202020202021F +:10D9F000020202020202020201010101010101010F +:10DA00000101010101010101010101010101010106 +:10DA100001010101010101010101010101010101F6 +:10DA200001010101010101010101010101010101E6 +:10DA300001010101010101010101010101010101D6 +:10DA400001010101010101010101010101010101C6 +:10DA500001010101010101010101010101010101B6 +:10DA600001010101010101010101010101010101A6 +:10DA70000101010101010101010101010101010196 +:10DA80000101010101010101010101010101010186 +:10DA90000101010101010101010101010101010176 +:10DAA0000101010101010101010101010101010166 +:10DAB000010101010101010100000000000000005E +:10DAC0000000000000000000000000000000000056 +:10DAD000000000000000000001010101010101013E +:10DAE000010101010101010102020202020202021E +:10DAF000020202020202020201010101010101010E +:10DB00000101010101010101010101010101010105 +:10DB100001010101010101010101010101010101F5 +:10DB200001010101010101010101010101010101E5 +:10DB300001010101010101010101010101010101D5 +:10DB400001010101010101010101010101010101C5 +:10DB500001010101010101010101010101010101B5 +:10DB600001010101010101010101010101010101A5 +:10DB70000101010101010101010101010101010195 +:10DB80000101010101010101010101010101010185 +:10DB90000101010101010101010101010101010175 +:10DBA0000101010101010101010101010101010165 +:10DBB0000101010101010101010101010101010155 +:10DBC0000101010101010101010101010101010145 +:10DBD0000101010101010101010101010101010135 +:10DBE000010101010101010100000000000000002D +:10DBF000000000000000000001010101010101011D +:10DC00000101010101010101010101010101010104 +:10DC100001010101010101010101010101010101F4 +:10DC200001010101010101010101010101010101E4 +:10DC300001010101010101010101010101010101D4 +:10DC400001010101010101010101010101010101C4 +:10DC500001010101010101010101010101010101B4 +:10DC600001010101010101010101010101010101A4 +:10DC70000101010101010101010101010101010194 +:10DC80000101010101010101010101010101010184 +:10DC90000101010101010101010101010101010174 +:10DCA0000101010101010101010101010101010164 +:10DCB0000101010101010101010101010101010154 +:10DCC0000101010101010101010101010101010144 +:10DCD0000101010101010101010101010101010134 +:10DCE000010101010101010100000000000000002C +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000000000000000000000000000000003 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000202020202020202D3 +:10DD400002020202020202020202020202020202B3 +:10DD500002020202020202020202020202020202A3 +:10DD60000202020202020202020202020202020293 +:10DD70000202020202020202020202020202020283 +:10DD80000202020202020202020202020202020273 +:10DD90000202020202020202020202020202020263 +:10DDA0000202020202020202020202020202020253 +:10DDB0000202020202020202020202020202020243 +:10DDC0000202020202020202020202020202020233 +:10DDD0000202020202020202020202020202020223 +:10DDE0000202020202020202000000000000000023 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE10000000000000000000000000000000000002 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000000062 +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000020202020202020232 +:10DEE0000202020202020202000000000000000022 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF10000000000000000000000000000000000001 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000000000000000000B1 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000000061 +:10DFC0000000000000000000000000000000000051 +:10DFD0000000000000000000020202020202020231 +:10DFE0000202020202020202000000000000000021 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E010000000000000000000000000000000000000 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000000000000000000B0 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000000000000000000060 +:10E0C0000000000000000000000000000000000050 +:10E0D0000000000000000000000000000000000040 +:10E0E0000000000000000000000000000000000030 +:10E0F00000000000000000003100000000000000EF +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000000000000000000FF +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000000000000000000000000000000AF +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000000000000000000005F +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F0000000000100010101010100010000000018 +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000000000000000000FE +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000000000000000000000000000000AE +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000000000000000000005E +:10E2C000000000000000000000000000000001004D +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F0000000000101010101010101010101010012 +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000000000000000000FD +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E3600000000000000000000000000000000000AD +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000000000000000000005D +:10E3C000000000000000000000000000000001004C +:10E3D000000000000000000000000000000000003D +:10E3E000000000000100000000000000000000002C +:10E3F0000000000101010101010101010101010011 +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000000000000000000FC +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E4600000000000000000000000000000000000AC +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000000000000010001005A +:10E4C000000000000000000000000000010001004A +:10E4D000000000000000000000000000000000003C +:10E4E0000000000101010000000000000000000029 +:10E4F0000000000101010101010101010101010010 +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000000000000000000FB +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000001010100D8 +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E5600000000000000000000000000000000000AB +:10E57000000000000000000000000000000000009B +:10E580000000000000000000000000000101010088 +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B0000000000100010000000000000100010057 +:10E5C0000000000000000000000000000100010049 +:10E5D000000000000000000000000000000000003B +:10E5E0000000000101010000000000000100000027 +:10E5F000000000010101010101010101010101000F +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000000000000000000FA +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000101010100D6 +:10E6400000000000000000000000000001010000C8 +:10E6500000000000000000000000000000000000BA +:10E6600000000000000000000000000000000000AA +:10E67000000000000000000000000000000000009A +:10E680000000000000000000000000010101010086 +:10E690000000000000000000000000000101000078 +:10E6A000000000000000000000000000000000006A +:10E6B0000000000100010000000000000101010154 +:10E6C0000000000000000000000000000101010047 +:10E6D000000000000000000000000000000000003A +:10E6E0000001010101010000000000010100000023 +:10E6F000000000010101010101010101010101000E +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000000000000000000F9 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000101010101D4 +:10E7400000000000000000000000000001010000C7 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000000000000000000A9 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000001010101010084 +:10E790000000000000000000000000010101000076 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000100010100000000000101010152 +:10E7C0000000000000010000000000010101010044 +:10E7D0000000000000000000000000000000000039 +:10E7E0000001010101010000000000010100000022 +:10E7F000000000010101010101010101010101000D +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000000000001000100F6 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000100000000000101010101D2 +:10E8400000000000000000000000010001010100C4 +:10E8500000000000000000000000000001010100B5 +:10E8600000000000000000000000000000000000A8 +:10E870000000000000000000000000000000010097 +:10E880000000000000000000000001010101010083 +:10E890000000000000000000000000010101000075 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000101010100000000000101010150 +:10E8C0000000000001010000000000010101010042 +:10E8D0000000000000000000000000000000000038 +:10E8E0000101010101010000000000010100000020 +:10E8F000000000010101010101010101010101000C +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000000000001000100F5 +:10E9200000000000000000000000000001010101E3 +:10E9300000000000000100000000010101010101D0 +:10E9400000000000000000000000010101010100C2 +:10E9500000000000000000000000000001010100B4 +:10E9600000000000000000000000000001000000A6 +:10E970000000000000000000000000000000010096 +:10E980000000000000000000000001010101010181 +:10E990000000000000000000000000010101000074 +:10E9A0000000000000000000000000000001010065 +:10E9B000000000010101010000000001010101014E +:10E9C0000000000001010100000000010101010040 +:10E9D0000000000100010101000100010000000031 +:10E9E000010101010101000000000001010000001F +:10E9F000000001010101010101010101010101000A +:10EA00000000000000000001000000000000000005 +:10EA100000000000000000000000000001010100F3 +:10EA200000000000000001000000000101010101E0 +:10EA300000000000000101010000010101010101CD +:10EA400000000000000000000000010101010101C0 +:10EA500000000000000000000000000001010100B3 +:10EA600000000000000000000000000001000000A5 +:10EA70000000000000000000000000000101010093 +:10EA8000000000000001010100000101010101017D +:10EA90000000000001000000000000010101010170 +:10EAA0000000000000000000000000000001010064 +:10EAB000000000010101010000000101010101014C +:10EAC000000000000101010000000001010101003F +:10EAD000000000010001010100010101010101012B +:10EAE000010101010101000000000001010000001E +:10EAF0000000010101010101010101010101010009 +:10EB00000000000000000001000000000000010003 +:10EB100000000000000000000000000001010100F2 +:10EB200000000000000001000000010101010101DE +:10EB300000000000010101010000010101010101CB +:10EB400000000000000000000000010101010101BF +:10EB500000000000000000000000000001010100B2 +:10EB600000000000000000000000000001010100A2 +:10EB70000000000000000000000000000101010092 +:10EB8000000000000101010100000101010101017B +:10EB9000000000000101010100000001010101016C +:10EBA0000000000000000000000000000101010062 +:10EBB0000000000101010101010001010101010149 +:10EBC000000001010101010000000001010101003C +:10EBD0000101010100010101010101010101010126 +:10EBE000010101010101000000000001010000001D +:10EBF0000000010101010101010101010101010008 +:10EC00000000000000000101000000000000010001 +:10EC100000000000000000000000000001010100F1 +:10EC200000000000000101010100010101010101DA +:10EC300000000000010101010100010101010101C9 +:10EC400000000000000000000000010101010101BE +:10EC500000000000000000000000000001010101B0 +:10EC600000000000000000000000000001010100A1 +:10EC70000000000000000000000000000101010091 +:10EC80000000000101010101000001010101010179 +:10EC9000000000000101010100000101010101016A +:10ECA0000000000000000000000000010101010060 +:10ECB0000000000101010101010001010101010148 +:10ECC000000001010101010000000001010101003B +:10ECD0000101010101010101010101010101010124 +:10ECE000010101010101000100000001010000001B +:10ECF0000000010101010101010101010101010007 +:10ED000000000000010001020000000000010100FD +:10ED100001000000000100000000000101010100ED +:10ED200000000000010101010100010101010101D8 +:10ED300000000000010101010100010101010101C8 +:10ED400000000000000100010000010101010101BB +:10ED500000000000000100000000000101010101AD +:10ED600000000000000000000000000001010100A0 +:10ED7000000000000000000000000001010101008F +:10ED80000000000101010101000001010101010178 +:10ED90000000000101010101010001010101010167 +:10EDA000000000000000000000000001010101005F +:10EDB0000001000101010101010101010101010145 +:10EDC0000001010101010101000000010101010038 +:10EDD0000101010101010101010101010101010123 +:10EDE000010101010101000100000001010000001A +:10EDF0000001010101010101010101010101010005 +:10EE000002000000010001020000000000010100FA +:10EE100001000000010100000000000101010101EA +:10EE200000000001010101010101010101010101D5 +:10EE300000000001010101010101010101010101C5 +:10EE400000000000010100010000010101010101B9 +:10EE500000000000000100000000000101010101AC +:10EE6000000000000000000000000000010101009F +:10EE7000000000000000000000000001010101018D +:10EE80000000000101010101010101010101010175 +:10EE90000000000101010101010001010101010166 +:10EEA000000000000001010000000001010101005C +:10EEB0000001000101010101010101010101010144 +:10EEC0000001010101010101000000010101010037 +:10EED0000101010101010101010101010101010122 +:10EEE0000101010101010001000000010100000019 +:10EEF0000001010101010101010101010101010004 +:10EF000002000000010001020000000000010100F9 +:10EF100001000000010101000000000101010101E8 +:10EF200000000001010101010101010101010101D4 +:10EF300000000001010101010101010101010101C4 +:10EF400000000000010101010001010101010101B6 +:10EF500000000000000101000000000101010101AA +:10EF6000000000000000000000000000010101019D +:10EF7000000000000000000000000001010101018C +:10EF80000000000101010101010101010101010174 +:10EF90000000000101010101010101010101010164 +:10EFA0000000000001010100000001010101010158 +:10EFB0000001010101010101010101010101010142 +:10EFC0000101010101010101000000010101010035 +:10EFD0000101010101010101010101010101010121 +:10EFE0000101010101010001000000010100000018 +:10EFF0000001010101010101010101010101010003 +:10F0000002000200010001020000000000010100F6 +:10F0100001000000010101000000000101010101E7 +:10F0200000000001010101010101010101010101D3 +:10F0300000000001010101010101010101010101C3 +:10F0400000000000010101010001010101010101B5 +:10F0500000000000000101000100000101010101A8 +:10F06000000000000001000000000001010101019A +:10F07000000000000000000000000001010101018B +:10F080000001010101010101010101010101010171 +:10F090000000000101010101010101010101010163 +:10F0A0000000000101010101000001010101010155 +:10F0B0000001010101010101010101010101010141 +:10F0C0000101010101010101000001010101010132 +:10F0D0000101010101010101010101010101010120 +:10F0E0000201010101010001000000010100000016 +:10F0F0000001010001010101010101010101010003 +:10F1000002000200010001020000000001010100F4 +:10F1100002000000010101000000000101010101E5 +:10F1200000000001010101010101010101010101D2 +:10F1300000000001010101010101010101010101C2 +:10F1400000000001010101010001010101010101B3 +:10F1500000000000000101000100010101010101A6 +:10F160000000000000010000000000010101010199 +:10F170000000000000010100000000010101010188 +:10F180000001010101010101010101010101010170 +:10F190000001010101010101010101010101010160 +:10F1A0000000000101010101000001010101010154 +:10F1B0000001010101010101010101010101010140 +:10F1C0000101010101010101000001010101010131 +:10F1D000010101010101010101010101010101011F +:10F1E0000201010101010001000000010100000015 +:10F1F0000001010000000000000001010101010107 +:10F2000002000200010001020000000101010100F2 +:10F2100002000000010101000000010101010101E3 +:10F2200000010101010101010101010101010101CF +:10F2300000010101010101010101010101010101BF +:10F2400000000001010101010001010101010101B2 +:10F2500000000000010101000101010101010101A3 +:10F260000000000000010000000000010101010198 +:10F270000000000001010100000001010101010185 +:10F28000010101010101010101010101010101016E +:10F29000000101010101010101010101010101015F +:10F2A0000000000101010101010001010101010152 +:10F2B000000101010101010101010101010101013F +:10F2C0000101010101010101000001010101010130 +:10F2D000010101010101010101010101010101011E +:10F2E0000202010101010001000000010100000013 +:10F2F0000001010000000000000000000101010108 +:10F3000002000200010002020000000101010100F0 +:10F3100002000001010101010000010101010101E0 +:10F3200000010101010101010101010101010101CE +:10F3300000010101010101010101010101010101BE +:10F3400001010001010101010101010101010101AE +:10F3500000010001010101000101010101010101A0 +:10F360000000000001010000000000010101010196 +:10F370000000000101010101000001010101010182 +:10F38000010101010101010101010101010101016D +:10F39000010101010101010101010101010101015D +:10F3A0000000000101010101010001010101010151 +:10F3B000010101010101010101010101010101013D +:10F3C000020101010101010100000101010101012E +:10F3D000020101010101010101010101010101011C +:10F3E000020202020201000100000001010000010E +:10F3F000000100000000000000000000000000010B +:10F4000002000200020102020000000101010201EB +:10F4100002000001010101010000010101010101DF +:10F4200001010101010101010101010101010101CC +:10F4300001010101010101010101010101010101BC +:10F4400001010001010101010101010101010101AD +:10F45000000100010101010001010101010101019F +:10F460000001000101010100000001010101010191 +:10F470000000000101010101000001010101010181 +:10F48000010101010101010101010101010101016C +:10F49000010101010101010101010101010101015C +:10F4A000000101010101010101000101010101014E +:10F4B000010101010101010101010101010101013C +:10F4C000020101010101010100000101010102012C +:10F4D000020101010101010101010101010101011B +:10F4E000020202020202000100000001010000010C +:10F4F000000000000000000000000000000000010B +:10F5000002000200020102020000000101020201E9 +:10F5100002010001010101010000010101010101DD +:10F5200001010101010101010101010101010101CB +:10F5300001010101010101010101010101010101BB +:10F5400002010101010101010101020101010101A9 +:10F55000010100010101010101010101010101019C +:10F560000001000101010100000001010101010190 +:10F57000000100010101010101000101010101017E +:10F58000020101010101010101010101010101016A +:10F59000010101010101010101010101010101015B +:10F5A000000101010101010101000101010101014D +:10F5B000010101010101010101010101010101013B +:10F5C0000202020102020101000001010201020126 +:10F5D000020101010101010101010101010101011A +:10F5E000020202020202000100000001010000010B +:10F5F000000000000000000000000000000000010A +:10F6000002000200020102020001000101020201E7 +:10F6100002010001010101010000010101010101DC +:10F6200001010101010101010101010101010101CA +:10F6300001010101010101010101010101010101BA +:10F6400002010101010101010101020102020101A6 +:10F65000020100010101010101010101010101019A +:10F66000010100010101010100000101010101018D +:10F67000000100010101010101000101010101017D +:10F680000201010101010101010102020202020164 +:10F690000201010101010101010101010101010159 +:10F6A000010101010101010101010101010101014A +:10F6B0000101010201010101010101010101010139 +:10F6C0000202020202020201000101020202020120 +:10F6D0000202010101010101010101010101010118 +:10F6E0000202020202020001010100020200000106 +:10F6F0000000000000000000000000000000000109 +:10F7000002000200020102020002010101020201E4 +:10F7100002010101010101010100010101010101D9 +:10F7200002010101010101010101010101010101C8 +:10F7300002010101010201010101010202020201B3 +:10F7400002010101010101010101020202020201A3 +:10F750000201010101010101010101010202020195 +:10F76000020100010101010101000101010101018A +:10F770000101010101010101010101010101010179 +:10F78000020201020202020201010202020202015D +:10F790000201010102010101010101020202010154 +:10F7A0000101010101010101010101010101010149 +:10F7B0000101010201020101010101010101010137 +:10F7C000020202020202020101010102020202011E +:10F7D0000202020201010101010101010101010115 +:10F7E0000202020202020001010100020200010104 +:10F7F0000000000000000000000000000000000108 +:10F8000002010201020102010002010201020201E1 +:10F8100002010101010101010100010102010201D6 +:10F8200002010101010102010101010101010101C6 +:10F8300002010101020202020101020202020202AD +:10F84000020201010202010201020202020202029C +:10F850000202010101020101010101010202020192 +:10F860000201010101010101010001010201010187 +:10F870000101010101010101010101010101010178 +:10F88000020202020202020201010202020202025A +:10F89000020201020202020201010102020201014E +:10F8A0000101010101010101010101010101010148 +:10F8B0000202010202020201010101010201020130 +:10F8C000020202020202020201010102020202011C +:10F8D0000202020201020202010201010101010110 +:10F8E0000202020202020102010100020200010101 +:10F8F0000000000000000000000000000000000107 +:10F9000002020201020102010002010201020201DF +:10F9100002010101020201010100010102020201D2 +:10F9200002020102020202020201020202020202B9 +:10F9300002020102020202020201020202020202A9 +:10F940000202010202020202010202020202020299 +:10F95000020201010102020102010102020202028D +:10F960000202010101010101010001010202020183 +:10F970000201010101010101010101010101020175 +:10F980000202020202020202020202020202020257 +:10F990000202020202020202020102020202020248 +:10F9A0000201010101010101010101010101010146 +:10F9B000020201020202020101010101020202022D +:10F9C000020202020202020201010102020202011B +:10F9D000020202020202020202020202010101010B +:10F9E00002020202020201020101010202010101FE +:10F9F0000000000200000000000000000000000104 +:10FA000002020102020102010002010201020201DE +:10FA100002020101020202010100010202020201CE +:10FA200002020202020202020202020202020202B6 +:10FA300002020202020202020202020202020202A6 +:10FA40000202020202020202010202020202020297 +:10FA50000202010202020201020202020202020288 +:10FA60000202010101020101010001010202020181 +:10FA70000201010101010101010101010202020172 +:10FA80000202020202020202020202020202020256 +:10FA90000202020202020202020202020202020246 +:10FAA0000201010101010101010101010102020143 +:10FAB0000202020202020202020102020202020227 +:10FAC0000202020202020202010102020202020119 +:10FAD0000202020202020202020202020202020206 +:10FAE00002020202020201020101010202010101FD +:10FAF00000000002020202020202000000000001F7 +:10FB000002020102020202010002020202020200DB +:10FB100002020102020202010101010202020202CA +:10FB200002020202020202020202020202020202B5 +:10FB300002020202020202020202020202020202A5 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020201020202020202020286 +:10FB6000020201020202010101010102020202027B +:10FB7000020201010101010101010102020202016F +:10FB80000202020202020202020202020202020255 +:10FB90000202020202020202020202020202020245 +:10FBA000020201020202020101010102020202013B +:10FBB0000202020202020202020202020202020225 +:10FBC0000202020202020202010102020202020217 +:10FBD0000202020202020202020202020202020205 +:10FBE00002020202020201020101010202010101FC +:10FBF00000000002020202020202020200000001F2 +:10FC000002020102020202010001020202020200DB +:10FC100002020202020202020101020202020202C6 +:10FC200002020202020202020202020202020202B4 +:10FC300002020202020202020202020202020202A4 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC60000202020202020201010102020202020277 +:10FC70000202010202020201010101020202020269 +:10FC80000202020202020202020202020202020254 +:10FC90000202020202020202020202020202020244 +:10FCA0000202020202020202010102020202020137 +:10FCB0000202020202020202020202020202020224 +:10FCC0000202020202020202010202020202020215 +:10FCD0000202020202020202020202020202020204 +:10FCE00002020202020201020101010202010101FB +:10FCF00001000202020202020202020202020200E9 +:10FD000001020102020201010001020202010100DE +:10FD100002020202020202020101020202020202C5 +:10FD200002020202020202020202020202020202B3 +:10FD300002020202020202020202020202020202A3 +:10FD40000202020202020202020202020202020293 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202020102020202020274 +:10FD70000202020202020202010102020202020265 +:10FD80000202020202020202020202020202020253 +:10FD90000202020202020202020202020202020243 +:10FDA0000202020202020202020102020202020234 +:10FDB0000202020202020202020202020202020223 +:10FDC0000202020202020202020202020202020213 +:10FDD0000202020202020202020202020202020203 +:10FDE00002020202020201020202010202010102F7 +:10FDF00002020202020202020202020202020200E5 +:10FE000001020102010201010101020102010100DE +:10FE100002020202020202020201020202020202C3 +:10FE200002020202020202020202020202020202B2 +:10FE300002020202020202020202020202020202A2 +:10FE40000202020202020202020202020202020292 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202020102020202020273 +:10FE70000202020202020202020102020202020263 +:10FE80000202020202020202020202020202020252 +:10FE90000202020202020202020202020202020242 +:10FEA0000202020202020202020102020202020233 +:10FEB0000202020202020202020202020202020222 +:10FEC0000202020202020202020202020202020212 +:10FED0000202020202020202020202020202020202 +:10FEE00002020202020202020202010202010102F5 +:10FEF00002020202020202020202020202020200E4 +:10FF000001020101010201010101010102010100DF +:10FF100002020202020202020201020202020202C2 +:10FF200002020202020202020202020202020202B1 +:10FF300002020202020202020202020202020202A1 +:10FF40000202020202020202020202020202020291 +:10FF50000202020202020202020202020202020281 +:10FF60000202020202020202020202020202020271 +:10FF70000202020202020202020202020202020261 +:10FF80000202020202020202020202020202020251 +:10FF90000202020202020202020202020202020241 +:10FFA0000202020202020202020202020202020231 +:10FFB0000202020202020202020202020202020221 +:10FFC0000202020202020202020202020202020211 +:10FFD0000202020202020202020202020202020201 +:10FFE00002020202020202020202020202010202F2 +:10FFF00002020202020202020202020202020200E3 +:02000002A0005C +:1000000001010101010201010201010102010100DE +:1000100002020202020202020202020202020202C0 +:1000200002020202020202020202020202020202B0 +:1000300002020202020202020202020202020202A0 +:100040000202020202020202020202020202020290 +:100050000202020202020202020202020202020280 +:100060000202020202020202020202020202020270 +:100070000202020202020202020202020202020260 +:100080000202020202020202020202020202020250 +:100090000202020202020202020202020202020240 +:1000A0000202020202020202020202020202020230 +:1000B0000202020202020202020202020202020220 +:1000C0000202020202020202020202020202020210 +:1000D0000202020202020202020202020202020200 +:1000E00002020202020202020202020202020202F0 +:1000F00002020202020202020202020202020200E2 +:1001000001010101010101010101010101010100E0 +:1001100002020202020202020202020202020202BF +:1001200002020202020202020202020202020202AF +:10013000020202020202020202020202020202029F +:10014000020202020202020202020202020202028F +:10015000020202020202020202020202020202027F +:10016000020202020202020202020202020202026F +:10017000020202020202020202020202020202025F +:10018000020202020202020202020202020202024F +:10019000020202020202020202020202020202023F +:1001A000020202020202020202020202020202022F +:1001B000020202020202020202020202020202021F +:1001C000020202020202020202020202020202020F +:1001D00002020202020202020202020202020202FF +:1001E00002020202020202020202020202020202EF +:1001F00002020202020202020202020202020200E1 +:1002000001010101010101000101010101010100E0 +:1002100002020202020202020202020202020202BE +:1002200002020202020202020202020202020202AE +:10023000020202020202020202020202020202029E +:10024000020202020202020202020202020202028E +:10025000020202020202020202020202020202027E +:10026000020202020202020202020202020202026E +:10027000020202020202020202020202020202025E +:10028000020202020202020202020202020202024E +:10029000020202020202020202020202020202023E +:1002A000020202020202020202020202020202022E +:1002B000020202020202020202020202020202021E +:1002C000020202020202020202020202020202020E +:1002D00002020202020202020202020202020202FE +:1002E00002020202020202020202020202020202EE +:1002F00002020202020202020202020202020202DE +:1003000001010001010101000101010101010100E0 +:1003100002020202020202020202020202020202BD +:1003200002020202020202020202020202020202AD +:10033000020202020202020202020202020202029D +:10034000020202020202020202020202020202028D +:10035000020202020202020202020202020202027D +:10036000020202020202020202020202020202026D +:10037000020202020202020202020202020202025D +:10038000020202020202020202020202020202024D +:10039000020202020202020202020202020202023D +:1003A000020202020202020202020202020202022D +:1003B000020202020202020202020202020202021D +:1003C000020202020202020202020202020202020D +:1003D00002020202020202020202020202020202FD +:1003E00002020202020202020202020202020202ED +:1003F00002020202020202020202020202020202DD +:1004000000010001010100000100010101000000E4 +:1004100002020202020202020202020202020202BC +:1004200002020202020202020202020202020202AC +:10043000020202020202020202020202020202029C +:10044000020202020202020202020202020202028C +:10045000020202020202020202020202020202027C +:10046000020202020202020202020202020202026C +:10047000020202020202020202020202020202025C +:10048000020202020202020202020202020202024C +:10049000020202020202020202020202020202023C +:1004A000020202020202020202020202020202022C +:1004B000020202020202020202020202020202021C +:1004C000020202020202020202020202020202020C +:1004D00002020202020202020202020202020202FC +:1004E00002020202020202020202020202020202EC +:1004F00002020202020202020202020202020202DC +:1005000000010000000100000100000001000000E7 +:1005100001020202020202020202020202020202BC +:1005200002020202020202020202020202020202AB +:10053000020202020202020202020202020202029B +:10054000020202020202020202010102020202028D +:10055000020202020202020202020202020202027B +:10056000020202020202020202020202020202026B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202024B +:10059000020202020202020202020202020202023B +:1005A000020202020202020202020202020202022B +:1005B000020202020202020202020202020202021B +:1005C000020202020202020202020202020202020B +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000000000000000000000000000000000000EA +:1006100002020202020202020202020202020202BA +:1006200002020202020202020202020202020202AA +:10063000020202020202020202020202020202029A +:10064000020202020202020202020202020202028A +:10065000020202020202020201010102020202027D +:10066000020202020202020201010102020202026D +:10067000020202020202020202020202020202025A +:10068000010101010101010101010101010101015A +:10069000020202020202020202020202020202023A +:1006A000020202020202020202020202020202022A +:1006B000020202020202020202020202020202021A +:1006C000020202020202020202010202020202020B +:1006D00002020202020202020202020202020202FA +:1006E00002020202020202020202020202020202EA +:1006F00002020202020202020202020202020202DA +:1007000000000000000000010000000000000000E8 +:1007100001010101010101010101010101010101C9 +:1007200002020202020202020202020202020202A9 +:100730000202020202020202020202020202020299 +:1007400000000000000000000000000000000000A9 +:100750000101010101010101010101010101010189 +:100760000101010101010101010101010101010179 +:100770000202020202020202020202020202020259 +:100780000101010101010101010101010101010159 +:100790000101010101010101010101010101010149 +:1007A0000202020202020202020202020202020229 +:1007B0000202020202020202020202020202020219 +:1007C0000101010101010101010101010101010119 +:1007D00002020202020202020202020202020202F9 +:1007E00001010101010101010101010101010101F9 +:1007F00002020202020202020202020202020202D9 +:1008000000000100000000010000000000000000E6 +:1008100001020202020202020202020202020202B9 +:1008200001010101010101010101010101010101B8 +:100830000202020202020202020202020202020298 +:1008400000000000000000000000000000000000A8 +:100850000202020202020202020202020202020278 +:100860000202020202020202020202020202020268 +:100870000202020202020202020202020202020258 +:100880000202020202020202020202020202020248 +:100890000202020202020202020202020202020238 +:1008A0000202020202020202020202020202020228 +:1008B0000202020202020202020202020202020218 +:1008C0000202020202020202020202020202020208 +:1008D00002020202020202020202020202020202F8 +:1008E00002020202020202020202020202020202E8 +:1008F00002020202020202020202020202020202D8 +:1009000001000100000001010001000000010101DF +:1009100001010101010101010101010101010101C7 +:1009200002020202020202020202020202020202A7 +:1009300001010101010101010101010101010101A7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000020202000000000091 +:100960000000000000000000020202000000000081 +:100970000202020202020202020202020202020257 +:100980000202020202020202020202020202020247 +:100990000000000000000000000000000000000057 +:1009A0000202020202020202020202020202020227 +:1009B0000202020202020202020202020202020217 +:1009C0000000000000000000000200000000000025 +:1009D00002020202020202020202020202020202F7 +:1009E0000000000000000000000000000000000007 +:1009F00002020202020202020202020202020202D7 +:100A000001000101010001010001010100010101DA +:100A100001010101010101010101010101010101C6 +:100A200000000000000000000000000000000000C6 +:100A30000202020202020202020202020202020296 +:100A40000101010101010101010101010101010196 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000101010101010101010101010101010166 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000202020202020202020202020202020226 +:100AB0000202020202020202020202020202020216 +:100AC0000000000000000000000000000000000026 +:100AD00002020202020202020202020202020202F6 +:100AE0000000000000000000000000000000000006 +:100AF00002020202020202020202020202020202D6 +:100B000001010101010101010101010101010101D5 +:100B100001010101010101010101010101010101C5 +:100B200001010101010101010101010101010101B5 +:100B300000000000000000000000000000000000B5 +:100B40000101010101010101010101010101010195 +:100B50000101010101010101010101010101010185 +:100B60000000000000000000000000000000000085 +:100B70000202020202020202020202020202020255 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000101010101010101010101010101010135 +:100BB0000202020202020202020202020202020215 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00002020202020202020202020202020202D5 +:100C000001010101010101010101010101010101D4 +:100C100001010101010101010101010101010101C4 +:100C200001010101010101010101010101010101B4 +:100C300001010101010101010101010101010101A4 +:100C40000101010101010101010101010101010194 +:100C50000101010101010101010101010101010184 +:100C60000101010101010101010101010101010174 +:100C70000101010101010101010101010101010164 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000202020202020202020202020202020224 +:100CB0000202020202020202020202020202020214 +:100CC0000000000000000000000000000000000024 +:100CD0000101010101010101010101010101010104 +:100CE0000000000000000000000000000000000004 +:100CF00002020202020202020202020202020202D4 +:100D000001010101010101010101010101010101D3 +:100D100001010101010101010101010101010101C3 +:100D200001010101010101010101010101010101B3 +:100D300001010101010101010101010101010101A3 +:100D40000101010101010101010101010101010193 +:100D50000101010101010101010101010101010183 +:100D60000101010101010101010101010101010173 +:100D70000101010101010101010101010101010163 +:100D80000101010101010101010101010101010153 +:100D90000101010101010101010101010101010143 +:100DA0000101010101010101010101010101010133 +:100DB0000101010101010101010101010101010123 +:100DC0000101010101010101010101010101010113 +:100DD0000101010101010101010101010101010103 +:100DE00001010101010101010101010101010101F3 +:100DF00000000000000000000000000000000000F3 +:100E000001010101010101010101010101010101D2 +:100E100001010101010101010101010101010101C2 +:100E200001010101010101010101010101010101B2 +:100E300001010101010101010101010101010101A2 +:100E40000101010101010101010101010101010192 +:100E50000101010101010101010101010101010182 +:100E60000101010101010101010101010101010172 +:100E70000101010101010101010101010101010162 +:100E80000101010101010101010101010101010152 +:100E90000101010101010101010101010101010142 +:100EA0000101010101010101010101010101010132 +:100EB0000101010101010101010101010101010122 +:100EC0000101010101010101010101010101010112 +:100ED0000101010101010101010101010101010102 +:100EE00001010101010101010101010101010101F2 +:100EF00000000000000000000000000000000000F2 +:100F000001010101010101010101010101010101D1 +:100F100001010101010101010101010101010101C1 +:100F200001010101010101010101010101010101B1 +:100F300001010101010101010101010101010101A1 +:100F40000101010101010101010101010101010191 +:100F50000101010101010101010101010101010181 +:100F60000101010101010101010101010101010171 +:100F70000101010101010101010101010101010161 +:100F80000101010101010101010101010101010151 +:100F90000101010101010101010101010101010141 +:100FA0000101010101010101010101010101010131 +:100FB0000101010101010101010101010101010121 +:100FC0000202020202020202020202020202020201 +:100FD00002020202020202020202020202020202F1 +:100FE00002020202020202020202020202020202E1 +:100FF00000000000000000000000000000000000F1 +:1010000001010101010101010101010101010101D0 +:1010100001010101010101010101010101010101C0 +:1010200001010101010101010101010101010101B0 +:1010300001010101010101010101010101010101A0 +:101040000202020202020202020202020202020280 +:101050000202020202020202020202020202020270 +:101060000202020202020202020202020202020260 +:101070000202020202020202020202020202020250 +:101080000202020202020202020202020202020240 +:101090000202020202020202020202020202020230 +:1010A0000202020202020202020202020202020220 +:1010B0000202020202020202020202020202020210 +:1010C0000000000000000000000000000000000020 +:1010D00002020202020202020202020202020202F0 +:1010E00002020202020202020202020202020202E0 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000032000000000000000000000000000000AC +:1012100000000000000000000000000000000000CE +:1012200000000000000000000000000000000000BE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000010000002D +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200000000000000000000000000000000000BD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000001010000002B +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200000000000000000000000000000000000BC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000001010000002A +:1014C000000000000000000000000000000000001C +:1014D000000000000000000000000000000000000C +:1014E00000000000000000000000000000000000FC +:1014F00000000000000000000000000000010000EB +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200000000000000000000000000000000000BB +:1015300000000000000000000000000000000000AB +:101540000000000001010100000000000000000098 +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B0000000000000000000000000010100000029 +:1015C000000000000000000000000000000000001B +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000010000EA +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200000000000000000000000000000000000BA +:1016300000000000000000000000000000000000AA +:101640000000000101010100000000000000000096 +:10165000000000000000000000000000000000008A +:101660000000000100000000000000000000000079 +:10167000000000000000000000000000000000006A +:101680000000000100000000000000000000000059 +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B0000000000000000000000000010100000028 +:1016C000000000000000000000000000000000001A +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000101010000E7 +:1017000000000000000000000000010000000000D8 +:1017100000000000000000000000000000000000C9 +:1017200000000000000000000000000000000000B9 +:1017300000000000000000000000000000000000A9 +:101740000000000101010101000000000000000094 +:101750000000000000000000000000000000000089 +:101760000000000101010101000000000000000074 +:101770000000000000000000000000000000000069 +:101780000000000101010101000000000000000054 +:101790000000000001010100000000000000000046 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000010100000027 +:1017C0000000000000000000000000000000000019 +:1017D0000000000000000000000000000001000008 +:1017E00000000100010101000000000000000000F5 +:1017F00000000000000000000000010101010000E5 +:1018000000000000000101000200010100000000D2 +:1018100000000000000100000000000000000000C7 +:1018200000000000000000000000000000000000B8 +:1018300000000000000000000000000000000000A8 +:101840000000000101010101000000000000000093 +:101850000000000000000000000000000000000088 +:101860000000000101010101000000000000000073 +:101870000000000000000000000000000000010067 +:101880000000000101010101000000000000000053 +:101890000000000001010100000000000000000045 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000010100000026 +:1018C0000000000000000000000000000000000018 +:1018D0000000000000000000000000000001010006 +:1018E00001000101010101000000000000000000F2 +:1018F00000000000000000000000010101010000E4 +:1019000000000000000101000200010100000100D0 +:1019100000000000000100000000000000000000C6 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000100000000000000A6 +:101940000000010101010101000000000000000091 +:101950000000000000000000000000000000000087 +:101960000000010101010101000000000000000071 +:101970000000000000000000000000000000010066 +:101980000000010101010101000000000000000051 +:101990000000000001010100000000000000000044 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000010100000025 +:1019C0000000000000000000000000000000000017 +:1019D0000000000000000000000000010001010004 +:1019E00001000101010101000000000100010000EF +:1019F00000000000010000000000010101010000E2 +:101A000000000000000101000200020100000100CE +:101A100000000000000100000000000000000000C5 +:101A200000000000000000000000000000000000B6 +:101A300000000000000000000100000000000100A4 +:101A40000000010101010101000000000000000090 +:101A50000000000001010000000000000000010083 +:101A60000000010101010101000000000000000070 +:101A70000000000000000000000000000000010065 +:101A8000010001010101010100000000000000004F +:101A90000000000101010100000000000000000042 +:101AA0000000000001010100000000000000000033 +:101AB0000000000000000000000000010100000024 +:101AC0000000000001010100000000000000000013 +:101AD0000000000000000000000000010001010003 +:101AE00001010101010101000000010100010000EC +:101AF00000000001010000000000010101010101DE +:101B000000010000000101000200020100000100CC +:101B100000000000000100000000000000000000C4 +:101B200000000000010101000000000000000000B2 +:101B300000000000000000000100000000000100A3 +:101B4000000001010101010100000000000000008F +:101B50000000000001010000000000000000010082 +:101B6000000001010101010100000000000000006F +:101B70000000000001010100000000000001010060 +:101B8000010001010101010100000000000000004E +:101B90000000000101010101000000000000000040 +:101BA0000000000001010100000000000000000032 +:101BB0000000000000000000000000010100000023 +:101BC0000000000001010100000000000000000012 +:101BD0000000000000000000000000010101010001 +:101BE00001010101010101010000010100010000EA +:101BF00000000001010000000000010101010101DD +:101C000000010000000101000200020200000100CA +:101C100000000000000100000000000000000000C3 +:101C200000000000010101000000000000000000B1 +:101C3000000000000101010001000000000001019E +:101C4000010101010101010100000000000000008C +:101C5000000000000101010000000000000001017F +:101C6000010101010101010100000000000000006C +:101C7000000000000101010000000000000101015E +:101C8000010101010101010100000000000000004C +:101C9000000000010101010100000000000000003F +:101CA0000000000001010100000000000000000031 +:101CB0000000000000000000000000010100000022 +:101CC0000000000001010100000000000000000011 +:101CD00000000000010101000000010101010100FC +:101CE00001010101010101010001010100010000E8 +:101CF00000000001010000000000010101010101DC +:101D000000010000000101000201020200000101C7 +:101D100000000000000100000100000000000000C1 +:101D200000000000010101000000000000000000B0 +:101D3000000000000101010001000000000101019C +:101D4000010101010101010100000000000000008B +:101D5000000000010101010000000000000101017C +:101D6000010101010101010100000000000000006B +:101D7000000000000101010000000000000101015D +:101D8000010101010101010100000000000000004B +:101D9000000000010101010100000000000000003E +:101DA000000000010101010000000000000000002F +:101DB0000000000000000000000000010100000021 +:101DC000000000010101010000000000000000000F +:101DD00000000000010101000000010101010100FB +:101DE00001010101010101010001010100010000E7 +:101DF00000000001010000000001010101010101DA +:101E000000010000000101000201020200010101C5 +:101E100000000000000100000100000000000000C0 +:101E200000000001010101000000000000000000AE +:101E3000000000000101010101000000000101019A +:101E4000010101010101010100000000000000008A +:101E5000000000010101010100000000000101017A +:101E6000010101010101010100000000000000006A +:101E7000000000000101010000000000000101015C +:101E80000101010101010101000000000000010049 +:101E9000000000010101010100000000000000003D +:101EA000000000010101010100000000000000002D +:101EB0000000000000000000000000010100000020 +:101EC000000000010101010000000000000000000E +:101ED00000000000010101000001010101010100F9 +:101EE00001010101010101010001010100010000E6 +:101EF00000000001010000000001010101010101D9 +:101F000000010000000101000202020200010201C2 +:101F100000000000000200000100000000000000BE +:101F200000000001010101010000000000000000AC +:101F30000000000101010101010000000001010198 +:101F40000101010101010101000000000000000089 +:101F50000000000101010101000000000001010179 +:101F60000101010101010101000000000000000069 +:101F70000000000001010101000000010101010158 +:101F80000101010101010101000000000000010048 +:101F9000000001010101010100000000000000003B +:101FA000000000010101010100000000000000002C +:101FB000000000000000000000000001010001001E +:101FC000000000010101010000000000000000000D +:101FD00000000000010101000001010101010100F8 +:101FE00001010101010101010101010100010000E4 +:101FF00000000001010000000001010101010101D8 +:1020000000010000000101000202020201010202BF +:1020100000000000010200000200000000000000BB +:1020200000000001010101010000000000000000AB +:102030000000000101010101010000000001010197 +:102040000101010101010101000000000000000088 +:102050000000000101010101000101000001010176 +:102060000101010101010101000000000000000068 +:102070000000000101010101000001010101010155 +:102080000101010101010101000000000000010146 +:10209000000001010101010100000000000000003A +:1020A000000000010101010100000000000000002B +:1020B000000000000000000000000001010001001D +:1020C000000000010101010100000000000000000B +:1020D00000000000010101000001010101010100F7 +:1020E00001010101010101010101010100010000E3 +:1020F00000000001010000000001010101010101D7 +:1021000000010000000101000202020201010202BE +:1021100000000000010200000200000000000000BA +:1021200000000001010101010000000000000100A9 +:102130000000000101010101010000010101010194 +:102140000101010101010101000000000000000087 +:102150000000000101010101000101000001010175 +:102160000101010101010101000000000000000067 +:102170000000000101010101000001010101010154 +:102180000101010101010101000000000001010144 +:102190000000010101010101000000000000010137 +:1021A0000000000101010101000000000100000029 +:1021B000000000000000000000000001010001011B +:1021C000000000010101010100000000000000000A +:1021D00000000001010101000101010101010100F4 +:1021E00001010101010101010101010100010000E2 +:1021F00000000001010100010001010101010101D4 +:1022000000010000000101000202020201010202BD +:1022100000000000010200000201000000000000B8 +:1022200000000001010101010000000000000100A8 +:10223000000001010101010102010101010101018F +:102240000101010101010101000000000000000086 +:102250000000010101010101000101000001010173 +:102260000101010101010101000000000000000066 +:102270000000000101010101000101010101010152 +:102280000101010101010101000000000001010143 +:102290000100010101010101000000000001010134 +:1022A0000000010101010101000000000100000027 +:1022B0000000000001010100000000020201010114 +:1022C0000000000101010101000000000000000009 +:1022D00000000001010101000101010101010101F2 +:1022E00001010101010101010101010100010000E1 +:1022F00000000001010100010001010101010101D3 +:1023000000010000000101000202020201010202BC +:1023100000000001010200000201000000000000B6 +:1023200000000001010101010000000000000100A7 +:10233000000001010101010102010101010101018E +:102340000101010101010101000000000000010084 +:102350000000010101010101000101010001010171 +:102360000101010101010101000000000000000065 +:102370000000000101010101000101010101010151 +:102380000101010101010101000000000001010142 +:102390000100010101010101000000000001010133 +:1023A0000100010101010101000000000100000025 +:1023B0000000000001010100000001020201010112 +:1023C0000000000101010101000000000000000008 +:1023D00000000001010101000101010101010101F1 +:1023E00001010101010101010101010100010000E0 +:1023F00000000001010100010001010101010101D2 +:1024000000010000010101000202020202020202B8 +:1024100000000001010200000201000000000100B4 +:1024200000000001010101010000000000000100A6 +:10243000000001010101010102010101010101018D +:102440000101010101010101000000000000010083 +:102450000000010101010101000101010001010170 +:102460000101010101010101000000000000010063 +:102470000000000101010101000101010101010150 +:10248000010101010101010100010100000101013F +:102490000101010101010101000000000001010131 +:1024A0000100010101010101000000000100000024 +:1024B0000000000001010100000001020201010111 +:1024C0000000010101010101000000000001000005 +:1024D00000000001010101010101010101010101EF +:1024E00001010101010101010101010100010000DF +:1024F00000000001010100010001000000000101D5 +:1025000000010001010101000202020202020202B6 +:1025100000000001010200000201000000010100B2 +:1025200000000001010101010001010000000101A2 +:10253000010001010101010102010101010101018B +:102540000101010101010101000000000000010181 +:10255000000001010101010101010101010101016D +:102560000101010101010101000000000000010062 +:10257000000001010101010100010101010101014E +:10258000010101010101010100010101000101013D +:102590000101010101010101000000000001010130 +:1025A0000101010101010101000000000100000022 +:1025B000000000010101010000010102020101010E +:1025C0000000010101010101000000000001010003 +:1025D00000000001010101010101010101010101EE +:1025E00001010101010101010101010100010000DE +:1025F00000000001010100010001000000000101D4 +:1026000000010101010101000202020202020202B4 +:1026100000000002010200010201010000010100AE +:1026200000000001010101010001010000010101A0 +:10263000010001010101010102010101010101018A +:10264000010101010101010100000000000101017F +:10265000000001010101010101010101010101016C +:102660000101010101010101000100000000010060 +:10267000000001010101010100010101010101014D +:10268000010101010101010100010101000101013C +:10269000010101010101010100000000000101012F +:1026A0000101010101010101000000000100000021 +:1026B000000000010101010101010102020101010B +:1026C0000000010101010101000100000001010001 +:1026D00000000001010101010101010101010101ED +:1026E00001010101010101010201010100010000DC +:1026F00000000001010100010000000000000101D4 +:1027000000010101010101000202020202020202B3 +:1027100000000002010200010201010000010100AD +:10272000000000010101010100010100000101019F +:102730000101010101010101020101010101010188 +:10274000010101010101010100010100000101017C +:10275000010001010101010101010101010101016A +:10276000010101020101010100010000000101005D +:10277000000001010101010101010101010101014B +:102780000101010101010101010101010101010139 +:10279000010101010101010100010100000101012C +:1027A000010101010101010100000000010001001F +:1027B000000000010101010101010102020101010A +:1027C00000000101010101010101010000010100FE +:1027D00000000001010101010201010201020101E9 +:1027E00001010101010101010202020200010000D8 +:1027F00000000001010100010000000000000101D3 +:1028000000010101010101000202020202020202B2 +:1028100000000102010200010202010000010100AA +:10282000020000010101010100010100000101019C +:102830000101010101010101020101010101010187 +:102840000101010202020201000101000001010177 +:102850000100010101010101020201010101020166 +:102860000101020202020202000101000001010155 +:102870000000010101010101010101010101020149 +:102880000101010201010101010101010101010137 +:102890000101010102020201000101010101010126 +:1028A000010101010101010100000000010001001E +:1028B0000000000101010101020101020201010108 +:1028C00000000101010101010101010000010100FD +:1028D00000000101010101010202020202020201E3 +:1028E00002010201010101010202020200020000D4 +:1028F00000010001010100010000000000000101D1 +:1029000000010101010101010202020202020202B0 +:1029100000000102010200010202010000010100A9 +:102920000100010102020201000101000001010198 +:102930000101010101010101020101010101020185 +:102940000101020202020202000101000001010174 +:102950000100010101010101020202010102020262 +:102960000202020202020202010101000001010151 +:102970000000010101010101010101010102020147 +:10298000020102020202020202010101010101012F +:102990000101010202020201000101010101010124 +:1029A000010101010101010100000000010001001D +:1029B0000000000101010101020101020201010107 +:1029C00002020101020202010201010101010100F2 +:1029D00000000101010101010202020202020201E2 +:1029E00002020202020202010202020200020000CE +:1029F00000010001010101010000000000000101CF +:102A000000010101010101010202010202020202B0 +:102A100000000102020200010202010000010101A6 +:102A20000102010202020201010101000001010193 +:102A30000101010101010101020201010102020281 +:102A4000020202020202020201010101000101016F +:102A50000100010101010101020202010102020261 +:102A6000020202020202020202010100010101014E +:102A7000010001010202020102020202020202023C +:102A8000020202020202020202020101010102012B +:102A90000101010202020202010101010101010121 +:102AA000010101010101010100000000010101001B +:102AB0000000010101010101020202020201020102 +:102AC00001020102020202010201010101010100F1 +:102AD00000000101010101010202020202020201E1 +:102AE00002020202020202010202020200020000CD +:102AF00001010002020101010000000000000101CB +:102B000000010101010101010102010102020201B2 +:102B100000000102020100010202020100010101A4 +:102B20000101010202020202020201000001010190 +:102B3000010101010202020102020202020202027A +:102B4000020202020202020201010101000101016E +:102B5000010101010202010102020202010202025C +:102B6000020202020202020202020101010101014B +:102B7000010001010202020102020202020202023B +:102B80000202020202020202020202010102020227 +:102B9000010102020202020201010101010101011F +:102BA0000101010102020201000000000101010116 +:102BB00000000101010101010202020202020202FF +:102BC00001010102020202010202010101010101EF +:102BD00000000101020202010202020202020201DD +:102BE00002020202020202020202020200020000CB +:102BF00001010002020101010000020202020202C0 +:102C000000020101010202010102010102020101AF +:102C100000000102020101010202020100020201A0 +:102C2000010101020202020202020201000102018C +:102C30000101010202020202020202020202020277 +:102C4000020202020202020202010101010101016B +:102C50000101010202020201020202020202020258 +:102C6000020202020202020202020101010101014A +:102C70000102010202020202020202020202020236 +:102C80000202020202020202020202020102020225 +:102C9000020102020202020202010101010101011C +:102CA0000101010202020201000000000201010113 +:102CB00000000101010101010202020202020202FE +:102CC00001010102020202020202010101010101ED +:102CD00000000101020202010202020202020201DC +:102CE00002020202020202020202020200020001C9 +:102CF00001010002020101010000020202020202BF +:102D000000020101010202010101010102020101AF +:102D100000000101020101000202020101020201A0 +:102D2000010101020202020202020201000102018B +:102D30000101020202020202020202020202020275 +:102D40000202020202020202020201010101010169 +:102D50000101010202020202020202020202020256 +:102D60000202020202020202020202010101020147 +:102D70000101010202020202020202020202020236 +:102D80000202020202020202020202020202020223 +:102D90000202020202020202020201010102020216 +:102DA000010101020202020200010100020101010F +:102DB00001000101010101010202020202020202FC +:102DC00001010202020202020202020101020101E9 +:102DD00000000102020202010202020202020202D9 +:102DE00002020202020202020202020200020001C8 +:102DF00001010002020101010102020202020202BB +:102E000000020101010202010101010102020101AE +:102E1000000001010201010002020202010202019E +:102E20000101010202020202020202010102020287 +:102E30000201020202020202020202020202020273 +:102E40000202020202020202020202010101020166 +:102E50000101020202020202020202020202020254 +:102E60000202020202020202020202010202020144 +:102E70000101020202020202020202020202020234 +:102E80000202020202020202020202020202020222 +:102E90000202020202020202020202010102020214 +:102EA000020102020202020201010100020101010B +:102EB00001000101010101010202020202020202FB +:102EC00001010202020202020202020202020201E5 +:102ED00000000102020202010202020202020202D8 +:102EE00002020202020202020202020200020001C7 +:102EF00001010002020201020102020202020202B8 +:102F000001020101010202010101010101010101AE +:102F10000100020102010200020202020202020298 +:102F20000201020202020202020202010102020284 +:102F30000202020202020202020202020202020271 +:102F40000202020202020202020202010102020263 +:102F50000101020202020202020202020202020253 +:102F60000202020202020202020202020202020241 +:102F70000101020202020202020202020202020233 +:102F80000202020202020202020202020202020221 +:102F90000202020202020202020202020202020211 +:102FA0000202020202020202020101000201010108 +:102FB00001000101010101010202020202020202FA +:102FC00001010202020202020202020202020201E4 +:102FD00002000102020202020202020202020202D4 +:102FE00002020202020202020202020201020001C5 +:102FF00001010002020201020202020202020202B6 +:1030000001020101010202010101010101010101AD +:103010000200020102010200020202020202020296 +:103020000202020202020202020202020102020281 +:103030000202020202020202020202020202020270 +:103040000202020202020202020202020102020261 +:103050000201020202020202020202020202020251 +:103060000202020202020202020202020202020240 +:103070000201020202020202020202020202020231 +:103080000202020202020202020202020202020220 +:103090000202020202020202020202020202020210 +:1030A0000202020202020202020101010201010106 +:1030B00001000101020202010202020202020202F6 +:1030C00002010202020202020202020202020201E2 +:1030D00001000202020202020202020202020202D3 +:1030E00002020202020202020202020201020101C3 +:1030F00001020002020201020202020202020202B4 +:1031000001020101010202010101010101010101AC +:103110000201020102010100020202020202020295 +:10312000020202020202020202020202020202027F +:10313000020202020202020202020202020202026F +:10314000020202020202020202020202020202025F +:103150000201020202020202020202020202020250 +:10316000020202020202020202020202020202023F +:103170000201020202020202020202020202020230 +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A0000202020202020202020201010201020103 +:1031B00001010102020202010202020202020202F3 +:1031C00002020202020202020202020202020202DF +:1031D00001020202020202020202020202020202D0 +:1031E00002020202020202020202020201020101C2 +:1031F00002020002020201020202020202020202B2 +:1032000001020202020202010101010101010101A8 +:103210000102020101010100020202020202020295 +:10322000020202020202020202020202020202027E +:10323000020202020202020202020202020202026E +:10324000020202020202020202020202020202025E +:10325000020202020202020202020202020202024E +:10326000020202020202020202020202020202023E +:10327000020202020202020202020202020202022E +:10328000020202020202020202020202020202021E +:10329000020202020202020202020202020202020E +:1032A0000202020202020202020202010202020100 +:1032B00001010102020202020202020202020202F1 +:1032C00002020202020202020202020202020202DE +:1032D00001010202020202020202020202020202D0 +:1032E00002020202020202020202020202020102BF +:1032F00002020002020202020202020202020202B0 +:1033000001020202020202000101010101010101A8 +:103310000101020101010100020202020202020295 +:10332000020202020202020202020202020202027D +:10333000020202020202020202020202020202026D +:10334000020202020202020202020202020202025D +:10335000020202020202020202020202020202024D +:10336000020202020202020202020202020202023D +:10337000020202020202020202020202020202022D +:10338000020202020202020202020202020202021D +:10339000020202020202020202020202020202020D +:1033A00002020202020202020202020102020202FE +:1033B00001010202020202020202020202020202EF +:1033C00002020202020202020202020202020202DD +:1033D00001010202020202020202020202020202CF +:1033E00002020202020202020202020202020102BE +:1033F00002020002020202020202020202020202AF +:1034000001020202020202000001000001010100AB +:103410000101010101000100000202020202020298 +:10342000020202020202020202020202020202027C +:10343000020202020202020202020202020202026C +:10344000020202020202020202020202020202025C +:10345000020202020202020202020202020202024C +:10346000020202020202020202020202020202023C +:10347000020202020202020202020202020202022C +:10348000020202020202020202020202020202021C +:10349000020202020202020202020202020202020C +:1034A00002020202020202020202020202020202FC +:1034B00002010202020202020202020202020202ED +:1034C00002020202020202020202020202020202DC +:1034D00002010202020202020202020202020202CD +:1034E00002020202020202020202020202020202BC +:1034F00002020002020202020202020202020202AE +:1035000001020202020202000000000001010000AC +:103510000101010001000100010202020202020297 +:10352000020202020202020202020202020202027B +:10353000020202020202020202020202020202026B +:10354000020202020202020202020202020202025B +:10355000020202020202020202020202020202024B +:10356000020202020202020202020202020202023B +:10357000020202020202020202020202020202022B +:10358000020202020202020202020202020202021B +:10359000020202020202020202020202020202020B +:1035A00002020202020202020202020202020202FB +:1035B00002010202020202020202020202020202EC +:1035C00002020202020202020202020202020202DB +:1035D00002020202020202020202020202020202CB +:1035E00002020202020202020202020202020202BB +:1035F00002020002020202020202020202020202AD +:1036000002020202020202020000000000000000AA +:103610000101010001000100010202020202020296 +:10362000020202020202020202020202020202027A +:10363000020202020202020202020202020202026A +:10364000020202020202020202020202020202025A +:10365000020202020202020202020202020202024A +:10366000020202020202020202020202020202023A +:10367000020202020202020202020202020202022A +:10368000020202020202020202020202020202021A +:10369000020202020202020202020202020202020A +:1036A00002020202020202020202020202020202FA +:1036B00002020202020202020202020202020202EA +:1036C00002020202020202020202020202020202DA +:1036D00002020202020202020202020202020202CA +:1036E00002020202020202020202020202020202BA +:1036F00002020002020202020202020202020202AC +:1037000002020202020202020000000000000000A9 +:1037100001010100010000000100000000000000A4 +:103720000000000000000000020202020202020289 +:103730000202020202020202020202020202020269 +:103740000202020202020202020202020202020259 +:103750000202020202020202020202020202020249 +:103760000202020202020202020202020202020239 +:103770000202020202020202020202020202020229 +:103780000202020202020202020202020202020219 +:103790000202020202020202020202020202020209 +:1037A00002020202020202020202020202020202F9 +:1037B00002020202020202020202020102020202EA +:1037C00002020202020202020202020202020202D9 +:1037D00002020202020202020202020202020202C9 +:1037E00002020202020202020202020202020202B9 +:1037F00002020102020202020202020202020202AA +:1038000002020202020202020000000000000000A8 +:10381000000001000000000001010101010101019F +:103820000101010101010101020202020202020280 +:103830000202020202020202020202020202020268 +:103840000202020202020202020202020202020258 +:103850000202020202020202020202020202020248 +:103860000202020202020202020202020102020239 +:103870000202020202020202020202020202020228 +:103880000202020202020202010101010101010120 +:103890000101010101010101020202020202020210 +:1038A00002020202020202020202020202020202F8 +:1038B00002020202020202020101010101010101F0 +:1038C00001010101010101010202020202020202E0 +:1038D00002020202020202020202020202020202C8 +:1038E00002020202020202020202020202020202B8 +:1038F00002020202020202020202020202020202A8 +:1039000002020202020202020100010100000001A3 +:10391000000000000001000001010101010101019E +:103920000101010101010101010101010101010187 +:103930000101010101010101010202020202020270 +:103940000202020202020202020202020202020257 +:10395000020202020202020201010101010101014F +:103960000101010101010101010101010201010146 +:10397000010101010101010102020202020202022F +:103980000202020202020202020202020202020217 +:103990000202020202020202020202020202020207 +:1039A00002020202020202020202020202020202F7 +:1039B00002020202020202020202020201020202E8 +:1039C00002020202020202020202020202020202D7 +:1039D00002020202020202020202020202020202C7 +:1039E00002020202020202020202020202020202B7 +:1039F00002020202020202020202020202020202A7 +:103A000002020202020202020101010100000101A0 +:103A1000000000010001000001010101010101019C +:103A2000010101010101010102020202020202027E +:103A3000020202020202020202010101010101016D +:103A4000010101010101010102020202020202025E +:103A50000202020202020202020202020202020246 +:103A60000202020202020202020202020002020238 +:103A70000202020202020202020202020202020226 +:103A80000202020202020202000000000000000026 +:103A90000000000000000000020202020202020216 +:103AA00002020202020202020202020202020202F6 +:103AB00002020202020202020000000202000000F2 +:103AC00000000000000000000000020000020202EE +:103AD00002020202020202020202020202020202C6 +:103AE00002020202020202020202020202020202B6 +:103AF00002020202020202020202020202020202A6 +:103B0000020202020202020201010101010101019D +:103B1000000000010001000001010101010101019B +:103B20000101010101010101010101010101010185 +:103B3000010101010101010101020202020202026E +:103B4000020202020202020201010101010101015D +:103B5000010101010101010100000000000000005D +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000020202020202020205 +:103BB00002020202020202020000000002000000F3 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000202020202020202D5 +:103BE00002020202020202020101010101010101BD +:103BF00001010101010101010202020202020202AD +:103C0000020202020202020201010101010101019C +:103C10000000000100010101010101010101010198 +:103C20000101010101010101010101010101010184 +:103C30000101010101010101010101010101010174 +:103C40000101010101010101010101010101010164 +:103C50000101010101010101010101010101010154 +:103C6000010101010101010100000000000000004C +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000020202020202020204 +:103CB00002020202020202020000000000000000F4 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000202020202020202C4 +:103CF00002020202020202020202020202020202A4 +:103D0000020202020202020201010101010101019B +:103D10000101000101010101010101010101010194 +:103D20000101010101010101010101010101010183 +:103D30000101010101010101010101010101010173 +:103D40000101010101010101010101010101010163 +:103D50000101010101010101010101010101010153 +:103D60000101010101010101010101010101010143 +:103D70000101010101010101010101010101010133 +:103D8000010101010101010100000000000000002B +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000020202020002020205 +:103DB00002020202020202020000000000000000F3 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000202020202020202B3 +:103E0000020202020202020201010101010101019A +:103E10000101010101010101010101010101010192 +:103E20000101010101010101010101010101010182 +:103E30000101010101010101010101010101010172 +:103E40000101010101010101010101010101010162 +:103E50000101010101010101010101010101010152 +:103E60000101010101010101010101010101010142 +:103E70000101010101010101010101010101010132 +:103E80000101010101010101010101010101010122 +:103E90000101010101010101010101010101010112 +:103EA0000101010101010101010101010101010102 +:103EB00001010101010101010000000000000000FA +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000101010101010101DA +:103EE00001010101010101010000000000000000CA +:103EF00000000000000000000202020202020202B2 +:103F00000202020202020202010101010101010199 +:103F10000101010101010101010101010101010191 +:103F20000101010101010101010101010101010181 +:103F30000101010101010101010101010101010171 +:103F40000101010101010101010101010101010161 +:103F50000101010101010101010101010101010151 +:103F60000101010101010101010101010101010141 +:103F70000101010101010101010101010101010131 +:103F80000101010101010101010101010101010121 +:103F90000101010101010101010101010101010111 +:103FA0000101010101010101010101010101010101 +:103FB00001010101010101010101010101010101F1 +:103FC00001010101010101010101010101010101E1 +:103FD00001010101010101010101010101010101D1 +:103FE00001010101010101010101010101010101C1 +:103FF00001010101010101010000000000000000B9 +:1040000000000000000000000101010101010101A8 +:104010000101010101010101010101010101010190 +:104020000101010101010101010101010101010180 +:104030000101010101010101010101010101010170 +:104040000101010101010101010101010101010160 +:104050000101010101010101010101010101010150 +:104060000101010101010101010101010101010140 +:104070000101010101010101010101010101010130 +:104080000101010101010101010101010101010120 +:104090000101010101010101010101010101010110 +:1040A0000101010101010101010101010101010100 +:1040B00001010101010101010101010101010101F0 +:1040C00001010101010101010101010101010101E0 +:1040D00001010101010101010101010101010101D0 +:1040E00001010101010101010101010101010101C0 +:1040F00001010101010101010000000000000000B8 +:1041000000000000000000000101010101010101A7 +:104110000101010101010101000000000000000097 +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000002020202020202025F +:10415000020202020202020202020202020202023F +:10416000020202020202020202020202020202022F +:10417000020202020202020202020202020202021F +:10418000020202020202020202020202020202020F +:1041900002020202020202020202020202020202FF +:1041A00002020202020202020202020202020202EF +:1041B00002020202020202020202020202020202DF +:1041C00002020202020202020202020202020202CF +:1041D00002020202020202020202020202020202BF +:1041E00002020202020202020202020202020202AF +:1041F00002020202020202020000000000000000AF +:1042000000000000000000000101010101010101A6 +:104210000101010101010101000000000000000096 +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000202020202020202CE +:1042E00002020202020202020202020202020202AE +:1042F00002020202020202020000000000000000AE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:10440000000000000000000030000000000000007C +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000101007A +:10444000000000000000000000000000000001006B +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000010000000000000000000000009A +:10452000000000000000000000000000000000008B +:104530000000000000000000000000000001010079 +:10454000000000000000000000000000000001006A +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:104590000000000000000000000001000001010117 +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000010100D9 +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:104610000000000100000000000000000001000098 +:10462000000000000000000000000000000000008A +:104630000100000000000000000001000001010175 +:104640000000000000000000000000000001010167 +:10465000000000000000000000000000000000005A +:104660000000000000000000000000000001010048 +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:104690000000000000000001000001010101010113 +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000010100D8 +:1046E00000000000000000000000010000010000C8 +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000100000000000000000001000097 +:104720000000000000000000000000000000000089 +:104730000100000000000001000001010101010171 +:104740000000000000000000000000010001010165 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000001010047 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000001000001010101010112 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000010000010100D6 +:1047E00000000001010001010000010001010000C2 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000100000000000000000001000096 +:104820000000000000000000000000000000000088 +:104830000100000000000001000001010101010170 +:104840000000000000000000000001010001010163 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000001010145 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:10489000000000000000010101000101010101010F +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000010000010101010100D2 +:1048E00000000001010001010000010001010100C0 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000100000100000000000001000094 +:104920000000000000000000000000000000000087 +:10493000010000000000010100000101010101016E +:104940000000000000000000000001010101010161 +:104950000000000000000000000000000000010056 +:104960000000000000000000000000010101010142 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:10499000000000000001010101000101010101010D +:1049A0000000000000000000000000000000010006 +:1049B00000000000000000000000000000010101F4 +:1049C00000000000000000010000000101000000E4 +:1049D00000000000000000010000010101010101D0 +:1049E00000000001010001010000010101010100BE +:1049F00001000000000000000000000000000000B6 +:104A000000000000000000000000000000000000A6 +:104A10000000000100000100000000000001000093 +:104A20000000000000000000000000000000000086 +:104A3000010000000000010100000101010101016D +:104A40000000000000000000000001010101010160 +:104A50000000000000000000000000000000010055 +:104A60000000000000000000000001010101010140 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A9000000000000101010101010101010101010A +:104AA0000000000000000000000000000000010005 +:104AB00000000000000000000000000101010101F1 +:104AC00000000000000000010000010101010101DF +:104AD00000000000000001010000010101010101CE +:104AE00000000001010101010000010101010101BB +:104AF00001000000000000000000000000000000B5 +:104B000000000000000000000000000000000000A5 +:104B10000000000100000100000000000001000092 +:104B20000000000000000000000000000001010083 +:104B3000010000000000010101010101010101016A +:104B4000000000000000010100000101010101015D +:104B50000000000000000000000000000001010053 +:104B6000000000000000010100000101010101013D +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000001010101010101010101010109 +:104BA0000000000000000000000000000001010003 +:104BB00000000000000000000000000101010101F0 +:104BC00000000000000001010000010101010101DD +:104BD00000000000000001010000010101010101CD +:104BE00000000001010101010000010101010101BA +:104BF00001000000000000000000000000000000B4 +:104C000000000000000000000000000000000000A4 +:104C10000000000100000100000000000001000091 +:104C20000000000000000000000000000001010082 +:104C30000100000000010101010101010101010168 +:104C4000000000000000010100000101010101015C +:104C50000000000000000000000000000001010052 +:104C6000000000000000010100000101010101013C +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000101010101010101010101010107 +:104CA0000000000000000000000000010101010000 +:104CB00000000000000001010101000101010101EB +:104CC00000000000000001010000010101010101DC +:104CD00000000001010001010101010101010101C8 +:104CE00000000001010101010000010101010101B9 +:104CF00001000000000000000000000000000000B3 +:104D000000000000000000000000000000000000A3 +:104D10000000000100000100000000000001000090 +:104D20000000000000000000000000000001010180 +:104D30000100000101010101010101010101010165 +:104D40000000000000000101010101010101010159 +:104D50000000000000000000000000000001010150 +:104D6000000000000000010101000101010101013A +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000101010101010101010101010106 +:104DA00000000000000000000000010101010101FD +:104DB00000000000000101010101010101010101E8 +:104DC00000000000010001010000010101010101DA +:104DD00000000001010101010101010101010101C6 +:104DE00000010001010101010000010101010101B7 +:104DF00001000000000000000000000000000001B1 +:104E000000000000000000000000000000000000A2 +:104E1000000000020001010000000000000100008D +:104E2000000000000000000000000001010101017D +:104E30000100010101010101010101010101010163 +:104E40000000000000010101010101010101010157 +:104E5000000000000000000000000001010101014D +:104E60000000000000000101010001010101010139 +:104E70000000000000000000000000000001010030 +:104E80000000000000000000000000000000000022 +:104E90000000000101010101010101010101010105 +:104EA00000000000000001010000010101010101FA +:104EB00000000000010101010101010101010101E6 +:104EC00000000000010101010000010101010101D8 +:104ED00000000001010101010101010101010101C5 +:104EE00000010101010101010000010101010101B5 +:104EF00001000000000000000000000000000001B0 +:104F000000000000000000000000000000000000A1 +:104F10000001000201010100010000000001000089 +:104F2000000000000000000000000001010101017C +:104F30000100010101010101010101010101010162 +:104F40000001000101010101010101010101010153 +:104F5000000000000000000000000101010101014B +:104F60000000000101000101010101010101010135 +:104F7000000000000000000000000000000101002F +:104F80000000000000000000000000000000000021 +:104F90000000010101010101010101010101010103 +:104FA00000000000000001010000010101010101F9 +:104FB00000000000010101010101010101010101E5 +:104FC00000000001010101010101010101010101D4 +:104FD00000000101010101010101010101010101C3 +:104FE00000010101010101010001010101010101B3 +:104FF00001000000000000000000000000000001AF +:1050000000000000000000000000000000000000A0 +:105010000101000201010100010000000001010086 +:10502000000000000000000000000001010101017B +:105030000100010101010101010101010101010161 +:105040000001000101010101010101010101010152 +:10505000000000000000000000000101010101014A +:105060000000000101010101010101010101010133 +:10507000000000000000000000000000000101012D +:10508000000000000000000000000000000101001E +:105090000001010101010101010101010101010101 +:1050A00000000000000001010100010101010101F7 +:1050B00000010000010101010101010101010101E3 +:1050C00000000001010101010101010101010101D3 +:1050D00000010101010101010101010101010101C1 +:1050E00001010101010101010001010101010101B1 +:1050F00001000000000000000000000000000001AE +:10510000000000000000000000000000000000009F +:105110000101000201010100010000000001010085 +:10512000000000000000000000000001010101017A +:10513000010101010101010101010101010101015F +:105140000001000101010101010101010101010151 +:105150000000000000000000000001010101010149 +:105160000000000101010101010101010101010132 +:10517000000000000000000000000001010101012A +:10518000000000000000000000000000000101001D +:105190000001010101010101010101010101010100 +:1051A00000000000000101010100010101010101F5 +:1051B00000010100010101010101010101010101E1 +:1051C00000010001010101010101010101010101D1 +:1051D00000010101010101010101010101010101C0 +:1051E00001010101010101010001010101010101B0 +:1051F00001000000000000000000000000000001AD +:10520000000000000000000000000000000000009E +:105210000201000201010200010000000001010082 +:105220000000000000000101000000010101010177 +:10523000020101010101010101010101010101015D +:10524000010101010101010101010101010101014E +:105250000000000000000101000001010101010146 +:105260000000010101010101010101010101010130 +:105270000000000000000000000000010101010129 +:10528000000000000000000000000000000101001C +:1052900000010101010101010101010101010101FF +:1052A00000000001010101010101010101010101F1 +:1052B00000010101010101010101010101010101DF +:1052C00000010101010101010101010101010101CF +:1052D00000010101010101010101010101010101BF +:1052E00001010101010101010001010101010101AF +:1052F00001000000000000000100000000000001AB +:10530000000000000000000000000000000000009D +:10531000020200020202020001000000000201007D +:105320000100000000000101000001010101010174 +:10533000020101010101010101010101010101015C +:10534000010101010101010101010101010101014D +:105350000000000000000101000001010101010145 +:10536000000101010101010101010101010101012E +:105370000000000000000000000000010101010128 +:10538000000000000000000000000000000101001B +:1053900001010101010101010101010101010101FD +:1053A00000000001010101010101010101010101F0 +:1053B00000010101010101010101010101010101DE +:1053C00000010101010101010101010101010101CE +:1053D00000010101010101010101010101010101BE +:1053E00001010101010101010001010101010101AE +:1053F00002000100000000000100000000000001A8 +:10540000000000000000000000000000000000009C +:10541000020200020202020002000000000201007B +:105420000101000000000101000001010101010172 +:10543000020101010101010101010101010101015B +:10544000010101010101010101010101010101014C +:105450000000000000000101000001010101010144 +:10546000010101010101010101010101010101012C +:105470000000000000000000000001010101010126 +:105480000000000000000000000000000001010119 +:1054900001010101010101010101010101010101FC +:1054A00000010001010101010101010101010101EE +:1054B00000010101010101010101010101010101DD +:1054C00001010101010101010101010101010101CC +:1054D00000010101010101010101010101010101BD +:1054E00001010101010101010001010101010101AD +:1054F00002000100000000000101000100000001A5 +:10550000000000000000000000000000000000009B +:10551000020200020202020002000000000201007A +:105520000101000000000101000001010101010171 +:10553000020101010101010101010101010101015A +:10554000010101010101010101010101010101014B +:105550000000000000000101000001010101010143 +:10556000010101010101010101010101010101012B +:105570000000000000000000000001010101010125 +:105580000000000000000000000000010101010116 +:1055900001010101010101010101010101010101FB +:1055A00000010101010101010101010101010101EC +:1055B00000010101010101010101010101010101DC +:1055C00001010101010101010101010101010101CB +:1055D00000010101010101010101010101010101BC +:1055E00001010101010101010001010101010101AC +:1055F00002000100000000000101000100000101A3 +:105600000000000000000000000000000001010098 +:105610000202010202020200020000000002010177 +:10562000010100000000010100010101010101016F +:105630000201010101010101010101010101010159 +:10564000010101010101010101010101010101014A +:10565000000100010100010101000101010101013E +:10566000010101010101010101010101010101012A +:105670000000000000000000000001010101010124 +:105680000000000000000000000000010101010115 +:1056900001010101010101010101010101010101FA +:1056A00000010101010101010101010101010101EB +:1056B00000010101010101010101010101010101DB +:1056C00001010101010101010101010101010101CA +:1056D00000010101010101010101010101010101BB +:1056E00001010102020101010001010101010101A9 +:1056F00002000100000001000101000101000101A0 +:105700000000000000000000000000000001010097 +:105710000202010202020200020000010002010175 +:10572000020101000000010100010101010101016C +:105730000201010101010102010102010102020154 +:105740000101010101010101010101010101020148 +:10575000000101010101010101000101010101013B +:105760000101010101010101010101010101010129 +:105770000000000000000101000001010101010121 +:105780000000000000000000000000010101010114 +:1057900001010101010101020101020101010101F7 +:1057A00001010101010101010101010101010101E9 +:1057B00001010101010101010101010101010101D9 +:1057C00001010101010101020101010101010101C8 +:1057D00001010101010101010101010101010101B9 +:1057E00001010102020102020001020101010101A5 +:1057F000020001000001010001010001010001019E +:105800000000020000000000000002000001010191 +:105810000202020202020200020000010002010173 +:10582000020101000000010100010101010101016B +:10583000020101010101020201010202020202024F +:105840000101010101010101010102020102020243 +:105850000001010101010101010101010101010139 +:105860000101010101010101010101010102020126 +:105870000000000000000101000001010101010120 +:105880000000000000000000000000010101010113 +:1058900001010101020202020201020202020202ED +:1058A00001010101010101010101010101010101E8 +:1058B00001010101010101010101010101010101D8 +:1058C00001010101020102020101020202010101C2 +:1058D00001010101010101020101020101020201B4 +:1058E000020201020202020200010201020201019F +:1058F000020001000101010001010001010001019C +:10590000000201000000000002020101010101018A +:105910000202020202020200020000010002010172 +:105920000201010000010101000101010102020167 +:105930000201020202020202020202020202020248 +:10594000020201010101020201010202020202023D +:105950000101010101010101010101010101020136 +:10596000010101010101020201010202020202021F +:10597000000000000000010101000101010101011E +:105980000000000000000000000000010101010112 +:1059900001010102020202020202020202020202EA +:1059A00001010101010101010101010101010101E7 +:1059B00001010101010101010101010101010101D7 +:1059C00002020102020202020101020202020202BA +:1059D00001010102020102020101020202020201AE +:1059E000020202020202020200010202020202019B +:1059F000020001000101010001010001010001019B +:105A0000000101000002000001010101010101018A +:105A10000202020202020200020000010002020170 +:105A20000202010101010101000101020202020260 +:105A30000202020202020202020202020202020246 +:105A40000202010202020202020202020202020237 +:105A50000101010101010101010101010102020134 +:105A6000020101020201020202010202020202021A +:105A7000010000000001010101000101010101011B +:105A8000010000000000000000000101010101010F +:105A900002020202020202020202020202020202E6 +:105AA00001010101010101010101010101010101E6 +:105AB00001010101010101010101010101010101D6 +:105AC00002020202020202020202020202020202B6 +:105AD00001020202020202020202020202020202A7 +:105AE0000202020202020202000102020202020299 +:105AF0000201020001010100010100010100010297 +:105B00000001010002010101010101010101010186 +:105B1000020202020202020102010001000202006E +:105B2000020201010101020200010102020202025D +:105B30000202020202020202020202020202020245 +:105B40000202020202020202020202020202020235 +:105B5000010101010101010101010202020202022F +:105B60000202020202020202020202020202020215 +:105B70000101000101010101010101010101010116 +:105B8000010100000000010000000101010101010C +:105B900002020202020202020202020202020202E5 +:105BA00001010101010101010101010101010201E4 +:105BB00001020101020202020202010202020202C9 +:105BC00002020202020202020202020202020202B5 +:105BD00001020202020202020202020202020202A6 +:105BE0000202020202020202000202020202020297 +:105BF0000201020001010100020101010100010294 +:105C00000001010001010101010101010101010186 +:105C1000020202020202020102020002000202006B +:105C2000020202010101020200010202020202025A +:105C30000202020202020202020202020202020244 +:105C40000202020202020202020202020202020234 +:105C5000020201010101020201010202020202022A +:105C60000202020202020202020202020202020214 +:105C70000101010101010101010101010102020112 +:105C80000201010000000100000001010102020107 +:105C900002020202020202020202020202020202E4 +:105CA00001010101010102020101020202020201DD +:105CB00001020201020202020202020202020202C6 +:105CC00002020202020202020202020202020202B4 +:105CD00002020202020202020202020202020202A4 +:105CE0000202020202020202000202020202020296 +:105CF0000201020001010100020201010100010292 +:105D00000001010101010101010101010101010184 +:105D10000202020202020202020200020002020069 +:105D20000202020101010202000202020202020258 +:105D30000202020202020202020202020202020243 +:105D40000202020202020202020202020202020233 +:105D50000202020202010202010102020202020226 +:105D60000202020202020202020202020202020213 +:105D7000020101010101010101010102020202020D +:105D80000201010100000101000001010102020104 +:105D900002020202020202020202020202020202E3 +:105DA00002020102020202020201020202020202D5 +:105DB00002020202020202020202020202020202C3 +:105DC00002020202020202020202020202020202B3 +:105DD00002020202020202020202020202020202A3 +:105DE0000202020202020202000202020202020295 +:105DF000020202000202020002020102010001028C +:105E00000000000101010101010101010101010185 +:105E10000202020202020202020200020002020068 +:105E20000202020202020202010202020202020253 +:105E30000202020202020202020202020202020242 +:105E40000202020202020202020202020202020232 +:105E50000202020202020202020102020202020223 +:105E60000202020202020202020202020202020212 +:105E7000020101010101010101010202020202020B +:105E800002020101000101010000010202020202FE +:105E900002020202020202020202020202020202E2 +:105EA00002020202020202020202020202020202D2 +:105EB00002020202020202020202020202020202C2 +:105EC00002020202020202020202020202020202B2 +:105ED00002020202020202020202020202020202A2 +:105EE0000202020202020202000202020202020294 +:105EF0000202020102020201020201020200020287 +:105F00000000000101010101010101010100000186 +:105F10000202020202020202020200020002020067 +:105F20000202020202020202010202020202020252 +:105F30000202020202020202020202020202020241 +:105F40000202020202020202020202020202020231 +:105F50000202020202020202020202020202020221 +:105F60000202020202020202020202020202020211 +:105F70000202010101010202010102020202020207 +:105F800002020201010101010000010202020202FB +:105F900002020202020202020202020202020202E1 +:105FA00002020202020202020202020202020202D1 +:105FB00002020202020202020202020202020202C1 +:105FC00002020202020202020202020202020202B1 +:105FD00002020202020202020202020202020202A1 +:105FE0000202020202020202000202020202020293 +:105FF0000202020102020201020201020200020286 +:106000000000000000000000000000000000000090 +:10601000020202010101020201020002000202006A +:106020000202020202020202010202020202020251 +:106030000202020202020202020202020202020240 +:106040000202020202020202020202020202020230 +:106050000202020202020202020202020202020220 +:106060000202020202020202020202020202020210 +:106070000202020202020202020102020202020201 +:1060800002020202010102010000020202020202F7 +:1060900002020202020202020202020202020202E0 +:1060A00002020202020202020202020202020202D0 +:1060B00002020202020202020202020202020202C0 +:1060C00002020202020202020202020202020202B0 +:1060D00002020202020202020202020202020202A0 +:1060E0000202020202020202000202020202020292 +:1060F0000202020202020201020202020200020283 +:10610000010000000000000000000000000000008E +:10611000010102010101010201020002000202006C +:10612000020202020202020202020202020202024F +:10613000020202020202020202020202020202023F +:10614000020202020202020202020202020202022F +:10615000020202020202020202020202020202021F +:10616000020202020202020202020202020202020F +:1061700002020202020202020202020202020202FF +:1061800002020202020202020100020202020202F2 +:1061900002020202020202020202020202020202DF +:1061A00002020202020202020202020202020202CF +:1061B00002020202020202020202020202020202BF +:1061C00002020202020202020202020202020202AF +:1061D000020202020202020202020202020202029F +:1061E0000202020202020202010202020202020290 +:1061F0000202020202020202020202020201020280 +:10620000010000000000000000000000000000008D +:10621000010101010101010201010102000102006D +:10622000020202020202020202020202020202024E +:10623000020202020202020202020202020202023E +:10624000020202020202020202020202020202022E +:10625000020202020202020202020202020202021E +:10626000020202020202020202020202020202020E +:1062700002020202020202020202020202020202FE +:1062800002020202020202020100020202020202F1 +:1062900002020202020202020202020202020202DE +:1062A00002020202020202020202020202020202CE +:1062B00002020202020202020202020202020202BE +:1062C00002020202020202020202020202020202AE +:1062D000020202020202020202020202020202029E +:1062E000020202020202020201020202020202028F +:1062F000020202020202020202020202020102027F +:10630000020000000000000000000000000000008B +:10631000010101010101010101010101010102006D +:10632000020202020202020202020202020202024D +:10633000020202020202020202020202020202023D +:10634000020202020202020202020202020202022D +:10635000020202020202020202020202020202021D +:10636000020202020202020202020202020202020D +:1063700002020202020202020202020202020202FD +:1063800002020202020202020201020202020202EE +:1063900002020202020202020202020202020202DD +:1063A00002020202020202020202020202020202CD +:1063B00002020202020202020202020202020202BD +:1063C00002020202020202020202020202020202AD +:1063D000020202020202020202020202020202029D +:1063E000020202020202020201020202020202028E +:1063F000020202020202020202020202020102027E +:10640000020000000000000000000000000000008A +:10641000010101010101010101010101010101006D +:10642000020202020202020202020202020202024C +:10643000020202020202020202020202020202023C +:10644000020202020202020202020202020202022C +:10645000020202020202020202020202020202021C +:10646000020202020202020202020202020202020C +:1064700002020202020202020202020202020202FC +:1064800002020202020202020202020202020202EC +:1064900002020202020202020202020202020202DC +:1064A00002020202020202020202020202020202CC +:1064B00002020202020202020202020202020202BC +:1064C00002020202020202020202020202020202AC +:1064D000020202020202020202020202020202029C +:1064E000020202020202020202020202020202028C +:1064F000020202020202020202020202020202027C +:106500000202020000000000000000000000000085 +:10651000010101010101010101010201020101006A +:10652000020202020202020202020202020202024B +:10653000020202020202020202020202020202023B +:10654000020202020202020202020202020202022B +:10655000020202020202020202020202020202021B +:10656000020202020202020202020202020202020B +:1065700002020202020202020202020202020202FB +:1065800002020202020202020202020202020202EB +:1065900002020202020202020202020202020202DB +:1065A00002020202020202020202020202020202CB +:1065B00002020202020202020202020202020202BB +:1065C00002020202020202020202020202020202AB +:1065D000020202020202020202020202020202029B +:1065E000020202020202020202020202020202028B +:1065F000020202020202020202020202020202027B +:106600000202020000000000000000000002020080 +:10661000010101010101010101010201010101006A +:10662000000202020202020202020202020202024C +:10663000020202020202020202020202020202023A +:10664000020202020202020202020202020202022A +:10665000020202020202020202020202020202021A +:10666000020202020202020202020202020202020A +:1066700002020202020202020202020202020202FA +:1066800002020202020202020202020202020202EA +:1066900002020202020202020202020202020202DA +:1066A00002020202020202020202020202020202CA +:1066B00002020202020202020202020202020202BA +:1066C00002020202020202020202020202020202AA +:1066D000020202020202020202020202020202029A +:1066E000020202020202020202020202020202028A +:1066F000020202020202020202020202020202027A +:106700000202020202020202020202020202020269 +:106710000000010000000001000101010101010071 +:106720000000000000000000000000000000000069 +:106730000202020202020202020202020202020239 +:106740000202020202020202020202020202020229 +:106750000202020202020202020202020202020219 +:106760000202020202020202020202020202020209 +:1067700002020202020202020202020202020202F9 +:1067800001010101010101010101010101010101F9 +:1067900002020202020202020202020202020202D9 +:1067A00002020202020202020202020202020202C9 +:1067B00002020202020202020202020202020202B9 +:1067C00002020202020202020202020202020202A9 +:1067D0000202020202020202020202020202020299 +:1067E0000202020202020202020202020202020289 +:1067F0000202020202020202020202020202020279 +:106800000202020202020202020202020202020268 +:106810000000000000000000000001000100010075 +:106820000100000000000000000000000000000067 +:106830000202020202020202020202020202020238 +:106840000202020202020202020202020202020228 +:106850000101010101010101010101010101010128 +:106860000202020202020202020202020202020208 +:1068700002020202020202020202020202020202F8 +:1068800002020202020202020202020202020202E8 +:1068900002020202020202020202020202020202D8 +:1068A00002020202020202020202020202020202C8 +:1068B00002020202020202020202020202020202B8 +:1068C00001010101010101010101010101010101B8 +:1068D0000202020202020202020202020202020298 +:1068E0000202020202020202020202020202020288 +:1068F0000000000000000000000000000000000098 +:106900000202020202020202020202020202020267 +:106910000000000000000000000001000100000075 +:106920000101010101010101010101010101010157 +:106930000102020202020202020202020202020238 +:106940000101010101010101010101010101010137 +:106950000202020202020202020202020202020217 +:106960000202020202020202020202020202020207 +:1069700002020202020202020202020202020202F7 +:106980000000000000000000000000000000000007 +:1069900002020202020202020202020202020202D7 +:1069A00002020202020202020202020202020202C7 +:1069B00002020202020202020202020202020202B7 +:1069C00002020202020202020202020202020202A7 +:1069D0000202020202020202020202020202020297 +:1069E0000202020202020202020202020202020287 +:1069F0000000000000000000000000000000000097 +:106A00000202020202020202020202020202020266 +:106A10000000000000000000000000000000000076 +:106A20000101010101010101010101010101010156 +:106A30000101010101010101010101010101010146 +:106A40000202020202020202020202020202020226 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900001010101010101010101010101010101E6 +:106AA00002020202020202020202020202020202C6 +:106AB00002020202020202020202020202020202B6 +:106AC00000000000000000000000000000000000C6 +:106AD0000202020202020202020202020202020296 +:106AE0000202020202020202020202020202020286 +:106AF0000000000000000000000000000000000096 +:106B00000202020202020202020202020202020265 +:106B10000000000000000000000000000000000075 +:106B20000101010101010101010101010101010155 +:106B30000101010101010101010101010101010145 +:106B40000000000000000000000000000000000045 +:106B50000101010101010101010101010101010125 +:106B60000101010101010101010101010101010115 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900002020202020202020202020202020202D5 +:106BA00002020202020202020202020202020202C5 +:106BB00002020202020202020202020202020202B5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000202020202020202020202020202020264 +:106C1000010100010101010001000000000000006D +:106C20000101010101010101010101010101010154 +:106C30000101010101010101010101010101010144 +:106C40000101010101010101010101010101010134 +:106C50000101010101010101010101010101010124 +:106C60000101010101010101010101010101010114 +:106C70000101010101010101010101010101010104 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000000000000E4 +:106CB00002020202020202020202020202020202B4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000101010101010101010101010101010184 +:106D00000202020202020202020202020202020263 +:106D10000101010101010101010100010001000067 +:106D20000101010101010101010101010101010153 +:106D30000101010101010101010101010101010143 +:106D40000101010101010101010101010101010133 +:106D50000101010101010101010101010101010123 +:106D60000101010101010101010101010101010113 +:106D70000101010101010101010101010101010103 +:106D800001010101010101010101010101010101F3 +:106D900001010101010101010101010101010101E3 +:106DA00001010101010101010101010101010101D3 +:106DB00001010101010101010101010101010101C3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000000000000000000B3 +:106DE0000101010101010101010101010101010193 +:106DF0000101010101010101010101010101010183 +:106E00000202020202020202020202020202020262 +:106E10000101010101010101010100010001010164 +:106E20000101010101010101010101010101010152 +:106E30000101010101010101010101010101010142 +:106E40000101010101010101010101010101010132 +:106E50000101010101010101010101010101010122 +:106E60000101010101010101010101010101010112 +:106E70000101010101010101010101010101010102 +:106E800001010101010101010101010101010101F2 +:106E900001010101010101010101010101010101E2 +:106EA00001010101010101010101010101010101D2 +:106EB00001010101010101010101010101010101C2 +:106EC00001010101010101010101010101010101B2 +:106ED00001010101010101010101010101010101A2 +:106EE0000101010101010101010101010101010192 +:106EF0000101010101010101010101010101010182 +:106F00000000000000000000000000000000000081 +:106F10000101010101010101010101010101010161 +:106F20000101010101010101010101010101010151 +:106F30000101010101010101010101010101010141 +:106F40000101010101010101010101010101010131 +:106F50000101010101010101010101010101010121 +:106F60000101010101010101010101010101010111 +:106F70000101010101010101010101010101010101 +:106F800001010101010101010101010101010101F1 +:106F900001010101010101010101010101010101E1 +:106FA00001010101010101010101010101010101D1 +:106FB00001010101010101010101010101010101C1 +:106FC00001010101010101010101010101010101B1 +:106FD00001010101010101010101010101010101A1 +:106FE0000101010101010101010101010101010191 +:106FF0000101010101010101010101010101010181 +:107000000000000000000000000000000000000080 +:107010000101010101010101010101010101010160 +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:107050000202020202020202020202020202020210 +:107060000202020202020202020202020202020200 +:1070700002020202020202020202020202020202F0 +:1070800002020202020202020202020202020202E0 +:1070900002020202020202020202020202020202D0 +:1070A00002020202020202020202020202020202C0 +:1070B00002020202020202020202020202020202B0 +:1070C00002020202020202020202020202020202A0 +:1070D0000202020202020202020202020202020290 +:1070E0000202020202020202020202020202020280 +:1070F0000202020202020202020202020202020270 +:10710000000000000000000000000000000000007F +:10711000010101010101010101010101010101015F +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D00000000000000000000000000000000000AF +:1071E000020202020202020202020202020202027F +:1071F000020202020202020202020202020202026F +:10720000000000000000000000000000000000007E +:10721000010101010101010101010101010101015E +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000020202020202020202020202020202026E +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000000000000000000007C +:107410003300000000000000000000000000000039 +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000001000000BB +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000001000000BA +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000001000000B9 +:1076D00000000000010000000000000000000000A9 +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000000000000000000D9 +:1077B00001000000000000000000000000000000C8 +:1077C00000000000000000000000000001000000B8 +:1077D00001000000010000000000000000000000A7 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000000000001000000D7 +:1078B00001000000010100000000000000000000C5 +:1078C00000000000000100000000000001000000B6 +:1078D00001000000010100000000000000000000A5 +:1078E0000000000001010000000000000000000096 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000000000001000000D6 +:1079B00001000000010100000000000000000000C4 +:1079C00000000000000100000000000001000001B4 +:1079D00001000000010101000000000000000000A3 +:1079E0000100000001010100000000000000000093 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000000000001000000D5 +:107AB00001000000010100000000000001000000C2 +:107AC00000000000010100000000000101000001B1 +:107AD000010001010101010100000000010000009E +:107AE000010001000101010100000000010000008F +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000010000000000000000000034 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000100000000000001000000D3 +:107BB00001000000010100000000000001000000C1 +:107BC00000000000010100000000000101000101AF +:107BD000010101010101010100000000010000009C +:107BE000010001000101010100000000010000008E +:107BF0000000000000000000000000000000000085 +:107C00000000000001010000000000000000000072 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000010000000000000000000033 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000100000000000101000000D1 +:107CB00001000001010100000000000001000000BF +:107CC00000000000010100010000000101000101AD +:107CD000010101010101010100000001010000009A +:107CE000010001010101010100000000010000008C +:107CF0000000000000000000000000000000000084 +:107D00000000000001010000000000000000000071 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D3000000000000101000100000000010000003F +:107D40000000000001010000000000000000000031 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000100000000000000000000E2 +:107DA00000000000010100010000000101000101CC +:107DB00001000001010100000000000001000000BE +:107DC00001000000010101010000000101000101AA +:107DD0000101010101010101000000010100000198 +:107DE000010001010101010100000000010000008B +:107DF0000000000000000000000000000000000083 +:107E00000000000001010000000000000000000070 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E3000000000000101010100000000010000003D +:107E4000010000000101000000000000000000002F +:107E50000000000001010000000000000000000020 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000100000000000000000000F1 +:107E900000000000000101000000000000000000E0 +:107EA00001000000010101010000000101010101C8 +:107EB00001000101010100010000000001010000BA +:107EC00001000101010101010000010101010101A5 +:107ED0000101010101010101000000010101000196 +:107EE000010001010101010100000000010000008A +:107EF0000000000000010000000000000000000081 +:107F0000000000000101000000000000000000006F +:107F10000000000000000000000000000000000061 +:107F2000000000000000000001000000010000004F +:107F3000000001010101010100000000010000003A +:107F4000010000000101000000000000000000002E +:107F5000000000000101000000000000000000001F +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800001000000000101000000000000000000EE +:107F900000000000010101010000000001000000DC +:107FA00001000100010101010000000101010101C6 +:107FB00001010101010100010000000001010101B6 +:107FC00001000101010101010000010101010101A4 +:107FD0000101010101010101000000010101010194 +:107FE0000101010101010101000000000100000088 +:107FF000000000000001000000000000000100007F +:10800000000000000101000000000000000000006E +:108010000000000000000000000000000000000060 +:10802000000000000101000001000000010000004C +:108030000100010101010101000000000100000038 +:10804000010000000101000000000000000000002D +:10805000000000000101000000000000000000001E +:108060000000000000000000000000000000000010 +:1080700000000000000000000000000001000000FF +:1080800001000000010101010000000000000000EB +:1080900001000000010101010000000001000000DA +:1080A00001000100010101010000000101010101C5 +:1080B00001010101010100010000000101010101B4 +:1080C00001000101010101010001010101010101A2 +:1080D0000101010101010101000000010101010193 +:1080E0000101010101010101000000000100000087 +:1080F000000000000001000000000000000100007E +:10810000000000000101000000000000000000006D +:10811000000000000000000000000000000000005F +:108120000100000001010100010000000100000049 +:108130000100010101010101000000000100000037 +:10814000010000000101000100000000000000002B +:10815000000000000101000000000000000000001D +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000001000000FE +:1081800001000000010101010000000001000000E9 +:1081900001000000010101010000000101000000D8 +:1081A00001000101010101010000000101010101C3 +:1081B00001010101010101010000000101010101B2 +:1081C00001010101010101010001010101010101A0 +:1081D0000101010101010101000000010101010192 +:1081E0000101010101010101000000000100000086 +:1081F000000000000001000000000000000100007D +:10820000000000000101000000000000000000006C +:10821000000000000000000000000000000000005E +:108220000100000001010100010000000100010146 +:108230000101010101010101000000000100000035 +:10824000010000000101000100000000000000002A +:10825000000000000101000000000000000000001C +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000001000000FD +:1082800001000101010101010000000001000000E6 +:1082900001000000010101010000000101000101D5 +:1082A00001010101010101010000000101010101C1 +:1082B00001010101010101010000000101010101B1 +:1082C000010101010101010100010101010101019F +:1082D000010101010101010100010101010101018F +:1082E0000101010101010101000000000100000085 +:1082F000000000000001000000000000000100007C +:10830000000000000101000000000000000000006B +:10831000000000000000000000000000000000005D +:108320000100000001010100010000010101010143 +:108330000101010101010101010000000100000033 +:108340000100000001010001000000000000000029 +:10835000000000000101000000000000000000001B +:10836000000000000101000100000000000000000A +:1083700000000000000000000000000001000000FC +:1083800001000101010101010000000101000000E4 +:1083900001000101010101010000000101010101D1 +:1083A00001010101010101010000000101010101C0 +:1083B00001010101010101010000000101010101B0 +:1083C000010101010101010100010101010101019E +:1083D000010101010101010100010101010101018E +:1083E0000101010101010101000000000100000084 +:1083F000000000000001000000000000000100007B +:10840000000000000101000000000000000000006A +:10841000000000000000000000000000010000005B +:108420000100000001010100010000010101010142 +:108430000101010101010101010000000100000032 +:108440000100000001010001000000000101000026 +:108450000000010001010001000000000000000018 +:108460000100000001010101000000000000000007 +:1084700000000000010100000000000101000000F8 +:1084800001000101010101010000000101000000E3 +:1084900001010101010101010000000101010101CF +:1084A00001010101010101010001000101010101BE +:1084B00001010101010101010000000101010101AF +:1084C000010101010101010101010101010101019C +:1084D000010101010101010100010101010101018D +:1084E0000101010101010101000001000100000082 +:1084F0000000010001010001000000000001010076 +:108500000000000001010000000000000000000069 +:108510000000000000000000000000000100010059 +:108520000101000001010100010000010101010140 +:108530000101010101010101010000010100000030 +:108540000100000001010001000000000101000025 +:108550000100010001010001000000000000000016 +:108560000100000101010101000000000000000005 +:1085700000000000010101000000000101000101F4 +:1085800001010101010101010000000101000000E1 +:1085900001010101010101010000000101010101CE +:1085A00001010101010101010001000101010101BD +:1085B00001010101010101010000000101010101AE +:1085C000010101010101010101010101010101019B +:1085D000010101010101010100010101010101018C +:1085E0000101010101010101000001000100000081 +:1085F0000100010001010001000000000001010074 +:108600000000000001010000000000000000000068 +:108610000000000000000000010000010101010055 +:10862000010101010101010101000001010101013C +:10863000010101010101010101000001010000002F +:108640000100000001010001000000000101000024 +:108650000100010001010001000000000000000015 +:108660000100000101010101000000000000000004 +:1086700000000000010101010000000101010101F1 +:1086800001010101010101010000000101000101DE +:1086900001010101010101010000000101010101CD +:1086A00001010101010101010001000101010101BC +:1086B00001010101010101010001010101010101AB +:1086C000010101010101010101010101010101019A +:1086D000010101010101010100010101010101018B +:1086E000010101010101010100010100010100007E +:1086F0000100010001010001000000000001010172 +:108700000000000001010000000000000000000067 +:108710000000000000000000010000010101010153 +:10872000010101010101010101010001010101013A +:10873000010101010101010101010101010000002C +:108740000100000001010001000000000101000023 +:108750000100010001010001000000000000000014 +:108760000100010101010101000000000000000002 +:1087700001000000010101010000000101010101EF +:1087800001010101010101010001000101010101DB +:1087900001010101010101010001010101010101CA +:1087A00001010101010101010001000101010101BB +:1087B00001010101010101010001010101010101AA +:1087C0000101010101010101010101010201010198 +:1087D000010101010101010100010101010101018A +:1087E000010101010101010100010100010100017C +:1087F0000101010001010001000000000001010170 +:108800000000000001010000000000000000000066 +:108810000000000000000000010100010101010151 +:108820000101010101010101020100010101010138 +:10883000010101010101010102010101010000002A +:108840000100000001010001000000000101000022 +:108850000100010001010001000000000000000013 +:108860000100010101010101000000000100000000 +:1088700001000000010101010001000101010101ED +:1088800001010101010101010001000101010101DA +:1088900001010101010101010001010101010101C9 +:1088A00001010101010101010001010102010101B8 +:1088B00002010101010101010101010101010101A7 +:1088C0000101010101010101010101010201010197 +:1088D0000101010101010101010101010101010188 +:1088E0000101010101010101010101010101000179 +:1088F000010101000101000100000000000101016F +:108900000000000001010000000000000000000065 +:10891000000000000000000002010001010101014F +:108920000201010101010101020101010101010135 +:108930000101010101010101020101010200000028 +:108940000100000001020001000000000101000020 +:10895000010201000101010100000000010000000E +:1089600001000101010101010000000001000000FF +:1089700001000000010101010001000101010101EC +:1089800001010101010101010001010101010101D8 +:1089900001010101010101010001010101010101C8 +:1089A00001010101010101010001010202010101B6 +:1089B00002010101020201010101010101010101A4 +:1089C0000101010101010101010101020201010294 +:1089D0000201010102010101010101010101010185 +:1089E0000101010101010101010101010101000178 +:1089F000010101000101000100000000000101016E +:108A0000000000000101000100000000000002025F +:108A10000002000000000200020101010102020147 +:108A20000202010102020200020101010101010131 +:108A30000101010101010101020101010200000027 +:108A4000020000000202020100000000010100001B +:108A5000010101010101010100000000010000000D +:108A600001010101010101010000000001000000FD +:108A700001000001010101010001000101010101EA +:108A800001010101010101010001010101010101D7 +:108A900001010101010101010001010101010101C7 +:108AA00001010101010101010101010202020202B1 +:108AB00002010102020201010101010101010101A2 +:108AC0000101010101010101010102020201020291 +:108AD000020202020202020101010101010101017F +:108AE0000101010101010101010101010201000176 +:108AF000010101000101000100000000000101016D +:108B0000000000000101000100000000000202025C +:108B1000000202020101010002020102020202023D +:108B2000020202020202020002010101010101012E +:108B30000101010101010101020101010200000026 +:108B40000200000202020101000000000101010117 +:108B5000010101010101010100000000010000000C +:108B600001010101010101010000000001000000FC +:108B700001000001010101010001000101010101E9 +:108B800001010101010101010101010101010101D5 +:108B900001010101010101010101010101010101C5 +:108BA00001010101010101010101010202020202B0 +:108BB000020202020202010101010101010101019F +:108BC000010101010101010101020202020202028E +:108BD000020202020202020201010102020101017B +:108BE0000201020102020201010101010201000170 +:108BF000010101000101000100000000010101016B +:108C0000000000000101000100000200000201025A +:108C1000010102010101010002020202020202023C +:108C2000020202020202020002010101020101012C +:108C3000010102020202020202020202020000001C +:108C40000200000102020102000000010102010114 +:108C50000101010102020101000000000100010107 +:108C600001010101010101010000000101000000FA +:108C700001000101010101010101010101010101E5 +:108C800001010101010101010101010101010101D4 +:108C900001010101010202010101010101010101C2 +:108CA00001010101010101010102010202020202AE +:108CB000020202020202010201010101020101019C +:108CC000010101010102010102020202020202028B +:108CD0000202020202020202010101020202010278 +:108CE000020102020202020201010101020100016D +:108CF0000101010201010001000000000102010167 +:108D00000000000002020001000002020102010155 +:108D1000010101010101010002020202020202023C +:108D20000202020202020200020101020202020227 +:108D30000202020202020202020202020200000019 +:108D40000200000102020102000000010102010113 +:108D50000101010102020101000100010100010104 +:108D600001010101010101010000000101000100F8 +:108D700001000101010101010101010101010101E4 +:108D800001010101010101010101010202010101D1 +:108D900002010101020202020101010101010101BE +:108DA00001010101010201010102010202020202AC +:108DB0000202020202020202010101010202010199 +:108DC0000101010102020101020202020202020289 +:108DD0000202020202020202010202020202020274 +:108DE000020202020202020201010201020100016A +:108DF0000101010101020001000001000102010165 +:108E00000000010002020001000002010101010155 +:108E1000010101010101010002020202020202023B +:108E20000202020202020200020201020202020225 +:108E30000202020202020202020202020200000018 +:108E40000200000102020102000100010202010110 +:108E50000101020102020101000100010100010102 +:108E600001010101010101010001000101000100F6 +:108E700001000101010101010101010102010101E2 +:108E800002010101010202010102010202010101CC +:108E900002020202020202020101010202010101B8 +:108EA00002010201020202020202020202020202A4 +:108EB0000202020202020202010101020202020295 +:108EC0000201020202020202020202020202020283 +:108ED0000202020202020202010202020202020273 +:108EE0000202020202020202020202010201000167 +:108EF0000101010101020001000001000102010164 +:108F00000100010002020101000202010101010150 +:108F10000101010101010101020202020202020239 +:108F20000202020202020200020202020202020223 +:108F30000202020202020202020202020200000017 +:108F4000020000010202010200010001020201010F +:108F500002010201020201020101000101010101FD +:108F600001010101010101010001000101000101F4 +:108F700001010101010101010101010202010101DF +:108F800002010202020202020202020202020202C2 +:108F900002020202020202020101010202020202B4 +:108FA00002020202020202020202020202020202A1 +:108FB0000202020202020202010101020202020294 +:108FC0000202020202020202020202020202020281 +:108FD0000202020202020202020202020202020271 +:108FE0000202020202020202020202010202010164 +:108FF0000101020101020001000001000102020161 +:10900000010001010202010100020101010101014F +:109010000101010101010101020202020202020238 +:109020000202020202020200020202020202020222 +:109030000202020202020202020202020200000016 +:10904000020000010202010201010101020202020A +:1090500002020202020201020101000101010101FA +:1090600002010102020202020101000101000101EC +:1090700001010101010101010102010202020202DA +:1090800002020202020202020202020202020202C0 +:1090900002020202020202020102020202020202B1 +:1090A00002020202020202020202020202020202A0 +:1090B0000202020202020202020202020202020290 +:1090C0000202020202020202020202020202020280 +:1090D0000202020202020202020202020202020270 +:1090E0000202020202020202020202020202010261 +:1090F000020202010202000200000100010202025B +:10910000010101010202010100010101010101014E +:109110000101010101010101020202020202020237 +:109120000202020202020200020202020202020221 +:109130000202020202020202020202020200000015 +:109140000200000202020202020202020202020203 +:1091500002020202020202020101010101010101F7 +:1091600002010202020202020101000101000101EA +:1091700001010101020202010202010202020202D5 +:1091800002020202020202020202020202020202BF +:1091900002020202020202020202020202020202AF +:1091A000020202020202020202020202020202029F +:1091B000020202020202020202020202020202028F +:1091C000020202020202020202020202020202027F +:1091D000020202020202020202020202020202026F +:1091E0000202020202020202020202020202010260 +:1091F0000202020102020002010001010102020258 +:10920000010101010202010100010101010101014D +:109210000101010101010101020202020202020236 +:109220000202020202020200020202020202020220 +:109230000202020202020202020202020200000014 +:109240000200000202020202020202020202020202 +:1092500002020202020202020202010102010101F3 +:1092600002020202020202020101010102010101E5 +:1092700002010101020202020202020202020202D1 +:1092800002020202020202020202020202020202BE +:1092900002020202020202020202020202020202AE +:1092A000020202020202020202020202020202029E +:1092B000020202020202020202020202020202028E +:1092C000020202020202020202020202020202027E +:1092D000020202020202020202020202020202026E +:1092E000020202020202020202020202020201025F +:1092F0000202020102020002010002010102020256 +:10930000010101010202010100010100000100014F +:10931000000001000000000102020202020202023B +:10932000020202020202020002020202020202021F +:109330000202020202020202020202020202000011 +:109340000200000202020202020202020202020201 +:1093500002020202020202020202010202010202EF +:1093600002020202020202020202010202010101E1 +:1093700002010102020202020202020202020202CF +:1093800002020202020202020202020202020202BD +:1093900002020202020202020202020202020202AD +:1093A000020202020202020202020202020202029D +:1093B000020202020202020202020202020202028D +:1093C000020202020202020202020202020202027D +:1093D000020202020202020202020202020202026D +:1093E000020202020202020202020202020201025E +:1093F0000202020102020102020102010202020251 +:109400000101010102020102000000000000000051 +:10941000000000000000000102020202020101013E +:109420000101010102020200020202020202020222 +:10943000020202020202020202020202020202020C +:1094400002020002020202020202020202020202FE +:1094500002020202020202020202020202020202EC +:1094600002020202020202020202010202010201DF +:1094700002010202020202020202020202020202CD +:1094800002020202020202020202020202020202BC +:1094900002020202020202020202020202020202AC +:1094A000020202020202020202020202020202029C +:1094B000020202020202020202020202020202028C +:1094C000020202020202020202020202020202027C +:1094D000020202020202020202020202020202026C +:1094E000020202020202020202020202020202025C +:1094F000020202020202010202010201020202024F +:10950000010102010202010200000000000000004F +:109510000000000000000000010101010101010143 +:109520000101010101010100020202020202020224 +:10953000020202020202020202020202020202020B +:1095400002020202020202020202020202020202FB +:1095500002020202020202020202020202020202EB +:1095600002020202020202020202020202010202DC +:1095700002020202020202020202020202020202CB +:1095800002020202020202020202020202020202BB +:1095900002020202020202020202020202020202AB +:1095A000020202020202020202020202020202029B +:1095B000020202020202020202020202020202028B +:1095C000020202020202020202020202020202027B +:1095D000020202020202020202020202020202026B +:1095E000020202020202020202020202020202025B +:1095F000020202020202010202020202020202024C +:10960000020202020202020200000000000000004A +:109610000000000000000000010101010101010142 +:109620000101010101010100020202020202020223 +:10963000020202020202020202020202020202020A +:1096400002020202020202020202020202020202FA +:1096500002020202020202020202020202020202EA +:1096600002020202020202020202020202020202DA +:1096700002020202020202020202020202020202CA +:1096800002020202020202020202020202020202BA +:1096900002020202020202020202020202020202AA +:1096A000020202020202020202020202020202029A +:1096B000020202020202020202020202020202028A +:1096C000020202020202020202020202020202027A +:1096D000020202020202020202020202020202026A +:1096E000020202020202020202020202020202025A +:1096F000020202020202010202020202020202024B +:109700000202020202020202000000000000000049 +:109710000000000000000000010101010101010141 +:109720000101010101010100020202020202020222 +:10973000020202020202020200020202020202020B +:1097400002020202020202020202020202020202F9 +:1097500002020202020202020202020202020202E9 +:1097600002020202020202020202020202020202D9 +:1097700002020202020202020202020202020202C9 +:1097800002020202020202020202020202020202B9 +:1097900002020202020202020202020202020202A9 +:1097A0000202020202020202020202020202020299 +:1097B0000202020202020202020202020202020289 +:1097C0000202020202020202020202020202020279 +:1097D0000202020202020202020202020202020269 +:1097E0000202020202020202020202020202020259 +:1097F0000202020202020202020202020202020249 +:109800000202020202020202000000000000000048 +:109810000000000000000000010101010101010140 +:109820000101010101010100020202020202020221 +:109830000202020202020202000000000000000018 +:109840000000000000000000020202020202020208 +:1098500002020202020202020202020202020202E8 +:1098600002020202020202020202020202020202D8 +:1098700002020202020202020202020202020202C8 +:1098800002020202020202020202020202020202B8 +:1098900002020202020202020202020202020202A8 +:1098A0000202020202020202020202020202020298 +:1098B0000202020202020202020202020202020288 +:1098C0000202020202020202020202020202020278 +:1098D0000202020202020202020202020202020268 +:1098E0000202020202020202020202020202020258 +:1098F0000202020202020202020202020202020248 +:109900000202020202020202000000000000000047 +:109910000000000000000000000000000000000047 +:109920000000000000000000020202020202020227 +:109930000202020202020202000000000000000017 +:10994000000000000000000002020102020101010B +:1099500002010201020202020202020202020202E9 +:1099600002020202020202020202020202020202D7 +:1099700002020202020202020202020202020202C7 +:1099800002020202020202020202020202020202B7 +:1099900002020202020202020202020202020202A7 +:1099A0000202020202020202020202020202020297 +:1099B0000202020202020202020202020202020287 +:1099C0000202020202020202020202020202020277 +:1099D0000202020202020202020202020202020267 +:1099E0000202020202020202020202020202020257 +:1099F0000202020202020202020202020202020247 +:109A0000020202020202020202000002020002003E +:109A1000020200020202020000000000000000003A +:109A20000000000000000000010202020202020227 +:109A30000202020202020202010000000000000015 +:109A40000000000000000000020202020202020206 +:109A500002020202020202020202020202020202E6 +:109A600002020202020202020202020202020202D6 +:109A700002020202020202020202020202020202C6 +:109A800002020202020202020101010101010101BE +:109A900001010101010101010202020202020202AE +:109AA000020202020202020201010101010101019E +:109AB000010101010101010102020202020202028E +:109AC0000202020202020202020202020202020276 +:109AD0000202020202020202020202020202020266 +:109AE0000202020202020202020202020202020256 +:109AF0000202020202020202020202020202020246 +:109B00000202020202020202020200020202020237 +:109B10000202020202020200000000000000000037 +:109B2000000000000000000002010101010101012C +:109B30000101010101010101010101010101010115 +:109B40000101010101010101010100010100000009 +:109B500001000100010101010202020202020202EF +:109B600002020202020202020202020202020202D5 +:109B700002020202020202020202020202020202C5 +:109B800002020202020202020202020202020202B5 +:109B900002020202020202020202020202020202A5 +:109BA0000202020202020202020202020202020295 +:109BB0000202020202020202020202020202020285 +:109BC0000202020202020202020202020202020275 +:109BD0000202020202020202020202020202020265 +:109BE0000202020202020202020202020202020255 +:109BF0000202020202020202020202020202020245 +:109C00000202020202020202020202020202020234 +:109C10000202020202020202000000000000000034 +:109C20000000000000000000010202020202020225 +:109C3000020202020202020201010101010101010C +:109C40000101010101010101020200020200000004 +:109C500002000200020202020202020202020202E8 +:109C600002020202020202020202020202020202D4 +:109C700002020202020202020202020202020202C4 +:109C800002020202020202020000000000000000C4 +:109C900000000000000000000202020202020202B4 +:109CA00002020202020202020000000000000000A4 +:109CB0000000000000000000020202020202020294 +:109CC000020202020202020201010101010101017C +:109CD000010101010101010102020202020202026C +:109CE0000202020202020202020202020202020254 +:109CF0000202020202020202020202020202020244 +:109D00000202020202020202020202020202020233 +:109D10000202020202020202000000000000000033 +:109D2000000000000000000001010101010101012B +:109D30000101010101010101010101010101010113 +:109D40000101010101010101010101010101010103 +:109D500001010101010101010202020202020202EB +:109D600002020202020202020101010101010101DB +:109D700001010101010101010202020202020202CB +:109D800002020202020202020000000000000000C3 +:109D900000000000000000000202020202020202B3 +:109DA00002020202020202020000000000000000A3 +:109DB0000000000000000000020202020202020293 +:109DC0000202020202020202020202020202020273 +:109DD0000202020202020202020202020202020263 +:109DE0000202020202020202000000000000000063 +:109DF0000000000000000000020202020202020253 +:109E00000202020202020202020202020202020232 +:109E1000020202020202020201010101010101012A +:109E20000101010101010100010101010101010123 +:109E30000101010101010101010101010101010112 +:109E40000101010101010101010101010101010102 +:109E500001010101010101010101010101010101F2 +:109E600001010101010101010202020202020202DA +:109E700002020202020202020000000000000000D2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000202020202020202B2 +:109EA000020202020202020201010101010101019A +:109EB000010101010101010102020202020202028A +:109EC0000202020202020202000000000000000082 +:109ED0000000000000000000020202020202020272 +:109EE0000202020202020202000000000000000062 +:109EF000000000000000000001010101010101015A +:109F00000101010101010101020202020202020239 +:109F10000202020202020202010101010101010129 +:109F20000101010101010101010101010101010121 +:109F30000101010101010101010101010101010111 +:109F40000101010101010101010101010101010101 +:109F500001010101010101010202020202020202E9 +:109F600002020202020202020101010101010101D9 +:109F700001010101010101010101010101010101D1 +:109F800001010101010101010000000000000000C9 +:109F900000000000000000000202020202020202B1 +:109FA0000202020202020202010101010101010199 +:109FB0000101010101010101020202020202020289 +:109FC0000202020202020202010101010101010179 +:109FD0000101010101010101000000000000000079 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000010101010101010159 +:10A000000101010101010101020202020202020238 +:10A010000202020202020202010101010101010128 +:10A020000101010101010101010101010101010120 +:10A030000101010101010101010101010101010110 +:10A040000101010101010101010101010101010100 +:10A0500001010101010101010101010101010101F0 +:10A0600001010101010101010101010101010101E0 +:10A0700001010101010101010101010101010101D0 +:10A0800001010101010101010101010101010101C0 +:10A0900001010101010101010000000000000000B8 +:10A0A00000000000000000000101010101010101A8 +:10A0B0000101010101010101010101010101010190 +:10A0C0000101010101010101010101010101010180 +:10A0D0000101010101010101000000000000000078 +:10A0E0000000000000000000010101010101010168 +:10A0F0000101010101010101010101010101010150 +:10A100000101010101010101020202020202020237 +:10A110000202020202020202010101010101010127 +:10A12000010101010101010101010101010101011F +:10A13000010101010101010101010101010101010F +:10A1400001010101010101010101010101010101FF +:10A1500001010101010101010101010101010101EF +:10A1600001010101010101010101010101010101DF +:10A1700001010101010101010101010101010101CF +:10A1800001010101010101010101010101010101BF +:10A1900001010101010101010101010101010101AF +:10A1A000010101010101010101010101010101019F +:10A1B000010101010101010101010101010101018F +:10A1C000010101010101010101010101010101017F +:10A1D000010101010101010101010101010101016F +:10A1E000010101010101010101010101010101015F +:10A1F000010101010101010101010101010101014F +:10A200000101010101010101000000000000000046 +:10A210000000000000000000010101010101010136 +:10A22000010101010101010101010101010101011E +:10A23000010101010101010101010101010101010E +:10A2400001010101010101010101010101010101FE +:10A2500001010101010101010101010101010101EE +:10A2600001010101010101010101010101010101DE +:10A2700001010101010101010101010101010101CE +:10A2800001010101010101010101010101010101BE +:10A2900001010101010101010101010101010101AE +:10A2A000010101010101010101010101010101019E +:10A2B000010101010101010101010101010101018E +:10A2C000010101010101010101010101010101017E +:10A2D000010101010101010101010101010101016E +:10A2E000010101010101010101010101010101015E +:10A2F000010101010101010101010101010101014E +:10A300000101010101010101000000000000000045 +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000002020202020202020D +:10A3400002020202020202020202020202020202ED +:10A3500002020202020202020000000000000000ED +:10A3600000000000000000000202020202020202DD +:10A3700002020202020202020202020202020202BD +:10A3800002020202020202020202020202020202AD +:10A3900002020202020202020000000000000000AD +:10A3A000000000000000000002020202020202029D +:10A3B000020202020202020202020202020202027D +:10A3C000020202020202020202020202020202026D +:10A3D000020202020202020202020202020202025D +:10A3E000020202020202020202020202020202024D +:10A3F000020202020202020202020202020202023D +:10A40000020202020202020200000000000000003C +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A000000000000000000002020202020202029C +:10A4B000020202020202020200000000000000008C +:10A4C000000000000000000002020202020202027C +:10A4D000020202020202020200000000000000006C +:10A4E000000000000000000002020202020202025C +:10A4F000020202020202020202020202020202023C +:10A50000020202020202020200000000000000003B +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000002020202020202024B +:10A60000020202020202020200000000000000003A +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000000000000000000310000000000000008 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000001000000000000000078 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000001000000000001000101000154 +:10A800000000000000000000000000000000000048 +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000001000000000000000077 +:10A8E0000000000000000000000000000000000068 +:10A8F000000000000101010101010101010101014C +:10A900000000000000000000000000000000000047 +:10A910000000000000000000000000000000000037 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600000000000000000000000010000000000E6 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000010001000000000000000075 +:10A9E0000000000000000000000000000000000067 +:10A9F000000000000101010101010101010101014B +:10AA00000000000000000000000000000000000046 +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600000000000000000000000010000000000E5 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000010001000000000000000074 +:10AAE0000000000000000000000000000000000066 +:10AAF000000000000101010101010101010101014A +:10AB00000000000000000000000000000000000045 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600000000000000000000000010000000000E4 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000010101000000000001010070 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000001010101010101010101010149 +:10AC00000000000000000000000000000000000044 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600000000000000000000000010000000000E3 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000100A3 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD000000001000001010101000000000101006D +:10ACE0000000000000000000000000000000000064 +:10ACF0000001010001010101010101010101010146 +:10AD00000000000000000000000000000000000043 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000010000000000E2 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000100A2 +:10ADB0000000000000010101000000000000000090 +:10ADC0000000000000000000000000000000000083 +:10ADD000000001000001010101000000000101016B +:10ADE0000000000000000000000000000000000063 +:10ADF0000001010001010101010101010101010145 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600000000000000000000101010000000000DF +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA000000000000001000100000000000101019D +:10AEB000000000000001010100000000000000008F +:10AEC0000000000000000000000000000000000082 +:10AED000000001000001010101000000000101016A +:10AEE0000000000000000000000000000000000062 +:10AEF0000101010001010101010101010101010143 +:10AF00000000000000000000000000000000000041 +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF400000000000000000000000000000000101FF +:10AF500001000000000000000000000000000000F0 +:10AF600000000000000000000101010000000000DE +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000100C0 +:10AF900000000000000000000000000000000000B1 +:10AFA000000000000001000100000000000101019C +:10AFB000000000000001010100000000000000008E +:10AFC0000000000000000000000000000000000081 +:10AFD0000000010000010101010000000001010169 +:10AFE0000000000000000000000000000000000061 +:10AFF0000101010001010101010101010101010142 +:10B000000000000000000000000000000000000040 +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B0400000000000000000000000000000000101FE +:10B0500001000000000000000000000000000000EF +:10B0600000000000000000000101010000000000DD +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000100BF +:10B0900000000000000000000000000000000000B0 +:10B0A0000000000000010101000001000101010198 +:10B0B000000000000001010100000000000000008D +:10B0C0000000000000000000000000000000000080 +:10B0D0000000010000010101010000000001010168 +:10B0E0000000000000000000000000000000000060 +:10B0F0000101010001010101010101010101010141 +:10B10000010000000000000000000000000000003E +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000001000000001E +:10B13000000000000000000000000000000000000F +:10B1400000000000000100000000000000000101FC +:10B1500001000000000000000000000000000000EE +:10B1600000000000000000000101010000000000DC +:10B1700000000000000000000000000000000000CF +:10B1800000000000000100000000000000000101BC +:10B1900000000000000000000000000000000100AE +:10B1A0000000010000010101000001010101010195 +:10B1B000000000000001010100000000000000008C +:10B1C000000000000000000000000000000000007F +:10B1D0000000010000010101010001000001010166 +:10B1E000000000000000000000000000000000005F +:10B1F0000101010001010101010101010101010140 +:10B20000010000000000000000000000000000003D +:10B21000000000000000000000000000000000002E +:10B22000000000000000010000000101010000001A +:10B23000000000000000000000000000000000000E +:10B2400000000000000100000000000000000101FB +:10B2500001000000000000000000000000000000ED +:10B2600000000000000000000101010000000000DB +:10B2700000000000000000000000000000000000CE +:10B2800000000000000100000000000000000101BB +:10B2900000000000000000000000000000000100AD +:10B2A0000000010101010101000001010101010192 +:10B2B000000001000001010100000000000000008A +:10B2C000000000000000000000000000000000007E +:10B2D0000000010000010101010101000001010164 +:10B2E000000000000000000000000000000000005E +:10B2F000010101000101010101010101010101013F +:10B30000010000000000000000000000000100003B +:10B31000000000000000000000000000000000002D +:10B320000000000000000100000001010100000019 +:10B33000000000000000000000000000000000000D +:10B3400000000000000101010000000000010101F7 +:10B3500001000000000000000000000000000000EC +:10B3600001000000000000000101010000000000D9 +:10B3700000000000000000000000000000000000CD +:10B3800000000000000101010000000000010101B7 +:10B3900000000000000000000000000000000101AB +:10B3A000000101010101010101010101010101018E +:10B3B0000000010000010101000000000000000188 +:10B3C000000000000000000000000000000000007D +:10B3D0000000010100010101010101000101010161 +:10B3E000000000000000000000000000000000005D +:10B3F000010101000101010101010101010101013E +:10B400000100000000000000000100010001000038 +:10B41000000000000000000000000000000000002C +:10B420000000000000000100000001010101000017 +:10B43000000000000000000000000000000000000C +:10B4400000000100000101010000000000010101F5 +:10B4500001000000000000000000000000000000EB +:10B4600001000000000000000101010000000000D8 +:10B4700000000000000000000000000000000000CC +:10B4800000000100000101010000000000010101B5 +:10B4900000000000000000000000000000000101AA +:10B4A000000101010101010101010101010101018D +:10B4B0000000010000010101010000000000000186 +:10B4C000000000000000000000000000000000007C +:10B4D0000000010100010101010101000101010160 +:10B4E000000000000000000000000000000001005B +:10B4F000010101000101010101010101010101013D +:10B500000100000000000000000100010001000136 +:10B51000000000000000000000000000000000002B +:10B520000001010000000100010101010101000012 +:10B53000010000000000000000000000000000000A +:10B5400000000101000101010000010001010101F1 +:10B5500001000000000000000000000000000000EA +:10B5600001000000000000000101010000000000D7 +:10B5700000000000000000000000020000000100C8 +:10B5800000000101000101010000010001010101B1 +:10B5900000000000000100000000000000010101A7 +:10B5A000000101010101010101010101010101018C +:10B5B0000000010000010101010000000000000185 +:10B5C000000000000000000000000000000000007B +:10B5D000000001010001010101010100010101015F +:10B5E000000000000000000000000000000001005A +:10B5F000010101010101010101010101010101013B +:10B600000100000000000000010100010001000134 +:10B61000000000000000000000000000000000002A +:10B620000001010000000100010101010101000011 +:10B630000100000000000000000000000000000009 +:10B6400000000101000101010001010101010101EE +:10B6500001000100000000000000000000000000E8 +:10B6600001000000000000000101010000000000D6 +:10B6700000000100000000000000010000000100C7 +:10B6800000000101000101010000010101010101AF +:10B6900000000100000100000000000000010101A5 +:10B6A000000101010101010101010101010101018B +:10B6B0000000010000010101010000010000000183 +:10B6C0000000000000000000000000000000010079 +:10B6D000000101010001010101010100010101015D +:10B6E0000000000000010101000000000001010154 +:10B6F0000101010102010101010101010101010139 +:10B70000010000000000010101010101010101012E +:10B710000000000000000000000000000000000029 +:10B720000001010000000100010101010101000010 +:10B730000100000000000000000000000000010106 +:10B7400000000101010101010001010101010101EC +:10B7500002000100000000000000010002010000E2 +:10B7600001000000000000000101010000000000D5 +:10B7700000000100000000000000010000010100C5 +:10B7800000000101010101010000010101010101AD +:10B79000000001010001010100000100010101019F +:10B7A000000101010101010101010101010101018A +:10B7B0000000010100010101010000010000000181 +:10B7C0000000000000000000000000000000010078 +:10B7D000000101010001010101010100010101015C +:10B7E0000000000000010101000000000001010153 +:10B7F0000201010102010101020202020202010131 +:10B80000010000000000010101010101010101012D +:10B810000000000000000000000000000000000028 +:10B82000000101000000010001010101010100000F +:10B830000100000000000000000000000000010105 +:10B8400000010101010101010001010101010101EA +:10B8500002000100000000000202010201010000DC +:10B8600001000100000000000101010000000000D3 +:10B8700000000100000000000000010000010100C4 +:10B8800000010101010101010001010101010101AA +:10B89000000001010001010100000100010101019E +:10B8A0000001010101010101010101010101010189 +:10B8B000000101010001010101000001000000017F +:10B8C0000000000000000000000000000200010174 +:10B8D0000001010100010102010101010101010159 +:10B8E000000000010101010100000100010101014E +:10B8F000020201010202020202020202020201022B +:10B90000010000000000010101010101010101012C +:10B910000000000000000000000000000000000027 +:10B92000000101000000010001010102010100000D +:10B930000100000000010000000000000000010103 +:10B9400000010101010101010001010101010101E9 +:10B9500002000100000000000202010201010001DA +:10B9600001000100000000000101020000000100D0 +:10B9700000000100000000000000010002010101C0 +:10B9800000010101010101010001010101010101A9 +:10B99000000001010101010100000100010101019C +:10B9A0000001010101010101010101010101010188 +:10B9B000000101010001010101000101000000017D +:10B9C0000000010000000000000000000100010173 +:10B9D0000001010100020102010101010101010157 +:10B9E0000000010101010101010101010101010149 +:10B9F0000202020102020202020202020202020228 +:10BA0000010001000000010101010101010101012A +:10BA10000000000000000000000000000000000026 +:10BA20000001010001010101010101020201010106 +:10BA30000100000000010000000000000000010102 +:10BA400000010101010101010001010101010101E8 +:10BA500002010100000000000101010201010001DA +:10BA600001000100000000000101020100000100CE +:10BA700000000100000000000200010201010101BC +:10BA800000010101010101010001010101010101A8 +:10BA90000001010101010101000101010101010198 +:10BAA0000001010101010101010101010101010187 +:10BAB000000101010001010101000101000000017C +:10BAC000000001010001010100000100010101016C +:10BAD0000001020100020202020101010102010152 +:10BAE0000000010101010101010101010101010148 +:10BAF0000202020102020202020202020202020227 +:10BB00000200010001010101010101010101010126 +:10BB10000000000000000000000000000000000025 +:10BB20000002010001010201010102020202010101 +:10BB30000200000000010000000000000000010100 +:10BB400000010101010101010001010101010101E7 +:10BB500002010100000000000101010101010001DA +:10BB600002000100000100000202020100000101C8 +:10BB700000000100000100000100010201010101BB +:10BB800000010101010101010001010101010101A7 +:10BB90000001010101010101000101010101010197 +:10BBA0000001010101010101010101010101010186 +:10BBB000000101010001010101000101000000017B +:10BBC0000000010100010101000001020101010169 +:10BBD0000001020100020202020101010102020150 +:10BBE0000001010101010101010101010101010146 +:10BBF0000202020102020202020202020202020226 +:10BC00000200010001010101010101010101010125 +:10BC10000000000000000000000000000000000024 +:10BC200002020201010102010202020202020101FA +:10BC300002000100000100000000000000000101FE +:10BC400000010101010101010001010101010101E6 +:10BC500002010100020000000101010101010001D7 +:10BC600002000100000100000202020100000101C7 +:10BC700000000100000100000102010101010101B9 +:10BC800000010101010101010001010101010101A6 +:10BC90000001010101010101000101010101010196 +:10BCA0000101010101010101010101010101010184 +:10BCB0000001010100020202010001010000000177 +:10BCC0000000010101010101000001010101010168 +:10BCD000000102010002020202010101010202024E +:10BCE0000001010101010101010101010101010145 +:10BCF0000202020102020202020202020202020225 +:10BD00000200010001010101010101010101010124 +:10BD10000000000000000000000000000000000023 +:10BD200002020201010102010202020202020101F9 +:10BD300002000100000101000000000000000101FC +:10BD400000010101010201010001010101010202E2 +:10BD500002010100010000010101010101010001D6 +:10BD600002000100000101010202020100000101C4 +:10BD700000000100000101000102010101010101B7 +:10BD800000010101010101010001010101010101A5 +:10BD90000001010101010101000101010101010195 +:10BDA000010101010102010201010101010202017F +:10BDB0000001010100020202010001010200000174 +:10BDC0000001010101010101020201010101010162 +:10BDD000000102020002020202020201010202024A +:10BDE0000001010101010101010101010101010144 +:10BDF0000202020202020202020202020202020223 +:10BE00000200010001010101010101010101010123 +:10BE10000000000000000000000000000000000022 +:10BE200002020201020102010202020202020100F8 +:10BE300002010100000101000000000000000101FA +:10BE400000010202010202020001010101020202DC +:10BE500002010200010000010101010101010001D4 +:10BE600002010100000101010202020100000101C2 +:10BE700000010200000101000101010101010101B5 +:10BE800000010101010201010001010101010201A2 +:10BE90000001010101010101010101010101010193 +:10BEA0000102020202020202010102020202020275 +:10BEB0000001020100020202010201010100000171 +:10BEC0000001010101010101010101010101010163 +:10BED0000002020200020202020202010202020247 +:10BEE0000001010101010101010101010101010143 +:10BEF0000202020202020202020202020202020222 +:10BF0000020001010101010101020102010201011E +:10BF10000000000000000000000000000000000021 +:10BF200002020202020102010202020202020100F6 +:10BF300002010100000101000000000000000101F9 +:10BF400001020202020202020002020202020202D4 +:10BF500002020201010100010101020101020101CD +:10BF600002010100000101010202020101000101C0 +:10BF700000010200000101010101020101020201B0 +:10BF8000010102020102020200010101010202029A +:10BF90000001010101010101010101010101020191 +:10BFA0000102020202020202020202020202020272 +:10BFB0000001020100020202020101010100000170 +:10BFC0000001010101010101010101010101010162 +:10BFD0000102020200020202020202010202020245 +:10BFE0000001010101010101010101010101010142 +:10BFF0000202020202020202020202020202020221 +:10C00000020101010101010102020102010201011B +:10C010000000000000000000000000000000000020 +:10C0200002020202020102020202020202020100F4 +:10C0300002010100000101000000000000000101F8 +:10C0400001020202020202020002020202020202D3 +:10C0500002020201020100010101020102020101CA +:10C0600002010100000101010202020101000101BF +:10C0700000010200000101010101020101020201AF +:10C080000102020202020202000102020202020294 +:10C09000000102020102010101010101010202028B +:10C0A0000102020202020202020202020202020271 +:10C0B000000202020102020202010102010000026A +:10C0C0000001010101010101010101010101010161 +:10C0D0000102020200020202020202020202020243 +:10C0E0000001010101010101010101010101010141 +:10C0F0000202020202020202020202020202020220 +:10C100000201010101010202020202020202010215 +:10C11000000000000000000000000000000000001F +:10C1200002020202020202020202020202020200F1 +:10C1300002010101010101000000000000000101F5 +:10C1400002020202020202020002020202020202D1 +:10C1500002020202020100010202020102020102C5 +:10C1600002010201020101010202020201010101B8 +:10C1700002020200000201010201020102020202A7 +:10C180000102020202020202000202020202020292 +:10C190000102020202020202010102010202020283 +:10C1A000020202020202020202020202020202026F +:10C1B0000002020201020202020101020100000269 +:10C1C000000102020101010101010101010102015D +:10C1D0000202020200020202020202020202020241 +:10C1E0000001010101010101010101010101010140 +:10C1F000020202020202020202020202020202021F +:10C200000201020102010202020202020202020211 +:10C21000000001000000000000000000000000001D +:10C2200002020202020202020202020202020200F0 +:10C2300002010101010201000000000000000202F1 +:10C2400002020202020202020002020202020202D0 +:10C2500002020202020100020202020202020102C2 +:10C2600002010201010101010202020201010101B8 +:10C2700002020200000202010201020202020202A4 +:10C280000202020202020202000202020202020290 +:10C290000102020202020202010202020202020280 +:10C2A000020202020202020202020202020202026E +:10C2B0000002020201020202020102020100000267 +:10C2C0000102020202020202010102010202020252 +:10C2D0000202020200020202020202020202020240 +:10C2E000010101010101010101010101010101013E +:10C2F000020202020202020202020202020202021E +:10C30000020102010202020202020202020202020F +:10C31000000001000000000000000000000000001C +:10C3200002020202020202020202020202020200EF +:10C3300002020201010201000000000000000202EE +:10C3400002020202020202020002020202020202CF +:10C3500002020202020200020202020202020102C0 +:10C3600002020201010201010202020201010201B4 +:10C3700002020201000202020202020202020202A0 +:10C38000020202020202020200020202020202028F +:10C39000020202020202020201020202020202027E +:10C3A000020202020202020202020202020202026D +:10C3B0000002020201020202020102020100010265 +:10C3C000020202020202020201010202020202024F +:10C3D000020202020102020202020202020202023E +:10C3E000010101010101010101010101010101013D +:10C3F000020202020202020202020202020202021D +:10C40000020202020202020202020202020202020C +:10C410000000010000000000000200000000000019 +:10C4200002020202020202020202020202020200EE +:10C4300002020201010202000000000000000202EC +:10C4400002020202020202020002020202020202CE +:10C4500002020202020200020202020202020202BE +:10C4600002020201010202020202020202010202AF +:10C47000020202020002020202020202020202029E +:10C48000020202020202020201020202020202028D +:10C49000020202020202020202020202020202027C +:10C4A000020202020202020202020202020202026C +:10C4B0000002020202020202020102020100010263 +:10C4C000020202020202020202020202020202024C +:10C4D000020202020102020202020202020202023D +:10C4E0000101010202020202010101010102020135 +:10C4F000020202020202020202020202020202021C +:10C50000020202020202020202020202020202020B +:10C510000001010000010000000100020100000014 +:10C5200002020202020202020202020202020200ED +:10C5300002020202020202000000000000000202E9 +:10C5400002020202020202020002020202020202CD +:10C5500002020202020200020202020202020202BD +:10C5600002020202010202020202020202020202AC +:10C57000020202020202020202020202020202029B +:10C58000020202020202020201020202020202028C +:10C59000020202020202020202020202020202027B +:10C5A000020202020202020202020202020202026B +:10C5B000020202020202020202020202020001025E +:10C5C000020202020202020202020202020202024B +:10C5D000020202020202020202020202020202023B +:10C5E000010202020202020202020202020202022C +:10C5F000020202020202020202020202020202021B +:10C60000020202020202020202020202020202020A +:10C610000001010000010000000100010100010112 +:10C6200002020202020202020202020202020200EC +:10C6300002020202020202000000000000000202E8 +:10C6400002020202020202020102020202020202CB +:10C6500002020202020200020202020202020202BC +:10C6600002020202020202020202020202020202AA +:10C67000020202020202020202020202020202029A +:10C68000020202020202020201020202020202028B +:10C69000020202020202020202020202020202027A +:10C6A000020202020202020202020202020202026A +:10C6B000020202020202020202020202020001025D +:10C6C000020202020202020202020202020202024A +:10C6D000020202020202020202020202020202023A +:10C6E000010202020202020202020202020202022B +:10C6F000020202020202020202020202020202021A +:10C700000202020202020202020202020202020209 +:10C71000010101000001000002010101010001010D +:10C7200001020202020202020202020101010200EF +:10C7300002020202020202010000000000000202E6 +:10C7400002020202020202020202020202020202C9 +:10C7500002020202010202020202020202020202BA +:10C7600002020202020202020202020202020202A9 +:10C770000202020202020202020202020202020299 +:10C780000202020202020202020202020202020289 +:10C790000202020202020202020202020202020279 +:10C7A0000202020202020202020202020202020269 +:10C7B000020202020202020202020202020001025C +:10C7C0000202020202020202020202020202020249 +:10C7D0000202020202020202020202020202020239 +:10C7E0000202020202020202020202020202020229 +:10C7F0000202020202020202020202020202020219 +:10C800000202020202020202020202020202020208 +:10C81000010101000101000001010101000101010C +:10C8200001010101010201020101010101010200F6 +:10C8300002020202020202010001000000000202E4 +:10C8400002020202020202020202020202020202C8 +:10C8500002020201010202020202020202020202BA +:10C8600002020202020202020202020202020202A8 +:10C870000202020202020202020202020202020298 +:10C880000202020202020202020202020202020288 +:10C890000202020202020202020202020202020278 +:10C8A0000202020202020202020202020202020268 +:10C8B000020202020202020202020202020002025A +:10C8C0000202020202020202020202020202020248 +:10C8D0000202020202020202020202020202020238 +:10C8E0000202020202020202020202020202020228 +:10C8F0000202020202020202020202020202020218 +:10C900000202020202020202020202020202020207 +:10C910000200020001010101010101000001010109 +:10C9200001010101010201010101010101010100F7 +:10C9300002020202020202020002010000010202DF +:10C9400002020202020202020202020202020202C7 +:10C9500001020201020202020202020202020202B9 +:10C9600002020202020202020202020202020202A7 +:10C970000202020202020202020202020202020297 +:10C980000202020202020202020202020202020287 +:10C990000202020202020202020202020202020277 +:10C9A0000202020202020202020202020202020267 +:10C9B0000202020202020202020202020200020259 +:10C9C0000202020202020202020202020202020247 +:10C9D0000202020202020202020202020202020237 +:10C9E0000202020202020202020202020202020227 +:10C9F0000102020202020202020202020202020218 +:10CA00000202020202020202020202020202020206 +:10CA10000202020100010101010000000001010108 +:10CA200001010101010101010101010101010100F7 +:10CA300002020202020202020202020200020202D8 +:10CA400002020202020202020202020202020202C6 +:10CA500002010102020101010101010101010101C3 +:10CA600002020202020202020202020202020202A6 +:10CA700001010101010101010101010101010101A6 +:10CA80000202020202020202020202020202020286 +:10CA90000202020202020202020202020202020276 +:10CAA0000202020202020202020202020202020266 +:10CAB0000202020202020202020202020200020258 +:10CAC0000202020202020202020202020202020246 +:10CAD0000101010101010101010101010101010146 +:10CAE0000202020202020202020202020202020226 +:10CAF0000201010101020202010101010101020121 +:10CB00000202020202020202020202020202020205 +:10CB10000202020100020101000000000000010108 +:10CB200001010101010101010101010101010100F6 +:10CB300002020202020202020202020202020202D5 +:10CB400002020202020202020202020202020202C5 +:10CB500000020202000202020202020202020202B9 +:10CB600002020202020202020101010101010202AB +:10CB70000202020202020202020202020202020295 +:10CB80000202020202020202020202020202020285 +:10CB90000202020202020202020202020202020275 +:10CBA0000202020202020202020202020202020265 +:10CBB0000202020202020202020202020202020255 +:10CBC0000101010101010101010101010101010155 +:10CBD0000202020202020202020202020202020235 +:10CBE0000202020202020202020202020202020225 +:10CBF000000202020201010102020202020201021B +:10CC00000202020202020202020202020202020204 +:10CC1000020202000002000000020000000000000A +:10CC200000010101010101010101010000000100F9 +:10CC300001020202020202020202020202020202D5 +:10CC400001010101010101010101010101010101D4 +:10CC500000000000000000000000000000000000D4 +:10CC600000020202020202020202020202020202A6 +:10CC700000000000000000000000000000000000B4 +:10CC80000202020202020202020202020202020284 +:10CC90000202020202020202020202020202020274 +:10CCA0000202020202020202020202020202020264 +:10CCB0000202020202020202020202020202020254 +:10CCC0000202020202020202020202020202020244 +:10CCD0000000000000000000000000000000000054 +:10CCE0000202020202020202020202020202020224 +:10CCF000000000000002020200000000000002002C +:10CD00000101010101010101010101010101010113 +:10CD10000202020202020000000200000000020201 +:10CD20000000000000010000000000000000000002 +:10CD300001020202020202020202020202020202D4 +:10CD400002020202020202020202020202020202C3 +:10CD500001000000000000000000000000000000D2 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD80000202020202020202020202020202020283 +:10CD90000101010101010101010101010101010183 +:10CDA0000000000000000000000000000000000083 +:10CDB0000202020200020202020202020202020255 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000202020202020202020202020202020223 +:10CDF0000000000000000000000000000000000033 +:10CE00000202020202020202020202020202020202 +:10CE100002020202020202020202020202020202F2 +:10CE20000000000000000000000000000000000002 +:10CE300001010101010101010101010101010101E2 +:10CE400000000000000000000000000000000000E2 +:10CE500001010101010101010101010101010101C2 +:10CE600001000000000000000000000000000000C1 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000202020202020202020202020202020272 +:10CEA0000000000000000000000000000000000082 +:10CEB0000101010101010101010101010101010162 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000202020202020202020202020202020222 +:10CEF0000101010101010101010101010101010122 +:10CF00000000000000000000000000000000000021 +:10CF100002020202020202020202020202020202F1 +:10CF20000000000000000000000000000000000001 +:10CF300001010101010101010101010101010101E1 +:10CF400000000000000000000000000000000000E1 +:10CF500001010101010101010101010101010101C1 +:10CF600001010101010101010101010101010101B1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB0000101010101010101010101010101010161 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000202020202020202020202020202020221 +:10CFF0000101010101010101010101010101010121 +:10D000000000000000000000000000000000000020 +:10D0100002020202020202020202020202020202F0 +:10D020000000000000000000000000000000000000 +:10D0300001010101010101010101010101010101E0 +:10D0400001010101010101010101010101010101D0 +:10D0500001010101010101010101010101010101C0 +:10D0600001010101010101010101010101010101B0 +:10D0700001010101010101010101010101010101A0 +:10D080000101010101010101010101010101010190 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B0000101010101010101010101010101010160 +:10D0C0000000000000000000000000000000000060 +:10D0D0000101010101010101010101010101010140 +:10D0E0000202020202020202020202020202020220 +:10D0F0000101010101010101010101010101010120 +:10D10000000000000000000000000000000000001F +:10D1100002020202020202020202020202020202EF +:10D1200001000000000000000000000101010000FB +:10D1300001010101010101010101010101010101DF +:10D1400001010101010101010101010101010101CF +:10D1500001010101010101010101010101010101BF +:10D1600001010101010101010101010101010101AF +:10D17000010101010101010101010101010101019F +:10D18000010101010101010101010101010101018F +:10D19000010101010101010101010101010101017F +:10D1A000010101010101010101010101010101016F +:10D1B000010101010101010101010101010101015F +:10D1C000000000000000000000000000000000005F +:10D1D000010101010101010101010101010101013F +:10D1E000020202020202020202020202020202021F +:10D1F000010101010101010101010101010101011F +:10D20000000000000000000000000000000000001E +:10D2100002020202020202020202020202020202EE +:10D2200001010101010001010101010101010100F0 +:10D2300001010101010101010101010101010101DE +:10D2400001010101010101010101010101010101CE +:10D2500001010101010101010101010101010101BE +:10D2600001010101010101010101010101010101AE +:10D27000010101010101010101010101010101019E +:10D28000010101010101010101010101010101018E +:10D29000010101010101010101010101010101017E +:10D2A000010101010101010101010101010101016E +:10D2B000010101010101010101010101010101015E +:10D2C000010101010101010101010101010101014E +:10D2D000010101010101010101010101010101013E +:10D2E000020202020202020202020202020202021E +:10D2F000010101010101010101010101010101011E +:10D30000010101010101010101010101010101010D +:10D31000000000000000000000000000000000000D +:10D3200001010101010101010101010101010101ED +:10D3300001010101010101010101010101010101DD +:10D3400001010101010101010101010101010101CD +:10D3500001010101010101010101010101010101BD +:10D3600001010101010101010101010101010101AD +:10D37000010101010101010101010101010101019D +:10D38000010101010101010101010101010101018D +:10D39000010101010101010101010101010101017D +:10D3A000010101010101010101010101010101016D +:10D3B000010101010101010101010101010101015D +:10D3C000010101010101010101010101010101014D +:10D3D000010101010101010101010101010101013D +:10D3E000010101010101010101010101010101012D +:10D3F000010101010101010101010101010101011D +:10D40000010101010101010101010101010101010C +:10D41000000000000000000000000000000000000C +:10D4200001010101010101010101010101010101EC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500002020202020202020202020202020202AC +:10D46000020202020202020202020202020202029C +:10D47000020202020202020202020202020202028C +:10D48000020202020202020202020202020202027C +:10D49000020202020202020202020202020202026C +:10D4A000020202020202020202020202020202025C +:10D4B000020202020202020202020202020202024C +:10D4C000020202020202020202020202020202023C +:10D4D000020202020202020202020202020202022C +:10D4E000000000000000000000000000000000003C +:10D4F000020202020202020202020202020202020C +:10D5000002020202020202020202020202020202FB +:10D51000000000000000000000000000000000000B +:10D5200001010101010101010101010101010101EB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000020202020202020202020202020202024B +:10D5C000000000000000000000000000000000005B +:10D5D000020202020202020202020202020202022B +:10D5E000000000000000000000000000000000003B +:10D5F000020202020202020202020202020202020B +:10D6000002020202020202020202020202020202FA +:10D61000000000000000000000000000000000000A +:10D6200001010101010101010101010101010101EA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F000020202020202020202020202020202020A +:10D700000000000000000000000000000000000019 +:10D710000000000000000000000000000000000009 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000000000000000000B9 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D810000000000000000000000000000000000008 +:10D8200030000000000000000000000000000000C8 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000000000000000000B8 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000001000000000000000000000000000087 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000010000000000000047 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D910000000000000000000000000000000000007 +:10D9200000000000000000000000000000000000F7 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000000000000000000B7 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000001000000000000000000000000000086 +:10D9A0000000000000000000000000000000000077 +:10D9B0000000000000000000000000000000000067 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000100000000010000000000000045 +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA10000000000000000000000000000000000006 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000000000000000000B6 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000001000000000000000000000000000085 +:10DAA0000000000000000000000000000000000076 +:10DAB0000000000000000000000000000000000066 +:10DAC0000000000000000000000000000001000154 +:10DAD0000000000100000000010000000000000044 +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB10000000000000000000000000000000000005 +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000000000000000000B5 +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000010000000000000094 +:10DB90000001000000000000000000000000000084 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000000000000000000065 +:10DBC0000100000000010000000000000001000151 +:10DBD0000000000101000000010000000000000042 +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC10000000000000000000000000000000000004 +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000000000000000000B4 +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000010000000000000093 +:10DC90000001000000000000000000000000000083 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000000000000000000064 +:10DCC0000100000000010000000000000001000150 +:10DCD000000000010101010001000000000000003F +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD10000000010000000001000000000000000001 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000000000000000000B3 +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000010000000000000092 +:10DD90000001000000000000000000000000000082 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000000000000000000063 +:10DDC000010000000001000000000000000100014F +:10DDD000000001010101010101000000000000003C +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000001000000000000000100000000000010 +:10DE100000010100000000010000000000000100FE +:10DE200000000000000000000100000000000000F1 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000000000000000000B2 +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000010000000000000091 +:10DE90000001000000000000000000000000000081 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000000000000000010061 +:10DEC000010000000001000000000000000100014E +:10DED000000001010101010101000000000000003B +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000100000000000000000021 +:10DF0000000100000000000000010000000000000F +:10DF100000010101000000010000000000000100FC +:10DF200000000000000000000101000000000000EF +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000001000000000100000000000000AF +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000010000000000000090 +:10DF90000001000000000000000000000000000080 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000000000000000010060 +:10DFC000010000000001010000000000000101014B +:10DFD000000001010101010101000000000000003A +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000100000000000000000020 +:10E00000000100000000000000010000000000000E +:10E0100000010101000000010000000000000100FB +:10E0200000000000000000000101000000000000EE +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000001000100000100000000000000AD +:10E0700000000000000000000000000000000000A0 +:10E08000000000000000000001000000000000008F +:10E09000000100000000000000000000000000007F +:10E0A0000000000000000000000000000000000070 +:10E0B000000000000000000000000000000001005F +:10E0C0000100000100010101000000000001010148 +:10E0D0000100010101010101010000000000000038 +:10E0E0000000000000000000000000000000000030 +:10E0F000000000000001010000000000000000001E +:10E10000000100000000000001010000000000000C +:10E1100000010101010000010000000000000100F9 +:10E1200000000000000000000101000000000000ED +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E1600000000001000100010100000000000000AB +:10E17000000000000000000000000000000000009F +:10E18000000000000000000001000000000000008E +:10E19000000100000000000000000000000000007E +:10E1A000000000000000000000000000000000006F +:10E1B000000000010000000000000000000001005D +:10E1C0000100000100010101000000000001010147 +:10E1D0000100010101010101010000000000000037 +:10E1E000000000000000000000000000000000002F +:10E1F000000000000001010000000000000000001D +:10E20000000100000000000001010000000000000B +:10E2100000010101010100010000000000000100F7 +:10E2200000000000000000000201000100000000EA +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E2600000000001000101010100000000000000A9 +:10E27000000000000000000000000000000000009E +:10E28000000000000000000001000000000000008D +:10E29000000100000000000000000000000000007D +:10E2A000000000010000000000000000000000006D +:10E2B000000000010001000000000000000001005B +:10E2C0000100010100010101000000000001010145 +:10E2D0000100010101010101010000000000000036 +:10E2E000000000000000000000000000000000002E +:10E2F000000000000001010000000000000000001C +:10E30000000100000000000001010000000000000A +:10E3100000010101010100010000000000000100F6 +:10E3200000000001000000000201000100000000E8 +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000100BC +:10E3600000000101010101010101000000000000A5 +:10E37000000000000000000000000000000000009D +:10E38000000000000000000001000000000000008C +:10E39000000100010000000000000000000000007B +:10E3A000000000010000000000000000000000006C +:10E3B0000000000100010001000000000000010059 +:10E3C0000100010100010101000000000001010144 +:10E3D0000100010101010101010000000000000035 +:10E3E000000000000000000000000000000000002D +:10E3F000000000010001010000000000000000001A +:10E400000001000000000000010100000000000009 +:10E4100001010101010101010000010000000100F2 +:10E4200000000001000000000201000100000100E6 +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000100000000000001010100B8 +:10E4600000010101010101010101000000000000A3 +:10E47000000000000000000000000000000000009C +:10E48000000000000000000001000000000000008B +:10E49000000100010000000000000000000000007A +:10E4A000000000010000000100000000000000006A +:10E4B0000000000100010101000000000000010057 +:10E4C0000100010100010101000000000001010143 +:10E4D0000100010101010101020000000000000033 +:10E4E000000000000000000000000000010000002B +:10E4F0000000000100010100000000000000000019 +:10E500000001000000000000010100000000000008 +:10E5100001010101010101010000010000000100F1 +:10E5200000000001000000000202000101010101E1 +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000001000100010000000001010100B5 +:10E5600000010101010101010101000000000000A2 +:10E57000000000000000000000000000000000009B +:10E580000000000100000000010000000000000089 +:10E590000001000100000000000000000000000079 +:10E5A0000001000100010101000000000000010065 +:10E5B0000000010101010101000000000000010153 +:10E5C0000100010100010101000000000001010142 +:10E5D0000100010101010101020000000000000032 +:10E5E000000000000000000000000000010000002A +:10E5F0000000000100010101000000000000000017 +:10E600000001000000000000010100000001000105 +:10E6100001010101010101010000010000000100F0 +:10E6200000000001000000000202000101010101E0 +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000001000100010000000001010101B3 +:10E6600001010101010101010101000000000000A0 +:10E67000000000000000000000000000000000009A +:10E680000000000100000000010000000000000088 +:10E690000001000100000000000000000000010077 +:10E6A0000001010101010101000000000101010060 +:10E6B0000000010101010101000000000000010152 +:10E6C0000100010100010101000000000001010141 +:10E6D0000100010101010101020000000000000031 +:10E6E0000000000100000000000000000100000028 +:10E6F0000000000100010101000000000000000016 +:10E700000001000000000000010101010001010101 +:10E7100001010101010101010000010000000100EF +:10E7200000000001000000000202000101010101DF +:10E7300001010000000000000000000000000000D7 +:10E7400000000000000000000000000000000100C8 +:10E7500000000101010100010000010101010101AE +:10E76000010101010101010101010000000000009F +:10E770000000000000000000000000000000000099 +:10E780000000000100000000020000000000000086 +:10E790000002000100000000000000000101010172 +:10E7A000010101010101010100000101010101005C +:10E7B0000000010101010101000000000000010151 +:10E7C000010101010001010101000000000101013E +:10E7D0000100010101010101020000000000000030 +:10E7E0000000000100010000000000000100000026 +:10E7F0000000000100010101000000000000000015 +:10E8000001010000000000000101010101010101FE +:10E8100001010101010101010000010000000100EE +:10E8200000000001000000000202000201010101DD +:10E8300001010101010000000100000000000000D2 +:10E8400000000001000000010000000001010100C3 +:10E8500000000101010101010001010101010101AB +:10E86000010101010101010102010000000000009D +:10E870000000000000000000000000000000000098 +:10E880000000000100000000020000000000000085 +:10E89000000200010001000000000100010101016F +:10E8A0000101010101010101000101010101010159 +:10E8B000010101010101010100000000000001014E +:10E8C000010101010001010101000000000201023B +:10E8D000010001010101010102000000000000002F +:10E8E0000000000100010001000000000100000024 +:10E8F0000000000100010101000000000000000014 +:10E9000001010000000000000101010101010101FD +:10E9100001010101010101010000010000000100ED +:10E9200000000001000000000202000201010101DC +:10E9300001010101010000000100000000000000D1 +:10E9400000000001000100010000000001010100C1 +:10E9500000000101010101010001010101010101AA +:10E96000010101010101010102010000000000009C +:10E970000000000000000000000000000000000097 +:10E980000000000100000000020000000000000084 +:10E99000000201010001000100000100010101016C +:10E9A0000101010101010101000101010101010158 +:10E9B000010101010101010100000000000001014D +:10E9C0000201010100010101010000000002010239 +:10E9D000010001020201010102000000000000002C +:10E9E0000000000100010101000000000100010021 +:10E9F0000000010100010101000100000000000011 +:10EA000001010000000000000101010101010101FC +:10EA100001010101010101010000010000000000ED +:10EA200000000001000000000202010201010102D9 +:10EA300002010101010000010100000000000100CD +:10EA400000000001000100010000000001010100C0 +:10EA500000010101010101010001010101010101A8 +:10EA6000010101010101010102010000000000009B +:10EA70000000000000000000000000000000000096 +:10EA80000000000100000000020000000000000083 +:10EA9000000201010001000100000101010101016A +:10EAA0000101010101010101000101010101010157 +:10EAB000010101010101010100000100000001014B +:10EAC0000201010101020101010000000102010235 +:10EAD0000101020202020201020000000000000027 +:10EAE0000000000100010101000000000100010020 +:10EAF0000000010100010101000100000000000010 +:10EB000001010100000000000101010101010101FA +:10EB100001010101010101010001010000000000EB +:10EB200000000001000000000202010201010102D8 +:10EB300002020101010000010100000001000100CA +:10EB400000000001000100010000000001010100BF +:10EB500000010101010101010001010101010101A7 +:10EB6000010101010101010102010000000000009A +:10EB70000000000000000000000000000000000095 +:10EB80000000000100000000020000000000010081 +:10EB90000002010100010001000101010101010168 +:10EBA0000101010101010101000101010101010156 +:10EBB0000101010101010101000001000000020149 +:10EBC0000201010101020101020001010102020230 +:10EBD0000201020202020202020000000100000023 +:10EBE000000200010001010100000100010001001C +:10EBF000000001010101010100010000000000000E +:10EC000001020100000000000202010101010101F6 +:10EC100001010101010101010001010000010000E9 +:10EC200000000001000000000202010202020202D4 +:10EC300002020201010000010200000001000100C7 +:10EC400000000001010100010000000001010100BD +:10EC500001010101010101010001010101010101A5 +:10EC60000101010101010101020200000000000098 +:10EC70000000000000000000000000000000000094 +:10EC8000000000010001000002000000010101007D +:10EC90000002010100010001000101010101010167 +:10ECA0000101010101010101000101010101010155 +:10ECB0000101010101010101000001000000020148 +:10ECC000020101010102020102010101010202022D +:10ECD0000201020202020202020000000100010021 +:10ECE0000002000101010101000001000100010119 +:10ECF000010001010101010100010101000000000A +:10ED000001020100010000010202010101010101F3 +:10ED100001020201010101010001010000010000E6 +:10ED200001000001000000000202020202020202D1 +:10ED300002020201020000010200000001000100C5 +:10ED400000000001010101010000010101010100B9 +:10ED500001010101010101010101010101010101A3 +:10ED60000101010101010101020200000000000196 +:10ED7000010100000000000100000001000000008F +:10ED8000000000010001000102000000010101007B +:10ED90000002010101010001000101010101010165 +:10EDA0000101010101010101000101010101010154 +:10EDB0000101010101010101000001000001020146 +:10EDC0000201020201020202020101010102020229 +:10EDD0000201020202020202020000000100010020 +:10EDE0000001000101010101000001000100010119 +:10EDF0000100010101010201000101010001000007 +:10EE000001020100010000010202010101010101F2 +:10EE100001020201010101020001000000010000E5 +:10EE200001000001000000000202020202020202D0 +:10EE300002020201020000000200000001000100C5 +:10EE400000000001010101010001010101010100B7 +:10EE500001010101010101010101010101010101A2 +:10EE60000101010101010101020201000000000194 +:10EE7000010100000000000100000001000000018D +:10EE80000101000100010001020100000101010077 +:10EE90000002010101010001000101010101010164 +:10EEA0000101010101010101000101010101010153 +:10EEB0000101010101010101020001010001020241 +:10EEC0000201020201020202020101010102020228 +:10EED000020102020202020202000100010001001E +:10EEE0000001010101010101000001000100010117 +:10EEF0000100010101020201000101010001010004 +:10EF000001020100010000010202010101010101F1 +:10EF100001020202020101020001000000010000E2 +:10EF200001000001000000000202020202020202CF +:10EF300002020202020000000200000001000102C1 +:10EF400000000001010101010001010101010100B6 +:10EF500001010101010101010101010101010101A1 +:10EF60000101010101010101020201000000000193 +:10EF7000010100000000000100000001000000018C +:10EF80000101000101010001020101010101010073 +:10EF90000002010101010001000101010101010163 +:10EFA0000101010101010101000101010101010152 +:10EFB000010101010101010102000101010102023F +:10EFC0000202020201020202020101010102020226 +:10EFD000020102020202020202000100010001001D +:10EFE0000001010101010101000001010200010114 +:10EFF0000100010101020201000101010101010002 +:10F0000001020100010101010202010101010101EE +:10F0100002020202020201020001000000010000DF +:10F0200001000001000000000202020202020202CE +:10F0300002020202020000000200000001000102C0 +:10F0400000000001010101010001010101010100B5 +:10F0500001010101010101010101010101010101A0 +:10F06000010101020102010102020101000000018F +:10F070000101010002000101000000010100000186 +:10F080000101000101010001020101010101010072 +:10F090000002010201010001010101010101010160 +:10F0A0000101010101010101000101010101010151 +:10F0B000010101020102010102000201010102023B +:10F0C0000202020201020202020202020202020221 +:10F0D000020202020202020202000100010001001B +:10F0E0000001010101010101000101010200010112 +:10F0F00001000102010202010002010101010100FF +:10F1000002020100010101010202020201020102E8 +:10F1100002020202020202020001000000010001DC +:10F1200001000000000000000202020202020202CE +:10F1300002020202020000000201000001000101BF +:10F1400000000001010101010101010101010100B3 +:10F15000010101010102010101010101020202019B +:10F160000102020202020202020201010001010187 +:10F170000101010002010101000000010100000184 +:10F18000010101020101000102010101010101006F +:10F19000000201020101000101010101010101015F +:10F1A0000101010101010101010202020202020149 +:10F1B0000101020202020202020102010101020235 +:10F1C000020202020202020202020202020202021F +:10F1D0000202020202020202020101000100010019 +:10F1E000020101020102010100010101020001010D +:10F1F00001000102010202020002010101010101FC +:10F2000002020100010101010202020202020202E5 +:10F2100002020202020202020001000100010001DA +:10F2200001000000000000000202020202020202CD +:10F2300002020202020000000201000002000201BC +:10F2400000000002010201020101010102020200AC +:10F250000101020202020102010202020202020292 +:10F260000202020202020202020202010001010283 +:10F270000202010001010101000000020101000180 +:10F28000010101020101000102010101010101006E +:10F29000000202020102000101010101010101015C +:10F2A0000101010101010101010202020202020247 +:10F2B0000202020202020202020102020102020230 +:10F2C000020202020202020202020202020202021E +:10F2D0000202020202020202020101000200010017 +:10F2E0000201010201020202000102010201020107 +:10F2F00001010202010202020002020201010101F7 +:10F3000002020200010101010202020202020202E3 +:10F3100002020202020202020001000100010001D9 +:10F3200001000000000001000202020202020202CB +:10F3300002020202020100000201000002000201BA +:10F3400000000002020201020101010102020200AA +:10F35000010202020202020202020202020202028E +:10F360000202020202020202020202020101010280 +:10F37000020201000101010102000102010100027B +:10F380000202010201010001020201010202020067 +:10F39000000202020102000201010101010101015A +:10F3A0000102010201010101010202020202020244 +:10F3B000020202020202020202020202020202022D +:10F3C000020202020202020202020202020202021D +:10F3D0000202020202020202020102000201020013 +:10F3E0000101010202020202000102010201020205 +:10F3F00002010202020202020202020201020101F1 +:10F4000002020200020101010202020202020202E1 +:10F4100002020202020202020000000100010001D9 +:10F4200001000000000001000102020202020202CB +:10F4300002020202020100000202010002000201B7 +:10F4400000000102020202020202020202020200A3 +:10F45000020202020202020202020202020202028C +:10F46000020202020202020202020202010201027E +:10F470000202020101010102020101020101000276 +:10F480000202010202020101020202020202020061 +:10F490000002020202020002010102010202020253 +:10F4A000020202020202020202020202020202023C +:10F4B000020202020202020202020202020202022C +:10F4C000020202020202020202020202020202021C +:10F4D0000202020202020202020202010201020010 +:10F4E0000102020202020202000202020201020200 +:10F4F00002010202020202020202020202020201EE +:10F5000002020200020101020202020202020202DF +:10F5100002020202020202020000000100010001D8 +:10F5200001000000000001000101020202020202CB +:10F5300001020202020102000202010002000201B5 +:10F5400000000102020202020202020202020200A2 +:10F55000020202020202020202020202020202028B +:10F56000020202020202020202020202020202027B +:10F570000202020101020202020101020201000272 +:10F58000020202020202010202020202020202005E +:10F590000002020202020002010202020202020250 +:10F5A000020202020202020202020202020202023B +:10F5B000020202020202020202020202020202022B +:10F5C000020202020202020202020202020202021B +:10F5D000020202020202020202020201020102000F +:10F5E00001020202020202020202020202010202FD +:10F5F00002010202020202020202020202020202EC +:10F6000002020200020202020202020202020202DC +:10F6100002020202020202020000000100010001D7 +:10F6200001000000000001010101020102020201CB +:10F6300001010102020102000202020002000202B4 +:10F6400000000102020202020202020202020200A1 +:10F65000020202020202020202020202020202028A +:10F66000020202020202020202020202020202027A +:10F67000020202010202020202020202020200026D +:10F68000020202020202010202020202020202005D +:10F69000000202020202010202020202020202024D +:10F6A000020202020202020202020202020202023A +:10F6B000020202020202020202020202020202022A +:10F6C000020202020202020202020202020202021A +:10F6D000020202020202020202020202020202000C +:10F6E00001020202020202020202020202020202FB +:10F6F00002020202020202020202020202020202EA +:10F7000002020200020202020202020202020202DB +:10F7100002020202020202020000000100000001D7 +:10F7200001000000000001010101010102020201CB +:10F7300001010102010102000202020002010202B3 +:10F74000000002020202020202020202020202009F +:10F750000202020202020202020202020202020289 +:10F760000202020202020202020202020202020279 +:10F77000020202010202020202020202020201026B +:10F78000020202020202010202020202020202005C +:10F79000000202020202010202020202020202024C +:10F7A0000202020202020202020202020202020239 +:10F7B000020202020202020201020202020202022A +:10F7C0000202020202020202020202020202020219 +:10F7D000020202020202020202020202020202000B +:10F7E00002020202020202020202020202020202F9 +:10F7F00002020202020202020202020202020202E9 +:10F8000002020200020202020202020202020202DA +:10F8100002020202020202020002020100020201CE +:10F8200002010102000001010101010101010101C8 +:10F8300001010101010201000202020202020202B0 +:10F84000000002020202020202020202020202009E +:10F850000202020202020202020202020202020288 +:10F860000202020202020202020202020202020278 +:10F870000202020202020202020202020202010269 +:10F88000020202020202020202020202020202005A +:10F89000000202020202010202020202020202024B +:10F8A0000202020202020202020202020202020238 +:10F8B0000202020202020202020202020202020228 +:10F8C0000202020202020202010202020202020219 +:10F8D000020202020202020202020202020202000A +:10F8E00002020202020202020202020202020202F8 +:10F8F00002020202020202020202020202020202E8 +:10F9000002020201020202020202020202020202D8 +:10F9100002020202020202020002020101020201CC +:10F9200002010102000001010101010101010101C7 +:10F9300001010101010201000202020202020202AF +:10F940000202020202020202020202020202020099 +:10F950000202020202020202020202020202020287 +:10F960000202020202020202020202020202020277 +:10F970000202020202020202020202020202020267 +:10F980000202020202020202020202020202020059 +:10F990000002020202020202020202020202020249 +:10F9A0000202020202020202020202020202020237 +:10F9B0000202020202020202000202020202020229 +:10F9C0000202020202020202010202020202020218 +:10F9D0000202020202020202010202020202020208 +:10F9E00002020202020202020202020202020202F7 +:10F9F00002020202020202020202020202020202E7 +:10FA000002020201020202020202020202020202D7 +:10FA100002020202020202020102020201020202C8 +:10FA200002010102000001010101010101010101C6 +:10FA300001010101010201000202020202020202AE +:10FA40000202020202020202020202020202020197 +:10FA50000202020202020202020202020202020286 +:10FA60000202020202020202020202020202020276 +:10FA70000202020202020202020202020202020266 +:10FA80000202020202020202020202020202020256 +:10FA90000201020202020202020202020202020247 +:10FAA0000202020202020202020202020202020236 +:10FAB0000202020202020202000202020202020228 +:10FAC000020202020202020202010101010101011D +:10FAD000010101010101010102020202020202020E +:10FAE00002020202020202020202020202020202F6 +:10FAF00002020202020202020202020202020202E6 +:10FB000002020202020202020202020202020202D5 +:10FB100002020202020202020102020201020202C7 +:10FB200002010102000001010000010101010101C7 +:10FB300000010101010201000002020202020202B0 +:10FB40000202020202020202020202020202020295 +:10FB50000202020202020202020202020202020285 +:10FB6000020202020202020201010101010102017C +:10FB7000010101020101020201020201020202016D +:10FB80000101010201020202020202020202020259 +:10FB90000202020202020202020202020202020245 +:10FBA0000202020202020202020202020202020235 +:10FBB0000202020202020202000000000000000035 +:10FBC0000000000000000000020202020202020225 +:10FBD0000202020202020202000202020202020207 +:10FBE00002020202020202020202020202020202F5 +:10FBF00002020202020202020102020202020202E6 +:10FC000002020202020202020202020202020202D4 +:10FC100002020202020202020202020201020202C5 +:10FC200002010102000002010000000001010100C8 +:10FC300000000001000101000002020202020202B3 +:10FC40000202020202020202020202020202020294 +:10FC50000202020202020202020202020202020284 +:10FC6000020202020202020202010101010101017B +:10FC7000010101020101010101020201020202016E +:10FC80000101010201020202020202020202020258 +:10FC90000200020202020202020202020202020246 +:10FCA0000202020202020202020202020202020234 +:10FCB0000202020202020202000000000000000034 +:10FCC0000000000000000000000000000000000034 +:10FCD0000000000000000000000202020202020216 +:10FCE00002020202020202020202020202020202F4 +:10FCF00002020202020202020201010101010101EB +:10FD000001010101010101010202020202020202DB +:10FD100002020202020202020202020201020202C4 +:10FD200002000102010002010000000000000000CA +:10FD300000000000000100000100000000000000C1 +:10FD400000000000000000000202020202020202A3 +:10FD50000202020202020202020202020202020283 +:10FD60000202020202020202000202020202020275 +:10FD70000202020102020202020101020101010269 +:10FD80000202020102010101000202020202020259 +:10FD90000200020202020202020202020202020245 +:10FDA0000202020202020202020202020202020233 +:10FDB0000202020202020202000000000000000033 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF00000000000000000000002020202020202F5 +:10FE000002020202020202020101010101010101DA +:10FE100001010101010101010202020202020202CA +:10FE200002020202010102020000000000000000C4 +:10FE300000000000000100000100000000000000C0 +:10FE400000000000000000000202020202020202A2 +:10FE50000202020202020202020202020202020282 +:10FE60000202020202020202000202020202000276 +:10FE70000202020202020000020202020202020266 +:10FE80000202020202020202000000000000000062 +:10FE90000000000000000000020202020202020252 +:10FEA0000202020202020202000000000000000042 +:10FEB0000000000000000000000000000000000042 +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000202020202020202E1 +:10FF100002020202020202020202020202020202C1 +:10FF200002020202000102020000000000000000C4 +:10FF300000000000000000000101010101010101B9 +:10FF400001010101010101010101010101010101A1 +:10FF50000101010101010101020202020202020289 +:10FF60000202020202020202010000000000000080 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000020202020202020251 +:10FFA0000202020202020202000000000000000041 +:10FFB0000000000000000000010101010101010139 +:10FFC0000101010101010101000000000000000029 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:02000002B0004C +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000202020202020202D0 +:1000200002020202000102020101000000000000C1 +:1000300001000000000000000101010101010101B7 +:100040000101010101010101020202020202020298 +:100050000202020202020202020202020202020280 +:100060000202020202020202010101010101010178 +:100070000101010101010101000000000000000078 +:10008000000000000000000001000000000000006F +:100090000000000000000000020202020202020250 +:1000A0000202020202020202000000000000000040 +:1000B0000000000000000000010101010101010138 +:1000C0000101010101010101010101010101010120 +:1000D0000101010101010101000000000000000018 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000202020202020202CF +:1001200002020202000002020101010100000001BE +:1001300001010100010000000101010101010101B3 +:10014000010101010101010101010101010101019F +:10015000010101010101010101010101010101018F +:10016000010101010101010101010101010101017F +:10017000010101010101010101010101010101016F +:10018000010101010101010101010101010101015F +:100190000101010101010101020202020202020247 +:1001A000020202020202020200000000000000003F +:1001B0000000000000000000010101010101010137 +:1001C000010101010101010101010101010101011F +:1001D0000101010101010101000000000000000017 +:1001E0000000000000000000010101010101010107 +:1001F00001010101010101010000000000000000F7 +:1002000000000000000000000000000000000000EE +:1002100000000000000000000202020202020202CE +:1002200002020202020202020101010101010101B6 +:1002300001010101010001000101010101010101B0 +:10024000010101010101010101010101010101019E +:10025000010101010101010101010101010101018E +:10026000010101010101010101010101010101017E +:10027000010101010101010101010101010101016E +:10028000010101010101010101010101010101015E +:100290000101010101010101020202020202020246 +:1002A0000202020202020202010101010101010136 +:1002B000010101010101010101010101010101012E +:1002C000010101010101010101010101010101011E +:1002D0000101010101010101000000000000000016 +:1002E0000000000000000000010101010101010106 +:1002F00001010101010101010101010101010101EE +:1003000001010101010101010000000000000000E5 +:1003100000000000000000000202020202020202CD +:1003200002020202020202020101010101010101B5 +:1003300001010101010001010101010101010101AE +:10034000010101010101010101010101010101019D +:10035000010101010101010101010101010101018D +:10036000010101010101010101010101010101017D +:10037000010101010101010101010101010101016D +:10038000010101010101010101010101010101015D +:10039000010101010101010101010101010101014D +:1003A000010101010101010101010101010101013D +:1003B000010101010101010101010101010101012D +:1003C000010101010101010101010101010101011D +:1003D000010101010101010101010101010101010D +:1003E00001010101010101010101010101010101FD +:1003F00001010101010101010101010101010101ED +:1004000001010101010101010101010101010101DC +:1004100001010101010101010202020202020202C4 +:1004200002020202020202020101010101010101B4 +:1004300001010101010101010101010101010101AC +:10044000010101010101010101010101010101019C +:10045000010101010101010101010101010101018C +:10046000010101010101010101010101010101017C +:10047000010101010101010101010101010101016C +:10048000010101010101010101010101010101015C +:10049000010101010101010101010101010101014C +:1004A000010101010101010101010101010101013C +:1004B000010101010101010101010101010101012C +:1004C000010101010101010101010101010101011C +:1004D000010101010101010101010101010101010C +:1004E00001010101010101010101010101010101FC +:1004F00001010101010101010101010101010101EC +:1005000001010101010101010101010101010101DB +:1005100001010101010101010202020202020202C3 +:1005200002020202020202020101010101010101B3 +:1005300001010101010101010000000000000000B3 +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000002020202020202027B +:10057000020202020202020202020202020202025B +:10058000020202020202020202020202020202024B +:10059000020202020202020200000000000000004B +:1005A000000000000000000002020202020202023B +:1005B000020202020202020202020202020202021B +:1005C000020202020202020202020202020202020B +:1005D00002020202020202020202020202020202FB +:1005E00002020202020202020202020202020202EB +:1005F00002020202020202020202020202020202DB +:1006000002020202020202020202020202020202CA +:1006100002020202020202020000000000000000CA +:1006200000000000000000000101010101010101C2 +:1006300001010101010101010000000000000000B2 +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000002020202020202022A +:1006C000020202020202020202020202020202020A +:1006D000020202020202020200000000000000000A +:1006E00000000000000000000202020202020202FA +:1006F00002020202020202020202020202020202DA +:1007000002020202020202020202020202020202C9 +:1007100002020202020202020000000000000000C9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000002C000000000000009C +:1008300000000001000000000000000000000000B7 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000010000000001D5 +:1009200000000000000000000000000000000000C7 +:1009300000000001000000000000000000000000B6 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000101000000000000E4 +:100A100000010000000000000001010000000001D2 +:100A200000000000000001000000000000000000C5 +:100A300000000001000000000000000000000000B5 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000100F5 +:100B000000000000000000000101000000000000E3 +:100B100000010000000000000001010000000001D1 +:100B200000000000000001000000000000000000C4 +:100B300000000001010000000000000000000000B3 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000100F4 +:100C000000010000000000000101000000000000E1 +:100C100000010000000000000001010000000001D0 +:100C200000000000000001000000000000000000C3 +:100C300001000001010000000000000000000000B1 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000010001010000000000000011 +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000000000000000010100F2 +:100D000000010000000000000101010000000000DF +:100D100001010000000000000001010001000001CD +:100D200000000000000001000000000000000000C2 +:100D300001010001010000000000000000000000AF +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000000000000000000000000000000000073 +:100D80000000000000000000000000000000000063 +:100D90000100000000000000000000000000000052 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000000000000000000010000000001000021 +:100DD000000000000001000101000000010000000F +:100DE0000000000000000000000000000000000003 +:100DF00000000000000000000000000000010100F1 +:100E000000010000000000000101010000000000DE +:100E100001010000000000000001010001010001CB +:100E200000000000000001000000000000000000C1 +:100E300001010001010000000000000000000000AE +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000001000081 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000100000000000000000000000000000051 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000000000000000000010000000001000020 +:100ED000000000000001000101000000010000000E +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000010100F0 +:100F000000010001000000000101010001000001DA +:100F100001010000000000000001010001010001CA +:100F200000000000000001000000000100000000BF +:100F300002010001010100010000000000000000AA +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F6000000000000000000000000001000100017E +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000100000000000000000000000000000050 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC000000000000000000001000000000100001F +:100FD000000000000001000101000000010000010C +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000010100EF +:1010000000010001000100000101010001000001D8 +:1010100001010000000000000101010001010101C7 +:1010200000000100000001000000000100000000BD +:1010300002010002010100010000000000000000A8 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:10106000000000000000000000000001000100017D +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:10109000010000000000000000000000000000004F +:1010A000000000000000000000000001000000013E +:1010B0000000000000000000000000000000000030 +:1010C000000000000000010001000000000100001D +:1010D000000000000001000101000000010000010B +:1010E0000000000000000000000000000000000000 +:1010F00000000000010000000000000000010100ED +:1011000000010001000101000101010001000001D6 +:1011100001010000000000000101010001010101C6 +:1011200000000100000001000000000100000000BC +:1011300002010002010100010100000000000000A6 +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:101160000000000000000100000001010101000179 +:10117000000000000000000000000000000000006F +:10118000010000000000000000000000000000005E +:10119000010000000000000000000000000000004E +:1011A000000000000000000000000001000101013B +:1011B000000000000000000000000000000000002F +:1011C000000000000000010001000000000100001C +:1011D000000000000001000101000000010000010A +:1011E00000000000000000000000000000000000FF +:1011F00000000000010000000000000000010101EB +:1012000000010001010101000101010001010101D2 +:1012100001010000000100010101010001010101C3 +:1012200000000100000001000000000100000000BB +:1012300002020002010100010100000000000000A4 +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:101260000000000001010100000101010101010174 +:10127000000000000000000000000000000000006E +:10128000010000000000000000000000000000005D +:10129000010000000000000000000000000000004D +:1012A0000000000000000100000001010101010137 +:1012B000000000000000000000000000000100002D +:1012C000000000000000010001000000000100001B +:1012D0000000000000010001010000000100000109 +:1012E00000000000000000000000000000000000FE +:1012F00000000000010000000000000000010101EA +:1013000001010001010101000101010001010101D0 +:1013100001010101000101010101010001010101BF +:1013200000000100000001000000000100000000BA +:1013300002020002010100010100000000000000A3 +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:101360000000000001010100000101010101010173 +:10137000010000000000000000000000000000006C +:10138000010000000000000000000000000000005C +:10139000010000000000000000000000000000004C +:1013A0000000000001010100010101010101010132 +:1013B000000000000000000000000001000100012A +:1013C000000000000000010001000000000100001A +:1013D0000000000000010001010001000100000107 +:1013E00000000000000000000000000000000000FD +:1013F00000000000010000000000000000010101E9 +:1014000001010001010101010101010001010101CE +:1014100001010101010101010101010001010101BD +:1014200000000100000001000000000100000000B9 +:10143000020200020201000202000000000000009F +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000100008B +:101460000000000001010101010101010101010170 +:10147000010000000000000000000000000000006B +:10148000010000000000000000000000000000005B +:10149000010000000000000000000000000000004B +:1014A0000000000001010100010101010101010131 +:1014B0000000000000000000000000010001010128 +:1014C0000000000000000100010000000001000019 +:1014D0000000000000010001010001000100000106 +:1014E00000000000000000000000000000000000FC +:1014F00000000000010000000000000000010101E8 +:1015000001010001010101010101010001010101CD +:1015100001010101010101010101010001010101BC +:1015200000000100000001000000000100000000B8 +:10153000020200020201000202000000000000009E +:10154000000000000000000000000000000000009B +:101550000000000000000000000000010001000188 +:10156000000001010101010101010101010101016D +:101570000100000000000000000000010000000069 +:10158000010000000000000000000000000000005A +:10159000010000000000000000000000000000004A +:1015A000000000000101010101010101010101012F +:1015B0000000000000000100000001010101010124 +:1015C0000000000000000100010000000001000018 +:1015D0000000000000010001010001000100000105 +:1015E00000000000000000000000000000000000FB +:1015F00000000000010001000000000100010101E5 +:1016000001010001010101010101010001010101CC +:1016100001010101010101010101010001010101BB +:1016200000000100000000000000000100000000B8 +:10163000020200020202000202000100000000019A +:10164000000000000000000000000000000000009A +:101650000000000000000000000000010001000187 +:10166000000101010101010101010101010101016B +:101670000100000000000000000000010000000068 +:101680000100000000000000000000000000000059 +:101690000200000000000000000000000000000048 +:1016A000000001010101010101010101010101012C +:1016B0000000000001010100000001010101010121 +:1016C0000000000000000100010000000001000116 +:1016D0000000000000010001010001000100000104 +:1016E00000000000000000000000000100000000F9 +:1016F00000000000010001000000000100010101E4 +:1017000001010001010101010101010001010101CB +:1017100001010101010101010101010001010101BA +:1017200000010100000000000000000100000000B6 +:101730000202000202020002020001000000000199 +:101740000000000000000000000000000000000099 +:101750000000000000000100000001010101000183 +:10176000000101010101010101010101010101016A +:101770000100000000000000000000010000000067 +:101780000100000000000000000000010000000057 +:101790000200000000000000000000000000000047 +:1017A000000101010101010101010101010101012A +:1017B0000000000001010100000001010101010120 +:1017C0000000000000000101020000000001000113 +:1017D00000000000000201020200010001000001FF +:1017E00000000000000000000000000100010000F7 +:1017F00000000000010001000000000101010101E2 +:1018000001010001010101010101010001010101CA +:1018100002020101010101010101010001010101B7 +:1018200000010100000100000000000100000001B3 +:101830000202010202020002020001000000000197 +:101840000000000000000000000000010000000196 +:10185000000000000101010000000101010101017F +:101860000001010101010101010101010101010169 +:101870000100000000000000000000010000000066 +:101880000100000000000000000000010001000055 +:101890000200000000000000000000000000000046 +:1018A0000001010101010101010101010101010129 +:1018B000000000000101010101010101010101011C +:1018C0000000000000000101020000000002000111 +:1018D00000000000000201020200010002000001FD +:1018E00000000000000000000000000100010001F5 +:1018F00000000000010001010100000101010101DF +:1019000001010001010101010101010001010101C9 +:1019100002020101010101010102020001010101B4 +:1019200000010100000100000100000100000001B1 +:101930000202010202020002020001000000000196 +:101940000000000000000000000000010001000194 +:10195000000000000101010000000101010101017E +:101960000001010101010101010101010101010168 +:101970000200000000000000000000010000000163 +:101980000200000000000000000000010001000152 +:101990000200000000000000000000010000000044 +:1019A0000001010101010101010101010101010128 +:1019B0000000010101010101010101010101010119 +:1019C000000000000000020102000000000200010F +:1019D00000000000000201020200010002000001FC +:1019E00000000000000000000000000100010101F3 +:1019F00000000100010001010100000101010201DC +:101A000001020001010101010202010001010101C5 +:101A100002020101010101010102020001010102B2 +:101A200000010000000100000100000100000001B1 +:101A30000202020202020002020002000000000094 +:101A40000000000000000100000000010001000192 +:101A5000000000000101010000010101010101017C +:101A60000001010101010101010101010101010167 +:101A70000200000000000000000000010000000162 +:101A80000200000000000000000000010001000151 +:101A90000200000000000000000000010001000042 +:101AA0000001010101010101010101010101010127 +:101AB0000001010101010101010101010101010117 +:101AC000000000000000020102000100000200010D +:101AD00000000000000201020200010002010002F9 +:101AE00000000000000000000000000100010101F2 +:101AF00000000100010001010100000101020201DA +:101B000001020101010101010202010101010101C2 +:101B100002020101010101010102020002010102B0 +:101B200000010000000100000100000100000001B0 +:101B30000202020202020002020002000000000093 +:101B40000000000001000100000000010001000190 +:101B5000000000000101010000010101010101017B +:101B60000101010101010101010101010101010165 +:101B70000200000000000000000000010000000161 +:101B80000200000000000000000000010001000150 +:101B90000200000000000000000000010001000140 +:101BA0000001010101010101010101010101010126 +:101BB0000001010101010101010101010101010116 +:101BC000000000000000020102000100000200010C +:101BD00000000000000201020200020002010002F7 +:101BE00000000000010000000000000100010101F0 +:101BF00000000100020001010100000101020201D8 +:101C000002020102010101010202020101010101BE +:101C100002020101010101010202020002020102AD +:101C200000010000000100000100000100000001AF +:101C30000202020202020002020002000000000092 +:101C4000020000000100010000000001010100018C +:101C50000000000001010100010101010101010179 +:101C60000101010101010101010101010101010164 +:101C7000020000000000000000000001000001015F +:101C8000020000000000000000000001000100014F +:101C9000020000000000000000000001000100013F +:101CA0000101010101010101010101010101010124 +:101CB0000001010101010101010101010101010115 +:101CC0000200000000000202020001000102000107 +:101CD00000000000010201020201020002010102F3 +:101CE00000000000010001000000000101010101ED +:101CF00000000100020001010100000101020201D7 +:101D000002020102010201010202020102010101BB +:101D100002020202010201020202020002020202A7 +:101D200000010000000100010100000000000001AE +:101D30000202020202020002020002000000000091 +:101D4000020000000100010000000001010101018A +:101D50000000010101010100010101010101010176 +:101D60000101010101010101010101010102010162 +:101D7000020000000000010000000101010001015B +:101D8000020000000000000000000001000100014E +:101D9000020000000000010000000001000100013D +:101DA0000101010101010101010101010101010123 +:101DB0000001010101010101010101010101010114 +:101DC0000200000000000202020001000102000205 +:101DD00002000101010202020201020102010102EC +:101DE00000000000010001000000000101010101EC +:101DF00001000101020001010100000101020202D3 +:101E000002020102020202010202020102010102B7 +:101E100002020202020202020202020002020202A4 +:101E200000010001000100010100000000000001AC +:101E30000202020202020002020002000000000090 +:101E40000200000001000100000000010101010189 +:101E50000001010101010100010101010101010174 +:101E60000101010102020201010202020202010259 +:101E70000200000000010101010101010101010155 +:101E8000020000000100000000000001000100014C +:101E9000020000000100010000000001000100013B +:101EA0000101010101010101010101010101010122 +:101EB0000001010101010101010101010102010112 +:101EC0000200000000000202020002000102000203 +:101ED00002010101010202020201020102010102EA +:101EE00000000100010001000000010101010101E9 +:101EF00001010101020002010101000101020202CF +:101F000002020102020202020202020102020202B3 +:101F100002020202020202020202020002020202A3 +:101F200000010001000100010100000000000101AA +:101F3000020202020202000202000200000000008F +:101F40000200000001000100000000010101010188 +:101F50000101010101010100010101010102010171 +:101F60000102020202020202020202020202020252 +:101F70000200010000010101010101020101010152 +:101F80000200000001000000000001010101000149 +:101F90000200000001000100000000010101000139 +:101FA0000101010101010101010101010101010121 +:101FB0000001010102020201010102020202020209 +:101FC00002020000000102020201020002020002FD +:101FD00002020202020202020202020102020102E3 +:101FE00000000100010001000000010201020101E6 +:101FF00002010201020002020201000202020202C8 +:1020000002020102020202020202020102020202B2 +:1020100002020202020202020202020002020202A2 +:1020200000000001000100010100000000000101AA +:102030000102020202020002010002000000000090 +:102040000200000002000200000000020102010282 +:102050000101010102020200010102020202010269 +:102060000202020202020202020202020202020250 +:102070000201010000010101010101020101010150 +:102080000200000001010001010001010101010144 +:102090000200000001000100000000010101000138 +:1020A0000101010102020201020202020202020215 +:1020B0000002020202020202020202020202020202 +:1020C00002020202000202020202020002020002F6 +:1020D00002020202020202020202020102020202E1 +:1020E00002000100020001000000010201020202E0 +:1020F00002010201020002020201000202020202C7 +:1021000002020102020202020202020102020202B1 +:1021100002020202020202020202020002020202A1 +:1021200000000001000100010100000000000101A9 +:102130000101020102020001010002000000000092 +:10214000020000000200020100000002020201027F +:102150000201010102020200010202020202020265 +:10216000020202020202020202020202020202024F +:10217000020101000001010101010102010101024E +:102180000200010001010001010001020102010140 +:102190000200010001000100000000020102000134 +:1021A0000102020202020202020202020202020210 +:1021B0000102020202020202020202020202020200 +:1021C00002020202020202020202020002020102F2 +:1021D00002020202020202020202020202020202DF +:1021E00002010200020002000000010202020202DB +:1021F00002020202020002020201000202020202C4 +:1022000002020202020202020202020102020202AF +:1022100002020202020202020202020002020202A0 +:1022200000000001000100010100000000000101A8 +:10223000010102010202000101000201010000008F +:10224000020000000200020100000002020202027D +:102250000202020202020200020202020202020260 +:10226000020202020202020202020202020202024E +:102270000202020000020202020202020201020243 +:10228000020101000101000101000102010201023D +:102290000200010002000200000000020102000230 +:1022A000020202020202020202020202020202020E +:1022B00002020202020202020202020202020202FE +:1022C00002020202020202020202020002020202F0 +:1022D00002020202020202020202020202020202DE +:1022E00002020200020002000000020202020202D8 +:1022F00002020202020102020202000202020202C1 +:1023000002020202020202020202020102020202AE +:10231000020202020202020202020200020202029F +:1023200000000001000000010100000000000101A8 +:102330000101010101010001010001010100020090 +:102340000202000002000202000000020202020279 +:10235000020202020202020002020202020202025F +:10236000020202020202020202020202020202024D +:102370000202020100020202020202020202020240 +:10238000020101000201010101000102010201023A +:10239000020002000200020000000002020200022D +:1023A000020202020202020202020202020202020D +:1023B00002020202020202020202020202020202FD +:1023C00002020202020202020202020002020202EF +:1023D00002020202020202020202020202020202DD +:1023E00002020200020002000000020202020202D7 +:1023F00002020202020102020202010202020202BF +:1024000002020202020202020202020202020202AC +:10241000020202020202020202020200020202029E +:10242000000202010002020102010102000001019A +:10243000010101010101010101000101010002008E +:102440000202020202000202000001020202020273 +:10245000020202020202020002020202020202025E +:10246000020202020202020202020202020202024C +:10247000020202020002020202020202020202023E +:102480000202020002020102020002020202010232 +:102490000202020002010200000000020202000229 +:1024A000020202020202020202020202020202020C +:1024B00002020202020202020202020202020202FC +:1024C00002020202020202020202020202020202EC +:1024D00002020202020202020202020202020202DC +:1024E00002020202020002000000020202020202D4 +:1024F00002020202020202020202010202020202BD +:1025000002020202020202020202020202020202AB +:10251000020202020202020202020201020202029C +:102520000002020101020201020101020000010297 +:10253000010101010101010101000101020101008C +:10254000020202020202020202020202020202026B +:10255000020202020202020002020202020202025D +:10256000020202020202020202020202020202024B +:10257000020202020002020202020202020202023D +:102580000202020002020102020002020202020230 +:102590000202020202020200000001020202000224 +:1025A000020202020202020202020202020202020B +:1025B00002020202020202020202020202020202FB +:1025C000000000000000000000000000000000000B +:1025D00002020202020202020202020202020202DB +:1025E00002020202020202020202020202020202CB +:1025F00002020202020202020202020202020202BB +:1026000002020202020202020202020202020202AA +:10261000020202020202020202020201020202029B +:102620000002020201020202020101020000010294 +:10263000010101010101010101000101020101008B +:10264000020202020202020202020202020202026A +:10265000020202020202020002020202020202025C +:10266000020202020202020202020202020202024A +:10267000020202020202020202020202020202023A +:10268000020202000202020202000202020202022E +:10269000020202020202020202020202020200021C +:1026A000020202020202020202020202020202020A +:1026B00002020202020202020202020202020202FA +:1026C000000000000000000000000000000000000A +:1026D00001010101010101010101010101010101EA +:1026E00002020202020202020202020202020202CA +:1026F00002020202020202020202020202020202BA +:1027000002020202020202020202020202020202A9 +:10271000020202020202020202020201020202029A +:102720000002020201020202020101020000010293 +:10273000000001000101010000000102020101008E +:10274000000202020202020202020202020202026B +:10275000020202020202020002020202020202025B +:102760000202020202020202020202020202020249 +:102770000202020202020202020202020202020239 +:10278000020202020202020202000202020202022B +:10279000020202020202020202020202020200021B +:1027A0000202020202020202020202020202020209 +:1027B00002020202020202020202020202020202F9 +:1027C0000000000000000000000000000000000009 +:1027D00002020202020202020202020202020202D9 +:1027E00002020202020202020202020202020202C9 +:1027F00002020202020202020202020202020202B9 +:1028000002020202020202020202020202020202A8 +:102810000202020202020202020202020202020298 +:102820000102020201020202020101020000020290 +:102830000000000000000200000000020101010091 +:10284000000202020202020202020202020202026A +:102850000202020202020202020202020202020258 +:102860000202020202020202020202020202020248 +:102870000202020202020202020202020202020238 +:102880000202020202020202020202020202020228 +:102890000202020202020202020202020202020218 +:1028A0000202020202020202020202020202020208 +:1028B00002020202020202020202020202020202F8 +:1028C0000000000000000000000000000000000008 +:1028D00000000000000000000000000000000000F8 +:1028E00002020202020202020202020202020202C8 +:1028F00002020202020202020202020202020202B8 +:1029000002020202020202020202020202020202A7 +:102910000202020202020202020202020202020297 +:10292000020202020102020202000102010002028E +:102930000000000000000200000100010102000090 +:102940000100000000000000000000000000000086 +:102950000202020202020202020202020202020257 +:102960000202020202020202020202020202020247 +:102970000202020202020202020202020202020237 +:102980000202020202020202020202020202020227 +:102990000002020202020202020202020202020219 +:1029A0000202020202020202020202020202020207 +:1029B00002020202020202020202020202020202F7 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000002020202020202020202020202020202A6 +:102A100001010101010101010101010101010101A6 +:102A20000202020202020202020202020101020288 +:102A30000000000000000100000100010101000091 +:102A40000100000000000000000000000000000085 +:102A50000202020202020202020202020202020256 +:102A60000202020202020202020202020202020246 +:102A70000102020202020202020202020202020237 +:102A80000202020202020202020202020202020226 +:102A90000000000000000000000000000000000036 +:102AA0000202020202020202020202020202020206 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000000E6 +:102AF00000000000000000000000000000000000D6 +:102B000002020202020202020202020202020202A5 +:102B10000202020202020202020202020202020295 +:102B20000202020202020202020202020001020288 +:102B30000000000000000100000000000001000093 +:102B40000101010101010101010101010101010175 +:102B50000101010101010101010101010101010165 +:102B60000202020202020202020202020202020245 +:102B70000101010101010101010101010101010145 +:102B80000102020202020202020202020202020226 +:102B90000000000000000000000000000000000035 +:102BA0000202020202020202020202020202020205 +:102BB0000000000000000000000000000000000015 +:102BC00001010101010101010101010101010101F5 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000002020202020202020202020202020202A4 +:102C100000000000000000000000000000000000B4 +:102C20000202020202020202020202020001020287 +:102C3000010100010000000101000000000000008F +:102C40000101010101010101010101010101010174 +:102C50000202020202020202020202020202020254 +:102C60000202020202020202020202020202020244 +:102C70000101010101010101010101010101010144 +:102C80000101010101010101010101010101010134 +:102C90000100000000000000000000000000000033 +:102CA0000202020202020202020202020202020204 +:102CB0000000000000000000000000000000000014 +:102CC00001010101010101010101010101010101F4 +:102CD00001010101010101010101010101010101E4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000002020202020202020202020202020202A3 +:102D100000000000000000000000000000000000B3 +:102D20000202020202020202020202020000020287 +:102D3000010101010101000101000100000000008A +:102D40000101010101010101010101010101010173 +:102D50000101010101010101010101010101010163 +:102D60000101010101010101010101010101010153 +:102D70000101010101010101010101010101010143 +:102D80000101010101010101010101010101010133 +:102D90000101010101010101010101010101010123 +:102DA0000202020202020202020202020202020203 +:102DB0000000000000000000000000000000000013 +:102DC00001010101010101010101010101010101F3 +:102DD00001010101010101010101010101010101E3 +:102DE00000000000000000000000000000000000E3 +:102DF00001010101010101010101010101010101C3 +:102E000001010101010101010101010101010101B2 +:102E100000000000000000000000000000000000B2 +:102E20000202020202020202020202020202020282 +:102E30000101010101010001010001000000010088 +:102E40000101010101010101010101010101010172 +:102E50000101010101010101010101010101010162 +:102E60000101010101010101010101010101010152 +:102E70000101010101010101010101010101010142 +:102E80000101010101010101010101010101010132 +:102E90000101010101010101010101010101010122 +:102EA0000202020202020202020202020202020202 +:102EB0000101010101010101010101010101010102 +:102EC00001010101010101010101010101010101F2 +:102ED00001010101010101010101010101010101E2 +:102EE00000000000000000000000000000000000E2 +:102EF00001010101010101010101010101010101C2 +:102F000001010101010101010101010101010101B1 +:102F100000000000000000000000000000000000B1 +:102F20000202020202020202020202020202020281 +:102F30000101010101010001010001000000010186 +:102F40000101010101010101010101010101010171 +:102F50000101010101010101010101010101010161 +:102F60000101010101010101010101010101010151 +:102F70000101010101010101010101010101010141 +:102F80000101010101010101010101010101010131 +:102F90000101010101010101010101010101010121 +:102FA0000101010101010101010101010101010111 +:102FB0000101010101010101010101010101010101 +:102FC00001010101010101010101010101010101F1 +:102FD00001010101010101010101010101010101E1 +:102FE00001010101010101010101010101010101D1 +:102FF00001010101010101010101010101010101C1 +:1030000001010101010101010101010101010101B0 +:1030100001010101010101010101010101010101A0 +:103020000202020202020202020202020202020280 +:103030000101010101010001010101010100010182 +:103040000101010101010101010101010101010170 +:103050000101010101010101010101010101010160 +:103060000101010101010101010101010101010150 +:103070000101010101010101010101010101010140 +:103080000101010101010101010101010101010130 +:103090000101010101010101010101010101010120 +:1030A0000101010101010101010101010101010110 +:1030B0000101010101010101010101010101010100 +:1030C00001010101010101010101010101010101F0 +:1030D00001010101010101010101010101010101E0 +:1030E00001010101010101010101010101010101D0 +:1030F00001010101010101010101010101010101C0 +:1031000001010101010101010101010101010101AF +:10311000010101010101010101010101010101019F +:10312000020202020202020202020202020202027F +:10313000010101010101010101010101010101017F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000020202020202020202020202020202022F +:10318000020202020202020202020202020202021F +:10319000020202020202020202020202020202020F +:1031A000000000000000000000000000000000001F +:1031B00002020202020202020202020202020202EF +:1031C00002020202020202020202020202020202DF +:1031D00002020202020202020202020202020202CF +:1031E00002020202020202020202020202020202BF +:1031F00002020202020202020202020202020202AF +:10320000020202020202020202020202020202029E +:10321000020202020202020202020202020202028E +:10322000000000000000000000000000000000009E +:10323000010101010101010101010101010101017E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00002020202020202020202020202020202DE +:1032D00002020202020202020202020202020202CE +:1032E00000000000000000000000000000000000DE +:1032F00002020202020202020202020202020202AE +:10330000020202020202020202020202020202029D +:10331000020202020202020202020202020202028D +:10332000000000000000000000000000000000009D +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000000FD +:1033D00000000000000000000000000000000000ED +:1033E00000000000000000000000000000000000DD +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000000000000000000009C +:1034300068340B000000000070690B000000000001 +:1034400078980B000000000080C40B000000000012 +:1034500088F00B000000000090190C000000000034 +:10346000983F0C0000000000A05D0C000000000070 +:10347000A87B0C0000000000B0990C0000000000C8 +:10348000B8B70C0000000000C0D50C000000000020 +:10349000C8F30C0000000000D0110D000000000077 +:1034A000D82F0D00000000003500000000000000D3 +:1034B0000202020002000000000100000100000002 +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000000EC +:1034E00000000000000000000000000000000000DC +:1034F00000000000000000000000000000000000CC +:1035000000000000000101010100000100000001B5 +:1035100000000000000000000000000000000000AB +:10352000000000000000000000000000000000009B +:10353000000000000000000000000000000000008B +:10354000000000000000000000000000000000007B +:103550000000000000000001010000000000000168 +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A0000000000000010001000000000000000118 +:1035B00002020202020202020202000001000000F6 +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000000000000000000000EB +:1035E00000000000000000000000000000000000DB +:1035F00000000000000000000000000000000000CB +:1036000000000000010101010100000100000001B3 +:1036100000000000000000000000000000000000AA +:10362000000000000000000000000000000000009A +:10363000000000000000000000000000000000008A +:10364000000000000000000000000000000000007A +:103650000000000000000001010000000101000165 +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A0000000000001010001000000000000000116 +:1036B00002020202020202020202000002000000F4 +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000010101010100000100000001B2 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000000000000000000099 +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000001010000000101000164 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000001010001000000000000000115 +:1037B00002020202020202020202020002000000F1 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000010101010101000100000001B0 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000000000000000000098 +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000010000000001010100000101000161 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000001010001000000000000000114 +:1038B00002020202020202020202020002000000F0 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000010101010101010100000001AE +:1039100000000000000000000000000000000000A7 +:103920000000000000000000000000000000000097 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000010000000001010100000101000160 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000001010001000000000000000113 +:1039B00002020202020202020202020002000000EF +:1039C00000000000000000000000000000000000F7 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000001000100010101010101010100000001AB +:103A100000000000000000000000000000000000A6 +:103A20000000000000000000000000000000000096 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A5000000001000000000101010000010100015F +:103A60000000000000000000000000000000000056 +:103A70000000000000000000000000000000000046 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000001010001000100000000000111 +:103AB00002020202020202020202020002010000ED +:103AC00000000000000000000000000000000000F6 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000001000100020101010101010100000001A9 +:103B100000000000000000000000000000000000A5 +:103B20000000000000000000000000000000000095 +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B5000000001000001010101010100010100015B +:103B60000000000000000000000000000000000055 +:103B70000000000000000000000000000000000045 +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA000000000000101000101010101000000010D +:103BB00002020202020202020202020202010100E9 +:103BC00000000000000000000000000000000000F5 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000002010100020202010101010100000001A4 +:103C100000000000000000000000000000000000A4 +:103C20000000000000000000000000000000000094 +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000101010000010101010101000101000158 +:103C60000000000000000000000000000000000054 +:103C70000000000000000000000000000000000044 +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA000000000000101000101010101010000010B +:103CB00002020202020202020202020202020100E7 +:103CC00000000000000000000000000000000000F4 +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000002010200020202010201010100000001A1 +:103D100000000000000000000000000000000000A3 +:103D20000000000000000000000000000000000093 +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000101010000010101010101010101000156 +:103D60000000000000000000000000000000000053 +:103D70000000000000000000000000000000000043 +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA000000000000101000101010101010000010A +:103DB00002020202020202020202020202020200E5 +:103DC00000000000000000000000000000000000F3 +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E0000020202000202020202010101000000019E +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000101010000010101010101010101000155 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000000000000000000042 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000001010001010101010101000108 +:103EB00002020202020202020202020202020200E4 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F0000020202010202020202010101000000019C +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000101010100010101010101010101000153 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000001010001010101010101000107 +:103FB00002020202020202020202020202020200E3 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:104000000202020102020202020201020000000199 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000101010100010101010101010101000152 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000001010001010101010101000106 +:1040B00002020202020202020202020202020200E2 +:1040C00000000000000000000000000000000000F0 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:104100000202020102020202020202020000000197 +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000020102010001010101010101010100014F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A0000000000001010001010101010101000105 +:1041B00002020202020202020202020202020200E1 +:1041C00000000000000000000000000000000000EF +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:104200000202020202020202020202020000000195 +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000020202010101010101010101010100014C +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A0000000000001010001010101010101000104 +:1042B00002020202020202020202020202020200E0 +:1042C00000000000000000000000000000000000EE +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:104300000202020202020202020202020000000194 +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000020202010101010102010101010100014A +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A0000000000002010001010101010101010101 +:1043B00002020202020202020202020202020200DF +:1043C00000000000000000000000000000000000ED +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:104400000202020202020202020202020100000192 +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:104450000202020101010102020101010101000148 +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A00000010000020100010101010101010101FF +:1044B00002020202020202020202020202020200DE +:1044C00000000000000000000000000000000000EC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:104500000202020202020202020202020100000191 +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:104550000202020101010102020101010101010146 +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A00000010000020200010101010101010101FD +:1045B00002020202020202020202020201020200DE +:1045C00000000000000000000000000000000000EB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:104600000202020202020202020202020100000190 +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:104650000202020101020102020101010101010144 +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A00001010000020200020101010101010101FA +:1046B00002020202020202020201010201020200DF +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:10470000020202020202020202020202010000018F +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:10475000020202020102020202020101020101013F +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A00001010001020200020101010101010101F8 +:1047B00002020202020202010101010101010100E3 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:10480000020202020202020202020202010100028C +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:10485000020202020102020202020101020201013D +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A00002020101020200020101010101010101F4 +:1048B00002020202020201010101010101010100E3 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:10490000020202020202020202020202010101028A +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:10495000020202020202020202020201020201013A +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A00002020101020201020201010101010101F1 +:1049B00002020202020101010101010101010100E3 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A00000202020202020202020202020201010288 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000202020202020202020202010202010139 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA00002020101020201020202010101010101EF +:104AB00002020202010101010101010101010100E3 +:104AC00000000000000000000000000000000000E6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B00000202020202020202020202020201010287 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000202020202020202020202020202010137 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA00002020201020201020202020101010101EC +:104BB00002020201010101010101010101010101E2 +:104BC00000000000000000000000000000000000E5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C00000202020202020202020202020201010286 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000202020202020202020202020202010235 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA00002020202020201020202020201010101E9 +:104CB00002020101010101010101010101010101E2 +:104CC00000000000000000000000000000000000E4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D00000202020202020202020202020201010285 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000202020202020202020202020202010234 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA00002020202020201020202020202010102E6 +:104DB00002010101010101010101010101010101E2 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E00000202020202020202020202020202010283 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E30000000000000000000000000000000000072 +:104E40000000000000000000000000000000000062 +:104E50000202020202020202020202020202010233 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000000000000000000000000000000000022 +:104E90000000000000000000000000000000000012 +:104EA00002020202020201020202020202010102E5 +:104EB00001010101010101010101010101010101E2 +:104EC00000000000000000000000000000000000E2 +:104ED00000000000000000000000000000000000D2 +:104EE00000000000000000000000000000000000C2 +:104EF00000000000000000000000000000000000B2 +:104F00000202020202020202020202020202020281 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000000000000000000000000000000000071 +:104F40000000000000000000000000000000000061 +:104F50000202020202020202020202020202010232 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000000000000000000000000000000000021 +:104F90000000000000000000000000000000000011 +:104FA00002020202020201020202020202020102E3 +:104FB00001010101010101010101010101010101E1 +:104FC00000000000000000000000000000000000E1 +:104FD00000000000000000000000000000000000D1 +:104FE00000000000000000000000000000000000C1 +:104FF00000000000000000000000000000000000B1 +:105000000202020202020202020202020202020280 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000000000000000000000000000000000070 +:105040000000000000000000000000000000000060 +:105050000202020202020202020202020202010231 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000000000000000000000000000000000020 +:105090000000000000000000000000000000000010 +:1050A00002020202020202020202020202020102E1 +:1050B00001010101010101010101010101010101E0 +:1050C00000000000000000000000000000000000E0 +:1050D00000000000000000000000000000000000D0 +:1050E00000000000000000000000000000000000C0 +:1050F00000000000000000000000000000000000B0 +:10510000020202020202020202020202020202027F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000000000000000000000000000000000006F +:10514000000000000000000000000000000000005F +:105150000202020202020202020202020202010230 +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:10518000000000000000000000000000000000001F +:10519000000000000000000000000000000000000F +:1051A00002020202020202020202020202020102E0 +:1051B00001010101010101010101010101010101DF +:1051C00000000000000000000000000000000000DF +:1051D00000000000000000000000000000000000CF +:1051E00000000000000000000000000000000000BF +:1051F00000000000000000000000000000000000AF +:10520000020202020202020202020202020202027E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000000000000000000000000000000000006E +:10524000000000000000000000000000000000005E +:10525000020202020202020202020202020202022E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:10528000000000000000000000000000000000001E +:10529000000000000000000000000000000000000E +:1052A00002020202020202020202020202020202DE +:1052B00001010101010101010101010101010101DE +:1052C00000000000000000000000000000000000DE +:1052D00000000000000000000000000000000000CE +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000020202020202020202020202020202027D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000000000000000000000000000000000006D +:10534000000000000000000000000000000000005D +:10535000020202020202020202020202020202022D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:10538000000000000000000000000000000000001D +:10539000000000000000000000000000000000000D +:1053A00002020202020202020202020202020202DD +:1053B00001010101010101010101010101010101DD +:1053C00000000000000000000000000000000000DD +:1053D00000000000000000000000000000000000CD +:1053E00000000000000000000000000000000000BD +:1053F00000000000000000000000000000000000AD +:10540000020202020202020202020202020202027C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:10543000000000000000000000000000000000006C +:10544000000000000000000000000000000000005C +:10545000020202020202020202020202020202022C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:10548000000000000000000000000000000000001C +:10549000000000000000000000000000000000000C +:1054A00002020202020202020202020202020202DC +:1054B00001010101010101010101010101010101DC +:1054C00000000000000000000000000000000000DC +:1054D00000000000000000000000000000000000CC +:1054E00000000000000000000000000000000000BC +:1054F00000000000000000000000000000000000AC +:105500000202020202020102010101010202020280 +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:10553000000000000000000000000000000000006B +:10554000000000000000000000000000000000005B +:10555000020202020202020202020202020202022B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:10558000000000000000000000000000000000001B +:10559000000000000000000000000000000000000B +:1055A00002020202020202020202020202020202DB +:1055B00001010101010101010101010101010101DB +:1055C00000000000000000000000000000000000DB +:1055D00000000000000000000000000000000000CB +:1055E00000000000000000000000000000000000BB +:1055F00000000000000000000000000000000000AB +:105600000202020201010101010101010202020282 +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000000000000000000000000000000000006A +:10564000000000000000000000000000000000005A +:10565000020202020202020202020202020202022A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000000000000000000000000000000000001A +:10569000000000000000000000000000000000000A +:1056A00002020202020202020202020202020202DA +:1056B00001010101010101010101010101010101DA +:1056C00000000000000000000000000000000000DA +:1056D00000000000000000000000000000000000CA +:1056E00000000000000000000000000000000000BA +:1056F00000000000000000000000000000000000AA +:105700000202020201010101010101010102020282 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000000000000000000000000000000000069 +:105740000000000000000000000000000000000059 +:105750000202020202020202020202020202020229 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000000000000000000000019 +:105790000000000000000000000000000000000009 +:1057A00002020202020202020202020202020202D9 +:1057B00001010101010101010101010101010101D9 +:1057C00000000000000000000000000000000000D9 +:1057D00000000000000000000000000000000000C9 +:1057E00000000000000000000000000000000000B9 +:1057F00000000000000000000000000000000000A9 +:105800000202010201010101010101010101010284 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000000000000000000000000000000000068 +:105840000000000000000000000000000000000058 +:105850000202020202020202020202020202020228 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00002020202020202020202020202020202D8 +:1058B00001010101010101010101010101010101D8 +:1058C00000000000000000000000000000000000D8 +:1058D00000000000000000000000000000000000C8 +:1058E00000000000000000000000000000000000B8 +:1058F00000000000000000000000000000000000A8 +:105900000101010101010101010101010101010187 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000000000000000000000000000000000067 +:105940000000000000000000000000000000000057 +:105950000202020202020202020202020202020227 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000000000000000000000000000000000017 +:105990000000000000000000000000000000000007 +:1059A00002020202020202020202020202020202D7 +:1059B00001010101010101010101010101010101D7 +:1059C00000000000000000000000000000000000D7 +:1059D00000000000000000000000000000000000C7 +:1059E00000000000000000000000000000000000B7 +:1059F00000000000000000000000000000000000A7 +:105A00000101010101010101010101010101010186 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000000000000000000000000000000000066 +:105A40000000000000000000000000000000000056 +:105A50000202020202020202020202020202020226 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000000000000000000000000000000000016 +:105A90000000000000000000000000000000000006 +:105AA00002020202020202020202020202020202D6 +:105AB00001010101010101010101010101010101D6 +:105AC00000000000000000000000000000000000D6 +:105AD00000000000000000000000000000000000C6 +:105AE00000000000000000000000000000000000B6 +:105AF00000000000000000000000000000000000A6 +:105B00000101010101010101010101010101010185 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000000000000000000000000000000000065 +:105B40000000000000000000000000000000000055 +:105B50000202020202020202020202020202020225 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000000000000000000000000000000000015 +:105B90000000000000000000000000000000000005 +:105BA00002020202020202020202020202020202D5 +:105BB00001010101010101010101010101010101D5 +:105BC00000000000000000000000000000000000D5 +:105BD00000000000000000000000000000000000C5 +:105BE00000000000000000000000000000000000B5 +:105BF00000000000000000000000000000000000A5 +:105C00000101010101010101010101010101010184 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000000000000000000000000000000000064 +:105C40000000000000000000000000000000000054 +:105C50000202020202020202020202020202020224 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C80000000000000000000000000000000000014 +:105C90000000000000000000000000000000000004 +:105CA00002020202020202020202020202020202D4 +:105CB00001010101010101010101010101010101D4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000000000000000000000000000000C4 +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000101010101010101010101010101010183 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000202020202020202020202020202020223 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00002020202020202020202020202020202D3 +:105DB00001010101010101010101010101010101D3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE00000000000000000000000000000000000B3 +:105DF00000000000000000000000000000000000A3 +:105E00000101010101010101010101010101010182 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000062 +:105E40000000000000000000000000000000000052 +:105E50000202020202020202020202020202020222 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00002020202020202020202020202020202D2 +:105EB00001010101010101010101010101010101D2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000000000000000000C2 +:105EE00000000000000000000000000000000000B2 +:105EF00000000000000000000000000000000000A2 +:105F00000101010101010101010101010101010181 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F30000000000000000000000000000000000061 +:105F40000000000000000000000000000000000051 +:105F50000202020202020202010202020101020224 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00002020202020202020202020202020202D1 +:105FB00001010101010101010101010101010101D1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000000000000000000C1 +:105FE00000000000000000000000000000000000B1 +:105FF00000000000000000000000000000000000A1 +:106000000101010101010101010101010101010180 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:106030000000000000000000000000000000000060 +:106040000000000000000000000000000000000050 +:106050000202020202020201010101010101020227 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00002020202020202020202020202020202D0 +:1060B00001010101010101010101010101010101D0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000000000000000000C0 +:1060E00000000000000000000000000000000000B0 +:1060F00000000000000000000000000000000000A0 +:10610000010101010101010101010101010101017F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000000000000000000005F +:10614000000000000000000000000000000000004F +:10615000010101020201010101010101010101012D +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000000000000000000F +:1061900000000000000000000000000000000000FF +:1061A00002020202020202020202020202020202CF +:1061B00001010101010101010101010101010101CF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000000000000000000BF +:1061E00000000000000000000000000000000000AF +:1061F000000000000000000000000000000000009F +:10620000010101010101010101010101010101017E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:10623000000000000000000000000000000000005E +:10624000000000000000000000000000000000004E +:10625000010101010101010101010101010101012E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000000000000000000E +:1062900000000000000000000000000000000000FE +:1062A00002020202020202020202020202020202CE +:1062B00001010101010101010101010101010101CE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000000000000000000BE +:1062E00000000000000000000000000000000000AE +:1062F000000000000000000000000000000000009E +:10630000010101010101010101010101010101017D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:10633000000000000000000000000000000000005D +:10634000000000000000000000000000000000004D +:10635000010101010101010101010101010101012D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:10638000000000000000000000000000000000000D +:1063900000000000000000000000000000000000FD +:1063A00002020202020202020202020202020202CD +:1063B00001010101010101010101010101010101CD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000000000000000000BD +:1063E00000000000000000000000000000000000AD +:1063F000000000000000000000000000000000009D +:10640000010101010101010101010101010101017C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:10643000000000000000000000000000000000005C +:10644000000000000000000000000000000000004C +:10645000010101010101010101010101010101012C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:10648000000000000000000000000000000000000C +:1064900000000000000000000000000000000000FC +:1064A00002020202020202020202020202020202CC +:1064B00001010101010101010101010101010101CC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000000000000000000BC +:1064E00000000000000000000000000000000000AC +:1064F000000000000000000000000000000000009C +:10650000010101010101010101010101010101017B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:10653000000000000000000000000000000000005B +:10654000000000000000000000000000000000004B +:10655000010101010101010101010101010101012B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:10658000000000000000000000000000000000000B +:1065900000000000000000000000000000000000FB +:1065A00002020202020202020202020202020202CB +:1065B00001010101010101010101010101010101CB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000000000000000000BB +:1065E00000000000000000000000000000000000AB +:1065F000000000000000000000000000000000009B +:10660000010101010101010101010101010101017A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:10663000000000000000000000000000000000005A +:10664000000000000000000000000000000000004A +:10665000010101010101010101010101010101012A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:10668000000000000000000000000000000000000A +:1066900000000000000000000000000000000000FA +:1066A00002020202010202010101010101010101D4 +:1066B00001010101010101010101010101010101CA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000000000000000000BA +:1066E00000000000000000000000000000000000AA +:1066F000000000000000000000000000000000009A +:106700000101010101010101010101010101010179 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000000000000000000059 +:106740000000000000000000000000000000000049 +:106750000101010101010101010101010101010129 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000000000000000000009 +:1067900000000000000000000000000000000000F9 +:1067A00000000000000200000000000000000000E7 +:1067B00001010101010101010101010101010101C9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000000000000000000B9 +:1067E00000000000000000000000000000000000A9 +:1067F0000000000000000000000000000000000099 +:106800000101010101010101010101010101010178 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:106830000000000000000000000000000000000058 +:106840000000000000000000000000000000000048 +:106850000101010101010101010101010101010128 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:106880000000000000000000000000000000000008 +:1068900000000000000000000000000000000000F8 +:1068A00000000000000100000000000000000000E7 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000000000000000000B8 +:1068E00000000000000000000000000000000000A8 +:1068F0000000000000000000000000000000000098 +:106900000000000000000000000000000000000087 +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:106930000000000000000000000000000000000057 +:106940000000000000000000000000000000000047 +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:106980000000000000000000000000000000000007 +:1069900000000000000000000000000000000000F7 +:1069A00000000000000000000000000000000000E7 +:1069B0002F0000000000000000020000020202029E +:1069C00002000200000000000000000000000000C3 +:1069D00000000000000000000000000000000000B7 +:1069E00000000000000000000000000000000000A7 +:1069F0000000000000000000000000000000000097 +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000000000000000000056 +:106A40000000000000000000000000000000000046 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A80000000000000000000000000000000000006 +:106A900000000000000000000000000000000000F6 +:106AA00000000000000000000000000001010101E2 +:106AB00000000000000000000002020202020202C8 +:106AC00002020200020000000000000000000000BE +:106AD00000000000000000000000000000000000B6 +:106AE00000000000000000000000000000000000A6 +:106AF0000000000000000000000000000000000096 +:106B00000000000000000000000001000000000084 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000000000000000000055 +:106B40000000000000000000000000000000000045 +:106B50000000000000000000000000000000000035 +:106B60000000000000000001000000000000000024 +:106B70000000000000000000000000000000000015 +:106B80000000000000000000000000000000000005 +:106B900000000000000000000000000000000000F5 +:106BA00000000000000000000000000001010101E1 +:106BB00000000000000000010202020202020202C4 +:106BC00002020200020000000000000000000000BD +:106BD00000000000000000000000000000000000B5 +:106BE00000000000000000000000000000000000A5 +:106BF0000000000000000000000000000000000095 +:106C00000000000000000000000001000101000081 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000000000000000000054 +:106C40000000000000000000000000000000000044 +:106C50000000000000000000000000000000000034 +:106C60000000000000000001000000000000000023 +:106C70000000000000000000000000000000000014 +:106C80000000000000000000000000000000000004 +:106C900000000000000000000000000000000000F4 +:106CA00000000000000000000000000001010101E0 +:106CB00001000000000000010202020202020202C2 +:106CC00002020200020000000000000000000000BC +:106CD00000000000000000000000000000000000B4 +:106CE00000000000000000000000000000000000A4 +:106CF0000000000000000000000000000000000094 +:106D00000000000000000000000001000101000080 +:106D10000000000000000001000000000000000072 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000000000000000000053 +:106D40000000000000000000000000000000000043 +:106D50000000000000000000000001000000000032 +:106D60000000000000000001000000000000000022 +:106D70000000000000000000000000000000000013 +:106D80000000000000000000000000000000000003 +:106D900000000000000000000000000000000000F3 +:106DA00000000000000000000000000001010101DF +:106DB00001000001000000010202020202020202C0 +:106DC00002020200020000000000000000000000BB +:106DD00000000000000000000000000000000000B3 +:106DE00000000000000000000000000000000000A3 +:106DF0000000000000000000000000000000000093 +:106E0000000000000000000001010100010101007C +:106E10000000000000000001000000000000000071 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000000000000000000052 +:106E40000000000000000000000000000000000042 +:106E50000000000000000000000001000000000031 +:106E60000100000000000001000000000000000020 +:106E70000000000000000000000000000000000012 +:106E80000000000000000000000000000000000002 +:106E900000000000000000000000000000000000F2 +:106EA00000000000000000000000000001010101DE +:106EB00001000001000000010202020202020202BF +:106EC00002020202020000000000000000000000B8 +:106ED00000000000000000000000000000000000B2 +:106EE00000000000000000000000000000000000A2 +:106EF0000000000000000000000000000000000092 +:106F0000000000000000000001010101010101007A +:106F10000000000000000001000000000000000070 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000000000000000000051 +:106F40000000000000000000000000000000000041 +:106F50000000000000000000000001000000000030 +:106F6000010000000000000100000000000000001F +:106F70000000000000000000000000000000000011 +:106F80000000000000000000000000000000000001 +:106F900000000000000000000000000000000000F1 +:106FA00000000000000000000000000001010101DD +:106FB00001010001000000010202020202020202BD +:106FC00002020202020000000000000000000000B7 +:106FD00000000000000000000000000000000000B1 +:106FE00000000000000000000000000000000000A1 +:106FF0000000000000000000000000000000000091 +:107000000000000000000000010101010101010079 +:10701000000000000000000100000000000000006F +:107020000000000000000000000000000000000060 +:107030000000000000000000000000000000000050 +:107040000000000000000000000000000000000040 +:10705000000000000000000000000100010000002E +:10706000010000000000000100000000000000001E +:107070000000000000000000000000000000000010 +:107080000000000000000000000000000000000000 +:1070900000000000000000000000000000000000F0 +:1070A00000000000000000000000000001010101DC +:1070B00001010001000000010202020202020202BC +:1070C00002020202020201000000000000000000B3 +:1070D00000000000000000000000000000000000B0 +:1070E00000000000000000000000000000000000A0 +:1070F0000000000000000000000000000000000090 +:107100000000000000000000020102010101010076 +:10711000000000000000000100000000000000006E +:10712000000000000000000000000000000000005F +:10713000000000000000000000000000000000004F +:10714000000000000000000000000000000000003F +:10715000000000000000000000000100010000002D +:10716000010100010000000100000000000000001B +:10717000000000000000000000000000000000000F +:1071800000000000000000000000000000000000FF +:1071900000000000000000000000000000000000EF +:1071A00000000000000000000000000001010101DB +:1071B00001010001000001010202020202020202BA +:1071C00002020202020201000000000000000000B2 +:1071D00000000000000000000000000000000000AF +:1071E000000000000000000000000000000000009F +:1071F000000000000000000000000000000000008F +:107200000000000000000000020202010202010171 +:10721000010000000000000100000000000000006C +:10722000000000000000000000000000000000005E +:10723000000000000000000000000000000000004E +:10724000000000000000000000000000000000003E +:10725000000000000000000000000100010001002B +:10726000010100010000000100000000000000001A +:10727000000000000000000000000000000000000E +:1072800000000000000000000000000000000000FE +:1072900000000000000000000000000000000000EE +:1072A00000000000000000000000000001010101DA +:1072B00001010001000001010202020202020202B9 +:1072C00002020202020202000000000000000000B0 +:1072D00000000000000000000000000000000000AE +:1072E000000000000000000000000000000000009E +:1072F000000000000000000000000000000000008E +:107300000000000000000000020202010202010170 +:10731000010000000100000100000000000000006A +:10732000000000000000000000000000000000005D +:10733000000000000000000000000000000000004D +:10734000000000000000000000000000000000003D +:10735000000000000000000000000100010001002A +:107360000101000100000001000000000000000019 +:10737000000000000000000000000000000000000D +:1073800000000000000000000000000000000000FD +:1073900000000000000000000000000000000000ED +:1073A00000000000000000000000000001010101D9 +:1073B00001010001000001010202020202020202B8 +:1073C00002020202020202000000000000000000AF +:1073D00000000000000000000000000000000000AD +:1073E000000000000000000000000000000000009D +:1073F000000000000000000000000000000000008D +:10740000000000000000000002020202020201016E +:107410000100010001000001000000000000000068 +:10742000000000000000000000000000000000005C +:10743000000000000000000000000000000000004C +:10744000000000000000000000000000000000003C +:107450000000000000000000010101000100010126 +:107460000101000100000001000000000000000018 +:10747000000000000000000000000000000000000C +:1074800000000000000000000000000000000000FC +:1074900000000000000000000000000000000000EC +:1074A00000000000000000000000000001010101D8 +:1074B00001010101000001010202020202020202B6 +:1074C00002020202020202000000000000000000AE +:1074D00000000000000000000000000000000000AC +:1074E000000000000000000000000000000000009C +:1074F000000000000000000000000000000000008C +:10750000000000000000000002020202020202016C +:107510000101010101010001000000000000000064 +:10752000000000000000000000000000000000005B +:10753000000000000000000000000000000000004B +:10754000000000000000000000000000000000003B +:107550000000000000000000010101000100010125 +:107560000101000100010001000000000000000016 +:10757000000000000000000000000000000000000B +:1075800000000000000000000000000000000000FB +:1075900000000000000000000000000000000000EB +:1075A00000000000000000000000000001010101D7 +:1075B00001010101010101010202020202020202B3 +:1075C00002020202020202000000000000000000AD +:1075D00000000000000000000000000000000000AB +:1075E000000000000000000000000000000000009B +:1075F000000000000000000000000000000000008B +:10760000000000000000000002020202020202016B +:107610000101010101010001000000000000000063 +:10762000000000000000000000000000000000005A +:10763000000000000000000000000000000000004A +:10764000000000000000000000000000000000003A +:107650000000000000000000010102000100010123 +:107660000101000100010001000000000000000015 +:10767000000000000000000000000000000000000A +:1076800000000000000000000000000000000000FA +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000100000002010101D4 +:1076B00001010101010101010202020202020202B2 +:1076C00002020202020202000000000000000000AC +:1076D00000000000000000000000000000000000AA +:1076E000000000000000000000000000000000009A +:1076F000000000000000000000000000000000008A +:10770000000000000000000002020202020202016A +:107710000201010101010001000000000000000061 +:107720000000000000000000000000000000000059 +:107730000000000000000000000000000000000049 +:107740000000000000000000000000000000000039 +:107750000000000000000000010102000100010122 +:107760000101000100010001000000000000000014 +:107770000000000000000000000000000000000009 +:1077800000000000000000000000000000000000F9 +:1077900000000000000000000000000000000000E9 +:1077A00000000000000000000100000002020101D2 +:1077B00001010101010101010202020202020202B1 +:1077C00002020202010202000000000000000000AC +:1077D00000000000000000000000000000000000A9 +:1077E0000000000000000000000000000000000099 +:1077F0000000000000000000000000000000000089 +:107800000000000000000000020202020202020268 +:107810000201010101010001000000000000000060 +:107820000000000000000000000000000000000058 +:107830000000000000000000000000000000000048 +:107840000000000000000000000000000000000038 +:10785000000000000000000002010200010101011F +:107860000101000100010001000000000000000013 +:107870000000000000000000000000000000000008 +:1078800000000000000000000000000000000000F8 +:1078900000000000000000000000000000000000E8 +:1078A00000000000000000000201000002020202CD +:1078B00001010101010101010202020202020202B0 +:1078C00002020102010202000000000000000000AC +:1078D00000000000000000000000000000000000A8 +:1078E0000000000000000000000000000000000098 +:1078F0000000000000000000000000000000000088 +:107900000000000000000000020202020202020267 +:10791000020202010101010100000000000000005C +:107920000000000000000000000000000000000057 +:107930000000000000000000000000000000000047 +:107940000000000000000000000000000000000037 +:10795000000000000000000002020200020101011C +:107960000101000101010001000000000000000011 +:107970000000000000000000000000000000000007 +:1079800000000000000000000000000000000000F7 +:1079900000000000000000000000000000000000E7 +:1079A00000000000000000000201010102020202CA +:1079B00002010101010101010202020202020201AF +:1079C00001010101010102000000000000000000AF +:1079D00000000000000000000000000000000000A7 +:1079E0000000000000000000000000000000000097 +:1079F0000000000000000000000000000000000087 +:107A00000000000000000000020202020202020266 +:107A1000020202010201010100000000000000005A +:107A20000000000000000000000000000000000056 +:107A30000000000000000000000000000000000046 +:107A40000000000000000000000000000000000036 +:107A5000000000000000000002020200020101011B +:107A6000020101010101000100000000000000000E +:107A70000000000000000000000000000000000006 +:107A800000000000000000000000000000000000F6 +:107A900000000000000000000000000000000000E6 +:107AA00000000000000000000202010102020202C8 +:107AB00002010101010101010202020202020101AF +:107AC00001010101010101000000000000000000AF +:107AD00000000000000000000000000000000000A6 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000020202020202020265 +:107B10000202020102010101000000000000000059 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000020202010201010119 +:107B6000020101010101010100000000000000000C +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000202010102020202C7 +:107BB00002020101010101010202020202010101AE +:107BC00001010101010101000000000000000000AE +:107BD00000000000000000000000000000000000A5 +:107BE0000000000000000000000000000000000095 +:107BF0000000000000000000000000000000000085 +:107C00000000000000000000020202020202020264 +:107C10000202020202010101000000000000000057 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000000000034 +:107C50000000000000000000020202010201020117 +:107C6000020201010101010100000000000000000A +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000202020102020202C5 +:107CB00002020102010101010202020201010101AD +:107CC00001010101010101000000000000000000AD +:107CD00000000000000000000000000000000000A4 +:107CE0000000000000000000000000000000000094 +:107CF0000000000000000000000000000000000084 +:107D00000000000000000000020202020202020263 +:107D10000202020202010101000000000000000056 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000000000033 +:107D50000000000000000000020202010201020116 +:107D60000202010101010101000000000000000009 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000000000000E3 +:107DA00000000000000000000202020202020202C3 +:107DB00002020102010101010202020101010101AD +:107DC00001010101010101000000000000000000AC +:107DD00000000000000000000000000000000000A3 +:107DE0000000000000000000000000000000000093 +:107DF0000000000000000000000000000000000083 +:107E00000000000000000000020202020202020262 +:107E10000202020202020102000000000000000053 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000000000032 +:107E50000000000000000000020202010202020213 +:107E60000202010201010101000000000000000007 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000000000000E2 +:107EA00000000000000000000202020202020202C2 +:107EB00002020202010101020202010101010101AB +:107EC00001010101010101010000000000000000AA +:107ED00000000000000000000000000000000000A2 +:107EE0000000000000000000000000000000000092 +:107EF0000000000000000000000000000000000082 +:107F00000000000000000000020202020202020261 +:107F10000202020202020102000000000000000052 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F40000000000000000000000000000000000031 +:107F50000000000000000000020202020202020211 +:107F60000202010201010102000000000000000005 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000000000000E1 +:107FA00000000000000000000202020202020202C1 +:107FB00002020202010101020201010101010101AB +:107FC00001010101010101010000000000000000A9 +:107FD00000000000000000000000000000000000A1 +:107FE0000000000000000000000000000000000091 +:107FF0000000000000000000000000000000000081 +:108000000000000000000000020202020202020260 +:108010000202020202020102000000000000000051 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:108040000000000000000000000000000000000030 +:108050000000000000000000020202020202020210 +:108060000202010201010102000000000000000004 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000000000000000000000000E0 +:1080A00000000000000000000202020202020202C0 +:1080B00002020202020102020201010101010101A8 +:1080C00001010101010101010000000000000000A8 +:1080D00000000000000000000000000000000000A0 +:1080E0000000000000000000000000000000000090 +:1080F0000000000000000000000000000000000080 +:10810000000000000000000002020202020202025F +:108110000202020202020102000000000000000050 +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:10814000000000000000000000000000000000002F +:10815000000000000000000002020202020202020F +:108160000202020201010102000000000000000002 +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000000000000000000000000DF +:1081A00000000000000000000202020202020202BF +:1081B00002020202020202020101010101010101A7 +:1081C00001010101010101010000000000000000A7 +:1081D000000000000000000000000000000000009F +:1081E000000000000000000000000000000000008F +:1081F000000000000000000000000000000000007F +:10820000000000000000000002020202020202025E +:10821000020202020202010200000000000000004F +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:10824000000000000000000000000000000000002E +:10825000000000000000000002020202020202020E +:1082600002020202020201020000000000000000FF +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000000000000000000000000000000DE +:1082A00000000000000000000202020202020202BE +:1082B00002020202020202020101010101010101A6 +:1082C00001010101010101010000000000000000A6 +:1082D000000000000000000000000000000000009E +:1082E000000000000000000000000000000000008E +:1082F000000000000000000000000000000000007E +:10830000000000000000000002020202020202025D +:10831000020202020202020200000000000000004D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:10834000000000000000000000000000000000002D +:10835000000000000000000002020202020202020D +:1083600002020202020201020000000000000000FE +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000000000000000000000000000000DD +:1083A00000000000000000000202020202020202BD +:1083B00002020202020202020101010101010101A5 +:1083C00001010101010101010000000000000000A5 +:1083D000000000000000000000000000000000009D +:1083E000000000000000000000000000000000008D +:1083F000000000000000000000000000000000007D +:10840000000000000000000002020202020202025C +:10841000020202020202020200000000000000004C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:10844000000000000000000000000000000000002C +:10845000000000000000000002020202020202020C +:1084600002020202020201020000000000000000FD +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900000000000000000000000000000000000DC +:1084A00000000000000000000202020202020202BC +:1084B00002020202020202020101010101010101A4 +:1084C00001010101010101010000000000000000A4 +:1084D000000000000000000000000000000000009C +:1084E000000000000000000000000000000000008C +:1084F000000000000000000000000000000000007C +:10850000000000000000000002020202020202025B +:10851000020202020202020200000000000000004B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000000000000000000000000000000000002B +:10855000000000000000000002020202020202020B +:1085600002020202020201020000000000000000FC +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900000000000000000000000000000000000DB +:1085A00000000000000000000202020202020202BB +:1085B00002020202020202020101010101010101A3 +:1085C00001010101010101010000000000000000A3 +:1085D000000000000000000000000000000000009B +:1085E000000000000000000000000000000000008B +:1085F000000000000000000000000000000000007B +:10860000000000000000000002020202020202025A +:10861000020202020202020200000000000000004A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000000000000000000000000000000000002A +:10865000000000000000000002020202020202020A +:1086600002020202020201020000000000000000FB +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900000000000000000000000000000000000DA +:1086A00000000000000000000202020202020202BA +:1086B00002020202020202020101010101010101A2 +:1086C00001010101010101010000000000000000A2 +:1086D000000000000000000000000000000000009A +:1086E000000000000000000000000000000000008A +:1086F000000000000000000000000000000000007A +:108700000000000000000000020202020202020259 +:108710000202020202020202000000000000000049 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000000000000000000000000000000000029 +:108750000000000000000000020202020202020209 +:1087600002020202020201020000000000000000FA +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900000000000000000000000000000000000D9 +:1087A00000000000000000000202020202020202B9 +:1087B00002020202020202020101010101010101A1 +:1087C00001010101010101010000000000000000A1 +:1087D0000000000000000000000000000000000099 +:1087E0000000000000000000000000000000000089 +:1087F0000000000000000000000000000000000079 +:108800000000000000000000020202020201020259 +:10881000010101020102020200000000000000004C +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000000000000000000000000000000000028 +:108850000000000000000000020202020202020208 +:1088600002020202020202020000000000000000F8 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900000000000000000000000000000000000D8 +:1088A00000000000000000000202020202020202B8 +:1088B00002020202020202020101010101010101A0 +:1088C00001010101010101010000000000000000A0 +:1088D0000000000000000000000000000000000098 +:1088E0000000000000000000000000000000000088 +:1088F0000000000000000000000000000000000078 +:10890000000000000000000002020202010101015B +:10891000010101010102020200000000000000004C +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:108940000000000000000000000000000000000027 +:108950000000000000000000020202020202020207 +:1089600002020202020202020000000000000000F7 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900000000000000000000000000000000000D7 +:1089A00000000000000000000202020202020202B7 +:1089B000020202020202020201010101010101019F +:1089C000010101010101010100000000000000009F +:1089D0000000000000000000000000000000000097 +:1089E0000000000000000000000000000000000087 +:1089F0000000000000000000000000000000000077 +:108A0000000000000000000002020101010101015C +:108A1000010101010101020200000000000000004C +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A40000000000000000000000000000000000026 +:108A50000000000000000000020202020202020206 +:108A600002020202020202020000000000000000F6 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900000000000000000000000000000000000D6 +:108AA00000000000000000000202020202020202B6 +:108AB000020202020202020201010101010101019E +:108AC000010101010101010100000000000000009E +:108AD0000000000000000000000000000000000096 +:108AE0000000000000000000000000000000000086 +:108AF0000000000000000000000000000000000076 +:108B0000000000000000000001010101010101015D +:108B1000010101010101020200000000000000004B +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000000000000000000000000000000000025 +:108B50000000000000000000020202020202020205 +:108B600002020202020202020000000000000000F5 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900000000000000000000000000000000000D5 +:108BA00000000000000000000202020202020202B5 +:108BB000020202020202020201010101010101019D +:108BC000010101010101010100000000000000009D +:108BD0000000000000000000000000000000000095 +:108BE0000000000000000000000000000000000085 +:108BF0000000000000000000000000000000000075 +:108C0000000000000000000001010101010101015C +:108C1000010101010101010100000000000000004C +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000000000000000000000000000000000024 +:108C50000000000000000000020202020202020204 +:108C600002020202020202020000000000000000F4 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900000000000000000000000000000000000D4 +:108CA00000000000000000000202020202020202B4 +:108CB000020202020202020201010101010101019C +:108CC000010101010101010100000000000000009C +:108CD0000000000000000000000000000000000094 +:108CE0000000000000000000000000000000000084 +:108CF0000000000000000000000000000000000074 +:108D0000000000000000000001010101010101015B +:108D1000010101010101010100000000000000004B +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000000000000000000000000000000000023 +:108D50000000000000000000020202020202020203 +:108D600002020202020202020000000000000000F3 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900000000000000000000000000000000000D3 +:108DA00000000000000000000202020202020202B3 +:108DB000020202020202020201010101010101019B +:108DC000010101010101010100000000000000009B +:108DD0000000000000000000000000000000000093 +:108DE0000000000000000000000000000000000083 +:108DF0000000000000000000000000000000000073 +:108E0000000000000000000001010101010101015A +:108E1000010101010101010100000000000000004A +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000000000000000000000000000000000022 +:108E50000000000000000000020202020202020202 +:108E600002020202020202020000000000000000F2 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900000000000000000000000000000000000D2 +:108EA00000000000000000000202020202020202B2 +:108EB000020202020202020201010101010101019A +:108EC000010101010101010100000000000000009A +:108ED0000000000000000000000000000000000092 +:108EE0000000000000000000000000000000000082 +:108EF0000000000000000000000000000000000072 +:108F00000000000000000000010101010101010159 +:108F10000101010101010101000000000000000049 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000000000000000000000000000000000021 +:108F50000000000000000000020202020202020201 +:108F600002020202020202020000000000000000F1 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900000000000000000000000000000000000D1 +:108FA00000000000000000000202020202020202B1 +:108FB0000202020202020202010101010101010199 +:108FC0000101010101010101000000000000000099 +:108FD0000000000000000000000000000000000091 +:108FE0000000000000000000000000000000000081 +:108FF0000000000000000000000000000000000071 +:109000000000000000000000010101010101010158 +:109010000101010101010101000000000000000048 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000000000000000000000000000000000020 +:109050000000000000000000020202020202020200 +:1090600001010101010202020000000000000000F5 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900000000000000000000000000000000000D0 +:1090A00000000000000000000202020202020202B0 +:1090B0000202020202020202010101010101010198 +:1090C0000101010101010101000000000000000098 +:1090D0000000000000000000000000000000000090 +:1090E0000000000000000000000000000000000080 +:1090F0000000000000000000000000000000000070 +:109100000000000000000000010101010101010157 +:109110000101010101010101000000000000000047 +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000000000000000000000000000000000001F +:109150000000000000000000020201020101010104 +:1091600001010101010102010000000000000000F6 +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900000000000000000000000000000000000CF +:1091A00000000000000000000202020202020202AF +:1091B0000202020202020202010101010101010197 +:1091C0000101010101010101000000000000000097 +:1091D000000000000000000000000000000000008F +:1091E000000000000000000000000000000000007F +:1091F000000000000000000000000000000000006F +:109200000000000000000000010101010101010156 +:109210000101010101010101000000000000000046 +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:10924000000000000000000000000000000000001E +:109250000000000000000000010101010101010106 +:1092600001010101010102010000000000000000F5 +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900000000000000000000000000000000000CE +:1092A00000000000000000000202020202020201AF +:1092B000010101010101010101010101010101019E +:1092C0000101010101010101000000000000000096 +:1092D000000000000000000000000000000000008E +:1092E000000000000000000000000000000000007E +:1092F000000000000000000000000000000000006E +:109300000000000000000000010101010101010155 +:109310000101010101010101000000000000000045 +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000000000000000000000000000000000001D +:109350000000000000000000010101010101010105 +:1093600001010101010101010000000000000000F5 +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900000000000000000000000000000000000CD +:1093A00000000000000000000000000002020200B7 +:1093B00000000000000000000101010101010101A5 +:1093C0000101010101010101000000000000000095 +:1093D000000000000000000000000000000000008D +:1093E000000000000000000000000000000000007D +:1093F000000000000000000000000000000000006D +:109400000000000000000000010101010101010154 +:109410000101010101010101000000000000000044 +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000000000000000000000000000000000001C +:109450000000000000000000010101010101010104 +:1094600001010101010101010000000000000000F4 +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900000000000000000000000000000000000CC +:1094A00000000000000000000000000001010100B9 +:1094B00000000000000000000101010101010101A4 +:1094C0000101010101010101000000000000000094 +:1094D000000000000000000000000000000000008C +:1094E000000000000000000000000000000000007C +:1094F000000000000000000000000000000000006C +:109500000000000000000000010101010101010153 +:109510000101010101010101000000000000000043 +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000000000000000000000000000000000001B +:109550000000000000000000010101010101010103 +:1095600001010101010101010000000000000000F3 +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900000000000000000000000000000000000CB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000101010101010101A3 +:1095C0000101010101010101000000000000000093 +:1095D000000000000000000000000000000000008B +:1095E000000000000000000000000000000000007B +:1095F000000000000000000000000000000000006B +:109600000000000000000000010101010101010152 +:109610000101010101010101000000000000000042 +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000000000000000000000000000000000001A +:109650000000000000000000010101010101010102 +:1096600001010101010101010000000000000000F2 +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900000000000000000000000000000000000CA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000101010101010101A2 +:1096C0000101010101010101000000000000000092 +:1096D000000000000000000000000000000000008A +:1096E000000000000000000000000000000000007A +:1096F000000000000000000000000000000000006A +:109700000000000000000000010101010101010151 +:109710000101010101010101000000000000000041 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000000000000000000000000000000000019 +:109750000000000000000000010101010101010101 +:1097600001010101010101010000000000000000F1 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900000000000000000000000000000000000C9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000099 +:1097D0000000000000000000000000000000000089 +:1097E0000000000000000000000000000000000079 +:1097F0000000000000000000000000000000000069 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:109840000000000000000000000000000000000018 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900000000000000000000000000000000000C8 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000002C000000000000007C +:1098C000000000000102000200020200020000008D +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000000000000000078 +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000000000057 +:109910000000000000000000000000000000000047 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000010000000000000000000000000000F6 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000000B7 +:1099B00000000101010100000000000000000000A3 +:1099C0000101010002020202020202000200000084 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0000000000000000000000000000000000067 +:109A00000000000000000000000000000000000056 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000000000000000000000000000006 +:109A600000010000000000000000010000000000F4 +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000000000000C6 +:109AA00000000000000000000000000000000000B6 +:109AB00000000101010100000000000000000000A2 +:109AC000010202000202020202020202020000007F +:109AD0000000000000000000000000000000000086 +:109AE0000000000000000000000000000000000076 +:109AF0000000000000000000000000000000000066 +:109B00000000000000000000000000000000000055 +:109B10000000000000000000000000000000000144 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000000000000000000000000000005 +:109B600000010100000000000000010000000000F2 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000000000000C5 +:109BA00000000000000000000000000000000000B5 +:109BB00000000101010100000000000000000001A0 +:109BC000020202000202020202020202020201007A +:109BD0000000000000000000000000000000000085 +:109BE0000000000000000000000000000000000075 +:109BF0000000000000000000000000000000000065 +:109C00000000000000000000000000000000000054 +:109C10000000000000000000000000000000000143 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000000000000000000000000000004 +:109C600000010101000000010000010100000000EE +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000000000000C4 +:109CA00000000000000000000000000000000000B4 +:109CB000000001010101000000000000000000019F +:109CC0000202020202020202020202020202010077 +:109CD0000000000000000000000000000000000084 +:109CE0000000000000000000000000000000000074 +:109CF0000000000000000000000000000000000064 +:109D00000000000000000000000000000000000053 +:109D10000001000000000000000000000000000141 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D50000000000000000000000000000000000003 +:109D600000010101000000010000010100010000EC +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000000000000C3 +:109DA00000000000000000000000000000000000B3 +:109DB000000001010101010000000000000000019D +:109DC0000202020202020202020202020202020075 +:109DD0000000000000000000000000000000000083 +:109DE0000000000000000000000000000000000073 +:109DF0000000000000000000000000000000000063 +:109E00000000000000000000000000000000000052 +:109E1000000100000000000000000100000000013F +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E50000000000000000000000000000000000002 +:109E600000010101010000010000010100010000EA +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000000000000C2 +:109EA00000000000000000000000000000000000B2 +:109EB000000001010101010100000000000000019B +:109EC0000202020202020202020202020202020074 +:109ED0000000000000000000000000000000000082 +:109EE0000000000000000000000000000000000072 +:109EF0000000000000000000000000000000000062 +:109F00000000000000000000000000000000000051 +:109F1000000101000000000000000100000000013D +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F50000000000000000000000000000000000001 +:109F600000010101010000010100010100010100E7 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000000000000C1 +:109FA00000000000000000000000000000000000B1 +:109FB000000001010101010100000000000000019A +:109FC0000202020202020202020202020202020073 +:109FD0000000000000000000000000000000000081 +:109FE0000000000000000000000000000000000071 +:109FF0000000000000000000000000000000000061 +:10A000000000000000000000000000000000000050 +:10A01000000101000000000100000100000000013B +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A040000000000000000000000000000000000010 +:10A050000000000000000000000000000000000000 +:10A0600000010101010000010100010101010100E5 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000000000000C0 +:10A0A00000000000000000000000000000000000B0 +:10A0B0000000010101010101000000000000000199 +:10A0C0000202020202020202020202020202020072 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000000000000000000070 +:10A0F0000000000000000000000000000000000060 +:10A10000000000000000000000000000000000004F +:10A11000000101000000000100000100000000013A +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000000000000000000000F +:10A1500000000000000000000000000000000000FF +:10A1600000010101010000010100010101010101E3 +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000000000000BF +:10A1A00000000000000000000000000000000000AF +:10A1B0000000010101010101010000000000000197 +:10A1C0000202020202020202020202020202020071 +:10A1D000000000000000000000000000000000007F +:10A1E000000000000000000000000000000000006F +:10A1F000000000000000000000000000000000005F +:10A20000000000000000000000000000000000004E +:10A210000002010100000001000001000000000137 +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A24000000000000000000000000000000000000E +:10A2500000000000000000000000000000000000FE +:10A2600000020101010100010101010101010101DF +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000000000000BE +:10A2A00000000000000000000000000000000000AE +:10A2B0000000010101010101010101010000000193 +:10A2C0000202020202020202020202020202020070 +:10A2D000000000000000000000000000000000007E +:10A2E000000000000000000000000000000000006E +:10A2F000000000000000000000000000000000005E +:10A30000000000000000000000000000000000004D +:10A310000102010100000001000001000000000135 +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A34000000000000000000000000000000000000D +:10A3500000000000000000000000000000000000FD +:10A3600000020101010101010101010101010101DD +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000000000000BD +:10A3A00000000000000000000000000000000000AD +:10A3B0000000020101010101010101010000000191 +:10A3C000020202020202020202020202020202006F +:10A3D000000000000000000000000000000000007D +:10A3E000000000000000000000000000000000006D +:10A3F000000000000000000000000000000000005D +:10A40000000000000000000000000000000000004C +:10A410000102020101000001000101000000000131 +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A44000000000000000000000000000000000000C +:10A4500000000000000000000000000000000000FC +:10A4600000020201010101010101010101010101DB +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000000000000000000BC +:10A4A00000000000000000000000000000000000AC +:10A4B0000000020101010101010101010000000190 +:10A4C000020202020202020202020202020202006E +:10A4D000000000000000000000000000000000007C +:10A4E000000000000000000000000000000000006C +:10A4F000000000000000000000000000000000005C +:10A50000000000000000000000000000000000004B +:10A51000020202010100010101010100000001012C +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A54000000000000000000000000000000000000B +:10A5500000000000000000000000000000000000FB +:10A5600001020201010101010101010101010101D9 +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000000000000000000BB +:10A5A00000000000000000000000000000000000AB +:10A5B000010002010102010101010101000001018C +:10A5C000020202020202020202020202010202006E +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000000000000000000006B +:10A5F000000000000000000000000000000000005B +:10A60000000000000000000000000000000000004A +:10A610000202020101000102010101000100010129 +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A64000000000000000000000000000000000000A +:10A6500000000000000000000000000000000000FA +:10A6600001020202010101010101010101010101D7 +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000000000000000000BA +:10A6A00000000000000000000000000000000000AA +:10A6B0000100020201020101010101010100010189 +:10A6C0000202020202020202020201010101020070 +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000000000000000000006A +:10A6F000000000000000000000000000000000005A +:10A700000000000000000000000000000000000049 +:10A710000202020201000102010102000100010126 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A740000000000000000000000000000000000009 +:10A7500000000000000000000000000000000000F9 +:10A7600001020202010101020101010101010101D5 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000000000000000000B9 +:10A7A00000000000000000000000000000000000A9 +:10A7B0000200020202020201010101010100010185 +:10A7C0000202020202020202020101010101010071 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000000000000000000069 +:10A7F0000000000000000000000000000000000059 +:10A800000000000000000000000000000000000048 +:10A810000202020201000102010102010100010124 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A840000000000000000000000000000000000008 +:10A8500000000000000000000000000000000000F8 +:10A8600002020202020101020101020101010101D1 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000000000000000000B8 +:10A8A00000000000000000000000000000000000A8 +:10A8B0000200020202020202010101010100010183 +:10A8C0000202020202020201010101010101010072 +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000000000000000000068 +:10A8F0000000000000000000000000000000000058 +:10A900000000000000000000000000000000000047 +:10A91000020202020200020202020201010001011F +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A940000000000000000000000000000000000007 +:10A9500000000000000000000000000000000000F7 +:10A9600002020202020101020201020101010101CF +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000000000000000000B7 +:10A9A00000000000000000000000000000000000A7 +:10A9B0000201020202020202010101010101010180 +:10A9C0000202020202010101010101010101010073 +:10A9D0000000000000000000000000000000000077 +:10A9E0000000000000000000000000000000000067 +:10A9F0000000000000000000000000000000000057 +:10AA00000000000000000000000000000000000046 +:10AA1000020202020201020202020201010001011D +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA40000000000000000000000000000000000006 +:10AA500000000000000000000000000000000000F6 +:10AA600002020202020201020201020201010101CC +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000000000000000000B6 +:10AAA00000000000000000000000000000000000A6 +:10AAB000020202020202020202010101010101017D +:10AAC0000202020201010101010101010101010073 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000000000000000000066 +:10AAF0000000000000000000000000000000000056 +:10AB00000000000000000000000000000000000045 +:10AB1000020202020201020202020201010101011B +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB40000000000000000000000000000000000005 +:10AB500000000000000000000000000000000000F5 +:10AB600002020202020202020202020201020101C8 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000000000000000000B5 +:10ABA00000000000000000000000000000000000A5 +:10ABB000020202020202020202020101010101017B +:10ABC0000202020201010101010101010101010072 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000000000000000000065 +:10ABF0000000000000000000000000000000000055 +:10AC00000000000000000000000000000000000044 +:10AC10000202020202020202020202010101010218 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC40000000000000000000000000000000000004 +:10AC500000000000000000000000000000000000F4 +:10AC600002020202020202020202020202020101C6 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000000000000000000B4 +:10ACA00000000000000000000000000000000000A4 +:10ACB0000202020202020202020202010101010278 +:10ACC0000202020101010101010101010101010072 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000000000000000000064 +:10ACF0000000000000000000000000000000000054 +:10AD00000000000000000000000000000000000043 +:10AD10000202020202020202020202010201010216 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600002020202020202020202020202020101C5 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000000000000000000B3 +:10ADA00000000000000000000000000000000000A3 +:10ADB0000202020202020202020202020101010276 +:10ADC0000202010101010101010101010101010171 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000000000000000000063 +:10ADF0000000000000000000000000000000000053 +:10AE00000000000000000000000000000000000042 +:10AE10000202020202020202020202020201010214 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE40000000000000000000000000000000000002 +:10AE500000000000000000000000000000000000F2 +:10AE600002020202020202020202020202020201C3 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000000000000000000B2 +:10AEA00000000000000000000000000000000000A2 +:10AEB0000202020202020202020202020101010275 +:10AEC0000201010101010101010101010101010171 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000000000000000000062 +:10AEF0000000000000000000000000000000000052 +:10AF00000000000000000000000000000000000041 +:10AF10000202020202020202020202020201010213 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF40000000000000000000000000000000000001 +:10AF500000000000000000000000000000000000F1 +:10AF600002020202020202020202020202020201C2 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000000000000000000B1 +:10AFA00000000000000000000000000000000000A1 +:10AFB0000202020202020202020202020201010273 +:10AFC0000201010101010101010101010101010170 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000000000000000000061 +:10AFF0000000000000000000000000000000000051 +:10B000000000000000000000000000000000000040 +:10B010000202020202020202020202020201020211 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600002020202020202020202020202020201C1 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000000000000000000B0 +:10B0A00000000000000000000000000000000000A0 +:10B0B0000202020202020202020202020201020271 +:10B0C0000101010101010101010101010101010170 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000000000000000000060 +:10B0F0000000000000000000000000000000000050 +:10B10000000000000000000000000000000000003F +:10B11000020202020202020202020202020202020F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000000000000000000FF +:10B1500000000000000000000000000000000000EF +:10B1600002020202020202020202020202020202BF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B1900000000000000000000000000000000000AF +:10B1A000000000000000000000000000000000009F +:10B1B000020202020202020202020202020202026F +:10B1C000010101010101010101010101010101016F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000000000000000000005F +:10B1F000000000000000000000000000000000004F +:10B20000000000000000000000000000000000003E +:10B21000020202020202020202020202020202020E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000000000000000000FE +:10B2500000000000000000000000000000000000EE +:10B2600002020202020202020202020202020202BE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B2900000000000000000000000000000000000AE +:10B2A000000000000000000000000000000000009E +:10B2B000020202020202020202020202020202026E +:10B2C000010101010101010101010101010101016E +:10B2D000000000000000000000000000000000006E +:10B2E000000000000000000000000000000000005E +:10B2F000000000000000000000000000000000004E +:10B30000000000000000000000000000000000003D +:10B31000020202020202020202020202020202020D +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000000000000000000FD +:10B3500000000000000000000000000000000000ED +:10B3600002020202020202020202020202020202BD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B3900000000000000000000000000000000000AD +:10B3A000000000000000000000000000000000009D +:10B3B000020202020202020202020202020202026D +:10B3C000010101010101010101010101010101016D +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000000000000000005D +:10B3F000000000000000000000000000000000004D +:10B40000000000000000000000000000000000003C +:10B41000020202020202020202020202020202020C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000000000000000000FC +:10B4500000000000000000000000000000000000EC +:10B4600002020202020202020202020202020202BC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000000000000000000AC +:10B4A000000000000000000000000000000000009C +:10B4B000020202020202020202020202020202026C +:10B4C000010101010101010101010101010101016C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000000000000000005C +:10B4F000000000000000000000000000000000004C +:10B50000000000000000000000000000000000003B +:10B51000020202020202020202020202020202020B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000000000000000000FB +:10B5500000000000000000000000000000000000EB +:10B5600002020202020202020202020202020202BB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000000000000000000AB +:10B5A000000000000000000000000000000000009B +:10B5B000020202020202020202020202020202026B +:10B5C000010101010101010101010101010101016B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000000000000005B +:10B5F000000000000000000000000000000000004B +:10B60000000000000000000000000000000000003A +:10B61000020202020202020202020202020202020A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000000000000000000FA +:10B6500000000000000000000000000000000000EA +:10B6600002020202020202020202020202020202BA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000000000000000000AA +:10B6A000000000000000000000000000000000009A +:10B6B000020202020202020202020202020202026A +:10B6C000010101010101010101010101010101016A +:10B6D000000000000000000000000000000000006A +:10B6E000000000000000000000000000000000005A +:10B6F000000000000000000000000000000000004A +:10B700000000000000000000000000000000000039 +:10B71000020202020202020101010102020202020D +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600002020202020202020202020202020202B9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000202020202020202020202020202020269 +:10B7C0000101010101010101010101010101010169 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F0000000000000000000000000000000000049 +:10B800000000000000000000000000000000000038 +:10B81000020202020202010101010101010202020F +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000000000E8 +:10B8600002020202020202020202020202020202B8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000202020202020202020202020202020268 +:10B8C0000101010101010101010101010101010168 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000000000000000000000000000000000037 +:10B910000201010101010101010101010101020214 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000000000E7 +:10B9600002020202020202020202020202020202B7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000000000097 +:10B9B0000202020202020202020202020202020267 +:10B9C0000101010101010101010101010101010167 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000000000047 +:10BA00000000000000000000000000000000000036 +:10BA10000101010101010101010101010101010116 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000000000E6 +:10BA600002020202020202020202020202020202B6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000000000000096 +:10BAB0000202020202020202020202020202020266 +:10BAC0000101010101010101010101010101010166 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000000000000046 +:10BB00000000000000000000000000000000000035 +:10BB10000101010101010101010101010101010115 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000000000000E5 +:10BB600002020202020202020202020202020202B5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000000000000095 +:10BBB0000202020202020202020202020202020265 +:10BBC0000101010101010101010101010101010165 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF0000000000000000000000000000000000045 +:10BC00000000000000000000000000000000000034 +:10BC10000101010101010101010101010101010114 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000000000000E4 +:10BC600002020202020202020202020202020202B4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA0000000000000000000000000000000000094 +:10BCB0000202020202020202020202020202020264 +:10BCC0000101010101010101010101010101010164 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000000000000000000000000000000000044 +:10BD00000000000000000000000000000000000033 +:10BD10000101010101010101010101010101010113 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000000000000E3 +:10BD600002020202020202010101010101010202BA +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA0000000000000000000000000000000000093 +:10BDB0000202020202020202020202020202020263 +:10BDC0000101010101010101010101010101010163 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000000000000000000000000000000000043 +:10BE00000000000000000000000000000000000032 +:10BE10000101010101010101010101010101010112 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000000000000000E2 +:10BE600002010101010101010101010101010102C0 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA0000000000000000000000000000000000092 +:10BEB000020202020202010101010101010101016C +:10BEC0000101010101010101010101010101010162 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000000000000000000000000000000000042 +:10BF00000000000000000000000000000000000031 +:10BF10000101010101010101010101010101010111 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000000000000000E1 +:10BF600001010101010101010101010101010101C1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA0000000000000000000000000000000000091 +:10BFB000000002020201000000000000000000007A +:10BFC0000101010101010101010101010101010161 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000000000000000000000000000041 +:10C000000000000000000000000000000000000030 +:10C010000101010101010101010101010101010110 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500000000000000000000000000000000000E0 +:10C0600001010101010101010101010101010101C0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000000000000000000000000000000000090 +:10C0B000000001020200000000000000000000007B +:10C0C0000101010101010101010101010101010160 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000000000000000000000000000040 +:10C10000000000000000000000000000000000002F +:10C11000010101010101010101010101010101010F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500000000000000000000000000000000000DF +:10C1600001010101010101010101010101010101BF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A000000000000000000000000000000000008F +:10C1B000000000020200000000000000000000007B +:10C1C000010101010101010101010101010101015F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000003F +:10C20000000000000000000000000000000000002E +:10C21000010101010101010101010101010101010E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500000000000000000000000000000000000DE +:10C2600001010101010101010101010101010101BE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000000000000000000000000000000000008E +:10C2B000000000020200000000000000000000007A +:10C2C000010101010101010101010101010101015E +:10C2D000000000000000000000000000000000005E +:10C2E000000000000000000000000000000000004E +:10C2F000000000000000000000000000000000003E +:10C30000000000000000000000000000000000002D +:10C31000010101010101010101010101010101010D +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500000000000000000000000000000000000DD +:10C3600001010101010101010101010101010101BD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000000000000000000000000000000000008D +:10C3B000000000010100000000000000000000007B +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000000000000000000000000000000000003D +:10C40000000000000000000000000000000000002C +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500000000000000000000000000000000000DC +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000000000000000000000000000000000008C +:10C4B000000000000000000000000000000000007C +:10C4C0002C00000000000000000000000000000040 +:10C4D0000001000101000100000000000000000058 +:10C4E000000000000000000000000000000000004C +:10C4F000000000000000000000000000000000003C +:10C50000000000000000000000000000000000002B +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500000000000000000000000000000000000DB +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A000000000000000000000000000000000008B +:10C5B000000000000000000000000000000000007B +:10C5C0000000000000000001010101010101010162 +:10C5D0000201010101010100000000000000000053 +:10C5E000000000000000000000000000000000004B +:10C5F000000000000000000000000000000000003B +:10C60000000000000000000000000000000000002A +:10C610000000000000000000000000000001000019 +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500000000000000000000000000000000000DA +:10C6600000000000000000000000000100000000C9 +:10C6700000000000000000010000000000000000B9 +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A000000000000000000000000000000000008A +:10C6B000000000000000000000000000000000007A +:10C6C0000000000000000001010101010101010161 +:10C6D0000202010201010100000000000000000050 +:10C6E000000000000000000000000000000000004A +:10C6F000000000000000000000000000000000003A +:10C700000000000000000000000000000000000029 +:10C710000000000000000000000000000001000018 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500000000000000000000000000000000000D9 +:10C7600000000000000000000001000100000000C7 +:10C7700000000000000000010000000000000000B8 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000000000000000000000000000000000089 +:10C7B0000000000000000000000000000000000079 +:10C7C000000000000000000101010101010102025E +:10C7D000020202020101010000000000000000004E +:10C7E0000000000000000000000000000000000049 +:10C7F0000000000000000000000000000000000039 +:10C800000000000000000000000000000000000028 +:10C810000000000000000000000100000101000015 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500000000000000000000000000000000000D8 +:10C8600000000000000000000101010100000000C4 +:10C8700000000000000000010000000000000000B7 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000000000000000000000000000000000088 +:10C8B0000000000000000000000000000000000078 +:10C8C000000000000000000101010201020102025B +:10C8D000020202020101010000000000000000004D +:10C8E0000000000000000000000000000000000048 +:10C8F0000000000000000000000000000000000038 +:10C900000000000000000000000000000000000027 +:10C910000000000000000000000100000101000014 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500000000000000000000000000000000000D7 +:10C9600000000000000000000101010100000000C3 +:10C9700000000000000000010000000000000000B6 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000000000000000000000000000000000087 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000001010202010202020258 +:10C9D000020202020201010000000000000000004B +:10C9E0000000000000000000000000000000000047 +:10C9F0000000000000000000000000000000000037 +:10CA00000000000000000000000000000000000026 +:10CA10000000000000000000010100000101000012 +:10CA20000000000000000001000000000000000005 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500000000000000000000000000000000000D6 +:10CA600000000000000000000101010101010000C0 +:10CA700000000000000000010000000000000000B5 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000000000000000000000000000000000086 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000001020202020202020255 +:10CAD0000202020202020100000000000000000049 +:10CAE0000000000000000000000000000000000046 +:10CAF0000000000000000000000000000000000036 +:10CB00000000000000000000000000000000000025 +:10CB10000000000000000000010100000101000011 +:10CB20000000000000000001000000000000000004 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500000000000000000000000000000000000D5 +:10CB600000000000000000000101010101010000BF +:10CB700000000000000001010000000000000000B3 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000000000000000000000000000000000085 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000001020202020202020254 +:10CBD0000202020202020100000000000000000048 +:10CBE0000000000000000000000000000000000045 +:10CBF0000000000000000000000000000000000035 +:10CC00000000000000000000000000000000000024 +:10CC1000000000000000000001010101010100000E +:10CC20000000000000010001000000000000000002 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500000000000000000000000000000000000D4 +:10CC600000000000000000000101010101010000BE +:10CC700000000000000101010000000000000000B1 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000000000000000000000000000000000084 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000001020202020202020253 +:10CCD0000202020202020200000000000000000046 +:10CCE0000000000000000000000000000000000044 +:10CCF0000000000000000000000000000000000034 +:10CD00000000000000000000000000000000000023 +:10CD1000000000000000000002020101010100000B +:10CD20000000000000010001000000000000000001 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500000000000000000000000000000000000D3 +:10CD600000000000000000000101010101010000BD +:10CD700000000000000101010000000000000000B0 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000000000000000000000000000000000083 +:10CDB0000000000000000000000000000001000072 +:10CDC0000000000000000001020202020202020252 +:10CDD0000202020202020200000000000000000045 +:10CDE0000000000000000000000000000000000043 +:10CDF0000000000000000000000000000000000033 +:10CE00000000000000000000000000000000000022 +:10CE1000000000000000000002020101010100000A +:10CE20000000000000010001000000000000000000 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500000000000000000000000000000000000D2 +:10CE600000000000000000000201010101010001BA +:10CE700000000000000101010000000000000000AF +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000000000000000000000000000000000082 +:10CEB0000000000000000000000001000001000070 +:10CEC0000000000000000001020202020202020251 +:10CED0000202020202020200000000000000000044 +:10CEE0000000000000000000000000000000000042 +:10CEF0000000000000000000000000000000000032 +:10CF00000000000000000000000000000000000021 +:10CF10000000000000000000020201010202000007 +:10CF200000000000000100010000000000000000FF +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000202010101010001B8 +:10CF700000000000010101010000000000000000AD +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000000000000000000000000000000000081 +:10CFB000000000000000000000010100000100006E +:10CFC000000000000001010102020202020202024E +:10CFD0000202020202020200000000000000000043 +:10CFE0000000000000000000000000000000000041 +:10CFF0000000000000000000000000000000000031 +:10D000000000000000000000000000000000000020 +:10D010000000000000000000020202010202000104 +:10D0200001000000000100010000000000000000FD +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500000000000000000000000000000000000D0 +:10D0600000000000000000000202020101010101B5 +:10D0700000000000010101010000000000000000AC +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000000000000000000000000000000000080 +:10D0B000000000000000000000010100000100016C +:10D0C000000000000101010102020202020202024C +:10D0D0000202020202020200000000000000000042 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000000000000000000000000000000000001F +:10D110000000000000000000020202010202000103 +:10D1200001000000000100010000000000000000FC +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500000000000000000000000000000000000CF +:10D1600000000000000000000202020201010101B3 +:10D1700000000000010101010000000000000000AB +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000000000000000000000000000000000007F +:10D1B000000000000000000001010000010100016A +:10D1C000000000000101010102020202020202024B +:10D1D0000202020202020200000000000000000041 +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000000000000000000000000000000000001E +:10D210000000000000000000020202020202010100 +:10D2200001000000000100010000000000000000FB +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500000000000000000000000000000000000CE +:10D2600000000000000000000202020201010101B2 +:10D2700000000100010101010000000000000000A9 +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000000000000000000000000000000000007E +:10D2B0000000000000000000010000010101000169 +:10D2C000000000000101010002020202020202024B +:10D2D0000202020202020200000000000000000040 +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000000000000000000000000000000000001D +:10D3100000000000000000000202020202020101FF +:10D3200001000001010100010000000000000000F8 +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500000000000000000000000000000000000CD +:10D3600000000000000000000202020202010101B0 +:10D3700001010101010101010000000000000000A5 +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000000000000000000000000000000000007D +:10D3B0000000000000000000020000010100010167 +:10D3C000000000000101010002020202020202024A +:10D3D0000102020102020200000000000000000041 +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000000000000000000000000000000000001C +:10D4100000000000000000000202020202020101FE +:10D4200002000001010100010000000000000000F6 +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500000000000000000000000000000000000CC +:10D4600000000000000000000202020202020101AE +:10D4700001010101010101010000000000000000A4 +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000000000000000000000000000000000007C +:10D4B0000000000000000000020000010100010166 +:10D4C0000000000001010100020202020202020249 +:10D4D0000101010102020200000000000000000042 +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D5100000000000000000000202020202020202FB +:10D5200002010001010101010000000000000000F3 +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000202020202020101AD +:10D5700001010101010101010000000000000000A3 +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B0000000000000000000020000010000010067 +:10D5C0000100000001010100020202020202020148 +:10D5D0000101010101010200000000000000000043 +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D60000000000000000000000000000000000001A +:10D6100000000000000000000202020202020202FA +:10D6200002010001010101010000000000000000F2 +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000202020202020101AC +:10D6700001010101010101010000000000000000A2 +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B0000000000000000000020200010000000065 +:10D6C0000101010101010100020202020202010145 +:10D6D0000101010101010200000000000000000042 +:10D6E000000000000000000000000000000000003A +:10D6F000000000000000000000000000000000002A +:10D700000000000000000000000000000000000019 +:10D7100000000000000000000202020202020202F9 +:10D7200002010001010201010000000000000000F0 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000000000000C9 +:10D7600000000000000000000202020202020202A9 +:10D7700001010101010101010000000000000000A1 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000020200010000000064 +:10D7C0000001010101000100020202020202010146 +:10D7D0000101010101010100000000000000000042 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000000000029 +:10D800000000000000000000000000000000000018 +:10D8100000000000000000000202020202020202F8 +:10D8200002020102010201020000000000000000EB +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000000000000C8 +:10D8600000000000000000000202020202020202A8 +:10D87000010101010101010200000000000000009F +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000000000078 +:10D8B0000000000000000000020202000000000062 +:10D8C000000001010000000002020202010101014A +:10D8D0000101010101010100000000000000000041 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000000000000000028 +:10D900000000000000000000000000000000000017 +:10D9100000000000000000000202020202020202F7 +:10D9200002020102010201020000000000000000EA +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000000000000C7 +:10D9600000000000000000000202020202020202A7 +:10D97000020101010101010200000000000000009D +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000000000077 +:10D9B000000000000000000002020202000000005F +:10D9C000000000000000000002020202010101014B +:10D9D000010101010101010100000000000000003F +:10D9E0000000000000000000000000000000000037 +:10D9F0000000000000000000000000000000000027 +:10DA00000000000000000000000000000000000016 +:10DA100000000000000000000202020202020202F6 +:10DA200002020202020201020000000000000000E7 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000000000000C6 +:10DA600000000000000000000202020202020202A6 +:10DA70000202020101020202000000000000000098 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000000000076 +:10DAB000000000000000000002020202000000005E +:10DAC000000000000000000002020101010101014C +:10DAD000010101010101010100000000000000003E +:10DAE0000000000000000000000000000000000036 +:10DAF0000000000000000000000000000000000026 +:10DB00000000000000000000000000000000000015 +:10DB100000000000000000000202020202020202F5 +:10DB200002020202020201020000000000000000E6 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000000000000C5 +:10DB600000000000000000000202020202020202A5 +:10DB70000202020202020202000000000000000095 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000000000075 +:10DBB0000000000000000000020202020202000059 +:10DBC000000000000000000002020101010101014B +:10DBD000010101010101010100000000000000003D +:10DBE0000000000000000000000000000000000035 +:10DBF0000000000000000000000000000000000025 +:10DC00000000000000000000000000000000000014 +:10DC100000000000000000000202020202020202F4 +:10DC200002020202020201020000000000000000E5 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000000000000C4 +:10DC600000000000000000000202020202020202A4 +:10DC70000202020202020202000000000000000094 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000000000074 +:10DCB0000000000000000000020202020202000058 +:10DCC000000000000000000002010101010101014B +:10DCD000010101010101010100000000000000003C +:10DCE0000000000000000000000000000000000034 +:10DCF0000000000000000000000000000000000024 +:10DD00000000000000000000000000000000000013 +:10DD100000000000000000000202020202020202F3 +:10DD200002020202020202020000000000000000E3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000000000000000000C3 +:10DD600000000000000000000202020202020202A3 +:10DD70000202020202020202000000000000000093 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000000000073 +:10DDB0000000000000000000020202020202000057 +:10DDC000000000000000000002010101010101014A +:10DDD000010101010101010100000000000000003B +:10DDE0000000000000000000000000000000000033 +:10DDF0000000000000000000000000000000000023 +:10DE00000000000000000000000000000000000012 +:10DE100000000000000000000202020202020202F2 +:10DE200002020202020202020000000000000000E2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000000000000000000C2 +:10DE600000000000000000000202020202020202A2 +:10DE70000202020202020202000000000000000092 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA0000000000000000000000000000000000072 +:10DEB0000000000000000000020202020202020252 +:10DEC0000000000000000002020101010101010147 +:10DED000010101010101010100000000000000003A +:10DEE0000000000000000000000000000000000032 +:10DEF0000000000000000000000000000000000022 +:10DF00000000000000000000000000000000000011 +:10DF100000000000000000000202020202020202F1 +:10DF200002020202020202020000000000000000E1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000000000000000000C1 +:10DF600000000000000000000202020202020202A1 +:10DF70000202020202020202000000000000000091 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000000000000000000071 +:10DFB0000000000000000000020202020202020251 +:10DFC0000000000000000002010101010101010147 +:10DFD0000101010101010101000000000000000039 +:10DFE0000000000000000000000000000000000031 +:10DFF0000000000000000000000000000000000021 +:10E000000000000000000000000000000000000010 +:10E0100000000000000000000202020202020202F0 +:10E0200002020202020202020000000000000000E0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000000000000000000C0 +:10E0600000000000000000000202020202020202A0 +:10E070000202020202020202000000000000000090 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000000000000000000070 +:10E0B0000000000000000000020202020202020250 +:10E0C0000000000002000002010101010101010144 +:10E0D0000101010101010101000000000000000038 +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E10000000000000000000000000000000000000F +:10E1100000000000000000000202020202020202EF +:10E1200000020202020202020000000000000000E1 +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000000000000000000BF +:10E16000000000000000000002020202020202029F +:10E17000020202020202020200000000000000008F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A000000000000000000000000000000000006F +:10E1B000000000000000000002020202020202024F +:10E1C000020000000202020201010101010101013D +:10E1D0000101010101010101000000000000000037 +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E20000000000000000000000000000000000000E +:10E2100000000000000000000202020202020202EE +:10E2200000020202020202020000000000000000E0 +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000000000000000000BE +:10E26000000000000000000002020202020202029E +:10E27000020202020202020200000000000000008E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000000000000000000006E +:10E2B000000000000000000002020202020202024E +:10E2C0000202020002020202010101010101010138 +:10E2D0000101010101010101000000000000000036 +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E30000000000000000000000000000000000000D +:10E3100000000000000000000202020201010101F1 +:10E3200001010101020202020000000000000000E1 +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000000000000000000BD +:10E36000000000000000000002020202020202029D +:10E37000020202020202020200000000000000008D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000000000000000000006D +:10E3B000000000000000000002020202020202024D +:10E3C0000202020202020202010101010101010135 +:10E3D0000101010101010101000000000000000035 +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E40000000000000000000000000000000000000C +:10E4100000000000000000000201010101010101F3 +:10E4200001010101010102020000000000000000E2 +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000000000000000000BC +:10E46000000000000000000002020202020202029C +:10E47000020202020202020200000000000000008C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000000000000000000006C +:10E4B000000000000000000002020202020202024C +:10E4C0000202020202020202010101010101010134 +:10E4D0000101010101010101000000000000000034 +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E50000000000000000000000000000000000000B +:10E5100000000000000000000101010101010101F3 +:10E5200001010101010101010000000000000000E3 +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000000000000000000BB +:10E56000000000000000000002020202020202029B +:10E57000020202020202020200000000000000008B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000000000000000000006B +:10E5B000000000000000000002020202020202024B +:10E5C0000202020202020202010101010101010133 +:10E5D0000101010101010101000000000000000033 +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E60000000000000000000000000000000000000A +:10E6100000000000000000000101010101010101F2 +:10E6200001010101010101010000000000000000E2 +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000000000000000000BA +:10E66000000000000000000002020202020202029A +:10E67000000202020202020200000000000000008C +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000000000000000000006A +:10E6B000000000000000000002020202020202024A +:10E6C0000202020202020202010101010101010132 +:10E6D0000101010101010101000000000000000032 +:10E6E000000000000000000000000000000000002A +:10E6F000000000000000000000000000000000001A +:10E700000000000000000000000000000000000009 +:10E7100000000000000000000101010101010101F1 +:10E7200001010101010101010000000000000000E1 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000000000000000000B9 +:10E7600000000000000000000202000000000000A5 +:10E770000000000002020202000000000000000091 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A0000000000000000000000000000000000069 +:10E7B0000000000000000000020202020202020249 +:10E7C0000202020202020202010101010101010131 +:10E7D0000101010101010101000000000000000031 +:10E7E0000000000000000000000000000000000029 +:10E7F0000000000000000000000000000000000019 +:10E800000000000000000000000000000000000008 +:10E8100000000000000000000101010101010101F0 +:10E8200001010101010101010000000000000000E0 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000000000000000000B8 +:10E8600000000000000000000200000000000000A6 +:10E870000000000002020202000000000000000090 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000000000000000000068 +:10E8B0000000000000000000020202020202020248 +:10E8C0000202020202020202010101010101010130 +:10E8D0000101010101010101000000000000000030 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000000000000000000018 +:10E900000000000000000000000000000000000007 +:10E9100000000000000000000101010101010101EF +:10E9200001010101010101010000000000000000DF +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000000000000000000B7 +:10E96000000000000000000001010101010101019F +:10E97000010101010101010100000000000000008F +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000020202020202020247 +:10E9C000020202020202020201010101010101012F +:10E9D000010101010101010100000000000000002F +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000000000000000000017 +:10EA00000000000000000000000000000000000006 +:10EA100000000000000000000101010101010101EE +:10EA200001010101010101010000000000000000DE +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA6000000000000000000001010101010101019E +:10EA7000010101010101010100000000000000008E +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000020202020202020246 +:10EAC000020202020202020201010101010101012E +:10EAD000010101010101010100000000000000002E +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000000000000000000016 +:10EB00000000000000000000000000000000000005 +:10EB100000000000000000000101010101010101ED +:10EB200001010101010101010000000000000000DD +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB6000000000000000000001010101010101019D +:10EB7000010101010101010100000000000000008D +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC000000000000000000001010101010101013D +:10EBD000010101010101010100000000000000002D +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000000000000000000015 +:10EC00000000000000000000000000000000000004 +:10EC100000000000000000000101010101010101EC +:10EC200001010101010101010000000000000000DC +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC6000000000000000000001010101010101019C +:10EC7000010101010101010100000000000000008C +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC000000000000000000001010101010101013C +:10ECD000010101010101010100000000000000002C +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000000000000000000014 +:10ED00000000000000000000000000000000000003 +:10ED100000000000000000000101010101010101EB +:10ED200001010101010101010000000000000000DB +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED6000000000000000000001010101010101019B +:10ED7000010101010101010100000000000000008B +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC000000000000000000001010101010101013B +:10EDD000010101010101010100000000000000002B +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000000000000000000013 +:10EE00000000000000000000000000000000000002 +:10EE100000000000000000000101010101010101EA +:10EE200001010101010101010000000000000000DA +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000000000000000000B2 +:10EE6000000000000000000001010101010101019A +:10EE7000010101010101010100000000000000008A +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC000000000000000000001010101010101013A +:10EED000010101010101010100000000000000002A +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF00000000000000000000000000000000000001 +:10EF100000000000000000000202020202020202E1 +:10EF200002020202020202020000000000000000D1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000000000000000000B1 +:10EF60000000000000000000020202020202020291 +:10EF70000202020202020202000000000000000081 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F000000000000000000000000000000000000000 +:10F0100000000000000000000000000000000000F0 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000000000000000000B0 +:10F0600000000000000000000000000000000000A0 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000000000000000000060 +:10F0B0000000000000000000000000000000000050 +:10F0C0000000000000000000290000000000000017 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000000000000000000FF +:10F1100000000000000000000000000000000000EF +:10F1200001000000000000000000000000000000DE +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000000000000000000AF +:10F16000000000000000000000000000000000009F +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A000000000000000000000000000000000005F +:10F1B000000000000000000000000000000000004F +:10F1C000000000000000000000000000000000003F +:10F1D0000100010200020002020200000000010121 +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000000000000000000FE +:10F2100000000000000000000000000000000000EE +:10F2200001000000000000000000000000000000DD +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F2500000000000000000000000000000000000AE +:10F26000000000000000000000000000000000009E +:10F27000010000000000000000000000000001018B +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000000000000000000005E +:10F2B000000000000000000000000000000000004E +:10F2C0000001000002020000000000020202020130 +:10F2D0000101010202020202020202000000010119 +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200001000000000000000000000000000000DC +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000010000000000000000000000000001018A +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000101010202000000000002020201012E +:10F3D0000201020202020202020202000200010114 +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000000000000000000000FC +:10F4100000000000000000000000000000000000EC +:10F4200001000000000000000000000000000000DB +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F470000100000000000000000000000000010189 +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000101010101000000000201010201012F +:10F4D0000202020202020202020202000200010112 +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000000000000000000000000000000FB +:10F5100000000000000000000000000000000000EB +:10F5200001000000000100000000000000000000D9 +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F56000000000000000000000000000000000009B +:10F570000100000000000000000000000000010188 +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000001010101000000020101010101012F +:10F5D000020202020202020202020202020001010F +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000000000000000000000000000000FA +:10F6100000000000000000000000000000000000EA +:10F6200001000000000100000000000000000000D8 +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F66000000000000000000000000000000000009A +:10F670000100000000010000000000010000010185 +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000001010101000000020101010101012E +:10F6D000020202020202020202020202020001010E +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000000000000000000000000000000000F9 +:10F7100000000000000000000000000000000000E9 +:10F7200002000001000100000000000000000101D3 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000000000000000000000000099 +:10F770000101000000010000000001010000010182 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C000000000010101000000010101010101012F +:10F7D000020202020202020202020202020101010C +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000000000000000000000000000000000F8 +:10F8100000000000000000000000000000000000E8 +:10F8200002000001010100000000000000000101D1 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000000000000000000000000098 +:10F870000101000000010000000001010001010180 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C000000000000101020002010101010101012B +:10F8D000020202020202020202020202020102010A +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000000000000000000000000000000000F7 +:10F9100000000000000000000000000000000000E7 +:10F9200002000001010100000000000000000101D0 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000000000000000000000000097 +:10F97000020100000001000000000101000101017E +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000001010102020101010101010129 +:10F9D0000202020202020202020202020202020108 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000000000000000000000000000000000000F6 +:10FA100000000000000000000000000000000000E6 +:10FA200002010001010101000000000000000101CD +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000000000000000000000000000000096 +:10FA7000020100000001000000010101010101017B +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC0000100000001010102010101010101010128 +:10FAD0000202020202020202020101020202020109 +:10FAE0000000000000000000000000000000000016 +:10FAF0000000000000000000000000000000000006 +:10FB000000000000000000000000000000000000F5 +:10FB100000000000000000000000000000000000E5 +:10FB200002010001010101010000000000000101CB +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB60000000000000000000000000000000000095 +:10FB70000201000001010100010101010101010177 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000055 +:10FBB0000000000000000000000000000000000045 +:10FBC000010000000000010101010101010101012A +:10FBD000020202020202020201010102010202000B +:10FBE0000000000000000000000000000000000015 +:10FBF0000000000000000000000000000000000005 +:10FC000000000000000000000000000000000000F4 +:10FC100000000000000000000000000000000000E4 +:10FC200002010001010101010000000000000101CA +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC60000000000000000000000000000000000094 +:10FC70000201010001010101010101010101010174 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000200000000000101010101010101010128 +:10FCD000020202020202020101010101010202000C +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000004 +:10FD000000000000000000000000000000000000F3 +:10FD100000000000000000000000000000000000E3 +:10FD200002020102010201010000000000000101C5 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000000000000000000000000000000000093 +:10FD70000202010001010101010101010101010172 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000000000000000000000000043 +:10FDC000020000000000000101010001010101002A +:10FDD000020202020201010101010101010202000D +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000000000000000000000000000000F2 +:10FE100000000000000000000000000000000000E2 +:10FE200002020102020201010100000000000101C2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000000000000000000000000000000000092 +:10FE70000202010001010101010101010101010171 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB0000000000000000000000000000000000042 +:10FEC000020200000000000101000000000101002A +:10FED000020202010101010101010101010102000F +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000000000000000000000000000000F1 +:10FF100000000000000000000000000000000000E1 +:10FF200002020102020201010101000000010101BF +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000000000000000000000000000000000091 +:10FF7000020201000102010101010101010101016F +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB0000000000000000000000000000000000041 +:10FFC000020200000000000000000000000101002B +:10FFD000020202010101010101010101010101000F +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:02000002C0003C +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200002020202020202010101010000010101BB +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:10007000020201010102010101010101010101016D +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000202020000000000000000000001000029 +:1000D000020202010101010101010101010101000E +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200002020202020202020101010000010101B9 +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000020202010202010101010101010101016A +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C0000202020200000000000000000001000026 +:1001D000020201010101010101010101010101000E +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000000000000000000000000000000000000EE +:1002100000000000000000000000000000000000DE +:1002200002020202020202020101010000010101B8 +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:10026000000000000000000000000000000000008E +:100270000202020102020201010102020101010166 +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B000000000000000000000000000000000003E +:1002C0000202020200000000000000000000000026 +:1002D000020201010101010101010101010101000D +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000000000000000000000000000000000000ED +:1003100000000000000000000000000000000000DD +:1003200002020202020202020201010102010101B3 +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:10036000000000000000000000000000000000008D +:100370000202020102020202020202020101020260 +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C0000202020200000000000000000000000025 +:1003D000020101010101010101010101010101000D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200002020202020202020202010101010101B2 +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000020202020202020202020202020102025D +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C0000202020202020000000000000000000020 +:1004D000010101010101010101010101010101000D +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200002020202020202020202020101010202AE +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000020202020202020202020202020202025B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000020202020202000000000000000000001F +:1005D000010101010101010101000001010101000E +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200002020202020202020202020101010202AD +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000020202020202020202020202020202025A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000020202020202020000000200000000001A +:1006D000010101010101010100000001010101000E +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200002020202020202020202020101010202AC +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000202020202020202020202020202020259 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000202020202020200000202020200000211 +:1007D0000101010101010100000000000001010010 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000000000000000000000000000000000000E8 +:1008100000000000000000000000000000000000D8 +:1008200002020202020202020202020201020202A9 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000000000000000000000000000000000088 +:100870000202020202020202020202020202020258 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000000000000000000000000000000000038 +:1008C000020202020202020202020202020000020C +:1008D0000101010000000000000000000000010014 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000000000000000000000000000000000000E7 +:1009100000000000000000000000000000000000D7 +:1009200002020202020202020202020202020202A7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000000000000000000000000000000000087 +:100970000202020202020202020202020202020257 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000000000000000000000000000000000037 +:1009C0000202020202020202020202020200020209 +:1009D0000101010000000000000000000000000014 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000000000000000000000000000000000000E6 +:100A100000000000000000000000000000000000D6 +:100A200002020202020202020202020202020202A6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000000000000000000000000000000000086 +:100A70000202020202020202020202020202020256 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000000000000000000000000000000000036 +:100AC0000202020202020202020202020202020206 +:100AD0000101000000000000000000000000000014 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000000000000000000000000000000000000E5 +:100B100000000000000000000000000000000000D5 +:100B200002020202020202020202020202020202A5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000000000000000000000000000000000085 +:100B70000202020202020202020202020202020255 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000000000000000000000000000000000035 +:100BC0000202020202020202020202020202020205 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C000000000000000000000000000000000000E4 +:100C100000000000000000000000000000000000D4 +:100C200002020202020202020202020202020202A4 +:100C300000000000000000000000000000000000B4 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000000000000000000000000000000000084 +:100C70000202020202020202020202020202020254 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000000000000000000000000000000000034 +:100CC0000202020202020202020202020202020204 +:100CD000000000000000000101010101010000000E +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000000000000000000000F4 +:100D000000000000000000000000000000000000E3 +:100D100000000000000000000000000000000000D3 +:100D200002020202020202020202020202020202A3 +:100D300000000000000000000000000000000000B3 +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000000000000000000000000000000000083 +:100D70000202020202020202020202020202020253 +:100D80000000000000000000000000000000000063 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000000000000000000000000000000000033 +:100DC0000202020202020202020202020202020203 +:100DD0000000000101010101010101010101000008 +:100DE0000000000000000000000000000000000003 +:100DF00000000000000000000000000000000000F3 +:100E000000000000000000000000000000000000E2 +:100E100000000000000000000000000000000000D2 +:100E200002020201010101010101010202020202AA +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000000000000000000000000000000000082 +:100E70000202020202020202020202020202020252 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB0000000000000000000000000000000000032 +:100EC0000202020202020202020202020202020202 +:100ED0000000000101010101010101010101010105 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000000000000000000000000000000E1 +:100F100000000000000000000000000000000000D1 +:100F200001010101010101010101010101020202AE +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000000000000000000000000000000000081 +:100F70000202020202020202020202020202020251 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB0000000000000000000000000000000000031 +:100FC0000202020202020202020202020202020201 +:100FD0000000010101010101010101010101010103 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000000000000000000000000000000E0 +:1010100000000000000000000000000000000000D0 +:1010200001010101010101010101010101010101B0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000000000000000000000000000000000080 +:101070000202020202020202020202020202020250 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000000000000000000000000000000000030 +:1010C0000202020202020202020202020202020200 +:1010D0000101010101010101010101010101010100 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000000000000000000000000000000DF +:1011100000000000000000000000000000000000CF +:1011200001010101010101010101010101010101AF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:101170000202020201010101010101010102020258 +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C00002020202020202020202020202020202FF +:1011D00001010101010101010101010101010101FF +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:1012100000000000000000000000000000000000CE +:1012200001010101010101010101010101010101AE +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000020202020202020202020202020202024E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C0000000000002020000000000020202020012 +:1012D00001010101010101010101010101010101FE +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000000000000000000DD +:1013100000000000000000000000000000000000CD +:1013200001010101010101010101010101010101AD +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000000002D +:1013C0000000000002000000000000000002020017 +:1013D00001010101010101010101010101010101FD +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000000000000000000DC +:1014100000000000000000000000000000000000CC +:1014200001010101010101010101010101010101AC +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000010101010101010101010101010101015C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000000000002C +:1014C0000000000000000000000000000002020018 +:1014D00001010101010101010101010101010101FC +:1014E00000000000000000000000000000000000FC +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000000000000000000DB +:1015100000000000000000000000000000000000CB +:1015200001010101010101010101010101010101AB +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000010101010101010101010101010101015B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B000000000000000000000000000000000002B +:1015C0000000000000000000000000000002000019 +:1015D00001010101010101010101010101010101FB +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000000000000000000DA +:1016100000000000000000000000000000000000CA +:1016200001010101010101010101010101010101AA +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000010101010101010101010101010101015A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B000000000000000000000000000000000002A +:1016C000000000000000000000000000000000001A +:1016D00001010101010101010101010101010101FA +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000000000000000000D9 +:1017100000000000000000000000000000000000C9 +:1017200001010101010101010101010101010101A9 +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000101010101010101010101010101010159 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000000000029 +:1017C0000000000000000000000000000000000019 +:1017D00001010101010101010101010101010101F9 +:1017E00000000000000000000000000000000000F9 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000000000000000000D8 +:1018100000000000000000000000000000000000C8 +:101820000202020202020202020202020202020298 +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000000000000000000000000000068 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000000000028 +:1018C0000000000000000000000000000000000018 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000000000000000000000F8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000000000000000000D7 +:1019100000000000000000000000000000000000C7 +:1019200000000000000000000000000000000000B7 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000000000000000000000000000067 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000000000027 +:1019C0000000000000000000000000000000000017 +:1019D00026000000000000000000000000000000E1 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000000000000000000D6 +:101A100000000000000000000000000000000000C6 +:101A200000000000000000000000010000000000B5 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000000000000000000000000000066 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000000000026 +:101AC0000000000000000000000000000000000016 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000000000000000000D5 +:101B100000000000000000000000000000000000C5 +:101B200000000000000000000000010000000000B4 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000000000000000000000000000065 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000000000025 +:101BC0000000000000000000000000000000000015 +:101BD0000000000000000001000000020000000002 +:101BE00000020000000000010000000000000000F2 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000000000000000D4 +:101C100000000000000000000000000000000000C4 +:101C200000000000000000000000010000000000B3 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000000000000000000074 +:101C70000000000000000000000000000000000064 +:101C80000000000000000000000000000000000054 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000000000000000000000034 +:101CB0000000000000000000000000000000000024 +:101CC000000000000000000000000101020002000E +:101CD00000000000000202010102000200000000FA +:101CE00000020000000001010000000000000000F0 +:101CF00000000000000000000000000000000000E4 +:101D000000000000000000000000000000000000D3 +:101D100000000000000000000000000000000000C3 +:101D200000000000000000000001010000000000B1 +:101D300000000000010000000000000000000000A2 +:101D40000000000000000000000000000000000093 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000000000000000000073 +:101D70000000000000000000000000000000000063 +:101D80000000000000000000000000000000000053 +:101D90000000000000000000000000000000000043 +:101DA0000000000000000000000000000000000033 +:101DB0000000000000000000000000000000000023 +:101DC000000000000000000000000101010102020B +:101DD00000000000000101010102010200000002F8 +:101DE00002020002000001010000000000000000EB +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000000000000000D2 +:101E100000000000000000000000000000000000C2 +:101E200000000000000000000001010001000000AF +:101E3000020001000100010100000000000000009C +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E60000000000000000000000000000000000072 +:101E70000000000000000000000000000000000062 +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000000000000000000022 +:101EC000000000000000000000010101010101020A +:101ED00000020000020101010102010200000002F3 +:101EE00002020002020001010000000000000000E8 +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000000000000000000D1 +:101F100000000000000000000000000000000000C1 +:101F200000000000000000000001010001000100AD +:101F3000010101000100010100000000000000009B +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F60000000000000000000000000000000000071 +:101F70000000000000000000000000000000000061 +:101F80000000000000000000000000000000000051 +:101F90000000000000000000000000000000000041 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000000000000000000021 +:101FC000000000000000000000010101010101010A +:101FD00002020000010101010202010200020002EE +:101FE00002020002020001010000000000000000E7 +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000000000000000000D0 +:1020100000000000000000000000000000000000C0 +:1020200000000000000000000001010101010101A9 +:102030000101010101000101000000000000000099 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000000000000000000070 +:102070000000000000000000000000000000000060 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000000000000000000020 +:1020C0000000000000000000000101010101010109 +:1020D00002010000010101010202020200020202EB +:1020E00002020002020001010000000000000000E6 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000000000000000000CF +:1021100000000000000000000000000000000000BF +:1021200000000000000000000001010101010101A8 +:102130000101010101010101000000000000000097 +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:10216000000000000000000000000000000000006F +:10217000000000000000000000000100000000005E +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B000000000000000000000000000000000001F +:1021C0000000000000000000000001010101010109 +:1021D00001010100010101010202020200020202EA +:1021E00002020002020001010000000000000000E5 +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000000000000000000CE +:1022100000000000000000000000000000000000BE +:1022200000000000000000000001010101010101A7 +:102230000101010101010101000000000000000096 +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:10226000000000000000000000000000000000006E +:10227000000000000000000000010100000000005C +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000000000000000000001E +:1022C0000000000000000000000001010101010108 +:1022D00001010100010101010202020200020202E9 +:1022E00002020002020101010000000000000000E3 +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000000000000000000CD +:1023100000000000000000000000000000000000BD +:1023200000000000000000000002010101010101A5 +:102330000101010101010101000000000000000095 +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000000000000000000006D +:10237000000000000000000000010100000000005B +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000000000000000000001D +:1023C0000000000000000000000000000101010109 +:1023D00001010100010101010202020202020202E6 +:1023E00002010202020101010000000000000000E1 +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000000000000000000CC +:1024100000000000000000000000000000000000BC +:1024200000000000000000000102020101010101A2 +:102430000101010101010101000000000000000094 +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000000000000000000006C +:10247000000000000000000000010100000000005A +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000000000000000000001C +:1024C0000000000000000000000000000100010109 +:1024D00001010100010101010202020202020202E5 +:1024E00002010201010101000000000000000000E3 +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000000000000000000CB +:1025100000000000000000000000000000000000BB +:1025200000000000000000000102020101010101A1 +:102530000101010101010101000000000000000093 +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000000000000000000006B +:102570000000000000000000000101000000000059 +:102580000000000000000101000000000000000049 +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000000000000000000001B +:1025C0000000000000000000000000000000010109 +:1025D00001010102010101010202020202020201E3 +:1025E00001010201010101000000000000000000E3 +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000000000000000000CA +:1026100000000000000000000000000000000000BA +:10262000000000000000000002020201010101019F +:102630000101010101010101000000000000000092 +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000000000000000000006A +:102670000000000000000000000201000000000057 +:102680000000000000000101000000000000000048 +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B000000000000000000000000000000000001A +:1026C0000000000000000000010000000000010107 +:1026D00001010101010101000202020102020201E5 +:1026E00001010201010201000000000000000000E1 +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000000000000000000C9 +:1027100000000000000000000000000000000000B9 +:10272000000000000000000002020202020101019C +:102730000101010101010101000000000000000091 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000000000000000000069 +:102770000000000000000000010201000000000055 +:102780000000000000000101000000000000000047 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B0000000000000000000000000000000000019 +:1027C0000000000000000000010000000000000008 +:1027D00001010101010101000202020102010101E6 +:1027E00001010101010201000000000000000000E1 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000000000000000000C8 +:1028100000000000000000000000000000000000B8 +:102820000000000000000000020202020202020199 +:102830000101010101010101000000000000000090 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000020202000000000052 +:102880000000000001010101000000000000000044 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000000000018 +:1028C0000000000000000000020000000000000006 +:1028D00000000001000001000202020102010101EA +:1028E00001010101010202000000000000000000DF +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000000000000000000C7 +:1029100000000000000000000000000000000000B7 +:102920000000000000000000020202020202020297 +:10293000020202010201010100000000000000008B +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:10297000000000000000000002020201010000004F +:102980000000000001010101000000000000000043 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000020000000000000005 +:1029D00000000001000000000201020101010101EC +:1029E00001010101010102000000000000000000DF +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000000000000000000C6 +:102A100000000000000000000000000000000000B6 +:102A20000000000000000000020202020202020296 +:102A30000202020202010101000000000000000089 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A60000000000000000000000000000000000066 +:102A7000000000000000000002020201010000004E +:102A80000000000001010101000000000000000042 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000020200000000000002 +:102AD00000000001000000000201010101010101EC +:102AE00001010101010102000000000000000000DE +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000000000000000000C5 +:102B100000000000000000000000000000000000B5 +:102B20000000000000000000020202020202020295 +:102B30000202020202010101000000000000000088 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B60000000000000000000000000000000000065 +:102B7000000000000000000002020201010100014B +:102B8000020001020101010100000000000000003C +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000020200000000000001 +:102BD00000000000000000000201010101010101EC +:102BE00001010101010102000000000000000000DD +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000000000000000000C4 +:102C100000000000000000000000000000000000B4 +:102C20000000000000000000020202020202020294 +:102C30000202020202010202000000000000000085 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C60000000000000000000000000000000000064 +:102C70000000000000000000020202020101010148 +:102C8000010101010101010100000000000000003C +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB0000000000000000000000000000000000014 +:102CC00000000000000000000202020200000000FC +:102CD00000000000000000000201010101010101EB +:102CE00001010101010102000000000000000000DC +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000000000000000000C3 +:102D100000000000000000000000000000000000B3 +:102D20000000000000000000020202020202020293 +:102D30000202020202020202000000000000000083 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D60000000000000000000000000000000000063 +:102D70000000000000000000020202020201010146 +:102D8000010101010101010100000000000000003B +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB0000000000000000000000000000000000013 +:102DC00000000000000000000202020200020000F9 +:102DD00000000000000000000201010101010101EA +:102DE00001000101010102000000000000000000DC +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E20000000000000000000020202020202020292 +:102E30000202020202020202000000000000000082 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000020202020202010144 +:102E8000010101010101010100000000000000003A +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000000000000000000012 +:102EC00000000000000000000202020202020000F6 +:102ED00000000000000000000201010101010101E9 +:102EE00001000100000102000000000000000000DD +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F20000000000000000000020202020202020291 +:102F30000202020202020202000000000000000081 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000020202020202020241 +:102F80000101010102010101000000000000000038 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC00000000000000000000202020202020000F5 +:102FD00000000000000000000201010001010100EA +:102FE00000000100000102000000000000000000DD +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000000000000000000000B0 +:103020000000000000000000020202020202020290 +:103030000202020202020202000000000000000080 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000020202020202020240 +:103080000202020102010202000000000000000032 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C00000000000000000000202020202020202F0 +:1030D00000000000000000020101010001000000EA +:1030E00000000000000101000000000000000000DE +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:10312000000000000000000002020202020202028F +:10313000020202020202020200000000000000007F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000002020202020202023F +:10318000020202020202020200000000000000002F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000202020202020202EF +:1031D00002020200020200020100000000000000E2 +:1031E00000000000000001000000000000000000DE +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000000000000000000000000000000000AE +:10322000000000000000000002020202020202028E +:10323000020202020202020200000000000000007E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000002020202020202023E +:10328000020202020202020200000000000000002E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000202020202020202EE +:1032D00002020200020202020100000000000000DF +:1032E00000000000000001000000000000000000DD +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000000000000000000000000000000000AD +:10332000000000000000000002020202020202028D +:10333000020202020202020200000000000000007D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000002020202020202023D +:10338000020202020202020200000000000000002D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000202020202020202ED +:1033D00002020200020202020100000000000000DE +:1033E00000010001010001000000000000000000D9 +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000000000000000000000000000000000AC +:10342000000000000000000002020202020202028C +:10343000020202020202020200000000000000007C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000002020202020202023C +:10348000020202020202020200000000000000002C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000202020202020202EC +:1034D00002020202020202020100000100000001D9 +:1034E00001010001010001000000000000000000D7 +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000000000000000000000000000000000AB +:10352000000000000000000002020202020202028B +:10353000020202020202020200000000000000007B +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000002020202020202023B +:10358000020202020202020200000000000000002B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000202020202020202EB +:1035D00002020202020202020100000100010101D6 +:1035E00001010101010001010000000000000000D4 +:1035F00000000000000000000000000000000000CB +:1036000000000000000000000000000000000000BA +:1036100000000000000000000000000000000000AA +:10362000000000000000000002020202020202028A +:10363000020202020202020200000000000000007A +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000002020202020202023A +:10368000020202020202020200000000000000002A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000202020202020202EA +:1036D00002020202020202020101010101010101D2 +:1036E00001010101010101010000000000000000D2 +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000000000000000000000000000000000A9 +:103720000000000000000000020101010101010190 +:10373000010101010102020200000000000000007E +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000020202020202020239 +:103780000202020202020202000000000000000029 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000202020202020202E9 +:1037D00002020202020202020101010101010101D1 +:1037E00001010101010101010000000000000000D1 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000000000000000000000000000000000A8 +:103820000000000000000000010101010101010190 +:103830000101010101010101000000000000000080 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:10387000000000000000000002010101010101013F +:10388000010101010102020200000000000000002D +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000202020202020202E8 +:1038D00002020202020202020101010101010101D0 +:1038E00001010101010101010000000000000000D0 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000000000000000000000000000000000A7 +:10392000000000000000000001010101010101018F +:10393000010101010101010100000000000000007F +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000020202020202020237 +:103980000202020202020202000000000000000027 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000202020202020202E7 +:1039D00002020202020202020101010101010101CF +:1039E00001010101010101010000000000000000CF +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000000000000000000000000000000000A6 +:103A2000000000000000000001010101010101018E +:103A3000010101010101010100000000000000007E +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A7000000000000000000001010101010101013E +:103A8000010101010101010100000000000000002E +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000202020202020202E6 +:103AD00002020202020202020101010101010101CE +:103AE00001010101010101010000000000000000CE +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000000000000000000000000000000A5 +:103B2000000000000000000001010101010101018D +:103B3000010101010101010100000000000000007D +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B7000000000000000000001010101010101013D +:103B8000010101010101010100000000000000002D +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000000000202020202020202E5 +:103BD00002020202020202000101010101010101CF +:103BE00001010101010101010000000000000000CD +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C100000000000000000000000000000000000A4 +:103C2000000000000000000001010101010101018C +:103C3000010101010101010100000000000000007C +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C7000000000000000000001010101010101013C +:103C8000010101010101010100000000000000002C +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000000000000000020202000200EC +:103CD00000000000000002000101010101010101DA +:103CE00001010101010101010000000000000000CC +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D100000000000000000000000000000000000A3 +:103D2000000000000000000001010101010101018B +:103D3000010101010101010100000000000000007B +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D7000000000000000000001010101010101013B +:103D8000010101010101010100000000000000002B +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000000000000000000000000200F1 +:103DD00000000000000000000101010101010101DB +:103DE00001010101010101010000000000000000CB +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E100000000000000000000000000000000000A2 +:103E20000000000000000000000000000000000092 +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000000000000000000020202020202020232 +:103E80000202020202020202000000000000000022 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000000000000000000000000000F2 +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F100000000000000000000000000000000000A1 +:103F20000000000000000000000000000000000091 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F70000000000000000000000000000000000041 +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00000000000000000000000000000000000F1 +:103FD00000000000000000001E00000000000000C3 +:103FE00001010000000002020200000202000101C3 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:1040100000000000000000000000000000000000A0 +:104020000000000000000000000000000000000090 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000000000000000000000000000000000040 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00000000000000000000000000000000000F0 +:1040D00000010101020201020202020202020200C8 +:1040E00001010102020002020202020202000101B9 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000000000000000000000000000000009F +:10412000000000000000000000000000000000008F +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:10417000000000000000000000000000000000003F +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00000000000000000000000000000000000EF +:1041D00000010101010101010201010202020100CD +:1041E00002020202020002020202020202000201B4 +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000000000000000000000000000000009E +:10422000000000000000000000000000000000008E +:10423000000000000000000000000000000000017D +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000000000000000000000000000000000003E +:10428000010000000000000000000000000000002D +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00000000000000000000000000000000000EE +:1042D00000010101010101010101010101010100D0 +:1042E00002020202020002020202020202010201B2 +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:10431000000000000000000000000000000000009D +:10432000000000000000000000000000000000008D +:10433000010000000000000000000000000000017B +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000000000000000000000000000000000003D +:10438000010100000000000000000000000000002B +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00000000000000000000000000000000000ED +:1043D00000010101010101010101010101010100CF +:1043E00002020202020002020202020202010201B1 +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:10441000000000000000000000000000000000009C +:10442000000000000000000000000000000000008C +:10443000010000000000000000000000000000017A +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000000000000000000000000000000000003C +:104480000101000000000000000000000000000129 +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00000000000000000000000000000000000EC +:1044D00000000101010101010101010101010100CF +:1044E00002020202020002020202020202010201B0 +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:10451000000000000000000000000000000000009B +:10452000000000000000000000000000000000008B +:104530000100000000000000000000000000010178 +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000000000000000000000000000000000003B +:104580000201000000000000000000000000000127 +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00000000000000000000000000000000000EB +:1045D00001000001010101010101010101010100CE +:1045E00002020202020202020202020101010201AF +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000000000000000000000000000000000009A +:10462000000000000000000000000000000000008A +:104630000200000000000000000000000000010176 +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:10467000000000000000000000000000000000003A +:104680000201000000000000000000000000000126 +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00001000000010100010101010101010100CF +:1046E00002020202020201010101010101010100B5 +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:104710000000000000000000000000000000000099 +:104720000000000000000000000000000000000089 +:104730000200000000000000000000000000010175 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:104770000000000000000000000000000000000039 +:104780000202000000000000000000000000010123 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00002000000000000010100000101010100D1 +:1047E00002020202020201010101010101010100B4 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000000000000000000000000000000000098 +:104820000000000000000000000000000000000088 +:104830000200000000000000000000000000010174 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000000000000000000000000000000000038 +:104880000202000100000000000001000000010120 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00002000000000000000100000101010100D1 +:1048E00002020201010201010101010101020100B4 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000000000000000000000000000000000097 +:104920000000000000000000000000000000000087 +:104930000201000000000100000000000000010171 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000000000000000000000000000000000037 +:104980000202010100010101010001000100010119 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00002000000000000000000000100010000D3 +:1049E00002020201010201010101010101020100B3 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000000000000000000000000000000000096 +:104A20000000000000000000000000000000000086 +:104A3000020100000000010000000000000101016F +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000000000000000000000000000000000036 +:104A80000202010101010101010001010101010115 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00000000000000000000000000000000000E6 +:104AD00002000000000000000000000000010001D2 +:104AE00002020101010101010101010101020100B4 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000000000000000000000000000000000095 +:104B20000000000000000000000000000000000085 +:104B3000020200000000010000000100000101016C +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000000000000000000000000000000000035 +:104B80000202020201010101010101010101010111 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00000000000000000000000000000000000E5 +:104BD00002000000000000000000000000000001D2 +:104BE00002010101010101010101010101020100B4 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000000000000000000000000000000000094 +:104C20000000000000000000000000000000000084 +:104C30000202010100010100000001000001010168 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000000000000000000000000000000000034 +:104C8000020202020202010102010201010101010C +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00000000000000000000000000000000000E4 +:104CD00002000000000000000000000000000001D1 +:104CE00002010101010101010101010101010100B4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000202020100010100010101000101010262 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000202020202020102020102010201010109 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00002020000000000000000000000000001CE +:104DE00001010101010101010101010101010100B4 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:104E20000000000000000000000000000000000082 +:104E3000020202020102020001010201010102025A +:104E40000000000000000000000000000000000062 +:104E50000000000000000000000000000000000052 +:104E60000000000000000000000000000000000042 +:104E70000000000000000000000000000000000032 +:104E80000202020202020202020102010201010206 +:104E90000000000000000000000000000000000012 +:104EA0000000000000000000000000000000000002 +:104EB00000000000000000000000000000000000F2 +:104EC00000000000000000000000000000000000E2 +:104ED00002020200000000000000000000000001CB +:104EE00001010101010100000000000000010000BB +:104EF00000000000000000000000000000000000B2 +:104F000000000000000000000000000000000000A1 +:104F10000000000000000000000000000000000091 +:104F20000000000000000000000000000000000081 +:104F30000202020202020201020102010101020256 +:104F40000000000000000000000000000000000061 +:104F50000000000000000000000000000000000051 +:104F60000000000000000000000000000000000041 +:104F70000000000000000000000000000000000031 +:104F80000202020202020202020202020201020202 +:104F90000000000000000000000000000000000011 +:104FA0000000000000000000000000000000000001 +:104FB00000000000000000000000000000000000F1 +:104FC00000000000000000000000000000000000E1 +:104FD00002020202000002000000000000000001C6 +:104FE00001010100000100000000000000010000BC +:104FF00000000000000000000000000000000000B1 +:1050000000000000000000000000000000000000A0 +:105010000000000000000000000000000000000090 +:105020000000000000000000000000000000000080 +:105030000202020202020201020202010202020252 +:105040000000000000000000000000000000000060 +:105050000000000000000000000000000000000050 +:105060000000000000000000000000000000000040 +:105070000000000000000000000000000000000030 +:105080000202020202020202020202020202020200 +:105090000000000000000000000000000000000010 +:1050A0000000000000000000000000000000000000 +:1050B00000000000000000000000000000000000F0 +:1050C00000000000000000000000000000000000E0 +:1050D00002020202020202000002020000000001BD +:1050E00001010000000000000000000000010000BD +:1050F00000000000000000000000000000000000B0 +:10510000000000000000000000000000000000009F +:10511000000000000000000000000000000000008F +:10512000000000000000000000000000000000007F +:10513000020202020202020202020202020202024F +:10514000000000000000000000000000000000005F +:10515000000000000000000000000000000000004F +:10516000000000000000000000000000000000003F +:10517000000000000000000000000000000000002F +:1051800002020202020202020202020202020202FF +:10519000000000000000000000000000000000000F +:1051A00000000000000000000000000000000000FF +:1051B00000000000000000000000000000000000EF +:1051C00000000000000000000000000000000000DF +:1051D00002020202020202020002020000000002B9 +:1051E00001000000000000000000000000000000BE +:1051F00000000000000000000000000000000000AF +:10520000000000000000000000000000000000009E +:10521000000000000000000000000000000000008E +:10522000000000000000000000000000000000007E +:10523000020202020202020202020202020202024E +:10524000000000000000000000000000000000005E +:10525000000000000000000000000000000000004E +:10526000000000000000000000000000000000003E +:10527000000000000000000000000000000000002E +:105280000202020202020202010201020102020201 +:10529000000000000000000000000000000000000E +:1052A00000000000000000000000000000000000FE +:1052B00000000000000000000000000000000000EE +:1052C00000000000000000000000000000000000DE +:1052D00002020202020202020202020002000202B2 +:1052E00000000000000000000000000000000000BE +:1052F00000000000000000000000000000000000AE +:10530000000000000000000000000000000000009D +:10531000000000000000000000000000000000008D +:10532000000000000000000000000000000000007D +:10533000020202020202020202020002020202024F +:10534000000000000000000000000000000000005D +:10535000000000000000000000000000000000004D +:10536000000000000000000000000000000000003D +:10537000000000000000000000000000000000002D +:1053800002020202020202020202020202020202FD +:10539000000000000000000000000000000000000D +:1053A00000000000000000000000000000000000FD +:1053B00000000000000000000000000000000000ED +:1053C00000000000000000000000000000000000DD +:1053D00002020202020202020202020202000202AF +:1053E00000000000000001010101010101000100B5 +:1053F00000000000000000000000000000000000AD +:10540000000000000000000000000000000000009C +:10541000000000000000000000000000000000008C +:10542000000000000000000000000000000000007C +:105430000202020202020202000200020002020252 +:10544000000000000000000000000000000000005C +:10545000000000000000000000000000000000004C +:10546000000000000000000000000000000000003C +:10547000000000000000000000000000000000002C +:105480000201020101010201000200020002020207 +:10549000000000000000000000000000000000000C +:1054A00000000000000000000000000000000000FC +:1054B00000000000000000000000000000000000EC +:1054C00000000000000000000000000000000000DC +:1054D00002020202020202020202020202020202AC +:1054E00000000001010001010101010101000101B1 +:1054F00000000000000000000000000000000000AC +:10550000000000000000000000000000000000009B +:10551000000000000000000000000000000000008B +:10552000000000000000000000000000000000007B +:105530000202020202000202000000000002020257 +:10554000000000000000000000000000000000005B +:10555000000000000000000000000000000000004B +:10556000000000000000000000000000000000003B +:10557000000000000000000000000000000000002B +:105580000102010202020202000100010002020205 +:10559000000000000000000000000000000000000B +:1055A00000000000000000000000000000000000FB +:1055B00000000000000000000000000000000000EB +:1055C00000000000000000000000000000000000DB +:1055D00002020202020202020202020202020202AB +:1055E00000000101010101010101010101000101AE +:1055F00000000000000000000000000000000000AB +:10560000000000000000000000000000000000009A +:10561000000000000000000000000000000000008A +:10562000000000000000000000000000000000007A +:10563000010101010101010101010101010101015A +:10564000000000000000000000000000000000005A +:10565000000000000000000000000000000000004A +:10566000000000000000000000000000000000003A +:10567000000000000000000000000000000000002A +:10568000020002000000010000020002000101010E +:10569000000000000000000000000000000000000A +:1056A00000000000000000000000000000000000FA +:1056B00000000000000000000000000000000000EA +:1056C00000000000000000000000000000000000DA +:1056D00002020202020202020202020202020202AA +:1056E00000010101010101010101010101010101AB +:1056F00000000000000000000000000000000000AA +:105700000000000000000000000000000000000099 +:105710000000000000000000000000000000000089 +:105720000000000000000000000000000000000079 +:105730000101010101010101010101010101010159 +:105740000000000000000000000000000000000059 +:105750000000000000000000000000000000000049 +:105760000000000000000000000000000000000039 +:105770000000000000000000000000000000000029 +:105780000000000000000200000000000002020211 +:105790000000000000000000000000000000000009 +:1057A00000000000000000000000000000000000F9 +:1057B00000000000000000000000000000000000E9 +:1057C00000000000000000000000000000000000D9 +:1057D00002020202020202020202020202020202A9 +:1057E00001010101010101010101010101010101A9 +:1057F00000000000000000000000000000000000A9 +:105800000000000000000000000000000000000098 +:105810000000000000000000000000000000000088 +:105820000000000000000000000000000000000078 +:105830000101010101010101010101010101010158 +:105840000000000000000000000000000000000058 +:105850000000000000000000000000000000000048 +:105860000000000000000000000000000000000038 +:105870000000000000000000000000000000000028 +:105880000000000000000000000000000000000018 +:105890000000000000000000000000000000000008 +:1058A00000000000000000000000000000000000F8 +:1058B00000000000000000000000000000000000E8 +:1058C00000000000000000000000000000000000D8 +:1058D00000020202020202020202020202020200AC +:1058E00001010101010101010101010101010101A8 +:1058F00000000000000000000000000000000000A8 +:105900000000000000000000000000000000000097 +:105910000000000000000000000000000000000087 +:105920000000000000000000000000000000000077 +:105930000101010101010101010101010101010157 +:105940000000000000000000000000000000000057 +:105950000000000000000000000000000000000047 +:105960000000000000000000000000000000000037 +:105970000000000000000000000000000000000027 +:105980000101010101010101010101010101010107 +:105990000000000000000000000000000000000007 +:1059A00000000000000000000000000000000000F7 +:1059B00000000000000000000000000000000000E7 +:1059C00000000000000000000000000000000000D7 +:1059D00000020202020202020200000202020200AF +:1059E00001010101010101010101010101010101A7 +:1059F00000000000000000000000000000000000A7 +:105A00000000000000000000000000000000000096 +:105A10000000000000000000000000000000000086 +:105A20000000000000000000000000000000000076 +:105A30000101010101010101010101010101010156 +:105A40000000000000000000000000000000000056 +:105A50000000000000000000000000000000000046 +:105A60000000000000000000000000000000000036 +:105A70000000000000000000000000000000000026 +:105A80000101010101010101010101010101010106 +:105A90000000000000000000000000000000000006 +:105AA00000000000000000000000000000000000F6 +:105AB00000000000000000000000000000000000E6 +:105AC00000000000000000000000000000000000D6 +:105AD00000020202020200020200000200020000B4 +:105AE00001010101010101010101010101010101A6 +:105AF00000000000000000000000000000000000A6 +:105B00000000000000000000000000000000000095 +:105B10000000000000000000000000000000000085 +:105B20000000000000000000000000000000000075 +:105B30000101010101010101010101010101010155 +:105B40000000000000000000000000000000000055 +:105B50000000000000000000000000000000000045 +:105B60000000000000000000000000000000000035 +:105B70000000000000000000000000000000000025 +:105B80000101010101010101010101010101010105 +:105B90000000000000000000000000000000000005 +:105BA00000000000000000000000000000000000F5 +:105BB00000000000000000000000000000000000E5 +:105BC00000000000000000000000000000000000D5 +:105BD00000020202020200020200000200020000B3 +:105BE00001010101010101010101010101010101A5 +:105BF00000000000000000000000000000000000A5 +:105C00000000000000000000000000000000000094 +:105C10000000000000000000000000000000000084 +:105C20000000000000000000000000000000000074 +:105C30000202020202020202020202020202020244 +:105C40000000000000000000000000000000000054 +:105C50000000000000000000000000000000000044 +:105C60000000000000000000000000000000000034 +:105C70000000000000000000000000000000000024 +:105C800002020202020202020202020202020202F4 +:105C90000000000000000000000000000000000004 +:105CA00000000000000000000000000000000000F4 +:105CB00000000000000000000000000000000000E4 +:105CC00000000000000000000000000000000000D4 +:105CD00000000202020000000000000000020000BC +:105CE00000000000000000000000000000000000B4 +:105CF00000000000000000000000000000000000A4 +:105D00000000000000000000000000000000000093 +:105D10000000000000000000000000000000000083 +:105D20000000000000000000000000000000000073 +:105D30000000000000000000000000000000000063 +:105D40000000000000000000000000000000000053 +:105D50000000000000000000000000000000000043 +:105D60000000000000000000000000000000000033 +:105D70000000000000000000000000000000000023 +:105D80000000000000000000000000000000000013 +:105D90000000000000000000000000000000000003 +:105DA00000000000000000000000000000000000F3 +:105DB00000000000000000000000000000000000E3 +:105DC00000000000000000000000000000000000D3 +:105DD00000000000000000000000000000000000C3 +:105DE0001E00000000000000000001010000000093 +:105DF000000100010101010100000000000000009D +:105E00000000000000000000000000000000000092 +:105E10000000000000000000000000000000000082 +:105E20000000000000000000000000000000000072 +:105E30000000000000000000000000000000000161 +:105E40000000000000000001000000000000000051 +:105E50000000000000000000000000000000000042 +:105E60000000000000000000000000000000000032 +:105E70000000000000000000000000000000000022 +:105E80000000000000000000000000000000000012 +:105E90000000000000000000000000000000000002 +:105EA00000000000000000000000000000000000F2 +:105EB00000000000000000000000000000000000E2 +:105EC00000000000000000000000000000000000D2 +:105ED00000000000000000000001010101010101BB +:105EE00001010101010101000101010100000101A5 +:105EF000010100010101010100000000000000009B +:105F00000000000000000000000000000000000091 +:105F10000000000000000000000000000000000081 +:105F20000000000000000000000000000000000071 +:105F3000000000000000000001000000000000015F +:105F4000000101010000000100000000000000004D +:105F50000000000000000000000000000000000041 +:105F60000000000000000000000000000000000031 +:105F70000000000000000000000000000000000021 +:105F80000000000000000000000000000000000011 +:105F90000000000000000000000000000000000001 +:105FA00000000000000000000000000000000000F1 +:105FB00000000000000000000000000000000000E1 +:105FC00000000000000000000000000000000000D1 +:105FD00000000000000000000001010101010101BA +:105FE00001010101010101000201010100010101A2 +:105FF0000101010101010101000000000000000099 +:106000000000000000000000000000000000000090 +:106010000000000000000000000000000000000080 +:106020000000000000000000000000000000000070 +:10603000000000000000000001010000000000015D +:10604000010101010000000100000000000000004B +:106050000000000000000000000000000000000040 +:106060000000000000000000000000000000000030 +:106070000000000000000000000000000000000020 +:106080000000000000000000000000000000000010 +:106090000000000000000000000000000000000000 +:1060A00000000000000000000000000000000000F0 +:1060B00000000000000000000000000000000000E0 +:1060C00000000000000000000000000000000000D0 +:1060D00000000000000000000001010101010101B9 +:1060E00001010101010101000201010200010101A0 +:1060F0000101010101010101000000000000000098 +:10610000000000000000000000000000000000008F +:10611000000000000000000000000000000000007F +:10612000000000000000000000000000000000006F +:10613000000000000000000001010100000000015B +:106140000101010101010101000000000000000047 +:10615000000000000000000000000000000000003F +:10616000000000000000000000000000000000002F +:10617000000000000000000000000000000000001F +:10618000000000000000000000010000000000000E +:1061900000000000000000000000000000000000FF +:1061A00000000000000000000000000000000000EF +:1061B00000000000000000000000000000000000DF +:1061C00000000000000000000000000000000000CF +:1061D00000000000000000000001010101010101B8 +:1061E000010101010101010002010102000101019F +:1061F0000101010101010101000000000000000097 +:10620000000000000000000000000000000000008E +:10621000000000000000000000000000000000007E +:10622000000000000000000000000000000000006E +:106230000000000000000000020101000000000159 +:106240000101010101010101000000000000000046 +:10625000000000000000000000000000000000003E +:10626000000000000000000000000000000000002E +:10627000000000000000000000000000000000001E +:10628000000000000000000000010100000000000C +:1062900000000000000000000000000000000000FE +:1062A00000000000000000000000000000000000EE +:1062B00000000000000000000000000000000000DE +:1062C00000000000000000000000000000000000CE +:1062D00000000000000000000001010101010101B7 +:1062E000010101010101010002020202000101019C +:1062F0000101010101010101000000000000000096 +:10630000000000000000000000000000000000008D +:10631000000000000000000000000000000000007D +:10632000000000000000000000000000000000006D +:106330000000000000000000020101000000000158 +:106340000101010101010101000000000000000045 +:10635000000000000000000000000000000000003D +:10636000000000000000000000000000000000002D +:10637000000000000000000000000000000000001D +:106380000000000000000000010101000000000109 +:1063900000000000000000000000000000000000FD +:1063A00000000000000000000000000000000000ED +:1063B00000000000000000000000000000000000DD +:1063C00000000000000000000000000000000000CD +:1063D00000000000000000000100010101010101B6 +:1063E0000101010101010100020202020201020198 +:1063F0000101010101010101000000000000000095 +:10640000000000000000000000000000000000008C +:10641000000000000000000000000000000000007C +:10642000000000000000000000000000000000006C +:106430000000000000000000020101000000000157 +:106440000101010101010101000000000000000044 +:10645000000000000000000000000000000000003C +:10646000000000000000000000000000000000002C +:10647000000000000000000000000000000000001C +:106480000000000000000000020101000000000107 +:1064900000010100000000000000000000000000FA +:1064A00000000000000000000000000000000000EC +:1064B00000000000000000000000000000000000DC +:1064C00000000000000000000000000000000000CC +:1064D00000000000000000000100010000010101B7 +:1064E0000101010101010100020202020202020196 +:1064F0000101010102010100000000000000000094 +:10650000000000000000000000000000000000008B +:10651000000000000000000000000000000000007B +:10652000000000000000000000000000000000006B +:106530000000000000000000020201000000000155 +:106540000101010101010101000000000000000043 +:10655000000000000000000000000000000000003B +:10656000000000000000000000000000000000002B +:10657000000000000000000000000000000000001B +:106580000000000000000000020201000000000105 +:1065900000010101000000000000000000000000F8 +:1065A00000000000000000000000000000000000EB +:1065B00000000000000000000000000000000000DB +:1065C00000000000000000000000000000000000CB +:1065D00000000000000000000200000000000101B7 +:1065E0000101010101010100020202020202020195 +:1065F0000101010102020100000000000000000092 +:10660000000000000000000000000000000000008A +:10661000000000000000000000000000000000007A +:10662000000000000000000000000000000000006A +:106630000000000000000000020201010000010152 +:106640000101010101010101000000000000000042 +:10665000000000000000000000000000000000003A +:10666000000000000000000000000000000000002A +:10667000000000000000000000000000000000001A +:106680000000000000000000020201010000000103 +:1066900000010101000101000000000000000000F5 +:1066A00000000000000000000000000000000000EA +:1066B00000000000000000000000000000000000DA +:1066C00000000000000000000000000000000000CA +:1066D00000000000000000000200000000000001B7 +:1066E0000101010101010100020202020202020194 +:1066F0000101010102020100000000000000000091 +:106700000000000000000000000000000000000089 +:106710000000000000000000000000000000000079 +:106720000000000000000000000000000000000069 +:106730000000000000000000020202010000010150 +:106740000101010101010101000000000000000041 +:106750000000000000000000000000000000000039 +:106760000000000000000000000000000000000029 +:106770000000000000000000000000000000000019 +:106780000000000000000000020202010000000101 +:1067900001010101000101010000000000000000F2 +:1067A00000000000000000000000000000000000E9 +:1067B00000000000000000000000000000000000D9 +:1067C00000000000000000000000000000000000C9 +:1067D00000000000000000000200000000000001B6 +:1067E0000101010101000000020202020202020195 +:1067F000010101010202020000000000000000008F +:106800000000000000000000000000000000000088 +:106810000000000000000000000000000000000078 +:106820000000000000000000000000000000000068 +:10683000000000000000000002020201010001024D +:106840000101010101010101000000000000000040 +:106850000000000000000000000000000000000038 +:106860000000000000000000000000000000000028 +:106870000000000000000000000000000000000018 +:1068800000000000000000000202020200010001FE +:1068900001010101000101010000000000000000F1 +:1068A00000000000000000000000000000000000E8 +:1068B00000000000000000000000000000000000D8 +:1068C00000000000000000000000000000000000C8 +:1068D00000000000000000000200000000000000B6 +:1068E0000001000000000001020202010102020199 +:1068F000010101020202020000000000000000008D +:106900000000000000000000000000000000000087 +:106910000000000000000000000000000000000077 +:106920000000000000000000000000000000000067 +:10693000000000000000000002020202010101024A +:10694000020202020101010200000000000000003A +:106950000000000000000000000000000000000037 +:106960000000000000000000000000000000000027 +:106970000000000000000000000000000000000017 +:1069800000000000000000000202020200010001FD +:1069900001010101010101010000000000000000EF +:1069A00000000000000000000000000000000000E7 +:1069B00000000000000000000000000000000000D7 +:1069C00000000000000000000000000000000000C7 +:1069D00000000000000000000200000000000000B5 +:1069E000000000000000000102020201010201019A +:1069F000010101020102020000000000000000008D +:106A00000000000000000000000000000000000086 +:106A10000000000000000000000000000000000076 +:106A20000000000000000000000000000000000066 +:106A30000000000000000000020202020201010248 +:106A40000202020202020202000000000000000036 +:106A50000000000000000000000000000000000036 +:106A60000000000000000000000000000000000026 +:106A70000000000000000000000000000000000016 +:106A800000000000000000000202020200010002FB +:106A900001010101010202010000000000000000EC +:106AA00000000000000000000000000000000000E6 +:106AB00000000000000000000000000000000000D6 +:106AC00000000000000000000000000000000000C6 +:106AD00000000000000000000200020000020000B0 +:106AE000000000000000000102020101010101029A +:106AF000020201020101020000000000000000008B +:106B00000000000000000000000000000000000085 +:106B10000000000000000000000000000000000075 +:106B20000000000000000000000000000000000065 +:106B30000000000000000000020202020201020246 +:106B40000202020202020202000000000000000035 +:106B50000000000000000000000000000000000035 +:106B60000000000000000000000000000000000025 +:106B70000000000000000000000000000000000015 +:106B800000000000000000000202020200020102F8 +:106B900001020202010202010000000000000000E8 +:106BA00000000000000000000000000000000000E5 +:106BB00000000000000000000000000000000000D5 +:106BC00000000000000000000000000000000000C5 +:106BD00000000000000000000200020000020000AF +:106BE000000000000000000101010101010101029B +:106BF0000202020201010200000000000000000089 +:106C00000000000000000000000000000000000084 +:106C10000000000000000000000000000000000074 +:106C20000000000000000000000000000000000064 +:106C30000000000000000000020202020202020244 +:106C40000202020202020202000000000000000034 +:106C50000000000000000000000000000000000034 +:106C60000000000000000000000000000000000024 +:106C70000000000000000000000000000000000014 +:106C800000000000000000000202020202020102F5 +:106C900002020202010202010000000000000000E6 +:106CA00000000000000000000000000000000000E4 +:106CB00000000000000000000000000000000000D4 +:106CC00000000000000000000000000000000000C4 +:106CD00000000000000000000202020000020000AC +:106CE000000000000000000101010101010101029A +:106CF0000202020201010100000000000000000089 +:106D00000000000000000000000000000000000083 +:106D10000000000000000000000000000000000073 +:106D20000000000000000000000000000000000063 +:106D30000000000000000000020202020202020243 +:106D40000202020202020202000000000000000033 +:106D50000000000000000000000000000000000033 +:106D60000000000000000000000000000000000023 +:106D70000000000000000000000000000000000013 +:106D800000000000000000000202020202020202F3 +:106D900002020202020202020000000000000000E3 +:106DA00000000000000000000000000000000000E3 +:106DB00000000000000000000000000000000000D3 +:106DC00000000000000000000000000000000000C3 +:106DD00000000000000000000202020202020002A5 +:106DE0000200020000000001010101010101010295 +:106DF0000202020101010100000000000000000089 +:106E00000000000000000000000000000000000082 +:106E10000000000000000000000000000000000072 +:106E20000000000000000000000000000000000062 +:106E30000000000000000000020202020202020242 +:106E40000202020202020202000000000000000032 +:106E50000000000000000000000000000000000032 +:106E60000000000000000000000000000000000022 +:106E70000000000000000000000000000000000012 +:106E800000000000000000000202020202020202F2 +:106E900002020202020202020000000000000000E2 +:106EA00000000000000000000000000000000000E2 +:106EB00000000000000000000000000000000000D2 +:106EC00000000000000000000000000000000000C2 +:106ED00000000000000000000202020202020002A4 +:106EE000020202020202020101010100000101028C +:106EF0000202020101010100000000000000000088 +:106F00000000000000000000000000000000000081 +:106F10000000000000000000000000000000000071 +:106F20000000000000000000000000000000000061 +:106F30000000000000000000020202020202020241 +:106F40000202020202020202000000000000000031 +:106F50000000000000000000000000000000000031 +:106F60000000000000000000000000000000000021 +:106F70000000000000000000000000000000000011 +:106F800000000000000000000202020202020202F1 +:106F900002020202020202020000000000000000E1 +:106FA00000000000000000000000000000000000E1 +:106FB00000000000000000000000000000000000D1 +:106FC00000000000000000000000000000000000C1 +:106FD00000000000000000000202020202020202A1 +:106FE000020202020202020201010000000000018E +:106FF000010101010000010000000000000000008C +:107000000000000000000000000000000000000080 +:107010000000000000000000000000000000000070 +:107020000000000000000000000000000000000060 +:107030000000000000000000020202020202020240 +:107040000202020202020202000000000000000030 +:107050000000000000000000000000000000000030 +:107060000000000000000000000000000000000020 +:107070000000000000000000000000000000000010 +:1070800000000000000000000202020202020202F0 +:1070900002020202020101020000000000000000E2 +:1070A00000000000000000000000000000000000E0 +:1070B00000000000000000000000000000000000D0 +:1070C00000000000000000000000000000000000C0 +:1070D00000000000000000000202020202020202A0 +:1070E000020202020202020200000000000000018F +:1070F000010101010000000000000000000000008C +:10710000000000000000000000000000000000007F +:10711000000000000000000000000000000000006F +:10712000000000000000000000000000000000005F +:10713000000000000000000002020202020202023F +:10714000020202020202020200000000000000002F +:10715000000000000000000000000000000000002F +:10716000000000000000000000000000000000001F +:10717000000000000000000000000000000000000F +:1071800000000000000000000202020202020202EF +:1071900002020202020202020000000000000000DF +:1071A00000000000000000000000000000000000DF +:1071B00000000000000000000000000000000000CF +:1071C00000000000000000000000000000000000BF +:1071D000000000000000000002020202020202029F +:1071E000020202020202020200000000000000018E +:1071F000010101000000000000000000000000008C +:10720000000000000000000000000000000000007E +:10721000000000000000000000000000000000006E +:10722000000000000000000000000000000000005E +:10723000000000000000000002020202020202023E +:10724000020202020202020200000000000000002E +:10725000000000000000000000000000000000002E +:10726000000000000000000000000000000000001E +:10727000000000000000000000000000000000000E +:1072800000000000000000000202020102020202EF +:1072900002020202020000020000000000000000E2 +:1072A00000000000000000000000000000000000DE +:1072B00000000000000000000000000000000000CE +:1072C00000000000000000000000000000000000BE +:1072D000000000000000000002020202020202029E +:1072E000020202020202020200000000000000008E +:1072F000000000000000000100000000000000008D +:10730000000000000000000000000000000000007D +:10731000000000000000000000000000000000006D +:10732000000000000000000000000000000000005D +:107330000000000000000000020202000002020241 +:10734000020202020202020200000000000000002D +:10735000000000000000000000000000000000002D +:10736000000000000000000000000000000000001D +:10737000000000000000000000000000000000000D +:1073800000000000000000000202020202020202ED +:1073900002020201010000020000000000000000E3 +:1073A00000000000000000000000000000000000DD +:1073B00000000000000000000000000000000000CD +:1073C00000000000000000000000000000000000BD +:1073D000000000000000000002020202020202029D +:1073E000020202020202020200000001010000008B +:1073F000000000000000000100000000000000008C +:10740000000000000000000000000000000000007C +:10741000000000000000000000000000000000006C +:10742000000000000000000000000000000000005C +:107430000000000000000000010101010101010144 +:107440000101010101010101000000000000000034 +:10745000000000000000000000000000000000002C +:10746000000000000000000000000000000000001C +:10747000000000000000000000000000000000000C +:1074800000000000000000000201010001010101F4 +:1074900001010102020000010000000000000000E4 +:1074A00000000000000000000000000000000000DC +:1074B00000000000000000000000000000000000CC +:1074C00000000000000000000000000000000000BC +:1074D000000000000000000002020202020202029C +:1074E0000202020202020202010001010101010086 +:1074F0000000000001010001000000000000000089 +:10750000000000000000000000000000000000007B +:10751000000000000000000000000000000000006B +:10752000000000000000000000000000000000005B +:107530000000000000000000010101010101010143 +:107540000101010101010101000000000000000033 +:10755000000000000000000000000000000000002B +:10756000000000000000000000000000000000001B +:10757000000000000000000000000000000000000B +:1075800000000000000000000102020002020202EE +:1075900002020200000000020000000000000000E3 +:1075A00000000000000000000000000000000000DB +:1075B00000000000000000000000000000000000CB +:1075C00000000000000000000000000000000000BB +:1075D000000000000000000002020202020202029B +:1075E0000202020202020202010101010101010084 +:1075F0000000000001010101000000000000000087 +:10760000000000000000000000000000000000007A +:10761000000000000000000000000000000000006A +:10762000000000000000000000000000000000005A +:107630000000000000000000010101010101010142 +:107640000101010101010101000000000000000032 +:10765000000000000000000000000000000000002A +:10766000000000000000000000000000000000001A +:10767000000000000000000000000000000000000A +:1076800000000000000000000200000000000000F8 +:1076900000000000000000000000000000000000EA +:1076A00000000000000000000000000000000000DA +:1076B00000000000000000000000000000000000CA +:1076C00000000000000000000000000000000000BA +:1076D000000000000000000000020202020002029E +:1076E0000202020202020200010101010101010085 +:1076F0000000000101010101000000000000000085 +:107700000000000000000000000000000000000079 +:107710000000000000000000000000000000000069 +:107720000000000000000000000000000000000059 +:107730000000000000000000010101010101010141 +:107740000101010101010101000000000000000031 +:107750000000000000000000000000000000000029 +:107760000000000000000000000000000000000019 +:107770000000000000000000000000000000000009 +:1077800000000000000000000101010101010101F1 +:1077900001010101010101010000000000000000E1 +:1077A00000000000000000000000000000000000D9 +:1077B00000000000000000000000000000000000C9 +:1077C00000000000000000000000000000000000B9 +:1077D000000000000000000000020202020002029D +:1077E0000202020202020200010101010101010183 +:1077F0000101010101010101000000000000000081 +:107800000000000000000000000000000000000078 +:107810000000000000000000000000000000000068 +:107820000000000000000000000000000000000058 +:107830000000000000000000010101010101010140 +:107840000101010101010101000000000000000030 +:107850000000000000000000000000000000000028 +:107860000000000000000000000000000000000018 +:107870000000000000000000000000000000000008 +:1078800000000000000000000101010101010101F0 +:1078900001010101010101010000000000000000E0 +:1078A00000000000000000000000000000000000D8 +:1078B00000000000000000000000000000000000C8 +:1078C00000000000000000000000000000000000B8 +:1078D000000000000000000000020002020002029E +:1078E0000202000202000000010101010101010188 +:1078F0000101010101010101000000000000000080 +:107900000000000000000000000000000000000077 +:107910000000000000000000000000000000000067 +:107920000000000000000000000000000000000057 +:10793000000000000000000001010101010101013F +:10794000010101010101010100000000000000002F +:107950000000000000000000000000000000000027 +:107960000000000000000000000000000000000017 +:107970000000000000000000000000000000000007 +:1079800000000000000000000101010101010101EF +:1079900001010101010101010000000000000000DF +:1079A00000000000000000000000000000000000D7 +:1079B00000000000000000000000000000000000C7 +:1079C00000000000000000000000000000000000B7 +:1079D000000000000000000000020002020002009F +:1079E000000200000000000001010101010101018D +:1079F000010101010101010100000000000000007F +:107A00000000000000000000000000000000000076 +:107A10000000000000000000000000000000000066 +:107A20000000000000000000000000000000000056 +:107A30000000000000000000020202020202020236 +:107A40000202020202020202000000000000000026 +:107A50000000000000000000000000000000000026 +:107A60000000000000000000000000000000000016 +:107A70000000000000000000000000000000000006 +:107A800000000000000000000202020202020202E6 +:107A900002020202020202020000000000000000D6 +:107AA00000000000000000000000000000000000D6 +:107AB00000000000000000000000000000000000C6 +:107AC00000000000000000000000000000000000B6 +:107AD00000000000000000000002000000000200A2 +:107AE0000000000000000000000000000000000096 +:107AF0000000000000000000000000000000000086 +:107B00000000000000000000000000000000000075 +:107B10000000000000000000000000000000000065 +:107B20000000000000000000000000000000000055 +:107B30000000000000000000000000000000000045 +:107B40000000000000000000000000000000000035 +:107B50000000000000000000000000000000000025 +:107B60000000000000000000000000000000000015 +:107B70000000000000000000000000000000000005 +:107B800000000000000000000000000000000000F5 +:107B900000000000000000000000000000000000E5 +:107BA00000000000000000000000000000000000D5 +:107BB00000000000000000000000000000000000C5 +:107BC00000000000000000000000000000000000B5 +:107BD00000000000000000000000000000000000A5 +:107BE00000000000000000001E0000000000000077 +:107BF000020101010101010100010000000000017A +:107C00000000000000000000000000000000000074 +:107C10000000000000000000000000000000000064 +:107C20000000000000000000000000000000000054 +:107C30000000000000000000000000000000000044 +:107C40000000000000000000000000000101000032 +:107C50000000000000000000000000000000000024 +:107C60000000000000000000000000000000000014 +:107C70000000000000000000000000000000000004 +:107C800000000000000000000000000000000000F4 +:107C900000000000000000000000000000000000E4 +:107CA00000000000000000000000000000000000D4 +:107CB00000000000000000000000000000000000C4 +:107CC00000000000000000000000000000000000B4 +:107CD00000000000000000000000000000000000A4 +:107CE000000101000000000001010100000000018E +:107CF0000201010101010101000200000101010175 +:107D00000000000000000000000000000000000073 +:107D10000000000000000000000000000000000063 +:107D20000000000000000000000000000000000053 +:107D30000000000000000000000000000000000043 +:107D40000000000000000000000000000101000031 +:107D50000000000000000000000000000000000023 +:107D60000000000000000000000000000000000013 +:107D70000000000000000000000000000000000003 +:107D800000000000000000000000000000000000F3 +:107D900000000000000000000000000001010100E0 +:107DA00000000000000000000000000000000000D3 +:107DB00000000000000000000000000000000000C3 +:107DC00000000000000000000000000000000000B3 +:107DD00000000000000000000000000000000000A3 +:107DE000000101000001000001010100000000018C +:107DF0000202010101010101010200010101010171 +:107E00000000000000000000000000000000000072 +:107E10000000000000000000000000000000000062 +:107E20000000000000000000000000000000000052 +:107E30000000000000000000000000000000000042 +:107E40000000000000000000000000000101000030 +:107E50000000000000000000000000000000000022 +:107E60000000000000000000000000000000000012 +:107E70000000000000000000000000000000000002 +:107E800000000000000000000000000000000000F2 +:107E900000000000000000000000000001010100DF +:107EA00000000000000000000000000000000000D2 +:107EB00000000000000000000000000000000000C2 +:107EC00000000000000000000000000000000000B2 +:107ED00000000000000000000000000000000000A2 +:107EE000000101000101000001010100000000018A +:107EF000020202010101010101020001010101016F +:107F00000000000000000000000000000000000071 +:107F10000000000000000000000000000000000061 +:107F20000000000000000000000000000000000051 +:107F30000000000000000000000000000000000041 +:107F4000010000000000000000000000010100002E +:107F50000000000000000000000000000000000021 +:107F60000000000000000000000000000000000011 +:107F70000000000000000000000000000000000001 +:107F800000000000000000000000000000000000F1 +:107F900000000000000000000000000001010100DE +:107FA00000000000000000000000000000000000D1 +:107FB00000000000000000000000000000000000C1 +:107FC00000000000000000000000000000000000B1 +:107FD00000000000000000000000000000000000A1 +:107FE0000001010101010000010101000101010185 +:107FF000020202020101010101020001010101016D +:108000000000000000000000000000000000000070 +:108010000000000000000000000000000000000060 +:108020000000000000000000000000000000000050 +:108030000000000000000000000000000000000040 +:10804000020000000000000000000000010101002B +:108050000000000000000000000000000000000020 +:108060000000000000000000000000000000000010 +:108070000000000000000000000000000000000000 +:1080800000000000000000000000000000000000F0 +:1080900000000000000100000000000101010100DB +:1080A00000000000000000000000000000000000D0 +:1080B00000000000000000000000000000000000C0 +:1080C00000000000000000000000000000000000B0 +:1080D00000000000000000000000000000000000A0 +:1080E0000001010101010000010101010101010183 +:1080F000020202020101010102020101010101016A +:10810000000000000000000000000000000000006F +:10811000000000000000000000000000000000005F +:10812000000000000000000000000000000000004F +:10813000000000000000000000000000000000003F +:108140000201000000000000000000000101010029 +:10815000000000000000000000000000000000001F +:10816000000000000000000000000000000000000F +:1081700000000000000000000000000000000000FF +:1081800000000000000000000000000000000000EF +:1081900000000000000100000000000101010101D9 +:1081A00000000000000000000000000000000000CF +:1081B00000000000000000000000000000000000BF +:1081C00000000000000000000000000000000000AF +:1081D000000000000000000000000000000000009F +:1081E0000000010101010101010101010101010181 +:1081F0000202020201010102020201010101010168 +:10820000000000000000000000000000000000006E +:10821000000000000000000000000000000000005E +:10822000000000000000000000000000000000004E +:10823000000000000000000000000000000000003E +:108240000201000001000000000000000101010126 +:10825000000000000000000000000000000000001E +:10826000000000000000000000000000000000000E +:1082700000000000000000000000000000000000FE +:1082800000000000000000000000000000000000EE +:1082900000000001000101000000000101010101D6 +:1082A00000000000000000000000000000000000CE +:1082B00000000000000000000000000000000000BE +:1082C00000000000000000000000000000000000AE +:1082D000000000000000000000000000000000009E +:1082E0000000000101010101010101010101010181 +:1082F0000202020202020102020101010101010067 +:10830000000000000000000000000000000000006D +:10831000000000000000000000000000000000005D +:10832000000000000000000000000000000000004D +:10833000000000000000000000000000000000003D +:108340000201000101010000000000000101010123 +:10835000000000000000000000000000000000001D +:10836000000000000000000000000000000000000D +:1083700000000000000000000000000000000000FD +:1083800000000000000000000000000000000000ED +:1083900000000001010101000000000101010101D4 +:1083A00000000000000000000000000000000000CD +:1083B00000000000000000000000000000000000BD +:1083C00000000000000000000000000000000000AD +:1083D000000000000000000000000000000000009D +:1083E0000000000101010101010101010101010180 +:1083F0000202020202020102020101010101010066 +:10840000000000000000000000000000000000006C +:10841000000000000000000000000000000000005C +:10842000000000000000000000000000000000004C +:10843000000000000000000000000000000000003C +:108440000202000101010000000000000101010121 +:10845000000000000000000000000000000000001C +:10846000000000000000000000000000000000000C +:1084700000000000000000000000000000000000FC +:1084800000000000000000000000000000000000EC +:1084900001010001010101010000000101010101D0 +:1084A00000000000000000000000000000000000CC +:1084B00000000000000000000000000000000000BC +:1084C00000000000000000000000000000000000AC +:1084D000000000000000000000000000000000009C +:1084E0000000000101010101000001010101010181 +:1084F0000202020202020202020101010101010064 +:10850000000000000000000000000000000000006B +:10851000000000000000000000000000000000005B +:10852000000000000000000000000000000000004B +:10853000000000000000000000000000000000003B +:10854000020201010101000000010000010101011E +:10855000000000000000000000000000000000001B +:10856000000000000000000000000000000000000B +:1085700000000000000000000000000000000000FB +:1085800000000000000000000000000000000000EB +:1085900002010001010101010000010101010101CD +:1085A00000000000000000000000000000000000CB +:1085B00000000000000000000000000000000000BB +:1085C00000000000000000000000000000000000AB +:1085D000000000000000000000000000000000009B +:1085E000010000010101010100000101010101017F +:1085F0000202020202020202010101010101010064 +:10860000000000000000000000000000000000006A +:10861000000000000000000000000000000000005A +:10862000000000000000000000000000000000004A +:10863000000000000000000000000000000000003A +:10864000020201010101000000010000020201011B +:10865000000000000000000000000000000000001A +:10866000000000000000000000000000000000000A +:1086700000000000000000000000000000000000FA +:1086800000000000000000000000000000000000EA +:1086900002010101010101010100010101010101CA +:1086A00000000000000000000000000000000000CA +:1086B00000000000000000000000000000000000BA +:1086C00000000000000000000000000000000000AA +:1086D000000000000000000000000000000000009A +:1086E000010000010101010100000101010101017E +:1086F0000201010102020202010101010101010066 +:108700000000000000000000000000000000000069 +:108710000000000000000000000000000000000059 +:108720000000000000000000000000000000000049 +:108730000000000000000000000000000000000039 +:108740000202020202010100000100010202010115 +:108750000000000000000000000000000000000019 +:108760000000000000000000000000000000000009 +:1087700000000000000000000000000000000000F9 +:1087800000000000000000000000000000000000E9 +:1087900002010101010101010100010101010101C9 +:1087A00000000000000000000000000000000000C9 +:1087B00000000000000000000000000000000000B9 +:1087C00000000000000000000000000000000000A9 +:1087D0000000000000000000000000000000000099 +:1087E000020000000001010100000101010101007F +:1087F0000101010102020201010101010101010067 +:108800000000000000000000000000000000000068 +:108810000000000000000000000000000000000058 +:108820000000000000000000000000000000000048 +:108830000000000000000000000000000000000038 +:108840000202020202020100000100010202020112 +:108850000000000000000000000000000000000018 +:108860000000000000000000000000000000000008 +:1088700000000000000000000000000000000000F8 +:1088800000000000000000000000000000000000E8 +:1088900002020101010101010101010101010101C6 +:1088A00000000000000000000000000000000000C8 +:1088B00000000000000000000000000000000000B8 +:1088C00000000000000000000000000000000000A8 +:1088D0000000000000000000000000000000000098 +:1088E000020000000001010100000001010101007F +:1088F0000101010102010201010102020101020064 +:108900000000000000000000000000000000000067 +:108910000000000000000000000000000000000057 +:108920000000000000000000000000000000000047 +:108930000000000000000000000000000000000037 +:10894000020202020202010000020001020202020F +:108950000000000000000000000000000000000017 +:108960000000000000000000000000000000000007 +:1089700000000000000000000000000000000000F7 +:1089800000000000000000000000000000000000E7 +:1089900002020102010201010101010102020201C0 +:1089A00000000000000000000000000000000000C7 +:1089B00000000000000000000000000000000000B7 +:1089C00000000000000000000000000000000000A7 +:1089D0000000000000000000000000000000000097 +:1089E000020000000002000000000001010101007F +:1089F0000101010101010201010102020202020062 +:108A00000000000000000000000000000000000066 +:108A10000000000000000000000000000000000056 +:108A20000000000000000000000000000000000046 +:108A30000000000000000000000000000000000036 +:108A4000020202020202020000020102020202020B +:108A50000000000000000000000000000000000016 +:108A60000000000000000000000000000000000006 +:108A700000000000000000000000000000000000F6 +:108A800000000000000000000000000000000000E6 +:108A900002020202020202010101010202020201BB +:108AA00000000000000000000000000000000000C6 +:108AB00000000000000000000000000000000000B6 +:108AC00000000000000000000000000000000000A6 +:108AD0000000000000000000000000000000000096 +:108AE0000202000000020000000000000000000080 +:108AF0000101010101010101010002020202020063 +:108B00000000000000000000000000000000000065 +:108B10000000000000000000000000000000000055 +:108B20000000000000000000000000000000000045 +:108B30000000000000000000000000000000000035 +:108B40000202020202020201010201020202020208 +:108B50000000000000000000000000000000000015 +:108B60000000000000000000000000000000000005 +:108B700000000000000000000000000000000000F5 +:108B800000000000000000000000000000000000E5 +:108B900002020202020202020101010202020202B8 +:108BA00000000000000000000000000000000000C5 +:108BB00000000000000000000000000000000000B5 +:108BC00000000000000000000000000000000000A5 +:108BD0000000000000000000000000000000000095 +:108BE0000202020202020000000002000000000077 +:108BF0000101010101010101010001020202020063 +:108C00000000000000000000000000000000000064 +:108C10000000000000000000000000000000000054 +:108C20000000000000000000000000000000000044 +:108C30000000000000000000000000000000000034 +:108C40000202020202020202020202020202020204 +:108C50000000000000000000000000000000000014 +:108C60000000000000000000000000000000000004 +:108C700000000000000000000000000000000000F4 +:108C800000000000000000000000000000000000E4 +:108C900002020202020202020201020202020202B5 +:108CA00000000000000000000000000000000000C4 +:108CB00000000000000000000000000000000000B4 +:108CC00000000000000000000000000000000000A4 +:108CD0000000000000000000000000000000000094 +:108CE0000202020202020000000002000000000076 +:108CF0000100000001010101000001020202020066 +:108D00000000000000000000000000000000000063 +:108D10000000000000000000000000000000000053 +:108D20000000000000000000000000000000000043 +:108D30000000000000000000000000000000000033 +:108D40000202020202020202020202020202020203 +:108D50000000000000000000000000000000000013 +:108D60000000000000000000000000000000000003 +:108D700000000000000000000000000000000000F3 +:108D800000000000000000000000000000000000E3 +:108D900002020202020202020202020202020202B3 +:108DA00000000000000000000000000000000000C3 +:108DB00000000000000000000000000000000000B3 +:108DC00000000000000000000000000000000000A3 +:108DD0000000000000000000000000000000000093 +:108DE0000202020202020202020202020202020263 +:108DF000000000000100010000000101020201006A +:108E00000000000000000000000000000000000062 +:108E10000000000000000000000000000000000052 +:108E20000000000000000000000000000000000042 +:108E30000000000000000000000000000000000032 +:108E40000202020202020202020202020202020202 +:108E50000000000000000000000000000000000012 +:108E60000000000000000000000000000000000002 +:108E700000000000000000000000000000000000F2 +:108E800000000000000000000000000000000000E2 +:108E900002020202020202020202020202020202B2 +:108EA00000000000000000000000000000000000C2 +:108EB00000000000000000000000000000000000B2 +:108EC00000000000000000000000000000000000A2 +:108ED0000000000000000000000000000000000092 +:108EE0000202020202020202020202020202020262 +:108EF000000000000000000000000101010101006D +:108F00000000000000000000000000000000000061 +:108F10000000000000000000000000000000000051 +:108F20000000000000000000000000000000000041 +:108F30000000000000000000000000000000000031 +:108F40000202020202020202020202010202020202 +:108F50000000000000000000000000000000000011 +:108F60000000000000000000000000000000000001 +:108F700000000000000000000000000000000000F1 +:108F800000000000000000000000000000000000E1 +:108F900002020202020202020202020202020202B1 +:108FA00000000000000000000000000000000000C1 +:108FB00000000000000000000000000000000000B1 +:108FC00000000000000000000000000000000000A1 +:108FD0000000000000000000000000000000000091 +:108FE0000202020202020202020202020202020261 +:108FF000000000000000000000010001010101006C +:109000000000000000000000000000000000000060 +:109010000000000000000000000000000000000050 +:109020000000000000000000000000000000000040 +:109030000000000000000000000000000000000030 +:109040000202020202020202020202010202020201 +:109050000000000000000000000000000000000010 +:109060000000000000000000000000000000000000 +:1090700000000000000000000000000000000000F0 +:1090800000000000000000000000000000000000E0 +:1090900002020202020202020202020202020202B0 +:1090A00000000000000000000000000000000000C0 +:1090B00000000000000000000000000000000000B0 +:1090C00000000000000000000000000000000000A0 +:1090D0000000000000000000000000000000000090 +:1090E0000202020202020202020202020202020260 +:1090F000000000000000000000010001010101016A +:10910000000000000000000000000000000000005F +:10911000000000000000000000000000000000004F +:10912000000000000000000000000000000000003F +:10913000000000000000000000000000000000002F +:10914000010101010101010101020202010101010C +:10915000000000000000000000000000000000000F +:1091600000000000000000000000000000000000FF +:1091700000000000000000000000000000000000EF +:1091800000000000000000000000000000000000DF +:1091900002020202020202020202020202020202AF +:1091A00000000000000000000000000000000000BF +:1091B00000000000000000000000000000000000AF +:1091C000000000000000000000000000000000009F +:1091D000000000000000000000000000000000008F +:1091E000020202020202020202020202020202025F +:1091F0000001010100000000010100000000000169 +:10920000000000000000000000000000000000005E +:10921000000000000000000000000000000000004E +:10922000000000000000000000000000000000003E +:10923000000000000000000000000000000000002E +:109240000202020202020202020101020202020200 +:10925000000000000000000000000000000000000E +:1092600000000000000000000000000000000000FE +:1092700000000000000000000000000000000000EE +:1092800000000000000000000000000000000000DE +:1092900002020202020202020202020202020202AE +:1092A00000000000000000000000000000000000BE +:1092B00000000000000000000000000000000000AE +:1092C000000000000000000000000000000000009E +:1092D000000000000000000000000000000000008E +:1092E000020202020202020202020202020202025E +:1092F0000101010101010001010100000000000164 +:10930000000000000000000000000000000000005D +:10931000000000000000000000000000000000004D +:10932000000000000000000000000000000000003D +:10933000000000000000000000000000000000002D +:10934000010101010101010101010101010101010D +:10935000000000000000000000000000000000000D +:1093600000000000000000000000000000000000FD +:1093700000000000000000000000000000000000ED +:1093800000000000000000000000000000000000DD +:1093900002020202020202020202020202020202AD +:1093A00000000000000000000000000000000000BD +:1093B00000000000000000000000000000000000AD +:1093C000000000000000000000000000000000009D +:1093D000000000000000000000000000000000008D +:1093E000020202020202020202020202020202025D +:1093F0000101010101010101010100000000000162 +:10940000000000000000000000000000000000005C +:10941000000000000000000000000000000000004C +:10942000000000000000000000000000000000003C +:10943000000000000000000000000000000000002C +:10944000010101010101010101010101010101010C +:10945000000000000000000000000000000000000C +:1094600000000000000000000000000000000000FC +:1094700000000000000000000000000000000000EC +:1094800000000000000000000000000000000000DC +:1094900002020202020202020202020202020202AC +:1094A00000000000000000000000000000000000BC +:1094B00000000000000000000000000000000000AC +:1094C000000000000000000000000000000000009C +:1094D000000000000000000000000000000000008C +:1094E000020202020202020202020202020202025C +:1094F000010101010101010101010101010101015C +:10950000000000000000000000000000000000005B +:10951000000000000000000000000000000000004B +:10952000000000000000000000000000000000003B +:10953000000000000000000000000000000000002B +:10954000010101010101010101010101010101010B +:10955000000000000000000000000000000000000B +:1095600000000000000000000000000000000000FB +:1095700000000000000000000000000000000000EB +:1095800000000000000000000000000000000000DB +:1095900001010101010101010101010101010101BB +:1095A00000000000000000000000000000000000BB +:1095B00000000000000000000000000000000000AB +:1095C000000000000000000000000000000000009B +:1095D000000000000000000000000000000000008B +:1095E000020202020202020202020202020202025B +:1095F000010101010101010101010101010101015B +:10960000000000000000000000000000000000005A +:10961000000000000000000000000000000000004A +:10962000000000000000000000000000000000003A +:10963000000000000000000000000000000000002A +:10964000010101010101010101010101010101010A +:10965000000000000000000000000000000000000A +:1096600000000000000000000000000000000000FA +:1096700000000000000000000000000000000000EA +:1096800000000000000000000000000000000000DA +:1096900002020202020202020202020202020202AA +:1096A00000000000000000000000000000000000BA +:1096B00000000000000000000000000000000000AA +:1096C000000000000000000000000000000000009A +:1096D000000000000000000000000000000000008A +:1096E000020202020202020202020202020202025A +:1096F000010101010101010101010101010101015A +:109700000000000000000000000000000000000059 +:109710000000000000000000000000000000000049 +:109720000000000000000000000000000000000039 +:109730000000000000000000000000000000000029 +:109740000101010101010101010101010101010109 +:109750000000000000000000000000000000000009 +:1097600000000000000000000000000000000000F9 +:1097700000000000000000000000000000000000E9 +:1097800000000000000000000000000000000000D9 +:1097900001010101010101010101010101010101B9 +:1097A00000000000000000000000000000000000B9 +:1097B00000000000000000000000000000000000A9 +:1097C0000000000000000000000000000000000099 +:1097D0000000000000000000000000000000000089 +:1097E0000202020202020202020202020202020259 +:1097F0000101010101010101010101010101010159 +:109800000000000000000000000000000000000058 +:109810000000000000000000000000000000000048 +:109820000000000000000000000000000000000038 +:109830000000000000000000000000000000000028 +:1098400002020202020202020202020202020202F8 +:109850000000000000000000000000000000000008 +:1098600000000000000000000000000000000000F8 +:1098700000000000000000000000000000000000E8 +:1098800000000000000000000000000000000000D8 +:1098900001010101010101010101010101010101B8 +:1098A00000000000000000000000000000000000B8 +:1098B00000000000000000000000000000000000A8 +:1098C0000000000000000000000000000000000098 +:1098D0000000000000000000000000000000000088 +:1098E0000000000000000000000002000000000076 +:1098F0000000000000000000000000000000000068 +:109900000000000000000000000000000000000057 +:109910000000000000000000000000000000000047 +:109920000000000000000000000000000000000037 +:109930000000000000000000000000000000000027 +:109940000000000000000000000000000000000017 +:109950000000000000000000000000000000000007 +:1099600000000000000000000000000000000000F7 +:1099700000000000000000000000000000000000E7 +:1099800000000000000000000000000000000000D7 +:1099900000000000000000000000000000000000C7 +:1099A00000000000000000000000000000000000B7 +:1099B00000000000000000000000000000000000A7 +:1099C0000000000000000000000000000000000097 +:1099D0000000000000000000000000000000000087 +:1099E0000000000000000000000000000000000077 +:1099F0001E00000000000000020000000200000045 +:109A00000000000001010101000000000000000052 +:109A10000000000000000000000000000000000046 +:109A20000000000000000000000000000000000036 +:109A30000000000000000000000000000000000026 +:109A40000000000000000000000000000000000016 +:109A50000000000001010100000000000000000003 +:109A600000000000000000000000000000000000F6 +:109A700000000000000000000000000000000000E6 +:109A800000000000000000000000000000000000D6 +:109A900000000000000000000000000100000000C5 +:109AA00000000000000000000000000000000000B6 +:109AB00000000000000000000000000000000000A6 +:109AC0000000000000000000000000000000000096 +:109AD0000000000000000000000000000000000086 +:109AE000000000000000000000010101010101016F +:109AF0000100010101010100020101000200010059 +:109B00000100000001010101000000000000000050 +:109B10000000000000000000000000000000000045 +:109B20000000000000000000000000000000000035 +:109B30000000000000000000000000000000000025 +:109B40000000000000000000000000000000000015 +:109B50000000000001010100000000000000000002 +:109B600000000000000000000000000000000000F5 +:109B700000000000000000000000000000000000E5 +:109B800000000000000000000000000000000000D5 +:109B900000000000000000000000000100000000C4 +:109BA00001010000000000000000000000000000B3 +:109BB00000000000000000000000000000000000A5 +:109BC0000000000000000000000000000000000095 +:109BD0000000000000000000000000000000000085 +:109BE000000000000000000000010101010101016E +:109BF0000101010101010100020101010201010055 +:109C0000010001000101010100000000000000004E +:109C10000000000000000000000000000000000044 +:109C20000000000000000000000000000000000034 +:109C30000000000000000000000000000000000024 +:109C40000000000000000000000000000000000014 +:109C50000000000001010101000000000000000000 +:109C600000000000000000000000000000000000F4 +:109C700000000000000000000000000000000000E4 +:109C800000000000000000000000000000000000D4 +:109C900000000000000000000000000100000000C3 +:109CA00001010000000000000000000000000000B2 +:109CB00000000000000000000000000000000000A4 +:109CC0000000000000000000000000000000000094 +:109CD0000000000000000000000000000000000084 +:109CE000000000000000000000010101010101016D +:109CF0000101010101010100020102010201010152 +:109D0000010201010101010100000000000000004A +:109D10000000000000000000000000000000000043 +:109D20000000000000000000000000000000000033 +:109D30000000000000000000000000000000000023 +:109D40000000000000000000000000000000000013 +:109D500000000001010101010000000000000000FE +:109D600000000000000000000000000000000000F3 +:109D700000000000000000000000000000000000E3 +:109D800000000000000000000000000000000000D3 +:109D900000000000000000000000000100000000C2 +:109DA00001010000000000000000000000000000B1 +:109DB00000000000000000000000000000000000A3 +:109DC0000000000000000000000000000000000093 +:109DD0000000000000000000000000000000000083 +:109DE000000000000000000000010101010101016C +:109DF000010101010101010102020202020101014E +:109E00000102010101010101000000000000000049 +:109E10000000000000000000000000000000000042 +:109E20000000000000000000000000000000000032 +:109E30000000000000000000000000000000000022 +:109E40000000000000000000000000000000000012 +:109E500000000001010101010000000000000000FD +:109E600000000000000000000000000000000000F2 +:109E700000000000000000000000000000000000E2 +:109E800000000000000000000000000000000000D2 +:109E900000000000000000000000000101000000C0 +:109EA00001010001000000000000000000000000AF +:109EB00000000000000000000000000000000000A2 +:109EC0000000000000000000000000000000000092 +:109ED0000000000000000000000000000000000082 +:109EE000000000000000000000010101010101016B +:109EF000010101010101010102020202020101024C +:109F00000102010201010101000000000000000047 +:109F10000000000000000000000000000000000041 +:109F20000000000000000000000000000000000031 +:109F30000000000000000000000000000000000021 +:109F40000000000000000000000000000000000011 +:109F500000000001010101010000000000000000FC +:109F600000000000000000000000000000000000F1 +:109F700000000000000000000000000000000000E1 +:109F800000000000000000000000000000000000D1 +:109F900000000000000000000000000101000000BF +:109FA00001010001010101010000000000000000AA +:109FB00000000000000000000000000000000000A1 +:109FC0000000000000000000000000000000000091 +:109FD0000000000000000000000000000000000081 +:109FE000000000000000000000010101010101016A +:109FF000010101010101010102020202020101024B +:10A000000102010201010101000000000000000046 +:10A010000000000000000000000000000000000040 +:10A020000000000000000000000000000000000030 +:10A030000000000000000000000000000000000020 +:10A04000000000000000000001000000000000000F +:10A0500000000001010101010000000000000000FB +:10A0600000000000000000000000000000000000F0 +:10A0700000000000000000000000000000000000E0 +:10A0800000000000000000000000000000000000D0 +:10A0900000000000000000000000000101000100BD +:10A0A00001010001010101010000000000000000A9 +:10A0B00000000000000000000000000000000000A0 +:10A0C0000000000000000000000000000000000090 +:10A0D0000000000000000000000000000000000080 +:10A0E0000000000000000000010101010101010168 +:10A0F0000101010101010101020202020202020248 +:10A100000202020201010100000000000000000044 +:10A11000000000000000000000000000000000003F +:10A12000000000000000000000000000000000002F +:10A13000000000000000000000000000000000001F +:10A14000000000000000000002010000000101000A +:10A1500000000101010101010000000000000000F9 +:10A1600000000000000000000000000000000000EF +:10A1700000000000000000000000000000000000DF +:10A1800000000000000000000000000000000000CF +:10A1900000000000000000000000000101000100BC +:10A1A00001010001010101010000000000000000A8 +:10A1B000000000000000000000000000000000009F +:10A1C000000000000000000000000000000000008F +:10A1D000000000000000000000000000000000007F +:10A1E0000000000000000000010101010101010167 +:10A1F0000101010101010101020202020102020248 +:10A200000201020201010100000000000000000044 +:10A21000000000000000000000000000000000003E +:10A22000000000000000000000000000000000002E +:10A23000000000000000000000000000000000001E +:10A240000000000000000000020100000001010009 +:10A2500000000101010101010000000000000000F8 +:10A2600000000000000000000000000000000000EE +:10A2700000000000000000000000000000000000DE +:10A2800000000000000000000000000000000000CE +:10A2900000000000000000000000000101000100BB +:10A2A00001010001010101010000000000000000A7 +:10A2B000000000000000000000000000000000009E +:10A2C000000000000000000000000000000000008E +:10A2D000000000000000000000000000000000007E +:10A2E0000000000000000000020001010101010166 +:10A2F0000101010101010101020202020102020247 +:10A300000201020101010200000000000000000043 +:10A31000000000000000000000000000000000003D +:10A32000000000000000000000000000000000002D +:10A33000000000000000000000000000000000001D +:10A340000000000000000000020101000001010007 +:10A3500001000101010101010000000000000000F6 +:10A3600000000000000000000000000000000000ED +:10A3700000000000000000000000000000000000DD +:10A3800000000000000000000000000000000000CD +:10A3900000000000000000000000000101000100BA +:10A3A00001010101010101010000000000000000A5 +:10A3B000000000000000000000000000000000009D +:10A3C000000000000000000000000000000000008D +:10A3D000000000000000000000000000000000007D +:10A3E0000000000000000000020001010101010165 +:10A3F0000101010101010101020202020102020147 +:10A400000201020101010200000000000000000042 +:10A41000000000000000000000000000000000003C +:10A42000000000000000000000000000000000002C +:10A43000000000000000000000000000000000001C +:10A440000000000000000000020201000001010005 +:10A4500001000101010101010000000000000000F5 +:10A4600000000000000000000000000000000000EC +:10A4700000000000000000000000000000000000DC +:10A4800000000000000000000000000000000000CC +:10A4900000000000000000000001000201000101B6 +:10A4A00001010101010101010000000000000000A4 +:10A4B000000000000000000000000000000000009C +:10A4C000000000000000000000000000000000008C +:10A4D000000000000000000000000000000000007C +:10A4E0000000000000000000020201010101010162 +:10A4F000000001010101010102020101010202014A +:10A500000201020101010200000000000000000041 +:10A51000000000000000000000000000000000003B +:10A52000000000000000000000000000000000002B +:10A53000000000000000000000000000000000001B +:10A540000000000000000000020201000101010102 +:10A5500001000101020202010000000000000000F1 +:10A5600000000000000000000000000000000000EB +:10A5700000000000000000000000000000000000DB +:10A5800000000000000000000000000000000000CB +:10A5900000000000000000000101000201010101B3 +:10A5A00001010101010101010000000000000000A3 +:10A5B000000000000000000000000000000000009B +:10A5C000000000000000000000000000000000008B +:10A5D000000000000000000000000000000000007B +:10A5E000000000000000000002020202020101015E +:10A5F000000001010101010101020101010202014A +:10A60000020101010202020000000000000000003F +:10A61000000000000000000000000000000000003A +:10A62000000000000000000000000000000000002A +:10A63000000000000000000000000000000000001A +:10A6400000000000000000000202020101020101FE +:10A6500001000102020202020000000000000000EE +:10A6600000000000000000000000000000000000EA +:10A6700000000000000000000000000000000000DA +:10A6800000000000000000000000000000000000CA +:10A6900000000000000000000201010202010101AF +:10A6A00002020101010101010000000000000000A0 +:10A6B000000000000000000000000000000000009A +:10A6C000000000000000000000000000000000008A +:10A6D000000000000000000000000000000000007A +:10A6E000000000000000000002020202020201015C +:10A6F0000202010101010100010101010101010149 +:10A70000010101010202020000000000000000003F +:10A710000000000000000000000000000000000039 +:10A720000000000000000000000000000000000029 +:10A730000000000000000000000000000000000019 +:10A7400000000000000000000202020102020201FB +:10A7500002010202020202020000000000000000EA +:10A7600000000000000000000000000000000000E9 +:10A7700000000000000000000000000000000000D9 +:10A7800000000000000000000000000000000000C9 +:10A7900000000000000000000201010202010101AE +:10A7A000020201010101010100000000000000009F +:10A7B0000000000000000000000000000000000099 +:10A7C0000000000000000000000000000000000089 +:10A7D0000000000000000000000000000000000079 +:10A7E0000000000000000000020202020202020259 +:10A7F0000202020201010100010101010101010146 +:10A80000010101010202010000000000000000003F +:10A810000000000000000000000000000000000038 +:10A820000000000000000000000000000000000028 +:10A830000000000000000000000000000000000018 +:10A8400000000000000000000202020202020201F9 +:10A8500002010202020202020000000000000000E9 +:10A8600000000000000000000000000000000000E8 +:10A8700000000000000000000000000000000000D8 +:10A8800000000000000000000000000000000000C8 +:10A8900000000000000000000202010202010101AC +:10A8A000020201010101010100000000000000009E +:10A8B0000000000000000000000000000000000098 +:10A8C0000000000000000000000000000000000088 +:10A8D0000000000000000000000000000000000078 +:10A8E0000000000000000000020202020202020258 +:10A8F0000202020202020000010101010101010144 +:10A90000010101010202010000000000000000003E +:10A910000000000000000000000000000000000037 +:10A920000000000000000000000000000000000027 +:10A930000000000000000000000000000000000017 +:10A9400000000000000000000202020202020202F7 +:10A9500002020202020202020000000000000000E7 +:10A9600000000000000000000000000000000000E7 +:10A9700000000000000000000000000000000000D7 +:10A9800000000000000000000000000000000000C7 +:10A9900000000000000000000202010202010201AA +:10A9A000020201020101010100000000000000009C +:10A9B0000000000000000000000000000000000097 +:10A9C0000000000000000000000000000000000087 +:10A9D0000000000000000000000000000000000077 +:10A9E0000000000000000000020202020202020257 +:10A9F0000202020202020202010101010001010140 +:10AA0000010001000202010000000000000000003F +:10AA10000000000000000000000000000000000036 +:10AA20000000000000000000000000000000000026 +:10AA30000000000000000000000000000000000016 +:10AA400000000000000000000202020202020202F6 +:10AA500002020202020202020000000000000000E6 +:10AA600000000000000000000000000000000000E6 +:10AA700000000000000000000000000000000000D6 +:10AA800000000000000000000000000000000000C6 +:10AA900000000000000000000202020202010201A8 +:10AAA0000202010202020202000000000000000097 +:10AAB0000000000000000000000000000000000096 +:10AAC0000000000000000000000000000000000086 +:10AAD0000000000000000000000000000000000076 +:10AAE0000000000000000000020202020202020256 +:10AAF0000202020202020202010100000001010042 +:10AB00000100010001010100000000000000000040 +:10AB10000000000000000000000000000000000035 +:10AB20000000000000000000000000000000000025 +:10AB30000000000000000000000000000000000015 +:10AB400000000000000000000202020202020202F5 +:10AB500002020202020202020000000000000000E5 +:10AB600000000000000000000000000000000000E5 +:10AB700000000000000000000000000000000000D5 +:10AB800000000000000000000000000000000000C5 +:10AB900000000000000000000202020202020202A5 +:10ABA0000202020202020202000000000000000095 +:10ABB0000000000000000000000000000000000095 +:10ABC0000000000000000000000000000000000085 +:10ABD0000000000000000000000000000000000075 +:10ABE0000000000000000000020202020202020255 +:10ABF0000202020202020202000000000000000045 +:10AC00000000000001010100000000000000000041 +:10AC10000000000000000000000000000000000034 +:10AC20000000000000000000000000000000000024 +:10AC30000000000000000000000000000000000014 +:10AC400000000000000000000202020202020202F4 +:10AC500002020202020202020000000000000000E4 +:10AC600000000000000000000000000000000000E4 +:10AC700000000000000000000000000000000000D4 +:10AC800000000000000000000000000000000000C4 +:10AC900000000000000000000202020202020202A4 +:10ACA0000202020202020202000000000000000094 +:10ACB0000000000000000000000000000000000094 +:10ACC0000000000000000000000000000000000084 +:10ACD0000000000000000000000000000000000074 +:10ACE0000000000000000000020202020202020254 +:10ACF0000202020202020202000000000000000044 +:10AD00000000000001010000000000000000000041 +:10AD10000000000000000000000000000000000033 +:10AD20000000000000000000000000000000000023 +:10AD30000000000000000000000000000000000013 +:10AD400000000000000000000202020202020202F3 +:10AD500002020202020202020000000000000000E3 +:10AD600000000000000000000000000000000000E3 +:10AD700000000000000000000000000000000000D3 +:10AD800000000000000000000000000000000000C3 +:10AD900000000000000000000202020202020202A3 +:10ADA0000202020202020202000000000000000093 +:10ADB0000000000000000000000000000000000093 +:10ADC0000000000000000000000000000000000083 +:10ADD0000000000000000000000000000000000073 +:10ADE0000000000000000000020202020202020253 +:10ADF0000202020202020202000000000000000043 +:10AE00000000000000000000000000000000000042 +:10AE10000000000000000000000000000000000032 +:10AE20000000000000000000000000000000000022 +:10AE30000000000000000000000000000000000012 +:10AE400000000000000000000202020202020202F2 +:10AE500000000202020202020000000000000000E6 +:10AE600000000000000000000000000000000000E2 +:10AE700000000000000000000000000000000000D2 +:10AE800000000000000000000000000000000000C2 +:10AE900000000000000000000202020202020202A2 +:10AEA0000202020202020202000000000000000092 +:10AEB0000000000000000000000000000000000092 +:10AEC0000000000000000000000000000000000082 +:10AED0000000000000000000000000000000000072 +:10AEE0000000000000000000020202020202020252 +:10AEF0000202020202020202000000000100000041 +:10AF0000000100010000000000000000000000003F +:10AF10000000000000000000000000000000000031 +:10AF20000000000000000000000000000000000021 +:10AF30000000000000000000000000000000000011 +:10AF400000000000000000000202020200000202F5 +:10AF500000000002020202020000000000000000E7 +:10AF600000000000000000000000000000000000E1 +:10AF700000000000000000000000000000000000D1 +:10AF800000000000000000000000000000000000C1 +:10AF900000000000000000000202020202020202A1 +:10AFA0000202020202020202000000000000000091 +:10AFB0000000000000000000000000000000000091 +:10AFC0000000000000000000000000000000000081 +:10AFD0000000000000000000000000000000000071 +:10AFE0000000000000000000020202020202020251 +:10AFF000020202020202020200000101010000013D +:10B00000000100010000000100000000000000003D +:10B010000000000000000000000000000000000030 +:10B020000000000000000000000000000000000020 +:10B030000000000000000000000000000000000010 +:10B040000000000000000000000000000000000000 +:10B0500000000000000000000000000000000000F0 +:10B0600000000000000000000000000000000000E0 +:10B0700000000000000000000000000000000000D0 +:10B0800000000000000000000000000000000000C0 +:10B0900000000000000000000202020202020202A0 +:10B0A0000202020202020202000000000000000090 +:10B0B0000000000000000000000000000000000090 +:10B0C0000000000000000000000000000000000080 +:10B0D0000000000000000000000000000000000070 +:10B0E0000000000000000000020202020202020250 +:10B0F0000202020202020202010101010101010138 +:10B10000010101010000000100000000000000003A +:10B11000000000000000000000000000000000002F +:10B12000000000000000000000000000000000001F +:10B13000000000000000000000000000000000000F +:10B1400000000000000000000101010101010101F7 +:10B1500001010101010101010000000000000000E7 +:10B1600000000000000000000000000000000000DF +:10B1700000000000000000000000000000000000CF +:10B1800000000000000000000000000000000000BF +:10B19000000000000000000002020202020202029F +:10B1A000020202020202020200000000000000008F +:10B1B000000000000000000000000000000000008F +:10B1C000000000000000000000000000000000007F +:10B1D000000000000000000000000000000000006F +:10B1E000000000000000000002020202020202024F +:10B1F0000202020202020202010101010101010137 +:10B200000101010100000101000000000000000038 +:10B21000000000000000000000000000000000002E +:10B22000000000000000000000000000000000001E +:10B23000000000000000000000000000000000000E +:10B2400000000000000000000101010101010101F6 +:10B2500001010101010101010000000000000000E6 +:10B2600000000000000000000000000000000000DE +:10B2700000000000000000000000000000000000CE +:10B2800000000000000000000000000000000000BE +:10B29000000000000000000002020202020202029E +:10B2A000020202020202020200000000000000008E +:10B2B000000000000000000000000000000000008E +:10B2C000000000000000000000000000000000007E +:10B2D000000000000000000000000000000000006E +:10B2E0000000000000000000000202020202020250 +:10B2F000020002020202020001010101010101013A +:10B300000101010101010101000000000000000035 +:10B31000000000000000000000000000000000002D +:10B32000000000000000000000000000000000001D +:10B33000000000000000000000000000000000000D +:10B3400000000000000000000101010101010101F5 +:10B3500001010101010101010000000000000000E5 +:10B3600000000000000000000000000000000000DD +:10B3700000000000000000000000000000000000CD +:10B3800000000000000000000000000000000000BD +:10B39000000000000000000002020202020202029D +:10B3A000020202020202020200000000000000008D +:10B3B000000000000000000000000000000000008D +:10B3C000000000000000000000000000000000007D +:10B3D000000000000000000000000000000000006D +:10B3E000000000000000000000020202020202024F +:10B3F000000002020202020001010101010101013B +:10B400000101010101010101000000000000000034 +:10B41000000000000000000000000000000000002C +:10B42000000000000000000000000000000000001C +:10B43000000000000000000000000000000000000C +:10B4400000000000000000000101010101010101F4 +:10B4500001010101010101010000000000000000E4 +:10B4600000000000000000000000000000000000DC +:10B4700000000000000000000000000000000000CC +:10B4800000000000000000000000000000000000BC +:10B4900000000000000000000202020000020202A0 +:10B4A0000000020202020202000000000000000090 +:10B4B000000000000000000000000000000000008C +:10B4C000000000000000000000000000000000007C +:10B4D000000000000000000000000000000000006C +:10B4E000000000000000000000020202020202024E +:10B4F000000002020202020001010101010101013A +:10B500000101010101010101000000000000000033 +:10B51000000000000000000000000000000000002B +:10B52000000000000000000000000000000000001B +:10B53000000000000000000000000000000000000B +:10B5400000000000000000000101010101010101F3 +:10B5500001010101010101010000000000000000E3 +:10B5600000000000000000000000000000000000DB +:10B5700000000000000000000000000000000000CB +:10B5800000000000000000000000000000000000BB +:10B5900000000000000000000101010101010101A3 +:10B5A0000101010101010101000000000000000093 +:10B5B000000000000000000000000000000000008B +:10B5C000000000000000000000000000000000007B +:10B5D000000000000000000000000000000000006B +:10B5E000000000000000000000000202020202024F +:10B5F000000002000202020001010101010101013B +:10B600000101010101010101000000000000000032 +:10B61000000000000000000000000000000000002A +:10B62000000000000000000000000000000000001A +:10B63000000000000000000000000000000000000A +:10B6400000000000000000000202020202020202EA +:10B6500002020202020202020000000000000000DA +:10B6600000000000000000000000000000000000DA +:10B6700000000000000000000000000000000000CA +:10B6800000000000000000000000000000000000BA +:10B6900000000000000000000101010101010101A2 +:10B6A0000101010101010101000000000000000092 +:10B6B000000000000000000000000000000000008A +:10B6C000000000000000000000000000000000007A +:10B6D000000000000000000000000000000000006A +:10B6E0000000000000000000000002000000020254 +:10B6F0000000000000000200000000000000000048 +:10B700000000000000000000000000000000000039 +:10B710000000000000000000000000000000000029 +:10B720000000000000000000000000000000000019 +:10B730000000000000000000000000000000000009 +:10B7400000000000000000000000000000000000F9 +:10B7500000000000000000000000000000000000E9 +:10B7600000000000000000000000000000000000D9 +:10B7700000000000000000000000000000000000C9 +:10B7800000000000000000000000000000000000B9 +:10B7900000000000000000000000000000000000A9 +:10B7A0000000000000000000000000000000000099 +:10B7B0000000000000000000000000000000000089 +:10B7C0000000000000000000000000000000000079 +:10B7D0000000000000000000000000000000000069 +:10B7E0000000000000000000000000000000000059 +:10B7F00000000000000000001E000000000000002B +:10B800000100010000010000000001000001010131 +:10B810000000000000000000000000000000000028 +:10B820000000000000000000000000000000000018 +:10B830000000000000000000000000000000000008 +:10B8400000000000000000000000000000000000F8 +:10B8500000000000000000000000000000010100E6 +:10B8600000000000000000000000000000000000D8 +:10B8700000000000000000000000000000000000C8 +:10B8800000000000000000000000000000000000B8 +:10B8900000000000000000000000000000000000A8 +:10B8A0000000000000000000000000000000000098 +:10B8B0000000000000000000000000000000000088 +:10B8C0000000000000000000000000000000000078 +:10B8D0000000000000000000000000000000000068 +:10B8E0000000000000000000000000000000000058 +:10B8F0000000000000000000000000000000000048 +:10B900000101020101010101010101010101010126 +:10B910000000000000000000000000000000000027 +:10B920000000000000000000000000000000000017 +:10B930000000000000000000000000000000000007 +:10B9400000000000000000000000000000000000F7 +:10B9500000000000000000000000000000010100E5 +:10B9600000000000000000000000000000000000D7 +:10B9700000000000000000000000000000000000C7 +:10B9800000000000000000000000000000000000B7 +:10B9900000000000000000000000000000000000A7 +:10B9A0000000000000000000000000000001010194 +:10B9B0000000000000000000000000000000000087 +:10B9C0000000000000000000000000000000000077 +:10B9D0000000000000000000000000000000000067 +:10B9E0000000000000000000000000000000000057 +:10B9F0000000000000000000000000000001010045 +:10BA00000202020202020101010101010101010120 +:10BA10000000000000000000000000000000000026 +:10BA20000000000000000000000000000000000016 +:10BA30000000000000000000000000000000000006 +:10BA400000000000000000000000000000000000F6 +:10BA500000000000000000000000000000010100E4 +:10BA600000000000000000000000000000000000D6 +:10BA700000000000000000000000000000000000C6 +:10BA800000000000000000000000000000000000B6 +:10BA900000000000000000000000000000000000A6 +:10BAA0000000000000000000000000010101010191 +:10BAB0000000000000000000000000000000000086 +:10BAC0000000000000000000000000000000000076 +:10BAD0000000000000000000000000000000000066 +:10BAE0000000000000000000000000000000000056 +:10BAF0000000000000000000000000010101010141 +:10BB0000020202020202010102020201010101011C +:10BB10000000000000000000000000000000000025 +:10BB20000000000000000000000000000000000015 +:10BB30000000000000000000000000000000000005 +:10BB400000000000000000000000000000000000F5 +:10BB500000000000000000000000000100010100E2 +:10BB600000000000000000000000000000000000D5 +:10BB700000000000000000000000000000000000C5 +:10BB800000000000000000000000000000000000B5 +:10BB900000000000000000000000000000000000A5 +:10BBA0000000000000000000000000010101010190 +:10BBB0000000000000000000000000000000000085 +:10BBC0000000000000000000000000000000000075 +:10BBD0000000000000000000000000000000000065 +:10BBE0000000000000000000000000000000000055 +:10BBF000000001000000000000000101010101013E +:10BC00000202020202020202020202010101010119 +:10BC10000000000000000000000000000000000024 +:10BC20000000000000000000000000000000000014 +:10BC30000000000000000000000000000000000004 +:10BC400000000000000000000000000000000000F4 +:10BC500000000000000000000000000100010101E0 +:10BC600000000000000000000000000000000000D4 +:10BC700000000000000000000000000000000000C4 +:10BC800000000000000000000000000000000000B4 +:10BC900000000000000000000000000000000000A4 +:10BCA000000000000000000000000001010101018F +:10BCB0000000000000000000000000000000000084 +:10BCC0000000000000000000000000000000000074 +:10BCD0000000000000000000000000000000000064 +:10BCE0000000000000000000000000000000000054 +:10BCF0000001010000000101010101010101010138 +:10BD00000202020202020202020202010101010019 +:10BD10000000000000000000000000000000000023 +:10BD20000000000000000000000000000000000013 +:10BD30000000000000000000000000000000000003 +:10BD400000000000000000000000000000000000F3 +:10BD500000000000000000000000000101010101DE +:10BD600000000000000000000000000000000000D3 +:10BD700000000000000000000000000000000000C3 +:10BD800000000000000000000000000000000000B3 +:10BD900000000000000000000000000000000000A3 +:10BDA000000000000000000000000001010101018E +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:10BDD0000000000000000000000000000000000063 +:10BDE0000000000000000000000000000000000053 +:10BDF0000001010000010101010101010101010136 +:10BE00000202020202020202020202010201010017 +:10BE10000000000000000000000000000000000022 +:10BE20000000000000000000000000000000000012 +:10BE30000000000000000000000000000000000002 +:10BE400000000000000000000000000000000000F2 +:10BE500000000000000000000000010101010101DC +:10BE600000000000000000000000000000000000D2 +:10BE700000000000000000000000000000000000C2 +:10BE800000000000000000000000000000000000B2 +:10BE900000000000000000000000000000000000A2 +:10BEA000000000000000000000000001010101018D +:10BEB0000000000000000000000000000000000082 +:10BEC0000000000000000000000000000000000072 +:10BED0000000000000000000000000000000000062 +:10BEE0000000000000000000000000000000000052 +:10BEF0000001010101010101010101010101010133 +:10BF00000202020202020202020202020202010014 +:10BF10000000000000000000000000000000000021 +:10BF20000000000000000000000000000000000011 +:10BF30000000000000000000000000000000000001 +:10BF400000000000000000000000000000000000F1 +:10BF500000000000000000000000010101010101DB +:10BF600000000000000000000000000000000000D1 +:10BF700000000000000000000000000000000000C1 +:10BF800000000000000000000000000000000000B1 +:10BF900000000000000000000000000000000000A1 +:10BFA000000000000000000000000101010101018B +:10BFB0000000000000000000000000000000000081 +:10BFC0000000000000000000000000000000000071 +:10BFD0000000000000000000000000000000000061 +:10BFE0000000000000000000000000000000000051 +:10BFF0000000000101010101010101010101010134 +:10C000000202020202020202020202020202020012 +:10C010000000000000000000000000000000000020 +:10C020000000000000000000000000000000000010 +:10C030000000000000000000000000000000000000 +:10C0400000000000000000000000000000000000F0 +:10C0500001000000000000000000010101010101D9 +:10C0600000000000000000000000000000000000D0 +:10C0700000000000000000000000000000000000C0 +:10C0800000000000000000000000000000000000B0 +:10C0900000000000000000000000000000000000A0 +:10C0A0000001000000000101010101010101010185 +:10C0B0000000000000000000000000000000000080 +:10C0C0000000000000000000000000000000000070 +:10C0D0000000000000000000000000000000000060 +:10C0E0000000000000000000000000000000000050 +:10C0F0000000000101010101010101010101010133 +:10C100000202020202020202020202020202020011 +:10C11000000000000000000000000000000000001F +:10C12000000000000000000000000000000000000F +:10C1300000000000000000000000000000000000FF +:10C1400000000000000000000000000000000000EF +:10C1500001010000000000000000010101010101D7 +:10C1600000000000000000000000000000000000CF +:10C1700000000000000000000000000000000000BF +:10C1800000000000000000000000000000000000AF +:10C19000000000000000000000000000000000009F +:10C1A0000101000000010101010101010101010182 +:10C1B000000000000000000000000000000000007F +:10C1C000000000000000000000000000000000006F +:10C1D000000000000000000000000000000000005F +:10C1E000000000000000000000000000000000004F +:10C1F000000000000000000000000000000000013E +:10C200000202020202020202020202020202020010 +:10C21000000000000000000000000000000000001E +:10C22000000000000000000000000000000000000E +:10C2300000000000000000000000000000000000FE +:10C2400000000000000000000000000000000000EE +:10C2500002010000000000000100010101010101D4 +:10C2600000000000000000000000000000000000CE +:10C2700000000000000000000000000000000000BE +:10C2800000000000000000000000000000000000AE +:10C29000000000000000000000000000000000009E +:10C2A000010100010101010101010101010101017F +:10C2B000000000000000000000000000000000007E +:10C2C000000000000000000000000000000000006E +:10C2D000000000000000000000000000000000005E +:10C2E000000000000000000000000000000000004E +:10C2F000010000000000000000000000000000003D +:10C300000202010101010202010101020202020016 +:10C31000000000000000000000000000000000001D +:10C32000000000000000000000000000000000000D +:10C3300000000000000000000000000000000000FD +:10C3400000000000000000000000000000000000ED +:10C3500002010000000000000100010101020201D1 +:10C3600000000000000000000000000000000000CD +:10C3700000000000000000000000000000000000BD +:10C3800000000000000000000000000000000000AD +:10C39000000000000000000000000000000000009D +:10C3A000010101010101010101010101010101017D +:10C3B000000000000000000000000000000000007D +:10C3C000000000000000000000000000000000006D +:10C3D000000000000000000000000000000000005D +:10C3E000000000000000000000000000000000004D +:10C3F000010000000000000000000000000000003C +:10C400000201010101010101010101020202020018 +:10C41000000000000000000000000000000000001C +:10C42000000000000000000000000000000000000C +:10C4300000000000000000000000000000000000FC +:10C4400000000000000000000000000000000000EC +:10C4500002020100000000000200020201020201CB +:10C4600000000000000000000000000000000000CC +:10C4700000000000000000000000000000000000BC +:10C4800000000000000000000000000000000000AC +:10C49000000000000000000000000000000000009C +:10C4A000020101010101010101010101010101017B +:10C4B000000000000000000000000000000000007C +:10C4C000000000000000000000000000000000006C +:10C4D000000000000000000000000000000000005C +:10C4E000000000000000000000000000000000004C +:10C4F000020000000000000000000000000000003A +:10C500000201010101010101010101020102020018 +:10C51000000000000000000000000000000000001B +:10C52000000000000000000000000000000000000B +:10C5300000000000000000000000000000000000FB +:10C5400000000000000000000000000000000000EB +:10C5500002020101000100000200020202020202C6 +:10C5600000000000000000000000000000000000CB +:10C5700000000000000000000000000000000000BB +:10C5800000000000000000000000000000000000AB +:10C59000000000000000000000000000000000009B +:10C5A0000202010101010101010101020202020274 +:10C5B000000000000000000000000000000000007B +:10C5C000000000000000000000000000000000006B +:10C5D000000000000000000000000000000000005B +:10C5E000000000000000000000000000000000004B +:10C5F0000200000000000000000000000000000039 +:10C600000201010101010101010101010101020019 +:10C61000000000000000000000000000000000001A +:10C62000000000000000000000000000000000000A +:10C6300000000000000000000000000000000000FA +:10C6400000000000000000000000000000000000EA +:10C6500002020201000100000200020202020202C4 +:10C6600000000000000000000000000000000000CA +:10C6700000000000000000000000000000000000BA +:10C6800000000000000000000000000000000000AA +:10C69000000000000000000000000000000000009A +:10C6A0000202010101010101010101020202020273 +:10C6B000000000000000000000000000000000007A +:10C6C000000000000000000000000000000000006A +:10C6D000000000000000000000000000000000005A +:10C6E000000000000000000000000000000000004A +:10C6F0000202020000000000000000000000000034 +:10C700000201010101010101010101010101010019 +:10C710000000000000000000000000000000000019 +:10C720000000000000000000000000000000000009 +:10C7300000000000000000000000000000000000F9 +:10C7400000000000000000000000000000000000E9 +:10C7500002020202010201000200020202020202BF +:10C7600000000000000000000000000000000000C9 +:10C7700000000000000000000000000000000000B9 +:10C7800000000000000000000000000000000000A9 +:10C790000000000000000000000000000000000099 +:10C7A0000202020202020202020202020202020269 +:10C7B0000000000000000000000000000000000079 +:10C7C0000000000000000000000000000000000069 +:10C7D0000000000000000000000000000000000059 +:10C7E0000000000000000000000000000000000049 +:10C7F0000202020000000000000000000000000033 +:10C800000101010101010101010101010101010019 +:10C810000000000000000000000000000000000018 +:10C820000000000000000000000000000000000008 +:10C8300000000000000000000000000000000000F8 +:10C8400000000000000000000000000000000000E8 +:10C8500002020202020201000100020202020202BE +:10C8600000000000000000000000000000000000C8 +:10C8700000000000000000000000000000000000B8 +:10C8800000000000000000000000000000000000A8 +:10C890000000000000000000000000000000000098 +:10C8A0000202020202020202020202020202020268 +:10C8B0000000000000000000000000000000000078 +:10C8C0000000000000000000000000000000000068 +:10C8D0000000000000000000000000000000000058 +:10C8E0000000000000000000000000000000000048 +:10C8F0000202020202020202020202020202020218 +:10C90000010100000000010100000001010101001F +:10C910000000000000000000000000000000000017 +:10C920000000000000000000000000000000000007 +:10C9300000000000000000000000000000000000F7 +:10C9400000000000000000000000000000000000E7 +:10C9500002020202020202010100020202020202BB +:10C9600000000000000000000000000000000000C7 +:10C9700000000000000000000000000000000000B7 +:10C9800000000000000000000000000000000000A7 +:10C990000000000000000000000000000000000097 +:10C9A0000202020202020202020202020202020267 +:10C9B0000000000000000000000000000000000077 +:10C9C0000000000000000000000000000000000067 +:10C9D0000000000000000000000000000000000057 +:10C9E0000000000000000000000000000000000047 +:10C9F0000202020202020202020202020202020217 +:10CA00000100000000000000000000010001010022 +:10CA10000000000000000000000000000000000016 +:10CA20000000000000000000000000000000000006 +:10CA300000000000000000000000000000000000F6 +:10CA400000000000000000000000000000000000E6 +:10CA500002020202020202020200020202020202B8 +:10CA600000000000000000000000000000000000C6 +:10CA700000000000000000000000000000000000B6 +:10CA800000000000000000000000000000000000A6 +:10CA90000000000000000000000000000000000096 +:10CAA0000202020202020202020202020202020266 +:10CAB0000000000000000000000000000000000076 +:10CAC0000000000000000000000000000000000066 +:10CAD0000000000000000000000000000000000056 +:10CAE0000000000000000000000000000000000046 +:10CAF0000202020202020202020202020202020216 +:10CB00000100000000000000000000000000000024 +:10CB10000000000000000000000000000000000015 +:10CB20000000000000000000000000000000000005 +:10CB300000000000000000000000000000000000F5 +:10CB400000000000000000000000000000000000E5 +:10CB500002020202020202020202010202020202B6 +:10CB600000000000000000000000000000000000C5 +:10CB700000000000000000000000000000000000B5 +:10CB800000000000000000000000000000000000A5 +:10CB90000000000000000000000000000000000095 +:10CBA0000202020202020202020202020202020265 +:10CBB0000000000000000000000000000000000075 +:10CBC0000000000000000000000000000000000065 +:10CBD0000000000000000000000000000000000055 +:10CBE0000000000000000000000000000000000045 +:10CBF0000202020202020202020202020202020215 +:10CC00000100000000000000000000000000000023 +:10CC10000000000000000000000000000000000014 +:10CC20000000000000000000000000000000000004 +:10CC300000000000000000000000000000000000F4 +:10CC400000000000000000000000000000000000E4 +:10CC500002020202020102020002010202020202B8 +:10CC600000000000000000000000000000000000C4 +:10CC700000000000000000000000000000000000B4 +:10CC800000000000000000000000000000000000A4 +:10CC90000000000000000000000000000000000094 +:10CCA0000202020202020202020202020202020264 +:10CCB0000000000000000000000000000000000074 +:10CCC0000000000000000000000000000000000064 +:10CCD0000000000000000000000000000000000054 +:10CCE0000000000000000000000000000000000044 +:10CCF0000202020202020202020202020202020214 +:10CD00000100000000000000000000000000000022 +:10CD10000000000000000000000000000000000013 +:10CD20000000000000000000000000000000000003 +:10CD300000000000000000000000000000000000F3 +:10CD400000000000000000000000000000000000E3 +:10CD500001010101010201010001020101010101C2 +:10CD600000000000000000000000000000000000C3 +:10CD700000000000000000000000000000000000B3 +:10CD800000000000000000000000000000000000A3 +:10CD90000000000000000000000000000000000093 +:10CDA0000202020202020202020202020202020263 +:10CDB0000000000000000000000000000000000073 +:10CDC0000000000000000000000000000000000063 +:10CDD0000000000000000000000000000000000053 +:10CDE0000000000000000000000000000000000043 +:10CDF0000202020202020202020202020202020213 +:10CE0000000001010101000001010100000000001B +:10CE10000000000000000000000000000000000012 +:10CE20000000000000000000000000000000000002 +:10CE300000000000000000000000000000000000F2 +:10CE400000000000000000000000000000000000E2 +:10CE500002020202020002020002020202020202B6 +:10CE600000000000000000000000000000000000C2 +:10CE700000000000000000000000000000000000B2 +:10CE800000000000000000000000000000000000A2 +:10CE90000000000000000000000000000000000092 +:10CEA0000202020202020202020202020202020262 +:10CEB0000000000000000000000000000000000072 +:10CEC0000000000000000000000000000000000062 +:10CED0000000000000000000000000000000000052 +:10CEE0000000000000000000000000000000000042 +:10CEF0000202020202020202020202020202020212 +:10CF00000101010101010101010101000100000015 +:10CF10000000000000000000000000000000000011 +:10CF20000000000000000000000000000000000001 +:10CF300000000000000000000000000000000000F1 +:10CF400000000000000000000000000000000000E1 +:10CF500000000000000000000000000000000000D1 +:10CF600000000000000000000000000000000000C1 +:10CF700000000000000000000000000000000000B1 +:10CF800000000000000000000000000000000000A1 +:10CF90000000000000000000000000000000000091 +:10CFA0000202020202020202020202020202020261 +:10CFB0000000000000000000000000000000000071 +:10CFC0000000000000000000000000000000000061 +:10CFD0000000000000000000000000000000000051 +:10CFE0000000000000000000000000000000000041 +:10CFF0000202020202020202020202020202020211 +:10D000000101010101010101010101010101010110 +:10D010000000000000000000000000000000000010 +:10D020000000000000000000000000000000000000 +:10D0300000000000000000000000000000000000F0 +:10D0400000000000000000000000000000000000E0 +:10D0500001010101010101010101010101010101C0 +:10D0600000000000000000000000000000000000C0 +:10D0700000000000000000000000000000000000B0 +:10D0800000000000000000000000000000000000A0 +:10D090000000000000000000000000000000000090 +:10D0A0000202020202020202020202020202020260 +:10D0B0000000000000000000000000000000000070 +:10D0C0000000000000000000000000000000000060 +:10D0D0000000000000000000000000000000000050 +:10D0E0000000000000000000000000000000000040 +:10D0F0000000000000000000000000000000000030 +:10D10000010101010101010101010101010101010F +:10D11000000000000000000000000000000000000F +:10D1200000000000000000000000000000000000FF +:10D1300000000000000000000000000000000000EF +:10D1400000000000000000000000000000000000DF +:10D1500001010101010101010101010101010101BF +:10D1600000000000000000000000000000000000BF +:10D1700000000000000000000000000000000000AF +:10D18000000000000000000000000000000000009F +:10D19000000000000000000000000000000000008F +:10D1A000010101010101010101010101010101016F +:10D1B000000000000000000000000000000000006F +:10D1C000000000000000000000000000000000005F +:10D1D000000000000000000000000000000000004F +:10D1E000000000000000000000000000000000003F +:10D1F000000000000000000000000000000000002F +:10D20000010101010101010101010101010101010E +:10D21000000000000000000000000000000000000E +:10D2200000000000000000000000000000000000FE +:10D2300000000000000000000000000000000000EE +:10D2400000000000000000000000000000000000DE +:10D2500001010101010101010101010101010101BE +:10D2600000000000000000000000000000000000BE +:10D2700000000000000000000000000000000000AE +:10D28000000000000000000000000000000000009E +:10D29000000000000000000000000000000000008E +:10D2A000010101010101010101010101010101016E +:10D2B000000000000000000000000000000000006E +:10D2C000000000000000000000000000000000005E +:10D2D000000000000000000000000000000000004E +:10D2E000000000000000000000000000000000003E +:10D2F000000000000000000000000000000000002E +:10D30000010101010101010101010101010101010D +:10D31000000000000000000000000000000000000D +:10D3200000000000000000000000000000000000FD +:10D3300000000000000000000000000000000000ED +:10D3400000000000000000000000000000000000DD +:10D3500001010101010101010101010101010101BD +:10D3600000000000000000000000000000000000BD +:10D3700000000000000000000000000000000000AD +:10D38000000000000000000000000000000000009D +:10D39000000000000000000000000000000000008D +:10D3A000010101010101010101010101010101016D +:10D3B000000000000000000000000000000000006D +:10D3C000000000000000000000000000000000005D +:10D3D000000000000000000000000000000000004D +:10D3E000000000000000000000000000000000003D +:10D3F000000000000000000000000000000000002D +:10D40000010101010101010101010101010101010C +:10D41000000000000000000000000000000000000C +:10D4200000000000000000000000000000000000FC +:10D4300000000000000000000000000000000000EC +:10D4400000000000000000000000000000000000DC +:10D4500002020202020202020202020202020202AC +:10D4600000000000000000000000000000000000BC +:10D4700000000000000000000000000000000000AC +:10D48000000000000000000000000000000000009C +:10D49000000000000000000000000000000000008C +:10D4A000020202020202020202020202020202025C +:10D4B000000000000000000000000000000000006C +:10D4C000000000000000000000000000000000005C +:10D4D000000000000000000000000000000000004C +:10D4E000000000000000000000000000000000003C +:10D4F000000000000000000000000000000000002C +:10D50000000000000000000000000000000000001B +:10D51000000000000000000000000000000000000B +:10D5200000000000000000000000000000000000FB +:10D5300000000000000000000000000000000000EB +:10D5400000000000000000000000000000000000DB +:10D5500000000000000000000000000000000000CB +:10D5600000000000000000000000000000000000BB +:10D5700000000000000000000000000000000000AB +:10D58000000000000000000000000000000000009B +:10D59000000000000000000000000000000000008B +:10D5A000000000000000000000000000000000007B +:10D5B000000000000000000000000000000000006B +:10D5C000000000000000000000000000000000005B +:10D5D000000000000000000000000000000000004B +:10D5E000000000000000000000000000000000003B +:10D5F000000000000000000000000000000000002B +:10D600001E000000000000000001010000000000FA +:10D610000000000000010001000000000000000008 +:10D6200000000000000000000000000000000000FA +:10D6300000000000000000000000000000000000EA +:10D6400000000000000000000000000000000000DA +:10D6500000000000000000000000000000000000CA +:10D6600000000000000000000000000000000000BA +:10D6700000000000000000000000000000000000AA +:10D68000000000000000000000000000000000009A +:10D69000000000000000000000000000000000008A +:10D6A000000000000000000000000000000000007A +:10D6B000000000000000000000000000000000006A +:10D6C000000000000000000000000000000000005A +:10D6D000000000000000000000000000000000004A +:10D6E000000000000000000000000000000000003A +:10D6F0000000000000000000000000000000020226 +:10D700000002000000000200000101000000010012 +:10D710000000000000010001000000000000000007 +:10D7200000000000000000000000000000000000F9 +:10D7300000000000000000000000000000000000E9 +:10D7400000000000000000000000000000000000D9 +:10D7500000000000000000000000000001000000C8 +:10D7600000000000010100010000000000000000B6 +:10D7700000000000000000000000000000000000A9 +:10D780000000000000000000000000000000000099 +:10D790000000000000000000000000000000000089 +:10D7A0000000000000000000000000000000000079 +:10D7B0000000000000000000000000000000000069 +:10D7C0000000000000000000000000000000000059 +:10D7D0000000000000000000000000000000000049 +:10D7E0000000000000000000000000000000000039 +:10D7F0000000000000000000000000000002020223 +:10D800000002020201010100010102010100010008 +:10D810000000000001010001000000000000000005 +:10D8200000000000000000000000000000000000F8 +:10D8300000000000000000000000000000000000E8 +:10D8400000000000000000000000000000000000D8 +:10D8500000000000000000000000000001000000C7 +:10D8600001000000010101010000000000000000B3 +:10D8700000000000000000000000000000000000A8 +:10D880000000000000000000000000000000000098 +:10D890000000000000000000000000000000000088 +:10D8A0000000000000000000000000000100000077 +:10D8B0000000000000000000000000000000000068 +:10D8C0000000000000000000000000000000000058 +:10D8D0000000000000000000000000000000000048 +:10D8E0000000000000000000000000000000000038 +:10D8F0000000000000000000000002000002010221 +:10D900000101020101010100010202010100010007 +:10D910000001000001010001000000000000000003 +:10D9200000000000000000000000000000000000F7 +:10D9300000000000000000000000000000000000E7 +:10D9400000000000000000000000000000000000D7 +:10D9500000000000000000000000000001000000C6 +:10D9600001000000010101010000000000000000B2 +:10D9700000000000000000000000000000000000A7 +:10D980000000000000000000000000000000000097 +:10D990000000000000000000000000000000000087 +:10D9A0000000000000000000000000000100000076 +:10D9B0000100000000000000000000000000000066 +:10D9C0000000000000000000000000000000000057 +:10D9D0000000000000000000000000000000000047 +:10D9E0000000000000000000000000000000000037 +:10D9F000000000000000000000000202010201011E +:10DA00000101010101010100020202010100010006 +:10DA10000001010101010000000000000000000001 +:10DA200000000000000000000000000000000000F6 +:10DA300000000000000000000000000000000000E6 +:10DA400000000000000000000000000000000000D6 +:10DA500000000000000000000000000001000000C5 +:10DA600001000000010101010000000000000000B1 +:10DA700000000000000000000000000000000000A6 +:10DA80000000000000000000000000000000000096 +:10DA90000000000000000000000000000000000086 +:10DAA0000000000000000000000000000100000075 +:10DAB0000100000001010000000000000000000063 +:10DAC0000000000000000000000000000000000056 +:10DAD0000000000000000000000000000000000046 +:10DAE0000000000000000000000000000000000036 +:10DAF000000000000000000000000201010101011F +:10DB00000101010101010100020202010100020004 +:10DB100001020101010101000000000000000000FD +:10DB200000000000000000000000000000000000F5 +:10DB300000000000000000000000000000000000E5 +:10DB400000000000000000000000000000000000D5 +:10DB500000000000000000000000000101000000C3 +:10DB600001000101010101010000000000000000AE +:10DB700000000000000000000000000000000000A5 +:10DB80000000000000000000000000000000000095 +:10DB90000000000000000000000000000000000085 +:10DBA0000000000000000000000000000100000074 +:10DBB0000100000001010000000000000000000062 +:10DBC0000000000000000000000000000000000055 +:10DBD0000000000000000000000000000000000045 +:10DBE0000000000000000000000000000000000035 +:10DBF000000000000000000000020201010101011C +:10DC00000101010101010101020202020100020001 +:10DC100001020101010101000000000000000000FC +:10DC200000000000000000000000000000000000F4 +:10DC300000000000000000000000000000000000E4 +:10DC400000000000000000000000000000000000D4 +:10DC500000000000000000000000000101000000C2 +:10DC600001000101010101010000000000000000AD +:10DC700000000000000000000000000000000000A4 +:10DC80000000000000000000000000000000000094 +:10DC90000000000000000000000000000000000084 +:10DCA0000000000000000000000000000100000073 +:10DCB0000100000001010001000000000000000060 +:10DCC0000000000000000000000000000000000054 +:10DCD0000000000000000000000000000000000044 +:10DCE0000000000000000000000000000000000034 +:10DCF000000000000000000000020101010101011C +:10DD000001010101010101010202020201000201FF +:10DD100001020202010101000000000000000000F9 +:10DD200000000000000000000000000000000000F3 +:10DD300000000000000000000000000000000000E3 +:10DD400000000000000000000000000000000000D3 +:10DD500000000000000000000001000101000000C0 +:10DD600001000101010101010000000000000000AC +:10DD700000000000000000000000000000000000A3 +:10DD80000000000000000000000000000000000093 +:10DD90000000000000000000000000000000000083 +:10DDA0000000000000000000000000000100000072 +:10DDB000010000000101010100000000000000005E +:10DDC0000000000000000000000000000000000053 +:10DDD0000000000000000000000000000000000043 +:10DDE0000000000000000000000000000000000033 +:10DDF000000000000000000000010101010101011C +:10DE000001010101010101010202020202020202FA +:10DE100001020202010201000000000000000000F7 +:10DE200000000000000000000000000000000000F2 +:10DE300000000000000000000000000000000000E2 +:10DE400000000000000000000000000000000000D2 +:10DE500000000000000000000001000101000101BD +:10DE600001010101010101010000000000000000AA +:10DE700000000000000000000000000000000000A2 +:10DE80000000000000000000000000000000000092 +:10DE90000000000000000000000000000000000082 +:10DEA000000000000000000001010001010200006C +:10DEB000010002000101010100000000000000005B +:10DEC0000000000000000000000000000000000052 +:10DED0000000000000000000000000000000000042 +:10DEE0000000000000000000000000000000000032 +:10DEF000000000000000000000010101010101011B +:10DF000001010101010101010202020202020202F9 +:10DF100001020202020201000000000000000000F5 +:10DF200000000000000000000000000000000000F1 +:10DF300000000000000000000000000000000000E1 +:10DF400000000000000000000000000000000000D1 +:10DF500000000000000000000101010101000101BA +:10DF600001010101010101010000000000000000A9 +:10DF700000000000000000000000000000000000A1 +:10DF80000000000000000000000000000000000091 +:10DF90000000000000000000000000000000000081 +:10DFA0000000000000000000020100010201010168 +:10DFB000010101000101010100000000000000005A +:10DFC0000000000000000000000000000000000051 +:10DFD0000000000000000000000000000000000041 +:10DFE0000000000000000000000000000000000031 +:10DFF000000000000000000000010100000100011D +:10E0000000000100000000010202020202020202FE +:10E0100002020202020202000000000000000000F2 +:10E0200000000000000000000000000000000000F0 +:10E0300000000000000000000000000000000000E0 +:10E0400000000000000000000000000000000000D0 +:10E0500000000000000000000101010102000101B8 +:10E0600001010101010101010000000000000000A8 +:10E0700000000000000000000000000000000000A0 +:10E080000000000000000000000000000000000090 +:10E090000000000000000000000000000000000080 +:10E0A0000000000000000000020201010201010165 +:10E0B0000201010101010101000000000000000057 +:10E0C0000000000000000000000000000000000050 +:10E0D0000000000000000000000000000000000040 +:10E0E0000000000000000000000000000000000030 +:10E0F0000000000000000000000000000000000020 +:10E1000000000000000000010202020202020202FE +:10E1100002020202020202000000000000000000F1 +:10E1200000000000000000000000000000000000EF +:10E1300000000000000000000000000000000000DF +:10E1400000000000000000000000000000000000CF +:10E1500000000000000000000202010202000101B4 +:10E1600002010101020202020000000000000000A2 +:10E17000000000000000000000000000000000009F +:10E18000000000000000000000000000000000008F +:10E19000000000000000000000000000000000007F +:10E1A0000000000000000000020202020202010260 +:10E1B0000202010102020101000000000000000053 +:10E1C000000000000000000000000000000000004F +:10E1D000000000000000000000000000000000003F +:10E1E000000000000000000000000000000000002F +:10E1F000000000000000000000000000000000001F +:10E2000000000000000000000202020202020202FE +:10E2100002020202020202000000000000000000F0 +:10E2200000000000000000000000000000000000EE +:10E2300000000000000000000000000000000000DE +:10E2400000000000000000000000000000000000CE +:10E2500000000000000000000202020202000101B2 +:10E26000020102020202020200000000000000009F +:10E27000000000000000000000000000000000009E +:10E28000000000000000000000000000000000008E +:10E29000000000000000000000000000000000007E +:10E2A000000000000000000002020202020202025E +:10E2B0000202010102020202000000000000000050 +:10E2C000000000000000000000000000000000004E +:10E2D000000000000000000000000000000000003E +:10E2E000000000000000000000000000000000002E +:10E2F000000000000000000000000000000000001E +:10E3000000000000000000000202010202020202FE +:10E3100002010202020202000000000000000000F0 +:10E3200000000000000000000000000000000000ED +:10E3300000000000000000000000000000000000DD +:10E3400000000000000000000000000000000000CD +:10E3500000000000000000000202020202010202AE +:10E36000020202020202020200000000000000009D +:10E37000000000000000000000000000000000009D +:10E38000000000000000000000000000000000008D +:10E39000000000000000000000000000000000007D +:10E3A000000000000000000002020202020202025D +:10E3B000020202020202020200000000000000004D +:10E3C000000000000000000000000000000000004D +:10E3D000000000000000000000000000000000003D +:10E3E000000000000000000000000000000000002D +:10E3F000000000000000000000000000000000001D +:10E400000000000000000000020101020201010101 +:10E4100002010101020202000000000000000000F1 +:10E4200000000000000000000000000000000000EC +:10E4300000000000000000000000000000000000DC +:10E4400000000000000000000000000000000000CC +:10E4500000000000000000000202020202010202AD +:10E46000020202020202020200000000000000009C +:10E47000000000000000000000000000000000009C +:10E48000000000000000000000000000000000008C +:10E49000000000000000000000000000000000007C +:10E4A000000000000000000002020202020202025C +:10E4B000020202020202020200000000000000004C +:10E4C000000000000000000000000000000000004C +:10E4D000000000000000000000000000000000003C +:10E4E000000000000000000000000000000000002C +:10E4F000000000000000000000000000000000001C +:10E500000000000000000000010101010201010102 +:10E5100002010101020202000000000000000000F0 +:10E5200000000000000000000000000000000000EB +:10E5300000000000000000000000000000000000DB +:10E5400000000000000000000000000000000000CB +:10E5500000000000000000000202020202020202AB +:10E56000020202020202020200000000000000009B +:10E57000000000000000000000000000000000009B +:10E58000000000000000000000000000000000008B +:10E59000000000000000000000000000000000007B +:10E5A000000000000000000002020202020102015D +:10E5B000020102020202020200000000000000004C +:10E5C000000000000000000000000000000000004B +:10E5D000000000000000000000000000000000003B +:10E5E000000000000000000000000000000000002B +:10E5F000000000000000000000000000000000001B +:10E600000000000000000000010101010101010102 +:10E6100001010101010101000000000000000000F3 +:10E6200000000000000000000000000000000000EA +:10E6300000000000000000000000000000000000DA +:10E6400000000000000000000000000000000000CA +:10E6500000000000000000000202020202020202AA +:10E66000020202020202020200000000000000009A +:10E67000000000000000000000000000000000009A +:10E68000000000000000000000000000000000008A +:10E69000000000000000000000000000000000007A +:10E6A000000000000000000002020202020102015C +:10E6B000020102020202020200000000000000004B +:10E6C000000000000000000000000000000000004A +:10E6D000000000000000000000000000000000003A +:10E6E000000000000000000000000000000000002A +:10E6F0000000000000000000020000020200020012 +:10E7000002020002020202000101010101010101F5 +:10E7100001010101010101000000000000000000F2 +:10E7200000000000000000000000000000000000E9 +:10E7300000000000000000000000000000000000D9 +:10E7400000000000000000000000000000000000C9 +:10E7500000000000000000000202020202020202A9 +:10E760000202020202020202000000000000000099 +:10E770000000000000000000000000000000000099 +:10E780000000000000000000000000000000000089 +:10E790000000000000000000000000000000000079 +:10E7A000000000000000000001010101010201025F +:10E7B0000102010101010101000000000000000050 +:10E7C0000000000000000000000000000000000049 +:10E7D0000000000000000000000000000000000039 +:10E7E0000000000000000000000000000000000029 +:10E7F000000000000000000002020002020202020B +:10E8000002020202020202000101000101010101F3 +:10E8100001000101010101000000000000000000F2 +:10E8200000000000000000000000000000000000E8 +:10E8300000000000000000000000000000000000D8 +:10E8400000000000000000000000000000000000C8 +:10E8500000000000000000000202020202020202A8 +:10E860000202020202020202000000000000000098 +:10E870000000000000000000000000000000000098 +:10E880000000000000000000000000000000000088 +:10E890000000000000000000000000000000000078 +:10E8A0000000000000000000020202020202020258 +:10E8B0000202020202020202000000000000000048 +:10E8C0000000000000000000000000000000000048 +:10E8D0000000000000000000000000000000000038 +:10E8E0000000000000000000000000000000000028 +:10E8F0000000000000000000020202020202020208 +:10E9000002020202020202020000000001000000F6 +:10E9100001000000010101000000000000000000F3 +:10E9200000000000000000000000000000000000E7 +:10E9300000000000000000000000000000000000D7 +:10E9400000000000000000000000000000000000C7 +:10E9500000000000000000000202020202020202A7 +:10E960000202020202020202000000000000000097 +:10E970000000000000000000000000000000000097 +:10E980000000000000000000000000000000000087 +:10E990000000000000000000000000000000000077 +:10E9A0000000000000000000000000000000000067 +:10E9B0000000000000000000000000000000000057 +:10E9C0000000000000000000000000000000000047 +:10E9D0000000000000000000000000000000000037 +:10E9E0000000000000000000000000000000000027 +:10E9F0000000000000000000020202020202020207 +:10EA000002020202020202020000000000000000F6 +:10EA100000000000000000000000000000000000F6 +:10EA200000000000000000000000000000000000E6 +:10EA300000000000000000000000000000000000D6 +:10EA400000000000000000000000000000000000C6 +:10EA500000000000000000000000000000000000B6 +:10EA600000000000000000000000000000000000A6 +:10EA70000000000000000000000000000000000096 +:10EA80000000000000000000000000000000000086 +:10EA90000000000000000000000000000000000076 +:10EAA0000000000000000000000000000000000066 +:10EAB0000000000000000000000000000000000056 +:10EAC0000000000000000000000000000000000046 +:10EAD0000000000000000000000000000000000036 +:10EAE0000000000000000000000000000000000026 +:10EAF0000000000000000000020202020202020206 +:10EB000002020202020202020000000000000000F5 +:10EB100000000000000000000000000000000000F5 +:10EB200000000000000000000000000000000000E5 +:10EB300000000000000000000000000000000000D5 +:10EB400000000000000000000000000000000000C5 +:10EB500000000000000000000000000000000000B5 +:10EB600000000000000000000000000000000000A5 +:10EB70000000000000000000000000000000000095 +:10EB80000000000000000000000000000000000085 +:10EB90000000000000000000000000000000000075 +:10EBA0000000000000000000000000000000000065 +:10EBB0000000000000000000000000000000000055 +:10EBC0000000000000000000000000000000000045 +:10EBD0000000000000000000000000000000000035 +:10EBE0000000000000000000000000000000000025 +:10EBF0000000000000000000020202020202020205 +:10EC000002020202020202020000000000000000F4 +:10EC100000000000000000000000000000000000F4 +:10EC200000000000000000000000000000000000E4 +:10EC300000000000000000000000000000000000D4 +:10EC400000000000000000000000000000000000C4 +:10EC500000000000000000000000000000000000B4 +:10EC600000000000000000000000000000000000A4 +:10EC70000000000000000000000000000000000094 +:10EC80000000000000000000000000000000000084 +:10EC90000000000000000000000000000000000074 +:10ECA0000000000000000000000000000000000064 +:10ECB0000000000000000000000000000000000054 +:10ECC0000000000000000000000000000000000044 +:10ECD0000000000000000000000000000000000034 +:10ECE0000000000000000000000000000000000024 +:10ECF0000000000000000000020202020202020204 +:10ED000002020202020202020000010000000000F2 +:10ED100000010000000000000000000000000000F2 +:10ED200000000000000000000000000000000000E3 +:10ED300000000000000000000000000000000000D3 +:10ED400000000000000000000000000000000000C3 +:10ED500000000000000000000000000000000000B3 +:10ED600000000000000000000000000000000000A3 +:10ED70000000000000000000000000000000000093 +:10ED80000000000000000000000000000000000083 +:10ED90000000000000000000000000000000000073 +:10EDA0000000000000000000000000000000000063 +:10EDB0000000000000000000000000000000000053 +:10EDC0000000000000000000000000000000000043 +:10EDD0000000000000000000000000000000000033 +:10EDE0000000000000000000000000000000000023 +:10EDF0000000000000000000020202020202020203 +:10EE000002020202020202020101010100010101EB +:10EE100000010101000000000000000000000000EF +:10EE200000000000000000000000000000000000E2 +:10EE300000000000000000000000000000000000D2 +:10EE400000000000000000000000000000000000C2 +:10EE500000000000000000000101010101010101AA +:10EE6000010101010101010100000000000000009A +:10EE70000000000000000000000000000000000092 +:10EE80000000000000000000000000000000000082 +:10EE90000000000000000000000000000000000072 +:10EEA0000000000000000000000000000000000062 +:10EEB0000000000000000000000000000000000052 +:10EEC0000000000000000000000000000000000042 +:10EED0000000000000000000000000000000000032 +:10EEE0000000000000000000000000000000000022 +:10EEF0000000000000000000000000000000000012 +:10EF000000000000000000000101010101010101F9 +:10EF100001010101010101010000000000000000E9 +:10EF200000000000000000000000000000000000E1 +:10EF300000000000000000000000000000000000D1 +:10EF400000000000000000000000000000000000C1 +:10EF500000000000000000000101010101010101A9 +:10EF60000101010101010101000000000000000099 +:10EF70000000000000000000000000000000000091 +:10EF80000000000000000000000000000000000081 +:10EF90000000000000000000000000000000000071 +:10EFA0000000000000000000000000000000000061 +:10EFB0000000000000000000000000000000000051 +:10EFC0000000000000000000000000000000000041 +:10EFD0000000000000000000000000000000000031 +:10EFE0000000000000000000000000000000000021 +:10EFF0000000000000000000000000000000000011 +:10F0000000000000000000000101010101010101F8 +:10F0100001010101010101010000000000000000E8 +:10F0200000000000000000000000000000000000E0 +:10F0300000000000000000000000000000000000D0 +:10F0400000000000000000000000000000000000C0 +:10F0500000000000000000000101010101010101A8 +:10F060000101010101010101000000000000000098 +:10F070000000000000000000000000000000000090 +:10F080000000000000000000000000000000000080 +:10F090000000000000000000000000000000000070 +:10F0A0000000000000000000010101010101010158 +:10F0B0000101010101010101000000000000000048 +:10F0C0000000000000000000000000000000000040 +:10F0D0000000000000000000000000000000000030 +:10F0E0000000000000000000000000000000000020 +:10F0F0000000000000000000000000000000000010 +:10F1000000000000000000000101010101010101F7 +:10F1100001010101010101010000000000000000E7 +:10F1200000000000000000000000000000000000DF +:10F1300000000000000000000000000000000000CF +:10F1400000000000000000000000000000000000BF +:10F1500000000000000000000101010101010101A7 +:10F160000101010101010101000000000000000097 +:10F17000000000000000000000000000000000008F +:10F18000000000000000000000000000000000007F +:10F19000000000000000000000000000000000006F +:10F1A0000000000000000000010101010101010157 +:10F1B0000101010101010101000000000000000047 +:10F1C000000000000000000000000000000000003F +:10F1D000000000000000000000000000000000002F +:10F1E000000000000000000000000000000000001F +:10F1F000000000000000000000000000000000000F +:10F2000000000000000000000101010101010101F6 +:10F2100001010101010101010000000000000000E6 +:10F2200000000000000000000000000000000000DE +:10F2300000000000000000000000000000000000CE +:10F2400000000000000000000000000000000000BE +:10F25000000000000000000002020202020202029E +:10F26000020202020202020200000000000000008E +:10F27000000000000000000000000000000000008E +:10F28000000000000000000000000000000000007E +:10F29000000000000000000000000000000000006E +:10F2A000000000000000000002020202020202024E +:10F2B000020202020202020200000000000000003E +:10F2C000000000000000000000000000000000003E +:10F2D000000000000000000000000000000000002E +:10F2E000000000000000000000000000000000001E +:10F2F000000000000000000000000000000000000E +:10F3000000000000000000000000000000000000FD +:10F3100000000000000000000000000000000000ED +:10F3200000000000000000000000000000000000DD +:10F3300000000000000000000000000000000000CD +:10F3400000000000000000000000000000000000BD +:10F3500000000000000000000000000000000000AD +:10F36000000000000000000000000000000000009D +:10F37000000000000000000000000000000000008D +:10F38000000000000000000000000000000000007D +:10F39000000000000000000000000000000000006D +:10F3A000000000000000000000000000000000005D +:10F3B000000000000000000000000000000000004D +:10F3C000000000000000000000000000000000003D +:10F3D000000000000000000000000000000000002D +:10F3E000000000000000000000000000000000001D +:10F3F000000000000000000000000000000000000D +:10F4000000000000000000001E00000000000000DE +:10F4100000000000010001010000010000010101E5 +:10F4200000000000000000000000000000000000DC +:10F4300000000000000000000000000000000000CC +:10F4400000000000000000000000000000000000BC +:10F4500000000000000000000000000000000000AC +:10F46000000000000000000000000000000000009C +:10F47000000000000000000000000000000000008C +:10F48000000000000000000000000000000000007C +:10F49000000000000000000000000000000000006C +:10F4A000000000000000000000000000000000005C +:10F4B000000000000000000000000000000000004C +:10F4C000000000000000000000000000000000003C +:10F4D000000000000000000000000000000000002C +:10F4E000000000000000000000000000000000001C +:10F4F000000000000000000000000000000000000C +:10F5000000000100000000000100000001000001F7 +:10F5100000000000020001010000010100010101E2 +:10F5200000000000000000000000000000000000DB +:10F5300000000000000000000000000000000000CB +:10F5400000000000000000000000000000000000BB +:10F5500000000000000000000000000000000000AB +:10F560000000000000000000000000000000010199 +:10F57000000000000000000000000000000000008B +:10F58000000000000000000000000000000000007B +:10F59000000000000000000000000000000000006B +:10F5A000000000000000000000000000000000005B +:10F5B000000000000000000000000000000000004B +:10F5C000000000000000000000000000000000003B +:10F5D000000000000000000000000000000000002B +:10F5E000000000000000000000000000000000001B +:10F5F000000000000000000000000000000000000B +:10F6000000000100010000000101000101000001F3 +:10F6100000000001020101010000010201020101DC +:10F6200000000000000000000000000000000000DA +:10F6300000000000000000000000000000000000CA +:10F6400000000000000000000000000000000000BA +:10F6500000000000000000000000000000000000AA +:10F660000000000000000000000000000000010198 +:10F67000000000000000000000000000000000008A +:10F68000000000000000000000000000000000007A +:10F69000000000000000000000000000000000006A +:10F6A000000000000000000000000000000000005A +:10F6B000000000000000000000000000000000004A +:10F6C000000000000000000000000000000000003A +:10F6D000000000000000000000000000000000002A +:10F6E000000000000000000000000000000000001A +:10F6F000000000000000000000000000000000000A +:10F7000000010100010000000101000101000001F1 +:10F7100000010101020101010000010201020101D9 +:10F7200000000000000000000000000000000000D9 +:10F7300000000000000000000000000000000000C9 +:10F7400000000000000000000000000000000000B9 +:10F7500000000000000000000000000000000000A9 +:10F760000000000000010000000000000000010196 +:10F770000000000000000000000000000000000089 +:10F780000000000000000000000000000000000079 +:10F790000000000000000000000000000000000069 +:10F7A0000000000000000000000000000000000059 +:10F7B0000000000000000000000000000000000049 +:10F7C0000000000000000000000000000000000039 +:10F7D0000000000000000000000000000000000029 +:10F7E0000000000000000000000000000000000019 +:10F7F0000000000000000000000000000000000009 +:10F8000000010100010000000101000101000001F0 +:10F8100000010101020101010000020202020100D7 +:10F8200000000000000000000000000000000000D8 +:10F8300000000000000000000000000000000000C8 +:10F8400000000000000000000000000000000000B8 +:10F8500000000000000000000000000000000000A8 +:10F860000000000000010000000000000000010195 +:10F870000000000000000000000000000000000088 +:10F880000000000000000000000000000000000078 +:10F890000000000000000000000000000000000068 +:10F8A0000000000000000000000000000000000058 +:10F8B0000000000000000000000000000000000048 +:10F8C0000000000000000000000000000000000038 +:10F8D0000000000000000000000000000000000028 +:10F8E0000000000000000000000000000000000018 +:10F8F0000000000000000000000000000000000008 +:10F9000000010100010000010101010101000001ED +:10F9100000020102020102020201020202020100CF +:10F9200000000000000000000000000000000000D7 +:10F9300000000000000000000000000000000000C7 +:10F9400000000000000000000000000000000000B7 +:10F9500000000000000000000000000000000000A7 +:10F960000000000000010000000001000000010193 +:10F970000000000000000000000000000000000087 +:10F980000000000000000000000000000000000077 +:10F990000000000000000000000000000000000067 +:10F9A0000000000000000000000000000000000057 +:10F9B0000000000000000000000000000000000047 +:10F9C0000000000000000000000000000000000037 +:10F9D0000000000000000000000000000000000027 +:10F9E0000000000000000000000000000000000017 +:10F9F0000000000000000000000000000000000007 +:10FA000000010100010000010101010101000001EC +:10FA100002020102020102020202020202020100CB +:10FA200000000000000000000000000000000000D6 +:10FA300000000000000000000000000000000000C6 +:10FA400000000000000000000000000000000000B6 +:10FA500000000000000000000000000000000000A6 +:10FA60000000010000010000000001000000010191 +:10FA70000000000000000000000000000000000086 +:10FA80000000000000000000000000000000000076 +:10FA90000000000000000000000000000000000066 +:10FAA0000000000000000000000000000000000056 +:10FAB0000000000000000000000000000000000046 +:10FAC0000000000000000000000000000000000036 +:10FAD0000000000000000000000000000000000026 +:10FAE0000000000000000000000000000000000016 +:10FAF0000000000000000000000000000000000006 +:10FB000000010100010000010101010101000001EB +:10FB100002020202020102020202020202020100C9 +:10FB200000000000000000000000000000000000D5 +:10FB300000000000000000000000000000000000C5 +:10FB400000000000000000000000000000000000B5 +:10FB500000000000000000000000000000000000A5 +:10FB6000000001000001010100000100000001018E +:10FB70000000000000000000000000000000000085 +:10FB80000000000000000000000000000000000075 +:10FB90000000000000000000000000000000000065 +:10FBA0000000000000000000000000000000000055 +:10FBB0000000000000000000000000000000000045 +:10FBC0000000000000000000000000000000000035 +:10FBD0000000000000000000000000000000000025 +:10FBE0000000000000000000000000000000000015 +:10FBF0000000000000000000000000000000000005 +:10FC000000010100010000010001010101000001EB +:10FC100002020202020202020202020202020200C6 +:10FC200000000000000000000000000000000000D4 +:10FC300000000000000000000000000000000000C4 +:10FC400000000000000000000000000000000000B4 +:10FC500000000000000000000000000000000000A4 +:10FC6000000101000001010100000100000001018C +:10FC70000000000000000000000000000000000084 +:10FC80000000000000000000000000000000000074 +:10FC90000000000000000000000000000000000064 +:10FCA0000000000000000000000000000000000054 +:10FCB0000000000000000000000000000000000044 +:10FCC0000000000000000000000000000000000034 +:10FCD0000000000000000000000000000000000024 +:10FCE0000000000000000000000000000000000014 +:10FCF0000000000000000000000000000000000004 +:10FD000000010100010101010001010001000001E9 +:10FD100002020202020202020202020202020200C5 +:10FD200000000000000000000000000000000000D3 +:10FD300000000000000000000000000000000000C3 +:10FD400000000000000000000000000000000000B3 +:10FD500000000000000000000000000000000000A3 +:10FD60000001010101010101000001000001010188 +:10FD70000000000000000000000000000000000083 +:10FD80000000000000000000000000000000000073 +:10FD90000000000000000000000000000000000063 +:10FDA0000000000000000000000000000000000053 +:10FDB0000000000000010000000000000000010140 +:10FDC0000000000000000000000000000000000033 +:10FDD0000000000000000000000000000000000023 +:10FDE0000000000000000000000000000000000013 +:10FDF0000000000000000000000000000000000003 +:10FE000000000100010101010001010001000001E9 +:10FE100002020202020202020202020202020200C4 +:10FE200000000000000000000000000000000000D2 +:10FE300000000000000000000000000000000000C2 +:10FE400000000000000000000000000000000000B2 +:10FE500000000000000000000000000000000000A2 +:10FE60000001010101010101010101010001010184 +:10FE70000000000000000000000000000000000082 +:10FE80000000000000000000000000000000000072 +:10FE90000000000000000000000000000000000062 +:10FEA0000000000000000000000000000000000052 +:10FEB000000001000001000000000000000001013E +:10FEC0000000000000000000000000000000000032 +:10FED0000000000000000000000000000000000022 +:10FEE0000000000000000000000000000000000012 +:10FEF0000000000000000000000000000000000002 +:10FF000000000101000101010000010000010101E8 +:10FF100002020202010202020202020102010200C6 +:10FF200000000000000000000000000000000000D1 +:10FF300000000000000000000000000000000000C1 +:10FF400000000000000000000000000000000000B1 +:10FF500000000000000000000000000000000000A1 +:10FF60000101010101010101010101010101010181 +:10FF70000000000000000000000000000000000081 +:10FF80000000000000000000000000000000000071 +:10FF90000000000000000000000000000000000061 +:10FFA0000000000000000000000000000000000051 +:10FFB000000001000001000000010000000001013C +:10FFC0000000000000000000000000000000000031 +:10FFD0000000000000000000000000000000000021 +:10FFE0000000000000000000000000000000000011 +:10FFF0000000000000000000000000000000000001 +:02000002D0002C +:1000000000000001020101010000010000010100E7 +:1000100002020202010202020102020101010200C7 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000101010101010101010101010101010180 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000010001010000000100000100010139 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000001020001020101010002000000010100E2 +:1001100002020202010202020101010101010200C8 +:1001200000000000000000000000000000000000CF +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000010101010102010101010101010102027C +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B0000000010101010101000100000100010135 +:1001C000000000000000000000000000000000002F +:1001D000000000000000000000000000000000001F +:1001E000000000000000000000000000000000000F +:1001F00000000000000000000000000000000000FF +:1002000001020001020101020002000000010102DE +:1002100002010201010201010101010101010200CB +:1002200000000000000000000000000000000000CE +:1002300000000000000000000000000000000000BE +:1002400000000000000000000000000000000000AE +:10025000000000000000000000000000000000009E +:100260000202020101020101010102010101020277 +:10027000000000000000000000000000000000007E +:10028000000000000000000000000000000000006E +:10029000000000000000000000000000000000005E +:1002A000000000000000000000000000000000004E +:1002B0000001010101010101000100010100010132 +:1002C000000000000000000000000000000000002E +:1002D000000000000000000000000000000000001E +:1002E000000000000000000000000000000000000E +:1002F00000000000000000000000000000000000FE +:1003000002020001020101020002020202010102D6 +:1003100001010101010201010101010101010200CC +:1003200000000000000000000000000000000000CD +:1003300000000000000000000000000000000000BD +:1003400000000000000000000000000000000000AD +:10035000000000000000000000000000000000009D +:100360000202020202020202010102010101020272 +:10037000000000000000000000000000000000007D +:10038000000000000000000000000000000000006D +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000010101010101010101010101010101012D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000002020202020202020002020202000102D1 +:1004100001010101010101010101010101010100CD +:1004200000000000000000000000000000000000CC +:1004300000000000000000000000000000000000BC +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000020202020202020202020202010202026D +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000010101010101010101010101010101012C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000002020202020202020002020202000102D0 +:1005100001010101000101010101010001000100CF +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000020202020202020202020202020202026B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B0000201020102020101010201010101010126 +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000002020202020202020202020202020202CA +:1006100001010101000101010000000000000100D2 +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000020202020202020202020202020202026A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000020202020202010101020102020102021F +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000002020202020202020202020202020202C9 +:1007100000000000000100000000000000000100D7 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000202020202020202020202020202020269 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B000020202020202020202020102020102021B +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F00000000000000000000000000000000000F9 +:1008000002020202020202020202020202020202C8 +:1008100000000000000000000000000000000000D8 +:1008200000000000000000000000000000000000C8 +:1008300000000000000000000000000000000000B8 +:1008400000000000000000000000000000000000A8 +:100850000000000000000000000000000000000098 +:100860000202020202020202020202020202020268 +:100870000000000000000000000000000000000078 +:100880000000000000000000000000000000000068 +:100890000000000000000000000000000000000058 +:1008A0000000000000000000000000000000000048 +:1008B0000202020202020202020202020202020218 +:1008C0000000000000000000000000000000000028 +:1008D0000000000000000000000000000000000018 +:1008E0000000000000000000000000000000000008 +:1008F00000000000000000000000000000000000F8 +:1009000002020202020202020202020202020202C7 +:1009100000000000000000000000000000000000D7 +:1009200000000000000000000000000000000000C7 +:1009300000000000000000000000000000000000B7 +:1009400000000000000000000000000000000000A7 +:100950000000000000000000000000000000000097 +:100960000202020202020202020202020202020267 +:100970000000000000000000000000000000000077 +:100980000000000000000000000000000000000067 +:100990000000000000000000000000000000000057 +:1009A0000000000000000000000000000000000047 +:1009B0000202020202020202020202020202020217 +:1009C0000000000000000000000000000000000027 +:1009D0000000000000000000000000000000000017 +:1009E0000000000000000000000000000000000007 +:1009F00000000000000000000000000000000000F7 +:100A000002020202020202020202020202020202C6 +:100A100000000000010000000000000100010000D3 +:100A200000000000000000000000000000000000C6 +:100A300000000000000000000000000000000000B6 +:100A400000000000000000000000000000000000A6 +:100A50000000000000000000000000000000000096 +:100A60000202020202020202020202020202020266 +:100A70000000000000000000000000000000000076 +:100A80000000000000000000000000000000000066 +:100A90000000000000000000000000000000000056 +:100AA0000000000000000000000000000000000046 +:100AB0000202020202020202020202020202020216 +:100AC0000000000000000000000000000000000026 +:100AD0000000000000000000000000000000000016 +:100AE0000000000000000000000000000000000006 +:100AF00000000000000000000000000000000000F6 +:100B000002020202020202020202020202020202C5 +:100B100000000000010000000101010101010000CE +:100B200000000000000000000000000000000000C5 +:100B300000000000000000000000000000000000B5 +:100B400000000000000000000000000000000000A5 +:100B50000000000000000000000000000000000095 +:100B60000202020202020202020202020202020265 +:100B70000000000000000000000000000000000075 +:100B80000000000000000000000000000000000065 +:100B90000000000000000000000000000000000055 +:100BA0000000000000000000000000000000000045 +:100BB0000202020202020202020202020202020215 +:100BC0000000000000000000000000000000000025 +:100BD0000000000000000000000000000000000015 +:100BE0000000000000000000000000000000000005 +:100BF00000000000000000000000000000000000F5 +:100C000002020202020202020202020202020202C4 +:100C100001010101010001010101010101010000C7 +:100C200000000000000000000000000000000000C4 +:100C300000000000000000000000000000000000B4 +:100C400000000000000000000000000000000000A4 +:100C50000000000000000000000000000000000094 +:100C60000202020202020202020202020202020264 +:100C70000000000000000000000000000000000074 +:100C80000000000000000000000000000000000064 +:100C90000000000000000000000000000000000054 +:100CA0000000000000000000000000000000000044 +:100CB0000202020202020202020202010202020215 +:100CC0000000000000000000000000000000000024 +:100CD0000000000000000000000000000000000014 +:100CE0000000000000000000000000000000000004 +:100CF00000000000000000000000000000000000F4 +:100D000000000200000000000200000002000000DD +:100D100001010101010101010101010101010101C3 +:100D200000000000000000000000000000000000C3 +:100D300000000000000000000000000000000000B3 +:100D400000000000000000000000000000000000A3 +:100D50000000000000000000000000000000000093 +:100D60000202020202020202020202020202020263 +:100D70000000000000000000000000000000000073 +:100D80000000000000000000000000000000000063 +:100D90000000000000000000000000000000000053 +:100DA0000000000000000000000000000000000043 +:100DB0000202020201020202010102020102020217 +:100DC0000000000000000000000000000000000023 +:100DD0000000000000000000000000000000000013 +:100DE0000000000000000000000000000000000003 +:100DF00000000000000000000000000000000000F3 +:100E000000000200000000000200000002000000DC +:100E100001010101010101010101010101010101C2 +:100E200000000000000000000000000000000000C2 +:100E300000000000000000000000000000000000B2 +:100E400000000000000000000000000000000000A2 +:100E50000000000000000000000000000000000092 +:100E60000101010101010101010101010101010172 +:100E70000000000000000000000000000000000072 +:100E80000000000000000000000000000000000062 +:100E90000000000000000000000000000000000052 +:100EA0000000000000000000000000000000000042 +:100EB000010101010201010102020100020101011F +:100EC0000000000000000000000000000000000022 +:100ED0000000000000000000000000000000000012 +:100EE0000000000000000000000000000000000002 +:100EF00000000000000000000000000000000000F2 +:100F000000000200000000000200000000000000DD +:100F100001010101010101010101010101010101C1 +:100F200000000000000000000000000000000000C1 +:100F300000000000000000000000000000000000B1 +:100F400000000000000000000000000000000000A1 +:100F50000000000000000000000000000000000091 +:100F60000101010101010101010101010101010171 +:100F70000000000000000000000000000000000071 +:100F80000000000000000000000000000000000061 +:100F90000000000000000000000000000000000051 +:100FA0000000000000000000000000000000000041 +:100FB000020202020002020200000200000202021B +:100FC0000000000000000000000000000000000021 +:100FD0000000000000000000000000000000000011 +:100FE0000000000000000000000000000000000001 +:100FF00000000000000000000000000000000000F1 +:1010000000000200000000000000000000000000DE +:1010100001010101010101010101010101010101C0 +:1010200000000000000000000000000000000000C0 +:1010300000000000000000000000000000000000B0 +:1010400000000000000000000000000000000000A0 +:101050000000000000000000000000000000000090 +:101060000101010101010101010101010101010170 +:101070000000000000000000000000000000000070 +:101080000000000000000000000000000000000060 +:101090000000000000000000000000000000000050 +:1010A0000000000000000000000000000000000040 +:1010B0000101010101010101010101010101010120 +:1010C0000000000000000000000000000000000020 +:1010D0000000000000000000000000000000000010 +:1010E0000000000000000000000000000000000000 +:1010F00000000000000000000000000000000000F0 +:1011000000000200000000000000000000000000DD +:1011100000000000000000000000000000000000CF +:1011200000000000000000000000000000000000BF +:1011300000000000000000000000000000000000AF +:10114000000000000000000000000000000000009F +:10115000000000000000000000000000000000008F +:10116000000000000000000000000000000000007F +:10117000000000000000000000000000000000006F +:10118000000000000000000000000000000000005F +:10119000000000000000000000000000000000004F +:1011A000000000000000000000000000000000003F +:1011B000000000000000000000000000000000002F +:1011C000000000000000000000000000000000001F +:1011D000000000000000000000000000000000000F +:1011E00000000000000000000000000000000000FF +:1011F00000000000000000000000000000000000EF +:1012000000000000000000000000000000000000DE +:101210001E000000000000000200020200000100A9 +:1012200000000101010000010000000000000000BA +:1012300000000000000000000000000000000000AE +:10124000000000000000000000000000000000009E +:10125000000000000000000000000000000000008E +:10126000000000000000000000000000000000007E +:10127000000000000000000000000000000000006E +:10128000000000000000000000000000000000005E +:10129000000000000000000000000000000000004E +:1012A000000000000000000000000000000000003E +:1012B000000000000000000000000000000000002E +:1012C000000000000000000000000000000000001E +:1012D000000000000000000000000000000000000E +:1012E00000000000000000000000000000000000FE +:1012F00000000000000000000000000000000000EE +:1013000000000000000000000001010101000100D8 +:1013100000000000000000000202020202000101C1 +:1013200001010201020101010000000000000000B3 +:1013300000000000000000000000000000000000AD +:10134000000000000000000000000000000000009D +:10135000000000000000000000000000000000008D +:10136000000000000000000000000000000000007D +:10137000000000000000000000000000000000006D +:10138000000000000000000000000000000000005D +:10139000000000000000000000000000000000004D +:1013A000000000000000000000000000000000003D +:1013B000000000000000000000000000000100002C +:1013C000000000000000000000000000000000001D +:1013D000000000000000000000000000000000000D +:1013E00000000000000000000000000000000000FD +:1013F00000000000000000000000000000000000ED +:1014000000000000000000000001010101000100D7 +:1014100000000000000000000202020202000102BF +:1014200002020201020102010000000000000000AF +:1014300000000000000000000000000000000000AC +:10144000000000000000000000000000000000009C +:10145000000000000000000000000000000000008C +:10146000000000000000000000000000000000007C +:10147000000000000000000000000000000000006C +:10148000000000000000000000000000000000005C +:10149000000000000000000000000000000000004C +:1014A000000000000000000000000000000000003C +:1014B000000000000000000000000000010100002A +:1014C000000001000000000000000000000000001B +:1014D000000000000000000000000000000000000C +:1014E00000000000000000000000000000000000FC +:1014F00000000000000000000000000000000000EC +:1015000000000000000000000001010101000100D6 +:1015100000000000000000000202020202020102BC +:1015200002020201020102010000000000000000AE +:1015300000000000000000000000000000000000AB +:10154000000000000000000000000000000000009B +:10155000000000000000000000000000000000008B +:10156000000000000000000000000000000000007B +:10157000000000000000000000000000000000006B +:10158000000000000000000000000000000000005B +:10159000000000000000000000000000000000004B +:1015A000000000000000000000000000000000003B +:1015B0000000000000000000000000000101010028 +:1015C000000001000000000000000000000000001A +:1015D000000000000000000000000000000000000B +:1015E00000000000000000000000000000000000FB +:1015F00000000000000000000000000000000000EB +:1016000000000000000000000001010101000100D5 +:1016100000000000000000000202020202020102BB +:1016200002020201020102000000000000000000AE +:1016300000000000000000000000000000000000AA +:10164000000000000000000000000000000000009A +:10165000000000000000000000000000000000008A +:10166000000000000000000000000000000000007A +:10167000000000000000000000000000000000006A +:10168000000000000000000000000000000000005A +:10169000000000000000000000000000000000004A +:1016A000000000000000000000000000000000003A +:1016B0000000000000000000000000000101010027 +:1016C0000000010000000000000000000000000019 +:1016D000000000000000000000000000000000000A +:1016E00000000000000000000000000000000000FA +:1016F00000000000000000000000000000000000EA +:1017000000000000000000000001010101000100D4 +:1017100000000000000000000202020202020202B9 +:1017200002020201020202000000000000000000AC +:1017300000000000000000000000000000000000A9 +:101740000000000000000000000000000000000099 +:101750000000000000000000000000000000000089 +:101760000000000000000000000000000000000079 +:101770000000000000000000000000000000000069 +:101780000000000000000000000000000000000059 +:101790000000000000000000000000000000000049 +:1017A0000000000000000000000000000000000039 +:1017B0000000000000000000000000000101010026 +:1017C0000000010001000000000000000000000017 +:1017D0000000000000000000000000000000000009 +:1017E00000000000000000000000000000000000F9 +:1017F00000000000000000000000000000000000E9 +:1018000000000000000000000001010101000100D3 +:1018100000000000000000000202020202020202B8 +:1018200002020201020202000000000000000000AB +:1018300000000000000000000000000000000000A8 +:101840000000000000000000000000000000000098 +:101850000000000000000000000000000000000088 +:101860000000000000000000000000000000000078 +:101870000000000100000000000000000000000067 +:101880000000000000000000000000000000000058 +:101890000000000000000000000000000000000048 +:1018A0000000000000000000000000000000000038 +:1018B0000000000000000000000000000101010025 +:1018C0000000010001000000000000000000000016 +:1018D0000000000000000000000000000000000008 +:1018E00000000000000000000000000000000000F8 +:1018F00000000000000000000000000000000000E8 +:1019000000000000000000000001010101000100D2 +:1019100000000000000000000202020202020202B7 +:1019200002020202020202000000000000000000A9 +:1019300000000000000000000000000000000000A7 +:101940000000000000000000000000000000000097 +:101950000000000000000000000000000000000087 +:101960000000000000000000000000000000000077 +:101970000000000100000000000000000000000066 +:101980000000000000000000000000000000000057 +:101990000000000000000000000000000000000047 +:1019A0000000000000000000000000000000000037 +:1019B0000000000000000000000000000101010024 +:1019C0000000010001000000000000000000000015 +:1019D0000000000000000000000000000000000007 +:1019E00000000000000000000000000000000000F7 +:1019F00000000000000000000000000000000000E7 +:101A000000000000000000000001010101000100D1 +:101A100000000000000000000202020202020202B6 +:101A200002020202020202000000000000000000A8 +:101A300000000000000000000000000000000000A6 +:101A40000000000000000000000000000000000096 +:101A50000000000000000000000000000000000086 +:101A60000000000000000000000000000000000076 +:101A70000000000100000000000000000000000065 +:101A80000000000000000000000000000000000056 +:101A90000000000000000000000000000000000046 +:101AA0000000000000000000000000000000000036 +:101AB0000000000000000000000000000101010122 +:101AC0000100010001000000000000000000000013 +:101AD0000000000000000000000000000000000006 +:101AE00000000000000000000000000000000000F6 +:101AF00000000000000000000000000000000000E6 +:101B000000000000000000000001010101000100D0 +:101B100000000000010000010202020202020202B3 +:101B200002020202020202000000000000000000A7 +:101B300000000000000000000000000000000000A5 +:101B40000000000000000000000000000000000095 +:101B50000000000000000000000000000000000085 +:101B60000000000000000000000000000000000075 +:101B70000000000100000000000000000000000064 +:101B80000000000000000000000000000000000055 +:101B90000000000000000000000000000000000045 +:101BA0000000000000000000000000000000000035 +:101BB0000000000000000000000000000101010121 +:101BC0000100010101000000000000000000000011 +:101BD0000000000000000000000000000000000005 +:101BE00000000000000000000000000000000000F5 +:101BF00000000000000000000000000000000000E5 +:101C000000000000000000000000010101000100D0 +:101C100000000000010001010202010101020202B4 +:101C200002020102010201000000000000000000A9 +:101C300000000000000000000000000000000000A4 +:101C40000000000000000000000000000000000094 +:101C50000000000000000000000000000000000084 +:101C60000000000000000000010000000000000073 +:101C70000000000101000000000000000000000062 +:101C80000000000000000000000000000000000054 +:101C90000000000000000000000000000000000044 +:101CA0000000000000000000000000000000000034 +:101CB000000000000000000000000000020201011E +:101CC000010101010100000000000000000000000F +:101CD0000000000000000000000000000000000004 +:101CE00000000000000000000000000000000000F4 +:101CF00000000000000000000000000000000000E4 +:101D000000000000000000000000020201000100CD +:101D100000000000010001010201010101010201B6 +:101D200001010102010201000000000000000000AA +:101D300000000000000000000000000000000000A3 +:101D40000000000000000000000000000000000093 +:101D50000000000000000000000000000000000083 +:101D60000000000000000000020000000000000170 +:101D7000010100010101000000000000000000005E +:101D80000000000000000000000000000000000053 +:101D90000000000000000000000000000000000043 +:101DA0000000000000000000000000000000000033 +:101DB000000000000000000001000000020202011B +:101DC000010102010100000000000000000000000D +:101DD0000000000000000000000000000000000003 +:101DE00000000000000000000000000000000000F3 +:101DF00000000000000000000000000000000000E3 +:101E000000000000000000000000020202010101C9 +:101E100001010000010001010101010101010201B4 +:101E200001010102010201000000000000000000A9 +:101E300000000000000000000000000000000000A2 +:101E40000000000000000000000000000000000092 +:101E50000000000000000000000000000000000082 +:101E6000000000000000000002000000000000016F +:101E7000010100010101000100000000000000005C +:101E80000000000000000000000000000000000052 +:101E90000000000000000000000000000000000042 +:101EA0000000000000000000000000000000000032 +:101EB0000000000000000000020000000202020119 +:101EC000010102010200000000000000000000000B +:101ED0000000000000000000000000000000000002 +:101EE00000000000000000000000000000000000F2 +:101EF00000000000000000000000000000000000E2 +:101F000000000000000000000100020202010201C6 +:101F100001010001010001010101010101010201B2 +:101F200001010102010101000000000000000000A9 +:101F300000000000000000000000000000000000A1 +:101F40000000000000000000000000000000000091 +:101F50000000000000000000000000000000000081 +:101F6000000000000000000002000000000100016D +:101F7000010100010101010100000000000000005A +:101F80000000000000000000000000000000000051 +:101F90000000000000000000000000000000000041 +:101FA0000000000000000000000000000000000031 +:101FB0000000000000000000020001000202020216 +:101FC0000201020102000001000000000000000008 +:101FD0000000000000000000000000000000000001 +:101FE00000000000000000000000000000000000F1 +:101FF00000000000000000000000000000000000E1 +:1020000000000000000000000102020202010201C3 +:1020100001010001010101010101010101010101B1 +:1020200001010102010101000000000000000000A8 +:1020300000000000000000000000000000000000A0 +:102040000000000000000000000000000000000090 +:102050000000000000000000000000000000000080 +:102060000000000000000000020001000001010269 +:102070000202010202010101000000000000000054 +:102080000000000000000000000000000000000050 +:102090000000000000000000000000000000000040 +:1020A0000000000000000000000000000000000030 +:1020B0000000000000000000020001000202020215 +:1020C0000202020102010101000000000000000004 +:1020D0000000000000000000000000000000000000 +:1020E00000000000000000000000000000000000F0 +:1020F00000000000000000000000000000000000E0 +:1021000000000000000000000202020202010201C1 +:1021100001010101010101010101010101010101AF +:1021200001010101010101000000000000000000A8 +:10213000000000000000000000000000000000009F +:10214000000000000000000000000000000000008F +:10215000000000000000000000000000000000007F +:102160000000000000000000020101000102010265 +:102170000202010202010101000000000000000053 +:10218000000000000000000000000000000000004F +:10219000000000000000000000000000000000003F +:1021A000000000000000000000000000000000002F +:1021B0000000000000000000020002010202020212 +:1021C0000202020102010101000000000000000003 +:1021D00000000000000000000000000000000000FF +:1021E00000000000000000000000000000000000EF +:1021F00000000000000000000000000000000000DF +:1022000000000000000000000202020202010201C0 +:1022100000010101020101010101010101010101AE +:1022200001010101010101000000000000000000A7 +:10223000000000000000000000000000000000009E +:10224000000000000000000000000000000000008E +:10225000000000000000000000000000000000007E +:102260000000000000000000020202000102010262 +:102270000202020202020101000000000000000050 +:10228000000000000000000000000000000000004E +:10229000000000000000000000000000000000003E +:1022A000000000000000000000000000000000002E +:1022B000000000000000000002010202020202020F +:1022C0000202020202010101000000000000000001 +:1022D00000000000000000000000000000000000FE +:1022E00000000000000000000000000000000000EE +:1022F00000000000000000000000000000000000DE +:1023000000000000000000000202020202020202BD +:1023100000020101020102020100000000000100B0 +:1023200000000001000100000000000000000000AB +:10233000000000000000000000000000000000009D +:10234000000000000000000000000000000000008D +:10235000000000000000000000000000000000007D +:10236000000000000000000002020200020202025F +:10237000020202020202020200000000000000004D +:10238000000000000000000000000000000000004D +:10239000000000000000000000000000000000003D +:1023A000000000000000000000000000000000002D +:1023B000000000000000000002020202020202020D +:1023C0000202020202010101000000000000000000 +:1023D00000000000000000000000000000000000FD +:1023E00000000000000000000000000000000000ED +:1023F00000000000000000000000000000000000DD +:1024000000000000000000000202020202020202BC +:1024100002020001020102020000000000000100AF +:1024200000000001000000000000000000000000AB +:10243000000000000000000000000000000000009C +:10244000000000000000000000000000000000008C +:10245000000000000000000000000000000000007C +:10246000000000000000000002020202020202025C +:10247000020202020202020200000000000000004C +:10248000000000000000000000000000000000004C +:10249000000000000000000000000000000000003C +:1024A000000000000000000000000000000000002C +:1024B000000000000000000002020202020202020C +:1024C00002020202020202020000000000000000FC +:1024D00000000000000000000000000000000000FC +:1024E00000000000000000000000000000000000EC +:1024F00000000000000000000000000000000000DC +:1025000000000000000000000202020202020202BB +:1025100002020002020202020000000000000000AD +:1025200000000000000000000000000000000000AB +:10253000000000000000000000000000000000009B +:10254000000000000000000000000000000000008B +:10255000000000000000000000000000000000007B +:10256000000000000000000002020202020202025B +:10257000020202020202020200000000000000004B +:10258000000000000000000000000000000000004B +:10259000000000000000000000000000000000003B +:1025A000000000000000000000000000000000002B +:1025B000000000000000000002020202020202020B +:1025C00002020202020202020000000000000000FB +:1025D00000000000000000000000000000000000FB +:1025E00000000000000000000000000000000000EB +:1025F00000000000000000000000000000000000DB +:1026000000000000000000000202020202020202BA +:1026100002020202020202020000000000000000AA +:1026200000000000000000000000000000000000AA +:10263000000000000000000000000000000000009A +:10264000000000000000000000000000000000008A +:10265000000000000000000000000000000000007A +:10266000000000000000000001020202020102015D +:10267000010101020102020200000000000000004E +:10268000000000000000000000000000000000004A +:10269000000000000000000000000000000000003A +:1026A000000000000000000000000000000000002A +:1026B0000000000000000000010200000102010112 +:1026C00001010202010202020000000000000000FD +:1026D00000000000000000000000000000000000FA +:1026E00000000000000000000000000000000000EA +:1026F00000000000000000000000000000000000DA +:1027000000000000000000000202020202020202B9 +:1027100002020202020202020000000000000000A9 +:1027200000000000000000000000000000000000A9 +:102730000000000000000000000000000000000099 +:102740000000000000000000000000000000000089 +:102750000000000000000000000000000000000079 +:102760000000000000000000020202020202020259 +:102770000202020202020202000000000000000049 +:102780000000000000000000000000000000000049 +:102790000000000000000000000000000000000039 +:1027A0000000000000000000000000000000000029 +:1027B000000000000000000002020000020102020E +:1027C00002020102020202020000000000000000FA +:1027D00000000000000000000000000000000000F9 +:1027E00000000000000000000000000000000000E9 +:1027F00000000000000000000000000000000000D9 +:1028000000000000000000000202020202020202B8 +:1028100002020202020202020001010101010001A2 +:1028200001010100010001000000000000000000A3 +:102830000000000000000000000000000000000098 +:102840000000000000000000000000000000000088 +:102850000000000000000000000000000000000078 +:102860000000000000000000000000000000000068 +:102870000000000000000000000000000000000058 +:102880000000000000000000000000000000000048 +:102890000000000000000000000000000000000038 +:1028A0000000000000000000000000000000000028 +:1028B0000000000000000000000000000002000016 +:1028C0000000020000000000000000000000000006 +:1028D00000000000000000000000000000000000F8 +:1028E00000000000000000000000000000000000E8 +:1028F00000000000000000000000000000000000D8 +:1029000000000000000000000202020202020202B7 +:1029100002020202020202020101010101010001A0 +:1029200001010100010101000000000000000000A1 +:102930000000000000000000000000000000000097 +:102940000000000000000000000000000000000087 +:102950000000000000000000000000000000000077 +:102960000000000000000000000000000000000067 +:102970000000000000000000000000000000000057 +:102980000000000000000000000000000000000047 +:102990000000000000000000000000000000000037 +:1029A0000000000000000000000000000000000027 +:1029B0000000000000000000000000000000000017 +:1029C0000000000000000000000000000000000007 +:1029D00000000000000000000000000000000000F7 +:1029E00000000000000000000000000000000000E7 +:1029F00000000000000000000000000000000000D7 +:102A000000000000000000000202020202020202B6 +:102A1000020202020202020201010101010101019E +:102A2000010101010101010000000000000000009F +:102A30000000000000000000000000000000000096 +:102A40000000000000000000000000000000000086 +:102A50000000000000000000000000000000000076 +:102A6000000000000000000001010101010101015E +:102A7000010101010101010100000000000000004E +:102A80000000000000000000000000000000000046 +:102A90000000000000000000000000000000000036 +:102AA0000000000000000000000000000000000026 +:102AB0000000000000000000000000000000000016 +:102AC0000000000000000000000000000000000006 +:102AD00000000000000000000000000000000000F6 +:102AE00000000000000000000000000000000000E6 +:102AF00000000000000000000000000000000000D6 +:102B000000000000000000000002000002000200BF +:102B100000000000000000000101010101010101AD +:102B2000010101010101010100000000000000009D +:102B30000000000000000000000000000000000095 +:102B40000000000000000000000000000000000085 +:102B50000000000000000000000000000000000075 +:102B6000000000000000000001010101010101015D +:102B7000010101010101010100000000000000004D +:102B80000000000000000000000000000000000045 +:102B90000000000000000000000000000000000035 +:102BA0000000000000000000000000000000000025 +:102BB0000000000000000000000000000000000015 +:102BC0000000000000000000000000000000000005 +:102BD00000000000000000000000000000000000F5 +:102BE00000000000000000000000000000000000E5 +:102BF00000000000000000000000000000000000D5 +:102C000000000000000000000002000000000200C0 +:102C100000000000000000000101010101010101AC +:102C2000010101010101010100000000000000009C +:102C30000000000000000000000000000000000094 +:102C40000000000000000000000000000000000084 +:102C50000000000000000000000000000000000074 +:102C6000000000000000000001010101010101015C +:102C7000010101010101010100000000000000004C +:102C80000000000000000000000000000000000044 +:102C90000000000000000000000000000000000034 +:102CA0000000000000000000000000000000000024 +:102CB000000000000000000001010101010101010C +:102CC00001010101010101010000000000000000FC +:102CD00000000000000000000000000000000000F4 +:102CE00000000000000000000000000000000000E4 +:102CF00000000000000000000000000000000000D4 +:102D000000000000000000000002000000000000C1 +:102D100000000000000000000101010101010101AB +:102D2000010101010101010100000000000000009B +:102D30000000000000000000000000000000000093 +:102D40000000000000000000000000000000000083 +:102D50000000000000000000000000000000000073 +:102D6000000000000000000001010101010101015B +:102D7000010101010101010100000000000000004B +:102D80000000000000000000000000000000000043 +:102D90000000000000000000000000000000000033 +:102DA0000000000000000000000000000000000023 +:102DB000000000000000000001010101010101010B +:102DC00001010101010101010000000000000000FB +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000101010101010101AA +:102E2000010101010101010100000000000000009A +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000020202020202020252 +:102E70000202020202020202000000000000000042 +:102E80000000000000000000000000000000000042 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB0000000000000000000020202020202020202 +:102EC00002020202020202020000000000000000F2 +:102ED00000000000000000000000000000000000F2 +:102EE00000000000000000000000000000000000E2 +:102EF00000000000000000000000000000000000D2 +:102F000000000000000000000000000000000000C1 +:102F100000000000000000000000000000000000B1 +:102F200000000000000000000000000000000000A1 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD00000000000000000000000000000000000F1 +:102FE00000000000000000000000000000000000E1 +:102FF00000000000000000000000000000000000D1 +:1030000000000000000000000000000000000000C0 +:1030100000000000000000001E0000000000000092 +:10302000000001010000000000000101010000019A +:103030000000000000000000000000000000000090 +:103040000000000000000000000000000000000080 +:103050000000000000000000000000000000000070 +:103060000000000000000000000000000000000060 +:103070000000000000000000000000000000000050 +:103080000000000000000000000000000000000040 +:103090000000000000000000000000000000000030 +:1030A0000000000000000000000000000000000020 +:1030B0000000000000000000000000000000000010 +:1030C0000000000000000000000000000000000000 +:1030D00000000000000000000000000000000000F0 +:1030E00000000000000000000000000000000000E0 +:1030F00000000000000000000000000000000000D0 +:1031000000000000000000000000000000000000BF +:1031100000000000000000000000000000000000AF +:103120000001020100010002010001010100000193 +:10313000000000000000000000000000000000008F +:10314000000000000000000000000000000000007F +:10315000000000000000000000000000000000006F +:10316000000000000000000000000000000000005F +:10317000000000000000000000000000000000004F +:10318000000000000000000000000000000000003F +:10319000000000000000000000000000000000002F +:1031A000000000000000000000000000000000001F +:1031B000000000000000000000000000000000000F +:1031C00000000000000000000000000000000000FF +:1031D00000000000000000000000000000000000EF +:1031E00000000000000000000000000000000000DF +:1031F00000000000000000000000000000000000CF +:1032000000000000000000000000000000000000BE +:1032100000010000000000000000000000000000AD +:10322000000102020002010201000201010000018E +:10323000000000000000000000000000000000008E +:10324000000000000000000000000000000000007E +:10325000000000000000000000000000000000006E +:10326000000000000000000000000000000000005E +:10327000000000000000000000000000000000004E +:10328000000000000000000000000000000000003E +:10329000000000000000000000000000000000002E +:1032A000000000000000000000000000000000001E +:1032B000000000000000000000000000000000000E +:1032C00000000000000000000000000000000000FE +:1032D00000000000000000000000000000000000EE +:1032E00000000000000000000000000000000000DE +:1032F00000000000000000000000000000000000CE +:1033000000000000000000000000000000000000BD +:1033100000010000000001000000000000000001AA +:10332000000202020102010201000201010000018B +:10333000000000000000000000000000000000008D +:10334000000000000000000000000000000000007D +:10335000000000000000000000000000000000006D +:10336000000000000000000000000000000000005D +:10337000000000000000000000000000000000004D +:10338000000000000000000000000000000000003D +:10339000000000000000000000000000000000002D +:1033A000000000000000000000000000000000001D +:1033B000000000000000000000000000000000000D +:1033C00000000000000000000000000000000000FD +:1033D00000000000000000000000000000000000ED +:1033E00000000000000000000000000000000000DD +:1033F00000000000000000000000000000000000CD +:1034000000000000000000000000000000000000BC +:1034100000010000010001000000000000000001A8 +:103420000002020201020102020002010200000089 +:10343000000000000000000000000000000000008C +:10344000000000000000000000000000000000007C +:10345000000000000000000000000000000000006C +:10346000000000000000000000000000000000005C +:10347000000000000000000000000000000000004C +:10348000000000000000000000000000000000003C +:10349000000000000000000000000000000000002C +:1034A000000000000000000000000000000000001C +:1034B000000000000000000000000000000000000C +:1034C00000000000000000000000000000000000FC +:1034D00000000000000000000000000000000000EC +:1034E00000000000000000000000000000000000DC +:1034F00000000000000000000000000000000000CC +:1035000000000000000000000000000000000000BB +:1035100000010101010001000000000000000001A5 +:103520000002020202020102020002010201000086 +:10353000000000000000000000000000000000008B +:10354000000000000000000000000000000000007B +:10355000000000000000000000000000000000006B +:10356000000000000000000000000000000000005B +:10357000000000000000000000000000000000004B +:10358000000000000000000000000000000000003B +:10359000000000000000000000000000000000002B +:1035A000000000000000000000000000000000001B +:1035B000000000000000000000000000000000000B +:1035C00000000000000000000000000000000000FB +:1035D00000000000000000000000000000000000EB +:1035E00000000000000000000000000000000000DB +:1035F00000000000000000000000000000000000CB +:1036000000000000000000000000000000000000BA +:1036100000010101010001000000000000000001A4 +:103620000102020202020102020002010201000084 +:10363000000000000000000000000000000000008A +:10364000000000000000000000000000000000007A +:10365000000000000000000000000000000000006A +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:1037000000000000000000000000000000000000B9 +:1037100000010101010001000000000000000001A3 +:10372000020202020202020202010201020101007F +:103730000000000000000000000000000000000089 +:103740000000000000000000000000000000000079 +:103750000000000000000000000000000000000069 +:103760000000000000000000000000000000000059 +:103770000000000000000000000000000000000049 +:103780000000000000000000000000000000000039 +:103790000000000000000000000000000000000029 +:1037A0000000000000000000000000000000000019 +:1037B0000000000000000000000000000000000009 +:1037C00000000000000000000000000000000000F9 +:1037D00000000000000000000000000000000000E9 +:1037E00000000000000000000000000000000000D9 +:1037F00000000000000000000000000000000000C9 +:1038000000000000000000000000000000000000B8 +:1038100000010101010001000000000000000001A2 +:10382000020202020202020202010202020202007B +:103830000000000000000000000000000000000088 +:103840000000000000000000000000000000000078 +:103850000000000000000000000000000000000068 +:103860000000000000000000000000000000000058 +:103870000000000000000000000000000000000048 +:103880000000000000000000000000000000000038 +:103890000000000000000000000000000000000028 +:1038A0000000000000000000000000000000000018 +:1038B0000000000000000000000000000000000008 +:1038C00000000000000000000000000000000000F8 +:1038D00000000000000000000000000000000000E8 +:1038E00000000000000000000000000000000000D8 +:1038F00000000000000000000000000000000000C8 +:1039000000000000000000000000000000000000B7 +:1039100000010101010001000000000000000001A1 +:103920000202020202020202020202020202020079 +:103930000000000000000000000000000000000087 +:103940000000000000000000000000000000000077 +:103950000000000000000000000000000000000067 +:103960000000000000000000000000000000000057 +:103970000000000000000000000000000000000047 +:103980000000000000000000000000000000000037 +:103990000000000000000000000000000000000027 +:1039A0000000000000000000000000000000000017 +:1039B0000000000000000000000000000000000007 +:1039C00000000000000000000000000100000000F6 +:1039D00000000000000000000000000000000000E7 +:1039E00000000000000000000000000000000000D7 +:1039F00000000000000000000000000000000000C7 +:103A000000000000000000000000000000000000B6 +:103A100000010101010001000000000000000001A0 +:103A20000202020202020201020202020202020079 +:103A30000000000000000000000000000000000086 +:103A40000000000000000000000000000000000076 +:103A50000000000000000000000000000000000066 +:103A60000000000000000000000000000000000056 +:103A70000100000000000100000001010000000042 +:103A80000000000000000000000000000000000036 +:103A90000000000000000000000000000000000026 +:103AA0000000000000000000000000000000000016 +:103AB0000000000000000000000000000000000006 +:103AC00000000000000000000000000100000000F5 +:103AD00000000000000000000000000000000000E6 +:103AE00000000000000000000000000000000000D6 +:103AF00000000000000000000000000000000000C6 +:103B000000000000000000000000000000000000B5 +:103B100000000101010001000000000000000001A0 +:103B2000020201020201020102020102020202007B +:103B30000000000000000000000000000000000085 +:103B40000000000000000000000000000000000075 +:103B50000000000000000000000000000000000065 +:103B60000000000000000000000000000000000055 +:103B7000020000000100010000000101000100003E +:103B80000000000000000000000000000000000035 +:103B90000000000000000000000000000000000025 +:103BA0000000000000000000000000000000000015 +:103BB0000000000000000000000000000000000005 +:103BC00000000000000001000000000100000000F3 +:103BD00000000000000000000000000000000000E5 +:103BE00000000000000000000000000000000000D5 +:103BF00000000000000000000000000000000000C5 +:103C000000000000000000000000000000000000B4 +:103C1000000001010100010000000000000000019F +:103C2000020201010201020102020102020202007B +:103C30000000000000000000000000000000000084 +:103C40000000000000000000000000000000000074 +:103C50000000000000000000000000000000000064 +:103C60000000000000000000000000000000000054 +:103C7000020000000100010000000101000100013C +:103C80000000000000000000000000000000000034 +:103C90000000000000000000000000000000000024 +:103CA0000000000000000000000000000000000014 +:103CB0000000000000000000000000000000000004 +:103CC00000000000010001000000000100010100EF +:103CD00000000000000000000000000000000000E4 +:103CE00000000000000000000000000000000000D4 +:103CF00000000000000000000000000000000000C4 +:103D000000000000000000000000000000000000B3 +:103D1000000001010100010000000000010000019D +:103D2000020101010101020101020102010201007F +:103D30000000000000000000000000000000000083 +:103D40000000000000000000000000000000000073 +:103D50000000000000000000000000000000000063 +:103D60000000000000000000000000000000000053 +:103D7000020000000100010000000101000101013A +:103D80000000000000000000000000000000000033 +:103D90000000000000000000000000000000000023 +:103DA0000000000000000000000000000000000013 +:103DB0000000000000000000000000000000000003 +:103DC00000000000010001000000000101010101EC +:103DD00000000000000000000000000000000000E3 +:103DE00000000000000000000000000000000000D3 +:103DF00000000000000000000000000000000000C3 +:103E000000000000000000000000000000000000B2 +:103E1000000001010100010000000000010001019B +:103E2000020101010101020101020102010101007F +:103E30000000000000000000000000000000000082 +:103E40000000000000000000000000000000000072 +:103E50000000000000000000000000000000000062 +:103E60000000000000000000000000000000000052 +:103E70000200010101000100000001010001010137 +:103E80000000000000000000000000000000000032 +:103E90000000000000000000000000000000000022 +:103EA0000000000000000000000000000000000012 +:103EB0000000000000000000000000000000000002 +:103EC00000000000010001000000000101010101EB +:103ED00000000000000000000000000000000000E2 +:103EE00000000000000000000000000000000000D2 +:103EF00000000000000000000000000000000000C2 +:103F000000000000000000000000000000000000B1 +:103F10000002020202000200000000000100010194 +:103F20000201010101010101010101020101010080 +:103F30000000000000000000000000000000000081 +:103F40000000000000000000000000000000000071 +:103F50000000000000000000000000000000000061 +:103F60000000000000000000000000000000000051 +:103F7000020101010200020101010201000101012F +:103F80000000000000000000000000000000000031 +:103F90000000000000000000000000000000000021 +:103FA0000000000000000000000000000000000011 +:103FB0000000000000000000000000000000000001 +:103FC00002000100010001000000000101010101E7 +:103FD00000000000000000000000000000000000E1 +:103FE00000000000000000000000000000000000D1 +:103FF00000000000000000000000000000000000C1 +:1040000000000000000000000000000000000000B0 +:10401000000202020201020101010000010001028E +:104020000101010101010101010101010101010081 +:104030000000000000000000000000000000000080 +:104040000000000000000000000000000000000070 +:104050000000000000000000000000000000000060 +:104060000000000000000000000000000000000050 +:104070000202020202000201010102020102010128 +:104080000000000000000000000000000000000030 +:104090000000000000000000000000000000000020 +:1040A0000000000000000000000000000000000010 +:1040B0000000000000000000000000000000000000 +:1040C00002010100020102000000000201010101E1 +:1040D00000000000000000000000000000000000E0 +:1040E00000000000000000000000000000000000D0 +:1040F00000000000000000000000000000000000C0 +:1041000000000000000000000000000000000000AF +:10411000000202020201020101010000010001028D +:104120000101000101000100010100010101010084 +:10413000000000000000000000000000000000007F +:10414000000000000000000000000000000000006F +:10415000000000000000000000000000000000005F +:10416000000000000000000000000000000000004F +:104170000202020202010202020202020102020221 +:10418000000000000000000000000000000000002F +:10419000000000000000000000000000000000001F +:1041A000000000000000000000000000000000000F +:1041B00000000000000000000000000000000000FF +:1041C00002020201020102000000010202020201D9 +:1041D00000000000000000000000000000000000DF +:1041E00000000000000000000000000000000000CF +:1041F00000000000000000000000000000000000BF +:1042000000000000000000000000000000000000AE +:10421000000202020201020101010000010101028B +:104220000100000000000100000100010001000089 +:10423000000000000000000000000000000000007E +:10424000000000000000000000000000000000006E +:10425000000000000000000000000000000000005E +:10426000000000000000000000000000000000004E +:10427000020202020202020202020202020202021E +:10428000000000000000000000000000000000002E +:10429000000000000000000000000000000000001E +:1042A000000000000000000000000000000000000E +:1042B00000000000000000000000000000000000FE +:1042C00002020202020202000001010202020202D4 +:1042D00000000000000000000000000000000000DE +:1042E00000000000000000000000000000000000CE +:1042F00000000000000000000000000000000000BE +:1043000000000000000000000000000000000000AD +:104310000102020202010201010100000101010289 +:10432000010000000000000000000001000000008B +:10433000000000000000000000000000000000007D +:10434000000000000000000000000000000000006D +:10435000000000000000000000000000000000005D +:10436000000000000000000000000000000000004D +:10437000020202020202020202020202020202021D +:10438000000000000000000000000000000000002D +:10439000000000000000000000000000000000001D +:1043A000000000000000000000000000000000000D +:1043B00000000000000000000000000000000000FD +:1043C00002020202020202000002020202020202D1 +:1043D00000000000000000000000000000000000DD +:1043E00000000000000000000000000000000000CD +:1043F00000000000000000000000000000000000BD +:1044000000000000000000000000000000000000AC +:104410000202020202010201000101000201010286 +:10442000000000000000000000000000000000008C +:10443000000000000000000000000000000000007C +:10444000000000000000000000000000000000006C +:10445000000000000000000000000000000000005C +:10446000000000000000000000000000000000004C +:10447000020202020202020202020202020202021C +:10448000000000000000000000000000000000002C +:10449000000000000000000000000000000000001C +:1044A000000000000000000000000000000000000C +:1044B00000000000000000000000000000000000FC +:1044C00002020202020202020202020202020202CC +:1044D00000000000000000000000000000000000DC +:1044E00000000000000000000000000000000000CC +:1044F00000000000000000000000000000000000BC +:1045000000000000000000000000000000000000AB +:104510000202020202020202000201010201020280 +:10452000000000000000000000000000000000008B +:10453000000000000000000000000000000000007B +:10454000000000000000000000000000000000006B +:10455000000000000000000000000000000000005B +:10456000000000000000000000000000000000004B +:10457000010202020202020202020202020202021C +:10458000000000000000000000000000000000002B +:10459000000000000000000000000000000000001B +:1045A000000000000000000000000000000000000B +:1045B00000000000000000000000000000000000FB +:1045C00002020202020202020202020202020202CB +:1045D00000000000000000000000000000000000DB +:1045E00000000000000000000000000000000000CB +:1045F00000000000000000000000000000000000BB +:1046000000000000000000000000000000000000AA +:10461000020202020202020202020101020102027D +:104620000000010000010001000001000000000086 +:10463000000000000000000000000000000000007A +:10464000000000000000000000000000000000006A +:10465000000000000000000000000000000000005A +:10466000000000000000000000000000000000004A +:104670000201010101010101010101010101010129 +:10468000000000000000000000000000000000002A +:10469000000000000000000000000000000000001A +:1046A000000000000000000000000000000000000A +:1046B00000000000000000000000000000000000FA +:1046C00000000000000000000000000000000000EA +:1046D00000000000000000000000000000000000DA +:1046E00000000000000000000000000000000000CA +:1046F00000000000000000000000000000000000BA +:1047000000000000000000000000000000000000A9 +:10471000020202020202020202020001020202027C +:10472000000101010101000101000100010001007F +:104730000000000000000000000000000000000079 +:104740000000000000000000000000000000000069 +:104750000000000000000000000000000000000059 +:104760000000000000000000000000000000000049 +:10477000010202020202020202020202020202021A +:104780000000000000000000000000000000000029 +:104790000000000000000000000000000000000019 +:1047A0000000000000000000000000000000000009 +:1047B00000000000000000000000000000000000F9 +:1047C00000000000000000000000000000000000E9 +:1047D00000000000000000000000000000000000D9 +:1047E00000000000000000000000000000000000C9 +:1047F00000000000000000000000000000000000B9 +:1048000000000000000000000000000000000000A8 +:104810000202020202020202020202010202020279 +:10482000000101010101010101010100010101007B +:104830000000000000000000000000000000000078 +:104840000000000000000000000000000000000068 +:104850000000000000000000000000000000000058 +:104860000000000000000000000000000000000048 +:104870000101010101010101010101010101010128 +:104880000000000000000000000000000000000028 +:104890000000000000000000000000000000000018 +:1048A0000000000000000000000000000000000008 +:1048B00000000000000000000000000000000000F8 +:1048C00000000000000000000000000000000000E8 +:1048D00000000000000000000000000000000000D8 +:1048E00000000000000000000000000000000000C8 +:1048F00000000000000000000000000000000000B8 +:1049000000000000000000000000000000000000A7 +:104910000202020202020202020202020202020277 +:104920000101010101010101010101010101010177 +:104930000000000000000000000000000000000077 +:104940000000000000000000000000000000000067 +:104950000000000000000000000000000000000057 +:104960000000000000000000000000000000000047 +:104970000101010101010101010101010101010127 +:104980000000000000000000000000000000000027 +:104990000000000000000000000000000000000017 +:1049A0000000000000000000000000000000000007 +:1049B00000000000000000000000000000000000F7 +:1049C00000000000000000000000000000000000E7 +:1049D00000000000000000000000000000000000D7 +:1049E00000000000000000000000000000000000C7 +:1049F00000000000000000000000000000000000B7 +:104A000000000000000000000000000000000000A6 +:104A10000202020202020202020202020202020276 +:104A20000101010101010101010101010101010176 +:104A30000000000000000000000000000000000076 +:104A40000000000000000000000000000000000066 +:104A50000000000000000000000000000000000056 +:104A60000000000000000000000000000000000046 +:104A70000101010101010101010101010101010126 +:104A80000000000000000000000000000000000026 +:104A90000000000000000000000000000000000016 +:104AA0000000000000000000000000000000000006 +:104AB00000000000000000000000000000000000F6 +:104AC00001010101010101010101010101010101D6 +:104AD00000000000000000000000000000000000D6 +:104AE00000000000000000000000000000000000C6 +:104AF00000000000000000000000000000000000B6 +:104B000000000000000000000000000000000000A5 +:104B10000202020202020202020202020202020275 +:104B20000101010101010101010101010101010175 +:104B30000000000000000000000000000000000075 +:104B40000000000000000000000000000000000065 +:104B50000000000000000000000000000000000055 +:104B60000000000000000000000000000000000045 +:104B70000101010101010101010101010101010125 +:104B80000000000000000000000000000000000025 +:104B90000000000000000000000000000000000015 +:104BA0000000000000000000000000000000000005 +:104BB00000000000000000000000000000000000F5 +:104BC00001010101010101010101010101010101D5 +:104BD00000000000000000000000000000000000D5 +:104BE00000000000000000000000000000000000C5 +:104BF00000000000000000000000000000000000B5 +:104C000000000000000000000000000000000000A4 +:104C10000202020202020202020202020202020274 +:104C20000101010101010101010101010101010174 +:104C30000000000000000000000000000000000074 +:104C40000000000000000000000000000000000064 +:104C50000000000000000000000000000000000054 +:104C60000000000000000000000000000000000044 +:104C70000202020202020202020202020202020214 +:104C80000000000000000000000000000000000024 +:104C90000000000000000000000000000000000014 +:104CA0000000000000000000000000000000000004 +:104CB00000000000000000000000000000000000F4 +:104CC00002020202020202020202020202020202C4 +:104CD00000000000000000000000000000000000D4 +:104CE00000000000000000000000000000000000C4 +:104CF00000000000000000000000000000000000B4 +:104D000000000000000000000000000000000000A3 +:104D10000000000000000000000000000000000093 +:104D20000000000000000000000000000000000083 +:104D30000000000000000000000000000000000073 +:104D40000000000000000000000000000000000063 +:104D50000000000000000000000000000000000053 +:104D60000000000000000000000000000000000043 +:104D70000000000000000000000000000000000033 +:104D80000000000000000000000000000000000023 +:104D90000000000000000000000000000000000013 +:104DA0000000000000000000000000000000000003 +:104DB00000000000000000000000000000000000F3 +:104DC00000000000000000000000000000000000E3 +:104DD00000000000000000000000000000000000D3 +:104DE00000000000000000000000000000000000C3 +:104DF00000000000000000000000000000000000B3 +:104E000000000000000000000000000000000000A2 +:104E10000000000000000000000000000000000092 +:00000001FF diff --git a/fs/fat/dir.c b/fs/fat/dir.c index ee42b9e0b16a..2242ac239866 100644 --- a/fs/fat/dir.c +++ b/fs/fat/dir.c @@ -753,6 +753,13 @@ static int fat_ioctl_readdir(struct inode *inode, struct file *filp, return ret; } +static int fat_ioctl_volume_id(struct inode *dir) +{ + struct super_block *sb = dir->i_sb; + struct msdos_sb_info *sbi = MSDOS_SB(sb); + return sbi->vol_id; +} + static long fat_dir_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { @@ -769,6 +776,8 @@ static long fat_dir_ioctl(struct file *filp, unsigned int cmd, short_only = 0; both = 1; break; + case VFAT_IOCTL_GET_VOLUME_ID: + return fat_ioctl_volume_id(inode); default: return fat_generic_ioctl(filp, cmd, arg); } diff --git a/fs/fat/fat.h b/fs/fat/fat.h index 27ac25725954..a488c7750e72 100644 --- a/fs/fat/fat.h +++ b/fs/fat/fat.h @@ -78,6 +78,7 @@ struct msdos_sb_info { const void *dir_ops; /* Opaque; default directory operations */ int dir_per_block; /* dir entries per block */ int dir_per_block_bits; /* log2(dir_per_block) */ + unsigned long vol_id; /* volume ID */ int fatent_shift; struct fatent_operations *fatent_ops; diff --git a/fs/fat/inode.c b/fs/fat/inode.c index 7bf45aee56d7..1afa217d9050 100644 --- a/fs/fat/inode.c +++ b/fs/fat/inode.c @@ -1249,6 +1249,7 @@ int fat_fill_super(struct super_block *sb, void *data, int silent, struct inode *root_inode = NULL, *fat_inode = NULL; struct buffer_head *bh; struct fat_boot_sector *b; + struct fat_boot_bsx *bsx; struct msdos_sb_info *sbi; u16 logical_sector_size; u32 total_sectors, total_clusters, fat_clusters, rootdir_sectors; @@ -1393,6 +1394,8 @@ int fat_fill_super(struct super_block *sb, void *data, int silent, goto out_fail; } + bsx = (struct fat_boot_bsx *)(bh->b_data + FAT32_BSX_OFFSET); + fsinfo = (struct fat_boot_fsinfo *)fsinfo_bh->b_data; if (!IS_FSINFO(fsinfo)) { printk(KERN_WARNING "FAT: Invalid FSINFO signature: " @@ -1408,8 +1411,14 @@ int fat_fill_super(struct super_block *sb, void *data, int silent, } brelse(fsinfo_bh); + } else { + bsx = (struct fat_boot_bsx *)(bh->b_data + FAT16_BSX_OFFSET); } + /* interpret volume ID as a little endian 32 bit integer */ + sbi->vol_id = (((u32)bsx->vol_id[0]) | ((u32)bsx->vol_id[1] << 8) | + ((u32)bsx->vol_id[2] << 16) | ((u32)bsx->vol_id[3] << 24)); + sbi->dir_per_block = sb->s_blocksize / sizeof(struct msdos_dir_entry); sbi->dir_per_block_bits = ffs(sbi->dir_per_block) - 1; diff --git a/fs/jffs2/fs.c b/fs/jffs2/fs.c index 459d39d1ea0b..8a7ca85024c2 100644 --- a/fs/jffs2/fs.c +++ b/fs/jffs2/fs.c @@ -673,7 +673,9 @@ void jffs2_gc_release_page(struct jffs2_sb_info *c, static int jffs2_flash_setup(struct jffs2_sb_info *c) { int ret = 0; - if (jffs2_cleanmarker_oob(c)) { + if (c->mtd->type == MTD_NANDFLASH) { + if (!(c->mtd->flags & MTD_OOB_WRITEABLE)) + printk(KERN_INFO "JFFS2 doesn't use OOB.\n"); /* NAND flash... do setup accordingly */ ret = jffs2_nand_flash_setup(c); if (ret) @@ -706,7 +708,7 @@ static int jffs2_flash_setup(struct jffs2_sb_info *c) { void jffs2_flash_cleanup(struct jffs2_sb_info *c) { - if (jffs2_cleanmarker_oob(c)) { + if (c->mtd->type == MTD_NANDFLASH) { jffs2_nand_flash_cleanup(c); } diff --git a/fs/jffs2/os-linux.h b/fs/jffs2/os-linux.h index 4791aacf3084..9bf830b4f7c0 100644 --- a/fs/jffs2/os-linux.h +++ b/fs/jffs2/os-linux.h @@ -106,7 +106,7 @@ static inline void jffs2_init_inode_info(struct jffs2_inode_info *f) #define jffs2_can_mark_obsolete(c) (c->mtd->flags & (MTD_BIT_WRITEABLE)) #endif -#define jffs2_cleanmarker_oob(c) (c->mtd->type == MTD_NANDFLASH) +#define jffs2_cleanmarker_oob(c) (c->mtd->type == MTD_NANDFLASH && (c->mtd->flags & MTD_OOB_WRITEABLE)) #define jffs2_flash_write_oob(c, ofs, len, retlen, buf) ((c)->mtd->write_oob((c)->mtd, ofs, len, retlen, buf)) #define jffs2_flash_read_oob(c, ofs, len, retlen, buf) ((c)->mtd->read_oob((c)->mtd, ofs, len, retlen, buf)) diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c index 46f870d1cc36..a0d222496a3d 100644 --- a/fs/jffs2/scan.c +++ b/fs/jffs2/scan.c @@ -112,7 +112,7 @@ int jffs2_scan_medium(struct jffs2_sb_info *c) if (!flashbuf) { /* For NAND it's quicker to read a whole eraseblock at a time, apparently */ - if (jffs2_cleanmarker_oob(c)) + if (c->mtd->type == MTD_NANDFLASH) buf_size = c->sector_size; else buf_size = PAGE_SIZE; @@ -451,22 +451,24 @@ static int jffs2_scan_eraseblock (struct jffs2_sb_info *c, struct jffs2_eraseblo D1(printk(KERN_DEBUG "jffs2_scan_eraseblock(): Scanning block at 0x%x\n", ofs)); #ifdef CONFIG_JFFS2_FS_WRITEBUFFER - if (jffs2_cleanmarker_oob(c)) { + if (c->mtd->type == MTD_NANDFLASH) { int ret; if (c->mtd->block_isbad(c->mtd, jeb->offset)) return BLK_STATE_BADBLOCK; - ret = jffs2_check_nand_cleanmarker(c, jeb); - D2(printk(KERN_NOTICE "jffs_check_nand_cleanmarker returned %d\n",ret)); + if (jffs2_cleanmarker_oob(c)) { + ret = jffs2_check_nand_cleanmarker(c, jeb); + D2(printk(KERN_NOTICE "jffs_check_nand_cleanmarker returned %d\n", ret)); - /* Even if it's not found, we still scan to see - if the block is empty. We use this information - to decide whether to erase it or not. */ - switch (ret) { - case 0: cleanmarkerfound = 1; break; - case 1: break; - default: return ret; + /* Even if it's not found, we still scan to see + if the block is empty. We use this information + to decide whether to erase it or not. */ + switch (ret) { + case 0: cleanmarkerfound = 1; break; + case 1: break; + default: return ret; + } } } #endif diff --git a/fs/partitions/check.c b/fs/partitions/check.c index 5dcd4b0c5533..e37a2930189a 100644 --- a/fs/partitions/check.c +++ b/fs/partitions/check.c @@ -341,10 +341,18 @@ static void part_release(struct device *dev) kfree(p); } +static int part_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct hd_struct *part = dev_to_part(dev); + add_uevent_var(env, "PARTN=%u", part->partno); + return 0; +} + struct device_type part_type = { .name = "partition", .groups = part_attr_groups, .release = part_release, + .uevent = part_uevent, }; static void delete_partition_rcu_cb(struct rcu_head *head) diff --git a/include/linux/Kbuild b/include/linux/Kbuild index 9aa9bcadf869..ee0062a6a53a 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -52,6 +52,7 @@ header-y += comstats.h header-y += const.h header-y += cgroupstats.h header-y += cramfs_fs.h +header-y += cryptodev.h header-y += cycx_cfm.h header-y += dcbnl.h header-y += dlmconstants.h @@ -387,6 +388,29 @@ unifdef-y += wireless.h unifdef-y += xattr.h unifdef-y += xfrm.h +## i.MX specific files +unifdef-y += fsl_devices.h +unifdef-y += imx_adc.h +unifdef-y += ipu.h +unifdef-y += mxc_asrc.h +unifdef-y += mxc_mlb.h +unifdef-y += mxc_pf.h +unifdef-y += mxc_scc2_driver.h +unifdef-y += mxc_scc_driver.h +unifdef-y += mxc_srtc.h +unifdef-y += mxc_si4702.h +unifdef-y += mxc_sim_interface.h +unifdef-y += mxc_v4l2.h +unifdef-y += mxcfb.h +unifdef-y += pmic_adc.h +unifdef-y += pmic_battery.h +unifdef-y += pmic_external.h +unifdef-y += pmic_light.h +unifdef-y += pmic_rtc.h +unifdef-y += pmic_status.h +unifdef-y += soundcard.h +unifdef-y += pxp_dma.h + objhdr-y += version.h header-y += wimax.h header-y += wimax/ diff --git a/include/linux/android_pmem.h b/include/linux/android_pmem.h new file mode 100644 index 000000000000..f940946646e6 --- /dev/null +++ b/include/linux/android_pmem.h @@ -0,0 +1,91 @@ +/* include/linux/android_pmem.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _ANDROID_PMEM_H_ +#define _ANDROID_PMEM_H_ + +#define PMEM_IOCTL_MAGIC 'p' +#define PMEM_GET_PHYS _IOW(PMEM_IOCTL_MAGIC, 1, unsigned int) +#define PMEM_MAP _IOW(PMEM_IOCTL_MAGIC, 2, unsigned int) +#define PMEM_GET_SIZE _IOW(PMEM_IOCTL_MAGIC, 3, unsigned int) +#define PMEM_UNMAP _IOW(PMEM_IOCTL_MAGIC, 4, unsigned int) +/* This ioctl will allocate pmem space, backing the file, it will fail + * if the file already has an allocation, pass it the len as the argument + * to the ioctl */ +#define PMEM_ALLOCATE _IOW(PMEM_IOCTL_MAGIC, 5, unsigned int) +/* This will connect a one pmem file to another, pass the file that is already + * backed in memory as the argument to the ioctl + */ +#define PMEM_CONNECT _IOW(PMEM_IOCTL_MAGIC, 6, unsigned int) +/* Returns the total size of the pmem region it is sent to as a pmem_region + * struct (with offset set to 0). + */ +#define PMEM_GET_TOTAL_SIZE _IOW(PMEM_IOCTL_MAGIC, 7, unsigned int) +#define PMEM_CACHE_FLUSH _IOW(PMEM_IOCTL_MAGIC, 8, unsigned int) + +struct android_pmem_platform_data { + const char *name; + /* starting physical address of memory region */ + unsigned long start; + /* size of memory region */ + unsigned long size; + /* set to indicate the region should not be managed with an allocator */ + unsigned no_allocator; + /* set to indicate maps of this region should be cached, if a mix of + * cached and uncached is desired, set this and open the device with + * O_SYNC to get an uncached region */ + unsigned cached; + /* The MSM7k has bits to enable a write buffer in the bus controller*/ + unsigned buffered; +}; + +struct pmem_region { + unsigned long offset; + unsigned long len; +}; + +#ifdef CONFIG_ANDROID_PMEM +int is_pmem_file(struct file *file); +int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart, + unsigned long *end, struct file **filp); +int get_pmem_user_addr(struct file *file, unsigned long *start, + unsigned long *end); +void put_pmem_file(struct file *file); +void flush_pmem_file(struct file *file, unsigned long start, unsigned long len); +int pmem_setup(struct android_pmem_platform_data *pdata, + long (*ioctl)(struct file *, unsigned int, unsigned long), + int (*release)(struct inode *, struct file *)); +int pmem_remap(struct pmem_region *region, struct file *file, + unsigned operation); + +#else +static inline int is_pmem_file(struct file *file) { return 0; } +static inline int get_pmem_file(int fd, unsigned long *start, + unsigned long *vstart, unsigned long *end, + struct file **filp) { return -ENOSYS; } +static inline int get_pmem_user_addr(struct file *file, unsigned long *start, + unsigned long *end) { return -ENOSYS; } +static inline void put_pmem_file(struct file *file) { return; } +static inline void flush_pmem_file(struct file *file, unsigned long start, + unsigned long len) { return; } +static inline int pmem_setup(struct android_pmem_platform_data *pdata, + long (*ioctl)(struct file *, unsigned int, unsigned long), + int (*release)(struct inode *, struct file *)) { return -ENOSYS; } + +static inline int pmem_remap(struct pmem_region *region, struct file *file, + unsigned operation) { return -ENOSYS; } +#endif + +#endif /* _ANDROID_PMEM_H_ */ diff --git a/include/linux/ashmem.h b/include/linux/ashmem.h new file mode 100644 index 000000000000..1976b10ef93e --- /dev/null +++ b/include/linux/ashmem.h @@ -0,0 +1,48 @@ +/* + * include/linux/ashmem.h + * + * Copyright 2008 Google Inc. + * Author: Robert Love + * + * This file is dual licensed. It may be redistributed and/or modified + * under the terms of the Apache 2.0 License OR version 2 of the GNU + * General Public License. + */ + +#ifndef _LINUX_ASHMEM_H +#define _LINUX_ASHMEM_H + +#include +#include + +#define ASHMEM_NAME_LEN 256 + +#define ASHMEM_NAME_DEF "dev/ashmem" + +/* Return values from ASHMEM_PIN: Was the mapping purged while unpinned? */ +#define ASHMEM_NOT_PURGED 0 +#define ASHMEM_WAS_PURGED 1 + +/* Return values from ASHMEM_GET_PIN_STATUS: Is the mapping pinned? */ +#define ASHMEM_IS_UNPINNED 0 +#define ASHMEM_IS_PINNED 1 + +struct ashmem_pin { + __u32 offset; /* offset into region, in bytes, page-aligned */ + __u32 len; /* length forward from offset, in bytes, page-aligned */ +}; + +#define __ASHMEMIOC 0x77 + +#define ASHMEM_SET_NAME _IOW(__ASHMEMIOC, 1, char[ASHMEM_NAME_LEN]) +#define ASHMEM_GET_NAME _IOR(__ASHMEMIOC, 2, char[ASHMEM_NAME_LEN]) +#define ASHMEM_SET_SIZE _IOW(__ASHMEMIOC, 3, size_t) +#define ASHMEM_GET_SIZE _IO(__ASHMEMIOC, 4) +#define ASHMEM_SET_PROT_MASK _IOW(__ASHMEMIOC, 5, unsigned long) +#define ASHMEM_GET_PROT_MASK _IO(__ASHMEMIOC, 6) +#define ASHMEM_PIN _IOW(__ASHMEMIOC, 7, struct ashmem_pin) +#define ASHMEM_UNPIN _IOW(__ASHMEMIOC, 8, struct ashmem_pin) +#define ASHMEM_GET_PIN_STATUS _IO(__ASHMEMIOC, 9) +#define ASHMEM_PURGE_ALL_CACHES _IO(__ASHMEMIOC, 10) + +#endif /* _LINUX_ASHMEM_H */ diff --git a/include/linux/cryptodev.h b/include/linux/cryptodev.h new file mode 100644 index 000000000000..0f8f6705cdc9 --- /dev/null +++ b/include/linux/cryptodev.h @@ -0,0 +1,82 @@ +/* + * Driver for /dev/crypto device (aka CryptoDev) + * + * Copyright (c) 2004 Michal Ludvig , SuSE Labs + * + * Structures and ioctl command names were taken from + * OpenBSD to preserve compatibility with their API. + * + */ + +#ifndef _CRYPTODEV_H +#define _CRYPTODEV_H + +#ifndef __KERNEL__ +#include +#endif + +#define CRYPTODEV_MINOR MISC_DYNAMIC_MINOR + +#define CRYPTO_FLAG_ECB 0x0000 +#define CRYPTO_FLAG_CBC 0x0001 +#define CRYPTO_FLAG_CFB 0x0002 +#define CRYPTO_FLAG_OFB 0x0003 +#define CRYPTO_FLAG_CTR 0x0004 +#define CRYPTO_FLAG_HMAC 0x0010 +#define CRYPTO_FLAG_MASK 0x00FF + +#define CRYPTO_CIPHER_NAME 0x0100 +#define CRYPTO_CIPHER_NAME_CBC (CRYPTO_CIPHER_NAME | CRYPTO_FLAG_CBC) +#define CRYPTO_HASH_NAME 0x0200 +#define CRYPTO_HASH_NAME_HMAC (CRYPTO_HASH_NAME | CRYPTO_FLAG_HMAC) + +/* ioctl parameter to create a session */ +struct session_op { + unsigned int cipher; /* e.g. CRYPTO_DES_CBC */ + unsigned int mac; /* e.g. CRYPTO_MD5_HMAC */ + char *alg_name; /* set cipher=CRYPTO_CIPHER_NAME + or mac=CRYPTO_HASH_NAME */ + #define MAX_ALG_NAME_LEN 128 + size_t alg_namelen; + + size_t keylen; /* cipher key */ + char *key; + int mackeylen; /* mac key */ + char *mackey; + + /* Return values */ + unsigned int blocksize; /* selected algorithm's block size */ + uint32_t ses; /* session ID */ +}; + +/* ioctl parameter to request a crypt/decrypt operation against a session */ +struct crypt_op { + uint32_t ses; /* from session_op->ses */ + #define COP_DECRYPT 0 + #define COP_ENCRYPT 1 + uint32_t op; /* ie. COP_ENCRYPT */ + uint32_t flags; /* unused */ + + size_t len; + char *src, *dst; + char *mac; + char *iv; +}; + +/* clone original filedescriptor */ +#define CRIOGET _IOWR('c', 100, uint32_t) + +/* create crypto session */ +#define CIOCGSESSION _IOWR('c', 101, struct session_op) + +/* finish crypto session */ +#define CIOCFSESSION _IOW('c', 102, uint32_t) + +/* request encryption/decryptions of a given buffer */ +#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) + +/* ioctl()s for asym-crypto. Not yet supported. */ +#define CIOCKEY _IOWR('c', 104, void *) +#define CIOCASYMFEAT _IOR('c', 105, uint32_t) + +#endif /* _CRYPTODEV_H */ diff --git a/include/linux/fec.h b/include/linux/fec.h index 5d3523d8dd0c..e2d160844bba 100644 --- a/include/linux/fec.h +++ b/include/linux/fec.h @@ -1,6 +1,7 @@ /* include/linux/fec.h * * Copyright (c) 2009 Orex Computed Radiography + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. * Baruch Siach * * Header file for the FEC platform data @@ -12,10 +13,33 @@ #ifndef __LINUX_FEC_H__ #define __LINUX_FEC_H__ +#include #include struct fec_platform_data { phy_interface_t phy; + unsigned char mac[ETH_ALEN]; + int (*init)(void); + int (*uninit)(void); + struct regulator *vddio_reg; +}; + +struct switch_platform_data { + int id; + int hash_table; + unsigned int *switch_hw; + struct fec_platform_data *fec_enet; + void (*request_intrs)(struct net_device *dev, + irqreturn_t (*)(int, void *), + void *irq_privatedata); + void (*set_mii)(struct net_device *dev); + void (*get_mac)(struct net_device *dev); + void (*enable_phy_intr)(void); + void (*disable_phy_intr)(void); + void (*phy_ack_intr)(void); + void (*localhw_setup)(void); + void (*uncache)(unsigned long addr); + void (*platform_flush_cache)(void); }; #endif diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index 28e33fea5107..0e6e744f828c 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -6,7 +6,7 @@ * * Maintainer: Kumar Gala * - * Copyright 2004 Freescale Semiconductor, Inc + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -50,6 +50,15 @@ enum fsl_usb2_operating_modes { FSL_USB2_DR_OTG, }; +/* this used for usb port type */ +enum fsl_usb2_modes { + FSL_USB_DR_HOST, + FSL_USB_DR_DEVICE, + FSL_USB_MPH_HOST1, + FSL_USB_MPH_HOST2, + FSL_USB_UNKNOWN, /* unkonwn status */ +}; + enum fsl_usb2_phy_modes { FSL_USB2_PHY_NONE, FSL_USB2_PHY_ULPI, @@ -58,17 +67,88 @@ enum fsl_usb2_phy_modes { FSL_USB2_PHY_SERIAL, }; +enum usb_wakeup_event { + WAKEUP_EVENT_INVALID, + WAKEUP_EVENT_VBUS, + WAKEUP_EVENT_ID, + WAKEUP_EVENT_DPDM, /* for remote wakeup */ +}; + +struct fsl_usb2_wakeup_platform_data; +struct platform_device; struct fsl_usb2_platform_data { /* board specific information */ enum fsl_usb2_operating_modes operating_mode; enum fsl_usb2_phy_modes phy_mode; unsigned int port_enables; + char *name; /* pretty print */ + int (*platform_init) (struct platform_device *); + void (*platform_uninit) (struct fsl_usb2_platform_data *); + void __iomem *regs; /* ioremap'd register base */ + u32 phy_regs; /* usb phy register base */ + u32 xcvr_type; /* PORTSC_PTS_* */ + char *transceiver; /* transceiver name */ + unsigned power_budget; /* for hcd->power_budget */ + struct platform_device *pdev; + struct fsl_xcvr_ops *xcvr_ops; + struct fsl_xcvr_power *xcvr_pwr; + int (*gpio_usb_active) (void); + void (*gpio_usb_inactive) (void); + void (*usb_clock_for_pm) (bool); + void (*platform_suspend)(struct fsl_usb2_platform_data *); + void (*platform_resume)(struct fsl_usb2_platform_data *); + void (*wake_up_enable)(struct fsl_usb2_platform_data *pdata, bool on); + void (*phy_lowpower_suspend)(struct fsl_usb2_platform_data *pdata, bool on); + void (*platform_driver_vbus)(bool on); /* platform special function for vbus shutdown/open */ + enum usb_wakeup_event (*is_wakeup_event)(struct fsl_usb2_platform_data *pdata); + void (*wakeup_handler)(struct fsl_usb2_platform_data *pdata); + unsigned big_endian_mmio:1; + unsigned big_endian_desc:1; + unsigned es:1; /* need USBMODE:ES */ + unsigned have_sysif_regs:1; + unsigned le_setup_buf:1; + unsigned change_ahb_burst:1; + unsigned ahb_burst_mode:3; + unsigned suspended:1; + unsigned already_suspended:1; + unsigned lowpower:1; + unsigned irq_delay:1; + unsigned wakeup_event:1; + struct fsl_usb2_wakeup_platform_data *wakeup_pdata; + + u32 id_gpio; + /* register save area for suspend/resume */ + u32 pm_command; + u32 pm_status; + u32 pm_intr_enable; + u32 pm_frame_index; + u32 pm_segment; + u32 pm_frame_list; + u32 pm_async_next; + u32 pm_configured_flag; + u32 pm_portsc; }; /* Flags in fsl_usb2_mph_platform_data */ #define FSL_USB2_PORT0_ENABLED 0x00000001 #define FSL_USB2_PORT1_ENABLED 0x00000002 +struct fsl_usb2_wakeup_platform_data { + char *name; + void (*usb_clock_for_pm) (bool); + void (*usb_wakeup_exhandle) (void); + struct fsl_usb2_platform_data *usb_pdata[3]; + /* This waitqueue is used to wait "usb_wakeup thread" to finish + * during system resume routine. "usb_wakeup theard" should be finished + * prior to usb resume routine. + */ + wait_queue_head_t wq; + /* This flag is used to indicate the "usb_wakeup thread" is finished during + * usb wakeup routine. + */ + bool usb_wakeup_is_pending; +}; + struct spi_device; struct fsl_spi_platform_data { @@ -86,6 +166,455 @@ struct fsl_spi_platform_data { u32 sysclk; }; +struct fsl_ata_platform_data { + int adma_flag; /* AMDA mode is used or not, 1:used.*/ + int udma_mask; /* UDMA modes h/w can handle */ + int mwdma_mask; /* MDMA modes h/w can handle */ + int pio_mask; /* PIO modes h/w can handle */ + int fifo_alarm; /* value for fifo_alarm reg */ + int max_sg; /* longest sglist h/w can handle */ + int (*init)(struct platform_device *pdev); + void (*exit)(void); + char *io_reg; + char *core_reg; +}; + +/*! + * This structure is used to define the One wire platform data. + * It includes search rom accelerator. + */ +struct mxc_w1_config { + int search_rom_accelerator; +}; +/*! + * This structure is used to define the SPI master controller's platform + * data. It includes the SPI bus number and the maximum number of + * slaves/chips it supports. + */ +struct mxc_spi_master { + /*! + * SPI Master's bus number. + */ + unsigned int bus_num; + /*! + * SPI Master's maximum number of chip selects. + */ + unsigned int maxchipselect; + /*! + * CSPI Hardware Version. + */ + unsigned int spi_version; + /*! + * CSPI chipselect pin table. + * Workaround for ecspi chipselect pin may not keep correct level when + * idle. + */ + void (*chipselect_active) (int cspi_mode, int status, int chipselect); + void (*chipselect_inactive) (int cspi_mode, int status, int chipselect); +}; + +struct mxc_ipu_config { + int rev; + void (*reset) (void); + struct clk *di_clk[2]; + struct clk *csi_clk[2]; +}; + +struct mxc_ir_platform_data { + int uart_ir_mux; + int ir_rx_invert; + int ir_tx_invert; + struct clk *uart_clk; +}; + +struct mxc_i2c_platform_data { + u32 i2c_clk; +}; + +/* + * This struct is to define the number of SSIs on a platform, + * DAM source port config, DAM external port config, + * regulator names, and other stuff audio needs. + */ +struct mxc_audio_platform_data { + int ssi_num; + int src_port; + int ext_port; + + int intr_id_hp; + int ext_ram; + struct clk *ssi_clk[2]; + + int hp_irq; + int (*hp_status) (void); + + int sysclk; + + int (*init) (void); /* board specific init */ + int (*amp_enable) (int enable); + int (*clock_enable) (int enable); + int (*finit) (void); /* board specific finit */ + void *priv; /* used by board specific functions */ +}; + +struct mxc_spdif_platform_data { + int spdif_tx; + int spdif_rx; + int spdif_clk_44100; + int spdif_clk_48000; + int spdif_clkid; + struct clk *spdif_clk; + struct clk *spdif_core_clk; + struct clk *spdif_audio_clk; +}; + +struct mxc_asrc_platform_data { + struct clk *asrc_core_clk; + struct clk *asrc_audio_clk; + unsigned int channel_bits; + int clk_map_ver; +}; + +struct mxc_bt_platform_data { + char *bt_vdd; + char *bt_vdd_parent; + char *bt_vusb; + char *bt_vusb_parent; + void (*bt_reset) (void); +}; + +struct mxc_audio_codec_platform_data { + char *core_regulator; + char *io_regulator; + char *analog_regulator; + void (*pwdn)(int pwdn); +}; + +struct mxc_lightsensor_platform_data { + char *vdd_reg; + int rext; +}; + +struct mxc_fb_platform_data { + struct fb_videomode *mode; + int num_modes; + char *mode_str; + u32 interface_pix_fmt; +}; + +struct mxc_lcd_platform_data { + char *io_reg; + char *core_reg; + char *analog_reg; + void (*reset) (void); +}; + + +struct mxc_tsc_platform_data { + char *vdd_reg; + int penup_threshold; + void (*active) (void); + void (*inactive) (void); +}; + +struct mxc_tvout_platform_data { + char *io_reg; + char *core_reg; + char *analog_reg; + u32 detect_line; +}; + +struct mxc_tvin_platform_data { + char *dvddio_reg; + char *dvdd_reg; + char *avdd_reg; + char *pvdd_reg; + void (*pwdn) (int pwdn); + void (*reset) (void); + bool cvbs; +}; + +struct mxc_epdc_fb_mode { + struct fb_videomode *vmode; + int vscan_holdoff; + int sdoed_width; + int sdoed_delay; + int sdoez_width; + int sdoez_delay; + int gdclk_hp_offs; + int gdsp_offs; + int gdoe_offs; + int gdclk_offs; + int num_ce; +}; + +struct mxc_epdc_fb_platform_data { + struct mxc_epdc_fb_mode *epdc_mode; + int num_modes; + void (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); +}; + +struct mxc_pm_platform_data { + void (*suspend_enter) (void); + void (*suspend_exit) (void); +}; + +/*! Platform data for the IDE drive structure. */ +struct mxc_ide_platform_data { + char *power_drive; /*!< The power pointer */ + char *power_io; /*!< The power pointer */ +}; + +struct mxc_camera_platform_data { + char *core_regulator; + char *io_regulator; + char *analog_regulator; + char *gpo_regulator; + u32 mclk; + u32 csi; + void (*pwdn)(int pwdn); +}; + +/*gpo1-3 is in fixed state by hardware design, + * only deal with reset pin and clock_enable pin + * only poll mode can be used to control the chip, + * interrupt mode is not supported by 3ds*/ +struct mxc_fm_platform_data { + char *reg_vio; + char *reg_vdd; + void (*gpio_get) (void); + void (*gpio_put) (void); + void (*reset) (void); + void (*clock_ctl) (int flag); + u8 sksnr; /*0,disable;1,most stop;0xf,fewest stop*/ + u8 skcnt; /*0,disable;1,most stop;0xf,fewest stop*/ + /* + 00 = 87.5-108 MHz (USA,Europe) (Default). + 01 = 76-108 MHz (Japan wide band). + 10 = 76-90 MHz (Japan). + 11 = Reserved. + */ + u8 band; + /* + 00 = 200 kHz (USA, Australia) (default). + 01 = 100 kHz (Europe, Japan). + 10 = 50 kHz. + */ + u8 space; + u8 seekth; +}; + +struct mxc_mma7450_platform_data { + char *reg_dvdd_io; + char *reg_avdd; + void (*gpio_pin_get) (void); + void (*gpio_pin_put) (void); + int int1; + int int2; +}; + +struct mxc_keyp_platform_data { + u16 *matrix; + void (*active) (void); + void (*inactive) (void); + char *vdd_reg; +}; + +struct mxc_unifi_platform_data { + void (*hardreset) (int pin_level); + void (*enable) (int en); + /* power parameters */ + char *reg_gpo1; + char *reg_gpo2; + char *reg_1v5_ana_bb; + char *reg_vdd_vpa; + char *reg_1v5_dd; + + int host_id; + + void *priv; +}; + +struct mxc_gps_platform_data { + char *core_reg; + char *analog_reg; + struct regulator *gps_regu_core; + struct regulator *gps_regu_analog; +}; + +struct mxc_mlb_platform_data { + u32 buf_address; + u32 phy_address; + char *reg_nvcc; + char *mlb_clk; +}; + +struct flexcan_platform_data { + char *core_reg; + char *io_reg; + char *root_clk_id; + void (*xcvr_enable) (int id, int en); + void (*active) (int id); + void (*inactive) (int id); + /* word 1 */ + unsigned int br_presdiv:8; + unsigned int br_rjw:2; + unsigned int br_propseg:3; + unsigned int br_pseg1:3; + unsigned int br_pseg2:3; + unsigned int maxmb:6; + unsigned int xmit_maxmb:6; + unsigned int wd1_resv:1; + + /* word 2 */ + unsigned int fifo:1; + unsigned int wakeup:1; + unsigned int srx_dis:1; + unsigned int wak_src:1; + unsigned int bcc:1; + unsigned int lprio:1; + unsigned int abort:1; + unsigned int br_clksrc:1; + unsigned int loopback:1; + unsigned int smp:1; + unsigned int boff_rec:1; + unsigned int tsyn:1; + unsigned int listen:1; + unsigned int ext_msg:1; + unsigned int std_msg:1; +}; + +struct tve_platform_data { + char *dac_reg; + char *dig_reg; +}; + +struct ldb_platform_data { + char *lvds_bg_reg; + u32 ext_ref; +}; + + struct mxc_vpu_platform_data { + void (*reset) (void); +}; + +struct mxc_esai_platform_data { + void (*activate_esai_ports) (void); + void (*deactivate_esai_ports) (void); +}; + +struct mxc_pwm_platform_data { + int pwmo_invert; + void (*enable_pwm_pad) (void); + void (*disable_pwm_pad) (void); +}; + +/* The name that links the i.MX NAND Flash Controller driver to its devices. */ + +#define IMX_NFC_DRIVER_NAME ("imx_nfc") + +/* Resource names for the i.MX NAND Flash Controller driver. */ + +#define IMX_NFC_BUFFERS_ADDR_RES_NAME \ + ("i.MX NAND Flash Controller Buffer") +#define IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME \ + ("i.MX NAND Flash Controller Primary Registers") +#define IMX_NFC_SECONDARY_REGS_ADDR_RES_NAME \ + ("i.MX NAND Flash Controller Secondary Registers") +#define IMX_NFC_INTERRUPT_RES_NAME \ + ("i.MX NAND Flash Controller Interrupt") + +/** + * struct imx_nfc_platform_data - i.MX NFC driver platform data. + * + * This structure communicates information to the i.MX NFC driver that can't be + * expressed as resources. + * + * @nfc_major_version: The "major version" of the NFC hardware. + * @nfc_minor_version: The "minor version" of the NFC hardware. + * @force_ce: If true, this flag causes the driver to assert the + * hardware chip enable signal for the currently selected + * chip as long as the MTD NAND Flash HAL has the chip + * selected (not just when an I/O transaction is in + * progress). + * @target_cycle_in_ns: The target read and write cycle period, in nanoseconds. + * NAND Flash part data sheets give minimum times for read + * and write cycles in nanoseconds (usually tRC and tWC, + * respectively). Set this value to the maximum of these + * two parameters. The driver will set the NFC clock as + * close as possible without violating this value. + * @clock_name: The name of the clock used by the NAND Flash controller. + * @init: A pointer to a function the driver must call so the + * platform can prepare for this device to operate. This + * pointer may be NULL. + * @exit: A pointer to a function the driver must call so the + * platform clean up after this device stops operating. + * This pointer may be NULL. + * @set_page_size: A pointer to a function the driver can call to set the + * page size. This pointer may be NULL. + * + * For some i.MX SoC's, the NFC gets information about the + * page size from signals driven by a system register + * outside the NFC. The address and format of this external + * register varies across SoC's. In other SoC's, the NFC + * still receives this signal, but it is overridden by a + * page size register in the NFC itself. + * + * For SoC's where the page size *must* be set in an + * external register, the driver must rely on a platform- + * specific function, and this member must point to it. + * + * For SoC's where the NFC has its own page size register, + * the driver will set that register itself and ignore the + * external signals. In this case, there's no need for the + * platform-specific function and this member must be NULL. + * + * This function accepts the page size in bytes (MTD calls + * this the "writesize") discovered by the NAND Flash MTD + * base driver (e.g., 512, 2048, 4096). This size refers + * specifically to the the data bytes in the page, *not* + * including out-of-band bytes. The return value is zero if + * the operation succeeded. The driver does *not* view a + * non-zero value as an error code - only an indication of + * failure. The driver will decide for itself what error + * code to return to its caller. + * @interleave: Indicates that the driver should "interleave" the NAND + * Flash chips it finds. If true, the driver will aggregate + * the chips "horizontally" such that MTD will see a single + * chip with a potentially very large page size. This can + * improve write performance for some applications. + * @partitions: An optional pointer to an array of partitions. If this + * is NULL, the driver will create a single MTD that + * represents the entire medium. + * @partition_count: The number of elements in the partition array. + */ + +struct imx_nfc_platform_data { + unsigned int nfc_major_version; + unsigned int nfc_minor_version; + int force_ce; + unsigned int target_cycle_in_ns; + char *clock_name; + int (*init)(void); + void (*exit)(void); + int (*set_page_size)(unsigned int data_size_in_bytes); + int interleave; + struct mtd_partition *partitions; + unsigned int partition_count; +}; + +struct mxc_sim_platform_data { + unsigned int clk_rate; + char *clock_sim; + char *power_sim; + int (*init)(struct platform_device *pdev); + void (*exit)(void); + unsigned int detect; /* 1 have detect pin, 0 not */ +}; + struct mpc8xx_pcmcia_ops { void(*hw_ctrl)(int slot, int enable); int(*voltage_set)(int slot, int vcc, int vpp); @@ -101,4 +630,15 @@ int fsl_deep_sleep(void); static inline int fsl_deep_sleep(void) { return 0; } #endif +struct mxs_perfmon_bit_config { + int reg; + int field; + const char *name; +}; + +struct mxs_platform_perfmon_data { + struct mxs_perfmon_bit_config *bit_config_tab; + int bit_config_cnt; +}; + #endif /* _FSL_DEVICE_H_ */ diff --git a/include/linux/gpmi-nfc.h b/include/linux/gpmi-nfc.h new file mode 100644 index 000000000000..2311fd6678b2 --- /dev/null +++ b/include/linux/gpmi-nfc.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __INCLUDE_LINUX_DEVICE_H +#define __INCLUDE_LINUX_DEVICE_H + +/* The name that links together the GPMI NFC driver data structures. */ + +#define GPMI_NFC_DRIVER_NAME "gpmi-nfc" + +/* Resource names for the GPMI NFC driver. */ + +#define GPMI_NFC_GPMI_REGS_ADDR_RES_NAME "GPMI NFC GPMI Registers" +#define GPMI_NFC_GPMI_INTERRUPT_RES_NAME "GPMI NFC GPMI Interrupt" +#define GPMI_NFC_BCH_REGS_ADDR_RES_NAME "GPMI NFC BCH Registers" +#define GPMI_NFC_BCH_INTERRUPT_RES_NAME "GPMI NFC BCH Interrupt" +#define GPMI_NFC_DMA_CHANNELS_RES_NAME "GPMI NFC DMA Channels" +#define GPMI_NFC_DMA_INTERRUPT_RES_NAME "GPMI NFC DMA Interrupt" + +/** + * struct gpmi_nfc_platform_data - GPMI NFC driver platform data. + * + * This structure communicates platform-specific information to the GPMI NFC + * driver that can't be expressed as resources. + * + * @nfc_version: The version of the NFC hardware. This single number + * represents a collection of NFC behaviors and + * attributes the driver must comprehend. See the + * driver code for details about what each version + * means. + * @boot_rom_version: The version of the Boot ROM. This single number + * represents a collection of Boot ROM behaviors and + * attributes the driver must comprehend. See the + * driver code for details about what each version + * means. + * @clock_name: The name of the clock that drives the NFC. + * @platform_init: A pointer to a function the driver will call to + * initialize the platform (e.g., set up the pin mux). + * The max_chip_count parameter is the maximum number + * of chips the driver is to support. If the platform + * can't be configured to support this number, the + * function should print a message and return a + * non-zero value . The driver will only view this as + * an indication of failure and will choose its own + * error code to return. + * @platform_exit: A pointer to a function the driver will call to + * exit the platform (e.g., free pins). The + * max_chip_count parameter is same value passed to + * the platform init function. + * @min_prop_delay_in_ns: Minimum propagation delay of GPMI signals to and + * from the NAND Flash device, in nanoseconds. + * @max_prop_delay_in_ns: Maximum propagation delay of GPMI signals to and + * from the NAND Flash device, in nanoseconds. + * @max_chip_count: The maximum number of chips for which the driver + * should configure the hardware. This value most + * likely reflects the number of pins that are + * connected to a NAND Flash device. If this is + * greater than the SoC hardware can support, the + * driver will print a message and fail to initialize. + * @boot_area_size_in_bytes: The amount of space reserved for each boot area. + * Note that some Boot ROMs call for multiple boot + * areas. If this value is zero, the driver will not + * construct special partitions for boot areas. + * @partition_source_types: An array of strings that name sources of + * partitioning information (e.g., the boot loader, + * kernel command line, etc.). The function + * parse_mtd_partitions() recognizes these names and + * applies the appropriate "plugins" to discover + * partitioning information. If any is found, it will + * be applied to the "general use" MTD (it will NOT + * override the boot area protection mechanism). + * @partitions: An optional pointer to an array of partition + * descriptions. If the driver finds no other + * partitioning information, it will apply these + * partitions to the "general use" MTD (they do NOT + * override the boot area protection mechanism). + * @partition_count: The number of elements in the partitions array. + */ + +struct gpmi_nfc_platform_data { + + /* Version information. */ + + unsigned int nfc_version; + unsigned int boot_rom_version; + + /* SoC hardware information. */ + + char *clock_name; + int (*platform_init)(unsigned int max_chip_count); + void (*platform_exit)(unsigned int max_chip_count); + + /* NAND Flash information. */ + + unsigned int min_prop_delay_in_ns; + unsigned int max_prop_delay_in_ns; + unsigned int max_chip_count; + + /* Medium information. */ + + uint32_t boot_area_size_in_bytes; + const char **partition_source_types; + struct mtd_partition *partitions; + unsigned partition_count; + +}; + +#endif diff --git a/include/linux/i2c/mpr.h b/include/linux/i2c/mpr.h new file mode 100644 index 000000000000..ded00db775f3 --- /dev/null +++ b/include/linux/i2c/mpr.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mpr.h - Header file for Freescale MPR121 Capacitive Touch Sensor Controllor */ + +#ifndef MPR_H +#define MPR_H + +/* Register definitions */ +#define ELE_TOUCH_STATUS_0_ADDR 0x0 +#define ELE_TOUCH_STATUS_1_ADDR 0X1 +#define MHD_RISING_ADDR 0x2b +#define NHD_RISING_ADDR 0x2c +#define NCL_RISING_ADDR 0x2d +#define FDL_RISING_ADDR 0x2e +#define MHD_FALLING_ADDR 0x2f +#define NHD_FALLING_ADDR 0x30 +#define NCL_FALLING_ADDR 0x31 +#define FDL_FALLING_ADDR 0x32 +#define ELE0_TOUCH_THRESHOLD_ADDR 0x41 +#define ELE0_RELEASE_THRESHOLD_ADDR 0x42 +/* ELE0...ELE11's threshold will set in a loop */ +#define AFE_CONF_ADDR 0x5c +#define FILTER_CONF_ADDR 0x5d + +/* ELECTRODE_CONF: this register is most important register, it + * control how many of electrode is enabled. If you set this register + * to 0x0, it make the sensor going to suspend mode. Other value(low + * bit is non-zero) will make the sensor into Run mode. This register + * should be write at last. + */ +#define ELECTRODE_CONF_ADDR 0x5e +#define AUTO_CONFIG_CTRL_ADDR 0x7b +/* AUTO_CONFIG_USL: Upper Limit for auto baseline search, this + * register is related to VDD supplied on your board, the value of + * this register is calc by EQ: `((VDD-0.7)/VDD) * 256`. + * AUTO_CONFIG_LSL: Low Limit of auto baseline search. This is 65% of + * USL AUTO_CONFIG_TL: The Traget Level of auto baseline search, This + * is 90% of USL */ +#define AUTO_CONFIG_USL_ADDR 0x7d +#define AUTO_CONFIG_LSL_ADDR 0x7e +#define AUTO_CONFIG_TL_ADDR 0x7f + +/* Threshold of touch/release trigger */ +#define TOUCH_THRESHOLD 0x0f +#define RELEASE_THRESHOLD 0x0a +/* Mask Button bits of STATUS_0 & STATUS_1 register */ +#define TOUCH_STATUS_MASK 0xfff +/* MPR121 have 12 electrodes */ +#define MPR121_MAX_KEY_COUNT 12 + + +/** + * @keycount: how many key maped + * @vdd_uv: voltage of vdd supply the chip in uV + * @matrix: maxtrix of keys + * @wakeup: can key wake up system. + */ +struct mpr121_platform_data { + u16 keycount; + u16 *matrix; + int wakeup; + int vdd_uv; +}; + +#endif diff --git a/include/linux/imx_adc.h b/include/linux/imx_adc.h new file mode 100644 index 000000000000..d04fa7d4f1ec --- /dev/null +++ b/include/linux/imx_adc.h @@ -0,0 +1,275 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef __ASM_ARCH_IMX_ADC_H__ +#define __ASM_ARCH_IMX_ADC_H__ + +/*! + * @defgroup IMX_ADC Digitizer Driver + * @ingroup IMX_DRVRS + */ + +/*! + * @file arch-mxc/imx_adc.h + * @brief This is the header of IMX ADC driver. + * + * @ingroup IMX_ADC + */ + +#include + +/*! + * @enum IMX_ADC_STATUS + * @brief Define return values for all IMX_ADC APIs. + * + * These return values are used by all of the IMX_ADC APIs. + * + * @ingroup IMX_ADC + */ +enum IMX_ADC_STATUS { + /*! The requested operation was successfully completed. */ + IMX_ADC_SUCCESS = 0, + /*! The requested operation could not be completed due to an error. */ + IMX_ADC_ERROR = -1, + /*! + * The requested operation failed because one or more of the + * parameters was invalid. + */ + IMX_ADC_PARAMETER_ERROR = -2, + /*! + * The requested operation could not be completed because the ADC + * hardware does not support it. + */ + IMX_ADC_NOT_SUPPORTED = -3, + /*! Error in malloc function */ + IMX_ADC_MALLOC_ERROR = -5, + /*! Error in un-subscribe event */ + IMX_ADC_UNSUBSCRIBE_ERROR = -6, + /*! Event occur and not subscribed */ + IMX_ADC_EVENT_NOT_SUBSCRIBED = -7, + /*! Error - bad call back */ + IMX_ADC_EVENT_CALL_BACK = -8, + /*! + * The requested operation could not be completed because there + * are too many ADC client requests + */ + IMX_ADC_CLIENT_NBOVERFLOW = -9, +}; + +/* + * Macros implementing error handling + */ +#define CHECK_ERROR(a) \ +do { \ + int ret = (a); \ + if (ret != IMX_ADC_SUCCESS) \ + return ret; \ +} while (0) + +#define CHECK_ERROR_KFREE(func, freeptrs) \ +do { \ + int ret = (func); \ + if (ret != IMX_ADC_SUCCESS) { \ + freeptrs; \ + return ret; \ + } \ +} while (0) + +#define MOD_NAME "mxcadc" + +/*! + * @name IOCTL user space interface + */ + +/*! + * Initialize ADC. + * Argument type: none. + */ +#define IMX_ADC_INIT _IO('p', 0xb0) +/*! + * De-initialize ADC. + * Argument type: none. + */ +#define IMX_ADC_DEINIT _IO('p', 0xb1) +/*! + * Convert one channel. + * Argument type: pointer to t_adc_convert_param. + */ +#define IMX_ADC_CONVERT _IOWR('p', 0xb2, int) +/*! + * Convert multiple channels. + * Argument type: pointer to t_adc_convert_param. + */ +#define IMX_ADC_CONVERT_MULTICHANNEL _IOWR('p', 0xb4, int) + +/*! @{ */ +/*! + * @name Touch Screen minimum and maximum values + */ +#define IMX_ADC_DEVICE "/dev/imx_adc" + +/* + * Maximun allowed variation in the three X/Y co-ordinates acquired from + * touch screen + */ +#define DELTA_Y_MAX 100 +#define DELTA_X_MAX 100 + +/* Upon clearing the filter, this is the delay in restarting the filter */ +#define FILTER_MIN_DELAY 4 + +/* Length of X and Y touch screen filters */ +#define FILTLEN 3 + +#define TS_X_MAX 1000 +#define TS_Y_MAX 1000 + +#define TS_X_MIN 80 +#define TS_Y_MIN 80 + +/*! @} */ +/*! + * This enumeration defines input channels for IMX ADC + */ + +enum t_channel { + TS_X_POS, + TS_Y_POS, + GER_PURPOSE_ADC0, + GER_PURPOSE_ADC1, + GER_PURPOSE_ADC2, + GER_PURPOSE_MULTICHNNEL, +}; + +/*! + * This structure is used to report touch screen value. + */ +struct t_touch_screen { + /* Touch Screen X position */ + unsigned int x_position; + /* Touch Screen X position1 */ + unsigned int x_position1; + /* Touch Screen X position2 */ + unsigned int x_position2; + /* Touch Screen X position3 */ + unsigned int x_position3; + /* Touch Screen Y position */ + unsigned int y_position; + /* Touch Screen Y position1 */ + unsigned int y_position1; + /* Touch Screen Y position2 */ + unsigned int y_position2; + /* Touch Screen Y position3 */ + unsigned int y_position3; + /* Touch Screen contact value */ + unsigned int contact_resistance; + /* Flag indicate the data usability */ + unsigned int valid_flag; +}; + +/*! + * This structure is used with IOCTL code \a IMX_ADC_CONVERT, + * \a IMX_ADC_CONVERT_8X and \a IMX_ADC_CONVERT_MULTICHANNEL. + */ + +struct t_adc_convert_param { + /* channel or channels to be sampled. */ + enum t_channel channel; + /* holds up to 16 sampling results */ + unsigned short result[16]; +}; + +/* EXPORTED FUNCTIONS */ + +#ifdef __KERNEL__ +/* Driver data */ +struct imx_adc_data { + u32 irq; + struct clk *adc_clk; +}; + +/*! + * This function initializes all ADC registers with default values. This + * function also registers the interrupt events. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_init(void); + +/*! + * This function disables the ADC, de-registers the interrupt events. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_deinit(void); + +/*! + * This function triggers a conversion and returns one sampling result of one + * channel. + * + * @param channel The channel to be sampled + * @param result The pointer to the conversion result. The memory + * should be allocated by the caller of this function. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ + +enum IMX_ADC_STATUS imx_adc_convert(enum t_channel channel, + unsigned short *result); + +/*! + * This function triggers a conversion and returns sampling results of each + * specified channel. + * + * @param channels This input parameter is bitmap to specify channels + * to be sampled. + * @param result The pointer to array to store sampling result. + * The order of the result in the array is from lowest + * channel number to highest channel number of the + * sampled channels. + * The memory should be allocated by the caller of this + * function. + * Note that the behavior of this function might differ + * from one platform to another regarding especially + * channels order. + * + * @return This function returns IMX_ADC_SUCCESS if successful. + */ + +enum IMX_ADC_STATUS imx_adc_convert_multichnnel(enum t_channel channels, + unsigned short *result); + +/*! + * This function retrieves the current touch screen operation mode. + * + * @param touch_sample Pointer to touch sample. + * @param wait_tsi if true, we wait until interrupt occurs + * @return This function returns IMX_ADC_SUCCESS if successful. + */ +enum IMX_ADC_STATUS imx_adc_get_touch_sample(struct t_touch_screen *ts_value, + int wait_tsi); + +/*! + * This function read the touch screen value. + * + * @param touch_sample return value of touch screen + * @param wait_tsi if true, we need wait until interrupt occurs + * @return This function returns 0. + */ +enum IMX_ADC_STATUS imx_adc_read_ts(struct t_touch_screen *touch_sample, + int wait_tsi); + +int is_imx_adc_ready(void); + +#endif /* _KERNEL */ +#endif /* __ASM_ARCH_IMX_ADC_H__ */ diff --git a/include/linux/ipu.h b/include/linux/ipu.h new file mode 100644 index 000000000000..2e2b3ceff389 --- /dev/null +++ b/include/linux/ipu.h @@ -0,0 +1,1292 @@ +/* + * Copyright 2005-2011 Freescale Semiconductor, Inc. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup IPU MXC Image Processing Unit (IPU) Driver + */ +/*! + * @file arch-mxc/ipu.h + * + * @brief This file contains the IPU driver API declarations. + * + * @ingroup IPU + */ + +#ifndef __ASM_ARCH_IPU_H__ +#define __ASM_ARCH_IPU_H__ + +#include +#include +#ifdef __KERNEL__ +#include +#else +#ifndef __cplusplus +typedef unsigned char bool; +#endif +#define irqreturn_t int +#define dma_addr_t int +#define u32 unsigned int +#define __u32 u32 +#endif + +/*! + * Enumeration of IPU rotation modes + */ +typedef enum { + /* Note the enum values correspond to BAM value */ + IPU_ROTATE_NONE = 0, + IPU_ROTATE_VERT_FLIP = 1, + IPU_ROTATE_HORIZ_FLIP = 2, + IPU_ROTATE_180 = 3, + IPU_ROTATE_90_RIGHT = 4, + IPU_ROTATE_90_RIGHT_VFLIP = 5, + IPU_ROTATE_90_RIGHT_HFLIP = 6, + IPU_ROTATE_90_LEFT = 7, +} ipu_rotate_mode_t; + +/*! + * Enumeration of Post Filter modes + */ +typedef enum { + PF_DISABLE_ALL = 0, + PF_MPEG4_DEBLOCK = 1, + PF_MPEG4_DERING = 2, + PF_MPEG4_DEBLOCK_DERING = 3, + PF_H264_DEBLOCK = 4, +} pf_operation_t; + +/*! + * Enumeration of Synchronous (Memory-less) panel types + */ +typedef enum { + IPU_PANEL_SHARP_TFT, + IPU_PANEL_TFT, +} ipu_panel_t; + +/*! + * Enumeration of VDI MOTION select + */ +typedef enum { + MED_MOTION = 0, + LOW_MOTION = 1, + HIGH_MOTION = 2, +} ipu_motion_sel; + +/* IPU Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/*! + * @name IPU Pixel Formats + * + * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are + * the same used by V4L2 API. + */ + +/*! @{ */ +/*! @name Generic or Raw Data Formats */ +/*! @{ */ +#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') /*!< IPU Generic Data */ +#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') /*!< IPU Generic Data */ +/*! @} */ +/*! @name RGB Formats */ +/*! @{ */ +#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */ +#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */ +#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */ +#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */ +#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */ +#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */ +#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */ +#define IPU_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */ +#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */ +#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */ +#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */ +/*! @} */ +/*! @name YUV Interleaved Formats */ +/*! @{ */ +#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */ +#define IPU_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */ +#define IPU_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */ +#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */ +#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */ +/* two planes -- one Y, one Cb + Cr interleaved */ +#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +/*! @} */ +/*! @name YUV Planar Formats */ +/*! @{ */ +#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */ +#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */ +#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */ +#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */ +#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */ +#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */ +#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */ +/*! @} */ + +/* IPU Driver channels definitions. */ +/* Note these are different from IDMA channels */ +#ifdef CONFIG_MXC_IPU_V1 +#define _MAKE_CHAN(num, in, out, sec) ((num << 24) | (sec << 16) | (out << 8) | in) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_SEC_DMA(ch) ((uint32_t) (ch >> 16) & 0xFF) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch >> 8) & 0xFF) +#define IPU_CHAN_IN_DMA(ch) ((uint32_t) (ch & 0xFF)) + +#else +#define IPU_MAX_CH 32 +#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ + ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) +#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_ALT(ch) (ch & 0x02000000) +#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) +#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) +#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) +#define NO_DMA 0x3F +#define ALT 1 +#endif +/*! + * Enumeration of IPU logical channels. An IPU logical channel is defined as a + * combination of an input (memory to IPU), output (IPU to memory), and/or + * secondary input IDMA channels and in some cases an Image Converter task. + * Some channels consist of only an input or output. + */ +typedef enum { + CHAN_NONE = -1, +#ifdef CONFIG_MXC_IPU_V1 + CSI_MEM = _MAKE_CHAN(1, 0xFF, 7, 0xFF), /*!< CSI raw sensor data to memory */ + + CSI_PRP_ENC_MEM = _MAKE_CHAN(2, 0xFF, 0, 0xFF), /*!< CSI to IC Encoder PreProcessing to Memory */ + MEM_PRP_ENC_MEM = _MAKE_CHAN(3, 6, 0, 0xFF), /*!< Memory to IC Encoder PreProcessing to Memory */ + MEM_ROT_ENC_MEM = _MAKE_CHAN(4, 10, 8, 0xFF), /*!< Memory to IC Encoder Rotation to Memory */ + + CSI_PRP_VF_MEM = _MAKE_CHAN(5, 0xFF, 1, 0xFF), /*!< CSI to IC Viewfinder PreProcessing to Memory */ + CSI_PRP_VF_ADC = _MAKE_CHAN(6, 0xFF, 1, 0xFF), /*!< CSI to IC Viewfinder PreProcessing to ADC */ + MEM_PRP_VF_MEM = _MAKE_CHAN(7, 6, 1, 3), /*!< Memory to IC Viewfinder PreProcessing to Memory */ + MEM_PRP_VF_ADC = _MAKE_CHAN(8, 6, 1, 3), /*!< Memory to IC Viewfinder PreProcessing to ADC */ + MEM_ROT_VF_MEM = _MAKE_CHAN(9, 11, 9, 0xFF), /*!< Memory to IC Viewfinder Rotation to Memory */ + + MEM_PP_MEM = _MAKE_CHAN(10, 5, 2, 4), /*!< Memory to IC PostProcessing to Memory */ + MEM_ROT_PP_MEM = _MAKE_CHAN(11, 13, 12, 0xFF), /*!< Memory to IC PostProcessing Rotation to Memory */ + MEM_PP_ADC = _MAKE_CHAN(12, 5, 2, 4), /*!< Memory to IC PostProcessing to ADC */ + + MEM_SDC_BG = _MAKE_CHAN(14, 14, 0xFF, 0xFF), /*!< Memory to SDC Background plane */ + MEM_SDC_FG = _MAKE_CHAN(15, 15, 0xFF, 0xFF), /*!< Memory to SDC Foreground plane */ + MEM_SDC_MASK = _MAKE_CHAN(16, 16, 0xFF, 0xFF), /*!< Memory to SDC Mask */ + + MEM_BG_SYNC = MEM_SDC_BG, + MEM_FG_SYNC = MEM_SDC_FG, + + ADC_SYS1 = _MAKE_CHAN(17, 18, 22, 20), /*!< Memory to ADC System Channel 1 */ + ADC_SYS2 = _MAKE_CHAN(18, 19, 23, 21), /*!< Memory to ADC System Channel 2 */ + + MEM_PF_Y_MEM = _MAKE_CHAN(19, 26, 29, 24), /*!< Y and PF Memory to Post-filter to Y Memory */ + MEM_PF_U_MEM = _MAKE_CHAN(20, 27, 30, 25), /*!< U and PF Memory to Post-filter to U Memory */ + MEM_PF_V_MEM = _MAKE_CHAN(21, 28, 31, 0xFF), /*!< V Memory to Post-filter to V Memory */ + + MEM_DC_SYNC = CHAN_NONE, + DIRECT_ASYNC0 = CHAN_NONE, + DIRECT_ASYNC1 = CHAN_NONE, + MEM_VDI_PRP_VF_MEM_P = CHAN_NONE, + MEM_VDI_PRP_VF_MEM = CHAN_NONE, + MEM_VDI_PRP_VF_MEM_N = CHAN_NONE, +#else + MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48), + MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49), + MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50), + + MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20), + MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21), + MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22), + + MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), + MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), + MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), + MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), + + MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), + MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), + MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), + MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), + + DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + + CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0), + CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1), + CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2), + CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3), + + CSI_MEM = CSI_MEM0, + + CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20), + CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21), + + MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21), + MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21), + MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21), + + MEM_PP_ADC = CHAN_NONE, + ADC_SYS2 = CHAN_NONE, +#endif + +} ipu_channel_t; + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */ + IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */ + IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */ + IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */ + IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, + IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, +} ipu_buffer_t; + +#define IPU_PANEL_SERIAL 1 +#define IPU_PANEL_PARALLEL 2 + +/*! + * Enumeration of DI ports for ADC. + */ +typedef enum { + DISP0, + DISP1, + DISP2, + DISP3 +} display_port_t; + +/*! + * Enumeration of ADC channel operation mode. + */ +typedef enum { + Disable, + WriteTemplateNonSeq, + ReadTemplateNonSeq, + WriteTemplateUnCon, + ReadTemplateUnCon, + WriteDataWithRS, + WriteDataWoRS, + WriteCmd +} mcu_mode_t; + +/*! + * Enumeration of ADC channel addressing mode. + */ +typedef enum { + FullWoBE, + FullWithBE, + XY +} display_addressing_t; + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + uint32_t csi; + uint32_t mipi_id; + bool mipi_en; + bool interlaced; + } csi_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t csi; + } csi_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + } mem_prp_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + } mem_rot_enc_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t csi; + } csi_prp_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } csi_prp_vf_adc; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + ipu_motion_sel motion_sel; + enum v4l2_field field_fmt; + } mem_prp_vf_mem; + struct { + uint32_t temp; + } mem_prp_vf_adc; + struct { + uint32_t temp; + } mem_rot_vf_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + uint32_t outh_resize_ratio; + uint32_t outv_resize_ratio; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + uint32_t in_g_pixel_fmt; + uint8_t alpha; + uint32_t key_color; + bool alpha_chan_en; + } mem_pp_mem; + struct { + uint32_t temp; + } mem_rot_mem; + struct { + uint32_t in_width; + uint32_t in_height; + uint32_t in_pixel_fmt; + uint32_t out_width; + uint32_t out_height; + uint32_t out_pixel_fmt; + bool graphics_combine_en; + bool global_alpha_en; + bool key_color_en; + display_port_t disp; + uint32_t out_left; + uint32_t out_top; + } mem_pp_adc; + struct { + pf_operation_t operation; + } mem_pf_mem; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + } mem_dc_sync; + struct { + uint32_t temp; + } mem_sdc_fg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_bg_sync; + struct { + uint32_t temp; + } mem_sdc_bg; + struct { + uint32_t di; + bool interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + bool alpha_chan_en; + } mem_dp_fg_sync; + struct { + uint32_t di; + } direct_async; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys1; + struct { + display_port_t disp; + mcu_mode_t ch_mode; + uint32_t out_left; + uint32_t out_top; + } adc_sys2; +} ipu_channel_params_t; + +/*! + * Enumeration of IPU interrupt sources. + */ +enum ipu_irq_line { +#ifdef CONFIG_MXC_IPU_V1 + IPU_IRQ_DC_FC_1 = -1, + + IPU_IRQ_PRP_ENC_OUT_EOF = 0, + IPU_IRQ_PRP_VF_OUT_EOF = 1, + IPU_IRQ_PP_OUT_EOF = 2, + IPU_IRQ_PRP_GRAPH_IN_EOF = 3, + IPU_IRQ_PP_GRAPH_IN_EOF = 4, + IPU_IRQ_PP_IN_EOF = 5, + IPU_IRQ_PRP_IN_EOF = 6, + IPU_IRQ_SENSOR_OUT_EOF = 7, + IPU_IRQ_CSI0_OUT_EOF = IPU_IRQ_SENSOR_OUT_EOF, + IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 8, + IPU_IRQ_PRP_VF_ROT_OUT_EOF = 9, + IPU_IRQ_PRP_ENC_ROT_IN_EOF = 10, + IPU_IRQ_PRP_VF_ROT_IN_EOF = 11, + IPU_IRQ_PP_ROT_OUT_EOF = 12, + IPU_IRQ_PP_ROT_IN_EOF = 13, + IPU_IRQ_BG_SYNC_EOF = 14, + IPU_IRQ_SDC_BG_EOF = IPU_IRQ_BG_SYNC_EOF, + IPU_IRQ_FG_SYNC_EOF = 15, + IPU_IRQ_SDC_FG_EOF = IPU_IRQ_FG_SYNC_EOF, + IPU_IRQ_SDC_MASK_EOF = 16, + IPU_IRQ_SDC_BG_PART_EOF = 17, + IPU_IRQ_ADC_SYS1_WR_EOF = 18, + IPU_IRQ_ADC_SYS2_WR_EOF = 19, + IPU_IRQ_ADC_SYS1_CMD_EOF = 20, + IPU_IRQ_ADC_SYS2_CMD_EOF = 21, + IPU_IRQ_ADC_SYS1_RD_EOF = 22, + IPU_IRQ_ADC_SYS2_RD_EOF = 23, + IPU_IRQ_PF_QP_IN_EOF = 24, + IPU_IRQ_PF_BSP_IN_EOF = 25, + IPU_IRQ_PF_Y_IN_EOF = 26, + IPU_IRQ_PF_U_IN_EOF = 27, + IPU_IRQ_PF_V_IN_EOF = 28, + IPU_IRQ_PF_Y_OUT_EOF = 29, + IPU_IRQ_PF_U_OUT_EOF = 30, + IPU_IRQ_PF_V_OUT_EOF = 31, + + IPU_IRQ_PRP_ENC_OUT_NF = 32, + IPU_IRQ_PRP_VF_OUT_NF = 33, + IPU_IRQ_PP_OUT_NF = 34, + IPU_IRQ_PRP_GRAPH_IN_NF = 35, + IPU_IRQ_PP_GRAPH_IN_NF = 36, + IPU_IRQ_PP_IN_NF = 37, + IPU_IRQ_PRP_IN_NF = 38, + IPU_IRQ_SENSOR_OUT_NF = 39, + IPU_IRQ_PRP_ENC_ROT_OUT_NF = 40, + IPU_IRQ_PRP_VF_ROT_OUT_NF = 41, + IPU_IRQ_PRP_ENC_ROT_IN_NF = 42, + IPU_IRQ_PRP_VF_ROT_IN_NF = 43, + IPU_IRQ_PP_ROT_OUT_NF = 44, + IPU_IRQ_PP_ROT_IN_NF = 45, + IPU_IRQ_SDC_FG_NF = 46, + IPU_IRQ_SDC_BG_NF = 47, + IPU_IRQ_SDC_MASK_NF = 48, + IPU_IRQ_SDC_BG_PART_NF = 49, + IPU_IRQ_ADC_SYS1_WR_NF = 50, + IPU_IRQ_ADC_SYS2_WR_NF = 51, + IPU_IRQ_ADC_SYS1_CMD_NF = 52, + IPU_IRQ_ADC_SYS2_CMD_NF = 53, + IPU_IRQ_ADC_SYS1_RD_NF = 54, + IPU_IRQ_ADC_SYS2_RD_NF = 55, + IPU_IRQ_PF_QP_IN_NF = 56, + IPU_IRQ_PF_BSP_IN_NF = 57, + IPU_IRQ_PF_Y_IN_NF = 58, + IPU_IRQ_PF_U_IN_NF = 59, + IPU_IRQ_PF_V_IN_NF = 60, + IPU_IRQ_PF_Y_OUT_NF = 61, + IPU_IRQ_PF_U_OUT_NF = 62, + IPU_IRQ_PF_V_OUT_NF = 63, + + IPU_IRQ_BREAKRQ = 64, + IPU_IRQ_SDC_BG_OUT_EOF = 65, + IPU_IRQ_BG_SF_END = IPU_IRQ_SDC_BG_OUT_EOF, + IPU_IRQ_SDC_FG_OUT_EOF = 66, + IPU_IRQ_SDC_MASK_OUT_EOF = 67, + IPU_IRQ_ADC_SERIAL_DATA_OUT = 68, + IPU_IRQ_SENSOR_NF = 69, + IPU_IRQ_SENSOR_EOF = 70, + IPU_IRQ_SDC_DISP3_VSYNC = 80, + IPU_IRQ_ADC_DISP0_VSYNC = 81, + IPU_IRQ_ADC_DISP12_VSYNC = 82, + IPU_IRQ_ADC_PRP_EOF = 83, + IPU_IRQ_ADC_PP_EOF = 84, + IPU_IRQ_ADC_SYS1_EOF = 85, + IPU_IRQ_ADC_SYS2_EOF = 86, + + IPU_IRQ_PRP_ENC_OUT_NFB4EOF_ERR = 96, + IPU_IRQ_PRP_VF_OUT_NFB4EOF_ERR = 97, + IPU_IRQ_PP_OUT_NFB4EOF_ERR = 98, + IPU_IRQ_PRP_GRAPH_IN_NFB4EOF_ERR = 99, + IPU_IRQ_PP_GRAPH_IN_NFB4EOF_ERR = 100, + IPU_IRQ_PP_IN_NFB4EOF_ERR = 101, + IPU_IRQ_PRP_IN_NFB4EOF_ERR = 102, + IPU_IRQ_SENSOR_OUT_NFB4EOF_ERR = 103, + IPU_IRQ_PRP_ENC_ROT_OUT_NFB4EOF_ERR = 104, + IPU_IRQ_PRP_VF_ROT_OUT_NFB4EOF_ERR = 105, + IPU_IRQ_PRP_ENC_ROT_IN_NFB4EOF_ERR = 106, + IPU_IRQ_PRP_VF_ROT_IN_NFB4EOF_ERR = 107, + IPU_IRQ_PP_ROT_OUT_NFB4EOF_ERR = 108, + IPU_IRQ_PP_ROT_IN_NFB4EOF_ERR = 109, + IPU_IRQ_SDC_FG_NFB4EOF_ERR = 110, + IPU_IRQ_SDC_BG_NFB4EOF_ERR = 111, + IPU_IRQ_SDC_MASK_NFB4EOF_ERR = 112, + IPU_IRQ_SDC_BG_PART_NFB4EOF_ERR = 113, + IPU_IRQ_ADC_SYS1_WR_NFB4EOF_ERR = 114, + IPU_IRQ_ADC_SYS2_WR_NFB4EOF_ERR = 115, + IPU_IRQ_ADC_SYS1_CMD_NFB4EOF_ERR = 116, + IPU_IRQ_ADC_SYS2_CMD_NFB4EOF_ERR = 117, + IPU_IRQ_ADC_SYS1_RD_NFB4EOF_ERR = 118, + IPU_IRQ_ADC_SYS2_RD_NFB4EOF_ERR = 119, + IPU_IRQ_PF_QP_IN_NFB4EOF_ERR = 120, + IPU_IRQ_PF_BSP_IN_NFB4EOF_ERR = 121, + IPU_IRQ_PF_Y_IN_NFB4EOF_ERR = 122, + IPU_IRQ_PF_U_IN_NFB4EOF_ERR = 123, + IPU_IRQ_PF_V_IN_NFB4EOF_ERR = 124, + IPU_IRQ_PF_Y_OUT_NFB4EOF_ERR = 125, + IPU_IRQ_PF_U_OUT_NFB4EOF_ERR = 126, + IPU_IRQ_PF_V_OUT_NFB4EOF_ERR = 127, + + IPU_IRQ_BAYER_BUFOVF_ERR = 128, + IPU_IRQ_ENC_BUFOVF_ERR = 129, + IPU_IRQ_VF_BUFOVF_ERR = 130, + IPU_IRQ_ADC_PP_TEAR_ERR = 131, + IPU_IRQ_ADC_SYS1_TEAR_ERR = 132, + IPU_IRQ_ADC_SYS2_TEAR_ERR = 133, + IPU_IRQ_SDC_BGD_ERR = 134, + IPU_IRQ_SDC_FGD_ERR = 135, + IPU_IRQ_SDC_MASKD_ERR = 136, + IPU_IRQ_BAYER_FRM_LOST_ERR = 137, + IPU_IRQ_ENC_FRM_LOST_ERR = 138, + IPU_IRQ_VF_FRM_LOST_ERR = 139, + IPU_IRQ_ADC_LOCK_ERR = 140, + IPU_IRQ_DI_LLA_LOCK_ERR = 141, + IPU_IRQ_AHB_M1_ERR = 142, + IPU_IRQ_AHB_M12_ERR = 143, +#else + IPU_IRQ_CSI0_OUT_EOF = 0, + IPU_IRQ_CSI1_OUT_EOF = 1, + IPU_IRQ_CSI2_OUT_EOF = 2, + IPU_IRQ_CSI3_OUT_EOF = 3, + IPU_IRQ_VDI_P_IN_EOF = 8, + IPU_IRQ_VDI_C_IN_EOF = 9, + IPU_IRQ_VDI_N_IN_EOF = 10, + IPU_IRQ_PP_IN_EOF = 11, + IPU_IRQ_PRP_IN_EOF = 12, + IPU_IRQ_PRP_GRAPH_IN_EOF = 14, + IPU_IRQ_PP_GRAPH_IN_EOF = 15, + IPU_IRQ_PRP_ALPHA_IN_EOF = 17, + IPU_IRQ_PP_ALPHA_IN_EOF = 18, + IPU_IRQ_PRP_ENC_OUT_EOF = 20, + IPU_IRQ_PRP_VF_OUT_EOF = 21, + IPU_IRQ_PP_OUT_EOF = 22, + IPU_IRQ_BG_SYNC_EOF = 23, + IPU_IRQ_BG_ASYNC_EOF = 24, + IPU_IRQ_FG_SYNC_EOF = 27, + IPU_IRQ_DC_SYNC_EOF = 28, + IPU_IRQ_FG_ASYNC_EOF = 29, + IPU_IRQ_FG_ALPHA_SYNC_EOF = 31, + + IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33, + IPU_IRQ_DC_READ_EOF = 40, + IPU_IRQ_DC_ASYNC_EOF = 41, + IPU_IRQ_DC_CMD1_EOF = 42, + IPU_IRQ_DC_CMD2_EOF = 43, + IPU_IRQ_DC_MASK_EOF = 44, + IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45, + IPU_IRQ_PRP_VF_ROT_IN_EOF = 46, + IPU_IRQ_PP_ROT_IN_EOF = 47, + IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48, + IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49, + IPU_IRQ_PP_ROT_OUT_EOF = 50, + IPU_IRQ_BG_ALPHA_SYNC_EOF = 51, + IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52, + + IPU_IRQ_DP_SF_START = 448 + 2, + IPU_IRQ_DP_SF_END = 448 + 3, + IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END, + IPU_IRQ_DC_FC_0 = 448 + 8, + IPU_IRQ_DC_FC_1 = 448 + 9, + IPU_IRQ_DC_FC_2 = 448 + 10, + IPU_IRQ_DC_FC_3 = 448 + 11, + IPU_IRQ_DC_FC_4 = 448 + 12, + IPU_IRQ_DC_FC_6 = 448 + 13, + IPU_IRQ_VSYNC_PRE_0 = 448 + 14, + IPU_IRQ_VSYNC_PRE_1 = 448 + 15, +#endif + + IPU_IRQ_COUNT +}; + +/*! + * Bitfield of Display Interface signal polarities. + */ +typedef struct { + unsigned datamask_en:1; + unsigned int_clk:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; +} ipu_di_signal_cfg_t; + +/*! + * Bitfield of CSI signal polarities and modes. + */ + +typedef struct { + unsigned data_width:4; + unsigned clk_mode:3; + unsigned ext_vsync:1; + unsigned Vsync_pol:1; + unsigned Hsync_pol:1; + unsigned pixclk_pol:1; + unsigned data_pol:1; + unsigned sens_clksrc:1; + unsigned pack_tight:1; + unsigned force_eof:1; + unsigned data_en_pol:1; + unsigned data_fmt; + unsigned csi; + unsigned mclk; +} ipu_csi_signal_cfg_t; + +/*! + * Enumeration of CSI data bus widths. + */ +enum { + IPU_CSI_DATA_WIDTH_4, + IPU_CSI_DATA_WIDTH_8, + IPU_CSI_DATA_WIDTH_10, + IPU_CSI_DATA_WIDTH_16, +}; + +/*! + * Enumeration of CSI clock modes. + */ +enum { + IPU_CSI_CLK_MODE_GATED_CLK, + IPU_CSI_CLK_MODE_NONGATED_CLK, + IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE, + IPU_CSI_CLK_MODE_CCIR656_INTERLACED, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR, + IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR, + IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR, +}; + +enum { + IPU_CSI_MIPI_DI0, + IPU_CSI_MIPI_DI1, + IPU_CSI_MIPI_DI2, + IPU_CSI_MIPI_DI3, +}; + +typedef enum { + RGB, + YCbCr, + YUV +} ipu_color_space_t; + +/*! + * Enumeration of ADC vertical sync mode. + */ +typedef enum { + VsyncNone, + VsyncInternal, + VsyncCSI, + VsyncExternal +} vsync_t; + +typedef enum { + DAT, + CMD +} cmddata_t; + +/*! + * Enumeration of ADC display update mode. + */ +typedef enum { + IPU_ADC_REFRESH_NONE, + IPU_ADC_AUTO_REFRESH, + IPU_ADC_AUTO_REFRESH_SNOOP, + IPU_ADC_SNOOPING, +} ipu_adc_update_mode_t; + +/*! + * Enumeration of ADC display interface types (serial or parallel). + */ +enum { + IPU_ADC_IFC_MODE_SYS80_TYPE1, + IPU_ADC_IFC_MODE_SYS80_TYPE2, + IPU_ADC_IFC_MODE_SYS68K_TYPE1, + IPU_ADC_IFC_MODE_SYS68K_TYPE2, + IPU_ADC_IFC_MODE_3WIRE_SERIAL, + IPU_ADC_IFC_MODE_4WIRE_SERIAL, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK, + IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS, +}; + +enum { + IPU_ADC_IFC_WIDTH_8, + IPU_ADC_IFC_WIDTH_16, +}; + +/*! + * Enumeration of ADC display interface burst mode. + */ +enum { + IPU_ADC_BURST_WCS, + IPU_ADC_BURST_WBLCK, + IPU_ADC_BURST_NONE, + IPU_ADC_BURST_SERIAL, +}; + +/*! + * Enumeration of ADC display interface RW signal timing modes. + */ +enum { + IPU_ADC_SER_NO_RW, + IPU_ADC_SER_RW_BEFORE_RS, + IPU_ADC_SER_RW_AFTER_RS, +}; + +/*! + * Bitfield of ADC signal polarities and modes. + */ +typedef struct { + unsigned data_pol:1; + unsigned clk_pol:1; + unsigned cs_pol:1; + unsigned rs_pol:1; + unsigned addr_pol:1; + unsigned read_pol:1; + unsigned write_pol:1; + unsigned Vsync_pol:1; + unsigned burst_pol:1; + unsigned burst_mode:2; + unsigned ifc_mode:3; + unsigned ifc_width:5; + unsigned ser_preamble_len:4; + unsigned ser_preamble:8; + unsigned ser_rw_mode:2; +} ipu_adc_sig_cfg_t; + +/*! + * Enumeration of ADC template commands. + */ +enum { + RD_DATA, + RD_ACK, + RD_WAIT, + WR_XADDR, + WR_YADDR, + WR_ADDR, + WR_CMND, + WR_DATA, +}; + +/*! + * Enumeration of ADC template command flow control. + */ +enum { + SINGLE_STEP, + PAUSE, + STOP, +}; + + +/*Define template constants*/ +#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */ +#define TEMPLATE_BUF_SIZE 0x20 /*size of template */ + +/*! + * Define to create ADC template command entry. + */ +#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \ + ((oc) << 24) | (dat)) + +typedef struct { + u32 reg; + u32 value; +} ipu_lpmc_reg_t; + +#define IPU_LPMC_REG_READ 0x80000000L + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +/* Common IPU API */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params); +void ipu_uninit_channel(ipu_channel_t channel); + +static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot) +{ +#ifdef CONFIG_MXC_IPU_V3D + return (rot < IPU_ROTATE_HORIZ_FLIP); +#else + return (rot < IPU_ROTATE_90_RIGHT); +#endif +} + +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + ipu_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u_offset, uint32_t v_offset); + +int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr); + +int32_t ipu_update_channel_offset(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + uint32_t u, uint32_t v, + uint32_t vertical_offset, uint32_t horizontal_offset); + +int32_t ipu_select_buffer(ipu_channel_t channel, + ipu_buffer_t type, uint32_t bufNum); +int32_t ipu_select_multi_vdi_buffer(uint32_t bufNum); + +int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch); +int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch); + +int32_t ipu_is_channel_busy(ipu_channel_t channel); +int32_t ipu_check_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +uint32_t ipu_get_cur_buffer_idx(ipu_channel_t channel, ipu_buffer_t type); +int32_t ipu_enable_channel(ipu_channel_t channel); +int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop); +int32_t ipu_swap_channel(ipu_channel_t from_ch, ipu_channel_t to_ch); + +int32_t ipu_enable_csi(uint32_t csi); +int32_t ipu_disable_csi(uint32_t csi); + +int ipu_lowpwr_display_enable(void); +int ipu_lowpwr_display_disable(void); + +void ipu_enable_irq(uint32_t irq); +void ipu_disable_irq(uint32_t irq); +void ipu_clear_irq(uint32_t irq); +int ipu_request_irq(uint32_t irq, + irqreturn_t(*handler) (int, void *), + uint32_t irq_flags, const char *devname, void *dev_id); +void ipu_free_irq(uint32_t irq, void *dev_id); +bool ipu_get_irq_status(uint32_t irq); +void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]); + +/* SDC API */ +int32_t ipu_sdc_init_panel(ipu_panel_t panel, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t hStartWidth, uint16_t hSyncWidth, + uint16_t hEndWidth, uint16_t vStartWidth, + uint16_t vSyncWidth, uint16_t vEndWidth, + ipu_di_signal_cfg_t sig); + +int32_t ipu_sdc_set_global_alpha(bool enable, uint8_t alpha); +int32_t ipu_sdc_set_color_key(ipu_channel_t channel, bool enable, + uint32_t colorKey); +int32_t ipu_sdc_set_brightness(uint8_t value); + +int32_t ipu_init_sync_panel(int disp, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); + +int32_t ipu_disp_set_window_pos(ipu_channel_t channel, int16_t x_pos, + int16_t y_pos); +int32_t ipu_disp_get_window_pos(ipu_channel_t channel, int16_t *x_pos, + int16_t *y_pos); +int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, bool enable, + uint8_t alpha); +int32_t ipu_disp_set_color_key(ipu_channel_t channel, bool enable, + uint32_t colorKey); +int32_t ipu_disp_set_gamma_correction(ipu_channel_t channel, bool enable, + int constk[], int slopek[]); + +int ipu_init_async_panel(int disp, int type, uint32_t cycle_time, + uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig); +void ipu_disp_direct_write(ipu_channel_t channel, u32 value, u32 offset); +void ipu_reset_disp_panel(void); + +/* ADC API */ +int32_t ipu_adc_write_template(display_port_t disp, uint32_t *pCmd, + bool write); + +int32_t ipu_adc_set_update_mode(ipu_channel_t channel, + ipu_adc_update_mode_t mode, + uint32_t refresh_rate, unsigned long addr, + uint32_t *size); + +int32_t ipu_adc_get_snooping_status(uint32_t *statl, uint32_t *stath); + +int32_t ipu_adc_write_cmd(display_port_t disp, cmddata_t type, + uint32_t cmd, const uint32_t *params, + uint16_t numParams); + +int32_t ipu_adc_init_panel(display_port_t disp, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint32_t stride, + ipu_adc_sig_cfg_t sig, + display_addressing_t addr, + uint32_t vsync_width, vsync_t mode); + +int32_t ipu_adc_init_ifc_timing(display_port_t disp, bool read, + uint32_t cycle_time, + uint32_t up_time, + uint32_t down_time, + uint32_t read_latch_time, uint32_t pixel_clk); + +/* CMOS Sensor Interface API */ +int32_t ipu_csi_init_interface(uint16_t width, uint16_t height, + uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig); + +int32_t ipu_csi_get_sensor_protocol(uint32_t csi); + +int32_t ipu_csi_enable_mclk(int src, bool flag, bool wait); + +static inline int32_t ipu_csi_enable_mclk_if(int src, uint32_t csi, + bool flag, bool wait) +{ +#ifdef CONFIG_MXC_IPU_V1 + return ipu_csi_enable_mclk(src, flag, wait); +#else + return ipu_csi_enable_mclk(csi, flag, wait); +#endif +} + +int ipu_csi_read_mclk_flag(void); + +void ipu_csi_flash_strobe(bool flag); + +void ipu_csi_get_window_size(uint32_t *width, uint32_t *height, uint32_t csi); + +void ipu_csi_set_window_size(uint32_t width, uint32_t height, uint32_t csi); + +void ipu_csi_set_window_pos(uint32_t left, uint32_t top, uint32_t csi); + +/* Post Filter functions */ +int32_t ipu_pf_set_pause_row(uint32_t pause_row); + +uint32_t bytes_per_pixel(uint32_t fmt); + +/* New added for IPU-lib functionality*/ +int ipu_open(void); +int ipu_register_generic_isr(int irq, void *dev); +void ipu_close(void); + +/* two stripe calculations */ +struct stripe_param{ + unsigned int input_width; /* width of the input stripe */ + unsigned int output_width; /* width of the output stripe */ + unsigned int input_column; /* the first column on the input stripe */ + unsigned int output_column; /* the first column on the output stripe */ + unsigned int idr; + /* inverse downisizing ratio parameter; expressed as a power of 2 */ + unsigned int irr; + /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */ +}; + +typedef struct _ipu_stripe_parm { + unsigned int input_width; + unsigned int output_width; + unsigned int maximal_stripe_width; + unsigned long long cirr; + unsigned int equal_stripes; + u32 input_pixelformat; + u32 output_pixelformat; + struct stripe_param left; + struct stripe_param right; +} ipu_stripe_parm; + +typedef struct _ipu_channel_parm { + ipu_channel_t channel; + ipu_channel_params_t params; + bool flag; +} ipu_channel_parm; + +typedef struct _ipu_channel_buf_parm { + ipu_channel_t channel; + ipu_buffer_t type; + uint32_t pixel_fmt; + uint16_t width; + uint16_t height; + uint16_t stride; + ipu_rotate_mode_t rot_mode; + dma_addr_t phyaddr_0; + dma_addr_t phyaddr_1; + uint32_t u_offset; + uint32_t v_offset; + uint32_t bufNum; +} ipu_channel_buf_parm; + +typedef struct _ipu_buf_offset_parm { + ipu_channel_t channel; + ipu_buffer_t type; + uint32_t pixel_fmt; + uint16_t width; + uint16_t height; + uint16_t stride; + uint32_t u_offset; + uint32_t v_offset; + uint32_t vertical_offset; + uint32_t horizontal_offset; +} ipu_buf_offset_parm; + +typedef struct _ipu_channel_link { + ipu_channel_t src_ch; + ipu_channel_t dest_ch; +} ipu_channel_link; + +typedef struct _ipu_channel_info { + ipu_channel_t channel; + bool stop; +} ipu_channel_info; + +typedef struct ipu_irq_info { + uint32_t irq; + irqreturn_t(*handler) (int, void *); + uint32_t irq_flags; + char *devname; + void *dev_id; +} ipu_irq_info; + +typedef struct _ipu_sdc_panel_info { + ipu_panel_t panel; + uint32_t pixel_clk; + uint16_t width; + uint16_t height; + uint32_t pixel_fmt; + uint16_t hStartWidth; + uint16_t hSyncWidth; + uint16_t hEndWidth; + uint16_t vStartWidth; + uint16_t vSyncWidth; + uint16_t vEndWidth; + ipu_di_signal_cfg_t signal; +} ipu_sdc_panel_info; + +typedef struct _ipu_sdc_window_pos { + ipu_channel_t channel; + int16_t x_pos; + int16_t y_pos; +} ipu_sdc_window_pos; + +typedef struct _ipu_sdc_global_alpha { + bool enable; + uint8_t alpha; +} ipu_sdc_global_alpha; + +typedef struct _ipu_sdc_color_key { + ipu_channel_t channel; + bool enable; + uint32_t colorKey; +} ipu_sdc_color_key; + +typedef struct _ipu_adc_template { + display_port_t disp; + uint32_t *pCmd; + bool write; +} ipu_adc_template; + +typedef struct _ipu_adc_update { + ipu_channel_t channel; + ipu_adc_update_mode_t mode; + uint32_t refresh_rate; + unsigned long addr; + uint32_t *size; +} ipu_adc_update; + +typedef struct _ipu_adc_snoop { + uint32_t *statl; + uint32_t *stath; +} ipu_adc_snoop; + +typedef struct _ipu_adc_cmd { + display_port_t disp; + cmddata_t type; + uint32_t cmd; + uint32_t *params; + uint16_t numParams; +} ipu_adc_cmd; + +typedef struct _ipu_adc_panel { + display_port_t disp; + uint16_t width; + uint16_t height; + uint32_t pixel_fmt; + uint32_t stride; + ipu_adc_sig_cfg_t signal; + display_addressing_t addr; + uint32_t vsync_width; + vsync_t mode; +} ipu_adc_panel; + +typedef struct _ipu_adc_ifc_timing { + display_port_t disp; + bool read; + uint32_t cycle_time; + uint32_t up_time; + uint32_t down_time; + uint32_t read_latch_time; + uint32_t pixel_clk; +} ipu_adc_ifc_timing; + +typedef struct _ipu_csi_interface { + uint16_t width; + uint16_t height; + uint16_t pixel_fmt; + ipu_csi_signal_cfg_t signal; +} ipu_csi_interface; + +typedef struct _ipu_csi_mclk { + int src; + bool flag; + bool wait; +} ipu_csi_mclk; + +typedef struct _ipu_csi_window { + uint32_t left; + uint32_t top; +} ipu_csi_window; + +typedef struct _ipu_csi_window_size { + uint32_t width; + uint32_t height; +} ipu_csi_window_size; + +typedef struct _ipu_event_info { + int irq; + void *dev; +} ipu_event_info; + +typedef struct _ipu_mem_info { + dma_addr_t paddr; + void *vaddr; + int size; +} ipu_mem_info; + +typedef struct _ipu_csc_update { + ipu_channel_t channel; + int **param; +} ipu_csc_update; + +/* IOCTL commands */ + +#define IPU_INIT_CHANNEL _IOW('I', 0x1, ipu_channel_parm) +#define IPU_UNINIT_CHANNEL _IOW('I', 0x2, ipu_channel_t) +#define IPU_INIT_CHANNEL_BUFFER _IOW('I', 0x3, ipu_channel_buf_parm) +#define IPU_UPDATE_CHANNEL_BUFFER _IOW('I', 0x4, ipu_channel_buf_parm) +#define IPU_SELECT_CHANNEL_BUFFER _IOW('I', 0x5, ipu_channel_buf_parm) +#define IPU_LINK_CHANNELS _IOW('I', 0x6, ipu_channel_link) +#define IPU_UNLINK_CHANNELS _IOW('I', 0x7, ipu_channel_link) +#define IPU_ENABLE_CHANNEL _IOW('I', 0x8, ipu_channel_t) +#define IPU_DISABLE_CHANNEL _IOW('I', 0x9, ipu_channel_info) +#define IPU_ENABLE_IRQ _IOW('I', 0xA, int) +#define IPU_DISABLE_IRQ _IOW('I', 0xB, int) +#define IPU_CLEAR_IRQ _IOW('I', 0xC, int) +#define IPU_FREE_IRQ _IOW('I', 0xD, ipu_irq_info) +#define IPU_REQUEST_IRQ_STATUS _IOW('I', 0xE, int) +#define IPU_SDC_INIT_PANEL _IOW('I', 0xF, ipu_sdc_panel_info) +#define IPU_SDC_SET_WIN_POS _IOW('I', 0x10, ipu_sdc_window_pos) +#define IPU_SDC_SET_GLOBAL_ALPHA _IOW('I', 0x11, ipu_sdc_global_alpha) +#define IPU_SDC_SET_COLOR_KEY _IOW('I', 0x12, ipu_sdc_color_key) +#define IPU_SDC_SET_BRIGHTNESS _IOW('I', 0x13, int) +#define IPU_ADC_WRITE_TEMPLATE _IOW('I', 0x14, ipu_adc_template) +#define IPU_ADC_UPDATE _IOW('I', 0x15, ipu_adc_update) +#define IPU_ADC_SNOOP _IOW('I', 0x16, ipu_adc_snoop) +#define IPU_ADC_CMD _IOW('I', 0x17, ipu_adc_cmd) +#define IPU_ADC_INIT_PANEL _IOW('I', 0x18, ipu_adc_panel) +#define IPU_ADC_IFC_TIMING _IOW('I', 0x19, ipu_adc_ifc_timing) +#define IPU_CSI_INIT_INTERFACE _IOW('I', 0x1A, ipu_csi_interface) +#define IPU_CSI_ENABLE_MCLK _IOW('I', 0x1B, ipu_csi_mclk) +#define IPU_CSI_READ_MCLK_FLAG _IOR('I', 0x1C, ipu_csi_mclk) +#define IPU_CSI_FLASH_STROBE _IOW('I', 0x1D, ipu_csi_mclk) +#define IPU_CSI_GET_WIN_SIZE _IOR('I', 0x1E, ipu_csi_window_size) +#define IPU_CSI_SET_WIN_SIZE _IOW('I', 0x1F, ipu_csi_window_size) +#define IPU_CSI_SET_WINDOW _IOW('I', 0x20, ipu_csi_window) +#define IPU_PF_SET_PAUSE_ROW _IOW('I', 0x21, uint32_t) +#define IPU_REGISTER_GENERIC_ISR _IOW('I', 0x22, ipu_event_info) +#define IPU_GET_EVENT _IOWR('I', 0x23, ipu_event_info) +#define IPU_ALOC_MEM _IOWR('I', 0x24, ipu_mem_info) +#define IPU_FREE_MEM _IOW('I', 0x25, ipu_mem_info) +#define IPU_IS_CHAN_BUSY _IOW('I', 0x26, ipu_channel_t) +#define IPU_CALC_STRIPES_SIZE _IOWR('I', 0x27, ipu_stripe_parm) +#define IPU_UPDATE_BUF_OFFSET _IOW('I', 0x28, ipu_buf_offset_parm) +#define IPU_CSC_UPDATE _IOW('I', 0x29, ipu_csc_update) +#define IPU_SELECT_MULTI_VDI_BUFFER _IOW('I', 0x2A, uint32_t) + +int ipu_calc_stripes_sizes(const unsigned int input_frame_width, + unsigned int output_frame_width, + const unsigned int maximal_stripe_width, + const unsigned long long cirr, + const unsigned int equal_stripes, + u32 input_pixelformat, + u32 output_pixelformat, + struct stripe_param *left, + struct stripe_param *right); +#endif diff --git a/include/linux/iram_alloc.h b/include/linux/iram_alloc.h new file mode 100644 index 000000000000..12881aaa3d21 --- /dev/null +++ b/include/linux/iram_alloc.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifdef CONFIG_IRAM_ALLOC +int __init iram_init(unsigned long base, unsigned long size); +void *iram_alloc(unsigned int size, unsigned long *dma_addr); +void iram_free(unsigned long dma_addr, unsigned int size); +#else +static inline int __init iram_init(unsigned long base, unsigned long size) +{ + return -ENOMEM; +} +static inline void *iram_alloc(unsigned int size, unsigned long *dma_addr) +{ + return NULL; +} +static inline void iram_free(unsigned long base, unsigned long size) {} +#endif + diff --git a/include/linux/ldb.h b/include/linux/ldb.h new file mode 100644 index 000000000000..6540694b7498 --- /dev/null +++ b/include/linux/ldb.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*! + * @file include/linux/ldb.h + * + * @brief This file contains the LDB driver API declarations. + * + * @ingroup LDB + */ + +#ifndef __MXC_LDB_H__ +#define __MXC_LDB_H__ + +#include + +typedef enum { + LDB_INT_REF = 0, + LDB_EXT_REF = 1, +} ldb_bgref_t; + +typedef enum { + LDB_VS_ACT_H = 0, + LDB_VS_ACT_L = 1, +} ldb_vsync_t; + +typedef enum { + LDB_BIT_MAP_SPWG = 0, + LDB_BIT_MAP_JEIDA = 1, +} ldb_bitmap_t; + +typedef enum { + LDB_CHAN_MODE_SIN = 0, + LDB_CHAN_MODE_SEP = 1, + LDB_CHAN_MODE_DUL = 2, + LDB_CHAN_MODE_SPL = 3, +} ldb_channel_mode_t; + +typedef struct _ldb_bgref_parm { + ldb_bgref_t bgref_mode; +} ldb_bgref_parm; + +typedef struct _ldb_vsync_parm { + int di; + ldb_vsync_t vsync_mode; +} ldb_vsync_parm; + +typedef struct _ldb_bitmap_parm { + int channel; + ldb_bitmap_t bitmap_mode; +} ldb_bitmap_parm; + +typedef struct _ldb_data_width_parm { + int channel; + int data_width; +} ldb_data_width_parm; + +typedef struct _ldb_chan_mode_parm { + int di; + ldb_channel_mode_t channel_mode; +} ldb_chan_mode_parm; + +/* IOCTL commands */ +#define LDB_BGREF_RMODE _IOW('L', 0x1, ldb_bgref_parm) +#define LDB_VSYNC_POL _IOW('L', 0x2, ldb_vsync_parm) +#define LDB_BIT_MAP _IOW('L', 0x3, ldb_bitmap_parm) +#define LDB_DATA_WIDTH _IOW('L', 0x4, ldb_data_width_parm) +#define LDB_CHAN_MODE _IOW('L', 0x5, ldb_chan_mode_parm) +#define LDB_ENABLE _IOW('L', 0x6, int) +#define LDB_DISABLE _IOW('L', 0x7, int) +#endif diff --git a/include/linux/major.h b/include/linux/major.h index 6a8ca98c9a96..052b05353110 100644 --- a/include/linux/major.h +++ b/include/linux/major.h @@ -171,6 +171,8 @@ #define VIOTAPE_MAJOR 230 +#define LBA_MAJOR 240 + #define BLOCK_EXT_MAJOR 259 #define SCSI_OSD_MAJOR 260 /* open-osd's OSD scsi device */ diff --git a/include/linux/mfd/da9052/adc.h b/include/linux/mfd/da9052/adc.h new file mode 100644 index 000000000000..49c7d181d150 --- /dev/null +++ b/include/linux/mfd/da9052/adc.h @@ -0,0 +1,66 @@ +/* + * da9052 ADC module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_ADC_H +#define __LINUX_MFD_DA9052_ADC_H + +#include "gpio.h" + +#define DA9052_ADC_DEVICE_NAME "da9052_adc" + +/* Channel Definations */ +#define DA9052_ADC_VDDOUT 0 +#define DA9052_ADC_ICH 1 +#define DA9052_ADC_TBAT 2 +#define DA9052_ADC_VBAT 3 +#define DA9052_ADC_ADCIN4 4 +#define DA9052_ADC_ADCIN5 5 +#define DA9052_ADC_ADCIN6 6 +#define DA9052_ADC_TSI 7 +#define DA9052_ADC_TJUNC 8 +#define DA9052_ADC_VBBAT 9 + +#if (DA9052_GPIO_PIN_0 == DA9052_GPIO_CONFIG_ADC) +#define DA9052_ADC_CONF_ADC4 1 +#else +#define DA9052_ADC_CONF_ADC4 0 +#endif +#if (DA9052_GPIO_PIN_1 == DA9052_GPIO_CONFIG_ADC) +#define DA9052_ADC_CONF_ADC5 1 +#else +#define DA9052_ADC_CONF_ADC5 0 +#endif +#if (DA9052_GPIO_PIN_2 == DA9052_GPIO_CONFIG_ADC) +#define DA9052_ADC_CONF_ADC6 1 +#else +#define DA9052_ADC_CONF_ADC6 0 +#endif + +/* Maximum retry count to check manual conversion over */ +#define DA9052_ADC_MAX_MANCONV_RETRY_COUNT 8 + +struct da9052_adc_priv { + struct da9052 *da9052; + struct device *hwmon_dev; + struct mutex manconv_lock; +}; + +#endif /* __LINUX_MFD_DA9052_ADC_H */ diff --git a/include/linux/mfd/da9052/bat.h b/include/linux/mfd/da9052/bat.h new file mode 100644 index 000000000000..63797aad1031 --- /dev/null +++ b/include/linux/mfd/da9052/bat.h @@ -0,0 +1,341 @@ +/* + * da9052 BAT module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_BAT_H +#define __LINUX_MFD_DA9052_BAT_H + +#include + +/* STATIC CONFIGURATION */ +#define BAT_MANUFACTURER "Samsung" +#define BAT_TYPE POWER_SUPPLY_TECHNOLOGY_LION +#define DA9052_LOOK_UP_TABLE_SIZE 68 +#define DA9052_NO_OF_LOOKUP_TABLE 3 +#define CURRENT_MONITORING_WINDOW 10 +#define FILTER_SIZE 4 +#define DA9052_NUMBER_OF_STORE_CURENT_READING 4 +#define DA9052_ILLEGAL_BATTERY_DETECT 1 +#define DA9052_BAT_FILTER_HYS 0 + + +static const u16 temperature_lookup_ref + [DA9052_NO_OF_LOOKUP_TABLE] = {10, 25, 40}; +static u32 const vbat_vs_capacity_look_up[DA9052_NO_OF_LOOKUP_TABLE] + [DA9052_LOOK_UP_TABLE_SIZE][2] = { + /* For temperature 10 degree celisus*/ + { + {4082, 100}, {4036, 98}, + {4020, 96}, {4008, 95}, + {3997, 93}, {3983, 91}, + {3964, 90}, {3943, 88}, + {3926, 87}, {3912, 85}, + {3900, 84}, {3890, 82}, + {3881, 80}, {3873, 79}, + {3865, 77}, {3857, 76}, + {3848, 74}, {3839, 73}, + {3829, 71}, {3820, 70}, + {3811, 68}, {3802, 67}, + {3794, 65}, {3785, 64}, + {3778, 62}, {3770, 61}, + {3763, 59}, {3756, 58}, + {3750, 56}, {3744, 55}, + {3738, 53}, {3732, 52}, + {3727, 50}, {3722, 49}, + {3717, 47}, {3712, 46}, + {3708, 44}, {3703, 43}, + {3700, 41}, {3696, 40}, + {3693, 38}, {3691, 37}, + {3688, 35}, {3686, 34}, + {3683, 32}, {3681, 31}, + {3678, 29}, {3675, 28}, + {3672, 26}, {3669, 25}, + {3665, 23}, {3661, 22}, + {3656, 21}, {3651, 19}, + {3645, 18}, {3639, 16}, + {3631, 15}, {3622, 13}, + {3611, 12}, {3600, 10}, + {3587, 9}, {3572, 7}, + {3548, 6}, {3503, 5}, + {3420, 3}, {3268, 2}, + {2992, 1}, {2746, 0} + }, + /* For temperature 25 degree celisus */ + { + {4102, 100}, {4065, 98}, + {4048, 96}, {4034, 95}, + {4021, 93}, {4011, 92}, + {4001, 90}, {3986, 88}, + {3968, 87}, {3952, 85}, + {3938, 84}, {3926, 82}, + {3916, 81}, {3908, 79}, + {3900, 77}, {3892, 76}, + {3883, 74}, {3874, 73}, + {3864, 71}, {3855, 70}, + {3846, 68}, {3836, 67}, + {3827, 65}, {3819, 64}, + {3810, 62}, {3801, 61}, + {3793, 59}, {3786, 58}, + {3778, 56}, {3772, 55}, + {3765, 53}, {3759, 52}, + {3754, 50}, {3748, 49}, + {3743, 47}, {3738, 46}, + {3733, 44}, {3728, 43}, + {3724, 41}, {3720, 40}, + {3716, 38}, {3712, 37}, + {3709, 35}, {3706, 34}, + {3703, 33}, {3701, 31}, + {3698, 30}, {3696, 28}, + {3693, 27}, {3690, 25}, + {3687, 24}, {3683, 22}, + {3680, 21}, {3675, 19}, + {3671, 18}, {3666, 17}, + {3660, 15}, {3654, 14}, + {3647, 12}, {3639, 11}, + {3630, 9}, {3621, 8}, + {3613, 6}, {3606, 5}, + {3597, 4}, {3582, 2}, + {3546, 1}, {2747, 0} + }, + /* For temperature 40 degree celisus*/ + { + {4114, 100}, {4081, 98}, + {4065, 96}, {4050, 95}, + {4036, 93}, {4024, 92}, + {4013, 90}, {4002, 88}, + {3990, 87}, {3976, 85}, + {3962, 84}, {3950, 82}, + {3939, 81}, {3930, 79}, + {3921, 77}, {3912, 76}, + {3902, 74}, {3893, 73}, + {3883, 71}, {3874, 70}, + {3865, 68}, {3856, 67}, + {3847, 65}, {3838, 64}, + {3829, 62}, {3820, 61}, + {3812, 59}, {3803, 58}, + {3795, 56}, {3787, 55}, + {3780, 53}, {3773, 52}, + {3767, 50}, {3761, 49}, + {3756, 47}, {3751, 46}, + {3746, 44}, {3741, 43}, + {3736, 41}, {3732, 40}, + {3728, 38}, {3724, 37}, + {3720, 35}, {3716, 34}, + {3713, 33}, {3710, 31}, + {3707, 30}, {3704, 28}, + {3701, 27}, {3698, 25}, + {3695, 24}, {3691, 22}, + {3686, 21}, {3681, 19}, + {3676, 18}, {3671, 17}, + {3666, 15}, {3661, 14}, + {3655, 12}, {3648, 11}, + {3640, 9}, {3632, 8}, + {3622, 6}, {3616, 5}, + {3611, 4}, {3604, 2}, + {3594, 1}, {2747, 0} + } +}; + +enum charge_status_enum { + DA9052_NONE = 1, + DA9052_CHARGING, + DA9052_DISCHARGING_WITH_CHARGER, + DA9052_DISCHARGING_WITHOUT_CHARGER, + DA9052_PRECHARGING, + DA9052_LINEARCHARGING, + DA9052_CHARGEEND +}; + +enum charger_type_enum { + DA9052_NOCHARGER = 1, + DA9052_USB_HUB, + DA9052_USB_CHARGER, + DA9052_WALL_CHARGER +}; + +enum precharge_enum { + PRE_CHARGE_0MA = 0, + PRE_CHARGE_20MA = 20, + PRE_CHARGE_40MA = 40, + PRE_CHARGE_60MA = 60 +}; + +struct da9052_bat_event_registration { + u8 da9052_event_vddlow:1; + u8 da9052_event_tbat:1; +}; + +struct da9052_bat_threshold { + u16 vddout_mon; + u16 ichg_thr; + u16 tbat_thr_min; + u16 tbat_thr_max; + u16 tbat_thr_highns; + u16 tbat_thr_limit; + u16 tjunc_thr_limit; + u16 ichg_av_thr_min; + u16 ichg_av_thr_max; +}; + +struct da9052_bat_hysteresis { + u16 bat_volt_arr[3]; + u16 array_hys_batvoltage[2]; + u16 upper_limit; + u16 lower_limit; + u8 index; + u8 hys_flag; +}; + +struct da9052_bat_status { + u8 cal_capacity; + u8 charging_mode; + u8 charger_type; + u8 health; + u8 status; + u8 illegalbattery; +}; + +struct monitoring_state { + u16 vddout_value; + u16 bat_temp_value; + u16 current_value; + u16 junc_temp_value; + u8 bat_level; + u8 vddout_status:1; + u8 bat_temp_status:1; + u8 junc_temp_status:1; + u8 current_status:1; + u8 bat_level_status:1; +}; + +struct da9052_bat_device { + char manufacture[32]; + u16 chg_current_raw[DA9052_NUMBER_OF_STORE_CURENT_READING]; + u16 chg_current; + u16 chg_junc_temp; + u16 bat_voltage; + u16 backup_bat_voltage; + u16 bat_temp; + u16 vddout; +}; + +/* Below macro is for testing purpose only */ +#define DA9052_BAT_STATUS 1 + +#if (DA9052_BAT_STATUS == 1) +struct bat_thread_type { + u8 pid; + u8 state; + struct completion notifier; + struct task_struct *thread_task; +}; +#endif + +struct da9052_charger_device { + struct da9052_bat_threshold threshold; + struct da9052 *da9052; + struct da9052_bat_platform_data *bat_pdata; + struct delayed_work work; +#if (DA9052_BAT_STATUS == 1) + struct bat_thread_type print_bat_status; +#endif + struct power_supply psy; + struct da9052_eh_nb vddlow_eh_data; + struct da9052_eh_nb tbat_eh_data; + u16 monitoring_interval; + u8 hys_flag; + u16 charger_voltage_drop; + u16 bat_target_voltage; + u16 voltage_threshold; + u16 dcin_current; + u16 vbus_current; + u16 usb_charger_current;; + u16 chg_end_current; + u16 precharging_current; + u16 charging_time; + u8 timer_mode:1; + u8 charger_buck_lp:1; + u8 usb_charger_det:1; + u8 ichg_low_cntr:1; + u8 sw_temp_cntr:1; + u8 auto_temp_cntr:1; +}; + +static inline u8 bat_temp_reg_to_C(u16 value) { return (55 - value); } +static inline u8 bat_mV_to_reg(u16 value) { return (((value-4100)/100)<<4); } +static inline u8 bat_drop_mV_to_reg(u16 value) + { return (((value-100)/100)<<6); } +static inline u16 bat_reg_to_mV(u8 value) { return ((value*100) + 4100); } +static inline u16 bat_drop_reg_to_mV(u8 value) { return ((value*100)+100); } +static inline u8 vch_thr_mV_to_reg(u16 value) { return ((value-3700)/100); } +static inline u8 precharge_mA_to_reg(u8 value) { return ((value/20)<<6); } +static inline u8 vddout_mon_mV_to_reg(u16 value) + { return (((value-2500)*128)/1000); } +static inline u16 vddout_reg_to_mV(u8 value) + { return ((value*1000)/128)+2500; } +static inline u16 volt_reg_to_mV(u16 value) + { return ((value*1000)/512)+2500; } +static inline u8 ichg_mA_to_reg(u16 value) { return (value/4); } +static inline u16 ichg_reg_to_mA(u8 value) { return ((value*3900)/1000); } +static inline u8 iset_mA_to_reg(u16 iset_value) + {\ + if ((70 <= iset_value) && (iset_value <= 120)) \ + return (iset_value-70)/10; \ + else if ((400 <= iset_value) && (iset_value <= 700)) \ + return ((iset_value-400)/50)+6; \ + else if ((900 <= iset_value) && (iset_value <= 1300)) \ + return ((iset_value-900)/200)+13; else return 0; + } + +#define DA9052_BAT_DEBUG 0 + +#define DA9052_BAT_PROFILE 0 +#define SUCCESS 0 +#define FAILURE 1 + +#define TRUE 1 +#define FALSE 0 + +#define set_bits(value, mask) (value | mask) +#define clear_bits(value, mask) (value & ~(mask)) + +#undef DA9052_DEBUG +#if DA9052_BAT_DEBUG +#define DA9052_DEBUG(fmt, args...) printk(KERN_CRIT "" fmt, ##args) +#else +#define DA9052_DEBUG(fmt, args...) +#endif + + +/* SSC Read or Write Error */ +#define DA9052_SSC_FAIL 150 + +/* To enable debug output for your module, set this to 1 */ +#define DA9052_SSC_DEBUG 0 + +#undef DA9052_DEBUG +#if DA9052_SSC_DEBUG +#define DA9052_DEBUG(fmt, args...) printk(KERN_CRIT "" fmt, ##args) +#else +#define DA9052_DEBUG(fmt, args...) +#endif + + +#endif /* __LINUX_MFD_DA9052_BAT_H */ diff --git a/include/linux/mfd/da9052/bl.h b/include/linux/mfd/da9052/bl.h new file mode 100644 index 000000000000..9217eb95a77e --- /dev/null +++ b/include/linux/mfd/da9052/bl.h @@ -0,0 +1,289 @@ +/* + * da9052 Backlight module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_BL_H +#define __LINUX_MFD_DA9052_BL_H + +/* + * enum da9052_bl_current_value - Enum for current values of LED + * DA9052_BL_CURRENT_50_0UA: represents 50.0 uA current value + */ +enum da9052_bl_current_value { +/* Current Value for LEDMIN, LED1_CONF, LED2_CONF, LED3_CONF Registers */ + DA9052_BL_CURRENT_50_0UA = 0, + DA9052_BL_CURRENT_51_2UA, + DA9052_BL_CURRENT_52_5UA, + DA9052_BL_CURRENT_53_7UA, + DA9052_BL_CURRENT_55_1UA, + DA9052_BL_CURRENT_56_4UA, + DA9052_BL_CURRENT_57_8UA, + DA9052_BL_CURRENT_59_3UA, + DA9052_BL_CURRENT_60_7UA, + DA9052_BL_CURRENT_62_2UA, + DA9052_BL_CURRENT_63_8UA, + DA9052_BL_CURRENT_65_3UA, + DA9052_BL_CURRENT_67_0UA, + DA9052_BL_CURRENT_68_6UA, + DA9052_BL_CURRENT_70_3UA, + DA9052_BL_CURRENT_72_0UA, + DA9052_BL_CURRENT_73_8UA, + DA9052_BL_CURRENT_75_7UA, + DA9052_BL_CURRENT_77_5UA, + DA9052_BL_CURRENT_79_4UA, + DA9052_BL_CURRENT_81_4UA, + DA9052_BL_CURRENT_83_4UA, + DA9052_BL_CURRENT_85_5UA, + DA9052_BL_CURRENT_87_6UA, + DA9052_BL_CURRENT_89_8UA, + DA9052_BL_CURRENT_92_0UA, + DA9052_BL_CURRENT_94_2UA, + DA9052_BL_CURRENT_96_6UA, + DA9052_BL_CURRENT_99_0UA, + DA9052_BL_CURRENT_101_4UA, + DA9052_BL_CURRENT_103_9UA, + DA9052_BL_CURRENT_106_5UA, + DA9052_BL_CURRENT_109_1UA, + DA9052_BL_CURRENT_111_8UA, + DA9052_BL_CURRENT_114_6UA, + DA9052_BL_CURRENT_117_4UA, + DA9052_BL_CURRENT_120_6UA, + DA9052_BL_CURRENT_123_3UA, + DA9052_BL_CURRENT_126_3UA, + DA9052_BL_CURRENT_129_4UA, + DA9052_BL_CURRENT_132_6UA, + DA9052_BL_CURRENT_135_9UA, + DA9052_BL_CURRENT_139_3UA, + DA9052_BL_CURRENT_142_7UA, + DA9052_BL_CURRENT_146_2UA, + DA9052_BL_CURRENT_149_9UA, + DA9052_BL_CURRENT_153_6UA, + DA9052_BL_CURRENT_157_4UA, + DA9052_BL_CURRENT_161_2UA, + DA9052_BL_CURRENT_165_2UA, + DA9052_BL_CURRENT_169_3UA, + DA9052_BL_CURRENT_173_5UA, + DA9052_BL_CURRENT_177_8UA, + DA9052_BL_CURRENT_182_2UA, + DA9052_BL_CURRENT_186_7UA, + DA9052_BL_CURRENT_191_3UA, + DA9052_BL_CURRENT_196_0UA, + DA9052_BL_CURRENT_200_9UA, + DA9052_BL_CURRENT_205_8UA, + DA9052_BL_CURRENT_210_9UA, + DA9052_BL_CURRENT_216_1UA, + DA9052_BL_CURRENT_221_4UA, + DA9052_BL_CURRENT_226_9UA, + DA9052_BL_CURRENT_232_5UA, + DA9052_BL_CURRENT_238_3UA, + DA9052_BL_CURRENT_244_2UA, + DA9052_BL_CURRENT_250_2UA, + DA9052_BL_CURRENT_256_4UA, + DA9052_BL_CURRENT_262_7UA, + DA9052_BL_CURRENT_269_2UA, + DA9052_BL_CURRENT_275_8UA, + DA9052_BL_CURRENT_282_7UA, + DA9052_BL_CURRENT_289_6UA, + DA9052_BL_CURRENT_296_8UA, + DA9052_BL_CURRENT_304_1UA, + DA9052_BL_CURRENT_311_6UA, + DA9052_BL_CURRENT_319_3UA, + DA9052_BL_CURRENT_327_2UA, + DA9052_BL_CURRENT_335_3UA, + DA9052_BL_CURRENT_343_6UA, + DA9052_BL_CURRENT_352_1UA, + DA9052_BL_CURRENT_360_8UA, + DA9052_BL_CURRENT_369_7UA, + DA9052_BL_CURRENT_378_8UA, + DA9052_BL_CURRENT_388_2UA, + DA9052_BL_CURRENT_397_8UA, + DA9052_BL_CURRENT_407_6UA, + DA9052_BL_CURRENT_417_7UA, + DA9052_BL_CURRENT_428_0UA, + DA9052_BL_CURRENT_438_6UA, + DA9052_BL_CURRENT_449_4UA, + DA9052_BL_CURRENT_460_5UA, + DA9052_BL_CURRENT_471_9UA, + DA9052_BL_CURRENT_483_5UA, + DA9052_BL_CURRENT_495_5UA, + DA9052_BL_CURRENT_507_7UA, + DA9052_BL_CURRENT_520_3UA, + DA9052_BL_CURRENT_533_1UA, + DA9052_BL_CURRENT_546_3UA, + DA9052_BL_CURRENT_559_8UA, + DA9052_BL_CURRENT_573_6UA, + DA9052_BL_CURRENT_587_8UA, + DA9052_BL_CURRENT_602_3UA, + DA9052_BL_CURRENT_617_2UA, + DA9052_BL_CURRENT_632_4UA, + DA9052_BL_CURRENT_648_0UA, + DA9052_BL_CURRENT_664_0UA, + DA9052_BL_CURRENT_680_4UA, + DA9052_BL_CURRENT_697_2UA, + DA9052_BL_CURRENT_714_5UA, + DA9052_BL_CURRENT_732_1UA, + DA9052_BL_CURRENT_750_2UA, + DA9052_BL_CURRENT_768_7UA, + DA9052_BL_CURRENT_787_7UA, + DA9052_BL_CURRENT_807_2UA, + DA9052_BL_CURRENT_827_1UA, + DA9052_BL_CURRENT_847_6UA, + DA9052_BL_CURRENT_868_5UA, + DA9052_BL_CURRENT_889_9UA, + DA9052_BL_CURRENT_911_9UA, + DA9052_BL_CURRENT_934_4UA, + DA9052_BL_CURRENT_957_5UA, + DA9052_BL_CURRENT_981_2UA, + DA9052_BL_CURRENT_1005_4UA, + DA9052_BL_CURRENT_1030_3UA, + DA9052_BL_CURRENT_1055_7UA, + DA9052_BL_CURRENT_1081_8UA, + DA9052_BL_CURRENT_1108_5UA, + DA9052_BL_CURRENT_1135_9UA, + DA9052_BL_CURRENT_1163_9UA, + DA9052_BL_CURRENT_1192_7UA, + DA9052_BL_CURRENT_1222_2UA, + DA9052_BL_CURRENT_1252_3UA, + DA9052_BL_CURRENT_1283_3UA, + DA9052_BL_CURRENT_1315_0UA, + DA9052_BL_CURRENT_1347_5UA, + DA9052_BL_CURRENT_1380_7UA, + DA9052_BL_CURRENT_1414_8UA, + DA9052_BL_CURRENT_1449_8UA, + DA9052_BL_CURRENT_1485_6UA, + DA9052_BL_CURRENT_1522_3UA, + DA9052_BL_CURRENT_1559_9UA, + DA9052_BL_CURRENT_1598_4UA, + DA9052_BL_CURRENT_1637_9UA, + DA9052_BL_CURRENT_1678_4UA, + DA9052_BL_CURRENT_1719_8UA, + DA9052_BL_CURRENT_1762_3UA, + DA9052_BL_CURRENT_1805_8UA, + DA9052_BL_CURRENT_1850_4UA, + DA9052_BL_CURRENT_1896_1UA, + DA9052_BL_CURRENT_1943_0UA, + DA9052_BL_CURRENT_1991_0UA, + DA9052_BL_CURRENT_2040_2UA, + DA9052_BL_CURRENT_2090_5UA, + DA9052_BL_CURRENT_2142_2UA, + DA9052_BL_CURRENT_2195_1UA, + DA9052_BL_CURRENT_2249_3UA, + DA9052_BL_CURRENT_2304_9UA, + DA9052_BL_CURRENT_2361_8UA, + DA9052_BL_CURRENT_2420_1UA, + DA9052_BL_CURRENT_2479_9UA, + DA9052_BL_CURRENT_2541_2UA, + DA9052_BL_CURRENT_2604_0UA, + DA9052_BL_CURRENT_2668_3UA, + DA9052_BL_CURRENT_2734_2UA, + DA9052_BL_CURRENT_2801_7UA, + DA9052_BL_CURRENT_2870_9UA, + DA9052_BL_CURRENT_2941_8UA, + DA9052_BL_CURRENT_3014_5UA, + DA9052_BL_CURRENT_3089_0UA, + DA9052_BL_CURRENT_3165_3UA, + DA9052_BL_CURRENT_3243_4UA, + DA9052_BL_CURRENT_3323_5UA, + DA9052_BL_CURRENT_3405_6UA, + DA9052_BL_CURRENT_3489_8UA, + DA9052_BL_CURRENT_3576_0UA, + DA9052_BL_CURRENT_3664_3UA, + DA9052_BL_CURRENT_3754_8UA, + DA9052_BL_CURRENT_3847_5UA, + DA9052_BL_CURRENT_3942_6UA, + DA9052_BL_CURRENT_4040_0UA, + DA9052_BL_CURRENT_4139_7UA, + DA9052_BL_CURRENT_4242_0UA, + DA9052_BL_CURRENT_4346_8UA, + DA9052_BL_CURRENT_4454_1UA, + DA9052_BL_CURRENT_4564_2UA, + DA9052_BL_CURRENT_4676_9UA, + DA9052_BL_CURRENT_4792_4UA, + DA9052_BL_CURRENT_4910_8UA, + DA9052_BL_CURRENT_5032_1UA, + DA9052_BL_CURRENT_5156_4UA, + DA9052_BL_CURRENT_5283_7UA, + DA9052_BL_CURRENT_5414_3UA, + DA9052_BL_CURRENT_5548_0UA, + DA9052_BL_CURRENT_5685_0UA, + DA9052_BL_CURRENT_5825_5UA, + DA9052_BL_CURRENT_5969_3UA, + DA9052_BL_CURRENT_6116_8UA, + DA9052_BL_CURRENT_6267_9UA, + DA9052_BL_CURRENT_6422_7UA, + DA9052_BL_CURRENT_6581_3UA, + DA9052_BL_CURRENT_6743_9UA, + DA9052_BL_CURRENT_6910_5UA, + DA9052_BL_CURRENT_7081_2UA, + DA9052_BL_CURRENT_7256_1UA, + DA9052_BL_CURRENT_7435_3UA, + DA9052_BL_CURRENT_7618_9UA, + DA9052_BL_CURRENT_7807_1UA, + DA9052_BL_CURRENT_8000_0UA, + DA9052_BL_CURRENT_8197_6UA, + DA9052_BL_CURRENT_8400_0UA, + DA9052_BL_CURRENT_8607_5UA, + DA9052_BL_CURRENT_8820_1UA, + DA9052_BL_CURRENT_9038_0UA, + DA9052_BL_CURRENT_9261_2UA, + DA9052_BL_CURRENT_9490_0UA, + DA9052_BL_CURRENT_9724_4UA, + DA9052_BL_CURRENT_9964_6UA, + DA9052_BL_CURRENT_10210_7UA, + DA9052_BL_CURRENT_10462_9UA, + DA9052_BL_CURRENT_10721_4UA, + DA9052_BL_CURRENT_10986_4UA, + DA9052_BL_CURRENT_11257_5UA, + DA9052_BL_CURRENT_11535_6UA, + DA9052_BL_CURRENT_11820_5UA, + DA9052_BL_CURRENT_12112_5UA, + DA9052_BL_CURRENT_12411_7UA, + DA9052_BL_CURRENT_12718_2UA, + DA9052_BL_CURRENT_13032_4UA, + DA9052_BL_CURRENT_13354_3UA, + DA9052_BL_CURRENT_13684_1UA, + DA9052_BL_CURRENT_14022_1UA, + DA9052_BL_CURRENT_14368_5UA, + DA9052_BL_CURRENT_14723_4UA, + DA9052_BL_CURRENT_15087_1UA, + DA9052_BL_CURRENT_15459_7UA, + DA9052_BL_CURRENT_15841_6UA, + DA9052_BL_CURRENT_16232_9UA, + DA9052_BL_CURRENT_16633_8UA, + DA9052_BL_CURRENT_17044_7UA, + DA9052_BL_CURRENT_17465_7UA, + DA9052_BL_CURRENT_17897_1UA, + DA9052_BL_CURRENT_18339_1UA, + DA9052_BL_CURRENT_18792_1UA, + DA9052_BL_CURRENT_19256_3UA, + DA9052_BL_CURRENT_19731_9UA, + DA9052_BL_CURRENT_20219_3UA, + DA9052_BL_CURRENT_20718_7UA, + DA9052_BL_CURRENT_21230_5UA, + DA9052_BL_CURRENT_21754_8UA, + DA9052_BL_CURRENT_22292_2UA, + DA9052_BL_CURRENT_22842_8UA, + DA9052_BL_CURRENT_23407_0UA, + DA9052_BL_CURRENT_23985_2UA, + DA9052_BL_CURRENT_24577_6UA, + DA9052_BL_CURRENT_25000_0UA, +}; + +#endif /* __LINUX_MFD_DA9052_BL_H */ diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h new file mode 100644 index 000000000000..6070696b658d --- /dev/null +++ b/include/linux/mfd/da9052/da9052.h @@ -0,0 +1,228 @@ +/* + * da9052 declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_DA9052_H +#define __LINUX_MFD_DA9052_DA9052_H + +#include +#include + +#include +#include +#include + + +#define SPI 1 +#define I2C 2 + +#define DA9052_SSC_DEVICE_NAME "da9052_ssc" +#define DA9052_EH_DEVICE_NAME "da9052_eh" + +#define DA9052_IRQ S3C_EINT(9) + +/* Module specific error codes */ +#define INVALID_REGISTER 2 +#define INVALID_READ 3 +#define INVALID_PAGE 4 + +/* Defines for Volatile and Non Volatile register types */ +#define VOLATILE 0 +#define NON_VOLATILE 1 + +/* Defines for cache state */ +#define VALID 0 +#define INVALID 1 + +/* Total number of registers in DA9057 */ +#define DA9052_REG_CNT DA9052_PAGE1_REG_END + +/* Maximum number of registers that can be read/written by a singe request */ +#define MAX_READ_WRITE_CNT 16 + + +#define DA9052_SSC_SPI_DEVICE_NAME "da9052_ssc_spi" +#define PAGE_0_START 1 +#define PAGE_0_END 127 +#define PAGE_1_START 128 +#define PAGE_1_END 255 +#define ACTIVE_PAGE_0 0 +#define ACTIVE_PAGE_1 1 +#define PAGECON_0 0 +#define PAGECON_128 128 +#define RW_POL 1 + +#define DA9052_SSC_I2C_DEVICE_NAME "da9052_ssc_i2c" +#define DA9052_I2C_ADDR 0x90 +#define DA9052_SSC_I2C_PAGE_WRITE_MODE 0 +#define DA9052_SSC_I2C_REPEAT_WRITE_MODE 1 +#define DA9052_SSC_I2C_WRITE_MODE DA9052_SSC_I2C_REPEAT_WRITE_MODE + +struct da9052_ssc_msg { + unsigned char data; + unsigned char addr; +}; + +struct ssc_cache_entry{ + unsigned char val; + unsigned char type:4; + unsigned char status:4; +}; + +struct da9052_eh_nb{ + struct list_head nb_list; + unsigned char eve_type; + void (*call_back)(struct da9052_eh_nb *, unsigned int); +}; + + +struct da9052_regulator_init_data { + struct regulator_init_data *init_data; + int id; +}; + +struct da9052_regulator_platform_data { + struct regulator_init_data *regulators; +}; + +struct da9052_tsi_platform_data { + u32 pen_up_interval; + u16 tsi_delay_bit_shift; + u16 tsi_skip_bit_shift; + u16 num_gpio_tsi_register; + u16 tsi_supply_voltage; + u16 tsi_ref_source; + u16 max_tsi_delay; + u16 max_tsi_skip_slot; +}; + + +struct da9052_bat_platform_data { + u16 sw_temp_control_en; + u16 monitoring_interval; + u16 sw_bat_temp_threshold; + u16 sw_junc_temp_threshold; + u16 hysteresis_window_size; + u16 current_monitoring_window; + u16 bat_with_no_resistor; + u16 bat_capacity_limit_low; + u16 bat_capacity_full; + u16 bat_capacity_limit_high; + u16 chg_hysteresis_const; + u16 hysteresis_reading_interval; + u16 hysteresis_no_of_reading; + u16 filter_size; + u16 bat_volt_cutoff; + u16 vbat_first_valid_detect_iteration; +}; + +struct da9052 { + struct mutex ssc_lock; + struct mutex eve_nb_lock; + struct mutex manconv_lock; + struct work_struct eh_isr_work; + struct ssc_cache_entry ssc_cache[DA9052_REG_CNT]; + int (*read) (struct da9052 *da9052, struct da9052_ssc_msg *sscmsg); + int (*write) (struct da9052 *da9052, struct da9052_ssc_msg *sscmsg); + int (*read_many) (struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int cnt); + int (*write_many)(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int cnt); + int (*register_event_notifier)(struct da9052 *da9052, + struct da9052_eh_nb *nb); + int (*unregister_event_notifier)(struct da9052 *da9052, + struct da9052_eh_nb *nb); + int num_regulators; + int connecting_device; + int irq; + struct spi_device *spi_dev; + unsigned int spi_active_page; + unsigned char rw_pol; + unsigned char *spi_rx_buf; + unsigned char *spi_tx_buf; + + struct i2c_client *i2c_client; + struct device *dev; + struct i2c_adapter *adapter; + unsigned char slave_addr; +}; + +struct da9052_platform_data { + int (*init)(struct da9052 *da9052); + int irq_high; + int irq_base; + int gpio_base; + int num_regulators; + struct da9052 *da9052; + struct regulator_init_data *regulators; + struct da9052_leds_platform_data *led_data; + struct da9052_tsi_platform_data *tsi_data; + struct da9052_bat_platform_data *bat_data; +}; + +struct da9052_ssc_ops { + int (*write)(struct da9052 *da9052, struct da9052_ssc_msg *msg); + int (*read)(struct da9052 *da9052, struct da9052_ssc_msg *msg); + int (*write_many)(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no); + int (*read_many)(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no); + int (*device_register)(struct da9052 *da9052); + void (*device_unregister)(void); +}; + +int da9052_ssc_write(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg); +int da9052_ssc_read(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg); +int da9052_ssc_write_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int cnt); +int da9052_ssc_read_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int cnt); + +int da9052_spi_write(struct da9052 *da9052, + struct da9052_ssc_msg *msg); +int da9052_spi_read(struct da9052 *da9052, + struct da9052_ssc_msg *msg); + +int da9052_spi_write_many(struct da9052 *da9052, struct da9052_ssc_msg *sscmsg, + int msg_no); +int da9052_spi_read_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, + int msg_no); + +void da9052_ssc_exit(struct da9052 *da9052); +int da9052_ssc_init(struct da9052 *da9052); + +/* I2C specific Functions */ +int da9052_i2c_write(struct da9052 *da9052, struct da9052_ssc_msg *msg); +int da9052_i2c_read(struct da9052 *da9052, struct da9052_ssc_msg *msg); +int da9052_i2c_write_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no); +int da9052_i2c_read_many(struct da9052 *da9052, + struct da9052_ssc_msg *sscmsg, int msg_no); + +void da9052_lock(struct da9052 *da9052); +void da9052_unlock(struct da9052 *da9052); +int eh_register_nb(struct da9052 *da9052, struct da9052_eh_nb *nb); +int eh_unregister_nb(struct da9052 *da9052, struct da9052_eh_nb *nb); +int da9052_manual_read(struct da9052 *da9052, + unsigned char channel); +#endif /* __LINUX_MFD_DA9052_DA9052_H */ diff --git a/include/linux/mfd/da9052/eh.h b/include/linux/mfd/da9052/eh.h new file mode 100644 index 000000000000..55de50fd04a2 --- /dev/null +++ b/include/linux/mfd/da9052/eh.h @@ -0,0 +1,74 @@ +/* + * da9052 Event Handler module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_EH_H +#define __LINUX_MFD_DA9052_EH_H + +/* Define for all possible events */ +#define DCIN_DET_EVE 0 +#define VBUS_DET_EVE 1 +#define DCIN_REM_EVE 2 +#define VBUS_REM_EVE 3 +#define VDD_LOW_EVE 4 +#define ALARM_EVE 5 +#define SEQ_RDY_EVE 6 +#define COMP_1V2 7 +#define ONKEY_EVE 8 +#define ID_FLOAT_EVE 9 +#define ID_GND_EVE 10 +#define CHG_END_EVE 11 +#define TBAT_EVE 12 +#define ADC_EOM_EVE 13 +#define PEN_DOWN_EVE 14 +#define TSI_READY_EVE 15 +#define GPI0_EVE 16 +#define GPI1_EVE 17 +#define GPI2_EVE 18 +#define GPI3_EVE 19 +#define GPI4_EVE 20 +#define GPI5_EVE 21 +#define GPI6_EVE 22 +#define GPI7_EVE 23 +#define GPI8_EVE 24 +#define GPI9_EVE 25 +#define GPI10_EVE 26 +#define GPI11_EVE 27 +#define GPI12_EVE 28 +#define GPI13_EVE 29 +#define GPI14_EVE 30 +#define GPI15_EVE 31 + +/* Total number of events */ +#define EVE_CNT (GPI15_EVE+1) + +/* Error code for register/unregister functions */ +#define INVALID_NB 2 +#define INVALID_EVE 3 + +/* State for EH thread */ +#define ACTIVE 0 +#define INACTIVE 1 + +/* Status of nIRQ line */ +#define IRQ_HIGH 0 +#define IRQ_LOW 1 + +#endif /* __LINUX_MFD_DA9052_EH_H */ diff --git a/include/linux/mfd/da9052/gpio.h b/include/linux/mfd/da9052/gpio.h new file mode 100644 index 000000000000..68a24ad9d828 --- /dev/null +++ b/include/linux/mfd/da9052/gpio.h @@ -0,0 +1,253 @@ +/* + * da9052 GPIO module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_GPIO_H +#define __LINUX_MFD_DA9052_GPIO_H + +#include +#define DA9052_GPIO_DEVICE_NAME "da9052_gpio" + +#define DA9052_GPIO_INVALID_TYPE 1 +#define DA9052_GPIO_INVALID_MODE 2 +#define DA9052_GPIO_INVALID_PORTNUMBER 3 +#define DA9052_GPIO_INVALID_FUNCTION 4 + +#define DA9052_GPIO_CONFIG_ADC 1 +#define DA9052_GPIO_CONFIG_TSI 2 +#define DA9052_GPIO_CONFIG_PM 3 +#define DA9052_GPIO_CONFIG_ACC_ID_DET 4 +#define DA9052_GPIO_CONFIG_GP_FB1 5 +#define DA9052_GPIO_CONFIG_VDD_FAULT 6 +#define DA9052_GPIO_CONFIG_I2C 7 +#define DA9052_GPIO_CONFIG 8 + +/* Currently used defines for GPIO PINs */ +#define DA9052_GPIO_PIN_0 DA9052_GPIO_CONFIG_ADC +#define DA9052_GPIO_PIN_1 DA9052_GPIO_CONFIG_ADC +#define DA9052_GPIO_PIN_2 DA9052_GPIO_CONFIG_ADC + +#define DA9052_GPIO_PIN_3 DA9052_GPIO_CONFIG_TSI +#define DA9052_GPIO_PIN_4 DA9052_GPIO_CONFIG_TSI +#define DA9052_GPIO_PIN_5 DA9052_GPIO_CONFIG_TSI +#define DA9052_GPIO_PIN_6 DA9052_GPIO_CONFIG_TSI +#define DA9052_GPIO_PIN_7 DA9052_GPIO_CONFIG_TSI + +#define DA9052_GPIO_PIN_8 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_9 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_10 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_11 DA9052_GPIO_CONFIG + +#define DA9052_GPIO_PIN_12 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_13 DA9052_GPIO_CONFIG + +#define DA9052_GPIO_PIN_14 DA9052_GPIO_CONFIG +#define DA9052_GPIO_PIN_15 DA9052_GPIO_CONFIG + +enum ip_op_type { + ALTERNATE_FUNCTIONALITY = 0, + INPUT, + OUTPUT_OPENDRAIN, + OUTPUT_PUSHPULL +}; + +enum ip_type { + ACTIVE_LOW = 0, + ACTIVE_HIGH +}; + +enum op_type { + SUPPLY_VDD_IO1 = 0, + SUPPLY_VDD_IO2 +}; + + +enum op_mode { + OUTPUT_LOWLEVEL = 0, + OUTPUT_HIGHLEVEL +}; + + +enum ip_mode { + DEBOUNCING_OFF = 0, + DEBOUNCING_ON +}; + +/*DEFAULT CONFIG FOR GPIO 0*/ +#if (DA9052_GPIO_PIN_0 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO0_FUNCTION INPUT +#define DEFAULT_GPIO0_TYPE ACTIVE_LOW +#define DEFAULT_GPIO0_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 1*/ +#if (DA9052_GPIO_PIN_1 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO1_FUNCTION INPUT +#define DEFAULT_GPIO1_TYPE ACTIVE_LOW +#define DEFAULT_GPIO1_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 2*/ +#if (DA9052_GPIO_PIN_2 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO2_FUNCTION INPUT +#define DEFAULT_GPIO2_TYPE ACTIVE_LOW +#define DEFAULT_GPIO2_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 3*/ +#if (DA9052_GPIO_PIN_3 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO3_FUNCTION INPUT +#define DEFAULT_GPIO3_TYPE ACTIVE_LOW +#define DEFAULT_GPIO3_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 4*/ +#if (DA9052_GPIO_PIN_4 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO4_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO4_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO4_MODE OUTPUT_LOWLEVEL +#endif +/*DEFAULT CONFIG FOR GPIO 5*/ +#if (DA9052_GPIO_PIN_5 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO5_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO5_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO5_MODE OUTPUT_LOWLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 6*/ +#if (DA9052_GPIO_PIN_6 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO6_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO6_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO6_MODE OUTPUT_LOWLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 7*/ +#if (DA9052_GPIO_PIN_7 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO7_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO7_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO7_MODE OUTPUT_LOWLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 8*/ +#if (DA9052_GPIO_PIN_8 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO8_FUNCTION INPUT +#define DEFAULT_GPIO8_TYPE ACTIVE_LOW +#define DEFAULT_GPIO8_MODE DEBOUNCING_ON +#endif + +/*DEFAULT CONFIG FOR GPIO 9*/ +#if (DA9052_GPIO_PIN_9 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO9_FUNCTION INPUT +#define DEFAULT_GPIO9_TYPE ACTIVE_LOW +#define DEFAULT_GPIO9_MODE DEBOUNCING_ON +#endif + +#if (DA9052_GPIO_PIN_10 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO10_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO10_TYPE SUPPLY_VDD_IO2 +#define DEFAULT_GPIO10_MODE OUTPUT_HIGHLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 11 - for RTC blinking LED */ +#if (DA9052_GPIO_PIN_11 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO11_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO11_TYPE SUPPLY_VDD_IO2 +#define DEFAULT_GPIO11_MODE OUTPUT_HIGHLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 12*/ +#if (DA9052_GPIO_PIN_12 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO12_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO12_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO12_MODE OUTPUT_LOWLEVEL +#endif +/*DEFAULT CONFIG FOR GPIO 13*/ +#if (DA9052_GPIO_PIN_13 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO13_FUNCTION OUTPUT_PUSHPULL +#define DEFAULT_GPIO13_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO13_MODE OUTPUT_LOWLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 14 - for LED4 */ +#if (DA9052_GPIO_PIN_14 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO14_FUNCTION OUTPUT_OPENDRAIN +#define DEFAULT_GPIO14_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO14_MODE OUTPUT_HIGHLEVEL +#endif + +/*DEFAULT CONFIG FOR GPIO 15 - for LED5 */ +#if (DA9052_GPIO_PIN_15 == DA9052_GPIO_CONFIG) +#define DEFAULT_GPIO15_FUNCTION OUTPUT_OPENDRAIN +#define DEFAULT_GPIO15_TYPE SUPPLY_VDD_IO1 +#define DEFAULT_GPIO15_MODE OUTPUT_HIGHLEVEL +#endif + +#define DA9052_GPIO_MAX_PORTNUMBER 16 +#define DA9052_GPIO_MAX_PORTS_PER_REGISTER 8 +#define DA9052_GPIO_SHIFT_COUNT(no) ((no)%8) +#define DA9052_GPIO_EVEN_PORT_FUNCTIONALITY 0x03 +#define DA9052_GPIO_ODD_PORT_FUNCTIONALITY 0x30 +#define DA9052_GPIO_MASK_UPPER_NIBBLE 0xF0 +#define DA9052_GPIO_MASK_LOWER_NIBBLE 0x0F +#define DA9052_GPIO_NIBBLE_SHIFT 4 +#define DA9052_GPIO_EVEN_PORT_WRITE_MODE (1 << 3) +#define DA9052_GPIO_ODD_PORT_WRITE_MODE (1 << 7) + + +struct da9052_gpio_read_write { + u8 port_number:4; + u8 read_write_value:1; +} ; + +struct da9052_gpio_multiple_read { + u8 signal_value[16]; +}; + +struct da9052_gpi_config { + enum ip_type type; + enum ip_mode mode; +}; + +struct da9052_gpo_config { + enum op_type type; + enum op_mode mode; +} ; + +union da9052_gpio_config { + struct da9052_gpi_config input; + struct da9052_gpo_config output; +}; + +struct da9052_gpio { + union da9052_gpio_config gpio_config; + enum ip_op_type gpio_function; + u8 port_number:4; +}; + +struct da9052_gpio_chip { + struct da9052_gpio gpio; + struct da9052_gpio_read_write read_write; + struct da9052 *da9052; + /* For testing*/ + struct da9052_eh_nb eh_data; + struct gpio_chip gp; +}; + +#endif /* __LINUX_MFD_DA9052_GPIO_H */ diff --git a/include/linux/mfd/da9052/led.h b/include/linux/mfd/da9052/led.h new file mode 100644 index 000000000000..b4145cd2023d --- /dev/null +++ b/include/linux/mfd/da9052/led.h @@ -0,0 +1,39 @@ +/* + * da9052 LED module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_LED_H +#define __LINUX_MFD_DA9052_LED_H + +struct da9052_led_platform_data { +#define DA9052_LED_4 4 +#define DA9052_LED_5 5 +#define DA9052_LED_MAX 2 + int id; + const char *name; + const char *default_trigger; +}; + +struct da9052_leds_platform_data { + int num_leds; + struct da9052_led_platform_data *led; +}; + +#endif /* __LINUX_MFD_DA9052_LED_H */ diff --git a/include/linux/mfd/da9052/pm.h b/include/linux/mfd/da9052/pm.h new file mode 100644 index 000000000000..9fdb87c3f260 --- /dev/null +++ b/include/linux/mfd/da9052/pm.h @@ -0,0 +1,75 @@ +/* + * da9052 Power Management module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_PM_H +#define __LINUX_MFD_DA9052_PM_H + +/* PM Device name and static Major number macros */ +#define DRIVER_NAME "da9052-regulator" + +/* PM Device Macros */ +#define DA9052_LDO1 0 +#define DA9052_LDO2 1 +#define DA9052_LDO3 2 +#define DA9052_LDO4 3 +#define DA9052_LDO5 4 +#define DA9052_LDO6 5 +#define DA9052_LDO7 6 +#define DA9052_LDO8 7 +#define DA9052_LDO9 8 +#define DA9052_LDO10 9 +#define DA9052_BUCK_CORE 10 +#define DA9052_BUCK_PRO 11 +#define DA9052_BUCK_MEM 12 +#define DA9052_BUCK_PERI 13 + +/* PM Device Error Codes */ + +/* Buck Config Validation Macros */ +#define DA9052_BUCK_CORE_PRO_VOLT_UPPER 2075 +#define DA9052_BUCK_CORE_PRO_VOLT_LOWER 500 +#define DA9052_BUCK_CORE_PRO_STEP 25 +#define DA9052_BUCK_MEM_VOLT_UPPER 2500 +#define DA9052_BUCK_MEM_VOLT_LOWER 925 +#define DA9052_BUCK_MEM_STEP 25 +#define DA9052_BUCK_PERI_VOLT_UPPER 3600 +#define DA9052_BUCK_PERI_VOLT_LOWER 1800 +#define DA9052_BUCK_PERI_STEP_BELOW_3000 50 +#define DA9052_BUCK_PERI_STEP_ABOVE_3000 100000 +#define DA9052_BUCK_PERI_VALUES_UPTO_3000 24 +#define DA9052_BUCK_PERI_VALUES_3000 3000000 +#define DA9052_LDO1_VOLT_UPPER 1800 +#define DA9052_LDO1_VOLT_LOWER 600 +#define DA9052_LDO1_VOLT_STEP 50 +#define DA9052_LDO2_VOLT_UPPER 1800 +#define DA9052_LDO2_VOLT_LOWER 600 +#define DA9052_LDO2_VOLT_STEP 25 +#define DA9052_LDO34_VOLT_UPPER 3300 +#define DA9052_LDO34_VOLT_LOWER 1725 +#define DA9052_LDO34_VOLT_STEP 25 +#define DA9052_LDO567810_VOLT_UPPER 3600 +#define DA9052_LDO567810_VOLT_LOWER 1200 +#define DA9052_LDO567810_VOLT_STEP 50 +#define DA9052_LDO9_VOLT_STEP 50 +#define DA9052_LDO9_VOLT_LOWER 1250 +#define DA9052_LDO9_VOLT_UPPER 3650 + +#endif /* __LINUX_MFD_DA9052_PM_H */ diff --git a/include/linux/mfd/da9052/reg.h b/include/linux/mfd/da9052/reg.h new file mode 100644 index 000000000000..65522303e896 --- /dev/null +++ b/include/linux/mfd/da9052/reg.h @@ -0,0 +1,922 @@ +/* + * da9052 register declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_REG_H +#define __LINUX_MFD_DA9052_REG_H + +#define DA9052_PAGECON0_REG 0 +#define DA9052_STATUSA_REG 1 +#define DA9052_STATUSB_REG 2 +#define DA9052_STATUSC_REG 3 +#define DA9052_STATUSD_REG 4 +#define DA9052_EVENTA_REG 5 +#define DA9052_EVENTB_REG 6 +#define DA9052_EVENTC_REG 7 +#define DA9052_EVENTD_REG 8 +#define DA9052_FAULTLOG_REG 9 +#define DA9052_IRQMASKA_REG 10 +#define DA9052_IRQMASKB_REG 11 +#define DA9052_IRQMASKC_REG 12 +#define DA9052_IRQMASKD_REG 13 +#define DA9052_CONTROLA_REG 14 +#define DA9052_CONTROLB_REG 15 +#define DA9052_CONTROLC_REG 16 +#define DA9052_CONTROLD_REG 17 +#define DA9052_PDDIS_REG 18 +#define DA9052_INTERFACE_REG 19 +#define DA9052_RESET_REG 20 +#define DA9052_GPIO0001_REG 21 +#define DA9052_GPIO0203_REG 22 +#define DA9052_GPIO0405_REG 23 +#define DA9052_GPIO0607_REG 24 +#define DA9052_GPIO0809_REG 25 +#define DA9052_GPIO1011_REG 26 +#define DA9052_GPIO1213_REG 27 +#define DA9052_GPIO1415_REG 28 +#define DA9052_ID01_REG 29 +#define DA9052_ID23_REG 30 +#define DA9052_ID45_REG 31 +#define DA9052_ID67_REG 32 +#define DA9052_ID89_REG 33 +#define DA9052_ID1011_REG 34 +#define DA9052_ID1213_REG 35 +#define DA9052_ID1415_REG 36 +#define DA9052_ID1617_REG 37 +#define DA9052_ID1819_REG 38 +#define DA9052_ID2021_REG 39 +#define DA9052_SEQSTATUS_REG 40 +#define DA9052_SEQA_REG 41 +#define DA9052_SEQB_REG 42 +#define DA9052_SEQTIMER_REG 43 +#define DA9052_BUCKA_REG 44 +#define DA9052_BUCKB_REG 45 +#define DA9052_BUCKCORE_REG 46 +#define DA9052_BUCKPRO_REG 47 +#define DA9052_BUCKMEM_REG 48 +#define DA9052_BUCKPERI_REG 49 +#define DA9052_LDO1_REG 50 +#define DA9052_LDO2_REG 51 +#define DA9052_LDO3_REG 52 +#define DA9052_LDO4_REG 53 +#define DA9052_LDO5_REG 54 +#define DA9052_LDO6_REG 55 +#define DA9052_LDO7_REG 56 +#define DA9052_LDO8_REG 57 +#define DA9052_LDO9_REG 58 +#define DA9052_LDO10_REG 59 +#define DA9052_SUPPLY_REG 60 +#define DA9052_PULLDOWN_REG 61 +#define DA9052_CHGBUCK_REG 62 +#define DA9052_WAITCONT_REG 63 +#define DA9052_ISET_REG 64 +#define DA9052_BATCHG_REG 65 +#define DA9052_CHGCONT_REG 66 +#define DA9052_INPUTCONT_REG 67 +#define DA9052_CHGTIME_REG 68 +#define DA9052_BBATCONT_REG 69 +#define DA9052_BOOST_REG 70 +#define DA9052_LEDCONT_REG 71 +#define DA9052_LEDMIN123_REG 72 +#define DA9052_LED1CONF_REG 73 +#define DA9052_LED2CONF_REG 74 +#define DA9052_LED3CONF_REG 75 +#define DA9052_LED1CONT_REG 76 +#define DA9052_LED2CONT_REG 77 +#define DA9052_LED3CONT_REG 78 +#define DA9052_LED4CONT_REG 79 +#define DA9052_LED5CONT_REG 80 +#define DA9052_ADCMAN_REG 81 +#define DA9052_ADCCONT_REG 82 +#define DA9052_ADCRESL_REG 83 +#define DA9052_ADCRESH_REG 84 +#define DA9052_VDDRES_REG 85 +#define DA9052_VDDMON_REG 86 +#define DA9052_ICHGAV_REG 87 +#define DA9052_ICHGTHD_REG 88 +#define DA9052_ICHGEND_REG 89 +#define DA9052_TBATRES_REG 90 +#define DA9052_TBATHIGHP_REG 91 +#define DA9052_TBATHIGHIN_REG 92 +#define DA9052_TBATLOW_REG 93 +#define DA9052_TOFFSET_REG 94 +#define DA9052_ADCIN4RES_REG 95 +#define DA9052_AUTO4HIGH_REG 96 +#define DA9052_AUTO4LOW_REG 97 +#define DA9052_ADCIN5RES_REG 98 +#define DA9052_AUTO5HIGH_REG 99 +#define DA9052_AUTO5LOW_REG 100 +#define DA9052_ADCIN6RES_REG 101 +#define DA9052_AUTO6HIGH_REG 102 +#define DA9052_AUTO6LOW_REG 103 +#define DA9052_TJUNCRES_REG 104 +#define DA9052_TSICONTA_REG 105 +#define DA9052_TSICONTB_REG 106 +#define DA9052_TSIXMSB_REG 107 +#define DA9052_TSIYMSB_REG 108 +#define DA9052_TSILSB_REG 109 +#define DA9052_TSIZMSB_REG 110 +#define DA9052_COUNTS_REG 111 +#define DA9052_COUNTMI_REG 112 +#define DA9052_COUNTH_REG 113 +#define DA9052_COUNTD_REG 114 +#define DA9052_COUNTMO_REG 115 +#define DA9052_COUNTY_REG 116 +#define DA9052_ALARMMI_REG 117 +#define DA9052_ALARMH_REG 118 +#define DA9052_ALARMD_REG 119 +#define DA9052_ALARMMO_REG 120 +#define DA9052_ALARMY_REG 121 +#define DA9052_SECONDA_REG 122 +#define DA9052_SECONDB_REG 123 +#define DA9052_SECONDC_REG 124 +#define DA9052_SECONDD_REG 125 +#define DA9052_PAGECON128_REG 128 +#define DA9052_CHIPID_REG 129 +#define DA9052_CONFIGID_REG 130 +#define DA9052_OTPCONT_REG 131 +#define DA9052_OSCTRIM_REG 132 +#define DA9052_GPID0_REG 133 +#define DA9052_GPID1_REG 134 +#define DA9052_GPID2_REG 135 +#define DA9052_GPID3_REG 136 +#define DA9052_GPID4_REG 137 +#define DA9052_GPID5_REG 138 +#define DA9052_GPID6_REG 139 +#define DA9052_GPID7_REG 140 +#define DA9052_GPID8_REG 141 +#define DA9052_GPID9_REG 142 + +#define DA9052_PAGE0_REG_START (DA9052_STATUSA_REG) +#define DA9052_PAGE0_REG_END (DA9052_SECONDD_REG) + +#define DA9052_PAGE1_REG_START (DA9052_CHIPID_REG) +#define DA9052_PAGE1_REG_END (DA9052_GPID9_REG) + +/* PAGE CONFIGURATION */ + +/* Reg Page Configuration */ +#define DA9052_PAGECON0_REGPAGE (1<<7) + +/* PAGE CONFIGURATION 128 REGISTER */ +#define DA9052_PAGECON128_REGPAGE (1<<7) + +/* SYSTEM REGISTER */ + +/* STATUS REGISTER A */ +#define DA9052_STATUSA_VDATDET (1<<7) +#define DA9052_STATUSA_VBUSSEL (1<<6) +#define DA9052_STATUSA_DCINSEL (1<<5) +#define DA9052_STATUSA_VBUSDET (1<<4) +#define DA9052_STATUSA_DCINDET (1<<3) +#define DA9052_STATUSA_IDGND (1<<2) +#define DA9052_STATUSA_IDFLOAT (1<<1) +#define DA9052_STATUSA_NONKEY (1<<0) + + +/* STATUS REGISTER B */ +#define DA9052_STATUSB_COMPDET (1<<7) +#define DA9052_STATUSB_SEQUENCING (1<<6) +#define DA9052_STATUSB_GPFB2 (1<<5) +#define DA9052_STATUSB_CHGTO (1<<4) +#define DA9052_STATUSB_CHGEND (1<<3) +#define DA9052_STATUSB_CHGLIM (1<<2) +#define DA9052_STATUSB_CHGPRE (1<<1) +#define DA9052_STATUSB_CHGATT (1<<0) + + +/* STATUS REGISTER C */ +#define DA9052_STATUSC_GPI7 (1<<7) +#define DA9052_STATUSC_GPI6 (1<<6) +#define DA9052_STATUSC_GPI5 (1<<5) +#define DA9052_STATUSC_GPI4 (1<<4) +#define DA9052_STATUSC_GPI3 (1<<3) +#define DA9052_STATUSC_GPI2 (1<<2) +#define DA9052_STATUSC_GPI1 (1<<1) +#define DA9052_STATUSC_GPI0 (1<<0) + + +/* STATUS REGISTER D */ +#define DA9052_STATUSD_GPI15 (1<<7) +#define DA9052_STATUSD_GPI14 (1<<6) +#define DA9052_STATUSD_GPI13 (1<<5) +#define DA9052_STATUSD_GPI12 (1<<4) +#define DA9052_STATUSD_GPI11 (1<<3) +#define DA9052_STATUSD_GPI10 (1<<2) +#define DA9052_STATUSD_GPI9 (1<<1) +#define DA9052_STATUSD_GPI8 (1<<0) + + +/* EVENT REGISTER A */ +#define DA9052_EVENTA_ECOMP1V2 (1<<7) +#define DA9052_EVENTA_ESEQRDY (1<<6) +#define DA9052_EVENTA_EALRAM (1<<5) +#define DA9052_EVENTA_EVDDLOW (1<<4) +#define DA9052_EVENTA_EVBUSREM (1<<3) +#define DA9052_EVENTA_EDCINREM (1<<2) +#define DA9052_EVENTA_EVBUSDET (1<<1) +#define DA9052_EVENTA_EDCINDET (1<<0) + +/* EVENT REGISTER B */ +#define DA9052_EVENTB_ETSIREADY (1<<7) +#define DA9052_EVENTB_EPENDOWN (1<<6) +#define DA9052_EVENTB_EADCEOM (1<<5) +#define DA9052_EVENTB_ETBAT (1<<4) +#define DA9052_EVENTB_ECHGEND (1<<3) +#define DA9052_EVENTB_EIDGND (1<<2) +#define DA9052_EVENTB_EIDFLOAT (1<<1) +#define DA9052_EVENTB_ENONKEY (1<<0) + +/* EVENT REGISTER C */ +#define DA9052_EVENTC_EGPI7 (1<<7) +#define DA9052_EVENTC_EGPI6 (1<<6) +#define DA9052_EVENTC_EGPI5 (1<<5) +#define DA9052_EVENTC_EGPI4 (1<<4) +#define DA9052_EVENTC_EGPI3 (1<<3) +#define DA9052_EVENTC_EGPI2 (1<<2) +#define DA9052_EVENTC_EGPI1 (1<<1) +#define DA9052_EVENTC_EGPI0 (1<<0) + +/* EVENT REGISTER D */ +#define DA9052_EVENTC_EGPI15 (1<<7) +#define DA9052_EVENTC_EGPI14 (1<<6) +#define DA9052_EVENTC_EGPI13 (1<<5) +#define DA9052_EVENTC_EGPI12 (1<<4) +#define DA9052_EVENTC_EGPI11 (1<<3) +#define DA9052_EVENTC_EGPI10 (1<<2) +#define DA9052_EVENTC_EGPI9 (1<<1) +#define DA9052_EVENTC_EGPI8 (1<<0) + + +/* FAULT LOG REGISTER */ +#define DA9052_FAULTLOG_WAITSET (1<<7) +#define DA9052_FAULTLOG_NSDSET (1<<6) +#define DA9052_FAULTLOG_KEYSHUT (1<<5) +#define DA9052_FAULTLOG_TEMPOVER (1<<3) +#define DA9052_FAULTLOG_VDDSTART (1<<2) +#define DA9052_FAULTLOG_VDDFAULT (1<<1) +#define DA9052_FAULTLOG_TWDERROR (1<<0) + +/* IRQ_MASK REGISTER A */ +#define DA9052_IRQMASKA_MCOMP1V2 (1<<7) +#define DA9052_IRQMASKA_MSEQRDY (1<<6) +#define DA9052_IRQMASKA_MALRAM (1<<5) +#define DA9052_IRQMASKA_MVDDLOW (1<<4) +#define DA9052_IRQMASKA_MVBUSREM (1<<3) +#define DA9052_IRQMASKA_MDCINREM (1<<2) +#define DA9052_IRQMASKA_MVBUSVLD (1<<1) +#define DA9052_IRQMASKA_MDCINVLD (1<<0) + +/* IRQ_MASK REGISTER B */ +#define DA9052_IRQMASKB_MTSIREADY (1<<7) +#define DA9052_IRQMASKB_MPENDOWN (1<<6) +#define DA9052_IRQMASKB_MADCEOM (1<<5) +#define DA9052_IRQMASKB_MTBAT (1<<4) +#define DA9052_IRQMASKB_MCHGEND (1<<3) +#define DA9052_IRQMASKB_MIDGND (1<<2) +#define DA9052_IRQMASKB_MIDFLOAT (1<<1) +#define DA9052_IRQMASKB_MNONKEY (1<<0) + +/* IRQ_MASK REGISTER C */ +#define DA9052_IRQMASKC_MGPI7 (1<<7) +#define DA9052_IRQMASKC_MGPI6 (1<<6) +#define DA9052_IRQMASKC_MGPI5 (1<<5) +#define DA9052_IRQMASKC_MGPI4 (1<<4) +#define DA9052_IRQMASKC_MGPI3 (1<<3) +#define DA9052_IRQMASKC_MGPI2 (1<<2) +#define DA9052_IRQMASKC_MGPI1 (1<<1) +#define DA9052_IRQMASKC_MGPI0 (1<<0) + +/* IRQ_MASK REGISTER D */ +#define DA9052_IRQMASKD_MGPI15 (1<<7) +#define DA9052_IRQMASKD_MGPI14 (1<<6) +#define DA9052_IRQMASKD_MGPI13 (1<<5) +#define DA9052_IRQMASKD_MGPI12 (1<<4) +#define DA9052_IRQMASKD_MGPI11 (1<<3) +#define DA9052_IRQMASKD_MGPI10 (1<<2) +#define DA9052_IRQMASKD_MGPI9 (1<<1) +#define DA9052_IRQMASKD_MGPI8 (1<<0) + +/* CONTROL REGISTER A */ +#define DA9052_CONTROLA_GPIV (1<<7) +#define DA9052_CONTROLA_PMOTYPE (1<<5) +#define DA9052_CONTROLA_PMOV (1<<4) +#define DA9052_CONTROLA_PMIV (1<<3) +#define DA9052_CONTROLA_PMIFV (1<<3) +#define DA9052_CONTROLA_PWR1EN (1<<2) +#define DA9052_CONTROLA_PWREN (1<<1) +#define DA9052_CONTROLA_SYSEN (1<<0) + +/* CONTROL REGISTER B */ +#define DA9052_CONTROLB_SHUTDOWN (1<<7) +#define DA9052_CONTROLB_DEEPSLEEP (1<<6) +#define DA9052_CONTROLB_WRITEMODE (1<<5) +#define DA9052_CONTROLB_BBATEN (1<<4) +#define DA9052_CONTROLB_OTPREADEN (1<<3) +#define DA9052_CONTROLB_AUTOBOOT (1<<2) +#define DA9052_CONTROLB_ACTDIODE (1<<1) +#define DA9052_CONTROLB_BUCKMERGE (1<<0) + +/* CONTROL REGISTER C */ +#define DA9052_CONTROLC_BLINKDUR (1<<7) +#define DA9052_CONTROLC_BLINKFRQ (3<<5) +#define DA9052_CONTROLC_DEBOUNCING (7<<2) +#define DA9052_CONTROLC_PMFB2PIN (1<<1) +#define DA9052_CONTROLC_PMFB1PIN (1<<0) + +/* CONTROL REGISTER D */ +#define DA9052_CONTROLD_WATCHDOG (1<<7) +#define DA9052_CONTROLD_ACCDETEN (1<<6) +#define DA9052_CONTROLD_GPI1415SD (1<<5) +#define DA9052_CONTROLD_NONKEYSD (1<<4) +#define DA9052_CONTROLD_KEEPACTEN (1<<3) +#define DA9052_CONTROLD_TWDSCALE (7<<0) + +/* POWER DOWN DISABLE REGISTER */ +#define DA9052_PDDIS_PMCONTPD (1<<7) +#define DA9052_PDDIS_OUT32KPD (1<<6) +#define DA9052_PDDIS_CHGBBATPD (1<<5) +#define DA9052_PDDIS_CHGPD (1<<4) +#define DA9052_PDDIS_HS2WIREPD (1<<3) +#define DA9052_PDDIS_PMIFPD (1<<2) +#define DA9052_PDDIS_GPADCPD (1<<1) +#define DA9052_PDDIS_GPIOPD (1<<0) + +/* CONTROL REGISTER D */ +#define DA9052_INTERFACE_IFBASEADDR (7<<5) +#define DA9052_INTERFACE_NCSPOL (1<<4) +#define DA9052_INTERFACE_RWPOL (1<<3) +#define DA9052_INTERFACE_CPHA (1<<2) +#define DA9052_INTERFACE_CPOL (1<<1) +#define DA9052_INTERFACE_IFTYPE (1<<0) + +/* CONTROL REGISTER D */ +#define DA9052_RESET_RESETEVENT (3<<6) +#define DA9052_RESET_RESETTIMER (63<<0) + +/* GPIO REGISTERS */ + +/* GPIO control register for PIN 0 and 1 */ +#define DA9052_GPIO0001_GPIO1MODE (1<<7) +#define DA9052_GPIO0001_GPIO1TYPE (1<<6) +#define DA9052_GPIO0001_GPIO1PIN (3<<4) +#define DA9052_GPIO0001_GPIO0MODE (1<<3) +#define DA9052_GPIO0001_GPIO0TYPE (1<<2) +#define DA9052_GPIO0001_GPIO0PIN (3<<0) + +/* GPIO control register for PIN 2 and 3 */ +#define DA9052_GPIO0203_GPIO3MODE (1<<7) +#define DA9052_GPIO0203_GPIO3TYPE (1<<6) +#define DA9052_GPIO0203_GPIO3PIN (3<<4) +#define DA9052_GPIO0203_GPIO2MODE (1<<3) +#define DA9052_GPIO0203_GPIO2TYPE (1<<2) +#define DA9052_GPIO0203_GPIO2PIN (3<<0) + +/* GPIO control register for PIN 4 and 5 */ +#define DA9052_GPIO0405_GPIO5MODE (1<<7) +#define DA9052_GPIO0405_GPIO5TYPE (1<<6) +#define DA9052_GPIO0405_GPIO5PIN (3<<4) +#define DA9052_GPIO0405_GPIO4MODE (1<<3) +#define DA9052_GPIO0405_GPIO4TYPE (1<<2) +#define DA9052_GPIO0405_GPIO4PIN (3<<0) + +/* GPIO control register for PIN 6 and 7 */ +#define DA9052_GPIO0607_GPIO7MODE (1<<7) +#define DA9052_GPIO0607_GPIO7TYPE (1<<6) +#define DA9052_GPIO0607_GPIO7PIN (3<<4) +#define DA9052_GPIO0607_GPIO6MODE (1<<3) +#define DA9052_GPIO0607_GPIO6TYPE (1<<2) +#define DA9052_GPIO0607_GPIO6PIN (3<<0) + +/* GPIO control register for PIN 8 and 9 */ +#define DA9052_GPIO0809_GPIO9MODE (1<<7) +#define DA9052_GPIO0809_GPIO9TYPE (1<<6) +#define DA9052_GPIO0809_GPIO9PIN (3<<4) +#define DA9052_GPIO0809_GPIO8MODE (1<<3) +#define DA9052_GPIO0809_GPIO8TYPE (1<<2) +#define DA9052_GPIO0809_GPIO8PIN (3<<0) + +/* GPIO control register for PIN 10 and 11 */ +#define DA9052_GPIO1011_GPIO11MODE (1<<7) +#define DA9052_GPIO1011_GPIO11TYPE (1<<6) +#define DA9052_GPIO1011_GPIO11PIN (3<<4) +#define DA9052_GPIO1011_GPIO10MODE (1<<3) +#define DA9052_GPIO1011_GPIO10TYPE (1<<2) +#define DA9052_GPIO1011_GPIO10PIN (3<<0) + +/* GPIO control register for PIN 12 and 13 */ +#define DA9052_GPIO1213_GPIO13MODE (1<<7) +#define DA9052_GPIO1213_GPIO13TYPE (1<<6) +#define DA9052_GPIO1213_GPIO13PIN (3<<4) +#define DA9052_GPIO1213_GPIO12MODE (1<<3) +#define DA9052_GPIO1213_GPIO12TYPE (1<<2) +#define DA9052_GPIO1213_GPIO12PIN (3<<0) + +/* GPIO control register for PIN 14 and 15 */ +#define DA9052_GPIO1415_GPIO15MODE (1<<7) +#define DA9052_GPIO1415_GPIO15TYPE (1<<6) +#define DA9052_GPIO1415_GPIO15PIN (3<<4) +#define DA9052_GPIO1415_GPIO14MODE (1<<3) +#define DA9052_GPIO1415_GPIO14TYPE (1<<2) +#define DA9052_GPIO1415_GPIO14PIN (3<<0) + +/*POWER SEQUENCER REGISTER*/ + +/* SEQ control register for ID 0 and 1 */ +#define DA9052_ID01_LDO1STEP (15<<4) +#define DA9052_ID01_SYSPRE (1<<2) +#define DA9052_ID01_DEFSUPPLY (1<<1) +#define DA9052_ID01_nRESMODE (1<<0) + +/* SEQ control register for ID 2 and 3 */ +#define DA9052_ID23_LDO3STEP (15<<4) +#define DA9052_ID23_LDO2STEP (15<<0) + +/* SEQ control register for ID 4 and 5 */ +#define DA9052_ID45_LDO5STEP (15<<4) +#define DA9052_ID45_LDO4STEP (15<<0) + +/* SEQ control register for ID 6 and 7 */ +#define DA9052_ID67_LDO7STEP (15<<4) +#define DA9052_ID67_LDO6STEP (15<<0) + +/* SEQ control register for ID 8 and 9 */ +#define DA9052_ID89_LDO9STEP (15<<4) +#define DA9052_ID89_LDO8STEP (15<<0) + +/* SEQ control register for ID 10 and 11 */ +#define DA9052_ID1011_PDDISSTEP (15<<4) +#define DA9052_ID1011_LDO10STEP (15<<0) + +/* SEQ control register for ID 12 and 13 */ +#define DA9052_ID1213_VMEMSWSTEP (15<<4) +#define DA9052_ID1213_VPERISWSTEP (15<<0) + +/* SEQ control register for ID 14 and 15 */ +#define DA9052_ID1415_BUCKPROSTEP (15<<4) +#define DA9052_ID1415_BUCKCORESTEP (15<<0) + +/* SEQ control register for ID 16 and 17 */ +#define DA9052_ID1617_BUCKPERISTEP (15<<4) +#define DA9052_ID1617_BUCKMEMSTEP (15<<0) + +/* SEQ control register for ID 18 and 19 */ +#define DA9052_ID1819_GPRISE2STEP (15<<4) +#define DA9052_ID1819_GPRISE1STEP (15<<0) + +/* SEQ control register for ID 20 and 21 */ +#define DA9052_ID2021_GPFALL2STEP (15<<4) +#define DA9052_ID2021_GPFALL1STEP (15<<0) + +/* Power SEQ Status register */ +#define DA9052_SEQSTATUS_SEQPOINTER (15<<4) +#define DA9052_SEQSTATUS_WAITSTEP (15<<0) + +/* Power SEQ A register */ +#define DA9052_SEQA_POWEREND (15<<4) +#define DA9052_SEQA_SYSTEMEND (15<<0) + +/* Power SEQ B register */ +#define DA9052_SEQB_PARTDOWN (15<<4) +#define DA9052_SEQB_MAXCOUNT (15<<0) + +/* Power SEQ TIMER register */ +#define DA9052_SEQTIMER_SEQDUMMY (15<<4) +#define DA9052_SEQTIMER_SEQTIME (15<<0) + +/*POWER SUPPLY CONTROL REGISTER*/ + +/* BUCK REGISTER A */ +#define DA9052_BUCKA_BPROILIM (3<<6) +#define DA9052_BUCKA_BPROMODE (3<<4) +#define DA9052_BUCKA_BCOREILIM (3<<2) +#define DA9052_BUCKA_BCOREMODE (3<<0) + +/* BUCK REGISTER B */ +#define DA9052_BUCKB_BERIILIM (3<<6) +#define DA9052_BUCKB_BPERIMODE (3<<4) +#define DA9052_BUCKB_BMEMILIM (3<<2) +#define DA9052_BUCKB_BMEMMODE (3<<0) + +/* BUCKCORE REGISTER */ +#define DA9052_BUCKCORE_BCORECONF (1<<7) +#define DA9052_BUCKCORE_BCOREEN (1<<6) +#define DA9052_BUCKCORE_VBCORE (63<<0) + +/* BUCKPRO REGISTER */ +#define DA9052_BUCKPRO_BPROCONF (1<<7) +#define DA9052_BUCKPRO_BPROEN (1<<6) +#define DA9052_BUCKPRO_VBPRO (63<<0) + +/* BUCKMEM REGISTER */ +#define DA9052_BUCKMEM_BMEMCONF (1<<7) +#define DA9052_BUCKMEM_BMEMEN (1<<6) +#define DA9052_BUCKMEM_VBMEM (63<<0) + +/* BUCKPERI REGISTER */ +#define DA9052_BUCKPERI_BPERICONF (1<<7) +#define DA9052_BUCKPERI_BPERIEN (1<<6) +#define DA9052_BUCKPERI_BPERIHS (1<<5) +#define DA9052_BUCKPERI_VBPERI (31<<0) + +/* LDO1 REGISTER */ +#define DA9052_LDO1_LDO1CONF (1<<7) +#define DA9052_LDO1_LDO1EN (1<<6) +#define DA9052_LDO1_VLDO1 (31<<0) + +/* LDO2 REGISTER */ +#define DA9052_LDO2_LDO2CONF (1<<7) +#define DA9052_LDO2_LDO2EN (1<<6) +#define DA9052_LDO2_VLDO2 (63<<0) + +/* LDO3 REGISTER */ +#define DA9052_LDO3_LDO3CONF (1<<7) +#define DA9052_LDO3_LDO3EN (1<<6) +#define DA9052_LDO3_VLDO3 (63<<0) + +/* LDO4 REGISTER */ +#define DA9052_LDO4_LDO4CONF (1<<7) +#define DA9052_LDO4_LDO4EN (1<<6) +#define DA9052_LDO4_VLDO4 (63<<0) + +/* LDO5 REGISTER */ +#define DA9052_LDO5_LDO5CONF (1<<7) +#define DA9052_LDO5_LDO5EN (1<<6) +#define DA9052_LDO5_VLDO5 (63<<0) + +/* LDO6 REGISTER */ +#define DA9052_LDO6_LDO6CONF (1<<7) +#define DA9052_LDO6_LDO6EN (1<<6) +#define DA9052_LDO6_VLDO6 (63<<0) + +/* LDO7 REGISTER */ +#define DA9052_LDO7_LDO7CONF (1<<7) +#define DA9052_LDO7_LDO7EN (1<<6) +#define DA9052_LDO7_VLDO7 (63<<0) + +/* LDO8 REGISTER */ +#define DA9052_LDO8_LDO8CONF (1<<7) +#define DA9052_LDO8_LDO8EN (1<<6) +#define DA9052_LDO8_VLDO8 (63<<0) + +/* LDO9 REGISTER */ +#define DA9052_LDO9_LDO9CONF (1<<7) +#define DA9052_LDO9_LDO9EN (1<<6) +#define DA9052_LDO9_VLDO9 (63<<0) + +/* LDO10 REGISTER */ +#define DA9052_LDO10_LDO10CONF (1<<7) +#define DA9052_LDO10_LDO10EN (1<<6) +#define DA9052_LDO10_VLDO10 (63<<0) + +/* SUPPLY REGISTER */ +#define DA9052_SUPPLY_VLOCK (1<<7) +#define DA9052_SUPPLY_VMEMSWEN (1<<6) +#define DA9052_SUPPLY_VPERISWEN (1<<5) +#define DA9052_SUPPLY_VLDO3GO (1<<4) +#define DA9052_SUPPLY_VLDO2GO (1<<3) +#define DA9052_SUPPLY_VBMEMGO (1<<2) +#define DA9052_SUPPLY_VBPROGO (1<<1) +#define DA9052_SUPPLY_VBCOREGO (1<<0) + +/* PULLDOWN REGISTER */ +#define DA9052_PULLDOWN_LDO5PDDIS (1<<5) +#define DA9052_PULLDOWN_LDO2PDDIS (1<<4) +#define DA9052_PULLDOWN_LDO1PDDIS (1<<3) +#define DA9052_PULLDOWN_MEMPDDIS (1<<2) +#define DA9052_PULLDOWN_PROPDDIS (1<<1) +#define DA9052_PULLDOWN_COREPDDIS (1<<0) + +/* BAT CHARGER REGISTER */ + +/* CHARGER BUCK REGISTER */ +#define DA9052_CHGBUCK_CHGTEMP (1<<7) +#define DA9052_CHGBUCK_CHGUSBILIM (1<<6) +#define DA9052_CHGBUCK_CHGBUCKLP (1<<5) +#define DA9052_CHGBUCK_CHGBUCKEN (1<<4) +#define DA9052_CHGBUCK_ISETBUCK (15<<0) + +/* WAIT COUNTER REGISTER */ +#define DA9052_WAITCONT_WAITDIR (1<<7) +#define DA9052_WAITCONT_RTCCLOCK (1<<6) +#define DA9052_WAITCONT_WAITMODE (1<<5) +#define DA9052_WAITCONT_EN32KOUT (1<<4) +#define DA9052_WAITCONT_DELAYTIME (15<<0) + +/* ISET CONTROL REGISTER */ +#define DA9052_ISET_ISETDCIN (15<<4) +#define DA9052_ISET_ISETVBUS (15<<0) + +/* BATTERY CHARGER CONTROL REGISTER */ +#define DA9052_BATCHG_ICHGPRE (3<<6) +#define DA9052_BATCHG_ICHGBAT (63<<0) + +/* CHARGER COUNTER REGISTER */ +#define DA9052_CHGCONT_VCHGBAT (31<<3) +#define DA9052_CHGCONT_TCTR (7<<0) + +/* INPUT CONTROL REGISTER */ +#define DA9052_INPUTCONT_TCTRMODE (1<<7) +#define DA9052_INPUTCONT_ICHGLOW (1<<5) +#define DA9052_INPUTCONT_VBUSSUSP (1<<4) +#define DA9052_INPUTCONT_DCINSUSP (1<<3) +#define DA9052_INPUTCONT_VCHGTHR (7<<0) + +/* CHARGING TIME REGISTER */ +#define DA9052_CHGTIME_CHGTIME (255<<0) + +/* BACKUP BATTERY CONTROL REGISTER */ +#define DA9052_BBATCONT_BCHARGERISET (15<<4) +#define DA9052_BBATCONT_BCHARGERVSET (15<<0) + +/* LED REGISTERS */ + +/* LED BOOST REGISTER */ +#define DA9052_BOOST_EBFAULT (1<<7) +#define DA9052_BOOST_MBFAULT (1<<6) +#define DA9052_BOOST_BOOSTFRQ (1<<5) +#define DA9052_BOOST_BOOSTILIM (1<<4) +#define DA9052_BOOST_LED3INEN (1<<3) +#define DA9052_BOOST_LED2INEN (1<<2) +#define DA9052_BOOST_LED1INEN (1<<1) +#define DA9052_BOOST_BOOSTEN (1<<0) + +/* LED COUNT REGISTER */ +#define DA9052_LEDCONT_LED3ICONT (1<<6) +#define DA9052_LEDCONT_LED3RAMP (1<<5) +#define DA9052_LEDCONT_LED3EN (1<<4) +#define DA9052_LEDCONT_LED2RAMP (1<<3) +#define DA9052_LEDCONT_LED2EN (1<<2) +#define DA9052_LEDCONT_LED1RAMP (1<<1) +#define DA9052_LEDCONT_LED1EN (1<<0) + +/* LEDMIN123 REGISTER */ +#define DA9052_LEDMIN123_LEDMINCURRENT (255<<0) + +/* LED1CONF REGISTER */ +#define DA9052_LED1CONF_LED1CURRENT (255<<0) + +/* LED2CONF REGISTER */ +#define DA9052_LED2CONF_LED2CURRENT (255<<0) + +/* LED3CONF REGISTER */ +#define DA9052_LED3CONF_LED3CURRENT (255<<0) + +/* LED1 COUNT REGISTER */ +#define DA9052_LED1CONT_LED1DIM (1<<7) +#define DA9052_LED1CONT_LED1PWM (127<<0) + +/* LED2 COUNT REGISTER */ +#define DA9052_LED2CONT_LED2DIM (1<<7) +#define DA9052_LED2CONT_LED2PWM (127<<0) + +/* LED3 COUNT REGISTER */ +#define DA9052_LED3CONT_LED3DIM (1<<7) +#define DA9052_LED3CONT_LED3PWM (127<<0) + +/* LED4 COUNT REGISTER */ +#define DA9052_LED4CONT_LED4DIM (1<<7) +#define DA9052_LED4CONT_LED4PWM (127<<0) + +/* LED5 COUNT REGISTER */ +#define DA9052_LED5CONT_LED5DIM (1<<7) +#define DA9052_LED5CONT_LED5PWM (127<<0) + +/* ADC REGISTERS */ + +/* ADC MAN registers */ +#define DA9052_ADCMAN_MANCONV (1<<4) +#define DA9052_ADCMAN_MUXSEL (15<<0) + +/* ADC COUNT regsisters */ +#define DA9052_ADCCONT_COMP1V2EN (1<<7) +#define DA9052_ADCCONT_ADCMODE (1<<6) +#define DA9052_ADCCONT_TBATISRCEN (1<<5) +#define DA9052_ADCCONT_AD4ISRCEN (1<<4) +#define DA9052_ADCCONT_AUTOAD6EN (1<<3) +#define DA9052_ADCCONT_AUTOAD5EN (1<<2) +#define DA9052_ADCCONT_AUTOAD4EN (1<<1) +#define DA9052_ADCCONT_AUTOVDDEN (1<<0) + +/* ADC 10 BIT MANUAL CONVERSION RESULT LOW register */ +#define DA9052_ADCRESL_ADCRESLSB (3<<0) + +/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH register */ +#define DA9052_ADCRESH_ADCRESMSB (255<<0) + +/* VDD RES regsister*/ +#define DA9052_VDDRES_VDDOUTRES (255<<0) + +/* VDD MON regsister*/ +#define DA9052_VDDMON_VDDOUTMON (255<<0) + +/* ICHG_AV regsister*/ +#define DA9052_ICHGAV_ICHGAV (255<<0) + +/* ICHG_THD regsister*/ +#define DA9052_ICHGTHD_ICHGTHD (255<<0) + +/* ICHG_END regsister*/ +#define DA9052_ICHGEND_ICHGEND (255<<0) + +/* TBAT_RES regsister*/ +#define DA9052_TBATRES_TBATRES (255<<0) + +/* TBAT_HIGHP regsister*/ +#define DA9052_TBATHIGHP_TBATHIGHP (255<<0) + +/* TBAT_HIGHN regsister*/ +#define DA9052_TBATHIGHN_TBATHIGHN (255<<0) + +/* TBAT_LOW regsister*/ +#define DA9052_TBATLOW_TBATLOW (255<<0) + +/* T_OFFSET regsister*/ +#define DA9052_TOFFSET_TOFFSET (255<<0) + +/* ADCIN4_RES regsister*/ +#define DA9052_ADCIN4RES_ADCIN4RES (255<<0) + +/* ADCIN4_HIGH regsister*/ +#define DA9052_AUTO4HIGH_AUTO4HIGH (255<<0) + +/* ADCIN4_LOW regsister*/ +#define DA9052_AUTO4LOW_AUTO4LOW (255<<0) + +/* ADCIN5_RES regsister*/ +#define DA9052_ADCIN5RES_ADCIN5RES (255<<0) + +/* ADCIN5_HIGH regsister*/ +#define DA9052_AUTO5HIGH_AUTOHIGH (255<<0) + +/* ADCIN5_LOW regsister*/ +#define DA9052_AUTO5LOW_AUTO5LOW (255<<0) + +/* ADCIN6_RES regsister*/ +#define DA9052_ADCIN6RES_ADCIN6RES (255<<0) + +/* ADCIN6_HIGH regsister*/ +#define DA9052_AUTO6HIGH_AUTO6HIGH (255<<0) + +/* ADCIN6_LOW regsister*/ +#define DA9052_AUTO6LOW_AUTO6LOW (255<<0) + +/* TJUNC_RES regsister*/ +#define DA9052_TJUNCRES_TJUNCRES (255<<0) + +/* TSI REGISTER */ + +/* TSI Control Register A */ +#define DA9052_TSICONTA_TSIDELAY (3<<6) +#define DA9052_TSICONTA_TSISKIP (7<<3) +#define DA9052_TSICONTA_TSIMODE (1<<2) +#define DA9052_TSICONTA_PENDETEN (1<<1) +#define DA9052_TSICONTA_AUTOTSIEN (1<<0) + +/* TSI Control Register B */ +#define DA9052_TSICONTB_ADCREF (1<<7) +#define DA9052_TSICONTB_TSIMAN (1<<6) +#define DA9052_TSICONTB_TSIMUX (3<<4) +#define DA9052_TSICONTB_TSISEL3 (1<<3) +#define DA9052_TSICONTB_TSISEL2 (1<<2) +#define DA9052_TSICONTB_TSISEL1 (1<<1) +#define DA9052_TSICONTB_TSISEL0 (1<<0) + +/* TSI X Co-ordinate MSB Result register */ +#define DA9052_TSIXMSB_TSIXM (255<<0) + +/* TSI Y Co-ordinate MSB Result register */ +#define DA9052_TSIYMSB_TSIYM (255<<0) + +/* TSI Co-ordinate LSB Result register */ +#define DA9052_TSILSB_PENDOWN (1<<6) +#define DA9052_TSILSB_TSIZL (3<<4) +#define DA9052_TSILSB_TSIYL (3<<2) +#define DA9052_TSILSB_TSIXL (3<<0) + +/* TSI Z Measurement MSB Result register */ +#define DA9052_TSIZMSB_TSIZM (255<<0) + +/* RTC REGISTER */ + +/* RTC TIMER SECONDS REGISTER */ +#define DA9052_COUNTS_MONITOR (1<<6) +#define DA9052_COUNTS_COUNTSEC (63<<0) + +/* RTC TIMER MINUTES REGISTER */ +#define DA9052_COUNTMI_COUNTMIN (63<<0) + +/* RTC TIMER HOUR REGISTER */ +#define DA9052_COUNTH_COUNTHOUR (31<<0) + +/* RTC TIMER DAYS REGISTER */ +#define DA9052_COUNTD_COUNTDAY (31<<0) + +/* RTC TIMER MONTHS REGISTER */ +#define DA9052_COUNTMO_COUNTMONTH (15<<0) + +/* RTC TIMER YEARS REGISTER */ +#define DA9052_COUNTY_COUNTYEAR (63<<0) + +/* RTC ALARM MINUTES REGISTER */ +#define DA9052_ALARMMI_TICKTYPE (1<<7) +#define DA9052_ALARMMI_ALARMTYPE (1<<6) +#define DA9052_ALARMMI_ALARMMIN (63<<0) + +/* RTC ALARM HOURS REGISTER */ +#define DA9052_ALARMH_ALARMHOUR (31<<0) + +/* RTC ALARM DAYS REGISTER */ +#define DA9052_ALARMD_ALARMDAY (31<<0) + +/* RTC ALARM MONTHS REGISTER */ +#define DA9052_ALARMMO_ALARMMONTH (15<<0) + +/* RTC ALARM YEARS REGISTER */ +#define DA9052_ALARMY_TICKON (1<<7) +#define DA9052_ALARMY_ALARMON (1<<6) +#define DA9052_ALARMY_ALARMYEAR (63<<0) + +/* RTC SECONDS REGISTER A*/ +#define DA9052_SECONDA_SECONDSA (255<<0) + +/* RTC SECONDS REGISTER B*/ +#define DA9052_SECONDB_SECONDSB (255<<0) + +/* RTC SECONDS REGISTER C*/ +#define DA9052_SECONDC_SECONDSC (255<<0) + +/* RTC SECONDS REGISTER D*/ +#define DA9052_SECONDD_SECONDSD (255<<0) + +/* OTP REGISTER */ + +/* CHIP IDENTIFICATION REGISTER */ +#define DA9052_CHIPID_MRC (15<<4) +#define DA9052_CHIPID_TRC (15<<0) + +/* CONFIGURATION IDENTIFICATION REGISTER */ +#define DA9052_CONFIGID_CUSTOMERID (31<<3) +#define DA9052_CONFIGID_CONFID (7<<0) + +/* OTP CONTROL REGISTER */ +#define DA9052_OTPCONT_GPWRITEDIS (1<<7) +#define DA9052_OTPCONT_OTPCONFLOCK (1<<6) +#define DA9052_OTPCONT_OTPGPLOCK (1<<5) +#define DA9052_OTPCONT_OTPCONFG (1<<3) +#define DA9052_OTPCONT_OTPGP (1<<2) +#define DA9052_OTPCONT_OTPRP (1<<1) +#define DA9052_OTPCONT_OTPTRANSFER (1<<0) + +/* RTC OSCILLATOR TRIM REGISTER */ +#define DA9052_OSCTRIM_TRIM32K (255<<0) + +/* GP ID REGISTER 0 */ +#define DA9052_GPID0_GP0 (255<<0) + +/* GP ID REGISTER 1 */ +#define DA9052_GPID1_GP1 (255<<0) + +/* GP ID REGISTER 2 */ +#define DA9052_GPID2_GP2 (255<<0) + +/* GP ID REGISTER 3 */ +#define DA9052_GPID3_GP3 (255<<0) + +/* GP ID REGISTER 4 */ +#define DA9052_GPID4_GP4 (255<<0) + +/* GP ID REGISTER 5 */ +#define DA9052_GPID5_GP5 (255<<0) + +/* GP ID REGISTER 6 */ +#define DA9052_GPID6_GP6 (255<<0) + +/* GP ID REGISTER 7 */ +#define DA9052_GPID7_GP7 (255<<0) + +/* GP ID REGISTER 8 */ +#define DA9052_GPID8_GP8 (255<<0) + +/* GP ID REGISTER 9 */ +#define DA9052_GPID9_GP9 (255<<0) + +#endif +/* __LINUX_MFD_DA9052_REG_H */ diff --git a/include/linux/mfd/da9052/rtc.h b/include/linux/mfd/da9052/rtc.h new file mode 100644 index 000000000000..c7fc87dd7eb2 --- /dev/null +++ b/include/linux/mfd/da9052/rtc.h @@ -0,0 +1,322 @@ +/* + * da9052 RTC module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_RTC_H +#define __LINUX_MFD_DA9052_RTC_H + +#define DA9052_RTC_DEVICE_NAME "da9052_rtc" + +/* Limit values */ +#define DA9052_RTC_SECONDS_LIMIT 59 +#define DA9052_RTC_MINUTES_LIMIT 59 +#define DA9052_RTC_HOURS_LIMIT 23 +#define DA9052_RTC_DAYS_LIMIT 31 +#define DA9052_RTC_MONTHS_LIMIT 12 +#define DA9052_RTC_YEARS_LIMIT 63 + +/* Months */ +#define FEBRUARY 2 +#define APRIL 4 +#define JUNE 6 +#define SEPTEMBER 9 +#define NOVEMBER 11 + +/* BYTE shifts */ +#define DA9052_RTC_FOURTH_BYTE 24 +#define DA9052_RTC_THIRD_BYTE 16 +#define DA9052_RTC_SECOND_BYTE 8 +#define DA9052_RTC_FIRST_BYTE 0 + +/* Oscillator trim values */ +#define DA9052_RTC_OSC_FRQ_0_0ppm 0 +#define DA9052_RTC_OSC_FRQ_1_9ppm 1 +#define DA9052_RTC_OSC_FRQ_3_8ppm 2 +#define DA9052_RTC_OSC_FRQ_5_7ppm 3 +#define DA9052_RTC_OSC_FRQ_7_6ppm 4 +#define DA9052_RTC_OSC_FRQ_9_5ppm 5 +#define DA9052_RTC_OSC_FRQ_11_4ppm 6 +#define DA9052_RTC_OSC_FRQ_13_3ppm 7 +#define DA9052_RTC_OSC_FRQ_15_2ppm 8 +#define DA9052_RTC_OSC_FRQ_17_1ppm 9 +#define DA9052_RTC_OSC_FRQ_19_0ppm 10 +#define DA9052_RTC_OSC_FRQ_20_9ppm 11 +#define DA9052_RTC_OSC_FRQ_22_8ppm 12 +#define DA9052_RTC_OSC_FRQ_24_7ppm 13 +#define DA9052_RTC_OSC_FRQ_26_7ppm 14 +#define DA9052_RTC_OSC_FRQ_28_6ppm 15 +#define DA9052_RTC_OSC_FRQ_30_5ppm 16 +#define DA9052_RTC_OSC_FRQ_32_4ppm 17 +#define DA9052_RTC_OSC_FRQ_34_3ppm 18 +#define DA9052_RTC_OSC_FRQ_36_2ppm 19 +#define DA9052_RTC_OSC_FRQ_38_1ppm 20 +#define DA9052_RTC_OSC_FRQ_40_0ppm 21 +#define DA9052_RTC_OSC_FRQ_41_9ppm 22 +#define DA9052_RTC_OSC_FRQ_43_8ppm 23 +#define DA9052_RTC_OSC_FRQ_45_7ppm 24 +#define DA9052_RTC_OSC_FRQ_47_6ppm 25 +#define DA9052_RTC_OSC_FRQ_49_5ppm 26 +#define DA9052_RTC_OSC_FRQ_51_4ppm 27 +#define DA9052_RTC_OSC_FRQ_53_4ppm 28 +#define DA9052_RTC_OSC_FRQ_55_3ppm 29 +#define DA9052_RTC_OSC_FRQ_57_2ppm 30 +#define DA9052_RTC_OSC_FRQ_59_1ppm 31 +#define DA9052_RTC_OSC_FRQ_61_0ppm 32 +#define DA9052_RTC_OSC_FRQ_62_9ppm 33 +#define DA9052_RTC_OSC_FRQ_64_8ppm 34 +#define DA9052_RTC_OSC_FRQ_66_7ppm 35 +#define DA9052_RTC_OSC_FRQ_68_6ppm 36 +#define DA9052_RTC_OSC_FRQ_70_5ppm 37 +#define DA9052_RTC_OSC_FRQ_72_4ppm 38 +#define DA9052_RTC_OSC_FRQ_74_3ppm 39 +#define DA9052_RTC_OSC_FRQ_76_2ppm 40 +#define DA9052_RTC_OSC_FRQ_78_2ppm 41 +#define DA9052_RTC_OSC_FRQ_80_1ppm 42 +#define DA9052_RTC_OSC_FRQ_82_0ppm 43 +#define DA9052_RTC_OSC_FRQ_83_9ppm 44 +#define DA9052_RTC_OSC_FRQ_85_8ppm 45 +#define DA9052_RTC_OSC_FRQ_87_7ppm 46 +#define DA9052_RTC_OSC_FRQ_89_6ppm 47 +#define DA9052_RTC_OSC_FRQ_91_5ppm 48 +#define DA9052_RTC_OSC_FRQ_93_4ppm 49 +#define DA9052_RTC_OSC_FRQ_95_3ppm 50 +#define DA9052_RTC_OSC_FRQ_97_2ppm 51 +#define DA9052_RTC_OSC_FRQ_99_1ppm 52 +#define DA9052_RTC_OSC_FRQ_101_0ppm 53 +#define DA9052_RTC_OSC_FRQ_102_9ppm 54 +#define DA9052_RTC_OSC_FRQ_104_9ppm 55 +#define DA9052_RTC_OSC_FRQ_106_8ppm 56 +#define DA9052_RTC_OSC_FRQ_108_7ppm 57 +#define DA9052_RTC_OSC_FRQ_110_6ppm 58 +#define DA9052_RTC_OSC_FRQ_112_5ppm 59 +#define DA9052_RTC_OSC_FRQ_114_4ppm 60 +#define DA9052_RTC_OSC_FRQ_116_3ppm 61 +#define DA9052_RTC_OSC_FRQ_118_2ppm 62 +#define DA9052_RTC_OSC_FRQ_120_1ppm 63 +#define DA9052_RTC_OSC_FRQ_122_0ppm 64 +#define DA9052_RTC_OSC_FRQ_123_9ppm 65 +#define DA9052_RTC_OSC_FRQ_125_8ppm 66 +#define DA9052_RTC_OSC_FRQ_127_7ppm 67 +#define DA9052_RTC_OSC_FRQ_129_6ppm 68 +#define DA9052_RTC_OSC_FRQ_131_6ppm 69 +#define DA9052_RTC_OSC_FRQ_133_5ppm 70 +#define DA9052_RTC_OSC_FRQ_135_4ppm 71 +#define DA9052_RTC_OSC_FRQ_137_3ppm 72 +#define DA9052_RTC_OSC_FRQ_139_2ppm 73 +#define DA9052_RTC_OSC_FRQ_141_1ppm 74 +#define DA9052_RTC_OSC_FRQ_143_0ppm 75 +#define DA9052_RTC_OSC_FRQ_144_9ppm 76 +#define DA9052_RTC_OSC_FRQ_146_8ppm 77 +#define DA9052_RTC_OSC_FRQ_148_7ppm 78 +#define DA9052_RTC_OSC_FRQ_150_6ppm 79 +#define DA9052_RTC_OSC_FRQ_152_5ppm 80 +#define DA9052_RTC_OSC_FRQ_154_4ppm 81 +#define DA9052_RTC_OSC_FRQ_156_4ppm 82 +#define DA9052_RTC_OSC_FRQ_158_3ppm 83 +#define DA9052_RTC_OSC_FRQ_160_2ppm 84 +#define DA9052_RTC_OSC_FRQ_162_1ppm 85 +#define DA9052_RTC_OSC_FRQ_164_0ppm 86 +#define DA9052_RTC_OSC_FRQ_165_9ppm 87 +#define DA9052_RTC_OSC_FRQ_167_8ppm 88 +#define DA9052_RTC_OSC_FRQ_169_7ppm 89 +#define DA9052_RTC_OSC_FRQ_171_6ppm 90 +#define DA9052_RTC_OSC_FRQ_173_5ppm 91 +#define DA9052_RTC_OSC_FRQ_175_4ppm 92 +#define DA9052_RTC_OSC_FRQ_177_3ppm 93 +#define DA9052_RTC_OSC_FRQ_179_2ppm 94 +#define DA9052_RTC_OSC_FRQ_181_1ppm 95 +#define DA9052_RTC_OSC_FRQ_183_1ppm 96 +#define DA9052_RTC_OSC_FRQ_185_0ppm 97 +#define DA9052_RTC_OSC_FRQ_186_9ppm 98 +#define DA9052_RTC_OSC_FRQ_188_8ppm 99 +#define DA9052_RTC_OSC_FRQ_190_7ppm 100 +#define DA9052_RTC_OSC_FRQ_192_6ppm 101 +#define DA9052_RTC_OSC_FRQ_194_5ppm 102 +#define DA9052_RTC_OSC_FRQ_196_4ppm 103 +#define DA9052_RTC_OSC_FRQ_198_3ppm 104 +#define DA9052_RTC_OSC_FRQ_200_2ppm 105 +#define DA9052_RTC_OSC_FRQ_202_1ppm 106 +#define DA9052_RTC_OSC_FRQ_204_0ppm 107 +#define DA9052_RTC_OSC_FRQ_205_9ppm 108 +#define DA9052_RTC_OSC_FRQ_207_9ppm 109 +#define DA9052_RTC_OSC_FRQ_209_8ppm 110 +#define DA9052_RTC_OSC_FRQ_211_7ppm 111 +#define DA9052_RTC_OSC_FRQ_213_6ppm 112 +#define DA9052_RTC_OSC_FRQ_215_5ppm 113 +#define DA9052_RTC_OSC_FRQ_217_4ppm 114 +#define DA9052_RTC_OSC_FRQ_219_3ppm 115 +#define DA9052_RTC_OSC_FRQ_221_2ppm 116 +#define DA9052_RTC_OSC_FRQ_223_1ppm 117 +#define DA9052_RTC_OSC_FRQ_225_0ppm 118 +#define DA9052_RTC_OSC_FRQ_226_9ppm 119 +#define DA9052_RTC_OSC_FRQ_228_8ppm 120 +#define DA9052_RTC_OSC_FRQ_230_7ppm 121 +#define DA9052_RTC_OSC_FRQ_232_6ppm 122 +#define DA9052_RTC_OSC_FRQ_234_6ppm 123 +#define DA9052_RTC_OSC_FRQ_236_5ppm 124 +#define DA9052_RTC_OSC_FRQ_238_4ppm 125 +#define DA9052_RTC_OSC_FRQ_240_3ppm 126 +#define DA9052_RTC_OSC_FRQ_242_2ppm 127 +#define DA9052_RTC_OSC_FRQ_MINUS_244_1ppm 128 +#define DA9052_RTC_OSC_FRQ_MINUS_242_2ppm 129 +#define DA9052_RTC_OSC_FRQ_MINUS_240_3ppm 130 +#define DA9052_RTC_OSC_FRQ_MINUS_238_4ppm 131 +#define DA9052_RTC_OSC_FRQ_MINUS_236_5ppm 132 +#define DA9052_RTC_OSC_FRQ_MINUS_234_6ppm 133 +#define DA9052_RTC_OSC_FRQ_MINUS_232_6ppm 134 +#define DA9052_RTC_OSC_FRQ_MINUS_230_7ppm 135 +#define DA9052_RTC_OSC_FRQ_MINUS_228_8ppm 136 +#define DA9052_RTC_OSC_FRQ_MINUS_226_9ppm 137 +#define DA9052_RTC_OSC_FRQ_MINUS_225_0ppm 138 +#define DA9052_RTC_OSC_FRQ_MINUS_223_1ppm 139 +#define DA9052_RTC_OSC_FRQ_MINUS_221_2ppm 140 +#define DA9052_RTC_OSC_FRQ_MINUS_219_3ppm 141 +#define DA9052_RTC_OSC_FRQ_MINUS_217_4ppm 142 +#define DA9052_RTC_OSC_FRQ_MINUS_215_5ppm 143 +#define DA9052_RTC_OSC_FRQ_MINUS_213_6ppm 144 +#define DA9052_RTC_OSC_FRQ_MINUS_211_7ppm 145 +#define DA9052_RTC_OSC_FRQ_MINUS_209_8ppm 146 +#define DA9052_RTC_OSC_FRQ_MINUS_207_9ppm 147 +#define DA9052_RTC_OSC_FRQ_MINUS_205_9ppm 148 +#define DA9052_RTC_OSC_FRQ_MINUS_204_0ppm 149 +#define DA9052_RTC_OSC_FRQ_MINUS_202_1ppm 150 +#define DA9052_RTC_OSC_FRQ_MINUS_200_2ppm 151 +#define DA9052_RTC_OSC_FRQ_MINUS_198_3ppm 152 +#define DA9052_RTC_OSC_FRQ_MINUS_196_4ppm 153 +#define DA9052_RTC_OSC_FRQ_MINUS_194_5ppm 154 +#define DA9052_RTC_OSC_FRQ_MINUS_192_6ppm 155 +#define DA9052_RTC_OSC_FRQ_MINUS_190_7ppm 156 +#define DA9052_RTC_OSC_FRQ_MINUS_188_8ppm 157 +#define DA9052_RTC_OSC_FRQ_MINUS_186_9ppm 158 +#define DA9052_RTC_OSC_FRQ_MINUS_185_0ppm 159 +#define DA9052_RTC_OSC_FRQ_MINUS_183_1ppm 160 +#define DA9052_RTC_OSC_FRQ_MINUS_181_1ppm 161 +#define DA9052_RTC_OSC_FRQ_MINUS_179_2ppm 162 +#define DA9052_RTC_OSC_FRQ_MINUS_177_3ppm 163 +#define DA9052_RTC_OSC_FRQ_MINUS_175_4ppm 164 +#define DA9052_RTC_OSC_FRQ_MINUS_173_5ppm 165 +#define DA9052_RTC_OSC_FRQ_MINUS_171_6ppm 166 +#define DA9052_RTC_OSC_FRQ_MINUS_169_7ppm 167 +#define DA9052_RTC_OSC_FRQ_MINUS_167_8ppm 168 +#define DA9052_RTC_OSC_FRQ_MINUS_165_9ppm 169 +#define DA9052_RTC_OSC_FRQ_MINUS_164_0ppm 170 +#define DA9052_RTC_OSC_FRQ_MINUS_162_1ppm 171 +#define DA9052_RTC_OSC_FRQ_MINUS_160_2ppm 172 +#define DA9052_RTC_OSC_FRQ_MINUS_158_3ppm 173 +#define DA9052_RTC_OSC_FRQ_MINUS_156_4ppm 174 +#define DA9052_RTC_OSC_FRQ_MINUS_154_4ppm 175 +#define DA9052_RTC_OSC_FRQ_MINUS_152_5ppm 176 +#define DA9052_RTC_OSC_FRQ_MINUS_150_6ppm 177 +#define DA9052_RTC_OSC_FRQ_MINUS_148_7ppm 178 +#define DA9052_RTC_OSC_FRQ_MINUS_146_8ppm 179 +#define DA9052_RTC_OSC_FRQ_MINUS_144_9ppm 180 +#define DA9052_RTC_OSC_FRQ_MINUS_143_0ppm 181 +#define DA9052_RTC_OSC_FRQ_MINUS_141_1ppm 182 +#define DA9052_RTC_OSC_FRQ_MINUS_139_2ppm 183 +#define DA9052_RTC_OSC_FRQ_MINUS_137_3ppm 184 +#define DA9052_RTC_OSC_FRQ_MINUS_135_4ppm 185 +#define DA9052_RTC_OSC_FRQ_MINUS_133_5ppm 186 +#define DA9052_RTC_OSC_FRQ_MINUS_131_6ppm 187 +#define DA9052_RTC_OSC_FRQ_MINUS_129_6ppm 188 +#define DA9052_RTC_OSC_FRQ_MINUS_127_7ppm 189 +#define DA9052_RTC_OSC_FRQ_MINUS_125_8ppm 190 +#define DA9052_RTC_OSC_FRQ_MINUS_123_9ppm 191 +#define DA9052_RTC_OSC_FRQ_MINUS_122_0ppm 192 +#define DA9052_RTC_OSC_FRQ_MINUS_120_1ppm 193 +#define DA9052_RTC_OSC_FRQ_MINUS_118_2ppm 194 +#define DA9052_RTC_OSC_FRQ_MINUS_116_3ppm 195 +#define DA9052_RTC_OSC_FRQ_MINUS_114_4ppm 196 +#define DA9052_RTC_OSC_FRQ_MINUS_112_5ppm 197 +#define DA9052_RTC_OSC_FRQ_MINUS_110_6ppm 198 +#define DA9052_RTC_OSC_FRQ_MINUS_108_7ppm 199 +#define DA9052_RTC_OSC_FRQ_MINUS_106_8ppm 200 +#define DA9052_RTC_OSC_FRQ_MINUS_104_9ppm 201 +#define DA9052_RTC_OSC_FRQ_MINUS_102_9ppm 202 +#define DA9052_RTC_OSC_FRQ_MINUS_101_0ppm 203 +#define DA9052_RTC_OSC_FRQ_MINUS_99_1ppm 204 +#define DA9052_RTC_OSC_FRQ_MINUS_97_2ppm 205 +#define DA9052_RTC_OSC_FRQ_MINUS_95_3ppm 206 +#define DA9052_RTC_OSC_FRQ_MINUS_93_4ppm 207 +#define DA9052_RTC_OSC_FRQ_MINUS_91_5ppm 208 +#define DA9052_RTC_OSC_FRQ_MINUS_89_6ppm 209 +#define DA9052_RTC_OSC_FRQ_MINUS_87_7ppm 210 +#define DA9052_RTC_OSC_FRQ_MINUS_85_8ppm 211 +#define DA9052_RTC_OSC_FRQ_MINUS_83_9ppm 212 +#define DA9052_RTC_OSC_FRQ_MINUS_82_0ppm 213 +#define DA9052_RTC_OSC_FRQ_MINUS_80_1ppm 214 +#define DA9052_RTC_OSC_FRQ_MINUS_78_2ppm 215 +#define DA9052_RTC_OSC_FRQ_MINUS_76_2ppm 216 +#define DA9052_RTC_OSC_FRQ_MINUS_74_3ppm 217 +#define DA9052_RTC_OSC_FRQ_MINUS_72_4ppm 218 +#define DA9052_RTC_OSC_FRQ_MINUS_70_5ppm 219 +#define DA9052_RTC_OSC_FRQ_MINUS_68_6ppm 220 +#define DA9052_RTC_OSC_FRQ_MINUS_66_7ppm 221 +#define DA9052_RTC_OSC_FRQ_MINUS_64_8ppm 222 +#define DA9052_RTC_OSC_FRQ_MINUS_62_9ppm 223 +#define DA9052_RTC_OSC_FRQ_MINUS_61_0ppm 224 +#define DA9052_RTC_OSC_FRQ_MINUS_59_1ppm 225 +#define DA9052_RTC_OSC_FRQ_MINUS_57_2ppm 226 +#define DA9052_RTC_OSC_FRQ_MINUS_55_3ppm 227 +#define DA9052_RTC_OSC_FRQ_MINUS_53_4ppm 228 +#define DA9052_RTC_OSC_FRQ_MINUS_51_4ppm 229 +#define DA9052_RTC_OSC_FRQ_MINUS_49_5ppm 230 +#define DA9052_RTC_OSC_FRQ_MINUS_47_6ppm 231 +#define DA9052_RTC_OSC_FRQ_MINUS_45_7ppm 232 +#define DA9052_RTC_OSC_FRQ_MINUS_43_8ppm 233 +#define DA9052_RTC_OSC_FRQ_MINUS_41_9ppm 234 +#define DA9052_RTC_OSC_FRQ_MINUS_40_0ppm 235 +#define DA9052_RTC_OSC_FRQ_MINUS_38_1ppm 236 +#define DA9052_RTC_OSC_FRQ_MINUS_36_2ppm 237 +#define DA9052_RTC_OSC_FRQ_MINUS_34_3ppm 238 +#define DA9052_RTC_OSC_FRQ_MINUS_32_4ppm 239 +#define DA9052_RTC_OSC_FRQ_MINUS_30_5ppm 240 +#define DA9052_RTC_OSC_FRQ_MINUS_28_6ppm 241 +#define DA9052_RTC_OSC_FRQ_MINUS_26_7ppm 242 +#define DA9052_RTC_OSC_FRQ_MINUS_24_7ppm 243 +#define DA9052_RTC_OSC_FRQ_MINUS_22_8ppm 244 +#define DA9052_RTC_OSC_FRQ_MINUS_20_9ppm 245 +#define DA9052_RTC_OSC_FRQ_MINUS_19_0ppm 246 +#define DA9052_RTC_OSC_FRQ_MINUS_17_1ppm 247 +#define DA9052_RTC_OSC_FRQ_MINUS_15_2ppm 248 +#define DA9052_RTC_OSC_FRQ_MINUS_13_3ppm 249 +#define DA9052_RTC_OSC_FRQ_MINUS_11_4ppm 250 +#define DA9052_RTC_OSC_FRQ_MINUS_9_5ppm 251 +#define DA9052_RTC_OSC_FRQ_MINUS_7_6ppm 252 +#define DA9052_RTC_OSC_FRQ_MINUS_5_7ppm 253 +#define DA9052_RTC_OSC_FRQ_MINUS_3_8ppm 254 +#define DA9052_RTC_OSC_FRQ_MINUS_1_9ppm 255 + +/* RTC error codes */ +#define DA9052_RTC_INVALID_SECONDS 3 +#define DA9052_RTC_INVALID_MINUTES 4 +#define DA9052_RTC_INVALID_HOURS 5 +#define DA9052_RTC_INVALID_DAYS 6 +#define DA9052_RTC_INVALID_MONTHS 7 +#define DA9052_RTC_INVALID_YEARS 8 +#define DA9052_RTC_INVALID_EVENT 9 +#define DA9052_RTC_INVALID_IOCTL 10 +#define DA9052_RTC_INVALID_SETTING 11 +#define DA9052_RTC_EVENT_ALREADY_REGISTERED 12 +#define DA9052_RTC_EVENT_UNREGISTERED 13 +#define DA9052_RTC_EVENT_REGISTRATION_FAILED 14 +#define DA9052_RTC_EVENT_UNREGISTRATION_FAILED 15 + +#endif +/* __LINUX_MFD_DA9052_RTC_H */ \ No newline at end of file diff --git a/include/linux/mfd/da9052/tsi.h b/include/linux/mfd/da9052/tsi.h new file mode 100644 index 000000000000..b0f5c2449e4f --- /dev/null +++ b/include/linux/mfd/da9052/tsi.h @@ -0,0 +1,427 @@ +/* + * da9052 TSI module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_TSI_H +#define __LINUX_MFD_DA9052_TSI_H + +#include +#include +#include +#include + +#define DA9052_TSI_DEVICE_NAME "da9052-tsi" +#define DA9052_TSI_INPUT_DEV DA9052_TSI_DEVICE_NAME + +#define TSI_VERSION 0x0101 +#define DA9052_VENDOR_ID 0x15B6 +#define DA9052_PRODUCT_ID 0x9052 + +#define TSI_INPUT_DEVICE_OFF 0 +#define NUM_INPUT_DEVS 1 + +#define DA9052_DISPLAY_X_MAX 0x3FF +#define DA9052_DISPLAY_Y_MAX 0x3FF +#define DA9052_TOUCH_PRESSURE_MAX 0x3FF + +#define DA9052_TCA_AUTO_TSI_ENABLE (1<<0) +#define DA9052_TCA_PEN_DET_ENABLE (1<<1) +#define DA9052_TCA_TSI_XP_MODE_ENABLE (1<<2) + +#define DA9052_TCA_TSI_DELAY_0SLOTS (0<<6) +#define DA9052_TCA_TSI_DELAY_2SLOTS (2<<6) +#define DA9052_TCA_TSI_DELAY_4SLOTS (3<<6) + +#define DA9052_TCA_TSI_SEL_XPLUS (1<<0) +#define DA9052_TCA_TSI_SEL_XMINUS (1<<1) +#define DA9052_TCA_TSI_SEL_YPLUS (1<<2) +#define DA9052_TCA_TSI_SEL_YMINUS (1<<3) + +#define DA9052_TCA_TSI_MUX_XPLUS_ROUTED_ADCIN7 (0<<4) +#define DA9052_TCA_TSI_MUX_YPLUS_ROUTED_ADCIN7 (1<<4) +#define DA9052_TCA_TSI_MUX_XMINUS_ROUTED_ADCIN7 (2<<4) +#define DA9052_TCA_TSI_MUX_YMINUS_ROUTED_ADCIN7 (3<<4) + +#define DA9052_TCA_TSI_MAN_ENABLE (1<<6) +#define DA9052_TCA_TSI_SET_TSIREF (0<<7) +#define DA9052_TCA_TSI_SET_XY_REF (1<<7) + +#define DA9052_EVETN_B_E_PEN_DOWN (1<<6) +#define DA9052_EVENT_B_E_TSI_READY (1<<7) + +#define DA9052_IRQMASK_B_PENDOWN_MASK (1<<6) +#define DA9052_IRQMASK_B_TSI_READY_MASK (1<<7) + +#define X_LSB_SHIFT (0) +#define Y_LSB_SHIFT (2) +#define Z_LSB_SHIFT (4) +#define PEN_DET_SHIFT (6) +#define X_MSB_SHIFT (2) +#define Y_MSB_SHIFT (2) +#define Z_MSB_SHIFT (2) +#define X_LSB_MASK (11 << X_LSB_SHIFT) +#define Y_LSB_MASK (11 << Y_LSB_SHIFT) +#define Z_LSB_MASK (11 << Z_LSB_SHIFT) +#define PEN_DET_MASK (11 << PEN_DET_SHIFT) + +#define TSI_FIFO_SIZE 16 + +#define INVALID_LDO9_VOLT_VALUE 17 + +#define set_bits(value, mask) (value | mask) +#define clear_bits(value, mask) (value & ~(mask)) + +#define SUCCESS 0 +#define FAILURE 1 + +#define SET 1 +#define RESET 0 +#define CLEAR 0 + +#define ENABLE 1 +#define DISABLE 0 + +#define TRUE 1 +#define FALSE 0 + +#define incr_with_wrap_reg_fifo(x) \ + if(++x >= TSI_REG_DATA_BUF_SIZE) \ + x = 0 + +#define incr_with_wrap(x) \ + if(++x >= TSI_FIFO_SIZE) \ + x = 0 + +#undef DA9052_DEBUG +#if DA9052_TSI_DEBUG +#define DA9052_DEBUG( fmt, args... ) printk( KERN_CRIT "" fmt, ##args ) +#else +#define DA9052_DEBUG( fmt, args... ) +#endif + +enum ADC_MODE { + + ECONOMY_MODE = 0, + FAST_MODE = 1 +}; + +enum TSI_DELAY { + TSI_DELAY_0SLOTS = 0, + TSI_DELAY_1SLOTS = 1, + TSI_DELAY_2SLOTS = 2, + TSI_DELAY_4SLOTS = 3 +}; + +enum TSI_SLOT_SKIP{ + TSI_SKIP_0SLOTS = 0, + TSI_SKIP_2SLOTS = 1, + TSI_SKIP_5SLOTS = 2, + TSI_SKIP_10SLOTS = 3, + TSI_SKIP_30SLOTS = 4, + TSI_SKIP_80SLOTS = 5, + TSI_SKIP_130SLOTS = 6, + TSI_SKIP_330SLOTS = 7 +}; + + +enum TSI_MUX_SEL +{ + TSI_MUX_XPLUS = 0, + TSI_MUX_YPLUS = 1, + TSI_MUX_XMINUS = 2, + TSI_MUX_YMINUS = 3 +}; + + +enum TSI_IRQ{ + TSI_PEN_DWN, + TSI_DATA_RDY +}; + + +enum TSI_COORDINATE{ + X_COORDINATE, + Y_COORDINATE, + Z_COORDINATE +}; + +enum TSI_MEASURE_SEQ{ + XYZP_MODE, + XP_MODE +}; + +enum TSI_STATE { + TSI_AUTO_MODE, + TSI_MANUAL_COORD_X, + TSI_MANUAL_COORD_Y, + TSI_MANUAL_COORD_Z, + TSI_MANUAL_SET, + TSI_IDLE +}; + +union da9052_tsi_cont_reg { + u8 da9052_tsi_cont_a; + struct{ + u8 auto_tsi_en:1; + u8 pen_det_en:1; + u8 tsi_mode:1; + u8 tsi_skip:3; + u8 tsi_delay:2; + }tsi_cont_a; +}; + +union da9052_tsi_man_cont_reg { + u8 da9052_tsi_cont_b; + struct{ + u8 tsi_sel_0:1; + u8 tsi_sel_1:1; + u8 tsi_sel_2:1; + u8 tsi_sel_3:1; + u8 tsi_mux:2; + u8 tsi_man:1; + u8 tsi_adc_ref:1; + }tsi_cont_b; +}; + +struct da9052_tsi_conf { + union da9052_tsi_cont_reg auto_cont; + union da9052_tsi_man_cont_reg man_cont; + u8 tsi_adc_sample_intervel:1; + enum TSI_STATE state; + u8 ldo9_en:1; + u8 ldo9_conf:1; + u8 tsi_ready_irq_mask:1; + u8 tsi_pendown_irq_mask:1; +}; + + +struct da9052_tsi_reg { + u8 x_msb; + u8 y_msb; + u8 z_msb; + u8 lsb; + }; + + +struct da9052_tsi_reg_fifo { + struct semaphore lock; + s32 head; + s32 tail; + struct da9052_tsi_reg data[TSI_REG_DATA_BUF_SIZE]; +}; + +struct da9052_tsi_info { + struct da9052_tsi_conf tsi_conf; + struct input_dev *input_devs[NUM_INPUT_DEVS]; + struct calib_cfg_t *tsi_calib; + u32 tsi_data_poll_interval; + u32 tsi_penup_count; + u32 tsi_zero_data_cnt; + u8 pen_dwn_event; + u8 tsi_rdy_event; + u8 pd_reg_status; + u8 datardy_reg_status; +}; + +struct da9052_tsi { + struct da9052_tsi_reg tsi_fifo[TSI_FIFO_SIZE]; + struct mutex tsi_fifo_lock; + u8 tsi_sampling; + u8 tsi_state; + u32 tsi_fifo_start; + u32 tsi_fifo_end; +}; + + struct da9052_ts_priv { + struct da9052 *da9052; + struct da9052_eh_nb pd_nb; + struct da9052_eh_nb datardy_nb; + + struct tsi_thread_type tsi_reg_proc_thread; + struct tsi_thread_type tsi_raw_proc_thread; + + struct da9052_tsi_platform_data *tsi_pdata; + + struct da9052_tsi_reg_fifo tsi_reg_fifo; + struct da9052_tsi_raw_fifo tsi_raw_fifo; + + u32 tsi_reg_data_poll_interval; + u32 tsi_raw_data_poll_interval; + + u8 early_data_flag; + u8 debounce_over; + u8 win_reference_valid; + + int os_data_cnt; + int raw_data_cnt; +}; + +static inline u8 mask_pendwn_irq(u8 val) +{ + return (val |= DA9052_IRQMASKB_MPENDOWN); +} + +static inline u8 unmask_pendwn_irq(u8 val) +{ + return (val &= ~DA9052_IRQMASKB_MPENDOWN); +} + +static inline u8 mask_tsi_rdy_irq(u8 val) +{ + return (val |=DA9052_IRQMASKB_MTSIREADY); +} + +static inline u8 unmask_tsi_rdy_irq(u8 val) +{ + return (val &= ~DA9052_IRQMASKB_MTSIREADY); +} + +static inline u8 enable_ldo9(u8 val) +{ + return (val |=DA9052_LDO9_LDO9EN); +} + +static inline u8 disable_ldo9(u8 val) +{ + return (val &= ~DA9052_LDO9_LDO9EN); +} + +static inline u8 set_auto_tsi_en(u8 val) +{ + return (val |=DA9052_TSICONTA_AUTOTSIEN); +} + +static inline u8 reset_auto_tsi_en(u8 val) +{ + return (val &=~DA9052_TSICONTA_AUTOTSIEN); +} + +static inline u8 enable_pen_detect(u8 val) +{ + return (val |=DA9052_TSICONTA_PENDETEN); +} + +static inline u8 disable_pen_detect(u8 val) +{ + return (val &=~DA9052_TSICONTA_PENDETEN); +} + +static inline u8 enable_xyzp_mode(u8 val) +{ + return (val &= ~DA9052_TSICONTA_TSIMODE); +} + +static inline u8 enable_xp_mode(u8 val) +{ + return(val |= DA9052_TSICONTA_TSIMODE); +} + +static inline u8 enable_tsi_manual_mode(u8 val) +{ + return(val |= DA9052_TSICONTB_TSIMAN); +} + +static inline u8 disable_tsi_manual_mode(u8 val) +{ + return(val &= ~DA9052_TSICONTB_TSIMAN); +} + +static inline u8 tsi_sel_xplus_close(u8 val) +{ + return(val |= DA9052_TSICONTB_TSISEL0); +} + +static inline u8 tsi_sel_xplus_open(u8 val) +{ + return(val &= ~DA9052_TSICONTB_TSISEL0); +} + +static inline u8 tsi_sel_xminus_close(u8 val) +{ + return(val |= DA9052_TSICONTB_TSISEL1); +} + +static inline u8 tsi_sel_xminus_open(u8 val) +{ + return(val &= ~DA9052_TSICONTB_TSISEL1); +} + +static inline u8 tsi_sel_yplus_close(u8 val) +{ + return(val |= DA9052_TSICONTB_TSISEL2); +} + +static inline u8 tsi_sel_yplus_open(u8 val) +{ + return(val &= ~DA9052_TSICONTB_TSISEL2); +} + +static inline u8 tsi_sel_yminus_close(u8 val) +{ + return(val |= DA9052_TSICONTB_TSISEL3); +} + +static inline u8 tsi_sel_yminus_open(u8 val) +{ + return(val &= ~DA9052_TSICONTB_TSISEL3); +} + +static inline u8 adc_mode_economy_mode(u8 val) +{ + return(val &= ~DA9052_ADCCONT_ADCMODE); +} + +static inline u8 adc_mode_fast_mode(u8 val) +{ + return(val |= DA9052_ADCCONT_ADCMODE); +} +int da9052_tsi_get_calib_display_point(struct da9052_tsi_data *display); + +struct da9052_ldo_config { + u16 ldo_volt; + u8 ldo_num; + u8 ldo_conf:1; + u8 ldo_pd:1; +}; + +static inline u8 ldo9_mV_to_reg(u16 value) +{ + return ((value - DA9052_LDO9_VOLT_LOWER)/DA9052_LDO9_VOLT_STEP); +} + +static inline u8 validate_ldo9_mV(u16 value) +{ + if ((value >= DA9052_LDO9_VOLT_LOWER) && \ + (value <= DA9052_LDO9_VOLT_UPPER)) + return + (((value - DA9052_LDO9_VOLT_LOWER) % DA9052_LDO9_VOLT_STEP > 0) ? -1 : 0); + return FAILURE; +} + +s32 da9052_tsi_raw_proc_thread (void *ptr); +void __init da9052_init_tsi_fifos (struct da9052_ts_priv *priv); +void clean_tsi_fifos(struct da9052_ts_priv *priv); +u32 get_reg_data_cnt (struct da9052_ts_priv *priv); +u32 get_reg_free_space_cnt(struct da9052_ts_priv *priv); +void da9052_tsi_process_reg_data(struct da9052_ts_priv *priv); +void da9052_tsi_pen_down_handler(struct da9052_eh_nb *eh_data, u32 event); +void da9052_tsi_data_ready_handler(struct da9052_eh_nb *eh_data, u32 event); + +#endif /* __LINUX_MFD_DA9052_TSI_H */ diff --git a/include/linux/mfd/da9052/tsi_calibrate.h b/include/linux/mfd/da9052/tsi_calibrate.h new file mode 100644 index 000000000000..a4b42ea079a9 --- /dev/null +++ b/include/linux/mfd/da9052/tsi_calibrate.h @@ -0,0 +1,47 @@ +/* + * da9052 TSI calibration module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_TSI_CALIBRATE_H +#define __LINUX_MFD_DA9052_TSI_CALIBRATE_H + +#include + +struct Calib_xform_matrix_t { + s32 An; + s32 Bn; + s32 Cn; + s32 Dn; + s32 En; + s32 Fn; + s32 Divider; +} ; + + +struct calib_cfg_t { + u8 calibrate_flag; +} ; + +ssize_t da9052_tsi_set_calib_matrix(struct da9052_tsi_data *displayPtr, + struct da9052_tsi_data *screenPtr); +u8 configure_tsi_calib(struct calib_cfg_t *tsi_calib); +struct calib_cfg_t *get_calib_config(void); +#endif /* __LINUX_MFD_DA9052_TSI_CALIBRATE_H */ + diff --git a/include/linux/mfd/da9052/tsi_cfg.h b/include/linux/mfd/da9052/tsi_cfg.h new file mode 100644 index 000000000000..512fe3bf8d4f --- /dev/null +++ b/include/linux/mfd/da9052/tsi_cfg.h @@ -0,0 +1,132 @@ +/* + * da9052 TSI configuration module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_TSI_CFG_H +#define __LINUX_MFD_DA9052_TSI_CFG_H + +#define DA9052_TSI_DEBUG 0 + +#define AUTO_MODE 0 +#define IDLE 1 +#define DEFAULT_TSI_STATE AUTO_MODE + +#define TSI_SLOT_SKIP_VALUE 0 + +#define TSI_DELAY_VALUE 3 + +#define TSI_MODE_VALUE 0 + +#define ENABLE_AVERAGE_FILTER 1 + +#define DEFAULT_AVERAGE_FILTER_SIZE 3 + +#define ENABLE_WINDOW_FILTER 1 + +#define TSI_X_WINDOW_SIZE 50 +#define TSI_Y_WINDOW_SIZE 50 + +#define SAMPLE_CNT_FOR_WIN_REF 3 + +#define TSI_ECONOMY_MODE 0 +#define TSI_FAST_MODE 1 +#define DEFAULT_TSI_SAMPLING_MODE TSI_FAST_MODE + +#define TSI_USE_CALIBRATION 1 + +#define DA9052_TSI_CALIB_AN 1 +#define DA9052_TSI_CALIB_BN 0 +#define DA9052_TSI_CALIB_CN 0 +#define DA9052_TSI_CALIB_DN 0 +#define DA9052_TSI_CALIB_EN 1 +#define DA9052_TSI_CALIB_FN 0 +#define DA9052_TSI_CALIB_DIVIDER 1 + +#define TS_X_MIN (0) +#define TS_X_MAX (1023) +#define TS_Y_MIN (0) +#define TS_Y_MAX (1023) + +#define DISPLAY_X_MIN (0) +#define DISPLAY_X_MAX (1023) +#define DISPLAY_Y_MIN (0) +#define DISPLAY_Y_MAX (1023) + +#define ENABLE_TSI_DEBOUNCE 0 + +#define TSI_DEBOUNCE_DATA_CNT 3 + + +#define RELEASE +#define DA9052_TSI_RAW_DATA_PROFILING 0 +#define DA9052_TSI_WIN_FLT_DATA_PROFILING 0 +#define DA9052_TSI_AVG_FLT_DATA_PROFILING 0 +#define DA9052_TSI_CALIB_DATA_PROFILING 0 +#define DA9052_TSI_OS_DATA_PROFILING 0 +#define DA9052_TSI_PRINT_DEBOUNCED_DATA 0 +#define DA9052_TSI_PRINT_PREVIOUS_DATA 0 + + +#if ENABLE_AVERAGE_FILTER +#define TSI_AVERAGE_FILTER_SIZE DEFAULT_AVERAGE_FILTER_SIZE +#else +#define TSI_AVERAGE_FILTER_SIZE 1 +#endif + +#define TSI_FAST_MODE_SAMPLE_CNT 1000 +#define TSI_ECO_MODE_SAMPLE_CNT 100 + +#define TSI_POLL_SAMPLE_CNT 10 + +#define TSI_FAST_MODE_REG_DATA_PROCESSING_INTERVAL \ + ((1000 / TSI_FAST_MODE_SAMPLE_CNT)* TSI_POLL_SAMPLE_CNT) +#define TSI_ECO_MODE_REG_DATA_PROCESSING_INTERVAL \ + ((1000 / TSI_ECO_MODE_SAMPLE_CNT)* TSI_POLL_SAMPLE_CNT) + +#if DEFAULT_TSI_SAMPLING_MODE +#define DEFAULT_REG_DATA_PROCESSING_INTERVAL \ + TSI_FAST_MODE_REG_DATA_PROCESSING_INTERVAL +#else +#define DEFAULT_REG_DATA_PROCESSING_INTERVAL \ + TSI_ECO_MODE_REG_DATA_PROCESSING_INTERVAL +#endif + +#define TSI_REG_DATA_BUF_SIZE (2 * TSI_POLL_SAMPLE_CNT) + +#define TSI_FAST_MODE_RAW_DATA_PROCESSING_INTERVAL \ + ((1000 / TSI_FAST_MODE_SAMPLE_CNT) * (TSI_AVERAGE_FILTER_SIZE)) +#define TSI_ECO_MODE_RAW_DATA_PROCESSING_INTERVAL \ + ((1000 / TSI_ECO_MODE_SAMPLE_CNT) * (TSI_AVERAGE_FILTER_SIZE)) + + +#if DEFAULT_TSI_SAMPLING_MODE +#define DEFAULT_RAW_DATA_PROCESSING_INTERVAL \ + TSI_FAST_MODE_RAW_DATA_PROCESSING_INTERVAL +#else +#define DEFAULT_RAW_DATA_PROCESSING_INTERVAL \ + TSI_ECO_MODE_RAW_DATA_PROCESSING_INTERVAL +#endif + + +#define TSI_RAW_DATA_BUF_SIZE \ + (TSI_REG_DATA_BUF_SIZE * \ + ( (TSI_AVERAGE_FILTER_SIZE / TSI_POLL_SAMPLE_CNT) + 1)) + +#endif /* __LINUX_MFD_DA9052_TSI_CFG_H */ diff --git a/include/linux/mfd/da9052/tsi_filter.h b/include/linux/mfd/da9052/tsi_filter.h new file mode 100644 index 000000000000..a244fbd9bf12 --- /dev/null +++ b/include/linux/mfd/da9052/tsi_filter.h @@ -0,0 +1,57 @@ +/* + * da9052 TSI filter module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_TSI_FILTER_H +#define __LINUX_MFD_DA9052_TSI_FILTER_H + +#include +#include + +struct da9052_tsi_data { + s16 x; + s16 y; + s16 z; +}; + +struct da9052_tsi_raw_fifo { + struct semaphore lock; + s32 head; + s32 tail; + struct da9052_tsi_data data[TSI_RAW_DATA_BUF_SIZE]; +}; + +struct tsi_thread_type { + u8 pid; + u8 state; + struct completion notifier; + struct task_struct *thread_task; +} ; + +/* State for TSI thread */ +#define ACTIVE 0 +#define INACTIVE 1 + + +extern u32 da9052_tsi_get_input_dev(u8 off); + +ssize_t da9052_tsi_get_calib_display_point(struct da9052_tsi_data *displayPtr); + +#endif /* __LINUX_MFD_DA9052_TSI_FILTER_H */ diff --git a/include/linux/mfd/da9052/wdt.h b/include/linux/mfd/da9052/wdt.h new file mode 100644 index 000000000000..6a77bfc5fd9b --- /dev/null +++ b/include/linux/mfd/da9052/wdt.h @@ -0,0 +1,83 @@ +/* + * da9052 SM (watchdog) module declarations. + * + * Copyright(c) 2009 Dialog Semiconductor Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __LINUX_MFD_DA9052_WDT_H +#define __LINUX_MFD_DA9052_WDT_H + +#include + +/* To enable debug output for your module, set this to 1 */ +#define DA9052_SM_DEBUG 0 + +/* Error codes */ +#define BUS_ERR 2 +#define INIT_FAIL 3 +#define SM_OPEN_FAIL 4 +#define NO_IOCTL_CMD 5 +#define INVALID_SCALING_VALUE 6 +#define STROBING_FILTER_ERROR 7 +#define TIMER_DELETE_ERR 8 +#define STROBING_MODE_ERROR 9 + +/* IOCTL Switch */ +/* For strobe watchdog function */ +#define DA9052_SM_IOCTL_STROBE_WDT 1 + +/* For setting watchdog timer time */ +#define DA9052_SM_IOCTL_SET_WDT 2 + +/* For enabling/disabling strobing filter */ +#define DA9052_SM_IOCTL_SET_STROBING_FILTER 3 + +/* For enabling/disabling strobing filter */ +#define DA9052_SM_IOCTL_SET_STROBING_MODE 4 + +/* Watchdog time scaling TWDMAX scaling macros */ +#define DA9052_WDT_DISABLE 0 +#define DA9052_SCALE_1X 1 +#define DA9052_SCALE_2X 2 +#define DA9052_SCALE_4X 3 +#define DA9052_SCALE_8X 4 +#define DA9052_SCALE_16X 5 +#define DA9052_SCALE_32X 6 +#define DA9052_SCALE_64X 7 + +#define DA9052_STROBE_WIN_FILTER_PER 80 +#define DA9052_X1_WINDOW ((1 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X2_WINDOW ((2 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X4_WINDOW ((4 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X8_WINDOW ((8 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X16_WINDOW ((16 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X32_WINDOW ((32 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) +#define DA9052_X64_WINDOW ((64 * 2048 * DA9052_STROBE_WIN_FILTER_PER)/100) + +#define DA9052_STROBE_AUTO 1 +#define DA9052_STROBE_MANUAL 0 + +#define DA9052_SM_STROBE_CONF DISABLE + +#define DA9052_ADC_TWDMIN_TIME 500 + +void start_strobing(struct work_struct *work); +/* Create a handler for the scheduling start_strobing function */ +DECLARE_WORK(strobing_action, start_strobing); + +#endif /* __LINUX_MFD_DA9052_WDT_H */ diff --git a/include/linux/mfd/ltc3589/core.h b/include/linux/mfd/ltc3589/core.h new file mode 100644 index 000000000000..514dc56e5992 --- /dev/null +++ b/include/linux/mfd/ltc3589/core.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __LINUX_MFD_LTC3589_CORE_H_ +#define __LINUX_MFD_LTC3589_CORE_H_ + +#include +#include +#include +#include + +#define LTC3589_SW1 0 +#define LTC3589_SW2 1 +#define LTC3589_SW3 2 +#define LTC3589_SW4 3 +#define LTC3589_LDO1 4 +#define LTC3589_LDO2 5 +#define LTC3589_LDO3 6 +#define LTC3589_LDO4 7 +#define LTC3589_REG_NUM 8 + +extern struct i2c_client *ltc3589_client; + +struct ltc3589; +struct regulator_init_data; + +struct ltc3589_platform_data { + int (*init)(struct ltc3589 *); +}; + +struct ltc3589_pmic { + /* regulator devices */ + struct platform_device *pdev[LTC3589_REG_NUM]; +}; + +struct ltc3589 { + int rev; /* chip revision */ + + struct device *dev; + + /* device IO */ + struct i2c_client *i2c_client; + int (*read_dev)(struct ltc3589 *ltc, u8 reg); + int (*write_dev)(struct ltc3589 *ltc, u8 reg, u8 val); + u16 *reg_cache; + + /* Client devices */ + struct ltc3589_pmic pmic; +}; + +int ltc3589_register_regulator(struct ltc3589 *ltc3589, int reg, + struct regulator_init_data *initdata); +#endif diff --git a/include/linux/mfd/max17135.h b/include/linux/mfd/max17135.h new file mode 100644 index 000000000000..7c44ce14f785 --- /dev/null +++ b/include/linux/mfd/max17135.h @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __LINUX_REGULATOR_MAX17135_H_ +#define __LINUX_REGULATOR_MAX17135_H_ + +/* + * PMIC Register Addresses + */ +enum { + REG_MAX17135_EXT_TEMP = 0x0, + REG_MAX17135_CONFIG, + REG_MAX17135_INT_TEMP = 0x4, + REG_MAX17135_STATUS, + REG_MAX17135_PRODUCT_REV, + REG_MAX17135_PRODUCT_ID, + REG_MAX17135_DVR, + REG_MAX17135_ENABLE, + REG_MAX17135_FAULT, /*0x0A*/ + REG_MAX17135_HVINP, + REG_MAX17135_PRGM_CTRL, + REG_MAX17135_TIMING1 = 0x10, /* Timing regs base address is 0x10 */ + REG_MAX17135_TIMING2, + REG_MAX17135_TIMING3, + REG_MAX17135_TIMING4, + REG_MAX17135_TIMING5, + REG_MAX17135_TIMING6, + REG_MAX17135_TIMING7, + REG_MAX17135_TIMING8, +}; +#define MAX17135_REG_NUM 21 +#define MAX17135_MAX_REGISTER 0xFF + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Shift and width values for each register bitfield + */ +#define EXT_TEMP_LSH 7 +#define EXT_TEMP_WID 9 + +#define THERMAL_SHUTDOWN_LSH 0 +#define THERMAL_SHUTDOWN_WID 1 + +#define INT_TEMP_LSH 7 +#define INT_TEMP_WID 9 + +#define STAT_BUSY_LSH 0 +#define STAT_BUSY_WID 1 +#define STAT_OPEN_LSH 1 +#define STAT_OPEN_WID 1 +#define STAT_SHRT_LSH 2 +#define STAT_SHRT_WID 1 + +#define PROD_REV_LSH 0 +#define PROD_REV_WID 8 + +#define PROD_ID_LSH 0 +#define PROD_ID_WID 8 + +#define DVR_LSH 0 +#define DVR_WID 8 + +#define ENABLE_LSH 0 +#define ENABLE_WID 1 +#define VCOM_ENABLE_LSH 1 +#define VCOM_ENABLE_WID 1 + +#define FAULT_FBPG_LSH 0 +#define FAULT_FBPG_WID 1 +#define FAULT_HVINP_LSH 1 +#define FAULT_HVINP_WID 1 +#define FAULT_HVINN_LSH 2 +#define FAULT_HVINN_WID 1 +#define FAULT_FBNG_LSH 3 +#define FAULT_FBNG_WID 1 +#define FAULT_HVINPSC_LSH 4 +#define FAULT_HVINPSC_WID 1 +#define FAULT_HVINNSC_LSH 5 +#define FAULT_HVINNSC_WID 1 +#define FAULT_OT_LSH 6 +#define FAULT_OT_WID 1 +#define FAULT_POK_LSH 7 +#define FAULT_POK_WID 1 + +#define HVINP_LSH 0 +#define HVINP_WID 4 + +#define CTRL_DVR_LSH 0 +#define CTRL_DVR_WID 1 +#define CTRL_TIMING_LSH 1 +#define CTRL_TIMING_WID 1 + +#define TIMING1_LSH 0 +#define TIMING1_WID 8 +#define TIMING2_LSH 0 +#define TIMING2_WID 8 +#define TIMING3_LSH 0 +#define TIMING3_WID 8 +#define TIMING4_LSH 0 +#define TIMING4_WID 8 +#define TIMING5_LSH 0 +#define TIMING5_WID 8 +#define TIMING6_LSH 0 +#define TIMING6_WID 8 +#define TIMING7_LSH 0 +#define TIMING7_WID 8 +#define TIMING8_LSH 0 +#define TIMING8_WID 8 + +struct max17135 { + /* chip revision */ + int rev; + + struct device *dev; + + /* Platform connection */ + struct i2c_client *i2c_client; + + /* Client devices */ + struct platform_device *pdev[MAX17135_REG_NUM]; + + /* Timings */ + unsigned int gvee_pwrup; + unsigned int vneg_pwrup; + unsigned int vpos_pwrup; + unsigned int gvdd_pwrup; + unsigned int gvdd_pwrdn; + unsigned int vpos_pwrdn; + unsigned int vneg_pwrdn; + unsigned int gvee_pwrdn; + + /* GPIOs */ + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_intr; + + /* MAX17135 part variables */ + int pass_num; + int vcom_uV; + + /* One-time VCOM setup marker */ + bool vcom_setup; + bool init_done; + + /* powerup/powerdown wait time */ + int max_wait; + + /* Dynamically determined polarity for PWRGOOD */ + int pwrgood_polarity; +}; + +enum { + /* In alphabetical order */ + MAX17135_DISPLAY, /* virtual master enable */ + MAX17135_GVDD, + MAX17135_GVEE, + MAX17135_HVINN, + MAX17135_HVINP, + MAX17135_VCOM, + MAX17135_VNEG, + MAX17135_VPOS, + MAX17135_NUM_REGULATORS, +}; + +/* + * Declarations + */ +struct regulator_init_data; + +struct max17135_platform_data { + unsigned int gvee_pwrup; + unsigned int vneg_pwrup; + unsigned int vpos_pwrup; + unsigned int gvdd_pwrup; + unsigned int gvdd_pwrdn; + unsigned int vpos_pwrdn; + unsigned int vneg_pwrdn; + unsigned int gvee_pwrdn; + int gpio_pmic_pwrgood; + int gpio_pmic_vcom_ctrl; + int gpio_pmic_wakeup; + int gpio_pmic_intr; + int pass_num; + int vcom_uV; + struct regulator_init_data *regulator_init; + int (*init)(struct max17135 *); +}; + +int max17135_register_regulator(struct max17135 *max17135, int reg, + struct regulator_init_data *initdata); + +int max17135_reg_read(int reg_num, unsigned int *reg_val); +int max17135_reg_write(int reg_num, const unsigned int reg_val); + +#endif diff --git a/include/linux/mfd/mc13783/core.h b/include/linux/mfd/mc13783/core.h new file mode 100644 index 000000000000..3a068913f92c --- /dev/null +++ b/include/linux/mfd/mc13783/core.h @@ -0,0 +1,72 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __LINUX_MFD_MC13783_CORE_H_ +#define __LINUX_MFD_MC13783_CORE_H_ + +#include + +/*! + * brief PMIC regulators. + */ +#define MC13783_SW1A 0 +#define MC13783_SW1B 1 +#define MC13783_SW2A 2 +#define MC13783_SW2B 3 +#define MC13783_SW3 4 +#define MC13783_VAUDIO 5 +#define MC13783_VIOHI 6 +#define MC13783_VIOLO 7 +#define MC13783_VDIG 8 +#define MC13783_VGEN 9 +#define MC13783_VRFDIG 10 +#define MC13783_VRFREF 11 +#define MC13783_VRFCP 12 +#define MC13783_VSIM 13 +#define MC13783_VESIM 14 +#define MC13783_VCAM 15 +#define MC13783_VRFBG 16 +#define MC13783_VVIB 17 +#define MC13783_VRF1 18 +#define MC13783_VRF2 19 +#define MC13783_VMMC1 20 +#define MC13783_VMMC2 21 +#define MC13783_GPO1 22 +#define MC13783_GPO2 23 +#define MC13783_GPO3 24 +#define MC13783_GPO4 25 +#define MC13783_REG_NUM 26 + +struct mc13783; +struct regulator_init_data; + +struct mc13783_pmic { + /* regulator devices */ + struct platform_device *pdev[MC13783_REG_NUM]; +}; + +struct mc13783 { + int rev; /* chip revision */ + + struct device *dev; + + u16 *reg_cache; + + /* Client devices */ + struct mc13783_pmic pmic; +}; + +int mc13783_register_regulator(struct mc13783 *mc13783, int reg, + struct regulator_init_data *initdata); + +#endif diff --git a/include/linux/mfd/mc13892/core.h b/include/linux/mfd/mc13892/core.h new file mode 100644 index 000000000000..3924e2e3bce9 --- /dev/null +++ b/include/linux/mfd/mc13892/core.h @@ -0,0 +1,77 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __LINUX_MFD_MC13892_CORE_H_ +#define __LINUX_MFD_MC13892_CORE_H_ + +#include +#include +#include + +#define MC13892_SW1 0 +#define MC13892_SW2 1 +#define MC13892_SW3 2 +#define MC13892_SW4 3 +#define MC13892_SWBST 4 +#define MC13892_VIOHI 5 +#define MC13892_VPLL 6 +#define MC13892_VDIG 7 +#define MC13892_VSD 8 +#define MC13892_VUSB2 9 +#define MC13892_VVIDEO 10 +#define MC13892_VAUDIO 11 +#define MC13892_VCAM 12 +#define MC13892_VGEN1 13 +#define MC13892_VGEN2 14 +#define MC13892_VGEN3 15 +#define MC13892_VUSB 16 +#define MC13892_GPO1 17 +#define MC13892_GPO2 18 +#define MC13892_GPO3 19 +#define MC13892_GPO4 20 +#define MC13892_PWGT1 21 +#define MC13892_PWGT2 22 +#define MC13892_REG_NUM 23 + +struct mc13892; +struct regulator_init_data; + +struct mc13892_platform_data { + int (*init)(struct mc13892 *); +}; + +struct mc13892_pmic { + /* regulator devices */ + struct platform_device *pdev[MC13892_REG_NUM]; +}; + +struct mc13892 { + int rev; /* chip revision */ + + struct device *dev; + + /* device IO */ + union { + struct i2c_client *i2c_client; + struct spi_device *spi_device; + }; + u16 *reg_cache; + + /* Client devices */ + struct mc13892_pmic pmic; +}; + +int mc13892_register_regulator(struct mc13892 *mc13892, int reg, + struct regulator_init_data *initdata); + +#endif diff --git a/include/linux/mfd/mc34704/core.h b/include/linux/mfd/mc34704/core.h new file mode 100644 index 000000000000..f63ef0826364 --- /dev/null +++ b/include/linux/mfd/mc34704/core.h @@ -0,0 +1,84 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __LINUX_MFD_MC34704_CORE_H_ +#define __LINUX_MFD_MC34704_CORE_H_ + +#include +#include +#include + +#define MC34704_BKLT 0 /* REG1 5V for Backlight */ +#define MC34704_CPU 1 /* REG2 3.3V for CPU & CPU board peripherals */ +#define MC34704_CORE 2 /* REG3 1.45V for CPU Core */ +#define MC34704_DDR 3 /* REG4 1.8V for DDR */ +#define MC34704_PERS 4 /* REG5 3.3V for Personality board */ +#define MC34704_REG6 5 /* REG6 not used */ +#define MC34704_REG7 6 /* REG7 not used */ +#define MC34704_REG8 7 /* REG8 not used */ +#define MC34704_REG_NUM 8 + +/* Regulator voltages in mV and dynamic voltage scaling limits in percent */ + +#define REG1_V_MV 5000 +#define REG1_DVS_MIN_PCT (-10) +#define REG1_DVS_MAX_PCT 10 + +#define REG2_V_MV 3300 +#define REG2_DVS_MIN_PCT (-20) +#define REG2_DVS_MAX_PCT 17.5 + +#define REG3_V_MV 1450 +#define REG3_DVS_MIN_PCT (-20) +#define REG3_DVS_MAX_PCT 17.5 + +#define REG4_V_MV 1800 +#define REG4_DVS_MIN_PCT (-20) +#define REG4_DVS_MAX_PCT 17.5 + +#define REG5_V_MV 3300 +#define REG5_DVS_MIN_PCT (-20) +#define REG5_DVS_MAX_PCT 17.5 + +struct mc34704; +struct regulator_init_data; + +struct mc34704_platform_data { + int (*init) (struct mc34704 *); +}; + +struct mc34704_pmic { + /* regulator devices */ + struct platform_device *pdev[MC34704_REG_NUM]; +}; + +struct mc34704 { + int rev; /* chip revision */ + + struct device *dev; + + /* device IO */ + union { + struct i2c_client *i2c_client; + struct spi_device *spi_device; + }; + u16 *reg_cache; + + /* Client devices */ + struct mc34704_pmic pmic; +}; + +int mc34704_register_regulator(struct mc34704 *mc34704, int reg, + struct regulator_init_data *initdata); + +#endif diff --git a/include/linux/mfd/mc9s08dz60/core.h b/include/linux/mfd/mc9s08dz60/core.h new file mode 100644 index 000000000000..d568f651e760 --- /dev/null +++ b/include/linux/mfd/mc9s08dz60/core.h @@ -0,0 +1,59 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __LINUX_MFD_MC13892_CORE_H_ +#define __LINUX_MFD_MC13892_CORE_H_ + +#include +#include +#include + +#define MC9S08DZ60_LCD 0 +#define MC9S08DZ60_WIFI 1 +#define MC9S08DZ60_HDD 2 +#define MC9S08DZ60_GPS 3 +#define MC9S08DZ60_SPKR 4 +#define MC9S08DZ60_REG_NUM 5 + +struct mc9s08dz60; +struct regulator_init_data; + +struct mc9s08dz60_platform_data { + int (*init)(struct mc9s08dz60 *); +}; + +struct mc9s08dz60_pmic { + /* regulator devices */ + struct platform_device *pdev[MC9S08DZ60_REG_NUM]; +}; + +struct mc9s08dz60 { + int rev; /* chip revision */ + + struct device *dev; + + /* device IO */ + union { + struct i2c_client *i2c_client; + struct spi_device *spi_device; + }; + u16 *reg_cache; + + /* Client devices */ + struct mc9s08dz60_pmic pmic; +}; + +int mc9s08dz60_register_regulator(struct mc9s08dz60 *mc9s08dz60, int reg, + struct regulator_init_data *initdata); + +#endif diff --git a/include/linux/mfd/mc9s08dz60/pmic.h b/include/linux/mfd/mc9s08dz60/pmic.h new file mode 100644 index 000000000000..67a682245502 --- /dev/null +++ b/include/linux/mfd/mc9s08dz60/pmic.h @@ -0,0 +1,82 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +#ifndef __LINUX_MCU_PMIC_H_ +#define __LINUX_MCU_PMIC_H_ + +enum { + + /*reg names for mcu */ + REG_MCU_VERSION = 0, + REG_MCU_SECS, + REG_MCU_MINS, + REG_MCU_HRS, + REG_MCU_DAY, + REG_MCU_DATE, + REG_MCU_MONTH, + REG_MCU_YEAR, + REG_MCU_ALARM_SECS, + REG_MCU_ALARM_MINS, + REG_MCU_ALARM_HRS, + REG_MCU_TS_CONTROL, + REG_MCU_X_LOW, + REG_MCU_Y_LOW, + REG_MCU_XY_HIGH, + REG_MCU_X_LEFT_LOW, + REG_MCU_X_LEFT_HIGH, + REG_MCU_X_RIGHT, + REG_MCU_Y_TOP_LOW, + REG_MCU_Y_TOP_HIGH, + REG_MCU_Y_BOTTOM, + REG_MCU_RESET_1, + REG_MCU_RESET_2, + REG_MCU_POWER_CTL, + REG_MCU_DELAY_CONFIG, + REG_MCU_GPIO_1, + REG_MCU_GPIO_2, + REG_MCU_KPD_1, + REG_MCU_KPD_2, + REG_MCU_KPD_CONTROL, + REG_MCU_INT_ENABLE_1, + REG_MCU_INT_ENABLE_2, + REG_MCU_INT_FLAG_1, + REG_MCU_INT_FLAG_2, + REG_MCU_DES_FLAG, +}; + +enum { + + MCU_GPIO_REG_RESET_1, + MCU_GPIO_REG_RESET_2, + MCU_GPIO_REG_POWER_CONTROL, + MCU_GPIO_REG_GPIO_CONTROL_1, + MCU_GPIO_REG_GPIO_CONTROL_2, +}; + +int pmic_gpio_set_bit_val(int reg, unsigned int bit, + unsigned int val); + +int pmic_gpio_get_bit_val(int reg, unsigned int bit, + unsigned int *val); + +int pmic_gpio_get_designation_bit_val(unsigned int bit, + unsigned int *val); + + +int mcu_pmic_read_reg(int reg, unsigned int *reg_value, + unsigned int reg_mask); + +int mcu_pmic_write_reg(int reg, unsigned int reg_value, + unsigned int reg_mask); +#endif diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h index a95141eafce3..badb74cc2265 100644 --- a/include/linux/mfd/wm8350/audio.h +++ b/include/linux/mfd/wm8350/audio.h @@ -605,6 +605,8 @@ struct wm8350_audio_platform_data { int drain_msecs; /* OFF drain time */ int cap_discharge_msecs; /* Cap ON (from OFF) discharge time */ int vmid_charge_msecs; /* vmid power up time */ + char *regulator1; + char *regulator2; u32 vmid_s_curve:2; /* vmid enable s curve speed */ u32 dis_out4:2; /* out4 discharge speed */ u32 dis_out3:2; /* out3 discharge speed */ diff --git a/include/linux/mfd/wm8350/bl.h b/include/linux/mfd/wm8350/bl.h new file mode 100644 index 000000000000..c2c3fc921aa4 --- /dev/null +++ b/include/linux/mfd/wm8350/bl.h @@ -0,0 +1,33 @@ +/* + * bl.h -- Backlight Driver for Wolfson WM8350 PMIC + * + * Copyright 2009 Wolfson Microelectronics PLC + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __LINUX_MFD_WM8350_BL_H_ +#define __LINUX_MFD_WM8350_BL_H_ + +#include + +/* + * WM8350 Backlight platform data + */ +struct wm8350_bl_platform_data { + int isink; + int dcdc; + int voltage_ramp; + int retries; + int max_brightness; + int power; + int brightness; + int (*check_fb)(struct fb_info *); +}; + +#endif diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index d02d2c6e0cfe..8613fa6a6860 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -44,6 +44,12 @@ struct mmc_ext_csd { unsigned int sa_timeout; /* Units: 100ns */ unsigned int hs_max_dtr; unsigned int sectors; + unsigned int card_type; +#define MMC_DDR_MODE_MASK (0x3<<2) + unsigned char boot_info; + unsigned char boot_size_mult; + unsigned char boot_config; + unsigned char boot_bus_width; }; struct sd_scr { diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index f65913c9f5a4..e77d7541da3c 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -44,6 +44,7 @@ struct mmc_ios { #define MMC_BUS_WIDTH_1 0 #define MMC_BUS_WIDTH_4 2 #define MMC_BUS_WIDTH_8 3 +#define MMC_BUS_WIDTH_DDR 8 unsigned char timing; /* timing specification used */ @@ -155,6 +156,7 @@ struct mmc_host { #define MMC_CAP_DISABLE (1 << 7) /* Can the host be disabled */ #define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ +#define MMC_CAP_DATA_DDR (1 << 10) /* Can the host do ddr transfers */ mmc_pm_flag_t pm_caps; /* supported pm features */ diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index 8a49cbf0376d..139dadf4bbfd 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -251,12 +251,16 @@ struct _mmc_csd { * EXT_CSD fields */ +#define EXT_CSD_BOOT_BUS_WIDTH 177 /* R/W */ +#define EXT_CSD_BOOT_CONFIG 179 /* R/W */ #define EXT_CSD_BUS_WIDTH 183 /* R/W */ #define EXT_CSD_HS_TIMING 185 /* R/W */ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_REV 192 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ #define EXT_CSD_S_A_TIMEOUT 217 +#define EXT_CSD_BOOT_SIZE_MULT 226 /* RO, 1 bytes */ +#define EXT_CSD_BOOT_INFO 228 /* RO, 1 bytes */ /* * EXT_CSD field definitions @@ -273,6 +277,31 @@ struct _mmc_csd { #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +#define EXT_CSD_BUS_WIDTH_4_DDR 5 /* Card is in 4 bit ddr mode */ +#define EXT_CSD_BUS_WIDTH_8_DDR 6 /* Card is in 8 bit ddr mode */ + +#define EXT_CSD_BOOT_BUS_WIDTH_MASK (0x1F) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE_MASK (0x3 << 3) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE_SDR_NORMAL (0x0) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE_SDR_HIGH (0x1) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE_DDR (0x2) +#define EXT_CSD_BOOT_BUS_WIDTH_RST_WIDTH (1 << 2) +#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH_MASK (0x3) +#define EXT_CSD_BOOT_BUS_WIDTH_1_SDR_4_DDR (0x0) +#define EXT_CSD_BOOT_BUS_WIDTH_4_SDR_4_DDR (0x1) +#define EXT_CSD_BOOT_BUS_WIDTH_8_SDR_8_DDR (0x2) + +#define EXT_CSD_BOOT_ACK_ENABLE (0x1 << 6) +#define EXT_CSD_BOOT_PARTITION_ENABLE_MASK (0x7 << 3) +#define EXT_CSD_BOOT_PARTITION_DISABLE (0x0) +#define EXT_CSD_BOOT_PARTITION_PART1 (0x1 << 3) +#define EXT_CSD_BOOT_PARTITION_PART2 (0x2 << 3) +#define EXT_CSD_BOOT_PARTITION_USER (0x7 << 3) + +#define EXT_CSD_BOOT_PARTITION_ACCESS_MASK (0x7) +#define EXT_CSD_BOOT_PARTITION_ACCESS_DISABLE (0x0) +#define EXT_CSD_BOOT_PARTITION_ACCESS_PART1 (0x1) +#define EXT_CSD_BOOT_PARTITION_ACCESS_PART2 (0x2) /* * MMC_SWITCH access modes diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h index 34066e65fdeb..f38d4f0a5ae8 100644 --- a/include/linux/msdos_fs.h +++ b/include/linux/msdos_fs.h @@ -101,6 +101,7 @@ struct __fat_dirent { /* has used 0x72 ('r') in collision, so skip a few */ #define FAT_IOCTL_GET_ATTRIBUTES _IOR('r', 0x10, __u32) #define FAT_IOCTL_SET_ATTRIBUTES _IOW('r', 0x11, __u32) +#define VFAT_IOCTL_GET_VOLUME_ID _IOR('r', 0x12, __u32) struct fat_boot_sector { __u8 ignored[3]; /* Boot strap short or near jump */ @@ -138,6 +139,17 @@ struct fat_boot_fsinfo { __le32 reserved2[4]; }; +struct fat_boot_bsx { + __u8 drive; /* drive number */ + __u8 reserved1; + __u8 signature; /* extended boot signature */ + __u8 vol_id[4]; /* volume ID */ + __u8 vol_label[11]; /* volume label */ + __u8 type[8]; /* file system type */ +}; +#define FAT16_BSX_OFFSET 36 /* offset of fat_boot_bsx in FAT12 and FAT16 */ +#define FAT32_BSX_OFFSET 64 /* offset of fat_boot_bsx in FAT32 */ + struct msdos_dir_entry { __u8 name[MSDOS_NAME];/* name and extension */ __u8 attr; /* attribute bits */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index a81b185e23a7..3a470b1e60fe 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -53,8 +53,8 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ -#define NAND_MAX_OOBSIZE 256 -#define NAND_MAX_PAGESIZE 4096 +#define NAND_MAX_OOBSIZE (256 * NAND_MAX_CHIPS) +#define NAND_MAX_PAGESIZE (4096 * NAND_MAX_CHIPS) /* * Constants for hardware specific CLE/ALE/NCE function @@ -99,6 +99,14 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); #define NAND_CMD_RNDOUTSTART 0xE0 #define NAND_CMD_CACHEDPROG 0x15 +/* Extended commands for ONFI nand */ +#define NAND_CMD_READ_PARAMETER_PAGE 0xec +#define NAND_CMD_READ_UNIQUE_ID 0xed +#define NAND_CMD_GET_FEATURE 0xee +#define NAND_CMD_SET_FEATURE 0xef +#define NAND_CMD_RESET_LUN 0xfa +#define NAND_CMD_SYNC_RESET 0xfc + /* Extended commands for AG-AND device */ /* * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but @@ -334,6 +342,10 @@ struct nand_buffers { * @block_markbad: [REPLACEABLE] mark the block bad * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling * ALE/CLE/nCE. Also used to write command and address + * @init_size: [BOARDSPECIFIC] hardwarespecific funtion for setting + * mtd->oobsize, mtd->writesize and so on. + * @id_data contains the 8 bytes values of NAND_CMD_READID. + * Return with the bus width. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line * If set to NULL no access to ready/busy is available and the ready/busy information * is read from the chip status register @@ -388,6 +400,8 @@ struct nand_chip { int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); + int (*init_size)(struct mtd_info *mtd, + struct nand_chip *this, u8 *id_data); int (*dev_ready)(struct mtd_info *mtd); void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); @@ -446,6 +460,8 @@ struct nand_chip { #define NAND_MFR_HYNIX 0xad #define NAND_MFR_MICRON 0x2c #define NAND_MFR_AMD 0x01 +#define NAND_MFR_SANDISK 0x45 +#define NAND_MFR_INTEL 0x89 /** * struct nand_flash_dev - NAND Flash Device ID Structure @@ -489,6 +505,10 @@ extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt); extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, uint8_t * buf); +extern int nand_do_read_ops(struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops); +extern int nand_do_write_ops(struct mtd_info *mtd, loff_t to, + struct mtd_oob_ops *ops); /** * struct platform_nand_chip - chip level device structure diff --git a/include/linux/mxc_asrc.h b/include/linux/mxc_asrc.h new file mode 100644 index 000000000000..326cd20b2c30 --- /dev/null +++ b/include/linux/mxc_asrc.h @@ -0,0 +1,210 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mx35_asrc.h + * + * @brief MX35 Asynchronous Sample Rate Converter + * + * @ingroup ?? + */ + +#ifndef __MXC_ASRC_H__ +#define __MXC_ASRC_H__ + +#define ASRC_IOC_MAGIC 'C' + +#define ASRC_REQ_PAIR _IOWR(ASRC_IOC_MAGIC, 0, struct asrc_req) +#define ASRC_CONFIG_PAIR _IOWR(ASRC_IOC_MAGIC, 1, struct asrc_config) +#define ASRC_RELEASE_PAIR _IOW(ASRC_IOC_MAGIC, 2, enum asrc_pair_index) +#define ASRC_QUERYBUF _IOWR(ASRC_IOC_MAGIC, 3, struct asrc_buffer) +#define ASRC_Q_INBUF _IOW(ASRC_IOC_MAGIC, 4, struct asrc_buffer) +#define ASRC_DQ_INBUF _IOW(ASRC_IOC_MAGIC, 5, struct asrc_buffer) +#define ASRC_Q_OUTBUF _IOW(ASRC_IOC_MAGIC, 6, struct asrc_buffer) +#define ASRC_DQ_OUTBUF _IOW(ASRC_IOC_MAGIC, 7, struct asrc_buffer) +#define ASRC_START_CONV _IOW(ASRC_IOC_MAGIC, 8, enum asrc_pair_index) +#define ASRC_STOP_CONV _IOW(ASRC_IOC_MAGIC, 9, enum asrc_pair_index) +#define ASRC_STATUS _IOW(ASRC_IOC_MAGIC, 10, struct asrc_status_flags) +#define ASRC_FLUSH _IOW(ASRC_IOC_MAGIC, 11, enum asrc_pair_index) + +enum asrc_pair_index { + ASRC_PAIR_A, + ASRC_PAIR_B, + ASRC_PAIR_C +}; + +enum asrc_inclk { + INCLK_NONE = 0x03, + INCLK_ESAI_RX = 0x00, + INCLK_SSI1_RX = 0x01, + INCLK_SSI2_RX = 0x02, + INCLK_SPDIF_RX = 0x04, + INCLK_MLB_CLK = 0x05, + INCLK_ESAI_TX = 0x08, + INCLK_SSI1_TX = 0x09, + INCLK_SSI2_TX = 0x0a, + INCLK_SPDIF_TX = 0x0c, + INCLK_ASRCK1_CLK = 0x0f, +}; + +enum asrc_outclk { + OUTCLK_NONE = 0x03, + OUTCLK_ESAI_TX = 0x00, + OUTCLK_SSI1_TX = 0x01, + OUTCLK_SSI2_TX = 0x02, + OUTCLK_SPDIF_TX = 0x04, + OUTCLK_MLB_CLK = 0x05, + OUTCLK_ESAI_RX = 0x08, + OUTCLK_SSI1_RX = 0x09, + OUTCLK_SSI2_RX = 0x0a, + OUTCLK_SPDIF_RX = 0x0c, + OUTCLK_ASRCK1_CLK = 0x0f, +}; + +struct asrc_config { + enum asrc_pair_index pair; + unsigned int channel_num; + unsigned int buffer_num; + unsigned int dma_buffer_size; + unsigned int input_sample_rate; + unsigned int output_sample_rate; + unsigned int word_width; + enum asrc_inclk inclk; + enum asrc_outclk outclk; +}; + +struct asrc_pair { + unsigned int start_channel; + unsigned int chn_num; + unsigned int chn_max; + unsigned int active; + unsigned int overload_error; +}; + +struct asrc_req { + unsigned int chn_num; + enum asrc_pair_index index; +}; + +struct asrc_querybuf { + unsigned int buffer_index; + unsigned int input_length; + unsigned int output_length; + unsigned long input_offset; + unsigned long output_offset; +}; + +struct asrc_buffer { + unsigned int index; + unsigned int length; + int buf_valid; +}; + +struct asrc_status_flags { + enum asrc_pair_index index; + unsigned int overload_error; +}; + +#define ASRC_BUF_NA -35 /* ASRC DQ's buffer is NOT available */ +#define ASRC_BUF_AV 35 /* ASRC DQ's buffer is available */ +enum asrc_error_status { + ASRC_TASK_Q_OVERLOAD = 0x01, + ASRC_OUTPUT_TASK_OVERLOAD = 0x02, + ASRC_INPUT_TASK_OVERLOAD = 0x04, + ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08, + ASRC_INPUT_BUFFER_UNDERRUN = 0x10, +}; + +#ifdef __KERNEL__ + +#define ASRC_DMA_BUFFER_NUM 8 + +#define ASRC_ASRCTR_REG 0x00 +#define ASRC_ASRIER_REG 0x04 +#define ASRC_ASRCNCR_REG 0x0C +#define ASRC_ASRCFG_REG 0x10 +#define ASRC_ASRCSR_REG 0x14 +#define ASRC_ASRCDR1_REG 0x18 +#define ASRC_ASRCDR2_REG 0x1C +#define ASRC_ASRSTR_REG 0x20 +#define ASRC_ASRRA_REG 0x24 +#define ASRC_ASRRB_REG 0x28 +#define ASRC_ASRRC_REG 0x2C +#define ASRC_ASRPM1_REG 0x40 +#define ASRC_ASRPM2_REG 0x44 +#define ASRC_ASRPM3_REG 0x48 +#define ASRC_ASRPM4_REG 0x4C +#define ASRC_ASRPM5_REG 0x50 +#define ASRC_ASRTFR1 0x54 +#define ASRC_ASRCCR_REG 0x5C +#define ASRC_ASRDIA_REG 0x60 +#define ASRC_ASRDOA_REG 0x64 +#define ASRC_ASRDIB_REG 0x68 +#define ASRC_ASRDOB_REG 0x6C +#define ASRC_ASRDIC_REG 0x70 +#define ASRC_ASRDOC_REG 0x74 +#define ASRC_ASRIDRHA_REG 0x80 +#define ASRC_ASRIDRLA_REG 0x84 +#define ASRC_ASRIDRHB_REG 0x88 +#define ASRC_ASRIDRLB_REG 0x8C +#define ASRC_ASRIDRHC_REG 0x90 +#define ASRC_ASRIDRLC_REG 0x94 +#define ASRC_ASR76K_REG 0x98 +#define ASRC_ASR56K_REG 0x9C + +struct dma_block { + unsigned int index; + unsigned int length; + unsigned char *dma_vaddr; + dma_addr_t dma_paddr; + struct list_head queue; +}; + +struct asrc_pair_params { + enum asrc_pair_index index; + struct list_head input_queue; + struct list_head input_done_queue; + struct list_head output_queue; + struct list_head output_done_queue; + wait_queue_head_t input_wait_queue; + wait_queue_head_t output_wait_queue; + unsigned int input_counter; + unsigned int output_counter; + unsigned int input_queue_empty; + unsigned int output_queue_empty; + unsigned int input_dma_channel; + unsigned int output_dma_channel; + unsigned int input_buffer_size; + unsigned int output_buffer_size; + unsigned int buffer_num; + unsigned int pair_hold; + unsigned int asrc_active; + struct dma_block input_dma[ASRC_DMA_BUFFER_NUM]; + struct dma_block output_dma[ASRC_DMA_BUFFER_NUM]; + struct semaphore busy_lock; +}; + +struct asrc_data { + struct asrc_pair asrc_pair[3]; +}; + +extern int asrc_req_pair(int chn_num, enum asrc_pair_index *index); +extern void asrc_release_pair(enum asrc_pair_index index); +extern int asrc_config_pair(struct asrc_config *config); +extern void asrc_get_status(struct asrc_status_flags *flags); +extern void asrc_start_conv(enum asrc_pair_index index); +extern void asrc_stop_conv(enum asrc_pair_index index); + +#endif /* __kERNEL__ */ + +#endif /* __MXC_ASRC_H__ */ diff --git a/include/linux/mxc_mlb.h b/include/linux/mxc_mlb.h new file mode 100644 index 000000000000..5fcc41dd118e --- /dev/null +++ b/include/linux/mxc_mlb.h @@ -0,0 +1,51 @@ +/* + * mxc_mlb.h + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _MXC_MLB_H +#define _MXC_MLB_H + +/* define IOCTL command */ +#define MLB_SET_FPS _IOW('S', 0x10, unsigned int) +#define MLB_GET_VER _IOR('S', 0x11, unsigned long) +#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char) +/*! + * set channel address for each logical channel + * the MSB 16bits is for tx channel, the left LSB is for rx channel + */ +#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int) +#define MLB_CHAN_STARTUP _IO('S', 0x14) +#define MLB_CHAN_SHUTDOWN _IO('S', 0x15) +#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long) + +/*! + * MLB event define + */ +enum { + MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0, + MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1, + MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8, + MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9, + MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16, + MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17, + MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24, + MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25, +}; + +#ifdef __KERNEL__ +extern void gpio_mlb_active(void); +extern void gpio_mlb_inactive(void); +#endif + +#endif /* _MXC_MLB_H */ diff --git a/include/linux/mxc_pf.h b/include/linux/mxc_pf.h new file mode 100644 index 000000000000..cf8f35ec4abe --- /dev/null +++ b/include/linux/mxc_pf.h @@ -0,0 +1,125 @@ +/* + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @defgroup MXC_PF MPEG4/H.264 Post Filter Driver + */ +/*! + * @file arch-mxc/mxc_pf.h + * + * @brief MXC IPU MPEG4/H.264 Post-filtering driver + * + * User-level API for IPU Hardware MPEG4/H.264 Post-filtering. + * + * @ingroup MXC_PF + */ +#ifndef __INCLUDED_MXC_PF_H__ +#define __INCLUDED_MXC_PF_H__ + +#define PF_MAX_BUFFER_CNT 17 + +#define PF_WAIT_Y 0x0001 +#define PF_WAIT_U 0x0002 +#define PF_WAIT_V 0x0004 +#define PF_WAIT_ALL (PF_WAIT_Y|PF_WAIT_U|PF_WAIT_V) + +/*! + * Structure for Post Filter initialization parameters. + */ +typedef struct { + uint16_t pf_mode; /*!< Post filter operation mode */ + uint16_t width; /*!< Width of frame in pixels */ + uint16_t height; /*!< Height of frame in pixels */ + uint16_t stride; /*!< Stride of Y plane in pixels. Stride for U and V planes is half Y stride */ + uint32_t qp_size; + unsigned long qp_paddr; +} pf_init_params; + +/*! + * Structure for Post Filter buffer request parameters. + */ +typedef struct { + int count; /*!< Number of buffers requested */ + __u32 req_size; +} pf_reqbufs_params; + +/*! + * Structure for Post Filter buffer request parameters. + */ +typedef struct { + int index; + int size; /*!< Size of buffer allocated */ + __u32 offset; /*!< Buffer offset in driver memory. Set by QUERYBUF */ + __u32 y_offset; /*!< Optional starting relative offset of Y data + from beginning of buffer. Set to 0 to use default + calculated based on height and stride */ + __u32 u_offset; /*!< Optional starting relative offset of U data + from beginning of buffer. Set to 0 to use default + calculated based on height and stride */ + __u32 v_offset; /*!< Optional starting relative offset of V data + from beginning of buffer. Set to 0 to use default + calculated based on height and stride */ +} pf_buf; + +/*! + * Structure for Post Filter start parameters. + */ +typedef struct { + pf_buf in; /*!< Input buffer address and offsets */ + pf_buf out; /*!< Output buffer address and offsets */ + int qp_buf; + int wait; + uint32_t h264_pause_row; /*!< Row to pause at for H.264 mode. 0 to disable pause */ +} pf_start_params; + +/*! @name User Client Ioctl Interface */ +/*! @{ */ + +/*! + * IOCTL to Initialize the Post Filter. + */ +#define PF_IOCTL_INIT _IOW('F', 0x0, pf_init_params) + +/*! + * IOCTL to Uninitialize the Post Filter. + */ +#define PF_IOCTL_UNINIT _IO('F', 0x1) + +/*! + * IOCTL to set the buffer mode and allocate buffers if driver allocated. + */ +#define PF_IOCTL_REQBUFS _IOWR('F', 0x2, pf_reqbufs_params) + +/*! + * IOCTL to set the buffer mode and allocate buffers if driver allocated. + */ +#define PF_IOCTL_QUERYBUF _IOR('F', 0x2, pf_buf) + +/*! + * IOCTL to start post filtering on a frame of data. This ioctl may block until + * processing is done or return immediately. + */ +#define PF_IOCTL_START _IOWR('F', 0x3, pf_start_params) + +/*! + * IOCTL to resume post-filtering after an intra frame pause in H.264 mode. + */ +#define PF_IOCTL_RESUME _IOW('F', 0x4, int) + +/*! + * IOCTL to wait for post-filtering to complete. + */ +#define PF_IOCTL_WAIT _IOW('F', 0x5, int) +/*! @} */ + +#endif /* __INCLUDED_MXC_PF_H__ */ diff --git a/include/linux/mxc_scc2_driver.h b/include/linux/mxc_scc2_driver.h new file mode 100644 index 000000000000..fc8f055f66cf --- /dev/null +++ b/include/linux/mxc_scc2_driver.h @@ -0,0 +1,975 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef SCC_DRIVER_H +#define SCC_DRIVER_H + +/* + * NAMING CONVENTIONS + * ================== + * (A note to maintainers and other interested parties) + * + * Use scc_ or SCC_ prefix for 'high-level' interface routines and the types + * passed to those routines. Try to avoid #defines in these interfaces. + * + * Use SMN_ or SCM_ prefix for the #defines used with scc_read_register() and + * scc_write_register, or values passed/retrieved from those routines. + */ + +/*! @file mxc_scc2_driver.h + * + * @brief (Header file to use the SCC2 driver.) + * + * The SCC2 driver is available to other kernel modules directly. Secure + * Partition functionality is extended to users through the SHW API. Other + * functionality of the SCC2 is limited to kernel-space users. + * + * With the exception of #scc_monitor_security_failure(), all routines are + * 'synchronous', i.e. they will not return to their caller until the requested + * action is complete, or fails to complete. Some of these functions could + * take quite a while to perform, depending upon the request. + * + * Routines are provided to: + * @li trigger a security-violation alarm - #scc_set_sw_alarm() + * @li get configuration and version information - #scc_get_configuration() + * @li zeroize memory - #scc_zeroize_memories() + * @li Work with secure partitions: #scc_allocate_partition() + * #scc_engage_partition() #scc_diminish_permissions() + * #scc_release_partition() + * @li Encrypt or decrypt regions of data: #scc_encrypt_region() + * #scc_decrypt_region() + * @li monitor the Security Failure alarm - #scc_monitor_security_failure() + * @li stop monitoring Security Failure alarm - + * #scc_stop_monitoring_security_failure() + * @li write registers of the SCC - #scc_write_register() + * @li read registers of the SCC - #scc_read_register() + * + * The SCC2 encrypts and decrypts using Triple DES with an internally stored + * key. When the SCC2 is in Secure mode, it uses its secret, unique-per-chip + * key. When it is in Non-Secure mode, it uses a default key. This ensures + * that secrets stay secret if the SCC2 is not in Secure mode. + * + * Not all functions that could be provided in a 'high level' manner have been + * implemented. Among the missing are interfaces to the ASC/AIC components and + * the timer functions. These and other features must be accessed through + * #scc_read_register() and #scc_write_register(), using the @c \#define values + * provided. + * + * Here is a glossary of acronyms used in the SCC2 driver documentation: + * - CBC - Cipher Block Chaining. A method of performing a block cipher. + * Each block is encrypted using some part of the result of the previous + * block's encryption. It needs an 'initialization vector' to seed the + * operation. + * - ECB - Electronic Code Book. A method of performing a block cipher. + * With a given key, a given block will always encrypt to the same value. + * - DES - Data Encryption Standard. (8-byte) Block cipher algorithm which + * uses 56-bit keys. In SCC2, this key is constant and unique to the device. + * SCC uses the "triple DES" form of this algorithm. + * - AIC - Algorithm Integrity Checker. + * - ASC - Algorithm Sequence Checker. + * - SMN - Security Monitor. The part of the SCC2 responsible for monitoring + * for security problems and notifying the CPU and other PISA components. + * - SCM - Secure Memory. The part of the SCC2 which handles the cryptography. + * - SCC - Security Controller. Central security mechanism for PISA. + * - PISA - Platform-Independent Security Architecture. + */ + +/* Temporarily define compile-time flags to make Doxygen happy. */ +#ifdef DOXYGEN_HACK +/** @defgroup scccompileflags SCC Driver compile-time flags + * + * These preprocessor flags should be set, if desired, in a makefile so + * that they show up on the compiler command line. + */ +/** @addtogroup scccompileflags */ + +/** @{ */ +/** + * Compile-time flag to change @ref smnregs and @ref scmregs + * offset values for the SCC's implementation on the MX.21 board. + * + * This must also be set properly for any code which calls the + * scc_read_register() or scc_write_register() functions or references the + * register offsets. + */ +#define TAHITI +/** @} */ +#undef TAHITI + +#endif /* DOXYGEN_HACK */ + +/*! Major Version of the driver. Used for + scc_configuration->driver_major_version */ +#define SCC_DRIVER_MAJOR_VERSION 2 +/*! Old Minor Version of the driver. */ +#define SCC_DRIVER_MINOR_VERSION_0 0 +/*! Minor Version of the driver. Used for + scc_configuration->driver_minor_version */ +#define SCC_DRIVER_MINOR_VERSION_2 2 + + +/*! + * Interrupt line number of SCM interrupt. + */ +#define INT_SCC_SCM MXC_INT_SCC_SCM + +/*! + * Interrupt line number of the SMN interrupt. + */ +#define INT_SCC_SMN MXC_INT_SCC_SMN + +/** + * @typedef scc_return_t + */ +/** Common status return values from SCC driver functions. */ + typedef enum scc_return_t { + SCC_RET_OK = 0, /**< Function succeeded */ + SCC_RET_FAIL, /**< Non-specific failure */ + SCC_RET_VERIFICATION_FAILED, + /**< Decrypt validation failed */ + SCC_RET_TOO_MANY_FUNCTIONS, + /**< At maximum registered functions */ + SCC_RET_BUSY, /**< SCC is busy and cannot handle request */ + /**< Encryption or decryption failed because@c count_out_bytes + says that @c data_out is too small to hold the value. */ + SCC_RET_INSUFFICIENT_SPACE, + } scc_return_t; + +/** + * @typedef scc_partition_status_t + */ +/** Partition status information. */ + typedef enum scc_partition_status_t { + SCC_PART_S_UNUSABLE, + /**< Partition not implemented */ + SCC_PART_S_UNAVAILABLE, + /**< Partition owned by other host */ + SCC_PART_S_AVAILABLE, + /**< Partition available */ + SCC_PART_S_ALLOCATED, + /**< Partition owned by host but not engaged*/ + SCC_PART_S_ENGAGED, + /**< Partition owned by host and engaged */ + } scc_partition_status_t; + +/** + * Configuration information about SCC and the driver. + * + * This struct/typedef contains information from the SCC and the driver to + * allow the user of the driver to determine the size of the SCC's memories and + * the version of the SCC and the driver. + */ + typedef struct scc_config_t { + int driver_major_version; + /**< Major version of the SCC driver code */ + int driver_minor_version; + /**< Minor version of the SCC driver code */ + int scm_version; /**< Version from SCM Configuration register */ + int smn_version; /**< Version from SMN Status register */ + /**< Number of bytes per block of RAM; also + block size of the crypto algorithm. */ + int block_size_bytes; + int partition_size_bytes; + /**< Number of bytes in each partition */ + int partition_count; + /**< Number of partitions on this platform */ + } scc_config_t; + +/** + * @typedef scc_enc_dec_t + */ +/** + * Determine whether SCC will run its cryptographic + * function as an encryption or decryption. + */ + typedef enum scc_enc_dec_t { + SCC_ENCRYPT, /**< Encrypt (from Red to Black) */ + SCC_DECRYPT /**< Decrypt (from Black to Red) */ + } scc_enc_dec_t; + +/** + * @typedef scc_verify_t + */ +/** + * Tell the driver whether it is responsible for verifying the integrity of a + * secret. During an encryption, using other than #SCC_VERIFY_MODE_NONE will + * cause a check value to be generated and appended to the plaintext before + * encryption. During decryption, the check value will be verified after + * decryption, and then stripped from the message. + */ + typedef enum scc_verify_t { + /** No verification value added or checked. Input plaintext data must be + * be a multiple of the blocksize (#scc_get_configuration()). */ + SCC_VERIFY_MODE_NONE, + /** Driver will generate/validate a 2-byte CCITT CRC. Input plaintext + will be padded to a multiple of the blocksize, adding 3-10 bytes + to the resulting output ciphertext. Upon decryption, this padding + will be stripped, and the CRC will be verified. */ + SCC_VERIFY_MODE_CCITT_CRC + } scc_verify_t; + +/** + * @typedef scc_cypher_mode_t + */ +/** + * Select the cypher mode to use for partition cover/uncover operations. + */ + + typedef enum scc_cypher_mode_t { + SCC_CYPHER_MODE_ECB = 1, + /**< ECB mode */ + SCC_CYPHER_MODE_CBC = 2, + /**< CBC mode */ + } scc_cypher_mode_t; + +/** + * Allocate a partition of secure memory + * + * @param smid_value Value to use for the SMID register. Must be 0 for + * kernel mode ownership. + * @param[out] part_no (If successful) Assigned partition number. + * @param[out] part_base Kernel virtual address of the partition. + * @param[out] part_phys Physical address of the partition. + * + * @return SCC_RET_OK if successful. + */ + extern scc_return_t + scc_allocate_partition(uint32_t smid_value, + int *part_no, + void **part_base, uint32_t *part_phys); + +/* Note: This function has to be run in the same context (userspace or kernel + * mode) as the process that will be using the partition. Because the SCC2 API + * is not accessible in user mode, this function is also provided as a macro in + * in fsl_shw.h. Kernel-mode users that include this file are able to use this + * version of the function without having to include the whole SHW API. If the + * macro definition was defined before we got here, un-define it so this + * version will be used instead. + */ + +#ifdef scc_engage_partition +#undef scc_engage_partition +#endif + +/** + * Engage partition of secure memory + * + * @param part_base (kernel) Virtual + * @param UMID NULL, or 16-byte UMID for partition security + * @param permissions ORed values of the type SCM_PERM_* which will be used as + * initial partition permissions. SHW API users should use + * the FSL_PERM_* definitions instead. + * + * @return SCC_RET_OK if successful. + */ + extern scc_return_t + scc_engage_partition(void *part_base, + const uint8_t *UMID, uint32_t permissions); + +/** + * Release a partition of secure memory + * + * @param part_base Kernel virtual address of the partition to be released. + * + * @return SCC_RET_OK if successful. + */ + extern scc_return_t scc_release_partition(void *part_base); + +/** + * Diminish the permissions on a partition of secure memory + * + * @param part_base Kernel virtual address of the partition. + * + * @param permissions ORed values of the type SCM_PERM_* which will be used as + * initial partition permissions. SHW API users should use + * the FSL_PERM_* definitions instead. + * + * @return SCC_RET_OK if successful. + */ + extern scc_return_t + scc_diminish_permissions(void *part_base, uint32_t permissions); + +/** + * Query the status of a partition of secure memory + * + * @param part_base Kernel virtual address of the partition. + * + * @return SCC_RET_OK if successful. + */ + extern scc_partition_status_t scc_partition_status(void *part_base); + +/** + * Calculate the physical address from the kernel virtual address. + */ + extern uint32_t scc_virt_to_phys(void *address); +/*scc_return_t +scc_verify_slot_access(uint64_t owner_id, uint32_t slot, uint32_t access_len);*/ + + +/** + * Encrypt a region of secure memory. + * + * @param part_base Kernel virtual address of the partition. + * @param offset_bytes Offset from the start of the partition to the plaintext + * data. + * @param byte_count Length of the region (octets). + * @param black_data Physical location to store the encrypted data. + * @param IV Value to use for the Initialization Vector. + * @param cypher_mode Cyphering mode to use, specified by type + * #scc_cypher_mode_t + * + * @return SCC_RET_OK if successful. + */ + extern scc_return_t + scc_encrypt_region(uint32_t part_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t *black_data, + uint32_t *IV, scc_cypher_mode_t cypher_mode); + +/** + * Decrypt a region into secure memory + * + * @param part_base Kernel virtual address of the partition. + * @param offset_bytes Offset from the start of the partition to store the + * plaintext data. + * @param byte_count Length of the region (octets). + * @param black_data Physical location of the encrypted data. + * @param IV Value to use for the Initialization Vector. + * @param cypher_mode Cyphering mode to use, specified by type + * #scc_cypher_mode_t + * + * @return SCC_RET_OK if successful. + */ + extern scc_return_t + scc_decrypt_region(uint32_t part_base, uint32_t offset_bytes, + uint32_t byte_count, uint8_t *black_data, + uint32_t *IV, scc_cypher_mode_t cypher_mode); + +/** + * Retrieve configuration information from the SCC. + * + * This function always succeeds. + * + * @return A pointer to the configuration information. This is a pointer to + * static memory and must not be freed. The values never change, and + * the return value will never be null. + */ + extern scc_config_t *scc_get_configuration(void); + +/** + * Zeroize Red and Black memories of the SCC. This will start the Zeroizing + * process. The routine will return when the memories have zeroized or failed + * to do so. The driver will poll waiting for this to occur, so this + * routine must not be called from interrupt level. Some future version of + * driver may elect instead to sleep. + * + * @return 0 or error if initialization fails. + */ + extern scc_return_t scc_zeroize_memories(void); + +/** + * Signal a software alarm to the SCC. This will take the SCC and other PISA + * parts out of Secure mode and into Security Failure mode. The SCC will stay + * in failed mode until a reboot. + * + * @internal + * If the SCC is not already in fail state, simply write the + * #SMN_COMMAND_SET_SOFTWARE_ALARM bit in #SMN_COMMAND_REG. Since there is no + * reason to wait for the interrupt to bounce back, simply act as though + * one did. + */ + extern void scc_set_sw_alarm(void); + +/** + * This routine will register a function to be called should a Security Failure + * be signalled by the SCC (Security Monitor). + * + * The callback function may be called from interrupt level, it may be called + * from some process' task. It should therefore not take a long time to + * perform its operation, and it may not sleep. + * + * @param callback_func Function pointer to routine which will receive + * notification of the security failure. + * @return 0 if function was successfully registered, non-zero on + * failure. See #scc_return_t. + * + * @internal + * There is a fixed global static array which keeps track of the requests to + * monitor the failure. + * + * Add @c callback_func to the first empty slot in #scc_callbacks[]. If there + * is no room, return #SCC_RET_TOO_MANY_FUNCTIONS. + */ + extern scc_return_t scc_monitor_security_failure(void + callback_func(void)); + +/** + * This routine will deregister a function previously registered with + * #scc_monitor_security_failure(). + * + * @param callback_func Function pointer to routine previously registered with + * #scc_stop_monitoring_security_failure(). + */ + extern void scc_stop_monitoring_security_failure(void + callback_func(void)); + +/** + * Read value from an SCC register. + * The offset will be checked for validity (range) as well as whether it is + * accessible (e.g. not busy, not in failed state) at the time of the call. + * + * @param[in] register_offset The (byte) offset within the SCC block + * of the register to be queried. See + * @ref scmregs and @ref smnregs. + * @param[out] value Pointer to where value from the register + * should be placed. + * @return 0 if OK, non-zero on error. See #scc_return_t. + * + * @internal + * Verify that the register_offset is a) valid, b) refers to a readable + * register, and c) the SCC is in a state which would allow a read of this + * register. + */ + extern scc_return_t scc_read_register(int register_offset, + uint32_t *value); + +/** + * Write a new value into an SCC register. + * The offset will be checked for validity (range) as well as whether it is + * accessible (e.g. not busy, not in failed state) at the time of the call. + * + * @param[in] register_offset The (byte) offset within the SCC block + * of the register to be modified. See + * @ref scmregs and @ref smnregs + * @param[in] value The value to store into the register. + * @return 0 if OK, non-zero on error. See #scc_return_t. + * + * @internal + * Verify that the register_offset is a) valid, b) refers to a writeable + * register, and c) the SCC is in a state which would allow a write to this + * register. + */ + extern scc_return_t scc_write_register(int register_offset, + uint32_t value); + +/** + * @defgroup scmregs SCM Registers + * + * These values are offsets into the SCC for the Secure Memory + * (SCM) registers. They are used in the @c register_offset parameter of + * #scc_read_register() and #scc_write_register(). + */ +/** @addtogroup scmregs */ +/** @{ */ +/** Offset of SCM Version ID Register */ +#define SCM_VERSION_REG 0x000 +/** Offset of SCM Interrupt Control Register */ +#define SCM_INT_CTL_REG 0x008 +/** Offset of SCM Status Register */ +#define SCM_STATUS_REG 0x00c +/** Offset of SCM Error Status Register */ +#define SCM_ERR_STATUS_REG 0x010 +/** Offset of SCM Fault Address Register */ +#define SCM_FAULT_ADR_REG 0x014 +/** Offset of SCM Partition Owners Register */ +#define SCM_PART_OWNERS_REG 0x018 +/** Offset of SCM Partitions Engaged Register */ +#define SCM_PART_ENGAGED_REG 0x01c +/** Offset of SCM Unique Number 0 Register */ +#define SCM_UNIQUE_ID0_REG 0x020 +/** Offset of SCM Unique Number 1 Register */ +#define SCM_UNIQUE_ID1_REG 0x024 +/** Offset of SCM Unique Number 2 Register */ +#define SCM_UNIQUE_ID2_REG 0x028 +/** Offset of SCM Unique Number 3 Register */ +#define SCM_UNIQUE_ID3_REG 0x02c +/** Offset of SCM Zeroize Command Register */ +#define SCM_ZCMD_REG 0x050 +/** Offset of SCM Cipher Command Register */ +#define SCM_CCMD_REG 0x054 +/** Offset of SCM Cipher Black RAM Start Address Register */ +#define SCM_C_BLACK_ST_REG 0x058 +/** Offset of SCM Internal Debug Register */ +#define SCM_DBG_STATUS_REG 0x05c +/** Offset of SCM Cipher IV 0 Register */ +#define SCM_AES_CBC_IV0_REG 0x060 +/** Offset of SCM Cipher IV 1 Register */ +#define SCM_AES_CBC_IV1_REG 0x064 +/** Offset of SCM Cipher IV 2 Register */ +#define SCM_AES_CBC_IV2_REG 0x068 +/** Offset of SCM Cipher IV 3 Register */ +#define SCM_AES_CBC_IV3_REG 0x06c +/** Offset of SCM SMID Partition 0 Register */ +#define SCM_SMID0_REG 0x080 +/** Offset of SCM Partition 0 Access Permissions Register */ +#define SCM_ACC0_REG 0x084 +/** Offset of SCM SMID Partition 1 Register */ +#define SCM_SMID1_REG 0x088 +/** Offset of SCM Partition 1 Access Permissions Register */ +#define SCM_ACC1_REG 0x08c +/** Offset of SCM SMID Partition 2 Register */ +#define SCM_SMID2_REG 0x090 +/** Offset of SCM Partition 2 Access Permissions Register */ +#define SCM_ACC2_REG 0x094 +/** Offset of SCM SMID Partition 3 Register */ +#define SCM_SMID3_REG 0x098 +/** Offset of SCM Partition 3 Access Permissions Register */ +#define SCM_ACC3_REG 0x09c +/** Offset of SCM SMID Partition 4 Register */ +#define SCM_SMID4_REG 0x0a0 +/** Offset of SCM Partition 4 Access Permissions Register */ +#define SCM_ACC4_REG 0x0a4 +/** Offset of SCM SMID Partition 5 Register */ +#define SCM_SMID5_REG 0x0a8 +/** Offset of SCM Partition 5 Access Permissions Register */ +#define SCM_ACC5_REG 0x0ac +/** Offset of SCM SMID Partition 6 Register */ +#define SCM_SMID6_REG 0x0b0 +/** Offset of SCM Partition 6 Access Permissions Register */ +#define SCM_ACC6_REG 0x0b4 +/** Offset of SCM SMID Partition 7 Register */ +#define SCM_SMID7_REG 0x0b8 +/** Offset of SCM Partition 7 Access Permissions Register */ +#define SCM_ACC7_REG 0x0bc +/** Offset of SCM SMID Partition 8 Register */ +#define SCM_SMID8_REG 0x0c0 +/** Offset of SCM Partition 8 Access Permissions Register */ +#define SCM_ACC8_REG 0x0c4 +/** Offset of SCM SMID Partition 9 Register */ +#define SCM_SMID9_REG 0x0c8 +/** Offset of SCM Partition 9 Access Permissions Register */ +#define SCM_ACC9_REG 0x0cc +/** Offset of SCM SMID Partition 10 Register */ +#define SCM_SMID10_REG 0x0d0 +/** Offset of SCM Partition 10 Access Permissions Register */ +#define SCM_ACC10_REG 0x0d4 +/** Offset of SCM SMID Partition 11 Register */ +#define SCM_SMID11_REG 0x0d8 +/** Offset of SCM Partition 11 Access Permissions Register */ +#define SCM_ACC11_REG 0x0dc +/** Offset of SCM SMID Partition 12 Register */ +#define SCM_SMID12_REG 0x0e0 +/** Offset of SCM Partition 12 Access Permissions Register */ +#define SCM_ACC12_REG 0x0e4 +/** Offset of SCM SMID Partition 13 Register */ +#define SCM_SMID13_REG 0x0e8 +/** Offset of SCM Partition 13 Access Permissions Register */ +#define SCM_ACC13_REG 0x0ec +/** Offset of SCM SMID Partition 14 Register */ +#define SCM_SMID14_REG 0x0f0 +/** Offset of SCM Partition 14 Access Permissions Register */ +#define SCM_ACC14_REG 0x0f4 +/** Offset of SCM SMID Partition 15 Register */ +#define SCM_SMID15_REG 0x0f8 +/** Offset of SCM Partition 15 Access Permissions Register */ +#define SCM_ACC15_REG 0x0fc +/** @} */ + +/** Number of bytes of register space for the SCM. */ +#define SCM_REG_BANK_SIZE 0x100 + +/** Number of bytes of register space for the SCM. */ +#define SCM_REG_BANK_SIZE 0x100 + +/** Offset of the SMN registers */ +#define SMN_ADDR_OFFSET 0x100 + +/** + * @defgroup smnregs SMN Registers + * + * These values are offsets into the SCC for the Security Monitor + * (SMN) registers. They are used in the @c register_offset parameter of the + * #scc_read_register() and #scc_write_register(). + */ +/** @addtogroup smnregs */ +/** @{ */ +/** Offset of SMN Status Register */ +#define SMN_STATUS_REG (SMN_ADDR_OFFSET+0x00000000) +/** Offset of SMH Command Register */ +#define SMN_COMMAND_REG (SMN_ADDR_OFFSET+0x00000004) +/** Offset of SMH Sequence Start Register */ +#define SMN_SEQ_START_REG (SMN_ADDR_OFFSET+0x00000008) +/** Offset of SMH Sequence End Register */ +#define SMN_SEQ_END_REG (SMN_ADDR_OFFSET+0x0000000c) +/** Offset of SMH Sequence Check Register */ +#define SMN_SEQ_CHECK_REG (SMN_ADDR_OFFSET+0x00000010) +/** Offset of SMH BitBank Count Register */ +#define SMN_BB_CNT_REG (SMN_ADDR_OFFSET+0x00000014) +/** Offset of SMH BitBank Increment Register */ +#define SMN_BB_INC_REG (SMN_ADDR_OFFSET+0x00000018) +/** Offset of SMH BitBank Decrement Register */ +#define SMN_BB_DEC_REG (SMN_ADDR_OFFSET+0x0000001c) +/** Offset of SMH Compare Register */ +#define SMN_COMPARE_REG (SMN_ADDR_OFFSET+0x00000020) +/** Offset of SMH Plaintext Check Register */ +#define SMN_PT_CHK_REG (SMN_ADDR_OFFSET+0x00000024) +/** Offset of SMH Ciphertext Check Register */ +#define SMN_CT_CHK_REG (SMN_ADDR_OFFSET+0x00000028) +/** Offset of SMH Timer Initial Value Register */ +#define SMN_TIMER_IV_REG (SMN_ADDR_OFFSET+0x0000002c) +/** Offset of SMH Timer Control Register */ +#define SMN_TIMER_CTL_REG (SMN_ADDR_OFFSET+0x00000030) +/** Offset of SMH Security Violation Register */ +#define SMN_SEC_VIO_REG (SMN_ADDR_OFFSET+0x00000034) +/** Offset of SMH Timer Register */ +#define SMN_TIMER_REG (SMN_ADDR_OFFSET+0x00000038) +/** Offset of SMH High-Assurance Control Register */ +#define SMN_HAC_REG (SMN_ADDR_OFFSET+0x0000003c) +/** Number of bytes allocated to the SMN registers */ +#define SMN_REG_BANK_SIZE 0x40 +/** @} */ + +/** Number of bytes of total register space for the SCC. */ +#define SCC_ADDRESS_RANGE (SMN_ADDR_OFFSET + SMN_REG_BANK_SIZE) + +/** + * @defgroup smnstatusregdefs SMN Status Register definitions (SMN_STATUS) + */ +/** @addtogroup smnstatusregdefs */ +/** @{ */ +/** SMN version id. */ +#define SMN_STATUS_VERSION_ID_MASK 0xfc000000 +/** number of bits to shift #SMN_STATUS_VERSION_ID_MASK to get it to LSB */ +#define SMN_STATUS_VERSION_ID_SHIFT 28 +/** Illegal bus master access attempted. */ +#define SMN_STATUS_ILLEGAL_MASTER 0x01000000 +/** Scan mode entered/exited since last reset. */ +#define SMN_STATUS_SCAN_EXIT 0x00800000 +/** Some security peripheral is initializing */ +#define SMN_STATUS_PERIP_INIT 0x00010000 +/** Internal error detected in SMN. */ +#define SMN_STATUS_SMN_ERROR 0x00004000 +/** SMN has an outstanding interrupt. */ +#define SMN_STATUS_SMN_STATUS_IRQ 0x00004000 +/** Software Alarm was triggered. */ +#define SMN_STATUS_SOFTWARE_ALARM 0x00002000 +/** Timer has expired. */ +#define SMN_STATUS_TIMER_ERROR 0x00001000 +/** Plaintext/Ciphertext compare failed. */ +#define SMN_STATUS_PC_ERROR 0x00000800 +/** Bit Bank detected overflow or underflow */ +#define SMN_STATUS_BITBANK_ERROR 0x00000400 +/** Algorithm Sequence Check failed. */ +#define SMN_STATUS_ASC_ERROR 0x00000200 +/** Security Policy Block detected error. */ +#define SMN_STATUS_SECURITY_POLICY_ERROR 0x00000100 +/** Security Violation Active error. */ +#define SMN_STATUS_SEC_VIO_ACTIVE_ERROR 0x00000080 +/** Processor booted from internal ROM. */ +#define SMN_STATUS_INTERNAL_BOOT 0x00000020 +/** SMN's internal state. */ +#define SMN_STATUS_STATE_MASK 0x0000001F +/** Number of bits to shift #SMN_STATUS_STATE_MASK to get it to LSB. */ +#define SMN_STATUS_STATE_SHIFT 0 +/** @} */ + +/** + * @defgroup sccscmstates SMN Model Secure State Controller States (SMN_STATE_MASK) + */ +/** @addtogroup sccscmstates */ +/** @{ */ +/** This is the first state of the SMN after power-on reset */ +#define SMN_STATE_START 0x0 +/** The SMN is zeroizing its RAM during reset */ +#define SMN_STATE_ZEROIZE_RAM 0x5 +/** SMN has passed internal checks, and is waiting for Software check-in */ +#define SMN_STATE_HEALTH_CHECK 0x6 +/** Fatal Security Violation. SMN is locked, SCM is inoperative. */ +#define SMN_STATE_FAIL 0x9 +/** SCC is in secure state. SCM is using secret key. */ +#define SMN_STATE_SECURE 0xA +/** Due to non-fatal error, device is not secure. SCM is using default key. */ +#define SMN_STATE_NON_SECURE 0xC +/** @} */ + +/** @{ */ +/** SCM Status bit: Key Status is Default Key in Use */ +#define SCM_STATUS_KST_DEFAULT_KEY 0x80000000 +/** SCM Status bit: Key Status is (reserved) */ +#define SCM_STATUS_KST_RESERVED1 0x40000000 +/** SCM Status bit: Key status is Wrong Key */ +#define SCM_STATUS_KST_WRONG_KEY 0x20000000 +/** SCM Status bit: Bad Key detected */ +#define SCM_STATUS_KST_BAD_KEY 0x10000000 +/** SCM Status bit: Error has occurred */ +#define SCM_STATUS_ERR 0x00008000 +/** SCM Status bit: Monitor State is Failed */ +#define SCM_STATUS_MSS_FAIL 0x00004000 +/** SCM Status bit: Monitor State is Secure */ +#define SCM_STATUS_MSS_SEC 0x00002000 +/** SCM Status bit: Secure Storage is Failed */ +#define SCM_STATUS_RSS_FAIL 0x00000400 +/** SCM Status bit: Secure Storage is Secure */ +#define SCM_STATUS_RSS_SEC 0x00000200 +/** SCM Status bit: Secure Storage is Initializing */ +#define SCM_STATUS_RSS_INIT 0x00000100 +/** SCM Status bit: Unique Number Valid */ +#define SCM_STATUS_UNV 0x00000080 +/** SCM Status bit: Big Endian mode */ +#define SCM_STATUS_BIG 0x00000040 +/** SCM Status bit: Using Secret Key */ +#define SCM_STATUS_USK 0x00000020 +/** SCM Status bit: Ram is being blocked */ +#define SCM_STATUS_BAR 0x00000010 +/** Bit mask of SRS */ +#define SCM_STATUS_SRS_MASK 0x0000000F +/** Number of bits to shift SRS to/from MSb */ +#define SCM_STATUS_SRS_SHIFT 0 +/** @} */ + +#define SCM_STATUS_SRS_RESET 0x0 /**< Reset, Zeroise All */ +#define SCM_STATUS_SRS_READY 0x1 /**< All Ready */ +#define SCM_STATUS_SRS_ZBUSY 0x2 /**< Zeroize Busy (Partition Only) */ +#define SCM_STATUS_SRS_CBUSY 0x3 /**< Cipher Busy */ +#define SCM_STATUS_SRS_ABUSY 0x4 /**< All Busy */ +#define SCM_STATUS_SRS_ZDONE 0x5 /**< Zeroize Done, Cipher Ready */ +#define SCM_STATUS_SRS_CDONE 0x6 /**< Cipher Done, Zeroize Ready */ +#define SCM_STATUS_SRS_ZDONE2 0x7 /**< Zeroize Done, Cipher Busy */ +#define SCM_STATUS_SRS_CDONE2 0x8 /**< Cipher Done, Zeroize Busy */ +#define SCM_STATUS_SRS_ADONE 0xD /**< All Done */ +#define SCM_STATUS_SRS_FAIL 0xF /**< Fail State */ + + +/* Format of the SCM VERSION ID REGISTER */ +#define SCM_VER_BPP_MASK 0xFF000000 /**< Bytes Per Partition Mask */ +#define SCM_VER_BPP_SHIFT 24 /**< Bytes Per Partition Shift */ +#define SCM_VER_BPCB_MASK 0x001F0000 /**< Bytes Per Cipher Block Mask */ +#define SCM_VER_BPCB_SHIFT 16 /**< Bytes Per Cipher Block Shift */ +#define SCM_VER_NP_MASK 0x0000F000 /**< Number of Partitions Mask */ +#define SCM_VER_NP_SHIFT 12 /**< Number of Partitions Shift */ +#define SCM_VER_MAJ_MASK 0x00000F00 /**< Major Version Mask */ +#define SCM_VER_MAJ_SHIFT 8 /**< Major Version Shift */ +#define SCM_VER_MIN_MASK 0x000000FF /**< Minor Version Mask */ +#define SCM_VER_MIN_SHIFT 0 /**< Minor Version Shift */ + +/**< SCC Hardware version supported by this driver */ +#define SCM_MAJOR_VERSION_2 2 + +/* Format of the SCM ERROR STATUS REGISTER */ +#define SCM_ERRSTAT_MID_MASK 0x00F00000 /**< Master ID Mask */ +#define SCM_ERRSTAT_MID_SHIFT 20 /**< Master ID Shift */ +#define SCM_ERRSTAT_ILM 0x00080000 /**< Illegal Master */ +#define SCM_ERRSTAT_SUP 0x00008000 /**< Supervisor Access */ +#define SCM_ERRSTAT_ERC_MASK 0x00000F00 /**< Error Code Mask */ +#define SCM_ERRSTAT_ERC_SHIFT 8 /**< Error Code Shift */ +#define SCM_ERRSTAT_SMS_MASK 0x000000F0 /**< Secure Monitor State Mask */ +#define SCM_ERRSTAT_SMS_SHIFT 4 /**< Secure Monitor State Shift */ +#define SCM_ERRSTAT_SRS_MASK 0x0000000F /**< Secure Ram State Mask */ +#define SCM_ERRSTAT_SRS_SHIFT 0 /**< Secure Ram State Shift */ + +/* SCM ERROR STATUS REGISTER ERROR CODES */ +#define SCM_ERCD_UNK_ADDR 0x1 /**< Unknown Address */ +#define SCM_ERCD_UNK_CMD 0x2 /**< Unknown Command */ +#define SCM_ERCD_READ_PERM 0x3 /**< Read Permission Error */ +#define SCM_ERCD_WRITE_PERM 0x4 /**< Write Permission Error */ +#define SCM_ERCD_DMA_ERROR 0x5 /**< DMA Error */ +#define SCM_ERCD_BLK_OVFL 0x6 /**< Encryption Block Length Overflow */ +#define SCM_ERCD_NO_KEY 0x7 /**< Key Not Engaged */ +#define SCM_ERCD_ZRZ_OVFL 0x8 /**< Zeroize Command Queue Overflow */ +#define SCM_ERCD_CPHR_OVFL 0x9 /**< Cipher Command Queue Overflow */ +#define SCM_ERCD_PROC_INTR 0xA /**< Process Interrupted */ +#define SCM_ERCD_WRNG_KEY 0xB /**< Wrong Key */ +#define SCM_ERCD_DEVICE_BUSY 0xC /**< Device Busy */ +#define SCM_ERCD_UNALGN_ADDR 0xD /**< DMA Unaligned Address */ + +/* Format of the CIPHER COMMAND REGISTER */ +#define SCM_CCMD_LENGTH_MASK 0xFFF00000 /**< Cipher Length Mask */ +#define SCM_CCMD_LENGTH_SHIFT 20 /**< Cipher Length Shift */ +#define SCM_CCMD_OFFSET_MASK 0x000FFF00 /**< Block Offset Mask */ +#define SCM_CCMD_OFFSET_SHIFT 8 /**< Block Offset Shift */ +#define SCM_CCMD_PART_MASK 0x000000F0 /**< Partition Number Mask */ +#define SCM_CCMD_PART_SHIFT 4 /**< Partition Number Shift */ +#define SCM_CCMD_CCMD_MASK 0x0000000F /**< Cipher Command Mask */ +#define SCM_CCMD_CCMD_SHIFT 0 /**< Cipher Command Shift */ + +/* Values for SCM_CCMD_CCMD field */ +#define SCM_CCMD_AES_DEC_ECB 1 /**< Decrypt without Chaining (ECB) */ +#define SCM_CCMD_AES_ENC_ECB 3 /**< Encrypt without Chaining (ECB) */ +#define SCM_CCMD_AES_DEC_CBC 5 /**< Decrypt with Chaining (CBC) */ +#define SCM_CCMD_AES_ENC_CBC 7 /**< Encrypt with Chaining (CBC) */ + +#define SCM_CCMD_AES 1 /**< Use AES Mode */ +#define SCM_CCMD_DEC 0 /**< Decrypt */ +#define SCM_CCMD_ENC 2 /**< Encrypt */ +#define SCM_CCMD_ECB 0 /**< Perform operation without chaining (ECB) */ +#define SCM_CCMD_CBC 4 /**< Perform operation with chaining (CBC) */ + +/* Format of the ZEROIZE COMMAND REGISTER */ +#define SCM_ZCMD_PART_MASK 0x000000F0 /**< Target Partition Mask */ +#define SCM_ZCMD_PART_SHIFT 4 /**< Target Partition Shift */ +#define SCM_ZCMD_CCMD_MASK 0x0000000F /**< Zeroize Command Mask */ +#define SCM_ZCMD_CCMD_SHIFT 0 /**< Zeroize Command Shift */ + +/* MASTER ACCESS PERMISSIONS REGISTER */ +/* Note that API users should use the FSL_PERM_ defines instead of these */ +/** SCM Access Permission: Do not zeroize/deallocate partition + on SMN Fail state */ +#define SCM_PERM_NO_ZEROIZE 0x10000000 +/** SCM Access Permission: Ignore Supervisor/User mode + in permission determination */ +#define SCM_PERM_HD_SUP_DISABLE 0x00000800 +/** SCM Access Permission: Allow Read Access to Host Domain */ +#define SCM_PERM_HD_READ 0x00000400 +/** SCM Access Permission: Allow Write Access to Host Domain */ +#define SCM_PERM_HD_WRITE 0x00000200 +/** SCM Access Permission: Allow Execute Access to Host Domain */ +#define SCM_PERM_HD_EXECUTE 0x00000100 +/** SCM Access Permission: Allow Read Access to Trusted Host Domain */ +#define SCM_PERM_TH_READ 0x00000040 +/** SCM Access Permission: Allow Write Access to Trusted Host Domain */ +#define SCM_PERM_TH_WRITE 0x00000020 +/** SCM Access Permission: Allow Read Access to Other/World Domain */ +#define SCM_PERM_OT_READ 0x00000004 +/** SCM Access Permission: Allow Write Access to Other/World Domain */ +#define SCM_PERM_OT_WRITE 0x00000002 +/** SCM Access Permission: Allow Execute Access to Other/World Domain */ +#define SCM_PERM_OT_EXECUTE 0x00000001 +/**< Valid bits that can be set in the Permissions register */ +#define SCM_PERM_MASK 0xC0000F67 + +/* Zeroize Command register definitions */ +#define ZCMD_DEALLOC_PART 3 /**< Deallocate Partition */ +#define Z_INT_EN 0x00000002 /**< Zero Interrupt Enable */ + +/** + * @defgroup scmpartitionownersregdefs SCM Partition Owners Register + */ +/** @addtogroup scmpartitionownersregdefs */ +/** @{ */ +/** Number of bits to shift partition number to get to its field. */ +#define SCM_POWN_SHIFT 2 +/** Mask for a field once the register has been shifted. */ +#define SCM_POWN_MASK 3 +/** Partition is free */ +#define SCM_POWN_PART_FREE 0 +/** Partition is unable to be allocated */ +#define SCM_POWN_PART_UNUSABLE 1 +/** Partition is owned by another master */ +#define SCM_POWN_PART_OTHER 2 +/** Partition is owned by this master */ +#define SCM_POWN_PART_OWNED 3 +/** @} */ + +/** + * @defgroup smnpartitionsengagedregdefs SCM Partitions Engaged Register + */ +/** @addtogroup smnpartitionsengagedregdefs */ +/** @{ */ +/** Number of bits to shift partition number to get to its field. */ +#define SCM_PENG_SHIFT 1 +/** Engaged value for a field once the register has been shifted. */ +#define SCM_PENG_ENGAGED 1 +/** @} */ + +/** Number of bytes between each subsequent SMID register */ +#define SCM_SMID_WIDTH 8 + +/** + * @defgroup smncommandregdefs SMN Command Register Definitions (SMN_COMMAND_REG) + */ +/** @addtogroup smncommandregdefs */ +/** @{ */ + +/** These bits are unimplemented or reserved */ +#define SMN_COMMAND_ZEROS_MASK 0xfffffff0 +#define SMN_COMMAND_CLEAR_INTERRUPT 0x8 /**< Clear SMN Interrupt */ +#define SMN_COMMAND_CLEAR_BIT_BANK 0x4 /**< Clear SMN Bit Bank */ +#define SMN_COMMAND_ENABLE_INTERRUPT 0x2 /**< Enable SMN Interrupts */ +#define SMN_COMMAND_SET_SOFTWARE_ALARM 0x1 /**< Set Software Alarm */ +/** @} */ + +/** + * @defgroup smntimercontroldefs SMN Timer Control Register definitions (SMN_TIMER_CONTROL) + */ +/** @addtogroup smntimercontroldefs */ +/** @{ */ +/** These bits are reserved or zero */ +#define SMN_TIMER_CTRL_ZEROS_MASK 0xfffffffc +/** Load the timer from #SMN_TIMER_IV_REG */ +#define SMN_TIMER_LOAD_TIMER 0x2 +/** Setting to zero stops the Timer */ +#define SMN_TIMER_STOP_MASK 0x1 +/** Setting this value starts the timer */ +#define SMN_TIMER_START_TIMER 0x1 +/** @} */ + +/** + * @defgroup scmchainmodedefs SCM_CHAINING_MODE_MASK - Bit definitions + */ +/** @addtogroup scmchainmodedefs */ +/** @{ */ +#define SCM_CBC_MODE 0x2 /**< Cipher block chaining */ +#define SCM_ECB_MODE 0x0 /**< Electronic codebook. */ +/** @} */ + +/* Bit definitions in the SCM_CIPHER_MODE_MASK */ +/** + * @defgroup scmciphermodedefs SCM_CIPHER_MODE_MASK - Bit definitions + */ +/** @addtogroup scmciphermodedefs */ +/** @{ */ +#define SCM_DECRYPT_MODE 0x1 /**< decrypt from black to red memory */ +#define SCM_ENCRYPT_MODE 0x0 /**< encrypt from red to black memory */ +/** @} */ + +/** + * @defgroup smndbgdetdefs SMN Debug Detector Status Register (SCM_DEBUG_DETECT_STAT) + */ +/** @addtogroup smndbgdetdefs */ +/** @{ */ +#define SMN_DBG_ZEROS_MASK 0xfffff000 /**< These bits are zero or reserved */ +#define SMN_DBG_D12 0x0800 /**< Error detected on Debug Port D12 */ +#define SMN_DBG_D11 0x0400 /**< Error detected on Debug Port D11 */ +#define SMN_DBG_D10 0x0200 /**< Error detected on Debug Port D10 */ +#define SMN_DBG_D9 0x0100 /**< Error detected on Debug Port D9 */ +#define SMN_DBG_D8 0x0080 /**< Error detected on Debug Port D8 */ +#define SMN_DBG_D7 0x0040 /**< Error detected on Debug Port D7 */ +#define SMN_DBG_D6 0x0020 /**< Error detected on Debug Port D6 */ +#define SMN_DBG_D5 0x0010 /**< Error detected on Debug Port D5 */ +#define SMN_DBG_D4 0x0008 /**< Error detected on Debug Port D4 */ +#define SMN_DBG_D3 0x0004 /**< Error detected on Debug Port D3 */ +#define SMN_DBG_D2 0x0002 /**< Error detected on Debug Port D2 */ +#define SMN_DBG_D1 0x0001 /**< Error detected on Debug Port D1 */ +/** @} */ + +/** Mask for the usable bits of the Sequence Start Register + (#SMN_SEQ_START_REG) */ +#define SMN_SEQUENCE_START_MASK 0x0000ffff + +/** Mask for the usable bits of the Sequence End Register + (#SMN_SEQ_END_REG) */ +#define SMN_SEQUENCE_END_MASK 0x0000ffff + +/** Mask for the usable bits of the Sequence Check Register + (#SMN_SEQ_CHECK_REG) */ +#define SMN_SEQUENCE_CHECK_MASK 0x0000ffff + +/** Mask for the usable bits of the Bit Counter Register + (#SMN_BB_CNT_REG) */ +#define SMN_BIT_COUNT_MASK 0x000007ff + +/** Mask for the usable bits of the Bit Bank Increment Size Register + (#SMN_BB_INC_REG) */ +#define SMN_BITBANK_INC_SIZE_MASK 0x000007ff + +/** Mask for the usable bits of the Bit Bank Decrement Register + (#SMN_BB_DEC_REG) */ +#define SMN_BITBANK_DECREMENT_MASK 0x000007ff + +/** Mask for the usable bits of the Compare Size Register + (#SMN_COMPARE_REG) */ +#define SMN_COMPARE_SIZE_MASK 0x0000003f + +/*! @} */ + +#endif /* SCC_DRIVER_H */ diff --git a/include/linux/mxc_scc_driver.h b/include/linux/mxc_scc_driver.h new file mode 100644 index 000000000000..a2f808cb3c53 --- /dev/null +++ b/include/linux/mxc_scc_driver.h @@ -0,0 +1,1031 @@ + +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_SCC_DRIVER_H__ +#define __ASM_ARCH_MXC_SCC_DRIVER_H__ + +/* Start marker for C++ compilers */ +#ifdef __cplusplus +extern "C" { +#endif + +/* + * NAMING CONVENTIONS + * ================== + * (A note to maintainers and other interested parties) + * + * Use scc_ or SCC_ prefix for 'high-level' interface routines and the types + * passed to those routines. Try to avoid #defines in these interfaces. + * + * Use SMN_ or SCM_ prefix for the #defines used with scc_read_register() and + * scc_write_register, or values passed/retrieved from those routines. + */ + +/*! + * @defgroup MXCSCC SCC Driver + * + * @ingroup MXCSECDRVRS + */ + +/*! + * @file arch-mxc/mxc_scc_driver.h + * + * @brief (Header file to use the SCC driver.) + * + * The SCC driver will only be available to other kernel modules. That is, + * there will be no node file in /dev, no way for a user-mode program to access + * the driver, no way for a user program to access the device directly. + * + * With the exception of #scc_monitor_security_failure(), all routines are + * 'synchronous', i.e. they will not return to their caller until the requested + * action is complete, or fails to complete. Some of these functions could + * take quite a while to perform, depending upon the request. + * + * Routines are provided to: + * @li encrypt or decrypt secrets - #scc_crypt() + * @li trigger a security-violation alarm - #scc_set_sw_alarm() + * @li get configuration and version information - #scc_get_configuration() + * @li zeroize memory - #scc_zeroize_memories() + * @li Work on wrapped and stored secret values: #scc_alloc_slot(), + * #scc_dealloc_slot(), scc_load_slot(), #scc_decrypt_slot(), + * #scc_encrypt_slot(), #scc_get_slot_info() + + * @li monitor the Security Failure alarm - #scc_monitor_security_failure() + * @li stop monitoring Security Failure alarm - + * #scc_stop_monitoring_security_failure() + * @li write registers of the SCC - #scc_write_register() + * @li read registers of the SCC - #scc_read_register() + * + * The driver does not allow "storage" of data in either the Red or Black + * memories. Any decrypted secret is returned to the user, and if the user + * wants to use it at a later point, the encrypted form must again be passed + * to the driver, and it must be decrypted again. + * + * The SCC encrypts and decrypts using Triple DES with an internally stored + * key. When the SCC is in Secure mode, it uses its secret, unique-per-chip + * key. When it is in Non-Secure mode, it uses a default key. This ensures + * that secrets stay secret if the SCC is not in Secure mode. + * + * Not all functions that could be provided in a 'high level' manner have been + * implemented. Among the missing are interfaces to the ASC/AIC components and + * the timer functions. These and other features must be accessed through + * #scc_read_register() and #scc_write_register(), using the @c \#define values + * provided. + * + * Here is a glossary of acronyms used in the SCC driver documentation: + * - CBC - Cipher Block Chaining. A method of performing a block cipher. + * Each block is encrypted using some part of the result of the previous + * block's encryption. It needs an 'initialization vector' to seed the + * operation. + * - ECB - Electronic Code Book. A method of performing a block cipher. + * With a given key, a given block will always encrypt to the same value. + * - DES - Data Encryption Standard. (8-byte) Block cipher algorithm which + * uses 56-bit keys. In SCC, this key is constant and unique to the device. + * SCC uses the "triple DES" form of this algorithm. + * - AIC - Algorithm Integrity Checker. + * - ASC - Algorithm Sequence Checker. + * - SMN - Security Monitor. The part of the SCC responsible for monitoring + * for security problems and notifying the CPU and other PISA components. + * - SCM - Secure Memory. The part of the SCC which handles the cryptography. + * - SCC - Security Controller. Central security mechanism for PISA. + * - PISA - Platform-Independent Security Architecture. + */ + +/* Temporarily define compile-time flags to make Doxygen happy. */ +#ifdef DOXYGEN_HACK +/*! @defgroup scccompileflags SCC Driver compile-time flags + * + * These preprocessor flags should be set, if desired, in a makefile so + * that they show up on the compiler command line. + */ +/*! @addtogroup scccompileflags */ + +/*! @{ */ +/*! + * Compile-time flag to change @ref smnregs and @ref scmregs + * offset values for the SCC's implementation on the MX.21 board. + * + * This must also be set properly for any code which calls the + * scc_read_register() or scc_write_register() functions or references the + * register offsets. + */ +#define TAHITI +/*! @} */ +#undef TAHITI + +#endif /* DOXYGEN_HACK */ + +/*! Major Version of the driver. Used for + scc_configuration->driver_major_version */ +#define SCC_DRIVER_MAJOR_VERSION_1 1 +/*! Old Minor Version of the driver. */ +#define SCC_DRIVER_MINOR_VERSION_0 0 +/*! Old Minor Version of the driver. */ +#define SCC_DRIVER_MINOR_VERSION_4 4 +/*! Old Minor Version of the driver. */ +#define SCC_DRIVER_MINOR_VERSION_5 5 +/*! Old Minor Version of the driver. */ +#define SCC_DRIVER_MINOR_VERSION_6 6 +/*! Minor Version of the driver. Used for + scc_configuration->driver_minor_version */ +#define SCC_DRIVER_MINOR_VERSION_8 8 + + +/*! + * @typedef scc_return_t + */ +/*! Common status return values from SCC driver functions. */ + typedef enum scc_return_t { + SCC_RET_OK = 0, /*!< Function succeeded */ + SCC_RET_FAIL, /*!< Non-specific failure */ + SCC_RET_VERIFICATION_FAILED, /*!< Decrypt validation failed */ + SCC_RET_TOO_MANY_FUNCTIONS, /*!< At maximum registered functions */ + SCC_RET_BUSY, /*!< SCC is busy and cannot handle request */ + SCC_RET_INSUFFICIENT_SPACE, /*!< Encryption or decryption failed because + @c count_out_bytes says that @c data_out is + too small to hold the value. */ + } scc_return_t; + +/*! + * Configuration information about SCC and the driver. + * + * This struct/typedef contains information from the SCC and the driver to + * allow the user of the driver to determine the size of the SCC's memories and + * the version of the SCC and the driver. + */ + typedef struct scc_config_t { + int driver_major_version; /*!< Major version of the SCC driver code */ + int driver_minor_version; /*!< Minor version of the SCC driver code */ + int scm_version; /*!< Version from SCM Configuration register */ + int smn_version; /*!< Version from SMN Status register */ + int block_size_bytes; /*!< Number of bytes per block of RAM; also + block size of the crypto algorithm. */ + int black_ram_size_blocks; /*!< Number of blocks of Black RAM */ + int red_ram_size_blocks; /*!< Number of blocks of Red RAM */ + } scc_config_t; + +/*! + * @typedef scc_enc_dec_t + */ +/*! + * Determine whether SCC will run its cryptographic + * function as an encryption or decryption. Used as an argument to + * #scc_crypt(). + */ + typedef enum scc_enc_dec_t { + SCC_ENCRYPT, /*!< Encrypt (from Red to Black) */ + SCC_DECRYPT /*!< Decrypt (from Black to Red) */ + } scc_enc_dec_t; + +/* + * @typedef scc_crypto_mode_t + */ +/*! + * Determine whether SCC will run its cryptographic function in ECB (electronic + * codebook) or CBC (cipher-block chaining) mode. Used as an argument to + * #scc_crypt(). + */ + typedef enum scc_crypto_mode_t { + SCC_ECB_MODE, /*!< Electronic Codebook Mode */ + SCC_CBC_MODE /*!< Cipher Block Chaining Mode */ + } scc_crypto_mode_t; + +/*! + * @typedef scc_verify_t + */ +/*! + * Tell the driver whether it is responsible for verifying the integrity of a + * secret. During an encryption, using other than #SCC_VERIFY_MODE_NONE will + * cause a check value to be generated and appended to the plaintext before + * encryption. During decryption, the check value will be verified after + * decryption, and then stripped from the message. + */ + typedef enum scc_verify_t { + /*! No verification value added or checked. Input plaintext data must be + * be a multiple of the blocksize (#scc_get_configuration()). */ + SCC_VERIFY_MODE_NONE, + /*! Driver will generate/validate a 2-byte CCITT CRC. Input plaintext will + be padded to a multiple of the blocksize, adding 3-10 bytes to the + resulting output ciphertext. Upon decryption, this padding will be + stripped, and the CRC will be verified. */ + SCC_VERIFY_MODE_CCITT_CRC + } scc_verify_t; + +/*! + * Determine if the given credentials match that of the key slot. + * + * @param[in] owner_id A value which will control access to the slot. + * @param[in] slot Key Slot to query + * @param[in] access_len Length of the key + * + * @return 0 on success, non-zero on failure. See #scc_return_t. + */ + scc_return_t + scc_verify_slot_access(uint64_t owner_id, uint32_t slot, + uint32_t access_len); + +/*! + * Retrieve configuration information from the SCC. + * + * This function always succeeds. + * + * @return A pointer to the configuration information. This is a pointer to + * static memory and must not be freed. The values never change, and + * the return value will never be null. + */ + extern scc_config_t *scc_get_configuration(void); + +/*! + * Zeroize Red and Black memories of the SCC. This will start the Zeroizing + * process. The routine will return when the memories have zeroized or failed + * to do so. The driver will poll waiting for this to occur, so this + * routine must not be called from interrupt level. Some future version of + * driver may elect instead to sleep. + * + * @return 0 or error if initialization fails. + */ + extern scc_return_t scc_zeroize_memories(void); + +/*! + * Perform a Triple DES encryption or decryption operation. + * + * This routine will cause the SCM to perform an encryption or decryption with + * its internal key. If the SCC's #SMN_STATUS register shows that the SCC is + * in #SMN_STATE_SECURE, then the Secret Key will be used. If it is + * #SMN_STATE_NON_SECURE (or health check), then the Default Key will be used. + * + * This function will perform in a variety of ways, depending upon the values + * of @c direction, @c crypto_mode, and @c check_mode. If + * #SCC_VERIFY_MODE_CCITT_CRC mode is requested, upon successful completion, + * the @c count_in_bytes will be different from the returned value of @c + * count_out_bytes. This is because the two-byte CRC and some amount of + * padding (at least one byte) will either be added or stripped. + * + * This function will not return until the SCC has performed the operation (or + * reported failure to do so). It must therefore not be called from interrupt + * level. In the current version, it will poll the SCC for completion. In + * future versions, it may sleep. + * + * @param[in] count_in_bytes The number of bytes to move through the crypto + * function. Must be greater than zero. + * + * @param[in] data_in Pointer to the array of bytes to be used as input + * to the crypto function. + * + * @param[in] init_vector Pointer to the block-sized (8 byte) array of + * bytes which form the initialization vector for + * this operation. A non-null value is required + * when @c crypto_mode has the value #SCC_CBC_MODE; + * the value is ignored in #SCC_ECB_MODE. + * + * @param[in] direction Direct the driver to perform encryption or + * decryption. + * + * @param[in] crypto_mode Run the crypto function in ECB or CBC mode. + * + * @param[in] check_mode During encryption, generate and append a check + * value to the plaintext and pad the resulting + * data. During decryption, validate the plaintext + * with that check value and remove the padding. + * + * @param[in,out] count_out_bytes On input, the number of bytes available for + * copying to @c data_out. On return, the number of + * bytes copied to @c data_out. + * + * @param[out] data_out Pointer to the array of bytes that are where the + * output of the crypto function are to be placed. + * For encryption, this must be able to hold a + * longer ciphertext than the plaintext message at + * @c data_in. The driver will append a 'pad' of + * 1-8 bytes to the message, and if @c check_mode is + * used, additional bytes may be added, the number + * depending upon the type of check being requested. + * + * @return 0 on success, non-zero on failure. See #scc_return_t. + * + * @internal + * This function will verify SCC state and the functions parameters. It will + * acquire the crypto lock, and set up some SCC registers and variables common + * to encryption and decryption. A rough check will be made to verify that + * enough space is available in @c count_out_bytes. Upon success, either the + * #scc_encrypt or #scc_decrypt routine will be called to do the actual work. + * The crypto lock will then be released. + */ +extern scc_return_t scc_crypt(unsigned long count_in_bytes, + const uint8_t *data_in, + const uint8_t *init_vector, + scc_enc_dec_t direction, + scc_crypto_mode_t crypto_mode, + scc_verify_t check_mode, + uint8_t *data_out, + unsigned long *count_out_bytes); + + +/*! + * Allocate a key slot for a stored key (or other stored value). + * + * This feature is to allow decrypted secret values to be kept in RED RAM. + * This can all visibility of the data only by Sahara. + * + * @param value_size_bytes Size, in bytes, of RED key/value. Currently only + * a size up to 32 bytes is supported. + * + * @param owner_id A value which will control access to the slot. + * It must be passed into to any subsequent calls to + * use the assigned slot. + * + * @param[out] slot The slot number for the key. + * + * @return 0 on success, non-zero on failure. See #scc_return_t. + */ + extern scc_return_t scc_alloc_slot(uint32_t value_size_bytes, + uint64_t owner_id, uint32_t *slot); + +/*! + * Deallocate the key slot of a stored key or secret value. + * + * @param owner_id The id which owns the @c slot. + * + * @param slot The slot number for the key. + + * @return 0 on success, non-zero on failure. See #scc_return_t. + */ + extern scc_return_t scc_dealloc_slot(uint64_t owner_id, uint32_t slot); + +/*! + * Load a value into a slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param key_data Data to load into the slot + * @param key_length Length, in bytes, of @c key_data to copy to SCC. + * + * @return SCC_RET_OK on success. SCC_RET_FAIL will be returned if slot + * specified cannot be accessed for any reason, or SCC_RET_INSUFFICIENT_SPACE + * if @c key_length exceeds the size of the slot. + */ + extern scc_return_t scc_load_slot(uint64_t owner_id, uint32_t slot, + const uint8_t *key_data, + uint32_t key_length); +/*! + * Read a value from a slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param key_length Length, in bytes, of @c key_data to copy from SCC. + * @param key_data Location to write the key + * + * @return SCC_RET_OK on success. SCC_RET_FAIL will be returned if slot + * specified cannot be accessed for any reason, or SCC_RET_INSUFFICIENT_SPACE + * if @c key_length exceeds the size of the slot. + */ + extern scc_return_t scc_read_slot(uint64_t owner_id, uint32_t slot, + uint32_t key_length, + uint8_t *key_data); + +/*! + * Allocate a key slot to fit the requested size. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param length Length, in bytes, of @c black_data + * @param black_data Location to store result of encrypting RED data in slot + * + * @return SCC_RET_OK on success, SCC_RET_FAIL if slot specified cannot be + * accessed for any reason. + */ + extern scc_return_t scc_encrypt_slot(uint64_t owner_id, uint32_t slot, + uint32_t length, + uint8_t *black_data); + +/*! + * Decrypt some black data and leave result in the slot. + * + * @param owner_id Value of owner of slot + * @param slot Handle of slot + * @param length Length, in bytes, of @c black_data + * @param black_data Location of data to dencrypt and store in slot + * + * @return SCC_RET_OK on success, SCC_RET_FAIL if slot specified cannot be + * accessed for any reason. + */ + extern scc_return_t scc_decrypt_slot(uint64_t owner_id, uint32_t slot, + uint32_t length, + const uint8_t *black_data); + +/*! + * Get attributes of data in RED slot. + * + * @param owner_id The id which owns the @c slot. + * + * @param slot The slot number for the key. + * + * @param[out] address Physical address of RED value. + * + * @param[out] value_size_bytes Length, in bytes, of RED value, + * or NULL if unneeded.. + * + * @param[out] slot_size_bytes Length, in bytes, of slot size, + * or NULL if unneeded.. + * + * @return 0 on success, non-zero on failure. See #scc_return_t. + */ + extern scc_return_t scc_get_slot_info(uint64_t owner_id, uint32_t slot, + uint32_t *address, + uint32_t *value_size_bytes, + uint32_t *slot_size_bytes); + +/*! + * Signal a software alarm to the SCC. This will take the SCC and other PISA + * parts out of Secure mode and into Security Failure mode. The SCC will stay + * in failed mode until a reboot. + * + * @internal + * If the SCC is not already in fail state, simply write the + * #SMN_COMMAND_SET_SOFTWARE_ALARM bit in #SMN_COMMAND. Since there is no + * reason to wait for the interrupt to bounce back, simply act as though + * one did. + */ + extern void scc_set_sw_alarm(void); + +/*! + * This routine will register a function to be called should a Security Failure + * be signalled by the SCC (Security Monitor). + * + * The callback function may be called from interrupt level, it may be called + * from some process' task. It should therefore not take a long time to + * perform its operation, and it may not sleep. + * + * @param callback_func Function pointer to routine which will receive + * notification of the security failure. + * @return 0 if function was successfully registered, non-zero on + * failure. See #scc_return_t. + * + * @internal + * There is a fixed global static array which keeps track of the requests to + * monitor the failure. + * + * Add @c callback_func to the first empty slot in #scc_callbacks[]. If there + * is no room, return #SCC_RET_TOO_MANY_FUNCTIONS. + */ + extern scc_return_t scc_monitor_security_failure(void + callback_func(void)); + +/*! + * This routine will deregister a function previously registered with + * #scc_monitor_security_failure(). + * + * @param callback_func Function pointer to routine previously registered with + * #scc_stop_monitoring_security_failure(). + */ + extern void scc_stop_monitoring_security_failure(void + callback_func(void)); + +/*! + * Read value from an SCC register. + * The offset will be checked for validity (range) as well as whether it is + * accessible (e.g. not busy, not in failed state) at the time of the call. + * + * @param[in] register_offset The (byte) offset within the SCC block + * of the register to be queried. See + * @ref scmregs and @ref smnregs. + * @param[out] value Pointer to where value from the register + * should be placed. + * @return 0 if OK, non-zero on error. See #scc_return_t. + * + * @internal + * Verify that the register_offset is a) valid, b) refers to a readable + * register, and c) the SCC is in a state which would allow a read of this + * register. + */ + extern scc_return_t scc_read_register(int register_offset, + uint32_t *value); + +/*! + * Write a new value into an SCC register. + * The offset will be checked for validity (range) as well as whether it is + * accessible (e.g. not busy, not in failed state) at the time of the call. + * + * @param[in] register_offset The (byte) offset within the SCC block + * of the register to be modified. See + * @ref scmregs and @ref smnregs. + * @param[in] value The value to store into the register. + * @return 0 if OK, non-zero on error. See #scc_return_t. + * + * @internal + * Verify that the register_offset is a) valid, b) refers to a writeable + * register, and c) the SCC is in a state which would allow a write to this + * register. + */ + extern scc_return_t scc_write_register(int register_offset, + uint32_t value); + +/* + * NOTE TO MAINTAINERS + * + * All of the doxygen comments for the register offset values are in this the + * following comment section. Any changes to register names or definitions + * must be reflected in this section and in both the TAHITI and non-TAHITI + *version of the memory map. + */ + +/*! + * @defgroup scmregs SCM Registers + * + * These values are offsets into the SCC for the Secure Memory + * (SCM) registers. They are used in the @c register_offset parameter of + * #scc_read_register() and #scc_write_register(). + */ +/*! @addtogroup scmregs */ +/*! @{ */ +/*! @def SCM_RED_START + * Starting block offset in red memory for cipher function. */ + +/*! @def SCM_BLACK_START + * Starting block offset in black memory for cipher function. */ + +/*! @def SCM_LENGTH + * Number of blocks to process during cipher function */ + +/*! @def SCM_CONTROL + * SCM Control register. + * See @ref scmcontrolregdefs "SCM Control Register definitions" for details. + */ + +/*! @def SCM_STATUS + * SCM Status register. + * See @ref scmstatusregdefs "SCM Status Register Definitions" for details. + */ + +/*! @def SCM_ERROR_STATUS + * SCM Error Status Register. + * See @ref scmerrstatdefs "SCM Error Status Register definitions" for + * details. */ + +/*! @def SCM_INTERRUPT_CTRL + * SCM Interrupt Control Register. + * See @ref scminterruptcontroldefs "SCM Interrupt Control Register definitions" + * for details. + */ + +/*! @def SCM_CONFIGURATION + * SCM Configuration Register. + * See @ref scmconfigdefs "SCM Configuration Register Definitions" for + * details. + */ + +/*! @def SCM_INIT_VECTOR_0 + * Upper Half of the Initialization Vector */ + +/*! @def SCM_INIT_VECTOR_1 + * Lower Half of the Initialization Vector */ + +/*! @def SCM_RED_MEMORY + * Starting location of first block of Red memory */ + +/*! @def SCM_BLACK_MEMORY + * Starting location of first block of Black memory */ + + /*! @} *//* end of SCM group */ + +/*! + * @defgroup smnregs SMN Registers + * + * These values are offsets into the SCC for the Security Monitor + * (SMN) registers. They are used in the @c register_offset parameter of the + * #scc_read_register() and #scc_write_register(). + */ +/*! @addtogroup smnregs */ +/*! @{ */ +/*! @def SMN_STATUS + * Status register for SMN. + * See @ref smnstatusregdefs "SMN Status Register definitions" for further + * information. + */ + +/*! @def SMN_COMMAND + * Command register for SMN. See + * @ref smncommandregdefs "Command Register Definitions" for further + * information. + */ + +/*! @def SMN_SEQUENCE_START + * Sequence Start register for ASC. See #SMN_SEQUENCE_START_MASK + */ + +/*! @def SMN_SEQUENCE_END + * Sequence End register for ASC. See #SMN_SEQUENCE_CHECK_MASK + */ + +/*! @def SMN_SEQUENCE_CHECK + * Sequence Check register for ASC. See #SMN_SEQUENCE_END_MASK + */ + +/*! @def SMN_BIT_COUNT + * Bit Bank Repository for AIC. See #SMN_BIT_COUNT_MASK + */ + +/*! @def SMN_BITBANK_INC_SIZE + * Bit Bank Increment Size for AIC. See #SMN_BITBANK_INC_SIZE_MASK + */ + +/*! @def SMN_BITBANK_DECREMENT + * Bit Bank Decrement for AIC. See #SMN_BITBANK_DECREMENT_MASK + */ + +/*! @def SMN_COMPARE_SIZE + * Compare Size register for Plaintext/Ciphertext checker. See + * #SMN_COMPARE_SIZE_MASK */ + +/*! @def SMN_PLAINTEXT_CHECK + * Plaintext Check register for Plaintext/Ciphertext checker. + */ + +/*! @def SMN_CIPHERTEXT_CHECK + * Ciphertext Check register for Plaintext/Ciphertext checker. + */ + +/*! @def SMN_TIMER_IV + * Timer Initial Value register + */ + +/*! @def SMN_TIMER_CONTROL + * Timer Control register. + * See @ref smntimercontroldefs "SMN Timer Control Register definitions". + */ + +/*! @def SMN_DEBUG_DETECT_STAT + * Debug Detector Status Register + * See @ref smndbgdetdefs "SMN Debug Detector Status Register"for definitions. + */ + +/*! @def SMN_TIMER + * Current value of the Timer Register + */ + + /*! @} *//* end of SMN group */ + +/* + * SCC MEMORY MAP + * + */ + +/* SCM registers */ +#define SCM_RED_START 0x00000000 /* read/write */ +#define SCM_BLACK_START 0x00000004 /* read/write */ +#define SCM_LENGTH 0x00000008 /* read/write */ +#define SCM_CONTROL 0x0000000C /* read/write */ +#define SCM_STATUS 0x00000010 /* read only */ +#define SCM_ERROR_STATUS 0x00000014 /* read/write */ +#define SCM_INTERRUPT_CTRL 0x00000018 /* read/write */ +#define SCM_CONFIGURATION 0x0000001C /* read only */ +#define SCM_INIT_VECTOR_0 0x00000020 /* read/write */ +#define SCM_INIT_VECTOR_1 0x00000024 /* read/write */ +#define SCM_RED_MEMORY 0x00000400 /* read/write */ +#define SCM_BLACK_MEMORY 0x00000800 /* read/write */ + +/* SMN Registers */ +#define SMN_STATUS 0x00001000 /* read/write */ +#define SMN_COMMAND 0x00001004 /* read/write */ +#define SMN_SEQUENCE_START 0x00001008 /* read/write */ +#define SMN_SEQUENCE_END 0x0000100C /* read/write */ +#define SMN_SEQUENCE_CHECK 0x00001010 /* read/write */ +#define SMN_BIT_COUNT 0x00001014 /* read only */ +#define SMN_BITBANK_INC_SIZE 0x00001018 /* read/write */ +#define SMN_BITBANK_DECREMENT 0x0000101C /* write only */ +#define SMN_COMPARE_SIZE 0x00001020 /* read/write */ +#define SMN_PLAINTEXT_CHECK 0x00001024 /* read/write */ +#define SMN_CIPHERTEXT_CHECK 0x00001028 /* read/write */ +#define SMN_TIMER_IV 0x0000102C /* read/write */ +#define SMN_TIMER_CONTROL 0x00001030 /* read/write */ +#define SMN_DEBUG_DETECT_STAT 0x00001034 /* read/write */ +#define SMN_TIMER 0x00001038 /* read only */ + +/*! Total address space of the SCC, in bytes */ +#define SCC_ADDRESS_RANGE 0x103c + +/*! + * @defgroup smnstatusregdefs SMN Status Register definitions (SMN_STATUS) + */ +/*! @addtogroup smnstatusregdefs */ +/*! @{ */ +/*! SMN version id. */ +#define SMN_STATUS_VERSION_ID_MASK 0xfc000000 +/*! number of bits to shift #SMN_STATUS_VERSION_ID_MASK to get it to LSB */ +#define SMN_STATUS_VERSION_ID_SHIFT 26 +/*! Cacheable access to SMN attempted. */ +#define SMN_STATUS_CACHEABLE_ACCESS 0x02000000 +/*! Illegal bus master access attempted. */ +#define SMN_STATUS_ILLEGAL_MASTER 0x01000000 +/*! Scan mode entered/exited since last reset. */ +#define SMN_STATUS_SCAN_EXIT 0x00800000 +/*! Unaligned access attempted. */ +#define SMN_STATUS_UNALIGNED_ACCESS 0x00400000 +/*! Bad byte offset access attempted. */ +#define SMN_STATUS_BYTE_ACCESS 0x00200000 +/*! Illegal address access attempted. */ +#define SMN_STATUS_ILLEGAL_ADDRESS 0x00100000 +/*! User access attempted. */ +#define SMN_STATUS_USER_ACCESS 0x00080000 +/*! SCM is using DEFAULT key. */ +#define SMN_STATUS_DEFAULT_KEY 0x00040000 +/*! SCM detects weak or bad key. */ +#define SMN_STATUS_BAD_KEY 0x00020000 +/*! Illegal access to SCM detected. */ +#define SMN_STATUS_ILLEGAL_ACCESS 0x00010000 +/*! Internal error detected in SCM. */ +#define SMN_STATUS_SCM_ERROR 0x00008000 +/*! SMN has an outstanding interrupt. */ +#define SMN_STATUS_SMN_STATUS_IRQ 0x00004000 +/*! Software Alarm was triggered. */ +#define SMN_STATUS_SOFTWARE_ALARM 0x00002000 +/*! Timer has expired. */ +#define SMN_STATUS_TIMER_ERROR 0x00001000 +/*! Plaintext/Ciphertext compare failed. */ +#define SMN_STATUS_PC_ERROR 0x00000800 +/*! Bit Bank detected overflow or underflow */ +#define SMN_STATUS_BITBANK_ERROR 0x00000400 +/*! Algorithm Sequence Check failed. */ +#define SMN_STATUS_ASC_ERROR 0x00000200 +/*! Security Policy Block detected error. */ +#define SMN_STATUS_SECURITY_POLICY_ERROR 0x00000100 +/*! At least one Debug signal is active. */ +#define SMN_STATUS_DEBUG_ACTIVE 0x00000080 +/*! SCM failed to zeroize its memory. */ +#define SMN_STATUS_ZEROIZE_FAIL 0x00000040 +/*! Processor booted from internal ROM. */ +#define SMN_STATUS_INTERNAL_BOOT 0x00000020 +/*! SMN's internal state. */ +#define SMN_STATUS_STATE_MASK 0x0000001F +/*! Number of bits to shift #SMN_STATUS_STATE_MASK to get it to LSB. */ +#define SMN_STATUS_STATE_SHIFT 0 +/*! @} */ + +/*! + * @defgroup sccscmstates SMN Model Secure State Controller States (SMN_STATE_MASK) + */ +/*! @addtogroup sccscmstates */ +/*! @{ */ +/*! This is the first state of the SMN after power-on reset */ +#define SMN_STATE_START 0x0 +/*! The SMN is zeroizing its RAM during reset */ +#define SMN_STATE_ZEROIZE_RAM 0x5 +/*! SMN has passed internal checks, and is waiting for Software check-in */ +#define SMN_STATE_HEALTH_CHECK 0x6 +/*! Fatal Security Violation. SMN is locked, SCM is inoperative. */ +#define SMN_STATE_FAIL 0x9 +/*! SCC is in secure state. SCM is using secret key. */ +#define SMN_STATE_SECURE 0xA +/*! Due to non-fatal error, device is not secure. SCM is using default key. */ +#define SMN_STATE_NON_SECURE 0xC +/*! @} */ + +/*! + * @defgroup scmconfigdefs SCM Configuration Register definitions (SCM_CONFIGURATION) + **/ +/*! @addtogroup scmconfigdefs */ +/*! @{ */ +/*! Version number of the Secure Memory. */ +#define SCM_CFG_VERSION_ID_MASK 0xf8000000 +/*! Number of bits to shift #SCM_CFG_VERSION_ID_MASK to get it to LSB. */ +#define SCM_CFG_VERSION_ID_SHIFT 27 +/*! Version one value for SCC configuration */ +#define SCM_VERSION_1 1 +/*! Size, in blocks, of Red memory. */ +#define SCM_CFG_BLACK_SIZE_MASK 0x07fe0000 +/*! Number of bits to shift #SCM_CFG_BLACK_SIZE_MASK to get it to LSB. */ +#define SCM_CFG_BLACK_SIZE_SHIFT 17 +/*! Size, in blocks, of Black memory. */ +#define SCM_CFG_RED_SIZE_MASK 0x0001ff80 +/*! Number of bits to shift #SCM_CFG_RED_SIZE_MASK to get it to LSB. */ +#define SCM_CFG_RED_SIZE_SHIFT 7 +/*! Number of bytes per block. */ +#define SCM_CFG_BLOCK_SIZE_MASK 0x0000007f +/*! Number of bits to shift #SCM_CFG_BLOCK_SIZE_MASK to get it to LSB. */ +#define SCM_CFG_BLOCK_SIZE_SHIFT 0 +/*! @} */ + +/*! + * @defgroup smncommandregdefs SMN Command Register Definitions (SMN_COMMAND) + */ +/*! @addtogroup smncommandregdefs */ +/*! @{ */ +#define SMN_COMMAND_ZEROS_MASK 0xffffff70 /*!< These bits are unimplemented + or reserved */ +#define SMN_COMMAND_TAMPER_LOCK 0x10 /*!< Lock Tamper Detect Bit */ +#define SMN_COMMAND_CLEAR_INTERRUPT 0x8 /*!< Clear SMN Interrupt */ +#define SMN_COMMAND_CLEAR_BIT_BANK 0x4 /*!< Clear SMN Bit Bank */ +#define SMN_COMMAND_ENABLE_INTERRUPT 0x2 /*!< Enable SMN Interrupts */ +#define SMN_COMMAND_SET_SOFTWARE_ALARM 0x1 /*!< Set Software Alarm */ +/*! @} */ + +/*! + * @defgroup smntimercontroldefs SMN Timer Control Register definitions (SMN_TIMER_CONTROL) + */ +/*! @addtogroup smntimercontroldefs */ +/*! @{ */ +/*! These bits are reserved or zero */ +#define SMN_TIMER_CTRL_ZEROS_MASK 0xfffffffc +/*! Load the timer from #SMN_TIMER_IV */ +#define SMN_TIMER_LOAD_TIMER 0x2 +/*! Setting to zero stops the Timer */ +#define SMN_TIMER_STOP_MASK 0x1 +/*! Setting this value starts the timer */ +#define SMN_TIMER_START_TIMER 0x1 +/*! @} */ + +/*! + * @defgroup scminterruptcontroldefs SCM Interrupt Control Register definitions (SCM_INTERRUPT_CTRL) + * + * These are the bit definitions for the #SCM_INTERRUPT_CTRL register. + */ +/*! @addtogroup scminterruptcontroldefs */ +/*! @{ */ +/*! Clear SCM memory */ +#define SCM_INTERRUPT_CTRL_ZEROIZE_MEMORY 0x4 +/*! Clear outstanding SCM interrupt */ +#define SCM_INTERRUPT_CTRL_CLEAR_INTERRUPT 0x2 +/*! Inhibit SCM interrupts */ +#define SCM_INTERRUPT_CTRL_MASK_INTERRUPTS 0x1 +/*! @} */ + +/*! + * @defgroup scmcontrolregdefs SCM Control Register definitions (SCM_CONTROL). + * These values are used with the #SCM_CONTROL register. + */ +/*! @addtogroup scmcontrolregdefs */ +/*! @{ */ +/*! These bits are zero or reserved */ +#define SCM_CONTROL_ZEROS_MASK 0xfffffff8 +/*! Setting this will start encrypt/decrypt */ +#define SCM_CONTROL_START_CIPHER 0x04 +/*! CBC/ECB flag. + * See @ref scmchainmodedefs "Chaining Mode bit definitions." + */ +#define SCM_CONTROL_CHAINING_MODE_MASK 0x02 +/*! Encrypt/decrypt choice. + * See @ref scmciphermodedefs "Cipher Mode bit definitions." */ +#define SCM_CONTROL_CIPHER_MODE_MASK 0x01 +/*! @} */ + +/*! + * @defgroup scmchainmodedefs SCM_CHAINING_MODE_MASK - Bit definitions + */ +/*! @addtogroup scmchainmodedefs */ +/*! @{ */ +#define SCM_CBC_MODE 0x2 /*!< Cipher block chaining */ +#define SCM_ECB_MODE 0x0 /*!< Electronic codebook. */ +/*! @} */ + +/* Bit definitions in the SCM_CIPHER_MODE_MASK */ +/*! + * @defgroup scmciphermodedefs SCM_CIPHER_MODE_MASK - Bit definitions + */ +/*! @{ */ +#define SCM_DECRYPT_MODE 0x1 /*!< decrypt from black to red memory */ +#define SCM_ENCRYPT_MODE 0x0 /*!< encrypt from red to black memory */ +/*! @} */ + +/*! + * @defgroup scmstatusregdefs SCM Status Register (SCM_STATUS). + * Bit and field definitions of the SCM_STATUS register. + */ +/*! @addtogroup scmstatusregdefs */ +/*! @{ */ +/*! These bits are zero or reserved */ +#define SCM_STATUS_ZEROS_MASK 0xffffe000 +/*! Ciphering failed due to length error. */ +#define SCM_STATUS_LENGTH_ERROR 0x1000 +/*! SMN has stopped blocking access to the SCM */ +#define SCM_STATUS_BLOCK_ACCESS_REMOVED 0x0800 +/*! Ciphering done. */ +#define SCM_STATUS_CIPHERING_DONE 0x0400 +/*! Zeroizing done. */ +#define SCM_STATUS_ZEROIZING_DONE 0x0200 +/*! SCM wants attention. Interrupt status is available. */ +#define SCM_STATUS_INTERRUPT_STATUS 0x0100 +/*! Secret Key is in use. */ +#define SCM_STATUS_SECRET_KEY 0x0080 +/*! Secret Key is in use. Deprecated. Use #SCM_STATUS_SECRET_KEY. */ +#define SCM_STATUS_DEFAULT_KEY 0x0080 +/*! Internal error to SCM. */ +#define SCM_STATUS_INTERNAL_ERROR 0x0040 +/*! Secret key is not valid. */ +#define SCM_STATUS_BAD_SECRET_KEY 0x0020 +/*! Failed to zeroize memory. */ +#define SCM_STATUS_ZEROIZE_FAILED 0x0010 +/*! SMN is blocking access to Secure Memory. */ +#define SCM_STATUS_SMN_BLOCKING_ACCESS 0x0008 +/*! SCM is current encrypting or decrypting data. */ +#define SCM_STATUS_CIPHERING 0x0004 +/*! SCM is currently zeroizing data. */ +#define SCM_STATUS_ZEROIZING 0x0002 +/*! SCM is busy and access to memory is blocked. */ +#define SCM_STATUS_BUSY 0x0001 +/*! @} */ + +/*! + * @defgroup scmerrstatdefs SCM Error Status Register (SCM_ERROR_STATUS) + * + * These definitions are associated with the SCM Error Status Register + * (SCM_ERROR_STATUS). + */ +/*! @addtogroup scmerrstatdefs */ +/*! @{ */ +/*! These bits are zero or reserved */ +#define SCM_ERR_ZEROS_MASK 0xffffc000 +/*! Cacheable access to SCM was attempted */ +#define SCM_ERR_CACHEABLE_ACCESS 0x2000 +/*! Access attempted by illegal bus master */ +#define SCM_ERR_ILLEGAL_MASTER 0x1000 +/*! Unaligned access attempted */ +#define SCM_ERR_UNALIGNED_ACCESS 0x0800 +/*! Byte or half-word access attempted */ +#define SCM_ERR_BYTE_ACCESS 0x0400 +/*! Illegal address attempted */ +#define SCM_ERR_ILLEGAL_ADDRESS 0x0200 +/*! User access attempted */ +#define SCM_ERR_USER_ACCESS 0x0100 +/*! Access attempted while SCM was using default key */ +#define SCM_ERR_SECRET_KEY_IN_USE 0x0080 +/*! Access attempted while SCM had internal error */ +#define SCM_ERR_INTERNAL_ERROR 0x0040 +/*! Access attempted while SCM was detecting Bad Key */ +#define SCM_ERR_BAD_SECRET_KEY 0x0020 +/*! The SCM failed to Zeroize memory */ +#define SCM_ERR_ZEROIZE_FAILED 0x0010 +/*! Access attempted while SMN was Blocking Access */ +#define SCM_ERR_SMN_BLOCKING_ACCESS 0x0008 +/*! Access attempted while SCM was CIPHERING */ +#define SCM_ERR_CIPHERING 0x0004 +/*! Access attempted while SCM was ZEROIZING */ +#define SCM_ERR_ZEROIZING 0x0002 +/*! Access attempted while SCM was BUSY */ +#define SCM_ERR_BUSY 0x0001 +/*! @} */ + +/*! + * @defgroup smndbgdetdefs SMN Debug Detector Status Register + * (SCM_DEBUG_DETECT_STAT) + */ +/*! @addtogroup smndbgdetdefs */ +/*! @{ */ +#define SMN_DBG_ZEROS_MASK 0xfffff000 /*!< These bits are zero or reserved */ +#define SMN_DBG_D12 0x0800 /*!< Error detected on Debug Port D12 */ +#define SMN_DBG_D11 0x0400 /*!< Error detected on Debug Port D11 */ +#define SMN_DBG_D10 0x0200 /*!< Error detected on Debug Port D10 */ +#define SMN_DBG_D9 0x0100 /*!< Error detected on Debug Port D9 */ +#define SMN_DBG_D8 0x0080 /*!< Error detected on Debug Port D8 */ +#define SMN_DBG_D7 0x0040 /*!< Error detected on Debug Port D7 */ +#define SMN_DBG_D6 0x0020 /*!< Error detected on Debug Port D6 */ +#define SMN_DBG_D5 0x0010 /*!< Error detected on Debug Port D5 */ +#define SMN_DBG_D4 0x0008 /*!< Error detected on Debug Port D4 */ +#define SMN_DBG_D3 0x0004 /*!< Error detected on Debug Port D3 */ +#define SMN_DBG_D2 0x0002 /*!< Error detected on Debug Port D2 */ +#define SMN_DBG_D1 0x0001 /*!< Error detected on Debug Port D1 */ +/*! @} */ + +/*! Mask for the usable bits of the Sequence Start Register + (#SMN_SEQUENCE_START) */ +#define SMN_SEQUENCE_START_MASK 0x0000ffff + +/*! Mask for the usable bits of the Sequence End Register + (#SMN_SEQUENCE_END) */ +#define SMN_SEQUENCE_END_MASK 0x0000ffff + +/*! Mask for the usable bits of the Sequence Check Register + (#SMN_SEQUENCE_CHECK) */ +#define SMN_SEQUENCE_CHECK_MASK 0x0000ffff + +/*! Mask for the usable bits of the Bit Counter Register + (#SMN_BIT_COUNT) */ +#define SMN_BIT_COUNT_MASK 0x000007ff + +/*! Mask for the usable bits of the Bit Bank Increment Size Register + (#SMN_BITBANK_INC_SIZE) */ +#define SMN_BITBANK_INC_SIZE_MASK 0x000007ff + +/*! Mask for the usable bits of the Bit Bank Decrement Register + (#SMN_BITBANK_DECREMENT) */ +#define SMN_BITBANK_DECREMENT_MASK 0x000007ff + +/*! Mask for the usable bits of the Compare Size Register + (#SMN_COMPARE_SIZE) */ +#define SMN_COMPARE_SIZE_MASK 0x0000003f + +/* Close out marker for C++ compilers */ +#ifdef __cplusplus +} +#endif +#endif /* __ASM_ARCH_MXC_SCC_DRIVER_H__ */ diff --git a/include/linux/mxc_si4702.h b/include/linux/mxc_si4702.h new file mode 100644 index 000000000000..d1d67cc35dcc --- /dev/null +++ b/include/linux/mxc_si4702.h @@ -0,0 +1,39 @@ +/* + * linux/drivers/char/mxc_si4702.h + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup Character device driver for SI4702 FM radio + */ + +/* + * @file mxc_si4702.h + * + * @brief SI4702 Radio FM driver + * + * @ingroup Character + */ + +#ifndef _MXC_SI4702_FM_H +#define _MXC_SI4702_FM_H + +/* define IOCTL command */ +#define SI4702_GETVOLUME _IOR('S', 0x10, unsigned int) +#define SI4702_SETVOLUME _IOW('S', 0x11, unsigned int) +#define SI4702_MUTEON _IO('S', 0x12) +#define SI4702_MUTEOFF _IO('S', 0x13) +#define SI4702_SELECT _IOW('S', 0x14, unsigned int) +#define SI4702_SEEK _IOWR('S', 0x15, unsigned int) + +#endif /* _MXC_SI4702_FM_H */ diff --git a/include/linux/mxc_sim_interface.h b/include/linux/mxc_sim_interface.h new file mode 100644 index 000000000000..2d578763bcf5 --- /dev/null +++ b/include/linux/mxc_sim_interface.h @@ -0,0 +1,108 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_sim_interface.h + * + * @brief Driver for Freescale IMX SIM interface + * + */ + +#ifndef MXC_SIM_INTERFACE_H +#define MXC_SIM_INTERFACE_H + +#define SIM_ATR_LENGTH_MAX 32 + +/* Raw ATR SIM_IOCTL_GET_ATR */ +typedef struct { + uint32_t size; /* length of ATR received */ + uint8_t t[SIM_ATR_LENGTH_MAX]; /* raw ATR string received */ +} sim_atr_t; + +/* Communication parameters for SIM_IOCTL_[GET|SET]_PARAM */ +typedef struct { + uint8_t convention; /* direct = 0, indirect = 1 */ + uint8_t FI, DI; /* frequency multiplier and devider indices */ + uint8_t PI1, II; /* programming voltage and current indices */ + uint8_t N; /* extra guard time */ + uint8_t T; /* protocol type: T0 = 0, T1 = 1 */ + uint8_t PI2; /* programming voltage 2 value */ + uint8_t WWT; /* working wait time */ +} sim_param_t; + +/* ISO7816-3 protocols */ +#define SIM_PROTOCOL_T0 0 +#define SIM_PROTOCOL_T1 1 + +/* Transfer data for SIM_IOCTL_XFER */ +typedef struct { + uint8_t *xmt_buffer; /* transmit buffer pointer */ + int32_t xmt_length; /* transmit buffer length */ + uint8_t *rcv_buffer; /* receive buffer pointer */ + int32_t rcv_length; /* receive buffer length */ + int type; /* transfer type: TPDU = 0, PTS = 1 */ + int timeout; /* transfer timeout in milliseconds */ + uint8_t sw1; /* status word 1 */ + uint8_t sw2; /* status word 2 */ +} sim_xfer_t; + +/* Transfer types for SIM_IOCTL_XFER */ +#define SIM_XFER_TYPE_TPDU 0 +#define SIM_XFER_TYPE_PTS 1 + +/* Interface power states */ +#define SIM_POWER_OFF 0 +#define SIM_POWER_ON 1 + +/* Return values for SIM_IOCTL_GET_PRESENSE */ +#define SIM_PRESENT_REMOVED 0 +#define SIM_PRESENT_DETECTED 1 +#define SIM_PRESENT_OPERATIONAL 2 + +/* Return values for SIM_IOCTL_GET_ERROR */ +#define SIM_OK 0 +#define SIM_E_ACCESS 1 +#define SIM_E_TPDUSHORT 2 +#define SIM_E_PTSEMPTY 3 +#define SIM_E_INVALIDXFERTYPE 4 +#define SIM_E_INVALIDXMTLENGTH 5 +#define SIM_E_INVALIDRCVLENGTH 6 +#define SIM_E_NACK 7 +#define SIM_E_TIMEOUT 8 +#define SIM_E_NOCARD 9 +#define SIM_E_PARAM_FI_INVALID 10 +#define SIM_E_PARAM_DI_INVALID 11 +#define SIM_E_PARAM_FBYD_WITHFRACTION 12 +#define SIM_E_PARAM_FBYD_NOTDIVBY8OR12 13 +#define SIM_E_PARAM_DIVISOR_RANGE 14 +#define SIM_E_MALLOC 15 +#define SIM_E_IRQ 16 +#define SIM_E_POWERED_ON 17 +#define SIM_E_POWERED_OFF 18 + +/* ioctl encodings */ +#define SIM_IOCTL_BASE 0xc0 +#define SIM_IOCTL_GET_PRESENSE _IOR(SIM_IOCTL_BASE, 1, int) +#define SIM_IOCTL_GET_ATR _IOR(SIM_IOCTL_BASE, 2, sim_atr_t) +#define SIM_IOCTL_GET_PARAM_ATR _IOR(SIM_IOCTL_BASE, 3, sim_param_t) +#define SIM_IOCTL_GET_PARAM _IOR(SIM_IOCTL_BASE, 4, sim_param_t) +#define SIM_IOCTL_SET_PARAM _IOW(SIM_IOCTL_BASE, 5, sim_param_t) +#define SIM_IOCTL_XFER _IOR(SIM_IOCTL_BASE, 6, sim_xfer_t) +#define SIM_IOCTL_POWER_ON _IO(SIM_IOCTL_BASE, 7) +#define SIM_IOCTL_POWER_OFF _IO(SIM_IOCTL_BASE, 8) +#define SIM_IOCTL_WARM_RESET _IO(SIM_IOCTL_BASE, 9) +#define SIM_IOCTL_COLD_RESET _IO(SIM_IOCTL_BASE, 10) +#define SIM_IOCTL_CARD_LOCK _IO(SIM_IOCTL_BASE, 11) +#define SIM_IOCTL_CARD_EJECT _IO(SIM_IOCTL_BASE, 12) + +#endif diff --git a/include/linux/mxc_srtc.h b/include/linux/mxc_srtc.h new file mode 100644 index 000000000000..a61426443e53 --- /dev/null +++ b/include/linux/mxc_srtc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file mxc_srtc.h + * + * @brief SRTC IOCTL definitions + * + * @ingroup RTC + */ + + +#define RTC_READ_TIME_47BIT _IOR('p', 0x20, unsigned long long) +/* blocks until LPSCMR is set, returns difference */ +#define RTC_WAIT_TIME_SET _IOR('p', 0x21, int64_t) diff --git a/include/linux/mxc_v4l2.h b/include/linux/mxc_v4l2.h new file mode 100644 index 000000000000..530cf91f4b57 --- /dev/null +++ b/include/linux/mxc_v4l2.h @@ -0,0 +1,48 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/*! + * @file arch-mxc/mxc_v4l2.h + * + * @brief mxc V4L2 private structures + * + * @ingroup MXC_V4L2_CAPTURE + */ + +#ifndef __ASM_ARCH_MXC_V4L2_H__ +#define __ASM_ARCH_MXC_V4L2_H__ + +/* + * For IPUv1 and IPUv3, V4L2_CID_MXC_ROT means encoder ioctl ID. + * And V4L2_CID_MXC_VF_ROT is viewfinder ioctl ID only for IPUv1 and IPUv3. + */ +#define V4L2_CID_MXC_ROT (V4L2_CID_PRIVATE_BASE + 0) +#define V4L2_CID_MXC_FLASH (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_MXC_VF_ROT (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 3) + +#define V4L2_MXC_ROTATE_NONE 0 +#define V4L2_MXC_ROTATE_VERT_FLIP 1 +#define V4L2_MXC_ROTATE_HORIZ_FLIP 2 +#define V4L2_MXC_ROTATE_180 3 +#define V4L2_MXC_ROTATE_90_RIGHT 4 +#define V4L2_MXC_ROTATE_90_RIGHT_VFLIP 5 +#define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6 +#define V4L2_MXC_ROTATE_90_LEFT 7 + +struct v4l2_mxc_offset { + uint32_t u_offset; + uint32_t v_offset; +}; + +#endif diff --git a/include/linux/mxcfb.h b/include/linux/mxcfb.h new file mode 100644 index 000000000000..034d384d9874 --- /dev/null +++ b/include/linux/mxcfb.h @@ -0,0 +1,171 @@ +/* + * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +/* + * @file arch-mxc/ mxcfb.h + * + * @brief Global header file for the MXC Frame buffer + * + * @ingroup Framebuffer + */ +#ifndef __ASM_ARCH_MXCFB_H__ +#define __ASM_ARCH_MXCFB_H__ + +#include + +#define FB_SYNC_OE_LOW_ACT 0x80000000 +#define FB_SYNC_CLK_LAT_FALL 0x40000000 +#define FB_SYNC_DATA_INVERT 0x20000000 +#define FB_SYNC_CLK_IDLE_EN 0x10000000 +#define FB_SYNC_SHARP_MODE 0x08000000 +#define FB_SYNC_SWAP_RGB 0x04000000 + +struct mxcfb_gbl_alpha { + int enable; + int alpha; +}; + +struct mxcfb_loc_alpha { + int enable; + int alpha_in_pixel; + unsigned long alpha_phy_addr0; + unsigned long alpha_phy_addr1; +}; + +struct mxcfb_color_key { + int enable; + __u32 color_key; +}; + +struct mxcfb_pos { + __u16 x; + __u16 y; +}; + +struct mxcfb_gamma { + int enable; + int constk[16]; + int slopek[16]; +}; + +struct mxcfb_rect { + __u32 top; + __u32 left; + __u32 width; + __u32 height; +}; + +#define GRAYSCALE_8BIT 0x1 +#define GRAYSCALE_8BIT_INVERTED 0x2 + +#define AUTO_UPDATE_MODE_REGION_MODE 0 +#define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1 + +#define UPDATE_SCHEME_SNAPSHOT 0 +#define UPDATE_SCHEME_QUEUE 1 +#define UPDATE_SCHEME_QUEUE_AND_MERGE 2 + +#define UPDATE_MODE_PARTIAL 0x0 +#define UPDATE_MODE_FULL 0x1 + +#define WAVEFORM_MODE_AUTO 257 + +#define TEMP_USE_AMBIENT 0x1000 + +#define EPDC_FLAG_ENABLE_INVERSION 0x01 +#define EPDC_FLAG_FORCE_MONOCHROME 0x02 +#define EPDC_FLAG_USE_ALT_BUFFER 0x100 + +#define FB_POWERDOWN_DISABLE -1 + +struct mxcfb_alt_buffer_data { + __u32 phys_addr; + __u32 width; /* width of entire buffer */ + __u32 height; /* height of entire buffer */ + struct mxcfb_rect alt_update_region; /* region within buffer to update */ +}; + +struct mxcfb_update_data { + struct mxcfb_rect update_region; + __u32 waveform_mode; + __u32 update_mode; + __u32 update_marker; + int temp; + uint flags; + struct mxcfb_alt_buffer_data alt_buffer_data; +}; + +/* + * Structure used to define waveform modes for driver + * Needed for driver to perform auto-waveform selection + */ +struct mxcfb_waveform_modes { + int mode_init; + int mode_du; + int mode_gc4; + int mode_gc8; + int mode_gc16; + int mode_gc32; +}; + +#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t) +#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha) +#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key) +#define MXCFB_SET_OVERLAY_POS _IOWR('F', 0x24, struct mxcfb_pos) +#define MXCFB_GET_FB_IPU_CHAN _IOR('F', 0x25, u_int32_t) +#define MXCFB_SET_LOC_ALPHA _IOWR('F', 0x26, struct mxcfb_loc_alpha) +#define MXCFB_SET_LOC_ALP_BUF _IOW('F', 0x27, unsigned long) +#define MXCFB_SET_GAMMA _IOW('F', 0x28, struct mxcfb_gamma) +#define MXCFB_GET_FB_IPU_DI _IOR('F', 0x29, u_int32_t) +#define MXCFB_GET_DIFMT _IOR('F', 0x2A, u_int32_t) +#define MXCFB_GET_FB_BLANK _IOR('F', 0x2B, u_int32_t) +#define MXCFB_SET_DIFMT _IOW('F', 0x2C, u_int32_t) + +/* IOCTLs for E-ink panel updates */ +#define MXCFB_SET_WAVEFORM_MODES _IOW('F', 0x2B, struct mxcfb_waveform_modes) +#define MXCFB_SET_TEMPERATURE _IOW('F', 0x2C, int32_t) +#define MXCFB_SET_AUTO_UPDATE_MODE _IOW('F', 0x2D, __u32) +#define MXCFB_SEND_UPDATE _IOW('F', 0x2E, struct mxcfb_update_data) +#define MXCFB_WAIT_FOR_UPDATE_COMPLETE _IOW('F', 0x2F, __u32) +#define MXCFB_SET_PWRDOWN_DELAY _IOW('F', 0x30, int32_t) +#define MXCFB_GET_PWRDOWN_DELAY _IOR('F', 0x31, int32_t) +#define MXCFB_SET_UPDATE_SCHEME _IOW('F', 0x32, __u32) + +#ifdef __KERNEL__ + +extern struct fb_videomode mxcfb_modedb[]; +extern int mxcfb_modedb_sz; + +enum { + MXCFB_REFRESH_OFF, + MXCFB_REFRESH_AUTO, + MXCFB_REFRESH_PARTIAL, +}; + +enum { + MXC_DISP_SPEC_DEV = 0, + MXC_DISP_DDC_DEV = 1, +}; + +int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode, + struct mxcfb_rect *update_region); +void mxcfb_register_mode(int disp_port, + const struct fb_videomode *modedb, + int num_modes, int dev_mode); + +void mxcfb_register_presetup(int disp_port, + int (*pre_setup)(struct fb_info *info)); + +int mxc_elcdif_frame_addr_setup(dma_addr_t phys); +#endif /* __KERNEL__ */ +#endif diff --git a/include/linux/mxcfb_epdc_kernel.h b/include/linux/mxcfb_epdc_kernel.h new file mode 100644 index 000000000000..3c474dee4f6b --- /dev/null +++ b/include/linux/mxcfb_epdc_kernel.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _MXCFB_EPDC_KERNEL +#define _MXCFB_EPDC_KERNEL + +void mxc_epdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes, + struct fb_info *info); +int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info); +int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info); +int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data, + struct fb_info *info); +int mxc_epdc_fb_wait_update_complete(u32 update_marker, struct fb_info *info); +int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay, + struct fb_info *info); +int mxc_epdc_get_pwrdown_delay(struct fb_info *info); +int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info); + +#endif diff --git a/include/linux/phy.h b/include/linux/phy.h index 987e111f7b11..d63736a84002 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -498,7 +498,7 @@ void phy_stop_machine(struct phy_device *phydev); int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); int phy_mii_ioctl(struct phy_device *phydev, - struct mii_ioctl_data *mii_data, int cmd); + struct ifreq *ifr, int cmd); int phy_start_interrupts(struct phy_device *phydev); void phy_print_status(struct phy_device *phydev); struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id); diff --git a/include/linux/pmic_adc.h b/include/linux/pmic_adc.h new file mode 100644 index 000000000000..a0c659989ab2 --- /dev/null +++ b/include/linux/pmic_adc.h @@ -0,0 +1,455 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef __ASM_ARCH_MXC_PMIC_ADC_H__ +#define __ASM_ARCH_MXC_PMIC_ADC_H__ + +/*! + * @defgroup PMIC_ADC PMIC Digitizer Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_adc.h + * @brief This is the header of PMIC ADC driver. + * + * @ingroup PMIC_ADC + */ + +#include +#include +#include + +/*! + * @name IOCTL user space interface + */ + +/*! @{ */ +/*! + * Initialize ADC. + * Argument type: none. + */ +#define PMIC_ADC_INIT _IO('p', 0xb0) +/*! + * De-initialize ADC. + * Argument type: none. + */ +#define PMIC_ADC_DEINIT _IO('p', 0xb1) +/*! + * Convert one channel. + * Argument type: pointer to t_adc_convert_param. + */ +#define PMIC_ADC_CONVERT _IOWR('p', 0xb2, int) +/*! + * Convert one channel eight samples. + * Argument type: pointer to t_adc_convert_param. + */ +#define PMIC_ADC_CONVERT_8X _IOWR('p', 0xb3, int) +/*! + * Convert multiple channels. + * Argument type: pointer to t_adc_convert_param. + */ +#define PMIC_ADC_CONVERT_MULTICHANNEL _IOWR('p', 0xb4, int) +/*! + * Set touch screen operation mode. + * Argument type: t_touch_mode. + */ +#define PMIC_ADC_SET_TOUCH_MODE _IOW('p', 0xb5, int) +/*! + * Get touch screen operation mode. + * Argument type: pointer to t_touch_mode. + */ +#define PMIC_ADC_GET_TOUCH_MODE _IOR('p', 0xb6, int) +/*! + * Get touch screen sample. + * Argument type: pointer to t_touch_sample. + */ +#define PMIC_ADC_GET_TOUCH_SAMPLE _IOWR('p', 0xb7, int) +/*! + * Get battery current. + * Argument type: pointer to unsigned short. + */ +#define PMIC_ADC_GET_BATTERY_CURRENT _IOR('p', 0xb8, int) +/*! + * Activate comparator. + * Argument type: pointer to t_adc_comp_param. + */ +#define PMIC_ADC_ACTIVATE_COMPARATOR _IOW('p', 0xb9, int) +/*! + * De-active comparator. + * Argument type: none. + */ +#define PMIC_ADC_DEACTIVE_COMPARATOR _IOW('p', 0xba, int) + +/*! + * Install touch screen read interface. + */ +#define TOUCH_SCREEN_READ_INSTALL _IOWR('D', 4, int) +/*! + * Remove touch screen read interface. + */ +#define TOUCH_SCREEN_READ_UNINSTALL _IOWR('D', 5, int) + +/*! @{ */ +/*! + * @name Touch Screen minimum and maximum values + */ +#define TS_X_MIN 80 /*! < Minimum X */ +#define TS_Y_MIN 80 /*! < Minimum Y */ + +#define TS_X_MAX 1000 /*! < Maximum X */ +#define TS_Y_MAX 1000 /*! < Maximum Y */ +/*! @} */ +/*! + * This enumeration defines input channels for PMIC ADC + */ + +typedef enum { + BATTERY_VOLTAGE, + BATTERY_CURRENT, + CHARGE_VOLTAGE, + CHARGE_CURRENT, + APPLICATION_SUPPLY, + TS_X_POS1, + TS_X_POS2, + TS_Y_POS1, + TS_Y_POS2, + GEN_PURPOSE_AD4, + GEN_PURPOSE_AD5, + GEN_PURPOSE_AD6, + GEN_PURPOSE_AD7, + GEN_PURPOSE_AD8, + GEN_PURPOSE_AD9, + GEN_PURPOSE_AD10, + GEN_PURPOSE_AD11, + USB_ID, + LICELL, + RAWEXTBPLUSSENSE, + MPBSENSE, + BATSENSE, + GND, + THERMISTOR, + DIE_TEMP +} t_channel; + +/*! + * This enumeration defines reason of ADC Comparator interrupt. + */ +typedef enum { + /*! + * Greater than WHIGH + */ + GTWHIGH, + /*! + * Less than WLOW + */ + LTWLOW, +} t_comp_exception; + +/*! + * ADC comparator callback function type + */ +typedef void (*t_comparator_cb) (t_comp_exception reason); + +/*! + * This enumeration defines the touch screen operation modes. + */ +typedef enum { + /*! + * Touch Screen X position + */ + TS_X_POSITION = 0, + /*! + * Touch Screen Y position + */ + TS_Y_POSITION = 1, + /*! + * Pressure + */ + TS_PRESSURE = 2, + /*! + * Plate X + */ + TS_PLATE_X = 3, + /*! + * Plate Y + */ + TS_PLATE_Y = 4, + /*! + * Standby + */ + TS_STANDBY = 5, + /*! + * No touch screen, TSX1, TSX2, TSY1 and TSY2 are used as general + * purpose A/D inputs. + */ + TS_NONE = 6, +} t_touch_mode; +/*! + * This structure is used to report touch screen value. + */ +typedef struct { +/*! + * Touch Screen X position + */ + unsigned int x_position; + /*! + * Touch Screen X position1 + */ + unsigned int x_position1; + /*! + * Touch Screen X position2 + */ + unsigned int x_position2; + /*! + * Touch Screen X position3 + */ + unsigned int x_position3; + /*! + * Touch Screen Y position + */ + unsigned int y_position; + /*! + * Touch Screen Y position1 + */ + unsigned int y_position1; + /*! + * Touch Screen Y position2 + */ + unsigned int y_position2; + /*! + * Touch Screen Y position3 + */ + unsigned int y_position3; + /*! + * Touch Screen contact value + */ + unsigned int contact_resistance; +} t_touch_screen; + +/*! + * This enumeration defines ADC conversion modes. + */ +typedef enum { + /*! + * Sample 8 channels, 1 sample per channel + */ + ADC_8CHAN_1X = 0, + /*! + * Sample 1 channel 8 times + */ + ADC_1CHAN_8X, +} t_conversion_mode; + +/*! + * This structure is used with IOCTL code \a PMIC_ADC_CONVERT, + * \a PMIC_ADC_CONVERT_8X and \a PMIC_ADC_CONVERT_MULTICHANNEL. + */ + +typedef struct { + /*! + * channel or channels to be sampled. + */ + t_channel channel; + /*! + * holds up to 16 sampling results + */ + unsigned short result[16]; +} t_adc_convert_param; + +/*! + * This structure is used to activate/deactivate ADC comparator. + */ +typedef struct { + /*! + * wlow. + */ + unsigned char wlow; + /*! + * whigh. + */ + unsigned char whigh; + /*! + * channel to monitor + */ + t_channel channel; + /*! + * callback function. + */ + t_comparator_cb callback; +} t_adc_comp_param; + +/* EXPORTED FUNCTIONS */ + +#ifdef __KERNEL__ +/*! + * This function initializes all ADC registers with default values. This + * function also registers the interrupt events. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_init(void); + +/*! + * This function disables the ADC, de-registers the interrupt events. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_deinit(void); + +/*! + * This function triggers a conversion and returns one sampling result of one + * channel. + * + * @param channel The channel to be sampled + * @param result The pointer to the conversion result. The memory + * should be allocated by the caller of this function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ + +PMIC_STATUS pmic_adc_convert(t_channel channel, unsigned short *result); + +/*! + * This function triggers a conversion and returns eight sampling results of + * one channel. + * + * @param channel The channel to be sampled + * @param result The pointer to array to store eight sampling results. + * The memory should be allocated by the caller of this + * function. + * + * @return This function returns PMIC_SUCCESS if successful. + */ + +PMIC_STATUS pmic_adc_convert_8x(t_channel channel, unsigned short *result); + +/*! + * This function triggers a conversion and returns sampling results of each + * specified channel. + * + * @param channels This input parameter is bitmap to specify channels + * to be sampled. + * @param result The pointer to array to store sampling result. + * The order of the result in the array is from lowest + * channel number to highest channel number of the + * sampled channels. + * The memory should be allocated by the caller of this + * function. + * Note that the behavior of this function might differ + * from one platform to another regarding especially + * channels order. + * + * @return This function returns PMIC_SUCCESS if successful. + */ + +PMIC_STATUS pmic_adc_convert_multichnnel(t_channel channels, + unsigned short *result); + +/*! + * This function sets touch screen operation mode. + * + * @param touch_mode Touch screen operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_set_touch_mode(t_touch_mode touch_mode); + +/*! + * This function retrieves the current touch screen operation mode. + * + * @param touch_mode Pointer to the retrieved touch screen operation + * mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_touch_mode(t_touch_mode *touch_mode); + +/*! + * This function retrieves the current touch screen operation mode. + * + * @param touch_sample Pointer to touch sample. + * @param wait Indicates if this function needs to block or not. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_touch_sample(t_touch_screen *ts_value, int wait); + +/*! + * This function starts a Battery Current mode conversion. + * + * @param mode Conversion mode. + * @param result Battery Current measurement result. + * if \a mode = ADC_8CHAN_1X, the result is \n + * result[0] = (BATTP - BATT_I) \n + * if \a mode = ADC_1CHAN_8X, the result is \n + * result[0] = BATTP \n + * result[1] = BATT_I \n + * result[2] = BATTP \n + * result[3] = BATT_I \n + * result[4] = BATTP \n + * result[5] = BATT_I \n + * result[6] = BATTP \n + * result[7] = BATT_I + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_get_battery_current(t_conversion_mode mode, + unsigned short *result); + +/*! + * This function actives the comparator. When comparator is activated and ADC + * is enabled, the 8th converted value will be digitally compared against the + * window defined by WLOW and WHIGH registers. + * + * @param low Comparison window low threshold (WLOW). + * @param high Comparison window high threshold (WHIGH). + * @param callback Callback function to be called when the converted + * value is beyond the comparison window. The callback + * function will pass a parameter of type + * \b t_comp_expection to indicate the reason of + * comparator exception. + * + * @return This function returns PMIC_SUCCESS if successful. + */ + +PMIC_STATUS pmic_adc_active_comparator(unsigned char low, + unsigned char high, + t_channel channel, + t_comparator_cb callback); + +/*! + * This function de-actives the comparator. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_adc_deactive_comparator(void); + +/*! + * This function enables the touch screen read interface. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_adc_install_ts(void); + +/*! + * This function disables the touch screen read interface. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_adc_remove_ts(void); + +int is_pmic_adc_ready(void); + +#endif /* _KERNEL */ +#endif /* __ASM_ARCH_MXC_PMIC_ADC_H__ */ diff --git a/include/linux/pmic_battery.h b/include/linux/pmic_battery.h new file mode 100644 index 000000000000..4f719e44d074 --- /dev/null +++ b/include/linux/pmic_battery.h @@ -0,0 +1,419 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_BATTERY_H__ +#define __ASM_ARCH_MXC_PMIC_BATTERY_H__ + +/*! + * @defgroup PMIC_BATTERY PMIC Battery Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_battery.h + * @brief This is the header of PMIC Battery driver. + * + * @ingroup PMIC_BATTERY + */ + +#include +#include +#include + +/*! + * @name IOCTL user space interface + */ + +/*! @{ */ +/*! + * Enable and disable charger. + * Argument type: pointer to t_charger_setting + */ +#define PMIC_BATT_CHARGER_CONTROL _IOW('p', 0xc0, int) +/*! + * Set charger configuration. + * Argument type: pointer to t_charger_setting + */ +#define PMIC_BATT_SET_CHARGER _IOW('p', 0xc1, int) +/*! + * Get charger configuration. + * Argument type: pointer to t_charger_setting + */ +#define PMIC_BATT_GET_CHARGER _IOR('p', 0xc2, int) +/*! + * Get charger current. + * Argument type: pointer to t_charger_setting + */ +#define PMIC_BATT_GET_CHARGER_CURRENT _IOR('p', 0xc3, int) +/*! + * Set EOL control + * Argument type: pointer to t_eol_setting + */ +#define PMIC_BATT_EOL_CONTROL _IOW('p', 0xc4, int) +/*! + * Enable and disable charging LED. + * Argument type: bool + */ +#define PMIC_BATT_LED_CONTROL _IOW('p', 0xc5, int) +/*! + * Enable and disable reverse supply. + * Argument type: bool + */ +#define PMIC_BATT_REV_SUPP_CONTROL _IOW('p', 0xc6, int) +/*! + * Enable and disable unregulated charging mode. + * Argument type: bool + */ +#define PMIC_BATT_UNREG_CONTROL _IOW('p', 0xc7, int) + +/*! + * Set the output controls. + * Argument type: t_control + */ +#define PMIC_BATT_SET_OUT_CONTROL _IOW('p', 0xc8, int) +/*! + * Set the over voltage threshold. + * Argument type: int + */ +#define PMIC_BATT_SET_THRESHOLD _IOW('p', 0xc9, int) + +/*! + * Get the charger voltage. + * Argument type: int + */ +#define PMIC_BATT_GET_CHARGER_VOLTAGE _IOR('p', 0xca, int) +/*! + * Get the battery voltage. + * Argument type: int + */ +#define PMIC_BATT_GET_BATTERY_VOLTAGE _IOR('p', 0xcb, int) +/*! + * Get the battery current. + * Argument type: int + */ +#define PMIC_BATT_GET_BATTERY_CURRENT _IOR('p', 0xcc, int) +/*! + * Get the charger sensor. + * Argument type: int + */ +#define PMIC_BATT_GET_CHARGER_SENSOR _IOR('p', 0xcd, int) +/*! + * Get the battery temperature. + * Argument type: int + */ +#define PMIC_BATT_GET_BATTERY_TEMPERATURE _IOR('p', 0xce, int) +/*! @} */ + +/*! + * This enumeration defines battery chargers. + */ +typedef enum { + BATT_MAIN_CHGR = 0, /*!< Main battery charger */ + BATT_CELL_CHGR, /*!< Cell battery charger */ + BATT_TRCKLE_CHGR /*!< Trickle charger (only available on mc13783) */ +} t_batt_charger; + +/*! + * This enumeration defines the bp threshold. + */ +typedef enum { + BATT_BP_0 = 0, /*!< LOBATL UVDET + 0.2 */ + BATT_BP_1, /*!< LOBATL UVDET + 0.3 */ + BATT_BP_2, /*!< LOBATL UVDET + 0.4 */ + BATT_BP_3 /*!< LOBATL UVDET + 0.5 */ +} t_bp_threshold; + +/*! + * This enumeration of all types of output controls + */ +typedef enum { + /*! + * controlled hardware + */ + CONTROL_HARDWARE = 0, + /*! + * BPFET is driven low, BATTFET is driven high + */ + CONTROL_BPFET_LOW, + /*! + * BPFET is driven high, BATTFET is driven low + */ + CONTROL_BPFET_HIGH, +} t_control; + +/*! + * This enumeration define all battery interrupt + */ +typedef enum { + /*! + * Charge detection interrupt + */ + BAT_IT_CHG_DET, + /*! + * Charge over voltage detection it + */ + BAT_IT_CHG_OVERVOLT, + /*! + * Charge path reverse current it + */ + BAT_IT_CHG_REVERSE, + /*! + * Charge path short circuitin revers supply mode it + */ + BAT_IT_CHG_SHORT_CIRCUIT, + /*! + * Charger has switched its mode (CC to CV or CV to CC) + */ + BAT_IT_CCCV, + /*! + * Charge current has dropped below its threshold + */ + BAT_IT_BELOW_THRESHOLD, +} t_batt_event; + +/*! + * This structure is used for the following battery changer control + * IOCTLs: + * - PMIC_BATT_CHARGER_CONTROL + * - PMIC_BATT_SET_CHARGER + * - PMIC_BATT_GET_CHARGER + */ +typedef struct { + /*! + * Charger + */ + t_batt_charger chgr; + /*! + * Turn on charger + */ + bool on; + /*! + * Charging voltage + */ + unsigned char c_voltage; + /*! + * Charging current + */ + unsigned char c_current; +} t_charger_setting; + +/*! + * This structure is used for EOL setting IOCTL PMIC_BATT_EOL_CONTROL + */ +typedef struct { + /*! + * Enable EOL comparator + */ + bool enable; + /*! + * c_voltage threshold - Used on SC55112 + */ + unsigned char threshold; + /*! + * bp threshold - Used on mc13783 + */ + t_bp_threshold typical; +} t_eol_setting; + +/* EXPORTED FUNCTIONS */ + +#ifdef __KERNEL__ + +/*START: for 3ds hw event*/ +/*! + * Battery event type enum + */ +enum { + BAT_EVENT_CHARGER_PLUG = 0x01, + BAT_EVENT_CHARGER_UNPLUG = 0x02, + BAT_EVENT_CHARGER_OVERVOLTAGE = 0x04, + BAT_EVENT_BATTERY_LOW = 0x08, + BAT_EVENT_POWER_FAILED = 0x10, + BAT_EVENT_CHARGER_FULL = 0x20, +} t_bat_event; +/*END: for 3ds hw event*/ + +/*! + * This function is used to start charging a battery. For different charger, + * different c_voltage and current range are supported. \n + * + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Charging voltage. + * @param c_current Charging current. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_enable_charger(t_batt_charger chgr, + unsigned char c_voltage, + unsigned char c_current); + +/*! + * This function turns off a charger. + * + * @param chgr Charger as defined in \b t_batt_charger. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_disable_charger(t_batt_charger chgr); + +/*! + * This function is used to change the charger setting. + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Charging voltage. + * @param c_current Charging current. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_charger(t_batt_charger chgr, + unsigned char c_voltage, + unsigned char c_current); + +/*! + * This function is used to retrieve the charger setting. + * + * @param chgr Charger as defined in \b t_batt_charger. + * @param c_voltage Output parameter for charging c_voltage setting. + * @param c_current Output parameter for charging current setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_get_charger_setting(t_batt_charger chgr, + unsigned char *c_voltage, + unsigned char *c_current); + +/*! + * This function is retrieves the main battery charging current. + * + * @param c_current Output parameter for charging current setting. + * + * @return This function returns PMIC_SUCCESS if successful. + */ + +PMIC_STATUS pmic_batt_get_charge_current(unsigned short *c_current); + +/*! + * This function enables End-of-Life comparator. + * + * @param threshold End-of-Life threshold. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_enable_eol(unsigned char threshold); + +/*! + * This function enables End-of-Life comparator. + * + * @param typical Falling Edge Threshold threshold. + * @verbatim + * BPDET UVDET LOBATL + * ____ _____ ___________ + * 0 2.6 UVDET + 0.2 + * 1 2.6 UVDET + 0.3 + * 2 2.6 UVDET + 0.4 + * 3 2.6 UVDET + 0.5 + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_bp_enable_eol(t_bp_threshold typical); + +/*! + * This function disables End-of-Life comparator. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_disable_eol(void); + +/*! + * This function sets the output controls. + * It sets the FETOVRD and FETCTRL bits of mc13783 + * + * @param control type of control. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_set_out_control(t_control control); + +/*! + * This function sets over voltage threshold. + * + * @param threshold value of over voltage threshold. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_set_threshold(int threshold); + +/*! + * This function controls charge LED. + * + * @param on If on is true, LED will be turned on, + * or otherwise, LED will be turned off. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_led_control(bool on); + +/*! + * This function sets reverse supply mode. + * + * @param enable If enable is true, reverse supply mode is enable, + * or otherwise, reverse supply mode is disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_reverse_supply(bool enable); + +/*! + * This function sets unregulated charging mode on main battery. + * + * @param enable If enable is true, unregulated charging mode is + * enable, or otherwise, disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_unregulated(bool enable); + +/*! + * This function sets a 5K pull down at CHRGRAW. + * To be used in the dual path charging configuration. + * + * @param enable If enable is true, 5k pull down is + * enable, or otherwise, disabled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_batt_set_5k_pull(bool enable); + +/*! + * This function is used to subscribe on battery event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_event_subscribe(t_batt_event event, void *callback); + +/*! + * This function is used to un subscribe on battery event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_batt_event_unsubscribe(t_batt_event event, void *callback); + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_PMIC_BATTERY_H__ */ diff --git a/include/linux/pmic_external.h b/include/linux/pmic_external.h new file mode 100644 index 000000000000..23aa37e1bfa2 --- /dev/null +++ b/include/linux/pmic_external.h @@ -0,0 +1,435 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_EXTERNAL_H__ +#define __ASM_ARCH_MXC_PMIC_EXTERNAL_H__ + +#ifdef __KERNEL__ +#include +#endif + +/*! + * @defgroup PMIC_DRVRS PMIC Drivers + */ + +/*! + * @defgroup PMIC_CORE PMIC Protocol Drivers + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_external.h + * @brief This file contains interface of PMIC protocol driver. + * + * @ingroup PMIC_CORE + */ + +#include +#include + +/*! + * This is the enumeration of versions of PMIC + */ +typedef enum { + PMIC_MC13783 = 1, /*!< MC13783 */ + PMIC_SC55112 = 2, /*!< SC55112 */ + PMIC_MC13892 = 3, + PMIC_MC34704 = 4 +} pmic_id_t; + +/*! + * @struct pmic_version_t + * @brief PMIC version and revision + */ +typedef struct { + /*! + * PMIC version identifier. + */ + pmic_id_t id; + /*! + * Revision of the PMIC. + */ + int revision; +} pmic_version_t; + +/*! + * struct pmic_event_callback_t + * @brief This structure contains callback function pointer and its + * parameter to be used when un/registering and launching a callback + * for an event. + */ +typedef struct { + /*! + * call back function + */ + void (*func) (void *); + + /*! + * call back function parameter + */ + void *param; +} pmic_event_callback_t; + +/*! + * This structure is used with IOCTL. + * It defines register, register value, register mask and event number + */ +typedef struct { + /*! + * register number + */ + int reg; + /*! + * value of register + */ + unsigned int reg_value; + /*! + * mask of bits, only used with PMIC_WRITE_REG + */ + unsigned int reg_mask; +} register_info; + +/*! + * @name IOCTL definitions for sc55112 core driver + */ +/*! @{ */ +/*! Read a PMIC register */ +#define PMIC_READ_REG _IOWR('P', 0xa0, register_info*) +/*! Write a PMIC register */ +#define PMIC_WRITE_REG _IOWR('P', 0xa1, register_info*) +/*! Subscribe a PMIC interrupt event */ +#define PMIC_SUBSCRIBE _IOR('P', 0xa2, int) +/*! Unsubscribe a PMIC interrupt event */ +#define PMIC_UNSUBSCRIBE _IOR('P', 0xa3, int) +/*! Subscribe a PMIC event for user notification*/ +#define PMIC_NOTIFY_USER _IOR('P', 0xa4, int) +/*! Get the PMIC event occured for which user recieved notification */ +#define PMIC_GET_NOTIFY _IOW('P', 0xa5, int) +/*! @} */ + +/*! + * This is PMIC registers valid bits + */ +#define PMIC_ALL_BITS 0xFFFFFF +#define PMIC_MAX_EVENTS 48 + +#define PMIC_ARBITRATION "NULL" + + +#if defined(CONFIG_MXC_PMIC_MC13892_MODULE) || defined(CONFIG_MXC_PMIC_MC13892) +enum { + REG_INT_STATUS0 = 0, + REG_INT_MASK0, + REG_INT_SENSE0, + REG_INT_STATUS1, + REG_INT_MASK1, + REG_INT_SENSE1, + REG_PU_MODE_S, + REG_IDENTIFICATION, + REG_UNUSED0, + REG_ACC0, + REG_ACC1, /*10 */ + REG_UNUSED1, + REG_UNUSED2, + REG_POWER_CTL0, + REG_POWER_CTL1, + REG_POWER_CTL2, + REG_REGEN_ASSIGN, + REG_UNUSED3, + REG_MEM_A, + REG_MEM_B, + REG_RTC_TIME, /*20 */ + REG_RTC_ALARM, + REG_RTC_DAY, + REG_RTC_DAY_ALARM, + REG_SW_0, + REG_SW_1, + REG_SW_2, + REG_SW_3, + REG_SW_4, + REG_SW_5, + REG_SETTING_0, /*30 */ + REG_SETTING_1, + REG_MODE_0, + REG_MODE_1, + REG_POWER_MISC, + REG_UNUSED4, + REG_UNUSED5, + REG_UNUSED6, + REG_UNUSED7, + REG_UNUSED8, + REG_UNUSED9, /*40 */ + REG_UNUSED10, + REG_UNUSED11, + REG_ADC0, + REG_ADC1, + REG_ADC2, + REG_ADC3, + REG_ADC4, + REG_CHARGE, + REG_USB0, + REG_USB1, /*50 */ + REG_LED_CTL0, + REG_LED_CTL1, + REG_LED_CTL2, + REG_LED_CTL3, + REG_UNUSED12, + REG_UNUSED13, + REG_TRIM0, + REG_TRIM1, + REG_TEST0, + REG_TEST1, /*60 */ + REG_TEST2, + REG_TEST3, + REG_TEST4, +}; + +typedef enum { + EVENT_ADCDONEI = 0, + EVENT_ADCBISDONEI = 1, + EVENT_TSI = 2, + EVENT_VBUSVI = 3, + EVENT_IDFACI = 4, + EVENT_USBOVI = 5, + EVENT_CHGDETI = 6, + EVENT_CHGFAULTI = 7, + EVENT_CHGREVI = 8, + EVENT_CHGRSHORTI = 9, + EVENT_CCCVI = 10, + EVENT_CHGCURRI = 11, + EVENT_BPONI = 12, + EVENT_LOBATLI = 13, + EVENT_LOBATHI = 14, + EVENT_IDFLOATI = 19, + EVENT_IDGNDI = 20, + EVENT_SE1I = 21, + EVENT_CKDETI = 22, + EVENT_1HZI = 24, + EVENT_TODAI = 25, + EVENT_PWRON3I = 26, + EVENT_PWRONI = 27, + EVENT_WDIRESETI = 29, + EVENT_SYSRSTI = 30, + EVENT_RTCRSTI = 31, + EVENT_PCI = 32, + EVENT_WARMI = 33, + EVENT_MEMHLDI = 34, + EVENT_THWARNLI = 36, + EVENT_THWARNHI = 37, + EVENT_CLKI = 38, + EVENT_SCPI = 40, + EVENT_LBPI = 44, + EVENT_NB, +} type_event; + +typedef enum { + SENSE_VBUSVS = 3, + SENSE_IDFACS = 4, + SENSE_USBOVS = 5, + SENSE_CHGDETS = 6, + SENSE_CHGREVS = 8, + SENSE_CHGRSHORTS = 9, + SENSE_CCCVS = 10, + SENSE_CHGCURRS = 11, + SENSE_BPONS = 12, + SENSE_LOBATLS = 13, + SENSE_LOBATHS = 14, + SENSE_IDFLOATS = 19, + SENSE_IDGNDS = 20, + SENSE_SE1S = 21, + SENSE_PWRONS = 27, + SENSE_THWARNLS = 36, + SENSE_THWARNHS = 37, + SENSE_CLKS = 38, + SENSE_LBPS = 44, + SENSE_NB, +} t_sensor; + +typedef struct { + bool sense_vbusvs; + bool sense_idfacs; + bool sense_usbovs; + bool sense_chgdets; + bool sense_chgrevs; + bool sense_chgrshorts; + bool sense_cccvs; + bool sense_chgcurrs; + bool sense_bpons; + bool sense_lobatls; + bool sense_lobaths; + bool sense_idfloats; + bool sense_idgnds; + bool sense_se1s; + bool sense_pwrons; + bool sense_thwarnls; + bool sense_thwarnhs; + bool sense_clks; + bool sense_lbps; +} t_sensor_bits; + +extern struct i2c_client *mc13892_client; +int pmic_i2c_24bit_read(struct i2c_client *client, unsigned int reg_num, + unsigned int *value); +int pmic_read(int reg_num, unsigned int *reg_val); +int pmic_write(int reg_num, const unsigned int reg_val); +void gpio_pmic_active(void); +void pmic_event_list_init(void); +void mc13892_power_off(void); + +#elif defined(CONFIG_MXC_PMIC_MC34704_MODULE) || defined(CONFIG_MXC_PMIC_MC34704) + +typedef enum { + /* register names for mc34704 */ + REG_MC34704_GENERAL1 = 0x01, + REG_MC34704_GENERAL2 = 0x02, + REG_MC34704_GENERAL3 = 0x03, + REG_MC34704_VGSET1 = 0x04, + REG_MC34704_VGSET2 = 0x05, + REG_MC34704_REG2SET1 = 0x06, + REG_MC34704_REG2SET2 = 0x07, + REG_MC34704_REG3SET1 = 0x08, + REG_MC34704_REG3SET2 = 0x09, + REG_MC34704_REG4SET1 = 0x0A, + REG_MC34704_REG4SET2 = 0x0B, + REG_MC34704_REG5SET1 = 0x0C, + REG_MC34704_REG5SET2 = 0x0D, + REG_MC34704_REG5SET3 = 0x0E, + REG_MC34704_REG6SET1 = 0x0F, + REG_MC34704_REG6SET2 = 0x10, + REG_MC34704_REG6SET3 = 0x11, + REG_MC34704_REG7SET1 = 0x12, + REG_MC34704_REG7SET2 = 0x13, + REG_MC34704_REG7SET3 = 0x14, + REG_MC34704_REG8SET1 = 0x15, + REG_MC34704_REG8SET2 = 0x16, + REG_MC34704_REG8SET3 = 0x17, + REG_MC34704_FAULTS = 0x18, + REG_MC34704_I2CSET1 = 0x19, + REG_MC34704_REG3DAC = 0x49, + REG_MC34704_REG7CR0 = 0x58, + REG_MC34704_REG7DAC = 0x59, + REG_NB = 0x60, +} pmic_reg; + +typedef enum { + /* events for mc34704 */ + EVENT_FLT1 = 0, + EVENT_FLT2, + EVENT_FLT3, + EVENT_FLT4, + EVENT_FLT5, + EVENT_FLT6, + EVENT_FLT7, + EVENT_FLT8, + EVENT_NB, +} type_event; + +typedef enum { + MCU_SENSOR_NOT_SUPPORT +} t_sensor; + +typedef enum { + MCU_SENSOR_BIT_NOT_SUPPORT +} t_sensor_bits; + +#else +typedef int type_event; +typedef int t_sensor; +typedef int t_sensor_bits; + +#endif /* MXC_PMIC_MC34704 */ + +/* EXPORTED FUNCTIONS */ +#ifdef __KERNEL__ + +#if defined(CONFIG_MXC_PMIC) +/*! + * This function is used to determine the PMIC type and its revision. + * + * @return Returns the PMIC type and its revision. + */ +pmic_version_t pmic_get_version(void); + +/*! + * This function is called by PMIC clients to read a register on PMIC. + * + * @param priority priority of access + * @param reg number of register + * @param reg_value return value of register + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_read_reg(int reg, unsigned int *reg_value, + unsigned int reg_mask); +/*! + * This function is called by PMIC clients to write a register on MC13783. + * + * @param priority priority of access + * @param reg number of register + * @param reg_value New value of register + * @param reg_mask Bitmap mask indicating which bits to modify + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_write_reg(int reg, unsigned int reg_value, + unsigned int reg_mask); + +/*! + * This function is called by PMIC clients to subscribe on an event. + * + * @param event_sub structure of event, it contains type of event and callback + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_event_subscribe(type_event event, + pmic_event_callback_t callback); +/*! +* This function is called by PMIC clients to un-subscribe on an event. +* +* @param event_unsub structure of event, it contains type of event and callback +* +* @return This function returns PMIC_SUCCESS if successful. +*/ +PMIC_STATUS pmic_event_unsubscribe(type_event event, + pmic_event_callback_t callback); +/*! +* This function is called to read all sensor bits of PMIC. +* +* @param sensor Sensor to be checked. +* +* @return This function returns true if the sensor bit is high; +* or returns false if the sensor bit is low. +*/ +bool pmic_check_sensor(t_sensor sensor); + +/*! +* This function checks one sensor of PMIC. +* +* @param sensor_bits structure of all sensor bits. +* +* @return This function returns PMIC_SUCCESS if successful. +*/ +PMIC_STATUS pmic_get_sensors(t_sensor_bits *sensor_bits); + +void pmic_event_callback(type_event event); +void pmic_event_list_init(void); + +#endif /*CONFIG_MXC_PMIC*/ +#endif /* __KERNEL__ */ +/* CONFIG_MXC_PMIC_MC13783 || CONFIG_MXC_PMIC_MC9SDZ60 */ + +struct pmic_platform_data { + int (*init)(void *); + int power_key_irq; +}; + +#endif /* __ASM_ARCH_MXC_PMIC_EXTERNAL_H__ */ diff --git a/include/linux/pmic_light.h b/include/linux/pmic_light.h new file mode 100644 index 000000000000..7611f4862390 --- /dev/null +++ b/include/linux/pmic_light.h @@ -0,0 +1,1082 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_LIGHT_H__ +#define __ASM_ARCH_MXC_PMIC_LIGHT_H__ + +/*! + * @defgroup PMIC_LIGHT PMIC Light Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_light.h + * @brief This is the header of PMIC Light driver. + * + * @ingroup PMIC_LIGHT + */ + +#include +#include +#include + +/*! + * @name IOCTL user space interface + */ + +/*! @{ */ +/*! + * Enable Backlight. + * Argument type: none. + */ +#define PMIC_BKLIT_ENABLE _IO('p', 0xe0) +/*! + * Disable Backlight. + * Argument type: none. + */ +#define PMIC_BKLIT_DISABLE _IO('p', 0xe1) +/*! + * Set backlight configuration. + * Argument type: pointer to t_bklit_setting_param + */ +#define PMIC_SET_BKLIT _IOW('p', 0xe2, int) +/*! + * Get backlight configuration. + * Argument type: pointer to t_bklit_setting_param + */ +#define PMIC_GET_BKLIT _IOWR('p', 0xe3, int) +/*! + * Ramp up configuration. + * Argument type: t_bklit_channel + */ +#define PMIC_RAMPUP_BKLIT _IOW('p', 0xe4, int) +/*! + * Ramp down configuration. + * Argument type: t_bklit_channel + */ +#define PMIC_RAMPDOWN_BKLIT _IOW('p', 0xe5, int) +/*! + * Enable Tri-color LED. + * Argument type: t_tcled_enable_param + */ +#define PMIC_TCLED_ENABLE _IOW('p', 0xe6, int) +/*! + * Disable Tri-color LED. + * Argument type: t_funlight_bank + */ +#define PMIC_TCLED_DISABLE _IOW('p', 0xe7, int) +/*! + * Start Tri-color LED pattern. + * Argument type: t_fun_param + */ +#define PMIC_TCLED_PATTERN _IOW('p', 0xe8, int) +/*! + * Enable Backlight & tcled. + * Argument type: none. + */ +#define PMIC_BKLIT_TCLED_ENABLE _IO('p', 0xe9) +/*! + * Disable Backlight & tcled. + * Argument type: none. + */ +#define PMIC_BKLIT_TCLED_DISABLE _IO('p', 0xea) +/*! + * Reset ramp up configuration. + * Argument type: t_bklit_channel + */ +#define PMIC_OFF_RAMPUP_BKLIT _IOW('p', 0xeb, int) +/*! + * Reset ramp down configuration. + * Argument type: t_bklit_channel + */ +#define PMIC_OFF_RAMPDOWN_BKLIT _IOW('p', 0xec, int) +/*! + * Set tcled ind configuration. + * Argument type: t_tcled_ind_param + */ +#define PMIC_SET_TCLED _IOW('p', 0xed, int) +/*! + * Get tcled ind configuration. + * Argument type: t_tcled_ind_param + */ +#define PMIC_GET_TCLED _IOWR('p', 0xee, int) +/*! @} */ +/*! + * @enum t_bklit_mode + * @brief Backlight modes. + */ +typedef enum { + BACKLIGHT_CURRENT_CTRL_MODE, /*! < Current control mode */ + BACKLIGHT_TRIODE_MODE /*! < Triode mode */ +} t_bklit_mode; + +/*! + * @enum t_bklit_channel + * @brief Backlight channels. + */ +typedef enum { + BACKLIGHT_LED1, /*! < Backlight channel 1 */ + BACKLIGHT_LED2, /*! < Backlight channel 2 */ + BACKLIGHT_LED3 /*! < Backlight channel 3 */ +} t_bklit_channel; + +/*! + * @enum t_bklit_strobe_mode + * @brief Backlight Strobe Light Pulsing modes. + */ +typedef enum { + /*! + * No Strobe Light Pulsing + */ + BACKLIGHT_STROBE_NONE, + /*! + * Strobe Light Pulsing at 3.3% duty cycle over 300msec (Driver goes + * into Triode Mode with pulses constrained to 10msec.) + */ + BACKLIGHT_STROBE_FAST, + /*! + * Strobe Light Pulsing at 10% duty cycle over 100msec (Driver goes + * into Triode Mode with pulses constrained to 10msec.) + */ + BACKLIGHT_STROBE_SLOW +} t_bklit_strobe_mode; + +/*! + * @struct t_bklit_setting_param + * @brief Backlight setting. + */ + +typedef struct { + t_bklit_channel channel; /*!< Channel */ + t_bklit_mode mode; /*!< Mode */ + t_bklit_strobe_mode strobe; /*!< Strobe mode */ + unsigned char current_level; /*!< Current level */ + unsigned char duty_cycle; /*!< Duty cycle */ + unsigned char cycle_time; /*!< Cycle time */ + bool edge_slow; /*!< Edge Slow */ + bool en_dis; /*!< Enable disable boost mode */ + unsigned int abms; /*!< Adaptive boost + * mode selection */ + unsigned int abr; /*!< Adaptive + * boost reference */ +} t_bklit_setting_param; + +/*! + * @enum t_funlight_bank + * @brief Tri-color LED fun light banks. + */ +typedef enum { + TCLED_FUN_BANK1 = 0, /*! < Fun light bank 1 */ + TCLED_FUN_BANK2, /*! < Fun light bank 2 */ + TCLED_FUN_BANK3 /*! < Fun light bank 3 */ +} t_funlight_bank; + +/*! + * @enum t_tcled_mode + * @brief Tri-color LED operation modes. + * + * The Tri-Color LED Driver circuitry includes 2 modes of operation. In LED + * Indicator Mode, this circuitry operates as Red and Green LED Drivers with + * flasher timing to indicate GSM network status. In Fun Light Mode, this + * circuitry provides expanded capability for current control and distribution + * that supplements the three channels. + */ +typedef enum { + TCLED_IND_MODE = 0, /*! < LED Indicator Mode */ + TCLED_FUN_MODE /*! < Fun Light Mode */ +} t_tcled_mode; + +/*! + * @struct t_tcled_enable_param + * @brief enable setting. + */ +typedef struct { + t_funlight_bank bank; /*!< Bank */ + t_tcled_mode mode; /*!< Mode */ +} t_tcled_enable_param; + +/*! + * @enum t_ind_channel + * @brief Tri-color LED indicator mode channels. + * + */ + +typedef enum { + TCLED_IND_RED = 0, /*! < Red LED */ + TCLED_IND_GREEN, /*! < Green LED */ + TCLED_IND_BLUE /*! < Blue LED */ +} t_ind_channel; + +/*! + * @enum t_funlight_channel + * @brief Tri-color LED fun light mode channels. + * + */ +typedef enum { + TCLED_FUN_CHANNEL1 = 0, /*! < Fun light channel 1 (Red) */ + TCLED_FUN_CHANNEL2, /*! < Fun light channel 2 (Green) */ + TCLED_FUN_CHANNEL3 /*! < Fun light channel 3 (Blue) */ +} t_funlight_channel; + +/*! + * @enum t_tcled_ind_blink_pattern + * @brief Tri-color LED Indicator Mode blinking mode. + */ +typedef enum { + TCLED_IND_OFF = 0, /*! < Continuous off */ + TCLED_IND_BLINK_1, /*! < 1 / 31 */ + TCLED_IND_BLINK_2, /*! < 2 / 31 */ + TCLED_IND_BLINK_3, /*! < 3 / 31 */ + TCLED_IND_BLINK_4, /*! < 4 / 31 */ + TCLED_IND_BLINK_5, /*! < 5 / 31 */ + TCLED_IND_BLINK_6, /*! < 6 / 31 */ + TCLED_IND_BLINK_7, /*! < 7 / 31 */ + TCLED_IND_BLINK_8, /*! < 8 / 31 */ + TCLED_IND_BLINK_9, /*! < 9 / 31 */ + TCLED_IND_BLINK_10, /*! < 10 / 31 */ + TCLED_IND_BLINK_11, /*! < 11 / 31 */ + TCLED_IND_BLINK_12, /*! < 12 / 31 */ + TCLED_IND_BLINK_13, /*! < 13 / 31 */ + TCLED_IND_BLINK_14, /*! < 14 / 31 */ + TCLED_IND_BLINK_15, /*! < 15 / 31 */ + TCLED_IND_BLINK_16, /*! < 16 / 31 */ + TCLED_IND_BLINK_17, /*! < 17 / 31 */ + TCLED_IND_BLINK_18, /*! < 18 / 31 */ + TCLED_IND_BLINK_19, /*! < 19 / 31 */ + TCLED_IND_BLINK_20, /*! < 20 / 31 */ + TCLED_IND_BLINK_21, /*! < 21 / 31 */ + TCLED_IND_BLINK_22, /*! < 22 / 31 */ + TCLED_IND_BLINK_23, /*! < 23 / 31 */ + TCLED_IND_BLINK_24, /*! < 24 / 31 */ + TCLED_IND_BLINK_25, /*! < 25 / 31 */ + TCLED_IND_BLINK_26, /*! < 26 / 31 */ + TCLED_IND_BLINK_27, /*! < 27 / 31 */ + TCLED_IND_BLINK_28, /*! < 28 / 31 */ + TCLED_IND_BLINK_29, /*! < 29 / 31 */ + TCLED_IND_BLINK_30, /*! < 30 / 31 */ + TCLED_IND_ON /*! < Continuous on */ +} t_tcled_ind_blink_pattern; + +/*! + * @enum t_tcled_cur_level + * @brief Tri-color LED current levels. + */ +typedef enum { + TCLED_CUR_LEVEL_1 = 0, /*! < Tri-Color LED current level 1 */ + TCLED_CUR_LEVEL_2, /*! < Tri-Color LED current level 2 */ + TCLED_CUR_LEVEL_3, /*! < Tri-Color LED current level 3 */ + TCLED_CUR_LEVEL_4 /*! < Tri-Color LED current level 4 */ +} t_tcled_cur_level; + +/*! + * @enum t_tcled_fun_cycle_time + * @brief Tri-color LED fun light mode cycle time. + */ +typedef enum { + TC_CYCLE_TIME_1 = 0, /*! < Tri-Color LED cycle time 1 */ + TC_CYCLE_TIME_2, /*! < Tri-Color LED cycle time 2 */ + TC_CYCLE_TIME_3, /*! < Tri-Color LED cycle time 3 */ + TC_CYCLE_TIME_4 /*! < Tri-Color LED cycle time 4 */ +} t_tcled_fun_cycle_time; + +/*! + * @enum t_tcled_fun_speed + * @brief Tri-color LED fun light mode pattern speed. + */ +typedef enum { + TC_OFF = 0, /*! < Tri-Color pattern off */ + TC_SLOW, /*! < Tri-Color slow pattern */ + TC_FAST /*! < Tri-Color fast pattern */ +} t_tcled_fun_speed; + +/*! + * @enum t_tcled_fun_speed + * @brief Tri-color LED fun light mode pattern speed. + */ +typedef enum { + TC_STROBE_OFF = 0, /*! < No strobe */ + TC_STROBE_SLOW, /*! < Slow strobe pattern */ + TC_STROBE_FAST /*! < fast strobe pattern */ +} t_tcled_fun_strobe_speed; + +/*! + * @enum t_chaselight_pattern + * @brief Tri-color LED fun light mode chasing light patterns. + */ +typedef enum { + PMIC_RGB = 0, /*!< R -> G -> B */ + BGR /*!< B -> G -> R */ +} t_chaselight_pattern; + +/*! + * This enumeration of Fun Light Pattern. + */ +typedef enum { + /*! + * Blended ramps slow + */ + BLENDED_RAMPS_SLOW, + /*! + * Blended ramps fast + */ + BLENDED_RAMPS_FAST, + /*! + * Saw ramps slow + */ + SAW_RAMPS_SLOW, + /*! + * Saw ramps fast + */ + SAW_RAMPS_FAST, + /*! + * Blended bowtie slow + */ + BLENDED_BOWTIE_SLOW, + /*! + * Blended bowtie fast + */ + BLENDED_BOWTIE_FAST, + /*! + * Strobe slow + */ + STROBE_SLOW, + /*! + * Strobe fast + */ + STROBE_FAST, + /*! + * Chasing Light RGB Slow + */ + CHASING_LIGHT_RGB_SLOW, + /*! + * Chasing Light RGB fast + */ + CHASING_LIGHT_RGB_FAST, + /*! + * Chasing Light BGR Slow + */ + CHASING_LIGHT_BGR_SLOW, + /*! + * Chasing Light BGR fast + */ + CHASING_LIGHT_BGR_FAST, +} t_fun_pattern; + +/*! + * @struct t_fun_param + * @brief LED fun pattern IOCTL parameter + */ +typedef struct { + t_funlight_bank bank; /*!< TCLED bank */ + t_funlight_channel channel; /*!< TCLED channel */ + t_fun_pattern pattern; /*!< Fun pattern */ +} t_fun_param; + +/*! + * @enum t_led_channel + * @brief LED channels including backlight and tri-color LEDs. + */ +typedef enum { + AUDIO_LED1, /*! < Backlight channel 1 */ + AUDIO_LED2, /*! < Backlight channel 2 */ + AUDIO_LEDR, /*! < Fun light channel 1 (Red) */ + AUDIO_LEDG, /*! < Fun light channel 2 (Green) */ + AUDIO_LEDB /*! < Fun light channel 3 (Blue) */ +} t_led_channel; + +/*! + * @enum t_aud_path + * @brief LED audio modulation in-out audio channels + */ +typedef enum { + MIXED_RX = 0, /*!< Mixed L & R Channel RX audio */ + TX /*!< TX path */ +} t_aud_path; + +/*! + * @enum t_aud_gain + * @brief LED audio modulation in-out audio channels + */ +typedef enum { + GAIN_MINUS6DB = 0, /*!< -6 dB */ + GAIN_0DB, /*!< 0 dB */ + GAIN_6DB, /*!< 6 dB */ + GAIN_12DB /*!< 12 dB */ +} t_aud_gain; + +/*! + * @struct t_tcled_ind_param + * @brief LED parameter + */ +typedef struct { + t_funlight_bank bank; /*! < tcled bank */ + t_ind_channel channel; /*! < tcled channel */ + t_tcled_cur_level level; /*! < tcled current level */ + t_tcled_ind_blink_pattern pattern; /*! < tcled dutty cycle */ + bool skip; /*! < tcled skip */ + bool rampup; /*! < tcled rampup */ + bool rampdown; /*! < tcled rampdown */ + bool half_current; /*! < tcled half current */ +} t_tcled_ind_param; + +#if defined(CONFIG_MXC_PMIC_MC13892) + +enum curr_level { + LIT_CURR_0 = 0, + LIT_CURR_3, + LIT_CURR_6, + LIT_CURR_9, + LIT_CURR_12, + LIT_CURR_15, + LIT_CURR_18, + LIT_CURR_21, + /* below setting only used for main/aux/keypad */ + LIT_CURR_HI_0, + LIT_CURR_HI_6, + LIT_CURR_HI_12, + LIT_CURR_HI_18, + LIT_CURR_HI_24, + LIT_CURR_HI_30, + LIT_CURR_HI_36, + LIT_CURR_HI_42, +}; + +enum lit_channel { + LIT_MAIN = 0, + LIT_AUX, + LIT_KEY, + LIT_RED, + LIT_GREEN, + LIT_BLUE, +}; + +#endif + +/* EXPORTED FUNCTIONS */ +#ifdef __KERNEL__ +/*! + * This function enables backlight & tcled. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_tcled_master_enable(void); + +/*! + * This function disables backlight & tcled. + * + * @return This function returns PMIC_SUCCESS if successful + */ +PMIC_STATUS pmic_bklit_tcled_master_disable(void); + +/*! + * This function enables backlight. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_master_enable(void); + +/*! + * This function disables backlight. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_master_disable(void); + +/*! + * This function sets backlight current level. + * + * @param channel Backlight channel + * @param level Backlight current level, as the following table. + * @verbatim + * level current + * ------ ----------- + * 0 0 mA + * 1 12 mA + * 2 24 mA + * 3 36 mA + * 4 48 mA + * 5 60 mA + * 6 72 mA + * 7 84 mA + * @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_current(t_bklit_channel channel, + unsigned char level); + +/*! + * This function retrives backlight current level. + * + * @param channel Backlight channel + * @param level Pointer to store backlight current level result. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_current(t_bklit_channel channel, + unsigned char *level); + +/*! + * This function sets a backlight channel duty cycle. + * LED perceived brightness for each zone may be individually set by setting + * duty cycle. The default setting is for 0% duty cycle; this keeps all zone + * drivers turned off even after the master enable command. Each LED current + * sink can be turned on and adjusted for brightness with an independent 4 bit + * word for a duty cycle ranging from 0% to 100% in approximately 6.7% steps. + * + * @param channel Backlight channel. + * @param dc Backlight duty cycle, as the following table. + * @verbatim + * dc Duty Cycle (% On-time over Cycle Time) + * ------ --------------------------------------- + * 0 0% + * 1 6.7% + * 2 13.3% + * 3 20% + * 4 26.7% + * 5 33.3% + * 6 40% + * 7 46.7% + * 8 53.3% + * 9 60% + * 10 66.7% + * 11 73.3% + * 12 80% + * 13 86.7% + * 14 93.3% + * 15 100% + * @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_dutycycle(t_bklit_channel channel, unsigned char dc); + +/*! + * This function retrives a backlight channel duty cycle. + * + * @param channel Backlight channel. + * @param cycle Pointer to backlight duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_dutycycle(t_bklit_channel channel, + unsigned char *dc); + +/*! + * This function sets a backlight channel cycle time. + * Cycle Time is defined as the period of a complete cycle of + * Time_on + Time_off. The default Cycle Time is set to 0.01 seconds such that + * the 100 Hz on-off cycling is averaged out by the eye to eliminate + * flickering. Additionally, the Cycle Time can be programmed to intentionally + * extend the period of on-off cycles for a visual pulsating or blinking effect. + * + * @param period Backlight cycle time, as the following table. + * @verbatim + * period Cycle Time + * -------- ------------ + * 0 0.01 seconds + * 1 0.1 seconds + * 2 0.5 seconds + * 3 2 seconds + * @endverbatim + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_cycle_time(unsigned char period); + +/*! + * This function retrives a backlight channel cycle time setting. + * + * @param period Pointer to save backlight cycle time setting result. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_cycle_time(unsigned char *period); + +/*! + * This function sets backlight operation mode. There are two modes of + * operations: current control and triode mode. + * The Duty Cycle/Cycle Time control is retained in Triode Mode. Audio + * coupling is not available in Triode Mode. + * + * @param channel Backlight channel. + * @param mode Backlight operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_mode(t_bklit_channel channel, t_bklit_mode mode); +/*! + * This function gets backlight operation mode. There are two modes of + * operations: current control and triode mode. + * The Duty Cycle/Cycle Time control is retained in Triode Mode. Audio + * coupling is not available in Triode Mode. + * + * @param channel Backlight channel. + * @param mode Backlight operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_mode(t_bklit_channel channel, t_bklit_mode *mode); +/*! + * This function starts backlight brightness ramp up function; ramp time is + * fixed at 0.5 seconds. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_rampup(t_bklit_channel channel); +/*! + * This function stops backlight brightness ramp up function; + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_off_rampup(t_bklit_channel channel); +/*! + * This function starts backlight brightness ramp down function; ramp time is + * fixed at 0.5 seconds. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_rampdown(t_bklit_channel channel); +/*! + * This function stops backlight brightness ramp down function. + * + * @param channel Backlight channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_off_rampdown(t_bklit_channel channel); +/*! + * This function enables backlight analog edge slowing mode. Analog Edge + * Slowing slows down the transient edges to reduce the chance of coupling LED + * modulation activity into other circuits. Rise and fall times will be targeted + * for approximately 50usec. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_enable_edge_slow(void); + +/*! + * This function disables backlight analog edge slowing mode. The backlight + * drivers will default to an Instant On mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_disable_edge_slow(void); +/*! + * This function gets backlight analog edge slowing mode. DThe backlight + * + * @param edge Edge slowing mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_get_edge_slow(bool *edge); +/*! + * This function sets backlight Strobe Light Pulsing mode. + * + * @param channel Backlight channel. + * @param mode Strobe Light Pulsing mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_bklit_set_strobemode(t_bklit_channel channel, + t_bklit_strobe_mode mode); + +/*! + * This function enables tri-color LED. + * + * @param mode Tri-color LED operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_enable(t_tcled_mode mode, t_funlight_bank bank); +/*! + * This function disables tri-color LED. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_disable(t_funlight_bank bank); +/*! + * This function retrives tri-color LED operation mode. + * + * @param mode Pointer to Tri-color LED operation mode. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_mode(t_tcled_mode *mode, t_funlight_bank bank); +/*! + * This function sets a tri-color LED channel current level in indicator mode. + * + * @param channel Tri-color LED channel. + * @param level Current level. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_set_current(t_ind_channel channel, + t_tcled_cur_level level, + t_funlight_bank bank); +/*! + * This function retrives a tri-color LED channel current level in indicator mode. + * + * @param channel Tri-color LED channel. + * @param level Pointer to current level. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_get_current(t_ind_channel channel, + t_tcled_cur_level *level, + t_funlight_bank bank); +/*! + * This function sets a tri-color LED channel blinking pattern in indication + * mode. + * + * @param channel Tri-color LED channel. + * @param pattern Blinking pattern. + * @param skip If true, skip a cycle after each cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ + +PMIC_STATUS pmic_tcled_ind_set_blink_pattern(t_ind_channel channel, + t_tcled_ind_blink_pattern pattern, + bool skip, t_funlight_bank bank); +/*! + * This function retrives a tri-color LED channel blinking pattern in + * indication mode. + * + * @param channel Tri-color LED channel. + * @param pattern Pointer to Blinking pattern. + * @param skip Pointer to a boolean variable indicating if skip + * a cycle after each cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_ind_get_blink_pattern(t_ind_channel channel, + t_tcled_ind_blink_pattern * + pattern, bool *skip, + t_funlight_bank bank); +/*! + * This function sets a tri-color LED channel current level in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param level Current level. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_current(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_cur_level level); + +/*! + * This function retrives a tri-color LED channel current level + * in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param level Pointer to current level. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_current(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_cur_level *level); + +/*! + * This function sets tri-color LED cycle time in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param ct Cycle time. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_cycletime(t_funlight_bank bank, + t_tcled_fun_cycle_time ct); + +/*! + * This function retrives tri-color LED cycle time in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param ct Pointer to cycle time. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_cycletime(t_funlight_bank bank, + t_tcled_fun_cycle_time *ct); + +/*! + * This function sets a tri-color LED channel duty cycle in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param dc Duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_set_dutycycle(t_funlight_bank bank, + t_funlight_channel channel, + unsigned char dc); + +/*! + * This function retrives a tri-color LED channel duty cycle in Fun Light mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param dc Pointer to duty cycle. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_get_dutycycle(t_funlight_bank bank, + t_funlight_channel channel, + unsigned char *dc); + +/*! + * This function initiates Blended Ramp fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_blendedramps(t_funlight_bank bank, + t_tcled_fun_speed speed); + +/*! + * This function initiates Saw Ramp fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_sawramps(t_funlight_bank bank, + t_tcled_fun_speed speed); + +/*! + * This function initiates Blended Bowtie fun light pattern. + * + * @param bank Tri-color LED bank + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_blendedbowtie(t_funlight_bank bank, + t_tcled_fun_speed speed); + +/*! + * This function initiates Chasing Lights fun light pattern. + * + * @param bank Tri-color LED bank + * @param pattern Chasing light pattern mode. + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_chasinglightspattern(t_funlight_bank bank, + t_chaselight_pattern pattern, + t_tcled_fun_speed speed); + +/*! + * This function initiates Strobe Mode fun light pattern. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param speed Speed of pattern. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_strobe(t_funlight_bank bank, + t_funlight_channel channel, + t_tcled_fun_strobe_speed speed); + +/*! + * This function initiates Tri-color LED brightness Ramp Up function; Ramp time + * is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampup Ramp-up configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_rampup(t_funlight_bank bank, + t_funlight_channel channel, bool rampup); +/*! + * This function gets Tri-color LED brightness Ramp Up function; Ramp time + * is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampup Ramp-up configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_fun_rampup(t_funlight_bank bank, + t_funlight_channel channel, + bool *rampup); + +/*! + * This function initiates Tri-color LED brightness Ramp Down function; Ramp + * time is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampdown Ramp-down configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_rampdown(t_funlight_bank bank, + t_funlight_channel channel, bool rampdown); +/*! + * This function initiates Tri-color LED brightness Ramp Down function; Ramp + * time is fixed at 1 second. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * @param rampdown Ramp-down configuration. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_get_fun_rampdown(t_funlight_bank bank, + t_funlight_channel channel, + bool *rampdown); + +/*! + * This function enables a Tri-color channel triode mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_triode_on(t_funlight_bank bank, + t_funlight_channel channel); + +/*! + * This function disables a Tri-color LED channel triode mode. + * + * @param bank Tri-color LED bank + * @param channel Tri-color LED channel. + * + * @return This function returns PMIC_SUCCESS if successful. + */ +PMIC_STATUS pmic_tcled_fun_triode_off(t_funlight_bank bank, + t_funlight_channel channel); + +/*! + * This function enables Tri-color LED edge slowing. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_enable_edge_slow(void); + +/*! + * This function disables Tri-color LED edge slowing. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_disable_edge_slow(void); + +/*! + * This function enables Tri-color LED half current mode. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_enable_half_current(void); + +/*! + * This function disables Tri-color LED half current mode. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_disable_half_current(void); + +/*! + * This function enables backlight or Tri-color LED audio modulation. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_enable_audio_modulation(t_led_channel channel, + t_aud_path path, + t_aud_gain gain, + bool lpf_bypass); + +/*! + * This function disables backlight or Tri-color LED audio modulation. + * + * @return This function returns PMIC_NOT_SUPPORTED. + */ +PMIC_STATUS pmic_tcled_disable_audio_modulation(void); +/*! + * This function enables the boost mode. + * Only on mc13783 2.0 or higher + * + * @param en_dis Enable or disable the boost mode + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_set_boost_mode(bool en_dis); + +/*! + * This function gets the boost mode. + * Only on mc13783 2.0 or higher + * + * @param en_dis Enable or disable the boost mode + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_get_boost_mode(bool *en_dis); + +/*! + * This function sets boost mode configuration + * Only on mc13783 2.0 or higher + * + * @param abms Define adaptive boost mode selection + * @param abr Define adaptive boost reference + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_config_boost_mode(unsigned int abms, unsigned int abr); + +/*! + * This function gets boost mode configuration + * Only on mc13783 2.0 or higher + * + * @param abms Define adaptive boost mode selection + * @param abr Define adaptive boost reference + * + * @return This function returns 0 if successful. + */ +PMIC_STATUS pmic_bklit_gets_boost_mode(unsigned int *abms, unsigned int *abr); + +#if defined(CONFIG_MXC_PMIC_MC13892) + +PMIC_STATUS mc13892_bklit_set_current(enum lit_channel channel, + unsigned char level); +PMIC_STATUS mc13892_bklit_get_current(enum lit_channel channel, + unsigned char *level); +PMIC_STATUS mc13892_bklit_set_dutycycle(enum lit_channel channel, + unsigned char dc); +PMIC_STATUS mc13892_bklit_get_dutycycle(enum lit_channel channel, + unsigned char *dc); +PMIC_STATUS mc13892_bklit_set_ramp(enum lit_channel channel, int flag); +PMIC_STATUS mc13892_bklit_get_ramp(enum lit_channel channel, int *flag); +PMIC_STATUS mc13892_bklit_set_blink_p(enum lit_channel channel, int period); +PMIC_STATUS mc13892_bklit_get_blink_p(enum lit_channel channel, int *period); + +#endif + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_PMIC_LIGHT_H__ */ diff --git a/include/linux/pmic_rtc.h b/include/linux/pmic_rtc.h new file mode 100644 index 000000000000..ff15676e43d8 --- /dev/null +++ b/include/linux/pmic_rtc.h @@ -0,0 +1,153 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ + +#ifndef __ASM_ARCH_MXC_PMIC_RTC_H__ +#define __ASM_ARCH_MXC_PMIC_RTC_H__ + +/*! + * @defgroup PMIC_RTC PMIC RTC Driver + * @ingroup PMIC_DRVRS + */ + +/*! + * @file arch-mxc/pmic_rtc.h + * @brief This is the header of PMIC RTC driver. + * + * @ingroup PMIC_RTC + */ + +/* + * Includes + */ +#include +#include +#include + +#define PMIC_RTC_SET_TIME _IOWR('p', 0xd1, int) +#define PMIC_RTC_GET_TIME _IOWR('p', 0xd2, int) +#define PMIC_RTC_SET_ALARM _IOWR('p', 0xd3, int) +#define PMIC_RTC_GET_ALARM _IOWR('p', 0xd4, int) +#define PMIC_RTC_WAIT_ALARM _IOWR('p', 0xd5, int) +#define PMIC_RTC_ALARM_REGISTER _IOWR('p', 0xd6, int) +#define PMIC_RTC_ALARM_UNREGISTER _IOWR('p', 0xd7, int) + +/*! + * This enumeration define all RTC interrupt + */ +typedef enum { + /*! + * Time of day alarm + */ + RTC_IT_ALARM, + /*! + * 1 Hz timetick + */ + RTC_IT_1HZ, + /*! + * RTC reset occurred + */ + RTC_IT_RST, +} t_rtc_int; + +/* + * RTC PMIC API + */ + +/* EXPORTED FUNCTIONS */ +#ifdef __KERNEL__ + +/*! + * This function set the real time clock of PMIC + * + * @param pmic_time value of date and time + * + * @return This function returns PMIC_STATUS if successful. + */ +PMIC_STATUS pmic_rtc_set_time(struct timeval *pmic_time); + +/*! + * This function get the real time clock of PMIC + * + * @param pmic_time return value of date and time + * + * @return This function returns PMIC_STATUS if successful. + */ +PMIC_STATUS pmic_rtc_get_time(struct timeval *pmic_time); + +/*! + * This function set the real time clock alarm of PMIC + * + * @param pmic_time value of date and time + * + * @return This function returns PMIC_STATUS if successful. + */ +PMIC_STATUS pmic_rtc_set_time_alarm(struct timeval *pmic_time); + +/*! + * This function get the real time clock alarm of PMIC + * + * @param pmic_time return value of date and time + * + * @return This function returns PMIC_STATUS if successful. + */ +PMIC_STATUS pmic_rtc_get_time_alarm(struct timeval *pmic_time); + +/*! + * This function wait the Alarm event + * + * @return This function returns PMIC_STATUS if successful. + */ +PMIC_STATUS pmic_rtc_wait_alarm(void); + +/*! + * This function is used to un/subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * @param sub define if Un/subscribe event. + * + * @return This function returns PMIC_STATUS if successful. + */ +PMIC_STATUS pmic_rtc_event(t_rtc_int event, void *callback, bool sub); + +/*! + * This function is used to subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns PMIC_STATUS if successful. + */ +PMIC_STATUS pmic_rtc_event_sub(t_rtc_int event, void *callback); + +/*! + * This function is used to un-subscribe on RTC event IT. + * + * @param event type of event. + * @param callback event callback function. + * + * @return This function returns PMIC_STATUS if successful. + */ +PMIC_STATUS pmic_rtc_event_unsub(t_rtc_int event, void *callback); + +/*! + * This function is used to tell if PMIC RTC has been correctly loaded. + * + * @return This function returns 1 if RTC was successfully loaded + * 0 otherwise. + */ +int pmic_rtc_loaded(void); + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_PMIC_RTC_H__ */ diff --git a/include/linux/pmic_status.h b/include/linux/pmic_status.h new file mode 100644 index 000000000000..08a2acbc7c94 --- /dev/null +++ b/include/linux/pmic_status.h @@ -0,0 +1,82 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __ASM_ARCH_MXC_PMIC_STATUS_H__ +#define __ASM_ARCH_MXC_PMIC_STATUS_H__ +#include +#ifdef __KERNEL__ +#include /* copy_{from,to}_user() */ +#endif +/*! + * @file arch-mxc/pmic_status.h + * @brief PMIC APIs return code definition. + * + * @ingroup PMIC_CORE + */ + +/*! + * @enum PMIC_STATUS + * @brief Define return values for all PMIC APIs. + * + * These return values are used by all of the PMIC APIs. + * + * @ingroup PMIC + */ +typedef enum { + PMIC_SUCCESS = 0, /*!< The requested operation was successfully + completed. */ + PMIC_ERROR = -1, /*!< The requested operation could not be completed + due to an error. */ + PMIC_PARAMETER_ERROR = -2, /*!< The requested operation failed because + one or more of the parameters was + invalid. */ + PMIC_NOT_SUPPORTED = -3, /*!< The requested operation could not be + completed because the PMIC hardware + does not support it. */ + PMIC_SYSTEM_ERROR_EINTR = -EINTR, + + PMIC_MALLOC_ERROR = -5, /*!< Error in malloc function */ + PMIC_UNSUBSCRIBE_ERROR = -6, /*!< Error in un-subscribe event */ + PMIC_EVENT_NOT_SUBSCRIBED = -7, /*!< Event occur and not subscribed */ + PMIC_EVENT_CALL_BACK = -8, /*!< Error - bad call back */ + PMIC_CLIENT_NBOVERFLOW = -9, /*!< The requested operation could not be + completed because there are too many + PMIC client requests */ +} PMIC_STATUS; + +/* + * Bitfield macros that use rely on bitfield width/shift information. + */ +#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH)) +#define BITFVAL(field, val) ((val) << (field ## _LSH)) +#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH)) + +/* + * Macros implementing error handling + */ +#define CHECK_ERROR(a) \ +do { \ + int ret = (a); \ + if (ret != PMIC_SUCCESS) \ + return ret; \ +} while (0) + +#define CHECK_ERROR_KFREE(func, freeptrs) \ +do { \ + int ret = (func); \ + if (ret != PMIC_SUCCESS) { \ + freeptrs; \ + return ret; \ + } \ +} while (0); + +#endif /* __ASM_ARCH_MXC_PMIC_STATUS_H__ */ diff --git a/include/linux/powerkey.h b/include/linux/powerkey.h new file mode 100644 index 000000000000..f947a51e9595 --- /dev/null +++ b/include/linux/powerkey.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef POWER_KEY_H +#define POWER_KEY_H + +typedef void (*pwrkey_callback)(void *); + +struct power_key_platform_data { + int key_value; + void (*register_pwrkey) (pwrkey_callback); + int (*get_key_status) (int); +}; + +#endif /* POWER_KEY_H */ diff --git a/include/linux/pxp_dma.h b/include/linux/pxp_dma.h new file mode 100644 index 000000000000..91553970f22a --- /dev/null +++ b/include/linux/pxp_dma.h @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef _PXP_DMA +#define _PXP_DMA + +#include + +#ifndef __KERNEL__ +typedef unsigned long dma_addr_t; +typedef unsigned char bool; +#endif + +/* PXP Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/*! + * @name PXP Pixel Formats + * + * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are + * the same used by V4L2 API. + */ + +/*! @} */ +/*! @name RGB Formats */ +/*! @{ */ +#define PXP_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */ +#define PXP_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */ +#define PXP_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */ +#define PXP_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */ +#define PXP_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */ +#define PXP_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */ +#define PXP_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */ +#define PXP_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */ +#define PXP_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */ +#define PXP_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */ +#define PXP_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */ +#define PXP_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */ +/*! @} */ +/*! @name YUV Interleaved Formats */ +/*! @{ */ +#define PXP_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */ +#define PXP_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */ +#define PXP_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */ +#define PXP_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */ +/* two planes -- one Y, one Cb + Cr interleaved */ +#define PXP_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +/*! @} */ +/*! @name YUV Planar Formats */ +/*! @{ */ +#define PXP_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */ +#define PXP_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */ +#define PXP_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */ +#define PXP_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */ +#define PXP_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */ +#define PXP_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */ +#define PXP_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */ +#define PXP_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */ +/*! @} */ + +#define PXP_LUT_NONE 0x0 +#define PXP_LUT_INVERT 0x1 +#define PXP_LUT_BLACK_WHITE 0x2 + +#define NR_PXP_VIRT_CHANNEL 16 + +#define PXP_IOC_MAGIC 'P' + +#define PXP_IOC_GET_CHAN _IOR(PXP_IOC_MAGIC, 0, struct pxp_mem_desc) +#define PXP_IOC_PUT_CHAN _IOW(PXP_IOC_MAGIC, 1, struct pxp_mem_desc) +#define PXP_IOC_CONFIG_CHAN _IOW(PXP_IOC_MAGIC, 2, struct pxp_mem_desc) +#define PXP_IOC_START_CHAN _IOW(PXP_IOC_MAGIC, 3, struct pxp_mem_desc) +#define PXP_IOC_GET_PHYMEM _IOWR(PXP_IOC_MAGIC, 4, struct pxp_mem_desc) +#define PXP_IOC_PUT_PHYMEM _IOW(PXP_IOC_MAGIC, 5, struct pxp_mem_desc) +#define PXP_IOC_WAIT4CMPLT _IOWR(PXP_IOC_MAGIC, 6, struct pxp_mem_desc) + +/* Order significant! */ +enum pxp_channel_status { + PXP_CHANNEL_FREE, + PXP_CHANNEL_INITIALIZED, + PXP_CHANNEL_READY, +}; + +struct rect { + int top; /* Upper left coordinate of rectangle */ + int left; + int width; + int height; +}; + +struct pxp_layer_param { + unsigned short width; + unsigned short height; + unsigned int pixel_fmt; + + /* layers combining parameters + * (these are ignored for S0 and output + * layers, and only apply for OL layer) + */ + bool combine_enable; + __u32 color_key_enable; + __u32 color_key; + bool global_alpha_enable; + __u8 global_alpha; + bool local_alpha_enable; + + dma_addr_t paddr; +}; + +struct pxp_proc_data { + /* S0 Transformation Info */ + int scaling; + int hflip; + int vflip; + int rotate; + int yuv; + + /* Source rectangle (srect) defines the sub-rectangle + * within S0 to undergo processing. + */ + struct rect srect; + /* Dest rect (drect) defines how to position the processed + * source rectangle (after resizing) within the output frame, + * whose dimensions are defined in pxp->pxp_conf_state.out_param + */ + struct rect drect; + + /* Current S0 configuration */ + __u32 bgcolor; + + /* Output overlay support */ + int overlay_state; + + /* LUT transformation on Y data */ + int lut_transform; +}; + +struct pxp_config_data { + struct pxp_layer_param s0_param; + struct pxp_layer_param ol_param[8]; + struct pxp_layer_param out_param; + struct pxp_proc_data proc_data; + int layer_nr; + + /* Users don't touch */ + int chan_id; +}; + +struct pxp_mem_desc { + __u32 size; + dma_addr_t phys_addr; + __u32 cpu_addr; /* cpu address to free the dma mem */ + __u32 virt_uaddr; /* virtual user space address */ +}; + +#ifdef __KERNEL__ + +struct pxp_tx_desc { + struct dma_async_tx_descriptor txd; + struct list_head tx_list; + struct list_head list; + int len; + union { + struct pxp_layer_param s0_param; + struct pxp_layer_param out_param; + struct pxp_layer_param ol_param; + } layer_param; + struct pxp_proc_data proc_data; + + u32 hist_status; /* Histogram output status */ + + struct pxp_tx_desc *next; +}; + +struct pxp_channel { + struct dma_chan dma_chan; + dma_cookie_t completed; /* last completed cookie */ + enum pxp_channel_status status; + void *client; /* Only one client per channel */ + unsigned int n_tx_desc; + struct pxp_tx_desc *desc; /* allocated tx-descriptors */ + struct list_head active_list; /* active tx-descriptors */ + struct list_head free_list; /* free tx-descriptors */ + struct list_head queue; /* queued tx-descriptors */ + struct list_head list; /* track queued channel number */ + spinlock_t lock; /* protects sg[0,1], queue */ + struct mutex chan_mutex; /* protects status, cookie, free_list */ + int active_buffer; + unsigned int eof_irq; + char eof_name[16]; /* EOF IRQ name for request_irq() */ +}; + +struct pxp_irq_info { + wait_queue_head_t waitq; + int irq_pending; + int hist_status; +}; + +#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd) +#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan) + +void pxp_txd_ack(struct dma_async_tx_descriptor *txd, + struct pxp_channel *pxp_chan); +#endif + +#endif diff --git a/include/linux/regulator/da9052-regulator.h b/include/linux/regulator/da9052-regulator.h new file mode 100644 index 000000000000..58e6f0bafef6 --- /dev/null +++ b/include/linux/regulator/da9052-regulator.h @@ -0,0 +1,15 @@ +/* This file is there to support additional attributes in + sysfs - changestate and setvoltage +*/ +#ifndef _DA9052_REGULATOR_H +#define _DA9052_REGULATOR_H + +int da9052_ldo_buck_enable(struct regulator_dev *rdev); +int da9052_ldo_buck_disable(struct regulator_dev *rdev); + + +int da9052_ldo_buck_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV); +int da9052_ldo_buck_get_voltage(struct regulator_dev *rdev); + +#endif diff --git a/include/linux/regulator/ltc3589.h b/include/linux/regulator/ltc3589.h new file mode 100644 index 000000000000..abacb9f2c1b0 --- /dev/null +++ b/include/linux/regulator/ltc3589.h @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __LINUX_LTC3589_PMIC_H +#define __LINUX_LTC3589_PMIC_H + +#include +#include +#include + +/* + * Register values. + */ +#define LTC3589_REG_IRSTAT 0x02 +#define LTC3589_REG_SCR1 0x07 +#define LTC3589_REG_OVEN 0x10 +#define LTC3589_REG_SCR2 0x12 +#define LTC3589_REG_PGSTAT 0x13 +#define LTC3589_REG_VCCR 0x20 +#define LTC3589_REG_CLIRQ 0x21 +#define LTC3589_REG_B1DTV1 0x23 +#define LTC3589_REG_B1DTV2 0x24 +#define LTC3589_REG_VRRCR 0x25 +#define LTC3589_REG_B2DTV1 0x26 +#define LTC3589_REG_B2DTV2 0x27 +#define LTC3589_REG_B3DTV1 0x29 +#define LTC3589_REG_B3DTV2 0x2A +#define LTC3589_REG_L2DTV1 0x32 +#define LTC3589_REG_L2DTV2 0x33 + +/* + * IRQSTAT (0x02) - Event register + */ +#define LTC3589_IRQSTAT_TIMEOUT_SHUTDOWN 0x08 +#define LTC3589_IRQSTAT_NRAE_UNDERVOLTAGE 0x10 +#define LTC3589_IRQSTAT_UNDERVOLTAGE_SHUTDOWN 0x20 +#define LTC3589_IRQSTAT_NRAE_THERMAL 0x40 +#define LTC3589_IRQSTAT_THERMAL_SHUTDOWN 0x80 + +/* + * SCR1 (0x07) - System control register 1 + */ +#define LTC3589_SCR1_SWITCH_REG1_MODE_SHIFT 0 +#define LTC3589_SCR1_SWITCH_REG2_MODE_SHIFT 2 +#define LTC3589_SCR1_SWITCH_REG3_MODE_SHIFT 4 +#define LTC3589_SCR1_SWITCH_REG_MODE_MASK 0x3 +#define LTC3589_SCR1_BUCK_BOOST_MODE 0x40 + +/* Bit values for SCR1 (0x07) */ +#define LTC3589_SCR1_REG_MODE_PULSE_SKIPPING 0 +#define LTC3589_SCR1_REG_MODE_BURST 1 +#define LTC3589_SCR1_REG_MODE_FORCED_CONTINUOUS 2 +#define LTC3589_SCR1_BUCK_BOOST_MODE_CONTINUOUS 0 +#define LTC3589_SCR1_BUCK_BOOST_MODE_BURST_MODE 1 + +/* + * OVEN (0x10) - Output voltage enable register + */ +#define LTC3589_OVEN_EN1 0x01 +#define LTC3589_OVEN_EN2 0x02 +#define LTC3589_OVEN_EN3 0x04 +#define LTC3589_OVEN_EN4 0x08 +#define LTC3589_OVEN_EN_LDO2 0x10 +#define LTC3589_OVEN_EN_LDO3 0x20 +#define LTC3589_OVEN_EN_LDO4 0x40 +#define LTC3589_OVEN_PWR_ON 0x80 + +/* + * SCR2 (0x12) - System control register 2 + */ +#define LTC3589_SCR2_REG1_STARTUP_SHIFT 0 +#define LTC3589_SCR2_REG2_STARTUP_SHIFT 1 +#define LTC3589_SCR2_REG3_STARTUP_SHIFT 2 +#define LTC3589_SCR2_BUCK_BOOST_STARTUP_SHIFT 3 +#define LTC3589_SCR2_LDO2_STARTUP_SHIFT 4 +#define LTC3589_SCR2_LDO3_STARTUP_SHIFT 5 +#define LTC3589_SCR2_LDO4_STARTUP_SHIFT 6 +#define LTC3589_SCR2_PGOOD_SHUTDOWN_SHIFT 7 + +/* Bit values for SCR2 (0x12) */ +#define LTC3589_SCR2_WAIT_FOR_OUTPUT 0 +#define LTC3589_SCR2_DO_NOT_WAIT 1 +#define LTC3589_SCR2_ALLOW_PGOOD_TIMEOUT_SHUTDOWN 0 +#define LTC3589_SCR2_INHIBIT_PGOOD_HARD_SHUTDOWN 1 + +/* + * PGSTAT (0x13) - Power good status register + */ +#define LTC3589_PGSTAT_LDO1_STATUS 0x01 +#define LTC3589_PGSTAT_SWITCH_REG1_STATUS 0x02 +#define LTC3589_PGSTAT_SWITCH_REG2_STATUS 0x04 +#define LTC3589_PGSTAT_SWITCH_REG3_STATUS 0x08 +#define LTC3589_PGSTAT_BUCK_BOOST_STATUS 0x10 +#define LTC3589_PGSTAT_LDO2_STATUS 0x20 +#define LTC3589_PGSTAT_LDO3_STATUS 0x40 +#define LTC3589_PGSTAT_LDO4_STATUS 0x80 + +/* Bit values for PGSTAT (0x13) */ +#define LTC3589_PGSTAT_V_OUT_LOW 0 +#define LTC3589_PGSTAT_V_OUT_GOOD 1 + +/* + * VCCR (0x20) - Voltage change control register + */ +#define LTC3589_VCCR_START_REG1_SLEW 0x01 +#define LTC3589_VCCR_REG1_REF_SELECT 0x02 +#define LTC3589_VCCR_START_REG2_SLEW 0x04 +#define LTC3589_VCCR_REG2_REF_SELECT 0x08 +#define LTC3589_VCCR_START_REG3_SLEW 0x10 +#define LTC3589_VCCR_REG3_REF_SELECT 0x20 +#define LTC3589_VCCR_LDO2_SLEW 0x40 +#define LTC3589_VCCR_LDO2_REF_SELECT 0x80 + +/* Bit values for VCCR (0x20) */ +#define LTC3589_VCCR_WENT 0 +#define LTC3589_VCCR_GO 1 +#define LTC3589_VCCR_REF_SELECT_DTV1 0 +#define LTC3589_VCCR_REF_SELECT_DTV2 1 + +/* + * B1DTV1 (0x23) - REG1 DAC Dynamic Target Voltage V1 register + */ +#define LTC3589_B1DTV1_REG1_REF_INPUT_V1_MASK 0x1F +#define LTC3589_B1DTV1_REG1_REF_INPUT_V1_SHIFT 0 +#define LTC3589_B1DTV1_PGOOD_MASK 0x20 +#define LTC3589_B1DTV1_SWITCH_DV_DT_CTRL_MASK 0x03 +#define LTC3589_B1DTV1_SWITCH_DV_DT_CTRL_SHIFT 6 + +/* Bit values for B1DTV1 (0x23) */ +#define LTC3589_B1DTV1_PGOOD_LOW 0 +#define LTC3589_B1DTV1_PGOOD_NOT_FORCED_LOW 1 +#define LTC3589_B1DTV1_DV_DT_CTRL_WW_NS 0 +#define LTC3589_B1DTV1_DV_DT_CTRL_XX_NS 1 +#define LTC3589_B1DTV1_DV_DT_CTRL_YY_NS 2 +#define LTC3589_B1DTV1_DV_DT_CTRL_ZZ_NS 3 + +/* + * B1DTV2 (0x24) - REG1 DAC Dynamic Target Voltage V2 register + */ +#define LTC3589_B1DTV2_REG1_REF_INPUT_V2_MASK 0x1F +#define LTC3589_B1DTV2_REG1_REF_INPUT_V2_SHIFT 0 + +/* + * VRRCR (0x25) - Voltage ramp rate command register + */ +#define LTC3589_VRRCR_REG1_REF_SLEW_RATE_MASK 0x3 +#define LTC3589_VRRCR_REG1_REF_SLEW_RATE_SHIFT 0 +#define LTC3589_VRRCR_REG2_REF_SLEW_RATE_MASK 0x3 +#define LTC3589_VRRCR_REG2_REF_SLEW_RATE_SHIFT 2 +#define LTC3589_VRRCR_REG3_REF_SLEW_RATE_MASK 0x3 +#define LTC3589_VRRCR_REG3_REF_SLEW_RATE_SHIFT 4 +#define LTC3589_VRRCR_LDO2_REF_SLEW_RATE_MASK 0x3 +#define LTC3589_VRRCR_LDO2_REF_SLEW_RATE_SHIFT 6 + +/* Bit values for VRRCR (0x25) */ +#define LTC3589_VRRCR_SLEW_RATE_0P88MV_US 0 +#define LTC3589_VRRCR_SLEW_RATE_1P75MV_US 1 +#define LTC3589_VRRCR_SLEW_RATE_3P50MV_US 2 +#define LTC3589_VRRCR_SLEW_RATE_7P00MV_US 3 + +/* + * B2DTV1 (0x26) - REG2 DAC Dynamic Target Voltage V1 register + */ +#define LTC3589_B2DTV1_REG2_REF_INPUT_V1_MASK 0x1F +#define LTC3589_B2DTV1_REG2_REF_INPUT_V1_SHIFT 0 +#define LTC3589_B2DTV1_PGOOD_MASK 0x20 + +/* + * B2DTV2 (0x27) - REG2 DAC Dynamic Target Voltage V2 register + */ +#define LTC3589_B2DTV2_REG2_REF_INPUT_V2_MASK 0x1F +#define LTC3589_B2DTV2_REG2_REF_INPUT_V2_SHIFT 0 + +/* + * B3DTV1 (0x29) - REG3 DAC Dynamic Target Voltage V1 register + */ +#define LTC3589_B3DTV1_REG3_REF_INPUT_V1_MASK 0x1F +#define LTC3589_B3DTV1_REG3_REF_INPUT_V1_SHIFT 0 +#define LTC3589_B3DTV1_PGOOD_MASK 0x20 + +/* + * B3DTV2 (0x2A) - REG3 DAC Dynamic Target Voltage V2 register + */ +#define LTC3589_B3DTV2_REG3_REF_INPUT_V2_MASK 0x1F +#define LTC3589_B3DTV2_REG3_REF_INPUT_V2_SHIFT 0 + +/* + * L2DTV1 (0x32) - LDO2 DAC Dynamic Target Voltage V1 register + */ +#define LTC3589_L2DTV1_LDO2_REF_INPUT_V1_MASK 0x1F +#define LTC3589_L2DTV1_LDO2_REF_INPUT_V1_SHIFT 0 +#define LTC3589_L2DTV1_PGOOD_MASK 0x20 + +/* + * L2DTV2 (0x33) - LDO2 DAC Dynamic Target Voltage V2 register + */ +#define LTC3589_L2DTV2_LDO2_REF_INPUT_V2_MASK 0x1F +#define LTC3589_L2DTV2_LDO2_REF_INPUT_V2_SHIFT 0 +#define LTC3589_L2DTV2_LDO4_OUTPUT_VOLTAGE_MASK 0x3 +#define LTC3589_L2DTV2_LDO4_OUTPUT_VOLTAGE_SHIFT 5 +#define LTC3589_L2DTV2_LDO4_CONTROL_MODE_SHIFT 7 + +/* Bit values for L2DTV2 (0x33) */ +#define LTC3589_L2DTV2_LDO4_OUTPUT_VOL_1P8V 0 +#define LTC3589_L2DTV2_LDO4_OUTPUT_VOL_2P5V 1 +#define LTC3589_L2DTV2_LDO4_OUTPUT_VOL_3P0V 2 +#define LTC3589_L2DTV2_LDO4_OUTPUT_VOL_3P3V 3 + +#endif diff --git a/include/linux/sched.h b/include/linux/sched.h index 5ee397ee3bca..794b8f447d03 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1682,6 +1682,9 @@ static inline void put_task_struct(struct task_struct *t) extern void task_times(struct task_struct *p, cputime_t *ut, cputime_t *st); extern void thread_group_times(struct task_struct *p, cputime_t *ut, cputime_t *st); +extern int task_free_register(struct notifier_block *n); +extern int task_free_unregister(struct notifier_block *n); + /* * Per process flags */ diff --git a/include/linux/sockios.h b/include/linux/sockios.h index 241f179347d9..f4fa1a164c74 100644 --- a/include/linux/sockios.h +++ b/include/linux/sockios.h @@ -65,6 +65,7 @@ #define SIOCDIFADDR 0x8936 /* delete PA address */ #define SIOCSIFHWBROADCAST 0x8937 /* set hardware broadcast addr */ #define SIOCGIFCOUNT 0x8938 /* get number of devices */ +#define SIOCKILLADDR 0x8939 /* kill sockets with this local addr */ #define SIOCGIFBR 0x8940 /* Bridging support */ #define SIOCSIFBR 0x8941 /* Set bridging options */ diff --git a/include/linux/soundcard.h b/include/linux/soundcard.h index 1904afedb82f..91b9b7928ab4 100644 --- a/include/linux/soundcard.h +++ b/include/linux/soundcard.h @@ -873,12 +873,16 @@ typedef struct copr_msg { #define SOUND_MIXER_READ_LINE1 MIXER_READ(SOUND_MIXER_LINE1) #define SOUND_MIXER_READ_LINE2 MIXER_READ(SOUND_MIXER_LINE2) #define SOUND_MIXER_READ_LINE3 MIXER_READ(SOUND_MIXER_LINE3) +#define SOUND_MIXER_READ_PHONEIN MIXER_READ(SOUND_MIXER_PHONEIN) +#define SOUND_MIXER_READ_PHONEOUT MIXER_READ(SOUND_MIXER_PHONEOUT) /* Obsolete macros */ #define SOUND_MIXER_READ_MUTE MIXER_READ(SOUND_MIXER_MUTE) #define SOUND_MIXER_READ_ENHANCE MIXER_READ(SOUND_MIXER_ENHANCE) #define SOUND_MIXER_READ_LOUD MIXER_READ(SOUND_MIXER_LOUD) +#define SOUND_MIXER_READ_OUTSRC MIXER_READ(SOUND_MIXER_OUTSRC) +#define SOUND_MIXER_READ_OUTMASK MIXER_READ(SOUND_MIXER_OUTMASK) #define SOUND_MIXER_READ_RECSRC MIXER_READ(SOUND_MIXER_RECSRC) #define SOUND_MIXER_READ_DEVMASK MIXER_READ(SOUND_MIXER_DEVMASK) #define SOUND_MIXER_READ_RECMASK MIXER_READ(SOUND_MIXER_RECMASK) @@ -903,6 +907,8 @@ typedef struct copr_msg { #define SOUND_MIXER_WRITE_LINE1 MIXER_WRITE(SOUND_MIXER_LINE1) #define SOUND_MIXER_WRITE_LINE2 MIXER_WRITE(SOUND_MIXER_LINE2) #define SOUND_MIXER_WRITE_LINE3 MIXER_WRITE(SOUND_MIXER_LINE3) +#define SOUND_MIXER_WRITE_PHONEIN MIXER_WRITE(SOUND_MIXER_PHONEIN) +#define SOUND_MIXER_WRITE_PHONEOUT MIXER_WRITE(SOUND_MIXER_PHONEOUT) /* Obsolete macros */ #define SOUND_MIXER_WRITE_MUTE MIXER_WRITE(SOUND_MIXER_MUTE) @@ -910,6 +916,7 @@ typedef struct copr_msg { #define SOUND_MIXER_WRITE_LOUD MIXER_WRITE(SOUND_MIXER_LOUD) #define SOUND_MIXER_WRITE_RECSRC MIXER_WRITE(SOUND_MIXER_RECSRC) +#define SOUND_MIXER_WRITE_OUTSRC MIXER_WRITE(SOUND_MIXER_OUTSRC) typedef struct mixer_info { diff --git a/include/linux/uid_stat.h b/include/linux/uid_stat.h new file mode 100644 index 000000000000..6bd6c4e52d17 --- /dev/null +++ b/include/linux/uid_stat.h @@ -0,0 +1,29 @@ +/* include/linux/uid_stat.h + * + * Copyright (C) 2008-2009 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __uid_stat_h +#define __uid_stat_h + +/* Contains definitions for resource tracking per uid. */ + +#ifdef CONFIG_UID_STAT +int uid_stat_tcp_snd(uid_t uid, int size); +int uid_stat_tcp_rcv(uid_t uid, int size); +#else +#define uid_stat_tcp_snd(uid, size) do {} while (0); +#define uid_stat_tcp_rcv(uid, size) do {} while (0); +#endif + +#endif /* _LINUX_UID_STAT_H */ diff --git a/include/linux/usb/fsl_xcvr.h b/include/linux/usb/fsl_xcvr.h new file mode 100644 index 000000000000..96e5526127db --- /dev/null +++ b/include/linux/usb/fsl_xcvr.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU Lesser General + * Public License. You may obtain a copy of the GNU Lesser General + * Public License Version 2.1 or later at the following locations: + * + * http://www.opensource.org/licenses/lgpl-license.html + * http://www.gnu.org/copyleft/lgpl.html + */ +#ifndef __LINUX_USB_FSL_XCVR_H +#define __LINUX_USB_FSL_XCVR_H +#include +#include + +struct fsl_usb2_platform_data; + +enum usb_test_mode{ + USB_TEST_J = 1, + USB_TEST_K = 2, +}; + +/** + * @name: transceiver name + * @xcvr_type: one of PORTSC_PTS_{UTMI,SERIAL,ULPI} + * @init: transceiver- and board-specific initialization function + * @uninit: transceiver- and board-specific uninitialization function + * @set_host: + * @set_device: + * @pullup: enable or disable D+ pullup + * + */ +struct fsl_xcvr_ops { + char *name; + u32 xcvr_type; + + void (*init)(struct fsl_xcvr_ops *ops); + void (*uninit)(struct fsl_xcvr_ops *ops); + void (*suspend)(struct fsl_xcvr_ops *ops); + void (*set_host)(void); + void (*set_device)(void); + void (*set_vbus_power)(struct fsl_xcvr_ops *ops, + struct fsl_usb2_platform_data *pdata, int on); + void (*set_vbus_draw)(struct fsl_xcvr_ops *ops, + struct fsl_usb2_platform_data *pdata, unsigned mA); + void (*set_remote_wakeup)(u32 *view); + void (*pullup)(int on); + void(*set_test_mode)(u32 *view, enum usb_test_mode mode); +}; + +struct fsl_xcvr_power { + struct platform_device *usb_pdev; + struct regulator *regu1; + struct regulator *regu2; +}; +#endif diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index be51ae2bd0ff..1fc324aaa182 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -42,12 +42,13 @@ struct mtd_oob_buf64 { #define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */ #define MTD_NO_ERASE 0x1000 /* No erase necessary */ #define MTD_POWERUP_LOCK 0x2000 /* Always locked after reset */ +#define MTD_OOB_WRITEABLE 0x4000 /* Use Out-Of-Band area */ // Some common devices / combinations of capabilities #define MTD_CAP_ROM 0 #define MTD_CAP_RAM (MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE) #define MTD_CAP_NORFLASH (MTD_WRITEABLE | MTD_BIT_WRITEABLE) -#define MTD_CAP_NANDFLASH (MTD_WRITEABLE) +#define MTD_CAP_NANDFLASH (MTD_WRITEABLE | MTD_OOB_WRITEABLE) /* ECC byte placement */ #define MTD_NANDECC_OFF 0 // Switch off ECC (Not recommended) diff --git a/include/net/tcp.h b/include/net/tcp.h index a1449144848a..250698be4d99 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -1433,6 +1433,8 @@ extern struct sk_buff **tcp4_gro_receive(struct sk_buff **head, extern int tcp_gro_complete(struct sk_buff *skb); extern int tcp4_gro_complete(struct sk_buff *skb); +extern void tcp_v4_nuke_addr(__u32 saddr); + #ifdef CONFIG_PROC_FS extern int tcp4_proc_init(void); extern void tcp4_proc_exit(void); diff --git a/init/Kconfig b/init/Kconfig index 5cff9a980c39..c8e8d2f74011 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -958,6 +958,15 @@ config SHMEM option replaces shmem and tmpfs with the much simpler ramfs code, which may be appropriate on small systems without swap. +config ASHMEM + bool "Enable the Anonymous Shared Memory Subsystem" + default n + depends on SHMEM || TINY_SHMEM + help + The ashmem subsystem is a new shared memory allocator, similar to + POSIX SHM but with different behavior and sporting a simpler + file-based API. + config AIO bool "Enable AIO support" if EMBEDDED default y diff --git a/kernel/fork.c b/kernel/fork.c index b6cce14ba047..19615bcae7fe 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -147,6 +147,9 @@ struct kmem_cache *vm_area_cachep; /* SLAB cache for mm_struct structures (tsk->mm) */ static struct kmem_cache *mm_cachep; +/* Notifier list called when a task struct is freed */ +static ATOMIC_NOTIFIER_HEAD(task_free_notifier); + static void account_kernel_stack(struct thread_info *ti, int account) { struct zone *zone = page_zone(virt_to_page(ti)); @@ -177,6 +180,20 @@ static inline void put_signal_struct(struct signal_struct *sig) free_signal_struct(sig); } +int task_free_register(struct notifier_block *n) +{ + return atomic_notifier_chain_register(&task_free_notifier, n); +} + +EXPORT_SYMBOL(task_free_register); + +int task_free_unregister(struct notifier_block *n) +{ + return atomic_notifier_chain_unregister(&task_free_notifier, n); +} + +EXPORT_SYMBOL(task_free_unregister); + void __put_task_struct(struct task_struct *tsk) { WARN_ON(!tsk->exit_state); @@ -187,6 +204,7 @@ void __put_task_struct(struct task_struct *tsk) delayacct_tsk_free(tsk); put_signal_struct(tsk->signal); + atomic_notifier_call_chain(&task_free_notifier, 0, tsk); if (!profile_handoff_task(tsk)) free_task(tsk); } diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig index ca6066a6952e..631de1141247 100644 --- a/kernel/power/Kconfig +++ b/kernel/power/Kconfig @@ -123,6 +123,20 @@ config PM_TEST_SUSPEND You probably want to have your system's RTC driver statically linked, ensuring that it's available when this test runs. +config SUSPEND_DEVICE_TIME_DEBUG + bool "Warnning device suspend/resume takes too much time" + depends on SUSPEND && PM_DEBUG + default n + ---help--- + This option will enable a timing function to check device + suspend time consumption, If the device takes more time that + the threshold(default 0.5 ms), it will print the device and + bus name on the console. You can change the threshold + on-the-fly by modify /sys/power/time_threshold the time unit + is in microsecond. + + This options only for debug proprose, If in doubt, say N. + config SUSPEND_FREEZER bool "Enable freezer for suspend to RAM/standby" \ if ARCH_WANTS_FREEZER_CONTROL || BROKEN diff --git a/kernel/power/main.c b/kernel/power/main.c index b58800b21fc0..bfb684a4d412 100644 --- a/kernel/power/main.c +++ b/kernel/power/main.c @@ -229,11 +229,47 @@ pm_trace_store(struct kobject *kobj, struct kobj_attribute *attr, power_attr(pm_trace); #endif /* CONFIG_PM_TRACE */ +#ifdef CONFIG_SUSPEND_DEVICE_TIME_DEBUG +/* + * threshold of device suspend time consumption in microsecond(0.5ms), the + * driver suspend/resume time longer than this threshold will be + * print to console, 0 to disable */ +int device_suspend_time_threshold; + +static ssize_t +device_suspend_time_threshold_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + if (device_suspend_time_threshold == 0) + return sprintf(buf, "off\n"); + else + return sprintf(buf, "%d usecs\n", + device_suspend_time_threshold); +} + +static ssize_t +device_suspend_time_threshold_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t n) +{ + int val; + if (sscanf(buf, "%d", &val) > 0) { + device_suspend_time_threshold = val; + return n; + } + return -EINVAL; +} +power_attr(device_suspend_time_threshold); +#endif + static struct attribute * g[] = { &state_attr.attr, #ifdef CONFIG_PM_TRACE &pm_trace_attr.attr, #endif +#ifdef CONFIG_SUSPEND_DEVICE_TIME_DEBUG + &device_suspend_time_threshold_attr.attr, +#endif #ifdef CONFIG_PM_SLEEP &pm_async_attr.attr, #ifdef CONFIG_PM_DEBUG diff --git a/localversion b/localversion new file mode 100644 index 000000000000..63bbb6fb50e9 --- /dev/null +++ b/localversion @@ -0,0 +1 @@ +-744-g27fdf7b diff --git a/mm/Makefile b/mm/Makefile index 34b2546a9e37..a62e107d7e50 100644 --- a/mm/Makefile +++ b/mm/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_HUGETLBFS) += hugetlb.o obj-$(CONFIG_NUMA) += mempolicy.o obj-$(CONFIG_SPARSEMEM) += sparse.o obj-$(CONFIG_SPARSEMEM_VMEMMAP) += sparse-vmemmap.o +obj-$(CONFIG_ASHMEM) += ashmem.o obj-$(CONFIG_SLOB) += slob.o obj-$(CONFIG_COMPACTION) += compaction.o obj-$(CONFIG_MMU_NOTIFIER) += mmu_notifier.o diff --git a/mm/ashmem.c b/mm/ashmem.c new file mode 100644 index 000000000000..6001efb8e177 --- /dev/null +++ b/mm/ashmem.c @@ -0,0 +1,745 @@ +/* mm/ashmem.c +** +** Anonymous Shared Memory Subsystem, ashmem +** +** Copyright (C) 2008 Google, Inc. +** +** Robert Love +** +** This software is licensed under the terms of the GNU General Public +** License version 2, as published by the Free Software Foundation, and +** may be copied, distributed, and modified under those terms. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ASHMEM_NAME_PREFIX "dev/ashmem/" +#define ASHMEM_NAME_PREFIX_LEN (sizeof(ASHMEM_NAME_PREFIX) - 1) +#define ASHMEM_FULL_NAME_LEN (ASHMEM_NAME_LEN + ASHMEM_NAME_PREFIX_LEN) + +/* + * ashmem_area - anonymous shared memory area + * Lifecycle: From our parent file's open() until its release() + * Locking: Protected by `ashmem_mutex' + * Big Note: Mappings do NOT pin this structure; it dies on close() + */ +struct ashmem_area { + char name[ASHMEM_FULL_NAME_LEN];/* optional name for /proc/pid/maps */ + struct list_head unpinned_list; /* list of all ashmem areas */ + struct file *file; /* the shmem-based backing file */ + size_t size; /* size of the mapping, in bytes */ + unsigned long prot_mask; /* allowed prot bits, as vm_flags */ +}; + +/* + * ashmem_range - represents an interval of unpinned (evictable) pages + * Lifecycle: From unpin to pin + * Locking: Protected by `ashmem_mutex' + */ +struct ashmem_range { + struct list_head lru; /* entry in LRU list */ + struct list_head unpinned; /* entry in its area's unpinned list */ + struct ashmem_area *asma; /* associated area */ + size_t pgstart; /* starting page, inclusive */ + size_t pgend; /* ending page, inclusive */ + unsigned int purged; /* ASHMEM_NOT or ASHMEM_WAS_PURGED */ +}; + +/* LRU list of unpinned pages, protected by ashmem_mutex */ +static LIST_HEAD(ashmem_lru_list); + +/* Count of pages on our LRU list, protected by ashmem_mutex */ +static unsigned long lru_count; + +/* + * ashmem_mutex - protects the list of and each individual ashmem_area + * + * Lock Ordering: ashmex_mutex -> i_mutex -> i_alloc_sem + */ +static DEFINE_MUTEX(ashmem_mutex); + +static struct kmem_cache *ashmem_area_cachep __read_mostly; +static struct kmem_cache *ashmem_range_cachep __read_mostly; + +#define range_size(range) \ + ((range)->pgend - (range)->pgstart + 1) + +#define range_on_lru(range) \ + ((range)->purged == ASHMEM_NOT_PURGED) + +#define page_range_subsumes_range(range, start, end) \ + (((range)->pgstart >= (start)) && ((range)->pgend <= (end))) + +#define page_range_subsumed_by_range(range, start, end) \ + (((range)->pgstart <= (start)) && ((range)->pgend >= (end))) + +#define page_in_range(range, page) \ + (((range)->pgstart <= (page)) && ((range)->pgend >= (page))) + +#define page_range_in_range(range, start, end) \ + (page_in_range(range, start) || page_in_range(range, end) || \ + page_range_subsumes_range(range, start, end)) + +#define range_before_page(range, page) \ + ((range)->pgend < (page)) + +#define PROT_MASK (PROT_EXEC | PROT_READ | PROT_WRITE) + +static inline void lru_add(struct ashmem_range *range) +{ + list_add_tail(&range->lru, &ashmem_lru_list); + lru_count += range_size(range); +} + +static inline void lru_del(struct ashmem_range *range) +{ + list_del(&range->lru); + lru_count -= range_size(range); +} + +/* + * range_alloc - allocate and initialize a new ashmem_range structure + * + * 'asma' - associated ashmem_area + * 'prev_range' - the previous ashmem_range in the sorted asma->unpinned list + * 'purged' - initial purge value (ASMEM_NOT_PURGED or ASHMEM_WAS_PURGED) + * 'start' - starting page, inclusive + * 'end' - ending page, inclusive + * + * Caller must hold ashmem_mutex. + */ +static int range_alloc(struct ashmem_area *asma, + struct ashmem_range *prev_range, unsigned int purged, + size_t start, size_t end) +{ + struct ashmem_range *range; + + range = kmem_cache_zalloc(ashmem_range_cachep, GFP_KERNEL); + if (unlikely(!range)) + return -ENOMEM; + + range->asma = asma; + range->pgstart = start; + range->pgend = end; + range->purged = purged; + + list_add_tail(&range->unpinned, &prev_range->unpinned); + + if (range_on_lru(range)) + lru_add(range); + + return 0; +} + +static void range_del(struct ashmem_range *range) +{ + list_del(&range->unpinned); + if (range_on_lru(range)) + lru_del(range); + kmem_cache_free(ashmem_range_cachep, range); +} + +/* + * range_shrink - shrinks a range + * + * Caller must hold ashmem_mutex. + */ +static inline void range_shrink(struct ashmem_range *range, + size_t start, size_t end) +{ + size_t pre = range_size(range); + + range->pgstart = start; + range->pgend = end; + + if (range_on_lru(range)) + lru_count -= pre - range_size(range); +} + +static int ashmem_open(struct inode *inode, struct file *file) +{ + struct ashmem_area *asma; + int ret; + + ret = generic_file_open(inode, file); + if (unlikely(ret)) + return ret; + + asma = kmem_cache_zalloc(ashmem_area_cachep, GFP_KERNEL); + if (unlikely(!asma)) + return -ENOMEM; + + INIT_LIST_HEAD(&asma->unpinned_list); + memcpy(asma->name, ASHMEM_NAME_PREFIX, ASHMEM_NAME_PREFIX_LEN); + asma->prot_mask = PROT_MASK; + file->private_data = asma; + + return 0; +} + +static int ashmem_release(struct inode *ignored, struct file *file) +{ + struct ashmem_area *asma = file->private_data; + struct ashmem_range *range, *next; + + mutex_lock(&ashmem_mutex); + list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) + range_del(range); + mutex_unlock(&ashmem_mutex); + + if (asma->file) + fput(asma->file); + kmem_cache_free(ashmem_area_cachep, asma); + + return 0; +} + +static ssize_t ashmem_read(struct file *file, char __user *buf, + size_t len, loff_t *pos) +{ + struct ashmem_area *asma = file->private_data; + int ret = 0; + + mutex_lock(&ashmem_mutex); + + /* If size is not set, or set to 0, always return EOF. */ + if (asma->size == 0) { + goto out; + } + + if (!asma->file) { + ret = -EBADF; + goto out; + } + + ret = asma->file->f_op->read(asma->file, buf, len, pos); + if (ret < 0) { + goto out; + } + + /** Update backing file pos, since f_ops->read() doesn't */ + asma->file->f_pos = *pos; + +out: + mutex_unlock(&ashmem_mutex); + return ret; +} + +static loff_t ashmem_llseek(struct file *file, loff_t offset, int origin) +{ + struct ashmem_area *asma = file->private_data; + int ret; + + mutex_lock(&ashmem_mutex); + + if (asma->size == 0) { + ret = -EINVAL; + goto out; + } + + if (!asma->file) { + ret = -EBADF; + goto out; + } + + ret = asma->file->f_op->llseek(asma->file, offset, origin); + if (ret < 0) { + goto out; + } + + /** Copy f_pos from backing file, since f_ops->llseek() sets it */ + file->f_pos = asma->file->f_pos; + +out: + mutex_unlock(&ashmem_mutex); + return ret; +} + +static inline unsigned long +calc_vm_may_flags(unsigned long prot) +{ + return _calc_vm_trans(prot, PROT_READ, VM_MAYREAD ) | + _calc_vm_trans(prot, PROT_WRITE, VM_MAYWRITE) | + _calc_vm_trans(prot, PROT_EXEC, VM_MAYEXEC); +} + +extern void shmem_set_file(struct vm_area_struct *vma, struct file *file); + +static int ashmem_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct ashmem_area *asma = file->private_data; + int ret = 0; + + mutex_lock(&ashmem_mutex); + + /* user needs to SET_SIZE before mapping */ + if (unlikely(!asma->size)) { + ret = -EINVAL; + goto out; + } + + /* requested protection bits must match our allowed protection mask */ + if (unlikely((vma->vm_flags & ~calc_vm_prot_bits(asma->prot_mask)) & + calc_vm_prot_bits(PROT_MASK))) { + ret = -EPERM; + goto out; + } + vma->vm_flags &= ~calc_vm_may_flags(~asma->prot_mask); + + if (!asma->file) { + char *name = ASHMEM_NAME_DEF; + struct file *vmfile; + + if (asma->name[ASHMEM_NAME_PREFIX_LEN] != '\0') + name = asma->name; + + /* ... and allocate the backing shmem file */ + vmfile = shmem_file_setup(name, asma->size, vma->vm_flags); + if (unlikely(IS_ERR(vmfile))) { + ret = PTR_ERR(vmfile); + goto out; + } + asma->file = vmfile; + } + get_file(asma->file); + + if (vma->vm_flags & VM_SHARED) + shmem_set_file(vma, asma->file); + else { + if (vma->vm_file) + fput(vma->vm_file); + vma->vm_file = asma->file; + } + vma->vm_flags |= VM_CAN_NONLINEAR; + +out: + mutex_unlock(&ashmem_mutex); + return ret; +} + +/* + * ashmem_shrink - our cache shrinker, called from mm/vmscan.c :: shrink_slab + * + * 'nr_to_scan' is the number of objects (pages) to prune, or 0 to query how + * many objects (pages) we have in total. + * + * 'gfp_mask' is the mask of the allocation that got us into this mess. + * + * Return value is the number of objects (pages) remaining, or -1 if we cannot + * proceed without risk of deadlock (due to gfp_mask). + * + * We approximate LRU via least-recently-unpinned, jettisoning unpinned partial + * chunks of ashmem regions LRU-wise one-at-a-time until we hit 'nr_to_scan' + * pages freed. + */ +static int ashmem_shrink(struct shrinker *s, int nr_to_scan, gfp_t gfp_mask) +{ + struct ashmem_range *range, *next; + + /* We might recurse into filesystem code, so bail out if necessary */ + if (nr_to_scan && !(gfp_mask & __GFP_FS)) + return -1; + if (!nr_to_scan) + return lru_count; + + mutex_lock(&ashmem_mutex); + list_for_each_entry_safe(range, next, &ashmem_lru_list, lru) { + struct inode *inode = range->asma->file->f_dentry->d_inode; + loff_t start = range->pgstart * PAGE_SIZE; + loff_t end = (range->pgend + 1) * PAGE_SIZE - 1; + + vmtruncate_range(inode, start, end); + range->purged = ASHMEM_WAS_PURGED; + lru_del(range); + + nr_to_scan -= range_size(range); + if (nr_to_scan <= 0) + break; + } + mutex_unlock(&ashmem_mutex); + + return lru_count; +} + +static struct shrinker ashmem_shrinker = { + .shrink = ashmem_shrink, + .seeks = DEFAULT_SEEKS * 4, +}; + +static int set_prot_mask(struct ashmem_area *asma, unsigned long prot) +{ + int ret = 0; + + mutex_lock(&ashmem_mutex); + + /* the user can only remove, not add, protection bits */ + if (unlikely((asma->prot_mask & prot) != prot)) { + ret = -EINVAL; + goto out; + } + + /* does the application expect PROT_READ to imply PROT_EXEC? */ + if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC)) + prot |= PROT_EXEC; + + asma->prot_mask = prot; + +out: + mutex_unlock(&ashmem_mutex); + return ret; +} + +static int set_name(struct ashmem_area *asma, void __user *name) +{ + int ret = 0; + + mutex_lock(&ashmem_mutex); + + /* cannot change an existing mapping's name */ + if (unlikely(asma->file)) { + ret = -EINVAL; + goto out; + } + + if (unlikely(copy_from_user(asma->name + ASHMEM_NAME_PREFIX_LEN, + name, ASHMEM_NAME_LEN))) + ret = -EFAULT; + asma->name[ASHMEM_FULL_NAME_LEN-1] = '\0'; + +out: + mutex_unlock(&ashmem_mutex); + + return ret; +} + +static int get_name(struct ashmem_area *asma, void __user *name) +{ + int ret = 0; + + mutex_lock(&ashmem_mutex); + if (asma->name[ASHMEM_NAME_PREFIX_LEN] != '\0') { + size_t len; + + /* + * Copying only `len', instead of ASHMEM_NAME_LEN, bytes + * prevents us from revealing one user's stack to another. + */ + len = strlen(asma->name + ASHMEM_NAME_PREFIX_LEN) + 1; + if (unlikely(copy_to_user(name, + asma->name + ASHMEM_NAME_PREFIX_LEN, len))) + ret = -EFAULT; + } else { + if (unlikely(copy_to_user(name, ASHMEM_NAME_DEF, + sizeof(ASHMEM_NAME_DEF)))) + ret = -EFAULT; + } + mutex_unlock(&ashmem_mutex); + + return ret; +} + +/* + * ashmem_pin - pin the given ashmem region, returning whether it was + * previously purged (ASHMEM_WAS_PURGED) or not (ASHMEM_NOT_PURGED). + * + * Caller must hold ashmem_mutex. + */ +static int ashmem_pin(struct ashmem_area *asma, size_t pgstart, size_t pgend) +{ + struct ashmem_range *range, *next; + int ret = ASHMEM_NOT_PURGED; + + list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) { + /* moved past last applicable page; we can short circuit */ + if (range_before_page(range, pgstart)) + break; + + /* + * The user can ask us to pin pages that span multiple ranges, + * or to pin pages that aren't even unpinned, so this is messy. + * + * Four cases: + * 1. The requested range subsumes an existing range, so we + * just remove the entire matching range. + * 2. The requested range overlaps the start of an existing + * range, so we just update that range. + * 3. The requested range overlaps the end of an existing + * range, so we just update that range. + * 4. The requested range punches a hole in an existing range, + * so we have to update one side of the range and then + * create a new range for the other side. + */ + if (page_range_in_range(range, pgstart, pgend)) { + ret |= range->purged; + + /* Case #1: Easy. Just nuke the whole thing. */ + if (page_range_subsumes_range(range, pgstart, pgend)) { + range_del(range); + continue; + } + + /* Case #2: We overlap from the start, so adjust it */ + if (range->pgstart >= pgstart) { + range_shrink(range, pgend + 1, range->pgend); + continue; + } + + /* Case #3: We overlap from the rear, so adjust it */ + if (range->pgend <= pgend) { + range_shrink(range, range->pgstart, pgstart-1); + continue; + } + + /* + * Case #4: We eat a chunk out of the middle. A bit + * more complicated, we allocate a new range for the + * second half and adjust the first chunk's endpoint. + */ + range_alloc(asma, range, range->purged, + pgend + 1, range->pgend); + range_shrink(range, range->pgstart, pgstart - 1); + break; + } + } + + return ret; +} + +/* + * ashmem_unpin - unpin the given range of pages. Returns zero on success. + * + * Caller must hold ashmem_mutex. + */ +static int ashmem_unpin(struct ashmem_area *asma, size_t pgstart, size_t pgend) +{ + struct ashmem_range *range, *next; + unsigned int purged = ASHMEM_NOT_PURGED; + +restart: + list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) { + /* short circuit: this is our insertion point */ + if (range_before_page(range, pgstart)) + break; + + /* + * The user can ask us to unpin pages that are already entirely + * or partially pinned. We handle those two cases here. + */ + if (page_range_subsumed_by_range(range, pgstart, pgend)) + return 0; + if (page_range_in_range(range, pgstart, pgend)) { + pgstart = min_t(size_t, range->pgstart, pgstart), + pgend = max_t(size_t, range->pgend, pgend); + purged |= range->purged; + range_del(range); + goto restart; + } + } + + return range_alloc(asma, range, purged, pgstart, pgend); +} + +/* + * ashmem_get_pin_status - Returns ASHMEM_IS_UNPINNED if _any_ pages in the + * given interval are unpinned and ASHMEM_IS_PINNED otherwise. + * + * Caller must hold ashmem_mutex. + */ +static int ashmem_get_pin_status(struct ashmem_area *asma, size_t pgstart, + size_t pgend) +{ + struct ashmem_range *range; + int ret = ASHMEM_IS_PINNED; + + list_for_each_entry(range, &asma->unpinned_list, unpinned) { + if (range_before_page(range, pgstart)) + break; + if (page_range_in_range(range, pgstart, pgend)) { + ret = ASHMEM_IS_UNPINNED; + break; + } + } + + return ret; +} + +static int ashmem_pin_unpin(struct ashmem_area *asma, unsigned long cmd, + void __user *p) +{ + struct ashmem_pin pin; + size_t pgstart, pgend; + int ret = -EINVAL; + + if (unlikely(!asma->file)) + return -EINVAL; + + if (unlikely(copy_from_user(&pin, p, sizeof(pin)))) + return -EFAULT; + + /* per custom, you can pass zero for len to mean "everything onward" */ + if (!pin.len) + pin.len = PAGE_ALIGN(asma->size) - pin.offset; + + if (unlikely((pin.offset | pin.len) & ~PAGE_MASK)) + return -EINVAL; + + if (unlikely(((__u32) -1) - pin.offset < pin.len)) + return -EINVAL; + + if (unlikely(PAGE_ALIGN(asma->size) < pin.offset + pin.len)) + return -EINVAL; + + pgstart = pin.offset / PAGE_SIZE; + pgend = pgstart + (pin.len / PAGE_SIZE) - 1; + + mutex_lock(&ashmem_mutex); + + switch (cmd) { + case ASHMEM_PIN: + ret = ashmem_pin(asma, pgstart, pgend); + break; + case ASHMEM_UNPIN: + ret = ashmem_unpin(asma, pgstart, pgend); + break; + case ASHMEM_GET_PIN_STATUS: + ret = ashmem_get_pin_status(asma, pgstart, pgend); + break; + } + + mutex_unlock(&ashmem_mutex); + + return ret; +} + +static long ashmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct ashmem_area *asma = file->private_data; + long ret = -ENOTTY; + + switch (cmd) { + case ASHMEM_SET_NAME: + ret = set_name(asma, (void __user *) arg); + break; + case ASHMEM_GET_NAME: + ret = get_name(asma, (void __user *) arg); + break; + case ASHMEM_SET_SIZE: + ret = -EINVAL; + if (!asma->file) { + ret = 0; + asma->size = (size_t) arg; + } + break; + case ASHMEM_GET_SIZE: + ret = asma->size; + break; + case ASHMEM_SET_PROT_MASK: + ret = set_prot_mask(asma, arg); + break; + case ASHMEM_GET_PROT_MASK: + ret = asma->prot_mask; + break; + case ASHMEM_PIN: + case ASHMEM_UNPIN: + case ASHMEM_GET_PIN_STATUS: + ret = ashmem_pin_unpin(asma, cmd, (void __user *) arg); + break; + case ASHMEM_PURGE_ALL_CACHES: + ret = -EPERM; + if (capable(CAP_SYS_ADMIN)) { + ret = ashmem_shrink(&ashmem_shrinker, 0, GFP_KERNEL); + ashmem_shrink(&ashmem_shrinker, ret, GFP_KERNEL); + } + break; + } + + return ret; +} + +static struct file_operations ashmem_fops = { + .owner = THIS_MODULE, + .open = ashmem_open, + .release = ashmem_release, + .read = ashmem_read, + .llseek = ashmem_llseek, + .mmap = ashmem_mmap, + .unlocked_ioctl = ashmem_ioctl, + .compat_ioctl = ashmem_ioctl, +}; + +static struct miscdevice ashmem_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = "ashmem", + .fops = &ashmem_fops, +}; + +static int __init ashmem_init(void) +{ + int ret; + + ashmem_area_cachep = kmem_cache_create("ashmem_area_cache", + sizeof(struct ashmem_area), + 0, 0, NULL); + if (unlikely(!ashmem_area_cachep)) { + printk(KERN_ERR "ashmem: failed to create slab cache\n"); + return -ENOMEM; + } + + ashmem_range_cachep = kmem_cache_create("ashmem_range_cache", + sizeof(struct ashmem_range), + 0, 0, NULL); + if (unlikely(!ashmem_range_cachep)) { + printk(KERN_ERR "ashmem: failed to create slab cache\n"); + return -ENOMEM; + } + + ret = misc_register(&ashmem_misc); + if (unlikely(ret)) { + printk(KERN_ERR "ashmem: failed to register misc device!\n"); + return ret; + } + + register_shrinker(&ashmem_shrinker); + + printk(KERN_INFO "ashmem: initialized\n"); + + return 0; +} + +static void __exit ashmem_exit(void) +{ + int ret; + + unregister_shrinker(&ashmem_shrinker); + + ret = misc_deregister(&ashmem_misc); + if (unlikely(ret)) + printk(KERN_ERR "ashmem: failed to unregister misc device!\n"); + + kmem_cache_destroy(ashmem_range_cachep); + kmem_cache_destroy(ashmem_area_cachep); + + printk(KERN_INFO "ashmem: unloaded\n"); +} + +module_init(ashmem_init); +module_exit(ashmem_exit); + +MODULE_LICENSE("GPL"); diff --git a/mm/shmem.c b/mm/shmem.c index f65f84062db5..5446c68fc79d 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -2739,6 +2739,14 @@ put_memory: } EXPORT_SYMBOL_GPL(shmem_file_setup); +void shmem_set_file(struct vm_area_struct *vma, struct file *file) +{ + if (vma->vm_file) + fput(vma->vm_file); + vma->vm_file = file; + vma->vm_ops = &shmem_vm_ops; +} + /** * shmem_zero_setup - setup a shared anonymous mapping * @vma: the vma to be mmapped is prepared by do_mmap_pgoff @@ -2751,10 +2759,6 @@ int shmem_zero_setup(struct vm_area_struct *vma) file = shmem_file_setup("dev/zero", size, vma->vm_flags); if (IS_ERR(file)) return PTR_ERR(file); - - if (vma->vm_file) - fput(vma->vm_file); - vma->vm_file = file; - vma->vm_ops = &shmem_vm_ops; + shmem_set_file(vma, file); return 0; } diff --git a/net/core/dev.c b/net/core/dev.c index 1f466e82ac33..33a21d46dfcf 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -4531,6 +4531,9 @@ static int dev_ifsioc(struct net *net, struct ifreq *ifr, unsigned int cmd) default: if ((cmd >= SIOCDEVPRIVATE && cmd <= SIOCDEVPRIVATE + 15) || +#if defined(CONFIG_FEC_L2SWITCH) + (cmd >= 0x9101 && cmd <= 0x92ff) || +#endif cmd == SIOCBONDENSLAVE || cmd == SIOCBONDRELEASE || cmd == SIOCBONDSETHWADDR || @@ -4723,6 +4726,9 @@ int dev_ioctl(struct net *net, unsigned int cmd, void __user *arg) */ default: if (cmd == SIOCWANDEV || +#if defined(CONFIG_FEC_L2SWITCH) + (cmd >= 0x9101 && cmd <= 0x92ff) || +#endif (cmd >= SIOCDEVPRIVATE && cmd <= SIOCDEVPRIVATE + 15)) { dev_load(net, ifr.ifr_name); diff --git a/net/dsa/slave.c b/net/dsa/slave.c index 8fdca56bb08f..64ca2a6fa0d4 100644 --- a/net/dsa/slave.c +++ b/net/dsa/slave.c @@ -164,10 +164,9 @@ out: static int dsa_slave_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { struct dsa_slave_priv *p = netdev_priv(dev); - struct mii_ioctl_data *mii_data = if_mii(ifr); if (p->phy != NULL) - return phy_mii_ioctl(p->phy, mii_data, cmd); + return phy_mii_ioctl(p->phy, ifr, cmd); return -EOPNOTSUPP; } diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index 551ce564b035..6dac2d9f35ef 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -864,6 +864,7 @@ int inet_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) case SIOCSIFPFLAGS: case SIOCGIFPFLAGS: case SIOCSIFFLAGS: + case SIOCKILLADDR: err = devinet_ioctl(net, cmd, (void __user *)arg); break; default: diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c index da14c49284f4..8b7dfaf3b6ea 100644 --- a/net/ipv4/devinet.c +++ b/net/ipv4/devinet.c @@ -58,6 +58,7 @@ #include #include +#include #include #include #include @@ -635,6 +636,7 @@ int devinet_ioctl(struct net *net, unsigned int cmd, void __user *arg) case SIOCSIFBRDADDR: /* Set the broadcast address */ case SIOCSIFDSTADDR: /* Set the destination address */ case SIOCSIFNETMASK: /* Set the netmask for the interface */ + case SIOCKILLADDR: /* Nuke all sockets on this address */ ret = -EACCES; if (!capable(CAP_NET_ADMIN)) goto out; @@ -686,7 +688,8 @@ int devinet_ioctl(struct net *net, unsigned int cmd, void __user *arg) } ret = -EADDRNOTAVAIL; - if (!ifa && cmd != SIOCSIFADDR && cmd != SIOCSIFFLAGS) + if (!ifa && cmd != SIOCSIFADDR && cmd != SIOCSIFFLAGS + && cmd != SIOCKILLADDR) goto done; switch (cmd) { @@ -811,6 +814,10 @@ int devinet_ioctl(struct net *net, unsigned int cmd, void __user *arg) inet_insert_ifa(ifa); } break; + case SIOCKILLADDR: /* Nuke all connections on this address */ + ret = 0; + tcp_v4_nuke_addr(sin->sin_addr.s_addr); + break; } done: rtnl_unlock(); diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 65afeaec15b7..61dccaf37f1c 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -266,6 +266,7 @@ #include #include #include +#include #include #include @@ -1101,6 +1102,9 @@ out: tcp_push(sk, flags, mss_now, tp->nonagle); TCP_CHECK_TIMER(sk); release_sock(sk); + + if (copied > 0) + uid_stat_tcp_snd(current_uid(), copied); return copied; do_fault: @@ -1377,8 +1381,10 @@ int tcp_read_sock(struct sock *sk, read_descriptor_t *desc, tcp_rcv_space_adjust(sk); /* Clean up data we have read: This will do ACK frames. */ - if (copied > 0) + if (copied > 0) { tcp_cleanup_rbuf(sk, copied); + uid_stat_tcp_rcv(current_uid(), copied); + } return copied; } @@ -1764,6 +1770,9 @@ skip_copy: TCP_CHECK_TIMER(sk); release_sock(sk); + + if (copied > 0) + uid_stat_tcp_rcv(current_uid(), copied); return copied; out: @@ -1773,6 +1782,8 @@ out: recv_urg: err = tcp_recv_urg(sk, msg, len, flags); + if (err > 0) + uid_stat_tcp_rcv(current_uid(), err); goto out; } diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index fe193e53af44..3c7b72437b58 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c @@ -1963,6 +1963,49 @@ void tcp_v4_destroy_sock(struct sock *sk) EXPORT_SYMBOL(tcp_v4_destroy_sock); +/* + * tcp_v4_nuke_addr - destroy all sockets on the given local address + */ +void tcp_v4_nuke_addr(__u32 saddr) +{ + unsigned int bucket; + + for (bucket = 0; bucket < tcp_hashinfo.ehash_mask; bucket++) { + struct hlist_nulls_node *node; + struct sock *sk; + spinlock_t *lock = inet_ehash_lockp(&tcp_hashinfo, bucket); + +restart: + spin_lock_bh(lock); + sk_nulls_for_each(sk, node, &tcp_hashinfo.ehash[bucket].chain) { + struct inet_sock *inet = inet_sk(sk); + + if (inet->inet_rcv_saddr != saddr) + continue; + if (sysctl_ip_dynaddr && sk->sk_state == TCP_SYN_SENT) + continue; + if (sock_flag(sk, SOCK_DEAD)) + continue; + + sock_hold(sk); + spin_unlock_bh(lock); + + local_bh_disable(); + bh_lock_sock(sk); + sk->sk_err = ETIMEDOUT; + sk->sk_error_report(sk); + + tcp_done(sk); + bh_unlock_sock(sk); + local_bh_enable(); + sock_put(sk); + + goto restart; + } + spin_unlock_bh(lock); + } +} + #ifdef CONFIG_PROC_FS /* Proc filesystem TCP sock list dumping. */ diff --git a/sound/arm/Kconfig b/sound/arm/Kconfig index 885683a3b0bd..ae88981852b0 100644 --- a/sound/arm/Kconfig +++ b/sound/arm/Kconfig @@ -39,5 +39,54 @@ config SND_PXA2XX_AC97 Say Y or M if you want to support any AC97 codec attached to the PXA2xx AC97 interface. +config SND_MXC_SPDIF + tristate "MXC SPDIF sound card spport" + select SND_PCM + help + Say Y here to enable SPDIF sound card + +config SND_MXC_PMIC + tristate "MXC PMIC sound system" + depends on ARCH_MXC && MXC_DAM && MXC_SSI && \ + (MXC_MC13783_AUDIO || MXC_PMIC_SC55112_AUDIO) + default y + select SND_PCM + help + Say Y here to include support for soundcards based on the + MC13783 chip. + + To compile this driver as a module, choose M here: the module + will be called snd-mc13783. + +config SND_MXC_PLAYBACK_MIXING + bool "Playback Stream Mixing" + depends on (!ARCH_MX27) && (!ARCH_MXC91131) && ARCH_MXC && MXC_DAM && MXC_SSI && \ + (MXC_MC13783_AUDIO) + default n + select SND_PCM + help + Say Y here to include support mixing for soundcards based on the + MC13783 chip. This supports audio stream mixing on VCODEC for mc13783 based platforms. + Analog mixng as well as Digital mixing can be tested on these platforms. + As of now , mixing of mono files only are supported in Digital Mixing since it is done on VCODEC. + SSI 2 channel mode is used to mix 2 streams on a single SSI. This is supported on all platforms except imx27ads(imx27ads - Analog mixing only). + +config HEADSET_DETECT_ENABLE + bool "Headset Detect Enable" + depends on (!ARCH_MXC91131) && ARCH_MXC && MXC_DAM && MXC_SSI && \ + (MXC_MC13783_AUDIO) + default n + select SND_PCM + help + Say Y here to enable Headset Detect Feature. + +config SND_MXC_PMIC_IRAM + bool "MXC PMIC sound system supports IRAM" + depends on SND_MXC_PMIC && SDMA_IRAM + default n + select SND_PCM + help + It will use IRAM as the DMA buffer of ALSA playback. + endif # SND_ARM diff --git a/sound/arm/Makefile b/sound/arm/Makefile index 8c0c851d4641..c943c65ba032 100644 --- a/sound/arm/Makefile +++ b/sound/arm/Makefile @@ -14,3 +14,14 @@ snd-pxa2xx-lib-$(CONFIG_SND_PXA2XX_LIB_AC97) += pxa2xx-ac97-lib.o obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o snd-pxa2xx-ac97-objs := pxa2xx-ac97.o + +# +# Define the header file locations for PMIC drivers. +# +CFLAGS_mxc-alsa-pmic.o = -I$(srctree)/drivers/mxc +obj-$(CONFIG_SND_MXC_PMIC) += snd-mxc-alsa.o +snd-mxc-alsa-objs := mxc-alsa-pmic.o mxc-alsa-mixer.o + +CFLGS_mxc_alsa_spdif.o = -I$(TOPDIR)/drivers/mxc +obj-$(CONFIG_SND_MXC_SPDIF) += snd-spdif.o +snd-spdif-objs := mxc-alsa-spdif.o diff --git a/sound/arm/mxc-alsa-common.h b/sound/arm/mxc-alsa-common.h new file mode 100644 index 000000000000..09d8d8de842a --- /dev/null +++ b/sound/arm/mxc-alsa-common.h @@ -0,0 +1,68 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file mxc-alsa-common.h + * @brief + * @ingroup SOUND_DRV + */ + +#ifndef __MXC_ALSA_COMMON_H__ +#define __MXC_ALSA_COMMON_H__ + +/* Enums typically used by the Mixer support APIs + * Emunerates IP, OP and mixer sources. + */ + +typedef enum { + CODEC_DIR_OUT, + MIXER_OUT +} OUTPUT_SOURCE; + +typedef enum { + OP_NODEV = -1, + OP_EARPIECE, + OP_HANDSFREE, + OP_HEADSET, + OP_LINEOUT, + OP_MAXDEV, + OP_MONO +} OUTPUT_DEVICES; + +typedef enum { + IP_NODEV = -1, + IP_HANDSET, + IP_HEADSET, + IP_LINEIN, + IP_MAXDEV +} INPUT_DEVICES; + +extern int mxc_alsa_create_ctl(struct snd_card *card, void *p_value); + +extern int set_mixer_output_device(PMIC_AUDIO_HANDLE handle, OUTPUT_SOURCE src, + OUTPUT_DEVICES dev, bool enable); +extern int set_mixer_output_volume(PMIC_AUDIO_HANDLE handle, int volume, + OUTPUT_DEVICES dev); +extern int set_mixer_input_device(PMIC_AUDIO_HANDLE handle, INPUT_DEVICES dev, + bool enable); +extern int set_mixer_output_mono_adder(PMIC_AUDIO_MONO_ADDER_MODE mode); +extern int set_mixer_input_gain(PMIC_AUDIO_HANDLE handle, int val); +extern int set_mixer_output_balance(int bal); + +extern int get_mixer_output_device(void); +extern int get_mixer_output_volume(void); +extern int get_mixer_output_mono_adder(void); +extern int get_mixer_output_balance(void); +extern int get_mixer_input_gain(void); +extern int get_mixer_input_device(void); +#endif /* __MXC_ALSA_COMMON_H__ */ diff --git a/sound/arm/mxc-alsa-mixer.c b/sound/arm/mxc-alsa-mixer.c new file mode 100644 index 000000000000..bd46d3a5f7f1 --- /dev/null +++ b/sound/arm/mxc-alsa-mixer.c @@ -0,0 +1,411 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file mxc-alsa-mixer.c + * @brief this file implements the mxc sound driver mixer interface for ALSA. + * The mxc sound driver supports mono/stereo recording (there are + * some limitations due to hardware), mono/stereo playback and + * audio mixing. This file implements output switching, volume/balance controls + * mono adder config, I/P dev switching and gain on the PCM streams. + * Recording supports 8000 khz and 16000 khz sample rate. + * Playback supports 8000, 11025, 16000, 22050, 24000, 32000, + * 44100 and 48000 khz for mono and stereo. + * + * @ingroup SOUND_DRV + */ + +#include +#include +#include +#include +#include +#include +#include "mxc-alsa-common.h" +/*! + * These are the functions implemented in the ALSA PCM driver that + * are used for mixer operations + * + */ + +/*! + * These are the callback functions for mixer controls + * + */ +/* Output device control*/ +static int pmic_mixer_output_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 15; + uinfo->value.integer.step = 1; + return 0; +} +static int pmic_mixer_output_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int dev, i; + dev = uvalue->value.integer.value[0]; + for (i = OP_EARPIECE; i < OP_MAXDEV; i++) { + if (dev & (1 << i)) { + set_mixer_output_device(NULL, MIXER_OUT, i, 1); + } else { + set_mixer_output_device(NULL, MIXER_OUT, i, 0); + } + } + return 0; +} +static int pmic_mixer_output_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int val, ret = 0, i = 0; + for (i = OP_EARPIECE; i < OP_MAXDEV; i++) { + val = get_mixer_output_device(); + if (val & SOUND_MASK_PHONEOUT) + ret = ret | 1; + if (val & SOUND_MASK_SPEAKER) + ret = ret | 2; + if (val & SOUND_MASK_VOLUME) + ret = ret | 4; + if (val & SOUND_MASK_PCM) + ret = ret | 8; + uvalue->value.integer.value[0] = ret; + } + return 0; + +} + +/* Input gain control*/ +static int pmic_cap_volume_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 100; + uinfo->value.integer.step = 1; + return 0; +} +static int pmic_cap_volume_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int val; + val = get_mixer_input_gain(); + val = val & 0xFF; + uvalue->value.integer.value[0] = val; + return 0; +} + +static int pmic_cap_volume_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + + int vol; + vol = uvalue->value.integer.value[0]; + vol = vol | (vol << 8); + set_mixer_input_gain(NULL, vol); + return 0; +} + +/* Mono adder control*/ +static int pmic_pb_monoconfig_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 3; + uinfo->value.integer.step = 1; + return 0; +} +static int pmic_pb_monoconfig_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int mono; + mono = uvalue->value.integer.value[0]; + set_mixer_output_mono_adder(mono); + return 0; +} +static int pmic_pb_monoconfig_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + uvalue->value.integer.value[0] = get_mixer_output_mono_adder(); + return 0; +} + +/*! + * These are the ALSA control structures with init values + * + */ + +/* Input device control*/ +static int pmic_cap_input_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 7; + uinfo->value.integer.step = 1; + return 0; +} +static int pmic_cap_input_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int dev, i; + dev = uvalue->value.integer.value[0]; + for (i = IP_HANDSET; i < IP_MAXDEV; i++) { + dev &= (1 << i); + if (dev) { + set_mixer_input_device(NULL, i, 1); + } else { + set_mixer_input_device(NULL, i, 0); + } + } + return 0; +} +static int pmic_cap_input_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int val, ret = 0, i = 0; + for (i = IP_HANDSET; i < IP_MAXDEV; i++) { + val = get_mixer_input_device(); + if (val & SOUND_MASK_PHONEIN) + ret = ret | 1; + if (val & SOUND_MASK_MIC) + ret = ret | 2; + if (val & SOUND_MASK_LINE) + ret = ret | 4; + uvalue->value.integer.value[0] = ret; + } + return 0; +} + +/* Volume control*/ +static int pmic_pb_volume_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int volume; + volume = uvalue->value.integer.value[0]; + volume = volume | (volume << 8); + set_mixer_output_volume(NULL, volume, OP_NODEV); + return 0; +} +static int pmic_pb_volume_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 1; + uinfo->value.integer.max = 100; + uinfo->value.integer.step = 1; + return 0; +} + +static int pmic_pb_volume_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int val; + val = get_mixer_output_volume(); + val = val & 0xFF; + uvalue->value.integer.value[0] = val; + return 0; +} + +/* Balance control start */ +static int pmic_pb_balance_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 100; + uinfo->value.integer.step = 1; + return 0; +} + +static int pmic_pb_balance_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + uvalue->value.integer.value[0] = get_mixer_output_balance(); + return 0; + +} +static int pmic_pb_balance_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int bal; + bal = uvalue->value.integer.value[0]; + set_mixer_output_balance(bal); + return 0; +} + +/* Balance control end */ + +/* loopback control start */ +static int pmic_loopback_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + return 0; +} + +static int pmic_loopback_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + uvalue->value.integer.value[0] = kcontrol->private_value; + return 0; + +} +static int pmic_loopback_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + int changed; + long flag = uvalue->value.integer.value[0]; + changed = + (uvalue->value.integer.value[0] == kcontrol->private_value) ? 0 : 1; + kcontrol->private_value = uvalue->value.integer.value[0]; + if (flag) + pmic_audio_fm_output_enable(true); + else + pmic_audio_fm_output_enable(false); + + return changed; +} + +/* Loopback control end */ + +/* Kcontrol structure definitions */ +struct snd_kcontrol_new pmic_control_pb_vol __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Master Playback Volume", + .index = 0x00, + .info = pmic_pb_volume_info, + .get = pmic_pb_volume_get, + .put = pmic_pb_volume_put, + .private_value = 0xffab1, +}; + +struct snd_kcontrol_new pmic_control_pb_bal __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Master Balance Playback Volume", + .index = 0x00, + .info = pmic_pb_balance_info, + .get = pmic_pb_balance_get, + .put = pmic_pb_balance_put, + .private_value = 0xffab2, +}; +struct snd_kcontrol_new pmic_control_pb_monoconfig __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Master Monoconfig Playback Volume", + .index = 0x00, + .info = pmic_pb_monoconfig_info, + .get = pmic_pb_monoconfig_get, + .put = pmic_pb_monoconfig_put, + .private_value = 0xffab2, +}; +struct snd_kcontrol_new pmic_control_op_sw __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Master Output Playback Volume", + .index = 0x00, + .info = pmic_mixer_output_info, + .get = pmic_mixer_output_get, + .put = pmic_mixer_output_put, + .private_value = 0xffab4, +}; + +struct snd_kcontrol_new pmic_control_cap_vol __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Master Capture Volume", + .index = 0x00, + .info = pmic_cap_volume_info, + .get = pmic_cap_volume_get, + .put = pmic_cap_volume_put, + .private_value = 0xffab5, +}; +struct snd_kcontrol_new pmic_control_ip_sw __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Master Input Capture Volume", + .index = 0x00, + .info = pmic_cap_input_info, + .get = pmic_cap_input_get, + .put = pmic_cap_input_put, + .private_value = 0xffab5, +}; + +struct snd_kcontrol_new pmic_control_loop_out __devinitdata = { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Loopback Line-in", + .index = 0x00, + .info = pmic_loopback_info, + .get = pmic_loopback_get, + .put = pmic_loopback_put, + .private_value = 0, +}; + +/*! + * This function registers the control components of ALSA Mixer + * It is called by ALSA PCM init. + * + * @param card pointer to the ALSA sound card structure. + * + * @return 0 on success, -ve otherwise. + */ +int __devinit mxc_alsa_create_ctl(struct snd_card *card, void *p_value) +{ + int err = 0; + + err = snd_ctl_add(card, snd_ctl_new1(&pmic_control_op_sw, p_value)); + if (err < 0) + return err; + + err = snd_ctl_add(card, snd_ctl_new1(&pmic_control_pb_vol, p_value)); + if (err < 0) + return err; + + err = snd_ctl_add(card, snd_ctl_new1(&pmic_control_pb_monoconfig, p_value)); + if (err < 0) + return err; + + err = snd_ctl_add(card, snd_ctl_new1(&pmic_control_pb_bal, p_value)); + if (err < 0) + return err; + + err = snd_ctl_add(card, snd_ctl_new1(&pmic_control_cap_vol, p_value)); + if (err < 0) + return err; + + err = snd_ctl_add(card, snd_ctl_new1(&pmic_control_ip_sw, p_value)); + if (err < 0) + return err; + + err = snd_ctl_add(card, snd_ctl_new1(&pmic_control_loop_out, p_value)); + if (err < 0) + return err; + + return 0; +} + +EXPORT_SYMBOL(mxc_alsa_create_ctl); diff --git a/sound/arm/mxc-alsa-pmic.c b/sound/arm/mxc-alsa-pmic.c new file mode 100644 index 000000000000..c8785ccefc28 --- /dev/null +++ b/sound/arm/mxc-alsa-pmic.c @@ -0,0 +1,3793 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @defgroup SOUND_DRV MXC Sound Driver for ALSA + */ + + /*! + * @file mxc-alsa-pmic.c + * @brief this fle mxc-alsa-pmic.c + * @brief this file implements the mxc sound driver interface for ALSA. + * The mxc sound driver supports mono/stereo recording (there are + * some limitations due to hardware), mono/stereo playback and + * audio mixing. + * Recording supports 8000 khz and 16000 khz sample rate. + * Playback supports 8000, 11025, 16000, 22050, 24000, 32000, + * 44100, 48000 and 96000 Hz for mono and stereo. + * This file also handles the software mixer and abstraction APIs + * that control the volume,balance,mono-adder,input and output + * devices for PMIC. + * These mixer controls shall be accessible thru alsa as well as + * OSS emulation modes + * + * @ingroup SOUND_DRV + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "mxc-alsa-pmic.h" +#include "mxc-alsa-common.h" + +/* + * PMIC driver buffer policy. + * Customize here if the sound is not correct + */ +#define MAX_BUFFER_SIZE (32*1024) +#define DMA_BUF_SIZE (8*1024) +#define MIN_PERIOD_SIZE 64 +#define MIN_PERIOD 2 +#define MAX_PERIOD 255 + +#define AUD_MUX_CONF 0x0031010 +#define MASK_2_TS 0xfffffffc +#define MASK_1_TS 0xfffffffd +#define MASK_1_TS_MIX 0xfffffffc +#define MASK_1_TS_STDAC 0xfffffffe +#define MASK_1_TS_REC 0xfffffffe +#define SOUND_CARD_NAME "MXC" + +#ifdef CONFIG_SND_MXC_PMIC_IRAM +#define MAX_IRAM_SIZE (IRAM_SIZE - CONFIG_SDMA_IRAM_SIZE) +#define DMA_IRAM_SIZE (4*1024) +#define ADMA_BASE_PADDR (IRAM_BASE_ADDR + CONFIG_SDMA_IRAM_SIZE) +#define ADMA_BASE_VADDR (IRAM_BASE_ADDR_VIRT + CONFIG_SDMA_IRAM_SIZE) + +#if (MAX_IRAM_SIZE + CONFIG_SDMA_IRAM_SIZE) > IRAM_SIZE +#error "The IRAM size required has beyond the limitation of IC spec" +#endif + +#if (MAX_IRAM_SIZE&(DMA_IRAM_SIZE-1)) +#error "The IRAM size for DMA ring buffer should be multiples of dma buffer size" +#endif + +#endif /* CONFIG_SND_MXC_PMIC_IRAM */ + +/*! + * These defines enable DMA chaining for playback + * and capture respectively. + */ +#define MXC_SOUND_PLAYBACK_CHAIN_DMA_EN 1 +#define MXC_SOUND_CAPTURE_CHAIN_DMA_EN 1 + +/*! + * ID for this card + */ +static char *id; + +#define MXC_ALSA_MAX_PCM_DEV 3 +#define MXC_ALSA_MAX_PLAYBACK 3 +#define MXC_ALSA_MAX_CAPTURE 1 + +struct mxc_audio_platform_data *audio_data; +/*! + * This structure is the global configuration of the soundcard + * that are accessed by the mixer as well as by the playback/recording + * stream. This contains various volume, balance, mono adder settings + * + */ +typedef struct audio_mixer_control { + + /*! + * This variable holds the current active output device(s) + */ + int output_device; + + /*! + * This variable holds the current active input device. + */ + int input_device; + + /* Used only for playback/recording on codec .. Use 1 for playback + * and 0 for recording*/ + int direction; + + /*! + * This variable holds the current source for active ouput device(s) + */ + OUTPUT_SOURCE source_for_output[OP_MAXDEV]; + + /*! + * This variable says if a given output device is part of an ongoing + * playback. This variable will be set and reset by the playback stream + * when stream is activated and when stream is closed. This shall also + * be set and reset my mixer functions for enabling/disabling output devs + */ + int output_active[OP_MAXDEV]; + + /*! + * This variable holds the current volume for active input device. + * This maps to the input gain of recording device + */ + int input_volume; + + /*! + * This variable holds the current volume for playback devices. + */ + int master_volume_out; + + /*! + * This variable holds the balance setting for the mixer out. + * The range is 0 to 100. 50 means both L and R equal. + * < 50 attenuates left side and > 50 attenualtes right side + */ + int mixer_balance; + + /*! + * This variable holds the current mono adder config. + */ + PMIC_AUDIO_MONO_ADDER_MODE mixer_mono_adder; + + /*! + * Semaphore used to control the access to this structure. + */ + struct semaphore sem; + + /*! + * These variables are set by PCM stream and mixer when the voice codec's / ST dac's outputs are + * connected to the analog mixer of PMIC audio chip + */ + int codec_out_to_mixer; + int stdac_out_to_mixer; + + int codec_playback_active; + int codec_capture_active; + int stdac_playback_active; + int mixing_active; + + /*! + * This variable holds the configuration of the headset which was previously enabled. + */ + int old_prof; + + PMIC_AUDIO_HANDLE stdac_handle; + PMIC_AUDIO_HANDLE voice_codec_handle; + +} audio_mixer_control_t; + +/*! + * This structure stores current state of audio configuration + * soundcard wrt a specific stream (playback on different DACs, recording on the codec etc). + * It is used to set/get current values and are NOT accessed by the Mixer. This structure shall + * be retrieved thru pcm substream pointer and hence the mixer component will have no access + * to it. There will be as many structures as the number of streams. In our case it's 3. Codec playback + * STDAC playback and voice codec recording. + * This structure will be used at the beginning of activating a stream to configure audio chip. + * + */ +typedef struct pmic_audio_device { + + PMIC_AUDIO_HANDLE handle; + /*! + * This variable holds the sample rate currently being used. + */ + int sample_rate; + + /*! + * This variable holds the current protocol PMIC is using. + * PMIC can use one of three protocols at any given time: + * normal, network and I2S. + */ + int protocol; + + /*! + * This variables tells us whether PMIC runs in + * master mode (PMIC generates audio clocks)or slave mode (AP side + * generates audio clocks) + * + * Currently the default mode is master mode because PMIC clocks have + * higher precision. + */ + int mode; + + /* This variable holds the value representing the + * base clock PMIC will use to generate internal + * clocks (BCL clock and FrameSync clock) + */ + int pll; + + /*! + * This variable holds the SSI to which PMIC is currently connected. + */ + int ssi; + + /*! + * This variable tell us whether bit clock is inverted or not. + */ + int bcl_inverted; + + /*! + * This variable tell us whether frame clock is inverted or not. + */ + int fs_inverted; + + /*! + * This variable holds the pll used for PMIC audio operations. + */ + int pll_rate; + + /*! + * This variable holds the filter that PMIC is applying to + * CODEC operations. + */ + int codec_filter; + +} pmic_audio_device_t; + +/*! + * This structure represents an audio stream in term of + * channel DMA, HW configuration on PMIC and on AudioMux/SSI + */ +typedef struct audio_stream { + /*! + * identification string + */ + char *id; + + /*! + * numeric identification + */ + int stream_id; + + /*! + * SSI ID on the ARM side + */ + int ssi; + + /*! + * DAM port on the ARM side + */ + int dam_port; + + /*! + * device identifier for DMA + */ + int dma_wchannel; + + /*! + * we are using this stream for transfer now + */ + int active:1; + + /*! + * current transfer period + */ + int period; + + /*! + * current count of transfered periods + */ + int periods; + + /*! + * are we recording - flag used to do DMA trans. for sync + */ + int tx_spin; + + /*! + * Previous offset value for resume + */ + unsigned int old_offset; +#if 0 + /*! + * Path for this stream + */ + device_data_t stream_device; +#endif + + /*! + * pmic audio chip stream specific configuration + */ + pmic_audio_device_t pmic_audio_device; + + /*! + * for locking in DMA operations + */ + spinlock_t dma_lock; + + /*! + * Alsa substream pointer + */ + struct snd_pcm_substream *stream; +} audio_stream_t; + +/*! + * This structure represents the PMIC sound card with its + * 2 streams (StDac and Codecs) and its shared parameters + */ +typedef struct snd_card_mxc_pmic_audio { + /*! + * ALSA sound card handle + */ + struct snd_card *card; + + /*! + * ALSA pcm driver type handle + */ + struct snd_pcm *pcm[MXC_ALSA_MAX_PCM_DEV]; + + /*! + * playback & capture streams handle + * We can support a maximum of two playback streams (voice-codec + * and ST-DAC) and 1 recording stream + */ + audio_stream_t s[MXC_ALSA_MAX_CAPTURE + MXC_ALSA_MAX_PLAYBACK]; + +} mxc_pmic_audio_t; + +/*! + * pmic audio chip parameters for IP/OP and volume controls + */ +audio_mixer_control_t audio_mixer_control; + +/*! + * Global variable that represents the PMIC soundcard + * with its 2 availables stream devices: stdac and codec + */ +mxc_pmic_audio_t *mxc_audio; + +/*! + * Supported playback rates array + */ +static unsigned int playback_rates_stereo[] = { + 8000, + 11025, + 12000, + 16000, + 22050, + 24000, + 32000, + 44100, + 48000, + 64000, + 96000, +}; + +static unsigned int playback_rates_mono[] = { + 8000, + 16000, +}; + +/*! + * Supported capture rates array + */ +static unsigned int capture_rates[] = { + 8000, + 16000, +}; + +/*! + * this structure represents the sample rates supported + * by PMIC for playback operations on StDac. + */ +static struct snd_pcm_hw_constraint_list hw_playback_rates_stereo = { + .count = ARRAY_SIZE(playback_rates_stereo), + .list = playback_rates_stereo, + .mask = 0, +}; + +#ifdef CONFIG_SND_MXC_PMIC_IRAM +static DEFINE_SPINLOCK(g_audio_iram_lock); +static int g_audio_iram_en = 1; +static int g_device_opened; +extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end); + +static inline int mxc_snd_enable_iram(int enable) +{ + int ret = -EBUSY; + unsigned long flags; + spin_lock_irqsave(&g_audio_iram_lock, flags); + if (!g_device_opened) { + g_audio_iram_en = (enable != 0); + ret = 0; + } + spin_unlock_irqrestore(&g_audio_iram_lock, flags); + return ret; +} + +static inline void mxc_snd_pcm_iram_get(void) +{ + unsigned long flags; + spin_lock_irqsave(&g_audio_iram_lock, flags); + g_audio_iram_en++; + spin_unlock_irqrestore(&g_audio_iram_lock, flags); +} + +static inline void mxc_snd_pcm_iram_put(void) +{ + unsigned long flags; + spin_lock_irqsave(&g_audio_iram_lock, flags); + g_audio_iram_en--; + spin_unlock_irqrestore(&g_audio_iram_lock, flags); +} + +struct snd_dma_buffer g_iram_dmab; + +#endif /* CONFIG_SND_MXC_PMIC_IRAM */ + +/*! + * this structure represents the sample rates supported + * by PMIC for playback operations on Voice codec. + */ +static struct snd_pcm_hw_constraint_list hw_playback_rates_mono = { + .count = ARRAY_SIZE(playback_rates_mono), + .list = playback_rates_mono, + .mask = 0, +}; + +/*! + * this structure represents the sample rates supported + * by PMIC for capture operations on Codec. + */ +static struct snd_pcm_hw_constraint_list hw_capture_rates = { + .count = ARRAY_SIZE(capture_rates), + .list = capture_rates, + .mask = 0, +}; + +#ifdef CONFIG_HEADSET_DETECT_ENABLE +static PMIC_HS_STATE hs_state; + +/*! + *This is used to maintain the state of the Headset*/ +static int headset_state; + +/*Callback for headset event. */ +static void HSCallback(const PMIC_HS_STATE hs_st) +{ + + msleep(10); + + if (headset_state == 1) { + pmic_audio_output_disable_phantom_ground(); + headset_state = 0; + if (audio_mixer_control.stdac_playback_active) + pmic_audio_output_clear_port(audio_mixer_control. + stdac_handle, + STEREO_HEADSET_LEFT | + STEREO_HEADSET_RIGHT); + else if (audio_mixer_control.voice_codec_handle) + pmic_audio_output_clear_port(audio_mixer_control. + voice_codec_handle, + STEREO_HEADSET_LEFT | + STEREO_HEADSET_RIGHT); + + if (audio_mixer_control.old_prof & (SOUND_MASK_PHONEOUT)) { + set_mixer_output_device(NULL, MIXER_OUT, OP_EARPIECE, + 1); + } + if (audio_mixer_control.old_prof & (SOUND_MASK_VOLUME)) { + set_mixer_output_device(NULL, MIXER_OUT, OP_HANDSFREE, + 1); + } + if (audio_mixer_control.old_prof & (SOUND_MASK_SPEAKER)) { +#ifdef CONFIG_HEADSET_DETECT_ENABLE + /*This is a temporary workaround which should be removed later */ + set_mixer_output_device(NULL, MIXER_OUT, OP_MONO, 1); +#else + set_mixer_output_device(NULL, MIXER_OUT, OP_HEADSET, 1); +#endif + } + if (audio_mixer_control.old_prof & (SOUND_MASK_PCM)) { + set_mixer_output_device(NULL, MIXER_OUT, OP_LINEOUT, 1); + } + + } else { + headset_state = 1; + + pmic_audio_output_enable_phantom_ground(); + + audio_mixer_control.old_prof = + audio_mixer_control.output_device; + + if (audio_mixer_control.old_prof & (SOUND_MASK_PHONEOUT)) { + set_mixer_output_device(NULL, MIXER_OUT, OP_EARPIECE, + 0); + } + if (audio_mixer_control.old_prof & (SOUND_MASK_VOLUME)) { + set_mixer_output_device(NULL, MIXER_OUT, OP_HANDSFREE, + 0); + } + if (audio_mixer_control.old_prof & (SOUND_MASK_SPEAKER)) { + set_mixer_output_device(NULL, MIXER_OUT, OP_HEADSET, 0); + } + if (audio_mixer_control.old_prof & (SOUND_MASK_PCM)) { + set_mixer_output_device(NULL, MIXER_OUT, OP_LINEOUT, 0); + } + /*This is a temporary workaround which should be removed later */ + set_mixer_output_device(NULL, MIXER_OUT, OP_MONO, 1); + + } +} + +#endif +/*! + * This function configures audio multiplexer to support + * audio data routing in PMIC master mode. + * + * @param ssi SSI of the ARM to connect to the DAM. + */ +void configure_dam_pmic_master(int ssi) +{ + int source_port; + int target_port; + + if (ssi == SSI1) { + pr_debug("DAM: port 1 -> port 4\n"); + source_port = audio_data->src_port; + + target_port = port_4; + } else { + pr_debug("DAM: port 2 -> port 5\n"); + source_port = port_2; + target_port = port_5; + } + + dam_reset_register(source_port); + dam_reset_register(target_port); + + dam_select_mode(source_port, normal_mode); + dam_select_mode(target_port, internal_network_mode); + + dam_set_synchronous(source_port, true); + dam_set_synchronous(target_port, true); + + dam_select_RxD_source(source_port, target_port); + dam_select_RxD_source(target_port, source_port); + + dam_select_TxFS_direction(source_port, signal_out); + dam_select_TxFS_source(source_port, false, target_port); + + dam_select_TxClk_direction(source_port, signal_out); + dam_select_TxClk_source(source_port, false, target_port); + + dam_select_RxFS_direction(source_port, signal_out); + dam_select_RxFS_source(source_port, false, target_port); + + dam_select_RxClk_direction(source_port, signal_out); + dam_select_RxClk_source(source_port, false, target_port); + + dam_set_internal_network_mode_mask(target_port, 0xfc); + + writel(AUD_MUX_CONF, IO_ADDRESS(AUDMUX_BASE_ADDR) + 0x38); +} + +/*! + * This function configures the SSI in order to receive audio + * from PMIC (recording). Configuration of SSI consists mainly in + * setting the following: + * + * 1) SSI to use (SSI1 or SSI2) + * 2) SSI mode (normal or network. We use always network mode) + * 3) SSI STCCR register settings, which control the sample rate (BCL and + * FS clocks) + * 4) Watermarks for SSI FIFOs as well as timeslots to be used. + * 5) Enable SSI. + * + * @param substream pointer to the structure of the current stream. + */ +void configure_ssi_rx(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + audio_stream_t *s; + int ssi; + + chip = snd_pcm_substream_chip(substream); + s = &chip->s[substream->pstr->stream]; + ssi = s->ssi; + + pr_debug("configure_ssi_rx: SSI %d\n", ssi + 1); + + ssi_enable(ssi, false); + ssi_synchronous_mode(ssi, true); + ssi_network_mode(ssi, true); + + if (machine_is_mx27ads()) { + ssi_tx_clock_divide_by_two(ssi, 0); + ssi_tx_clock_prescaler(ssi, 0); + ssi_tx_frame_rate(ssi, 2); + } + /* OJO */ + ssi_tx_frame_rate(ssi, 1); + + ssi_tx_early_frame_sync(ssi, ssi_frame_sync_one_bit_before); + ssi_tx_frame_sync_length(ssi, ssi_frame_sync_one_bit); + ssi_tx_word_length(ssi, ssi_16_bits); + + ssi_rx_early_frame_sync(ssi, ssi_frame_sync_one_bit_before); + ssi_rx_frame_sync_length(ssi, ssi_frame_sync_one_bit); + ssi_rx_fifo_enable(ssi, ssi_fifo_0, true); + ssi_rx_bit0(ssi, true); + + ssi_rx_fifo_full_watermark(ssi, ssi_fifo_0, RX_WATERMARK); + + /* We never use the divider by 2 implemented in SSI */ + ssi_rx_clock_divide_by_two(ssi, 0); + + /* Set prescaler range (a fixed divide-by-eight prescaler + * in series with the variable prescaler) to 0 as we don't + * need it. + */ + ssi_rx_clock_prescaler(ssi, 0); + + /* Currently, only supported sample length is 16 bits */ + ssi_rx_word_length(ssi, ssi_16_bits); + + /* set direction of clocks ("externally" means that clocks come + * from PMIC to MCU) + */ + ssi_rx_frame_direction(ssi, ssi_tx_rx_externally); + ssi_rx_clock_direction(ssi, ssi_tx_rx_externally); + + /* Frame Rate Divider Control. + * In Normal mode, this ratio determines the word + * transfer rate. In Network mode, this ration sets + * the number of words per frame. + */ + ssi_tx_frame_rate(ssi, 4); + ssi_rx_frame_rate(ssi, 4); + + ssi_enable(ssi, true); +} + +/*! + * This function configures the SSI in order to + * send data to PMIC. Configuration of SSI consists + * mainly in setting the following: + * + * 1) SSI to use (SSI1 or SSI2) + * 2) SSI mode (normal for normal use e.g. playback, network for mixing) + * 3) SSI STCCR register settings, which control the sample rate (BCL and + * FS clocks) + * 4) Watermarks for SSI FIFOs as well as timeslots to be used. + * 5) Enable SSI. + * + * @param substream pointer to the structure of the current stream. + */ +void configure_ssi_tx(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + audio_stream_t *s; + struct snd_pcm_runtime *runtime; + int ssi; + int device, stream_id = -1; + device = substream->pcm->device; + if (device == 0) + stream_id = 0; + else if (device == 1) + stream_id = 2; + else + stream_id = 3; + + chip = snd_pcm_substream_chip(substream); + s = &chip->s[stream_id]; + runtime = substream->runtime; + ssi = s->ssi; + + pr_debug("configure_ssi_tx: SSI %d\n", ssi + 1); + + ssi_enable(ssi, false); + ssi_synchronous_mode(ssi, true); + if (runtime->channels == 1) { + if (stream_id == 2) { + ssi_network_mode(ssi, true); + } else { +#ifndef CONFIG_SND_MXC_PLAYBACK_MIXING + ssi_network_mode(ssi, false); +#endif + } + } else { + ssi_network_mode(ssi, true); + } + +#ifdef CONFIG_SND_MXC_PLAYBACK_MIXING + ssi_two_channel_mode(ssi, true); + ssi_tx_fifo_enable(ssi, ssi_fifo_1, true); + ssi_tx_fifo_empty_watermark(ssi, ssi_fifo_1, TX_WATERMARK); +#endif + + ssi_tx_early_frame_sync(ssi, ssi_frame_sync_one_bit_before); + ssi_tx_frame_sync_length(ssi, ssi_frame_sync_one_bit); + ssi_tx_fifo_enable(ssi, ssi_fifo_0, true); + ssi_tx_bit0(ssi, true); + + ssi_tx_fifo_empty_watermark(ssi, ssi_fifo_0, TX_WATERMARK); + + /* We never use the divider by 2 implemented in SSI */ + ssi_tx_clock_divide_by_two(ssi, 0); + + ssi_tx_clock_prescaler(ssi, 0); + + /*Currently, only supported sample length is 16 bits */ + ssi_tx_word_length(ssi, ssi_16_bits); + + /* clocks are being provided by PMIC */ + ssi_tx_frame_direction(ssi, ssi_tx_rx_externally); + ssi_tx_clock_direction(ssi, ssi_tx_rx_externally); + + if (runtime->channels == 1) { +#ifndef CONFIG_SND_MXC_PLAYBACK_MIXING + if (stream_id == 2) { + ssi_tx_frame_rate(ssi, 4); + } else { + ssi_tx_frame_rate(ssi, 1); + } +#else + if (stream_id == 2) { + ssi_tx_frame_rate(ssi, 2); + } +#endif + + } else { + ssi_tx_frame_rate(ssi, 2); + } + + ssi_enable(ssi, true); +} + +/*! + * This function normalizes speed given by the user + * if speed is not supported, the function will + * calculate the nearest one. + * + * @param speed speed requested by the user. + * + * @return The normalized speed. + */ +int adapt_speed(int speed) +{ + + /* speeds from 8k to 96k */ + if (speed >= (64000 + 96000) / 2) { + speed = 96000; + } else if (speed >= (48000 + 64000) / 2) { + speed = 64000; + } else if (speed >= (44100 + 48000) / 2) { + speed = 48000; + } else if (speed >= (32000 + 44100) / 2) { + speed = 44100; + } else if (speed >= (24000 + 32000) / 2) { + speed = 32000; + } else if (speed >= (22050 + 24000) / 2) { + speed = 24000; + } else if (speed >= (16000 + 22050) / 2) { + speed = 22050; + } else if (speed >= (12000 + 16000) / 2) { + speed = 16000; + } else if (speed >= (11025 + 12000) / 2) { + speed = 12000; + } else if (speed >= (8000 + 11025) / 2) { + speed = 11025; + } else { + speed = 8000; + } + return speed; +} + +/*! + * This function get values to be put in PMIC registers. + * This values represents the sample rate that PMIC + * should use for current playback or recording. + * + * @param substream pointer to the structure of the current stream. + */ +void normalize_speed_for_pmic(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + audio_stream_t *s; + pmic_audio_device_t *pmic_device; + struct snd_pcm_runtime *runtime; + int device, stream_id = -1; + device = substream->pcm->device; + if (device == 0) { + if ((audio_mixer_control.codec_capture_active == 1) + && (substream->stream == 1)) { + stream_id = 1; + } else + stream_id = 0; + } else { + stream_id = 2; + } + + chip = snd_pcm_substream_chip(substream); + s = &chip->s[stream_id]; + pmic_device = &s->pmic_audio_device; + runtime = substream->runtime; + + /* As the driver allows continuous sample rate, we must adapt the rate */ + runtime->rate = adapt_speed(runtime->rate); + + if (pmic_device->handle == audio_mixer_control.voice_codec_handle) { + switch (runtime->rate) { + case 8000: + pmic_device->sample_rate = VCODEC_RATE_8_KHZ; + break; + case 16000: + pmic_device->sample_rate = VCODEC_RATE_16_KHZ; + break; + default: + pmic_device->sample_rate = VCODEC_RATE_8_KHZ; + break; + } + + } else if (pmic_device->handle == audio_mixer_control.stdac_handle) { + switch (runtime->rate) { + case 8000: + pmic_device->sample_rate = STDAC_RATE_8_KHZ; + break; + + case 11025: + pmic_device->sample_rate = STDAC_RATE_11_025_KHZ; + break; + + case 12000: + pmic_device->sample_rate = STDAC_RATE_12_KHZ; + break; + + case 16000: + pmic_device->sample_rate = STDAC_RATE_16_KHZ; + break; + + case 22050: + pmic_device->sample_rate = STDAC_RATE_22_050_KHZ; + break; + + case 24000: + pmic_device->sample_rate = STDAC_RATE_24_KHZ; + break; + + case 32000: + pmic_device->sample_rate = STDAC_RATE_32_KHZ; + break; + + case 44100: + pmic_device->sample_rate = STDAC_RATE_44_1_KHZ; + break; + + case 48000: + pmic_device->sample_rate = STDAC_RATE_48_KHZ; + break; + + case 64000: + pmic_device->sample_rate = STDAC_RATE_64_KHZ; + break; + + case 96000: + pmic_device->sample_rate = STDAC_RATE_96_KHZ; + break; + + default: + pmic_device->sample_rate = STDAC_RATE_8_KHZ; + } + } + +} + +/*! + * This function configures number of channels for next audio operation + * (recording/playback) Number of channels define if sound is stereo + * or mono. + * + * @param substream pointer to the structure of the current stream. + * + */ +void set_pmic_channels(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + audio_stream_t *s; + struct snd_pcm_runtime *runtime; + int device = -1, stream_id = -1; + + chip = snd_pcm_substream_chip(substream); + device = substream->pcm->device; + + if (device == 0) { + if (substream->pstr->stream == 1) { + stream_id = 1; + } else { + stream_id = 0; + } + } else { + stream_id = 2; + } + s = &chip->s[stream_id]; + runtime = substream->runtime; + + if (runtime->channels == 2) { + ssi_tx_mask_time_slot(s->ssi, MASK_2_TS); + ssi_rx_mask_time_slot(s->ssi, MASK_1_TS_REC); + } else { + if (stream_id == 2) { +#ifdef CONFIG_MXC_PMIC_SC55112 + ssi_tx_mask_time_slot(s->ssi, MASK_1_TS_REC); +#else + + if (audio_mixer_control.mixing_active == 1) + ssi_tx_mask_time_slot(s->ssi, MASK_1_TS_MIX); + else + ssi_tx_mask_time_slot(s->ssi, MASK_1_TS); + +#endif + } else { + + ssi_tx_mask_time_slot(s->ssi, MASK_1_TS_STDAC); + } +#ifndef CONFIG_SND_MXC_PLAYBACK_MIXING + ssi_rx_mask_time_slot(s->ssi, MASK_1_TS_REC); +#endif + + } + +} + +/*! + * This function sets the input device in PMIC. It takes an + * ALSA value and modifies registers using pmic-specific values. + * + * @param handle Handle to the PMIC device opened + * @param val ALSA value. This value defines the input device that + * PMIC should activate to get audio signal (recording) + * @param enable Whether to enable or diable the input + */ +int set_mixer_input_device(PMIC_AUDIO_HANDLE handle, INPUT_DEVICES dev, + bool enable) +{ + + if (down_interruptible(&audio_mixer_control.sem)) + return -EINTR; + if (handle != NULL) { + if (audio_mixer_control.input_device & SOUND_MASK_PHONEIN) { + pmic_audio_vcodec_set_mic(handle, MIC1_LEFT, + MIC1_RIGHT_MIC_MONO); + pmic_audio_vcodec_enable_micbias(handle, MIC_BIAS1); + } else { + pmic_audio_vcodec_set_mic_on_off(handle, + MIC1_LEFT, + MIC1_RIGHT_MIC_MONO); + pmic_audio_vcodec_disable_micbias(handle, MIC_BIAS1); + } + if (audio_mixer_control.input_device & SOUND_MASK_MIC) { + pmic_audio_vcodec_set_mic(handle, NO_MIC, MIC2_AUX); + pmic_audio_vcodec_enable_micbias(handle, MIC_BIAS2); + } else { + pmic_audio_vcodec_set_mic_on_off(handle, NO_MIC, + MIC2_AUX); + pmic_audio_vcodec_disable_micbias(handle, MIC_BIAS2); + } + if (audio_mixer_control.input_device & SOUND_MASK_LINE) { + pmic_audio_vcodec_set_mic(handle, NO_MIC, TXIN_EXT); + } else { + pmic_audio_vcodec_set_mic_on_off(handle, NO_MIC, + TXIN_EXT); + } + up(&audio_mixer_control.sem); + return 0; + + } + switch (dev) { + case IP_HANDSET: + pr_debug("Input: SOUND_MASK_PHONEIN \n"); + if (handle == NULL) { + if (enable) { + if (audio_mixer_control.codec_capture_active) { + handle = + audio_mixer_control. + voice_codec_handle; + pmic_audio_vcodec_set_mic(handle, + MIC1_LEFT, + MIC1_RIGHT_MIC_MONO); + pmic_audio_vcodec_enable_micbias(handle, + MIC_BIAS1); + } + audio_mixer_control.input_device |= + SOUND_MASK_PHONEIN; + } else { + if (audio_mixer_control.codec_capture_active) { + handle = + audio_mixer_control. + voice_codec_handle; + pmic_audio_vcodec_set_mic_on_off(handle, + MIC1_LEFT, + MIC1_RIGHT_MIC_MONO); + pmic_audio_vcodec_disable_micbias + (handle, MIC_BIAS1); + } + audio_mixer_control.input_device &= + ~SOUND_MASK_PHONEIN; + } + } + break; + + case IP_HEADSET: + if (handle == NULL) { + if (enable) { + if (audio_mixer_control.codec_capture_active) { + handle = + audio_mixer_control. + voice_codec_handle; + pmic_audio_vcodec_set_mic(handle, + NO_MIC, + MIC2_AUX); + pmic_audio_vcodec_enable_micbias(handle, + MIC_BIAS2); + } + audio_mixer_control.input_device |= + SOUND_MASK_MIC; + } else { + if (audio_mixer_control.codec_capture_active) { + handle = + audio_mixer_control. + voice_codec_handle; + pmic_audio_vcodec_set_mic_on_off(handle, + NO_MIC, + MIC2_AUX); + pmic_audio_vcodec_disable_micbias + (handle, MIC_BIAS2); + } + audio_mixer_control.input_device &= + ~SOUND_MASK_MIC; + } + /* Enable Mic with MIC2_AUX */ + } + break; + + case IP_LINEIN: + if (handle == NULL) { + if (enable) { + if (audio_mixer_control.codec_capture_active) { + handle = + audio_mixer_control. + voice_codec_handle; + pmic_audio_vcodec_set_mic(handle, + NO_MIC, + TXIN_EXT); + } + audio_mixer_control.input_device |= + SOUND_MASK_LINE; + } else { + if (audio_mixer_control.codec_capture_active) { + handle = + audio_mixer_control. + voice_codec_handle; + pmic_audio_vcodec_set_mic_on_off(handle, + NO_MIC, + TXIN_EXT); + } + audio_mixer_control.input_device &= + ~SOUND_MASK_LINE; + } + } + break; + + default: + up(&audio_mixer_control.sem); + return -1; + break; + } + up(&audio_mixer_control.sem); + return 0; +} + +EXPORT_SYMBOL(set_mixer_input_device); + +int get_mixer_input_device() +{ + int val; + val = audio_mixer_control.input_device; + return val; +} + +EXPORT_SYMBOL(get_mixer_input_device); + +/*! + * This function sets the PMIC input device's gain. + * Note that the gain is the input volume + * + * @param handle Handle to the opened PMIC device + * @param val gain to be applied. This value can go + * from 0 (mute) to 100 (max gain) + */ +int set_mixer_input_gain(PMIC_AUDIO_HANDLE handle, int val) +{ + int leftdb, rightdb; + int left, right; + + left = (val & 0x00ff); + right = ((val & 0xff00) >> 8); + if (down_interruptible(&audio_mixer_control.sem)) + return -EINTR; + leftdb = (left * PMIC_INPUT_VOLUME_MAX) / INPUT_VOLUME_MAX; + rightdb = (right * PMIC_INPUT_VOLUME_MAX) / INPUT_VOLUME_MAX; + audio_mixer_control.input_volume = val; + if (audio_mixer_control.voice_codec_handle == handle) { + pmic_audio_vcodec_set_record_gain(handle, VOLTAGE_TO_VOLTAGE, + leftdb, VOLTAGE_TO_VOLTAGE, + rightdb); + } else if ((handle == NULL) + && (audio_mixer_control.codec_capture_active)) { + pmic_audio_vcodec_set_record_gain(audio_mixer_control. + voice_codec_handle, + VOLTAGE_TO_VOLTAGE, leftdb, + VOLTAGE_TO_VOLTAGE, rightdb); + } + up(&audio_mixer_control.sem); + return 0; +} + +EXPORT_SYMBOL(set_mixer_input_gain); + +int get_mixer_input_gain() +{ + int val; + val = audio_mixer_control.input_volume; + return val; +} + +EXPORT_SYMBOL(get_mixer_input_gain); + +/*! + * This function sets the PMIC output device's volume. + * + * @param handle Handle to the PMIC device opened + * @param volume ALSA value. This value defines the playback volume + * @param dev which output device gets affected by this volume + * + */ + +int set_mixer_output_volume(PMIC_AUDIO_HANDLE handle, int volume, + OUTPUT_DEVICES dev) +{ + int leftdb, rightdb; + int right, left; + + if (down_interruptible(&audio_mixer_control.sem)) + return -EINTR; + left = (volume & 0x00ff); + right = ((volume & 0xff00) >> 8); + + leftdb = (left * PMIC_OUTPUT_VOLUME_MAX) / OUTPUT_VOLUME_MAX; + rightdb = (right * PMIC_OUTPUT_VOLUME_MAX) / OUTPUT_VOLUME_MAX; + if (handle == NULL) { + /* Invoked by mixer */ + audio_mixer_control.master_volume_out = volume; + if (audio_mixer_control.codec_playback_active) + pmic_audio_output_set_pgaGain(audio_mixer_control. + voice_codec_handle, + rightdb); + if (audio_mixer_control.stdac_playback_active) + pmic_audio_output_set_pgaGain(audio_mixer_control. + stdac_handle, rightdb); + + } else { + /* change the required volume */ + audio_mixer_control.master_volume_out = volume; + pmic_audio_output_set_pgaGain(handle, rightdb); + } + up(&audio_mixer_control.sem); + return 0; +} + +EXPORT_SYMBOL(set_mixer_output_volume); + +int get_mixer_output_volume() +{ + int val; + val = audio_mixer_control.master_volume_out; + return val; +} + +EXPORT_SYMBOL(get_mixer_output_volume); + +/*! + * This function sets the PMIC output device's balance. + * + * @param bal Balance to be applied. This value can go + * from 0 (Left atten) to 100 (Right atten) + * 50 is both equal + */ +int set_mixer_output_balance(int bal) +{ + int channel = 0; + PMIC_AUDIO_OUTPUT_BALANCE_GAIN b_gain; + PMIC_AUDIO_HANDLE handle; + if (down_interruptible(&audio_mixer_control.sem)) + return -EINTR; + /* Convert ALSA value to PMIC value i.e. atten and channel value */ + if (bal < 0) + bal = 0; + if (bal > 100) + bal = 100; + if (bal < 50) { + channel = 1; + } else { + bal = 100 - bal; + channel = 0; + } + + b_gain = bal / 8; + + audio_mixer_control.mixer_balance = bal; + if (audio_mixer_control.codec_playback_active) { + handle = audio_mixer_control.voice_codec_handle; + /* Use codec's handle to set balance */ + } else if (audio_mixer_control.stdac_playback_active) { + handle = audio_mixer_control.stdac_handle; + /* Use STDac's handle to set balance */ + } else { + up(&audio_mixer_control.sem); + return 0; + } + if (channel == 0) + pmic_audio_output_set_balance(handle, BAL_GAIN_0DB, b_gain); + else + pmic_audio_output_set_balance(handle, b_gain, BAL_GAIN_0DB); + up(&audio_mixer_control.sem); + return 0; +} + +EXPORT_SYMBOL(set_mixer_output_balance); + +int get_mixer_output_balance() +{ + int val; + val = audio_mixer_control.mixer_balance; + return val; +} + +EXPORT_SYMBOL(get_mixer_output_balance); + +/*! + * This function sets the PMIC output device's mono adder config. + * + * @param mode Mono adder mode to be set + */ +int set_mixer_output_mono_adder(PMIC_AUDIO_MONO_ADDER_MODE mode) +{ + PMIC_AUDIO_HANDLE handle; + if (down_interruptible(&audio_mixer_control.sem)) + return -EINTR; + audio_mixer_control.mixer_mono_adder = mode; + if (audio_mixer_control.codec_playback_active) { + handle = audio_mixer_control.voice_codec_handle; + /* Use codec's handle to set balance */ + pmic_audio_output_enable_mono_adder(audio_mixer_control. + voice_codec_handle, mode); + } else if (audio_mixer_control.stdac_playback_active) { + handle = audio_mixer_control.stdac_handle; + pmic_audio_output_enable_mono_adder(audio_mixer_control. + stdac_handle, mode); + /* Use STDac's handle to set balance */ + } + up(&audio_mixer_control.sem); + return 0; +} + +EXPORT_SYMBOL(set_mixer_output_mono_adder); + +int get_mixer_output_mono_adder() +{ + int val; + val = audio_mixer_control.mixer_mono_adder; + return val; +} + +EXPORT_SYMBOL(get_mixer_output_mono_adder); + +/*! + * This function sets the output device(s) in PMIC. It takes an + * ALSA value and modifies registers using PMIC-specific values. + * + * @param handle handle to the device already opened + * @param src Source connected to o/p device + * @param dev Output device to be enabled + * @param enable Enable or disable the device + * + */ +int set_mixer_output_device(PMIC_AUDIO_HANDLE handle, OUTPUT_SOURCE src, + OUTPUT_DEVICES dev, bool enable) +{ + PMIC_AUDIO_OUTPUT_PORT port; + if (down_interruptible(&audio_mixer_control.sem)) + return -EINTR; + if (!((src == CODEC_DIR_OUT) || (src == MIXER_OUT))) { + up(&audio_mixer_control.sem); + return -1; + } + if (handle != (PMIC_AUDIO_HANDLE) NULL) { + /* Invoked by playback stream */ + if (audio_mixer_control.output_device & SOUND_MASK_PHONEOUT) { + audio_mixer_control.output_active[OP_EARPIECE] = 1; + pmic_audio_output_set_port(handle, MONO_SPEAKER); + } else { + audio_mixer_control.output_active[OP_EARPIECE] = 0; + pmic_audio_output_clear_port(handle, MONO_SPEAKER); + } + if (audio_mixer_control.output_device & SOUND_MASK_SPEAKER) { + audio_mixer_control.output_active[OP_HANDSFREE] = 1; + pmic_audio_output_set_port(handle, MONO_LOUDSPEAKER); + } else { + audio_mixer_control.output_active[OP_HANDSFREE] = 0; + pmic_audio_output_clear_port(handle, MONO_LOUDSPEAKER); + } + if (audio_mixer_control.output_device & SOUND_MASK_VOLUME) { + audio_mixer_control.output_active[OP_HEADSET] = 1; + if (dev != OP_MONO) { + pmic_audio_output_set_port(handle, + STEREO_HEADSET_LEFT | + STEREO_HEADSET_RIGHT); + } else { + pmic_audio_output_set_port(handle, + STEREO_HEADSET_LEFT); + /*This is a temporary workaround which should be removed later */ + } + + } else { + audio_mixer_control.output_active[OP_HEADSET] = 0; + pmic_audio_output_clear_port(handle, + STEREO_HEADSET_LEFT | + STEREO_HEADSET_RIGHT); + } + if (audio_mixer_control.output_device & SOUND_MASK_PCM) { + audio_mixer_control.output_active[OP_LINEOUT] = 1; + pmic_audio_output_set_port(handle, + STEREO_OUT_LEFT | + STEREO_OUT_RIGHT); + } else { + audio_mixer_control.output_active[OP_LINEOUT] = 0; + pmic_audio_output_clear_port(handle, + STEREO_OUT_LEFT | + STEREO_OUT_RIGHT); + } + } else { + switch (dev) { + case OP_EARPIECE: + if (enable) { + audio_mixer_control.output_device |= + SOUND_MASK_PHONEOUT; + audio_mixer_control.source_for_output[dev] = + src; + } else { + audio_mixer_control.output_device &= + ~SOUND_MASK_PHONEOUT; + } + port = MONO_SPEAKER; + break; + case OP_HANDSFREE: + if (enable) { + audio_mixer_control.output_device |= + SOUND_MASK_SPEAKER; + audio_mixer_control.source_for_output[dev] = + src; + } else { + audio_mixer_control.output_device &= + ~SOUND_MASK_SPEAKER; + } + port = MONO_LOUDSPEAKER; + break; + case OP_HEADSET: + if (enable) { + audio_mixer_control.output_device |= + SOUND_MASK_VOLUME; + audio_mixer_control.source_for_output[dev] = + src; + } else { + audio_mixer_control.output_device &= + ~SOUND_MASK_VOLUME; + } + port = STEREO_HEADSET_LEFT | STEREO_HEADSET_RIGHT; + break; + case OP_MONO: + /*This is a temporary workaround which should be removed later */ + if (enable) { + audio_mixer_control.output_device |= + SOUND_MASK_VOLUME; + audio_mixer_control.source_for_output[dev] = + src; + } else { + audio_mixer_control.output_device &= + ~SOUND_MASK_VOLUME; + } + port = STEREO_HEADSET_LEFT; + break; + case OP_LINEOUT: + if (enable) { + audio_mixer_control.output_device |= + SOUND_MASK_PCM; + audio_mixer_control.source_for_output[dev] = + src; + } else { + audio_mixer_control.output_device &= + ~SOUND_MASK_PCM; + } + port = STEREO_OUT_LEFT | STEREO_OUT_RIGHT; + break; + default: + up(&audio_mixer_control.sem); + return -1; + break; + } + /* Invoked by mixer .. little tricky to handle over here */ + if (audio_mixer_control.codec_playback_active) { + if (enable) { + audio_mixer_control.output_active[dev] = 1; + pmic_audio_output_set_port(audio_mixer_control. + voice_codec_handle, + port); + } else { + audio_mixer_control.output_active[dev] = 0; + pmic_audio_output_clear_port + (audio_mixer_control.voice_codec_handle, + port); + } + } + if (audio_mixer_control.stdac_playback_active) { + if (enable) { + audio_mixer_control.output_active[dev] = 1; + pmic_audio_output_set_port(audio_mixer_control. + stdac_handle, port); + } else { + audio_mixer_control.output_active[dev] = 0; + pmic_audio_output_clear_port + (audio_mixer_control.stdac_handle, port); + } + } + + } + up(&audio_mixer_control.sem); + return 0; + /* Set O/P device with handle and port */ + +} + +EXPORT_SYMBOL(set_mixer_output_device); + +int get_mixer_output_device() +{ + int val; + val = audio_mixer_control.output_device; + return val; +} + +EXPORT_SYMBOL(get_mixer_output_device); + +/*! + * This function configures the CODEC for playback/recording. + * + * main configured elements are: + * - audio path on PMIC + * - external clock to generate BC and FS clocks + * - PMIC mode (master or slave) + * - protocol + * - sample rate + * + * @param substream pointer to the structure of the current stream. + * @param stream_id index into the audio_stream array. + */ +void configure_codec(struct snd_pcm_substream *substream, int stream_id) +{ + mxc_pmic_audio_t *chip; + audio_stream_t *s; + pmic_audio_device_t *pmic; + PMIC_AUDIO_HANDLE handle; + int ssi_bus; + + chip = snd_pcm_substream_chip(substream); + s = &chip->s[stream_id]; + pmic = &s->pmic_audio_device; + handle = audio_mixer_control.voice_codec_handle; + + ssi_bus = (pmic->ssi == SSI1) ? AUDIO_DATA_BUS_1 : AUDIO_DATA_BUS_2; + + pmic_audio_vcodec_set_rxtx_timeslot(handle, USE_TS0); + pmic_audio_vcodec_enable_mixer(handle, USE_TS1, VCODEC_MIX_IN_0DB, + VCODEC_MIX_OUT_0DB); + pmic_audio_set_protocol(handle, ssi_bus, pmic->protocol, pmic->mode, + USE_4_TIMESLOTS); + + msleep(20); + pmic_audio_vcodec_set_clock(handle, pmic->pll, pmic->pll_rate, + pmic->sample_rate, NO_INVERT); + msleep(20); + pmic_audio_vcodec_set_config(handle, VCODEC_MASTER_CLOCK_OUTPUTS); + pmic_audio_digital_filter_reset(handle); + msleep(15); + if (stream_id == 2) { + pmic_audio_output_enable_mixer(handle); + set_mixer_output_device(handle, MIXER_OUT, OP_NODEV, 1); + set_mixer_output_volume(handle, + audio_mixer_control.master_volume_out, + OP_HEADSET); + } else { + set_mixer_input_device(handle, IP_NODEV, 1); + set_mixer_input_gain(handle, audio_mixer_control.input_volume); + } + pmic_audio_enable(handle); +} + +/*! + * This function configures the STEREODAC for playback/recording. + * + * main configured elements are: + * - audio path on PMIC + * - external clock to generate BC and FS clocks + * - PMIC mode (master or slave) + * - protocol + * - sample rate + * + * @param substream pointer to the structure of the current stream. + */ +void configure_stereodac(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + int stream_id; + audio_stream_t *s; + pmic_audio_device_t *pmic; + int ssi_bus; + PMIC_AUDIO_HANDLE handle; + struct snd_pcm_runtime *runtime; + + chip = snd_pcm_substream_chip(substream); + stream_id = substream->pstr->stream; + s = &chip->s[stream_id]; + pmic = &s->pmic_audio_device; + handle = pmic->handle; + runtime = substream->runtime; + + if (runtime->channels == 1) { + audio_mixer_control.mixer_mono_adder = MONO_ADD_LEFT_RIGHT; + } else { + audio_mixer_control.mixer_mono_adder = MONO_ADDER_OFF; + } + + ssi_bus = (pmic->ssi == SSI1) ? AUDIO_DATA_BUS_1 : AUDIO_DATA_BUS_2; + pmic_audio_stdac_set_rxtx_timeslot(handle, USE_TS0_TS1); + pmic_audio_stdac_enable_mixer(handle, USE_TS2_TS3, STDAC_NO_MIX, + STDAC_MIX_OUT_0DB); +#ifdef CONFIG_MXC_PMIC_SC55112 + pmic_audio_set_protocol(handle, ssi_bus, pmic->protocol, pmic->mode, + USE_4_TIMESLOTS); +#else + pmic_audio_set_protocol(handle, ssi_bus, pmic->protocol, pmic->mode, + USE_2_TIMESLOTS); +#endif + pmic_audio_stdac_set_clock(handle, pmic->pll, pmic->pll_rate, + pmic->sample_rate, NO_INVERT); + + pmic_audio_stdac_set_config(handle, STDAC_MASTER_CLOCK_OUTPUTS); + pmic_audio_output_enable_mixer(handle); + audio_mixer_control.stdac_out_to_mixer = 1; + pmic_audio_digital_filter_reset(handle); + msleep(10); + pmic_audio_output_enable_phantom_ground(); + set_mixer_output_volume(handle, audio_mixer_control.master_volume_out, + OP_HEADSET); + pmic_audio_output_enable_mono_adder(handle, + audio_mixer_control. + mixer_mono_adder); +#ifdef CONFIG_HEADSET_DETECT_ENABLE + set_mixer_output_device(handle, MIXER_OUT, OP_MONO, 1); +#else + set_mixer_output_device(handle, MIXER_OUT, OP_NODEV, 1); +#endif + pmic_audio_enable(handle); + +} + +/*! + * This function disables CODEC's amplifiers, volume and clock. + * @param handle Handle of voice codec + */ + +void disable_codec(PMIC_AUDIO_HANDLE handle) +{ + pmic_audio_disable(handle); + pmic_audio_vcodec_clear_config(handle, VCODEC_MASTER_CLOCK_OUTPUTS); +} + +/*! + * This function disables STEREODAC's amplifiers, volume and clock. + * @param handle Handle of STdac + * @param + */ + +void disable_stereodac(void) +{ + + audio_mixer_control.stdac_out_to_mixer = 0; +} + +/*! + * This function configures PMIC for recording. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +int configure_pmic_recording(struct snd_pcm_substream *substream) +{ + + configure_codec(substream, 1); + return 0; +} + +/*! + * This function configures PMIC for playing back. + * + * @param substream pointer to the structure of the current stream. + * @param stream_id Index into the audio_stream array . + * + * @return 0 on success, -1 otherwise. + */ + +int configure_pmic_playback(struct snd_pcm_substream *substream, int stream_id) +{ + if (stream_id == 0) { + configure_stereodac(substream); + } else if (stream_id == 2 || stream_id == 3) { + configure_codec(substream, stream_id); + } + return 0; +} + +/*! + * This function shutsdown the PMIC soundcard. + * Nothing to be done here + * + * @param mxc_audio pointer to the sound card structure. + * + * @return + */ +/* +static void mxc_pmic_audio_shutdown(mxc_pmic_audio_t * mxc_audio) +{ + +} +*/ + +/*! + * This function configures the DMA channel used to transfer + * audio from MCU to PMIC + * + * @param substream pointer to the structure of the current stream. + * @param callback pointer to function that will be + * called when a SDMA TX transfer finishes. + * + * @return 0 on success, -1 otherwise. + */ +static int +configure_write_channel(audio_stream_t *s, mxc_dma_callback_t callback, + int stream_id) +{ + int ret = -1; + int channel = -1; +#ifdef CONFIG_SND_MXC_PLAYBACK_MIXING + + int channel1 = -1; +#endif + + if (stream_id == 0) { + if (audio_data->ssi_num == 2) { + channel = + mxc_dma_request(MXC_DMA_SSI2_16BIT_TX0, + "ALSA TX DMA"); + ret = + mxc_dma_callback_set(channel, + (mxc_dma_callback_t) callback, + (void *)s); + if (ret != 0) { + mxc_dma_free(channel); + return -1; + } + s->dma_wchannel = channel; + + } else { + channel = + mxc_dma_request(MXC_DMA_SSI1_16BIT_TX0, + "ALSA TX DMA"); + ret = + mxc_dma_callback_set(channel, + (mxc_dma_callback_t) callback, + (void *)s); + if (ret != 0) { + mxc_dma_free(channel); + return -1; + } + s->dma_wchannel = channel; + } + + } + if (stream_id == 3) { + channel = + mxc_dma_request(MXC_DMA_SSI1_16BIT_TX0, "ALSA TX DMA"); + if (channel < 0) { + pr_debug("error requesting a write dma channel\n"); + return -1; + } + ret = + mxc_dma_callback_set(channel, (mxc_dma_callback_t) callback, + (void *)s); + if (ret != 0) { + mxc_dma_free(channel); + + return -1; + } + s->dma_wchannel = channel; + } +#ifdef CONFIG_SND_MXC_PLAYBACK_MIXING + else if (stream_id == 2) { + channel1 = + mxc_dma_request(MXC_DMA_SSI1_16BIT_TX1, "ALSA TX DMA"); + ret = + mxc_dma_callback_set(channel1, + (mxc_dma_callback_t) callback, + (void *)s); + if (ret != 0) { + mxc_dma_free(channel1); + return -1; + } + s->dma_wchannel = channel1; + } +#else + + if (stream_id == 2) { + channel = + mxc_dma_request(MXC_DMA_SSI1_16BIT_TX0, "ALSA TX DMA"); + ret = + mxc_dma_callback_set(channel, (mxc_dma_callback_t) callback, + (void *)s); + if (ret != 0) { + mxc_dma_free(channel); + return -1; + } + s->dma_wchannel = channel; + } +#endif + /*if (channel < 0) { + pr_debug("error requesting a write dma channel\n"); + return -1; + } */ + + return 0; +} + +/*! + * This function configures the DMA channel used to transfer + * audio from PMIC to MCU + * + * @param substream pointer to the structure of the current stream. + * @param callback pointer to function that will be + * called when a SDMA RX transfer finishes. + * + * @return 0 on success, -1 otherwise. + */ +static int configure_read_channel(audio_stream_t *s, + mxc_dma_callback_t callback) +{ + int ret = -1; + int channel = -1; + + channel = mxc_dma_request(MXC_DMA_SSI1_16BIT_RX0, "ALSA RX DMA"); + if (channel < 0) { + pr_debug("error requesting a read dma channel\n"); + return -1; + } + + ret = + mxc_dma_callback_set(channel, (mxc_dma_callback_t) callback, + (void *)s); + if (ret != 0) { + mxc_dma_free(channel); + return -1; + } + s->dma_wchannel = channel; + + return 0; +} + +/*! + * This function frees the stream structure + * + * @param s pointer to the structure of the current stream. + */ +static void audio_dma_free(audio_stream_t *s) +{ + /* + * There is nothing to be done here since the dma channel has been + * freed either in the callback or in the stop method + */ + +} + +/*! + * This function gets the dma pointer position during record. + * Our DMA implementation does not allow to retrieve this position + * when a transfert is active, so, it answers the middle of + * the current period beeing transfered + * + * @param s pointer to the structure of the current stream. + * + */ +static u_int audio_get_capture_dma_pos(audio_stream_t *s) +{ + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int offset; + + substream = s->stream; + runtime = substream->runtime; + offset = 0; + + /* tx_spin value is used here to check if a transfert is active */ + if (s->tx_spin) { + offset = (runtime->period_size * (s->periods)) + 0; + if (offset >= runtime->buffer_size) + offset = 0; + pr_debug("MXC: audio_get_dma_pos offset %d\n", offset); + } else { + offset = (runtime->period_size * (s->periods)); + if (offset >= runtime->buffer_size) + offset = 0; + pr_debug("MXC: audio_get_dma_pos BIS offset %d\n", offset); + } + + return offset; +} + +/*! + * This function gets the dma pointer position during playback. + * Our DMA implementation does not allow to retrieve this position + * when a transfert is active, so, it answers the middle of + * the current period beeing transfered + * + * @param s pointer to the structure of the current stream. + * + */ +static u_int audio_get_playback_dma_pos(audio_stream_t *s) +{ + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int offset; + + substream = s->stream; + runtime = substream->runtime; + offset = 0; + + /* tx_spin value is used here to check if a transfert is active */ + if (s->tx_spin) { + offset = (runtime->period_size * (s->periods)) + 0; + if (offset >= runtime->buffer_size) + offset = 0; + pr_debug("MXC: audio_get_dma_pos offset %d\n", offset); + } else { + offset = (runtime->period_size * (s->periods)); + if (offset >= runtime->buffer_size) + offset = 0; + pr_debug("MXC: audio_get_dma_pos BIS offset %d\n", offset); + } + + return offset; +} + +/*! + * This function is called whenever a new audio block needs to be + * transferred to PMIC. The function receives the address and the size + * of the new block and start a new DMA transfer. + * + * @param substream pointer to the structure of the current stream. + * + */ +static void audio_playback_dma(audio_stream_t *s) +{ + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int dma_size = 0; + unsigned int offset; + int ret = 0; + mxc_dma_requestbuf_t dma_request; +#ifdef CONFIG_SND_MXC_PLAYBACK_MIXING + unsigned int dma_size_mix = 0, offset_mix; + mxc_dma_requestbuf_t dma_request_mix; + int ret1 = 0; +#endif + int device; + int stream_id; + + substream = s->stream; + runtime = substream->runtime; + device = substream->pcm->device; + if (device == 0) { + stream_id = 0; + } else if (device == 1) { + stream_id = 2; + } else { + stream_id = 3; + } + + pr_debug("\nDMA direction %d\(0 is playback 1 is capture)\n", + s->stream_id); + +#ifndef CONFIG_SND_MXC_PLAYBACK_MIXING + memset(&dma_request, 0, sizeof(mxc_dma_requestbuf_t)); + +#else + if (stream_id == 2) { + memset(&dma_request, 0, sizeof(mxc_dma_requestbuf_t)); + } else if (stream_id == 3) { + memset(&dma_request_mix, 0, sizeof(mxc_dma_requestbuf_t)); + } +#endif + if (s->active) { + if (ssi_get_status(s->ssi) & (ssi_transmitter_underrun_0)) { + ssi_enable(s->ssi, false); + ssi_transmit_enable(s->ssi, false); + ssi_enable(s->ssi, true); + } +#ifndef CONFIG_SND_MXC_PLAYBACK_MIXING + + dma_size = frames_to_bytes(runtime, runtime->period_size); + pr_debug("s->period (%x) runtime->periods (%d)\n", + s->period, runtime->periods); + pr_debug("runtime->period_size (%d) dma_size (%d)\n", + (unsigned int)runtime->period_size, + runtime->dma_bytes); + + offset = dma_size * s->period; + if (snd_BUG_ON(dma_size > DMA_BUF_SIZE)) + return; +#ifdef CONFIG_SND_MXC_PMIC_IRAM + + if (g_audio_iram_en && stream_id == 0) { + dma_request.src_addr = ADMA_BASE_PADDR + offset; + } else +#endif /*CONFIG_SND_MXC_PMIC_IRAM */ + { + + dma_request.src_addr = + (dma_addr_t) (dma_map_single + (NULL, runtime->dma_area + offset, + dma_size, DMA_TO_DEVICE)); + } + if (stream_id == 0) { + dma_request.dst_addr = + (dma_addr_t) get_ssi_fifo_addr(s->ssi, 1); + } else if (stream_id == 2) { + dma_request.dst_addr = + (dma_addr_t) get_ssi_fifo_addr(s->ssi, 1); + } + dma_request.num_of_bytes = dma_size; + pr_debug("MXC: Start DMA offset (%d) size (%d)\n", + offset, runtime->dma_bytes); + + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_WRITE); + ret = mxc_dma_enable(s->dma_wchannel); + ssi_transmit_enable(s->ssi, true); + s->tx_spin = 1; /* FGA little trick to retrieve DMA pos */ + + if (ret) { + pr_debug("audio_process_dma: cannot queue DMA buffer\ + (%i)\n", ret); + return; + } + s->period++; + s->period %= runtime->periods; +#else + + if (stream_id == 2) { + dma_size = + frames_to_bytes(runtime, runtime->period_size); + pr_debug("s->period (%x) runtime->periods (%d)\n", + s->period, runtime->periods); + pr_debug("runtime->period_size (%d) dma_size (%d)\n", + (unsigned int)runtime->period_size, + runtime->dma_bytes); + + offset = dma_size * s->period; + if (snd_BUG_ON(dma_size > DMA_BUF_SIZE)) + return; + + dma_request.src_addr = + (dma_addr_t) (dma_map_single + (NULL, runtime->dma_area + offset, + dma_size, DMA_TO_DEVICE)); + dma_request.dst_addr = + (dma_addr_t) get_ssi_fifo_addr(s->ssi, 1); + dma_request.num_of_bytes = dma_size; + pr_debug("MXC: Start DMA offset (%d) size (%d)\n", + offset, runtime->dma_bytes); + + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_WRITE); + ret = mxc_dma_enable(s->dma_wchannel); + ssi_transmit_enable(s->ssi, true); + s->tx_spin = 1; /* FGA little trick to retrieve DMA pos */ + + if (ret) { + pr_debug("audio_process_dma: cannot queue DMA buffer\ + (%i)\n", + ret); + return; + } + s->period++; + s->period %= runtime->periods; + + } else if (stream_id == 3) { + + dma_size_mix = + frames_to_bytes(runtime, runtime->period_size); + pr_debug("s->period (%x) runtime->periods (%d)\n", + s->period, runtime->periods); + pr_debug("runtime->period_size (%d) dma_size (%d)\n", + (unsigned int)runtime->period_size, + runtime->dma_bytes); + + offset_mix = dma_size_mix * s->period; + if (snd_BUG_ON(dma_size_mix > DMA_BUF_SIZE)) + return; + dma_request_mix.src_addr = + (dma_addr_t) (dma_map_single + (NULL, runtime->dma_area + offset_mix, + dma_size_mix, DMA_TO_DEVICE)); + dma_request_mix.dst_addr = + (dma_addr_t) get_ssi_fifo_addr(s->ssi, 1); + dma_request_mix.num_of_bytes = dma_size_mix; + + pr_debug("MXC: Start DMA offset (%d) size (%d)\n", + offset_mix, runtime->dma_bytes); + + mxc_dma_config(s->dma_wchannel, &dma_request_mix, 1, + MXC_DMA_MODE_WRITE); + ret1 = mxc_dma_enable(s->dma_wchannel); + ssi_transmit_enable(s->ssi, true); + s->tx_spin = 1; /* FGA little trick to retrieve DMA pos */ + + if (ret1) { + pr_debug("audio_process_dma: cannot queue DMA buffer\ + (%i)\n", + ret1); + return; + } + s->period++; + s->period %= runtime->periods; + + } +#endif +#ifdef MXC_SOUND_PLAYBACK_CHAIN_DMA_EN + + if ((s->period > s->periods) && ((s->period - s->periods) > 1)) { + pr_debug + ("audio playback chain dma: already double buffered\n"); + return; + } + + if ((s->period < s->periods) + && ((s->period + runtime->periods - s->periods) > 1)) { + pr_debug + ("audio playback chain dma: already double buffered\n"); + return; + } + + if (s->period == s->periods) { + pr_debug + ("audio playback chain dma: s->period == s->periods\n"); + return; + } + + if (snd_pcm_playback_hw_avail(runtime) < + 2 * runtime->period_size) { + pr_debug + ("audio playback chain dma: available data is not enough\n"); + return; + } + + pr_debug + ("audio playback chain dma:to set up the 2nd dma buffer\n"); + +#ifndef CONFIG_SND_MXC_PLAYBACK_MIXING + offset = dma_size * s->period; +#ifdef CONFIG_SND_MXC_PMIC_IRAM + if (g_audio_iram_en && stream_id == 0) { + dma_request.src_addr = ADMA_BASE_PADDR + offset; + } else +#endif /*CONFIG_SND_MXC_PMIC_IRAM */ + { + + dma_request.src_addr = + (dma_addr_t) (dma_map_single + (NULL, runtime->dma_area + offset, + dma_size, DMA_TO_DEVICE)); + } + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_WRITE); +#else + if (stream_id == 3) { + offset_mix = dma_size_mix * s->period; + dma_request.src_addr = + (dma_addr_t) (dma_map_single + (NULL, + runtime->dma_area + offset_mix, + dma_size, DMA_TO_DEVICE)); + + mxc_dma_config(s->dma_wchannel, &dma_request_mix, 1, + MXC_DMA_MODE_WRITE); + } else { + offset = dma_size * s->period; + dma_request.src_addr = + (dma_addr_t) (dma_map_single + (NULL, + runtime->dma_area + offset, + dma_size, DMA_TO_DEVICE)); + + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_WRITE); + } + +#endif + ret = mxc_dma_enable(s->dma_wchannel); + + s->period++; + s->period %= runtime->periods; +#endif /* MXC_SOUND_PLAYBACK_CHAIN_DMA_EN */ + } +} + +/*! + * This function is called whenever a new audio block needs to be + * transferred from PMIC. The function receives the address and the size + * of the block that will store the audio samples and start a new DMA transfer. + * + * @param substream pointer to the structure of the current stream. + * + */ +static void audio_capture_dma(audio_stream_t *s) +{ + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int dma_size; + unsigned int offset; + int ret = 0; + mxc_dma_requestbuf_t dma_request; + + substream = s->stream; + runtime = substream->runtime; + + pr_debug("\nDMA direction %d\ + (0 is playback 1 is capture)\n", s->stream_id); + + memset(&dma_request, 0, sizeof(mxc_dma_requestbuf_t)); + + if (s->active) { + dma_size = frames_to_bytes(runtime, runtime->period_size); + pr_debug("s->period (%x) runtime->periods (%d)\n", + s->period, runtime->periods); + pr_debug("runtime->period_size (%d) dma_size (%d)\n", + (unsigned int)runtime->period_size, + runtime->dma_bytes); + + offset = dma_size * s->period; + snd_BUG_ON(dma_size > DMA_BUF_SIZE); + + dma_request.dst_addr = (dma_addr_t) (dma_map_single(NULL, + runtime-> + dma_area + + offset, + dma_size, + DMA_FROM_DEVICE)); + dma_request.src_addr = + (dma_addr_t) get_ssi_fifo_addr(s->ssi, 0); + dma_request.num_of_bytes = dma_size; + + pr_debug("MXC: Start DMA offset (%d) size (%d)\n", offset, + runtime->dma_bytes); + + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_READ); + ret = mxc_dma_enable(s->dma_wchannel); + + s->tx_spin = 1; /* FGA little trick to retrieve DMA pos */ + + if (ret) { + pr_debug("audio_process_dma: cannot queue DMA buffer\ + (%i)\n", ret); + return; + } + s->period++; + s->period %= runtime->periods; + +#ifdef MXC_SOUND_CAPTURE_CHAIN_DMA_EN + if ((s->period > s->periods) && ((s->period - s->periods) > 1)) { + pr_debug + ("audio capture chain dma: already double buffered\n"); + return; + } + + if ((s->period < s->periods) + && ((s->period + runtime->periods - s->periods) > 1)) { + pr_debug + ("audio capture chain dma: already double buffered\n"); + return; + } + + if (s->period == s->periods) { + pr_debug + ("audio capture chain dma: s->period == s->periods\n"); + return; + } + + if (snd_pcm_capture_hw_avail(runtime) < + 2 * runtime->period_size) { + pr_debug + ("audio capture chain dma: available data is not enough\n"); + return; + } + + pr_debug + ("audio capture chain dma:to set up the 2nd dma buffer\n"); + offset = dma_size * s->period; + dma_request.dst_addr = (dma_addr_t) (dma_map_single(NULL, + runtime-> + dma_area + + offset, + dma_size, + DMA_FROM_DEVICE)); + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_READ); + ret = mxc_dma_enable(s->dma_wchannel); + + s->period++; + s->period %= runtime->periods; +#endif /* MXC_SOUND_CAPTURE_CHAIN_DMA_EN */ + } +} + +/*! + * This is a callback which will be called + * when a TX transfer finishes. The call occurs + * in interrupt context. + * + * @param dat pointer to the structure of the current stream. + * + */ +static void audio_playback_dma_callback(void *data, int error, + unsigned int count) +{ + audio_stream_t *s; + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int dma_size; + unsigned int previous_period; + unsigned int offset; + + s = data; + substream = s->stream; + runtime = substream->runtime; + previous_period = s->periods; + dma_size = frames_to_bytes(runtime, runtime->period_size); + offset = dma_size * previous_period; + + s->tx_spin = 0; + s->periods++; + s->periods %= runtime->periods; + + /* + * Give back to the CPU the access to the non cached memory + */ + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_TO_DEVICE); + + /* + * If we are getting a callback for an active stream then we inform + * the PCM middle layer we've finished a period + */ + if (s->active) + snd_pcm_period_elapsed(s->stream); + spin_lock(&s->dma_lock); + + /* + * Trig next DMA transfer + */ + audio_playback_dma(s); + + spin_unlock(&s->dma_lock); + +} + +/*! + * This is a callback which will be called + * when a RX transfer finishes. The call occurs + * in interrupt context. + * + * @param substream pointer to the structure of the current stream. + * + */ +static void audio_capture_dma_callback(void *data, int error, + unsigned int count) +{ + audio_stream_t *s; + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int dma_size; + unsigned int previous_period; + unsigned int offset; + + s = data; + substream = s->stream; + runtime = substream->runtime; + previous_period = s->periods; + dma_size = frames_to_bytes(runtime, runtime->period_size); + offset = dma_size * previous_period; + + s->tx_spin = 0; + s->periods++; + s->periods %= runtime->periods; + + /* + * Give back to the CPU the access to the non cached memory + */ + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_FROM_DEVICE); + + /* + * If we are getting a callback for an active stream then we inform + * the PCM middle layer we've finished a period + */ + if (s->active) + snd_pcm_period_elapsed(s->stream); + + spin_lock(&s->dma_lock); + + /* + * Trig next DMA transfer + */ + audio_capture_dma(s); + + spin_unlock(&s->dma_lock); + +} + +/*! + * This function is a dispatcher of command to be executed + * by the driver for playback. + * + * @param substream pointer to the structure of the current stream. + * @param cmd command to be executed + * + * @return 0 on success, -1 otherwise. + */ +static int +snd_mxc_audio_playback_trigger(struct snd_pcm_substream *substream, int cmd) +{ + mxc_pmic_audio_t *chip; + int stream_id; + audio_stream_t *s; + int err; + int device; + device = substream->pcm->device; + if (device == 0) { + stream_id = 0; + } else if (device == 1) { + stream_id = 2; + } else { + stream_id = 3; + } + + chip = snd_pcm_substream_chip(substream); + + s = &chip->s[stream_id]; + err = 0; + + /* note local interrupts are already disabled in the midlevel code */ + spin_lock(&s->dma_lock); + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + s->tx_spin = 0; + s->active = 1; + audio_playback_dma(s); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + s->active = 0; + break; + default: + err = -EINVAL; + break; + } + spin_unlock(&s->dma_lock); + return err; +} + +/*! + * This function is a dispatcher of command to be executed + * by the driver for capture. + * + * @param substream pointer to the structure of the current stream. + * @param cmd command to be executed + * + * @return 0 on success, -1 otherwise. + */ +static int +snd_mxc_audio_capture_trigger(struct snd_pcm_substream *substream, int cmd) +{ + mxc_pmic_audio_t *chip; + int stream_id; + audio_stream_t *s; + int err; + + chip = snd_pcm_substream_chip(substream); + stream_id = substream->pstr->stream; + s = &chip->s[stream_id]; + err = 0; + + /* note local interrupts are already disabled in the midlevel code */ + spin_lock(&s->dma_lock); + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + s->tx_spin = 0; + s->active = 1; + audio_capture_dma(s); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + s->active = 0; + break; + default: + err = -EINVAL; + break; + } + spin_unlock(&s->dma_lock); + return err; +} + +/*! + * This function configures the hardware to allow audio + * playback operations. It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_audio_playback_prepare(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + audio_stream_t *s; + int ssi; + int device = -1, stream_id = -1; + + device = substream->pcm->device; + if (device == 0) + stream_id = 0; + else if (device == 1) + stream_id = 2; + else if (device == 2) + stream_id = 3; + + chip = snd_pcm_substream_chip(substream); + s = &chip->s[stream_id]; + ssi = s->ssi; + + normalize_speed_for_pmic(substream); + + configure_dam_pmic_master(ssi); + + configure_ssi_tx(substream); + + ssi_interrupt_enable(ssi, ssi_tx_dma_interrupt_enable); + ssi_interrupt_enable(ssi, ssi_tx_interrupt_enable); + + if (configure_pmic_playback(substream, stream_id) == -1) + pr_debug(KERN_ERR "MXC: PMIC Playback Config FAILED\n"); + ssi_interrupt_enable(ssi, ssi_tx_fifo_0_empty); + ssi_interrupt_enable(ssi, ssi_tx_fifo_1_empty); + /* + ssi_transmit_enable(ssi, true); + */ + msleep(20); + set_pmic_channels(substream); + s->period = 0; + s->periods = 0; + + msleep(100); + + return 0; +} + +/*! + * This function gets the current capture pointer position. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + */ +static +snd_pcm_uframes_t snd_mxc_audio_capture_pointer(struct snd_pcm_substream + *substream) +{ + mxc_pmic_audio_t *chip; + + chip = snd_pcm_substream_chip(substream); + return audio_get_capture_dma_pos(&chip->s[substream->pstr->stream]); +} + +/*! + * This function gets the current playback pointer position. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + */ +static snd_pcm_uframes_t +snd_mxc_audio_playback_pointer(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + int device; + int stream_id; + device = substream->pcm->device; + if (device == 0) + stream_id = 0; + else if (device == 1) + stream_id = 2; + else + stream_id = 3; + chip = snd_pcm_substream_chip(substream); + return audio_get_playback_dma_pos(&chip->s[stream_id]); +} + +/*! + * This structure reprensents the capabilities of the driver + * in capture mode. + * It is used by ALSA framework. + */ +static struct snd_pcm_hardware snd_mxc_pmic_capture = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000), + .rate_min = 8000, + .rate_max = 16000, + .channels_min = 1, + .channels_max = 1, + .buffer_bytes_max = MAX_BUFFER_SIZE, + .period_bytes_min = MIN_PERIOD_SIZE, + .period_bytes_max = DMA_BUF_SIZE, + .periods_min = MIN_PERIOD, + .periods_max = MAX_PERIOD, + .fifo_size = 0, + +}; + +/*! + * This structure reprensents the capabilities of the driver + * in playback mode for ST-Dac. + * It is used by ALSA framework. + */ +static struct snd_pcm_hardware snd_mxc_pmic_playback_stereo = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_CONTINUOUS), + .rate_min = 8000, + .rate_max = 96000, + .channels_min = 1, + .channels_max = 2, + .buffer_bytes_max = MAX_BUFFER_SIZE, + .period_bytes_min = MIN_PERIOD_SIZE, + .period_bytes_max = DMA_BUF_SIZE, + .periods_min = MIN_PERIOD, + .periods_max = MAX_PERIOD, + .fifo_size = 0, + +}; + +/*! + * This structure reprensents the capabilities of the driver + * in playback mode for Voice-codec. + * It is used by ALSA framework. + */ +static struct snd_pcm_hardware snd_mxc_pmic_playback_mono = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000), + .rate_min = 8000, + .rate_max = 16000, + .channels_min = 1, + .channels_max = 1, + .buffer_bytes_max = MAX_BUFFER_SIZE, + .period_bytes_min = MIN_PERIOD_SIZE, + .period_bytes_max = DMA_BUF_SIZE, + .periods_min = MIN_PERIOD, + .periods_max = MAX_PERIOD, + .fifo_size = 0, + +}; + +/*! + * This function opens a PMIC audio device in playback mode + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_card_mxc_audio_playback_open(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + struct snd_pcm_runtime *runtime; + int stream_id = -1; + int err; + audio_stream_t *s; + PMIC_AUDIO_HANDLE temp_handle; + int device = -1; + + device = substream->pcm->device; + + chip = snd_pcm_substream_chip(substream); + runtime = substream->runtime; + if (device == 0) + stream_id = 0; + else if (device == 1) + stream_id = 2; + else if (device == 2) { + stream_id = 3; + } + + s = &chip->s[stream_id]; + err = -1; + + if (stream_id == 0) { + if ((audio_data->ssi_num == 1) + && (audio_mixer_control.codec_playback_active + || audio_mixer_control.codec_capture_active)) { + return -EBUSY; + } + + if (PMIC_SUCCESS == pmic_audio_open(&temp_handle, STEREO_DAC)) { + audio_mixer_control.stdac_handle = temp_handle; + audio_mixer_control.stdac_playback_active = 1; + chip->s[stream_id].pmic_audio_device.handle = + temp_handle; + } else { + return -EBUSY; + } + } else if (stream_id == 2) { + if ((audio_data->ssi_num == 1) + && (audio_mixer_control.stdac_playback_active)) { + return -EBUSY; + } + + audio_mixer_control.codec_playback_active = 1; + if (PMIC_SUCCESS == pmic_audio_open(&temp_handle, VOICE_CODEC)) { + audio_mixer_control.voice_codec_handle = temp_handle; + chip->s[stream_id].pmic_audio_device.handle = + temp_handle; + } else { + if (audio_mixer_control.codec_capture_active) { + temp_handle = + audio_mixer_control.voice_codec_handle; + } else { + return -EBUSY; + } + } + + } else if (stream_id == 3) { + audio_mixer_control.mixing_active = 1; + + } + + pmic_audio_antipop_enable(ANTI_POP_RAMP_SLOW); + msleep(250); + + chip->s[stream_id].stream = substream; + + if (stream_id == 0) + runtime->hw = snd_mxc_pmic_playback_stereo; + else if (stream_id == 2) + runtime->hw = snd_mxc_pmic_playback_mono; + + else if (stream_id == 3) { + runtime->hw = snd_mxc_pmic_playback_mono; + + err = snd_pcm_hw_constraint_list(runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &hw_playback_rates_mono); + if (err < 0) + return err; + } +#ifdef CONFIG_SND_MXC_PMIC_IRAM + if (g_audio_iram_en && stream_id == 0) { + runtime->hw.buffer_bytes_max = MAX_IRAM_SIZE; + runtime->hw.period_bytes_max = DMA_IRAM_SIZE; + } +#endif /*CONFIG_SND_MXC_PMIC_IRAM */ + + err = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS)); + if (err < 0) + goto exit_err; + if (stream_id == 0) { + err = snd_pcm_hw_constraint_list(runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &hw_playback_rates_stereo); + if (err < 0) + goto exit_err; + + } else if (stream_id == 2) { + err = snd_pcm_hw_constraint_list(runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &hw_playback_rates_mono); + if (err < 0) + goto exit_err; + } + msleep(10); + + /* setup DMA controller for playback */ + err = configure_write_channel(&mxc_audio->s[stream_id], + audio_playback_dma_callback, + stream_id); + if (err < 0) + goto exit_err; + + /* enable ssi clock */ + clk_enable(audio_data->ssi_clk[s->ssi]); + + return 0; + exit_err: +#ifdef CONFIG_SND_MXC_PMIC_IRAM + if (stream_id == 0) + mxc_snd_pcm_iram_put(); +#endif /*CONFIG_SND_MXC_PMIC_IRAM */ + return err; + +} + +/*! + * This function closes an PMIC audio device for playback. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_card_mxc_audio_playback_close(struct snd_pcm_substream + *substream) +{ + mxc_pmic_audio_t *chip; + audio_stream_t *s; + PMIC_AUDIO_HANDLE handle; + int ssi; + int device, stream_id = -1; + handle = (PMIC_AUDIO_HANDLE) NULL; + device = substream->pcm->device; + if (device == 0) { + stream_id = 0; + } else if (device == 1) { + stream_id = 2; + } else + stream_id = 3; + + chip = snd_pcm_substream_chip(substream); + s = &chip->s[stream_id]; + ssi = s->ssi; + + if (audio_mixer_control.mixing_active == 1) { + goto End; + + } else { + + if (stream_id == 0) { + disable_stereodac(); + audio_mixer_control.stdac_playback_active = 0; + handle = audio_mixer_control.stdac_handle; + audio_mixer_control.stdac_handle = NULL; + chip->s[stream_id].pmic_audio_device.handle = NULL; + } else if ((stream_id == 2) || (stream_id == 3)) { + + audio_mixer_control.codec_playback_active = 0; + handle = audio_mixer_control.voice_codec_handle; + disable_codec(handle); + audio_mixer_control.voice_codec_handle = NULL; + chip->s[stream_id].pmic_audio_device.handle = NULL; + } + + } + pmic_audio_close(handle); + + ssi_transmit_enable(ssi, false); + ssi_interrupt_disable(ssi, ssi_tx_dma_interrupt_enable); + ssi_tx_fifo_enable(ssi, ssi_fifo_0, false); + ssi_enable(ssi, false); + mxc_dma_free((mxc_audio->s[stream_id]).dma_wchannel); + + chip->s[stream_id].stream = NULL; + End: + audio_mixer_control.mixing_active = 0; +#ifdef CONFIG_SND_MXC_PMIC_IRAM + if (stream_id == 0) + mxc_snd_pcm_iram_put(); +#endif /*CONFIG_SND_MXC_PMIC_IRAM */ + /* disable ssi clock */ + clk_disable(audio_data->ssi_clk[ssi]); + + return 0; +} + +/*! + * This function closes a PMIC audio device for capture. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_card_mxc_audio_capture_close(struct snd_pcm_substream *substream) +{ + PMIC_AUDIO_HANDLE handle; + mxc_pmic_audio_t *chip; + audio_stream_t *s; + int ssi; + + chip = snd_pcm_substream_chip(substream); + s = &chip->s[substream->pstr->stream]; + ssi = s->ssi; + + audio_mixer_control.codec_capture_active = 0; + handle = audio_mixer_control.voice_codec_handle; + disable_codec(handle); + audio_mixer_control.voice_codec_handle = NULL; + chip->s[SNDRV_PCM_STREAM_CAPTURE].pmic_audio_device.handle = NULL; + + pmic_audio_close(handle); + + ssi_receive_enable(ssi, false); + ssi_interrupt_disable(ssi, ssi_rx_dma_interrupt_enable); + ssi_rx_fifo_enable(ssi, ssi_fifo_0, false); + ssi_enable(ssi, false); + mxc_dma_free((mxc_audio->s[1]).dma_wchannel); + + chip->s[substream->pstr->stream].stream = NULL; + + /* disable ssi clock */ + clk_disable(audio_data->ssi_clk[ssi]); + + return 0; +} + +/*! + * This function configure the Audio HW in terms of memory allocation. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_audio_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + struct snd_pcm_runtime *runtime; + int ret = 0, size; + int device, stream_id = -1; +#ifdef CONFIG_SND_MXC_PMIC_IRAM + struct snd_dma_buffer *dmab; +#endif /*CONFIG_SND_MXC_PMIC_IRAM */ + + runtime = substream->runtime; + ret = + snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); + if (ret < 0) + return ret; + size = params_buffer_bytes(hw_params); + device = substream->pcm->device; + if (device == 0) + stream_id = 0; + else if (device == 1) + stream_id = 2; + + runtime->dma_addr = virt_to_phys(runtime->dma_area); + +#ifdef CONFIG_SND_MXC_PMIC_IRAM + if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) && g_audio_iram_en + && stream_id == 0) { + if (runtime->dma_buffer_p + && (runtime->dma_buffer_p != &g_iram_dmab)) { + snd_pcm_lib_free_pages(substream); + } + dmab = &g_iram_dmab; + dmab->dev = substream->dma_buffer.dev; + dmab->area = (char *)ADMA_BASE_VADDR; + dmab->addr = ADMA_BASE_PADDR; + dmab->bytes = size; + snd_pcm_set_runtime_buffer(substream, dmab); + runtime->dma_bytes = size; + } else +#endif /* CONFIG_SND_MXC_PMIC_IRAM */ + { + ret = snd_pcm_lib_malloc_pages(substream, size); + if (ret < 0) + return ret; + + runtime->dma_addr = virt_to_phys(runtime->dma_area); + } + + pr_debug("MXC: snd_mxc_audio_hw_params runtime->dma_addr 0x(%x)\n", + (unsigned int)runtime->dma_addr); + pr_debug("MXC: snd_mxc_audio_hw_params runtime->dma_area 0x(%x)\n", + (unsigned int)runtime->dma_area); + pr_debug("MXC: snd_mxc_audio_hw_params runtime->dma_bytes 0x(%x)\n", + (unsigned int)runtime->dma_bytes); + + return ret; +} + +/*! + * This function frees the audio hardware at the end of playback/capture. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_audio_hw_free(struct snd_pcm_substream *substream) +{ +#ifdef CONFIG_SND_MXC_PMIC_IRAM + if (substream->runtime->dma_buffer_p == &g_iram_dmab) { + snd_pcm_set_runtime_buffer(substream, NULL); + return 0; + } else +#endif /* CONFIG_SND_MXC_PMIC_IRAM */ + { + return snd_pcm_lib_free_pages(substream); + } + return 0; +} + +/*! + * This function configures the hardware to allow audio + * capture operations. It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_audio_capture_prepare(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + audio_stream_t *s; + int ssi; + + chip = snd_pcm_substream_chip(substream); + s = &chip->s[substream->pstr->stream]; + ssi = s->ssi; + + normalize_speed_for_pmic(substream); + + pr_debug("substream->pstr->stream %d\n", substream->pstr->stream); + pr_debug("SSI %d\n", ssi + 1); + configure_dam_pmic_master(ssi); + + configure_ssi_rx(substream); + + ssi_interrupt_enable(ssi, ssi_rx_dma_interrupt_enable); + + if (configure_pmic_recording(substream) == -1) + pr_debug(KERN_ERR "MXC: PMIC Record Config FAILED\n"); + + ssi_interrupt_enable(ssi, ssi_rx_fifo_0_full); + ssi_receive_enable(ssi, true); + + msleep(20); + set_pmic_channels(substream); + + s->period = 0; + s->periods = 0; + + return 0; +} + +/*! + * This function opens an PMIC audio device in capture mode + * on Codec. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_card_mxc_audio_capture_open(struct snd_pcm_substream *substream) +{ + mxc_pmic_audio_t *chip; + struct snd_pcm_runtime *runtime; + int stream_id; + int err; + PMIC_AUDIO_HANDLE temp_handle; + audio_stream_t *s; + + chip = snd_pcm_substream_chip(substream); + runtime = substream->runtime; + stream_id = substream->pstr->stream; + s = &chip->s[stream_id]; + err = -1; + + if ((audio_data->ssi_num == 1) + && (audio_mixer_control.stdac_playback_active)) { + return -EBUSY; + } + if (PMIC_SUCCESS == pmic_audio_open(&temp_handle, VOICE_CODEC)) { + audio_mixer_control.voice_codec_handle = temp_handle; + audio_mixer_control.codec_capture_active = 1; + chip->s[SNDRV_PCM_STREAM_CAPTURE].pmic_audio_device.handle = + temp_handle; + } else { + if (audio_mixer_control.codec_playback_active) { + temp_handle = audio_mixer_control.voice_codec_handle; + } else { + return -EBUSY; + } + } + pmic_audio_antipop_enable(ANTI_POP_RAMP_SLOW); + + chip->s[stream_id].stream = substream; + + if (stream_id == SNDRV_PCM_STREAM_CAPTURE) { + runtime->hw = snd_mxc_pmic_capture; + } else { + return err; + } + + err = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (err < 0) + return err; + + err = snd_pcm_hw_constraint_list(runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &hw_capture_rates); + if (err < 0) + return err; + + /* setup DMA controller for Record */ + err = configure_read_channel(&mxc_audio->s[SNDRV_PCM_STREAM_CAPTURE], + audio_capture_dma_callback); + if (err < 0) { + return err; + } + + /* enable ssi clock */ + clk_enable(audio_data->ssi_clk[s->ssi]); + + msleep(50); + + return 0; +} + +#ifdef CONFIG_SND_MXC_PMIC_IRAM +static struct page *snd_mxc_audio_playback_nopage(struct vm_area_struct *area, + unsigned long address, + int *type) +{ + struct snd_pcm_substream *substream = area->vm_private_data; + struct snd_pcm_runtime *runtime; + unsigned long offset; + struct page *page; + void *vaddr; + size_t dma_bytes; + + if (substream == NULL) + return NOPAGE_OOM; + runtime = substream->runtime; + if (g_audio_iram_en) { + return NOPAGE_SIGBUS; + } + offset = area->vm_pgoff << PAGE_SHIFT; + offset += address - area->vm_start; + if (snd_BUG_ON(offset % PAGE_SIZE) != 0) + return NOPAGE_OOM; + dma_bytes = PAGE_ALIGN(runtime->dma_bytes); + if (offset > dma_bytes - PAGE_SIZE) + return NOPAGE_SIGBUS; + if (substream->ops->page) { + page = substream->ops->page(substream, offset); + if (!page) + return NOPAGE_OOM; + } else { + vaddr = runtime->dma_area + offset; + page = virt_to_page(vaddr); + } + get_page(page); + if (type) + *type = VM_FAULT_MINOR; + return page; +} + +static struct vm_operations_struct snd_mxc_audio_playback_vm_ops = { + .open = snd_pcm_mmap_data_open, + .close = snd_pcm_mmap_data_close, + .nopage = snd_mxc_audio_playback_nopage, +}; + +#ifdef CONFIG_ARCH_MX3 +static inline int snd_mxc_set_pte_attr(struct mm_struct *mm, + pmd_t *pmd, + unsigned long addr, unsigned long end) +{ + pte_t *pte; + spinlock_t *ptl; + pte = pte_alloc_map_lock(mm, pmd, addr, &ptl); + + if (!pte) + return -ENOMEM; + do { + /* The mapping is created. It should not be none. */ + BUG_ON(pte_none(*pte)); + /* Directly modify to non-shared device */ + *(pte - 512) |= 0x83; + } while (pte++, addr += PAGE_SIZE, addr != end); + + pte_unmap_unlock(pte - 1, ptl); + + return 0; + +} + +static int snd_mxc_set_pmd_attr(struct mm_struct *mm, + pud_t *pud, + unsigned long addr, unsigned long end) +{ + + pmd_t *pmd; + unsigned long next; + pmd = pmd_alloc(mm, pud, addr); + + if (!pmd) + return -ENOMEM; + do { + + next = pmd_addr_end(addr, end); + if (snd_mxc_set_pte_attr(mm, pmd, addr, next)) + return -ENOMEM; + + } while (pmd++, addr = next, addr != end); + + return 0; + +} + +static int snd_mxc_set_pud_attr(struct mm_struct *mm, + pgd_t *pgd, + unsigned long addr, unsigned long end) +{ + + pud_t *pud; + unsigned long next; + pud = pud_alloc(mm, pgd, addr); + + if (!pud) + return -ENOMEM; + do { + + next = pud_addr_end(addr, end); + if (snd_mxc_set_pmd_attr(mm, pud, addr, next)) + return -ENOMEM; + + } while (pud++, addr = next, addr != end); + + return 0; + +} + +static inline int snd_mxc_set_pgd_attr(struct vm_area_struct *area) +{ + + int ret = 0; + pgd_t *pgd; + struct mm_struct *mm = current->mm; + unsigned long next, addr = area->vm_start; + + pgd = pgd_offset(mm, addr); + flush_cache_range(area, addr, area->vm_end); + + do { + if (!pgd_present(*pgd)) + return -1; + + next = pgd_addr_end(addr, area->vm_end); + ret = snd_mxc_set_pud_attr(mm, pgd, addr, next); + if (ret) + break; + + } while (pgd++, addr = next, addr != area->vm_end); + + return ret; + +} + +#else +#define snd_mxc_set_page_attr() (0) +#endif + +static int snd_mxc_audio_playback_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *area) +{ + int ret = 0; + area->vm_ops = &snd_mxc_audio_playback_vm_ops; + area->vm_private_data = substream; + if (g_audio_iram_en) { + unsigned long off = area->vm_pgoff << PAGE_SHIFT; + unsigned long phys = ADMA_BASE_PADDR + off; + unsigned long size = area->vm_end - area->vm_start; + if (off + size > MAX_IRAM_SIZE) { + return -EINVAL; + } + area->vm_page_prot = pgprot_nonshareddev(area->vm_page_prot); + area->vm_flags |= VM_IO; + ret = + remap_pfn_range(area, area->vm_start, phys >> PAGE_SHIFT, + size, area->vm_page_prot); + if (ret == 0) { + ret = snd_mxc_set_pgd_attr(area); + } + + } else { + area->vm_flags |= VM_RESERVED; + } + if (ret == 0) + area->vm_ops->open(area); + return ret; +} + +#endif /*CONFIG_SND_MXC_PMIC_IRAM */ + +/*! + * This structure is the list of operation that the driver + * must provide for the capture interface + */ +static struct snd_pcm_ops snd_card_mxc_audio_capture_ops = { + .open = snd_card_mxc_audio_capture_open, + .close = snd_card_mxc_audio_capture_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_mxc_audio_hw_params, + .hw_free = snd_mxc_audio_hw_free, + .prepare = snd_mxc_audio_capture_prepare, + .trigger = snd_mxc_audio_capture_trigger, + .pointer = snd_mxc_audio_capture_pointer, +}; + +/*! + * This structure is the list of operation that the driver + * must provide for the playback interface + */ +static struct snd_pcm_ops snd_card_mxc_audio_playback_ops = { + .open = snd_card_mxc_audio_playback_open, + .close = snd_card_mxc_audio_playback_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_mxc_audio_hw_params, + .hw_free = snd_mxc_audio_hw_free, + .prepare = snd_mxc_audio_playback_prepare, + .trigger = snd_mxc_audio_playback_trigger, + .pointer = snd_mxc_audio_playback_pointer, +#ifdef CONFIG_SND_MXC_PMIC_IRAM + .mmap = snd_mxc_audio_playback_mmap, +#endif /*CONFIG_SND_MXC_PMIC_IRAM */ +}; + +/*! + * This functions initializes the capture audio device supported by + * PMIC IC. + * + * @param mxc_audio pointer to the sound card structure + * + */ +void init_device_capture(mxc_pmic_audio_t *mxc_audio) +{ + audio_stream_t *audio_stream; + pmic_audio_device_t *pmic_device; + + audio_stream = &mxc_audio->s[SNDRV_PCM_STREAM_CAPTURE]; + pmic_device = &audio_stream->pmic_audio_device; + + /* These parameters defines the identity of + * the device (codec or stereodac) + */ + audio_stream->ssi = SSI1; + audio_stream->dam_port = DAM_PORT_4; + pmic_device->ssi = SSI1; + + pmic_device->mode = BUS_MASTER_MODE; + pmic_device->protocol = NETWORK_MODE; + +#ifdef CONFIG_MXC_PMIC_SC55112 + pmic_device->pll = CLOCK_IN_CLKIN; + pmic_device->pll_rate = VCODEC_CLI_33_6MHZ; +#else + if (machine_is_mx31ads()) { + pmic_device->pll = CLOCK_IN_CLIB; + } else { + pmic_device->pll = CLOCK_IN_CLIA; + } + pmic_device->pll_rate = VCODEC_CLI_26MHZ; +#endif + pmic_device->bcl_inverted = 0; + pmic_device->fs_inverted = 0; + +} + +/*! + * This functions initializes the playback audio device supported by + * PMIC IC. + * + * @param mxc_audio pointer to the sound card structure. + * @param device device ID of PCM instance. + * + */ +void init_device_playback(mxc_pmic_audio_t *mxc_audio, int device) +{ + audio_stream_t *audio_stream; + pmic_audio_device_t *pmic_device; + if (device == 0) + audio_stream = &mxc_audio->s[0]; + else + audio_stream = &mxc_audio->s[2]; + pmic_device = &audio_stream->pmic_audio_device; + + /* These parameters defines the identity of + * the device (codec or stereodac) + */ + if (device == 0) { + if (audio_data->ssi_num == 2) { + audio_stream->ssi = SSI2; + audio_stream->dam_port = DAM_PORT_5; + pmic_device->ssi = SSI2; + } else { + audio_stream->ssi = SSI1; + audio_stream->dam_port = DAM_PORT_4; + pmic_device->ssi = SSI1; + } + + pmic_device->mode = BUS_MASTER_MODE; + pmic_device->protocol = NETWORK_MODE; + +#ifdef CONFIG_MXC_PMIC_SC55112 + pmic_device->pll = CLOCK_IN_CLKIN; + pmic_device->pll_rate = STDAC_CLI_33_6MHZ; +#else + if (machine_is_mx31ads()) { + pmic_device->pll = CLOCK_IN_CLIB; + } else { + pmic_device->pll = CLOCK_IN_CLIA; + } + pmic_device->pll_rate = STDAC_CLI_26MHZ; +#endif + + pmic_device->bcl_inverted = 0; + pmic_device->fs_inverted = 0; + + } else if ((device == 1) || (device == 2)) { + audio_stream->ssi = SSI1; + audio_stream->dam_port = DAM_PORT_4; + pmic_device->ssi = SSI1; + + pmic_device->mode = BUS_MASTER_MODE; + pmic_device->protocol = NETWORK_MODE; + +#ifdef CONFIG_MXC_PMIC_SC55112 + pmic_device->pll = CLOCK_IN_CLKIN; + pmic_device->pll_rate = VCODEC_CLI_33_6MHZ; +#else + if (machine_is_mx31ads()) { + pmic_device->pll = CLOCK_IN_CLIB; + } else { + pmic_device->pll = CLOCK_IN_CLIA; + } + pmic_device->pll_rate = VCODEC_CLI_26MHZ; +#endif + pmic_device->bcl_inverted = 0; + pmic_device->fs_inverted = 0; + } + +} + +/*! + * This functions initializes the mixer related information + * + * @param mxc_audio pointer to the sound card structure. + * + */ +void mxc_pmic_mixer_controls_init(mxc_pmic_audio_t *mxc_audio) +{ + audio_mixer_control_t *audio_control; + int i = 0; + + audio_control = &audio_mixer_control; + + memset(audio_control, 0, sizeof(audio_mixer_control_t)); + sema_init(&audio_control->sem, 1); + + audio_control->input_device = SOUND_MASK_MIC; + audio_control->output_device = SOUND_MASK_VOLUME | SOUND_MASK_PCM; + + /* PMIC has to internal sources that can be routed to output + One is codec direct out and the other is mixer out + Initially we configure all outputs to have no source and + will be later configured either by PCM stream handler or mixer */ + for (i = 0; i < OP_MAXDEV && i != OP_HEADSET; i++) { + audio_control->source_for_output[i] = MIXER_OUT; + } + + /* These bits are initially reset and set when playback begins */ + audio_control->codec_out_to_mixer = 0; + audio_control->stdac_out_to_mixer = 0; + + audio_control->mixer_balance = 50; + if (machine_is_mx31ads()) + audio_control->mixer_mono_adder = STEREO_OPPOSITE_PHASE; + else + audio_control->mixer_mono_adder = MONO_ADDER_OFF; + /* Default values for input and output */ + audio_control->input_volume = ((40 << 8) & 0xff00) | (40 & 0x00ff); + audio_control->master_volume_out = ((50 << 8) & 0xff00) | (50 & 0x00ff); + + if (PMIC_SUCCESS != pmic_audio_set_autodetect(1)) + msleep(30); +} + +/*! + * This functions initializes the 2 audio devices supported by + * PMIC IC. The parameters define the type of device (CODEC or STEREODAC) + * + * @param mxc_audio pointer to the sound card structure. + * @param device device id of the PCM stream. + * + */ +void mxc_pmic_audio_init(mxc_pmic_audio_t *mxc_audio, int device) +{ + if (device == 0) { + mxc_audio->s[SNDRV_PCM_STREAM_PLAYBACK].id = "Audio out"; + mxc_audio->s[SNDRV_PCM_STREAM_PLAYBACK].stream_id = + SNDRV_PCM_STREAM_PLAYBACK; + mxc_audio->s[SNDRV_PCM_STREAM_CAPTURE].id = "Audio in"; + mxc_audio->s[SNDRV_PCM_STREAM_CAPTURE].stream_id = + SNDRV_PCM_STREAM_CAPTURE; + } else if (device == 1) { + mxc_audio->s[2].id = "Audio out"; + mxc_audio->s[2].stream_id = 2; + } else if (device == 2) { + mxc_audio->s[2].id = "Audio out"; + mxc_audio->s[2].stream_id = 3; + } + + init_device_playback(mxc_audio, device); + if (!device) { + init_device_capture(mxc_audio); + } +} + +/*! + * This function the soundcard structure. + * + * @param mxc_audio pointer to the sound card structure. + * @param device the device index (zero based) + * + * @return 0 on success, -1 otherwise. + */ +static int __devinit snd_card_mxc_audio_pcm(mxc_pmic_audio_t *mxc_audio, + int device) +{ + struct snd_pcm *pcm; + int err; + + /* + * Create a new PCM instance with 1 capture stream and 1 playback substream + */ + err = snd_pcm_new(mxc_audio->card, "MXC", device, 1, 1, &pcm); + if (err < 0) + return err; + + /* + * this sets up our initial buffers and sets the dma_type to isa. + * isa works but I'm not sure why (or if) it's the right choice + * this may be too large, trying it for now + */ + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, + snd_dma_continuous_data + (GFP_KERNEL), MAX_BUFFER_SIZE * 2, + MAX_BUFFER_SIZE * 2); + + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_card_mxc_audio_playback_ops); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, + &snd_card_mxc_audio_capture_ops); + + pcm->private_data = mxc_audio; + pcm->info_flags = 0; + strncpy(pcm->name, SOUND_CARD_NAME, sizeof(pcm->name)); + mxc_audio->pcm[device] = pcm; + mxc_pmic_audio_init(mxc_audio, device); + + /* Allocating a second device for PCM playback on voice codec */ + device = 1; + err = snd_pcm_new(mxc_audio->card, "MXC", device, 1, 0, &pcm); + if (err < 0) + return err; + + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, + snd_dma_continuous_data + (GFP_KERNEL), MAX_BUFFER_SIZE * 2, + MAX_BUFFER_SIZE * 2); + + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_card_mxc_audio_playback_ops); + pcm->private_data = mxc_audio; + pcm->info_flags = 0; + strncpy(pcm->name, SOUND_CARD_NAME, sizeof(pcm->name)); + mxc_audio->pcm[device] = pcm; + mxc_pmic_audio_init(mxc_audio, device); + + device = 2; + err = snd_pcm_new(mxc_audio->card, "MXC", device, 1, 0, &pcm); + if (err < 0) + return err; + + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, + snd_dma_continuous_data + (GFP_KERNEL), MAX_BUFFER_SIZE * 2, + MAX_BUFFER_SIZE * 2); + + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_card_mxc_audio_playback_ops); + pcm->private_data = mxc_audio; + pcm->info_flags = 0; + strncpy(pcm->name, SOUND_CARD_NAME, sizeof(pcm->name)); + mxc_audio->pcm[device] = pcm; + + /* End of allocation */ + /* FGA for record and not hard coded playback */ + mxc_pmic_mixer_controls_init(mxc_audio); + + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function suspends all active streams. + * + * TBD + * + * @param card pointer to the sound card structure. + * @param state requested state + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_audio_suspend(struct platform_device *dev, + pm_message_t state) +{ + struct snd_card *card = platform_get_drvdata(dev); + mxc_pmic_audio_t *chip = card->private_data; + + snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); + snd_pcm_suspend_all(chip->pcm[0]); + + return 0; +} + +/*! + * This function resumes all suspended streams. + * + * TBD + * + * @param card pointer to the sound card structure. + * @param state requested state + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_audio_resume(struct platform_device *dev) +{ + struct snd_card *card = platform_get_drvdata(dev); + + snd_power_change_state(card, SNDRV_CTL_POWER_D0); + + return 0; +} +#endif /* COMFIG_PM */ + +/*! + * This function frees the sound card structure + * + * @param card pointer to the sound card structure. + * + * @return 0 on success, -1 otherwise. + */ +void snd_mxc_audio_free(struct snd_card *card) +{ + mxc_pmic_audio_t *chip; + + chip = card->private_data; + audio_dma_free(&chip->s[SNDRV_PCM_STREAM_PLAYBACK]); + audio_dma_free(&chip->s[SNDRV_PCM_STREAM_CAPTURE]); + mxc_audio = NULL; + card->private_data = NULL; + kfree(chip); + +} + +/*! + * This function initializes the driver in terms of memory of the soundcard + * and some basic HW clock settings. + * + * @return 0 on success, -1 otherwise. + */ +static int __devinit mxc_alsa_audio_probe(struct platform_device *pdev) +{ + int err; + struct snd_card *card; + + audio_data = (struct mxc_audio_platform_data *)pdev->dev.platform_data; + if (!audio_data) { + dev_err(&pdev->dev, "Can't get the platform data for ALSA\n"); + return -EINVAL; + } + /* register the soundcard */ + err = snd_card_create(-1, id, THIS_MODULE, sizeof(mxc_pmic_audio_t), &card); + if (err < 0) { + return -ENOMEM; + } + + mxc_audio = kcalloc(1, sizeof(*mxc_audio), GFP_KERNEL); + if (mxc_audio == NULL) { + return -ENOMEM; + } + + card->private_data = (void *)mxc_audio; + card->private_free = snd_mxc_audio_free; + + mxc_audio->card = card; + card->dev = &pdev->dev; + err = snd_card_mxc_audio_pcm(mxc_audio, 0); + if (err < 0) + goto nodev; + + if (0 == mxc_alsa_create_ctl(card, (void *)&audio_mixer_control)) + printk(KERN_INFO "Control ALSA component registered\n"); + +#ifdef CONFIG_HEADSET_DETECT_ENABLE + pmic_audio_antipop_enable(ANTI_POP_RAMP_SLOW); + pmic_audio_set_callback((PMIC_AUDIO_CALLBACK) HSCallback, + HEADSET_DETECTED | HEADSET_REMOVED, &hs_state); +#endif + /* Set autodetect feature in order to allow audio operations */ + + spin_lock_init(&(mxc_audio->s[0].dma_lock)); + spin_lock_init(&(mxc_audio->s[1].dma_lock)); + spin_lock_init(&(mxc_audio->s[2].dma_lock)); + + strcpy(card->driver, "MXC"); + strcpy(card->shortname, "PMIC-audio"); + sprintf(card->longname, "MXC Freescale with PMIC"); + + err = snd_card_register(card); + if (err == 0) { + pr_debug(KERN_INFO "MXC audio support initialized\n"); + platform_set_drvdata(pdev, card); + return 0; + } + + nodev: + snd_card_free(card); + return err; +} + +static int __devexit mxc_alsa_audio_remove(struct platform_device *dev) +{ + snd_card_free(mxc_audio->card); + kfree(mxc_audio); + platform_set_drvdata(dev, NULL); + + return 0; +} + +static struct platform_driver mxc_alsa_audio_driver = { + .probe = mxc_alsa_audio_probe, + .remove = __devexit_p(mxc_alsa_audio_remove), +#ifdef CONFIG_PM + .suspend = snd_mxc_audio_suspend, + .resume = snd_mxc_audio_resume, +#endif + .driver = { + .name = "mxc_alsa", + }, +}; + +static int __init mxc_alsa_audio_init(void) +{ + return platform_driver_register(&mxc_alsa_audio_driver); +} + +/*! + * This function frees the sound driver structure. + * + */ + +static void __exit mxc_alsa_audio_exit(void) +{ + platform_driver_unregister(&mxc_alsa_audio_driver); +} + +module_init(mxc_alsa_audio_init); +module_exit(mxc_alsa_audio_exit); + +MODULE_AUTHOR("FREESCALE SEMICONDUCTOR"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MXC driver for ALSA"); +MODULE_SUPPORTED_DEVICE("{{PMIC}}"); + +module_param(id, charp, 0444); +MODULE_PARM_DESC(id, "ID string for MXC + PMIC soundcard."); diff --git a/sound/arm/mxc-alsa-pmic.h b/sound/arm/mxc-alsa-pmic.h new file mode 100644 index 000000000000..ccda66ecc70f --- /dev/null +++ b/sound/arm/mxc-alsa-pmic.h @@ -0,0 +1,110 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /*! + * @file mxc-alsa-pmic.h + * @brief + * @ingroup SOUND_DRV + */ + +#ifndef __MXC_ALSA_PMIC_H__ +#define __MXC_ALSA_PMIC_H__ + +#ifdef __KERNEL__ + + /**/ +#define PMIC_MASTER 0x1 +#define PMIC_SLAVE 0x2 + /**/ +#define DAM_PORT_4 port_4 +#define DAM_PORT_5 port_5 + /**/ +#define PMIC_STEREODAC 0x1 +#define PMIC_CODEC 0x2 + /**/ +#define PMIC_AUDIO_ADDER_STEREO 0x1 +#define PMIC_AUDIO_ADDER_STEREO_OPPOSITE 0x2 +#define PMIC_AUDIO_ADDER_MONO 0x4 +#define PMIC_AUDIO_ADDER_MONO_OPPOSITE 0x8 +#define TX_WATERMARK 0x4 +#define RX_WATERMARK 0x6 + /**/ +#define SSI_DEFAULT_FIFO 0x0 +#define DEFAULT_MASTER_CLOCK 0x1 + /**/ +#define SDMA_TXFIFO_WATERMARK 0x4 +#define SDMA_RXFIFO_WATERMARK 0x6 + /**/ +#define TIMESLOTS_2 0x3 +#define TIMESLOTS_4 0x2 +#define SAMPLE_RATE_MAX 0x9 + /**/ +#define CLK_SELECT_SLAVE_BCL 0x7 +#define CLK_SELECT_SLAVE_CLI 0x5 +#define CLK_SELECT_MASTER_CLI 0x4 +/* Volume to balance ratio */ +#define VOLUME_BALANCE_RATIO ((6 + 39) / (21 + 21)) +/* -21dB */ +#define PMIC_BALANCE_MIN 0x0 +/* 0dB*/ +#define PMIC_BALANCE_MAX 0x7 +/* -21dB left */ +#define BALANCE_MIN 0x0 +/* 0db, no balance */ +#define NO_BALANCE 0x32 +/* -21dB right*/ +#define BALANCE_MAX 0x64 +/* -8dB */ +#define PMIC_INPUT_VOLUME_MIN 0x0 +/* +23dB */ +#define PMIC_INPUT_VOLUME_MAX 0x1f +/* -39dB */ +#define PMIC_OUTPUT_VOLUME_MIN PMIC_INPUT_VOLUME_MIN +/* +6dB */ +#define PMIC_OUTPUT_VOLUME_MAX 0xd +/* -8dB */ +#define INPUT_VOLUME_MIN 0x0 +/* +23dB */ +#define INPUT_VOLUME_MAX 0x64 +/* -39dB */ +#define OUTPUT_VOLUME_MIN 0x0 +/* +6dB */ +#define OUTPUT_VOLUME_MAX 0x64 +/* 96 Khz */ +#define SAMPLE_FREQ_MAX 96000 +/* 8 Khz */ +#define SAMPLE_FREQ_MIN 8000 +/*! + * Define channels available on MC13783. This is mainly used + * in mixer interface to control different input/output + * devices + */ +#define MXC_STEREO_OUTPUT (SOUND_MASK_VOLUME | SOUND_MASK_PCM) +#define MXC_STEREO_INPUT (SOUND_MASK_PHONEIN) +#define MXC_MONO_OUTPUT (SOUND_MASK_PHONEOUT | SOUND_MASK_SPEAKER) +#define MXC_MONO_INPUT (SOUND_MASK_LINE | SOUND_MASK_MIC) +#define SNDCTL_CLK_SET_MASTER _SIOR('Z', 30, int) +#define SNDCTL_PMIC_READ_OUT_BALANCE _SIOR('Z', 8, int) +/*#define SNDCTL_MC13783_WRITE_OUT_BALANCE _SIOWR('Z', 9, int)*/ +#define SNDCTL_PMIC_WRITE_OUT_ADDER _SIOWR('Z', 10, int) +#define SNDCTL_PMIC_READ_OUT_ADDER _SIOR('Z', 11, int) +#define SNDCTL_PMIC_WRITE_CODEC_FILTER _SIOWR('Z', 12, int) +#define SNDCTL_PMIC_READ_CODEC_FILTER _SIOR('Z', 13, int) +#define SNDCTL_DAM_SET_OUT_PORT _SIOWR('Z', 14, int) +#endif /* __KERNEL__ */ +#endif /* __MXC_ALSA_PMIC_H__ */ diff --git a/sound/arm/mxc-alsa-spdif.c b/sound/arm/mxc-alsa-spdif.c new file mode 100644 index 000000000000..2ab3b22ae0d7 --- /dev/null +++ b/sound/arm/mxc-alsa-spdif.c @@ -0,0 +1,2293 @@ +/* + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @defgroup SOUND_DRV MXC Sound Driver for ALSA + */ + +/*! + * @file mxc-alsa-spdif.c + * @brief this fle mxc-alsa-spdif.c + * @brief this file implements mxc alsa driver for spdif. + * The spdif tx supports consumer channel for linear PCM and + * compressed audio data. The supported sample rates are + * 48KHz, 44.1KHz and 32KHz. + * + * @ingroup SOUND_DRV + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#define MXC_SPDIF_NAME "MXC_SPDIF" +static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; +static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; +static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE; +module_param_array(index, int, NULL, 0444); +MODULE_PARM_DESC(index, "Index value for spdif sound card."); +module_param_array(id, charp, NULL, 0444); +MODULE_PARM_DESC(id, "ID string for spdif sound card."); +module_param_array(enable, bool, NULL, 0444); +MODULE_PARM_DESC(enable, "Enable spdif sound card."); + +#define SPDIF_MAX_BUF_SIZE (32*1024) +#define SPDIF_DMA_BUF_SIZE (8*1024) +#define SPDIF_MIN_PERIOD_SIZE 64 +#define SPDIF_MIN_PERIOD 2 +#define SPDIF_MAX_PERIOD 255 + +#define SPDIF_REG_SCR 0x00 +#define SPDIF_REG_SRCD 0x04 +#define SPDIF_REG_SRPC 0x08 +#define SPDIF_REG_SIE 0x0C +#define SPDIF_REG_SIS 0x10 +#define SPDIF_REG_SIC 0x10 +#define SPDIF_REG_SRL 0x14 +#define SPDIF_REG_SRR 0x18 +#define SPDIF_REG_SRCSLH 0x1C +#define SPDIF_REG_SRCSLL 0x20 +#define SPDIF_REG_SQU 0x24 +#define SPDIF_REG_SRQ 0x28 +#define SPDIF_REG_STL 0x2C +#define SPDIF_REG_STR 0x30 +#define SPDIF_REG_STCSCH 0x34 +#define SPDIF_REG_STCSCL 0x38 +#define SPDIF_REG_SRFM 0x44 +#define SPDIF_REG_STC 0x50 + +/* SPDIF Configuration register */ +#define SCR_RXFIFO_CTL_ZERO (1 << 23) +#define SCR_RXFIFO_OFF (1 << 22) +#define SCR_RXFIFO_RST (1 << 21) +#define SCR_RXFIFO_FSEL_BIT (19) +#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_BIT) +#define SCR_RXFIFO_AUTOSYNC (1 << 18) +#define SCR_TXFIFO_AUTOSYNC (1 << 17) +#define SCR_TXFIFO_ESEL_BIT (15) +#define SCR_TXFIFO_ESEL_MASK (0x3 << SCR_TXFIFO_FSEL_BIT) +#define SCR_LOW_POWER (1 << 13) +#define SCR_SOFT_RESET (1 << 12) +#define SCR_TXFIFO_ZERO (0 << 10) +#define SCR_TXFIFO_NORMAL (1 << 10) +#define SCR_TXFIFO_ONESAMPLE (1 << 11) +#define SCR_DMA_RX_EN (1 << 9) +#define SCR_DMA_TX_EN (1 << 8) +#define SCR_VAL_CLEAR (1 << 5) +#define SCR_TXSEL_OFF (0 << 2) +#define SCR_TXSEL_RX (1 << 2) +#define SCR_TXSEL_NORMAL (0x5 << 2) +#define SCR_USRC_SEL_NONE (0x0) +#define SCR_USRC_SEL_RECV (0x1) +#define SCR_USRC_SEL_CHIP (0x3) + +/* SPDIF CDText control */ +#define SRCD_CD_USER_OFFSET 1 +#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET) + +/* SPDIF Phase Configuration register */ +#define SRPC_DPLL_LOCKED (1 << 6) +#define SRPC_CLKSRC_SEL_OFFSET 7 +#define SRPC_CLKSRC_SEL_LOCKED 5 +/* gain sel */ +#define SRPC_GAINSEL_OFFSET 3 + +enum spdif_gainsel { + GAINSEL_MULTI_24 = 0, + GAINSEL_MULTI_16, + GAINSEL_MULTI_12, + GAINSEL_MULTI_8, + GAINSEL_MULTI_6, + GAINSEL_MULTI_4, + GAINSEL_MULTI_3, + GAINSEL_MULTI_MAX, +}; + +#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8 + +/* SPDIF interrupt mask define */ +#define INT_DPLL_LOCKED (1 << 20) +#define INT_TXFIFO_UNOV (1 << 19) +#define INT_TXFIFO_RESYNC (1 << 18) +#define INT_CNEW (1 << 17) +#define INT_VAL_NOGOOD (1 << 16) +#define INT_SYM_ERR (1 << 15) +#define INT_BIT_ERR (1 << 14) +#define INT_URX_FUL (1 << 10) +#define INT_URX_OV (1 << 9) +#define INT_QRX_FUL (1 << 8) +#define INT_QRX_OV (1 << 7) +#define INT_UQ_SYNC (1 << 6) +#define INT_UQ_ERR (1 << 5) +#define INT_RX_UNOV (1 << 4) +#define INT_RX_RESYNC (1 << 3) +#define INT_LOSS_LOCK (1 << 2) +#define INT_TX_EMPTY (1 << 1) +#define INT_RXFIFO_FUL (1 << 0) + +/* SPDIF Clock register */ +#define STC_SYSCLK_DIV_OFFSET 11 +#define STC_TXCLK_SRC_OFFSET 8 +#define STC_TXCLK_DIV_OFFSET 0 + +#define SPDIF_CSTATUS_BYTE 6 +#define SPDIF_UBITS_SIZE 96 +#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE/8) + +enum spdif_clk_accuracy { + SPDIF_CLK_ACCURACY_LEV2 = 0, + SPDIF_CLK_ACCURACY_LEV1 = 2, + SPDIF_CLK_ACCURACY_LEV3 = 1, + SPDIF_CLK_ACCURACY_RESV = 3 +}; + +/* SPDIF clock source */ +enum spdif_clk_src { + SPDIF_CLK_SRC1 = 0, + SPDIF_CLK_SRC2, + SPDIF_CLK_SRC3, + SPDIF_CLK_SRC4, + SPDIF_CLK_SRC5, +}; + +enum spdif_max_wdl { + SPDIF_MAX_WDL_20, + SPDIF_MAX_WDL_24 +}; + +enum spdif_wdl { + SPDIF_WDL_DEFAULT = 0, + SPDIF_WDL_FIFTH = 4, + SPDIF_WDL_FOURTH = 3, + SPDIF_WDL_THIRD = 2, + SPDIF_WDL_SECOND = 1, + SPDIF_WDL_MAX = 5 +}; + +static unsigned int gainsel_multi[GAINSEL_MULTI_MAX] = { + 24 * 1024, 16 * 1024, 12 * 1024, + 8 * 1024, 6 * 1024, 4 * 1024, + 3 * 1024, +}; + +/*! + * SPDIF control structure + * Defines channel status, subcode and Q sub + */ +struct spdif_mixer_control { + + /* spinlock to access control data */ + spinlock_t ctl_lock; + /* IEC958 channel tx status bit */ + unsigned char ch_status[4]; + /* User bits */ + unsigned char subcode[2 * SPDIF_UBITS_SIZE]; + /* Q subcode part of user bits */ + unsigned char qsub[2 * SPDIF_QSUB_SIZE]; + /* buffer ptrs for writer */ + unsigned int upos; + unsigned int qpos; + /* ready buffer index of the two buffers */ + unsigned int ready_buf; +}; + +/*! + * This structure represents an audio stream in term of + * channel DMA, HW configuration on spdif controller. + */ +struct mxc_spdif_stream { + + /*! + * identification string + */ + char *id; + /*! + * device identifier for DMA + */ + int dma_wchannel; + /*! + * we are using this stream for transfer now + */ + int active:1; + /*! + * current transfer period + */ + int period; + /*! + * current count of transfered periods + */ + int periods; + /*! + * for locking in DMA operations + */ + spinlock_t dma_lock; + /*! + * Alsa substream pointer + */ + struct snd_pcm_substream *stream; +}; + +struct mxc_spdif_device { + /*! + * SPDIF module register base address + */ + unsigned long __iomem *reg_base; + unsigned long reg_phys_base; + + /*! + * spdif tx available or not + */ + int mxc_spdif_tx; + + /*! + * spdif rx available or not + */ + int mxc_spdif_rx; + + /*! + * spdif 44100 clock src + */ + int spdif_txclk_44100; + + /*! + * spdif 48000 clock src + */ + int spdif_txclk_48000; + + /*! + * ALSA SPDIF sound card handle + */ + struct snd_card *card; + + /*! + * ALSA spdif driver type handle + */ + struct snd_pcm *pcm; + + /*! + * DPLL locked status + */ + atomic_t dpll_locked; + + /*! + * Playback/Capture substream + */ + struct mxc_spdif_stream s[2]; +}; + +static struct spdif_mixer_control mxc_spdif_control; + +static unsigned long spdif_base_addr; + +/* define each spdif interrupt handlers */ +typedef void (*spdif_irq_func_t) (unsigned int bit, void *desc); + +/* spdif irq functions declare */ +static void spdif_irq_fifo(unsigned int bit, void *devid); +static void spdif_irq_dpll_lock(unsigned int bit, void *devid); +static void spdif_irq_uq(unsigned int bit, void *devid); +static void spdif_irq_bit_error(unsigned int bit, void *devid); +static void spdif_irq_sym_error(unsigned int bit, void *devid); +static void spdif_irq_valnogood(unsigned int bit, void *devid); +static void spdif_irq_cnew(unsigned int bit, void *devid); + +/* irq function list */ +static spdif_irq_func_t spdif_irq_handlers[] = { + spdif_irq_fifo, + spdif_irq_fifo, + spdif_irq_dpll_lock, + NULL, + spdif_irq_fifo, + spdif_irq_uq, + spdif_irq_uq, + spdif_irq_uq, + spdif_irq_uq, + spdif_irq_uq, + spdif_irq_uq, + NULL, + NULL, + NULL, + spdif_irq_bit_error, + spdif_irq_sym_error, + spdif_irq_valnogood, + spdif_irq_cnew, + NULL, + spdif_irq_fifo, + spdif_irq_dpll_lock, +}; + +/*! + * @brief Enable/Disable spdif DMA request + * + * This function is called to enable or disable the dma transfer + */ +static void spdif_dma_enable(int txrx, int enable) +{ + unsigned long value; + + value = __raw_readl(SPDIF_REG_SCR + spdif_base_addr) & 0xfffeff; + if (enable) + value |= txrx; + + __raw_writel(value, SPDIF_REG_SCR + spdif_base_addr); + +} + +/*! + * @brief Enable spdif interrupt + * + * This function is called to enable relevant interrupts. + */ +static void spdif_intr_enable(unsigned long intr, int enable) +{ + unsigned long value; + + value = __raw_readl(spdif_base_addr + SPDIF_REG_SIE) & 0xffffff; + if (enable) + value |= intr; + else + value &= ~intr; + + __raw_writel(value, spdif_base_addr + SPDIF_REG_SIE); +} + +/*! + * @brief Set the clock accuracy level in the channel bit + * + * This function is called to set the clock accuracy level + */ +static int spdif_set_clk_accuracy(enum spdif_clk_accuracy level) +{ + unsigned long value; + + value = __raw_readl(SPDIF_REG_STCSCL + spdif_base_addr) & 0xffffcf; + value |= (level << 4); + __raw_writel(value, SPDIF_REG_STCSCL + spdif_base_addr); + + return 0; +} + +/*! + * set SPDIF PhaseConfig register for rx clock + */ +static int spdif_set_rx_clksrc(enum spdif_clk_src clksrc, + enum spdif_gainsel gainsel, int dpll_locked) +{ + unsigned long value; + if (clksrc > SPDIF_CLK_SRC5 || gainsel > GAINSEL_MULTI_3) + return 1; + + value = (dpll_locked ? (clksrc) : + (clksrc + SRPC_CLKSRC_SEL_LOCKED)) << SRPC_CLKSRC_SEL_OFFSET | + (gainsel << SRPC_GAINSEL_OFFSET); + __raw_writel(value, spdif_base_addr + SPDIF_REG_SRPC); + + return 0; +} + +/*! + * Get RX data clock rate + * given the SPDIF bus_clk + */ +static int spdif_get_rxclk_rate(struct clk *bus_clk, enum spdif_gainsel gainsel) +{ + unsigned long freqmeas, phaseconf, busclk_freq = 0; + u64 tmpval64; + enum spdif_clk_src clksrc; + + freqmeas = __raw_readl(spdif_base_addr + SPDIF_REG_SRFM); + phaseconf = __raw_readl(spdif_base_addr + SPDIF_REG_SRPC); + + clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0x0F; + if (clksrc < 5 && (phaseconf & SRPC_DPLL_LOCKED)) { + /* get bus clock from system */ + busclk_freq = clk_get_rate(bus_clk); + } + + /* FreqMeas_CLK = (BUS_CLK*FreqMeas[23:0])/2^10/GAINSEL/128 */ + tmpval64 = (u64) busclk_freq * freqmeas; + do_div(tmpval64, gainsel_multi[gainsel]); + do_div(tmpval64, 128 * 1024); + return (int)tmpval64; +} + +/*! + * @brief Set the audio sample rate in the channel status bit + * + * This function is called to set the audio sample rate to be transfered. + */ +static int spdif_set_sample_rate(int src_44100, int src_48000, int sample_rate) +{ + unsigned long cstatus, stc; + int ret = 0; + + cstatus = __raw_readl(SPDIF_REG_STCSCL + spdif_base_addr) & 0xfffff0; + stc = __raw_readl(SPDIF_REG_STC + spdif_base_addr) & ~0x7FF; + + switch (sample_rate) { + case 44100: + if (src_44100 < 0) { + pr_info("spdif_set_sample_rate: no defined 44100 clk src\n"); + ret = -1; + } else { + __raw_writel(cstatus, SPDIF_REG_STCSCL + spdif_base_addr); + stc |= (src_44100 << 8) | 0x07; + __raw_writel(stc, SPDIF_REG_STC + spdif_base_addr); + pr_debug("set sample rate to 44100\n"); + } + break; + case 48000: + if (src_48000 < 0) { + pr_info("spdif_set_sample_rate: no defined 48000 clk src\n"); + ret = -1; + } else { + cstatus |= 0x04; + __raw_writel(cstatus, SPDIF_REG_STCSCL + spdif_base_addr); + stc |= (src_48000 << 8) | 0x07; + __raw_writel(stc, SPDIF_REG_STC + spdif_base_addr); + pr_debug("set sample rate to 48000\n"); + } + break; + case 32000: + if (src_48000 < 0) { + pr_info("spdif_set_sample_rate: no defined 48000 clk src\n"); + ret = -1; + } else { + cstatus |= 0x0c; + __raw_writel(cstatus, SPDIF_REG_STCSCL + spdif_base_addr); + stc |= (src_48000 << 8) | 0x0b; + __raw_writel(stc, SPDIF_REG_STC + spdif_base_addr); + pr_debug("set sample rate to 32000\n"); + } + break; + } + + return ret; +} + +/*! + * @brief Set the lchannel status bit + * + * This function is called to set the channel status + */ +static int spdif_set_channel_status(int value, unsigned long reg) +{ + __raw_writel(value & 0xffffff, reg + spdif_base_addr); + + return 0; +} + +/*! + * @brief Get spdif interrupt status and clear the interrupt + * + * This function is called to check relevant interrupt status + */ +static int spdif_intr_status(void) +{ + unsigned long value; + + value = __raw_readl(SPDIF_REG_SIS + spdif_base_addr) & 0xffffff; + value &= __raw_readl(spdif_base_addr + SPDIF_REG_SIE); + __raw_writel(value, SPDIF_REG_SIC + spdif_base_addr); + + return value; +} + +/*! + * @brief spdif interrupt handler + */ +static irqreturn_t spdif_isr(int irq, void *dev_id) +{ + unsigned long int_stat; + int line; + + int_stat = spdif_intr_status(); + + while ((line = ffs(int_stat)) != 0) { + int_stat &= ~(1UL << (line - 1)); + if (spdif_irq_handlers[line - 1] != NULL) + spdif_irq_handlers[line - 1] (line - 1, dev_id); + } + + return IRQ_HANDLED; +} + +/*! + * Interrupt handlers + * + */ +/*! + * FIFO related interrupts handler + * + * Rx FIFO Full, Underrun/Overrun interrupts + * Tx FIFO Empty, Underrun/Overrun interrupts + */ +static void spdif_irq_fifo(unsigned int bit, void *devid) +{ + +} + +/*! + * DPLL lock related interrupts handler + * + * DPLL locked and lock loss interrupts + */ +static void spdif_irq_dpll_lock(unsigned int bit, void *devid) +{ + struct mxc_spdif_device *chip = (struct mxc_spdif_device *)devid; + unsigned int locked = __raw_readl(spdif_base_addr + SPDIF_REG_SRPC); + + if (locked & SRPC_DPLL_LOCKED) { + pr_debug("SPDIF Rx dpll locked\n"); + atomic_set(&chip->dpll_locked, 1); + } else { + /* INT_LOSS_LOCK */ + pr_debug("SPDIF Rx dpll loss lock\n"); + atomic_set(&chip->dpll_locked, 0); + } +} + +/*! + * U/Q channel related interrupts handler + * + * U/QChannel full, overrun interrupts + * U/QChannel sync error and frame error interrupts + */ +static void spdif_irq_uq(unsigned int bit, void *devid) +{ + unsigned long val; + int index; + struct spdif_mixer_control *ctrl = &mxc_spdif_control; + + bit = 1 << bit; + /* get U/Q channel datas */ + switch (bit) { + + case INT_URX_OV: /* read U data */ + pr_debug("User bit receive overrun\n"); + case INT_URX_FUL: + pr_debug("U bit receive full\n"); + + if (ctrl->upos >= SPDIF_UBITS_SIZE * 2) { + ctrl->upos = 0; + } else if (unlikely((ctrl->upos % SPDIF_UBITS_SIZE) + 3 + > SPDIF_UBITS_SIZE)) { + pr_err("User bit receivce buffer overflow\n"); + break; + } + val = __raw_readl(spdif_base_addr + SPDIF_REG_SQU); + ctrl->subcode[ctrl->upos++] = val >> 16; + ctrl->subcode[ctrl->upos++] = val >> 8; + ctrl->subcode[ctrl->upos++] = val; + + break; + + case INT_QRX_OV: /* read Q data */ + pr_debug("Q bit receive overrun\n"); + case INT_QRX_FUL: + pr_debug("Q bit receive full\n"); + + if (ctrl->qpos >= SPDIF_QSUB_SIZE * 2) { + ctrl->qpos = 0; + } else if (unlikely((ctrl->qpos % SPDIF_QSUB_SIZE) + 3 + > SPDIF_QSUB_SIZE)) { + pr_err("Q bit receivce buffer overflow\n"); + break; + } + val = __raw_readl(spdif_base_addr + SPDIF_REG_SRQ); + ctrl->qsub[ctrl->qpos++] = val >> 16; + ctrl->qsub[ctrl->qpos++] = val >> 8; + ctrl->qsub[ctrl->qpos++] = val; + + break; + + case INT_UQ_ERR: /* read U/Q data and do buffer reset */ + pr_debug("U/Q bit receive error\n"); + val = __raw_readl(spdif_base_addr + SPDIF_REG_SQU); + val = __raw_readl(spdif_base_addr + SPDIF_REG_SRQ); + /* drop this U/Q buffer */ + ctrl->ready_buf = ctrl->upos = ctrl->qpos = 0; + break; + + case INT_UQ_SYNC: /* U/Q buffer reset */ + pr_debug("U/Q sync receive\n"); + + if (ctrl->qpos == 0) + break; + index = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE; + /* set ready to this buffer */ + ctrl->ready_buf = index + 1; + break; + } +} + +/*! + * SPDIF receiver found parity bit error interrupt handler + */ +static void spdif_irq_bit_error(unsigned int bit, void *devid) +{ + pr_debug("SPDIF interrupt parity bit error\n"); +} + +/*! + * SPDIF receiver found illegal symbol interrupt handler + */ +static void spdif_irq_sym_error(unsigned int bit, void *devid) +{ + pr_debug("SPDIF interrupt symbol error\n"); +} + +/*! + * SPDIF validity flag no good interrupt handler + */ +static void spdif_irq_valnogood(unsigned int bit, void *devid) +{ + pr_debug("SPDIF interrupt validate is not good\n"); +} + +/*! + * SPDIF receive change in value of control channel + */ +static void spdif_irq_cnew(unsigned int bit, void *devid) +{ + pr_debug("SPDIF interrupt cstatus new\n"); +} + +/*! + * Do software reset to SPDIF + */ +static void spdif_softreset(void) +{ + unsigned long value = 1; + int cycle = 0; + __raw_writel(SCR_SOFT_RESET, spdif_base_addr + SPDIF_REG_SCR); + while (value && (cycle++ < 10)) { + value = __raw_readl(spdif_base_addr + SPDIF_REG_SCR) & 0x1000; + } + +} + +/*! + * SPDIF RX initial function + */ +static void spdif_rx_init(void) +{ + unsigned long regval; + + regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR); + /** + * initial and reset SPDIF configuration: + * RxFIFO off + * RxFIFO sel to 8 sample + * Autosync + * Valid bit set + */ + regval &= ~(SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO | SCR_LOW_POWER); + regval |= (2 << SCR_RXFIFO_FSEL_BIT) | SCR_RXFIFO_AUTOSYNC; + __raw_writel(regval, spdif_base_addr + SPDIF_REG_SCR); +} + +/*! + * SPDIF RX un-initial function + */ +static void spdif_rx_uninit(void) +{ + unsigned long regval; + + /* turn off RX fifo, disable dma and autosync */ + regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR); + regval |= SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; + regval &= ~(SCR_DMA_RX_EN | SCR_RXFIFO_AUTOSYNC); + __raw_writel(regval, spdif_base_addr + SPDIF_REG_SCR); +} + +/*! + * @brief Initialize spdif module + * + * This function is called to set the spdif to initial state. + */ +static void spdif_tx_init(void) +{ + unsigned long regval; + + regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR); + + regval &= 0xfc33e3; + regval |= SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_NORMAL | + SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | (2 << SCR_TXFIFO_ESEL_BIT); + __raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr); + + /* Default clock source from EXTAL, divider by 8, generate 44.1kHz + sample rate */ + regval = 0x07; + __raw_writel(regval, SPDIF_REG_STC + spdif_base_addr); + +} + +/*! + * @brief deinitialize spdif module + * + * This function is called to stop the spdif + */ +static void spdif_tx_uninit(void) +{ + unsigned long regval; + + regval = __raw_readl(SPDIF_REG_SCR + spdif_base_addr) & 0xffffe3; + regval |= SCR_TXSEL_OFF; + __raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr); + regval = __raw_readl(SPDIF_REG_STC + spdif_base_addr) & ~0x7FF; + regval |= (0x7 << STC_TXCLK_SRC_OFFSET); + __raw_writel(regval, SPDIF_REG_STC + spdif_base_addr); + +} + +static unsigned int spdif_playback_rates[] = { 32000, 44100, 48000 }; +static unsigned int spdif_capture_rates[] = { + 16000, 32000, 44100, 48000, 64000, 96000 +}; + +/*! + * this structure represents the sample rates supported + * by SPDIF + */ +static struct snd_pcm_hw_constraint_list hw_playback_rates_stereo = { + .count = ARRAY_SIZE(spdif_playback_rates), + .list = spdif_playback_rates, + .mask = 0, +}; + +static struct snd_pcm_hw_constraint_list hw_capture_rates_stereo = { + .count = ARRAY_SIZE(spdif_capture_rates), + .list = spdif_capture_rates, + .mask = 0, +}; + +/*! + * This structure reprensents the capabilities of the driver + * in playback mode. + */ +static struct snd_pcm_hardware snd_spdif_playback_hw = { + .info = + (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_HALF_DUPLEX | + SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME), + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | + SNDRV_PCM_FMTBIT_S24_LE, + .rates = + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, + .rate_min = 32000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + .buffer_bytes_max = SPDIF_MAX_BUF_SIZE, + .period_bytes_min = SPDIF_MIN_PERIOD_SIZE, + .period_bytes_max = SPDIF_DMA_BUF_SIZE, + .periods_min = SPDIF_MIN_PERIOD, + .periods_max = SPDIF_MAX_PERIOD, + .fifo_size = 0, +}; + +/*! + * This structure reprensents the capabilities of the driver + * in capture mode. + */ +static struct snd_pcm_hardware snd_spdif_capture_hw = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), + .formats = SNDRV_PCM_FMTBIT_S24_LE, + .rates = + (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 + | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | + SNDRV_PCM_RATE_96000), + .rate_min = 16000, + .rate_max = 96000, + .channels_min = 2, + .channels_max = 2, + .buffer_bytes_max = SPDIF_MAX_BUF_SIZE, + .period_bytes_min = SPDIF_MIN_PERIOD_SIZE, + .period_bytes_max = SPDIF_DMA_BUF_SIZE, + .periods_min = SPDIF_MIN_PERIOD, + .periods_max = SPDIF_MAX_PERIOD, + .fifo_size = 0, + +}; + +/*! + * This function configures the DMA channel used to transfer + * audio from MCU to SPDIF or from SPDIF to MCU + * + * @param s pointer to the structure of the current stream. + * @param callback pointer to function that will be + * called when a SDMA TX transfer finishes. + * + * @return 0 on success, -1 otherwise. + */ +static int +spdif_configure_dma_channel(struct mxc_spdif_stream *s, + mxc_dma_callback_t callback) +{ + int ret = -1; + int channel = -1; + + if (s->dma_wchannel != 0) + mxc_dma_free(s->dma_wchannel); + + if (s->stream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + + if (s->stream->runtime->sample_bits > 16) { + channel = + mxc_dma_request(MXC_DMA_SPDIF_32BIT_TX, + "SPDIF TX DMA"); + } else { + channel = + mxc_dma_request(MXC_DMA_SPDIF_16BIT_TX, + "SPDIF TX DMA"); + } + + } else if (s->stream->stream == SNDRV_PCM_STREAM_CAPTURE) { + + channel = mxc_dma_request(MXC_DMA_SPDIF_32BIT_RX, + "SPDIF RX DMA"); + + } + + pr_debug("spdif_configure_dma_channel: %d\n", channel); + + ret = mxc_dma_callback_set(channel, + (mxc_dma_callback_t) callback, (void *)s); + if (ret != 0) { + pr_info("spdif_configure_dma_channel - err\n"); + mxc_dma_free(channel); + return -1; + } + s->dma_wchannel = channel; + return 0; +} + +/*! + * This function gets the dma pointer position during playback/capture. + * Our DMA implementation does not allow to retrieve this position + * when a transfert is active, so, it answers the middle of + * the current period beeing transfered + * + * @param s pointer to the structure of the current stream. + * + */ +static u_int spdif_get_dma_pos(struct mxc_spdif_stream *s) +{ + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int offset = 0; + substream = s->stream; + runtime = substream->runtime; + + offset = (runtime->period_size * (s->periods)); + if (offset >= runtime->buffer_size) + offset = 0; + pr_debug + ("MXC: spdif_get_dma_pos BIS offset %d, buffer_size %d\n", + offset, (int)runtime->buffer_size); + return offset; +} + +/*! + * This function stops the current dma transfert for playback + * and clears the dma pointers. + * + * @param s pointer to the structure of the current stream. + * + */ +static void spdif_stop_tx(struct mxc_spdif_stream *s) +{ + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int dma_size; + unsigned int offset; + + substream = s->stream; + runtime = substream->runtime; + dma_size = frames_to_bytes(runtime, runtime->period_size); + offset = dma_size * s->periods; + + s->active = 0; + s->period = 0; + s->periods = 0; + + /* this stops the dma channel and clears the buffer ptrs */ + mxc_dma_disable(s->dma_wchannel); + spdif_dma_enable(SCR_DMA_TX_EN, 0); + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_TO_DEVICE); +} + +/*! + * This function is called whenever a new audio block needs to be + * transferred to SPDIF. The function receives the address and the size + * of the new block and start a new DMA transfer. + * + * @param s pointer to the structure of the current stream. + * + */ +static void spdif_start_tx(struct mxc_spdif_stream *s) +{ + struct snd_pcm_substream *substream = s->stream; + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_spdif_device *chip = snd_pcm_substream_chip(substream); + unsigned int dma_size = 0; + unsigned int offset; + int ret = 0; + mxc_dma_requestbuf_t dma_request; + substream = s->stream; + runtime = substream->runtime; + memset(&dma_request, 0, sizeof(mxc_dma_requestbuf_t)); + if (s->active) { + dma_size = frames_to_bytes(runtime, runtime->period_size); + offset = dma_size * s->period; + dma_request.src_addr = + (dma_addr_t) (dma_map_single + (NULL, runtime->dma_area + offset, dma_size, + DMA_TO_DEVICE)); + + dma_request.dst_addr = (dma_addr_t) (chip->reg_phys_base + 0x2c); + + dma_request.num_of_bytes = dma_size; + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_WRITE); + ret = mxc_dma_enable(s->dma_wchannel); + if (ret) { + pr_info("audio_process_dma: cannot queue DMA \ + buffer\n"); + return; + } + s->period++; + s->period %= runtime->periods; + + if ((s->period > s->periods) + && ((s->period - s->periods) > 1)) { + pr_debug("audio playback chain dma: already double \ + buffered\n"); + return; + } + + if ((s->period < s->periods) + && ((s->period + runtime->periods - s->periods) > 1)) { + pr_debug("audio playback chain dma: already double \ + buffered\n"); + return; + } + + if (s->period == s->periods) { + pr_debug("audio playback chain dma: s->period == \ + s->periods\n"); + return; + } + + if (snd_pcm_playback_hw_avail(runtime) < + 2 * runtime->period_size) { + pr_debug("audio playback chain dma: available data \ + is not enough\n"); + return; + } + + pr_debug + ("audio playback chain dma:to set up the 2nd dma buffer\n"); + pr_debug("SCR: 0x%08x\n", + __raw_readl(spdif_base_addr + SPDIF_REG_SCR)); + + offset = dma_size * s->period; + dma_request.src_addr = + (dma_addr_t) (dma_map_single + (NULL, runtime->dma_area + offset, dma_size, + DMA_TO_DEVICE)); + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_WRITE); + ret = mxc_dma_enable(s->dma_wchannel); + s->period++; + s->period %= runtime->periods; + + } else + spdif_dma_enable(SCR_DMA_TX_EN, 0); + + return; +} + +/*! + * This is a callback which will be called + * when a TX transfer finishes. The call occurs + * in interrupt context. + * + * @param data pointer to the structure of the current stream + * @param error DMA error flag + * @param count number of bytes transfered by the DMA + */ +static void spdif_tx_callback(void *data, int error, unsigned int count) +{ + struct mxc_spdif_stream *s; + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int dma_size; + unsigned int previous_period; + unsigned int offset; + s = data; + substream = s->stream; + runtime = substream->runtime; + previous_period = s->periods; + dma_size = frames_to_bytes(runtime, runtime->period_size); + offset = dma_size * previous_period; + + spin_lock(&s->dma_lock); + s->periods++; + s->periods %= runtime->periods; + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_TO_DEVICE); + spin_unlock(&s->dma_lock); + + if (s->active) + snd_pcm_period_elapsed(s->stream); + + spin_lock(&s->dma_lock); + spdif_start_tx(s); + spin_unlock(&s->dma_lock); +} + +/*! + * This function is a dispatcher of command to be executed + * by the driver for playback. + * + * @param substream pointer to the structure of the current stream. + * @param cmd command to be executed + * + * @return 0 on success, -1 otherwise. + */ +static int +snd_mxc_spdif_playback_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct mxc_spdif_device *chip; + struct mxc_spdif_stream *s; + int err = 0; + unsigned long flags; + chip = snd_pcm_substream_chip(substream); + s = &chip->s[SNDRV_PCM_STREAM_PLAYBACK]; + + spin_lock_irqsave(&s->dma_lock, flags); + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + s->active = 1; + spdif_start_tx(s); + break; + case SNDRV_PCM_TRIGGER_STOP: + spdif_stop_tx(s); + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + s->active = 0; + s->periods = 0; + break; + case SNDRV_PCM_TRIGGER_RESUME: + s->active = 1; + spdif_start_tx(s); + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + s->active = 0; + break; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + s->active = 1; + spdif_start_tx(s); + break; + default: + err = -EINVAL; + break; + } + spin_unlock_irqrestore(&s->dma_lock, flags); + return err; +} + +/*! + * This function configures the hardware to allow audio + * playback operations. It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_spdif_playback_prepare(struct snd_pcm_substream *substream) +{ + struct mxc_spdif_device *chip; + struct snd_pcm_runtime *runtime; + int err; + unsigned int ch_status; + + chip = snd_pcm_substream_chip(substream); + runtime = substream->runtime; + + spdif_tx_init(); + + ch_status = + ((mxc_spdif_control.ch_status[2] << 16) | (mxc_spdif_control. + ch_status[1] << 8) | + mxc_spdif_control.ch_status[0]); + spdif_set_channel_status(ch_status, SPDIF_REG_STCSCH); + ch_status = mxc_spdif_control.ch_status[3]; + spdif_set_channel_status(ch_status, SPDIF_REG_STCSCL); + spdif_intr_enable(INT_TXFIFO_RESYNC, 1); + err = spdif_set_sample_rate(chip->spdif_txclk_44100, chip->spdif_txclk_48000, + runtime->rate); + if (err < 0) { + pr_info("snd_mxc_spdif_playback_prepare - err < 0\n"); + return err; + } + spdif_set_clk_accuracy(SPDIF_CLK_ACCURACY_LEV2); + /* setup DMA controller for spdif tx */ + err = spdif_configure_dma_channel(&chip-> + s[SNDRV_PCM_STREAM_PLAYBACK], + spdif_tx_callback); + if (err < 0) { + pr_info("snd_mxc_spdif_playback_prepare - err < 0\n"); + return err; + } + + /** + * FIXME: dump registers + */ + pr_debug("SCR: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SCR)); + pr_debug("SIE: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIE)); + pr_debug("STC: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_STC)); + return 0; +} + +/*! + * This function gets the current playback pointer position. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + */ +static snd_pcm_uframes_t +snd_mxc_spdif_playback_pointer(struct snd_pcm_substream *substream) +{ + struct mxc_spdif_device *chip; + chip = snd_pcm_substream_chip(substream); + return spdif_get_dma_pos(&chip->s[SNDRV_PCM_STREAM_PLAYBACK]); +} + +static int snd_card_mxc_spdif_playback_open(struct snd_pcm_substream *substream) +{ + struct mxc_spdif_device *chip; + struct snd_pcm_runtime *runtime; + int err; + struct mxc_spdif_platform_data *spdif_data; + + chip = snd_pcm_substream_chip(substream); + + spdif_data = chip->card->dev->platform_data; + /* enable tx clock */ + clk_enable(spdif_data->spdif_clk); + clk_enable(spdif_data->spdif_audio_clk); + + runtime = substream->runtime; + chip->s[SNDRV_PCM_STREAM_PLAYBACK].stream = substream; + runtime->hw = snd_spdif_playback_hw; + err = snd_pcm_hw_constraint_list(runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &hw_playback_rates_stereo); + if (err < 0) + goto failed; + err = + snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); + if (err < 0) + goto failed; + + return 0; + failed: + clk_disable(spdif_data->spdif_clk); + return err; +} + +/*! + * This function closes an spdif device for playback. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_card_mxc_spdif_playback_close(struct snd_pcm_substream + *substream) +{ + struct mxc_spdif_device *chip; + struct mxc_spdif_platform_data *spdif_data; + + chip = snd_pcm_substream_chip(substream); + spdif_data = chip->card->dev->platform_data; + + pr_debug("SIS: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIS)); + + spdif_intr_status(); + spdif_intr_enable(INT_TXFIFO_RESYNC, 0); + spdif_tx_uninit(); + clk_disable(spdif_data->spdif_audio_clk); + clk_disable(spdif_data->spdif_clk); + mxc_dma_free(chip->s[SNDRV_PCM_STREAM_PLAYBACK].dma_wchannel); + chip->s[SNDRV_PCM_STREAM_PLAYBACK].dma_wchannel = 0; + + return 0; +} + +/*! TODO: update the dma start/stop callback routine + * This function stops the current dma transfert for capture + * and clears the dma pointers. + * + * @param s pointer to the structure of the current stream. + * + */ +static void spdif_stop_rx(struct mxc_spdif_stream *s) +{ + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int dma_size; + unsigned int offset; + + substream = s->stream; + runtime = substream->runtime; + dma_size = frames_to_bytes(runtime, runtime->period_size); + offset = dma_size * s->periods; + + s->active = 0; + s->period = 0; + s->periods = 0; + + /* this stops the dma channel and clears the buffer ptrs */ + mxc_dma_disable(s->dma_wchannel); + spdif_dma_enable(SCR_DMA_RX_EN, 0); + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_FROM_DEVICE); +} + +/*! + * This function is called whenever a new audio block needs to be + * received from SPDIF. The function receives the address and the size + * of the new block and start a new DMA transfer. + * + * @param s pointer to the structure of the current stream. + * + */ +static void spdif_start_rx(struct mxc_spdif_stream *s) +{ + struct snd_pcm_substream *substream = s->stream; + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_spdif_device *chip = snd_pcm_substream_chip(substream); + unsigned int dma_size = 0; + unsigned int offset; + int ret = 0; + mxc_dma_requestbuf_t dma_request; + + memset(&dma_request, 0, sizeof(mxc_dma_requestbuf_t)); + + if (s->active) { + dma_size = frames_to_bytes(runtime, runtime->period_size); + pr_debug("s->period (%x) runtime->periods (%d)\n", + s->period, runtime->periods); + pr_debug("runtime->period_size (%d) dma_size (%d)\n", + (unsigned int)runtime->period_size, + runtime->dma_bytes); + + offset = dma_size * s->period; + dma_request.dst_addr = + (dma_addr_t) (dma_map_single + (NULL, runtime->dma_area + offset, dma_size, + DMA_FROM_DEVICE)); + + dma_request.src_addr = + (dma_addr_t) (chip->reg_phys_base + SPDIF_REG_SRL); + dma_request.num_of_bytes = dma_size; + /* config and enable sdma for RX */ + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_READ); + ret = mxc_dma_enable(s->dma_wchannel); + /* enable SPDIF dma */ + spdif_dma_enable(SCR_DMA_RX_EN, 1); + + if (ret) { + pr_info("audio_process_dma: cannot queue DMA \ + buffer\n"); + return; + } + s->period++; + s->period %= runtime->periods; + + if ((s->period > s->periods) + && ((s->period - s->periods) > 1)) { + pr_debug("audio capture chain dma: already double \ + buffered\n"); + return; + } + + if ((s->period < s->periods) + && ((s->period + runtime->periods - s->periods) > 1)) { + pr_debug("audio capture chain dma: already double \ + buffered\n"); + return; + } + + if (s->period == s->periods) { + pr_debug("audio capture chain dma: s->period == \ + s->periods\n"); + return; + } + + if (snd_pcm_capture_hw_avail(runtime) < + 2 * runtime->period_size) { + pr_debug("audio capture chain dma: available data \ + is not enough\n"); + return; + } + + pr_debug + ("audio playback chain dma:to set up the 2nd dma buffer\n"); + + offset = dma_size * s->period; + dma_request.dst_addr = + (dma_addr_t) (dma_map_single + (NULL, runtime->dma_area + offset, dma_size, + DMA_FROM_DEVICE)); + mxc_dma_config(s->dma_wchannel, &dma_request, 1, + MXC_DMA_MODE_READ); + ret = mxc_dma_enable(s->dma_wchannel); + s->period++; + s->period %= runtime->periods; + + } + return; +} + +/*! + * This is a callback which will be called + * when a RX transfer finishes. The call occurs + * in interrupt context. + * + * @param data pointer to the structure of the current stream + * @param error DMA error flag + * @param count number of bytes transfered by the DMA + */ +static void spdif_rx_callback(void *data, int error, unsigned int count) +{ + struct mxc_spdif_stream *s; + struct snd_pcm_substream *substream; + struct snd_pcm_runtime *runtime; + unsigned int dma_size; + unsigned int previous_period; + unsigned int offset; + + s = data; + substream = s->stream; + runtime = substream->runtime; + previous_period = s->periods; + dma_size = frames_to_bytes(runtime, runtime->period_size); + offset = dma_size * previous_period; + + spin_lock(&s->dma_lock); + s->periods++; + s->periods %= runtime->periods; + + dma_unmap_single(NULL, runtime->dma_addr + offset, dma_size, + DMA_FROM_DEVICE); + spin_unlock(&s->dma_lock); + + if (s->active) + snd_pcm_period_elapsed(s->stream); + spin_lock(&s->dma_lock); + spdif_start_rx(s); + spin_unlock(&s->dma_lock); +} + +/*! + * This function is a dispatcher of command to be executed + * by the driver for capture. + * + * @param substream pointer to the structure of the current stream. + * @param cmd command to be executed + * + * @return 0 on success, -1 otherwise. + */ +static int +snd_mxc_spdif_capture_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct mxc_spdif_device *chip; + struct mxc_spdif_stream *s; + int err = 0; + unsigned long flags; + chip = snd_pcm_substream_chip(substream); + s = &chip->s[SNDRV_PCM_STREAM_CAPTURE]; + + spin_lock_irqsave(&s->dma_lock, flags); + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + s->active = 1; + spdif_start_rx(s); + break; + case SNDRV_PCM_TRIGGER_STOP: + spdif_stop_rx(s); + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + s->active = 0; + s->periods = 0; + break; + case SNDRV_PCM_TRIGGER_RESUME: + s->active = 1; + spdif_start_rx(s); + break; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + s->active = 0; + break; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + s->active = 1; + spdif_start_rx(s); + break; + default: + err = -EINVAL; + break; + } + spin_unlock_irqrestore(&s->dma_lock, flags); + return err; +} + +/*! + * This function configures the hardware to allow audio + * capture operations. It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_spdif_capture_prepare(struct snd_pcm_substream *substream) +{ + struct mxc_spdif_device *chip; + struct mxc_spdif_platform_data *spdif_data; + struct snd_pcm_runtime *runtime; + int err; + + chip = snd_pcm_substream_chip(substream); + runtime = substream->runtime; + spdif_data = chip->card->dev->platform_data; + + spdif_rx_init(); + /* enable interrupts, include DPLL lock */ + spdif_intr_enable(INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | + INT_URX_OV | INT_QRX_FUL | INT_QRX_OV | + INT_UQ_SYNC | INT_UQ_ERR | INT_RX_RESYNC | + INT_LOSS_LOCK, 1); + + /* setup rx clock source */ + spdif_set_rx_clksrc(spdif_data->spdif_clkid, SPDIF_DEFAULT_GAINSEL, 1); + + /* setup DMA controller for spdif rx */ + err = spdif_configure_dma_channel(&chip-> + s[SNDRV_PCM_STREAM_CAPTURE], + spdif_rx_callback); + if (err < 0) { + pr_info("snd_mxc_spdif_playback_prepare - err < 0\n"); + return err; + } + + /* Debug: dump registers */ + pr_debug("SCR: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SCR)); + pr_debug("SIE: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIE)); + pr_debug("SRPC: 0x%08x\n", + __raw_readl(spdif_base_addr + SPDIF_REG_SRPC)); + pr_debug("FreqMeas: 0x%08x\n", + __raw_readl(spdif_base_addr + SPDIF_REG_SRFM)); + + return 0; +} + +/*! + * This function gets the current capture pointer position. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + */ +static snd_pcm_uframes_t +snd_mxc_spdif_capture_pointer(struct snd_pcm_substream *substream) +{ + struct mxc_spdif_device *chip; + chip = snd_pcm_substream_chip(substream); + return spdif_get_dma_pos(&chip->s[SNDRV_PCM_STREAM_CAPTURE]); +} + +/*! + * This function opens a spdif device in capture mode + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_card_mxc_spdif_capture_open(struct snd_pcm_substream *substream) +{ + struct mxc_spdif_device *chip; + struct snd_pcm_runtime *runtime; + int err = 0; + struct mxc_spdif_platform_data *spdif_data; + + chip = snd_pcm_substream_chip(substream); + + spdif_data = chip->card->dev->platform_data; + /* enable rx bus clock */ + clk_enable(spdif_data->spdif_clk); + + runtime = substream->runtime; + chip->s[SNDRV_PCM_STREAM_CAPTURE].stream = substream; + runtime->hw = snd_spdif_capture_hw; + + /* set hw param constraints */ + err = snd_pcm_hw_constraint_list(runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &hw_capture_rates_stereo); + if (err < 0) + goto failed; + err = + snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); + if (err < 0) + goto failed; + + /* enable spdif dpll lock interrupt */ + spdif_intr_enable(INT_DPLL_LOCKED, 1); + + return 0; + + failed: + clk_disable(spdif_data->spdif_clk); + return err; +} + +/*! + * This function closes an spdif device for capture. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_card_mxc_spdif_capture_close(struct snd_pcm_substream + *substream) +{ + struct mxc_spdif_device *chip; + struct mxc_spdif_platform_data *spdif_data; + + chip = snd_pcm_substream_chip(substream); + spdif_data = chip->card->dev->platform_data; + + pr_debug("SIS: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIS)); + pr_debug("SRPC: 0x%08x\n", + __raw_readl(spdif_base_addr + SPDIF_REG_SRPC)); + pr_debug("FreqMeas: 0x%08x\n", + __raw_readl(spdif_base_addr + SPDIF_REG_SRFM)); + + spdif_intr_enable(INT_DPLL_LOCKED | INT_SYM_ERR | INT_BIT_ERR | + INT_URX_FUL | INT_URX_OV | INT_QRX_FUL | INT_QRX_OV | + INT_UQ_SYNC | INT_UQ_ERR | INT_RX_RESYNC | + INT_LOSS_LOCK, 0); + spdif_rx_uninit(); + clk_disable(spdif_data->spdif_clk); + mxc_dma_free(chip->s[SNDRV_PCM_STREAM_CAPTURE].dma_wchannel); + chip->s[SNDRV_PCM_STREAM_CAPTURE].dma_wchannel = 0; + return 0; +} + +/*! + * This function configure the Audio HW in terms of memory allocation. + * It is called by ALSA framework. + * + * @param substream pointer to the structure of the current stream. + * @param hw_params Pointer to hardware paramters structure + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_spdif_hw_params(struct snd_pcm_substream + *substream, struct snd_pcm_hw_params + *hw_params) +{ + struct snd_pcm_runtime *runtime; + int ret = 0; + runtime = substream->runtime; + ret = + snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); + if (ret < 0) { + pr_info("snd_mxc_spdif_hw_params - ret: %d\n", ret); + return ret; + } + runtime->dma_addr = virt_to_phys(runtime->dma_area); + spdif_dma_enable(SCR_DMA_TX_EN, 1); + + return ret; +} + +/*! + * This function frees the spdif hardware at the end of playback. + * + * @param substream pointer to the structure of the current stream. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_mxc_spdif_hw_free(struct snd_pcm_substream *substream) +{ + return snd_pcm_lib_free_pages(substream); +} + +/*! + * This structure is the list of operation that the driver + * must provide for the playback interface + */ +static struct snd_pcm_ops snd_card_mxc_spdif_playback_ops = { + .open = snd_card_mxc_spdif_playback_open, + .close = snd_card_mxc_spdif_playback_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_mxc_spdif_hw_params, + .hw_free = snd_mxc_spdif_hw_free, + .prepare = snd_mxc_spdif_playback_prepare, + .trigger = snd_mxc_spdif_playback_trigger, + .pointer = snd_mxc_spdif_playback_pointer, +}; + +static struct snd_pcm_ops snd_card_mxc_spdif_capture_ops = { + .open = snd_card_mxc_spdif_capture_open, + .close = snd_card_mxc_spdif_capture_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = snd_mxc_spdif_hw_params, + .hw_free = snd_mxc_spdif_hw_free, + .prepare = snd_mxc_spdif_capture_prepare, + .trigger = snd_mxc_spdif_capture_trigger, + .pointer = snd_mxc_spdif_capture_pointer, +}; + +/*! + * This functions initializes the playback audio device supported by + * spdif + * + * @param mxc_spdif pointer to the sound card structure. + * + */ +void mxc_init_spdif_device(struct mxc_spdif_device *mxc_spdif) +{ + + /* initial spinlock for control data */ + spin_lock_init(&mxc_spdif_control.ctl_lock); + + if (mxc_spdif->mxc_spdif_tx) { + + mxc_spdif->s[SNDRV_PCM_STREAM_PLAYBACK].id = "spdif tx"; + /* init tx channel status default value */ + mxc_spdif_control.ch_status[0] = + IEC958_AES0_CON_NOT_COPYRIGHT | + IEC958_AES0_CON_EMPHASIS_5015; + mxc_spdif_control.ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; + mxc_spdif_control.ch_status[2] = 0x00; + mxc_spdif_control.ch_status[3] = + IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM; + } + if (mxc_spdif->mxc_spdif_rx) { + + /* TODO: Add code here if capture is available */ + mxc_spdif->s[SNDRV_PCM_STREAM_CAPTURE].id = "spdif rx"; + } + +} + +/*! + * MXC SPDIF IEC958 controller(mixer) functions + * + * Channel status get/put control + * User bit value get/put control + * Valid bit value get control + * DPLL lock status get control + * User bit sync mode selection control + * + */ +static int mxc_pb_spdif_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; + uinfo->count = 1; + return 0; +} + +static int mxc_pb_spdif_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + uvalue->value.iec958.status[0] = mxc_spdif_control.ch_status[0]; + uvalue->value.iec958.status[1] = mxc_spdif_control.ch_status[1]; + uvalue->value.iec958.status[2] = mxc_spdif_control.ch_status[2]; + uvalue->value.iec958.status[3] = mxc_spdif_control.ch_status[3]; + return 0; +} + +static int mxc_pb_spdif_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uvalue) +{ + unsigned int ch_status; + mxc_spdif_control.ch_status[0] = uvalue->value.iec958.status[0]; + mxc_spdif_control.ch_status[1] = uvalue->value.iec958.status[1]; + mxc_spdif_control.ch_status[2] = uvalue->value.iec958.status[2]; + mxc_spdif_control.ch_status[3] = uvalue->value.iec958.status[3]; + ch_status = + ((mxc_spdif_control.ch_status[2] << 16) | (mxc_spdif_control. + ch_status[1] << 8) | + mxc_spdif_control.ch_status[0]); + spdif_set_channel_status(ch_status, SPDIF_REG_STCSCH); + ch_status = mxc_spdif_control.ch_status[3]; + spdif_set_channel_status(ch_status, SPDIF_REG_STCSCL); + return 0; +} + +static int snd_mxc_spdif_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; + uinfo->count = 1; + return 0; +} + +/*! + * Get channel status from SPDIF_RX_CCHAN register + */ +static int snd_mxc_spdif_capture_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int cstatus; + + if (!(__raw_readl(spdif_base_addr + SPDIF_REG_SIS) & INT_CNEW)) + return -EAGAIN; + + cstatus = __raw_readl(spdif_base_addr + SPDIF_REG_SRCSLH); + ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; + ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; + ucontrol->value.iec958.status[2] = cstatus & 0xFF; + cstatus = __raw_readl(spdif_base_addr + SPDIF_REG_SRCSLL); + ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; + ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; + ucontrol->value.iec958.status[5] = cstatus & 0xFF; + + /* clear intr */ + __raw_writel(INT_CNEW, spdif_base_addr + SPDIF_REG_SIC); + + return 0; +} + +/*! + * Get User bits (subcode) from chip value which readed out + * in UChannel register. + */ +static int snd_mxc_spdif_subcode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&mxc_spdif_control.ctl_lock, flags); + if (mxc_spdif_control.ready_buf) { + memcpy(&ucontrol->value.iec958.subcode[0], + &mxc_spdif_control. + subcode[(mxc_spdif_control.ready_buf - + 1) * SPDIF_UBITS_SIZE], SPDIF_UBITS_SIZE); + } else { + ret = -EAGAIN; + } + spin_unlock_irqrestore(&mxc_spdif_control.ctl_lock, flags); + + return ret; +} + +/*! + * Q-subcode infomation. + * the byte size is SPDIF_UBITS_SIZE/8 + */ +static int snd_mxc_spdif_qinfo(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = SPDIF_QSUB_SIZE; + return 0; +} + +/*! + * Get Q subcode from chip value which readed out + * in QChannel register. + */ +static int snd_mxc_spdif_qget(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&mxc_spdif_control.ctl_lock, flags); + if (mxc_spdif_control.ready_buf) { + memcpy(&ucontrol->value.bytes.data[0], + &mxc_spdif_control. + qsub[(mxc_spdif_control.ready_buf - + 1) * SPDIF_QSUB_SIZE], SPDIF_QSUB_SIZE); + } else { + ret = -EAGAIN; + } + spin_unlock_irqrestore(&mxc_spdif_control.ctl_lock, flags); + + return ret; +} + +/*! + * Valid bit infomation. + */ +static int snd_mxc_spdif_vbit_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + return 0; +} + +/*! + * Get valid good bit from interrupt status register. + */ +static int snd_mxc_spdif_vbit_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int int_val; + + int_val = __raw_readl(spdif_base_addr + SPDIF_REG_SIS); + ucontrol->value.integer.value[0] = (int_val & INT_VAL_NOGOOD) != 0; + __raw_writel(INT_VAL_NOGOOD, spdif_base_addr + SPDIF_REG_SIC); + + return 0; +} + +/*! + * DPLL lock infomation. + */ +static int snd_mxc_spdif_rxrate_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 16000; + uinfo->value.integer.max = 96000; + return 0; +} + +/*! + * Get DPLL lock or not info from stable interrupt status register. + * User application must use this control to get locked, + * then can do next PCM operation + */ +static int snd_mxc_spdif_rxrate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct mxc_spdif_device *chip = snd_kcontrol_chip(kcontrol); + struct mxc_spdif_platform_data *spdif_data; + + spdif_data = chip->card->dev->platform_data; + + if (atomic_read(&chip->dpll_locked)) { + ucontrol->value.integer.value[0] = + spdif_get_rxclk_rate(spdif_data->spdif_clk, + SPDIF_DEFAULT_GAINSEL); + } else { + ucontrol->value.integer.value[0] = 0; + } + return 0; +} + +/*! + * User bit sync mode info + */ +static int snd_mxc_spdif_usync_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + return 0; +} + +/*! + * User bit sync mode: + * 1 CD User channel subcode + * 0 Non-CD data + */ +static int snd_mxc_spdif_usync_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int int_val; + + int_val = __raw_readl(spdif_base_addr + SPDIF_REG_SRCD); + ucontrol->value.integer.value[0] = (int_val & SRCD_CD_USER) != 0; + return 0; +} + +/*! + * User bit sync mode: + * 1 CD User channel subcode + * 0 Non-CD data + */ +static int snd_mxc_spdif_usync_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int int_val; + + int_val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; + __raw_writel(int_val, spdif_base_addr + SPDIF_REG_SRCD); + return 0; +} + +/*! + * MXC SPDIF IEC958 controller defines + */ +static struct snd_kcontrol_new snd_mxc_spdif_ctrls[] = { + /* status cchanel controller */ + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), + .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | + SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = mxc_pb_spdif_info, + .get = mxc_pb_spdif_get, + .put = mxc_pb_spdif_put, + }, + { + .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), + .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = snd_mxc_spdif_info, + .get = snd_mxc_spdif_capture_get, + }, + /* user bits controller */ + { + .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .name = "IEC958 Subcode Capture Default", + .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = snd_mxc_spdif_info, + .get = snd_mxc_spdif_subcode_get, + }, + { + .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .name = "IEC958 Q-subcode Capture Default", + .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = snd_mxc_spdif_qinfo, + .get = snd_mxc_spdif_qget, + }, + /* valid bit error controller */ + { + .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .name = "IEC958 V-Bit Errors", + .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = snd_mxc_spdif_vbit_info, + .get = snd_mxc_spdif_vbit_get, + }, + /* DPLL lock info get controller */ + { + .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .name = "RX Sample Rate", + .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = snd_mxc_spdif_rxrate_info, + .get = snd_mxc_spdif_rxrate_get, + }, + /* User bit sync mode set/get controller */ + { + .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .name = "IEC958 USyncMode CDText", + .access = + SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | + SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = snd_mxc_spdif_usync_info, + .get = snd_mxc_spdif_usync_get, + .put = snd_mxc_spdif_usync_put, + }, +}; + +/*! + * This function the soundcard structure. + * + * @param mxc_spdif pointer to the sound card structure. + * + * @return 0 on success, -1 otherwise. + */ +static int snd_card_mxc_spdif_pcm(struct mxc_spdif_device *mxc_spdif) +{ + struct snd_pcm *pcm; + int err; + err = snd_pcm_new(mxc_spdif->card, MXC_SPDIF_NAME, 0, + mxc_spdif->mxc_spdif_tx, + mxc_spdif->mxc_spdif_rx, &pcm); + if (err < 0) + return err; + + snd_pcm_lib_preallocate_pages_for_all(pcm, + SNDRV_DMA_TYPE_CONTINUOUS, + snd_dma_continuous_data + (GFP_KERNEL), + SPDIF_MAX_BUF_SIZE * 2, + SPDIF_MAX_BUF_SIZE * 2); + if (mxc_spdif->mxc_spdif_tx) + snd_pcm_set_ops(pcm, + SNDRV_PCM_STREAM_PLAYBACK, + &snd_card_mxc_spdif_playback_ops); + if (mxc_spdif->mxc_spdif_rx) + snd_pcm_set_ops(pcm, + SNDRV_PCM_STREAM_CAPTURE, + &snd_card_mxc_spdif_capture_ops); + pcm->private_data = mxc_spdif; + pcm->info_flags = 0; + strncpy(pcm->name, MXC_SPDIF_NAME, sizeof(pcm->name)); + mxc_spdif->pcm = pcm; + mxc_init_spdif_device(mxc_spdif); + return 0; +} + +extern void gpio_spdif_active(void); + +/*! + * This function initializes the driver in terms of memory of the soundcard + * and some basic HW clock settings. + * + * @param pdev Pointer to the platform device + * @return 0 on success, -1 otherwise. + */ +static int mxc_alsa_spdif_probe(struct platform_device + *pdev) +{ + int err, idx, irq; + static int dev; + struct snd_card *card; + struct mxc_spdif_device *chip; + struct resource *res; + struct snd_kcontrol *kctl; + struct mxc_spdif_platform_data *plat_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENOENT; + + if (dev >= SNDRV_CARDS) + return -ENODEV; + if (!enable[dev]) { + dev++; + return -ENOENT; + } + + /* register the soundcard */ + err = snd_card_create(index[dev], id[dev], THIS_MODULE, + sizeof(struct mxc_spdif_device), &card); + if (err < 0) + return err; + chip = card->private_data; + chip->card = card; + card->dev = &pdev->dev; + chip->reg_phys_base = res->start; + chip->reg_base = ioremap(res->start, res->end - res->start + 1); + spdif_base_addr = (unsigned long)chip->reg_base; + plat_data = (struct mxc_spdif_platform_data *)pdev->dev.platform_data; + chip->mxc_spdif_tx = plat_data->spdif_tx; + chip->mxc_spdif_rx = plat_data->spdif_rx; + chip->spdif_txclk_44100 = plat_data->spdif_clk_44100; + chip->spdif_txclk_48000 = plat_data->spdif_clk_48000; + if ((chip->spdif_txclk_44100 == 1) || + (chip->spdif_txclk_48000 == 1)) { + /*spdif0_clk used as clk src*/ + struct clk *spdif_clk; + spdif_clk = clk_get(&pdev->dev, NULL); + clk_enable(spdif_clk); + } + atomic_set(&chip->dpll_locked, 0); + + err = snd_card_mxc_spdif_pcm(chip); + if (err < 0) + goto nodev; + + /*! + * Add controls to the card + */ + for (idx = 0; idx < ARRAY_SIZE(snd_mxc_spdif_ctrls); idx++) { + + kctl = snd_ctl_new1(&snd_mxc_spdif_ctrls[idx], chip); + if (kctl == NULL) { + err = -ENOMEM; + goto nodev; + } + /* check to add control to corresponding substream */ + if (strstr(kctl->id.name, "Playback")) + kctl->id.device = 0; + else + kctl->id.device = 1; + + err = snd_ctl_add(card, kctl); + if (err < 0) + goto nodev; + } + + clk_enable(plat_data->spdif_core_clk); + /*! + * SPDIF interrupt initialization + * software reset to SPDIF + */ + spdif_softreset(); + /* disable all the interrupts */ + spdif_intr_enable(0xffffff, 0); + /* spdif interrupt register and disable */ + irq = platform_get_irq(pdev, 0); + if ((irq <= 0) || request_irq(irq, spdif_isr, 0, "spdif", chip)) { + pr_err("MXC spdif: failed to request irq\n"); + err = -EBUSY; + goto nodev; + } + + if (chip->mxc_spdif_tx) + spin_lock_init(&chip->s[SNDRV_PCM_STREAM_PLAYBACK].dma_lock); + if (chip->mxc_spdif_rx) + spin_lock_init(&chip->s[SNDRV_PCM_STREAM_CAPTURE].dma_lock); + strcpy(card->driver, MXC_SPDIF_NAME); + strcpy(card->shortname, "MXC SPDIF TX/RX"); + sprintf(card->longname, "MXC Freescale with SPDIF"); + + err = snd_card_register(card); + if (err == 0) { + pr_info("MXC spdif support initialized\n"); + platform_set_drvdata(pdev, card); + gpio_spdif_active(); + return 0; + } + + nodev: + snd_card_free(card); + return err; +} + +extern void gpio_spdif_inactive(void); + +/*! + * This function releases the sound card and unmap the io address + * + * @param pdev Pointer to the platform device + * @return 0 on success, -1 otherwise. + */ + +static int mxc_alsa_spdif_remove(struct platform_device *pdev) +{ + struct mxc_spdif_device *chip; + struct snd_card *card; + struct mxc_spdif_platform_data *plat_data; + + card = platform_get_drvdata(pdev); + plat_data = pdev->dev.platform_data; + chip = card->private_data; + free_irq(platform_get_irq(pdev, 0), chip); + iounmap(chip->reg_base); + + snd_card_free(card); + platform_set_drvdata(pdev, NULL); + + clk_disable(plat_data->spdif_core_clk); + gpio_spdif_inactive(); + + return 0; +} + +#ifdef CONFIG_PM +/*! + * This function suspends all active streams. + * + * TBD + * + * @param card pointer to the sound card structure. + * @param state requested state + * + * @return 0 on success, -1 otherwise. + */ +static int mxc_alsa_spdif_suspend(struct platform_device *pdev, + pm_message_t state) +{ + return 0; +} + +/*! + * This function resumes all suspended streams. + * + * TBD + * + * @param card pointer to the sound card structure. + * @param state requested state + * + * @return 0 on success, -1 otherwise. + */ +static int mxc_alsa_spdif_resume(struct platform_device *pdev) +{ + return 0; +} +#endif + +static struct platform_driver mxc_alsa_spdif_driver = { + .probe = mxc_alsa_spdif_probe, + .remove = mxc_alsa_spdif_remove, +#ifdef CONFIG_PM + .suspend = mxc_alsa_spdif_suspend, + .resume = mxc_alsa_spdif_resume, +#endif + .driver = { + .name = "mxc_alsa_spdif", + }, +}; + +/*! + * This function registers the sound driver structure. + * + */ +static int __init mxc_alsa_spdif_init(void) +{ + return platform_driver_register(&mxc_alsa_spdif_driver); +} + +/*! + * This function frees the sound driver structure. + * + */ +static void __exit mxc_alsa_spdif_exit(void) +{ + platform_driver_unregister(&mxc_alsa_spdif_driver); +} + +module_init(mxc_alsa_spdif_init); +module_exit(mxc_alsa_spdif_exit); +MODULE_AUTHOR("FREESCALE SEMICONDUCTOR"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MXC ALSA driver for SPDIF"); diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index b1749bc67979..e2b2406ab8e7 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -36,6 +36,7 @@ source "sound/soc/s3c24xx/Kconfig" source "sound/soc/s6000/Kconfig" source "sound/soc/sh/Kconfig" source "sound/soc/txx9/Kconfig" +source "sound/soc/mxs/Kconfig" # Supported codecs source "sound/soc/codecs/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 1470141d4167..6f3109485742 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_SND_SOC) += s3c24xx/ obj-$(CONFIG_SND_SOC) += s6000/ obj-$(CONFIG_SND_SOC) += sh/ obj-$(CONFIG_SND_SOC) += txx9/ +obj-$(CONFIG_SND_SOC) += mxs/ diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 5da30eb6ad00..5b8b951537c4 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -23,6 +23,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_AK4671 if I2C select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC select SND_SOC_CS4270 if I2C + select SND_SOC_CS42888 if I2C select SND_SOC_MAX9877 if I2C select SND_SOC_DA7210 if I2C select SND_SOC_PCM3008 @@ -117,6 +118,10 @@ config SND_SOC_AK4642 config SND_SOC_AK4671 tristate +config SND_SOC_AK5702 + tristate + depends on I2C + config SND_SOC_CQ0093VC tristate @@ -138,6 +143,9 @@ config SND_SOC_CS4270_VD33_ERRATA config SND_SOC_CX20442 tristate +config SND_SOC_CS42888 + tristate + config SND_SOC_L3 tristate @@ -269,6 +277,23 @@ config SND_SOC_WM9712 config SND_SOC_WM9713 tristate +config SND_SOC_SGTL5000 + tristate + depends on I2C + +config SND_SOC_AK4647 + tristate + depends on I2C + +config SND_SOC_MXS_ADC_CODEC + tristate + +config SND_SOC_BLUETOOTH + tristate + +config SND_SOC_MXS_SPDIF + tristate + # Amp config SND_SOC_MAX9877 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 91429eab0707..4c0ade6bd995 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -10,6 +10,7 @@ snd-soc-ak4642-objs := ak4642.o snd-soc-ak4671-objs := ak4671.o snd-soc-cq93vc-objs := cq93vc.o snd-soc-cs4270-objs := cs4270.o +snd-soc-cs42888-objs := cs42888.o snd-soc-cx20442-objs := cx20442.o snd-soc-da7210-objs := da7210.o snd-soc-l3-objs := l3.o @@ -56,6 +57,12 @@ snd-soc-wm9705-objs := wm9705.o snd-soc-wm9712-objs := wm9712.o snd-soc-wm9713-objs := wm9713.o snd-soc-wm-hubs-objs := wm_hubs.o +snd-soc-sgtl5000-objs := sgtl5000.o +snd-soc-ak4647-objs := ak4647.o +snd-soc-ak5702-objs := ak5702.o +snd-soc-bluetooth-objs := bluetooth.o +snd-soc-mxs-spdif-objs := mxs_spdif.o +snd-soc-mxs-adc-objs := mxs-adc-codec.o # Amp snd-soc-max9877-objs := max9877.o @@ -75,6 +82,7 @@ obj-$(CONFIG_SND_SOC_AK4642) += snd-soc-ak4642.o obj-$(CONFIG_SND_SOC_AK4671) += snd-soc-ak4671.o obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o +obj-$(CONFIG_SND_SOC_CS42888) += snd-soc-cs42888.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o @@ -121,6 +129,12 @@ obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o +obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o +obj-$(CONFIG_SND_SOC_AK4647) += snd-soc-ak4647.o +obj-$(CONFIG_SND_SOC_AK5702) += snd-soc-ak5702.o +obj-$(CONFIG_SND_SOC_BLUETOOTH) += snd-soc-bluetooth.o +obj-$(CONFIG_SND_SOC_MXS_SPDIF) += snd-soc-mxs-spdif.o +obj-$(CONFIG_SND_SOC_MXS_ADC_CODEC) += snd-soc-mxs-adc.o # Amp obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o diff --git a/sound/soc/codecs/ak4647.c b/sound/soc/codecs/ak4647.c new file mode 100644 index 000000000000..98865daf772a --- /dev/null +++ b/sound/soc/codecs/ak4647.c @@ -0,0 +1,800 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ak4647.c + * @brief Driver for AK4647 + * + * @ingroup Sound + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "ak4647.h" + +#define SET_BIT_IN_BYTE(byte, pos) (byte |= (0x01 << pos)) +#define CLEAR_BIT_IN_BYTE(byte, pos) (byte &= ~(0x01 << pos)) + +static struct i2c_client *ak4647_i2c_client; + +int ak4647_read_reg(unsigned int reg, u8 *value) +{ + s32 retval; + retval = i2c_smbus_read_byte_data(ak4647_i2c_client, reg); + if (retval < 0) { + pr_err("%s:read reg errorr:reg=%x,val=%x\n", + __func__, reg, retval); + return -1; + } else { + *value = (u8) retval; + return 0; + } +} + +int ak4647_write_reg(unsigned int reg, u8 value) +{ + if (i2c_smbus_write_byte_data(ak4647_i2c_client, reg, value) < 0) { + pr_err("%s:write reg errorr:reg=%x,val=%x\n", + __func__, reg, value); + return -1; + } + return 0; +} + +static unsigned int ak4647_codec_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 value; + ak4647_read_reg(reg, &value); + return value; +} + +static int ak4647_codec_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + return ak4647_write_reg(reg, value); +} + +#define DEBUG_AK4647 0 + +#if DEBUG_AK4647 + +static char *ak4647_reg_names[] = { + "AK4647_PM1", + "AK4647_PM2", + "AK4647_SIG1", + "AK4647_SIG2", + "AK4647_MODE1", + "AK4647_MODE2", + "AK4647_TIMER", + "AK4647_ALC1", + "AK4647_ALC2", + "AK4647_LEFT_INPUT_VOLUME", + "AK4647_LEFT_DGT_VOLUME", + "AK4647_ALC3", + "AK4647_RIGHT_INPUT_VOLUME", + "AK4647_RIGHT_DGT_VOLUME", + "AK4647_MODE3", + "AK4647_MODE4", + "AK4647_PM3", + "AK4647_DGT_FIL_SEL", + "AK4647_FIL3_COEF0", + "AK4647_FIL3_COEF1", + "AK4647_FIL3_COEF2", + "AK4647_FIL3_COEF3", + "AK4647_EQ_COEF0", + "AK4647_EQ_COEF1", + "AK4647_EQ_COEF2", + "AK4647_EQ_COEF3", + "AK4647_EQ_COEF4", + "AK4647_EQ_COEF5", + "AK4647_FIL1_COEF0", + "AK4647_FIL1_COEF1", + "AK4647_FIL1_COEF2", + "AK4647_FIL1_COEF3", +}; + +static void dump_all_regs(void) +{ + int i; + u8 value; + + for (i = AK4647_REG_START; i < AK4647_REG_NUMBER; i++) { + ak4647_read_reg(i, &value); + pr_info("%s = 0x%x\n", ak4647_reg_names[i], value); + } +} +#endif + +static int loopback_xhandle_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +static int loopback_xhandle_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +static const char *ak4647_hp_out[] = { "Stereo", "Mono" }; + +static const char *ak4647_left_in[] = { "LIN1", "LIN2" }; + +static const char *ak4647_right_in[] = { "RIN1", "RIN2" }; + +static const char *ak4647_deemp[] = { "44.1kHz", "Off", "48kHz", "32kHz" }; + +static const struct soc_enum ak4647_enum[] = { + SOC_ENUM_SINGLE(AK4647_MODE4, 2, 2, ak4647_hp_out), + SOC_ENUM_SINGLE(AK4647_MODE3, 0, 4, ak4647_deemp), + SOC_ENUM_SINGLE(AK4647_PM3, 1, 2, ak4647_left_in), + SOC_ENUM_SINGLE(AK4647_PM3, 2, 2, ak4647_right_in), +}; + +#undef snd_soc_info_bool_ext +#define snd_soc_info_bool_ext snd_ctl_boolean_mono_info +static const struct snd_kcontrol_new ak4647_snd_controls[] = { + SOC_ENUM("Headphone Output", ak4647_enum[0]), + SOC_ENUM("Playback Deemphasis", ak4647_enum[1]), + SOC_ENUM("Left Capture Select", ak4647_enum[2]), + SOC_ENUM("Right Capture Select", ak4647_enum[3]), + SOC_SINGLE("Bass Volume", AK4647_MODE3, 2, 3, 0), + SOC_SINGLE("Mic Boost (+20dB) Switch", AK4647_SIG1, 0, 1, 0), + SOC_SINGLE("Mic Bias", AK4647_SIG1, 2, 1, 0), + SOC_SINGLE("ALC Switch", AK4647_ALC1, 5, 1, 0), + SOC_SINGLE("ALC Recovery Time", AK4647_TIMER, 2, 3, 0), + SOC_SINGLE("ALC ZC Time", AK4647_TIMER, 4, 3, 0), + SOC_SINGLE("ALC Volume", AK4647_ALC2, 0, 127, 0), + SOC_SINGLE("Left Capture Volume", AK4647_LEFT_INPUT_VOLUME, 0, 242, 0), + SOC_SINGLE("Right Capture Volume", + AK4647_RIGHT_INPUT_VOLUME, 0, 242, 0), + SOC_SINGLE("Left Playback Volume", AK4647_LEFT_DGT_VOLUME, 0, 255, 1), + SOC_SINGLE("Right Playback Volume", AK4647_RIGHT_DGT_VOLUME, 0, 255, 1), + SOC_SINGLE_BOOL_EXT("Loopback Line-in", 0, + loopback_xhandle_get, loopback_xhandle_put), +}; + +/* Stereo Mixer for HP*/ +static const struct snd_kcontrol_new ak4647_hp_stereo_mixer_controls[] = { + SOC_DAPM_SINGLE("Playback Switch", AK4647_MODE4, 0, 1, 0), + SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4647_MODE4, 1, 1, 0), +}; + +/* Stereo Mixer for Line out*/ +static const struct snd_kcontrol_new ak4647_line_stereo_mixer_controls[] = { + SOC_DAPM_SINGLE("Playback Switch", AK4647_SIG1, 4, 1, 0), + SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4647_SIG2, 2, 1, 0), +}; + +/* ak4647 dapm widgets */ +static const struct snd_soc_dapm_widget ak4647_dapm_widgets[] = { + SND_SOC_DAPM_MIXER("Headphone Mixer", SND_SOC_NOPM, 0, 0, + &ak4647_hp_stereo_mixer_controls[0], + ARRAY_SIZE(ak4647_hp_stereo_mixer_controls)), + SND_SOC_DAPM_MIXER("Lineout Mixer", SND_SOC_NOPM, 0, 0, + &ak4647_line_stereo_mixer_controls[0], + ARRAY_SIZE(ak4647_line_stereo_mixer_controls)), + SND_SOC_DAPM_DAC("DAC", "Playback", AK4647_PM1, 2, 0), + SND_SOC_DAPM_OUTPUT("HPL"), + SND_SOC_DAPM_OUTPUT("HPR"), + SND_SOC_DAPM_OUTPUT("LOUT"), + + SND_SOC_DAPM_ADC("Left ADC", "Capture", AK4647_PM1, 0, 0), + SND_SOC_DAPM_ADC("Right ADC", "Capture", AK4647_PM3, 0, 0), + SND_SOC_DAPM_PGA("HP R Amp", AK4647_PM2, 4, 0, NULL, 0), + SND_SOC_DAPM_PGA("HP L Amp", AK4647_PM2, 5, 0, NULL, 0), + SND_SOC_DAPM_PGA("Mic", AK4647_PM1, 5, 0, NULL, 0), + SND_SOC_DAPM_PGA("Line Out Amp", AK4647_PM1, 3, 0, NULL, 0), + + SND_SOC_DAPM_MICBIAS("Mic Bias", AK4647_SIG1, 2, 0), + SND_SOC_DAPM_INPUT("Left Input"), + SND_SOC_DAPM_INPUT("Right Input"), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /*headphone stereo mixer */ + {"Headphone Mixer", "Playback Switch", "DAC"}, + {"Headphone Mixer", "Mic Sidetone Switch", "Mic"}, + + /*lineout stereo mixer */ + {"Lineout Mixer", "Playback Switch", "DAC"}, + {"Lineout Mixer", "Mic Sidetone Switch", "Mic"}, + + /* headphone amp */ + {"HP R Amp", NULL, "Headphone Mixer"}, + {"HP L Amp", NULL, "Headphone Mixer"}, + + /* headphone */ + {"HPR", NULL, "HP R Amp"}, + {"HPL", NULL, "HP L Amp"}, + + /* line out */ + {"Line Out Amp", NULL, "Lineout Mixer"}, + {"LOUT", NULL, "Line Out Amp"}, + + /* ADC */ + {"Left ADC", NULL, "Left Input"}, + {"Right ADC", NULL, "Right Input"}, + +}; + +static int ak4647_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, ak4647_dapm_widgets, + ARRAY_SIZE(ak4647_dapm_widgets)); + + /* set up audio path audio_mapnects */ + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +#define AK4647_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_48000) + +#define AK4647_FORMATS SNDRV_PCM_FMTBIT_S16_LE + +static int ak4647_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + u8 value; + u8 fs = 0; + + /* FS3 is on D5 */ + switch (freq) { + case 8000: + fs = 0x0; + break; + case 11025: + fs = 0x5; + break; + case 16000: + fs = 0x2; + break; + case 22050: + fs = 0x7; + break; + case 32000: + fs = 0x22; + break; + case 44100: + fs = 0x27; + break; + case 48000: + fs = 0x23; + break; + default: + pr_err("unsupported sample rate"); + return -1; + } + + ak4647_read_reg(AK4647_MODE2, &value); + value &= 0xC0; + value |= fs; + ak4647_write_reg(AK4647_MODE2, value); + return 0; +} + +static int ak4647_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + u8 reg_mode1, reg_pm2; + + /* get current values */ + ak4647_read_reg(AK4647_MODE1, ®_mode1); + ak4647_read_reg(AK4647_PM2, ®_pm2); + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + SET_BIT_IN_BYTE(reg_pm2, 3); + break; + case SND_SOC_DAIFMT_CBS_CFS: + CLEAR_BIT_IN_BYTE(reg_pm2, 3); + break; + default: + return -EINVAL; + } + + /* interface format */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + SET_BIT_IN_BYTE(reg_mode1, 0); + SET_BIT_IN_BYTE(reg_mode1, 1); + break; + case SND_SOC_DAIFMT_RIGHT_J: + SET_BIT_IN_BYTE(reg_mode1, 0); + CLEAR_BIT_IN_BYTE(reg_mode1, 1); + break; + case SND_SOC_DAIFMT_LEFT_J: + CLEAR_BIT_IN_BYTE(reg_mode1, 0); + SET_BIT_IN_BYTE(reg_mode1, 1); + break; + case SND_SOC_DAIFMT_DSP_A: + case SND_SOC_DAIFMT_DSP_B: + default: + pr_err("dai format %d not supported", fmt); + return -EINVAL; + } + + ak4647_write_reg(AK4647_MODE1, reg_mode1); + ak4647_write_reg(AK4647_PM2, reg_pm2); + return 0; +} + +static int ak4647_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) +{ + int retval = 0; + u8 value; + if (AK4647_BCLK_CLKDIV == div_id) { + ak4647_read_reg(AK4647_MODE1, &value); + switch (div) { + case AK4647_BCLK_DIV_32: + CLEAR_BIT_IN_BYTE(value, 3); + ak4647_write_reg(AK4647_MODE1, value); + break; + case AK4647_BCLK_DIV_64: + SET_BIT_IN_BYTE(value, 3); + ak4647_write_reg(AK4647_MODE1, value); + break; + default: + retval = -1; + pr_err("wrong div value for divid %d", div_id); + break; + } + } else if (AK4647_MCLK_CLKDIV == div_id) { + ak4647_read_reg(AK4647_MODE2, &value); + switch (div) { + case AK4647_MCLK_DIV_32: + SET_BIT_IN_BYTE(value, 7); + SET_BIT_IN_BYTE(value, 6); + ak4647_write_reg(AK4647_MODE2, value); + break; + case AK4647_MCLK_DIV_64: + SET_BIT_IN_BYTE(value, 7); + CLEAR_BIT_IN_BYTE(value, 6); + ak4647_write_reg(AK4647_MODE2, value); + break; + case AK4647_MCLK_DIV_128: + CLEAR_BIT_IN_BYTE(value, 7); + SET_BIT_IN_BYTE(value, 6); + ak4647_write_reg(AK4647_MODE2, value); + break; + case AK4647_MCLK_DIV_256: + CLEAR_BIT_IN_BYTE(value, 7); + CLEAR_BIT_IN_BYTE(value, 6); + ak4647_write_reg(AK4647_MODE2, value); + break; + default: + retval = -1; + pr_err("wrong div value for div id %d", div_id); + break; + } + } else { + retval = -1; + pr_err("wrong div id"); + } + + return retval; +} + +static int ak4647_digital_mute(struct snd_soc_dai *dai, int mute) +{ + u8 value; + + ak4647_read_reg(AK4647_MODE3, &value); + + if (mute) + SET_BIT_IN_BYTE(value, 5); + else + CLEAR_BIT_IN_BYTE(value, 5); + ak4647_write_reg(AK4647_MODE3, value); + return 0; +} + +struct ak4647_state_data { + u8 left_capture_vol; + u8 right_capture_vol; +}; +static struct ak4647_state_data ak4647_state; + +static int ak4647_pcm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + u8 value; + /* for playback, save down capture volume */ + if (SNDRV_PCM_STREAM_PLAYBACK == substream->stream) { + ak4647_read_reg(AK4647_LEFT_INPUT_VOLUME, &value); + ak4647_state.left_capture_vol = value; + ak4647_read_reg(AK4647_RIGHT_INPUT_VOLUME, &value); + ak4647_state.right_capture_vol = value; + + /* when PMADL=PMADR=0 set IVL &IVR to be 0x91 (0db) */ + ak4647_write_reg(AK4647_LEFT_INPUT_VOLUME, 0x91); + ak4647_write_reg(AK4647_RIGHT_INPUT_VOLUME, 0x91); + } + + /* output digital volume independent */ + ak4647_read_reg(AK4647_MODE3, &value); + CLEAR_BIT_IN_BYTE(value, 4); + ak4647_write_reg(AK4647_MODE3, value); + return 0; +} + +static void ak4647_pcm_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + u8 value; + ak4647_read_reg(AK4647_PM2, &value); + /* mute */ + CLEAR_BIT_IN_BYTE(value, 6); + ak4647_write_reg(AK4647_PM2, value); + + /* after playback, restore capture volume */ + if (SNDRV_PCM_STREAM_PLAYBACK == substream->stream) { + ak4647_write_reg(AK4647_LEFT_INPUT_VOLUME, + ak4647_state.left_capture_vol); + ak4647_write_reg(AK4647_RIGHT_INPUT_VOLUME, + ak4647_state.right_capture_vol); + } +} + +static int ak4647_pcm_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + u8 value; + + /* VCOM power on */ + ak4647_write_reg(AK4647_PM1, 0x44); + msleep(30); + + ak4647_read_reg(AK4647_PM2, &value); + /* PLL enabled */ + SET_BIT_IN_BYTE(value, 0); + + ak4647_write_reg(AK4647_PM2, value); + /* wait for PLL locked */ + msleep(40); + + /* don't mute */ + SET_BIT_IN_BYTE(value, 6); + ak4647_write_reg(AK4647_PM2, value); + return 0; +} + +struct snd_soc_dai_ops ak4647_ops = { + .prepare = ak4647_pcm_prepare, + .startup = ak4647_pcm_startup, + .shutdown = ak4647_pcm_shutdown, + .digital_mute = ak4647_digital_mute, + .set_fmt = ak4647_set_dai_fmt, + .set_sysclk = ak4647_set_dai_sysclk, + .set_clkdiv = ak4647_set_clkdiv, +}; + +struct snd_soc_dai ak4647_hifi_dai = { + .name = "ak4647", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = AK4647_RATES, + .formats = AK4647_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = AK4647_RATES, + .formats = AK4647_FORMATS, + }, + .ops = &ak4647_ops, +}; +EXPORT_SYMBOL_GPL(ak4647_hifi_dai); + +static struct snd_soc_codec *ak4647_codec; + +static int ak4647_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = ak4647_codec; + int ret = 0; + + socdev->card->codec = ak4647_codec; + + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(&ak4647_i2c_client->dev, "failed to create pcms\n"); + return ret; + } + + /* setup init value for audio path controls here */ + /* enable DAC to headphone */ + ak4647_write_reg(AK4647_MODE4, 0x9); + /* capture source to be LIN2 and RIN2 */ + ak4647_write_reg(AK4647_PM3, 0x6); + /* MPWR pin up */ + ak4647_write_reg(AK4647_SIG1, 0x5); + + /* MCKI = 12M, default audio interface format as "left-justified" */ + ak4647_write_reg(AK4647_MODE1, 0x62); + + /* ALC disabled */ + ak4647_write_reg(AK4647_ALC1, 0x0); + + ak4647_state.left_capture_vol = 0x91; + ak4647_state.right_capture_vol = 0x91; + + snd_soc_add_controls(codec, ak4647_snd_controls, + ARRAY_SIZE(ak4647_snd_controls)); + ak4647_add_widgets(codec); + + ret = snd_soc_init_card(socdev); + if (ret < 0) { + pr_err("ak4647: failed to register card\n"); + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + return ret; + } + + return 0; +} + +static __devexit int ak4647_i2c_remove(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + + snd_soc_unregister_dai(&ak4647_hifi_dai); + snd_soc_unregister_codec(codec); + kfree(codec); + ak4647_codec = NULL; + return 0; +} + +static int ak4647_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct snd_soc_codec *codec; + int ret; + u8 val; + + if (ak4647_codec) { + dev_err(&client->dev, + "Multiple AK4647 devices not supported\n"); + return -ENOMEM; + } + + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + i2c_set_clientdata(client, codec); + ak4647_i2c_client = client; + codec->control_data = client; + ret = ak4647_read_reg(AK4647_REG_START, &val); + if (ret < 0) { + pr_err("Device with ID register %x is not a AK4647\n", val); + return -ENODEV; + } + + codec->dev = &client->dev; + codec->name = "ak4647", codec->owner = THIS_MODULE; + codec->owner = THIS_MODULE; + codec->read = ak4647_codec_read; + codec->write = ak4647_codec_write; + codec->dai = &ak4647_hifi_dai; + codec->num_dai = 1; + + ak4647_codec = codec; + ak4647_hifi_dai.dev = &client->dev; + + ret = snd_soc_register_codec(codec); + if (ret != 0) { + dev_err(codec->dev, "Failed to register codec: %d\n", ret); + return ret; + } + + ret = snd_soc_register_dai(&ak4647_hifi_dai); + if (ret != 0) { + dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); + return ret; + } + + return ret; +} + +static const struct i2c_device_id ak4647_id[] = { + {"ak4647-i2c", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, ak4647_id); + +static struct i2c_driver ak4647_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "ak4647-i2c", + }, + .probe = ak4647_i2c_probe, + .remove = __devexit_p(ak4647_i2c_remove), + .id_table = ak4647_id, +}; + +int pmic_audio_fm_output_enable(bool enable) +{ + u8 val; + if (enable) { + ak4647_set_dai_fmt(NULL, + SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM); + ak4647_set_dai_sysclk(NULL, 0, 44100, 0); + ak4647_set_clkdiv(NULL, 0, 0); + /* VCOM power on */ + ak4647_write_reg(AK4647_PM1, 0x44); + msleep(30); + + ak4647_read_reg(AK4647_PM2, &val); + /* PLL enabled */ + SET_BIT_IN_BYTE(val, 0); + + ak4647_write_reg(AK4647_PM2, val); + /* wait for PLL locked */ + msleep(40); + + /* don't mute */ + SET_BIT_IN_BYTE(val, 6); + ak4647_write_reg(AK4647_PM2, val); + + /* loopback STDO to DAC */ + ak4647_read_reg(AK4647_MODE3, &val); + SET_BIT_IN_BYTE(val, 6); + ak4647_write_reg(AK4647_MODE3, val); + + /* switch to R/L 1 */ + ak4647_read_reg(AK4647_PM3, &val); + CLEAR_BIT_IN_BYTE(val, 1); + CLEAR_BIT_IN_BYTE(val, 2); + ak4647_write_reg(AK4647_PM3, val); + + /* power up ADC */ + ak4647_read_reg(AK4647_PM1, &val); + SET_BIT_IN_BYTE(val, 0); + ak4647_write_reg(AK4647_PM1, val); + ak4647_read_reg(AK4647_PM3, &val); + SET_BIT_IN_BYTE(val, 0); + ak4647_write_reg(AK4647_PM3, val); + + /* power up DAC */ + ak4647_read_reg(AK4647_PM1, &val); + SET_BIT_IN_BYTE(val, 2); + ak4647_write_reg(AK4647_PM1, val); + + msleep(30); + + /* headphone output switch on */ + ak4647_read_reg(AK4647_MODE4, &val); + SET_BIT_IN_BYTE(val, 0); + ak4647_write_reg(AK4647_MODE4, val); + + /* power on headphone amp */ + ak4647_read_reg(AK4647_PM2, &val); + SET_BIT_IN_BYTE(val, 4); + SET_BIT_IN_BYTE(val, 5); + ak4647_write_reg(AK4647_PM2, val); + + ak4647_digital_mute(NULL, 0); + } else { + ak4647_digital_mute(NULL, 1); + + /* disbale loopback */ + ak4647_read_reg(AK4647_MODE3, &val); + CLEAR_BIT_IN_BYTE(val, 6); + SET_BIT_IN_BYTE(val, 5); + ak4647_write_reg(AK4647_MODE3, val); + + /* switch to R/L 2 */ + ak4647_read_reg(AK4647_PM3, &val); + SET_BIT_IN_BYTE(val, 1); + SET_BIT_IN_BYTE(val, 2); + ak4647_write_reg(AK4647_PM3, val); + } + return 0; +} + +static int loopback_xhandle_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = kcontrol->private_value; + return 0; +} + +static int loopback_xhandle_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int changed; + long flag = ucontrol->value.integer.value[0]; + changed = + (ucontrol->value.integer.value[0] == + kcontrol->private_value) ? 0 : 1; + kcontrol->private_value = flag; + if (flag) + pmic_audio_fm_output_enable(true); + else + pmic_audio_fm_output_enable(false); + + return changed; +} + +/* power down chip */ +static int ak4647_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + i2c_del_driver(&ak4647_i2c_driver); + kfree(codec); + + return 0; +} + +static int ak4647_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int ak4647_resume(struct platform_device *pdev) +{ + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_ak4647 = { + .probe = ak4647_probe, + .remove = ak4647_remove, + .suspend = ak4647_suspend, + .resume = ak4647_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_ak4647); + +static int __init ak4647_modinit(void) +{ + return i2c_add_driver(&ak4647_i2c_driver); +} +module_init(ak4647_modinit); + +static void __exit ak4647_exit(void) +{ + i2c_del_driver(&ak4647_i2c_driver); +} +module_exit(ak4647_exit); + +MODULE_DESCRIPTION("ASoC ak4647 driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/ak4647.h b/sound/soc/codecs/ak4647.h new file mode 100644 index 000000000000..d32a758c427b --- /dev/null +++ b/sound/soc/codecs/ak4647.h @@ -0,0 +1,92 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file ak4647.h + * @brief Driver for AK4647 + * + * @ingroup Sound + */ +#ifndef _AK4647_H_ +#define _AK4647_H_ + +#ifdef __KERNEL__ + +/*! + * AK4647 registers + */ + +#define AK4647_PM1 0x00 +#define AK4647_PM2 0x01 +#define AK4647_SIG1 0x02 +#define AK4647_SIG2 0x03 +#define AK4647_MODE1 0x04 +#define AK4647_MODE2 0x05 +#define AK4647_TIMER 0x06 +#define AK4647_ALC1 0x07 +#define AK4647_ALC2 0x08 + +#define AK4647_LEFT_INPUT_VOLUME 0x09 +#define AK4647_LEFT_DGT_VOLUME 0x0A +#define AK4647_ALC3 0x0B +#define AK4647_RIGHT_INPUT_VOLUME 0x0C +#define AK4647_RIGHT_DGT_VOLUME 0x0D +#define AK4647_MODE3 0x0E +#define AK4647_MODE4 0x0F +#define AK4647_PM3 0x10 +#define AK4647_DGT_FIL_SEL 0x11 + +/* filter 3 coeffecient*/ + +#define AK4647_FIL3_COEF0 0x12 +#define AK4647_FIL3_COEF1 0x13 +#define AK4647_FIL3_COEF2 0x14 +#define AK4647_FIL3_COEF3 0x15 + +/* eq coeffecient*/ + +#define AK4647_EQ_COEF0 0x16 +#define AK4647_EQ_COEF1 0x17 +#define AK4647_EQ_COEF2 0x18 +#define AK4647_EQ_COEF3 0x19 +#define AK4647_EQ_COEF4 0x1A +#define AK4647_EQ_COEF5 0x1B + +/* filter 3 coeffecient*/ + +#define AK4647_FIL1_COEF0 0x1C +#define AK4647_FIL1_COEF1 0x1D +#define AK4647_FIL1_COEF2 0x1E +#define AK4647_FIL1_COEF3 0x1F + +#define AK4647_REG_START 0x00 +#define AK4647_REG_END 0x1F +#define AK4647_REG_NUMBER 0x20 + +/* clock divider id's */ +#define AK4647_BCLK_CLKDIV 0 +#define AK4647_MCLK_CLKDIV 1 + +/* bit clock div values (AK4647_BCLK_CLKDIV)*/ +#define AK4647_BCLK_DIV_32 0 +#define AK4647_BCLK_DIV_64 1 + +/* m clock div values (AK4647_MCLK_CLKDIV)*/ +#define AK4647_MCLK_DIV_32 0 +#define AK4647_MCLK_DIV_64 1 +#define AK4647_MCLK_DIV_128 2 +#define AK4647_MCLK_DIV_256 3 + +#endif /* __KERNEL__ */ + +#endif /* _AK4647_H_ */ diff --git a/sound/soc/codecs/ak5702.c b/sound/soc/codecs/ak5702.c new file mode 100644 index 000000000000..408f6efc84ca --- /dev/null +++ b/sound/soc/codecs/ak5702.c @@ -0,0 +1,595 @@ +/* + * ak5702.c -- AK5702 Soc Audio driver + * + * Copyright 2009-2010 Freescale Semiconductor, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ak5702.h" + +#define AK5702_VERSION "0.1" + +/* codec private data */ +struct ak5702_priv { + unsigned int sysclk; +}; + +/* + * ak5702 register cache + */ +static const u16 ak5702_reg[AK5702_CACHEREGNUM] = { + 0x0000, 0x0024, 0x0000, 0x0001, 0x0023, 0x001f, + 0x0000, 0x0001, 0x0091, 0x0000, 0x00e1, 0x0000, + 0x00a0, 0x0000, 0x0000, 0x0000, 0x0001, 0x0020, + 0x0000, 0x0000, 0x0001, 0x0091, 0x0000, 0x00e1, + 0x0000, +}; + +/* + * read ak5702 register cache + */ +static inline unsigned int ak5702_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + + if (reg >= AK5702_CACHEREGNUM) + return -1; + return cache[reg]; +} + +static inline unsigned int ak5702_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 data; + data = reg; + + if (i2c_master_send(codec->control_data, &data, 1) != 1) + return -EIO; + if (i2c_master_recv(codec->control_data, &data, 1) != 1) + return -EIO; + + return data; +}; + +/* + * write ak5702 register cache + */ +static inline void ak5702_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + + if (reg >= AK5702_CACHEREGNUM) + return; + cache[reg] = value; +} + +/* + * write to the AK5702 register space + */ +static int ak5702_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + u8 data[2]; + + data[0] = reg & 0xff; + data[1] = value & 0xff; + + ak5702_write_reg_cache(codec, reg, value); + if (i2c_master_send(codec->control_data, data, 2) == 2) + return 0; + else + return -EIO; +} + +static const char *ak5702_mic_gain[] = { "0dB", "+15dB", "+30dB", "+36dB" }; +static const char *ak5702_adca_left_type[] = { + "Single-ended", "Full-differential" }; +static const char *ak5702_adca_right_type[] = { + "Single-ended", "Full-differential" }; +static const char *ak5702_adcb_left_type[] = { + "Single-ended", "Full-differential" }; +static const char *ak5702_adcb_right_type[] = { + "Single-ended", "Full-differential" }; +static const char *ak5702_adca_left_input[] = { "LIN1", "LIN2" }; +static const char *ak5702_adca_right_input[] = { "RIN1", "RIN2" }; +static const char *ak5702_adcb_left_input[] = { "LIN3", "LIN4" }; +static const char *ak5702_adcb_right_input[] = { "RIN3", "RIN4" }; + +static const struct soc_enum ak5702_enum[] = { + SOC_ENUM_SINGLE(AK5702_MICG1, 0, 4, ak5702_mic_gain), + SOC_ENUM_SINGLE(AK5702_MICG2, 0, 4, ak5702_mic_gain), + + SOC_ENUM_SINGLE(AK5702_SIG1, 0, 2, ak5702_adca_left_input), + SOC_ENUM_SINGLE(AK5702_SIG1, 1, 2, ak5702_adca_right_input), + SOC_ENUM_SINGLE(AK5702_SIG2, 0, 2, ak5702_adcb_left_input), + SOC_ENUM_SINGLE(AK5702_SIG1, 1, 2, ak5702_adcb_right_input), + + SOC_ENUM_SINGLE(AK5702_SIG1, 2, 2, ak5702_adca_left_type), + SOC_ENUM_SINGLE(AK5702_SIG1, 3, 2, ak5702_adca_right_type), + SOC_ENUM_SINGLE(AK5702_SIG2, 2, 2, ak5702_adcb_left_type), + SOC_ENUM_SINGLE(AK5702_SIG2, 3, 2, ak5702_adcb_right_type), +}; + +static const struct snd_kcontrol_new ak5702_snd_controls[] = { + SOC_SINGLE("ADCA Left Vol", AK5702_LVOL1, 0, 242, 0), + SOC_SINGLE("ADCA Right Vol", AK5702_RVOL1, 0, 242, 0), + SOC_SINGLE("ADCB Left Vol", AK5702_LVOL2, 0, 242, 0), + SOC_SINGLE("ADCB Right Vol", AK5702_RVOL2, 0, 242, 0), + + SOC_ENUM("MIC-AmpA Gain", ak5702_enum[0]), + SOC_ENUM("MIC-AmpB Gain", ak5702_enum[1]), + + SOC_ENUM("ADCA Left Source", ak5702_enum[2]), + SOC_ENUM("ADCA Right Source", ak5702_enum[3]), + SOC_ENUM("ADCB Left Source", ak5702_enum[4]), + SOC_ENUM("ADCB Right Source", ak5702_enum[5]), + + SOC_ENUM("ADCA Left Type", ak5702_enum[6]), + SOC_ENUM("ADCA Right Type", ak5702_enum[7]), + SOC_ENUM("ADCB Left Type", ak5702_enum[8]), + SOC_ENUM("ADCB Right Type", ak5702_enum[9]), +}; + +/* ak5702 dapm widgets */ +static const struct snd_soc_dapm_widget ak5702_dapm_widgets[] = { + SND_SOC_DAPM_ADC("ADCA Left", "Capture", AK5702_PM1, 0, 0), + SND_SOC_DAPM_ADC("ADCA Right", "Capture", AK5702_PM1, 1, 0), + SND_SOC_DAPM_ADC("ADCB Left", "Capture", AK5702_PM2, 0, 0), + SND_SOC_DAPM_ADC("ADCB Right", "Capture", AK5702_PM2, 1, 0), + + SND_SOC_DAPM_INPUT("ADCA Left Input"), + SND_SOC_DAPM_INPUT("ADCA Right Input"), + SND_SOC_DAPM_INPUT("ADCB Left Input"), + SND_SOC_DAPM_INPUT("ADCB Right Input"), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + {"ADCA Left", NULL, "ADCA Left Input"}, + {"ADCA Right", NULL, "ADCA Right Input"}, + {"ADCB Left", NULL, "ADCB Left Input"}, + {"ADCB Right", NULL, "ADCB Right Input"}, +}; + +static int ak5702_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, ak5702_dapm_widgets, + ARRAY_SIZE(ak5702_dapm_widgets)); + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + return 0; +} + +static int ak5702_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 fs = 0; + u8 value; + + switch (freq) { + case 8000: + fs = 0x0; + break; + case 11025: + fs = 0x05; + break; + case 12000: + fs = 0x01; + break; + case 16000: + fs = 0x02; + break; + case 22050: + fs = 0x07; + break; + case 24000: + fs = 0x03; + break; + case 32000: + fs = 0x0a; + break; + case 44100: + fs = 0x0f; + break; + case 48000: + fs = 0x0b; + break; + default: + return -EINVAL; + } + + value = ak5702_read_reg_cache(codec, AK5702_FS1); + value &= (~AK5702_FS1_FS_MASK); + value |= fs; + ak5702_write(codec, AK5702_FS1, value); + return 0; +} + +static int ak5702_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 fmt1 = 0; + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + fmt1 = AK5702_FMT1_I2S; + break; + case SND_SOC_DAIFMT_LEFT_J: + fmt1 = AK5702_FMT1_MSB; + break; + default: + return -EINVAL; + } + + ak5702_write(codec, AK5702_FMT1, fmt1); + ak5702_write(codec, AK5702_FMT2, AK5702_FMT2_STEREO); + return 0; +} + +static int ak5702_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, + int source, unsigned int freq_in, + unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 reg = 0; + + reg = ak5702_read_reg_cache(codec, AK5702_PLL1); + switch (pll_id) { + case AK5702_PLL_POWERDOWN: + reg &= (~AK5702_PLL1_PM_MASK); + reg |= AK5702_PLL1_POWERDOWN; + break; + case AK5702_PLL_MASTER: + reg &= (~AK5702_PLL1_MODE_MASK); + reg |= AK5702_PLL1_MASTER; + reg |= AK5702_PLL1_POWERUP; + break; + case AK5702_PLL_SLAVE: + reg &= (~AK5702_PLL1_MODE_MASK); + reg |= AK5702_PLL1_SLAVE; + reg |= AK5702_PLL1_POWERUP; + break; + default: + return -ENODEV; + } + + switch (freq_in) { + case 11289600: + reg &= (~AK5702_PLL1_PLL_MASK); + reg |= AK5702_PLL1_11289600; + break; + case 12000000: + reg &= (~AK5702_PLL1_PLL_MASK); + reg |= AK5702_PLL1_12000000; + break; + case 12288000: + reg &= (~AK5702_PLL1_PLL_MASK); + reg |= AK5702_PLL1_12288000; + break; + case 19200000: + reg &= (~AK5702_PLL1_PLL_MASK); + reg |= AK5702_PLL1_19200000; + break; + default: + return -ENODEV; + } + + ak5702_write(codec, AK5702_PLL1, reg); + return 0; +} + +static int ak5702_set_dai_clkdiv(struct snd_soc_dai *codec_dai, + int div_id, int div) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u8 reg = 0; + + if (div_id == AK5702_BCLK_CLKDIV) { + reg = ak5702_read_reg_cache(codec, AK5702_FS1); + switch (div) { + case AK5702_BCLK_DIV_32: + reg &= (~AK5702_FS1_BCKO_MASK); + reg |= AK5702_FS1_BCKO_32FS; + ak5702_write(codec, AK5702_FS1, reg); + break; + case AK5702_BCLK_DIV_64: + reg &= (~AK5702_FS1_BCKO_MASK); + reg |= AK5702_FS1_BCKO_64FS; + ak5702_write(codec, AK5702_FS1, reg); + break; + default: + return -EINVAL; + } + } + return 0; +} + +static int ak5702_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + u8 reg = 0; + + switch (level) { + case SND_SOC_BIAS_ON: + case SND_SOC_BIAS_PREPARE: + reg = ak5702_read_reg_cache(codec, AK5702_PM1); + ak5702_write(codec, AK5702_PM1, reg | AK5702_PM1_PMVCM); + reg = ak5702_read_reg_cache(codec, AK5702_PLL1); + reg = reg | AK5702_PLL1_POWERUP | AK5702_PLL1_MASTER; + ak5702_write(codec, AK5702_PLL1, reg); + break; + case SND_SOC_BIAS_STANDBY: + reg = ak5702_read_reg_cache(codec, AK5702_PM1); + ak5702_write(codec, AK5702_PM1, reg | AK5702_PM1_PMVCM); + reg = ak5702_read_reg_cache(codec, AK5702_PLL1); + ak5702_write(codec, AK5702_PLL1, reg & (~AK5702_PLL1_POWERUP)); + break; + case SND_SOC_BIAS_OFF: + reg = ak5702_read_reg_cache(codec, AK5702_PM1); + ak5702_write(codec, AK5702_PM1, reg & (~AK5702_PM1_PMVCM)); + break; + } + + codec->bias_level = level; + return 0; +} + +static int ak5702_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + ak5702_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int ak5702_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + int i; + + /* Bring the codec back up to standby first to minimise pop/clicks */ + ak5702_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + ak5702_set_bias_level(codec, codec->suspend_bias_level); + + /* Sync back everything else */ + for (i = 0; i < ARRAY_SIZE(ak5702_reg); i++) + ak5702_write(codec, i, ak5702_reg[i]); + + return 0; +} + +#define AK5702_RATES SNDRV_PCM_RATE_8000_48000 +#define AK5702_FORMATS SNDRV_PCM_FMTBIT_S16_LE + +struct snd_soc_dai_ops ak5702_ops = { + .set_fmt = ak5702_set_dai_fmt, + .set_sysclk = ak5702_set_dai_sysclk, + .set_clkdiv = ak5702_set_dai_clkdiv, + .set_pll = ak5702_set_dai_pll, +}; + +struct snd_soc_dai ak5702_dai = { + .name = "AK5702", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 4, + .rates = AK5702_RATES, + .formats = AK5702_FORMATS, + }, + .ops = &ak5702_ops, +}; +EXPORT_SYMBOL_GPL(ak5702_dai); + +static struct snd_soc_codec *ak5702_codec; + +static int ak5702_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = ak5702_codec; + int ret = 0; + u8 reg = 0; + + socdev->card->codec = ak5702_codec; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + printk(KERN_ERR "ak5702: failed to create pcms\n"); + goto pcm_err; + } + + /* power on device */ + reg = ak5702_read_reg_cache(codec, AK5702_PM1); + reg |= AK5702_PM1_PMVCM; + ak5702_write(codec, AK5702_PM1, reg); + + /* initialize ADC */ + reg = AK5702_SIG1_L_LIN1 | AK5702_SIG1_R_RIN2; + ak5702_write(codec, AK5702_SIG1, reg); + reg = AK5702_SIG2_L_LIN3 | AK5702_SIG2_R_RIN4; + ak5702_write(codec, AK5702_SIG2, reg); + + reg = ak5702_read_reg_cache(codec, AK5702_PM1); + reg = reg | AK5702_PM1_PMADAL | AK5702_PM1_PMADAR; + ak5702_write(codec, AK5702_PM1, reg); + reg = ak5702_read_reg_cache(codec, AK5702_PM2); + reg = reg | AK5702_PM2_PMADBL | AK5702_PM2_PMADBR; + ak5702_write(codec, AK5702_PM2, reg); + + /* initialize volume */ + ak5702_write(codec, AK5702_MICG1, AK5702_MICG1_INIT); + ak5702_write(codec, AK5702_MICG2, AK5702_MICG2_INIT); + ak5702_write(codec, AK5702_VOL1, AK5702_VOL1_IVOLAC); + ak5702_write(codec, AK5702_VOL2, AK5702_VOL2_IVOLBC); + ak5702_write(codec, AK5702_LVOL1, AK5702_LVOL1_INIT); + ak5702_write(codec, AK5702_RVOL1, AK5702_RVOL1_INIT); + ak5702_write(codec, AK5702_LVOL2, AK5702_LVOL2_INIT); + ak5702_write(codec, AK5702_RVOL2, AK5702_RVOL2_INIT); + + snd_soc_add_controls(codec, ak5702_snd_controls, + ARRAY_SIZE(ak5702_snd_controls)); + ak5702_add_widgets(codec); + + return ret; + +pcm_err: + kfree(codec->reg_cache); + return ret; +} + +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) +static int ak5702_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ak5702_priv *ak5702; + struct snd_soc_codec *codec; + int ret; + + if (ak5702_codec) { + dev_err(&client->dev, + "Multiple AK5702 devices not supported\n"); + return -ENOMEM; + } + + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + ak5702 = kzalloc(sizeof(struct ak5702_priv), GFP_KERNEL); + if (ak5702 == NULL) { + kfree(codec); + return -ENOMEM; + } + + snd_soc_codec_set_drvdata(codec, ak5702); + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + i2c_set_clientdata(client, codec); + codec->control_data = client; + + codec->dev = &client->dev; + codec->name = "AK5702"; + codec->owner = THIS_MODULE; + codec->read = ak5702_read_reg_cache; + codec->write = ak5702_write; + codec->set_bias_level = ak5702_set_bias_level; + codec->dai = &ak5702_dai; + codec->num_dai = 1; + codec->reg_cache_size = ARRAY_SIZE(ak5702_reg); + codec->reg_cache = (void *)&ak5702_reg; + if (codec->reg_cache == NULL) + return -ENOMEM; + + ak5702_codec = codec; + ak5702_dai.dev = &client->dev; + + ret = snd_soc_register_codec(codec); + if (ret != 0) { + dev_err(codec->dev, "Failed to register codec: %d\n", ret); + return ret; + } + + ret = snd_soc_register_dai(&ak5702_dai); + if (ret != 0) { + dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); + return ret; + } + + return ret; +} + +static __devexit int ak5702_i2c_remove(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + struct ak5702_priv *ak5702 = snd_soc_codec_get_drvdata(codec); + + snd_soc_unregister_dai(&ak5702_dai); + snd_soc_unregister_codec(codec); + kfree(codec); + kfree(ak5702); + ak5702_codec = NULL; + return 0; +} + +static const struct i2c_device_id ak5702_i2c_id[] = { + {"ak5702-i2c", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, ak5702_i2c_id); + +static struct i2c_driver ak5702_i2c_driver = { + .driver = { + .name = "ak5702-i2c", + .owner = THIS_MODULE, + }, + .probe = ak5702_i2c_probe, + .remove = __devexit_p(ak5702_i2c_remove), + .id_table = ak5702_i2c_id, +}; +#endif + +static int ak5702_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + if (codec->control_data) + ak5702_set_bias_level(codec, SND_SOC_BIAS_OFF); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) + i2c_del_driver(&ak5702_i2c_driver); +#endif + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_ak5702 = { + .probe = ak5702_probe, + .remove = ak5702_remove, + .suspend = ak5702_suspend, + .resume = ak5702_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_ak5702); + +static int __init ak5702_modinit(void) +{ + return i2c_add_driver(&ak5702_i2c_driver); +} +module_init(ak5702_modinit); + +static void __exit ak5702_exit(void) +{ + i2c_del_driver(&ak5702_i2c_driver); +} +module_exit(ak5702_exit); + +MODULE_DESCRIPTION("Soc AK5702 driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/ak5702.h b/sound/soc/codecs/ak5702.h new file mode 100644 index 000000000000..74b893ca2e8f --- /dev/null +++ b/sound/soc/codecs/ak5702.h @@ -0,0 +1,130 @@ +/* + * ak5702.h -- AK5702 Soc Audio driver + * + * Copyright 2009-2010 Freescale Semiconductor, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _AK5702_H +#define _AK5702_H + +/* AK5702 register space */ + +#define AK5702_PM1 0x00 +#define AK5702_PLL1 0x01 +#define AK5702_SIG1 0x02 +#define AK5702_MICG1 0x03 +#define AK5702_FMT1 0x04 +#define AK5702_FS1 0x05 +#define AK5702_CLK1 0x06 +#define AK5702_VOL1 0x07 +#define AK5702_LVOL1 0x08 +#define AK5702_RVOL1 0x09 +#define AK5702_TIMER1 0x0a +#define AK5702_ALC11 0x0b +#define AK5702_ALC12 0x0c +#define AK5702_MODE11 0x0d +#define AK5702_MODE12 0x0e +#define AK5702_MODE13 0x0f + +#define AK5702_PM2 0x10 +#define AK5702_PLL2 0x11 +#define AK5702_SIG2 0x12 +#define AK5702_MICG2 0x13 +#define AK5702_FMT2 0x14 +#define AK5702_FS2 0x15 +#define AK5702_CLK2 0x16 +#define AK5702_VOL2 0x17 +#define AK5702_LVOL2 0x18 +#define AK5702_RVOL2 0x19 +#define AK5702_TIMER2 0x1a +#define AK5702_ALC21 0x1b +#define AK5702_ALC22 0x1c +#define AK5702_MODE21 0x1d +#define AK5702_MODE22 0x1e + +#define AK5702_CACHEREGNUM 0x1F + +#define AK5702_PM1_PMADAL 0x01 +#define AK5702_PM1_PMADAR 0x02 +#define AK5702_PM1_PMVCM 0x04 +#define AK5702_PM2_PMADBL 0x01 +#define AK5702_PM2_PMADBR 0x02 + +#define AK5702_PLL1_POWERDOWN 0x0 +#define AK5702_PLL1_POWERUP 0x01 +#define AK5702_PLL1_MASTER 0x02 +#define AK5702_PLL1_SLAVE 0x0 +#define AK5702_PLL1_11289600 0x10 +#define AK5702_PLL1_12000000 0x24 +#define AK5702_PLL1_12288000 0x14 +#define AK5702_PLL1_19200000 0x20 + +#define AK5702_SIG1_L_LIN1 0x0 +#define AK5702_SIG1_L_LIN2 0x01 +#define AK5702_SIG1_R_RIN1 0x0 +#define AK5702_SIG1_R_RIN2 0x02 +#define AK5702_SIG1_PMMPA 0x10 +#define AK5702_SIG2_L_LIN3 0x0 +#define AK5702_SIG2_L_LIN4 0x01 +#define AK5702_SIG2_R_RIN3 0x0 +#define AK5702_SIG2_R_RIN4 0x02 +#define AK5702_SIG2_PMMPB 0x10 + +#define AK5702_MICG1_INIT 0x0 +#define AK5702_MICG2_INIT 0x0 + +#define AK5702_FMT1_I2S 0x23 +#define AK5702_FMT1_MSB 0x22 +#define AK5702_FMT2_STEREO 0x20 +#define AK5702_FS1_BCKO_32FS 0x10 +#define AK5702_FS1_BCKO_64FS 0x20 +#define AK5702_CLK1_PS_256FS 0x0 +#define AK5702_CLK1_PS_128FS 0x01 +#define AK5702_CLK1_PS_64FS 0x02 +#define AK5702_CLK1_PS_32FS 0x03 +#define AK5702_VOL1_IVOLAC 0x01 +#define AK5702_VOL2_IVOLBC 0x01 +#define AK5702_LVOL1_INIT 0x91 +#define AK5702_RVOL1_INIT 0x91 +#define AK5702_LVOL2_INIT 0x91 +#define AK5702_RVOL2_INIT 0x91 + +#define AK5702_PLL1_PM_MASK 0x01 +#define AK5702_PLL1_MODE_MASK 0x02 +#define AK5702_PLL1_PLL_MASK 0x3c +#define AK5702_FS1_BCKO_MASK 0x30 +#define AK5702_FS1_FS_MASK 0x0f +#define AK5702_CLK1_PS_MASK 0x03 + +/* clock divider id */ +#define AK5702_BCLK_CLKDIV 0 +#define AK5702_MCLK_CLKDIV 1 + +/* bit clock div values */ +#define AK5702_BCLK_DIV_32 0 +#define AK5702_BCLK_DIV_64 1 + +/* m clock div values */ +#define AK5702_MCLK_DIV_32 0 +#define AK5702_MCLK_DIV_64 1 +#define AK5702_MCLK_DIV_128 2 +#define AK5702_MCLK_DIV_256 3 + +/* PLL master and slave modes */ +#define AK5702_PLL_POWERDOWN 0 +#define AK5702_PLL_MASTER 1 +#define AK5702_PLL_SLAVE 2 + +struct ak5702_setup_data { + int i2c_bus; + unsigned short i2c_address; +}; + +extern struct snd_soc_dai ak5702_dai; +extern struct snd_soc_codec_device soc_codec_dev_ak5702; + +#endif diff --git a/sound/soc/codecs/bluetooth.c b/sound/soc/codecs/bluetooth.c new file mode 100644 index 000000000000..1b065f7653ad --- /dev/null +++ b/sound/soc/codecs/bluetooth.c @@ -0,0 +1,162 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file bluetooth.c + * @brief Driver for bluetooth PCM interface + * + * @ingroup Sound + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BLUETOOTH_RATES SNDRV_PCM_RATE_8000 + +#define BLUETOOTH_FORMATS SNDRV_PCM_FMTBIT_S16_LE + +struct snd_soc_dai bt_dai = { + .name = "bluetooth", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = BLUETOOTH_RATES, + .formats = BLUETOOTH_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = BLUETOOTH_RATES, + .formats = BLUETOOTH_FORMATS, + }, +}; +EXPORT_SYMBOL_GPL(bt_dai); + +static int bt_init(struct snd_soc_device *socdev) +{ + struct snd_soc_codec *codec = socdev->card->codec; + int ret = 0; + + codec->name = "bluetooth"; + codec->owner = THIS_MODULE; + codec->dai = &bt_dai; + codec->num_dai = 1; + + snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + pr_err("failed to create bluetooth pcms\n"); + return ret; + } + + ret = snd_soc_init_card(socdev); + strcpy(codec->card->id, "bluetooth"); + + if (ret < 0) { + pr_err("bluetooth: failed to register card\n"); + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + return ret; + } + return 0; +} + +static struct snd_soc_device *bt_socdev; + +static int bt_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + int ret = 0; + + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + socdev->card->codec = codec; + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + bt_socdev = socdev; + + ret = bt_init(socdev); + if (ret < 0) { + pr_err("Bluetooth codec initialisation failed\n"); + kfree(codec); + } + + return ret; +} + +/* power down chip */ +static int bt_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + kfree(codec); + + return 0; +} + +static int bt_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int bt_resume(struct platform_device *pdev) +{ + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_bt = { + .probe = bt_probe, + .remove = bt_remove, + .suspend = bt_suspend, + .resume = bt_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_bt); + +static int __init bluetooth_modinit(void) +{ + return snd_soc_register_dai(&bt_dai); +} + +module_init(bluetooth_modinit); + +static void __exit bluetooth_exit(void) +{ + snd_soc_unregister_dai(&bt_dai); +} + +module_exit(bluetooth_exit); + +MODULE_DESCRIPTION("ASoC bluetooth codec driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/cs42888.c b/sound/soc/codecs/cs42888.c new file mode 100644 index 000000000000..93f6dba5d5da --- /dev/null +++ b/sound/soc/codecs/cs42888.c @@ -0,0 +1,1193 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cs42888.h" + +#define CS42888_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +/* CS42888 registers addresses */ +#define CS42888_CHIPID 0x01 /* Chip ID */ +#define CS42888_PWRCTL 0x02 /* Power Control */ +#define CS42888_MODE 0x03 /* Functional Mode */ +#define CS42888_FORMAT 0x04 /* Interface Formats */ +#define CS42888_ADCCTL 0x05 /* ADC Control */ +#define CS42888_TRANS 0x06 /* Transition Control */ +#define CS42888_MUTE 0x07 /* Mute Control */ +#define CS42888_VOLAOUT1 0x08 /* Volume Control AOUT1*/ +#define CS42888_VOLAOUT2 0x09 /* Volume Control AOUT2*/ +#define CS42888_VOLAOUT3 0x0A /* Volume Control AOUT3*/ +#define CS42888_VOLAOUT4 0x0B /* Volume Control AOUT4*/ +#define CS42888_VOLAOUT5 0x0C /* Volume Control AOUT5*/ +#define CS42888_VOLAOUT6 0x0D /* Volume Control AOUT6*/ +#define CS42888_VOLAOUT7 0x0E /* Volume Control AOUT7*/ +#define CS42888_VOLAOUT8 0x0F /* Volume Control AOUT8*/ +#define CS42888_DACINV 0x10 /* DAC Channel Invert */ +#define CS42888_VOLAIN1 0x11 /* Volume Control AIN1 */ +#define CS42888_VOLAIN2 0x12 /* Volume Control AIN2 */ +#define CS42888_VOLAIN3 0x13 /* Volume Control AIN3 */ +#define CS42888_VOLAIN4 0x14 /* Volume Control AIN4 */ +#define CS42888_ADCINV 0x17 /* ADC Channel Invert */ +#define CS42888_STATUSCTL 0x18 /* Status Control */ +#define CS42888_STATUS 0x19 /* Status */ +#define CS42888_STATUSMASK 0x1A /* Status Mask */ + +#define CS42888_FIRSTREG 0x01 +#define CS42888_LASTREG 0x1A +#define CS42888_NUMREGS (CS42888_LASTREG - CS42888_FIRSTREG + 1) +#define CS42888_I2C_INCR 0x80 + +/* Bit masks for the CS42888 registers */ +#define CS42888_CHIPID_ID_MASK 0xF0 +#define CS42888_CHIPID_REV 0x0F +#define CS42888_PWRCTL_PDN_ADC2_OFFSET 6 +#define CS42888_PWRCTL_PDN_ADC1_OFFSET 5 +#define CS42888_PWRCTL_PDN_DAC4_OFFSET 4 +#define CS42888_PWRCTL_PDN_DAC3_OFFSET 3 +#define CS42888_PWRCTL_PDN_DAC2_OFFSET 2 +#define CS42888_PWRCTL_PDN_DAC1_OFFSET 1 +#define CS42888_PWRCTL_PDN_OFFSET 0 +#define CS42888_PWRCTL_PDN_ADC2_MASK (1 << CS42888_PWRCTL_PDN_ADC2_OFFSET) +#define CS42888_PWRCTL_PDN_ADC1_MASK (1 << CS42888_PWRCTL_PDN_ADC1_OFFSET) +#define CS42888_PWRCTL_PDN_DAC4_MASK (1 << CS42888_PWRCTL_PDN_DAC4_OFFSET) +#define CS42888_PWRCTL_PDN_DAC3_MASK (1 << CS42888_PWRCTL_PDN_DAC3_OFFSET) +#define CS42888_PWRCTL_PDN_DAC2_MASK (1 << CS42888_PWRCTL_PDN_DAC2_OFFSET) +#define CS42888_PWRCTL_PDN_DAC1_MASK (1 << CS42888_PWRCTL_PDN_DAC1_OFFSET) +#define CS42888_PWRCTL_PDN_MASK (1 << CS42888_PWRCTL_PDN_OFFSET) + +#define CS42888_MODE_SPEED_MASK 0xF0 +#define CS42888_MODE_1X 0x00 +#define CS42888_MODE_2X 0x50 +#define CS42888_MODE_4X 0xA0 +#define CS42888_MODE_SLAVE 0xF0 +#define CS42888_MODE_DIV_MASK 0x0E +#define CS42888_MODE_DIV1 0x00 +#define CS42888_MODE_DIV2 0x02 +#define CS42888_MODE_DIV3 0x04 +#define CS42888_MODE_DIV4 0x06 +#define CS42888_MODE_DIV5 0x08 + +#define CS42888_FORMAT_FREEZE_OFFSET 7 +#define CS42888_FORMAT_AUX_DIF_OFFSET 6 +#define CS42888_FORMAT_DAC_DIF_OFFSET 3 +#define CS42888_FORMAT_ADC_DIF_OFFSET 0 +#define CS42888_FORMAT_FREEZE_MASK (1 << CS42888_FORMAT_FREEZE_OFFSET) +#define CS42888_FORMAT_AUX_DIF_MASK (1 << CS42888_FORMAT_AUX_DIF_OFFSET) +#define CS42888_FORMAT_DAC_DIF_MASK (7 << CS42888_FORMAT_DAC_DIF_OFFSET) +#define CS42888_FORMAT_ADC_DIF_MASK (7 << CS42888_FORMAT_ADC_DIF_OFFSET) + +#define CS42888_TRANS_DAC_SNGVOL_OFFSET 7 +#define CS42888_TRANS_DAC_SZC_OFFSET 5 +#define CS42888_TRANS_AMUTE_OFFSET 4 +#define CS42888_TRANS_MUTE_ADC_SP_OFFSET 3 +#define CS42888_TRANS_ADC_SNGVOL_OFFSET 2 +#define CS42888_TRANS_ADC_SZC_OFFSET 0 +#define CS42888_TRANS_DAC_SNGVOL_MASK (1 << CS42888_TRANS_DAC_SNGVOL_OFFSET) +#define CS42888_TRANS_DAC_SZC_MASK (3 << CS42888_TRANS_DAC_SZC_OFFSET) +#define CS42888_TRANS_AMUTE_MASK (1 << CS42888_TRANS_AMUTE_OFFSET) +#define CS42888_TRANS_MUTE_ADC_SP_MASK (1 << CS42888_TRANS_MUTE_ADC_SP_OFFSET) +#define CS42888_TRANS_ADC_SNGVOL_MASK (1 << CS42888_TRANS_ADC_SNGVOL_OFFSET) +#define CS42888_TRANS_ADC_SZC_MASK (3 << CS42888_TRANS_ADC_SZC_OFFSET) + +#define CS42888_MUTE_AOUT8 (0x1 << 7) +#define CS42888_MUTE_AOUT7 (0x1 << 6) +#define CS42888_MUTE_AOUT6 (0x1 << 5) +#define CS42888_MUTE_AOUT5 (0x1 << 4) +#define CS42888_MUTE_AOUT4 (0x1 << 3) +#define CS42888_MUTE_AOUT3 (0x1 << 2) +#define CS42888_MUTE_AOUT2 (0x1 << 1) +#define CS42888_MUTE_AOUT1 (0x1 << 0) +#define CS42888_MUTE_ALL (CS42888_MUTE_AOUT1 | CS42888_MUTE_AOUT2 | \ + CS42888_MUTE_AOUT3 | CS42888_MUTE_AOUT4 | \ + CS42888_MUTE_AOUT5 | CS42888_MUTE_AOUT6 | \ + CS42888_MUTE_AOUT7 | CS42888_MUTE_AOUT8) + +#define DIF_LEFT_J 0 +#define DIF_I2S 1 +#define DIF_RIGHT_J 2 +#define DIF_TDM 6 + +/* Private data for the CS42888 */ +struct cs42888_private { + struct snd_soc_codec codec; + u8 reg_cache[CS42888_NUMREGS]; + unsigned int mclk; /* Input frequency of the MCLK pin */ + unsigned int mode; /* The mode (I2S or left-justified) */ + unsigned int slave_mode; + unsigned int manual_mute; + struct regulator *regulator_vsd; +}; + +static struct i2c_client *cs42888_i2c_client; + +int cs42888_read_reg(unsigned int reg, u8 *value) +{ + s32 retval; + retval = i2c_smbus_read_byte_data(cs42888_i2c_client, reg); + if (retval < 0) { + pr_err("%s:read reg errorr:reg=%x,val=%x\n", + __func__, reg, retval); + return -1; + } else { + *value = (u8) retval; + return 0; + } +} + +int cs42888_write_reg(unsigned int reg, u8 value) +{ + if (i2c_smbus_write_byte_data(cs42888_i2c_client, reg, value) < 0) { + pr_err("%s:write reg errorr:reg=%x,val=%x\n", + __func__, reg, value); + return -1; + } + return 0; +} +/** + * cs42888_fill_cache - pre-fill the CS42888 register cache. + * @codec: the codec for this CS42888 + * + * This function fills in the CS42888 register cache by reading the register + * values from the hardware. + * + * This CS42888 registers are cached to avoid excessive I2C I/O operations. + * After the initial read to pre-fill the cache, the CS42888 never updates + * the register values, so we won't have a cache coherency problem. + * + * We use the auto-increment feature of the CS42888 to read all registers in + * one shot. + */ +static int cs42888_fill_cache(struct snd_soc_codec *codec) +{ + u8 *cache = codec->reg_cache; + struct i2c_client *i2c_client = codec->control_data; + s32 length; + + length = i2c_smbus_read_i2c_block_data(i2c_client, + CS42888_FIRSTREG | CS42888_I2C_INCR, CS42888_NUMREGS, cache); + + if (length != CS42888_NUMREGS) { + dev_err(codec->dev, "i2c read failure, addr=0x%x\n", + i2c_client->addr); + return -EIO; + } + + return 0; +} + +/** + * cs42888_read_reg_cache - read from the CS42888 register cache. + * @codec: the codec for this CS42888 + * @reg: the register to read + * + * This function returns the value for a given register. It reads only from + * the register cache, not the hardware itself. + * + * This CS42888 registers are cached to avoid excessive I2C I/O operations. + * After the initial read to pre-fill the cache, the CS42888 never updates + * the register values, so we won't have a cache coherency problem. + */ +static u8 cs42888_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u8 *cache = codec->reg_cache; + + if ((reg < CS42888_FIRSTREG) || (reg > CS42888_LASTREG)) + return -EIO; + + return cache[reg - CS42888_FIRSTREG]; +} + +/** + * cs42888_i2c_write - write to a CS42888 register via the I2C bus. + * @codec: the codec for this CS42888 + * @reg: the register to write + * @value: the value to write to the register + * + * This function writes the given value to the given CS42888 register, and + * also updates the register cache. + * + * Note that we don't use the hw_write function pointer of snd_soc_codec. + * That's because it's too clunky: the hw_write_t prototype does not match + * i2c_smbus_write_byte_data(), and it's just another layer of overhead. + */ +static int cs42888_i2c_write(struct snd_soc_codec *codec, unsigned int reg, + u8 value) +{ + u8 *cache = codec->reg_cache; + + if ((reg < CS42888_FIRSTREG) || (reg > CS42888_LASTREG)) + return -EIO; + + /* Only perform an I2C operation if the new value is different */ + if (cache[reg - CS42888_FIRSTREG] != value) { + if (i2c_smbus_write_byte_data(cs42888_i2c_client, reg, value) + < 0) { + dev_err(codec->dev, "i2c write failed\n"); + return -EIO; + } + + /* We've written to the hardware, so update the cache */ + cache[reg - CS42888_FIRSTREG] = value; + } + + return 0; +} + +#ifdef CS42888_DEBUG +static void dump_reg(struct snd_soc_codec *codec) +{ + int i, reg; + int ret; + printk(KERN_DEBUG "dump begin\n"); + printk(KERN_DEBUG "reg value in cache\n"); + for (i = 0; i < CS42888_NUMREGS; i++) + printk(KERN_DEBUG "reg[%d] = 0x%x\n", i, cache[i]); + + printk(KERN_DEBUG "real reg value\n"); + ret = cs42888_fill_cache(codec); + if (ret < 0) { + pr_err("failed to fill register cache\n"); + return ret; + } + for (i = 0; i < CS42888_NUMREGS; i++) + printk(KERN_DEBUG "reg[%d] = 0x%x\n", i, cache[i]); + + printk(KERN_DEBUG "dump end\n"); +} +#else +static void dump_reg(struct snd_soc_codec *codec) +{ +} +#endif + +/* -127.5dB to 0dB with step of 0.5dB */ +static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); +/* -64dB to 24dB with step of 0.5dB */ +static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 1); + +static int cs42888_out_vu(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + unsigned int reg = mc->reg; + unsigned int reg2 = mc->rreg; + int ret; + u16 val; + + ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); + if (ret < 0) + return ret; + + /* Now write again with the volume update bit set */ + val = cs42888_read_reg_cache(codec, reg); + ret = cs42888_i2c_write(codec, reg, val); + + val = cs42888_read_reg_cache(codec, reg2); + ret = cs42888_i2c_write(codec, reg2, val); + return 0; +} + +int cs42888_info_volsw_s8(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + int max = mc->max; + int min = mc->min; + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 2; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = max-min; + return 0; +} + +int cs42888_get_volsw_s8(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + unsigned int reg = mc->reg; + unsigned int reg2 = mc->rreg; + int min = mc->min; + int val = cs42888_read_reg_cache(codec, reg); + + ucontrol->value.integer.value[0] = + ((signed char)(val))-min; + + val = cs42888_read_reg_cache(codec, reg2); + ucontrol->value.integer.value[1] = + ((signed char)(val))-min; + return 0; +} + +int cs42888_put_volsw_s8(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + unsigned int reg = mc->reg; + unsigned int reg2 = mc->rreg; + int min = mc->min; + unsigned short val; + int ret; + + val = (ucontrol->value.integer.value[0]+min); + ret = cs42888_i2c_write(codec, reg, val); + if (ret < 0) { + pr_err("i2c write failed\n"); + return ret; + } + + val = ((ucontrol->value.integer.value[1]+min)); + ret = cs42888_i2c_write(codec, reg2, val); + if (ret < 0) { + pr_err("i2c write failed\n"); + return ret; + } + + return 0; +} + +#define SOC_CS42888_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \ + xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_2r, \ + .get = snd_soc_get_volsw_2r, \ + .put = cs42888_out_vu, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = reg_left, \ + .rreg = reg_right, \ + .shift = xshift, \ + .max = xmax, \ + .invert = xinvert} \ +} + +#define SOC_CS42888_DOUBLE_R_S8_TLV(xname, reg_left, reg_right, xmin, xmax, \ + tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = cs42888_info_volsw_s8, .get = cs42888_get_volsw_s8, \ + .put = cs42888_put_volsw_s8, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = reg_left, \ + .rreg = reg_right, \ + .min = xmin, \ + .max = xmax} \ +} + +static const char *cs42888_adcfilter[] = { "None", "High Pass" }; +static const char *cs42888_dacinvert[] = { "Disabled", "Enabled" }; +static const char *cs42888_adcinvert[] = { "Disabled", "Enabled" }; +static const char *cs42888_dacamute[] = { "Disabled", "AutoMute" }; +static const char *cs42888_dac_sngvol[] = { "Disabled", "Enabled" }; +static const char *cs42888_dac_szc[] = { "Immediate Change", "Zero Cross", + "Soft Ramp", "Soft Ramp on Zero Cross" }; +static const char *cs42888_mute_adc[] = { "UnMute", "Mute" }; +static const char *cs42888_adc_sngvol[] = { "Disabled", "Enabled" }; +static const char *cs42888_adc_szc[] = { "Immediate Change", "Zero Cross", + "Soft Ramp", "Soft Ramp on Zero Cross" }; +static const char *cs42888_dac_dem[] = { "No-De-Emphasis", "De-Emphasis" }; +static const char *cs42888_adc_single[] = { "Differential", "Single-Ended" }; + +static const struct soc_enum cs42888_enum[] = { + SOC_ENUM_SINGLE(CS42888_ADCCTL, 7, 2, cs42888_adcfilter), + SOC_ENUM_DOUBLE(CS42888_DACINV, 0, 1, 2, cs42888_dacinvert), + SOC_ENUM_DOUBLE(CS42888_DACINV, 2, 3, 2, cs42888_dacinvert), + SOC_ENUM_DOUBLE(CS42888_DACINV, 4, 5, 2, cs42888_dacinvert), + SOC_ENUM_DOUBLE(CS42888_DACINV, 6, 7, 2, cs42888_dacinvert), + SOC_ENUM_DOUBLE(CS42888_ADCINV, 0, 1, 2, cs42888_adcinvert), + SOC_ENUM_DOUBLE(CS42888_ADCINV, 2, 3, 2, cs42888_adcinvert), + SOC_ENUM_SINGLE(CS42888_TRANS, 4, 2, cs42888_dacamute), + SOC_ENUM_SINGLE(CS42888_TRANS, 7, 2, cs42888_dac_sngvol), + SOC_ENUM_SINGLE(CS42888_TRANS, 5, 4, cs42888_dac_szc), + SOC_ENUM_SINGLE(CS42888_TRANS, 3, 2, cs42888_mute_adc), + SOC_ENUM_SINGLE(CS42888_TRANS, 2, 2, cs42888_adc_sngvol), + SOC_ENUM_SINGLE(CS42888_TRANS, 0, 4, cs42888_adc_szc), + SOC_ENUM_SINGLE(CS42888_ADCCTL, 5, 2, cs42888_dac_dem), + SOC_ENUM_SINGLE(CS42888_ADCCTL, 4, 2, cs42888_adc_single), + SOC_ENUM_SINGLE(CS42888_ADCCTL, 3, 2, cs42888_adc_single), +}; + +static const struct snd_kcontrol_new cs42888_snd_controls[] = { +SOC_CS42888_DOUBLE_R_TLV("DAC1 Playback Volume", + CS42888_VOLAOUT1, + CS42888_VOLAOUT2, + 0, 0xff, 1, dac_tlv), +SOC_CS42888_DOUBLE_R_TLV("DAC2 Playback Volume", + CS42888_VOLAOUT3, + CS42888_VOLAOUT4, + 0, 0xff, 1, dac_tlv), +SOC_CS42888_DOUBLE_R_TLV("DAC3 Playback Volume", + CS42888_VOLAOUT5, + CS42888_VOLAOUT6, + 0, 0xff, 1, dac_tlv), +SOC_CS42888_DOUBLE_R_TLV("DAC4 Playback Volume", + CS42888_VOLAOUT7, + CS42888_VOLAOUT8, + 0, 0xff, 1, dac_tlv), +SOC_CS42888_DOUBLE_R_S8_TLV("ADC1 Capture Volume", + CS42888_VOLAIN1, + CS42888_VOLAIN2, + -128, 48, adc_tlv), +SOC_CS42888_DOUBLE_R_S8_TLV("ADC2 Capture Volume", + CS42888_VOLAIN3, + CS42888_VOLAIN4, + -128, 48, adc_tlv), +SOC_ENUM("ADC High-Pass Filter Switch", cs42888_enum[0]), +SOC_ENUM("DAC1 Invert Switch", cs42888_enum[1]), +SOC_ENUM("DAC2 Invert Switch", cs42888_enum[2]), +SOC_ENUM("DAC3 Invert Switch", cs42888_enum[3]), +SOC_ENUM("DAC4 Invert Switch", cs42888_enum[4]), +SOC_ENUM("ADC1 Invert Switch", cs42888_enum[5]), +SOC_ENUM("ADC2 Invert Switch", cs42888_enum[6]), +SOC_ENUM("DAC Auto Mute Switch", cs42888_enum[7]), +SOC_ENUM("DAC Single Volume Control Switch", cs42888_enum[8]), +SOC_ENUM("DAC Soft Ramp and Zero Cross Control Switch", cs42888_enum[9]), +SOC_ENUM("Mute ADC Serial Port Switch", cs42888_enum[10]), +SOC_ENUM("ADC Single Volume Control Switch", cs42888_enum[11]), +SOC_ENUM("ADC Soft Ramp and Zero Cross Control Switch", cs42888_enum[12]), +SOC_ENUM("DAC Deemphasis Switch", cs42888_enum[13]), +SOC_ENUM("ADC1 Single Ended Mode Switch", cs42888_enum[14]), +SOC_ENUM("ADC2 Single Ended Mode Switch", cs42888_enum[15]), +}; + + +static const struct snd_soc_dapm_widget cs42888_dapm_widgets[] = { +SND_SOC_DAPM_DAC("DAC1", "Playback", CS42888_PWRCTL, 1, 1), +SND_SOC_DAPM_DAC("DAC2", "Playback", CS42888_PWRCTL, 2, 1), +SND_SOC_DAPM_DAC("DAC3", "Playback", CS42888_PWRCTL, 3, 1), +SND_SOC_DAPM_DAC("DAC4", "Playback", CS42888_PWRCTL, 4, 1), + +SND_SOC_DAPM_OUTPUT("AOUT1L"), +SND_SOC_DAPM_OUTPUT("AOUT1R"), +SND_SOC_DAPM_OUTPUT("AOUT2L"), +SND_SOC_DAPM_OUTPUT("AOUT2R"), +SND_SOC_DAPM_OUTPUT("AOUT3L"), +SND_SOC_DAPM_OUTPUT("AOUT3R"), +SND_SOC_DAPM_OUTPUT("AOUT4L"), +SND_SOC_DAPM_OUTPUT("AOUT4R"), + +SND_SOC_DAPM_ADC("ADC1", "Capture", CS42888_PWRCTL, 5, 1), +SND_SOC_DAPM_ADC("ADC2", "Capture", CS42888_PWRCTL, 6, 1), + +SND_SOC_DAPM_INPUT("AIN1L"), +SND_SOC_DAPM_INPUT("AIN1R"), +SND_SOC_DAPM_INPUT("AIN2L"), +SND_SOC_DAPM_INPUT("AIN2R"), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Playback */ + { "AOUT1L", NULL, "DAC1" }, + { "AOUT1R", NULL, "DAC1" }, + + { "AOUT2L", NULL, "DAC2" }, + { "AOUT2R", NULL, "DAC2" }, + + { "AOUT3L", NULL, "DAC3" }, + { "AOUT3R", NULL, "DAC3" }, + + { "AOUT4L", NULL, "DAC4" }, + { "AOUT4R", NULL, "DAC4" }, + + /* Capture */ + { "ADC1", NULL, "AIN1L" }, + { "ADC1", NULL, "AIN1R" }, + + { "ADC2", NULL, "AIN2L" }, + { "ADC2", NULL, "AIN2R" }, +}; + + +static int ca42888_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, cs42888_dapm_widgets, + ARRAY_SIZE(cs42888_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +/** + * struct cs42888_mode_ratios - clock ratio tables + * @ratio: the ratio of MCLK to the sample rate + * @speed_mode: the Speed Mode bits to set in the Mode Control register for + * this ratio + * @mclk: the Ratio Select bits to set in the Mode Control register for this + * ratio + * + * The data for this chart is taken from Table 10 of the CS42888 reference + * manual. + * + * This table is used to determine how to program the Functional Mode register. + * It is also used by cs42888_set_dai_sysclk() to tell ALSA which sampling + * rates the CS42888 currently supports. + * + * @speed_mode is the corresponding bit pattern to be written to the + * MODE bits of the Mode Control Register + * + * @mclk is the corresponding bit pattern to be wirten to the MCLK bits of + * the Mode Control Register. + * + */ +struct cs42888_mode_ratios { + unsigned int ratio; + u8 speed_mode; + u8 mclk; +}; + +static struct cs42888_mode_ratios cs42888_mode_ratios[] = { + {64, CS42888_MODE_4X, CS42888_MODE_DIV1}, + {96, CS42888_MODE_4X, CS42888_MODE_DIV2}, + {128, CS42888_MODE_2X, CS42888_MODE_DIV1}, + {192, CS42888_MODE_2X, CS42888_MODE_DIV2}, + {256, CS42888_MODE_1X, CS42888_MODE_DIV1}, + {384, CS42888_MODE_2X, CS42888_MODE_DIV4}, + {512, CS42888_MODE_1X, CS42888_MODE_DIV3}, + {768, CS42888_MODE_1X, CS42888_MODE_DIV4}, + {1024, CS42888_MODE_1X, CS42888_MODE_DIV5} +}; + +/* The number of MCLK/LRCK ratios supported by the CS42888 */ +#define NUM_MCLK_RATIOS ARRAY_SIZE(cs42888_mode_ratios) + +/** + * cs42888_set_dai_sysclk - determine the CS42888 samples rates. + * @codec_dai: the codec DAI + * @clk_id: the clock ID (ignored) + * @freq: the MCLK input frequency + * @dir: the clock direction (ignored) + * + * This function is used to tell the codec driver what the input MCLK + * frequency is. + * + */ +static int cs42888_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct cs42888_private *cs42888 = codec->drvdata; + + cs42888->mclk = freq; + + return 0; +} + +/** + * cs42888_set_dai_fmt - configure the codec for the selected audio format + * @codec_dai: the codec DAI + * @format: a SND_SOC_DAIFMT_x value indicating the data format + * + * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the + * codec accordingly. + * + * Currently, this function only supports SND_SOC_DAIFMT_I2S and + * SND_SOC_DAIFMT_LEFT_J. The CS42888 codec also supports right-justified + * data for playback only, but ASoC currently does not support different + * formats for playback vs. record. + */ +static int cs42888_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int format) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct cs42888_private *cs42888 = codec->drvdata; + int ret = 0; + u8 val; + val = cs42888_read_reg_cache(codec, CS42888_FORMAT); + val &= ~CS42888_FORMAT_DAC_DIF_MASK; + val &= ~CS42888_FORMAT_ADC_DIF_MASK; + /* set DAI format */ + switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_LEFT_J: + val |= DIF_LEFT_J << CS42888_FORMAT_DAC_DIF_OFFSET; + val |= DIF_LEFT_J << CS42888_FORMAT_ADC_DIF_OFFSET; + break; + case SND_SOC_DAIFMT_I2S: + val |= DIF_I2S << CS42888_FORMAT_DAC_DIF_OFFSET; + val |= DIF_I2S << CS42888_FORMAT_ADC_DIF_OFFSET; + break; + case SND_SOC_DAIFMT_RIGHT_J: + val |= DIF_RIGHT_J << CS42888_FORMAT_DAC_DIF_OFFSET; + val |= DIF_RIGHT_J << CS42888_FORMAT_ADC_DIF_OFFSET; + break; + default: + dev_err(codec->dev, "invalid dai format\n"); + ret = -EINVAL; + return ret; + } + + ret = cs42888_i2c_write(codec, CS42888_FORMAT, val); + if (ret < 0) { + pr_err("i2c write failed\n"); + return ret; + } + + val = cs42888_read_reg_cache(codec, CS42888_MODE); + /* set master/slave audio interface */ + switch (format & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + cs42888->slave_mode = 1; + val &= ~CS42888_MODE_SPEED_MASK; + val |= CS42888_MODE_SLAVE; + break; + case SND_SOC_DAIFMT_CBM_CFM: + cs42888->slave_mode = 0; + break; + default: + /* all other modes are unsupported by the hardware */ + ret = -EINVAL; + return ret; + } + + ret = cs42888_i2c_write(codec, CS42888_MODE, val); + if (ret < 0) { + pr_err("i2c write failed\n"); + return ret; + } + + return ret; +} + +/** + * cs42888_hw_params - program the CS42888 with the given hardware parameters. + * @substream: the audio stream + * @params: the hardware parameters to set + + * @dai: the SOC DAI (ignored) + * + * This function programs the hardware with the values provided. + * Specifically, the sample rate and the data format. + * + * The .ops functions are used to provide board-specific data, like input + * frequencies, to this driver. This function takes that information, + * combines it with the hardware parameters provided, and programs the + * hardware accordingly. + */ +static int cs42888_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct cs42888_private *cs42888 = codec->drvdata; + int ret; + unsigned int i; + unsigned int rate; + unsigned int ratio; + u8 val; + + rate = params_rate(params); /* Sampling rate, in Hz */ + ratio = cs42888->mclk / rate; /* MCLK/LRCK ratio */ + + for (i = 0; i < NUM_MCLK_RATIOS; i++) { + if (cs42888_mode_ratios[i].ratio == ratio) + break; + } + + if (i == NUM_MCLK_RATIOS) { + /* We did not find a matching ratio */ + dev_err(codec->dev, "could not find matching ratio\n"); + return -EINVAL; + } + + if (!cs42888->slave_mode) { + val = cs42888_read_reg_cache(codec, CS42888_MODE); + val &= ~CS42888_MODE_SPEED_MASK; + val |= cs42888_mode_ratios[i].speed_mode; + val &= ~CS42888_MODE_DIV_MASK; + val |= cs42888_mode_ratios[i].mclk; + } else { + val = cs42888_read_reg_cache(codec, CS42888_MODE); + val &= ~CS42888_MODE_SPEED_MASK; + val |= CS42888_MODE_SLAVE; + val &= ~CS42888_MODE_DIV_MASK; + val |= cs42888_mode_ratios[i].mclk; + } + ret = cs42888_i2c_write(codec, CS42888_MODE, val); + if (ret < 0) { + pr_err("i2c write failed\n"); + return ret; + } + + /* Out of low power state */ + val = cs42888_read_reg_cache(codec, CS42888_PWRCTL); + val &= ~CS42888_PWRCTL_PDN_MASK; + ret = cs42888_i2c_write(codec, CS42888_PWRCTL, val); + if (ret < 0) { + pr_err("i2c write failed\n"); + return ret; + } + + /* Unmute all the channels */ + val = cs42888_read_reg_cache(codec, CS42888_MUTE); + val &= ~CS42888_MUTE_ALL; + ret = cs42888_i2c_write(codec, CS42888_MUTE, val); + if (ret < 0) { + pr_err("i2c write failed\n"); + return ret; + } + + ret = cs42888_fill_cache(codec); + if (ret < 0) { + pr_err("failed to fill register cache\n"); + return ret; + } + + return ret; +} + +/** + * cs42888_shutdown - cs42888 enters into low power mode again. + * @substream: the audio stream + * @dai: the SOC DAI (ignored) + * + * The .ops functions are used to provide board-specific data, like input + * frequencies, to this driver. This function takes that information, + * combines it with the hardware parameters provided, and programs the + * hardware accordingly. + */ +static void cs42888_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + int ret; + u8 val; + + /* Mute all the channels */ + val = cs42888_read_reg_cache(codec, CS42888_MUTE); + val |= CS42888_MUTE_ALL; + ret = cs42888_i2c_write(codec, CS42888_MUTE, val); + if (ret < 0) + pr_err("i2c write failed\n"); + + /* Enter low power state */ + val = cs42888_read_reg_cache(codec, CS42888_PWRCTL); + val |= CS42888_PWRCTL_PDN_MASK; + ret = cs42888_i2c_write(codec, CS42888_PWRCTL, val); + if (ret < 0) + pr_err("i2c write failed\n"); +} + +/* + * cs42888_codec - global variable to store codec for the ASoC probe function + * + * If struct i2c_driver had a private_data field, we wouldn't need to use + * cs42888_codec. This is the only way to pass the codec structure from + * cs42888_i2c_probe() to cs42888_probe(). Unfortunately, there is no good + * way to synchronize these two functions. cs42888_i2c_probe() can be called + * multiple times before cs42888_probe() is called even once. So for now, we + * also only allow cs42888_i2c_probe() to be run once. That means that we do + * not support more than one cs42888 device in the system, at least for now. + */ +static struct snd_soc_codec *cs42888_codec; + +static struct snd_soc_dai_ops cs42888_dai_ops = { + .set_fmt = cs42888_set_dai_fmt, + .set_sysclk = cs42888_set_dai_sysclk, + .hw_params = cs42888_hw_params, + .shutdown = cs42888_shutdown, +}; + +struct snd_soc_dai cs42888_dai = { + .name = "CS42888", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 8, + .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_176400), + .formats = CS42888_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 4, + .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_176400), + .formats = CS42888_FORMATS, + }, + .ops = &cs42888_dai_ops, +}; +EXPORT_SYMBOL_GPL(cs42888_dai); + +/** + * cs42888_probe - ASoC probe function + * @pdev: platform device + * + * This function is called when ASoC has all the pieces it needs to + * instantiate a sound driver. + */ +static int cs42888_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = cs42888_codec; + int ret; + + /* Connect the codec to the socdev. snd_soc_new_pcms() needs this. */ + socdev->card->codec = codec; + + /* Register PCMs */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(codec->dev, "failed to create pcms\n"); + return ret; + } + + /* Add the non-DAPM controls */ + ret = snd_soc_add_controls(codec, cs42888_snd_controls, + ARRAY_SIZE(cs42888_snd_controls)); + if (ret < 0) { + dev_err(codec->dev, "failed to add controls\n"); + goto error_free_pcms; + } + + /* Add DAPM controls */ + ca42888_add_widgets(codec); + + return 0; + +error_free_pcms: + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + + return ret; +} + +/** + * cs42888_remove - ASoC remove function + * @pdev: platform device + * + * This function is the counterpart to cs42888_probe(). + */ +static int cs42888_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + + return 0; +}; + + +/** + * cs42888_i2c_probe - initialize the I2C interface of the CS42888 + * @i2c_client: the I2C client object + * @id: the I2C device ID (ignored) + * + * This function is called whenever the I2C subsystem finds a device that + * matches the device ID given via a prior call to i2c_add_driver(). + */ +static int cs42888_i2c_probe(struct i2c_client *i2c_client, + const struct i2c_device_id *id) +{ + struct snd_soc_codec *codec; + struct cs42888_private *cs42888; + int ret; + struct mxc_audio_codec_platform_data *plat_data = + i2c_client->dev.platform_data; + u8 val; + + if (cs42888_codec) { + dev_err(&i2c_client->dev, + "Multiple CS42888 devices not supported\n"); + return -ENOMEM; + } + + cs42888_i2c_client = i2c_client; + + /* Allocate enough space for the snd_soc_codec structure + and our private data together. */ + cs42888 = kzalloc(sizeof(struct cs42888_private), GFP_KERNEL); + if (!cs42888) { + dev_err(&i2c_client->dev, "could not allocate codec\n"); + return -ENOMEM; + } + + /* hold on reset */ + if (plat_data->pwdn) + plat_data->pwdn(1); + + cs42888->regulator_vsd = + regulator_get(&i2c_client->dev, plat_data->analog_regulator); + if (!IS_ERR(cs42888->regulator_vsd)) { + regulator_set_voltage(cs42888->regulator_vsd, + 2800000, 2800000); + if (regulator_enable(cs42888->regulator_vsd) != 0) { + pr_err("%s:VSD set voltage error\n", __func__); + } else { + dev_dbg(&i2c_client->dev, + "%s:io set voltage ok\n", __func__); + } + } + + msleep(1); + /* out of reset state */ + if (plat_data->pwdn) + plat_data->pwdn(0); + + /* Verify that we have a CS42888 */ + ret = cs42888_read_reg(CS42888_CHIPID, &val); + if (ret < 0) { + pr_err("Device with ID register %x is not a CS42888", val); + return -ENODEV; + } + /* The top four bits of the chip ID should be 0000. */ + if ((val & CS42888_CHIPID_ID_MASK) != 0x00) { + dev_err(&i2c_client->dev, "device is not a CS42888\n"); + return -ENODEV; + } + + dev_info(&i2c_client->dev, "found device at i2c address %X\n", + i2c_client->addr); + dev_info(&i2c_client->dev, "hardware revision %X\n", val & 0xF); + + codec = &cs42888->codec; + codec->hw_write = (hw_write_t)i2c_master_send; + + i2c_set_clientdata(i2c_client, cs42888); + codec->control_data = i2c_client; + + codec->dev = &i2c_client->dev; + + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + codec->drvdata = cs42888; + codec->name = "CS42888"; + codec->owner = THIS_MODULE; + codec->read = cs42888_read_reg_cache; + codec->write = cs42888_i2c_write; + codec->dai = &cs42888_dai; + codec->num_dai = 1; + codec->reg_cache = cs42888->reg_cache; + codec->reg_cache_size = ARRAY_SIZE(cs42888->reg_cache); + + /* The I2C interface is set up, so pre-fill our register cache */ + ret = cs42888_fill_cache(codec); + if (ret < 0) { + dev_err(&i2c_client->dev, "failed to fill register cache\n"); + goto error_free_codec; + } + + /* Enter low power state */ + val = cs42888_read_reg_cache(codec, CS42888_PWRCTL); + val |= CS42888_PWRCTL_PDN_MASK; + ret = cs42888_i2c_write(codec, CS42888_PWRCTL, val); + if (ret < 0) { + dev_err(&i2c_client->dev, "i2c write failed\n"); + return ret; + } + + /* Disable auto-mute */ + val = cs42888_read_reg_cache(codec, CS42888_TRANS); + val &= ~CS42888_TRANS_AMUTE_MASK; + ret = cs42888_i2c_write(codec, CS42888_TRANS, val); + if (ret < 0) { + pr_err("i2c write failed\n"); + return ret; + } + + cs42888_dai.dev = &i2c_client->dev; + + cs42888_codec = codec; + ret = snd_soc_register_codec(codec); + if (ret != 0) { + dev_err(&i2c_client->dev, + "Failed to register codec: %d\n", ret); + goto error_free_codec; + } + + ret = snd_soc_register_dai(&cs42888_dai); + if (ret < 0) { + dev_err(&i2c_client->dev, "failed to register DAIe\n"); + goto error_codec; + } + + return 0; + +error_codec: + snd_soc_unregister_codec(codec); +error_free_codec: + kfree(cs42888); + cs42888_codec = NULL; + cs42888_dai.dev = NULL; + + return ret; +} + +/** + * cs42888_i2c_remove - remove an I2C device + * @i2c_client: the I2C client object + * + * This function is the counterpart to cs42888_i2c_probe(). + */ +static int cs42888_i2c_remove(struct i2c_client *i2c_client) +{ + struct cs42888_private *cs42888 = i2c_get_clientdata(i2c_client); + + snd_soc_unregister_dai(&cs42888_dai); + snd_soc_unregister_codec(&cs42888->codec); + kfree(cs42888); + cs42888_codec = NULL; + cs42888_dai.dev = NULL; + + return 0; +} + +/* + * cs42888_i2c_id - I2C device IDs supported by this driver + */ +static struct i2c_device_id cs42888_i2c_id[] = { + {"cs42888", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, cs42888_i2c_id); + +#ifdef CONFIG_PM + +/* This suspend/resume implementation can handle both - a simple standby + * where the codec remains powered, and a full suspend, where the voltage + * domain the codec is connected to is teared down and/or any other hardware + * reset condition is asserted. + * + * The codec's own power saving features are enabled in the suspend callback, + * and all registers are written back to the hardware when resuming. + */ + +static int cs42888_i2c_suspend(struct i2c_client *client, pm_message_t mesg) +{ + struct cs42888_private *cs42888 = i2c_get_clientdata(client); + struct snd_soc_codec *codec = &cs42888->codec; + int reg = snd_soc_read(codec, CS42888_PWRCTL) | CS42888_PWRCTL_PDN_MASK; + + return snd_soc_write(codec, CS42888_PWRCTL, reg); +} + +static int cs42888_i2c_resume(struct i2c_client *client) +{ + struct cs42888_private *cs42888 = i2c_get_clientdata(client); + struct snd_soc_codec *codec = &cs42888->codec; + int reg; + + /* In case the device was put to hard reset during sleep, we need to + * wait 500ns here before any I2C communication. */ + ndelay(500); + + /* first restore the entire register cache ... */ + for (reg = CS42888_FIRSTREG; reg <= CS42888_LASTREG; reg++) { + u8 val = snd_soc_read(codec, reg); + + if (i2c_smbus_write_byte_data(client, reg, val)) { + dev_err(codec->dev, "i2c write failed\n"); + return -EIO; + } + } + + /* ... then disable the power-down bits */ + reg = snd_soc_read(codec, CS42888_PWRCTL); + reg &= ~CS42888_PWRCTL_PDN_MASK; + + return snd_soc_write(codec, CS42888_PWRCTL, reg); +} +#else +#define cs42888_i2c_suspend NULL +#define cs42888_i2c_resume NULL +#endif /* CONFIG_PM */ + +/* + * cs42888_i2c_driver - I2C device identification + * + * This structure tells the I2C subsystem how to identify and support a + * given I2C device type. + */ +static struct i2c_driver cs42888_i2c_driver = { + .driver = { + .name = "cs42888", + .owner = THIS_MODULE, + }, + .id_table = cs42888_i2c_id, + .probe = cs42888_i2c_probe, + .remove = cs42888_i2c_remove, + .suspend = cs42888_i2c_suspend, + .resume = cs42888_i2c_resume, +}; + +/* + * ASoC codec device structure + * + * Assign this variable to the codec_dev field of the machine driver's + * snd_soc_device structure. + */ +struct snd_soc_codec_device soc_codec_device_cs42888 = { + .probe = cs42888_probe, + .remove = cs42888_remove +}; +EXPORT_SYMBOL_GPL(soc_codec_device_cs42888); + +static int __init cs42888_init(void) +{ + pr_info("Cirrus Logic CS42888 ALSA SoC Codec Driver\n"); + + return i2c_add_driver(&cs42888_i2c_driver); +} +module_init(cs42888_init); + +static void __exit cs42888_exit(void) +{ + i2c_del_driver(&cs42888_i2c_driver); +} +module_exit(cs42888_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Cirrus Logic CS42888 ALSA SoC Codec Driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/cs42888.h b/sound/soc/codecs/cs42888.h new file mode 100644 index 000000000000..a2c8562c17c5 --- /dev/null +++ b/sound/soc/codecs/cs42888.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _CS42888_H +#define _CS42888_H + +/* + * The ASoC codec DAI structure for the CS42888. Assign this structure to + * the .codec_dai field of your machine driver's snd_soc_dai_link structure. + */ +extern struct snd_soc_dai cs42888_dai; + +/* + * The ASoC codec device structure for the CS42888. Assign this structure + * to the .codec_dev field of your machine driver's snd_soc_device + * structure. + */ +extern struct snd_soc_codec_device soc_codec_device_cs42888; + +extern void gpio_cs42888_pdwn(int pdwn); +#endif diff --git a/sound/soc/codecs/mxs-adc-codec.c b/sound/soc/codecs/mxs-adc-codec.c new file mode 100644 index 000000000000..34c06623e7c7 --- /dev/null +++ b/sound/soc/codecs/mxs-adc-codec.c @@ -0,0 +1,1214 @@ +/* + * ALSA codec for Freescale MXS ADC/DAC Audio + * + * Author: Vladislav Buzov + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "mxs-adc-codec.h" + +#define BV_AUDIOIN_ADCVOL_SELECT__MIC 0x00 /* missing define */ + +#ifndef BF +#define BF(value, field) (((value) << BP_##field) & BM_##field) +#endif + +#define BM_RTC_PERSISTENT0_RELEASE_GND BF(0x2, RTC_PERSISTENT0_SPARE_ANALOG) + +#define REGS_RTC_BASE (IO_ADDRESS(RTC_PHYS_ADDR)) + +struct mxs_codec_priv { + struct clk *clk; + struct snd_soc_codec codec; +}; + +/* + * ALSA API + */ +static void __iomem *adc_regmap[] = { + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_STAT, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACSRR, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACDEBUG, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_TEST, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTCTRL, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT0, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT1, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACLKCTRL, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DATA, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_VERSION, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL, + REGS_AUDIOIN_BASE + HW_AUDIOIN_STAT, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCSRR, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCDEBUG, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL, + REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ANACLKCTRL, + REGS_AUDIOIN_BASE + HW_AUDIOIN_DATA, +}; + +static u16 mxs_audio_regs[ADC_REGNUM]; + +static u8 dac_volumn_control_word[] = { + 0x37, 0x5e, 0x7e, 0x8e, + 0x9e, 0xae, 0xb6, 0xbe, + 0xc6, 0xce, 0xd6, 0xde, + 0xe6, 0xee, 0xf6, 0xfe, +}; + +/* + * ALSA core supports only 16 bit registers. It means we have to simulate it + * by virtually splitting a 32bit ADC/DAC registers into two halves + * high (bits 31:16) and low (bits 15:0). The routins abow detects which part + * of 32bit register is accessed. + */ +static void mxs_codec_write_cache(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + if (reg < ADC_REGNUM) + cache[reg] = value; +} + +static int mxs_codec_write(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + unsigned int reg_val; + unsigned int mask = 0xffff; + + if (reg >= ADC_REGNUM) + return -EIO; + + mxs_codec_write_cache(codec, reg, value); + + if (reg & 0x1) { + mask <<= 16; + value <<= 16; + } + + reg_val = __raw_readl(adc_regmap[reg >> 1]); + reg_val = (reg_val & ~mask) | value; + __raw_writel(reg_val, adc_regmap[reg >> 1]); + + return 0; +} + +static unsigned int mxs_codec_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + unsigned int reg_val; + + if (reg >= ADC_REGNUM) + return -1; + + reg_val = __raw_readl(adc_regmap[reg >> 1]); + if (reg & 1) + reg_val >>= 16; + + return reg_val & 0xffff; +} + +static unsigned int mxs_codec_read_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + if (reg >= ADC_REGNUM) + return -EINVAL; + return cache[reg]; +} + +static void mxs_codec_sync_reg_cache(struct snd_soc_codec *codec) +{ + int reg; + for (reg = 0; reg < ADC_REGNUM; reg += 1) + mxs_codec_write_cache(codec, reg, + mxs_codec_read(codec, reg)); +} + +static int mxs_codec_restore_reg(struct snd_soc_codec *codec, + unsigned int reg) +{ + unsigned int cached_val, hw_val; + + cached_val = mxs_codec_read_cache(codec, reg); + hw_val = mxs_codec_read(codec, reg); + + if (hw_val != cached_val) + return mxs_codec_write(codec, reg, cached_val); + + return 0; +} + +static int dac_info_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 2; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 0xf; + return 0; +} + +static int dac_get_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int reg, l, r; + int i; + + reg = __raw_readl(REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME); + + l = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) >> + BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT; + r = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) >> + BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT; + /*Left channel */ + i = 0; + while (i < 16) { + if (l == dac_volumn_control_word[i]) { + ucontrol->value.integer.value[0] = i; + break; + } + i++; + } + if (i == 16) + ucontrol->value.integer.value[0] = i; + /*Right channel */ + i = 0; + while (i < 16) { + if (r == dac_volumn_control_word[i]) { + ucontrol->value.integer.value[1] = i; + break; + } + i++; + } + if (i == 16) + ucontrol->value.integer.value[1] = i; + + return 0; +} + +static int dac_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int reg, l, r; + int i; + + i = ucontrol->value.integer.value[0]; + l = dac_volumn_control_word[i]; + /*Get dac volume for left channel */ + reg = BF(l, AUDIOOUT_DACVOLUME_VOLUME_LEFT); + + i = ucontrol->value.integer.value[1]; + r = dac_volumn_control_word[i]; + /*Get dac volume for right channel */ + reg = reg | BF(r, AUDIOOUT_DACVOLUME_VOLUME_RIGHT); + + /*Clear left/right dac volume */ + __raw_writel(BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT | + BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_CLR); + __raw_writel(reg, REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_SET); + + return 0; +} + +static int pga_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* Prepare powering up HP and SPEAKER output */ + __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET); + __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND, + REGS_RTC_BASE + HW_RTC_PERSISTENT0_SET); + msleep(100); + break; + case SND_SOC_DAPM_POST_PMU: + __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + break; + case SND_SOC_DAPM_POST_PMD: + __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND, + REGS_RTC_BASE + HW_RTC_PERSISTENT0_CLR); + break; + } + return 0; +} + +static int adc_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND, + REGS_RTC_BASE + HW_RTC_PERSISTENT0_SET); + msleep(100); + break; + case SND_SOC_DAPM_POST_PMD: + __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND, + REGS_RTC_BASE + HW_RTC_PERSISTENT0_CLR); + break; + } + return 0; +} + +static const char *mxs_codec_adc_input_sel[] = { + "Mic", "Line In 1", "Head Phone", "Line In 2" }; + +static const char *mxs_codec_hp_output_sel[] = { "DAC Out", "Line In 1" }; + +static const char *mxs_codec_adc_3d_sel[] = { + "Off", "Low", "Medium", "High" }; + +static const struct soc_enum mxs_codec_enum[] = { + SOC_ENUM_SINGLE(ADC_ADCVOL_L, 12, 4, mxs_codec_adc_input_sel), + SOC_ENUM_SINGLE(ADC_ADCVOL_L, 4, 4, mxs_codec_adc_input_sel), + SOC_ENUM_SINGLE(DAC_HPVOL_H, 0, 2, mxs_codec_hp_output_sel), + SOC_ENUM_SINGLE(DAC_CTRL_L, 8, 4, mxs_codec_adc_3d_sel), +}; + +/* Codec controls */ +static const struct snd_kcontrol_new mxs_snd_controls[] = { + /* Playback Volume */ + {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "DAC Playback Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | + SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = dac_info_volsw, + .get = dac_get_volsw, + .put = dac_put_volsw, + }, + + SOC_DOUBLE_R("DAC Playback Switch", + DAC_VOLUME_H, DAC_VOLUME_L, 8, 0x01, 1), + SOC_DOUBLE("HP Playback Volume", DAC_HPVOL_L, 8, 0, 0x7F, 1), + + /* Capture Volume */ + SOC_DOUBLE_R("ADC Capture Volume", + ADC_VOLUME_H, ADC_VOLUME_L, 0, 0xFF, 0), + SOC_DOUBLE("ADC PGA Capture Volume", ADC_ADCVOL_L, 8, 0, 0x0F, 0), + SOC_SINGLE("ADC PGA Capture Switch", ADC_ADCVOL_H, 8, 0x1, 1), + SOC_SINGLE("Mic PGA Capture Volume", ADC_MICLINE_L, 0, 0x03, 0), + + /* Virtual 3D effect */ + SOC_ENUM("3D effect", mxs_codec_enum[3]), +}; + +/* Left ADC Mux */ +static const struct snd_kcontrol_new mxs_left_adc_controls = +SOC_DAPM_ENUM("Route", mxs_codec_enum[0]); + +/* Right ADC Mux */ +static const struct snd_kcontrol_new mxs_right_adc_controls = +SOC_DAPM_ENUM("Route", mxs_codec_enum[1]); + +/* Head Phone Mux */ +static const struct snd_kcontrol_new mxs_hp_controls = +SOC_DAPM_ENUM("Route", mxs_codec_enum[2]); + +static const struct snd_soc_dapm_widget mxs_codec_widgets[] = { + + SND_SOC_DAPM_ADC_E("ADC", "Capture", DAC_PWRDN_L, 8, 1, adc_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_DAC("DAC", "Playback", DAC_PWRDN_L, 12, 1), + + SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, + &mxs_left_adc_controls), + SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, + &mxs_right_adc_controls), + SND_SOC_DAPM_MUX("HP Mux", SND_SOC_NOPM, 0, 0, + &mxs_hp_controls), + SND_SOC_DAPM_PGA_E("HP AMP", DAC_PWRDN_L, 0, 1, NULL, 0, pga_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_PGA("SPEAKER AMP", DAC_PWRDN_H, 8, 1, NULL, 0), + SND_SOC_DAPM_INPUT("LINE1L"), + SND_SOC_DAPM_INPUT("LINE1R"), + SND_SOC_DAPM_INPUT("LINE2L"), + SND_SOC_DAPM_INPUT("LINE2R"), + SND_SOC_DAPM_INPUT("MIC"), + + SND_SOC_DAPM_OUTPUT("SPEAKER"), + SND_SOC_DAPM_OUTPUT("HPL"), + SND_SOC_DAPM_OUTPUT("HPR"), +}; + +static const struct snd_soc_dapm_route intercon[] = { + + /* Left ADC Mux */ + {"Left ADC Mux", "Mic", "MIC"}, + {"Left ADC Mux", "Line In 1", "LINE1L"}, + {"Left ADC Mux", "Line In 2", "LINE2L"}, + {"Left ADC Mux", "Head Phone", "HPL"}, + + /* Right ADC Mux */ + {"Right ADC Mux", "Mic", "MIC"}, + {"Right ADC Mux", "Line In 1", "LINE1R"}, + {"Right ADC Mux", "Line In 2", "LINE2R"}, + {"Right ADC Mux", "Head Phone", "HPR"}, + + /* ADC */ + {"ADC", NULL, "Left ADC Mux"}, + {"ADC", NULL, "Right ADC Mux"}, + + /* HP Mux */ + {"HP Mux", "DAC Out", "DAC"}, + {"HP Mux", "Line In 1", "LINE1L"}, + {"HP Mux", "Line In 1", "LINE1R"}, + + /* HP amp */ + {"HP AMP", NULL, "HP Mux"}, + /* HP output */ + {"HPR", NULL, "HP AMP"}, + {"HPL", NULL, "HP AMP"}, + + /* Speaker amp */ + {"SPEAKER AMP", NULL, "DAC"}, + {"SPEAKER", NULL, "SPEAKER AMP"}, +}; + +static int mxs_codec_add_widgets(struct snd_soc_codec *codec) +{ + int ret = 0; + + snd_soc_dapm_new_controls(codec, mxs_codec_widgets, + ARRAY_SIZE(mxs_codec_widgets)); + + if (ret) { + dev_err(codec->dev, "dapm control register failed\n"); + return ret; + } + /* set up audio path interconnects */ + snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); + + if (ret) { + dev_err(codec->dev, "DAPM route register failed\n"); + return ret; + } + + return snd_soc_dapm_new_widgets(codec); +} + +struct dac_srr { + u32 rate; + u32 basemult; + u32 src_hold; + u32 src_int; + u32 src_frac; +}; + +static struct dac_srr srr_values[] = { + {192000, 0x4, 0x0, 0x0F, 0x13FF}, + {176400, 0x4, 0x0, 0x11, 0x0037}, + {128000, 0x4, 0x0, 0x17, 0x0E00}, + {96000, 0x2, 0x0, 0x0F, 0x13FF}, + {88200, 0x2, 0x0, 0x11, 0x0037}, + {64000, 0x2, 0x0, 0x17, 0x0E00}, + {48000, 0x1, 0x0, 0x0F, 0x13FF}, + {44100, 0x1, 0x0, 0x11, 0x0037}, + {32000, 0x1, 0x0, 0x17, 0x0E00}, + {24000, 0x1, 0x1, 0x0F, 0x13FF}, + {22050, 0x1, 0x1, 0x11, 0x0037}, + {16000, 0x1, 0x1, 0x17, 0x0E00}, + {12000, 0x1, 0x3, 0x0F, 0x13FF}, + {11025, 0x1, 0x3, 0x11, 0x0037}, + {8000, 0x1, 0x3, 0x17, 0x0E00} +}; + +static inline int get_srr_values(int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(srr_values); i++) + if (srr_values[i].rate == rate) + return i; + + return -1; +} + +static int mxs_codec_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + int i; + u32 srr_value = 0; + u32 src_hold = 0; + + i = get_srr_values(params_rate(params)); + if (i < 0) + dev_warn(socdev->dev, "%s doesn't support rate %d\n", + codec->name, params_rate(params)); + else { + src_hold = srr_values[i].src_hold; + + srr_value = + BF(srr_values[i].basemult, AUDIOOUT_DACSRR_BASEMULT) | + BF(srr_values[i].src_int, AUDIOOUT_DACSRR_SRC_INT) | + BF(srr_values[i].src_frac, AUDIOOUT_DACSRR_SRC_FRAC) | + BF(src_hold, AUDIOOUT_DACSRR_SRC_HOLD); + + if (playback) + __raw_writel(srr_value, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACSRR); + else + __raw_writel(srr_value, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCSRR); + } + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + if (playback) + __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_SET); + else + __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_SET); + + break; + + case SNDRV_PCM_FORMAT_S32_LE: + if (playback) + __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + else + __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + + break; + + default: + dev_warn(socdev->dev, "%s doesn't support format %d\n", + codec->name, params_format(params)); + + } + + return 0; +} + +static int mxs_codec_dig_mute(struct snd_soc_dai *dai, int mute) +{ + int l, r; + int ll, rr; + u32 reg, reg1, reg2; + u32 dac_mask = BM_AUDIOOUT_DACVOLUME_MUTE_LEFT | + BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT; + + if (mute) { + reg = __raw_readl(REGS_AUDIOOUT_BASE + \ + HW_AUDIOOUT_DACVOLUME); + + reg1 = reg & ~BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT; + reg1 = reg1 & ~BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT; + + l = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) >> + BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT; + r = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) >> + BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT; + + /* fade out dac vol */ + while ((l > DAC_VOLUME_MIN) || (r > DAC_VOLUME_MIN)) { + l -= 0x8; + r -= 0x8; + ll = l > DAC_VOLUME_MIN ? l : DAC_VOLUME_MIN; + rr = r > DAC_VOLUME_MIN ? r : DAC_VOLUME_MIN; + reg2 = reg1 | BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(ll) + | BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(rr); + __raw_writel(reg2, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME); + msleep(1); + } + + __raw_writel(dac_mask, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_SET); + reg = reg | dac_mask; + __raw_writel(reg, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME); + } else + __raw_writel(dac_mask, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_CLR); + + return 0; +} + +static int mxs_codec_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + pr_debug("dapm level %d\n", level); + switch (level) { + case SND_SOC_BIAS_ON: /* full On */ + if (codec->bias_level == SND_SOC_BIAS_ON) + break; + break; + + case SND_SOC_BIAS_PREPARE: /* partial On */ + if (codec->bias_level == SND_SOC_BIAS_PREPARE) + break; + /* Set Capless mode */ + __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_CLR); + break; + + case SND_SOC_BIAS_STANDBY: /* Off, with power */ + if (codec->bias_level == SND_SOC_BIAS_STANDBY) + break; + /* Unset Capless mode */ + __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET); + break; + + case SND_SOC_BIAS_OFF: /* Off, without power */ + if (codec->bias_level == SND_SOC_BIAS_OFF) + break; + /* Unset Capless mode */ + __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET); + break; + } + codec->bias_level = level; + return 0; +} + +/* + * Codec initialization + */ +#define VAG_BASE_VALUE ((1400/2 - 625)/25) +static void mxs_codec_dac_set_vag(void) +{ + u32 refctrl_val = __raw_readl(REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL); + + refctrl_val &= ~(BM_AUDIOOUT_REFCTRL_VAG_VAL); + refctrl_val &= ~(BM_AUDIOOUT_REFCTRL_VBG_ADJ); + refctrl_val |= BF(VAG_BASE_VALUE, AUDIOOUT_REFCTRL_VAG_VAL) | + BM_AUDIOOUT_REFCTRL_ADJ_VAG | + BF(0xF, AUDIOOUT_REFCTRL_ADC_REFVAL) | + BM_AUDIOOUT_REFCTRL_ADJ_ADC | + BF(0x3, AUDIOOUT_REFCTRL_VBG_ADJ) | BM_AUDIOOUT_REFCTRL_RAISE_REF; + + __raw_writel(refctrl_val, REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL); +} + +static bool mxs_codec_dac_is_capless() +{ + if ((__raw_readl(REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN) + & BM_AUDIOOUT_PWRDN_CAPLESS) == 0) + return false; + else + return true; +} +static void mxs_codec_dac_arm_short_cm(bool bShort) +{ + __raw_writel(BF(3, AUDIOOUT_ANACTRL_SHORTMODE_CM), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_CM_STS, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + if (bShort) + __raw_writel(BF(1, AUDIOOUT_ANACTRL_SHORTMODE_CM), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET); +} +static void mxs_codec_dac_arm_short_lr(bool bShort) +{ + __raw_writel(BF(3, AUDIOOUT_ANACTRL_SHORTMODE_LR), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + if (bShort) + __raw_writel(BF(1, AUDIOOUT_ANACTRL_SHORTMODE_LR), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET); +} +static void mxs_codec_dac_set_short_trip_level(u8 u8level) +{ + __raw_writel(__raw_readl(REGS_AUDIOOUT_BASE + + HW_AUDIOOUT_ANACTRL) + & (~BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL) + & (~BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR) + | BF(u8level, AUDIOOUT_ANACTRL_SHORT_LVLADJL) + | BF(u8level, AUDIOOUT_ANACTRL_SHORT_LVLADJR), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL); +} +static void mxs_codec_dac_arm_short(bool bLatchCM, bool bLatchLR) +{ + if (bLatchCM) { + if (mxs_codec_dac_is_capless()) + mxs_codec_dac_arm_short_cm(true); + } else + mxs_codec_dac_arm_short_cm(false); + + if (bLatchLR) + mxs_codec_dac_arm_short_lr(true); + else + mxs_codec_dac_arm_short_lr(false); + +} +static void +mxs_codec_dac_power_on(struct mxs_codec_priv *mxs_adc) +{ + /* Ungate DAC clocks */ + __raw_writel(BM_AUDIOOUT_CTRL_CLKGATE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + __raw_writel(BM_AUDIOOUT_ANACLKCTRL_CLKGATE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACLKCTRL_CLR); + + /* 16 bit word length */ + __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_SET); + + /* Arm headphone LR short protect */ + mxs_codec_dac_set_short_trip_level(0); + mxs_codec_dac_arm_short(false, true); + + /* Update DAC volume over zero crossings */ + __raw_writel(BM_AUDIOOUT_DACVOLUME_EN_ZCD, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_SET); + /* Mute DAC */ + __raw_writel(BM_AUDIOOUT_DACVOLUME_MUTE_LEFT | + BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_SET); + + /* Update HP volume over zero crossings */ + __raw_writel(BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_SET); + + __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET); + + /* Mute HP output */ + __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_SET); + /* Mute speaker amp */ + __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL_SET); + /* Enable the audioout */ + __raw_writel(BM_AUDIOOUT_CTRL_RUN, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_SET); +} + +static void +mxs_codec_dac_power_down(struct mxs_codec_priv *mxs_adc) +{ + /* Disable the audioout */ + __raw_writel(BM_AUDIOOUT_CTRL_RUN, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + /* Disable class AB */ + __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + + /* Set hold to ground */ + __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET); + + /* Mute HP output */ + __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_SET); + /* Power down HP output */ + __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET); + + /* Mute speaker amp */ + __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL_SET); + /* Power down speaker amp */ + __raw_writel(BM_AUDIOOUT_PWRDN_SPEAKER, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET); + + /* Mute DAC */ + __raw_writel(BM_AUDIOOUT_DACVOLUME_MUTE_LEFT | + BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_SET); + /* Power down DAC */ + __raw_writel(BM_AUDIOOUT_PWRDN_DAC, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET); + + /* Gate DAC clocks */ + __raw_writel(BM_AUDIOOUT_ANACLKCTRL_CLKGATE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACLKCTRL_SET); + __raw_writel(BM_AUDIOOUT_CTRL_CLKGATE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_SET); +} + +static void +mxs_codec_adc_power_on(struct mxs_codec_priv *mxs_adc) +{ + u32 reg; + + /* Ungate ADC clocks */ + __raw_writel(BM_AUDIOIN_CTRL_CLKGATE, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + __raw_writel(BM_AUDIOIN_ANACLKCTRL_CLKGATE, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ANACLKCTRL_CLR); + + /* 16 bit word length */ + __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_SET); + + /* Unmute ADC channels */ + __raw_writel(BM_AUDIOIN_ADCVOL_MUTE, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_CLR); + + /* + * The MUTE_LEFT and MUTE_RIGHT fields need to be cleared. + * They aren't presented in the datasheet, so this is hardcode. + */ + __raw_writel(0x01000100, REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME_CLR); + + /* Set the Input channel gain 3dB */ + __raw_writel(BM_AUDIOIN_ADCVOL_GAIN_LEFT, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_CLR); + __raw_writel(BM_AUDIOIN_ADCVOL_GAIN_RIGHT, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_CLR); + __raw_writel(BF(2, AUDIOIN_ADCVOL_GAIN_LEFT), + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_SET); + __raw_writel(BF(2, AUDIOIN_ADCVOL_GAIN_RIGHT), + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_SET); + + /* Select default input - Microphone */ + __raw_writel(BM_AUDIOIN_ADCVOL_SELECT_LEFT, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_CLR); + __raw_writel(BM_AUDIOIN_ADCVOL_SELECT_RIGHT, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_CLR); + __raw_writel(BF + (BV_AUDIOIN_ADCVOL_SELECT__MIC, + AUDIOIN_ADCVOL_SELECT_LEFT), + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_SET); + __raw_writel(BF + (BV_AUDIOIN_ADCVOL_SELECT__MIC, + AUDIOIN_ADCVOL_SELECT_RIGHT), + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_SET); + + /* Supply bias voltage to microphone */ + __raw_writel(BF(1, AUDIOIN_MICLINE_MIC_RESISTOR), + REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE_SET); + __raw_writel(BM_AUDIOIN_MICLINE_MIC_SELECT, + REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE_SET); + __raw_writel(BF(1, AUDIOIN_MICLINE_MIC_GAIN), + REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE_SET); + __raw_writel(BF(7, AUDIOIN_MICLINE_MIC_BIAS), + REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE_SET); + + /* Set max ADC volume */ + reg = __raw_readl(REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME); + reg &= ~BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT; + reg &= ~BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT; + reg |= BF(ADC_VOLUME_MAX, AUDIOIN_ADCVOLUME_VOLUME_LEFT); + reg |= BF(ADC_VOLUME_MAX, AUDIOIN_ADCVOLUME_VOLUME_RIGHT); + __raw_writel(reg, REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME); +} + +static void +mxs_codec_adc_power_down(struct mxs_codec_priv *mxs_adc) +{ + /* Mute ADC channels */ + __raw_writel(BM_AUDIOIN_ADCVOL_MUTE, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_SET); + + /* Power Down ADC */ + __raw_writel(BM_AUDIOOUT_PWRDN_ADC | BM_AUDIOOUT_PWRDN_RIGHT_ADC, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET); + + /* Gate ADC clocks */ + __raw_writel(BM_AUDIOIN_CTRL_CLKGATE, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_SET); + __raw_writel(BM_AUDIOIN_ANACLKCTRL_CLKGATE, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ANACLKCTRL_SET); + + /* Disable bias voltage to microphone */ + __raw_writel(BF(0, AUDIOIN_MICLINE_MIC_RESISTOR), + REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE_SET); +} + +static void mxs_codec_dac_enable(struct mxs_codec_priv *mxs_adc) +{ + /* Move DAC codec out of reset */ + __raw_writel(BM_AUDIOOUT_CTRL_SFTRST, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + + /* Reduce analog power */ + __raw_writel(BM_AUDIOOUT_TEST_HP_I1_ADJ, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_TEST_CLR); + __raw_writel(BF(0x1, AUDIOOUT_TEST_HP_I1_ADJ), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_TEST_SET); + __raw_writel(BM_AUDIOOUT_REFCTRL_LOW_PWR, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL_SET); + __raw_writel(BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL_SET); + __raw_writel(BM_AUDIOOUT_REFCTRL_BIAS_CTRL, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL_CLR); + __raw_writel(BF(0x1, AUDIOOUT_REFCTRL_BIAS_CTRL), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL_CLR); + + /* Set Vag value */ + mxs_codec_dac_set_vag(); + + /* Power on DAC codec */ + mxs_codec_dac_power_on(mxs_adc); +} + +static void mxs_codec_dac_disable(struct mxs_codec_priv *mxs_adc) +{ + mxs_codec_dac_power_down(mxs_adc); +} + +static void mxs_codec_adc_enable(struct mxs_codec_priv *mxs_adc) +{ + /* Move ADC codec out of reset */ + __raw_writel(BM_AUDIOIN_CTRL_SFTRST, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + + /* Power on ADC codec */ + mxs_codec_adc_power_on(mxs_adc); +} + +static void mxs_codec_adc_disable(struct mxs_codec_priv *mxs_adc) +{ + mxs_codec_adc_power_down(mxs_adc); +} + +static void mxs_codec_startup(struct snd_soc_codec *codec) +{ + struct mxs_codec_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); + + /* Soft reset DAC block */ + __raw_writel(BM_AUDIOOUT_CTRL_SFTRST, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_SET); + while (!(__raw_readl(REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL) + & BM_AUDIOOUT_CTRL_CLKGATE)){ + } + + /* Soft reset ADC block */ + __raw_writel(BM_AUDIOIN_CTRL_SFTRST, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_SET); + while (!(__raw_readl(REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL) + & BM_AUDIOIN_CTRL_CLKGATE)){ + } + + mxs_codec_dac_enable(mxs_adc); + mxs_codec_adc_enable(mxs_adc); + + /*Sync regs and cache */ + mxs_codec_sync_reg_cache(codec); + + snd_soc_add_controls(codec, mxs_snd_controls, + ARRAY_SIZE(mxs_snd_controls)); + + mxs_codec_add_widgets(codec); +} + +static void mxs_codec_stop(struct snd_soc_codec *codec) +{ + struct mxs_codec_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); + mxs_codec_dac_disable(mxs_adc); + mxs_codec_adc_disable(mxs_adc); +} + +#define MXS_ADC_RATES SNDRV_PCM_RATE_8000_192000 +#define MXS_ADC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_ops mxs_dai_ops = { + .hw_params = mxs_codec_hw_params, + .digital_mute = mxs_codec_dig_mute, +}; + +struct snd_soc_dai mxs_codec_dai = { + .name = "mxs adc/dac", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = MXS_ADC_RATES, + .formats = MXS_ADC_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 2, + .rates = MXS_ADC_RATES, + .formats = MXS_ADC_FORMATS, + }, + .ops = &mxs_dai_ops, +}; +EXPORT_SYMBOL_GPL(mxs_codec_dai); + +static struct snd_soc_codec *mxs_codec; + +static int mxs_codec_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + int ret = 0; + + socdev->card->codec = mxs_codec; + codec = mxs_codec; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(codec->dev, "failed to create pcms\n"); + return ret; + } + + mxs_codec_startup(codec); + + /* Set default bias level*/ + mxs_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + return 0; +} + +static int mxs_codec_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + mxs_codec_stop(codec); + + snd_soc_dapm_free(socdev); + snd_soc_free_pcms(socdev); + + return 0; +} + +#ifdef CONFIG_PM +static int mxs_codec_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + struct mxs_codec_priv *mxs_adc; + int ret = -EINVAL; + + if (codec == NULL) + goto out; + + mxs_adc = snd_soc_codec_get_drvdata(codec); + + mxs_codec_dac_disable(mxs_adc); + mxs_codec_adc_disable(mxs_adc); + clk_disable(mxs_adc->clk); + ret = 0; + +out: + return ret; +} + +static int mxs_codec_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + struct mxs_codec_priv *mxs_adc; + int ret = -EINVAL; + + if (codec == NULL) + goto out; + + mxs_adc = snd_soc_codec_get_drvdata(codec); + clk_enable(mxs_adc->clk); + + /* Soft reset DAC block */ + __raw_writel(BM_AUDIOOUT_CTRL_SFTRST, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_SET); + while (! + (__raw_readl(REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL) + & BM_AUDIOOUT_CTRL_CLKGATE)){ + } + + /* Soft reset ADC block */ + __raw_writel(BM_AUDIOIN_CTRL_SFTRST, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_SET); + while (! + (__raw_readl(REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL) + & BM_AUDIOIN_CTRL_CLKGATE)){ + } + + mxs_codec_dac_enable(mxs_adc); + mxs_codec_adc_enable(mxs_adc); + + /*restore registers relevant to amixer controls */ + mxs_codec_restore_reg(codec, DAC_CTRL_L); + mxs_codec_restore_reg(codec, DAC_VOLUME_L); + mxs_codec_restore_reg(codec, DAC_VOLUME_H); + mxs_codec_restore_reg(codec, DAC_HPVOL_L); + mxs_codec_restore_reg(codec, DAC_HPVOL_H); + mxs_codec_restore_reg(codec, DAC_SPEAKERCTRL_H); + mxs_codec_restore_reg(codec, ADC_VOLUME_L); + mxs_codec_restore_reg(codec, ADC_VOLUME_H); + mxs_codec_restore_reg(codec, ADC_ADCVOL_L); + mxs_codec_restore_reg(codec, ADC_ADCVOL_H); + mxs_codec_restore_reg(codec, ADC_MICLINE_L); + + ret = 0; + +out: + return ret; +} +#else +#define mxs_codec_suspend NULL +#define mxs_codec_resume NULL +#endif /* CONFIG_PM */ + +struct snd_soc_codec_device soc_codec_dev_mxs = { + .probe = mxs_codec_probe, + .remove = mxs_codec_remove, + .suspend = mxs_codec_suspend, + .resume = mxs_codec_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_mxs); + +/* codec register, unregister function */ +static int __init mxs_codec_audio_probe(struct platform_device *pdev) +{ + struct mxs_codec_priv *mxs_adc; + struct snd_soc_codec *codec; + int ret = 0; + + dev_info(&pdev->dev, + "MXS ADC/DAC Audio Codec \n"); + + mxs_adc = kzalloc(sizeof(struct mxs_codec_priv), GFP_KERNEL); + if (mxs_adc == NULL) + return -ENOMEM; + + codec = &mxs_adc->codec; + codec->dev = &pdev->dev; + codec->name = "mxs adc/dac"; + codec->owner = THIS_MODULE; + snd_soc_codec_set_drvdata(codec, mxs_adc); + codec->read = mxs_codec_read; + codec->write = mxs_codec_write; + codec->bias_level = SND_SOC_BIAS_OFF; + codec->set_bias_level = mxs_codec_set_bias_level; + codec->dai = &mxs_codec_dai; + codec->num_dai = 1; + codec->reg_cache_size = sizeof(mxs_audio_regs) >> 1; + codec->reg_cache_step = 1; + codec->reg_cache = (void *)&mxs_audio_regs; + + platform_set_drvdata(pdev, mxs_adc); + + mxs_codec = codec; + + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + /* Turn on audio clock */ + mxs_adc->clk = clk_get(&pdev->dev, "audio"); + if (IS_ERR(mxs_adc->clk)) { + ret = PTR_ERR(mxs_adc->clk); + dev_err(&pdev->dev, "%s: Clocks initialization failed\n", + __func__); + goto clk_err; + } + clk_enable(mxs_adc->clk); + + ret = snd_soc_register_codec(codec); + if (ret) { + dev_err(&pdev->dev, "failed to register card\n"); + goto card_err; + } + + ret = snd_soc_register_dai(&mxs_codec_dai); + if (ret) { + dev_err(&pdev->dev, "failed to register codec dai\n"); + goto dai_err; + } + + return 0; + +dai_err: + snd_soc_unregister_codec(codec); +card_err: + clk_disable(mxs_adc->clk); + clk_put(mxs_adc->clk); +clk_err: + kfree(mxs_adc); + return ret; +} + +static int __devexit mxs_codec_audio_remove(struct platform_device *pdev) +{ + struct mxs_codec_priv *mxs_adc = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = &mxs_adc->codec; + + snd_soc_unregister_codec(codec); + + clk_disable(mxs_adc->clk); + clk_put(mxs_adc->clk); + + kfree(mxs_adc); + + return 0; +} + +struct platform_driver mxs_codec_audio_driver = { + .driver = { + .name = "mxs-adc-audio", + }, + .probe = mxs_codec_audio_probe, + .remove = __devexit_p(mxs_codec_audio_remove), +}; + +static int __init mxs_codec_init(void) +{ + return platform_driver_register(&mxs_codec_audio_driver); +} + +static void __exit mxs_codec_exit(void) +{ + return platform_driver_unregister(&mxs_codec_audio_driver); +} + +module_init(mxs_codec_init); +module_exit(mxs_codec_exit); + +MODULE_DESCRIPTION("MXS ADC/DAC codec"); +MODULE_AUTHOR("Vladislav Buzov"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/mxs-adc-codec.h b/sound/soc/codecs/mxs-adc-codec.h new file mode 100644 index 000000000000..129c1c7bdf66 --- /dev/null +++ b/sound/soc/codecs/mxs-adc-codec.h @@ -0,0 +1,87 @@ +/* + * ALSA codec for Freescale MXS ADC/DAC Audio + * + * Author: Vladislav Buzov + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MXS_ADC_CODEC_H +#define __MXS_ADC_CODEC_H + +#define DAC_CTRL_L 0 +#define DAC_CTRL_H 1 +#define DAC_STAT_L 2 +#define DAC_STAT_H 3 +#define DAC_SRR_L 4 +#define DAC_VOLUME_L 6 +#define DAC_VOLUME_H 7 +#define DAC_DEBUG_L 8 +#define DAC_DEBUG_H 9 +#define DAC_HPVOL_L 10 +#define DAC_HPVOL_H 11 +#define DAC_PWRDN_L 12 +#define DAC_PWRDN_H 13 +#define DAC_REFCTRL_L 14 +#define DAC_REFCTRL_H 15 +#define DAC_ANACTRL_L 16 +#define DAC_ANACTRL_H 17 +#define DAC_TEST_L 18 +#define DAC_TEST_H 19 +#define DAC_BISTCTRL_L 20 +#define DAC_BISTCTRL_H 21 +#define DAC_BISTSTAT0_L 22 +#define DAC_BISTSTAT0_H 23 +#define DAC_BISTSTAT1_L 24 +#define DAC_BISTSTAT1_H 25 +#define DAC_ANACLKCTRL_L 26 +#define DAC_ANACLKCTRL_H 27 +#define DAC_DATA_L 28 +#define DAC_DATA_H 29 +#define DAC_SPEAKERCTRL_L 30 +#define DAC_SPEAKERCTRL_H 31 +#define DAC_VERSION_L 32 +#define DAC_VERSION_H 33 +#define ADC_CTRL_L 34 +#define ADC_CTRL_H 35 +#define ADC_STAT_L 36 +#define ADC_STAT_H 37 +#define ADC_SRR_L 38 +#define ADC_SRR_H 39 +#define ADC_VOLUME_L 40 +#define ADC_VOLUME_H 41 +#define ADC_DEBUG_L 42 +#define ADC_DEBUG_H 43 +#define ADC_ADCVOL_L 44 +#define ADC_ADCVOL_H 45 +#define ADC_MICLINE_L 46 +#define ADC_MICLINE_H 47 +#define ADC_ANACLKCTRL_L 48 +#define ADC_ANACLKCTRL_H 49 +#define ADC_DATA_L 50 +#define ADC_DATA_H 51 + +#define ADC_REGNUM 52 + +#define DAC_VOLUME_MIN 0x37 +#define DAC_VOLUME_MAX 0xFE +#define ADC_VOLUME_MIN 0x37 +#define ADC_VOLUME_MAX 0xFE +#define HP_VOLUME_MAX 0x0 +#define HP_VOLUME_MIN 0x7F +#define LO_VOLUME_MAX 0x0 +#define LO_VOLUME_MIN 0x1F + +extern struct snd_soc_dai mxs_codec_dai; +extern struct snd_soc_codec_device soc_codec_dev_mxs; + +#endif /* __MXS_ADC_CODEC_H */ diff --git a/sound/soc/codecs/mxs_spdif.c b/sound/soc/codecs/mxs_spdif.c new file mode 100644 index 000000000000..cdd8c343da71 --- /dev/null +++ b/sound/soc/codecs/mxs_spdif.c @@ -0,0 +1,447 @@ +/* + * ALSA SoC MXS SPDIF codec driver + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. + * + * Based on stmp3xxx_spdif.h by: + * Vladimir Barinov + * + * Copyright 2008 SigmaTel, Inc + * Copyright 2008 Embedded Alley Solutions, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxs_spdif.h" + +#define REGS_SPDIF_BASE IO_ADDRESS(SPDIF_PHYS_ADDR) + +#define BF(value, field) (((value) << BP_##field) & BM_##field) + +struct mxs_codec_priv { + struct clk *clk; + struct snd_soc_codec codec; +}; + +/* + * ALSA API + */ +static void __iomem *spdif_regmap[] = { + REGS_SPDIF_BASE + HW_SPDIF_CTRL, + REGS_SPDIF_BASE + HW_SPDIF_STAT, + REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL, + REGS_SPDIF_BASE + HW_SPDIF_SRR, + REGS_SPDIF_BASE + HW_SPDIF_DEBUG, + REGS_SPDIF_BASE + HW_SPDIF_DATA, + REGS_SPDIF_BASE + HW_SPDIF_VERSION, +}; + +/* + * ALSA core supports only 16 bit registers. It means we have to simulate it + * by virtually splitting a 32bit SPDIF registers into two halves + * high (bits 31:16) and low (bits 15:0). The routins abow detects which part + * of 32bit register is accessed. + */ +static int mxs_codec_write(struct snd_soc_codec *codec, + unsigned int reg, unsigned int value) +{ + unsigned int reg_val; + unsigned int mask = 0xffff; + + if (reg >= SPDIF_REGNUM) + return -EIO; + + if (reg & 0x1) { + mask <<= 16; + value <<= 16; + } + + reg_val = __raw_readl(spdif_regmap[reg >> 1]); + reg_val = (reg_val & ~mask) | value; + __raw_writel(reg_val, spdif_regmap[reg >> 1]); + + return 0; +} + +static unsigned int mxs_codec_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + unsigned int reg_val; + + if (reg >= SPDIF_REGNUM) + return -1; + + reg_val = __raw_readl(spdif_regmap[reg >> 1]); + if (reg & 1) + reg_val >>= 16; + + return reg_val & 0xffff; +} + +/* Codec controls */ +static const struct snd_kcontrol_new mxs_snd_controls[] = { + SOC_SINGLE("PRO", SPDIF_FRAMECTRL_L, 0, 0x1, 0), + SOC_SINGLE("AUDIO", SPDIF_FRAMECTRL_L, 1, 0x1, 0), + SOC_SINGLE("COPY", SPDIF_FRAMECTRL_L, 2, 0x1, 0), + SOC_SINGLE("PRE", SPDIF_FRAMECTRL_L, 3, 0x1, 0), + SOC_SINGLE("CC", SPDIF_FRAMECTRL_L, 4, 0x7F, 0), + SOC_SINGLE("L", SPDIF_FRAMECTRL_L, 12, 0x1, 0), + SOC_SINGLE("V", SPDIF_FRAMECTRL_L, 13, 0x1, 0), + SOC_SINGLE("USER DATA", SPDIF_FRAMECTRL_L, 14, 0x1, 0), + SOC_SINGLE("AUTO MUTE", SPDIF_FRAMECTRL_H, 16, 0x1, 0), + SOC_SINGLE("V CONFIG", SPDIF_FRAMECTRL_H, 17, 0x1, 0), +}; + +struct spdif_srr { + u32 rate; + u32 basemult; + u32 rate_factor; +}; + +static struct spdif_srr srr_values[] = { + {96000, 0x2, 0x0BB80}, + {88200, 0x2, 0x0AC44}, + {64000, 0x2, 0x07D00}, + {48000, 0x1, 0x0BB80}, + {44100, 0x1, 0x0AC44}, + {32000, 0x1, 0x07D00}, +}; + +static inline int get_srr_values(int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(srr_values); i++) + if (srr_values[i].rate == rate) + return i; + + return -1; +} + +static int mxs_codec_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + int i; + u32 srr_value = 0; + u32 basemult; + + i = get_srr_values(params_rate(params)); + if (i < 0) + printk(KERN_WARNING "%s doesn't support rate %d\n", + codec->name, params_rate(params)); + else { + basemult = srr_values[i].basemult; + + srr_value = BF(basemult, SPDIF_SRR_BASEMULT) | + BF(srr_values[i].rate_factor, SPDIF_SRR_RATE); + + if (playback) + __raw_writel(srr_value, REGS_SPDIF_BASE + HW_SPDIF_SRR); + } + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + if (playback) + __raw_writel(BM_SPDIF_CTRL_WORD_LENGTH, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S32_LE: + if (playback) + __raw_writel(BM_SPDIF_CTRL_WORD_LENGTH, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + break; + default: + printk(KERN_WARNING "%s doesn't support format %d\n", + codec->name, params_format(params)); + } + + return 0; +} + +static void mxs_codec_spdif_enable(struct mxs_codec_priv *mxs_spdif) +{ + /* Move SPDIF codec out of reset */ + __raw_writel(BM_SPDIF_CTRL_SFTRST, REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + + /* Ungate SPDIF clocks */ + __raw_writel(BM_SPDIF_CTRL_CLKGATE, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + + /* 16 bit word length */ + __raw_writel(BM_SPDIF_CTRL_WORD_LENGTH, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET); +} + +static void mxs_codec_spdif_disable(struct mxs_codec_priv *mxs_spdif) +{ + /* Gate SPDIF clocks */ + __raw_writel(BM_SPDIF_CTRL_CLKGATE, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET); +} + +static void mxs_codec_init(struct snd_soc_codec *codec) +{ + struct mxs_codec_priv *mxs_spdif = codec->drvdata; + + /* Soft reset SPDIF block */ + __raw_writel(BM_SPDIF_CTRL_SFTRST, REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET); + + while (!(__raw_readl(REGS_SPDIF_BASE + HW_SPDIF_CTRL) + & BM_SPDIF_CTRL_CLKGATE)) + ; + + mxs_codec_spdif_enable(mxs_spdif); + + snd_soc_add_controls(codec, mxs_snd_controls, + ARRAY_SIZE(mxs_snd_controls)); +} + +static void mxs_codec_exit(struct snd_soc_codec *codec) +{ + struct mxs_codec_priv *mxs_spdif = codec->drvdata; + + mxs_codec_spdif_disable(mxs_spdif); +} + +struct snd_soc_dai_ops mxs_spdif_codec_dai_ops = { + .hw_params = mxs_codec_hw_params, +}; + +struct snd_soc_dai mxs_spdif_codec_dai = { + .name = "mxs spdif", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = MXS_SPDIF_RATES, + .formats = MXS_SPDIF_FORMATS, + }, + .ops = &mxs_spdif_codec_dai_ops, +}; +EXPORT_SYMBOL_GPL(mxs_spdif_codec_dai); + +static struct snd_soc_codec *mxs_spdif_codec; + +static int mxs_codec_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec; + int ret = 0; + + socdev->card->codec = mxs_spdif_codec; + codec = mxs_spdif_codec; + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(codec->dev, "failed to create pcms\n"); + return ret; + } + + mxs_codec_init(codec); + + return 0; +} + +static int mxs_codec_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + mxs_codec_exit(codec); + + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + + return 0; +} + +#ifdef CONFIG_PM +static int mxs_codec_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + struct mxs_codec_priv *mxs_spdif; + int ret = -EINVAL; + + if (codec == NULL) + goto out; + + mxs_spdif = codec->drvdata; + + mxs_codec_spdif_disable(mxs_spdif); + clk_disable(mxs_spdif->clk); + ret = 0; + +out: + return ret; +} + +static int mxs_codec_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + struct mxs_codec_priv *mxs_spdif; + int ret = -EINVAL; + + if (codec == NULL) + goto out; + + mxs_spdif = codec->drvdata; + clk_enable(mxs_spdif->clk); + + /* Soft reset SPDIF block */ + __raw_writel(BM_SPDIF_CTRL_SFTRST, REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET); + while (!(__raw_readl(REGS_SPDIF_BASE + HW_SPDIF_CTRL) + & BM_SPDIF_CTRL_CLKGATE)) + ; + + mxs_codec_spdif_enable(mxs_spdif); + + ret = 0; + +out: + return ret; +} +#else +#define mxs_codec_suspend NULL +#define mxs_codec_resume NULL +#endif /* CONFIG_PM */ + +struct snd_soc_codec_device soc_spdif_codec_dev_mxs = { + .probe = mxs_codec_probe, + .remove = mxs_codec_remove, + .suspend = mxs_codec_suspend, + .resume = mxs_codec_resume, +}; +EXPORT_SYMBOL_GPL(soc_spdif_codec_dev_mxs); + +static int __init mxs_spdif_probe(struct platform_device *pdev) +{ + struct snd_soc_codec *codec; + struct mxs_codec_priv *mxs_spdif; + int ret = 0; + + dev_info(&pdev->dev, "MXS SPDIF Audio Transmitter\n"); + + mxs_spdif = kzalloc(sizeof(struct mxs_codec_priv), GFP_KERNEL); + if (mxs_spdif == NULL) + return -ENOMEM; + + codec = &mxs_spdif->codec; + codec->name = "mxs spdif"; + codec->owner = THIS_MODULE; + codec->drvdata = mxs_spdif; + codec->read = mxs_codec_read; + codec->write = mxs_codec_write; + codec->dai = &mxs_spdif_codec_dai; + codec->num_dai = 1; + + platform_set_drvdata(pdev, mxs_spdif); + mxs_spdif_codec = codec; + + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + /* Turn on audio clock */ + mxs_spdif->clk = clk_get(&pdev->dev, "spdif"); + if (IS_ERR(mxs_spdif->clk)) { + ret = PTR_ERR(mxs_spdif->clk); + dev_err(&pdev->dev, "Clocks initialization failed\n"); + goto clk_err; + } + clk_enable(mxs_spdif->clk); + + ret = snd_soc_register_codec(codec); + if (ret) { + dev_err(&pdev->dev, "failed to register card\n"); + goto card_err; + } + + ret = snd_soc_register_dai(&mxs_spdif_codec_dai); + if (ret) { + dev_err(&pdev->dev, "failed to register card\n"); + goto dai_err; + } + + return 0; + +dai_err: + snd_soc_unregister_codec(codec); +card_err: + clk_disable(mxs_spdif->clk); + clk_put(mxs_spdif->clk); +clk_err: + kfree(mxs_spdif); + return ret; +} + +static int __devexit mxs_spdif_remove(struct platform_device *pdev) +{ + struct mxs_codec_priv *mxs_spdif = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = &mxs_spdif->codec; + + snd_soc_unregister_codec(codec); + + clk_disable(mxs_spdif->clk); + clk_put(mxs_spdif->clk); + + kfree(mxs_spdif); + + return 0; +} + +struct platform_driver mxs_spdif_driver = { + .driver = { + .name = "mxs-spdif", + }, + .probe = mxs_spdif_probe, + .remove = __devexit_p(mxs_spdif_remove), +}; + +static int __init mxs_spdif_init(void) +{ + return platform_driver_register(&mxs_spdif_driver); +} + +static void __exit mxs_spdif_exit(void) +{ + return platform_driver_unregister(&mxs_spdif_driver); +} + +module_init(mxs_spdif_init); +module_exit(mxs_spdif_exit); + +MODULE_DESCRIPTION("MXS SPDIF transmitter"); +MODULE_AUTHOR("Vladimir Barinov"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/mxs_spdif.h b/sound/soc/codecs/mxs_spdif.h new file mode 100644 index 000000000000..6bce044d683e --- /dev/null +++ b/sound/soc/codecs/mxs_spdif.h @@ -0,0 +1,172 @@ +/* + * ALSA SoC MXS SPDIF codec driver + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. + * + * Based on stmp3xxx_spdif.h by: + * Vladimir Barinov + * + * Copyright 2008 SigmaTel, Inc + * Copyright 2008 Embedded Alley Solutions, Inc + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef __MXS_SPDIF_CODEC_H +#define __MXS_SPDIF_CODEC_H + +#define SPDIF_CTRL_L 0 +#define SPDIF_CTRL_H 1 +#define SPDIF_STAT_L 2 +#define SPDIF_STAT_H 3 +#define SPDIF_FRAMECTRL_L 4 +#define SPDIF_FRAMECTRL_H 5 +#define SPDIF_SRR_L 6 +#define SPDIF_SRR_H 7 +#define SPDIF_DEBUG_L 8 +#define SPDIF_DEBUG_H 9 +#define SPDIF_DATA_L 10 +#define SPDIF_DATA_H 11 +#define SPDIF_VERSION_L 12 +#define SPDIF_VERSION_H 13 + +#define SPDIF_REGNUM 14 + +#define HW_SPDIF_CTRL (0x00000000) +#define HW_SPDIF_CTRL_SET (0x00000004) +#define HW_SPDIF_CTRL_CLR (0x00000008) +#define HW_SPDIF_CTRL_TOG (0x0000000c) + +#define BM_SPDIF_CTRL_SFTRST 0x80000000 +#define BM_SPDIF_CTRL_CLKGATE 0x40000000 +#define BP_SPDIF_CTRL_RSRVD1 21 +#define BM_SPDIF_CTRL_RSRVD1 0x3FE00000 +#define BF_SPDIF_CTRL_RSRVD1(v) \ + (((v) << 21) & BM_SPDIF_CTRL_RSRVD1) +#define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 +#define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_SPDIF_CTRL_DMAWAIT_COUNT) +#define BP_SPDIF_CTRL_RSRVD0 6 +#define BM_SPDIF_CTRL_RSRVD0 0x0000FFC0 +#define BF_SPDIF_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_SPDIF_CTRL_RSRVD0) +#define BM_SPDIF_CTRL_WAIT_END_XFER 0x00000020 +#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 +#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_SPDIF_CTRL_RUN 0x00000001 + +#define HW_SPDIF_STAT (0x00000010) +#define HW_SPDIF_STAT_SET (0x00000014) +#define HW_SPDIF_STAT_CLR (0x00000018) +#define HW_SPDIF_STAT_TOG (0x0000001c) + +#define BM_SPDIF_STAT_PRESENT 0x80000000 +#define BP_SPDIF_STAT_RSRVD1 1 +#define BM_SPDIF_STAT_RSRVD1 0x7FFFFFFE +#define BF_SPDIF_STAT_RSRVD1(v) \ + (((v) << 1) & BM_SPDIF_STAT_RSRVD1) +#define BM_SPDIF_STAT_END_XFER 0x00000001 + +#define HW_SPDIF_FRAMECTRL (0x00000020) +#define HW_SPDIF_FRAMECTRL_SET (0x00000024) +#define HW_SPDIF_FRAMECTRL_CLR (0x00000028) +#define HW_SPDIF_FRAMECTRL_TOG (0x0000002c) + +#define BP_SPDIF_FRAMECTRL_RSRVD2 18 +#define BM_SPDIF_FRAMECTRL_RSRVD2 0xFFFC0000 +#define BF_SPDIF_FRAMECTRL_RSRVD2(v) \ + (((v) << 18) & BM_SPDIF_FRAMECTRL_RSRVD2) +#define BM_SPDIF_FRAMECTRL_V_CONFIG 0x00020000 +#define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x00010000 +#define BM_SPDIF_FRAMECTRL_RSRVD1 0x00008000 +#define BM_SPDIF_FRAMECTRL_USER_DATA 0x00004000 +#define BM_SPDIF_FRAMECTRL_V 0x00002000 +#define BM_SPDIF_FRAMECTRL_L 0x00001000 +#define BM_SPDIF_FRAMECTRL_RSRVD0 0x00000800 +#define BP_SPDIF_FRAMECTRL_CC 4 +#define BM_SPDIF_FRAMECTRL_CC 0x000007F0 +#define BF_SPDIF_FRAMECTRL_CC(v) \ + (((v) << 4) & BM_SPDIF_FRAMECTRL_CC) +#define BM_SPDIF_FRAMECTRL_PRE 0x00000008 +#define BM_SPDIF_FRAMECTRL_COPY 0x00000004 +#define BM_SPDIF_FRAMECTRL_AUDIO 0x00000002 +#define BM_SPDIF_FRAMECTRL_PRO 0x00000001 + +#define HW_SPDIF_SRR (0x00000030) +#define HW_SPDIF_SRR_SET (0x00000034) +#define HW_SPDIF_SRR_CLR (0x00000038) +#define HW_SPDIF_SRR_TOG (0x0000003c) + +#define BM_SPDIF_SRR_RSRVD1 0x80000000 +#define BP_SPDIF_SRR_BASEMULT 28 +#define BM_SPDIF_SRR_BASEMULT 0x70000000 +#define BF_SPDIF_SRR_BASEMULT(v) \ + (((v) << 28) & BM_SPDIF_SRR_BASEMULT) +#define BP_SPDIF_SRR_RSRVD0 20 +#define BM_SPDIF_SRR_RSRVD0 0x0FF00000 +#define BF_SPDIF_SRR_RSRVD0(v) \ + (((v) << 20) & BM_SPDIF_SRR_RSRVD0) +#define BP_SPDIF_SRR_RATE 0 +#define BM_SPDIF_SRR_RATE 0x000FFFFF +#define BF_SPDIF_SRR_RATE(v) \ + (((v) << 0) & BM_SPDIF_SRR_RATE) + +#define HW_SPDIF_DEBUG (0x00000040) +#define HW_SPDIF_DEBUG_SET (0x00000044) +#define HW_SPDIF_DEBUG_CLR (0x00000048) +#define HW_SPDIF_DEBUG_TOG (0x0000004c) + +#define BP_SPDIF_DEBUG_RSRVD1 2 +#define BM_SPDIF_DEBUG_RSRVD1 0xFFFFFFFC +#define BF_SPDIF_DEBUG_RSRVD1(v) \ + (((v) << 2) & BM_SPDIF_DEBUG_RSRVD1) +#define BM_SPDIF_DEBUG_DMA_PREQ 0x00000002 +#define BM_SPDIF_DEBUG_FIFO_STATUS 0x00000001 + +#define HW_SPDIF_DATA (0x00000050) +#define HW_SPDIF_DATA_SET (0x00000054) +#define HW_SPDIF_DATA_CLR (0x00000058) +#define HW_SPDIF_DATA_TOG (0x0000005c) + +#define BP_SPDIF_DATA_HIGH 16 +#define BM_SPDIF_DATA_HIGH 0xFFFF0000 +#define BF_SPDIF_DATA_HIGH(v) \ + (((v) << 16) & BM_SPDIF_DATA_HIGH) +#define BP_SPDIF_DATA_LOW 0 +#define BM_SPDIF_DATA_LOW 0x0000FFFF +#define BF_SPDIF_DATA_LOW(v) \ + (((v) << 0) & BM_SPDIF_DATA_LOW) + +#define HW_SPDIF_VERSION (0x00000060) + +#define BP_SPDIF_VERSION_MAJOR 24 +#define BM_SPDIF_VERSION_MAJOR 0xFF000000 +#define BF_SPDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SPDIF_VERSION_MAJOR) +#define BP_SPDIF_VERSION_MINOR 16 +#define BM_SPDIF_VERSION_MINOR 0x00FF0000 +#define BF_SPDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_SPDIF_VERSION_MINOR) +#define BP_SPDIF_VERSION_STEP 0 +#define BM_SPDIF_VERSION_STEP 0x0000FFFF +#define BF_SPDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_SPDIF_VERSION_STEP) + +#define MXS_SPDIF_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) + +#define MXS_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +extern struct snd_soc_dai mxs_spdif_codec_dai; +extern struct snd_soc_codec_device soc_spdif_codec_dev_mxs; + +#endif /* __MXS_SPDIF_CODEC_H */ diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c new file mode 100644 index 000000000000..bb94c65244f1 --- /dev/null +++ b/sound/soc/codecs/sgtl5000.c @@ -0,0 +1,1394 @@ +/* + * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sgtl5000.h" + +struct sgtl5000_priv { + int sysclk; + int master; + int fmt; + int rev; + int lrclk; + int capture_channels; + int playback_active; + int capture_active; + int clock_on; /* clock enable status */ + int need_clk_for_access; /* need clock on because doing access */ + int need_clk_for_bias; /* need clock on due to bias level */ + int (*clock_enable) (int enable); + struct regulator *reg_vddio; + struct regulator *reg_vdda; + struct regulator *reg_vddd; + int vddio; /* voltage of VDDIO (mv) */ + int vdda; /* voltage of vdda (mv) */ + int vddd; /* voltage of vddd (mv), 0 if not connected */ + struct snd_pcm_substream *master_substream; + struct snd_pcm_substream *slave_substream; +}; + +static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level); + +#define SGTL5000_MAX_CACHED_REG SGTL5000_CHIP_SHORT_CTRL +static u16 sgtl5000_regs[(SGTL5000_MAX_CACHED_REG >> 1) + 1]; + +/* + * Schedule clock to be turned off or turn clock on. + */ +static void sgtl5000_clock_gating(struct snd_soc_codec *codec, int enable) +{ + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + + if (sgtl5000->clock_enable == NULL) + return; + + if (enable == 0) { + if (!sgtl5000->need_clk_for_access && + !sgtl5000->need_clk_for_bias) + schedule_delayed_work(&codec->delayed_work, + msecs_to_jiffies(300)); + } else { + if (!sgtl5000->clock_on) { + sgtl5000->clock_enable(1); + sgtl5000->clock_on = 1; + } + } +} + +static unsigned int sgtl5000_read_reg_cache(struct snd_soc_codec *codec, + unsigned int reg) +{ + u16 *cache = codec->reg_cache; + unsigned int offset = reg >> 1; + if (offset >= ARRAY_SIZE(sgtl5000_regs)) + return -EINVAL; + pr_debug("r r:%02x,v:%04x\n", reg, cache[offset]); + return cache[offset]; +} + +static unsigned int sgtl5000_hw_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + struct i2c_client *client = codec->control_data; + int i2c_ret; + u16 value; + u8 buf0[2], buf1[2]; + u16 addr = client->addr; + u16 flags = client->flags; + struct i2c_msg msg[2] = { + {addr, flags, 2, buf0}, + {addr, flags | I2C_M_RD, 2, buf1}, + }; + + sgtl5000->need_clk_for_access = 1; + sgtl5000_clock_gating(codec, 1); + buf0[0] = (reg & 0xff00) >> 8; + buf0[1] = reg & 0xff; + i2c_ret = i2c_transfer(client->adapter, msg, 2); + sgtl5000->need_clk_for_access = 0; + sgtl5000_clock_gating(codec, 0); + if (i2c_ret < 0) { + pr_err("%s: read reg error : Reg 0x%02x\n", __func__, reg); + return 0; + } + + value = buf1[0] << 8 | buf1[1]; + + pr_debug("r r:%02x,v:%04x\n", reg, value); + return value; +} + +static unsigned int sgtl5000_read(struct snd_soc_codec *codec, unsigned int reg) +{ + if ((reg == SGTL5000_CHIP_ID) || + (reg == SGTL5000_CHIP_ADCDAC_CTRL) || + (reg == SGTL5000_CHIP_ANA_STATUS) || + (reg > SGTL5000_MAX_CACHED_REG)) + return sgtl5000_hw_read(codec, reg); + else + return sgtl5000_read_reg_cache(codec, reg); +} + +static inline void sgtl5000_write_reg_cache(struct snd_soc_codec *codec, + u16 reg, unsigned int value) +{ + u16 *cache = codec->reg_cache; + unsigned int offset = reg >> 1; + if (offset < ARRAY_SIZE(sgtl5000_regs)) + cache[offset] = value; +} + +static int sgtl5000_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + struct i2c_client *client = codec->control_data; + u16 addr = client->addr; + u16 flags = client->flags; + u8 buf[4]; + int i2c_ret; + struct i2c_msg msg = { addr, flags, 4, buf }; + + sgtl5000->need_clk_for_access = 1; + sgtl5000_clock_gating(codec, 1); + sgtl5000_write_reg_cache(codec, reg, value); + pr_debug("w r:%02x,v:%04x\n", reg, value); + buf[0] = (reg & 0xff00) >> 8; + buf[1] = reg & 0xff; + buf[2] = (value & 0xff00) >> 8; + buf[3] = value & 0xff; + + i2c_ret = i2c_transfer(client->adapter, &msg, 1); + sgtl5000->need_clk_for_access = 0; + sgtl5000_clock_gating(codec, 0); + if (i2c_ret < 0) { + pr_err("%s: write reg error : Reg 0x%02x = 0x%04x\n", + __func__, reg, value); + return -EIO; + } + + return i2c_ret; +} + +static void sgtl5000_sync_reg_cache(struct snd_soc_codec *codec) +{ + int reg; + for (reg = 0; reg <= SGTL5000_MAX_CACHED_REG; reg += 2) + sgtl5000_write_reg_cache(codec, reg, + sgtl5000_hw_read(codec, reg)); +} + +static int sgtl5000_restore_reg(struct snd_soc_codec *codec, unsigned int reg) +{ + unsigned int cached_val, hw_val; + + cached_val = sgtl5000_read_reg_cache(codec, reg); + hw_val = sgtl5000_hw_read(codec, reg); + + if (hw_val != cached_val) + return sgtl5000_write(codec, reg, cached_val); + + return 0; +} + +static int all_reg[] = { + SGTL5000_CHIP_ID, + SGTL5000_CHIP_DIG_POWER, + SGTL5000_CHIP_CLK_CTRL, + SGTL5000_CHIP_I2S_CTRL, + SGTL5000_CHIP_SSS_CTRL, + SGTL5000_CHIP_ADCDAC_CTRL, + SGTL5000_CHIP_DAC_VOL, + SGTL5000_CHIP_PAD_STRENGTH, + SGTL5000_CHIP_ANA_ADC_CTRL, + SGTL5000_CHIP_ANA_HP_CTRL, + SGTL5000_CHIP_ANA_CTRL, + SGTL5000_CHIP_LINREG_CTRL, + SGTL5000_CHIP_REF_CTRL, + SGTL5000_CHIP_MIC_CTRL, + SGTL5000_CHIP_LINE_OUT_CTRL, + SGTL5000_CHIP_LINE_OUT_VOL, + SGTL5000_CHIP_ANA_POWER, + SGTL5000_CHIP_PLL_CTRL, + SGTL5000_CHIP_CLK_TOP_CTRL, + SGTL5000_CHIP_ANA_STATUS, + SGTL5000_CHIP_SHORT_CTRL, +}; + +#ifdef DEBUG +static void dump_reg(struct snd_soc_codec *codec) +{ + int i, reg; + printk(KERN_DEBUG "dump begin\n"); + for (i = 0; i < 21; i++) { + reg = sgtl5000_read(codec, all_reg[i]); + printk(KERN_DEBUG "d r %04x, v %04x\n", all_reg[i], reg); + } + printk(KERN_DEBUG "dump end\n"); +} +#else +static void dump_reg(struct snd_soc_codec *codec) +{ +} +#endif + +static const char *adc_mux_text[] = { + "MIC_IN", "LINE_IN" +}; + +static const char *dac_mux_text[] = { + "DAC", "LINE_IN" +}; + +static const struct soc_enum adc_enum = +SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text); + +static const struct soc_enum dac_enum = +SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text); + +static const struct snd_kcontrol_new adc_mux = +SOC_DAPM_ENUM("ADC Mux", adc_enum); + +static const struct snd_kcontrol_new dac_mux = +SOC_DAPM_ENUM("DAC Mux", dac_enum); + +static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("LINE_IN"), + SND_SOC_DAPM_INPUT("MIC_IN"), + + SND_SOC_DAPM_OUTPUT("HP_OUT"), + SND_SOC_DAPM_OUTPUT("LINE_OUT"), + + SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_CTRL, 4, 1, NULL, 0), + SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_CTRL, 8, 1, NULL, 0), + + SND_SOC_DAPM_MUX("ADC Mux", SND_SOC_NOPM, 0, 0, &adc_mux), + SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0, &dac_mux), + + SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_DIG_POWER, 6, 0), + SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + {"ADC Mux", "LINE_IN", "LINE_IN"}, + {"ADC Mux", "MIC_IN", "MIC_IN"}, + {"ADC", NULL, "ADC Mux"}, + {"DAC Mux", "DAC", "DAC"}, + {"DAC Mux", "LINE_IN", "LINE_IN"}, + {"LO", NULL, "DAC"}, + {"HP", NULL, "DAC Mux"}, + {"LINE_OUT", NULL, "LO"}, + {"HP_OUT", NULL, "HP"}, +}; + +static int sgtl5000_add_widgets(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, sgtl5000_dapm_widgets, + ARRAY_SIZE(sgtl5000_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +} + +static int dac_info_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 2; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 0xfc - 0x3c; + return 0; +} + +static int dac_get_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + int reg, l, r; + + reg = sgtl5000_read(codec, SGTL5000_CHIP_DAC_VOL); + l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; + r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; + l = l < 0x3c ? 0x3c : l; + l = l > 0xfc ? 0xfc : l; + r = r < 0x3c ? 0x3c : r; + r = r > 0xfc ? 0xfc : r; + l = 0xfc - l; + r = 0xfc - r; + + ucontrol->value.integer.value[0] = l; + ucontrol->value.integer.value[1] = r; + + return 0; +} + +static int dac_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + int reg, l, r; + + l = ucontrol->value.integer.value[0]; + r = ucontrol->value.integer.value[1]; + + l = l < 0 ? 0 : l; + l = l > 0xfc - 0x3c ? 0xfc - 0x3c : l; + r = r < 0 ? 0 : r; + r = r > 0xfc - 0x3c ? 0xfc - 0x3c : r; + l = 0xfc - l; + r = 0xfc - r; + + reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | + r << SGTL5000_DAC_VOL_RIGHT_SHIFT; + + sgtl5000_write(codec, SGTL5000_CHIP_DAC_VOL, reg); + + return 0; +} + +static const char *mic_gain_text[] = { + "0dB", "20dB", "30dB", "40dB" +}; + +static const char *adc_m6db_text[] = { + "No Change", "Reduced by 6dB" +}; + +static const struct soc_enum mic_gain = +SOC_ENUM_SINGLE(SGTL5000_CHIP_MIC_CTRL, 0, 4, mic_gain_text); + +static const struct soc_enum adc_m6db = +SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_ADC_CTRL, 8, 2, adc_m6db_text); + +static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { + SOC_ENUM("MIC GAIN", mic_gain), + SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), + SOC_ENUM("Capture Vol Reduction", adc_m6db), + {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Playback Volume", + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | + SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = dac_info_volsw, + .get = dac_get_volsw, + .put = dac_put_volsw, + }, + SOC_DOUBLE("Headphone Volume", SGTL5000_CHIP_ANA_HP_CTRL, 0, 8, 0x7f, + 1), +}; + +static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute) +{ + struct snd_soc_codec *codec = codec_dai->codec; + u16 adcdac_ctrl; + + adcdac_ctrl = sgtl5000_read(codec, SGTL5000_CHIP_ADCDAC_CTRL); + + if (mute) { + adcdac_ctrl |= SGTL5000_DAC_MUTE_LEFT; + adcdac_ctrl |= SGTL5000_DAC_MUTE_RIGHT; + } else { + adcdac_ctrl &= ~SGTL5000_DAC_MUTE_LEFT; + adcdac_ctrl &= ~SGTL5000_DAC_MUTE_RIGHT; + } + + sgtl5000_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, adcdac_ctrl); + if (!mute) + dump_reg(codec); + return 0; +} + +static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + u16 i2sctl = 0; + pr_debug("%s:fmt=%08x\n", __func__, fmt); + sgtl5000->master = 0; + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + break; + case SND_SOC_DAIFMT_CBM_CFM: + i2sctl |= SGTL5000_I2S_MASTER; + sgtl5000->master = 1; + break; + case SND_SOC_DAIFMT_CBM_CFS: + case SND_SOC_DAIFMT_CBS_CFM: + return -EINVAL; + break; + default: + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + i2sctl |= SGTL5000_I2S_MODE_PCM; + break; + case SND_SOC_DAIFMT_DSP_B: + i2sctl |= SGTL5000_I2S_MODE_PCM; + i2sctl |= SGTL5000_I2S_LRALIGN; + break; + case SND_SOC_DAIFMT_I2S: + i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; + break; + case SND_SOC_DAIFMT_RIGHT_J: + i2sctl |= SGTL5000_I2S_MODE_RJ; + i2sctl |= SGTL5000_I2S_LRPOL; + break; + case SND_SOC_DAIFMT_LEFT_J: + i2sctl |= SGTL5000_I2S_MODE_I2S_LJ; + i2sctl |= SGTL5000_I2S_LRALIGN; + break; + default: + return -EINVAL; + } + sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; + + /* Clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + case SND_SOC_DAIFMT_NB_IF: + break; + case SND_SOC_DAIFMT_IB_IF: + case SND_SOC_DAIFMT_IB_NF: + i2sctl |= SGTL5000_I2S_SCLK_INV; + break; + default: + return -EINVAL; + } + sgtl5000_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl); + + return 0; +} + +static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + + switch (clk_id) { + case SGTL5000_SYSCLK: + sgtl5000->sysclk = freq; + break; + case SGTL5000_LRCLK: + sgtl5000->lrclk = freq; + break; + default: + return -EINVAL; + } + return 0; +} + +static int sgtl5000_pcm_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + int reg; + + reg = sgtl5000_read(codec, SGTL5000_CHIP_DIG_POWER); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + reg |= SGTL5000_I2S_IN_POWERUP; + else + reg |= SGTL5000_I2S_OUT_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_DIG_POWER, reg); + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + reg = sgtl5000_read(codec, SGTL5000_CHIP_ANA_POWER); + reg |= SGTL5000_ADC_POWERUP; + if (sgtl5000->capture_channels == 1) + reg &= ~SGTL5000_ADC_STEREO; + else + reg |= SGTL5000_ADC_STEREO; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, reg); + } + + return 0; +} + +static int sgtl5000_pcm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + struct snd_pcm_runtime *master_runtime; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + sgtl5000->playback_active++; + else + sgtl5000->capture_active++; + + /* The DAI has shared clocks so if we already have a playback or + * capture going then constrain this substream to match it. + */ + if (sgtl5000->master_substream) { + master_runtime = sgtl5000->master_substream->runtime; + + if (master_runtime->rate != 0) { + pr_debug("Constraining to %dHz\n", + master_runtime->rate); + snd_pcm_hw_constraint_minmax(substream->runtime, + SNDRV_PCM_HW_PARAM_RATE, + master_runtime->rate, + master_runtime->rate); + } + + if (master_runtime->sample_bits != 0) { + pr_debug("Constraining to %d bits\n", + master_runtime->sample_bits); + snd_pcm_hw_constraint_minmax(substream->runtime, + SNDRV_PCM_HW_PARAM_SAMPLE_BITS, + master_runtime->sample_bits, + master_runtime->sample_bits); + } + + sgtl5000->slave_substream = substream; + } else + sgtl5000->master_substream = substream; + + return 0; +} + +static void sgtl5000_pcm_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + int reg, dig_pwr, ana_pwr; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + sgtl5000->playback_active--; + else + sgtl5000->capture_active--; + + if (sgtl5000->master_substream == substream) + sgtl5000->master_substream = sgtl5000->slave_substream; + + sgtl5000->slave_substream = NULL; + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + ana_pwr = sgtl5000_read(codec, SGTL5000_CHIP_ANA_POWER); + ana_pwr &= ~(SGTL5000_ADC_POWERUP | SGTL5000_ADC_STEREO); + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); + } + + dig_pwr = sgtl5000_read(codec, SGTL5000_CHIP_DIG_POWER); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + dig_pwr &= ~SGTL5000_I2S_IN_POWERUP; + else + dig_pwr &= ~SGTL5000_I2S_OUT_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_DIG_POWER, dig_pwr); + + if (!sgtl5000->playback_active && !sgtl5000->capture_active) { + reg = sgtl5000_read(codec, SGTL5000_CHIP_I2S_CTRL); + reg &= ~SGTL5000_I2S_MASTER; + sgtl5000_write(codec, SGTL5000_CHIP_I2S_CTRL, reg); + } +} + +/* + * Set PCM DAI bit size and sample rate. + * input: params_rate, params_fmt + */ +static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->card->codec; + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + int channels = params_channels(params); + int clk_ctl = 0; + int pll_ctl = 0; + int i2s_ctl; + int div2 = 0; + int reg; + int sys_fs; + + pr_debug("%s channels=%d\n", __func__, channels); + + if (!sgtl5000->sysclk) { + pr_err("%s: set sysclk first!\n", __func__); + return -EFAULT; + } + + if (substream == sgtl5000->slave_substream) { + pr_debug("Ignoring hw_params for slave substream\n"); + return 0; + } + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + sgtl5000->capture_channels = channels; + + switch (sgtl5000->lrclk) { + case 8000: + case 16000: + sys_fs = 32000; + break; + case 11025: + case 22050: + sys_fs = 44100; + break; + default: + sys_fs = sgtl5000->lrclk; + break; + } + + switch (sys_fs / sgtl5000->lrclk) { + case 4: + clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; + break; + case 2: + clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; + break; + default: + break; + } + + switch (sys_fs) { + case 32000: + clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; + break; + case 44100: + clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; + break; + case 48000: + clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; + break; + case 96000: + clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; + break; + default: + pr_err("%s: sample rate %d not supported\n", __func__, + sgtl5000->lrclk); + return -EFAULT; + } + /* SGTL5000 rev1 has a IC bug to prevent switching to MCLK from PLL. */ + if (!sgtl5000->master) { + sys_fs = sgtl5000->lrclk; + clk_ctl = SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; + if (sys_fs * 256 == sgtl5000->sysclk) + clk_ctl |= SGTL5000_MCLK_FREQ_256FS << \ + SGTL5000_MCLK_FREQ_SHIFT; + else if (sys_fs * 384 == sgtl5000->sysclk && sys_fs != 96000) + clk_ctl |= SGTL5000_MCLK_FREQ_384FS << \ + SGTL5000_MCLK_FREQ_SHIFT; + else if (sys_fs * 512 == sgtl5000->sysclk && sys_fs != 96000) + clk_ctl |= SGTL5000_MCLK_FREQ_512FS << \ + SGTL5000_MCLK_FREQ_SHIFT; + else { + pr_err("%s: PLL not supported in slave mode\n", + __func__); + return -EINVAL; + } + } else + clk_ctl |= SGTL5000_MCLK_FREQ_PLL << SGTL5000_MCLK_FREQ_SHIFT; + + if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { + u64 out, t; + unsigned int in, int_div, frac_div; + if (sgtl5000->sysclk > 17000000) { + div2 = 1; + in = sgtl5000->sysclk / 2; + } else { + div2 = 0; + in = sgtl5000->sysclk; + } + if (sys_fs == 44100) + out = 180633600; + else + out = 196608000; + t = do_div(out, in); + int_div = out; + t *= 2048; + do_div(t, in); + frac_div = t; + pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | + frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; + } + + i2s_ctl = sgtl5000_read(codec, SGTL5000_CHIP_I2S_CTRL); + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) + return -EINVAL; + i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; + i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << + SGTL5000_I2S_SCLKFREQ_SHIFT; + break; + case SNDRV_PCM_FORMAT_S20_3LE: + i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; + i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << + SGTL5000_I2S_SCLKFREQ_SHIFT; + break; + case SNDRV_PCM_FORMAT_S24_LE: + i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; + i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << + SGTL5000_I2S_SCLKFREQ_SHIFT; + break; + case SNDRV_PCM_FORMAT_S32_LE: + if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) + return -EINVAL; + i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; + i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << + SGTL5000_I2S_SCLKFREQ_SHIFT; + break; + default: + return -EINVAL; + } + + pr_debug("\nfs=%d,clk_ctl=%04x,pll_ctl=%04x,i2s_ctl=%04x,div2=%d\n", + sgtl5000->lrclk, clk_ctl, pll_ctl, i2s_ctl, div2); + + if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { + sgtl5000_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl); + reg = sgtl5000_read(codec, SGTL5000_CHIP_CLK_TOP_CTRL); + if (div2) + reg |= SGTL5000_INPUT_FREQ_DIV2; + else + reg &= ~SGTL5000_INPUT_FREQ_DIV2; + sgtl5000_write(codec, SGTL5000_CHIP_CLK_TOP_CTRL, reg); + reg = sgtl5000_read(codec, SGTL5000_CHIP_ANA_POWER); + reg |= SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, reg); + } + sgtl5000_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl); + sgtl5000_write(codec, SGTL5000_CHIP_I2S_CTRL, i2s_ctl); + + return 0; +} + +static void sgtl5000_mic_bias(struct snd_soc_codec *codec, int enable) +{ + int reg, bias_r = 0; + if (enable) + bias_r = SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT; + reg = sgtl5000_read(codec, SGTL5000_CHIP_MIC_CTRL); + if ((reg & SGTL5000_BIAS_R_MASK) != bias_r) { + reg &= ~SGTL5000_BIAS_R_MASK; + reg |= bias_r; + sgtl5000_write(codec, SGTL5000_CHIP_MIC_CTRL, reg); + } +} + +static int sgtl5000_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + u16 reg, ana_pwr; + int delay = 0; + pr_debug("dapm level %d\n", level); + switch (level) { + case SND_SOC_BIAS_ON: /* full On */ + if (codec->bias_level == SND_SOC_BIAS_ON) + break; + + sgtl5000_mic_bias(codec, 1); + + reg = sgtl5000_read(codec, SGTL5000_CHIP_ANA_POWER); + reg |= SGTL5000_VAG_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, reg); + msleep(400); + + break; + + case SND_SOC_BIAS_PREPARE: /* partial On */ + /* Keep clock on while in PREPARE or BIAS_ON state */ + sgtl5000->need_clk_for_bias = 1; + sgtl5000_clock_gating(codec, 1); + + if (codec->bias_level == SND_SOC_BIAS_PREPARE) + break; + + sgtl5000_mic_bias(codec, 0); + + /* must power up hp/line out before vag & dac to + avoid pops. */ + reg = sgtl5000_read(codec, SGTL5000_CHIP_ANA_POWER); + if (reg & SGTL5000_VAG_POWERUP) + delay = 600; + reg &= ~SGTL5000_VAG_POWERUP; + reg |= SGTL5000_DAC_POWERUP; + reg |= SGTL5000_HP_POWERUP; + reg |= SGTL5000_LINE_OUT_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, reg); + if (delay) + msleep(delay); + + reg = sgtl5000_read(codec, SGTL5000_CHIP_DIG_POWER); + reg |= SGTL5000_DAC_EN; + sgtl5000_write(codec, SGTL5000_CHIP_DIG_POWER, reg); + + break; + + case SND_SOC_BIAS_STANDBY: /* Off, with power */ + /* soc doesn't do PREPARE state after record so make sure + that anything that needs to be turned OFF gets turned off. */ + if (codec->bias_level == SND_SOC_BIAS_STANDBY) + break; + + /* soc calls digital_mute to unmute before record but doesn't + call digital_mute to mute after record. */ + sgtl5000_digital_mute(&sgtl5000_dai, 1); + + sgtl5000_mic_bias(codec, 0); + + reg = sgtl5000_read(codec, SGTL5000_CHIP_ANA_POWER); + if (reg & SGTL5000_VAG_POWERUP) { + reg &= ~SGTL5000_VAG_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, reg); + msleep(400); + } + reg &= ~SGTL5000_DAC_POWERUP; + reg &= ~SGTL5000_HP_POWERUP; + reg &= ~SGTL5000_LINE_OUT_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, reg); + + reg = sgtl5000_read(codec, SGTL5000_CHIP_DIG_POWER); + reg &= ~SGTL5000_DAC_EN; + sgtl5000_write(codec, SGTL5000_CHIP_DIG_POWER, reg); + + sgtl5000->need_clk_for_bias = 0; + sgtl5000_clock_gating(codec, 0); + + break; + + case SND_SOC_BIAS_OFF: /* Off, without power */ + sgtl5000->need_clk_for_bias = 1; + sgtl5000_clock_gating(codec, 1); + + /* must power down hp/line out after vag & dac to + avoid pops. */ + reg = sgtl5000_read(codec, SGTL5000_CHIP_ANA_POWER); + ana_pwr = reg; + reg &= ~SGTL5000_VAG_POWERUP; + + /* Workaround for sgtl5000 rev 0x11 chip audio suspend failure + issue on mx25 */ + /* reg &= ~SGTL5000_REFTOP_POWERUP; */ + + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, reg); + msleep(600); + + reg &= ~SGTL5000_HP_POWERUP; + reg &= ~SGTL5000_LINE_OUT_POWERUP; + reg &= ~SGTL5000_DAC_POWERUP; + reg &= ~SGTL5000_ADC_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, reg); + + /* save ANA POWER register value for resume */ + sgtl5000_write_reg_cache(codec, SGTL5000_CHIP_ANA_POWER, + ana_pwr); + + sgtl5000->need_clk_for_bias = 0; + sgtl5000_clock_gating(codec, 0); + + break; + } + codec->bias_level = level; + return 0; +} + +#define SGTL5000_RATES (SNDRV_PCM_RATE_8000 |\ + SNDRV_PCM_RATE_11025 |\ + SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_22050 |\ + SNDRV_PCM_RATE_32000 |\ + SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000) + +#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE) + +struct snd_soc_dai_ops sgtl5000_ops = { + .prepare = sgtl5000_pcm_prepare, + .startup = sgtl5000_pcm_startup, + .shutdown = sgtl5000_pcm_shutdown, + .hw_params = sgtl5000_pcm_hw_params, + .digital_mute = sgtl5000_digital_mute, + .set_fmt = sgtl5000_set_dai_fmt, + .set_sysclk = sgtl5000_set_dai_sysclk +}; + +struct snd_soc_dai sgtl5000_dai = { + .name = "SGTL5000", + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SGTL5000_RATES, + .formats = SGTL5000_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 2, + .rates = SGTL5000_RATES, + .formats = SGTL5000_FORMATS, + }, + .ops = &sgtl5000_ops, +}; +EXPORT_SYMBOL_GPL(sgtl5000_dai); + +/* + * Delayed work that turns off the audio clock after a delay. + */ +static void sgtl5000_work(struct work_struct *work) +{ + struct snd_soc_codec *codec = + container_of(work, struct snd_soc_codec, delayed_work.work); + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + + if (!sgtl5000->need_clk_for_access && + !sgtl5000->need_clk_for_bias && + sgtl5000->clock_on) { + sgtl5000->clock_enable(0); + sgtl5000->clock_on = 0; + } +} + +static int sgtl5000_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); + + return 0; +} + +static int sgtl5000_resume(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + unsigned int i; + + /* Restore refs first in same order as in sgtl5000_init */ + sgtl5000_restore_reg(codec, SGTL5000_CHIP_LINREG_CTRL); + sgtl5000_restore_reg(codec, SGTL5000_CHIP_ANA_POWER); + msleep(10); + sgtl5000_restore_reg(codec, SGTL5000_CHIP_REF_CTRL); + sgtl5000_restore_reg(codec, SGTL5000_CHIP_LINE_OUT_CTRL); + + /* Restore everythine else */ + for (i = 1; i < sizeof(all_reg) / sizeof(int); i++) + sgtl5000_restore_reg(codec, all_reg[i]); + + sgtl5000_write(codec, SGTL5000_DAP_CTRL, 0); + + /* Bring the codec back up to standby first to minimise pop/clicks */ + sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + if (codec->suspend_bias_level == SND_SOC_BIAS_ON) + sgtl5000_set_bias_level(codec, SND_SOC_BIAS_PREPARE); + sgtl5000_set_bias_level(codec, codec->suspend_bias_level); + + return 0; +} + +static struct snd_soc_codec *sgtl5000_codec; + +/* + * initialise the SGTL5000 driver + * register the mixer and dsp interfaces with the kernel + */ +static int sgtl5000_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = sgtl5000_codec; + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + struct sgtl5000_setup_data *setup = socdev->codec_data; + u16 reg, ana_pwr, lreg_ctrl, ref_ctrl, lo_ctrl, short_ctrl, sss; + int vag; + int ret = 0; + + socdev->card->codec = sgtl5000_codec; + + if ((setup != NULL) && (setup->clock_enable != NULL)) { + sgtl5000->clock_enable = setup->clock_enable; + sgtl5000->need_clk_for_bias = 1; + INIT_DELAYED_WORK(&codec->delayed_work, sgtl5000_work); + } + + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { + dev_err(codec->dev, "failed to create pcms\n"); + return ret; + } + + /* reset value */ + ana_pwr = SGTL5000_DAC_STEREO | + SGTL5000_LINREG_SIMPLE_POWERUP | + SGTL5000_STARTUP_POWERUP | + SGTL5000_ADC_STEREO | SGTL5000_REFTOP_POWERUP; + lreg_ctrl = 0; + ref_ctrl = 0; + lo_ctrl = 0; + short_ctrl = 0; + sss = SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT; + + /* workaround for rev 0x11: use vddd linear regulator */ + if (!sgtl5000->vddd || (sgtl5000->rev >= 0x11)) { + /* set VDDD to 1.2v */ + lreg_ctrl |= 0x8 << SGTL5000_LINREG_VDDD_SHIFT; + /* power internal linear regulator */ + ana_pwr |= SGTL5000_LINEREG_D_POWERUP; + } else { + /* turn of startup power */ + ana_pwr &= ~SGTL5000_STARTUP_POWERUP; + ana_pwr &= ~SGTL5000_LINREG_SIMPLE_POWERUP; + } + if (sgtl5000->vddio < 3100 && sgtl5000->vdda < 3100) { + /* Enable VDDC charge pump */ + ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; + } + if (sgtl5000->vddio >= 3100 && sgtl5000->vdda >= 3100) { + /* VDDC use VDDIO rail */ + lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; + if (sgtl5000->vddio >= 3100) + lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << + SGTL5000_VDDC_MAN_ASSN_SHIFT; + } + /* If PLL is powered up (such as on power cycle) leave it on. */ + reg = sgtl5000_read(codec, SGTL5000_CHIP_ANA_POWER); + ana_pwr |= reg & (SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); + + /* set ADC/DAC ref voltage to vdda/2 */ + vag = sgtl5000->vdda / 2; + if (vag <= SGTL5000_ANA_GND_BASE) + vag = 0; + else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * + (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) + vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; + else + vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; + ref_ctrl |= vag << SGTL5000_ANA_GND_SHIFT; + + /* set line out ref voltage to vddio/2 */ + vag = sgtl5000->vddio / 2; + if (vag <= SGTL5000_LINE_OUT_GND_BASE) + vag = 0; + else if (vag >= SGTL5000_LINE_OUT_GND_BASE + SGTL5000_LINE_OUT_GND_STP * + SGTL5000_LINE_OUT_GND_MAX) + vag = SGTL5000_LINE_OUT_GND_MAX; + else + vag = (vag - SGTL5000_LINE_OUT_GND_BASE) / + SGTL5000_LINE_OUT_GND_STP; + lo_ctrl |= vag << SGTL5000_LINE_OUT_GND_SHIFT; + + /* enable small pop */ + ref_ctrl |= SGTL5000_SMALL_POP; + + /* Controls the output bias current for the lineout */ + lo_ctrl |= + (SGTL5000_LINE_OUT_CURRENT_360u << SGTL5000_LINE_OUT_CURRENT_SHIFT); + + /* set short detect */ + /* keep default */ + + /* set routing */ + /* keep default, bypass DAP */ + + sgtl5000_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); + msleep(10); + + /* For rev 0x11, if vddd linear reg has been enabled, we have + to disable simple reg to get proper VDDD voltage. */ + if ((ana_pwr & SGTL5000_LINEREG_D_POWERUP) && (sgtl5000->rev >= 0x11)) { + ana_pwr &= ~SGTL5000_LINREG_SIMPLE_POWERUP; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr); + msleep(10); + } + + sgtl5000_write(codec, SGTL5000_CHIP_REF_CTRL, ref_ctrl); + sgtl5000_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, lo_ctrl); + sgtl5000_write(codec, SGTL5000_CHIP_SHORT_CTRL, short_ctrl); + sgtl5000_write(codec, SGTL5000_CHIP_SSS_CTRL, sss); + sgtl5000_write(codec, SGTL5000_CHIP_DIG_POWER, 0); + + reg = SGTL5000_DAC_VOL_RAMP_EN | + SGTL5000_DAC_MUTE_RIGHT | SGTL5000_DAC_MUTE_LEFT; + sgtl5000_write(codec, SGTL5000_CHIP_ADCDAC_CTRL, reg); + +#ifdef CONFIG_ARCH_MXC + if (cpu_is_mx25()) + sgtl5000_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x01df); + else +#endif + sgtl5000_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f); + + reg = sgtl5000_read(codec, SGTL5000_CHIP_ANA_ADC_CTRL); + reg &= ~SGTL5000_ADC_VOL_M6DB; + reg &= ~(SGTL5000_ADC_VOL_LEFT_MASK | SGTL5000_ADC_VOL_RIGHT_MASK); + reg |= (0xf << SGTL5000_ADC_VOL_LEFT_SHIFT) + | (0xf << SGTL5000_ADC_VOL_RIGHT_SHIFT); + sgtl5000_write(codec, SGTL5000_CHIP_ANA_ADC_CTRL, reg); + + reg = SGTL5000_LINE_OUT_MUTE | SGTL5000_HP_MUTE | + SGTL5000_HP_ZCD_EN | SGTL5000_ADC_ZCD_EN; + sgtl5000_write(codec, SGTL5000_CHIP_ANA_CTRL, reg); + + sgtl5000_write(codec, SGTL5000_CHIP_MIC_CTRL, 0); + sgtl5000_write(codec, SGTL5000_CHIP_CLK_TOP_CTRL, 0); + /* disable DAP */ + sgtl5000_write(codec, SGTL5000_DAP_CTRL, 0); + /* TODO: initialize DAP */ + + snd_soc_add_controls(codec, sgtl5000_snd_controls, + ARRAY_SIZE(sgtl5000_snd_controls)); + sgtl5000_add_widgets(codec); + + sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + return 0; +} + +/* + * This function forces any delayed work to be queued and run. + */ +static int run_delayed_work(struct delayed_work *dwork) +{ + int ret; + + /* cancel any work waiting to be queued. */ + ret = cancel_delayed_work(dwork); + + /* if there was any work waiting then we run it now and + * wait for it's completion */ + if (ret) { + schedule_delayed_work(dwork, 0); + flush_scheduled_work(); + } + return ret; +} + +/* power down chip */ +static int sgtl5000_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct snd_soc_codec *codec = socdev->card->codec; + + if (codec->control_data) + sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF); + run_delayed_work(&codec->delayed_work); + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); + + return 0; +} + +struct snd_soc_codec_device soc_codec_dev_sgtl5000 = { + .probe = sgtl5000_probe, + .remove = sgtl5000_remove, + .suspend = sgtl5000_suspend, + .resume = sgtl5000_resume, +}; +EXPORT_SYMBOL_GPL(soc_codec_dev_sgtl5000); + +static __devinit int sgtl5000_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct sgtl5000_priv *sgtl5000; + struct snd_soc_codec *codec; + struct regulator *reg; + int ret = 0; + u32 val; + + if (sgtl5000_codec) { + dev_err(&client->dev, + "Multiple SGTL5000 devices not supported\n"); + return -ENOMEM; + } + + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; + + sgtl5000 = kzalloc(sizeof(struct sgtl5000_priv), GFP_KERNEL); + if (sgtl5000 == NULL) { + kfree(codec); + return -ENOMEM; + } + + snd_soc_codec_set_drvdata(codec, sgtl5000); + mutex_init(&codec->mutex); + INIT_LIST_HEAD(&codec->dapm_widgets); + INIT_LIST_HEAD(&codec->dapm_paths); + + i2c_set_clientdata(client, codec); + codec->control_data = client; + + reg = regulator_get(&client->dev, "VDDIO"); + if (!IS_ERR(reg)) + sgtl5000->reg_vddio = reg; + + reg = regulator_get(&client->dev, "VDDA"); + if (!IS_ERR(reg)) + sgtl5000->reg_vdda = reg; + + reg = regulator_get(&client->dev, "VDDD"); + if (!IS_ERR(reg)) + sgtl5000->reg_vddd = reg; + + if (sgtl5000->reg_vdda) { + sgtl5000->vdda = + regulator_get_voltage(sgtl5000->reg_vdda) / 1000; + regulator_enable(sgtl5000->reg_vdda); + } + if (sgtl5000->reg_vddio) { + sgtl5000->vddio = + regulator_get_voltage(sgtl5000->reg_vddio) / 1000; + regulator_enable(sgtl5000->reg_vddio); + } + if (sgtl5000->reg_vddd) { + sgtl5000->vddd = + regulator_get_voltage(sgtl5000->reg_vddd) / 1000; + regulator_enable(sgtl5000->reg_vddd); + } else { + sgtl5000->vddd = 0; /* use internal regulator */ + } + + msleep(1); + + val = sgtl5000_read(codec, SGTL5000_CHIP_ID); + if (((val & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != + SGTL5000_PARTID_PART_ID) { + pr_err("Device with ID register %x is not a SGTL5000\n", val); + ret = -ENODEV; + goto err_codec_reg; + } + + sgtl5000->rev = (val & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; + dev_info(&client->dev, "SGTL5000 revision %d\n", sgtl5000->rev); + + codec->dev = &client->dev; + codec->name = "SGTL5000"; + codec->owner = THIS_MODULE; + codec->read = sgtl5000_read_reg_cache; + codec->write = sgtl5000_write; + codec->bias_level = SND_SOC_BIAS_OFF; + codec->set_bias_level = sgtl5000_set_bias_level; + codec->dai = &sgtl5000_dai; + codec->num_dai = 1; + codec->reg_cache_size = sizeof(sgtl5000_regs); + codec->reg_cache_step = 2; + codec->reg_cache = (void *)&sgtl5000_regs; + + sgtl5000_sync_reg_cache(codec); + + sgtl5000_codec = codec; + sgtl5000_dai.dev = &client->dev; + + ret = snd_soc_register_codec(codec); + if (ret != 0) { + dev_err(codec->dev, "Failed to register codec: %d\n", ret); + goto err_codec_reg; + } + + ret = snd_soc_register_dai(&sgtl5000_dai); + if (ret != 0) { + dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); + goto err_codec_reg; + } + + return 0; + +err_codec_reg: + if (sgtl5000->reg_vddd) + regulator_disable(sgtl5000->reg_vddd); + if (sgtl5000->reg_vdda) + regulator_disable(sgtl5000->reg_vdda); + if (sgtl5000->reg_vddio) + regulator_disable(sgtl5000->reg_vddio); + if (sgtl5000->reg_vddd) + regulator_put(sgtl5000->reg_vddd); + if (sgtl5000->reg_vdda) + regulator_put(sgtl5000->reg_vdda); + if (sgtl5000->reg_vddio) + regulator_put(sgtl5000->reg_vddio); + kfree(sgtl5000); + kfree(codec); + return ret; +} + +static __devexit int sgtl5000_i2c_remove(struct i2c_client *client) +{ + struct snd_soc_codec *codec = i2c_get_clientdata(client); + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + + if (client->dev.platform_data) + clk_disable((struct clk *)client->dev.platform_data); + + snd_soc_unregister_dai(&sgtl5000_dai); + snd_soc_unregister_codec(codec); + + if (sgtl5000->reg_vddio) { + regulator_disable(sgtl5000->reg_vddio); + regulator_put(sgtl5000->reg_vddio); + } + if (sgtl5000->reg_vddd) { + regulator_disable(sgtl5000->reg_vddd); + regulator_put(sgtl5000->reg_vddd); + } + if (sgtl5000->reg_vdda) { + regulator_disable(sgtl5000->reg_vdda); + regulator_put(sgtl5000->reg_vdda); + } + + kfree(codec); + kfree(sgtl5000); + sgtl5000_codec = NULL; + return 0; +} + +static const struct i2c_device_id sgtl5000_id[] = { + {"sgtl5000-i2c", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, sgtl5000_id); + +static struct i2c_driver sgtl5000_i2c_driver = { + .driver = { + .name = "sgtl5000-i2c", + .owner = THIS_MODULE, + }, + .probe = sgtl5000_i2c_probe, + .remove = __devexit_p(sgtl5000_i2c_remove), + .id_table = sgtl5000_id, +}; + +static int __init sgtl5000_modinit(void) +{ + return i2c_add_driver(&sgtl5000_i2c_driver); +} +module_init(sgtl5000_modinit); + +static void __exit sgtl5000_exit(void) +{ + i2c_del_driver(&sgtl5000_i2c_driver); +} +module_exit(sgtl5000_exit); + +MODULE_DESCRIPTION("ASoC SGTL5000 driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h new file mode 100644 index 000000000000..49b444cd070d --- /dev/null +++ b/sound/soc/codecs/sgtl5000.h @@ -0,0 +1,410 @@ +/* + * sgtl5000.h - SGTL5000 audio codec interface + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef _SGTL5000_H +#define _SGTL5000_H + +#include + +extern struct snd_soc_dai sgtl5000_dai; +extern struct snd_soc_codec_device soc_codec_dev_sgtl5000; + +/* + * Register values. + */ +#define SGTL5000_CHIP_ID 0x0000 +#define SGTL5000_CHIP_DIG_POWER 0x0002 +#define SGTL5000_CHIP_CLK_CTRL 0x0004 +#define SGTL5000_CHIP_I2S_CTRL 0x0006 +#define SGTL5000_CHIP_SSS_CTRL 0x000a +#define SGTL5000_CHIP_ADCDAC_CTRL 0x000e +#define SGTL5000_CHIP_DAC_VOL 0x0010 +#define SGTL5000_CHIP_PAD_STRENGTH 0x0014 +#define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020 +#define SGTL5000_CHIP_ANA_HP_CTRL 0x0022 +#define SGTL5000_CHIP_ANA_CTRL 0x0024 +#define SGTL5000_CHIP_LINREG_CTRL 0x0026 +#define SGTL5000_CHIP_REF_CTRL 0x0028 +#define SGTL5000_CHIP_MIC_CTRL 0x002a +#define SGTL5000_CHIP_LINE_OUT_CTRL 0x002c +#define SGTL5000_CHIP_LINE_OUT_VOL 0x002e +#define SGTL5000_CHIP_ANA_POWER 0x0030 +#define SGTL5000_CHIP_PLL_CTRL 0x0032 +#define SGTL5000_CHIP_CLK_TOP_CTRL 0x0034 +#define SGTL5000_CHIP_ANA_STATUS 0x0036 +#define SGTL5000_CHIP_SHORT_CTRL 0x003c +#define SGTL5000_CHIP_ANA_TEST2 0x003a +#define SGTL5000_DAP_CTRL 0x0100 +#define SGTL5000_DAP_PEQ 0x0102 +#define SGTL5000_DAP_BASS_ENHANCE 0x0104 +#define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106 +#define SGTL5000_DAP_AUDIO_EQ 0x0108 +#define SGTL5000_DAP_SURROUND 0x010a +#define SGTL5000_DAP_FLT_COEF_ACCESS 0x010c +#define SGTL5000_DAP_COEF_WR_B0_MSB 0x010e +#define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110 +#define SGTL5000_DAP_EQ_BASS_BAND0 0x0116 +#define SGTL5000_DAP_EQ_BASS_BAND1 0x0118 +#define SGTL5000_DAP_EQ_BASS_BAND2 0x011a +#define SGTL5000_DAP_EQ_BASS_BAND3 0x011c +#define SGTL5000_DAP_EQ_BASS_BAND4 0x011e +#define SGTL5000_DAP_MAIN_CHAN 0x0120 +#define SGTL5000_DAP_MIX_CHAN 0x0122 +#define SGTL5000_DAP_AVC_CTRL 0x0124 +#define SGTL5000_DAP_AVC_THRESHOLD 0x0126 +#define SGTL5000_DAP_AVC_ATTACK 0x0128 +#define SGTL5000_DAP_AVC_DECAY 0x012a +#define SGTL5000_DAP_COEF_WR_B1_MSB 0x012c +#define SGTL5000_DAP_COEF_WR_B1_LSB 0x012e +#define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130 +#define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132 +#define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134 +#define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136 +#define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138 +#define SGTL5000_DAP_COEF_WR_A2_LSB 0x013a + +/* + * Field Definitions. + */ + +/* + * SGTL5000_CHIP_ID + */ +#define SGTL5000_PARTID_MASK 0xff00 +#define SGTL5000_PARTID_SHIFT 8 +#define SGTL5000_PARTID_WIDTH 8 +#define SGTL5000_PARTID_PART_ID 0xa0 +#define SGTL5000_REVID_MASK 0x00ff +#define SGTL5000_REVID_SHIFT 0 +#define SGTL5000_REVID_WIDTH 8 + +/* + * SGTL5000_CHIP_DIG_POWER + */ +#define SGTL5000_ADC_EN 0x0040 +#define SGTL5000_DAC_EN 0x0020 +#define SGTL5000_DAP_POWERUP 0x0010 +#define SGTL5000_I2S_OUT_POWERUP 0x0002 +#define SGTL5000_I2S_IN_POWERUP 0x0001 + +/* + * SGTL5000_CHIP_CLK_CTRL + */ +#define SGTL5000_RATE_MODE_MASK 0x0030 +#define SGTL5000_RATE_MODE_SHIFT 4 +#define SGTL5000_RATE_MODE_WIDTH 2 +#define SGTL5000_RATE_MODE_DIV_1 0 +#define SGTL5000_RATE_MODE_DIV_2 1 +#define SGTL5000_RATE_MODE_DIV_4 2 +#define SGTL5000_RATE_MODE_DIV_6 3 +#define SGTL5000_SYS_FS_MASK 0x000c +#define SGTL5000_SYS_FS_SHIFT 2 +#define SGTL5000_SYS_FS_WIDTH 2 +#define SGTL5000_SYS_FS_32k 0x0 +#define SGTL5000_SYS_FS_44_1k 0x1 +#define SGTL5000_SYS_FS_48k 0x2 +#define SGTL5000_SYS_FS_96k 0x3 +#define SGTL5000_MCLK_FREQ_MASK 0x0003 +#define SGTL5000_MCLK_FREQ_SHIFT 0 +#define SGTL5000_MCLK_FREQ_WIDTH 2 +#define SGTL5000_MCLK_FREQ_256FS 0x0 +#define SGTL5000_MCLK_FREQ_384FS 0x1 +#define SGTL5000_MCLK_FREQ_512FS 0x2 +#define SGTL5000_MCLK_FREQ_PLL 0x3 + +/* + * SGTL5000_CHIP_I2S_CTRL + */ +#define SGTL5000_I2S_SCLKFREQ_MASK 0x0100 +#define SGTL5000_I2S_SCLKFREQ_SHIFT 8 +#define SGTL5000_I2S_SCLKFREQ_WIDTH 1 +#define SGTL5000_I2S_SCLKFREQ_64FS 0x0 +#define SGTL5000_I2S_SCLKFREQ_32FS 0x1 /* Not for RJ mode */ +#define SGTL5000_I2S_MASTER 0x0080 +#define SGTL5000_I2S_SCLK_INV 0x0040 +#define SGTL5000_I2S_DLEN_MASK 0x0030 +#define SGTL5000_I2S_DLEN_SHIFT 4 +#define SGTL5000_I2S_DLEN_WIDTH 2 +#define SGTL5000_I2S_DLEN_32 0x0 +#define SGTL5000_I2S_DLEN_24 0x1 +#define SGTL5000_I2S_DLEN_20 0x2 +#define SGTL5000_I2S_DLEN_16 0x3 +#define SGTL5000_I2S_MODE_MASK 0x000c +#define SGTL5000_I2S_MODE_SHIFT 2 +#define SGTL5000_I2S_MODE_WIDTH 2 +#define SGTL5000_I2S_MODE_I2S_LJ 0x0 +#define SGTL5000_I2S_MODE_RJ 0x1 +#define SGTL5000_I2S_MODE_PCM 0x2 +#define SGTL5000_I2S_LRALIGN 0x0002 +#define SGTL5000_I2S_LRPOL 0x0001 /* set for which mode */ + +/* + * SGTL5000_CHIP_SSS_CTRL + */ +#define SGTL5000_DAP_MIX_LRSWAP 0x4000 +#define SGTL5000_DAP_LRSWAP 0x2000 +#define SGTL5000_DAC_LRSWAP 0x1000 +#define SGTL5000_I2S_OUT_LRSWAP 0x0400 +#define SGTL5000_DAP_MIX_SEL_MASK 0x0300 +#define SGTL5000_DAP_MIX_SEL_SHIFT 8 +#define SGTL5000_DAP_MIX_SEL_WIDTH 2 +#define SGTL5000_DAP_MIX_SEL_ADC 0x0 +#define SGTL5000_DAP_MIX_SEL_I2S_IN 0x1 +#define SGTL5000_DAP_SEL_MASK 0x00c0 +#define SGTL5000_DAP_SEL_SHIFT 6 +#define SGTL5000_DAP_SEL_WIDTH 2 +#define SGTL5000_DAP_SEL_ADC 0x0 +#define SGTL5000_DAP_SEL_I2S_IN 0x1 +#define SGTL5000_DAC_SEL_MASK 0x0030 +#define SGTL5000_DAC_SEL_SHIFT 4 +#define SGTL5000_DAC_SEL_WIDTH 2 +#define SGTL5000_DAC_SEL_ADC 0x0 +#define SGTL5000_DAC_SEL_I2S_IN 0x1 +#define SGTL5000_DAC_SEL_DAP 0x3 +#define SGTL5000_I2S_OUT_SEL_MASK 0x0003 +#define SGTL5000_I2S_OUT_SEL_SHIFT 0 +#define SGTL5000_I2S_OUT_SEL_WIDTH 2 +#define SGTL5000_I2S_OUT_SEL_ADC 0x0 +#define SGTL5000_I2S_OUT_SEL_I2S_IN 0x1 +#define SGTL5000_I2S_OUT_SEL_DAP 0x3 + +/* + * SGTL5000_CHIP_ADCDAC_CTRL + */ +#define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000 +#define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000 +#define SGTL5000_DAC_VOL_RAMP_EN 0x0200 +#define SGTL5000_DAC_VOL_RAMP_EXPO 0x0100 +#define SGTL5000_DAC_MUTE_RIGHT 0x0008 +#define SGTL5000_DAC_MUTE_LEFT 0x0004 +#define SGTL5000_ADC_HPF_FREEZE 0x0002 +#define SGTL5000_ADC_HPF_BYPASS 0x0001 + +/* + * SGTL5000_CHIP_DAC_VOL + */ +#define SGTL5000_DAC_VOL_RIGHT_MASK 0xff00 +#define SGTL5000_DAC_VOL_RIGHT_SHIFT 8 +#define SGTL5000_DAC_VOL_RIGHT_WIDTH 8 +#define SGTL5000_DAC_VOL_LEFT_MASK 0x00ff +#define SGTL5000_DAC_VOL_LEFT_SHIFT 0 +#define SGTL5000_DAC_VOL_LEFT_WIDTH 8 + +/* + * SGTL5000_CHIP_PAD_STRENGTH + */ +#define SGTL5000_PAD_I2S_LRCLK_MASK 0x0300 +#define SGTL5000_PAD_I2S_LRCLK_SHIFT 8 +#define SGTL5000_PAD_I2S_LRCLK_WIDTH 2 +#define SGTL5000_PAD_I2S_SCLK_MASK 0x00c0 +#define SGTL5000_PAD_I2S_SCLK_SHIFT 6 +#define SGTL5000_PAD_I2S_SCLK_WIDTH 2 +#define SGTL5000_PAD_I2S_DOUT_MASK 0x0030 +#define SGTL5000_PAD_I2S_DOUT_SHIFT 4 +#define SGTL5000_PAD_I2S_DOUT_WIDTH 2 +#define SGTL5000_PAD_I2C_SDA_MASK 0x000c +#define SGTL5000_PAD_I2C_SDA_SHIFT 2 +#define SGTL5000_PAD_I2C_SDA_WIDTH 2 +#define SGTL5000_PAD_I2C_SCL_MASK 0x0003 +#define SGTL5000_PAD_I2C_SCL_SHIFT 0 +#define SGTL5000_PAD_I2C_SCL_WIDTH 2 + +/* + * SGTL5000_CHIP_ANA_ADC_CTRL + */ +#define SGTL5000_ADC_VOL_M6DB 0x0100 +#define SGTL5000_ADC_VOL_RIGHT_MASK 0x00f0 +#define SGTL5000_ADC_VOL_RIGHT_SHIFT 4 +#define SGTL5000_ADC_VOL_RIGHT_WIDTH 4 +#define SGTL5000_ADC_VOL_LEFT_MASK 0x000f +#define SGTL5000_ADC_VOL_LEFT_SHIFT 0 +#define SGTL5000_ADC_VOL_LEFT_WIDTH 4 + +/* + * SGTL5000_CHIP_ANA_HP_CTRL + */ +#define SGTL5000_HP_VOL_RIGHT_MASK 0x7f00 +#define SGTL5000_HP_VOL_RIGHT_SHIFT 8 +#define SGTL5000_HP_VOL_RIGHT_WIDTH 7 +#define SGTL5000_HP_VOL_LEFT_MASK 0x007f +#define SGTL5000_HP_VOL_LEFT_SHIFT 0 +#define SGTL5000_HP_VOL_LEFT_WIDTH 7 + +/* + * SGTL5000_CHIP_ANA_CTRL + */ +#define SGTL5000_LINE_OUT_MUTE 0x0100 +#define SGTL5000_HP_SEL_MASK 0x0040 +#define SGTL5000_HP_SEL_SHIFT 6 +#define SGTL5000_HP_SEL_WIDTH 1 +#define SGTL5000_HP_SEL_DAC 0x0 +#define SGTL5000_HP_SEL_LINE_IN 0x1 +#define SGTL5000_HP_ZCD_EN 0x0020 +#define SGTL5000_HP_MUTE 0x0010 +#define SGTL5000_ADC_SEL_MASK 0x0004 +#define SGTL5000_ADC_SEL_SHIFT 2 +#define SGTL5000_ADC_SEL_WIDTH 1 +#define SGTL5000_ADC_SEL_MIC 0x0 +#define SGTL5000_ADC_SEL_LINE_IN 0x1 +#define SGTL5000_ADC_ZCD_EN 0x0002 +#define SGTL5000_ADC_MUTE 0x0001 + +/* + * SGTL5000_CHIP_LINREG_CTRL + */ +#define SGTL5000_VDDC_MAN_ASSN_MASK 0x0040 +#define SGTL5000_VDDC_MAN_ASSN_SHIFT 6 +#define SGTL5000_VDDC_MAN_ASSN_WIDTH 1 +#define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0 +#define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x1 +#define SGTL5000_VDDC_ASSN_OVRD 0x0020 +#define SGTL5000_LINREG_VDDD_MASK 0x000f +#define SGTL5000_LINREG_VDDD_SHIFT 0 +#define SGTL5000_LINREG_VDDD_WIDTH 4 + +/* + * SGTL5000_CHIP_REF_CTRL + */ +#define SGTL5000_ANA_GND_MASK 0x01f0 +#define SGTL5000_ANA_GND_SHIFT 4 +#define SGTL5000_ANA_GND_WIDTH 5 +#define SGTL5000_ANA_GND_BASE 800 /* mv */ +#define SGTL5000_ANA_GND_STP 25 /*mv */ +#define SGTL5000_BIAS_CTRL_MASK 0x000e +#define SGTL5000_BIAS_CTRL_SHIFT 1 +#define SGTL5000_BIAS_CTRL_WIDTH 3 +#define SGTL5000_SMALL_POP 0x0001 + +/* + * SGTL5000_CHIP_MIC_CTRL + */ +#define SGTL5000_BIAS_R_MASK 0x0200 +#define SGTL5000_BIAS_R_SHIFT 8 +#define SGTL5000_BIAS_R_WIDTH 2 +#define SGTL5000_BIAS_R_off 0x0 +#define SGTL5000_BIAS_R_2K 0x1 +#define SGTL5000_BIAS_R_4k 0x2 +#define SGTL5000_BIAS_R_8k 0x3 +#define SGTL5000_BIAS_VOLT_MASK 0x0070 +#define SGTL5000_BIAS_VOLT_SHIFT 4 +#define SGTL5000_BIAS_VOLT_WIDTH 3 +#define SGTL5000_MIC_GAIN_MASK 0x0003 +#define SGTL5000_MIC_GAIN_SHIFT 0 +#define SGTL5000_MIC_GAIN_WIDTH 2 + +/* + * SGTL5000_CHIP_LINE_OUT_CTRL + */ +#define SGTL5000_LINE_OUT_CURRENT_MASK 0x0f00 +#define SGTL5000_LINE_OUT_CURRENT_SHIFT 8 +#define SGTL5000_LINE_OUT_CURRENT_WIDTH 4 +#define SGTL5000_LINE_OUT_CURRENT_180u 0x0 +#define SGTL5000_LINE_OUT_CURRENT_270u 0x1 +#define SGTL5000_LINE_OUT_CURRENT_360u 0x3 +#define SGTL5000_LINE_OUT_CURRENT_450u 0x7 +#define SGTL5000_LINE_OUT_CURRENT_540u 0xf +#define SGTL5000_LINE_OUT_GND_MASK 0x003f +#define SGTL5000_LINE_OUT_GND_SHIFT 0 +#define SGTL5000_LINE_OUT_GND_WIDTH 6 +#define SGTL5000_LINE_OUT_GND_BASE 800 /* mv */ +#define SGTL5000_LINE_OUT_GND_STP 25 +#define SGTL5000_LINE_OUT_GND_MAX 0x23 + +/* + * SGTL5000_CHIP_LINE_OUT_VOL + */ +#define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 0x1f00 +#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 8 +#define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH 5 +#define SGTL5000_LINE_OUT_VOL_LEFT_MASK 0x001f +#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0 +#define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH 5 + +/* + * SGTL5000_CHIP_ANA_POWER + */ +#define SGTL5000_DAC_STEREO 0x4000 +#define SGTL5000_LINREG_SIMPLE_POWERUP 0x2000 +#define SGTL5000_STARTUP_POWERUP 0x1000 +#define SGTL5000_VDDC_CHRGPMP_POWERUP 0x0800 +#define SGTL5000_PLL_POWERUP 0x0400 +#define SGTL5000_LINEREG_D_POWERUP 0x0200 +#define SGTL5000_VCOAMP_POWERUP 0x0100 +#define SGTL5000_VAG_POWERUP 0x0080 +#define SGTL5000_ADC_STEREO 0x0040 +#define SGTL5000_REFTOP_POWERUP 0x0020 +#define SGTL5000_HP_POWERUP 0x0010 +#define SGTL5000_DAC_POWERUP 0x0008 +#define SGTL5000_CAPLESS_HP_POWERUP 0x0004 +#define SGTL5000_ADC_POWERUP 0x0002 +#define SGTL5000_LINE_OUT_POWERUP 0x0001 + +/* + * SGTL5000_CHIP_PLL_CTRL + */ +#define SGTL5000_PLL_INT_DIV_MASK 0xf800 +#define SGTL5000_PLL_INT_DIV_SHIFT 11 +#define SGTL5000_PLL_INT_DIV_WIDTH 5 +#define SGTL5000_PLL_FRAC_DIV_MASK 0x0700 +#define SGTL5000_PLL_FRAC_DIV_SHIFT 0 +#define SGTL5000_PLL_FRAC_DIV_WIDTH 11 + +/* + * SGTL5000_CHIP_CLK_TOP_CTRL + */ +#define SGTL5000_INT_OSC_EN 0x0800 +#define SGTL5000_INPUT_FREQ_DIV2 0x0008 + +/* + * SGTL5000_CHIP_ANA_STATUS + */ +#define SGTL5000_HP_LRSHORT 0x0200 +#define SGTL5000_CAPLESS_SHORT 0x0100 +#define SGTL5000_PLL_LOCKED 0x0010 + +/* + * SGTL5000_CHIP_SHORT_CTRL + */ +#define SGTL5000_LVLADJR_MASK 0x7000 +#define SGTL5000_LVLADJR_SHIFT 12 +#define SGTL5000_LVLADJR_WIDTH 3 +#define SGTL5000_LVLADJL_MASK 0x0700 +#define SGTL5000_LVLADJL_SHIFT 8 +#define SGTL5000_LVLADJL_WIDTH 3 +#define SGTL5000_LVLADJC_MASK 0x0070 +#define SGTL5000_LVLADJC_SHIFT 4 +#define SGTL5000_LVLADJC_WIDTH 3 +#define SGTL5000_LR_SHORT_MOD_MASK 0x000c +#define SGTL5000_LR_SHORT_MOD_SHIFT 2 +#define SGTL5000_LR_SHORT_MOD_WIDTH 2 +#define SGTL5000_CM_SHORT_MOD_MASK 0x0003 +#define SGTL5000_CM_SHORT_MOD_SHIFT 0 +#define SGTL5000_CM_SHORT_MOD_WIDTH 2 + +/* + *SGTL5000_CHIP_ANA_TEST2 + */ +#define SGTL5000_MONO_DAC 0x1000 + +/* + * SGTL5000_DAP_CTRL + */ +#define SGTL5000_DAP_MIX_EN 0x0010 +#define SGTL5000_DAP_EN 0x0001 + +#define SGTL5000_SYSCLK 0x00 +#define SGTL5000_LRCLK 0x01 + +struct sgtl5000_setup_data { + int (*clock_enable) (int enable); +}; + +#endif diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c index 0221ca79b3ae..b9ee3cfee17f 100644 --- a/sound/soc/codecs/wm8350.c +++ b/sound/soc/codecs/wm8350.c @@ -1136,7 +1136,7 @@ static int wm8350_set_fll(struct snd_soc_dai *codec_dai, fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) & ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000); wm8350_codec_write(codec, WM8350_FLL_CONTROL_1, - fll_1 | (fll_div.div << 8) | 0x50); + fll_1 | (fll_div.div << 8)); wm8350_codec_write(codec, WM8350_FLL_CONTROL_2, (fll_div.ratio << 11) | (fll_div. n & WM8350_FLL_N_MASK)); @@ -1534,13 +1534,13 @@ static int wm8350_probe(struct platform_device *pdev) /* Latch VU bits & mute */ wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, - WM8350_OUT1_VU | WM8350_OUT1L_MUTE); + WM8350_OUT1_VU); wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, - WM8350_OUT2_VU | WM8350_OUT2L_MUTE); + WM8350_OUT2_VU); wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME, - WM8350_OUT1_VU | WM8350_OUT1R_MUTE); + WM8350_OUT1_VU); wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME, - WM8350_OUT2_VU | WM8350_OUT2R_MUTE); + WM8350_OUT2_VU); /* Make sure jack detect is disabled to start off with */ wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index c3571ee5c11b..75a92347718c 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -163,6 +164,8 @@ #define WM8580_DAC_CONTROL5_MUTEALL 0x10 +#define WM8580_REG_DATA_LENGTH 9 + /* * wm8580 register cache * We can't read the WM8580 register space when we @@ -190,11 +193,8 @@ struct pll_state { unsigned int out; }; -#define WM8580_NUM_SUPPLIES 3 +#define WM8580_NUM_SUPPLIES 0 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = { - "AVDD", - "DVDD", - "PVDD", }; /* codec private data */ @@ -259,7 +259,6 @@ SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume", WM8580_DIGITAL_ATTENUATION_DACL3, WM8580_DIGITAL_ATTENUATION_DACR3, 0, 0xff, 0, dac_tlv), - SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0), SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0), SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0), @@ -463,7 +462,7 @@ static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, (pll_div.k >> 18 & 0xf) | (pll_div.n << 4)); reg = snd_soc_read(codec, WM8580_PLLA4 + offset); - reg &= ~0x1b; + reg &= ~0x3b; reg |= pll_div.prescale | pll_div.postscale << 1 | pll_div.freqmode << 3; @@ -679,6 +678,33 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, return 0; } +static int wm8580_set_paif_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = codec_dai->codec; + unsigned int reg; + + switch (clk_id) { + case WM8580_BCLK_CLKDIV: + reg = snd_soc_read(codec, WM8580_PAIF1) & + ~WM8580_AIF_BCLKSEL_MASK; + snd_soc_write(codec, WM8580_PAIF1, reg | freq); + reg = snd_soc_read(codec, WM8580_PAIF2) & + ~WM8580_AIF_BCLKSEL_MASK; + snd_soc_write(codec, WM8580_PAIF2, reg | freq); + break; + case WM8580_LRCLK_CLKDIV: + reg = snd_soc_read(codec, WM8580_PAIF1) & ~0x07; + snd_soc_write(codec, WM8580_PAIF1, reg | freq); + break; + + default: + return -EINVAL; + } + + return 0; +} + static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute) { struct snd_soc_codec *codec = codec_dai->codec; @@ -734,6 +760,7 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec, static struct snd_soc_dai_ops wm8580_dai_ops_playback = { .hw_params = wm8580_paif_hw_params, .set_fmt = wm8580_set_paif_dai_fmt, + .set_sysclk = wm8580_set_paif_dai_sysclk, .set_clkdiv = wm8580_set_dai_clkdiv, .set_pll = wm8580_set_dai_pll, .digital_mute = wm8580_digital_mute, @@ -970,6 +997,91 @@ static struct i2c_driver wm8580_i2c_driver = { }; #endif +#if defined(CONFIG_SPI) || defined(CONFIG_SPI_MODULE) + /*! + * This function is called to transfer data to WM8580 on SPI. + * + * @param spi the SPI slave device(WM8580) + * @param buf the pointer to the data buffer + * @param len the length of the data to be transferred + * + * @return Returns 0 on success -1 on failure. + */ +static inline int spi_rw(void *control_data, char *data, int length) +{ + int ret; + struct spi_transfer t = { + .tx_buf = (const void *)data, + .rx_buf = (void *)data, + .len = length / 2, + .cs_change = 0, + .delay_usecs = 0, + }; + struct spi_message m; + u8 temp = data[0]; + data[0] = data[1]; + data[1] = temp; + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + ret = spi_sync((struct spi_device *)control_data, &m); + if (unlikely(ret < 0)) + return ret; + else + return length; + +} + +/*! + * This function is called whenever the SPI slave device is detected. + * + * @param spi the SPI slave device + * + * @return Returns 0 on SUCCESS and error on FAILURE. + */ +static int __devinit wm8580_spi_probe(struct spi_device *spi) +{ + struct wm8580_priv *wm8580; + struct snd_soc_codec *codec; + + wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL); + if (wm8580 == NULL) + return -ENOMEM; + + codec = &wm8580->codec; + + spi->bits_per_word = 16; + spi->mode = SPI_MODE_2; + + spi_setup(spi); + + spi_set_drvdata(spi, wm8580); + codec->hw_write = (hw_write_t) spi_rw; + codec->control_data = spi; + + codec->dev = &spi->dev; + + return wm8580_register(wm8580, SND_SOC_SPI); +} + +static int __devinit wm8580_spi_remove(struct spi_device *spi) +{ + struct wm8580_priv *wm8580 = spi_get_drvdata(spi); + wm8580_unregister(wm8580); + return 0; +} + +static struct spi_driver wm8580_spi_driver = { + .driver = { + .name = "wm8580_spi", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = wm8580_spi_probe, + .remove = __devexit_p(wm8580_spi_remove), +}; +#endif + static int __init wm8580_modinit(void) { int ret; @@ -981,6 +1093,13 @@ static int __init wm8580_modinit(void) } #endif +#if defined(CONFIG_SPI) || defined(CONFIG_SPI_MODULE) + spi_register_driver(&wm8580_spi_driver); + if (ret != 0) { + pr_err("Failed to register WM8580 SPI driver: %d\n", ret); + } +#endif + return 0; } module_init(wm8580_modinit); @@ -990,6 +1109,10 @@ static void __exit wm8580_exit(void) #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) i2c_del_driver(&wm8580_i2c_driver); #endif + +#if defined(CONFIG_SPI) || defined(CONFIG_SPI_MODULE) + spi_unregister_driver(&wm8580_spi_driver); +#endif } module_exit(wm8580_exit); diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h index 0dfb5ddde6a2..0c51ede6b13b 100644 --- a/sound/soc/codecs/wm8580.h +++ b/sound/soc/codecs/wm8580.h @@ -28,6 +28,15 @@ #define WM8580_CLKSRC_OSC 4 #define WM8580_CLKSRC_NONE 5 +/*clock divider id's */ +#define WM8580_BCLK_CLKDIV 0 +#define WM8580_LRCLK_CLKDIV 1 + +struct wm8580_setup_data { + unsigned short spi; + unsigned short i2c_address; +}; + #define WM8580_DAI_PAIFRX 0 #define WM8580_DAI_PAIFTX 1 diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig index 252defea93b5..45033c2ecbdf 100644 --- a/sound/soc/imx/Kconfig +++ b/sound/soc/imx/Kconfig @@ -1,15 +1,15 @@ -config SND_IMX_SOC +config SND_MXC_SOC tristate "SoC Audio for Freescale i.MX CPUs" depends on ARCH_MXC select SND_PCM - select FIQ - select SND_SOC_AC97_BUS help Say Y or M if you want to add support for codecs attached to the i.MX SSI interface. +if SND_MXC_SOC + config SND_MXC_SOC_SSI - tristate + tristate config SND_MXC_SOC_WM1133_EV1 tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted" @@ -28,3 +28,80 @@ config SND_SOC_PHYCORE_AC97 help Say Y if you want to add support for SoC audio on Phytec phyCORE and phyCARD boards in AC97 mode + +config SND_MXC_SOC_ESAI + tristate + +config SND_MXC_SOC_AC97 + tristate + +config SND_MXC_SOC_IRAM + bool "Locate Audio DMA playback buffers in IRAM" + help + Say Y if you don't want Audio playback buffers in external ram + +config SND_SOC_IMX_3STACK_WM8350 + tristate "SoC Audio support for IMX - WM8350" + depends on MFD_WM8350 + select SND_MXC_SOC_SSI + select SND_SOC_WM8350 + help + Say Y if you want to add support for SoC audio on IMX 3STACK + with the WM8350. + +config SND_SOC_IMX_3STACK_SGTL5000 + tristate "SoC Audio support for IMX - SGTL5000" + select SND_MXC_SOC_SSI + select SND_SOC_SGTL5000 + help + Say Y if you want to add support for SoC audio on IMX 3STACK + with the SGTL5000. + +config SND_SOC_IMX_3STACK_AK4647 + tristate "SoC Audio support for IMX - AK4647" + select SND_MXC_SOC_SSI + select SND_SOC_AK4647 + help + Say Y if you want to add support for SoC audio on IMX 3STACK + with the AK4647. + +config SND_SOC_IMX_3STACK_WM8580 + tristate "SoC Audio support for IMX - WM8580" + select SND_MXC_SOC_ESAI + select SND_SOC_WM8580 + help + Say Y if you want to add support for Soc audio on IMX 3STACK + with the WM8580 + +config SND_SOC_IMX_3STACK_AK5702 + tristate "SoC Audio support for IMX - AK5702" + select SND_MXC_SOC_ESAI + select SND_SOC_AK5702 + help + Say Y if you want to add support for Soc audio on IMX 3STACK + with the AK5702 + +config SND_SOC_IMX_3STACK_BLUETOOTH + tristate "SoC Audio support for IMX - BLUETOOTH" + select SND_MXC_SOC_SSI + select SND_SOC_BLUETOOTH + help + Say Y if you want to add support for Soc audio on IMX 3STACK + with the BLUETOOTH + +config SND_SOC_IMX_3STACK_CS42888 + tristate "SoC Audio support for IMX - CS42888" + select SND_MXC_SOC_ESAI + select SND_SOC_CS42888 + help + Say Y if you want to add support for Soc audio on IMX 3STACK + with the CS42888 + +config MXC_SSI_DUAL_FIFO + bool "MXC SSI enable dual fifo" + def_bool n + depends on SND_MXC_SOC_SSI && (ARCH_MX51 || ARCH_MX53) + help + Say Y if you want to use 2 ssi fifo for audio transfer, + NOTE: ONLY support MX51 and MX53. +endif diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile index 2d203635ac11..657777f6dd2f 100644 --- a/sound/soc/imx/Makefile +++ b/sound/soc/imx/Makefile @@ -1,15 +1,37 @@ # i.MX Platform Support -snd-soc-imx-objs := imx-ssi.o imx-pcm-fiq.o +snd-soc-imx-objs := imx-pcm.o +snd-soc-imx-ssi-objs := imx-ssi.o +snd-soc-imx-esai-objs := imx-esai.o ifdef CONFIG_MACH_MX27 snd-soc-imx-objs += imx-pcm-dma-mx2.o endif -obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o - # i.MX Machine Support snd-soc-phycore-ac97-objs := phycore-ac97.o snd-soc-wm1133-ev1-objs := wm1133-ev1.o obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o + +obj-$(CONFIG_SND_MXC_SOC) += snd-soc-imx.o +obj-$(CONFIG_SND_MXC_SOC_SSI) += snd-soc-imx-ssi.o +obj-$(CONFIG_SND_MXC_SOC_ESAI) += snd-soc-imx-esai.o +obj-$(CONFIG_SND_MXC_SOC_AC97) += snd-soc-imx-ac97.o + +# i.MX Machine Support +snd-soc-imx-3stack-wm8350-objs := imx-3stack-wm8350.o +obj-$(CONFIG_SND_SOC_IMX_3STACK_WM8350) += snd-soc-imx-3stack-wm8350.o +snd-soc-imx-3stack-sgtl5000-objs := imx-3stack-sgtl5000.o +obj-$(CONFIG_SND_SOC_IMX_3STACK_SGTL5000) += snd-soc-imx-3stack-sgtl5000.o +snd-soc-imx-3stack-ak4647-objs := imx-3stack-ak4647.o +obj-$(CONFIG_SND_SOC_IMX_3STACK_AK4647) += snd-soc-imx-3stack-ak4647.o +snd-soc-imx-3stack-wm8580-objs := imx-3stack-wm8580.o +obj-$(CONFIG_SND_SOC_IMX_3STACK_WM8580) += snd-soc-imx-3stack-wm8580.o +snd-soc-imx-3stack-ak5702-objs := imx-3stack-ak5702.o +obj-$(CONFIG_SND_SOC_IMX_3STACK_AK5702) += snd-soc-imx-3stack-ak5702.o +snd-soc-imx-3stack-bt-objs := imx-3stack-bt.o +obj-$(CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH) += snd-soc-imx-3stack-bt.o +snd-soc-imx-3stack-cs42888-objs := imx-3stack-cs42888.o +obj-$(CONFIG_SND_SOC_IMX_3STACK_CS42888) += snd-soc-imx-3stack-cs42888.o + diff --git a/sound/soc/imx/imx-3stack-ak4647.c b/sound/soc/imx/imx-3stack-ak4647.c new file mode 100644 index 000000000000..56c7a498e5b1 --- /dev/null +++ b/sound/soc/imx/imx-3stack-ak4647.c @@ -0,0 +1,445 @@ +/* + * imx-3stack-ak4647.c -- SoC audio for imx_3stack + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-pcm.h" +#include "imx-ssi.h" + +#define AK4647_SSI_MASTER 1 + +extern struct snd_soc_dai ak4647_hifi_dai; +extern struct snd_soc_codec_device soc_codec_dev_ak4647; + +static void headphone_detect_handler(struct work_struct *work); +static DECLARE_WORK(hp_event, headphone_detect_handler); +static int ak4647_jack_func; +static int ak4647_spk_func; + +struct imx_3stack_priv { + struct platform_device *pdev; +}; + +static struct imx_3stack_priv card_priv; + +static void imx_3stack_init_dam(int ssi_port, int dai_port) +{ + /* AK4647 uses SSI1 or SSI2 via AUDMUX port dai_port for audio */ + unsigned int ssi_ptcr = 0; + unsigned int dai_ptcr = 0; + unsigned int ssi_pdcr = 0; + unsigned int dai_pdcr = 0; + + /* reset port ssi_port & dai_port */ + __raw_writel(0, DAM_PTCR(ssi_port)); + __raw_writel(0, DAM_PTCR(dai_port)); + __raw_writel(0, DAM_PDCR(ssi_port)); + __raw_writel(0, DAM_PDCR(dai_port)); + + /* set to synchronous */ + ssi_ptcr |= AUDMUX_PTCR_SYN; + dai_ptcr |= AUDMUX_PTCR_SYN; + +#if AK4647_SSI_MASTER + /* set Rx sources ssi_port <--> dai_port */ + ssi_pdcr |= AUDMUX_PDCR_RXDSEL(dai_port); + dai_pdcr |= AUDMUX_PDCR_RXDSEL(ssi_port); + + /* set Tx frame direction and source dai_port--> ssi_port output */ + ssi_ptcr |= AUDMUX_PTCR_TFSDIR; + ssi_ptcr |= AUDMUX_PTCR_TFSSEL(AUDMUX_FROM_TXFS, dai_port); + + /* set Tx Clock direction and source dai_port--> ssi_port output */ + ssi_ptcr |= AUDMUX_PTCR_TCLKDIR; + ssi_ptcr |= AUDMUX_PTCR_TCSEL(AUDMUX_FROM_TXFS, dai_port); +#else + /* set Rx sources ssi_port <--> dai_port */ + ssi_pdcr |= AUDMUX_PDCR_RXDSEL(dai_port); + dai_pdcr |= AUDMUX_PDCR_RXDSEL(ssi_port); + + /* set Tx frame direction and source ssi_port --> dai_port output */ + dai_ptcr |= AUDMUX_PTCR_TFSDIR; + dai_ptcr |= AUDMUX_PTCR_TFSSEL(AUDMUX_FROM_TXFS, ssi_port); + + /* set Tx Clock direction and source ssi_port--> dai_port output */ + dai_ptcr |= AUDMUX_PTCR_TCLKDIR; + dai_ptcr |= AUDMUX_PTCR_TCSEL(AUDMUX_FROM_TXFS, ssi_port); +#endif + + __raw_writel(ssi_ptcr, DAM_PTCR(ssi_port)); + __raw_writel(dai_ptcr, DAM_PTCR(dai_port)); + __raw_writel(ssi_pdcr, DAM_PDCR(ssi_port)); + __raw_writel(dai_pdcr, DAM_PDCR(dai_port)); +} + +static int imx_3stack_hifi_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + unsigned int channels = params_channels(params); + unsigned int rate = params_rate(params); + struct imx_ssi *ssi_mode = (struct imx_ssi *)cpu_dai->private_data; + int ret = 0; + u32 dai_format; + +#if AK4647_SSI_MASTER + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM; +#else + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS; +#endif + + ssi_mode->sync_mode = 1; + if (channels == 1) + ssi_mode->network_mode = 0; + else + ssi_mode->network_mode = 1; + + /* set codec DAI configuration */ + ret = snd_soc_dai_set_fmt(codec_dai, dai_format); + if (ret < 0) + return ret; + + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, + channels == 1 ? 0xfffffffe : 0xfffffffc, 2); + + /* set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format); + if (ret < 0) + return ret; + + /* set the SSI system clock as input (unused) */ + snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN); + + snd_soc_dai_set_sysclk(codec_dai, 0, rate, 0); + + /* set codec BCLK division for sample rate */ + snd_soc_dai_set_clkdiv(codec_dai, 0, 0); + + return 0; +} + +/* + * imx_3stack ak4647 HiFi DAI operations. + */ +static struct snd_soc_ops imx_3stack_hifi_ops = { + .hw_params = imx_3stack_hifi_hw_params, +}; + +static int ak4647_get_jack(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ak4647_jack_func; + return 0; +} + +static int ak4647_set_jack(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + if (ak4647_jack_func == ucontrol->value.integer.value[0]) + return 0; + + ak4647_jack_func = ucontrol->value.integer.value[0]; + + if (ak4647_jack_func) + snd_soc_dapm_enable_pin(codec, "Headphone Jack"); + else + snd_soc_dapm_disable_pin(codec, "Headphone Jack"); + + snd_soc_dapm_sync(codec); + return 1; +} + +static int ak4647_get_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ak4647_spk_func; + return 0; +} + +static int ak4647_set_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + if (ak4647_spk_func == ucontrol->value.integer.value[0]) + return 0; + + ak4647_spk_func = ucontrol->value.integer.value[0]; + if (ak4647_spk_func) + snd_soc_dapm_enable_pin(codec, "Line Out Jack"); + else + snd_soc_dapm_disable_pin(codec, "Line Out Jack"); + + snd_soc_dapm_sync(codec); + return 1; +} + +static int spk_amp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct imx_3stack_priv *priv = &card_priv; + struct platform_device *pdev = priv->pdev; + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + + if (plat->amp_enable == NULL) + return 0; + + if (SND_SOC_DAPM_EVENT_ON(event)) + plat->amp_enable(1); + else + plat->amp_enable(0); + return 0; +} + +/* imx_3stack card dapm widgets */ +static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = { + SND_SOC_DAPM_MIC("Mic1 Jack", NULL), + SND_SOC_DAPM_LINE("Line In Jack", NULL), + SND_SOC_DAPM_LINE("Line Out Jack", NULL), + SND_SOC_DAPM_SPK("Ext Spk", spk_amp_event), + SND_SOC_DAPM_HP("Headphone Jack", NULL), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* mic is connected to mic1 - with bias */ + {"Left Input", NULL, "Mic1 Jack"}, + + /* Line in jack */ + {"Left Input", NULL, "Line In Jack"}, + {"Right Input", NULL, "Line In Jack"}, + + /* Headphone jack */ + {"Headphone Jack", NULL, "HPL"}, + {"Headphone Jack", NULL, "HPR"}, + + /* Line out jack */ + {"Line Out Jack", NULL, "LOUT"}, + + /* Ext Spk */ + {"Ext Spk", NULL, "LOUT"}, + +}; + +static const char *jack_function[] = { "off", "on" }; + +static const char *spk_function[] = { "off", "on" }; + +static const struct soc_enum ak4647_enum[] = { + SOC_ENUM_SINGLE_EXT(2, jack_function), + SOC_ENUM_SINGLE_EXT(2, spk_function), +}; + +static const struct snd_kcontrol_new ak4647_card_controls[] = { + SOC_ENUM_EXT("Jack Function", ak4647_enum[0], ak4647_get_jack, + ak4647_set_jack), + SOC_ENUM_EXT("Speaker Function", ak4647_enum[1], ak4647_get_spk, + ak4647_set_spk), +}; + +static void headphone_detect_handler(struct work_struct *work) +{ + struct imx_3stack_priv *priv = &card_priv; + struct platform_device *pdev = priv->pdev; + + sysfs_notify(&pdev->dev.kobj, NULL, "headphone"); +} + +static irqreturn_t imx_headphone_detect_handler(int irq, void *dev_id) +{ + schedule_work(&hp_event); + return IRQ_HANDLED; + +} + +static ssize_t show_headphone(struct device_driver *dev, char *buf) +{ + struct imx_3stack_priv *priv = &card_priv; + struct platform_device *pdev = priv->pdev; + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + unsigned int value; + + value = plat->hp_status(); + + if (value == 0) + strcpy(buf, "speaker\n"); + else + strcpy(buf, "headphone\n"); + + return strlen(buf); +} + +DRIVER_ATTR(headphone, S_IRUGO | S_IWUSR, show_headphone, NULL); + +static int imx_3stack_ak4647_init(struct snd_soc_codec *codec) +{ + int i, ret; + for (i = 0; i < ARRAY_SIZE(ak4647_card_controls); i++) { + ret = snd_ctl_add(codec->card, + snd_soc_cnew(&ak4647_card_controls[i], + codec, NULL)); + if (ret < 0) + return ret; + } + + snd_soc_dapm_new_controls(codec, imx_3stack_dapm_widgets, + ARRAY_SIZE(imx_3stack_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_sync(codec); + + return 0; +} + +static struct snd_soc_dai_link imx_3stack_dai = { + .name = "ak4647", + .stream_name = "ak4647", + .codec_dai = &ak4647_hifi_dai, + .init = imx_3stack_ak4647_init, + .ops = &imx_3stack_hifi_ops, +}; + +static struct snd_soc_card snd_soc_card_imx_3stack = { + .name = "imx-3stack", + .platform = &imx_soc_platform, + .dai_link = &imx_3stack_dai, + .num_links = 1, +}; + +static struct snd_soc_device imx_3stack_snd_devdata = { + .card = &snd_soc_card_imx_3stack, + .codec_dev = &soc_codec_dev_ak4647, +}; + +/* + * This function will register the snd_soc_pcm_link drivers. + * It also registers devices for platform DMA, I2S, SSP and registers an + * I2C driver to probe the codec. + */ +static int __init imx_3stack_ak4647_probe(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *dev_data = pdev->dev.platform_data; + struct imx_3stack_priv *priv = &card_priv; + struct snd_soc_dai *ak4647_cpu_dai; + int ret = 0; + + dev_data->init(); + + if (dev_data->src_port == 1) + ak4647_cpu_dai = imx_ssi_dai[0]; + else + ak4647_cpu_dai = imx_ssi_dai[2]; + + imx_3stack_dai.cpu_dai = ak4647_cpu_dai; + + imx_3stack_init_dam(dev_data->src_port, dev_data->ext_port); + + ret = request_irq(dev_data->intr_id_hp, imx_headphone_detect_handler, 0, + "headphone", NULL); + if (ret < 0) + goto err; + + ret = driver_create_file(pdev->dev.driver, &driver_attr_headphone); + if (ret < 0) + goto sysfs_err; + + priv->pdev = pdev; + return ret; + +sysfs_err: + free_irq(dev_data->intr_id_hp, NULL); +err: + return ret; +} + +static int __devexit imx_3stack_ak4647_remove(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *dev_data = pdev->dev.platform_data; + free_irq(dev_data->intr_id_hp, NULL); + driver_remove_file(pdev->dev.driver, &driver_attr_headphone); + return 0; +} + +static struct platform_driver imx_3stack_ak4647_driver = { + .probe = imx_3stack_ak4647_probe, + .remove = __devexit_p(imx_3stack_ak4647_remove), + .driver = { + .name = "imx-3stack-ak4647", + .owner = THIS_MODULE, + }, +}; + +static struct platform_device *imx_3stack_snd_device; + +static int __init imx_3stack_asoc_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_3stack_ak4647_driver); + if (ret < 0) + goto exit; + + if (snd_soc_card_imx_3stack.codec == NULL) { + ret = -ENOMEM; + goto err_device_alloc; + } + + imx_3stack_snd_device = platform_device_alloc("soc-audio", 3); + if (!imx_3stack_snd_device) + goto err_device_alloc; + platform_set_drvdata(imx_3stack_snd_device, &imx_3stack_snd_devdata); + imx_3stack_snd_devdata.dev = &imx_3stack_snd_device->dev; + ret = platform_device_add(imx_3stack_snd_device); + if (0 == ret) + goto exit; + + platform_device_put(imx_3stack_snd_device); +err_device_alloc: + platform_driver_unregister(&imx_3stack_ak4647_driver); +exit: + return ret; +} + +static void __exit imx_3stack_asoc_exit(void) +{ + platform_driver_unregister(&imx_3stack_ak4647_driver); + platform_device_unregister(imx_3stack_snd_device); +} + +module_init(imx_3stack_asoc_init); +module_exit(imx_3stack_asoc_exit); + +/* Module information */ +MODULE_DESCRIPTION("ALSA SoC ak4647 imx_3stack"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-3stack-ak5702.c b/sound/soc/imx/imx-3stack-ak5702.c new file mode 100644 index 000000000000..d90252b729fd --- /dev/null +++ b/sound/soc/imx/imx-3stack-ak5702.c @@ -0,0 +1,226 @@ +/* + * imx-3stack-ak5702.c -- SoC audio for imx_3stack + * + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "imx-pcm.h" +#include "imx-esai.h" +#include "../codecs/ak5702.h" + +struct imx_3stack_pcm_state { + int lr_clk_active; +}; + +static struct imx_3stack_pcm_state clk_state; + +static int imx_3stack_startup(struct snd_pcm_substream *substream) +{ + clk_state.lr_clk_active++; + return 0; +} + +static void imx_3stack_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + + /* disable the PLL if there are no active Rx channels */ + if (!codec_dai->active) + snd_soc_dai_set_pll(codec_dai, 0, 0, 0, 0); + clk_state.lr_clk_active--; +} + +static int imx_3stack_surround_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + unsigned int rate = params_rate(params); + struct imx_esai *esai_mode = (struct imx_esai *)cpu_dai->private_data; + u32 dai_format; + + if (clk_state.lr_clk_active > 1) + return 0; + + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM; + + esai_mode->sync_mode = 0; + esai_mode->network_mode = 1; + + /* set codec DAI configuration */ + snd_soc_dai_set_fmt(codec_dai, dai_format); + + /* set cpu DAI configuration */ + snd_soc_dai_set_fmt(cpu_dai, dai_format); + + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffff, 0xffffffff, 2, 0); + + /* set the ESAI system clock as input */ + snd_soc_dai_set_sysclk(cpu_dai, 0, 0, SND_SOC_CLOCK_IN); + + /* set codec BCLK division */ + snd_soc_dai_set_clkdiv(codec_dai, AK5702_BCLK_CLKDIV, + AK5702_BCLK_DIV_32); + + snd_soc_dai_set_sysclk(codec_dai, 0, rate, SND_SOC_CLOCK_OUT); + + snd_soc_dai_set_pll(codec_dai, 1, 0, 12000000, 0); + return 0; +} + +/* + * imx_3stack ak5702 DAI opserations. + */ +static struct snd_soc_ops imx_3stack_surround_ops = { + .startup = imx_3stack_startup, + .shutdown = imx_3stack_shutdown, + .hw_params = imx_3stack_surround_hw_params, +}; + +/* imx_3stack card dapm widgets */ +static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = { + SND_SOC_DAPM_LINE("Line In Jack", NULL), +}; + +/* example card audio map */ +static const struct snd_soc_dapm_route audio_map[] = { + /* Line in jack */ + {"ADCA Left Input", NULL, "Line In Jack"}, + {"ADCA Right Input", NULL, "Line In Jack"}, + {"ADCB Left Input", NULL, "Line In Jack"}, + {"ADCB Right Input", NULL, "Line In Jack"}, +}; + +static int imx_3stack_ak5702_init(struct snd_soc_codec *codec) +{ + snd_soc_dapm_new_controls(codec, imx_3stack_dapm_widgets, + ARRAY_SIZE(imx_3stack_dapm_widgets)); + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + snd_soc_dapm_sync(codec); + return 0; +} + +static struct snd_soc_dai_link imx_3stack_dai = { + .name = "ak5702", + .stream_name = "ak5702", + .codec_dai = &ak5702_dai, + .init = imx_3stack_ak5702_init, + .ops = &imx_3stack_surround_ops, +}; + +static int imx_3stack_card_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + + kfree(socdev->codec_data); + return 0; +} + +static struct snd_soc_card snd_soc_card_imx_3stack = { + .name = "imx-3stack", + .platform = &imx_soc_platform, + .dai_link = &imx_3stack_dai, + .num_links = 1, + .remove = imx_3stack_card_remove, +}; + +static struct snd_soc_device imx_3stack_snd_devdata = { + .card = &snd_soc_card_imx_3stack, + .codec_dev = &soc_codec_dev_ak5702, +}; + +static int __devinit imx_3stack_ak5702_probe(struct platform_device *pdev) +{ + struct ak5702_setup_data *setup; + + imx_3stack_dai.cpu_dai = &imx_esai_dai[2]; + + setup = kzalloc(sizeof(struct ak5702_setup_data), GFP_KERNEL); + setup->i2c_bus = 1; + setup->i2c_address = 0x13; + imx_3stack_snd_devdata.codec_data = setup; + + return 0; +} + +static int imx_3stack_ak5702_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver imx_3stack_ak5702_driver = { + .probe = imx_3stack_ak5702_probe, + .remove = imx_3stack_ak5702_remove, + .driver = { + .name = "imx-3stack-ak5702", + }, +}; + +static struct platform_device *imx_3stack_snd_device; + +static int __init imx_3stack_asoc_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_3stack_ak5702_driver); + if (ret) + return -ENOMEM; + + imx_3stack_snd_device = platform_device_alloc("soc-audio", -1); + if (!imx_3stack_snd_device) + return -ENOMEM; + + platform_set_drvdata(imx_3stack_snd_device, &imx_3stack_snd_devdata); + imx_3stack_snd_devdata.dev = &imx_3stack_snd_device->dev; + ret = platform_device_add(imx_3stack_snd_device); + if (ret) + platform_device_put(imx_3stack_snd_device); + + return ret; +} + +static void __exit imx_3stack_asoc_exit(void) +{ + platform_driver_unregister(&imx_3stack_ak5702_driver); + platform_device_unregister(imx_3stack_snd_device); +} + +module_init(imx_3stack_asoc_init); +module_exit(imx_3stack_asoc_exit); + +/* Module information */ +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("ALSA SoC ak5702 imx_3stack"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-3stack-bt.c b/sound/soc/imx/imx-3stack-bt.c new file mode 100644 index 000000000000..4b6e36b629e6 --- /dev/null +++ b/sound/soc/imx/imx-3stack-bt.c @@ -0,0 +1,256 @@ +/* + * imx-3stack-bt.c -- SoC bluetooth audio for imx_3stack + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-pcm.h" +#include "imx-ssi.h" +#include "imx-3stack-bt.h" + +#define BT_SSI_MASTER 1 + +struct imx_3stack_priv { + struct platform_device *pdev; + int active; +}; + +static struct imx_3stack_priv card_priv; + +static void imx_3stack_init_dam(int ssi_port, int dai_port) +{ + /* bt uses SSI1 or SSI2 via AUDMUX port dai_port for audio */ + unsigned int ssi_ptcr = 0; + unsigned int dai_ptcr = 0; + unsigned int ssi_pdcr = 0; + unsigned int dai_pdcr = 0; + + /* reset port ssi_port & dai_port */ + __raw_writel(0, DAM_PTCR(ssi_port)); + __raw_writel(0, DAM_PTCR(dai_port)); + __raw_writel(0, DAM_PDCR(ssi_port)); + __raw_writel(0, DAM_PDCR(dai_port)); + + /* set to synchronous */ + ssi_ptcr |= AUDMUX_PTCR_SYN; + dai_ptcr |= AUDMUX_PTCR_SYN; + +#if BT_SSI_MASTER + /* set Rx sources ssi_port <--> dai_port */ + ssi_pdcr |= AUDMUX_PDCR_RXDSEL(dai_port); + dai_pdcr |= AUDMUX_PDCR_RXDSEL(ssi_port); + + /* set Tx frame direction and source dai_port--> ssi_port output */ + ssi_ptcr |= AUDMUX_PTCR_TFSDIR; + ssi_ptcr |= AUDMUX_PTCR_TFSSEL(AUDMUX_FROM_TXFS, dai_port); + + /* set Tx Clock direction and source dai_port--> ssi_port output */ + ssi_ptcr |= AUDMUX_PTCR_TCLKDIR; + ssi_ptcr |= AUDMUX_PTCR_TCSEL(AUDMUX_FROM_TXFS, dai_port); +#else + /* set Rx sources ssi_port <--> dai_port */ + ssi_pdcr |= AUDMUX_PDCR_RXDSEL(dai_port); + dai_pdcr |= AUDMUX_PDCR_RXDSEL(ssi_port); + + /* set Tx frame direction and source ssi_port --> dai_port output */ + dai_ptcr |= AUDMUX_PTCR_TFSDIR; + dai_ptcr |= AUDMUX_PTCR_TFSSEL(AUDMUX_FROM_TXFS, ssi_port); + + /* set Tx Clock direction and source ssi_port--> dai_port output */ + dai_ptcr |= AUDMUX_PTCR_TCLKDIR; + dai_ptcr |= AUDMUX_PTCR_TCSEL(AUDMUX_FROM_TXFS, ssi_port); +#endif + + __raw_writel(ssi_ptcr, DAM_PTCR(ssi_port)); + __raw_writel(dai_ptcr, DAM_PTCR(dai_port)); + __raw_writel(ssi_pdcr, DAM_PDCR(ssi_port)); + __raw_writel(dai_pdcr, DAM_PDCR(dai_port)); +} + +static int imx_3stack_bt_startup(struct snd_pcm_substream *substream) +{ + struct imx_3stack_priv *priv = &card_priv; + + if (!priv->active) + gpio_activate_bt_audio_port(); + priv->active++; + return 0; +} + +static int imx_3stack_bt_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + unsigned int channels = params_channels(params); + struct imx_ssi *ssi_mode = (struct imx_ssi *)cpu_dai->private_data; + int ret = 0; + u32 dai_format; + +#if BT_SSI_MASTER + dai_format = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_IB_IF | + SND_SOC_DAIFMT_CBM_CFM; +#else + dai_format = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_IB_IF | + SND_SOC_DAIFMT_CBS_CFS; +#endif + + ssi_mode->sync_mode = 1; + if (channels == 1) + ssi_mode->network_mode = 0; + else + ssi_mode->network_mode = 1; + + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, + channels == 1 ? 0xfffffffe : 0xfffffffc, 2); + + /* set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format); + if (ret < 0) + return ret; + + /* set the SSI system clock as input (unused) */ + snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN); + + return 0; +} + +static void imx_3stack_bt_shutdown(struct snd_pcm_substream *substream) +{ + struct imx_3stack_priv *priv = &card_priv; + + priv->active--; + if (!priv->active) + gpio_inactivate_bt_audio_port(); +} + +/* + * imx_3stack bt DAI opserations. + */ +static struct snd_soc_ops imx_3stack_bt_ops = { + .startup = imx_3stack_bt_startup, + .hw_params = imx_3stack_bt_hw_params, + .shutdown = imx_3stack_bt_shutdown, +}; + +static struct snd_soc_dai_link imx_3stack_dai = { + .name = "bluetooth", + .stream_name = "bluetooth", + .codec_dai = &bt_dai, + .ops = &imx_3stack_bt_ops, +}; + +static struct snd_soc_card snd_soc_card_imx_3stack = { + .name = "imx-3stack", + .platform = &imx_soc_platform, + .dai_link = &imx_3stack_dai, + .num_links = 1, +}; + +static struct snd_soc_device imx_3stack_snd_devdata = { + .card = &snd_soc_card_imx_3stack, + .codec_dev = &soc_codec_dev_bt, +}; + +/* + * This function will register the snd_soc_pcm_link drivers. + * It also registers devices for platform DMA, I2S, SSP and registers an + * I2C driver to probe the codec. + */ +static int __init imx_3stack_bt_probe(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *dev_data = pdev->dev.platform_data; + struct imx_3stack_priv *priv = &card_priv; + struct snd_soc_dai *bt_cpu_dai; + + if (dev_data->src_port == 1) + bt_cpu_dai = imx_ssi_dai[0]; + else + bt_cpu_dai = imx_ssi_dai[2]; + + bt_cpu_dai->dev = &pdev->dev; + imx_3stack_dai.cpu_dai = bt_cpu_dai; + + /* Configure audio port */ + imx_3stack_init_dam(dev_data->src_port, dev_data->ext_port); + + priv->pdev = pdev; + priv->active = 0; + return 0; + +} + +static int __devexit imx_3stack_bt_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver imx_3stack_bt_driver = { + .probe = imx_3stack_bt_probe, + .remove = __devexit_p(imx_3stack_bt_remove), + .driver = { + .name = "imx-3stack-bt", + .owner = THIS_MODULE, + }, +}; + +static struct platform_device *imx_3stack_snd_device; + +static int __init imx_3stack_asoc_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_3stack_bt_driver); + if (ret < 0) + goto exit; + imx_3stack_snd_device = platform_device_alloc("soc-audio", 4); + if (!imx_3stack_snd_device) + goto err_device_alloc; + platform_set_drvdata(imx_3stack_snd_device, &imx_3stack_snd_devdata); + imx_3stack_snd_devdata.dev = &imx_3stack_snd_device->dev; + ret = platform_device_add(imx_3stack_snd_device); + if (0 == ret) + goto exit; + + platform_device_put(imx_3stack_snd_device); +err_device_alloc: + platform_driver_unregister(&imx_3stack_bt_driver); +exit: + return ret; +} + +static void __exit imx_3stack_asoc_exit(void) +{ + platform_driver_unregister(&imx_3stack_bt_driver); + platform_device_unregister(imx_3stack_snd_device); +} + +module_init(imx_3stack_asoc_init); +module_exit(imx_3stack_asoc_exit); + +/* Module information */ +MODULE_DESCRIPTION("ALSA SoC bluetooth imx_3stack"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-3stack-bt.h b/sound/soc/imx/imx-3stack-bt.h new file mode 100644 index 000000000000..50ff66bd738e --- /dev/null +++ b/sound/soc/imx/imx-3stack-bt.h @@ -0,0 +1,21 @@ +/* + * imx-3stack-bt.h -- Bluetooth PCM driver header file for Freescale IMX + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _MXC_BTPCM_H +#define _MXC_BTPCM_H + +extern struct snd_soc_dai bt_dai; +extern struct snd_soc_codec_device soc_codec_dev_bt; +#endif diff --git a/sound/soc/imx/imx-3stack-cs42888.c b/sound/soc/imx/imx-3stack-cs42888.c new file mode 100644 index 000000000000..4d91be6effca --- /dev/null +++ b/sound/soc/imx/imx-3stack-cs42888.c @@ -0,0 +1,428 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "imx-pcm.h" +#include "imx-esai.h" +#include "../codecs/cs42888.h" + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +#include +#endif + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +static unsigned int asrc_rates[] = { + 0, + 8000, + 11025, + 16000, + 22050, + 32000, + 44100, + 48000, + 64000, + 88200, + 96000, + 176400, + 192000, +}; + +struct asrc_esai { + unsigned int cpu_dai_rates; + unsigned int codec_dai_rates; + enum asrc_pair_index asrc_index; + unsigned int output_sample_rate; +}; + +static struct asrc_esai asrc_esai_data; + +#endif + +struct imx_3stack_pcm_state { + int lr_clk_active; +}; + +static struct imx_3stack_pcm_state clk_state; +unsigned int mclk_freq; + +static int imx_3stack_startup(struct snd_pcm_substream *substream) +{ + clk_state.lr_clk_active++; +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (asrc_esai_data.output_sample_rate >= 32000) { + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + asrc_esai_data.cpu_dai_rates = cpu_dai->playback.rates; + asrc_esai_data.codec_dai_rates = codec_dai->playback.rates; + cpu_dai->playback.rates = + SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT; + codec_dai->playback.rates = + SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT; + } +#endif + + return 0; +} + +static void imx_3stack_shutdown(struct snd_pcm_substream *substream) +{ +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + + if (asrc_esai_data.output_sample_rate >= 32000) { + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + codec_dai->playback.rates = asrc_esai_data.codec_dai_rates; + cpu_dai->playback.rates = asrc_esai_data.cpu_dai_rates; + asrc_release_pair(asrc_esai_data.asrc_index); + } +#endif + + clk_state.lr_clk_active--; +} + +static int imx_3stack_surround_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + unsigned int rate = params_rate(params); + u32 dai_format; + unsigned int lrclk_ratio = 0; +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + unsigned int channel = params_channels(params); +#endif + struct imx_esai *esai_mode = (struct imx_esai *)cpu_dai->private_data; + if (clk_state.lr_clk_active > 1) + return 0; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (asrc_esai_data.output_sample_rate >= 32000) { + unsigned int asrc_input_rate = rate; + struct mxc_runtime_data *pcm_data = + substream->runtime->private_data; + struct asrc_config config; + int retVal = 0;; + + retVal = asrc_req_pair(channel, &asrc_esai_data.asrc_index); + if (retVal < 0) { + pr_err("Fail to request asrc pair\n"); + return -1; + } + + config.pair = asrc_esai_data.asrc_index; + config.channel_num = channel; + config.input_sample_rate = asrc_input_rate; + config.output_sample_rate = asrc_esai_data.output_sample_rate; + config.inclk = INCLK_NONE; + config.word_width = 32; + config.outclk = OUTCLK_ESAI_TX; + retVal = asrc_config_pair(&config); + if (retVal < 0) { + pr_err("Fail to config asrc\n"); + asrc_release_pair(asrc_esai_data.asrc_index); + return retVal; + } + rate = asrc_esai_data.output_sample_rate; + pcm_data->asrc_index = asrc_esai_data.asrc_index; + pcm_data->asrc_enable = 1; + } +#endif + + switch (rate) { + case 32000: + lrclk_ratio = 3; + break; + case 48000: + lrclk_ratio = 3; + break; + case 64000: + lrclk_ratio = 1; + break; + case 96000: + lrclk_ratio = 1; + break; + case 128000: + lrclk_ratio = 1; + break; + case 44100: + lrclk_ratio = 3; + break; + case 88200: + lrclk_ratio = 1; + break; + case 176400: + lrclk_ratio = 0; + break; + case 192000: + lrclk_ratio = 0; + break; + default: + pr_info("Rate not support.\n"); + return -EINVAL;; + } + + dai_format = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS; + + esai_mode->sync_mode = 0; + esai_mode->network_mode = 1; + + /* set cpu DAI configuration */ + snd_soc_dai_set_fmt(cpu_dai, dai_format); + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 2, 32); + /* set the ESAI system clock as output */ + snd_soc_dai_set_sysclk(cpu_dai, ESAI_CLK_EXTAL, + mclk_freq, SND_SOC_CLOCK_OUT); + /* set the ratio */ + snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PSR, 1); + snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PM, 0); + snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_FP, lrclk_ratio); + snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PSR, 1); + snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PM, 0); + snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_FP, lrclk_ratio); + + /* set codec DAI configuration */ + snd_soc_dai_set_fmt(codec_dai, dai_format); + /* set codec Master clock */ + snd_soc_dai_set_sysclk(codec_dai, 0, mclk_freq, SND_SOC_CLOCK_IN); + + return 0; +} + +static struct snd_soc_ops imx_3stack_surround_ops = { + .startup = imx_3stack_startup, + .shutdown = imx_3stack_shutdown, + .hw_params = imx_3stack_surround_hw_params, +}; + +static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = { + SND_SOC_DAPM_LINE("Line Out Jack", NULL), + SND_SOC_DAPM_LINE("Line In Jack", NULL), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Line out jack */ + {"Line Out Jack", NULL, "AOUT1L"}, + {"Line Out Jack", NULL, "AOUT1R"}, + {"Line Out Jack", NULL, "AOUT2L"}, + {"Line Out Jack", NULL, "AOUT2R"}, + {"Line Out Jack", NULL, "AOUT3L"}, + {"Line Out Jack", NULL, "AOUT3R"}, + {"Line Out Jack", NULL, "AOUT4L"}, + {"Line Out Jack", NULL, "AOUT4R"}, + {"AIN1L", NULL, "Line In Jack"}, + {"AIN1R", NULL, "Line In Jack"}, + {"AIN2L", NULL, "Line In Jack"}, + {"AIN2R", NULL, "Line In Jack"}, +}; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +static int asrc_func; + +static const char *asrc_function[] = { + "disable", "32KHz", "44.1KHz", + "48KHz", "64KHz", "88.2KHz", "96KHz", "176.4KHz", "192KHz" +}; + +static const struct soc_enum asrc_enum[] = { + SOC_ENUM_SINGLE_EXT(9, asrc_function), +}; + +static int asrc_get_rate(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = asrc_func; + return 0; +} + +static int asrc_set_rate(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + if (asrc_func == ucontrol->value.enumerated.item[0]) + return 0; + + asrc_func = ucontrol->value.enumerated.item[0]; + asrc_esai_data.output_sample_rate = asrc_rates[asrc_func + 4]; + + return 1; +} + +static const struct snd_kcontrol_new asrc_controls[] = { + SOC_ENUM_EXT("ASRC", asrc_enum[0], asrc_get_rate, + asrc_set_rate), +}; + +#endif + +static int imx_3stack_cs42888_init(struct snd_soc_codec *codec) +{ + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + int i; + int ret; + for (i = 0; i < ARRAY_SIZE(asrc_controls); i++) { + ret = snd_ctl_add(codec->card, + snd_soc_cnew(&asrc_controls[i], codec, NULL)); + if (ret < 0) + return ret; + } + asrc_esai_data.output_sample_rate = asrc_rates[asrc_func + 4]; +#endif + + snd_soc_dapm_new_controls(codec, imx_3stack_dapm_widgets, + ARRAY_SIZE(imx_3stack_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_sync(codec); + + return 0; +} + +static struct snd_soc_dai_link imx_3stack_dai = { + .name = "cs42888", + .stream_name = "cs42888", + .codec_dai = &cs42888_dai, + .init = imx_3stack_cs42888_init, + .ops = &imx_3stack_surround_ops, +}; + +static int imx_3stack_card_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + kfree(socdev->codec_data); + return 0; +} + +static struct snd_soc_card snd_soc_card_imx_3stack = { + .name = "imx-3stack", + .platform = &imx_soc_platform, + .dai_link = &imx_3stack_dai, + .num_links = 1, + .remove = imx_3stack_card_remove, +}; + +static struct snd_soc_device imx_3stack_snd_devdata = { + .card = &snd_soc_card_imx_3stack, + .codec_dev = &soc_codec_device_cs42888, +}; + +/* + * This function will register the snd_soc_pcm_link drivers. + */ +static int __devinit imx_3stack_cs42888_probe(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat_data = pdev->dev.platform_data; + imx_3stack_dai.cpu_dai = &imx_esai_dai[2]; + imx_3stack_dai.cpu_dai->dev = &pdev->dev; + mclk_freq = plat_data->sysclk; + if (!(mclk_freq % 44100)) { + imx_3stack_dai.codec_dai->playback.rates = + SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_176400; + imx_3stack_dai.codec_dai->capture.rates = + SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_88200 |\ + SNDRV_PCM_RATE_176400; + } + if (!(mclk_freq % 48000)) { + imx_3stack_dai.codec_dai->playback.rates = + SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_192000; + imx_3stack_dai.codec_dai->capture.rates = + SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_96000 |\ + SNDRV_PCM_RATE_192000; + } + + return 0; +} + +static int __devexit imx_3stack_cs42888_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver imx_3stack_cs42888_driver = { + .probe = imx_3stack_cs42888_probe, + .remove = __devexit_p(imx_3stack_cs42888_remove), + .driver = { + .name = "imx-3stack-cs42888", + .owner = THIS_MODULE, + }, +}; + +static struct platform_device *imx_3stack_snd_device; + +static int __init imx_3stack_asoc_init(void) +{ + int ret; + ret = platform_driver_register(&imx_3stack_cs42888_driver); + if (ret < 0) + goto exit; + + imx_3stack_snd_device = platform_device_alloc("soc-audio", 1); + if (!imx_3stack_snd_device) + goto err_device_alloc; + platform_set_drvdata(imx_3stack_snd_device, &imx_3stack_snd_devdata); + imx_3stack_snd_devdata.dev = &imx_3stack_snd_device->dev; + ret = platform_device_add(imx_3stack_snd_device); + if (0 == ret && snd_soc_card_imx_3stack.codec != NULL) + goto exit; + + platform_device_unregister(imx_3stack_snd_device); +err_device_alloc: + platform_driver_unregister(&imx_3stack_cs42888_driver); +exit: + return ret; +} + +static void __exit imx_3stack_asoc_exit(void) +{ + platform_driver_unregister(&imx_3stack_cs42888_driver); + platform_device_unregister(imx_3stack_snd_device); +} + +module_init(imx_3stack_asoc_init); +module_exit(imx_3stack_asoc_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("ALSA SoC cs42888 imx_3stack"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-3stack-sgtl5000.c b/sound/soc/imx/imx-3stack-sgtl5000.c new file mode 100644 index 000000000000..cccc0bda6150 --- /dev/null +++ b/sound/soc/imx/imx-3stack-sgtl5000.c @@ -0,0 +1,706 @@ +/* + * imx-3stack-sgtl5000.c -- i.MX 3Stack Driver for Freescale SGTL5000 Codec + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 21th Oct 2008 Initial version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../codecs/sgtl5000.h" +#include "imx-ssi.h" +#include "imx-pcm.h" + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +#include + +static unsigned int sgtl5000_rates[] = { + 0, + 32000, + 44100, + 48000, + 96000, +}; + +struct asrc_esai { + unsigned int cpu_dai_rates; + unsigned int codec_dai_rates; + enum asrc_pair_index asrc_index; + unsigned int output_sample_rate; +}; + +static struct asrc_esai asrc_ssi_data; +#endif + +/* SSI BCLK and LRC master */ +#define SGTL5000_SSI_MASTER 1 + +struct imx_3stack_priv { + int sysclk; + int hw; + struct platform_device *pdev; +}; + +static struct imx_3stack_priv card_priv; + +static int imx_3stack_audio_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *machine = rtd->dai; + struct snd_soc_dai *cpu_dai = machine->cpu_dai; + struct snd_soc_dai *codec_dai = machine->codec_dai; + struct imx_3stack_priv *priv = &card_priv; + unsigned int rate = params_rate(params); + struct imx_ssi *ssi_mode = (struct imx_ssi *)cpu_dai->private_data; + int ret = 0; + + unsigned int channels = params_channels(params); + u32 dai_format; + + /* only need to do this once as capture and playback are sync */ + if (priv->hw) + return 0; + priv->hw = 1; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if ((asrc_ssi_data.output_sample_rate != 0) + && (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) { + unsigned int asrc_input_rate = rate; + unsigned int channel = params_channels(params); + struct mxc_runtime_data *pcm_data = + substream->runtime->private_data; + struct asrc_config config; + struct mxc_audio_platform_data *plat; + struct imx_3stack_priv *priv = &card_priv; + int retVal = 0; + retVal = asrc_req_pair(channel, &asrc_ssi_data.asrc_index); + if (retVal < 0) { + pr_err("asrc_req_pair fail\n"); + return -1; + } + config.pair = asrc_ssi_data.asrc_index; + config.channel_num = channel; + config.input_sample_rate = asrc_input_rate; + config.output_sample_rate = asrc_ssi_data.output_sample_rate; + config.inclk = INCLK_NONE; + config.word_width = 32; + plat = priv->pdev->dev.platform_data; + if (plat->src_port == 1) + config.outclk = OUTCLK_SSI1_TX; + else + config.outclk = OUTCLK_SSI2_TX; + retVal = asrc_config_pair(&config); + if (retVal < 0) { + pr_err("Fail to config asrc\n"); + asrc_release_pair(asrc_ssi_data.asrc_index); + return retVal; + } + rate = asrc_ssi_data.output_sample_rate; + pcm_data->asrc_index = asrc_ssi_data.asrc_index; + pcm_data->asrc_enable = 1; + } +#endif + + snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, priv->sysclk, 0); + snd_soc_dai_set_sysclk(codec_dai, SGTL5000_LRCLK, rate, 0); + +#if SGTL5000_SSI_MASTER + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM; +#else + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS; +#endif + + ssi_mode->sync_mode = 1; + if (channels == 1) + ssi_mode->network_mode = 0; + else + ssi_mode->network_mode = 1; + + /* set codec DAI configuration */ + ret = snd_soc_dai_set_fmt(codec_dai, dai_format); + if (ret < 0) + return ret; + + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, + channels == 1 ? 0xfffffffe : 0xfffffffc, + channels == 1 ? 0xfffffffe : 0xfffffffc, + 2, 32); + + /* set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format); + if (ret < 0) + return ret; + + /* set the SSI system clock as input (unused) */ + snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN); + + return 0; +} + +static int imx_3stack_startup(struct snd_pcm_substream *substream) +{ +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (asrc_ssi_data.output_sample_rate != 0) { + struct snd_soc_pcm_runtime *rtd = + substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + asrc_ssi_data.cpu_dai_rates = cpu_dai->playback.rates; + asrc_ssi_data.codec_dai_rates = + codec_dai->playback.rates; + cpu_dai->playback.rates = + SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT; + codec_dai->playback.rates = + SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT; + } + } +#endif + return 0; +} + +static void imx_3stack_shutdown(struct snd_pcm_substream *substream) +{ + struct imx_3stack_priv *priv = &card_priv; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (asrc_ssi_data.output_sample_rate != 0) { + struct snd_soc_pcm_runtime *rtd = + substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + codec_dai->playback.rates = + asrc_ssi_data.codec_dai_rates; + cpu_dai->playback.rates = asrc_ssi_data.cpu_dai_rates; + asrc_release_pair(asrc_ssi_data.asrc_index); + } + } +#endif + + priv->hw = 0; +} + +/* + * imx_3stack SGTL5000 audio DAI opserations. + */ +static struct snd_soc_ops imx_3stack_ops = { + .startup = imx_3stack_startup, + .shutdown = imx_3stack_shutdown, + .hw_params = imx_3stack_audio_hw_params, +}; + +static void imx_3stack_init_dam(int ssi_port, int dai_port) +{ + unsigned int ssi_ptcr = 0; + unsigned int dai_ptcr = 0; + unsigned int ssi_pdcr = 0; + unsigned int dai_pdcr = 0; + /* SGTL5000 uses SSI1 or SSI2 via AUDMUX port dai_port for audio */ + + /* reset port ssi_port & dai_port */ + __raw_writel(0, DAM_PTCR(ssi_port)); + __raw_writel(0, DAM_PTCR(dai_port)); + __raw_writel(0, DAM_PDCR(ssi_port)); + __raw_writel(0, DAM_PDCR(dai_port)); + + /* set to synchronous */ + ssi_ptcr |= AUDMUX_PTCR_SYN; + dai_ptcr |= AUDMUX_PTCR_SYN; + +#if SGTL5000_SSI_MASTER + /* set Rx sources ssi_port <--> dai_port */ + ssi_pdcr |= AUDMUX_PDCR_RXDSEL(dai_port); + dai_pdcr |= AUDMUX_PDCR_RXDSEL(ssi_port); + + /* set Tx frame direction and source dai_port--> ssi_port output */ + ssi_ptcr |= AUDMUX_PTCR_TFSDIR; + ssi_ptcr |= AUDMUX_PTCR_TFSSEL(AUDMUX_FROM_TXFS, dai_port); + + /* set Tx Clock direction and source dai_port--> ssi_port output */ + ssi_ptcr |= AUDMUX_PTCR_TCLKDIR; + ssi_ptcr |= AUDMUX_PTCR_TCSEL(AUDMUX_FROM_TXFS, dai_port); +#else + /* set Rx sources ssi_port <--> dai_port */ + ssi_pdcr |= AUDMUX_PDCR_RXDSEL(dai_port); + dai_pdcr |= AUDMUX_PDCR_RXDSEL(ssi_port); + + /* set Tx frame direction and source ssi_port --> dai_port output */ + dai_ptcr |= AUDMUX_PTCR_TFSDIR; + dai_ptcr |= AUDMUX_PTCR_TFSSEL(AUDMUX_FROM_TXFS, ssi_port); + + /* set Tx Clock direction and source ssi_port--> dai_port output */ + dai_ptcr |= AUDMUX_PTCR_TCLKDIR; + dai_ptcr |= AUDMUX_PTCR_TCSEL(AUDMUX_FROM_TXFS, ssi_port); +#endif + + __raw_writel(ssi_ptcr, DAM_PTCR(ssi_port)); + __raw_writel(dai_ptcr, DAM_PTCR(dai_port)); + __raw_writel(ssi_pdcr, DAM_PDCR(ssi_port)); + __raw_writel(dai_pdcr, DAM_PDCR(dai_port)); +} + +/* imx_3stack machine connections to the codec pins */ +static const struct snd_soc_dapm_route audio_map[] = { + + /* Mic Jack --> MIC_IN (with automatic bias) */ + {"MIC_IN", NULL, "Mic Jack"}, + + /* Line in Jack --> LINE_IN */ + {"LINE_IN", NULL, "Line In Jack"}, + + /* HP_OUT --> Headphone Jack */ + {"Headphone Jack", NULL, "HP_OUT"}, + + /* LINE_OUT --> Ext Speaker */ + {"Ext Spk", NULL, "LINE_OUT"}, +}; + +static int sgtl5000_jack_func; +static int sgtl5000_spk_func; +static int sgtl5000_line_in_func; + +static void headphone_detect_handler(struct work_struct *work) +{ + struct imx_3stack_priv *priv = &card_priv; + struct platform_device *pdev = priv->pdev; + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + int hp_status; + + sysfs_notify(&pdev->dev.kobj, NULL, "headphone"); + hp_status = plat->hp_status(); + if (hp_status) + set_irq_type(plat->hp_irq, IRQ_TYPE_EDGE_FALLING); + else + set_irq_type(plat->hp_irq, IRQ_TYPE_EDGE_RISING); + enable_irq(plat->hp_irq); +} + +static DECLARE_DELAYED_WORK(hp_event, headphone_detect_handler); + +static irqreturn_t imx_headphone_detect_handler(int irq, void *data) +{ + disable_irq_nosync(irq); + schedule_delayed_work(&hp_event, msecs_to_jiffies(200)); + return IRQ_HANDLED; +} + +static ssize_t show_headphone(struct device_driver *dev, char *buf) +{ + struct imx_3stack_priv *priv = &card_priv; + struct platform_device *pdev = priv->pdev; + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + u16 hp_status; + + /* determine whether hp is plugged in */ + hp_status = plat->hp_status(); + + if (hp_status == 0) + strcpy(buf, "speaker\n"); + else + strcpy(buf, "headphone\n"); + + return strlen(buf); +} + +static DRIVER_ATTR(headphone, S_IRUGO | S_IWUSR, show_headphone, NULL); + +static const char *jack_function[] = { "off", "on"}; + +static const char *spk_function[] = { "off", "on" }; + +static const char *line_in_function[] = { "off", "on" }; + +static const struct soc_enum sgtl5000_enum[] = { + SOC_ENUM_SINGLE_EXT(2, jack_function), + SOC_ENUM_SINGLE_EXT(2, spk_function), + SOC_ENUM_SINGLE_EXT(2, line_in_function), +}; + +static int sgtl5000_get_jack(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = sgtl5000_jack_func; + return 0; +} + +static int sgtl5000_set_jack(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + + if (sgtl5000_jack_func == ucontrol->value.enumerated.item[0]) + return 0; + + sgtl5000_jack_func = ucontrol->value.enumerated.item[0]; + if (sgtl5000_jack_func) + snd_soc_dapm_enable_pin(codec, "Headphone Jack"); + else + snd_soc_dapm_disable_pin(codec, "Headphone Jack"); + + snd_soc_dapm_sync(codec); + return 1; +} + +static int sgtl5000_get_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = sgtl5000_spk_func; + return 0; +} + +static int sgtl5000_set_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + + if (sgtl5000_spk_func == ucontrol->value.enumerated.item[0]) + return 0; + + sgtl5000_spk_func = ucontrol->value.enumerated.item[0]; + if (sgtl5000_spk_func) + snd_soc_dapm_enable_pin(codec, "Ext Spk"); + else + snd_soc_dapm_disable_pin(codec, "Ext Spk"); + + snd_soc_dapm_sync(codec); + return 1; +} + +static int sgtl5000_get_line_in(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = sgtl5000_line_in_func; + return 0; +} + +static int sgtl5000_set_line_in(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + + if (sgtl5000_line_in_func == ucontrol->value.enumerated.item[0]) + return 0; + + sgtl5000_line_in_func = ucontrol->value.enumerated.item[0]; + if (sgtl5000_line_in_func) + snd_soc_dapm_enable_pin(codec, "Line In Jack"); + else + snd_soc_dapm_disable_pin(codec, "Line In Jack"); + + snd_soc_dapm_sync(codec); + return 1; +} + +static int spk_amp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct imx_3stack_priv *priv = &card_priv; + struct platform_device *pdev = priv->pdev; + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + + if (plat->amp_enable == NULL) + return 0; + + if (SND_SOC_DAPM_EVENT_ON(event)) + plat->amp_enable(1); + else + plat->amp_enable(0); + + return 0; +} + +/* imx_3stack card dapm widgets */ +static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = { + SND_SOC_DAPM_MIC("Mic Jack", NULL), + SND_SOC_DAPM_LINE("Line In Jack", NULL), + SND_SOC_DAPM_SPK("Ext Spk", spk_amp_event), + SND_SOC_DAPM_HP("Headphone Jack", NULL), +}; + +static const struct snd_kcontrol_new sgtl5000_machine_controls[] = { + SOC_ENUM_EXT("Jack Function", sgtl5000_enum[0], sgtl5000_get_jack, + sgtl5000_set_jack), + SOC_ENUM_EXT("Speaker Function", sgtl5000_enum[1], sgtl5000_get_spk, + sgtl5000_set_spk), + SOC_ENUM_EXT("Line In Function", sgtl5000_enum[1], sgtl5000_get_line_in, + sgtl5000_set_line_in), +}; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +static int asrc_func; + +static const char *asrc_function[] = { + "disable", "32KHz", "44.1KHz", "48KHz", "96KHz" }; + +static const struct soc_enum asrc_enum[] = { + SOC_ENUM_SINGLE_EXT(5, asrc_function), +}; + +static int asrc_get_rate(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = asrc_func; + return 0; +} + +static int asrc_set_rate(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + if (asrc_func == ucontrol->value.enumerated.item[0]) + return 0; + + asrc_func = ucontrol->value.enumerated.item[0]; + asrc_ssi_data.output_sample_rate = sgtl5000_rates[asrc_func]; + + return 1; +} + +static const struct snd_kcontrol_new asrc_controls[] = { + SOC_ENUM_EXT("ASRC", asrc_enum[0], asrc_get_rate, + asrc_set_rate), +}; +#endif + +static int imx_3stack_sgtl5000_init(struct snd_soc_codec *codec) +{ + int i, ret; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + for (i = 0; i < ARRAY_SIZE(asrc_controls); i++) { + ret = snd_ctl_add(codec->card, + snd_soc_cnew(&asrc_controls[i], codec, NULL)); + if (ret < 0) + return ret; + } + asrc_ssi_data.output_sample_rate = sgtl5000_rates[asrc_func]; +#endif + + /* Add imx_3stack specific controls */ + for (i = 0; i < ARRAY_SIZE(sgtl5000_machine_controls); i++) { + ret = snd_ctl_add(codec->card, + snd_soc_cnew(&sgtl5000_machine_controls[i], + codec, NULL)); + if (ret < 0) + return ret; + } + + /* Add imx_3stack specific widgets */ + snd_soc_dapm_new_controls(codec, imx_3stack_dapm_widgets, + ARRAY_SIZE(imx_3stack_dapm_widgets)); + + /* Set up imx_3stack specific audio path audio_map */ + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_disable_pin(codec, "Line In Jack"); + + snd_soc_dapm_sync(codec); + + return 0; +} + +/* imx_3stack digital audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link imx_3stack_dai = { + .name = "SGTL5000", + .stream_name = "SGTL5000", + .codec_dai = &sgtl5000_dai, + .init = imx_3stack_sgtl5000_init, + .ops = &imx_3stack_ops, +}; + +static int imx_3stack_card_remove(struct platform_device *pdev) +{ + struct imx_3stack_priv *priv = &card_priv; + struct mxc_audio_platform_data *plat; + if (priv->pdev) { + plat = priv->pdev->dev.platform_data; + if (plat->finit) + plat->finit(); + } + + return 0; +} + +static struct snd_soc_card snd_soc_card_imx_3stack = { + .name = "imx-3stack", + .platform = &imx_soc_platform, + .dai_link = &imx_3stack_dai, + .num_links = 1, + .remove = imx_3stack_card_remove, +}; + +static struct snd_soc_device imx_3stack_snd_devdata = { + .card = &snd_soc_card_imx_3stack, + .codec_dev = &soc_codec_dev_sgtl5000, +}; + +static int __devinit imx_3stack_sgtl5000_probe(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + struct imx_3stack_priv *priv = &card_priv; + struct snd_soc_dai *sgtl5000_cpu_dai; + struct sgtl5000_setup_data *setup; + + int ret = 0; + + priv->pdev = pdev; + + gpio_activate_audio_ports(); + imx_3stack_init_dam(plat->src_port, plat->ext_port); + + if (plat->src_port == 2) + sgtl5000_cpu_dai = imx_ssi_dai[2]; + else if (plat->src_port == 1) + sgtl5000_cpu_dai = imx_ssi_dai[0]; + else if (plat->src_port == 7) + sgtl5000_cpu_dai = imx_ssi_dai[4]; + + + imx_3stack_dai.cpu_dai = sgtl5000_cpu_dai; + + ret = driver_create_file(pdev->dev.driver, &driver_attr_headphone); + if (ret < 0) { + pr_err("%s:failed to create driver_attr_headphone\n", __func__); + goto sysfs_err; + } + + ret = -EINVAL; + if (plat->init && plat->init()) + goto err_plat_init; + + priv->sysclk = plat->sysclk; + + /* The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLK + cycles after all power rails have been brought up. After this time + communication can start */ + + if (plat->hp_status()) + ret = request_irq(plat->hp_irq, + imx_headphone_detect_handler, + IRQ_TYPE_EDGE_FALLING, pdev->name, priv); + else + ret = request_irq(plat->hp_irq, + imx_headphone_detect_handler, + IRQ_TYPE_EDGE_RISING, pdev->name, priv); + if (ret < 0) { + pr_err("%s: request irq failed\n", __func__); + goto err_card_reg; + } + + setup = kzalloc(sizeof(struct sgtl5000_setup_data), GFP_KERNEL); + if (!setup) { + pr_err("%s: kzalloc sgtl5000_setup_data failed\n", __func__); + goto err_card_reg; + } + setup->clock_enable = plat->clock_enable; + imx_3stack_snd_devdata.codec_data = setup; + + sgtl5000_jack_func = 1; + sgtl5000_spk_func = 1; + sgtl5000_line_in_func = 0; + + return 0; + +err_card_reg: + if (plat->finit) + plat->finit(); +err_plat_init: + driver_remove_file(pdev->dev.driver, &driver_attr_headphone); +sysfs_err: + return ret; +} + +static int imx_3stack_sgtl5000_remove(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + struct imx_3stack_priv *priv = &card_priv; + + free_irq(plat->hp_irq, priv); + + if (plat->finit) + plat->finit(); + + driver_remove_file(pdev->dev.driver, &driver_attr_headphone); + + return 0; +} + +static struct platform_driver imx_3stack_sgtl5000_audio_driver = { + .probe = imx_3stack_sgtl5000_probe, + .remove = imx_3stack_sgtl5000_remove, + .driver = { + .name = "imx-3stack-sgtl5000", + }, +}; + +static struct platform_device *imx_3stack_snd_device; + +static int __init imx_3stack_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_3stack_sgtl5000_audio_driver); + if (ret) + return -ENOMEM; + + imx_3stack_snd_device = platform_device_alloc("soc-audio", 2); + if (!imx_3stack_snd_device) + return -ENOMEM; + + platform_set_drvdata(imx_3stack_snd_device, &imx_3stack_snd_devdata); + imx_3stack_snd_devdata.dev = &imx_3stack_snd_device->dev; + ret = platform_device_add(imx_3stack_snd_device); + + if (ret) + platform_device_put(imx_3stack_snd_device); + + return ret; +} + +static void __exit imx_3stack_exit(void) +{ + platform_driver_unregister(&imx_3stack_sgtl5000_audio_driver); + platform_device_unregister(imx_3stack_snd_device); +} + +module_init(imx_3stack_init); +module_exit(imx_3stack_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("SGTL5000 Driver for i.MX 3STACK"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-3stack-wm8350.c b/sound/soc/imx/imx-3stack-wm8350.c new file mode 100644 index 000000000000..1cd51d31e128 --- /dev/null +++ b/sound/soc/imx/imx-3stack-wm8350.c @@ -0,0 +1,696 @@ +/* + * imx-3stack-wm8350.c -- i.MX 3Stack Driver for Wolfson WM8350 Codec + * + * Copyright 2007 Wolfson Microelectronics PLC. + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. + * + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 19th Jun 2007 Initial version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../codecs/wm8350.h" +#include "imx-ssi.h" +#include "imx-pcm.h" + +void gpio_activate_audio_ports(void); + +/* SSI BCLK and LRC master */ +#define WM8350_SSI_MASTER 1 + +struct imx_3stack_priv { + int lr_clk_active; + int playback_active; + int capture_active; + struct platform_device *pdev; + struct wm8350 *wm8350; +}; + +static struct imx_3stack_priv machine_priv; + +struct _wm8350_audio { + unsigned int channels; + snd_pcm_format_t format; + unsigned int rate; + unsigned int sysclk; + unsigned int bclkdiv; + unsigned int clkdiv; + unsigned int lr_rate; +}; + +/* in order of power consumption per rate (lowest first) */ +static const struct _wm8350_audio wm8350_audio[] = { + /* 16bit mono modes */ + + {1, SNDRV_PCM_FORMAT_S16_LE, 8000, 12288000, + WM8350_BCLK_DIV_48, WM8350_DACDIV_6, 32,}, + {1, SNDRV_PCM_FORMAT_S16_LE, 16000, 12288000, + WM8350_BCLK_DIV_24, WM8350_DACDIV_6, 32,}, + {1, SNDRV_PCM_FORMAT_S16_LE, 32000, 12288000, + WM8350_BCLK_DIV_12, WM8350_DACDIV_3, 32,}, + {1, SNDRV_PCM_FORMAT_S16_LE, 48000, 12288000, + WM8350_BCLK_DIV_8, WM8350_DACDIV_2, 32,}, + {1, SNDRV_PCM_FORMAT_S16_LE, 96000, 24576000, + WM8350_BCLK_DIV_8, WM8350_DACDIV_2, 32,}, + {1, SNDRV_PCM_FORMAT_S16_LE, 11025, 11289600, + WM8350_BCLK_DIV_32, WM8350_DACDIV_4, 32,}, + {1, SNDRV_PCM_FORMAT_S16_LE, 22050, 11289600, + WM8350_BCLK_DIV_16, WM8350_DACDIV_4, 32,}, + {1, SNDRV_PCM_FORMAT_S16_LE, 44100, 11289600, + WM8350_BCLK_DIV_8, WM8350_DACDIV_2, 32,}, + {1, SNDRV_PCM_FORMAT_S16_LE, 88200, 22579200, + WM8350_BCLK_DIV_8, WM8350_DACDIV_2, 32,}, + + /* 16 bit stereo modes */ + {2, SNDRV_PCM_FORMAT_S16_LE, 8000, 12288000, + WM8350_BCLK_DIV_48, WM8350_DACDIV_6, 32,}, + {2, SNDRV_PCM_FORMAT_S16_LE, 16000, 12288000, + WM8350_BCLK_DIV_24, WM8350_DACDIV_3, 32,}, + {2, SNDRV_PCM_FORMAT_S16_LE, 32000, 12288000, + WM8350_BCLK_DIV_12, WM8350_DACDIV_1_5, 32,}, + {2, SNDRV_PCM_FORMAT_S16_LE, 48000, 12288000, + WM8350_BCLK_DIV_8, WM8350_DACDIV_1, 32,}, + {2, SNDRV_PCM_FORMAT_S16_LE, 96000, 24576000, + WM8350_BCLK_DIV_8, WM8350_DACDIV_1, 32,}, + {2, SNDRV_PCM_FORMAT_S16_LE, 11025, 11289600, + WM8350_BCLK_DIV_32, WM8350_DACDIV_4, 32,}, + {2, SNDRV_PCM_FORMAT_S16_LE, 22050, 11289600, + WM8350_BCLK_DIV_16, WM8350_DACDIV_2, 32,}, + {2, SNDRV_PCM_FORMAT_S16_LE, 44100, 11289600, + WM8350_BCLK_DIV_8, WM8350_DACDIV_1, 32,}, + {2, SNDRV_PCM_FORMAT_S16_LE, 88200, 22579200, + WM8350_BCLK_DIV_8, WM8350_DACDIV_1, 32,}, + + /* 24bit stereo modes */ + {2, SNDRV_PCM_FORMAT_S24_LE, 48000, 12288000, + WM8350_BCLK_DIV_4, WM8350_DACDIV_1, 64,}, + {2, SNDRV_PCM_FORMAT_S24_LE, 96000, 24576000, + WM8350_BCLK_DIV_4, WM8350_DACDIV_1, 64,}, + {2, SNDRV_PCM_FORMAT_S24_LE, 44100, 11289600, + WM8350_BCLK_DIV_4, WM8350_DACDIV_1, 64,}, + {2, SNDRV_PCM_FORMAT_S24_LE, 88200, 22579200, + WM8350_BCLK_DIV_4, WM8350_DACDIV_1, 64,}, +}; + +#if WM8350_SSI_MASTER +static int imx_3stack_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec *codec = rtd->socdev->card->codec; + struct wm8350 *wm8350 = codec->control_data; + struct imx_3stack_priv *priv = &machine_priv; + + /* In master mode the LR clock can come from either the DAC or ADC. + * We use the LR clock from whatever stream is enabled first. + */ + + if (!priv->lr_clk_active) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2, + WM8350_LRC_ADC_SEL); + else + wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2, + WM8350_LRC_ADC_SEL); + } + priv->lr_clk_active++; + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + priv->capture_active = 1; + else + priv->playback_active = 1; + return 0; +} +#else +#define imx_3stack_startup NULL +#endif + +static int imx_3stack_audio_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *machine = rtd->dai; + struct snd_soc_dai *cpu_dai = machine->cpu_dai; + struct snd_soc_dai *codec_dai = machine->codec_dai; + struct imx_3stack_priv *priv = &machine_priv; + int ret = 0; + int i, found = 0; + snd_pcm_format_t format = params_format(params); + unsigned int rate = params_rate(params); + unsigned int channels = params_channels(params); + struct imx_ssi *ssi_mode = (struct imx_ssi *)cpu_dai->private_data; + u32 dai_format; + + /* only need to do this once as capture and playback are sync */ + if (priv->lr_clk_active > 1) + return 0; + + /* find the correct audio parameters */ + for (i = 0; i < ARRAY_SIZE(wm8350_audio); i++) { + if (rate == wm8350_audio[i].rate && + format == wm8350_audio[i].format && + channels == wm8350_audio[i].channels) { + found = 1; + break; + } + } + if (!found) { + printk(KERN_ERR "%s: invalid params\n", __func__); + return -EINVAL; + } + +#if WM8350_SSI_MASTER + /* codec FLL input is 32768 kHz from MCLK */ + snd_soc_dai_set_pll(codec_dai, 0, 32768, wm8350_audio[i].sysclk); +#else + /* codec FLL input is rate from DAC LRC */ + snd_soc_dai_set_pll(codec_dai, 0, rate, wm8350_audio[i].sysclk); +#endif + +#if WM8350_SSI_MASTER + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM; + + ssi_mode->sync_mode = 1; + if (channels == 1) + ssi_mode->network_mode = 0; + else + ssi_mode->network_mode = 1; + + /* set codec DAI configuration */ + ret = snd_soc_dai_set_fmt(codec_dai, dai_format); + if (ret < 0) + return ret; + + /* set cpu DAI configuration */ + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + dai_format &= ~SND_SOC_DAIFMT_INV_MASK; + /* Invert frame to switch mic from right channel to left */ + dai_format |= SND_SOC_DAIFMT_NB_IF; + } + + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, + channels == 1 ? 0xfffffffe : 0xfffffffc, + channels); + + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format); + if (ret < 0) + return ret; + + /* set 32KHZ as the codec system clock for DAC and ADC */ + snd_soc_dai_set_sysclk(codec_dai, WM8350_MCLK_SEL_PLL_32K, + wm8350_audio[i].sysclk, SND_SOC_CLOCK_IN); +#else + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS; + + /* set codec DAI configuration */ + ret = snd_soc_dai_set_fmt(codec_dai, dai_format); + if (ret < 0) + return ret; + + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, + channels == 1 ? 0xfffffffe : 0xfffffffc, + channels); + + /* set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format); + if (ret < 0) + return ret; + + /* set DAC LRC as the codec system clock for DAC and ADC */ + snd_soc_dai_set_sysclk(codec_dai, WM8350_MCLK_SEL_PLL_DAC, + wm8350_audio[i].sysclk, SND_SOC_CLOCK_IN); +#endif + + /* set the SSI system clock as input (unused) */ + snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN); + + /* set codec BCLK division for sample rate */ + snd_soc_dai_set_clkdiv(codec_dai, WM8350_BCLK_CLKDIV, + wm8350_audio[i].bclkdiv); + + /* DAI is synchronous and clocked with DAC LRCLK & ADC LRC */ + snd_soc_dai_set_clkdiv(codec_dai, + WM8350_DACLR_CLKDIV, + wm8350_audio[i].lr_rate); + snd_soc_dai_set_clkdiv(codec_dai, + WM8350_ADCLR_CLKDIV, + wm8350_audio[i].lr_rate); + + /* now configure DAC and ADC clocks */ + snd_soc_dai_set_clkdiv(codec_dai, + WM8350_DAC_CLKDIV, wm8350_audio[i].clkdiv); + + snd_soc_dai_set_clkdiv(codec_dai, + WM8350_ADC_CLKDIV, wm8350_audio[i].clkdiv); + + return 0; +} + +static void imx_3stack_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec *codec = rtd->socdev->card->codec; + struct snd_soc_dai_link *machine = rtd->dai; + struct snd_soc_dai *codec_dai = machine->codec_dai; + struct imx_3stack_priv *priv = &machine_priv; + struct wm8350 *wm8350 = codec->control_data; + + /* disable the PLL if there are no active Tx or Rx channels */ + if (!codec_dai->active) + snd_soc_dai_set_pll(codec_dai, 0, 0, 0); + priv->lr_clk_active--; + + /* + * We need to keep track of active streams in master mode and + * switch LRC source if necessary. + */ + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + priv->capture_active = 0; + else + priv->playback_active = 0; + + if (priv->capture_active) + wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2, + WM8350_LRC_ADC_SEL); + else if (priv->playback_active) + wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2, + WM8350_LRC_ADC_SEL); +} + +/* + * imx_3stack WM8350 HiFi DAI operations. + */ +static struct snd_soc_ops imx_3stack_ops = { + .startup = imx_3stack_startup, + .shutdown = imx_3stack_shutdown, + .hw_params = imx_3stack_audio_hw_params, +}; + +static void imx_3stack_init_dam(int ssi_port, int dai_port) +{ + unsigned int ssi_ptcr = 0; + unsigned int dai_ptcr = 0; + unsigned int ssi_pdcr = 0; + unsigned int dai_pdcr = 0; + /* WM8350 uses SSI1 or SSI2 via AUDMUX port dai_port for audio */ + + /* reset port ssi_port & dai_port */ + __raw_writel(0, DAM_PTCR(ssi_port)); + __raw_writel(0, DAM_PTCR(dai_port)); + __raw_writel(0, DAM_PDCR(ssi_port)); + __raw_writel(0, DAM_PDCR(dai_port)); + + /* set to synchronous */ + ssi_ptcr |= AUDMUX_PTCR_SYN; + dai_ptcr |= AUDMUX_PTCR_SYN; + +#if WM8350_SSI_MASTER + /* set Rx sources ssi_port <--> dai_port */ + ssi_pdcr |= AUDMUX_PDCR_RXDSEL(dai_port); + dai_pdcr |= AUDMUX_PDCR_RXDSEL(ssi_port); + + /* set Tx frame direction and source dai_port--> ssi_port output */ + ssi_ptcr |= AUDMUX_PTCR_TFSDIR; + ssi_ptcr |= AUDMUX_PTCR_TFSSEL(AUDMUX_FROM_TXFS, dai_port); + + /* set Tx Clock direction and source dai_port--> ssi_port output */ + ssi_ptcr |= AUDMUX_PTCR_TCLKDIR; + ssi_ptcr |= AUDMUX_PTCR_TCSEL(AUDMUX_FROM_TXFS, dai_port); +#else + /* set Rx sources ssi_port <--> dai_port */ + ssi_pdcr |= AUDMUX_PDCR_RXDSEL(dai_port); + dai_pdcr |= AUDMUX_PDCR_RXDSEL(ssi_port); + + /* set Tx frame direction and source ssi_port --> dai_port output */ + dai_ptcr |= AUDMUX_PTCR_TFSDIR; + dai_ptcr |= AUDMUX_PTCR_TFSSEL(AUDMUX_FROM_TXFS, ssi_port); + + /* set Tx Clock direction and source ssi_port--> dai_port output */ + dai_ptcr |= AUDMUX_PTCR_TCLKDIR; + dai_ptcr |= AUDMUX_PTCR_TCSEL(AUDMUX_FROM_TXFS, ssi_port); +#endif + + __raw_writel(ssi_ptcr, DAM_PTCR(ssi_port)); + __raw_writel(dai_ptcr, DAM_PTCR(dai_port)); + __raw_writel(ssi_pdcr, DAM_PDCR(ssi_port)); + __raw_writel(dai_pdcr, DAM_PDCR(dai_port)); +} + +static const struct snd_soc_dapm_route audio_map[] = { + /* SiMIC --> IN1LN (with automatic bias) via SP1 */ + {"IN1RP", NULL, "Mic Bias"}, + {"Mic Bias", NULL, "SiMIC"}, + + /* Mic 1 Jack --> IN1LN and IN1LP (with automatic bias) */ + {"IN1LN", NULL, "Mic Bias"}, + {"IN1LP", NULL, "Mic1 Jack"}, + {"Mic Bias", NULL, "Mic1 Jack"}, + + /* Mic 2 Jack --> IN1RN and IN1RP (with automatic bias) */ + {"IN1RN", NULL, "Mic2 Jack"}, + {"IN1RP", NULL, "Mic Bias"}, + {"Mic Bias", NULL, "Mic2 Jack"}, + + /* Line in Jack --> AUX (L+R) */ + {"IN3R", NULL, "Line In Jack"}, + {"IN3L", NULL, "Line In Jack"}, + + /* Out1 --> Headphone Jack */ + {"Headphone Jack", NULL, "OUT1R"}, + {"Headphone Jack", NULL, "OUT1L"}, + + /* Out1 --> Line Out Jack */ + {"Line Out Jack", NULL, "OUT2R"}, + {"Line Out Jack", NULL, "OUT2L"}, +}; + +static int wm8350_jack_func; +static int wm8350_spk_func; + +static void headphone_detect_handler(struct work_struct *work) +{ + struct imx_3stack_priv *priv = &machine_priv; + struct platform_device *pdev = priv->pdev; + struct wm8350 *wm8350 = priv->wm8350; + + sysfs_notify(&pdev->dev.kobj, NULL, "headphone"); + wm8350_unmask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); +} + +static DECLARE_DELAYED_WORK(hp_event, headphone_detect_handler); + +static void imx_3stack_jack_handler(struct wm8350 *wm8350, int irq, void *data) +{ + wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + schedule_delayed_work(&hp_event, msecs_to_jiffies(200)); +} + +static ssize_t show_headphone(struct device_driver *dev, char *buf) +{ + struct imx_3stack_priv *priv = &machine_priv; + u16 reg; + + reg = wm8350_reg_read(priv->wm8350, WM8350_JACK_PIN_STATUS); + + if (reg & WM8350_JACK_R_LVL) + strcpy(buf, "speaker\n"); + else + strcpy(buf, "headphone\n"); + + return strlen(buf); +} + +static DRIVER_ATTR(headphone, S_IRUGO | S_IWUSR, show_headphone, NULL); + +static const char *jack_function[] = { "off", "on" +}; + +static const char *spk_function[] = { "off", "on" }; + +static const struct soc_enum wm8350_enum[] = { + SOC_ENUM_SINGLE_EXT(2, jack_function), + SOC_ENUM_SINGLE_EXT(2, spk_function), +}; + +static int wm8350_get_jack(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = wm8350_jack_func; + return 0; +} + +static int wm8350_set_jack(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + + if (wm8350_jack_func == ucontrol->value.enumerated.item[0]) + return 0; + + wm8350_jack_func = ucontrol->value.enumerated.item[0]; + if (wm8350_jack_func) + snd_soc_dapm_enable_pin(codec, "Headphone Jack"); + else + snd_soc_dapm_disable_pin(codec, "Headphone Jack"); + + snd_soc_dapm_sync(codec); + return 1; +} + +static int wm8350_get_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = wm8350_spk_func; + return 0; +} + +static int wm8350_set_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + + if (wm8350_spk_func == ucontrol->value.enumerated.item[0]) + return 0; + + wm8350_spk_func = ucontrol->value.enumerated.item[0]; + if (wm8350_spk_func) + snd_soc_dapm_enable_pin(codec, "Line Out Jack"); + else + snd_soc_dapm_disable_pin(codec, "Line Out Jack"); + + snd_soc_dapm_sync(codec); + return 1; +} + +static int spk_amp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct imx_3stack_priv *priv = &machine_priv; + struct platform_device *pdev = priv->pdev; + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + + if (plat->amp_enable == NULL) + return 0; + + if (SND_SOC_DAPM_EVENT_ON(event)) + plat->amp_enable(1); + else + plat->amp_enable(0); + + return 0; +} + +static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = { + SND_SOC_DAPM_MIC("SiMIC", NULL), + SND_SOC_DAPM_MIC("Mic1 Jack", NULL), + SND_SOC_DAPM_MIC("Mic2 Jack", NULL), + SND_SOC_DAPM_LINE("Line In Jack", NULL), + SND_SOC_DAPM_LINE("Line Out Jack", NULL), + SND_SOC_DAPM_SPK("Ext Spk", spk_amp_event), + SND_SOC_DAPM_HP("Headphone Jack", NULL), +}; + +static const struct snd_kcontrol_new wm8350_machine_controls[] = { + SOC_ENUM_EXT("Jack Function", wm8350_enum[0], wm8350_get_jack, + wm8350_set_jack), + SOC_ENUM_EXT("Speaker Function", wm8350_enum[1], wm8350_get_spk, + wm8350_set_spk), +}; + +static int imx_3stack_wm8350_init(struct snd_soc_codec *codec) +{ + struct imx_3stack_priv *priv = &machine_priv; + struct wm8350 *wm8350 = priv->wm8350; + int i, ret; + + codec->control_data = wm8350; + + /* Add imx_3stack specific controls */ + for (i = 0; i < ARRAY_SIZE(wm8350_machine_controls); i++) { + ret = snd_ctl_add(codec->card, + snd_soc_cnew(&wm8350_machine_controls[i], + codec, NULL)); + if (ret < 0) + return ret; + } + + /* Add imx_3stack specific widgets */ + snd_soc_dapm_new_controls(codec, imx_3stack_dapm_widgets, + ARRAY_SIZE(imx_3stack_dapm_widgets)); + + /* Set up imx_3stack specific audio path audio_map */ + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_sync(codec); + + return 0; + +} + +/* imx_3stack digital audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link imx_3stack_dai = { + .name = "WM8350", + .stream_name = "WM8350", + .codec_dai = &wm8350_dai, + .init = imx_3stack_wm8350_init, + .ops = &imx_3stack_ops, +}; + +static int imx_3stack_machine_probe(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + struct imx_3stack_priv *priv = &machine_priv; + struct wm8350 *wm8350 = priv->wm8350; + + socdev->codec_data = wm8350; + + return 0; +} + +static struct snd_soc_card snd_soc_card_imx_3stack = { + .name = "imx-3stack", + .platform = &imx_soc_platform, + .dai_link = &imx_3stack_dai, + .num_links = 1, + .probe = imx_3stack_machine_probe, +}; + +static struct snd_soc_device imx_3stack_snd_devdata = { + .card = &snd_soc_card_imx_3stack, + .codec_dev = &soc_codec_dev_wm8350, +}; + +static int __devinit imx_3stack_wm8350_probe(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + struct imx_3stack_priv *priv = &machine_priv; + struct wm8350 *wm8350 = plat->priv; + struct snd_soc_dai *wm8350_cpu_dai; + int ret = 0; + u16 reg; + + priv->pdev = pdev; + priv->wm8350 = wm8350; + + gpio_activate_audio_ports(); + imx_3stack_init_dam(plat->src_port, plat->ext_port); + + if (plat->src_port == 2) + wm8350_cpu_dai = imx_ssi_dai[2]; + else + wm8350_cpu_dai = imx_ssi_dai[0]; + + imx_3stack_dai.cpu_dai = wm8350_cpu_dai; + + ret = driver_create_file(pdev->dev.driver, &driver_attr_headphone); + if (ret < 0) { + pr_err("%s:failed to create driver_attr_headphone\n", __func__); + return ret; + } + + /* enable slow clock gen for jack detect */ + reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_4); + wm8350_reg_write(wm8350, WM8350_POWER_MGMT_4, reg | WM8350_TOCLK_ENA); + /* enable jack detect */ + reg = wm8350_reg_read(wm8350, WM8350_JACK_DETECT); + wm8350_reg_write(wm8350, WM8350_JACK_DETECT, reg | WM8350_JDR_ENA); + wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, + imx_3stack_jack_handler, NULL); + wm8350_unmask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + + wm8350_jack_func = 1; + wm8350_spk_func = 1; + + return 0; +} + +static int imx_3stack_wm8350_remove(struct platform_device *pdev) +{ + struct imx_3stack_priv *priv = &machine_priv; + struct wm8350 *wm8350 = priv->wm8350; + + wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); + + return 0; +} + +static struct platform_driver imx_3stack_wm8350_audio_driver = { + .probe = imx_3stack_wm8350_probe, + .remove = __devexit_p(imx_3stack_wm8350_remove), + .driver = { + .name = "wm8350-imx-3stack-audio", + }, +}; + +static struct platform_device *imx_3stack_snd_device; + +static int __init imx_3stack_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_3stack_wm8350_audio_driver); + if (ret) + return -ENOMEM; + + imx_3stack_snd_device = platform_device_alloc("soc-audio", -1); + if (!imx_3stack_snd_device) + return -ENOMEM; + + platform_set_drvdata(imx_3stack_snd_device, &imx_3stack_snd_devdata); + imx_3stack_snd_devdata.dev = &imx_3stack_snd_device->dev; + ret = platform_device_add(imx_3stack_snd_device); + + if (ret) + platform_device_put(imx_3stack_snd_device); + + return ret; +} + +static void __exit imx_3stack_exit(void) +{ + platform_driver_unregister(&imx_3stack_wm8350_audio_driver); + platform_device_unregister(imx_3stack_snd_device); +} + +module_init(imx_3stack_init); +module_exit(imx_3stack_exit); + +MODULE_AUTHOR("Liam Girdwood"); +MODULE_DESCRIPTION("PMIC WM8350 Driver for i.MX 3STACK"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-3stack-wm8580.c b/sound/soc/imx/imx-3stack-wm8580.c new file mode 100644 index 000000000000..d2366e9c74a1 --- /dev/null +++ b/sound/soc/imx/imx-3stack-wm8580.c @@ -0,0 +1,437 @@ +/* + * imx-3stack-wm8580.c -- SoC 5.1 audio for imx_3stack + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "imx-pcm.h" +#include "imx-esai.h" +#include "../codecs/wm8580.h" + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +#include +#endif + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +static unsigned int asrc_rates[] = { + 0, + 8000, + 11025, + 16000, + 22050, + 32000, + 44100, + 48000, + 64000, + 88200, + 96000, + 176400, + 192000, +}; + +struct asrc_esai { + unsigned int cpu_dai_rates; + unsigned int codec_dai_rates; + enum asrc_pair_index asrc_index; + unsigned int output_sample_rate; +}; + +static struct asrc_esai asrc_esai_data; + +#endif + +struct imx_3stack_pcm_state { + int lr_clk_active; +}; + +static struct imx_3stack_pcm_state clk_state; + +static int imx_3stack_startup(struct snd_pcm_substream *substream) +{ + clk_state.lr_clk_active++; +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (asrc_esai_data.output_sample_rate >= 32000) { + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + asrc_esai_data.cpu_dai_rates = cpu_dai->playback.rates; + asrc_esai_data.codec_dai_rates = codec_dai->playback.rates; + cpu_dai->playback.rates = + SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT; + codec_dai->playback.rates = + SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT; + } +#endif + + return 0; +} + +static void imx_3stack_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (asrc_esai_data.output_sample_rate >= 32000) { + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + codec_dai->playback.rates = asrc_esai_data.codec_dai_rates; + cpu_dai->playback.rates = asrc_esai_data.cpu_dai_rates; + asrc_release_pair(asrc_esai_data.asrc_index); + } +#endif + + /* disable the PLL if there are no active Tx or Rx channels */ + if (!codec_dai->active) + snd_soc_dai_set_pll(codec_dai, 0, 0, 0, 0); + clk_state.lr_clk_active--; +} + +static int imx_3stack_surround_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *pcm_link = rtd->dai; + struct snd_soc_dai *cpu_dai = pcm_link->cpu_dai; + struct snd_soc_dai *codec_dai = pcm_link->codec_dai; + unsigned int rate = params_rate(params); + u32 dai_format; + unsigned int pll_out = 0, lrclk_ratio = 0; + unsigned int channel = params_channels(params); + struct imx_esai *esai_mode = (struct imx_esai *)cpu_dai->private_data; + + if (clk_state.lr_clk_active > 1) + return 0; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (asrc_esai_data.output_sample_rate >= 32000) { + unsigned int asrc_input_rate = rate; + struct mxc_runtime_data *pcm_data = + substream->runtime->private_data; + struct asrc_config config; + int retVal = 0;; + + retVal = asrc_req_pair(channel, &asrc_esai_data.asrc_index); + if (retVal < 0) { + pr_err("Fail to request asrc pair\n"); + return -1; + } + + config.pair = asrc_esai_data.asrc_index; + config.channel_num = channel; + config.input_sample_rate = asrc_input_rate; + config.output_sample_rate = asrc_esai_data.output_sample_rate; + config.inclk = INCLK_NONE; + config.word_width = 32; + config.outclk = OUTCLK_ESAI_TX; + retVal = asrc_config_pair(&config); + if (retVal < 0) { + pr_err("Fail to config asrc\n"); + asrc_release_pair(asrc_esai_data.asrc_index); + return retVal; + } + rate = asrc_esai_data.output_sample_rate; + pcm_data->asrc_index = asrc_esai_data.asrc_index; + pcm_data->asrc_enable = 1; + } +#endif + + switch (rate) { + case 8000: + lrclk_ratio = 5; + pll_out = 6144000; + break; + case 11025: + lrclk_ratio = 4; + pll_out = 5644800; + break; + case 16000: + lrclk_ratio = 3; + pll_out = 6144000; + break; + case 32000: + lrclk_ratio = 3; + pll_out = 12288000; + break; + case 48000: + lrclk_ratio = 2; + pll_out = 12288000; + break; + case 64000: + lrclk_ratio = 1; + pll_out = 12288000; + break; + case 96000: + lrclk_ratio = 2; + pll_out = 24576000; + break; + case 128000: + lrclk_ratio = 1; + pll_out = 24576000; + break; + case 22050: + lrclk_ratio = 4; + pll_out = 11289600; + break; + case 44100: + lrclk_ratio = 2; + pll_out = 11289600; + break; + case 88200: + lrclk_ratio = 0; + pll_out = 11289600; + break; + case 176400: + lrclk_ratio = 0; + pll_out = 22579200; + break; + case 192000: + lrclk_ratio = 0; + pll_out = 24576000; + break; + default: + pr_info("Rate not support.\n"); + return -EINVAL;; + } + + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM; + + esai_mode->sync_mode = 0; + esai_mode->network_mode = 1; + + /* set codec DAI configuration */ + snd_soc_dai_set_fmt(codec_dai, dai_format); + + /* set cpu DAI configuration */ + snd_soc_dai_set_fmt(cpu_dai, dai_format); + + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, + channel == 1 ? 0x1 : 0x3, + channel == 1 ? 0x1 : 0x3, + 2, 0); + + /* set the ESAI system clock as input (unused) */ + snd_soc_dai_set_sysclk(cpu_dai, 0, 0, SND_SOC_CLOCK_IN); + + snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_PLLA); + snd_soc_dai_set_clkdiv(codec_dai, WM8580_DAC_CLKSEL, + WM8580_CLKSRC_PLLA); + + /* set codec LRCLK and BCLK */ + snd_soc_dai_set_sysclk(codec_dai, WM8580_BCLK_CLKDIV, 0, + SND_SOC_CLOCK_OUT); + snd_soc_dai_set_sysclk(codec_dai, WM8580_LRCLK_CLKDIV, lrclk_ratio, + SND_SOC_CLOCK_OUT); + + snd_soc_dai_set_pll(codec_dai, 1, 0, 12000000, pll_out); + return 0; +} + +static struct snd_soc_ops imx_3stack_surround_ops = { + .startup = imx_3stack_startup, + .shutdown = imx_3stack_shutdown, + .hw_params = imx_3stack_surround_hw_params, +}; + +static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets[] = { + SND_SOC_DAPM_LINE("Line Out Jack", NULL), +}; + +static const struct snd_soc_dapm_route audio_map[] = { + /* Line out jack */ + {"Line Out Jack", NULL, "VOUT1L"}, + {"Line Out Jack", NULL, "VOUT1R"}, + {"Line Out Jack", NULL, "VOUT2L"}, + {"Line Out Jack", NULL, "VOUT2R"}, + {"Line Out Jack", NULL, "VOUT3L"}, + {"Line Out Jack", NULL, "VOUT3R"}, +}; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +static int asrc_func; + +static const char *asrc_function[] = { + "disable", "32KHz", "44.1KHz", + "48KHz", "64KHz", "88.2KHz", "96KHz", "176.4KHz", "192KHz" +}; + +static const struct soc_enum asrc_enum[] = { + SOC_ENUM_SINGLE_EXT(9, asrc_function), +}; + +static int asrc_get_rate(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = asrc_func; + return 0; +} + +static int asrc_set_rate(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + if (asrc_func == ucontrol->value.enumerated.item[0]) + return 0; + + asrc_func = ucontrol->value.enumerated.item[0]; + asrc_esai_data.output_sample_rate = asrc_rates[asrc_func + 4]; + + return 1; +} + +static const struct snd_kcontrol_new asrc_controls[] = { + SOC_ENUM_EXT("ASRC", asrc_enum[0], asrc_get_rate, + asrc_set_rate), +}; + +#endif + +static int imx_3stack_wm8580_init(struct snd_soc_codec *codec) +{ + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + int i; + int ret; + for (i = 0; i < ARRAY_SIZE(asrc_controls); i++) { + ret = snd_ctl_add(codec->card, + snd_soc_cnew(&asrc_controls[i], codec, NULL)); + if (ret < 0) + return ret; + } + asrc_esai_data.output_sample_rate = asrc_rates[asrc_func + 4]; +#endif + + snd_soc_dapm_new_controls(codec, imx_3stack_dapm_widgets, + ARRAY_SIZE(imx_3stack_dapm_widgets)); + + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_sync(codec); + + return 0; +} + +static struct snd_soc_dai_link imx_3stack_dai = { + .name = "wm8580", + .stream_name = "wm8580", + .codec_dai = wm8580_dai, + .init = imx_3stack_wm8580_init, + .ops = &imx_3stack_surround_ops, +}; + +static int imx_3stack_card_remove(struct platform_device *pdev) +{ + struct snd_soc_device *socdev = platform_get_drvdata(pdev); + kfree(socdev->codec_data); + return 0; +} + +static struct snd_soc_card snd_soc_card_imx_3stack = { + .name = "imx-3stack", + .platform = &imx_soc_platform, + .dai_link = &imx_3stack_dai, + .num_links = 1, + .remove = imx_3stack_card_remove, +}; + +static struct snd_soc_device imx_3stack_snd_devdata = { + .card = &snd_soc_card_imx_3stack, + .codec_dev = &soc_codec_dev_wm8580, +}; + +/* + * This function will register the snd_soc_pcm_link drivers. + */ +static int __devinit imx_3stack_wm8580_probe(struct platform_device *pdev) +{ + struct wm8580_setup_data *setup; + + imx_3stack_dai.cpu_dai = &imx_esai_dai[2]; + imx_3stack_dai.cpu_dai->dev = &pdev->dev; + + setup = kzalloc(sizeof(struct wm8580_setup_data), GFP_KERNEL); + setup->spi = 1; + imx_3stack_snd_devdata.codec_data = setup; + + return 0; +} + +static int __devexit imx_3stack_wm8580_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver imx_3stack_wm8580_driver = { + .probe = imx_3stack_wm8580_probe, + .remove = __devexit_p(imx_3stack_wm8580_remove), + .driver = { + .name = "imx-3stack-wm8580", + .owner = THIS_MODULE, + }, +}; + +static struct platform_device *imx_3stack_snd_device; + +static int __init imx_3stack_asoc_init(void) +{ + int ret; + + ret = platform_driver_register(&imx_3stack_wm8580_driver); + if (ret < 0) + goto exit; + imx_3stack_snd_device = platform_device_alloc("soc-audio", 1); + if (!imx_3stack_snd_device) + goto err_device_alloc; + platform_set_drvdata(imx_3stack_snd_device, &imx_3stack_snd_devdata); + imx_3stack_snd_devdata.dev = &imx_3stack_snd_device->dev; + ret = platform_device_add(imx_3stack_snd_device); + if (0 == ret) + goto exit; + + platform_device_put(imx_3stack_snd_device); + err_device_alloc: + platform_driver_unregister(&imx_3stack_wm8580_driver); + exit: + return ret; +} + +static void __exit imx_3stack_asoc_exit(void) +{ + platform_driver_unregister(&imx_3stack_wm8580_driver); + platform_device_unregister(imx_3stack_snd_device); +} + +module_init(imx_3stack_asoc_init); +module_exit(imx_3stack_asoc_exit); + +/* Module information */ +MODULE_DESCRIPTION("ALSA SoC wm8580 imx_3stack"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-ac97.c b/sound/soc/imx/imx-ac97.c new file mode 100644 index 000000000000..801e98efb4f8 --- /dev/null +++ b/sound/soc/imx/imx-ac97.c @@ -0,0 +1,564 @@ +/* + * imx-ac97.c -- AC97 driver for Freescale IMX + * + * + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Revision history + * 26th Nov. 2009 Initial version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-ssi.h" +#include "imx-pcm.h" + +static DEFINE_MUTEX(ac97_mutex); +static DECLARE_COMPLETION(ac97_completion); + +struct imx_ac97_runtime { + u32 id; + u32 playback; + u32 capture; +}; + +static struct imx_ac97_runtime imx_ac97_para; +static struct imx_ssi imx_ac97_data[2]; + +#define IMX_SSI_DUMP 0 +#if IMX_SSI_DUMP +#define SSI_DUMP() \ + do { \ + printk(KERN_INFO "dump @ %s\n", __func__); \ + printk(KERN_INFO "scr %x\t, %x\n", \ + __raw_readl(SSI1_SCR), __raw_readl(SSI2_SCR)); \ + printk(KERN_INFO "sisr %x\t, %x\n", \ + __raw_readl(SSI1_SISR), __raw_readl(SSI2_SISR)); \ + printk(KERN_INFO "stcr %x\t, %x\n", \ + __raw_readl(SSI1_STCR), __raw_readl(SSI2_STCR)); \ + printk(KERN_INFO "srcr %x\t, %x\n", \ + __raw_readl(SSI1_SRCR), __raw_readl(SSI2_SRCR)); \ + printk(KERN_INFO "stccr %x\t, %x\n", \ + __raw_readl(SSI1_STCCR), __raw_readl(SSI2_STCCR)); \ + printk(KERN_INFO "srccr %x\t, %x\n", \ + __raw_readl(SSI1_SRCCR), __raw_readl(SSI2_SRCCR)); \ + printk(KERN_INFO "sfcsr %x\t, %x\n", \ + __raw_readl(SSI1_SFCSR), __raw_readl(SSI2_SFCSR)); \ + printk(KERN_INFO "stmsk %x\t, %x\n", \ + __raw_readl(SSI1_STMSK), __raw_readl(SSI2_STMSK)); \ + printk(KERN_INFO "srmsk %x\t, %x\n", \ + __raw_readl(SSI1_SRMSK), __raw_readl(SSI2_SRMSK)); \ + printk(KERN_INFO "sier %x\t, %x\n", \ + __raw_readl(SSI1_SIER), __raw_readl(SSI2_SIER)); \ + printk(KERN_INFO "sacnt %x\t, %x\n", \ + __raw_readl(SSI1_SACNT), __raw_readl(SSI2_SACNT)); \ + printk(KERN_INFO "sacdd %x\t, %x\n", \ + __raw_readl(SSI1_SACADD), __raw_readl(SSI2_SACADD)); \ + printk(KERN_INFO "sacdat %x\t, %x\n", \ + __raw_readl(SSI1_SACDAT), __raw_readl(SSI2_SACDAT)); \ + printk(KERN_INFO "satag %x\t, %x\n", \ + __raw_readl(SSI1_SATAG), __raw_readl(SSI2_SATAG)); \ + printk(KERN_INFO "saccst %x\t, %x\n", \ + __raw_readl(SSI1_SACCST), __raw_readl(SSI2_SACCST)); \ + printk(KERN_INFO "saccen %x\t, %x\n", \ + __raw_readl(SSI1_SACCEN), __raw_readl(SSI2_SACCEN)); \ + printk(KERN_INFO "saccdis %x\t, %x\n", \ + __raw_readl(SSI1_SACCDIS), __raw_readl(SSI2_SACCDIS)); \ + } while (0); +#else +#define SSI_DUMP() +#endif + +/* + * Read register value from codec, the read command is sent from + * AC97 slot 2 - 3. The register value is sent back at slot 2 -3 + * in next RX frame. + */ +static unsigned short imx_ac97_read(struct snd_ac97 *ac97, unsigned short reg) +{ + u32 sacdat, sier, scr; + mutex_lock(&ac97_mutex); + if (imx_ac97_para.id == IMX_DAI_AC97_1) { + sier = __raw_readl(SSI1_SIER); + scr = __raw_readl(SSI1_SCR); + __raw_writel((reg << 12), SSI1_SACADD); + __raw_writel(sier | SSI_SIER_CMDDU_EN, SSI1_SIER); + __raw_writel(SSI_SACNT_RD | __raw_readl(SSI1_SACNT), + SSI1_SACNT); + __raw_writel(scr | SSI_SCR_TE | SSI_SCR_RE, SSI1_SCR); + wait_for_completion_timeout(&ac97_completion, HZ); + sacdat = __raw_readl(SSI1_SACDAT); + __raw_writel(sier, SSI1_SIER); + __raw_writel(scr, SSI1_SCR); + } else { + sier = __raw_readl(SSI2_SIER); + scr = __raw_readl(SSI2_SCR); + __raw_writel((reg << 12), SSI2_SACADD); + __raw_writel(sier | SSI_SIER_CMDDU_EN, SSI2_SIER); + __raw_writel(SSI_SACNT_RD | __raw_readl(SSI2_SACNT), + SSI2_SACNT); + __raw_writel(scr | SSI_SCR_TE | SSI_SCR_RE, SSI2_SCR); + wait_for_completion_timeout(&ac97_completion, HZ); + sacdat = __raw_readl(SSI2_SACDAT); + __raw_writel(sier, SSI2_SIER); + __raw_writel(scr, SSI2_SCR); + } + mutex_unlock(&ac97_mutex); + return (unsigned short)(sacdat >> 4); + +} + +/* + * This fucntion is used to send command to codec. + */ +static void imx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, + unsigned short val) +{ + u32 scr; + mutex_lock(&ac97_mutex); + if (imx_ac97_para.id == IMX_DAI_AC97_1) { + scr = __raw_readl(SSI1_SCR); + __raw_writel(reg << 12, SSI1_SACADD); + __raw_writel(val << 4, SSI1_SACDAT); + __raw_writel(SSI_SACNT_WR | __raw_readl(SSI1_SACNT), + SSI1_SACNT); + __raw_writel(scr | SSI_SCR_TE | SSI_SCR_RE, SSI1_SCR); + udelay(100); + __raw_writel(scr, SSI1_SCR); + } else { + scr = __raw_readl(SSI2_SCR); + __raw_writel(reg << 12, SSI2_SACADD); + __raw_writel(val << 4, SSI2_SACDAT); + __raw_writel(SSI_SACNT_WR | __raw_readl(SSI2_SACNT), + SSI2_SACNT); + __raw_writel(scr | SSI_SCR_TE | SSI_SCR_RE, SSI2_SCR); + udelay(100); + __raw_writel(scr, SSI1_SCR); + } + mutex_unlock(&ac97_mutex); + +} + +struct snd_ac97_bus_ops soc_ac97_ops = { + .read = imx_ac97_read, + .write = imx_ac97_write, +}; +EXPORT_SYMBOL_GPL(soc_ac97_ops); + +static struct clk *ssi1_clk; +static struct clk *ssi2_clk; + +static int imx_ac97_hw_tx_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) +{ + struct imx_ssi *ssi_mode = (struct imx_ssi *)cpu_dai->private_data; + u32 channel = params_channels(params); + u32 stccr, sier; + + if (cpu_dai->id == IMX_DAI_AC97_1) { + stccr = + __raw_readl(SSI1_STCCR) & ~(SSI_STCCR_WL_MASK | + SSI_STCCR_DC_MASK); + sier = __raw_readl(SSI1_SIER); + } else { + stccr = + __raw_readl(SSI2_STCCR) & ~(SSI_STCCR_WL_MASK | + SSI_STCCR_DC_MASK); + sier = __raw_readl(SSI2_SIER); + } + + /* DAI data (word) size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + stccr |= SSI_STCCR_WL(16) | SSI_STCCR_DC(0x0C); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + stccr |= SSI_STCCR_WL(20) | SSI_STCCR_DC(0x0C); + break; + } + if (ssi_mode->ac97_rx_slots) + __raw_writel(ssi_mode->ac97_rx_slots, SSI1_SACCEN); + else + __raw_writel(((1 << channel) - 1) << (10 - channel), + SSI1_SACCEN); + + sier |= SSI_SIER_TDMAE; + + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI1) { + __raw_writel(stccr, SSI1_STCCR); + __raw_writel(sier, SSI1_SIER); + } else { + __raw_writel(stccr, SSI2_STCCR); + __raw_writel(sier, SSI2_SIER); + } + + return 0; +} + +static int imx_ac97_hw_rx_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) +{ + struct imx_ssi *ssi_mode = (struct imx_ssi *)cpu_dai->private_data; + u32 channel = params_channels(params); + u32 srccr, sier; + + if (cpu_dai->id == IMX_DAI_AC97_1) { + srccr = __raw_readl(SSI1_SRCCR); + sier = __raw_readl(SSI1_SIER); + } else { + srccr = __raw_readl(SSI2_SRCCR); + sier = __raw_readl(SSI2_SIER); + } + srccr &= ~(SSI_SRCCR_WL_MASK | SSI_SRCCR_DC_MASK); + + /* DAI data (word) size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + srccr |= SSI_SRCCR_WL(16) | SSI_SRCCR_DC(0x0C); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + srccr |= SSI_SRCCR_WL(20) | SSI_SRCCR_DC(0x0C); + break; + } + + if (ssi_mode->ac97_tx_slots) + __raw_writel(ssi_mode->ac97_tx_slots, SSI1_SACCEN); + else + __raw_writel(((1 << channel) - 1) << (10 - channel), + SSI1_SACCEN); + + /* enable interrupts */ + sier |= SSI_SIER_RDMAE; + + if (cpu_dai->id == IMX_DAI_AC97_1) { + __raw_writel(srccr, SSI1_SRCCR); + __raw_writel(sier, SSI1_SIER); + } else { + __raw_writel(srccr, SSI2_SRCCR); + __raw_writel(sier, SSI2_SIER); + } + return 0; +} + +static int imx_ac97_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) +{ + u32 rate = params_rate(params); + u32 sacnt; + + if (cpu_dai->id == IMX_DAI_AC97_1) + sacnt = __raw_readl(SSI1_SACNT); + else + sacnt = __raw_readl(SSI2_SACNT); + + switch (rate) { + case 8000: + sacnt |= SSI_SACNT_FV | SSI_SACNT_FRDIV(0x05); + break; + case 11050: + sacnt |= SSI_SACNT_FV | SSI_SACNT_FRDIV(0x03); + break; + case 16000: + sacnt |= SSI_SACNT_FV | SSI_SACNT_FRDIV(0x02); + break; + case 22050: + sacnt |= SSI_SACNT_FV | SSI_SACNT_FRDIV(0x01); + break; + case 44100: + case 48000: + sacnt |= SSI_SACNT_FV | SSI_SACNT_FRDIV(0x00); + break; + } + + if (cpu_dai->id == IMX_DAI_AC97_1) + __raw_writel(sacnt, SSI1_SACNT); + else + __raw_writel(sacnt, SSI2_SACNT); + + /* Tx/Rx config */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + return imx_ac97_hw_tx_params(substream, params, cpu_dai); + else + return imx_ac97_hw_rx_params(substream, params, cpu_dai); +} + +static int imx_ac97_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; + u32 scr, i, reg; + + if (cpu_dai->id == IMX_DAI_AC97_1) + scr = __raw_readl(SSI1_SCR); + else + scr = __raw_readl(SSI2_SCR); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + for (i = 0; i < 12; i++) + __raw_writel(0x0, SSI1_STX0); + } else { + for (i = 0; i < 12; i++) + reg = __raw_readl(SSI1_SRX0); + } + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + imx_ac97_para.playback = 1; + else + imx_ac97_para.capture = 1; + scr |= SSI_SCR_TE | SSI_SCR_RE; + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + imx_ac97_para.playback = 0; + else + imx_ac97_para.capture = 0; + + if ((imx_ac97_para.playback == 0) + && (imx_ac97_para.capture == 0)) + scr &= ~(SSI_SCR_TE | SSI_SCR_RE); + break; + default: + return -EINVAL; + } + if (cpu_dai->id == IMX_DAI_SSI0 || cpu_dai->id == IMX_DAI_SSI1) + __raw_writel(scr, SSI1_SCR); + else + __raw_writel(scr, SSI2_SCR); + SSI_DUMP(); + return 0; +} + +#ifdef CONFIG_PM +static int imx_ac97_suspend(struct snd_soc_dai *dai) +{ + if (!dai->active) + return 0; + + /* do we need to disable any clocks? */ + + return 0; +} + +static int imx_ac97_resume(struct snd_soc_dai *dai) +{ + if (!dai->active) + return 0; + + /* do we need to enable any clocks? */ + + return 0; +} +#else +#define imx_ac97_suspend NULL +#define imx_ac97_resume NULL +#endif + +static irqreturn_t ssi1_irq(int irq, void *dev_id) +{ + u32 sier, sisr, reg; + sier = __raw_readl(SSI1_SIER); + sisr = __raw_readl(SSI1_SISR); + if ((sier & SSI_SIER_CMDDU_EN) && (sisr & SSI_SISR_CMDDU)) { + reg = __raw_readl(SSI1_SACADD); + reg = __raw_readl(SSI1_SACDAT); + complete(&ac97_completion); + } + return IRQ_HANDLED; +} + +static irqreturn_t ssi2_irq(int irq, void *dev_id) +{ + u32 sier, sisr, reg; + sier = __raw_readl(SSI1_SIER); + sisr = __raw_readl(SSI1_SISR); + if ((sier & SSI_SIER_CMDDU_EN) && (sisr & SSI_SISR_CMDDU)) { + reg = __raw_readl(SSI2_SACADD); + reg = __raw_readl(SSI2_SACDAT); + complete(&ac97_completion); + } + return IRQ_HANDLED; +} + +static int imx_ac97_probe(struct platform_device *pdev, struct snd_soc_dai *dai) +{ + + u32 stccr; + stccr = SSI_STCCR_WL(16) | SSI_STCCR_DC(0x0C); + + if (!strcmp(dai->name, "imx-ac97-1")) { + dai->id = IMX_DAI_AC97_1; + ssi1_clk = clk_get(NULL, "ssi_clk.0"); + clk_enable(ssi1_clk); + + __raw_writel(SSI_SCR_SSIEN, SSI1_SCR); + + __raw_writel((SSI_SFCSR_RFWM1(SSI_RXFIFO_WATERMARK) | + SSI_SFCSR_RFWM0(SSI_RXFIFO_WATERMARK) | + SSI_SFCSR_TFWM1(SSI_TXFIFO_WATERMARK) | + SSI_SFCSR_TFWM0(SSI_TXFIFO_WATERMARK)), + SSI1_SFCSR); + + __raw_writel(stccr, SSI1_STCCR); + __raw_writel(stccr, SSI1_SRCCR); + __raw_writel(SSI_SACNT_AC97EN, SSI1_SACNT); + } else if (!strcmp(dai->name, "imx-ac97-2")) { + dai->id = IMX_DAI_AC97_2; + ssi2_clk = clk_get(NULL, "ssi_clk.1"); + clk_enable(ssi2_clk); + + __raw_writel(SSI_SCR_SSIEN, SSI2_SCR); + + __raw_writel((SSI_SFCSR_RFWM1(SSI_RXFIFO_WATERMARK) | + SSI_SFCSR_RFWM0(SSI_RXFIFO_WATERMARK) | + SSI_SFCSR_TFWM1(SSI_TXFIFO_WATERMARK) | + SSI_SFCSR_TFWM0(SSI_TXFIFO_WATERMARK)), + SSI2_SFCSR); + + __raw_writel(stccr, SSI2_STCCR); + __raw_writel(stccr, SSI2_SRCCR); + + __raw_writel(SSI_SACNT_AC97EN, SSI2_SACNT); + } else { + printk(KERN_ERR "%s: invalid device %s\n", __func__, dai->name); + return -ENODEV; + } + + if (!strcmp(dai->name, "imx-ac97-1")) { + if (request_irq(MXC_INT_SSI1, ssi1_irq, 0, "ssi1", dai)) { + printk(KERN_ERR + "%s: failure requesting irq %s\n", + __func__, "ssi1"); + return -EBUSY; + } + } + + if (!strcmp(dai->name, "imx-ac97-2")) { + if (request_irq(MXC_INT_SSI2, ssi2_irq, 0, "ssi2", dai)) { + printk(KERN_ERR + "%s: failure requesting irq %s\n", + __func__, "ssi2"); + return -EBUSY; + } + } + + return 0; +} + +static void imx_ac97_remove(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + if (!strcmp(dai->name, "imx-ac97-1")) + free_irq(MXC_INT_SSI1, dai); + + if (!strcmp(dai->name, "imx-ac97-2")) + free_irq(MXC_INT_SSI2, dai); +} + +#define IMX_AC97_RATES \ + (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000) + +#define IMX_AC97_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE) + +static struct snd_soc_dai_ops imx_ac97_dai_ops = { + .hw_params = imx_ac97_hw_params, + .trigger = imx_ac97_trigger, +}; + +struct snd_soc_dai imx_ac97_dai[] = { + { + .name = "imx-ac97-1", + .id = 0, + .ac97_control = 1, + .probe = imx_ac97_probe, + .remove = imx_ac97_remove, + .suspend = imx_ac97_suspend, + .resume = imx_ac97_resume, + .playback = { + .stream_name = "AC97 Playback", + .channels_min = 1, + .channels_max = 10, + .rates = IMX_AC97_RATES, + .formats = IMX_AC97_FORMATS, + }, + .capture = { + .stream_name = "AC97 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = IMX_AC97_RATES, + .formats = IMX_AC97_FORMATS, + }, + .ops = &imx_ac97_dai_ops, + .private_data = &imx_ac97_data[IMX_DAI_AC97_1], + }, + { + .name = "imx-ac97-2", + .id = 1, + .ac97_control = 1, + .probe = imx_ac97_probe, + .remove = imx_ac97_remove, + .suspend = imx_ac97_suspend, + .resume = imx_ac97_resume, + .playback = { + .stream_name = "AC97 Playback", + .channels_min = 1, + .channels_max = 10, + .rates = IMX_AC97_RATES, + .formats = IMX_AC97_FORMATS, + }, + .capture = { + .stream_name = "AC97 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = IMX_AC97_RATES, + .formats = IMX_AC97_FORMATS, + }, + .ops = &imx_ac97_dai_ops, + .private_data = &imx_ac97_data[IMX_DAI_AC97_2], + }, +}; +EXPORT_SYMBOL_GPL(imx_ac97_dai); + +static int __init imx_ac97_init(void) +{ + return snd_soc_register_dais(imx_ac97_dai, ARRAY_SIZE(imx_ac97_dai)); +} + +static void __exit imx_ac97_exit(void) +{ + snd_soc_unregister_dais(imx_ac97_dai, ARRAY_SIZE(imx_ac97_dai)); +} + +module_init(imx_ac97_init); +module_exit(imx_ac97_exit); + +MODULE_DESCRIPTION("i.MX ASoC AC97 driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-esai.c b/sound/soc/imx/imx-esai.c new file mode 100644 index 000000000000..2154599def5d --- /dev/null +++ b/sound/soc/imx/imx-esai.c @@ -0,0 +1,711 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + /*! + * @file imx-esai.c + * @brief this file implements the esai interface + * in according to ASoC architeture + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-esai.h" +#include "imx-pcm.h" + +static int imx_esai_txrx_state; +static struct imx_esai imx_esai_priv[3]; +static void __iomem *esai_ioaddr; + +static int imx_esai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, + int clk_id, unsigned int freq, int dir) +{ + u32 ecr, tccr, rccr; + + ecr = __raw_readl(ESAI_ECR); + tccr = __raw_readl(ESAI_TCCR); + rccr = __raw_readl(ESAI_RCCR); + + if (dir == SND_SOC_CLOCK_IN) { + if (cpu_dai->id & IMX_DAI_ESAI_TX) + tccr &= + ~(ESAI_TCCR_THCKD | ESAI_TCCR_TCKD | + ESAI_TCCR_TFSD); + if (cpu_dai->id & IMX_DAI_ESAI_RX) + rccr &= + ~(ESAI_RCCR_RHCKD | ESAI_RCCR_RCKD | + ESAI_RCCR_RFSD); + } else { + tccr |= + ESAI_TCCR_THCKD | ESAI_TCCR_TCKD | ESAI_TCCR_TFSD; + rccr |= + ESAI_RCCR_RHCKD | ESAI_RCCR_RCKD | ESAI_RCCR_RFSD; + if (clk_id == ESAI_CLK_FSYS) { + if (cpu_dai->id & IMX_DAI_ESAI_TX) + ecr &= ~(ESAI_ECR_ETI | ESAI_ECR_ETO); + if (cpu_dai->id & IMX_DAI_ESAI_RX) + ecr &= ~(ESAI_ECR_ERI | ESAI_ECR_ERO); + } else if (clk_id == ESAI_CLK_EXTAL) { + ecr |= ESAI_ECR_ETI; + ecr |= ESAI_ECR_ETO; + ecr |= ESAI_ECR_ERI; + ecr |= ESAI_ECR_ERO; + } + } + + __raw_writel(ecr, ESAI_ECR); + if (cpu_dai->id & IMX_DAI_ESAI_TX) + __raw_writel(tccr, ESAI_TCCR); + if (cpu_dai->id & IMX_DAI_ESAI_RX) + __raw_writel(rccr, ESAI_RCCR); + + ESAI_DUMP(); + + return 0; +} + +static int imx_esai_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, + int div_id, int div) +{ + u32 tccr, rccr; + + tccr = __raw_readl(ESAI_TCCR); + rccr = __raw_readl(ESAI_RCCR); + + switch (div_id) { + case ESAI_TX_DIV_PSR: + tccr &= ESAI_TCCR_TPSR_MASK; + if (div) + tccr |= ESAI_TCCR_TPSR_BYPASS; + else + tccr &= ~ESAI_TCCR_TPSR_DIV8; + break; + case ESAI_TX_DIV_PM: + tccr &= ESAI_TCCR_TPM_MASK; + tccr |= ESAI_TCCR_TPM(div); + break; + case ESAI_TX_DIV_FP: + tccr &= ESAI_TCCR_TFP_MASK; + tccr |= ESAI_TCCR_TFP(div); + break; + case ESAI_RX_DIV_PSR: + rccr &= ESAI_RCCR_RPSR_MASK; + if (div) + rccr |= ESAI_RCCR_RPSR_BYPASS; + else + rccr &= ~ESAI_RCCR_RPSR_DIV8; + break; + case ESAI_RX_DIV_PM: + rccr &= ESAI_RCCR_RPM_MASK; + rccr |= ESAI_RCCR_RPM(div); + break; + case ESAI_RX_DIV_FP: + rccr &= ESAI_RCCR_RFP_MASK; + rccr |= ESAI_RCCR_RFP(div); + break; + return -EINVAL; + } + if (cpu_dai->id & IMX_DAI_ESAI_TX) + __raw_writel(tccr, ESAI_TCCR); + if (cpu_dai->id & IMX_DAI_ESAI_RX) + __raw_writel(rccr, ESAI_RCCR); + return 0; +} + +/* + * ESAI Network Mode or TDM slots configuration. + */ +static int imx_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) +{ + u32 tccr, rccr; + + if (dai->id & IMX_DAI_ESAI_TX) { + tccr = __raw_readl(ESAI_TCCR); + + tccr &= ESAI_TCCR_TDC_MASK; + tccr |= ESAI_TCCR_TDC(slots - 1); + + __raw_writel(tccr, ESAI_TCCR); + __raw_writel((tx_mask & 0xffff), ESAI_TSMA); + __raw_writel(((tx_mask >> 16) & 0xffff), ESAI_TSMB); + } + + if (dai->id & IMX_DAI_ESAI_RX) { + rccr = __raw_readl(ESAI_RCCR); + + rccr &= ESAI_RCCR_RDC_MASK; + rccr |= ESAI_RCCR_RDC(slots - 1); + + __raw_writel(rccr, ESAI_RCCR); + __raw_writel((rx_mask & 0xffff), ESAI_RSMA); + __raw_writel(((rx_mask >> 16) & 0xffff), ESAI_RSMB); + } + + ESAI_DUMP(); + + return 0; +} + +/* + * ESAI DAI format configuration. + */ +static int imx_esai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) +{ + struct imx_esai *esai_mode = (struct imx_esai *)cpu_dai->private_data; + u32 tcr, tccr, rcr, rccr, saicr; + + tcr = __raw_readl(ESAI_TCR); + tccr = __raw_readl(ESAI_TCCR); + rcr = __raw_readl(ESAI_RCR); + rccr = __raw_readl(ESAI_RCCR); + saicr = __raw_readl(ESAI_SAICR); + + /* DAI mode */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + /* data on rising edge of bclk, frame low 1clk before data */ + tcr &= ~ESAI_TCR_TFSL; + tcr |= ESAI_TCR_TFSR; + rcr &= ~ESAI_RCR_RFSL; + rcr |= ESAI_RCR_RFSR; + break; + case SND_SOC_DAIFMT_LEFT_J: + /* data on rising edge of bclk, frame high with data */ + tcr &= ~(ESAI_TCR_TFSL | ESAI_TCR_TFSR); + rcr &= ~(ESAI_RCR_RFSL | ESAI_RCR_RFSR); + break; + case SND_SOC_DAIFMT_DSP_B: + /* data on rising edge of bclk, frame high with data */ + tcr |= ESAI_TCR_TFSL; + rcr |= ESAI_RCR_RFSL; + break; + case SND_SOC_DAIFMT_DSP_A: + /* data on rising edge of bclk, frame high 1clk before data */ + tcr |= ESAI_TCR_TFSL; + rcr |= ESAI_RCR_RFSL; + break; + } + + /* DAI clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_IB_IF: + tccr |= ESAI_TCCR_TFSP; + tccr &= ~(ESAI_TCCR_TCKP | ESAI_TCCR_THCKP); + rccr &= ~(ESAI_RCCR_RCKP | ESAI_RCCR_RHCKP); + rccr |= ESAI_RCCR_RFSP; + break; + case SND_SOC_DAIFMT_IB_NF: + tccr &= ~(ESAI_TCCR_TCKP | ESAI_TCCR_THCKP | ESAI_TCCR_TFSP); + rccr &= ~(ESAI_RCCR_RCKP | ESAI_RCCR_RHCKP | ESAI_RCCR_RFSP); + break; + case SND_SOC_DAIFMT_NB_IF: + tccr |= ESAI_TCCR_TCKP | ESAI_TCCR_THCKP | ESAI_TCCR_TFSP; + rccr |= ESAI_RCCR_RCKP | ESAI_RCCR_RHCKP | ESAI_RCCR_RFSP; + break; + case SND_SOC_DAIFMT_NB_NF: + tccr &= ~ESAI_TCCR_TFSP; + tccr |= ESAI_TCCR_TCKP | ESAI_TCCR_THCKP; + rccr &= ~ESAI_RCCR_RFSP; + rccr |= ESAI_RCCR_RCKP | ESAI_RCCR_RHCKP; + break; + } + + /* DAI clock master masks */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + tccr &= ~(ESAI_TCCR_TFSD | ESAI_TCCR_TCKD); + rccr &= ~(ESAI_RCCR_RFSD | ESAI_RCCR_RCKD); + break; + case SND_SOC_DAIFMT_CBS_CFM: + tccr &= ~ESAI_TCCR_TFSD; + tccr |= ESAI_TCCR_TCKD; + rccr &= ~ESAI_RCCR_RFSD; + rccr |= ESAI_RCCR_RCKD; + break; + case SND_SOC_DAIFMT_CBM_CFS: + tccr &= ~ESAI_TCCR_TCKD; + tccr |= ESAI_TCCR_TFSD; + rccr &= ~ESAI_RCCR_RCKD; + rccr |= ESAI_RCCR_RFSD; + break; + case SND_SOC_DAIFMT_CBS_CFS: + tccr |= (ESAI_TCCR_TFSD | ESAI_TCCR_TCKD); + rccr |= (ESAI_RCCR_RFSD | ESAI_RCCR_RCKD); + } + + /* sync */ + if (esai_mode->sync_mode) + saicr |= ESAI_SAICR_SYNC; + else + saicr &= ~ESAI_SAICR_SYNC; + + tcr &= ESAI_TCR_TMOD_MASK; + rcr &= ESAI_RCR_RMOD_MASK; + if (esai_mode->network_mode) { + tcr |= ESAI_TCR_TMOD_NETWORK; + rcr |= ESAI_RCR_RMOD_NETWORK; + } else { + tcr |= ESAI_TCR_TMOD_NORMAL; + rcr |= ESAI_RCR_RMOD_NORMAL; + } + + if (cpu_dai->id & IMX_DAI_ESAI_TX) { + __raw_writel(tcr, ESAI_TCR); + __raw_writel(tccr, ESAI_TCCR); + } + if (cpu_dai->id & IMX_DAI_ESAI_RX) { + __raw_writel(rcr, ESAI_RCR); + __raw_writel(rccr, ESAI_RCCR); + } + + __raw_writel(saicr, ESAI_SAICR); + + ESAI_DUMP(); + return 0; +} + +static struct clk *esai_clk; + +static int fifo_err_counter; + +static irqreturn_t esai_irq(int irq, void *dev_id) +{ + if (fifo_err_counter++ % 1000 == 0) + printk(KERN_ERR + "esai_irq SAISR %x fifo_errs=%d\n", + __raw_readl(ESAI_SAISR), fifo_err_counter); + return IRQ_HANDLED; +} + +static int imx_esai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + if (cpu_dai->playback.active && (cpu_dai->id & IMX_DAI_ESAI_TX)) + return 0; + if (cpu_dai->capture.active && (cpu_dai->id & IMX_DAI_ESAI_RX)) + return 0; + + if (!(imx_esai_txrx_state & IMX_DAI_ESAI_TXRX)) { + if (request_irq(MXC_INT_ESAI, esai_irq, 0, "esai", NULL)) { + pr_err("%s: failure requesting esai irq\n", __func__); + return -EBUSY; + } + clk_enable(esai_clk); + __raw_writel(ESAI_ECR_ERST, ESAI_ECR); + __raw_writel(ESAI_ECR_ESAIEN, ESAI_ECR); + + __raw_writel(ESAI_GPIO_ESAI, ESAI_PRRC); + __raw_writel(ESAI_GPIO_ESAI, ESAI_PCRC); + } + + if (cpu_dai->id & IMX_DAI_ESAI_TX) { + imx_esai_txrx_state |= IMX_DAI_ESAI_TX; + __raw_writel(ESAI_TCR_TPR, ESAI_TCR); + } + if (cpu_dai->id & IMX_DAI_ESAI_RX) { + imx_esai_txrx_state |= IMX_DAI_ESAI_RX; + __raw_writel(ESAI_RCR_RPR, ESAI_RCR); + } + + ESAI_DUMP(); + return 0; +} + +/* + * This function is called to initialize the TX port before enable + * the tx port. + */ +static int imx_esai_hw_tx_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + u32 tcr, tfcr; + unsigned int channels; + + tcr = __raw_readl(ESAI_TCR); + tfcr = __raw_readl(ESAI_TFCR); + + tfcr |= ESAI_TFCR_TFR; + __raw_writel(tfcr, ESAI_TFCR); + tfcr &= ~ESAI_TFCR_TFR; + /* DAI data (word) size */ + tfcr &= ESAI_TFCR_TWA_MASK; + tcr &= ESAI_TCR_TSWS_MASK; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + tfcr |= ESAI_WORD_LEN_16; + tcr |= ESAI_TCR_TSHFD_MSB | ESAI_TCR_TSWS_STL32_WDL16; + break; + case SNDRV_PCM_FORMAT_S20_3LE: + tfcr |= ESAI_WORD_LEN_20; + tcr |= ESAI_TCR_TSHFD_MSB | ESAI_TCR_TSWS_STL32_WDL20; + break; + case SNDRV_PCM_FORMAT_S24_LE: + tfcr |= ESAI_WORD_LEN_24; + tcr |= ESAI_TCR_TSHFD_MSB | ESAI_TCR_TSWS_STL32_WDL24; + break; + } + + channels = params_channels(params); + tfcr &= ESAI_TFCR_TE_MASK; + tfcr |= ESAI_TFCR_TE(channels); + + tfcr |= ESAI_TFCR_TFWM(64); + + /* Left aligned, Zero padding */ + tcr |= ESAI_TCR_PADC; + + __raw_writel(tcr, ESAI_TCR); + __raw_writel(tfcr, ESAI_TFCR); + + ESAI_DUMP(); + return 0; +} + +/* + * This function is called to initialize the RX port before enable + * the rx port. + */ +static int imx_esai_hw_rx_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + u32 rcr, rfcr; + unsigned int channels; + + rcr = __raw_readl(ESAI_RCR); + rfcr = __raw_readl(ESAI_RFCR); + + rfcr |= ESAI_RFCR_RFR; + __raw_writel(rfcr, ESAI_RFCR); + rfcr &= ~ESAI_RFCR_RFR; + + rfcr &= ESAI_RFCR_RWA_MASK; + rcr &= ESAI_RCR_RSWS_MASK; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + rfcr |= ESAI_WORD_LEN_16; + rcr |= ESAI_RCR_RSHFD_MSB | ESAI_RCR_RSWS_STL32_WDL16; + break; + } + + channels = params_channels(params); + rfcr &= ESAI_RFCR_RE_MASK; + rfcr |= ESAI_RFCR_RE(channels); + + rfcr |= ESAI_RFCR_RFWM(64); + + __raw_writel(rcr, ESAI_RCR); + __raw_writel(rfcr, ESAI_RFCR); + return 0; +} + +/* + * This function is called to initialize the TX or RX port, + */ +static int imx_esai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + /* Tx/Rx config */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (__raw_readl(ESAI_TCR) & ESAI_TCR_TE0) + return 0; + return imx_esai_hw_tx_params(substream, params, dai); + } else { + if (__raw_readl(ESAI_RCR) & ESAI_RCR_RE1) + return 0; + return imx_esai_hw_rx_params(substream, params, dai); + } +} + +static int imx_esai_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) +{ + u32 reg, tfcr = 0, rfcr = 0; + u32 temp; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + tfcr = __raw_readl(ESAI_TFCR); + reg = __raw_readl(ESAI_TCR); + } else { + rfcr = __raw_readl(ESAI_RFCR); + reg = __raw_readl(ESAI_RCR); + } + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + tfcr |= ESAI_TFCR_TFEN; + __raw_writel(tfcr, ESAI_TFCR); + reg &= ~ESAI_TCR_TPR; + reg |= ESAI_TCR_TE(substream->runtime->channels); + __raw_writel(reg, ESAI_TCR); + } else { + temp = __raw_readl(ESAI_TCR); + temp &= ~ESAI_TCR_TPR; + __raw_writel(temp, ESAI_TCR); + rfcr |= ESAI_RFCR_RFEN; + __raw_writel(rfcr, ESAI_RFCR); + reg &= ~ESAI_RCR_RPR; + reg |= ESAI_RCR_RE(substream->runtime->channels); + __raw_writel(reg, ESAI_RCR); + } + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + reg &= ~ESAI_TCR_TE(substream->runtime->channels); + __raw_writel(reg, ESAI_TCR); + reg |= ESAI_TCR_TPR; + __raw_writel(reg, ESAI_TCR); + tfcr |= ESAI_TFCR_TFR; + tfcr &= ~ESAI_TFCR_TFEN; + __raw_writel(tfcr, ESAI_TFCR); + tfcr &= ~ESAI_TFCR_TFR; + __raw_writel(tfcr, ESAI_TFCR); + } else { + reg &= ~ESAI_RCR_RE(substream->runtime->channels); + __raw_writel(reg, ESAI_RCR); + reg |= ESAI_RCR_RPR; + __raw_writel(reg, ESAI_RCR); + rfcr |= ESAI_RFCR_RFR; + rfcr &= ~ESAI_RFCR_RFEN; + __raw_writel(rfcr, ESAI_RFCR); + rfcr &= ~ESAI_RFCR_RFR; + __raw_writel(rfcr, ESAI_RFCR); + } + break; + default: + return -EINVAL; + } + ESAI_DUMP(); + return 0; +} + +static void imx_esai_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + if (dai->id & IMX_DAI_ESAI_TX) + imx_esai_txrx_state &= ~IMX_DAI_ESAI_TX; + if (dai->id & IMX_DAI_ESAI_RX) + imx_esai_txrx_state &= ~IMX_DAI_ESAI_RX; + + /* shutdown ESAI if neither Tx or Rx is active */ + if (!(imx_esai_txrx_state & IMX_DAI_ESAI_TXRX)) { + free_irq(MXC_INT_ESAI, NULL); + clk_disable(esai_clk); + } +} + +#ifdef CONFIG_PM +static int imx_esai_suspend(struct snd_soc_dai *dai) +{ + if (!dai->active) + return 0; + + /*do we need to disable any clocks */ + return 0; +} + +static int imx_esai_resume(struct snd_soc_dai *dai) +{ + if (!dai->active) + return 0; + + /* do we need to enable any clocks */ + return 0; +} + +#else +#define imx_esai_suspend NULL +#define imx_esai_resume NULL +#endif + +static int imx_esai_probe(struct platform_device *pdev, struct snd_soc_dai *dai) +{ + imx_esai_txrx_state = 0; + + esai_clk = clk_get(NULL, "esai_clk"); + if (!esai_clk) + printk(KERN_WARNING "Can't get the clock esai_clk \n"); + return 0; +} + +static void imx_esai_remove(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + + clk_put(esai_clk); +} + +#define IMX_ESAI_RATES SNDRV_PCM_RATE_8000_192000 + +#define IMX_ESAI_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +static struct snd_soc_dai_ops imx_esai_dai_ops = { + .startup = imx_esai_startup, + .shutdown = imx_esai_shutdown, + .trigger = imx_esai_trigger, + .hw_params = imx_esai_hw_params, + .set_sysclk = imx_esai_set_dai_sysclk, + .set_clkdiv = imx_esai_set_dai_clkdiv, + .set_fmt = imx_esai_set_dai_fmt, + .set_tdm_slot = imx_esai_set_dai_tdm_slot, +}; + +struct snd_soc_dai imx_esai_dai[] = { + { + .name = "imx-esai-tx", + .id = IMX_DAI_ESAI_TX, + .probe = imx_esai_probe, + .remove = imx_esai_remove, + .suspend = imx_esai_suspend, + .resume = imx_esai_resume, + .playback = { + .channels_min = 1, + .channels_max = 6, + .rates = IMX_ESAI_RATES, + .formats = IMX_ESAI_FORMATS, + }, + .capture = { + .channels_min = 1, + .channels_max = 4, + .rates = IMX_ESAI_RATES, + .formats = IMX_ESAI_FORMATS, + }, + .ops = &imx_esai_dai_ops, + .private_data = &imx_esai_priv[0], + }, + { + .name = "imx-esai-rx", + .id = IMX_DAI_ESAI_RX, + .probe = imx_esai_probe, + .remove = imx_esai_remove, + .suspend = imx_esai_suspend, + .resume = imx_esai_resume, + .playback = { + .channels_min = 1, + .channels_max = 6, + .rates = IMX_ESAI_RATES, + .formats = IMX_ESAI_FORMATS, + }, + .capture = { + .channels_min = 1, + .channels_max = 4, + .rates = IMX_ESAI_RATES, + .formats = IMX_ESAI_FORMATS, + }, + .ops = &imx_esai_dai_ops, + .private_data = &imx_esai_priv[1], + }, + { + .name = "imx-esai-txrx", + .id = IMX_DAI_ESAI_TXRX, + .probe = imx_esai_probe, + .remove = imx_esai_remove, + .suspend = imx_esai_suspend, + .resume = imx_esai_resume, + .playback = { + .channels_min = 1, + .channels_max = 6, + .rates = IMX_ESAI_RATES, + .formats = IMX_ESAI_FORMATS, + }, + .capture = { + .channels_min = 1, + .channels_max = 4, + .rates = IMX_ESAI_RATES, + .formats = IMX_ESAI_FORMATS, + }, + .ops = &imx_esai_dai_ops, + .private_data = &imx_esai_priv[2], + }, + +}; + +EXPORT_SYMBOL_GPL(imx_esai_dai); + +static int imx_esai_dev_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mxc_esai_platform_data *plat_data = pdev->dev.platform_data; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + esai_ioaddr = ioremap(res->start, res->end - res->start + 1); + + if (plat_data->activate_esai_ports) + plat_data->activate_esai_ports(); + + snd_soc_register_dais(imx_esai_dai, ARRAY_SIZE(imx_esai_dai)); + return 0; +} + +static int __devexit imx_esai_dev_remove(struct platform_device *pdev) +{ + + struct mxc_esai_platform_data *plat_data = pdev->dev.platform_data; + iounmap(esai_ioaddr); + if (plat_data->deactivate_esai_ports) + plat_data->deactivate_esai_ports(); + + snd_soc_unregister_dais(imx_esai_dai, ARRAY_SIZE(imx_esai_dai)); + return 0; +} + + +static struct platform_driver imx_esai_driver = { + .probe = imx_esai_dev_probe, + .remove = __devexit_p(imx_esai_dev_remove), + .driver = { + .name = "mxc_esai", + }, +}; + +static int __init imx_esai_init(void) +{ + return platform_driver_register(&imx_esai_driver); +} + +static void __exit imx_esai_exit(void) +{ + platform_driver_unregister(&imx_esai_driver); +} + +module_init(imx_esai_init); +module_exit(imx_esai_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("i.MX ASoC ESAI driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-esai.h b/sound/soc/imx/imx-esai.h new file mode 100644 index 000000000000..6e2cce0eff4a --- /dev/null +++ b/sound/soc/imx/imx-esai.h @@ -0,0 +1,314 @@ +/* + * imx-esai.h -- ESAI driver header file for Freescale IMX + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _MXC_ESAI_H +#define _MXC_ESAI_H + +/*#define IMX_ESAI_DUMP 1*/ + +#ifdef IMX_ESAI_DUMP +#define ESAI_DUMP() \ + do {pr_info("dump @ %s\n", __func__); \ + pr_info("ecr %x\n", __raw_readl(ESAI_ECR)); \ + pr_info("esr %x\n", __raw_readl(ESAI_ESR)); \ + pr_info("tfcr %x\n", __raw_readl(ESAI_TFCR)); \ + pr_info("tfsr %x\n", __raw_readl(ESAI_TFSR)); \ + pr_info("rfcr %x\n", __raw_readl(ESAI_RFCR)); \ + pr_info("rfsr %x\n", __raw_readl(ESAI_RFSR)); \ + pr_info("tsr %x\n", __raw_readl(ESAI_TSR)); \ + pr_info("saisr %x\n", __raw_readl(ESAI_SAISR)); \ + pr_info("saicr %x\n", __raw_readl(ESAI_SAICR)); \ + pr_info("tcr %x\n", __raw_readl(ESAI_TCR)); \ + pr_info("tccr %x\n", __raw_readl(ESAI_TCCR)); \ + pr_info("rcr %x\n", __raw_readl(ESAI_RCR)); \ + pr_info("rccr %x\n", __raw_readl(ESAI_RCCR)); \ + pr_info("tsma %x\n", __raw_readl(ESAI_TSMA)); \ + pr_info("tsmb %x\n", __raw_readl(ESAI_TSMB)); \ + pr_info("rsma %x\n", __raw_readl(ESAI_RSMA)); \ + pr_info("rsmb %x\n", __raw_readl(ESAI_RSMB)); \ + pr_info("prrc %x\n", __raw_readl(ESAI_PRRC)); \ + pr_info("pcrc %x\n", __raw_readl(ESAI_PCRC)); } while (0); +#else +#define ESAI_DUMP() +#endif + +#define ESAI_IO_BASE_ADDR (esai_ioaddr) + +#define ESAI_ETDR (ESAI_IO_BASE_ADDR + 0x00) +#define ESAI_ERDR (ESAI_IO_BASE_ADDR + 0x04) +#define ESAI_ECR (ESAI_IO_BASE_ADDR + 0x08) +#define ESAI_ESR (ESAI_IO_BASE_ADDR + 0x0C) +#define ESAI_TFCR (ESAI_IO_BASE_ADDR + 0x10) +#define ESAI_TFSR (ESAI_IO_BASE_ADDR + 0x14) +#define ESAI_RFCR (ESAI_IO_BASE_ADDR + 0x18) +#define ESAI_RFSR (ESAI_IO_BASE_ADDR + 0x1C) +#define ESAI_TX0 (ESAI_IO_BASE_ADDR + 0x80) +#define ESAI_TX1 (ESAI_IO_BASE_ADDR + 0x84) +#define ESAI_TX2 (ESAI_IO_BASE_ADDR + 0x88) +#define ESAI_TX3 (ESAI_IO_BASE_ADDR + 0x8C) +#define ESAI_TX4 (ESAI_IO_BASE_ADDR + 0x90) +#define ESAI_TX5 (ESAI_IO_BASE_ADDR + 0x94) +#define ESAI_TSR (ESAI_IO_BASE_ADDR + 0x98) +#define ESAI_RX0 (ESAI_IO_BASE_ADDR + 0xA0) +#define ESAI_RX1 (ESAI_IO_BASE_ADDR + 0xA4) +#define ESAI_RX2 (ESAI_IO_BASE_ADDR + 0xA8) +#define ESAI_RX3 (ESAI_IO_BASE_ADDR + 0xAC) +#define ESAI_SAISR (ESAI_IO_BASE_ADDR + 0xCC) +#define ESAI_SAICR (ESAI_IO_BASE_ADDR + 0xD0) +#define ESAI_TCR (ESAI_IO_BASE_ADDR + 0xD4) +#define ESAI_TCCR (ESAI_IO_BASE_ADDR + 0xD8) +#define ESAI_RCR (ESAI_IO_BASE_ADDR + 0xDC) +#define ESAI_RCCR (ESAI_IO_BASE_ADDR + 0xE0) +#define ESAI_TSMA (ESAI_IO_BASE_ADDR + 0xE4) +#define ESAI_TSMB (ESAI_IO_BASE_ADDR + 0xE8) +#define ESAI_RSMA (ESAI_IO_BASE_ADDR + 0xEC) +#define ESAI_RSMB (ESAI_IO_BASE_ADDR + 0xF0) +#define ESAI_PRRC (ESAI_IO_BASE_ADDR + 0xF8) +#define ESAI_PCRC (ESAI_IO_BASE_ADDR + 0xFC) + +#define ESAI_ECR_ETI (1 << 19) +#define ESAI_ECR_ETO (1 << 18) +#define ESAI_ECR_ERI (1 << 17) +#define ESAI_ECR_ERO (1 << 16) +#define ESAI_ECR_ERST (1 << 1) +#define ESAI_ECR_ESAIEN (1 << 0) + +#define ESAI_ESR_TINIT (1 << 10) +#define ESAI_ESR_RFF (1 << 9) +#define ESAI_ESR_TFE (1 << 8) +#define ESAI_ESR_TLS (1 << 7) +#define ESAI_ESR_TDE (1 << 6) +#define ESAI_ESR_TED (1 << 5) +#define ESAI_ESR_TD (1 << 4) +#define ESAI_ESR_RLS (1 << 3) +#define ESAI_ESR_RDE (1 << 2) +#define ESAI_ESR_RED (1 << 1) +#define ESAI_ESR_RD (1 << 0) + +#define ESAI_TFCR_TIEN (1 << 19) +#define ESAI_TFCR_TE5 (1 << 7) +#define ESAI_TFCR_TE4 (1 << 6) +#define ESAI_TFCR_TE3 (1 << 5) +#define ESAI_TFCR_TE2 (1 << 4) +#define ESAI_TFCR_TE1 (1 << 3) +#define ESAI_TFCR_TE0 (1 << 2) +#define ESAI_TFCR_TFR (1 << 1) +#define ESAI_TFCR_TFEN (1 << 0) +#define ESAI_TFCR_TE(x) ((0x3f >> (6 - ((x + 1) >> 1))) << 2) +#define ESAI_TFCR_TE_MASK 0xfff03 +#define ESAI_TFCR_TFWM(x) ((x - 1) << 8) +#define ESAI_TFCR_TWA_MASK 0xf8ffff + +#define ESAI_RFCR_REXT (1 << 19) +#define ESAI_RFCR_RE3 (1 << 5) +#define ESAI_RFCR_RE2 (1 << 4) +#define ESAI_RFCR_RE1 (1 << 3) +#define ESAI_RFCR_RE0 (1 << 2) +#define ESAI_RFCR_RFR (1 << 1) +#define ESAI_RFCR_RFEN (1 << 0) +#define ESAI_RFCR_RE(x) ((0xf >> (4 - ((x + 1) >> 1))) << 2) +#define ESAI_RFCR_RE_MASK 0xfffc3 +#define ESAI_RFCR_RFWM(x) ((x-1) << 8) +#define ESAI_RFCR_RWA_MASK 0xf8ffff + +#define ESAI_WORD_LEN_32 (0x00 << 16) +#define ESAI_WORD_LEN_28 (0x01 << 16) +#define ESAI_WORD_LEN_24 (0x02 << 16) +#define ESAI_WORD_LEN_20 (0x03 << 16) +#define ESAI_WORD_LEN_16 (0x04 << 16) +#define ESAI_WORD_LEN_12 (0x05 << 16) +#define ESAI_WORD_LEN_8 (0x06 << 16) +#define ESAI_WORD_LEN_4 (0x07 << 16) + +#define ESAI_SAISR_TODFE (1 << 17) +#define ESAI_SAISR_TEDE (1 << 16) +#define ESAI_SAISR_TDE (1 << 15) +#define ESAI_SAISR_TUE (1 << 14) +#define ESAI_SAISR_TFS (1 << 13) +#define ESAI_SAISR_RODF (1 << 10) +#define ESAI_SAISR_REDF (1 << 9) +#define ESAI_SAISR_RDF (1 << 8) +#define ESAI_SAISR_ROE (1 << 7) +#define ESAI_SAISR_RFS (1 << 6) +#define ESAI_SAISR_IF2 (1 << 2) +#define ESAI_SAISR_IF1 (1 << 1) +#define ESAI_SAISR_IF0 (1 << 0) + +#define ESAI_SAICR_ALC (1 << 8) +#define ESAI_SAICR_TEBE (1 << 7) +#define ESAI_SAICR_SYNC (1 << 6) +#define ESAI_SAICR_OF2 (1 << 2) +#define ESAI_SAICR_OF1 (1 << 1) +#define ESAI_SAICR_OF0 (1 << 0) + +#define ESAI_TCR_TLIE (1 << 23) +#define ESAI_TCR_TIE (1 << 22) +#define ESAI_TCR_TEDIE (1 << 21) +#define ESAI_TCR_TEIE (1 << 20) +#define ESAI_TCR_TPR (1 << 19) +#define ESAI_TCR_PADC (1 << 17) +#define ESAI_TCR_TFSR (1 << 16) +#define ESAI_TCR_TFSL (1 << 15) +#define ESAI_TCR_TWA (1 << 7) +#define ESAI_TCR_TSHFD_MSB (0 << 6) +#define ESAI_TCR_TSHFD_LSB (1 << 6) +#define ESAI_TCR_TE5 (1 << 5) +#define ESAI_TCR_TE4 (1 << 4) +#define ESAI_TCR_TE3 (1 << 3) +#define ESAI_TCR_TE2 (1 << 2) +#define ESAI_TCR_TE1 (1 << 1) +#define ESAI_TCR_TE0 (1 << 0) +#define ESAI_TCR_TE(x) (0x3f >> (6 - ((x + 1) >> 1))) + +#define ESAI_TCR_TSWS_MASK 0xff83ff +#define ESAI_TCR_TSWS_STL8_WDL8 (0x00 << 10) +#define ESAI_TCR_TSWS_STL12_WDL8 (0x04 << 10) +#define ESAI_TCR_TSWS_STL12_WDL12 (0x01 << 10) +#define ESAI_TCR_TSWS_STL16_WDL8 (0x08 << 10) +#define ESAI_TCR_TSWS_STL16_WDL12 (0x05 << 10) +#define ESAI_TCR_TSWS_STL16_WDL16 (0x02 << 10) +#define ESAI_TCR_TSWS_STL20_WDL8 (0x0c << 10) +#define ESAI_TCR_TSWS_STL20_WDL12 (0x09 << 10) +#define ESAI_TCR_TSWS_STL20_WDL16 (0x06 << 10) +#define ESAI_TCR_TSWS_STL20_WDL20 (0x03 << 10) +#define ESAI_TCR_TSWS_STL24_WDL8 (0x10 << 10) +#define ESAI_TCR_TSWS_STL24_WDL12 (0x0d << 10) +#define ESAI_TCR_TSWS_STL24_WDL16 (0x0a << 10) +#define ESAI_TCR_TSWS_STL24_WDL20 (0x07 << 10) +#define ESAI_TCR_TSWS_STL24_WDL24 (0x1e << 10) +#define ESAI_TCR_TSWS_STL32_WDL8 (0x18 << 10) +#define ESAI_TCR_TSWS_STL32_WDL12 (0x15 << 10) +#define ESAI_TCR_TSWS_STL32_WDL16 (0x12 << 10) +#define ESAI_TCR_TSWS_STL32_WDL20 (0x0f << 10) +#define ESAI_TCR_TSWS_STL32_WDL24 (0x1f << 10) + +#define ESAI_TCR_TMOD_MASK 0xfffcff +#define ESAI_TCR_TMOD_NORMAL (0x00 << 8) +#define ESAI_TCR_TMOD_ONDEMAND (0x01 << 8) +#define ESAI_TCR_TMOD_NETWORK (0x01 << 8) +#define ESAI_TCR_TMOD_RESERVED (0x02 << 8) +#define ESAI_TCR_TMOD_AC97 (0x03 << 8) + +#define ESAI_TCCR_THCKD (1 << 23) +#define ESAI_TCCR_TFSD (1 << 22) +#define ESAI_TCCR_TCKD (1 << 21) +#define ESAI_TCCR_THCKP (1 << 20) +#define ESAI_TCCR_TFSP (1 << 19) +#define ESAI_TCCR_TCKP (1 << 18) + +#define ESAI_TCCR_TPSR_MASK 0xfffeff +#define ESAI_TCCR_TPSR_BYPASS (1 << 8) +#define ESAI_TCCR_TPSR_DIV8 (0 << 8) + +#define ESAI_TCCR_TFP_MASK 0xfc3fff +#define ESAI_TCCR_TFP(x) ((x & 0xf) << 14) + +#define ESAI_TCCR_TDC_MASK 0xffc1ff +#define ESAI_TCCR_TDC(x) (((x) & 0x1f) << 9) + +#define ESAI_TCCR_TPM_MASK 0xffff00 +#define ESAI_TCCR_TPM(x) (x & 0xff) + +#define ESAI_RCR_RLIE (1 << 23) +#define ESAI_RCR_RIE (1 << 22) +#define ESAI_RCR_REDIE (1 << 21) +#define ESAI_RCR_REIE (1 << 20) +#define ESAI_RCR_RPR (1 << 19) +#define ESAI_RCR_RFSR (1 << 16) +#define ESAI_RCR_RFSL (1 << 15) +#define ESAI_RCR_RWA (1 << 7) +#define ESAI_RCR_RSHFD_MSB (0 << 6) +#define ESAI_RCR_RSHFD_LSB (1 << 6) +#define ESAI_RCR_RE3 (1 << 3) +#define ESAI_RCR_RE2 (1 << 2) +#define ESAI_RCR_RE1 (1 << 1) +#define ESAI_RCR_RE0 (1 << 0) +#define ESAI_RCR_RE(x) (0xf >> (4 - ((x + 1) >> 1))) + +#define ESAI_RCR_RSWS_MASK 0xff83ff +#define ESAI_RCR_RSWS_STL8_WDL8 (0x00 << 10) +#define ESAI_RCR_RSWS_STL12_WDL8 (0x04 << 10) +#define ESAI_RCR_RSWS_STL12_WDL12 (0x01 << 10) +#define ESAI_RCR_RSWS_STL16_WDL8 (0x08 << 10) +#define ESAI_RCR_RSWS_STL16_WDL12 (0x05 << 10) +#define ESAI_RCR_RSWS_STL16_WDL16 (0x02 << 10) +#define ESAI_RCR_RSWS_STL20_WDL8 (0x0c << 10) +#define ESAI_RCR_RSWS_STL20_WDL12 (0x09 << 10) +#define ESAI_RCR_RSWS_STL20_WDL16 (0x06 << 10) +#define ESAI_RCR_RSWS_STL20_WDL20 (0x03 << 10) +#define ESAI_RCR_RSWS_STL24_WDL8 (0x10 << 10) +#define ESAI_RCR_RSWS_STL24_WDL12 (0x0d << 10) +#define ESAI_RCR_RSWS_STL24_WDL16 (0x0a << 10) +#define ESAI_RCR_RSWS_STL24_WDL20 (0x07 << 10) +#define ESAI_RCR_RSWS_STL24_WDL24 (0x1e << 10) +#define ESAI_RCR_RSWS_STL32_WDL8 (0x18 << 10) +#define ESAI_RCR_RSWS_STL32_WDL12 (0x15 << 10) +#define ESAI_RCR_RSWS_STL32_WDL16 (0x12 << 10) +#define ESAI_RCR_RSWS_STL32_WDL20 (0x0f << 10) +#define ESAI_RCR_RSWS_STL32_WDL24 (0x1f << 10) + +#define ESAI_RCR_RMOD_MASK 0xfffcff +#define ESAI_RCR_RMOD_NORMAL (0x00 << 8) +#define ESAI_RCR_RMOD_ONDEMAND (0x01 << 8) +#define ESAI_RCR_RMOD_NETWORK (0x01 << 8) +#define ESAI_RCR_RMOD_RESERVED (0x02 << 8) +#define ESAI_RCR_RMOD_AC97 (0x03 << 8) + +#define ESAI_RCCR_RHCKD (1 << 23) +#define ESAI_RCCR_RFSD (1 << 22) +#define ESAI_RCCR_RCKD (1 << 21) +#define ESAI_RCCR_RHCKP (1 << 20) +#define ESAI_RCCR_RFSP (1 << 19) +#define ESAI_RCCR_RCKP (1 << 18) + +#define ESAI_RCCR_RPSR_MASK 0xfffeff +#define ESAI_RCCR_RPSR_BYPASS (1 << 8) +#define ESAI_RCCR_RPSR_DIV8 (0 << 8) + +#define ESAI_RCCR_RFP_MASK 0xfc3fff +#define ESAI_RCCR_RFP(x) ((x & 0xf) << 14) + +#define ESAI_RCCR_RDC_MASK 0xffc1ff +#define ESAI_RCCR_RDC(x) (((x) & 0x1f) << 9) + +#define ESAI_RCCR_RPM_MASK 0xffff00 +#define ESAI_RCCR_RPM(x) (x & 0xff) + +#define ESAI_GPIO_ESAI 0xfff + +/* ESAI clock source */ +#define ESAI_CLK_FSYS 0 +#define ESAI_CLK_EXTAL 1 + +/* ESAI clock divider */ +#define ESAI_TX_DIV_PSR 0 +#define ESAI_TX_DIV_PM 1 +#define ESAI_TX_DIV_FP 2 +#define ESAI_RX_DIV_PSR 3 +#define ESAI_RX_DIV_PM 4 +#define ESAI_RX_DIV_FP 5 + +#define IMX_DAI_ESAI_TX 0x04 +#define IMX_DAI_ESAI_RX 0x08 +#define IMX_DAI_ESAI_TXRX (IMX_DAI_ESAI_TX | IMX_DAI_ESAI_RX) + +struct imx_esai { + bool network_mode; + bool sync_mode; +}; + +extern struct snd_soc_dai imx_esai_dai[]; + +#endif diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/imx/imx-pcm.c new file mode 100644 index 000000000000..142e584ddf22 --- /dev/null +++ b/sound/soc/imx/imx-pcm.c @@ -0,0 +1,719 @@ +/* + * imx-pcm.c -- ALSA SoC interface for the Freescale i.MX3 CPU's + * + * Copyright 2006 Wolfson Microelectronics PLC. + * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com + * + * Based on imx31-pcm.c by Nicolas Pitre, (C) 2004 MontaVista Software, Inc. + * and on mxc-alsa-mc13783 (C) 2006 Freescale. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "imx-pcm.h" +#include "imx-ssi.h" +#include "imx-esai.h" + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) +#include +#include +#endif + +#ifdef CONFIG_SND_MXC_SOC_IRAM +static bool UseIram = 1; +#else +static bool UseIram; +#endif + +/* debug */ +#define IMX_PCM_DEBUG 0 +#if IMX_PCM_DEBUG +#define dbg(format, arg...) printk(format, ## arg) +#else +#define dbg(format, arg...) +#endif + +static const struct snd_pcm_hardware imx_pcm_hardware = { + .info = (SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .buffer_bytes_max = SND_RAM_SIZE, + .period_bytes_max = SND_RAM_SIZE / 4, +#else + .buffer_bytes_max = 64 * 1024, + .period_bytes_max = 16 * 1024, +#endif + .period_bytes_min = 2 * SZ_1K, + .periods_min = 2, + .periods_max = 255, + .fifo_size = 0, +}; + +static struct vm_operations_struct snd_mxc_audio_playback_vm_ops = { + .open = snd_pcm_mmap_data_open, + .close = snd_pcm_mmap_data_close, +}; + +/* + enable user space access to iram buffer +*/ +static int imx_iram_audio_playback_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *area) +{ + struct snd_dma_buffer *buf = &substream->dma_buffer; + unsigned long off; + unsigned long phys; + unsigned long size; + int ret = 0; + + area->vm_ops = &snd_mxc_audio_playback_vm_ops; + area->vm_private_data = substream; + + off = area->vm_pgoff << PAGE_SHIFT; + phys = buf->addr + off; + size = area->vm_end - area->vm_start; + + if (off + size > SND_RAM_SIZE) + return -EINVAL; + + area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); + area->vm_flags |= VM_IO; + ret = + remap_pfn_range(area, area->vm_start, phys >> PAGE_SHIFT, + size, area->vm_page_prot); + + return ret; +} + +static int imx_get_sdma_transfer(int format, int dai_port, + struct snd_pcm_substream *substream) +{ + int transfer = -1; + +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + if (prtd->asrc_enable == 1) { + if (dai_port == IMX_DAI_SSI0) { + if (prtd->asrc_index == 0) + transfer = MXC_DMA_ASRCA_SSI1_TX0; + else if (prtd->asrc_index == 1) + transfer = MXC_DMA_ASRCB_SSI1_TX0; + } else if (dai_port == IMX_DAI_SSI1) { + if (prtd->asrc_index == 0) + transfer = MXC_DMA_ASRCA_SSI1_TX1; + else if (prtd->asrc_index == 1) + transfer = MXC_DMA_ASRCB_SSI1_TX1; + } else if (dai_port == IMX_DAI_SSI2) { + if (prtd->asrc_index == 0) + transfer = MXC_DMA_ASRCA_SSI2_TX0; + else if (prtd->asrc_index == 1) + transfer = MXC_DMA_ASRCB_SSI2_TX0; + } else if (dai_port == IMX_DAI_SSI3) { + if (prtd->asrc_index == 0) + transfer = MXC_DMA_ASRCA_SSI2_TX1; + else if (prtd->asrc_index == 1) + transfer = MXC_DMA_ASRCB_SSI2_TX1; + } else if (dai_port & IMX_DAI_ESAI_TX) { + if (prtd->asrc_index == 0) + transfer = MXC_DMA_ASRCA_ESAI; + else if (prtd->asrc_index == 1) + transfer = MXC_DMA_ASRCB_ESAI; + else + transfer = MXC_DMA_ASRCC_ESAI; + } + } else { +#endif + + if (dai_port == IMX_DAI_SSI0) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI1_16BIT_TX0; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI1_24BIT_TX0; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI1_24BIT_TX0; + } else { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI1_16BIT_RX0; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI1_24BIT_RX0; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI1_24BIT_RX0; + } + } else if (dai_port == IMX_DAI_SSI1) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI1_16BIT_TX1; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI1_24BIT_TX1; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI1_24BIT_TX1; + } else { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI1_16BIT_RX1; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI1_24BIT_RX1; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI1_24BIT_RX1; + } + } else if (dai_port == IMX_DAI_SSI2) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI2_16BIT_TX0; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI2_24BIT_TX0; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI2_24BIT_TX0; + } else { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI2_16BIT_RX0; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI2_24BIT_RX0; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI2_24BIT_RX0; + } + } else if (dai_port == IMX_DAI_SSI3) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI2_16BIT_TX1; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI2_24BIT_TX1; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI2_24BIT_TX1; + } else { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI2_16BIT_RX1; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI2_24BIT_RX1; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI2_24BIT_RX1; + } + } else if (dai_port == IMX_DAI_SSI4) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI3_16BIT_TX0; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI3_24BIT_TX0; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI3_24BIT_TX0; + } else { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI3_16BIT_RX0; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI3_24BIT_RX0; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI3_24BIT_RX0; + } + } else if (dai_port == IMX_DAI_SSI5) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI3_16BIT_TX1; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI3_24BIT_TX1; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI3_24BIT_TX1; + } else { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_SSI3_16BIT_RX1; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_SSI3_24BIT_RX1; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_SSI3_24BIT_RX1; + } + } else if ((dai_port & IMX_DAI_ESAI_TX) + || (dai_port & IMX_DAI_ESAI_RX)) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_ESAI_16BIT_TX; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_ESAI_24BIT_TX; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_ESAI_24BIT_TX; + } else { + if (format == SNDRV_PCM_FORMAT_S16_LE) + transfer = MXC_DMA_ESAI_16BIT_RX; + else if (format == SNDRV_PCM_FORMAT_S24_LE) + transfer = MXC_DMA_ESAI_24BIT_RX; + else if (format == SNDRV_PCM_FORMAT_S20_3LE) + transfer = MXC_DMA_ESAI_24BIT_RX; + } + } +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + } +#endif + return transfer; +} + +static int dma_new_period(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + unsigned int dma_size = frames_to_bytes(runtime, runtime->period_size); + unsigned int offset = dma_size * prtd->period; + int ret = 0; + mxc_dma_requestbuf_t sdma_request; + + if (!prtd->active) + return 0; + + memset(&sdma_request, 0, sizeof(mxc_dma_requestbuf_t)); + + dbg("period pos ALSA %x DMA %x\n", runtime->periods, prtd->period); + dbg("period size ALSA %x DMA %x Offset %x dmasize %x\n", + (unsigned int)runtime->period_size, + runtime->dma_bytes, offset, dma_size); + dbg("DMA addr %x\n", runtime->dma_addr + offset); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + sdma_request.src_addr = + (dma_addr_t) (runtime->dma_addr + offset); + else + sdma_request.dst_addr = + (dma_addr_t) (runtime->dma_addr + offset); + + sdma_request.num_of_bytes = dma_size; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mxc_dma_config(prtd->dma_wchannel, + &sdma_request, 1, MXC_DMA_MODE_WRITE); + ret = mxc_dma_enable(prtd->dma_wchannel); + } else { + + mxc_dma_config(prtd->dma_wchannel, + &sdma_request, 1, MXC_DMA_MODE_READ); + ret = mxc_dma_enable(prtd->dma_wchannel); + } + prtd->dma_active = 1; + prtd->period++; + prtd->period %= runtime->periods; + + return ret; +} + +static void audio_dma_irq(void *data) +{ + struct snd_pcm_substream *substream = (struct snd_pcm_substream *)data; + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + + prtd->dma_active = 0; + prtd->periods++; + prtd->periods %= runtime->periods; + + dbg("irq per %d offset %x\n", prtd->periods, + frames_to_bytes(runtime, runtime->period_size) * prtd->periods); + + if (prtd->active) + snd_pcm_period_elapsed(substream); + dma_new_period(substream); +} + +static int imx_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + int ret = 0, channel = 0; + + if (prtd->dma_alloc) { + mxc_dma_free(prtd->dma_wchannel); + prtd->dma_alloc = 0; + } + + /* only allocate the DMA chn once */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (prtd->asrc_enable == 1) { + struct dma_channel_info info; + mxc_dma_requestbuf_t sdma_request; + info.asrc.channs = runtime->channels; + if (prtd->dma_asrc) { + mxc_dma_free(prtd->dma_asrc); + prtd->dma_asrc = 0; + } + memset(&sdma_request, 0, sizeof(mxc_dma_requestbuf_t)); + /* num_of_bytes can be set any value except for zero */ + sdma_request.num_of_bytes = 0x40; + channel = + mxc_dma_request_ext(prtd->dma_ch, + "ALSA TX SDMA", &info); + + mxc_dma_config(channel, &sdma_request, + 1, MXC_DMA_MODE_WRITE); + prtd->dma_asrc = channel; + if (prtd->asrc_index == 0) + prtd->dma_ch = MXC_DMA_ASRC_A_RX; + else if (prtd->asrc_index == 1) + prtd->dma_ch = MXC_DMA_ASRC_B_RX; + else + prtd->dma_ch = MXC_DMA_ASRC_C_RX; + + channel = + mxc_dma_request(MXC_DMA_ASRC_A_RX, "ALSA ASRC RX"); + } else + channel = mxc_dma_request(prtd->dma_ch, "ALSA TX SDMA"); +#else + channel = mxc_dma_request(prtd->dma_ch, "ALSA TX SDMA"); +#endif + if (channel < 0) { + pr_err("imx-pcm: error requesting \ + a write dma channel\n"); + return channel; + } + ret = mxc_dma_callback_set(channel, (mxc_dma_callback_t) + audio_dma_irq, (void *)substream); + + } else { + channel = mxc_dma_request(prtd->dma_ch, "ALSA RX SDMA"); + if (channel < 0) { + pr_err("imx-pcm: error requesting \ + a read dma channel\n"); + return channel; + } + ret = mxc_dma_callback_set(channel, (mxc_dma_callback_t) + audio_dma_irq, (void *)substream); + } + prtd->dma_wchannel = channel; + prtd->dma_alloc = 1; + + prtd->period = 0; + prtd->periods = 0; + return 0; +} + +static int imx_pcm_hw_params(struct snd_pcm_substream + *substream, struct snd_pcm_hw_params *params) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + + prtd->dma_ch = + imx_get_sdma_transfer(params_format(params), + rtd->dai->cpu_dai->id, substream); + + if (prtd->dma_ch < 0) { + printk(KERN_ERR "imx-pcm: invaild sdma transfer type"); + return -1; + } + + snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); + + return 0; +} + +static int imx_pcm_hw_free(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + + if (prtd->dma_wchannel) { + mxc_dma_free(prtd->dma_wchannel); + prtd->dma_wchannel = 0; + prtd->dma_alloc = 0; + } +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if ((prtd->asrc_enable == 1) && prtd->dma_asrc) { + mxc_dma_free(prtd->dma_asrc); + prtd->dma_asrc = 0; + } +#endif + + return 0; +} + +static int imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct mxc_runtime_data *prtd = substream->runtime->private_data; + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + prtd->dma_active = 0; + prtd->active = 1; + ret = dma_new_period(substream); + ret = dma_new_period(substream); +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (prtd->asrc_enable == 1) { + ret = mxc_dma_enable(prtd->dma_asrc); + asrc_start_conv(prtd->asrc_index); + /* There is underrun, if immediately enable SSI after + start ASRC */ + mdelay(1); + } +#endif + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + prtd->active = 0; +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + if (prtd->asrc_enable == 1) { + mxc_dma_disable(prtd->dma_asrc); + asrc_stop_conv(prtd->asrc_index); + } +#endif + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static snd_pcm_uframes_t imx_pcm_pointer(struct + snd_pcm_substream + *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + unsigned int offset = 0; + + offset = (runtime->period_size * (prtd->periods)); + if (offset >= runtime->buffer_size) + offset = 0; + dbg("pointer offset %x\n", offset); + + return offset; +} + +static int imx_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd; + int ret; + + snd_soc_set_runtime_hwparams(substream, &imx_pcm_hardware); + + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) + return ret; + + prtd = kzalloc(sizeof(struct mxc_runtime_data), GFP_KERNEL); + if (prtd == NULL) + return -ENOMEM; + + runtime->private_data = prtd; + return 0; +} + +static int imx_pcm_close(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxc_runtime_data *prtd = runtime->private_data; + + kfree(prtd); + return 0; +} + +static int +imx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_dai *cpu_dai = socdev->card->dai_link->cpu_dai; + struct mxc_audio_platform_data *dev_data; + int ext_ram = 0; + int ret = 0; + + dbg("+imx_pcm_mmap:" + "UseIram=%d dma_addr=%x dma_area=%x dma_bytes=%d\n", + UseIram, (unsigned int)runtime->dma_addr, + runtime->dma_area, runtime->dma_bytes); + + if (cpu_dai->dev && cpu_dai->dev->platform_data) { + dev_data = cpu_dai->dev->platform_data; + ext_ram = dev_data->ext_ram; + } + + if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE) + || ext_ram || !UseIram) { + ret = + dma_mmap_writecombine(substream->pcm->card-> + dev, vma, + runtime->dma_area, + runtime->dma_addr, + runtime->dma_bytes); + return ret; + } else + return imx_iram_audio_playback_mmap(substream, vma); +} + +struct snd_pcm_ops imx_pcm_ops = { + .open = imx_pcm_open, + .close = imx_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = imx_pcm_hw_params, + .hw_free = imx_pcm_hw_free, + .prepare = imx_pcm_prepare, + .trigger = imx_pcm_trigger, + .pointer = imx_pcm_pointer, + .mmap = imx_pcm_mmap, +}; + +static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) +{ + struct snd_pcm_substream *substream = pcm->streams[stream].substream; + struct snd_dma_buffer *buf = &substream->dma_buffer; + struct snd_soc_pcm_runtime *rtd = pcm->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_dai *cpu_dai = socdev->card->dai_link->cpu_dai; + struct mxc_audio_platform_data *dev_data; + unsigned long buf_paddr; + int ext_ram = 0; + size_t size = imx_pcm_hardware.buffer_bytes_max; + + if (cpu_dai->dev && cpu_dai->dev->platform_data) { + dev_data = cpu_dai->dev->platform_data; + ext_ram = dev_data->ext_ram; + } + + buf->dev.type = SNDRV_DMA_TYPE_DEV; + buf->dev.dev = pcm->card->dev; + buf->private_data = NULL; + + if ((stream == SNDRV_PCM_STREAM_CAPTURE) || ext_ram || !UseIram) + buf->area = + dma_alloc_writecombine(pcm->card->dev, size, + &buf->addr, GFP_KERNEL); + else { + buf->area = iram_alloc(size, &buf_paddr); + buf->addr = buf_paddr; + + if (!buf->area) { + pr_warning("imx-pcm: Falling back to external ram.\n"); + UseIram = 0; + buf->area = + dma_alloc_writecombine(pcm->card->dev, size, + &buf->addr, GFP_KERNEL); + } + } + + if (!buf->area) + return -ENOMEM; + buf->bytes = size; + printk(KERN_INFO "DMA Sound Buffers Allocated:" + "UseIram=%d buf->addr=%x buf->area=%p size=%d\n", + UseIram, buf->addr, buf->area, size); + return 0; +} + +static void imx_pcm_free_dma_buffers(struct snd_pcm *pcm) +{ + struct snd_pcm_substream *substream; + struct snd_dma_buffer *buf; + struct snd_soc_pcm_runtime *rtd = pcm->private_data; + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_dai *cpu_dai = socdev->card->dai_link->cpu_dai; + struct mxc_audio_platform_data *dev_data; + int ext_ram = 0; + int stream; + + if (cpu_dai->dev && cpu_dai->dev->platform_data) { + dev_data = cpu_dai->dev->platform_data; + ext_ram = dev_data->ext_ram; + } + + for (stream = 0; stream < 2; stream++) { + substream = pcm->streams[stream].substream; + if (!substream) + continue; + + buf = &substream->dma_buffer; + if (!buf->area) + continue; + + if ((stream == SNDRV_PCM_STREAM_CAPTURE) + || ext_ram || !UseIram) + dma_free_writecombine(pcm->card->dev, + buf->bytes, buf->area, buf->addr); + else { + iram_free(buf->addr, imx_pcm_hardware.buffer_bytes_max); + } + buf->area = NULL; + } +} + +static u64 imx_pcm_dmamask = 0xffffffff; + +static int imx_pcm_new(struct snd_card *card, + struct snd_soc_dai *dai, struct snd_pcm *pcm) +{ + int ret = 0; + + if (!card->dev->dma_mask) + card->dev->dma_mask = &imx_pcm_dmamask; + if (!card->dev->coherent_dma_mask) + card->dev->coherent_dma_mask = 0xffffffff; + + if (dai->playback.channels_min) { + ret = imx_pcm_preallocate_dma_buffer(pcm, + SNDRV_PCM_STREAM_PLAYBACK); + if (ret) + goto out; + } + + if (dai->capture.channels_min) { + ret = imx_pcm_preallocate_dma_buffer(pcm, + SNDRV_PCM_STREAM_CAPTURE); + if (ret) + goto out; + } + out: + return ret; +} + +struct snd_soc_platform imx_soc_platform = { + .name = "imx-audio", + .pcm_ops = &imx_pcm_ops, + .pcm_new = imx_pcm_new, + .pcm_free = imx_pcm_free_dma_buffers, +}; +EXPORT_SYMBOL_GPL(imx_soc_platform); + +static int __init imx_pcm_init(void) +{ + return snd_soc_register_platform(&imx_soc_platform); +} +module_init(imx_pcm_init); + +static void __exit imx_pcm_exit(void) +{ + snd_soc_unregister_platform(&imx_soc_platform); +} +module_exit(imx_pcm_exit); + +MODULE_AUTHOR("Liam Girdwood"); +MODULE_DESCRIPTION("Freescale i.MX3x PCM DMA module"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/imx/imx-pcm.h new file mode 100644 index 000000000000..5a7efa171a71 --- /dev/null +++ b/sound/soc/imx/imx-pcm.h @@ -0,0 +1,83 @@ +/* + * imx-pcm.h :- ASoC platform header for Freescale i.MX + * + * Copyright 2006 Wolfson Microelectronics PLC. + * Copyright 2006, 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MXC_PCM_H +#define _MXC_PCM_H + +#include + +/* AUDMUX regs definition */ +#define AUDMUX_IO_BASE_ADDR IO_ADDRESS(AUDMUX_BASE_ADDR) + +#define DAM_PTCR1 ((AUDMUX_IO_BASE_ADDR) + 0x00) +#define DAM_PDCR1 ((AUDMUX_IO_BASE_ADDR) + 0x04) +#define DAM_PTCR2 ((AUDMUX_IO_BASE_ADDR) + 0x08) +#define DAM_PDCR2 ((AUDMUX_IO_BASE_ADDR) + 0x0C) +#define DAM_PTCR3 ((AUDMUX_IO_BASE_ADDR) + 0x10) +#define DAM_PDCR3 ((AUDMUX_IO_BASE_ADDR) + 0x14) +#define DAM_PTCR4 ((AUDMUX_IO_BASE_ADDR) + 0x18) +#define DAM_PDCR4 ((AUDMUX_IO_BASE_ADDR) + 0x1C) +#define DAM_PTCR5 ((AUDMUX_IO_BASE_ADDR) + 0x20) +#define DAM_PDCR5 ((AUDMUX_IO_BASE_ADDR) + 0x24) +#define DAM_PTCR6 ((AUDMUX_IO_BASE_ADDR) + 0x28) +#define DAM_PDCR6 ((AUDMUX_IO_BASE_ADDR) + 0x2C) +#define DAM_PTCR7 ((AUDMUX_IO_BASE_ADDR) + 0x30) +#define DAM_PDCR7 ((AUDMUX_IO_BASE_ADDR) + 0x34) +#define DAM_CNMCR ((AUDMUX_IO_BASE_ADDR) + 0x38) +#define DAM_PTCR(a) ((AUDMUX_IO_BASE_ADDR) + (a-1)*8) +#define DAM_PDCR(a) ((AUDMUX_IO_BASE_ADDR) + 4 + (a-1)*8) + +#define AUDMUX_PTCR_TFSDIR (1 << 31) +#define AUDMUX_PTCR_TFSSEL(x, y) \ + ((x << 30) | (((y - 1) & 0x7) << 27)) +#define AUDMUX_PTCR_TCLKDIR (1 << 26) +#define AUDMUX_PTCR_TCSEL(x, y) \ + ((x << 25) | (((y - 1) & 0x7) << 22)) +#define AUDMUX_PTCR_RFSDIR (1 << 21) +#define AUDMUX_PTCR_RFSSEL(x, y) \ + ((x << 20) | (((y - 1) & 0x7) << 17)) +#define AUDMUX_PTCR_RCLKDIR (1 << 16) +#define AUDMUX_PTCR_RCSEL(x, y) \ + ((x << 15) | (((y - 1) & 0x7) << 12)) +#define AUDMUX_PTCR_SYN (1 << 11) + +#define AUDMUX_FROM_TXFS 0 +#define AUDMUX_FROM_RXFS 1 + +#define AUDMUX_PDCR_RXDSEL(x) (((x - 1) & 0x7) << 13) +#define AUDMUX_PDCR_TXDXEN (1 << 12) +#define AUDMUX_PDCR_MODE(x) (((x) & 0x3) << 8) +#define AUDMUX_PDCR_INNMASK(x) (((x) & 0xff) << 0) + +#define AUDMUX_CNMCR_CEN (1 << 18) +#define AUDMUX_CNMCR_FSPOL (1 << 17) +#define AUDMUX_CNMCR_CLKPOL (1 << 16) +#define AUDMUX_CNMCR_CNTHI(x) (((x) & 0xff) << 8) +#define AUDMUX_CNMCR_CNTLOW(x) (((x) & 0xff) << 0) + + +struct mxc_runtime_data { + int dma_ch; + spinlock_t dma_lock; + int active, period, periods; + int dma_wchannel; + int dma_active; + int dma_alloc; +#if defined(CONFIG_MXC_ASRC) || defined(CONFIG_MXC_ASRC_MODULE) + int dma_asrc; + int asrc_index; + int asrc_enable; +#endif +}; + +extern struct snd_soc_platform imx_soc_platform; + +#endif diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c index 80b4fee2442b..372854a75caf 100644 --- a/sound/soc/imx/imx-ssi.c +++ b/sound/soc/imx/imx-ssi.c @@ -1,81 +1,227 @@ /* - * imx-ssi.c -- ALSA Soc Audio Layer + * imx-ssi.c -- SSI driver for Freescale IMX * - * Copyright 2009 Sascha Hauer + * Copyright 2006 Wolfson Microelectronics PLC. + * Author: Liam Girdwood + * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com * - * This code is based on code copyrighted by Freescale, - * Liam Girdwood, Javier Martin and probably others. + * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. + * Based on mxc-alsa-mc13783 * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * + * Revision history + * 29th Aug 2006 Initial version. + * + * TODO: + * Need to rework SSI register defs when new defs go into mainline. + * Add support for TDM and FIFO 1. * - * The i.MX SSI core has some nasty limitations in AC97 mode. While most - * sane processor vendors have a FIFO per AC97 slot, the i.MX has only - * one FIFO which combines all valid receive slots. We cannot even select - * which slots we want to receive. The WM9712 with which this driver - * was developped with always sends GPIO status data in slot 12 which - * we receive in our (PCM-) data stream. The only chance we have is to - * manually skip this data in the FIQ handler. With sampling rates different - * from 48000Hz not every frame has valid receive data, so the ratio - * between pcm data and GPIO status data changes. Our FIQ handler is not - * able to handle this, hence this driver only works with 48000Hz sampling - * rate. - * Reading and writing AC97 registers is another challange. The core - * provides us status bits when the read register is updated with *another* - * value. When we read the same register two times (and the register still - * contains the same value) these status bits are not set. We work - * around this by not polling these bits but only wait a fixed delay. - * */ -#include -#include -#include -#include -#include -#include #include +#include #include #include - +#include +#include #include -#include #include #include #include - -#include +#include +#include +#include #include #include "imx-ssi.h" +#include "imx-pcm.h" + +#define SSI_STX0 (0x00) +#define SSI_STX1 (0x04) +#define SSI_SRX0 (0x08) +#define SSI_SRX1 (0x0c) +#define SSI_SCR (0x10) +#define SSI_SISR (0x14) +#define SSI_SIER (0x18) +#define SSI_STCR (0x1c) +#define SSI_SRCR (0x20) +#define SSI_STCCR (0x24) +#define SSI_SRCCR (0x28) +#define SSI_SFCSR (0x2c) +#define SSI_STR (0x30) +#define SSI_SOR (0x34) +#define SSI_SACNT (0x38) +#define SSI_SACADD (0x3c) +#define SSI_SACDAT (0x40) +#define SSI_SATAG (0x44) +#define SSI_STMSK (0x48) +#define SSI_SRMSK (0x4c) +#define SSI_SACCST (0x50) +#define SSI_SACCEN (0x54) +#define SSI_SACCDIS (0x58) + +/* debug */ +#define IMX_SSI_DEBUG 0 +#if IMX_SSI_DEBUG +#define dbg(format, arg...) printk(format, ## arg) +#else +#define dbg(format, arg...) +#endif + +#define IMX_SSI_DUMP 0 +#if IMX_SSI_DUMP +#define SSI_DUMP() \ + do { \ + printk(KERN_INFO "dump @ %s\n", __func__); \ + printk(KERN_INFO "scr %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_SCR), \ + __raw_readl(ioaddr + SSI_SCR)); \ + printk(KERN_INFO "sisr %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_SISR), \ + __raw_readl(ioaddr + SSI_SISR)); \ + printk(KERN_INFO "stcr %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_STCR), \ + __raw_readl(ioaddr + SSI_STCR)); \ + printk(KERN_INFO "srcr %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_SRCR), \ + __raw_readl(ioaddr + SSI_SRCR)); \ + printk(KERN_INFO "stccr %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_STCCR), \ + __raw_readl(ioaddr + SSI_STCCR)); \ + printk(KERN_INFO "srccr %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_SRCCR), \ + __raw_readl(ioaddr + SSI_SRCCR)); \ + printk(KERN_INFO "sfcsr %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_SFCSR), \ + __raw_readl(ioaddr + SSI_SFCSR)); \ + printk(KERN_INFO "stmsk %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_STMSK), \ + __raw_readl(ioaddr + SSI_STMSK)); \ + printk(KERN_INFO "srmsk %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_SRMSK), \ + __raw_readl(ioaddr + SSI_SRMSK)); \ + printk(KERN_INFO "sier %x\t, %x\n", \ + __raw_readl(ioaddr + SSI_SIER), \ + __raw_readl(ioaddr + SSI_SIER)); \ + } while (0); +#else +#define SSI_DUMP() +#endif + +/* + * SSI system clock configuration. + * Should only be called when port is inactive (i.e. SSIEN = 0). + */ +static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, + int clk_id, unsigned int freq, int dir) +{ + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + u32 scr; + + scr = __raw_readl(ioaddr + SSI_SCR); + + if (scr & SSI_SCR_SSIEN) + return 0; + + switch (clk_id) { + case IMX_SSP_SYS_CLK: + if (dir == SND_SOC_CLOCK_OUT) + scr |= SSI_SCR_SYS_CLK_EN; + else + scr &= ~SSI_SCR_SYS_CLK_EN; + break; + default: + return -EINVAL; + } + + __raw_writel(scr, ioaddr + SSI_SCR); + + return 0; +} + +/* + * SSI Clock dividers + * Should only be called when port is inactive (i.e. SSIEN = 0). + */ +static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, + int div_id, int div) +{ + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + u32 stccr, srccr; + + if (__raw_readl(ioaddr + SSI_SCR) & SSI_SCR_SSIEN) + return 0; + + srccr = __raw_readl(ioaddr + SSI_SRCCR); + stccr = __raw_readl(ioaddr + SSI_STCCR); + + switch (div_id) { + case IMX_SSI_TX_DIV_2: + stccr &= ~SSI_STCCR_DIV2; + stccr |= div; + break; + case IMX_SSI_TX_DIV_PSR: + stccr &= ~SSI_STCCR_PSR; + stccr |= div; + break; + case IMX_SSI_TX_DIV_PM: + stccr &= ~0xff; + stccr |= SSI_STCCR_PM(div); + break; + case IMX_SSI_RX_DIV_2: + stccr &= ~SSI_STCCR_DIV2; + stccr |= div; + break; + case IMX_SSI_RX_DIV_PSR: + stccr &= ~SSI_STCCR_PSR; + stccr |= div; + break; + case IMX_SSI_RX_DIV_PM: + stccr &= ~0xff; + stccr |= SSI_STCCR_PM(div); + break; + default: + return -EINVAL; + } -#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV) + __raw_writel(stccr, ioaddr + SSI_STCCR); + __raw_writel(srccr, ioaddr + SSI_SRCCR); + + return 0; +} /* * SSI Network Mode or TDM slots configuration. * Should only be called when port is inactive (i.e. SSIEN = 0). */ static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, - unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) + unsigned int tx_mask, + unsigned int rx_mask, + int slots, int slot_width) { - struct imx_ssi *ssi = cpu_dai->private_data; - u32 sccr; + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + u32 stmsk, srmsk, stccr; - sccr = readl(ssi->base + SSI_STCCR); - sccr &= ~SSI_STCCR_DC_MASK; - sccr |= SSI_STCCR_DC(slots - 1); - writel(sccr, ssi->base + SSI_STCCR); + if (__raw_readl(ioaddr + SSI_SCR) & SSI_SCR_SSIEN) + return 0; + stccr = __raw_readl(ioaddr + SSI_STCCR); - sccr = readl(ssi->base + SSI_SRCCR); - sccr &= ~SSI_STCCR_DC_MASK; - sccr |= SSI_STCCR_DC(slots - 1); - writel(sccr, ssi->base + SSI_SRCCR); + stmsk = tx_mask; + srmsk = rx_mask; + stccr &= ~SSI_STCCR_DC_MASK; + stccr |= SSI_STCCR_DC(slots - 1); - writel(tx_mask, ssi->base + SSI_STMSK); - writel(rx_mask, ssi->base + SSI_SRMSK); + __raw_writel(stmsk, ioaddr + SSI_STMSK); + __raw_writel(srmsk, ioaddr + SSI_SRMSK); + __raw_writel(stccr, ioaddr + SSI_STCCR); + __raw_writel(stccr, ioaddr + SSI_SRCCR); return 0; } @@ -84,144 +230,231 @@ static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, * SSI DAI format configuration. * Should only be called when port is inactive (i.e. SSIEN = 0). * Note: We don't use the I2S modes but instead manually configure the - * SSI for I2S because the I2S mode is only a register preset. + * SSI for I2S. */ static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) { - struct imx_ssi *ssi = cpu_dai->private_data; - u32 strcr = 0, scr; + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + u32 stcr = 0, srcr = 0, scr; - scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET); + scr = __raw_readl(ioaddr + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET); + + if (scr & SSI_SCR_SSIEN) + return 0; /* DAI mode */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: /* data on rising edge of bclk, frame low 1clk before data */ - strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; - scr |= SSI_SCR_NET; + stcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; + srcr |= SSI_SRCR_RFSI | SSI_SRCR_REFS | SSI_SRCR_RXBIT0; break; case SND_SOC_DAIFMT_LEFT_J: /* data on rising edge of bclk, frame high with data */ - strcr |= SSI_STCR_TXBIT0; + stcr |= SSI_STCR_TXBIT0; + srcr |= SSI_SRCR_RXBIT0; break; case SND_SOC_DAIFMT_DSP_B: /* data on rising edge of bclk, frame high with data */ - strcr |= SSI_STCR_TFSL; + stcr |= SSI_STCR_TFSL; + srcr |= SSI_SRCR_RFSL; break; case SND_SOC_DAIFMT_DSP_A: /* data on rising edge of bclk, frame high 1clk before data */ - strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS; + stcr |= SSI_STCR_TFSL | SSI_STCR_TEFS; + srcr |= SSI_SRCR_RFSL | SSI_SRCR_REFS; break; } /* DAI clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_IB_IF: - strcr |= SSI_STCR_TFSI; - strcr &= ~SSI_STCR_TSCKP; + stcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI); + srcr &= ~(SSI_SRCR_RSCKP | SSI_SRCR_RFSI); break; case SND_SOC_DAIFMT_IB_NF: - strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI); + stcr |= SSI_STCR_TFSI; + stcr &= ~SSI_STCR_TSCKP; + srcr |= SSI_SRCR_RFSI; + srcr &= ~SSI_SRCR_RSCKP; break; case SND_SOC_DAIFMT_NB_IF: - strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP; + stcr &= ~SSI_STCR_TFSI; + stcr |= SSI_STCR_TSCKP; + srcr &= ~SSI_SRCR_RFSI; + srcr |= SSI_SRCR_RSCKP; break; case SND_SOC_DAIFMT_NB_NF: - strcr &= ~SSI_STCR_TFSI; - strcr |= SSI_STCR_TSCKP; + stcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP; + srcr |= SSI_SRCR_RFSI | SSI_SRCR_RSCKP; break; } /* DAI clock master masks */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + stcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; + if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) + && priv->network_mode) { + scr &= ~SSI_SCR_I2S_MODE_MASK; + scr |= SSI_SCR_I2S_MODE_MSTR; + } + break; + case SND_SOC_DAIFMT_CBM_CFS: + stcr |= SSI_STCR_TFDIR; + srcr |= SSI_SRCR_RFDIR; + break; + case SND_SOC_DAIFMT_CBS_CFM: + stcr |= SSI_STCR_TXDIR; + srcr |= SSI_SRCR_RXDIR; + break; case SND_SOC_DAIFMT_CBM_CFM: + if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) + && priv->network_mode) { + scr &= ~SSI_SCR_I2S_MODE_MASK; + scr |= SSI_SCR_I2S_MODE_SLAVE; + } break; - default: - /* Master mode not implemented, needs handling of clocks. */ - return -EINVAL; } - strcr |= SSI_STCR_TFEN0; + /* sync */ + if (priv->sync_mode) + scr |= SSI_SCR_SYN; - writel(strcr, ssi->base + SSI_STCR); - writel(strcr, ssi->base + SSI_SRCR); - writel(scr, ssi->base + SSI_SCR); + /* tdm - only for stereo atm */ + if (priv->network_mode) + scr |= SSI_SCR_NET; +#ifdef CONFIG_MXC_SSI_DUAL_FIFO + if (cpu_is_mx51() || cpu_is_mx53()) { + stcr |= SSI_STCR_TFEN1; + srcr |= SSI_SRCR_RFEN1; + scr |= SSI_SCR_TCH_EN; + } +#endif + __raw_writel(stcr, ioaddr + SSI_STCR); + __raw_writel(srcr, ioaddr + SSI_SRCR); + __raw_writel(scr, ioaddr + SSI_SCR); + SSI_DUMP(); return 0; } -/* - * SSI system clock configuration. - * Should only be called when port is inactive (i.e. SSIEN = 0). - */ -static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, - int clk_id, unsigned int freq, int dir) +static int imx_ssi_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) { - struct imx_ssi *ssi = cpu_dai->private_data; - u32 scr; - - scr = readl(ssi->base + SSI_SCR); - - switch (clk_id) { - case IMX_SSP_SYS_CLK: - if (dir == SND_SOC_CLOCK_OUT) - scr |= SSI_SCR_SYS_CLK_EN; - else - scr &= ~SSI_SCR_SYS_CLK_EN; - break; - default: - return -EINVAL; + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + + /* we cant really change any SSI values after SSI is enabled + * need to fix in software for max flexibility - lrg */ + if (cpu_dai->playback.active || cpu_dai->capture.active) + return 0; + + /* reset the SSI port - Sect 45.4.4 */ + if (clk_get_usecount(priv->ssi_clk) != 0) { + clk_enable(priv->ssi_clk); + return 0; } - writel(scr, ssi->base + SSI_SCR); + __raw_writel(0, ioaddr + SSI_SCR); + clk_enable(priv->ssi_clk); + + /* BIG FAT WARNING + * SDMA FIFO watermark must == SSI FIFO watermark for best results. + */ + __raw_writel((SSI_SFCSR_RFWM1(SSI_RXFIFO_WATERMARK) | + SSI_SFCSR_RFWM0(SSI_RXFIFO_WATERMARK) | + SSI_SFCSR_TFWM1(SSI_TXFIFO_WATERMARK) | + SSI_SFCSR_TFWM0(SSI_TXFIFO_WATERMARK)), + ioaddr + SSI_SFCSR); + __raw_writel(0, ioaddr + SSI_SIER); + SSI_DUMP(); return 0; } -/* - * SSI Clock dividers - * Should only be called when port is inactive (i.e. SSIEN = 0). - */ -static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, - int div_id, int div) +static int imx_ssi_hw_tx_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) { - struct imx_ssi *ssi = cpu_dai->private_data; - u32 stccr, srccr; + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + u32 stccr, stcr, sier; - stccr = readl(ssi->base + SSI_STCCR); - srccr = readl(ssi->base + SSI_SRCCR); + stccr = __raw_readl(ioaddr + SSI_STCCR) & ~SSI_STCCR_WL_MASK; + stcr = __raw_readl(ioaddr + SSI_STCR); + sier = __raw_readl(ioaddr + SSI_SIER); - switch (div_id) { - case IMX_SSI_TX_DIV_2: - stccr &= ~SSI_STCCR_DIV2; - stccr |= div; + /* DAI data (word) size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + stccr |= SSI_STCCR_WL(16); break; - case IMX_SSI_TX_DIV_PSR: - stccr &= ~SSI_STCCR_PSR; - stccr |= div; + case SNDRV_PCM_FORMAT_S20_3LE: + stccr |= SSI_STCCR_WL(20); break; - case IMX_SSI_TX_DIV_PM: - stccr &= ~0xff; - stccr |= SSI_STCCR_PM(div); + case SNDRV_PCM_FORMAT_S24_LE: + stccr |= SSI_STCCR_WL(24); break; - case IMX_SSI_RX_DIV_2: - stccr &= ~SSI_STCCR_DIV2; - stccr |= div; + } + + /* enable interrupts */ + if ((cpu_dai->id & 0x1) == 0) + stcr |= SSI_STCR_TFEN0; + else + stcr |= SSI_STCR_TFEN1; + sier |= SSI_SIER_TDMAE | SSI_SIER_TIE | SSI_SIER_TUE0_EN; + + __raw_writel(stcr, ioaddr + SSI_STCR); + __raw_writel(stccr, ioaddr + SSI_STCCR); + __raw_writel(sier, ioaddr + SSI_SIER); + + return 0; +} + +static int imx_ssi_hw_rx_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) +{ + u32 srccr, srcr, sier; + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + bool sync_mode = priv->sync_mode; + + srccr = + sync_mode ? __raw_readl(ioaddr + SSI_STCCR) : + __raw_readl(ioaddr + SSI_SRCCR); + srcr = __raw_readl(ioaddr + SSI_SRCR); + sier = __raw_readl(ioaddr + SSI_SIER); + srccr &= ~SSI_SRCCR_WL_MASK; + + /* DAI data (word) size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + srccr |= SSI_SRCCR_WL(16); break; - case IMX_SSI_RX_DIV_PSR: - stccr &= ~SSI_STCCR_PSR; - stccr |= div; + case SNDRV_PCM_FORMAT_S20_3LE: + srccr |= SSI_SRCCR_WL(20); break; - case IMX_SSI_RX_DIV_PM: - stccr &= ~0xff; - stccr |= SSI_STCCR_PM(div); + case SNDRV_PCM_FORMAT_S24_LE: + srccr |= SSI_SRCCR_WL(24); break; - default: - return -EINVAL; } - writel(stccr, ssi->base + SSI_STCCR); - writel(srccr, ssi->base + SSI_SRCCR); + /* enable interrupts */ + if ((cpu_dai->id & 0x1) == 0) + srcr |= SSI_SRCR_RFEN0; + else + srcr |= SSI_SRCR_RFEN1; + sier |= SSI_SIER_RDMAE | SSI_SIER_RIE | SSI_SIER_ROE0_EN; + + __raw_writel(srcr, ioaddr + SSI_SRCR); + if (sync_mode) + __raw_writel(srccr, ioaddr + SSI_STCCR); + else + __raw_writel(srccr, ioaddr + SSI_SRCCR); + __raw_writel(sier, ioaddr + SSI_SIER); return 0; } @@ -234,530 +467,327 @@ static int imx_ssi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *cpu_dai) { - struct imx_ssi *ssi = cpu_dai->private_data; - struct imx_pcm_dma_params *dma_data; - u32 reg, sccr; + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + int id; + + id = cpu_dai->id; /* Tx/Rx config */ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - reg = SSI_STCCR; - dma_data = &ssi->dma_params_tx; + /* cant change any parameters when SSI is running */ + if ((__raw_readl(ioaddr + SSI_SCR) & SSI_SCR_SSIEN) && + (__raw_readl(ioaddr + SSI_SCR) & SSI_SCR_TE)) + return 0; + return imx_ssi_hw_tx_params(substream, params, cpu_dai); } else { - reg = SSI_SRCCR; - dma_data = &ssi->dma_params_rx; + /* cant change any parameters when SSI is running */ + if ((__raw_readl(ioaddr + SSI_SCR) & SSI_SCR_SSIEN) && + (__raw_readl(ioaddr + SSI_SCR) & SSI_SCR_RE)) + return 0; + return imx_ssi_hw_rx_params(substream, params, cpu_dai); } +} - snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); - - sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK; - - /* DAI data (word) size */ - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S16_LE: - sccr |= SSI_SRCCR_WL(16); - break; - case SNDRV_PCM_FORMAT_S20_3LE: - sccr |= SSI_SRCCR_WL(20); - break; - case SNDRV_PCM_FORMAT_S24_LE: - sccr |= SSI_SRCCR_WL(24); - break; - } +static int imx_ssi_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + u32 scr; - writel(sccr, ssi->base + reg); + /* enable the SSI port, note that no other port config + * should happen after SSIEN is set */ + scr = __raw_readl(ioaddr + SSI_SCR); + __raw_writel((scr | SSI_SCR_SSIEN), ioaddr + SSI_SCR); + SSI_DUMP(); return 0; } static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd, - struct snd_soc_dai *dai) + struct snd_soc_dai *cpu_dai) { - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; - struct imx_ssi *ssi = cpu_dai->private_data; - unsigned int sier_bits, sier; - unsigned int scr; + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + u32 scr; - scr = readl(ssi->base + SSI_SCR); - sier = readl(ssi->base + SSI_SIER); - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - if (ssi->flags & IMX_SSI_DMA) - sier_bits = SSI_SIER_TDMAE; - else - sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN; - } else { - if (ssi->flags & IMX_SSI_DMA) - sier_bits = SSI_SIER_RDMAE; - else - sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN; - } + scr = __raw_readl(ioaddr + SSI_SCR); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (scr & SSI_SCR_RE) { + __raw_writel(0, ioaddr + SSI_SCR); + } scr |= SSI_SCR_TE; - else + } else scr |= SSI_SCR_RE; - sier |= sier_bits; - - if (++ssi->enabled == 1) - scr |= SSI_SCR_SSIEN; - break; - - case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) scr &= ~SSI_SCR_TE; else scr &= ~SSI_SCR_RE; - sier &= ~sier_bits; - - if (--ssi->enabled == 0) - scr &= ~SSI_SCR_SSIEN; - break; default: return -EINVAL; } + __raw_writel(scr, ioaddr + SSI_SCR); - if (!(ssi->flags & IMX_SSI_USE_AC97)) - /* rx/tx are always enabled to access ac97 registers */ - writel(scr, ssi->base + SSI_SCR); - - writel(sier, ssi->base + SSI_SIER); - + SSI_DUMP(); return 0; } -static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = { - .hw_params = imx_ssi_hw_params, - .set_fmt = imx_ssi_set_dai_fmt, - .set_clkdiv = imx_ssi_set_dai_clkdiv, - .set_sysclk = imx_ssi_set_dai_sysclk, - .set_tdm_slot = imx_ssi_set_dai_tdm_slot, - .trigger = imx_ssi_trigger, -}; - -static struct snd_soc_dai imx_ssi_dai = { - .playback = { - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_96000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .capture = { - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_96000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .ops = &imx_ssi_pcm_dai_ops, -}; - -int snd_imx_pcm_mmap(struct snd_pcm_substream *substream, - struct vm_area_struct *vma) -{ - struct snd_pcm_runtime *runtime = substream->runtime; - int ret; - - ret = dma_mmap_coherent(NULL, vma, runtime->dma_area, - runtime->dma_addr, runtime->dma_bytes); - - pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret, - runtime->dma_area, - runtime->dma_addr, - runtime->dma_bytes); - return ret; -} - -static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) +static void imx_ssi_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) { - struct snd_pcm_substream *substream = pcm->streams[stream].substream; - struct snd_dma_buffer *buf = &substream->dma_buffer; - size_t size = IMX_SSI_DMABUF_SIZE; - - buf->dev.type = SNDRV_DMA_TYPE_DEV; - buf->dev.dev = pcm->card->dev; - buf->private_data = NULL; - buf->area = dma_alloc_writecombine(pcm->card->dev, size, - &buf->addr, GFP_KERNEL); - if (!buf->area) - return -ENOMEM; - buf->bytes = size; + struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; + void __iomem *ioaddr = priv->ioaddr; + int id; - return 0; -} + id = cpu_dai->id; -static u64 imx_pcm_dmamask = DMA_BIT_MASK(32); - -int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm) -{ + /* shutdown SSI if neither Tx or Rx is active */ + if (cpu_dai->playback.active || cpu_dai->capture.active) + return; - int ret = 0; - - if (!card->dev->dma_mask) - card->dev->dma_mask = &imx_pcm_dmamask; - if (!card->dev->coherent_dma_mask) - card->dev->coherent_dma_mask = DMA_BIT_MASK(32); - if (dai->playback.channels_min) { - ret = imx_pcm_preallocate_dma_buffer(pcm, - SNDRV_PCM_STREAM_PLAYBACK); - if (ret) - goto out; + if (clk_get_usecount(priv->ssi_clk) > 1) { + clk_disable(priv->ssi_clk); + return; } - if (dai->capture.channels_min) { - ret = imx_pcm_preallocate_dma_buffer(pcm, - SNDRV_PCM_STREAM_CAPTURE); - if (ret) - goto out; - } + __raw_writel(0, ioaddr + SSI_SCR); -out: - return ret; + clk_disable(priv->ssi_clk); } -void imx_pcm_free(struct snd_pcm *pcm) +#ifdef CONFIG_PM +static int imx_ssi_suspend(struct snd_soc_dai *dai) { - struct snd_pcm_substream *substream; - struct snd_dma_buffer *buf; - int stream; - - for (stream = 0; stream < 2; stream++) { - substream = pcm->streams[stream].substream; - if (!substream) - continue; - - buf = &substream->dma_buffer; - if (!buf->area) - continue; - - dma_free_writecombine(pcm->card->dev, buf->bytes, - buf->area, buf->addr); - buf->area = NULL; - } -} - -struct snd_soc_platform imx_soc_platform = { - .name = "imx-audio", -}; -EXPORT_SYMBOL_GPL(imx_soc_platform); - -static struct snd_soc_dai imx_ac97_dai = { - .name = "AC97", - .ac97_control = 1, - .playback = { - .stream_name = "AC97 Playback", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_48000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .capture = { - .stream_name = "AC97 Capture", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_48000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .ops = &imx_ssi_pcm_dai_ops, -}; - -static void setup_channel_to_ac97(struct imx_ssi *imx_ssi) -{ - void __iomem *base = imx_ssi->base; - - writel(0x0, base + SSI_SCR); - writel(0x0, base + SSI_STCR); - writel(0x0, base + SSI_SRCR); + if (!dai->active) + return 0; - writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR); + /* do we need to disable any clocks? */ - writel(SSI_SFCSR_RFWM0(8) | - SSI_SFCSR_TFWM0(8) | - SSI_SFCSR_RFWM1(8) | - SSI_SFCSR_TFWM1(8), base + SSI_SFCSR); - - writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR); - writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR); - - writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR); - writel(SSI_SOR_WAIT(3), base + SSI_SOR); - - writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN | - SSI_SCR_TE | SSI_SCR_RE, - base + SSI_SCR); - - writel(SSI_SACNT_DEFAULT, base + SSI_SACNT); - writel(0xff, base + SSI_SACCDIS); - writel(0x300, base + SSI_SACCEN); + return 0; } -static struct imx_ssi *ac97_ssi; - -static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, - unsigned short val) +static int imx_ssi_resume(struct snd_soc_dai *dai) { - struct imx_ssi *imx_ssi = ac97_ssi; - void __iomem *base = imx_ssi->base; - unsigned int lreg; - unsigned int lval; - - if (reg > 0x7f) - return; - - pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val); + if (!dai->active) + return 0; - lreg = reg << 12; - writel(lreg, base + SSI_SACADD); + /* do we need to enable any clocks? */ - lval = val << 4; - writel(lval , base + SSI_SACDAT); - - writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT); - udelay(100); + return 0; } +#else +#define imx_ssi_suspend NULL +#define imx_ssi_resume NULL +#endif -static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97, - unsigned short reg) -{ - struct imx_ssi *imx_ssi = ac97_ssi; - void __iomem *base = imx_ssi->base; - - unsigned short val = -1; - unsigned int lreg; - - lreg = (reg & 0x7f) << 12 ; - writel(lreg, base + SSI_SACADD); - writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT); - - udelay(100); - - val = (readl(base + SSI_SACDAT) >> 4) & 0xffff; - - pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val); +static int fifo_err_counter; - return val; +static irqreturn_t imx_ssi_irq(int irq, void *dev_id) +{ + struct imx_ssi *priv = (struct imx_ssi *)dev_id; + void __iomem *ioaddr = priv->ioaddr; + if (fifo_err_counter++ % 1000 == 0) + printk(KERN_ERR "%s %s SISR %x SIER %x fifo_errs=%d\n", + __func__, priv->pdev->name, + __raw_readl(ioaddr + SSI_SISR), + __raw_readl(ioaddr + SSI_SIER), fifo_err_counter); + __raw_writel((SSI_SIER_TUE0_EN | SSI_SIER_ROE0_EN), ioaddr + SSI_SISR); + return IRQ_HANDLED; } -static void imx_ssi_ac97_reset(struct snd_ac97 *ac97) +static int imx_ssi_probe(struct platform_device *pdev, struct snd_soc_dai *dai) { - struct imx_ssi *imx_ssi = ac97_ssi; + struct imx_ssi *priv = (struct imx_ssi *)dai->private_data; + + if (priv->irq >= 0) { + if (request_irq(priv->irq, imx_ssi_irq, IRQF_SHARED, + pdev->name, priv)) { + printk(KERN_ERR "%s: failure requesting irq for %s\n", + __func__, pdev->name); + return -EBUSY; + } + } - if (imx_ssi->ac97_reset) - imx_ssi->ac97_reset(ac97); + return 0; } -static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97) +static void imx_ssi_remove(struct platform_device *pdev, + struct snd_soc_dai *dai) { - struct imx_ssi *imx_ssi = ac97_ssi; + struct imx_ssi *priv = (struct imx_ssi *)dai->private_data; - if (imx_ssi->ac97_warm_reset) - imx_ssi->ac97_warm_reset(ac97); + if (priv->irq >= 0) + free_irq(priv->irq, dai); } -struct snd_ac97_bus_ops soc_ac97_ops = { - .read = imx_ssi_ac97_read, - .write = imx_ssi_ac97_write, - .reset = imx_ssi_ac97_reset, - .warm_reset = imx_ssi_ac97_warm_reset +#define IMX_SSI_RATES \ + (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \ + SNDRV_PCM_RATE_96000) + +#define IMX_SSI_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +static struct snd_soc_dai_ops imx_ssi_dai_ops = { + .startup = imx_ssi_startup, + .shutdown = imx_ssi_shutdown, + .trigger = imx_ssi_trigger, + .prepare = imx_ssi_prepare, + .hw_params = imx_ssi_hw_params, + .set_sysclk = imx_ssi_set_dai_sysclk, + .set_clkdiv = imx_ssi_set_dai_clkdiv, + .set_fmt = imx_ssi_set_dai_fmt, + .set_tdm_slot = imx_ssi_set_dai_tdm_slot, }; -EXPORT_SYMBOL_GPL(soc_ac97_ops); -struct snd_soc_dai imx_ssi_pcm_dai[2]; -EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai); +struct snd_soc_dai *imx_ssi_dai[MAX_SSI_CHANNELS]; +EXPORT_SYMBOL_GPL(imx_ssi_dai); -static int imx_ssi_probe(struct platform_device *pdev) +static int imx_ssi_dev_probe(struct platform_device *pdev) { + int fifo0_channel = pdev->id * 2; + struct snd_soc_dai *dai; + struct imx_ssi *priv; + int fifo, channel; struct resource *res; - struct imx_ssi *ssi; - struct imx_ssi_platform_data *pdata = pdev->dev.platform_data; - struct snd_soc_platform *platform; - int ret = 0; - unsigned int val; - struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id]; - - if (dai->id >= ARRAY_SIZE(imx_ssi_pcm_dai)) - return -EINVAL; + int ret; + + BUG_ON(fifo0_channel >= MAX_SSI_CHANNELS); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; - ssi = kzalloc(sizeof(*ssi), GFP_KERNEL); - if (!ssi) + priv = kzalloc(sizeof(struct imx_ssi), GFP_KERNEL); + if (!priv) return -ENOMEM; - if (pdata) { - ssi->ac97_reset = pdata->ac97_reset; - ssi->ac97_warm_reset = pdata->ac97_warm_reset; - ssi->flags = pdata->flags; - } + /* Each SSI block has 2 fifos which share the same + private data (struct imx_ssi) */ + priv->baseaddr = res->start; + priv->ioaddr = ioremap(res->start, 0x5C); + priv->irq = platform_get_irq(pdev, 0); + priv->ssi_clk = clk_get(&pdev->dev, "ssi_clk"); + priv->pdev = pdev; + + for (fifo = 0; fifo < 2; fifo++) { + channel = (pdev->id * 2) + fifo; + + dai = kzalloc(sizeof(struct snd_soc_dai), GFP_KERNEL); + if (IS_ERR(dai)) { + ret = -ENOMEM; + goto DAI_ERR; + } - ssi->irq = platform_get_irq(pdev, 0); + dai->name = kasprintf(GFP_KERNEL, "imx-ssi-%d-%d", + pdev->id + 1, fifo); + if (IS_ERR(dai->name)) { + kfree(dai); + ret = -ENOMEM; + goto DAI_ERR; + } - ssi->clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(ssi->clk)) { - ret = PTR_ERR(ssi->clk); - dev_err(&pdev->dev, "Cannot get the clock: %d\n", - ret); - goto failed_clk; - } - clk_enable(ssi->clk); + dai->probe = imx_ssi_probe; + dai->suspend = imx_ssi_suspend; + dai->remove = imx_ssi_remove; + dai->resume = imx_ssi_resume; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - ret = -ENODEV; - goto failed_get_resource; - } + dai->playback.channels_min = 1; + dai->playback.channels_max = 2; + dai->playback.rates = IMX_SSI_RATES; + dai->playback.formats = IMX_SSI_FORMATS; - if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) { - dev_err(&pdev->dev, "request_mem_region failed\n"); - ret = -EBUSY; - goto failed_get_resource; - } + dai->capture.channels_min = 1; + dai->capture.channels_max = 2; + dai->capture.rates = IMX_SSI_RATES; + dai->capture.formats = IMX_SSI_FORMATS; - ssi->base = ioremap(res->start, resource_size(res)); - if (!ssi->base) { - dev_err(&pdev->dev, "ioremap failed\n"); - ret = -ENODEV; - goto failed_ioremap; - } + dai->ops = &imx_ssi_dai_ops; - if (ssi->flags & IMX_SSI_USE_AC97) { - if (ac97_ssi) { - ret = -EBUSY; - goto failed_ac97; - } - ac97_ssi = ssi; - setup_channel_to_ac97(ssi); - memcpy(dai, &imx_ac97_dai, sizeof(imx_ac97_dai)); - } else - memcpy(dai, &imx_ssi_dai, sizeof(imx_ssi_dai)); - - writel(0x0, ssi->base + SSI_SIER); - - ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0; - ssi->dma_params_tx.dma_addr = res->start + SSI_STX0; - - res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0"); - if (res) - ssi->dma_params_tx.dma = res->start; - - res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0"); - if (res) - ssi->dma_params_rx.dma = res->start; - - dai->id = pdev->id; - dai->dev = &pdev->dev; - dai->name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id); - dai->private_data = ssi; - - if ((cpu_is_mx27() || cpu_is_mx21()) && - !(ssi->flags & IMX_SSI_USE_AC97) && - (ssi->flags & IMX_SSI_DMA)) { - ssi->flags |= IMX_SSI_DMA; - platform = imx_ssi_dma_mx2_init(pdev, ssi); - } else - platform = imx_ssi_fiq_init(pdev, ssi); - - imx_soc_platform.pcm_ops = platform->pcm_ops; - imx_soc_platform.pcm_new = platform->pcm_new; - imx_soc_platform.pcm_free = platform->pcm_free; - - val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) | - SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize); - writel(val, ssi->base + SSI_SFCSR); - - ret = snd_soc_register_dai(dai); - if (ret) { - dev_err(&pdev->dev, "register DAI failed\n"); - goto failed_register; - } + dai->private_data = priv; - platform_set_drvdata(pdev, ssi); + dai->id = channel; + imx_ssi_dai[channel] = dai; + ret = snd_soc_register_dai(dai); + if (ret < 0) { + kfree(dai->name); + kfree(dai); + goto DAI_ERR; + } + } return 0; -failed_register: -failed_ac97: - iounmap(ssi->base); -failed_ioremap: - release_mem_region(res->start, resource_size(res)); -failed_get_resource: - clk_disable(ssi->clk); - clk_put(ssi->clk); -failed_clk: - kfree(ssi); +DAI_ERR: + if (fifo == 1) { + dai = imx_ssi_dai[fifo0_channel]; + snd_soc_unregister_dai(dai); + kfree(dai->name); + kfree(dai); + } + clk_put(priv->ssi_clk); + iounmap(priv->ioaddr); + kfree(priv); return ret; } -static int __devexit imx_ssi_remove(struct platform_device *pdev) +static int __devexit imx_ssi_dev_remove(struct platform_device *pdev) { - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - struct imx_ssi *ssi = platform_get_drvdata(pdev); - struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id]; - - snd_soc_unregister_dai(dai); + int fifo0_channel = pdev->id * 2; + int fifo1_channel = (pdev->id * 2) + 1; + struct imx_ssi *priv = imx_ssi_dai[fifo0_channel]->private_data; - if (ssi->flags & IMX_SSI_USE_AC97) - ac97_ssi = NULL; + snd_soc_unregister_dai(imx_ssi_dai[fifo0_channel]); + snd_soc_unregister_dai(imx_ssi_dai[fifo1_channel]); - if (!(ssi->flags & IMX_SSI_DMA)) - imx_ssi_fiq_exit(pdev, ssi); + kfree(imx_ssi_dai[fifo0_channel]->name); + kfree(imx_ssi_dai[fifo0_channel]); - iounmap(ssi->base); - release_mem_region(res->start, resource_size(res)); - clk_disable(ssi->clk); - clk_put(ssi->clk); - kfree(ssi); + kfree(imx_ssi_dai[fifo1_channel]->name); + kfree(imx_ssi_dai[fifo1_channel]); + clk_put(priv->ssi_clk); + iounmap(priv->ioaddr); + kfree(priv); return 0; } static struct platform_driver imx_ssi_driver = { - .probe = imx_ssi_probe, - .remove = __devexit_p(imx_ssi_remove), - + .probe = imx_ssi_dev_probe, + .remove = __devexit_p(imx_ssi_dev_remove), .driver = { - .name = DRV_NAME, - .owner = THIS_MODULE, - }, + .name = "mxc_ssi", + }, }; static int __init imx_ssi_init(void) { - int ret; - - ret = snd_soc_register_platform(&imx_soc_platform); - if (ret) { - pr_err("failed to register soc platform: %d\n", ret); - return ret; - } - - ret = platform_driver_register(&imx_ssi_driver); - if (ret) { - snd_soc_unregister_platform(&imx_soc_platform); - return ret; - } - - return 0; + return platform_driver_register(&imx_ssi_driver); } static void __exit imx_ssi_exit(void) { platform_driver_unregister(&imx_ssi_driver); - snd_soc_unregister_platform(&imx_soc_platform); } module_init(imx_ssi_init); module_exit(imx_ssi_exit); - -/* Module information */ -MODULE_AUTHOR("Sascha Hauer, "); -MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface"); +MODULE_AUTHOR + ("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com"); +MODULE_DESCRIPTION("i.MX ASoC I2S driver"); MODULE_LICENSE("GPL"); - diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/imx/imx-ssi.h index 55f26ebcd8c2..6f0f24a2509d 100644 --- a/sound/soc/imx/imx-ssi.h +++ b/sound/soc/imx/imx-ssi.h @@ -7,231 +7,240 @@ #ifndef _IMX_SSI_H #define _IMX_SSI_H -#define SSI_STX0 0x00 -#define SSI_STX1 0x04 -#define SSI_SRX0 0x08 -#define SSI_SRX1 0x0c - -#define SSI_SCR 0x10 -#define SSI_SCR_CLK_IST (1 << 9) -#define SSI_SCR_CLK_IST_SHIFT 9 -#define SSI_SCR_TCH_EN (1 << 8) -#define SSI_SCR_SYS_CLK_EN (1 << 7) -#define SSI_SCR_I2S_MODE_NORM (0 << 5) -#define SSI_SCR_I2S_MODE_MSTR (1 << 5) -#define SSI_SCR_I2S_MODE_SLAVE (2 << 5) -#define SSI_I2S_MODE_MASK (3 << 5) -#define SSI_SCR_SYN (1 << 4) -#define SSI_SCR_NET (1 << 3) -#define SSI_SCR_RE (1 << 2) -#define SSI_SCR_TE (1 << 1) -#define SSI_SCR_SSIEN (1 << 0) - -#define SSI_SISR 0x14 -#define SSI_SISR_MASK ((1 << 19) - 1) -#define SSI_SISR_CMDAU (1 << 18) -#define SSI_SISR_CMDDU (1 << 17) -#define SSI_SISR_RXT (1 << 16) -#define SSI_SISR_RDR1 (1 << 15) -#define SSI_SISR_RDR0 (1 << 14) -#define SSI_SISR_TDE1 (1 << 13) -#define SSI_SISR_TDE0 (1 << 12) -#define SSI_SISR_ROE1 (1 << 11) -#define SSI_SISR_ROE0 (1 << 10) -#define SSI_SISR_TUE1 (1 << 9) -#define SSI_SISR_TUE0 (1 << 8) -#define SSI_SISR_TFS (1 << 7) -#define SSI_SISR_RFS (1 << 6) -#define SSI_SISR_TLS (1 << 5) -#define SSI_SISR_RLS (1 << 4) -#define SSI_SISR_RFF1 (1 << 3) -#define SSI_SISR_RFF0 (1 << 2) -#define SSI_SISR_TFE1 (1 << 1) -#define SSI_SISR_TFE0 (1 << 0) - -#define SSI_SIER 0x18 -#define SSI_SIER_RDMAE (1 << 22) -#define SSI_SIER_RIE (1 << 21) -#define SSI_SIER_TDMAE (1 << 20) -#define SSI_SIER_TIE (1 << 19) -#define SSI_SIER_CMDAU_EN (1 << 18) -#define SSI_SIER_CMDDU_EN (1 << 17) -#define SSI_SIER_RXT_EN (1 << 16) -#define SSI_SIER_RDR1_EN (1 << 15) -#define SSI_SIER_RDR0_EN (1 << 14) -#define SSI_SIER_TDE1_EN (1 << 13) -#define SSI_SIER_TDE0_EN (1 << 12) -#define SSI_SIER_ROE1_EN (1 << 11) -#define SSI_SIER_ROE0_EN (1 << 10) -#define SSI_SIER_TUE1_EN (1 << 9) -#define SSI_SIER_TUE0_EN (1 << 8) -#define SSI_SIER_TFS_EN (1 << 7) -#define SSI_SIER_RFS_EN (1 << 6) -#define SSI_SIER_TLS_EN (1 << 5) -#define SSI_SIER_RLS_EN (1 << 4) -#define SSI_SIER_RFF1_EN (1 << 3) -#define SSI_SIER_RFF0_EN (1 << 2) -#define SSI_SIER_TFE1_EN (1 << 1) -#define SSI_SIER_TFE0_EN (1 << 0) - -#define SSI_STCR 0x1c -#define SSI_STCR_TXBIT0 (1 << 9) -#define SSI_STCR_TFEN1 (1 << 8) -#define SSI_STCR_TFEN0 (1 << 7) -#define SSI_FIFO_ENABLE_0_SHIFT 7 -#define SSI_STCR_TFDIR (1 << 6) -#define SSI_STCR_TXDIR (1 << 5) -#define SSI_STCR_TSHFD (1 << 4) -#define SSI_STCR_TSCKP (1 << 3) -#define SSI_STCR_TFSI (1 << 2) -#define SSI_STCR_TFSL (1 << 1) -#define SSI_STCR_TEFS (1 << 0) - -#define SSI_SRCR 0x20 -#define SSI_SRCR_RXBIT0 (1 << 9) -#define SSI_SRCR_RFEN1 (1 << 8) -#define SSI_SRCR_RFEN0 (1 << 7) -#define SSI_FIFO_ENABLE_0_SHIFT 7 -#define SSI_SRCR_RFDIR (1 << 6) -#define SSI_SRCR_RXDIR (1 << 5) -#define SSI_SRCR_RSHFD (1 << 4) -#define SSI_SRCR_RSCKP (1 << 3) -#define SSI_SRCR_RFSI (1 << 2) -#define SSI_SRCR_RFSL (1 << 1) -#define SSI_SRCR_REFS (1 << 0) - -#define SSI_SRCCR 0x28 -#define SSI_SRCCR_DIV2 (1 << 18) -#define SSI_SRCCR_PSR (1 << 17) -#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) -#define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8) -#define SSI_SRCCR_PM(x) (((x) & 0xff) << 0) -#define SSI_SRCCR_WL_MASK (0xf << 13) -#define SSI_SRCCR_DC_MASK (0x1f << 8) -#define SSI_SRCCR_PM_MASK (0xff << 0) - -#define SSI_STCCR 0x24 -#define SSI_STCCR_DIV2 (1 << 18) -#define SSI_STCCR_PSR (1 << 17) -#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) -#define SSI_STCCR_DC(x) (((x) & 0x1f) << 8) -#define SSI_STCCR_PM(x) (((x) & 0xff) << 0) -#define SSI_STCCR_WL_MASK (0xf << 13) -#define SSI_STCCR_DC_MASK (0x1f << 8) -#define SSI_STCCR_PM_MASK (0xff << 0) - -#define SSI_SFCSR 0x2c -#define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28) -#define SSI_RX_FIFO_1_COUNT_SHIFT 28 -#define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24) -#define SSI_TX_FIFO_1_COUNT_SHIFT 24 -#define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20) -#define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16) -#define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12) -#define SSI_RX_FIFO_0_COUNT_SHIFT 12 -#define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8) -#define SSI_TX_FIFO_0_COUNT_SHIFT 8 -#define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4) -#define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0) -#define SSI_SFCSR_RFWM0_MASK (0xf << 4) -#define SSI_SFCSR_TFWM0_MASK (0xf << 0) - -#define SSI_STR 0x30 -#define SSI_STR_TEST (1 << 15) -#define SSI_STR_RCK2TCK (1 << 14) -#define SSI_STR_RFS2TFS (1 << 13) -#define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8) -#define SSI_STR_TXD2RXD (1 << 7) -#define SSI_STR_TCK2RCK (1 << 6) -#define SSI_STR_TFS2RFS (1 << 5) -#define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0) - -#define SSI_SOR 0x34 -#define SSI_SOR_CLKOFF (1 << 6) -#define SSI_SOR_RX_CLR (1 << 5) -#define SSI_SOR_TX_CLR (1 << 4) -#define SSI_SOR_INIT (1 << 3) -#define SSI_SOR_WAIT(x) (((x) & 0x3) << 1) -#define SSI_SOR_WAIT_MASK (0x3 << 1) -#define SSI_SOR_SYNRST (1 << 0) - -#define SSI_SACNT 0x38 -#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5) -#define SSI_SACNT_WR (1 << 4) -#define SSI_SACNT_RD (1 << 3) -#define SSI_SACNT_TIF (1 << 2) -#define SSI_SACNT_FV (1 << 1) -#define SSI_SACNT_AC97EN (1 << 0) - -#define SSI_SACADD 0x3c -#define SSI_SACDAT 0x40 -#define SSI_SATAG 0x44 -#define SSI_STMSK 0x48 -#define SSI_SRMSK 0x4c -#define SSI_SACCST 0x50 -#define SSI_SACCEN 0x54 -#define SSI_SACCDIS 0x58 +#include + +/* SSI regs definition */ +#define SSI1_IO_BASE_ADDR IO_ADDRESS(SSI1_BASE_ADDR) +#define SSI2_IO_BASE_ADDR IO_ADDRESS(SSI2_BASE_ADDR) + +#define SSI1_STX0 ((SSI1_IO_BASE_ADDR) + 0x00) +#define SSI1_STX1 ((SSI1_IO_BASE_ADDR) + 0x04) +#define SSI1_SRX0 ((SSI1_IO_BASE_ADDR) + 0x08) +#define SSI1_SRX1 ((SSI1_IO_BASE_ADDR) + 0x0c) +#define SSI1_SCR ((SSI1_IO_BASE_ADDR) + 0x10) +#define SSI1_SISR ((SSI1_IO_BASE_ADDR) + 0x14) +#define SSI1_SIER ((SSI1_IO_BASE_ADDR) + 0x18) +#define SSI1_STCR ((SSI1_IO_BASE_ADDR) + 0x1c) +#define SSI1_SRCR ((SSI1_IO_BASE_ADDR) + 0x20) +#define SSI1_STCCR ((SSI1_IO_BASE_ADDR) + 0x24) +#define SSI1_SRCCR ((SSI1_IO_BASE_ADDR) + 0x28) +#define SSI1_SFCSR ((SSI1_IO_BASE_ADDR) + 0x2c) +#define SSI1_STR ((SSI1_IO_BASE_ADDR) + 0x30) +#define SSI1_SOR ((SSI1_IO_BASE_ADDR) + 0x34) +#define SSI1_SACNT ((SSI1_IO_BASE_ADDR) + 0x38) +#define SSI1_SACADD ((SSI1_IO_BASE_ADDR) + 0x3c) +#define SSI1_SACDAT ((SSI1_IO_BASE_ADDR) + 0x40) +#define SSI1_SATAG ((SSI1_IO_BASE_ADDR) + 0x44) +#define SSI1_STMSK ((SSI1_IO_BASE_ADDR) + 0x48) +#define SSI1_SRMSK ((SSI1_IO_BASE_ADDR) + 0x4c) +#define SSI1_SACCST ((SSI1_IO_BASE_ADDR) + 0x50) +#define SSI1_SACCEN ((SSI1_IO_BASE_ADDR) + 0x54) +#define SSI1_SACCDIS ((SSI1_IO_BASE_ADDR) + 0x58) + +#define SSI2_STX0 ((SSI2_IO_BASE_ADDR) + 0x00) +#define SSI2_STX1 ((SSI2_IO_BASE_ADDR) + 0x04) +#define SSI2_SRX0 ((SSI2_IO_BASE_ADDR) + 0x08) +#define SSI2_SRX1 ((SSI2_IO_BASE_ADDR) + 0x0c) +#define SSI2_SCR ((SSI2_IO_BASE_ADDR) + 0x10) +#define SSI2_SISR ((SSI2_IO_BASE_ADDR) + 0x14) +#define SSI2_SIER ((SSI2_IO_BASE_ADDR) + 0x18) +#define SSI2_STCR ((SSI2_IO_BASE_ADDR) + 0x1c) +#define SSI2_SRCR ((SSI2_IO_BASE_ADDR) + 0x20) +#define SSI2_STCCR ((SSI2_IO_BASE_ADDR) + 0x24) +#define SSI2_SRCCR ((SSI2_IO_BASE_ADDR) + 0x28) +#define SSI2_SFCSR ((SSI2_IO_BASE_ADDR) + 0x2c) +#define SSI2_STR ((SSI2_IO_BASE_ADDR) + 0x30) +#define SSI2_SOR ((SSI2_IO_BASE_ADDR) + 0x34) +#define SSI2_SACNT ((SSI2_IO_BASE_ADDR) + 0x38) +#define SSI2_SACADD ((SSI2_IO_BASE_ADDR) + 0x3c) +#define SSI2_SACDAT ((SSI2_IO_BASE_ADDR) + 0x40) +#define SSI2_SATAG ((SSI2_IO_BASE_ADDR) + 0x44) +#define SSI2_STMSK ((SSI2_IO_BASE_ADDR) + 0x48) +#define SSI2_SRMSK ((SSI2_IO_BASE_ADDR) + 0x4c) +#define SSI2_SACCST ((SSI2_IO_BASE_ADDR) + 0x50) +#define SSI2_SACCEN ((SSI2_IO_BASE_ADDR) + 0x54) +#define SSI2_SACCDIS ((SSI2_IO_BASE_ADDR) + 0x58) + +#define SSI_SCR_CLK_IST (1 << 9) +#define SSI_SCR_TCH_EN (1 << 8) +#define SSI_SCR_SYS_CLK_EN (1 << 7) +#define SSI_SCR_I2S_MODE_NORM (0 << 5) +#define SSI_SCR_I2S_MODE_MSTR (1 << 5) +#define SSI_SCR_I2S_MODE_SLAVE (2 << 5) +#define SSI_SCR_SYN (1 << 4) +#define SSI_SCR_NET (1 << 3) +#define SSI_SCR_RE (1 << 2) +#define SSI_SCR_TE (1 << 1) +#define SSI_SCR_SSIEN (1 << 0) +#define SSI_SCR_I2S_MODE_MASK (3 << 5) + +#define SSI_SISR_CMDAU (1 << 18) +#define SSI_SISR_CMDDU (1 << 17) +#define SSI_SISR_RXT (1 << 16) +#define SSI_SISR_RDR1 (1 << 15) +#define SSI_SISR_RDR0 (1 << 14) +#define SSI_SISR_TDE1 (1 << 13) +#define SSI_SISR_TDE0 (1 << 12) +#define SSI_SISR_ROE1 (1 << 11) +#define SSI_SISR_ROE0 (1 << 10) +#define SSI_SISR_TUE1 (1 << 9) +#define SSI_SISR_TUE0 (1 << 8) +#define SSI_SISR_TFS (1 << 7) +#define SSI_SISR_RFS (1 << 6) +#define SSI_SISR_TLS (1 << 5) +#define SSI_SISR_RLS (1 << 4) +#define SSI_SISR_RFF1 (1 << 3) +#define SSI_SISR_RFF0 (1 << 2) +#define SSI_SISR_TFE1 (1 << 1) +#define SSI_SISR_TFE0 (1 << 0) + +#define SSI_SIER_RDMAE (1 << 22) +#define SSI_SIER_RIE (1 << 21) +#define SSI_SIER_TDMAE (1 << 20) +#define SSI_SIER_TIE (1 << 19) +#define SSI_SIER_CMDAU_EN (1 << 18) +#define SSI_SIER_CMDDU_EN (1 << 17) +#define SSI_SIER_RXT_EN (1 << 16) +#define SSI_SIER_RDR1_EN (1 << 15) +#define SSI_SIER_RDR0_EN (1 << 14) +#define SSI_SIER_TDE1_EN (1 << 13) +#define SSI_SIER_TDE0_EN (1 << 12) +#define SSI_SIER_ROE1_EN (1 << 11) +#define SSI_SIER_ROE0_EN (1 << 10) +#define SSI_SIER_TUE1_EN (1 << 9) +#define SSI_SIER_TUE0_EN (1 << 8) +#define SSI_SIER_TFS_EN (1 << 7) +#define SSI_SIER_RFS_EN (1 << 6) +#define SSI_SIER_TLS_EN (1 << 5) +#define SSI_SIER_RLS_EN (1 << 4) +#define SSI_SIER_RFF1_EN (1 << 3) +#define SSI_SIER_RFF0_EN (1 << 2) +#define SSI_SIER_TFE1_EN (1 << 1) +#define SSI_SIER_TFE0_EN (1 << 0) + +#define SSI_STCR_TXBIT0 (1 << 9) +#define SSI_STCR_TFEN1 (1 << 8) +#define SSI_STCR_TFEN0 (1 << 7) +#define SSI_STCR_TFDIR (1 << 6) +#define SSI_STCR_TXDIR (1 << 5) +#define SSI_STCR_TSHFD (1 << 4) +#define SSI_STCR_TSCKP (1 << 3) +#define SSI_STCR_TFSI (1 << 2) +#define SSI_STCR_TFSL (1 << 1) +#define SSI_STCR_TEFS (1 << 0) + +#define SSI_SRCR_RXBIT0 (1 << 9) +#define SSI_SRCR_RFEN1 (1 << 8) +#define SSI_SRCR_RFEN0 (1 << 7) +#define SSI_SRCR_RFDIR (1 << 6) +#define SSI_SRCR_RXDIR (1 << 5) +#define SSI_SRCR_RSHFD (1 << 4) +#define SSI_SRCR_RSCKP (1 << 3) +#define SSI_SRCR_RFSI (1 << 2) +#define SSI_SRCR_RFSL (1 << 1) +#define SSI_SRCR_REFS (1 << 0) + +#define SSI_STCCR_DIV2 (1 << 18) +#define SSI_STCCR_PSR (1 << 15) +#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) +#define SSI_STCCR_DC(x) (((x) & 0x1f) << 8) +#define SSI_STCCR_PM(x) (((x) & 0xff) << 0) +#define SSI_STCCR_WL_MASK (0xf << 13) +#define SSI_STCCR_DC_MASK (0x1f << 8) +#define SSI_STCCR_PM_MASK (0xff << 0) + +#define SSI_SRCCR_DIV2 (1 << 18) +#define SSI_SRCCR_PSR (1 << 15) +#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) +#define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8) +#define SSI_SRCCR_PM(x) (((x) & 0xff) << 0) +#define SSI_SRCCR_WL_MASK (0xf << 13) +#define SSI_SRCCR_DC_MASK (0x1f << 8) +#define SSI_SRCCR_PM_MASK (0xff << 0) + + +#define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28) +#define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24) +#define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20) +#define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16) +#define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12) +#define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8) +#define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4) +#define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0) + +#define SSI_STR_TEST (1 << 15) +#define SSI_STR_RCK2TCK (1 << 14) +#define SSI_STR_RFS2TFS (1 << 13) +#define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8) +#define SSI_STR_TXD2RXD (1 << 7) +#define SSI_STR_TCK2RCK (1 << 6) +#define SSI_STR_TFS2RFS (1 << 5) +#define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0) + +#define SSI_SOR_CLKOFF (1 << 6) +#define SSI_SOR_RX_CLR (1 << 5) +#define SSI_SOR_TX_CLR (1 << 4) +#define SSI_SOR_INIT (1 << 3) +#define SSI_SOR_WAIT(x) (((x) & 0x3) << 1) +#define SSI_SOR_SYNRST (1 << 0) + +#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5) +#define SSI_SACNT_WR (1 << 4) +#define SSI_SACNT_RD (1 << 3) +#define SSI_SACNT_TIF (1 << 2) +#define SSI_SACNT_FV (1 << 1) +#define SSI_SACNT_AC97EN (1 << 0) + +/* SDMA & SSI watermarks for FIFO's */ +#define SDMA_TXFIFO_WATERMARK 0x4 +#define SDMA_RXFIFO_WATERMARK 0x6 +#define SSI_TXFIFO_WATERMARK 0x4 +#define SSI_RXFIFO_WATERMARK 0x6 + +/* Maximum number of ssi channels (counting two channels per block) */ +#define MAX_SSI_CHANNELS 12 + +/* i.MX DAI SSP ID's */ +#define IMX_DAI_SSI0 0 /* SSI1 FIFO 0 */ +#define IMX_DAI_SSI1 1 /* SSI1 FIFO 1 */ +#define IMX_DAI_SSI2 2 /* SSI2 FIFO 0 */ +#define IMX_DAI_SSI3 3 /* SSI2 FIFO 1 */ +#define IMX_DAI_SSI4 4 /* SSI3 FIFO 0 */ +#define IMX_DAI_SSI5 5 /* SSI3 FIFO 1 */ /* SSI clock sources */ -#define IMX_SSP_SYS_CLK 0 +#define IMX_SSP_SYS_CLK 0 /* SSI audio dividers */ -#define IMX_SSI_TX_DIV_2 0 -#define IMX_SSI_TX_DIV_PSR 1 -#define IMX_SSI_TX_DIV_PM 2 -#define IMX_SSI_RX_DIV_2 3 -#define IMX_SSI_RX_DIV_PSR 4 -#define IMX_SSI_RX_DIV_PM 5 - -extern struct snd_soc_dai imx_ssi_pcm_dai[2]; -extern struct snd_soc_platform imx_soc_platform; - -#define DRV_NAME "imx-ssi" - -struct imx_pcm_dma_params { - int dma; - unsigned long dma_addr; - int burstsize; -}; - -struct imx_ssi { - struct platform_device *ac97_dev; +#define IMX_SSI_TX_DIV_2 0 +#define IMX_SSI_TX_DIV_PSR 1 +#define IMX_SSI_TX_DIV_PM 2 +#define IMX_SSI_RX_DIV_2 3 +#define IMX_SSI_RX_DIV_PSR 4 +#define IMX_SSI_RX_DIV_PM 5 - struct snd_soc_device imx_ac97; - struct clk *clk; - void __iomem *base; - int irq; - int fiq_enable; - unsigned int offset; - - unsigned int flags; - void (*ac97_reset) (struct snd_ac97 *ac97); - void (*ac97_warm_reset)(struct snd_ac97 *ac97); +/* SSI Div 2 */ +#define IMX_SSI_DIV_2_OFF (~SSI_STCCR_DIV2) +#define IMX_SSI_DIV_2_ON SSI_STCCR_DIV2 - struct imx_pcm_dma_params dma_params_rx; - struct imx_pcm_dma_params dma_params_tx; +#define IMX_DAI_AC97_1 0 +#define IMX_DAI_AC97_2 1 - int enabled; +/* private info */ +struct imx_ssi { + bool network_mode; + bool sync_mode; + unsigned int ac97_tx_slots; + unsigned int ac97_rx_slots; + void __iomem *ioaddr; + unsigned long baseaddr; + int irq; + struct platform_device *pdev; + struct clk *ssi_clk; }; -struct snd_soc_platform *imx_ssi_fiq_init(struct platform_device *pdev, - struct imx_ssi *ssi); -void imx_ssi_fiq_exit(struct platform_device *pdev, struct imx_ssi *ssi); -struct snd_soc_platform *imx_ssi_dma_mx2_init(struct platform_device *pdev, - struct imx_ssi *ssi); - -int snd_imx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma); -int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai, - struct snd_pcm *pcm); -void imx_pcm_free(struct snd_pcm *pcm); - -/* - * Do not change this as the FIQ handler depends on this size - */ -#define IMX_SSI_DMABUF_SIZE (64 * 1024) - -#define DMA_RXFIFO_BURST 0x4 -#define DMA_TXFIFO_BURST 0x6 +extern struct snd_soc_dai *imx_ssi_dai[]; +extern struct snd_soc_dai imx_ac97_dai[]; -#endif /* _IMX_SSI_H */ +#endif diff --git a/sound/soc/mxs/Kconfig b/sound/soc/mxs/Kconfig new file mode 100644 index 000000000000..213feb404a6b --- /dev/null +++ b/sound/soc/mxs/Kconfig @@ -0,0 +1,51 @@ +config SND_MXS_SOC + tristate "SoC Audio for the MXS chips" + depends on ARCH_MXS && SND_SOC + select SND_PCM + help + Say Y or M if you want to add support for codecs attached to + the MXS I2S or SSP interface. + + +config SND_MXS_SOC_SPDIF_DAI + tristate + +config SND_MXS_SOC_EVK_DEVB + tristate "SoC Audio support for MXS-EVK SGTL5000" + depends on SND_MXS_SOC && ARCH_MX28 + select SND_SOC_SGTL5000 + help + Say Y if you want to add support for SoC audio on MXS EVK development + board with the sgtl5000 codec. + +config SND_MXS_SOC_EVK_ADC + tristate "SoC Audio support for MXS-EVK ADC/DAC" + depends on SND_MXS_SOC && ARCH_MX23 + select SND_SOC_MXS_ADC_CODEC + help + Say Y if you want to add support for SoC audio on MXS EVK development + board with ADC/DAC audio interface. + +config SND_MXS_SOC_DAI + tristate "MXS Digital Audio Interface SAIF" + default y + depends on SND_MXS_SOC_EVK_DEVB + help + Enable MXS Digital Audio Interface SAIF + +config SND_MXS_SOC_ADC + tristate "MXS ADC/DAC Audio Interface" + default y + depends on SND_MXS_SOC_EVK_ADC + help + Enable MXS ADC/DAC Audio Interface + +config SND_MXS_SOC_EVK_DEVB_SPDIF + tristate "SoC SPDIF support for MXS EVK Development Board" + default n + depends on SND_MXS_SOC && ARCH_MXS + select SND_MXS_SOC_SPDIF_DAI + select SND_SOC_MXS_SPDIF + help + Say Y if you want to add support for SoC audio on MXS EVK development + board with the SPDIF transmitter. diff --git a/sound/soc/mxs/Makefile b/sound/soc/mxs/Makefile new file mode 100644 index 000000000000..971c622a34fb --- /dev/null +++ b/sound/soc/mxs/Makefile @@ -0,0 +1,16 @@ +# MXS platfrom support +snd-soc-mxs-objs := mxs-pcm.o +snd-soc-mxs-dai-objs := mxs-dai.o +snd-soc-mxs-spdif-dai-objs := mxs-spdif-dai.o +snd-soc-mxs-devb-objs := mxs-devb.o +snd-soc-mxs-devb-spdif-objs := mxs-devb-spdif.o +snd-soc-mxs-adc-objs := mxs-adc.o +snd-soc-mxs-evk-adc-objs := mxs-evk-adc.o + +obj-$(CONFIG_SND_MXS_SOC) += snd-soc-mxs.o +obj-$(CONFIG_SND_MXS_SOC_DAI) += snd-soc-mxs-dai.o +obj-$(CONFIG_SND_MXS_SOC_SPDIF_DAI) += snd-soc-mxs-spdif-dai.o +obj-$(CONFIG_SND_MXS_SOC_EVK_DEVB) += snd-soc-mxs-devb.o +obj-$(CONFIG_SND_MXS_SOC_EVK_DEVB_SPDIF) += snd-soc-mxs-devb-spdif.o +obj-$(CONFIG_SND_MXS_SOC_ADC) += snd-soc-mxs-adc.o +obj-$(CONFIG_SND_MXS_SOC_EVK_ADC) += snd-soc-mxs-evk-adc.o diff --git a/sound/soc/mxs/mxs-adc.c b/sound/soc/mxs/mxs-adc.c new file mode 100644 index 000000000000..6733652f76bc --- /dev/null +++ b/sound/soc/mxs/mxs-adc.c @@ -0,0 +1,477 @@ +/* + * ASoC Audio Layer for Freescale MXS ADC/DAC + * + * Author: Vladislav Buzov + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mxs-pcm.h" + +#define MXS_ADC_RATES SNDRV_PCM_RATE_8000_192000 +#define MXS_ADC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) +#define ADC_VOLUME_MIN 0x37 + +struct mxs_pcm_dma_params mxs_audio_in = { + .name = "mxs-audio-in", + .dma_ch = MXS_DMA_CHANNEL_AHB_APBX_AUDIOADC, + .irq = IRQ_ADC_DMA, +}; + +struct mxs_pcm_dma_params mxs_audio_out = { + .name = "mxs-audio-out", + .dma_ch = MXS_DMA_CHANNEL_AHB_APBX_AUDIODAC, + .irq = IRQ_DAC_DMA, +}; + +static struct delayed_work work; +static struct delayed_work adc_ramp_work; +static struct delayed_work dac_ramp_work; +static bool adc_ramp_done = 1; +static bool dac_ramp_done = 1; + +static void mxs_adc_schedule_work(struct delayed_work *work) +{ + schedule_delayed_work(work, HZ / 10); +} +static void mxs_adc_work(struct work_struct *work) +{ + /* disable irq */ + disable_irq(IRQ_HEADPHONE_SHORT); + + while (true) { + __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_CLR); + msleep(10); + if ((__raw_readl(REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL) + & BM_AUDIOOUT_ANACTRL_SHORT_LR_STS) != 0) { + /* rearm the short protection */ + __raw_writel(BM_AUDIOOUT_ANACTRL_SHORTMODE_LR, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + __raw_writel(BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(0x1), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET); + + __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET); + printk(KERN_WARNING "WARNING : Headphone LR short!\r\n"); + } else { + printk(KERN_WARNING "INFO : Headphone LR no longer short!\r\n"); + break; + } + msleep(1000); + } + + /* power up the HEADPHONE and un-mute the HPVOL */ + __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_CLR); + __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_CLR); + + /* enable irq for next short detect*/ + enable_irq(IRQ_HEADPHONE_SHORT); +} + +static void mxs_adc_schedule_ramp_work(struct delayed_work *work) +{ + schedule_delayed_work(work, msecs_to_jiffies(2)); + adc_ramp_done = 0; +} + +static void mxs_adc_ramp_work(struct work_struct *work) +{ + u32 reg = 0; + u32 reg1 = 0; + u32 reg2 = 0; + u32 l, r; + u32 ll, rr; + int i; + + reg = __raw_readl(REGS_AUDIOIN_BASE + \ + HW_AUDIOIN_ADCVOLUME); + + reg1 = reg & ~BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT; + reg1 = reg1 & ~BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT; + /* minimize adc volume */ + reg2 = reg1 | + BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(ADC_VOLUME_MIN) | + BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(ADC_VOLUME_MIN); + __raw_writel(reg2, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME); + msleep(1); + + l = (reg & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT) >> + BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT; + r = (reg & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT) >> + BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT; + + /* fade in adc vol */ + for (i = ADC_VOLUME_MIN; (i < l) || (i < r);) { + i += 0x8; + ll = i < l ? i : l; + rr = i < r ? i : r; + reg2 = reg1 | + BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(ll) | + BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(rr); + __raw_writel(reg2, + REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME); + msleep(1); + } + adc_ramp_done = 1; +} + +static void mxs_dac_schedule_ramp_work(struct delayed_work *work) +{ + schedule_delayed_work(work, msecs_to_jiffies(2)); + dac_ramp_done = 0; +} + +static void mxs_dac_ramp_work(struct work_struct *work) +{ + u32 reg = 0; + u32 reg1 = 0; + u32 l, r; + u32 ll, rr; + int i; + + /* unmute hp and speaker */ + __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_CLR); + __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL_CLR); + + reg = __raw_readl(REGS_AUDIOOUT_BASE + \ + HW_AUDIOOUT_HPVOL); + + reg1 = reg & ~BM_AUDIOOUT_HPVOL_VOL_LEFT; + reg1 = reg1 & ~BM_AUDIOOUT_HPVOL_VOL_RIGHT; + + l = (reg & BM_AUDIOOUT_HPVOL_VOL_LEFT) >> + BP_AUDIOOUT_HPVOL_VOL_LEFT; + r = (reg & BM_AUDIOOUT_HPVOL_VOL_RIGHT) >> + BP_AUDIOOUT_HPVOL_VOL_RIGHT; + /* fade in hp vol */ + for (i = 0x7f; i > 0 ;) { + i -= 0x8; + ll = i > (int)l ? i : l; + rr = i > (int)r ? i : r; + reg = reg1 | BF_AUDIOOUT_HPVOL_VOL_LEFT(ll) + | BF_AUDIOOUT_HPVOL_VOL_RIGHT(rr); + __raw_writel(reg, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL); + msleep(1); + } + dac_ramp_done = 1; +} + +static irqreturn_t mxs_short_irq(int irq, void *dev_id) +{ + __raw_writel(BM_AUDIOOUT_ANACTRL_SHORTMODE_LR, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR); + __raw_writel(BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(0x1), + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET); + + __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_SET); + __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET); + __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET); + + mxs_adc_schedule_work(&work); + return IRQ_HANDLED; +} +static irqreturn_t mxs_err_irq(int irq, void *dev_id) +{ + struct snd_pcm_substream *substream = dev_id; + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + u32 ctrl_reg; + u32 overflow_mask; + u32 underflow_mask; + + if (playback) { + ctrl_reg = __raw_readl(REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL); + underflow_mask = BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ; + overflow_mask = BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ; + } else { + ctrl_reg = __raw_readl(REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL); + underflow_mask = BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ; + overflow_mask = BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ; + } + + if (ctrl_reg & underflow_mask) { + printk(KERN_DEBUG "%s underflow detected\n", + playback ? "DAC" : "ADC"); + + if (playback) + __raw_writel( + BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + else + __raw_writel( + BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + + } else if (ctrl_reg & overflow_mask) { + printk(KERN_DEBUG "%s overflow detected\n", + playback ? "DAC" : "ADC"); + + if (playback) + __raw_writel( + BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + else + __raw_writel(BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + } else + printk(KERN_WARNING "Unknown DAC error interrupt\n"); + + return IRQ_HANDLED; +} + +static int mxs_adc_trigger(struct snd_pcm_substream *substream, + int cmd, + struct snd_soc_dai *dai) +{ + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + struct mxs_runtime_data *prtd = substream->runtime->private_data; + int ret = 0; + u32 xfer_count1 = 0; + u32 xfer_count2 = 0; + u32 cur_bar1 = 0; + u32 cur_bar2 = 0; + u32 reg; + struct mxs_dma_info dma_info; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + + if (playback) { + /* enable the fifo error interrupt */ + __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_SET); + /* write a data to data reg to trigger the transfer */ + __raw_writel(0x0, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DATA); + mxs_dac_schedule_ramp_work(&dac_ramp_work); + } else { + mxs_dma_get_info(prtd->dma_ch, &dma_info); + cur_bar1 = dma_info.buf_addr; + xfer_count1 = dma_info.xfer_count; + + __raw_writel(BM_AUDIOIN_CTRL_RUN, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_SET); + udelay(100); + + mxs_dma_get_info(prtd->dma_ch, &dma_info); + cur_bar2 = dma_info.buf_addr; + xfer_count2 = dma_info.xfer_count; + + /* check if DMA getting stuck */ + if ((xfer_count1 == xfer_count2) && (cur_bar1 == cur_bar2)) + /* read a data from data reg to trigger the receive */ + reg = __raw_readl(REGS_AUDIOIN_BASE + HW_AUDIOIN_DATA); + + mxs_adc_schedule_ramp_work(&adc_ramp_work); + } + break; + + case SNDRV_PCM_TRIGGER_STOP: + + if (playback) { + if (dac_ramp_done == 0) { + cancel_delayed_work(&dac_ramp_work); + dac_ramp_done = 1; + } + __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_SET); + __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL_SET); + /* disable the fifo error interrupt */ + __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + mdelay(50); + } else { + if (adc_ramp_done == 0) { + cancel_delayed_work(&adc_ramp_work); + adc_ramp_done = 1; + } + __raw_writel(BM_AUDIOIN_CTRL_RUN, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + } + break; + + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int mxs_adc_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + int irq; + int irq_short; + int ret; + + INIT_DELAYED_WORK(&work, mxs_adc_work); + INIT_DELAYED_WORK(&adc_ramp_work, mxs_adc_ramp_work); + INIT_DELAYED_WORK(&dac_ramp_work, mxs_dac_ramp_work); + + if (playback) { + irq = IRQ_DAC_ERROR; + snd_soc_dai_set_dma_data(dai, substream, &mxs_audio_out); + } else { + irq = IRQ_ADC_ERROR; + snd_soc_dai_set_dma_data(dai, substream, &mxs_audio_in); + } + + ret = request_irq(irq, mxs_err_irq, 0, "MXS DAC and ADC Error", + substream); + if (ret) { + printk(KERN_ERR "%s: Unable to request ADC/DAC error irq %d\n", + __func__, IRQ_DAC_ERROR); + return ret; + } + + irq_short = IRQ_HEADPHONE_SHORT; + ret = request_irq(irq_short, mxs_short_irq, + IRQF_DISABLED | IRQF_SHARED, "MXS DAC and ADC HP SHORT", substream); + if (ret) { + printk(KERN_ERR "%s: Unable to request ADC/DAC HP SHORT irq %d\n", + __func__, IRQ_DAC_ERROR); + return ret; + } + + /* Enable error interrupt */ + if (playback) { + __raw_writel(BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + __raw_writel(BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + } else { + __raw_writel(BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + __raw_writel(BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + __raw_writel(BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_SET); + } + + return 0; +} + +static void mxs_adc_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + + /* Disable error interrupt */ + if (playback) { + __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN, + REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR); + free_irq(IRQ_DAC_ERROR, substream); + } else { + __raw_writel(BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN, + REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR); + free_irq(IRQ_ADC_ERROR, substream); + } +} + +#ifdef CONFIG_PM +static int mxs_adc_suspend(struct snd_soc_dai *cpu_dai) +{ + return 0; +} + +static int mxs_adc_resume(struct snd_soc_dai *cpu_dai) +{ + return 0; +} +#else +#define mxs_adc_suspend NULL +#define mxs_adc_resume NULL +#endif /* CONFIG_PM */ + +struct snd_soc_dai_ops mxs_adc_dai_ops = { + .startup = mxs_adc_startup, + .shutdown = mxs_adc_shutdown, + .trigger = mxs_adc_trigger, +}; + +struct snd_soc_dai mxs_adc_dai = { + .name = "mxs adc/dac", + .id = 0, + .suspend = mxs_adc_suspend, + .resume = mxs_adc_resume, + .playback = { + .channels_min = 2, + .channels_max = 2, + .rates = MXS_ADC_RATES, + .formats = MXS_ADC_FORMATS, + }, + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = MXS_ADC_RATES, + .formats = MXS_ADC_FORMATS, + }, + .ops = &mxs_adc_dai_ops, +}; +EXPORT_SYMBOL_GPL(mxs_adc_dai); + +static int __init mxs_adc_dai_init(void) +{ + return snd_soc_register_dai(&mxs_adc_dai); +} + +static void __exit mxs_adc_dai_exit(void) +{ + snd_soc_unregister_dai(&mxs_adc_dai); +} +module_init(mxs_adc_dai_init); +module_exit(mxs_adc_dai_exit); + +MODULE_AUTHOR("Vladislav Buzov"); +MODULE_DESCRIPTION("MXS ADC/DAC DAI"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/mxs/mxs-adc.h b/sound/soc/mxs/mxs-adc.h new file mode 100644 index 000000000000..b922c14cb894 --- /dev/null +++ b/sound/soc/mxs/mxs-adc.h @@ -0,0 +1,21 @@ +/* + * ASoC Audio Layer for Freescale MXS ADC/DAC + * + * Author: Vladislav Buzov + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef _MXS_ADC_H +#define _MXS_ADC_H +extern struct snd_soc_dai mxs_adc_dai; +#endif diff --git a/sound/soc/mxs/mxs-dai.c b/sound/soc/mxs/mxs-dai.c new file mode 100644 index 000000000000..e8c4642e660c --- /dev/null +++ b/sound/soc/mxs/mxs-dai.c @@ -0,0 +1,689 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "mxs-pcm.h" +#include "mxs-dai.h" + +#define SAIF0_CTRL (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_CTRL) +#define SAIF1_CTRL (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_CTRL) +#define SAIF0_CTRL_SET (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_CTRL_SET) +#define SAIF1_CTRL_SET (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_CTRL_SET) +#define SAIF0_CTRL_CLR (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_CTRL_CLR) +#define SAIF1_CTRL_CLR (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_CTRL_CLR) + +#define SAIF0_STAT (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_STAT) +#define SAIF1_STAT (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_STAT) +#define SAIF0_STAT_SET (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_STAT_SET) +#define SAIF1_STAT_SET (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_STAT_SET) +#define SAIF0_STAT_CLR (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_STAT_CLR) +#define SAIF1_STAT_CLR (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_STAT_CLR) + +#define SAIF0_DATA (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_DATA) +#define SAIF1_DATA (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_DATA) +#define SAIF0_DATA_SET (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_DATA_SET) +#define SAIF1_DATA_SET (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_DATA_SET) +#define SAIF0_DATA_CLR (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_DATA_CLR) +#define SAIF1_DATA_CLR (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_DATA_CLR) + +#define SAIF0_VERSION (IO_ADDRESS(SAIF0_PHYS_ADDR) + HW_SAIF_VERSION) +#define SAIF1_VERSION (IO_ADDRESS(SAIF1_PHYS_ADDR) + HW_SAIF_VERSION) + +#define HW_SAIF_CTRL (0x00000000) +#define HW_SAIF_CTRL_SET (0x00000004) +#define HW_SAIF_CTRL_CLR (0x00000008) +#define HW_SAIF_CTRL_TOG (0x0000000c) + +#define BM_SAIF_CTRL_SFTRST 0x80000000 +#define BM_SAIF_CTRL_CLKGATE 0x40000000 +#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 +#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 +#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \ + (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE) +#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000 +#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000 +#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000 +#define BP_SAIF_CTRL_RSRVD2 21 +#define BM_SAIF_CTRL_RSRVD2 0x00E00000 +#define BF_SAIF_CTRL_RSRVD2(v) \ + (((v) << 21) & BM_SAIF_CTRL_RSRVD2) +#define BP_SAIF_CTRL_DMAWAIT_COUNT 16 +#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT) +#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 +#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000 +#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \ + (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT) +#define BM_SAIF_CTRL_LRCLK_PULSE 0x00002000 +#define BM_SAIF_CTRL_BIT_ORDER 0x00001000 +#define BM_SAIF_CTRL_DELAY 0x00000800 +#define BM_SAIF_CTRL_JUSTIFY 0x00000400 +#define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200 +#define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100 +#define BP_SAIF_CTRL_WORD_LENGTH 4 +#define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0 +#define BF_SAIF_CTRL_WORD_LENGTH(v) \ + (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH) +#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008 +#define BM_SAIF_CTRL_SLAVE_MODE 0x00000004 +#define BM_SAIF_CTRL_READ_MODE 0x00000002 +#define BM_SAIF_CTRL_RUN 0x00000001 + +#define HW_SAIF_STAT (0x00000010) +#define HW_SAIF_STAT_SET (0x00000014) +#define HW_SAIF_STAT_CLR (0x00000018) +#define HW_SAIF_STAT_TOG (0x0000001c) + +#define BM_SAIF_STAT_PRESENT 0x80000000 +#define BP_SAIF_STAT_RSRVD2 17 +#define BM_SAIF_STAT_RSRVD2 0x7FFE0000 +#define BF_SAIF_STAT_RSRVD2(v) \ + (((v) << 17) & BM_SAIF_STAT_RSRVD2) +#define BM_SAIF_STAT_DMA_PREQ 0x00010000 +#define BP_SAIF_STAT_RSRVD1 7 +#define BM_SAIF_STAT_RSRVD1 0x0000FF80 +#define BF_SAIF_STAT_RSRVD1(v) \ + (((v) << 7) & BM_SAIF_STAT_RSRVD1) +#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040 +#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020 +#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010 +#define BP_SAIF_STAT_RSRVD0 1 +#define BM_SAIF_STAT_RSRVD0 0x0000000E +#define BF_SAIF_STAT_RSRVD0(v) \ + (((v) << 1) & BM_SAIF_STAT_RSRVD0) +#define BM_SAIF_STAT_BUSY 0x00000001 + +#define HW_SAIF_DATA (0x00000020) +#define HW_SAIF_DATA_SET (0x00000024) +#define HW_SAIF_DATA_CLR (0x00000028) +#define HW_SAIF_DATA_TOG (0x0000002c) + +#define BP_SAIF_DATA_PCM_RIGHT 16 +#define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000 +#define BF_SAIF_DATA_PCM_RIGHT(v) \ + (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT) +#define BP_SAIF_DATA_PCM_LEFT 0 +#define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF +#define BF_SAIF_DATA_PCM_LEFT(v) \ + (((v) << 0) & BM_SAIF_DATA_PCM_LEFT) + +#define HW_SAIF_VERSION (0x00000030) + +#define BP_SAIF_VERSION_MAJOR 24 +#define BM_SAIF_VERSION_MAJOR 0xFF000000 +#define BF_SAIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SAIF_VERSION_MAJOR) +#define BP_SAIF_VERSION_MINOR 16 +#define BM_SAIF_VERSION_MINOR 0x00FF0000 +#define BF_SAIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_SAIF_VERSION_MINOR) +#define BP_SAIF_VERSION_STEP 0 +#define BM_SAIF_VERSION_STEP 0x0000FFFF +#define BF_SAIF_VERSION_STEP(v) \ + (((v) << 0) & BM_SAIF_VERSION_STEP) +/* debug */ +#define MXS_SAIF_DEBUG 0 +#if MXS_SAIF_DEBUG +#define dbg(format, arg...) printk(format, ## arg) +#else +#define dbg(format, arg...) +#endif + +#define MXS_SAIF_DUMP 0 +#if MXS_SAIF_DUMP +#define SAIF_DUMP() \ + do { \ + printk(KERN_INFO "dump @ %s\n", __func__);\ + printk(KERN_INFO "scr %x\t, %x\n", \ + __raw_readl(SAIF0_CTRL), __raw_readl(SAIF1_CTRL));\ + printk(KERN_INFO "stat %x\t, %x\n", \ + __raw_readl(SAIF0_STAT), __raw_readl(SAIF1_STAT));\ + printk(KERN_INFO "data %x\t, %x\n", \ + __raw_readl(SAIF0_DATA), __raw_readl(SAIF1_DATA));\ + printk(KERN_INFO "version %x\t, %x\n", \ + __raw_readl(SAIF0_VERSION), __raw_readl(SAIF1_VERSION)); + } while (0); +#else +#define SAIF_DUMP() +#endif + +#define SAIF0_PORT 0 +#define SAIF1_PORT 1 + +#define MXS_DAI_SAIF0 0 +#define MXS_DAI_SAIF1 1 + +static struct mxs_saif mxs_saif_en; + +static int saif_active[2] = { 0, 0 }; + +struct mxs_pcm_dma_params mxs_saif_0 = { + .name = "mxs-saif-0", + .dma_ch = MXS_DMA_CHANNEL_AHB_APBX_SAIF0, + .irq = IRQ_SAIF0_DMA, +}; + +struct mxs_pcm_dma_params mxs_saif_1 = { + .name = "mxs-saif-1", + .dma_ch = MXS_DMA_CHANNEL_AHB_APBX_SAIF1, + .irq = IRQ_SAIF1_DMA, +}; + +/* +* SAIF system clock configuration. +* Should only be called when port is inactive. +*/ +static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, + int clk_id, unsigned int freq, int dir) +{ + struct clk *saif_clk; + u32 scr; + struct mxs_saif *saif_select = (struct mxs_saif *)cpu_dai->private_data; + + switch (clk_id) { + case IMX_SSP_SYS_CLK: + saif_clk = saif_select->saif_mclk; + if (IS_ERR(saif_clk)) { + pr_err("%s:failed to get sys_clk\n", __func__); + return -EINVAL; + } + clk_set_rate(saif_clk, freq); + clk_enable(saif_clk); + break; + default: + return -EINVAL; + } + return 0; +} + +/* + * SAIF Clock dividers + * Should only be called when port is inactive. + */ +static int mxs_saif_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, + int div_id, int div) +{ + u32 scr; + struct mxs_saif *saif_select = (struct mxs_saif *)cpu_dai->private_data; + + if (saif_select->saif_clk == SAIF0) + scr = __raw_readl(SAIF0_CTRL); + else + scr = __raw_readl(SAIF1_CTRL); + + scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; + scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; + + switch (div_id) { + case IMX_SSP_SYS_MCLK: + switch (div) { + case 32: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); + scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + case 64: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); + scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + case 128: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); + scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + case 256: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); + scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + case 512: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); + scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + case 48: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); + scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + case 96: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); + scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + case 192: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); + scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + case 384: + scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); + scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + + if (saif_select->saif_clk == SAIF0) + __raw_writel(scr, SAIF0_CTRL); + else + __raw_writel(scr, SAIF1_CTRL); + + return 0; +} + +/* + * SAIF DAI format configuration. + * Should only be called when port is inactive. + * Note: We don't use the I2S modes but instead manually configure the + * SAIF for I2S. + */ +static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) +{ + u32 scr, stat; + u32 scr0, scr1; + struct mxs_saif *saif_select = (struct mxs_saif *)cpu_dai->private_data; + + stat = (__raw_readl(SAIF0_STAT)) | (__raw_readl(SAIF1_STAT)); + if (stat & BM_SAIF_STAT_BUSY) + return 0; + + scr0 = __raw_readl(SAIF0_CTRL); + scr1 = __raw_readl(SAIF1_CTRL); + scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ + & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; + scr1 = scr1 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ + & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; + scr = 0; + + /* DAI mode */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + /* data frame low 1clk before data */ + scr |= BM_SAIF_CTRL_DELAY; + scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; + break; + case SND_SOC_DAIFMT_LEFT_J: + /* data frame high with data */ + scr &= ~BM_SAIF_CTRL_DELAY; + scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; + scr &= ~BM_SAIF_CTRL_JUSTIFY; + break; + } + + /* DAI clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_IB_IF: + scr |= BM_SAIF_CTRL_BITCLK_EDGE; + scr |= BM_SAIF_CTRL_LRCLK_POLARITY; + break; + case SND_SOC_DAIFMT_IB_NF: + scr |= BM_SAIF_CTRL_BITCLK_EDGE; + scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; + break; + case SND_SOC_DAIFMT_NB_IF: + scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; + scr |= BM_SAIF_CTRL_LRCLK_POLARITY; + break; + case SND_SOC_DAIFMT_NB_NF: + scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; + scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; + break; + } + + /* DAI clock master masks */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + break; + case SND_SOC_DAIFMT_CBM_CFS: + break; + case SND_SOC_DAIFMT_CBS_CFM: + break; + case SND_SOC_DAIFMT_CBM_CFM: + if (saif_select->saif_clk == SAIF0) { + scr &= ~BM_SAIF_CTRL_SLAVE_MODE; + __raw_writel(scr | scr0, SAIF0_CTRL); + scr |= BM_SAIF_CTRL_SLAVE_MODE; + __raw_writel(scr | scr1, SAIF1_CTRL); + } else { + scr &= ~BM_SAIF_CTRL_SLAVE_MODE; + __raw_writel(scr | scr1, SAIF1_CTRL); + scr |= BM_SAIF_CTRL_SLAVE_MODE; + __raw_writel(scr | scr0, SAIF0_CTRL); + } + break; + } + + SAIF_DUMP(); + return 0; +} + +static int mxs_saif_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + /* we cant really change any saif values after saif is enabled*/ + struct mxs_saif *saif_select = (struct mxs_saif *)cpu_dai->private_data; + + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_CAPTURE))) + snd_soc_dai_set_dma_data(cpu_dai, substream, &mxs_saif_0); + else + snd_soc_dai_set_dma_data(cpu_dai, substream, &mxs_saif_1); + + if (cpu_dai->playback.active && cpu_dai->capture.active) + return 0; + + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_CAPTURE))) + if (saif_active[SAIF0_PORT]++) + return 0; + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_CAPTURE)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))) + if (saif_active[SAIF1_PORT]++) + return 0; + SAIF_DUMP(); + return 0; +} + +/* + * Should only be called when port is inactive. + * although can be called multiple times by upper layers. + */ +static int mxs_saif_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) +{ + u32 scr, stat; + struct mxs_saif *saif_select = (struct mxs_saif *)cpu_dai->private_data; + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_CAPTURE))) { + scr = __raw_readl(SAIF0_CTRL); + stat = __raw_readl(SAIF0_STAT); + } else { + scr = __raw_readl(SAIF1_CTRL); + stat = __raw_readl(SAIF1_STAT); + } + /* cant change any parameters when SAIF is running */ + /* DAI data (word) size */ + scr &= ~BM_SAIF_CTRL_WORD_LENGTH; + scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + scr |= BF_SAIF_CTRL_WORD_LENGTH(0); + break; + case SNDRV_PCM_FORMAT_S20_3LE: + scr |= BF_SAIF_CTRL_WORD_LENGTH(4); + scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; + break; + case SNDRV_PCM_FORMAT_S24_LE: + scr |= BF_SAIF_CTRL_WORD_LENGTH(8); + scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; + break; + } + /* Tx/Rx config */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* enable TX mode */ + scr &= ~BM_SAIF_CTRL_READ_MODE; + } else { + /* enable RX mode */ + scr |= BM_SAIF_CTRL_READ_MODE; + } + + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_CAPTURE))) + __raw_writel(scr, SAIF0_CTRL); + else + __raw_writel(scr, SAIF1_CTRL); + return 0; +} + +static int mxs_saif_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + struct mxs_saif *saif_select = (struct mxs_saif *)cpu_dai->private_data; + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_CAPTURE))) + __raw_writel(BM_SAIF_CTRL_CLKGATE, SAIF0_CTRL_CLR); + else + __raw_writel(BM_SAIF_CTRL_CLKGATE, SAIF1_CTRL_CLR); + SAIF_DUMP(); + return 0; +} + +static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *cpu_dai) +{ + void __iomem *reg; + struct mxs_saif *saif_select = (struct mxs_saif *)cpu_dai->private_data; + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_CAPTURE))) + reg = (void __iomem *)SAIF0_DATA; + else + reg = (void __iomem *)SAIF1_DATA; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + /*write a data to saif data register to trigger + the transfer*/ + __raw_writel(0, reg); + else + /*read a data from saif data register to trigger + the receive*/ + __raw_readl(reg); + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + break; + default: + return -EINVAL; + } + SAIF_DUMP(); + return 0; +} + +static void mxs_saif_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + struct mxs_saif *saif_select = (struct mxs_saif *)cpu_dai->private_data; + /* shutdown SAIF if neither Tx or Rx is active */ + if (cpu_dai->playback.active || cpu_dai->capture.active) + return; + + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_CAPTURE))) + if (--saif_active[SAIF0_PORT] > 1) + return; + + if (((saif_select->stream_mapping == PLAYBACK_SAIF0_CAPTURE_SAIF1) && \ + (substream->stream == SNDRV_PCM_STREAM_CAPTURE)) || \ + ((saif_select->stream_mapping == PLAYBACK_SAIF1_CAPTURE_SAIF0) \ + && (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))) + if (--saif_active[SAIF1_PORT]) + return; +} + +#ifdef CONFIG_PM +static int mxs_saif_suspend(struct snd_soc_dai *dai) +{ + if (!dai->active) + return 0; + /* do we need to disable any clocks? */ + return 0; +} + +static int mxs_saif_resume(struct snd_soc_dai *dai) +{ + if (!dai->active) + return 0; + /* do we need to enable any clocks? */ + return 0; +} +#else +#define mxs_saif_suspend NULL +#define mxs_saif_resume NULL +#endif + +static int fifo_err_counter; + +static irqreturn_t saif0_irq(int irq, void *dev_id) +{ + if (fifo_err_counter++ % 100 == 0) + printk(KERN_ERR "saif0_irq SAIF_STAT %x SAIF_CTRL %x fifo_errs=\ + %d\n", + __raw_readl(SAIF0_STAT), + __raw_readl(SAIF0_CTRL), + fifo_err_counter); + __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | \ + BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, SAIF0_STAT_CLR); + return IRQ_HANDLED; +} + +static irqreturn_t saif1_irq(int irq, void *dev_id) +{ + if (fifo_err_counter++ % 100 == 0) + printk(KERN_ERR "saif1_irq SAIF_STAT %x SAIF_CTRL %x \ + fifo_errs=%d\n", + __raw_readl(SAIF1_STAT), + __raw_readl(SAIF1_CTRL), + fifo_err_counter); + __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | \ + BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, SAIF1_STAT_CLR); + return IRQ_HANDLED; +} + +static int mxs_saif_probe(struct platform_device *pdev, struct snd_soc_dai *dai) +{ + if (request_irq(IRQ_SAIF0, saif0_irq, 0, "saif0", dai)) { + printk(KERN_ERR "%s: failure requesting irq %s\n", + __func__, "saif0"); + return -EBUSY; + } + + if (request_irq(IRQ_SAIF1, saif1_irq, 0, "saif1", dai)) { + printk(KERN_ERR "%s: failure requesting irq %s\n", + __func__, "saif1"); + return -EBUSY; + } + return 0; +} + +static void mxs_saif_remove(struct platform_device *pdev, + struct snd_soc_dai *dai) +{ + free_irq(IRQ_SAIF0, dai); + free_irq(IRQ_SAIF1, dai); +} + +#define MXS_SAIF_RATES \ + (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \ + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \ + SNDRV_PCM_RATE_192000) + +#define MXS_SAIF_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +static struct snd_soc_dai_ops mxs_saif_dai_ops = { + .startup = mxs_saif_startup, + .shutdown = mxs_saif_shutdown, + .trigger = mxs_saif_trigger, + .prepare = mxs_saif_prepare, + .hw_params = mxs_saif_hw_params, + .set_sysclk = mxs_saif_set_dai_sysclk, + .set_clkdiv = mxs_saif_set_dai_clkdiv, + .set_fmt = mxs_saif_set_dai_fmt, +}; + +struct snd_soc_dai mxs_saif_dai[] = { + { + .name = "mxs-saif", + .probe = mxs_saif_probe, + .remove = mxs_saif_remove, + .suspend = mxs_saif_suspend, + .resume = mxs_saif_resume, + .playback = { + .channels_min = 2, + .channels_max = 2, + .rates = MXS_SAIF_RATES, + .formats = MXS_SAIF_FORMATS, + }, + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = MXS_SAIF_RATES, + .formats = MXS_SAIF_FORMATS, + }, + .ops = &mxs_saif_dai_ops, + .private_data = &mxs_saif_en, + } +}; +EXPORT_SYMBOL_GPL(mxs_saif_dai); + +static int __init mxs_saif_init(void) +{ + return snd_soc_register_dais(mxs_saif_dai, ARRAY_SIZE(mxs_saif_dai)); +} + +static void __exit mxs_saif_exit(void) +{ + snd_soc_unregister_dais(mxs_saif_dai, ARRAY_SIZE(mxs_saif_dai)); +} + +module_init(mxs_saif_init); +module_exit(mxs_saif_exit); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("i.MX28 ASoC I2S driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/mxs/mxs-dai.h b/sound/soc/mxs/mxs-dai.h new file mode 100644 index 000000000000..2476feb832b3 --- /dev/null +++ b/sound/soc/mxs/mxs-dai.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _MXS_SAIF_H +#define _MXS_SAIF_H + +#include + +/* SAIF clock sources */ +#define IMX_SSP_SYS_CLK 0 +#define IMX_SSP_SYS_MCLK 1 + +#define SAIF0 0 +#define SAIF1 1 + +/*private info*/ +struct mxs_saif { + u8 saif_clk; +#define PLAYBACK_SAIF0_CAPTURE_SAIF1 0 +#define PLAYBACK_SAIF1_CAPTURE_SAIF0 1 + u16 stream_mapping; + struct clk *saif_mclk; +}; + +extern struct snd_soc_dai mxs_saif_dai[]; + +#endif diff --git a/sound/soc/mxs/mxs-devb-spdif.c b/sound/soc/mxs/mxs-devb-spdif.c new file mode 100644 index 000000000000..9ed62110dff7 --- /dev/null +++ b/sound/soc/mxs/mxs-devb-spdif.c @@ -0,0 +1,90 @@ +/* + * ASoC driver for MXS Evk development board + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. + * + * based on stmp3780_devb_spdif.c + * + * Vladimir Barinov + * + * Copyright 2008 SigmaTel, Inc + * Copyright 2008 Embedded Alley Solutions, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "mxs-spdif-dai.h" +#include "../codecs/mxs_spdif.h" +#include "mxs-pcm.h" + +/* mxs devb digital audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link mxs_devb_dai = { + .name = "MXS SPDIF", + .stream_name = "MXS SPDIF", + .cpu_dai = &mxs_spdif_dai, + .codec_dai = &mxs_spdif_codec_dai, +}; + +/* mxs devb audio machine driver */ +static struct snd_soc_card snd_soc_machine_mxs_devb = { + .name = "mxs-evk", + .platform = &mxs_soc_platform, + .dai_link = &mxs_devb_dai, + .num_links = 1, +}; + +/* mxs devb audio subsystem */ +static struct snd_soc_device mxs_devb_snd_devdata = { + .card = &snd_soc_machine_mxs_devb, + .codec_dev = &soc_spdif_codec_dev_mxs, +}; + +static struct platform_device *mxs_devb_snd_device; + +static int __init mxs_devb_init(void) +{ + int ret = 0; + + mxs_devb_snd_device = platform_device_alloc("soc-audio", 2); + if (!mxs_devb_snd_device) + return -ENOMEM; + + platform_set_drvdata(mxs_devb_snd_device, + &mxs_devb_snd_devdata); + mxs_devb_snd_devdata.dev = &mxs_devb_snd_device->dev; + mxs_devb_snd_device->dev.platform_data = + &mxs_devb_snd_devdata; + + ret = platform_device_add(mxs_devb_snd_device); + if (ret) + platform_device_put(mxs_devb_snd_device); + + return ret; +} + +static void __exit mxs_devb_exit(void) +{ + platform_device_unregister(mxs_devb_snd_device); +} + +module_init(mxs_devb_init); +module_exit(mxs_devb_exit); + +MODULE_AUTHOR("Vladimir Barinov"); +MODULE_DESCRIPTION("MXS EVK development board ASoC driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/mxs/mxs-devb.c b/sound/soc/mxs/mxs-devb.c new file mode 100644 index 000000000000..6847c54a6485 --- /dev/null +++ b/sound/soc/mxs/mxs-devb.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mxs-dai.h" +#include "mxs-pcm.h" +#include "../codecs/sgtl5000.h" + +struct mxs_evk_priv { + int sysclk; + int hw; + struct platform_device *pdev; +}; + +static struct mxs_evk_priv card_priv; + +static int mxs_evk_audio_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *machine = rtd->dai; + struct snd_soc_dai *cpu_dai = machine->cpu_dai; + struct snd_soc_dai *codec_dai = machine->codec_dai; + struct mxs_evk_priv *priv = &card_priv; + unsigned int rate = params_rate(params); + int ret = 0; + + u32 dai_format; + + /* only need to do this once as capture and playback are sync */ + if (priv->hw) + return 0; + priv->hw = 1; + priv->sysclk = 512 * rate; + + snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, (priv->sysclk)/2, 0); + snd_soc_dai_set_sysclk(codec_dai, SGTL5000_LRCLK, rate, 0); + + snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSP_SYS_MCLK, 256); + /* set codec to slave mode */ + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS; + + /* set codec DAI configuration */ + ret = snd_soc_dai_set_fmt(codec_dai, dai_format); + if (ret < 0) + return ret; + /* set cpu_dai to master mode for playback, slave mode for record */ + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM; + + /* set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format); + if (ret < 0) + return ret; + + /* set the SAIF system clock as output */ + snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, priv->sysclk, \ + SND_SOC_CLOCK_OUT); + + return 0; +} + +static int mxs_evk_startup(struct snd_pcm_substream *substream) +{ + return 0; +} + +static void mxs_evk_shutdown(struct snd_pcm_substream *substream) +{ + struct mxs_evk_priv *priv = &card_priv; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai_link *machine = rtd->dai; + struct snd_soc_dai *cpu_dai = machine->cpu_dai; + + if (cpu_dai->playback.active || cpu_dai->capture.active) + priv->hw = 1; + else + priv->hw = 0; +} + +/* + * mxs_evk SGTL5000 audio DAI opserations. + */ +static struct snd_soc_ops mxs_evk_ops = { + .startup = mxs_evk_startup, + .shutdown = mxs_evk_shutdown, + .hw_params = mxs_evk_audio_hw_params, +}; + +/* mxs_evk machine connections to the codec pins */ +static const struct snd_soc_dapm_route audio_map[] = { + + /* Mic Jack --> MIC_IN (with automatic bias) */ + {"MIC_IN", NULL, "Mic Jack"}, + + /* Line in Jack --> LINE_IN */ + {"LINE_IN", NULL, "Line In Jack"}, + + /* HP_OUT --> Headphone Jack */ + {"Headphone Jack", NULL, "HP_OUT"}, + + /* LINE_OUT --> Ext Speaker */ + {"Ext Spk", NULL, "LINE_OUT"}, +}; + +static const char *jack_function[] = { "off", "on"}; + +static const char *spk_function[] = { "off", "on" }; + +static const char *line_in_function[] = { "off", "on" }; + +static const struct soc_enum sgtl5000_enum[] = { + SOC_ENUM_SINGLE_EXT(2, jack_function), + SOC_ENUM_SINGLE_EXT(2, spk_function), + SOC_ENUM_SINGLE_EXT(2, line_in_function), +}; + +/* mxs_evk card dapm widgets */ +static const struct snd_soc_dapm_widget mxs_evk_dapm_widgets[] = { + SND_SOC_DAPM_MIC("Mic Jack", NULL), + SND_SOC_DAPM_LINE("Line In Jack", NULL), + SND_SOC_DAPM_HP("Headphone Jack", NULL), +}; + +static int mxs_evk_sgtl5000_init(struct snd_soc_codec *codec) +{ + /* Add mxs_evk specific widgets */ + snd_soc_dapm_new_controls(codec, mxs_evk_dapm_widgets, + ARRAY_SIZE(mxs_evk_dapm_widgets)); + + /* Set up mxs_evk specific audio path audio_map */ + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_sync(codec); + + return 0; +} + +/* mxs_evk digital audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link mxs_evk_dai = { + .name = "SGTL5000", + .stream_name = "SGTL5000", + .codec_dai = &sgtl5000_dai, + .init = mxs_evk_sgtl5000_init, + .ops = &mxs_evk_ops, +}; + +static int mxs_evk_card_remove(struct platform_device *pdev) +{ + struct mxs_evk_priv *priv = &card_priv; + struct mxs_audio_platform_data *plat; + if (priv->pdev) { + plat = priv->pdev->dev.platform_data; + if (plat->finit) + plat->finit(); + } + + return 0; +} + +static struct snd_soc_card snd_soc_card_mxs_evk = { + .name = "mxs-evk", + .platform = &mxs_soc_platform, + .dai_link = &mxs_evk_dai, + .num_links = 1, + .remove = mxs_evk_card_remove, +}; + +static struct snd_soc_device mxs_evk_snd_devdata = { + .card = &snd_soc_card_mxs_evk, + .codec_dev = &soc_codec_dev_sgtl5000, +}; + +static int __devinit mxs_evk_sgtl5000_probe(struct platform_device *pdev) +{ + struct mxs_audio_platform_data *plat = pdev->dev.platform_data; + struct mxs_saif *saif_select; + int ret = -EINVAL; + if (plat->init && plat->init()) + goto err_plat_init; + mxs_evk_dai.cpu_dai = &mxs_saif_dai[0]; + saif_select = (struct mxs_saif *)mxs_evk_dai.cpu_dai->private_data; + saif_select->stream_mapping = PLAYBACK_SAIF0_CAPTURE_SAIF1; + saif_select->saif_mclk = plat->saif_mclock; + saif_select->saif_clk = SAIF0; + return 0; +err_plat_init: + if (plat->finit) + plat->finit(); + return ret; +} + +static int mxs_evk_sgtl5000_remove(struct platform_device *pdev) +{ + struct mxs_audio_platform_data *plat = pdev->dev.platform_data; + + if (plat->finit) + plat->finit(); + return 0; +} + +static struct platform_driver mxs_evk_sgtl5000_audio_driver = { + .probe = mxs_evk_sgtl5000_probe, + .remove = mxs_evk_sgtl5000_remove, + .driver = { + .name = "mxs-sgtl5000", + }, +}; + +static struct platform_device *mxs_evk_snd_device; + +static int __init mxs_evk_init(void) +{ + int ret; + + ret = platform_driver_register(&mxs_evk_sgtl5000_audio_driver); + if (ret) + return -ENOMEM; + + mxs_evk_snd_device = platform_device_alloc("soc-audio", 1); + if (!mxs_evk_snd_device) + return -ENOMEM; + + platform_set_drvdata(mxs_evk_snd_device, &mxs_evk_snd_devdata); + mxs_evk_snd_devdata.dev = &mxs_evk_snd_device->dev; + ret = platform_device_add(mxs_evk_snd_device); + + if (ret) + platform_device_put(mxs_evk_snd_device); + + return ret; +} + +static void __exit mxs_evk_exit(void) +{ + platform_driver_unregister(&mxs_evk_sgtl5000_audio_driver); + platform_device_unregister(mxs_evk_snd_device); +} + +module_init(mxs_evk_init); +module_exit(mxs_evk_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("SGTL5000 Driver for MXS EVK"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/mxs/mxs-evk-adc.c b/sound/soc/mxs/mxs-evk-adc.c new file mode 100644 index 000000000000..16c1cb4fab96 --- /dev/null +++ b/sound/soc/mxs/mxs-evk-adc.c @@ -0,0 +1,198 @@ +/* + * ASoC driver for Freescale MXS EVK board + * + * Author: Vladislav Buzov + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../codecs/mxs-adc-codec.h" +#include "mxs-adc.h" +#include "mxs-pcm.h" + +/* mxs evk machine connections to the codec pins */ +static const struct snd_soc_dapm_route audio_map[] = { + /* HPR/HPL OUT --> Headphone Jack */ + {"Headphone Jack", NULL, "HPR"}, + {"Headphone Jack", NULL, "HPL"}, + + /* SPEAKER OUT --> Ext Speaker */ + {"Ext Spk", NULL, "SPEAKER"}, +}; + +static int mxs_evk_jack_func; +static int mxs_evk_spk_func; + +static const char *jack_function[] = { "off", "on"}; + +static const char *spk_function[] = { "off", "on" }; + + +static const struct soc_enum mxs_evk_enum[] = { + SOC_ENUM_SINGLE_EXT(2, jack_function), + SOC_ENUM_SINGLE_EXT(2, spk_function), +}; + +static int mxs_evk_get_jack(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = mxs_evk_jack_func; + return 0; +} + +static int mxs_evk_set_jack(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + + if (mxs_evk_jack_func == ucontrol->value.enumerated.item[0]) + return 0; + + mxs_evk_jack_func = ucontrol->value.enumerated.item[0]; + if (mxs_evk_jack_func) + snd_soc_dapm_enable_pin(codec, "Headphone Jack"); + else + snd_soc_dapm_disable_pin(codec, "Headphone Jack"); + + snd_soc_dapm_sync(codec); + return 1; +} + +static int mxs_evk_get_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = mxs_evk_spk_func; + return 0; +} + +static int mxs_evk_set_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + + if (mxs_evk_spk_func == ucontrol->value.enumerated.item[0]) + return 0; + + mxs_evk_spk_func = ucontrol->value.enumerated.item[0]; + if (mxs_evk_spk_func) + snd_soc_dapm_enable_pin(codec, "Ext Spk"); + else + snd_soc_dapm_disable_pin(codec, "Ext Spk"); + + snd_soc_dapm_sync(codec); + return 1; +} +/* mxs evk card dapm widgets */ +static const struct snd_soc_dapm_widget mxs_evk_dapm_widgets[] = { + SND_SOC_DAPM_SPK("Ext Spk", NULL), + SND_SOC_DAPM_HP("Headphone Jack", NULL), +}; + +static const struct snd_kcontrol_new mxs_evk_controls[] = { + SOC_ENUM_EXT("HP Playback Switch", mxs_evk_enum[0], mxs_evk_get_jack, + mxs_evk_set_jack), + SOC_ENUM_EXT("Speaker Playback Switch", mxs_evk_enum[1], + mxs_evk_get_spk, mxs_evk_set_spk), +}; + +static int mxs_evk_codec_init(struct snd_soc_codec *codec) +{ + int i, ret; + /* Add mxs evk specific controls */ + snd_soc_add_controls(codec, mxs_evk_controls, + ARRAY_SIZE(mxs_evk_controls)); + + /* Add mxs evk specific widgets */ + snd_soc_dapm_new_controls(codec, mxs_evk_dapm_widgets, + ARRAY_SIZE(mxs_evk_dapm_widgets)); + + /* Set up mxs evk specific audio path audio_map */ + snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); + + snd_soc_dapm_sync(codec); + /* default on */ + mxs_evk_jack_func = 1; + mxs_evk_spk_func = 1; + + return ret; +} +/* mxs evk dac/adc audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link mxs_evk_codec_dai = { + .name = "MXS ADC/DAC", + .stream_name = "MXS ADC/DAC", + .cpu_dai = &mxs_adc_dai, + .codec_dai = &mxs_codec_dai, + .init = mxs_evk_codec_init, +}; + +/* mxs evk audio machine driver */ +static struct snd_soc_card snd_soc_card_mxs_evk = { + .name = "MXS EVK", + .platform = &mxs_soc_platform, + .dai_link = &mxs_evk_codec_dai, + .num_links = 1, +}; + +/* mxs evk audio subsystem */ +static struct snd_soc_device mxs_evk_snd_devdata = { + .card = &snd_soc_card_mxs_evk, + .codec_dev = &soc_codec_dev_mxs, +}; + +static struct platform_device *mxs_evk_snd_device; + +static int __init mxs_evk_adc_init(void) +{ + int ret = 0; + + mxs_evk_snd_device = platform_device_alloc("soc-audio", 0); + if (!mxs_evk_snd_device) + return -ENOMEM; + + platform_set_drvdata(mxs_evk_snd_device, + &mxs_evk_snd_devdata); + mxs_evk_snd_devdata.dev = &mxs_evk_snd_device->dev; + mxs_evk_snd_device->dev.platform_data = + &mxs_evk_snd_devdata; + + ret = platform_device_add(mxs_evk_snd_device); + if (ret) + platform_device_put(mxs_evk_snd_device); + + return ret; +} + +static void __exit mxs_evk_adc_exit(void) +{ + platform_device_unregister(mxs_evk_snd_device); +} + +module_init(mxs_evk_adc_init); +module_exit(mxs_evk_adc_exit); + +MODULE_AUTHOR("Vladislav Buzov"); +MODULE_DESCRIPTION("MXS EVK board ADC/DAC driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/mxs/mxs-pcm.c b/sound/soc/mxs/mxs-pcm.c new file mode 100644 index 000000000000..b4d7ca00a68f --- /dev/null +++ b/sound/soc/mxs/mxs-pcm.c @@ -0,0 +1,504 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "mxs-pcm.h" +static const struct snd_pcm_hardware mxs_pcm_hardware = { + .info = SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME | + SNDRV_PCM_INFO_INTERLEAVED, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S20_3LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 2, + .period_bytes_min = 32, + .period_bytes_max = 8192, + .periods_min = 1, + .periods_max = 255, + .buffer_bytes_max = 64 * 1024, + .fifo_size = 32, +}; + +/* + * Required to request DMA channels + */ +struct device *mxs_pcm_dev; + +static irqreturn_t mxs_pcm_dma_irq(int irq, void *dev_id) +{ + struct snd_pcm_substream *substream = dev_id; + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxs_runtime_data *prtd = substream->runtime->private_data; + struct mxs_dma_info dma_info; + void *pdma; + unsigned long prev_appl_offset, appl_count, cont, appl_ptr_bytes; + + mxs_dma_get_info(prtd->dma_ch, &dma_info); + + if (dma_info.status) { + printk(KERN_WARNING "%s: DMA audio channel %d (%s) error\n", + __func__, prtd->params->dma_ch, prtd->params->name); + mxs_dma_ack_irq(prtd->dma_ch); + } else { + if ((prtd->params->dma_ch == MXS_DMA_CHANNEL_AHB_APBX_SPDIF) && + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) && + (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) && + ((prtd->format == SNDRV_PCM_FORMAT_S24_LE) + || (prtd->format == SNDRV_PCM_FORMAT_S20_3LE))) { + + appl_ptr_bytes = + frames_to_bytes(runtime, + runtime->control->appl_ptr); + + appl_count = appl_ptr_bytes - prtd->appl_ptr_bytes; + prev_appl_offset = + prtd->appl_ptr_bytes % prtd->dma_totsize; + cont = prtd->dma_totsize - prev_appl_offset; + + if (appl_count > cont) { + pdma = runtime->dma_area + prev_appl_offset; + memmove(pdma + 1, pdma, cont - 1); + pdma = runtime->dma_area; + memmove(pdma + 1, pdma, appl_count - cont - 1); + } else { + pdma = runtime->dma_area + prev_appl_offset; + memmove(pdma + 1, pdma, appl_count - 1); + } + prtd->appl_ptr_bytes = appl_ptr_bytes; + } + mxs_dma_ack_irq(prtd->dma_ch); + snd_pcm_period_elapsed(substream); + } + return IRQ_HANDLED; +} + +/* + * Make a circular DMA descriptor list + */ +static int mxs_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxs_runtime_data *prtd = runtime->private_data; + dma_addr_t dma_buffer_phys; + int periods_num, playback, i; + + playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + periods_num = prtd->dma_totsize / prtd->dma_period; + + dma_buffer_phys = runtime->dma_addr; + + /* Reset DMA channel, enable interrupt */ + mxs_dma_reset(prtd->dma_ch); + + /* Set up a DMA chain to sent DMA buffer */ + for (i = 0; i < periods_num; i++) { + int ret; + /* Link with previous command */ + prtd->dma_desc_array[i]->cmd.cmd.bits.bytes = prtd->dma_period; + prtd->dma_desc_array[i]->cmd.cmd.bits.irq = 1; + prtd->dma_desc_array[i]->cmd.cmd.bits.dec_sem = 0; + prtd->dma_desc_array[i]->cmd.cmd.bits.chain = 1; + /* Set DMA direction */ + if (playback) + prtd->dma_desc_array[i]->cmd.cmd.bits.command = \ + DMA_READ; + else + prtd->dma_desc_array[i]->cmd.cmd.bits.command = \ + DMA_WRITE; + + prtd->dma_desc_array[i]->cmd.address = dma_buffer_phys; + + ret = mxs_dma_desc_append(prtd->dma_ch, \ + prtd->dma_desc_array[i]); + if (ret) { + printk(KERN_ERR "%s: Failed to append DMA descriptor\n", + __func__); + return ret; + } + /* Next data chunk */ + dma_buffer_phys += prtd->dma_period; + } + + return 0; +} + +/* + * Stop circular DMA descriptor list + * We should not stop DMA in a middle of current transaction once we receive + * stop request from ALSA core. This function finds the next DMA descriptor + * and set it up to decrement DMA channel semaphore. So the current transaction + * is the last data transfer. + */ +static void mxs_pcm_stop(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxs_runtime_data *prtd = runtime->private_data; + struct mxs_dma_info dma_info; + int desc; + + int periods_num = prtd->dma_totsize / prtd->dma_period; + /* Freez DMA channel for a moment */ + mxs_dma_freeze(prtd->dma_ch); + mxs_dma_get_info(prtd->dma_ch, &dma_info); + + desc = (dma_info.buf_addr - runtime->dma_addr) / prtd->dma_period; + + if (desc >= periods_num) + desc = 0; + else if (desc < 0) + desc = 0; + + /* Set up the next descriptor to decrement DMA channel sempahore */ + prtd->dma_desc_array[(desc + 1)%periods_num]->cmd.cmd.bits.bytes = 0; + prtd->dma_desc_array[(desc + 1)%periods_num]->cmd.cmd.bits.pio_words = \ + 0; + prtd->dma_desc_array[(desc + 1)%periods_num]->cmd.cmd.bits.dec_sem = 1; + prtd->dma_desc_array[(desc + 1)%periods_num]->cmd.cmd.bits.irq = 0; + prtd->dma_desc_array[(desc + 1)%periods_num]->cmd.cmd.bits.command = \ + NO_DMA_XFER; + + mxs_dma_unfreeze(prtd->dma_ch); + + mxs_dma_disable(prtd->dma_ch); +} + +static int mxs_pcm_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxs_runtime_data *prtd = substream->runtime->private_data; + int ret = 0; + switch (cmd) { + + case SNDRV_PCM_TRIGGER_START: + if ((prtd->params->dma_ch == MXS_DMA_CHANNEL_AHB_APBX_SPDIF) && + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) && + (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) && + ((prtd->format == SNDRV_PCM_FORMAT_S24_LE) + || (prtd->format == SNDRV_PCM_FORMAT_S20_3LE))) { + prtd->appl_ptr_bytes = + frames_to_bytes(runtime, + runtime->control->appl_ptr); + memmove(runtime->dma_area + 1, runtime->dma_area, + prtd->appl_ptr_bytes - 1); + } + mxs_dma_enable(prtd->dma_ch); + break; + + case SNDRV_PCM_TRIGGER_STOP: + mxs_pcm_stop(substream); + break; + + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + mxs_dma_unfreeze(prtd->dma_ch); + break; + + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + mxs_dma_freeze(prtd->dma_ch); + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static snd_pcm_uframes_t +mxs_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxs_runtime_data *prtd = runtime->private_data; + struct mxs_dma_info dma_info; + unsigned int offset; + dma_addr_t pos; + + mxs_dma_get_info(prtd->params->dma_ch, &dma_info); + pos = dma_info.buf_addr; + + offset = bytes_to_frames(runtime, pos - runtime->dma_addr); + + if (offset >= runtime->buffer_size) + offset = 0; + + return offset; +} + +static int mxs_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + struct mxs_runtime_data *prtd = substream->runtime->private_data; + + prtd->dma_period = params_period_bytes(hw_params); + prtd->dma_totsize = params_buffer_bytes(hw_params); + prtd->format = params_format(hw_params); + + return snd_pcm_lib_malloc_pages(substream, + params_buffer_bytes(hw_params)); +} + +static int mxs_pcm_hw_free(struct snd_pcm_substream *substream) +{ + return snd_pcm_lib_free_pages(substream); +} + +static int mxs_pcm_dma_request(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mxs_runtime_data *prtd = runtime->private_data; + struct mxs_pcm_dma_params *dma_data = + snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream); + int desc_num = mxs_pcm_hardware.periods_max; + int desc; + int ret; + + if (!dma_data) + return -ENODEV; + + prtd->params = dma_data; + prtd->dma_ch = dma_data->dma_ch; + + ret = mxs_dma_request(prtd->dma_ch, mxs_pcm_dev, + prtd->params->name); + if (ret) { + printk(KERN_ERR "%s: Failed to request DMA channel (%d:%d)\n", + __func__, dma_data->dma_bus, dma_data->dma_ch); + return ret; + } + + /* Allocate memory for data and pio DMA descriptors */ + for (desc = 0; desc < desc_num; desc++) { + prtd->dma_desc_array[desc] = mxs_dma_alloc_desc(); + if (prtd->dma_desc_array[desc] == NULL) { + printk(KERN_ERR"%s Unable to allocate DMA command %d\n", + __func__, desc); + goto err; + } + } + + ret = request_irq(prtd->params->irq, mxs_pcm_dma_irq, 0, + "MXS PCM DMA", substream); + if (ret) { + printk(KERN_ERR "%s: Unable to request DMA irq %d\n", __func__, + prtd->params->irq); + goto err; + } + /* Enable completion interrupt */ + mxs_dma_ack_irq(prtd->dma_ch); + mxs_dma_enable_irq(prtd->dma_ch, 1); + + return 0; + +err: + while (--desc >= 0) + mxs_dma_free_desc(prtd->dma_desc_array[desc]); + mxs_dma_release(prtd->dma_ch, mxs_pcm_dev); + + return ret; +} + +static int mxs_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxs_runtime_data *prtd; + int ret; + + /* Ensure that buffer size is a multiple of the period size */ + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) + return ret; + + snd_soc_set_runtime_hwparams(substream, &mxs_pcm_hardware); + + prtd = kzalloc(sizeof(struct mxs_runtime_data), GFP_KERNEL); + if (prtd == NULL) + return -ENOMEM; + + runtime->private_data = prtd; + + ret = mxs_pcm_dma_request(substream); + if (ret) { + printk(KERN_ERR "mxs_pcm: Failed to request channels\n"); + kfree(prtd); + return ret; + } + return 0; +} + +static int mxs_pcm_close(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxs_runtime_data *prtd = runtime->private_data; + int desc_num = mxs_pcm_hardware.periods_max; + int desc; + + static LIST_HEAD(list); + mxs_dma_disable(prtd->dma_ch); + /* Free DMA irq */ + free_irq(prtd->params->irq, substream); + mxs_dma_get_cooked(prtd->dma_ch, &list); + /* Free DMA channel*/ + mxs_dma_reset(prtd->dma_ch); + for (desc = 0; desc < desc_num; desc++) + mxs_dma_free_desc(prtd->dma_desc_array[desc]); + mxs_dma_release(prtd->dma_ch, mxs_pcm_dev); + + /* Free private runtime data */ + kfree(prtd); + return 0; +} + +static int mcs_pcm_copy(struct snd_pcm_substream *substream, int channel, + snd_pcm_uframes_t hwoff, void __user *buf, + snd_pcm_uframes_t frames) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct mxs_runtime_data *prtd = runtime->private_data; + char *hwbuf = runtime->dma_area + frames_to_bytes(runtime, hwoff); + unsigned long count = frames_to_bytes(runtime, frames); + + /* For S/PDIF 24-bit playback, fix the buffer. Code taken from + snd_pcm_lib_write_transfer() and snd_pcm_lib_read_transfer() + in sound/core/pcm_lib.c */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + if ((prtd->params->dma_ch == MXS_DMA_CHANNEL_AHB_APBX_SPDIF) && + ((prtd->format == SNDRV_PCM_FORMAT_S24_LE) + || (prtd->format == SNDRV_PCM_FORMAT_S20_3LE))) { + if (copy_from_user(hwbuf + 1, buf, count - 1)) + return -EFAULT; + } else { + if (copy_from_user(hwbuf, buf, count)) + return -EFAULT; + } + } else { + if (copy_to_user(buf, hwbuf, count)) + return -EFAULT; + } + + return 0; +} + +static int mxs_pcm_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *vma) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + return dma_mmap_coherent(NULL, vma, runtime->dma_area, + runtime->dma_addr, runtime->dma_bytes); +} + +struct snd_pcm_ops mxs_pcm_ops = { + .open = mxs_pcm_open, + .close = mxs_pcm_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = mxs_pcm_hw_params, + .hw_free = mxs_pcm_hw_free, + .prepare = mxs_pcm_prepare, + .trigger = mxs_pcm_trigger, + .pointer = mxs_pcm_pointer, + .copy = mcs_pcm_copy, + .mmap = mxs_pcm_mmap, +}; + +static u64 mxs_pcm_dma_mask = DMA_BIT_MASK(32); + +static int mxs_pcm_new(struct snd_card *card, + struct snd_soc_dai *dai, struct snd_pcm *pcm) +{ + size_t size = mxs_pcm_hardware.buffer_bytes_max; + + if (!card->dev->dma_mask) + card->dev->dma_mask = &mxs_pcm_dma_mask; + + if (!card->dev->coherent_dma_mask) + card->dev->coherent_dma_mask = DMA_BIT_MASK(32); + + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, NULL, + size, size); + + return 0; +} + +static void mxs_pcm_free(struct snd_pcm *pcm) +{ + snd_pcm_lib_preallocate_free_for_all(pcm); +} + +/* + * We need probe/remove callbacks to setup mxs_pcm_dev + */ +static int mxs_pcm_probe(struct platform_device *pdev) +{ + mxs_pcm_dev = &pdev->dev; + return 0; +} + +static int mxs_pcm_remove(struct platform_device *pdev) +{ + mxs_pcm_dev = NULL; + return 0; +} + +struct snd_soc_platform mxs_soc_platform = { + .name = "MXS Audio", + .pcm_ops = &mxs_pcm_ops, + .probe = mxs_pcm_probe, + .remove = mxs_pcm_remove, + .pcm_new = mxs_pcm_new, + .pcm_free = mxs_pcm_free, +}; +EXPORT_SYMBOL_GPL(mxs_soc_platform); + +static int __init mxs_pcm_init(void) +{ + return snd_soc_register_platform(&mxs_soc_platform); +} + +static void __exit mxs_pcm_exit(void) +{ + snd_soc_unregister_platform(&mxs_soc_platform); +} +module_init(mxs_pcm_init); +module_exit(mxs_pcm_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXS DMA Module"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/mxs/mxs-pcm.h b/sound/soc/mxs/mxs-pcm.h new file mode 100644 index 000000000000..738e3fd82d73 --- /dev/null +++ b/sound/soc/mxs/mxs-pcm.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _MXS_PCM_H +#define _MXS_PCM_H + +struct mxs_pcm_dma_params { + char *name; + int dma_bus; /* DMA bus */ + int dma_ch; /* DMA channel number */ + int irq; /* DMA interrupt number */ +}; +struct mxs_runtime_data { + u32 dma_ch; + u32 dma_period; + u32 dma_totsize; + unsigned long appl_ptr_bytes; + int format; + struct mxs_pcm_dma_params *params; + struct mxs_dma_desc *dma_desc_array[255]; +}; + +extern struct snd_soc_platform mxs_soc_platform; + +#endif diff --git a/sound/soc/mxs/mxs-spdif-dai.c b/sound/soc/mxs/mxs-spdif-dai.c new file mode 100644 index 000000000000..1b45b595b90d --- /dev/null +++ b/sound/soc/mxs/mxs-spdif-dai.c @@ -0,0 +1,203 @@ +/* + * ALSA SoC SPDIF Audio Layer for MXS + * + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. + * + * Based on stmp3xxx_spdif_dai.c + * Vladimir Barinov + * Copyright 2008 SigmaTel, Inc + * Copyright 2008 Embedded Alley Solutions, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../codecs/mxs_spdif.h" +#include "mxs-pcm.h" + +#define REGS_SPDIF_BASE IO_ADDRESS(SPDIF_PHYS_ADDR) + +struct mxs_pcm_dma_params mxs_spdif = { + .name = "mxs spdif", + .dma_ch = MXS_DMA_CHANNEL_AHB_APBX_SPDIF, + .irq = IRQ_SPDIF_DMA, +}; + +static irqreturn_t mxs_err_irq(int irq, void *dev_id) +{ + struct snd_pcm_substream *substream = dev_id; + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + u32 ctrl_reg = 0; + u32 overflow_mask; + u32 underflow_mask; + + if (playback) { + ctrl_reg = __raw_readl(REGS_SPDIF_BASE + HW_SPDIF_CTRL); + underflow_mask = BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ; + overflow_mask = BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ; + } + + if (ctrl_reg & underflow_mask) { + printk(KERN_DEBUG "underflow detected SPDIF\n"); + + if (playback) + __raw_writel(BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + } else if (ctrl_reg & overflow_mask) { + printk(KERN_DEBUG "overflow detected SPDIF\n"); + + if (playback) + __raw_writel(BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + } else + printk(KERN_WARNING "Unknown SPDIF error interrupt\n"); + + return IRQ_HANDLED; +} + +static int mxs_spdif_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) +{ + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (playback) + __raw_writel(BM_SPDIF_CTRL_RUN, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET); + break; + case SNDRV_PCM_TRIGGER_STOP: + if (playback) + __raw_writel(BM_SPDIF_CTRL_RUN, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + break; + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + + default: + ret = -EINVAL; + } + + return ret; +} + +static int mxs_spdif_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + int irq; + int ret; + + if (playback) { + irq = IRQ_SPDIF_ERROR; + snd_soc_dai_set_dma_data(cpu_dai, substream, &mxs_spdif); + } + + ret = request_irq(irq, mxs_err_irq, 0, "Mxs SPDIF Error", + substream); + if (ret) { + printk(KERN_ERR "%s: Unable to request SPDIF error irq %d\n", + __func__, IRQ_SPDIF_ERROR); + return ret; + } + + /* Enable error interrupt */ + if (playback) { + __raw_writel(BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + __raw_writel(BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + __raw_writel(BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET); + } + + return 0; +} + +static void mxs_spdif_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; + + /* Disable error interrupt */ + if (playback) { + __raw_writel(BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN, + REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR); + free_irq(IRQ_SPDIF_ERROR, substream); + } +} + +#ifdef CONFIG_PM +static int mxs_spdif_suspend(struct snd_soc_dai *cpu_dai) +{ + return 0; +} + +static int mxs_spdif_resume(struct snd_soc_dai *cpu_dai) +{ + return 0; +} +#else +#define mxs_spdif_suspend NULL +#define mxs_spdif_resume NULL +#endif /* CONFIG_PM */ + +struct snd_soc_dai_ops mxs_spdif_dai_ops = { + .startup = mxs_spdif_startup, + .shutdown = mxs_spdif_shutdown, + .trigger = mxs_spdif_trigger, +}; + +struct snd_soc_dai mxs_spdif_dai = { + .name = "mxs-spdif", + .id = 0, + .suspend = mxs_spdif_suspend, + .resume = mxs_spdif_resume, + .playback = { + .channels_min = 2, + .channels_max = 2, + .rates = MXS_SPDIF_RATES, + .formats = MXS_SPDIF_FORMATS, + }, + .capture = { + .channels_min = 2, + .channels_max = 2, + .rates = MXS_SPDIF_RATES, + .formats = MXS_SPDIF_FORMATS, + }, + .ops = &mxs_spdif_dai_ops, +}; +EXPORT_SYMBOL_GPL(mxs_spdif_dai); + +static int __init mxs_spdif_dai_init(void) +{ + return snd_soc_register_dai(&mxs_spdif_dai); +} + +static void __exit mxs_spdif_dai_exit(void) +{ + snd_soc_unregister_dai(&mxs_spdif_dai); +} +module_init(mxs_spdif_dai_init); +module_exit(mxs_spdif_dai_exit); + +MODULE_AUTHOR("Vladimir Barinov"); +MODULE_DESCRIPTION("MXS SPDIF DAI"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/mxs/mxs-spdif-dai.h b/sound/soc/mxs/mxs-spdif-dai.h new file mode 100644 index 000000000000..035369af9676 --- /dev/null +++ b/sound/soc/mxs/mxs-spdif-dai.h @@ -0,0 +1,21 @@ +/* + * ASoC Audio Layer for Freescale STMP3XXX SPDIF transmitter + * + * Author: Vladimir Barinov + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef _STMP3XXX_SPDIF_H +#define _STMP3XXX_SPDIF_H +extern struct snd_soc_dai mxs_spdif_dai; +#endif -- cgit v1.2.3